From c11f5bb2510c9c961819c554c1e4cc69f7f52ab7 Mon Sep 17 00:00:00 2001 From: flyingcys Date: Sun, 19 Mar 2023 14:41:18 +0800 Subject: [PATCH] add bl60x/bl70x/bl61x/bl808 (#7063) Co-authored-by: flyingcys --- bsp/bl808/README.md | 128 - bsp/bl808/figures/program.jpg | Bin 139945 -> 0 bytes bsp/bl808/m0/drivers/Kconfig | 63 - bsp/bl808/m0/drivers/SConscript | 53 - bsp/bl808/m0/drivers/board.c | 115 - bsp/bl808/m0/drivers/board.h | 35 - bsp/bl808/m0/drivers/drv_gpio.c | 208 - bsp/bl808/m0/drivers/drv_gpio.h | 39 - bsp/bl808/m0/drivers/drv_i2c.c | 186 - bsp/bl808/m0/drivers/drv_i2c.h | 43 - bsp/bl808/m0/drivers/drv_uart.c | 318 - bsp/bl808/m0/libraries/SConscript | 103 - .../platform/hosal/adapter/hosal_adapter.h | 38 - .../hosal/adapter/hosal_adpt_iotsdk.c | 45 - .../platform/hosal/bl808_e907_hal/bl_audio.c | 545 - .../platform/hosal/bl808_e907_hal/bl_audio.h | 120 - .../platform/hosal/bl808_e907_hal/bl_boot2.c | 145 - .../platform/hosal/bl808_e907_hal/bl_boot2.h | 197 - .../platform/hosal/bl808_e907_hal/bl_cam.c | 79 - .../platform/hosal/bl808_e907_hal/bl_cam.h | 35 - .../platform/hosal/bl808_e907_hal/bl_chip.c | 188 - .../platform/hosal/bl808_e907_hal/bl_chip.h | 35 - .../platform/hosal/bl808_e907_hal/bl_efuse.c | 127 - .../platform/hosal/bl808_e907_hal/bl_efuse.h | 40 - .../hosal/bl808_e907_hal/bl_ethernetif.c | 746 -- .../hosal/bl808_e907_hal/bl_ethernetif.h | 76 - .../platform/hosal/bl808_e907_hal/bl_flash.c | 184 - .../platform/hosal/bl808_e907_hal/bl_flash.h | 42 - .../platform/hosal/bl808_e907_hal/bl_ipc.c | 73 - .../platform/hosal/bl808_e907_hal/bl_ipc.h | 37 - .../platform/hosal/bl808_e907_hal/bl_irq.c | 418 - .../platform/hosal/bl808_e907_hal/bl_irq.h | 74 - .../hosal/bl808_e907_hal/bl_mm_clock.c | 272 - .../hosal/bl808_e907_hal/bl_mm_clock.h | 86 - .../platform/hosal/bl808_e907_hal/bl_pm.c | 489 - .../platform/hosal/bl808_e907_hal/bl_pm.h | 111 - .../platform/hosal/bl808_e907_hal/bl_psram.c | 51 - .../platform/hosal/bl808_e907_hal/bl_psram.h | 34 - .../platform/hosal/bl808_e907_hal/bl_sdh.c | 1715 --- .../platform/hosal/bl808_e907_hal/bl_sdh.h | 516 - .../platform/hosal/bl808_e907_hal/bl_sec.c | 797 -- .../platform/hosal/bl808_e907_hal/bl_sec.h | 85 - .../hosal/bl808_e907_hal/bl_sec_sha.c | 180 - .../platform/hosal/bl808_e907_hal/bl_sys.c | 325 - .../platform/hosal/bl808_e907_hal/bl_sys.h | 61 - .../platform/hosal/bl808_e907_hal/bl_timer.c | 132 - .../platform/hosal/bl808_e907_hal/bl_timer.h | 35 - .../platform/hosal/bl808_e907_hal/bl_uart.c | 552 - .../platform/hosal/bl808_e907_hal/bl_uart.h | 62 - .../hosal/bl808_e907_hal/bl_usb_cam.c | 322 - .../hosal/bl808_e907_hal/bl_usb_cam.h | 35 - .../platform/hosal/bl808_e907_hal/bl_wifi.c | 255 - .../platform/hosal/bl808_e907_hal/bl_wifi.h | 52 - .../platform/hosal/bl808_e907_hal/emac_phy.c | 30 - .../hosal/bl808_e907_hal/ethernet_phy.h | 49 - .../hosal/bl808_e907_hal/ethernetif.c | 574 - .../hosal/bl808_e907_hal/ethernetif.h | 49 - .../platform/hosal/bl808_e907_hal/hal_board.c | 1273 -- .../platform/hosal/bl808_e907_hal/hal_board.h | 34 - .../platform/hosal/bl808_e907_hal/hal_boot2.c | 314 - .../platform/hosal/bl808_e907_hal/hal_boot2.h | 87 - .../hosal/bl808_e907_hal/hal_common.h | 50 - .../platform/hosal/bl808_e907_hal/hal_emac.c | 666 - .../platform/hosal/bl808_e907_hal/hal_emac.h | 127 - .../platform/hosal/bl808_e907_hal/hal_sdh.c | 91 - .../platform/hosal/bl808_e907_hal/hal_sdh.h | 33 - .../platform/hosal/bl808_e907_hal/hal_sys.c | 139 - .../platform/hosal/bl808_e907_hal/hal_sys.h | 67 - .../platform/hosal/bl808_e907_hal/hal_uart.c | 284 - .../platform/hosal/bl808_e907_hal/hal_uart.h | 35 - .../platform/hosal/bl808_e907_hal/hal_usb.c | 1285 -- .../platform/hosal/bl808_e907_hal/hal_usb.h | 158 - .../platform/hosal/bl808_e907_hal/hal_wifi.c | 51 - .../platform/hosal/bl808_e907_hal/hal_wifi.h | 33 - .../platform/hosal/bl808_e907_hal/hosal_adc.c | 527 - .../platform/hosal/bl808_e907_hal/hosal_dma.c | 314 - .../platform/hosal/bl808_e907_hal/hosal_pwm.c | 267 - .../platform/hosal/bl808_e907_hal/hosal_spi.c | 275 - .../hosal/bl808_e907_hal/hosal_uart.c | 557 - .../platform/hosal/bl808_e907_hal/phy_8720.c | 419 - .../platform/hosal/include/hosal_adc.h | 238 - .../platform/hosal/include/hosal_dac.h | 187 - .../platform/hosal/include/hosal_dma.h | 152 - .../platform/hosal/include/hosal_efuse.h | 70 - .../platform/hosal/include/hosal_flash.h | 229 - .../platform/hosal/include/hosal_gpio.h | 186 - .../platform/hosal/include/hosal_i2c.h | 212 - .../platform/hosal/include/hosal_pwm.h | 175 - .../platform/hosal/include/hosal_rng.h | 74 - .../platform/hosal/include/hosal_rtc.h | 146 - .../platform/hosal/include/hosal_spi.h | 178 - .../platform/hosal/include/hosal_timer.h | 118 - .../platform/hosal/include/hosal_uart.h | 356 - .../platform/hosal/include/hosal_wdg.h | 99 - .../platform_hal/platform_hal_device.cpp | 251 - .../hosal/platform_hal/platform_hal_device.h | 109 - .../platform/hosal/sec_common/bl_sec_aes.c | 231 - .../platform/hosal/sec_common/bl_sec_aes.h | 79 - .../platform/hosal/sec_common/bl_sec_common.c | 62 - .../platform/hosal/sec_common/bl_sec_common.h | 88 - .../hosal/sec_common/bl_sec_hw_common.h | 57 - .../platform/hosal/sec_common/bl_sec_pka.c | 71 - .../platform/hosal/sec_common/bl_sec_pka.h | 37 - .../platform/hosal/sec_common/bl_sec_sha.c | 465 - .../bl808_e907_std/bflb_bsp_driver_glue.h | 53 - .../soc/bl808/bl808_e907_std/bflb_stub.c | 160 - .../soc/bl808/bl808_e907_std/bflb_stub.h | 54 - .../bl808_bsp_driver/.gitignore | 3 - .../bl808_bsp_driver/blsp_boot2_iap_flash.ld | 264 - .../bl808_bsp_driver/cpu_flags.cmake | 3 - .../hal_drv/default_config/adc_config.h | 17 - .../hal_drv/default_config/dac_config.h | 14 - .../hal_drv/default_config/i2s_config.h | 11 - .../hal_drv/default_config/uart_config.h | 17 - .../bl808_bsp_driver/hal_drv/inc/hal_adc.h | 176 - .../bl808_bsp_driver/hal_drv/inc/hal_audio.h | 261 - .../bl808_bsp_driver/hal_drv/inc/hal_boot2.h | 323 - .../bl808_bsp_driver/hal_drv/inc/hal_clock.h | 72 - .../bl808_bsp_driver/hal_drv/inc/hal_common.h | 49 - .../bl808_bsp_driver/hal_drv/inc/hal_dac.h | 72 - .../bl808_bsp_driver/hal_drv/inc/hal_dma.h | 262 - .../bl808_bsp_driver/hal_drv/inc/hal_dsi.h | 574 - .../bl808_bsp_driver/hal_drv/inc/hal_emac.h | 107 - .../bl808_bsp_driver/hal_drv/inc/hal_flash.h | 42 - .../bl808_bsp_driver/hal_drv/inc/hal_gpio.h | 103 - .../bl808_bsp_driver/hal_drv/inc/hal_i2c.h | 77 - .../bl808_bsp_driver/hal_drv/inc/hal_i2s.h | 117 - .../bl808_bsp_driver/hal_drv/inc/hal_mtimer.h | 43 - .../bl808_bsp_driver/hal_drv/inc/hal_pm.h | 92 - .../bl808_bsp_driver/hal_drv/inc/hal_pwm.h | 117 - .../bl808_bsp_driver/hal_drv/inc/hal_rtc.h | 38 - .../hal_drv/inc/hal_sec_aes.h | 57 - .../hal_drv/inc/hal_sec_dsa.h | 57 - .../hal_drv/inc/hal_sec_ecdsa.h | 62 - .../hal_drv/inc/hal_sec_hash.h | 64 - .../bl808_bsp_driver/hal_drv/inc/hal_spi.h | 129 - .../hal_drv/inc/hal_spi_flash.h | 35 - .../bl808_bsp_driver/hal_drv/inc/hal_timer.h | 94 - .../bl808_bsp_driver/hal_drv/inc/hal_uart.h | 131 - .../bl808_bsp_driver/hal_drv/inc/hal_usb.h | 151 - .../hal_drv/inc/mipi_display.h | 187 - .../bl808_bsp_driver/hal_drv/src/hal_adc.c | 383 - .../bl808_bsp_driver/hal_drv/src/hal_boot2.c | 602 - .../bl808_bsp_driver/hal_drv/src/hal_clock.c | 305 - .../bl808_bsp_driver/hal_drv/src/hal_common.c | 141 - .../bl808_bsp_driver/hal_drv/src/hal_dac.c | 324 - .../bl808_bsp_driver/hal_drv/src/hal_dma.c | 562 - .../bl808_bsp_driver/hal_drv/src/hal_dsi.c | 932 -- .../bl808_bsp_driver/hal_drv/src/hal_emac.c | 584 - .../bl808_bsp_driver/hal_drv/src/hal_flash.c | 352 - .../bl808_bsp_driver/hal_drv/src/hal_gpio.c | 227 - .../bl808_bsp_driver/hal_drv/src/hal_i2c.c | 131 - .../bl808_bsp_driver/hal_drv/src/hal_i2s.c | 352 - .../bl808_bsp_driver/hal_drv/src/hal_mtimer.c | 139 - .../bl808_bsp_driver/hal_drv/src/hal_pm.c | 855 -- .../bl808_bsp_driver/hal_drv/src/hal_pwm.c | 205 - .../bl808_bsp_driver/hal_drv/src/hal_rtc.c | 102 - .../hal_drv/src/hal_sec_aes.c | 125 - .../hal_drv/src/hal_sec_dsa.c | 389 - .../hal_drv/src/hal_sec_ecdsa.c | 1458 --- .../hal_drv/src/hal_sec_hash.c | 387 - .../bl808_bsp_driver/hal_drv/src/hal_spi.c | 494 - .../hal_drv/src/hal_spi_flash.c | 589 - .../bl808_bsp_driver/hal_drv/src/hal_uart.c | 528 - .../bl808_bsp_driver/hal_drv/src/hal_usb.c | 1291 -- .../bl808_bsp_driver/regs/audio_reg.h | 6651 ---------- .../bl808_bsp_driver/regs/cam_reg.h | 689 - .../bl808_bsp_driver/regs/can_reg.h | 807 -- .../bl808_bsp_driver/regs/cnn_reg.h | 241 - .../bl808_bsp_driver/regs/csi_reg.h | 528 - .../bl808_bsp_driver/regs/dbi_reg.h | 423 - .../bl808_bsp_driver/regs/dma2d_reg.h | 574 - .../bl808_bsp_driver/regs/dma_reg.h | 2084 --- .../bl808_bsp_driver/regs/dsi_reg.h | 1231 -- .../bl808_bsp_driver/regs/dsp2_auto_reg.h | 201 - .../bl808_bsp_driver/regs/dsp2_axi_ctrl_reg.h | 336 - .../bl808_bsp_driver/regs/dsp2_back_reg.h | 574 - .../bl808_bsp_driver/regs/dsp2_blae_reg.h | 95 - .../bl808_bsp_driver/regs/dsp2_blawb_reg.h | 95 - .../bl808_bsp_driver/regs/dsp2_blback_reg.h | 8061 ------------ .../bl808_bsp_driver/regs/dsp2_front_reg.h | 346 - .../bl808_bsp_driver/regs/dsp2_gamma_reg.h | 2288 ---- .../bl808_bsp_driver/regs/dsp2_middle2_reg.h | 1115 -- .../bl808_bsp_driver/regs/dsp2_middle3_reg.h | 928 -- .../bl808_bsp_driver/regs/dsp2_middle4_reg.h | 167 - .../bl808_bsp_driver/regs/dsp2_middle5_reg.h | 2589 ---- .../bl808_bsp_driver/regs/dsp2_middle_reg.h | 1278 -- .../bl808_bsp_driver/regs/dsp2_misc_reg.h | 4491 ------- .../bl808_bsp_driver/regs/dsp2_tg_reg.h | 423 - .../bl808_bsp_driver/regs/dtsrc_reg.h | 505 - .../bl808_bsp_driver/regs/emac_reg.h | 583 - .../bl808_bsp_driver/regs/emi_misc_reg.h | 121 - .../bl808_bsp_driver/regs/i2c_reg.h | 550 - .../bl808_bsp_driver/regs/i2s_reg.h | 441 - .../bl808_bsp_driver/regs/ir_reg.h | 646 - .../bl808_bsp_driver/regs/iso11898_reg.h | 807 -- .../bl808_bsp_driver/regs/lz4_reg.h | 276 - .../bl808_bsp_driver/regs/mjdec_reg.h | 652 - .../bl808_bsp_driver/regs/mjpeg_q_reg.h | 1584 --- .../bl808_bsp_driver/regs/mjpeg_reg.h | 1098 -- .../bl808_bsp_driver/regs/osd_blend_reg.h | 500 - .../bl808_bsp_driver/regs/osd_draw_h_reg.h | 1382 -- .../bl808_bsp_driver/regs/osd_draw_l_reg.h | 1511 --- .../bl808_bsp_driver/regs/osd_draw_reg.h | 1511 --- .../bl808_bsp_driver/regs/osd_pb_reg.h | 878 -- .../bl808_bsp_driver/regs/osd_probe_reg.h | 913 -- .../bl808_bsp_driver/regs/pdm_reg.h | 722 -- .../bl808_bsp_driver/regs/pwm_reg.h | 1502 --- .../bl808_bsp_driver/regs/sec_dbg_reg.h | 209 - .../bl808_bsp_driver/regs/sec_eng_reg.h | 1966 --- .../bl808_bsp_driver/regs/spi_reg.h | 535 - .../bl808_bsp_driver/regs/timer_reg.h | 963 -- .../bl808_bsp_driver/regs/uart_reg.h | 978 -- .../bl808_bsp_driver/regs/usb_reg.h | 5352 -------- .../risc-v/Core/Include/clic.h | 21 - .../risc-v/Core/Include/riscv_bits.h | 36 - .../risc-v/Core/Include/riscv_const.h | 18 - .../risc-v/Core/Include/riscv_encoding.h | 1363 -- .../bl808_bsp_driver/risc-v/rv_pmp.h | 73 - .../startup/d0/bl808_ram_dv.ld | 195 - .../startup/d0/cpu_flags.cmake | 18 - .../startup/d0/source/interrupt.c | 218 - .../startup/d0/source/system_bl808.c | 105 - .../startup/d0/source/system_bl808.h | 23 - .../startup/lp/bl808_flash.ld | 264 - .../bl808_bsp_driver/startup/lp/bl808_ram.ld | 191 - .../startup/lp/bl808_ram_dv.ld | 195 - .../startup/lp/cpu_flags.cmake | 22 - .../startup/lp/source/interrupt.c | 361 - .../startup/lp/source/irq_ctx.h | 172 - .../startup/lp/source/system_bl808.c | 84 - .../startup/lp/source/system_bl808.h | 20 - .../startup/m0/bl808_flash_dv.ld | 213 - .../bl808_bsp_driver/startup/m0/bl808_ram.ld | 221 - .../startup/m0/bl808_ram_dv.ld | 195 - .../bl808_bsp_driver/startup/m0/bl808_rom.ld | 195 - .../startup/m0/cpu_flags.cmake | 20 - .../startup/m0/source/GCC/startup.S | 168 - .../startup/m0/source/interrupt.c | 343 - .../startup/m0/source/system_bl808.h | 20 - .../bl808_bsp_driver/std_drv/inc/bl808_adc.h | 550 - .../std_drv/inc/bl808_audio.h | 971 -- .../std_drv/inc/bl808_aupdm.h | 267 - .../bl808_bsp_driver/std_drv/inc/bl808_cam.h | 349 - .../bl808_bsp_driver/std_drv/inc/bl808_can.h | 244 - .../std_drv/inc/bl808_common.h | 56 - .../bl808_bsp_driver/std_drv/inc/bl808_dac.h | 290 - .../bl808_bsp_driver/std_drv/inc/bl808_dbi.h | 294 - .../bl808_bsp_driver/std_drv/inc/bl808_dma.h | 439 - .../std_drv/inc/bl808_dma2d.h | 492 - .../bl808_bsp_driver/std_drv/inc/bl808_dsi.h | 382 - .../bl808_bsp_driver/std_drv/inc/bl808_dsp2.h | 689 - .../std_drv/inc/bl808_dsp2_axi_ctrl.h | 174 - .../std_drv/inc/bl808_dsp2_misc.h | 722 -- .../std_drv/inc/bl808_dsp2_wdr.h | 121 - .../std_drv/inc/bl808_dvp_tsrc.h | 255 - .../std_drv/inc/bl808_ef_cfg.h | 238 - .../bl808_bsp_driver/std_drv/inc/bl808_emac.h | 360 - .../bl808_bsp_driver/std_drv/inc/bl808_i2c.h | 210 - .../bl808_bsp_driver/std_drv/inc/bl808_i2s.h | 309 - .../bl808_bsp_driver/std_drv/inc/bl808_ir.h | 289 - .../std_drv/inc/bl808_iso11898.h | 242 - .../std_drv/inc/bl808_mfg_efuse.h | 25 - .../std_drv/inc/bl808_mfg_flash.h | 30 - .../std_drv/inc/bl808_mfg_media.h | 35 - .../std_drv/inc/bl808_mjdec.h | 175 - .../std_drv/inc/bl808_mjpeg.h | 259 - .../std_drv/inc/bl808_osd_blend.h | 212 - .../std_drv/inc/bl808_osd_draw.h | 212 - .../bl808_bsp_driver/std_drv/inc/bl808_pwm.h | 356 - .../std_drv/inc/bl808_sec_eng.h | 778 -- .../std_drv/inc/bl808_sf_cfg.h | 106 - .../std_drv/inc/bl808_sf_ctrl.h | 470 - .../bl808_bsp_driver/std_drv/inc/bl808_spi.h | 321 - .../std_drv/inc/bl808_timer.h | 312 - .../std_drv/inc/bl808_touch.h | 480 - .../bl808_bsp_driver/std_drv/inc/bl808_uart.h | 359 - .../std_drv/inc/bl808_uhs_phy.h | 46 - .../bl808_bsp_driver/std_drv/inc/bl808_usb.h | 643 - .../std_drv/src/bl808_acomp.c | 209 - .../bl808_bsp_driver/std_drv/src/bl808_adc.c | 1487 --- .../std_drv/src/bl808_audio.c | 2814 ----- .../std_drv/src/bl808_aupdm.c | 777 -- .../bl808_bsp_driver/std_drv/src/bl808_cam.c | 979 -- .../bl808_bsp_driver/std_drv/src/bl808_can.c | 671 - .../bl808_bsp_driver/std_drv/src/bl808_dac.c | 518 - .../bl808_bsp_driver/std_drv/src/bl808_dbi.c | 802 -- .../bl808_bsp_driver/std_drv/src/bl808_dma.c | 1060 -- .../std_drv/src/bl808_dma2d.c | 1228 -- .../bl808_bsp_driver/std_drv/src/bl808_dsi.c | 1500 --- .../bl808_bsp_driver/std_drv/src/bl808_dsp2.c | 2029 --- .../std_drv/src/bl808_dsp2_axi_ctrl.c | 234 - .../std_drv/src/bl808_dsp2_misc.c | 1575 --- .../std_drv/src/bl808_dsp2_wdr.c | 557 - .../std_drv/src/bl808_dvp_tsrc.c | 394 - .../std_drv/src/bl808_ef_cfg.c | 610 - .../std_drv/src/bl808_ef_ctrl.c | 1727 --- .../bl808_bsp_driver/std_drv/src/bl808_emac.c | 785 -- .../std_drv/src/bl808_glb_misc.c | 2959 ----- .../std_drv/src/bl808_glb_pll.c | 3050 ----- .../bl808_bsp_driver/std_drv/src/bl808_i2c.c | 964 -- .../bl808_bsp_driver/std_drv/src/bl808_i2s.c | 508 - .../bl808_bsp_driver/std_drv/src/bl808_ipc.c | 737 -- .../bl808_bsp_driver/std_drv/src/bl808_ir.c | 1269 -- .../std_drv/src/bl808_iso11898.c | 671 - .../bl808_bsp_driver/std_drv/src/bl808_lz4d.c | 286 - .../std_drv/src/bl808_mfg_efuse.c | 105 - .../std_drv/src/bl808_mfg_flash.c | 241 - .../std_drv/src/bl808_mfg_media.c | 237 - .../std_drv/src/bl808_mjdec.c | 467 - .../std_drv/src/bl808_mjpeg.c | 1006 -- .../std_drv/src/bl808_osd_blend.c | 480 - .../std_drv/src/bl808_osd_draw.c | 335 - .../std_drv/src/bl808_osd_probe.c | 245 - .../bl808_bsp_driver/std_drv/src/bl808_pwm.c | 1247 -- .../std_drv/src/bl808_romapi_patch.c | 3092 ----- .../std_drv/src/bl808_sec_dbg.c | 163 - .../std_drv/src/bl808_sec_eng.c | 5135 -------- .../std_drv/src/bl808_sf_cfg.c | 1673 --- .../std_drv/src/bl808_sf_cfg_ext.c | 295 - .../std_drv/src/bl808_sf_ctrl.c | 1870 --- .../std_drv/src/bl808_sflash.c | 2164 ---- .../bl808_bsp_driver/std_drv/src/bl808_spi.c | 1373 -- .../std_drv/src/bl808_timer.c | 1317 -- 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bsp/bouffalo_lab/bl61x/flash_prog_cfg.ini | 12 + bsp/bouffalo_lab/bl61x/rtconfig.h | 244 + bsp/bouffalo_lab/bl61x/rtconfig.py | 62 + bsp/bouffalo_lab/bl70x/.config | 1001 ++ bsp/bouffalo_lab/bl70x/Kconfig | 26 + bsp/bouffalo_lab/bl70x/SConscript | 14 + bsp/bouffalo_lab/bl70x/SConstruct | 46 + .../bl70x/applications/SConscript | 9 + .../bl70x}/applications/main.c | 2 +- bsp/bouffalo_lab/bl70x/board/Kconfig | 16 + bsp/bouffalo_lab/bl70x/board/SConscript | 9 + bsp/bouffalo_lab/bl70x/board/board.c | 197 + bsp/bouffalo_lab/bl70x/board/board.h | 34 + .../builtin_imgs/boot2_bl702_debug_v8.0.7.bin | Bin 0 -> 43216 bytes .../boot2_bl702_release_v8.0.7.bin | Bin 0 -> 43168 bytes .../board/builtin_imgs/mfg_bl702_stdfw.bin | Bin 0 -> 141440 bytes bsp/bouffalo_lab/bl70x/board/config/.gitkeep | 0 bsp/bouffalo_lab/bl70x/board/fw_header.c | 126 + bsp/bouffalo_lab/bl70x/board/fw_header.h | 170 + .../board/linker_scripts/bl702_flash.ld} | 193 +- bsp/bouffalo_lab/bl70x/board/trap_gcc.S | 17 + bsp/bouffalo_lab/bl70x/combine.sh | 39 + bsp/bouffalo_lab/bl70x/flash_prog_cfg.ini | 12 + bsp/bouffalo_lab/bl70x/rtconfig.h | 244 + bsp/bouffalo_lab/bl70x/rtconfig.py | 62 + bsp/bouffalo_lab/bl808/build_bl808.sh | 5 + .../builtin_imgs/boot2_bl808_debug_v8.0.7.bin | Bin 0 -> 56224 bytes .../boot2_bl808_release_v8.0.7.bin | Bin 0 -> 56224 bytes .../mfg_bl808_gu_7c2526e09_autoboot_v0.56.bin | Bin 0 -> 468448 bytes .../mfg_bl808_gu_7c2526e09_v0.56.bin | Bin 0 -> 468448 bytes bsp/bouffalo_lab/bl808/config/.gitkeep | 0 bsp/bouffalo_lab/bl808/flash_prog_cfg.ini | 11 + bsp/{ => bouffalo_lab}/bl808/m0/.config | 44 +- bsp/bouffalo_lab/bl808/m0/Kconfig | 26 + bsp/bouffalo_lab/bl808/m0/SConscript | 14 + bsp/bouffalo_lab/bl808/m0/SConstruct | 45 + .../bl808/m0/applications/SConscript | 9 + bsp/bouffalo_lab/bl808/m0/applications/main.c | 19 + bsp/bouffalo_lab/bl808/m0/board/Kconfig | 16 + bsp/bouffalo_lab/bl808/m0/board/SConscript | 9 + bsp/bouffalo_lab/bl808/m0/board/board.c | 221 + bsp/bouffalo_lab/bl808/m0/board/board.h | 38 + bsp/bouffalo_lab/bl808/m0/board/fw_header.c | 208 + bsp/bouffalo_lab/bl808/m0/board/fw_header.h | 213 + .../board/linker_scripts/bl808_flash_m0.ld} | 84 +- bsp/bouffalo_lab/bl808/m0/board/trap_gcc.S | 17 + bsp/bouffalo_lab/bl808/m0/combine.sh | 39 + bsp/bouffalo_lab/bl808/m0/flash_prog_cfg.ini | 12 + bsp/{ => bouffalo_lab}/bl808/m0/rtconfig.h | 22 +- bsp/{ => bouffalo_lab}/bl808/m0/rtconfig.py | 21 +- bsp/bouffalo_lab/bouffalo_flash_cube.sh | 42 + .../figures/bouffalo_flash_cube.jpg | Bin 0 -> 75105 bytes .../figures/rt-thread.jpg} | Bin bsp/bouffalo_lab/libraries/Kconfig | 2 + .../libraries/bl_mcu_sdk}/.ignore_format.yml | 5 +- .../libraries/bl_mcu_sdk/SConscript | 15 + .../libraries/bl_mcu_sdk/drivers/SConscript | 15 + .../bl_mcu_sdk/drivers/lhal/Doxyfile | 2768 ++++ .../bl_mcu_sdk/drivers/lhal/SConscript | 123 + .../drivers/lhal/config/bl602/bl602_irq.h | 84 + .../lhal/config/bl602/bl602_memorymap.h | 67 + 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| 247 + .../drivers/lhal/include/bflb_sec_dsa.h | 82 + .../drivers/lhal/include/bflb_sec_ecdsa.h | 158 + .../drivers/lhal/include/bflb_sec_irq.h | 53 + .../drivers/lhal/include/bflb_sec_pka.h | 285 + .../drivers/lhal/include/bflb_sec_sha.h | 318 + .../drivers/lhal/include/bflb_sec_trng.h | 69 + .../drivers/lhal/include/bflb_spi.h | 273 + .../drivers/lhal/include/bflb_spi_psram.h | 152 + .../drivers/lhal/include/bflb_timer.h | 204 + .../drivers/lhal/include/bflb_uart.h | 368 + .../drivers/lhal/include/bflb_wdg.h | 117 + .../lhal/include/compiler/compiler_gcc.h} | 66 +- .../lhal/include/compiler/compiler_ld.h | 20 + .../drivers/lhal/include/hardware/adc_reg.h | 268 + .../drivers/lhal/include/hardware/auadc_reg.h | 193 + .../drivers/lhal/include/hardware/audac_reg.h | 167 + .../lhal/include/hardware/cam_front_reg.h | 185 + .../drivers/lhal/include/hardware/cam_reg.h | 449 + .../drivers/lhal/include/hardware/cks_reg.h | 64 + .../drivers/lhal/include/hardware/csi_reg.h | 165 + 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.../drivers/lhal/include/hardware/spi_reg.h | 184 + .../drivers/lhal/include/hardware/timer_reg.h | 285 + .../drivers/lhal/include/hardware/uart_reg.h | 370 + .../lhal/include/hardware/usb_v1_reg.h | 618 + .../lhal/include/hardware/usb_v2_reg.h | 734 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_adc.c | 646 + .../bl_mcu_sdk/drivers/lhal/src/bflb_auadc.c | 291 + .../bl_mcu_sdk/drivers/lhal/src/bflb_audac.c | 360 + .../bl_mcu_sdk/drivers/lhal/src/bflb_cam.c | 624 + .../bl_mcu_sdk/drivers/lhal/src/bflb_cks.c | 34 + .../bl_mcu_sdk/drivers/lhal/src/bflb_clock.c | 93 + .../drivers/lhal/src/bflb_common.c} | 148 +- .../bl_mcu_sdk/drivers/lhal/src/bflb_csi.c | 143 + .../bl_mcu_sdk/drivers/lhal/src/bflb_dac.c | 160 + .../bl_mcu_sdk/drivers/lhal/src/bflb_dbi.c | 799 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_dma.c | 455 + .../drivers/lhal/src/bflb_ef_ctrl.c | 932 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_emac.c | 879 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_flash.c | 809 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c | 447 + .../bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c | 456 + .../bl_mcu_sdk/drivers/lhal/src/bflb_i2s.c | 341 + .../bl_mcu_sdk/drivers/lhal/src/bflb_ir.c | 637 + .../bl_mcu_sdk/drivers/lhal/src/bflb_irq.c | 130 + .../drivers/lhal/src/bflb_iso11898.c | 366 + .../bl_mcu_sdk/drivers/lhal/src/bflb_kys.c | 217 + .../bl_mcu_sdk/drivers/lhal/src/bflb_l1c.c | 188 + .../bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c | 569 + .../bl_mcu_sdk/drivers/lhal/src/bflb_mtimer.c | 123 + .../bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v1.c | 278 + .../bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v2.c | 388 + .../bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c | 76 + .../bl_mcu_sdk/drivers/lhal/src/bflb_sdio2.c | 296 + .../drivers/lhal/src/bflb_sec_aes.c | 392 + .../drivers/lhal/src/bflb_sec_irq.c | 176 + .../drivers/lhal/src/bflb_sec_sha.c | 880 ++ .../drivers/lhal/src/bflb_sec_trng.c | 172 + .../bl_mcu_sdk/drivers/lhal/src/bflb_spi.c | 587 + .../drivers/lhal/src/bflb_spi_psram.c | 774 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_timer.c | 292 + .../bl_mcu_sdk/drivers/lhal/src/bflb_uart.c | 719 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c | 584 + .../bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c | 1073 ++ .../bl_mcu_sdk/drivers/lhal/src/bflb_wdg.c | 119 + .../drivers/lhal/src/flash/bflb_sf_cfg.c | 3703 ++++++ .../drivers/lhal/src/flash/bflb_sf_cfg.h | 215 + .../drivers/lhal/src/flash/bflb_sf_ctrl.c | 2244 ++++ .../drivers/lhal/src/flash/bflb_sf_ctrl.h | 482 + .../drivers/lhal/src/flash/bflb_sflash.c | 2182 ++++ .../drivers/lhal/src/flash/bflb_sflash.h | 226 + .../drivers/lhal/src/flash/bflb_xip_sflash.c | 495 + .../drivers/lhal/src/flash/bflb_xip_sflash.h} | 57 +- .../bl_mcu_sdk/drivers/soc/SConscript | 15 + .../bl_mcu_sdk/drivers/soc/bl602/SConscript | 48 + .../drivers/soc/bl602/std/include/bl602_aon.h | 107 + .../soc/bl602/std/include/bl602_clock.h | 128 + .../soc/bl602/std/include/bl602_common.h | 215 + .../soc/bl602/std/include/bl602_ef_cfg.h | 97 + .../soc/bl602/std/include/bl602_ef_ctrl.h | 352 + .../drivers/soc/bl602/std/include/bl602_glb.h | 666 + .../soc/bl602/std/include/bl602_gpio.h | 444 + .../drivers/soc/bl602/std/include/bl602_hbn.h | 497 + .../drivers/soc/bl602/std/include/bl602_l1c.h | 189 + .../drivers/soc/bl602/std/include/bl602_pds.h | 501 + .../soc/bl602/std/include/bl602_romdriver.h | 799 ++ .../drivers/soc/bl602/std/include/bl602_sdu.h | 184 + .../soc/bl602/std/include/bl602_sf_cfg_ext.h} | 23 +- .../soc/bl602/std/include/bl602_sflash_ext.h | 87 + .../soc/bl602/std/include/bl602_tzc_sec.h} | 47 +- .../bl602/std/include/bl602_xip_sflash_ext.h | 97 + .../soc/bl602/std/include/hardware/aon_reg.h | 1560 +++ .../soc/bl602/std/include/hardware/bl602.h | 250 + .../bl602/std/include/hardware/ef_ctrl_reg.h | 812 ++ .../bl602/std/include/hardware/ef_data_reg.h | 762 ++ .../soc/bl602/std/include/hardware/glb_reg.h | 4094 ++++++ .../soc/bl602/std/include/hardware/hbn_reg.h | 760 ++ .../soc/bl602/std/include/hardware/l1c_reg.h | 318 + .../soc/bl602/std/include/hardware/pds_reg.h | 1085 ++ .../bl602/std/include/hardware/sf_ctrl_reg.h | 2450 ++++ .../bl602/std/include/hardware/tzc_sec_reg.h | 256 + .../drivers/soc/bl602/std/port/bl602_clock.c | 19 + .../drivers/soc/bl602/std/src/bl602_aon.c | 551 + .../drivers/soc/bl602/std/src/bl602_clock.c | 601 + .../drivers/soc/bl602/std/src/bl602_common.c | 162 + .../drivers/soc/bl602/std/src/bl602_ef_cfg.c | 413 + .../drivers/soc/bl602/std/src/bl602_glb.c | 2619 ++++ .../drivers/soc/bl602/std/src/bl602_hbn.c | 1799 +++ .../drivers/soc/bl602/std/src/bl602_l1c.c | 428 + .../drivers/soc/bl602/std/src/bl602_pds.c | 841 ++ .../drivers/soc/bl602/std/src/bl602_romapi.c | 1035 ++ .../soc/bl602/std/src/bl602_romdriver.c | 291 + .../soc/bl602/std/src/bl602_sf_cfg_ext.c | 792 ++ .../soc/bl602/std/src/bl602_sflash_ext.c | 719 ++ .../drivers/soc/bl602/std/src/bl602_tzc_sec.c | 237 + .../soc/bl602/std/src/bl602_xip_sflash_ext.c | 593 + .../drivers/soc/bl602/std/startup/interrupt.c | 204 + .../drivers/soc/bl602/std/startup/start.S | 96 + .../soc/bl602/std/startup}/start_load.c | 53 +- .../soc/bl602/std/startup/system_bl602.c | 79 + .../bl_mcu_sdk/drivers/soc/bl616/SConscript | 54 + .../soc/bl616/std/include/bl616_acomp.h} | 14 +- .../drivers/soc/bl616/std/include/bl616_aon.h | 114 + .../soc/bl616/std/include/bl616_clock.h | 196 + .../soc/bl616/std/include/bl616_common.h | 186 + .../soc/bl616/std/include/bl616_ef_cfg.h | 88 + .../soc/bl616/std/include/bl616_ef_ctrl.h | 457 + .../drivers/soc/bl616/std/include/bl616_glb.h | 1748 +++ .../soc/bl616/std/include/bl616_glb_gpio.h | 232 + .../soc/bl616/std/include/bl616_gpio.h | 148 + .../drivers/soc/bl616/std/include/bl616_hbn.h | 687 + .../soc/bl616/std/include/bl616_l1c.h} | 115 +- .../soc/bl616/std/include/bl616_mfg_efuse.h | 31 + .../soc/bl616/std/include/bl616_mfg_flash.h | 36 + .../soc/bl616/std/include/bl616_mfg_media.h | 52 + .../drivers/soc/bl616/std/include/bl616_pds.h | 585 + .../drivers/soc/bl616/std/include/bl616_pm.h | 43 + .../soc/bl616/std/include/bl616_psram.h | 487 + .../bl616/std/include/bl616_romapi_patch.h} | 27 +- .../bl616/std/include/bl616_romdriver_e907.h} | 1036 +- .../drivers/soc/bl616/std/include/bl616_sdh.h | 979 ++ .../drivers/soc/bl616/std/include/bl616_sdu.h | 194 + .../soc/bl616/std/include/bl616_tzc_sec.h | 247 + .../soc/bl616/std/include/hardware/aon_reg.h | 1762 +++ .../soc/bl616/std/include/hardware/bl616.h | 354 + .../soc/bl616/std/include/hardware/cci_reg.h | 777 ++ .../bl616/std/include/hardware/ef_ctrl_reg.h | 895 ++ .../bl616/std/include/hardware/ef_data_reg.h | 2225 ++++ .../soc/bl616/std/include/hardware/glb_reg.h | 10496 ++++++++++++++++ .../soc/bl616/std/include/hardware/hbn_reg.h | 941 ++ .../bl616/std/include/hardware/mcu_misc_reg.h | 421 + .../bl616/std/include/hardware}/mm_glb_reg.h | 102 +- .../bl616/std/include/hardware/mm_misc_reg.h | 243 + .../soc/bl616/std/include/hardware/pds_reg.h | 1264 ++ .../bl616/std/include/hardware/psram_reg.h | 1377 ++ .../soc/bl616/std/include/hardware/sdh_reg.h | 2732 ++++ .../bl616/std/include/hardware/sf_ctrl_reg.h | 3371 +++++ .../bl616/std/include/hardware/tzc_nsec_reg.h | 2833 +++++ .../bl616/std/include/hardware/tzc_sec_reg.h | 2833 +++++ .../drivers/soc/bl616/std/port/bl616_clock.c | 25 + .../drivers/soc/bl616/std/src/bl616_aon.c | 717 ++ .../drivers/soc/bl616/std/src/bl616_clock.c | 1424 +++ .../drivers/soc/bl616/std/src/bl616_common.c | 224 + .../drivers/soc/bl616/std/src/bl616_ef_cfg.c | 584 + .../drivers/soc/bl616/std/src/bl616_glb.c | 3823 ++++++ .../soc/bl616/std/src/bl616_glb_gpio.c | 962 ++ .../drivers/soc/bl616/std/src/bl616_hbn.c | 2216 ++++ .../drivers/soc/bl616/std/src/bl616_l1c.c | 388 + .../soc/bl616/std/src/bl616_mfg_efuse.c | 434 + .../soc/bl616/std/src/bl616_mfg_flash.c | 116 + .../soc/bl616/std/src/bl616_mfg_media.c | 396 + .../drivers/soc/bl616/std/src/bl616_pds.c | 863 ++ .../drivers/soc/bl616/std/src/bl616_pm.c | 974 ++ .../drivers/soc/bl616/std/src/bl616_psram.c} | 70 +- .../soc/bl616/std/src/bl616_romapi_e907.c} | 1558 +-- .../soc/bl616/std/src/bl616_romapi_patch.c | 3200 +++++ .../soc/bl616/std/src/bl616_romdriver_e907.c} | 248 +- .../drivers/soc/bl616/std/src/bl616_sdh.c | 1363 ++ .../drivers/soc/bl616/std/src/bl616_sdu.c | 76 + .../drivers/soc/bl616/std/src/bl616_tzc_sec.c | 826 ++ .../drivers/soc/bl616/std/startup/interrupt.c | 185 + .../drivers/soc/bl616/std/startup/irq_ctx.h | 378 + .../soc/bl616/std/startup}/riscv_fpu.S | 0 .../drivers/soc/bl616/std/startup/start.S | 57 + .../soc/bl616/std/startup}/start_load.c | 35 +- .../soc/bl616/std/startup/system_bl616.c | 147 + .../drivers/soc/bl616/std/startup/vector.S} | 121 +- .../bl_mcu_sdk/drivers/soc/bl702/SConscript | 48 + .../drivers/soc/bl702/std/include/bl702_aon.h | 111 + .../soc/bl702/std/include/bl702_clock.h | 134 + .../soc/bl702/std/include/bl702_common.h | 215 + .../soc/bl702/std/include/bl702_ef_cfg.h | 94 + .../soc/bl702/std/include/bl702_ef_ctrl.h | 329 + .../drivers/soc/bl702/std/include/bl702_glb.h | 822 ++ .../soc/bl702/std/include/bl702_gpio.h | 952 ++ .../drivers/soc/bl702/std/include/bl702_hbn.h | 564 + .../drivers/soc/bl702/std/include/bl702_l1c.h | 202 + .../soc/bl702/std/include/bl702_nf_cfg.h | 48 + .../soc/bl702/std/include/bl702_nflash.h} | 166 +- .../drivers/soc/bl702/std/include/bl702_pds.h | 802 ++ .../soc/bl702/std/include/bl702_romdriver.h | 632 + .../soc/bl702/std/include/bl702_sf_cfg_ext.h | 84 + .../soc/bl702/std/include/bl702_sflash_ext.h | 93 + .../soc/bl702/std/include/bl702_snflash.h | 183 + .../bl702/std/include/bl702_xip_sflash_ext.h | 88 + .../soc/bl702/std/include/hardware/aon_reg.h | 1579 +++ .../soc/bl702/std/include/hardware/bl702.h | 306 + .../bl702/std/include/hardware/ef_ctrl_reg.h | 812 ++ .../bl702/std/include/hardware/ef_data_reg.h | 762 ++ .../soc/bl702/std/include/hardware/glb_reg.h | 5498 ++++++++ .../soc/bl702/std/include/hardware/gpip_reg.h | 317 + .../soc/bl702/std/include/hardware/hbn_reg.h | 814 ++ .../soc/bl702/std/include/hardware/l1c_reg.h | 366 + .../soc/bl702/std/include/hardware/pds_reg.h | 1411 +++ .../bl702/std/include/hardware/sf_ctrl_reg.h | 2735 ++++ .../bl702/std/include/hardware/tzc_sec_reg.h | 256 + .../drivers/soc/bl702/std/port/bl702_clock.c | 19 + .../drivers/soc/bl702/std/src/bl702_aon.c | 582 + .../drivers/soc/bl702/std/src/bl702_clock.c | 738 ++ .../drivers/soc/bl702/std/src/bl702_common.c | 204 + .../drivers/soc/bl702/std/src/bl702_ef_cfg.c | 410 + .../drivers/soc/bl702/std/src/bl702_glb.c | 4056 ++++++ .../drivers/soc/bl702/std/src/bl702_hbn.c | 2031 +++ .../drivers/soc/bl702/std/src/bl702_l1c.c | 647 + .../drivers/soc/bl702/std/src/bl702_pds.c | 1364 ++ .../drivers/soc/bl702/std/src/bl702_romapi.c | 1125 ++ .../soc/bl702/std/src/bl702_romdriver.c | 246 + .../soc/bl702/std/src/bl702_sf_cfg_ext.c | 710 ++ .../soc/bl702/std/src/bl702_sflash_ext.c | 274 + .../drivers/soc/bl702/std/src/bl702_snflash.c | 890 ++ .../soc/bl702/std/src/bl702_xip_sflash_ext.c | 197 + .../drivers/soc/bl702/std/startup/interrupt.c | 204 + .../drivers/soc/bl702/std/startup/start.S | 96 + .../soc/bl702/std/startup}/start_load.c | 56 +- .../soc/bl702/std/startup/system_bl702.c | 112 + .../bl_mcu_sdk/drivers/soc/bl808/SConscript | 69 + .../soc/bl808/std/include}/bl808_aon.h | 0 .../soc/bl808/std/include}/bl808_clock.h | 2 +- .../soc/bl808/std/include/bl808_common.h | 192 + .../soc/bl808/std/include/bl808_ef_cfg.h} | 62 +- .../soc/bl808/std/include}/bl808_ef_ctrl.h | 40 +- .../soc/bl808/std/include}/bl808_glb.h | 170 +- .../soc/bl808/std/include}/bl808_glb_gpio.h | 5 +- .../soc/bl808/std/include}/bl808_gpio.h | 0 .../soc/bl808/std/include}/bl808_hbn.h | 6 +- .../soc/bl808/std/include}/bl808_ipc.h | 0 .../soc/bl808/std/include}/bl808_l1c.h | 0 .../soc/bl808/std/include}/bl808_pds.h | 11 +- .../soc/bl808/std/include}/bl808_psram.h | 23 +- .../soc/bl808/std/include}/bl808_psram_uhs.h | 1 + .../soc/bl808/std/include}/bl808_sdh.h | 3 +- .../soc/bl808/std/include}/bl808_tzc_sec.h | 10 +- .../soc/bl808/std/include/bl808_uhs_phy.h | 117 + .../soc/bl808/std/include/hardware}/aon_reg.h | 0 .../soc/bl808/std/include/hardware}/bl808.h | 32 +- .../soc/bl808/std/include/hardware}/cci_reg.h | 0 .../std/include/hardware}/codec_misc_reg.h | 0 .../bl808/std/include/hardware}/ef_ctrl_reg.h | 0 .../std/include/hardware}/ef_data_0_reg.h | 0 .../std/include/hardware}/ef_data_1_reg.h | 0 .../soc/bl808/std/include/hardware}/glb_reg.h | 0 .../bl808/std/include/hardware}/gpip_reg.h | 0 .../soc/bl808/std/include/hardware}/hbn_reg.h | 0 .../soc/bl808/std/include/hardware}/ipc_reg.h | 0 .../std/include/hardware}/mcu_misc_reg.h | 0 .../bl808/std/include/hardware/mm_glb_reg.h | 726 ++ .../bl808/std/include/hardware}/mm_misc_reg.h | 168 +- .../soc/bl808/std/include/hardware}/pds_reg.h | 0 .../bl808/std/include/hardware}/psram_reg.h | 0 .../std/include/hardware}/psram_uhs_reg.h | 0 .../soc/bl808/std/include/hardware}/sdh_reg.h | 0 .../bl808/std/include/hardware}/sf_ctrl_reg.h | 0 .../std/include/hardware}/tzc_nsec_reg.h | 422 +- .../bl808/std/include/hardware}/tzc_sec_reg.h | 576 +- .../drivers/soc/bl808/std/port/bl808_clock.c | 21 + .../drivers/soc/bl808/std}/src/bl808_aon.c | 2 +- .../drivers/soc/bl808/std}/src/bl808_clock.c | 373 +- .../drivers/soc/bl808/std}/src/bl808_common.c | 0 .../drivers/soc/bl808/std/src/bl808_ef_cfg.c | 434 + .../drivers/soc/bl808/std}/src/bl808_glb.c | 734 +- .../soc/bl808/std}/src/bl808_glb_gpio.c | 0 .../drivers/soc/bl808/std}/src/bl808_hbn.c | 24 +- .../drivers/soc/bl808/std}/src/bl808_l1c.c | 0 .../drivers/soc/bl808/std}/src/bl808_pds.c | 4 +- .../soc/bl808/std}/src/bl808_psram_uhs.c | 24 +- .../drivers/soc/bl808/std}/src/bl808_sdh.c | 34 +- .../soc/bl808/std}/src/bl808_tzc_sec.c | 4 +- .../drivers/soc/bl808/std/src/bl808_uhs_phy.c | 2894 +++++ .../soc/bl808/std/startup/d0/interrupt.c | 154 + .../soc/bl808/std/startup/d0}/irq_ctx.h | 0 .../soc/bl808/std/startup/d0/riscv_fpu.S | 221 + .../drivers/soc/bl808/std/startup/d0/start.S} | 19 +- .../soc/bl808/std/startup/d0/start_load.c | 84 + .../soc/bl808/std/startup/d0/system_bl808.c | 56 + .../soc/bl808/std/startup/d0/vector.S} | 24 +- .../soc/bl808/std/startup/lp/interrupt.c | 206 + .../soc/bl808/std/startup/lp}/irq_ctx.h | 11 +- .../soc/bl808/std/startup/lp/riscv_fpu.S | 221 + .../drivers/soc/bl808/std/startup/lp/start.S} | 32 +- .../soc/bl808/std/startup/lp/start_load.c | 92 + .../soc/bl808/std/startup/lp/system_bl808.c | 24 + .../soc/bl808/std/startup/lp/vector.S} | 162 +- .../soc/bl808/std/startup/m0/interrupt.c | 185 + .../soc/bl808/std/startup/m0/irq_ctx.h | 378 + .../soc/bl808/std/startup/m0/riscv_fpu.S | 221 + .../drivers/soc/bl808/std/startup/m0/start.S | 57 + .../soc/bl808/std/startup/m0/start_load.c | 92 + .../soc/bl808/std/startup/m0}/system_bl808.c | 95 +- .../drivers/soc/bl808/std/startup/m0/vector.S | 320 + .../bflb_tools/bflb_fw_post_proc/usage.txt | 17 + bsp/bouffalo_lab/libraries/rt_drivers/Kconfig | 89 + .../libraries/rt_drivers/SConscript | 25 + .../libraries/rt_drivers/drv_gpio.c | 229 + .../libraries/rt_drivers/drv_gpio.h | 23 + .../libraries/rt_drivers/drv_uart.c | 305 + .../libraries/rt_drivers}/drv_uart.h | 6 +- libcpu/risc-v/SConscript | 2 +- libcpu/risc-v/t-head/e9xx/SConscript | 12 - libcpu/risc-v/t-head/e9xx/interrupt_gcc.S | 224 - 944 files changed, 190650 insertions(+), 205718 deletions(-) delete mode 100644 bsp/bl808/README.md delete mode 100644 bsp/bl808/figures/program.jpg delete mode 100644 bsp/bl808/m0/drivers/Kconfig delete mode 100644 bsp/bl808/m0/drivers/SConscript delete mode 100644 bsp/bl808/m0/drivers/board.c delete mode 100644 bsp/bl808/m0/drivers/board.h delete mode 100644 bsp/bl808/m0/drivers/drv_gpio.c delete mode 100644 bsp/bl808/m0/drivers/drv_gpio.h delete mode 100644 bsp/bl808/m0/drivers/drv_i2c.c delete mode 100644 bsp/bl808/m0/drivers/drv_i2c.h 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bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/csi_dsp/include/csi_const_structs.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/csi_dsp/include/csi_instance.h (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/csi_dsp/include/csi_math.h (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/rv_Sv39.c (94%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/rv_Sv39.h (97%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/rv_hart.c (81%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/rv_hart.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/rv_hpm.h (91%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/rv_pmp.c (99%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head}/rv_syscall.h (98%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_adc.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_auadc.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_audac.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cam.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cks.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_clock.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_common.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_csi.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dac.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dbi.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ef_ctrl.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_efuse.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_emac.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_flash.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2c.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2s.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ir.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_irq.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_kys.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_l1c.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_list.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mtimer.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v1.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v2.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sdio2.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_aes.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_dsa.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_ecdsa.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_irq.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_pka.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_sha.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_trng.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi_psram.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_timer.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_wdg.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_gcc.h} (52%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/adc_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/auadc_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/audac_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/cam_front_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/cam_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/cks_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/csi_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dac_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dbi_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dma_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dtsrc_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/ef_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/emac_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/gpio_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/i2c_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/i2s_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/ir_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/iso11898_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/kys_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/mjpeg_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/pwm_v1_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/pwm_v2_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sdio2_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sec_eng_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sf_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/spi_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/timer_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/uart_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v1_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v2_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_adc.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_auadc.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_audac.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cam.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cks.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_common.c} (76%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_csi.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dac.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dbi.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dma.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ef_ctrl.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_emac.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_flash.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2s.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ir.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_irq.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_kys.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_l1c.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mtimer.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v1.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v2.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sdio2.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_aes.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_irq.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_sha.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi_psram.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_timer.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_wdg.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.h} (55%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/SConscript create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/SConscript create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_aon.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_clock.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_common.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_cfg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_ctrl.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_glb.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_gpio.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_hbn.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_l1c.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pds.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_romdriver.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sdu.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h} (79%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sflash_ext.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_tzc_sec.h} (68%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/aon_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/bl602.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_data_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/glb_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/hbn_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/l1c_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/pds_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/sf_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/tzc_sec_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/port/bl602_clock.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_aon.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_clock.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_common.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_ef_cfg.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_glb.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_l1c.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pds.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romapi.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romdriver.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_sflash_ext.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_tzc_sec.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/interrupt.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup}/start_load.c (70%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/system_bl602.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/SConscript rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_acomp.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h} (97%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_aon.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_common.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_cfg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_ctrl.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb_gpio.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_gpio.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_hbn.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_lz4d.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_l1c.h} (50%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_efuse.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_flash.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_media.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pds.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pm.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_psram.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romapi_patch.h} (70%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romdriver_e907.h} (64%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdh.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdu.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_tzc_sec.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/aon_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/bl616.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/cci_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/ef_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/ef_data_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/glb_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/hbn_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mcu_misc_reg.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware}/mm_glb_reg.h (92%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mm_misc_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/pds_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/psram_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sdh_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sf_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/tzc_nsec_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/tzc_sec_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/port/bl616_clock.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_aon.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_clock.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_common.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_ef_cfg.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb_gpio.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_l1c.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_efuse.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_flash.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_media.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pds.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_psram.c} (91%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c} (53%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c} (74%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdh.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdu.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_tzc_sec.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/interrupt.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/irq_ctx.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup}/riscv_fpu.S (100%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/start.S rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup}/start_load.c (78%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/system_bl616.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/vectors.S => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/vector.S} (74%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/SConscript create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_aon.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_clock.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_common.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_cfg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_ctrl.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_glb.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_gpio.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_hbn.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_l1c.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nf_cfg.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nflash.h} (58%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_pds.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_romdriver.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sflash_ext.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_snflash.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/aon_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/bl702.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_data_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/glb_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/gpip_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/hbn_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/l1c_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/pds_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/sf_ctrl_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/tzc_sec_reg.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/port/bl702_clock.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_aon.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_clock.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_common.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_ef_cfg.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_glb.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_hbn.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_l1c.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_pds.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romapi.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romdriver.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sflash_ext.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_snflash.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/interrupt.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/start.S rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup}/start_load.c (70%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/system_bl702.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_aon.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_clock.h (99%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_common.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_probe.h => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ef_cfg.h} (65%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_ef_ctrl.h (87%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_glb.h (95%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_glb_gpio.h (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_gpio.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_hbn.h (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_ipc.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_l1c.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_pds.h (98%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_psram.h (95%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_psram_uhs.h (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_sdh.h (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include}/bl808_tzc_sec.h (97%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_uhs_phy.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/aon_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/bl808.h (97%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/cci_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/codec_misc_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/ef_ctrl_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/ef_data_0_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/ef_data_1_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/glb_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/gpip_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/hbn_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/ipc_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/mcu_misc_reg.h (100%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mm_glb_reg.h rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/mm_misc_reg.h (88%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/pds_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/psram_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/psram_uhs_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/sdh_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/sf_ctrl_reg.h (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/tzc_nsec_reg.h (93%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware}/tzc_sec_reg.h (90%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/port/bl808_clock.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_aon.c (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_clock.c (82%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_common.c (100%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_ef_cfg.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_glb.c (89%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_glb_gpio.c (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_hbn.c (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_l1c.c (100%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_pds.c (99%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_psram_uhs.c (98%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_sdh.c (98%) mode change 100644 => 100755 rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std}/src/bl808_tzc_sec.c (99%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/interrupt.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0}/irq_ctx.h (100%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/riscv_fpu.S rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/startup.S => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start.S} (85%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start_load.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/system_bl808.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/vectors.S => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/vector.S} (98%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/interrupt.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp}/irq_ctx.h (97%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/riscv_fpu.S rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/startup.S => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start.S} (59%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start_load.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/system_bl808.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/vectors.S => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/vector.S} (53%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/irq_ctx.h create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/riscv_fpu.S create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start.S create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start_load.c rename bsp/{bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source => bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0}/system_bl808.c (70%) mode change 100644 => 100755 create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/vector.S create mode 100755 bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt create mode 100755 bsp/bouffalo_lab/libraries/rt_drivers/Kconfig create mode 100755 bsp/bouffalo_lab/libraries/rt_drivers/SConscript create mode 100755 bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c create mode 100755 bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.h create mode 100755 bsp/bouffalo_lab/libraries/rt_drivers/drv_uart.c rename bsp/{bl808/m0/drivers => bouffalo_lab/libraries/rt_drivers}/drv_uart.h (84%) mode change 100644 => 100755 delete mode 100644 libcpu/risc-v/t-head/e9xx/SConscript delete mode 100644 libcpu/risc-v/t-head/e9xx/interrupt_gcc.S diff --git a/bsp/bl808/README.md b/bsp/bl808/README.md deleted file mode 100644 index 9a609207ec..0000000000 --- a/bsp/bl808/README.md +++ /dev/null @@ -1,128 +0,0 @@ -# 博流智能 BL808板级支持包说明 - -## 1. 简介 - -BL808 是高度集成的 AIoT 芯片组，具有 Wi-Fi/BT/BLE/Zigbee 等无线互联单元，包含多个 CPU 以及音频编码译码器、视频编码译码器和 AI 硬件加速器，适用于各种高性能和低功耗应用领域。 - -BL808 系列芯片主要包含无线和多媒体两个子系统。 - -无线子系统包含一颗 RISC-V 32-bit 高性能 CPU（m0），集成 Wi-Fi/BT/Zigbee 无线子系统，可以实现多种无线连接和数据传输，提供多样化的连接与传输体验。 -多媒体子系统包含一颗 RISC-V 64-bit 超高性能 CPU（d0），集成 DVP/CSI/ H264/NPU 等视频处理模块，可以广泛应用于视频监控/智能音箱等多种 AI 领域 - -多媒体子系统组成部分如下： - -- NPU HW NN 协处理器 (BLAI-100)，适用于人工智能应用领域 -- 摄像头接口 -- 音频编码译码器 -- 视频编码解码器 -- 传感器 -- 显示接口 - -电源管理单元控制低功耗模式。此外，还支持各种安全功能。 - -外围接口包括 USB2.0、 Ethernet、 SD/MMC、 SPI、 UART、 I2C、 I2S、 PWM、 GPDAC/GPADC、 ACOMP、 PIR、 Touch、 -IR remote、 Display 和 GPIO。 - -支持灵活的 GPIO 配置， BL808 最多可达 40 个 GPIO。 - -芯片规格包括如下： - -| 硬件 | 描述 | -| -- | -- | -|芯片型号| bl808 | -|CPU| 三核异构RISC-V CPUs：
RV64GCV 480MHz
RV32GCP 320MHz
RV32EMC 160MHz | -|RAM| 768KB SRAM + 64MB UHS PSRAM | -| 外设 | 内嵌AES与SHA256算法加速器 | -| AI NN 通用硬件加速器 | BLAI-100 用于视频/音频检测/识别，100GOPS 算力 | -| 摄像头接口 | DVP 和 MIPI-CSI | -| 显示接口 | SPI、DBI、DPI(RGB) | -| 无线 | 支持 Wi-Fi 802.11 b/g/n
支持 Bluetooth 5.x Dual-mode(BT+BLE)
支持 Wi-Fi / 蓝牙 共存 | - -## 2. 编译说明 - -BL808是多核异构架构，分为m0和d0，每个核需要单独编译，并烧录到对应的位置。 - -### 2.1. 交叉编译期路径设置 -下载risc-v的工具链，[下载地址1](https://occ.t-head.cn/community/download?id=4073475960903634944)或[下载地址2](https://dl.sipeed.com/shareURL/others/toolchain) - -Windows下请使用使用[env工具][1]，使用命令 `tar -xvf Xuantie-900-gcc-elf-newlib-mingw-V2.6.1-20220906.tar.gz` 解压交叉编译器，使用Windows下解压工具直接解压可能出现Windows下编译错误。 - -在`rtconfig.py`中将risc-v工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径 - -Windows： -``` -set RTT_EXEC_PATH=C:\Users\xxxx\Downloads\Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1\bin -``` - -Linux: -``` -export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin -``` - -### 2.2. 编译 - -Windows下推荐使用[env工具][1]，在console下进入bsp/bl808目录中，选择需要编译的核心，m0或d0，运行： - - cd bsp/bl808/m0 - menuconfig - pkgs --update - -如果在Linux平台下，可以先执行： - - scons --menuconfig - -它会自动下载env相关脚本到~/.env目录，然后执行 - - source ~/.env/env.sh - - cd bsp/bl808/m0 - pkgs --update - -更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。 - -如果编译正确无误，会产生rtthread.elf、rtthread_m0.bin文件。其中rtthread_m0.bin需要烧写到设备中进行运行。 - -## 3. 烧写及执行 - -连接好串口，然后使用[Bouffalo Lab Dev Cube](https://dev.bouffalolab.com/download)工具进行烧写bin文件。 - -![Bouffalo Lab Dev Cube](figures/program.jpg) - -### 3.1 运行结果 - -如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息： - -![terminal](figures/bl808.jpg) - -## 4. 驱动支持情况及计划 - -| 驱动 | 支持情况 | 备注 | -| ------ | ---- | :------: | -| UART | 支持 | UART0，用于shell，默认波特率2000000 | -| GPIO | 支持 | | -| I2C | 支持 | 软件 I2C1，默认 SCL——20，SDA——21 | - -## 5. 联系人信息 - -维护人：[flyingcys](https://github.com/flyingcys) - -## 6. 支持开发板列表 - -| | 开发板型号 | -| ------ | ---------- | -| Sipeed | M1s Dock | -| | | - - -## 7. 参考 -* 芯片[datasheet][2] - - [1]: https://www.rt-thread.org/page/download.html - [2]: https://github.com/bouffalolab/bl_docs - -## 8. FAQ - -- 在 windows 环境下，通过 UART 接口将开发板连接至电脑时，仅能识别到两个 USB converter 设备，但是识别不到对应的串口设备。 - - 进入到设备管理器中，右击对应的 USB converter 设备，进入到属性中的高级设置，钩选 vcp 选项，刷新后即可看到对应的串口设备。 - - 也可通过安装以下驱动解决问题： https://dl.sipeed.com/shareURL/MAIX/tools/ftdi_vcp_driver -- 使用 TypeC 数据线将电脑与板子的 UART 口连接起来，此时电脑上会出现两个串口 （如果出现鼠标不能动的现象请拔掉 USB 并且查看 [更新板载 bl702 固件](https://wiki.sipeed.com/hardware/zh/maix/m1s/other/start.html#给板载-bl702-进行烧录) 相关内容来修复问题)。 diff --git a/bsp/bl808/figures/program.jpg b/bsp/bl808/figures/program.jpg deleted file mode 100644 index dc9d9c262fa2dc36c734b656bb7db337a34408e3..0000000000000000000000000000000000000000 GIT binary patch literal 0 HcmV?d00001 literal 139945 zcmeFZ2RL0@*C@P{1kpl>P6W{f(L0IWdv8&<-b+Mw$U%rMh#sBjqIc1Ibha*f?}Bab zyK`#JdEayH_x<-i-@V^|!?W1WUTcjxM;~*HF(-Tqz6jiwlaiGJkdTl76T~k7p8*~N z=r?bo-MoR0hK7cLfqn~%02>Pv6N?1@4lV%&DHSCJDLMH)S~mK7_gQGj$r*SVS=c$a zxVWh3`Gxs7h1ec(aef1Wgn@y9g^5LsjZMr+O-{}EpZct|LC zNbq)m3ILF9AZGh*!oU6?A)}z)xQT|2aSIdiK;>-!83_di85QNm4OCRb)4quN04m-M zd}f(=a>n;&72`SwJdIm-&E^Z!PK7N76 zPb8(JWn|^lH8i!fb#(R2%q=XftU)%eZtfnQUf$1M{S*)w^g1{sI_7O`T>QI)#Ei_W z?3~=Z{14?HD=Mq1YijF0wY7J2c6Imkj*O0tPfSitLzb4mtgNoBZ)|QI9vz>Yo}GWa zxcr6}5`gjxTEAoV7rgKgcp;;rqM)LE!wU)76LF#7q28e8xQQ>Wie~D3=RT(&I)Ow~ zdRZ$5%_Fq~!ly37x9-w%Ezuo*L+xkG{$q&w|9`^lcf|g{3j$!FAR(BCf(M8KXUaF> zKzG;@9JsnU0|z!Li|X1B9HFo0so+4VeKYKho}!O-)9{W}t-cH?ZRZ1T8P#Z@*DrbH z47!y`L~pK;l~Fv<%N##^nucfaQ5u{L*>Alk$un2OxAJ^pNM!uuhaur&KVPTNyUWbF z6uMGkCRr<13lp(Ab)f3cj6E7t&63{dfeq>`F0wq?g~kRtIdKmyedXHqyNl81R`Nm~ z-3Pp>^`qYjEmvh7R@{x7ykny$m7hyoMB5N981TB{@coUmov4?lu@^e|>r;z1gA0?V z??;;ue_eAkYTy8gSDd^el~%>*VuS4z>ta+Ya){;w4>668I8vRL=4MTdAkvg}5$bWs z7llbRY|aS+f5s9mF%9{p_6vkB37{-<4!+cSwx33~Yn@A9rOf5}|%c1)$Z&y|@>uTn(`r_4a zB?JxxK{-CF8a!{Jb;Rh)o7ukftFNr|XMXLl@+4g9m?Bc@>kQ>?i)m>l+FIvGr#;#7 z&4{8tRF7pzkd>{=^C=6NSt)a%!G#mrOB{OVT!xRUb;Dgl3%e^ggA%jmkgl>K41Y$r zoue;+6Tlg5<-=}0ZQV>|LUyOZ1;q=@mle$#OW&v;a$y|Ltm1xMJ8Z|MuW%l z(E~IdfjjM3Z)gZ53X6OCuw2?G^idLl&5c4)tgj_Xhnkh`RoH>mk#nwZG+i&TYNoz2{R2&(MO*4wZ=u7sNB?N_4Zc?6REMpwzB-Q_PKOCxY#(kvsR zhKkH9NM+Pr@O2TlV3Omx|b|Mcm2 zr`+aItWTb%K?aLG^>htk4+Nm4#Nf+xcX}pBcA`Ze_^`P65Y&f-?%`HykB2lBsNjfm%uLej}Q(px~^> z1;(+4=F^o86HHa|xXPz6m5U=W)irz_zgLO#)f0}*OC*Okj%UT!r)P~=aGj7l{W)h) z%*e5@QY%XKj=hbK-~h+W{OWP_I!szs(z_@=xKb-*YXn>C3`BodwUsB=gmv$pcNW7A z&CzF01|XkFYA3X`fHbi711QWnYpBqWKS(w3VO5)T^t=$~6JrcgDa~ZgqbFcjdJ>YH z@#cry`}m&FA&HFA2CBT-trwKxKJ^h53Lh2mqB8NiHO(!IIoNq*E3o_gUZtYR&85Fo zl_UWE-?_A#8r~>>jNUR&`J!Mhj?%wQi-U(`Hd*?mL=GsEbcF*42_W$Cb}@J{@Ei_= zPKt}&AW%hI+VrkDU4>t_Rjcdk#^Nx2IR}=*CskAD9t%}d2jdC&%Sf)QzkiQY9drl(f+R_RxCq;AFRv&4OOn>@ zr6yIZq8TjS?tgp^9o+4?+Y%{Hb?Ob6-zGq*&iGhi%eYgh4B204s!Qn~>6gW*@oTq@ z#zTY#B3aS00$krXh!niIaDmq#3I|MPz}I&xU3EvkOjIOPT$o#r7}i>Bv9~s7s~os> z3*o*;o(#b7y7cw_NQ8js{)@LsH4{nXTV70anN38`inD!KcU0O~K30hPxA*q~GGjP8>)|gN z#>139c?e`|QQA$SPmYK)bJ_`#;@={~%AyqOHfg!kn*4c^LK|?P@lxgVMtXqN5~jTF zPb2g5^9qiN$30HNt1Il@#MCO-^~z#sBD1QwUUJw1KI+%Gd9!-D_;x$FUj157LSkx^ zs&P80Gdq+mB(f$q@ccEy&oq#1bA6=q8C>bevVVVU-|Z?%{C*c*-s@;8GCzEph$V^w z9%U4Ld0)D|ElAWI195ku$32)_pLZbrPkfqRT8Lxzv=EM548sARlgz=0tA%V#X*V=s zIDl?Z4au?^=cX@@JDBe=F%qR)Wo^KhaBQ)os4sQm#8GmqY$SBgV~yFZ)^eFqV!NL> zW4UUAzOmISMSMyK{uvbI&$HZ!H`#W@YoN1Y4d^E#(vF!kXmF7Q)0Ct&J$g6oluiU9 zxkd2M;8k2-G4$cx%naF_Ez;C()mkZF_tfU!n>+!^2fXm2ArcO8Q|`)N|YKJw%j4P&{jRily~j+Lwu zXGdT9I(7y~`*7oCGNUSx!(=;#-{>Y=R574)-hd<*V^C zxmRo>g*wgYJxBsqAhV~7PupRH)lukgRK{3WWJhdu@g>cywKyoJUKKE?)pp-ocNSGF z`B{p+f9CG{TM(lJoS3Ior4`Z72WX>v#k~!~b*En5l%+iYb^u~RkIe5d0M_Ba61HE7 zWwfHYYV@G(P*tNJ2f9M~E0ieW7^GMw-Y?-Ue3`J@8?w!Tiu$TC%1z$piLDJ$cg=hF zOo<~+k|Wam|3nfVEm(8WZE`pOrLH=b7Bsd=3_G2D9o6M6_=NT)jiZDgo;G!pT`cW+ z_ww7XBD0@L5aN$5W8j;4r9j+pbmieTy}CPnv^yQ@8hWe``$PQ22)R<2C@2TshsfrD zXhAuNPci#w$Ul+;H+=!X4Y<{;`n_-ivXau@={FJ`A=UTViTYOK#do0bRe!wvgJ3^| zkX5X1Hdxc6paw%h1ce43C{(IzK z_=o|d7k{#=(IF8(zf6EM=%rwP;1DRxb>$2PA}2lysV?(ZgxM;W85+xsysz~K>8-1W zmd8nj-Y}l;jM)^Z}D7;WIm77?Zdd@sK!j7 zzb2J;VNH6INQS)%)%>$(_2&@4EIv{bq{w z`A9ur4=QUWL|Uq<<;fJz4(HjGALvHn9~P5&NRfT;JL19k@W|_hp~IS@lB1|{w5z3J z;YR4;b*e{9ba=0)RoRyl470@~AF4Y&1@}fnxQ+}MVS~yQ`_ETMdT5JvUjrzg&Henx z>n>nv2jaWAQR7+;m0+GETkJ7YEM{lYSqIc*9{a3tuhx6(sYpdk{gdY+QQS47Y?U`^ z)iFElhM8|z@H@^6V7=g9ahAaoZxDY7rDe3_VJ$Gihr;7+1U_Q&$rtPZSqlrM6kE>`ogm zk8!2n9bK>}&Ai(hBXot7n$G1Ibf%{b$zaT>tf(5YNtH^BQW&l_<}rwi{DMMbEfkH> zi5+zPLUhF@H)Mydv9=;yFenkTd#5)5#fN=xwP#g|jQ%=sJ7l(4S@u8zlo+1iOLt|U z2tp}rZztNl!|{|(=s-G&m;4&mpslN{ynT5A?b*Ht8%c=On;0sWvlM{;r`af&`*;lcX-(xx?^Kv*BFN z0B>e`&QM@poI~D`*$Jmv(mM7g1eZtGKi26dJ+Xcm>q(p&tHL+6;=*f| z?B5Wf&tvqkqHzq?S;c$U>5% z4&F?hsD?a%1F0n!6VicjU`1<0bi0@88qi94hWC?w**bskRkUx0kqwc)@|j_q*ZgdIfnl|CL0L|gyMHy|H5!)Bx_fjKyU z-}UQ!hkt?NZVba~z5@q7w`PGCQ;lJ=A10k`F402_wQS{Q_|0X)1`4r}0uua-SFE1< zw_~@~3@NxOD#dt|CNpLGz#c^W1sa98w>Ne`=Img*)Vr$>vb4znuo5i;;ABlSMDCak ziL5qPD8d0@1D+b=^`y672j8+#`GP{Cm6$` z2lfx)0F9Qx2{_BPNB`0??Jq+ntbDD8`3ca&u(J`QvJpzVi@=8d2^?sxXoiMK3sY^P z(K&7=f`6gD^l$94idkN`MBPaH%7dU;RNm2ZeK;VNf}q4rL?Y{mn;bD5d2DkI==v|* zJ3|oMCfe5feKh0<%lorzXz{b#(pb4@sLv>Wy3M8)!fvxkQad2X(<3s>3q3_F=6*%E zaHe2005YYcmsG!|{K(WdsCn;7*--o&SLgt|3V&V zN%E*2$`RkcvMp~TGg|o74-~$cxF1~j!*Kl&B!ocx=0kp{GxT@!93Jw+BK;Pd{5LSF z8Na!lHRS+A_@Fl2yxob5NWq)wH2R9l)Yb;`_UBg-z@TAA888+xs0}U_vJibH%9su! zmVVEw!vVJbnkzec_-@g%IoYG#3-1*iuqV+0Pd<`UTMg(UK33||&e+V)+=$b2;W@Ow z)oF0*g2v+8(*w0xi74lJZe>kRux0+ih)8_=tzY7CwvQlX^z0f7RNJ>uZ;FCSt~znc zhuAS!KB)6!q~`5))E)D?%|i*o{kdTOBQ4M=WXv_b}GIA}hp}M#MtF!G3BD2QKX5Wrz|R zZjfm?uS(xD$Xo4m&PY{~fKR@&TXEbPor2NjoneC17~pSY?E@ z*g`Re(>_78_CB<@`4zJ0t?*Tmg=JwHrLEVyzU*+ok_DCO{P1(cIkwz=*x;d3QSKMK z!9Fms8_Y?I0)sGfz=2}_tbb(hCy?0>ky0hT@FWtCT{`K@~Cnd9A0t7Xy z&2kDG&5SCCX-7vk=^U#KSqm-M(Y5X+SIK-jcxJV!7dz`98k$_H?V; zWom3bX#YmRT%r2wcm2WVRRmG-G~pO%QIOIiC~vXcq~}MyHj0yB-8s}~6_r`qqy9sD zPA3$my-oqV4xnR!svS_dSrL`RQY#{KiJ72x}Xf zmzqnynmO!i_z$it`#*`Sgmw~#_`Q5$2M2hC*@JStJB*4A?;uE`NU?X~eR48t4qA-{ zWmrUoDpF2;dW0|H;?nAc67IFdU|t;bu!Mf9K{0zFoTgs7>@6IqK#IQqBFTbEo6sTa zQ1fl|JXyWI#hg33evTuk;zFy0tsj;|jXptc`= zYMe-W9D|4J%{|t*#C7%9Cb4#X*Yg2!#5HFSgDCQ{6y<;+o%%?{*OQd{LrSmX!Y2q` zb8O9sk%+7p85C>n?YVd8>aiz4jif&;o@WJ>6t#2znA^ zDX`SDsd%veY7gH>dz_}B`iRSi+4Rg_LPk1?Dxp#5$rlgKMi>4sjTnZ87cZ1ng&#U@ zYr+B4g@!|hs+wqYt}v-fd9Mlibh|RDk1OUkXTP|b(c3r(3rl&h7E{+(hOEuCNA~;6 z%(_|7+=FTME$G{l+OHLzVajhVk6Gxy-s3t)R8p1*NpzGXcByZoV|hE=L=wIkL79#d zW<^=RshG#Y#6}xIW_Z{`j1qc( z4S)W`ku348s-y?G>Cd&xZ}rO`*Y`BIX&m@kgmAcf!!8}Mc)Ve2jVBGtw}AxAz7#r= zM&(0YrWKpI+>cfsDT5*wqxa*&;D8Z37||eP4hPiW!0BA`32LDQrF9k@D8e>n)8%O{ zQVP0K8iM(NzvMz0V51)qIf8|+h+c?W>v{Q?4RV+LgMWKJbL$Yduzv$wu>%Lzt6>7* zPZ7Iqd80B}pw( z(^-0F$`x#D(@~!x_l3iOdJ+`wMoDf7W=nb_WjEXF@&(wlh${pt0aSL?2)bp$E<~4f z3Dhndq)!tP;lLkXO3xscwCj0rph@|wmL!3%5%que0Ugqmdf8=p<}1$7B1gK$o~IgS z)S1GZPM+athlyo~NioiG2priA-0Tru&#t~cL)73T$!HOiid#5Gw1^!NsOq^i!GZV- zl4G`ow2Q#MeN38p{{kH8`s1M=B={i(KNR7IE%;#$e|Ur+PEqv-3I02gfPS#t&NqmG zoZzWAYSb*QoF3J+3wZJdV$CogmtQ2EsVtTe!YqN6hKVTQWM_gWL#ZxVZFNP*ny)<_ zuaTJPKOss>jMfXMU(gVn2_}?J5sL{!L>MV1H*^6mM&zG(Psf-AwZ=Q&+TYflof~jx z3}h%eyGhH;u{teAtUh01i`y>nB(ZWLJl*o>UOkB3%YpQ+}vnsg8`?e3;HjEejk^h6_gMrZU>uSaL+D*HOE ziEB@9>E)|U9g+J7r*rMfIB8fPrMTYIYjVyKnbExK&9}1e64a0OaW8n5^M-q@EPCCMzDT#b&C*+(@qO&Sp0C%ViZ;OlX?8 zT%3Y-+b#D3h7`CpMxh)Zbhu|FFnwOrlv`HI`(wGx_J+`6Wqx(}DK+6(?@c4PWZUYi z=M92OIAA;q9sEGyBVAJwy+@(fsc-#`C5En-K*HxP8gQ&^XeRHIaA`~I_g-CK@pRL%UwxYp2P9FKj7yX;ajD0o8G-2ubG_Crqm`MDmPoT3qL=a1M3WNhwZG1@wNy7MS_ zoGp2l8aUW}WO~WTPwS47Pl!cHJ(@bO=U}Bz#q=0!cwV4$Scb@1eNbedAJv~9HQYv6 ziLBmNZ&I`3qwNA4QFR>poR(stMxbIlW2=!k&8w(Uw4`zS5}Jn5Q|2Px{?u(<+2{^K z%n#Z10XKqYnpfv0Nm_a0AiNK-EjhcRP3w2wZrSfHqv%aA5NBI2icHTroH54^OiCr=`j!napfK1Oqd zFVhuyEKtX6@e+oQVF2wKO&n_&sU#Y6C>rU>3g0_|Y&v?r*SRa4Ai;|^v^U6(esMvQ zc;}e`x!Lf!0J^&`=km$)<2;D0$NLy$r5rJ&RzdM0v=H~4{M;@4A;Q?xqW-wuD)T@K zSCaKW;J{1R7uz*XkM6W)WN2Dbk3#Ec%`ru~8|E=0vz^kjZQUK1%bVnu$#4&R&H zX9A}zdx$=St%OQ$d~Y|qB9PWzQ04Ad3lQc_N;mU^zVOCvQH^0C@oWD&^SkADeOc{8 ztH4%$d{{!YdInT1$Q-3sbm5X#{gbC#puW4i;O)m%zUs;ms*3#kMOv4VvvC8Q!NjiJ z1}ovXD>g)vTpKJ+)85|pR!9lyxX#X``4&$(YB)$Plu3s2Q1NusrfjU*F=_7-;dRip zt1FoMc(WSYIay?>@8=N> z8r6S$oZi5Yjgm|~OPr78h03uWo=JG)Gq_dSa<2r5ggvPC#plq%MkTm86gb7f8;`B>L%&0os6%sH~#pzMOO!_x>!0`$;sN2VE3J-YsmaZ-BFPkzX8-gPBCVx0+)GLIB5oVeO;L^VEV1 z^}P2tVgHM_IC8~gW|&PD-v+;XVWQ@n4qi{`f}u2j)pTk4wDu&e;ncV{V*Xjls_OOc zw^Yv%QA4UH)mI!u&$%@74tZZK{qJ+q09zYhtRp%kU+%*Q{s5=idxgfiCwn!d3C+7+ z{{YjZf)K&HXTght-%@Vhz2ef;+Fu|22g1^S8tl85$V*CH*;al`@COBd$lwnp`PFLu zFf%_4^>5DS{|Qf`KBDRRl0xZGkVNj${di^^^M}8CVwEFlss(rB{EkPv?BF3pgYJHr zx|`-ZIPlG#OMiPT$2SM}VwdXrjNwXw>KGz=wWI1j%W{SL%|UDY?1HTzCJ0wQ3*`{3`AYvq`9`HJ39R?NssQhcU|GY3o0nXe{+Bm6jDZv zDpn+3)6!cE>k&>X@utn+V$L`oOYC|QG;*~OX+;0=Jj_2Y>O}MsQJ*bFq`A@?3BLQR zP;ERZrQrdd)Icn$bsuO4Vu;)s4&JguNbcvmmFm|BqE31sKI51FLtu_5r(SLtAA=1g zehs?+2)>6^4eF&qkMi4?IM5ad*LWz|$BW#;cvTw52Ovh9+C=J4A&<^HBLL11yMwZ= zSk7tU>Wo>ZFhmvkekK}ggnC9pu_M9PkQt>z0@fFj9U0R?_}$deGSEq+SE!QeU3TPF z`MF;c98a#T^so!&3||WgjH1?s+?A%AGL4iX2uIo+cTw6XO8*s5~@Q!uls?f0vqz`+%BgCl05q(p@O4z&TjpLoI5oN1q4sAti`NFS2 z%iQhgNe3-oJeErD#DwySKTbrH;`PDrYAH&t-NES_T-r#B17O|ev5J~X%wuG+>Pj>}IzcII=x(PExtj8_q7vE4 zIC;_Be415$7eNPb=kYslyQ0)BOfqOC59)e9_auo>uFD}B6A*p%8}@pYpKON7z-ScD zW*M4>EmMz>y>QZ#`a{#C3?hngZOXi}n&OvaS(+wks|6~eT6u4w$UlOeiFfYoS}sN- zXDnioA56el8kH_d)gp4C{L{lmj!XHK*lfOhU0{|tPsl{No!#@icI)&#a?X_cbBBm} zGql`i&nc-V%tl5|D|u2CA4}DZp|TQ~==2b)eMr*4e_yNKP}YmG%(LoQecBiy znbEMXR(D7d(DY$@SwHBCGP*8tZ30k8Yv>2NUTgP^?!$rVt*a6|+o9#$yN9zyv6TZ^ zH`&h$9JZPApRP&a?_YEqCgZ;}i3ZK+gAIe5;$d~7V<)7{gI0CpM*NO$eMwnY?gInu zZ%pjNdcuXvo-8?tsNcQA`YO46aWSzV--f93T<;Jksi22w8Y&8UCRE^t>EbE~w6+nd z4*`Me`_8g9#hP_s{p`!sbV(<@_1Es0hV~ZajZM+>WZU}suQRJ(>b0$LnG_bT4_Glj z5RdSSMRju3Q?xZE<(%#E@pa~gRdR>WRe1DH97@x+c)u{YrTddjR=3Q$UurHwOAST) z4Iln2iDTNSZ29?HclEq$;}Ebhefl!F$I84-KUc6<-|vxNDTFAo{XSskU}1sp3aTuE<1A7s@QRhOb||^mNls)!7!vXce*!LpOD*41-vw^aZP1pl{(S3 z${sc{!N~>Zd4W~Zv>KcecUM&P9uwROiDK>j5Srtn$rG)gE{uC0mqK{%y8YZ$G7nV$ zTreNSioe>v#oHh{;H#kDlHUcIlBY=Xq-~h={5R>+%4pcTQlE6Iedty>k&`F}0fleL zP|p!T=sD^>{B%o-D6AzaRW^5a+vr~Pp*p0EZfBy3mnSZCggf!EKzBjo3X7I9`@Y~4 z6Gn!cI5NoE9v5I^Z%o?@1B8IRGQMrYyu6J^xOzH~;^`}#&gzKj@j;bV@J$m!q*2M33W`o7mYiF{pAH0Xz<_DHX>Bq%znjttVF=<#?HxVZBi)E5$p>DfKcd z_?~X*1%jg6PFC5fMsihs`H~ z@z&=#oh_oe`aY0*{(^3g&FA*AE&?NOEmXGMwqEkMPF#g!-7@2Co?xf@6M?DJ!+{l_ zxj3p5xT1S^sGL|o?&Slo&Yh(BjVDjfZ~RQ!M`IhsD7uGtvmFb%gtNzw#R*rli~2Df zk!Qp#IQDdPhZ2W^IkCVD7vkjP>oV?&N^n4YjIFXB5%=DinaZq|F~Q4tQq6>RS>DC; zj$as~69*et61<&z;jgU?t8zRMmIyg4;?aLUQN6apo07Y6ZzjoFD0aa~9Fi_#VEVdC zqKksaQU7k`2QaA31M-T?Q!iyO)om?YxHQZ5!6Yi%byqKzCx?Nkcxx_QAD9`2*jL70 zy?J4<$52f4Nuan)c;Y8_3N`uh@d}S7H!m~EfU%Bq9tOVqk5k%@_`2jao~weLb2q|R z3;jvVQ^~-5#m}Q?Ljn%ONmSZH4RPsdSEEqn< zDixEH^T$s=%f$^E)S#ZJrqHQYUb=eo75dl}VHiq2d}6s*tL2rUrRCwIyf^+rjlhiN zkSng>TM6#oGq6$GT6j*#&_toW>d0CZQM^`28{1hi-n38gGKPw;Hui?3_i0s%NZHcR zO;EktdWHS%-kyB@q}RIRroe@1JPVQ?`C+towl7sYlLW<=cFLXk8yne z{(b%o+geqtcWErM79?L$_h7fXikVJGD`5pUgDvisxmsHVuI@d2F?6eU2$P9;TE-2H zr6c6vdAT-lz@e{C(MY%|pj47CzJ%#fF)ms7%qXzV-!7Qsp-x3I&!Wz~qm~PF$9eZn zLj~URbI8EX(e`7->ax1PS=|QbcWXGW7dT9)TuFF}Cs3I99K=OSK8u!&ZCe-9FRhNR z4klrFs#h>Of=JuU3FRuxojL3f6leopvWuf0>rzs{M&$MFAFz7tjk7)EmJe(=djIfU z@vYaL8)u7qR-$ZPeD|Eta!(PPoXyHME3{K&i)|q}Z{5+krA8qXH-%+7u{vq z-(~FxN~56V5WBvseA6gtWiN20;xqOL#QS;(pFVEHa4E{e@96m}vhuciQjpKYarGBd zH&{dS0L58M{^P=p34!do?oy+fE@#qiz@#|+B_FL7+SqvSIurvA&>pvmp53a11HP}-@^aMKXAckbkrjOjwnm8hbeuWuwLjGl~~zQJ4%wV0S# zrDGCS8gbSWEcmoCz8Ys;yjz)st>h*2(37+;>lH~UHKAW*(DO1Hl-O2O#F2dOro@+O zPK9kXDo5B(CTeRNd?ifG>!*@5di9w&YJR$*k=m7QP}qzJQ?5>^1xvR3phJ3dQdm}9e-XOm#b;`yzZ5g7w zU_)+pQ|v?2)mt1u%>`7O-F$kj>z}i5x}ZM3QOwrXK|0vT-5_AV!*dkIgSjaQsb{W8 z_{6Bj6OKC&xIL1Y*7+>{?6jk(IQjT7$eW^YSkj8Cu+={W+cQt0+WgNKwjoP-e2BA-I<6_}O|Y>>NfI|Jvck zco$^J{)se0WI9nv!lb= zCWx!tQc9CcYnFZt?sk~-<=gvfH({6`UWelukrQ%2J?te>whp8VfCl&`HA3s@a5jZC9>9^w|y0+Z5hMr zt6?u=(~c0bg9&ro&QmA5w(-S1$sPUWf5APwvf!s)Gt`E1$vzWGVN1UBk4Lq7AtUsv z=>D=6VOTNrnUOb_2JD6@{>1}VR{t0cpLrX zp2nM;DY}#RJ`1~Q7q-ddCrxI!5>q{dHX$tjI|VnBOl=Mu8)GY230`Pe^2N$MaIG+L zdNe4Y;YrF9@6Gkm5LD&b$MQlWg5_5KX7Vm=xRe;*S;3g9IgzCmlqQiXY6WZtnpfJL zH=b5^@Yo&Xm~^C4VrthjN<)iTnbPZ8>3sUeoJpucSkr5f9Os69#+!TfOgfv1FXG9h zbEjtXq;?TYMZ!>y(|bq*`WYc6HXBt3bJlA5v!9~dSYnvF?gwhC?M8|(zS3hgwVae# zExN~x;y}j{_Qheh;S{mKX4LtVyN@_fY5IXeauj)Crl=T52odxN?=>GhP(CcQ5|>lb zUg(2iR4~_wOU-!0ffj+-(VdvyX)A{&jUq0uV5u&82(#%^0>y}d+K3c3Cn3^>{>Bs8 zGl$;}%TUwN?JsAkisXxX_&{vs*E{rIhgYdC_TAxtA164BO3QfQE4Y$fpw)%1KYd|Aq% zD1~^LQLC}^v7FH&+U5X{4z~lwIF6xPE9N-Lk7xgZt3OMPF9;4iL>OIQLptb0b8JS< z@P3Q&M+e(s1@%{#>6&ok%L1h3}C9tGZ8>c#oZV@=MoUL<0Q}Hhzc2 zcs#fbhWE*u3HvH9BpPa;Q}W)tr;L5NGK$%DZv68x)|(` zS*;l-=A1HkQ(1iMtk|_z^mu+74j>~!L(=c;LgrT4K0>E{ zG_nu8)ccdHX4zV>+wmfOG&jF#t(>sjH?9406|ab#pdIQo)%_*BkvZ|-n*`9cuF*H@ z+`b%Z{zW2rUr-G@?rKdO%aqnu>ylc8*qXcHv`4q#g|$b^ZujInxTWx%+3FToT*UYlsT1ko8jk1kGJ!*M@~?2ZF!Dh zu7Hy_jdnKG9xAhgQIZ7mLNeR9as9pB=)F}2N4Tas|7;+rCbFT;5m1!$ z+5^}d?-$kQdXhh#hX6#sm`~ns=94RhM@Nl>>qGyJ*)*+QhZz zf4Hs8@5NT6upUNr@OWG8XCpBT2TV7~mcTm&6rZKaBo?d`Izw7xwZj1mRHV-@ebh%~ zM$N{u$6}N!^e| zM_Cf7eE72?ARv8^WZ_V{IiWQ{Y2ZlCYU}XY6i3`X)8VEJYN$yhC-zfN(~auk_X%zT zdY6OV37$iaj@Ccr4HB8W>O*0X74)R!bOQ3e*Xlo$?H8|1rRU@F&2I)Njye=JEL7TR zLn563{fd{Um)@$m#?Mc34XvL^o~7ZWd1mX(>OPKOn%8&p`qI(@$uco<;xJhM8w+*( zg6cr>G#~u4@!K*VEwqfyiW{6;u}`oJmK7v(agA7_joR=gOmk0HqS^5a7DIJ! z0==!Bq*^9@sAqw!tt0uGn?K#V_o3alZ!&O7tQRAyI|LAz|ez&k2dv1ykj@qZ@ zKpyH4u0VCvs*T}z+UOaXPFdRZu|)kaBDwm}rO`dNKE}fInN@vRhaysYV#5zoH_;T_ ziXH!FIQ(V>)vN`C7R-*_l8CPEI8@Hr1$FbIF?RL3Ab=3k)=4Ee=ReL@%+-?x-`Wk? zTvTTpl8HX^QGH^+nh=?Voi6R>`)2Q0{{0!3lNhXb2H!*Q$&j zyJxN_@VY7ySmp!pvKDEDWZk@2}=Xh#_r zl&GAt?i)D5?8xgdcXgX>$NUT5Ag8TF&BAxe`u#kAv7WzKx89I1e{V#7(+2R*L7pHJ zbJ+KQzJvdpG5F1~@8lKp{xkKdPk+IpJmbei|IGry`Ugct7yqx3(PA(n%M+QB4hM2L z!CZykX%?v0Pic8@Ak<>EtZOWBB!v*e)gUA`MdoO#Hg~qoA*OJY)*@?`x0HlTZ2yGY z^-5|8_F@qZG#9|QV(_ME4PStuQJG5BT^T?fTmIurQI) zSHHic@Pc&Vk1sR-42DYU827*AfxDHM?;P-N1e!+{CWUvRp@1lwGCmAT+AEQVbQ01J z?)^0@x7AJab2g5tDLn^b6W8bHLzINy9UU;My{3hg>o0JdsRa(`AQDoWO7F4qp7Un4 zI-?%y*+*ln)`m5737SXVUN1o$(eZv)vv~>ob3ld1rY)Cq`{3|}rz>@+=)9)Mw1(&` znq#G-s(h>m6<2j_ntcYS$`j;nZ&Ria*JquLf%FuOT4J5T=L@%Z1L4xy$I8kp6c(QD z!*={-NkQ_}w~^Bp^m%q63mHkWd$$zr`Wc0&(&gAn3=Z#6-rH z-T7GuO<}B;^OdP|SP_-x?qLZx@eW%UlWu4EO460jf#m*a$nJI^S*n z`awAK3avW#|3Ww#r|Kz)!}Av+;J{{Dsi~sPxfWO2=jL)iqVg9O3%jj|=R- z<^M!c6o|BTJtp2b36U9PM6+7%PFQ0&)n$dsJG6o=quznAZ?OaEzgh zhyy#Q5QWRrdBky|+WH2kHZ_7Y&othSPj_21uZO~c^HoHHTWB@(FbxK6{;F*(X>l4% zdaZ{>9fwFbMj^Bv+$ z+0$UO@%Jtyju&4!d1oBaG--%_@3v*=ZE4jS?I%`VuH;7nxxKHOh5NNPO3a>VB0sr*my_#(P=5=RyT~1@n=H1HK_5qiE2x2-p?jl7fIjOO(@2jo8+Mu&{qU#ml^Qp|=+hh%G6r!cdrM5O&2rc+g zDVI~~(k7@({&tW|cdB1Nb^l90t+sJp*qE=y8EygFI`tm|-KM&*r@B62E z0x`~E!*1_$nIAp+L%9gPQ|G!%=A>Ba&?oY&rZ)QRDdtqebP+fs~IL}%aW{a ziD^)ON73z9h=$7twRQ8c(t@*{mE4#*wmsxv-|-i@1Veu`klR~Z-JVT-v~I??TM2HT zDBc>>gxKrUERBYE^5g#T*dHpref~G4bq$32Gb6OP_g_>`>nv%Rl}Ok7j{F46!&HuV zef_s@^G*e2JFNF|PlKiq*|6lGf7{*u&8kRG82>Np`-5m{`dRn?!QNNLRkf{aFGWRA z!Ju0@B?P2Hq@`23)5Q`{8kT^dbO}g{bS#i=7D%^rgLH#5ELh8L>fQ?b+`Z4a=lt%y z-|v3k`GX%5=A2`W9`AUc=Y0kwxr?vl#UH_I7yBg*wj3-;L&|R;jiaO`g>-RL{@6*on$3ORC-LrvDgdEpA z-OPJ3{MMw8FZm&d|I>w1*)w8!&>4?BFXIJqwon0OEetK{d^+cO=#>crHouL%zn4np zZ-W1^Z`+vuRT9v>=UgJMr0 zN0Du)Qz(L{U(=79?zO)J&2PXigC!NP)7pZH>Y7s^&O{dc&o0xo^Vd=s0q$Qm&@QHi+34$gMWCx;=sKZ+D@?t+a;DI3^VY8-FRm8 zcka12$wLk9VzEgJI}NAxs?R{z`cF&tP3%{Un{%thGA#5i_O63{;wv}WVkgNCY)e}s z{H_%xO$LIGdAeO(5Fx%B6d%71#aV(KqMwP`yotVAA0>jWC`ka5Vf+wV)5L2J3=mbR z??;;H9d@5kA>+DtcWU(`iagc>!P7f7J#rJ~`M9_x`^`CE!&F@bN3Pbv(g~J%CFcb7lf#2h&BjQ)pM5ZdxYo&2V zMlHtl;yC*?S4tfUdpw!yFQ!Nb$Gst$n~JkeUcuwOKQd;i&V69NxeJ>qdldXQkhJ{@ zmLxh?XEDHb+?`lK0cZOyJ}U!5?Pqli83Y~3hr6+O%(Zb~=VJiCQ%TZQaDV7H=EOYmIoij#7!ZTZ`FSa(Ilgtz4j40@@ zbrsaICT#2ln2Qq9DHVz>O60NGP@(%?GEc--bSB`6%vc?Jx2>GEu;1`xQo;7d#~|>0 zafFRbHU~MciJDlIhsNEymJV%)%Im#d0C=ulJ7{=`&Fg>|>{)+3kNaW9Gm2YXTHcTP zz$Jtw#O@sJ#K-lwCnarim|xEE$6rtM&f1X8m_BCRLC@wTzr03NGrMfBzlNqnl%7P> zSa8)?3GJ>3=3CI*;$3g^#g$?c^{pU)*LXE(kycZFxqvA!+hbqINDy61m;V!yLr|)F zfTUUf5_>8H3b`(95lZ)Py;UukXF)-aT}9jCJ`>+6-{b-8=~@XaKe=?Lt(9Wtu1Z*l zj;l&!;v07xyNJn2IzP^F;;Lgvb5bq`tiL(n?hRwANCW?DsmT$nt36qDA1yhNjIte4 zMn#E-4bczSC$xmOAP(z7?#)8$DIOBn(M?HxmBlBa? zOPOd3)c5TK6<{<`L1~s{`1p84;Dp>^mP%&|Po*?oI%bg$l8E7<==~#2*0TMfr9>-- z10rLqN}Gu5?3VVT>0w|@A1`T>gts}yAZGuY{PsKXGnHh~b-l1$m##NuzMsdfF3Tlk zb=8zEr+^Dcu6tM69&0R`9lIv9aRZ=hVXUvi znKW5AtylJ#EF6tUxu+(T3hi5+-eKAIlgiu6p8(cByaTbCYwi@SRonOCg7x(}?lh2B z1AT^R_t%P*p7xoK_Kk8|np&K9w2#7v)oOg(UE^xxH#@q5Y4N4-yO?T4Ml3!xqep3= zG1`ae!lEMPDcvg%+|@PHb`4_>=p7qv%NBO#M0n`p%_F)QP5L-T_8DGK_rvf|COZq2 zH!~xLL*CYMNTPYUV#)$1yr60>tiq5`UFb|V`K)~2YJkzUm6BH7!67y^-u>1Hczn6s zvX2PpwkSoo;`JTuWQkd+A@S>IAQ4kW=Y90BJud7KW>jO8zKQpGm=6Ye6gRyN_=3xI z1LJ<&Xdyt&#g^J{w#y91jF~c+i6c|+$}&bBa6G~1stes?t1g3sHMK}9r{J_)ohKN0 z1khe%zx44UdQr2TL237fL=aa@o~W(8y}PZWW4iTC3xwSSb3}a%X}EORvBU!y7vD_=*w921P?vS}=W`J+^Ks^w6k2j)m0lud z8*26F2{i7Qn_uQLexGcKbcX7sfQ8q35R$~%xv}ZF5ThzO%8{cTcexA$P3tDFGQbq`nXq=64B0}z@3kVZ#lAK99wRJ;4Qm+ncEe7TLDZj}$;ADTnK zvDdaJzt+ZZM>faB66T-I>LI3lqH*NO#m zU{n^8xiLue{8kUw`YpVe3p8q+lRz{9j9c=uPHo>L@3!<0i$ub)7qaVb|5?6WJQ$M(`9T1xAwjfO?c9W+Yod;w> z0^&)ZJd%A>RZ#Ge&%Ih5&pu|Z$RFos0pqF|Et~3bplu81TEZ3en=R>U8e`(Q>~H#p znu!gGJo_)q7zwgr@vH#c`Qb^V8(;$Iy8;xXLjpuCEL&@BY(DDHj@X?^TDEmPijzqo zkap%>)>DrSCuQE#5TUW)0{gT$ccr{k@!G!hVA+=9UAsf3a&VcE0Q@a3^95eR2>(4f zVR<|$Ep0#6dod5C9R+N23+bt|3xaSAY_PI#&JX18sxk?fv3?XPTv=+&wk5niq zUe^&!T)jkAjfoeGO7borhwm>S-Ir+6oxF9+w=H+o7oH!&D~j0LhjK2a8kQEiO*u!* zU-G)za2o_7f|<_hYHxJoE5~ZPb}`QG3~j0SUS*NZ3NeD^Ng0M7zp8qKCqRcUBw5aAko;2DtVEiuF=8?5z@ z1F~Ry53~f=JHRZ}a-R}72oDTJBUkaM%jj941J<0x6 zxzJVsDj2>5a5WP%!*NrL>z>^5JGhRK*9t}7;xRvkl&=6Ai!7+cD8RCtAV2)7{OfWb z+Fah>VUZZe(eTTh6@6@NL)#Z-#NSx985tY__6#*P~y0p1C((WB#PLw6MPf zCLt%YD^mg1f6=hmy$(#b!WH0?mulmYg!RqVgTlpt!urxC_6Y($CwUN*bczJV5LDyT zDs>B*GzZ;1y%`mC>;ZUKSsS;B^>Lk2bgO)4`Kv})1e6#x#~2@X9NfnU=?Z)1q1@25 z0x-wG<2TGzi;i9k<{u<9r|(SYlg*LnNV+%@j^9vZeI*_o|-tWD3$GHG1PM?R`M z<3t)|guC2o6`D<20(Mox-~G@-KwizWsKe!@>8J-(KFqmBs~5%=3aE%xRQ8{;WWdrE zCS+*?vgF&#ustb1V%C|1f=8M$=(4!r^9so1nGS^wIgO60KJ$w5Zy>){hnRadGbP(3IhIyg4Elxd{GEf@fadO8>A~ILRGB}_hpukz zIp7!f4WZyOeddvti2cr5-u@^-36m%JHn63l*i~s#HMP>M$FCko9*gLFv1^G99syD5cVl)e5x&_Vx6}<`GlI0u6396; &?0*htKAByk0`Y55s-I=r#Y0Le` zMu5O+Wd&*pQ9{3n8^t#@K^vjGTrPRbL#4a=y0Xl-_;Z;E97LqlSt{(89r7gIuw~le zbzOkyK%*q>6vgltKHo%02|?Nu&MjK^hu8FZm=CW!U@W*%_3R4Tjk<`$LAxcb?aOfg z#34dfvyy^};$pL~+&;n~aow%EMupC=oyVvyNQKo|!Ezcw6>195l9A@QJKDnUzP%lc?fajs_ z1x1*#gfV5sA>R#F(!nhx1PRsNiOoyS1BU2kkCwGl?&gM}?}T>q_Q$v4RnAnlC-Z?E zU-nzSs8>fTCTjHAaAgHXx$NC+fHEsNC+kfJv1Q&Y)p_YKmoB;m9N%U>`tEu#3CapJ~>{tejaNvf|%T!-8n)q4P;mf2&IP25~MZ&jO zIm>2KV$wA^603UZs#xLsn4^T4DJzv#C*KLhQ4R-=T0%*Juu_3HG^G+!AKAFG2=oLQ zHTQzJ2?X90uRVJ0A{_ORUbiDCgJ6}7&DB7$7$9zAPa~bt@6HUt`?#RDUsjfu>Z?eN ziA!^)nj?czSFuuG&Tf?qw$TJs)?Cxo6P7L0SH`N}BOucDFXM zABD-1)zYxVUh?$UvKhna-HL`MPH|e*B}r;0D&XR;8?|W%^s{miU6e9XMyjP80WVXb z50U)3Lq>i3I0N|*Lm}N9?THCVOP1#2cj*JcSD1V$o|=R?vBpfC_j@UrD zb@R384&@oS-?Oedkq#~_1r{=XWBco76LPJAoHQ}DBF~%*n^!xEZ@e&cHyJkiswJB} zCCdYX7*^7>l9(^q*P$`m_Tw%W965@;R)|&zkm&Dgf9hP?VdeFp<#8SxlqhOkqHlfH z3HE%PhwAyxB&DY+$L>xjI#onVMP_)-a3q{{P{(p?3ciH6@9(WRxc-!;e`CMEm1#sv zN0cd-z1U2W(fCc|RawR)X6dB3Ej)BDIcs&-8ysz10ae-+T=0)N9nKINx}eAMGgw`{ z_mN$>DI}Q`@!lgXGe|sQ;sE;MfJ?;{M*VfAtyFIl)1nEC>(J(>S9g{)Kc28m)>VRq zZb)d9U&Zg*ITR(n$!5;NxMO9(d+i%P=-6Nj^oum z4F_%Sa90=Rzr$PK*khsWL-!h&De$6uC%@ff;|~K2R|+i6n^-Pi8I4o(SB@Sa-F){? zp~TR7fkXKV0t%*CE!G!Hy0ctuqF1L^G#+6?uh_j(?Pm=yO+mpnmAE??G%$C=F2D~^ z_7o4zyx{n1!Vc7|`I0eED-mX!YH^t5NUiZvbLF7xSu3gcq#S{r*u`s4)dT>;YpRB5 zNvw|*T-)WCHqrxGB0S9k_eOV8haXW9`%wem&2YWO``|b#ROlE_W0HVB!L}qMi&z5t zDYlHPtQ%Y#Wh#^r2{qGgnj=rr9iSbZy`ABr9W-w_?#FLL61Ed>VEq2ZuFBq|#*^>i z4Y`lCawGf%SXtH?sM*1#PEjnLZ12NfFF8M*E0fu)D3+sLoY|!7TTe@vq_zYcvM~|- z1mPSq^Ir~na1Q!7hde33e4jss53e ze-%a5w65L=qR_Rxhycd%kj}Jxb=V07x zBK`Ml=4(mf{V& zi2F2Nh-p+Fr^;IdcRrKg0ECqjtsMKGn%eC=(dJKLW$tC5Gn`0(zY3R3o>$fqbp4Q@ z28VS+A6HgK$ZxX*EzC#54EgIx8(aN1(=SCVUd^t!-1-Fzl)2`Cm?C&SDLv!M>73#i z876XXoIPUo8K`ajvVn#=aenK3=NzF?4PVN=HE)EGTxdzt@ zVa0%sq?pF}O^>GPQA~}nCw|#~h?~v$!#?8tJ5SnlIW6(cV&-uX!-(H8j9 zM7!QCjiO_r+Grio;;6tx=L}nOIVhWX;wE~ph&Ee=3>X=@Tq0N=H#53a_6v*uQ%A6 zAA8%#cnLk@oeXx@Xt*;iH{;GBC-XdU8y4EZNJSA=a9CQHMY!gbvH}23=XPKrXZyAO zT2HX-c;=)k^e^_JmKVqh?QfJJ9ln7^iHfX-lI?GN68YE}jvHY+QuhT+RW_iewcc<_ zhetJcn{^-RhkA}M`8_~)zrvH?caERVa3gV6?kTRTVD)Z2Wi?f&=co=EBbrzB4hD&a z%nvM74J;{FJeaH3j$q}UY>$#_vQzWM5=GC%iLE5jO^s;?(mNEd9Jt4MRKmbH8dOq} zIT(1VQ?)_u46h!!a0xgm&1|cwvJ+o;)S?t!QBIv0^N?t@V%w zA${^P%xTiruW{aXpNH6p9#HIDomZnjy`L&ca+O7T#|8+mZC_tBU?Y8((D}@E_m1+1 zVO`-b`A5QGIvuW1bzY@R>!7To*!DG*V7U-WOOO}dn-m!w8?ow*lg2~d`qpNK*pdxY zDUR`q3k5zVo>$J~u+u3pz zNmD)RsLeh^e?kb1Md;V05RR$E3_PBF5azK~Y*>09iZb=J4W+ot= zt2L!yYVU4mR6YE%Fs|#VkL=4rv82rnMv;}k;X-xJMBH8)U!KIKCsfrB+G2>AczN$( z*$?ckY-n??G&OTWhu)}Br!nQPDFSM?t>0tqSuK|EHS{+nPp3Y@a+9?Bw@LzFHi+&W z{x~0hsl3U%#hR(6ioI8Em0z$MukTi%FeY|UYU=9w5kj14bIO#WH`!({Sp2GeX3_7S zsg#*vu!)~0RpJ#{hE@=nSM@5KSdd8nB7K7ein3-ft#XjnklUUaFTH(ZMylm)$Re)F zYwFr(C()qm#=J|#(>SZwa$B;eblRwId=SyPY)9#=`FLhfx{hT5#Dk(>DjEPtqpQ)h zv#V1I?4KoBBW$T3nvmj&1YQbgo2e(DcH~?O!M4O#j-dqtASei~i(JHK#RKsWYesB+ zo>ztHFLo>gQYAsc**Z7n(9e~`5p*?%5w-$1ITmd}4h2kQQ`38CnBnFp5;W#Jl zbwf_}re`EKtGy3vP5z0GkXP={@#wZWm6@)rgi0!kqVI5) zd?+ct?^v5GPP>5mdb&IXpCV7VXF9>FZ)lPF;}7EDlZM@t7)LCP5iN!X`G>EUB=)~Q zxv1L^d4T6Hw}zZK?yZ4V3-j?tKU;A3`4Hjq4dmqU9HPI4-5vagl%mg4qE9tbB{ahn zluo~Eky-mY(-Y?>`-{Q;-rRz_-=Ex}|M6Lx4o&KU@{>WmKf50#Pr{ozg>_SZVa-ui`OM=svTh#Go^+ON+FE+c$#(O-Zs^X2iMT8JY&}ke#~^g&0fE!L_x7f(br%8 zDgdcJ3r!G;!AHOwzk&GNLH`+oCsyzi0|zIWi*;xfc04N+F0m0Chwv$H6cW&s#Z@$q zzwE%%eM^?S?^g(gI!6#Ua!#{5TW=Hi%30iv(6lRZS$Jz4x~+EQPh%$(XvkM0d$bXc z{;9V}-a^w!_Ti}t=L2R^&gbzQG5l91mD(f`hX22O%cShVotB06-t|^$%A4|7t`Soy z=V5<}Gm>T`NcM`O%kFQCSYkUK_A~3b25b%@f&+5%o%g}uwm_`R5 zaFDprpSzB+f#(Hgt^*sDOdznV@bO=tE7Jb8p6-(iyPzC!EZD`N>|YW@&<^Bt)?;{H z@?*$;)}C-*((k`>UmBOlx?CUJS`V1sYyg%W>?3tI_-YceUpL5pD2u+t_=68m8-ILB zQ|>`v0Gnv_ZSGPRZlCxl45%Y5QrUe`Mq zwOP>Zt?SDSYsu7^_t)gQ#uS&e@xH1oYIeetQ>mSBu1BtpB&4}|SP`qT8D=7-E5G!l zAaU?&L$wT52WxgF76u8Hi&>VKz!Y&`NrFe8cBw4+&F-?B$h1+@z=bPnahEn<@Cw9V zU%Hr7(zk^eKLtcSaQR`vFyJ(`15Bn)0o(^~Xt!}|19J2xrN(sR9Br8%k0f=gu_rGr zV#@B%E#R)~XFF<8%5>KQVH7t37Ah!dr;i-5L5_OG^ga)Y(h>t$ZGeybbJKI&rZ-2y zoe$~&ooa*Uf6MCrXa6QZygq#uhbqt5wF<^QI(~I4)I?Df;SVsdQ4i&SKBID6B8h$K z_WkSl$NuZDzk2NYLz_>6lYo6C>3~h%{o=S6YUP7Zndfg!>T8SMCA`L*ok3Pkn>wkJ zo?}0M6uV4(A}dPcm1P|{LA+>#-pPB4dK*VL!tD8$<0GSlD7v?7WqA-u7faLICzU~l zeM67Rc4I`J&0iFu;@uMr;uy0YA2IeFLoDQ(6~CP_lj!6K1b+iPTcScEQ32E<;q%mv zz}8jI77v!A-xJ`#zVk3=p^bVIJ$Q9nZ2IeAcRZdVBi;@;PMD3d}jDLcZVh4YWs{2Mjy( zO`haaNcA#6A*uFOA1I-(*3axA%kl8SzPU2g`{|x``z@(}8V7Srbio!qi5q+!T7&ve zN}H3N#^zT0o1huRutH)sa%*SZTOzkYznJuhoaHbTJv7YiyY9u&{ClD$njKcGmevj+s+>`l|$kEL)s_us9wD zSu)qQzj4BJO*j`C)um>PF-g(b9BZVb_1>L+#NId1{a%1zkqi*;MdW~r!diWxcxgNf z<9eFr#jEw`HFjfDA-PjligM{|_FCEnO^wdoy{n0+!Ox8Xnc;%#CnCi0^GSB@7HF|$ z)Z>p7l)aDDkgO=7JmCq2#la+?9mxPFzFauc!VKzuIQ@Q3gc zkc6b^THdI3F`CrZZ8GO7h?0(-+35%CTpXRNz+}Tn-$T_vTV)Za!kz1fK$k%+u4!B3 z!UA_&?6XDuiEUNxP?^S&`YGS{7l#k97N-vo9m5=ZNJMEOd#{Q&TP+r{G?er?Hc-w2PQjp-%N@Ib~Y`SR=Y(}Vg3|okMW)g45xO7Q09(c_EO&qQTT|!*iHoK1nH1<1RQ$Unm1d zS_p=_huG^CbLQG579*096)$oo91p!98u58sQYg#u8;BFGINw`4y#W2ZpUw0tq?s=s zMO|9x!;)H1oj5zj&^P)ugs1@Bo@bX=Peg?8WeXv%i)3I)<{l{#2DNt1+PHIG;9|37 z_n_M)hFf&hNi}t7Bt&|>00#;zHrl#}V2lcLzCwdCw&YJ)I__LlN0Uq$!U zuoeTtz3Bx`X;h?)ii54QL@A5!m@`h@VS=7%S-ffDVU^A0lJ z3zB;M?UYdj=J*4+KVF-|cAvF-g0Bo4EtLqr3n)CO=S8;zM01SJlp zLRA9}(9f4GGtTaqpTdV9egnlJR&koYfwYpukPLgjUof^_yl{!kH+6Rja6kgiysb58 z5Qo1!!=`WQP^Y@N-L*EVuzuI5mL+L%oIY7Y?x~scA(udZxgfldD!e}?jJ&ELs&jn7 z_i8Jr+c(he)EwZz6h0aj)RMPZo{ChvZ1x;SLl}rl=y44>0a|ZP5@4zcZVGP!{|YkQ zcP2ubp^J(GZc^dXLx6Gy??IhUrgz^NeaPVNq(H6_>i+Kp{@_BnCYn)Hz zFIGkz5g8Crhc_msy$grlk=14QNpA0Umfu~J7#;)S$`XNvV%jKT;~BKa3FyNGngi;> z>bu;Cp0J{Wa^a=wA2HHrHGjqItfDM3w|3z7Bx& z_=&XgwS{mERRxx4dy?x53VU3*xJ5oQ?S_P7Zp~%qc(WFN;I*3cY9h5er`Loe{@yc^ zgVhcHosVS7^J829^j>}wYPnUH2A)$Hphw@yLFk{l>p;tsy0X(~d0Wj@0!<0BkW5;k ziy@5c8C-<+_uqd2P>Lj!>jZQfm~M!KpvPObz&*??ehB=hIV7j`->?69-TrT=I%7p(V*?&W+Ct~8DMP&^h@>?g zZ!q12UbM7!QJrA5CmO`rFhaiCZn~D!nk~Du$g?i|3Fe-MeY^!60mek+?`OEVWtZ}% zP^P)(Y&r-j0l4RabKj5sGFFmZoicSdZyo(PDwTfD3%OSGh_ZM89k<|60lQEB;Y>G= zkL6v-x3h7Sv{hbH7Whc-R{8yOs&V{IFetp*f@nc}1IhTJJ`JlB#I_&c#*UeeQ-eSI zzk}vN^Y=28tbNuu0~L-Q73&xDSRE8fMN|reur!7+n4G-sWYz(<5C|xNXGpO=vqqTJ z!A5E>XN38^yOG?+EX}i)SfjvI_Fd5DI3ZU#K)TRdy?kKSFMM<6;^Ph`@H4*KF=J9B z=7cST*@aHVl2L8BQ$1`Y!{cl;&mN7JL2kr*Cy8n8DVZ=8VUeRRD_SW{H<@(U;^cFh z_e4Ck8J$pj0M?nGzufC{<c-cb+`1b&LV<3cwt#D%}`uA>~Oe|C$%{!qD2}ATM-m zsf}$y`cB@=?#0#mH&0JT>1^j0bH0I|T9K80M=6f7g-f}xwZ8+dr)rV~Nk+&Tp@p2D z>lVX1)X0D!_&fZ(tqMIW@bBVC%NBXAC&r5VrQcy^K;uaXS&->6{sSSJ%{;ijPBxWf zpZwuJk&*K@v*Y=!X6CVOZqDqaTR7at7$v;)W&Q^|2oqBUp;P3s>Ld5k1%I?6dykM8U;v} zW<^T1*rmuTkEDsq+FA>yPtWeEbjb9E0N21dMOsQrnbtH94$-e*ch-G2tokI zHJ<%?&fleh1kX?=UFB9nF{X>DCO4fpt1=M{>*VUX-74ph@k-!GjFdIjkM2(#dCy_! ztANWXB)7JH-*jT(H?aLXEWeg>PGRT+AQ<7+397rzMu3Rbq=;ICFy2fnjXDnIApq>i zQFa;2h5WQ^oFSo;?!p6Bnsh-eH>$`M&|`!oD|IrBGpl7HX*&L#NY zT^se2CQ7TlAIW2I5W@q)^TaQJ1xWvxs1>%NYG2c7t)f`+iW(~w^GE;I)?#le&Va`R zqAnIYs@vuDTQ#*{#j8}bpW(B^8kKR>Z8%`+;7osx&K3~1vXw{S3GVkHQud3Fvi6~L zU_Jjy)X>h9gHqHjnOwMy!Q{&!cr zEov6Z4U<_&aF&px%EqChPw#g8i$Mj*?d1P&A5-t8?zdMig~VWf1F`GkstgLx)x)P1 zkk?gy7xppz8)D;sR@jHB0gdcVZwope8^E=GrhbN+{woK!{0^SlUAlNx@P_msVoRH0 zbPtkih_W%#Ev?~eVE7~y8CC7rqSdt+oo&6$MI2y&cr0fYaQ~jku9VSBvhrrBjbZ=2 z#q$nDd7LqSz+6=S2sx@qa+HWt}dPE`87=##0LA%O(Dug>1GD!Dw&Z*QA5IhRdM(?-m z!K}5*UTgS{p#UERzCx_#lGnnb$V~YzMW~IhQa6qPiLqsqd}V0{GAvUToRb^tuqG-H zHN2}USXqSHuU-@%k6e8pp789xUXeH^Hhe#G@(}{6MdH}7i-vuR*mBAVE1xc!slceA zBLv-c;dSy7Reb!gu{f^f6Pi&<;;N^>;$d{>4?rs5_Uw>?t`$QOH}ky83&?Mc`W{{M zr_aTD`TG$0rDyj~{*4AuZ-4pC&f%vK-}lxL&|w@DSV`hx7xA5!d8w!?Rd-Lxt7nt8 zYv(=y>uk=?-Eiv9{jmn&nD*a+QzJkB+6;_PGNy}m9v zYl$19ZO5NtOsGzQikz5TP>3YKl;LuY85$fjtoOfR9P-8W;%y0=LQf zI}rV+zK>8QQYTLw>3IyjglhK?^sws>0VKol`*uWq4}OFI9CmiXi-XFrm7jBTF4O6i z5oqAR2Y;qFn}5c7{%8KjWJSJnqY|)CSxqen`sRh( zLg{Mke1nCMOt`E*y z>YOjgY;Z8>PEkcG*IZF*?^L}#wTo&t*=JntBSne1^4&1cR)pG6=y*#y%i#Wmy1h1` zNlYF&3-@3hOCo=03Mh8D_HTO#u%zbe@7_ki(LyUKhsKzgj0LtQRzoR$CsZ3-N6lJ{ zR0C(jAp6%g7)q|xTI=q%+>|zb{_xhbxVC=4_?UQo%s}*yX6*!0CT?ZMZX_9ym+*I}c>~(`^4_l?jcwnEr zG!&9onuL#xM`JQ>-$5w<;k7K(SmhMqxnV6;HwXfLtDh*QCl5aQsYSUr!mecXpDK1z{5h1 zeUu?ar~8RV&8`NxxPzY;LS6Q{!@5mi^lJ;&5gJeTg*w9K`*KZdOVFcByAmCUmHb)f zkXQS%6*kp8>F&zJek`e#RdI^7mUpY(T*Qt_8?m|J-7AI0)1(I_wsusnd}Vpy)Udp( zKc*{bwS1)^_<@j)!Ph30c+yl`-S=N>153wVloyie#Y>lv8GCF|c-@cxNU?(@ntf1< z`4#!rXQtq3oI^=t^lhn2EQ2633f3~wZuVGtjw0#9Q}_%#T`Qi|p~?d~yccYYx+7>c zG<8i1jGA%Ola5S&WJ{G6I~ppbV-DZ?^wen^8&JxH>ew* zQ~e1Nhs>l>ZoVA0C*AfA4cT>D#TI|+*`H?f5(fkVJp;jTH#bc-(tN&)i>eq!;S8fT1{LcG7oif~hEu9dfSj;6Se)2lMa7FU3{?2kEs8{)o=u&IvID zQ#)Smy;ydmQc-&T%k`7zq=HO6Iom~_)4o!XaQe=#Og%@5RPP)f!{CrexXtP2+B9zq zPSh65T7xA^<1BCn&DL$@+!GSU@VfagI!hia7CQ5@lhuea`YG;WTDEt5R#~E4T1CRmCy0 z*+2v!<$l+ffZyij&t2rt-;9ZX+mHg#NALhtrq$XrvVrMN5dK5S8|Oz<%ikJ*{}oX! z`PYq6w*<*;Y!3+7lMXLi{b%7}Jb(Ihz>@!N&Hv%&;!OgBK=1P?E(`9x-(X{fKZAHI zEz;V^8V({h>COSay@N-MK4aWJwuc% z&Tyi%55ZCg*p@=G=WyxXb4ax8?)}SBqa%SE`ZD^AYbdwH)8SJq{UZ79rhKcx!Daxg z{)uLve@lKR55Ck5>4G+g{CWu@+v-+Q{ZG7MQNv2H09$-;9?3eZJjY027b#@#VU6N+ z*3jQwdawwe6JK#gXMwQ8|FjTw^Q1IMKy^R&IPzfSY=yzt(}9;D&#zH zmaw1;?TMd`1yFc0wc*p_u46#)#zjxGL%S35=MA;>v$z(&Y9OF*2TN{*N#OE5}d`IFxmwADoCHk;e?HyJ2Zu+cx&Klct>Q~m!ii4jvPx3$0 z81D_jWpBGg8A+eYv9O*M@>juCvqhh_Jzo|4{8st+XFHy&3}h~Uz^KB4!Fg>tSghGQtJ@|IW*I2?Lft^(H9YTyGl$Y&Oy%apXqv;HLR4!{~kdAo#!7+fd8J({*2x9e|I|LJddVZ zy8WC^&o2;ZeAY&~d?B{iKZidVUppW-Lp9OxJlOT{^~>YpH0{)V-4l5 z3|Mfrmq!-O&=a154b1$_?lInU@Q)4S>nwm!c z1FmlL+mSsCgJk8>Ezx;TiEKib@KSV_tS$lW_>?{s}kmzkSjZTHF zknRw6;aXw7*D^OIQ^eJ6)gPC9k3Z1{NJ}Z-@zV2usOkTBRG<-cbh_#uB-C&)$RAY; zM8m8>Pxhck+1~?We!t8)R|2x;B!mCwp9Dfv@NXU46>D=~Tzz%NJ8}Ln^G7``@7_6? z+fC0BwKn7%Br0j?`~8@kxE~cHd+SDZa9kw{H#vspj8^%tFf2`u^ikq0#Heb6Z=hal ztu_>}A6ct{E@M0a1P%8;!xvGNKJ4(JjL!g(!~N$);f3x2vpqtX!a6TNU0M`AIe<17 zntlVRegkdBu3INoFW}{N$KDK#sN{|7U|>$hOMa?&v-I6TbW&&dOh4hL{`zz{sp z+RlG7q;Yt7_<@CERWi7nyD)aDE5kg(nHg<|vTo^R?u4Ba&dPwBU!l1i@2G`~5AMPt zpI*MO|6&xRICsPKQmG?GdUf7MADzs&PSqeDgH~r=0TO?Ym~?&3(}&jYp5D9nXjrAV za8gTvLnO^f$R#|y+38b!SPRI%S9)3v2`K7n_JnC23Ud4J!tu1M9fyZFthm{(-MZeo zEehdIBM99X8OM>RFDSp#j6WRPJR~5P)nV??H#)7S+mNhHeWx0|^FDLxcJaquQ1i3K z{iRsmX$T;bc`A{WF^s6x&srCEcw6<5HeTzpNeg<`&~Yx4!zdg4+E3-UkkF>hOO4F`Ab& z@F)yh5^#z=y!yVPtWw?Dc{WC=^QrN(dQFm>wi9F@((-A(E-dDNXZbz(3oQ%vr_)~g zKl~sIYn)X&6$u&_ouk-}C(^yWq%#Cd_hK;y&sRPTvL|uumt}SYq?I%bG_k&@HWQdQ z@N^kvPtw^$pRyv|f^?a<^N06Q@H<0RIjidIS{*NFHVU;rHBrZ;DZZ)u;${C*bS`nf z%jv#y?a*^3q=Uq}xY29cqEw^>j1)Q-#+eCDhVSNBIz&&St>-Ur6qgQ7S$Q&D=BV~| zWkb<+Z`P*6+VUH=aVX-X4+~ZuUDA^>ikV#9t)KQM6kw#Qa*&I+&F}E37U^n_3or;a zDhc!y(l}z8JT>Xcl>U6gV_995$C5_?TalWInQ0hfK5w zH)pQ&m9UQ%LcRF)i3ni=HN!#(!|pCxBpE>Gv6oF!NPrVV^#>Ou4))+P_Lb>=RF*_s zFYdi#e!o+(5~c^p&BE$awI;N!@cYFwyX@1Rw40jo1H;jl+rF*NuqumyHw!p!;L(tq z+5vIa(0ZGRW{1N}Pz5GUMEn;lpHB%DJWZ^Y3xNDrVNGHws*0>gDejHk>j~ zkDT6d$g#V3WBqGXMZC-wUd!Zb5JVwT>Z!eFxB{1qBh+yYvU|rT5(&KqIG3Xg%hi}95N`lUPZ7qLkWQ>z9!k%GzE<7?Vx@f&aC zIFdsV_Y~;D`l^f6`!-l>(MR>$O)bH&>cNZZn5NEG4h&D_5+>c{^tU5)wAK(l4LTp3 zV^w8M!8DaJWx<8)Y#Rpl;Tm_JIim|GF7_9pilOsDkM{M4a!z}sV^^m}XQVeN{TAKB zn95bCjCpkSdC)yoG_L)!qpvV&Jg)-!yMT-+Cz82cQe&s z@ijkp6}0Yj{I*Y@J0Oe&wDg*h)R;t&u59`>dVxF_6P28{l7G-IrET4_;J)cj)uL8W zIa!&$3Z)a(5`u6}ImZHR;z}Xgq_-ukmPq&MrQ?v%8sWUxnSar9Z5mJyWq-iYFlUb> zD9gGBMwMCx{*?nKS)Fbg#{lEahL;aA+EclC>)PmI_pf0eW3U2D%*EpDs($FOIU-V8 z>x2HV8iE+unLSIW{~JHh-};6AmA|iez)*S9s4D1skSZhU?3$?v`)j;rQlJ!k5Jh*~ zzY+$`IaS!r7+Sm_u3OlzyfYx*-}$QOI_<eygm1 zqIzKtXL>E#+lfd`{NfyOfG_HHnzL-%(9H)7j-^<9z~do)@VVjur|ZXIpNPe=xw@d% zu>}th67<)welb^V%T|e%?eqrzIRh-#B!Mj8SjE`w!F(+mLO@XQ^I^haep2$@$o#H?$ekj(mi|h}~*_aYj||0Zdl1OE_)5GD}U( zAaSrpL+eV7(Ulc%=6R(3RsKM)f@lOjJ%ZpHe(@tkzF6 z9~n_74G9xAPnF%o%Ln7nltY;W7^&b^I7hMb^xT->Kj?9*cqzP`6ML)7VQP{ zOr!4?1cyEVG(SDq5uJ})>?nrHDS7+5&%)b~j@EtPd+7FIsQXg{$7|#VxiEsWYiITH zvp$iVZ&Yl^*byE9tpvhSjNki~m{6P#j3}#9HA0)Ir{dFLJ9%bYNS210K~iPs zaKlWkx(*AB1W{FXiW5=zvxzi$tnWq1lJ4|XBLhR2st#$s!I~4XzVt$=rezQoD~Y;g zTHZH&)A`cD5fLcLQbWlXbagKeTylNG%7uV8?Tj+Zti8cx>0(H;6_ZaT8PYr%T=3s& z#+uCfP&|#M4girX;fG8FoAum>pCxv*x#v8gyOo*HG_E=Eei^m+*y4&@9-suO27(tZ z5@iE>_eh_n?ta9lE7$VJ7u&O*W># zlzz2Q^y{Lmhv-*Dz%)h{Ca`!y>jnNz@ne+KoyE3p@gtFd<9+TembB8ewxH#$sT@*( zI`Xiyu%{C+Kd z4~reIlM2@ou|SJtq!EcErIO(B`YP(Y?Xh!(Q`kB)PB?#IplX4gagt~$Wfh4*GS15j zKGE#L?KTPaD%+!$ojW4oMfw?cON#we9nl$tR=T9F`a`cciS!v*L_WYdyc?L2sMM9` zTgLCImS4%r>CLvJOqaN4B^CUrS8}#{2H0n^X^G064)KNR+Ugk+W^7QS$zKMVKdV|~ zxM-lwb(3JEL_s(vUe93C?GX)4Cb7$EE44WB`G;cS>sJHDqrkQcm;r;o&@F9%6=>yl zMxXezzVtjjVjJlF07Ja%pSmX)?>)zaL0BE6%j0RPjx&V1%I@9czzI8mC?mKV}rXddX@k9a3zt&NHk_g$fZUa|O>#l}e#%bF6>bky-V)_v15P^-y8Y$Y~7=c7(QhoApOjcpRq{3vx%Bk`SXOFWi^Xy z_kL=}ACL6`akgbw3I5(=T$mg;(#m!Az@N6oU#rsSIa0aDIT09~{1@L_5WZ$6Z8&;M zTQLDRlm>XzP1Fz}0CJnOm60GGY;59iDS|8vxL2eo!Q4M&Y=@2!&&e*BfI3U3pQ2zpG83;uW*#0~5usGShzm zN+-v}e@jpwRKng9jw36ur^{{jI}gGKd8;UU}ve zY5Wh~D1;ydg#)G7A{LE?#Y^8BT%X$R?@oF766leW0d&b7dPiE%b)j-00M%_ozuaL0TI*`Ri{to9p%>UEp%(~Tnv8qc z4H*j^k&4ynYmR{SE!krPXGsQrwIK<+&OJ+ z!(x&CNb)|QSNdo?u{nG~(NVG22HK(L^9vvGk1V*d z2oG9OR(cK7aql1P6oKTcaHf|PbNLP5Xg=c>H&D-#|94hhp9lD)6YQ$2`W&Cr<@nJC z5TqY*2WZ^%asc;Jeo$(woI0Xf8*lXG24*fOV&5d|~oE{iqt{;>QX~ zEBY$DJ?4dT7_S%KY@z2(J?;{Ae{OWQtCG~gqqeYnDeO5s#(MWUOSG90!Yelno?3?$ zw-e7G*4(OQbc`HnK`ycG1J14Cg^I}jeIg5S@_>(dqZB@dh^_wDxRj~NVlxEVPgtcI zc-iu@=agA{@@XXTxb#{Gb02EdURU@Or*~KC1?!c}beo!stlL=W2J#b6g=R}CJ_dD< zr85n}R5dlP#Y%4yT@|JsB%Wzfi!h6_w~Z|>C@d?qvr8t9x{Qd=_LSk{7U7zXsh-8s z9``1NRCfmuE&)PjidLKZ(!=WYRj;Jl*FuCY6Zmp%OwA~+J9%m$b;ksY^y1WDD@R(y zE9FsO%=7ApO?Dks6Fv02k|={|sf@(SmL->$oBy#u!H!+q;DbsjI{6L3&TEvm$}M9c z*d>kh0Oh$A5L!6uAPDCvE6SG%7A~?|%0fmq4_v{l7=Fke7*0TCFhwn3YbRAWY`+ti zXzkI`y^WGPqT^SO-~UMG%KeVK>!`SMJy}n%w@WA^Zd$<$jka&+K?honeCXB%T{DUM zwF>icwV8JE_2%CNTv5z=p@XOukrz^I1BI{hV@pS2-q zx>>P-U@9%wz+`gT?$Co>E}wvQaxyfw*~Y-PHU2v1p~Z?~g#2uruKrw6A8mca+M>j; zD9Osly zCaeQQXX7TEt;&k~3_tfO)Ufy~2nAowVs2=aLPKpAhTn{sUNe!mEDU>(PiBzAVa2#4 zlv|tmTap@y$Qr`1jviDxyJqk1!T7vf-a*^e!D!I(K)*QE zgZj^&tGt)qI#nVV+M~P_u}GGGCD1!3;YAA>&V9G$% zr=8T2YG2W+c(@;>lrXXMz}2n4-(K`Zsaqe+b!fHd$=545lnpV=iMK~Fs>fLDcroNR7!5H!B%q>7Y%jx!E+_{C%N4QqUG-e zSX=Tu<%WiayhRx4N#AXgbic(l02;urUs5F5(JdWh=f{I?0%q;Zi9;elN~ObX`dKUb zKI>PAL)Ms{C`KS!=-f6d&*T6k#)cg_D<;803Qail0IK2g*&(j$6K|9X=A zLIy+jaG#>VW3K#^<0OKk&EO3JATJpK-E3EBgnFqiv}70N`IsS#^k~|(NSAz+vNo@i z-E9aIMu@Oz9P=bl)}=C_)k{_@xYhG;MTgp|gXlVm@03o{;T#(q)|V2x6;K6p5f#1w zEX$oY1wMzSaK0m*BGIjrAToN2hT=wkjkNJ60g4K(X(>f6Gjgafzbl`kSQ}CH`ws2c z)1WtmNz2PJ)%_Klm@Z-y$~clB>191Zh_Jmf|06$bc#jXJ4%3I(gb@xx+Mi(S+1_a2;|2=kUPW)%E7Ja4PpK7k2J{ zT$N*iQEgIOO(JxvI$s!fS#F}SI&aFth_P*^v?OejhK5;TpUHLo>a8_J(y1Wp)<=zw ziZG3_hG#3D&n)o7pLNkO8wiZU4(ybuq=c}CVE7MJ{l}!VOh_i1qwM@`2U5G_4>^Gj zDu~B>VxL%gqPG}21*hn>z(cE*{gh>OEk-S|hCE2G$;^a8twNOoXWhwv#sTswF5sE& z{bvg$4em+V#pb19A{03H#VY2P(`FlySS2Eiu2>?}Q}rh&ejX`5k(>~J_?)HZpyyye zBG?H=o5@uEw8;)-EVaFQD7M&tnrH<}g{|v}1MUXn0M?fx6=Yrc<7gL6X&dSJ`IWm~ zxYSSdQyXk3x)QLSwOeys%U|AlI{CVsX77S7X-~?G^nrJxdE~RFxqZ%c`Hl+XHkJo( z2Lw&=y3>RjPrw$EAV4K9(UXy{ zKta8FOQ6vAWgn^aE-J5-BMH>N+ipCr@M)YNWGC2L2?ZkeAm{7;;UR>0HO4{fKxv zv{go=q&S>clFE`e@QTS+9q@_j022wv%#rKf0KaxqzDDO<9CY2SqLnY}&LPXs-smAcL`-6k ztBAh)VW#nkFbPi89dXG^%MW_3ZVebKjH)c`_`9vZf<)M%)M*A3`D;bZj$$TndYA#G z>U(xwKPG|PzziTB$+zQM4l~`sX5JFpk-2Q#DgSVTpIYr|x6p^{@t@W4#typ`h8Axu z$OP@|v=Xrk0LnzHpBcT42xMR{&^Q|lkZ-7RwG2G8y0Beub z{5~FLJh8_cV)B>&mI!FDHVPRhExBy)5&LCABVR{jV_Sp?X0ja+D4S4t3?ldLX3o!H zt3oS)z-%AX!sJ2Er#W-&>Jd!n(0zE&1c)Bo3**i)I;N=rOn&Rk#lT`$o_FXo_-y$l zkg%FKP=KCD!vZ&WQ^gj*l~rT_ftCJQ5D31KG|K7BRZnp0Nj}TrKt|B$@L=Ld)X*@_ z0)N=P<}9Os_Bu)}VUjG9gy3DnK_X6s`eF1KW?F8-d98jizh+?jzfW&Xlk`+G=l|jS zKII4R-xz}`VRifie3Sn%G-RI#6)kH!Pa2^-MMc?`O1savE#2J1Yq8;n9sEc0$8)i8 zbI9WV)}>49f@Bl?M#*jWzdH@ZzZL2AW*78duc&GOn)MmaSlHg>3IN`)uc1u)Q_4qb#0Yq zL*!-K7c=p8!f2lVM6r&N>l)yOx z9Z=aMH8{3``c*E%S^DGFuS&`(<;e4=%F8M$2v4Wm_(|o^U4_+{u-6cIS5A>7u4%y1 zQpfdztq#(A_zY4NhpKdm-l;tjz!AQ4KM29l_HCyMAUVz zbzeEE)pA7Syhk}xo{|5-S3#lfQjkE9IL-N0vp(+!0i!+Q2Zt3+$5YS&u%SkP(fsNy zcKAE@{-2zXzBq97)(~LARF2Q-=~<{MLK}IPjzQ~n-YSS$5Bb7%?mhRxG_Yp?D0NIZ z`l(}!7J%l{!nK4BNS(wJ-u)x?n?GjLKE;_WAs5!4KCEb&hJKm3ZuHAIMvw|6XYI{R zu4}B4i04Rr>Dv@6?@)!AOH*S{e-V1oOC8ic36mcSZnYAu)qL1hP*wKA3fU3U0)oW^ z;H5g)QL8y)^b)91_(IA|+J`y05X@`SH@&xtefQ-u_{}<|P}shpXp)ABvy5T0z4S*! zW_p7Gx4^>n=QNSOp%?aQIBp@kwSGnzw{{X4a{1}BfhJ_*gFoAplh}fjhkzG`t3{fw zt75chkNFbYksER7bWxf1>wRMg^36FI{!|8sbyOA8AT8{|I#cF)2->YMesdC5DonKv zUsGH2IX@8~4aTCK-t>wuzUJoR-DF}^bh}EDo3tEd*V&MW{Tilqsj|>@Zkgqwbx?%L z4Yarq%VEABRyZf+k2upr(Am}MOEO+xhvCT~sI?Pbxg6U)-i?!OdillD9b?E-#v=sG zCiZOi05}>A}#59=w7Y#T7e?LLn+UtF{5;h`lFbZSKJe$In{zmUz0*#YcgNLvh~c+i*6+aH^)@J zV9MPZe_ExkkA$H4*w6nGrs}W>gZ zqCS_6w=iK)2H&pu#%&sl6aL;^1~Nr)^Ipei@)5eDLq#y`T>&jzRdwL@QQP|^1@Xq< zmBQ%p!rw?ncSbtCMbIUJ?QAMd4lp|8cO36Q*W&amHdg=u={3O-g{cHQWPb@N^dC-1 zJ{@;_Z!Y7QNTpyLYCG`@d92`w5qCKVn)t?^nq1HVg7XKscPGC>s=ZD<-rr}dCaQ4j z-RlvXZ-IJ%4VK{4i=KWrmQz`HKj!YaW;@YMdT21W3wGt-xK`~8Horv@p0LY${CKb5 zRS+9FQ2b;&d&xiO1OInhQUa}YmDpFQT^Io&k=yswupr;YBy@7TRE1&e#dO@QMd@W% z^;1*8-$3I3c)!ne8w9wB2!J^olY2|PKj-hIy5vgwGRDSY6H?{d@2l!5WFMxzC3H-; z%vSy|hm?3}&WqBk#ptwFunpgO8)9@H~ysF}`9?Lj!Nw4{# z0&++uP0U*lk3#47aYA;F_K~b%51w0e=5un$jSX>Tj2)?d7NaH6jx%FK(v-w-t09M| zCE3oeO>B0;c|GqRZE^c1G~;$09D4IYF9;LK$$P}JWCIJZW^`(9V{!`)gcV}rPf%q~ z2@9TF8WCQmrPXv4_V1pd4ZXad81~3ih8Q*@Yt~L*XD<8g?EwV9mY`9hxgsli-<5sQ zlw};P!b$uFR)%NS;2=LfRzYY+Wc2J5`{iNAfh-J7B^(7iz0j_esgknNn~Dm2=Ib$@ z0>qcdq{dO3Gm6N$Ybs|;6u*@+4h8V5qfS%g8_#J`B<|VCbZ0EjIxPn%KOA_h7PiRi z!WNIF)k-Ow6NuoqY1WvwbAU2z{kTQc&Q0>5S73=UM*FDtMUD4mNdfu>#KL>0-aqa= zTR5Ajk!U|N9-U;#C&w{TAJHPm;qG?9XuFb)I(G^(hx5)b8#YYR&iwF0HIoOjb(YcU z*Q@eT{qx$7X#MU?PN1{g@XmSAS0r4>O%GSVyj$-6?(8k z9aFns$XswMk}-)HsltzVt>hm(2nFN_Dk-}Flcp;&kC$xcsu z_RJ$_2^j4Kk^KUg+Lbo+g?^EbUTp%q$b987W&J{}Bs{;n0OxF%JSLeYt9Y<#_KMYo zLDLTpzCx}yaniS0DWnVyf1A)Ue=V9M)~|(rhz8s>f+uM0KRJx;xX{|2fzFusE*7}9GToU&nO=~2o~`jt%`N%C*^7!(g!l( z94Y9!tHG96klO9S%Di)kO75w@4Afw|VC(+HV$Ll8sk0~d-=m=mq!-6B<%hJ~+MQ^w zn-mMC;Mutc1s8_E|7`%$h;qJ$LE}OLtfPYs^V<8Nj`8}-0+v|`I*Sz>s7AZMMATXL z>?0tm^#>jLHe64>K0N~0GvP6%F3HcqvT}AdVaI1^*}o@m`wiH720;Fm%b*VUvTU~N${!f;@Ch#m% zSdUUBw4&kmv%vmj0LMs+i;xHF1truCjF^&lGX4QV#I7Fh`m>)pxQ`CofQ@M6i2RTP zEIn55A0Ha6Wd>Uanpj|Dlm*{p8H|&J4T1oLg=gFEFt)WLc8BHwSEEe@5Ic7!IQ58Z zz4W2+_B$@Z7o0ijuWEM#Jpnzz;EM5hdUFKf~W2_FFla~AR&-`)5>HjfVelt*kkG!-5##+psFn$y4?vS zmhJ0$Y-m!-wphh0&C3tZTIX($e)6k8YaS!hR-6|n^cTNNaY^<{*6S9e_b&t2T6uVj zrUOQO| z@G(5+@L%TExiq+Mf!k+t15OB_pY$Bmv!2fpSXa28VDN_d zij%;aF7#CXQc&G2V0(m4MISu}Kpy;Vyf#jNcJKII($fV`25`I`UziT4Pt8+l35L^7 ztb+t6gc2BnB&A4suBM;zCmXlDM8tY!B+9c(Kccy*=WqC+L2!s38C&BAiXB!-+j{!Y zw8tffY8Bin%=E#=8GJ)R?Qj=KlHm;qzt0f=<3jA1f?C0!!?XEJ^B9UAngOH9*m?%l zv!8Atra-xb5VC_CkayJ;0e6K&v;5{C7gXHeGQT2g0Xgb+`Tys&Q~oKd*i0M<5HtR+ zdEk92`zL`44cvRFY@~yn@$6xCY1gLUyth@pg(GU6zB@IpFq9)_g=&_?SezJwx}YHO z_I+kopiNzM)4QKq$OfJistgF2HvGmK@mEY_f2(Hy2H2ESp}V4%%#A%9$w0HZB2Y~_ zAe<%PIgea8Hqd)F+EoFJ#aZ|I{OzD_&y<-C>JoBwx&-ci{CNM|pwM*6ac{_Hr;!Y+ zJHJ5b^PeVu3HD8r5H1|u#N!hv39c*Req*=Qi)nR|l- z6jOdYl6GU<%*r}gS;<3xqq&H;=lYZIA`X_m&k)uu`B)!y0KH4vKM#f~uq;K98O4kP zQ#c(u3pUMhez&&O4c$8{N>^bfGg*W-UcH`L2;L8*Yjm(n_uTT9%So3l-vejxq?4!p?1#RsvX4}F zxDKLPRZ|9`jl$3qnQ!Ja+pHt&8&M*OobZ>=sei=%D+umM(g&}r>PzrrygTvj{1r&` ze_L8<`sFid66LlJSdgh6t6(#xtuge!|BZs*Fg=_qPtjVj6he@Q(`E-V<*u!PR7+WTB?0MHPq|^hPD$y&3Zvl@E z_ihdN$o)9v^U$qJA%U5pUhHkYDq?Tu#UdNMa;u)3IuKK8Uxvibdu}|vAQG?4_C>Im zRnD!3Hg{GL0*=(l(1%SNHv%FE9*@I23*q~KCIRP&{M4a|Q4*kKd&fKhG!DGQ=7jr5 z-J84l--qv^Q8htmX7&w=ZgCZ{&UHKYWEn9fmV9#mLX{N7OsKFQr>~c1#MeT>#(~f) zBX=BQbi4_e7w+##oI2DReAQCi!koVqByU}myRjn4CRMj%L-urNU!i5J*p$)pctUrH zDL)90vY%~S&`<4L7>^6LL_o(Eo#-ELeyS4KxvEQG%3#wUcj_TO4kc&oU0X|CQq7DA zfDD35PU^}^>$6%995g=lqj*cM3i$-35c6IO)^!v%?Z1`fSyF?<=54iz$SvOz&WQ1A z`6Sm#Kk0^N?~oQfGz>l311f!h!|=+SwFkTGf~;QJXk{#Lu;u1`h3v1Nz(Ymg=uj$yna*_QyZXW zxVjh^^?i7V&&40$N8HD;Oq+%%N;ExPQ#IDY>@wuVLnRwFYo4gD7b;%>ye zYgcAcTa>~!`awSw{R5i;A}9-?Uo(E!+C+rM`2J z{ofeeXASl1|a_yVZraKlzkdH9^xt?`XjOdVuAhxe*OXJKYr=v z=7)>FntZ~s10UjGt-4!4^cIldq$%*D=mVVRD}CV!xH?O}{4v%y+hS>JGV~jDkc$W~ zzuY=;sR3h?1aMhF{_ccXurgIefMoAVo&g@+RCncVNnwkbTc)L+CMaITj()w#O$bc2 zdjXSXMi;W|iEIk8$1x6>vSuF5or_5I{cxR!7&&H9#zX0&;Y#oH>f7~>4Z^B7RtFWh35mQ?Wx@s*jtOu);Bf1=wX z=xesD*ajuMuwtQtH(w$Z7I85XMw>VIYRSzYeJ0?=P`T;k<4i$bAp*Y)dz|M!@?GiM z$ zo`c)SN^NopnSJXGt-)tmMIH*jYh8KQAE!)1Y)vA}`lF%2OVG|JkAoFZmI1KY`Uly^ zf-TGjpc`nv`AOUQoPqi9B(!+|csS*UUF+4{_7I-}9{2!w5gpuR>&M~t0L{R5SA@wB zFcUuoCII!&Kg3D>5j;711EfWU8!aV+^fCV#YTbXQG#5*8O08)wn0BBW;%(qna%6KJ zd&$AOa)DL16nc2TU7s_bspVQ)-X8caC*Mna1&4e85bS0v;*PX`e^+~enh>1LQy?t~%`V|8FE~2NC^m_vo z&Sp!|aRfWo#Hp;hPAAX?&KKMb7=AmR=jtDEedmD?A8#8gRIO|ER)0w4Ezh2Y)>Ds- zw-W*)!J3jR|s;y5_p7u^(Qe+dnM+=C=sr{s{B|qD!Ms99QpB=juubK?rv? zd;}godr4>``h{=iBtfWG_Cmx85^~wzD2JW6 zVG&T1cF3nI?{sbV?PoDXuh`P@18I2K7J0&p}!S!)B|$T$)g8xk*&GD~#D@`ub|GW=|d- zK~3)baD-LCM`SyfTk$+t{2)Sz`D5la)~O8=LKb^-Xn9j+rfOtJh3wm8X@VhQq_FROkZ4^!Z(FROmz>v<*H6oFw_r_)Iqfpqidhj; z$nnVXJ|8{SXU&odSKC)RRtIkva}|b#FHjl)1}^oF9&K2o%{fA?9ZoL#5bNoP0UH1n zTup=aufXF0owWk#!D}s7-Jnk-Jx40sZXdc}S=&YhqMz#W_T{@tAk;E9awe5_P*)Av zv+JokkMz59_muZ(=|`JBaO{_An*zuFF!nWUYW#|H@~Q7*|4mo zX_culhP-Yi-4KU97sR}Un>l%XcvEM`1@?~q@}R)`bal>StH&0AL$?Ya=PTq=RQ_GR zlo92HT~ja8m8}d8w~(@(FY`j(p4Y-HuX-c)bQe71>!Zn+a%m7NcD(dTf}_9kVKr+U zOFRO}9r3 zg>YUQ^91IWxd^Z#K|J3`(c~Ej(`@eiBP$P)wJ&(lbh)TKsRJh@SX)Ak# z=b_8u{bv>1n?|r}LGY5-4{%*;TEw%n+}w3`Z?WX+ZipD*uI0(OHDF$R?ohpEOkWTF zDMc;%0LEl<6}rmH_a#c=Ku3TC0QO`6Q221_#0&5lZ4~$o$XO^&({KbGgMQ)$AkXAi znyfw!8b1}mQZhZ^eQ5a3`w%z@-AB(eI#_r53gOQ&UXii@` z9W=?W{qUdF<@rBVu5goGUOfarSQ>Ow!H;&ryEjol?8UF=PG|kAPHxEer)mEnaungm^#hO=``RC; zPSHcklTZ7+04kbyf6zSw==rZCk>3?|f1Ena8yV!zMhvhOhwof|a7ltlmfsj6f7AB; z*M8wn2!2_FznE}BY?!BXqnM=K$Dfi|FPsR8sCjoBEIPWAr;+?I20G_Y*sTF2_`$r& zCRB;nojl_bfLWiYbDaJDvvu&(byn;N**N9*W!7JVv6IK<5&pA8+WyOy1G?P=HtDwk zRf8@0spEHs6`7vNKlbQE!eRS&2;_>xxam)q}J&W>rVa?O0=_c|7gAZblzJ$ zF{LoX{Ugk>SyyrQ#06OqSne5fk7A@oFRH*x3*iodr_G(u%X`z!r%~*zP>S?dHgV4n zF1?vZUXUJkFJ+{Wkd0mov4+AOec^&fApH4lP0d%x7P{*O_oUpRtxD^swcRo=Ee?JY6%_;-ND?#xvW nndlD-PP=>?m*)fcFUm=%WfmLaq0(BZ%?X&lUgZnFlM+iy` zN4GmG&sqJP^`E~Tr)T5qZ2mc$pU=J*|98Kq6ir{+&I?{CNhl&atW7>@!yo>(DDeuT z$Zqtn&kXK?l3o%^ZLN8-do9r)em^T%vh|A?j8 zCc1VXbCKnSza=$wr7fBboVT2ztl^8*k#jn9=?z$Xd6~>YVcq+$wOEMvB;h4-&cJCl z<3sWsQEF!p2d%zTjHIv4tQqKe|i{zR>@aE$-BF&Y{%xvZQ7(y+OG5 ze2VREs1;OC6@9ezrWKE)@Xd0c64lM`^kQFVCp3*P8h4+rH=%drMpj&m5T7;b0<+9G{pSnAZ&- zG0`u?*MfyOT)HqF;Hj2r_N@Q>7p$kK6M_b`bsfzlksVw`2;3R^@`}f)cU8l&@Zw%Z zcse;b$w?(OXL?e0P0J`irOCh$BmUpm>mrQ20*hXvAOM$A{0d3QD5+h89=Xd~9h<=u z3zk;Mp;x%vb~*v7CAs>qc+G!!@=rPSlTT3S&EG9>&1;nnZ?{aU>OAp&x7+;V+3trK z8)KIHX2mp(8h8s-_*=c6wAR;T&_?+NcoD(zr2%{`_zGR{teGmeGu=`uD^T?PB)h@; zSKjA8nf6jrf%^i6rf73I=2gGO11T%ZTZL8pt#@{|*a&@UpNCPT2M(E2i?W!s8YZ}F7< zC{lhqqoX_UlYOWncj$@E#pzVXJ~I2h_TsJUlz*0;&q;1hi?6lbNhkw)k5dow+2cC` z29JkDP)5M|uhs`wCwR8W@z{N5;&&IS2~O-W7i;#T0hS6sYm@LGI`oT_42Uy2eFc8~ zE9AsfLrVZY7+wT}+t5&?-lGn**z&@^xwPiG2Zg^ehHC+QS3}xSBUjR_bs)w{#i{ea zHpG2m8$x#7n3~gD}({{tlG}1?NmoR)vL~W+uw}D zvq5@#20NSEp!H{;gg^N(pM6RHEfyeb9AqErCxb-_NubuZ2>jv>u}{`C;V}H00zTDY zx*x0Vxg4Pq@AtQ{uy&L8vvx@`oqI0zf*cQm|9)|I5??lXhus(KfYknyYyZr({a0)- z|6^%SxwHRq*Y=}#^)p^^msFsw@e#gAS%=J#zXN6INs)x{v-GHAmcWm=cdNjvp56j5 zV6QsCnK{vyom(4!`;$p^=@9G@CXkMFZOL=4Y4Uhvt%6nYD}wd7+bR>T@ICISXI=ch zW(-%ApsxuIKZAAmk36H?shvW7zvrM`H*i9E{RwricS}MYx7F#l90X`9Do~Htp!G?y z9)z<$FO(b-BjNY-UEfQQG9TN>7K->=2Aengz zY{LD&_1$15vPmd>+$i+WNt@U~7^vXrM)Tt)vxR^qBrn6?U`cgnX$%u{_KcE76+Sgd zR!``?z-d~WG+@`UkZ9wDy1-8hCD@^i9-ZokTebpK+BPyFYNpT%fMH&K*R7!}q-4RRzc4iU&=@)t@rMIcrO5oOOt60bg1 zOc3B`c*(Cmk0_q=*q4*0-PS^`zZ{(RZ-}6t0gb(B#~^27`@6PGG4yFqpjQJXg8GFUrr9ei!z85bv*sxdG))_o1STa6*KlLWhC&T8P5y zW7pkQd9L#-7hfxSZu(jA*bBforDv7IF5D17e=T(mFVGm{dH9F+Sx#1>kMRTB zR0NmCg}LI}j7v&okq4ab3lc=;8uLFzzS!R76yS}@R~x@I5DS>>5c2Evl4K6xIN_bz z_p=wQ7Vak8=%d}mC=q!|RA^8t)8ZWZ5%C;hc2iRa>n&!K`%i<&WkgGQGD6PZwF^g} ze;qLi#g~|-D;z190Y6-^EjR` z^CdK}gdLtPWxwUHML}Y= zY&;Rgj5YGOh&S@(LWgv_$hX^sPM$hkVGWXnk)-cv(8%Oy%AC2>&`K4c5_yPIpH_9h zZ2R2QHCf1Blu(|azMRltV?^WZ8h&xKR4(FitJe%+wFP|y{ruwVhQn1 zmr}lLfbKs!6ym3rud=VFpF zJLX9`nQHKpVyspt=l$YYsqn@77%3Hq0Z_zHlbb5?;;%MJYfPBkhOlon$2`&)%eQX- zEH3ZNB>ET`>AEh9QL^a$aHd^p8j^=?V>KrT@dKX>&u@=$`EpP4jKp7i9w){`D)8SpLJq$W8BKS+MT%dzqAN zOR*xXqepLVT$54?s1EK*i0_wgADJ(kV1|9ri3x6H_kq3j@QQ!QAlBD7m%%RCV`#v1 zOeNZrK?@r)B;3rpnmwZ?j9%=Ui)heN>WswUc}}hnyC8EMDZlq+-xI5+is|>s8u^Gn zMhHl3us9-q9+3%X_I&`e4pV56-8xJY*i9$Z& zrBvhsOP%zq^Ezhq8=1Aix30J8Q49Ii!kne~c>+l+j;OBCU0XtlXHMwP)-)vE@G5W1 zcM{;c)3M6;c>IMvILCTo^2L|7aJ`=0zw)B@)onnbK{NSa#0OQF83naN|_d4WA!9_;MzE>3sy`Zbvmp>%(Q z+~Tz1v<>Sh@7xwX;?uJ?NRh32iO44xj;KbiZ#Y{0l(A~qay_6bP5D-NQSU3#xbboB zP%{%P^qfzS(N>252guUOb3>Q~4isl0=qtpq&8zojfG*L~a}PsQ8>q$PO0Ls;Gcf3i zJ(mACBR%NOeLd?eJHL2WI2{D?lLQ*G;0{UwZ$0s;R9JiB9}Hz&&FbGmh|N2x4sQ zA~V;u$oo4#gfw7NyLY8j&L5UU_?yWU928_D1|%z#m2B$zhFgWw(X6NkVd6FCeat8c zG;{WKX7_#ui}GR#PaPefKgj9GRFNB5*d@e!yx7f}c~yYH|` zGBuPQ^kY+du^Nd^j!1szvch);9LkS1_2c~I+@@fe=bcvv2rst6%Ao{{)j9b`6{w3- zbQ~Bj%~BOq1TB(zn@r}!v2}0bE7s_}3g>7`y^o=P&L+M`IQ_0+u?Abjr1JpDbgyk$&(yL6b)nTfZO(>g` zX_tC$c(vAAVp+Hpr;2>(Mbo{FSPf>5U~_s8!Am$d>Z>@q$O+YR^+{E9$RJn5nkNRf z6I{s?Dz+<*Zrb)d>UC}nmN{^K-$PA=bpSfM{?*TjzYM}FC8Cpwvjm-X09^1ge}gB6t%)=3={YTqi~NhtDeh589#)0 z;%}{@DUb5#8R%(o1P#ap->A+_f8o|!;>sR^j*=G{lN(TZVO_LYMt+A>fMu}9dmPD2 zF5?C=)psmj$Y_eUHI9XK z_N5>3Q3E5ahOP6$5bN9@T|%_(t|Aj;*L6_~n!;fFw>QPnYyNr*p~XQ;uUaY;bVyWA^cp6Z%C>4KUkDt_vi^=`xH%r^y}6jjlG|d2TXDyNem0hpO@54>H|CUhvY!(4)|wx<^|(neFlI>hNTs`J!sVcgDqDSOKB zjrsxc!oFC?e)1_{jeEj7Ng9jQQh^W>OUfFyMq+nID3)?vjO-$kz#)7421)(#Y@y5O z9b&WMw>fEQlAAJK`+_X2SW-jIcGO&-?Pc|+fBt;Pn76(ljCXccr333@NJA=&wl1ZYV(pwEG2 zpc~5Lzez6W@3T-SuX^3;asJWc6%`s~aX-NeN3{U~9S|cPjjNXH#5Fh!AFe*0 zBg0QDI%WY(Smj+7OEyNC8HURQ_W8A6MxQjQU5kC0+oBjT2e}@v?sz$~LabbgPt0)z zqgSZ7roPc^!Ud}#2F8Ykz8_VxbDOe9Y`Q`NP(nrBfKHtMu~w4o5@dvNJsAm(0-K9=kY2st zh3xnG7|Qj9acvzbUayr!Q7Fk{ORq6f)nEb`tGM7uguTmEt>Y>s7oV>XeDFJwC2IH` zIh2z3sY@LSdzxENH<|7&y)=RqOjSz}do;P*AuKogoib1F{=f=4u?XoSs<_fN8TNJn$iBh7d@u!kqMHTZ>n5!aZm z5Z^qyHdp%E2zWM#yPnmADcUmk2TZdME4ltZ>fSP_&G>us4uwJ~PSK)m0<^e0w3K3{ zcyV_LA-Gd06e|uTxD_kz1efAo91`3u!Cm_Bd$<3c*`1x)oqe8XCf~_qlF6IQo%@_~ zea>}JKGEHXSMb0mo#3Nnp|wa40MI>E_-*6vovzyFco`NONDiqe2q5Vr*la@Y-sv9h zfg_J5%d=MfNf!`%_4Q45HHr`~bNiPQ%a_t#fjqJOWwQ)kK^`Ej!l;CgP2(uwG_*ww ze-t-R$!?yB=;UrmucnA#@Psc$T3PQa2Aw~{{>^oo2R-csIukh(sKPw239Q%M(D&t9 z#3ueD*he*(ZsPqM&YWS(S&04X*b4n@>CMK%S54>q5Wb*{k}3BJp5y1#_UxJZexin- z))m6-?cLY{XD?g;%i?c{lbkT;ct33x(h2g;y~Q|%CnRLLWIBof$b*;Z9*9%tESU6_w)H9s1^JD<9ygR{QK?-V zl)GuoJ9K@|HwO5P*CAZ8^83RTjKr*ozpB$3q!)aV$diV0Mk|$xp)f~;-4TkF3-b@C-Upd1J7%c@t5kU1eP z96LdbK9-W>&!X=6g|;u_<-o4v%Ls|Gznad)r*iQzbKHH5C#*?5rytL*`HFu1$i;8U zwR4e^$Vk<}xGkDMrD}=$?F^f6eU0`eG9n&w`IyiJ;^o}gP%q_+4C*Yk@df5d7b+DV zw7_Om1M+)woCHVGi$0(~ThJ0~<1l(ZSD}t=Bbo+*Fvyq<5+dziHC^n^H0norKkV(H zA6NpHZV)3_A30G~WBm5PKQq5d1)<9#)%T(MB{+5e0A-`8+g(z7Dfn!1wnWdp- z;HfCvH1TWF0-mhjBix`tw@~!zr!!ri7U4*yvw}$H9$VbRokD3A;ofCQg{@wEcV%Mg z(uo+n7Jn{oK@R^tYvC|i(K|Ma^>5ZXQr$ z>TRsZ4I;UUSQx_VK~5h#7!2izD21zY#3l^rM}($reJ#};Fzc|u&%`8A+k1F9={6L` z(spa>faEW!sHf9NR<0!3>YeiX}nu^5?-sO$x!0*~7ln6wAmi`J&K7x>Kf!G{@|s<(7L-O7 z-~{OyUGl^4*9)8;9kMM_>(eegIkgb3sc+X3b5F^{9m<6`Wu@2xF>n^N63MW;%n5;N zKsI4aC(RC)Hf-g0d^&GeX|QK21iQKIae)Mc9Tt}hYH#or5%+FCeJFKZAwEKICP_nT4s)-TXn zY%8eOQ{Cx9Q=J-~u>NMIX!%p8iG0AJl%-+Nc417_|m7KcyzrLgPzeFSapQa>A zQRWX4FCLnRHo&qqbum|GDmOdt;>zCo+Kg6o41ap_s}*zXKhW`iM~#&C$vtLZKA!T> z>*wot+%BsUv@7^?ogM!Gj@qWVk7l%wXIAlf(1G0gSwG^7%SG=Ct+S4IOcL2;2=HFq3E zdbKY{>RQGPjP&*>RX9r3a}r(H60t}Hx9c4x_6b~Dy)V0(BH8j5b&QzH?sFY#1{@yj zQs5}VYTiT4f;&!B%VYIuC_%Y z$Nm-GbYd^eKqBeS(*kLR^!)KCE^1?8!5Iw$b2^vJ5(tBVHc!Eow~n~P8gr6trbZDq zP`R<$SkhOP>^i=LH^e1Vnm9W;0~;QeZF|=2!;`xQ4_i;1tbi?azwaRI)fwVqiAkn) z7S-_P!0@{M2QZ!;+)QgHv!#$_5Zs)%3b!I6Xo>$NyX>|YCm%&5Y{lsKxWi}G@(-YS zv{WUTMetMh8j3!fs%dMiiC+>EWTo<54Nc`~tlDJVX0-4pQonfRD^)Pef5vBVKxqKyY0P!Yh(@`w88<1JYTjSi*f}7_BWH42pL7J7L@Q zdQt!kgV&^LIcA!raBM_beqMLAAH<62zmART-;UEc_P4X6=eC|YW9vVFwDjBOlj_&% zu!SW419)v&h7OW(0n*Q}!BlnnJ4{6?$@NIzEB65i$pJo3wiIpXKA^aS4zmQF&_@MbYeKa4-?tf(qOT7#sW+qbnZq5lULUCT zTHu~Ue_9_ooNTq8vq7v~;mQ8x?EVVwBX2#60|Y*MayN8|bRibBR5`W=Ja1jQ9TEd8 z@s27czs~fNosz;6)=IEHPN?%vCv4c&wj8ls#C?d|wfXhC%iM{gPyo3%n;^~jXTIsf z>zG1TE$;i~sy)9dM!kkiHho(MW=Pe?;KfR1GW>+TIxBt81eNB=t+o&j`Oarg;k!w1 z4v0R4ndAQh91+{iRAIsO=yRaY(J*~m5=utPAF()+=UIie%SX{RRCV=J71k${e$B@G zXng>2ftTQKI!7u(R)_QJueqpucL94S4b?W#l24 zP-5gOJYE|SLo~LfPi5K+cdJQN52wfLX0nPngfIvRFLnqQhyJ+<^b}I8Z2pU`D2K2# zdX}ZIqZws*g33rT>{OJ{9#u@%<8ZZ)#qrWo3s>Ii%miAlP z8K?XBJ^$K~4RoNy5apoq_PakV=8}2Z@7CWD>DyKBYEO82FYEY-Wla1T|1cpgD`c4c zm~KLySSioI>HSR=?5<7#?nv`?PSo_11y%2MAJLDw9 zUd_m|)RP{4+x;>mkH0ovf!_LuRvcf}8I-LERc$6gsDc&fU@J-464Xa(=W%h9W`I|e zr@!;iv!U?9VJ>ox66+}=LdJs=jg?tPJWEVX`cwBk8YV+ zs#1j;SHd%d@-|{DTGaP0ZsXK!r{#AGTp%V8WR+6vnWQ*gcmlOd7mgY6XP(jht`INO zuO=VmDPE5==tp1*HrH-GlF3M?r*HSE=MD`TsmJEx{0OSzMTtCjs?D75dDI3IO7;*D z20eL3m1!zEsBR7Y!Z;o)cFu3U3Jh!~F+5-Y0S1)`^e43R4U+e1T1R`g^(ITt73lSV$9%1Q2@D-m33BrGZlH zQu2;a+zz>iU^n{L&#BmBfulxJ)TA(h`2ym`xpf)S1Mw#U_0KF7N?D=}L=fL)`{}+h z27IBHDvq~JEgK09tH9?j&-bB)T{w=_jlX_BMCFi;W=aprYQxyoL0APl(S_tC=~0x= z@OC-`PJsKB)(0aM-m-prl6@_&!PvQ2_r+0V|K)D(qYaoufkuweu+{2NG~x^J|@((Brh&+KS6jQuQ&h^E=Af}kzc9?Idm zEzg9x!P>lJ0J(NND8>D=0#IU@U48KOdLo9`PHE%*RSI_2H1@1PJCK@5ChRP3o-FL| z=_wCp&=_{9${K+rQX@ts4W+;z`8%FQq$PgjuNTs{B{O+(Ho9*6^a`j|Tk|kV0r7&k z70TF;BL?HT$c9>ogk0G8+1g*J(ymq)elw)cEif7@+O5>vy$OH~WIuUO%)6zQVQfc> zPbelXWGA2CQkekwXC6Jp_iy$%vw#i^B(@2Ap~}&=pI1{bX}qwM_cI2o6X%AxopZuz z^rH!>3$JqJrkUf}6bqP0@`*savhlCeDWeuY^yfxa$BWROu%$~dc&AQh5iGoT>jn7duFx9Y1)*AaT z2ndD|t<9LertzP@i1Q82I_byRe&#O;}8E`;E96!8^67cx#wn zpGyg~t{S&?R2Mq^4O*_CHj_rpe--8I)8*{|(s9VH&&X$WVXgH5u&$smzd8aK&kG)t zp!aWfw=LQ$ns4ru+eY`q_T|xLx-b#!_oxV*=OdJi@n5}Z+(qBrdB3}Neb=uITy4K5uZ_7m zd35=BPd;n&-{7|f=l&s3xvM~(Jt1v>d-obCeBKr(FBb=|=kbJ6s+5HcJa??WJOfn@ zQXKNC@tonZ;~X=P&W+_--#IF3@#Bs$y)=dB6Y_SrkM_5y?rItFU}{=E(r3?+4eN|+ zMO+~cRuhNp70{KWv4-1E{8}UQeTxkn)P$Q7JaN6UUKIi&^ZM}h!aD|_`!>{L>>R$M zJJ})!bu;&Oa@p)=rwT_<^7aMrB|@?*QIo%47tFZ1PqODW#~es%xPhB%0OA%;uW3N1 zePpmErJl0H75ypw{kZO9sk+yHP)b$to&Z8zk?kG!C8^(v__nql5Ry*P+KXPp<@a<> z%QI=)o2L)$6{oab*KP}=&ByqazyZ2=dw88Lox9If5^dp#}mmm+H zO9Z#YuoW!ug0Wo1V(h=AMkvjKTASd}V4Ixi6HF&Nb-#mtp37Mqgkx8Z>1>u}{Y1s; ztko2Adwr$|uBL3ADah$U2FeGp#>!~9M17wWe@7Rc%XAyT!-uWP!GVQ$O03|ZQ{yz1 z)s>(@?^6JY*oG+rvAIpn} zmMrEPUspCiEj%{q7s%^VT=cwn8{fAuq=)~f%zcfPy4uPHFjYs!n!E&p)wq zEScK*($LkZAoty#e=>6RzT1YQfXU+6x3UHvpl zb2?lsnLgkQyJV?-#J}^QCHS_7Vj0?Zb2p;*rnqXio_lG)hdi;`u%G+1^b=iZvpGxl zUGceq$Bu%>yLtP<24wSKRF;ENI{sR_j>K$mN?v>?Jt84A{wnHLDNI!@Du2v**TgPOQ#=Mzv-fo6NB-|d$tG6yL z%=NPm7_tP;Z}`RV7C+fsEnLKDT=fo!osr{jjfDSJM!^WGs>I6dQ{ic#A1K zWUo={lkO^+sOc+hC7>TA2{|4j8z44`9Q0sKT<9?6)yHH>cT%%UWm+n@IJ{`qv50z7 zdyEtvCOYwn35mUoieS^aY0D;^v+ZaFP=bq2Ol^_x25yk+z`L$=r$de1Cc5dw#nPHRHgPQ& z3W5)Y)@+J7J`$<+jAQTpaNH=>kSWj4p>X34*)Kb~(< z{{TkZ{yTO5WuCZQcE{)auKSG**YCx?;)S82AvT)EmB6=VF@piX>hdSWHLlbPeT7(B zWT_AN=BqRVEK@1vl-ghn@1ug9_0xKXXT=yMjRfs)zBwwTri<=mMBd z{2L=`vs0=XOvc#l3aqC$@!Ig7yht zzd+8KX)ztANbT&jd4mBuLizSB3-GGtNcOMX(dn49R>J?5Y;D`B6;Qi8_Bf|{5ji8S zRMc0{S0v-(TgjY6x7kupL2pm#jIwfK;}!ZDgge#i*tf-kzSwv3oQ1`eMMEru^I+>E zn1fDmJIJ03Y`cEhyTWO8gmV|wG6y<=B&v&9X3D_--2XMj2iiMD7WLv}mpI$b#P2!U zaZxy|M6E?D^=)cDieADZh*mi}4{cD_t!zGJq!xls>CoIJ54JVj9YI(84=}{eZP=L{ zX`1|q{Q|i8d!ZOwKH)~T;%O;B zKQuBqR13e6rHVe|ZD^M_^ulcSIHG}3SA1gTvPOoj-QA0%t5Ia5O5{-S<}Sop$Ozch z^wKD+aPMXH2#6BDTOWB}ZMz;TYi6GluBnU~#+KCVayfl0(ZF^|ndCq} zO(BcsHigTqz-@0BX1QRj*P*_LB*g@0DXL6wNhh}+ze=EPxKci+?Pw{IDnz^zga)!O zrxn{I7)cfC&Z|JI&B5a8;_s~3b>iaDj?Db0Ee;W&z3)KT zKtXMqkQE&wRjKm5twqkVJa}B*m$*+=KeVC(BqQ^9vmB*Le~WYEB4ys3Sp9770}i=( zuur_8!I9dM@2M}rM~#Xe59HXO??UHB8jsx;3zA$v3yON@n_&6=M`7-{K9pZ_7|gLAShnQV6_;~Z&R!H%l)Rt9>&_QgpYsEhs>Q* zQrS{wjvXMJ8y_aHNJ15WCUX5eC$Z1Qib`&b5-oqtalo>066{MyUpU!Qm<>BCh{r2Q zral&JlP`9m`!|1c{Ys5FYx&E#R06kLgB>{Ow>CQBa`{+SzB>U8e*QJzrj-R!Y z$`wRBZLH^$#;W-sUHWd_SarOtihrD>7c=fd@V(ABV?{z z3ehWQ*agh#-`}%qUH)FHzxa7ih+?9(OObX1FXf|^{BhN=X}tr@7i;Q{zE6s7j(+k7 z*3F?kh}OKD@3R!)woixE2IFEt&BIi0HL)UJ-><2(n(sc2QBu)t&5gB+{k2ypdNg%6 zU(_B?usKNnTQW&h`FhYOw~7=_NG%fLpk&79b1^SVm!+EVH(K79y-_LG#l##_+$;t1 zsIN`1g}n~+uU?QHmncng5yzk@F8$m??B9fq^WhmJd6VDa; zkeS5QMLwB^%(X#knVvtdmH1~#Kc75ZguBRhr#mpZOk!q}3zp>Sf>pcdcCs!>udBo< zdEf8ce%j!-FB?yGJ5;*HYd@d78@3TQtrznWpm_zRk(heXUjxeC=yVEL>4(1iaMKta?;&z6vU&q^)-`O@q?-^&b*_zK+H66!r2-7-^X=r92wZ%b;={~SozqpQK zEozASr9g8i`cdDkYG8;p=#<_|gktDF0me8F&z9q|3Out^r!Cq8#Rw$v`c-QMJt!yS zL};o~h`WAj%qMv#{LQQr3UZ^f);Ow*LRUQfoeI{;Q($c1v>M!i(d%Kc{IzhIsjyvQ zm^>RQYz#s%@ zt?HS`P6L@MVSbb(I4w$a35-;!S`;_Uho53)YM3W32n(N+4|~>VO}(Betxdx#Y4&1< z!`vv;KAtMC6c-Z-=#pcvJ?_ik^^X#%6wc|}db_m-|1{DpYcUf}aDo(L0|o}(MQKmF zvJu$GTy&@T>IW)3?T!^DxJ>f3FRNX#u*SiReoCaB4UB7^aT{o1$=}~~@xjWnA~n2^ zgCHh&TWb128gD;ahn+Zz(cA5N=6hdviB zoX9g84}8!Xw*5Bt`ADsT=)-Qtw_+VI$t`T@=_kb zP1hbqF`R6SE^yjuBcBm~D5^$_ji{dvwN}G)QsvEbHcSSwV0p5H9k{}29D$+uynXQa zUWEQmg++v0x0<+ocP7aojB3YO&7XC+`UnWTQ?H>lMO?K0qCd_pa$Hs($ee2g&BTLPVQvtxav5q}i8i`;#u=dN7t9PnR z*7XyIDOqpoOA*S~N4*K;QPU}bwzCLO0 zBICI|L2*F}Tp|4PXVw!|ezJ-RR5hVf<%;#P&v?Dk2G_4#V(iqF3SwpQCav6C1y+ux z+wv)D{H@=`|A^BA;hv%xR63cxLI4nk6sZJ z(4X@SV&)a&hXFpS;Y`y7N45H>fo7=4qQd#JI~!QlUWEr(qr(JT~P8xf^ehs&|aCzcl-;lkPjEElZlrZMOKvy#ZNNgo(L`RB$kxVLpWq|MT7Tt~P9&wA@P3l%Z-NZinVm#Uoj-1>eBycR z3L1-;@L(G#l0SKamTc!slVqN9YscRAfDPVAJf_aFrvxW&nvoLxviTc{Hg07o$9YxU zTl0JG0|5)AXhzxNSVqC27D?jrDh;>p`LzSNJf}-7{CJ{#cQhe(W^>LEASt<@UDI`_&wwq#IsCyx<`a{fsh zXu39QF^P+^qAP#tDM;PWK7sU?XsWf^5H|O)W`faeU;DY|)L{gXZvdyMh~~yA$Q`sm z|GpuO<~IxT+{f%E-?)1k&74R6ev5R9ODMZfv%VPe$$1hE`DJ6;`N~|j_q|aNI@;;4 zS<&MEoHJ8G17oU=jmkKyz@83Pus=T6We%n`>-s)!G=EsRjd?b&F@=V|ScYJ9JlZ6z za!;+d)=zQSo7GP+O_W1_{h)~vv<*!D1bs>dG#$g3vuqT{G$fOxnaG}|QHx%@yRdRB z6OSUT@!Qggu-6h1G09G^S78w-yCYw{)sBnrsK527du_Y%^O-Sqlr+!ttT%rmF-8Fc z`E(TRGg({O`v0L1&U0YmGHW!3(z>_q2{dW?&sai6dv`52Q%#1AWFl^ZfGol5pec%% z4`l^c>JsYL&~hkeCex2)bso->p@!?%qi<=W3-R+S^U?uIuI}_y6RutEGk-r>G>4lt zz`!Y1UYZ^zd}5?d4FUhTg;T{}zMrfkkVN!)<`W~TYq4ph#Hs33$m}Tj z#uPi?*OzX(1e~7oM7xvvy&iUcXhZhk8Nh2}0)vJA}qDQw)SsJnLD*EoC zzpi&Dsb7UylkUatQfPB`OdzB&!Xt_WEqSdzAg116wRCt|&C6w9p*1JTNX0qYc$bO5bRK0LgcFuuI#g9}#l5c^7 z@(2lR2EuQJUB!aA5k(G)d~X|CQY|9k>R|_(gt!cEXh}uYCLbHX{&$a)^r_7=0gPa~gRUvEpxi-zPtOQaqX1qe1^vBM?M z;%C{U@i>QMU-ySBvCQ2kM_1E-Ob2y&Tef)ERV~QRIwj}Bz>Stkrh6s8DoZ1UKd~4a zE^4}-8VZ#YX#Re!qj?qLZ>y;fUhgBH2$o-pVG~LkeElh*>c;EZ3RbN>x-aV*k*shk zHljKkcia5)*@Cn{Hk$j%fvoR$7A*W1S}iing%pAC2|I03!#yH)z1=bV0sit%bHmB^ z3ImK5Pxrjn>MPFDIFx(r(PmI4YF+W7m&}nBA4k9G;!JVusgAz}1Z)eGC zD~AZI{sGim8^I7ku7iFi7?A{8K2-t8q;Kydh+23y;4~>*YDjUbe~evK^k}{f=P&Wx z@C1I=N&fZfi_1gRa0*j%A=G?aI(tsvZo*C#FL^sLLX>0S7lj$OPEYgDK%Zgbn1tN| zh2X`Xl@Gy^<3L4bs*`SjijgSc&!pX}sE77%1A1U>J;{_(I}g#QiwbMHL4Df+@=%v=P5zL=D9jR z{6zzTBK79w&WPQ+ni+v8vxRxp2F8%lm5u;uYZ2;Euiq*mwX+kW87xT4pph4BL;hle z(L90GHAzMp$!?Mb$<%sxnan)46H)|sK#PJ42?|ABUH#4ZkS0z1hQ)EIkuPn>hx5Q{ zB`)Qb8O(VZ_Y*v?%UWng1IhcL7L)_c5S_?=bl`fIJEfNUMS|k*WD~46FEa*{aDKa! zTB%%7^BZ1Se`?9ZjpRcPVSOM2vlT&9U?R_a3k(OvFk^Y0rv3)ygck4Jj4Ve$YD*NA z>_(?eANfHw3*Uw6sJ;=aS2!XV(%W^S#xLv=?3xT>5uMOqBfpg#CQ~kzxTD|JB;U2L zqGK3CM*%Aq-=_Vdmr;K%hyDTNNxWWNGBl>I(}~U)d?g)!J^eymU-tI1bIUk7^Fv&7 z2%#Dt#1NS#j0xJfOh>5VSC=09w}@Hv)pYC;+iQ zg`>kd1n(-eZ-@%d?>$83&&xh>ykcK(ok{v48i*VsAJ)pUf0fHg!4YP% zgK60S5N0o=YR!y*Vs5Jk7J5zEld!%bwGifr9JpHu2u;<_#+bGlu>kqgGiuwTp0^?#NWb=+5K6t}oiha&$0 zN~k+_2tF*aOmhhM8Pxss&{L|rZ=v_dBw5!r55*vUwHy*#wJ_AVE`hzd9m>Cd`F+u^ z`pXXeH>>wB0cu=B@ydz|Ezklo{Vbo7TuDr3Av;D z206~}5rIc+!RWmOJnS6YYAt^&QA%uc`7*M;z}%_H_Pf(adf(=%wyzhKq$BqGfhVm= z-5=w(j-mW(uu9z#FY*z1<}SYzIYI3JzG+RP{2K!XwN9}rPZgO^O(g{m1{BZmX}3~$ z@M{lz+FuliX1Jguw!*+b=kL-M%4{9^F@gxeeUCb%M0diQ;NvFl@@}kaxj}3khl1F% z_Va~46_R}fI-*F?UhIjOG}?`oJO9L*FaY@BxnAB-{enq^F1YK{?cfr+WJH!!P&n< ze#|>jT%tg(5D&v)1iHDJ#QDUa|E#mw&up?&3og`jK3#Uw zYnZ~3V_T5eKHU`+tg!L+c|aBBQ?J1**uH+%1WEwZ&<>A(gOvofuRjFi8c^DL6#c9) zKKBx)ixGgAT=^)^GS$JZAA`STt-hfSnc)`f+{)&b62jY4H>r@Z5Le_fqrrW>&T5ny ziDZsQv<$=PxDYBqVkm^A&Gx)Kxhy{t0`5*NOkV#~52w(&iOSErj5jd*U?dO6iWxHL zvJbGR&QunC0@X9vd%F(aXNx!#otn$?$OC7O7k!`OH)HKCN*7D232z^JG^3hOW z*A!tQeOASusLd4QaO8eut+ffEx5vE5%&he$KNDj!Y=|(IU9etmksMy=DJMG-H#0$# zxQJ1&fqm9Rk%!eeIWf86k)P)7 z9H3$@s`L2=&=2BeY(2)#v8`b0Y=pPew0-z?vmtU|_3`y|k=$UmgW{P0~g0*a&*eQwE(VfZ|miAN;Pj?T^Ufn_sd2 zuWI!FJrnT1s@W&5ev84~Sr3Y!67_Fjt9<;y*B{S*&cla>L%jdQI_3J$Ml#%RfUEwS zw;K2T@t0zb@u38ByOp}&qzZhBF^TiJrY3`r2NA%N34D5NN0+`jr=#UvXHOz+`1n>$ zQ+1H8RU^EvLFw0Y;n=X$wYdr5)^3f{hE;RMOT*`QBW7S+F5tD#7vG+@>qEf`pabA+G=iqf`eRb+O)qWO-zRk^Adi@lzEz^JY{E8mBM#ej*D_(!& z+LYLvKsq7bc@QkVS@)Xy^ha{% zuyr6a-O*mB1DrlQ3lG-XyQE0wNeGC%Krz@J}2jym^l!d8lDxPA@KO4 zokWouoQmjl+8mu7HT`y1^gjMARWx~}YC5sYcqmT1A`My&5tEUAwgX6bO2x@ULF8Y0Ac8^_vlGY zj;y4v+obh#-^WAW4fmolm6spy==PA?b|Gb3uKgp1yBDM9LU35$2PLhck5v-{t;3FW z!>`y$x&zpUUO4K;QbghIpiUiK+L<%jJL##izQFnH1mS`oM9}Nlo~QgKC$gG9)+HqN z3(|T-1zLm44&auiO^$J2H;2#*WFbn;N%$W!Iv^m-9}(RQbB}7uBllF-hRmw1m~Y9d z^)hnUL~eQcvn(NF_#)2^zrc;!%N|a=eY4JY9Hyx(r)e}&MGg)oI*1mPlk6v|)(>UP zF?`Nk{(2vK|Bz<2tIiWuTBtU@|3=De)qL&m%yZdhq8;NX71l>U4UvG#O)rRe{`uF(p2r8TB-y@ntGU51R*L3PcSwIj&4QVksG=}idk-C@ zP*-ZBYqM}cDq#LLO%wxZ+S5Ba1qJPXnr)(=d8AeLNAD!y;U>lyo}ctpi05qUA2GYS z^M%)d*sPl7>XjHy!3D}lNBKwo+IUqAnIZi_7wzzJhdN(}Q};>AD&a?GVgLhgfOGZ} zZaM5)G2Miq(J0=p^2{h>7f4|* z3y5-;gTA=maj@V>Qg=!ILfFN^cu_8{;my2ohDMzAd!xxV4r5X{Q3lM zQ1ypCTPjzxNRcy3;8BrPs+cDz)mmpQO0l`BLsbMcp^S`r4E8BM=sk8Tou#MC1Z#45 zSPXeN;HV!HulldNCx29dUv6*-H2*$R@RchZBPjKr$$o)?zj&s;G*4U#Y0ZuM!uKC{ zqRWPrSUIyywh0F1rnXZDbvErUDWIAZCiOYw?XPd6&OE`}b)Uqg3kf*ts9)~kIX>u6 zQn<(fg)DUzrK?0b0JNFdwjK}dB|B`Wdw(sFA+|-ZTHRlWN*KqbVMGGQMe?`-F8QJL?)?(-Enuj#WIGwZa4w40soeVi{uwoxQN4<`|gW>xImP zfmOw~QsXy#$eYJDDc*yGT;doa_aG96=?xAQ>&XE0${!2Q+e*-N_Kv&boA6_M_LOxAr&p^tyeyp9$sy2B+ z%o6cSQVf1G#=#|Oz8&g-^Y>@l=%!2!nfLx23qVmcZkdW6r(Z_e?ND(^o^(R19*~X5 zStOGM~JWJTe}`in_Le0t5%Yb%~AjYLb$&vAXj-lsou86sF7I#O>S0$S%>(OGoA z3>>tRhEHa1(6gQ zELLPm0-yU1Xr@SujJ*m|l~WGV?^fl%F>Fm9KiBVe8r+>7axh~w!7*pIOiJh*CKRD# zl>qi?B{gZ4`1ouf%YPogRiHo>!oSTCzytMlYMjlzJeR4lH5FoooZZT0nfs)T#!iT| zs$f7oZw?XcHhJZ^?-O0w<&)Nje}JoZvr8^b6(Q&0XIJ*WgogY*3i30~N77-(^Hr){ z+xX(+Q6n*LwM8(2SKdigc#oT3riEU=@D$7_dwsohdG6BQMYu0)*N=IRO!*o**~AYK zrcwVG9TeL?c5~Zk;b~hBHjJbW>FsBdb>ti9-JNFdxvvXPqZE1^?G;R(zD6y$MB+n@ z+UguGZy&G3D^OX|Ir0HxWN|mCDJy)&)Ae3w1U6Kw)#vc`zI289;n7jp5YKa(ZY}1(ckjkxvyGDf7 zPQ>N*_ag3w#NSXl+WtD}gXNiL^u>#A3mAVmE}E_jzD+kLbX4JUIBlaAPB8wU z&>II#6CvtSAAbTveceSnp52>~)(v=xI4w8hK;TjvPSrUK&4?Wa~; zNM>Ao4_HtERdr&$y10%Pd#b9Rj-Q?o6hMTNZ=&nDrt|>_g;;`_i!LUus>;^=Qs!hW z*qKjGwCyTa`5H(feWzdue|`UshIjAw{jZqB78!J^jzo8>Y-jZn&quZq`6q=DmtN_g zr1>LLgx5Ez`ggF|G+Ra6H05>lU>Jl zj=SMJ`V}>XtcwJ(l|Mfs^&O12L>S)mYQOl3L~b&Xjq2;-+_~gjs|+Jw z-M(#wuUHWRS#Z5w3lpAwY}1IbRp`J`jYnf)6kU3Cr_8PKTQtU;N68erX0no&RajnL zy?3PF^oP4%43zJyHs4~Wxp~$2&#!v9Thr7BI%O`h;Yb||EQj&?q&0*7ma{~1C6O1D zTYrv=2RRX{uGi1x7qq`xhVEC5z=IuLANgOnl}G(DhTdw|ZK)YDnVz08Rus;L;J z6rtW6(@0h1!nf19kxT>^U%7%QX4X&?f4m^`udLFzn=$Jpeu>A#IcKkG#Ix1Z9Fy^R z8g=P6)HljB2a0?a{Hx&FZz$CZRPQD-%stBUC%45lhj>;m4ABi(MhmlV!PLL3){y47 zAv{Geae{)B6Fu>b+FNrN1$#Y3cpgDAlT`w7ZvW z#`#A+jjk!I-6|msq%Xvhdl!-GoMX)<2x>Kb#wYI6w`0_{2>03>zqJw42>EiDW}w_F z!wdyCO=bbZAoe*-58?73X^^30@o1p(Q65Y*F*Bb&gVqC8YNY7q)To$d&G(b0CL=F7 zy7TX8r9JV^>as>0Jf5e7O8@L z^-nN9`7zRxL>TUC_Na{V<|zm1pb&$g=sLl|5?z~%U5T>-eh-p@x%v5ppy21(@yfyg zXHVKx`apf!#j@xk$+W_q%PPZXR!#9F)aa{oeO^evg$`pnBMte3(@CfShV{oN7|rnNp&egM$liBQ{V}!n`?b z!p7v4|IY#`mSFOoh^=(tYR#t~C~IR~?WcngpEg(_bD%3s(tN+KicD#ytLASjxM_?2 z3ZkpF1-yt$mspMt#>vV9;(1ouo6qjWq^M-u*z4&i=67`m-8qFV*R59>nn;MZ&%SA=Or&eFZO ze>0^5$o+OmO$JGEW{(~viy14c{1R1RoZHaI)%l6%&BbpB-B_J|C zq+MVqS^_^sWpKleOq$c-yZ-#1zcJD9 zk4EH0tS&BxpcH7*bbT9;6*PR1mOYk!@P0Ed{GJt4^DH(r&)6^W`Q&ReoXp&PW*EkW zx~;}7!H=O1*(&_@%rs-x60|(|fyWL(i;$iE;A^K9&(UX=)Mfg5xy_k7ITtuBWsdMn zk#BuamlDmED&rY-zCLH@m=iRu=MJ&^z6YcXp9$bAsgM=b%{S0DRH~mOfogi0WzSd_ zz?VNDw+A21y5Km@lSPa1!5b&pc2H+ z>k5a_os@2e_+o7z3r=7I98`7XHpTcAZYzHKq!lJ<21{D;CLs5#YqX_b>A!D8tjDP; zP!@7~#wv2`m@TnUSwmdWh%{O1Sbc&A<3W$tRA1{wlE9yu$ zxby%E369JsR@A{t@e|$O4PXTy7pIR@^!h#a;@g)L!`oYeXlIhht`k}P;3;mOS?v-FM$c}hs_la;+@3wApuOGX>-%6r{5zPN$CuYnx zH-WWxC!m(gfYm{0xqbKrHtRr&UPwy7{+l%`DA)zNvR6^muBnel+RT^(S!;}1VPpd2 zDH>`QRSi1AH#1f&;a6L;m6qU_l4QC@X}{e~zep$KD^{eAa=Zq_7Dw7;b0+yx6(8me zpaI)k=Y8_x^@B4Z;1CAwXnO=KdYwFQzbUzuLX&XV@V4Us(W}+c3*Xo3(RQ`yguz!x zf+X&gcc?xJs*U!5UkMh#M6DQ#YR!t--W#?xYE3J>(||pX(s1;7S?39?_L4`(%I3ir zg$)i%sw^-1)$|T{0x&xb%eWDN7Waw>XHYK9HbRw#a z5~=JB&7=?QLWC|o_Yb#WBMNzN$-EjB*A<0hTO4jlDt7*agh4UuWo$SSO7S0HivJeJ z#QdkN=}(8b&(aW}hz^ph@fF#82)=tilQIx}@QBriv>{B1o+5n%s7y%R?)eAnwW}?R z=P11+SO42f|NB4w@l_)K)d}ylUV;2aiLhXzdxttjG0GHYQ_)42|FRM{ejPQ&6)yBmwz3zf5jx(!a~T zT8Zhal_F0l8VagKCHriK5Hh>fQa`wXc2G5YRV#dJ34{={zu$Q`hG?}Wp~nfvV4?s{ z?&;agUKyX_lxoWHKXfiUzjhz|(q1>qN2n;ze5Ekm599xB8W8fDa!5g7Bo_yhJo6&< z<+waTJNs4s>=iQZTCKieJW;tb@aA*Ei<`sN>ODyrn417}jxPDNy*;}QnQK-8Lp%Z2 z@9Tgvx$AYjY!_|5>c$MTnFwbM}R5mYYSIR(l+IVYe-i! zXV*aIDMQ0?c1AH#9gvLG#Ezk<7Jv06D#mCklx_%BP;!lAi-Jzy0BK#;sd{V`%yaco zeJgH8(W>u(%vT_x@bJ;*D*<|pT2O2ntgxB(bI|xGD4rR}1?dQxix7t%sH|uE30pKZ z*&M_4c3;zS(sz8P)OQL+!1kE37jMecTY;00!!fd>W-MD0?XU)Gt2xd}i#ll1c4K2B z#5&Vn`kU;o^fG_*I?ML@gQhXgtr$e;c&u@H`HL0VpmhQwb!~58FD89p*QcR*a8qqqx70YieY#vDZ(Lre+e1(tb6h%)Dg9mWa`2y9wIfXoD$C zOFQ(@i3ngCOpo8U7fsoKS5o~wN%MzR%RfNMMyZF&>D)y1#$k+r`keSIk3rf-&e6sT zz(WElLCgroh}X+7FVeEf4bs9Hj>^3h*_M{pH2REVZ{1`V3$uns@EF-=fV06xjtY8p zM8j*|W7hFVRZKZvCohDDmr3f2E)QxeR179^%A}t-<>e$+jcL_j!Kx&^4Qe@iFk_r^ z;(Ho{6SC=Z>ig5dm&OGdG~OpnnN)(%8(_F70{ifM zaKAvyVV3zE?6@Dq)iuDf+KyA`WL3CSn6diJ{&=UUDcD?9nl6DfwS2hg1xlCUUaW2B zbJt@nPDaHCa!VYF=KIZ`U0 zvKokOk>@3m-4U=g|D@X~Xgv~#}dKb224}Pg@PVP8?uKWdd zP3T=V=#SM{r^jOOla7>aeujlAKMC%A&8H2UhBOkZKpuW%xLI{t!D&1jw?sT%@WejZ z3N*Av$>{5orP4OX@_kMB#QHga!hl*TYIPgFrDn_B_TF%LntzEdbV-RPh#)~%STwzS zA77DWb=2`s5g&{`h);<8*qUJ7zwPzDZZrLM<+SnHKR^(Zh&=1UB@b1%NBymg;?zk4 zyZGJ_zO?$ptZr^Puf%VLh|!Cym8>rF4}%2#r)<~H9S)fqb8Dy7=67&#kL?kG)$~uP8T;3N&JhL-$5T&j{02& zcqUjWEbrGeJ7l18cBZY7RJi8v z(VO5iYri|vMhtT5AHn)@%_L-XZ%!r6&yAzs5_25(dY?`|s)22Z1ZEEA&wqtsG6wwo z#)=;>&VyxwVYDZN8aWf(cPw5tKU_QkLW?79#vASaww<$bgh-;J8Qvc>U=OP-F*=wR zw`kM47SO6weyiKq8a)W9f%9hyd>*WBV1`BAN|#H?ANqj*+>0GoUfw5{`n{YxswqG{ zx*mA76(dLel4HA;&Dp~&FyNz$huUl>gtEVFjq|8c!Rf}O6(vmg?51VzfCXu^h80v) zKDi536L`vV;u$O%63!X{H51Uhle0N#Ec}}9Fh5|uiGI79k0EM)8@@4eI4wh*Q`n2Y zzd1%{BO%pD_erdYGeT|%BTP_p`z^MIs|sYXygsS*H0$WbIl?U@Tsi$3bDx?&qrira zE35V9JI(nZnKSO0*-mNYBcB^_B$YN0A^Y3X-I}e^2t9|+`eHI2=_PFb?2P`36r&(7 zHu<>~voO}smvXdl|JtTh6l7JPSoAtS4v4?WwTtsZO|)$*yWO+sR=K-;BLji>&6tf1 z``Bk%GuvMP+)25sA^pkZPoFqD8#t$`^w-h;U~FQ+b#U&o7!tXzKSCdAUC8zK&Dl^L zhc+D@3pcmm39E?ibi=s590X#huN-E*8*8&8>{2&0JygdycM+(X)IDss7p*NNMcq7R zbSrNtsiuE-h4#)=Y=eDBZ4~Pa%smLWyBkpA-(nIX_;evM*e+Uv~-(?kI`IaE$=>XC@KAL6n5$!k=jrw zI2~&-J7}%a+u_K|7;%pzl97?pS(P>+VHP)hn&6K{fvL(|-3JDj*}yaJL7{^gFDFWi zmoby@q)lSY!lYG5Gwf9tU+Ao_UzYH3zR6P77XI1xF?rE9pXdk_=6Qee4^V_`tp{v% z$S6qRYRsY?oj9BI2uNzyG%HHXkW>;8ST#aCt1NY3zH!Vcz~4f5x~~9dljC}M1IU8d z82+w@E@)z<@;G+=TaiQz-FH`1Q|3vbm4S~+?F1)({SQ?cOe-shoeWmR`uB1O>d=Ee zF>}VZer8R$sq2C&SBa?q#XnGxBO0+bX{Or-TSu1^uSkCQbTd`@r{GG9bVz1H(Vi2% zH&><_oiLmbmIJ@ju}R5RU~DuDf~~0o_kKd&Z2D`VSCtIrYOtq?#B?&@I&VMwzpZKuCNx; zL=&TB(-=|t80G1{{#9oOA+!yB>q>%o0+f#QnBUlT*6P4Y$JS)>lO}?MT?79lvGXtA zfy1!ggSNRJ7rQ1tsy-^wD)b)!Vlfe-@1$(-&grF2h@kXPU*iT(=!04Q9v za4~FEZvEwJK&BH4SuESipbxW%5o%Uue3{*yh-F!t6f{n9m&Ix2%07tJb1V5ub@-Jb zk4$W@BJ7BEg}%;!6msp#D9!d&mO=G>kP-?zVvW7!v>nz$PD$AaGf{l2$6jzYZfo9@ z0D!v>x3Pemo>5~vQuj-8aeykP(Rw)%G%yZrrMEq17F>%cuI_Io8oEv0&8@6ee5^>v zQ>Gg*$L--4DlqnfhWfOkhOpJ?JV*IDz==7i7fAV{N(r~YUR7cWtDJ%n_{!}y{yu$Y zd)hAWCoKcA(MBd|URI(S(<{gnJRd-YdG`&_MnA2S=jEn(=Jl~7Z~nk^i^ledPM*%%Rz#)#-c=;Q&P-=Dy!JR zLU7iw71~iZwj6$!CL&YK`Uz@>GOE z@ESREH9p++*0a9;P^@gS!=t~9{>~w3X?v)9c{`bj+)4~^S!}rPzEC?zUg=y)(i34{ z5Jk6UhP@UGjQD?wkUttT>_JD&={7% z&EL(a2VM(OappFR4kCxFU|W59@QgO_6P>t|Itgdzt@|Fy-%faW5>v4|eG>He-e0z! zGQo!8tgUZG5sWlJ$kF~5lP~Ae+@cE*6x^4y$k(yCfXq*GHyh@=R&5Xq!2^H3Y8N!X z!N{%RFe&DY3%MsxXBfyG=XH@PmWXo0^a7QQgchU1LmMI!3n&ug8mU=C70{y_FAbt1*NB6hWs8gx8Jp4~g8Y2)UHp*7{eVbvaC z<1}PEIZOfQTw|HPv+<|sGEmAWm z&CWq_xL;-KTp!=~>*IpOT9L2GuD9VJ(wdukY-Vj91LE2C%l4vKN(dhLh%Dglr~Qf) zU9hv-h*>Gx@CQy9q?4BE&;dd}aLE%}`F3ryjiL(Rw!+DYlp!;Q5P|n?r1igE6ZD|z z&&eNin5iwkK_TtpgBkaNN^TW;y<-LvK@M(&;|Zan@z~IPGc=imUuY%Cq4!G>y)4K++^;)3@y-p4eY3!3_x|?KChDvu0VjKt76%1JrNQ-VUG}R1sSclG4QzTH^N(|i_{L8E`%({xIhgik%wp9m=FitUuJ0c1`wxdO4UF>M|MHb-p1;;Cs5Vd(YQB*(DosXBx z6b$f*@*RZ&BFMbLweP-&p?@Kz3!bU`BmQi><5HE^Br7Ueu4hB^z9I$Rc&WX=zbp~I zwE1P+QsIya`es>f$(vPc!2#C#+Q>~Z61tWq0pd3S3LjKj5zSoy92*qV$P0&ewgX!_ z$s>FE;8h(yACmPMv)E5-QoB8?z#XjAWgUC0vNxfJnTsusjXVcvb7s@pmZapJkRUEU3X4bT8(N@Ase0yjhX>KIc_R*cFAODv<}VKH^*G?@k&5 zui50DY>d%!jz=sf+WD$rx9e8Yg6HXnABg6y3*R_a%Ow&o&%cdi9v%ZeQ*>&PTjDfz zmC&T?l1lSg>?LA}s~&jp4zyQD)XSvC(Yxl$z!&m!_&!D#bRG^Z+}Kffadh3k%8*^5 z4|W<{nrb;V(zeGmaX*#*VC;l2n`5qKZksEtZNCVs<%lW~2(N&z_Be1TM3n|BLTM=! zgoXhjDt$FO-kRg`AX8=XKOXSdVE+f?3Pd|L$cs)LwrY69!weep5>gF~Mj7rd2b#Ec zCjA3oW~WGbX~kc&pP?{G)dIK54C&(;*N#aRfB_f$0=yWv8i5d!XUh%S-88Acdbs{n1;MzxJW$2=tTXAA_3{r zrAc+)sfm(@n(E5bi2qudn@TP&P&Lxt#HJjT4F59Y_Hrg~20USL(ST-L+wZKan=>k? z8Ou}5}Z(8VL8x)ZBf~OBusC~Ret>N^+>k{T2Q671+WM(OCLbAC(8T9z!onfI!U6mU z@HQmu@+@r=$hD;;h~2y%nb8+10TVVizcCGvp*=x~Llt~kI{{z{)bXC-edcOco391R zl_1&^YqZ+Zsa7_qF_J=XKepoF{zXAel$hIJd+eM%#mHM|L~hKIpRFpVjV#?#I?uG? zE#@uK@7c9>^rgQ>Gt?Cbya}zz{%)!Aifs|pSJJgU)$rje=bcSG;x@v_R?S9$lg$~C z|HbTskFyy(kc|3Nb-AW%f@i1!iC?fW7Rx90 zr(3|N7Aq?X=6Cg(e=8r0%MM?l+P^AUviLAkdKbW_HGrKh5+tI01T6nkz2|fIAQzqT zLxC+s#_`4T(Ff*SV!I;)=D`u_jubJD$cstL(G4*xgSprwM({khJ_!>9f8eiIn8;q5 z5WNe8=X{C&^b1E#B=)qzPgSySTX7Y~F6A5RE%0&xU8!l#-lJQ44+NiH;fMQ_w%%S{Kwx;FCyKZ}=T^180!YIj_6 zFM1fA|0dN+HuZD(1nn_$K~8(C49!P3Z|XW1{sHQIq2Wi~KoZTrn(_F9V`}3U_TQwX z`Kk1XT2W{3FOl=z>bxd>Mf|_2XHQS7WpMU`rHHRamdW30OL0EOz}0KE&mCRrZLOyro}GuG+Vp&;|-v)BYb8^Tj3pYqD~ z{F8a}f-};`!)mLCH!^%i$6p*^MvQ@F7=jHE!^{!jt(!6mB{?H>;fv4S+2K-N zDG_{x!r|BEE!_~HqFN6bh;o&rXY>^qbvIt6$pDO^rAa1n?vnOSTR0^OqUuyR%CPO- z-Xk8LFjzOI#TqKHsQi(K8I8z}e^bLOU#}dwb^kObEb!!SJR`;!d2T4sf4^JEQAm-T z$EgKkIoMsL5*M;;OnQSRjn_?;eEUNM5>D;km2sUV%!v(jzc%~Y*5C^Ds=jQxmT4~R z)-PsM=CQuZtR2<@by+dEK6h3H+YVN#8krO#MM=Uhhi3n}KClZb>YC+f&Cc-EMKVVC zo|e9RxBDiXq08M=?hl`@0m>hG%Ks^I)XRi zcyG4oL9?`7CcQhNn~{@|KSrC4ME1nn1(v#E=-zZ}W$EolxF=2-)qD2m9!AV>MA|u3 zxf$!_;JPA)zv`~im(RGT?Fz?{r0PINIb=n6di1Qm&~-cJ9(d)z;d@d1QFfh2?uM4d ziIVU$TI0x@WYOqZ@7F-&16=t1hgUmewR>Y<6r(`j=+KBTKE$oD35GAyq{K~1&9HC+ zE_*fcBDzxLjK6`^Q*U$NLA`aFE0?a@^pI@a^C*^rq=g97s=?n?V9yY-g#(8OmN)Er zw-ff*62q}``r2{FU~Ks?WVGf7B88+2^bM-yR3_GJ$9z)yO!M^L8^>BYS95js3*cSt zc?a;GoK#H5Bt`}gDHUL-*nOGnd$A+QFj`?r$E3hj!=!v(ThIK-paSd)`3hoT<6mNn zd!bB&=FCEq0;MwP1k(4IFjyR`L-%M6#Sdj#VWQGEKj!>2g? zU)``|NGF^H%pF~uj?0lT$7%Z-+Dz+&L1K*8WM8bWe|ip(9+~06$KI4O5}<{u$f=>2 zG;vKbQCRT*{KlLYDf$1ane6`uv(+MSx>)6IDPNQ!4R`$tX+h2qE?B4NVkg!mD<{T4 z(Lp&;F;PW#2>LTpgx9X%qu{^{w-ORk>7yz3<{Xu>5KRq9!djV_M6+)lFxaBb=0ONn z)S8s7Sl=YXi2Epn!o-(eC2fMX##RCwhL!=(Y*<@R;JA8HQmcQ;zMp8!@(!@lsIzo- z$ry2f$D4e#O$TxV^T$kGb!!1)Ux~(ss5>-}@NR2o*~>${!r*eXafXpjxAPRSarDAk zH8VCdoro{AGd_X4qakpQq1S-gNyz}N+1#nQO&izS%CIbd#|j~Rk>7aVuuM{iLSnt0 z1-I3mQ`nEIubzIGMHg&&bdIHO8O~O={m@CUi`@ zk+N+<(BllRWy=DR(Y$mpnr&M4nYOLfEtywC_f(;oP z4;s;9l1li}%{&Hh%0#lL-QUltSM;AEQF&nQSKJ1Tn-M zZT`GxIC>xYYa#iZK3VG+6&aMPd5faOpe3RLP|`scBAv8}E?P-{mw8u_VvL*+1#i0v z5aa1}A-(c+s>6r3D9aBx4M?=3nCqe&uF!bf_A6-5&T@7DHQCSgv*=TsX~WeF(xRMi z36^rCYO6x3=~5VPy1)eHEgq9j5#-u)7u}P37sFdZ)(V{4od}(PG zvC4bJxkDpS5Q~DXDNlvPuv*yXRHIg>U7XGsE$DRB#+0^FBrXjnhiD1A=ZdE_v?GbJU?hNWDvc(JbildU zx4GBp0^l?6{3~(V-*~PQ-|7QX-hbSQQ0?}X2a3+DYp=b#B=^r58DMm$KRk&?*e?9p zlmjU*OX^#7u+K-?+ZUE#Xo%p@@NKwH?41z#TozC!2oqDmPe9_~OV|!$gyaqiI=vRC zbrCd#5xTW6BUujik$E+e|^V4t(M4O+A1hdWCzpewKP_sRbDGK_t_p@Q#;c3F>xJ zR@jy>Zo6u56G7%a{4P}MlKq^Vaymy(sBqj;K#0l5+7+g1U{Uqcon~%5Sb=EY1<3Nc zDnCS-K4yxP)~wn4X&qNdzy4Rcj|YdEO*vhCUb9>!pW#QJ)`WRi8%_}KcDQ^t>#L;R{ZkohU6OE7-s5IoeR3&$ z&zjagTkKCL>4TnX`F)6T^FYu@5az}O-Cz+g>a(gD=9|@&f;LDeB!bG3mJ1CPB<>jS zKmE{huSEtoB5^{780UQXy70kAZ>A?#s-gK`9lTcB>y``zsz!l(p-2}9sW|aJK!Soa zasW*7=~8dO>_5fwIIaHI=l;*gp4Vn2D~3%#J9TGlTS5wigQ&bV}P@G z;%&RcNpdy4eE}k|DCHUr^bn?pkHfjVT$4H0)oR?nGGo>&o1r+$OTHPzSwYlKRyesV&(P(kCJs@#xTS+5{DG7ugp zjP#j>_hRSANW*F+-)0v+RG( z>MoKcNqt8Ms7>>yz(4F$kGu%^OZ}ZpuB~EMKbU~cBh_XJ%$K{rpxUe~G!x3-$iS*D z1$j40;B-Z6+{U%FSOh^$#yqjXqL~jGEfDQ`y+uT2tHF>xjaN~WEiIaxsjSrm4h~>N z3$g1C|1)v1<8i#xTq{MWCB{EMw!~>#2UTcBr*!)%S#x7&eo2*NR5bDQ5@!G0U1Vrv zcOe>~XP7o{oSSLYC_f%w8~?1n0UI&@3@M!#?Zw+2`S{Uz*>15{dxT?$!Z-zCQ}BWXhqQuh9p#jZ zX0^|%yk9vnVvc9ymHBv*qCLx?gG);VP28~93zeYt$Rgiho+z?3M|_;BRk#gk@H!Ln9oSR zu=)|#Xy;Fxa)F{R+g6KvW@j=+0wWK&)5o4GiB4!hT6jKY`5(ZdE_=)VFAKk4^ME5y zWPflk<+npl1P@drky87{0{qPlDR4-A6g#v%!EMl0c4&3TAY(kTA|)B;T=fxngd;9_ zi+22dhiBR(_^|nX7Wlu_hKjg8gteI@Oed+l^$QR?kmVc7ojT%l`;fopO7H<1DXmKq z^jUM@Ar%J2EKPg1ldKT^DM`~H(pNFQq z)SV-i0MxB67gnDN)pvJoy!^Xq#itqk3_I~08es3;+WVto7T&SR&LR|Rd^dFXiJ83v zTgm4}E4Ah)HbuOAuagEOBpv7ru(sH1m8MUertY=;=EFVj{g>Ds)+5M@nk|!I!->0h zk?0go!QF>Bwub6oTVbm!&kI1Tgj}s`5i8xmXHNFMfL!r#$E$Jry+yK;YK!WtUHJ~0 z`uCLsIsCUfk>(K}r7c8~=!3X=1D`zChlpT&x_-{|Z6ze@~})^B(g+!0Dio`@nf*;KY+U zQYZgB_tjB(Kv~5Kx(C;OH(@AaXQ|Gu^ts#>BQhx$-euJGp+)fVI3tK9K!?LUnmp6d zn=(;hx~jq-^1Z1&5-3tym`oo@9H!GYz}7WHFLco>>Se3nc+&EId zrp&dLg@Cn!V_LIDgX3|WUpjGQMo(h#w>~=atGx!1J~n?H*o^rT z3`JFyxgjQV=FGqGeu{+yqR+9dJyUJN6=FerS2`!eB6+hNBXUE}oT7LTyhqWCskwsF z-4x0gw}LyI>lBmzu4FHIuwgG6B)Wfikd%oUfbm7m_B};*F#*@I*d{%7s6KE%7tN{H z%f7Y6pUCGv-9a;#UEn{`C;GPd;@;Uh?bjZt8m+OtE*$i7U=Iz?c)8rFn<+mQvqRnE z#+Au+_w%8>WyOeZrvPY{p=)Bp&~)+nJQD=Z@Xp+6K5kqsU-ooSXz_7Ck{B{9G-8*m z5UXJT1qWJbycE11Gh^P5aQ}Iy0BK+g}FdCmqu-sKeq4~tUWwy|>= za;JjPhDb!H$~Xy@Mt$<+Xpq;WA#V8Pt(!E=$%TE`(&9mCyPn>n<(G_UX*b;tYLJY) zecHx2r%bcgQRNCnis|2MIU@QAcj<~g>E^+a02~bRHwubKuiU_6)I!1}dqD!i0Mkq7 zyF!ilni|TM-~>-Xra5JJVw~#SNe2;QNqSn8iav4HiEoIdY1v?4OaK_;G$HzIDmLgp zM@ujKUqnl5em!-Mp$vl4vY*Z_ZudVGI%VPowYH5ToF0V`$LjQO8$zN)Z5Ge42aVvK zdGDCQe}JWJtw!$SP@U2CY1z>ifL?w_o>?@rjBLi_^La7xgPCU^$Hp2ddgg?>Z*}q! zlJ;uSD1vb9YHto?5VMgD|GmLKfP;^M%P-|))_7$hvQ)X|n$H89PJz+tS7P{^=W9w3 zXuB+k-6~S|>sj0R2%Ve73rT9~$F_QOCO%LV@UnAVLQ#6M7AYs51MR_fXJVWcW%$e#+hMzS@J=OIS`_h$uTXs;# z`V5i2Zm;n)XQq(+?pu+`f4L*q6MZr6rVT}+kMiLwG@b@QqfJ$gU&w&4;e%A%01>O@F^7f@E}l}h`jY#t?oxFyY@@5{8kPP zKwaJb;-x_#>bL2Ek40XqR*#0mX1D3kS^FM89DhyNqZCGT1sfYX8$(_CjMuC5vwRNC zJW|2X8f~vG4D6;o5<=b!!yGCd#0Y&X;z%1`!n94qf+i1pSF)azENq7SW-EOf22r5U z1A0{@JMq`N2e3DMulQh)jLeKm=!Y(FyD|k}Ep*PR-hnUpwNWqRJ5;-`H2(b!% z!d&FZe*5-uFjxe@H1jA{Y(2}HjOm77!$KpFD9ZeL0-w<|LX1B!HaL=Q@5%og>2Rd{1ZYn7xuVL!nN%a(kBQm@tv+H*4FQZ{{=ey}) z#@`}}WLu=VQFl=TGFXE29=s??ZdPu-F zW~J%@S{J%!C}&DZ4#j%=iHj>bqe3e`x@5nE@1jX8WAEAHkZ>`P5Ee6qx)#?4jlVp4 zE1?qzDp7vzJjiC4(2Y!vW|JFcYA&^Z6e%)d2e)zeUo$M(&o?6DMuA6;IQlLeRGlM{eX9wRTYp|M%-$b9f4)cTJo)X2q4p&LiEp$T`JqsUw`|aH z=YIfO%vQ2&#u)d~qmi-VS}|K=T!RVp(xOrN6zrlEFT7DY{27`U`p;wD@#Gvza)`v? za$%3~Bi`2k#o8WgZBO4W+oR`9J%-?;J4LTs<(Bfcv)Nob%kU0tZf;5^@0zyy4%#(Y(;-?};OJ&aL4XlzBCx>SeYc*B1A^ zZH@0z@DxPjOvu?kYA}B+a;7s#*@k)|Bh=~qm203gmxn%>%x&fRo_$V?n+Odolti%q z`(TY}yM{nwcz+M%D^fhTtKdZ}CVji4j}aZczV7{op(7xgEJo{G>a_hTwv?;3ttpn2 zE_nql5j|#@o7~YkKNK@KJ0GAsX9Z(_R4kSOmWe>l1K`%7qP6xIf9c)f25-G7x}7y0 zmE>xDHn88{vE_qVOY-YfpwsX*W&4Enx36?oq(9SJRrAr^8Y}pLuHr6X?JktpQ7TO_ zR8}ikksGq)r_wk|-swR9oQ+&D$dSwS{Yg31&tsaF6g6BIKXyp6nl4&HEOi~P133c4 zoh4FLYItn9RqkO* z?ct5KO5vD0)Wtv&H&sVaPPCJQ8j}Y@MDwa z2a7gFcLy=mglk+j0H$+r&abem)-AFaW#v#lOtN-)W)q1EuMc+fXJzpUV-(*Cow8|% zyN|1!0ySECvLFfwnJ(|~GM+_Mz-}10)pb1_QrL=7(1h-vFeg=ha?Ku5RxIHf!=8^DoFZJct$8mFTqc49$qt z9*i9+aP1G%pNg@ps52lNsj?n|* zD(Ay)v(JZu^c&69CA`%->Z3A3$CqxJ!!~PYPZj=)NG|dvVdWqGT@ynFREbFDs@aI) z)6U08J%K0B?tg&1`Bn<5XECbh7OHL5*#GK8cH`;zAEaks;B+N6<7INQ_i4A?#hPJM zd10T@P~9hX>h5(b3{f9#D(vSJrhqFSKT4oTIWu1}FvCYb1kSGK``Aa7%nvxR&k&%L z26oJ-%QUpjG1dYL7`1%zc@vS+It7AN-`WWmWN`Y=%KdYjI$KO3qG>J}%a~tb7$k6M zxk&)Zr0u#|Z0r;9`oc!>rn^voBa-C$ESzZ^mW5*I)1|kY7H~{r|h23Wy#uWCuDlR-#@B8 zzIv6e;O>kEZ5bw${^Pw~4v;~kl#%$*2#KA;pEtsoX4J2i# zd_anK7uJ!Q3zbn5^K-=h%z^g%Zwh8+r3OTu^{ME08=pg3!P;zC<|N%rs5_TL&7N0J z{4N_Z5>r){S4RwP#SElvz|{wl6x5gPDtB7@I; z0TJ-0kZVN{d8di%9CagLjQ-B?CI&V(+4;uHI45zqT1HWC`Um`}MwJ-FyWf=@|bk4?pGy>ntKE47B`@C<9I-U?Iu|u3z4t4vjA`1Uotx?tXE) zfiQJW#~;sE_V<)zz^l4$B%RaqUqMZ7e!l}8MWV084&!PS8c(-dEE9^5y+ZD_rlzLp z=#SlOWP}lcl%EMne@ZrF6odw6pBYg{`meoRE;2q&MWh$^@zSxN?3w9BbESall*6Nd7k}wy2DWow8Ckvi{OVV< zOEp62DdjITOo0=?nli1HhOC`mDG8!Ms~;8Q=s8KKvA_Z-2`Ahv7C_#fgFhRtop1GJ zPXG4w%o+p@3=Lvep5$XnZ%$PR!4=TIns#gNk=qY&OEKL1tfo0VP8wTf2wHvTBwRV1 z4u@~v6Ckr*CM4g1k&+PfA(~%~K0n>cNn9IXX*>KOR^IwU{W8uPA1nrNoY6&KjowKO zaq;$8zpWf2MloBq4ZM2FZP4$)07I7zX`Ebd`M&&(0eRpS2x9O-854Po!-4;_SDVjUD} z$9mBPr<3WU+So3Q+vs(q|DXdBDOBmMEH^+T1V{Dnrfa+!d)_cR6TB4BsWsSZ*EoHe zZ}!89P06NiNw|ukIZ4ZJ3>2R@FzJr=vMPz+bKl7ROu^cb7iHscSbg{W(pYPfdz#M+ z(ivLLkyYhyZKT%?!a5tLr+W|((Y*0;!p}h8N+UdLq<@QJzYm8txc!C)ZjxapH_Z_( zIoNT~wzA?$=n&!2I$+TIW@0yEPx!rv1g)$fbwilNtB$KIGgrkkyidZ4Mib|&z&~55 zYx_NtA32k7@TOmpbdyORx&MvZ!gjvt`Pf}-qdo8K3)S<7|Cppo0y#K(2#gXik{ULv z>1xgb;xfQ8C3E`Y((vwegu0+|70>H}bnYT`!;XhT=*Vy@Ep5c9=N;Od7%Jef@{GR8syXlz`LYzN!9{90lSN|WM?I?-1fWgu)1V8!41YGL7$*Rs$1c#WSuP0d9 zbZi^-#J0_pvu8HkaG??mo*AAO0^dQ-0)S6ZsDj7oGl}|Pn`>(NAA%JvqbYuY39l35 zB%~Db3>28cA;a_@U^#X=D-Tlz{CxV%g`A^HZ6DSj#@n$e%4xbC{{S)n0Au-P`NKF# z6};)L)z?$9knDA@x()uU^B14lT&C8sT>tR$d8QkRvzineFSFukP5k+)j!I(5O+%NR z8Hc32Z&3> zYcpfN0Zcdzf@W=rHS3(Lc3@E=pk zpn`-17Yi4kDz;iZBmI{gb(5k8XTk)m4-g!LPFAsq#ya^`cX6(DN{ua%x{>}6SXUo{ z%?tkDrWyW#HDYSSTL(tV1c@i<+eIWyqy+;l*OWZKrGZpJ;z8Ui5N1 zZ}Bp}P5BkqIP}D;mla5uJ>~LvzC!tR#D*79Q?4CwH@bOfd)g!G>?^;$=TAvKlR6}M9tvyfeteWl&wf=R7W^^AQN)VH|={W%fla(9cIpEh#1W`2siTUp2QTV(R~ zY_V5s$~LRMnY{JynTZNsPfU;tV{7R8Q)Iw^;dkBOe*g_(;{)mV@;9Ij3>-J!tcATK)hbL z_Mhi}2C0}?QGfR{)y~?w{;$yyze_HC7q{db5bEz)zww~5y;Ju5J=^w3-JiQGGVb=7 zPs`^Pq;_B7L)TRGif-cdr6aSc(W+yJPn^|x#eimbM=?RuR>BfX3Jv}>~+k7?U z%22ZB^UN@L8#wiyOViD3r+XOxaJfVS&r~cvAD6uh#ow|T+ly*jN`Cj{{r1|qIe$|x>N>)7`%20``Rmt~{ti9<=lk@3zfHGj>|A~4Sm_kmH6>rd4Zp4K z|M_13@3#!Ne0^B$iC?GQV3jnfjr`8PX5Ddr*JAlBV9`GhxOne=TL0FV`tz0b?>D<& zonJ7j_22K&U>Z#lXxVBsNsJ~5qLRdtwr3B{OBkPUOq{sq*QJWGX^$gX?ye~*WxcZT zFz2L5F%#Lya}1BKt+@B<+BNaAZ{LMFZaqCyD5lQZp7VU=8rulH#g9(Q+P!tTR-al~ zGyQ4#6NVdKkIQ#{H9c3t|68o{@9w{A|1Q{%}R zPF;VeiO*3wXe;pEJh2P=Ux;P{*CB=QCTA~?F%c_J5flm6Xl7QKIR8Rj=vMxoWBU*2 ziUh_U=R`f1I(u#&uaUl*clF7+x69w@-aH^{soZ~PQw_=uNAKSRr=>;D>mt^dckRaXS4fPc-tL-mIufnIR<8~&ex z;a2|-Z{7MA@~eQ0zodgMx?i1MFlxkTSd6BN!H`FeCGP!q`J+yGVAS2CLXlfi&NHi9 zUjYtF+l0*(3A@m)w6W#+xpyLgu91pEd7{N@la7vR&0FUkZ-b6AU*Pk<5ESUSdV$}$ zr`~t-z4!0lzGKIwt)5ah&rD?7oWo}O@s*ZFsmT71t!p1NJ-f&8HqNYihEH;#LZ83r zLf7KIk>yr(n|@2(&)xE$Vg8Ex_Yc;*-kCh@%a$VT6}@gD&v%D}ggW)>tS?HBpJfId LDHGk<`2QvV-Benz diff --git a/bsp/bl808/m0/drivers/Kconfig b/bsp/bl808/m0/drivers/Kconfig deleted file mode 100644 index ac17b47215..0000000000 --- a/bsp/bl808/m0/drivers/Kconfig +++ /dev/null @@ -1,63 +0,0 @@ -menu "BL808_M0 Hardware Drivers Config" -config SOC_BL808 - bool - select RT_USING_COMPONENTS_INIT - select RT_USING_USER_MAIN - select ARCH_RISCV_FPU_S - default y - - -config BSP_USING_JTAG_M0 - bool "Enable M0 JTAG " - default n - -menu "On-chip Peripheral Drivers" - - config BSP_USING_GPIO - bool "Enable GPIO" - select RT_USING_PIN - default y - - menuconfig BSP_USING_I2C1 - bool "Enable I2C1 BUS (software simulation)" - default n - select RT_USING_I2C - select RT_USING_I2C_BITOPS - select RT_USING_PIN - if BSP_USING_I2C1 - config BSP_I2C1_SCL_PIN - int "i2c1 scl pin number" - range 0 33 - default 20 - config BSP_I2C1_SDA_PIN - int "I2C1 sda pin number" - range 0 33 - default 21 - endif - - menuconfig BSP_USING_UART - bool "Enable UART" - default y - select RT_USING_SERIAL - if BSP_USING_UART - config BSP_USING_UART0 - bool "Enable UART0" - default y - - if BSP_USING_UART0 - config BSP_UART0_TXD_PIN - int "uart0 TXD pin number" - default 14 - - config BSP_UART0_RXD_PIN - int "uart0 RXD pin number" - default 15 - - endif - - endif - -endmenu - -endmenu - diff --git a/bsp/bl808/m0/drivers/SConscript b/bsp/bl808/m0/drivers/SConscript deleted file mode 100644 index 3cd7a608dd..0000000000 --- a/bsp/bl808/m0/drivers/SConscript +++ /dev/null @@ -1,53 +0,0 @@ -# RT-Thread building script for component - -from building import * - -cwd = GetCurrentDir() -src = Split(''' - board.c -''') - -CPPPATH = [cwd] - -if GetDepend(['RT_USING_SERIAL']): - if GetDepend(['RT_USING_SERIAL_V2']): - src += ['drv_uart_v2.c'] - else: - src += ['drv_uart.c'] - -if GetDepend('RT_USING_PIN'): - src += ['drv_gpio.c'] - -if GetDepend('RT_USING_I2C'): - src += ['drv_i2c.c'] - -# if GetDepend('BSP_USING_LCD'): -# src += ['drv_lcd.c'] -# src += ['drv_mpylcd.c'] - -# if GetDepend('RT_USING_HWTIMER'): -# src += ['drv_hw_timer.c'] - -# if GetDepend('RT_USING_CPUTIME'): -# src += ['drv_cputime.c'] - -# if GetDepend('RT_USING_SPI'): -# src += ['drv_spi.c'] - -# if GetDepend('RT_USING_PWM'): -# src += ['drv_pwm.c'] - -# if GetDepend('RT_USING_WDT'): -# src += ['drv_wdt.c'] - -group = DefineGroup('Drivers', src, depend = [''], CPPPATH = CPPPATH) - -objs = [group] - -list = os.listdir(cwd) - -for item in list: - if os.path.isfile(os.path.join(cwd, item, 'SConscript')): - objs = objs + SConscript(os.path.join(item, 'SConscript')) - -Return('objs') diff --git a/bsp/bl808/m0/drivers/board.c b/bsp/bl808/m0/drivers/board.c deleted file mode 100644 index a5c823ac8d..0000000000 --- a/bsp/bl808/m0/drivers/board.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022/12/25 flyingcys first version - * 2023/01/17 chushicheng add pin and i2c - */ -#include -#include - -#include "board.h" -#include "drv_uart.h" - -static void sipeed_bl_sys_enabe_jtag(int cpuid) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.pullType = GPIO_PULL_NONE; - - gpio_cfg.gpioMode = GPIO_MODE_AF; - switch (cpuid) { - case 0: { - gpio_cfg.gpioFun = GPIO_FUN_JTAG_M0; - } break; - case 1: { - gpio_cfg.gpioFun = GPIO_FUN_JTAG_D0; - } break; - default: { - } break; - } - gpio_cfg.gpioPin = GLB_GPIO_PIN_0; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_1; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_2; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_3; - GLB_GPIO_Init(&gpio_cfg); -} - -static void cmd_jtag_m0(void) -{ - sipeed_bl_sys_enabe_jtag(0); -} - -static void cmd_jtag_cpu0(void) -{ - sipeed_bl_sys_enabe_jtag(1); -} - -/* This is the timer interrupt service routine. */ -static void mtime_handler(void) -{ - rt_tick_increase(); - - csi_coret_config(CPU_Get_MTimer_Clock() / RT_TICK_PER_SECOND, MTIME_IRQn); -} - -void rt_hw_board_init(void) -{ - bl_sys_lowlevel_init(); - - csi_coret_config(CPU_Get_MTimer_Clock() / RT_TICK_PER_SECOND, MTIME_IRQn); - bl_irq_register(MTIME_IRQn, mtime_handler); - bl_irq_enable(MTIME_IRQn); - -#ifdef RT_USING_HEAP - /* initialize memory system */ - rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END); -#endif - - /* GPIO driver initialization is open by default */ -#ifdef RT_USING_PIN - rt_hw_pin_init(); -#endif - - /* I2C driver initialization is open by default */ -#ifdef RT_USING_I2C - rt_hw_i2c_init(); -#endif - - /* UART driver initialization is open by default */ -#ifdef RT_USING_SERIAL - rt_hw_uart_init(); -#endif - - /* Set the shell console output device */ -#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE) - rt_console_set_device(RT_CONSOLE_DEVICE_NAME); -#endif - -#ifdef RT_USING_COMPONENTS_INIT - rt_components_board_init(); -#endif - -#ifdef BSP_USING_JTAG_M0 - cmd_jtag_m0(); -#endif -} - -void rt_hw_cpu_reset(void) -{ - bl_sys_reset_por(); - while(1); -} - -MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine); diff --git a/bsp/bl808/m0/drivers/board.h b/bsp/bl808/m0/drivers/board.h deleted file mode 100644 index ead8fbdf84..0000000000 --- a/bsp/bl808/m0/drivers/board.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2022/12/25 flyingcys first version - */ - -#ifndef BOARD_H__ -#define BOARD_H__ - -#include - -#include "core_rv32.h" -#include "bl_sys.h" -#include "bl_irq.h" -#include "bl808_clock.h" - -#ifdef BL808 -#include "bl808.h" -#elif defined(BL606P) -#include "bl606p.h" -#endif - -extern uint8_t _heap_start; -extern uint8_t _heap_size; - -#define RT_HW_HEAP_BEGIN (void*)&_heap_start -#define RT_HW_HEAP_END (void*)(&_heap_start + (rt_ubase_t)&_heap_size) - -void rt_hw_board_init(void); - -#endif diff --git a/bsp/bl808/m0/drivers/drv_gpio.c b/bsp/bl808/m0/drivers/drv_gpio.c deleted file mode 100644 index ab43565f81..0000000000 --- a/bsp/bl808/m0/drivers/drv_gpio.c +++ /dev/null @@ -1,208 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/5 chushicheng first version - * - */ - -#include "drv_gpio.h" -#include -#include "bl808_gpio.h" -#include "bl808_glb.h" -#include "bl808.h" - -#ifdef RT_USING_PIN - -#define DBG_TAG "drv.gpio" -#define DBG_LVL DBG_INFO -#include - -static void GPIO0_IRQHandler(void); - -struct gpio_int_cfg_private -{ - slist_t list; - uint32_t pin; - void (*hdr)(uint32_t pin); -}; - -static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head); - - -static void bl808_pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value) -{ - GLB_GPIO_Write(pin, value); -} - -static int bl808_pin_read(rt_device_t dev, rt_base_t pin) -{ - int value; - value = GLB_GPIO_Read(pin);; - return value; -} - -static void bl808_pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.gpioFun = GPIO_FUN_GPIO; - gpio_cfg.gpioPin = pin; - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.outputMode = 0; - - switch (mode) - { - case GPIO_OUTPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_OUTPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_OUTPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - - case GPIO_INPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_INPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_INPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - case GPIO_HZ_MODE: - GLB_GPIO_Set_HZ(pin); - default: - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - GLB_GPIO_IntMask(pin, MASK); - - GLB_GPIO_INT_Cfg_Type intCfg; - - intCfg.gpioPin = pin; - intCfg.intMask = MASK; - - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - - if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE; - } - else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE; - } - else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL; - } - else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL; - } - else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE; - } - else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE; - } - else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_NONE; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE; - } - else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL; - } - else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) - { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL; - } - - GLB_GPIO_Int_Init(&intCfg); - break; - } - - GLB_GPIO_Init(&gpio_cfg); -} - - -static rt_err_t bl808_pin_attach_irq(struct rt_device *device, rt_int32_t pin, - rt_uint32_t irq_mode, void (*hdr)(void *args), void *args) -{ - struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private)); - int_cfg->hdr = hdr; - int_cfg->pin = pin; - slist_add_tail(&gpio_int_head, &int_cfg->list); - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO0_IRQHandler); - CPU_Interrupt_Enable(GPIO_INT0_IRQn); - return RT_EOK; -} - - -static rt_err_t bl808_pin_irq_enable(struct rt_device *device, rt_base_t pin, - rt_uint32_t enabled) -{ - if (enabled) - { - GLB_GPIO_IntMask(pin, UNMASK); - } - else - { - GLB_GPIO_IntMask(pin, MASK); - } - return RT_EOK; -} - -const static struct rt_pin_ops _bl808_pin_ops = -{ - bl808_pin_mode, - bl808_pin_write, - bl808_pin_read, - bl808_pin_attach_irq, - bl808_pin_irq_enable, - NULL, -}; - -int rt_hw_pin_init(void) -{ - return rt_device_pin_register("pin", &_bl808_pin_ops, RT_NULL); -} -INIT_BOARD_EXPORT(rt_hw_pin_init); - -/* irq handle */ -void GPIO0_IRQHandler(void) -{ - rt_interrupt_enter(); - // GPIO_INT0_IRQHandler(); - rt_interrupt_leave(); -} - -#endif /* RT_USING_PIN */ diff --git a/bsp/bl808/m0/drivers/drv_gpio.h b/bsp/bl808/m0/drivers/drv_gpio.h deleted file mode 100644 index ff60c9ec79..0000000000 --- a/bsp/bl808/m0/drivers/drv_gpio.h +++ /dev/null @@ -1,39 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/5 chushicheng first version - * - */ - -#ifndef __DRV_GPIO_H__ -#define __DRV_GPIO_H__ - -#include -#include -#include "drv_device.h" - -#define GPIO_OUTPUT_MODE 0 -#define GPIO_OUTPUT_PP_MODE 1 -#define GPIO_OUTPUT_PD_MODE 2 -#define GPIO_INPUT_MODE 3 -#define GPIO_INPUT_PP_MODE 4 -#define GPIO_INPUT_PD_MODE 5 -#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 -#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 -#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8 -#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9 -#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10 -#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11 -#define GPIO_SYNC_RISING_FALLING_TRIGER_INT_MODE 12 -#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 13 -#define GPIO_SYNC_LOW_LEVEL_INT_MODE 14 -#define GPIO_HZ_MODE 15 - - -int rt_hw_pin_init(void); - -#endif /* __DRV_GPIO_H__ */ diff --git a/bsp/bl808/m0/drivers/drv_i2c.c b/bsp/bl808/m0/drivers/drv_i2c.c deleted file mode 100644 index b69c6e623f..0000000000 --- a/bsp/bl808/m0/drivers/drv_i2c.c +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/17 chushicheng first version - */ - -#include -#include "drv_i2c.h" -#include "bl808_common.h" - -#ifdef RT_USING_I2C - -#define DBG_TAG "drv.i2c" -#define DBG_LVL DBG_INFO -#include - -#if !defined(BSP_USING_I2C1) -#error "Please define at least one BSP_USING_I2Cx" -/* this driver can be disabled at menuconfig -> RT-Thread Components -> Device Drivers */ -#endif - -static const struct bl808_soft_i2c_config soft_i2c_config[] = -{ -#ifdef BSP_USING_I2C1 - I2C1_BUS_CONFIG, -#endif -}; - -static struct bl808_i2c i2c_obj[sizeof(soft_i2c_config) / sizeof(soft_i2c_config[0])]; - -/** - * This function initializes the i2c pin. - * - * @param bl808 i2c dirver class. - */ -static void bl808_i2c_gpio_init(struct bl808_i2c *i2c) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)i2c->ops.data; - - rt_pin_mode(cfg->scl, PIN_MODE_OUTPUT_OD); - rt_pin_mode(cfg->sda, PIN_MODE_OUTPUT_OD); - - rt_pin_write(cfg->scl, PIN_HIGH); - rt_pin_write(cfg->sda, PIN_HIGH); -} - -/** - * This function sets the sda pin. - * - * @param bl808 config class. - * @param The sda pin state. - */ -static void bl808_set_sda(void *data, rt_int32_t state) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - if (state) - { - rt_pin_write(cfg->sda, PIN_HIGH); - } - else - { - rt_pin_write(cfg->sda, PIN_LOW); - } -} - -/** - * This function sets the scl pin. - * - * @param bl808 config class. - * @param The scl pin state. - */ -static void bl808_set_scl(void *data, rt_int32_t state) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - if (state) - { - rt_pin_write(cfg->scl, PIN_HIGH); - } - else - { - rt_pin_write(cfg->scl, PIN_LOW); - } -} - -/** - * This function gets the sda pin state. - * - * @param The sda pin state. - */ -static rt_int32_t bl808_get_sda(void *data) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - return rt_pin_read(cfg->sda); -} - -/** - * This function gets the scl pin state. - * - * @param The scl pin state. - */ -static rt_int32_t bl808_get_scl(void *data) -{ - struct bl808_soft_i2c_config* cfg = (struct bl808_soft_i2c_config*)data; - return rt_pin_read(cfg->scl); -} -/** - * The time delay function. - * - * @param microseconds. - */ -static void bl808_udelay(rt_uint32_t us) -{ - arch_delay_us(us); -} - -static const struct rt_i2c_bit_ops bl808_bit_ops_default = -{ - .data = RT_NULL, - .set_sda = bl808_set_sda, - .set_scl = bl808_set_scl, - .get_sda = bl808_get_sda, - .get_scl = bl808_get_scl, - .udelay = bl808_udelay, - .delay_us = 1, - .timeout = 100 -}; - -/** - * if i2c is locked, this function will unlock it - * - * @param bl808 config class - * - * @return RT_EOK indicates successful unlock. - */ -static rt_err_t bl808_i2c_bus_unlock(const struct bl808_soft_i2c_config *cfg) -{ - rt_int32_t i = 0; - - if (PIN_LOW == rt_pin_read(cfg->sda)) - { - while (i++ < 9) - { - rt_pin_write(cfg->scl, PIN_HIGH); - bl808_udelay(100); - rt_pin_write(cfg->scl, PIN_LOW); - bl808_udelay(100); - } - } - if (PIN_LOW == rt_pin_read(cfg->sda)) - { - return -RT_ERROR; - } - - return RT_EOK; -} - -/* I2C initialization function */ -int rt_hw_i2c_init(void) -{ - rt_err_t result; - - for (rt_size_t i = 0; i < sizeof(i2c_obj) / sizeof(struct bl808_i2c); i++) - { - i2c_obj[i].ops = bl808_bit_ops_default; - i2c_obj[i].ops.data = (void*)&soft_i2c_config[i]; - i2c_obj[i].i2c2_bus.priv = &i2c_obj[i].ops; - bl808_i2c_gpio_init(&i2c_obj[i]); - result = rt_i2c_bit_add_bus(&i2c_obj[i].i2c2_bus, soft_i2c_config[i].bus_name); - RT_ASSERT(result == RT_EOK); - bl808_i2c_bus_unlock(&soft_i2c_config[i]); - - LOG_D("software simulation %s init done, pin scl: %d, pin sda %d", - soft_i2c_config[i].bus_name, - soft_i2c_config[i].scl, - soft_i2c_config[i].sda); - } - - return RT_EOK; -} -INIT_BOARD_EXPORT(rt_hw_i2c_init); - -#endif /* RT_USING_I2C */ diff --git a/bsp/bl808/m0/drivers/drv_i2c.h b/bsp/bl808/m0/drivers/drv_i2c.h deleted file mode 100644 index 4add722a00..0000000000 --- a/bsp/bl808/m0/drivers/drv_i2c.h +++ /dev/null @@ -1,43 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes - * 2023/01/17 chushicheng first version - */ - -#ifndef __DRV_I2C__ -#define __DRV_I2C__ - -#include -#include -#include - -/* bl808 config class */ -struct bl808_soft_i2c_config -{ - rt_uint8_t scl; - rt_uint8_t sda; - const char *bus_name; -}; -/* bl808 i2c dirver class */ -struct bl808_i2c -{ - struct rt_i2c_bit_ops ops; - struct rt_i2c_bus_device i2c2_bus; -}; - -#ifdef BSP_USING_I2C1 -#define I2C1_BUS_CONFIG \ - { \ - .scl = BSP_I2C1_SCL_PIN, \ - .sda = BSP_I2C1_SDA_PIN, \ - .bus_name = "i2c1", \ - } -#endif - -int rt_hw_i2c_init(void); - -#endif diff --git a/bsp/bl808/m0/drivers/drv_uart.c b/bsp/bl808/m0/drivers/drv_uart.c deleted file mode 100644 index 5f880cae9f..0000000000 --- a/bsp/bl808/m0/drivers/drv_uart.c +++ /dev/null @@ -1,318 +0,0 @@ -/* - * Copyright (c) 2006-2023, RT-Thread Development Team - * - * SPDX-License-Identifier: Apache-2.0 - * - * Change Logs: - * Date Author Notes -* 2022/12/25 flyingcys first version -*/ - -#include -#include -#include - -#include "board.h" -#include "drv_uart.h" - - -struct device_uart -{ - struct rt_serial_device serial; - uint8_t port; - uint8_t tx_pin; - uint8_t rx_pin; -}; - -static void _uart_rx_irq(void *param) -{ - struct device_uart *uart = (struct device_uart *)param;; - - struct rt_serial_device *serial = &uart->serial; - - rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND); -} - -static int uart_signal_get(uint8_t pin) -{ - //TODO no magic number is allowed here - if (pin >= 12 && pin <=23) { - return (pin + 6) % 12; - } else if (pin >= 36 && pin <=45) { - return (pin + 6) % 12; - } - return (pin % 12); -} - -static int uart_func_get(uint8_t id, GLB_UART_SIG_FUN_Type uartfunc) -{ - switch (id) { - case 0: - return uartfunc; - case 1: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - case 2: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - default: - /*empty here*/ - //TODO should assert here? - return uartfunc; - } -} -static void uart_gpio_demo(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - uint8_t uart_func, uart_sig; - - //FIXME SWAP set is NOT put here - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 1); - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1); - - //common GPIO cfg - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.gpioMode = GPIO_MODE_AF; - gpio_cfg.pullType = GPIO_PULL_UP; - gpio_cfg.gpioFun = GPIO_FUN_UART; - - //cfg for UART Tx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + tx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_TXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - - //cfg for UART Rx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + rx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_RXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - - //Enable UART clock - GLB_Set_UART_CLK(1, 0, 0); -} - -static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *cfg) -{ - struct device_uart *uart; - uint8_t id; - - RT_ASSERT(serial != RT_NULL); - RT_ASSERT(cfg != RT_NULL); - - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - id = uart->port; - - UART_CFG_Type uart_cfg = { - 80*1000*1000, /*UART clock from XTAL*/ - 2000000, /* baudrate */ - UART_DATABITS_8, /* data bits */ - UART_STOPBITS_1, /* stop bits */ - UART_PARITY_NONE, /* parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - DISABLE, /* Disable tx output SW control mode */ - DISABLE, /* Disable tx lin mode */ - DISABLE, /* Disable rx lin mode */ - 0, /* Tx break bit count for lin mode */ - UART_LSB_FIRST, /* UART each data byte is send out LSB-first */ - }; - - UART_FifoCfg_Type fifoCfg = { - 16, /* TX FIFO threshold */ - 16, /* RX FIFO threshold */ - DISABLE, /* Disable tx dma req/ack interface */ - DISABLE /* Disable rx dma req/ack interface */ - }; - - /* init debug uart gpio first */ - uart_gpio_demo(id, uart->tx_pin, uart->rx_pin, 0xff, 0xff); - - /* disable all interrupt */ - UART_IntMask(id, UART_INT_ALL, MASK); - - /* disable uart before config */ - UART_Disable(id, UART_TXRX); - - uart_cfg.baudRate = cfg->baud_rate; - - switch (cfg->data_bits) - { - case DATA_BITS_5: - uart_cfg.dataBits = UART_DATABITS_5; - break; - - case DATA_BITS_6: - uart_cfg.dataBits = UART_DATABITS_6; - break; - - case DATA_BITS_7: - uart_cfg.dataBits = UART_DATABITS_7; - break; - - case DATA_BITS_8: - uart_cfg.dataBits = UART_DATABITS_8; - break; - - default: - uart_cfg.dataBits = UART_DATABITS_8; - break; - } - - switch (cfg->stop_bits) - { - case STOP_BITS_1: - uart_cfg.stopBits = UART_STOPBITS_1; - break; - - case STOP_BITS_2: - uart_cfg.stopBits = UART_STOPBITS_2; - break; - - default: - uart_cfg.stopBits = UART_STOPBITS_1; - break; - } - - switch (cfg->parity) - { - case PARITY_NONE: - uart_cfg.parity = UART_PARITY_NONE; - break; - - case PARITY_ODD: - uart_cfg.parity = UART_PARITY_ODD; - break; - - case PARITY_EVEN: - uart_cfg.parity = UART_PARITY_EVEN; - break; - - default: - uart_cfg.parity = UART_PARITY_NONE; - break; - } - - /* uart init with configuration */ - UART_Init(id, &uart_cfg); - - /* UART fifo configuration */ - UART_FifoConfig(id, &fifoCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* Set rx time-out value */ - UART_SetRxTimeoutValue(id, UART_DEFAULT_RTO_TIMEOUT); - - /* enable uart */ - UART_AutoBaudDetection(id, 0); - UART_Enable(id, UART_TXRX); - - return RT_EOK; -} - -static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg) -{ - struct device_uart *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - switch (cmd) - { - /* disable interrupt */ - case RT_DEVICE_CTRL_CLR_INT: - bl_uart_int_disable(uart->port); - bl_uart_int_rx_notify_unregister(uart->port, _uart_rx_irq, uart); - break; - - /* enable interrupt */ - case RT_DEVICE_CTRL_SET_INT: - bl_uart_int_rx_notify_register(uart->port, _uart_rx_irq, uart); - bl_uart_int_enable(uart->port); - break; - } - return RT_EOK; -} - -static int _uart_putc(struct rt_serial_device *serial, char c) -{ - struct device_uart *uart; - - RT_ASSERT(serial != RT_NULL); - - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - bl_uart_data_send(uart->port, c); - - return 1; -} - -static int _uart_getc(struct rt_serial_device *serial) -{ - int ch = -1; - struct device_uart *uart; - - RT_ASSERT(serial != RT_NULL); - uart = serial->parent.user_data; - RT_ASSERT(uart != RT_NULL); - - ch = bl_uart_data_recv(uart->port); - - return ch; -} - -static const struct rt_uart_ops _uart_ops = -{ - .configure = _uart_configure, - .control = _uart_control, - .putc = _uart_putc, - .getc = _uart_getc, - .dma_transmit = RT_NULL -}; - -/* - * UART Initiation - */ -int rt_hw_uart_init(void) -{ - rt_err_t result = 0; - - struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT; - struct rt_serial_device *serial; - struct device_uart *uart; - -#ifdef BSP_USING_UART0 - static struct device_uart uart0; - - serial = &uart0.serial; - uart = &uart0; - - serial->ops = &_uart_ops; - serial->config = config; - serial->config.baud_rate = 2000000; - - uart->port = 0; - uart->tx_pin = BSP_UART0_TXD_PIN; - uart->rx_pin = BSP_UART0_RXD_PIN; - - /* register USART device */ - result = rt_hw_serial_register(serial, - "uart0", - RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX, - uart); - RT_ASSERT(result == RT_EOK); -#endif - - return 0; -} diff --git a/bsp/bl808/m0/libraries/SConscript b/bsp/bl808/m0/libraries/SConscript deleted file mode 100644 index c8b2699f66..0000000000 --- a/bsp/bl808/m0/libraries/SConscript +++ /dev/null @@ -1,103 +0,0 @@ -import os -from building import * - -cwd = GetCurrentDir() - -# add general drivers -src = Split(''' - platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c - platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c - platform/soc/bl808/startup_bl808/evb/src/debug.c - platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c - platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S -''') - -path = [cwd, - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include', - cwd + r'/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config', - cwd + r'/platform/soc/bl808/bl808_e907_std/common/misc', - cwd + r'/platform/soc/bl808/bl808_e907_std/common/soft_crc'] - -src += Split(""" - stage/blog/blog.c - utils/src/utils_log.c - stage/blfdt/src/fdt.c - stage/blfdt/src/fdt_ro.c - stage/blfdt/src/fdt_wip.c - stage/blfdt/src/fdt_sw.c - stage/blfdt/src/fdt_rw.c - stage/blfdt/src/fdt_strerror.c - stage/blfdt/src/fdt_empty_tree.c - stage/blfdt/src/fdt_addresses.c - stage/blfdt/src/fdt_overlay.c -""") - -path += [cwd + r'/stage/blog', - cwd + r'/stage/blfdt/inc', - cwd + r'/utils/include' -] - - # platform/hosal/bl808_e907_hal/bl_pm.c - # platform/hosal/bl808_e907_hal/bl_sec.c - # platform/hosal/bl808_e907_hal/bl_timer.c - # platform/hosal/bl808_e907_hal/hal_board.c - # platform/hosal/bl808_e907_hal/hal_sdh.c - # platform/hosal/bl808_e907_hal/hosal_adc.c - # platform/hosal/bl808_e907_hal/hosal_dma.c - # platform/hosal/bl808_e907_hal/hosal_pwm.c - # platform/hosal/bl808_e907_hal/hosal_spi.c - # platform/hosal/bl808_e907_hal/hosal_uart.c - # platform/hosal/bl808_e907_hal/hal_sdh.c - - -src += Split(""" - platform/hosal/bl808_e907_hal/bl_uart.c - platform/hosal/bl808_e907_hal/bl_irq.c - platform/hosal/bl808_e907_hal/bl_chip.c - platform/hosal/bl808_e907_hal/bl_flash.c - platform/hosal/bl808_e907_hal/bl_wifi.c - platform/hosal/bl808_e907_hal/bl_efuse.c - platform/hosal/bl808_e907_hal/bl_sys.c - platform/hosal/bl808_e907_hal/bl_boot2.c - platform/hosal/bl808_e907_hal/bl_ipc.c - platform/hosal/bl808_e907_hal/bl_cam.c - platform/hosal/bl808_e907_hal/bl_audio.c - platform/hosal/bl808_e907_hal/bl_sdh.c - platform/hosal/bl808_e907_hal/hal_boot2.c - platform/hosal/bl808_e907_hal/hal_sys.c - platform/hosal/bl808_e907_hal/bl_psram.c - platform/hosal/bl808_e907_hal/bl_mm_clock.c - platform/hosal/bl808_e907_hal/hal_board.c - platform/soc/bl808/bl808_e907_std/common/misc/misc.c - platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c -""") - -src += Split(""" - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c - platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_ctrl.c -""") - -path += [cwd + r'/platform/hosal/bl808_e907_hal'] -path += [cwd + r'/platform/soc/bl808/bl808_e907_std/common/device', - cwd + r'/platform/soc/bl808/bl808_e907_std/common/list'] - -libpath = [] -libs = [] - -group = DefineGroup('Libraries', src, depend = [''], CPPPATH = path, LIBS = libs, LIBPATH = libpath) - - -Return('group') diff --git a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adapter.h b/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adapter.h deleted file mode 100644 index d4faed1793..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adapter.h +++ /dev/null @@ -1,38 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef _HOSAL_ADAPTER_H_ -#define _HOSAL_ADAPTER_H_ - -#include - -uintptr_t hosal_adpt_critical_enter(void); -void hosal_adpt_critical_exit(uintptr_t); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adpt_iotsdk.c b/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adpt_iotsdk.c deleted file mode 100644 index 37f2868c8c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/adapter/hosal_adpt_iotsdk.c +++ /dev/null @@ -1,45 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "hosal_adapter.h" -#include "FreeRTOS.h" -#include "task.h" - -uintptr_t hosal_adpt_critical_enter(void) -{ - taskENTER_CRITICAL(); - return 0; -} - -void hosal_adpt_critical_exit(uintptr_t irq_state) -{ - (void)irq_state; - taskEXIT_CRITICAL(); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.c deleted file mode 100644 index 65edf03c10..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.c +++ /dev/null @@ -1,545 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_audio.h" - -#include "bl808.h" -#include "bl808_audio.h" -#include "bl808_glb.h" -#include "bl808_hbn.h" -#include "bl808_dma.h" -#include "bl_irq.h" -// #include -// #include - -static bl_audio_dev_t *gp_audio_dac_dev = NULL; - -#define AUDIO_DMA_ID DMA0_ID -#define AUDIO_TX_DMA_CHANNLE DMA_CH0 -#define AUDIO_RX_DMA_CHANNLE DMA_CH1 - -static struct DMA_Control_Reg dmaCtrlRegVal={ - .TransferSize = 1000, - .SBSize = DMA_BURST_SIZE_8, - .DBSize = DMA_BURST_SIZE_8, - .SWidth = DMA_TRNS_WIDTH_16BITS, - .DWidth = DMA_TRNS_WIDTH_16BITS, - .SI = DMA_MINC_ENABLE, - .DI = DMA_MINC_DISABLE, - .dst_min_mode = DISABLE, - .dst_add_mode = DISABLE, - .fix_cnt = 0, - .I = 1, -}; - -static DMA_LLI_Cfg_Type lliCfg={ - DMA_TRNS_M2P, - DMA_REQ_NONE, - DMA_REQ_AUDIO_TX, -}; - -static int __hw_init(bl_audio_dev_t *p_dev) -{ - Audio_FifoCfg_Type audioFifoCfg; - - Audio_Clock_CFG_Type audioClockCfg = { - AUDIO_ADC_16_KHZ, - AUDIO_DAC_16_KHZ, - DISABLE, - DISABLE, - DISABLE, - }; - - Audio_Volume_Cfg_Type audioVolumeCfg = { - AUIDO_MUTE_DIRECTLY, - AUIDO_RAMP_RATE_2_FS, - AUIDO_RAMP_RATE_2_FS, - AUIDO_VOLUME_UPDATE_FORCE, - AUIDO_ZERO_CROSS_RATE_2_FS, - AUIDO_RAMP_RATE_2_FS, - AUIDO_ZERO_CROSS_RATE_2_FS, - }; - - GLB_Config_AUDIO_PLL(GLB_XTAL_40M, audioPllCfg_451P584M); - /* ungate audio */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_AUDIO); - - /* enable dac clock*/ - GLB_Set_Audio_DAC_CLK(ENABLE, 19); - /* enable adc clock*/ - GLB_Set_Audio_ADC_CLK(ENABLE, 19); - - Audio_Poweron(); - - switch (p_dev->samplerate) { - case AUDIO_8_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_8_KHZ; - printf("samplerate 8K\r\n"); - break; - case AUDIO_16_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_16_KHZ; - printf("samplerate 16K\r\n"); - break; - case AUDIO_24_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_24_KHZ; - printf("samplerate 24K\r\n"); - break; - case AUDIO_32_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_32_KHZ; - printf("samplerate 32K\r\n"); - break; - case AUDIO_48_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_48_KHZ; - printf("samplerate 48K\r\n"); - break; - case AUDIO_96_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_96_KHZ; - printf("samplerate 96K\r\n"); - break; - case AUDIO_192_KHZ: - audioClockCfg.dac_clock = AUDIO_DAC_192_KHZ; - printf("samplerate 192K\r\n"); - break; - default: - printf("samplerate NULL\r\n"); - break; - } - - Audio_Clock_Init(&audioClockCfg); - //set mute ramp - Audio_DAC_Software_Volume_Config(AUDIO_DAC_0, &audioVolumeCfg); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_DAC_Software_Volume_Config(AUDIO_DAC_1, &audioVolumeCfg); - } - - Audio_DAC_Set_Volume_Reg(ENABLE, 0, AUDIO_PLAY_DEFAULT_INITIAL_VOLUME); - - Audio_DAC_Enable(AUDIO_DAC_0); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_DAC_Enable(AUDIO_DAC_1); - } - - Audio_DAC_Set_Mute(ENABLE, 0, AUDIO_UNMUTE); - - switch (p_dev->playBitWidth) { - case AUDIO_BIT_WIDTH_16: - audioFifoCfg.resolution = AUDIO_RES_16_BITS; - audioFifoCfg.ailgnMode = AUDIO_FIFO_AILGN_MSB_AT_BIT15; - printf("BitWidth 16\r\n"); - break; - case AUDIO_BIT_WIDTH_24: - audioFifoCfg.resolution = AUDIO_RES_20_BITS; - audioFifoCfg.ailgnMode = AUDIO_FIFO_AILGN_MSB_AT_BIT23; - printf("BitWidth 24\r\n"); - break; - case AUDIO_BIT_WIDTH_32: - audioFifoCfg.resolution = AUDIO_RES_20_BITS; - audioFifoCfg.ailgnMode = AUDIO_FIFO_AILGN_MSB_AT_BIT31; - printf("BitWidth 32\r\n"); - break; - default: - printf("BitWidth NULL\r\n"); - break; - } - audioFifoCfg.FifoIntThreshold = AUDIO_DEFAULT_TX_DRQ_THR; - audioFifoCfg.dmaThresholdMode = AUDIO_DRQ_EQUEL_TO_IRQ; - audioFifoCfg.dmaEn = ENABLE; - - Audio_TxFifoConfig(&audioFifoCfg); - - Audio_TxFifoDisable(p_dev->tx_channel); - - if (p_dev->rx_enable) { - Audio_ADC_Software_Volume_Config(AUDIO_ADC_0, &audioVolumeCfg); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_ADC_Software_Volume_Config(AUDIO_ADC_1, &audioVolumeCfg); - } - - Audio_ADC_Set_Volume_Reg(ENABLE, 0, AUDIO_PLAY_DEFAULT_INITIAL_VOLUME); - - Audio_ADC_Enable(AUDIO_ADC_0); - if (p_dev->rx_channel == STEREO_CHANNEL) { - Audio_ADC_Enable(AUDIO_ADC_1); - } - - Audio_ADC_Set_Mute(ENABLE, 0, AUDIO_UNMUTE); - - audioFifoCfg.FifoIntThreshold = AUDIO_DEFAULT_RX_DRQ_THR; - Audio_RxFifoConfig(&audioFifoCfg); - Audio_RxFifoDisable(p_dev->rx_channel); - } - Auido_IntMask(AUDIO_INT_NUM_ALL, MASK); - - return 0; -} - -static void __audio_lli_init(bl_audio_dev_t *p_dev) -{ - p_dev->lli_tx_buffer_size = p_dev->lli_tx_buffer_size / 2; - - switch (p_dev->playBitWidth) { - case AUDIO_BIT_WIDTH_16: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.TransferSize = p_dev->lli_tx_buffer_size / 2; - break; - case AUDIO_BIT_WIDTH_24: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_tx_buffer_size / 4; - break; - case AUDIO_BIT_WIDTH_32: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_tx_buffer_size / 4; - break; - - default: - //private_bflb_platform_printf("BIT WIDTH Is Invaild\r\n"); - break; - } - - p_dev->lli_tx_list[0].srcDmaAddr = (uint32_t)p_dev->lli_tx_buffer; - p_dev->lli_tx_list[0].destDmaAddr = AUDIO_TX_FIFO_ADDR; - p_dev->lli_tx_list[0].nextLLI = (uint32_t)&p_dev->lli_tx_list[1]; - p_dev->lli_tx_list[0].dmaCtrl= dmaCtrlRegVal; - - p_dev->lli_tx_list[1].srcDmaAddr = (uint32_t)p_dev->lli_tx_buffer + p_dev->lli_tx_buffer_size; - p_dev->lli_tx_list[1].destDmaAddr = AUDIO_TX_FIFO_ADDR; - p_dev->lli_tx_list[1].nextLLI=(uint32_t)&p_dev->lli_tx_list[0]; - p_dev->lli_tx_list[1].dmaCtrl= dmaCtrlRegVal; - - DMA_LLI_Init(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, &lliCfg); - DMA_LLI_Update(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, (uint32_t)&gp_audio_dac_dev->lli_tx_list); - - if (p_dev->rx_enable) { - p_dev->lli_rx_buffer_size = p_dev->lli_rx_buffer_size / 2; - - switch (p_dev->playBitWidth) { - case AUDIO_BIT_WIDTH_16: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_16BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_8; - dmaCtrlRegVal.TransferSize = p_dev->lli_rx_buffer_size / 2; - break; - case AUDIO_BIT_WIDTH_24: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_rx_buffer_size / 4; - break; - case AUDIO_BIT_WIDTH_32: - dmaCtrlRegVal.SWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.DWidth = DMA_TRNS_WIDTH_32BITS; - dmaCtrlRegVal.SBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.DBSize = DMA_BURST_SIZE_4; - dmaCtrlRegVal.TransferSize = p_dev->lli_rx_buffer_size / 4; - break; - - default: - //private_bflb_platform_printf("BIT WIDTH Is Invaild\r\n"); - break; - } - - dmaCtrlRegVal.SI = DMA_MINC_DISABLE; - dmaCtrlRegVal.DI = DMA_MINC_ENABLE; - - p_dev->lli_rx_list[0].srcDmaAddr = AUDIO_RX_FIFO_ADDR; - p_dev->lli_rx_list[0].destDmaAddr = (uint32_t)p_dev->lli_rx_buffer; - p_dev->lli_rx_list[0].nextLLI = (uint32_t)&p_dev->lli_rx_list[1]; - p_dev->lli_rx_list[0].dmaCtrl= dmaCtrlRegVal; - - p_dev->lli_rx_list[1].srcDmaAddr = AUDIO_RX_FIFO_ADDR; - p_dev->lli_rx_list[1].destDmaAddr = (uint32_t)p_dev->lli_rx_buffer + p_dev->lli_rx_buffer_size; - p_dev->lli_rx_list[1].nextLLI=(uint32_t)&p_dev->lli_rx_list[0]; - p_dev->lli_rx_list[1].dmaCtrl= dmaCtrlRegVal; - - lliCfg.dir = DMA_TRNS_P2M; - lliCfg.srcPeriph = DMA_REQ_AUDIO_RX; - lliCfg.dstPeriph = DMA_REQ_NONE; - - DMA_LLI_Init(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, &lliCfg); - DMA_LLI_Update(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, (uint32_t)&gp_audio_dac_dev->lli_rx_list); - } -} - -static int __dma_int_clear(DMA_ID_Type dma_id, int ch) -{ - uint32_t tmpVal; - uint32_t intClr; - /* Get DMA register */ - - const uint32_t dmaAddr[] = { DMA0_BASE, DMA1_BASE, DMA2_BASE }; - uint32_t DMAChs = dmaAddr[dma_id]; - - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - } - - return 0; -} - -static void __dma_irq_handler(void) -{ - uint32_t tmpVal, count; - int ret, size; - tmpVal = BL_RD_REG(DMA0_BASE, DMA_INTTCSTATUS); - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << AUDIO_TX_DMA_CHANNLE)) != 0) { - __dma_int_clear(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); //clear int first - - if ( NULL == gp_audio_dac_dev) { - return; - } - size = gp_audio_dac_dev->lli_tx_buffer_size; - /*FIXME: set dma chain resonable option first 2 chain*/ - if (gp_audio_dac_dev->usr_cb) { - /* software count may reliable*/ - //if (++gp_audio_dac_dev->pingpang >= 2) { - // gp_audio_dac_dev->pingpang = 0; - //} - - count = ((*(volatile uint32_t *)0x2000c110) & (0x3FF << 20)) >> 20; - if (0x01 == (count & 0x01)) { - ret = gp_audio_dac_dev->usr_cb(gp_audio_dac_dev->p_usr_arg, - gp_audio_dac_dev->lli_tx_buffer, - size, - gp_audio_dac_dev->is_underrun); - } else { - ret = gp_audio_dac_dev->usr_cb(gp_audio_dac_dev->p_usr_arg, - gp_audio_dac_dev->lli_tx_buffer + size, - size, - gp_audio_dac_dev->is_underrun); - } - if (ret != 0) { - gp_audio_dac_dev->is_underrun = 1; - } else { - gp_audio_dac_dev->is_underrun = 0; - } - } - } - - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << AUDIO_RX_DMA_CHANNLE)) != 0) { - __dma_int_clear(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); //clear int first - if ( NULL == gp_audio_dac_dev) { - return; - } - size = gp_audio_dac_dev->lli_rx_buffer_size; - if (gp_audio_dac_dev->usr_rx_cb) { - count = ((*(volatile uint32_t *)0x2000c210) & (0x3FF << 20)) >> 20; - /*FIXME: set dma multi chains*/ - if (0x01 == (count & 0x01)) { - ret = gp_audio_dac_dev->usr_rx_cb(gp_audio_dac_dev->p_usr_rx_arg, - gp_audio_dac_dev->lli_rx_buffer, - size, - gp_audio_dac_dev->is_overflow); - } else { - ret = gp_audio_dac_dev->usr_rx_cb(gp_audio_dac_dev->p_usr_rx_arg, - gp_audio_dac_dev->lli_rx_buffer + size, - size, - gp_audio_dac_dev->is_overflow); - } - if (ret != 0) { - gp_audio_dac_dev->is_overflow = 1; - } else { - gp_audio_dac_dev->is_overflow = 0; - } - } - } -} - -int bl_audio_samplerate_set (bl_audio_dev_t *p_dev, Audio_Samplerate_Type samplerate) -{ - p_dev->samplerate = samplerate; - - return 0; -} - -int bl_audio_tx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_tx_ready_t cb, - void *p_arg) -{ - if (NULL == p_dev) { - printf("tx ready config fail dev is null\r\n"); - return -1; - } - p_dev->usr_cb = cb; - p_dev->p_usr_arg = p_arg; - return 0; -} - -int bl_audio_rx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_rx_ready_t cb, - void *p_arg) -{ - if (NULL == p_dev) { - printf("rx ready config fail dev is null\r\n"); - return -1; - } - p_dev->usr_rx_cb = cb; - p_dev->p_usr_rx_arg = p_arg; - return 0; -} - -int bl_audio_tx_buffer_config (bl_audio_dev_t *p_dev, void **ptr_mem, uint32_t bufsize) -{ - if (NULL == p_dev->lli_tx_buffer) { - p_dev->lli_tx_buffer = pvPortMalloc(bufsize); - } - - if (NULL == p_dev->lli_tx_buffer) { - printf("malloc tx buffer fail\r\n"); - return -1; - } - - memset(p_dev->lli_tx_buffer, 0, bufsize); - csi_dcache_clean_range((void *)(p_dev->lli_tx_buffer), bufsize); - *ptr_mem = p_dev->lli_tx_buffer; - p_dev->lli_tx_buffer_size = bufsize; - - return 0; -} - -int bl_audio_rx_buffer_config (bl_audio_dev_t *p_dev, - void **ptr_mem, - uint32_t bufsize) -{ - if (NULL == p_dev->lli_rx_buffer) { - p_dev->lli_rx_buffer = pvPortMalloc(bufsize); - } - - if (NULL == p_dev->lli_rx_buffer) { - printf("malloc rx buffer fail\r\n"); - return -1; - } - - memset(p_dev->lli_rx_buffer, 0, bufsize); - csi_dcache_clean_range((void *)(p_dev->lli_rx_buffer), bufsize); - *ptr_mem = p_dev->lli_rx_buffer; - p_dev->lli_rx_buffer_size = bufsize; - - return 0; -} - -int bl_audio_start (bl_audio_dev_t *p_dev) -{ - if (NULL == p_dev) { - printf("audio start fail dev is NULL\r\n"); - return -1; - } - - __hw_init(p_dev); - - GLB_Set_DMA_CLK(ENABLE, GLB_DMA0_CLK_CH0); - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0); - - DMA_Disable(AUDIO_DMA_ID); - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); - - DMA_IntMask(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, DMA_INT_ALL, MASK); - DMA_IntMask(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE, DMA_INT_TCOMPLETED, UNMASK); - DMA_IntMask(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, DMA_INT_ALL, MASK); - DMA_IntMask(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE, DMA_INT_TCOMPLETED, UNMASK); - bl_irq_register(DMA0_ALL_IRQn, __dma_irq_handler); - bl_irq_enable(DMA0_ALL_IRQn); - - __audio_lli_init(p_dev); - - csi_dcache_clean(); - DMA_Enable(AUDIO_DMA_ID); - DMA_Channel_Enable(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); - - Audio_TxFifoEnable(p_dev->tx_channel); - - if (p_dev->rx_enable) { - DMA_Channel_Enable(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); - Audio_RxFifoEnable(p_dev->rx_channel); - } - return 0; -} - -int bl_audio_stop (bl_audio_dev_t *p_dev) -{ - gp_audio_dac_dev->pingpang = 0; - - DMA_Disable(AUDIO_DMA_ID); - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_TX_DMA_CHANNLE); - if (p_dev->rx_enable) { - DMA_Channel_Disable(AUDIO_DMA_ID, AUDIO_RX_DMA_CHANNLE); - } - bl_irq_disable(DMA0_ALL_IRQn); - - return 0; -} - -int bl_audio_init (bl_audio_dev_t *p_dev) -{ - if (NULL == p_dev) { - printf("init audio fail dev is null\r\n"); - return -1; - } - memset(p_dev, 0, sizeof(bl_audio_dev_t)); - gp_audio_dac_dev = p_dev; - - return 0; -} - -int bl_audio_deinit (bl_audio_dev_t *p_dev) -{ - vPortFree(p_dev->lli_tx_buffer); - p_dev->lli_tx_buffer = NULL; - - vPortFree(p_dev->lli_rx_buffer); - p_dev->lli_tx_buffer = NULL; - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.h deleted file mode 100644 index 620edef1f9..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_audio.h +++ /dev/null @@ -1,120 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_AUDIO_H__ -#define __BL_AUDIO_H__ - -#include -#include -#include "bl808_audio.h" - -typedef int (*audio_callback_rx_ready_t)(void *usrdata, uint8_t *audiodata, int len, int is_overflow); -typedef int (*audio_callback_tx_ready_t)(void *uerdata, uint8_t *audiodata, int len, int is_underrun); - -#define AUDIO_PLAY_DEFAULT_INITIAL_VOLUME 0x0 -#define AUDIO_TX_FIFO_ADDR AUDIO_BASE + 0x94 -#define AUDIO_RX_FIFO_ADDR AUDIO_BASE + 0x88 -#define AUDIO_DEFAULT_TX_DRQ_THR 8 -#define AUDIO_DEFAULT_RX_DRQ_THR 8 - -typedef enum { - LEFT_CHANNEL = 1, /*!< select mono mode left only */ - RIGHT_CHANNEL = 2, /*!< select mono mode right only */ - STEREO_CHANNEL = 3, /*!< select stereo */ - THREE_CHANNEL = 7, /*!< select Three */ -} Audio_Channel_Type; - -typedef enum { - AUDIO_BIT_WIDTH_16, /*!< 16 bit */ - AUDIO_BIT_WIDTH_24, /*!< 24 bit */ - AUDIO_BIT_WIDTH_32, /*!< 32 bit */ -} Audio_BitWidth_Type; - -typedef enum { - AUDIO_8_KHZ, /*!< Audio DAC Clock set as 8KHZ */ - AUDIO_16_KHZ, /*!< Audio DAC Clock set as 16KHZ */ - AUDIO_24_KHZ, /*!< Audio DAC Clock set as 24KHZ */ - AUDIO_32_KHZ, /*!< Audio DAC Clock set as 32KHZ */ - AUDIO_48_KHZ, /*!< Audio DAC Clock set as 48KHZ */ - AUDIO_96_KHZ, /*!< Audio DAC Clock set as 96KHZ */ - AUDIO_192_KHZ, /*!< Audio DAC Clock set as 192KHZ */ -} Audio_Samplerate_Type; - -typedef struct { - uint8_t pingpang; - DMA_LLI_Ctrl_Type lli_tx_list[2]; - DMA_LLI_Ctrl_Type lli_rx_list[2]; - uint8_t *lli_tx_buffer; - uint32_t lli_tx_buffer_size; - uint8_t *lli_rx_buffer; - uint32_t lli_rx_buffer_size; - - int is_underrun; - int is_overflow; - audio_callback_tx_ready_t usr_cb; - audio_callback_rx_ready_t usr_rx_cb; - void *p_usr_arg; - void *p_usr_rx_arg; - - Audio_Samplerate_Type samplerate; - Audio_BitWidth_Type playBitWidth; - Audio_Channel_Type tx_channel; - Audio_Channel_Type rx_channel; - uint8_t rx_enable; - -} bl_audio_dev_t; - -int bl_audio_init (bl_audio_dev_t *p_dev); - -int bl_audio_deinit (bl_audio_dev_t *p_dev); - -int bl_audio_start (bl_audio_dev_t *p_dev); - -int bl_audio_stop (bl_audio_dev_t *p_dev); - -int bl_audio_tx_buffer_config (bl_audio_dev_t *p_dev, - void **ptr_mem, - uint32_t bufsize); - -int bl_audio_rx_buffer_config (bl_audio_dev_t *p_dev, - void **ptr_mem, - uint32_t bufsize); - -int bl_audio_tx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_tx_ready_t cb, - void *p_arg); - -int bl_audio_rx_ready_config(bl_audio_dev_t *p_dev, - audio_callback_rx_ready_t cb, - void *p_arg); - -int bl_audio_samplerate_set (bl_audio_dev_t *p_dev, - Audio_Samplerate_Type samplerate); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.c deleted file mode 100644 index 78abe66492..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.c +++ /dev/null @@ -1,145 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg, - PtTable_ID_Type targetTableID, - PtTable_Stuff_Config *ptStuff, - PtTable_Entry_Config *ptEntry) -{ - uint32_t i=0; - BL_Err_Type ret; - uint32_t writeAddr; - uint32_t entriesLen; - PtTable_Config *ptTable; - PtTable_Entry_Config *ptEntries; - uint32_t *pCrc32; - - if(ptEntry==NULL||ptStuff==NULL){ - return PT_ERROR_PARAMETER; - } - - ptTable=&ptStuff->ptTable; - ptEntries=ptStuff->ptEntries; - - if(targetTableID==PT_TABLE_ID_INVALID){ - return PT_ERROR_TABLE_NOT_VALID; - } - - if(targetTableID==PT_TABLE_ID_0){ - writeAddr=BFLB_PT_TABLE0_ADDRESS; - }else{ - writeAddr=BFLB_PT_TABLE1_ADDRESS; - } - for (i=0; i < ptTable->entryCnt; i++) { - if (ptEntries[i].type == ptEntry->type){ - memcpy(&ptEntries[i],ptEntry,sizeof(PtTable_Entry_Config)); - break; - } - } - if(i==ptTable->entryCnt){ - /* Not found this entry ,add new one */ - if(ptTable->entryCntentryCnt],ptEntry,sizeof(PtTable_Entry_Config)); - ptTable->entryCnt++; - }else{ - return PT_ERROR_ENTRY_UPDATE_FAIL; - } - } - - /* Prepare write back to flash */ - /* Update age */ - ptTable->age++; - ptTable->crc32=BFLB_Soft_CRC32((uint8_t*)ptTable,sizeof(PtTable_Config)-4); - - /* Update entries CRC */ - entriesLen=ptTable->entryCnt*sizeof(PtTable_Entry_Config); - pCrc32=(uint32_t *)((uint32_t)ptEntries+entriesLen); - *pCrc32=BFLB_Soft_CRC32((uint8_t *)&ptEntries[0],entriesLen); - - /* Write back to flash */ - /* Erase flash first */ - ret=bl_flash_erase(writeAddr,sizeof(PtTable_Config)+entriesLen+4); - if(ret!=SUCCESS){ - //MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - /* Write flash */ - ret=bl_flash_write(writeAddr,(uint8_t *)ptStuff,sizeof(PtTable_Stuff_Config)); - if(ret!=SUCCESS){ - //MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - return PT_ERROR_SUCCESS; -} - -PtTable_Error_Type PtTable_Get_Active_Entries(PtTable_Stuff_Config *ptStuff, - PtTable_Entry_Type type, - PtTable_Entry_Config *ptEntry) -{ - uint32_t i=0; - - if(ptStuff==NULL||ptEntry==NULL){ - return PT_ERROR_PARAMETER; - } - for (i=0; i < ptStuff->ptTable.entryCnt; i++) { - if (ptStuff->ptEntries[i].type == type){ - memcpy(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config)); - return PT_ERROR_SUCCESS; - } - } - return PT_ERROR_ENTRY_NOT_FOUND; -} - -PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff, - uint8_t *name, - PtTable_Entry_Config *ptEntry) -{ - uint32_t i=0; - uint32_t len=strlen((char *)name); - - if(ptStuff==NULL||ptEntry==NULL){ - return PT_ERROR_PARAMETER; - } - for (i=0; i < ptStuff->ptTable.entryCnt; i++) { - if (strlen((char *)ptStuff->ptEntries[i].name) == len && - memcmp((char *)ptStuff->ptEntries[i].name,(char *)name,len) == 0){ - //BL602_MemCpy_Fast(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config)); - /*FIXME :need fast memory copy*/ - memcpy(ptEntry,&ptStuff->ptEntries[i],sizeof(PtTable_Entry_Config)); - return PT_ERROR_SUCCESS; - } - } - return PT_ERROR_ENTRY_NOT_FOUND; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.h deleted file mode 100644 index 04f5747ce1..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_boot2.h +++ /dev/null @@ -1,197 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __BL606_PARTITION_H__ -#define __BL606_PARTITION_H__ - -#include - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -/** @addtogroup BL606_Common_Driver - * @{ - */ - -/** @addtogroup PARTITION - * @{ - */ - -/** @defgroup PARTITION_Public_Types - * @{ - */ - -/** - * @brief Partition table error type definition - */ -typedef enum { - PT_ERROR_SUCCESS, /*!< Partition table error type:success */ - PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:entry not found */ - PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */ - PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */ - PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */ - PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */ - PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */ - PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */ - PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */ -}PtTable_Error_Type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_TABLE_ID_0, /*!< Partition table ID 0 */ - PT_TABLE_ID_1, /*!< Partition table ID 1 */ - PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */ -}PtTable_ID_Type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ - PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ - PT_ENTRY_MAX=16, /*!< Partition entry type:Max */ -}PtTable_Entry_Type; - -/** - * @brief Partition table config definition - */ -typedef struct { - uint32_t magicCode; /*!< Partition table magic code */ - uint16_t version; /*!< Partition table verdion */ - uint16_t entryCnt; /*!< Partition table entry count */ - uint32_t age; /*!< Partition table age */ - uint32_t crc32; /*!< Partition table CRC32 value */ -}PtTable_Config; - -/** - * @brief Partition table entry config definition - */ -typedef struct { - uint8_t type; /*!< Partition entry type */ - uint8_t device; /*!< Partition entry device */ - uint8_t activeIndex; /*!< Partition entry active index */ - uint8_t name[9]; /*!< Partition entry name */ - uint32_t Address[2]; /*!< Partition entry start address */ - uint32_t maxLen[2]; /*!< Partition entry max length */ - uint32_t len; /*!< Partition entry length */ - uint32_t age; /*!< Partition entry age */ -}PtTable_Entry_Config; - -/** - * @brief Partition table stuff config definition - */ -typedef struct { - PtTable_Config ptTable; /*!< Partition table */ - PtTable_Entry_Config ptEntries[PT_ENTRY_MAX]; /*!< Partition entries */ - uint32_t crc32; /*!< Partition entries crc32 */ -}PtTable_Stuff_Config; - -/*@} end of group PARTITION_Public_Types */ - -/** @defgroup PARTITION_Public_Constants - * @{ - */ - -/** @defgroup PTTABLE_ERROR_TYPE - * @{ - */ -#define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \ - ((type) == PT_ERROR_TABLE_NOT_VALID) || \ - ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \ - ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \ - ((type) == PT_ERROR_CRC32) || \ - ((type) == PT_ERROR_PARAMETER) || \ - ((type) == PT_ERROR_FALSH_READ) || \ - ((type) == PT_ERROR_FALSH_WRITE) || \ - ((type) == PT_ERROR_FALSH_ERASE)) - -/** @defgroup PTTABLE_ID_TYPE - * @{ - */ -#define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \ - ((type) == PT_TABLE_ID_1) || \ - ((type) == PT_TABLE_ID_INVALID)) - -/** @defgroup PTTABLE_ENTRY_TYPE - * @{ - */ -#define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \ - ((type) == PT_ENTRY_FW_CPU1) || \ - ((type) == PT_ENTRY_MAX)) - -/*@} end of group PARTITION_Public_Constants */ - -/** @defgroup PARTITION_Public_Macros - * @{ - */ -#define BFLB_PT_TABLE0_ADDRESS 0xE000 -#define BFLB_PT_TABLE1_ADDRESS 0xF000 -#define BFLB_PT_MAGIC_CODE 0x54504642 -typedef BL_Err_Type (*pPtTable_Flash_Erase)(uint32_t startaddr,uint32_t endaddr); -typedef BL_Err_Type (*pPtTable_Flash_Write)(uint32_t addr,uint8_t *data, uint32_t len); -typedef BL_Err_Type (*pPtTable_Flash_Read)(uint32_t addr,uint8_t *data, uint32_t len); - -/*@} end of group PARTITION_Public_Macros */ - -/** @defgroup PARTITION_Public_Functions - * @{ - */ -void PtTable_Set_Flash_Operation(pPtTable_Flash_Erase erase,pPtTable_Flash_Write write); -PtTable_ID_Type PtTable_Get_Active_Partition(const SPI_Flash_Cfg_Type *pFlashCfg, - PtTable_Stuff_Config ptStuff[2]); -PtTable_Error_Type PtTable_Get_Active_Entries(PtTable_Stuff_Config *ptStuff, -PtTable_Entry_Type type, - PtTable_Entry_Config *ptEntry); -PtTable_Error_Type PtTable_Update_Entry(const SPI_Flash_Cfg_Type *pFlashCfg, -PtTable_ID_Type targetTableID, - PtTable_Stuff_Config *ptStuff, -PtTable_Entry_Config *ptEntry); -PtTable_Error_Type PtTable_Create(const SPI_Flash_Cfg_Type *pFlashCfg,PtTable_ID_Type ptID); -PtTable_Error_Type PtTable_Get_Active_Entries_By_Name(PtTable_Stuff_Config *ptStuff, - uint8_t *name, - PtTable_Entry_Config *ptEntry); - -/*@} end of group PARTITION_Public_Functions */ - -/*@} end of group PARTITION */ - -/*@} end of group BL606_Common_Driver */ - -#endif /* __BL606_PARTITION_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.c deleted file mode 100644 index 3af88bcfce..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.c +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include "bl_cam.h" - -#define MJPEG_DEFAULT_ADDR 0x80400000 - -int bl_cam_mjpeg_buffer_info_get(uint32_t *mjpeg_addr, uint32_t *mjpeg_size) -{ - int ret = 0; - uint32_t tmpVal; - - *mjpeg_addr = BL_RD_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR); - if (*mjpeg_addr == MJPEG_DEFAULT_ADDR) { - *mjpeg_addr = 0; - ret = -1; - goto exit; - } - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_XLEN); - /*get memory brust size 0 sigle; 1 INCR4; 2 INCR8; 3 INCR16*/ - *mjpeg_size = BL_RD_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY); - *mjpeg_size = *mjpeg_size << (3 + tmpVal + (tmpVal > 0 ? 1 : 0)); - -exit: - return ret; -} - -int bl_cam_mjpeg_get(uint8_t **ptr, uint32_t *len) -{ - int ret = 0; - MJPEG_Frame_Info mjpeg_info; - MJPEG_Get_Frame_Info(&mjpeg_info); - - if (mjpeg_info.validFrames > 0) { - *ptr = (uint8_t *)(uintptr_t)mjpeg_info.curFrameAddr; - *len = mjpeg_info.curFrameBytes; - } else { - ret = -1; - } - return ret; -} - -int bl_cam_mjpeg_pop(void) -{ - MJPEG_Pop_Frame(); - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.h deleted file mode 100644 index 4860fc47b5..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_cam.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_CAM_H__ -#define __BL_CAM_H__ -int bl_cam_mjpeg_get(uint8_t **ptr, uint32_t *len); -int bl_cam_mjpeg_pop(); -int bl_cam_mjpeg_buffer_info_get(uint32_t *mjpeg_addr, uint32_t *mjpeg_size); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.c deleted file mode 100644 index b0ae92815c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.c +++ /dev/null @@ -1,188 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -#include "bl_chip.h" - -static unsigned long _risc_isa_info(void) -{ - volatile unsigned long misa = 0; - - __asm volatile( "csrr %0, misa" : "=r"( misa ) ); - - return misa; -} - - -int bl_chip_info(char *info) -{ - unsigned long misa; - int i; - i = sizeof(misa) * 8 - 2; // MXL field pos - - misa = _risc_isa_info(); - - /*Get base ISA*/ - i = (misa >> i); - switch (i) { - case 1: - { - memcpy(info, "RV32", 4); - info += 4; - } - break; - case 2: - { - memcpy(info, "RV64", 4); - info += 4; - } - break; - case 3: - { - memcpy(info, "RV128", 5); - info += 5; - } - break; - default: - { - memcpy(info, "RVxx", 4); - info += 4; - } - break; - } - - /*add switch*/ - *(info++) = '-'; - - /*add feature set*/ - for (i = 0; i < 26; i++) { - if (misa & (1 << i)) { - /*Feature bit is set*/ - *(info++) = ('A' + i); - } - } - *info = '\0'; - - return 0; -} - -static const char bannder_shadow_bl602[] = { - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0x20, 0x20, 0x20, 0x20, - 0x20, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0x20, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x91, 0x20, 0x20, 0x20, 0x20, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x97, 0xe2, 0x95, 0x9a, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x97, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, - 0xe2, 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x91, - 0x20, 0x20, 0x20, 0x20, 0x20, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x97, 0x20, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, - 0xe2, 0x95, 0x91, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, - 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x91, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x9d, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x91, 0x20, 0x20, 0x20, 0x20, 0x20, 0xe2, 0x96, - 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, - 0x97, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, 0x96, - 0x88, 0xe2, 0x95, 0x91, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, - 0x94, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x9d, 0x0a, 0x0d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, - 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x97, 0xe2, 0x95, 0x9a, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x95, 0x94, 0xe2, 0x95, 0x9d, 0xe2, 0x95, 0x9a, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x95, 0x94, 0xe2, 0x95, 0x9d, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, - 0x96, 0x88, 0xe2, 0x96, 0x88, 0xe2, 0x95, 0x97, 0x0a, 0x0d, 0xe2, 0x95, 0x9a, - 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, - 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, 0x95, 0x9a, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, 0x95, 0x9a, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x20, 0x20, 0xe2, 0x95, 0x9a, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, - 0x90, 0xe2, 0x95, 0x9d, 0x20, 0xe2, 0x95, 0x9a, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, 0x95, 0x90, 0xe2, - 0x95, 0x90, 0xe2, 0x95, 0x9d, 0x0a, 0x0d, 0x00 -}; - -int bl_chip_banner(const char **banner) -{ - *banner = bannder_shadow_bl602; - return 0; -} - -int bl_chip_memory_ram(int *num, unsigned int addr[], unsigned int size[], char desc[][6]) -{ - return -1; -#if 0 - if (*num < 3) { - /*only one block memory*/ - return -1; - } - *num = 3; - -extern uint8_t _ld_ram_size0, _ld_ram_addr0; -extern uint8_t _ld_ram_size1, _ld_ram_addr1; -extern uint8_t _ld_ram_size2, _ld_ram_addr2; - addr[0] = (unsigned int)&_ld_ram_addr0; - size[0] = (unsigned int)&_ld_ram_size0; - strcpy(desc[0], "flash"); - addr[1] = (unsigned int)&_ld_ram_addr1; - size[1] = (unsigned int)&_ld_ram_size1; - strcpy(desc[1], "tcm"); - addr[2] = (unsigned int)&_ld_ram_addr2; - size[2] = (unsigned int)&_ld_ram_size2; - strcpy(desc[2], "wifi"); - return 0; -#endif -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.h deleted file mode 100644 index 3f8744eea4..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_chip.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_CHIP_H__ -#define __BL_CHIP_H__ -int bl_chip_info(char *info); -int bl_chip_banner(const char **banner); -int bl_chip_memory_ram(int *num, unsigned int addr[], unsigned int size[], char desc[][6]); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.c deleted file mode 100644 index 80a9015464..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.c +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_efuse.h" -#ifdef BL808 -#include -#include "bl808_mfg_media.h" -#include "bl808_glb.h" -#endif - -int bl_efuse_read_mac(uint8_t mac[6]) -{ - EF_Ctrl_Read_MAC_Address(mac); - return 0; -} - -int bl_efuse_read_mac_factory(uint8_t mac[6]) -{ - // if (0 == mfg_media_read_macaddr(mac, 1)) { - // return 0; - //zys } - return -1; -} - -int bl_efuse_read_capcode(uint8_t *capcode) -{ -// if (0 == mfg_media_read_xtal_capcode(capcode, 1)) { - // return 0; - //zys } - return -1; -} - -int bl_efuse_read_pwroft(int8_t poweroffset[14]) -{ - // if (0 == mfg_media_read_poweroffset(poweroffset, 1)) { - // return 0; - //} - return -1; -} - -int bl_efuse_ctrl_program_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint8_t hdiv=0, bdiv=0; - HBN_MCU_ROOT_CLK_Type rtClk=(HBN_MCU_ROOT_CLK_Type)HBN_Get_MCU_Root_CLK_Sel(); - -// bdiv=GLB_Get_BCLK_Div(); -// hdiv=GLB_Get_HCLK_Div(); - hdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - - EF_Ctrl_Program_Direct_R0(index, data, len); - - GLB_Set_System_CLK_Div(hdiv, bdiv); - HBN_Set_MCU_Root_CLK_Sel(rtClk); - - return 0; -} - -int bl_efuse_ctrl_read_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint8_t hdiv=0, bdiv=0; - HBN_MCU_ROOT_CLK_Type rtClk=(HBN_MCU_ROOT_CLK_Type)HBN_Get_MCU_Root_CLK_Sel(); - -// bdiv=GLB_Get_BCLK_Div(); -// hdiv=GLB_Get_HCLK_Div(); - hdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - - - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - - EF_Ctrl_Read_Direct_R0(index, data, len); - - GLB_Set_System_CLK_Div(hdiv, bdiv); - HBN_Set_MCU_Root_CLK_Sel(rtClk); - - return 0; -} - -int bl_efuse_read_mac_opt(uint8_t slot, uint8_t mac[6], uint8_t reload) -{ - uint8_t hdiv=0, bdiv=0; - HBN_MCU_ROOT_CLK_Type rtClk=(HBN_MCU_ROOT_CLK_Type)HBN_Get_MCU_Root_CLK_Sel(); - -// bdiv=GLB_Get_BCLK_Div(); -// hdiv=GLB_Get_HCLK_Div(); - hdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - bdiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - -// EF_Ctrl_Read_MAC_Address_Opt(slot, mac, reload); - EF_Ctrl_Read_MAC_Address_Raw(mac); - - GLB_Set_System_CLK_Div(hdiv, bdiv); - HBN_Set_MCU_Root_CLK_Sel(rtClk); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.h deleted file mode 100644 index 48a6bc864e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_efuse.h +++ /dev/null @@ -1,40 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_EFUSE_H__ -#define __BL_EFUSE_H__ -#include -int bl_efuse_read_mac(uint8_t mac[6]); -int bl_efuse_read_mac_factory(uint8_t mac[6]); -int bl_efuse_read_capcode(uint8_t *capcode); -int bl_efuse_read_pwroft(int8_t poweroffset[14]); -int bl_efuse_ctrl_program_R0(uint32_t index, uint32_t *data, uint32_t len); -int bl_efuse_ctrl_read_R0(uint32_t index, uint32_t *data, uint32_t len); -int bl_efuse_read_mac_opt(uint8_t slot, uint8_t mac[6], uint8_t reload); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.c deleted file mode 100644 index b5e463da8b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.c +++ /dev/null @@ -1,746 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "lwip/opt.h" -#include "lwip/timeouts.h" -#include "lwip/netif.h" -#include "lwip/err.h" -#define LWIP_DHCP 1 -#if LWIP_DHCP -#include "lwip/dhcp.h" -#endif -#include "netif/etharp.h" -#include "bl_ethernetif.h" -#include -#include "hal_emac.h" -#include -#include "semphr.h" -#if CTX_TYPE -#include -#endif -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Network interface name */ -#define IFNAME0 'b' -#define IFNAME1 'l' - -#define ETH_DMA_TRANSMIT_TIMEOUT (20U) - -#define BL702_EMAC 0 -#define EMAC_OUTPUT BL702_EMAC - -#if LWIP_DHCP -#define MAX_DHCP_TRIES 4 -uint32_t DHCPfineTimer = 0; -uint8_t DHCP_state = DHCP_OFF; -// #else -/*Static IP ADDRESS: IP_ADDR0.IP_ADDR1.IP_ADDR2.IP_ADDR3 */ -#define IP_ADDR0 (uint8_t)192 -#define IP_ADDR1 (uint8_t)168 -#define IP_ADDR2 (uint8_t)10 -#define IP_ADDR3 (uint8_t)221 - -/*NETMASK*/ -#define NETMASK_ADDR0 (uint8_t)255 -#define NETMASK_ADDR1 (uint8_t)255 -#define NETMASK_ADDR2 (uint8_t)255 -#define NETMASK_ADDR3 (uint8_t)0 - -/*Gateway Address*/ -#define GW_ADDR0 (uint8_t)192 -#define GW_ADDR1 (uint8_t)168 -#define GW_ADDR2 (uint8_t)10 -#define GW_ADDR3 (uint8_t)1 -#endif - -#if CTX_TYPE -extern EMAC_Handle_Type *thiz; -eth_context *ctx = NULL; -TaskHandle_t DequeueTaskHandle; -TaskHandle_t OutputTaskHandle; -#endif -/* Private function prototypes -----------------------------------------------*/ -void pbuf_free_custom(struct pbuf *p); -void ethernetif_input(struct netif *netif); -SemaphoreHandle_t emac_rx_sem = NULL; -static StackType_t emac_rx_stack[256]; -static StaticTask_t emac_rx_handle; -#if LWIP_DHCP -static StackType_t emac_dhcp_stack[256]; -static StaticTask_t emac_dhcp_handle; -#endif -static uint8_t emac_rx_buffer[ETH_RX_BUFFER_SIZE] __attribute__((aligned(16))) = { 0 }; - -LWIP_MEMPOOL_DECLARE(RX_POOL, 10, sizeof(struct pbuf_custom), "Zero-copy RX PBUF pool"); - -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* - LL Driver Interface ( LwIP stack --> ETH) -*******************************************************************************/ -/** - * @brief In this function, the hardware should be initialized. - * Called from ethernetif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -extern void emac_init_txrx_buffer(void); -extern int emac_phy_init(emac_phy_cfg_t *cfg); - -/* For emac tx and rx,we put here to make controlling it's size easy */ -#define ETH_RXBUFNB 6 -#define ETH_TXBUFNB 4 -#define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram"))) -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethRxBuff[ETH_RXBUFNB][ETH_RX_BUFFER_SIZE] ATTR_EALIGN(4) = { 0 }; /* Ethernet Receive Buffers */ -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethTxBuff[ETH_TXBUFNB][ETH_TX_BUFFER_SIZE] ATTR_EALIGN(4); /* Ethernet Transmit Buffers */ -void emac_init_txrx_buffer(void) -{ -#if CTX_TYPE - ctx = pvPortMalloc(sizeof(eth_context)); - memset(ctx, 0, sizeof(eth_context)); - utils_list_init(&ctx->unsent); -#endif - - emac_bd_init((uint8_t *)ethTxBuff, ETH_TXBUFNB, (uint8_t *)ethRxBuff, ETH_RXBUFNB); -} -void dhcp_thread(void const *argument); -void low_level_init(struct netif *netif) -{ - int ret = 0; - - emac_device_t emac_cfg = { - .mac_addr[0] = 0x18, - .mac_addr[1] = 0xB9, - .mac_addr[2] = 0x05, - .mac_addr[3] = 0x12, - .mac_addr[4] = 0x34, - .mac_addr[5] = 0x56, - }; - - /* set phy cfg */ - emac_phy_cfg_t phy_cfg = { - .auto_negotiation = 1, /*!< Speed and mode auto negotiation */ - .full_duplex = 0, /*!< Duplex mode */ - .speed = 0, /*!< Speed mode */ - .phy_address = 1, /*!< PHY address */ - .phy_id = 0x7c0f0, /*!< PHY OUI, masked */ - .phy_state = PHY_STATE_DOWN, - }; - - /* set MAC hardware address length */ - netif->hwaddr_len = ETH_HWADDR_LEN; - - /* set MAC hardware address */ - netif->hwaddr[0] = emac_cfg.mac_addr[0]; - netif->hwaddr[1] = emac_cfg.mac_addr[1]; - netif->hwaddr[2] = emac_cfg.mac_addr[2]; - netif->hwaddr[3] = emac_cfg.mac_addr[3]; - netif->hwaddr[4] = emac_cfg.mac_addr[4]; - netif->hwaddr[5] = emac_cfg.mac_addr[5]; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* emac init,configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */ - MSG("emac_init\r\n"); - emac_init(&emac_cfg); - - ret = emac_phy_init(&phy_cfg); - if (PHY_STATE_UP == phy_cfg.phy_state) { - MSG("PHY[%x] @%d ready on %dMbps, %s duplex\n\r", (int)phy_cfg.phy_id, (int)phy_cfg.phy_address, - (int)phy_cfg.speed, - phy_cfg.full_duplex ? "full" : "half"); - } else { - MSG("PHY Init fail\n\r"); - BL_CASE_FAIL; - while (1) - ; - } - emac_init_txrx_buffer(); - emac_start(); - // emac_start_tx(); - - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; - - /* Initialize the RX POOL */ - LWIP_MEMPOOL_INIT(RX_POOL); - - /* create a binary semaphore used for informing ethernetif of frame reception */ - //vSemaphoreCreateBinary(emac_rx_sem); - emac_rx_sem = xSemaphoreCreateBinary(); - -#if !CTX_TYPE - /* create the task that handles the ETH_MAC */ - MSG("[OS] Starting emac rx task...\r\n"); - xTaskCreateStatic(ethernetif_input, (char *)"emac_rx_task", sizeof(emac_rx_stack) / 4, netif, 16, emac_rx_stack, &emac_rx_handle); -#endif -#if LWIP_DHCP - MSG("[OS] Starting emac dhcp task...\r\n"); - xTaskCreateStatic(dhcp_thread, (char *)"emac_dhcp_task", sizeof(emac_dhcp_stack) / 4, netif, 16, emac_dhcp_stack, &emac_dhcp_handle); -#endif - - if (ret == 0) { - MSG("[OS] %s Netif is up\r\n", netif->name); - netif_set_up(netif); - netif_set_link_up(netif); - } -} - -void emac_tx_error_callback_app() -{ - MSG("EMAC tx error callback\r\n"); -} - -void emac_rx_error_callback_app() -{ - MSG("EMAC rx error callback\r\n"); - // MSG("EMAC tx bd num 0x%x\r\n", BL_RD_WORD(0x4000D020)); - // MSG("EMAC rx bd description0 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8))); - // MSG("EMAC rx bd description1 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8) + 0x4)); -} -/** - * @brief This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to - * strange results. You might consider waiting for space in the DMA queue - * to become available since the stack doesn't retry to send a packet - * dropped because of memory failure (except for the TCP timers). - */ - -static unsigned char emac_send_buf[1514]; -static err_t low_level_output(struct netif *netif, struct pbuf *p) -{ -#if CTX_TYPE - struct unsent_item *item; - - if (pbuf_header(p, PBUF_LINK_ENCAPSULATION_HLEN)) { - printf("[TX] Reserve room failed for header\r\n"); - return ERR_IF; - } - item = (struct unsent_item *)(((uintptr_t)(p->payload + 3))&(~3)); - item->p = p; - - pbuf_ref(p); - __disable_irq(); - utils_list_push_back(&ctx->unsent, (struct utils_list_hdr *)&(item->hdr)); - ctx->unsent_num++; - __enable_irq(); - xTaskNotify(DequeueTaskHandle, 0x01, eSetBits); - - return ERR_OK; -#else - err_t errval = ERR_OK; - struct pbuf *q; - - if (!emac_bd_fragment_support()){ - - uint32_t byteslefttocopy = 0; - // uint32_t payloadoffset = 0; - // uint32_t bufferoffset = 0; - uint32_t framelength = 0; - uint32_t flags = (EMAC_NORMAL_PACKET); - - for (q = p; q != NULL; q = q->next) { - // MSG("p->tot_len:%d,q->len:%d, q->next:%d,f:%d\r\n", q->tot_len, q->len, q->next, framelength); - - byteslefttocopy = q->len; - // payloadoffset = 0; - - // check is copy data is larger than emac tx buf - while ((byteslefttocopy + framelength) > ETH_TX_BUFFER_SIZE) { - // copy data to tx buf - MSG("tx buf is too larger!\r\n"); - flags = EMAC_FRAGMENT_PACKET; - // ARCH_MemCpy_Fast(&emac_send_buf[framelength + bufferoffset], q->payload + payloadoffset, (ETH_TX_BUFFER_SIZE - bufferoffset)); - } - ARCH_MemCpy_Fast(&emac_send_buf[framelength], q->payload, byteslefttocopy); - // bufferoffset = bufferoffset + byteslefttocopy; - framelength = framelength + byteslefttocopy; - } - - if (0 != emac_bd_tx_enqueue(flags, framelength, emac_send_buf)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - - }else{ - for (q = p; q != NULL; q = q->next) { - //MSG("p->tot_len:%d,q->len:%d, q->next:%d\r\n", q->tot_len, q->len, q->next); - if (q->len == q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_NORMAL_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else if (q->len < q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_FRAGMENT_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else { - MSG("low_level_output error! Wrong packet!\r\n"); - } - } - } - - return errval; -#endif -} - -/** - * @brief Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - * @param netif the lwip network interface structure for this ethernetif - * @return a pbuf filled with the received packet (including MAC header) - * NULL on memory error - */ -static struct pbuf *low_level_input(struct netif *netif) -{ -#if CTX_TYPE - uint16_t pkt_len; - uint16_t max_len, min_len; - struct pbuf *h = NULL; - EMAC_BD_Desc_Type *bd; - bd = &thiz->bd[thiz->rxIndexCPU]; - if(bd->C_S_L & EMAC_BD_FIELD_MSK(RX_E)){ - // MSG("RX BD is empty\r\n"); - h = NULL; - } else { - emac_get_fram_len(&max_len, &min_len); - pkt_len = (bd->C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS; - //check length - if (pkt_len > max_len) { - MSG("pkt is too huge %d\r\n", pkt_len); - return NULL; - } - if (bd->C_S_L & 0xFF) { - // MSG("RX bd %x\r\n", (int)bd->C_S_L & 0xFF); - } - if ((bd->C_S_L >>16) == ETH_MAX_BUFFER_SIZE) { - puts("Bug now...\r\n"); - } - - h = pbuf_alloc(PBUF_RAW, pkt_len, PBUF_POOL); - if (h) { - pbuf_take(h, bd->Buffer, pkt_len); - } - if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) { - /* wrap back */ - thiz->rxIndexCPU = thiz->txBuffLimit + 1; - bd->C_S_L = (EMAC_BD_FIELD_MSK(RX_IRQ) | EMAC_BD_FIELD_MSK(RX_E) | (ETH_MAX_BUFFER_SIZE << 16) | EMAC_BD_FIELD_MSK(RX_WR)); - } else { - bd->C_S_L = (EMAC_BD_FIELD_MSK(RX_IRQ) | EMAC_BD_FIELD_MSK(RX_E) | (ETH_MAX_BUFFER_SIZE << 16)); - } - } - return h; -#else - uint32_t rx_len = 0; - struct pbuf *p = NULL, *q; - - emac_bd_rx_dequeue(-1, &rx_len, emac_rx_buffer); - - if (rx_len <= 0) { - //MSG("Recv Null Data\r\n"); - return NULL; - } - - //MSG("Recv full Data\r\n"); - - p = pbuf_alloc(PBUF_RAW, rx_len, PBUF_POOL); - - if (p != NULL) { - for (q = p; q != NULL; q = q->next) { - memcpy(q->payload, emac_rx_buffer + rx_len - q->tot_len, q->len); - } - } - - return p; -#endif -} - -void emac_rx_done_callback_app(void) -{ - BaseType_t xHigherPriorityTaskWoken; - - /* Is it time for vATask() to run? */ - xHigherPriorityTaskWoken = pdFALSE; - //MSG("emac_rx_done_callback_app\r\n"); - //low_level_input(NULL); - xSemaphoreGiveFromISR(emac_rx_sem, &xHigherPriorityTaskWoken); - /* If xHigherPriorityTaskWoken was set to true you - we should yield. The actual macro used here is - port specific. */ - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -} - -#if CTX_TYPE -void ethernetif_output(struct netif *netif) -{ - struct unsent_item *item; - struct pbuf *q, *p; - EMAC_BD_Desc_Type *bd; - int wrap_found, offset; - - bd = &thiz->bd[thiz->txIndexCPU]; - while (0 == (bd->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) && ctx->unsent_num) { - - __disable_irq(); - item = (struct unsent_item *)utils_list_pop_front(&ctx->unsent); - ctx->unsent_num--; - __enable_irq(); - - p = item->p; - p->len -= PBUF_LINK_ENCAPSULATION_HLEN; - p->tot_len -= PBUF_LINK_ENCAPSULATION_HLEN; - p->payload += PBUF_LINK_ENCAPSULATION_HLEN; - if ((++thiz->txIndexCPU) > thiz->txBuffLimit) { - /* wrap back */ - thiz->txIndexCPU = 0; - wrap_found = 1; - } else { - wrap_found = 0; - } - - offset = 0; - for (q = p; q != NULL; q = q->next) { - memcpy((uint8_t *)bd->Buffer + offset, (uint8_t*)q->payload, q->len); - offset += q->len; - } - - bd->C_S_L = (wrap_found ? EMAC_BD_FIELD_MSK(TX_WR) : 0) | EMAC_TX_COMMON_FLAGS | p->tot_len << BD_TX_LEN_POS; - pbuf_free(p); - bd = &thiz->bd[thiz->txIndexCPU]; - } -} -#endif - -/** - * @brief This function is the ethernetif_input task, it is processed when a packet - * is ready to be read from the interface. It uses the function low_level_input() - * that should handle the actual reception of bytes from the network - * interface. Then the type of the received packet is determined and - * the appropriate input function is called. - * - * @param netif the lwip network interface structure for this ethernetif - */ -void ethernetif_input(struct netif *netif) -{ - struct pbuf *p = NULL; - -#if CTX_TYPE - static unsigned int rx_counter; - err_t err = ERR_OK; - EMAC_BD_Desc_Type *bd; - - /* move received packet into a new pbuf */ - do { - p = low_level_input(netif); - bd = &thiz->bd[thiz->rxIndexCPU]; - - rx_counter++; - /* no packet could be read, silently ignore this */ - if (p == NULL) return; - - /* entry point to the LwIP stack */ - err = netif->input(p, netif); - - if (err != ERR_OK) - { - LWIP_DEBUGF(NETIF_DEBUG, ("ethernetif_input: IP input error\n")); - pbuf_free(p); - } - } while (!(bd->C_S_L & EMAC_BD_FIELD_MSK(RX_E))); - return; -#else - for (;;) { - if (xSemaphoreTake(emac_rx_sem, portMAX_DELAY) == pdTRUE) { - do { - p = low_level_input(netif); - - if (p != NULL) { - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } - } - } while (p != NULL); - } - } -#endif -} - -#if CTX_TYPE -void unsent_recv_task(void *pvParameters) -{ - struct netif *netif = (struct netif *)pvParameters; - uint32_t NotifyValue; - BaseType_t recv; - printf("unsent_recv_task.\r\n"); - while(1) { - NotifyValue = 0; - recv = xTaskNotifyWait(0, ULONG_MAX, &NotifyValue, 200); - if (recv == pdTRUE) { - if (NotifyValue & (1 << 0)) { - ethernetif_output(netif); - emac_intmask(EMAC_INT_TX_DONE, UNMASK); - } - if (NotifyValue & (1 << 1)) { - ethernetif_input(netif); - emac_intmask(EMAC_INT_RX_DONE, UNMASK); - } - } else { - /*XXX only work when we has no EVENT. Maybe buggy here??*/ - // _emac_phy_if_init(); - // printf("no EVENT!\r\n"); - } - } -} -#endif - -/** - * @brief Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t ethernetif_init(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; -#endif /* LWIP_NETIF_HOSTNAME */ - - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); -#if CTX_TYPE - xTaskCreate(unsent_recv_task, (const char *)"Ontput_Unsent_queue", 1024, netif, 29, &DequeueTaskHandle); -#endif - - return ERR_OK; -} - -/** - * @brief Custom Rx pbuf free callback - * @param pbuf: pbuf to be freed - * @retval None - */ -void pbuf_free_custom(struct pbuf *p) -{ - struct pbuf_custom *custom_pbuf = (struct pbuf_custom *)p; - LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); -} - -static void ethernet_set_static_ip(struct netif *netif) -{ - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - - IP4_ADDR(&ipaddr, IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3); - IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3); - IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); - netif_set_addr(netif, ip_2_ip4(&ipaddr), ip_2_ip4(&netmask), ip_2_ip4(&gw)); -} - -/** - * @brief Notify the User about the network interface config status - * @param netif: the network interface - * @retval None - */ -void ethernet_link_status_updated(struct netif *netif) -{ - if (netif_is_link_up(netif)) { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_START; - MSG("DHCP Start\r\n"); -#else - /* IP address default setting */ - ethernet_set_static_ip(netif); - uint8_t iptxt[20]; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("Static IP address: %s\r\n", iptxt); -#endif - } else { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_LINK_DOWN; -#else - MSG("The network cable is not connected.\r\n"); -#endif /* LWIP_DHCP */ - } -} - -/** - * @brief - * @retval None - */ -void ethernet_link_check_state(struct netif *netif) -{ - emac_phy_status_t phy_state; - - uint32_t linkchanged = 0; - // uint32_t speed = 0, duplex = 0; - - phy_state = ethernet_phy_status_get(); - - if (netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Link Down\n"); - emac_stop(); - netif_set_down(netif); - netif_set_link_down(netif); - } else if (!netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Reinit\n"); - emac_phy_init(NULL); - } else if (!netif_is_link_up(netif) && (phy_state > EMAC_PHY_STAT_LINK_UP)) { - // switch (phy_state) { - // case EMAC_PHY_STAT_100MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_100MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 10; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 10; - // linkchanged = 1; - // break; - - // default: - // break; - // } - - if (linkchanged) { - /* Get MAC Config MAC */ - //HAL_ETH_GetMACConfig(&EthHandle, &MACConf); - //MACConf.DuplexMode = duplex; - //MACConf.Speed = speed; - //HAL_ETH_SetMACConfig(&EthHandle, &MACConf); - //HAL_ETH_Start(&EthHandle); - netif_set_up(netif); - netif_set_link_up(netif); - } - } -} - -#if LWIP_DHCP -/** - * @brief DHCP Process - * @param argument: network interface - * @retval None - */ -void dhcp_thread(void const *argument) -{ - struct netif *netif = (struct netif *)argument; - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - struct dhcp *dhcp; - uint8_t iptxt[20]; - - for (;;) { - switch (DHCP_state) { - case DHCP_START: { - ip_addr_set_zero_ip4(&netif->ip_addr); - ip_addr_set_zero_ip4(&netif->netmask); - ip_addr_set_zero_ip4(&netif->gw); - DHCP_state = DHCP_WAIT_ADDRESS; - MSG("State: Looking for DHCP server ...\r\n"); - dhcp_start(netif); - } break; - case DHCP_WAIT_ADDRESS: { - if (dhcp_supplied_address(netif)) { - DHCP_state = DHCP_ADDRESS_ASSIGNED; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("IP address assigned by a DHCP server: %s\r\n", iptxt); - } else { - dhcp = (struct dhcp *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP); - - /* DHCP timeout */ - if (dhcp->tries > MAX_DHCP_TRIES) { - DHCP_state = DHCP_TIMEOUT; - - /* Static address used */ - ethernet_set_static_ip(netif); - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("DHCP Timeout !!\r\n"); - MSG("Static IP address: %s\r\n", iptxt); - } - } - } break; - case DHCP_LINK_DOWN: { - DHCP_state = DHCP_OFF; - MSG("The network cable is not connected \r\n"); - } break; - default: - break; - } - vTaskDelay(100); - } -} -#endif /* LWIP_DHCP */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.h deleted file mode 100644 index 2f2746c124..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ethernetif.h +++ /dev/null @@ -1,76 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __ETHERNETIF_H__ -#define __ETHERNETIF_H__ -#include "hal_emac.h" -#if CTX_TYPE -#include -#endif -#include "lwip/err.h" -#include "lwip/netif.h" -#include "ethernet_phy.h" - -#define DHCP_OFF (uint8_t)0 -#define DHCP_START (uint8_t)1 -#define DHCP_WAIT_ADDRESS (uint8_t)2 -#define DHCP_ADDRESS_ASSIGNED (uint8_t)3 -#define DHCP_TIMEOUT (uint8_t)4 -#define DHCP_LINK_DOWN (uint8_t)5 - -#if CTX_TYPE -#define ETH_MAX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \ - EMAC_BD_FIELD_MSK(TX_IRQ) | \ - EMAC_BD_FIELD_MSK(TX_PAD) | \ - EMAC_BD_FIELD_MSK(TX_CRC) | \ - EMAC_BD_FIELD_MSK(TX_EOF) ) - -struct unsent_item{ - struct utils_list_hdr hdr; - struct pbuf *p; -}; - -typedef struct { - struct utils_list unsent; - uint8_t Tx_free_bd_num; - uint8_t Rx_free_bd_num; - volatile uint16_t unsent_num; - uint32_t tx_pkt_cnt; - uint32_t rx_pkt_cnt; - uint32_t out_tmr; - uint32_t done_tmr; -}eth_context; -#endif -/* Exported types ------------------------------------------------------------*/ -err_t ethernetif_init(struct netif *netif); -void ethernet_link_check_state(struct netif *netif); -void ethernet_link_status_updated(struct netif *netif); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.c deleted file mode 100644 index eb6fcdec81..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.c +++ /dev/null @@ -1,184 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#ifdef BL808 -#include -#include -#include -#include -#elif defined(BL606P) -#include -#include -#include -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl_irq.h" - -#define XIP_START_ADDR (0x58000000) -#define ADDR_LIMIT (0x1000000) - -#define USER_UNUSED(a) ((void)(a)) -static SPI_Flash_Cfg_Type g_flash_cfg; - -/** - * @brief flash read data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_read(uint32_t startaddr, void *data, uint32_t len) -{ - BL_Err_Type stat; - uint8_t isAesEnable=0; - - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, startaddr, data, len, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return stat; -} - -/** - * @brief flash write data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_write(uint32_t startaddr, void *data, uint32_t len) -{ - BL_Err_Type stat; - uint8_t isAesEnable=0; - - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, startaddr, data, len, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return stat; -} - -/** - * @brief flash erase - * - * @param startaddr - * @param endaddr - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_erase(uint32_t startaddr, uint32_t len) -{ - BL_Err_Type stat; - uint8_t isAesEnable=0; - - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, len-1, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return stat; -} - -/** - * @brief flash read from xip - * - * @param xip addr - * @param dst - * @param len - * @return BL_Err_Type - */ -int bl_flash_read_byxip(uint32_t addr, uint8_t *dst, int len) -{ - uint32_t offset; - uint32_t xipaddr; - - offset = RomDriver_SF_Ctrl_Get_Flash_Image_Offset(0, 0); - - if ((addr < offset) || (addr >= ADDR_LIMIT)) { - // not support or arg err ? - return -1; - } - - xipaddr = XIP_START_ADDR - offset + addr; - memcpy(dst, (void *)xipaddr, len); - - return 0; -} - -/** - * @brief multi flash adapter - * - * @return BL_Err_Type - */ -int ATTR_TCM_SECTION bl_flash_init(void) -{ - uint8_t isAesEnable=0; - - /* Get flash config identify */ - GLOBAL_IRQ_SAVE(); - XIP_SFlash_Opt_Enter(&isAesEnable); - SF_Cfg_Flash_Identify_Ext(1, 0x80, 0, &g_flash_cfg, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - GLOBAL_IRQ_RESTORE(); - - return 0; -} - -static void _dump_flash_config() -{ - extern uint8_t __boot2_flashCfg_src; - - USER_UNUSED(__boot2_flashCfg_src); - - blog_info("======= FlashCfg magiccode @%p=======\r\n", &__boot2_flashCfg_src); - blog_info("mid \t\t0x%X\r\n", g_flash_cfg.mid); - blog_info("clkDelay \t0x%X\r\n", g_flash_cfg.clkDelay); - blog_info("clkInvert \t0x%X\r\n", g_flash_cfg.clkInvert); - blog_info("sector size\t%uKBytes\r\n", g_flash_cfg.sectorSize); - blog_info("page size\t%uBytes\r\n", g_flash_cfg.pageSize); - blog_info("---------------------------------------------------------------\r\n"); -} - -int bl_flash_config_update(void) -{ - _dump_flash_config(); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.h deleted file mode 100644 index 1bf262137b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_flash.h +++ /dev/null @@ -1,42 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_FLASH_H__ -#define __BL_FLASH_H__ -#include - -int bl_flash_erase(uint32_t addr, int len); -int bl_flash_write(uint32_t addr, void *src, int len); -int bl_flash_read(uint32_t addr, void *dst, int len); -int bl_flash_config_update(void); -void* bl_flash_get_flashCfg(void); - -int bl_flash_read_byxip(uint32_t addr, uint8_t *dst, int len); -int bl_flash_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.c deleted file mode 100644 index 328841c527..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_ipc.h" - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - - -extern void IPC_Common_Interrupt_Handler(uint32_t irqStatus, ipcIntCallback *callBack[GLB_CORE_ID_MAX -1]); -extern ipcIntCallback *m0IpcIntCbfArra[GLB_CORE_ID_MAX - 1]; - -static void ipc_m0_handler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_M0_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, m0IpcIntCbfArra); - IPC_M0_Clear_Int_By_Word(irqStatus); -} -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -void ipc_m0_init(ipcIntCallback *onLPTriggerCallBack, - ipcIntCallback *onD0TriggerCallBack) -{ - IPC_M0_Init(onLPTriggerCallBack, onD0TriggerCallBack); - -#ifdef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_M0_IRQn, ipc_m0_handler); -#endif - - System_NVIC_SetPriority(IPC_M0_IRQn, 5, 0); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.h deleted file mode 100644 index 1bb38c92ea..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_ipc.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_IPC_H__ -#define __BL_IPC_H__ - -#include -typedef void(ipcIntCallback)(uint32_t src); -void ipc_m0_init(ipcIntCallback *onLPTriggerCallBack, ipcIntCallback *onD0TriggerCallBack); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.c deleted file mode 100644 index d9b3113c7f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.c +++ /dev/null @@ -1,418 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "clic.h" - -#include -#include "bl_irq.h" - -#ifdef SYS_ENABLE_COREDUMP -#include -#endif - -void CPU_Interrupt_Enable(uint32_t irq_num); -void CPU_Interrupt_Disable(uint32_t irq_num); -void bl_irq_enable(unsigned int source) -{ - CPU_Interrupt_Enable(source); - //*(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 1; -} - -void bl_irq_disable(unsigned int source) -{ - CPU_Interrupt_Disable(source); - //*(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIE + source) = 0; -} - -void bl_irq_pending_set(unsigned int source) -{ - *(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 1; -} - -void bl_irq_pending_clear(unsigned int source) -{ - *(volatile uint8_t*)(CLIC_HART0_ADDR + CLIC_INTIP + source) = 0; -} - -void bl_irq_exception_trigger(BL_IRQ_EXCEPTION_TYPE_T type, void *ptr) -{ - uint32_t val = 0x12345678;; - - switch (type) { - case BL_IRQ_EXCEPTION_TYPE_LOAD_MISALIGN: - { - val = *(uint32_t*)ptr; - } - break; - case BL_IRQ_EXCEPTION_TYPE_STORE_MISALIGN: - { - *(uint32_t*)ptr = val; - } - break; - case BL_IRQ_EXCEPTION_TYPE_ACCESS_ILLEGAL: - { - *(uint32_t*)ptr = val; - } - break; - case BL_IRQ_EXCEPTION_TYPE_ILLEGAL_INSTRUCTION: - { - uint32_t fun_val = 0; - typedef void (*ins_ptr_t)(void); - ins_ptr_t func = (ins_ptr_t)&fun_val; - - func(); - } - break; - default: - { - /*nothing here*/ - } - } - printf("Trigger exception val is %08lx\r\n", val); -} - -void bl_irq_default(void) -{ - while (1) { - /*dead loop*/ - } -} - -static void (*handler_list[2][16 + 64])(void) = { - -}; - - -static inline void _irq_num_check(int irqnum) -{ - if (irqnum < 0 || irqnum >= sizeof(handler_list[0])/sizeof(handler_list[0][0])) { - blog_error("illegal irqnum %d\r\n", irqnum); - while (1) { - /*Deap loop here, TODO ass blog_assert*/ - } - } -} - -void bl_irq_register_with_ctx(int irqnum, void *handler, void *ctx) -{ - _irq_num_check(irqnum); - if (handler_list[0][irqnum] && handler_list[0][irqnum] != handler) { - blog_warn("IRQ %d already registered with %p \r\n", - irqnum, - handler_list[0][irqnum] - ); - } - - if (handler == NULL) { - blog_error("handler is NULL pointer! \r\n"); - return; - } - - if (NULL == ctx) { - handler_list[0][irqnum] = handler; - handler_list[1][irqnum] = NULL; - } - else { - handler_list[0][irqnum] = handler; - handler_list[1][irqnum] = ctx; - } - - return; - -} - -void bl_irq_ctx_get(int irqnum, void **ctx) -{ - _irq_num_check(irqnum); - *ctx = handler_list[1][irqnum]; - - return; -} - -struct irq_ctx **bl_irq_ctx_list(int *num) -{ - *num = 16 + 64; - return (struct irq_ctx **)handler_list[1]; -} - -void bl_irq_ctx_count_cost(int irqnum, uint64_t cost) -{ - struct irq_ctx *ctx; - _irq_num_check(irqnum); - if(handler_list[0][irqnum] != NULL) { - ctx = (struct irq_ctx *)(handler_list[1][irqnum]); - ctx->irq_run_time += cost; - } -} - -//void Interrupt_Handler_Register(IRQn_Type irq,void * interruptFun); -void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun); -void bl_irq_register(int irqnum, void *handler) -{ - - Interrupt_Handler_Register(irqnum, handler); - //bl_irq_register_with_ctx(irqnum, handler, NULL); -} - -void bl_irq_unregister(int irqnum, void *handler) -{ -#if 0 - _irq_num_check(irqnum); - if (handler_list[0][irqnum] != handler) { - blog_warn("IRQ %d:%p Not match with registered %p\r\n", - irqnum, - handler, - handler_list[0][irqnum] - ); - } - handler_list[0][irqnum] = handler; -#endif -} - -void interrupt_entry(uint32_t mcause) -{ - void *handler = NULL; - mcause &= 0x7FFFFFF; - if (mcause < sizeof(handler_list[0])/sizeof(handler_list[0][0])) { - handler = handler_list[0][mcause]; - } - if (handler) { - if (handler_list[1][mcause]) { - ((void (*)(void *))handler)(handler_list[1][mcause]);//handler(ctx) - } - else { - ((void (*)(void))handler)(); - } - } else { - printf("Cannot handle mcause 0x%lx:%lu, adjust to externel(0x%lx:%lu)\r\n", - mcause, - mcause, - mcause - 16, - mcause - 16 - ); - while (1) { - /*dead loop now*/ - } - } -} - -static void __dump_exception_code_str(uint32_t code) -{ - printf("Exception code: %lu\r\n", code); - switch (code) { - case 0x00: - /*Instruction address misaligned*/ - { - puts(" msg: Instruction address misaligned\r\n"); - } - break; - case 0x01: - /*Instruction access fault*/ - { - puts(" msg: Instruction access fault\r\n"); - } - break; - case 0x02: - /*Illegal instruction*/ - { - puts(" msg: Illegal instruction\r\n"); - } - break; - case 0x03: - /*Breakpoint*/ - { - puts(" msg: Breakpoint\r\n"); - } - break; - case 0x04: - /*Load address misaligned*/ - { - puts(" msg: Load address misaligned\r\n"); - } - break; - case 0x05: - /*Load access fault*/ - { - puts(" msg: Load access fault\r\n"); - } - break; - case 0x06: - /*Store/AMO access misaligned*/ - { - puts(" msg: Store/AMO access misaligned\r\n"); - } - break; - case 0x07: - /*Store/AMO access fault*/ - { - puts(" msg: Store/AMO access fault\r\n"); - } - break; - case 0x08: - /*Environment call from U-mode*/ - { - puts(" msg: Environment call from U-mode\r\n"); - } - break; - case 0x09: - /*Environment call from S-mode*/ - { - puts(" msg: Environment call from S-mode\r\n"); - } - break; - case 0x0a: - case 0x0e: - /*Reserved*/ - { - puts(" msg: Reserved\r\n"); - } - break; - case 0x0b: - /*Environment call from M-mode*/ - { - puts(" msg: Environment call from M-mode\r\n"); - } - break; - case 0x0c: - /*Instruction page fault*/ - { - puts(" msg: Instruction page fault\r\n"); - } - break; - case 0x0d: - /*Load page fault*/ - { - puts(" msg: Load page fault\r\n"); - } - break; - case 0x0f: - /*Store/AMO page fault*/ - { - puts(" msg: Store/AMO page fault\r\n"); - } - break; - default:{ - puts(" msg: Reserved default exception\r\n"); - } - } -} - -extern void misaligned_load_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc); -extern void misaligned_store_trap(uintptr_t* regs, uintptr_t mcause, uintptr_t mepc); - -#define EXCPT_LOAD_MISALIGNED 4 -#define EXCPT_STORE_MISALIGNED 6 - -#ifdef DBG_RECORD_EXCEP_VAL -struct{ - uint32_t mcause; - uint32_t mepc; - uint32_t mtval; -}rval[4]; -int rval_idx; -#endif /* DBG_RECORD_EXCEP_VAL */ - -void exception_entry(uint32_t mcause, uint32_t mepc, uint32_t mtval, uintptr_t *regs) -{ -#ifdef DBG_RECORD_EXCEP_VAL - rval[rval_idx&0x3].mcause = mcause; - rval[rval_idx&0x3].mepc = mepc; - rval[rval_idx&0x3].mtval = mtval; - rval_idx++; -#endif /* DBG_RECORD_EXCEP_VAL */ - if ((mcause & 0x3ff) == EXCPT_LOAD_MISALIGNED) { - //misaligned_load_trap(regs, mcause, mepc); - } else if ((mcause & 0x3ff) == EXCPT_STORE_MISALIGNED){ - //misaligned_store_trap(regs, mcause, mepc); - } - { - //registerdump(tasksp); - puts("Exception Entry--->>>\r\n"); - blog_info("mcause %08lx, mepc %08lx, mtval %08lx\r\n", - mcause, - mepc, - mtval - ); - __dump_exception_code_str(mcause & 0xFFFF); - //backtrace_now_task((int (*)(const char *s))puts, regs); - while (1) { - /*Deap loop now*/ -#ifdef SYS_ENABLE_COREDUMP - /* For stack check */ - extern uintptr_t _sp_main, _sp_base; - - /* XXX change sp to irq stack base */ - __asm__ volatile("add sp, x0, %0" ::"r"(&_sp_main)); - bl_coredump_run(); -#endif - } - } -} - -int bl_irq_save(void) -{ - uint32_t oldstat; - - /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */ - __asm volatile("csrrc %0, mstatus, %1" : "=r"(oldstat) : "r"(8)); - return oldstat; -} - -void bl_irq_restore(int flags) -{ - __asm volatile("csrw mstatus, %0" - : /* no output */ - : "r"(flags)); -} -void bl_irq_init(void) -{ - uint32_t ptr; - - // puts("[IRQ] Clearing and Disable all the pending IRQ...\r\n"); - - /*clear mask*/ - for (ptr = 0x02800400; ptr < 0x02800400 + 128; ptr++) { - *(uint8_t*)ptr = 0; - } - /*clear pending*/ - for (ptr = 0x02800000; ptr < 0x02800000 + 128; ptr++) { - *(uint8_t*)ptr = 0; - } -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.h deleted file mode 100644 index a70b2733bc..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_irq.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_IRQ_H__ -#define __BL_IRQ_H__ -void bl_irq_enable(unsigned int source); -void bl_irq_disable(unsigned int source); -typedef enum { - BL_IRQ_EXCEPTION_TYPE_LOAD_MISALIGN, - BL_IRQ_EXCEPTION_TYPE_STORE_MISALIGN, - BL_IRQ_EXCEPTION_TYPE_ACCESS_ILLEGAL, - BL_IRQ_EXCEPTION_TYPE_ILLEGAL_INSTRUCTION, -} BL_IRQ_EXCEPTION_TYPE_T; - -struct irq_ctx { - char *name; - int irqnum; - uint64_t irq_run_time; -}; - -struct irq_ctx **bl_irq_ctx_list(int *num); -void bl_irq_exception_trigger(BL_IRQ_EXCEPTION_TYPE_T type, void *ptr); - -void bl_irq_init(void); -/*The following section define the IRQ handler for other files*/ -void bl_sec_aes_IRQHandler(void); -void bl_sec_sha_IRQHandler(void); -void bl_sec_pka_IRQHandler(void); -void bl_dma_IRQHandler(void); -void intc_irq(void);//MAC IRQ -void bl_irq_handler(void);//IPC host IRQ -void bl_irq_register_with_ctx(int irqnum, void *handler, void *ctx); -void bl_irq_register(int irqnum, void *handler); -void bl_irq_unregister(int irqnum, void *handler); -void bl_irq_ctx_get(int irqnum, void **ctx); - - -int bl_irq_save(void); -void bl_irq_restore(int flags); -void __attribute__((noreturn)) bl_sys_abort(const char *details); - -#define GLOBAL_IRQ_SAVE() if (1) { \ - int ____global_prev_mie_irq____ = bl_irq_save(); - -#define GLOBAL_IRQ_RESTORE() \ - bl_irq_restore(____global_prev_mie_irq____ ); \ -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.c deleted file mode 100644 index d02bd63c46..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.c +++ /dev/null @@ -1,272 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include "bl_mm_clock.h" -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -//TODO BL606P H FILE -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -static void get_mm_xclk(uint32_t reg_val) -{ - uint32_t cpu_pll_clk = 0; - cpu_pll_clk = BL_GET_REG_BITS_VAL(reg_val, MM_GLB_REG_XCLK_CLK_SEL); - - switch (cpu_pll_clk) { - case 0: - printf("XCLK select RC32M\r\n"); - break; - case 1: - printf("XCLK select XTAL\r\n"); - break; - default: - break; - } -} - -static void get_mm_cpu_pll_clk(uint32_t reg_val) -{ - uint32_t cpu_pll_clk = 0; - cpu_pll_clk = BL_GET_REG_BITS_VAL(reg_val, MM_GLB_REG_CPU_CLK_SEL); - - switch (cpu_pll_clk) { - case 0: - printf("MM CPU select 240Mhz\r\n"); - break; - case 1: - printf("MM CPU select 320Mhz\r\n"); - break; - case 2: - printf("MM CPU select 400Mhz\r\n"); - break; - default: - break; - } - -} - -static void dump_mm_cpu_clk(void) -{ - uint32_t tmpVal = 0, cpu_root_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - cpu_root_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL); - switch (cpu_root_clk) { - case 0: - printf("MM CPU select XCLK--->"); - get_mm_xclk(tmpVal); - break; - case 1: - printf("MM CPU select PLL--->"); - get_mm_cpu_pll_clk(tmpVal); - break; - default: - break; - } -} - -static void dump_mm_bus_clk(void) -{ - uint32_t tmpVal = 0, mm_bus_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_bus_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL); - - switch (mm_bus_clk) { - case 0: - printf("MM BUS CLK select XCLK--->"); - get_mm_xclk(tmpVal); - break; - case 2: - printf("MM BUS CLK select 160Mhz\r\n"); - break; - case 3: - printf("MM BUS CLK select 240Mhz\r\n"); - break; - default: - break; - } - -} - -static void dump_mm_xclk(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - get_mm_xclk(tmpVal); -} - -static void dump_mm_uart_clk(void) -{ - uint32_t tmpVal = 0, mm_uart_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_uart_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL); - - switch (mm_uart_clk) { - case 0: - printf("UART CLK select MM BUS CLK--->"); - dump_mm_bus_clk(); - break; - case 1: - printf("UART CLK select 160Mhz\r\n"); - break; - case 2: - case 3: - printf("UART CLK select MM XCLK--->"); - get_mm_xclk(tmpVal); - break; - default: - break; - } -} - -static void dump_mm_i2c_clk(void) -{ - uint32_t tmpVal = 0, mm_i2c_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_i2c_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL); - - switch (mm_i2c_clk) { - case 0: - printf("I2C CLK select MM BUS CLK--->"); - dump_mm_bus_clk(); - break; - case 1: - printf("I2C CLK select MM XCLK--->"); - get_mm_xclk(tmpVal); - break; - default: - break; - } -} - -static void dump_mm_spi_clk(void) -{ - uint32_t tmpVal = 0, mm_spi_clk = 0; - - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - mm_spi_clk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL); - - switch (mm_spi_clk) { - case 0: - printf("SPI CLK select 160Mhz\r\n"); - break; - case 1: - printf("SPI CLK select MM XCLK--->"); - get_mm_xclk(tmpVal); - break; - default: - break; - } -} - -void bl_mm_clk_dump(void) -{ - dump_mm_cpu_clk(); - dump_mm_uart_clk(); - dump_mm_i2c_clk(); - dump_mm_spi_clk(); - dump_mm_bus_clk(); - dump_mm_xclk(); -} - -void bl_mm_xclk_config(mm_xclk_type xclk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL, xclk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_bclk_config(mm_bclk_type bclk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, bclk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_cpu_root_clk_config(mm_cpu_root_clk_type cpu_root_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, cpu_root_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_cpu_clk_config(mm_cpu_clk_type cpu_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, cpu_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_spi_clk_config(mm_spi_clk_type spi_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL, spi_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_i2c_clk_config(mm_i2c_clk_type i2c_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, i2c_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - -void bl_mm_uart_clk_config(mm_uart_clk_type uart_clk_num) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uart_clk_num); - - BL_WR_REG(CLKRST_CTRL_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.h deleted file mode 100644 index ef8946c9f4..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_mm_clock.h +++ /dev/null @@ -1,86 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_MM_CLOCK__ -#define __BL_MM_CLOCK__ -/*MM XCLK select*/ -typedef enum { - XCLK_RC32M = 0, - XCLK_XTAL, -}mm_xclk_type; - -/*MM BCLK1x select*/ -typedef enum { - BCLK_XCLK = 0, - BCLK_MUXPLL_160M = 2, - BCLK_MUXPLL_240M = 3, -}mm_bclk_type; - -/*MM CPU PLL select*/ -typedef enum { - CPU_CLK_MUXPLL_240M = 0, - CPU_CLK_MUXPLL_320M, - CPU_CLK_MUXPLL_400M, -}mm_cpu_clk_type; - -/*MM CPU ROOT CLK select*/ -typedef enum { - CPU_ROOT_CLK_XCLK = 0, - CPU_ROOT_CLK_PLL, -}mm_cpu_root_clk_type; - -/*MM SPI CLK select*/ -typedef enum { - SPI_CLK_MUXPLL_160M = 0, - SPI_CLK_XCLK, -}mm_spi_clk_type; - -/*MM I2C CLK select*/ -typedef enum { - I2C_CLK_BCLK = 0, - I2C_CLK_XCLK, -}mm_i2c_clk_type; - -/*MM UART CLK select*/ -typedef enum { - UART_CLK_BCLK = 0, - UART_CLK_MUXPLL_160M, - UART_CLK_XCLK1, //2 or 3 all select MM XCLK - UART_CLK_XCLK2, -}mm_uart_clk_type; - -void bl_mm_clk_dump(void); -void bl_mm_xclk_config(mm_xclk_type xclk_num); -void bl_mm_bclk_config(mm_bclk_type bclk_num); -void bl_mm_cpu_clk_config(mm_cpu_clk_type cpu_clk_num); -void bl_mm_cpu_root_clk_config(mm_cpu_root_clk_type cpu_root_clk_num); -void bl_mm_spi_clk_config(mm_spi_clk_type spi_clk_num); -void bl_mm_i2c_clk_config(mm_i2c_clk_type i2c_clk_num); -void bl_mm_uart_clk_config(mm_uart_clk_type uart_clk_num); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.c deleted file mode 100644 index a9a1b0dfb5..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.c +++ /dev/null @@ -1,489 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include -#include -#include "bl_pm.h" -#include - -enum PM_STATE { - PM_STATE_INITED = 0, - PM_STATE_STOP, - PM_STATE_START, - PM_STATE_STOPPED, - PM_STATE_RUNNING, -}; - -union ps_cap { - uint32_t cap; - struct { - unsigned int uapsd_mode : 1; - unsigned int mac_idle : 1; - unsigned int ma_doze : 1; - unsigned int rf_onoff : 1; - unsigned int pti_pta_config : 1; - unsigned int force_sleep : 1; - } bits; -}; - -struct pm_env -{ - uint32_t level; - union ps_cap wlan_capacity; - union ps_cap bt_capacity; - enum PM_STATE state; - SemaphoreHandle_t pm_mux; - utils_dlist_t *pm_list; -}; - -struct pm_node -{ - utils_dlist_t dlist_item; - enum PM_EVEMT event; - uint32_t code; - uint16_t priority; - uint32_t cap_bit; - bl_pm_cb_t ops; - enum PM_EVENT_ABLE enable; - void *ctx; -}; - -static struct pm_env *gp_pm_env = NULL; - -static int pm_env_init(void) -{ - int i = 0; - - assert(!gp_pm_env); - - gp_pm_env = pvPortMalloc(sizeof(struct pm_env)); - assert(gp_pm_env); - - memset(gp_pm_env, 0, sizeof(struct pm_env)); - gp_pm_env->pm_list = pvPortMalloc(sizeof(utils_dlist_t) * PM_EVENT_MAX); - assert(gp_pm_env->pm_list); - - memset(gp_pm_env->pm_list, 0, sizeof(bl_pm_cb_t) * PM_EVENT_MAX); - - gp_pm_env->pm_mux = xSemaphoreCreateMutex(); - assert(gp_pm_env->pm_mux); - - for (i = 0; i < PM_EVENT_MAX; i++) { - INIT_UTILS_DLIST_HEAD(&(gp_pm_env->pm_list)[i]); - } - - gp_pm_env->state = PM_STATE_INITED; - - ///for debug - gp_pm_env->bt_capacity.cap = 0xffff; - - return 0; -} - -static void pm_node_delete(utils_dlist_t *queue) -{ - struct pm_node *node = NULL; - utils_dlist_t *tmp; - - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - xSemaphoreTake(gp_pm_env->pm_mux, portMAX_DELAY); - utils_dlist_del(&(node->dlist_item)); - vPortFree(node); - xSemaphoreGive(gp_pm_env->pm_mux); - } -} - -static int pm_deinit(void) -{ - int i = 0; - - assert(gp_pm_env); - - for (i = 0; i < PM_EVENT_MAX; i++) { - pm_node_delete(&(gp_pm_env->pm_list)[i]); - } - - vPortFree(gp_pm_env->pm_list); - gp_pm_env->pm_list = NULL; - - vSemaphoreDelete(gp_pm_env->pm_mux); - gp_pm_env->pm_mux = NULL; - - vPortFree(gp_pm_env); - gp_pm_env = NULL; - - return 0; -} - -static int pm_set_wlan_capacity(uint32_t capacity) -{ - assert(gp_pm_env); - - gp_pm_env->wlan_capacity.cap = capacity; - - return 0; -} - -static int pm_set_state(enum PM_STATE state) -{ - gp_pm_env->state = state; - - return 0; -} - -static enum PM_STATE pm_get_state(void) -{ - return gp_pm_env->state; -} - -static void pm_node_add(struct pm_node *pnode, utils_dlist_t *queue) -{ - struct pm_node *node = NULL; - utils_dlist_t *tmp; - utils_dlist_t *pre_save; - - pre_save = queue; - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - if (pnode->priority < node->priority) { - xSemaphoreTake(gp_pm_env->pm_mux, portMAX_DELAY); - utils_dlist_add(&(pnode->dlist_item), pre_save); - xSemaphoreGive(gp_pm_env->pm_mux); - break; - } - - pre_save = &(node->dlist_item); - } - - if (&(node->dlist_item) == queue) { - xSemaphoreTake(gp_pm_env->pm_mux, portMAX_DELAY); - utils_dlist_add_tail(&(pnode->dlist_item), queue); - xSemaphoreGive(gp_pm_env->pm_mux); - } -} - -static int pm_node_ops_exec(struct pm_node *node) -{ - if (node->ops == NULL) { - return 0; - } - - return node->ops(node->ctx); -} - -static int pm_state_exec_func_check(enum PM_EVEMT event, uint32_t code) -{ - int ret; - - if ((WLAN_PM_EVENT_CONTROL == event) || (PM_STATE_RUNNING == gp_pm_env->state)) { - ret = 0; - } else { - ret = 1; - } - - return ret; -} - -static int pm_pmlist_traverse(enum PM_EVEMT event, utils_dlist_t *queue, uint32_t code, uint32_t *retval) -{ - struct pm_node *node = NULL; - int ret = 0; - utils_dlist_t *tmp; - - if (retval) { - *retval = 0; - } - - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - if ((node->enable) && (code == node->code) && (gp_pm_env->wlan_capacity.cap & node->cap_bit) && - (gp_pm_env->bt_capacity.cap & node->cap_bit)) { - - if (pm_state_exec_func_check(event, code)) { - return -1; - } - - ret = pm_node_ops_exec(node); - if (ret && retval) { - *retval |= 1; - } - } - } - - return 0; -} - -static int pm_internal_process_event(enum PM_EVEMT event, uint32_t code) -{ - int ret = 0; - - switch (event) { - case WLAN_PM_EVENT_CONTROL: - { - switch (code) { - case WLAN_CODE_PM_NOTIFY_START: - { - if ((PM_STATE_INITED != pm_get_state()) && (PM_STATE_STOPPED != pm_get_state())) { - blog_error("pm not init or is running.\r\n"); - ret = -1; - - return ret; - } - pm_set_state(PM_STATE_START); - } - break; - - case WLAN_CODE_PM_NOTIFY_STOP: - { - if (PM_STATE_RUNNING != pm_get_state()) { - blog_error("pm is not running.\r\n"); - ret = -1; - - return ret; - } - - pm_set_state(PM_STATE_STOP); - } - break; - - default: - { - } - } - } - break; - - default: - { - - } - } - - return ret; -} - -int pm_post_event(enum PM_EVEMT event, uint32_t code, uint32_t *retval) -{ - if (!gp_pm_env) { - return -1; - } - - pm_pmlist_traverse(event, &(gp_pm_env->pm_list)[event], code, retval); - pm_internal_process_event(event, code); - - return 0; -} - -int bl_pm_event_register(enum PM_EVEMT event, uint32_t code, uint32_t cap_bit, uint16_t priority, bl_pm_cb_t ops, void *arg, enum PM_EVENT_ABLE enable) -{ - struct pm_node *p_node; - - if (!gp_pm_env) { - return -1; - } - - p_node = pvPortMalloc(sizeof(struct pm_node)); - assert(p_node); - - memset(p_node, 0, sizeof(struct pm_node)); - p_node->event = event; - p_node->code = code; - p_node->cap_bit = cap_bit; - p_node->priority = priority; - p_node->ops = ops; - p_node->ctx = arg; - p_node->enable = enable; - - pm_node_add(p_node, &(gp_pm_env->pm_list)[event]); - - return 0; -} - -int bl_pm_event_switch(enum PM_EVEMT event, uint32_t code, enum PM_EVENT_ABLE enable) -{ - struct pm_node *node = NULL; - utils_dlist_t *tmp; - utils_dlist_t *queue; - int ret = -1; - - if (!gp_pm_env) { - return -1; - } - - queue = &(gp_pm_env->pm_list)[event]; - - utils_dlist_for_each_entry_safe(queue, tmp, node, struct pm_node, dlist_item) { - if (code == node->code) { - node->enable = enable; - - ret = 0; - } - } - - return ret; -} - -int bl_pm_state_run(void) -{ - int ret = -1; - - if (!gp_pm_env) { - return -1; - } - - switch (gp_pm_env->state) { - case PM_STATE_INITED: - { - } - break; - - case PM_STATE_START: - { - pm_set_state(PM_STATE_RUNNING); - pm_post_event(WLAN_PM_EVENT_CONTROL, WLAN_CODE_PM_START, NULL);; - ret = 0; - } - break; - - case PM_STATE_STOP: - { - pm_set_state(PM_STATE_STOPPED); - pm_post_event(WLAN_PM_EVENT_CONTROL, WLAN_CODE_PM_STOP, NULL); - } - break; - - case PM_STATE_RUNNING: - { - ret = 0; - } - break; - - case PM_STATE_STOPPED: - { - } - break; - - default: - { - - } - } - - return ret; -} - -int bl_pm_capacity_set(enum PM_LEVEL level) -{ - uint32_t capacity = 0; - - switch (level) { - case PM_MODE_STA_NONE: - { - return -1; - } - break; - - case PM_MODE_STA_IDLE: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - } - break; - - case PM_MODE_STA_MESH: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_WLAN_BLE_ABORT; - capacity |= NODE_CAP_BIT_FORCE_SLEEP; - } - break; - - case PM_MODE_STA_DOZE: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - capacity |= NODE_CAP_BIT_RF_ONOFF; - capacity |= NODE_CAP_BIT_FORCE_SLEEP; - } - break; - - case PM_MODE_STA_COEX: - { - capacity |= NODE_CAP_BIT_UAPSD_MODE; - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - capacity |= NODE_CAP_BIT_RF_ONOFF; - capacity |= NODE_CAP_BIT_WLAN_BLE_ABORT; - } - break; - - case PM_MODE_STA_DOWN: - { - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - capacity |= NODE_CAP_BIT_RF_ONOFF; - } - break; - - case PM_MODE_AP_IDLE: - { - capacity |= NODE_CAP_BIT_MAC_IDLE; - capacity |= NODE_CAP_BIT_MAC_DOZE; - } - break; - - default: - { - return -1; - } - } - - pm_set_wlan_capacity(capacity); - - return 0; -} - -int bl_pm_init(void) -{ - pm_env_init(); - - return 0; -} - -int bl_pm_deinit(void) -{ - pm_deinit(); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.h deleted file mode 100644 index 174863be2c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_pm.h +++ /dev/null @@ -1,111 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_PM_H__ -#define __BL_PM_H__ -#include -#include - -#define NODE_CAP_BIT_UAPSD_MODE (1 << 0) -#define NODE_CAP_BIT_MAC_IDLE (1 << 1) -#define NODE_CAP_BIT_MAC_DOZE (1 << 2) -#define NODE_CAP_BIT_RF_ONOFF (1 << 3) -#define NODE_CAP_BIT_WLAN_BLE_ABORT (1 << 4) -#define NODE_CAP_BIT_FORCE_SLEEP (1 << 5) -#define NODE_CAP_BIT_ALL_ALLOWED (0xffff) - -enum PM_EVENT_ABLE { - PM_DISABLE = 0, - PM_ENABLE, -}; - -enum WLAN_CODE_SLEEP_CONTROL { - WLAN_CODE_PM_NOTIFY_START = 0, - WLAN_CODE_PM_NOTIFY_STOP, - WLAN_CODE_PM_START, - WLAN_CODE_PM_STOP, -}; - -enum WLAN_CODE_ENTER_SLEEP { - WLAN_CODE_PM_ENTER_SLEEP_PRE = 0, - WLAN_CODE_PM_ENTER_SLEEP, -}; - -enum WLAN_CODE_EXIT_SLEEP { - WLAN_CODE_PM_ENTER_SLEEP_PRE_FAILED = 0, - WLAN_CODE_PM_EXIT_SLEEP_PRE, - WLAN_CODE_PM_EXIT_SLEEP, -}; - -enum WLAN_CODE_BEACON_LOSS { - WLAN_CODE_BEACON_LOSS = 0, -}; - -enum WLAN_CODE_SEND_NULLDATA { - WLAN_CODE_PM_PAUSE = 0, - WLAN_CODE_PM_NULLDATA_NOACK, - WLAN_CODE_PM_NULLDATA_SEND_ERROR, -}; - -enum BLE_CODE_BLE_CONTROL { - BLE_CODE_PM_TURNON_RF = 0, - BLE_CODE_PM_TURNOFF_RF, -}; - -enum PM_LEVEL{ - PM_MODE_STA_NONE = 0, - PM_MODE_STA_IDLE, - PM_MODE_STA_MESH, - PM_MODE_STA_DOZE, - PM_MODE_STA_COEX, - PM_MODE_STA_DOWN, - PM_MODE_AP_IDLE, - PM_MODE_MAX, -}; - -enum PM_EVEMT{ - WLAN_PM_EVENT_CONTROL = 0, - WLAN_PM_EVENT_ENTER_SLEEP, - WLAN_PM_EVENT_EXIT_SLEEP, - WLAN_PM_EVENT_BEACON_LOSS, - WLAN_PM_EVENT_SEND_NULLDATA, - BLE_PM_EVENT_CONTROL, - PM_EVENT_MAX, -}; - -typedef int (*bl_pm_cb_t)(void *arg); - -int bl_pm_init(void); -int bl_pm_event_register(enum PM_EVEMT event, uint32_t code, uint32_t cap_bit, uint16_t pirority, bl_pm_cb_t ops, void *arg, enum PM_EVENT_ABLE enable); -int bl_pm_deinit(void); -int bl_pm_state_run(void); -int bl_pm_capacity_set(enum PM_LEVEL level); -int pm_post_event(enum PM_EVEMT event, uint32_t code, uint32_t *retval); -int bl_pm_event_switch(enum PM_EVEMT event, uint32_t code, enum PM_EVENT_ABLE enable); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.c deleted file mode 100644 index b922b5695a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_psram.h" -#ifdef BL808 -#include -#include - -int bl_psram_init(void) -{ - GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); - Psram_UHS_x16_Init(2000); - printf("Done. \r\nData @0x5000_0000 is %08lx\r\n", *(uint32_t*)0x50000000); - return 0; -} - -#elif defined(BL606P) -#include -int bl_psram_init(void) -{ - puts("--> dummy PSRAM init implemented\r\n"); - return 0; -} -#endif - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.h deleted file mode 100644 index 7120c15781..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_psram.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_PSRAM_H__ -#define __BL_PSRAM_H__ - -int bl_psram_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.c deleted file mode 100644 index 2ab832702c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.c +++ /dev/null @@ -1,1715 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "bl_sdh.h" - -#define SDH_CLK_PIN GLB_GPIO_PIN_0 -#define SDH_CMD_PIN GLB_GPIO_PIN_1 -#define SDH_DAT0_PIN GLB_GPIO_PIN_2 -#define SDH_DAT1_PIN GLB_GPIO_PIN_3 -#define SDH_DAT2_PIN GLB_GPIO_PIN_4 -#define SDH_DAT3_PIN GLB_GPIO_PIN_5 - -#define SDH_CLK_PIN_FUN GPIO_FUN_SDH -#define SDH_CMD_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT0_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT1_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT2_PIN_FUN GPIO_FUN_SDH -#define SDH_DAT3_PIN_FUN GPIO_FUN_SDH - - -#if SDIO_SDCARD_INT_MODE -#define SDH_SDCARD_IRQn SDH_IRQn -#endif - -/* Private variables ---------------------------------------------------------*/ - -static uint32_t sdhClockInit = 400000ul; -static uint32_t sdhClockSrc = 96000000ul; -static uint32_t sdhClockTransfer = 48000000ul; - -static sd_card_t *pSDCardInfo = NULL; -static SDH_Cfg_Type SDH_Cfg_Type_Instance; - -#if SDIO_SDCARD_INT_MODE -static volatile SD_Error SDH_DataWaitStatus = SD_WAITING; -static volatile SD_Error SDH_CMDWaitStatus = SD_WAITING; - -static SDH_Trans_Callback_Cfg_Type SDH_Trans_Callback_Cfg_TypeInstance; -static SDH_Handle_Cfg_Type SDH_Handle_Cfg_TypeInstance; -#endif - -static SDH_DMA_Cfg_Type SDH_DMA_Cfg_TypeInstance; -/*causion: ADMA related variables must on OCRAM or shared ram*/ -static __EALIGN(64) SDH_ADMA2_Desc_Type adma2Entries[32]; - -/* Private function prototypes -----------------------------------------------*/ -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid); -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd); -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr); -#if SDIO_SDCARD_INT_MODE -static void SDH_INT_Init(void); -#endif -static status_t SDH_SendCardCommand(SDH_CMD_Cfg_Type *cmd); -static void SDH_HostInit(void); -static status_t SDH_GoIdle(void); -static status_t SD_SendApplicationCmd(uint32_t relativeAddress); -static status_t SD_SendInterfaceCondition(void); -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument); -static status_t SD_AllSendCid(sd_card_t *card); -static status_t SD_SendRca(sd_card_t *card); -static status_t SD_SendCsd(sd_card_t *card); -static status_t SD_SelectCard(sd_card_t *card, BL_Fun_Type NewState); -static status_t SD_SendScr(sd_card_t *card); -static status_t SD_SendSsr(sd_card_t *card); -static status_t SD_SetDataBusWidth(sd_card_t *card, SDH_Data_Bus_Width_Type width); -static status_t SD_SwitchFunction(uint32_t mode, uint32_t group, uint32_t number, uint32_t status[16]); -static status_t SD_SelectFunction(uint32_t group, uint32_t function); -static status_t SD_SetBlockSize(uint32_t blockSize); -static status_t SDH_SDCardInit(uint32_t bus_wide, sd_card_t *card); -static status_t WaitInProgramming(void); -static status_t IsCardProgramming(uint8_t *pstatus); -static status_t SDH_CardTransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer); - -static void SD_DecodeCid(sd_card_t *card, uint32_t *rawCid) -{ - sd_cid_t *cid; - - cid = &(card->cid); - cid->manufacturerID = (uint8_t)((rawCid[3U] & 0xFF0000U) >> 16U); - cid->applicationID = (uint16_t)((rawCid[3U] & 0xFFFFU) >> 0U); - - cid->productName[0U] = (uint8_t)((rawCid[1U] & 0xFF000000U) >> 24); - cid->productName[1U] = (uint8_t)((rawCid[2U] & 0xFF) >> 0U); - cid->productName[2U] = (uint8_t)((rawCid[2U] & 0xFF00U) >> 8U); - cid->productName[3U] = (uint8_t)((rawCid[2U] & 0xFF0000U) >> 16U); - cid->productName[4U] = (uint8_t)((rawCid[2U] & 0xFF000000U) >> 24U); - - cid->productVersion = (uint8_t)((rawCid[1U] & 0xFF0000U) >> 16U); - - cid->productSerialNumber = (uint32_t)((rawCid[1U] & 0xFFFFU) << 16U); - cid->productSerialNumber |= (uint32_t)((rawCid[0U] & 0xFFFF0000U) >> 16U); - - cid->manufacturerData = (uint16_t)((rawCid[0U] & 0xFFFU) >> 0U); -} -static void SD_DecodeCsd(sd_card_t *card, uint32_t *rawCsd) -{ - sd_csd_t *csd; - - csd = &(card->csd); - csd->csdStructure = (uint8_t)((rawCsd[3U] & 0xC00000U) >> 22U); - csd->dataReadAccessTime1 = (uint8_t)((rawCsd[3U] & 0xFF00U) >> 8U); - csd->dataReadAccessTime2 = (uint8_t)((rawCsd[3U] & 0xFFU) >> 0U); - - csd->transferSpeed = (uint8_t)((rawCsd[2U] & 0xFF000000U) >> 24); - csd->cardCommandClass = (uint16_t)((rawCsd[2U] & 0xFFF000U) >> 12U); - csd->readBlockLength = (uint8_t)((rawCsd[2U] & 0xF00U) >> 8U); - - switch (csd->csdStructure) { - /*csd version 1.1*/ - case 0: - csd->deviceSize = (uint32_t)((rawCsd[2U] & 0x3U) << 10U); - csd->deviceSize |= (uint32_t)((rawCsd[1U] & 0xFFC00000U) >> 22U); - - csd->deviceSizeMultiplier = (uint8_t)((rawCsd[1U] & 0x380U) >> 7U); - - /* Get card total block count and block size. */ - card->blockCount = ((csd->deviceSize + 1U) << (csd->deviceSizeMultiplier + 2U)); - card->blockSize = (1U << (csd->readBlockLength)); - - if (card->blockSize != SDH_DEFAULT_BLOCK_SIZE) { - card->blockCount = (card->blockCount * card->blockSize); - card->blockSize = SDH_DEFAULT_BLOCK_SIZE; - card->blockCount = (card->blockCount / card->blockSize); - } - - break; - - /*csd version 2.0*/ - case 1: - card->blockSize = SDH_DEFAULT_BLOCK_SIZE; - csd->deviceSize = (uint32_t)((rawCsd[1U] & 0x3FFFFF00U) >> 8U); - - if (csd->deviceSize >= 0xFFFFU) { - card->flags |= SD_SupportSdxcFlag; - } - - card->blockCount = ((csd->deviceSize + 1U) * 1024U); - break; - - default: - break; - } -} -static void SD_DecodeScr(sd_card_t *card, uint32_t *rawScr) -{ - sd_scr_t *scr; - - scr = &(card->scr); - scr->scrStructure = (uint8_t)((rawScr[1U] & 0xF0000000U) >> 28U); - scr->sdSpecification = (uint8_t)((rawScr[1U] & 0xF000000U) >> 24U); - - if ((uint8_t)((rawScr[1U] & 0x800000U) >> 23U)) { - scr->flags |= SD_ScrDataStatusAfterErase; - } - - scr->sdSecurity = (uint8_t)((rawScr[1U] & 0x700000U) >> 20U); - scr->sdBusWidths = (uint8_t)((rawScr[1U] & 0xF0000U) >> 16U); - - if ((uint8_t)((rawScr[0U] & 0x8000U) >> 15U)) { - scr->flags |= SD_ScrSdSpecification3; - } - - scr->extendedSecurity = (uint8_t)((rawScr[1U] & 0x7800U) >> 10U); - scr->commandSupport = (uint8_t)(rawScr[1U] & 0x3U); - scr->reservedForManufacturer = rawScr[0U]; - - /* Get specification version. */ - switch (scr->sdSpecification) { - case 0U: - card->version = SD_SpecificationVersion1_0; - break; - - case 1U: - card->version = SD_SpecificationVersion1_1; - break; - - case 2U: - card->version = SD_SpecificationVersion2_0; - - if (card->scr.flags & SD_ScrSdSpecification3) { - card->version = SD_SpecificationVersion3_0; - } - - break; - - default: - break; - } - - if (card->scr.sdBusWidths & 0x4U) { - card->flags |= SD_Support4BitWidthFlag; - } - - /* speed class control cmd */ - if (card->scr.commandSupport & 0x01U) { - card->flags |= SD_SupportSpeedClassControlCmd; - } - - /* set block count cmd */ - if (card->scr.commandSupport & 0x02U) { - card->flags |= SD_SupportSetBlockCountCmd; - } -} - -#if SDIO_SDCARD_INT_MODE -/*!< SDH transfer complete callback */ -void SDH_DataTransferFinished_CallBack(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData) -{ - //bflb_platform_printf("Interrupt occurs! intFlag=0x%02lX,\r\n",handle->intFlag); - if (status != SDH_STAT_SUCCESS) { - SDH_DataWaitStatus = SD_DataCfg_ERROR; - } else { - SDH_DataWaitStatus = SD_OK; - } -} -/*!< SDH transfer complete callback */ -void SDH_CMDTransferFinished_CallBack(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData) -{ - //bflb_platform_printf("Interrupt occurs! intFlag=0x%02lX,\r\n",handle->intFlag); - if (status != SDH_STAT_SUCCESS) { - SDH_CMDWaitStatus = SD_CMD_ERROR; - } else { - SDH_CMDWaitStatus = SD_OK; - } -} - -/****************************************************************************/ /** - * @brief SDH INT init - * - * @param None - * - * @return None - * -*******************************************************************************/ -static void SDH_INT_Init(void) -{ - System_NVIC_SetPriority(SDH_SDCARD_IRQn, 7, 1); - CPU_Interrupt_Enable(SDH_SDCARD_IRQn); - - SDH_EnableIntStatus(SDH_INT_ALL); - SDH_DisableIntSource(SDH_INT_ALL); - SDH_Trans_Callback_Cfg_TypeInstance.SDH_CallBack_TransferFinished = SDH_DataTransferFinished_CallBack; - SDH_Trans_Callback_Cfg_TypeInstance.SDH_CMDCallBack_TransferFinished = SDH_CMDTransferFinished_CallBack; - SDH_InstallHandleCallback(&SDH_Handle_Cfg_TypeInstance, &SDH_Trans_Callback_Cfg_TypeInstance, NULL); -} -#endif - -static status_t SDH_SendCardCommand(SDH_CMD_Cfg_Type *cmd) -{ - status_t errorstatus = Status_Success; - SD_Error sd_status; - uint32_t time_node; - - SDH_ClearIntStatus(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - - SDH_SendCommand(cmd); - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_CMDWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_CMDWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH send CMD%ld timeout: %ld ms\r\n", cmd->index, (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - sd_status = SDH_CMDWaitStatus; - SDH_DisableIntSource(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS); - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_CMD_ERRORS) { - sd_status = SD_CMD_ERROR; - break; - - } else if (intFlag & SDH_INT_CMD_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH send CMD%ld timeout: %ld ms\r\n", cmd->index, (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - // SDH_MSG("SDH send CMD%ld used time : %ld\r\n", cmd->index, (uint32_t)SDH_GET_TIME() - time_node); - - if (sd_status != SD_OK) { - SDH_MSG("SDH send CMD%ld error\r\n", cmd->index); - errorstatus = Status_SDH_CmdResponseError; - } else { - SDH_GetCmdResp(cmd); - SDH_MSG("SDH send CMD%ld success\r\n", cmd->index); - } - - return errorstatus; -} - -static void SDH_GPIO_Init(uint32_t bus_wide) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t gpiofuns[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 2; - cfg.smtCtrl = 1; - - gpiopins[0] = SDH_CLK_PIN; - gpiopins[1] = SDH_CMD_PIN; - gpiopins[2] = SDH_DAT0_PIN; - gpiopins[3] = SDH_DAT1_PIN; - gpiopins[4] = SDH_DAT2_PIN; - gpiopins[5] = SDH_DAT3_PIN; - - gpiofuns[0] = SDH_CLK_PIN_FUN; - gpiofuns[1] = SDH_CMD_PIN_FUN; - gpiofuns[2] = SDH_DAT0_PIN_FUN; - gpiofuns[3] = SDH_DAT1_PIN_FUN; - gpiofuns[4] = SDH_DAT2_PIN_FUN; - gpiofuns[5] = SDH_DAT3_PIN_FUN; - switch (bus_wide) { - case SDH_DATA_BUS_WIDTH_1BIT: - for (i = 1; i < sizeof(gpiopins) - 3; i++) { - cfg.gpioPin = gpiopins[i]; - cfg.gpioFun = gpiofuns[i]; - GLB_GPIO_Init(&cfg); - } - break; - - case SDH_DATA_BUS_WIDTH_4BITS: - for (i = 1; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - cfg.gpioFun = gpiofuns[i]; - GLB_GPIO_Init(&cfg); - } - break; - - /*set 1bit as default*/ - default: - for (i = 1; i < sizeof(gpiopins) - 3; i++) { - cfg.gpioPin = gpiopins[i]; - cfg.gpioFun = gpiofuns[i]; - GLB_GPIO_Init(&cfg); - } - break; - } - - cfg.gpioPin = gpiopins[0]; - cfg.gpioFun = gpiofuns[0]; - cfg.pullType = GPIO_PULL_NONE; - GLB_GPIO_Init(&cfg); -} - -static void SDH_HostInit(void) -{ - /* initialise SDH controller*/ - SDH_Cfg_Type_Instance.vlot18Enable = DISABLE; - SDH_Cfg_Type_Instance.highSpeed = ENABLE; - SDH_Cfg_Type_Instance.dataWidth = SDH_DATA_BUS_WIDTH_1BIT; - SDH_Cfg_Type_Instance.volt = SDH_VOLTAGE_3P3V; - SDH_Cfg_Type_Instance.srcClock = sdhClockSrc; - SDH_Cfg_Type_Instance.busClock = sdhClockInit; - SDH_Ctrl_Init(&SDH_Cfg_Type_Instance); - - /*setup timeout counter*/ - SDH_Set_Timeout(0x0e); - - /*power on host controller*/ - SDH_Powon(); -} - -/* -* GO_IDLE_STATE, send card to reset state -*/ -static status_t SDH_GoIdle(void) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*CMD0: GO_IDLE_STATE, send card to reset state*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_GO_IDLE_STATE; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_NONE; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - return errorstatus; -} - -static status_t SD_SendApplicationCmd(uint32_t relativeAddress) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* send CMD55 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_APP_CMD; - SDH_CMD_Cfg_TypeInstance.argument = relativeAddress; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - return Status_SDH_CmdResponseError; - } - - return errorstatus; -} - -static status_t SD_SendInterfaceCondition(void) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* CMD8: SEND_IF_COND */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_HS_SEND_EXT_CSD; - SDH_CMD_Cfg_TypeInstance.argument = SD_CHECK_PATTERN; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R7; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - SDH_MSG("Response to CMD8 is: 0x%02lX.\r\n", SDH_CMD_Cfg_TypeInstance.response[0]); - - if ((SDH_CMD_Cfg_TypeInstance.response[0U] & 0xFFU) != (SD_CHECK_PATTERN & 0xff)) { - return Status_SDH_CardNotSupport; - } - - return errorstatus; -} - -static status_t SD_ApplicationSendOperationCondition(sd_card_t *card, uint32_t argument) -{ - status_t errorstatus = Status_Success; - uint32_t response = 0, count = 0, validvoltage = 0; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - do { - if (Status_Success != (errorstatus = SD_SendApplicationCmd(0))) { - return errorstatus; - } - - /*ACMD41*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_APP_OP_COND; - SDH_CMD_Cfg_TypeInstance.argument = argument; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R3; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - response = SDH_CMD_Cfg_TypeInstance.response[0]; - validvoltage = (((response >> 31) == 1) ? 1 : 0); - count++; - } while ((!validvoltage) && (count < SD_MAX_VOLT_TRIAL)); - - if (count == SD_MAX_VOLT_TRIAL) { - return Status_Timeout; - } else { - card->ocr = response; - - if (response &= SD_OcrHostCapacitySupportFlag) { - /* change from sdsc to sdhc */ - card->flags |= SD_SupportHighCapacityFlag; - } - } - - return errorstatus; -} -static status_t SD_AllSendCid(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* CMD2: SD_CMD_ALL_SEND_CID */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_ALL_SEND_CID; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R2; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - card->rawCid[0] = SDH_CMD_Cfg_TypeInstance.response[0]; - card->rawCid[1] = SDH_CMD_Cfg_TypeInstance.response[1]; - card->rawCid[2] = SDH_CMD_Cfg_TypeInstance.response[2]; - card->rawCid[3] = SDH_CMD_Cfg_TypeInstance.response[3]; - - SD_DecodeCid(card, card->rawCid); - - return errorstatus; -} - -static status_t SD_SendRca(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*CMD3: send relative card address*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SET_REL_ADDR; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R6; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - card->relativeAddress = SDH_CMD_Cfg_TypeInstance.response[0] >> 16; - - return errorstatus; -} - -static status_t SD_SendCsd(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*CMD9: send card-specific data(CSD)*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SEND_CSD; - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)((card->relativeAddress) << 16); - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R2; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_CmdResponseError; - } - - card->rawCsd[0] = SDH_CMD_Cfg_TypeInstance.response[0]; - card->rawCsd[1] = SDH_CMD_Cfg_TypeInstance.response[1]; - card->rawCsd[2] = SDH_CMD_Cfg_TypeInstance.response[2]; - card->rawCsd[3] = SDH_CMD_Cfg_TypeInstance.response[3]; - - SD_DecodeCsd(card, card->rawCsd); - - return errorstatus; -} - -static status_t SD_SelectCard(sd_card_t *card, BL_Fun_Type NewState) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* CMD7: select/deselect specified card */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SEL_DESEL_CARD; - - if (NewState == ENABLE) { - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)((card->relativeAddress) << 16); - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1B; - } else { - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_NONE; - } - - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - return Status_SDH_TransferFailed; - } else if ((NewState == ENABLE) && (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS)) { - return Status_SDH_CmdResponseError; - } - - return errorstatus; -} - -/* get CSR */ -static status_t SD_SendScr(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - SD_Error sd_status; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - uint32_t tempscr[2] = { 0, 0 }; - uint32_t time_node; - - /* send CMD55 */ - errorstatus = SD_SendApplicationCmd((uint32_t)((card->relativeAddress) << 16)); - - if (errorstatus != Status_Success) { - goto out; - } - - /*!< Set Block Size To 8 Bytes */ - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = 8; - SDH_Data_Cfg_TypeInstance.blockCount = 1; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = tempscr; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - /* Config the data transfer parameter */ - stat = SDH_ConfigDataTranfer(&SDH_Data_Cfg_TypeInstance); - - if (SDH_STAT_SUCCESS != stat) { - return Status_SDH_TransferFailed; - } - - /*!< Send ACMD51 SD_APP_SEND_SCR with argument as 0 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_APP_SEND_SCR; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* Waiting for CSR data */ - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("sdh get csr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_BUFFER_READ_READY || intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get csr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status == SD_OK) { - SDH_ReadDataPort(&SDH_Data_Cfg_TypeInstance); - card->rawScr[1] = ((tempscr[0] & SD_0TO7BITS) << 24) | ((tempscr[0] & SD_8TO15BITS) << 8) | ((tempscr[0] & SD_16TO23BITS) >> 8) | ((tempscr[0] & SD_24TO31BITS) >> 24); - card->rawScr[0] = ((tempscr[1] & SD_0TO7BITS) << 24) | ((tempscr[1] & SD_8TO15BITS) << 8) | ((tempscr[1] & SD_16TO23BITS) >> 8) | ((tempscr[1] & SD_24TO31BITS) >> 24); - SD_DecodeScr(card, card->rawScr); - SDH_MSG("SDH get csr success\r\n"); - } else { - errorstatus = Status_SDH_TransferFailed; - SDH_MSG("SDH get csr failed\r\n"); - goto out; - } - -out: - return errorstatus; -} - -/* get SSR */ -static status_t SD_SendSsr(sd_card_t *card) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - SD_Error sd_status; - uint32_t time_node; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - - errorstatus = SD_SendApplicationCmd((uint32_t)((card->relativeAddress) << 16)); - - if (errorstatus != Status_Success) { - goto out; - } - - /*!< Set Block Size To 512 Bytes */ - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = 64; - SDH_Data_Cfg_TypeInstance.blockCount = 1; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = card->rawSsr; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - /* Config the data transfer parameter */ - stat = SDH_ConfigDataTranfer(&SDH_Data_Cfg_TypeInstance); - - if (SDH_STAT_SUCCESS != stat) { - return Status_SDH_TransferFailed; - } - - /*!< Send ACMD13 SD_APP_SEND_SCR with argument as 0 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_APP_STAUS; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* Waiting for SSR data */ - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get ssr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_BUFFER_READ_READY || intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get ssr data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status == SD_OK) { - SDH_ReadDataPort(&SDH_Data_Cfg_TypeInstance); - SDH_MSG("SDH get ssr success\r\n"); - } else { - errorstatus = Status_SDH_TransferFailed; - SDH_MSG("SDH get ssr failed\r\n"); - goto out; - } - -out: - return errorstatus; -} - -/* Set Data Bus Width */ -static status_t SD_SetDataBusWidth(sd_card_t *card, SDH_Data_Bus_Width_Type width) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - if (width == SDH_DATA_BUS_WIDTH_1BIT) { - SDH_CMD_Cfg_TypeInstance.argument = 0; - } else if (width == SDH_DATA_BUS_WIDTH_4BITS) { - SDH_CMD_Cfg_TypeInstance.argument = 2; - } else { - return Status_InvalidArgument; - } - - errorstatus = SD_SendApplicationCmd((uint32_t)((card->relativeAddress) << 16)); - - if (errorstatus != Status_Success) { - goto out; - } - - /*!< Send ACMD6 APP_CMD with argument as 2 for wide bus mode */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_APP_SD_SET_BUSWIDTH; - - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* reinitialise SDH controller*/ - SDH_Cfg_Type_Instance.vlot18Enable = DISABLE; - SDH_Cfg_Type_Instance.highSpeed = ENABLE; - SDH_Cfg_Type_Instance.dataWidth = width; - SDH_Cfg_Type_Instance.volt = SDH_VOLTAGE_3P3V; - SDH_Cfg_Type_Instance.srcClock = sdhClockSrc; - SDH_Cfg_Type_Instance.busClock = sdhClockTransfer; - SDH_Ctrl_Init(&SDH_Cfg_Type_Instance); - -out: - return errorstatus; -} - -/* switch function - mode: 0 check function, 1 set function - group: group number,1~6 - number: - */ -static status_t SD_SwitchFunction(uint32_t mode, uint32_t group, uint32_t number, uint32_t status[16]) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - SD_Error sd_status; - uint32_t time_node; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - - /*!< Set Block Size To 64 Bytes */ - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = 64; - SDH_Data_Cfg_TypeInstance.blockCount = 1; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = status; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - /* Config the data transfer parameter */ - stat = SDH_ConfigDataTranfer(&SDH_Data_Cfg_TypeInstance); - - if (SDH_STAT_SUCCESS != stat) { - return Status_SDH_TransferFailed; - } - - /*!< Send CMD6 SD_CMD_HS_SWITCH with argument as 0 */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_HS_SWITCH; - SDH_CMD_Cfg_TypeInstance.argument = (mode << 31U | 0x00FFFFFFU); - SDH_CMD_Cfg_TypeInstance.argument &= ~((uint32_t)(0xFU) << (group * 4U)); - SDH_CMD_Cfg_TypeInstance.argument |= (number << (group * 4U)); - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /* Waiting for CSR data */ - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get CMD6 status data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_BUFFER_READ_READY || intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH get CMD6 status data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status == SD_OK) { - SDH_ReadDataPort(&SDH_Data_Cfg_TypeInstance); - SDH_MSG("SDH get CMD6 status data success\r\n"); - } else { - errorstatus = Status_SDH_TransferFailed; - SDH_MSG("SDH get CMD6 status data failed\r\n"); - goto out; - } - -out: - return errorstatus; -} - -/* */ -static ATTR_USED status_t SD_SelectFunction(uint32_t group, uint32_t function) -{ - status_t errorstatus = Status_Success; - uint32_t cmd6Status[16] = { 0 }; - uint16_t functionGroupInfo[6U] = { 0 }; - uint32_t currentFunctionStatus = 0U; - - uint32_t i; - - /* Check if card support high speed mode. */ - if (Status_Success != SD_SwitchFunction(SDH_SwitchCheck, group, function, cmd6Status)) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - for (i = 0; i < 16; i++) { - SDH_MSG("cmd6Status[%ld]=0x%lX.\r\n", i, cmd6Status[i]); - } - - /* In little endian mode, SD bus byte transferred first is the byte stored in lowest byte position in - a word which will cause 4 byte's sequence in a word is not consistent with their original sequence from - card. So the sequence of 4 bytes received in a word should be converted. */ - cmd6Status[0U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[0U]); - cmd6Status[1U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[1U]); - cmd6Status[2U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[2U]); - cmd6Status[3U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[3U]); - cmd6Status[4U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[4U]); - - functionGroupInfo[5U] = (uint16_t)cmd6Status[0U]; - functionGroupInfo[4U] = (uint16_t)(cmd6Status[1U] >> 16U); - functionGroupInfo[3U] = (uint16_t)(cmd6Status[1U]); - functionGroupInfo[2U] = (uint16_t)(cmd6Status[2U] >> 16U); - functionGroupInfo[1U] = (uint16_t)(cmd6Status[2U]); - functionGroupInfo[0U] = (uint16_t)(cmd6Status[3U] >> 16U); - currentFunctionStatus = ((cmd6Status[3U] & 0xFFFFU) << 8U) | (cmd6Status[4U] >> 24U); - - for (i = 0; i < 6; i++) { - SDH_MSG("functionGroupInfo[%ld]=0x%X.\r\n", i, functionGroupInfo[i]); - } - - SDH_MSG("currentFunctionStatus = 0x%lX.\r\n", currentFunctionStatus); - - /* check if function is support */ - if (((functionGroupInfo[group] & (1 << function)) == 0U) || - ((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - /* Check if card support high speed mode. */ - if (Status_Success != SD_SwitchFunction(SDH_SwitchSet, group, function, cmd6Status)) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - /* In little endian mode is little endian, SD bus byte transferred first is the byte stored in lowest byte - position in a word which will cause 4 byte's sequence in a word is not consistent with their original - sequence from card. So the sequence of 4 bytes received in a word should be converted. */ - cmd6Status[3U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[3U]); - cmd6Status[4U] = SWAP_WORD_BYTE_SEQUENCE(cmd6Status[4U]); - - /* According to the "switch function status[bits 511~0]" return by switch command in mode "set function": - -check if group 1 is successfully changed to function 1 by checking if bits 379~376 equal value 1; - */ - currentFunctionStatus = ((cmd6Status[3U] & 0xFFFFU) << 8U) | (cmd6Status[4U] >> 24U); - SDH_MSG("currentFunctionStatus = 0x%lX.\r\n", currentFunctionStatus); - - if (((currentFunctionStatus >> (group * 4U)) & 0xFU) != function) { - return Status_SDH_SDIO_SwitchHighSpeedFail; - } - - return errorstatus; -} - -static status_t SD_SetBlockSize(uint32_t blockSize) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*!< Set Block Size for SDSC Card,cmd16,no impact on SDHC card */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SET_BLOCKLEN; - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)blockSize; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - -out: - return errorstatus; -} - -static status_t SDH_SDCardInit(uint32_t bus_wide, sd_card_t *card) -{ - status_t errorstatus = Status_Success; - uint32_t applicationCommand41Argument = SD_OcrVdd33_34Flag | SD_OcrVdd32_33Flag; - - /* reset variables */ - card->flags = 0U; - - SDH_MSG("SD CARD GO IDEL...\r\n"); - errorstatus = SDH_GoIdle(); - - if (errorstatus != SD_OK) { - return Status_SDH_GoIdleFailed; - } - - SDH_MSG("SD CARD GO IDEL END\r\n"); - - for (uint16_t i = 0; i < 4; i++) { - /* send CMD8 */ - errorstatus = SD_SendInterfaceCondition(); - /* check response */ - if (errorstatus == Status_Success) { - /* SDHC or SDXC card */ - applicationCommand41Argument |= SD_OcrHostCapacitySupportFlag; - card->flags |= SD_SupportSdhcFlag; - break; - } else { - /* Try sending CMD8 again */ - SDH_MSG("Try sending CMD8 again:%d\r\n", i + 1); - errorstatus = SDH_GoIdle(); - if (errorstatus != Status_Success) { - return Status_SDH_GoIdleFailed; - } - } - } - - /* Set card interface condition according to SDHC capability and card's supported interface condition. */ - errorstatus = SD_ApplicationSendOperationCondition(card, applicationCommand41Argument); - - if (errorstatus != Status_Success) { - return Status_SDH_SendApplicationCommandFailed; - } - - SDH_MSG("\r\nOCR is: 0x%02lX.\r\n", card->ocr); - SDH_MSG("\t SDHC supported[%s].\r\n\r\n", ((card->flags & SD_SupportHighCapacityFlag) ? "YES" : "NO")); - - errorstatus = SD_AllSendCid(card); - - if (errorstatus != Status_Success) { - return Status_SDH_AllSendCidFailed; - } - - SDH_MSG("\r\nCID is: 0x%02lX-0x%02lX-0x%02lX-0x%02lX.\r\n", - card->rawCid[0], card->rawCid[1], card->rawCid[2], card->rawCid[3]); - SDH_MSG("\t manufacturerID is: 0x%02X.\r\n", card->cid.manufacturerID); - SDH_MSG("\t applicationID is: %c%c.\r\n", (card->cid.applicationID) >> 8, card->cid.applicationID); - SDH_MSG("\t productName is: %c%c%c%c%c.\r\n", - card->cid.productName[0], card->cid.productName[1], card->cid.productName[2], card->cid.productName[3], card->cid.productName[4]); - SDH_MSG("\t manufacturerData is: 0x%02X.\r\n\r\n", card->cid.manufacturerData); - - errorstatus = SD_SendRca(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendRelativeAddressFailed; - } - - SDH_MSG("\r\nRCA is: 0x%02lX.\r\n\r\n", card->relativeAddress); - - errorstatus = SD_SendCsd(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendCsdFailed; - } - - SDH_MSG("\r\nCSD is: 0x%02lX-0x%02lX-0x%02lX-0x%02lX.\r\n", - card->rawCsd[0], card->rawCsd[1], card->rawCsd[2], card->rawCsd[3]); - SDH_MSG("\t CSD Version is: %s .\r\n", card->csd.csdStructure ? "csd version 2.0" : "csd version 1.0"); - SDH_MSG("\t blockLen=%ld, blockCounter=%ld, CardSize is %ld[MBytes].\r\n\r\n", card->blockSize, card->blockCount, (card->blockCount) >> 11); - - errorstatus = SD_SelectCard(card, ENABLE); - - if (errorstatus != Status_Success) { - return Status_SDH_SelectCardFailed; - } - - errorstatus = SD_SendScr(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendScrFailed; - } - - SDH_MSG("\r\nSCR is: 0x%lX-0x%lX.\r\n", card->rawScr[0], card->rawScr[1]); - SDH_MSG("\t SD Spec Version is: [0x%02lX]%s.\r\n", card->version, - (card->version & SD_SpecificationVersion3_0) ? "V3.0" : ((card->version & SD_SpecificationVersion2_0) ? "V2.0" : ((card->version & SD_SpecificationVersion1_1) ? "V1.1" : "V1.0"))); - SDH_MSG("\t Erased bit is %d.\r\n", (card->scr.flags & SD_ScrDataStatusAfterErase)); - SDH_MSG("\t 4-line supported[%s].\r\n", ((card->flags & SD_Support4BitWidthFlag) ? "YES" : "NO")); - SDH_MSG("\t SetBlockCountCmd supported[%s].\r\n", ((card->flags & SD_SupportSetBlockCountCmd) ? "YES" : "NO")); - SDH_MSG("\t SDXC supported[%s].\r\n\r\n", ((card->flags & SD_SupportSdxcFlag) ? "YES" : "NO")); - - if (card->flags & SD_Support4BitWidthFlag) { - errorstatus = SD_SetDataBusWidth(card, (SDH_Data_Bus_Width_Type)bus_wide); - } else { - errorstatus = SD_SetDataBusWidth(card, SDH_DATA_BUS_WIDTH_1BIT); - } - - if (errorstatus != Status_Success) { - return Status_SDH_SetDataBusWidthFailed; - } - - errorstatus = SD_SendSsr(card); - - if (errorstatus != Status_Success) { - return Status_SDH_SendSsrFailed; - } - - SDH_MSG("\r\nSSR[0] is: 0x%lX.\r\n", card->rawSsr[0]); - SDH_MSG("\t Current is %d-line mode.\r\n\r\n", (card->rawSsr[0] & 0x80) ? 4 : 1); - - errorstatus = SD_SetBlockSize(SDH_DEFAULT_BLOCK_SIZE); - - if (errorstatus != Status_Success) { - return Status_SDH_SetCardBlockSizeFailed; - } - - //SD_SelectFunction(SDH_GroupTimingMode,SDH_TimingSDR25HighSpeedMode); - - return errorstatus; -} - -/** - * @brief Initializes SD Card clock. - * @retval SD status - */ -status_t SDH_ClockSet(uint32_t clockInit, uint32_t clockSrc, uint32_t clockTransfer) -{ - sdhClockInit = clockInit; - sdhClockSrc = clockSrc; - sdhClockTransfer = clockTransfer; - - return Status_Success; -} - -/** - * @brief Initializes the SD card device. - * @retval SD status - */ -status_t SDH_Init(uint32_t bus_wide, sd_card_t *pOutCardInfo) -{ - pSDCardInfo = pOutCardInfo; - - /* gpio init */ - SDH_GPIO_Init(bus_wide); - - /* config sdh clock */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SDH); - GLB_Set_SDH_CLK(1, GLB_SDH_CLK_WIFIPLL_96M, 0); - SDH_ClockSet(400000, 96000000, 96000000); - -#if SDIO_SDCARD_INT_MODE - SDH_INT_Init(); -#endif - - /* reset SDH controller*/ - SDH_Reset(); - - SDH_HostInit(); - - if (pOutCardInfo == NULL) { - return Status_InvalidArgument; - } else { - return SDH_SDCardInit(bus_wide, pOutCardInfo); - } -} - -/** - * @brief Allows to erase memory area specified for the given card. - * @param startaddr: the start address. - * @param endaddr: the end address. - * @retval SD_Error: SD Card Error code. - */ -status_t SD_Erase(uint32_t startaddr, uint32_t endaddr) -{ - status_t errorstatus = Status_Success; - uint8_t cardstate = 0; - - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /* SDSC card uses byte unit address*/ - if (!(pSDCardInfo->flags & SD_SupportHighCapacityFlag)) { - startaddr *= 512; - endaddr *= 512; - } - - /*!< Send CMD32 SD_ERASE_GRP_START with argument as addr */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_ERASE_GRP_START; - SDH_CMD_Cfg_TypeInstance.argument = startaddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Send CMD33 SD_ERASE_GRP_END with argument as addr */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SD_ERASE_GRP_END; - SDH_CMD_Cfg_TypeInstance.argument = endaddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Send CMD38 ERASE */ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_ERASE; - SDH_CMD_Cfg_TypeInstance.argument = 0; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1B; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Wait till the card is in programming state */ - errorstatus = IsCardProgramming(&cardstate); - - while ((errorstatus == SD_OK) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) { - errorstatus = IsCardProgramming(&cardstate); - } - -out: - return errorstatus; -} - -static status_t WaitInProgramming(void) -{ - uint8_t cardstate = 0; - status_t errorstatus = Status_Success; - //uint32_t maxdelay = 0; - //maxdelay = 120000/(sdhClockSrc/sdhClockTransfer); - - //while(maxdelay--){} - /*!< Wait till the card is in programming state */ - errorstatus = IsCardProgramming(&cardstate); - - while ((errorstatus == Status_Success) && ((SD_CARD_PROGRAMMING == cardstate) || (SD_CARD_RECEIVING == cardstate))) { - errorstatus = IsCardProgramming(&cardstate); - } - - return errorstatus; -} - -/*check sd card state*/ -static status_t IsCardProgramming(uint8_t *pstatus) -{ - status_t errorstatus = Status_Success; - SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - - /*cmd13 addressed card send its status*/ - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_SEND_STATUS; - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)(pSDCardInfo->relativeAddress) << 16; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_NONE; - - errorstatus = SDH_SendCardCommand(&SDH_CMD_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - goto out; - } else if (SDH_CMD_Cfg_TypeInstance.response[0] & SD_CSR_ERRORBITS) { - errorstatus = Status_SDH_CmdResponseError; - goto out; - } - - /*!< Find out card status */ - *pstatus = (uint8_t)((SDH_CMD_Cfg_TypeInstance.response[0] >> 9) & 0x0000000F); //status[12:9] :cardstate - -out: - return (errorstatus); -} - -/* Transmit data in non-blocking mode, Only the sending status of commands is checked */ -static status_t SDH_CardTransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer) -{ - status_t errorstatus = Status_Success; - SDH_Stat_Type stat = SDH_STAT_SUCCESS; - - stat = SDH_TransferNonBlocking(dmaCfg, transfer); - - if (stat != SDH_STAT_SUCCESS) { - return Status_SDH_TransferFailed; - } - - /* Flush ADMA2-descriptor-table to RAM, Otherwise ADMA2 will fail */ - L1C_DCache_Clean_By_Addr((uintptr_t)(dmaCfg->admaEntries), dmaCfg->maxEntries * sizeof(SDH_ADMA2_Desc_Type)); - - errorstatus = SDH_SendCardCommand(transfer->cmdCfg); - - if (errorstatus != Status_Success) { - return errorstatus; - } else if (transfer->cmdCfg->response[0] & SD_CSR_ERRORBITS) { - return Status_SDH_CmdResponseError; - } - - return errorstatus; -} - -status_t SDH_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - status_t errorstatus = Status_Success; - SD_Error sd_status; - uint32_t time_node; - - static SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - static SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - static SDH_Trans_Cfg_Type SDH_Trans_Cfg_TypeInstance = { &SDH_Data_Cfg_TypeInstance, &SDH_CMD_Cfg_TypeInstance }; - -#if defined(BL808) || defined(BL606P) - /* BL808/BL606 supports only 8-byte aligned addresses */ - if ((uintptr_t)readbuff % 8 != 0) { - return Status_InvalidArgument; - } -#endif - - /* SDSC card uses byte unit address*/ - if (!(pSDCardInfo->flags & SD_SupportHighCapacityFlag)) { - BlockSize = 512; - ReadAddr *= 512; - } - - SDH_MSG("\r\nRead-->IN, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, ReadAddr, readbuff); - - /*set cmd parameter for READ_MULTIPLE_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_READ_SINGLE_BLOCK; - } else { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_READ_MULT_BLOCK; - } - - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)ReadAddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - /*set data parameter for READ_MULTIPLE_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - if (pSDCardInfo->flags & SD_SupportSetBlockCountCmd) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = ENABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = ENABLE; - } - } - - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = BlockSize; - SDH_Data_Cfg_TypeInstance.blockCount = NumberOfBlocks; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = (uint32_t *)readbuff; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = NULL; - - /*set parameters for SDH_DMA_Cfg_TypeInstance*/ - SDH_DMA_Cfg_TypeInstance.dmaMode = SDH_DMA_MODE_ADMA2; - SDH_DMA_Cfg_TypeInstance.burstSize = SDH_BURST_SIZE_64_BYTES; - SDH_DMA_Cfg_TypeInstance.fifoThreshold = SDH_FIFO_THRESHOLD_256_BYTES; - SDH_DMA_Cfg_TypeInstance.admaEntries = (uint32_t *)adma2Entries; - SDH_DMA_Cfg_TypeInstance.maxEntries = sizeof(adma2Entries) / sizeof(adma2Entries[0]); - - L1C_DCache_Clean_By_Addr((uintptr_t)(readbuff), 0); - L1C_DCache_Clean_By_Addr((uintptr_t)(readbuff) + BlockSize * NumberOfBlocks, 0); - L1C_DCache_Invalid_By_Addr((uintptr_t)(readbuff), BlockSize * NumberOfBlocks); - - errorstatus = SDH_CardTransferNonBlocking(&SDH_DMA_Cfg_TypeInstance, &SDH_Trans_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - SDH_MSG("SDH Transfer err:%ld\r\n", errorstatus); - goto out; - } - - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH read data timeout: %ld", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - sd_status = SDH_DataWaitStatus; - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR || intFlag & SDH_INT_AUTO_CMD12_ERROR) { - sd_status = SD_CMD_ERROR; - break; - - } else if (intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH read data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status != SD_OK) { - errorstatus = Status_SDH_TransferFailed; - goto out; - } - - SDH_MSG("Read data used time: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_MSG("Read-->OUT, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, ReadAddr, readbuff); - -out: - return (errorstatus); -} - -status_t SDH_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks) -{ - status_t errorstatus = Status_Success; - SD_Error sd_status; - uint32_t time_node; - - static SDH_CMD_Cfg_Type SDH_CMD_Cfg_TypeInstance; - static SDH_Data_Cfg_Type SDH_Data_Cfg_TypeInstance; - static SDH_Trans_Cfg_Type SDH_Trans_Cfg_TypeInstance = { &SDH_Data_Cfg_TypeInstance, &SDH_CMD_Cfg_TypeInstance }; - -#if defined(BL808) || defined(BL606P) - /* BL808/BL606 supports only 8-byte aligned addresses */ - if ((uintptr_t)writebuff % 8 != 0) { - return Status_InvalidArgument; - } -#endif - - if ((pSDCardInfo != NULL) && (!(pSDCardInfo->flags & SD_SupportHighCapacityFlag))) { - /* It's SDCS card,SDSC card uses byte unit address*/ - BlockSize = 512; - WriteAddr *= 512; - } - - SDH_MSG("\r\nWrite-->IN, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, WriteAddr, writebuff); - - /*set cmd parameter for SD_CMD_WRITE_MULT_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_WRITE_SINGLE_BLOCK; - } else { - SDH_CMD_Cfg_TypeInstance.index = SD_CMD_WRITE_MULT_BLOCK; - } - - SDH_CMD_Cfg_TypeInstance.argument = (uint32_t)WriteAddr; - SDH_CMD_Cfg_TypeInstance.type = SDH_CMD_NORMAL; - SDH_CMD_Cfg_TypeInstance.respType = SDH_RESP_R1; - SDH_CMD_Cfg_TypeInstance.flag = SDH_TRANS_FLAG_DATA_PRESENT; - - /*set data parameter for WRITE_MULTIPLE_BLOCK*/ - if (NumberOfBlocks <= 1) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - if (pSDCardInfo->flags & SD_SupportSetBlockCountCmd) { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = ENABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = DISABLE; - } else { - SDH_Data_Cfg_TypeInstance.enableAutoCommand23 = DISABLE; - SDH_Data_Cfg_TypeInstance.enableAutoCommand12 = ENABLE; - } - } - - SDH_Data_Cfg_TypeInstance.enableIgnoreError = DISABLE; - SDH_Data_Cfg_TypeInstance.dataType = SDH_TRANS_DATA_NORMAL; - SDH_Data_Cfg_TypeInstance.blockSize = BlockSize; - SDH_Data_Cfg_TypeInstance.blockCount = NumberOfBlocks; - SDH_Data_Cfg_TypeInstance.rxDataLen = 0; - SDH_Data_Cfg_TypeInstance.rxData = NULL; - SDH_Data_Cfg_TypeInstance.txDataLen = 0; - SDH_Data_Cfg_TypeInstance.txData = (uint32_t *)writebuff; - /*set parameters for SDH_DMA_Cfg_TypeInstance*/ - SDH_DMA_Cfg_TypeInstance.dmaMode = SDH_DMA_MODE_ADMA2; - SDH_DMA_Cfg_TypeInstance.burstSize = SDH_BURST_SIZE_64_BYTES; - SDH_DMA_Cfg_TypeInstance.fifoThreshold = SDH_FIFO_THRESHOLD_256_BYTES; - SDH_DMA_Cfg_TypeInstance.admaEntries = (uint32_t *)adma2Entries; - SDH_DMA_Cfg_TypeInstance.maxEntries = sizeof(adma2Entries) / sizeof(adma2Entries[0]); - - L1C_DCache_Clean_By_Addr((uintptr_t)(writebuff), BlockSize * NumberOfBlocks); - - errorstatus = SDH_CardTransferNonBlocking(&SDH_DMA_Cfg_TypeInstance, &SDH_Trans_Cfg_TypeInstance); - - if (errorstatus != Status_Success) { - SDH_MSG("SDH Transfer err:%ld\r\n", errorstatus); - return errorstatus; - } - - time_node = (uint32_t)SDH_GET_TIME(); - -#if SDIO_SDCARD_INT_MODE - - SDH_DataWaitStatus = SD_WAITING; - SDH_EnableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - - /*wait for Xfer status. might pending here in multi-task OS*/ - while (SDH_DataWaitStatus == SD_WAITING) { - if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH write data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - errorstatus = Status_Timeout; - goto out; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - - SDH_DisableIntSource(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR | SDH_INT_AUTO_CMD12_ERROR); - sd_status = SDH_DataWaitStatus; - -#else - - uint32_t intFlag; - while (1) { - intFlag = SDH_GetIntStatus(); - if (intFlag & SDH_INT_DATA_ERRORS || intFlag & SDH_INT_DMA_ERROR || intFlag & SDH_INT_AUTO_CMD12_ERROR) { - sd_status = SD_DataCfg_ERROR; - break; - - } else if (intFlag & SDH_INT_DATA_COMPLETED) { - sd_status = SD_OK; - break; - - } else if ((uint32_t)SDH_GET_TIME() - time_node > SDIO_CMDTIMEOUT_MS) { - SDH_MSG("SDH write data timeout: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - return Status_Timeout; - } - BL_DRV_DUMMY; - BL_DRV_DUMMY; - } - SDH_ClearIntStatus(intFlag); - -#endif - - if (sd_status != SD_OK) { - errorstatus = Status_SDH_TransferFailed; - goto out; - } else { - errorstatus = WaitInProgramming(); - } - - SDH_MSG("Write data used time: %ld ms\r\n", (uint32_t)SDH_GET_TIME() - time_node); - SDH_MSG("Write-->OUT, block num: %ld, block addr: %ld, read buffer addr: 0x%p.\r\n", NumberOfBlocks, WriteAddr, writebuff); - -out: - return (errorstatus); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.h deleted file mode 100644 index ccb4772ea3..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sdh.h +++ /dev/null @@ -1,516 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __SDIO_SDCARD_H -#define __SDIO_SDCARD_H -#include "bl808_common.h" -#include "bl808_glb.h" -#include "bl808_sdh.h" - -#define SDIO_CMDTIMEOUT_MS (100) /* time out */ -#define SDH_GET_TIME() (0) /* get time */ -#define SDIO_SDCARD_INT_MODE (0) /* Interrupt mode, which can be paired with the OS */ -#define SDH_DEBUG 0 /* debug printf */ - -/*! @brief Reverse byte sequence in uint32_t */ -#define SWAP_WORD_BYTE_SEQUENCE(x) (__REV(x)) -#define __OCRAM __attribute__ ((section (".system_ram"))) -#define __EALIGN(x) __attribute((aligned (x))) - -/*! @brief Default block size */ -#define SDH_DEFAULT_BLOCK_SIZE (512U) - -typedef enum { - SD_OK = 0, - SD_CMD_ERROR, - SD_DataCfg_ERROR, - SD_WAITING, -} SD_Error; - -/*! @brief Type used for all status and error return values. */ -typedef int32_t status_t; -/*! @brief Construct a status code value from a group and code number. */ -#define MAKE_STATUS(group, code) ((((group)*100) + (code))) - -/*! @brief Status group numbers. */ -enum _status_groups { - StatusGroup_Generic = 0, /*!< Group number for generic status codes. */ - StatusGroup_SDH = 1, /*!< Group number for SDHC status code */ -}; - -/*! @brief Generic status return codes. */ -enum _generic_status { - Status_Success = MAKE_STATUS(StatusGroup_Generic, 0), - Status_Fail = MAKE_STATUS(StatusGroup_Generic, 1), - Status_OutOfRange = MAKE_STATUS(StatusGroup_Generic, 2), - Status_InvalidArgument = MAKE_STATUS(StatusGroup_Generic, 3), - Status_Timeout = MAKE_STATUS(StatusGroup_Generic, 4), - -}; -/*! @brief SD/MMC card API's running status. */ -enum _sdmmc_status { - Status_SDH_NotSupportYet = MAKE_STATUS(StatusGroup_SDH, 0U), /*!< Haven't supported */ - Status_SDH_TransferFailed = MAKE_STATUS(StatusGroup_SDH, 1U), /*!< Send command failed */ - Status_SDH_SetCardBlockSizeFailed = MAKE_STATUS(StatusGroup_SDH, 2U), /*!< Set block size failed */ - Status_SDH_HostNotSupport = MAKE_STATUS(StatusGroup_SDH, 3U), /*!< Host doesn't support */ - Status_SDH_CardNotSupport = MAKE_STATUS(StatusGroup_SDH, 4U), /*!< Card doesn't support */ - Status_SDH_AllSendCidFailed = MAKE_STATUS(StatusGroup_SDH, 5U), /*!< Send CID failed */ - Status_SDH_SendRelativeAddressFailed = MAKE_STATUS(StatusGroup_SDH, 6U), /*!< Send relative address failed */ - Status_SDH_SendCsdFailed = MAKE_STATUS(StatusGroup_SDH, 7U), /*!< Send CSD failed */ - Status_SDH_SelectCardFailed = MAKE_STATUS(StatusGroup_SDH, 8U), /*!< Select card failed */ - Status_SDH_SendScrFailed = MAKE_STATUS(StatusGroup_SDH, 9U), /*!< Send SCR failed */ - Status_SDH_SetDataBusWidthFailed = MAKE_STATUS(StatusGroup_SDH, 10U), /*!< Set bus width failed */ - Status_SDH_GoIdleFailed = MAKE_STATUS(StatusGroup_SDH, 11U), /*!< Go idle failed */ - Status_SDH_HandShakeOperationConditionFailed = MAKE_STATUS(StatusGroup_SDH, 12U), /*!< Send Operation Condition failed */ - Status_SDH_SendApplicationCommandFailed = MAKE_STATUS(StatusGroup_SDH, 13U), /*!< Send application command failed */ - Status_SDH_SwitchFailed = MAKE_STATUS(StatusGroup_SDH, 14U), /*!< Switch command failed */ - Status_SDH_StopTransmissionFailed = MAKE_STATUS(StatusGroup_SDH, 15U), /*!< Stop transmission failed */ - Status_SDH_WaitWriteCompleteFailed = MAKE_STATUS(StatusGroup_SDH, 16U), /*!< Wait write complete failed */ - Status_SDH_SetBlockCountFailed = MAKE_STATUS(StatusGroup_SDH, 17U), /*!< Set block count failed */ - Status_SDH_SetRelativeAddressFailed = MAKE_STATUS(StatusGroup_SDH, 18U), /*!< Set relative address failed */ - Status_SDH_SwitchBusTimingFailed = MAKE_STATUS(StatusGroup_SDH, 19U), /*!< Switch high speed failed */ - Status_SDH_SendExtendedCsdFailed = MAKE_STATUS(StatusGroup_SDH, 20U), /*!< Send EXT_CSD failed */ - Status_SDH_ConfigureBootFailed = MAKE_STATUS(StatusGroup_SDH, 21U), /*!< Configure boot failed */ - Status_SDH_ConfigureExtendedCsdFailed = MAKE_STATUS(StatusGroup_SDH, 22U), /*!< Configure EXT_CSD failed */ - Status_SDH_EnableHighCapacityEraseFailed = MAKE_STATUS(StatusGroup_SDH, 23U), /*!< Enable high capacity erase failed */ - Status_SDH_SendTestPatternFailed = MAKE_STATUS(StatusGroup_SDH, 24U), /*!< Send test pattern failed */ - Status_SDH_ReceiveTestPatternFailed = MAKE_STATUS(StatusGroup_SDH, 25U), /*!< Receive test pattern failed */ - Status_SDH_SDIO_ResponseError = MAKE_STATUS(StatusGroup_SDH, 26U), /*!< sdio response error */ - Status_SDH_SDIO_InvalidArgument = MAKE_STATUS(StatusGroup_SDH, 27U), /*!< sdio invalid argument response error */ - Status_SDH_SDIO_SendOperationConditionFail = MAKE_STATUS(StatusGroup_SDH, 28U), /*!< sdio send operation condition fail */ - Status_SDH_InvalidVoltage = MAKE_STATUS(StatusGroup_SDH, 29U), /*!< invaild voltage */ - Status_SDH_SDIO_SwitchHighSpeedFail = MAKE_STATUS(StatusGroup_SDH, 30U), /*!< switch to high speed fail */ - Status_SDH_SDIO_ReadCISFail = MAKE_STATUS(StatusGroup_SDH, 31U), /*!< read CIS fail */ - Status_SDH_SDIO_InvalidCard = MAKE_STATUS(StatusGroup_SDH, 32U), /*!< invaild SDIO card */ - Status_SDH_TuningFail = MAKE_STATUS(StatusGroup_SDH, 33U), /*!< tuning fail */ - Status_SDH_SwitchVoltageFail = MAKE_STATUS(StatusGroup_SDH, 34U), /*!< switch voltage fail*/ - Status_SDH_ReTuningRequest = MAKE_STATUS(StatusGroup_SDH, 35U), /*!< retuning request */ - Status_SDH_SetDriverStrengthFail = MAKE_STATUS(StatusGroup_SDH, 36U), /*!< set driver strength fail */ - Status_SDH_SetPowerClassFail = MAKE_STATUS(StatusGroup_SDH, 37U), /*!< set power class fail */ - Status_SDH_HostNotReady = MAKE_STATUS(StatusGroup_SDH, 38U), /*!< host controller not ready */ - Status_SDH_CardDetectFailed = MAKE_STATUS(StatusGroup_SDH, 39U), /*!< card detect failed */ - Status_SDH_CmdResponseError = MAKE_STATUS(StatusGroup_SDH, 40U), /*!< cmd response timeout */ - Status_SDH_SendSsrFailed = MAKE_STATUS(StatusGroup_SDH, 41U), /*!< Send SSR failed */ -}; -/** - * @brief SDIO Transfer state - */ -typedef enum { - SD_TRANSFER_OK = 0, - SD_TRANSFER_BUSY = 1, - SD_TRANSFER_ERROR -} SDTransferState; - -/** - * @brief SD Card States - */ -typedef enum { - SD_CARD_READY = ((uint32_t)0x00000001), - SD_CARD_IDENTIFICATION = ((uint32_t)0x00000002), - SD_CARD_STANDBY = ((uint32_t)0x00000003), - SD_CARD_TRANSFER = ((uint32_t)0x00000004), - SD_CARD_SENDING = ((uint32_t)0x00000005), - SD_CARD_RECEIVING = ((uint32_t)0x00000006), - SD_CARD_PROGRAMMING = ((uint32_t)0x00000007), - SD_CARD_DISCONNECTED = ((uint32_t)0x00000008), - SD_CARD_ERROR = ((uint32_t)0x000000FF) -} SDCardState; - -/** - * @brief Card Specific Data: CSD Register - */ -typedef struct -{ - uint8_t CSDStruct; /*!< CSD structure */ - uint8_t SysSpecVersion; /*!< System specification version */ - uint8_t Reserved1; /*!< Reserved */ - uint8_t TAAC; /*!< Data read access-time 1 */ - uint8_t NSAC; /*!< Data read access-time 2 in CLK cycles */ - uint8_t MaxBusClkFrec; /*!< Max. bus clock frequency */ - uint16_t CardComdClasses; /*!< Card command classes */ - uint8_t RdBlockLen; /*!< Max. read data block length */ - uint8_t PartBlockRead; /*!< Partial blocks for read allowed */ - uint8_t WrBlockMisalign; /*!< Write block misalignment */ - uint8_t RdBlockMisalign; /*!< Read block misalignment */ - uint8_t DSRImpl; /*!< DSR implemented */ - uint8_t Reserved2; /*!< Reserved */ - uint32_t DeviceSize; /*!< Device Size */ - uint8_t MaxRdCurrentVDDMin; /*!< Max. read current @ VDD min */ - uint8_t MaxRdCurrentVDDMax; /*!< Max. read current @ VDD max */ - uint8_t MaxWrCurrentVDDMin; /*!< Max. write current @ VDD min */ - uint8_t MaxWrCurrentVDDMax; /*!< Max. write current @ VDD max */ - uint8_t DeviceSizeMul; /*!< Device size multiplier */ - uint8_t EraseGrSize; /*!< Erase group size */ - uint8_t EraseGrMul; /*!< Erase group size multiplier */ - uint8_t WrProtectGrSize; /*!< Write protect group size */ - uint8_t WrProtectGrEnable; /*!< Write protect group enable */ - uint8_t ManDeflECC; /*!< Manufacturer default ECC */ - uint8_t WrSpeedFact; /*!< Write speed factor */ - uint8_t MaxWrBlockLen; /*!< Max. write data block length */ - uint8_t WriteBlockPaPartial; /*!< Partial blocks for write allowed */ - uint8_t Reserved3; /*!< Reserded */ - uint8_t ContentProtectAppli; /*!< Content protection application */ - uint8_t FileFormatGrouop; /*!< File format group */ - uint8_t CopyFlag; /*!< Copy flag (OTP) */ - uint8_t PermWrProtect; /*!< Permanent write protection */ - uint8_t TempWrProtect; /*!< Temporary write protection */ - uint8_t FileFormat; /*!< File Format */ - uint8_t ECC; /*!< ECC code */ -} SD_CSD; - -/** - * @brief Card Identification Data: CID Register - */ -typedef struct -{ - uint8_t ManufacturerID; /*!< ManufacturerID */ - uint8_t OEM_AppliID[3]; /*!< OEM/Application ID end with 0 for str display*/ - uint8_t ProdName[6]; /*!< Product Name part1 end with 0 for str display*/ - uint8_t ProdRev; /*!< Product Revision */ - uint32_t ProdSN; /*!< Product Serial Number */ - uint8_t month; /*!< Reserved1 */ - uint32_t year; /*!< Manufacturing Date */ -} SD_CID; - -/** - * @brief SD Card Status - */ -typedef struct -{ - uint8_t DAT_BUS_WIDTH; - uint8_t SECURED_MODE; - uint16_t SD_CARD_TYPE; - uint32_t SIZE_OF_PROTECTED_AREA; - uint8_t SPEED_CLASS; - uint8_t PERFORMANCE_MOVE; - uint8_t AU_SIZE; - uint16_t ERASE_SIZE; - uint8_t ERASE_TIMEOUT; - uint8_t ERASE_OFFSET; -} SD_CardStatus; - -/******************************************************************************* - * Definitions - ******************************************************************************/ -/*! @brief OCR register in SD card */ -enum _sd_ocr_flag { - - SD_OcrHostCapacitySupportFlag = (1U << 30U), /*!< Card capacity status */ - SD_OcrCardCapacitySupportFlag = SD_OcrHostCapacitySupportFlag, /*!< Card capacity status */ - SD_OcrSwitch18RequestFlag = (1U << 24U), /*!< Switch to 1.8V request */ - SD_OcrSwitch18AcceptFlag = SD_OcrSwitch18RequestFlag, /*!< Switch to 1.8V accepted */ - SD_OcrVdd27_28Flag = (1U << 15U), /*!< VDD 2.7-2.8 */ - SD_OcrVdd28_29Flag = (1U << 16U), /*!< VDD 2.8-2.9 */ - SD_OcrVdd29_30Flag = (1U << 17U), /*!< VDD 2.9-3.0 */ - SD_OcrVdd30_31Flag = (1U << 18U), /*!< VDD 2.9-3.0 */ - SD_OcrVdd31_32Flag = (1U << 19U), /*!< VDD 3.0-3.1 */ - SD_OcrVdd32_33Flag = (1U << 20U), /*!< VDD 3.1-3.2 */ - SD_OcrVdd33_34Flag = (1U << 21U), /*!< VDD 3.2-3.3 */ - SD_OcrVdd34_35Flag = (1U << 22U), /*!< VDD 3.3-3.4 */ - SD_OcrVdd35_36Flag = (1U << 23U), /*!< VDD 3.4-3.5 */ -}; -/*! @brief SD card flags */ -enum _sd_card_flag { - SD_SupportHighCapacityFlag = (1U << 1U), /*!< Support high capacity */ - SD_Support4BitWidthFlag = (1U << 2U), /*!< Support 4-bit data width */ - SD_SupportSdhcFlag = (1U << 3U), /*!< Card is SDHC */ - SD_SupportSdxcFlag = (1U << 4U), /*!< Card is SDXC */ - SD_SupportVoltage180v = (1U << 5U), /*!< card support 1.8v voltage*/ - SD_SupportSetBlockCountCmd = (1U << 6U), /*!< card support cmd23 flag*/ - SD_SupportSpeedClassControlCmd = (1U << 7U), /*!< card support speed class control flag */ -}; -/*! @brief SD card CID register */ -typedef struct _sd_cid { - uint8_t manufacturerID; /*!< Manufacturer ID [127:120] */ - uint16_t applicationID; /*!< OEM/Application ID [119:104] */ - uint8_t productName[5]; /*!< Product name [103:64] */ - uint8_t productVersion; /*!< Product revision [63:56] */ - uint32_t productSerialNumber; /*!< Product serial number [55:24] */ - uint16_t manufacturerData; /*!< Manufacturing date [19:8] */ -} sd_cid_t; - -/*! @brief SD card SCR register flags */ -enum _sd_scr_flag { - SD_ScrDataStatusAfterErase = (1U << 0U), /*!< Data status after erases [55:55] */ - SD_ScrSdSpecification3 = (1U << 1U), /*!< Specification version 3.00 or higher [47:47]*/ -}; -/*! @brief SD card CSD register */ -typedef struct _sd_csd { - uint8_t csdStructure; /*!< CSD structure [127:126] */ - uint8_t dataReadAccessTime1; /*!< Data read access-time-1 [119:112] */ - uint8_t dataReadAccessTime2; /*!< Data read access-time-2 in clock cycles (NSAC*100) [111:104] */ - uint8_t transferSpeed; /*!< Maximum data transfer rate [103:96] */ - uint16_t cardCommandClass; /*!< Card command classes [95:84] */ - uint8_t readBlockLength; /*!< Maximum read data block length [83:80] */ - uint16_t flags; /*!< Flags in _sd_csd_flag */ - uint32_t deviceSize; /*!< Device size [73:62] */ - /* Following fields from 'readCurrentVddMin' to 'deviceSizeMultiplier' exist in CSD version 1 */ - uint8_t readCurrentVddMin; /*!< Maximum read current at VDD min [61:59] */ - uint8_t readCurrentVddMax; /*!< Maximum read current at VDD max [58:56] */ - uint8_t writeCurrentVddMin; /*!< Maximum write current at VDD min [55:53] */ - uint8_t writeCurrentVddMax; /*!< Maximum write current at VDD max [52:50] */ - uint8_t deviceSizeMultiplier; /*!< Device size multiplier [49:47] */ - - uint8_t eraseSectorSize; /*!< Erase sector size [45:39] */ - uint8_t writeProtectGroupSize; /*!< Write protect group size [38:32] */ - uint8_t writeSpeedFactor; /*!< Write speed factor [28:26] */ - uint8_t writeBlockLength; /*!< Maximum write data block length [25:22] */ - uint8_t fileFormat; /*!< File format [11:10] */ -} sd_csd_t; -/*! @brief SD card SCR register */ -typedef struct _sd_scr { - uint8_t scrStructure; /*!< SCR Structure [63:60] */ - uint8_t sdSpecification; /*!< SD memory card specification version [59:56] */ - uint16_t flags; /*!< SCR flags in _sd_scr_flag */ - uint8_t sdSecurity; /*!< Security specification supported [54:52] */ - uint8_t sdBusWidths; /*!< Data bus widths supported [51:48] */ - uint8_t extendedSecurity; /*!< Extended security support [46:43] */ - uint8_t commandSupport; /*!< Command support bits [33:32] 33-support CMD23, 32-support cmd20*/ - uint32_t reservedForManufacturer; /*!< reserved for manufacturer usage [31:0] */ -} sd_scr_t; -/*! @brief SD Status register */ -typedef struct _sd_ssr { - uint8_t dataBusWidth; /*!< Data Bus Width [511:510] 0b00--1line, 0b10--4line*/ - uint8_t secureMode; /*!< Secure Mode [509] */ - uint16_t SDCardType; /*!< SD Card Type [495:480] */ - uint32_t sizeOfProtectedArea; /*!< Size Of Protected area [479:448] */ - uint8_t speedClass; /*!< speed classes [447:440] */ - uint8_t performanceMove; /*!< performance move [439:432] */ - uint8_t AUSize; /*!< AU size [431:428] */ - - uint16_t eraseSize; /*!< erase size [423:408] */ - uint8_t eraseTimeOut; /*!< erase timeout [407:402] */ - uint8_t eraseOffset; /*!< erase offset [401:400] */ - uint8_t UHSSpeedGrade; /*!< UHS speed grade [399:396] */ - uint8_t UHSAUSize; /*!< UHS AU size [395:392] */ -} sd_ssr_t; -/*! - * @brief SD card state - * - * Define the card structure including the necessary fields to identify and describe the card. - */ -typedef struct _sd_card { - uint32_t relativeAddress; /*!< Relative address of the card */ - uint32_t version; /*!< Card version */ - uint32_t flags; /*!< Flags in _sd_card_flag */ - uint32_t rawCid[4U]; /*!< Raw CID content */ - uint32_t rawCsd[4U]; /*!< Raw CSD content */ - uint32_t rawScr[2U]; /*!< Raw CSD content */ - uint32_t rawSsr[16U]; /*!< Raw CSD content */ - uint32_t ocr; /*!< Raw OCR content */ - sd_cid_t cid; /*!< CID */ - sd_csd_t csd; /*!< CSD */ - sd_scr_t scr; /*!< SCR */ - sd_ssr_t ssr; /*!< SCR */ - uint32_t blockCount; /*!< Card total block number */ - uint32_t blockSize; /*!< Card block size */ -} sd_card_t; -/** - * @brief SDIO Commands Index - */ -#define SD_CMD_GO_IDLE_STATE ((uint8_t)0) -#define SD_CMD_SEND_OP_COND ((uint8_t)1) -#define SD_CMD_ALL_SEND_CID ((uint8_t)2) -#define SD_CMD_SET_REL_ADDR ((uint8_t)3) /*!< SDIO_SEND_REL_ADDR for SD Card */ -#define SD_CMD_SET_DSR ((uint8_t)4) -#define SD_CMD_SDIO_SEN_OP_COND ((uint8_t)5) -#define SD_CMD_HS_SWITCH ((uint8_t)6) -#define SD_CMD_SEL_DESEL_CARD ((uint8_t)7) -#define SD_CMD_HS_SEND_EXT_CSD ((uint8_t)8) -#define SDIO_SEND_IF_COND ((uint8_t)8) -#define SD_CMD_SEND_CSD ((uint8_t)9) -#define SD_CMD_SEND_CID ((uint8_t)10) -#define SD_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11) /*!< SD Card doesn't support it */ -#define SD_CMD_STOP_TRANSMISSION ((uint8_t)12) -#define SD_CMD_SEND_STATUS ((uint8_t)13) -#define SD_CMD_HS_BUSTEST_READ ((uint8_t)14) -#define SD_CMD_GO_INACTIVE_STATE ((uint8_t)15) -#define SD_CMD_SET_BLOCKLEN ((uint8_t)16) -#define SD_CMD_READ_SINGLE_BLOCK ((uint8_t)17) -#define SD_CMD_READ_MULT_BLOCK ((uint8_t)18) -#define SD_CMD_HS_BUSTEST_WRITE ((uint8_t)19) -#define SD_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20) /*!< SD Card doesn't support it */ -#define SD_CMD_SET_BLOCK_COUNT ((uint8_t)23) /*!< SD Card doesn't support it */ -#define SD_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24) -#define SD_CMD_WRITE_MULT_BLOCK ((uint8_t)25) -#define SD_CMD_PROG_CID ((uint8_t)26) /*!< reserved for manufacturers */ -#define SD_CMD_PROG_CSD ((uint8_t)27) -#define SD_CMD_SET_WRITE_PROT ((uint8_t)28) -#define SD_CMD_CLR_WRITE_PROT ((uint8_t)29) -#define SD_CMD_SEND_WRITE_PROT ((uint8_t)30) -#define SD_CMD_SD_ERASE_GRP_START ((uint8_t)32) /*!< To set the address of the first write - block to be erased. (For SD card only) */ -#define SD_CMD_SD_ERASE_GRP_END ((uint8_t)33) /*!< To set the address of the last write block of the - continuous range to be erased. (For SD card only) */ -#define SD_CMD_ERASE_GRP_START ((uint8_t)35) /*!< To set the address of the first write block to be erased. - (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE_GRP_END ((uint8_t)36) /*!< To set the address of the last write block of the - continuous range to be erased. (For MMC card only spec 3.31) */ - -#define SD_CMD_ERASE ((uint8_t)38) -#define SD_CMD_FAST_IO ((uint8_t)39) /*!< SD Card doesn't support it */ -#define SD_CMD_GO_IRQ_STATE ((uint8_t)40) /*!< SD Card doesn't support it */ -#define SD_CMD_LOCK_UNLOCK ((uint8_t)42) -#define SD_CMD_APP_CMD ((uint8_t)55) -#define SD_CMD_GEN_CMD ((uint8_t)56) -#define SD_CMD_NO_CMD ((uint8_t)64) - -/** - * @brief Following commands are SD Card Specific commands. - * SDIO_APP_CMD :CMD55 should be sent before sending these commands. - */ -#define SD_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6) /*!< For SD Card only */ -#define SD_CMD_SD_APP_STAUS ((uint8_t)13) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22) /*!< For SD Card only */ -#define SD_CMD_SD_APP_OP_COND ((uint8_t)41) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SEND_SCR ((uint8_t)51) /*!< For SD Card only */ -#define SD_CMD_SDIO_RW_DIRECT ((uint8_t)52) /*!< For SD I/O Card only */ -#define SD_CMD_SDIO_RW_EXTENDED ((uint8_t)53) /*!< For SD I/O Card only */ - -/** - * @brief Following commands are SD Card Specific security commands. - * SDIO_APP_CMD should be sent before sending these commands. - */ -#define SD_CMD_SD_APP_GET_MKB ((uint8_t)43) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_MID ((uint8_t)44) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47) /*!< For SD Card only */ -#define SD_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_ERASE ((uint8_t)38) /*!< For SD Card only */ -#define SD_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49) /*!< For SD Card only */ -#define SD_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48) /*!< For SD Card only */ - -/** - * @brief Mask for errors Card Status R1 (CSR Register) - */ -#define SD_CSR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000) -#define SD_CSR_ADDR_MISALIGNED ((uint32_t)0x40000000) -#define SD_CSR_BLOCK_LEN_ERR ((uint32_t)0x20000000) -#define SD_CSR_ERASE_SEQ_ERR ((uint32_t)0x10000000) -#define SD_CSR_BAD_ERASE_PARAM ((uint32_t)0x08000000) -#define SD_CSR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000) -#define SD_CSR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000) -#define SD_CSR_COM_CRC_FAILED ((uint32_t)0x00800000) -#define SD_CSR_ILLEGAL_CMD ((uint32_t)0x00400000) -#define SD_CSR_CARD_ECC_FAILED ((uint32_t)0x00200000) -#define SD_CSR_CC_ERROR ((uint32_t)0x00100000) -#define SD_CSR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000) -#define SD_CSR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000) -#define SD_CSR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000) -#define SD_CSR_CID_CSD_OVERWRIETE ((uint32_t)0x00010000) -#define SD_CSR_WP_ERASE_SKIP ((uint32_t)0x00008000) -#define SD_CSR_CARD_ECC_DISABLED ((uint32_t)0x00004000) -#define SD_CSR_ERASE_RESET ((uint32_t)0x00002000) -#define SD_CSR_AKE_SEQ_ERROR ((uint32_t)0x00000008) -#define SD_CSR_ERRORBITS ((uint32_t)0xFDFFE008) - -#define SD_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFF) -#define SD_ALLZERO ((uint32_t)0x00000000) - -#define SD_WIDE_BUS_SUPPORT ((uint32_t)0x00040000) -#define SD_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000) -#define SD_CARD_LOCKED ((uint32_t)0x02000000) - -#define SD_0TO7BITS ((uint32_t)0x000000FF) -#define SD_8TO15BITS ((uint32_t)0x0000FF00) -#define SD_16TO23BITS ((uint32_t)0x00FF0000) -#define SD_24TO31BITS ((uint32_t)0xFF000000) -#define SD_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFF) -/** - * @brief Masks for R7 Response - */ -#define SD_VOLTAGE_WINDOW_SD ((uint32_t)0x00100000) -#define SD_HIGH_CAPACITY ((uint32_t)0x40000000) -#define SD_STD_CAPACITY ((uint32_t)0x00000000) -#define SD_CHECK_PATTERN ((uint32_t)0x000001AA) - -/** - * @brief Supported SD Memory Cards - */ -#define SDIO_STD_CAPACITY_SD_CARD_V1_1 ((uint32_t)0x00000000) -#define SDIO_STD_CAPACITY_SD_CARD_V2_0 ((uint32_t)0x00000001) -#define SDIO_HIGH_CAPACITY_SD_CARD ((uint32_t)0x00000002) -#define SDIO_MULTIMEDIA_CARD ((uint32_t)0x00000003) -#define SDIO_SECURE_DIGITAL_IO_CARD ((uint32_t)0x00000004) -#define SDIO_HIGH_SPEED_MULTIMEDIA_CARD ((uint32_t)0x00000005) -#define SDIO_SECURE_DIGITAL_IO_COMBO_CARD ((uint32_t)0x00000006) -#define SDIO_HIGH_CAPACITY_MMC_CARD ((uint32_t)0x00000007) - -/*! @brief SD group number */ -typedef enum _sd_group_num { - SDH_GroupTimingMode = 0U, /*!< acess mode group*/ - SDH_GroupCommandSystem = 1U, /*!< command system group*/ - SDH_GroupDriverStrength = 2U, /*!< driver strength group*/ - SDH_GroupCurrentLimit = 3U, /*!< current limit group*/ -} sd_group_num; - -/*! @brief SD card timing mode flags */ -typedef enum _sd_timing_mode { - SDH_TimingSDR12DefaultMode = 0U, /*!< Identification mode & SDR12 */ - SDH_TimingSDR25HighSpeedMode = 1U, /*!< High speed mode & SDR25 */ - SDH_TimingSDR50Mode = 2U, /*!< SDR50 mode*/ - SDH_TimingSDR104Mode = 3U, /*!< SDR104 mode */ - SDH_TimingDDR50Mode = 4U, /*!< DDR50 mode */ -} sd_timing_mode_t; - -/*! @brief SD card specification version number */ -enum _sd_specification_version { - SD_SpecificationVersion1_0 = (1U << 0U), /*!< SD card version 1.0-1.01 */ - SD_SpecificationVersion1_1 = (1U << 1U), /*!< SD card version 1.10 */ - SD_SpecificationVersion2_0 = (1U << 2U), /*!< SD card version 2.00 */ - SD_SpecificationVersion3_0 = (1U << 3U), /*!< SD card version 3.0 */ -}; - -/*! @brief SD card switch mode */ -typedef enum _sd_switch_mode { - SDH_SwitchCheck = 0U, /*!< SD switch mode 0: check function */ - SDH_SwitchSet = 1U, /*!< SD switch mode 1: set function */ -} sd_switch_mode_t; - - -#if SDH_DEBUG -#define SDH_MSG(a, ...) printf(a, ##__VA_ARGS__) -#else -#define SDH_MSG(a, ...) -#endif - -/* -bus_wide shoud be SDH_DATA_BUS_WIDTH_1BIT/SDH_DATA_BUS_WIDTH_4BITS/SDH_DATA_BUS_WIDTH_8BITS -*/ -status_t SDH_ClockSet(uint32_t clockInit, uint32_t clockSrc, uint32_t clockTransfer); -status_t SDH_Init(uint32_t bus_wide, sd_card_t *pOutCardInfo); -status_t SD_Erase(uint32_t startaddr, uint32_t endaddr); -status_t SDH_ReadMultiBlocks(uint8_t *readbuff, uint32_t ReadAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -status_t SDH_WriteMultiBlocks(uint8_t *writebuff, uint32_t WriteAddr, uint16_t BlockSize, uint32_t NumberOfBlocks); -#endif /* __SDCARD_H */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.c deleted file mode 100644 index 3a9d62d8ca..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.c +++ /dev/null @@ -1,797 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -#include -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include - -#include "bl_sec.h" -#include "bl_irq.h" - -#include - -#define xstr(a) str_macro(a) -#define str_macro(a) #a -#define TRNG_LOOP_COUNTER (17) - -#define TRNG_SIZE_IN_WORD (8) -#define TRNG_SIZE_IN_BYTES (32) -static uint32_t trng_buffer[TRNG_SIZE_IN_WORD]; -static unsigned int trng_idx = 0; - -static StaticSemaphore_t sha_mutex_buf; -SemaphoreHandle_t g_bl_sec_sha_mutex = NULL; - -static inline void _trng_trigger() -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t val; - - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - if (BL_IS_REG_BIT_SET(val, SEC_ENG_SE_TRNG_0_BUSY)) { - return; - } - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_1, trng_buffer[0]); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_2, trng_buffer[1]); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_SET_1T); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_EN); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_TRIG_1T); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, val); -} - -static inline void wait_trng4feed() -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t val; - - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - while (BL_IS_REG_BIT_SET(val, SEC_ENG_SE_TRNG_0_BUSY)) { - /*wait until trng is NOT busy*/ - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - } - - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - val = BL_CLR_REG_BIT(val, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, val); - - blog_debug("Feed random number is %08lx\r\n", trng_buffer[0]); - trng_buffer[0] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0); - trng_buffer[1] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1); - trng_buffer[2] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2); - trng_buffer[3] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3); - trng_buffer[4] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4); - trng_buffer[5] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5); - trng_buffer[6] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6); - trng_buffer[7] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7); -} - -uint32_t bl_sec_get_random_word(void) -{ - trng_idx = (trng_idx & 0x7); - if (0 == trng_idx) { - _trng_trigger(); - } - return trng_buffer[trng_idx++]; -} - -void bl_rand_stream(uint8_t *buf, int len) -{ - // int pos, copysize; - - // pos = 0; - // if (trng_idx) { - // /*reset trng_buffer*/ - // _trng_trigger(); - // wait_trng4feed(); - // trng_idx = 0; - // } - - // while (len > 0) { - // if (trng_idx) { - // /*reset trng_buffer*/ - // _trng_trigger(); - // wait_trng4feed(); - // trng_idx = 0; - // } - // copysize = len > TRNG_SIZE_IN_BYTES ? TRNG_SIZE_IN_BYTES : len; - // memcpy(buf + pos, trng_buffer, copysize); - // pos += copysize; - // len -= copysize; - // trng_idx = TRNG_SIZE_IN_BYTES - 1; - // } - // _trng_trigger(); - // wait_trng4feed(); - // trng_idx = 0; - int i; - - for (i = 0; i < len; i++) { - buf[i] = (uint8_t)bl_rand(); - } -} - -int bl_rand() -{ - // unsigned int val; - // int counter = 0; - - // do { - // val = bl_sec_get_random_word(); - // if ((counter++) > TRNG_LOOP_COUNTER) { - // puts("[BL] [SEC] Failed after loop " xstr(TRNG_LOOP_COUNTER) "\r\n"); - // break; - // } - // } while (0 == val); - // val >>= 1;//leave signe bit alone - return rand(); -} - -void sec_trng_IRQHandler(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t val; - - if (aos_now_ms() < 1000 * 2) { - /*debug when boot*/ - puts("[BL] [SEC] TRNG Handler\r\n"); - } - val = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - val = BL_CLR_REG_BIT(val, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, val); - - blog_debug("random number is %08lx\r\n", trng_buffer[0]); - trng_buffer[0] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0); - trng_buffer[1] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1); - trng_buffer[2] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2); - trng_buffer[3] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3); - trng_buffer[4] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4); - trng_buffer[5] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5); - trng_buffer[6] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6); - trng_buffer[7] = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7); -} - -int bl_sec_init(void) -{ - if (g_bl_sec_sha_mutex) { - return 0; - } - g_bl_sec_sha_mutex = xSemaphoreCreateMutexStatic(&sha_mutex_buf); -#if 0 - _trng_trigger(); - wait_trng4feed(); - /*Trigger again*/ - _trng_trigger(); - wait_trng4feed(); - bl_irq_register(SEC_TRNG_IRQn, sec_trng_IRQHandler); - bl_irq_enable(SEC_TRNG_IRQn); -#endif - - return 0; -} - -int bl_exp_mod(uint32_t *src, uint32_t *result, int len, uint32_t *exp, int exp_len, uint32_t *mod, int mod_len) -{ - return 0; -} - -int bl_sec_test(void) -{ - blog_print("------------------TRNG TEST---------------------------------\r\n"); - blog_print("**********TRNG TEST rand[%08x]**************\r\n", bl_rand()); - blog_print("**********TRNG TEST rand[%08x]**************\r\n", bl_rand()); - blog_print("------------------------------------------------------------\r\n"); - - return 0; -} - -void _dump_rsa_data(const uint8_t *data, int size) -{ - int i; - - for (i = 0; i < size; i++) { - switch (i & 0xF) { - case 0x0: - { - blog_print("[%04X]:", i); - blog_print(" %02X", data[i]); - } - break; - case 0xF: - { - blog_print(" %02X", data[i]); - puts("\r\n"); - } - break; - default: - { - blog_print(" %02X", data[i]); - } - } - } -} - -static void RSA_Compare_Data(const uint8_t *expected, const uint8_t *input, uint32_t len) -{ - int i = 0, is_failed = 0; - - for (i = 0; i < len; i++) { - if (input[i] != expected[i]) { - is_failed = 1; - blog_info("%s[%02d], %02x %02x\r\n", - input[i] ==expected[i] ? "S" : "F", - i, - input[i], - expected[i] - ); - } - } - if (is_failed) { - blog_error("====== Failed %lu Bytes======\r\n", len); - } else { - blog_info("====== Success %lu Bytes=====\r\n", len); - } -} - -static void _pka_test_case2(void) -{ - static const uint8_t n[256] = { - 0xd8, 0xa6, 0x4f, 0xea, 0x28, 0xf9, 0xdf, 0x07, 0x04, 0x55, 0xfa, 0xfb, 0x50, 0x5d, 0xbe, 0xb6, - 0x9f, 0x7b, 0x53, 0x96, 0xef, 0x05, 0x5e, 0x0a, 0xf5, 0x2d, 0xe3, 0x67, 0x78, 0x07, 0x6b, 0xf6, - 0xb2, 0x17, 0xac, 0x2e, 0x51, 0x42, 0x84, 0xbb, 0xfe, 0x3e, 0x5f, 0x0c, 0x85, 0xc4, 0x9d, 0xd4, - 0x8b, 0xd5, 0xfa, 0x17, 0x2d, 0xb1, 0x26, 0x81, 0xe7, 0x79, 0x07, 0x45, 0x82, 0x42, 0x22, 0x3d, - 0x0d, 0x97, 0xcf, 0xde, 0xea, 0xb8, 0xba, 0x16, 0x05, 0x8a, 0x5b, 0x0f, 0xec, 0x07, 0x30, 0xa4, - 0xc6, 0xbf, 0xff, 0x20, 0x52, 0x1b, 0x94, 0xad, 0xfa, 0xb7, 0x6e, 0x83, 0x14, 0x48, 0x58, 0x14, - 0x99, 0xe7, 0xa3, 0x9e, 0xc1, 0x08, 0xbd, 0xfe, 0x20, 0x11, 0x56, 0xdb, 0x96, 0x0a, 0xbb, 0x0b, - 0xbc, 0xd4, 0x37, 0x55, 0xf9, 0x9c, 0x6d, 0x5b, 0x87, 0x4e, 0x50, 0x9f, 0x24, 0x0e, 0x3a, 0x1a, - 0x0c, 0x54, 0x67, 0xbd, 0x0f, 0x34, 0x03, 0x5e, 0x45, 0x5b, 0x93, 0x42, 0xbe, 0x71, 0xe6, 0xa7, - 0xf9, 0x49, 0x1a, 0xb3, 0xb2, 0xfb, 0x0e, 0xee, 0x3d, 0xcf, 0x0c, 0x5a, 0xf8, 0xb5, 0x80, 0x42, - 0x7c, 0x0c, 0x75, 0xc5, 0xe1, 0x17, 0x29, 0x39, 0x55, 0x2b, 0xb1, 0xf5, 0x72, 0x06, 0x9e, 0x54, - 0x0b, 0x0e, 0xf2, 0x95, 0xc8, 0x5b, 0x69, 0xaf, 0x5b, 0x81, 0x97, 0xae, 0xb1, 0x6e, 0xc4, 0x6d, - 0x95, 0xd8, 0x22, 0x1e, 0x39, 0xf0, 0x76, 0x54, 0x19, 0x96, 0x03, 0x4c, 0x25, 0x85, 0x2f, 0xe1, - 0x84, 0xd7, 0xc1, 0x62, 0xe1, 0x9e, 0x9f, 0x1f, 0xd4, 0xb8, 0xf0, 0xc2, 0x68, 0x76, 0x7c, 0xcf, - 0x43, 0x3e, 0x60, 0x93, 0xd0, 0x89, 0x65, 0xae, 0x72, 0xcd, 0xd6, 0x00, 0x0d, 0x91, 0x42, 0x90, - 0x98, 0x02, 0xa9, 0xf6, 0x82, 0x1b, 0xb5, 0x22, 0xfd, 0xb6, 0xc2, 0x5c, 0xad, 0x86, 0x81, 0x1d, - }; - static const uint8_t m[256] = { - 0x30, 0x31, 0x36, 0x64, 0x61, 0x34, 0x31, 0x66, 0x34, 0x62, 0x66, 0x35, 0x38, 0x61, 0x36, 0x32, - 0x35, 0x61, 0x61, 0x35, 0x63, 0x33, 0x30, 0x37, 0x62, 0x63, 0x64, 0x31, 0x61, 0x37, 0x35, 0x30, - 0x33, 0x64, 0x62, 0x30, 0x36, 0x63, 0x39, 0x37, 0x62, 0x30, 0x39, 0x31, 0x39, 0x33, 0x38, 0x61, - 0x32, 0x31, 0x62, 0x35, 0x66, 0x36, 0x38, 0x65, 0x33, 0x37, 0x37, 0x61, 0x62, 0x38, 0x39, 0x39, - 0x62, 0x65, 0x66, 0x37, 0x63, 0x61, 0x31, 0x36, 0x35, 0x30, 0x65, 0x38, 0x66, 0x30, 0x38, 0x64, - 0x37, 0x32, 0x38, 0x37, 0x64, 0x64, 0x30, 0x66, 0x36, 0x64, 0x32, 0x61, 0x64, 0x36, 0x34, 0x31, - 0x32, 0x38, 0x38, 0x33, 0x38, 0x63, 0x35, 0x39, 0x35, 0x61, 0x32, 0x64, 0x31, 0x30, 0x65, 0x34, - 0x36, 0x37, 0x61, 0x62, 0x35, 0x34, 0x35, 0x33, 0x63, 0x34, 0x65, 0x63, 0x37, 0x37, 0x30, 0x35, - 0x33, 0x38, 0x61, 0x63, 0x39, 0x66, 0x38, 0x30, 0x36, 0x66, 0x30, 0x38, 0x66, 0x66, 0x33, 0x30, - 0x38, 0x65, 0x36, 0x65, 0x64, 0x62, 0x35, 0x35, 0x34, 0x31, 0x66, 0x39, 0x66, 0x30, 0x34, 0x36, - 0x63, 0x36, 0x37, 0x32, 0x62, 0x31, 0x32, 0x30, 0x37, 0x37, 0x35, 0x35, 0x62, 0x30, 0x35, 0x66, - 0x35, 0x36, 0x64, 0x33, 0x61, 0x36, 0x36, 0x31, 0x37, 0x64, 0x63, 0x37, 0x35, 0x34, 0x64, 0x35, - 0x65, 0x32, 0x30, 0x34, 0x63, 0x31, 0x36, 0x31, 0x36, 0x61, 0x31, 0x33, 0x65, 0x33, 0x62, 0x31, - 0x34, 0x65, 0x38, 0x65, 0x32, 0x39, 0x63, 0x39, 0x35, 0x33, 0x33, 0x38, 0x36, 0x65, 0x65, 0x64, - 0x62, 0x63, 0x30, 0x39, 0x34, 0x30, 0x37, 0x62, 0x39, 0x34, 0x33, 0x34, 0x38, 0x37, 0x37, 0x36, - 0x36, 0x37, 0x63, 0x62, 0x33, 0x30, 0x39, 0x63, 0x36, 0x33, 0x30, 0x34, 0x32, 0x32, 0x36, 0x32, - }; - static const uint8_t e[4] = { - 0x00, 0x01, 0x00, 0x01, - }; - static const uint8_t nprime[256] = { - 0x38, 0x62, 0xc1, 0xf5, 0x55, 0x2d, 0x3d, 0x60, 0x5e, 0x42, 0xe1, 0x65, 0xde, 0xed, 0x35, 0xd5, - 0xc5, 0x85, 0xe4, 0x4e, 0xeb, 0x74, 0xa5, 0x22, 0xb3, 0xed, 0x5f, 0x5b, 0xb1, 0xb9, 0xe9, 0x0a, - 0x7d, 0xa5, 0x74, 0x58, 0xf8, 0xa1, 0xab, 0x17, 0x74, 0xd0, 0x07, 0xa3, 0x7f, 0xd2, 0x9b, 0x50, - 0x2a, 0xed, 0x5e, 0xdc, 0x5a, 0x69, 0xfe, 0x0e, 0xb1, 0xd8, 0x53, 0x35, 0x9b, 0xef, 0x1d, 0x76, - 0x52, 0x9e, 0x87, 0x3c, 0xb0, 0x82, 0x4e, 0x03, 0xdf, 0x75, 0xed, 0x09, 0x9f, 0x3d, 0x37, 0xf6, - 0xe8, 0x0d, 0xc9, 0x2e, 0x81, 0xf2, 0x9d, 0x2e, 0xaa, 0xe6, 0x53, 0x79, 0x6b, 0x99, 0xef, 0x46, - 0x36, 0xd9, 0x2e, 0x9d, 0x15, 0xd1, 0x7f, 0x23, 0x14, 0xb9, 0xeb, 0x33, 0xa7, 0xd4, 0x8e, 0x86, - 0x60, 0xc9, 0xd9, 0x7c, 0xca, 0x54, 0x59, 0x57, 0x94, 0x1e, 0x52, 0x4d, 0xc8, 0x3f, 0x9b, 0x24, - 0x28, 0x25, 0xcb, 0x57, 0xca, 0x8f, 0x16, 0x5a, 0x37, 0xc2, 0xc6, 0xae, 0xc5, 0xe7, 0xc4, 0x2e, - 0xf3, 0x24, 0x1c, 0xb7, 0xe9, 0xf5, 0x92, 0x4e, 0xd4, 0x51, 0x50, 0xff, 0xde, 0x44, 0x3c, 0xae, - 0x72, 0xbd, 0x16, 0x39, 0x63, 0x8a, 0x22, 0x9c, 0x95, 0xda, 0x21, 0xf0, 0x4c, 0x12, 0x36, 0x2d, - 0x00, 0xad, 0xb3, 0x89, 0xb5, 0x09, 0x9e, 0x3d, 0x24, 0x81, 0xfc, 0xef, 0x99, 0x95, 0x22, 0x9d, - 0xb3, 0x94, 0x39, 0x32, 0xdd, 0xc4, 0x2b, 0x2f, 0xb0, 0x13, 0xfe, 0xb5, 0x5e, 0xc7, 0x64, 0x93, - 0x7a, 0xb5, 0x81, 0x93, 0x1f, 0x9f, 0x96, 0x1e, 0x7a, 0x5c, 0x8d, 0xde, 0x8f, 0xae, 0xd9, 0xc8, - 0xdd, 0x35, 0x1e, 0x17, 0x47, 0xb6, 0xab, 0xed, 0xb6, 0x82, 0x22, 0x4c, 0x62, 0xbd, 0x12, 0x4e, - 0x44, 0x5c, 0x48, 0x2b, 0x75, 0x63, 0x1c, 0xde, 0xfa, 0x15, 0x0d, 0xb1, 0x50, 0x31, 0xb6, 0xcb, - }; - static const uint8_t inv_r[256] = { - 0x2f, 0xb7, 0xf5, 0x4a, 0xd2, 0x19, 0xde, 0x24, 0x7c, 0xdb, 0xcd, 0x52, 0x6e, 0xbc, 0x2c, 0x5c, - 0x76, 0x9a, 0x36, 0xc3, 0x87, 0x33, 0xf7, 0xe9, 0x3d, 0x5b, 0x3d, 0xcd, 0x33, 0x7a, 0x3b, 0x4e, - 0x55, 0xf5, 0xd9, 0x42, 0x76, 0x63, 0x28, 0x7a, 0xa8, 0x7c, 0xf7, 0xd1, 0xf6, 0x0d, 0x26, 0xba, - 0xbe, 0x9f, 0x35, 0xf4, 0x86, 0xc5, 0x93, 0x4c, 0xe8, 0x76, 0xda, 0x88, 0xb8, 0xbe, 0xad, 0x25, - 0x6b, 0xe7, 0x44, 0x3b, 0x1c, 0x2c, 0x99, 0x15, 0xee, 0x33, 0x46, 0xc6, 0xe0, 0xb0, 0x39, 0x6d, - 0x20, 0xb2, 0x68, 0xc7, 0x75, 0x41, 0x2c, 0xff, 0xcb, 0x93, 0x1d, 0x40, 0xd2, 0x0e, 0x64, 0xea, - 0x2e, 0x0a, 0x55, 0x9f, 0x04, 0x9d, 0xfd, 0x5e, 0x24, 0xa9, 0x28, 0x5c, 0x2d, 0x1b, 0x29, 0x87, - 0x61, 0x6b, 0x50, 0x6a, 0x31, 0x31, 0x43, 0x12, 0x13, 0xe3, 0x1f, 0x47, 0x8a, 0x11, 0xd2, 0x5b, - 0x26, 0x5e, 0x79, 0x04, 0x0b, 0xa8, 0xb0, 0x36, 0x22, 0xda, 0x3c, 0x5e, 0xb9, 0x09, 0x48, 0xb0, - 0x32, 0x38, 0x25, 0xec, 0xfd, 0x5e, 0xef, 0xff, 0x80, 0x33, 0x9f, 0x94, 0x8c, 0x6e, 0x2a, 0xfb, - 0xbf, 0x65, 0x18, 0x98, 0x7e, 0xff, 0x41, 0xde, 0x00, 0x2f, 0xd2, 0x7d, 0xbf, 0x4c, 0x54, 0x4e, - 0x1c, 0x46, 0xd6, 0xab, 0xf6, 0x07, 0x34, 0x63, 0xe3, 0x0b, 0x81, 0xa0, 0x94, 0x7d, 0xaf, 0x7e, - 0x37, 0xd6, 0xc5, 0xa6, 0x4a, 0x90, 0x6c, 0x44, 0x6a, 0xd9, 0x0f, 0x20, 0xb2, 0xef, 0x22, 0xa0, - 0xdf, 0x38, 0x2d, 0x0b, 0xb3, 0x03, 0xb2, 0xc8, 0xe6, 0x8d, 0x74, 0xbf, 0x45, 0x91, 0xe0, 0x22, - 0x16, 0xbf, 0xc4, 0xda, 0x54, 0x26, 0xaa, 0x65, 0x85, 0x88, 0xc3, 0xfb, 0x9f, 0xfc, 0x14, 0xc4, - 0xff, 0x8b, 0x88, 0x47, 0x5f, 0xb1, 0x55, 0xdf, 0x47, 0x5c, 0xc0, 0x27, 0x39, 0x7b, 0xe8, 0xad, - }; - uint32_t result[64]; - static const uint8_t encrypted[256] = { - 0x9e, 0xf6, 0x6f, 0x46, 0xf5, 0x51, 0x1a, 0xbc, 0xc2, 0x9c, 0x49, 0x02, 0x21, 0x6c, 0x20, 0xae, - 0x49, 0x91, 0xcd, 0xba, 0xb9, 0x4f, 0xaf, 0xfd, 0x8d, 0x9a, 0x27, 0xbc, 0x0b, 0x69, 0x57, 0xc4, - 0xba, 0x18, 0xe1, 0x56, 0x45, 0x55, 0xbb, 0x3f, 0x7b, 0xca, 0x45, 0xb3, 0x9a, 0x0e, 0xd7, 0x64, - 0x6e, 0x71, 0xce, 0xd3, 0x08, 0xc9, 0x4b, 0x97, 0xab, 0x24, 0xe4, 0x6c, 0xe3, 0xc7, 0x52, 0x97, - 0x3c, 0x45, 0x17, 0x3b, 0x17, 0x0a, 0x90, 0x50, 0xed, 0x73, 0x4b, 0x49, 0x07, 0xee, 0x13, 0xaf, - 0x47, 0x1e, 0xd0, 0x24, 0xb1, 0xd2, 0xc8, 0x09, 0x75, 0xf3, 0x14, 0x9c, 0x71, 0x99, 0xe3, 0x94, - 0x5b, 0xf6, 0xef, 0x2e, 0x79, 0xf5, 0x1d, 0xdc, 0xa7, 0xc5, 0xed, 0x0a, 0x3f, 0x1d, 0x43, 0xd0, - 0x19, 0x14, 0x3a, 0xb7, 0x35, 0xc2, 0x3f, 0xa1, 0x9c, 0x00, 0xde, 0xf6, 0x96, 0x55, 0xf8, 0x0c, - 0x79, 0x08, 0x68, 0xf3, 0x84, 0x7c, 0x2e, 0x0c, 0x51, 0xb6, 0x5e, 0x9e, 0xcd, 0x50, 0xcc, 0x5f, - 0x71, 0x99, 0xc1, 0x0d, 0xf0, 0x3c, 0xd0, 0x80, 0x02, 0xf0, 0x8f, 0x12, 0x3e, 0x49, 0xa4, 0x9b, - 0x1f, 0x14, 0x05, 0xf2, 0x7b, 0x41, 0xc1, 0x3e, 0x8a, 0xb2, 0xab, 0x70, 0x28, 0x2f, 0x20, 0x94, - 0x17, 0x65, 0xf3, 0x89, 0x28, 0x6d, 0xcd, 0x0c, 0xea, 0x03, 0x4a, 0x10, 0x9d, 0xf9, 0x2e, 0xf4, - 0x64, 0x79, 0x7a, 0xec, 0x46, 0xb4, 0xdf, 0xce, 0x6a, 0x8e, 0xd8, 0x35, 0x62, 0xb3, 0x04, 0xea, - 0xf9, 0xc4, 0xde, 0xba, 0x2a, 0x5e, 0xbf, 0x59, 0xfa, 0xef, 0x2a, 0x42, 0x18, 0xc9, 0xf5, 0x7a, - 0x73, 0xb8, 0x67, 0x78, 0x97, 0x6d, 0x75, 0x4b, 0xdd, 0xfb, 0x9b, 0xe6, 0x4c, 0x04, 0x9c, 0x61, - 0x5f, 0x9a, 0x12, 0xbf, 0x2e, 0x75, 0x63, 0xdd, 0x50, 0xba, 0x2c, 0xef, 0xb0, 0x9a, 0x65, 0x24, - }; - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 0, (uint32_t*)n, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 1, (uint32_t*)nprime, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 2, (uint32_t*)m, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 3, (uint32_t*)e, 1, 0); - - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 4, 0, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 5, 0, 1); - Sec_Eng_PKA_LMUL2N( - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 2, - 2048, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 0, - 0 - ); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_512, 2, 0, 1); - - Sec_Eng_PKA_MEXP( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 3, - SEC_ENG_PKA_REG_SIZE_256, 0, - 1 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 4, - 1 - ); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 1, (uint32_t*)inv_r, 64, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 4, 0, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 5, 0, 1); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_512, 2, - SEC_ENG_PKA_REG_SIZE_256, 0, - 0 - ); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_512, 2, 0, 1); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, sizeof(result)); - RSA_Compare_Data(encrypted, (uint8_t*)result, sizeof(result)); -} - -static void __attribute__((unused)) dump_xgcd_step(uint32_t result[64]) -{ - puts(" ---- PKA 8:0\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 0, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:1\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 1, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:2\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:3\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 3, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:4\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 4, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:5\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 5, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:6\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); - - puts(" ---- PKA 8:7\r\n"); - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 7, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, 256); -} - - -static void _pka_test_case_xgcd(void) -{ - int count = 0; - static const uint8_t n[256] = { - 0xd8, 0xa6, 0x4f, 0xea, 0x28, 0xf9, 0xdf, 0x07, 0x04, 0x55, 0xfa, 0xfb, 0x50, 0x5d, 0xbe, 0xb6, - 0x9f, 0x7b, 0x53, 0x96, 0xef, 0x05, 0x5e, 0x0a, 0xf5, 0x2d, 0xe3, 0x67, 0x78, 0x07, 0x6b, 0xf6, - 0xb2, 0x17, 0xac, 0x2e, 0x51, 0x42, 0x84, 0xbb, 0xfe, 0x3e, 0x5f, 0x0c, 0x85, 0xc4, 0x9d, 0xd4, - 0x8b, 0xd5, 0xfa, 0x17, 0x2d, 0xb1, 0x26, 0x81, 0xe7, 0x79, 0x07, 0x45, 0x82, 0x42, 0x22, 0x3d, - 0x0d, 0x97, 0xcf, 0xde, 0xea, 0xb8, 0xba, 0x16, 0x05, 0x8a, 0x5b, 0x0f, 0xec, 0x07, 0x30, 0xa4, - 0xc6, 0xbf, 0xff, 0x20, 0x52, 0x1b, 0x94, 0xad, 0xfa, 0xb7, 0x6e, 0x83, 0x14, 0x48, 0x58, 0x14, - 0x99, 0xe7, 0xa3, 0x9e, 0xc1, 0x08, 0xbd, 0xfe, 0x20, 0x11, 0x56, 0xdb, 0x96, 0x0a, 0xbb, 0x0b, - 0xbc, 0xd4, 0x37, 0x55, 0xf9, 0x9c, 0x6d, 0x5b, 0x87, 0x4e, 0x50, 0x9f, 0x24, 0x0e, 0x3a, 0x1a, - 0x0c, 0x54, 0x67, 0xbd, 0x0f, 0x34, 0x03, 0x5e, 0x45, 0x5b, 0x93, 0x42, 0xbe, 0x71, 0xe6, 0xa7, - 0xf9, 0x49, 0x1a, 0xb3, 0xb2, 0xfb, 0x0e, 0xee, 0x3d, 0xcf, 0x0c, 0x5a, 0xf8, 0xb5, 0x80, 0x42, - 0x7c, 0x0c, 0x75, 0xc5, 0xe1, 0x17, 0x29, 0x39, 0x55, 0x2b, 0xb1, 0xf5, 0x72, 0x06, 0x9e, 0x54, - 0x0b, 0x0e, 0xf2, 0x95, 0xc8, 0x5b, 0x69, 0xaf, 0x5b, 0x81, 0x97, 0xae, 0xb1, 0x6e, 0xc4, 0x6d, - 0x95, 0xd8, 0x22, 0x1e, 0x39, 0xf0, 0x76, 0x54, 0x19, 0x96, 0x03, 0x4c, 0x25, 0x85, 0x2f, 0xe1, - 0x84, 0xd7, 0xc1, 0x62, 0xe1, 0x9e, 0x9f, 0x1f, 0xd4, 0xb8, 0xf0, 0xc2, 0x68, 0x76, 0x7c, 0xcf, - 0x43, 0x3e, 0x60, 0x93, 0xd0, 0x89, 0x65, 0xae, 0x72, 0xcd, 0xd6, 0x00, 0x0d, 0x91, 0x42, 0x90, - 0x98, 0x02, 0xa9, 0xf6, 0x82, 0x1b, 0xb5, 0x22, 0xfd, 0xb6, 0xc2, 0x5c, 0xad, 0x86, 0x81, 0x1d, - }; -#if 0 - static const uint8_t nprime[256] = { - 0x38, 0x62, 0xc1, 0xf5, 0x55, 0x2d, 0x3d, 0x60, 0x5e, 0x42, 0xe1, 0x65, 0xde, 0xed, 0x35, 0xd5, - 0xc5, 0x85, 0xe4, 0x4e, 0xeb, 0x74, 0xa5, 0x22, 0xb3, 0xed, 0x5f, 0x5b, 0xb1, 0xb9, 0xe9, 0x0a, - 0x7d, 0xa5, 0x74, 0x58, 0xf8, 0xa1, 0xab, 0x17, 0x74, 0xd0, 0x07, 0xa3, 0x7f, 0xd2, 0x9b, 0x50, - 0x2a, 0xed, 0x5e, 0xdc, 0x5a, 0x69, 0xfe, 0x0e, 0xb1, 0xd8, 0x53, 0x35, 0x9b, 0xef, 0x1d, 0x76, - 0x52, 0x9e, 0x87, 0x3c, 0xb0, 0x82, 0x4e, 0x03, 0xdf, 0x75, 0xed, 0x09, 0x9f, 0x3d, 0x37, 0xf6, - 0xe8, 0x0d, 0xc9, 0x2e, 0x81, 0xf2, 0x9d, 0x2e, 0xaa, 0xe6, 0x53, 0x79, 0x6b, 0x99, 0xef, 0x46, - 0x36, 0xd9, 0x2e, 0x9d, 0x15, 0xd1, 0x7f, 0x23, 0x14, 0xb9, 0xeb, 0x33, 0xa7, 0xd4, 0x8e, 0x86, - 0x60, 0xc9, 0xd9, 0x7c, 0xca, 0x54, 0x59, 0x57, 0x94, 0x1e, 0x52, 0x4d, 0xc8, 0x3f, 0x9b, 0x24, - 0x28, 0x25, 0xcb, 0x57, 0xca, 0x8f, 0x16, 0x5a, 0x37, 0xc2, 0xc6, 0xae, 0xc5, 0xe7, 0xc4, 0x2e, - 0xf3, 0x24, 0x1c, 0xb7, 0xe9, 0xf5, 0x92, 0x4e, 0xd4, 0x51, 0x50, 0xff, 0xde, 0x44, 0x3c, 0xae, - 0x72, 0xbd, 0x16, 0x39, 0x63, 0x8a, 0x22, 0x9c, 0x95, 0xda, 0x21, 0xf0, 0x4c, 0x12, 0x36, 0x2d, - 0x00, 0xad, 0xb3, 0x89, 0xb5, 0x09, 0x9e, 0x3d, 0x24, 0x81, 0xfc, 0xef, 0x99, 0x95, 0x22, 0x9d, - 0xb3, 0x94, 0x39, 0x32, 0xdd, 0xc4, 0x2b, 0x2f, 0xb0, 0x13, 0xfe, 0xb5, 0x5e, 0xc7, 0x64, 0x93, - 0x7a, 0xb5, 0x81, 0x93, 0x1f, 0x9f, 0x96, 0x1e, 0x7a, 0x5c, 0x8d, 0xde, 0x8f, 0xae, 0xd9, 0xc8, - 0xdd, 0x35, 0x1e, 0x17, 0x47, 0xb6, 0xab, 0xed, 0xb6, 0x82, 0x22, 0x4c, 0x62, 0xbd, 0x12, 0x4e, - 0x44, 0x5c, 0x48, 0x2b, 0x75, 0x63, 0x1c, 0xde, 0xfa, 0x15, 0x0d, 0xb1, 0x50, 0x31, 0xb6, 0xcb, - }; - static const uint8_t inv_r[256] = { - 0x2f, 0xb7, 0xf5, 0x4a, 0xd2, 0x19, 0xde, 0x24, 0x7c, 0xdb, 0xcd, 0x52, 0x6e, 0xbc, 0x2c, 0x5c, - 0x76, 0x9a, 0x36, 0xc3, 0x87, 0x33, 0xf7, 0xe9, 0x3d, 0x5b, 0x3d, 0xcd, 0x33, 0x7a, 0x3b, 0x4e, - 0x55, 0xf5, 0xd9, 0x42, 0x76, 0x63, 0x28, 0x7a, 0xa8, 0x7c, 0xf7, 0xd1, 0xf6, 0x0d, 0x26, 0xba, - 0xbe, 0x9f, 0x35, 0xf4, 0x86, 0xc5, 0x93, 0x4c, 0xe8, 0x76, 0xda, 0x88, 0xb8, 0xbe, 0xad, 0x25, - 0x6b, 0xe7, 0x44, 0x3b, 0x1c, 0x2c, 0x99, 0x15, 0xee, 0x33, 0x46, 0xc6, 0xe0, 0xb0, 0x39, 0x6d, - 0x20, 0xb2, 0x68, 0xc7, 0x75, 0x41, 0x2c, 0xff, 0xcb, 0x93, 0x1d, 0x40, 0xd2, 0x0e, 0x64, 0xea, - 0x2e, 0x0a, 0x55, 0x9f, 0x04, 0x9d, 0xfd, 0x5e, 0x24, 0xa9, 0x28, 0x5c, 0x2d, 0x1b, 0x29, 0x87, - 0x61, 0x6b, 0x50, 0x6a, 0x31, 0x31, 0x43, 0x12, 0x13, 0xe3, 0x1f, 0x47, 0x8a, 0x11, 0xd2, 0x5b, - 0x26, 0x5e, 0x79, 0x04, 0x0b, 0xa8, 0xb0, 0x36, 0x22, 0xda, 0x3c, 0x5e, 0xb9, 0x09, 0x48, 0xb0, - 0x32, 0x38, 0x25, 0xec, 0xfd, 0x5e, 0xef, 0xff, 0x80, 0x33, 0x9f, 0x94, 0x8c, 0x6e, 0x2a, 0xfb, - 0xbf, 0x65, 0x18, 0x98, 0x7e, 0xff, 0x41, 0xde, 0x00, 0x2f, 0xd2, 0x7d, 0xbf, 0x4c, 0x54, 0x4e, - 0x1c, 0x46, 0xd6, 0xab, 0xf6, 0x07, 0x34, 0x63, 0xe3, 0x0b, 0x81, 0xa0, 0x94, 0x7d, 0xaf, 0x7e, - 0x37, 0xd6, 0xc5, 0xa6, 0x4a, 0x90, 0x6c, 0x44, 0x6a, 0xd9, 0x0f, 0x20, 0xb2, 0xef, 0x22, 0xa0, - 0xdf, 0x38, 0x2d, 0x0b, 0xb3, 0x03, 0xb2, 0xc8, 0xe6, 0x8d, 0x74, 0xbf, 0x45, 0x91, 0xe0, 0x22, - 0x16, 0xbf, 0xc4, 0xda, 0x54, 0x26, 0xaa, 0x65, 0x85, 0x88, 0xc3, 0xfb, 0x9f, 0xfc, 0x14, 0xc4, - 0xff, 0x8b, 0x88, 0x47, 0x5f, 0xb1, 0x55, 0xdf, 0x47, 0x5c, 0xc0, 0x27, 0x39, 0x7b, 0xe8, 0xad, - }; -#endif - static const uint8_t n_exp[256] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - }; - static const uint8_t all_zero[256] = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - }; - uint32_t result[64]; - uint8_t pka_a_eq_0 = 0; - - - (void) count; - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 1, (uint32_t*)n, 64, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 2, 0, 0); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_256, 3, 0, 1); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 0, (uint32_t*)n_exp, 64, 0); - - - Sec_Eng_PKA_LMUL2N( - SEC_ENG_PKA_REG_SIZE_512, 1, - SEC_ENG_PKA_REG_SIZE_256, 0, - 2048, - 0 - ); - Sec_Eng_PKA_LDIV( - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_512, 1, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_512, 1, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_512, 1, 0, 1); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 1, - SEC_ENG_PKA_REG_SIZE_256, 4, - 1 - ); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 4, (uint32_t*)all_zero, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 5, (uint32_t*)n_exp, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 6, (uint32_t*)n_exp, 64, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 7, (uint32_t*)all_zero, 64, 0); - - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 9, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 5, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 7, - SEC_ENG_PKA_REG_SIZE_256, 9, - 1 - ); - -#if 0 - blog_info("Dumping Step count %d\r\n", count++); - dump_xgcd_step(result); -#endif - while (!pka_a_eq_0) { - Sec_Eng_PKA_LDIV( - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_MREM( - SEC_ENG_PKA_REG_SIZE_256, 3, - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 8, - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_LMUL( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 0, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_LSUB( - SEC_ENG_PKA_REG_SIZE_256, 9, - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 9, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 2, - SEC_ENG_PKA_REG_SIZE_256, 1, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 4, - SEC_ENG_PKA_REG_SIZE_256, 5, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 5, - SEC_ENG_PKA_REG_SIZE_256, 8, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - SEC_ENG_PKA_REG_SIZE_256, 7, - 0 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 7, - SEC_ENG_PKA_REG_SIZE_256, 9, - 1 - ); - Sec_Eng_PKA_Move_Data( - SEC_ENG_PKA_REG_SIZE_256, 1, - SEC_ENG_PKA_REG_SIZE_256, 3, - 1 - ); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_256, 10, (uint32_t*)n_exp, 64, 0); - Sec_Eng_PKA_LCMP( - &pka_a_eq_0, - SEC_ENG_PKA_REG_SIZE_256, 1, - SEC_ENG_PKA_REG_SIZE_256, 10 - ); -#if 0 - blog_info("Dumping Step count %d\r\n", count++); - dump_xgcd_step(result); -#endif - } - Sec_Eng_PKA_Read_Data( - SEC_ENG_PKA_REG_SIZE_256, 6, - result, - 64 - ); - _dump_rsa_data((uint8_t*)result, sizeof(result)); - //RSA_Compare_Data(encrypted, (uint8_t*)result, sizeof(result)); -} - -int bl_pka_test(void) -{ -#if 0 - bl_irq_register(SEC_PKA_IRQn, bl_sec_pka_IRQHandler); - bl_irq_enable(SEC_PKA_IRQn); -#endif - - _pka_test_case2(); - _pka_test_case_xgcd(); - _pka_test_case2(); - - return 0; -} - -void bl_sec_pka_IRQHandler(void) -{ - puts("--->>> PKA IRQ\r\n"); - SEC_Eng_IntMask(SEC_ENG_INT_PKA, MASK); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.h deleted file mode 100644 index 09306bca1e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec.h +++ /dev/null @@ -1,85 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_SEC_H__ -#define __BL_SEC_H__ -#include -#include -#include - -#include -#include - -/* copied SEC_Eng_SHA256_Ctx from stddrv */ -typedef struct { - uint32_t total[2]; - uint32_t *shaBuf; - uint32_t *shaPadding; - uint8_t shaFeed; -} _bl_sha_SEC_Eng_SHA256_Ctx_t; - -/* copied SEC_ENG_SHA_Type from stddrv, SHA1_RSVD removed */ -typedef enum { - BL_SHA256, - BL_SHA224, - BL_SHA1, -} bl_sha_type_t; - -typedef struct bl_sha_ctx { - _bl_sha_SEC_Eng_SHA256_Ctx_t sha_ctx; - uint32_t tmp[16]; - uint32_t pad[16]; -} bl_sha_ctx_t; - -extern SemaphoreHandle_t g_bl_sec_sha_mutex; - -int bl_sec_init(void); -int bl_sec_test(void); -int bl_pka_test(void); -int bl_sec_aes_init(void); -int bl_sec_aes_enc(uint8_t *key, int keysize, uint8_t *input, uint8_t *output); -int bl_sec_aes_test(void); -uint32_t bl_sec_get_random_word(void); -void bl_rand_stream(uint8_t *buf, int len); -int bl_rand(void); -/*SHA Engine API*/ -int bl_sec_sha_test(void); - -int bl_sha_mutex_take(); -int bl_sha_mutex_give(); -void bl_sha_init(bl_sha_ctx_t *ctx, const bl_sha_type_t type); -int bl_sha_update(bl_sha_ctx_t *ctx, const uint8_t *input, uint32_t len); -int bl_sha_finish(bl_sha_ctx_t *ctx, uint8_t *hash); -int bl_sec_ccm_encrypt_and_tag(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *iv, size_t iv_len, const unsigned char *add, size_t add_len, - const unsigned char *input, unsigned char *output, unsigned char *tag, size_t tag_len); -int bl_sec_ccm_auth_decrypt(const uint8_t *key, unsigned int key_bytelen, size_t length,const unsigned char *iv, size_t iv_len, const unsigned char *add, - size_t add_len, const unsigned char *input, unsigned char *output, const unsigned char *tag, size_t tag_len); -int bl_sec_aes_ecb_encrypt(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *input, unsigned char *output); -int bl_sec_aes_ecb_decrypt(const uint8_t *key, unsigned int key_bytelen, size_t length, const unsigned char *input, unsigned char *output); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec_sha.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec_sha.c deleted file mode 100644 index 58f3d606a6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sec_sha.c +++ /dev/null @@ -1,180 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -#include - -#include -#include - -#include "bl_irq.h" -#include "bl_sec.h" - -#include - -typedef struct sha256_link_item { - SEC_Eng_SHA256_Link_Ctx ctx; - SEC_Eng_SHA_Link_Config_Type linkCfg; - uint32_t tmp[16]; - uint32_t pad[16]; -} sha256_link_item_t; - -#define BL_SHA_ID SEC_ENG_SHA_ID0 // this is the only valid value - -int bl_sha_mutex_take() -{ - if (pdPASS != xSemaphoreTake(g_bl_sec_sha_mutex, portMAX_DELAY)) { - blog_error("sha semphr take failed\r\n"); - return -1; - } - return 0; -} - -int bl_sha_mutex_give() -{ - if (pdPASS != xSemaphoreGive(g_bl_sec_sha_mutex)) { - blog_error("sha semphr give failed\\n"); - return -1; - } - return 0; -} - -void bl_sha_init(bl_sha_ctx_t *ctx, const bl_sha_type_t type) -{ - const SEC_ENG_SHA_Type sha_type = (SEC_ENG_SHA_Type)type; // bl_sha_type_t is the same as SEC_ENG_SHA_Type in driver - - Sec_Eng_SHA256_Init((SEC_Eng_SHA256_Ctx *)&ctx->sha_ctx, BL_SHA_ID, sha_type, ctx->tmp, ctx->pad); - Sec_Eng_SHA_Start(BL_SHA_ID); -} - -int bl_sha_update(bl_sha_ctx_t *ctx, const uint8_t *input, uint32_t len) -{ - return Sec_Eng_SHA256_Update((SEC_Eng_SHA256_Ctx *)&ctx->sha_ctx, BL_SHA_ID, input, len); -} - -int bl_sha_finish(bl_sha_ctx_t *ctx, uint8_t *hash) -{ - return Sec_Eng_SHA256_Finish((SEC_Eng_SHA256_Ctx *)&ctx->sha_ctx, BL_SHA_ID, hash); -} - -static const uint8_t shaSrcBuf1[64] = -{ - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', - '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', '1', -}; - -static void SHA_Compare_Data(const uint8_t *expected, const uint8_t *input, uint32_t len) -{ - int i = 0, is_failed = 0; - - for (i = 0; i < len; i++) { - if (input[i] != expected[i]) { - is_failed = 1; - blog_print("%s[%02d], %02x %02x\r\n", - input[i] ==expected[i] ? "S" : "F", - i, - input[i], - expected[i] - ); - } - } - if (is_failed) { - blog_print("====== Failed %lu Bytes======\r\n", len); - } else { - blog_print("====== Success %lu Bytes=====\r\n", len); - } -} - -void sha256_test_case0(void) -{ - SEC_ENG_SHA_ID_Type shaId = SEC_ENG_SHA_ID0; - sha256_link_item_t sha256_link = { - .linkCfg.shaMode = SEC_ENG_SHA256, - .linkCfg.shaHashSel = 0, - .linkCfg.shaIntClr = 0, - .linkCfg.shaIntSet = 1, - .linkCfg.shaMsgLen = 1, - .linkCfg.shaSrcAddr = 0x50020000, - }; - static const uint8_t sha256_test_result[] = - { - 0x31, 0x38, 0xbb, 0x9b, 0xc7, 0x8d, 0xf2, 0x7c, 0x47, 0x3e, 0xcf, 0xd1, 0x41, 0x0f, 0x7b, 0xd4, - 0x5e, 0xba, 0xc1, 0xf5, 0x9c, 0xf3, 0xff, 0x9c, 0xfe, 0x4d, 0xb7, 0x7a, 0xab, 0x7a, 0xed, 0xd3, - }; - - -#define SEC_SHA_IRQn (IRQ_NUM_BASE+14) - - bl_irq_register(SEC_SHA_IRQn, bl_sec_sha_IRQHandler); - bl_irq_enable(SEC_SHA_IRQn); - - Sec_Eng_SHA_Enable_Link(shaId); - Sec_Eng_SHA256_Link_Init(&sha256_link.ctx, shaId, - (uint32_t)&sha256_link.linkCfg, - sha256_link.tmp, - sha256_link.pad - ); - Sec_Eng_SHA256_Link_Update(&sha256_link.ctx, shaId, - shaSrcBuf1, - 64 - ); - //FIXME Request to change driver API - Sec_Eng_SHA256_Link_Finish(&sha256_link.ctx, shaId, (uint8_t*)sha256_link.linkCfg.result); - Sec_Eng_SHA_Disable_Link(shaId); - - SHA_Compare_Data((const uint8_t*)sha256_link.linkCfg.result, sha256_test_result, sizeof(sha256_test_result)); -} - -int bl_sec_sha_test(void) -{ - puts("^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\r\n"); - puts("^^^^^^^^^^^^^^^^^^^^^^^SHA256 TEST CASE^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^\r\n"); - sha256_test_case0(); - puts("------------------------------------------------------------------------------------\r\n"); - - return 0; -} -static void _clear_sha_int() -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t val; - - val = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - val = BL_SET_REG_BIT(val, SEC_ENG_SE_SHA_0_INT_CLR_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, val); -} - -void bl_sec_sha_IRQHandler(void) -{ - puts("--->>> SHA IRQ\r\n"); - _clear_sha_int(); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.c deleted file mode 100644 index bc86c9c552..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.c +++ /dev/null @@ -1,325 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -// #include -#include -#include -#include -#include -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif -#include "bl_sys.h" - -#define MFG_CONFIG_REG (0x4000F100) -#define MFG_CONFIG_VAL ("0mfg") - -#define REASON_WDT (0x77646F67) // watchdog reboot wdog -#define REASON_SOFTWARE (0x736F6674) // software soft -#define REASON_POWEROFF (0x0) // software soft - -#define RST_REASON (*((volatile uint32_t *)0x40010000)) // use 4 Bytes - -static BL_RST_REASON_E s_rst_reason = BL_RST_POWER_OFF; - -static char *RST_REASON_ARRAY[] = { - "BL_RST_POWER_OFF", - "BL_RST_HARDWARE_WATCHDOG", - "BL_RST_FATAL_EXCEPTION", - "BL_RST_SOFTWARE_WATCHDOG", - "BL_RST_SOFTWARE" -}; -extern volatile bool sys_log_all_enable;//XXX in debug.c - -BL_RST_REASON_E bl_sys_rstinfo_get(void) -{ - BL_RST_REASON_E ret = s_rst_reason; - - s_rst_reason = REASON_POWEROFF; - - return ret; -} - -int bl_sys_rstinfo_set(BL_RST_REASON_E val) -{ - if (val == BL_RST_SOFTWARE_WATCHDOG) { - RST_REASON = REASON_WDT; - } else if (val == BL_RST_SOFTWARE) { - RST_REASON = REASON_SOFTWARE; - } - - return 0; -} - -void bl_sys_rstinfo_init(void) -{ - if (RST_REASON == REASON_WDT) { - s_rst_reason = BL_RST_SOFTWARE_WATCHDOG; - } else if (RST_REASON == REASON_SOFTWARE) { - s_rst_reason = BL_RST_SOFTWARE; - } else { - s_rst_reason = BL_RST_POWER_OFF; - } - - bl_sys_rstinfo_set(BL_RST_SOFTWARE_WATCHDOG); -} - -int bl_sys_rstinfo_getsting(char *info) -{ - memcpy(info, (char *)RST_REASON_ARRAY[s_rst_reason], strlen(RST_REASON_ARRAY[s_rst_reason])); - *(info + strlen(RST_REASON_ARRAY[s_rst_reason])) = '\0'; - return 0; -} - -int bl_sys_logall_enable(void) -{ - sys_log_all_enable = true; - return 0; -} - -int bl_sys_logall_disable(void) -{ - sys_log_all_enable = false; - return 0; -} - -void bl_sys_mfg_config(void) -{ -#if 0 - union _reg_t { - uint8_t byte[4]; - uint32_t word; - } mfg = { - .byte = MFG_CONFIG_VAL, - }; - - *(volatile uint32_t*)(MFG_CONFIG_REG) = mfg.word; -#else - puts("WARN: bl_sys_mfg_config is NOT implemented\r\n"); -#endif -} - -int bl_sys_reset_por(void) -{ -#if 0 - bl_sys_rstinfo_set(BL_RST_SOFTWARE); - __disable_irq(); - GLB_SW_POR_Reset(); - while (1) { - /*empty dead loop*/ - } - - return 0; -#else - puts("WARN: bl_sys_rstinfo_set is NOT implemented\r\n"); - __disable_irq(); - GLB_SW_POR_Reset(); - while (1) { - /*empty dead loop*/ - } - - return 0; -#endif -} - -void bl_sys_reset_system(void) -{ - __disable_irq(); - GLB_SW_System_Reset(); - while (1) { - /*empty dead loop*/ - } -} - - -int bl_sys_em_config(void) -{ -#if 0 - extern uint8_t __LD_CONFIG_EM_SEL; - volatile uint32_t em_size; - - em_size = (uint32_t)&__LD_CONFIG_EM_SEL; - - switch (em_size) { - case 0 * 1024: - { - GLB_Set_EM_Sel(GLB_EM_0KB); - } - break; - case 8 * 1024: - { - GLB_Set_EM_Sel(GLB_EM_8KB); - } - break; - case 16 * 1024: - { - GLB_Set_EM_Sel(GLB_EM_16KB); - } - break; - default: - { - /*nothing here*/ - } - } - - return 0; -#else - puts("WARN: bl_sys_em_config is NOT implemented\r\n"); - return 0; -#endif -} - -int bl_sys_early_init(void) -{ -#if 0 - extern BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg); - HBN_Aon_Pad_IeSmt_Cfg(1); - - extern void freertos_risc_v_trap_handler(void); //freertos_riscv_ram/portable/GCC/RISC-V/portASM.S - write_csr(mtvec, &freertos_risc_v_trap_handler); - - /* reset here for use wtd first then init hwtimer later*/ - GLB_AHB_Slave1_Reset(BL_AHB_SLAVE1_TMR); - /*debuger may NOT ready don't print anything*/ - return 0; -#else - puts("WARN: bl_sys_early_init is NOT implemented\r\n"); - return 0; -#endif -} - -int bl_sys_init(void) -{ - bl_sys_em_config(); - bl_sys_rstinfo_get(); - bl_sys_rstinfo_init(); - return 0; -} - -int bl_sys_isxipaddr(uint32_t addr) -{ - //XXX is 0xD000_0000 Address Range is really used - if ( ((addr & 0xFF000000) == 0x58000000) || ((addr & 0xFF000000) == 0x5C000000) || - ((addr & 0xFF000000) == 0xD8000000) || ((addr & 0xFF000000) == 0xDC000000)) { - return 1; - } - return 0; -} - -void bl_enable_cpu0(void) -{ - PDS_Power_On_MM_System(); -} - -void bl_boot_cpu0(uint32_t start_addr) -{ - GLB_Halt_CPU(GLB_CORE_ID_D0); - GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, start_addr); - GLB_Release_CPU(GLB_CORE_ID_D0); -} - -void bl_halt_cpu0(void) -{ - GLB_Halt_CPU(GLB_CORE_ID_D0); -} - -void bl_release_cpu0(void) -{ - GLB_Release_CPU(GLB_CORE_ID_D0); -} - -void bl_sys_enabe_jtag(int cpuid) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.pullType = GPIO_PULL_NONE; - - gpio_cfg.gpioMode = GPIO_MODE_AF; - gpio_cfg.gpioFun = GPIO_FUN_JTAG_D0; - switch (cpuid) { - case 0: - { - } - break; - case 1: - { - puts("Enable CPU1 (D0/C906) on PIN6/PIN7/PIN12/PIN13\r\n"); - gpio_cfg.gpioPin = GLB_GPIO_PIN_6; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_7; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_12; - GLB_GPIO_Init(&gpio_cfg); - - gpio_cfg.gpioPin = GLB_GPIO_PIN_13; - GLB_GPIO_Init(&gpio_cfg); - } - break; - default: - { - } - break; - } -} - -static void bl_sys_reduce_mcu2ext(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_WORD(MCU_MISC_BASE + MCU_MISC_MCU_BUS_CFG1_OFFSET); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_X_WTHRE_MCU2EXT, 3); - BL_WR_WORD(MCU_MISC_BASE + MCU_MISC_MCU_BUS_CFG1_OFFSET, tmpVal); -} - -void bl_sys_lowlevel_init(void) -{ - bl_sys_reduce_mcu2ext(); - // blog_init(); - bl_irq_init(); - bl_flash_init(); - hal_boot2_init(); - hal_board_cfg(0); -#ifndef NO_BLE_CONFIG - GLB_Set_EM_Sel(GLB_WRAM96KB_EM64KB); -#endif -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.h deleted file mode 100644 index 4fc3430a2f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_sys.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_SYS_H__ -#define __BL_SYS_H__ - -#include - -typedef enum { - BL_RST_POWER_OFF = 0, - BL_RST_HARDWARE_WATCHDOG, - BL_RST_FATAL_EXCEPTION, - BL_RST_SOFTWARE_WATCHDOG, - BL_RST_SOFTWARE, -} BL_RST_REASON_E; - -BL_RST_REASON_E bl_sys_rstinfo_get(void); -int bl_sys_rstinfo_set(BL_RST_REASON_E val); -int bl_sys_rstinfo_getsting(char *info); -void bl_sys_rstinfo_init(void); -int bl_sys_logall_enable(void); -int bl_sys_logall_disable(void); -void bl_sys_mfg_config(void); -int bl_sys_reset_por(void); -void bl_sys_reset_system(void); -int bl_sys_isxipaddr(uint32_t addr); -int bl_sys_early_init(void); -int bl_sys_init(void); -void bl_enable_cpu0(void); -void bl_boot_cpu0(uint32_t start_addr); -void bl_halt_cpu0(void); -void bl_release_cpu0(void); -void bl_sys_enabe_jtag(int cpuid); -void bl_sys_lowlevel_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.c deleted file mode 100644 index 80012c4c46..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.c +++ /dev/null @@ -1,132 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_timer.h" -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include -#include - -uint32_t bl_timer_now_us(void) -{ - return xTaskGetTickCount() * 1000000 / configTICK_RATE_HZ; -} - -uint32_t bl_system_core_clock_get(GLB_CORE_ID_Type core) -{ - uint32_t clockVal = 0; - - switch (core) { - case GLB_CORE_ID_M0: - clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); - break; - case GLB_CORE_ID_D0: - clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK); - break; - case GLB_CORE_ID_LP: - clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK); - break; - default: - clockVal = 0; - break; - } - clockVal = clockVal ? clockVal : (32 * 1000 * 1000); - - return clockVal; -} - -BL_Err_Type bl_cpu_set_core_mtimer_clk(GLB_CORE_ID_Type core, uint8_t enable, uint16_t div) -{ - uint32_t tmpVal = 0; - uint32_t address = 0; - - CHECK_PARAM((div <= 0x3FF)); - - switch (core) { - case GLB_CORE_ID_M0: - address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET; - break; - case GLB_CORE_ID_D0: - address = MM_MISC_BASE + MM_MISC_CPU_RTC_OFFSET; - break; - case GLB_CORE_ID_LP: - address = PDS_BASE + PDS_CPU_CORE_CFG8_OFFSET; - break; - default: - address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET; - break; - } - - /* disable rtc first */ - /* MCU RTC_EN is [31] */ - /* DSP RTC_EN is [31] */ - /* LP RTC_EN is [31] */ - tmpVal = BL_RD_WORD(address); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - BL_WR_WORD(address, tmpVal); - - /* set div */ - /* MCU RTC_DIV is [9:0] */ - /* DSP RTC_DIV is [9:0] */ - /* LP RTC_DIV is [9:0] */ - tmpVal = BL_RD_WORD(address); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div); - BL_WR_WORD(address, tmpVal); - - /* enable or not */ - /* MCU RTC_EN is [31] */ - /* DSP RTC_EN is [31] */ - /* LP RTC_EN is [31] */ - tmpVal = BL_RD_WORD(address); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } - BL_WR_WORD(address, tmpVal); - - return SUCCESS; -} - -void bl_mtimer_c906_clock_init(void) -{ - uint32_t clockVal = 0; - clockVal = bl_system_core_clock_get(GLB_CORE_ID_D0); - - /* Set MTimer clock source 10M */ - bl_cpu_set_core_mtimer_clk(GLB_CORE_ID_D0, 1, (clockVal / 1000 / 1000 / 10) - 1); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.h deleted file mode 100644 index 2ea2756d01..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_timer.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_TIMER_H__ -#define __BL_TIMER_H__ -#include -uint32_t bl_timer_now_us(void); -void bl_mtimer_c906_clock_init(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.c deleted file mode 100644 index da0b7c2cd2..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.c +++ /dev/null @@ -1,552 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#include -#elif defined(BL606P) -#include -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl_uart.h" -#include "bl_irq.h" - -#ifdef BFLB_USE_HAL_DRIVER -void UART0_IRQHandler(void); -void UART1_IRQHandler(void); -void UART2_IRQHandler(void); -void UART3_IRQHandler(void); -#endif - -//TODO Do in std driver -#define UART_NUMBER_SUPPORTED 4 -#define UART_FIFO_TX_CNT (32) -#define FIFO_TX_SIZE_BURST (32) -static const uint32_t uartAddr[4] = {UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE}; - -typedef struct bl_uart_notify { - cb_uart_notify_t rx_cb; - void *rx_cb_arg; - - cb_uart_notify_t tx_cb; - void *tx_cb_arg; -} bl_uart_notify_t; - -static bl_uart_notify_t g_uart_notify_arg[UART_NUMBER_SUPPORTED]; - - -static void uart_init_demo(uint8_t id) -{ - static UART_CFG_Type uartCfg = { - 80*1000*1000, /* UART clock */ - 2000000, /* UART Baudrate */ - UART_DATABITS_8, /* UART data bits length */ - UART_STOPBITS_1, /* UART data stop bits length */ - UART_PARITY_NONE, /* UART no parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - DISABLE, /* Disable tx output SW control mode */ - DISABLE, /* Disable tx lin mode */ - DISABLE, /* Disable rx lin mode */ - 0, /* Tx break bit count for lin mode */ - UART_LSB_FIRST /* UART each data byte is send out LSB-first */ - }; - - /* Disable all interrupt */ - UART_IntMask(id, UART_INT_ALL,MASK); - - /* Disable uart before config */ - UART_Disable(id, UART_TXRX); - - /* UART init */ - UART_Init(id, &uartCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* Enable uart */ - UART_Enable(id, UART_TXRX); -} - -static int uart_signal_get(uint8_t pin) -{ - //TODO no magic number is allowed here - if (pin >= 12 && pin <=23) { - return (pin + 6) % 12; - } else if (pin >= 36 && pin <=45) { - return (pin + 6) % 12; - } - return (pin % 12); -} - -static int uart_func_get(uint8_t id, GLB_UART_SIG_FUN_Type uartfunc) -{ - switch (id) { - case 0: - return uartfunc; - case 1: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - case 2: - return (GLB_UART_SIG_FUN_UART1_RTS - GLB_UART_SIG_FUN_UART0_RTS) * 1 + uartfunc; - default: - /*empty here*/ - //TODO should assert here? - return uartfunc; - } -} - -static void uart_gpio_demo(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - uint8_t uart_func, uart_sig; - - //FIXME SWAP set is NOT put here - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 1); - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1); - - //common GPIO cfg - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.gpioMode = GPIO_MODE_AF; - gpio_cfg.pullType = GPIO_PULL_UP; - gpio_cfg.gpioFun = GPIO_FUN_UART; - //cfg for UART Tx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + tx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_TXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - //cfg for UART Rx - gpio_cfg.gpioPin = GLB_GPIO_PIN_0 + rx_pin; - uart_func = uart_func_get(id, GLB_UART_SIG_FUN_UART0_RXD); - uart_sig = uart_signal_get(gpio_cfg.gpioPin); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_sig, (GLB_UART_SIG_FUN_Type)uart_func); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)uart_func, (GLB_UART_SIG_FUN_Type)uart_sig); - GLB_GPIO_Init(&gpio_cfg); - - //Enable UART clock - GLB_Set_UART_CLK(1, 0, 0); -} - -int bl_uart_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin, uint32_t baudrate) -{ - UART_CFG_Type uart_dbg_cfg = { - // 32 * 1000 * 1000, /*UART clock*/ - 80*1000*1000, /*UART clock from XTAL*/ - 2000000, /* baudrate */ - UART_DATABITS_8, /* data bits */ - UART_STOPBITS_1, /* stop bits */ - UART_PARITY_NONE, /* parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - DISABLE, /* Disable tx output SW control mode */ - DISABLE, /* Disable tx lin mode */ - DISABLE, /* Disable rx lin mode */ - 0, /* Tx break bit count for lin mode */ - UART_LSB_FIRST, /* UART each data byte is send out LSB-first */ - }; - - UART_FifoCfg_Type fifoCfg = { - 16, /* TX FIFO threshold */ - 16, /* RX FIFO threshold */ - DISABLE, /* Disable tx dma req/ack interface */ - DISABLE /* Disable rx dma req/ack interface */ - }; - - /* init debug uart gpio first */ - uart_gpio_demo(id, tx_pin, rx_pin, cts_pin, rts_pin); - uart_init_demo(id); - - /* disable all interrupt */ - UART_IntMask(id, UART_INT_ALL, MASK); - - /* disable uart before config */ - UART_Disable(id, UART_TXRX); - - /* uart init with default configuration */ - UART_Init(id, &uart_dbg_cfg); - - /* UART fifo configuration */ - UART_FifoConfig(id, &fifoCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* Set rx time-out value */ - UART_SetRxTimeoutValue(id, 80); - - /* enable uart */ - UART_AutoBaudDetection(id, 0); - UART_Enable(id, UART_TXRX); - - return 0; -} - -/*This function is NOT thread safe*/ -int bl_uart_data_send(uint8_t id, uint8_t data) -{ - -// UART_SendData(id, &data,1); - uint32_t UARTx = uartAddr[id]; - - /* Wait for FIFO */ - while (UART_GetTxFifoCount(id) == 0) { - } - - BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data); - - return 0; -} - -int bl_uart_data_recv(uint8_t id) -{ - int ret; - uint32_t UARTx = uartAddr[id]; - - /* Receive data */ - if (UART_GetRxFifoCount(id) > 0) { - ret = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET); - } else { - ret = -1; - } - - return ret; -} - -int bl_uart_int_rx_enable(uint8_t id) -{ - UART_SetRxTimeoutValue((UART_ID_Type)id, 24); - UART_IntMask((UART_ID_Type)id, UART_INT_RX_FIFO_REQ, UNMASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RX_END, UNMASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RTO, UNMASK); - return 0; -} - -int bl_uart_int_rx_disable(uint8_t id) -{ - UART_IntMask((UART_ID_Type)id, UART_INT_RX_FIFO_REQ, MASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RX_END, MASK); - UART_IntMask((UART_ID_Type)id, UART_INT_RTO, MASK); - return 0; -} - -int bl_uart_int_tx_enable(uint8_t id) -{ - UART_IntMask((UART_ID_Type)id, UART_INT_TX_FIFO_REQ, UNMASK); - return 0; -} - -int bl_uart_int_tx_disable(uint8_t id) -{ - UART_IntMask((UART_ID_Type)id, UART_INT_TX_FIFO_REQ, MASK); - return 0; -} - -int bl_uart_flush(uint8_t id) -{ - /* Wait for FIFO */ - while (UART_FIFO_TX_CNT != UART_GetTxFifoCount(id)) { - } - - return 0; -} - -void bl_uart_getdefconfig(uint8_t id, uint8_t *parity) -{ - if (NULL == parity) { - return; - } - - //*baudrate = 115200;/* not support set no baud */ - *parity = (uint8_t)UART_PARITY_NONE; -} - -void bl_uart_setbaud(uint8_t id, uint32_t baud) -{ - //FIXME - puts("uart is NOT implemented\r\n"); - while (1) { - } -} - -int bl_uart_int_enable(uint8_t id) -{ - switch (id) { - case 0: - { - bl_uart_int_rx_enable(0); - // bl_uart_int_tx_enable(0); - bl_irq_register(UART0_IRQn, UART0_IRQHandler); - bl_irq_enable(UART0_IRQn); - } - break; - case 1: - { - bl_uart_int_rx_enable(1); - // bl_uart_int_tx_enable(1); - bl_irq_register(UART1_IRQn, UART1_IRQHandler); - bl_irq_enable(UART1_IRQn); - } - break; - case 2: - { - bl_uart_int_rx_enable(2); - // bl_uart_int_tx_enable(2); - bl_irq_register(UART2_IRQn, UART2_IRQHandler); - bl_irq_enable(UART2_IRQn); - } - break; - case 3: - { - bl_uart_int_rx_enable(3); - // bl_uart_int_tx_enable(3); - bl_irq_register(UART3_IRQn, UART3_IRQHandler); - bl_irq_enable(UART3_IRQn); - } - break; - default: - { - return -1; - } - } - - return 0; -} - -int bl_uart_int_disable(uint8_t id) -{ - switch (id) { - case 0: - { - bl_uart_int_rx_disable(0); - bl_uart_int_tx_disable(0); - bl_irq_unregister(UART0_IRQn, UART0_IRQHandler); - bl_irq_disable(UART0_IRQn); - } - break; - case 1: - { - bl_uart_int_rx_disable(1); - bl_uart_int_tx_disable(1); - bl_irq_unregister(UART1_IRQn, UART1_IRQHandler); - bl_irq_disable(UART1_IRQn); - } - break; - case 2: - { - bl_uart_int_rx_disable(2); - bl_uart_int_tx_disable(2); - bl_irq_unregister(UART2_IRQn, UART2_IRQHandler); - bl_irq_disable(UART2_IRQn); - } - break; - case 3: - { - bl_uart_int_rx_disable(3); - bl_uart_int_tx_disable(3); - bl_irq_unregister(UART3_IRQn, UART3_IRQHandler); - bl_irq_disable(UART3_IRQn); - } - break; - default: - { - return -1; - } - } - - return 0; -} - -int bl_uart_int_rx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - - g_uart_notify_arg[id].rx_cb = cb; - g_uart_notify_arg[id].rx_cb_arg = arg; - - return 0; -} - -int bl_uart_int_tx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - - g_uart_notify_arg[id].tx_cb = cb; - g_uart_notify_arg[id].tx_cb_arg = arg; - - return 0; -} - -int bl_uart_int_rx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - g_uart_notify_arg[id].rx_cb = NULL; - g_uart_notify_arg[id].rx_cb_arg = NULL; - - return 0; -} - -int bl_uart_int_tx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg) -{ - if (!(id < UART_NUMBER_SUPPORTED)) { - /*UART ID overflow*/ - return -1; - } - g_uart_notify_arg[id].tx_cb = NULL; - g_uart_notify_arg[id].tx_cb_arg = NULL; - - return 0; -} - -static inline void uart_generic_notify_handler(uint8_t id) -{ - cb_uart_notify_t cb; - void *arg; - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[id]; - - tmpVal = BL_RD_REG(UARTx,UART_INT_STS); - maskVal = BL_RD_REG(UARTx,UART_INT_MASK); - - /* Length of uart tx data transfer arrived interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_END_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x1); - } - - /* Length of uart rx data transfer arrived interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_END_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x2); - - /*Receive Data ready*/ - cb = g_uart_notify_arg[id].rx_cb; - arg = g_uart_notify_arg[id].rx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FRDY_MASK)){ - /* Transmit data request interrupt */ - cb = g_uart_notify_arg[id].tx_cb; - arg = g_uart_notify_arg[id].tx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FRDY_MASK)){ - /*Receive Data ready*/ - - cb = g_uart_notify_arg[id].rx_cb; - arg = g_uart_notify_arg[id].rx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal,UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_RTO_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x10); - - /*Receive Data ready*/ - cb = g_uart_notify_arg[id].rx_cb; - arg = g_uart_notify_arg[id].rx_cb_arg; - - if (cb) { - /*notify up layer*/ - cb(arg); - } - } - - /* Rx parity check error interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_PCE_MASK)){ - BL_WR_REG(UARTx,UART_INT_CLEAR,0x20); - } - - /* Tx fifo overflow/underflow error interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_UTX_FER_MASK)){ - } - - /* Rx fifo overflow/underflow error interrupt */ - if(BL_IS_REG_BIT_SET(tmpVal,UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal,UART_CR_URX_FER_MASK)){ - } - - return; -} - -#ifdef BFLB_USE_HAL_DRIVER -void UART0_IRQHandler(void) -{ - uart_generic_notify_handler(0); -} - -void UART1_IRQHandler(void) -{ - uart_generic_notify_handler(1); -} - -void UART2_IRQHandler(void) -{ - uart_generic_notify_handler(2); -} - -void UART3_IRQHandler(void) -{ - uart_generic_notify_handler(3); -} -#endif - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.h deleted file mode 100644 index 909ba99e73..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_uart.h +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_UART_H__ -#define __BL_UART_H__ -#include -#define BL_UART_BUFFER_SIZE_MIN (128) -#define BL_UART_BUFFER_SIZE_MASK (128 - 1) - -typedef void (*cb_uart_notify_t)(void *arg); -int bl_uart_gpio_init(uint8_t id, uint8_t tx, uint8_t rx, uint8_t rts, uint8_t cts, int baudrate); -int bl_uart_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin, uint32_t baudrate); -int bl_uart_simple_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin, uint32_t baudrate); -int bl_uart_debug_early_init(uint32_t baudrate); -int bl_uart_early_init(uint8_t id, uint8_t tx_pin, uint32_t baudrate); - -int bl_uart_int_rx_enable(uint8_t id); -int bl_uart_int_rx_disable(uint8_t id); -int bl_uart_int_tx_enable(uint8_t id); -int bl_uart_int_tx_disable(uint8_t id); -int bl_uart_string_send(uint8_t id, char *data); -int bl_uart_flush(uint8_t id); -void bl_uart_getdefconfig(uint8_t id, uint8_t *parity); -//FIXME fix bl_uart_setconfig -//void bl_uart_setconfig(uint8_t id, uint32_t baudrate, UART_Parity_Type parity); -void bl_uart_setbaud(uint8_t id, uint32_t baud); -int bl_uart_data_send(uint8_t id, uint8_t data); -int bl_uart_datas_send(uint8_t id, uint8_t *data, int len); -int bl_uart_data_recv(uint8_t id); -int bl_uart_int_enable(uint8_t id); -int bl_uart_int_disable(uint8_t id); -int bl_uart_int_rx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg); -int bl_uart_int_tx_notify_register(uint8_t id, cb_uart_notify_t cb, void *arg); -int bl_uart_int_rx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg); -int bl_uart_int_tx_notify_unregister(uint8_t id, cb_uart_notify_t cb, void *arg); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.c deleted file mode 100644 index 8625934d5d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.c +++ /dev/null @@ -1,322 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include -#include -#include "bl_usb_cam.h" - -#define VIDEO_IN_EP 0x81 - -#ifdef CONFIG_USB_HS -#define MAX_PAYLOAD_SIZE 1024 -#else -#define MAX_PAYLOAD_SIZE 1023 -#endif -#define VIDEO_PACKET_SIZE (unsigned int)(((MAX_PAYLOAD_SIZE / 1)) | (0x00 << 11)) - -#define WIDTH (unsigned int)(800) -#define HEIGHT (unsigned int)(600) - -#define CAM_FPS (30) -#define INTERVAL (unsigned long)(10000000 / CAM_FPS) -#define MIN_BIT_RATE (unsigned long)(WIDTH * HEIGHT * 16 * CAM_FPS) //16 bit -#define MAX_BIT_RATE (unsigned long)(WIDTH * HEIGHT * 16 * CAM_FPS) -#define MAX_FRAME_SIZE (unsigned long)(WIDTH * HEIGHT * 2) - -#define USB_VIDEO_DESC_SIZ (unsigned long)(9 + \ - 8 + \ - 9 + \ - 13 + \ - 18 + \ - 9 + \ - 12 + \ - 9 + \ - 14 + \ - 11 + \ - 38 + \ - 9 + \ - 7) - -#define VC_TERMINAL_SIZ (unsigned int)(13 + 18 + 12 + 9) -#define VS_HEADER_SIZ (unsigned int)(13 + 1 + 11 + 38) - -#define USBD_VID 0xffff -#define USBD_PID 0xffff -#define USBD_MAX_POWER 100 -#define USBD_LANGID_STRING 1033 -#define TASK_MAIN_PRIORITY 20 -#define PER_FRAME_MJPEG 100*1024 -#define USB_MAX_BUFFER 120*1024 -#define MJPEG_DEFAULT_ADDR 0x80400000 //if mjpeg no init mjpeg addr reg default value - -const uint8_t video_descriptor[] = { - USB_DEVICE_DESCRIPTOR_INIT(USB_2_0, 0x00, 0x00, 0x00, USBD_VID, USBD_PID, 0x0001, 0x01), - USB_CONFIG_DESCRIPTOR_INIT(USB_VIDEO_DESC_SIZ, 0x02, 0x01, USB_CONFIG_BUS_POWERED, USBD_MAX_POWER), - VIDEO_VC_DESCRIPTOR_INIT(0x00, 0, 0x0100, VC_TERMINAL_SIZ, 48000000, 0x02), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x00, 0x00), - VIDEO_VS_HEADER_DESCRIPTOR_INIT(0x01, VS_HEADER_SIZ, VIDEO_IN_EP, 1, 0x00), - VIDEO_VS_FORMAT_MJPEG_DESCRIPTOR_INIT(0x01, 0x01), - VIDEO_VS_FRAME_MJPEG_DESCRIPTOR_INIT(0x01, WIDTH, HEIGHT, MIN_BIT_RATE, MAX_BIT_RATE, MAX_FRAME_SIZE, INTERVAL, 0x00, DBVAL(INTERVAL), DBVAL(INTERVAL), DBVAL(0)), - VIDEO_VS_DESCRIPTOR_INIT(0x01, 0x01, 0x01), - /* 1.2.2.2 Standard VideoStream Isochronous Video Data Endpoint Descriptor */ - 0x07, /* bLength */ - USB_DESCRIPTOR_TYPE_ENDPOINT, /* bDescriptorType: ENDPOINT */ - 0x81, /* bEndpointAddress: IN endpoint 2 */ - 0x01, /* bmAttributes: Isochronous transfer type. Asynchronous synchronization type. */ - WBVAL(VIDEO_PACKET_SIZE), /* wMaxPacketSize */ - 0x01, /* bInterval: One frame interval */ - - /////////////////////////////////////// - /// string0 descriptor - /////////////////////////////////////// - USB_LANGID_INIT(USBD_LANGID_STRING), - /////////////////////////////////////// - /// string1 descriptor - /////////////////////////////////////// - 0x12, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'B', 0x00, /* wcChar0 */ - 'o', 0x00, /* wcChar1 */ - 'u', 0x00, /* wcChar2 */ - 'f', 0x00, /* wcChar3 */ - 'f', 0x00, /* wcChar4 */ - 'a', 0x00, /* wcChar5 */ - 'l', 0x00, /* wcChar6 */ - 'o', 0x00, /* wcChar7 */ - /////////////////////////////////////// - /// string2 descriptor - /////////////////////////////////////// - 0x28, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - 'B', 0x00, /* wcChar0 */ - 'o', 0x00, /* wcChar1 */ - 'u', 0x00, /* wcChar2 */ - 'f', 0x00, /* wcChar3 */ - 'f', 0x00, /* wcChar4 */ - 'a', 0x00, /* wcChar5 */ - 'l', 0x00, /* wcChar6 */ - 'o', 0x00, /* wcChar7 */ - ' ', 0x00, /* wcChar8 */ - 'V', 0x00, /* wcChar9 */ - 'E', 0x00, /* wcChar10 */ - 'D', 0x00, /* wcChar11 */ - 'I', 0x00, /* wcChar12 */ - 'O', 0x00, /* wcChar13 */ - ' ', 0x00, /* wcChar14 */ - 'D', 0x00, /* wcChar15 */ - 'E', 0x00, /* wcChar16 */ - 'M', 0x00, /* wcChar17 */ - 'O', 0x00, /* wcChar18 */ - /////////////////////////////////////// - /// string3 descriptor - /////////////////////////////////////// - 0x16, /* bLength */ - USB_DESCRIPTOR_TYPE_STRING, /* bDescriptorType */ - '2', 0x00, /* wcChar0 */ - '0', 0x00, /* wcChar1 */ - '2', 0x00, /* wcChar2 */ - '1', 0x00, /* wcChar3 */ - '0', 0x00, /* wcChar4 */ - '3', 0x00, /* wcChar5 */ - '1', 0x00, /* wcChar6 */ - '0', 0x00, /* wcChar7 */ - '0', 0x00, /* wcChar8 */ - '0', 0x00, /* wcChar9 */ -#ifdef CONFIG_USB_HS - /////////////////////////////////////// - /// device qualifier descriptor - /////////////////////////////////////// - 0x0a, - USB_DESCRIPTOR_TYPE_DEVICE_QUALIFIER, - 0x00, - 0x02, - 0x00, - 0x00, - 0x00, - 0x40, - 0x01, - 0x00, -#endif - 0x00 -}; - -static usbd_class_t video_class; -static usbd_interface_t video_control_intf; -static usbd_interface_t video_stream_intf; -#if defined NO_PSRAM_HEAP -#define CUSTOMER_SECTION __attribute__((section(".custom_psram_bss"))) -static uint8_t usb_buffer[USB_MAX_BUFFER] CUSTOMER_SECTION; -static uint8_t mjpeg_swap_buffer[PER_FRAME_MJPEG] CUSTOMER_SECTION; -#else -static uint8_t *usb_buffer = NULL; -static uint8_t *mjpeg_swap_buffer = NULL; -#endif -static uint32_t mjpeg_start_addr, mjpeg_buffer_size; -SemaphoreHandle_t usb_cam_semap = NULL; - -void usbd_video_iso_callback(uint8_t ep) -{ - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - if (usb_cam_semap) { - xSemaphoreGiveFromISR(usb_cam_semap, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - } -} - -static usbd_endpoint_t video_in_ep = { - .ep_cb = usbd_video_iso_callback, - .ep_addr = VIDEO_IN_EP -}; - -volatile bool tx_flag = 0; - -void usbd_video_open(uint8_t intf) -{ - tx_flag = 1; - printf("OPEN\r\n"); -} -void usbd_video_close(uint8_t intf) -{ - printf("CLOSE\r\n"); - tx_flag = 0; -} - -static void bl_usb_clock_init(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpVal |= (1 << 13); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); - GLB_Set_USB_CLK_From_WIFIPLL(1); -} - -int bl_usb_cam_init(void) -{ - int ret = 0; - - ret = bl_cam_mjpeg_buffer_info_get(&mjpeg_start_addr, &mjpeg_buffer_size); - if (ret != 0) { - printf("mjpeg not init\r\n"); - goto exit; - } - - usb_cam_semap = xSemaphoreCreateBinary(); - if (NULL == usb_cam_semap) { - printf("create usb_cam_semap fail\r\n"); - ret = -1; - goto exit; - } - -#ifndef NO_PSRAM_HEAP - usb_buffer = pvPortMalloc(USB_MAX_BUFFER); - if (NULL == usb_buffer) { - printf("malloc usb_buffer fail!\r\n"); - vSemaphoreDelete(usb_cam_semap); - usb_cam_semap = NULL; - ret = -1; - goto exit; - } - - mjpeg_swap_buffer = pvPortMalloc(PER_FRAME_MJPEG); - if (NULL == mjpeg_swap_buffer) { - printf("malloc mjpeg_swap_buffer fail!\r\n"); - vPortFree(usb_buffer); - usb_buffer = NULL; - vSemaphoreDelete(usb_cam_semap); - usb_cam_semap = NULL; - ret = -1; - goto exit; - } -#endif - bl_usb_clock_init(); - usbd_desc_register(video_descriptor); - usbd_video_add_interface(&video_class, &video_control_intf); - usbd_video_add_interface(&video_class, &video_stream_intf); - usbd_interface_add_endpoint(&video_stream_intf, &video_in_ep); - - usbd_video_probe_and_commit_controls_init(CAM_FPS, MAX_FRAME_SIZE, MAX_PAYLOAD_SIZE); - usbd_initialize(); - - xSemaphoreGive(usb_cam_semap); -exit: - return ret; -} - -int bl_usb_cam_transfer(void) -{ - int ret = 0; - uint8_t *pic, *usb_ptr; - uint32_t len, first_len, second_len, out_len; - - if (tx_flag) { - ret = bl_cam_mjpeg_get(&pic, &len); - if (ret == 0) { - if (((uint32_t)(uintptr_t)pic + len) > (mjpeg_start_addr + mjpeg_buffer_size)) { - /* if mjpeg store edge loop to start*/ - first_len = mjpeg_start_addr + mjpeg_buffer_size - (uint32_t)(uintptr_t)pic; - second_len = len - first_len; - csi_dcache_invalid_range((void *)pic, first_len); - memcpy(mjpeg_swap_buffer, pic, first_len); - csi_dcache_invalid_range((void *)mjpeg_start_addr, second_len); - memcpy(mjpeg_swap_buffer + first_len, (void *)mjpeg_start_addr, second_len); - usb_ptr = mjpeg_swap_buffer; - } else { - /*mjpeg data not cut*/ - usb_ptr = pic; - csi_dcache_invalid_range((void *)usb_ptr, len); - } - - if (NULL == usb_cam_semap) { - ret = -1; - goto exit; - } - if (len > USB_MAX_BUFFER) { - ret = -1; - printf("jpeg frame size is out of %dbytes\r\n", USB_MAX_BUFFER); - goto exit; - } - xSemaphoreTake(usb_cam_semap, portMAX_DELAY); - /*fill mjpeg in usb data struct*/ - usbd_video_mjpeg_payload_fill(usb_ptr, len, usb_buffer, &out_len); - bl_cam_mjpeg_pop(); - - /* send usb data async*/ - usbd_ep_write_async(VIDEO_IN_EP, usb_buffer, out_len); - } - } - -exit: - return ret; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.h deleted file mode 100644 index d03df4ae90..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_usb_cam.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_USB_CAM_H__ -#define __BL_USB_CAM_H__ -#include -int bl_usb_cam_init(void); -int bl_usb_cam_transfer(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.c deleted file mode 100644 index 1e031ae52a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.c +++ /dev/null @@ -1,255 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl_wifi.h" -#include "bl_irq.h" - -typedef struct _bl_wifi_env { - uint8_t sta_mac_addr_board[6]; - uint8_t sta_mac_addr_usr[6]; - uint8_t ap_mac_addr_board[6]; - uint8_t ap_mac_addr_usr[6]; - uint8_t country_code; - - bl_wifi_ap_info_t ap_info; - uint8_t ap_info_en; - - bl_wifi_ap_info_t sta_info; - uint8_t sta_info_en; -} bl_wifi_env_t; - -bl_wifi_env_t wifi_env = { - .sta_mac_addr_board = {0x18, 0xb9, 0x05, 0x88, 0x88, 0x88} -}; - - -/****************************************************************************/ /** - * @brief set wifi core clock divider - * - * @param clkDiv: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -/* 0x3B0 : wifi_cfg0 */ -#define GLB_WIFI_CFG0_OFFSET (0x3B0) -#define GLB_WIFI_MAC_CORE_DIV GLB_WIFI_MAC_CORE_DIV -#define GLB_WIFI_MAC_CORE_DIV_POS (0U) -#define GLB_WIFI_MAC_CORE_DIV_LEN (4U) -#define GLB_WIFI_MAC_CORE_DIV_MSK (((1U<hwaddr[0] = 0x18; - netif->hwaddr[1] = 0xB9; - netif->hwaddr[2] = 0x05; - netif->hwaddr[3] = 0x88; - netif->hwaddr[4] = 0x88; - netif->hwaddr[5] = 0x88; - - /* - netif_add(struct netif *netif, struct ip_addr *ipaddr, - * struct ip_addr *netmask, struct ip_addr *gw, - * void *state, err_t (* init)(struct netif *netif), - * err_t (* input)(struct pbuf *p, struct netif *netif)) - * - * Adds your network interface to the netif_list. Allocate a struct - * netif and pass a pointer to this structure as the first argument. - * Give pointers to cleared ip_addr structures when using DHCP, - * or fill them with sane numbers otherwise. The state pointer may be NULL. - * - * The init function pointer must point to a initialization function for - * your ethernet netif interface. The following code illustrates it's use.*/ - - netif_add(netif, &ipaddr, &netmask, &gw, NULL, &bl606a0_wifi_netif_init, &tcpip_input); - netif->name[0] = 's'; - netif->name[1] = 't'; - netif->flags |= NETIF_FLAG_LINK_UP; - netif_set_default(netif); - netif_set_up(netif); - netifapi_dhcp_start(netif); - - return 0; -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.h deleted file mode 100644 index 17c3b4a45d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/bl_wifi.h +++ /dev/null @@ -1,52 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __BL_WIFI_H__ -#define __BL_WIFI_H__ -typedef struct bl_wifi_ap_info { - uint8_t ssid[33]; - uint8_t psk[65]; - uint8_t chan; -} bl_wifi_ap_info_t; - - -int bl_wifi_enable_irq(void); -int bl_wifi_clock_enable(void); -int bl_wifi_sta_mac_addr_set(uint8_t mac[6]); -int bl_wifi_ap_mac_addr_set(uint8_t mac[6]); -int bl_wifi_mac_addr_set(uint8_t mac[6]); -int bl_wifi_country_code_set(uint8_t country_code); -int bl_wifi_ap_info_set(uint8_t* ssid, uint8_t ssid_len, - uint8_t* psk, uint8_t psk_len, - uint8_t chan); -int bl_wifi_mac_addr_get(uint8_t mac[6]); -int bl_wifi_ap_info_get(bl_wifi_ap_info_t* ap_info); -int bl_wifi_sta_info_set(uint8_t* ssid, uint8_t ssid_len, uint8_t* psk, uint8_t psk_len, int autoconnect); -int bl_wifi_sta_info_get(bl_wifi_ap_info_t* sta_info); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/emac_phy.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/emac_phy.c deleted file mode 100644 index 9cbe9791d1..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/emac_phy.c +++ /dev/null @@ -1,30 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "phy_8720.c" diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernet_phy.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernet_phy.h deleted file mode 100644 index a155e1e0de..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernet_phy.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __ETHERNET_PHY_H__ -#define __ETHERNET_PHY_H__ - -#include "hal_emac.h" - -typedef enum emac_phy_status { - EMAC_PHY_STAT_EEROR, - EMAC_PHY_STAT_LINK_DOWN, - EMAC_PHY_STAT_LINK_INIT, - EMAC_PHY_STAT_LINK_UP, - EMAC_PHY_STAT_100MBITS_FULLDUPLEX, - EMAC_PHY_STAT_100MBITS_HALFDUPLEX, - EMAC_PHY_STAT_10MBITS_FULLDUPLEX, - EMAC_PHY_STAT_10MBITS_HALFDUPLEX, -} emac_phy_status_t; - -emac_phy_status_t ethernet_phy_status_get(); -int emac_phy_init(emac_phy_cfg_t *cfg); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.c deleted file mode 100644 index c2135e56f5..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.c +++ /dev/null @@ -1,574 +0,0 @@ -/* - * Copyright (c) 2020 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -/* Includes ------------------------------------------------------------------*/ -#include "lwip/opt.h" -#include "lwip/timeouts.h" -#include "lwip/netif.h" -#define LWIP_DHCP 0 -#if LWIP_DHCP -#include "lwip/dhcp.h" -#endif -#include "netif/etharp.h" -#include "ethernetif.h" -#include -#include "hal_emac.h" -#include -#include "semphr.h" -#include "bflb_platform.h" -/* Private typedef -----------------------------------------------------------*/ -/* Private define ------------------------------------------------------------*/ -/* Network interface name */ -#define IFNAME0 'b' -#define IFNAME1 'l' - -#define ETH_DMA_TRANSMIT_TIMEOUT (20U) - -#define BL702_EMAC 0 -#define EMAC_OUTPUT BL702_EMAC - -#if LWIP_DHCP -#define MAX_DHCP_TRIES 4 -uint32_t DHCPfineTimer = 0; -uint8_t DHCP_state = DHCP_OFF; -#else -/*Static IP ADDRESS: IP_ADDR0.IP_ADDR1.IP_ADDR2.IP_ADDR3 */ -#define IP_ADDR0 (uint8_t)10 -#define IP_ADDR1 (uint8_t)28 -#define IP_ADDR2 (uint8_t)30 -#define IP_ADDR3 (uint8_t)221 - -/*NETMASK*/ -#define NETMASK_ADDR0 (uint8_t)255 -#define NETMASK_ADDR1 (uint8_t)255 -#define NETMASK_ADDR2 (uint8_t)255 -#define NETMASK_ADDR3 (uint8_t)0 - -/*Gateway Address*/ -#define GW_ADDR0 (uint8_t)10 -#define GW_ADDR1 (uint8_t)28 -#define GW_ADDR2 (uint8_t)30 -#define GW_ADDR3 (uint8_t)1 -#endif - -/* Private function prototypes -----------------------------------------------*/ -void pbuf_free_custom(struct pbuf *p); -void ethernetif_input(void *argument); -SemaphoreHandle_t emac_rx_sem = NULL; -static StackType_t emac_rx_stack[256]; -static StaticTask_t emac_rx_handle; -#if LWIP_DHCP -static StackType_t emac_dhcp_stack[256]; -static StaticTask_t emac_dhcp_handle; -#endif -static uint8_t emac_rx_buffer[ETH_RX_BUFFER_SIZE] __attribute__((aligned(16))) = { 0 }; - -LWIP_MEMPOOL_DECLARE(RX_POOL, 10, sizeof(struct pbuf_custom), "Zero-copy RX PBUF pool"); - -/* Private functions ---------------------------------------------------------*/ -/******************************************************************************* - LL Driver Interface ( LwIP stack --> ETH) -*******************************************************************************/ -/** - * @brief In this function, the hardware should be initialized. - * Called from ethernetif_init(). - * - * @param netif the already initialized lwip network interface structure - * for this ethernetif - */ -extern void emac_init_txrx_buffer(void); -extern int emac_phy_init(emac_phy_cfg_t *cfg); - -/* For emac tx and rx,we put here to make controlling it's size easy */ -#define ETH_RXBUFNB 5 -#define ETH_TXBUFNB 5 -#define ATTR_NOCACHE_RAM_SECTION __attribute__((section(".nocache_ram"))) -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethRxBuff[ETH_RXBUFNB][ETH_RX_BUFFER_SIZE] ATTR_EALIGN(4) = { 0 }; /* Ethernet Receive Buffers */ -ATTR_NOCACHE_RAM_SECTION ATTR_EALIGN(4) uint8_t ethTxBuff[ETH_TXBUFNB][ETH_TX_BUFFER_SIZE] ATTR_EALIGN(4); /* Ethernet Transmit Buffers */ -void emac_init_txrx_buffer(void) -{ - emac_bd_init((uint8_t *)ethTxBuff, ETH_TXBUFNB, (uint8_t *)ethRxBuff, ETH_RXBUFNB); - -} -void dhcp_thread(void const *argument); -void low_level_init(struct netif *netif) -{ - int ret = 0; - - emac_device_t emac_cfg = { - .mac_addr[0] = 0x18, - .mac_addr[1] = 0xB9, - .mac_addr[2] = 0x05, - .mac_addr[3] = 0x12, - .mac_addr[4] = 0x34, - .mac_addr[5] = 0x56, - }; - - /* set phy cfg */ - emac_phy_cfg_t phy_cfg = { - .auto_negotiation = 1, /*!< Speed and mode auto negotiation */ - .full_duplex = 0, /*!< Duplex mode */ - .speed = 0, /*!< Speed mode */ - .phy_address = 1, /*!< PHY address */ - .phy_id = 0x7c0f0, /*!< PHY OUI, masked */ - .phy_state = PHY_STATE_DOWN, - }; - - /* set MAC hardware address length */ - netif->hwaddr_len = ETH_HWADDR_LEN; - - /* set MAC hardware address */ - netif->hwaddr[0] = emac_cfg.mac_addr[0]; - netif->hwaddr[1] = emac_cfg.mac_addr[1]; - netif->hwaddr[2] = emac_cfg.mac_addr[2]; - netif->hwaddr[3] = emac_cfg.mac_addr[3]; - netif->hwaddr[4] = emac_cfg.mac_addr[4]; - netif->hwaddr[5] = emac_cfg.mac_addr[5]; - - /* maximum transfer unit */ - netif->mtu = 1500; - - /* emac init,configure ethernet peripheral (GPIOs, clocks, MAC, DMA) */ - MSG("emac_init\r\n"); - emac_init(&emac_cfg); - - ret = emac_phy_init(&phy_cfg); - if (PHY_STATE_UP == phy_cfg.phy_state) { - MSG("PHY[%x] @%d ready on %dMbps, %s duplex\n\r", (int)phy_cfg.phy_id, (int)phy_cfg.phy_address, - (int)phy_cfg.speed, - phy_cfg.full_duplex ? "full" : "half"); - } else { - MSG("PHY Init fail\n\r"); - BL_CASE_FAIL; - while (1) - ; - } - emac_init_txrx_buffer(); - emac_start(); - // emac_start_tx(); - - /* device capabilities */ - /* don't set NETIF_FLAG_ETHARP if this device is not an ethernet one */ - netif->flags |= NETIF_FLAG_BROADCAST | NETIF_FLAG_ETHARP; - - /* Initialize the RX POOL */ - LWIP_MEMPOOL_INIT(RX_POOL); - - /* create a binary semaphore used for informing ethernetif of frame reception */ - //vSemaphoreCreateBinary(emac_rx_sem); - emac_rx_sem = xSemaphoreCreateBinary(); - - /* create the task that handles the ETH_MAC */ - MSG("[OS] Starting emac rx task...\r\n"); - xTaskCreateStatic(ethernetif_input, (char *)"emac_rx_task", sizeof(emac_rx_stack) / 4, netif, 16, emac_rx_stack, &emac_rx_handle); -#if LWIP_DHCP - MSG("[OS] Starting emac dhcp task...\r\n"); - xTaskCreateStatic(dhcp_thread, (char *)"emac_dhcp_task", sizeof(emac_dhcp_stack) / 4, netif, 16, emac_dhcp_stack, &emac_dhcp_handle); -#endif - - if (ret == 0) { - MSG("[OS] %s Netif is up\r\n", netif->name); - netif_set_up(netif); - netif_set_link_up(netif); - } -} - -void emac_tx_error_callback_app() -{ - MSG("EMAC tx error callback\r\n"); -} - -void emac_rx_error_callback_app() -{ - MSG("EMAC rx error callback\r\n"); - // MSG("EMAC tx bd num 0x%x\r\n", BL_RD_WORD(0x4000D020)); - // MSG("EMAC rx bd description0 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8))); - // MSG("EMAC rx bd description1 0x%x\r\n", BL_RD_WORD(0x4000D400 + ((5 + 5) * 8) + 0x4)); -} -/** - * @brief This function should do the actual transmission of the packet. The packet is - * contained in the pbuf that is passed to the function. This pbuf - * might be chained. - * - * @param netif the lwip network interface structure for this ethernetif - * @param p the MAC packet to send (e.g. IP packet including MAC addresses and type) - * @return ERR_OK if the packet could be sent - * an err_t value if the packet couldn't be sent - * - * @note Returning ERR_MEM here if a DMA queue of your MAC is full can lead to - * strange results. You might consider waiting for space in the DMA queue - * to become available since the stack doesn't retry to send a packet - * dropped because of memory failure (except for the TCP timers). - */ - -static unsigned char emac_send_buf[1514]; -static err_t low_level_output(struct netif *netif, struct pbuf *p) -{ - err_t errval = ERR_OK; - struct pbuf *q; - - if (!emac_bd_fragment_support()){ - - uint32_t byteslefttocopy = 0; - // uint32_t payloadoffset = 0; - // uint32_t bufferoffset = 0; - uint32_t framelength = 0; - uint32_t flags = (EMAC_NORMAL_PACKET); - - for (q = p; q != NULL; q = q->next) { - // MSG("p->tot_len:%d,q->len:%d, q->next:%d,f:%d\r\n", q->tot_len, q->len, q->next, framelength); - - byteslefttocopy = q->len; - // payloadoffset = 0; - - // check is copy data is larger than emac tx buf - while ((byteslefttocopy + framelength) > ETH_TX_BUFFER_SIZE) { - // copy data to tx buf - MSG("tx buf is too larger!\r\n"); - flags = EMAC_FRAGMENT_PACKET; - // ARCH_MemCpy_Fast(&emac_send_buf[framelength + bufferoffset], q->payload + payloadoffset, (ETH_TX_BUFFER_SIZE - bufferoffset)); - } - ARCH_MemCpy_Fast(&emac_send_buf[framelength], q->payload, byteslefttocopy); - // bufferoffset = bufferoffset + byteslefttocopy; - framelength = framelength + byteslefttocopy; - } - - if (0 != emac_bd_tx_enqueue(flags, framelength, emac_send_buf)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - - }else{ - for (q = p; q != NULL; q = q->next) { - //MSG("p->tot_len:%d,q->len:%d, q->next:%d\r\n", q->tot_len, q->len, q->next); - if (q->len == q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_NORMAL_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else if (q->len < q->tot_len) { - if (0 != emac_bd_tx_enqueue(EMAC_FRAGMENT_PACKET, q->len, q->payload)) { - MSG("emac_bd_tx_enqueue error!\r\n"); - return ERR_IF; - } - } else { - MSG("low_level_output error! Wrong packet!\r\n"); - } - } - } - - return errval; -} - -/** - * @brief Should allocate a pbuf and transfer the bytes of the incoming - * packet from the interface into the pbuf. - * - * @param netif the lwip network interface structure for this ethernetif - * @return a pbuf filled with the received packet (including MAC header) - * NULL on memory error - */ -static struct pbuf *low_level_input(struct netif *netif) -{ - uint32_t rx_len = 0; - struct pbuf *p = NULL, *q; - - emac_bd_rx_dequeue(-1, &rx_len, emac_rx_buffer); - - if (rx_len <= 0) { - //MSG("Recv Null Data\r\n"); - return NULL; - } - - //MSG("Recv full Data\r\n"); - - p = pbuf_alloc(PBUF_RAW, rx_len, PBUF_POOL); - - if (p != NULL) { - for (q = p; q != NULL; q = q->next) { - memcpy(q->payload, emac_rx_buffer + rx_len - q->tot_len, q->len); - } - } - - return p; -} - -void emac_rx_done_callback_app(void) -{ - BaseType_t xHigherPriorityTaskWoken; - - /* Is it time for vATask() to run? */ - xHigherPriorityTaskWoken = pdFALSE; - //MSG("emac_rx_done_callback_app\r\n"); - //low_level_input(NULL); - xSemaphoreGiveFromISR(emac_rx_sem, &xHigherPriorityTaskWoken); - /* If xHigherPriorityTaskWoken was set to true you - we should yield. The actual macro used here is - port specific. */ - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -} -/** - * @brief This function is the ethernetif_input task, it is processed when a packet - * is ready to be read from the interface. It uses the function low_level_input() - * that should handle the actual reception of bytes from the network - * interface. Then the type of the received packet is determined and - * the appropriate input function is called. - * - * @param netif the lwip network interface structure for this ethernetif - */ -void ethernetif_input(void *argument) -{ - struct pbuf *p = NULL; - struct netif *netif = (struct netif *)argument; - - for (;;) { - if (xSemaphoreTake(emac_rx_sem, portMAX_DELAY) == pdTRUE) { - do { - //MSG("ethernetif_input\r\n"); - p = low_level_input(netif); - - if (p != NULL) { - if (netif->input(p, netif) != ERR_OK) { - pbuf_free(p); - } - } - } while (p != NULL); - } - } -} - -/** - * @brief Should be called at the beginning of the program to set up the - * network interface. It calls the function low_level_init() to do the - * actual setup of the hardware. - * - * This function should be passed as a parameter to netif_add(). - * - * @param netif the lwip network interface structure for this ethernetif - * @return ERR_OK if the loopif is initialized - * ERR_MEM if private data couldn't be allocated - * any other err_t on error - */ -err_t ethernetif_init(struct netif *netif) -{ - LWIP_ASSERT("netif != NULL", (netif != NULL)); - -#if LWIP_NETIF_HOSTNAME - /* Initialize interface hostname */ - netif->hostname = "lwip"; -#endif /* LWIP_NETIF_HOSTNAME */ - - netif->name[0] = IFNAME0; - netif->name[1] = IFNAME1; - /* We directly use etharp_output() here to save a function call. - * You can instead declare your own function an call etharp_output() - * from it if you have to do some checks before sending (e.g. if link - * is available...) */ - netif->output = etharp_output; - netif->linkoutput = low_level_output; - - /* initialize the hardware */ - low_level_init(netif); - - return ERR_OK; -} - -/** - * @brief Custom Rx pbuf free callback - * @param pbuf: pbuf to be freed - * @retval None - */ -void pbuf_free_custom(struct pbuf *p) -{ - struct pbuf_custom *custom_pbuf = (struct pbuf_custom *)p; - LWIP_MEMPOOL_FREE(RX_POOL, custom_pbuf); -} - -static void ethernet_set_static_ip(struct netif *netif) -{ - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - - IP4_ADDR(&ipaddr, IP_ADDR0, IP_ADDR1, IP_ADDR2, IP_ADDR3); - IP4_ADDR(&netmask, NETMASK_ADDR0, NETMASK_ADDR1, NETMASK_ADDR2, NETMASK_ADDR3); - IP4_ADDR(&gw, GW_ADDR0, GW_ADDR1, GW_ADDR2, GW_ADDR3); - netif_set_addr(netif, ip_2_ip4(&ipaddr), ip_2_ip4(&netmask), ip_2_ip4(&gw)); -} - -/** - * @brief Notify the User about the network interface config status - * @param netif: the network interface - * @retval None - */ -void ethernet_link_status_updated(struct netif *netif) -{ - if (netif_is_link_up(netif)) { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_START; - MSG("DHCP Start\n"); -#else - /* IP address default setting */ - ethernet_set_static_ip(netif); - uint8_t iptxt[20]; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("Static IP address: %s\n", iptxt); -#endif - } else { -#if LWIP_DHCP - /* Update DHCP state machine */ - DHCP_state = DHCP_LINK_DOWN; -#else - MSG("The network cable is not connected \n"); -#endif /* LWIP_DHCP */ - } -} - -/** - * @brief - * @retval None - */ -void ethernet_link_check_state(struct netif *netif) -{ - emac_phy_status_t phy_state; - - uint32_t linkchanged = 0; - // uint32_t speed = 0, duplex = 0; - - phy_state = ethernet_phy_status_get(); - - if (netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Link Down\n"); - emac_stop(); - netif_set_down(netif); - netif_set_link_down(netif); - } else if (!netif_is_link_up(netif) && (phy_state <= EMAC_PHY_STAT_LINK_DOWN)) { - MSG("Reinit\n"); - emac_phy_init(NULL); - } else if (!netif_is_link_up(netif) && (phy_state > EMAC_PHY_STAT_LINK_UP)) { - // switch (phy_state) { - // case EMAC_PHY_STAT_100MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_100MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 100; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_FULLDUPLEX: - // duplex = 1; - // speed = 10; - // linkchanged = 1; - // break; - - // case EMAC_PHY_STAT_10MBITS_HALFDUPLEX: - // duplex = 0; - // speed = 10; - // linkchanged = 1; - // break; - - // default: - // break; - // } - - if (linkchanged) { - /* Get MAC Config MAC */ - //HAL_ETH_GetMACConfig(&EthHandle, &MACConf); - //MACConf.DuplexMode = duplex; - //MACConf.Speed = speed; - //HAL_ETH_SetMACConfig(&EthHandle, &MACConf); - //HAL_ETH_Start(&EthHandle); - netif_set_up(netif); - netif_set_link_up(netif); - } - } -} - -#if LWIP_DHCP -/** - * @brief DHCP Process - * @param argument: network interface - * @retval None - */ -void dhcp_thread(void const *argument) -{ - struct netif *netif = (struct netif *)argument; - ip_addr_t ipaddr; - ip_addr_t netmask; - ip_addr_t gw; - struct dhcp *dhcp; - uint8_t iptxt[20]; - - for (;;) { - switch (DHCP_state) { - case DHCP_START: { - ip_addr_set_zero_ip4(&netif->ip_addr); - ip_addr_set_zero_ip4(&netif->netmask); - ip_addr_set_zero_ip4(&netif->gw); - DHCP_state = DHCP_WAIT_ADDRESS; - MSG(" State: Looking for DHCP server ...\n"); - dhcp_start(netif); - } break; - case DHCP_WAIT_ADDRESS: { - if (dhcp_supplied_address(netif)) { - DHCP_state = DHCP_ADDRESS_ASSIGNED; - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("IP address assigned by a DHCP server: %s\n", iptxt); - } else { - dhcp = (struct dhcp *)netif_get_client_data(netif, LWIP_NETIF_CLIENT_DATA_INDEX_DHCP); - - /* DHCP timeout */ - if (dhcp->tries > MAX_DHCP_TRIES) { - DHCP_state = DHCP_TIMEOUT; - - /* Static address used */ - ethernet_set_static_ip(netif); - sprintf((char *)iptxt, "%s", ip4addr_ntoa(netif_ip4_addr(netif))); - MSG("DHCP Timeout !! \n"); - MSG("Static IP address: %s\n", iptxt); - } - } - } break; - case DHCP_LINK_DOWN: { - DHCP_state = DHCP_OFF; - MSG("The network cable is not connected \n"); - } break; - default: - break; - } - vTaskDelay(100); - } -} -#endif /* LWIP_DHCP */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.h deleted file mode 100644 index 8b21d0b9eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/ethernetif.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * Copyright (c) 2020 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __ETHERNETIF_H__ -#define __ETHERNETIF_H__ - -#include "lwip/err.h" -#include "lwip/netif.h" -#include "ethernet_phy.h" - -#define DHCP_OFF (uint8_t)0 -#define DHCP_START (uint8_t)1 -#define DHCP_WAIT_ADDRESS (uint8_t)2 -#define DHCP_ADDRESS_ASSIGNED (uint8_t)3 -#define DHCP_TIMEOUT (uint8_t)4 -#define DHCP_LINK_DOWN (uint8_t)5 - -/* Exported types ------------------------------------------------------------*/ -err_t ethernetif_init(struct netif *netif); -void ethernet_link_check_state(struct netif *netif); -void ethernet_link_status_updated(struct netif *netif); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.c deleted file mode 100644 index 5640d84252..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.c +++ /dev/null @@ -1,1273 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include -#include - -#include - -#include -BLOG_DECLARE(dts); -#include - -#define USER_UNUSED(a) ((void)(a)) - -#define BL_FDT32_TO_U8(addr, byte_offset) ((uint8_t)fdt32_to_cpu(*(uint32_t *)((uint8_t *)addr + byte_offset))) -#define BL_FDT32_TO_U16(addr, byte_offset) ((uint16_t)fdt32_to_cpu(*(uint32_t *)((uint8_t *)addr + byte_offset))) -#define BL_FDT32_TO_U32(addr, byte_offset) ((uint32_t)fdt32_to_cpu(*(uint32_t *)((uint8_t *)addr + byte_offset))) - -static uint32_t factory_addr = 0; - -//#ifndef FEATURE_WIFI_DISABLE -//#include -//#include - -#ifdef CFG_BLE_ENABLE -#include "ble_lib_api.h" -#endif -static int update_mac_config_get_mac_from_dtb(const void *fdt, int offset1, uint8_t mac_addr[6]) -{ - int lentmp; - const uint8_t *addr_prop = 0; - - /* set sta_mac_addr ap_mac_addr */ - addr_prop = fdt_getprop(fdt, offset1, "sta_mac_addr", &lentmp); - if (6 == lentmp) { - - memcpy(mac_addr, addr_prop, 6); - blog_info("sta_mac_addr :\r\n"); - blog_buf(mac_addr, 6); - - bl_wifi_sta_mac_addr_set(mac_addr); - } else { - blog_error("sta_mac_addr NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "ap_mac_addr", &lentmp); - if (6 == lentmp) { - - memcpy(mac_addr, addr_prop, 6); - blog_info("ap_mac_addr :\r\n"); - blog_buf(mac_addr, 6); - - bl_wifi_ap_mac_addr_set(mac_addr); - } else { - blog_error("ap_mac_addr NULL.\r\n"); - return -1; - } - blog_info("return 0000 \r\n"); - - return 0; -} - -static int update_mac_config_get_mac_from_efuse(uint8_t mac_addr[6]) -{ - uint8_t result_or, result_and; - - bl_efuse_read_mac(mac_addr); - result_or = mac_addr[0] | mac_addr[1] | mac_addr[2] | mac_addr[3] | mac_addr[4] | mac_addr[5]; - result_and = mac_addr[0] & mac_addr[1] & mac_addr[2] & mac_addr[3] & mac_addr[4] & mac_addr[5]; - - if (0 == result_or || 1 == result_and) { - /*all zero or one found in efuse*/ - return -1; - } - return 0; -} - -static int update_mac_config_get_mac_from_factory(uint8_t mac_addr[6]) -{ - uint8_t result_or, result_and; - - if (bl_efuse_read_mac_factory(mac_addr)) { - return -1; - } - result_or = mac_addr[0] | mac_addr[1] | mac_addr[2] | mac_addr[3] | mac_addr[4] | mac_addr[5]; - result_and = mac_addr[0] & mac_addr[1] & mac_addr[2] & mac_addr[3] & mac_addr[4] & mac_addr[5]; - if (0 == result_or || 1 == result_and) { - /*all zero or one found in efuse*/ - return -1; - } - return 0; -} - -/* - * Update MAC address according to order string - * BFM: - * 'B' for EFUSE built-in MAC address - * 'F' for Flash built-in MAC address - * 'M' for manufacutre configured EFUSE built-in MAC address - * */ -#define MAC_ORDER_ADDR_LEN_MAX (3) -static void update_mac_config_with_order(const void *fdt, int offset1, const char *order) -{ - int i, set, len; - uint8_t mac_addr[6]; - static const uint8_t mac_default[] = {0x18, 0xB9, 0x05, 0x88, 0x88, 0x88}; - - set = 0; - len = strlen(order); - for (i = 0; i < MAC_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (order[i]) { - case 'B': - { - if (0 == update_mac_config_get_mac_from_efuse(mac_addr)) { - set = 1; - blog_info("get MAC from B ready\r\n"); - goto break_scan; - } else { - blog_info("get MAC from B failed\r\n"); - } - } - break; - case 'F': - { - if (0 == update_mac_config_get_mac_from_dtb(fdt, offset1, mac_addr)) { - set = 1; - printf("get MAC from F ready\r\n"); - goto break_scan; - } else { - printf("get MAC from F failed\r\n"); - } - } - break; - case 'M': - { - if (0 == update_mac_config_get_mac_from_factory(mac_addr)) { - set = 1; - blog_info("get MAC from M ready\r\n"); - goto break_scan; - } else { - blog_info("get MAC from M failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default MAC address\r\n"); - memcpy(mac_addr, mac_default, 6); - } - //FIXME maybe we should set a different MAC address - blog_info("Set MAC addrress %02X:%02X:%02X:%02X:%02X:%02X\r\n", - mac_addr[0], - mac_addr[1], - mac_addr[2], - mac_addr[3], - mac_addr[4], - mac_addr[5] - ); - bl_wifi_ap_mac_addr_set(mac_addr); - bl_wifi_sta_mac_addr_set(mac_addr); -} - -static void update_mac_config(const void *fdt, int offset1) -{ - int countindex = 0, lentmp = 0; - const char *result = 0; - char mac_mode[4]; - - countindex = fdt_stringlist_count(fdt, offset1, "mode"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "mode", 0, &lentmp); - blog_info_user(dts, "MAC address mode length %d\r\n", lentmp); - if (lentmp <= MAC_ORDER_ADDR_LEN_MAX) { - memcpy(mac_mode, result, lentmp); - mac_mode[3] = '\0'; - blog_info_user(dts, "MAC address mode is %s\r\n", mac_mode); - update_mac_config_with_order(fdt, offset1, mac_mode); - } - } -} - - -static int update_xtal_config_get_mac_from_factory(uint32_t capcode[5]) -{ - uint8_t capcode_efuse = 0; - - if (bl_efuse_read_capcode(&capcode_efuse)) { - return -1; - } - /*efuse only have one capcode entry, so we fill the left with hardcode*/ - capcode[0] = capcode_efuse; - capcode[1] = capcode_efuse; - capcode[2] = 1; - capcode[3] = 60; - capcode[4] = 60; - - return 0; -} - -static int update_xtal_config_get_mac_from_dtb(const void *fdt, int offset1, uint32_t capcode[5]) -{ - const uint8_t *addr_prop = 0; - int lentmp = 0; - - addr_prop = fdt_getprop(fdt, offset1, "xtal", &lentmp); - - if (5*4 == lentmp) { - blog_info( - "xtal dtb in DEC :%u %u %u %u %u\r\n", - BL_FDT32_TO_U8(addr_prop, 4*0), - BL_FDT32_TO_U8(addr_prop, 4*1), - BL_FDT32_TO_U8(addr_prop, 4*2), - BL_FDT32_TO_U8(addr_prop, 4*3), - BL_FDT32_TO_U8(addr_prop, 4*4) - ); - capcode[0] = BL_FDT32_TO_U8(addr_prop, 4*0); - capcode[1] = BL_FDT32_TO_U8(addr_prop, 4*1); - capcode[2] = BL_FDT32_TO_U8(addr_prop, 4*2); - capcode[3] = BL_FDT32_TO_U8(addr_prop, 4*3); - capcode[4] = BL_FDT32_TO_U8(addr_prop, 4*4); - } else { - blog_error("xtal dtb NULL."); - return -1; - } - return 0; -} - -#define XTAL_ORDER_ADDR_LEN_MAX (2) -static void update_xtal_config_with_order(const void *fdt, int offset1, const char *order) -{ - int i, set, len; - uint32_t capcode[5]; - - set = 0; - len = strlen(order); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (order[i]) { - case 'F': - { - if (0 == update_xtal_config_get_mac_from_dtb(fdt, offset1, capcode)) { - set = 1; - blog_info("get xtal from F ready\r\n"); - goto break_scan; - } else { - blog_info("get xtal from F failed\r\n"); - } - } - break; - case 'M': - { - if (0 == update_xtal_config_get_mac_from_factory(capcode)) { - set = 1; - blog_info("get xtal from M ready\r\n"); - goto break_scan; - } else { - blog_info("get xtal from M failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default xtal\r\n"); - capcode[0] = 50; - capcode[1] = 50; - capcode[2] = 1; - capcode[3] = 60; - capcode[4] = 60; - } - hal_sys_capcode_update(capcode[0], capcode[1]); -} - -static void update_xtal_config(const void *fdt, int offset1) -{ - int lentmp = 0, countindex; - char xtal_mode[3]; - const char *result = 0; - - countindex = fdt_stringlist_count(fdt, offset1, "xtal_mode"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "xtal_mode", 0, &lentmp); - blog_info("xtal_mode length %d\r\n", lentmp); - if (lentmp <= XTAL_ORDER_ADDR_LEN_MAX) { - memcpy(xtal_mode, result, lentmp); - xtal_mode[sizeof(xtal_mode) - 1] = '\0'; - blog_info("xtal_mode is %s\r\n", xtal_mode); - update_xtal_config_with_order(fdt, offset1, xtal_mode); - } - } -} -#if 0 -static void update_xtal_config_rftv(uint32_t tlv_addr) -{ - int i, set, len; - uint8_t buffer[20] = {0}; - uint32_t capcode[5] = {0}; - char xtal_mode[3] = {0}; - - if (rftlv_get(tlv_addr, RFTLV_API_TYPE_XTAL_MODE, 3, xtal_mode) > 0) { - xtal_mode[sizeof(xtal_mode) - 1] = '\0'; - blog_info("xtal_mode is %s\r\n", xtal_mode); - } - - set = 0; - len = strlen(xtal_mode); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (xtal_mode[i]) { - case 'F': - { - if (rftlv_get(tlv_addr, RFTLV_API_TYPE_XTAL, sizeof(buffer), buffer) > 0) { - capcode[0] = *(uint32_t *)buffer; - capcode[1] = *(uint32_t *)(buffer + 4); - capcode[2] = *(uint32_t *)(buffer + 8); - capcode[3] = *(uint32_t *)(buffer + 12); - capcode[4] = *(uint32_t *)(buffer + 16); - set = 1; - blog_info("get xtal from F ready %d %d %d %d %d\r\n", - capcode[0], - capcode[1], - capcode[2], - capcode[3], - capcode[4]); - goto break_scan; - } else { - blog_info("get xtal from F failed\r\n"); - } - } - break; - case 'M': - { - if (0 == update_xtal_config_get_mac_from_factory(capcode)) { - set = 1; - blog_info("get xtal from M ready %d %d %d %d %d\r\n", - capcode[0], - capcode[1], - capcode[2], - capcode[3], - capcode[4]); - goto break_scan; - } else { - blog_info("get xtal from M failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default xtal\r\n"); - capcode[0] = 50; - capcode[1] = 50; - capcode[2] = 1; - capcode[3] = 60; - capcode[4] = 60; - } - hal_sys_capcode_update(capcode[0], capcode[1]); -} -#endif -static int update_poweroffset_config_get_mac_from_dtb(const void *fdt, int offset1, int8_t poweroffset[14]) -{ - int lentmp = 0, i; - const uint8_t *addr_prop = 0; - -#define PWR_OFFSET_BASE (10) - addr_prop = fdt_getprop(fdt, offset1, "pwr_offset", &lentmp); - if (14*4 == lentmp) { - for (i = 0; i < 14; i++) { - poweroffset[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_offset from dtb:\r\n"); - blog_buf(poweroffset, 14); - for (i = 0; i < 14; i++) { - poweroffset[i] -= PWR_OFFSET_BASE; - poweroffset[i] = poweroffset[i] * 4; - } - blog_info("pwr_offset from dtb (rebase on %d):\r\n", PWR_OFFSET_BASE); - //TODO FIXME log buffer - //blog_buf_int8(poweroffset, 14); - } else { - blog_error("pwr_offset NULL. lentmp = %d\r\n", lentmp); - return -1; - } - return 0; -} - -static void update_poweroffset_config_with_order(const void *fdt, int offset1, const char *order) -{ - int i, set, len, j; - int8_t poweroffset[14], poweroffset_tmp[14]; - - memset(poweroffset, 0, sizeof(poweroffset)); - memset(poweroffset_tmp, 0, sizeof(poweroffset_tmp)); - set = 0; - len = strlen(order); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (order[i]) { - case 'B': - case 'b': - { - if (0 == bl_efuse_read_pwroft(poweroffset_tmp)) { - set = 1; - blog_info("get pwr offset from B(b) ready\r\n"); - log_buf_int8(poweroffset_tmp, sizeof(poweroffset_tmp)); - if ('B' == order[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = poweroffset_tmp[j]; - } - blog_info("Use pwr offset from B only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from b in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] += poweroffset_tmp[j]; - } - } - } else { - blog_info("get pwr offset from B(b) failed\r\n"); - } - } - break; - case 'F': - case 'f': - { - if (0 == update_poweroffset_config_get_mac_from_dtb(fdt, offset1, poweroffset_tmp)) { - set = 1; - blog_info("get pwr offset from F(f) ready\r\n"); - if ('B' == order[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = poweroffset_tmp[j]; - } - blog_info("Use pwr offset from F only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from f in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] += poweroffset_tmp[j]; - } - } - goto break_scan; - } else { - blog_info("get pwr offset from F(f) failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default pwr offset\r\n");//all zeros actually - } - log_buf_int8(poweroffset, sizeof(poweroffset)); -#ifdef CFG_BLE_ENABLE - extern void ble_rf_set_pwr_offset_table(int8_t *poweroffset_table); - ble_rf_set_pwr_offset_table(poweroffset); -#endif - //zys phy_powroffset_set(poweroffset); -} - - -#define PWR_OFFSET_ORDER_ADDR_LEN_MAX (2) -static void update_poweroffset_config(const void *fdt, int offset1) -{ - int lentmp = 0, countindex; - char pwr_mode[3]; - const char *result = 0; - - countindex = fdt_stringlist_count(fdt, offset1, "pwr_mode"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "pwr_mode", 0, &lentmp); - blog_info("pwr_mode length %d\r\n", lentmp); - if (lentmp <= PWR_OFFSET_ORDER_ADDR_LEN_MAX) { - memcpy(pwr_mode, result, lentmp); - pwr_mode[sizeof(pwr_mode) - 1] = '\0'; - blog_info("pwr_mode is %s\r\n", pwr_mode); - update_poweroffset_config_with_order(fdt, offset1, pwr_mode); - } - } -} -#if 0 -zys -static void update_poweroffset_config_rftv(uint32_t tlv_addr, const char *pw_mode) -{ - int i, set, len, j; - int8_t poweroffset[14], poweroffset_tmp[14]; - - memset(poweroffset, 0, sizeof(poweroffset)); - memset(poweroffset_tmp, 0, sizeof(poweroffset_tmp)); - set = 0; - len = strlen(pw_mode); - for (i = 0; i < XTAL_ORDER_ADDR_LEN_MAX && i < len; i++) { - switch (pw_mode[i]) { - case 'B': - case 'b': - { - if (0 == bl_efuse_read_pwroft(poweroffset_tmp)) { - set = 1; - blog_info("get pwr offset from B(b) ready\r\n"); - log_buf_int8(poweroffset_tmp, sizeof(poweroffset_tmp)); - if ('B' == pw_mode[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = poweroffset_tmp[j]; - } - blog_info("Use pwr offset from B only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from b in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] += poweroffset_tmp[j]; - } - } - } else { - blog_info("get pwr offset from B(b) failed\r\n"); - } - } - break; - case 'F': - case 'f': - { - if (rftlv_get(tlv_addr, RFTLV_TYPE_PWR_OFFSET, sizeof(poweroffset_tmp), poweroffset_tmp) > 0) { - set = 1; - blog_info("get pwr offset from F(f) ready\r\n"); - if ('F' == pw_mode[i]) { - /*non-incremental mode*/ - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = (poweroffset_tmp[j] - 10)*4; - } - blog_info("Use pwr offset from F only\r\n"); - goto break_scan; - } else { - /*incremental mode*/ - blog_info("Use pwr offset from f in incremental mode\r\n"); - for (j = 0; j < sizeof(poweroffset); j++) { - poweroffset[j] = (poweroffset_tmp[j] - 10)*4; - } - } - goto break_scan; - } else { - blog_info("get pwr offset from F(f) failed\r\n"); - } - } - break; - default: - { - BL_ASSERT(0); - } - } - } -break_scan: - if (0 == set) { - blog_info("Using Default pwr offset\r\n");//all zeros actually - } - log_buf_int8(poweroffset, sizeof(poweroffset)); -#ifdef CFG_BLE_ENABLE - extern void ble_rf_set_pwr_offset_table(int8_t *poweroffset_table); - ble_rf_set_pwr_offset_table(poweroffset); -#endif - //zys phy_powroffset_set(poweroffset); -} -#endif -static int update_sta_field(const void *fdt, int wifi_offset, const char *name) -{ - int offset1 = 0; /* subnode offset1 */ - int countindex = 0, lentmp = 0; - const char *result = 0; - const uint8_t *addr_prop = 0; - int auto_connect_enable; - - /* set ssid pwd */ - uint8_t ap_ssid[32]; - uint8_t ap_ssid_len = 0; - uint8_t ap_psk[64]; - uint8_t ap_psk_len = 0; - - offset1 = fdt_subnode_offset(fdt, wifi_offset, name); - if (offset1 > 0) { - - countindex = fdt_stringlist_count(fdt, offset1, "ssid"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "ssid", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("[STA] ap_ssid string[%d] = %s, ap_ssid_len = %d\r\n", 0, result, lentmp); - memcpy(ap_ssid, result, lentmp); - ap_ssid[lentmp] = '\0'; - ap_ssid_len = lentmp; - } - } - - countindex = fdt_stringlist_count(fdt, offset1, "pwd"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "pwd", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("[STA] ap_psk string[%d] = %s, ap_psk_len = %d\r\n", 0, result, lentmp); - memcpy(ap_psk, result, lentmp); - ap_psk[lentmp] = '\0'; - ap_psk_len = lentmp; - } - } - addr_prop = fdt_getprop(fdt, offset1, "auto_connect_enable", &lentmp); - if (addr_prop) { - blog_info("auto_connect_enable = %ld\r\n", BL_FDT32_TO_U32(addr_prop, 0)); - - auto_connect_enable = BL_FDT32_TO_U32(addr_prop, 0); - } else { - auto_connect_enable = 0; - } - - bl_wifi_sta_info_set(ap_ssid, ap_ssid_len, ap_psk, ap_psk_len, auto_connect_enable); - } - return offset1; -} - -static int update_ap_field(const void *fdt, int wifi_offset, const char *name) -{ - int offset1 = 0; /* subnode offset1 */ - int countindex = 0, lentmp = 0; - const char *result = 0; - const uint8_t *addr_prop = 0; - - /* set ssid pwd */ - uint8_t ap_ssid[32]; - uint8_t ap_ssid_len = 0; - uint8_t ap_psk[64]; - uint8_t ap_psk_len = 0; - uint8_t ap_channel = 0; - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "ap"); - if (offset1 > 0) - { - countindex = fdt_stringlist_count(fdt, offset1, "ssid"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "ssid", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("ap_ssid string[%d] = %s, ap_ssid_len = %d\r\n", 0, result, lentmp); - memcpy(ap_ssid, result, lentmp); - ap_ssid[lentmp] = '\0'; - ap_ssid_len = lentmp; - } - } - - countindex = fdt_stringlist_count(fdt, offset1, "pwd"); - if (1 == countindex) { - result = fdt_stringlist_get(fdt, offset1, "pwd", 0, &lentmp); - if ((lentmp > 0) &&(lentmp<32)) {/* !NULL */ - blog_info("ap_psk string[%d] = %s, ap_psk_len = %d\r\n", 0, result, lentmp); - memcpy(ap_psk, result, lentmp); - ap_psk[lentmp] = '\0'; - ap_psk_len = lentmp; - } - } - - addr_prop = fdt_getprop(fdt, offset1, "ap_channel", &lentmp); - if (addr_prop) { - blog_info("ap_channel = %ld\r\n", BL_FDT32_TO_U32(addr_prop, 0)); - - ap_channel = BL_FDT32_TO_U32(addr_prop, 0); - } else { - blog_error("ap_channel NULL.\r\n"); - } - - bl_wifi_ap_info_set(ap_ssid, ap_ssid_len, - ap_psk, ap_psk_len, - ap_channel); - } - return offset1; -} - -typedef struct{ - uint16_t Tchannels[5]; - int16_t Tchannel_os[5]; - int16_t Tchannel_os_low[5]; - int16_t Troom_os; - uint8_t en_tcal; - uint8_t linear_or_follow; -} tcal_param_struct; -extern tcal_param_struct* tcal_param; -enum { - E_RF_TCAL_UPDATE_PARAM = 0, -}; -void rf_pri_update_tcal_param(uint8_t operation);//FIXME -#define TCAL_PARA_CHANNELS 5 - -static int update_rf_temp_field(const void *fdt, int wifi_offset, const char *name) -{ - int lentmp, i; - int offset1 = 0; - const uint8_t *addr_prop = 0; - uint32_t tmp[TCAL_PARA_CHANNELS]; - tcal_param_struct tcal_param_tmp; - - offset1 = fdt_subnode_offset(fdt, wifi_offset, name); - if (offset1 > 0) { - addr_prop = fdt_getprop(fdt, offset1, "Troom_os", &lentmp); - if (addr_prop) { - tcal_param_tmp.Troom_os=BL_FDT32_TO_U32(addr_prop, 0)-256; - blog_info_user(dts, "Troom_os = %d, lentmp = %d\r\n", (int)tcal_param_tmp.Troom_os, lentmp); - } else { - blog_info_user(dts, "Troom_os NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "linear_or_follow", &lentmp); - if (addr_prop) { - tcal_param_tmp.linear_or_follow=BL_FDT32_TO_U32(addr_prop, 0); - blog_info_user(dts, "linear_or_follow = %d, lentmp = %d\r\n", (int)tcal_param_tmp.linear_or_follow, lentmp); - } else { - blog_info_user(dts, "linear_or_follow NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "Tchannels", &lentmp); - if (lentmp == TCAL_PARA_CHANNELS*4) { - memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4); - blog_info_user(dts, "Tchannels:"); - for (i = 0; i < TCAL_PARA_CHANNELS; i++){ - tcal_param_tmp.Tchannels[i]=fdt32_to_cpu(tmp[i]); - blog_info_user_raw(dts, "%d,", (int)tcal_param_tmp.Tchannels[i]); - } - blog_info_user_raw(dts, "\r\n"); - } else { - blog_info_user(dts, "Tchannels NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "Tchannel_os", &lentmp); - if (lentmp == TCAL_PARA_CHANNELS*4) { - memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4); - blog_info_user(dts, "Tchannel_os:"); - for (i = 0; i < TCAL_PARA_CHANNELS; i++){ - tcal_param_tmp.Tchannel_os[i]=fdt32_to_cpu(tmp[i]); - blog_info_user_raw(dts, "%d,", (int)tcal_param_tmp.Tchannel_os[i]); - } - blog_info_user_raw(dts, "\r\b"); - } else { - blog_info_user(dts, "Tchannel_os NULL.\r\n"); - return -1; - } - - addr_prop = fdt_getprop(fdt, offset1, "Tchannel_os_low", &lentmp); - if (lentmp == TCAL_PARA_CHANNELS*4) { - memcpy(tmp, addr_prop, TCAL_PARA_CHANNELS*4); - blog_info_user(dts, "Tchannel_os_low:"); - for (i = 0; i < TCAL_PARA_CHANNELS; i++){ - tcal_param_tmp.Tchannel_os_low[i]=fdt32_to_cpu(tmp[i]); - blog_info_user_raw(dts, "%d,", (int)tcal_param_tmp.Tchannel_os_low[i]); - } - blog_info_user_raw(dts, "\r\n"); - } else { - blog_info_user(dts, "Tchannel_os_low NULL.\r\n"); - return -1; - } - addr_prop = fdt_getprop(fdt, offset1, "en_tcal", &lentmp); - if (addr_prop) { - tcal_param_tmp.en_tcal=BL_FDT32_TO_U32(addr_prop, 0); - blog_info_user(dts, "en_tcal = %u, lentmp = %d\r\n", tcal_param_tmp.en_tcal, lentmp); - } else { - blog_info_user(dts, "en_tcal NULL.\r\n"); - return -1; - } - } - memcpy(tcal_param, &tcal_param_tmp, sizeof(tcal_param_tmp)); - rf_pri_update_tcal_param(E_RF_TCAL_UPDATE_PARAM); - - return 0; -} -#if 0 -static int hal_board_load_rftv_info(uint32_t rftlv_addr) -{ - int i; - uint8_t *p_buffer; - - /* set tx_pwr_tbl */ - int8_t pwr_table[24]; - - int pwr_table_ble = 0; - - if (!rftlv_valid(rftlv_addr)) { - return -2; - } - - p_buffer = pvPortMalloc(80); - if (p_buffer == NULL) { - return -1; - } - - /* set xtal */ - update_xtal_config_rftv(rftlv_addr); - - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_11B, 80, p_buffer) > 0) { - for (i = 0; i < 4; i++) { - pwr_table[i] = *(int8_t *)(p_buffer + i); - } - blog_info("pwr_table_11b :%u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3] - ); - bl_tpc_update_power_rate_11b((int8_t*)pwr_table); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_11B NULL\r\n"); - } - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_11G, 80, p_buffer) > 0) { - for (i = 0; i < 8; i++) { - pwr_table[i] = *(int8_t *)(p_buffer + i); - } - blog_info("pwr_table_11g :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - bl_tpc_update_power_rate_11g((int8_t*)pwr_table); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_11G NULL\r\n"); - } - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_11N, 80, p_buffer) > 0) { - for (i = 0; i < 8; i++) { - pwr_table[i] = *(int8_t *)(p_buffer + i); - } - blog_info("pwr_table_11n :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - bl_tpc_update_power_rate_11n((int8_t*)pwr_table); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_11N NULL\r\n"); - } - - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_MODE, 80, p_buffer) > 0) { - p_buffer[2] = '\0'; - update_poweroffset_config_rftv(rftlv_addr, (const char *)p_buffer); - } else { - blog_error("RFTLV_TYPE_PWR_MODE NULL\r\n"); - } - - if (rftlv_get(rftlv_addr, RFTLV_API_TYPE_PWR_TABLE_BLE, 80, p_buffer) > 0) { - pwr_table_ble = *(int8_t *)p_buffer; - blog_info("set pwr_table_ble = %ld in dts\r\n", pwr_table_ble); - } else { - blog_error("RFTLV_TYPE_PWR_TABLE_BLE NULL\r\n"); - } -#ifdef CFG_BLE_ENABLE - ble_controller_set_tx_pwr(pwr_table_ble); -#endif - - vPortFree(p_buffer); - - return 0; -} -#endif -//static int __try_load_rftlv() -//{ -//extern uint32_t _ld_symbol_rftlv_address; -// return hal_board_load_rftv_info((uint32_t)&_ld_symbol_rftlv_address); -//zys} - -static int hal_board_load_fdt_info(const void *dtb) -{ - const void *fdt = (const void *)dtb;/* const */ - - /* set tx_pwr_tbl */ - uint8_t pwr_table[24]; - - uint32_t channel_div_table[15]; - uint16_t channel_cnt_table[14]; - uint16_t lo_fcal_div = 0; - int pwr_table_ble = 0; - - int wifi_offset = 0, bt_offset = 0; /* subnode wifi & bluetooth */ - int offset1 = 0, offset2 = 0; /* subnode offset1 */ - const uint8_t *addr_prop = 0; - - int lentmp = 0; - int i; - - wifi_offset = fdt_subnode_offset(fdt, 0, "wifi"); - if (!(wifi_offset > 0)) { - blog_error("wifi NULL.\r\n"); - } - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "mac"); - if (offset1 > 0) { - update_mac_config(fdt, offset1); - } - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "region"); - if (offset1 > 0) { - /* set country_code */ - addr_prop = fdt_getprop(fdt, offset1, "country_code", &lentmp); - if (4 == lentmp) { - blog_info("country_code : %d\r\n", BL_FDT32_TO_U8(addr_prop, 4*0)); - - bl_wifi_country_code_set(BL_FDT32_TO_U8(addr_prop, 4*0)); - } else { - blog_error("country_code NULL.\r\n"); - } - } - -//zys if (0 == __try_load_rftlv()) { - - /* load rf from tlv successful */ -// goto __exit; -// } - - offset1 = fdt_subnode_offset(fdt, wifi_offset, "brd_rf"); - if (offset1 > 0) - { - - USER_UNUSED(lo_fcal_div); - USER_UNUSED(channel_div_table); - USER_UNUSED(channel_cnt_table); - - /* set xtal */ - //update_xtal_config(fdt, offset1); - - /* set channel_div_table, channel_cnt_table, lo_fcal_div */ - addr_prop = fdt_getprop(fdt, offset1, "channel_div_table", &lentmp); - if (15*4 == lentmp) { - for (i = 0; i < 15; i++) { - channel_div_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("channel_div_table :\r\n"); - blog_buf(channel_div_table, 15*4); - } else { - blog_error("channel_div_table NULL.\r\n"); - } - - addr_prop = fdt_getprop(fdt, offset1, "channel_cnt_table", &lentmp); - if (14*4 == lentmp) { - for (i = 0; i < 14; i++) { - channel_cnt_table[i] = BL_FDT32_TO_U16(addr_prop, 4*i); - } - blog_info("channel_cnt_table :\r\n"); - blog_buf(channel_cnt_table, 14*4); - } else { - blog_error("channel_cnt_table NULL.\r\n"); - } - - addr_prop = fdt_getprop(fdt, offset1, "lo_fcal_div", &lentmp); - if (4 == lentmp) { - lo_fcal_div = BL_FDT32_TO_U16(addr_prop, 4*0); - blog_info("lo_fcal_div : %d\r\n", lo_fcal_div); - } else { - blog_error("lo_fcal_div NULL.\r\n"); - } - - //TODO FIXME POWER - //bl60x_fw_rf_table_set(channel_div_table, channel_cnt_table, lo_fcal_div); - - USER_UNUSED(pwr_table); - addr_prop = fdt_getprop(fdt, offset1, "pwr_table_11b", &lentmp); - if (4*4 == lentmp) { - for (i = 0; i < 4; i++) { - pwr_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_table_11b :%u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3] - ); - //bl_tpc_update_power_rate_11b((int8_t*)pwr_table); - } else { - blog_error("pwr_table_11b NULL. lentmp = %d\r\n", lentmp); - } - - addr_prop = fdt_getprop(fdt, offset1, "pwr_table_11g", &lentmp); - if (8*4 == lentmp) { - for (i = 0; i < 8; i++) { - pwr_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_table_11g :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - //bl_tpc_update_power_rate_11g((int8_t*)pwr_table); - } else { - blog_error("pwr_table_11g NULL. lentmp = %d\r\n", lentmp); - } - - addr_prop = fdt_getprop(fdt, offset1, "pwr_table_11n", &lentmp); - if (8*4 == lentmp) { - for (i = 0; i < 8; i++) { - pwr_table[i] = BL_FDT32_TO_U32(addr_prop, 4*i); - } - blog_info("pwr_table_11n :%u %u %u %u %u %u %u %u\r\n", - pwr_table[0], - pwr_table[1], - pwr_table[2], - pwr_table[3], - pwr_table[4], - pwr_table[5], - pwr_table[6], - pwr_table[7] - ); - //bl_tpc_update_power_rate_11n((int8_t*)pwr_table); - } else { - blog_error("pwr_table_11n NULL. lentmp = %d\r\n", lentmp); - } - //update_poweroffset_config(fdt, offset1); - } - - bt_offset = fdt_subnode_offset(fdt, 0, "bluetooth"); - if (!(bt_offset > 0)) { - blog_error("bt NULL.\r\n"); - } - - offset2 = fdt_subnode_offset(fdt, bt_offset, "brd_rf"); - if (offset2 > 0) { - addr_prop = fdt_getprop(fdt, offset2, "pwr_table_ble", &lentmp); - if (addr_prop) { - pwr_table_ble = (int8_t)BL_FDT32_TO_U32(addr_prop, 0); - } else { - pwr_table_ble = 0; - } - blog_info("set pwr_table_ble = %ld in dts\r\n", pwr_table_ble); -#ifdef CFG_BLE_ENABLE - //ble_controller_set_tx_pwr(pwr_table_ble); -#endif - } - -//__exit: - //offset1 = update_ap_field(fdt, wifi_offset, "ap"); - //offset1 = update_sta_field(fdt, wifi_offset, "sta"); -// offset1 = update_rf_temp_field(fdt, wifi_offset, "rf_temp"); - - return 0; -} -//#endif - -#ifdef CONFIG_USER_DTS_INAPP -/* - { - model = "bl bl602 iot board"; - wifi { - #address-cells = <1>; - #size-cells = <1>; - region { - country_code = <86>; - }; - mac { - mode = "MBF"; - sta_mac_addr = [C8 43 57 82 73 40]; - ap_mac_addr = [C8 43 57 82 73 02]; - }; - ap { - ssid = "bl_test_005"; - pwd = "12345678"; - ap_channel = <11>; - auto_chan_detect = "disable"; - }; - brd_rf { - xtal_mode = "MF"; - xtal = <36 36 0 60 60>; - pwr_mode = "bf"; - pwr_table = <0x4 0x3 0x3 0xBA 0x4 0x3 0x4 0xB0 0x4 0x3 0x5 0xA7 0x3 0x3 0x0 0x9F 0x3 0x3 0x1 0x95 0x3 0x3 0x2 0x8C 0x3 0x3 0x3 0x81 0x3 0x3 0x4 0x77 0x3 0x3 0x5 0x6E 0x2 0x3 0x0 0x65 0x2 0x3 0x1 0x5B 0x2 0x3 0x2 0x52 0x2 0x3 0x3 0x48 0x2 0x3 0x4 0x3E 0x2 0x3 0x5 0x34 0x1 0x3 0x3 0xA>; - pwr_offset = <10 10 10 10 10 10 10 10 10 10 10 10 10 10>; - channel_div_table = <0x1EEC4EC4 0x1EFCB7CB 0x1F0D20D2 0x1F1D89D8 0x1F2DF2DF 0x1F3E5BE5 0x1F4EC4EC 0x1F5F2DF2 0x1F6F96F9 0x1F800000 0x1F906906 0x1FA0D20D 0x1FB13B13 0x1FD89D89 0x201F81F8>; - channel_cnt_table = <0xA78A 0xA7E3 0xA83C 0xA895 0xA8ED 0xA946 0xA99F 0xA9F8 0xAA51 0xAAAA 0xAB03 0xAB5C 0xABB5 0xAC8A>; - lo_fcal_div = <0x56B>; - }; - }; -}; -*/ -const uint8_t factory_dtb[] = {//1126 - 0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x04, 0x66, 0x00, 0x00, 0x00, 0x38, - 0x00, 0x00, 0x03, 0x98, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11, - 0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xce, - 0x00, 0x00, 0x03, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13, - 0x00, 0x00, 0x00, 0x00, 0x62, 0x6c, 0x20, 0x62, 0x6c, 0x36, 0x30, 0x32, - 0x20, 0x69, 0x6f, 0x74, 0x20, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x01, 0x77, 0x69, 0x66, 0x69, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x06, - 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, - 0x00, 0x00, 0x00, 0x15, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, - 0x72, 0x65, 0x67, 0x69, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x56, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x6d, 0x61, 0x63, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x2e, - 0x4d, 0x42, 0x46, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, - 0x00, 0x00, 0x00, 0x33, 0xc8, 0x43, 0x57, 0x82, 0x73, 0x40, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x40, - 0xc8, 0x43, 0x57, 0x82, 0x73, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x01, 0x61, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x4c, 0x62, 0x6c, 0x5f, 0x74, - 0x65, 0x73, 0x74, 0x5f, 0x30, 0x30, 0x35, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x00, 0x51, 0x31, 0x32, 0x33, 0x34, - 0x35, 0x36, 0x37, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x55, 0x00, 0x00, 0x00, 0x0b, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x60, - 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x01, 0x62, 0x72, 0x64, 0x5f, 0x72, 0x66, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x71, - 0x4d, 0x46, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x14, - 0x00, 0x00, 0x00, 0x7b, 0x00, 0x00, 0x00, 0x24, 0x00, 0x00, 0x00, 0x24, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x00, 0x3c, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x80, - 0x62, 0x66, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x01, 0x00, - 0x00, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xba, 0x00, 0x00, 0x00, 0x04, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xb0, - 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, - 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9f, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x95, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x8c, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x81, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x77, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, - 0x00, 0x00, 0x00, 0x6e, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x5b, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x48, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x3e, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, - 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x03, - 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x00, 0x93, 0x00, 0x00, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x0a, - 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x3c, - 0x00, 0x00, 0x00, 0x9e, 0x1e, 0xec, 0x4e, 0xc4, 0x1e, 0xfc, 0xb7, 0xcb, - 0x1f, 0x0d, 0x20, 0xd2, 0x1f, 0x1d, 0x89, 0xd8, 0x1f, 0x2d, 0xf2, 0xdf, - 0x1f, 0x3e, 0x5b, 0xe5, 0x1f, 0x4e, 0xc4, 0xec, 0x1f, 0x5f, 0x2d, 0xf2, - 0x1f, 0x6f, 0x96, 0xf9, 0x1f, 0x80, 0x00, 0x00, 0x1f, 0x90, 0x69, 0x06, - 0x1f, 0xa0, 0xd2, 0x0d, 0x1f, 0xb1, 0x3b, 0x13, 0x1f, 0xd8, 0x9d, 0x89, - 0x20, 0x1f, 0x81, 0xf8, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x38, - 0x00, 0x00, 0x00, 0xb0, 0x00, 0x00, 0xa7, 0x8a, 0x00, 0x00, 0xa7, 0xe3, - 0x00, 0x00, 0xa8, 0x3c, 0x00, 0x00, 0xa8, 0x95, 0x00, 0x00, 0xa8, 0xed, - 0x00, 0x00, 0xa9, 0x46, 0x00, 0x00, 0xa9, 0x9f, 0x00, 0x00, 0xa9, 0xf8, - 0x00, 0x00, 0xaa, 0x51, 0x00, 0x00, 0xaa, 0xaa, 0x00, 0x00, 0xab, 0x03, - 0x00, 0x00, 0xab, 0x5c, 0x00, 0x00, 0xab, 0xb5, 0x00, 0x00, 0xac, 0x8a, - 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xc2, - 0x00, 0x00, 0x05, 0x6b, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x09, 0x6d, 0x6f, 0x64, 0x65, - 0x6c, 0x00, 0x23, 0x61, 0x64, 0x64, 0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, - 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x23, 0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, - 0x65, 0x6c, 0x6c, 0x73, 0x00, 0x63, 0x6f, 0x75, 0x6e, 0x74, 0x72, 0x79, - 0x5f, 0x63, 0x6f, 0x64, 0x65, 0x00, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x73, - 0x74, 0x61, 0x5f, 0x6d, 0x61, 0x63, 0x5f, 0x61, 0x64, 0x64, 0x72, 0x00, - 0x61, 0x70, 0x5f, 0x6d, 0x61, 0x63, 0x5f, 0x61, 0x64, 0x64, 0x72, 0x00, - 0x73, 0x73, 0x69, 0x64, 0x00, 0x70, 0x77, 0x64, 0x00, 0x61, 0x70, 0x5f, - 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x61, 0x75, 0x74, 0x6f, - 0x5f, 0x63, 0x68, 0x61, 0x6e, 0x5f, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74, - 0x00, 0x78, 0x74, 0x61, 0x6c, 0x5f, 0x6d, 0x6f, 0x64, 0x65, 0x00, 0x78, - 0x74, 0x61, 0x6c, 0x00, 0x70, 0x77, 0x72, 0x5f, 0x6d, 0x6f, 0x64, 0x65, - 0x00, 0x70, 0x77, 0x72, 0x5f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x70, - 0x77, 0x72, 0x5f, 0x6f, 0x66, 0x66, 0x73, 0x65, 0x74, 0x00, 0x63, 0x68, - 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x64, 0x69, 0x76, 0x5f, 0x74, 0x61, - 0x62, 0x6c, 0x65, 0x00, 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x5f, - 0x63, 0x6e, 0x74, 0x5f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x6c, 0x6f, - 0x5f, 0x66, 0x63, 0x61, 0x6c, 0x5f, 0x64, 0x69, 0x76, 0x00 -}; - -#endif - -uint32_t hal_board_get_factory_addr(void) -{ - return factory_addr; -} - -int hal_board_cfg(uint8_t board_code) -{ -#ifdef CONFIG_USER_DTS_INAPP - factory_addr = (uint32_t)factory_dtb; -#else - int ret; - uint32_t size; - - USER_UNUSED(ret); - ret = hal_boot2_partition_addr_active("factory", &factory_addr, &size); - blog_info("[MAIN] [BOARD] [FLASH] addr from partition is %08x, ret is %d\r\n", (unsigned int)factory_addr, ret); - if (0 == factory_addr) { - blog_error("[MAIN] [BOARD] [FLASH] Dead loop. Reason: NO valid Param Parition found\r\n"); - while (1) { - } - } - - ret = hal_boot2_partition_bus_addr_active("factory", &factory_addr, &size); - blog_info("[MAIN] [BOARD] [XIP] addr from partition is %08x, ret is %d\r\n", (unsigned int)factory_addr, ret); - if (0 == factory_addr) { - blog_error("[MAIN] [BOARD] [XIP] Dead loop. Reason: NO valid Param Parition found\r\n"); - while (1) { - } - } -#endif - -//#ifndef FEATURE_WIFI_DISABLE - // printf("hal_board_load_fdt_info\n\r"); - hal_board_load_fdt_info((const void *)factory_addr); -//#endif - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.h deleted file mode 100644 index b9cc17502b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_board.h +++ /dev/null @@ -1,34 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_BOARD_H__ -#define __HAL_BOARD_H__ -int hal_board_cfg(uint8_t board_code); -uint32_t hal_board_get_factory_addr(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.c deleted file mode 100644 index 826ce0daf6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include "bl_boot2.h" -#include "bl_flash.h" -#include "hal_boot2.h" -#include - -#define USER_UNUSED(a) ((void)(a)) - -#define PARTITION_BOOT2_RAM_ADDR_ACTIVE (0x62047e00) -#define PARTITION_MAGIC (0x54504642) -#define PARTITION_FW_PART_NAME "FW" -#define PARTITION_FW_PART_HEADER_SIZE (0x0) -//TODO use header file from project -#define FW_XIP_ADDRESS (0x58000000) - -static struct { - uint8_t partition_active_idx; - uint8_t pad[3]; - PtTable_Stuff_Config table; -} boot2_partition_table;//XXX Dont change the name of varaible, since we refer this boot2_partition_table in linker script - -void hal_boot2_set_ptable_opt(HALpPtTable_Flash_Erase erase, HALpPtTable_Flash_Write write) -{ - PtTable_Set_Flash_Operation((pPtTable_Flash_Erase)erase, (pPtTable_Flash_Write)write); -} - -int hal_boot2_update_ptable(HALPartition_Entry_Config *ptEntry_hal) -{ - int ret; - //FIXME force covert - PtTable_Entry_Config *ptEntry = (PtTable_Entry_Config*)ptEntry_hal; - - ptEntry->activeIndex = !ptEntry->activeIndex; - (ptEntry->age)++; - ret = PtTable_Update_Entry(NULL,!boot2_partition_table.partition_active_idx, &boot2_partition_table.table, ptEntry); - return ret; -} - -static void _dump_partition(void) -{ - int i; - PtTable_Stuff_Config *part = &boot2_partition_table.table; - - USER_UNUSED(i); - USER_UNUSED(part); - - blog_info("======= PtTable_Config @%p=======\r\n", part); - blog_info("magicCode 0x%08X;", (unsigned int)(part->ptTable.magicCode)); - blog_info_raw(" version 0x%04X;", part->ptTable.version); - blog_info_raw(" entryCnt %u;", part->ptTable.entryCnt); - blog_info_raw(" age %lu;", part->ptTable.age); - blog_info_raw(" crc32 0x%08X\r\n", (unsigned int)part->ptTable.crc32); - - blog_info("idx type device activeIndex name Address[0] Address[1] Length[0] Length[1] age\r\n"); - for (i = 0; i < part->ptTable.entryCnt; i++) { - blog_info("[%02d] ", i); - blog_info_raw(" %02u", part->ptEntries[i].type); - blog_info_raw(" %u", part->ptEntries[i].device); - blog_info_raw(" %u", part->ptEntries[i].activeIndex); - blog_info_raw(" %8s", part->ptEntries[i].name); - blog_info_raw(" 0x%08x", (part->ptEntries[i].Address[0])); - blog_info_raw(" 0x%08x", (part->ptEntries[i].Address[1])); - blog_info_raw(" 0x%08x", (part->ptEntries[i].maxLen[0])); - blog_info_raw(" 0x%08x", (part->ptEntries[i].maxLen[1])); - blog_info_raw(" %lu\r\n", (part->ptEntries[i].age)); - } -} - -uint32_t hal_boot2_get_flash_addr(void) -{ - extern uint8_t __boot2_flashCfg_src; - - return (uint32_t)(&__boot2_flashCfg_src + - (sizeof(boot2_partition_table.table.ptEntries[0]) * boot2_partition_table.table.ptTable.entryCnt)); -} - -int hal_boot2_partition_bus_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active) -{ - int i; - uint32_t addr0_t, addr1_t; - - if (PARTITION_MAGIC != boot2_partition_table.table.ptTable.magicCode) { - return -EIO; - } - - /*Get Target partition*/ - for (i = 0; i < boot2_partition_table.table.ptTable.entryCnt; i++) { - if (0 == strcmp((char *)&(boot2_partition_table.table.ptEntries[i].name[0]), name)) { - break; - } - } - if (boot2_partition_table.table.ptTable.entryCnt == i) { - return -ENOENT; - } - addr0_t = boot2_partition_table.table.ptEntries[i].Address[0]; - addr1_t = boot2_partition_table.table.ptEntries[i].Address[1]; - *active = boot2_partition_table.table.ptEntries[i].activeIndex; - *size0 = boot2_partition_table.table.ptEntries[i].maxLen[0]; - *size1 = boot2_partition_table.table.ptEntries[i].maxLen[1]; - - /*cal partition address*/ - for (i = 0; i < boot2_partition_table.table.ptTable.entryCnt; i++) { - if (0 == strcmp((char *)&(boot2_partition_table.table.ptEntries[i].name[0]), PARTITION_FW_PART_NAME)) { - break; - } - } - if (boot2_partition_table.table.ptTable.entryCnt == i) { - return -ECANCELED; - } - /*Make sure target partition is after FW partition*/ - if ( (addr0_t && (addr0_t < boot2_partition_table.table.ptEntries[i].Address[0])) || - (addr0_t && (addr0_t < boot2_partition_table.table.ptEntries[i].Address[1])) || - (addr1_t && (addr1_t < boot2_partition_table.table.ptEntries[i].Address[0])) || - (addr1_t && (addr1_t < boot2_partition_table.table.ptEntries[i].Address[1]))) { - return -EINVAL; - } - if ((0 != boot2_partition_table.table.ptEntries[i].activeIndex) && - (1 != boot2_partition_table.table.ptEntries[i].activeIndex)) { - return -EFAULT; - } - *addr0 = addr0_t - boot2_partition_table.table.ptEntries[i].Address[boot2_partition_table.table.ptEntries[i].activeIndex] - PARTITION_FW_PART_HEADER_SIZE + FW_XIP_ADDRESS; - *addr1 = addr1_t - boot2_partition_table.table.ptEntries[i].Address[boot2_partition_table.table.ptEntries[i].activeIndex] - PARTITION_FW_PART_HEADER_SIZE + FW_XIP_ADDRESS; - - return 0; -} - -int hal_boot2_partition_bus_addr_active(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_bus_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr1 : addr0; - *size = active ? size1 : size0; - - return 0; -} - -int hal_boot2_partition_bus_addr_inactive(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_bus_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr0 : addr1; - *size = active ? size0 : size1; - - return 0; -} - -int hal_boot2_partition_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active) -{ - int i; - - if (PARTITION_MAGIC != boot2_partition_table.table.ptTable.magicCode) { - return -EIO; - } - - /*Get Target partition*/ - for (i = 0; i < boot2_partition_table.table.ptTable.entryCnt; i++) { - if (0 == strcmp((char *)&(boot2_partition_table.table.ptEntries[i].name[0]), name)) { - break; - } - } - if (boot2_partition_table.table.ptTable.entryCnt == i) { - return -ENOENT; - } - *addr0 = boot2_partition_table.table.ptEntries[i].Address[0]; - *addr1 = boot2_partition_table.table.ptEntries[i].Address[1]; - *size0 = boot2_partition_table.table.ptEntries[i].maxLen[0]; - *size1 = boot2_partition_table.table.ptEntries[i].maxLen[1]; - *active = boot2_partition_table.table.ptEntries[i].activeIndex; - - return 0; -} - -int hal_boot2_partition_addr_active(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr1 : addr0; - *size = active ? size1 : size0; - - return 0; -} - -int hal_boot2_partition_addr_inactive(const char *name, uint32_t *addr, uint32_t *size) -{ - uint32_t addr0, addr1; - uint32_t size0, size1; - int active, ret; - - if ((ret = hal_boot2_partition_addr(name, &addr0, &addr1, &size0, &size1, &active))) { - return ret; - } - *addr = active ? addr0 : addr1; - *size = active ? size0 : size1; - - return 0; -} - -uint8_t hal_boot2_get_active_partition(void) -{ - return boot2_partition_table.partition_active_idx; -} - -int hal_boot2_get_active_entries_byname(uint8_t *name, HALPartition_Entry_Config *ptEntry_hal) -{ - PtTable_Entry_Config *ptEntry = (PtTable_Entry_Config*)ptEntry_hal; - if (PtTable_Get_Active_Entries_By_Name(&boot2_partition_table.table, name, ptEntry)) { - return -1; - } - return 0; -} - -int hal_boot2_get_active_entries(int type, HALPartition_Entry_Config *ptEntry_hal) -{ - PtTable_Entry_Config *ptEntry = (PtTable_Entry_Config*)ptEntry_hal; - if (PtTable_Get_Active_Entries(&boot2_partition_table.table, type, ptEntry)) { - return -1; - } - return 0; -} - -int hal_boot2_dump(void) -{ - _dump_partition(); - return 0; -} - -int hal_boot2_init(void) -{ - boot2_partition_table.partition_active_idx = *(uint8_t*)PARTITION_BOOT2_RAM_ADDR_ACTIVE; - - blog_info("[HAL] [BOOT2] Active Partition[%u] consumed %d Bytes\r\n", - boot2_partition_table.partition_active_idx, - sizeof(PtTable_Stuff_Config) - ); - _dump_partition(); - bl_flash_config_update(); - - return 0; -} - -#if 0 -#define PT_OTA_TYPE_NAME "FW" -#define PT_MEDIA_TYPE_NAME "mfg" -void hal_update_mfg_ptable(void) -{ - PtTable_Entry_Config ptEntry_fw; - PtTable_Entry_Config ptEntry_media; - - printf("update mfg table.\r\n"); - printf("====================\r\n"); - if (0 == hal_boot2_get_active_entries_byname((uint8_t *)PT_OTA_TYPE_NAME, (HALPartition_Entry_Config *)(&ptEntry_fw))) { // ota - if (0 == hal_boot2_get_active_entries_byname((uint8_t *)PT_MEDIA_TYPE_NAME, (HALPartition_Entry_Config *)(&ptEntry_media))) { // media - if (ptEntry_fw.Address[1] == ptEntry_media.Address[0]) { - - memset(ptEntry_media.name, 0, sizeof(ptEntry_media.name)); - PtTable_Update_Entry(NULL, !boot2_partition_table.partition_active_idx, &boot2_partition_table.table, &ptEntry_media); - - printf("===== update mfg partition =====\r\n"); - } - } - } - - printf("====================\r\n"); - printf("update mfg table.\r\n"); -} -#endif - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.h deleted file mode 100644 index 387257309d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_boot2.h +++ /dev/null @@ -1,87 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_BOOT2_H__ -#define __HAL_BOOT2_H__ -#include - -typedef int (*fptr_Flash_Erase_t)(uint32_t startaddr,uint32_t endaddr); -typedef int (*fptr_Flash_Write_t)(uint32_t addr,uint8_t *data, uint32_t len); -typedef int (*fptr_Flash_Read_t) (uint32_t addr,uint8_t *data, uint32_t len); - -typedef struct { - uint8_t type; /*!< Partition entry type */ - uint8_t device; /*!< Partition entry device */ - uint8_t activeIndex; /*!< Partition entry active index */ - uint8_t name[9]; /*!< Partition entry name */ - uint32_t Address[2]; /*!< Partition entry start address */ - uint32_t maxLen[2]; /*!< Partition entry max length */ - uint32_t len; /*!< Partition entry length */ - uint32_t age; /*!< Partition entry age */ -} HALPartition_Entry_Config; - -/** - * @brief Partition id type definition - */ -typedef enum { - HAL_PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ - HAL_PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ - HAL_PT_ENTRY_MAX=16, /*!< Partition entry type:Max */ -} HALPtTable_Entry_Type; - -#define BOOT2_PARTITION_TYPE_FW (0) - -/** - * @brief Error type definition - */ -typedef enum -{ - HAL_SUCCESS = 0, - HAL_ERROR = 1, -} HAL_Err_Type; - -typedef HAL_Err_Type (*HALpPtTable_Flash_Erase)(uint32_t startaddr,uint32_t endaddr); -typedef HAL_Err_Type (*HALpPtTable_Flash_Write)(uint32_t addr,uint8_t *data, uint32_t len); -typedef HAL_Err_Type (*HALpPtTable_Flash_Read) (uint32_t addr,uint8_t *data, uint32_t len); - -void hal_boot2_set_ptable_opt(HALpPtTable_Flash_Erase erase, HALpPtTable_Flash_Write write); -int hal_boot2_partition_bus_addr_active(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_bus_addr_inactive(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_bus_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active); -int hal_boot2_partition_addr_active(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_addr_inactive(const char *name, uint32_t *addr, uint32_t *size); -int hal_boot2_partition_addr(const char *name, uint32_t *addr0, uint32_t *addr1, uint32_t *size0, uint32_t *size1, int *active); -uint8_t hal_boot2_get_active_partition(void); -int hal_boot2_get_active_entries(int type, HALPartition_Entry_Config *ptEntry); -int hal_boot2_update_ptable(HALPartition_Entry_Config *ptEntry); -int hal_boot2_dump(void); -int hal_boot2_init(void); -void hal_update_mfg_ptable(void); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_common.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_common.h deleted file mode 100644 index d570eea05c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_common.h +++ /dev/null @@ -1,50 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_COMMON__H__ -#define __HAL_COMMON__H__ - -#include "bl808_common.h" - -void cpu_global_irq_enable(void); -void cpu_global_irq_disable(void); -void hal_por_reset(void); -void hal_system_reset(void); -void hal_cpu_reset(void); -void hal_get_chip_id(uint8_t chip_id[8]); -void hal_dcache_clean_all(void); -void hal_dcache_invalid_all(void); -void hal_dcache_clean_invalid_all(void); -void hal_dcache_clean_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_invalid_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_clean_invalid_byaddr(uintptr_t addr, uint32_t len); -void *hal_ioalloc(size_t size); -void hal_iofree(void *addr); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.c deleted file mode 100644 index 8e528c2ac7..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.c +++ /dev/null @@ -1,666 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#include "bl808_emac.h" -#include "bl_irq.h" -#include "bl808_glb.h" -#include "hal_emac.h" -#include "bl808_l1c.h" -#if CTX_TYPE -#include -#include -#endif - -#define EMAC_USE_INSIDE_CLOCK (0) -#define TAG "EMAC_BD: " -#define EMAC_USED_ID EMAC0_ID - -static const uint32_t emacAddr[EMAC_ID_MAX] = { EMAC_BASE }; - -#ifdef EMAC_DBG -#define MSG printf -#else -#define MSG(...) ((void)0) -#endif -#define EMAC_DO_FLUSH_DATA 1 - -#if CTX_TYPE -extern TaskHandle_t DequeueTaskHandle; -#endif -static EMAC_Handle_Type ethHandle; -EMAC_Handle_Type *thiz = NULL; - -/** - * @brief - * - */ -static void emac_gpio_init(void) -{ - uint8_t emacPins[] = { GLB_GPIO_PIN_24, GLB_GPIO_PIN_25, GLB_GPIO_PIN_26, - GLB_GPIO_PIN_27, GLB_GPIO_PIN_28, GLB_GPIO_PIN_29, - GLB_GPIO_PIN_30, GLB_GPIO_PIN_31, GLB_GPIO_PIN_32, - GLB_GPIO_PIN_33 }; - - GLB_GPIO_Func_Init(GPIO_FUN_ETHER_MAC, (GLB_GPIO_Type *)emacPins, sizeof(emacPins)); -} - -/** - * @brief - * - * @param bdt - * @return int - */ -static uint32_t emac_bd_get_cur_active(EMAC_BD_TYPE_e bdt) -{ - uint32_t bd = 0; - - EMAC_GetBD(EMAC_USED_ID, &bd); - - if (bdt == EMAC_BD_TYPE_TX) { - bd &= EMAC_TXBDPTR_MSK; - bd >>= EMAC_TXBDPTR_POS; - } - - if (bdt == EMAC_BD_TYPE_RX) { - bd &= EMAC_RXBDPTR_MSK; - bd >>= EMAC_RXBDPTR_POS; - } - - return bd; -} - -/** - * @brief - * - * @param index - * @return int - */ -static int emac_bd_rx_enqueue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - - thiz->rxIndexEMAC = index; - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_rx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_OR)) { - MSG("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_RE)) { - MSG("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_DN)) { - MSG("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_TL)) { - MSG("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_CRC)) { - MSG("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_LC)) { - MSG("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; - /* RX BD is ready for RX */ - thiz->bd[index].C_S_L |= EMAC_BD_FIELD_MSK(RX_E); -} - -/** - * @brief this func will be called in ISR - * - * @param index - * @return int - */ -static int emac_bd_tx_dequeue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - thiz->txIndexEMAC = index; - DMADesc = &thiz->bd[thiz->txIndexEMAC]; - /* release this tx BD to SW (HW will do this) */ - DMADesc->C_S_L &= EMAC_BD_FIELD_UMSK(TX_RD); - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_tx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_UR)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RTRY)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RL)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_LC)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_DF)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_CS)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; -} - -/** - * @brief - * - */ -__WEAK void emac_tx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_tx_done_callback(void) -{ -#if CTX_TYPE - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - xTaskNotifyFromISR(DequeueTaskHandle, 0x01, eSetBits, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -#else - uint32_t index = 0; - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - - emac_bd_tx_dequeue(index); - - emac_tx_done_callback_app(); -#endif -} - -/** - * @brief - * - */ -__WEAK void emac_tx_error_callback_app(void) -{ - puts("Tx error\r\n"); -} - -/** - * @brief - * - */ -static void emac_tx_error_callback(void) -{ - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - emac_bd_tx_on_err(index); - emac_tx_error_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_done_callback(void) -{ -#if CTX_TYPE - BaseType_t xHigherPriorityTaskWoken = pdFALSE; - - xTaskNotifyFromISR(DequeueTaskHandle, 0x02, eSetBits, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); -#else - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_enqueue(index); - - emac_rx_done_callback_app(); -#endif -} - -/** - * @brief - * - */ -__WEAK void emac_rx_error_callback_app(void) -{ - puts("Rx error\r\n"); -} - -/** - * @brief - * - */ -static void emac_rx_error_callback(void) -{ - uint32_t index; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_on_err(index); - - emac_rx_error_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_busy_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_busy_callback(void) -{ - MSG("EMAC Rx busy at %s:%d\r\n", __func__, __LINE__); - emac_rx_busy_callback_app(); -} - -void emac_irq_process(void) -{ - EMAC_ID_Type emacId = EMAC_USED_ID; - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - tmpVal = BL_RD_REG(EMACx,EMAC_INT_MASK); - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_TXB_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_TX_DONE); - EMAC_IntMask(emacId, EMAC_INT_TX_DONE, MASK); - emac_tx_done_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_TXE_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_TX_ERROR); - emac_tx_error_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_RXB_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_DONE); - EMAC_IntMask(emacId, EMAC_INT_RX_DONE, MASK); - emac_rx_done_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_RXE_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_ERROR); - emac_rx_error_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_BUSY_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_BUSY); - emac_rx_busy_callback(); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_TXC_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_TX_CTRL); - } - - if (SET == EMAC_GetIntStatus(emacId,EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal,EMAC_RXC_M)) { - EMAC_ClrIntStatus(emacId,EMAC_INT_RX_CTRL); - } -} - -void EMAC_Interrupt_Init(void) -{ - MSG("EMAC_Interrupt_Init.\r\n"); - bl_irq_register(EMAC_IRQn, emac_irq_process); - bl_irq_enable(EMAC_IRQn); - - EMAC_ClrIntStatus(EMAC_USED_ID,EMAC_INT_ALL); - EMAC_IntMask(EMAC_USED_ID,EMAC_INT_ALL, UNMASK); - MSG("emac_intmask.\r\n"); -} -/** - * @brief - * - * @param emac_cfg - * @return int - */ -int emac_init(emac_device_t *emac_cfg) -{ - EMAC_CFG_Type emacCfg = { - .recvSmallFrame = ENABLE, /*!< Receive small frmae or not */ - .recvHugeFrame = DISABLE, /*!< Receive huge frmae(>64K bytes) or not */ - .padEnable = ENABLE, /*!< Enable padding for frame which is less than MINFL or not */ - .crcEnable = ENABLE, /*!< Enable hardware CRC or not */ - .noPreamble = DISABLE, /*!< Enable preamble or not */ - .recvBroadCast = ENABLE, /*!< Receive broadcast frame or not */ - .interFrameGapCheck = ENABLE, /*!< Check inter frame gap or not */ - .miiNoPreamble = ENABLE, /*!< Enable MII interface preamble or not */ - .miiClkDiv = 49, /*!< MII interface clock divider from bus clock */ - .maxTxRetry = 16, /*!< Maximum tx retry count */ - .interFrameGapValue = 24, /*!< Inter frame gap vaule in clock cycles(default 24)*/ - .minFrameLen = 64, /*!< Minimum frame length */ - .maxFrameLen = ETH_MAX_PACKET_SIZE, /*!< Maximum frame length */ - .collisionValid = 16, /*!< Collision valid value */ - .macAddr[0] = 0x18, /*!< MAC Address */ - .macAddr[1] = 0xB0, - .macAddr[2] = 0x09, - .macAddr[3] = 0x00, - .macAddr[4] = 0x12, - .macAddr[5] = 0x34, - }; - BL_Err_Type err = SUCCESS; - - /* init emac giio */ - emac_gpio_init(); - - memcpy(emacCfg.macAddr, emac_cfg->mac_addr, 6); - GLB_PER_Clock_UnGate(1<<12); -#if EMAC_USE_INSIDE_CLOCK - /* 50MHZ clock is from uhs pll */ - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_INSIDE_50M); -#else - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_OUTSIDE_50M); -#endif - //GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC); - GLB_PER_Clock_UnGate(1<<12); - //GLB_Invert_ETH_RX_CLK(0); - //GLB_Invert_ETH_TX_CLK(0); - EMAC_Init(EMAC_USED_ID,&emacCfg); - - EMAC_Interrupt_Init(); - return err; -} - -/** - * @brief - * - * @param eth_tx_buff - * @param tx_buf_count - * @param eth_rx_buff - * @param rx_buf_count - * @return int - */ -int emac_bd_init(uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count) -{ - BL_Err_Type err = SUCCESS; - thiz = ðHandle; - - /* init the BDs in emac with buffer address */ - err = EMAC_DMADescListInit(EMAC_USED_ID,thiz, (uint8_t *)eth_tx_buff, tx_buf_count, - (uint8_t *)eth_rx_buff, rx_buf_count); - return err; -} - -/** - * @brief - * - * @param none - * @return int - */ -int emac_bd_fragment_support(void){ - return 1; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_in - * @return int - */ -//uint32_t tmpbuf[400]; -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - uint32_t tx_flags=EMAC_TX_COMMON_FLAGS; - DMADesc = &thiz->bd[thiz->txIndexCPU]; - - if (flags&EMAC_FRAGMENT_PACKET) { - /* Fragment packet, clear EOF */ - tx_flags &= EMAC_BD_FIELD_UMSK(TX_EOF); - } - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) { - /* no free BD, lost sync with DMA TX? */ - err = NORESC; - //MSG(TAG"%s:%d\n", __func__, __LINE__); - } else { - __DSB(); - // MSG("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in); - if (flags&EMAC_NOCOPY_PACKET) { - DMADesc->Buffer = (uint32_t)data_in; - }else{ - ARCH_MemCpy_Fast((void *)DMADesc->Buffer, data_in, len); - } - - /* following two lines is for cache test since tmpbuf is in cache range */ - //ARCH_MemCpy_Fast(tmpbuf, data_in, len); - //DMADesc->Buffer = (uint32_t)tmpbuf; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Clean_By_Addr((uintptr_t)DMADesc->Buffer,len); - } -#endif - DMADesc->C_S_L = tx_flags | (len << BD_TX_LEN_POS); - - /* move to next TX BD */ - if ((++thiz->txIndexCPU) > thiz->txBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); - /* wrap back */ - thiz->txIndexCPU = 0; - } - } - - return err; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_out - * @return int - */ -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - DMADesc = &thiz->bd[thiz->rxIndexCPU]; - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(RX_E)) { - /* current RX BD is empty */ - err = NORESC; - *len = 0; - } else { - *len = (thiz->bd[thiz->rxIndexCPU].C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Invalid_By_Addr((uintptr_t)DMADesc->Buffer, *len); - } -#endif - if (data_out) { - ARCH_MemCpy_Fast(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len); - } - - /* RX BD can be used for another receive */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_E); - - /* move to next RX BD */ - if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); - /* wrap back */ - thiz->rxIndexCPU = thiz->txBuffLimit + 1; - } - } - - return err; -} - -/** - * @brief - * - * @param phyAddress - * @return int - */ -int emac_phy_set_address(uint16_t phyAddress) -{ - EMAC_Phy_SetAddress(EMAC_USED_ID,phyAddress); - - return 0; -} - -/** - * @brief - * - * @param fullDuplex - * @return int - */ -int emac_phy_config_full_duplex(uint8_t fullDuplex) -{ - EMAC_Phy_Set_Full_Duplex(EMAC_USED_ID,fullDuplex); - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue) -{ - if (EMAC_Phy_Read(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue) -{ - if (EMAC_Phy_Write(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -int emac_stop(void) -{ - return EMAC_Disable(EMAC_USED_ID); -} - -int emac_start(void) -{ - EMAC_Enable(EMAC_USED_ID); - return 0; -} - -int emac_start_tx(void) -{ - return EMAC_Enable_TX(EMAC_USED_ID); -} - -int emac_stop_tx(void) -{ - return EMAC_Disable_TX(EMAC_USED_ID); -} - -int emac_start_rx(void) -{ - return EMAC_Enable_RX(EMAC_USED_ID); -} - -int emac_stop_rx(void) -{ - return EMAC_Disable_RX(EMAC_USED_ID); -} - -int emac_intmask(EMAC_INT_Type intType, BL_Mask_Type intMask) -{ - return EMAC_IntMask(EMAC_USED_ID,intType, intMask); -} - -int emac_get_fram_len(uint16_t *max, uint16_t *min) -{ - return EMAC_GetFramLen(EMAC_USED_ID, max, min); -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.h deleted file mode 100644 index a6d91b34b6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_emac.h +++ /dev/null @@ -1,127 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HAL_EMAC_H__ -#define __HAL_EMAC_H__ - -#include "hal_common.h" -#include "drv_device.h" -// #include "bl808_config.h" -#include "bl808_emac.h" - -#define CTX_TYPE 1 - -#define MSG(a,...) printf(a,##__VA_ARGS__) -// #define MSG_DBG(a,...) printf(a,##__VA_ARGS__) -// #define MSG_WAR(a,...) printf(a,##__VA_ARGS__) -// #define MSG_ERR(a,...) printf(a,##__VA_ARGS__) -#define BL_CASE_FAIL {MSG(" Case Fail\r\n");while(1){}} -#define BL_CASE_SUCCESS {MSG(" Case Success\r\n");while(1){}} - -typedef struct emac_device { - struct device parent; - uint8_t mac_addr[6]; /*!< mac address */ -} emac_device_t; - -/** - * @brief EMAC PHY configuration type definition - */ -typedef struct -{ - uint8_t auto_negotiation; /*!< Speed and mode auto negotiation */ - uint8_t full_duplex; /*!< Duplex mode */ -#define PHY_STATE_DOWN (0) /* PHY is not usable */ -#define PHY_STATE_READY (1) /* PHY is OK, wait for controller */ -#define PHY_STATE_UP (2) /* Network is ready for TX/RX */ -#define PHY_STATE_RUNNING (3) /* working */ -#define PHY_STATE_NOLINK (4) /* no cable connected */ -#define PHY_STATE_STOPPED (5) /* PHY has been stopped */ -#define PHY_STATE_TESTING (6) /* in test mode */ - uint8_t phy_state; /*!< down,ready,up,running,nolink,halted */ - uint8_t use_irq; /*!< 0: no IRQ used */ - uint16_t speed; /*!< Speed mode */ - uint16_t phy_address; /*!< PHY address */ - uint32_t phy_id; /*!< PHY OUI */ -} emac_phy_cfg_t; - -#define EMAC_NORMAL_PACKET (uint32_t)(0) -#define EMAC_FRAGMENT_PACKET (uint32_t)(0x01) -#define EMAC_NOCOPY_PACKET (uint32_t)(0x02) - -#ifndef ETH_TX_BUFFER_SIZE -#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#ifndef ETH_RX_BUFFER_SIZE -#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \ - EMAC_BD_FIELD_MSK(TX_IRQ) | \ - EMAC_BD_FIELD_MSK(TX_PAD) | \ - EMAC_BD_FIELD_MSK(TX_CRC) | \ - EMAC_BD_FIELD_MSK(TX_EOF)) - -#define EMAC_RX_COMMON_FLAGS (ETH_MAX_PACKET_SIZE << 16) | \ - EMAC_BD_FIELD_MSK(RX_IRQ) ) - -typedef enum _BD_TYPE_ { - EMAC_BD_TYPE_INVLAID, - EMAC_BD_TYPE_TX, - EMAC_BD_TYPE_RX, - EMAC_BD_TYPE_NONE, - EMAC_BD_TYPE_MAX = 0x7FFFFFFF -} EMAC_BD_TYPE_e; - -int emac_init(emac_device_t *emac_cfg); -int emac_bd_init(uint8_t *ethTxBuff, uint8_t txBufCount, uint8_t *ethRxBuff, uint8_t rxBufCount); -int emac_bd_fragment_support(void); -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in); -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out); -__WEAK void emac_rx_done_callback_app(void); -__WEAK void emac_rx_error_callback_app(void); -__WEAK void emac_rx_busy_callback_app(void); -__WEAK void emac_tx_error_callback_app(void); -__WEAK void emac_tx_done_callback_app(void); -int emac_phy_set_address(uint16_t phyAddress); -int emac_phy_config_full_duplex(uint8_t fullDuplex); -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue); -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue); -int emac_stop(void); -int emac_start(void); -int emac_start_tx(void); -int emac_stop_tx(void); -int emac_start_rx(void); -int emac_stop_rx(void); -int emac_intmask(EMAC_INT_Type intType, BL_Mask_Type intMask); -int emac_get_fram_len(uint16_t *max, uint16_t *min); -BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min); -BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.c deleted file mode 100644 index dcdc201d35..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.c +++ /dev/null @@ -1,91 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include "bl_sdh.h" -#include "hal_sdh.h" - -static sd_card_t gSDCardInfo; -static uint32_t sdio_bus_width = SDH_DATA_BUS_WIDTH_1BIT; - -int32_t hal_sd_init(sd_dev_t *sd) -{ - static uint8_t inited = 0; - - if (inited == 0) { - if (SDH_Init(sdio_bus_width, &gSDCardInfo) == SD_OK) { - inited = 1; - return 0; - } else { - return -1; - } - } - - return 0; -} - -void hal_sd_bus_4bits_enable() -{ - sdio_bus_width = SDH_DATA_BUS_WIDTH_4BITS; -} - -int32_t hal_sd_stat_get(sd_dev_t *sd, hal_sd_stat *stat) -{ - *stat = SD_STAT_TRANSFER; - return 0; -} - -int32_t hal_sd_blks_read(sd_dev_t *sd, uint8_t *data, uint32_t blk_addr, uint32_t blks, uint32_t timeout) -{ - if (SD_OK == SDH_ReadMultiBlocks(data, blk_addr, gSDCardInfo.blockSize, blks)) { - return 0; - } else { - return -1; - } -} - -int32_t hal_sd_blks_write(sd_dev_t *sd, uint8_t *data, uint32_t blk_addr, uint32_t blks, uint32_t timeout) -{ - if (SD_OK == SDH_WriteMultiBlocks(data, blk_addr, gSDCardInfo.blockSize, blks)) { - return 0; - } else { - return -1; - } -} - -int32_t hal_sd_info_get(sd_dev_t *sd, hal_sd_info_t *info) -{ - - info->blk_nums = gSDCardInfo.blockCount; - info->blk_size = gSDCardInfo.blockSize; - - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.h deleted file mode 100644 index 30801aab28..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sdh.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_SDH_H__ -#define __HAL_SDH_H__ -void hal_sd_bus_4bits_enable(); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.c deleted file mode 100644 index e0756ae4b9..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.c +++ /dev/null @@ -1,139 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include - -#include "bl_sys.h" -#include "hal_sys.h" - -void hal_reboot() -{ - bl_sys_reset_por(); -} - -void hal_sys_reset() -{ - //bl_sys_reset_system(); -} - -void hal_poweroff() -{ - /*TODO empty now*/ -} - -#if 0 -static uint32_t user_clz(uint32_t priorities) -{ - return __builtin_clz(priorities); -} - -struct romapi_freertos_map* hal_sys_romapi_get(void) -{ - extern uint8_t __global_pointer_head$; - uint32_t *gp_data_start = (uint32_t*)(&__global_pointer_head$); - struct romapi_freertos_map* romapi_freertos; - - puts(" Configuring Version 1.0 ROM API...\r\n"); - - /*clear bss/common section in GP aera*/ - memset(&__global_pointer_head$, 0, 0x498); - romapi_freertos = (struct romapi_freertos_map*) (((uint8_t*)gp_data_start) + 0x45c); - - /* pTrapNetCounter */ - *(gp_data_start + 0) = (uint32_t)((uint8_t*)(gp_data_start) + 0x58); - /* pullNextTime */ - *(gp_data_start + 1) = (uint32_t)((uint8_t*)(gp_data_start) + 0x60); - /* system tick */ - *(gp_data_start + 2) = 32 * 1000 / 1000;//Use 32K - - return romapi_freertos; -} - -void hal_sys_romapi_update(struct romapi_freertos_map *romapi_freertos) -{ - extern void interrupt_entry(uint32_t mcause); - extern void exception_entry(uint32_t mcause, uint32_t mepc, uint32_t mtval); - extern uint8_t __freertos_irq_stack_top; - - romapi_freertos->interrupt_entry_ptr = interrupt_entry; - romapi_freertos->rtos_sprintf = sprintf; - romapi_freertos->rtos_memcpy_ptr = memcpy; - romapi_freertos->rtos_strlen_ptr = strlen; - romapi_freertos->rtos_memset_ptr = memset; - romapi_freertos->exception_entry_ptr = exception_entry; - romapi_freertos->rtos_strcpy_ptr = strcpy; - romapi_freertos->xISRStackTop = &__freertos_irq_stack_top; - romapi_freertos->rtos_clz = user_clz; -} -#endif -void hal_sys_capcode_update(uint8_t capin, uint8_t capout) -{ - //TODO FPGA no capcode -#if 0 - static uint8_t capin_static, capout_static; - - if (255 != capin && 255 != capout) { - RomDriver_AON_Set_Xtal_CapCode(capin, capout); - capin_static = capin; - capout_static = capout; - } else { - RomDriver_AON_Set_Xtal_CapCode(capin_static, capout_static); - } -#endif -} - -uint8_t hal_sys_capcode_get(void) -{ - return 0; - // return AON_Get_Xtal_CapCode(); -} - -void hal_sys_mtimer_div(void) -{ - *(volatile uint32_t *)0x20009014 = 0x80000004; -} -void hal_enable_cpu0(void) -{ - bl_enable_cpu0(); -} - -void hal_boot_cpu0(uint32_t start_addr) -{ - bl_boot_cpu0(start_addr); -} - -void hal_halt_cpu0(void) -{ - bl_halt_cpu0(); -} - -void hal_release_cpu0(void) -{ - bl_release_cpu0(); -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.h deleted file mode 100644 index b78b98de28..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_sys.h +++ /dev/null @@ -1,67 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_SYS_H__ -#define __HAL_SYS_H__ - -#include - -void hal_reboot(); -void hal_sys_reset(); -void hal_poweroff(); - -struct romapi_freertos_map -{ - void *vApplicationIdleHook; - void *interrupt_entry_ptr; - void *vApplicationGetIdleTaskMemory; - void *vApplicationStackOverflowHook; - void *vApplicationGetTimerTaskMemory; - void *rtos_sprintf; - void *vApplicationMallocFailedHook; - void *rtos_memcpy_ptr; - void *vAssertCalled; - void *rtos_strlen_ptr; - void *rtos_memset_ptr; - void *rtos_clz; - void *exception_entry_ptr; - void *rtos_strcpy_ptr; - void *xISRStackTop; -}; -struct romapi_freertos_map* hal_sys_romapi_get(void); -void hal_sys_romapi_update(struct romapi_freertos_map *romapi); - -void hal_sys_capcode_update(uint8_t capin, uint8_t capout); -uint8_t hal_sys_capcode_get(void); -void hal_sys_mtimer_div(void); -void hal_enable_cpu0(void); -void hal_boot_cpu0(uint32_t start_addr); -void hal_halt_cpu0(void); -void hal_release_cpu0(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.c deleted file mode 100644 index 220c54b62b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.c +++ /dev/null @@ -1,284 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include -#include -#include - -#include "bl_uart.h" -#include "hal_uart.h" - -#include - -typedef struct uart_priv_data { - aos_mutex_t mutex; -} uart_priv_data_t; - -static int8_t inited; -static uart_dev_t *dev_uart0 = NULL; -static uart_dev_t *dev_uart1 = NULL; -static uart_dev_t *dev_uart2 = NULL; -static uart_dev_t *dev_uart3 = NULL; - -static int uart_dev_malloc(uart_dev_t **pdev) -{ - if (*pdev) { - blog_error("arg err.\r\n"); - return -1; - } - - *pdev = pvPortMalloc(sizeof(uart_dev_t)); - if (*pdev == 0) { - blog_error("mem err.\r\n"); - return -1; - } - memset(*pdev, 0, sizeof(uart_dev_t)); - - (*pdev)->read_block_flag = UART_READ_CFG_NOBLOCK; - (*pdev)->priv = NULL; - (*pdev)->priv = pvPortMalloc(sizeof(uart_priv_data_t)); - if ((*pdev)->priv == NULL) { - blog_error("mem err.\r\n"); - return -1; - } - memset((*pdev)->priv, 0, sizeof(uart_priv_data_t)); - - return 0; -} - -static void uart_dev_setdef(uart_dev_t **pdev, uint8_t id) -{ - if (*pdev == NULL) { - blog_error("mem err.\r\n"); - return; - } - - (*pdev)->port = id; - (*pdev)->read_block_flag = UART_READ_CFG_NOBLOCK; - - (*pdev)->config.baud_rate = 2000000; - (*pdev)->config.data_width = DATA_WIDTH_8BIT; - (*pdev)->config.parity = NO_PARITY; - (*pdev)->config.stop_bits = STOP_BITS_1; - (*pdev)->config.flow_control = FLOW_CONTROL_DISABLED; - (*pdev)->config.mode = MODE_TX_RX; -} - -static int dev_uart_init(uint8_t id, const char *path, uint32_t rx_buf_size, uint32_t tx_buf_size) -{ - uart_dev_t **pdev = NULL; - int ret; - - if ((id >= 4) || (path == 0)) { - blog_error("arg err.\r\n"); - return -1; - } - - switch (id) { - case 0: - { - pdev = &dev_uart0; - } break; - case 1: - { - pdev = &dev_uart1; - } break; - case 2: - { - pdev = &dev_uart2; - } break; - case 3: - { - pdev = &dev_uart3; - } break; - default: - { - blog_error("err.\r\n"); - return -1; - } break; - } - - if (uart_dev_malloc(pdev) != 0) { - return -1; - } - (*pdev)->rx_buf_size = rx_buf_size; - (*pdev)->tx_buf_size = tx_buf_size; - // (*pdev)->ring_rx_buffer = pvPortMalloc((*pdev)->rx_buf_size); - // (*pdev)->ring_tx_buffer = pvPortMalloc((*pdev)->tx_buf_size); - - // if ((*pdev)->ring_rx_buffe == NULL || (*pdev)->ring_rx_buffe == NULL ) { - // return -1; - // } - - uart_dev_setdef(pdev, id); - ret = aos_register_driver(path, &uart_ops, *pdev); - if (ret != VFS_SUCCESS) { - return ret; - } - - return 0; -} - -int32_t hal_uart_send_trigger(uart_dev_t *uart) -{ - bl_uart_int_tx_enable(uart->port); - return 0; -} - -int32_t hal_uart_send_trigger_off(uart_dev_t *uart) -{ - bl_uart_int_tx_disable(uart->port); - return 0; -} - -int32_t hal_uart_init(uart_dev_t *uart) -{ - uart_priv_data_t *data; - uint8_t parity; - - data = uart->priv; - if (aos_mutex_new(&(data->mutex))) { - /*we should assert here?*/ - return -1; - } - - bl_uart_getdefconfig(uart->port, &parity); - - if (parity == UART_PARITY_NONE) { - uart->config.parity = NO_PARITY; - } else if (parity == UART_PARITY_ODD) { - uart->config.parity = ODD_PARITY; - } else { - uart->config.parity = EVEN_PARITY; - } - - bl_uart_int_enable(uart->port); - - return 0; -} - -int vfs_uart_init_simple_mode(uint8_t id, uint8_t pin_tx, uint8_t pin_rx, int baudrate, const char *path) -{ - //bl_uart_flush(id); - - bl_uart_init(id, pin_tx, pin_rx, 255, 255, baudrate); - - if (dev_uart_init(id, path, 128, 128) != 0) { - blog_error("dev_uart_init err.\r\n"); - } - - return 0; -} - -int vfs_uart_init(uint32_t fdt, uint32_t dtb_uart_offset) -{ - dev_uart_init(0, "/dev/ttyS0", 512, 512); - return 0; -} - -int32_t hal_uart_recv_II(uart_dev_t *uart, void *data, uint32_t expect_size, uint32_t *recv_size, uint32_t timeout) -{ - int ch; - uint32_t counter = 0; - - while (counter < expect_size && (ch = bl_uart_data_recv(uart->port)) >= 0) { - ((uint8_t*)data)[counter] = ch; - counter++; - } - - *recv_size = counter; - return 0; -} - -int32_t hal_uart_send(uart_dev_t *uart, const void *data, uint32_t size, uint32_t timeout) -{ - uint32_t i = 0; - - while (i < size) { - bl_uart_data_send(uart->port, ((uint8_t*)data)[i]); - i++; - } - return 0; -} - -int32_t hal_uart_send_flush(uart_dev_t *uart, uint32_t timeout) -{ - bl_uart_flush(uart->port); - return 0; -} - -void hal_uart_setbaud(uart_dev_t *uart, uint32_t baud) -{ - bl_uart_setbaud(uart->port, baud); -} - -void hal_uart_setconfig(uart_dev_t *uart, uint32_t baud, hal_uart_parity_t parity) -{ - bl_uart_setconfig(uart->port, baud, parity); -} - -int32_t hal_uart_finalize(uart_dev_t *uart) -{ - uart_priv_data_t *data; - - data = uart->priv; - bl_uart_int_disable(uart->port); - aos_mutex_free(&(data->mutex)); - return 0; -} - -/*TODO better glue for ring buffer?*/ -int32_t hal_uart_notify_register(uart_dev_t *uart, hal_uart_int_t type, void (*cb)(void *arg)) -{ - if (type == UART_TX_INT) { - bl_uart_int_tx_notify_register(uart->port, cb, uart); - } else if (type == UART_RX_INT) { - bl_uart_int_rx_notify_register(uart->port, cb, uart); - } else { - return -1; - } - - return 0; -} - -int32_t hal_uart_notify_unregister(uart_dev_t *uart, hal_uart_int_t type, void (*cb)(void *arg)) -{ - if (type == UART_TX_INT) { - bl_uart_int_tx_notify_unregister(uart->port, cb, uart); - } else if (type == UART_RX_INT) { - bl_uart_int_rx_notify_unregister(uart->port, cb, uart); - } else { - return -1; - } - - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.h deleted file mode 100644 index c30f93f3de..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_uart.h +++ /dev/null @@ -1,35 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_UART_H__ -#define __HAL_UART_H__ -int vfs_uart_init(uint32_t fdt, uint32_t dtb_uart_offset); -int vfs_uart_init_simple_mode(uint8_t id, uint8_t pin_tx, uint8_t pin_rx, int baudrate, const char *path); -int hal_uart_data_notify(int number, int dir); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.c deleted file mode 100644 index ad4592651b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.c +++ /dev/null @@ -1,1285 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "hal_usb.h" -#include "bl808_usb.h" -#include "bl808_glb.h" - -#ifndef CONFIG_USB_VDMA_ENABLE -#define CONFIG_USB_VDMA_ENABLE -#endif - -#ifndef CONFIG_USB_PINGPONG_ENABLE -// #define CONFIG_USB_PINGPONG_ENABLE -#endif - -#ifndef CONFIG_USB_VDMA_OUT_ENABLE -// #define CONFIG_USB_VDMA_OUT_ENABLE -#endif - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -#define USB_DC_LOG_WRN(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) -#define USB_DC_LOG_DBG(a, ...) -#define USB_DC_LOG_ERR(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) -#define USB_DC_LOG(a, ...) //bflb_platform_printf(a, ##__VA_ARGS__) - -static uint8_t fifo_ep_map[4] = { 0, 0, 0, 0 }; - -static usb_dc_device_t usb_hs_device __attribute__((section(".RW_OCRAM_NOINIT"))); -static void USBD_IRQHandler(void); - -static uint8_t usb_ep_is_enabled(uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if ep enabled */ - if ((USB_EP_DIR_IS_OUT(ep)) && - usb_hs_device.out_ep[ep_idx].ep_ena) { - return 1; - } else if ((USB_EP_DIR_IS_IN(ep)) && - usb_hs_device.in_ep[ep_idx].ep_ena) { - return 1; - } - - return 0; -} -#ifndef CONFIG_USB_VDMA_ENABLE -static int usb_dma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_MEM_2_FIFO; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - csi_dcache_clean_range((uint32_t *)data, len); - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - return 0; -} - -static int usb_dma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_FIFO_2_MEM; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - csi_dcache_invalid_range((uint32_t *)data, len); - return 0; -} -#else -static int usb_vdma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - - csi_dcache_clean_range((void *)data, len); - - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - return 0; -} - -static int usb_vdma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - csi_dcache_invalid_range((void *)data, len); - return 0; -} -#endif - -static uint8_t usb_get_transfer_fifo(uint8_t ep_idx) -{ - uint8_t target_fifo_id; - - if (usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps > 512 || usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps > 512) { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (4 * ep_idx - 3); -#else - target_fifo_id = (2 * ep_idx - 1); -#endif - } else { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (2 * ep_idx - 1); -#else - target_fifo_id = ep_idx; -#endif - } - - return target_fifo_id; -} - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int usb_dc_init(void) -{ - CPU_Interrupt_Disable(USB_IRQn); - - PDS_Turn_On_USB(1); - - /* interrupt config */ - USB_Global_IntEnable(DISABLE); - - /* software reset usb */ - USB_NORMAL_Cfg_Type usbNormalCfg = { -#ifdef CONFIG_USB_HS - .forceFullSpeed = 0, -#else - .forceFullSpeed = 1, -#endif - .chipEn = 1, - .swRst = 1, - .remoteWakeupEn = 0, - .rstTimeOut = 0xFFFF - }; - USB_Set_Normal_Config(&usbNormalCfg); -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - USB_Set_Device_Address(0); - USB_Non_Ctrl_Transfer_Disable(); - - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - - USB_Group_IntMask(USB_GRP_INT_G0, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G1, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G2, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G3, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G4, UNMASK); - - USB_Global_IntMask(USB_GLOBAL_INT_DEV, UNMASK); - USB_Global_IntMask(USB_GLOBAL_INT_OTG, MASK); - USB_Global_IntMask(USB_GLOBAL_INT_HC, MASK); - - USB_Sub_Group_IntMask(USB_INT_DMA_CMPLT | USB_INT_DMA_ERROR | USB_INT_IDLE | USB_INT_RX0BYTE | USB_INT_TX0BYTE); - USB_Sub_Group_IntMask(USB_INT_VDMA_CMPLT_CXF | USB_INT_VDMA_CMPLT_F0 | USB_INT_VDMA_CMPLT_F1 | USB_INT_VDMA_CMPLT_F2 | USB_INT_VDMA_CMPLT_F3 | - USB_INT_VDMA_ERROR_CXF | USB_INT_VDMA_ERROR_F0 | USB_INT_VDMA_ERROR_F1 | USB_INT_VDMA_ERROR_F2 | USB_INT_VDMA_ERROR_F3); - - USB_Sub_Group_IntUnmask(USB_INT_CX_SETUP | USB_INT_CX_IN | USB_INT_CX_OUT | USB_INT_CX_COMFAIL | USB_INT_CX_COMABORT); - USB_Sub_Group_IntUnmask(USB_INT_RESET | USB_INT_SUSPEND | USB_INT_RESUME | USB_INT_RX0BYTE); - - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK | USB_SUB_GROUP_2_SUSPEND_BIT_MUSK | USB_SUB_GROUP_2_RESUME_BIT_MUSK | - USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK | USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK | - USB_SUB_GROUP_2_CMPLT_BIT_MUSK | USB_SUB_GROUP_2_ERROR_BIT_MUSK); - USB_Get_Sub_Group_3_IntClear(0xffffffff); //VDMA INT - USB_Get_Sub_Group_4_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - /*TODO mask no use rsv int use some drv*/ - BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, 1 << 3); - -#ifdef CONFIG_USB_VDMA_ENABLE - USB_Set_VDMA_Enable(); -#endif - - memset(&usb_hs_device, 0, sizeof(usb_hs_device)); - - usb_hs_device.out_ep[0].ep_ena = 1U; - usb_hs_device.in_ep[0].ep_ena = 1U; - usb_hs_device.out_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - usb_hs_device.in_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - - Interrupt_Handler_Register(USB_IRQn, USBD_IRQHandler); - CPU_Interrupt_Enable(USB_IRQn); - USB_SoftDetach_Disable(); - USB_Global_IntEnable(ENABLE); - - return 0; -} - -/** - * @brief Set USB device address - * - * @param[in] addr Device address - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_set_address(const uint8_t addr) -{ - USB_Set_Device_Address(addr); - return 0; -} - -/** - * @brief configure and enable endpoint - * This function sets endpoint configuration according to one specified in USB - * endpoint descriptor and then enables it for data transfers. - * - * @param dev - * @param ep_cfg ep_cfg Endpoint - * @return int - */ -int usbd_ep_open(const struct usb_dc_ep_cfg *ep_cfg) -{ - uint8_t ep; - USB_FIFO_Cfg_Type fifo_cfg; - - if (!ep_cfg) { - return -1; - } - - ep = ep_cfg->ep_addr; - - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx > 4) { - return -1; - } - - USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type); - - if (ep_idx == 0) { - return 0; - } - - fifo_cfg.enable = 1; - fifo_cfg.fifoType = ep_cfg->ep_type; - fifo_cfg.epID = ep_idx; - - if (USB_EP_DIR_IS_OUT(ep)) { - fifo_cfg.dir = USB_FIFO_DIR_OUT; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.out_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_OUT_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - - } else { - fifo_cfg.dir = USB_FIFO_DIR_IN; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.in_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_IN_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - } - -#ifndef CONFIG_USB_PINGPONG_ENABLE - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_SINGLE_BLOCK; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 4) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x02; - fifo_ep_map[2] = 0x03; - fifo_ep_map[3] = 0x04; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_4, USB_FIFO_3); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_4, USB_FIFO_3); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 2 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } else { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } -#else - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - } else { - if (ep_idx > 1) { - return -1; - } - - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x01; - fifo_ep_map[3] = 0x01; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx + 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT)); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); - } - } -#endif - - USB_Non_Ctrl_Transfer_Enable(); - - return 0; -} - -/** - * @brief Disable the selected endpoint - * - * Function to disable the selected endpoint. Upon success interrupts are - * disabled for the corresponding endpoint and the endpoint is no longer able - * for transmitting/receiving data. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_close(const uint8_t ep) -{ - return 0; -} -/** - * @brief Set stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_set_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (USB_EP_DIR_IS_OUT(ep)) { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_OUT_Stall(ep_idx, ENABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 1U; - } - } else { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_IN_Stall(ep_idx, ENABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 1U; - } - } - return 0; -} -/** - * @brief Clear stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_clear_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx) { - if (USB_EP_DIR_IS_OUT(ep)) { - USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_OUT_Stall(ep_idx, DISABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 0; - } else { - USB_Reset_Endpoint_IN_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_IN_Stall(ep_idx, DISABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 0; - } - } - return 0; -} -/** - * @brief Check if the selected endpoint is stalled - * - * @param dev usb device - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[out] stalled Endpoint stall status - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (!stalled) { - return -1; - } - *stalled = 0U; - if (ep_idx == 0) - return 0; - - if (USB_EP_DIR_IS_OUT(ep)) { - if (usb_hs_device.out_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } else { - if (usb_hs_device.in_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } - - return 0; -} - -/** - * @brief Write data to the specified endpoint - * - * This function is called to write data to the specified endpoint. The - * supplied usbd_endpoint_callback function will be called when data is transmitted - * out. - * - * @param dev - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data to write - * @param[in] data_len Length of the data requested to write. This may - * be zero for a zero length status packet. - * @param[out] ret_bytes Bytes scheduled for transmission. This value - * may be NULL if the application expects all - * bytes to be written - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) -{ - uint32_t timeout = 0xffffff; - uint32_t target_fifo_id = 0; - uint8_t mps_over_flag = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - if (ep_idx == 0) { - if (!data_len) { - /* enable ep0 transfer */ - USB_CTRL_Endpoint_Data_Transfer_Done(); - return USB_DC_OK; - } - if (data_len > usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps) { - /* Check if transfer len is too big */ - data_len = usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps; - mps_over_flag = 1; - } - -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(0, data, data_len); -#else - ret = usb_dma_write(0, data, data_len); -#endif - if (ret < 0) { - return ret; - } - if (!mps_over_flag) { - USB_CTRL_Endpoint_Data_Transfer_Done(); - } - - } else { - if (!data_len) { - /* send zlp */ - USB_Endpoint_Transmit_Zero_Length_Packet(ep_idx); - while (1) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(ep_idx)) { - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(ep_idx); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - return USB_DC_OK; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(target_fifo_id, data, data_len); -#else - ret = usb_dma_write(target_fifo_id, data, data_len); -#endif - if (ret < 0) { - return ret; - } - } - - USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len); - - if (ret_bytes) { - *ret_bytes = data_len; - } - - return USB_DC_OK; -} - -/** - * @brief Read data from the specified endpoint - * - * This function is called by the endpoint handler function, after an OUT - * interrupt has been received for that EP. The application must only call this - * function through the supplied usbd_ep_callback function. This function clears - * the ENDPOINT NAK when max_data_len is 0, if all data in the endpoint FIFO has been read, - * so as to accept more data from host. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data buffer to write to - * @param[in] max_data_len Max length of data to read - * @param[out] read_bytes Number of bytes read. If data is NULL and - * max_data_len is 0 the number of bytes - * available for read should be returned. - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes) -{ - uint32_t read_len = 0; - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - - /* Check if OUT ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - USB_DC_LOG_ERR("Wrong endpoint direction\r\n"); - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - USB_DC_LOG_ERR("Not enabled endpoint\r\n"); - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - /* Allow to read 0 bytes */ - if (!data_len) { - return USB_DC_OK; - } - - if (ep_idx == 0) { - /*setup handler*/ - if ((data_len == 8) && !read_bytes) { - USB_Get_Setup_Command((uint32_t *)data); - return USB_DC_OK; - } else { - read_len = BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_FNT); -#if defined(CONFIG_USB_VDMA_ENABLE) - ret = usb_vdma_read(0, data, read_len); -#else - ret = usb_dma_read(0, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - } else { - target_fifo_id = usb_get_transfer_fifo(ep_idx); - read_len = USB_Get_OUT_FIFO_Count(target_fifo_id - 1); - if (read_len == 0) { - if (read_bytes) { - *read_bytes = 0; - } - return 0; - } -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_read(target_fifo_id, data, read_len); -#else - ret = usb_dma_read(target_fifo_id, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - if (read_bytes) { - *read_bytes = read_len; - } - USB_DC_LOG_DBG("Read EP%d, req %d, read %d bytes\r\n", ep, data_len, *read_bytes); - - return USB_DC_OK; -} - -int usbd_ep_write_async(const uint8_t ep, const uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - csi_dcache_clean_range((void *)data, data_len); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -int usbd_ep_read_async(const uint8_t ep, uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -extern void usbd_event_notify_handler(uint8_t event, void *arg); - -static void usb_group0_isr(void) -{ - uint32_t group0intstatus = USB_Get_Sub_Group_0_IntStatus() & ~USB_Get_Sub_Group_0_IntMask(); - - if (group0intstatus & USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK) { - /* CX_COMABT_INT */ - USB_DC_LOG_ERR("CX COMABT\r\n"); - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_COMFAIL_BIT_MUSK) { - /* CX_COMFAIL_INT */ - USB_DC_LOG_ERR("CX COMFAIL\r\n"); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_OUT_BIT_MUSK) { - /* CX_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_OUT_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_IN_BIT_MUSK) { - /* CX_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_IN_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_SETUP_BIT_MUSK) { - /* CX_SETUP_INT */ - usbd_event_notify_handler(USB_DC_EVENT_SETUP_NOTIFY, NULL); - return; - } -} -static void usb_group1_isr(void) -{ - uint32_t group1intstatus = USB_Get_Sub_Group_1_IntStatus() & ~USB_Get_Sub_Group_1_IntMask(); - - if (group1intstatus & USB_SUB_GROUP_1_F0_OUT_BIT_MUSK) { - /* F0_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_OUT_BIT_MUSK) { - /* F1_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_OUT_BIT_MUSK) { - /* F2_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_OUT_BIT_MUSK) { - /* F3_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F0_IN_BIT_MUSK) { - /* F0_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_IN_BIT_MUSK) { - /* F1_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_IN_BIT_MUSK) { - /* F2_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_IN_BIT_MUSK) { - /* F3_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } -} -static void usb_group2_isr(void) -{ - uint32_t group2intstatus = USB_Get_Sub_Group_2_IntStatus() & ~USB_Get_Sub_Group_2_IntMask(); - - if (group2intstatus & USB_SUB_GROUP_2_WAKEUP_BY_VBUS_BIT_MUSK) { - /* Dev_Wakeup_byVBUS */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_IDLE_BIT_MUSK) { - /* Dev_Idle(HOV) */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - /* DMA_ERROR(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - /* DMA_CMPLT(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK) { - /* RX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Receive_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK) { - /* TX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESUME_BIT_MUSK) { - /* RESM_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESUME_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_RESUME, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_SUSPEND_BIT_MUSK) { - /* SUSP_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_SUSPEND_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_SUSPEND, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESET_BIT_MUSK) { - /* USBRST_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK); - USB_Non_Ctrl_Transfer_Disable(); - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - usbd_event_notify_handler(USB_DC_EVENT_RESET, NULL); - return; - } -} -#ifdef CONFIG_USB_VDMA_ENABLE -static void usb_group3_isr(void) -{ - uint32_t group3intstatus = USB_Get_Sub_Group_3_IntStatus() & ~USB_Get_Sub_Group_3_IntMask(); - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK) { - /* VDMA_CMPLT_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK) { - /* VDMA_CMPLT_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK) { - /* VDMA_CMPLT_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK) { - /* VDMA_CMPLT_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK) { - /* VDMA_CMPLT_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK) { - /* VDMA_ERROR_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK) { - /* VDMA_ERROR_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK) { - /* VDMA_ERROR_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK) { - /* VDMA_ERROR_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK) { - /* VDMA_ERROR_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK); - } -} -#endif -static void usb_group4_isr(void) -{ - uint32_t group4intstatus = USB_Get_Sub_Group_4_IntStatus() & ~USB_Get_Sub_Group_4_IntMask(); - - if (group4intstatus & USB_SUB_GROUP_4_L1_BIT_MUSK) { - /* L1_INT */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - return; - } -} - -/** - * @brief - * - */ -void USBD_IRQHandler(void) -{ - if (USB_Global_IntStatus(USB_GLOBAL_INT_DEV)) { - /* group 0 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G0)) { - usb_group0_isr(); - } - /* group 1 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G1)) { - usb_group1_isr(); - } - /* group 2 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G2)) { - usb_group2_isr(); - } -#ifdef CONFIG_USB_VDMA_ENABLE - /* group 3 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G3)) { - usb_group3_isr(); - } -#endif - /* group 4 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G4)) { - usb_group4_isr(); - } - } -} - -#ifdef USB_TEST_MODE -void usbd_set_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_set_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - case 2: //USB_FEATURE_TEST_MODE - switch (index >> 8) { - case 1: // Test_J - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_JSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 2: // Test_K - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_KSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 3: // TEST_SE0_NAK - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_SE0NAK); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 4: // Test_Packet - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKT); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 5: // Test_Force_Enable - { - uint8_t temp[53]; - uint8_t *pp; - uint8_t i; - pp = temp; - - for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/ - *pp++ = 0x00; - - for (i = 0; i < 8; i++) /* 8*AA */ - *pp++ = 0xAA; - - for (i = 0; i < 8; i++) /* 8*EE */ - *pp++ = 0xEE; - - *pp++ = 0xFE; - - for (i = 0; i < 11; i++) /* 11*FF */ - *pp++ = 0xFF; - - *pp++ = 0x7F; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0xFC; - *pp++ = 0x7E; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0x7E; - - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKDONE); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - } break; - - default: - break; - } - break; - case 3: //USB_FEATURE_BHNPENABLE - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_BUS_REQ); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_HNP_EN); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - } break; - case 4: //USB_FEATURE_AHNPSUPPORT - - break; - case 5: //USB_FEATURE_AALTHNPSUPPORT - - break; - - default: - break; - } -} - -void usbd_clear_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_clear_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - - default: - break; - } -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.h deleted file mode 100644 index 86f454312a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_usb.h +++ /dev/null @@ -1,158 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_USB__H__ -#define __HAL_USB__H__ - -#include "stdint.h" - -/** - * USB endpoint Transfer Type mask. - */ -#define USBD_EP_TYPE_CTRL 0 -#define USBD_EP_TYPE_ISOC 1 -#define USBD_EP_TYPE_BULK 2 -#define USBD_EP_TYPE_INTR 3 -#define USBD_EP_TYPE_MASK 3 - -/** - * USB endpoint direction and number. - */ -#define USB_EP_DIR_MASK 0x80U -#define USB_EP_DIR_IN 0x80U -#define USB_EP_DIR_OUT 0x00U - -#define USB_EP_OUT_MSK 0x7FU -#define USB_EP_IN_MSK 0x80U - -/** Get endpoint index (number) from endpoint address */ -#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) -/** Get direction from endpoint address */ -#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) -/** Get endpoint address from endpoint index and direction */ -#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) -/** True if the endpoint is an IN endpoint */ -#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) -/** True if the endpoint is an OUT endpoint */ -#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) - -#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK) -#define USB_SET_EP_IN(ep) (ep | USB_EP_IN_MSK) - -#define USB_OUT_EP_NUM 8 -#define USB_IN_EP_NUM 8 - -enum usb_dc_event_type { - /** USB error reported by the controller */ - USB_DC_EVENT_ERROR, - /** USB reset */ - USB_DC_EVENT_RESET, - /** Start of Frame received */ - USB_DC_EVENT_SOF, - /** USB connection established, hardware enumeration is completed */ - USB_DC_EVENT_CONNECTED, - /** USB configuration done */ - USB_DC_EVENT_CONFIGURED, - /** USB connection suspended by the HOST */ - USB_DC_EVENT_SUSPEND, - /** USB connection lost */ - USB_DC_EVENT_DISCONNECTED, - /** USB connection resumed by the HOST */ - USB_DC_EVENT_RESUME, - - /** USB interface selected */ - USB_DC_EVENT_SET_INTERFACE, - /** USB interface selected */ - USB_DC_EVENT_SET_REMOTE_WAKEUP, - /** USB interface selected */ - USB_DC_EVENT_CLEAR_REMOTE_WAKEUP, - /** Set Feature ENDPOINT_HALT received */ - USB_DC_EVENT_SET_HALT, - /** Clear Feature ENDPOINT_HALT received */ - USB_DC_EVENT_CLEAR_HALT, - /** setup packet received */ - USB_DC_EVENT_SETUP_NOTIFY, - /** ep0 in packet received */ - USB_DC_EVENT_EP0_IN_NOTIFY, - /** ep0 out packet received */ - USB_DC_EVENT_EP0_OUT_NOTIFY, - /** ep in packet except ep0 received */ - USB_DC_EVENT_EP_IN_NOTIFY, - /** ep out packet except ep0 received */ - USB_DC_EVENT_EP_OUT_NOTIFY, - /** Initial USB connection status */ - USB_DC_EVENT_UNKNOWN -}; - -enum usb_error_type { - USB_DC_OK = 0, - USB_DC_EP_DIR_ERR = 1, - USB_DC_EP_EN_ERR = 2, - USB_DC_EP_TIMEOUT_ERR = 3, - USB_DC_ADDR_ERR = 4, - USB_DC_DMA_ERR = 5, - USB_DC_VDMA_ERR = 6, - USB_DC_DATA_NONE = 7, -}; -/** - * @brief USB Endpoint Configuration. - * - * Structure containing the USB endpoint configuration. - */ -struct usb_dc_ep_cfg { - /** The number associated with the EP in the device - * configuration structure - * IN EP = 0x80 | \ - * OUT EP = 0x00 | \ - */ - uint8_t ep_addr; - /** Endpoint Transfer Type. - * May be Bulk, Interrupt, Control or Isochronous - */ - uint8_t ep_type; - /** Endpoint max packet size */ - uint16_t ep_mps; -}; - -/* - * USB endpoint structure. - */ -typedef struct -{ - uint8_t ep_ena; - uint8_t is_stalled; - struct usb_dc_ep_cfg ep_cfg; -} usb_dc_ep_state_t; - -typedef struct usb_dc_device { - usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */ - usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */ -} usb_dc_device_t; - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.c deleted file mode 100644 index 1a73c370bf..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.c +++ /dev/null @@ -1,51 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include "hal_wifi.h" -#include - - -#define WIFI_STACK_SIZE (1536) -#define TASK_PRIORITY_FW (30) - -#ifndef FEATURE_WIFI_DISABLE -#include -int hal_wifi_start_firmware_task(void) -{ - static StackType_t wifi_fw_stack[WIFI_STACK_SIZE]; - static StaticTask_t wifi_fw_task; - - bl_pm_init(); - xTaskCreateStatic(wifi_main, (char*)"fw", WIFI_STACK_SIZE, NULL, TASK_PRIORITY_FW, wifi_fw_stack, &wifi_fw_task); - - return 0; -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.h b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.h deleted file mode 100644 index d3df2cd5a8..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hal_wifi.h +++ /dev/null @@ -1,33 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_WIFI_H__ -#define __HAL_WIFI_H__ -int hal_wifi_start_firmware_task(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_adc.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_adc.c deleted file mode 100644 index 233c50838f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_adc.c +++ /dev/null @@ -1,527 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#include -#include -#elif defined(BL606P) -#include -#include -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include -#include -#include -#include - -#define ADC_CLOCK_FREQ 40000000 -#define ADC_GPIO_NUM 12 -#define ADC_CHANNEL_MAX 12 - -typedef struct adc_ctx { - uint32_t *channel_data; - void *adc_lli; - void *llibuf; - int lli_flag; - uint32_t chan_init_table; - uint32_t data_size; -}hosal_adc_ctx_t; - -static hosal_adc_dev_t *pgdevice; - -void adc_data_update (void *p_arg, uint32_t flag) -{ - hosal_adc_dev_t *adc = (hosal_adc_dev_t *)p_arg; - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (pstctx->lli_flag == 0) { - pstctx->channel_data = (uint32_t *)((DMA_LLI_Ctrl_Type *)(pstctx->adc_lli))[0].destDmaAddr; - pstctx->lli_flag = 1; - } else { - pstctx->channel_data = (uint32_t *)((DMA_LLI_Ctrl_Type *)(pstctx->adc_lli))[1].destDmaAddr; - pstctx->lli_flag = 0; - } -} - -static int adc_check_gpio_valid(GLB_GPIO_Type pin) -{ - int i; - - GLB_GPIO_Type gpio_arr[ADC_GPIO_NUM] = - { - GLB_GPIO_PIN_4, GLB_GPIO_PIN_5, GLB_GPIO_PIN_6, - GLB_GPIO_PIN_11, GLB_GPIO_PIN_12, GLB_GPIO_PIN_13, - GLB_GPIO_PIN_16, GLB_GPIO_PIN_17, GLB_GPIO_PIN_18, - GLB_GPIO_PIN_19, GLB_GPIO_PIN_34, GLB_GPIO_PIN_40 - }; - - for (i = 0; i < ADC_GPIO_NUM; i++) { - if (pin == gpio_arr[i]) { - return 0; - } - } - - blog_error("gpio %d can not used as adc\r\n", pin); - - return -1; -} - -static int adc_get_channel_by_gpio(GLB_GPIO_Type pin) -{ - int channel = -1; - - switch (pin) { - case GLB_GPIO_PIN_4: - channel = 2; - break; - case GLB_GPIO_PIN_5: - channel = 1; - break; - case GLB_GPIO_PIN_6: - channel = 4; - break; - case GLB_GPIO_PIN_11: - channel = 3; - break; - case GLB_GPIO_PIN_12: - channel = 6; - break; - case GLB_GPIO_PIN_13: - channel = 7; - break; - case GLB_GPIO_PIN_16: - channel = 8; - break; - case GLB_GPIO_PIN_17: - channel = 0; - break; - case GLB_GPIO_PIN_18: - channel = 9; - break; - case GLB_GPIO_PIN_19: - channel = 10; - break; - case GLB_GPIO_PIN_34: - channel = 11; - break; - case GLB_GPIO_PIN_40: - channel = 5; - break; - - default : - channel = -1; - break; - } - - return channel; -} - -static void adc_freq_init(hosal_adc_sample_mode_t mode, uint32_t freq) -{ - uint32_t div; - uint32_t source_freq; - uint32_t mode_freq; - - if (mode == HOSAL_ADC_ONE_SHOT) { - mode_freq = ADC_CHANNEL_MAX; - } else { - mode_freq = 1; - } - - source_freq = ADC_CLOCK_FREQ / (128 * 24 * mode_freq); - - div = source_freq / freq; - if (((div + 1) * freq - source_freq) < (source_freq - freq * div)) { - div = div + 1; - } - - if (div > 64) { - div = 64; - } - - /*adc clk can not more than 2M*/ - /*when adc work at scan mode, adc clk can not more than 1M*/ - blog_info("ADC freq: %ldHz. ,div:%lu\r\n", (int)(source_freq / div), div); - - /* set clk */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_GPIP | GLB_AHB_CLOCK_DMA_0); - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, div-1); -} - -static void adc_dma_lli_init(DMA_LLI_Ctrl_Type *pstlli, uint32_t *buf, uint32_t data_num) -{ - struct DMA_Control_Reg dma_ctrl_reg={ - .TransferSize=0, - .SBSize=DMA_BURST_SIZE_1, - .dst_min_mode=DISABLE, - .DBSize=DMA_BURST_SIZE_1, - .dst_add_mode=DISABLE, - .SWidth=DMA_TRNS_WIDTH_32BITS, - .DWidth=DMA_TRNS_WIDTH_32BITS, - .fix_cnt=0, - .SI=DMA_MINC_DISABLE, - .DI=DMA_MINC_ENABLE, - .I=1, - }; - dma_ctrl_reg.TransferSize = data_num; - - pstlli[0].srcDmaAddr = GPIP_BASE+GPIP_GPADC_DMA_RDATA_OFFSET; - pstlli[0].destDmaAddr = (uint32_t)&buf[0]; - pstlli[0].nextLLI = (uint32_t)&pstlli[1]; - pstlli[0].dmaCtrl= dma_ctrl_reg; - - pstlli[1].srcDmaAddr = GPIP_BASE+GPIP_GPADC_DMA_RDATA_OFFSET; - pstlli[1].destDmaAddr = (uint32_t)&buf[ADC_CHANNEL_MAX]; - pstlli[1].nextLLI = (uint32_t)&pstlli[0]; - pstlli[1].dmaCtrl= dma_ctrl_reg; -} - -static int adc_dma_init(hosal_adc_dev_t *adc, uint32_t data_num) -{ - DMA_LLI_Ctrl_Type *pstlli; - uint32_t *llibuf; - DMA_LLI_Cfg_Type llicfg = { - .dir = DMA_TRNS_P2M, - .srcPeriph = DMA_REQ_GPADC_RX, - .dstPeriph = DMA_REQ_NONE, - }; - - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (data_num < 1) { - blog_error("illegal para. \r\n"); - return -1; - } - - adc->dma_chan = hosal_dma_chan_request(0); - - pstlli = pvPortMalloc(sizeof(DMA_LLI_Ctrl_Type) * 2); - if (NULL == pstlli) { - blog_error("malloc lli failed. \r\n"); - return -1; - } - - llibuf = pvPortMalloc(sizeof(uint32_t) * data_num * 2); - if (NULL == llibuf) { - blog_error("malloc lli buf failed. \r\n"); - return -1; - } - - adc_dma_lli_init(pstlli, llibuf, data_num); - DMA_LLI_Init(DMA0_ID, adc->dma_chan, &llicfg); - DMA_LLI_Update(DMA0_ID, adc->dma_chan, (uint32_t)&(pstlli[0])); - - pstctx->llibuf = llibuf; - pstctx->adc_lli = pstlli; - pstctx->lli_flag = 0; - pstctx->chan_init_table = 0; - pstctx->channel_data = NULL; - pstctx->data_size = data_num; - - hosal_dma_irq_callback_set(adc->dma_chan, adc_data_update, adc); - - return 0; -} - -//mode = 0, for normal adc. freq 20HZ~1302HZ -static void adc_init(hosal_adc_dev_t *adc) -{ - int i, chan; - uint8_t channel_table[ADC_CHANNEL_MAX] = {0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11}; - - hosal_adc_sample_mode_t mode = adc->config.mode; - GLB_GPIO_Type pin = adc->config.pin; - - ADC_CFG_Type adccfg; - ADC_Chan_Type pos_chlist_single[ADC_CHANNEL_MAX]; - ADC_Chan_Type neg_chlist_single[ADC_CHANNEL_MAX]; - ADC_FIFO_Cfg_Type adc_fifo_cfg = { - /*dma request will happend when fifo count up to fifoThreshold.*/ - .fifoThreshold = ADC_FIFO_THRESHOLD_1, - .dmaEn = ENABLE, - }; - - adccfg.v18Sel=ADC_V18_SEL_1P82V; - adccfg.v11Sel=ADC_V11_SEL_1P1V; - adccfg.clkDiv=ADC_CLK_DIV_24; - /* one shot mode */ - if (mode == HOSAL_ADC_ONE_SHOT) { - adccfg.gain1=ADC_PGA_GAIN_NONE; - adccfg.gain2=ADC_PGA_GAIN_NONE; - adccfg.chopMode=ADC_CHOP_MOD_AZ_PGA_ON; - } else { - adccfg.gain1=ADC_PGA_GAIN_1; - adccfg.gain2=ADC_PGA_GAIN_1; - adccfg.chopMode=ADC_CHOP_MOD_AZ_PGA_ON; - } - adccfg.biasSel=ADC_BIAS_SEL_MAIN_BANDGAP; - adccfg.vcm=ADC_PGA_VCM_1V; - adccfg.vref=ADC_VREF_3P2V; - adccfg.inputMode=ADC_INPUT_SINGLE_END; - adccfg.resWidth = ADC_DATA_WIDTH_16_WITH_128_AVERAGE; - adccfg.offsetCalibEn=0; - adccfg.offsetCalibVal=0; - - ADC_Disable(); - ADC_Enable(); - ADC_Reset(); - - ADC_Init(&adccfg); - - if (mode == HOSAL_ADC_ONE_SHOT) { - for (i = 0; i < ADC_CHANNEL_MAX; i++) { - pos_chlist_single[i] = channel_table[i];; - neg_chlist_single[i] = ADC_CHAN_GND; - } - - ADC_Scan_Channel_Config(pos_chlist_single, neg_chlist_single, ADC_CHANNEL_MAX, ENABLE); - } - else { - chan = adc_get_channel_by_gpio(pin); - ADC_Channel_Config(chan, ADC_CHAN_GND, ENABLE); - ADC_Mic_Init(NULL); - } - - ADC_FIFO_Cfg(&adc_fifo_cfg); -} - -static void adc_dma_start(hosal_dma_chan_t chan) -{ - ADC_Start(); - - /* refresh cache */ - L1C_DCache_Clean_Invalid_All(); - hosal_dma_chan_start(chan); -} - -static int adc_parse_data(uint32_t *parr, int data_size, int channel) -{ - int i; - int32_t data; - - for (i = 0; i < data_size; i++) { - if (parr[i] >> 21 == channel) { - data = parr[i] & 0xFFFF; - data = (data * 3200) >> 16; - - return data; - } - } - blog_error("error!\r\n"); - return -1; -} - -int hosal_adc_init(hosal_adc_dev_t *adc) -{ - int res = -1; - int freq; - GLB_GPIO_Type pin; - hosal_adc_ctx_t *pstctx; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - freq = adc->config.sampling_freq; - pin = (GLB_GPIO_Type)adc->config.pin; - - /* check adc pin*/ - res = adc_check_gpio_valid(pin); - if (res) { - blog_error("pin is error!\r\n"); - return -1; - } - - pstctx = (hosal_adc_ctx_t *)pvPortMalloc(sizeof(hosal_adc_ctx_t)); - if (NULL == pstctx) { - blog_error("not have enough memory!\r\n"); - return -1; - } - - memset(pstctx, 0, sizeof(hosal_adc_ctx_t)); - adc->priv = pstctx; - - if (adc->config.mode == HOSAL_ADC_ONE_SHOT) { - if (freq < 20 || freq > 1250) { - blog_error("illegal freq. for mode0, freq 20HZ ~ 1250HZ \r\n"); - return -1; - } - /* init gpio */ - GLB_GPIO_Func_Init(GPIO_FUN_ANALOG, &pin, 1); - - /* init freq */ - adc_freq_init(adc->config.mode, freq); - adc_init(adc); - adc_dma_init(adc, ADC_CHANNEL_MAX); - adc_dma_start(adc->dma_chan); - } else { - blog_error("not support continue mode!\r\n"); - return -1; - } - - pgdevice = adc; - - return 0; -} - -int hosal_adc_add_channel(hosal_adc_dev_t *adc, uint32_t channel) -{ - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - if (channel > 11) { - blog_error("channel is error!"); - return -1; - } - pstctx->chan_init_table |= 1 << channel; - - return 0; -} - -int hosal_adc_remove_channel(hosal_adc_dev_t *adc, uint32_t channel) -{ - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - if (channel > 11) { - blog_error("channel is error!\r\n"); - return -1; - } - - pstctx->chan_init_table &= ~(1 << channel); - - return 0; -} - -hosal_adc_dev_t *hosal_adc_device_get(void) -{ - if (NULL == pgdevice) { - blog_error("please init adc first!\r\n"); - return NULL; - } - - return pgdevice; -} - -int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout) -{ - int val = -1; - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parameter is error!\r\n"); - return -1; - } - - if (channel > 11) { - blog_error("channel is error!\r\n"); - return -1; - } - - if (((1 << channel) & pstctx->chan_init_table) == 0) { - blog_error("channel = %d not init as adc \r\n", channel); - return -1; - } - - if (pstctx->channel_data == NULL) { - blog_error("adc sampling not finish. \r\n"); - return -1; - } - - /* refresh cache */ - L1C_DCache_Invalid_By_Addr(pstctx->channel_data, sizeof(uint32_t)*ADC_CHANNEL_MAX); - while ((val = adc_parse_data(pstctx->channel_data, ADC_CHANNEL_MAX, channel)) == -1) { - if (timeout-- == 0) { - return -1; - } - vTaskDelay(1); - } - - return val; -} - -int hosal_adc_tsen_value_get(hosal_adc_dev_t *adc) -{ - blog_error("not support now!\r\n"); - return -1; -} - -int hosal_adc_sample_cb_reg(hosal_adc_dev_t *adc, hosal_adc_cb_t cb) -{ - blog_error("not support now!\r\n"); - return -1; -} - -int hosal_adc_start(hosal_adc_dev_t *adc, void *data, uint32_t size) -{ - blog_error("not support now!\r\n"); - return -1; -} - -int hosal_adc_stop(hosal_adc_dev_t *adc) -{ - return 0; -} - -int hosal_adc_finalize(hosal_adc_dev_t *adc) -{ - hosal_adc_ctx_t *pstctx = (hosal_adc_ctx_t *)adc->priv; - - if (NULL == adc) { - blog_error("parm error!\r\n"); - return -1; - } - - vPortFree(pstctx->llibuf); - vPortFree(pstctx->adc_lli); - vPortFree(pstctx); - ADC_Stop(); - hosal_dma_chan_stop(adc->dma_chan); - hosal_dma_chan_release(adc->dma_chan); - - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_dma.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_dma.c deleted file mode 100644 index 984b03e1ac..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_dma.c +++ /dev/null @@ -1,314 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include -#include -#include - -static hosal_dma_dev_t *gp_hosal_dma_dev = NULL; - -static void __dma_irq_process(void *p_arg) -{ - int ch; - uint32_t intclr; - uint32_t tmpval; - uint32_t interr_val; - int tc_flag, interr_flag; - /* Get DMA register */ - uint32_t DMAChs = DMA0_BASE; - hosal_dma_dev_t *dma_dev = (hosal_dma_dev_t *)gp_hosal_dma_dev; - hosal_dma_irq_t pfn; - void *parg; - - if (!dma_dev) - return; - - tmpval = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - interr_val = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - - for (ch = 0; ch < dma_dev->max_chans; ch++) { - tc_flag = BL_GET_REG_BITS_VAL(tmpval, DMA_INTTCSTATUS) & (1 << ch); - interr_flag = BL_GET_REG_BITS_VAL(interr_val, DMA_INTERRORSTATUS) & (1 << ch); - - if((tc_flag != 0) || (interr_flag != 0)) { - if (tc_flag != 0) { - /* tc int, clear interrupt */ - tmpval = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intclr = BL_GET_REG_BITS_VAL(tmpval, DMA_INTTCCLEAR); - intclr |= (1 << ch); - tmpval = BL_SET_REG_BITS_VAL(tmpval, DMA_INTTCCLEAR, intclr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpval); - - pfn = gp_hosal_dma_dev->used_chan[ch].callback; - parg = gp_hosal_dma_dev->used_chan[ch].p_arg; - if (pfn) { - pfn(parg, HOSAL_DMA_INT_TRANS_COMPLETE); - } - } - - if (interr_flag != 0) { - /* int error, clear interrupt */ - tmpval = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intclr = BL_GET_REG_BITS_VAL(tmpval, DMA_INTERRCLR); - intclr |= (1 << ch); - tmpval = BL_SET_REG_BITS_VAL(tmpval, DMA_INTERRCLR, intclr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpval); - - pfn = gp_hosal_dma_dev->used_chan[ch].callback; - parg = gp_hosal_dma_dev->used_chan[ch].p_arg; - if (pfn) { - pfn(parg, HOSAL_DMA_INT_TRANS_ERROR); - } - } - } - } -} - -static int __dma_int_clear(int ch) -{ - uint32_t tmpVal; - uint32_t intClr; - /* Get DMA register */ - uint32_t DMAChs = DMA0_BASE; - - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - if((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - } - - return 0; -} - -/** - * @brief Initialises a DMA interface - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_init(void) -{ - int i; - if (gp_hosal_dma_dev) { - return 0; - } - - gp_hosal_dma_dev = calloc(sizeof(hosal_dma_dev_t), 1); - if (gp_hosal_dma_dev == NULL) { - blog_error("no memory !!!\r\n"); - return -1; - } - - gp_hosal_dma_dev->max_chans = DMA_CH_MAX; - gp_hosal_dma_dev->used_chan = calloc(sizeof(struct hosal_dma_chan) * DMA_CH_MAX, 1); - if (gp_hosal_dma_dev->used_chan == NULL) { - blog_error("no memory !!!\r\n"); - free(gp_hosal_dma_dev); - gp_hosal_dma_dev = NULL; - return -1; - } - DMA_Enable(DMA0_ID); - for (i = 0; i < gp_hosal_dma_dev->max_chans; i++) { - DMA_Channel_Disable(DMA0_ID, i); - DMA_IntMask(DMA0_ID, i, DMA_INT_ALL, MASK); - } - bl_irq_register(DMA0_ALL_IRQn, __dma_irq_process); - bl_irq_enable(DMA0_ALL_IRQn); - return 0; -} - -/** - * @brief Request a DMA channel - * - * @return < 0 : an error occurred with any step, otherwise is DMA channel number - */ -hosal_dma_chan_t hosal_dma_chan_request(int flag) -{ - int i; - - (void)flag; - - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - for (i = 0; i < gp_hosal_dma_dev->max_chans; i++) { - if (!gp_hosal_dma_dev->used_chan[i].used) { - gp_hosal_dma_dev->used_chan[i].used = 1; - return i; - } - } - return -1; -} - -/** - * @brief Release a DMA channel - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_release(hosal_dma_chan_t chan) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - hosal_dma_chan_stop(chan); - gp_hosal_dma_dev->used_chan[chan].used = 0; - gp_hosal_dma_dev->used_chan[chan].callback = NULL; - DMA_IntMask(DMA0_ID, chan, DMA_INT_TCOMPLETED, MASK); - DMA_IntMask(DMA0_ID, chan, DMA_INT_ERR, MASK); - return 0; -} - -/** - * @brief DMA channel start - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_start(hosal_dma_chan_t chan) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - DMA_Channel_Enable(DMA0_ID, chan); - return 0; -} - -/** - * @brief DMA channel stop - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_stop(hosal_dma_chan_t chan) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - __dma_int_clear(chan); - DMA_Channel_Disable(DMA0_ID, chan); - return 0; -} - -/** - * @brief DMA irq callback set - * - * @param[in] chan : DMA channel number - * @param[in] pfn : callback function - * @param[in] arg : callback function parameter - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_irq_callback_set(hosal_dma_chan_t chan, hosal_dma_irq_t pfn, void *p_arg) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - if (chan > gp_hosal_dma_dev->max_chans) { - return -1; - } - - gp_hosal_dma_dev->used_chan[chan].callback = pfn; - gp_hosal_dma_dev->used_chan[chan].p_arg = p_arg; - DMA_IntMask(DMA0_ID, chan, DMA_INT_TCOMPLETED, UNMASK); - DMA_IntMask(DMA0_ID, chan, DMA_INT_ERR, UNMASK); - return 0; -} - -/** - * @brief Deinitialises a DMA interface - * - * @param[in] DMA the interface which should be deinitialised - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_finalize(void) -{ - if (!gp_hosal_dma_dev) { - blog_error("please hosal_dma_init !\r\n"); - return -1; - } - - DMA_Disable(DMA0_ID); - bl_irq_disable(DMA0_ALL_IRQn); - - free(gp_hosal_dma_dev); - gp_hosal_dma_dev = NULL; - return 0; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_pwm.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_pwm.c deleted file mode 100644 index b0330d8e38..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_pwm.c +++ /dev/null @@ -1,267 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "hosal_pwm.h" -#include "blog.h" - - -#define PWM_CHANNAL_MAX 4 -#define PWM_XCLK_CLK 40000000 -#define PWM_DUTY_MAX 10000 - - -/** - * Initialises a PWM pin - * - * - * @param[in] pwm the PWM device - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_init(hosal_pwm_dev_t *pwm) -{ - GLB_GPIO_Cfg_Type gpioCfg = { - .gpioPin = 0, - .gpioFun = GPIO_FUN_PWM0, //GPIO_FUN_PWM1 - .gpioMode = GPIO_MODE_OUTPUT, - .pullType = GPIO_PULL_DOWN, - .drive = 0, - .smtCtrl = 1, - }; - - PWMx_CFG_Type pwmxCfg = { - .clk = PWM_CLK_XCLK, - .stopMode = PWM_STOP_GRACEFUL, - .clkDiv = 1, - .period = 0, - .intPulseCnt = 0, - .extPol = PWM_BREAK_Polarity_HIGH, - .stpRept = DISABLE, - .adcSrc = PWM_TRIGADC_SOURCE_NONE, - }; - - PWM_CHx_CFG_Type chxCfg = { - .modP = PWM_MODE_ENABLE, - .modN = PWM_MODE_ENABLE, - .polP = PWM_POL_ACTIVE_HIGH, - .polN = PWM_POL_ACTIVE_HIGH, - .idlP = PWM_IDLE_STATE_INACTIVE, - .idlN = PWM_IDLE_STATE_INACTIVE, - .brkP = PWM_BREAK_STATE_INACTIVE, - .brkN = PWM_BREAK_STATE_INACTIVE, - .thresholdL = 0, - .thresholdH = 0, - .dtg = 0, - }; - - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - gpioCfg.gpioPin = pwm->config.pin; - if (pwm->port == PWM0_ID) - gpioCfg.gpioFun = GPIO_FUN_PWM0; - else if (pwm->port == PWM1_ID) - gpioCfg.gpioFun = GPIO_FUN_PWM1; - GLB_GPIO_Init(&gpioCfg); - - PWMx_Disable(pwm->port); - pwmxCfg.period = PWM_XCLK_CLK/pwm->config.freq; - PWMx_Init(pwm->port, &pwmxCfg); - chxCfg.thresholdL = 0; - chxCfg.thresholdH = (PWM_XCLK_CLK/pwm->config.freq)*pwm->config.duty_cycle/PWM_DUTY_MAX; - PWM_Channelx_Init(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, &chxCfg); - PWM_Channelx_Pwm_Mode_Set(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, PWM_MODE_DISABLE, PWM_MODE_DISABLE); - PWMx_Enable(pwm->port); - return 0; -} - -/** - * Starts Pulse-Width Modulation signal output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_start(hosal_pwm_dev_t *pwm) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - PWM_Channelx_Pwm_Mode_Set(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, PWM_MODE_ENABLE, PWM_MODE_ENABLE); - return 0; -} - -/** - * Stops output on a PWM pin - * - * @param[in] pwm the PWM device, para set duty and freq - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_para_chg(hosal_pwm_dev_t *pwm, hosal_pwm_config_t para) -{ - PWM_CHx_CFG_Type chxCfg = { - .modP = PWM_MODE_ENABLE, - .modN = PWM_MODE_ENABLE, - .polP = PWM_POL_ACTIVE_HIGH, - .polN = PWM_POL_ACTIVE_HIGH, - .idlP = PWM_IDLE_STATE_INACTIVE, - .idlN = PWM_IDLE_STATE_INACTIVE, - .brkP = PWM_BREAK_STATE_INACTIVE, - .brkN = PWM_BREAK_STATE_INACTIVE, - .thresholdL = 0, - .thresholdH = 0, - .dtg = 0, - }; - - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - chxCfg.thresholdL = 0; - chxCfg.thresholdH = (PWM_XCLK_CLK/para.freq)*para.duty_cycle/PWM_DUTY_MAX; - PWM_Channelx_Init(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, &chxCfg); - return 0; -} - -/** - * set pwm freq - * - *@param[in] id pwm channel - *@param[in] freq pwm freq - * - *@return 0 : on success -1 : fail - */ -int hosal_pwm_freq_set(hosal_pwm_dev_t *pwm, uint32_t freq) -{ - return -1; -} - -int hosal_pwm_freq_get(hosal_pwm_dev_t *pwm, uint32_t *p_freq) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - *p_freq = pwm->config.freq; - return 0; -} - -int hosal_pwm_duty_set(hosal_pwm_dev_t *pwm, uint32_t duty) -{ - PWM_CHx_CFG_Type chxCfg = { - .modP = PWM_MODE_ENABLE, - .modN = PWM_MODE_ENABLE, - .polP = PWM_POL_ACTIVE_HIGH, - .polN = PWM_POL_ACTIVE_HIGH, - .idlP = PWM_IDLE_STATE_INACTIVE, - .idlN = PWM_IDLE_STATE_INACTIVE, - .brkP = PWM_BREAK_STATE_INACTIVE, - .brkN = PWM_BREAK_STATE_INACTIVE, - .thresholdL = 0, - .thresholdH = 0, - .dtg = 0, - }; - - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - chxCfg.thresholdL = 0; - chxCfg.thresholdH = (PWM_XCLK_CLK/pwm->config.freq)*duty/PWM_DUTY_MAX; - PWM_Channelx_Init(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, &chxCfg); - return 0; -} - -int hosal_pwm_duty_get(hosal_pwm_dev_t *pwm, uint32_t *p_duty) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - *p_duty = pwm->config.duty_cycle; - return 0; -} -/** - * Stops output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_stop(hosal_pwm_dev_t *pwm) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - PWM_Channelx_Pwm_Mode_Set(pwm->port, pwm->config.pin%PWM_CHANNAL_MAX, PWM_MODE_DISABLE, PWM_MODE_DISABLE); - return 0; -} - -/** - * De-initialises an PWM interface, Turns off an PWM hardware interface - * - * @param[in] pwm the interface which should be de-initialised - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_pwm_finalize(hosal_pwm_dev_t *pwm) -{ - if (NULL == pwm || (pwm->port != PWM0_ID && pwm->port != PWM1_ID)) { - blog_error("arg error.\r\n"); - return -1; - } - - PWMx_Disable(pwm->port); - return 0; -} - - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_spi.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_spi.c deleted file mode 100644 index 798e914b7c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_spi.c +++ /dev/null @@ -1,275 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - -#include "bl808_glb_gpio.h" -#include "hosal_spi.h" -#include "blog.h" - -static void spi_basic_init(hosal_spi_dev_t *arg) -{ - hosal_spi_dev_t *hw_arg = arg; - SPI_CFG_Type spicfg; - SPI_FifoCfg_Type fifocfg; - SPI_ID_Type spi_id; - - spi_id = hw_arg->port; - - /* clock config */ - SPI_SetClock(spi_id, hw_arg->config.freq); - - /* spi config */ - spicfg.deglitchEnable = DISABLE; - spicfg.slavePin = SPI_SLAVE_PIN_4; - spicfg.continuousEnable = ENABLE; - spicfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; - spicfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; - if (hw_arg->config.polar_phase == 0) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_0; - spicfg.clkPolarity = SPI_CLK_POLARITY_LOW; - } else if (hw_arg->config.polar_phase == 1) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_1; - spicfg.clkPolarity = SPI_CLK_POLARITY_LOW; - } else if (hw_arg->config.polar_phase == 2) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_0; - spicfg.clkPolarity = SPI_CLK_POLARITY_HIGH; - } else if (hw_arg->config.polar_phase == 3) { - spicfg.clkPhaseInv = SPI_CLK_PHASE_INVERSE_1; - spicfg.clkPolarity = SPI_CLK_POLARITY_HIGH; - } else { - blog_error("node support polar_phase \r\n"); - } - spicfg.frameSize = SPI_FRAME_SIZE_8; - SPI_Init(spi_id, &spicfg); - - if (hw_arg->config.mode == 0) { - SPI_Disable(spi_id, SPI_WORK_MODE_MASTER); - } else { - SPI_Disable(spi_id, SPI_WORK_MODE_SLAVE); - } - SPI_IntMask(spi_id, SPI_INT_ALL, MASK); - - /* fifo */ - fifocfg.txFifoThreshold = 1; - fifocfg.rxFifoThreshold = 1; - if (hw_arg->config.dma_enable) { - fifocfg.txFifoDmaEnable = ENABLE; - fifocfg.rxFifoDmaEnable = ENABLE; - SPI_FifoConfig(spi_id,&fifocfg); - } else { - fifocfg.txFifoDmaEnable = DISABLE; - fifocfg.rxFifoDmaEnable = DISABLE; - SPI_FifoConfig(spi_id,&fifocfg); - blog_info("spi no dma mode\r\n"); - } -} - -static int hosal_spi_trans(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data, uint32_t length, uint32_t timeout) -{ - int ret = -1; - - /* Clear tx and rx fifo */ - SPI_ClrTxFifo(spi->port); - SPI_ClrRxFifo(spi->port); - - if (spi->config.mode == 0) { - SPI_Enable(spi->port, SPI_WORK_MODE_MASTER); - } else { - SPI_Enable(spi->port, SPI_WORK_MODE_SLAVE); - } - - if (tx_data && rx_data) - ret = SPI_SendRecvData(spi->port, tx_data, rx_data, length, SPI_TIMEOUT_DISABLE); - else if (tx_data) - ret = SPI_SendData(spi->port, tx_data, length, SPI_TIMEOUT_DISABLE); - else if (rx_data) - ret = SPI_ReceiveData(spi->port, rx_data, length, SPI_TIMEOUT_DISABLE); - - if (spi->config.mode == 0) { - SPI_Disable(spi->port, SPI_WORK_MODE_MASTER); - } else { - SPI_Disable(spi->port, SPI_WORK_MODE_SLAVE); - } - return ret; -} - -static void hosal_spi_gpio_init(hosal_spi_dev_t *arg) -{ - if (!arg) { - blog_error("arg err.\r\n"); - return; - } - - GLB_GPIO_Type gpiopins[3]; - gpiopins[0] = arg->config.pin_clk; - gpiopins[1] = arg->config.pin_mosi; - gpiopins[2] = arg->config.pin_miso; - GLB_GPIO_Func_Init(GPIO_FUN_SPI0, gpiopins, sizeof(gpiopins)/sizeof(gpiopins[0])); - - if (arg->config.mode == 0) { - if(arg->port == SPI0_ID) { - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER); - } else { - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER); - } - } else { - if(arg->port == SPI0_ID) { - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE); - } else { - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_SLAVE); - } - } - - return; -} - -int hosal_spi_init(hosal_spi_dev_t *spi) -{ - hosal_spi_dev_t *dev = spi; - if (NULL == spi ) { - blog_error("arg err.\r\n"); - } - - hosal_spi_gpio_init(dev); - spi_basic_init(dev); - if (dev->config.dma_enable) { - blog_error("unsupport.\r\n"); - return -1; - } - return 0; -} - -int hosal_spi_set_cs(uint8_t pin, uint8_t value) -{ - GLB_GPIO_Cfg_Type cfg; - cfg.gpioPin = pin; - cfg.gpioFun = GPIO_FUN_GPIO; - cfg.gpioMode = GPIO_MODE_OUTPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 0; - cfg.smtCtrl = 1; - - if (GLB_GPIO_Get_Fun(pin) != GPIO_FUN_GPIO) - GLB_GPIO_Init(&cfg); - GLB_GPIO_Write(pin, value); - return 0; -} - -int hosal_spi_irq_callback_set(hosal_spi_dev_t *spi, hosal_spi_irq_t pfn, void *p_arg) -{ - if (NULL == spi ) { - blog_error("not init.\r\n"); - return -1; - } - - spi->cb = pfn; - spi->p_arg = p_arg; - return 0; -} - -int hosal_spi_finalize(hosal_spi_dev_t *spi) -{ - if (NULL == spi ) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - return -1; - } - SPI_DeInit(spi->port); - return 0; -} - -int hosal_spi_send(hosal_spi_dev_t *spi, const uint8_t *data, uint32_t size, uint32_t timeout) -{ - int ret; - - if (NULL == spi || data == NULL) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - ret = -1; - } else { - ret = hosal_spi_trans(spi, (uint8_t *)data, NULL, size, timeout); - } - return ret; -} - -int hosal_spi_recv(hosal_spi_dev_t *spi, uint8_t *data, uint16_t size, uint32_t timeout) -{ - int ret; - - if (NULL == spi || data == NULL) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - ret = -1; - } else { - ret = hosal_spi_trans(spi, NULL, data, size, timeout); - } - return ret; -} - -int hosal_spi_send_recv(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data, uint16_t size, uint32_t timeout) -{ - int ret; - - if (NULL == spi || tx_data == NULL || rx_data == NULL) { - blog_error("not init.\r\n"); - return -1; - } - - if (spi->config.dma_enable) { - blog_error("unsupport.\r\n"); - ret = -1; - } else { - ret = hosal_spi_trans(spi, tx_data, rx_data, size, timeout); - } - return ret; -} - diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_uart.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_uart.c deleted file mode 100644 index 52a61f072a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/hosal_uart.c +++ /dev/null @@ -1,557 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -//FIXME no BL808/BL606p header file including is Allowed here -#ifdef BL808 -#include -#include -#elif defined(BL606P) -#include -#include -#else -#error "Use CHIP BL808/BL606P for this module" -#endif - - -#include "bl_uart.h" -#include "bl_irq.h" -#include "hosal_uart.h" -#include "blog.h" - -// static const uint32_t g_uart_addr[2] = {UART0_BASE, UART1_BASE}; - -static void gpio_init(uint8_t id, uint8_t tx_pin, uint8_t rx_pin, uint8_t cts_pin, uint8_t rts_pin) -{ - GLB_GPIO_Cfg_Type cfg; - GLB_UART_SIG_FUN_Type tx_sigfun, rx_sigfun; - - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = 7; - - cfg.gpioPin = rx_pin; - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - GLB_GPIO_Init(&cfg); - - cfg.gpioPin = tx_pin; - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - GLB_GPIO_Init(&cfg); - - /* select uart gpio function */ - if (id == 0) { - tx_sigfun = GLB_UART_SIG_FUN_UART0_TXD; - rx_sigfun = GLB_UART_SIG_FUN_UART0_RXD; - } else { - tx_sigfun = GLB_UART_SIG_FUN_UART1_TXD; - rx_sigfun = GLB_UART_SIG_FUN_UART1_RXD; - } - - // clk - //GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, 0); - - GLB_UART_Fun_Sel(tx_pin%12, tx_sigfun); - GLB_UART_Fun_Sel(rx_pin%12, rx_sigfun); -} - -static void __uart_rx_irq(void *p_arg) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - if (uart->rx_cb) { - uart->rx_cb(uart->p_rxarg); - } -} - -static void __uart_tx_irq(void *p_arg) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - if (uart->tx_cb) { - uart->tx_cb(uart->p_txarg); - } -} -#if 0 -static void __uart_rx_dma_irq(void *p_arg, uint32_t flag) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - - if (flag != HOSAL_DMA_INT_TRANS_COMPLETE) { - blog_error("DMA RX TRANS ERROR\r\n"); - } - - if (uart->rxdma_cb) { - uart->rxdma_cb(uart->p_rxdma_arg); - } -} - -static void __uart_tx_dma_irq(void *p_arg, uint32_t flag) -{ - hosal_uart_dev_t *uart = (hosal_uart_dev_t *)p_arg; - - if (flag != HOSAL_DMA_INT_TRANS_COMPLETE) { - blog_error("DMA TX TRANS ERROR\r\n"); - } - - if (uart->txdma_cb) { - uart->txdma_cb(uart->p_txdma_arg); - } -} - -static int __uart_dma_txcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cfg) -{ - if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) { - return -1; - } - DMA_Channel_Cfg_Type txchCfg = { - (uint32_t)dma_cfg->dma_buf, - g_uart_addr[uart->port] + UART_FIFO_WDATA_OFFSET, - dma_cfg->dma_buf_size, - DMA_TRNS_M2P, - DMA_CH0, - DMA_TRNS_WIDTH_8BITS, - DMA_TRNS_WIDTH_8BITS, - DMA_BURST_SIZE_4, - DMA_BURST_SIZE_4, - DMA_MINC_ENABLE, - DMA_PINC_DISABLE, - DMA_REQ_NONE, - DMA_REQ_UART0_TX, - }; - UART_FifoCfg_Type fifoCfg = - { - .txFifoDmaThreshold = 0x10, - .rxFifoDmaThreshold = 0x10, - .txFifoDmaEnable = ENABLE, - .rxFifoDmaEnable = DISABLE, - }; - - if (uart->dma_tx_chan >= 0) { - DMA_Channel_Update_SrcMemcfg(uart->dma_tx_chan, - (uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size); - return 0; - } - - uart->dma_tx_chan = hosal_dma_chan_request(0); - if (uart->dma_tx_chan < 0) { - blog_error("dma_tx_chan request failed !\r\n"); - return -1; - } - - hosal_dma_chan_stop(uart->dma_tx_chan); - - /* FIFO Config*/ - fifoCfg.rxFifoDmaEnable = (uart->dma_rx_chan < 0) ? DISABLE : ENABLE; - UART_FifoConfig(uart->port, &fifoCfg); - - txchCfg.ch = uart->dma_tx_chan; - txchCfg.dstPeriph = (uart->port == 0) ? DMA_REQ_UART0_TX : DMA_REQ_UART1_TX; - DMA_Channel_Init(&txchCfg); - hosal_dma_irq_callback_set(uart->dma_tx_chan, __uart_tx_dma_irq, (void *)uart); - - return 0; -} - -static int __uart_dma_rxcfg(hosal_uart_dev_t *uart, hosal_uart_dma_cfg_t *dma_cfg) -{ - if (dma_cfg->dma_buf == NULL || dma_cfg->dma_buf_size == 0) { - return -1; - } - - DMA_Channel_Cfg_Type rxchCfg = { - g_uart_addr[uart->port] + UART_FIFO_RDATA_OFFSET, - (uint32_t)dma_cfg->dma_buf, - dma_cfg->dma_buf_size, - DMA_TRNS_P2M, - DMA_CH0, - DMA_TRNS_WIDTH_8BITS, - DMA_TRNS_WIDTH_8BITS, - DMA_BURST_SIZE_16, - DMA_BURST_SIZE_16, - DMA_PINC_DISABLE, - DMA_MINC_ENABLE, - DMA_REQ_UART0_RX, - DMA_REQ_NONE, - }; - UART_FifoCfg_Type fifoCfg = - { - .txFifoDmaThreshold = 0x10, - .rxFifoDmaThreshold = 0x10, - .txFifoDmaEnable = DISABLE, - .rxFifoDmaEnable = ENABLE, - }; - - if (uart->dma_rx_chan >= 0) { - DMA_Channel_Update_DstMemcfg(uart->dma_rx_chan, - (uint32_t)dma_cfg->dma_buf, dma_cfg->dma_buf_size); - return 0; - } - - uart->dma_rx_chan = hosal_dma_chan_request(0); - if (uart->dma_rx_chan < 0) { - blog_error("dma_rx_chan request failed !\r\n"); - return -1; - } - - hosal_dma_chan_stop(uart->dma_rx_chan); - - /* FIFO Config*/ - fifoCfg.txFifoDmaEnable = (uart->dma_tx_chan < 0) ? DISABLE : ENABLE; - UART_FifoConfig(uart->port, &fifoCfg); - - rxchCfg.ch = uart->dma_rx_chan; - rxchCfg.srcPeriph = (uart->port == 0) ? DMA_REQ_UART0_RX : DMA_REQ_UART1_RX; - - DMA_Channel_Init(&rxchCfg); - hosal_dma_irq_callback_set(uart->dma_rx_chan, __uart_rx_dma_irq, (void *)uart); - - return 0; -} -#endif -static void __uart_config_set(hosal_uart_dev_t *uart, const hosal_uart_config_t *cfg) -{ - const uint8_t uart_div = 3; - uint8_t id = uart->port; - -#if 0 - UART_CFG_Type uartCfg = - { - 80*1000*1000, /* UART clock */ - 2000000, /* UART Baudrate */ - UART_DATABITS_8, /* UART data bits length */ - UART_STOPBITS_1, /* UART data stop bits length */ - UART_PARITY_NONE, /* UART no parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - UART_LSB_FIRST /* UART each data byte is send out LSB-first */ - }; - - uartCfg.baudRate = cfg->baud_rate; - uartCfg.dataBits = (UART_DataBits_Type)cfg->data_width; - uartCfg.parity = (UART_Parity_Type)cfg->parity; - - if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 0; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_RTS) { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 1; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS_RTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 1; - } else { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 0; - } - - //uartCfg.uartClk = (160 * 1000 * 1000) / (uart_div + 1); - - /* Disable uart before config */ - UART_Disable(id, UART_TXRX); - - /* UART init */ - UART_Init(id, &uartCfg); -#endif - if (cfg->mode == HOSAL_UART_MODE_INT) { - bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart); - bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart); - bl_uart_int_enable(uart->port); - bl_uart_int_tx_disable(uart->port); - } else { - bl_uart_int_disable(uart->port); - } - - /* Enable uart */ - UART_Enable(id, UART_TXRX); -} - -int hosal_uart_init(hosal_uart_dev_t *uart) -{ - static uint8_t uart_clk_init = 0; - const uint8_t uart_div = 3; - hosal_uart_config_t *cfg = &uart->config; - uint8_t id; - - UART_CFG_Type uartCfg = - { - 80*1000*1000, /* UART clock */ - 2000000, /* UART Baudrate */ - UART_DATABITS_8, /* UART data bits length */ - UART_STOPBITS_1, /* UART data stop bits length */ - UART_PARITY_NONE, /* UART no parity */ - DISABLE, /* Disable auto flow control */ - DISABLE, /* Disable rx input de-glitch function */ - DISABLE, /* Disable RTS output SW control mode */ - UART_LSB_FIRST /* UART each data byte is send out LSB-first */ - }; - UART_FifoCfg_Type fifoCfg = - { - .txFifoDmaThreshold = 0x10, - .rxFifoDmaThreshold = 0x10, - .txFifoDmaEnable = DISABLE, - .rxFifoDmaEnable = DISABLE, - }; - - /* enable clk */ - -#if 0 - if (0 == uart_clk_init) { - GLB_Set_UART_CLK(1, HBN_UART_CLK_160M, uart_div); - uart_clk_init = 1; - } -#endif - - uart->dma_rx_chan = -1; - uart->dma_tx_chan = -1; - id = cfg->uart_id; - uart->port = cfg->uart_id; - - /* gpio init */ - //gpio_init(id, cfg->tx_pin, cfg->rx_pin, cfg->cts_pin, cfg->rts_pin); - - uartCfg.baudRate = cfg->baud_rate; - uartCfg.dataBits = (UART_DataBits_Type)cfg->data_width; - uartCfg.parity = (UART_Parity_Type)cfg->parity; - - if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 0; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_RTS) { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 1; - } else if (cfg->flow_control == HOSAL_FLOW_CONTROL_CTS_RTS) { - uartCfg.ctsFlowControl = 1; - uartCfg.rtsSoftwareControl = 1; - } else { - uartCfg.ctsFlowControl = 0; - uartCfg.rtsSoftwareControl = 0; - } - - //uartCfg.uartClk = (40 * 1000 * 1000) / (uart_div + 1); - - /* Disable all interrupt */ - UART_IntMask(id, UART_INT_ALL, MASK); - - /* Disable uart before config */ - UART_Disable(id, UART_TXRX); - - if (UART_GetRxBusBusyStatus(id) == SET) { - UART_DeInit(id); - } - - /* UART init */ - UART_Init(id, &uartCfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(id, ENABLE); - - /* FIFO Config*/ - UART_FifoConfig(id, &fifoCfg); - - if (cfg->mode == HOSAL_UART_MODE_INT) { - bl_uart_int_tx_notify_register(uart->port, __uart_tx_irq, uart); - bl_uart_int_rx_notify_register(uart->port, __uart_rx_irq, uart); - bl_uart_int_enable(uart->port); - bl_uart_int_tx_disable(uart->port); - } else { - bl_uart_int_disable(uart->port); - } - - /* Enable uart */ - UART_Enable(id, UART_TXRX); - return 0; -} - -int hosal_uart_receive(hosal_uart_dev_t *uart, void *data, uint32_t expect_size) -{ - int ch; - uint32_t counter = 0; - - while (counter < expect_size) { - if ((ch = bl_uart_data_recv(uart->port)) < 0) { - break; - } - ((uint8_t*)data)[counter] = ch; - counter++; - } - return counter; -} - -int hosal_uart_send(hosal_uart_dev_t *uart, const void *data, uint32_t size) -{ - uint32_t i = 0; - - while (i < size) { - bl_uart_data_send(uart->port, ((uint8_t*)data)[i]); - i++; - } - return i; -} - -int hosal_uart_ioctl(hosal_uart_dev_t *uart, int ctl, void *p_arg) -{ -#if 0 - hosal_uart_dma_cfg_t *dma_cfg; -#endif - - switch (ctl) { - case HOSAL_UART_BAUD_SET: - uart->config.baud_rate = (uint32_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_BAUD_GET: - if (p_arg) { - *(uint32_t *)p_arg = uart->config.baud_rate; - } - break; - case HOSAL_UART_DATA_WIDTH_SET: - uart->config.data_width = (hosal_uart_data_width_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_DATA_WIDTH_GET: - if (p_arg) { - *(hosal_uart_data_width_t *)p_arg = uart->config.data_width; - } - break; - case HOSAL_UART_STOP_BITS_SET: - uart->config.stop_bits = (hosal_uart_stop_bits_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_STOP_BITS_GET: - if (p_arg) { - *(hosal_uart_stop_bits_t *)p_arg = uart->config.stop_bits; - } - break; - case HOSAL_UART_FLOWMODE_SET: - uart->config.flow_control = (hosal_uart_flow_control_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_FLOWSTAT_GET: - if (p_arg) { - *(hosal_uart_flow_control_t *)p_arg = uart->config.flow_control; - } - break; - case HOSAL_UART_PARITY_SET: - uart->config.parity = (hosal_uart_parity_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_PARITY_GET: - if (p_arg) { - *(hosal_uart_parity_t *)p_arg = uart->config.parity; - } - break; - case HOSAL_UART_MODE_SET: - uart->config.mode = (hosal_uart_mode_t)p_arg; - __uart_config_set(uart, &uart->config); - break; - case HOSAL_UART_MODE_GET: - if (p_arg) { - *(hosal_uart_mode_t *)p_arg = uart->config.mode; - } - break; - case HOSAL_UART_FREE_TXFIFO_GET: - if (p_arg) { - *(uint32_t *)p_arg = UART_GetTxFifoCount(uart->port); - } - break; - case HOSAL_UART_FREE_RXFIFO_GET: - if (p_arg) { - *(uint32_t *)p_arg = UART_GetRxFifoCount(uart->port); - } - break; - case HOSAL_UART_FLUSH: - bl_uart_flush(uart->port); - break; - case HOSAL_UART_TX_TRIGGER_ON: - bl_uart_int_tx_enable(uart->port); - break; - case HOSAL_UART_TX_TRIGGER_OFF: - bl_uart_int_tx_disable(uart->port); - break; -#if 0 - case HOSAL_UART_DMA_TX_START: - dma_cfg = (hosal_uart_dma_cfg_t *)p_arg; - if (__uart_dma_txcfg(uart, dma_cfg) != 0) { - return -1; - } - hosal_dma_chan_start(uart->dma_tx_chan); - break; - case HOSAL_UART_DMA_RX_START: - dma_cfg = (hosal_uart_dma_cfg_t *)p_arg; - if (__uart_dma_rxcfg(uart, dma_cfg) != 0) { - return -1; - } - hosal_dma_chan_start(uart->dma_rx_chan); - break; -#endif - default : - return -1; - } - return 0; -} - -int hosal_uart_callback_set(hosal_uart_dev_t *uart, - int callback_type, - hosal_uart_callback_t pfn_callback, - void *arg) -{ - if (callback_type == HOSAL_UART_TX_CALLBACK) { - uart->tx_cb = pfn_callback; - uart->p_txarg = arg; - } else if (callback_type == HOSAL_UART_RX_CALLBACK) { - uart->rx_cb = pfn_callback; - uart->p_rxarg = arg; - } -#if 0 - else if (callback_type == HOSAL_UART_TX_DMA_CALLBACK) { - uart->txdma_cb = pfn_callback; - uart->p_txdma_arg = arg; - } else if (callback_type == HOSAL_UART_RX_DMA_CALLBACK) { - uart->rxdma_cb = pfn_callback; - uart->p_rxdma_arg = arg; - } -#endif - return 0; -} - -int hosal_uart_finalize(hosal_uart_dev_t *uart) -{ - bl_uart_int_disable(uart->port); - UART_Disable(uart->port, UART_TXRX); -#if 0 - if (uart->dma_rx_chan > 0) { - hosal_dma_chan_release(uart->dma_rx_chan); - } - if (uart->dma_tx_chan > 0) { - hosal_dma_chan_release(uart->dma_tx_chan); - } -#endif - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/phy_8720.c b/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/phy_8720.c deleted file mode 100644 index c8cd6e0b5f..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/bl808_e907_hal/phy_8720.c +++ /dev/null @@ -1,419 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "hal_emac.h" -#include "ethernet_phy.h" - -/* LAN8720 PHY Address*/ -#define EMAC_PHY_ADDRESS 0x00U -#define PHY_LINK_TO ((uint32_t)0x00000FFFU) -#define PHY_AUTONEGO_COMPLETED_TO ((uint32_t)0x00000FFFU) -/* Section 3: Common PHY Registers */ -#define PHY_BCR ((uint16_t)0x00U) /*!< Transceiver Basic Control Register */ -#define PHY_BSR ((uint16_t)0x01U) /*!< Transceiver Basic Status Register */ -#define PHY_BSR_100BASETXFULL (1 << 14) -#define PHY_BSR_100BASETXHALF (1 << 13) -#define PHY_BSR_10BASETXFULL (1 << 12) -#define PHY_BSR_10BASETXHALF (1 << 11) -#define PHY_RESET ((uint16_t)0x8000U) /*!< PHY Reset */ -#define PHY_LOOPBACK ((uint16_t)0x4000U) /*!< Select loop-back mode */ -#define PHY_FULLDUPLEX_100M ((uint16_t)0x2100U) /*!< Set the full-duplex mode at 100 Mb/s */ -#define PHY_HALFDUPLEX_100M ((uint16_t)0x2000U) /*!< Set the half-duplex mode at 100 Mb/s */ -#define PHY_FULLDUPLEX_10M ((uint16_t)0x0100U) /*!< Set the full-duplex mode at 10 Mb/s */ -#define PHY_HALFDUPLEX_10M ((uint16_t)0x0000U) /*!< Set the half-duplex mode at 10 Mb/s */ -#define PHY_AUTONEGOTIATION ((uint16_t)0x1000U) /*!< Enable auto-negotiation function */ -#define PHY_RESTART_AUTONEGOTIATION ((uint16_t)0x0200U) /*!< Restart auto-negotiation function */ -#define PHY_POWERDOWN ((uint16_t)0x0800U) /*!< Select the power down mode */ -#define PHY_ISOLATE ((uint16_t)0x0400U) /*!< Isolate PHY from MII */ -#define PHY_AUTONEGO_COMPLETE ((uint16_t)0x0020U) /*!< Auto-Negotiation process completed */ -#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */ -#define PHY_JABBER_DETECTION ((uint16_t)0x0002U) /*!< Jabber condition detected */ - -#define PHY_PHYID1 ((uint16_t)0x02U) /*!< PHY ID 1 */ -#define PHY_PHYID2 ((uint16_t)0x03U) /*!< PHY ID 2 */ -#define PHY_ADVERTISE ((uint16_t)0x04U) /*!< Auto-negotiation advertisement */ -#define PHY_ADVERTISE_100BASETXFULL (1 << 8) -#define PHY_ADVERTISE_100BASETXHALF (1 << 7) -#define PHY_ADVERTISE_10BASETXFULL (1 << 6) -#define PHY_ADVERTISE_10BASETXHALF (1 << 5) -#define PHY_ADVERTISE_8023 (1 << 0) -#define PHY_LPA ((uint16_t)0x05U) /*!< Auto-negotiation link partner base page ability */ -#define PHY_EXPANSION ((uint16_t)0x06U) /*!< Auto-negotiation expansion */ -/* Section 4: Extended PHY Registers */ -#define PHY_CTRL_STATUS ((uint16_t)17U) /*!< PHY MODE CONTROL/STATUS REGISTER Offset */ -#define PHY_CTRL_STATUS_EDPWRDOWN (1 << 13) /*!< EDPWRDOWN */ -#define PHY_CTRL_STATUS_ENERGYON (1 << 1) /*!< ENERGYON */ - -#define PHY_SPECIAL_MODES ((uint16_t)18U) /*!< PHY SPECIAL MODES REGISTER Offset */ -#define PHY_SPECIAL_MODES_MODE (7 << 5) /*!< Transceiver mode of operation */ -#define PHY_SPECIAL_MODES_MODE_PWRDOWN (6 << 5) /*!< All capable. Auto-negotiation enabled */ -#define PHY_SPECIAL_MODES_MODE_ALL (7 << 5) /*!< All capable. Auto-negotiation enabled */ -#define PHY_SPECIAL_MODES_PHYAD (0x1F << 0) /*!< PHY Address */ - -#define PHY_SR ((uint16_t)0x1FU) /*!< PHY special control/ status register Offset */ -#define PHY_SR_SPEED_OFFSET (2) -#define PHY_SR_SPEED_MASK (0x7 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_10BASETXHALF (0x1 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_10BASETXFULL (0x5 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_100BASETXHALF (0x2 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_100BASETXFULL (0x6 << PHY_SR_SPEED_OFFSET) -#define PHY_SR_SPEED_MODE_COMPARE(status, mode) (!!(mode == (status & PHY_SR_SPEED_MASK))) -#define PHY_SPEED_STATUS ((uint16_t)0x0004U) /*!< PHY Speed mask */ -#define PHY_DUPLEX_STATUS ((uint16_t)0x0010U) /*!< PHY Duplex mask */ -#define PHY_ISFR ((uint16_t)0x1DU) /*!< PHY Interrupt Source Flag register Offset */ -#define PHY_ISFR_INT4 ((uint16_t)0x0010U) /*!< PHY Link down inturrupt */ - -static emac_phy_cfg_t *phy_8720_cfg = NULL; - -int phy_8720_reset(void) -{ - int timeout = 1000; - uint16_t regval = PHY_RESET; - - /* pull the PHY from power down mode if it is in */ - if (0 != emac_phy_reg_read(PHY_SPECIAL_MODES, ®val)) { - return -1; - } - - if (PHY_SPECIAL_MODES_MODE_PWRDOWN == (regval & PHY_SPECIAL_MODES_MODE)) { - if (emac_phy_reg_write(PHY_SPECIAL_MODES, regval | PHY_SPECIAL_MODES_MODE_ALL) != 0) { - return -1; - } - } - - /* disable energy detect powerdown mode for cable detect, this increase the power by 220mW */ - if (0 != emac_phy_reg_read(PHY_CTRL_STATUS, ®val)) { - return -1; - } - - if (emac_phy_reg_write(PHY_CTRL_STATUS, regval & (~PHY_CTRL_STATUS_EDPWRDOWN)) != 0) { - return -1; - } - - /* do sw reset */ - if (emac_phy_reg_write(PHY_BCR, PHY_RESET) != 0) { - return -1; - } - - for (; timeout; timeout--) { - if (0 != emac_phy_reg_read(PHY_BCR, ®val)) { - return -1; - } - - if (!(regval & PHY_RESET)) { - return 0; - } - - arch_delay_ms(1); - } - - return -1; -} - -int phy_8720_auto_negotiate(emac_phy_cfg_t *cfg) -{ - uint16_t regval = 0; - uint16_t phyid1 = 0, phyid2 = 0; - uint16_t advertise = 0; - uint16_t lpa = 0; - uint32_t timeout = 100; //10s,in 100ms - - if (0 != emac_phy_reg_read(PHY_PHYID1, &phyid1)) { - // MSG("read emac phy id 1 error\r\n"); - return -1; - } - - if (0 != emac_phy_reg_read(PHY_PHYID2, &phyid2)) { - MSG("read emac phy id 2 error\r\n"); - return -1; - } - MSG("emac phy id 1 =%08x\r\n",(unsigned int )phyid1); - MSG("emac phy id 2 =%08x\r\n",(unsigned int )phyid2); - if (cfg->phy_id != (((phyid1 << 16) | phyid2) & 0x000FFFF0)) { - /* ID error */ - return -1; - } else { - cfg->phy_id = (phyid1 << 16) | phyid2; - } - - if (0 != emac_phy_reg_read(PHY_BCR, ®val)) { - return -1; - } - - regval &= ~PHY_AUTONEGOTIATION; - regval &= ~(PHY_LOOPBACK | PHY_POWERDOWN); - regval |= PHY_ISOLATE; - - if (emac_phy_reg_write(PHY_BCR, regval) != 0) { - return -1; - } - - /* set advertisement mode */ - advertise = PHY_ADVERTISE_100BASETXFULL | PHY_ADVERTISE_100BASETXHALF | - PHY_ADVERTISE_10BASETXFULL | PHY_ADVERTISE_10BASETXHALF | - PHY_ADVERTISE_8023; - - if (emac_phy_reg_write(PHY_ADVERTISE, advertise) != 0) { - return -1; - } - - arch_delay_ms(16); - - if (0 != emac_phy_reg_read(PHY_BCR, ®val)) { - return -1; - } - - arch_delay_ms(16); - regval |= (PHY_FULLDUPLEX_100M | PHY_AUTONEGOTIATION); - - if (emac_phy_reg_write(PHY_BCR, regval) != 0) { - return -1; - } - - arch_delay_ms(16); - regval |= PHY_RESTART_AUTONEGOTIATION; - regval &= ~PHY_ISOLATE; - - if (emac_phy_reg_write(PHY_BCR, regval) != 0) { - return -1; - } - - arch_delay_ms(100); - - while (1) { - if (0 != emac_phy_reg_read(PHY_BSR, ®val)) { - return -1; - } - - if (regval & PHY_AUTONEGO_COMPLETE) { - /* complete */ - break; - } - - if (!(--timeout)) { - return -1; - } - - arch_delay_ms(100); - } - - arch_delay_ms(100); - - if (0 != emac_phy_reg_read(PHY_LPA, &lpa)) { - return -1; - } - - if (((advertise & lpa) & PHY_ADVERTISE_100BASETXFULL) != 0) { - /* 100BaseTX and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_READY; - } else if (((advertise & lpa) & PHY_ADVERTISE_10BASETXFULL) != 0) { - /* 10BaseT and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_READY; - } else if (((advertise & lpa) & PHY_ADVERTISE_100BASETXHALF) != 0) { - /* 100BaseTX and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_READY; - } else if (((advertise & lpa) & PHY_ADVERTISE_10BASETXHALF) != 0) { - /* 10BaseT and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_READY; - } - - return 0; -} - -int phy_8720_link_up(emac_phy_cfg_t *cfg) -{ - uint16_t phy_bsr = 0; - uint16_t phy_sr = 0; - - arch_delay_ms(16); - - if (0 != emac_phy_reg_read(PHY_BSR, &phy_bsr)) { - return -1; - } - - arch_delay_ms(16); - - if (!(PHY_LINKED_STATUS & phy_bsr)) { - return ERROR; - } - - arch_delay_ms(16); - - if (0 != emac_phy_reg_read(PHY_SR, &phy_sr)) { - return -1; - } - - if ((phy_bsr & PHY_BSR_100BASETXFULL) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_100BASETXFULL)) { - /* 100BaseTX and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_UP; - } else if ((phy_bsr & PHY_BSR_10BASETXFULL) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_10BASETXFULL)) { - /* 10BaseT and Full Duplex */ - cfg->full_duplex = 1; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_UP; - } else if ((phy_bsr & PHY_BSR_100BASETXHALF) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_100BASETXHALF)) { - /* 100BaseTX and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 100; - cfg->phy_state = PHY_STATE_UP; - } else if ((phy_bsr & PHY_BSR_10BASETXHALF) && PHY_SR_SPEED_MODE_COMPARE(phy_sr, PHY_SR_SPEED_10BASETXHALF)) { - /* 10BaseT and half Duplex */ - cfg->full_duplex = 0; - cfg->speed = 10; - cfg->phy_state = PHY_STATE_UP; - } else { - /* 10BaseT and half Duplex */ - cfg->full_duplex = -1; - cfg->speed = -1; - cfg->phy_state = PHY_STATE_DOWN; - return -1; - } - - return 0; -} - -/****************************************************************************** - * @brief Use energy detector for cable plug in/out detect. - * - * @param cfg: EMAC PHY configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -int phy_8720_poll_cable_status(emac_phy_cfg_t *cfg) -{ - uint16_t phy_regval = 0; - - CHECK_PARAM(NULL != phy_8720_cfg); - - if (0 != emac_phy_reg_read(PHY_CTRL_STATUS, &phy_regval)) { - return -1; - } - - phy_8720_cfg->phy_state = (PHY_CTRL_STATUS_ENERGYON & phy_regval) ? - PHY_STATE_UP : - PHY_STATE_DOWN; - - return !!(PHY_CTRL_STATUS_ENERGYON & phy_regval); -} - -/****************************************************************************/ /** - * @brief Initialize EMAC PHY module - * - * @param cfg: EMAC PHY configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -int emac_phy_init(emac_phy_cfg_t *cfg) -{ - uint16_t phyReg; - - CHECK_PARAM(NULL != cfg); - - phy_8720_cfg = cfg; - - emac_phy_set_address(cfg->phy_address); - - if (0 != phy_8720_reset()) { - return -1; - } - - if (cfg->auto_negotiation) { - /* - uint32_t cnt=0; - do{ - if(emac_phy_reg_read(PHY_BSR, &phyReg) != SUCCESS){ - return ERROR; - } - cnt++; - if(cnt>PHY_LINK_TO){ - return ERROR; - } - }while((phyReg & PHY_LINKED_STATUS) != PHY_LINKED_STATUS); - */ - if (0 != phy_8720_auto_negotiate(cfg)) { - return -1; - } - } else { - if (emac_phy_reg_read(PHY_BCR, &phyReg) != 0) { - return -1; - } - - phyReg &= (~PHY_FULLDUPLEX_100M); - - if (cfg->speed == 10) { - if (cfg->full_duplex == 1) { - phyReg |= PHY_FULLDUPLEX_10M; - } else { - phyReg |= PHY_HALFDUPLEX_10M; - } - } else { - if (cfg->full_duplex == 1) { - phyReg |= PHY_FULLDUPLEX_100M; - } else { - phyReg |= PHY_HALFDUPLEX_100M; - } - } - - if ((emac_phy_reg_write(PHY_BCR, phyReg)) != 0) { - return -1; - } - } - - emac_phy_config_full_duplex(cfg->full_duplex); - - return phy_8720_link_up(cfg); -} - -emac_phy_status_t ethernet_phy_status_get() -{ - CHECK_PARAM(NULL != phy_8720_cfg); - - if ((100 == phy_8720_cfg->speed) && - (phy_8720_cfg->full_duplex) && - (PHY_STATE_UP == phy_8720_cfg->phy_state)) { - return EMAC_PHY_STAT_100MBITS_FULLDUPLEX; - } else if (PHY_STATE_UP == phy_8720_cfg->phy_state) { - return EMAC_PHY_STAT_LINK_UP; - } else { - return EMAC_PHY_STAT_LINK_DOWN; - } -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_adc.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_adc.h deleted file mode 100644 index 66fbecf04a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_adc.h +++ /dev/null @@ -1,238 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_ADC_H_ -#define __HOSAL_ADC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "hosal_dma.h" - -/** @addtogroup hosal_adc ADC - * HOSAL ADC API - * - * @{ - */ - -#define HOSAL_WAIT_FOREVER 0xFFFFFFFFU /**< @brief Define the wait forever timeout macro */ - -/** - * @brief ADC interrupt events - */ -typedef enum __ADC_INT_EVENTS__{ - HOSAL_ADC_INT_OV, /**< @brief Overrun error */ - HOSAL_ADC_INT_EOS, /**< @brief End of sample */ - HOSAL_ADC_INT_DMA_TRH, /**< @brief DMA transceive half */ - HOSAL_ADC_INT_DMA_TRC, /**< @brief DMA transceive complete */ - HOSAL_ADC_INT_DMA_TRE, /**< @briefDMA transceive error */ -} hosal_adc_event_t; - -/** - * @brief ADC data type - */ -typedef struct { - uint32_t size; /**< @brief sampled data size */ - void *data; /**< @brief sampled data, aligned with resolution (until the next power of two) */ -} hosal_adc_data_t; - -/** - * @brief ADC MODE type - */ -typedef enum { - HOSAL_ADC_ONE_SHOT, /**< @brief Single time sampling */ - HOSAL_ADC_CONTINUE /**< @brief Continuous sampling */ -} hosal_adc_sample_mode_t; - -/** - * @brief Define ADC config args - */ -typedef struct { - uint32_t sampling_freq; /**< @brief sampling frequency in Hz */ - uint32_t pin; /**< @brief adc pin */ - hosal_adc_sample_mode_t mode; /**< @brief adc sampling mode */ - uint8_t sample_resolution; /**< @brief adc sampling resolution */ -} hosal_adc_config_t; - -/** - * @brief ADC interrupt function - * - *@param[in] parg Set the custom parameters specified - * - */ -typedef void (*hosal_adc_irq_t)(void *parg); - -/** - * @brief Define ADC dev hosal handle - */ -typedef struct { - uint8_t port; /**< @brief adc port */ - hosal_adc_config_t config; /**< @brief adc config */ - hosal_dma_chan_t dma_chan; /**< @brief adc dma channel */ - hosal_adc_irq_t cb; /**< @brief adc callback */ - void *p_arg; /**< @brief p_arg data */ - void *priv; /**< @brief priv data */ -} hosal_adc_dev_t; - -/** - * @brief ADC interrupt callback - * - * @param[in] parg Set the custom parameters specified when the callback function is set - * - */ -typedef void (*hosal_adc_cb_t)(hosal_adc_event_t event, void *data, uint32_t size); - -/** - * @brief Initialises an ADC interface, Prepares an ADC hardware interface for sampling - * - * @param[in] adc the interface which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_init(hosal_adc_dev_t *adc); - -/** - * @brief Add a channel to an ADC interface - * - * @param[in] adc the interface which should be sampled - * @param[in] channel adc channel - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_add_channel(hosal_adc_dev_t *adc, uint32_t channel); - -/** - * @brief Remove a channel to an ADC interface - * - * @param[in] adc the interface which should be sampled - * @param[in] channel adc channel - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_remove_channel(hosal_adc_dev_t *adc, uint32_t channel); - -/** - * @brief Takes adc device handle from an ADC interface - * - * @return - * - other get adc device success - * - NULL if an error occurred with any step - */ -hosal_adc_dev_t *hosal_adc_device_get(void); - -/** - * @brief Takes a single sample from an ADC interface - * - * @param[in] adc the interface which should be sampled - * @param[in] channel adc channel - * @param[in] timeout ms timeout - * - * @return - * - other get adc data success - * - -1 if an error occurred with any step - */ -int hosal_adc_value_get(hosal_adc_dev_t *adc, uint32_t channel, uint32_t timeout); - -/** - * @brief Takes a tsen sample from an ADC interface - * - * @param[in] adc the interface which should be sampled - * - * @return - * - other get adc data success - * - -1 if an error occurred with any step - */ -int hosal_adc_tsen_value_get(hosal_adc_dev_t *adc); - -/** - * @brief ADC sampling cb register - * - * @param [in] adc the ADC interface - * @param [in] cb Non-zero pointer is the sample callback handler - * NULL pointer for send unregister operation - * adc in cb must be the same pointer with adc pointer passed to hosal_adc_sample_cb_reg - * driver must notify upper layer by calling cb if ADC data is ready in HW or memory(DMA) - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_sample_cb_reg(hosal_adc_dev_t *adc, hosal_adc_cb_t cb); - -/** - * @brief ADC sampling start - * - * @param[in] adc the ADC interface - * @param[in] data adc data buffer - * @param[in] size data buffer size aligned with resolution (until the next power of two) - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_start(hosal_adc_dev_t *adc, void *data, uint32_t size); - -/** - * @brief ADC sampling stop - * - * @param[in] adc the ADC interface - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_stop(hosal_adc_dev_t *adc); - -/** - * @brief De-initialises an ADC interface, Turns off an ADC hardware interface - * - * @param[in] adc the interface which should be de-initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_adc_finalize(hosal_adc_dev_t *adc); - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_ADC_H_ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dac.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dac.h deleted file mode 100644 index e5e9e6213e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dac.h +++ /dev/null @@ -1,187 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_DAC_H_ -#define __HOSAL_DAC_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include -#include "hosal_dma.h" - -/** @addtogroup hosal_dac DAC - * HOSAL DAC API - * - * @{ - */ - -/** - * @brief hosal dac callback - * - * @param[in] arg Set the custom parameters specified when the callback function is set - * - */ -typedef void (*hosal_dac_cb_t)(void *arg); - -/** - * @brief This struct define dac config args - */ -typedef struct { - uint8_t dma_enable; /**< @brief 1: use dma, 0: no dma */ - uint32_t pin; /**< @brief dac pin */ - uint32_t freq; /**< @brief dac freq */ -} hosal_dac_config_t; - -/** - * @brief This struct define dac device type - */ -typedef struct { - uint8_t port; /**< @brief dac id */ - hosal_dac_config_t config; /**< @brief dac config */ - hosal_dac_cb_t cb; /**< @brief dma callback */ - hosal_dma_chan_t dma_chan; /**< @brief dac dma channel */ - void *arg; /**< @brief arg data */ - void *priv; /**< @brief priv data */ -} hosal_dac_dev_t; - -/** - * @brief Initialises an dac interface - * - * @param[in] dac the interface which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_init(hosal_dac_dev_t *dac); - -/** - * @brief De-initialises an dac interface, Turns off an dac hardware interface - * - * @param[in] dac the interface which should be de-initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_finalize(hosal_dac_dev_t *dac); - -/** - * @brief Start output dac （no DMA mode） - * - * @param[in] dac the interface which should be started - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_start(hosal_dac_dev_t *dac); - -/** - * @brief Stop output dac - * - * @param[in] dac the interface which should be stopped - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_stop(hosal_dac_dev_t *dac); - -/** - * @brief Output a value to an dac interface - * - * @param[in] dac the interface to set value - * - * @param[in] data the value to output, output unit: μV - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_set_value(hosal_dac_dev_t *dac, uint32_t data); - -/** - * @brief Returns the last data output value of the selected dac channel - * - * @param[in] dac the interface to get value - * - * @return dac output value, output unit: μV - */ -int hosal_dac_get_value(hosal_dac_dev_t *dac); - -/** - * @brief DAC cb register - * - * @param [in] dac the DAC interface - * @param [in] callback callback handler - * @param [in] arg callback arg - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_dma_cb_reg(hosal_dac_dev_t *dac, hosal_dac_cb_t callback, void *arg); - -/** - * @brief DAC use DMA mode - * - * @param[in] adc the DAC interface - * @param[in] data dac data buffer - * @param[in] size data buffer size - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_dma_start(hosal_dac_dev_t *dac, uint32_t *data, uint32_t size); - -/** - * @brief Stop output dac - * - * @param[in] dac the interface which should be stopped - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_dac_dma_stop(hosal_dac_dev_t *dac); - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_DAC_H_ */ - -/* end of file */ - - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dma.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dma.h deleted file mode 100644 index 277154b3e1..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_dma.h +++ /dev/null @@ -1,152 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_DMA_H__ -#define __HOSAL_DMA_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_dma DMA - * HOSAL DMA API - * - * @{ - */ - -#include -#include - -/** - * @brief DMA irq callback function flag - */ -#define HOSAL_DMA_INT_TRANS_COMPLETE 0 -#define HOSAL_DMA_INT_TRANS_ERROR 1 - -/** - * @brief DMA irq callback function - */ -typedef void (*hosal_dma_irq_t)(void *p_arg, uint32_t flag); - -/** - * @brief DMA channel describe - */ -struct hosal_dma_chan { - uint8_t used; - hosal_dma_irq_t callback; - void *p_arg; -}; - -/** - * @brief DMA device type - */ -typedef struct hosal_dma_dev { - int max_chans; - struct hosal_dma_chan *used_chan; - void *priv; -} hosal_dma_dev_t; - -/** - * @brief DMA channel - */ -typedef int hosal_dma_chan_t; - -/** - * @brief Initialises a DMA interface - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_init(void); - -/** - * @brief Request a DMA channel - * - * @param[in] flag : DMA CHAN REQUEST FLAG - * - * @return < 0 : an error occurred with any step, otherwise is DMA channel number - */ -hosal_dma_chan_t hosal_dma_chan_request(int flag); - -/** - * @brief Release a DMA channel - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_release(hosal_dma_chan_t chan); - -/** - * @brief DMA channel trans start - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_start(hosal_dma_chan_t chan); - -/** - * @brief DMA channel trans stop - * - * @param[in] chan DMA channel number - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_chan_stop(hosal_dma_chan_t chan); - -/** - * @brief DMA irq callback set - * - * @param[in] chan : DMA channel number - * @param[in] pfn : callback function - * @param[in] arg : callback function parameter - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_irq_callback_set(hosal_dma_chan_t chan, hosal_dma_irq_t pfn, void *p_arg); - -/** - * @brief Deinitialises a DMA interface - * - * @param[in] DMA the interface which should be deinitialised - * - * @return 0 : on success, EIO : if an error occurred with any step - */ -int hosal_dma_finalize(void); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_DMA_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_efuse.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_efuse.h deleted file mode 100644 index 863e67c260..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_efuse.h +++ /dev/null @@ -1,70 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_EFUSE_H__ -#define __HOSAL_EFUSE_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * @brief Read data from efuse - * - * @param[in] addr efuse address - * @param[in] data store data - * @param[in] len data length - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_efuse_read(uint32_t addr, uint32_t *data, uint32_t len); - -/** - * @brief Write data to efuse - * - * @param[in] addr efuse address - * @param[in] data store data - * @param[in] len data length - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_efuse_write(uint32_t addr, uint32_t *data, uint32_t len); - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_EFUSE_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_flash.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_flash.h deleted file mode 100644 index 2de9049123..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_flash.h +++ /dev/null @@ -1,229 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_FLASH_H__ -#define __HOSAL_FLASH_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_flash FLASH - * HOSAL FLASH API - * - * @{ - */ - -#include - -#define HOSAL_FLASH_FLAG_ADDR_0 0 /**< @brief Open flash prtition address 0 in prtition table */ - -#define HOSAL_FLASH_FLAG_ADDR_1 (1 << 0) /**< @brief Open flash prtition address 1 in prtition table */ - -/** - * Open the partition table and use the bus physical address of flash. - * (If it is not set, the offset address set in the partition table is used by default.) - */ -#define HOSAL_FLASH_FLAG_BUSADDR (1 << 1) - -/** - * @brief Hal flash partition device - */ -typedef struct hosal_flash_dev { - void *flash_dev; /**< @brief flash device */ -} hosal_flash_dev_t; - -/** - * @brief Hal flash partition manage struct - */ -typedef struct { - const char *partition_description; /**< @brief name */ - uint32_t partition_start_addr; /**< @brief start addr */ - uint32_t partition_length; /**< @brief length */ - uint32_t partition_options; /**< @brief options */ -} hosal_logic_partition_t; - -/** - * @brief Open a flash partition device - * - * @param[in] name flash partition name - * @param[in] flags flash flags - * - HOSAL_FLASH_FLAG_ADDR_0 - * - HOSAL_FLASH_FLAG_ADDR_1 - * - HOSAL_FLASH_FLAG_BUSADDR - * - * @return - * - NULL flash open error - * - otherwise is flash partition device - */ -hosal_flash_dev_t *hosal_flash_open(const char *name, unsigned int flags); - -/** - * @brief Get the information of the specified flash area - * - * @param[in] p_dev The target flash logical partition device - * @param[out] partition The buffer to store partition info - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_info_get(hosal_flash_dev_t *p_dev, hosal_logic_partition_t *partition); - -/** - * @brief Erase an area on a Flash logical partition - * - * @note Erase on an address will erase all data on a sector that the - * address is belonged to, this function does not save data that - * beyond the address area but in the affected sector, the data - * will be lost. - * - * @param[in] p_dev The target flash logical partition which should be erased - * @param[in] off_set Start address of the erased flash area - * @param[in] size Size of the erased flash area - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_erase(hosal_flash_dev_t *p_dev, uint32_t off_set, uint32_t size); - -/** - * @brief Write data to an area on a flash logical partition without erase - * - * @param[in] p_dev The target flash logical partition which should be read which should be written - * @param[in/out] off_set Point to the start address that the data is written to, and - * point to the last unwritten address after this function is - * returned, so you can call this function serval times without - * update this start address. - * @param[in] in_buf point to the data buffer that will be written to flash - * @param[in] in_buf_size The size of the buffer - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_write(hosal_flash_dev_t *p_dev, uint32_t *off_set, - const void *in_buf, uint32_t in_buf_size); - -/** - * @brief Write data to an area on a flash logical partition with erase first - * - * @param[in] p_dev The target flash logical partition which should be read which should be written - * @param[in/out] off_set Point to the start address that the data is written to, and - * point to the last unwritten address after this function is - * returned, so you can call this function serval times without - * update this start address. - * @param[in] in_buf point to the data buffer that will be written to flash - * @param[in] in_buf_size The length of the buffer - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_erase_write(hosal_flash_dev_t *p_dev, uint32_t *off_set, - const void *in_buf, uint32_t in_buf_size); - -/** - * @brief Read data from an area on a Flash to data buffer in RAM - * - * @param[in] p_dev The target flash logical partition which should be read - * @param[in/out] off_set Point to the start address that the data is read, and - * point to the last unread address after this function is - * returned, so you can call this function serval times without - * update this start address. - * @param[in] out_buf Point to the data buffer that stores the data read from flash - * @param[in] out_buf_size The length of the buffer - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_read(hosal_flash_dev_t *p_dev, uint32_t *off_set, - void *out_buf, uint32_t out_buf_size); - -/** - * @brief Close a flash partition device - * - * @param[in] p_dev flash partition device - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_close(hosal_flash_dev_t *p_dev); - -/** - * @brief Read data from a row address on a Flash to data buffer in RAM - * - * @param[in] buffer Point to the data buffer that stores the data read from flash - * @param[in] address Address on flash to read from - * @param[in] length Length (in bytes) of data to read - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_raw_read(void *buffer, uint32_t address, uint32_t length); - -/** - * @brief Write data to a row address on a Flash - * - * @param[in] buffer Point to the data buffer that will be written to flash - * @param[in] address Address on flash to write to - * @param[in] length Length (in bytes) of data to write - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_raw_write(void *buffer, uint32_t address, uint32_t length); - -/** - * @brief Erase a region of the flash - * - * @param[in] start_addr Address to start erasing flash. - * @param[in] length Length of region to erase. - * - * @return - * - 0 On success - * - otherwise is error - */ -int hosal_flash_raw_erase(uint32_t start_addr, uint32_t length); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_FLASH_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_gpio.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_gpio.h deleted file mode 100644 index c2f8f42a52..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_gpio.h +++ /dev/null @@ -1,186 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_GPIO_H_ -#define __HOSAL_GPIO_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -#include - -/** @addtogroup hosal_gpio GPIO - * HOSAL GPIO API - * - * @{ - */ - -/** - * @brief gpio config struct - */ -typedef enum { - ANALOG_MODE, /**< @brief Used as a function pin, input and output analog */ - INPUT_PULL_UP, /**< @brief Input with an internal pull-up resistor - use with devices that actively drive the signal low - e.g. button connected to ground */ - INPUT_PULL_DOWN, /**< @brief Input with an internal pull-down resistor - use with devices that actively drive the signal high - e.g. button connected to a power rail */ - INPUT_HIGH_IMPEDANCE, /**< @brief Input - must always be driven, either actively or by an external pullup resistor */ - OUTPUT_PUSH_PULL, /**< @brief Output actively driven high and actively driven low - must not be connected to other active outputs - e.g. LED output */ - OUTPUT_OPEN_DRAIN_NO_PULL, /**< @brief Output actively driven low but is high-impedance when set high - can be connected to other open-drain/open-collector outputs. Needs an external pull-up resistor */ - OUTPUT_OPEN_DRAIN_PULL_UP, /**< @brief Output actively driven low and is pulled high with an internal resistor when set high - can be connected to other open-drain/open-collector outputs. */ - OUTPUT_OPEN_DRAIN_AF, /**< @brief Alternate Function Open Drain Mode. */ - OUTPUT_PUSH_PULL_AF, /**< @brief Alternate Function Push Pull Mode. */ -} hosal_gpio_config_t; - -/** - * @brief GPIO interrupt trigger - */ -typedef enum { - HOSAL_IRQ_TRIG_NEG_PULSE, /**< @brief GPIO negedge pulse trigger interrupt */ - HOSAL_IRQ_TRIG_POS_PULSE, /**< @brief GPIO posedge pulse trigger interrupt */ - HOSAL_IRQ_TRIG_NEG_LEVEL, /**< @brief GPIO negedge level trigger interrupt (32k 3T)*/ - HOSAL_IRQ_TRIG_POS_LEVEL, /**< @brief GPIO posedge level trigger interrupt (32k 3T)*/ -} hosal_gpio_irq_trigger_t; - -/** - * @brief GPIO interrupt callback handler - * - *@param[in] parg ：Set the custom parameters specified - */ -typedef void (*hosal_gpio_irq_handler_t)(void *arg); - -/** - * @brief hosal gpio ctx, use for multi gpio irq - */ -typedef struct hosal_gpio_ctx { - struct hosal_gpio_ctx *next; - hosal_gpio_irq_handler_t handle; - void *arg; - uint8_t pin; - uint8_t intCtrlMod; - uint8_t intTrigMod; -}hosal_gpio_ctx_t; - -/** - * @brief GPIO dev struct - */ -typedef struct { - uint8_t port; /**< @brief gpio port */ - hosal_gpio_config_t config; /**< @brief gpio config */ - void *priv; /**< @brief priv data */ -} hosal_gpio_dev_t; - -/** - * @brief Initialises a GPIO pin - * - * @note Prepares a GPIO pin for use. - * - * @param[in] gpio the gpio pin which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_init(hosal_gpio_dev_t *gpio); - -/** - * @brief Set GPIO output high or low - * - * @note Using this function on a gpio pin which is set to input mode is undefined. - * - * @param[in] gpio the gpio pin which should be set - * @param[in] value 0 : output low | >0 : output high - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_output_set(hosal_gpio_dev_t *gpio, uint8_t value); - -/** - * @brief Get the state of an input GPIO pin. Using this function on a - * gpio pin which is set to output mode will return an undefined value. - * - * @param[in] gpio the gpio pin which should be read - * @param[out] value gpio value - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_input_get(hosal_gpio_dev_t *gpio, uint8_t *value); - -/** - * @brief Enables an interrupt trigger for an input GPIO pin. - * Using this function on a gpio pin which is set to - * output mode is undefined. - * - * @param[in] gpio the gpio pin which will provide the interrupt trigger - * @param[in] trigger the type of trigger (rising/falling edge or both) - * @param[in] handler a function pointer to the interrupt handler - * @param[in] arg an argument that will be passed to the interrupt handler - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_irq_set(hosal_gpio_dev_t *gpio, hosal_gpio_irq_trigger_t trigger_type, hosal_gpio_irq_handler_t handler, void *arg); - -/** - * @brief Clear an interrupt status for an input GPIO pin. - * Using this function on a gpio pin which has generated a interrupt. - * - * @param[in] gpio the gpio pin which provided the interrupt trigger - * @param[in] mask 0 : mask | 1 : umask - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_irq_mask(hosal_gpio_dev_t *gpio, uint8_t mask); - -/** - * @brief Set a GPIO pin in default state. - * - * @param[in] gpio the gpio pin which should be deinitialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_gpio_finalize(hosal_gpio_dev_t *gpio); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_GPIO_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_i2c.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_i2c.h deleted file mode 100644 index c3b1de8bec..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_i2c.h +++ /dev/null @@ -1,212 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_I2C_H_ -#define __HOSAL_I2C_H_ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_i2c I2C - * HOSAL I2C API - * - * @{ - */ - -#include - -#define HOSAL_WAIT_FOREVER 0xFFFFFFFFU /**< @brief i2c wait time */ - -#define HOSAL_I2C_MODE_MASTER 1 /**< @brief i2c communication is master mode */ -#define HOSAL_I2C_MODE_SLAVE 2 /**< @brief i2c communication is slave mode */ - -#define HOSAL_I2C_MEM_ADDR_SIZE_8BIT 1 /**< @brief i2c memory address size 8bit */ -#define HOSAL_I2C_MEM_ADDR_SIZE_16BIT 2 /**< @brief i2c memory address size 16bit */ -#define HOSAL_I2C_MEM_ADDR_SIZE_24BIT 3 /**< @brief i2c memory address size 24bit */ -#define HOSAL_I2C_MEM_ADDR_SIZE_32BIT 4 /**< @brief i2c memory address size 32bit */ - -#define HOSAL_I2C_ADDRESS_WIDTH_7BIT 0 /**< @brief 7 bit mode */ -#define HOSAL_I2C_ADDRESS_WIDTH_10BIT 1 /**< @brief 10 bit mode */ - -/** - * @brief I2C configuration - */ -typedef struct { - uint32_t address_width; /**< @brief Addressing mode: 7 bit or 10 bit */ - uint32_t freq; /**< @brief CLK freq */ - uint8_t scl; /**< @brief i2c clk pin */ - uint8_t sda; /**< @brief i2c data pin */ - uint8_t mode; /**< @brief master or slave mode */ -} hosal_i2c_config_t; - -/** - * @brief I2C device type - */ -typedef struct { - uint8_t port; /**< @brief i2c port */ - hosal_i2c_config_t config; /**< @brief i2c config */ - void *priv; /**< @brief priv data */ -} hosal_i2c_dev_t; - -/** - * @brief Initialises an I2C interface - * - * @param[in] i2c the device for which the i2c port should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_init(hosal_i2c_dev_t *i2c); - -/** - * @brief I2c master send - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[in] data i2c send data - * @param[in] size i2c send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_master_send(hosal_i2c_dev_t *i2c, uint16_t dev_addr, const uint8_t *data, - uint16_t size, uint32_t timeout); - -/** - * @brief I2c master recv - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[out] data i2c receive data - * @param[in] size i2c receive data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_master_recv(hosal_i2c_dev_t *i2c, uint16_t dev_addr, uint8_t *data, - uint16_t size, uint32_t timeout); -/** - * @brief I2c slave send - * - * @param[in] i2c the i2c device - * @param[in] data i2c slave send data - * @param[in] size i2c slave send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_slave_send(hosal_i2c_dev_t *i2c, const uint8_t *data, uint16_t size, uint32_t timeout); - -/** - * @brief I2c slave receive - * - * @param[in] i2c tthe i2c device - * @param[out] data i2c slave receive data - * @param[in] size i2c slave receive data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_slave_recv(hosal_i2c_dev_t *i2c, uint8_t *data, uint16_t size, uint32_t timeout); - -/** - * @brief I2c mem write - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[in] mem_addr mem address - * @param[in] mem_addr_size mem address - * @param[in] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_mem_write(hosal_i2c_dev_t *i2c, uint16_t dev_addr, uint32_t mem_addr, - uint16_t mem_addr_size, const uint8_t *data, uint16_t size, - uint32_t timeout); - -/** - * @brief I2c master mem read - * - * @param[in] i2c the i2c device - * @param[in] dev_addr device address - * @param[in] mem_addr mem address - * @param[in] mem_addr_size mem address - * @param[out] data i2c master send data - * @param[in] size i2c master send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_mem_read(hosal_i2c_dev_t *i2c, uint16_t dev_addr, uint32_t mem_addr, - uint16_t mem_addr_size, uint8_t *data, uint16_t size, - uint32_t timeout); - -/** - * @brief Deinitialises an I2C device - * - * @param[in] i2c the i2c device - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_i2c_finalize(hosal_i2c_dev_t *i2c); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_I2C_H_ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_pwm.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_pwm.h deleted file mode 100644 index f40a699561..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_pwm.h +++ /dev/null @@ -1,175 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HOSAL_PWM_H__ -#define __HOSAL_PWM_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_pwm PWM - * HOSAL PWM API - * - * @{ - */ - -#include -/** - * @brief pwm config struct - * - */ -typedef struct { - uint8_t pin; /**< pwm pin */ - uint32_t duty_cycle; /**< the pwm duty_cycle 0 ~ 10000(0 ~ 100%)*/ - uint32_t freq; /**< the pwm freq,range is between 0 and 40M */ -} hosal_pwm_config_t; - -/** - * @brief pwm dev struct - * - */ -typedef struct { - uint8_t port; /**< pwm port */ - hosal_pwm_config_t config; /**< pwm config */ - void *priv; /**< priv data */ -} hosal_pwm_dev_t; - -/** - * @brief Initialises a PWM pin - * - * @param[in] pwm the PWM device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_init(hosal_pwm_dev_t *pwm); - -/** - * @brief Starts Pulse-Width Modulation signal output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_pwm_start(hosal_pwm_dev_t *pwm); - -/** - * @brief Stops output on a PWM pin - * - * @param[in] pwm the PWM device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_stop(hosal_pwm_dev_t *pwm); - -/** - * @change the para of pwm - * - * @param[in] pwm the PWM device - * @param[in] para the para of pwm - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_para_chg(hosal_pwm_dev_t *pwm, hosal_pwm_config_t para); - -/** - * @brief update PWM frequency - * - * @param[in] pwm the PWM device - * @param[in] freq the PWM frequency (0~40M under limited duty) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_freq_set(hosal_pwm_dev_t *pwm, uint32_t freq); - -/** - * @brief get PWM frequency - * - * @param[in] pwm the PWM device - * @param[out] p_freq the pointer to memory frequency - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_freq_get(hosal_pwm_dev_t *pwm, uint32_t *p_freq); - -/** - * @brief set PWM duty - * - * @param[in] pwm the PWM device - * @param[in] duty the PWM duty (original duty * 100) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_duty_set(hosal_pwm_dev_t *pwm, uint32_t duty); - -/** - * @brief get PWM duty - * - * @param[in] pwm the PWM device - * @param[out] p_duty the pointer to memory duty(original duty * 100) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_duty_get(hosal_pwm_dev_t *pwm, uint32_t *p_duty); - -/** - * @brief De-initialises an PWM interface, Turns off an PWM hardware interface - * - * @param[in] pwm the interface which should be de-initialised - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_pwm_finalize(hosal_pwm_dev_t *pwm); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_PWM_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rng.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rng.h deleted file mode 100644 index 733d1d397c..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rng.h +++ /dev/null @@ -1,74 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HAL_RNG_H -#define HAL_RNG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_rng RNG - * HOSAL RNG API - * - * @{ - */ - -#include - -/** - * @brief init rng - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_rng_init(void); - -/** - * @brief Fill in a memory buffer with random data - * - * @param[out] buf Point to a valid memory buffer, this function will fill - * in this memory with random numbers after executed - * @param[in] bytes Length of the memory buffer (bytes) - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_random_num_read(void *buf, uint32_t bytes); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_RNG_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rtc.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rtc.h deleted file mode 100644 index dc0a3082e7..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_rtc.h +++ /dev/null @@ -1,146 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __HAL_RTC_H__ -#define __HAL_RTC_H__ - -/** @addtogroup hal_rtc RTC - * rtc hal API. - * - * @{ - */ - -#include - -#define HOSAL_RTC_FORMAT_DEC 1 /**< RTC DEC format */ -#define HOSAL_RTC_FORMAT_BCD 2 /**< RTC BCD format */ - -/** - * @brief rtc config struct - */ -typedef struct { - uint8_t format; /**< time formart DEC or BCD */ -} hosal_rtc_config_t; - -/** - * @brief rtc dev struct - */ -typedef struct { - uint8_t port; /**< rtc port */ - hosal_rtc_config_t config; /**< rtc config */ - void *priv; /**< priv data */ -} hosal_rtc_dev_t; - -/** - * @brief RTC time struct - */ -typedef struct { - uint8_t sec; /**< DEC format:value range from 0 to 59, BCD format:value range from 0x00 to 0x59 */ - uint8_t min; /**< DEC format:value range from 0 to 59, BCD format:value range from 0x00 to 0x59 */ - uint8_t hr; /**< DEC format:value range from 0 to 23, BCD format:value range from 0x00 to 0x23 */ - uint8_t date; /**< DEC format:value range from 1 to 31, BCD format:value range from 0x01 to 0x31 */ - uint8_t month; /**< DEC format:value range from 1 to 12, BCD format:value range from 0x01 to 0x12 */ - uint16_t year; /**< DEC format:value range from 0 to 9999, BCD format:value range from 0x0000 to 0x9999 */ -} hosal_rtc_time_t; - -/** - * @brief This function will initialize the on board CPU real time clock - * - * - * @param[in] rtc rtc device - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_init(hosal_rtc_dev_t *rtc); - -/** - * @brief This function will set MCU RTC time to a new value. - * - * @param[in] rtc rtc device - * @param[in] time pointer to a time structure - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_set_time(hosal_rtc_dev_t *rtc, const hosal_rtc_time_t *time); - -/** - * @brief This function will return the value of time read from the on board CPU real time clock. - * - * @param[in] rtc rtc device - * @param[out] time pointer to a time structure - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_get_time(hosal_rtc_dev_t *rtc, hosal_rtc_time_t *time); - -/** - * @brief This function will set MCU RTC time to a new value. - * - * @param[in] rtc rtc device - * @param[in] time_stamp new time value - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_set_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp); - -/** - * @brief This function will return the value of time read from the on board CPU real time clock. - * - * @param[in] rtc rtc device - * @param[in] time_stamp new time value - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_get_count(hosal_rtc_dev_t *rtc, uint64_t *time_stamp); - -/** - * @brief De-initialises an RTC interface, Turns off an RTC hardware interface - * - * @param[in] RTC the interface which should be de-initialised - * - * @return - * - 0 : success - * - other : fail - */ -int hosal_rtc_finalize(hosal_rtc_dev_t *rtc); - -/** @} */ - -#endif /* HAL_RTC_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_spi.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_spi.h deleted file mode 100644 index ec259046f0..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_spi.h +++ /dev/null @@ -1,178 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HAL_SPI_H -#define HAL_SPI_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_spi SPI - * HOSAL SPI API - * - * @{ - */ - -#include -#include -#include - -#define HOSAL_SPI_MODE_MASTER 0 /**< spi communication is master mode */ -#define HOSAL_SPI_MODE_SLAVE 1 /**< spi communication is slave mode */ -#define HOSAL_WAIT_FOREVER 0xFFFFFFFFU /**< DMA transmission timeout */ - -typedef void (*hosal_spi_irq_t)(void *parg); /**< spi irq callback function */ - -/** - * @brief Define spi config args - */ -typedef struct { - uint8_t mode; /**< spi communication mode */ - uint8_t dma_enable; /**< enable dma tansmission or not */ - uint8_t polar_phase; /**< spi polar and phase */ - uint32_t freq; /**< communication frequency Hz */ - uint8_t pin_clk; /**< spi clk pin */ - uint8_t pin_mosi; /**< spi mosi pin */ - uint8_t pin_miso; /**< spi miso pin */ -} hosal_spi_config_t; - -/** - * @brief Define spi dev handle - */ -typedef struct { - uint8_t port; /**< spi port */ - hosal_spi_config_t config; /**< spi config */ - hosal_spi_irq_t cb; /**< spi interrupt callback */ - void *p_arg; /**< arg pass to callback */ - void *priv; /**< priv data */ -} hosal_spi_dev_t; - -/** - * @brief Initialises the SPI interface for a given SPI device - * - * @param[in] spi the spi device - * - * @return - * - 0 : on success - * - other : error - */ -int hosal_spi_init(hosal_spi_dev_t *spi); - -/** - * @brief Spi send - * - * @param[in] spi the spi device - * @param[in] data spi send data - * @param[in] size spi send data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 : on success - * - other : error - */ -int hosal_spi_send(hosal_spi_dev_t *spi, const uint8_t *data, uint32_t size, uint32_t timeout); - -/** - * @brief Spi recv - * - * @param[in] spi the spi device - * @param[out] data spi recv data - * @param[in] size spi recv data size - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_recv(hosal_spi_dev_t *spi, uint8_t *data, uint16_t size, uint32_t timeout); - -/** - * @brief spi send data and recv - * - * @param[in] spi the spi device - * @param[in] tx_data spi send data - * @param[out] rx_data spi recv data - * @param[in] size spi data to be sent and recived - * @param[in] timeout timeout in milisecond, set this value to HAL_WAIT_FOREVER - * if you want to wait forever - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_send_recv(hosal_spi_dev_t *spi, uint8_t *tx_data, uint8_t *rx_data, uint16_t size, uint32_t timeout); - -/* - * @brief set spi irq callback - * - * @param spi the spi device - * @param pfn callback function - * @param p_arg callback function parameter - * - * @return - * - 0 : success - * - othe : error - */ -int hosal_spi_irq_callback_set(hosal_spi_dev_t *spi, hosal_spi_irq_t pfn, void *p_arg); - -/** - * @brief spi software set cs pin high/low only for master device - * - * @param[in] pin cs pin - * @param[in] value 0 or 1 - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_set_cs(uint8_t pin, uint8_t value); - -/** - * @brief De-initialises a SPI interface - * - * - * @param[in] spi the SPI device to be de-initialised - * - * @return - * - 0 : success - * - other : error - */ -int hosal_spi_finalize(hosal_spi_dev_t *spi); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_SPI_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_timer.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_timer.h deleted file mode 100644 index 20a1a9b66e..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_timer.h +++ /dev/null @@ -1,118 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HOSAL_TIMER_H -#define HOSAL_TIMER_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hal_timer TIMER - * timer hal API. - * - * @{ - */ - -#include - -#define TIMER_RELOAD_PERIODIC 1 /**< timer reload automatic */ -#define TIMER_RELOAD_ONCE 2 /**< timer reload once and need to reload manually */ - -typedef void (*hosal_timer_cb_t)(void *arg); /**< Define timer handle function type */ - -/** - * Define timer config args - */ -typedef struct { - uint32_t period; /**< timer period, us */ - uint8_t reload_mode; /**< auto reload or not */ - hosal_timer_cb_t cb; /**< timer handle when expired */ - void *arg; /**< timer handle args */ -} hosal_timer_config_t; - -/** - * Define timer dev handle - */ -typedef struct { - int8_t port; /**< timer port */ - hosal_timer_config_t config; /**< timer config */ - void *priv; /**< priv data */ -} hosal_timer_dev_t; - -/** - * init a hardware timer - * - * @param[in] tim timer device - * - * @return - * - 0 : success - * - other :error - */ -int hosal_timer_init(hosal_timer_dev_t *tim); - -/** - * start a hardware timer - * - * @param[in] tim timer device - * - * @return - * - 0 : success - * - other : error - */ -int hosal_timer_start(hosal_timer_dev_t *tim); - -/** - * stop a hardware timer - * - * @param[in] tim timer device - * - * @return none - */ -void hosal_timer_stop(hosal_timer_dev_t *tim); - -/** - * De-initialises an TIMER interface, Turns off an TIMER hardware interface - * - * @param[in] tim timer device - * - * @return - * - 0 : success - * - other : error - */ -int hosal_timer_finalize(hosal_timer_dev_t *tim); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_TIMER_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_uart.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_uart.h deleted file mode 100644 index 0698406b89..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_uart.h +++ /dev/null @@ -1,356 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ - -#ifndef __HOSAL_UART_H__ -#define __HOSAL_UART_H__ - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_uart UART - * HOSAL UART API - * - * @{ - */ - -#include -#include -#include "hosal_dma.h" - -#define HOSAL_UART_AUTOBAUD_0X55 1 /**< @brief UART auto baudrate detection using codeword 0x55 */ -#define HOSAL_UART_AUTOBAUD_STARTBIT 2 /**< @brief UART auto baudrate detection using start bit */ - -#define HOSAL_UART_TX_CALLBACK 1 /**< @brief UART tx idle interrupt callback */ -#define HOSAL_UART_RX_CALLBACK 2 /**< @brief UART rx complete callback */ -#define HOSAL_UART_TX_DMA_CALLBACK 3 /**< @brief UART tx DMA trans complete callback */ -#define HOSAL_UART_RX_DMA_CALLBACK 4 /**< @brief UART rx DMA trans complete callback */ - -#define HOSAL_UART_BAUD_SET 1 /**< @brief UART baud set */ -#define HOSAL_UART_BAUD_GET 2 /**< @brief UART baud get */ -#define HOSAL_UART_DATA_WIDTH_SET 3 /**< @brief UART data width set */ -#define HOSAL_UART_DATA_WIDTH_GET 4 /**< @brief UART data width get */ -#define HOSAL_UART_STOP_BITS_SET 5 /**< @brief UART stop bits set */ -#define HOSAL_UART_STOP_BITS_GET 6 /**< @brief UART stop bits get */ -#define HOSAL_UART_FLOWMODE_SET 7 /**< @brief UART flow mode set */ -#define HOSAL_UART_FLOWSTAT_GET 8 /**< @brief UART flow state get */ -#define HOSAL_UART_PARITY_SET 9 /**< @brief UART flow mode set */ -#define HOSAL_UART_PARITY_GET 10 /**< @brief UART flow state get */ -#define HOSAL_UART_MODE_SET 11 /**< @brief UART mode set */ -#define HOSAL_UART_MODE_GET 12 /**< @brief UART mode get */ -#define HOSAL_UART_FREE_TXFIFO_GET 13 /**< @brief UART free tx fifo get */ -#define HOSAL_UART_FREE_RXFIFO_GET 14 /**< @brief UART free rx fifo get */ -#define HOSAL_UART_FLUSH 15 /**< @brief Wait for the send to complete */ -#define HOSAL_UART_TX_TRIGGER_ON 16 /**< @brief UART TX trigger on */ -#define HOSAL_UART_TX_TRIGGER_OFF 17 /**< @brief UART TX trigger off */ -#define HOSAL_UART_DMA_TX_START 18 /**< @brief UART DMA TX start trans */ -#define HOSAL_UART_DMA_RX_START 19 /**< @brief UART DMA RX start trans */ - -/** - * @brief hosal uart callback - * - * @param[in] p_arg Set the custom parameters specified when the callback function is set - * - * @return - * - 0 : on success - * - EIO : if an error occurred with any step - */ -typedef int (*hosal_uart_callback_t)(void *p_arg); - -/** - * @brief UART data width - */ -typedef enum { - HOSAL_DATA_WIDTH_5BIT, - HOSAL_DATA_WIDTH_6BIT, - HOSAL_DATA_WIDTH_7BIT, - HOSAL_DATA_WIDTH_8BIT, - HOSAL_DATA_WIDTH_9BIT -} hosal_uart_data_width_t; - -/** - * @brief UART stop bits - */ -typedef enum { - HOSAL_STOP_BITS_1 = 1, - HOSAL_STOP_BITS_2 = 3 -} hosal_uart_stop_bits_t; - -/** - * @brief UART flow control - */ -typedef enum { - HOSAL_FLOW_CONTROL_DISABLED, - HOSAL_FLOW_CONTROL_RTS, - HOSAL_FLOW_CONTROL_CTS, - HOSAL_FLOW_CONTROL_CTS_RTS -} hosal_uart_flow_control_t; - -/** - * @brief UART parity - */ -typedef enum { - HOSAL_NO_PARITY, - HOSAL_ODD_PARITY, - HOSAL_EVEN_PARITY -} hosal_uart_parity_t; - -/** - * @brief UART mode - */ -typedef enum { - HOSAL_UART_MODE_POLL, /**< @brief UART poll mode (default mode) */ - HOSAL_UART_MODE_INT_TX, /**< @brief UART TX int mode */ - HOSAL_UART_MODE_INT_RX, /**< @brief UART RX int mode */ - HOSAL_UART_MODE_INT, /**< @brief UART TX and RX int mode */ -} hosal_uart_mode_t; - -/** - * @brief UART DMA configuration - */ -typedef struct { - /** - * @brief UART DMA trans buffer - * When the transmission is TX, the address is the src address - * When the transmission is RX, the address is the dest address - */ - uint8_t *dma_buf; - - uint32_t dma_buf_size; /**< @brief UART DMA trans buffer size */ -} hosal_uart_dma_cfg_t; - -/** - * @brief UART configuration - */ -typedef struct { - uint8_t uart_id; /**< @brief UART id */ - uint8_t tx_pin; /**< @brief UART tx pin */ - uint8_t rx_pin; /**< @brief UART rx pin */ - uint8_t cts_pin; /**< @brief UART cts pin */ - uint8_t rts_pin; /**< @brief UART rts pin */ - uint32_t baud_rate; /**< @brief UART baud rate */ - hosal_uart_data_width_t data_width; /**< @brief UART data width */ - hosal_uart_parity_t parity; /**< @brief UART parity bit */ - hosal_uart_stop_bits_t stop_bits; /**< @brief UART stop btis */ - hosal_uart_flow_control_t flow_control; /**< @brief UART flow control */ - hosal_uart_mode_t mode; /**< @brief UART int or pull mode */ -} hosal_uart_config_t; - -/** - * @brief UART device type - */ -typedef struct { - uint8_t port; /**< @brief UART port */ - hosal_uart_config_t config; /**< @brief UART config */ - hosal_uart_callback_t tx_cb; /**< @brief UART tx callback */ - void *p_txarg; /**< @brief UART tx callback arg */ - hosal_uart_callback_t rx_cb; /**< @brief UART rx callback */ - void *p_rxarg; /**< @brief UART rx callback arg */ - hosal_uart_callback_t txdma_cb; /**< @brief UART tx dma callback */ - void *p_txdma_arg; /**< @brief UART tx dma callback arg */ - hosal_uart_callback_t rxdma_cb; /**< @brief UART rx dma callback */ - void *p_rxdma_arg; /**< @brief UART rx dma callback arg */ - hosal_dma_chan_t dma_tx_chan; /**< @brief UART dma tx channel */ - hosal_dma_chan_t dma_rx_chan; /**< @brief UART dma rx channel */ - void *priv; /**< @brief UART private data */ -} hosal_uart_dev_t; - -/** - * @brief define a UART default config - * - * @param[in] cfg config define - * @param[in] id uart id - * @param[in] tx uart tx pin - * @param[in] rx uart rx pin - * @param[in] baud uart baud - * - */ -#define HOSAL_UART_CFG_DECL(cfg, id, tx, rx, baud) \ - hosal_uart_config_t cfg = { \ - .uart_id = id, \ - .tx_pin = tx, \ - .rx_pin = rx, \ - .cts_pin = 255, \ - .rts_pin = 255, \ - .baud_rate = baud, \ - .data_width = HOSAL_DATA_WIDTH_8BIT, \ - .parity = HOSAL_NO_PARITY, \ - .stop_bits = HOSAL_STOP_BITS_1, \ - .mode = HOSAL_UART_MODE_POLL, \ - }; - -/** - * @brief define a UART device - * - * @param[in] dev uart device - * @param[in] id uart id - * @param[in] tx uart tx pin - * @param[in] rx uart rx pin - * @param[in] baud uart baud - */ -#define HOSAL_UART_DEV_DECL(dev, id, tx, rx, baud) \ - hosal_uart_dev_t dev = { \ - .config = { \ - .uart_id = id, \ - .tx_pin = tx, \ - .rx_pin = rx, \ - .cts_pin = 255, \ - .rts_pin = 255, \ - .baud_rate = baud, \ - .data_width = HOSAL_DATA_WIDTH_8BIT, \ - .parity = HOSAL_NO_PARITY, \ - .stop_bits = HOSAL_STOP_BITS_1, \ - .mode = HOSAL_UART_MODE_POLL, \ - }, \ - }; -/** - * @brief Get auto baudrate on a UART interface - * - * @param[in] uart the UART interface - * @param[in] mode auto baudrate detection mode(codeword 0x55 or start bit) - * - * @return - * - = 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_abr_get(hosal_uart_dev_t *uart, uint8_t mode); - -/** - * @brief Initialises a UART interface - * - * @param[in] uart the interface which should be initialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_init(hosal_uart_dev_t *uart); - -/** - * @brief Poll transmit data on a UART interface - * - * @param[in] uart the UART interface - * @param[in] txbuf pointer to the start of data - * @param[in] size number of bytes to transmit - * - * @return - * - > 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_send(hosal_uart_dev_t *uart, const void *txbuf, uint32_t size); - -/** - * @brief Poll receive data on a UART interface - * - * @param[in] uart the UART interface - * @param[out] rxbuf pointer to the buffer which will store incoming data - * @param[in] expect_size expect number of bytes to receive - * - * @return - * - > 0 number of bytes to receive - * - EIO if an error occurred with any step - */ -int hosal_uart_receive(hosal_uart_dev_t *uart, void *data, uint32_t expect_size); - -/** - * @brief hal uart ioctl - * - * @param[in] uart the UART interface - * @param[in] ctl Control request - * - HOSAL_UART_BAUD_SET : baud set, p_arg is baud - * - HOSAL_UART_BAUD_GET : baud get, p_arg is baud's pointer - * - HOSAL_UART_DATA_WIDTH_SET : set data width，p_arg is hosal_uart_data_width_t - * - HOSAL_UART_DATA_WIDTH_GET : get data width，p_arg is hosal_uart_data_width_t's pointer - * - HOSAL_UART_STOP_BITS_SET : set stop bits, p_arg is hosal_uart_stop_bits_t - * - HOSAL_UART_STOP_BITS_GET : get stop bits, p_arg is hosal_uart_stop_bits_t's pointer - * - HOSAL_UART_PARITY_SET : set parity, p_arg is hosal_uart_parity_t - * - HOSAL_UART_PARITY_GET : get parity, p_arg is hosal_uart_parity_t's pointer - * - HOSAL_UART_MODE_SET : UART mode set, p_arg is hosal_uart_mode_t - * - HOSAL_UART_MODE_GET : UART mode get, p_arg is hosal_uart_mode_t's pointer - * - HOSAL_UART_FLOWMODE_SET : UART flow mode set, p_arg is hosal_uart_flow_control_t - * - HOSAL_UART_FLOWSTAT_GET : UART flow state get, p_arg is hosal_uart_flow_control_t's pointer - * - HOSAL_UART_FREE_TXFIFO_GET : get uart free tx fifo size (bytes) - * - HOSAL_UART_FREE_RXFIFO_GET : get uart free rx fifo size (bytes) - * - HOSAL_UART_FLUSH : Wait for the send to complete - * - HOSAL_UART_TX_TRIGGER_ON : UART TX trigger on - * - HOSAL_UART_TX_TRIGGER_OFF : UART TX trigger off - * - HOSAL_UART_DMA_CONFIG : p_arg is hosal_uart_dma_cfg_t's pointer - * - HOSAL_UART_DMA_TX_START : UART DMA TX start trans p_arg is hosal_uart_dma_cfg_t's pointer - * - HOSAL_UART_DMA_RX_START : UART DMA RX start trans p_arg is hosal_uart_dma_cfg_t's pointer - * - * @param[in,out] p_arg parameter - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_ioctl (hosal_uart_dev_t *uart, int ctl, void *p_arg); - -/** - * @brief hal uart callback set - * - * @param[in] uart the UART interface - * @param[in] callback_type callback type - * - HOSAL_UART_TX_CALLBACK - * - HOSAL_UART_RX_CALLBACK - * - HOSAL_UART_TX_DMA_CALLBACK - * - HOSAL_UART_RX_DMA_CALLBACK - * @param[in] pfn_callback callback function - * @param[in] arg callback function parameter - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_callback_set (hosal_uart_dev_t *uart, - int callback_type, - hosal_uart_callback_t pfn_callback, - void *arg); - -/** - * @brief Deinitialises a UART interface - * - * @param[in] uart the interface which should be deinitialised - * - * @return - * - 0 on success - * - EIO if an error occurred with any step - */ -int hosal_uart_finalize(hosal_uart_dev_t *uart); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* __HOSAL_UART_H__ */ - -/* end of file */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_wdg.h b/bsp/bl808/m0/libraries/platform/hosal/include/hosal_wdg.h deleted file mode 100644 index 853c321420..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/include/hosal_wdg.h +++ /dev/null @@ -1,99 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef HAL_WDG_H -#define HAL_WDG_H - -#ifdef __cplusplus -extern "C" { -#endif - -/** @addtogroup hosal_wdg WATCHDOG - * HOSAL WATCHDOG API - * - * @{ - */ - -#include - -/** - * @brief wdg config struct - * - */ -typedef struct { - uint32_t timeout; /*!< Watchdag timeout in ms*/ -} hosal_wdg_config_t; - -/** - * @brief wdg dev struct - * - */ -typedef struct { - uint8_t port; /**< wdg port */ - hosal_wdg_config_t config; /**< wdg config */ - void *priv; /**< priv data */ -} hosal_wdg_dev_t; - -/** - * @brief This function will initialize the on board CPU hardware watch dog - * - * @param[in] wdg the watch dog device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_wdg_init(hosal_wdg_dev_t *wdg); - -/** - * @brief Reload watchdog counter. - * - * @param[in] wdg the watch dog device - */ -void hosal_wdg_reload(hosal_wdg_dev_t *wdg); - -/** - * @brief This function performs any platform-specific cleanup needed for hardware watch dog. - * - * @param[in] wdg the watch dog device - * - * @return - * - 0 : success - * - other: fail - */ -int hosal_wdg_finalize(hosal_wdg_dev_t *wdg); - -/** @} */ - -#ifdef __cplusplus -} -#endif - -#endif /* HAL_WDG_H */ - diff --git a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.cpp b/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.cpp deleted file mode 100644 index e36e2b459d..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.cpp +++ /dev/null @@ -1,251 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -extern "C" void* operator new(size_t size) -{ - /* printf("[C++] new %d\r\n", size); */ - return pvPortMalloc(size); -} - -extern "C" void* operator new[](size_t size) -{ - /* printf("[C++] new[] %d\r\n", size); */ - return pvPortMalloc(size); -} - -extern "C" void operator delete(void* ptr) { - /* printf("[C++] delete %p\r\n", ptr); */ - vPortFree(ptr); -} - -extern "C" void operator delete[](void* ptr) { - /* printf("[C++] delete[] %p\r\n", ptr); */ - vPortFree(ptr); -} - -BLLinkedItem::BLLinkedItem() -{ - this->next = NULL; -} - -BLLinkedItem* BLLinkedItem::attach(class BLLinkedItem &item) -{ - /*assert when next is NOT NULL*/ - if (this->next) { - printf("[ERR] next is NOT NULL. %p -->> %p\r\n", this->next, &item); - return NULL; - } else if (this == &item) { - printf("[ERR] linked to self. %p -->> %p\r\n", this, &item); - return NULL; - } - this->next = &item; - return this; -} - -BLLinkedItem* BLLinkedItem::detach() -{ - BLLinkedItem *tmp; - - tmp = this->next; - this->next = NULL; - - return tmp; -} - -BLLinkedList::BLLinkedList() -{ - this->head = NULL; - this->tail = NULL; -} - -BLLinkedList* BLLinkedList::push(class BLLinkedItem &item) -{ - printf("[BLLinkedList] push %p\r\n", &item); - - if (NULL == this->head) { - printf("new push\r\n"); - this->head = &item; - this->tail = &item; - return this; - } - /*tail should NOT be NULL, assert here if tail is NULL?*/ - printf("continue push\r\n"); - if (NULL == this->tail->attach(item)) { - return NULL; - } - this->tail = &item; - - return this; -} - -BLLinkedItem* BLLinkedList::pop() -{ - BLLinkedItem *item; - - if (NULL == this->head) { - printf("NULL HEAD\r\n"); - return NULL; - } - item = this->head; - this->head = item->detach(); - - printf("[POP] POP %p\r\n", item); - - return item; -} - -BLAesRequest::BLAesRequest() -{ - memset(this->key, 0, sizeof(this->key)); - memset(this->iv, 0, sizeof(this->iv)); - this->src = NULL; - this->dst = NULL; - this->len = 0; - this->first_use = 0; -} - -BLAesRequest::BLAesRequest(uint8_t *key, uint8_t *iv, uint8_t *src, uint8_t *dst, int len) -{ - memcpy(this->key, key, sizeof(this->key)); - if (iv) { - memcpy(this->iv, iv, sizeof(this->iv)); - } - this->src = src; - this->dst = dst; - this->len = len; - this->first_use = 0; -} - -int BLAesRequest::done_pre(int use_encryption) -{ - this->task_handle = xTaskGetCurrentTaskHandle(); - this->done = 0; - this->is_encryption = use_encryption; - - return 0; -} - -int BLAesRequest::done_wait() -{ - while (0 == this->done) { - ulTaskNotifyTake(pdTRUE, portMAX_DELAY); - } - return 0; -} - -int BLAesRequest::done_set() -{ - this->done = 1; - xTaskNotifyGive(this->task_handle); - - return 0; -} - -int BLAesRequest::done_set_auto() -{ - this->done = 1; - //TODO - printf("[C++] [%s] ongoing...\r\n", __PRETTY_FUNCTION__); - - return 0; -} - -int BLAesRequest::done_set_FromISR() -{ - BaseType_t xHigherPriorityTaskWoken; - - this->done = 1; - vTaskNotifyGiveFromISR(this->task_handle, &xHigherPriorityTaskWoken); - portYIELD_FROM_ISR(xHigherPriorityTaskWoken); - - return 0; -} - -int BLAesEngine::encryption(BLAesRequest &req) -{ - printf("%s %p...\r\n", __PRETTY_FUNCTION__, &req); - - /*request prepare*/ - req.done_pre(1); - /*push to queue and trigger if necessary*/ - if (NULL == this->push(req)) { - return -1; - } - this->encryption_trigger(); - /*request wait*/ - req.done_wait(); - - return 0; -} - -void BLAesEngine::encryption_trigger() -{ - /*Trigger SOFTIRQ if necessary*/ - return; -} - -void BLAesEngine::decryption_trigger() -{ - /*Trigger SOFTIRQ if necessary*/ - return; -} - -int BLAesEngine::decryption(BLAesRequest &req) -{ - printf("%s %p...\r\n", __PRETTY_FUNCTION__, &req); - - /*request prepare*/ - req.done_pre(0); - /*push to queue and trigger if necessary*/ - if (NULL == this->push(req)) { - return -1; - } - this->decryption_trigger(); - /*request wait*/ - req.done_wait(); - - return 0; -} - -static class BLAesEngine *aes_engine; -extern "C" int platform_hal_device_init(void) -{ - class BLAesRequest *aes_request = new BLAesRequest[6]; - aes_engine = new BLAesEngine(); - - (void)aes_request; -#if 0 - aes_engine->encryption(aes_request[0]); -#endif - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.h b/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.h deleted file mode 100644 index c884e3a080..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/platform_hal/platform_hal_device.h +++ /dev/null @@ -1,109 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef __PLATFORM_HAL_DEVICE_H__ -#define __PLATFORM_HAL_DEVICE_H__ -#include -#include - -#ifdef __cplusplus -extern "C" -{ -#endif -int platform_hal_device_init(void); - -/*TMP solution for getting API from c scope*/ -int printf(const char *fmt, ...); -void *memcpy(void *dst, const void *src, size_t n); -void *memset(void *s, int c, size_t n); - -#ifdef __cplusplus -} // extern "C" -#endif - -#ifdef __cplusplus -#include - -class BLLinkedItem { -private: - class BLLinkedItem *next; -public: - BLLinkedItem(); - class BLLinkedItem* attach(class BLLinkedItem &item); - class BLLinkedItem* detach(); -}; - -class BLAesRequest : public BLLinkedItem { -public: - uint32_t key[4]; - uint32_t iv[4]; - uint8_t *src; - uint8_t *dst; - size_t len; - int first_use; - - int is_encryption;//0 for encryption, 1 for decryption - /*section for task control*/ - TaskHandle_t task_handle; - int done; -public: - BLAesRequest(); - BLAesRequest(uint8_t *key, uint8_t *iv, uint8_t *src, uint8_t *dst, int len); - int done_pre(int use_encryption); - int done_wait(); - int done_set(); - int done_set_auto(); - int done_set_FromISR(); -}; - -class BLLinkedList { -protected: - class BLLinkedItem *head; - class BLLinkedItem *tail; -public: - BLLinkedList(); - class BLLinkedList* push(class BLLinkedItem &item); - class BLLinkedItem* pop(); - class BLLinkedList* dump(); -}; - -class BLAesEngine : public BLLinkedList { -private: - class BLLinkedList head; - - void encryption_trigger(); - void decryption_trigger(); -public: - int encryption(BLAesRequest &req); - int decryption(BLAesRequest &req); -}; - -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.c deleted file mode 100644 index 36d508123b..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.c +++ /dev/null @@ -1,231 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include "bl_sec_hw_common.h" -#include - -#define AES_ID SEC_ENG_AES_ID0 - -int bl_sec_aes_init() -{ -#ifdef BL616 - Sec_Eng_Group0_Request_AES_Access(); -#endif - Sec_Eng_AES_Enable_BE(AES_ID); - return 0; -} - -int bl_aes_acquire_hw() -{ - taskENTER_CRITICAL(); - return 0; -} - -int bl_aes_release_hw() -{ - taskEXIT_CRITICAL(); - return 0; -} - -int bl_aes_init(bl_sec_aes_t *aes) -{ - if (!aes) { - return -1; - } -#ifdef BL616 - if (bl_sec_is_cache_addr(aes)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)aes, sizeof(*aes)); - aes = bl_sec_get_no_cache_addr(aes); - } -#endif - memset(aes, 0, sizeof(*aes)); - aes->link_cfg.aesIntClr = 1; - aes->link_cfg.aesBlockMode = SEC_ENG_AES_ECB; - - return 0; -} - -int bl_aes_set_key(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *key, size_t key_len) -{ - if (!(aes && key && (key_len == 16 || key_len == 24 || key_len == 32))) { - return -1; - } - (void)op; - -#ifdef BL616 - aes = bl_sec_get_no_cache_addr(aes); -#endif - - aes->link_cfg.aesDecKeySel = SEC_ENG_AES_USE_NEW; - SEC_ENG_AES_Key_Type key_type; - if (key_len == 16) { - key_type = SEC_ENG_AES_KEY_128BITS; - } else if (key_len == 24) { - key_type = SEC_ENG_AES_KEY_192BITS; - } else { - key_type = SEC_ENG_AES_KEY_256BITS; - } - aes->link_cfg.aesMode = key_type; - memcpy(&aes->link_cfg.aesKey0, key, key_len); - - return 0; -} - -int bl_aes_transform(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *input, uint8_t *output) -{ - const uint16_t n_blk = 1; - if (!(aes && input && output)) { - return -1; - } - -#ifdef BL616 - aes = bl_sec_get_no_cache_addr(aes); - if (bl_sec_is_cache_addr(input)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)input, 16); - } - if (bl_sec_is_cache_addr(output) && input != output) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)output, 16); - } -#endif - aes->link_cfg.aesMsgLen = n_blk; - if (op == BL_AES_ENCRYPT) { - aes->link_cfg.aesDecEn = SEC_ENG_AES_ENCRYPTION; - } else { - aes->link_cfg.aesDecEn = SEC_ENG_AES_DECRYPTION; - } - - Sec_Eng_AES_Enable_Link(AES_ID); - Sec_Eng_AES_Link_Work(AES_ID, (uint32_t)&aes->link_cfg, input, n_blk << 4, output); - Sec_Eng_AES_Disable_Link(AES_ID); - - return 0; -} - - -/* - * Test cases - */ -#include -#include - -bool tc_aes_ecb() -{ - const void *plaintext = "Bouffalo Lab Ltd"; - const void *keys[3] = { - "0123456789ABCDEF", - "0123456789ABCDEF01234567", - "0123456789ABCDEF0123456789ABCDEF", - }; - const uint8_t ciphertext[][16] = { - {0x36, 0x6B, 0xE1, 0x1E, 0xB7, 0x89, 0x31, 0x23, 0xBD, 0x7A, 0x27, 0xAE, 0x46, 0xC4, 0x28, 0x7D}, - {0xBD, 0x1A, 0x22, 0xD1, 0x76, 0xC5, 0x8B, 0x53, 0x83, 0xE7, 0xB7, 0x26, 0xD6, 0x33, 0x2B, 0x61}, - {0xCC, 0xB7, 0x21, 0xB9, 0x7B, 0x18, 0x43, 0xA0, 0x5B, 0xA9, 0x2C, 0x55, 0xF1, 0x4D, 0x24, 0xF0}, - }; - const uint8_t keylen[3] = {16, 24, 32}; - - uint8_t output[16]; - - while (1) { - bl_sec_aes_t *aes = malloc(sizeof(*aes)); - void *buf = malloc(16); - - if (!aes || !buf) { - printf("Over\r\n"); - return true; - } - - printf("Test addr %p\r\n", aes); - for (int i = 0; i < 3; ++i) { - // 3 key lengths - for (int j = 0; j < 2; ++j) { - // 2 data sources - for (int k = 0; k < 2; ++k) { - // encrypt/decrypt - bl_sec_aes_op_t op = BL_AES_ENCRYPT; - if (k == 1) { - op = BL_AES_DECRYPT; - } - void *input = NULL; - if (j == 0) { - // input from flash - if (k == 0) { - input = (void *)plaintext; - } else { - input = (void *)ciphertext[i]; - } - } else { - // input from ram - input = buf; - if (k == 0) { - memcpy(input, plaintext, 16); - } else { - memcpy(input, ciphertext[i], 16); - } - } - - memset(output, 0, sizeof(output)); - bl_aes_init(aes); - bl_aes_set_key(aes, op, keys[i], keylen[i]); - bl_aes_transform(aes, op, input, output); - const void *exp_result = ciphertext[i]; - if (k == 1) { - exp_result = plaintext; - } - if (memcmp(output, exp_result, 16)) { - printf("AES-ECB (%d,%d,%d) failed\r\n", i, j, k); - return false; - } - } - } - } - } - return true; -} - -#define MD(tc) {tc, #tc} -static struct { - bool (*tc_fun)(void); - const char *desc; -} tc[] = { - MD(tc_aes_ecb), -}; - -int bl_sec_aes_mem_test(void) -{ - for (int i = 0; i < sizeof(tc) / sizeof(tc[0]); ++i) { - printf("Running test case %s\r\n", tc[i].desc); - if (tc[i].tc_fun()) { - printf("\t\tPassed\r\n"); - } else { - printf("\t\tFailed\r\n"); - } - } - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.h deleted file mode 100644 index c6ccbb51b0..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_aes.h +++ /dev/null @@ -1,79 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#pragma once - - -// copied struct from 616. Should be compatible with all chips -typedef struct -{ - uint32_t : 3; /*!< [2:0]Reserved */ - uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ - uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ - uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ - uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ - uint32_t : 1; /*!< [8]Reserved */ - uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ - uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ - uint32_t aesXTS : 1; /*!< [15]XTS mode select */ - uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t aesSrcAddr; /*!< Message source address */ - uint32_t aesDstAddr; /*!< Message destination address */ - uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ - uint32_t aesIV1; /*!< Big endian initial vector */ - uint32_t aesIV2; /*!< Big endian initial vector */ - uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ - uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */ - uint32_t aesKey1; /*!< Big endian aes key */ - uint32_t aesKey2; /*!< Big endian aes key */ - uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */ - uint32_t aesKey4; /*!< Big endian aes key */ - uint32_t aesKey5; /*!< Big endian aes key */ - uint32_t aesKey6; /*!< Big endian aes key */ - uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */ -} __attribute__((aligned(4))) bl_SEC_Eng_AES_Link_Config_Type; - -typedef enum { - BL_AES_ENCRYPT, - BL_AES_DECRYPT, -} bl_sec_aes_op_t; - -typedef struct { - bl_SEC_Eng_AES_Link_Config_Type link_cfg; -} bl_sec_aes_t; - -int bl_sec_aes_init(); -int bl_aes_acquire_hw(); -int bl_aes_release_hw(); -int bl_aes_init(bl_sec_aes_t *aes); -int bl_aes_set_key(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *key, size_t key_len); -int bl_aes_transform(bl_sec_aes_t *aes, bl_sec_aes_op_t op, const uint8_t *input, uint8_t *output); diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.c deleted file mode 100644 index 62c6ace600..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.c +++ /dev/null @@ -1,62 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include "bl_sec_hw_common.h" - -#ifdef BL616 -bool bl_sec_is_cache_addr(const void *addr) -{ - uintptr_t a = (uintptr_t)addr; - - if ((a & 0xFFFF0000UL) >= 0x62FC0000UL) { - return true; - } - return false; -} - -void *bl_sec_get_no_cache_addr(const void *addr) -{ - uintptr_t a = (uintptr_t)addr; - - if (!bl_sec_is_cache_addr(addr)) { - return (void *)addr; - } - - // OCRAM - if ((a & 0xF0000000UL) == 0x60000000UL) { - return (void *)((a & ~0xF0000000UL) | 0x20000000UL); - } - // pSRAM - if ((a & 0xF0000000UL) == 0xA0000000UL) { - return (void *)((a & ~0xF0000000UL) | 0x10000000UL); - } - - return NULL; -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.h deleted file mode 100644 index f7089cd9dc..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_common.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#pragma once - -#include - -typedef enum { - BL_SHA1, - BL_SHA224, - BL_SHA256, - BL_MD5, - BL_SHA384, - BL_SHA512, -} bl_sha_type_t; - -/* - * SHA1/SHA224/SHA256 - */ -/* copied SEC_Eng_SHA256_Ctx from stddrv */ -typedef struct { - uint32_t total[2]; - uint32_t *shaBuf; - uint32_t *shaPadding; - uint32_t linkAddr; -} bl_SEC_Eng_SHA256_Link_Ctx; - -// used for both SHA1/SHA224/SHA256 and SHA512 -typedef struct { - uint32_t shaCfgWord; - uint32_t shaSrcAddr; /*!< Message source address */ - uint32_t result[16]; /*!< Result of SHA */ -} __attribute__ ((aligned(4))) bl_SEC_Eng_SHA_Link_Config_Type; - -typedef struct bl_sha_ctx { - bl_sha_type_t type; - bl_SEC_Eng_SHA256_Link_Ctx ctx; - bl_SEC_Eng_SHA_Link_Config_Type link_cfg; - uint32_t tmp[16]; - uint32_t pad[16]; -} bl_sha_ctx_t; - - -/* - * SHA384/512 - */ -// copied SEC_Eng_SHA512_Link_Ctx from stddrv */ -typedef struct -{ - uint64_t total[2]; /*!< Number of bytes processed */ - uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint64_t *shaPadding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} bl_SEC_Eng_SHA512_Link_Ctx; - -typedef struct bl_sha512_ctx { - bl_sha_type_t type; - bl_SEC_Eng_SHA512_Link_Ctx ctx; - bl_SEC_Eng_SHA_Link_Config_Type link_cfg; - uint64_t tmp[16]; - uint64_t pad[16]; -} bl_sha512_ctx_t; diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_hw_common.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_hw_common.h deleted file mode 100644 index 0d2e1d9fc6..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_hw_common.h +++ /dev/null @@ -1,57 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#pragma once - -#include - -#ifdef BL602 -#include -#include -#elif defined BL616 -#include -#include -#define SHA512_CAPABLE -#elif defined BL702 -#include -#include -#elif defined BL702L -#include -#include -#elif defined BL808 -#include -#include -#define SHA512_CAPABLE -#define MD5_CAPABLE -#else -#warn "Chip not ported" -#endif - -bool bl_sec_is_cache_addr(const void *addr); -void *bl_sec_get_no_cache_addr(const void *addr); diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.c deleted file mode 100644 index 79defc9983..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.c +++ /dev/null @@ -1,71 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include - -#include -#include "bl_sec_hw_common.h" - -static StaticSemaphore_t pka_mutex_buf; -static SemaphoreHandle_t pka_mutex = NULL; - -int bl_sec_pka_init(void) -{ -#if defined(BL616) || defined BL808 - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); -#elif defined(BL702L) - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_SRC_HCLK); -#else - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_HCLK); -#endif - - pka_mutex = xSemaphoreCreateMutexStatic(&pka_mutex_buf); - if (pka_mutex) { - return 0; - } else { - return -1; - } -} - -int bl_sec_pka_mutex_take(void) -{ - if (pdPASS != xSemaphoreTake(pka_mutex, portMAX_DELAY)) { - return -1; - } - return 0; -} - -int bl_sec_pka_mutex_give(void) -{ - if (pdPASS != xSemaphoreGive(pka_mutex)) { - return -1; - } - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.h b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.h deleted file mode 100644 index a97f2165c2..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_pka.h +++ /dev/null @@ -1,37 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#ifndef BL_SEC_PKA_H_V3QMVSBY -#define BL_SEC_PKA_H_V3QMVSBY - -int bl_sec_pka_init(void); -int bl_sec_pka_mutex_take(void); -int bl_sec_pka_mutex_give(void); - -#endif /* end of include guard: BL_SEC_PKA_H_V3QMVSBY */ diff --git a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_sha.c b/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_sha.c deleted file mode 100644 index d6dc1bea8a..0000000000 --- a/bsp/bl808/m0/libraries/platform/hosal/sec_common/bl_sec_sha.c +++ /dev/null @@ -1,465 +0,0 @@ -/* - * Copyright (c) 2016-2022 Bouffalolab. - * - * This file is part of - * *** Bouffalolab Software Dev Kit *** - * (see www.bouffalolab.com). - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ -#include -#include -#include - -#include -#include - -#include -#include -#include "bl_sec_common.h" -#include "bl_sec_hw_common.h" - -#include - -#define BL_SHA_ID SEC_ENG_SHA_ID0 // this is the only valid value - -#ifdef BL602 -static bl_SEC_Eng_SHA_Link_Config_Type working_link_cfg __attribute__((section(".wifi_ram"))); -#elif defined BL616 -// Nothing -#else -#error "No support for this chip" -#endif - -int bl_sec_sha_init() -{ -#ifdef BL616 - Sec_Eng_Group0_Request_SHA_Access(); -#endif - Sec_Eng_SHA_Enable_Link(BL_SHA_ID); - - return 0; -} - -int bl_sha_mutex_take() -{ - taskENTER_CRITICAL(); - return 0; -} - -int bl_sha_mutex_give() -{ - taskEXIT_CRITICAL(); - return 0; -} - -#ifdef BL602 -static bool is_tcm_addr(void *addr) -{ - uintptr_t addr_masked = (uintptr_t)addr & 0x0FFFFFFFUL; - - // Checking upper boundary ought to be enough - #define BL602_END_OF_DTCM 0x02020000UL - if (addr_masked < BL602_END_OF_DTCM) { - return true; - } - return false; -} -#endif - -static int bl_to_drv_type(bl_sha_type_t type) -{ - const uint8_t map[] = { - [BL_SHA1] = SEC_ENG_SHA1, - [BL_SHA224] = SEC_ENG_SHA224, - [BL_SHA256] = SEC_ENG_SHA256, -#ifdef MD5_CAPABLE - [BL_MD5] = SEC_ENG_MD5, -#endif -#ifdef SHA512_CAPABLE - [BL_SHA384] = SEC_ENG_SHA384, - [BL_SHA512] = SEC_ENG_SHA512, -#endif - }; - if (type < sizeof(map)) { - return map[type]; - } - return -1; -} - - -/* - * SHA1/SHA224/SHA256 - */ -int bl_sha_init(bl_sha_ctx_t *ctx, const bl_sha_type_t type) -{ - if (!(type == BL_SHA1 || type == BL_SHA224 || type == BL_SHA256)) { - return -1; - } - const SEC_ENG_SHA_Type sha_type = (SEC_ENG_SHA_Type)bl_to_drv_type(type); - -#ifdef BL616 - if (bl_sec_is_cache_addr(ctx)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)ctx, sizeof(*ctx)); - ctx = bl_sec_get_no_cache_addr(ctx); - } -#endif - memset(ctx, 0, sizeof(*ctx)); - ctx->type = type; - SEC_Eng_SHA_Link_Config_Type *lc = (SEC_Eng_SHA_Link_Config_Type *)&ctx->link_cfg; - lc->shaMode = sha_type; - lc->shaIntSet = 1; - lc->shaIntClr = 1; - bl_SEC_Eng_SHA_Link_Config_Type *link_cfg = &ctx->link_cfg; -#ifdef BL602 - if (is_tcm_addr(ctx)) { - link_cfg = &working_link_cfg; - } -#endif - Sec_Eng_SHA256_Link_Init((SEC_Eng_SHA256_Link_Ctx *)&ctx->ctx, BL_SHA_ID, (uint32_t)link_cfg, ctx->tmp, ctx->pad); - return 0; -} - -int bl_sha_clone(bl_sha_ctx_t *dst, const bl_sha_ctx_t *src) -{ - if (!(dst && src)) { - return -1; - } - -#ifdef BL616 - if (bl_sec_is_cache_addr(dst)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)dst, sizeof(*dst)); - } - if (bl_sec_is_cache_addr(src)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)src, sizeof(*src)); - } - dst = bl_sec_get_no_cache_addr(dst); - src = bl_sec_get_no_cache_addr(src); -#endif - *dst = *src; - dst->ctx.shaBuf = dst->tmp; - dst->ctx.shaPadding = dst->pad; - dst->ctx.linkAddr = (uint32_t)&dst->link_cfg; -#ifdef BL602 - if (is_tcm_addr(dst)) { - dst->ctx.linkAddr = (uint32_t)&working_link_cfg; - } -#endif - return 0; -} - -int bl_sha_update(bl_sha_ctx_t *ctx, const uint8_t *input, uint32_t len) -{ -#ifdef BL602 - if (is_tcm_addr(ctx)) { - ARCH_MemCpy_Fast(&working_link_cfg, &ctx->link_cfg, sizeof(working_link_cfg)); - } -#elif defined BL616 - ctx = bl_sec_get_no_cache_addr(ctx); - if (bl_sec_is_cache_addr(input)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)input, len); - } -#endif - Sec_Eng_SHA256_Link_Update((SEC_Eng_SHA256_Link_Ctx *)&ctx->ctx, BL_SHA_ID, input, len); -#ifdef BL602 - if (is_tcm_addr(ctx)) { - ARCH_MemCpy_Fast(&ctx->link_cfg, &working_link_cfg, sizeof(working_link_cfg)); - } -#endif - return 0; -} - -int bl_sha_finish(bl_sha_ctx_t *ctx, uint8_t *hash) -{ -#ifdef BL602 - if (is_tcm_addr(ctx)) { - ARCH_MemCpy_Fast(&working_link_cfg, &ctx->link_cfg, sizeof(working_link_cfg)); - } -#elif defined BL616 - ctx = bl_sec_get_no_cache_addr(ctx); -#endif - Sec_Eng_SHA256_Link_Finish((SEC_Eng_SHA256_Link_Ctx *)&ctx->ctx, BL_SHA_ID, hash); - return 0; -} - - -/* - * SHA384/SHA512 - */ -#ifdef SHA512_CAPABLE -int bl_sha512_init(bl_sha512_ctx_t *ctx, const bl_sha_type_t type) -{ - if (!(type == BL_SHA384 || type == BL_SHA512)) { - return -1; - } - const SEC_ENG_SHA_Type sha_type = (SEC_ENG_SHA_Type)bl_to_drv_type(type); - -#ifdef BL616 - if (bl_sec_is_cache_addr(ctx)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)ctx, sizeof(*ctx)); - ctx = bl_sec_get_no_cache_addr(ctx); - } -#endif - memset(ctx, 0, sizeof(*ctx)); - ctx->type = type; - SEC_Eng_SHA_Link_Config_Type *lc = (SEC_Eng_SHA_Link_Config_Type *)&ctx->link_cfg; - lc->shaMode = sha_type; - lc->shaIntSet = 1; - lc->shaIntClr = 1; - bl_SEC_Eng_SHA_Link_Config_Type *link_cfg = &ctx->link_cfg; - Sec_Eng_SHA512_Link_Init((SEC_Eng_SHA512_Link_Ctx *)&ctx->ctx, BL_SHA_ID, (uint32_t)link_cfg, ctx->tmp, ctx->pad); - return 0; -} - -int bl_sha512_clone(bl_sha512_ctx_t *dst, const bl_sha512_ctx_t *src) -{ - if (!(dst && src)) { - return -1; - } - -#ifdef BL616 - if (bl_sec_is_cache_addr(dst)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)dst, sizeof(*dst)); - } - if (bl_sec_is_cache_addr(src)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)src, sizeof(*src)); - } - dst = bl_sec_get_no_cache_addr(dst); - src = bl_sec_get_no_cache_addr(src); -#endif - *dst = *src; - dst->ctx.shaBuf = dst->tmp; - dst->ctx.shaPadding = dst->pad; - dst->ctx.linkAddr = (uint32_t)&dst->link_cfg; - return 0; -} - -int bl_sha512_update(bl_sha512_ctx_t *ctx, const uint8_t *input, uint32_t len) -{ -#ifdef BL616 - ctx = bl_sec_get_no_cache_addr(ctx); - if (bl_sec_is_cache_addr(input)) { - L1C_DCache_Clean_Invalid_By_Addr((uintptr_t)input, len); - } -#endif - Sec_Eng_SHA512_Link_Update((SEC_Eng_SHA512_Link_Ctx *)&ctx->ctx, BL_SHA_ID, input, len); - return 0; -} - -int bl_sha512_finish(bl_sha512_ctx_t *ctx, uint8_t *hash) -{ -#ifdef BL616 - ctx = bl_sec_get_no_cache_addr(ctx); -#endif - Sec_Eng_SHA512_Link_Finish((SEC_Eng_SHA512_Link_Ctx *)&ctx->ctx, BL_SHA_ID, hash); - return 0; -} -#endif // SHA512_CAPABLE - - -/* - * Test cases - */ -#include - -static const char tc_hash_input[] = "The quick brown fox jumps over the lazy dog"; -bool tc_sha1() -{ - int i; - const bl_sha_type_t types[] = {BL_SHA1, BL_SHA224, BL_SHA256}; - uint8_t result[32]; - const uint8_t expected_results[][32] = { - {0x2f, 0xd4, 0xe1, 0xc6, 0x7a, 0x2d, 0x28, 0xfc, 0xed, 0x84, 0x9e, 0xe1, 0xbb, 0x76, 0xe7, 0x39, 0x1b, 0x93, 0xeb, 0x12, }, - {0x73, 0x0e, 0x10, 0x9b, 0xd7, 0xa8, 0xa3, 0x2b, 0x1c, 0xb9, 0xd9, 0xa0, 0x9a, 0xa2, 0x32, 0x5d, 0x24, 0x30, 0x58, 0x7d, 0xdb, 0xc0, 0xc3, 0x8b, 0xad, 0x91, 0x15, 0x25, }, - {0xd7, 0xa8, 0xfb, 0xb3, 0x07, 0xd7, 0x80, 0x94, 0x69, 0xca, 0x9a, 0xbc, 0xb0, 0x08, 0x2e, 0x4f, 0x8d, 0x56, 0x51, 0xe4, 0x6d, 0x3c, 0xdb, 0x76, 0x2d, 0x02, 0xd0, 0xbf, 0x37, 0xc9, 0xe5, 0x92, }, - }; - - const uint8_t z_2047_expected[][32] = { - {0xe3, 0x59, 0x9e, 0xf5, 0x8f, 0x6c, 0x1b, 0x77, 0x66, 0xf0, 0x45, 0x31, 0xb5, 0x01, 0xec, 0x24, 0x97, 0xb2, 0xa8, 0x2e, }, - {0xe6, 0xdb, 0x06, 0x25, 0xba, 0xb0, 0x0a, 0x65, 0xeb, 0x25, 0xeb, 0xcb, 0xe6, 0xd5, 0xc3, 0xb6, 0x6b, 0x04, 0xad, 0x12, 0xc8, 0x91, 0x25, 0xa3, 0x4e, 0x10, 0xfe, 0x6c, }, - {0xa6, 0xb4, 0xc4, 0x6a, 0xa0, 0xaa, 0xce, 0x53, 0x8f, 0x48, 0x4c, 0x2c, 0x7d, 0x3c, 0x96, 0x4b, 0x2c, 0x10, 0xb1, 0x95, 0x9b, 0xe4, 0xf9, 0xc6, 0x57, 0xa2, 0x7b, 0x37, 0xb6, 0xe7, 0x00, 0xe5, }, - }; - - while (1) { - uint8_t *in_buf; - bl_sha_ctx_t *ctx; - - for (int i = 0; i < 1; ++i) { - in_buf = malloc(2047); - ctx = malloc(sizeof(*ctx)); - if (!in_buf || !ctx) { - printf("Over!\r\n"); - while (1) { - } - } - } - printf("Test addr %p\r\n", ctx); - for (int j = 0; j < 1 * 1000; ++j) { - for (i = 0; i < sizeof(types) / sizeof(types[0]); ++i) { - size_t len = sizeof(tc_hash_input) - 1; - memcpy(in_buf, tc_hash_input, len); - bl_sha_init(ctx, types[i]); - bl_sha_update(ctx, in_buf, len); - memset(result, 0, sizeof(result)); - bl_sha_finish(ctx, result); - if (memcmp(result, expected_results[i], 32) != 0) { - printf("SHA1 #%d failed\r\n", i); - return false; - } - - // input from flash - bl_sha_init(ctx, types[i]); - bl_sha_update(ctx, (void *)tc_hash_input, len); - memset(result, 0, sizeof(result)); - bl_sha_finish(ctx, result); - if (memcmp(result, expected_results[i], 32) != 0) { - printf("SHA1 input from flash #%d failed\r\n", i); - return false; - } - - // 2047 Zs - size_t left = 2047; - memset(in_buf, 'Z', 2047); - bl_sha_init(ctx, types[i]); - while (left > 0) { - size_t l = (bl_rand() & 0xFFU) + 1; - if (l > left) { - l = left; - } - bl_sha_update(ctx, in_buf + (2047 - left), l); - left -= l; - } - memset(result, 0, sizeof(result)); - bl_sha_finish(ctx, result); - if (memcmp(result, z_2047_expected[i], 32) != 0) { - printf("SHA 2047-Z #%d failed\r\n", i); - return false; - } - } - } - } - return true; -} - -#ifdef SHA512_CAPABLE -bool tc_sha512() -{ - int i; - const bl_sha_type_t types[] = { - BL_SHA384, BL_SHA512, - }; - uint8_t result[64]; - const uint8_t expected_results[][64] = { - {0xca, 0x73, 0x7f, 0x10, 0x14, 0xa4, 0x8f, 0x4c, 0x0b, 0x6d, 0xd4, 0x3c, 0xb1, 0x77, 0xb0, 0xaf, 0xd9, 0xe5, 0x16, 0x93, 0x67, 0x54, 0x4c, 0x49, 0x40, 0x11, 0xe3, 0x31, 0x7d, 0xbf, 0x9a, 0x50, 0x9c, 0xb1, 0xe5, 0xdc, 0x1e, 0x85, 0xa9, 0x41, 0xbb, 0xee, 0x3d, 0x7f, 0x2a, 0xfb, 0xc9, 0xb1, }, - {0x07, 0xe5, 0x47, 0xd9, 0x58, 0x6f, 0x6a, 0x73, 0xf7, 0x3f, 0xba, 0xc0, 0x43, 0x5e, 0xd7, 0x69, 0x51, 0x21, 0x8f, 0xb7, 0xd0, 0xc8, 0xd7, 0x88, 0xa3, 0x09, 0xd7, 0x85, 0x43, 0x6b, 0xbb, 0x64, 0x2e, 0x93, 0xa2, 0x52, 0xa9, 0x54, 0xf2, 0x39, 0x12, 0x54, 0x7d, 0x1e, 0x8a, 0x3b, 0x5e, 0xd6, 0xe1, 0xbf, 0xd7, 0x09, 0x78, 0x21, 0x23, 0x3f, 0xa0, 0x53, 0x8f, 0x3d, 0xb8, 0x54, 0xfe, 0xe6, }, - }; - - const uint8_t z_2047_expected[][64] = { - {0x34, 0x1e, 0x3b, 0xd8, 0xf2, 0x3e, 0xc0, 0x3a, 0x26, 0x8a, 0x1d, 0x16, 0xc3, 0xe9, 0xf8, 0x0c, 0xeb, 0x5a, 0xd0, 0xe5, 0xf9, 0x79, 0x88, 0xa6, 0x2d, 0x39, 0x0b, 0x0e, 0x18, 0xb3, 0x1c, 0x42, 0x2c, 0xa0, 0x93, 0x72, 0x5a, 0x05, 0x94, 0x11, 0x3e, 0x65, 0x36, 0x16, 0x36, 0xcf, 0xe3, 0x24, }, - {0x62, 0x8e, 0x01, 0x46, 0x09, 0x53, 0x24, 0x5e, 0x40, 0x84, 0xe9, 0x06, 0x5b, 0x04, 0x7a, 0x92, 0xf5, 0xf6, 0x72, 0x7f, 0xfb, 0x93, 0x96, 0x35, 0x92, 0xed, 0xc9, 0x3b, 0xea, 0x62, 0x01, 0xf5, 0x66, 0x43, 0xf4, 0x9e, 0x70, 0xdf, 0x3c, 0x2a, 0x25, 0x19, 0xa6, 0xbc, 0x98, 0x36, 0xfe, 0x85, 0x05, 0xd1, 0x99, 0x76, 0x6d, 0x02, 0x35, 0xc5, 0x64, 0xbb, 0x16, 0x1f, 0x9b, 0x60, 0x99, 0x07, }, - }; - while (1) { - uint8_t *in_buf; - bl_sha512_ctx_t *ctx; - - for (int i = 0; i < 1; ++i) { - in_buf = malloc(2047); - ctx = malloc(sizeof(*ctx)); - if (!in_buf || !ctx) { - printf("Over!\r\n"); - while (1) { - } - } - } - printf("Test addr %p\r\n", ctx); - for (int j = 0; j < 1 * 1000; ++j) { - for (i = 0; i < sizeof(types) / sizeof(types[0]); ++i) { - size_t len = sizeof(tc_hash_input) - 1; - memcpy(in_buf, tc_hash_input, len); - bl_sha512_init(ctx, types[i]); - bl_sha512_update(ctx, in_buf, len); - memset(result, 0, sizeof(result)); - bl_sha512_finish(ctx, result); - if (memcmp(result, expected_results[i], 64) != 0) { - printf("SHA512 #%d failed\r\n", i); - return false; - } - - // input from flash - bl_sha512_init(ctx, types[i]); - bl_sha512_update(ctx, (void *)tc_hash_input, len); - memset(result, 0, sizeof(result)); - bl_sha512_finish(ctx, result); - if (memcmp(result, expected_results[i], 64) != 0) { - printf("SHA512 input from flash #%d failed\r\n", i); - return false; - } - - // 2047 Zs - size_t left = 2047; - memset(in_buf, 'Z', 2047); - bl_sha512_init(ctx, types[i]); - while (left > 0) { - size_t l = (bl_rand() & 0xFFU) + 1; - if (l > left) { - l = left; - } - bl_sha512_update(ctx, in_buf + (2047 - left), l); - left -= l; - } - memset(result, 0, sizeof(result)); - bl_sha512_finish(ctx, result); - if (memcmp(result, z_2047_expected[i], 64) != 0) { - printf("SHA 2047-Z #%d failed\r\n", i); - return false; - } - } - } - } - return true; -} -#endif - -#define MD(tc) {tc, #tc} -static struct { - bool (*tc_fun)(void); - const char *desc; -} tc[] = { - MD(tc_sha1), -#ifdef SHA512_CAPABLE - MD(tc_sha512), -#endif -}; - -int bl_sec_sha_test(void) -{ - for (int i = 0; i < sizeof(tc) / sizeof(tc[0]); ++i) { - printf("Running test case %s\r\n", tc[i].desc); - if (tc[i].tc_fun()) { - printf("\t\tPassed\r\n"); - } else { - printf("\t\tFailed\r\n"); - } - } - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_bsp_driver_glue.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_bsp_driver_glue.h deleted file mode 100644 index 614b7a351b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_bsp_driver_glue.h +++ /dev/null @@ -1,53 +0,0 @@ -/** - * ***************************************************************************** - * @file bflb_bsp_driver_glue.h - * @version 0.1 - * @date 2020-07-08 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#ifndef __bBFLB_BSP_DRIVER_GLUE_H__ -#define __bBFLB_BSP_DRIVER_GLUE_H__ - - -#include - -#include "bl808_common.h" -#include "bl808_sec_eng.h" -#include "bl808_glb.h" -#include "bl808_dma.h" -#include "bl808_usb.h" -#include "bl808_sdh.h" -#include "bl808_xip_sflash.h" - -#define CPU_FLASH_XIP_BASE BL606P_FLASH_XIP_BASE -#define CPU_FLASH_XIP_END BL606P_FLASH_XIP_END - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.c deleted file mode 100644 index 2448d3c28b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.c +++ /dev/null @@ -1,160 +0,0 @@ -/** - * ***************************************************************************** - * @file bflb_stub.c - * @version 0.1 - * @date 2020-07-08 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#include "bflb_stub.h" -#include "bflb_bsp_driver_glue.h" - - -void BFLB_Delay_Ms(uint32_t tim){ - ARCH_Delay_MS(tim); -} - -void BFLB_Delay_Us(uint32_t tim){ - ARCH_Delay_US(tim); -} - -int BFLB_BSP_Get_Random(uint8_t *data,uint32_t len) -{ - uint8_t tmpBuf[32]; - uint32_t readLen=0; - uint32_t i=0,cnt=0; - - while(readLensizeof(tmpBuf)){ - cnt=sizeof(tmpBuf); - } - for(i=0;i4){ - break; - } - }while(tmpValLow>tmpValLow1||tmpValHigh>tmpValHigh1); - - tmp=(SystemCoreClockGet()/(GLB_Get_BCLK_Div()+1)); - tmp=(tmp>>3)/1000; - - if(tmpValHigh1==0){ - return(uint64_t)(tmpValLow1/tmp); - }else{ - return (((uint64_t)tmpValHigh1<<32)+tmpValLow1)/tmp; - } -} - -void BFLB_BSP_Start_Time() -{ - *(volatile uint64_t*) (CLIC_CTRL_ADDR + CLIC_MTIME) = 0; -} - -void BFLB_BSP_Stop_Time() -{ - -} - -void BFLB_BSP_Set_Alarm_Time(uint64_t time) -{ - uint32_t tmp; - - tmp=(SystemCoreClockGet()/(GLB_Get_BCLK_Div()+1)); - tmp=(tmp>>3)/1000; - - time = time*tmp; - - *(volatile uint64_t*) (CLIC_CTRL_ADDR + CLIC_MTIMECMP) = (*(volatile uint64_t*) (CLIC_CTRL_ADDR + CLIC_MTIME) + time) ; - CPU_Interrupt_Enable(MTIME_IRQn); -} - -void BFLB_BSP_Set_Alarm_CallBack(void( *interruptFun )( void ) ) -{ - Interrupt_Handler_Register(MTIME_IRQn,interruptFun); -} - -void BFLB_BSP_Deinit_Time() -{ - CPU_Interrupt_Disable(MTIME_IRQn); - BFLB_BSP_Stop_Time(); -} - -void BFLB_BSP_Delay_Ms(uint32_t time) -{ - uint64_t cnt=0; - uint32_t clock=SystemCoreClockGet(); - uint64_t startTime=BFLB_BSP_Get_Time_Ms(); - - while(BFLB_BSP_Get_Time_Ms()-startTime(time*(clock>>(10+5)))*2){ - break; - } - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.h deleted file mode 100644 index 70aacb2cf2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bflb_stub.h +++ /dev/null @@ -1,54 +0,0 @@ -/** - * ***************************************************************************** - * @file bflb_stub.h - * @version 0.1 - * @date 2020-07-08 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#ifndef __BFLB_STUB__ -#define __BFLB_STUB__ - -#include "stdint.h" - -void BFLB_Delay_Ms(uint32_t tim); -void BFLB_Delay_Us(uint32_t tim); -int BFLB_BSP_Get_Random(uint8_t *data,uint32_t len); -void BFLB_BSP_Init_Time(void); -void BFLB_BSP_Clear_Time(void); -uint64_t BFLB_BSP_Get_Time_Ms(void); -void BFLB_BSP_Start_Time(void); -void BFLB_BSP_Stop_Time(void); -void BFLB_BSP_Set_Alarm_CallBack(void( *interruptFun )( void )); -void BFLB_BSP_Set_Alarm_Time(uint64_t time); -void BFLB_BSP_Deinit_Time(void); -void BFLB_BSP_Delay_Ms(uint32_t time); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/.gitignore b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/.gitignore deleted file mode 100644 index 03ec4f3e29..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/.gitignore +++ /dev/null @@ -1,3 +0,0 @@ -.vscode/* -.settings - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/blsp_boot2_iap_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/blsp_boot2_iap_flash.ld deleted file mode 100644 index 8778f84825..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/blsp_boot2_iap_flash.ld +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ -/* ToDo */ -PROVIDE(__boot2_pass_param_addr = 0x62057C00);/* 0x42030000+159*1024 */ -MEMORY -{ - xip_memory (rx) : ORIGIN = 0x58000000, LENGTH = 48K - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 48K - dtcm_memory (rx) : ORIGIN = 0x6202C000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x2202D000, LENGTH = 84K - ram_memory (!rx) : ORIGIN = 0x62042000, LENGTH = 16K -} - -SECTIONS -{ - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - KEEP(*startup*.*o(*.text*)) - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for usb desc */ - . = ALIGN(4); - _usb_desc_start = .; - KEEP(*(usb_desc)) - . = ALIGN(4); - _usb_desc_end = .; - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - /*__nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);*/ - - .nocache_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region (NOLOAD) : - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") - - .bl_bss : AT (__bss_start__) - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .nocache_noinit_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_noinit_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/cpu_flags.cmake deleted file mode 100644 index e30769db22..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/cpu_flags.cmake +++ /dev/null @@ -1,3 +0,0 @@ -include(${CMAKE_SOURCE_DIR}/drivers/${CHIP}_driver/startup/${CPU_ID}/cpu_flags.cmake) - -SET(BOOT2_LINKER_SCRIPT ${CMAKE_CURRENT_LIST_DIR}/blsp_boot2_iap_flash.ld) \ No newline at end of file diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/adc_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/adc_config.h deleted file mode 100644 index 68c0ffbca4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/adc_config.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _ADC_CONFIG_H -#define _ADC_CONFIG_H - -#define ADC_DATA_WIDIH_12 (0) - -#define ADC_V18_SELECT (2) /*!< ADC 1.8V select */ -#define ADC_V11_SELECT (1) /*!< ADC 1.1V select */ - -#define ADC_PGA_VCM (0) /*!< ADC VCM value */ -#define ADC_PGA_GAIN1 (0) /*!< PGA gain 1 */ -#define ADC_PGA_GAIN2 (0) /*!< PGA gain 2 */ -#define ADC_CHOP_MODE (2) /*!< ADC chop mode select */ -#define ADC_BIAS_SELECT (0) /*!< ADC current form main bandgap or aon bandgap */ -#define ADC_OFFSET_CALIB_EN (0) /*!< Offset calibration enable */ -#define ADC_OFFSER_CALIB_VAL (0) /*!< Offset calibration value */ - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/dac_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/dac_config.h deleted file mode 100644 index c611675bde..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/dac_config.h +++ /dev/null @@ -1,14 +0,0 @@ -#ifndef _DAC_CONFIG_H -#define _DAC_CONFIG_H - -/* | vref source | rng | output range | - * | Internal | 0 | 0.2~1V | - * | Internal | 1/2 | 0.224~1.425V | - * | Internal | 3 | 0.2~1.8V | - * | Extern | 0 | 0.1Vref~0.5Vref | - * | Extern | 1/2 | 0.1125Vref~0.7125Vref | - * | Extern | 3 | 0.1Vref~0.9Vref | - */ -#define DAC_REF_RNG_DEFAULT_SELECT (0x3) /*!< ADC 1.8V select */ - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/i2s_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/i2s_config.h deleted file mode 100644 index eeaf9f8784..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/i2s_config.h +++ /dev/null @@ -1,11 +0,0 @@ -#ifndef _I2S_CONFIG_H -#define _I2S_CONFIG_H - -#define I2S_ADUIO_PLL_DEFAULT AUDIO_PLL_12288000_HZ -#define I2S_DATA_ENDIAN I2S_DATA_ENDIAN_MSB -#define I2S_MONO_CHANNEL I2S_RX_MONO_MODE_LEFT_CHANNEL -#define I2S_LR_EXCHANGE DISABLE /*The position of L/R channel data within each entry is exchanged if enabled*/ -#define I2S_FS_INVERT DISABLE -#define I2S_BCLK_INVERT DISABLE - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/uart_config.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/uart_config.h deleted file mode 100644 index 96aa97821b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/default_config/uart_config.h +++ /dev/null @@ -1,17 +0,0 @@ -#ifndef _UART_CONFIG_H -#define _UART_CONFIG_H - -#define UART_CLOCK_SOURCE_96M_ENABLE (1) -#define UART_CTS_FLOWCONTROL_ENABLE (0) -#define UART_RTS_FLOWCONTROL_ENABLE (0) -#define UART_RX_DEGLITCH_ENABLE (0) -#define UART_MSB_FIRST_ENABLE (0) -#define UART_TX_SWCONTROL_ENABLE (0) -#define UART_TX_LINMODE_ENABLE (0) -#define UART_RX_LINMODE_ENABLE (0) -#define UART_TX_BREAKBIT_CNT (0) - -#define UART_FIFO_MAX_LEN 32 -#define UART_DEFAULT_RTO_TIMEOUT 100 - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_adc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_adc.h deleted file mode 100644 index f956db98f2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_adc.h +++ /dev/null @@ -1,176 +0,0 @@ -/** - * @file hal_adc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_ADC__H__ -#define __HAL_ADC__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_ADC_CHANNEL_START 0x10 -#define DEVICE_CTRL_ADC_CHANNEL_STOP 0x11 -#define DEVICE_CTRL_ADC_CHANNEL_CONFIG 0x12 -#define DEVICE_CTRL_ADC_VBAT_ON 0x13 -#define DEVICE_CTRL_ADC_VBAT_OFF 0x14 -#define DEVICE_CTRL_ADC_TSEN_ON 0x15 -#define DEVICE_CTRL_ADC_TSEN_OFF 0x16 - -enum adc_index_type { -#ifdef BSP_USING_ADC0 - ADC0_INDEX, -#endif - ADC_MAX_INDEX -}; - -#define adc_channel_start(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_START, NULL) -#define adc_channel_stop(dev) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_STOP, NULL) -#define adc_channel_config(dev, list) device_control(dev, DEVICE_CTRL_ADC_CHANNEL_CONFIG, list) - -typedef enum { - ADC_CHANNEL0, /* ADC channel 0 */ - ADC_CHANNEL1, /* ADC channel 1 */ - ADC_CHANNEL2, /* ADC channel 2 */ - ADC_CHANNEL3, /* ADC channel 3 */ - ADC_CHANNEL4, /* ADC channel 4 */ - ADC_CHANNEL5, /* ADC channel 5 */ - ADC_CHANNEL6, /* ADC channel 6 */ - ADC_CHANNEL7, /* ADC channel 7 */ - ADC_CHANNEL8, /* ADC channel 8 */ - ADC_CHANNEL9, /* ADC channel 9 */ - ADC_CHANNEL10, /* ADC channel 10 */ - ADC_CHANNEL11, /* ADC channel 11 */ - ADC_CHANNEL_DAC_OUTA, /* DACA, ADC channel 12 */ - ADC_CHANNEL_DAC_OUTB, /* DACB, ADC channel 13 */ - ADC_CHANNEL_TSEN_P, /* TSenp, ADC channel 14 */ - ADC_CHANNEL_TSEN_N, /* TSenn, ADC channel 15 */ - ADC_CHANNEL_VREF, /* Vref, ADC channel 16 */ - ADC_CHANNEL_DCTEST, /* DCTest, ADC channel 17 */ - ADC_CHANNEL_VABT_HALF, /* VBAT/2, ADC channel 18 */ - ADC_CHANNEL_SENP3, /* SenVP3, ADC channel 19 */ - ADC_CHANNEL_SENP2, /* SenVP2, ADC channel 20 */ - ADC_CHANNEL_SENP1, /* SenVP1, ADC channel 21 */ - ADC_CHANNEL_SENP0, /* SenVP0, ADC channel 22 */ - ADC_CHANNEL_GND, /* GND, ADC channel 23 */ -} adc_channel_t; - -typedef enum { - ADC_CLOCK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ - ADC_CLOCK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ - ADC_CLOCK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ - ADC_CLOCK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ - ADC_CLOCK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ - ADC_CLOCK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ - ADC_CLOCK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ - ADC_CLOCK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ -} adc_clk_div_t; - -typedef enum { - ADC_VREF_3V2 = 0, /* ADC select 3.2V as reference voltage */ - ADC_VREF_2V = 1, /* ADC select 2V as reference voltage */ -} adc_vref_t; - -/** - * @brief ADC data width type definition - */ -typedef enum { - ADC_DATA_WIDTH_12B, /*!< ADC 12 bits */ - ADC_DATA_WIDTH_14B_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ - ADC_DATA_WIDTH_14B_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */ - ADC_DATA_WIDTH_16B_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ - ADC_DATA_WIDTH_16B_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ -} adc_data_width_t; - -/** - * @brief ADC FIFO threshold type definition - */ -typedef enum { - ADC_FIFO_THRESHOLD_1BYTE, /*!< ADC FIFO threshold is 1 */ - ADC_FIFO_THRESHOLD_4BYTE, /*!< ADC FIFO threshold is 4 */ - ADC_FIFO_THRESHOLD_8BYTE, /*!< ADC FIFO threshold is 8 */ - ADC_FIFO_THRESHOLD_16BYTE, /*!< ADC FIFO threshold is 16 */ -} adc_fifo_threshold_t; - -/** - * @brief ADC PGA gain type definition - */ -typedef enum { - ADC_GAIN_NONE, /*!< No PGA gain */ - ADC_GAIN_1, /*!< PGA gain 1 */ - ADC_GAIN_2, /*!< PGA gain 2 */ - ADC_GAIN_4, /*!< PGA gain 4 */ - ADC_GAIN_8, /*!< PGA gain 8 */ - ADC_GAIN_16, /*!< PGA gain 16 */ - ADC_GAIN_32, /*!< PGA gain 32 */ -} adc_pga_gain_t; - -enum adc_event_type { - ADC_EVENT_UNDERRUN, - ADC_EVENT_OVERRUN, - ADC_EVENT_FIFO, - ADC_EVENT_UNKNOWN -}; - -enum adc_it_type { - ADC_UNDERRUN_IT = 1 << 2, - ADC_OVERRUN_IT = 1 << 3, - ADC_FIFO_IT = 1 << 5, -}; - -typedef struct { - uint8_t *pos_channel; - uint8_t *neg_channel; - uint8_t num; -} adc_channel_cfg_t; - -typedef struct { - int8_t posChan; /*!< Positive channel */ - int8_t negChan; /*!< Negative channel */ - uint16_t value; /*!< ADC value */ - float volt; /*!< ADC voltage result */ -} adc_channel_val_t; - -typedef struct adc_device { - struct device parent; - adc_clk_div_t clk_div; /* CLK is not more than 2Mhz */ - adc_vref_t vref; /* ADC voltage reference*/ - bool continuous_conv_mode; /** conversion mode: shot conversion mode or continuous conversion mode. */ - bool differential_mode; /** Channel type: single-ended or differential. */ - adc_data_width_t data_width; - adc_fifo_threshold_t fifo_threshold; - adc_pga_gain_t gain; -} adc_device_t; - -#define ADC_DEV(dev) ((adc_device_t *)dev) - -int adc_register(enum adc_index_type index, const char *name); -int adc_trim_tsen(uint16_t *tsen_offset); -float adc_get_tsen(uint16_t tsen_offset); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_audio.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_audio.h deleted file mode 100644 index 2131b47661..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_audio.h +++ /dev/null @@ -1,261 +0,0 @@ -/** - * @file hal_audio.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __HAL_AUDIO__ -#define __HAL_AUDIO__ - -#include "audio_reg.h" -#include "bl808_audio.h" -#include "bl808_dma.h" -#include "drv_device.h" - -/** @addtogroup BL808_Middleware_Driver - * @{ - */ - -/** @addtogroup AUDIO_Middleware - * @{ - */ - -/** @defgroup AUDIO_Middleware_Public_Types - * @{ - */ - -/** - * @brief Audio Flow Type - */ -typedef enum { - AUDIO_PLAY = 0, /*!< Audio Play selction */ - AUDIO_RECORDING, /*!< Audio Recording selction */ -} Audio_Flow_Type; - -/** - * @brief Audio Channel Sel - */ -typedef enum { - LEFT_CHANNEL = 1, /*!< select mono mode left only */ - RIGHT_CHANNEL, /*!< select mono mode right only */ - STEREO_CHANNEL, /*!< select stereo */ -} Audio_Channel_Type; - -/** - * @brief Audio mixer option - */ -typedef enum { - MIX_WITH_ADC_LEFT = 1, /*!< mix With ADC Left */ - MIX_WITH_ADC_RIGHT, /*!< mix With ADC Right */ -} Audio_Mixer_Cfg_Type; - -/** - * @brief Audio Play/recording bit width - */ -typedef enum { - AUDIO_BIT_WIDTH_16, /*!< 16 bit */ - AUDIO_BIT_WIDTH_24, /*!< 24 bit */ - AUDIO_BIT_WIDTH_32, /*!< 32 bit */ -} Audio_BitWidth_Type; - -/** - * @brief Audio Input Interface - */ -typedef enum { - AUDIO_INPUT_PDM_DMIC, /*!< audio input source is Dmic */ - AUDIO_INPUT_ANG_AMIC, /*!< audio input source is Amic */ -} Audio_RecordingInterface_Type; - -/** - * @brief Audio_PlayCfg_Type - */ -typedef struct { - DMA_ID_Type audioDmaId; /*!< audio dma id */ - DMA_Chan_Type audioDmaChannelId; /*!< audio dma channel id */ - uint32_t playSampleRate; /*!< audio play sample rate */ - Audio_BitWidth_Type playBitWidth; /*!< audio play bit width */ - Audio_Channel_Type channel; /*!< audio play channel number */ - uint16_t audioInitVolume; /*!< initial audio volume */ - void (*pingpongBufferCarryDoneCallback)(uint8_t pp_index); /*!< audio dma carry pingpong buffer done callback function pointer */ - void (*volumeSetDoneCallback)(uint8_t dac_index); /*!< When the volume is adjusted this function pointer will be run */ - BL_Fun_Type audioMixerEn; /*!< enable mixer or not */ - Audio_Mixer_Cfg_Type dacLeftMixWith; /*!< select dac left channel mix with adc right or left */ - Audio_Mixer_Cfg_Type dacRightMixWith; /*!< select dac right channel mix with adc right or left */ -} Audio_PlayCfg_Type; - -/** - * @brief Audio_RecordingCfg_Type - */ -typedef struct { - DMA_ID_Type audioDmaId; /*!< audio dma id */ - DMA_Chan_Type audioDmaChannelId; /*!< audio dma channel id */ - uint32_t recordingSampleRate; /*!< audio Recording sample rate */ - Audio_RecordingInterface_Type recordinginterface; /*!< audio Recording input interface */ - Audio_BitWidth_Type recordingBitWidth; /*!< audio Recording bit width */ - Audio_Channel_Type channel; /*!< audio Recording channel number */ - uint16_t audioInitVolume; /*!< initial audio Recording volume */ - void (*pingpongBufferCarryDoneCallback)(uint8_t pp_index); /*!< audio dma carry pingpong buffer done callback function pointer */ - void (*volumeSetDoneCallback)(uint8_t adc_index); /*!< When the volume is adjusted this function pointer will be run */ -} Audio_RecordingCfg_Type; - -/*@} end of group AUDIO_Middleware_Public_Types */ - -/** @defgroup AUDIO_Middleware_Public_Constants - * @{ - */ - -/** @defgroup AUDIO_FLOW_TYPE - * @{ - */ -#define IS_AUDIO_FLOW_TYPE(type) (((type) == AUDIO_PLAY) || \ - ((type) == AUDIO_RECORDING)) - -/** @defgroup AUDIO_CHANNEL_TYPE - * @{ - */ -#define IS_AUDIO_CHANNEL_TYPE(type) (((type) == LEFT_CHANNEL) || \ - ((type) == RIGHT_CHANNEL) || \ - ((type) == STEREO_CHANNEL)) - -/** @defgroup AUDIO_MIXER_CFG_TYPE - * @{ - */ -#define IS_AUDIO_MIXER_CFG_TYPE(type) (((type) == MIX_WITH_ADC_LEFT) || \ - ((type) == MIX_WITH_ADC_RIGHT)) - -/** @defgroup AUDIO_BITWIDTH_TYPE - * @{ - */ -#define IS_AUDIO_BITWIDTH_TYPE(type) (((type) == AUDIO_BIT_WIDTH_16) || \ - ((type) == AUDIO_BIT_WIDTH_24) || \ - ((type) == AUDIO_BIT_WIDTH_32)) - -/** @defgroup AUDIO_RECORDINGINTERFACE_TYPE - * @{ - */ -#define IS_AUDIO_RECORDINGINTERFACE_TYPE(type) (((type) == AUDIO_INPUT_PDM_DMIC) || \ - ((type) == AUDIO_INPUT_ANG_AMIC)) - -/*@} end of group AUDIO_Middleware_Public_Constants */ - -/** @defgroup AUDIO_Middleware_Public_Macros - * @{ - */ -#define AUDIO_PLAY_PINGPONG_BUFFER_SIZE (2 * 1024) -#define AUDIO_RECORDING_PINGPONG_BUFFER_SIZE (2 * 1024) -#define AUDIO_TX_FIFO_ADDR AUDIO_BASE + 0x94 -#define AUDIO_RX_FIFO_ADDR AUDIO_BASE + 0x88 -#define AUDIO_DEFAULT_TX_DRQ_THR 8 -#define AUDIO_DEFAULT_RX_DRQ_THR 8 -/* audio play configuration */ -#define AUDIO_PLAY_DEFAULT_DMA_ID DMA0_ID -#define AUDIO_PLAY_DEFAULT_DMA_CHANNEL DMA_CH0 -#define AUDIO_PLAY_DEFAULT_SAMPLE 48 * 1000 -#define AUDIO_PLAY_DEFAULT_BIT_WIDTH AUDIO_BIT_WIDTH_16 -#define AUDIO_PLAY_DEFAULT_INITIAL_VOLUME 0xffad -#define AUDIO_PLAY_DEFAULT_CHANNEL_NUM STEREO_CHANNEL -#define AUDIO_PLAY_DEFAULT_MIXER_EN DISABLE -#define AUDIO_PLAY_DEFAULT_LEFT_MIX_WITH MIX_WITH_ADC_LEFT -#define AUDIO_PLAY_DEFAULT_RIGHT_MIX_WITH MIX_WITH_ADC_RIGHT -/*audio recording configuration */ -#define AUDIO_RECORDING_DEFAULT_DMA_ID DMA0_ID -#define AUDIO_RECORDING_DEFAULT_DMA_CHANNEL DMA_CH1 -#define AUDIO_RECORDING_DEFAULT_SAMPLE 16 * 1000 -#define AUDIO_RECORDING_DEFAULT_BIT_WIDTH AUDIO_BIT_WIDTH_16 -#define AUDIO_RECORDING_DEFAULT_INITIAL_VOLUME 60 -/* if user want to select more adc channel option , -* you can write such as -* ADC1_DATA_CHANNEL_FIFO_EN | ADC3_DATA_CHANNEL_FIFO_EN | -* middleware default set is (ADC1_DATA_CHANNEL_FIFO_EN | ADC2_DATA_CHANNEL_FIFO_EN) equel to STEREO_CHANNEL -**/ -#define AUDIO_RECORDING_DEFAULT_CHANNEL_NUM STEREO_CHANNEL -#define AUDIO_RECORDING_DEFAULT_INTERFACE AUDIO_INPUT_PDM_DMIC - -/*@} end of group AUDIO_Middleware_Public_Macros */ - -/** @defgroup AUDIO_Middleware_Public_Functions - * @{ - */ -/* Audio Play Profile API */ -BL_Err_Type Audio_PlayDeInit(void); -BL_Err_Type Audio_PlayInit(Audio_PlayCfg_Type *cfg); -BL_Err_Type Audio_PlayParameterInit(Audio_PlayCfg_Type *cfg); -BL_Err_Type Audio_PlaySetVolume(Audio_Channel_Type channel, int16_t volume); -int16_t Audio_PlayGetVolume(Audio_Channel_Type channel); -BL_Err_Type Audio_PlayStart(Audio_PlayCfg_Type *cfg); -BL_Err_Type Audio_PlayStop(Audio_PlayCfg_Type *cfg); -/* Audio Recording API */ -BL_Err_Type Audio_RecordingDeInit(void); -BL_Err_Type Audio_RecordingInit(Audio_RecordingCfg_Type *cfg); -BL_Err_Type Audio_RecordingParameterInit(Audio_RecordingCfg_Type *cfg); -BL_Err_Type Audio_RecordingSetVolume(Audio_Channel_Type channel, int16_t volume); -int16_t Audio_RecordingGetVolume(Audio_Channel_Type channel); -BL_Err_Type Audio_RecordingStart(Audio_RecordingCfg_Type *cfg); -BL_Err_Type Audio_RecordingStop(Audio_RecordingCfg_Type *cfg); -/* Audio AEC API */ -BL_Err_Type Audio_AecInit(BL_Fun_Type sw, Audio_Channel_Type channel, - Audio_AEC_Atten_Mode aecDrop, Audio_PlayCfg_Type *playCfg, Audio_RecordingCfg_Type *recordingCfg); -uint32_t Audio_GetPingpongBufferAddr(Audio_Flow_Type flowType); -uint32_t Audio_GetPingBufferAddr(Audio_Flow_Type flowType); -uint32_t Audio_GetPongBufferAddr(Audio_Flow_Type flowType); -uint32_t Audio_GetPingpongBufferLength(Audio_Flow_Type flowType); -void Audio_FlushPingpongBuffer(Audio_Flow_Type flowType); - -//--adapt - -#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10 -#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11 - -enum audio_index_type { -#ifdef BSP_USING_AUDIO - AUDIO0_INDEX, -#endif - AUDIO_MAX_INDEX -}; - -typedef struct audio_device { - struct device parent; - uint32_t sampleRate; - Audio_BitWidth_Type bitWidth; - Audio_Channel_Type channel; - uint16_t audioInitVolume; - void (*pingpongBufferCarryDoneCallback)(uint8_t pp_index); - void (*volumeSetDoneCallback)(uint8_t dac_index); - void *tx_dma; - void *rx_dma; -} audio_device_t; - -#define AUDIO_DEV(dev) ((audio_device_t *)dev) - -#define DEVICE_CTRL_PLAY_VOLUME 0x0E -#define DEVICE_CTRL_RECORDING_VOLUME 0x0F - -#define DEVICE_CTRL_RECORDING_START 0x10 -#define DEVICE_CTRL_RECORDING_STOP 0x11 -#define DEVICE_CTRL_PLAY_START 0x12 -#define DEVICE_CTRL_PLAY_STOP 0x13 - -#define DEVICE_CTRL_GET_PLAY_PING_BUF 0x14 -#define DEVICE_CTRL_GET_PLAY_PONG_BUF 0x15 -#define DEVICE_CTRL_GET_RECORD_PING_BUF 0x16 -#define DEVICE_CTRL_GET_RECORD_PONG_BUF 0x17 - -int audio_register(enum audio_index_type index, const char *name); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_boot2.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_boot2.h deleted file mode 100644 index 0de6107507..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_boot2.h +++ /dev/null @@ -1,323 +0,0 @@ -/** - * ***************************************************************************** - * @file hal_boot2_custom.h - * @version 0.1 - * @date 2021-07-17 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#ifndef __HAL_BOOT2_H__ -#define __HAL_BOOT2_H__ - -#include "hal_common.h" -#include "bl808_sflash.h" -#include "bl808_glb.h" - -#define HAL_PLL_CFG_MAGICCODE "PCFG" - -#define HAL_BOOT2_PK_HASH_SIZE 256 / 8 -#define HAL_BOOT2_IMG_HASH_SIZE 256 / 8 -#define HAL_BOOT2_ECC_KEYXSIZE 256 / 8 -#define HAL_BOOT2_ECC_KEYYSIZE 256 / 8 -#define HAL_BOOT2_SIGN_MAXSIZE (2048 / 8) -#define HAL_BOOT2_DEADBEEF_VAL 0xdeadbeef -#define HAL_BOOT2_CPU0_MAGIC "BFNP" -#define HAL_BOOT2_CPU1_MAGIC "BFAP" -#define HAL_BOOT2_CP_FLAG 0x02 -#define HAL_BOOT2_MP_FLAG 0x01 -#define HAL_BOOT2_SP_FLAG 0x00 - -#define HAL_BOOT2_SUPPORT_DECOMPRESS 1 /* 1 support decompress, 0 not support */ -#define HAL_BOOT2_SUPPORT_USB_IAP 0 /* 1 support IAP, 0 not support */ -#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_RAM 0 /* 1 support eflash loader ram, 0 not support */ -#define HAL_BOOT2_SUPPORT_EFLASH_LOADER_FLASH 0 /* 1 support eflash loader flash, 0 not support */ -#define HAL_BOOT2_SUPPORT_SIGN_ENCRYPT 1 /* 1 support sign and encrypt, 0 not support */ - -#define HAL_BOOT2_CPU_GROUP_MAX 1 -#define HAL_BOOT2_CPU_MAX 3 -#define HAL_BOOT2_RAM_IMG_COUNT_MAX 5 - -#define HAL_BOOT2_FW_IMG_OFFSET_AFTER_HEADER 4 * 1024 -#define HAL_BOOT2_MFG_START_REQUEST_OFFSET 8 * 1024 - -#define HAL_BOOT2_PSRAM_INFO_MASK (0xff0000) -#define HAL_BOOT2_PSRAM_INFO_POS (16) - -struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg0_t { - uint32_t bootrom_protect : 1; /* ef_sw_usage_0 bit [0] */ - uint32_t uart_log_disable : 1; /* ef_sw_usage_0 bit [1] */ - uint32_t boot_pin_cfg : 1; /* ef_sw_usage_0 bit [2] */ - //uint32_t dbg_pin_cfg : 1; /* ef_sw_usage_0 bit [3] */ - uint32_t uart_download_cfg : 1; /* ef_sw_usage_0 bit [3] */ - - uint32_t mediaboot_disable : 1; /* ef_sw_usage_0 bit [4] */ - uint32_t uartboot_disable : 1; /* ef_sw_usage_0 bit [5] */ - uint32_t usbboot_enable : 1; /* ef_sw_usage_0 bit [6] */ - uint32_t uart_log_reopen : 1; /* ef_sw_usage_1 bit [7] */ - - uint32_t sign_cfg : 1; /* ef_sw_usage_0 bit [8] */ - uint32_t dcache_disable : 1; /* ef_sw_usage_0 bit [9] */ - uint32_t jtag_cfg : 2; /* ef_sw_usage_0 bit [11:10] */ - - uint32_t fix_key_sel : 1; /* ef_sw_usage_0 bit [12] */ - - uint32_t sdh_en : 1; /* ef_sw_usage_1 bit [13] */ - uint32_t sf_pin_cfg : 5; /* ef_sw_usage_0 bit [18:14] */ - uint32_t boot_level_revert : 1; /* ef_sw_usage_0 bit [19] */ - - uint32_t boot_pin_dly : 2; /* ef_sw_usage_0 bit [21:20] */ - uint32_t ldo_trim_enable : 1; /* ef_sw_usage_0 bit [22] */ - uint32_t trim_enable : 1; /* ef_sw_usage_0 bit [23] */ - - uint32_t no_hd_boot_en : 1; /* ef_sw_usage_0 bit [24] */ - uint32_t flash_power_delay : 2; /* ef_sw_usage_0 bit [26:25] */ - uint32_t tz_boot : 1; /* ef_sw_usage_0 bit [27] */ - - uint32_t encrypted_tz_boot : 1; /* ef_sw_usage_0 bit [28] */ - uint32_t hbn_check_sign : 1; /* ef_sw_usage_0 bit [29] */ - uint32_t keep_dbg_port_closed : 1; /* ef_sw_usage_0 bit [30] */ - uint32_t hbn_jump_disable : 1; /* ef_sw_usage_0 bit [31] */ -}; - -struct __attribute__((packed, aligned(4))) boot_efuse_sw_cfg1_t { - uint32_t xtal_type : 3; /* ef_sw_usage_1 bit [2:0] */ - uint32_t wifipll_pu : 1; /* ef_sw_usage_1 bit [3] */ - - uint32_t aupll_pu : 1; /* ef_sw_usage_1 bit [4] */ - uint32_t cpupll_pu : 1; /* ef_sw_usage_1 bit [5] */ - uint32_t mipipll_pu : 1; /* ef_sw_usage_1 bit [6] */ - uint32_t uhspll_pu : 1; /* ef_sw_usage_1 bit [7] */ - - uint32_t mcu_clk : 3; /* ef_sw_usage_1 bit [10:8] */ - uint32_t mcu_clk_div : 1; /* ef_sw_usage_1 bit [11] */ - - uint32_t mcu_pbclk_div : 2; /* ef_sw_usage_1 bit [13:12] */ - uint32_t lp_div : 1; /* ef_sw_usage_1 bit [14] */ - uint32_t dsp_clk : 2; /* ef_sw_usage_1 bit [16:15] */ - uint32_t dsp_clk_div : 1; /* ef_sw_usage_1 bit [17] */ - uint32_t dsp_pbclk : 2; /* ef_sw_usage_1 bit [19:18] */ - - uint32_t emi_clk : 2; /* ef_sw_usage_1 bit [21:20] */ - uint32_t emi_clk_div : 1; /* ef_sw_usage_1 bit [22] */ - uint32_t flash_clk_type : 3; /* ef_sw_usage_1 bit [25:23] */ - uint32_t flash_clk_div : 1; /* ef_sw_usage_1 bit [26] */ - uint32_t ldo18flash_bypass_cfg : 1; /* ef_sw_usage_1 bit [27] */ - uint32_t bootlog_pin_cfg : 1; /* ef_sw_usage_1 bit [28] */ - - uint32_t abt_offset : 1; /* ef_sw_usage_1 bit [29] */ - uint32_t boot_pull_cfg : 1; /* ef_sw_usage_1 bit [30] */ - uint32_t usb_if_int_disable : 1; /* ef_sw_usage_1 bit [31] */ -}; - -typedef struct -{ - uint8_t encrypted[HAL_BOOT2_CPU_GROUP_MAX]; - uint8_t sign[HAL_BOOT2_CPU_GROUP_MAX]; - uint8_t hbn_check_sign; - uint8_t rsvd[3]; - uint8_t chip_id[8]; - uint8_t pk_hash_cpu0[HAL_BOOT2_PK_HASH_SIZE]; - uint8_t pk_hash_cpu1[HAL_BOOT2_PK_HASH_SIZE]; - uint8_t uart_download_cfg; - uint8_t sf_pin_cfg; - uint8_t keep_dbg_port_closed; - uint8_t boot_pin_cfg; - uint32_t dev_info; -} boot2_efuse_hw_config; - -struct __attribute__((packed, aligned(4))) hal_flash_config { - uint32_t magicCode; /*'FCFG'*/ - SPI_Flash_Cfg_Type cfg; - uint32_t crc32; -}; - -struct __attribute__((packed, aligned(4))) hal_sys_clk_config { - uint8_t xtal_type; - uint8_t mcu_clk; - uint8_t mcu_clk_div; - uint8_t mcu_bclk_div; - - uint8_t mcu_pbclk_div; - uint8_t lp_div; - uint8_t dsp_clk; - uint8_t dsp_clk_div; - - uint8_t dsp_bclk_div; - uint8_t dsp_pbclk; - uint8_t dsp_pbclk_div; - uint8_t emi_clk; - - uint8_t emi_clk_div; - uint8_t flash_clk_type; - uint8_t flash_clk_div; - uint8_t wifipll_pu; - - uint8_t aupll_pu; - uint8_t cpupll_pu; - uint8_t mipipll_pu; - uint8_t uhspll_pu; -}; - -typedef struct { - uint32_t magiccode; - struct hal_sys_clk_config cfg; - uint32_t crc32; -} hal_pll_config; - -struct __attribute__((packed, aligned(4))) hal_basic_cfg_t { - uint32_t sign_type : 2; /* [1: 0] for sign */ - uint32_t encrypt_type : 2; /* [3: 2] for encrypt */ - uint32_t key_sel : 2; /* [5: 4] key slot */ - uint32_t xts_mode : 1; /* [6] for xts mode */ - uint32_t aes_region_lock : 1; /* [7] rsvd */ - uint32_t no_segment : 1; /* [8] no segment info */ - uint32_t boot2_enable : 1; /* [9] boot2 enable */ - uint32_t boot2_rollback : 1; /* [10] boot2 rollback */ - uint32_t cpu_master_id : 4; /* [14: 11] master id */ - uint32_t notload_in_bootrom : 1; /* [15] notload in bootrom */ - uint32_t crc_ignore : 1; /* [16] ignore crc */ - uint32_t hash_ignore : 1; /* [17] hash ignore */ - uint32_t power_on_mm : 1; /* [18] power on mm */ - uint32_t em_sel : 3; /* [21: 19] em_sel */ - uint32_t cmds_en : 1; /* [22] command spliter enable */ - uint32_t cmds_wrap_mode : 2; /* [24: 23] cmds wrap mode */ - uint32_t cmds_wrap_len : 4; /* [28: 25] cmds wrap len */ - uint32_t icache_invalid : 1; /* [29] icache invalid */ - uint32_t dcache_invalid : 1; /* [30] dcache invalid */ - uint32_t fpga_halt_release : 1; /* [31] FPGA halt release function */ - - uint32_t group_image_offset; /* flash controller offset */ - uint32_t aes_region_len; /* aes region length */ - - uint32_t img_len_cnt; /* image length or segment count */ - uint32_t hash[8]; /* hash of the image */ -}; - -struct __attribute__((packed, aligned(4))) hal_cpu_cfg_t { - uint8_t config_enable; /* coinfig this cpu */ - uint8_t halt_cpu; /* halt this cpu */ - uint8_t cache_enable : 1; /* cache setting */ - uint8_t cache_wa : 1; /* cache setting */ - uint8_t cache_wb : 1; /* cache setting */ - uint8_t cache_wt : 1; /* cache setting */ - uint8_t cache_way_dis : 4; /* cache setting */ - uint8_t rsvd; - - uint32_t cache_range_h; /* cache range high */ - uint32_t cache_range_l; /* cache range low */ - - uint32_t image_address_offset; /* image address on flash */ /*image_address_offset*/ - uint32_t boot_entry; /* entry point of the m0 image */ - uint32_t msp_val; /* msp value */ -}; - -struct __attribute__((packed, aligned(4))) hal_patch_cfg_t { - uint32_t addr; - uint32_t value; -}; - -struct __attribute__((packed, aligned(4))) hal_bootheader_t { - uint32_t magiccode; - uint32_t rivison; - - struct hal_flash_config flashCfg; - hal_pll_config clkCfg; - - struct hal_basic_cfg_t basic_cfg; - - struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; - - uint32_t boot2_pt_table_0; /* address of partition table 0 */ - uint32_t boot2_pt_table_1; /* address of partition table 1 */ - - uint32_t flashCfgTableAddr; /* address of flashcfg table list */ - uint32_t flashCfgTableLen; /* flashcfg table list len */ - - struct hal_patch_cfg_t patch_on_read[4]; /* do patch when read flash */ - struct hal_patch_cfg_t patch_on_jump[4]; /* do patch when jump */ - - uint32_t rsvd[5]; - - uint32_t crc32; -}; - -typedef struct -{ - uint8_t img_valid; - uint8_t pk_src; - uint8_t rsvd[2]; - - struct hal_basic_cfg_t basic_cfg; - - struct hal_cpu_cfg_t cpu_cfg[HAL_BOOT2_CPU_MAX]; - - uint8_t aes_iv[16 + 4]; //iv in boot header - - uint8_t eckye_x[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header - uint8_t eckey_y[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header - uint8_t eckey_x2[HAL_BOOT2_ECC_KEYXSIZE]; //ec key in boot header - uint8_t eckey_y2[HAL_BOOT2_ECC_KEYYSIZE]; //ec key in boot header - - uint8_t signature[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header - uint8_t signature2[HAL_BOOT2_SIGN_MAXSIZE]; //signature in boot header - -} boot2_image_config; - -extern boot2_efuse_hw_config g_efuse_cfg; -extern uint8_t g_ps_mode; -extern uint32_t g_user_hash_ignored; -extern struct device *dev_check_hash; - -void hal_boot2_init_clock(void); -uint32_t hal_boot2_custom(void *custom_param); -void hal_boot2_reset_sec_eng(void); -void hal_boot2_sw_system_reset(void); -void hal_boot2_set_psmode_status(uint32_t flag); -uint32_t hal_boot2_get_psmode_status(void); -uint32_t hal_boot2_get_user_fw(void); -void hal_boot2_clr_user_fw(void); -void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg); -int32_t hal_boot2_get_clk_cfg(hal_pll_config *cfg); -void hal_boot2_sboot_finish(void); -void hal_boot2_uart_gpio_init(void); -void hal_boot2_debug_uart_gpio_init(void); -void hal_boot2_debug_uart_gpio_deinit(void); -int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data); -void hal_boot2_clean_cache(void); -BL_Err_Type hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg); -void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt); -void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash); -void hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr); -uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr); -uint32_t hal_boot2_get_grp_count(void); -uint32_t hal_boot2_get_cpu_count(void); -uint32_t hal_boot2_get_feature_flag(void); -uint32_t hal_boot2_get_bootheader_offset(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_clock.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_clock.h deleted file mode 100644 index cb4698a215..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_clock.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file hal_clock.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_CLOCK__H__ -#define __HAL_CLOCK__H__ - -#include "hal_common.h" - -/*XTAL_TYPE*/ -#define XTAL_NONE 0 -#define EXTERNAL_XTAL_24M 1 -#define EXTERNAL_XTAL_32M 2 -#define EXTERNAL_XTAL_38P4M 3 -#define EXTERNAL_XTAL_40M 4 -#define EXTERNAL_XTAL_26M 5 -#define INTERNAL_RC_32M 6 - -/*CLOCK_32K_XTAL*/ -#define EXTERNAL_XTAL_32K 0 -#define INTERNAL_RC_32K 1 - -#define ROOT_CLOCK_SOURCE_32K_CLK 0 -#define ROOT_CLOCK_SOURCE_XCLK 1 -#define ROOT_CLOCK_SOURCE_WIFIPLL_32M 2 -#define ROOT_CLOCK_SOURCE_WIFIPLL_48M 3 -#define ROOT_CLOCK_SOURCE_WIFIPLL_80M 4 -#define ROOT_CLOCK_SOURCE_WIFIPLL_96M 5 -#define ROOT_CLOCK_SOURCE_WIFIPLL_160M 6 -#define ROOT_CLOCK_SOURCE_WIFIPLL_240M 7 -#define ROOT_CLOCK_SOURCE_WIFIPLL_320M 8 -#define ROOT_CLOCK_SOURCE_CPUPLL_80M 9 -#define ROOT_CLOCK_SOURCE_CPUPLL_100M 10 -#define ROOT_CLOCK_SOURCE_CPUPLL_160M 11 -#define ROOT_CLOCK_SOURCE_CPUPLL_200M 12 -#define ROOT_CLOCK_SOURCE_CPUPLL_400M 13 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV1 14 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV2 15 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV2P5 16 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV5 17 -#define ROOT_CLOCK_SOURCE_AUPLL_DIV6 18 -#define ROOT_CLOCK_SOURCE_AUPLL_CLK 19 - -#define BSP_CLOCK_SOURCE_FCLK 20 -#define BSP_CLOCK_SOURCE_BCLK 21 - -#define BSP_CLOCK_SOURCE_MUXPLL_80M ROOT_CLOCK_SOURCE_WIFIPLL_80M -#define BSP_CLOCK_SOURCE_MUXPLL_160M ROOT_CLOCK_SOURCE_WIFIPLL_160M - -void system_clock_init(void); -void peripheral_clock_init(void); -void system_mtimer_clock_init(void); -void system_mtimer_clock_reinit(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_common.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_common.h deleted file mode 100644 index 4fa4f5667d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_common.h +++ /dev/null @@ -1,49 +0,0 @@ -/** - * @file hal_common.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_COMMON__H__ -#define __HAL_COMMON__H__ - -#include "bl808_common.h" - -typedef enum { - HAL_REBOOT_AS_BOOTPIN, /*!< reboot as bootpin level */ - HAL_REBOOT_FROM_INTERFACE, /*!< reboot from interface, download mode */ - HAL_REBOOT_FROM_MEDIA, /*!< reboot from media, running mode */ - HAL_REBOOT_MAX /*!< reboot max value */ -} hal_reboot_cfg_t; - -void cpu_global_irq_enable(void); -void cpu_global_irq_disable(void); -void hal_por_reset(void); -void hal_system_reset(void); -void hal_cpu_reset(void); -void hal_reboot_config(hal_reboot_cfg_t rbot); -void hal_get_chip_id(uint8_t chip_id[8]); -void hal_dcache_clean_all(void); -void hal_dcache_invalid_all(void); -void hal_dcache_clean_invalid_all(void); -void hal_dcache_clean_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_invalidate_byaddr(uintptr_t addr, uint32_t len); -void hal_dcache_clean_invalidate_byaddr(uintptr_t addr, uint32_t len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dac.h deleted file mode 100644 index 9a6a152451..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dac.h +++ /dev/null @@ -1,72 +0,0 @@ -/** - * @file hal_dac.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_DAC__H__ -#define __HAL_DAC__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -enum dac_index_type { -#ifdef BSP_USING_DAC0 - DAC0_INDEX, -#endif - DAC_MAX_INDEX -}; - -#define DAC_CHANNEL_0 (1 << 0) -#define DAC_CHANNEL_1 (1 << 1) -#define DAC_CHANNEL_ALL (DAC_CHANNEL_0 | DAC_CHANNEL_1) - -/* default a_rng and b_rng is 0x03*/ -/*output Voltage = (1.8V-0.2V) * digital_val/1024 + 0.2V */ -#define DAC_VREF_INTERNAL 0 /*0.2V~1.8V*/ -/*output Voltage = (0.9vref-0.1vref) * digital_val/1024 + 0.1vref */ -#define DAC_VREF_EXTERNAL 1 /*0.1vref~0.9vref,using gpio7 for GPIO_FUN_ADC*/ - -enum dac_sample_frequence { - DAC_SAMPLE_FREQ_8KHZ, - DAC_SAMPLE_FREQ_16KHZ, - DAC_SAMPLE_FREQ_44P1KHZ, - DAC_SAMPLE_FREQ_500KHZ, -}; - -typedef struct dac_device { - struct device parent; - enum dac_sample_frequence sample_freq; - uint8_t channels; - uint8_t vref; - void *tx_dma; -} dac_device_t; - -#define DAC_DEV(dev) ((adc_device_t *)dev) - -int dac_register(enum dac_index_type index, const char *name); -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dma.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dma.h deleted file mode 100644 index 6af2c755f4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dma.h +++ /dev/null @@ -1,262 +0,0 @@ -/** - * @file hal_dma.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_DMA__H__ -#define __HAL_DMA__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_DMA_CHANNEL_GET_STATUS 0x10 -#define DEVICE_CTRL_DMA_CHANNEL_START 0x11 -#define DEVICE_CTRL_DMA_CHANNEL_STOP 0x12 -#define DEVICE_CTRL_DMA_CHANNEL_UPDATE 0x13 -#define DEVICE_CTRL_DMA_CONFIG_SI 0x14 -#define DEVICE_CTRL_DMA_CONFIG_DI 0x15 - -enum dma_index_type { -#ifdef BSP_USING_DMA0_CH0 - DMA0_CH0_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH1 - DMA0_CH1_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH2 - DMA0_CH2_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH3 - DMA0_CH3_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH4 - DMA0_CH4_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH5 - DMA0_CH5_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH6 - DMA0_CH6_INDEX, -#endif -#ifdef BSP_USING_DMA0_CH7 - DMA0_CH7_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH0 - DMA1_CH0_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH1 - DMA1_CH1_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH2 - DMA1_CH2_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH3 - DMA1_CH3_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH4 - DMA1_CH4_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH5 - DMA1_CH5_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH6 - DMA1_CH6_INDEX, -#endif -#ifdef BSP_USING_DMA1_CH7 - DMA1_CH7_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH0 - DMA2_CH0_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH1 - DMA2_CH1_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH2 - DMA2_CH2_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH3 - DMA2_CH3_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH4 - DMA2_CH4_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH5 - DMA2_CH5_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH6 - DMA2_CH6_INDEX, -#endif -#ifdef BSP_USING_DMA2_CH7 - DMA2_CH7_INDEX, -#endif - DMA_MAX_INDEX -}; - -#define dma_channel_start(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_START, NULL) -#define dma_channel_stop(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_STOP, NULL) -#define dma_channel_update(dev, list) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_UPDATE, list) -#define dma_channel_check_busy(dev) device_control(dev, DEVICE_CTRL_DMA_CHANNEL_GET_STATUS, NULL) - -#define DMA_LLI_ONCE_MODE 0 -#define DMA_LLI_CYCLE_MODE 1 - -#define DMA_ADDR_INCREMENT_DISABLE 0 /*!< Addr increment mode disable */ -#define DMA_ADDR_INCREMENT_ENABLE 1 /*!< Addr increment mode enable */ - -#define DMA_TRANSFER_WIDTH_8BIT 0 -#define DMA_TRANSFER_WIDTH_16BIT 1 -#define DMA_TRANSFER_WIDTH_32BIT 2 - -#define DMA_BURST_INCR1 0 -#define DMA_BURST_INCR4 1 -#define DMA_BURST_INCR8 2 -#define DMA_BURST_INCR16 3 - -#define DMA_ADDR_UART0_TDR (0x2000A000 + 0x88) -#define DMA_ADDR_UART0_RDR (0x2000A000 + 0x8C) -#define DMA_ADDR_UART1_TDR (0x2000A100 + 0x88) -#define DMA_ADDR_UART1_RDR (0x2000A100 + 0x8C) -#define DMA_ADDR_UART2_TDR (0x2000AA00 + 0x88) -#define DMA_ADDR_UART2_RDR (0x2000AA00 + 0x8C) -#define DMA_ADDR_UART3_TDR (0x30002000 + 0x88) -#define DMA_ADDR_UART3_RDR (0x30002000 + 0x8C) -#define DMA_ADDR_UART4_TDR (0x3000E000 + 0x88) -#define DMA_ADDR_UART4_RDR (0x3000E000 + 0x8C) -#define DMA_ADDR_I2C0_TDR (0x2000a300 + 0x88) -#define DMA_ADDR_I2C0_RDR (0x2000a300 + 0x8C) -#define DMA_ADDR_I2C1_TDR (0x2000a900 + 0x88) -#define DMA_ADDR_I2C1_RDR (0x2000a900 + 0x8C) -#define DMA_ADDR_I2C2_TDR (0x30003000 + 0x88) -#define DMA_ADDR_I2C2_RDR (0x30003000 + 0x8C) -#define DMA_ADDR_I2C3_TDR (0x30004000 + 0x88) -#define DMA_ADDR_I2C3_RDR (0x30004000 + 0x8C) -#define DMA_ADDR_SPI0_TDR (0x2000a200 + 0x88) -#define DMA_ADDR_SPI0_RDR (0x2000a200 + 0x8C) -#define DMA_ADDR_SPI1_TDR (0x30008000 + 0x88) -#define DMA_ADDR_SPI1_RDR (0x30008000 + 0x8C) -#define DMA_ADDR_I2S_TDR (0x2000AB00 + 0x88) -#define DMA_ADDR_I2S_RDR (0x2000AB00 + 0x8C) -#define DMA_ADDR_AUDIO_TDR (0x20055000 + 0x94) -#define DMA_ADDR_AUDIO_RDR (0x20055000 + 0x88) -#define DMA_ADDR_ADC_RDR (0x20002000 + 0x04) -#define DMA_ADDR_DAC_TDR (0x20002000 + 0x48) -#define DMA_ADDR_DSI_RDR (0x3001a100 + 0x6C) -#define DMA_ADDR_DSI_TDR (0x3001a100 + 0x68) -#define DMA_ADDR_DBI_TDR (0x3001b000 + 0x88) - -#define DMA_REQUEST_NONE 0x00000000 /*!< DMA request peripheral:None */ -#define DMA_REQUEST_UART0_RX 0x00000000 /*!< DMA request peripheral:UART0 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART0_TX 0x00000001 /*!< DMA request peripheral:UART0 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART1_RX 0x00000002 /*!< DMA request peripheral:UART1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART1_TX 0x00000003 /*!< DMA request peripheral:UART1 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART2_RX 0x00000004 /*!< DMA request peripheral:UART2 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_UART2_TX 0x00000005 /*!< DMA request peripheral:UART2 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C0_RX 0x00000006 /*!< DMA request peripheral:I2C0 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C0_TX 0x00000007 /*!< DMA request peripheral:I2C0 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_SPI0_RX 0x0000000A /*!< DMA request peripheral:SPI0 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_SPI0_TX 0x0000000B /*!< DMA request peripheral:SPI1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_AUDIO_RX 0x0000000C /*!< DMA request peripheral:SPI1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_AUDIO_TX 0x0000000D /*!< DMA request peripheral:SPI1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C1_RX 0x0000000E /*!< DMA request peripheral:I2C1 RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2C1_TX 0x0000000F /*!< DMA request peripheral:I2C1 TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2S_RX 0x00000010 /*!< DMA request peripheral:I2S RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_I2S_TX 0x00000011 /*!< DMA request peripheral:I2S TX, DMA0 and DMA1 support */ -#define DMA_REQUEST_PDM_RX 0x00000012 /*!< DMA request peripheral:PDM RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_ADC0 0x00000016 /*!< DMA request peripheral:GPADC RX, DMA0 and DMA1 support */ -#define DMA_REQUEST_DAC0 0x00000017 /*!< DMA request peripheral:GPADC TX, DMA0 and DMA1 support */ - -#define DMA_REQUEST_UART3_RX 0x0000000 /*!< DMA request peripheral:UART3 RX, only DMA2 support */ -#define DMA_REQUEST_UART3_TX 0x0000001 /*!< DMA request peripheral:UART3 TX, only DMA2 support */ -#define DMA_REQUEST_SPI1_RX 0x0000002 /*!< DMA request peripheral:SPI1 RX, only DMA2 support */ -#define DMA_REQUEST_SPI1_TX 0x0000003 /*!< DMA request peripheral:SPI1 TX, only DMA2 support */ -#define DMA_REQUEST_UART4_RX 0x0000004 /*!< DMA request peripheral:UART4 RX, only DMA2 support */ -#define DMA_REQUEST_UART4_TX 0x0000005 /*!< DMA request peripheral:UART4 TX, only DMA2 support */ -#define DMA_REQUEST_I2C2_RX 0x0000006 /*!< DMA request peripheral:I2C2 RX, only DMA2 support */ -#define DMA_REQUEST_I2C2_TX 0x0000007 /*!< DMA request peripheral:I2C2 TX, only DMA2 support */ -#define DMA_REQUEST_I2C3_RX 0x0000008 /*!< DMA request peripheral:I2C3 RX, only DMA2 support */ -#define DMA_REQUEST_I2C3_TX 0x0000009 /*!< DMA request peripheral:I2C3 TX, only DMA2 support */ -#define DMA_REQUEST_DSI_RX 0x000000A /*!< DMA request peripheral:DSI RX, only DMA2 support */ -#define DMA_REQUEST_DSI_TX 0x000000B /*!< DMA request peripheral:DSI TX, only DMA2 support */ -#define DMA_REQUEST_DBI_TX 0x0000016 /*!< DMA request peripheral:DBI TX, only DMA2 support */ - -/** - * @brief DMA transfer direction type definition - */ -typedef enum { - DMA_MEMORY_TO_MEMORY = 0, /*!< DMA transfer type:memory to memory */ - DMA_MEMORY_TO_PERIPH, /*!< DMA transfer type:memory to peripheral */ - DMA_PERIPH_TO_MEMORY, /*!< DMA transfer type:peripheral to memory */ - DMA_PERIPH_TO_PERIPH, /*!< DMA transfer type:peripheral to peripheral */ -} dma_transfer_dir_type; - -typedef union { - struct - { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 2; /* [24:23], r/w, 0x0 */ - uint32_t SLargerD : 1; /* [ 25], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } bits; - uint32_t WORD; -} dma_control_data_t; - -typedef struct -{ - uint32_t src_addr; - uint32_t dst_addr; - uint32_t nextlli; - dma_control_data_t cfg; -} dma_lli_ctrl_t; - -typedef struct dma_device { - struct device parent; - uint8_t id; - uint8_t ch; - uint8_t transfer_mode; - uint8_t direction; - uint32_t src_req; - uint32_t dst_req; - uint8_t src_addr_inc; - uint8_t dst_addr_inc; - uint8_t src_burst_size; - uint8_t dst_burst_size; - uint8_t src_width; - uint8_t dst_width; - dma_lli_ctrl_t *lli_cfg;/* private param*/ -} dma_device_t; - -#define DMA_DEV(dev) ((dma_device_t *)dev) - -int dma_register(enum dma_index_type index, const char *name); -int dma_allocate_register(const char *name); -int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dsi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dsi.h deleted file mode 100644 index 0b196b8986..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_dsi.h +++ /dev/null @@ -1,574 +0,0 @@ -/** - * @file hal_dsi.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_DSI__H__ -#define __HAL_DSI__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DSI_DEV_NAME_SIZE 20 -#define u8 uint8_t -#define u16 uint16_t -#define u32 uint32_t -#define __be16 uint16_t -/* VESA Display Stream Compression DSC 1.2 constants */ -#define DSC_NUM_BUF_RANGES 15 - -enum mipi_dsi_index_type { - DSI0_INDEX, - DSI_MAX_INDEX -}; - -struct mipi_dsi_host; -struct mipi_dsi_device; -struct drm_dsc_picture_parameter_set; - -/** - * struct drm_dsc_picture_parameter_set - Represents 128 bytes of - * Picture Parameter Set - * - * The VESA DSC standard defines picture parameter set (PPS) which display - * stream compression encoders must communicate to decoders. - * The PPS is encapsulated in 128 bytes (PPS 0 through PPS 127). The fields in - * this structure are as per Table 4.1 in Vesa DSC specification v1.1/v1.2. - * The PPS fields that span over more than a byte should be stored in Big Endian - * format. - */ -struct drm_dsc_picture_parameter_set { - /** - * @dsc_version: - * PPS0[3:0] - dsc_version_minor: Contains Minor version of DSC - * PPS0[7:4] - dsc_version_major: Contains major version of DSC - */ - u8 dsc_version; - /** - * @pps_identifier: - * PPS1[7:0] - Application specific identifier that can be - * used to differentiate between different PPS tables. - */ - u8 pps_identifier; - /** - * @pps_reserved: - * PPS2[7:0]- RESERVED Byte - */ - u8 pps_reserved; - /** - * @pps_3: - * PPS3[3:0] - linebuf_depth: Contains linebuffer bit depth used to - * generate the bitstream. (0x0 - 16 bits for DSC 1.2, 0x8 - 8 bits, - * 0xA - 10 bits, 0xB - 11 bits, 0xC - 12 bits, 0xD - 13 bits, - * 0xE - 14 bits for DSC1.2, 0xF - 14 bits for DSC 1.2. - * PPS3[7:4] - bits_per_component: Bits per component for the original - * pixels of the encoded picture. - * 0x0 = 16bpc (allowed only when dsc_version_minor = 0x2) - * 0x8 = 8bpc, 0xA = 10bpc, 0xC = 12bpc, 0xE = 14bpc (also - * allowed only when dsc_minor_version = 0x2) - */ - u8 pps_3; - /** - * @pps_4: - * PPS4[1:0] -These are the most significant 2 bits of - * compressed BPP bits_per_pixel[9:0] syntax element. - * PPS4[2] - vbr_enable: 0 = VBR disabled, 1 = VBR enabled - * PPS4[3] - simple_422: Indicates if decoder drops samples to - * reconstruct the 4:2:2 picture. - * PPS4[4] - Convert_rgb: Indicates if DSC color space conversion is - * active. - * PPS4[5] - blobk_pred_enable: Indicates if BP is used to code any - * groups in picture - * PPS4[7:6] - Reseved bits - */ - u8 pps_4; - /** - * @bits_per_pixel_low: - * PPS5[7:0] - This indicates the lower significant 8 bits of - * the compressed BPP bits_per_pixel[9:0] element. - */ - u8 bits_per_pixel_low; - /** - * @pic_height: - * PPS6[7:0], PPS7[7:0] -pic_height: Specifies the number of pixel rows - * within the raster. - */ - __be16 pic_height; - /** - * @pic_width: - * PPS8[7:0], PPS9[7:0] - pic_width: Number of pixel columns within - * the raster. - */ - __be16 pic_width; - /** - * @slice_height: - * PPS10[7:0], PPS11[7:0] - Slice height in units of pixels. - */ - __be16 slice_height; - /** - * @slice_width: - * PPS12[7:0], PPS13[7:0] - Slice width in terms of pixels. - */ - __be16 slice_width; - /** - * @chunk_size: - * PPS14[7:0], PPS15[7:0] - Size in units of bytes of the chunks - * that are used for slice multiplexing. - */ - __be16 chunk_size; - /** - * @initial_xmit_delay_high: - * PPS16[1:0] - Most Significant two bits of initial transmission delay. - * It specifies the number of pixel times that the encoder waits before - * transmitting data from its rate buffer. - * PPS16[7:2] - Reserved - */ - u8 initial_xmit_delay_high; - /** - * @initial_xmit_delay_low: - * PPS17[7:0] - Least significant 8 bits of initial transmission delay. - */ - u8 initial_xmit_delay_low; - /** - * @initial_dec_delay: - * - * PPS18[7:0], PPS19[7:0] - Initial decoding delay which is the number - * of pixel times that the decoder accumulates data in its rate buffer - * before starting to decode and output pixels. - */ - __be16 initial_dec_delay; - /** - * @pps20_reserved: - * - * PPS20[7:0] - Reserved - */ - u8 pps20_reserved; - /** - * @initial_scale_value: - * PPS21[5:0] - Initial rcXformScale factor used at beginning - * of a slice. - * PPS21[7:6] - Reserved - */ - u8 initial_scale_value; - /** - * @scale_increment_interval: - * PPS22[7:0], PPS23[7:0] - Number of group times between incrementing - * the rcXformScale factor at end of a slice. - */ - __be16 scale_increment_interval; - /** - * @scale_decrement_interval_high: - * PPS24[3:0] - Higher 4 bits indicating number of group times between - * decrementing the rcXformScale factor at beginning of a slice. - * PPS24[7:4] - Reserved - */ - u8 scale_decrement_interval_high; - /** - * @scale_decrement_interval_low: - * PPS25[7:0] - Lower 8 bits of scale decrement interval - */ - u8 scale_decrement_interval_low; - /** - * @pps26_reserved: - * PPS26[7:0] - */ - u8 pps26_reserved; - /** - * @first_line_bpg_offset: - * PPS27[4:0] - Number of additional bits that are allocated - * for each group on first line of a slice. - * PPS27[7:5] - Reserved - */ - u8 first_line_bpg_offset; - /** - * @nfl_bpg_offset: - * PPS28[7:0], PPS29[7:0] - Number of bits including frac bits - * deallocated for each group for groups after the first line of slice. - */ - __be16 nfl_bpg_offset; - /** - * @slice_bpg_offset: - * PPS30, PPS31[7:0] - Number of bits that are deallocated for each - * group to enforce the slice constraint. - */ - __be16 slice_bpg_offset; - /** - * @initial_offset: - * PPS32,33[7:0] - Initial value for rcXformOffset - */ - __be16 initial_offset; - /** - * @final_offset: - * PPS34,35[7:0] - Maximum end-of-slice value for rcXformOffset - */ - __be16 final_offset; - /** - * @flatness_min_qp: - * PPS36[4:0] - Minimum QP at which flatness is signaled and - * flatness QP adjustment is made. - * PPS36[7:5] - Reserved - */ - u8 flatness_min_qp; - /** - * @flatness_max_qp: - * PPS37[4:0] - Max QP at which flatness is signalled and - * the flatness adjustment is made. - * PPS37[7:5] - Reserved - */ - u8 flatness_max_qp; - /** - * @rc_model_size: - * PPS38,39[7:0] - Number of bits within RC Model. - */ - __be16 rc_model_size; - /** - * @rc_edge_factor: - * PPS40[3:0] - Ratio of current activity vs, previous - * activity to determine presence of edge. - * PPS40[7:4] - Reserved - */ - u8 rc_edge_factor; - /** - * @rc_quant_incr_limit0: - * PPS41[4:0] - QP threshold used in short term RC - * PPS41[7:5] - Reserved - */ - u8 rc_quant_incr_limit0; - /** - * @rc_quant_incr_limit1: - * PPS42[4:0] - QP threshold used in short term RC - * PPS42[7:5] - Reserved - */ - u8 rc_quant_incr_limit1; - /** - * @rc_tgt_offset: - * PPS43[3:0] - Lower end of the variability range around the target - * bits per group that is allowed by short term RC. - * PPS43[7:4]- Upper end of the variability range around the target - * bits per group that i allowed by short term rc. - */ - u8 rc_tgt_offset; - /** - * @rc_buf_thresh: - * PPS44[7:0] - PPS57[7:0] - Specifies the thresholds in RC model for - * the 15 ranges defined by 14 thresholds. - */ - u8 rc_buf_thresh[DSC_NUM_BUF_RANGES - 1]; - /** - * @rc_range_parameters: - * PPS58[7:0] - PPS87[7:0] - * Parameters that correspond to each of the 15 ranges. - */ - __be16 rc_range_parameters[DSC_NUM_BUF_RANGES]; - /** - * @native_422_420: - * PPS88[0] - 0 = Native 4:2:2 not used - * 1 = Native 4:2:2 used - * PPS88[1] - 0 = Native 4:2:0 not use - * 1 = Native 4:2:0 used - * PPS88[7:2] - Reserved 6 bits - */ - u8 native_422_420; - /** - * @second_line_bpg_offset: - * PPS89[4:0] - Additional bits/group budget for the - * second line of a slice in Native 4:2:0 mode. - * Set to 0 if DSC minor version is 1 or native420 is 0. - * PPS89[7:5] - Reserved - */ - u8 second_line_bpg_offset; - /** - * @nsl_bpg_offset: - * PPS90[7:0], PPS91[7:0] - Number of bits that are deallocated - * for each group that is not in the second line of a slice. - */ - __be16 nsl_bpg_offset; - /** - * @second_line_offset_adj: - * PPS92[7:0], PPS93[7:0] - Used as offset adjustment for the second - * line in Native 4:2:0 mode. - */ - __be16 second_line_offset_adj; - /** - * @pps_long_94_reserved: - * PPS 94, 95, 96, 97 - Reserved - */ - u32 pps_long_94_reserved; - /** - * @pps_long_98_reserved: - * PPS 98, 99, 100, 101 - Reserved - */ - u32 pps_long_98_reserved; - /** - * @pps_long_102_reserved: - * PPS 102, 103, 104, 105 - Reserved - */ - u32 pps_long_102_reserved; - /** - * @pps_long_106_reserved: - * PPS 106, 107, 108, 109 - reserved - */ - u32 pps_long_106_reserved; - /** - * @pps_long_110_reserved: - * PPS 110, 111, 112, 113 - reserved - */ - u32 pps_long_110_reserved; - /** - * @pps_long_114_reserved: - * PPS 114 - 117 - reserved - */ - u32 pps_long_114_reserved; - /** - * @pps_long_118_reserved: - * PPS 118 - 121 - reserved - */ - u32 pps_long_118_reserved; - /** - * @pps_long_122_reserved: - * PPS 122- 125 - reserved - */ - u32 pps_long_122_reserved; - /** - * @pps_short_126_reserved: - * PPS 126, 127 - reserved - */ - __be16 pps_short_126_reserved; -} __attribute__((packed)); - -/* request ACK from peripheral */ -#define MIPI_DSI_MSG_REQ_ACK BIT(0) -/* use Low Power Mode to transmit message */ -#define MIPI_DSI_MSG_USE_LPM BIT(1) - -/** - * struct mipi_dsi_msg - read/write DSI buffer - * @channel: virtual channel id - * @type: payload data type - * @flags: flags controlling this message transmission - * @tx_len: length of @tx_buf - * @tx_buf: data to be written - * @rx_len: length of @rx_buf - * @rx_buf: data to be read, or NULL - */ -struct mipi_dsi_msg { - u8 channel; - u8 type; - u16 flags; - - size_t tx_len; - const void *tx_buf; - - size_t rx_len; - void *rx_buf; -}; - -bool mipi_dsi_packet_format_is_short(u8 type); -bool mipi_dsi_packet_format_is_long(u8 type); - -/** - * struct mipi_dsi_packet - represents a MIPI DSI packet in protocol format - * @size: size (in bytes) of the packet - * @header: the four bytes that make up the header (Data ID, Word Count or - * Packet Data, and ECC) - * @payload_length: number of bytes in the payload - * @payload: a pointer to a buffer containing the payload, if any - */ -struct mipi_dsi_packet { - size_t size; - u8 header[4]; - size_t payload_length; - const u8 *payload; -}; - -int mipi_dsi_create_packet(struct mipi_dsi_packet *packet, - const struct mipi_dsi_msg *msg); -/** - * struct mipi_dsi_host_ops - DSI bus operations - * @attach: attach DSI device to DSI host - * @detach: detach DSI device from DSI host - * @transfer: transmit a DSI packet - * - * DSI packets transmitted by .transfer() are passed in as mipi_dsi_msg - * structures. This structure contains information about the type of packet - * being transmitted as well as the transmit and receive buffers. When an - * error is encountered during transmission, this function will return a - * negative error code. On success it shall return the number of bytes - * transmitted for write packets or the number of bytes received for read - * packets. - * - * Note that typically DSI packet transmission is atomic, so the .transfer() - * function will seldomly return anything other than the number of bytes - * contained in the transmit buffer on success. - */ -struct mipi_dsi_host_ops { - int (*attach)(struct mipi_dsi_host *host, - const struct mipi_dsi_device *dsi); - int (*detach)(struct mipi_dsi_host *host, - const struct mipi_dsi_device *dsi); - size_t (*transfer)(struct mipi_dsi_host *host, - const struct mipi_dsi_msg *msg); -}; - -/** - * struct mipi_dsi_host - DSI host device - * @dev: driver model device node for this DSI host - * @ops: DSI host operations - * @list: list management - */ -struct mipi_dsi_host { - //struct device *dev; - const struct mipi_dsi_host_ops *ops; - //struct list_head list; -}; - -/* DSI mode flags */ - -/* video mode */ -#define MIPI_DSI_MODE_VIDEO BIT(0) -/* video burst mode */ -#define MIPI_DSI_MODE_VIDEO_BURST BIT(1) -/* video pulse mode */ -#define MIPI_DSI_MODE_VIDEO_SYNC_PULSE BIT(2) -/* enable auto vertical count mode */ -#define MIPI_DSI_MODE_VIDEO_AUTO_VERT BIT(3) -/* enable hsync-end packets in vsync-pulse and v-porch area */ -#define MIPI_DSI_MODE_VIDEO_HSE BIT(4) -/* disable hfront-porch area */ -#define MIPI_DSI_MODE_VIDEO_HFP BIT(5) -/* disable hback-porch area */ -#define MIPI_DSI_MODE_VIDEO_HBP BIT(6) -/* disable hsync-active area */ -#define MIPI_DSI_MODE_VIDEO_HSA BIT(7) -/* flush display FIFO on vsync pulse */ -#define MIPI_DSI_MODE_VSYNC_FLUSH BIT(8) -/* disable EoT packets in HS mode */ -#define MIPI_DSI_MODE_EOT_PACKET BIT(9) -/* device supports non-continuous clock behavior (DSI spec 5.6.1) */ -#define MIPI_DSI_CLOCK_NON_CONTINUOUS BIT(10) -/* transmit data in low power */ -#define MIPI_DSI_MODE_LPM BIT(11) - -enum mipi_dsi_pixel_format { - MIPI_DSI_DATA_FMT_YUV422 = 0x2C, /*!< DSI data format:YUV 422 8bits */ - MIPI_DSI_DATA_FMT_RGB565 = 0x0E, /*!< DSI data format:RGB565 */ - MIPI_DSI_DATA_FMT_RGB666 = 0x2E, /*!< DSI data format:RGB666 */ - MIPI_DSI_DATA_FMT_RGB888 = 0x3E, /*!< DSI data format:RGB888 */ -}; - -/** - * struct mipi_dsi_device_info - template for creating a mipi_dsi_device - * @type: DSI peripheral chip type - * @channel: DSI virtual channel assigned to peripheral - * @node: pointer to OF device node or NULL - * - * This is populated and passed to mipi_dsi_device_new to create a new - * DSI device - */ -struct mipi_dsi_device_info { - char type[DSI_DEV_NAME_SIZE]; - u32 channel; - struct device_node *node; -}; - -/** - * struct mipi_dsi_device - DSI peripheral device - * @host: DSI host for this peripheral - * @dev: driver model device node for this peripheral - * @name: DSI peripheral chip type - * @channel: virtual channel assigned to the peripheral - * @format: pixel format for video mode - * @lanes: number of active data lanes - * @mode_flags: DSI operation mode related flags - * @hs_rate: maximum lane frequency for high speed mode in hertz, this should - * be set to the real limits of the hardware, zero is only accepted for - * legacy drivers - * @lp_rate: maximum lane frequency for low power mode in hertz, this should - * be set to the real limits of the hardware, zero is only accepted for - * legacy drivers - */ -typedef struct mipi_dsi_device { - struct device dev; - struct mipi_dsi_host *host; - - char name[DSI_DEV_NAME_SIZE]; - unsigned int channel; - unsigned int lanes; - enum mipi_dsi_pixel_format format; - unsigned long mode_flags; - unsigned long hs_rate; - unsigned long lp_rate; -} mipi_dsi_device_t; - -/** - * enum mipi_dsi_dcs_tear_mode - Tearing Effect Output Line mode - * @MIPI_DSI_DCS_TEAR_MODE_VBLANK: the TE output line consists of V-Blanking - * information only - * @MIPI_DSI_DCS_TEAR_MODE_VHBLANK : the TE output line consists of both - * V-Blanking and H-Blanking information - */ -enum mipi_dsi_dcs_tear_mode { - MIPI_DSI_DCS_TEAR_MODE_VBLANK, - MIPI_DSI_DCS_TEAR_MODE_VHBLANK, -}; - -int mipi_dsi_controller_init(const struct mipi_dsi_device *dsi); -int mipi_dsi_shutdown_peripheral(const struct mipi_dsi_device *dsi); -int mipi_dsi_turn_on_peripheral(const struct mipi_dsi_device *dsi); -int mipi_dsi_set_maximum_return_packet_size(const struct mipi_dsi_device *dsi, - u16 value); -int mipi_dsi_compression_mode(const struct mipi_dsi_device *dsi, bool enable); -int mipi_dsi_picture_parameter_set(const struct mipi_dsi_device *dsi, - const struct drm_dsc_picture_parameter_set *pps); - -int mipi_dsi_generic_write(const struct mipi_dsi_device *dsi, const void *payload, - size_t size); -int mipi_dsi_generic_read(const struct mipi_dsi_device *dsi, const void *params, - size_t num_params, void *data, size_t size); -int mipi_dsi_dcs_write_buffer(const struct mipi_dsi_device *dsi, - const void *data, size_t len); -int mipi_dsi_dcs_write(const struct mipi_dsi_device *dsi, u8 cmd, - const void *data, size_t len); -int mipi_dsi_dcs_read(const struct mipi_dsi_device *dsi, u8 cmd, void *data, - size_t len); -int mipi_dsi_dcs_nop(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_soft_reset(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_get_power_mode(const struct mipi_dsi_device *dsi, u8 *mode); -int mipi_dsi_dcs_get_pixel_format(const struct mipi_dsi_device *dsi, u8 *format); -int mipi_dsi_dcs_enter_sleep_mode(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_exit_sleep_mode(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_display_off(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_display_on(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_column_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end); -int mipi_dsi_dcs_set_page_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end); -int mipi_dsi_dcs_set_tear_off(const struct mipi_dsi_device *dsi); -int mipi_dsi_dcs_set_tear_on(const struct mipi_dsi_device *dsi, - enum mipi_dsi_dcs_tear_mode mode); -int mipi_dsi_dcs_set_pixel_format(const struct mipi_dsi_device *dsi, u8 format); -int mipi_dsi_dcs_set_tear_scanline(const struct mipi_dsi_device *dsi, u16 scanline); -int mipi_dsi_dcs_set_display_brightness(const struct mipi_dsi_device *dsi, - u16 brightness); -int mipi_dsi_dcs_get_display_brightness(const struct mipi_dsi_device *dsi, - u16 *brightness); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_emac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_emac.h deleted file mode 100644 index 0af6f8a69a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_emac.h +++ /dev/null @@ -1,107 +0,0 @@ -/** - * @file hal_emac.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __HAL_EMAC_H__ -#define __HAL_EMAC_H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" -#include "bl808_emac.h" - -typedef struct emac_device { - struct device parent; - uint8_t mac_addr[6]; /*!< mac address */ -} emac_device_t; - -/** - * @brief EMAC PHY configuration type definition - */ -typedef struct -{ - uint8_t auto_negotiation; /*!< Speed and mode auto negotiation */ - uint8_t full_duplex; /*!< Duplex mode */ -#define PHY_STATE_DOWN (0) /* PHY is not usable */ -#define PHY_STATE_READY (1) /* PHY is OK, wait for controller */ -#define PHY_STATE_UP (2) /* Network is ready for TX/RX */ -#define PHY_STATE_RUNNING (3) /* working */ -#define PHY_STATE_NOLINK (4) /* no cable connected */ -#define PHY_STATE_STOPPED (5) /* PHY has been stopped */ -#define PHY_STATE_TESTING (6) /* in test mode */ - uint8_t phy_state; /*!< down,ready,up,running,nolink,halted */ - uint8_t use_irq; /*!< 0: no IRQ used */ - uint16_t speed; /*!< Speed mode */ - uint16_t phy_address; /*!< PHY address */ - uint32_t phy_id; /*!< PHY OUI */ -} emac_phy_cfg_t; - -#define EMAC_NORMAL_PACKET (uint32_t)(0) -#define EMAC_FRAGMENT_PACKET (uint32_t)(0x01) -#define EMAC_NOCOPY_PACKET (uint32_t)(0x02) - -#ifndef ETH_TX_BUFFER_SIZE -#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#ifndef ETH_RX_BUFFER_SIZE -#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE) -#endif - -#define EMAC_TX_COMMON_FLAGS (EMAC_BD_FIELD_MSK(TX_RD) | \ - EMAC_BD_FIELD_MSK(TX_IRQ) | \ - EMAC_BD_FIELD_MSK(TX_PAD) | \ - EMAC_BD_FIELD_MSK(TX_CRC) | \ - EMAC_BD_FIELD_MSK(TX_EOF)) - -#define EMAC_RX_COMMON_FLAGS (ETH_MAX_PACKET_SIZE << 16) | \ - EMAC_BD_FIELD_MSK(RX_IRQ) ) - -typedef enum _BD_TYPE_ { - EMAC_BD_TYPE_INVLAID, - EMAC_BD_TYPE_TX, - EMAC_BD_TYPE_RX, - EMAC_BD_TYPE_NONE, - EMAC_BD_TYPE_MAX = 0x7FFFFFFF -} EMAC_BD_TYPE_e; - -int emac_init(emac_device_t *emac_cfg); -int emac_bd_init(uint8_t *ethTxBuff, uint8_t txBufCount, uint8_t *ethRxBuff, uint8_t rxBufCount); -int emac_bd_fragment_support(void); -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in); -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out); -__WEAK void emac_rx_done_callback_app(void); -__WEAK void emac_rx_error_callback_app(void); -__WEAK void emac_rx_busy_callback_app(void); -__WEAK void emac_tx_error_callback_app(void); -__WEAK void emac_tx_done_callback_app(void); -int emac_phy_set_address(uint16_t phyAddress); -int emac_phy_config_full_duplex(uint8_t fullDuplex); -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue); -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue); -int emac_stop(void); -int emac_start(void); -int emac_start_tx(void); -int emac_stop_tx(void); -int emac_start_rx(void); -int emac_stop_rx(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_flash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_flash.h deleted file mode 100644 index be350dd694..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_flash.h +++ /dev/null @@ -1,42 +0,0 @@ -/** - * @file hal_flash.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_FLASH__H__ -#define __HAL_FLASH__H__ - -#include "hal_common.h" -#include "bl808_sflash.h" - -#define FLASH_NOT_DETECT 0x10 -#define BL_FLASH_XIP_BASE 0//BL808_FLASH_XIP_BASE - -uint32_t flash_get_jedecid(void); -BL_Err_Type flash_init(void); -BL_Err_Type flash_read_jedec_id(uint8_t *data); -BL_Err_Type flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type flash_read(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type flash_write(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type flash_erase(uint32_t startaddr, uint32_t len); -BL_Err_Type flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset); -BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_gpio.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_gpio.h deleted file mode 100644 index e7459f3ca3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_gpio.h +++ /dev/null @@ -1,103 +0,0 @@ -/** - * @file hal_gpio.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_GPIO__H__ -#define __HAL_GPIO__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -enum gpio_pin_type { - GPIO_PIN_0 = 0, - GPIO_PIN_1, - GPIO_PIN_2, - GPIO_PIN_3, - GPIO_PIN_4, - GPIO_PIN_5, - GPIO_PIN_6, - GPIO_PIN_7, - GPIO_PIN_8, - GPIO_PIN_9, - GPIO_PIN_10, - GPIO_PIN_11, - GPIO_PIN_12, - GPIO_PIN_13, - GPIO_PIN_14, - GPIO_PIN_15, - GPIO_PIN_16, - GPIO_PIN_17, - GPIO_PIN_18, - GPIO_PIN_19, - GPIO_PIN_20, - GPIO_PIN_21, - GPIO_PIN_22, - GPIO_PIN_23, - GPIO_PIN_24, - GPIO_PIN_25, - GPIO_PIN_26, - GPIO_PIN_27, - GPIO_PIN_28, - GPIO_PIN_29, - GPIO_PIN_30, - GPIO_PIN_31, - GPIO_PIN_32, - GPIO_PIN_33, - GPIO_PIN_34, - GPIO_PIN_35, - GPIO_PIN_36, - GPIO_PIN_37, - GPIO_PIN_38, - GPIO_PIN_39, - GPIO_PIN_40, - GPIO_PIN_41, - GPIO_PIN_42, - GPIO_PIN_43, - GPIO_PIN_44, - GPIO_PIN_45, - GPIO_PIN_MAX, -}; - -#define GPIO_OUTPUT_MODE 0 -#define GPIO_OUTPUT_PP_MODE 1 -#define GPIO_OUTPUT_PD_MODE 2 -#define GPIO_INPUT_MODE 3 -#define GPIO_INPUT_PP_MODE 4 -#define GPIO_INPUT_PD_MODE 5 -#define GPIO_ASYNC_RISING_TRIGER_INT_MODE 6 -#define GPIO_ASYNC_FALLING_TRIGER_INT_MODE 7 -#define GPIO_ASYNC_HIGH_LEVEL_INT_MODE 8 -#define GPIO_ASYNC_LOW_LEVEL_INT_MODE 9 -#define GPIO_SYNC_RISING_TRIGER_INT_MODE 10 -#define GPIO_SYNC_FALLING_TRIGER_INT_MODE 11 -#define GPIO_SYNC_RISING_FALLING_TRIGER_INT_MODE 12 -#define GPIO_SYNC_HIGH_LEVEL_INT_MODE 13 -#define GPIO_SYNC_LOW_LEVEL_INT_MODE 14 -#define GPIO_HZ_MODE 15 - -void gpio_set_mode(uint32_t pin, uint32_t mode); -void gpio_write(uint32_t pin, uint32_t value); -void gpio_toggle(uint32_t pin); -int gpio_read(uint32_t pin); -void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)); -void gpio_irq_enable(uint32_t pin, uint8_t enabled); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2c.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2c.h deleted file mode 100644 index 028ef6888a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2c.h +++ /dev/null @@ -1,77 +0,0 @@ -/** - * @file hal_i2c.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_I2C__H__ -#define __HAL_I2C__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -enum i2c_index_type { -#ifdef BSP_USING_I2C0 - I2C0_INDEX, -#endif -#ifdef BSP_USING_I2C1 - I2C1_INDEX, -#endif -#ifdef BSP_USING_I2C2 - I2C2_INDEX, -#endif -#ifdef BSP_USING_I2C3 - I2C3_INDEX, -#endif - I2C_MAX_INDEX -}; - -#define I2C_WR 0x0000 -#define I2C_RD 0x0001 -#define I2C_RW_MASK 0x0001 - -#define SUB_ADDR_0BYTE 0x0010 -#define SUB_ADDR_1BYTE 0x0020 -#define SUB_ADDR_2BYTE 0x0040 - -#define I2C_HW_MODE 0 -#define I2C_SW_MODE 1 - -typedef struct i2c_msg { - uint8_t slaveaddr; - uint32_t subaddr; - uint16_t flags; - uint16_t len; - uint8_t *buf; -} i2c_msg_t; - -typedef struct i2c_device { - struct device parent; - uint8_t id; - uint8_t mode; - uint32_t phase; -} i2c_device_t; - -#define I2C_DEV(dev) ((i2c_device_t *)dev) - -int i2c_register(enum i2c_index_type index, const char *name); -int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2s.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2s.h deleted file mode 100644 index ec9ee66434..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_i2s.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * @file hal_i2s.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_I2S__H__ -#define __HAL_I2S__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define I2S_GET_TX_FIFO_CMD 0x10 -#define I2S_GET_RX_FIFO_CMD 0x11 -#define DEVICE_CTRL_I2S_ATTACH_TX_DMA 0x12 -#define DEVICE_CTRL_I2S_ATTACH_RX_DMA 0x13 - -enum i2s_index_type { -#ifdef BSP_USING_I2S0 - I2S0_INDEX, -#endif - I2S_MAX_INDEX -}; - -#define I2S_DEFAULT_RTO_TIMEOUT 15 - -/*! - * @brief I2S mode type settings - * - * This enumeration defines the I2S mode type - */ -typedef enum { - I2S_MODE_STD, /*!< I2S STD Mode */ - I2S_MODE_LEFT, /*!< Left-Justified Mode */ - I2S_MODE_RIGHT, /*!< Right-Justified Mode */ - I2S_MODE_DSP_A, /*!< DSP/PCM Mode A*/ - I2S_MODE_DSP_B, /*!< DSP/PCM Mode B*/ -} interface_mode_t; - -/*! - * @brief I2S frame size settings - * - * This enumeration defines the frame size type - */ -typedef enum { - I2S_FRAME_LEN_8 = 1, /*!< I2S frame size 8 bits */ - I2S_FRAME_LEN_16 = 2, /*!< I2S frame size 16 bits */ - I2S_FRAME_LEN_24 = 3, /*!< I2S frame size 24 bits */ - I2S_FRAME_LEN_32 = 4, /*!< I2S frame size 32 bits */ -} i2s_frame_size_t; - -/*! - * @brief I2S data size settings - * - * This enumeration defines the data size type - */ -typedef enum { - I2S_DATA_LEN_8 = 1, /*!< I2S data size 8 bits */ - I2S_DATA_LEN_16 = 2, /*!< I2S data size 16 bits */ - I2S_DATA_LEN_24 = 3, /*!< I2S data size 24 bits */ - I2S_DATA_LEN_32 = 4, /*!< I2S data size 32 bits */ -} i2s_data_size_t; - -/*! - * @brief I2S frame channel settings - * - * This enumeration defines the frame channel mode type - */ -typedef enum { - I2S_FS_CHANNELS_NUM_MONO = 1, /*!< I2S frame is for 1 channels */ - I2S_FS_CHANNELS_NUM_2 = 2, /*!< I2S frame is for 2 channels */ - I2S_FS_CHANNELS_NUM_3 = 3, /*!< I2S frame is for 3 channels, DSP mode only, frame_size must equal data_size*/ - I2S_FS_CHANNELS_NUM_4 = 4, /*!< I2S frame is for 4 channels, DSP mode only, frame_size must equal data_size*/ -} i2s_channel_num_t; - -typedef enum { - I2S_MODE_MASTER = 0, /*!< I2S as master */ - I2S_MODE_SLAVE, /*!< I2S as slave */ -} i2s_mode_t; - -typedef struct i2s_device { - struct device parent; - uint8_t id; - - i2s_mode_t iis_mode; - interface_mode_t interface_mode; - uint32_t sampl_freq_hz; /*!< I2S sample data frequency in Hz */ - i2s_channel_num_t channel_num; - i2s_frame_size_t frame_size; - i2s_data_size_t data_size; - uint8_t fifo_threshold; /*!< I2S receive and transmit threshold*/ - void *tx_dma; - void *rx_dma; -} i2s_device_t; - -#define I2S_DEV(dev) ((i2s_device_t *)dev) - -int i2s_register(enum i2s_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_mtimer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_mtimer.h deleted file mode 100644 index 07baccff02..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_mtimer.h +++ /dev/null @@ -1,43 +0,0 @@ -/** - * @file hal_mtimer.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_MTIMER__H__ -#define __HAL_MTIMER__H__ - -#include "stdint.h" - -#ifdef __cplusplus -extern "C" { -#endif - -void mtimer_init(void); -void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)); -uint64_t mtimer_get_time_ms(); -uint64_t mtimer_get_time_us(); -void mtimer_delay_ms(uint32_t time); -void mtimer_delay_us(uint32_t time); - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pm.h deleted file mode 100644 index 1fa174b148..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pm.h +++ /dev/null @@ -1,92 +0,0 @@ -/** - * @file hal_pm.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_PM__H__ -#define __HAL_PM__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -enum pm_pds_sleep_level { - PM_PDS_LEVEL_1 = 1, - PM_PDS_LEVEL_2 = 2, - PM_PDS_LEVEL_3 = 3, - PM_PDS_LEVEL_7 = 7, -}; - -enum pm_hbn_sleep_level { - PM_HBN_LEVEL_0, - PM_HBN_LEVEL_1, - PM_HBN_LEVEL_2, -}; - -/** - * @brief HBN BOR threshold type definition - */ -typedef enum { - HBN_BOR_THRES_2P05V = 0, /*!< BOR threshold 2.05V */ - HBN_BOR_THRES_2P10V, /*!< BOR threshold 2.10V */ - HBN_BOR_THRES_2P15V, /*!< BOR threshold 2.15V */ - HBN_BOR_THRES_2P20V, /*!< BOR threshold 2.20V */ - HBN_BOR_THRES_2P25V, /*!< BOR threshold 2.25V */ - HBN_BOR_THRES_2P30V, /*!< BOR threshold 2.30V */ - HBN_BOR_THRES_2P35V, /*!< BOR threshold 2.35V */ - HBN_BOR_THRES_2P40V, /*!< BOR threshold 2.40V */ -} HBN_BOR_THRES_Type; - -/** - * @brief HBN BOR mode type definition - */ -typedef enum { - HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */ - HBN_BOR_MODE_POR_RELEVANT, /*!< POR is relevant to BOR */ -} HBN_BOR_MODE_Type; - -enum pm_event_type { - PM_HBN_WAKEUP_EVENT_NONE, - PM_HBN_GPIO9_WAKEUP_EVENT, - PM_HBN_GPIO10_WAKEUP_EVENT, - PM_HBN_GPIO11_WAKEUP_EVENT, - PM_HBN_GPIO12_WAKEUP_EVENT, - PM_HBN_GPIO13_WAKEUP_EVENT, - PM_HBN_GPIO14_WAKEUP_EVENT, - PM_HBN_GPIO15_WAKEUP_EVENT, - PM_HBN_GPIO40_WAKEUP_EVENT, - PM_HBN_GPIO41_WAKEUP_EVENT, - PM_HBN_RTC_WAKEUP_EVENT, - PM_HBN_BOD_WAKEUP_EVENT, - PM_HBN_ACOMP0_WAKEUP_EVENT, - PM_HBN_ACOMP1_WAKEUP_EVENT, -}; - -void pm_pds_mask_all_wakeup_src(void); -void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time); -void pm_hbn_out0_irq_register(void); -void pm_hbn_out1_irq_register(void); -void HBN_OUT0_IRQ(void); -void HBN_OUT1_IRQ(void); -void pm_irq_callback(enum pm_event_type event); -void pm_pds_irq_register(void); -void PDS_WAKEUP_IRQ(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pwm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pwm.h deleted file mode 100644 index 10326175fb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_pwm.h +++ /dev/null @@ -1,117 +0,0 @@ -/** - * @file hal_pwm.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_PWM__H__ -#define __HAL_PWM__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_PWM_CHANNEL_CONFIG 0x10 -#define DEVICE_CTRL_PWM_BREAK_CONFIG 0x11 -#define DEVICE_CTRL_PWM_FREQUENCE_CONFIG 0x12 -#define DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG 0x13 -#define DEVICE_CTRL_PWM_PULSE_CONFIG 0x14 - -enum pwm_index_type { -#ifdef BSP_USING_PWM0 - PWM0_INDEX, -#endif -#ifdef BSP_USING_PWM1 - PWM1_INDEX, -#endif - PWM_MAX_INDEX -}; - -#define PWM_CHANNEL_0 (1 << 0) -#define PWM_CHANNEL_1 (1 << 1) -#define PWM_CHANNEL_2 (1 << 2) -#define PWM_CHANNEL_3 (1 << 3) - -#define PWM_SINGLE_OUTPUT_MODE 0 -#define PWM_CONTINUE_OUTPUT_MODE 1 - -#define PWM_CLK_SOURCE_XCLK 0 -#define PWM_CLK_SOURCE_BCLK 1 -#define PWM_CLK_SOURCE_32K 2 - -enum pwm_event_type { - PWM_EVENT_PERIOD_END, - PWM_EVENT_PULSE, - PWM_EVENT_BREAK, -}; - -typedef struct -{ - uint8_t ch; - uint8_t chp_enable; - uint8_t chn_enable; - uint8_t chp_polarity; - uint8_t chn_polarity; - uint8_t chp_idlestate; - uint8_t chn_idlestate; - uint16_t threshold_low; - uint16_t threshold_high; -} pwm_channel_common_t; - -typedef struct -{ - uint8_t ch; - uint16_t threshold_low; - uint16_t threshold_high; -} pwm_channel_dutycycle_t; - -typedef struct -{ - uint8_t ch; - uint8_t chp_breakstate; - uint8_t chn_breakstate; - uint8_t deadtime; -} pwm_channel_break_t; - -typedef struct pwm_device { - struct device parent; - uint8_t id; - uint8_t clk_source; - uint8_t clk_div; - uint8_t output_mode; - uint16_t period; - uint16_t pulse; - uint8_t extern_break_polarity; - uint8_t extern_break_enable; - uint8_t internal_break_enable; - uint8_t adc_trig_source; -} pwm_device_t; - -#define PWM_DEV(dev) ((pwm_device_t *)dev) - -int pwm_register(enum pwm_index_type index, const char *name); - -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_rtc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_rtc.h deleted file mode 100644 index d432ad6017..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_rtc.h +++ /dev/null @@ -1,38 +0,0 @@ -/** - * @file hal_rtc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_RTC__H__ -#define __HAL_RTC__H__ - -#ifdef __cplusplus -extern "C" { -#endif - -#include "hal_common.h" - -void rtc_init(uint64_t sleep_time); -void rtc_set_timestamp(uint64_t time_stamp); -uint64_t rtc_get_timestamp(void); -#ifdef __cplusplus -} -#endif -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_aes.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_aes.h deleted file mode 100644 index edeab53e15..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_aes.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file hal_sec_aes.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_AES__H__ -#define __HAL_SEC_AES__H__ - -#include "hal_common.h" - -typedef enum { - SEC_AES_CBC, - SEC_AES_CTR, - SEC_AES_XTS, - SEC_AES_ECB -} sec_aes_type; - -typedef enum { - SEC_AES_KEY_128, - SEC_AES_KEY_256, - SEC_AES_KEY_192 -} sec_aes_key_type; - -typedef struct sec_aes_handle_t { - sec_aes_type aes_type; - sec_aes_key_type key_type; -} sec_aes_handle_t; - -typedef enum { - SEC_AES_DIR_ENCRYPT, - SEC_AES_DIR_DECRYPT -} sec_aes_dir_type; - -int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type); -int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir); -int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out); -int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out); -int sec_aes_deinit(sec_aes_handle_t *handle); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_dsa.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_dsa.h deleted file mode 100644 index 246c695c54..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_dsa.h +++ /dev/null @@ -1,57 +0,0 @@ -/** - * @file hal_sec_dsa.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_DSA__H__ -#define __HAL_SEC_DSA__H__ - -#include "hal_common.h" - -typedef struct sec_dsa_crt_cfg_tag { - uint32_t *dP; - uint32_t *dQ; - uint32_t *qInv; - uint32_t *p; - uint32_t *invR_p; - uint32_t *primeN_p; - uint32_t *q; - uint32_t *invR_q; - uint32_t *primeN_q; -} sec_dsa_crt_cfg_t; - -typedef struct -{ - uint32_t size; - uint32_t crtSize; - uint32_t *n; - uint32_t *e; - uint32_t *d; - sec_dsa_crt_cfg_t crtCfg; -} sec_dsa_handle_t; - -int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size); -int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r); -int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r); -int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r); -int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s); -int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_ecdsa.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_ecdsa.h deleted file mode 100644 index 8c117ef5e8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_ecdsa.h +++ /dev/null @@ -1,62 +0,0 @@ -/** - * @file hal_sec_ecdsa.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_ECDSA__H__ -#define __HAL_SEC_ECDSA__H__ - -#include "hal_common.h" - -typedef enum { - ECP_SECP256R1 = 0, - ECP_SECP256K1 = 1, - ECP_TYPE_MAX = 2, -} sec_ecp_type; - -typedef struct -{ - sec_ecp_type ecpId; - uint32_t *privateKey; - uint32_t *publicKeyx; - uint32_t *publicKeyy; -} sec_ecdsa_handle_t; - -typedef struct -{ - sec_ecp_type ecpId; -} sec_ecdh_handle_t; - -int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id); -int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle); -int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s); -int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s); -int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key); -int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); - -int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id); -int sec_ecdh_deinit(sec_ecdh_handle_t *handle); -int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); -int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy); -int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size); - -#define SEC_CODEPATH_STATE_SIGN 0x48672386 - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_hash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_hash.h deleted file mode 100644 index 08d7d55480..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_sec_hash.h +++ /dev/null @@ -1,64 +0,0 @@ -/** - * @file hal_sec_hash.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SEC_HASH__H__ -#define __HAL_SEC_HASH__H__ - -#include "drv_device.h" -#include "hal_common.h" - -enum sec_hash_index_type { - SEC_HASH0_INDEX, - SEC_HASH_MAX_INDEX -}; - -enum sec_hash_type { - SEC_HASH_SHA1, - SEC_HASH_SHA224, - SEC_HASH_SHA256, - SEC_HASH_SHA384, - SEC_HASH_SHA512, - SEC_HASH_UNKNOWN -}; - -typedef struct sec_hash_device { - struct device parent; - uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */ - uint32_t shaPadding[64 / 4]; /*!< Padding data */ - uint8_t type; /*!< Sha has feed data */ -} sec_hash_device_t; - -typedef struct -{ - uint32_t shaBuf[64 / 4]; /*!< Data not processed but in this temp buffer */ - uint32_t shaPadding[64 / 4]; /*!< Padding data */ - uint8_t type; /*!< Sha has feed data */ -} sec_hash_handle_t; - -int sec_hash_init(sec_hash_handle_t *handle, uint8_t type); -int sec_hash_deinit(sec_hash_handle_t *handle); -int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size); -int sec_hash_finish(sec_hash_handle_t *handle, void *buffer); -int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name); -int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi.h deleted file mode 100644 index 105c9190db..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi.h +++ /dev/null @@ -1,129 +0,0 @@ -/** - * @file hal_spi.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SPI__H__ -#define __HAL_SPI__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define SPI_FIFO_LEN 32 - -#define DEVICE_CTRL_SPI_CONFIG_CLOCK 0x10 - -#define DEVICE_CTRL_SPI_GET_TX_FIFO 0x11 -#define DEVICE_CTRL_SPI_GET_RX_FIFO 0x12 -#define DEVICE_CTRL_SPI_CLEAR_TX_FIFO 0x13 -#define DEVICE_CTRL_SPI_CLEAR_RX_FIFO 0x14 - -#define DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS 0x15 -#define DEVICE_CTRL_SPI_SET_FRAME_SIZE 0x16 - -enum spi_index_type { -#ifdef BSP_USING_SPI0 - SPI0_INDEX, -#endif -#ifdef BSP_USING_SPI1 - SPI1_INDEX, -#endif - SPI_MAX_INDEX -}; - -/** @defgroup SPI_Direction SPI Direction Mode (Only when the datasize==SPI_DATASIZE_32BIT) - * @{ - */ -typedef enum { - SPI_LSB_BYTE0_DIRECTION_FIRST = 0, - SPI_LSB_BYTE3_DIRECTION_FIRST, - SPI_MSB_BYTE0_DIRECTION_FIRST, - SPI_MSB_BYTE3_DIRECTION_FIRST, -}spi_byte_order_type; - -/** @defgroup SPI_Data_Size SPI Data Size - * @{ - */ -typedef enum { - SPI_DATASIZE_8BIT = 0, - SPI_DATASIZE_16BIT, - SPI_DATASIZE_24BIT, - SPI_DATASIZE_32BIT, -}spi_data_size_type; - -/** @defgroup SPI_Clock_Polarity SPI Clock Polarity - * @{ - */ -typedef enum { - SPI_POLARITY_LOW = 0, - SPI_POLARITY_HIGH, -}spi_polarity_type; - -/** @defgroup SPI_Clock_Phase SPI Clock Phase - * @{ - */ - typedef enum { - SPI_PHASE_1EDGE = 0, - SPI_PHASE_2EDGE, -}spi_phase_type; - -/** @defgroup - * @{ - */ -typedef enum { - SPI_SLVAE_MODE = 0, - SPI_MASTER_MODE, -}spi_mode_type; - -typedef enum { - SPI_TRANSFER_TYPE_8BIT = 0, - SPI_TRANSFER_TYPE_16BIT, - SPI_TRANSFER_TPYE_24BIT, - SPI_TRANSFER_TYPE_32BIT, -}spi_transfer_size_type; - -typedef enum{ - SPI_EVENT_TX_FIFO =0, - SPI_EVENT_RX_FIFO, - SPI_EVENT_UNKNOWN, -}spi_event_type; - -typedef struct spi_device { - struct device parent; - uint8_t id; - uint32_t clk; - spi_mode_type mode; - spi_byte_order_type direction; - spi_polarity_type clk_polaraity; - spi_phase_type clk_phase; - spi_data_size_type datasize; - uint8_t fifo_threshold; - uint8_t pin_swap_enable; /*swap mosi and miso*/ - uint8_t delitch_cnt; - void *tx_dma; - void *rx_dma; -} spi_device_t; - -#define SPI_DEV(dev) ((spi_device_t *)dev) - -int spi_register(enum spi_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi_flash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi_flash.h deleted file mode 100644 index d43ccc4199..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_spi_flash.h +++ /dev/null @@ -1,35 +0,0 @@ -/** - * @file hal_spi_flash.h - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_SPI_FLASH__H__ -#define __HAL_SPI_FLASH__H__ - -#include "hal_common.h" - -void spi_flash_set_gpio(uint8_t clk, uint8_t cs, uint8_t mosi, uint8_t miso); -BL_Err_Type spi_flash_init(void); -BL_Err_Type spi_flash_read_jedec_id(uint8_t *data); -BL_Err_Type spi_flash_read(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type spi_flash_write(uint32_t addr, uint8_t *data, uint32_t len); -BL_Err_Type spi_flash_erase(uint32_t startaddr, uint32_t len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_timer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_timer.h deleted file mode 100644 index 2a8a52b36d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_timer.h +++ /dev/null @@ -1,94 +0,0 @@ -/** - * @file hal_timer.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_TIMER__H__ -#define __HAL_TIMER__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define DEVICE_CTRL_TIMER_CH_START 0x80 -#define DEVICE_CTRL_TIMER_CH_STOP 0x81 - -enum timer_index_type { -#ifdef BSP_USING_TIMER_CH0 - TIMER_CH0_INDEX, -#endif -#ifdef BSP_USING_TIMER_CH1 - TIMER_CH1_INDEX, -#endif - TIMER_MAX_INDEX -}; - -enum timer_event_type { - TIMER_EVENT_COMP0, - TIMER_EVENT_COMP1, - TIMER_EVENT_COMP2, - TIMER_EVENT_UNKNOWN -}; - -enum timer_it_type { - TIMER_COMP0_IT = 1 << 0, - TIMER_COMP1_IT = 1 << 1, - TIMER_COMP2_IT = 1 << 2, - TIMER_ALL_IT = 1 << 3 -}; -typedef enum { - TIMER_CLK_FCLK, - TIMER_CLK_32K, - TIMER_CLK_1K, - TIMER_CLK_XTAL, -} timer_clk_src_t; - -typedef enum { - TIMER_PL_TRIG_NONE, - TIMER_PL_TRIG_COMP0, - TIMER_PL_TRIG_COMP1, - TIMER_PL_TRIG_COMP2, -} timer_pl_trig_t; - -typedef enum { - TIMER_CNT_PRELOAD, - TIMER_CNT_FREERUN, -} timer_cnt_mode; - -typedef struct -{ - uint32_t timeout_val; - uint32_t comp_it; -} timer_user_cfg_t; - -typedef struct timer_device { - struct device parent; - uint8_t id; - uint8_t ch; - uint8_t clk_div; - timer_cnt_mode cnt_mode; - timer_pl_trig_t pl_trig_src; -} timer_device_t; - -#define TIMER_DEV(dev) ((timer_device_t *)dev) - -int timer_register(enum timer_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_uart.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_uart.h deleted file mode 100644 index 2555e746f7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_uart.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file hal_uart.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_UART__H__ -#define __HAL_UART__H__ - -#include "hal_common.h" -#include "drv_device.h" -#include "bl808_config.h" - -#define UART_FIFO_LEN 32 - -#define DEVICE_CTRL_UART_GET_TX_FIFO 0x10 -#define DEVICE_CTRL_UART_GET_RX_FIFO 0x11 - -enum uart_index_type { -#ifdef BSP_USING_UART0 - UART0_INDEX, -#endif -#ifdef BSP_USING_UART1 - UART1_INDEX, -#endif -#ifdef BSP_USING_UART2 - UART2_INDEX, -#endif -#ifdef BSP_USING_UART3 - UART3_INDEX, -#endif - UART_MAX_INDEX -}; - -/*! - * @brief UART data length settings - * - * This enumeration defines the UART data lengths. - */ -typedef enum { - UART_DATA_LEN_5 = 0, /*!< Data length is 5 bits */ - UART_DATA_LEN_6 = 1, /*!< Data length is 6 bits */ - UART_DATA_LEN_7 = 2, /*!< Data length is 7 bits */ - UART_DATA_LEN_8 = 3 /*!< Data length is 8 bits */ -} uart_databits_t; - -/*! - * @brief UART stop bit settings - * - * This enumeration defines the UART stop bits. - */ -typedef enum { - UART_STOP_ZERO_D_FIVE = 0, /*!< 0.5 stop bit */ - UART_STOP_ONE = 1, /*!< 1 stop bit */ - UART_STOP_ONE_D_FIVE = 2, /*!< 1.5 stop bit */ - UART_STOP_TWO = 3 /*!< 2 stop bits */ -} uart_stopbits_t; - -/*! - * @brief UART parity type settings - * - * This enumeration defines the UART parity types. - */ -typedef enum { - UART_PAR_NONE = 0, /*!< No parity */ - UART_PAR_ODD = 1, /*!< Parity bit is odd */ - UART_PAR_EVEN = 2, /*!< Parity bit is even */ -} uart_parity_t; - -enum uart_event_type { - UART_EVENT_TX_END, - UART_EVENT_TX_FIFO, - UART_EVENT_RX_END, - UART_EVENT_RX_FIFO, - UART_EVENT_RTO, - UART_EVENT_UNKNOWN -}; - -enum uart_it_type { - UART_TX_END_IT = 1 << 0, - UART_RX_END_IT = 1 << 1, - UART_TX_FIFO_IT = 1 << 2, - UART_RX_FIFO_IT = 1 << 3, - UART_RTO_IT = 1 << 4, - UART_PCE_IT = 1 << 5, - UART_TX_FER_IT = 1 << 6, - UART_RX_FER_IT = 1 << 7, - UART_ALL_IT = 1 << 8 -}; - -typedef struct -{ - uint32_t baudrate; - uart_databits_t databits; - uart_stopbits_t stopbits; - uart_parity_t parity; -} uart_param_cfg_t; - -typedef struct uart_device { - struct device parent; - uint8_t id; - uint32_t baudrate; - uart_databits_t databits; - uart_stopbits_t stopbits; - uart_parity_t parity; - uint8_t fifo_threshold; - void *tx_dma; - void *rx_dma; -} uart_device_t; - -#define UART_DEV(dev) ((uart_device_t *)dev) - -int uart_register(enum uart_index_type index, const char *name); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_usb.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_usb.h deleted file mode 100644 index 29d617c4af..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/hal_usb.h +++ /dev/null @@ -1,151 +0,0 @@ -/** - * @file hal_usb.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __HAL_USB__H__ -#define __HAL_USB__H__ - -#include "stdint.h" - -/** - * USB endpoint Transfer Type mask. - */ -#define USBD_EP_TYPE_CTRL 0 -#define USBD_EP_TYPE_ISOC 1 -#define USBD_EP_TYPE_BULK 2 -#define USBD_EP_TYPE_INTR 3 -#define USBD_EP_TYPE_MASK 3 - -/** - * USB endpoint direction and number. - */ -#define USB_EP_DIR_MASK 0x80U -#define USB_EP_DIR_IN 0x80U -#define USB_EP_DIR_OUT 0x00U - -#define USB_EP_OUT_MSK 0x7FU -#define USB_EP_IN_MSK 0x80U - -/** Get endpoint index (number) from endpoint address */ -#define USB_EP_GET_IDX(ep) ((ep) & ~USB_EP_DIR_MASK) -/** Get direction from endpoint address */ -#define USB_EP_GET_DIR(ep) ((ep)&USB_EP_DIR_MASK) -/** Get endpoint address from endpoint index and direction */ -#define USB_EP_GET_ADDR(idx, dir) ((idx) | ((dir)&USB_EP_DIR_MASK)) -/** True if the endpoint is an IN endpoint */ -#define USB_EP_DIR_IS_IN(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_IN) -/** True if the endpoint is an OUT endpoint */ -#define USB_EP_DIR_IS_OUT(ep) (USB_EP_GET_DIR(ep) == USB_EP_DIR_OUT) - -#define USB_SET_EP_OUT(ep) (ep & USB_EP_OUT_MSK) -#define USB_SET_EP_IN(ep) (ep | USB_EP_IN_MSK) - -#define USB_OUT_EP_NUM 8 -#define USB_IN_EP_NUM 8 - -enum usb_dc_event_type { - /** USB error reported by the controller */ - USB_DC_EVENT_ERROR, - /** USB reset */ - USB_DC_EVENT_RESET, - /** Start of Frame received */ - USB_DC_EVENT_SOF, - /** USB connection established, hardware enumeration is completed */ - USB_DC_EVENT_CONNECTED, - /** USB configuration done */ - USB_DC_EVENT_CONFIGURED, - /** USB connection suspended by the HOST */ - USB_DC_EVENT_SUSPEND, - /** USB connection lost */ - USB_DC_EVENT_DISCONNECTED, - /** USB connection resumed by the HOST */ - USB_DC_EVENT_RESUME, - - /** USB interface selected */ - USB_DC_EVENT_SET_INTERFACE, - /** USB interface selected */ - USB_DC_EVENT_SET_REMOTE_WAKEUP, - /** USB interface selected */ - USB_DC_EVENT_CLEAR_REMOTE_WAKEUP, - /** Set Feature ENDPOINT_HALT received */ - USB_DC_EVENT_SET_HALT, - /** Clear Feature ENDPOINT_HALT received */ - USB_DC_EVENT_CLEAR_HALT, - /** setup packet received */ - USB_DC_EVENT_SETUP_NOTIFY, - /** ep0 in packet received */ - USB_DC_EVENT_EP0_IN_NOTIFY, - /** ep0 out packet received */ - USB_DC_EVENT_EP0_OUT_NOTIFY, - /** ep in packet except ep0 received */ - USB_DC_EVENT_EP_IN_NOTIFY, - /** ep out packet except ep0 received */ - USB_DC_EVENT_EP_OUT_NOTIFY, - /** Initial USB connection status */ - USB_DC_EVENT_UNKNOWN -}; - -enum usb_error_type { - USB_DC_OK = 0, - USB_DC_EP_DIR_ERR = 1, - USB_DC_EP_EN_ERR = 2, - USB_DC_EP_TIMEOUT_ERR = 3, - USB_DC_ADDR_ERR = 4, - USB_DC_DMA_ERR = 5, - USB_DC_VDMA_ERR = 6, - USB_DC_DATA_NONE = 7, -}; -/** - * @brief USB Endpoint Configuration. - * - * Structure containing the USB endpoint configuration. - */ -struct usb_dc_ep_cfg { - /** The number associated with the EP in the device - * configuration structure - * IN EP = 0x80 | \ - * OUT EP = 0x00 | \ - */ - uint8_t ep_addr; - /** Endpoint Transfer Type. - * May be Bulk, Interrupt, Control or Isochronous - */ - uint8_t ep_type; - /** Endpoint max packet size */ - uint16_t ep_mps; -}; - -/* - * USB endpoint structure. - */ -typedef struct -{ - uint8_t ep_ena; - uint8_t is_stalled; - struct usb_dc_ep_cfg ep_cfg; -} usb_dc_ep_state_t; - -typedef struct usb_dc_device { - usb_dc_ep_state_t in_ep[8]; /*!< IN endpoint parameters */ - usb_dc_ep_state_t out_ep[8]; /*!< OUT endpoint parameters */ -} usb_dc_device_t; - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/mipi_display.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/mipi_display.h deleted file mode 100644 index a63d840161..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/inc/mipi_display.h +++ /dev/null @@ -1,187 +0,0 @@ -#ifndef MIPI_DISPLAY_H -#define MIPI_DISPLAY_H - -/** - * struct drm_panel - DRM panel object - */ -struct drm_panel { - /** - * @dev: - * - * Parent device of the panel. - */ - struct device *dev; - - /** - * @backlight: - * - * Backlight device, used to turn on backlight after the call - * to enable(), and to turn off backlight before the call to - * disable(). - * backlight is set by drm_panel_of_backlight() and drivers - * shall not assign it. - */ - struct backlight_device *backlight; - - /** - * @funcs: - * - * Operations that can be performed on the panel. - */ - const struct drm_panel_funcs *funcs; - - /** - * @connector_type: - * - * Type of the panel as a DRM_MODE_CONNECTOR_* value. This is used to - * initialise the drm_connector corresponding to the panel with the - * correct connector type. - */ - int connector_type; - - /** - * @list: - * - * Panel entry in registry. - */ - //struct list_head list; -}; - -/* MIPI DSI Processor-to-Peripheral transaction types */ -enum { - MIPI_DSI_V_SYNC_START = 0x01, - MIPI_DSI_V_SYNC_END = 0x11, - MIPI_DSI_H_SYNC_START = 0x21, - MIPI_DSI_H_SYNC_END = 0x31, - - MIPI_DSI_COMPRESSION_MODE = 0x07, - MIPI_DSI_END_OF_TRANSMISSION = 0x08, - - MIPI_DSI_COLOR_MODE_OFF = 0x02, - MIPI_DSI_COLOR_MODE_ON = 0x12, - MIPI_DSI_SHUTDOWN_PERIPHERAL = 0x22, - MIPI_DSI_TURN_ON_PERIPHERAL = 0x32, - - MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM = 0x03, - MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM = 0x13, - MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM = 0x23, - - MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM = 0x04, - MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM = 0x14, - MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM = 0x24, - - MIPI_DSI_DCS_SHORT_WRITE = 0x05, - MIPI_DSI_DCS_SHORT_WRITE_PARAM = 0x15, - - MIPI_DSI_DCS_READ = 0x06, - MIPI_DSI_EXECUTE_QUEUE = 0x16, - - MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE = 0x37, - - MIPI_DSI_NULL_PACKET = 0x09, - MIPI_DSI_BLANKING_PACKET = 0x19, - MIPI_DSI_GENERIC_LONG_WRITE = 0x29, - MIPI_DSI_DCS_LONG_WRITE = 0x39, - - MIPI_DSI_PICTURE_PARAMETER_SET = 0x0a, - MIPI_DSI_COMPRESSED_PIXEL_STREAM = 0x0b, - - MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20 = 0x0c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24 = 0x1c, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16 = 0x2c, - - MIPI_DSI_PACKED_PIXEL_STREAM_30 = 0x0d, - MIPI_DSI_PACKED_PIXEL_STREAM_36 = 0x1d, - MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12 = 0x3d, - - MIPI_DSI_PACKED_PIXEL_STREAM_16 = 0x0e, - MIPI_DSI_PACKED_PIXEL_STREAM_18 = 0x1e, - MIPI_DSI_PIXEL_STREAM_3BYTE_18 = 0x2e, - MIPI_DSI_PACKED_PIXEL_STREAM_24 = 0x3e, -}; - -/* MIPI DSI Peripheral-to-Processor transaction types */ -enum { - MIPI_DSI_RX_ACKNOWLEDGE_AND_ERROR_REPORT = 0x02, - MIPI_DSI_RX_END_OF_TRANSMISSION = 0x08, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_1BYTE = 0x11, - MIPI_DSI_RX_GENERIC_SHORT_READ_RESPONSE_2BYTE = 0x12, - MIPI_DSI_RX_GENERIC_LONG_READ_RESPONSE = 0x1a, - MIPI_DSI_RX_DCS_LONG_READ_RESPONSE = 0x1c, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_1BYTE = 0x21, - MIPI_DSI_RX_DCS_SHORT_READ_RESPONSE_2BYTE = 0x22, -}; - -/* MIPI DCS commands */ -enum { - MIPI_DCS_NOP = 0x00, - MIPI_DCS_SOFT_RESET = 0x01, - MIPI_DCS_GET_COMPRESSION_MODE = 0x03, - MIPI_DCS_GET_DISPLAY_ID = 0x04, - MIPI_DCS_GET_ERROR_COUNT_ON_DSI = 0x05, - MIPI_DCS_GET_RED_CHANNEL = 0x06, - MIPI_DCS_GET_GREEN_CHANNEL = 0x07, - MIPI_DCS_GET_BLUE_CHANNEL = 0x08, - MIPI_DCS_GET_DISPLAY_STATUS = 0x09, - MIPI_DCS_GET_POWER_MODE = 0x0A, - MIPI_DCS_GET_ADDRESS_MODE = 0x0B, - MIPI_DCS_GET_PIXEL_FORMAT = 0x0C, - MIPI_DCS_GET_DISPLAY_MODE = 0x0D, - MIPI_DCS_GET_SIGNAL_MODE = 0x0E, - MIPI_DCS_GET_DIAGNOSTIC_RESULT = 0x0F, - MIPI_DCS_ENTER_SLEEP_MODE = 0x10, - MIPI_DCS_EXIT_SLEEP_MODE = 0x11, - MIPI_DCS_ENTER_PARTIAL_MODE = 0x12, - MIPI_DCS_ENTER_NORMAL_MODE = 0x13, - MIPI_DCS_GET_IMAGE_CHECKSUM_RGB = 0x14, - MIPI_DCS_GET_IMAGE_CHECKSUM_CT = 0x15, - MIPI_DCS_EXIT_INVERT_MODE = 0x20, - MIPI_DCS_ENTER_INVERT_MODE = 0x21, - MIPI_DCS_SET_GAMMA_CURVE = 0x26, - MIPI_DCS_SET_DISPLAY_OFF = 0x28, - MIPI_DCS_SET_DISPLAY_ON = 0x29, - MIPI_DCS_SET_COLUMN_ADDRESS = 0x2A, - MIPI_DCS_SET_PAGE_ADDRESS = 0x2B, - MIPI_DCS_WRITE_MEMORY_START = 0x2C, - MIPI_DCS_WRITE_LUT = 0x2D, - MIPI_DCS_READ_MEMORY_START = 0x2E, - MIPI_DCS_SET_PARTIAL_ROWS = 0x30, /* MIPI DCS 1.02 - MIPI_DCS_SET_PARTIAL_AREA before that */ - MIPI_DCS_SET_PARTIAL_COLUMNS = 0x31, - MIPI_DCS_SET_SCROLL_AREA = 0x33, - MIPI_DCS_SET_TEAR_OFF = 0x34, - MIPI_DCS_SET_TEAR_ON = 0x35, - MIPI_DCS_SET_ADDRESS_MODE = 0x36, - MIPI_DCS_SET_SCROLL_START = 0x37, - MIPI_DCS_EXIT_IDLE_MODE = 0x38, - MIPI_DCS_ENTER_IDLE_MODE = 0x39, - MIPI_DCS_SET_PIXEL_FORMAT = 0x3A, - MIPI_DCS_WRITE_MEMORY_CONTINUE = 0x3C, - MIPI_DCS_SET_3D_CONTROL = 0x3D, - MIPI_DCS_READ_MEMORY_CONTINUE = 0x3E, - MIPI_DCS_GET_3D_CONTROL = 0x3F, - MIPI_DCS_SET_VSYNC_TIMING = 0x40, - MIPI_DCS_SET_TEAR_SCANLINE = 0x44, - MIPI_DCS_GET_SCANLINE = 0x45, - MIPI_DCS_SET_DISPLAY_BRIGHTNESS = 0x51, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_DISPLAY_BRIGHTNESS = 0x52, /* MIPI DCS 1.3 */ - MIPI_DCS_WRITE_CONTROL_DISPLAY = 0x53, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_CONTROL_DISPLAY = 0x54, /* MIPI DCS 1.3 */ - MIPI_DCS_WRITE_POWER_SAVE = 0x55, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_POWER_SAVE = 0x56, /* MIPI DCS 1.3 */ - MIPI_DCS_SET_CABC_MIN_BRIGHTNESS = 0x5E, /* MIPI DCS 1.3 */ - MIPI_DCS_GET_CABC_MIN_BRIGHTNESS = 0x5F, /* MIPI DCS 1.3 */ - MIPI_DCS_READ_DDB_START = 0xA1, - MIPI_DCS_READ_PPS_START = 0xA2, - MIPI_DCS_READ_DDB_CONTINUE = 0xA8, - MIPI_DCS_READ_PPS_CONTINUE = 0xA9, -}; - -/* MIPI DCS pixel formats */ -#define MIPI_DCS_PIXEL_FMT_24BIT 7 -#define MIPI_DCS_PIXEL_FMT_18BIT 6 -#define MIPI_DCS_PIXEL_FMT_16BIT 5 -#define MIPI_DCS_PIXEL_FMT_12BIT 3 -#define MIPI_DCS_PIXEL_FMT_8BIT 2 -#define MIPI_DCS_PIXEL_FMT_3BIT 1 - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_adc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_adc.c deleted file mode 100644 index 3a21ad8dd6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_adc.c +++ /dev/null @@ -1,383 +0,0 @@ -/** - * @file hal_adc.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_adc.h" -#include "hal_clock.h" -#include "bl808_glb.h" -#include "bl808_dma.h" -#include "bl808_adc.h" -#include "adc_config.h" - -#ifdef BSP_USING_ADC0 -static void ADC_IRQ(void); -#endif - -static adc_device_t adcx_device[ADC_MAX_INDEX] = { -#ifdef BSP_USING_ADC0 - ADC0_CONFIG, -#endif -}; - -/** - * @brief Check whether Channel Corresponding IO is configed success by Board System - * - * @param pos_list pos channel list - * @param neg_list negative channel list - * @param channelNum channel number - */ -uint8_t adc_check_channel_status(uint8_t *pos_list, uint8_t *neg_list, uint16_t channelNum) -{ - return SUCCESS; -} -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int adc_open(struct device *dev, uint16_t oflag) -{ - adc_device_t *adc_device = (adc_device_t *)dev; - ADC_CFG_Type adc_cfg = { 0 }; - ADC_FIFO_Cfg_Type adc_fifo_cfg = { 0 }; - - CPU_Interrupt_Disable(GPADC_DMA_IRQn); - - ADC_IntMask(ADC_INT_ALL, MASK); - - adc_cfg.clkDiv = adc_device->clk_div; - - adc_cfg.vref = adc_device->vref; - adc_cfg.resWidth = adc_device->data_width; - adc_cfg.inputMode = adc_device->differential_mode; - - adc_cfg.v18Sel = ADC_V18_SELECT; - adc_cfg.v11Sel = ADC_V11_SELECT; - adc_cfg.gain1 = ADC_PGA_GAIN1; - adc_cfg.gain2 = ADC_PGA_GAIN2; - adc_cfg.chopMode = ADC_CHOP_MODE; - adc_cfg.biasSel = ADC_BIAS_SELECT; - adc_cfg.vcm = ADC_PGA_VCM; - adc_cfg.offsetCalibEn = ADC_OFFSET_CALIB_EN; - adc_cfg.offsetCalibVal = ADC_OFFSER_CALIB_VAL; - - adc_fifo_cfg.dmaEn = DISABLE; - adc_fifo_cfg.fifoThreshold = adc_device->fifo_threshold; - - if (oflag & DEVICE_OFLAG_STREAM_TX) { - } - - if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { -#ifdef BSP_USING_ADC0 - Interrupt_Handler_Register(GPADC_DMA_IRQn, ADC_IRQ); -#endif - } - - if (oflag & DEVICE_OFLAG_DMA_TX) { - } - - if (oflag & DEVICE_OFLAG_DMA_RX) { - adc_fifo_cfg.dmaEn = ENABLE; - } - - ADC_Disable(); - ADC_Enable(); - - ADC_Reset(); - - ADC_Init(&adc_cfg); - - ADC_FIFO_Cfg(&adc_fifo_cfg); - - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int adc_close(struct device *dev) -{ - uint32_t tmpVal; - - ADC_IntMask(ADC_INT_ALL, MASK); - - /* disable convert start */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /*disable adc */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /*disable vbat */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - - ADC_Reset(); - return 0; -} - -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int adc_control(struct device *dev, int cmd, void *args) -{ - adc_device_t *adc_device = (adc_device_t *)dev; - adc_channel_cfg_t *adc_channel_cfg = (adc_channel_cfg_t *)args; - uint8_t rlt = 0; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: { - uint32_t offset = __builtin_ctz((uint32_t)(uintptr_t)args); - while ((2 <= offset) && (offset < 6)) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - ADC_IntMask(offset, UNMASK); - } - offset++; - } - CPU_Interrupt_Enable(GPADC_DMA_IRQn); - - break; - } - - case DEVICE_CTRL_CLR_INT: { - uint32_t offset = __builtin_ctz((uint32_t)(uintptr_t)args); - while ((2 <= offset) && (offset < 6)) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - ADC_IntMask(offset, UNMASK); - } - offset++; - } - CPU_Interrupt_Disable(GPADC_DMA_IRQn); - - break; - } - - case DEVICE_CTRL_GET_INT: - break; - - case DEVICE_CTRL_CONFIG: - break; - - case DEVICE_CTRL_ADC_CHANNEL_CONFIG: - for (uint32_t i = 0; i < adc_channel_cfg->num; i++) { - if ((adc_channel_cfg->pos_channel[i] == ADC_CHAN5) || (adc_channel_cfg->neg_channel[i] == ADC_CHAN5)) { - HBN_Set_IO4041_As_Xtal_32K_IO(DISABLE); - } - } - if (adc_channel_cfg->num == 1) { - ADC_Channel_Config((ADC_Chan_Type)adc_channel_cfg->pos_channel[0], (ADC_Chan_Type)adc_channel_cfg->neg_channel[0], adc_device->continuous_conv_mode); - rlt = adc_check_channel_status((uint8_t *)adc_channel_cfg->pos_channel, (uint8_t *)adc_channel_cfg->neg_channel, 1); - } else { - ADC_Scan_Channel_Config((ADC_Chan_Type *)adc_channel_cfg->pos_channel, (ADC_Chan_Type *)adc_channel_cfg->neg_channel, adc_channel_cfg->num, adc_device->continuous_conv_mode); - rlt = adc_check_channel_status((uint8_t *)adc_channel_cfg->pos_channel, (uint8_t *)adc_channel_cfg->neg_channel, adc_channel_cfg->num); - } - - break; - - case DEVICE_CTRL_ADC_CHANNEL_START: { - uint32_t regCmd; - - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - arch_delay_us(100); - - /* enable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - } break; - - case DEVICE_CTRL_ADC_CHANNEL_STOP: { - uint32_t tmpVal; - - /* disable convert start */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_VBAT_ON: { - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_VBAT_OFF: { - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - break; - } - - case DEVICE_CTRL_ADC_TSEN_ON: - ADC_Tsen_Init(ADC_TSEN_MOD_INTERNAL_DIODE); - break; - - default: - break; - } - - return rlt; -} -// int adc_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -// { - -// return 0; -// } -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int adc_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - uint32_t adc_fifo_val[32]; - - if (dev->oflag & DEVICE_OFLAG_STREAM_RX) { - if (size > 32) - return -1; - while (ADC_Get_FIFO_Count() < size) { - } - - for (uint32_t i = 0; i < size; i++) { - adc_fifo_val[i] = ADC_Read_FIFO(); - } - adc_channel_val_t *adc_parse_val = (adc_channel_val_t *)buffer; - ADC_Parse_Result(adc_fifo_val, size, (ADC_Result_Type *)adc_parse_val); - return size; - } - - return 0; -} - -int adc_trim_tsen(uint16_t *tsen_offset) -{ - return ADC_Trim_TSEN(tsen_offset); -} - -float adc_get_tsen(uint16_t tsen_offset) -{ - return TSEN_Get_Temp(tsen_offset); -} - -/** - * @brief - * - * @param index - * @param name - * @return int - */ -int adc_register(enum adc_index_type index, const char *name) -{ - struct device *dev; - - if (ADC_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(adcx_device[index].parent); - - dev->open = adc_open; - dev->close = adc_close; - dev->control = adc_control; - dev->write = NULL; - dev->read = adc_read; - - dev->type = DEVICE_CLASS_ADC; - dev->handle = NULL; - - return device_register(dev, name); -} - -/** - * @brief - * - * @param handle - */ -void adc_isr(adc_device_t *handle) -{ - if (!handle->parent.callback) - return; - - if (ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET && ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK) { - //handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_POS_SATURATION); - ADC_IntClr(ADC_INT_POS_SATURATION); - } - - if (ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET && ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK) { - //handle->parent.callback(&handle->parent, NULL, 0, ADC_EVEN_INT_NEG_SATURATION); - ADC_IntClr(ADC_INT_NEG_SATURATION); - } - - if (ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK) { - handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_UNDERRUN); - ADC_IntClr(ADC_INT_FIFO_UNDERRUN); - } - - if (ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET && ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK) { - handle->parent.callback(&handle->parent, NULL, 0, ADC_EVENT_OVERRUN); - ADC_IntClr(ADC_INT_FIFO_OVERRUN); - } - - if (ADC_GetIntStatus(ADC_INT_ADC_READY) == SET && ADC_IntGetMask(ADC_INT_ADC_READY) == UNMASK) { - uint32_t adc_count = ADC_Get_FIFO_Count(); - uint32_t adc_fifo_val[32]; - adc_channel_val_t adc_parse_val[32]; - for (uint32_t i = 0; i < adc_count; i++) { - adc_fifo_val[i] = ADC_Read_FIFO(); - } - ADC_Parse_Result(adc_fifo_val, adc_count, (ADC_Result_Type *)adc_parse_val); - handle->parent.callback(&handle->parent, (void *)adc_parse_val, adc_count, ADC_INT_ADC_READY); - ADC_IntClr(ADC_INT_ADC_READY); - } -} -#ifdef BSP_USING_ADC0 -void ADC_IRQ(void) -{ - adc_isr(&adcx_device[ADC0_INDEX]); -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_boot2.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_boot2.c deleted file mode 100644 index 41b67976eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_boot2.c +++ /dev/null @@ -1,602 +0,0 @@ -#include "hal_boot2.h" -#include "hal_flash.h" -#include "bl808_ef_ctrl.h" -#include "bl808_ef_cfg.h" -#include "bl808_hbn.h" -#include "bl808_glb.h" -#include "bl808_xip_sflash.h" -#include "bl808_tzc_sec.h" -#include "hal_gpio.h" -#include "hal_sec_hash.h" -#include "bl808_sec_eng.h" -#include "softcrc.h" -#include "bl808_psram_uhs.h" -#include "bl808_romapi_patch.h" - -extern sec_hash_handle_t hash_handle; - -/** - * @brief boot2 init system clock - * - * @param None - * @return None - */ -void hal_boot2_init_clock(void) -{ - extern void system_mtimer_clock_init(void); - extern void peripheral_clock_init(void); - - system_mtimer_clock_init(); - peripheral_clock_init(); -} - -/** - * @brief boot2 custom - * - * @param custom_param - * @return uint32_t - */ -uint32_t hal_boot2_custom(void *custom_param) -{ - if (((g_efuse_cfg.dev_info & HAL_BOOT2_PSRAM_INFO_MASK) >> HAL_BOOT2_PSRAM_INFO_POS) != 0) { - GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M); - Psram_UHS_x16_Init(2000); - Tzc_Sec_PSRAMA_Access_Release(); - - /* Flush i-cache in case branch prediction logic is wrong when - psram is not inited by hal_boot2_custom but cpu has already prefetch psram */ - __ISB(); - } - return 0; -} - -/** - * @brief get efuse Boot2 config - * - * @param g_efuse_cfg - * @param - * @param - * @return None - */ -void hal_boot2_get_efuse_cfg(boot2_efuse_hw_config *efuse_cfg) -{ - uint32_t timeout_cnt = 0; - uint32_t i = 0; - struct boot_efuse_sw_cfg0_t sw_cfg0; - - /* #define EF_CTRL_LOAD_BEFORE_READ_R0 in ef_ctrl to speed up */ - EF_Ctrl_Load_Efuse_R0(); - EF_Ctrl_Load_Efuse_R1(); - - while (EF_Ctrl_AutoLoad_Done() != SET && timeout_cnt < 80) { - arch_delay_us(1); - timeout_cnt++; - } - - /* get hw cfg (signature and aes type) */ - EF_Ctrl_Read_Secure_Boot((EF_Ctrl_SF_AES_Type *)efuse_cfg->encrypted); - - for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { - if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_192) { - efuse_cfg->encrypted[i] = SF_CTRL_AES_192BITS + 1; - } else if (efuse_cfg->encrypted[i] == EF_CTRL_SF_AES_256) { - efuse_cfg->encrypted[i] = SF_CTRL_AES_256BITS + 1; - } - } - - /* get sw uasge 0 */ - EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&sw_cfg0); - /* get sw uasge 1 */ - //EF_Ctrl_Read_Sw_Usage(1, &sw_cfg1); - - for (i = 0; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { - efuse_cfg->sign[i] = ((struct boot_efuse_sw_cfg0_t)sw_cfg0).sign_cfg; - } - for (i = 1; i < HAL_BOOT2_CPU_GROUP_MAX; i++) { - efuse_cfg->encrypted[i] = EF_CTRL_SF_AES_NONE; - } - - efuse_cfg->hbn_check_sign = (uint8_t)(sw_cfg0.hbn_check_sign); - efuse_cfg->sf_pin_cfg = (uint8_t)(sw_cfg0.sf_pin_cfg); - efuse_cfg->uart_download_cfg = (uint8_t)(sw_cfg0.uart_download_cfg); - efuse_cfg->keep_dbg_port_closed = (uint8_t)(sw_cfg0.keep_dbg_port_closed); - efuse_cfg->boot_pin_cfg = (uint8_t)(sw_cfg0.boot_pin_cfg); - - /* get device info */ - EF_Ctrl_Get_Chip_Info((Efuse_Chip_Info_Type *)&efuse_cfg->dev_info); - - /* get chip id */ - EF_Ctrl_Read_Chip_ID(efuse_cfg->chip_id); - - /* get public key hash */ - EF_Ctrl_Read_AES_Key(0, (uint32_t *)efuse_cfg->pk_hash_cpu0, HAL_BOOT2_PK_HASH_SIZE / 4); - EF_Ctrl_Read_AES_Key(8, (uint32_t *)efuse_cfg->pk_hash_cpu1, HAL_BOOT2_PK_HASH_SIZE / 4); -} -/** - * @brief reset sec eng clock - * - * @return - */ -void hal_boot2_reset_sec_eng(void) -{ - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SEC_ENG); - Sec_Eng_Group0_Request_SHA_Access(); - Sec_Eng_Group0_Request_AES_Access(); - Sec_Eng_Group0_Request_Trng_Access(); - Sec_Eng_Trng_Enable(); - GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M); -} - -/** - * @brief system soft reset - * - * @return - */ -void hal_boot2_sw_system_reset(void) -{ - GLB_SW_System_Reset(); -} - -/** - * @brief - * - * @param flag - * @param - * @param - * @return - */ -void hal_boot2_set_psmode_status(uint32_t flag) -{ - HBN_Set_Status_Flag(flag); -} - -/** - * @brief - * - * @param - * @param - * @param - * @return flag - */ -uint32_t hal_boot2_get_psmode_status(void) -{ - return HBN_Get_Status_Flag(); -} - -/** - * @brief - * - * @param - * @param - * @param - * @return user define flag - */ -uint32_t hal_boot2_get_user_fw(void) -{ - return BL_RD_WORD(HBN_BASE + HBN_RSV0_OFFSET); -} - -/** - * @brief clr user define flag - * - * @param - * @param - * @param - * @return - */ -void hal_boot2_clr_user_fw(void) -{ - uint32_t *p = (uint32_t *)(HBN_BASE + HBN_RSV0_OFFSET); - *p = 0; -} - -/** - * @brief hal_boot2_sboot_finish - * - * @return - */ -void ATTR_TCM_SECTION hal_boot2_sboot_finish(void) -{ - // uint32_t tmpVal; - // if (!g_efuse_cfg.keep_dbg_port_closed) { - // /* only after this, JTAG is really open */ - // tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf); - // BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal); - // } -} - -void bflb_boot2_pds_hbn_pad_pn(void) -{ - /* clear pds/hbn ctrl pad pull type */ - PDS_Set_Flash_Pad_Pull_None_Fast((SF_Ctrl_Pin_Select)g_efuse_cfg.sf_pin_cfg); - HBN_AON_PAD_CFG_Type aonPadCfg = { - .ctrlEn = ENABLE, - .inputEn = ENABLE, - .outputEn = ENABLE, - .pullCfg = HBN_GPIO_PAD_PULL_NONE, - }; - HBN_Aon_Pad_Cfg(ENABLE, HBN_AON_PAD_GPIO14, &aonPadCfg); - HBN_Aon_Pad_Cfg(ENABLE, HBN_AON_PAD_GPIO15, &aonPadCfg); -} - -/** - * @brief hal_boot2_pll_init - * - * @return - */ -void hal_boot2_uart_gpio_init(void) -{ - GLB_GPIO_Cfg_Type cfg; - - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 0; - cfg.smtCtrl = 1; - - /* ToDo: will crash */ - //bflb_boot2_pds_hbn_pad_pn(); - - cfg.gpioPin = GLB_GPIO_PIN_15; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_INPUT; - GLB_GPIO_Init(&cfg); - - //GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 0); - GLB_UART_Fun_Sel(GLB_UART_SIG_3, GLB_UART_SIG_FUN_UART0_RXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART0_RXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_3); - - cfg.gpioPin = GLB_GPIO_PIN_14; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_OUTPUT; - GLB_GPIO_Init(&cfg); - - //GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 0); - - GLB_UART_Fun_Sel(GLB_UART_SIG_2, GLB_UART_SIG_FUN_UART0_TXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART0_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_2); -} - -/** - * @brief hal_boot2_pll_init - * - * @return - */ -void hal_boot2_debug_uart_gpio_init(void) -{ - GLB_GPIO_Cfg_Type cfg; - - cfg.pullType = GPIO_PULL_NONE; - cfg.drive = 0; - cfg.smtCtrl = 1; - - /* OTP_BOOTLOG_PIN_CFG() */ - /* 0 -> GPIO39 -> qfn68 */ - /* 1 -> GPIO8 -> qfn88 */ - if (0 == g_efuse_cfg.boot_pin_cfg) { - cfg.gpioPin = GLB_GPIO_PIN_39; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_OUTPUT; - GLB_GPIO_Init(&cfg); - - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1); - GLB_UART_Fun_Sel(GLB_UART_SIG_9, GLB_UART_SIG_FUN_UART1_TXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART1_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_9); - - } else { - cfg.gpioPin = GLB_GPIO_PIN_8; - cfg.gpioFun = GPIO_FUN_UART; - cfg.gpioMode = GPIO_MODE_OUTPUT; - GLB_GPIO_Init(&cfg); - - GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, 0); - GLB_UART_Fun_Sel(GLB_UART_SIG_8, GLB_UART_SIG_FUN_UART1_TXD); - GLB_UART_Fun_Sel((GLB_UART_SIG_Type)GLB_UART_SIG_FUN_UART1_TXD, (GLB_UART_SIG_FUN_Type)GLB_UART_SIG_8); - } -} - -/** - * @brief hal_boot2_debug_usb_port_init - * - * @return - */ -#if HAL_BOOT2_SUPPORT_USB_IAP -void hal_boot2_debug_usb_port_init(void) -{ -} -#endif - -/** - * @brief hal_boot2_debug_uart_gpio_deinit - * - * @return - */ -void hal_boot2_debug_uart_gpio_deinit(void) -{ -} - -/****************************************************************************/ /** - * @brief Check bootheader crc - * - * @param data: bootheader data pointer - * - * @return boot_error_code type - * -*******************************************************************************/ -static uint32_t hal_boot_check_bootheader(struct hal_bootheader_t *header) -{ - uint32_t crc_pass = 0; - uint32_t crc; - - if (header->basic_cfg.crc_ignore == 1 && header->crc32 == HAL_BOOT2_DEADBEEF_VAL) { - //MSG("Crc ignored\r\n"); - crc_pass = 1; - } else { - crc = BFLB_Soft_CRC32((uint8_t *)header, sizeof(struct hal_bootheader_t) - sizeof(header->crc32)); - - if (header->crc32 == crc) { - crc_pass = 1; - } - } - return crc_pass; -} - -/****************************************************************************/ /** - * @brief Check if the input public key is the same as burned in the efuse - * - * @param g_boot_img_cfg: Boot image config pointer - * @param data: Image data pointer - * - * @return boot_error_code type - * -*******************************************************************************/ -int32_t hal_boot_parse_bootheader(boot2_image_config *boot_img_cfg, uint8_t *data) -{ - struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; - uint32_t crc_pass = 0; - uint32_t i = 0; - uint32_t *phash = (uint32_t *)header->basic_cfg.hash; - - crc_pass = hal_boot_check_bootheader(header); - - if (!crc_pass) { - //MSG_ERR("bootheader crc error\r\n"); - //blsp_dump_data((uint8_t *)&crc, 4); - return 0x0204; - } - - if (header->basic_cfg.notload_in_bootrom) { - return 0x0202; - } - - /* Get which CPU's img it is*/ - for (i = 0; i < HAL_BOOT2_CPU_MAX; i++) { - if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, - sizeof(header->magiccode))) { - break; - } else if (0 == memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, - sizeof(header->magiccode))) { - break; - } - } - - if (i == HAL_BOOT2_CPU_MAX) { - /* No cpu img magic match */ - //MSG_ERR("Magic code error\r\n"); - return 0x0203; - } - - if (boot_img_cfg == NULL) { - return 0; - } - - boot_img_cfg->pk_src = i; - boot_img_cfg->img_valid = 0; - - arch_memcpy_fast(&boot_img_cfg->basic_cfg, &header->basic_cfg, - sizeof(header->basic_cfg)); - - /* Check encrypt and sign match*/ - if (g_efuse_cfg.encrypted[i] != boot_img_cfg->basic_cfg.encrypt_type) { - if (boot_img_cfg->basic_cfg.xts_mode == 0) { - //("Encrypt not fit\r\n"); - return 0x0205; - } - } - - if (g_efuse_cfg.sign[i] != boot_img_cfg->basic_cfg.sign_type) { - //MSG_ERR("sign not fit\r\n"); - boot_img_cfg->basic_cfg.sign_type = g_efuse_cfg.sign[i]; - return 0x0206; - } - - if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { - /* In HBN Mode, if user select to ignore hash and sign*/ - boot_img_cfg->basic_cfg.hash_ignore = 1; - } else if ((boot_img_cfg->basic_cfg.hash_ignore == 1 && *phash != HAL_BOOT2_DEADBEEF_VAL) || - g_efuse_cfg.sign[i] != 0) { - /* If signed or user not really want to ignore, hash can't be ignored*/ - boot_img_cfg->basic_cfg.hash_ignore = 0; - } - - if (g_user_hash_ignored) { - boot_img_cfg->basic_cfg.hash_ignore = 1; - } - - if (boot_img_cfg->basic_cfg.img_len_cnt == 0) { - return 0x0207; - } - - arch_memcpy_fast(&boot_img_cfg->cpu_cfg, &header->cpu_cfg, - sizeof(header->cpu_cfg)); - return 0; -} - -void ATTR_TCM_SECTION hal_boot2_clean_cache(void) -{ - L1C_DCache_Clean_Invalid_All(); - L1C_ICache_Invalid_All(); -} - -BL_Err_Type ATTR_TCM_SECTION hal_boot2_set_cache(uint8_t cont_read, boot2_image_config *boot_img_cfg) -{ - flash_set_cache(cont_read, boot_img_cfg->cpu_cfg[0].cache_enable, - boot_img_cfg->cpu_cfg[0].cache_way_dis, - boot_img_cfg->basic_cfg.group_image_offset); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get the ram image name and count - * - * @param img_name: ram image name in partition - * @param ram_img_cnt: ram image count that support boot from flash - * - * @return None - * -*******************************************************************************/ -void hal_boot2_get_ram_img_cnt(char *img_name[], uint32_t *ram_img_cnt) -{ - *ram_img_cnt = 5; - img_name[0] = "Imgload"; - img_name[1] = "SBI"; - img_name[2] = "Kernel"; - img_name[3] = "Rootfs"; - img_name[4] = "DTB"; -} - -/****************************************************************************/ /** - * @brief get the ram image info - * - * @param data: bootheader information - * @param image_offset: ram image offset in flash(from of bootheader) - * @param img_len: ram image length - * @param hash: pointer to hash pointer - * - * @return None - * -*******************************************************************************/ -void hal_boot2_get_img_info(uint8_t *data, uint32_t *image_offset, uint32_t *img_len, uint8_t **hash) -{ - struct hal_bootheader_t *header = (struct hal_bootheader_t *)data; - uint32_t crc_pass = 0; - *img_len = 0; - uint8_t *phash = *hash; - uint8_t hash_ignore = 1; - - crc_pass = hal_boot_check_bootheader(header); - - if (!crc_pass) { - return; - } - if (0 != memcmp((void *)&header->magiccode, HAL_BOOT2_CPU0_MAGIC, sizeof(header->magiccode)) && - 0 != memcmp((void *)&header->magiccode, HAL_BOOT2_CPU1_MAGIC, sizeof(header->magiccode))) { - return; - } - - /* for ram image, it always download in iot tab, so - it share the same group with core 0 but use different image offset and - boot entry */ - *image_offset = 4096 * 1; //bootheader->basic_cfg.group_image_offset; - *img_len = header->basic_cfg.img_len_cnt; - - if (g_ps_mode == 1 && (!g_efuse_cfg.hbn_check_sign)) { - /* In HBN Mode, if user select to ignore hash and sign*/ - hash_ignore = 1; - } else if ((header->basic_cfg.hash_ignore == 1 && header->basic_cfg.hash[0] != HAL_BOOT2_DEADBEEF_VAL) || - g_efuse_cfg.sign[0] != 0) { - /* If signed or user not really want to ignore, hash can't be ignored*/ - hash_ignore = 0; - } - - if (hash_ignore == 1) { - *hash = NULL; - } else { - memcpy(phash, header->basic_cfg.hash, sizeof(header->basic_cfg.hash)); - } -} - -/****************************************************************************/ /** - * @brief release other cpu to boot up - * - * @param core: core number - * @param boot_addr: boot address - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION hal_boot2_release_cpu(uint32_t core, uint32_t boot_addr) -{ - GLB_Set_CPU_Reset_Address(core, boot_addr); - GLB_Release_CPU(core); -} - -/****************************************************************************/ /** - * @brief get xip address according to flash addr - * - * @param flash_addr: flash address - * - * @return XIP Address - * -*******************************************************************************/ -uint32_t hal_boot2_get_xip_addr(uint32_t flash_addr) -{ - uint32_t img_offset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - if (flash_addr >= img_offset) { - return BL808_FLASH_XIP_BASE + (flash_addr - img_offset); - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief get if multi-group - * - * @param None - * - * @return 1 for multi-group 0 for not - * -*******************************************************************************/ -uint32_t hal_boot2_get_grp_count(void) -{ - return 2; -} - -/****************************************************************************/ /** - * @brief get cpu count - * - * @param None - * - * @return 1 for multi-group 0 for not - * -*******************************************************************************/ -uint32_t hal_boot2_get_cpu_count(void) -{ - return 3; -} - -/****************************************************************************/ /** - * @brief get cpu count - * - * @param None - * - * @return 1 for multi-group 0 for not - * -*******************************************************************************/ -uint32_t ATTR_TCM_SECTION hal_boot2_get_feature_flag(void) -{ - return HAL_BOOT2_MP_FLAG; -} - -/****************************************************************************/ /** - * @brief get boot header offset - * - * @param None - * - * @return bootheader offset - * -*******************************************************************************/ -uint32_t hal_boot2_get_bootheader_offset(void) -{ - return 0x0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_clock.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_clock.c deleted file mode 100644 index e5faf33475..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_clock.c +++ /dev/null @@ -1,305 +0,0 @@ -/** - * @file hal_clock.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "bl808_glb.h" -#include "hal_clock.h" - -static void peripheral_clock_gate_all() -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpVal &= (~(1 << 2)); //gpip - tmpVal &= (~(1 << 3)); //sec_dbg - tmpVal &= (~(1 << 4)); //sec_eng - tmpVal &= (~(1 << 5)); //sec_eng - tmpVal &= (~(1 << 12)); //dma - tmpVal &= (~(1 << 13)); //usb - tmpVal &= (~(1 << 16)); //uart0 - tmpVal &= (~(1 << 17)); //uart1 - tmpVal &= (~(1 << 18)); //spi - tmpVal &= (~(1 << 19)); //i2c - tmpVal &= (~(1 << 20)); //pwm - tmpVal &= (~(1 << 21)); //timer - tmpVal &= (~(1 << 22)); //ir - tmpVal &= (~(1 << 23)); //cks - tmpVal &= (~(1 << 25)); //i2c1 - tmpVal &= (~(1 << 26)); //uart2 - tmpVal &= (~(1 << 27)); //i2s - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - tmpVal &= (~(1 << 4)); //wifi - tmpVal &= (~(1 << 8)); //bt/ble - tmpVal &= (~(1 << 9)); //m154 - tmpVal &= (~(1 << 10)); //bt/ble - tmpVal &= (~(1 << 11)); //m154 - tmpVal &= (~(1 << 19)); //emac - //tmpVal &= (~(1 << 21)); //audio - tmpVal &= (~(1 << 22)); //sdh - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal); -} - -void system_clock_init(void) -{ - GLB_Power_On_XTAL_And_PLL_CLK(XTAL_TYPE, GLB_PLL_WIFIPLL | - GLB_PLL_CPUPLL | - GLB_PLL_UHSPLL | - GLB_PLL_MIPIPLL); - -#if BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK -#if XTAL_TYPE == INTERNAL_RC_32M - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); -#else - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_XTAL); -#endif -#elif BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_WIFIPLL_240M - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_240M); -#elif BSP_ROOT_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_WIFIPLL_320M - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M); -#else -#error "do not support current root clock source" -#endif - GLB_Set_MCU_System_CLK_Div(BSP_HCLK_DIV, BSP_BCLK_DIV, BSP_LPCLK_DIV); -#if BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_WIFIPLL_160M - GLB_Set_MCU_Muxpll_160M_Sel(0); -#elif BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_CPUPLL_160M - GLB_Set_MCU_Muxpll_160M_Sel(1); -#elif BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_AUPLL_DIV2 - GLB_Set_MCU_Muxpll_160M_Sel(2); -#elif BSP_CLOCK_SOURCE_MUXPLL_160M == ROOT_CLOCK_SOURCE_AUPLL_DIV2P5 - GLB_Set_MCU_Muxpll_160M_Sel(3); -#else -#error "do not support current muxpll 160m clock source" -#endif - -#if BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_WIFIPLL_80M - GLB_Set_MCU_Muxpll_80M_Sel(0); -#elif BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_CPUPLL_80M - GLB_Set_MCU_Muxpll_80M_Sel(1); -#elif BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_AUPLL_DIV5 - GLB_Set_MCU_Muxpll_80M_Sel(2); -#elif BSP_CLOCK_SOURCE_MUXPLL_80M == ROOT_CLOCK_SOURCE_AUPLL_DIV6 - GLB_Set_MCU_Muxpll_80M_Sel(3); -#else -#error "do not support current muxpll 80m clock source" -#endif - - GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M); - - CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1); -} - -void peripheral_clock_init(void) -{ - uint32_t tmpVal; - - peripheral_clock_gate_all(); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); -#if defined(BSP_USING_UART0) || defined(BSP_USING_UART1) || defined(BSP_USING_UART2) -#if defined(BSP_USING_UART0) - tmpVal |= (1 << 16); -#endif -#if defined(BSP_USING_UART1) - tmpVal |= (1 << 17); -#endif -#if defined(BSP_USING_UART2) - tmpVal |= (1 << 26); -#endif - -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_MCU_PBCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, BSP_UART_CLOCK_DIV); -#else -#error "do not support current uart clock source" -#endif -#endif - -#if defined(BSP_USING_UART3) -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_PBCLK, BSP_UART_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_MUXPLL_160M, BSP_UART_CLOCK_DIV); -#else -#error "do not support current uart clock source" -#endif -#endif - -#if defined(BSP_USING_I2C0) || defined(BSP_USING_I2C1) -#if defined(BSP_USING_I2C0) - tmpVal |= (1 << 19); -#elif defined(BSP_USING_I2C1) - tmpVal |= (1 << 25); -#endif - -#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, BSP_I2C_CLOCK_DIV); -#elif BSP_I2C_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_BCLK, BSP_I2C_CLOCK_DIV); -#else -#error "do not support current i2c clock source" -#endif -#endif - -#if defined(BSP_USING_I2C2) -#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_I2C0_CLK(ENABLE, GLB_I2C_CLK_XCLK, BSP_I2C_CLOCK_DIV); -#elif BSP_I2C_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_DSP_I2C0_CLK(ENABLE, GLB_I2C_CLK_BCLK, BSP_I2C_CLOCK_DIV); -#else -#error "do not support current i2c clock source" -#endif -#endif - -#if defined(BSP_USING_I2C3) -#if BSP_I2C_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_I2C1_CLK(ENABLE, GLB_I2C_CLK_XCLK, BSP_I2C_CLOCK_DIV); -#elif BSP_I2C_CLOCK_SOURCE == BSP_CLOCK_SOURCE_BCLK - GLB_Set_DSP_I2C1_CLK(ENABLE, GLB_I2C_CLK_BCLK, BSP_I2C_CLOCK_DIV); -#else -#error "do not support current i2c clock source" -#endif -#endif - -#if defined(BSP_USING_SPI0) - tmpVal |= (1 << 18); -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_XCLK, BSP_SPI_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, BSP_SPI_CLOCK_DIV); -#else -#error "do not support current spi clock source" -#endif -#endif - -#if defined(BSP_USING_SPI1) -#if BSP_UART_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_XCLK, BSP_SPI_CLOCK_DIV); -#elif BSP_UART_CLOCK_SOURCE == BSP_CLOCK_SOURCE_MUXPLL_160M - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, BSP_SPI_CLOCK_DIV); -#else -#error "do not support current spi clock source" -#endif -#endif - -#if defined(BSP_USING_ADC0) - tmpVal |= (1 << 2); -#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_AUPLL_CLK - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_AUPLL, BSP_ADC_CLOCK_DIV); -#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, BSP_ADC_CLOCK_DIV); -#else -#error "do not support current adc clock source" -#endif -#endif - -#if defined(BSP_USING_DAC0) - tmpVal |= (1 << 2); -#if BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_WIFIPLL_32M - //GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_32M, BSP_DAC_CLOCK_DIV); -#elif BSP_ADC_CLOCK_SOURCE == ROOT_CLOCK_SOURCE_XCLK - //GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, BSP_DAC_CLOCK_DIV); -#else -#error "do not support current dac clock source" -#endif -#endif - -#if defined(BSP_USING_USB) - tmpVal |= (1 << 13); - GLB_Set_USB_CLK_From_WIFIPLL(1); -#endif -#if defined(BSP_USING_SDH) - uint32_t tmp_val; - tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5); - uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN); - tmp_val2 &= ~(1 << 0); - tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2); - BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val); - - GLB_Set_SDH_CLK(1, GLB_SDH_CLK_WIFIPLL_96M, 0); - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SDH); - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH); -#endif - tmpVal |= (1 << 12); //enable dma - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal); - - GLB_Set_DSP_DSP2_CLK(1, GLB_DSP_DSP2_CLK_CPUPLL_400M, 0); -} - -uint32_t system_clock_get(enum system_clock_type type) -{ - switch (type) { - case SYSTEM_CLOCK_ROOT_CLOCK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_ROOT_CLK); - - case SYSTEM_CLOCK_FCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); - - case SYSTEM_CLOCK_BCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_BCLK); - - case SYSTEM_CLOCK_XCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK); - - case SYSTEM_CLOCK_DSP_CLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK); - - case SYSTEM_CLOCK_DSP_BCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_BCLK); - - case SYSTEM_CLOCK_DSP_PBCLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK); - - case SYSTEM_CLOCK_LP_CLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK); - - case SYSTEM_CLOCK_32K_CLK: - return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_F32K); - - default: - break; - } - return 0; -} - -uint32_t peripheral_clock_get(enum peripheral_clock_type type) -{ - return 0; -} - -void system_mtimer_clock_init(void) -{ - CPU_Reset_MTimer(); - /* set mtimer clock 1M */ - CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000000); -} - -void system_mtimer_clock_reinit(void) -{ - /* ToDo */ -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_common.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_common.c deleted file mode 100644 index 2085fa0287..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_common.c +++ /dev/null @@ -1,141 +0,0 @@ -/** - * @file hal_common.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_common.h" -#include "bl808_l1c.h" -#include "bl808_glb.h" -#include "bl808_hbn.h" - -volatile uint32_t nesting = 0; - -void ATTR_TCM_SECTION cpu_global_irq_enable(void) -{ - nesting--; - if (nesting == 0) { - __enable_irq(); - } -} - -void ATTR_TCM_SECTION cpu_global_irq_disable(void) -{ - __disable_irq(); - nesting++; -} - -void hal_por_reset(void) -{ - GLB_SW_POR_Reset(); -} - -void hal_system_reset(void) -{ - GLB_SW_System_Reset(); -} - -void hal_cpu_reset(void) -{ - GLB_SW_CPU_Reset(); -} - -void hal_reboot_config(hal_reboot_cfg_t rbot) -{ - switch(rbot){ - case HAL_REBOOT_AS_BOOTPIN: - HBN_Set_Hand_Off_Config(0); - break; - case HAL_REBOOT_FROM_INTERFACE: - HBN_Set_Hand_Off_Config(1); - break; - case HAL_REBOOT_FROM_MEDIA: - HBN_Set_Hand_Off_Config(2); - break; - default : - HBN_Set_Hand_Off_Config(0); - break; - } -} - -void ATTR_TCM_SECTION hal_dcache_clean_all(void) -{ - L1C_DCache_Clean_All(); -} - -void ATTR_TCM_SECTION hal_dcache_invalid_all(void) -{ - L1C_DCache_Invalid_All(); -} - -void ATTR_TCM_SECTION hal_dcache_clean_invalid_all(void) -{ - L1C_DCache_Clean_Invalid_All(); -} - -void ATTR_TCM_SECTION hal_dcache_clean_byaddr(uintptr_t addr, uint32_t len) -{ - int64_t op_size = len + (uint64_t)addr % 32; - uint64_t op_addr = (uint64_t)addr & CACHE_INV_ADDR_Msk; - int64_t linesize = 32; - - __DSB(); - - while (op_size > 0) { - __DCACHE_CPA(op_addr); - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); -} - -void ATTR_TCM_SECTION hal_dcache_invalidate_byaddr(uintptr_t addr, uint32_t len) -{ - int64_t op_size = len + (uint64_t)addr % 32; - uint64_t op_addr = (uint64_t)addr; - int64_t linesize = 32; - - __DSB(); - - while (op_size > 0) { - __DCACHE_IPA(op_addr); - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); -} - -void ATTR_TCM_SECTION hal_dcache_clean_invalidate_byaddr(uintptr_t addr, uint32_t len) -{ - int64_t op_size = len + (uint64_t)addr % 32; - uint64_t op_addr = (uint64_t)addr; - int64_t linesize = 32; - - __DSB(); - - while (op_size > 0) { - __DCACHE_CIPA(op_addr); - op_addr += linesize; - op_size -= linesize; - } - - __DSB(); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dac.c deleted file mode 100644 index 1f97804753..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dac.c +++ /dev/null @@ -1,324 +0,0 @@ -/** - * @file hal_dac.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_dac.h" -#include "hal_dma.h" -#include "bl808_dac.h" -#include "bl808_glb.h" -#include "dac_config.h" - -static dac_device_t dacx_device[] = { -#ifdef BSP_USING_DAC0 - DAC_CONFIG, -#endif -}; - -static uint8_t dac_channel_enable_check = 0; -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int dac_open(struct device *dev, uint16_t oflag) -{ - dac_device_t *dac_device = (dac_device_t *)dev; - uint8_t dac_div = 0; - uint32_t tmpVal; - - uint32_t dac_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_DAC); - - if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_11) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_0)) { - dac_channel_enable_check |= DAC_CHANNEL_0; - } - if ((GLB_GPIO_Get_Fun(GLB_GPIO_PIN_17) == GPIO_FUN_ANALOG) && (dac_device->channels & DAC_CHANNEL_1)) { - dac_channel_enable_check |= DAC_CHANNEL_1; - } - - if (dac_channel_enable_check == 0) { - return -1; - } - - switch (dac_device->sample_freq) { - case DAC_SAMPLE_FREQ_500KHZ: - dac_div = dac_clk / 500000; - break; - - case DAC_SAMPLE_FREQ_8KHZ: - dac_div = dac_clk / 8000; - break; - - case DAC_SAMPLE_FREQ_16KHZ: - dac_div = dac_clk / 16000; - break; - - case DAC_SAMPLE_FREQ_44P1KHZ: - dac_div = dac_clk / 441000; - break; - - default: - break; - } - - if (dac_div == 1) { - dac_div = DAC_CLK_DIV_1; - } else if (dac_div == 16) { - dac_div = DAC_CLK_DIV_16; - } else if (dac_div == 32) { - dac_div = DAC_CLK_DIV_32; - } else if (dac_div == 64) { - dac_div = DAC_CLK_DIV_64; - } else - return -2; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0); - /*dac vref select*/ - if (dac_device->vref == DAC_VREF_EXTERNAL) { - if (GLB_GPIO_Get_Fun(GLB_GPIO_PIN_7) != GPIO_FUN_ANALOG) - return -1; - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDAC_REF_SEL); - } - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - - /*dac reset*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - /* dac clear reset */ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - - /* Set DAC div */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, dac_div); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_REG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_REG); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable or disable channel */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GLB enable or disable channel */ - if (dac_channel_enable_check & DAC_CHANNEL_0) { - /* a channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOA_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_A_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_RNG, DAC_REF_RNG_DEFAULT_SELECT); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal); - } - if (dac_channel_enable_check & DAC_CHANNEL_1) { - /* b channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_RNG, DAC_REF_RNG_DEFAULT_SELECT); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_IOB_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDAC_B_EN); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal); - } - - /* GPIP disable DMA */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); - - if (oflag & DEVICE_OFLAG_DMA_TX) { - /* GPIP select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, GPIP_DAC_ChanA_SRC_DMA); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, GPIP_DAC_ChanB_SRC_DMA); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable DMA */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - if (dac_channel_enable_check == 2) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, GPIP_DAC_DMA_FORMAT_0); - } - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); - } - - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int dac_close(struct device *dev) -{ - GLB_GPIP_DAC_ChanA_Cfg_Type chCfg = { 0 }; - GLB_GPIP_DAC_Cfg_Type dacCfg = { 0 }; - GLB_GPIP_DAC_Init(&dacCfg); - GLB_GPIP_DAC_Set_ChanA_Config(&chCfg); - GLB_GPIP_DAC_Set_ChanB_Config((GLB_GPIP_DAC_ChanB_Cfg_Type *)&chCfg); - GPIP_Set_DAC_DMA_TX_Disable(); - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int dac_control(struct device *dev, int cmd, void *args) -{ - dac_device_t *dac_device = (dac_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - - break; - - case DEVICE_CTRL_CLR_INT: - - break; - - case DEVICE_CTRL_GET_INT: - - break; - - case DEVICE_CTRL_CONFIG: - - break; - - case DEVICE_CTRL_RESUME: - - break; - - case DEVICE_CTRL_SUSPEND: - - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - dac_device->tx_dma = (struct device *)args; - break; - - default: - break; - } - - return 0; -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int dac_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - int ret = 0; - enum dac_sample_frequence channel = (enum dac_sample_frequence)pos; - dac_device_t *dac_device = (dac_device_t *)dev; - uint32_t i = 0; - - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)dac_device->tx_dma; - - if (!dma_ch) { - return -1; - } - - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_DAC_TDR, size); - dma_channel_start(dma_ch); - return ret; - } else if (dev->oflag & DEVICE_OFLAG_STREAM_TX) { - if (channel & DAC_CHANNEL_ALL) { - for (i = 0; i < size; i++) { - GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); - GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); - } - } else if (channel & DAC_CHANNEL_0) { - for (i = 0; i < size; i++) { - GLB_DAC_Set_ChanA_Value(*((uint16_t *)buffer + i)); - } - } else if (channel & DAC_CHANNEL_1) { - for (i = 0; i < size; i++) { - GLB_DAC_Set_ChanB_Value(*((uint16_t *)buffer + i)); - } - } else { - return -1; - } - return 0; - } - - return -1; -} - -/** - * @brief - * - * @param index - * @param name - * @return int - */ -int dac_register(enum dac_index_type index, const char *name) -{ - struct device *dev; - - if (DAC_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(dacx_device[index].parent); - - dev->open = dac_open; - dev->close = dac_close; - dev->control = dac_control; - dev->write = dac_write; - dev->read = NULL; - - dev->type = DEVICE_CLASS_DAC; - dev->handle = NULL; - - device_register(dev, name); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dma.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dma.c deleted file mode 100644 index 962226cc0f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dma.c +++ /dev/null @@ -1,562 +0,0 @@ -/** - * ***************************************************************************** - * @file hal_dma.c - * @version 0.1 - * @date 2021-03-01 - * @brief - * ***************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * ***************************************************************************** - */ -#include "hal_dma.h" -#include "bl808_dma.h" - -#define DMA_CHANNEL_BASE(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100) - -__UNUSED__ static const uint32_t dma_channel_base[][8] = { - { - DMA_CHANNEL_BASE(DMA0_BASE, 0), - DMA_CHANNEL_BASE(DMA0_BASE, 1), - DMA_CHANNEL_BASE(DMA0_BASE, 2), - DMA_CHANNEL_BASE(DMA0_BASE, 3), - DMA_CHANNEL_BASE(DMA0_BASE, 4), - DMA_CHANNEL_BASE(DMA0_BASE, 5), - DMA_CHANNEL_BASE(DMA0_BASE, 6), - DMA_CHANNEL_BASE(DMA0_BASE, 7), - }, - { - DMA_CHANNEL_BASE(DMA1_BASE, 0), - DMA_CHANNEL_BASE(DMA1_BASE, 1), - DMA_CHANNEL_BASE(DMA1_BASE, 2), - DMA_CHANNEL_BASE(DMA1_BASE, 3), - DMA_CHANNEL_BASE(DMA1_BASE, 4), - DMA_CHANNEL_BASE(DMA1_BASE, 5), - DMA_CHANNEL_BASE(DMA1_BASE, 6), - DMA_CHANNEL_BASE(DMA1_BASE, 7), - }, - { - DMA_CHANNEL_BASE(DMA2_BASE, 0), - DMA_CHANNEL_BASE(DMA2_BASE, 1), - DMA_CHANNEL_BASE(DMA2_BASE, 2), - DMA_CHANNEL_BASE(DMA2_BASE, 3), - DMA_CHANNEL_BASE(DMA2_BASE, 4), - DMA_CHANNEL_BASE(DMA2_BASE, 5), - DMA_CHANNEL_BASE(DMA2_BASE, 6), - DMA_CHANNEL_BASE(DMA2_BASE, 7), - } - -}; - -void DMA0_IRQ(void); -void DMA1_IRQ(void); -void (*p_dma2_chn_irq[])(void); - -dma_device_t dmax_device[DMA_MAX_INDEX] = { -#ifdef BSP_USING_DMA0_CH0 - DMA0_CH0_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH1 - DMA0_CH1_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH2 - DMA0_CH2_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH3 - DMA0_CH3_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH4 - DMA0_CH4_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH5 - DMA0_CH5_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH6 - DMA0_CH6_CONFIG, -#endif -#ifdef BSP_USING_DMA0_CH7 - DMA0_CH7_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH0 - DMA1_CH0_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH1 - DMA1_CH1_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH2 - DMA1_CH2_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH3 - DMA1_CH3_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH4 - DMA1_CH4_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH5 - DMA1_CH5_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH6 - DMA1_CH6_CONFIG, -#endif -#ifdef BSP_USING_DMA1_CH7 - DMA1_CH7_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH0 - DMA2_CH0_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH1 - DMA2_CH1_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH2 - DMA2_CH2_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH3 - DMA2_CH3_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH4 - DMA2_CH4_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH5 - DMA2_CH5_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH6 - DMA2_CH6_CONFIG, -#endif -#ifdef BSP_USING_DMA2_CH7 - DMA2_CH7_CONFIG, -#endif -}; -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int dma_open(struct device *dev, uint16_t oflag) -{ -#ifdef BSP_USING_DMA - dma_device_t *dma_device = (dma_device_t *)dev; - DMA_Channel_Cfg_Type chCfg = { 0 }; - - /* Disable all interrupt */ - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_ALL, MASK); - - /* disable cpu dma interrupt*/ - switch (dma_device->id) - { - case 0: - CPU_Interrupt_Disable(DMA0_ALL_IRQn); - break; - case 1: - CPU_Interrupt_Disable(DMA1_ALL_IRQn); - break; - case 2: - CPU_Interrupt_Disable(DMA2_INT0_IRQn + dma_device->ch); - break; - - default: - return 1; - } - - DMA_Disable(dma_device->id); - - DMA_Channel_Disable(dma_device->id, dma_device->ch); - - chCfg.ch = dma_device->ch; - chCfg.dir = dma_device->direction; - chCfg.srcPeriph = dma_device->src_req; - chCfg.dstPeriph = dma_device->dst_req; - chCfg.srcAddrInc = dma_device->src_addr_inc; - chCfg.destAddrInc = dma_device->dst_addr_inc; - chCfg.srcBurstSize = dma_device->src_burst_size; - chCfg.dstBurstSize = dma_device->dst_burst_size; - chCfg.srcTransfWidth = dma_device->src_width; - chCfg.dstTransfWidth = dma_device->dst_width; - DMA_Channel_Init(dma_device->id, &chCfg); - - DMA_Enable(dma_device->id); - if (dma_device->id == 0) { - Interrupt_Handler_Register(DMA0_ALL_IRQn, DMA0_IRQ); - /* Enable dma interrupt*/ - CPU_Interrupt_Enable(DMA0_ALL_IRQn); - } else if (dma_device->id == 1) { - Interrupt_Handler_Register(DMA1_ALL_IRQn, DMA1_IRQ); - /* Enable dma interrupt*/ - CPU_Interrupt_Enable(DMA1_ALL_IRQn); - } else if(dma_device->id == 2) { - Interrupt_Handler_Register(DMA2_INT0_IRQn + dma_device->ch, p_dma2_chn_irq[dma_device->ch]); - /* Enable dma interrupt*/ - CPU_Interrupt_Enable(DMA2_INT0_IRQn + dma_device->ch); - } -#endif - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int dma_control(struct device *dev, int cmd, void *args) -{ -#ifdef BSP_USING_DMA - dma_device_t *dma_device = (dma_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_TCOMPLETED, UNMASK); - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_ERR, UNMASK); - break; - - case DEVICE_CTRL_CLR_INT: - /* Dma interrupt configuration */ - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_TCOMPLETED, MASK); - DMA_IntMask(dma_device->id, dma_device->ch, DMA_INT_ERR, MASK); - break; - - case DEVICE_CTRL_GET_INT: - break; - - case DEVICE_CTRL_CONFIG: - break; - - case DEVICE_CTRL_DMA_CHANNEL_UPDATE: - DMA_LLI_Update(dma_device->id, dma_device->ch, (uint32_t)(uintptr_t)args); - break; - - case DEVICE_CTRL_DMA_CHANNEL_GET_STATUS: - return DMA_Channel_Is_Busy(dma_device->id, dma_device->ch); - - case DEVICE_CTRL_DMA_CHANNEL_START: - DMA_Channel_Enable(dma_device->id, dma_device->ch); - break; - - case DEVICE_CTRL_DMA_CHANNEL_STOP: - DMA_Channel_Disable(dma_device->id, dma_device->ch); - break; - case DEVICE_CTRL_DMA_CONFIG_SI: { - uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, ((uint32_t)(uintptr_t)args) & 0x01); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal); - - } break; - case DEVICE_CTRL_DMA_CONFIG_DI: { - uint32_t tmpVal = BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, ((uint32_t)(uintptr_t)args) & 0x01); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, tmpVal); - - } break; - default: - break; - } -#endif - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int dma_close(struct device *dev) -{ -#ifdef BSP_USING_DMA - dma_device_t *dma_device = (dma_device_t *)dev; - DMA_Channel_Cfg_Type chCfg = { 0 }; - chCfg.ch = dma_device->ch; - - DMA_Channel_Disable(dma_device->id, dma_device->ch); - DMA_Channel_Init(dma_device->id, &chCfg); -#endif - return 0; -} - -int dma_register(enum dma_index_type index, const char *name) -{ -#ifdef BSP_USING_DMA - struct device *dev; - - if (DMA_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(dmax_device[index].parent); - - dev->open = dma_open; - dev->close = dma_close; - dev->control = dma_control; - // dev->write = dma_write; - // dev->read = dma_read; - - dev->type = DEVICE_CLASS_DMA; - dev->handle = NULL; - - return device_register(dev, name); -#else - return 0; -#endif -} -/** - * @brief - * - * @param dev - * @param src_addr - * @param dst_addr - * @param transfer_size - * @return int - */ -int dma_reload(struct device *dev, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_size) -{ -#ifdef BSP_USING_DMA - uint32_t malloc_count; - uint32_t remain_len; - uint32_t actual_transfer_len = 0; - uint32_t actual_transfer_offset = 0; - dma_control_data_t dma_ctrl_cfg; - - dma_device_t *dma_device = (dma_device_t *)dev; - - DMA_Channel_Disable(dma_device->id, dma_device->ch); - - if (transfer_size == 0) { - return 0; - } - - switch (dma_device->src_width) { - case DMA_TRANSFER_WIDTH_8BIT: - actual_transfer_offset = 4064; - actual_transfer_len = transfer_size; - break; - case DMA_TRANSFER_WIDTH_16BIT: - if (transfer_size % 2) { - return -1; - } - actual_transfer_offset = 4064 << 1; - actual_transfer_len = transfer_size >> 1; - break; - case DMA_TRANSFER_WIDTH_32BIT: - if (transfer_size % 4) { - return -1; - } - actual_transfer_offset = 4064 << 2; - actual_transfer_len = transfer_size >> 2; - break; - - default: - return -3; - break; - } - - dma_ctrl_cfg = (dma_control_data_t)(BL_RD_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL)); - - malloc_count = actual_transfer_len / 4064 + 1; - remain_len = actual_transfer_len % 4064; - - /* The maximum transfer capacity of the last node is 4095 */ - if(malloc_count > 1 && remain_len < (4095 - 4064)){ - malloc_count --; - remain_len += 4064; - } - - dma_device->lli_cfg = (dma_lli_ctrl_t *)realloc(dma_device->lli_cfg, sizeof(dma_lli_ctrl_t) * malloc_count); - - if (dma_device->lli_cfg) { - dma_ctrl_cfg.bits.TransferSize = 4064; - dma_ctrl_cfg.bits.I = 0; - /*transfer_size will be integer multiple of 4064*n or 4064*2*n or 4064*4*n,(n>0) */ - for (uint32_t i = 0; i < malloc_count; i++) { - dma_device->lli_cfg[i].src_addr = src_addr; - dma_device->lli_cfg[i].dst_addr = dst_addr; - dma_device->lli_cfg[i].nextlli = 0; - - if (dma_ctrl_cfg.bits.SI) { - src_addr += actual_transfer_offset; - } - - if (dma_ctrl_cfg.bits.DI) { - dst_addr += actual_transfer_offset; - } - - if (i == malloc_count - 1) { - dma_ctrl_cfg.bits.TransferSize = remain_len; - dma_ctrl_cfg.bits.I = 1; - - if (dma_device->transfer_mode == DMA_LLI_CYCLE_MODE) { - dma_device->lli_cfg[i].nextlli = (uint32_t)(uintptr_t)&dma_device->lli_cfg[0]; - } - } - - if (i) { - dma_device->lli_cfg[i - 1].nextlli = (uint32_t)(uintptr_t)&dma_device->lli_cfg[i]; - } - - dma_device->lli_cfg[i].cfg = dma_ctrl_cfg; - } - /* clean cache, DMA does not pass through the cache */ - csi_dcache_clean_range((void*)(dma_device->lli_cfg), sizeof(dma_lli_ctrl_t) * malloc_count); - - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_SRCADDR, dma_device->lli_cfg[0].src_addr); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_DSTADDR, dma_device->lli_cfg[0].dst_addr); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_LLI, dma_device->lli_cfg[0].nextlli); - BL_WR_REG(dma_channel_base[dma_device->id][dma_device->ch], DMA_CONTROL, dma_device->lli_cfg[0].cfg.WORD); - } else { - return -2; - } -#endif - return 0; -} - -/** - * @brief - * - * @param handle - */ -void dma_channel_isr(dma_device_t *handle) -{ -#ifdef BSP_USING_DMA - uint32_t tmpVal; - uint32_t intClr; - const uint32_t dmaAddr[] = { DMA0_BASE, DMA1_BASE, DMA2_BASE }; - - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[handle->id]; - - if (!handle->parent.callback) { - return; - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << handle->ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << handle->ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_TCOMPLETED); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << handle->ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << handle->ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - handle->parent.callback(&handle->parent, NULL, 0, DMA_INT_ERR); - } -#endif -} - -/** - * @brief - * - */ -void DMA0_IRQ(void) -{ - for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { - if (dmax_device[i].id == 0) { - dma_channel_isr(&dmax_device[i]); - } - } -} - -/** - * @brief - * - */ -void DMA1_IRQ(void) -{ - for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { - if (dmax_device[i].id == 1) { - dma_channel_isr(&dmax_device[i]); - } - } -} - -/** - * @brief - * - */ -void dma2_common_irq(uint8_t ch) -{ - for (uint8_t i = 0; i < DMA_MAX_INDEX; i++) { - if (dmax_device[i].id == 2 && dmax_device[i].ch == ch) { - dma_channel_isr(&dmax_device[i]); - } - } -} - -/** - * @brief - * - */ -void DMA2_CH0_IRQ(void) -{ - dma2_common_irq(0); -} - -void DMA2_CH1_IRQ(void) -{ - dma2_common_irq(1); -} - -void DMA2_CH2_IRQ(void) -{ - dma2_common_irq(2); -} - -void DMA2_CH3_IRQ(void) -{ - dma2_common_irq(3); -} - -void DMA2_CH4_IRQ(void) -{ - dma2_common_irq(4); -} - -void DMA2_CH5_IRQ(void) -{ - dma2_common_irq(5); -} - -void DMA2_CH6_IRQ(void) -{ - dma2_common_irq(6); -} - -void DMA2_CH7_IRQ(void) -{ - dma2_common_irq(7); -} - -void (*p_dma2_chn_irq[])(void) = {DMA2_CH0_IRQ, DMA2_CH1_IRQ, DMA2_CH2_IRQ, DMA2_CH3_IRQ, DMA2_CH4_IRQ, DMA2_CH5_IRQ, DMA2_CH6_IRQ, DMA2_CH7_IRQ}; diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dsi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dsi.c deleted file mode 100644 index e87a5224d9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_dsi.c +++ /dev/null @@ -1,932 +0,0 @@ -/** - * @file hal_dsi.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_dsi.h" -#include "hal_clock.h" -#include "mipi_display.h" -#include "bl808_dsi.h" - -#define ENOSYS 123 -#define EINVAL 124 -#define ENOMEM 125 -#define ENODATA 126 - -/** - * mipi_dsi_packet_format_is_short - check if a packet is of the short format - * @type: MIPI DSI data type of the packet - * - * Return: true if the packet for the given data type is a short packet, false - * otherwise. - */ -bool mipi_dsi_packet_format_is_short(u8 type) -{ - switch (type) { - case MIPI_DSI_V_SYNC_START: - case MIPI_DSI_V_SYNC_END: - case MIPI_DSI_H_SYNC_START: - case MIPI_DSI_H_SYNC_END: - case MIPI_DSI_COMPRESSION_MODE: - case MIPI_DSI_END_OF_TRANSMISSION: - case MIPI_DSI_COLOR_MODE_OFF: - case MIPI_DSI_COLOR_MODE_ON: - case MIPI_DSI_SHUTDOWN_PERIPHERAL: - case MIPI_DSI_TURN_ON_PERIPHERAL: - case MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM: - case MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM: - case MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM: - case MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM: - case MIPI_DSI_DCS_SHORT_WRITE: - case MIPI_DSI_DCS_SHORT_WRITE_PARAM: - case MIPI_DSI_DCS_READ: - case MIPI_DSI_EXECUTE_QUEUE: - case MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE: - return true; - } - - return false; -} - -/** - * mipi_dsi_packet_format_is_long - check if a packet is of the long format - * @type: MIPI DSI data type of the packet - * - * Return: true if the packet for the given data type is a long packet, false - * otherwise. - */ -bool mipi_dsi_packet_format_is_long(u8 type) -{ - switch (type) { - case MIPI_DSI_NULL_PACKET: - case MIPI_DSI_BLANKING_PACKET: - case MIPI_DSI_GENERIC_LONG_WRITE: - case MIPI_DSI_DCS_LONG_WRITE: - case MIPI_DSI_PICTURE_PARAMETER_SET: - case MIPI_DSI_COMPRESSED_PIXEL_STREAM: - case MIPI_DSI_LOOSELY_PACKED_PIXEL_STREAM_YCBCR20: - case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR24: - case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR16: - case MIPI_DSI_PACKED_PIXEL_STREAM_30: - case MIPI_DSI_PACKED_PIXEL_STREAM_36: - case MIPI_DSI_PACKED_PIXEL_STREAM_YCBCR12: - case MIPI_DSI_PACKED_PIXEL_STREAM_16: - case MIPI_DSI_PACKED_PIXEL_STREAM_18: - case MIPI_DSI_PIXEL_STREAM_3BYTE_18: - case MIPI_DSI_PACKED_PIXEL_STREAM_24: - return true; - } - - return false; -} - -/** - * mipi_dsi_controller_init() - Init DSI controller - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_controller_init(const struct mipi_dsi_device *dsi) -{ - DSI_CFG_Type dsiCfg = { - .virtualChan = 0, /*!< DSI virtual channels */ - .laneNum = DSI_LANE_NUMBER_4, /*!< DSI lane numbers */ - .laneOrder = DSI_LANE_ORDER_3210, /*!< DSI lane order */ - .dataType = DSI_DATA_RGB888, /*!< DSI data type */ - .syncType = DSI_HS_SYNC_EVENT_MODE, /*!< HS sync event mode */ - .vsa = 10, /*!< HS vertical sync active width */ - .vfp = 10, /*!< HS vertical front porch width */ - }; - DSI_DPhy_CFG_Type dphyCfg = { - .time_clk_exit = 5, - .time_clk_trail = 3, - .time_clk_zero = 15, - .time_data_exit = 5, - .time_data_prepare = 2, - .time_data_trail = 3, - .time_data_zero = 15, - .time_lpx = 3, - .time_req_ready = 1, - .time_ta_get = 15, - .time_ta_go = 12, - .time_wakeup = 40001, - }; - DSI_Lane_Type usedLanes = DSI_LANE_CLOCK; - - dsiCfg.virtualChan = dsi->channel; - if (dsi->lanes == 1) { - dsiCfg.laneNum = DSI_LANE_NUMBER_1; - } else if(dsi->lanes == 2) { - dsiCfg.laneNum = DSI_LANE_NUMBER_2; - } else { - dsiCfg.laneNum = DSI_LANE_NUMBER_4; - } - dsiCfg.dataType = dsi->format; - - if (dsiCfg.laneNum == DSI_LANE_NUMBER_1) { - usedLanes |= DSI_LANE_DATA0; - } else if (dsiCfg.laneNum == DSI_LANE_NUMBER_2) { - usedLanes |= DSI_LANE_DATA0; - usedLanes |= DSI_LANE_DATA1; - } else if (dsiCfg.laneNum == DSI_LANE_NUMBER_4) { - usedLanes |= DSI_LANE_DATA0; - usedLanes |= DSI_LANE_DATA1; - usedLanes |= DSI_LANE_DATA2; - usedLanes |= DSI_LANE_DATA3; - } - - DSI_Init(DSI0_ID, &dsiCfg); - DSI_PHY_Reset(DSI0_ID); - DSI_PHY_Config(DSI0_ID, &dphyCfg); - DSI_PHY_Enable_Lanes(DSI0_ID, usedLanes); - return 0; -} - -static int mipi_dsi_device_transfer(const struct mipi_dsi_device *dsi, - struct mipi_dsi_msg *msg) -{ - DSI_LPDT_MSG_Type drvMsg = { - .dataType = msg->type, - .flag = msg->flags, /* MIPI_DSI_MSG_REQ_ACK or MIPI_DSI_MSG_USE_LPM*/ - .virtualChan = msg->channel, - .tx_buf = msg->tx_buf, - .tx_len = msg->tx_len, - .rx_buf = msg->rx_buf, - .rx_len = 0, - }; -#if 0 - const struct mipi_dsi_host_ops *ops = dsi->host->ops; - - if(!ops || !ops->transfer) - { - return -ENOSYS; - } - - if(dsi->mode_flags & MIPI_DSI_MODE_LPM) - { - msg->flags |= MIPI_DSI_MSG_USE_LPM; - } - - return ops->transfer(dsi->host, msg); -#endif - - if (mipi_dsi_packet_format_is_short(msg->type)) { - /* short packet */ - if (dsi->mode_flags & MIPI_DSI_MODE_LPM) { - /* use LPDT mode tx */ - if (SUCCESS != DSI_LPDT_Send_Short_Packet(DSI0_ID, &drvMsg)) { - return 0; - } - } else { - return 0; - } - } else { - /* long packet */ - if (dsi->mode_flags & MIPI_DSI_MODE_LPM) { - /* use LPDT mode tx */ - if (SUCCESS != DSI_LPDT_Send_Long_Packet(DSI0_ID, &drvMsg)) { - return 0; - } - } else { - return 0; - } - } - - /* get response */ - if (msg->flags & MIPI_DSI_MSG_REQ_ACK) { - if (dsi->mode_flags & MIPI_DSI_MODE_LPM) { - if (SUCCESS == DSI_LPDT_Recv_Packet(DSI0_ID, &drvMsg)) { - msg->rx_len = drvMsg.rx_len; - return msg->rx_len; - } else { - return 0; - } - } else { - return 0; - } - } - - return msg->tx_len; -} - -/** - * mipi_dsi_create_packet - create a packet from a message according to the - * DSI protocol - * @packet: pointer to a DSI packet structure - * @msg: message to translate into a packet - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_create_packet(struct mipi_dsi_packet *packet, - const struct mipi_dsi_msg *msg) -{ - if (!packet || !msg) { - return -EINVAL; - } - - /* do some minimum sanity checking */ - if (!mipi_dsi_packet_format_is_short(msg->type) && - !mipi_dsi_packet_format_is_long(msg->type)) { - return -EINVAL; - } - - if (msg->channel > 3) { - return -EINVAL; - } - - memset(packet, 0, sizeof(*packet)); - packet->header[0] = ((msg->channel & 0x3) << 6) | (msg->type & 0x3f); - - /* TODO: compute ECC if hardware support is not available */ - - /* - * Long write packets contain the word count in header bytes 1 and 2. - * The payload follows the header and is word count bytes long. - * - * Short write packets encode up to two parameters in header bytes 1 - * and 2. - */ - if (mipi_dsi_packet_format_is_long(msg->type)) { - packet->header[1] = (msg->tx_len >> 0) & 0xff; - packet->header[2] = (msg->tx_len >> 8) & 0xff; - - packet->payload_length = msg->tx_len; - packet->payload = msg->tx_buf; - } else { - const u8 *tx = msg->tx_buf; - - packet->header[1] = (msg->tx_len > 0) ? tx[0] : 0; - packet->header[2] = (msg->tx_len > 1) ? tx[1] : 0; - } - - packet->size = sizeof(packet->header) + packet->payload_length; - - return 0; -} - -/** - * mipi_dsi_shutdown_peripheral() - sends a Shutdown Peripheral command - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_shutdown_peripheral(const struct mipi_dsi_device *dsi) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_SHUTDOWN_PERIPHERAL, - .tx_buf = (u8[2]){ 0, 0 }, - .tx_len = 2, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/* - * mipi_dsi_set_maximum_return_packet_size() - specify the maximum size of the - * the payload in a long packet transmitted from the peripheral back to the - * host processor - * @dsi: DSI peripheral device - * @value: the maximum size of the payload - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_set_maximum_return_packet_size(const struct mipi_dsi_device *dsi, - u16 value) -{ - u8 tx[2] = { value & 0xff, value >> 8 }; - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_SET_MAXIMUM_RETURN_PACKET_SIZE, - .tx_len = sizeof(tx), - .tx_buf = tx, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/** - * mipi_dsi_compression_mode() - enable/disable DSC on the peripheral - * @dsi: DSI peripheral device - * @enable: Whether to enable or disable the DSC - * - * Enable or disable Display Stream Compression on the peripheral using the - * default Picture Parameter Set and VESA DSC 1.1 algorithm. - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_compression_mode(const struct mipi_dsi_device *dsi, bool enable) -{ - /* Note: Needs updating for non-default PPS or algorithm */ - u8 tx[2] = { enable << 0, 0 }; - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_COMPRESSION_MODE, - .tx_len = sizeof(tx), - .tx_buf = tx, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/** - * mipi_dsi_picture_parameter_set() - transmit the DSC PPS to the peripheral - * @dsi: DSI peripheral device - * @pps: VESA DSC 1.1 Picture Parameter Set - * - * Transmit the VESA DSC 1.1 Picture Parameter Set to the peripheral. - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_picture_parameter_set(const struct mipi_dsi_device *dsi, - const struct drm_dsc_picture_parameter_set *pps) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_PICTURE_PARAMETER_SET, - .tx_len = sizeof(*pps), - .tx_buf = pps, - }; - int ret = mipi_dsi_device_transfer(dsi, &msg); - - return (ret < 0) ? ret : 0; -} - -/** - * mipi_dsi_generic_write() - transmit data using a generic write packet - * @dsi: DSI peripheral device - * @payload: buffer containing the payload - * @size: size of payload buffer - * - * This function will automatically choose the right data type depending on - * the payload length. - * - * Return: The number of bytes transmitted on success or a negative error code - * on failure. - */ -int mipi_dsi_generic_write(const struct mipi_dsi_device *dsi, const void *payload, - size_t size) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .tx_buf = payload, - .tx_len = size - }; - - switch (size) { - case 0: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_0_PARAM; - break; - - case 1: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_1_PARAM; - break; - - case 2: - msg.type = MIPI_DSI_GENERIC_SHORT_WRITE_2_PARAM; - break; - - default: - msg.type = MIPI_DSI_GENERIC_LONG_WRITE; - break; - } - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_generic_read() - receive data using a generic read packet - * @dsi: DSI peripheral device - * @params: buffer containing the request parameters - * @num_params: number of request parameters - * @data: buffer in which to return the received data - * @size: size of receive buffer - * - * This function will automatically choose the right data type depending on - * the number of parameters passed in. - * - * Return: The number of bytes successfully read or a negative error code on - * failure. - */ -int mipi_dsi_generic_read(const struct mipi_dsi_device *dsi, const void *params, - size_t num_params, void *data, size_t size) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .tx_len = num_params, - .tx_buf = params, - .rx_len = size, - .rx_buf = data - }; - - switch (num_params) { - case 0: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_0_PARAM; - break; - - case 1: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_1_PARAM; - break; - - case 2: - msg.type = MIPI_DSI_GENERIC_READ_REQUEST_2_PARAM; - break; - - default: - return -EINVAL; - } - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_dcs_write_buffer() - transmit a DCS command with payload - * @dsi: DSI peripheral device - * @data: buffer containing data to be transmitted - * @len: size of transmission buffer - * - * This function will automatically choose the right data type depending on - * the command payload length. - * - * Return: The number of bytes successfully transmitted or a negative error - * code on failure. - */ -int mipi_dsi_dcs_write_buffer(const struct mipi_dsi_device *dsi, - const void *data, size_t len) -{ - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .tx_buf = data, - .tx_len = len - }; - - switch (len) { - case 0: - return -EINVAL; - - case 1: - msg.type = MIPI_DSI_DCS_SHORT_WRITE; - break; - - case 2: - msg.type = MIPI_DSI_DCS_SHORT_WRITE_PARAM; - break; - - default: - msg.type = MIPI_DSI_DCS_LONG_WRITE; - break; - } - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_dcs_write() - send DCS write command - * @dsi: DSI peripheral device - * @cmd: DCS command - * @data: buffer containing the command payload - * @len: command payload length - * - * This function will automatically choose the right data type depending on - * the command payload length. - * - * Return: The number of bytes successfully transmitted or a negative error - * code on failure. - */ -int mipi_dsi_dcs_write(const struct mipi_dsi_device *dsi, u8 cmd, - const void *data, size_t len) -{ - int err; - size_t size; - u8 stack_tx[64]; - u8 *tx; - - size = 1 + len; - - if (len > sizeof(stack_tx) - 1) { - return -ENOMEM; - } else { - tx = stack_tx; - } - - /* concatenate the DCS command byte and the payload */ - tx[0] = cmd; - - if (data) { - memcpy(&tx[1], data, len); - } - - err = mipi_dsi_dcs_write_buffer(dsi, tx, size); - - return err; -} - -/** - * mipi_dsi_dcs_read() - send DCS read request command - * @dsi: DSI peripheral device - * @cmd: DCS command - * @data: buffer in which to receive data - * @len: size of receive buffer - * - * Return: The number of bytes read or a negative error code on failure. - */ -int mipi_dsi_dcs_read(const struct mipi_dsi_device *dsi, u8 cmd, void *data, - size_t len) -{ - u8 wData[2] = {0}; - struct mipi_dsi_msg msg = { - .channel = dsi->channel, - .type = MIPI_DSI_DCS_READ, - .flags = MIPI_DSI_MSG_REQ_ACK, - .tx_buf = wData, - .tx_len = 1, - .rx_buf = data, - .rx_len = len - }; - - wData[0] = cmd; - - return mipi_dsi_device_transfer(dsi, &msg); -} - -/** - * mipi_dsi_dcs_nop() - send DCS nop packet - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_nop(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_NOP, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_soft_reset() - perform a software reset of the display module - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_soft_reset(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SOFT_RESET, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_get_power_mode() - query the display module's current power - * mode - * @dsi: DSI peripheral device - * @mode: return location for the current power mode - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_get_power_mode(const struct mipi_dsi_device *dsi, u8 *mode) -{ - int err; - - err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_POWER_MODE, mode, - sizeof(*mode)); - - if (err <= 0) { - if (err == 0) { - err = -ENODATA; - } - - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_get_pixel_format() - gets the pixel format for the RGB image - * data used by the interface - * @dsi: DSI peripheral device - * @format: return location for the pixel format - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_get_pixel_format(const struct mipi_dsi_device *dsi, u8 *format) -{ - int err; - - err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_PIXEL_FORMAT, format, - sizeof(*format)); - - if (err <= 0) { - if (err == 0) { - err = -ENODATA; - } - - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_enter_sleep_mode() - disable all unnecessary blocks inside the - * display module except interface communication - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_enter_sleep_mode(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_ENTER_SLEEP_MODE, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_exit_sleep_mode() - enable all blocks inside the display - * module - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_exit_sleep_mode(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_EXIT_SLEEP_MODE, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_display_off() - stop displaying the image data on the - * display device - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_display_off(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_OFF, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_display_on() - start displaying the image data on the - * display device - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_display_on(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_ON, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_column_address() - define the column extent of the frame - * memory accessed by the host processor - * @dsi: DSI peripheral device - * @start: first column of frame memory - * @end: last column of frame memory - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_column_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end) -{ - u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_COLUMN_ADDRESS, payload, - sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_page_address() - define the page extent of the frame - * memory accessed by the host processor - * @dsi: DSI peripheral device - * @start: first page of frame memory - * @end: last page of frame memory - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_page_address(const struct mipi_dsi_device *dsi, u16 start, - u16 end) -{ - u8 payload[4] = { start >> 8, start & 0xff, end >> 8, end & 0xff }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PAGE_ADDRESS, payload, - sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_tear_off() - turn off the display module's Tearing Effect - * output signal on the TE signal line - * @dsi: DSI peripheral device - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_tear_off(const struct mipi_dsi_device *dsi) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_OFF, NULL, 0); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_tear_on() - turn on the display module's Tearing Effect - * output signal on the TE signal line. - * @dsi: DSI peripheral device - * @mode: the Tearing Effect Output Line mode - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_tear_on(const struct mipi_dsi_device *dsi, - enum mipi_dsi_dcs_tear_mode mode) -{ - u8 value = mode; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_ON, &value, - sizeof(value)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_pixel_format() - sets the pixel format for the RGB image - * data used by the interface - * @dsi: DSI peripheral device - * @format: pixel format - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_pixel_format(const struct mipi_dsi_device *dsi, u8 format) -{ - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_PIXEL_FORMAT, &format, - sizeof(format)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_tear_scanline() - set the scanline to use as trigger for - * the Tearing Effect output signal of the display module - * @dsi: DSI peripheral device - * @scanline: scanline to use as trigger - * - * Return: 0 on success or a negative error code on failure - */ -int mipi_dsi_dcs_set_tear_scanline(const struct mipi_dsi_device *dsi, u16 scanline) -{ - u8 payload[2] = { scanline >> 8, scanline & 0xff }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_TEAR_SCANLINE, payload, - sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_set_display_brightness() - sets the brightness value of the - * display - * @dsi: DSI peripheral device - * @brightness: brightness value - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_set_display_brightness(const struct mipi_dsi_device *dsi, - u16 brightness) -{ - u8 payload[2] = { brightness & 0xff, brightness >> 8 }; - int err; - - err = mipi_dsi_dcs_write(dsi, MIPI_DCS_SET_DISPLAY_BRIGHTNESS, - payload, sizeof(payload)); - - if (err < 0) { - return err; - } - - return 0; -} - -/** - * mipi_dsi_dcs_get_display_brightness() - gets the current brightness value - * of the display - * @dsi: DSI peripheral device - * @brightness: brightness value - * - * Return: 0 on success or a negative error code on failure. - */ -int mipi_dsi_dcs_get_display_brightness(const struct mipi_dsi_device *dsi, - u16 *brightness) -{ - int err; - - err = mipi_dsi_dcs_read(dsi, MIPI_DCS_GET_DISPLAY_BRIGHTNESS, - brightness, sizeof(*brightness)); - - if (err <= 0) { - if (err == 0) { - err = -ENODATA; - } - - return err; - } - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_emac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_emac.c deleted file mode 100644 index 1ddb0aec41..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_emac.c +++ /dev/null @@ -1,584 +0,0 @@ -/** - * @file hal_emac.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "bl808_emac.h" -#include "bl808_glb.h" -#include "hal_emac.h" - -#define EMAC_USE_INSIDE_CLOCK (0) -#define TAG "EMAC_BD: " -#define EMAC_USED_ID EMAC0_ID - -//#define EMAC_DBG -#ifdef EMAC_DBG -#define MSG printf -#else -#define MSG(...) ((void)0) -#endif -#define EMAC_DO_FLUSH_DATA 1 - -static EMAC_Handle_Type ethHandle; -static EMAC_Handle_Type *thiz = NULL; - -/** - * @brief - * - */ -static void emac_gpio_init(void) -{ - uint8_t emacPins[] = { GLB_GPIO_PIN_24, GLB_GPIO_PIN_25, GLB_GPIO_PIN_26, - GLB_GPIO_PIN_27, GLB_GPIO_PIN_28, GLB_GPIO_PIN_29, - GLB_GPIO_PIN_30, GLB_GPIO_PIN_31, GLB_GPIO_PIN_32, - GLB_GPIO_PIN_33 }; - - GLB_GPIO_Func_Init(GPIO_FUN_ETHER_MAC, (GLB_GPIO_Type *)emacPins, sizeof(emacPins)); -} - -/** - * @brief - * - * @param bdt - * @return int - */ -static uint32_t emac_bd_get_cur_active(EMAC_BD_TYPE_e bdt) -{ - uint32_t bd = 0; - - bd = BL_RD_REG(EMAC_BASE, EMAC_TX_BD_NUM); - - if (bdt == EMAC_BD_TYPE_TX) { - bd &= EMAC_TXBDPTR_MSK; - bd >>= EMAC_TXBDPTR_POS; - } - - if (bdt == EMAC_BD_TYPE_RX) { - bd &= EMAC_RXBDPTR_MSK; - bd >>= EMAC_RXBDPTR_POS; - } - - return bd; -} - -/** - * @brief - * - * @param index - * @return int - */ -static int emac_bd_rx_enqueue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - - thiz->rxIndexEMAC = index; - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_rx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_OR)) { - MSG("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_RE)) { - MSG("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_DN)) { - MSG("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_TL)) { - MSG("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_CRC)) { - MSG("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(RX_LC)) { - MSG("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; - /* RX BD is ready for RX */ - thiz->bd[index].C_S_L |= EMAC_BD_FIELD_MSK(RX_E); -} - -/** - * @brief this func will be called in ISR - * - * @param index - * @return int - */ -static int emac_bd_tx_dequeue(uint32_t index) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - thiz->txIndexEMAC = index; - DMADesc = &thiz->bd[thiz->txIndexEMAC]; - /* release this tx BD to SW (HW will do this) */ - DMADesc->C_S_L &= EMAC_BD_FIELD_UMSK(TX_RD); - - return err; -} - -/** - * @brief - * - * @param index - * @return int - */ -static void emac_bd_tx_on_err(uint32_t index) -{ - /* handle error */ - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_UR)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RTRY)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_RL)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_LC)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_DF)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - if (thiz->bd[index].C_S_L & EMAC_BD_FIELD_MSK(TX_CS)) { - MSG("%s:%d\r\n", __func__, __LINE__); - } - - thiz->bd[index].C_S_L &= ~0xff; -} - -/** - * @brief - * - */ -__WEAK void emac_tx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_tx_done_callback(void) -{ - uint32_t index = 0; - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - - emac_bd_tx_dequeue(index); - - emac_tx_done_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_tx_error_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_tx_error_callback(void) -{ - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_TX); - - emac_bd_tx_on_err(index); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_done_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_done_callback(void) -{ - uint32_t index = 0; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_enqueue(index); - - emac_rx_done_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_error_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_error_callback(void) -{ - uint32_t index; - - index = emac_bd_get_cur_active(EMAC_BD_TYPE_RX); - - emac_bd_rx_on_err(index); - - emac_rx_error_callback_app(); -} - -/** - * @brief - * - */ -__WEAK void emac_rx_busy_callback_app(void) -{ -} - -/** - * @brief - * - */ -static void emac_rx_busy_callback(void) -{ - MSG("EMAC Rx busy at %s:%d\r\n", __func__, __LINE__); - emac_rx_busy_callback_app(); -} - -/** - * @brief - * - * @param emac_cfg - * @return int - */ -int emac_init(emac_device_t *emac_cfg) -{ - EMAC_CFG_Type emacCfg = { - .recvSmallFrame = ENABLE, /*!< Receive small frmae or not */ - .recvHugeFrame = DISABLE, /*!< Receive huge frmae(>64K bytes) or not */ - .padEnable = ENABLE, /*!< Enable padding for frame which is less than MINFL or not */ - .crcEnable = ENABLE, /*!< Enable hardware CRC or not */ - .noPreamble = DISABLE, /*!< Enable preamble or not */ - .recvBroadCast = ENABLE, /*!< Receive broadcast frame or not */ - .interFrameGapCheck = ENABLE, /*!< Check inter frame gap or not */ - .miiNoPreamble = ENABLE, /*!< Enable MII interface preamble or not */ - .miiClkDiv = 49, /*!< MII interface clock divider from bus clock */ - .maxTxRetry = 16, /*!< Maximum tx retry count */ - .interFrameGapValue = 24, /*!< Inter frame gap vaule in clock cycles(default 24)*/ - .minFrameLen = 64, /*!< Minimum frame length */ - .maxFrameLen = ETH_MAX_PACKET_SIZE, /*!< Maximum frame length */ - .collisionValid = 16, /*!< Collision valid value */ - .macAddr[0] = 0x18, /*!< MAC Address */ - .macAddr[1] = 0xB0, - .macAddr[2] = 0x09, - .macAddr[3] = 0x00, - .macAddr[4] = 0x12, - .macAddr[5] = 0x34, - }; - BL_Err_Type err = SUCCESS; - - /* init emac giio */ - emac_gpio_init(); - - memcpy(emacCfg.macAddr, emac_cfg->mac_addr, 6); - GLB_PER_Clock_UnGate(1<<12); -#if EMAC_USE_INSIDE_CLOCK - /* 50MHZ clock is from uhs pll */ - /* Pls make sure uhs pll UHSPLL_EVEN_DIV_EN is 1 */ - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_INSIDE_50M); - GLB_Invert_ETH_REF_O_CLK(0); -#else - GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_OUTSIDE_50M); -#endif - //GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_EMAC); - GLB_PER_Clock_UnGate(1<<12); - //GLB_Invert_ETH_RX_CLK(0); - //GLB_Invert_ETH_TX_CLK(0); - EMAC_Init(EMAC_USED_ID,&emacCfg); - - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_TX_DONE_IDX, emac_tx_done_callback); - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_TX_ERROR_IDX, emac_tx_error_callback); - - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_RX_DONE_IDX, emac_rx_done_callback); - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_RX_ERROR_IDX, emac_rx_error_callback); - - EMAC_Int_Callback_Install(EMAC_USED_ID, EMAC_INT_RX_BUSY_IDX, emac_rx_busy_callback); - - CPU_Interrupt_Enable(EMAC_IRQn); - - EMAC_ClrIntStatus(EMAC_USED_ID,EMAC_INT_ALL); - EMAC_IntMask(EMAC_USED_ID,EMAC_INT_ALL, UNMASK); - - //EMAC_Enable(); - - return err; -} - -/** - * @brief - * - * @param eth_tx_buff - * @param tx_buf_count - * @param eth_rx_buff - * @param rx_buf_count - * @return int - */ -int emac_bd_init(uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count) -{ - BL_Err_Type err = SUCCESS; - thiz = ðHandle; - - /* init the BDs in emac with buffer address */ - err = EMAC_DMADescListInit(EMAC_USED_ID,thiz, (uint8_t *)eth_tx_buff, tx_buf_count, - (uint8_t *)eth_rx_buff, rx_buf_count); - return err; -} - -/** - * @brief - * - * @param none - * @return int - */ -int emac_bd_fragment_support(void){ - return 1; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_in - * @return int - */ -//uint32_t tmpbuf[400]; -int emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - uint32_t tx_flags=EMAC_TX_COMMON_FLAGS; - DMADesc = &thiz->bd[thiz->txIndexCPU]; - - if (flags&EMAC_FRAGMENT_PACKET) { - /* Fragment packet, clear EOF */ - tx_flags &= EMAC_BD_FIELD_UMSK(TX_EOF); - } - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(TX_RD)) { - /* no free BD, lost sync with DMA TX? */ - err = NORESC; - //MSG(TAG"%s:%d\n", __func__, __LINE__); - } else { - __DSB(); - // MSG("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in); - if (flags&EMAC_NOCOPY_PACKET) { - DMADesc->Buffer = (uint32_t)(uintptr_t)data_in; - }else{ - ARCH_MemCpy_Fast((void *)(uintptr_t)(DMADesc->Buffer), data_in, len); - } - - /* following two lines is for cache test since tmpbuf is in cache range */ - //ARCH_MemCpy_Fast(tmpbuf, data_in, len); - //DMADesc->Buffer = (uint32_t)tmpbuf; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Clean_By_Addr((uintptr_t)DMADesc->Buffer,len); - } -#endif - DMADesc->C_S_L = tx_flags | (len << BD_TX_LEN_POS); - - /* move to next TX BD */ - if ((++thiz->txIndexCPU) > thiz->txBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); - /* wrap back */ - thiz->txIndexCPU = 0; - } - } - - return err; -} - -/** - * @brief - * - * @param flags - * @param len - * @param data_out - * @return int - */ -int emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out) -{ - BL_Err_Type err = SUCCESS; - EMAC_BD_Desc_Type *DMADesc; - - DMADesc = &thiz->bd[thiz->rxIndexCPU]; - - if (DMADesc->C_S_L & EMAC_BD_FIELD_MSK(RX_E)) { - /* current RX BD is empty */ - err = NORESC; - *len = 0; - } else { - *len = (thiz->bd[thiz->rxIndexCPU].C_S_L & EMAC_BD_FIELD_MSK(RX_LEN)) >> BD_RX_LEN_POS; -#ifdef EMAC_DO_FLUSH_DATA - if(L1C_Is_DCache_Range((uintptr_t)DMADesc->Buffer)){ - L1C_DCache_Invalid_By_Addr((uintptr_t)DMADesc->Buffer, *len); - } -#endif - if (data_out) { - ARCH_MemCpy_Fast(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len); - } - - /* RX BD can be used for another receive */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_E); - - /* move to next RX BD */ - if ((++thiz->rxIndexCPU) > thiz->rxBuffLimit) { - /* the last BD */ - DMADesc->C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); - /* wrap back */ - thiz->rxIndexCPU = thiz->txBuffLimit + 1; - } - } - - return err; -} - -/** - * @brief - * - * @param phyAddress - * @return int - */ -int emac_phy_set_address(uint16_t phyAddress) -{ - EMAC_Phy_SetAddress(EMAC_USED_ID,phyAddress); - - return 0; -} - -/** - * @brief - * - * @param fullDuplex - * @return int - */ -int emac_phy_config_full_duplex(uint8_t fullDuplex) -{ - EMAC_Phy_Set_Full_Duplex(EMAC_USED_ID,fullDuplex); - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_read(uint16_t phyReg, uint16_t *regValue) -{ - if (EMAC_Phy_Read(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -/** - * @brief - * - * @param phyReg - * @param regValue - * @return int - */ -int emac_phy_reg_write(uint16_t phyReg, uint16_t regValue) -{ - if (EMAC_Phy_Write(EMAC_USED_ID,phyReg, regValue) != SUCCESS) { - return -1; - } - - return 0; -} - -int emac_stop(void) -{ - return EMAC_Disable(EMAC_USED_ID); -} - -int emac_start(void) -{ - EMAC_Enable(EMAC_USED_ID); - return 0; -} - -int emac_start_tx(void) -{ - return EMAC_Enable_TX(EMAC_USED_ID); -} - -int emac_stop_tx(void) -{ - return EMAC_Disable_TX(EMAC_USED_ID); -} - -int emac_start_rx(void) -{ - return EMAC_Enable_RX(EMAC_USED_ID); -} - -int emac_stop_rx(void) -{ - return EMAC_Disable_RX(EMAC_USED_ID); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_flash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_flash.c deleted file mode 100644 index 64bdff924c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_flash.c +++ /dev/null @@ -1,352 +0,0 @@ -/** - * @file hal_flash.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "bl808_glb.h" -#include "bl808_xip_sflash.h" -#include "bl808_sf_cfg.h" -#include "bl808_romapi_patch.h" -#include "hal_flash.h" - -static uint32_t g_jedec_id = 0; -static SPI_Flash_Cfg_Type g_flash_cfg; - -/** - * @brief flash_get_jedecid - * - * @return BL_Err_Type - */ -uint32_t flash_get_jedecid(void) -{ - uint32_t jid = 0; - - jid = ((g_jedec_id&0xff)<<16) + (g_jedec_id&0xff00) + ((g_jedec_id&0xff0000)>>16); - return jid; -} - -/** - * @brief flash_get_cfg - * - * @return BL_Err_Type - */ -BL_Err_Type flash_get_cfg(uint8_t **cfg_addr, uint32_t *len) -{ - *cfg_addr = (uint8_t *)&g_flash_cfg; - *len = sizeof(SPI_Flash_Cfg_Type); - - return SUCCESS; -} - -/** - * @brief flash_get_clock_delay - * - * @return BL_Err_Type - */ -static BL_Err_Type flash_get_clock_delay(SPI_Flash_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - /* bit0-3 for clk delay */ - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN)) { - cfg->clkDelay = BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N)+1; - } else { - cfg->clkDelay = 0; - } - cfg->clkInvert = 0; - /* bit0 for clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL)&1)<<0); - /* bit1 for rx clk invert */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL)&1)<<1); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IO_DLY_1); - /* bit4-6 for do delay */ - cfg->clkDelay |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL)&7)<<4); - /* bit2-4 for di delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL)&7)<<2); - /* bit5-7 for oe delay */ - cfg->clkInvert |= ((BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL)&7)<<5); - - return SUCCESS; -} - -/** - * @brief flash_set_qspi_enable - * - * @return BL_Err_Type - */ -static BL_Err_Type ATTR_TCM_SECTION flash_set_qspi_enable(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_Qspi_Enable(p_flash_cfg); - } - - return SUCCESS; -} - -/** - * @brief flash_set_l1c_wrap - * - * @return BL_Err_Type - */ -static BL_Err_Type ATTR_TCM_SECTION flash_set_l1c_wrap(SPI_Flash_Cfg_Type *p_flash_cfg) -{ - if (((p_flash_cfg->ioMode >> 4) & 0x01) == 1) { - L1C_Set_Wrap(DISABLE); - } else { - L1C_Set_Wrap(ENABLE); - if ((p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(p_flash_cfg); - } - } - - return SUCCESS; -} - -/** - * @brief flash_config_init - * - * @return BL_Err_Type - */ -static BL_Err_Type ATTR_TCM_SECTION flash_config_init(SPI_Flash_Cfg_Type *p_flash_cfg, uint8_t *jedec_id) -{ - BL_Err_Type ret = ERROR; - uint8_t isAesEnable = 0; - uint32_t jid = 0; - uint32_t offset = 0; - - cpu_global_irq_disable(); - XIP_SFlash_Opt_Enter(&isAesEnable); - XIP_SFlash_State_Save(p_flash_cfg, &offset, 0, 0); - SFlash_GetJedecId(p_flash_cfg, (uint8_t *)&jid); - arch_memcpy(jedec_id, (uint8_t *)&jid, 3); - jid &= 0xFFFFFF; - g_jedec_id = jid; - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jid, p_flash_cfg, 0, 0); - if (ret == SUCCESS) { - p_flash_cfg->mid = (jid & 0xff); - } - - /* Set flash controler from p_flash_cfg */ - flash_set_qspi_enable(p_flash_cfg); - flash_set_l1c_wrap(p_flash_cfg); - XIP_SFlash_State_Restore(p_flash_cfg, offset, 0, 0); - XIP_SFlash_Opt_Exit(isAesEnable); - cpu_global_irq_enable(); - - return ret; -} - -/** - * @brief multi flash adapter - * - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_init(void) -{ - BL_Err_Type ret = ERROR; - uint32_t jedec_id = 0; - - jedec_id = GLB_Get_Flash_Id_Value(); - if (jedec_id != 0) { - ret = SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(jedec_id, &g_flash_cfg, 0, 0); - if (ret == SUCCESS) { - g_jedec_id = jedec_id; - flash_get_clock_delay(&g_flash_cfg); - return SUCCESS; - } - } - - cpu_global_irq_disable(); - L1C_ICache_Invalid_All(); - SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(0, &g_flash_cfg, 0, 0); - L1C_ICache_Invalid_All(); - cpu_global_irq_enable(); - if (g_flash_cfg.mid != 0xff) { - flash_get_clock_delay(&g_flash_cfg); - return SUCCESS; - } - - ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id); -#ifdef HAL_FLASH_MSG - MSG("flash ID = %08x\r\n", jedec_id); - bflb_platform_dump((uint8_t *)&g_flash_cfg, sizeof(g_flash_cfg)); - if (ret != SUCCESS) { - MSG("flash config init fail!\r\n"); - } -#endif - flash_get_clock_delay(&g_flash_cfg); - GLB_Set_Flash_Id_Value(g_jedec_id); - - return ret; -} - -/** - * @brief read jedec id - * - * @param data - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_read_jedec_id(uint8_t *data) -{ - uint32_t jid = 0; - - cpu_global_irq_disable(); - XIP_SFlash_GetJedecId_Need_Lock(&g_flash_cfg, (uint8_t *)&jid, 0, 0); - cpu_global_irq_enable(); - jid &= 0xFFFFFF; - arch_memcpy(data, (void *)&jid, 4); - - return SUCCESS; -} - -/** - * @brief read flash data via xip - * - * @param flash xip addr or flash absolute addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_read_via_xip(uint32_t addr, uint8_t *data, uint32_t len) -{ - addr = addr & (BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE-1); - - cpu_global_irq_disable(); - L1C_ICache_Invalid_All(); - XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len, 0, 0); - L1C_ICache_Invalid_All(); - cpu_global_irq_enable(); - - return SUCCESS; -} - -/** - * @brief read flash data via sbus - * - * @param flash absolute addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - - if (addr >= BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE) { - return ERROR; - } - - cpu_global_irq_disable(); - stat = XIP_SFlash_Read_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - cpu_global_irq_enable(); - - return stat; -} - -/** - * @brief write flash data via sbus - * - * @param flash absolute addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat; - - if (addr >= BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE) { - return ERROR; - } - - cpu_global_irq_disable(); - stat = XIP_SFlash_Write_Need_Lock(&g_flash_cfg, addr, data, len, 0, 0); - cpu_global_irq_enable(); - - return stat; -} - -/** - * @brief erase flash via sbus - * - * @param flash absolute startaddr - * @param flash absolute endaddr - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_erase(uint32_t startaddr, uint32_t len) -{ - BL_Err_Type stat; - - if (startaddr >= BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE) { - return ERROR; - } - - cpu_global_irq_disable(); - stat = XIP_SFlash_Erase_Need_Lock(&g_flash_cfg, startaddr, len, 0, 0); - cpu_global_irq_enable(); - - return stat; -} - -/** - * @brief set flash cache - * - * @param cont_read - * @param cache_enable - * @param cache_way_disable - * @param flash_offset - * @return BL_Err_Type - */ -BL_Err_Type ATTR_TCM_SECTION flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset) -{ - uint8_t isAesEnable = 0; - uint32_t tmp[1]; - BL_Err_Type stat; - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - - XIP_SFlash_Opt_Enter(&isAesEnable); - /* To make it simple, exit cont read anyway */ - SFlash_Reset_Continue_Read(&g_flash_cfg); - - if (g_flash_cfg.cReadSupport == 0) { - cont_read = 0; - } - - if (cont_read == 1) { - stat = SFlash_Read(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - - if (SUCCESS != stat) { - XIP_SFlash_Opt_Exit(isAesEnable); - return ERROR; - } - } - - /* TODO: Set default value */ - - SF_Ctrl_Set_Flash_Image_Offset(flash_offset, 0, 0); - SFlash_IDbus_Read_Enable(&g_flash_cfg, g_flash_cfg.ioMode & 0xf, cont_read, SF_CTRL_FLASH_BANK0); - - XIP_SFlash_Opt_Exit(isAesEnable); - - return SUCCESS; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_gpio.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_gpio.c deleted file mode 100644 index 3a0d01171e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_gpio.c +++ /dev/null @@ -1,227 +0,0 @@ -/** - * @file hal_gpio.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "bl808_glb.h" -#include "bl808_gpio.h" -#include "hal_gpio.h" - -static void GPIO_IRQ(void); - -struct gpio_int_cfg_private { - slist_t list; - uint32_t pin; - void (*cbfun)(uint32_t pin); -}; - -static slist_t gpio_int_head = SLIST_OBJECT_INIT(gpio_int_head); - -/** - * @brief - * - * @param pin - * @param mode - */ -void gpio_set_mode(uint32_t pin, uint32_t mode) -{ - GLB_GPIO_Cfg_Type gpio_cfg; - - gpio_cfg.gpioFun = GPIO_FUN_GPIO; - gpio_cfg.gpioPin = pin; - gpio_cfg.drive = 0; - gpio_cfg.smtCtrl = 1; - gpio_cfg.outputMode = 0; - - switch (mode) { - case GPIO_OUTPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_OUTPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_OUTPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_OUTPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - - case GPIO_INPUT_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_NONE; - break; - - case GPIO_INPUT_PP_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_UP; - break; - - case GPIO_INPUT_PD_MODE: - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - gpio_cfg.pullType = GPIO_PULL_DOWN; - break; - case GPIO_HZ_MODE: - GLB_GPIO_Set_HZ(pin); - default: - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - GLB_GPIO_IntMask(pin, MASK); - - GLB_GPIO_INT_Cfg_Type intCfg; - - intCfg.gpioPin = pin; - intCfg.intMask = MASK; - - gpio_cfg.gpioMode = GPIO_MODE_INPUT; - - if (mode == GPIO_ASYNC_RISING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE; - } else if (mode == GPIO_ASYNC_FALLING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE; - } else if (mode == GPIO_ASYNC_HIGH_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL; - } else if (mode == GPIO_ASYNC_LOW_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL; - } else if (mode == GPIO_SYNC_RISING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE; - } else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE; - } else if (mode == GPIO_SYNC_FALLING_TRIGER_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_NONE; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE; - } else if (mode == GPIO_SYNC_HIGH_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_DOWN; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL; - } else if (mode == GPIO_SYNC_LOW_LEVEL_INT_MODE) { - gpio_cfg.pullType = GPIO_PULL_UP; - intCfg.trig = GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL; - } - - GLB_GPIO_Int_Init(&intCfg); - break; - } - - GLB_GPIO_Init(&gpio_cfg); -} -/** - * @brief - * - * @param pin - * @param value - */ -void gpio_write(uint32_t pin, uint32_t value) -{ - GLB_GPIO_Write(pin, value); -} -/** - * @brief - * - * @param pin - */ -void gpio_toggle(uint32_t pin) -{ - uint32_t gpioCfgAddress; - uint32_t tmpVal; - - gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (pin << 2); - tmpVal = BL_RD_WORD(gpioCfgAddress); - - if (BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_O)) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_O); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_O); - } - - BL_WR_WORD(gpioCfgAddress, tmpVal); -} -/** - * @brief - * - * @param pin - * @return int - */ -int gpio_read(uint32_t pin) -{ - return GLB_GPIO_Read(pin); -} -/** - * @brief - * - * @param pin - * @param cbFun - */ -void gpio_attach_irq(uint32_t pin, void (*cbfun)(uint32_t pin)) -{ - struct gpio_int_cfg_private *int_cfg = malloc(sizeof(struct gpio_int_cfg_private)); - int_cfg->cbfun = cbfun; - int_cfg->pin = pin; - slist_add_tail(&gpio_int_head, &int_cfg->list); - CPU_Interrupt_Disable(GPIO_INT0_IRQn); - Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_IRQ); - CPU_Interrupt_Enable(GPIO_INT0_IRQn); -} -/** - * @brief - * - * @param pin - * @param enabled - */ -void gpio_irq_enable(uint32_t pin, uint8_t enabled) -{ - if (enabled) { - GLB_GPIO_IntMask(pin, UNMASK); - } else { - GLB_GPIO_IntMask(pin, MASK); - } -} - -static void GPIO_IRQ(void) -{ - slist_t *i; - uint32_t timeOut = 0; -#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32) - slist_for_each(i, &gpio_int_head) - { - struct gpio_int_cfg_private *int_cfg = slist_entry(i, struct gpio_int_cfg_private, list); - - if (SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) { - int_cfg->cbfun(int_cfg->pin); - GLB_Clr_GPIO_IntStatus(int_cfg->pin); - /* timeout check */ - timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT; - - do { - timeOut--; - } while ((SET == GLB_Get_GPIO_IntStatus(int_cfg->pin)) && timeOut); - - if (!timeOut) { - //MSG("WARNING: Clear GPIO interrupt status fail.\r\n"); - } - } - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2c.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2c.c deleted file mode 100644 index 574acf64f9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2c.c +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file hal_i2c.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_i2c.h" -#include "hal_gpio.h" -#include "bl808_i2c.h" -#include "bl808_glb.h" - -static i2c_device_t i2cx_device[I2C_MAX_INDEX] = { -#ifdef BSP_USING_I2C0 - I2C0_CONFIG, -#endif -#ifdef BSP_USING_I2C1 - I2C1_CONFIG, -#endif -#ifdef BSP_USING_I2C2 - I2C2_CONFIG, -#endif -#ifdef BSP_USING_I2C3 - I2C3_CONFIG, -#endif -}; -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int i2c_open(struct device *dev, uint16_t oflag) -{ - i2c_device_t *i2c_device = (i2c_device_t *)dev; - - if (i2c_device->mode == I2C_HW_MODE) { - I2C_SetPrd(i2c_device->id, i2c_device->phase); - } - - return 0; -} - -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int i2c_register(enum i2c_index_type index, const char *name) -{ - struct device *dev; - - if (I2C_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(i2cx_device[index].parent); - - dev->open = i2c_open; - dev->close = NULL; - dev->control = NULL; - dev->write = NULL; - dev->read = NULL; - - dev->type = DEVICE_CLASS_I2C; - dev->handle = NULL; - - return device_register(dev, name); -} -/** - * @brief - * - * @param dev - * @param msgs - * @param num - * @return uint32_t - */ -int i2c_transfer(struct device *dev, i2c_msg_t msgs[], uint32_t num) -{ - i2c_msg_t *msg; - I2C_Transfer_Cfg i2cCfg = { 0 }; - - i2c_device_t *i2c_device = (i2c_device_t *)dev; - - if (i2c_device->mode == I2C_HW_MODE) { - for (uint32_t i = 0; i < num; i++) { - msg = &msgs[i]; - i2cCfg.slaveAddr = msg->slaveaddr; - i2cCfg.stopEveryByte = DISABLE; - i2cCfg.subAddr = msg->subaddr; - i2cCfg.dataSize = msg->len; - i2cCfg.data = msg->buf; - - if (msg->flags & SUB_ADDR_0BYTE) { - i2cCfg.subAddrSize = 0; - } else if (msg->flags & SUB_ADDR_1BYTE) { - i2cCfg.subAddrSize = 1; - } else if (msg->flags & SUB_ADDR_2BYTE) { - i2cCfg.subAddrSize = 2; - } - - if ((msg->flags & I2C_RW_MASK) == I2C_WR) { - return I2C_MasterSendBlocking(i2c_device->id, &i2cCfg); - } else if ((msg->flags & I2C_RW_MASK) == I2C_RD) { - return I2C_MasterReceiveBlocking(i2c_device->id, &i2cCfg); - } - } - } else { - } - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2s.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2s.c deleted file mode 100644 index 549fc1363d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_i2s.c +++ /dev/null @@ -1,352 +0,0 @@ -/** - * @file hal_i2s.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_i2s.h" -#include "hal_clock.h" -#include "hal_dma.h" -#include "bl808_i2s.h" -#include "bl808_glb.h" -#include "i2s_config.h" - -static i2s_device_t i2sx_device[I2S_MAX_INDEX] = { -#ifdef BSP_USING_I2S0 - I2S0_CONFIG, -#endif -}; - -int i2s_open(struct device *dev, uint16_t oflag) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - I2S_CFG_Type i2sCfg = { 0 }; - I2S_FifoCfg_Type fifoCfg = { 0 }; - - /* todo unify clock configuretion */ - // GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_AUPLL); - if (i2s_device->sampl_freq_hz == 44100) { - GLB_Config_AUDIO_PLL(GLB_XTAL_40M, audioPllCfg_451P584M); - } - - i2sCfg.audioFreqHz = 24576000; - - i2sCfg.sampleFreqHz = i2s_device->sampl_freq_hz; - - /*!< default I2S msb first */ - i2sCfg.endianType = I2S_DATA_ENDIAN; - - /* Config the I2S type */ - switch (i2s_device->interface_mode) { - case I2S_MODE_STD: - i2sCfg.modeType = I2S_MODE_I2S_LEFT; - i2sCfg.fsMode = I2S_FS_MODE_EVEN; - i2sCfg.dataOffset = 1; - break; - - case I2S_MODE_LEFT: - i2sCfg.modeType = I2S_MODE_I2S_LEFT; - i2sCfg.fsMode = I2S_FS_MODE_EVEN; - i2sCfg.dataOffset = 0; - break; - - case I2S_MODE_RIGHT: - i2sCfg.modeType = I2S_MODE_I2S_RIGHT; - i2sCfg.fsMode = I2S_FS_MODE_EVEN; - i2sCfg.dataOffset = 0; - break; - - case I2S_MODE_DSP_A: - i2sCfg.modeType = I2S_MODE_I2S_DSP; - i2sCfg.fsMode = I2S_FS_MODE_1T; - i2sCfg.dataOffset = 1; - break; - - case I2S_MODE_DSP_B: - i2sCfg.modeType = I2S_MODE_I2S_DSP; - i2sCfg.fsMode = I2S_FS_MODE_1T; - i2sCfg.dataOffset = 0; - break; - - default: - return ERROR; - break; - } - - /* Config the frame/data Size */ - switch (i2s_device->frame_size) { - case I2S_FRAME_LEN_8: - i2sCfg.frameSize = I2S_SIZE_FRAME_8; - break; - - case I2S_FRAME_LEN_16: - i2sCfg.frameSize = I2S_SIZE_FRAME_16; - break; - - case I2S_FRAME_LEN_24: - i2sCfg.frameSize = I2S_SIZE_FRAME_24; - break; - - case I2S_FRAME_LEN_32: - i2sCfg.frameSize = I2S_SIZE_FRAME_32; - break; - - default: - return ERROR; - break; - } - - switch (i2s_device->data_size) { - case I2S_DATA_LEN_8: - i2sCfg.dataSize = I2S_SIZE_DATA_8; - break; - - case I2S_DATA_LEN_16: - i2sCfg.dataSize = I2S_SIZE_DATA_16; - break; - - case I2S_DATA_LEN_24: - i2sCfg.dataSize = I2S_SIZE_DATA_24; - break; - - case I2S_DATA_LEN_32: - i2sCfg.dataSize = I2S_SIZE_DATA_32; - break; - - default: - return ERROR; - break; - } - - fifoCfg.lRMerge = DISABLE; - fifoCfg.frameDataExchange = DISABLE; - - /* Config the Channel number */ - switch (i2s_device->channel_num) { - case I2S_FS_CHANNELS_NUM_MONO: - i2sCfg.monoMode = ENABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_2; - i2sCfg.monoModeChannel = I2S_MONO_CHANNEL; - break; - - case I2S_FS_CHANNELS_NUM_2: - i2sCfg.monoMode = DISABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_2; - - if (i2s_device->data_size == I2S_DATA_LEN_8 || i2s_device->data_size == I2S_DATA_LEN_16) { - fifoCfg.lRMerge = ENABLE; - fifoCfg.frameDataExchange = I2S_LR_EXCHANGE; - } - - break; - - case I2S_FS_CHANNELS_NUM_3: - if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) { - return ERROR; - } - - i2sCfg.monoMode = DISABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_3; - break; - - case I2S_FS_CHANNELS_NUM_4: - if ((i2s_device->interface_mode != I2S_MODE_DSP_A) && (i2s_device->interface_mode != I2S_MODE_DSP_B)) { - return ERROR; - } - - i2sCfg.monoMode = DISABLE; - i2sCfg.fsChannel = I2S_FS_CHANNELS_4; - - default: - return ERROR; - break; - } - - /* Config the bclk/fs invert */ - i2sCfg.bclkInvert = I2S_BCLK_INVERT; - i2sCfg.fsInvert = I2S_FS_INVERT; - - if (oflag & DEVICE_OFLAG_INT_TX) { - } - - if (oflag & DEVICE_OFLAG_INT_RX) { - } - - fifoCfg.txfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_TX) ? ENABLE : DISABLE; - fifoCfg.rxfifoDmaEnable = (oflag & DEVICE_OFLAG_DMA_RX) ? ENABLE : DISABLE; - fifoCfg.txFifoLevel = i2s_device->fifo_threshold; - fifoCfg.rxFifoLevel = i2s_device->fifo_threshold; - - /* I2S Init */ - I2S_Disable(i2s_device->id); - I2S_Init(i2s_device->id, &i2sCfg); - I2S_FifoConfig(i2s_device->id, &fifoCfg); - - if (i2s_device->iis_mode == I2S_MODE_MASTER) - I2S_Enable(i2s_device->id, I2S_ROLE_MASTER); - else if (i2s_device->iis_mode == I2S_MODE_SLAVE) - I2S_Enable(i2s_device->id, I2S_ROLE_SLAVE); - return 0; -} - -int i2s_close(struct device *dev) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - I2S_Disable(i2s_device->id); - return 0; -} - -int i2s_control(struct device *dev, int cmd, void *args) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - break; - - case DEVICE_CTRL_CLR_INT: - - break; - - case DEVICE_CTRL_GET_INT: - - break; - - case DEVICE_CTRL_RESUME: - - break; - - case DEVICE_CTRL_SUSPEND: - - break; - - case DEVICE_CTRL_CONFIG: - - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - i2s_device->tx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_ATTACH_RX_DMA: - i2s_device->rx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_GET_CONFIG: - switch ((uint32_t)(size_t)args) { - case I2S_GET_TX_FIFO_CMD: - return I2S_GetTxFIFO_AvlCnt(i2s_device->id); - - case I2S_GET_RX_FIFO_CMD: - return I2S_GetRxFIFO_AvlCnt(i2s_device->id); - - default: - break; - } - - break; - default: - return ERROR; - break; - } - - return SUCCESS; -} - -int i2s_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)i2s_device->tx_dma; - - if (!dma_ch) { - return -1; - } - - if (i2s_device->id == 0) { - dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size); - dma_channel_start(dma_ch); - } else if (i2s_device->id == 1) { - dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_I2S_TDR, size); - dma_channel_start(dma_ch); - } - - return 0; - } else { - return 0; - } -} - -int i2s_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - i2s_device_t *i2s_device = (i2s_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_RX) { - struct device *dma_ch = (struct device *)i2s_device->rx_dma; - - if (!dma_ch) { - return -1; - } - - if (i2s_device->id == 0) { - dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (i2s_device->id == 1) { - dma_reload(dma_ch, (uint32_t)DMA_ADDR_I2S_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } - - return 0; - } else { - return 0; - } -} - -int i2s_register(enum i2s_index_type index, const char *name) -{ - struct device *dev; - - if (I2S_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(i2sx_device[index].parent); - - dev->open = i2s_open; - dev->close = i2s_close; - dev->control = i2s_control; - dev->write = i2s_write; - dev->read = i2s_read; - - dev->type = DEVICE_CLASS_I2S; - dev->handle = NULL; - - return device_register(dev, name); -} - -void i2s_isr(i2s_device_t *handle) -{ - return; -} - -void I2S_IRQ(void) -{ - i2s_isr(&i2sx_device[0]); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_mtimer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_mtimer.c deleted file mode 100644 index 34880dd2b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_mtimer.c +++ /dev/null @@ -1,139 +0,0 @@ -/** - * @file hal_mtimer.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_mtimer.h" -#include "bl808_glb.h" - -static void (*systick_callback)(void); -static uint64_t current_set_ticks = 0; - -static void Systick_Handler(void) -{ - csi_coret_config(current_set_ticks, MTIME_IRQn); - systick_callback(); -} - -/** - * @brief - * - */ -void mtimer_init(void) -{ - uint32_t clkSrc = CPU_Get_MTimer_Source_Clock(); - - CPU_Interrupt_Disable(MTIME_IRQn); - - if (clkSrc > 1 * 1000 * 1000) { - /* Set MTimer clock source 1M */ - CPU_Set_MTimer_CLK(1, clkSrc / 1000 / 1000 - 1); - } else { - /* Set MTimer clock source 1k */ - CPU_Set_MTimer_CLK(1, clkSrc / 1000 - 1); - } - - /* never reset mtimer */ - //CPU_Reset_MTimer(); -} - -/** - * @brief - * - */ -void mtimer_deinit() -{ - CPU_Interrupt_Disable(MTIME_IRQn); -} -/** - * @brief - * - * @param time - * @param interruptFun - */ -void mtimer_set_alarm_time(uint64_t ticks, void (*interruptfun)(void)) -{ - current_set_ticks = ticks; - systick_callback = interruptfun; - - csi_coret_config_use(ticks, MTIME_IRQn); - CPU_Interrupt_Disable(MTIME_IRQn); - Interrupt_Handler_Register(MTIME_IRQn, Systick_Handler); - CPU_Interrupt_Enable(MTIME_IRQn); -} -/** - * @brief - * - */ -void mtimer_start() -{ -} -/** - * @brief - * - */ -void mtimer_stop() -{ -} -/** - * @brief - * - */ -void mtimer_clear_time() -{ - CPU_Reset_MTimer(); -} - -/** - * @brief - * - * @return uint64_t - */ -uint64_t mtimer_get_time_ms() -{ - return CPU_Get_MTimer_MS(); -} -/** - * @brief - * - * @return uint64_t - */ -uint64_t mtimer_get_time_us() -{ - return CPU_Get_MTimer_US(); -} -/** - * @brief - * - * @param time - */ -void mtimer_delay_ms(uint32_t time) -{ - CPU_MTimer_Delay_MS(time); -} -/** - * @brief - * - * @param time - */ -void mtimer_delay_us(uint32_t time) -{ - CPU_MTimer_Delay_US(time); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pm.c deleted file mode 100644 index 28bcc3b754..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pm.c +++ /dev/null @@ -1,855 +0,0 @@ -/** - * @file hal_pm.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_pm.h" -#include "bl808.h" -#include "bl808_hbn.h" -#include "bl808_pds.h" -#include "hal_flash.h" -#include "hal_rtc.h" - -#define PM_PDS_GPIO_KEEP_EN 0 -#define PM_HBN_GPIO_KEEP_EN 0 -#define PM_PDS_FLASH_POWER_OFF 1 -#define PM_PDS_DLL_POWER_OFF 1 -#define PM_PDS_PLL_POWER_OFF 1 -#define PM_PDS_RF_POWER_OFF 1 -#define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V -#define PM_PDS_DCDC_LEVEL_DEFAULT AON_DCDC_LEVEL_1P100V -#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_0P90V - -/* Cache Way Disable, will get from l1c register */ -uint8_t cacheWayDisable = 0; - -/* PSRAM IO Configuration, will get from glb register */ -uint32_t psramIoCfg = 0; - -/* Flash offset value, will get from sf_ctrl register */ -uint32_t flash_offset = 0; - -SPI_Flash_Cfg_Type *flash_cfg; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 0, - .saveWiFiState = 0, - .dcdc11Off = 0, - .bgSysOff = 0, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 1, - .usbpllOff = 0, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0x08, - .pdsCtlRfSel = 3, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 0, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 1, - .UsbIsoEn = 0, - .MiscIsoEn = 0, - }, - .pdsCtl4 = { - .mcuRst = 0, - .mcuMemStby = 0, - .mcuGateClk = 0, - .dspPwrOff = 1, - .dspRst = 1, - .dspMemStby = 1, - .dspGateClk = 1, - .WbRst = 0, - .WbMemStby = 0, - .WbGateClk = 0, - .usbPwrOff = 0, - .usbRst = 0, - .usbMemStby = 0, - .usbGateClk = 0, - .MiscPwrOff = 0, - .MiscRst = 0, - .MiscMemStby = 0, - .MiscGateClk = 0, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 7, - } -}; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 0, - .saveWiFiState = 0, - .dcdc11Off = 0, - .bgSysOff = 0, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 1, - .usbpllOff = 1, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0x08, - .pdsCtlRfSel = 3, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 0, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 0, - .UsbIsoEn = 1, - .MiscIsoEn = 0, - }, - .pdsCtl4 = { - .mcuRst = 0, - .mcuMemStby = 0, - .mcuGateClk = 0, - .dspPwrOff = 0, - .dspRst = 0, - .dspMemStby = 0, - .dspGateClk = 0, - .WbRst = 0, - .WbMemStby = 0, - .WbGateClk = 0, - .usbPwrOff = 1, - .usbRst = 1, - .usbMemStby = 1, - .usbGateClk = 1, - .MiscPwrOff = 0, - .MiscRst = 0, - .MiscMemStby = 0, - .MiscGateClk = 0, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 7, - } -}; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 0, - .saveWiFiState = 0, - .dcdc11Off = 0, - .bgSysOff = 0, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 1, - .usbpllOff = 1, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0x08, - .pdsCtlRfSel = 3, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 0, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 1, - .UsbIsoEn = 1, - .MiscIsoEn = 0, - }, - .pdsCtl4 = { - .mcuRst = 0, - .mcuMemStby = 0, - .mcuGateClk = 0, - .dspPwrOff = 1, - .dspRst = 1, - .dspMemStby = 1, - .dspGateClk = 1, - .WbRst = 0, - .WbMemStby = 0, - .WbGateClk = 0, - .usbPwrOff = 1, - .usbRst = 1, - .usbMemStby = 1, - .usbGateClk = 1, - .MiscPwrOff = 0, - .MiscRst = 0, - .MiscMemStby = 0, - .MiscGateClk = 0, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 7, - } -}; - -static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = { - .pdsCtl = { - .pdsStart = 1, - .sleepForever = 0, - .xtalForceOff = 1, - .saveWiFiState = 0, - .dcdc11Off = 1, - .bgSysOff = 1, - .ctrlGpioIePuPd = 0, - .dcdc18Off = 1, - .clkOff = 1, - .memStby = 1, - .glbRstProtect = 0, - .isolation = 1, - .waitXtalRdy = 0, - .pdsPwrOff = 1, - .xtalOff = 1, - .socEnbForceOn = 0, - .pdsRstSocEn = 0, - .pdsRC32mOn = 0, - .pdsDcdc11VselEn = 0, - .usbpllOff = 1, - .aupllOff = 1, - .cpupllOff = 1, - .wifipllOff = 1, - .pdsDcdc11Vsel = 0, - .pdsCtlRfSel = 1, - .pdsUseTbttSlp = 0, - .pdsGpioIsoMod = 1, - }, - .pdsCtl2 = { - .forceDspPwrOff = 0, - .forceUsbPwrOff = 0, - .forceDspIso = 0, - .forceUsbIso = 0, - .forceMcuPdsRst = 0, - .forceDspPdsRst = 0, - .forceWbPdsRst = 0, - .forceUsbPdsRst = 0, - .forceMcuMemStby = 0, - .forceDspMemStby = 0, - .forceWbMemStby = 0, - .forceUsbMemStby = 0, - .forceMcuGateClk = 0, - .forceDspGateClk = 0, - .forceWbGateClk = 0, - .forceUsbGateClk = 0, - }, - .pdsCtl3 = { - .forceMiscPwrOff = 0, - .forceMiscIsoEn = 0, - .forceMiscPdsRst = 0, - .forceMiscMemStby = 0, - .forceMiscGateClk = 0, - .DspIsoEn = 1, - .UsbIsoEn = 1, - .MiscIsoEn = 1, - }, - .pdsCtl4 = { - .mcuRst = 1, - .mcuMemStby = 1, - .mcuGateClk = 1, - .dspPwrOff = 1, - .dspRst = 1, - .dspMemStby = 1, - .dspGateClk = 1, - .WbRst = 1, - .WbMemStby = 1, - .WbGateClk = 1, - .usbPwrOff = 1, - .usbRst = 1, - .usbMemStby = 1, - .usbGateClk = 1, - .MiscPwrOff = 1, - .MiscRst = 1, - .MiscMemStby = 1, - .MiscGateClk = 1, - }, - .pdsCtl5 = { - .McuWfiMask = 0, - .DspWfiMask = 1, - .LpWfiMask = 1, - .ctrlUsb33 = 1, - .pdLdo18io = 1, - .gpioKeepEn = 0, - } -}; - -static void pm_hbn_rtc_rst_disable(void) -{ - HBN_RTC_MISC_Type rtcMiscCfg; - - HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg); - rtcMiscCfg.rtcRstEnRtc = 0; - HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg); -} - -/****************************************************************************** - * @brief set power down sleep VDDCORE gpio interrupt mask - * - * @param None - * - * @return SUCCESS or ERROR - * - *******************************************************************************/ -static BL_Err_Type pm_clr_pds_gpio_int(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT); - // PDS_GPIO_INT_SET_1_GPIO0_GPIO7: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR); - // PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR); - // PDS_GPIO_INT_SET_3_GPIO23_GPIO30: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR); - // PDS_GPIO_INT_SET_4_GPIO31_GPIO38: - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR); - - BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal); - return SUCCESS; -} - -void pm_pds_mask_all_wakeup_src(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_WAKEUP_SRC_EN); - BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); -} - -static void pm_pds_intc_clr(void) -{ - pm_clr_pds_gpio_int(); - PDS_IntClear(); -} - -/** - * @brief power management in pds(power down sleep) mode - * - * cpu's behavior after wakeup depend on psd level,see flow table if cpu off , - * cpu will reset after wakeup - * - * PD_AON_RTC PD_AON PD_AON_HBNCORE PD_CORE PD_CORE_MISC PD_USB PD_DSP - * PDS0 ON ON ON ON ON ON ON - * PDS1 ON ON ON ON ON ON OFF - * PDS2 ON ON ON ON ON OFF ON - * PDS3 ON ON ON ON ON OFF OFF - * PDS7 ON ON ON ON OFF OFF OFF - */ -void ATTR_TCM_SECTION pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, - uint32_t sleep_time) -{ - PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL; - uint32_t tmpVal; - uint32_t flash_cfg_len; - uint32_t pds_ram1; - uint32_t pds_ram2; - - /* To make it simple and safe*/ - cpu_global_irq_disable(); - - pm_hbn_rtc_rst_disable(); - - flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len); - - HBN_Set_Ldo11_All_Vout(PM_PDS_LDO_LEVEL_DEFAULT); - AON_Set_DCDC11_Top_Vout(PM_PDS_DCDC_LEVEL_DEFAULT); - /************************ PDS INT SET ***********************/ - // PDS_WAKEUP_IRQHandler_Install(); - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_INT); - - if (sleep_time) { - tmpVal |= (1 << 10); // unmask pds sleep time wakeup - } - - BL_WR_REG(PDS_BASE, PDS_INT, tmpVal); - - /* clear all interrupt status */ - pm_pds_intc_clr(); - - /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI)*/ - pm_pds_irq_register(); - /***********************************************************/ - - switch (pds_level) { - case PM_PDS_LEVEL_1: - pPdsCfg = &pdsCfgLevel1; - break; - case PM_PDS_LEVEL_2: - pPdsCfg = &pdsCfgLevel2; - break; - case PM_PDS_LEVEL_3: - pPdsCfg = &pdsCfgLevel3; - break; - case PM_PDS_LEVEL_7: - pPdsCfg = &pdsCfgLevel7; - break; - default: - return; - } - -#if PM_PDS_FLASH_POWER_OFF - uint32_t sw_cfg0 = 0; - SF_Ctrl_Pin_Select sf_pin_select = 0; - - /* get sw uasge 0 */ - EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&sw_cfg0); - sf_pin_select = (tmpVal >> 14) & 0x3f; - flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len); - - HBN_Power_Down_Flash(flash_cfg); - - /* LDO_FLASH Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO18FLASH); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_LDO18FLASH_PULLDOWN); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_LDO18FLASH_PULLDOWN_SEL); - BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal); - - /* Turn Off Flash PAD IE */ - /* GPIO46~51 */ - for (int i = 0; i < 6; i++) { - BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG46_OFFSET + i * 4, 0); - } - - /* Turn Off PSRAM PAD IE */ - /* GPIO52~63 */ - for (int i = 0; i < 12; i++) { - BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG52_OFFSET + i * 4, 0); - } -#endif - -#if PM_PDS_GPIO_KEEP_EN - pPdsCfg->pdsCtl.pdsGpioIsoMod = 1; - pPdsCfg->pdsCtl5.gpioKeepEn = 7; -#endif - -#if PM_PDS_PLL_POWER_OFF - /*************************** Clock Config **************************/ - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); // MCU CLK SELECT RC32M - GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_RC32M); - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - - /* Power Down Mipi PLL */ - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - /* Power Down UHS(PSRAM) PLL */ - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - - // GLB_Set_SF_CLK(1, GLB_SFLASH_CLK_BCLK, 0); - tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL); - tmpVal |= (0x3 << 9); - BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal); - /**************************************************************/ -#endif - -#if PM_PDS_RF_POWER_OFF == 0 - pPdsCfg->pdsCtl.pdsCtlRfSel = 0; -#endif - - if (0xFFFFFFFF != BL_RD_REG(PDS_BASE, PDS_GPIO_PD_SET)) { - pPdsCfg->pdsCtl.ctrlGpioIePuPd = 1; - } - - /* LDO12_UHS Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO12UHS); - BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); - - /* LDO15_CIS Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO15CIS); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO15CIS); - BL_WR_REG(GLB_BASE, GLB_LDO15CIS, tmpVal); - - /* DCDC18 Pull down When disable */ - tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_1); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_DCDC18_PULLDOWN_AON); - BL_WR_REG(AON_BASE, AON_DCDC18_TOP_1, tmpVal); - - /* LDO28_CIS Pull down */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO28CIS); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LDO28CIS); - BL_WR_REG(GLB_BASE, GLB_LDO28CIS, tmpVal); - - pds_ram1 = BL_RD_REG(PDS_BASE, PDS_RAM1); - pds_ram2 = BL_RD_REG(PDS_BASE, PDS_RAM2); - - /* PD_CORE's SRAM Clock Gating During PDS Mode */ - pds_ram1 |= (1 << 31); - - if (pds_level == PM_PDS_LEVEL_7) { - pds_ram1 &= ~(0xf < 4); // ocram retention - pds_ram1 |= 0xf; // ocram sleep - pds_ram2 &= ~(0x3ff < 9); // wram retention - pds_ram2 |= (0x380 < 9); // wram retention - pds_ram2 &= ~0x3ff; - pds_ram2 |= 0x7f; // wram sleep - } - - PDS_Default_Level_Config(pPdsCfg, (PDS_CTRL_RAM1_Type *)&pds_ram1, - (PDS_CTRL_RAM2_Type *)&pds_ram2, sleep_time); - - __WFI(); - - /****************************** Wakeup Flow *******************************/ - HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P10V); - AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_1P100V); - - /* LDO28_CIS Pull On */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO28CIS); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LDO28CIS); - BL_WR_REG(GLB_BASE, GLB_LDO28CIS, tmpVal); - - /* DCDC18 Pull On*/ - tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_DCDC18_PULLDOWN_AON); - BL_WR_REG(AON_BASE, AON_DCDC18_TOP_1, tmpVal); - - /* LDO15_CIS Pull On */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO15CIS); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LDO15CIS); - BL_WR_REG(GLB_BASE, GLB_LDO15CIS, tmpVal); - - /* LDO12_UHS Pull On */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LDO12UHS); - BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal); - -#if PM_PDS_PLL_POWER_OFF - GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL); - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M); - GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M); -#endif - -#if PM_PDS_FLASH_POWER_OFF - if (pds_level <= PM_PDS_LEVEL_3) { - /* Init flash gpio */ - SF_Cfg_Init_Ext_Flash_Gpio(0); - SF_Cfg_Init_Flash_Gpio(sf_pin_select, 1); - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - SFlash_Restore_From_Powerdown(flash_cfg, 0, SF_CTRL_FLASH_BANK0); - } -#endif - - cpu_global_irq_enable(); -} - -/** - * @brief - * - * power management in hbn(hibernation) mode - * cpu will reset after wakeup - * - * HBN_LEVEL PD_AON_RTC PD_AON PD_AON_HBNCORE PD_CORE&PD_CORE_MISC&PD_USB&PD_MM - * HBN0 ON ON ON OFF - * HBN1 ON ON OFF OFF - * HBN2 ON OFF OFF OFF - * - * @param hbn_level - */ -void ATTR_TCM_SECTION pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, - uint8_t sleep_time) -{ - uint32_t tmpVal; - - /* To make it simple and safe*/ - cpu_global_irq_disable(); - - CPU_Interrupt_Pending_Clear(HBN_OUT0_IRQn); - CPU_Interrupt_Pending_Clear(HBN_OUT1_IRQn); - - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff); - BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0); - - if (sleep_time) { - rtc_init(sleep_time); // sleep time,unit is second - } - - if (hbn_level >= PM_HBN_LEVEL_2) { - HBN_PD_RC32K_In_Poff(); - } - -#if PM_PDS_FLASH_POWER_OFF - HBN_Power_Down_Flash(NULL); -#endif - -#if PM_HBN_GPIO_KEEP_EN - tmpVal = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_AON_GPIO_ISO_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_AON_CTRL_GPIO); - BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal); -#endif - - /* Select RC32M */ - // GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M); - GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M); - /* power off pll */ - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - /* power off xtal */ - AON_Power_Off_XTAL(); - - /* HBN mode LDO level */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, - PM_HBN_LDO_LEVEL_DEFAULT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, - PM_HBN_LDO_LEVEL_DEFAULT); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - /* Set HBN flag */ - BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - - /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */ - if (hbn_level < PM_HBN_LEVEL_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE); - } - - /* Set power on option:0 for por reset twice for robust 1 for reset only - * once*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - /* Enable HBN mode */ - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - while (1) { - arch_delay_ms(100); - GLB_SW_POR_Reset(); - } -} - -void pm_hbn_out0_irq_register(void) -{ - Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQ); - CPU_Interrupt_Enable(HBN_OUT0_IRQn); -} - -void pm_hbn_out1_irq_register(void) -{ - Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQ); - CPU_Interrupt_Enable(HBN_OUT1_IRQn); -} - -void HBN_OUT0_IRQ(void) -{ - if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) { - HBN_Clear_IRQ(HBN_INT_GPIO9); - pm_irq_callback(PM_HBN_GPIO9_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) { - HBN_Clear_IRQ(HBN_INT_GPIO10); - pm_irq_callback(PM_HBN_GPIO10_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) { - HBN_Clear_IRQ(HBN_INT_GPIO11); - pm_irq_callback(PM_HBN_GPIO11_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) { - HBN_Clear_IRQ(HBN_INT_GPIO12); - pm_irq_callback(PM_HBN_GPIO12_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO13)) { - HBN_Clear_IRQ(HBN_INT_GPIO13); - pm_irq_callback(PM_HBN_GPIO13_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO14)) { - HBN_Clear_IRQ(HBN_INT_GPIO14); - pm_irq_callback(PM_HBN_GPIO14_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO15)) { - HBN_Clear_IRQ(HBN_INT_GPIO15); - pm_irq_callback(PM_HBN_GPIO15_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO40)) { - HBN_Clear_IRQ(HBN_INT_GPIO40); - pm_irq_callback(PM_HBN_GPIO40_WAKEUP_EVENT); - } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO41)) { - HBN_Clear_IRQ(HBN_INT_GPIO41); - pm_irq_callback(PM_HBN_GPIO41_WAKEUP_EVENT); - } else { - HBN_Clear_IRQ(HBN_INT_RTC); - HBN_Clear_RTC_INT(); - pm_irq_callback(PM_HBN_RTC_WAKEUP_EVENT); - } -} - -void ATTR_TCM_SECTION HBN_OUT1_IRQ(void) -{ - /* PIR */ - if (SET == HBN_Get_INT_State(HBN_INT_PIR)) { - HBN_Clear_IRQ(HBN_INT_PIR); - } - /* BOR */ - else if (SET == HBN_Get_INT_State(HBN_INT_BOD)) { - HBN_Clear_IRQ(HBN_INT_BOD); - pm_irq_callback(PM_HBN_BOD_WAKEUP_EVENT); - } - /* ACOMP0 */ - else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) { - HBN_Clear_IRQ(HBN_INT_ACOMP0); - pm_irq_callback(PM_HBN_ACOMP0_WAKEUP_EVENT); - } - /* ACOMP1 */ - else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) { - HBN_Clear_IRQ(HBN_INT_ACOMP1); - pm_irq_callback(PM_HBN_ACOMP1_WAKEUP_EVENT); - } -} - -__WEAK void pm_irq_callback(enum pm_event_type event) -{ -} - -void pm_pds_irq_register(void) -{ - Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQ); - CPU_Interrupt_Enable(PDS_WAKEUP_IRQn); -} - -void ATTR_TCM_SECTION PDS_WAKEUP_IRQ(void) -{ - /* WAKE INT */ - if (SET == PDS_Get_IntStatus(PDS_INT_WAKEUP)) { - } - /* RF DONE */ - else if (SET == PDS_Get_IntStatus(PDS_INT_RF_DONE)) { - } - /* WIFI_TBTT_SLEEP */ - else if (SET == PDS_Get_IntStatus(PDS_INT_WIFI_TBTT_SLEEP)) { - } - /* WIFI_TBTT_WAKEUP */ - else if (SET == PDS_Get_IntStatus(PDS_INT_WIFI_TBTT_WAKEUP)) { - } - - PDS_IntClear(); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pwm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pwm.c deleted file mode 100644 index 65c2513db4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_pwm.c +++ /dev/null @@ -1,205 +0,0 @@ -/** - * @file hal_pwm.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_pwm.h" -#include "hal_clock.h" -#include "bl808_pwm.h" - -static pwm_device_t pwmx_device[PWM_MAX_INDEX] = { -#ifdef BSP_USING_PWM0 - PWM0_CONFIG, -#endif -#ifdef BSP_USING_PWM1 - PWM1_CONFIG, -#endif -}; - -static void PWM_IRQ(void); - -int pwm_open(struct device *dev, uint16_t oflag) -{ - pwm_device_t *pwm_device = (pwm_device_t *)dev; - PWMx_CFG_Type pwmxCfg = { 0 }; - - CPU_Interrupt_Disable(PWM_IRQn); - PWMx_Disable(pwm_device->id); - PWM_SW_Break_Disable(pwm_device->id); - PWM_Int_Mask(pwm_device->id, PWM_INT_ALL, MASK); - - pwmxCfg.clk = pwm_device->clk_source; - pwmxCfg.clkDiv = pwm_device->clk_div; - pwmxCfg.stopMode = PWM_STOP_GRACEFUL; - pwmxCfg.stpRept = pwm_device->output_mode; - pwmxCfg.extPol = pwm_device->extern_break_polarity; - pwmxCfg.adcSrc = pwm_device->adc_trig_source; - pwmxCfg.intPulseCnt = pwm_device->pulse; - PWMx_Init(pwm_device->id, &pwmxCfg); - - if (pwm_device->extern_break_enable) { - PWM_EXT_Break_Enable(pwm_device->id); - } else { - PWM_EXT_Break_Disable(pwm_device->id); - } - - if (pwm_device->internal_break_enable) { - PWM_SW_Break_Enable(pwm_device->id); - } else { - PWM_SW_Break_Disable(pwm_device->id); - } - - Interrupt_Handler_Register(PWM_IRQn, PWM_IRQ); - CPU_Interrupt_Enable(PWM_IRQn); - - return 0; -} -int pwm_close(struct device *dev) -{ - pwm_device_t *pwm_device = (pwm_device_t *)dev; - PWM_CHx_CFG_Type chxCfg = { 0 }; - - CPU_Interrupt_Disable(PWM_IRQn); - PWMx_Disable(pwm_device->id); - PWM_Int_Mask(pwm_device->id, PWM_INT_ALL, MASK); - - for (uint8_t i = 0; i < PWM_CHx_MAX; i++) { - PWM_Channelx_Init(pwm_device->id, i, &chxCfg); - } - PWM_SW_Break_Disable(pwm_device->id); - PWM_EXT_Break_Disable(pwm_device->id); - - return 0; -} - -int pwm_control(struct device *dev, int cmd, void *args) -{ - pwm_device_t *pwm_device = (pwm_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: - break; - case DEVICE_CTRL_CLR_INT: - break; - case DEVICE_CTRL_CONFIG: - break; - case DEVICE_CTRL_PWM_CHANNEL_CONFIG: { - pwm_channel_common_t *config = (pwm_channel_common_t *)args; - - PWM_Channelx_Pwm_Mode_Set(pwm_device->id, config->ch, config->chp_enable, config->chn_enable); - PWM_Channelx_Polarity_Set(pwm_device->id, config->ch, config->chp_polarity, config->chn_polarity); - PWM_Channelx_Idle_State_Set(pwm_device->id, config->ch, config->chp_idlestate, config->chn_idlestate); - PWM_Channelx_Threshold_Set(pwm_device->id, config->ch, config->threshold_low, config->threshold_high); - - } break; - - case DEVICE_CTRL_RESUME: - PWMx_Enable(pwm_device->id); - break; - - case DEVICE_CTRL_SUSPEND: - PWMx_Disable(pwm_device->id); - break; - - case DEVICE_CTRL_PWM_FREQUENCE_CONFIG: - PWMx_Period_Set(pwm_device->id, (uint32_t)(uintptr_t)args); - break; - - case DEVICE_CTRL_PWM_DUTYCYCLE_CONFIG: { - pwm_channel_dutycycle_t *config = (pwm_channel_dutycycle_t *)args; - PWM_Channelx_Threshold_Set(pwm_device->id, config->ch, config->threshold_low, config->threshold_high); - } - - break; - - case DEVICE_CTRL_PWM_PULSE_CONFIG: { - uint32_t tmpVal; - uint32_t PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (pwm_device->id) * 0x40; - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, (uint32_t)(uintptr_t)args); - BL_WR_REG(PWMx, PWM_PERIOD, tmpVal); - } break; - case DEVICE_CTRL_PWM_BREAK_CONFIG: { - pwm_channel_break_t *config = (pwm_channel_break_t *)args; - PWM_Channelx_Break_State_Set(pwm_device->id, config->ch, config->chp_breakstate, config->chn_breakstate); - PWM_Channelx_Dtg_Set(pwm_device->id, config->ch, config->deadtime); - } - - break; - default: - break; - } - - return 0; -} - -int pwm_register(enum pwm_index_type index, const char *name) -{ - struct device *dev; - - if (PWM_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(pwmx_device[index].parent); - - dev->open = pwm_open; - dev->close = pwm_close; - dev->control = pwm_control; - dev->write = NULL; - dev->read = NULL; - - dev->type = DEVICE_CLASS_PWM; - dev->handle = NULL; - - return device_register(dev, name); -} - -static void pwm_isr(pwm_device_t *handle) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t PWMx; - uint16_t intIndex; - - if (!handle->parent.callback) { - return; - } - - /* Get PWMx start register address */ - PWMx = PWM_BASE + PWM_CHANNEL_OFFSET + (handle->id) * 0x40; - - tmpVal = BL_RD_REG(PWMx, PWM_INT_STS); - maskVal = BL_RD_REG(PWMx, PWM_INT_MASK); - - for (intIndex = 0; intIndex < PWM_INT_ALL; intIndex++) { - if (((1 << intIndex) & tmpVal) && (((1 << intIndex) & maskVal) == 0)) { - BL_WR_REG(PWMx, PWM_INT_CLEAR, 1 << intIndex); - handle->parent.callback(&handle->parent, NULL, 0, 1 << intIndex); - } - } -} - -static void PWM_IRQ(void) -{ - for (int8_t i = 0; i < PWM_MAX_INDEX; i++) { - pwm_isr(&pwmx_device[i]); - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_rtc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_rtc.c deleted file mode 100644 index 7210eaa341..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_rtc.c +++ /dev/null @@ -1,102 +0,0 @@ -/** - * @file hal_rtc.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_rtc.h" -#include "bl808_hbn.h" -static uint64_t current_timestamp = 0; - -/** - * @brief rtc init withc sleep time - * - * @param sleep_time - */ -void rtc_init(uint64_t sleep_time) -{ - uint32_t tmpVal; - uint32_t comp_l, comp_h; - - /* Clear & Disable RTC counter */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - /* Clear RTC control bit0 */ - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff0); - - /* Get current RTC timer */ - /* Tigger RTC val read */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - - /* Read RTC val */ - comp_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); - comp_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); - - /* calculate RTC Comp time */ - comp_l += (uint32_t)((sleep_time * 32768) & 0xFFFFFFFF); - comp_h += (uint32_t)(((sleep_time * 32768) >> 32) & 0xFFFFFFFF); - - /* Set RTC Comp time */ - BL_WR_REG(HBN_BASE, HBN_TIME_L, comp_l); - BL_WR_REG(HBN_BASE, HBN_TIME_H, comp_h & 0xff); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - /* Set interrupt delay option */ - tmpVal = - BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, HBN_RTC_INT_DELAY_0T); - /* Set RTC compare mode */ - tmpVal |= (HBN_RTC_COMP_BIT0_39 << 1); - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal); - - /* Enable RTC Counter */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL); - /* Set RTC control bit0 */ - BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01); -} - -void rtc_set_timestamp(uint64_t time_stamp) -{ - current_timestamp = time_stamp; -} -/** - * @bref Get rtc value - * - */ -uint64_t rtc_get_timestamp(void) -{ - uint32_t tmpVal; - uint64_t time_l; - uint64_t time_h; - - /* Tigger RTC val read */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH); - BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal); - - /* Read RTC val */ - time_l = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L); - time_h = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff); - - return (((time_h << 32 | time_l) >> 15) + current_timestamp); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_aes.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_aes.c deleted file mode 100644 index ee7a5ae838..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_aes.c +++ /dev/null @@ -1,125 +0,0 @@ -/** - * @file hal_sec_aes.c - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_sec_aes.h" -#include "bl808_sec_eng.h" - -static SEC_Eng_AES_Ctx aesCtx; - -int sec_aes_init(sec_aes_handle_t *handle, sec_aes_type aes_tye, sec_aes_key_type key_type) -{ - handle->aes_type = aes_tye; - handle->key_type = key_type; - - return 0; -} - -static SEC_ENG_AES_Key_Type sec_aes_get_key_type(sec_aes_handle_t *handle) -{ - SEC_ENG_AES_Key_Type type = 0; - - switch (handle->key_type) { - case SEC_AES_KEY_128: - type = SEC_ENG_AES_KEY_128BITS; - break; - - case SEC_AES_KEY_256: - type = SEC_ENG_AES_KEY_256BITS; - break; - - case SEC_AES_KEY_192: - type = SEC_ENG_AES_KEY_192BITS; - break; - - default: - return SEC_ENG_AES_KEY_128BITS; - } - - return type; -} - -int sec_aes_setkey(sec_aes_handle_t *handle, const uint8_t *key, uint8_t key_len, const uint8_t *nonce, uint8_t dir) -{ - SEC_ENG_AES_Key_Type type = sec_aes_get_key_type(handle); - - switch (handle->aes_type) { - case SEC_AES_CBC: - Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); - Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CBC, type, - SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); - break; - - case SEC_AES_CTR: - Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); - Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_CTR, type, - SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); - break; - - case SEC_AES_XTS: - Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID0); - Sec_Eng_AES_Init(&aesCtx, SEC_ENG_AES_ID0, SEC_ENG_AES_XTS, type, - SEC_AES_DIR_ENCRYPT == dir ? SEC_ENG_AES_ENCRYPTION : SEC_ENG_AES_DECRYPTION); - break; - - case SEC_AES_ECB: - break; - - default: - return -1; - } - - /* if key len is 0, means key is from efuse and *key value is key_sel value */ - if (key_len == 0) { - Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_HW, key, nonce); - } else { - Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID0, SEC_ENG_AES_KEY_SW, key, nonce); - } - - return 0; -} - -int sec_aes_encrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) -{ - if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) { - return -1; - } - - return 0; -} - -int sec_aes_decrypt(sec_aes_handle_t *handle, const uint8_t *in, uint32_t len, size_t offset, uint8_t *out) -{ - if (SUCCESS != Sec_Eng_AES_Crypt(&aesCtx, SEC_ENG_AES_ID0, in, len, out)) { - return -1; - } - - return 0; -} - -int sec_aes_deinit(sec_aes_handle_t *handle) -{ - Sec_Eng_AES_Finish(SEC_ENG_AES_ID0); - - memset(handle, 0, sizeof(sec_aes_handle_t)); - - return 0; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_dsa.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_dsa.c deleted file mode 100644 index 72901dbecc..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_dsa.c +++ /dev/null @@ -1,389 +0,0 @@ -/** - * @file hal_sec_dsa.c - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_sec_dsa.h" -#include "bl808_sec_eng.h" - -//#define DSA_DBG 1 -//#define DSA_DBG_DETAIL 1 -void bflb_platform_dump(uint8_t *data, uint32_t len); - -#if (defined(DSA_DBG) || defined(DSA_DBG_DETAIL)) -uint32_t pka_tmp[64] = { 0 }; -#endif - -/* -n=p*q; -F(n)=(p-1)*(q-1) -e*d%F(n)=1[e is public key and d is private key] -dP=d%(p-1) -dQ=d%(q-1) -m1=c^(dP)%p -m2=c^(dQ)%q -h=qInv*(m1-m2)%p -m=m2+h*q -m=c^d -*/ -static SEC_ENG_PKA_REG_SIZE_Type sec_dsa_get_reg_size(uint32_t size) -{ - switch (size) { - case 64: - return SEC_ENG_PKA_REG_SIZE_8; - - case 128: - return SEC_ENG_PKA_REG_SIZE_16; - - case 256: - return SEC_ENG_PKA_REG_SIZE_32; - - case 512: - return SEC_ENG_PKA_REG_SIZE_64; - - case 768: - return SEC_ENG_PKA_REG_SIZE_96; - - case 1024: - return SEC_ENG_PKA_REG_SIZE_128; - - case 1536: - return SEC_ENG_PKA_REG_SIZE_192; - - case 2048: - return SEC_ENG_PKA_REG_SIZE_256; - - case 3072: - return SEC_ENG_PKA_REG_SIZE_384; - - case 4096: - return SEC_ENG_PKA_REG_SIZE_512; - - default: - return SEC_ENG_PKA_REG_SIZE_32; - } - - return SEC_ENG_PKA_REG_SIZE_32; -} - -/* c code: -number = 1 -base = a -while b: - if b & 1: - number = number * base % c - b >>= 1 - base = base * base % c -return number -*/ -int sec_dsa_mexp_binary(uint32_t size, const uint32_t *a, const uint32_t *b, const uint32_t *c, uint32_t *r) -{ - uint32_t i, j, k; - uint32_t tmp; - uint32_t isOne = 0; - uint8_t *p = (uint8_t *)b; - SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); - SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); - uint32_t dataSize = (size >> 3) >> 2; -#if 1 - uint8_t oneBuf[128] ALIGN4 = { 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 }; -#endif - /* 0:c - * 4:a - * 5:number - * 6&7:temp - */ - - /* base = a */ - Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0); - - /* number = 1 */ - Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)oneBuf, sizeof(oneBuf) / 4, 0); - //Sec_Eng_PKA_Write_Immediate(nregType,5,0x01,1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize); - MSG("number:\r\n"); - bflb_platform_dump(pka_tmp, dataSize * 4); -#endif - - Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0); - - Sec_Eng_PKA_CREG(nregType, 6, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 7, dataSize, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("base:\r\n"); - bflb_platform_dump(pka_tmp, dataSize * 4); -#endif - /* Remove zeros bytes*/ - k = 0; - - while (p[k] == 0 && k < (size >> 3)) { - k++; - } - - i = (size >> 3) - 1; - - for (; i >= k; i--) { - tmp = p[i]; - j = 0; - - for (j = 0; j < 8; j++) { - isOne = tmp & (1 << j); - - if (isOne) { - /* number = number * base % c */ - Sec_Eng_PKA_LMUL(lregType, 3, nregType, 5, nregType, 4, 0); - Sec_Eng_PKA_MREM(nregType, 5, lregType, 3, nregType, 0, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)pka_tmp, dataSize); - MSG("number:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - } - - /* base = base * base % c */ - Sec_Eng_PKA_LSQR(lregType, 3, nregType, 4, 0); - Sec_Eng_PKA_MREM(nregType, 4, lregType, 3, nregType, 0, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("base:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - } - } - - Sec_Eng_PKA_Read_Data(nregType, 5, (uint32_t *)r, dataSize); -#ifdef DSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, dataSize * 4); -#endif - return 0; -} - -/*r=a^b%c*/ -int sec_dsa_mexp_mont(uint32_t size, uint32_t *a, uint32_t *b, uint32_t *c, uint32_t *invR_c, uint32_t *primeN_c, uint32_t *r) -{ - SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); - SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); - uint32_t dataSize = (size >> 3) >> 2; - - /* 0:c - * 1:NPrime_c - * 2:invR_c - * 4:a(mont domain) - * 5:b - * 6:a^b%c(mont domain) - * 7:a^b%c(gf domain) - * 10&11:2^size for GF2Mont*/ - Sec_Eng_PKA_Write_Data(nregType, 0, (uint32_t *)c, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 1, (uint32_t *)primeN_c, dataSize, 1); - Sec_Eng_PKA_Write_Data(nregType, 2, (uint32_t *)invR_c, dataSize, 1); - - /* change a into mont domain*/ - Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)a, dataSize, 0); - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - Sec_Eng_PKA_GF2Mont(nregType, 4, nregType, 4, size, lregType, 5, nregType, 0); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("GF2Mont Result of a:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - - Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)b, dataSize, 0); - /* a^b%c*/ - Sec_Eng_PKA_MEXP(nregType, 6, nregType, 4, nregType, 5, nregType, 0, 1); - - /* change result into gf domain*/ - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - /*index 2 is invertR*/ - Sec_Eng_PKA_Mont2GF(nregType, 7, nregType, 6, nregType, 2, lregType, 5, nregType, 0); - Sec_Eng_PKA_Read_Data(nregType, 7, (uint32_t *)r, dataSize); -#ifdef DSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, dataSize /*dataSize*4*/); -#endif - return 0; -} - -/** - * dP=d%(p-1) - * dQ=d%(q-1) - * qInv=qp^(1-1):qInv*q%p=1 - * invR_p*r%p=1(r is 1024/2048/256) - * invR_q*r%q=1(r is 1024/2048/256) - */ -int sec_dsa_decrypt_crt(uint32_t size, uint32_t *c, sec_dsa_crt_cfg_t *crtCfg, uint32_t *d, uint32_t *r) -{ - /* - * m1 = pow(c, dP, p) - * m2 = pow(c, dQ, q) - * h = (qInv * (m1 - m2)) % p - * m = m2 + h * q - * */ - SEC_ENG_PKA_REG_SIZE_Type nregType = sec_dsa_get_reg_size(size); - SEC_ENG_PKA_REG_SIZE_Type lregType = sec_dsa_get_reg_size(size * 2); - uint32_t dataSize = (size >> 3) >> 2; -#if 0 - uint8_t m1[64] = {0x11, 0xdd, 0x19, 0x7e, 0x69, 0x1a, 0x40, 0x0a, 0x28, 0xfc, 0x3b, 0x31, 0x47, 0xa2, 0x6c, 0x14, - 0x4e, 0xf6, 0xb0, 0xe6, 0xcd, 0x89, 0x0b, 0x4f, 0x02, 0xe4, 0x86, 0xe2, 0xe5, 0xbe, 0xe1, 0xaf, - 0x91, 0xd1, 0x7b, 0x59, 0x8d, 0xdc, 0xb3, 0x57, 0x18, 0xcb, 0x80, 0x05, 0x1c, 0xb5, 0xa4, 0x07, - 0xde, 0x31, 0x94, 0xa4, 0x2f, 0x45, 0xc7, 0x95, 0x75, 0x0f, 0x91, 0xf0, 0x37, 0x91, 0x85, 0xa5 - }; - uint8_t m2[64] = {0x63, 0x89, 0xa3, 0xbb, 0x64, 0x63, 0x87, 0x4f, 0x38, 0xbd, 0x9e, 0x0e, 0x93, 0x29, 0x58, 0xee, - 0xf8, 0xe2, 0x20, 0x2d, 0xe5, 0x38, 0x0a, 0x7f, 0x18, 0x38, 0x2f, 0xa3, 0xf5, 0x48, 0xf8, 0xfd, - 0xe5, 0x78, 0x4a, 0x10, 0x62, 0x01, 0x09, 0x29, 0xe3, 0xe3, 0x9f, 0xad, 0x9b, 0xbe, 0x20, 0xd2, - 0x68, 0x90, 0x57, 0x97, 0xfc, 0x78, 0xd5, 0xdb, 0x07, 0x5b, 0xfe, 0x21, 0x0a, 0x2d, 0x7f, 0xc1 - }; -#else - uint32_t m1[32]; - uint32_t m2[32]; -#endif - /* - * 4:m1 - * 5:m2 - * 6:qInv - * 7:p - * 8:q - * 9:h - * 10&11:qInv*(m1-m2) - */ - sec_dsa_mexp_mont(size, c, crtCfg->dP, crtCfg->p, crtCfg->invR_p, crtCfg->primeN_p, m1); - sec_dsa_mexp_mont(size, c, crtCfg->dQ, crtCfg->q, crtCfg->invR_q, crtCfg->primeN_q, m2); - - Sec_Eng_PKA_Write_Data(nregType, 4, (uint32_t *)m1, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 5, (uint32_t *)m2, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 6, (uint32_t *)crtCfg->qInv, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 7, (uint32_t *)crtCfg->p, dataSize, 0); - Sec_Eng_PKA_Write_Data(nregType, 8, (uint32_t *)crtCfg->q, dataSize, 0); - - /*(m1 - m2)%p*/ - Sec_Eng_PKA_MSUB(nregType, 4, nregType, 4, nregType, 5, nregType, 7, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 4, (uint32_t *)pka_tmp, dataSize); - MSG("m1 - m2:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*/); -#endif - /* (qInv * (m1 - m2)) % p*/ - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - Sec_Eng_PKA_LMUL(lregType, 5, nregType, 6, nregType, 4, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2); - MSG("qInv * (m1 - m2):\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/); -#endif - Sec_Eng_PKA_MREM(nregType, 9, lregType, 5, nregType, 7, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(nregType, 9, (uint32_t *)pka_tmp, dataSize); - MSG("h:\r\n"); - bflb_platform_dump(pka_tmp, dataSize * 4); -#endif - - /* h*q */ - Sec_Eng_PKA_CREG(nregType, 10, dataSize, 1); - Sec_Eng_PKA_CREG(nregType, 11, dataSize, 1); - Sec_Eng_PKA_LMUL(lregType, 5, nregType, 9, nregType, 8, 1); -#ifdef DSA_DBG - Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)pka_tmp, dataSize * 2); - MSG("h*q:\r\n"); - bflb_platform_dump(pka_tmp, dataSize /*dataSize*4*2*/); -#endif - /* m2 + h*q*/ - Sec_Eng_PKA_LADD(lregType, 5, lregType, 5, nregType, 5, 1); - - Sec_Eng_PKA_Read_Data(lregType, 5, (uint32_t *)r, dataSize * 2); -#ifdef DSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, dataSize * 4 * 2); -#endif - return 0; -} - -int sec_dsa_init(sec_dsa_handle_t *handle, uint32_t size) -{ - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - memset(handle, 0, sizeof(sec_dsa_handle_t)); - handle->size = size; - handle->crtSize = (size >> 1); - - return 0; -} - -int sec_dsa_sign(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s) -{ - uint32_t dsa_tmp[64] = { 0 }; - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - memcpy(dsa_tmp + ((handle->crtSize >> 3) >> 2) - hashLenInWord, hash, hashLenInWord * 4); - - if (0 == sec_dsa_decrypt_crt(handle->crtSize, dsa_tmp, &handle->crtCfg, handle->d, s)) { - return 0; - } else { - return -1; - } -} - -/** - */ -int sec_dsa_verify(sec_dsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s) -{ - uint32_t dsa_tmp[64]; - uint8_t i = 0; - uint8_t resultOffset = 0; - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - if (0 == sec_dsa_mexp_binary(handle->size, s, handle->e, handle->n, dsa_tmp)) { - resultOffset = (handle->size >> 5) - hashLenInWord; - - for (i = 0; i < hashLenInWord; i++) { - if (dsa_tmp[resultOffset + i] != hash[i]) { - return -1; - } - } - - return 0; - } else { - return -1; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_ecdsa.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_ecdsa.c deleted file mode 100644 index 0a1592e2a5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_ecdsa.c +++ /dev/null @@ -1,1458 +0,0 @@ -#include "hal_sec_ecdsa.h" -#include "bl808_sec_eng.h" - -#define ECP_SECP256R1_REG_TYPE SEC_ENG_PKA_REG_SIZE_32 -#define ECP_SECP256R1_N_REG_INDEX 0 -#define ECP_SECP256R1_NPRIME_N_REG_INDEX 1 -#define ECP_SECP256R1_INVR_N_REG_INDEX 2 -#define ECP_SECP256R1_NPRIME_P_REG_INDEX 3 -#define ECP_SECP256R1_INVR_P_REG_INDEX 4 -#define ECP_SECP256R1_SIZE 32 -/* Used in verify */ -#define ECP_SECP256R1_S_REG_INDEX 5 -#define ECP_SECP256R1_BAR_S_REG_INDEX 6 -#define ECP_SECP256R1_HASH_REG_INDEX 6 //use ECP_SECP256R1_BAR_S_REG_INDEX since it's temp -#define ECP_SECP256R1_U1_REG_INDEX 7 -#define ECP_SECP256R1_LT_REG_TYPE SEC_ENG_PKA_REG_SIZE_64 -#define ECP_SECP256R1_LT_REG_INDEX 7 -#define ECP_SECP256R1_SLT_REG_TYPE SEC_ENG_PKA_REG_SIZE_128 -#define ECP_SECP256R1_SLT_REG_INDEX 3 - -//#define ECDSA_DBG 1 -//#define ECDSA_DBG_DETAIL 1 - -#define secp256r1 -#define secp256k1 -#define SEC_ECC_POINT_MUL_PARAM_CFG(G) sec_ecc_point_mul_cfg( \ - (uint32_t *)G##P, \ - (uint32_t *)G##PrimeN_P, \ - (uint32_t *)G##_1, \ - (uint32_t *)G##_BAR2, \ - (uint32_t *)G##_BAR3, \ - (uint32_t *)G##_BAR4, \ - (uint32_t *)G##_BAR8, \ - (uint32_t *)G##_1P1, \ - (uint32_t *)G##_1M1) - -#define SEC_ECC_BASIC_PARAM_CFG(G) sec_ecc_basic_parameter_cfg( \ - (uint32_t *)G##N, \ - (uint32_t *)G##PrimeN_N, \ - (uint32_t *)G##InvR_N) - -void bflb_platform_dump(uint8_t *data, uint32_t len); - -#if (defined(ECDSA_DBG) || defined(ECDSA_DBG_DETAIL)) -uint32_t pka_tmp[32] = { 0 }; -#endif -/********************************************** secp256r1 *******************************************/ -const uint8_t secp256r1P[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff -}; -const uint8_t secp256r1B[32] ALIGN4 = { - 0x5a, 0xc6, 0x35, 0xd8, 0xaa, 0x3a, 0x93, 0xe7, 0xb3, 0xeb, 0xbd, 0x55, 0x76, 0x98, 0x86, 0xbc, - 0x65, 0x1d, 0x06, 0xb0, 0xcc, 0x53, 0xb0, 0xf6, 0x3b, 0xce, 0x3c, 0x3e, 0x27, 0xd2, 0x60, 0x4b -}; -const uint8_t secp256r1Gx[32] ALIGN4 = { - 0x6b, 0x17, 0xd1, 0xf2, 0xe1, 0x2c, 0x42, 0x47, 0xf8, 0xbc, 0xe6, 0xe5, 0x63, 0xa4, 0x40, 0xf2, - 0x77, 0x03, 0x7d, 0x81, 0x2d, 0xeb, 0x33, 0xa0, 0xf4, 0xa1, 0x39, 0x45, 0xd8, 0x98, 0xc2, 0x96 -}; -const uint8_t secp256r1Gy[32] ALIGN4 = { - 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, - 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5 -}; -const uint8_t secp256r1N[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xbc, 0xe6, 0xfa, 0xad, 0xa7, 0x17, 0x9e, 0x84, 0xf3, 0xb9, 0xca, 0xc2, 0xfc, 0x63, 0x25, 0x51 -}; -const uint8_t secp256r1PrimeN_N[32] ALIGN4 = { - 0x60, 0xd0, 0x66, 0x33, 0xa9, 0xd6, 0x28, 0x1c, 0x50, 0xfe, 0x77, 0xec, 0xc5, 0x88, 0xc6, 0xf6, - 0x48, 0xc9, 0x44, 0x08, 0x7d, 0x74, 0xd2, 0xe4, 0xcc, 0xd1, 0xc8, 0xaa, 0xee, 0x00, 0xbc, 0x4f -}; -const uint8_t secp256r1InvR_N[32] ALIGN4 = { - 0x60, 0xd0, 0x66, 0x33, 0x49, 0x05, 0xc1, 0xe9, 0x07, 0xf8, 0xb6, 0x04, 0x1e, 0x60, 0x77, 0x25, - 0xba, 0xde, 0xf3, 0xe2, 0x43, 0x56, 0x6f, 0xaf, 0xce, 0x1b, 0xc8, 0xf7, 0x9c, 0x19, 0x7c, 0x79 -}; -const uint8_t secp256r1PrimeN_P[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256r1InvR_P[32] ALIGN4 = { - 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x02, - 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256r1_1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256r1_BAR2[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x01, 0xff, 0xff, 0xff, 0xfd, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfe, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 -}; -const uint8_t secp256r1_BAR3[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x02, 0xff, 0xff, 0xff, 0xfc, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfd, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03 -}; -const uint8_t secp256r1_BAR4[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x03, 0xff, 0xff, 0xff, 0xfb, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xfc, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04 -}; -const uint8_t secp256r1_BAR8[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x07, 0xff, 0xff, 0xff, 0xf7, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xf8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08 -}; -const uint8_t secp256r1_1P1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02 -}; -const uint8_t secp256r1_1M1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256r1_Zerox[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256r1_Zeroy[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xfe, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, - 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256r1_Gx[32] ALIGN4 = { - 0x18, 0x90, 0x5f, 0x76, 0xa5, 0x37, 0x55, 0xc6, 0x79, 0xfb, 0x73, 0x2b, 0x77, 0x62, 0x25, 0x10, - 0x75, 0xba, 0x95, 0xfc, 0x5f, 0xed, 0xb6, 0x01, 0x79, 0xe7, 0x30, 0xd4, 0x18, 0xa9, 0x14, 0x3c -}; -const uint8_t secp256r1_Gy[32] ALIGN4 = { - 0x85, 0x71, 0xff, 0x18, 0x25, 0x88, 0x5d, 0x85, 0xd2, 0xe8, 0x86, 0x88, 0xdd, 0x21, 0xf3, 0x25, - 0x8b, 0x4a, 0xb8, 0xe4, 0xba, 0x19, 0xe4, 0x5c, 0xdd, 0xf2, 0x53, 0x57, 0xce, 0x95, 0x56, 0x0a -}; - -/********************************************** secp256k1 *******************************************/ -const uint8_t secp256k1P[32] ALIGN4 = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0xFF, 0xFF, 0xFC, 0x2F -}; -const uint8_t secp256k1B[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07 -}; -const uint8_t secp256k1Gx[32] ALIGN4 = { - 0x79, 0xBE, 0x66, 0x7E, 0xF9, 0xDC, 0xBB, 0xAC, 0x55, 0xA0, 0x62, 0x95, 0xCE, 0x87, 0x0B, 0x07, - 0x02, 0x9B, 0xFC, 0xDB, 0x2D, 0xCE, 0x28, 0xD9, 0x59, 0xF2, 0x81, 0x5B, 0x16, 0xF8, 0x17, 0x98 -}; -const uint8_t secp256k1Gy[32] ALIGN4 = { - 0x4f, 0xe3, 0x42, 0xe2, 0xfe, 0x1a, 0x7f, 0x9b, 0x8e, 0xe7, 0xeb, 0x4a, 0x7c, 0x0f, 0x9e, 0x16, - 0x2b, 0xce, 0x33, 0x57, 0x6b, 0x31, 0x5e, 0xce, 0xcb, 0xb6, 0x40, 0x68, 0x37, 0xbf, 0x51, 0xf5 -}; -const uint8_t secp256k1N[32] ALIGN4 = { - 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, - 0xBA, 0xAE, 0xDC, 0xE6, 0xAF, 0x48, 0xA0, 0x3B, 0xBF, 0xD2, 0x5E, 0x8C, 0xD0, 0x36, 0x41, 0x41 -}; -const uint8_t secp256k1PrimeN_N[32] ALIGN4 = { - 0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5e, - 0x50, 0xa5, 0x1a, 0xc8, 0x34, 0xb9, 0xec, 0x24, 0x4b, 0xd, 0xff, 0x66, 0x55, 0x88, 0xb1, 0x3f -}; -const uint8_t secp256k1InvR_N[32] ALIGN4 = { - 0xd9, 0xe8, 0x89, 0xd, 0x64, 0x94, 0xef, 0x93, 0x89, 0x7f, 0x30, 0xc1, 0x27, 0xcf, 0xab, 0x5d, - 0x3b, 0xbb, 0xd4, 0x56, 0x7f, 0xa5, 0xc, 0x3c, 0x80, 0xfd, 0x22, 0x93, 0x80, 0x97, 0xc0, 0x16 -}; -const uint8_t secp256k1PrimeN_P[32] ALIGN4 = { - 0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61, - 0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0xd2, 0x25, 0x35, 0x31 -}; -const uint8_t secp256k1InvR_P[32] ALIGN4 = { - 0xc9, 0xbd, 0x19, 0x5, 0x15, 0x53, 0x83, 0x99, 0x9c, 0x46, 0xc2, 0xc2, 0x95, 0xf2, 0xb7, 0x61, - 0xbc, 0xb2, 0x23, 0xfe, 0xdc, 0x24, 0xa0, 0x59, 0xd8, 0x38, 0x9, 0x1d, 0x8, 0x68, 0x19, 0x2a -}; -const uint8_t secp256k1_1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01 -}; -const uint8_t secp256k1_BAR2[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x07, 0xa2 -}; -const uint8_t secp256k1_BAR3[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x0b, 0x73 -}; -const uint8_t secp256k1_BAR4[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x0f, 0x44 -}; -const uint8_t secp256k1_BAR8[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x1e, 0x88 -}; -const uint8_t secp256k1_1P1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd2 -}; -const uint8_t secp256k1_1M1[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd0 -}; -const uint8_t secp256k1_Zerox[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 -}; -const uint8_t secp256k1_Zeroy[32] ALIGN4 = { - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x03, 0xd1 -}; -const uint8_t secp256k1_Gx[32] ALIGN4 = { - 0x99, 0x81, 0xe6, 0x43, 0xe9, 0x08, 0x9f, 0x48, 0x97, 0x9f, 0x48, 0xc0, 0x33, 0xfd, 0x12, 0x9c, - 0x23, 0x1e, 0x29, 0x53, 0x29, 0xbc, 0x66, 0xdb, 0xd7, 0x36, 0x2e, 0x5a, 0x48, 0x7e, 0x20, 0x97 -}; -const uint8_t secp256k1_Gy[32] ALIGN4 = { - 0xcf, 0x3f, 0x85, 0x1f, 0xd4, 0xa5, 0x82, 0xd6, 0x70, 0xb6, 0xb5, 0x9a, 0xac, 0x19, 0xc1, 0x36, - 0x8d, 0xfc, 0x5d, 0x5d, 0x1f, 0x1d, 0xc6, 0x4d, 0xb1, 0x5e, 0xa6, 0xd2, 0xd3, 0xdb, 0xab, 0xe2 -}; - -static BL_Err_Type sec_ecc_basic_parameter_cfg(uint32_t *n, uint32_t *prime_n, uint32_t *invr_n) -{ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)n, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_NPRIME_N_REG_INDEX, (uint32_t *)prime_n, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, (uint32_t *)invr_n, ECP_SECP256R1_SIZE / 4, 0); - return SUCCESS; -} -static BL_Err_Type sec_ecc_basic_parameter_init(uint8_t id) -{ - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - if (id == ECP_SECP256R1) { - SEC_ECC_BASIC_PARAM_CFG(secp256r1); - } else if (id == ECP_SECP256K1) { - SEC_ECC_BASIC_PARAM_CFG(secp256k1); - } - - return SUCCESS; -} - -static BL_Err_Type sec_ecc_point_mul_cfg(uint32_t *p, uint32_t *primeN_p, uint32_t *ori_1, uint32_t *bar2, - uint32_t *bar3, uint32_t *bar4, uint32_t *bar8, uint32_t *bar1p1, uint32_t *bar1m1) -{ - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)p, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 1, (uint32_t *)primeN_p, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 8, (uint32_t *)ori_1, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 9, (uint32_t *)bar2, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 10, (uint32_t *)bar3, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 11, (uint32_t *)bar4, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 12, (uint32_t *)bar8, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 19, (uint32_t *)bar1p1, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 20, (uint32_t *)bar1m1, ECP_SECP256R1_SIZE / 4, 0); - - return SUCCESS; -} - -static int sec_ecc_point_mul_init(uint8_t id) -{ - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - if (id == ECP_SECP256R1) { - SEC_ECC_POINT_MUL_PARAM_CFG(secp256r1); - } else if (id == ECP_SECP256K1) { - SEC_ECC_POINT_MUL_PARAM_CFG(secp256k1); - } - - return SUCCESS; -} - -static void sec_ecdsa_point_add_inf_check(uint8_t *pka_p1_eq_inf, uint8_t *pka_p2_eq_inf) -{ - uint8_t res[4]; - - /* index 2:BAR_Zero_x - * index 3:BAR_Zero_y - * index 4:BAR_Zero_z - * index 5:BAR_G_x - * index 6:BAR_G_y - * index 7:BAR_G_z - * index 8:1 - * index 9:2 - * index 10:3 - * index 11:4 - * index 12:8 - * index 19:1P1 - * index 20:1m1*/ - - //cout = 1 if X1 = 0 - Sec_Eng_PKA_LCMP(res, 3, 2, 3, 8); //s0 < s1 => cout = 1 - //cout = 1 if Y1 < Bar_1p1 - Sec_Eng_PKA_LCMP(res + 1, 3, 3, 3, 19); - //cout=1 if Y1 > Bar_1m1 - Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 3); - //cout =1 if Z1 = 0 - Sec_Eng_PKA_LCMP(res + 3, 3, 4, 3, 8); - *pka_p1_eq_inf = res[0] & res[1] & res[2] & res[3]; - - //cout = 1 if X2 = 0 - Sec_Eng_PKA_LCMP(res, 3, 5, 3, 8); - // cout = 1 if Y2 < Bar_1p1 - Sec_Eng_PKA_LCMP(res + 1, 3, 6, 3, 19); - //cout = 1 if Y2 > Bar_1m1 - Sec_Eng_PKA_LCMP(res + 2, 3, 20, 3, 6); - //cout = 1 if Z2 = 0 - Sec_Eng_PKA_LCMP(res + 3, 3, 7, 3, 8); - *pka_p2_eq_inf = res[0] & res[1] & res[2] & res[3]; -} - -static void sec_ecdsa_copy_x2_to_x1(uint8_t id) -{ - //X2->X1 - Sec_Eng_PKA_Move_Data(3, 2, 3, 5, 0); - //Y2->Y1 - Sec_Eng_PKA_Move_Data(3, 3, 3, 6, 0); - //Z2->Z1 - Sec_Eng_PKA_Move_Data(3, 4, 3, 7, 1); //Caution!!! wait movdat ready to execute next command -} - -static void sec_ecdsa_point_add(uint8_t id) -{ - /* index 2:BAR_Zero_x - * index 3:BAR_Zero_y - * index 4:BAR_Zero_z - * index 5:BAR_G_x - * index 6:BAR_G_y - * index 7:BAR_G_z - * index 8:1 - * index 9:2 - * index 10:3 - * index 11:4 - * index 12:8 - * index 19:1P1 - * index 20:1m1*/ - - //U1 = Y2*Z1 - //PKA_MMUL(0,3,13,3, 6,3, 4,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx - Sec_Eng_PKA_MMUL(3, 13, 3, 6, 3, 4, 3, 0, 0); - - //U2 = Y1*Z2 - //PKA_MMUL(0,3,14,3, 3,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 3, 3, 7, 3, 0, 0); - - //V1 = X2*Z1 - //PKA_MMUL(0,3,15,3, 5,3, 4,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 4, 3, 0, 0); - - //V2 = X1*Z2 - //PKA_MMUL(0,3,16,3, 2,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 16, 3, 2, 3, 7, 3, 0, 0); - - //U = U1-U2 - //PKA_MSUB(0,3,13,3,13,3,14,3,0); - Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); - - //V = V1-V2 - //PKA_MSUB(0,3,15,3,15,3,16,3,0); - Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 16, 3, 0, 0); - - //W = Z1*Z2 - //PKA_MMUL(0,3, 2,3, 4,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 2, 3, 4, 3, 7, 3, 0, 0); - - //V^2 - //PKA_MMUL(0,3, 3,3,15,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 3, 3, 15, 3, 15, 3, 0, 0); - - //V^3 - //PKA_MMUL(0,3, 4,3, 3,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 4, 3, 3, 3, 15, 3, 0, 0); - - //U^2 - //PKA_MMUL(0,3,17,3,13,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 17, 3, 13, 3, 13, 3, 0, 0); - - //U^2*W - //PKA_MMUL(0,3,17,3,17,3, 2,3,0); - Sec_Eng_PKA_MMUL(3, 17, 3, 17, 3, 2, 3, 0, 0); - - //U^2*W-V^3 - //PKA_MSUB(0,3,17,3,17,3, 4,3,0); - Sec_Eng_PKA_MSUB(3, 17, 3, 17, 3, 4, 3, 0, 0); - - //2*V^2 - //PKA_MMUL(0,3,18,3, 9,3, 3,3,0); - Sec_Eng_PKA_MMUL(3, 18, 3, 9, 3, 3, 3, 0, 0); - - //2*V^2*V2 - //PKA_MMUL(0,3,18,3,18,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 18, 3, 18, 3, 16, 3, 0, 0); - - //A = U^2*W-V^3-2*V^2*V2 - //PKA_MSUB(0,3,18,3,17,3,18,3,0); - Sec_Eng_PKA_MSUB(3, 18, 3, 17, 3, 18, 3, 0, 0); - - //V^2*V2 - //PKA_MMUL(0,3, 3,3, 3,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 3, 3, 3, 3, 16, 3, 0, 0); - - //V^3*U2 - //PKA_MMUL(0,3,14,3, 4,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 4, 3, 14, 3, 0, 0); - - //Z3 = V^3*W - //PKA_MMUL(0,3, 4,3, 4,3, 2,3,0); - Sec_Eng_PKA_MMUL(3, 4, 3, 4, 3, 2, 3, 0, 0); - - //X3 = V*A - //PKA_MMUL(0,3, 2,3,15,3,18,3,0); - Sec_Eng_PKA_MMUL(3, 2, 3, 15, 3, 18, 3, 0, 0); - - //V^2*V2-A - //PKA_MSUB(0,3, 3,3, 3,3,18,3,0); - Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 18, 3, 0, 0); - - //U*(V^2*V2-A) - //PKA_MMUL(0,3, 3,3,13,3, 3,3,0); - Sec_Eng_PKA_MMUL(3, 3, 3, 13, 3, 3, 3, 0, 0); - - //Y3 = U*(V^2*V2-A)-V^3*U2 - //PKA_MSUB(1,3, 3,3, 3,3,14,3,0); - Sec_Eng_PKA_MSUB(3, 3, 3, 3, 3, 14, 3, 0, 1); -} -/** - * @brief calculate secp256r1's W - * - * @note index 13:W = 3X^2-3Z^2 - */ -static void sec_ecdsa_cal_secp256r1_w(void) -{ - //X1^2 - //PKA_MMUL(0,3,13,3, 5,3, 5,3,0);//d_reg_type,d_reg_idx,s0_reg_type,s0_reg_idx,s1_reg_type,s1_reg_idx,s2_reg_type,s2_reg_idx - Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0); - - //Z1^2 - //PKA_MMUL(0,3,14,3, 7,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 7, 3, 7, 3, 0, 0); - - //X1^2-Z1^2 - //PKA_MSUB(0,3,13,3,13,3,14,3,0); - Sec_Eng_PKA_MSUB(3, 13, 3, 13, 3, 14, 3, 0, 0); - - //W = 3*(X1^2-Z1^2) - //PKA_MMUL(0,3,13,3,10,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0); -} - -/** - * @brief calculate secp256k1's W - * - * @note index 13:W = 3X^2 - */ -static void sec_ecdsa_cal_secp256k1_w(void) -{ - //X1^2 - Sec_Eng_PKA_MMUL(3, 13, 3, 5, 3, 5, 3, 0, 0); - - //W = 3* (X1^2) - Sec_Eng_PKA_MMUL(3, 13, 3, 10, 3, 13, 3, 0, 0); -} - -static BL_Err_Type sec_ecdsa_point_double(sec_ecp_type id) -{ - /* index 2:BAR_Zero_x - * index 3:BAR_Zero_y - * index 4:BAR_Zero_z - * index 5:BAR_G_x - * index 6:BAR_G_y - * index 7:BAR_G_z - * index 8:1 - * index 9:2 - * index 10:3 - * index 11:4 - * index 12:8 - * index 19:1P1 - * index 20:1m1*/ - - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - if (id == ECP_SECP256R1) { - sec_ecdsa_cal_secp256r1_w(); - } else if (id == ECP_SECP256K1) { - sec_ecdsa_cal_secp256k1_w(); - } - - //S = Y1*Z1 - //PKA_MMUL(0,3,14,3, 6,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 14, 3, 6, 3, 7, 3, 0, 0); - - //X1*Y1 - //PKA_MMUL(0,3,15,3, 5,3, 6,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 5, 3, 6, 3, 0, 0); - - //W^2 - //PKA_MMUL(0,3, 7,3,13,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 7, 3, 13, 3, 13, 3, 0, 0); - - //B = X1*Y1*S - //PKA_MMUL(0,3,15,3,15,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 14, 3, 0, 0); - - //8*B - //PKA_MMUL(0,3, 5,3,12,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 5, 3, 12, 3, 15, 3, 0, 0); - - //H = W^2-8*B - //PKA_MSUB(0,3, 7,3, 7,3, 5,3,0); - Sec_Eng_PKA_MSUB(3, 7, 3, 7, 3, 5, 3, 0, 0); - - //2*H - //PKA_MMUL(0,3, 5,3, 9,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 5, 3, 9, 3, 7, 3, 0, 0); - - //X2 = 2*H*S - //PKA_MMUL(0,3, 5,3, 5,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 5, 3, 5, 3, 14, 3, 0, 0); - - //4*B - //PKA_MMUL(0,3,15,3,11,3,15,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 11, 3, 15, 3, 0, 0); - - //S^2 - //PKA_MMUL(0,3,16,3,14,3,14,3,0); - Sec_Eng_PKA_MMUL(3, 16, 3, 14, 3, 14, 3, 0, 0); - - //4*B-H - //PKA_MSUB(0,3,15,3,15,3, 7,3,0); - Sec_Eng_PKA_MSUB(3, 15, 3, 15, 3, 7, 3, 0, 0); - - //Y1^2 - //PKA_MMUL(0,3, 6,3, 6,3, 6,3,0); - Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 6, 3, 0, 0); - - //W*(4*B-H) - //PKA_MMUL(0,3,15,3,15,3,13,3,0); - Sec_Eng_PKA_MMUL(3, 15, 3, 15, 3, 13, 3, 0, 0); - - //8*Y1^2 - //PKA_MMUL(0,3, 6,3,12,3, 6,3,0); - Sec_Eng_PKA_MMUL(3, 6, 3, 12, 3, 6, 3, 0, 0); - - //8*Y1^2*S^2 - //PKA_MMUL(0,3, 6,3, 6,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 6, 3, 6, 3, 16, 3, 0, 0); - - //Y2 = W*(4*B-H)-8*Y1^2*S^2 - //PKA_MSUB(0,3, 6,3,15,3, 6,3,0); - Sec_Eng_PKA_MSUB(3, 6, 3, 15, 3, 6, 3, 0, 0); - - //S^3 - //PKA_MMUL(0,3, 7,3,14,3,16,3,0); - Sec_Eng_PKA_MMUL(3, 7, 3, 14, 3, 16, 3, 0, 0); - - //Z2 = 8*S^3 - //PKA_MMUL(1,3, 7,3,12,3, 7,3,0); - Sec_Eng_PKA_MMUL(3, 7, 3, 12, 3, 7, 3, 0, 1); - - return SUCCESS; -} -#ifdef ECDSA_DBG_DETAIL -static void sec_ecdsa_dump_temp_result() -{ - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("2=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("3=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("4=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("5=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("6=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 7, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("7=\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -} -#endif -static int sec_ecdsa_verify_point_mul(uint8_t id, const uint32_t *m) -{ - uint32_t i, j, k; - uint32_t tmp; - uint32_t isOne = 0; - uint8_t *p = (uint8_t *)m; - uint8_t pka_p1_eq_inf, pka_p2_eq_inf; - - /* Remove zeros bytes*/ - k = 0; - - while (p[k] == 0 && k < 31) { - k++; - } - - i = 31; - - for (; i >= k; i--) { - tmp = p[i]; - j = 0; - - for (j = 0; j < 8; j++) { - isOne = tmp & (1 << j); - - if (isOne) { - sec_ecdsa_point_add_inf_check(&pka_p1_eq_inf, &pka_p2_eq_inf); - - if (pka_p1_eq_inf == 1 && pka_p2_eq_inf == 0) { - //sum = X2 - sec_ecdsa_copy_x2_to_x1(id); -#ifdef ECDSA_DBG_DETAIL - MSG("sum = X2\r\n"); - sec_ecdsa_dump_temp_result(); -#endif - } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 1) { - //sum = X1 - //MSG("sum = X1\r\n"); - } else if (pka_p1_eq_inf == 0 && pka_p2_eq_inf == 0) { - //sum = X1 + X2 - sec_ecdsa_point_add(id); -#ifdef ECDSA_DBG_DETAIL - MSG("sum = X1+X2\r\n"); - sec_ecdsa_dump_temp_result(); -#endif - } else { - //MSG("Error! infinite point + infinite point\r\n"); - return -1; - } - } - - sec_ecdsa_point_double(id); -#ifdef ECDSA_DBG_DETAIL - sec_ecdsa_dump_temp_result(); -#endif - } - - if (i == 0) { - break; - } - } - - return 0; -} - -/*cal d*G if pkX(pky)==NULL - * cal d(bG) if pkX(pky)!=NULL */ -static int32_t sec_ecdh_get_scalar_point(uint8_t id, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ -#ifdef ECDSA_DBG - uint32_t pk_z[8]; -#endif - - if (id >= ECP_TYPE_MAX) { - return ERROR; - } - - /* Pointer check */ - if (private_key == NULL) { - return -1; - } - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - sec_ecc_basic_parameter_init(id); - - //Clear D[7] - //PKA_CREG(1,4, 7,0); - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecc_point_mul_init(id); - - if (id == ECP_SECP256R1) { - //X1 - //PKA_CTREG(3, 2,8,bar_Zero_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - //PKA_CTREG(3, 3,8,bar_Zero_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - //X1 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256k1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256k1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - } - //Z1 - //PKA_CTREG(3, 4,8,bar_Zero_z); - //PKA_MOVDAT(1,3, 4,3, 2); - Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); - - if (pkX == NULL) { - if (id == ECP_SECP256R1) { - //X2 - //PKA_CTREG(3, 5,8,bar_G_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); - //Y2 - //PKA_CTREG(3, 6,8,bar_G_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - //X2 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256k1_Gx, ECP_SECP256R1_SIZE / 4, 0); - //Y2 - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1_Gy, ECP_SECP256R1_SIZE / 4, 0); - } - } else { - /* chaneg peer's public key to mont domain*/ - //PUB_x - //PKA_CTREG(3, 5,8,PUB_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pkX, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_x - //PKA_GF2MONT(3, 5,3, 5); - /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.x in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - //PUB_y - //PKA_CTREG(3, 6,8,PUB_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pkY, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_y - //PKA_GF2MONT(3, 6,3, 6); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.y in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - } - - //Z2 - //PKA_CTREG(3, 7,8,bar_G_z); - //PKA_MOVDAT(1,3, 7,3, 3); - Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); - /* Clear temp register since it's used in point-mul*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecdsa_verify_point_mul(id, private_key); - //get bar_u1_x - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_x\r\n"); - bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_y\r\n"); - bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); -#endif -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)pk_z, ECP_SECP256R1_SIZE / 4); - MSG("bar_u1_z\r\n"); - bflb_platform_dump(pk_z, ECP_SECP256R1_SIZE); -#endif - - //get R.x - //R.z ^ -1 - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); - if (id == ECP_SECP256R1) { - //inv_r - //PKA_CTREG(3, 6,8,inv_r); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } - //R.z ^ -1 - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - //PKA_MONT2GF(3, 5,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (Montgomery to GF) - //PKA_MONT2GF(3, 6,3, 2,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (GF to Affine domain) - //PKA_MONT2GF(3, 2,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.x=\r\n"); - bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); -#endif - if (id == ECP_SECP256R1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0); - } - - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 2, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)pRx, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.x%n=\r\n"); - bflb_platform_dump(pRx, ECP_SECP256R1_SIZE); -#endif - if (id == ECP_SECP256R1) { - /*after %n,re write p*/ - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256r1P, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_32, 0, (uint32_t *)secp256k1P, ECP_SECP256R1_SIZE / 4, 0); - } - - //get R.y - //R.z ^ -1 - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); - //inv_r - //PKA_CTREG(3, 6,8,inv_r); - if (id == ECP_SECP256R1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256k1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - } - //R.z ^ -1 - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - //PKA_MONT2GF(3, 5,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - //R.x (Montgomery to GF) - //PKA_MONT2GF(3, 6,3, 2,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (GF to Affine domain) - //PKA_MONT2GF(3, 2,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.y=\r\n"); - bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); -#endif - if (id == ECP_SECP256R1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - } else if (id == ECP_SECP256K1) { - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256k1N, ECP_SECP256R1_SIZE / 4, 0); - } - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 3, ECP_SECP256R1_REG_TYPE, 3, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)pRy, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.y%n=\r\n"); - bflb_platform_dump(pRy, ECP_SECP256R1_SIZE); -#endif - return 0; -} - -static int32_t sec_ecc_is_zero(uint8_t *a, uint32_t len) -{ - uint32_t i = 0; - - for (i = 0; i < len; i++) { - if (a[i] != 0) { - return 0; - } - } - - return 1; -} - -static int32_t sec_ecc_cmp(uint8_t *a, uint8_t *b, uint32_t len) -{ - uint32_t i = 0, j = 0; - - for (i = 0; i < len; i++) { - if (a[i] != 0) { - break; - } - } - - for (j = 0; j < len; j++) { - if (b[j] != 0) { - break; - } - } - - if (i == len && j == len) { - return (0); - } - - if (i > j) { - return (-1); - } - - if (j > i) { - return (1); - } - - for (; i < len; i++) { - if (a[i] > b[i]) { - return (1); - } - - if (a[i] < b[i]) { - return (-1); - } - } - - return 0; -} - -int sec_ecdsa_init(sec_ecdsa_handle_t *handle, sec_ecp_type id) -{ - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - Sec_Eng_Trng_Enable(); - - handle->ecpId = id; - - return 0; -} - -int sec_ecdsa_deinit(sec_ecdsa_handle_t *handle) -{ - Sec_Eng_PKA_Reset(); - - return 0; -} - -__WEAK void sec_ecdsa_verify_suss_callback(uint32_t state, uint8_t is_en) -{ - -} - -int sec_ecdsa_verify(sec_ecdsa_handle_t *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *r, const uint32_t *s) -{ - uint32_t bar_u1_x[8]; - uint32_t bar_u1_y[8]; - uint32_t bar_u1_z[8]; - uint32_t bar_u2_x[8]; - uint32_t bar_u2_y[8]; - uint32_t bar_u2_z[8]; - uint32_t pka_u1[8] = { 0 }; - uint32_t pka_u2[8] = { 0 }; - uint32_t i = 0; - - /* Pointer check */ - if (hash == NULL || handle->publicKeyx == NULL || handle->publicKeyy == NULL || r == NULL || s == NULL) { - return -1; - } - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - - /*Step 0: make sure r and s are in range 1..n-1*/ - - /* r and s should not be 0*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 8, (uint32_t *)secp256r1_1, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r = 0 - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 - - if (i == 1) { - return -1; - } - - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r = 0 - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, 8); //s0 < s1 => cout = 1 - - if (i == 1) { - return -1; - } - - sec_ecc_basic_parameter_init(handle->ecpId); - - /* r and s should not be 0*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r < N - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); - - if (i != 1) { - return -1; - } - - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); - //cout = 1 if r < N - Sec_Eng_PKA_LCMP((uint8_t *)&i, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); - - if (i != 1) { - return -1; - } - - /* u1 = e / s mod n, u2 = r / s mod n - * R = u1 G + u2 Q*/ - - /* Step1: Get S^-1*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)s, ECP_SECP256R1_SIZE / 4, 0); - /* Change s to Mont domain */ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("GF2Mont Result of s:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Get S^-1 in Mont domain */ - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("s^-1 in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Change S^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store s^-1*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_BAR_S_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("S^-1:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Step2: Get u1*/ - //u1=hash(e)*s^-1; - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u1, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("u1:\r\n"); - bflb_platform_dump(pka_u1, ECP_SECP256R1_SIZE); -#endif - - /* Step3: Get u2*/ - //u2=r*s^-1; - // use hash and u1 temp register - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_HASH_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_S_REG_INDEX, 0); - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_U1_REG_INDEX, (uint32_t *)pka_u2, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("u2:\r\n"); - bflb_platform_dump(pka_u2, ECP_SECP256R1_SIZE); -#endif - - /* Step4: Get u1*G*/ - - //Clear D[7] - //PKA_CREG(1,4, 7,0); - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecc_point_mul_init(handle->ecpId); - - //X1 - //PKA_CTREG(3, 2,8,bar_Zero_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - //PKA_CTREG(3, 3,8,bar_Zero_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - //Z1 - //PKA_CTREG(3, 4,8,bar_Zero_z); - //PKA_MOVDAT(1,3, 4,3, 2); - Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); - - //X2 - //PKA_CTREG(3, 5,8,bar_G_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)secp256r1_Gx, ECP_SECP256R1_SIZE / 4, 0); - //Y2 - //PKA_CTREG(3, 6,8,bar_G_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1_Gy, ECP_SECP256R1_SIZE / 4, 0); - //Z2 - //PKA_CTREG(3, 7,8,bar_G_z); - //PKA_MOVDAT(1,3, 7,3, 3); - Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); - - sec_ecdsa_verify_point_mul(handle->ecpId, pka_u1); - //get bar_u1_x - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_x\r\n"); - bflb_platform_dump(bar_u1_x, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_y\r\n"); - bflb_platform_dump(bar_u1_y, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u1_z\r\n"); - bflb_platform_dump(bar_u1_z, ECP_SECP256R1_SIZE); -#endif - - /* Step4: Get u2*Q*/ - //X1 - //PKA_CTREG(3, 2,8,bar_Zero_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)secp256r1_Zerox, ECP_SECP256R1_SIZE / 4, 0); - //Y1 - //PKA_CTREG(3, 3,8,bar_Zero_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)secp256r1_Zeroy, ECP_SECP256R1_SIZE / 4, 0); - //Z1 - //PKA_CTREG(3, 4,8,bar_Zero_z); - //PKA_MOVDAT(1,3, 4,3, 2); - Sec_Eng_PKA_Move_Data(3, 4, 3, 2, 1); - - //PUB_x - //PKA_CTREG(3, 5,8,PUB_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)handle->publicKeyx, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_x - //PKA_GF2MONT(3, 5,3, 5); - /* Change s to Mont domain,remember to clear temp register and index 0 is P256*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.x in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - //PUB_y - //PKA_CTREG(3, 6,8,PUB_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)handle->publicKeyy, ECP_SECP256R1_SIZE / 4, 0); - //bar_pub_y - //PKA_GF2MONT(3, 6,3, 6); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 6, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("PK.y in Mont:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - //bar_pub_z - //PKA_CTREG(3, 7,8,PUB_z); - //PKA_MOVDAT(1,3, 7,3, 3); - Sec_Eng_PKA_Move_Data(3, 7, 3, 3, 1); - - /* Clear temp register since it's used in point-mul*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_LT_REG_TYPE, 7, ECP_SECP256R1_SIZE / 4, 1); - - sec_ecdsa_verify_point_mul(handle->ecpId, pka_u2); - //get bar_u1_x - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u2_x\r\n"); - bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u2_y, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u2_y\r\n"); - bflb_platform_dump(bar_u2_y, ECP_SECP256R1_SIZE); -#endif - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u2_z, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("bar_u2_z\r\n"); - bflb_platform_dump(bar_u2_z, ECP_SECP256R1_SIZE); -#endif - - /* Step5: Get u1*G+u2*Q*/ - //move bar_u2_x - //PKA_MOVDAT(0,3, 5,3, 2); - Sec_Eng_PKA_Move_Data(3, 5, 3, 2, 0); - //move bar_u2_y - //PKA_MOVDAT(0,3, 6,3, 3); - Sec_Eng_PKA_Move_Data(3, 6, 3, 3, 0); - //move bar_u2_z - //PKA_MOVDAT(1,3, 7,3, 4); - Sec_Eng_PKA_Move_Data(3, 7, 3, 4, 1); - - //bar_u1_x - //PKA_CTREG(3, 2,8,bar_u1_x); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u1_x, ECP_SECP256R1_SIZE / 4, 0); - //bar_u1_y - //PKA_CTREG(3, 3,8,bar_u1_y); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 3, (uint32_t *)bar_u1_y, ECP_SECP256R1_SIZE / 4, 0); - //bar_u1_z - //PKA_CTREG(3, 4,8,bar_u1_z); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)bar_u1_z, ECP_SECP256R1_SIZE / 4, 0); - - //R = u1 * G + u2 * PUB - //PKA_POINT_ADDITION(); - sec_ecdsa_point_add(handle->ecpId); - - /* Step6 Get R.x(R=u1G+u2P)*/ - //R.z ^ -1 - //PKA_MINV(0,3, 5,3, 4,3, 0); - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_REG_TYPE, 0, 1); - //inv_r - //PKA_CTREG(3, 6,8,inv_r); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)secp256r1InvR_P, ECP_SECP256R1_SIZE / 4, 0); - //R.z ^ -1 - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - //PKA_MONT2GF(3, 5,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (Montgomery to GF) - //PKA_MONT2GF(3, 6,3, 2,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - - //R.x (GF to Affine domain) - //PKA_MONT2GF(3, 2,3, 5,3, 6); - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 2, ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 0); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 2, (uint32_t *)bar_u2_x, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("R.x=\r\n"); - bflb_platform_dump(bar_u2_x, ECP_SECP256R1_SIZE); -#endif - - /* Step7 check R.x=r*/ - /* Check Result */ - for (i = 0; i < 8; i++) { - if (bar_u2_x[i] != r[i]) { - return -1; - } - } - -#ifdef ECDSA_DBG - MSG("Verify success\r\n"); -#endif - - sec_ecdsa_verify_suss_callback(SEC_CODEPATH_STATE_SIGN, 1); - - return 0; -} - -int sec_ecdsa_sign(sec_ecdsa_handle_t *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s) -{ - uint32_t k[8]; - uint32_t Rx[8]; - uint32_t Ry[8]; - uint32_t KInvert[8]; - uint32_t maxTry1 = 100; - - /* Pointer check */ - if (handle->privateKey == NULL || hash == NULL || r == NULL || s == NULL) { - return -1; - } - - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - Sec_Eng_Trng_Enable(); - - while (maxTry1--) { - /* step 1 ,get random k*/ - if (random_k == NULL) { - if (sec_ecc_get_random_value(k, (uint32_t *)secp256r1N, 32) < 0) { - return -1; - } - } else { - memcpy(k, random_k, 32); - } - -#ifdef ECDSA_DBG - MSG("Random k:\r\n"); - bflb_platform_dump(k, ECP_SECP256R1_SIZE); -#endif - - /*step 2, calc R=kG*/ - if (sec_ecdsa_get_public_key(handle, k, Rx, Ry) < 0) { - return -1; - } - - if (sec_ecc_is_zero((uint8_t *)Rx, 32)) { - continue; - } - - memcpy(r, Rx, 32); -#ifdef ECDSA_DBG - MSG("r:\r\n"); - bflb_platform_dump(r, ECP_SECP256R1_SIZE); -#endif - sec_ecc_basic_parameter_init(handle->ecpId); - /* step 3,get k^-1*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)k, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - /* Change k to Mont domain */ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX - 1, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_CREG(ECP_SECP256R1_REG_TYPE, 2 * ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_SIZE / 4, 1); - Sec_Eng_PKA_GF2Mont(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 5, 256, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 4); - MSG("GF2Mont Result of k:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE); -#endif - - /* Get k^-1 in Mont domain */ - Sec_Eng_PKA_MINV(ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, 5, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 6, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); - MSG("k^-1 in Mont:\r\n"); - bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); -#endif - - /* Change k^-1 into GF domain,now ECP_SECP256R1_S_REG_INDEX store k^-1*/ - /* Clear register for ECP_SECP256R1_LT_REG_INDEX*/ - Sec_Eng_PKA_Mont2GF(ECP_SECP256R1_REG_TYPE, 5, ECP_SECP256R1_REG_TYPE, 6, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_INVR_N_REG_INDEX, - ECP_SECP256R1_LT_REG_TYPE, ECP_SECP256R1_LT_REG_INDEX, ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("k^-1:\r\n"); - bflb_platform_dump(KInvert, ECP_SECP256R1_SIZE); -#endif - - /* Step 4,r*d ((e + r * d) / k) */ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)handle->privateKey, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)r, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_REG_TYPE, 4, - ECP_SECP256R1_REG_TYPE, 5, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); - MSG("r*d:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); -#endif - - /* Step 5,e+r*d ((e + r * d) / k) */ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)hash, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LADD(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, 5, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); - MSG("e+r*d:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); -#endif - - /* Step 6,(e+r*d)*k^-1 ((e + r * d) / k) */ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, 5, (uint32_t *)KInvert, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_LMUL(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, 5, 1); -#ifdef ECDSA_DBG - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, (uint32_t *)pka_tmp, ECP_SECP256R1_SIZE / 2); - MSG("(e+r*d)*k^-1:\r\n"); - bflb_platform_dump(pka_tmp, ECP_SECP256R1_SIZE * 2); -#endif - /*N write only this time,add following operation will not change this register*/ - Sec_Eng_PKA_Write_Data(ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, (uint32_t *)secp256r1N, ECP_SECP256R1_SIZE / 4, 0); - Sec_Eng_PKA_MREM(ECP_SECP256R1_REG_TYPE, 4, ECP_SECP256R1_SLT_REG_TYPE, ECP_SECP256R1_SLT_REG_INDEX, - ECP_SECP256R1_REG_TYPE, ECP_SECP256R1_N_REG_INDEX, 1); - Sec_Eng_PKA_Read_Data(ECP_SECP256R1_REG_TYPE, 4, (uint32_t *)s, ECP_SECP256R1_SIZE / 4); -#ifdef ECDSA_DBG - MSG("s:\r\n"); - bflb_platform_dump(s, ECP_SECP256R1_SIZE); -#endif - - /* Check s zero*/ - if (sec_ecc_is_zero((uint8_t *)s, 32)) { - continue; - } - - return 0; - } - - return -1; -} - -int sec_ecdsa_get_private_key(sec_ecdsa_handle_t *handle, uint32_t *private_key) -{ - if (sec_ecc_get_random_value(private_key, (uint32_t *)secp256r1N, 32) < 0) { - return -1; - } - - return 0; -} - -int sec_ecdsa_get_public_key(sec_ecdsa_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ - return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); -} - -int sec_ecc_get_random_value(uint32_t *randomData, uint32_t *maxRef, uint32_t size) -{ - uint32_t maxTry = 100; - int32_t ret = 0; - - while (maxTry--) { - ret = Sec_Eng_Trng_Get_Random((uint8_t *)randomData, size); - - if (ret < 0) { - return -1; - } - - if (maxRef != NULL) { - if (sec_ecc_cmp((uint8_t *)maxRef, (uint8_t *)randomData, size) > 0) { - return 0; - } - } else { - return 0; - } - } - - return -1; -} - -int sec_eng_trng_enable(void) -{ - return Sec_Eng_Trng_Enable(); -} - -void sec_eng_trng_disable(void) -{ - Sec_Eng_Trng_Disable(); -} - -int sec_eng_trng_read(uint8_t data[32]) -{ - return Sec_Eng_Trng_Read(data); -} - -int sec_ecdh_init(sec_ecdh_handle_t *handle, sec_ecp_type id) -{ - Sec_Eng_PKA_Reset(); - Sec_Eng_PKA_BigEndian_Enable(); - Sec_Eng_Trng_Enable(); - - handle->ecpId = id; - - return 0; -} - -int sec_ecdh_deinit(sec_ecdh_handle_t *handle) -{ - Sec_Eng_PKA_Reset(); - - return 0; -} - -int sec_ecdh_get_encrypt_key(sec_ecdh_handle_t *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ - return sec_ecdh_get_scalar_point(handle->ecpId, pkX, pkY, private_key, pRx, pRy); -} - -int sec_ecdh_get_public_key(sec_ecdh_handle_t *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy) -{ - return sec_ecdh_get_scalar_point(handle->ecpId, NULL, NULL, private_key, pRx, pRy); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_hash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_hash.c deleted file mode 100644 index d34121dd95..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_sec_hash.c +++ /dev/null @@ -1,387 +0,0 @@ -/** - * @file hal_sec_hash.c - * @brief - * - * Copyright 2019-2030 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_sec_hash.h" -#include "bl808_sec_eng.h" - -void SEC_SHA_IRQHandler(void); - -static sec_hash_device_t sec_hashx_device[SEC_HASH_MAX_INDEX] = { - 0 -}; - -static SEC_Eng_SHA256_Ctx shaCtx; - -static SEC_Eng_SHA256_Ctx sha256Ctx; - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int sec_hash_open(struct device *dev, uint16_t oflag) -{ - sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - int ret = 0; - - switch (sec_hash_device->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, sec_hash_device->shaBuf, sec_hash_device->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Init(&shaCtx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, sec_hash_device->shaBuf, sec_hash_device->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} -/** - * @brief - * - * @param dev - * @return int - */ -int sec_hash_close(struct device *dev) -{ - //sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - //memset(sec_hash_device, 0, sizeof(sec_hash_device_t)); //will cause crash - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int sec_hash_control(struct device *dev, int cmd, void *args) -{ - return 0; -} - -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int sec_hash_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - int ret = 0; - - switch (sec_hash_device->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Update(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int sec_hash_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - sec_hash_device_t *sec_hash_device = (sec_hash_device_t *)dev; - int ret = 0; - - switch (sec_hash_device->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 28; - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Finish(&shaCtx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 32; - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param handle - * @param type - * @return int - */ -int sec_hash_init(sec_hash_handle_t *handle, uint8_t type) -{ - int ret = 0; - - switch (type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - handle->type = type; - Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA224, handle->shaBuf, handle->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA256: - handle->type = type; - Sec_Eng_SHA256_Init(&sha256Ctx, SEC_ENG_SHA_ID0, SEC_ENG_SHA256, handle->shaBuf, handle->shaPadding); - Sec_Eng_SHA_Start(SEC_ENG_SHA_ID0); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} -/** - * @brief - * - * @param handle - * @return int - */ -int sec_hash_deinit(sec_hash_handle_t *handle) -{ - memset(handle->shaBuf, 0, sizeof(handle->shaBuf)); - memset(handle->shaPadding, 0, sizeof(handle->shaPadding)); - - return 0; -} - -/** - * @brief - * - * @param handle - * @param buffer - * @param size - * @return int - */ -int sec_hash_update(sec_hash_handle_t *handle, const void *buffer, uint32_t size) -{ - int ret = 0; - - switch (handle->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Update(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer, size); - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param handle - * @param buffer - * @return int - */ -int sec_hash_finish(sec_hash_handle_t *handle, void *buffer) -{ - int ret = 0; - - switch (handle->type) { - case SEC_HASH_SHA1: - ret = -1; - break; - - case SEC_HASH_SHA224: - Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 28; - break; - - case SEC_HASH_SHA256: - Sec_Eng_SHA256_Finish(&sha256Ctx, SEC_ENG_SHA_ID0, (uint8_t *)buffer); - ret = 32; - break; - - case SEC_HASH_SHA384: - case SEC_HASH_SHA512: - ret = -1; - break; - - default: - ret = -1; - break; - } - - return ret; -} - -/** - * @brief - * - * @param index - * @param type - * @param name - * @param flag - * @return int - */ -static int sec_hash_sha_register(enum sec_hash_index_type index, enum sec_hash_type type, const char *name) -{ - struct device *dev; - - if (SEC_HASH_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(sec_hashx_device[index].parent); - sec_hashx_device[index].type = type; - - dev->open = sec_hash_open; - dev->close = sec_hash_close; - dev->control = sec_hash_control; - dev->write = sec_hash_write; - dev->read = sec_hash_read; - - dev->type = DEVICE_CLASS_SEC_HASH; - dev->handle = NULL; - - return device_register(dev, name); -} - -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int sec_hash_sha256_register(enum sec_hash_index_type index, const char *name) -{ - return sec_hash_sha_register(index, SEC_HASH_SHA256, name); -} - -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int sec_hash_sha224_register(enum sec_hash_index_type index, const char *name) -{ - return sec_hash_sha_register(index, SEC_HASH_SHA224, name); -} - -/** - * @brief - * - * @param handle - */ -void sec_hash_isr(void) -{ -} - -/** - * @brief - * - */ -void SEC_SHA_IRQ(void) -{ - sec_hash_isr(); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi.c deleted file mode 100644 index 8538d9706c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi.c +++ /dev/null @@ -1,494 +0,0 @@ -/** - * @file hal_spi.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_spi.h" -#include "hal_dma.h" -#include "bl808_glb.h" -#include "bl808_spi.h" - -#ifdef BSP_USING_SPI0 -static void SPI0_IRQ_Function(void); -#endif -#ifdef BSP_USING_SPI1 -static void SPI1_IRQ_Function(void); -#endif - -static spi_device_t spix_device[SPI_MAX_INDEX] = { -#ifdef BSP_USING_SPI0 - SPI0_CONFIG, -#endif -#ifdef BSP_USING_SPI1 - SPI1_CONFIG, -#endif -}; - -// static uint8_t SPI_IRQ_NumList[SPI_ID_MAX] = {SPI0_IRQn, SPI1_IRQn}; -extern const uint32_t spiAddr[]; - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int spi_open(struct device *dev, uint16_t oflag) -{ - spi_device_t *spi_device = (spi_device_t *)dev; - SPI_CFG_Type spiCfg = { 0 }; - SPI_FifoCfg_Type fifoCfg = { 0 }; - SPI_ClockCfg_Type clockCfg; - uint32_t spi_clk; - - /* reset SPI (close SPI)*/ - SPI_DeInit(spi_device->id); - - switch (spi_device->id) - { - case 0: - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SPI); - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0); - CPU_Interrupt_Disable(SPI0_IRQn); - GLB_Swap_MCU_SPI_0_MOSI_With_MISO(spi_device->pin_swap_enable); - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(spi_device->mode); - break; - case 1: - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, 0); - CPU_Interrupt_Disable(SPI1_IRQn); - GLB_Swap_DSP_SPI_0_MOSI_With_MISO(spi_device->pin_swap_enable); - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(spi_device->mode); - break; - default: - break; - } - - /* get spi peripheral clock */ - spi_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0 + spi_device->id); - - /* Out of maximum clock */ - if((spi_clk >> 1) < spi_device->clk ){ - return -1; - } - uint8_t div = spi_clk / spi_device->clk; - - clockCfg.dataPhase0Len = (div >> 1); - clockCfg.dataPhase1Len = (div >> 1); - clockCfg.startLen = (div >> 1); - clockCfg.stopLen = (div >> 1); - clockCfg.intervalLen = (div >> 1); - - if(div % 2){ - /* When Phase0 and Phase1 are not equal, increase the high level time */ - if((uint8_t)spi_device->clk_polaraity == (uint8_t)spi_device->clk_phase){ - clockCfg.dataPhase0Len += 1; - }else{ - clockCfg.dataPhase1Len += 1; - } - } - - SPI_ClockConfig(spi_device->id, &clockCfg); - - /* Continuous transmission is enabled by default */ - spiCfg.continuousEnable = 1; - - if (spi_device->direction == SPI_LSB_BYTE0_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; - } else if (spi_device->direction == SPI_LSB_BYTE3_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_LSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST; - } else if (spi_device->direction == SPI_MSB_BYTE0_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE0_FIRST; - } else if (spi_device->direction == SPI_MSB_BYTE3_DIRECTION_FIRST) { - spiCfg.bitSequence = SPI_BIT_INVERSE_MSB_FIRST; - spiCfg.byteSequence = SPI_BYTE_INVERSE_BYTE3_FIRST; - } - - spiCfg.clkPolarity = spi_device->clk_polaraity; - spiCfg.clkPhaseInv = spi_device->clk_phase; - spiCfg.frameSize = spi_device->datasize; - - if (spi_device->delitch_cnt) { - spiCfg.deglitchEnable = 1; - SPI_SetDeglitchCount(spi_device->id, spi_device->delitch_cnt - 1); - }else{ - spiCfg.deglitchEnable = 0; - } - - /* SPI config */ - SPI_Init(spi_device->id, &spiCfg); - - if(fifoCfg.txFifoThreshold){ - fifoCfg.txFifoThreshold = spi_device->fifo_threshold - 1; - fifoCfg.rxFifoThreshold = spi_device->fifo_threshold - 1; - }else{ - fifoCfg.txFifoThreshold = spi_device->fifo_threshold; - fifoCfg.rxFifoThreshold = spi_device->fifo_threshold; - } - fifoCfg.txFifoDmaEnable = DISABLE; - fifoCfg.rxFifoDmaEnable = DISABLE; - - if (oflag & DEVICE_OFLAG_INT_TX || oflag & DEVICE_OFLAG_INT_RX) { -#ifdef BSP_USING_SPI0 - if(spi_device->id == 0){ - Interrupt_Handler_Register(SPI0_IRQn, SPI0_IRQ_Function); - } -#endif -#ifdef BSP_USING_SPI1 - if(spi_device->id == 1){ - Interrupt_Handler_Register(SPI1_IRQn, SPI1_IRQ_Function); - } -#endif - } - - if (oflag & DEVICE_OFLAG_DMA_TX) { - fifoCfg.txFifoDmaEnable = ENABLE; - } - - if (oflag & DEVICE_OFLAG_DMA_RX) { - fifoCfg.rxFifoDmaEnable = ENABLE; - } - - SPI_FifoConfig(spi_device->id, &fifoCfg); - /* Enable spi master mode */ - SPI_Enable(spi_device->id, spi_device->mode); - - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int spi_close(struct device *dev) -{ - spi_device_t *spi_device = (spi_device_t *)dev; - - SPI_DeInit(spi_device->id); - - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int spi_control(struct device *dev, int cmd, void *args) -{ - spi_device_t *spi_device = (spi_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT /* constant-expression */: - - break; - - case DEVICE_CTRL_CLR_INT /* constant-expression */: - /* code */ - break; - - case DEVICE_CTRL_GET_INT /* constant-expression */: - /* code */ - break; - - case DEVICE_CTRL_RESUME: - /* code */ - SPI_Enable(spi_device->id, spi_device->mode); - break; - - case DEVICE_CTRL_SUSPEND: - SPI_Disable(spi_device->id, spi_device->mode); - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - spi_device->tx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_ATTACH_RX_DMA: - spi_device->rx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_SPI_CONFIG_CLOCK: - SPI_SetClock(spi_device->id, (uint32_t)(uintptr_t)args); - break; - - case DEVICE_CTRL_TX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_TX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_DMA_RX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_RX; - break; - } - - case DEVICE_CTRL_TX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_TX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_DMA_RX_EN); - BL_WR_REG(spiAddr[spi_device->id], SPI_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_RX; - break; - } - case DEVICE_CTRL_SPI_GET_TX_FIFO : - return SPI_GetTxFifoCount(spi_device->id); - - case DEVICE_CTRL_SPI_GET_RX_FIFO : - return SPI_GetRxFifoCount(spi_device->id); - - case DEVICE_CTRL_SPI_CLEAR_TX_FIFO : - return SPI_ClrTxFifo(spi_device->id); - - case DEVICE_CTRL_SPI_CLEAR_RX_FIFO : - return SPI_ClrRxFifo(spi_device->id); - - case DEVICE_CTRL_SPI_GET_BUS_BUSY_STATUS : - return SPI_GetBusyStatus(spi_device->id); - - case DEVICE_CTRL_SPI_SET_FRAME_SIZE: - SPI_SetFrameSize(spi_device->id, (uint32_t)(uintptr_t)args); - spi_device->datasize = (uint32_t)(uintptr_t)args; - break; - default: - break; - } - - return 0; -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int spi_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - int ret = 0; - spi_device_t *spi_device = (spi_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)spi_device->tx_dma; - if (!dma_ch) { - return -1; - } - /* Set valid width for each fifo entry */ - if(spi_device->datasize != DMA_DEV(dma_ch)->dst_width){ - switch (DMA_DEV(dma_ch)->dst_width) { - case DMA_TRANSFER_WIDTH_8BIT: - SPI_SetFrameSize(spi_device->id, SPI_FRAME_SIZE_8); - break; - case DMA_TRANSFER_WIDTH_16BIT: - SPI_SetFrameSize(spi_device->id, SPI_FRAME_SIZE_16); - break; - - case DMA_TRANSFER_WIDTH_32BIT: - SPI_SetFrameSize(spi_device->id, SPI_FRAME_SIZE_32); - break; - default: - break; - } - spi_device->datasize = DMA_DEV(dma_ch)->dst_width; - } - - if(spi_device->id == 0){ - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_SPI0_TDR, size); - }else if(spi_device->id == 1){ - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_SPI1_TDR, size); - } - dma_channel_start(dma_ch); - - return ret; - - } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { - return -2; - } else { - SPI_ClrRxFifo(spi_device->id); - ret = SPI_SendData(spi_device->id, (void *)buffer, size, SPI_TIMEOUT_DISABLE); - return 0; - } -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int spi_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - int ret = 0; - spi_device_t *spi_device = (spi_device_t *)dev; - - if (dev->oflag & DEVICE_OFLAG_DMA_RX) { - struct device *dma_ch = (struct device *)spi_device->rx_dma; - if (!dma_ch) { - return -1; - } - - /* Set valid width for each fifo entry */ - uint32_t tmpVal = BL_RD_REG(spiAddr[spi_device->id], SPI_CONFIG); - switch (DMA_DEV(dma_ch)->dst_width) { - case DMA_TRANSFER_WIDTH_8BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 0); - break; - case DMA_TRANSFER_WIDTH_16BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 1); - break; - - case DMA_TRANSFER_WIDTH_32BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, 3); - break; - default: - break; - } - BL_WR_REG(spiAddr[spi_device->id], SPI_CONFIG,tmpVal); - - if(spi_device->id == 0){ - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI0_RDR, (uint32_t)(uintptr_t)buffer, size); - }else if(spi_device->id == 1){ - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_SPI1_RDR, (uint32_t)(uintptr_t)buffer, size); - } - dma_channel_start(dma_ch); - return ret; - - } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { - return -2; - } else { - ret = SPI_ReceiveData(spi_device->id, buffer, size, SPI_TIMEOUT_DISABLE); - return 0; - } -} -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int spi_register(enum spi_index_type index, const char *name) -{ - struct device *dev; - - if (SPI_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(spix_device[index].parent); - - dev->open = spi_open; - dev->close = spi_close; - dev->control = spi_control; - dev->write = spi_write; - dev->read = spi_read; - - dev->type = DEVICE_CLASS_SPI; - dev->handle = NULL; - - return device_register(dev, name); -} - -/** - * @brief - * - * @param handle - */ -void spi_isr(spi_device_t *handle) -{ - uint32_t tmpVal; - uint32_t spix_base = spiAddr[handle->id]; - - tmpVal = BL_RD_REG(spix_base, SPI_INT_STS); - - if (!handle->parent.callback) { - return; - } - - /* Transfer end interrupt,shared by both master and slave mode */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) { - BL_WR_REG(spix_base, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR)); - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_END); - } - - /* TX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_TX_FIFO_REQ); - } - - /* RX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_RX_FIFO_REQ); - } - - /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) { - BL_WR_REG(spix_base, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR)); - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_TIMEOUT); - } - - /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) { - BL_WR_REG(spix_base, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR)); - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_SLAVE_UNDERRUN); - } - - /* TX/RX fifo overflow/underflow interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, SPI_INT_FIFO_ERROR); - } -} - -#ifdef BSP_USING_SPI0 -void SPI0_IRQ_Function() -{ - spi_isr(&spix_device[SPI0_INDEX]); -} -#endif - -#ifdef BSP_USING_SPI1 -void SPI1_IRQ_Function() -{ - spi_isr(&spix_device[SPI1_INDEX]); -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi_flash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi_flash.c deleted file mode 100644 index 4f190ae27e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_spi_flash.c +++ /dev/null @@ -1,589 +0,0 @@ -/** - * @file spi_hal_flash.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "bl808_common.h" -#include "bl808_glb.h" -#include "bl808_gpio.h" -#include "bl808_spi.h" -#include "hal_spi_flash.h" - - -#define SPI_USE_ID SPI0_ID -#define SPI_PAD_ACT GLB_SPI_PAD_ACT_AS_MASTER -#define SPI_USE_IRQ SPI0_IRQn -#define SPI_FLASH_BLK32K_SIZE (32 * 1024) -#define SPI_FLASH_BLK64K_SIZE (64 * 1024) -#define SPI_FLASH_DELAY_L (arch_delay_ms(1)) -#define SPI_FLASH_DELAY_H (arch_delay_ms(2)) - -static uint8_t spi_flash_cs_gpio = GLB_GPIO_PIN_4; -static uint8_t spi_flash_clk_gpio = GLB_GPIO_PIN_3; -static uint8_t spi_flash_mosi_gpio = GLB_GPIO_PIN_2; -static uint8_t spi_flash_miso_gpio = GLB_GPIO_PIN_1; - - -/** - * @brief SPI interrupt callback - * - * @return None - */ -static void SPI_Int_Callback(void) -{ - -} - -/** - * @brief spi flash pull cs gpio low - * - * @return None - */ -static __inline void spi_flash_pull_cs_low(void) -{ - GLB_GPIO_Write(spi_flash_cs_gpio, 0); -} - -/** - * @brief spi flash pull cs gpio high - * - * @return None - */ -static __inline void spi_flash_pull_cs_high(void) -{ - GLB_GPIO_Write(spi_flash_cs_gpio, 1); -} - -/** - * @brief spi flash gpio init - * - * @return None - */ -static void spi_flash_gpio_init(void) -{ - GLB_GPIO_Type gpioPins[3] = {spi_flash_clk_gpio, spi_flash_mosi_gpio, spi_flash_miso_gpio}; - GLB_GPIO_Cfg_Type gpioCfg = { - /* CS */ - .gpioPin=spi_flash_cs_gpio, - .gpioFun=11, - .gpioMode=GPIO_MODE_OUTPUT, - .pullType=GPIO_PULL_NONE, - .drive=3, - .smtCtrl=1 - }; - - GLB_GPIO_Func_Init(GPIO_FUN_SPI0, (GLB_GPIO_Type *)gpioPins, sizeof(gpioPins)/sizeof(gpioPins[0])); - GLB_GPIO_Init(&gpioCfg); - spi_flash_pull_cs_high(); - - if(SPI0_ID == SPI_USE_ID){ - GLB_Set_MCU_SPI_0_ACT_MOD_Sel(SPI_PAD_ACT); - }else{ - GLB_Set_DSP_SPI_0_ACT_MOD_Sel(SPI_PAD_ACT); - } -} - -/** - * @brief write enable - * - * @return None - */ -static void spi_flash_write_enable(void) -{ - uint8_t cmd[256] = {0}; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_8); - spi_flash_pull_cs_low(); - cmd[0] = 0x06; - SPI_SendData(SPI_USE_ID,cmd,1,SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); -} - -/** - * @brief wait not busy - * - * @return None - */ -static void spi_flash_wait_notbusy(void) -{ - uint32_t wdata[1] = {0x05}; - uint32_t rdata[1] = {0}; - - while(1){ - spi_flash_pull_cs_low(); - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_24); - SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - if(((uint8_t *)rdata)[1]&0x1){ - continue; - }else{ - break; - } - } -} - -/****************************************************************************//** - * @brief wait WEL 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -/** - * @brief wait WEL 0 - * - * @return None - */ -static void spi_flash_wait_wel_0(void) -{ - uint32_t wdata[1] = {0x05}; - uint32_t rdata[1] = {0}; - - while(1){ - spi_flash_pull_cs_low(); - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_24); - SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - if(((uint8_t *)rdata)[1]&(1<<1)){ - continue; - }else{ - break; - } - } -} - -/** - * @brief wait WEL 1 - * - * @return None - */ -static void spi_flash_wait_wel_1(void) -{ - uint32_t wdata[1] = {0x05}; - uint32_t rdata[1] = {0}; - - while(1){ - spi_flash_pull_cs_low(); - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_24); - SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - if(((uint8_t *)rdata)[1]&(1<<1)){ - break; - }else{ - continue; - } - } -} - -/** - * @brief spi flash sector erase - * - * @param sector number - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_sector_erase(uint32_t secNum) -{ - BL_Err_Type stat = SUCCESS; - uint32_t wdata[1] = {0}; - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - - spi_flash_pull_cs_low(); - ((uint8_t *)wdata)[0] = 0x20; - ((uint8_t *)wdata)[1] = ((secNum*4*1024)>>16)&0xFF; - ((uint8_t *)wdata)[2] = ((secNum*4*1024)>>8)&0xFF; - ((uint8_t *)wdata)[3] = ((secNum*4*1024)>>0)&0xFF; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - stat = SPI_SendData(SPI_USE_ID, wdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - spi_flash_wait_notbusy(); - spi_flash_wait_wel_0(); - - return stat; -} - -/** - * @brief spi flash block 32k erase - * - * @param block number - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_blk32_erase(uint32_t blkNum) -{ - BL_Err_Type stat = SUCCESS; - uint32_t wdata[1] = {0}; - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - - spi_flash_pull_cs_low(); - ((uint8_t *)wdata)[0] = 0x52; - ((uint8_t *)wdata)[1] = ((blkNum*SPI_FLASH_BLK32K_SIZE)>>16)&0xFF; - ((uint8_t *)wdata)[2] = ((blkNum*SPI_FLASH_BLK32K_SIZE)>>8)&0xFF; - ((uint8_t *)wdata)[3] = ((blkNum*SPI_FLASH_BLK32K_SIZE)>>0)&0xFF; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - stat = SPI_SendData(SPI_USE_ID, wdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - spi_flash_wait_notbusy(); - spi_flash_wait_wel_0(); - - return stat; -} - -/** - * @brief spi flash block 64k erase - * - * @param block number - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_blk64_erase(uint32_t blkNum) -{ - BL_Err_Type stat = SUCCESS; - uint32_t wdata[1] = {0}; - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - - spi_flash_pull_cs_low(); - ((uint8_t *)wdata)[0] = 0xd8; - ((uint8_t *)wdata)[1] = ((blkNum*SPI_FLASH_BLK64K_SIZE)>>16)&0xFF; - ((uint8_t *)wdata)[2] = ((blkNum*SPI_FLASH_BLK64K_SIZE)>>8)&0xFF; - ((uint8_t *)wdata)[3] = ((blkNum*SPI_FLASH_BLK64K_SIZE)>>0)&0xFF; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - stat = SPI_SendData(SPI_USE_ID, wdata, 1, SPI_TIMEOUT_ENABLE); - spi_flash_pull_cs_high(); - - spi_flash_wait_notbusy(); - spi_flash_wait_wel_0(); - - return stat; -} - -/** - * @brief spi flash page write - * - * @param flashAddr: flash address - * @param wBuff: write buff - * @param wLen: write length - * @return BL_Err_Type - */ -static BL_Err_Type spi_flash_page_write(uint32_t flashAddr, uint8_t *wBuff, uint32_t wLen) -{ - uint32_t i; - uint8_t cmd[260] = {0}; - - if ((!wLen) || (wLen>256)) { - SPI_FLASH_DELAY_H; - return ERROR; - } - if (flashAddr & 0xFF) { - SPI_FLASH_DELAY_H; - } - - spi_flash_wait_notbusy(); - spi_flash_write_enable(); - spi_flash_wait_wel_1(); - - spi_flash_pull_cs_low(); - cmd[0] = 0x02; - cmd[1] = (flashAddr>>16)&0xFF; - cmd[2] = (flashAddr>>8)&0xFF; - cmd[3] = (flashAddr>>0)&0xFF; - for (i=0; i256)) { - SPI_FLASH_DELAY_L; - return ERROR; - } - if (flashAddr & 0xFF) { - SPI_FLASH_DELAY_H; - } - - spi_flash_wait_notbusy(); - - spi_flash_pull_cs_low(); - cmd[0] = 0x03; - cmd[1] = (flashAddr>>16)&0xFF; - cmd[2] = (flashAddr>>8)&0xFF; - cmd[3] = (flashAddr>>0)&0xFF; - for (i=4; i<260; i++) { - cmd[i] = 0; - } - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_8); - stat = SPI_SendRecvData(SPI_USE_ID, cmd, resp, rLen+4, SPI_TIMEOUT_DISABLE); - spi_flash_pull_cs_high(); - if(stat != SUCCESS){ - return stat; - } - - arch_memcpy(rBuff, resp+4, rLen); - - return SUCCESS; -} - - -/** - * @brief spi flash select gpio - * - * @param clk: clk gpio - * @param cs: cs gpio - * @param mosi: mosi gpio - * @param miso: miso gpio - * @return None - */ -void spi_flash_set_gpio(uint8_t clk, uint8_t cs, uint8_t mosi, uint8_t miso) -{ - spi_flash_cs_gpio = cs; - spi_flash_clk_gpio = clk; - spi_flash_mosi_gpio = mosi; - spi_flash_miso_gpio = miso; -} - -/** - * @brief spi flash init - * - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_init(void) -{ - SPI_CFG_Type spiCfg = { - DISABLE, /* Disable de-glitch function */ - SPI_SLAVE_PIN_4, /* SPI 4-pin mode(CS is enabled) */ - ENABLE, /* Disable master continuous transfer mode */ - SPI_BYTE_INVERSE_BYTE0_FIRST, /* The byte 0 is sent first in SPI transfer */ - SPI_BIT_INVERSE_MSB_FIRST, /* MSB is sent first in SPI transfer */ - SPI_CLK_PHASE_INVERSE_0, /* SPI clock phase */ - SPI_CLK_POLARITY_LOW, /* SPI clock plarity */ - SPI_FRAME_SIZE_32 /* SPI frame size 8-bit(also the valid width for each fifo entry) */ - }; - - SPI_ClockCfg_Type clockCfg = { - 1, /* Length of start condition */ - 1, /* Length of stop condition */ - 1, /* Length of data phase 0,affecting clock */ - 1, /* Length of data phase 1,affecting clock */ - 1 /* Length of interval between frame */ - }; - - /* gpio and pad init */ - spi_flash_gpio_init(); - - /* GLB SPI clock config */ - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, 0); - - /* SPI interrupt config */ - SPI_Int_Callback_Install(SPI_USE_ID, SPI_INT_END, SPI_Int_Callback); - SPI_IntMask(SPI_USE_ID, SPI_INT_ALL, MASK); - SPI_IntMask(SPI_USE_ID, SPI_INT_END, UNMASK); - CPU_Interrupt_Enable(SPI_USE_IRQ); - System_NVIC_SetPriority(SPI_USE_IRQ, 4, 1); - - /* SPI config */ - SPI_Init(SPI_USE_ID, &spiCfg); - - /* Set SPI clock */ - SPI_ClockConfig(SPI_USE_ID, &clockCfg); - - /* Enable spi master mode */ - SPI_Enable(SPI_USE_ID, SPI_WORK_MODE_MASTER); - - return SUCCESS; -} - -/** - * @brief spi flash read jedec id - * - * @param jedecid - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_read_jedec_id(uint8_t *data) -{ - uint32_t wdata[1] = {0x9f}; - uint32_t rdata[1] = {0}; - BL_Err_Type stat = SUCCESS; - - SPI_SetFrameSize(SPI_USE_ID, SPI_FRAME_SIZE_32); - spi_flash_pull_cs_low(); - stat = SPI_SendRecvData(SPI_USE_ID, wdata, rdata, 1, SPI_TIMEOUT_ENABLE); - if(stat != SUCCESS) { - return stat; - } - spi_flash_pull_cs_high(); - if((0xFF==((uint8_t *)rdata)[1]) && (0xFF==((uint8_t *)rdata)[2]) && (0xFF==((uint8_t *)rdata)[3])) { - return ERROR; - } - - rdata[0] = (rdata[0]>>8); - arch_memcpy((uint8_t *)data, (uint8_t *)&rdata[0], 3); - - return stat; -} - -/** - * @brief spi flash read data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_read(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat = SUCCESS; - uint32_t i; - uint32_t curLen; - - for (i = 0; i < len;) { - curLen = len - i; - if (curLen >= 256) { - curLen = 256; - } - - stat = spi_flash_page_read(addr, data, curLen); - if (stat != SUCCESS) { - return stat; - } - spi_flash_wait_notbusy(); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} - -/** - * @brief spi flash write data - * - * @param addr - * @param data - * @param len - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_write(uint32_t addr, uint8_t *data, uint32_t len) -{ - BL_Err_Type stat = SUCCESS; - uint32_t i; - uint32_t curLen; - - for (i = 0; i < len;) { - /* Get current programmed length within page size */ - curLen = 256 - addr % 256; - - if (curLen > len - i) { - curLen = len - i; - } - - stat = spi_flash_page_write(addr, data, curLen); - if (stat != SUCCESS) { - return stat; - } - spi_flash_wait_notbusy(); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} - -/** - * @brief spi flash erase - * - * @param startaddr - * @param erase len - * @return BL_Err_Type - */ -BL_Err_Type spi_flash_erase(uint32_t startaddr, uint32_t len) -{ - uint32_t eraseLen = 0; - uint32_t endaddr = startaddr + len - 1; - BL_Err_Type stat = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if ((startaddr & (SPI_FLASH_BLK64K_SIZE - 1)) == 0 && - len > (SPI_FLASH_BLK64K_SIZE - 4 * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - stat = spi_flash_blk64_erase(startaddr / SPI_FLASH_BLK64K_SIZE); - eraseLen = SPI_FLASH_BLK64K_SIZE; - } else if ((startaddr & (SPI_FLASH_BLK32K_SIZE - 1)) == 0 && - len > (SPI_FLASH_BLK32K_SIZE - 4 * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - stat = spi_flash_blk32_erase(startaddr / SPI_FLASH_BLK32K_SIZE); - eraseLen = SPI_FLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(4 - 1))); - stat = spi_flash_sector_erase(startaddr / 4 / 1024); - eraseLen = 4 * 1024; - } - - startaddr += eraseLen; - - if (stat != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_uart.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_uart.c deleted file mode 100644 index ef0dd2562d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_uart.c +++ /dev/null @@ -1,528 +0,0 @@ -/** - * @file hal_uart.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_uart.h" -#include "hal_dma.h" -#include "bl808_uart.h" -#include "bl808_glb.h" -#include "uart_config.h" - -#ifdef BSP_USING_UART0 -void UART0_IRQ(void); -#endif -#ifdef BSP_USING_UART1 -void UART1_IRQ(void); -#endif -#ifdef BSP_USING_UART2 -void UART2_IRQ(void); -#endif -#ifdef BSP_USING_UART3 -void UART3_IRQ(void); -#endif - -uart_device_t uartx_device[UART_MAX_INDEX] = { -#ifdef BSP_USING_UART0 - UART0_CONFIG, -#endif -#ifdef BSP_USING_UART1 - UART1_CONFIG, -#endif -#ifdef BSP_USING_UART2 - UART2_CONFIG, -#endif -#ifdef BSP_USING_UART3 - UART3_CONFIG, -#endif -}; - -static const uint32_t uartAddr[] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE }; - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int uart_open(struct device *dev, uint16_t oflag) -{ - uart_device_t *uart_device = (uart_device_t *)dev; - UART_FifoCfg_Type fifoCfg = { 0 }; - UART_CFG_Type uart_cfg = { 0 }; - uint32_t uart_clk; - - /* disable all interrupt */ - UART_IntMask(uart_device->id, UART_INT_ALL, MASK); - /* disable uart before config */ - UART_Disable(uart_device->id, UART_TXRX); - - uart_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0 + uart_device->id); - - uart_cfg.baudRate = uart_device->baudrate; - uart_cfg.dataBits = uart_device->databits; - uart_cfg.stopBits = uart_device->stopbits; - uart_cfg.parity = uart_device->parity; - uart_cfg.uartClk = uart_clk; - uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; - uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; - uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; - uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE; - uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE; - uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE; - uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT; - - /* uart init with default configuration */ - UART_Init(uart_device->id, &uart_cfg); - - /* Enable tx free run mode */ - UART_TxFreeRun(uart_device->id, ENABLE); - - /* Set rx time-out value */ - UART_SetRxTimeoutValue(uart_device->id, UART_DEFAULT_RTO_TIMEOUT); - - fifoCfg.txFifoDmaThreshold = uart_device->fifo_threshold; - fifoCfg.txFifoDmaEnable = DISABLE; - fifoCfg.rxFifoDmaThreshold = uart_device->fifo_threshold; - fifoCfg.rxFifoDmaEnable = DISABLE; - - if (oflag & DEVICE_OFLAG_STREAM_TX) { - } - - if ((oflag & DEVICE_OFLAG_INT_TX) || (oflag & DEVICE_OFLAG_INT_RX)) { -#ifdef BSP_USING_UART0 - if (uart_device->id == UART0_ID) { - Interrupt_Handler_Register(UART0_IRQn, UART0_IRQ); - } -#endif -#ifdef BSP_USING_UART1 - if (uart_device->id == UART1_ID) { - Interrupt_Handler_Register(UART1_IRQn, UART1_IRQ); - } -#endif -#ifdef BSP_USING_UART2 - if (uart_device->id == UART2_ID) { - Interrupt_Handler_Register(UART2_IRQn, UART2_IRQ); - } -#endif -#ifdef BSP_USING_UART3 - if (uart_device->id == UART0_MM_ID) { - Interrupt_Handler_Register(UART3_IRQn, UART3_IRQ); - } -#endif - } - - if (oflag & DEVICE_OFLAG_DMA_TX) { - fifoCfg.txFifoDmaEnable = ENABLE; - } - - if (oflag & DEVICE_OFLAG_DMA_RX) { - fifoCfg.rxFifoDmaEnable = ENABLE; - } - - UART_FifoConfig(uart_device->id, &fifoCfg); - - UART_TxFifoClear(uart_device->id); - UART_RxFifoClear(uart_device->id); - - /* enable uart */ - UART_Enable(uart_device->id, UART_TXRX); - return 0; -} -/** - * @brief - * - * @param dev - * @return int - */ -int uart_close(struct device *dev) -{ - uart_device_t *uart_device = (uart_device_t *)dev; - - UART_Disable(uart_device->id, UART_TXRX); - return 0; -} -/** - * @brief - * - * @param dev - * @param cmd - * @param args - * @return int - */ -int uart_control(struct device *dev, int cmd, void *args) -{ - uart_device_t *uart_device = (uart_device_t *)dev; - - switch (cmd) { - case DEVICE_CTRL_SET_INT: { - int offset = __builtin_ctz((uint32_t)(uintptr_t)args); - - while (offset < 9) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - UART_IntMask(uart_device->id, offset, UNMASK); - } - - offset++; - } - - if (uart_device->id == UART0_ID) { - CPU_Interrupt_Enable(UART0_IRQn); - } else if (uart_device->id == UART1_ID) { - CPU_Interrupt_Enable(UART1_IRQn); - } else if (uart_device->id == UART2_ID) { - CPU_Interrupt_Enable(UART2_IRQn); - } else if (uart_device->id == UART0_MM_ID) { - CPU_Interrupt_Enable(UART3_IRQn); - } - - break; - } - - case DEVICE_CTRL_CLR_INT: { - int offset = __builtin_ctz((uint32_t)(uintptr_t)args); - - while (offset < 9) { - if ((uint32_t)(uintptr_t)args & (1 << offset)) { - UART_IntMask(uart_device->id, offset, MASK); - } - - offset++; - } - - if (uart_device->id == UART0_ID) { - CPU_Interrupt_Disable(UART0_IRQn); - } else if (uart_device->id == UART1_ID) { - CPU_Interrupt_Disable(UART1_IRQn); - } else if (uart_device->id == UART2_ID) { - CPU_Interrupt_Disable(UART2_IRQn); - } else if (uart_device->id == UART0_MM_ID) { - CPU_Interrupt_Disable(UART3_IRQn); - } - - break; - } - - case DEVICE_CTRL_GET_INT: - break; - - case DEVICE_CTRL_CONFIG: { - uart_param_cfg_t *cfg = (uart_param_cfg_t *)args; - UART_CFG_Type uart_cfg = { 0 }; - - /* Disable uart before config */ - UART_Disable(uart_device->id, UART_TXRX); - uint32_t uart_clk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0); - - uart_cfg.uartClk = uart_clk; - uart_cfg.baudRate = cfg->baudrate; - uart_cfg.stopBits = cfg->stopbits; - uart_cfg.parity = cfg->parity; - uart_cfg.dataBits = cfg->databits; - uart_cfg.ctsFlowControl = UART_CTS_FLOWCONTROL_ENABLE; - uart_cfg.rtsSoftwareControl = UART_RTS_FLOWCONTROL_ENABLE; - uart_cfg.byteBitInverse = UART_MSB_FIRST_ENABLE; - uart_cfg.txSoftwareControl = UART_TX_SWCONTROL_ENABLE; - uart_cfg.txLinMode = UART_TX_LINMODE_ENABLE; - uart_cfg.rxLinMode = UART_RX_LINMODE_ENABLE; - uart_cfg.txBreakBitCnt = UART_TX_BREAKBIT_CNT; - UART_Init(uart_device->id, &uart_cfg); - - UART_TxFifoClear(uart_device->id); - UART_RxFifoClear(uart_device->id); - - /* Enable uart */ - UART_Enable(uart_device->id, UART_TXRX); - break; - } - - case DEVICE_CTRL_GET_CONFIG: - break; - - case DEVICE_CTRL_ATTACH_TX_DMA: - uart_device->tx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_ATTACH_RX_DMA: - uart_device->rx_dma = (struct device *)args; - break; - - case DEVICE_CTRL_TX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_SUSPEND: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag &= ~DEVICE_OFLAG_DMA_RX; - break; - } - - case DEVICE_CTRL_TX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_TX; - break; - } - - case DEVICE_CTRL_RX_DMA_RESUME: { - uint32_t tmpVal = BL_RD_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN); - BL_WR_REG(uartAddr[uart_device->id], UART_FIFO_CONFIG_0, tmpVal); - dev->oflag |= DEVICE_OFLAG_DMA_RX; - break; - } - - case DEVICE_CTRL_UART_GET_TX_FIFO: - return UART_GetTxFifoCount(uart_device->id); - - case DEVICE_CTRL_UART_GET_RX_FIFO: - return UART_GetRxFifoCount(uart_device->id); - - default: - break; - } - - return 0; -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int uart_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ - int ret = 0; - uart_device_t *uart_device = (uart_device_t *)dev; - if (dev->oflag & DEVICE_OFLAG_DMA_TX) { - struct device *dma_ch = (struct device *)uart_device->tx_dma; - if (!dma_ch) - return -1; - - if (uart_device->id == 0) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART0_TDR, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 1) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART1_TDR, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 2) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART2_TDR, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 3) { - ret = dma_reload(dma_ch, (uint32_t)(uintptr_t)buffer, (uint32_t)DMA_ADDR_UART3_TDR, size); - dma_channel_start(dma_ch); - } - return ret; - } else if (dev->oflag & DEVICE_OFLAG_INT_TX) { - return -2; - } else - return UART_SendData(uart_device->id, (uint8_t *)buffer, size); -} -/** - * @brief - * - * @param dev - * @param pos - * @param buffer - * @param size - * @return int - */ -int uart_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ - int ret = -1; - uart_device_t *uart_device = (uart_device_t *)dev; - if (dev->oflag & DEVICE_OFLAG_DMA_RX) { - struct device *dma_ch = (struct device *)uart_device->rx_dma; - if (!dma_ch) - return -1; - - if (uart_device->id == 0) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART0_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 1) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART1_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 2) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART2_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } else if (uart_device->id == 3) { - ret = dma_reload(dma_ch, (uint32_t)DMA_ADDR_UART3_RDR, (uint32_t)(uintptr_t)buffer, size); - dma_channel_start(dma_ch); - } - return ret; - } else if (dev->oflag & DEVICE_OFLAG_INT_RX) { - return -2; - } else { - return UART_ReceiveData(uart_device->id, (uint8_t *)buffer, size); - } -} -/** - * @brief - * - * @param index - * @param name - * @param flag - * @return int - */ -int uart_register(enum uart_index_type index, const char *name) -{ - struct device *dev; - - if (UART_MAX_INDEX == 0) { - return -DEVICE_EINVAL; - } - - dev = &(uartx_device[index].parent); - - dev->open = uart_open; - dev->close = uart_close; - dev->control = uart_control; - dev->write = uart_write; - dev->read = uart_read; - - dev->type = DEVICE_CLASS_UART; - dev->handle = NULL; - - return device_register(dev, name); -} -/** - * @brief - * - * @param handle - */ -void uart_isr(uart_device_t *handle) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[handle->id]; - - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - maskVal = BL_RD_REG(UARTx, UART_INT_MASK); - - if (!handle->parent.callback) { - return; - } - - /* Length of uart tx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x1); - handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_END); - } - - /* Length of uart rx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x2); - handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_RX_END); - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, UART_EVENT_TX_FIFO); - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) { - uint8_t buffer[UART_FIFO_MAX_LEN]; - uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN); - - if (len) { - handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RX_FIFO); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x10); - uint8_t buffer[UART_FIFO_MAX_LEN]; - uint8_t len = UART_ReceiveData(handle->id, buffer, UART_FIFO_MAX_LEN); - - if (len) { - handle->parent.callback(&handle->parent, &buffer[0], len, UART_EVENT_RTO); - } - } - - /* Rx parity check error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 0x20); - handle->parent.callback(&handle->parent, NULL, 0, UART_PCE_IT); - } - - /* Tx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, UART_TX_FER_IT); - } - - /* Rx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { - handle->parent.callback(&handle->parent, NULL, 0, UART_RX_FER_IT); - } -} - -#ifdef BSP_USING_UART0 -/** - * @brief - * - */ -void UART0_IRQ(void) -{ - uart_isr(&uartx_device[UART0_INDEX]); -} -#endif -#ifdef BSP_USING_UART1 -/** - * @brief - * - */ -void UART1_IRQ(void) -{ - uart_isr(&uartx_device[UART1_INDEX]); -} -#endif -#ifdef BSP_USING_UART2 -/** - * @brief - * - */ -void UART2_IRQ(void) -{ - uart_isr(&uartx_device[UART2_INDEX]); -} -#endif -#ifdef BSP_USING_UART3 -/** - * @brief - * - */ -void UART3_IRQ(void) -{ - uart_isr(&uartx_device[UART3_INDEX]); -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_usb.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_usb.c deleted file mode 100644 index d0080bcf08..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/hal_drv/src/hal_usb.c +++ /dev/null @@ -1,1291 +0,0 @@ -/** - * @file hal_usb.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "hal_usb.h" -#include "bl808_usb.h" -#include "bl808_glb.h" - -#ifndef CONFIG_USB_VDMA_ENABLE -#define CONFIG_USB_VDMA_ENABLE -#endif - -#ifndef CONFIG_USB_PINGPONG_ENABLE -// #define CONFIG_USB_PINGPONG_ENABLE -#endif - -#ifndef CONFIG_USB_VDMA_OUT_ENABLE -// #define CONFIG_USB_VDMA_OUT_ENABLE -#endif - -#define MIN(a, b) (((a) < (b)) ? (a) : (b)) - -#define USB_DC_LOG_WRN(a, ...) //printf(a, ##__VA_ARGS__) -#define USB_DC_LOG_DBG(a, ...) -#define USB_DC_LOG_ERR(a, ...) //printf(a, ##__VA_ARGS__) -#define USB_DC_LOG(a, ...) //printf(a, ##__VA_ARGS__) - -static uint8_t fifo_ep_map[4] = { 0, 0, 0, 0 }; - -static usb_dc_device_t usb_hs_device __attribute__((section(".RW_OCRAM_NOINIT"))); -static void USBD_IRQHandler(void); - -static uint8_t usb_ep_is_enabled(uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if ep enabled */ - if ((USB_EP_DIR_IS_OUT(ep)) && - usb_hs_device.out_ep[ep_idx].ep_ena) { - return 1; - } else if ((USB_EP_DIR_IS_IN(ep)) && - usb_hs_device.in_ep[ep_idx].ep_ena) { - return 1; - } - - return 0; -} -#ifndef CONFIG_USB_VDMA_ENABLE -static int usb_dma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_MEM_2_FIFO; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - csi_dcache_clean_range((uint32_t *)data, len); - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - return 0; -} - -static int usb_dma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_DMA_Cfg_Type dma_cfg; - - dma_cfg.dir = USB_DMA_TRANS_DIR_FIFO_2_MEM; - dma_cfg.memAddr = (uint32_t)(uintptr_t)data; - dma_cfg.length = len; - - /* dma config */ - USB_Set_DMA_Config(fifo_num, &dma_cfg); - /* dma start */ - USB_Set_DMA_Start(); - /* dma wait */ - while (1) { - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - USB_DC_LOG_ERR("dma error\r\n"); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return -USB_DC_DMA_ERR; - } - if (USB_Get_Sub_Group_2_IntStatus() & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - USB_Reset_DMA_Accessing_Fifo(); - csi_dcache_invalid_range((uint32_t *)data, len); - return 0; -} -#else -static int usb_vdma_write(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - - csi_dcache_clean_range((uint32_t *)data, len); - - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - return 0; -} - -static int usb_vdma_read(uint8_t fifo_num, const uint8_t *data, uint32_t len) -{ - uint32_t timeout = 0xffffff; - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = len; - USB_Set_VDMA_Config(fifo_num, &vdma_fifo_cfg); - USB_Set_VDMA_Start(fifo_num); - - while (USB_Get_VDMA_Start(fifo_num)) { - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("fifo%d wait free timeout\r\n", fifo_num); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - - csi_dcache_invalid_range((uint32_t *)data, len); - return 0; -} -#endif - -static uint8_t usb_get_transfer_fifo(uint8_t ep_idx) -{ - uint8_t target_fifo_id; - - if (usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps > 512 || usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps > 512) { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (4 * ep_idx - 3); -#else - target_fifo_id = (2 * ep_idx - 1); -#endif - } else { -#ifdef CONFIG_USB_PINGPONG_ENABLE - target_fifo_id = (2 * ep_idx - 1); -#else - target_fifo_id = ep_idx; -#endif - } - - return target_fifo_id; -} - -/** - * @brief - * - * @param dev - * @param oflag - * @return int - */ -int usb_dc_init(void) -{ - CPU_Interrupt_Disable(USB_IRQn); - - PDS_Turn_On_USB(1); - - /* interrupt config */ - USB_Global_IntEnable(DISABLE); - - /* software reset usb */ - USB_NORMAL_Cfg_Type usbNormalCfg = { -#ifdef CONFIG_USB_HS - .forceFullSpeed = 0, -#else - .forceFullSpeed = 1, -#endif - .chipEn = 1, - .swRst = 1, - .remoteWakeupEn = 0, - .rstTimeOut = 0xFFFF - }; - USB_Set_Normal_Config(&usbNormalCfg); -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - USB_Set_Device_Address(0); - USB_Non_Ctrl_Transfer_Disable(); - - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - - USB_Group_IntMask(USB_GRP_INT_G0, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G1, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G2, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G3, UNMASK); - USB_Group_IntMask(USB_GRP_INT_G4, UNMASK); - - USB_Global_IntMask(USB_GLOBAL_INT_DEV, UNMASK); - USB_Global_IntMask(USB_GLOBAL_INT_OTG, MASK); - USB_Global_IntMask(USB_GLOBAL_INT_HC, MASK); - - USB_Sub_Group_IntMask(USB_INT_DMA_CMPLT | USB_INT_DMA_ERROR | USB_INT_IDLE | USB_INT_RX0BYTE | USB_INT_TX0BYTE); - USB_Sub_Group_IntMask(USB_INT_VDMA_CMPLT_CXF | USB_INT_VDMA_CMPLT_F0 | USB_INT_VDMA_CMPLT_F1 | USB_INT_VDMA_CMPLT_F2 | USB_INT_VDMA_CMPLT_F3 | - USB_INT_VDMA_ERROR_CXF | USB_INT_VDMA_ERROR_F0 | USB_INT_VDMA_ERROR_F1 | USB_INT_VDMA_ERROR_F2 | USB_INT_VDMA_ERROR_F3); - - USB_Sub_Group_IntUnmask(USB_INT_CX_SETUP | USB_INT_CX_IN | USB_INT_CX_OUT | USB_INT_CX_COMFAIL | USB_INT_CX_COMABORT); - USB_Sub_Group_IntUnmask(USB_INT_RESET | USB_INT_SUSPEND | USB_INT_RESUME | USB_INT_RX0BYTE); - - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK | USB_SUB_GROUP_2_SUSPEND_BIT_MUSK | USB_SUB_GROUP_2_RESUME_BIT_MUSK | - USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK | USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK | - USB_SUB_GROUP_2_CMPLT_BIT_MUSK | USB_SUB_GROUP_2_ERROR_BIT_MUSK); - USB_Get_Sub_Group_3_IntClear(0xffffffff); //VDMA INT - USB_Get_Sub_Group_4_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - - /* modify ep1 ~ ep8 fifo map ,default is fifo3 */ - for (uint8_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - USB_Set_FIFO_Of_Endpoint_IN(i, 15); - USB_Set_FIFO_Of_Endpoint_OUT(i, 15); - } - -#ifdef CONFIG_USB_VDMA_ENABLE - USB_Set_VDMA_Enable(); -#endif - - memset(&usb_hs_device, 0, sizeof(usb_hs_device)); - - usb_hs_device.out_ep[0].ep_ena = 1U; - usb_hs_device.in_ep[0].ep_ena = 1U; - usb_hs_device.out_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.out_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - usb_hs_device.in_ep[0].ep_cfg.ep_mps = 64; - usb_hs_device.in_ep[0].ep_cfg.ep_type = USBD_EP_TYPE_CTRL; - - Interrupt_Handler_Register(USB_IRQn, USBD_IRQHandler); - CPU_Interrupt_Enable(USB_IRQn); - USB_SoftDetach_Disable(); - USB_Global_IntEnable(ENABLE); - - return 0; -} - -/** - * @brief Set USB device address - * - * @param[in] addr Device address - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_set_address(const uint8_t addr) -{ - USB_Set_Device_Address(addr); - return 0; -} - -/** - * @brief configure and enable endpoint - * This function sets endpoint configuration according to one specified in USB - * endpoint descriptor and then enables it for data transfers. - * - * @param dev - * @param ep_cfg ep_cfg Endpoint - * @return int - */ -int usbd_ep_open(const struct usb_dc_ep_cfg *ep_cfg) -{ - uint8_t ep; - USB_FIFO_Cfg_Type fifo_cfg; - - if (!ep_cfg) { - return -1; - } - - ep = ep_cfg->ep_addr; - - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx > 4) { - return -1; - } - - USB_DC_LOG_DBG("%s ep %x, mps %d, type %d\r\n", __func__, ep, ep_cfg->ep_mps, ep_cfg->ep_type); - - if (ep_idx == 0) { - return 0; - } - - fifo_cfg.enable = 1; - fifo_cfg.fifoType = ep_cfg->ep_type; - fifo_cfg.epID = ep_idx; - - if (USB_EP_DIR_IS_OUT(ep)) { - fifo_cfg.dir = USB_FIFO_DIR_OUT; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.out_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.out_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_OUT_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - - } else { - fifo_cfg.dir = USB_FIFO_DIR_IN; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps = ep_cfg->ep_mps; - usb_hs_device.in_ep[ep_idx].ep_cfg.ep_type = ep_cfg->ep_type; - usb_hs_device.in_ep[ep_idx].ep_ena = 1U; - - USB_Set_Endpoint_IN_MaxPacketSize(ep_idx, ep_cfg->ep_mps); - } - -#ifndef CONFIG_USB_PINGPONG_ENABLE - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_SINGLE_BLOCK; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 4) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x02; - fifo_ep_map[2] = 0x03; - fifo_ep_map[3] = 0x04; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_1); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_3, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_4, USB_FIFO_3); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_4, USB_FIFO_3); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 2 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } else { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - - if (ep_cfg->ep_type == 0x01) { - uint32_t tmpVal; - tmpVal = BL_RD_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_TX_NUM_HBW_IEP1, 0); - BL_WR_WORD(USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (ep_idx - 1), tmpVal); - } - } -#else - fifo_cfg.blockType = USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS; - - if (ep_cfg->ep_mps <= 512) { - if (ep_idx > 2) { - return -1; - } - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x02; - fifo_ep_map[3] = 0x02; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_2, USB_FIFO_2); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_2, USB_FIFO_2); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_512; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT + 4 * (ep_idx - 1))); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0 + 2 * (ep_idx - 1))); - } - } else { - if (ep_idx > 1) { - return -1; - } - - fifo_ep_map[0] = 0x01; - fifo_ep_map[1] = 0x01; - fifo_ep_map[2] = 0x01; - fifo_ep_map[3] = 0x01; - - USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_1, USB_FIFO_0); - USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_1, USB_FIFO_0); - - fifo_cfg.blockSize = USB_FIFO_BLOCK_MAX_SIZE_1024; - USB_Set_FIFO_Config(2 * ep_idx - 2, &fifo_cfg); - fifo_cfg.enable = 0; - USB_Set_FIFO_Config(2 * ep_idx - 1, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx, &fifo_cfg); - USB_Set_FIFO_Config(2 * ep_idx + 1, &fifo_cfg); - - if (USB_EP_DIR_IS_OUT(ep)) { -#ifdef CONFIG_USB_VDMA_OUT_ENABLE - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); -#else - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP1_INT_F0_OUT)); -#endif - } else { - USB_Sub_Group_IntUnmask(1ULL << (USB_SUB_GRP3_INT_VDMA_CMPLT_F0)); - } - } -#endif - - USB_Non_Ctrl_Transfer_Enable(); - - return 0; -} - -/** - * @brief Disable the selected endpoint - * - * Function to disable the selected endpoint. Upon success interrupts are - * disabled for the corresponding endpoint and the endpoint is no longer able - * for transmitting/receiving data. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_close(const uint8_t ep) -{ - return 0; -} -/** - * @brief Set stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_set_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (USB_EP_DIR_IS_OUT(ep)) { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_OUT_Stall(ep_idx, ENABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 1U; - } - } else { - if (ep_idx == 0) { - USB_Set_CTRL_Endpoint_Stall_Once(); - } else { - USB_Set_Endpoint_IN_Stall(ep_idx, ENABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 1U; - } - } - return 0; -} -/** - * @brief Clear stall condition for the selected endpoint - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_clear_stall(const uint8_t ep) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (ep_idx) { - if (USB_EP_DIR_IS_OUT(ep)) { - USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_OUT_Stall(ep_idx, DISABLE); - usb_hs_device.out_ep[ep_idx].is_stalled = 0; - } else { - USB_Reset_Endpoint_IN_Data_Toggle_Sequence(ep_idx); - USB_Set_Endpoint_IN_Stall(ep_idx, DISABLE); - usb_hs_device.in_ep[ep_idx].is_stalled = 0; - } - } - return 0; -} -/** - * @brief Check if the selected endpoint is stalled - * - * @param dev usb device - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[out] stalled Endpoint stall status - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled) -{ - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - if (!stalled) { - return -1; - } - *stalled = 0U; - if (ep_idx == 0) - return 0; - - if (USB_EP_DIR_IS_OUT(ep)) { - if (usb_hs_device.out_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } else { - if (usb_hs_device.in_ep[ep_idx].is_stalled) { - *stalled = 1U; - } - } - - return 0; -} - -/** - * @brief Write data to the specified endpoint - * - * This function is called to write data to the specified endpoint. The - * supplied usbd_endpoint_callback function will be called when data is transmitted - * out. - * - * @param dev - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data to write - * @param[in] data_len Length of the data requested to write. This may - * be zero for a zero length status packet. - * @param[out] ret_bytes Bytes scheduled for transmission. This value - * may be NULL if the application expects all - * bytes to be written - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_write(const uint8_t ep, const uint8_t *data, uint32_t data_len, uint32_t *ret_bytes) -{ - uint32_t timeout = 0xffffff; - uint32_t target_fifo_id = 0; - uint8_t mps_over_flag = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - if (ep_idx == 0) { - if (!data_len) { - /* enable ep0 transfer */ - USB_CTRL_Endpoint_Data_Transfer_Done(); - return USB_DC_OK; - } - if (data_len > usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps) { - /* Check if transfer len is too big */ - data_len = usb_hs_device.in_ep[ep_idx].ep_cfg.ep_mps; - mps_over_flag = 1; - } - -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(0, data, data_len); -#else - ret = usb_dma_write(0, data, data_len); -#endif - if (ret < 0) { - return ret; - } - if (!mps_over_flag) { - USB_CTRL_Endpoint_Data_Transfer_Done(); - } - - } else { - if (!data_len) { - /* send zlp */ - USB_Endpoint_Transmit_Zero_Length_Packet(ep_idx); - while (1) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(ep_idx)) { - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(ep_idx); - break; - } - timeout--; - if (!timeout) { - USB_DC_LOG_ERR("ep%d wait free timeout\r\n", ep); - return -USB_DC_EP_TIMEOUT_ERR; - } - } - return USB_DC_OK; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_write(target_fifo_id, data, data_len); -#else - ret = usb_dma_write(target_fifo_id, data, data_len); -#endif - if (ret < 0) { - return ret; - } - } - - USB_DC_LOG_DBG("EP%d write %u bytes\r\n", ep_idx, data_len); - - if (ret_bytes) { - *ret_bytes = data_len; - } - - return USB_DC_OK; -} - -/** - * @brief Read data from the specified endpoint - * - * This function is called by the endpoint handler function, after an OUT - * interrupt has been received for that EP. The application must only call this - * function through the supplied usbd_ep_callback function. This function clears - * the ENDPOINT NAK when max_data_len is 0, if all data in the endpoint FIFO has been read, - * so as to accept more data from host. - * - * @param[in] ep Endpoint address corresponding to the one - * listed in the device configuration table - * @param[in] data Pointer to data buffer to write to - * @param[in] max_data_len Max length of data to read - * @param[out] read_bytes Number of bytes read. If data is NULL and - * max_data_len is 0 the number of bytes - * available for read should be returned. - * - * @return 0 on success, negative errno code on fail. - */ -int usbd_ep_read(const uint8_t ep, uint8_t *data, uint32_t data_len, uint32_t *read_bytes) -{ - uint32_t read_len = 0; - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - int ret = 0; - - /* Check if OUT ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - USB_DC_LOG_ERR("Wrong endpoint direction\r\n"); - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - USB_DC_LOG_ERR("Not enabled endpoint\r\n"); - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - /* Allow to read 0 bytes */ - if (!data_len) { - // if (ep_idx) { - // target_fifo_id = usb_get_transfer_fifo(ep_idx); - // uint32_t tmp = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); - // tmp &= ~(1 << (2 * (target_fifo_id - 1))); - // BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmp); - // } - return USB_DC_OK; - } - - if (ep_idx == 0) { - /*setup handler*/ - if ((data_len == 8) && !read_bytes) { - USB_Get_Setup_Command((uint32_t *)data); - return USB_DC_OK; - } else { - read_len = BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_FNT); -#if defined(CONFIG_USB_VDMA_ENABLE) - ret = usb_vdma_read(0, data, read_len); -#else - ret = usb_dma_read(0, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - } else { - target_fifo_id = usb_get_transfer_fifo(ep_idx); - read_len = USB_Get_OUT_FIFO_Count(target_fifo_id - 1); - if (read_len == 0) { - if (read_bytes) { - *read_bytes = 0; - } - return 0; - } -#ifdef CONFIG_USB_VDMA_ENABLE - ret = usb_vdma_read(target_fifo_id, data, read_len); -#else - ret = usb_dma_read(target_fifo_id, data, read_len); -#endif - if (ret < 0) { - return ret; - } - } - if (read_bytes) { - *read_bytes = read_len; - } - USB_DC_LOG_DBG("Read EP%d, req %d, read %d bytes\r\n", ep, data_len, *read_bytes); - - return USB_DC_OK; -} - -int usbd_ep_write_async(const uint8_t ep, const uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_IN) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_MEM_2_FIFO; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -int usbd_ep_read_async(const uint8_t ep, uint8_t *data, uint32_t data_len) -{ - uint32_t target_fifo_id = 0; - uint8_t ep_idx = USB_EP_GET_IDX(ep); - - /* Check if IN ep */ - if (USB_EP_GET_DIR(ep) != USB_EP_DIR_OUT) { - return -USB_DC_EP_DIR_ERR; - } - - /* Check if ep enabled */ - if (!usb_ep_is_enabled(ep)) { - return -USB_DC_EP_EN_ERR; - } - - if (!data && data_len) { - USB_DC_LOG_ERR("data is null\r\n"); - return -USB_DC_ADDR_ERR; - } - - target_fifo_id = usb_get_transfer_fifo(ep_idx); - - USB_VDMA_Cfg_Type vdma_fifo_cfg; - - vdma_fifo_cfg.dir = USB_VDMA_TRANS_DIR_FIFO_2_MEM; - vdma_fifo_cfg.memAddr = (uint32_t)(uintptr_t)data; - vdma_fifo_cfg.length = data_len; - - USB_Set_VDMA_Config(target_fifo_id, &vdma_fifo_cfg); - USB_Set_VDMA_Start(target_fifo_id); - - return 0; -} - -extern void usbd_event_notify_handler(uint8_t event, void *arg); - -static void usb_group0_isr(void) -{ - uint32_t group0intstatus = USB_Get_Sub_Group_0_IntStatus() & ~USB_Get_Sub_Group_0_IntMask(); - - if (group0intstatus & USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK) { - /* CX_COMABT_INT */ - USB_DC_LOG_ERR("CX COMABT\r\n"); - USB_Get_Sub_Group_0_IntClear(USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_COMFAIL_BIT_MUSK) { - /* CX_COMFAIL_INT */ - USB_DC_LOG_ERR("CX COMFAIL\r\n"); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_OUT_BIT_MUSK) { - /* CX_OUT_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_OUT_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_IN_BIT_MUSK) { - /* CX_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP0_IN_NOTIFY, NULL); - return; - } - if (group0intstatus & USB_SUB_GROUP_0_CX_SETUP_BIT_MUSK) { - /* CX_SETUP_INT */ - usbd_event_notify_handler(USB_DC_EVENT_SETUP_NOTIFY, NULL); - return; - } -} -static void usb_group1_isr(void) -{ - uint32_t group1intstatus = USB_Get_Sub_Group_1_IntStatus() & ~USB_Get_Sub_Group_1_IntMask(); - - if (group1intstatus & USB_SUB_GROUP_1_F0_OUT_BIT_MUSK) { - /* F0_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 0)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_OUT_BIT_MUSK) { - /* F1_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 2)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_OUT_BIT_MUSK) { - /* F2_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 4)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_OUT_BIT_MUSK) { - /* F3_OUT_INT */ - //BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET) | (1 << 6)); - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F0_IN_BIT_MUSK) { - /* F0_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F1_IN_BIT_MUSK) { - /* F1_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F2_IN_BIT_MUSK) { - /* F2_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } - - if (group1intstatus & USB_SUB_GROUP_1_F3_IN_BIT_MUSK) { - /* F3_IN_INT */ - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } -} -static void usb_group2_isr(void) -{ - uint32_t group2intstatus = USB_Get_Sub_Group_2_IntStatus() & ~USB_Get_Sub_Group_2_IntMask(); - - if (group2intstatus & USB_SUB_GROUP_2_WAKEUP_BY_VBUS_BIT_MUSK) { - /* Dev_Wakeup_byVBUS */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_IDLE_BIT_MUSK) { - /* Dev_Idle(HOV) */ - return; - } - if (group2intstatus & USB_SUB_GROUP_2_ERROR_BIT_MUSK) { - /* DMA_ERROR(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_ERROR_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_CMPLT_BIT_MUSK) { - /* DMA_CMPLT(HOV) */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_CMPLT_BIT_MUSK); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK) { - /* RX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Receive_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK) { - /* TX0BYTE_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK); - for (uint32_t i = USB_Endpoint_1; i <= USB_Endpoint_8; i++) { - if (USB_Is_Endpoint_Transfer_Zero_Length_Packet(i)) - USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(i); - } - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESUME_BIT_MUSK) { - /* RESM_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESUME_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_RESUME, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_SUSPEND_BIT_MUSK) { - /* SUSP_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_SUSPEND_BIT_MUSK); - usbd_event_notify_handler(USB_DC_EVENT_SUSPEND, NULL); - return; - } - if (group2intstatus & USB_SUB_GROUP_2_RESET_BIT_MUSK) { - /* USBRST_INT */ - USB_Get_Sub_Group_2_IntClear(USB_SUB_GROUP_2_RESET_BIT_MUSK); - USB_Non_Ctrl_Transfer_Disable(); - USB_Reset_FIFO(USB_FIFO_0); - USB_Reset_FIFO(USB_FIFO_1); - USB_Reset_FIFO(USB_FIFO_2); - USB_Reset_FIFO(USB_FIFO_3); - USB_Clear_CTRL_FIFO(); - -#ifdef CONFIG_USB_HS - USB_SOF_Mask_Time_HighSpeed(); -#else - USB_SOF_Mask_Time_FullSpeed(); -#endif - usbd_event_notify_handler(USB_DC_EVENT_RESET, NULL); - return; - } -} -#ifdef CONFIG_USB_VDMA_ENABLE -static void usb_group3_isr(void) -{ - uint32_t group3intstatus = USB_Get_Sub_Group_3_IntStatus() & ~USB_Get_Sub_Group_3_IntMask(); - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK) { - /* VDMA_CMPLT_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK) { - /* VDMA_CMPLT_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[0]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[0] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK) { - /* VDMA_CMPLT_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[1]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[1] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK) { - /* VDMA_CMPLT_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[2]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[2] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK) { - /* VDMA_CMPLT_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK); - if (usb_hs_device.in_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_IN_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] | 0x80)); - } else if (usb_hs_device.out_ep[fifo_ep_map[3]].ep_ena) { - usbd_event_notify_handler(USB_DC_EVENT_EP_OUT_NOTIFY, (void *)(uintptr_t)(fifo_ep_map[3] & 0x7f)); - } - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK) { - /* VDMA_ERROR_CXF */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK) { - /* VDMA_ERROR_F0 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK) { - /* VDMA_ERROR_F1 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK) { - /* VDMA_ERROR_F2 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK); - } - - if (group3intstatus & USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK) { - /* VDMA_ERROR_F3 */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK); - } -} -#endif -static void usb_group4_isr(void) -{ - uint32_t group4intstatus = USB_Get_Sub_Group_4_IntStatus() & ~USB_Get_Sub_Group_4_IntMask(); - - if (group4intstatus & USB_SUB_GROUP_4_L1_BIT_MUSK) { - /* L1_INT */ - USB_Get_Sub_Group_3_IntClear(USB_SUB_GROUP_4_L1_BIT_MUSK); - return; - } -} - -/** - * @brief - * - */ -void USBD_IRQHandler(void) -{ - if (USB_Global_IntStatus(USB_GLOBAL_INT_DEV)) { - /* group 0 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G0)) { - usb_group0_isr(); - } - /* group 1 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G1)) { - usb_group1_isr(); - } - /* group 2 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G2)) { - usb_group2_isr(); - } -#ifdef CONFIG_USB_VDMA_ENABLE - /* group 3 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G3)) { - usb_group3_isr(); - } -#endif - /* group 4 int */ - if (USB_Group_IntStatus(USB_GRP_INT_G4)) { - usb_group4_isr(); - } - } -} - -#ifdef USB_TEST_MODE -void usbd_set_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_set_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - case 2: //USB_FEATURE_TEST_MODE - switch (index >> 8) { - case 1: // Test_J - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_JSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 2: // Test_K - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_KSTA); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 3: // TEST_SE0_NAK - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_SE0NAK); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 4: // Test_Packet - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKT); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - } break; - case 5: // Test_Force_Enable - { - uint8_t temp[53]; - uint8_t *pp; - uint8_t i; - pp = temp; - - for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/ - *pp++ = 0x00; - - for (i = 0; i < 8; i++) /* 8*AA */ - *pp++ = 0xAA; - - for (i = 0; i < 8; i++) /* 8*EE */ - *pp++ = 0xEE; - - *pp++ = 0xFE; - - for (i = 0; i < 11; i++) /* 11*FF */ - *pp++ = 0xFF; - - *pp++ = 0x7F; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0xFC; - *pp++ = 0x7E; - *pp++ = 0xBF; - *pp++ = 0xDF; - *pp++ = 0xEF; - *pp++ = 0xF7; - *pp++ = 0xFB; - *pp++ = 0xFD; - *pp++ = 0x7E; - - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_PKDONE); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - } break; - - default: - break; - } - break; - case 3: //USB_FEATURE_BHNPENABLE - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_BUS_REQ); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_OTG_CSR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_B_HNP_EN); - BL_WR_REG(USB_BASE, USB_OTG_CSR, tmpVal); - } break; - case 4: //USB_FEATURE_AHNPSUPPORT - - break; - case 5: //USB_FEATURE_AALTHNPSUPPORT - - break; - - default: - break; - } -} - -void usbd_clear_feature(uint16_t index, uint16_t value) -{ - switch (value) { - case 0: //USB_FEATURE_ENDPOINT_HALT - //implement in usb_dc_ep_clear_stall - break; - case 1: //USB_FEATURE_REMOTE_WAKEUP - { - uint32_t tmpVal; - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - } break; - - default: - break; - } -} -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/audio_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/audio_reg.h deleted file mode 100644 index e51ca2aef3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/audio_reg.h +++ /dev/null @@ -1,6651 +0,0 @@ -/** - ****************************************************************************** - * @file audio_reg.h - * @version V1.0 - * @date 2021-07-19 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __AUDIO_REG_H__ -#define __AUDIO_REG_H__ - -#include "bl808.h" - -/* 0x0 : aud_top */ -#define AUDIO_AUD_TOP_OFFSET (0x0) -#define AUDIO_CKG_EN AUDIO_CKG_EN -#define AUDIO_CKG_EN_POS (0U) -#define AUDIO_CKG_EN_LEN (1U) -#define AUDIO_CKG_EN_MSK (((1U << AUDIO_CKG_EN_LEN) - 1) << AUDIO_CKG_EN_POS) -#define AUDIO_CKG_EN_UMSK (~(((1U << AUDIO_CKG_EN_LEN) - 1) << AUDIO_CKG_EN_POS)) -#define AUDIO_DAC_ITF_INV_SEL AUDIO_DAC_ITF_INV_SEL -#define AUDIO_DAC_ITF_INV_SEL_POS (1U) -#define AUDIO_DAC_ITF_INV_SEL_LEN (1U) -#define AUDIO_DAC_ITF_INV_SEL_MSK (((1U << AUDIO_DAC_ITF_INV_SEL_LEN) - 1) << AUDIO_DAC_ITF_INV_SEL_POS) -#define AUDIO_DAC_ITF_INV_SEL_UMSK (~(((1U << AUDIO_DAC_ITF_INV_SEL_LEN) - 1) << AUDIO_DAC_ITF_INV_SEL_POS)) -#define AUDIO_ADC_ITF_INV_SEL AUDIO_ADC_ITF_INV_SEL -#define AUDIO_ADC_ITF_INV_SEL_POS (2U) -#define AUDIO_ADC_ITF_INV_SEL_LEN (1U) -#define AUDIO_ADC_ITF_INV_SEL_MSK (((1U << AUDIO_ADC_ITF_INV_SEL_LEN) - 1) << AUDIO_ADC_ITF_INV_SEL_POS) -#define AUDIO_ADC_ITF_INV_SEL_UMSK (~(((1U << AUDIO_ADC_ITF_INV_SEL_LEN) - 1) << AUDIO_ADC_ITF_INV_SEL_POS)) -#define AUDIO_PDM_ITF_INV_SEL AUDIO_PDM_ITF_INV_SEL -#define AUDIO_PDM_ITF_INV_SEL_POS (3U) -#define AUDIO_PDM_ITF_INV_SEL_LEN (1U) -#define AUDIO_PDM_ITF_INV_SEL_MSK (((1U << AUDIO_PDM_ITF_INV_SEL_LEN) - 1) << AUDIO_PDM_ITF_INV_SEL_POS) -#define AUDIO_PDM_ITF_INV_SEL_UMSK (~(((1U << AUDIO_PDM_ITF_INV_SEL_LEN) - 1) << AUDIO_PDM_ITF_INV_SEL_POS)) -#define AUDIO_DAC_RATE AUDIO_DAC_RATE -#define AUDIO_DAC_RATE_POS (24U) -#define AUDIO_DAC_RATE_LEN (3U) -#define AUDIO_DAC_RATE_MSK (((1U << AUDIO_DAC_RATE_LEN) - 1) << AUDIO_DAC_RATE_POS) -#define AUDIO_DAC_RATE_UMSK (~(((1U << AUDIO_DAC_RATE_LEN) - 1) << AUDIO_DAC_RATE_POS)) -#define AUDIO_ADC_RATE AUDIO_ADC_RATE -#define AUDIO_ADC_RATE_POS (28U) -#define AUDIO_ADC_RATE_LEN (3U) -#define AUDIO_ADC_RATE_MSK (((1U << AUDIO_ADC_RATE_LEN) - 1) << AUDIO_ADC_RATE_POS) -#define AUDIO_ADC_RATE_UMSK (~(((1U << AUDIO_ADC_RATE_LEN) - 1) << AUDIO_ADC_RATE_POS)) - -/* 0x4 : aud_itf */ -#define AUDIO_AUD_ITF_OFFSET (0x4) -#define AUDIO_ADC_0_EN AUDIO_ADC_0_EN -#define AUDIO_ADC_0_EN_POS (0U) -#define AUDIO_ADC_0_EN_LEN (1U) -#define AUDIO_ADC_0_EN_MSK (((1U << AUDIO_ADC_0_EN_LEN) - 1) << AUDIO_ADC_0_EN_POS) -#define AUDIO_ADC_0_EN_UMSK (~(((1U << AUDIO_ADC_0_EN_LEN) - 1) << AUDIO_ADC_0_EN_POS)) -#define AUDIO_ADC_1_EN AUDIO_ADC_1_EN -#define AUDIO_ADC_1_EN_POS (1U) -#define AUDIO_ADC_1_EN_LEN (1U) -#define AUDIO_ADC_1_EN_MSK (((1U << AUDIO_ADC_1_EN_LEN) - 1) << AUDIO_ADC_1_EN_POS) -#define AUDIO_ADC_1_EN_UMSK (~(((1U << AUDIO_ADC_1_EN_LEN) - 1) << AUDIO_ADC_1_EN_POS)) -#define AUDIO_ADC_2_EN AUDIO_ADC_2_EN -#define AUDIO_ADC_2_EN_POS (2U) -#define AUDIO_ADC_2_EN_LEN (1U) -#define AUDIO_ADC_2_EN_MSK (((1U << AUDIO_ADC_2_EN_LEN) - 1) << AUDIO_ADC_2_EN_POS) -#define AUDIO_ADC_2_EN_UMSK (~(((1U << AUDIO_ADC_2_EN_LEN) - 1) << AUDIO_ADC_2_EN_POS)) -#define AUDIO_DAC_0_EN AUDIO_DAC_0_EN -#define AUDIO_DAC_0_EN_POS (3U) -#define AUDIO_DAC_0_EN_LEN (1U) -#define AUDIO_DAC_0_EN_MSK (((1U << AUDIO_DAC_0_EN_LEN) - 1) << AUDIO_DAC_0_EN_POS) -#define AUDIO_DAC_0_EN_UMSK (~(((1U << AUDIO_DAC_0_EN_LEN) - 1) << AUDIO_DAC_0_EN_POS)) -#define AUDIO_DAC_1_EN AUDIO_DAC_1_EN -#define AUDIO_DAC_1_EN_POS (4U) -#define AUDIO_DAC_1_EN_LEN (1U) -#define AUDIO_DAC_1_EN_MSK (((1U << AUDIO_DAC_1_EN_LEN) - 1) << AUDIO_DAC_1_EN_POS) -#define AUDIO_DAC_1_EN_UMSK (~(((1U << AUDIO_DAC_1_EN_LEN) - 1) << AUDIO_DAC_1_EN_POS)) -#define AUDIO_AEC_0_EN AUDIO_AEC_0_EN -#define AUDIO_AEC_0_EN_POS (5U) -#define AUDIO_AEC_0_EN_LEN (1U) -#define AUDIO_AEC_0_EN_MSK (((1U << AUDIO_AEC_0_EN_LEN) - 1) << AUDIO_AEC_0_EN_POS) -#define AUDIO_AEC_0_EN_UMSK (~(((1U << AUDIO_AEC_0_EN_LEN) - 1) << AUDIO_AEC_0_EN_POS)) -#define AUDIO_AEC_1_EN AUDIO_AEC_1_EN -#define AUDIO_AEC_1_EN_POS (6U) -#define AUDIO_AEC_1_EN_LEN (1U) -#define AUDIO_AEC_1_EN_MSK (((1U << AUDIO_AEC_1_EN_LEN) - 1) << AUDIO_AEC_1_EN_POS) -#define AUDIO_AEC_1_EN_UMSK (~(((1U << AUDIO_AEC_1_EN_LEN) - 1) << AUDIO_AEC_1_EN_POS)) -#define AUDIO_AUD_RX0_SEL AUDIO_AUD_RX0_SEL -#define AUDIO_AUD_RX0_SEL_POS (13U) -#define AUDIO_AUD_RX0_SEL_LEN (3U) -#define AUDIO_AUD_RX0_SEL_MSK (((1U << AUDIO_AUD_RX0_SEL_LEN) - 1) << AUDIO_AUD_RX0_SEL_POS) -#define AUDIO_AUD_RX0_SEL_UMSK (~(((1U << AUDIO_AUD_RX0_SEL_LEN) - 1) << AUDIO_AUD_RX0_SEL_POS)) -#define AUDIO_AUD_RX1_SEL AUDIO_AUD_RX1_SEL -#define AUDIO_AUD_RX1_SEL_POS (16U) -#define AUDIO_AUD_RX1_SEL_LEN (3U) -#define AUDIO_AUD_RX1_SEL_MSK (((1U << AUDIO_AUD_RX1_SEL_LEN) - 1) << AUDIO_AUD_RX1_SEL_POS) -#define AUDIO_AUD_RX1_SEL_UMSK (~(((1U << AUDIO_AUD_RX1_SEL_LEN) - 1) << AUDIO_AUD_RX1_SEL_POS)) -#define AUDIO_AUD_RX2_SEL AUDIO_AUD_RX2_SEL -#define AUDIO_AUD_RX2_SEL_POS (19U) -#define AUDIO_AUD_RX2_SEL_LEN (3U) -#define AUDIO_AUD_RX2_SEL_MSK (((1U << AUDIO_AUD_RX2_SEL_LEN) - 1) << AUDIO_AUD_RX2_SEL_POS) -#define AUDIO_AUD_RX2_SEL_UMSK (~(((1U << AUDIO_AUD_RX2_SEL_LEN) - 1) << AUDIO_AUD_RX2_SEL_POS)) -#define AUDIO_AUD_RX3_SEL AUDIO_AUD_RX3_SEL -#define AUDIO_AUD_RX3_SEL_POS (22U) -#define AUDIO_AUD_RX3_SEL_LEN (3U) -#define AUDIO_AUD_RX3_SEL_MSK (((1U << AUDIO_AUD_RX3_SEL_LEN) - 1) << AUDIO_AUD_RX3_SEL_POS) -#define AUDIO_AUD_RX3_SEL_UMSK (~(((1U << AUDIO_AUD_RX3_SEL_LEN) - 1) << AUDIO_AUD_RX3_SEL_POS)) -#define AUDIO_AUD_RX4_SEL AUDIO_AUD_RX4_SEL -#define AUDIO_AUD_RX4_SEL_POS (25U) -#define AUDIO_AUD_RX4_SEL_LEN (3U) -#define AUDIO_AUD_RX4_SEL_MSK (((1U << AUDIO_AUD_RX4_SEL_LEN) - 1) << AUDIO_AUD_RX4_SEL_POS) -#define AUDIO_AUD_RX4_SEL_UMSK (~(((1U << AUDIO_AUD_RX4_SEL_LEN) - 1) << AUDIO_AUD_RX4_SEL_POS)) -#define AUDIO_AUD_TX0_SEL AUDIO_AUD_TX0_SEL -#define AUDIO_AUD_TX0_SEL_POS (28U) -#define AUDIO_AUD_TX0_SEL_LEN (1U) -#define AUDIO_AUD_TX0_SEL_MSK (((1U << AUDIO_AUD_TX0_SEL_LEN) - 1) << AUDIO_AUD_TX0_SEL_POS) -#define AUDIO_AUD_TX0_SEL_UMSK (~(((1U << AUDIO_AUD_TX0_SEL_LEN) - 1) << AUDIO_AUD_TX0_SEL_POS)) -#define AUDIO_AUD_TX1_SEL AUDIO_AUD_TX1_SEL -#define AUDIO_AUD_TX1_SEL_POS (29U) -#define AUDIO_AUD_TX1_SEL_LEN (1U) -#define AUDIO_AUD_TX1_SEL_MSK (((1U << AUDIO_AUD_TX1_SEL_LEN) - 1) << AUDIO_AUD_TX1_SEL_POS) -#define AUDIO_AUD_TX1_SEL_UMSK (~(((1U << AUDIO_AUD_TX1_SEL_LEN) - 1) << AUDIO_AUD_TX1_SEL_POS)) -#define AUDIO_ADC_ITF_EN AUDIO_ADC_ITF_EN -#define AUDIO_ADC_ITF_EN_POS (30U) -#define AUDIO_ADC_ITF_EN_LEN (1U) -#define AUDIO_ADC_ITF_EN_MSK (((1U << AUDIO_ADC_ITF_EN_LEN) - 1) << AUDIO_ADC_ITF_EN_POS) -#define AUDIO_ADC_ITF_EN_UMSK (~(((1U << AUDIO_ADC_ITF_EN_LEN) - 1) << AUDIO_ADC_ITF_EN_POS)) -#define AUDIO_DAC_ITF_EN AUDIO_DAC_ITF_EN -#define AUDIO_DAC_ITF_EN_POS (31U) -#define AUDIO_DAC_ITF_EN_LEN (1U) -#define AUDIO_DAC_ITF_EN_MSK (((1U << AUDIO_DAC_ITF_EN_LEN) - 1) << AUDIO_DAC_ITF_EN_POS) -#define AUDIO_DAC_ITF_EN_UMSK (~(((1U << AUDIO_DAC_ITF_EN_LEN) - 1) << AUDIO_DAC_ITF_EN_POS)) - -/* 0x8 : adc_0 */ -#define AUDIO_ADC_0_OFFSET (0x8) -#define AUDIO_ADC_0_FIR_MODE AUDIO_ADC_0_FIR_MODE -#define AUDIO_ADC_0_FIR_MODE_POS (0U) -#define AUDIO_ADC_0_FIR_MODE_LEN (1U) -#define AUDIO_ADC_0_FIR_MODE_MSK (((1U << AUDIO_ADC_0_FIR_MODE_LEN) - 1) << AUDIO_ADC_0_FIR_MODE_POS) -#define AUDIO_ADC_0_FIR_MODE_UMSK (~(((1U << AUDIO_ADC_0_FIR_MODE_LEN) - 1) << AUDIO_ADC_0_FIR_MODE_POS)) -#define AUDIO_ADC_1_FIR_MODE AUDIO_ADC_1_FIR_MODE -#define AUDIO_ADC_1_FIR_MODE_POS (1U) -#define AUDIO_ADC_1_FIR_MODE_LEN (1U) -#define AUDIO_ADC_1_FIR_MODE_MSK (((1U << AUDIO_ADC_1_FIR_MODE_LEN) - 1) << AUDIO_ADC_1_FIR_MODE_POS) -#define AUDIO_ADC_1_FIR_MODE_UMSK (~(((1U << AUDIO_ADC_1_FIR_MODE_LEN) - 1) << AUDIO_ADC_1_FIR_MODE_POS)) -#define AUDIO_ADC_2_FIR_MODE AUDIO_ADC_2_FIR_MODE -#define AUDIO_ADC_2_FIR_MODE_POS (2U) -#define AUDIO_ADC_2_FIR_MODE_LEN (1U) -#define AUDIO_ADC_2_FIR_MODE_MSK (((1U << AUDIO_ADC_2_FIR_MODE_LEN) - 1) << AUDIO_ADC_2_FIR_MODE_POS) -#define AUDIO_ADC_2_FIR_MODE_UMSK (~(((1U << AUDIO_ADC_2_FIR_MODE_LEN) - 1) << AUDIO_ADC_2_FIR_MODE_POS)) -#define AUDIO_ADC_0_SCAL AUDIO_ADC_0_SCAL -#define AUDIO_ADC_0_SCAL_POS (3U) -#define AUDIO_ADC_0_SCAL_LEN (6U) -#define AUDIO_ADC_0_SCAL_MSK (((1U << AUDIO_ADC_0_SCAL_LEN) - 1) << AUDIO_ADC_0_SCAL_POS) -#define AUDIO_ADC_0_SCAL_UMSK (~(((1U << AUDIO_ADC_0_SCAL_LEN) - 1) << AUDIO_ADC_0_SCAL_POS)) -#define AUDIO_ADC_1_SCAL AUDIO_ADC_1_SCAL -#define AUDIO_ADC_1_SCAL_POS (9U) -#define AUDIO_ADC_1_SCAL_LEN (6U) -#define AUDIO_ADC_1_SCAL_MSK (((1U << AUDIO_ADC_1_SCAL_LEN) - 1) << AUDIO_ADC_1_SCAL_POS) -#define AUDIO_ADC_1_SCAL_UMSK (~(((1U << AUDIO_ADC_1_SCAL_LEN) - 1) << AUDIO_ADC_1_SCAL_POS)) -#define AUDIO_ADC_2_SCAL AUDIO_ADC_2_SCAL -#define AUDIO_ADC_2_SCAL_POS (15U) -#define AUDIO_ADC_2_SCAL_LEN (6U) -#define AUDIO_ADC_2_SCAL_MSK (((1U << AUDIO_ADC_2_SCAL_LEN) - 1) << AUDIO_ADC_2_SCAL_POS) -#define AUDIO_ADC_2_SCAL_UMSK (~(((1U << AUDIO_ADC_2_SCAL_LEN) - 1) << AUDIO_ADC_2_SCAL_POS)) -#define AUDIO_ADC_DITHER_DATA AUDIO_ADC_DITHER_DATA -#define AUDIO_ADC_DITHER_DATA_POS (29U) -#define AUDIO_ADC_DITHER_DATA_LEN (1U) -#define AUDIO_ADC_DITHER_DATA_MSK (((1U << AUDIO_ADC_DITHER_DATA_LEN) - 1) << AUDIO_ADC_DITHER_DATA_POS) -#define AUDIO_ADC_DITHER_DATA_UMSK (~(((1U << AUDIO_ADC_DITHER_DATA_LEN) - 1) << AUDIO_ADC_DITHER_DATA_POS)) -#define AUDIO_ADC_LFSR_MODE AUDIO_ADC_LFSR_MODE -#define AUDIO_ADC_LFSR_MODE_POS (30U) -#define AUDIO_ADC_LFSR_MODE_LEN (2U) -#define AUDIO_ADC_LFSR_MODE_MSK (((1U << AUDIO_ADC_LFSR_MODE_LEN) - 1) << AUDIO_ADC_LFSR_MODE_POS) -#define AUDIO_ADC_LFSR_MODE_UMSK (~(((1U << AUDIO_ADC_LFSR_MODE_LEN) - 1) << AUDIO_ADC_LFSR_MODE_POS)) - -/* 0xC : adc_1 */ -#define AUDIO_ADC_1_OFFSET (0xC) -#define AUDIO_ADC_0_K1 AUDIO_ADC_0_K1 -#define AUDIO_ADC_0_K1_POS (0U) -#define AUDIO_ADC_0_K1_LEN (4U) -#define AUDIO_ADC_0_K1_MSK (((1U << AUDIO_ADC_0_K1_LEN) - 1) << AUDIO_ADC_0_K1_POS) -#define AUDIO_ADC_0_K1_UMSK (~(((1U << AUDIO_ADC_0_K1_LEN) - 1) << AUDIO_ADC_0_K1_POS)) -#define AUDIO_ADC_0_K1_EN AUDIO_ADC_0_K1_EN -#define AUDIO_ADC_0_K1_EN_POS (4U) -#define AUDIO_ADC_0_K1_EN_LEN (1U) -#define AUDIO_ADC_0_K1_EN_MSK (((1U << AUDIO_ADC_0_K1_EN_LEN) - 1) << AUDIO_ADC_0_K1_EN_POS) -#define AUDIO_ADC_0_K1_EN_UMSK (~(((1U << AUDIO_ADC_0_K1_EN_LEN) - 1) << AUDIO_ADC_0_K1_EN_POS)) -#define AUDIO_ADC_0_K2 AUDIO_ADC_0_K2 -#define AUDIO_ADC_0_K2_POS (5U) -#define AUDIO_ADC_0_K2_LEN (4U) -#define AUDIO_ADC_0_K2_MSK (((1U << AUDIO_ADC_0_K2_LEN) - 1) << AUDIO_ADC_0_K2_POS) -#define AUDIO_ADC_0_K2_UMSK (~(((1U << AUDIO_ADC_0_K2_LEN) - 1) << AUDIO_ADC_0_K2_POS)) -#define AUDIO_ADC_0_K2_EN AUDIO_ADC_0_K2_EN -#define AUDIO_ADC_0_K2_EN_POS (9U) -#define AUDIO_ADC_0_K2_EN_LEN (1U) -#define AUDIO_ADC_0_K2_EN_MSK (((1U << AUDIO_ADC_0_K2_EN_LEN) - 1) << AUDIO_ADC_0_K2_EN_POS) -#define AUDIO_ADC_0_K2_EN_UMSK (~(((1U << AUDIO_ADC_0_K2_EN_LEN) - 1) << AUDIO_ADC_0_K2_EN_POS)) -#define AUDIO_ADC_1_K1 AUDIO_ADC_1_K1 -#define AUDIO_ADC_1_K1_POS (10U) -#define AUDIO_ADC_1_K1_LEN (4U) -#define AUDIO_ADC_1_K1_MSK (((1U << AUDIO_ADC_1_K1_LEN) - 1) << AUDIO_ADC_1_K1_POS) -#define AUDIO_ADC_1_K1_UMSK (~(((1U << AUDIO_ADC_1_K1_LEN) - 1) << AUDIO_ADC_1_K1_POS)) -#define AUDIO_ADC_1_K1_EN AUDIO_ADC_1_K1_EN -#define AUDIO_ADC_1_K1_EN_POS (14U) -#define AUDIO_ADC_1_K1_EN_LEN (1U) -#define AUDIO_ADC_1_K1_EN_MSK (((1U << AUDIO_ADC_1_K1_EN_LEN) - 1) << AUDIO_ADC_1_K1_EN_POS) -#define AUDIO_ADC_1_K1_EN_UMSK (~(((1U << AUDIO_ADC_1_K1_EN_LEN) - 1) << AUDIO_ADC_1_K1_EN_POS)) -#define AUDIO_ADC_1_K2 AUDIO_ADC_1_K2 -#define AUDIO_ADC_1_K2_POS (15U) -#define AUDIO_ADC_1_K2_LEN (4U) -#define AUDIO_ADC_1_K2_MSK (((1U << AUDIO_ADC_1_K2_LEN) - 1) << AUDIO_ADC_1_K2_POS) -#define AUDIO_ADC_1_K2_UMSK (~(((1U << AUDIO_ADC_1_K2_LEN) - 1) << AUDIO_ADC_1_K2_POS)) -#define AUDIO_ADC_1_K2_EN AUDIO_ADC_1_K2_EN -#define AUDIO_ADC_1_K2_EN_POS (19U) -#define AUDIO_ADC_1_K2_EN_LEN (1U) -#define AUDIO_ADC_1_K2_EN_MSK (((1U << AUDIO_ADC_1_K2_EN_LEN) - 1) << AUDIO_ADC_1_K2_EN_POS) -#define AUDIO_ADC_1_K2_EN_UMSK (~(((1U << AUDIO_ADC_1_K2_EN_LEN) - 1) << AUDIO_ADC_1_K2_EN_POS)) -#define AUDIO_ADC_2_K1 AUDIO_ADC_2_K1 -#define AUDIO_ADC_2_K1_POS (20U) -#define AUDIO_ADC_2_K1_LEN (4U) -#define AUDIO_ADC_2_K1_MSK (((1U << AUDIO_ADC_2_K1_LEN) - 1) << AUDIO_ADC_2_K1_POS) -#define AUDIO_ADC_2_K1_UMSK (~(((1U << AUDIO_ADC_2_K1_LEN) - 1) << AUDIO_ADC_2_K1_POS)) -#define AUDIO_ADC_2_K1_EN AUDIO_ADC_2_K1_EN -#define AUDIO_ADC_2_K1_EN_POS (24U) -#define AUDIO_ADC_2_K1_EN_LEN (1U) -#define AUDIO_ADC_2_K1_EN_MSK (((1U << AUDIO_ADC_2_K1_EN_LEN) - 1) << AUDIO_ADC_2_K1_EN_POS) -#define AUDIO_ADC_2_K1_EN_UMSK (~(((1U << AUDIO_ADC_2_K1_EN_LEN) - 1) << AUDIO_ADC_2_K1_EN_POS)) -#define AUDIO_ADC_2_K2 AUDIO_ADC_2_K2 -#define AUDIO_ADC_2_K2_POS (25U) -#define AUDIO_ADC_2_K2_LEN (4U) -#define AUDIO_ADC_2_K2_MSK (((1U << AUDIO_ADC_2_K2_LEN) - 1) << AUDIO_ADC_2_K2_POS) -#define AUDIO_ADC_2_K2_UMSK (~(((1U << AUDIO_ADC_2_K2_LEN) - 1) << AUDIO_ADC_2_K2_POS)) -#define AUDIO_ADC_2_K2_EN AUDIO_ADC_2_K2_EN -#define AUDIO_ADC_2_K2_EN_POS (29U) -#define AUDIO_ADC_2_K2_EN_LEN (1U) -#define AUDIO_ADC_2_K2_EN_MSK (((1U << AUDIO_ADC_2_K2_EN_LEN) - 1) << AUDIO_ADC_2_K2_EN_POS) -#define AUDIO_ADC_2_K2_EN_UMSK (~(((1U << AUDIO_ADC_2_K2_EN_LEN) - 1) << AUDIO_ADC_2_K2_EN_POS)) - -/* 0x10 : dac_0 */ -#define AUDIO_DAC_0_OFFSET (0x10) -#define AUDIO_ADC_PDM_H AUDIO_ADC_PDM_H -#define AUDIO_ADC_PDM_H_POS (0U) -#define AUDIO_ADC_PDM_H_LEN (6U) -#define AUDIO_ADC_PDM_H_MSK (((1U << AUDIO_ADC_PDM_H_LEN) - 1) << AUDIO_ADC_PDM_H_POS) -#define AUDIO_ADC_PDM_H_UMSK (~(((1U << AUDIO_ADC_PDM_H_LEN) - 1) << AUDIO_ADC_PDM_H_POS)) -#define AUDIO_ADC_PDM_L AUDIO_ADC_PDM_L -#define AUDIO_ADC_PDM_L_POS (6U) -#define AUDIO_ADC_PDM_L_LEN (6U) -#define AUDIO_ADC_PDM_L_MSK (((1U << AUDIO_ADC_PDM_L_LEN) - 1) << AUDIO_ADC_PDM_L_POS) -#define AUDIO_ADC_PDM_L_UMSK (~(((1U << AUDIO_ADC_PDM_L_LEN) - 1) << AUDIO_ADC_PDM_L_POS)) -#define AUDIO_ADC_0_SRC AUDIO_ADC_0_SRC -#define AUDIO_ADC_0_SRC_POS (12U) -#define AUDIO_ADC_0_SRC_LEN (1U) -#define AUDIO_ADC_0_SRC_MSK (((1U << AUDIO_ADC_0_SRC_LEN) - 1) << AUDIO_ADC_0_SRC_POS) -#define AUDIO_ADC_0_SRC_UMSK (~(((1U << AUDIO_ADC_0_SRC_LEN) - 1) << AUDIO_ADC_0_SRC_POS)) -#define AUDIO_ADC_0_PDM_LVL_SWAP AUDIO_ADC_0_PDM_LVL_SWAP -#define AUDIO_ADC_0_PDM_LVL_SWAP_POS (13U) -#define AUDIO_ADC_0_PDM_LVL_SWAP_LEN (1U) -#define AUDIO_ADC_0_PDM_LVL_SWAP_MSK (((1U << AUDIO_ADC_0_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_0_PDM_LVL_SWAP_POS) -#define AUDIO_ADC_0_PDM_LVL_SWAP_UMSK (~(((1U << AUDIO_ADC_0_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_0_PDM_LVL_SWAP_POS)) -#define AUDIO_ADC_0_MASH_BIT_SWAP AUDIO_ADC_0_MASH_BIT_SWAP -#define AUDIO_ADC_0_MASH_BIT_SWAP_POS (14U) -#define AUDIO_ADC_0_MASH_BIT_SWAP_LEN (1U) -#define AUDIO_ADC_0_MASH_BIT_SWAP_MSK (((1U << AUDIO_ADC_0_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_0_MASH_BIT_SWAP_POS) -#define AUDIO_ADC_0_MASH_BIT_SWAP_UMSK (~(((1U << AUDIO_ADC_0_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_0_MASH_BIT_SWAP_POS)) -#define AUDIO_ADC_1_SRC AUDIO_ADC_1_SRC -#define AUDIO_ADC_1_SRC_POS (15U) -#define AUDIO_ADC_1_SRC_LEN (1U) -#define AUDIO_ADC_1_SRC_MSK (((1U << AUDIO_ADC_1_SRC_LEN) - 1) << AUDIO_ADC_1_SRC_POS) -#define AUDIO_ADC_1_SRC_UMSK (~(((1U << AUDIO_ADC_1_SRC_LEN) - 1) << AUDIO_ADC_1_SRC_POS)) -#define AUDIO_ADC_1_PDM_LVL_SWAP AUDIO_ADC_1_PDM_LVL_SWAP -#define AUDIO_ADC_1_PDM_LVL_SWAP_POS (16U) -#define AUDIO_ADC_1_PDM_LVL_SWAP_LEN (1U) -#define AUDIO_ADC_1_PDM_LVL_SWAP_MSK (((1U << AUDIO_ADC_1_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_1_PDM_LVL_SWAP_POS) -#define AUDIO_ADC_1_PDM_LVL_SWAP_UMSK (~(((1U << AUDIO_ADC_1_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_1_PDM_LVL_SWAP_POS)) -#define AUDIO_ADC_1_MASH_BIT_SWAP AUDIO_ADC_1_MASH_BIT_SWAP -#define AUDIO_ADC_1_MASH_BIT_SWAP_POS (17U) -#define AUDIO_ADC_1_MASH_BIT_SWAP_LEN (1U) -#define AUDIO_ADC_1_MASH_BIT_SWAP_MSK (((1U << AUDIO_ADC_1_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_1_MASH_BIT_SWAP_POS) -#define AUDIO_ADC_1_MASH_BIT_SWAP_UMSK (~(((1U << AUDIO_ADC_1_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_1_MASH_BIT_SWAP_POS)) -#define AUDIO_ADC_2_SRC AUDIO_ADC_2_SRC -#define AUDIO_ADC_2_SRC_POS (18U) -#define AUDIO_ADC_2_SRC_LEN (1U) -#define AUDIO_ADC_2_SRC_MSK (((1U << AUDIO_ADC_2_SRC_LEN) - 1) << AUDIO_ADC_2_SRC_POS) -#define AUDIO_ADC_2_SRC_UMSK (~(((1U << AUDIO_ADC_2_SRC_LEN) - 1) << AUDIO_ADC_2_SRC_POS)) -#define AUDIO_ADC_2_PDM_LVL_SWAP AUDIO_ADC_2_PDM_LVL_SWAP -#define AUDIO_ADC_2_PDM_LVL_SWAP_POS (19U) -#define AUDIO_ADC_2_PDM_LVL_SWAP_LEN (1U) -#define AUDIO_ADC_2_PDM_LVL_SWAP_MSK (((1U << AUDIO_ADC_2_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_2_PDM_LVL_SWAP_POS) -#define AUDIO_ADC_2_PDM_LVL_SWAP_UMSK (~(((1U << AUDIO_ADC_2_PDM_LVL_SWAP_LEN) - 1) << AUDIO_ADC_2_PDM_LVL_SWAP_POS)) -#define AUDIO_ADC_2_MASH_BIT_SWAP AUDIO_ADC_2_MASH_BIT_SWAP -#define AUDIO_ADC_2_MASH_BIT_SWAP_POS (20U) -#define AUDIO_ADC_2_MASH_BIT_SWAP_LEN (1U) -#define AUDIO_ADC_2_MASH_BIT_SWAP_MSK (((1U << AUDIO_ADC_2_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_2_MASH_BIT_SWAP_POS) -#define AUDIO_ADC_2_MASH_BIT_SWAP_UMSK (~(((1U << AUDIO_ADC_2_MASH_BIT_SWAP_LEN) - 1) << AUDIO_ADC_2_MASH_BIT_SWAP_POS)) -#define AUDIO_MIX_0_SEL AUDIO_MIX_0_SEL -#define AUDIO_MIX_0_SEL_POS (21U) -#define AUDIO_MIX_0_SEL_LEN (2U) -#define AUDIO_MIX_0_SEL_MSK (((1U << AUDIO_MIX_0_SEL_LEN) - 1) << AUDIO_MIX_0_SEL_POS) -#define AUDIO_MIX_0_SEL_UMSK (~(((1U << AUDIO_MIX_0_SEL_LEN) - 1) << AUDIO_MIX_0_SEL_POS)) -#define AUDIO_MIX_0_MODE AUDIO_MIX_0_MODE -#define AUDIO_MIX_0_MODE_POS (23U) -#define AUDIO_MIX_0_MODE_LEN (2U) -#define AUDIO_MIX_0_MODE_MSK (((1U << AUDIO_MIX_0_MODE_LEN) - 1) << AUDIO_MIX_0_MODE_POS) -#define AUDIO_MIX_0_MODE_UMSK (~(((1U << AUDIO_MIX_0_MODE_LEN) - 1) << AUDIO_MIX_0_MODE_POS)) -#define AUDIO_MIX_0_ATT_MODE1 AUDIO_MIX_0_ATT_MODE1 -#define AUDIO_MIX_0_ATT_MODE1_POS (25U) -#define AUDIO_MIX_0_ATT_MODE1_LEN (3U) -#define AUDIO_MIX_0_ATT_MODE1_MSK (((1U << AUDIO_MIX_0_ATT_MODE1_LEN) - 1) << AUDIO_MIX_0_ATT_MODE1_POS) -#define AUDIO_MIX_0_ATT_MODE1_UMSK (~(((1U << AUDIO_MIX_0_ATT_MODE1_LEN) - 1) << AUDIO_MIX_0_ATT_MODE1_POS)) -#define AUDIO_MIX_0_ATT_MODE2 AUDIO_MIX_0_ATT_MODE2 -#define AUDIO_MIX_0_ATT_MODE2_POS (28U) -#define AUDIO_MIX_0_ATT_MODE2_LEN (3U) -#define AUDIO_MIX_0_ATT_MODE2_MSK (((1U << AUDIO_MIX_0_ATT_MODE2_LEN) - 1) << AUDIO_MIX_0_ATT_MODE2_POS) -#define AUDIO_MIX_0_ATT_MODE2_UMSK (~(((1U << AUDIO_MIX_0_ATT_MODE2_LEN) - 1) << AUDIO_MIX_0_ATT_MODE2_POS)) - -/* 0x14 : dac_1 */ -#define AUDIO_DAC_1_OFFSET (0x14) -#define AUDIO_DAC_DEM_BYPASS AUDIO_DAC_DEM_BYPASS -#define AUDIO_DAC_DEM_BYPASS_POS (0U) -#define AUDIO_DAC_DEM_BYPASS_LEN (1U) -#define AUDIO_DAC_DEM_BYPASS_MSK (((1U << AUDIO_DAC_DEM_BYPASS_LEN) - 1) << AUDIO_DAC_DEM_BYPASS_POS) -#define AUDIO_DAC_DEM_BYPASS_UMSK (~(((1U << AUDIO_DAC_DEM_BYPASS_LEN) - 1) << AUDIO_DAC_DEM_BYPASS_POS)) -#define AUDIO_DAC_DEM_OUT_SWAP AUDIO_DAC_DEM_OUT_SWAP -#define AUDIO_DAC_DEM_OUT_SWAP_POS (1U) -#define AUDIO_DAC_DEM_OUT_SWAP_LEN (1U) -#define AUDIO_DAC_DEM_OUT_SWAP_MSK (((1U << AUDIO_DAC_DEM_OUT_SWAP_LEN) - 1) << AUDIO_DAC_DEM_OUT_SWAP_POS) -#define AUDIO_DAC_DEM_OUT_SWAP_UMSK (~(((1U << AUDIO_DAC_DEM_OUT_SWAP_LEN) - 1) << AUDIO_DAC_DEM_OUT_SWAP_POS)) -#define AUDIO_DAC_DSM_ORDER AUDIO_DAC_DSM_ORDER -#define AUDIO_DAC_DSM_ORDER_POS (5U) -#define AUDIO_DAC_DSM_ORDER_LEN (1U) -#define AUDIO_DAC_DSM_ORDER_MSK (((1U << AUDIO_DAC_DSM_ORDER_LEN) - 1) << AUDIO_DAC_DSM_ORDER_POS) -#define AUDIO_DAC_DSM_ORDER_UMSK (~(((1U << AUDIO_DAC_DSM_ORDER_LEN) - 1) << AUDIO_DAC_DSM_ORDER_POS)) -#define AUDIO_DAC_DSM_SCALING_FACTOR AUDIO_DAC_DSM_SCALING_FACTOR -#define AUDIO_DAC_DSM_SCALING_FACTOR_POS (6U) -#define AUDIO_DAC_DSM_SCALING_FACTOR_LEN (4U) -#define AUDIO_DAC_DSM_SCALING_FACTOR_MSK (((1U << AUDIO_DAC_DSM_SCALING_FACTOR_LEN) - 1) << AUDIO_DAC_DSM_SCALING_FACTOR_POS) -#define AUDIO_DAC_DSM_SCALING_FACTOR_UMSK (~(((1U << AUDIO_DAC_DSM_SCALING_FACTOR_LEN) - 1) << AUDIO_DAC_DSM_SCALING_FACTOR_POS)) -#define AUDIO_DAC_DSM_SCALING_EN AUDIO_DAC_DSM_SCALING_EN -#define AUDIO_DAC_DSM_SCALING_EN_POS (10U) -#define AUDIO_DAC_DSM_SCALING_EN_LEN (1U) -#define AUDIO_DAC_DSM_SCALING_EN_MSK (((1U << AUDIO_DAC_DSM_SCALING_EN_LEN) - 1) << AUDIO_DAC_DSM_SCALING_EN_POS) -#define AUDIO_DAC_DSM_SCALING_EN_UMSK (~(((1U << AUDIO_DAC_DSM_SCALING_EN_LEN) - 1) << AUDIO_DAC_DSM_SCALING_EN_POS)) -#define AUDIO_DAC_DSM_DITHER_AMP AUDIO_DAC_DSM_DITHER_AMP -#define AUDIO_DAC_DSM_DITHER_AMP_POS (11U) -#define AUDIO_DAC_DSM_DITHER_AMP_LEN (3U) -#define AUDIO_DAC_DSM_DITHER_AMP_MSK (((1U << AUDIO_DAC_DSM_DITHER_AMP_LEN) - 1) << AUDIO_DAC_DSM_DITHER_AMP_POS) -#define AUDIO_DAC_DSM_DITHER_AMP_UMSK (~(((1U << AUDIO_DAC_DSM_DITHER_AMP_LEN) - 1) << AUDIO_DAC_DSM_DITHER_AMP_POS)) -#define AUDIO_DAC_DSM_DITHER_EN AUDIO_DAC_DSM_DITHER_EN -#define AUDIO_DAC_DSM_DITHER_EN_POS (14U) -#define AUDIO_DAC_DSM_DITHER_EN_LEN (1U) -#define AUDIO_DAC_DSM_DITHER_EN_MSK (((1U << AUDIO_DAC_DSM_DITHER_EN_LEN) - 1) << AUDIO_DAC_DSM_DITHER_EN_POS) -#define AUDIO_DAC_DSM_DITHER_EN_UMSK (~(((1U << AUDIO_DAC_DSM_DITHER_EN_LEN) - 1) << AUDIO_DAC_DSM_DITHER_EN_POS)) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE AUDIO_DAC_DSM_DITHER_PRBS_MODE -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_POS (15U) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_LEN (2U) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_MSK (((1U << AUDIO_DAC_DSM_DITHER_PRBS_MODE_LEN) - 1) << AUDIO_DAC_DSM_DITHER_PRBS_MODE_POS) -#define AUDIO_DAC_DSM_DITHER_PRBS_MODE_UMSK (~(((1U << AUDIO_DAC_DSM_DITHER_PRBS_MODE_LEN) - 1) << AUDIO_DAC_DSM_DITHER_PRBS_MODE_POS)) -#define AUDIO_MIX_1_SEL AUDIO_MIX_1_SEL -#define AUDIO_MIX_1_SEL_POS (21U) -#define AUDIO_MIX_1_SEL_LEN (2U) -#define AUDIO_MIX_1_SEL_MSK (((1U << AUDIO_MIX_1_SEL_LEN) - 1) << AUDIO_MIX_1_SEL_POS) -#define AUDIO_MIX_1_SEL_UMSK (~(((1U << AUDIO_MIX_1_SEL_LEN) - 1) << AUDIO_MIX_1_SEL_POS)) -#define AUDIO_MIX_1_MODE AUDIO_MIX_1_MODE -#define AUDIO_MIX_1_MODE_POS (23U) -#define AUDIO_MIX_1_MODE_LEN (2U) -#define AUDIO_MIX_1_MODE_MSK (((1U << AUDIO_MIX_1_MODE_LEN) - 1) << AUDIO_MIX_1_MODE_POS) -#define AUDIO_MIX_1_MODE_UMSK (~(((1U << AUDIO_MIX_1_MODE_LEN) - 1) << AUDIO_MIX_1_MODE_POS)) -#define AUDIO_MIX_1_ATT_MODE1 AUDIO_MIX_1_ATT_MODE1 -#define AUDIO_MIX_1_ATT_MODE1_POS (25U) -#define AUDIO_MIX_1_ATT_MODE1_LEN (3U) -#define AUDIO_MIX_1_ATT_MODE1_MSK (((1U << AUDIO_MIX_1_ATT_MODE1_LEN) - 1) << AUDIO_MIX_1_ATT_MODE1_POS) -#define AUDIO_MIX_1_ATT_MODE1_UMSK (~(((1U << AUDIO_MIX_1_ATT_MODE1_LEN) - 1) << AUDIO_MIX_1_ATT_MODE1_POS)) -#define AUDIO_MIX_1_ATT_MODE2 AUDIO_MIX_1_ATT_MODE2 -#define AUDIO_MIX_1_ATT_MODE2_POS (28U) -#define AUDIO_MIX_1_ATT_MODE2_LEN (3U) -#define AUDIO_MIX_1_ATT_MODE2_MSK (((1U << AUDIO_MIX_1_ATT_MODE2_LEN) - 1) << AUDIO_MIX_1_ATT_MODE2_POS) -#define AUDIO_MIX_1_ATT_MODE2_UMSK (~(((1U << AUDIO_MIX_1_ATT_MODE2_LEN) - 1) << AUDIO_MIX_1_ATT_MODE2_POS)) - -/* 0x18 : aec_0 */ -#define AUDIO_AEC_0_OFFSET (0x18) -#define AUDIO_AEC_0_ATTEN_MODE AUDIO_AEC_0_ATTEN_MODE -#define AUDIO_AEC_0_ATTEN_MODE_POS (5U) -#define AUDIO_AEC_0_ATTEN_MODE_LEN (3U) -#define AUDIO_AEC_0_ATTEN_MODE_MSK (((1U << AUDIO_AEC_0_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_0_ATTEN_MODE_POS) -#define AUDIO_AEC_0_ATTEN_MODE_UMSK (~(((1U << AUDIO_AEC_0_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_0_ATTEN_MODE_POS)) -#define AUDIO_AEC_1_ATTEN_MODE AUDIO_AEC_1_ATTEN_MODE -#define AUDIO_AEC_1_ATTEN_MODE_POS (8U) -#define AUDIO_AEC_1_ATTEN_MODE_LEN (3U) -#define AUDIO_AEC_1_ATTEN_MODE_MSK (((1U << AUDIO_AEC_1_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_1_ATTEN_MODE_POS) -#define AUDIO_AEC_1_ATTEN_MODE_UMSK (~(((1U << AUDIO_AEC_1_ATTEN_MODE_LEN) - 1) << AUDIO_AEC_1_ATTEN_MODE_POS)) -#define AUDIO_AEC_RECORD_VLD_4S_DIV AUDIO_AEC_RECORD_VLD_4S_DIV -#define AUDIO_AEC_RECORD_VLD_4S_DIV_POS (11U) -#define AUDIO_AEC_RECORD_VLD_4S_DIV_LEN (2U) -#define AUDIO_AEC_RECORD_VLD_4S_DIV_MSK (((1U << AUDIO_AEC_RECORD_VLD_4S_DIV_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_DIV_POS) -#define AUDIO_AEC_RECORD_VLD_4S_DIV_UMSK (~(((1U << AUDIO_AEC_RECORD_VLD_4S_DIV_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_DIV_POS)) -#define AUDIO_AEC_RECORD_VLD_4S_EN AUDIO_AEC_RECORD_VLD_4S_EN -#define AUDIO_AEC_RECORD_VLD_4S_EN_POS (13U) -#define AUDIO_AEC_RECORD_VLD_4S_EN_LEN (1U) -#define AUDIO_AEC_RECORD_VLD_4S_EN_MSK (((1U << AUDIO_AEC_RECORD_VLD_4S_EN_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_EN_POS) -#define AUDIO_AEC_RECORD_VLD_4S_EN_UMSK (~(((1U << AUDIO_AEC_RECORD_VLD_4S_EN_LEN) - 1) << AUDIO_AEC_RECORD_VLD_4S_EN_POS)) - -/* 0x1C : pdm_0 */ -#define AUDIO_PDM_0_OFFSET (0x1C) -#define AUDIO_PDM_0_EN AUDIO_PDM_0_EN -#define AUDIO_PDM_0_EN_POS (0U) -#define AUDIO_PDM_0_EN_LEN (1U) -#define AUDIO_PDM_0_EN_MSK (((1U << AUDIO_PDM_0_EN_LEN) - 1) << AUDIO_PDM_0_EN_POS) -#define AUDIO_PDM_0_EN_UMSK (~(((1U << AUDIO_PDM_0_EN_LEN) - 1) << AUDIO_PDM_0_EN_POS)) -#define AUDIO_PDM_1_EN AUDIO_PDM_1_EN -#define AUDIO_PDM_1_EN_POS (1U) -#define AUDIO_PDM_1_EN_LEN (1U) -#define AUDIO_PDM_1_EN_MSK (((1U << AUDIO_PDM_1_EN_LEN) - 1) << AUDIO_PDM_1_EN_POS) -#define AUDIO_PDM_1_EN_UMSK (~(((1U << AUDIO_PDM_1_EN_LEN) - 1) << AUDIO_PDM_1_EN_POS)) -#define AUDIO_PDM_2_EN AUDIO_PDM_2_EN -#define AUDIO_PDM_2_EN_POS (2U) -#define AUDIO_PDM_2_EN_LEN (1U) -#define AUDIO_PDM_2_EN_MSK (((1U << AUDIO_PDM_2_EN_LEN) - 1) << AUDIO_PDM_2_EN_POS) -#define AUDIO_PDM_2_EN_UMSK (~(((1U << AUDIO_PDM_2_EN_LEN) - 1) << AUDIO_PDM_2_EN_POS)) -#define AUDIO_ADC_0_PDM_SEL AUDIO_ADC_0_PDM_SEL -#define AUDIO_ADC_0_PDM_SEL_POS (3U) -#define AUDIO_ADC_0_PDM_SEL_LEN (3U) -#define AUDIO_ADC_0_PDM_SEL_MSK (((1U << AUDIO_ADC_0_PDM_SEL_LEN) - 1) << AUDIO_ADC_0_PDM_SEL_POS) -#define AUDIO_ADC_0_PDM_SEL_UMSK (~(((1U << AUDIO_ADC_0_PDM_SEL_LEN) - 1) << AUDIO_ADC_0_PDM_SEL_POS)) -#define AUDIO_ADC_1_PDM_SEL AUDIO_ADC_1_PDM_SEL -#define AUDIO_ADC_1_PDM_SEL_POS (6U) -#define AUDIO_ADC_1_PDM_SEL_LEN (3U) -#define AUDIO_ADC_1_PDM_SEL_MSK (((1U << AUDIO_ADC_1_PDM_SEL_LEN) - 1) << AUDIO_ADC_1_PDM_SEL_POS) -#define AUDIO_ADC_1_PDM_SEL_UMSK (~(((1U << AUDIO_ADC_1_PDM_SEL_LEN) - 1) << AUDIO_ADC_1_PDM_SEL_POS)) -#define AUDIO_ADC_2_PDM_SEL AUDIO_ADC_2_PDM_SEL -#define AUDIO_ADC_2_PDM_SEL_POS (9U) -#define AUDIO_ADC_2_PDM_SEL_LEN (3U) -#define AUDIO_ADC_2_PDM_SEL_MSK (((1U << AUDIO_ADC_2_PDM_SEL_LEN) - 1) << AUDIO_ADC_2_PDM_SEL_POS) -#define AUDIO_ADC_2_PDM_SEL_UMSK (~(((1U << AUDIO_ADC_2_PDM_SEL_LEN) - 1) << AUDIO_ADC_2_PDM_SEL_POS)) - -/* 0x20 : rsvd0 */ -#define AUDIO_RSVD0_OFFSET (0x20) - -/* 0x24 : dbg_0 */ -#define AUDIO_DBG_0_OFFSET (0x24) -#define AUDIO_AUD_SIN_EN AUDIO_AUD_SIN_EN -#define AUDIO_AUD_SIN_EN_POS (0U) -#define AUDIO_AUD_SIN_EN_LEN (1U) -#define AUDIO_AUD_SIN_EN_MSK (((1U << AUDIO_AUD_SIN_EN_LEN) - 1) << AUDIO_AUD_SIN_EN_POS) -#define AUDIO_AUD_SIN_EN_UMSK (~(((1U << AUDIO_AUD_SIN_EN_LEN) - 1) << AUDIO_AUD_SIN_EN_POS)) -#define AUDIO_AUD_SIN_STEP AUDIO_AUD_SIN_STEP -#define AUDIO_AUD_SIN_STEP_POS (1U) -#define AUDIO_AUD_SIN_STEP_LEN (3U) -#define AUDIO_AUD_SIN_STEP_MSK (((1U << AUDIO_AUD_SIN_STEP_LEN) - 1) << AUDIO_AUD_SIN_STEP_POS) -#define AUDIO_AUD_SIN_STEP_UMSK (~(((1U << AUDIO_AUD_SIN_STEP_LEN) - 1) << AUDIO_AUD_SIN_STEP_POS)) -#define AUDIO_TEST_OUT_SEL AUDIO_TEST_OUT_SEL -#define AUDIO_TEST_OUT_SEL_POS (18U) -#define AUDIO_TEST_OUT_SEL_LEN (2U) -#define AUDIO_TEST_OUT_SEL_MSK (((1U << AUDIO_TEST_OUT_SEL_LEN) - 1) << AUDIO_TEST_OUT_SEL_POS) -#define AUDIO_TEST_OUT_SEL_UMSK (~(((1U << AUDIO_TEST_OUT_SEL_LEN) - 1) << AUDIO_TEST_OUT_SEL_POS)) -#define AUDIO_DAC_TEST_CLKIN_EN AUDIO_DAC_TEST_CLKIN_EN -#define AUDIO_DAC_TEST_CLKIN_EN_POS (20U) -#define AUDIO_DAC_TEST_CLKIN_EN_LEN (1U) -#define AUDIO_DAC_TEST_CLKIN_EN_MSK (((1U << AUDIO_DAC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_DAC_TEST_CLKIN_EN_POS) -#define AUDIO_DAC_TEST_CLKIN_EN_UMSK (~(((1U << AUDIO_DAC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_DAC_TEST_CLKIN_EN_POS)) -#define AUDIO_ADC_TEST_CLKIN_EN AUDIO_ADC_TEST_CLKIN_EN -#define AUDIO_ADC_TEST_CLKIN_EN_POS (21U) -#define AUDIO_ADC_TEST_CLKIN_EN_LEN (1U) -#define AUDIO_ADC_TEST_CLKIN_EN_MSK (((1U << AUDIO_ADC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_ADC_TEST_CLKIN_EN_POS) -#define AUDIO_ADC_TEST_CLKIN_EN_UMSK (~(((1U << AUDIO_ADC_TEST_CLKIN_EN_LEN) - 1) << AUDIO_ADC_TEST_CLKIN_EN_POS)) -#define AUDIO_DAC_TEST_DIN_EN AUDIO_DAC_TEST_DIN_EN -#define AUDIO_DAC_TEST_DIN_EN_POS (22U) -#define AUDIO_DAC_TEST_DIN_EN_LEN (1U) -#define AUDIO_DAC_TEST_DIN_EN_MSK (((1U << AUDIO_DAC_TEST_DIN_EN_LEN) - 1) << AUDIO_DAC_TEST_DIN_EN_POS) -#define AUDIO_DAC_TEST_DIN_EN_UMSK (~(((1U << AUDIO_DAC_TEST_DIN_EN_LEN) - 1) << AUDIO_DAC_TEST_DIN_EN_POS)) -#define AUDIO_ADC_TEST_DIN_EN AUDIO_ADC_TEST_DIN_EN -#define AUDIO_ADC_TEST_DIN_EN_POS (23U) -#define AUDIO_ADC_TEST_DIN_EN_LEN (1U) -#define AUDIO_ADC_TEST_DIN_EN_MSK (((1U << AUDIO_ADC_TEST_DIN_EN_LEN) - 1) << AUDIO_ADC_TEST_DIN_EN_POS) -#define AUDIO_ADC_TEST_DIN_EN_UMSK (~(((1U << AUDIO_ADC_TEST_DIN_EN_LEN) - 1) << AUDIO_ADC_TEST_DIN_EN_POS)) -#define AUDIO_AUD_TEST_READ_SEL AUDIO_AUD_TEST_READ_SEL -#define AUDIO_AUD_TEST_READ_SEL_POS (24U) -#define AUDIO_AUD_TEST_READ_SEL_LEN (6U) -#define AUDIO_AUD_TEST_READ_SEL_MSK (((1U << AUDIO_AUD_TEST_READ_SEL_LEN) - 1) << AUDIO_AUD_TEST_READ_SEL_POS) -#define AUDIO_AUD_TEST_READ_SEL_UMSK (~(((1U << AUDIO_AUD_TEST_READ_SEL_LEN) - 1) << AUDIO_AUD_TEST_READ_SEL_POS)) - -/* 0x28 : dbg_1 */ -#define AUDIO_DBG_1_OFFSET (0x28) -#define AUDIO_AUD_TEST_READ AUDIO_AUD_TEST_READ -#define AUDIO_AUD_TEST_READ_POS (0U) -#define AUDIO_AUD_TEST_READ_LEN (32U) -#define AUDIO_AUD_TEST_READ_MSK (((1U << AUDIO_AUD_TEST_READ_LEN) - 1) << AUDIO_AUD_TEST_READ_POS) -#define AUDIO_AUD_TEST_READ_UMSK (~(((1U << AUDIO_AUD_TEST_READ_LEN) - 1) << AUDIO_AUD_TEST_READ_POS)) - -/* 0x2C : dbg_2 */ -#define AUDIO_DBG_2_OFFSET (0x2C) -#define AUDIO_ADC_FIR_4S_VAL AUDIO_ADC_FIR_4S_VAL -#define AUDIO_ADC_FIR_4S_VAL_POS (0U) -#define AUDIO_ADC_FIR_4S_VAL_LEN (20U) -#define AUDIO_ADC_FIR_4S_VAL_MSK (((1U << AUDIO_ADC_FIR_4S_VAL_LEN) - 1) << AUDIO_ADC_FIR_4S_VAL_POS) -#define AUDIO_ADC_FIR_4S_VAL_UMSK (~(((1U << AUDIO_ADC_FIR_4S_VAL_LEN) - 1) << AUDIO_ADC_FIR_4S_VAL_POS)) -#define AUDIO_ADC_0_FIR_4S_EN AUDIO_ADC_0_FIR_4S_EN -#define AUDIO_ADC_0_FIR_4S_EN_POS (20U) -#define AUDIO_ADC_0_FIR_4S_EN_LEN (1U) -#define AUDIO_ADC_0_FIR_4S_EN_MSK (((1U << AUDIO_ADC_0_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_0_FIR_4S_EN_POS) -#define AUDIO_ADC_0_FIR_4S_EN_UMSK (~(((1U << AUDIO_ADC_0_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_0_FIR_4S_EN_POS)) -#define AUDIO_ADC_1_FIR_4S_EN AUDIO_ADC_1_FIR_4S_EN -#define AUDIO_ADC_1_FIR_4S_EN_POS (21U) -#define AUDIO_ADC_1_FIR_4S_EN_LEN (1U) -#define AUDIO_ADC_1_FIR_4S_EN_MSK (((1U << AUDIO_ADC_1_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_1_FIR_4S_EN_POS) -#define AUDIO_ADC_1_FIR_4S_EN_UMSK (~(((1U << AUDIO_ADC_1_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_1_FIR_4S_EN_POS)) -#define AUDIO_ADC_2_FIR_4S_EN AUDIO_ADC_2_FIR_4S_EN -#define AUDIO_ADC_2_FIR_4S_EN_POS (22U) -#define AUDIO_ADC_2_FIR_4S_EN_LEN (1U) -#define AUDIO_ADC_2_FIR_4S_EN_MSK (((1U << AUDIO_ADC_2_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_2_FIR_4S_EN_POS) -#define AUDIO_ADC_2_FIR_4S_EN_UMSK (~(((1U << AUDIO_ADC_2_FIR_4S_EN_LEN) - 1) << AUDIO_ADC_2_FIR_4S_EN_POS)) -#define AUDIO_ADC_IN_0_TEST_SEL AUDIO_ADC_IN_0_TEST_SEL -#define AUDIO_ADC_IN_0_TEST_SEL_POS (23U) -#define AUDIO_ADC_IN_0_TEST_SEL_LEN (1U) -#define AUDIO_ADC_IN_0_TEST_SEL_MSK (((1U << AUDIO_ADC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_0_TEST_SEL_POS) -#define AUDIO_ADC_IN_0_TEST_SEL_UMSK (~(((1U << AUDIO_ADC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_0_TEST_SEL_POS)) -#define AUDIO_ADC_IN_1_TEST_SEL AUDIO_ADC_IN_1_TEST_SEL -#define AUDIO_ADC_IN_1_TEST_SEL_POS (24U) -#define AUDIO_ADC_IN_1_TEST_SEL_LEN (1U) -#define AUDIO_ADC_IN_1_TEST_SEL_MSK (((1U << AUDIO_ADC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_1_TEST_SEL_POS) -#define AUDIO_ADC_IN_1_TEST_SEL_UMSK (~(((1U << AUDIO_ADC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_1_TEST_SEL_POS)) -#define AUDIO_ADC_IN_2_TEST_SEL AUDIO_ADC_IN_2_TEST_SEL -#define AUDIO_ADC_IN_2_TEST_SEL_POS (25U) -#define AUDIO_ADC_IN_2_TEST_SEL_LEN (1U) -#define AUDIO_ADC_IN_2_TEST_SEL_MSK (((1U << AUDIO_ADC_IN_2_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_2_TEST_SEL_POS) -#define AUDIO_ADC_IN_2_TEST_SEL_UMSK (~(((1U << AUDIO_ADC_IN_2_TEST_SEL_LEN) - 1) << AUDIO_ADC_IN_2_TEST_SEL_POS)) - -/* 0x30 : dbg_3 */ -#define AUDIO_DBG_3_OFFSET (0x30) -#define AUDIO_DAC_4S_VAL AUDIO_DAC_4S_VAL -#define AUDIO_DAC_4S_VAL_POS (0U) -#define AUDIO_DAC_4S_VAL_LEN (20U) -#define AUDIO_DAC_4S_VAL_MSK (((1U << AUDIO_DAC_4S_VAL_LEN) - 1) << AUDIO_DAC_4S_VAL_POS) -#define AUDIO_DAC_4S_VAL_UMSK (~(((1U << AUDIO_DAC_4S_VAL_LEN) - 1) << AUDIO_DAC_4S_VAL_POS)) -#define AUDIO_DAC_DWA_0_4S_EN AUDIO_DAC_DWA_0_4S_EN -#define AUDIO_DAC_DWA_0_4S_EN_POS (20U) -#define AUDIO_DAC_DWA_0_4S_EN_LEN (1U) -#define AUDIO_DAC_DWA_0_4S_EN_MSK (((1U << AUDIO_DAC_DWA_0_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_0_4S_EN_POS) -#define AUDIO_DAC_DWA_0_4S_EN_UMSK (~(((1U << AUDIO_DAC_DWA_0_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_0_4S_EN_POS)) -#define AUDIO_DAC_DWA_1_4S_EN AUDIO_DAC_DWA_1_4S_EN -#define AUDIO_DAC_DWA_1_4S_EN_POS (21U) -#define AUDIO_DAC_DWA_1_4S_EN_LEN (1U) -#define AUDIO_DAC_DWA_1_4S_EN_MSK (((1U << AUDIO_DAC_DWA_1_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_1_4S_EN_POS) -#define AUDIO_DAC_DWA_1_4S_EN_UMSK (~(((1U << AUDIO_DAC_DWA_1_4S_EN_LEN) - 1) << AUDIO_DAC_DWA_1_4S_EN_POS)) -#define AUDIO_DAC_IN_0_TEST_SEL AUDIO_DAC_IN_0_TEST_SEL -#define AUDIO_DAC_IN_0_TEST_SEL_POS (22U) -#define AUDIO_DAC_IN_0_TEST_SEL_LEN (1U) -#define AUDIO_DAC_IN_0_TEST_SEL_MSK (((1U << AUDIO_DAC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_0_TEST_SEL_POS) -#define AUDIO_DAC_IN_0_TEST_SEL_UMSK (~(((1U << AUDIO_DAC_IN_0_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_0_TEST_SEL_POS)) -#define AUDIO_DAC_IN_1_TEST_SEL AUDIO_DAC_IN_1_TEST_SEL -#define AUDIO_DAC_IN_1_TEST_SEL_POS (23U) -#define AUDIO_DAC_IN_1_TEST_SEL_LEN (1U) -#define AUDIO_DAC_IN_1_TEST_SEL_MSK (((1U << AUDIO_DAC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_1_TEST_SEL_POS) -#define AUDIO_DAC_IN_1_TEST_SEL_UMSK (~(((1U << AUDIO_DAC_IN_1_TEST_SEL_LEN) - 1) << AUDIO_DAC_IN_1_TEST_SEL_POS)) - -/* 0x34 : dbg_4 */ -#define AUDIO_DBG_4_OFFSET (0x34) -#define AUDIO_ADC_IN_RATIO_4S_VAL AUDIO_ADC_IN_RATIO_4S_VAL -#define AUDIO_ADC_IN_RATIO_4S_VAL_POS (0U) -#define AUDIO_ADC_IN_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_RATIO_4S_VAL_POS)) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL AUDIO_ADC_IN_CH0_RATIO_4S_VAL -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_POS (1U) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_CH0_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH0_RATIO_4S_VAL_POS)) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL AUDIO_ADC_IN_CH1_RATIO_4S_VAL -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_POS (2U) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_CH1_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH1_RATIO_4S_VAL_POS)) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL AUDIO_ADC_IN_CH2_RATIO_4S_VAL -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_POS (3U) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_LEN (1U) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_MSK (((1U << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_POS) -#define AUDIO_ADC_IN_CH2_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << AUDIO_ADC_IN_CH2_RATIO_4S_VAL_POS)) -#define AUDIO_PDM_IN_RATIO_4S_VAL AUDIO_PDM_IN_RATIO_4S_VAL -#define AUDIO_PDM_IN_RATIO_4S_VAL_POS (4U) -#define AUDIO_PDM_IN_RATIO_4S_VAL_LEN (1U) -#define AUDIO_PDM_IN_RATIO_4S_VAL_MSK (((1U << AUDIO_PDM_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_VAL_POS) -#define AUDIO_PDM_IN_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_PDM_IN_RATIO_4S_VAL_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_VAL_POS)) -#define AUDIO_PDM_IN_RATIO_4S AUDIO_PDM_IN_RATIO_4S -#define AUDIO_PDM_IN_RATIO_4S_POS (5U) -#define AUDIO_PDM_IN_RATIO_4S_LEN (1U) -#define AUDIO_PDM_IN_RATIO_4S_MSK (((1U << AUDIO_PDM_IN_RATIO_4S_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_POS) -#define AUDIO_PDM_IN_RATIO_4S_UMSK (~(((1U << AUDIO_PDM_IN_RATIO_4S_LEN) - 1) << AUDIO_PDM_IN_RATIO_4S_POS)) -#define AUDIO_DAC_OUT_RATIO_4S_VAL AUDIO_DAC_OUT_RATIO_4S_VAL -#define AUDIO_DAC_OUT_RATIO_4S_VAL_POS (6U) -#define AUDIO_DAC_OUT_RATIO_4S_VAL_LEN (2U) -#define AUDIO_DAC_OUT_RATIO_4S_VAL_MSK (((1U << AUDIO_DAC_OUT_RATIO_4S_VAL_LEN) - 1) << AUDIO_DAC_OUT_RATIO_4S_VAL_POS) -#define AUDIO_DAC_OUT_RATIO_4S_VAL_UMSK (~(((1U << AUDIO_DAC_OUT_RATIO_4S_VAL_LEN) - 1) << AUDIO_DAC_OUT_RATIO_4S_VAL_POS)) -#define AUDIO_AEC_FS_RATE_4S_VAL AUDIO_AEC_FS_RATE_4S_VAL -#define AUDIO_AEC_FS_RATE_4S_VAL_POS (8U) -#define AUDIO_AEC_FS_RATE_4S_VAL_LEN (3U) -#define AUDIO_AEC_FS_RATE_4S_VAL_MSK (((1U << AUDIO_AEC_FS_RATE_4S_VAL_LEN) - 1) << AUDIO_AEC_FS_RATE_4S_VAL_POS) -#define AUDIO_AEC_FS_RATE_4S_VAL_UMSK (~(((1U << AUDIO_AEC_FS_RATE_4S_VAL_LEN) - 1) << AUDIO_AEC_FS_RATE_4S_VAL_POS)) - -/* 0x80 : rx_fifo_ctrl */ -#define AUDIO_RX_FIFO_CTRL_OFFSET (0x80) -#define AUDIO_RX_FIFO_FLUSH AUDIO_RX_FIFO_FLUSH -#define AUDIO_RX_FIFO_FLUSH_POS (0U) -#define AUDIO_RX_FIFO_FLUSH_LEN (1U) -#define AUDIO_RX_FIFO_FLUSH_MSK (((1U << AUDIO_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_RX_FIFO_FLUSH_POS) -#define AUDIO_RX_FIFO_FLUSH_UMSK (~(((1U << AUDIO_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_RX_FIFO_FLUSH_POS)) -#define AUDIO_RXO_INT_EN AUDIO_RXO_INT_EN -#define AUDIO_RXO_INT_EN_POS (1U) -#define AUDIO_RXO_INT_EN_LEN (1U) -#define AUDIO_RXO_INT_EN_MSK (((1U << AUDIO_RXO_INT_EN_LEN) - 1) << AUDIO_RXO_INT_EN_POS) -#define AUDIO_RXO_INT_EN_UMSK (~(((1U << AUDIO_RXO_INT_EN_LEN) - 1) << AUDIO_RXO_INT_EN_POS)) -#define AUDIO_RXU_INT_EN AUDIO_RXU_INT_EN -#define AUDIO_RXU_INT_EN_POS (2U) -#define AUDIO_RXU_INT_EN_LEN (1U) -#define AUDIO_RXU_INT_EN_MSK (((1U << AUDIO_RXU_INT_EN_LEN) - 1) << AUDIO_RXU_INT_EN_POS) -#define AUDIO_RXU_INT_EN_UMSK (~(((1U << AUDIO_RXU_INT_EN_LEN) - 1) << AUDIO_RXU_INT_EN_POS)) -#define AUDIO_RXA_INT_EN AUDIO_RXA_INT_EN -#define AUDIO_RXA_INT_EN_POS (3U) -#define AUDIO_RXA_INT_EN_LEN (1U) -#define AUDIO_RXA_INT_EN_MSK (((1U << AUDIO_RXA_INT_EN_LEN) - 1) << AUDIO_RXA_INT_EN_POS) -#define AUDIO_RXA_INT_EN_UMSK (~(((1U << AUDIO_RXA_INT_EN_LEN) - 1) << AUDIO_RXA_INT_EN_POS)) -#define AUDIO_RX_DRQ_EN AUDIO_RX_DRQ_EN -#define AUDIO_RX_DRQ_EN_POS (4U) -#define AUDIO_RX_DRQ_EN_LEN (1U) -#define AUDIO_RX_DRQ_EN_MSK (((1U << AUDIO_RX_DRQ_EN_LEN) - 1) << AUDIO_RX_DRQ_EN_POS) -#define AUDIO_RX_DRQ_EN_UMSK (~(((1U << AUDIO_RX_DRQ_EN_LEN) - 1) << AUDIO_RX_DRQ_EN_POS)) -#define AUDIO_RX_DATA_RES AUDIO_RX_DATA_RES -#define AUDIO_RX_DATA_RES_POS (5U) -#define AUDIO_RX_DATA_RES_LEN (1U) -#define AUDIO_RX_DATA_RES_MSK (((1U << AUDIO_RX_DATA_RES_LEN) - 1) << AUDIO_RX_DATA_RES_POS) -#define AUDIO_RX_DATA_RES_UMSK (~(((1U << AUDIO_RX_DATA_RES_LEN) - 1) << AUDIO_RX_DATA_RES_POS)) -#define AUDIO_RX_CH_EN AUDIO_RX_CH_EN -#define AUDIO_RX_CH_EN_POS (8U) -#define AUDIO_RX_CH_EN_LEN (5U) -#define AUDIO_RX_CH_EN_MSK (((1U << AUDIO_RX_CH_EN_LEN) - 1) << AUDIO_RX_CH_EN_POS) -#define AUDIO_RX_CH_EN_UMSK (~(((1U << AUDIO_RX_CH_EN_LEN) - 1) << AUDIO_RX_CH_EN_POS)) -#define AUDIO_RX_DRQ_CNT AUDIO_RX_DRQ_CNT -#define AUDIO_RX_DRQ_CNT_POS (14U) -#define AUDIO_RX_DRQ_CNT_LEN (2U) -#define AUDIO_RX_DRQ_CNT_MSK (((1U << AUDIO_RX_DRQ_CNT_LEN) - 1) << AUDIO_RX_DRQ_CNT_POS) -#define AUDIO_RX_DRQ_CNT_UMSK (~(((1U << AUDIO_RX_DRQ_CNT_LEN) - 1) << AUDIO_RX_DRQ_CNT_POS)) -#define AUDIO_RX_TRG_LEVEL AUDIO_RX_TRG_LEVEL -#define AUDIO_RX_TRG_LEVEL_POS (16U) -#define AUDIO_RX_TRG_LEVEL_LEN (7U) -#define AUDIO_RX_TRG_LEVEL_MSK (((1U << AUDIO_RX_TRG_LEVEL_LEN) - 1) << AUDIO_RX_TRG_LEVEL_POS) -#define AUDIO_RX_TRG_LEVEL_UMSK (~(((1U << AUDIO_RX_TRG_LEVEL_LEN) - 1) << AUDIO_RX_TRG_LEVEL_POS)) -#define AUDIO_RX_DATA_MODE AUDIO_RX_DATA_MODE -#define AUDIO_RX_DATA_MODE_POS (24U) -#define AUDIO_RX_DATA_MODE_LEN (2U) -#define AUDIO_RX_DATA_MODE_MSK (((1U << AUDIO_RX_DATA_MODE_LEN) - 1) << AUDIO_RX_DATA_MODE_POS) -#define AUDIO_RX_DATA_MODE_UMSK (~(((1U << AUDIO_RX_DATA_MODE_LEN) - 1) << AUDIO_RX_DATA_MODE_POS)) - -/* 0x84 : rx_fifo_status */ -#define AUDIO_RX_FIFO_STATUS_OFFSET (0x84) -#define AUDIO_RXO_INT AUDIO_RXO_INT -#define AUDIO_RXO_INT_POS (1U) -#define AUDIO_RXO_INT_LEN (1U) -#define AUDIO_RXO_INT_MSK (((1U << AUDIO_RXO_INT_LEN) - 1) << AUDIO_RXO_INT_POS) -#define AUDIO_RXO_INT_UMSK (~(((1U << AUDIO_RXO_INT_LEN) - 1) << AUDIO_RXO_INT_POS)) -#define AUDIO_RXU_INT AUDIO_RXU_INT -#define AUDIO_RXU_INT_POS (2U) -#define AUDIO_RXU_INT_LEN (1U) -#define AUDIO_RXU_INT_MSK (((1U << AUDIO_RXU_INT_LEN) - 1) << AUDIO_RXU_INT_POS) -#define AUDIO_RXU_INT_UMSK (~(((1U << AUDIO_RXU_INT_LEN) - 1) << AUDIO_RXU_INT_POS)) -#define AUDIO_RXA_INT AUDIO_RXA_INT -#define AUDIO_RXA_INT_POS (4U) -#define AUDIO_RXA_INT_LEN (1U) -#define AUDIO_RXA_INT_MSK (((1U << AUDIO_RXA_INT_LEN) - 1) << AUDIO_RXA_INT_POS) -#define AUDIO_RXA_INT_UMSK (~(((1U << AUDIO_RXA_INT_LEN) - 1) << AUDIO_RXA_INT_POS)) -#define AUDIO_RXA_CNT AUDIO_RXA_CNT -#define AUDIO_RXA_CNT_POS (16U) -#define AUDIO_RXA_CNT_LEN (7U) -#define AUDIO_RXA_CNT_MSK (((1U << AUDIO_RXA_CNT_LEN) - 1) << AUDIO_RXA_CNT_POS) -#define AUDIO_RXA_CNT_UMSK (~(((1U << AUDIO_RXA_CNT_LEN) - 1) << AUDIO_RXA_CNT_POS)) -#define AUDIO_RXA AUDIO_RXA -#define AUDIO_RXA_POS (24U) -#define AUDIO_RXA_LEN (1U) -#define AUDIO_RXA_MSK (((1U << AUDIO_RXA_LEN) - 1) << AUDIO_RXA_POS) -#define AUDIO_RXA_UMSK (~(((1U << AUDIO_RXA_LEN) - 1) << AUDIO_RXA_POS)) - -/* 0x88 : rx_fifo_data */ -#define AUDIO_RX_FIFO_DATA_OFFSET (0x88) -#define AUDIO_RX_DATA AUDIO_RX_DATA -#define AUDIO_RX_DATA_POS (0U) -#define AUDIO_RX_DATA_LEN (32U) -#define AUDIO_RX_DATA_MSK (((1U << AUDIO_RX_DATA_LEN) - 1) << AUDIO_RX_DATA_POS) -#define AUDIO_RX_DATA_UMSK (~(((1U << AUDIO_RX_DATA_LEN) - 1) << AUDIO_RX_DATA_POS)) - -/* 0x8C : tx_fifo_ctrl */ -#define AUDIO_TX_FIFO_CTRL_OFFSET (0x8C) -#define AUDIO_TX_FIFO_FLUSH AUDIO_TX_FIFO_FLUSH -#define AUDIO_TX_FIFO_FLUSH_POS (0U) -#define AUDIO_TX_FIFO_FLUSH_LEN (1U) -#define AUDIO_TX_FIFO_FLUSH_MSK (((1U << AUDIO_TX_FIFO_FLUSH_LEN) - 1) << AUDIO_TX_FIFO_FLUSH_POS) -#define AUDIO_TX_FIFO_FLUSH_UMSK (~(((1U << AUDIO_TX_FIFO_FLUSH_LEN) - 1) << AUDIO_TX_FIFO_FLUSH_POS)) -#define AUDIO_TXO_INT_EN AUDIO_TXO_INT_EN -#define AUDIO_TXO_INT_EN_POS (1U) -#define AUDIO_TXO_INT_EN_LEN (1U) -#define AUDIO_TXO_INT_EN_MSK (((1U << AUDIO_TXO_INT_EN_LEN) - 1) << AUDIO_TXO_INT_EN_POS) -#define AUDIO_TXO_INT_EN_UMSK (~(((1U << AUDIO_TXO_INT_EN_LEN) - 1) << AUDIO_TXO_INT_EN_POS)) -#define AUDIO_TXU_INT_EN AUDIO_TXU_INT_EN -#define AUDIO_TXU_INT_EN_POS (2U) -#define AUDIO_TXU_INT_EN_LEN (1U) -#define AUDIO_TXU_INT_EN_MSK (((1U << AUDIO_TXU_INT_EN_LEN) - 1) << AUDIO_TXU_INT_EN_POS) -#define AUDIO_TXU_INT_EN_UMSK (~(((1U << AUDIO_TXU_INT_EN_LEN) - 1) << AUDIO_TXU_INT_EN_POS)) -#define AUDIO_TXA_INT_EN AUDIO_TXA_INT_EN -#define AUDIO_TXA_INT_EN_POS (3U) -#define AUDIO_TXA_INT_EN_LEN (1U) -#define AUDIO_TXA_INT_EN_MSK (((1U << AUDIO_TXA_INT_EN_LEN) - 1) << AUDIO_TXA_INT_EN_POS) -#define AUDIO_TXA_INT_EN_UMSK (~(((1U << AUDIO_TXA_INT_EN_LEN) - 1) << AUDIO_TXA_INT_EN_POS)) -#define AUDIO_TX_DRQ_EN AUDIO_TX_DRQ_EN -#define AUDIO_TX_DRQ_EN_POS (4U) -#define AUDIO_TX_DRQ_EN_LEN (1U) -#define AUDIO_TX_DRQ_EN_MSK (((1U << AUDIO_TX_DRQ_EN_LEN) - 1) << AUDIO_TX_DRQ_EN_POS) -#define AUDIO_TX_DRQ_EN_UMSK (~(((1U << AUDIO_TX_DRQ_EN_LEN) - 1) << AUDIO_TX_DRQ_EN_POS)) -#define AUDIO_TX_DATA_RES AUDIO_TX_DATA_RES -#define AUDIO_TX_DATA_RES_POS (5U) -#define AUDIO_TX_DATA_RES_LEN (1U) -#define AUDIO_TX_DATA_RES_MSK (((1U << AUDIO_TX_DATA_RES_LEN) - 1) << AUDIO_TX_DATA_RES_POS) -#define AUDIO_TX_DATA_RES_UMSK (~(((1U << AUDIO_TX_DATA_RES_LEN) - 1) << AUDIO_TX_DATA_RES_POS)) -#define AUDIO_TX_CH_EN AUDIO_TX_CH_EN -#define AUDIO_TX_CH_EN_POS (8U) -#define AUDIO_TX_CH_EN_LEN (2U) -#define AUDIO_TX_CH_EN_MSK (((1U << AUDIO_TX_CH_EN_LEN) - 1) << AUDIO_TX_CH_EN_POS) -#define AUDIO_TX_CH_EN_UMSK (~(((1U << AUDIO_TX_CH_EN_LEN) - 1) << AUDIO_TX_CH_EN_POS)) -#define AUDIO_TX_DRQ_CNT AUDIO_TX_DRQ_CNT -#define AUDIO_TX_DRQ_CNT_POS (14U) -#define AUDIO_TX_DRQ_CNT_LEN (2U) -#define AUDIO_TX_DRQ_CNT_MSK (((1U << AUDIO_TX_DRQ_CNT_LEN) - 1) << AUDIO_TX_DRQ_CNT_POS) -#define AUDIO_TX_DRQ_CNT_UMSK (~(((1U << AUDIO_TX_DRQ_CNT_LEN) - 1) << AUDIO_TX_DRQ_CNT_POS)) -#define AUDIO_TX_TRG_LEVEL AUDIO_TX_TRG_LEVEL -#define AUDIO_TX_TRG_LEVEL_POS (16U) -#define AUDIO_TX_TRG_LEVEL_LEN (6U) -#define AUDIO_TX_TRG_LEVEL_MSK (((1U << AUDIO_TX_TRG_LEVEL_LEN) - 1) << AUDIO_TX_TRG_LEVEL_POS) -#define AUDIO_TX_TRG_LEVEL_UMSK (~(((1U << AUDIO_TX_TRG_LEVEL_LEN) - 1) << AUDIO_TX_TRG_LEVEL_POS)) -#define AUDIO_TX_DATA_MODE AUDIO_TX_DATA_MODE -#define AUDIO_TX_DATA_MODE_POS (24U) -#define AUDIO_TX_DATA_MODE_LEN (2U) -#define AUDIO_TX_DATA_MODE_MSK (((1U << AUDIO_TX_DATA_MODE_LEN) - 1) << AUDIO_TX_DATA_MODE_POS) -#define AUDIO_TX_DATA_MODE_UMSK (~(((1U << AUDIO_TX_DATA_MODE_LEN) - 1) << AUDIO_TX_DATA_MODE_POS)) - -/* 0x90 : tx_fifo_status */ -#define AUDIO_TX_FIFO_STATUS_OFFSET (0x90) -#define AUDIO_TXO_INT AUDIO_TXO_INT -#define AUDIO_TXO_INT_POS (1U) -#define AUDIO_TXO_INT_LEN (1U) -#define AUDIO_TXO_INT_MSK (((1U << AUDIO_TXO_INT_LEN) - 1) << AUDIO_TXO_INT_POS) -#define AUDIO_TXO_INT_UMSK (~(((1U << AUDIO_TXO_INT_LEN) - 1) << AUDIO_TXO_INT_POS)) -#define AUDIO_TXU_INT AUDIO_TXU_INT -#define AUDIO_TXU_INT_POS (2U) -#define AUDIO_TXU_INT_LEN (1U) -#define AUDIO_TXU_INT_MSK (((1U << AUDIO_TXU_INT_LEN) - 1) << AUDIO_TXU_INT_POS) -#define AUDIO_TXU_INT_UMSK (~(((1U << AUDIO_TXU_INT_LEN) - 1) << AUDIO_TXU_INT_POS)) -#define AUDIO_TXA_INT AUDIO_TXA_INT -#define AUDIO_TXA_INT_POS (4U) -#define AUDIO_TXA_INT_LEN (1U) -#define AUDIO_TXA_INT_MSK (((1U << AUDIO_TXA_INT_LEN) - 1) << AUDIO_TXA_INT_POS) -#define AUDIO_TXA_INT_UMSK (~(((1U << AUDIO_TXA_INT_LEN) - 1) << AUDIO_TXA_INT_POS)) -#define AUDIO_TXA_CNT AUDIO_TXA_CNT -#define AUDIO_TXA_CNT_POS (16U) -#define AUDIO_TXA_CNT_LEN (6U) -#define AUDIO_TXA_CNT_MSK (((1U << AUDIO_TXA_CNT_LEN) - 1) << AUDIO_TXA_CNT_POS) -#define AUDIO_TXA_CNT_UMSK (~(((1U << AUDIO_TXA_CNT_LEN) - 1) << AUDIO_TXA_CNT_POS)) -#define AUDIO_TXA AUDIO_TXA -#define AUDIO_TXA_POS (24U) -#define AUDIO_TXA_LEN (1U) -#define AUDIO_TXA_MSK (((1U << AUDIO_TXA_LEN) - 1) << AUDIO_TXA_POS) -#define AUDIO_TXA_UMSK (~(((1U << AUDIO_TXA_LEN) - 1) << AUDIO_TXA_POS)) - -/* 0x94 : tx_fifo_data */ -#define AUDIO_TX_FIFO_DATA_OFFSET (0x94) -#define AUDIO_TX_DATA AUDIO_TX_DATA -#define AUDIO_TX_DATA_POS (0U) -#define AUDIO_TX_DATA_LEN (32U) -#define AUDIO_TX_DATA_MSK (((1U << AUDIO_TX_DATA_LEN) - 1) << AUDIO_TX_DATA_POS) -#define AUDIO_TX_DATA_UMSK (~(((1U << AUDIO_TX_DATA_LEN) - 1) << AUDIO_TX_DATA_POS)) - -/* 0x200 : peq_00_b0 */ -#define AUDIO_PEQ_00_B0_OFFSET (0x200) -#define AUDIO_PEQ_00_B0 AUDIO_PEQ_00_B0 -#define AUDIO_PEQ_00_B0_POS (0U) -#define AUDIO_PEQ_00_B0_LEN (20U) -#define AUDIO_PEQ_00_B0_MSK (((1U << AUDIO_PEQ_00_B0_LEN) - 1) << AUDIO_PEQ_00_B0_POS) -#define AUDIO_PEQ_00_B0_UMSK (~(((1U << AUDIO_PEQ_00_B0_LEN) - 1) << AUDIO_PEQ_00_B0_POS)) -#define AUDIO_PEQ_00_BYP AUDIO_PEQ_00_BYP -#define AUDIO_PEQ_00_BYP_POS (20U) -#define AUDIO_PEQ_00_BYP_LEN (1U) -#define AUDIO_PEQ_00_BYP_MSK (((1U << AUDIO_PEQ_00_BYP_LEN) - 1) << AUDIO_PEQ_00_BYP_POS) -#define AUDIO_PEQ_00_BYP_UMSK (~(((1U << AUDIO_PEQ_00_BYP_LEN) - 1) << AUDIO_PEQ_00_BYP_POS)) -#define AUDIO_PEQ_00_QFMT AUDIO_PEQ_00_QFMT -#define AUDIO_PEQ_00_QFMT_POS (21U) -#define AUDIO_PEQ_00_QFMT_LEN (1U) -#define AUDIO_PEQ_00_QFMT_MSK (((1U << AUDIO_PEQ_00_QFMT_LEN) - 1) << AUDIO_PEQ_00_QFMT_POS) -#define AUDIO_PEQ_00_QFMT_UMSK (~(((1U << AUDIO_PEQ_00_QFMT_LEN) - 1) << AUDIO_PEQ_00_QFMT_POS)) - -/* 0x204 : peq_00_b1 */ -#define AUDIO_PEQ_00_B1_OFFSET (0x204) -#define AUDIO_PEQ_00_B1 AUDIO_PEQ_00_B1 -#define AUDIO_PEQ_00_B1_POS (0U) -#define AUDIO_PEQ_00_B1_LEN (20U) -#define AUDIO_PEQ_00_B1_MSK (((1U << AUDIO_PEQ_00_B1_LEN) - 1) << AUDIO_PEQ_00_B1_POS) -#define AUDIO_PEQ_00_B1_UMSK (~(((1U << AUDIO_PEQ_00_B1_LEN) - 1) << AUDIO_PEQ_00_B1_POS)) - -/* 0x208 : peq_00_b2 */ -#define AUDIO_PEQ_00_B2_OFFSET (0x208) -#define AUDIO_PEQ_00_B2 AUDIO_PEQ_00_B2 -#define AUDIO_PEQ_00_B2_POS (0U) -#define AUDIO_PEQ_00_B2_LEN (20U) -#define AUDIO_PEQ_00_B2_MSK (((1U << AUDIO_PEQ_00_B2_LEN) - 1) << AUDIO_PEQ_00_B2_POS) -#define AUDIO_PEQ_00_B2_UMSK (~(((1U << AUDIO_PEQ_00_B2_LEN) - 1) << AUDIO_PEQ_00_B2_POS)) - -/* 0x20C : peq_00_a1 */ -#define AUDIO_PEQ_00_A1_OFFSET (0x20C) -#define AUDIO_PEQ_00_A1 AUDIO_PEQ_00_A1 -#define AUDIO_PEQ_00_A1_POS (0U) -#define AUDIO_PEQ_00_A1_LEN (20U) -#define AUDIO_PEQ_00_A1_MSK (((1U << AUDIO_PEQ_00_A1_LEN) - 1) << AUDIO_PEQ_00_A1_POS) -#define AUDIO_PEQ_00_A1_UMSK (~(((1U << AUDIO_PEQ_00_A1_LEN) - 1) << AUDIO_PEQ_00_A1_POS)) - -/* 0x210 : peq_00_a2 */ -#define AUDIO_PEQ_00_A2_OFFSET (0x210) -#define AUDIO_PEQ_00_A2 AUDIO_PEQ_00_A2 -#define AUDIO_PEQ_00_A2_POS (0U) -#define AUDIO_PEQ_00_A2_LEN (20U) -#define AUDIO_PEQ_00_A2_MSK (((1U << AUDIO_PEQ_00_A2_LEN) - 1) << AUDIO_PEQ_00_A2_POS) -#define AUDIO_PEQ_00_A2_UMSK (~(((1U << AUDIO_PEQ_00_A2_LEN) - 1) << AUDIO_PEQ_00_A2_POS)) - -/* 0x214 : peq_01_b0 */ -#define AUDIO_PEQ_01_B0_OFFSET (0x214) -#define AUDIO_PEQ_01_B0 AUDIO_PEQ_01_B0 -#define AUDIO_PEQ_01_B0_POS (0U) -#define AUDIO_PEQ_01_B0_LEN (20U) -#define AUDIO_PEQ_01_B0_MSK (((1U << AUDIO_PEQ_01_B0_LEN) - 1) << AUDIO_PEQ_01_B0_POS) -#define AUDIO_PEQ_01_B0_UMSK (~(((1U << AUDIO_PEQ_01_B0_LEN) - 1) << AUDIO_PEQ_01_B0_POS)) -#define AUDIO_PEQ_01_BYP AUDIO_PEQ_01_BYP -#define AUDIO_PEQ_01_BYP_POS (20U) -#define AUDIO_PEQ_01_BYP_LEN (1U) -#define AUDIO_PEQ_01_BYP_MSK (((1U << AUDIO_PEQ_01_BYP_LEN) - 1) << AUDIO_PEQ_01_BYP_POS) -#define AUDIO_PEQ_01_BYP_UMSK (~(((1U << AUDIO_PEQ_01_BYP_LEN) - 1) << AUDIO_PEQ_01_BYP_POS)) -#define AUDIO_PEQ_01_QFMT AUDIO_PEQ_01_QFMT -#define AUDIO_PEQ_01_QFMT_POS (21U) -#define AUDIO_PEQ_01_QFMT_LEN (1U) -#define AUDIO_PEQ_01_QFMT_MSK (((1U << AUDIO_PEQ_01_QFMT_LEN) - 1) << AUDIO_PEQ_01_QFMT_POS) -#define AUDIO_PEQ_01_QFMT_UMSK (~(((1U << AUDIO_PEQ_01_QFMT_LEN) - 1) << AUDIO_PEQ_01_QFMT_POS)) - -/* 0x218 : peq_01_b1 */ -#define AUDIO_PEQ_01_B1_OFFSET (0x218) -#define AUDIO_PEQ_01_B1 AUDIO_PEQ_01_B1 -#define AUDIO_PEQ_01_B1_POS (0U) -#define AUDIO_PEQ_01_B1_LEN (20U) -#define AUDIO_PEQ_01_B1_MSK (((1U << AUDIO_PEQ_01_B1_LEN) - 1) << AUDIO_PEQ_01_B1_POS) -#define AUDIO_PEQ_01_B1_UMSK (~(((1U << AUDIO_PEQ_01_B1_LEN) - 1) << AUDIO_PEQ_01_B1_POS)) - -/* 0x21C : peq_01_b2 */ -#define AUDIO_PEQ_01_B2_OFFSET (0x21C) -#define AUDIO_PEQ_01_B2 AUDIO_PEQ_01_B2 -#define AUDIO_PEQ_01_B2_POS (0U) -#define AUDIO_PEQ_01_B2_LEN (20U) -#define AUDIO_PEQ_01_B2_MSK (((1U << AUDIO_PEQ_01_B2_LEN) - 1) << AUDIO_PEQ_01_B2_POS) -#define AUDIO_PEQ_01_B2_UMSK (~(((1U << AUDIO_PEQ_01_B2_LEN) - 1) << AUDIO_PEQ_01_B2_POS)) - -/* 0x220 : peq_01_a1 */ -#define AUDIO_PEQ_01_A1_OFFSET (0x220) -#define AUDIO_PEQ_01_A1 AUDIO_PEQ_01_A1 -#define AUDIO_PEQ_01_A1_POS (0U) -#define AUDIO_PEQ_01_A1_LEN (20U) -#define AUDIO_PEQ_01_A1_MSK (((1U << AUDIO_PEQ_01_A1_LEN) - 1) << AUDIO_PEQ_01_A1_POS) -#define AUDIO_PEQ_01_A1_UMSK (~(((1U << AUDIO_PEQ_01_A1_LEN) - 1) << AUDIO_PEQ_01_A1_POS)) - -/* 0x224 : peq_01_a2 */ -#define AUDIO_PEQ_01_A2_OFFSET (0x224) -#define AUDIO_PEQ_01_A2 AUDIO_PEQ_01_A2 -#define AUDIO_PEQ_01_A2_POS (0U) -#define AUDIO_PEQ_01_A2_LEN (20U) -#define AUDIO_PEQ_01_A2_MSK (((1U << AUDIO_PEQ_01_A2_LEN) - 1) << AUDIO_PEQ_01_A2_POS) -#define AUDIO_PEQ_01_A2_UMSK (~(((1U << AUDIO_PEQ_01_A2_LEN) - 1) << AUDIO_PEQ_01_A2_POS)) - -/* 0x228 : peq_02_b0 */ -#define AUDIO_PEQ_02_B0_OFFSET (0x228) -#define AUDIO_PEQ_02_B0 AUDIO_PEQ_02_B0 -#define AUDIO_PEQ_02_B0_POS (0U) -#define AUDIO_PEQ_02_B0_LEN (20U) -#define AUDIO_PEQ_02_B0_MSK (((1U << AUDIO_PEQ_02_B0_LEN) - 1) << AUDIO_PEQ_02_B0_POS) -#define AUDIO_PEQ_02_B0_UMSK (~(((1U << AUDIO_PEQ_02_B0_LEN) - 1) << AUDIO_PEQ_02_B0_POS)) -#define AUDIO_PEQ_02_BYP AUDIO_PEQ_02_BYP -#define AUDIO_PEQ_02_BYP_POS (20U) -#define AUDIO_PEQ_02_BYP_LEN (1U) -#define AUDIO_PEQ_02_BYP_MSK (((1U << AUDIO_PEQ_02_BYP_LEN) - 1) << AUDIO_PEQ_02_BYP_POS) -#define AUDIO_PEQ_02_BYP_UMSK (~(((1U << AUDIO_PEQ_02_BYP_LEN) - 1) << AUDIO_PEQ_02_BYP_POS)) -#define AUDIO_PEQ_02_QFMT AUDIO_PEQ_02_QFMT -#define AUDIO_PEQ_02_QFMT_POS (21U) -#define AUDIO_PEQ_02_QFMT_LEN (1U) -#define AUDIO_PEQ_02_QFMT_MSK (((1U << AUDIO_PEQ_02_QFMT_LEN) - 1) << AUDIO_PEQ_02_QFMT_POS) -#define AUDIO_PEQ_02_QFMT_UMSK (~(((1U << AUDIO_PEQ_02_QFMT_LEN) - 1) << AUDIO_PEQ_02_QFMT_POS)) - -/* 0x22C : peq_02_b1 */ -#define AUDIO_PEQ_02_B1_OFFSET (0x22C) -#define AUDIO_PEQ_02_B1 AUDIO_PEQ_02_B1 -#define AUDIO_PEQ_02_B1_POS (0U) -#define AUDIO_PEQ_02_B1_LEN (20U) -#define AUDIO_PEQ_02_B1_MSK (((1U << AUDIO_PEQ_02_B1_LEN) - 1) << AUDIO_PEQ_02_B1_POS) -#define AUDIO_PEQ_02_B1_UMSK (~(((1U << AUDIO_PEQ_02_B1_LEN) - 1) << AUDIO_PEQ_02_B1_POS)) - -/* 0x230 : peq_02_b2 */ -#define AUDIO_PEQ_02_B2_OFFSET (0x230) -#define AUDIO_PEQ_02_B2 AUDIO_PEQ_02_B2 -#define AUDIO_PEQ_02_B2_POS (0U) -#define AUDIO_PEQ_02_B2_LEN (20U) -#define AUDIO_PEQ_02_B2_MSK (((1U << AUDIO_PEQ_02_B2_LEN) - 1) << AUDIO_PEQ_02_B2_POS) -#define AUDIO_PEQ_02_B2_UMSK (~(((1U << AUDIO_PEQ_02_B2_LEN) - 1) << AUDIO_PEQ_02_B2_POS)) - -/* 0x234 : peq_02_a1 */ -#define AUDIO_PEQ_02_A1_OFFSET (0x234) -#define AUDIO_PEQ_02_A1 AUDIO_PEQ_02_A1 -#define AUDIO_PEQ_02_A1_POS (0U) -#define AUDIO_PEQ_02_A1_LEN (20U) -#define AUDIO_PEQ_02_A1_MSK (((1U << AUDIO_PEQ_02_A1_LEN) - 1) << AUDIO_PEQ_02_A1_POS) -#define AUDIO_PEQ_02_A1_UMSK (~(((1U << AUDIO_PEQ_02_A1_LEN) - 1) << AUDIO_PEQ_02_A1_POS)) - -/* 0x238 : peq_02_a2 */ -#define AUDIO_PEQ_02_A2_OFFSET (0x238) -#define AUDIO_PEQ_02_A2 AUDIO_PEQ_02_A2 -#define AUDIO_PEQ_02_A2_POS (0U) -#define AUDIO_PEQ_02_A2_LEN (20U) -#define AUDIO_PEQ_02_A2_MSK (((1U << AUDIO_PEQ_02_A2_LEN) - 1) << AUDIO_PEQ_02_A2_POS) -#define AUDIO_PEQ_02_A2_UMSK (~(((1U << AUDIO_PEQ_02_A2_LEN) - 1) << AUDIO_PEQ_02_A2_POS)) - -/* 0x23C : peq_03_b0 */ -#define AUDIO_PEQ_03_B0_OFFSET (0x23C) -#define AUDIO_PEQ_03_B0 AUDIO_PEQ_03_B0 -#define AUDIO_PEQ_03_B0_POS (0U) -#define AUDIO_PEQ_03_B0_LEN (20U) -#define AUDIO_PEQ_03_B0_MSK (((1U << AUDIO_PEQ_03_B0_LEN) - 1) << AUDIO_PEQ_03_B0_POS) -#define AUDIO_PEQ_03_B0_UMSK (~(((1U << AUDIO_PEQ_03_B0_LEN) - 1) << AUDIO_PEQ_03_B0_POS)) -#define AUDIO_PEQ_03_BYP AUDIO_PEQ_03_BYP -#define AUDIO_PEQ_03_BYP_POS (20U) -#define AUDIO_PEQ_03_BYP_LEN (1U) -#define AUDIO_PEQ_03_BYP_MSK (((1U << AUDIO_PEQ_03_BYP_LEN) - 1) << AUDIO_PEQ_03_BYP_POS) -#define AUDIO_PEQ_03_BYP_UMSK (~(((1U << AUDIO_PEQ_03_BYP_LEN) - 1) << AUDIO_PEQ_03_BYP_POS)) -#define AUDIO_PEQ_03_QFMT AUDIO_PEQ_03_QFMT -#define AUDIO_PEQ_03_QFMT_POS (21U) -#define AUDIO_PEQ_03_QFMT_LEN (1U) -#define AUDIO_PEQ_03_QFMT_MSK (((1U << AUDIO_PEQ_03_QFMT_LEN) - 1) << AUDIO_PEQ_03_QFMT_POS) -#define AUDIO_PEQ_03_QFMT_UMSK (~(((1U << AUDIO_PEQ_03_QFMT_LEN) - 1) << AUDIO_PEQ_03_QFMT_POS)) - -/* 0x240 : peq_03_b1 */ -#define AUDIO_PEQ_03_B1_OFFSET (0x240) -#define AUDIO_PEQ_03_B1 AUDIO_PEQ_03_B1 -#define AUDIO_PEQ_03_B1_POS (0U) -#define AUDIO_PEQ_03_B1_LEN (20U) -#define AUDIO_PEQ_03_B1_MSK (((1U << AUDIO_PEQ_03_B1_LEN) - 1) << AUDIO_PEQ_03_B1_POS) -#define AUDIO_PEQ_03_B1_UMSK (~(((1U << AUDIO_PEQ_03_B1_LEN) - 1) << AUDIO_PEQ_03_B1_POS)) - -/* 0x244 : peq_03_b2 */ -#define AUDIO_PEQ_03_B2_OFFSET (0x244) -#define AUDIO_PEQ_03_B2 AUDIO_PEQ_03_B2 -#define AUDIO_PEQ_03_B2_POS (0U) -#define AUDIO_PEQ_03_B2_LEN (20U) -#define AUDIO_PEQ_03_B2_MSK (((1U << AUDIO_PEQ_03_B2_LEN) - 1) << AUDIO_PEQ_03_B2_POS) -#define AUDIO_PEQ_03_B2_UMSK (~(((1U << AUDIO_PEQ_03_B2_LEN) - 1) << AUDIO_PEQ_03_B2_POS)) - -/* 0x248 : peq_03_a1 */ -#define AUDIO_PEQ_03_A1_OFFSET (0x248) -#define AUDIO_PEQ_03_A1 AUDIO_PEQ_03_A1 -#define AUDIO_PEQ_03_A1_POS (0U) -#define AUDIO_PEQ_03_A1_LEN (20U) -#define AUDIO_PEQ_03_A1_MSK (((1U << AUDIO_PEQ_03_A1_LEN) - 1) << AUDIO_PEQ_03_A1_POS) -#define AUDIO_PEQ_03_A1_UMSK (~(((1U << AUDIO_PEQ_03_A1_LEN) - 1) << AUDIO_PEQ_03_A1_POS)) - -/* 0x24C : peq_03_a2 */ -#define AUDIO_PEQ_03_A2_OFFSET (0x24C) -#define AUDIO_PEQ_03_A2 AUDIO_PEQ_03_A2 -#define AUDIO_PEQ_03_A2_POS (0U) -#define AUDIO_PEQ_03_A2_LEN (20U) -#define AUDIO_PEQ_03_A2_MSK (((1U << AUDIO_PEQ_03_A2_LEN) - 1) << AUDIO_PEQ_03_A2_POS) -#define AUDIO_PEQ_03_A2_UMSK (~(((1U << AUDIO_PEQ_03_A2_LEN) - 1) << AUDIO_PEQ_03_A2_POS)) - -/* 0x250 : peq_04_b0 */ -#define AUDIO_PEQ_04_B0_OFFSET (0x250) -#define AUDIO_PEQ_04_B0 AUDIO_PEQ_04_B0 -#define AUDIO_PEQ_04_B0_POS (0U) -#define AUDIO_PEQ_04_B0_LEN (20U) -#define AUDIO_PEQ_04_B0_MSK (((1U << AUDIO_PEQ_04_B0_LEN) - 1) << AUDIO_PEQ_04_B0_POS) -#define AUDIO_PEQ_04_B0_UMSK (~(((1U << AUDIO_PEQ_04_B0_LEN) - 1) << AUDIO_PEQ_04_B0_POS)) -#define AUDIO_PEQ_04_BYP AUDIO_PEQ_04_BYP -#define AUDIO_PEQ_04_BYP_POS (20U) -#define AUDIO_PEQ_04_BYP_LEN (1U) -#define AUDIO_PEQ_04_BYP_MSK (((1U << AUDIO_PEQ_04_BYP_LEN) - 1) << AUDIO_PEQ_04_BYP_POS) -#define AUDIO_PEQ_04_BYP_UMSK (~(((1U << AUDIO_PEQ_04_BYP_LEN) - 1) << AUDIO_PEQ_04_BYP_POS)) -#define AUDIO_PEQ_04_QFMT AUDIO_PEQ_04_QFMT -#define AUDIO_PEQ_04_QFMT_POS (21U) -#define AUDIO_PEQ_04_QFMT_LEN (1U) -#define AUDIO_PEQ_04_QFMT_MSK (((1U << AUDIO_PEQ_04_QFMT_LEN) - 1) << AUDIO_PEQ_04_QFMT_POS) -#define AUDIO_PEQ_04_QFMT_UMSK (~(((1U << AUDIO_PEQ_04_QFMT_LEN) - 1) << AUDIO_PEQ_04_QFMT_POS)) - -/* 0x254 : peq_04_b1 */ -#define AUDIO_PEQ_04_B1_OFFSET (0x254) -#define AUDIO_PEQ_04_B1 AUDIO_PEQ_04_B1 -#define AUDIO_PEQ_04_B1_POS (0U) -#define AUDIO_PEQ_04_B1_LEN (20U) -#define AUDIO_PEQ_04_B1_MSK (((1U << AUDIO_PEQ_04_B1_LEN) - 1) << AUDIO_PEQ_04_B1_POS) -#define AUDIO_PEQ_04_B1_UMSK (~(((1U << AUDIO_PEQ_04_B1_LEN) - 1) << AUDIO_PEQ_04_B1_POS)) - -/* 0x258 : peq_04_b2 */ -#define AUDIO_PEQ_04_B2_OFFSET (0x258) -#define AUDIO_PEQ_04_B2 AUDIO_PEQ_04_B2 -#define AUDIO_PEQ_04_B2_POS (0U) -#define AUDIO_PEQ_04_B2_LEN (20U) -#define AUDIO_PEQ_04_B2_MSK (((1U << AUDIO_PEQ_04_B2_LEN) - 1) << AUDIO_PEQ_04_B2_POS) -#define AUDIO_PEQ_04_B2_UMSK (~(((1U << AUDIO_PEQ_04_B2_LEN) - 1) << AUDIO_PEQ_04_B2_POS)) - -/* 0x25C : peq_04_a1 */ -#define AUDIO_PEQ_04_A1_OFFSET (0x25C) -#define AUDIO_PEQ_04_A1 AUDIO_PEQ_04_A1 -#define AUDIO_PEQ_04_A1_POS (0U) -#define AUDIO_PEQ_04_A1_LEN (20U) -#define AUDIO_PEQ_04_A1_MSK (((1U << AUDIO_PEQ_04_A1_LEN) - 1) << AUDIO_PEQ_04_A1_POS) -#define AUDIO_PEQ_04_A1_UMSK (~(((1U << AUDIO_PEQ_04_A1_LEN) - 1) << AUDIO_PEQ_04_A1_POS)) - -/* 0x260 : peq_04_a2 */ -#define AUDIO_PEQ_04_A2_OFFSET (0x260) -#define AUDIO_PEQ_04_A2 AUDIO_PEQ_04_A2 -#define AUDIO_PEQ_04_A2_POS (0U) -#define AUDIO_PEQ_04_A2_LEN (20U) -#define AUDIO_PEQ_04_A2_MSK (((1U << AUDIO_PEQ_04_A2_LEN) - 1) << AUDIO_PEQ_04_A2_POS) -#define AUDIO_PEQ_04_A2_UMSK (~(((1U << AUDIO_PEQ_04_A2_LEN) - 1) << AUDIO_PEQ_04_A2_POS)) - -/* 0x264 : peq_05_b0 */ -#define AUDIO_PEQ_05_B0_OFFSET (0x264) -#define AUDIO_PEQ_05_B0 AUDIO_PEQ_05_B0 -#define AUDIO_PEQ_05_B0_POS (0U) -#define AUDIO_PEQ_05_B0_LEN (20U) -#define AUDIO_PEQ_05_B0_MSK (((1U << AUDIO_PEQ_05_B0_LEN) - 1) << AUDIO_PEQ_05_B0_POS) -#define AUDIO_PEQ_05_B0_UMSK (~(((1U << AUDIO_PEQ_05_B0_LEN) - 1) << AUDIO_PEQ_05_B0_POS)) -#define AUDIO_PEQ_05_BYP AUDIO_PEQ_05_BYP -#define AUDIO_PEQ_05_BYP_POS (20U) -#define AUDIO_PEQ_05_BYP_LEN (1U) -#define AUDIO_PEQ_05_BYP_MSK (((1U << AUDIO_PEQ_05_BYP_LEN) - 1) << AUDIO_PEQ_05_BYP_POS) -#define AUDIO_PEQ_05_BYP_UMSK (~(((1U << AUDIO_PEQ_05_BYP_LEN) - 1) << AUDIO_PEQ_05_BYP_POS)) -#define AUDIO_PEQ_05_QFMT AUDIO_PEQ_05_QFMT -#define AUDIO_PEQ_05_QFMT_POS (21U) -#define AUDIO_PEQ_05_QFMT_LEN (1U) -#define AUDIO_PEQ_05_QFMT_MSK (((1U << AUDIO_PEQ_05_QFMT_LEN) - 1) << AUDIO_PEQ_05_QFMT_POS) -#define AUDIO_PEQ_05_QFMT_UMSK (~(((1U << AUDIO_PEQ_05_QFMT_LEN) - 1) << AUDIO_PEQ_05_QFMT_POS)) - -/* 0x268 : peq_05_b1 */ -#define AUDIO_PEQ_05_B1_OFFSET (0x268) -#define AUDIO_PEQ_05_B1 AUDIO_PEQ_05_B1 -#define AUDIO_PEQ_05_B1_POS (0U) -#define AUDIO_PEQ_05_B1_LEN (20U) -#define AUDIO_PEQ_05_B1_MSK (((1U << AUDIO_PEQ_05_B1_LEN) - 1) << AUDIO_PEQ_05_B1_POS) -#define AUDIO_PEQ_05_B1_UMSK (~(((1U << AUDIO_PEQ_05_B1_LEN) - 1) << AUDIO_PEQ_05_B1_POS)) - -/* 0x26C : peq_05_b2 */ -#define AUDIO_PEQ_05_B2_OFFSET (0x26C) -#define AUDIO_PEQ_05_B2 AUDIO_PEQ_05_B2 -#define AUDIO_PEQ_05_B2_POS (0U) -#define AUDIO_PEQ_05_B2_LEN (20U) -#define AUDIO_PEQ_05_B2_MSK (((1U << AUDIO_PEQ_05_B2_LEN) - 1) << AUDIO_PEQ_05_B2_POS) -#define AUDIO_PEQ_05_B2_UMSK (~(((1U << AUDIO_PEQ_05_B2_LEN) - 1) << AUDIO_PEQ_05_B2_POS)) - -/* 0x270 : peq_05_a1 */ -#define AUDIO_PEQ_05_A1_OFFSET (0x270) -#define AUDIO_PEQ_05_A1 AUDIO_PEQ_05_A1 -#define AUDIO_PEQ_05_A1_POS (0U) -#define AUDIO_PEQ_05_A1_LEN (20U) -#define AUDIO_PEQ_05_A1_MSK (((1U << AUDIO_PEQ_05_A1_LEN) - 1) << AUDIO_PEQ_05_A1_POS) -#define AUDIO_PEQ_05_A1_UMSK (~(((1U << AUDIO_PEQ_05_A1_LEN) - 1) << AUDIO_PEQ_05_A1_POS)) - -/* 0x274 : peq_05_a2 */ -#define AUDIO_PEQ_05_A2_OFFSET (0x274) -#define AUDIO_PEQ_05_A2 AUDIO_PEQ_05_A2 -#define AUDIO_PEQ_05_A2_POS (0U) -#define AUDIO_PEQ_05_A2_LEN (20U) -#define AUDIO_PEQ_05_A2_MSK (((1U << AUDIO_PEQ_05_A2_LEN) - 1) << AUDIO_PEQ_05_A2_POS) -#define AUDIO_PEQ_05_A2_UMSK (~(((1U << AUDIO_PEQ_05_A2_LEN) - 1) << AUDIO_PEQ_05_A2_POS)) - -/* 0x278 : peq_06_b0 */ -#define AUDIO_PEQ_06_B0_OFFSET (0x278) -#define AUDIO_PEQ_06_B0 AUDIO_PEQ_06_B0 -#define AUDIO_PEQ_06_B0_POS (0U) -#define AUDIO_PEQ_06_B0_LEN (20U) -#define AUDIO_PEQ_06_B0_MSK (((1U << AUDIO_PEQ_06_B0_LEN) - 1) << AUDIO_PEQ_06_B0_POS) -#define AUDIO_PEQ_06_B0_UMSK (~(((1U << AUDIO_PEQ_06_B0_LEN) - 1) << AUDIO_PEQ_06_B0_POS)) -#define AUDIO_PEQ_06_BYP AUDIO_PEQ_06_BYP -#define AUDIO_PEQ_06_BYP_POS (20U) -#define AUDIO_PEQ_06_BYP_LEN (1U) -#define AUDIO_PEQ_06_BYP_MSK (((1U << AUDIO_PEQ_06_BYP_LEN) - 1) << AUDIO_PEQ_06_BYP_POS) -#define AUDIO_PEQ_06_BYP_UMSK (~(((1U << AUDIO_PEQ_06_BYP_LEN) - 1) << AUDIO_PEQ_06_BYP_POS)) -#define AUDIO_PEQ_06_QFMT AUDIO_PEQ_06_QFMT -#define AUDIO_PEQ_06_QFMT_POS (21U) -#define AUDIO_PEQ_06_QFMT_LEN (1U) -#define AUDIO_PEQ_06_QFMT_MSK (((1U << AUDIO_PEQ_06_QFMT_LEN) - 1) << AUDIO_PEQ_06_QFMT_POS) -#define AUDIO_PEQ_06_QFMT_UMSK (~(((1U << AUDIO_PEQ_06_QFMT_LEN) - 1) << AUDIO_PEQ_06_QFMT_POS)) - -/* 0x27C : peq_06_b1 */ -#define AUDIO_PEQ_06_B1_OFFSET (0x27C) -#define AUDIO_PEQ_06_B1 AUDIO_PEQ_06_B1 -#define AUDIO_PEQ_06_B1_POS (0U) -#define AUDIO_PEQ_06_B1_LEN (20U) -#define AUDIO_PEQ_06_B1_MSK (((1U << AUDIO_PEQ_06_B1_LEN) - 1) << AUDIO_PEQ_06_B1_POS) -#define AUDIO_PEQ_06_B1_UMSK (~(((1U << AUDIO_PEQ_06_B1_LEN) - 1) << AUDIO_PEQ_06_B1_POS)) - -/* 0x280 : peq_06_b2 */ -#define AUDIO_PEQ_06_B2_OFFSET (0x280) -#define AUDIO_PEQ_06_B2 AUDIO_PEQ_06_B2 -#define AUDIO_PEQ_06_B2_POS (0U) -#define AUDIO_PEQ_06_B2_LEN (20U) -#define AUDIO_PEQ_06_B2_MSK (((1U << AUDIO_PEQ_06_B2_LEN) - 1) << AUDIO_PEQ_06_B2_POS) -#define AUDIO_PEQ_06_B2_UMSK (~(((1U << AUDIO_PEQ_06_B2_LEN) - 1) << AUDIO_PEQ_06_B2_POS)) - -/* 0x284 : peq_06_a1 */ -#define AUDIO_PEQ_06_A1_OFFSET (0x284) -#define AUDIO_PEQ_06_A1 AUDIO_PEQ_06_A1 -#define AUDIO_PEQ_06_A1_POS (0U) -#define AUDIO_PEQ_06_A1_LEN (20U) -#define AUDIO_PEQ_06_A1_MSK (((1U << AUDIO_PEQ_06_A1_LEN) - 1) << AUDIO_PEQ_06_A1_POS) -#define AUDIO_PEQ_06_A1_UMSK (~(((1U << AUDIO_PEQ_06_A1_LEN) - 1) << AUDIO_PEQ_06_A1_POS)) - -/* 0x288 : peq_06_a2 */ -#define AUDIO_PEQ_06_A2_OFFSET (0x288) -#define AUDIO_PEQ_06_A2 AUDIO_PEQ_06_A2 -#define AUDIO_PEQ_06_A2_POS (0U) -#define AUDIO_PEQ_06_A2_LEN (20U) -#define AUDIO_PEQ_06_A2_MSK (((1U << AUDIO_PEQ_06_A2_LEN) - 1) << AUDIO_PEQ_06_A2_POS) -#define AUDIO_PEQ_06_A2_UMSK (~(((1U << AUDIO_PEQ_06_A2_LEN) - 1) << AUDIO_PEQ_06_A2_POS)) - -/* 0x28C : peq_07_b0 */ -#define AUDIO_PEQ_07_B0_OFFSET (0x28C) -#define AUDIO_PEQ_07_B0 AUDIO_PEQ_07_B0 -#define AUDIO_PEQ_07_B0_POS (0U) -#define AUDIO_PEQ_07_B0_LEN (20U) -#define AUDIO_PEQ_07_B0_MSK (((1U << AUDIO_PEQ_07_B0_LEN) - 1) << AUDIO_PEQ_07_B0_POS) -#define AUDIO_PEQ_07_B0_UMSK (~(((1U << AUDIO_PEQ_07_B0_LEN) - 1) << AUDIO_PEQ_07_B0_POS)) -#define AUDIO_PEQ_07_BYP AUDIO_PEQ_07_BYP -#define AUDIO_PEQ_07_BYP_POS (20U) -#define AUDIO_PEQ_07_BYP_LEN (1U) -#define AUDIO_PEQ_07_BYP_MSK (((1U << AUDIO_PEQ_07_BYP_LEN) - 1) << AUDIO_PEQ_07_BYP_POS) -#define AUDIO_PEQ_07_BYP_UMSK (~(((1U << AUDIO_PEQ_07_BYP_LEN) - 1) << AUDIO_PEQ_07_BYP_POS)) -#define AUDIO_PEQ_07_QFMT AUDIO_PEQ_07_QFMT -#define AUDIO_PEQ_07_QFMT_POS (21U) -#define AUDIO_PEQ_07_QFMT_LEN (1U) -#define AUDIO_PEQ_07_QFMT_MSK (((1U << AUDIO_PEQ_07_QFMT_LEN) - 1) << AUDIO_PEQ_07_QFMT_POS) -#define AUDIO_PEQ_07_QFMT_UMSK (~(((1U << AUDIO_PEQ_07_QFMT_LEN) - 1) << AUDIO_PEQ_07_QFMT_POS)) - -/* 0x290 : peq_07_b1 */ -#define AUDIO_PEQ_07_B1_OFFSET (0x290) -#define AUDIO_PEQ_07_B1 AUDIO_PEQ_07_B1 -#define AUDIO_PEQ_07_B1_POS (0U) -#define AUDIO_PEQ_07_B1_LEN (20U) -#define AUDIO_PEQ_07_B1_MSK (((1U << AUDIO_PEQ_07_B1_LEN) - 1) << AUDIO_PEQ_07_B1_POS) -#define AUDIO_PEQ_07_B1_UMSK (~(((1U << AUDIO_PEQ_07_B1_LEN) - 1) << AUDIO_PEQ_07_B1_POS)) - -/* 0x294 : peq_07_b2 */ -#define AUDIO_PEQ_07_B2_OFFSET (0x294) -#define AUDIO_PEQ_07_B2 AUDIO_PEQ_07_B2 -#define AUDIO_PEQ_07_B2_POS (0U) -#define AUDIO_PEQ_07_B2_LEN (20U) -#define AUDIO_PEQ_07_B2_MSK (((1U << AUDIO_PEQ_07_B2_LEN) - 1) << AUDIO_PEQ_07_B2_POS) -#define AUDIO_PEQ_07_B2_UMSK (~(((1U << AUDIO_PEQ_07_B2_LEN) - 1) << AUDIO_PEQ_07_B2_POS)) - -/* 0x298 : peq_07_a1 */ -#define AUDIO_PEQ_07_A1_OFFSET (0x298) -#define AUDIO_PEQ_07_A1 AUDIO_PEQ_07_A1 -#define AUDIO_PEQ_07_A1_POS (0U) -#define AUDIO_PEQ_07_A1_LEN (20U) -#define AUDIO_PEQ_07_A1_MSK (((1U << AUDIO_PEQ_07_A1_LEN) - 1) << AUDIO_PEQ_07_A1_POS) -#define AUDIO_PEQ_07_A1_UMSK (~(((1U << AUDIO_PEQ_07_A1_LEN) - 1) << AUDIO_PEQ_07_A1_POS)) - -/* 0x29C : peq_07_a2 */ -#define AUDIO_PEQ_07_A2_OFFSET (0x29C) -#define AUDIO_PEQ_07_A2 AUDIO_PEQ_07_A2 -#define AUDIO_PEQ_07_A2_POS (0U) -#define AUDIO_PEQ_07_A2_LEN (20U) -#define AUDIO_PEQ_07_A2_MSK (((1U << AUDIO_PEQ_07_A2_LEN) - 1) << AUDIO_PEQ_07_A2_POS) -#define AUDIO_PEQ_07_A2_UMSK (~(((1U << AUDIO_PEQ_07_A2_LEN) - 1) << AUDIO_PEQ_07_A2_POS)) - -/* 0x2A0 : peq_08_b0 */ -#define AUDIO_PEQ_08_B0_OFFSET (0x2A0) -#define AUDIO_PEQ_08_B0 AUDIO_PEQ_08_B0 -#define AUDIO_PEQ_08_B0_POS (0U) -#define AUDIO_PEQ_08_B0_LEN (20U) -#define AUDIO_PEQ_08_B0_MSK (((1U << AUDIO_PEQ_08_B0_LEN) - 1) << AUDIO_PEQ_08_B0_POS) -#define AUDIO_PEQ_08_B0_UMSK (~(((1U << AUDIO_PEQ_08_B0_LEN) - 1) << AUDIO_PEQ_08_B0_POS)) -#define AUDIO_PEQ_08_BYP AUDIO_PEQ_08_BYP -#define AUDIO_PEQ_08_BYP_POS (20U) -#define AUDIO_PEQ_08_BYP_LEN (1U) -#define AUDIO_PEQ_08_BYP_MSK (((1U << AUDIO_PEQ_08_BYP_LEN) - 1) << AUDIO_PEQ_08_BYP_POS) -#define AUDIO_PEQ_08_BYP_UMSK (~(((1U << AUDIO_PEQ_08_BYP_LEN) - 1) << AUDIO_PEQ_08_BYP_POS)) -#define AUDIO_PEQ_08_QFMT AUDIO_PEQ_08_QFMT -#define AUDIO_PEQ_08_QFMT_POS (21U) -#define AUDIO_PEQ_08_QFMT_LEN (1U) -#define AUDIO_PEQ_08_QFMT_MSK (((1U << AUDIO_PEQ_08_QFMT_LEN) - 1) << AUDIO_PEQ_08_QFMT_POS) -#define AUDIO_PEQ_08_QFMT_UMSK (~(((1U << AUDIO_PEQ_08_QFMT_LEN) - 1) << AUDIO_PEQ_08_QFMT_POS)) - -/* 0x2A4 : peq_08_b1 */ -#define AUDIO_PEQ_08_B1_OFFSET (0x2A4) -#define AUDIO_PEQ_08_B1 AUDIO_PEQ_08_B1 -#define AUDIO_PEQ_08_B1_POS (0U) -#define AUDIO_PEQ_08_B1_LEN (20U) -#define AUDIO_PEQ_08_B1_MSK (((1U << AUDIO_PEQ_08_B1_LEN) - 1) << AUDIO_PEQ_08_B1_POS) -#define AUDIO_PEQ_08_B1_UMSK (~(((1U << AUDIO_PEQ_08_B1_LEN) - 1) << AUDIO_PEQ_08_B1_POS)) - -/* 0x2A8 : peq_08_b2 */ -#define AUDIO_PEQ_08_B2_OFFSET (0x2A8) -#define AUDIO_PEQ_08_B2 AUDIO_PEQ_08_B2 -#define AUDIO_PEQ_08_B2_POS (0U) -#define AUDIO_PEQ_08_B2_LEN (20U) -#define AUDIO_PEQ_08_B2_MSK (((1U << AUDIO_PEQ_08_B2_LEN) - 1) << AUDIO_PEQ_08_B2_POS) -#define AUDIO_PEQ_08_B2_UMSK (~(((1U << AUDIO_PEQ_08_B2_LEN) - 1) << AUDIO_PEQ_08_B2_POS)) - -/* 0x2AC : peq_08_a1 */ -#define AUDIO_PEQ_08_A1_OFFSET (0x2AC) -#define AUDIO_PEQ_08_A1 AUDIO_PEQ_08_A1 -#define AUDIO_PEQ_08_A1_POS (0U) -#define AUDIO_PEQ_08_A1_LEN (20U) -#define AUDIO_PEQ_08_A1_MSK (((1U << AUDIO_PEQ_08_A1_LEN) - 1) << AUDIO_PEQ_08_A1_POS) -#define AUDIO_PEQ_08_A1_UMSK (~(((1U << AUDIO_PEQ_08_A1_LEN) - 1) << AUDIO_PEQ_08_A1_POS)) - -/* 0x2B0 : peq_08_a2 */ -#define AUDIO_PEQ_08_A2_OFFSET (0x2B0) -#define AUDIO_PEQ_08_A2 AUDIO_PEQ_08_A2 -#define AUDIO_PEQ_08_A2_POS (0U) -#define AUDIO_PEQ_08_A2_LEN (20U) -#define AUDIO_PEQ_08_A2_MSK (((1U << AUDIO_PEQ_08_A2_LEN) - 1) << AUDIO_PEQ_08_A2_POS) -#define AUDIO_PEQ_08_A2_UMSK (~(((1U << AUDIO_PEQ_08_A2_LEN) - 1) << AUDIO_PEQ_08_A2_POS)) - -/* 0x2B4 : peq_09_b0 */ -#define AUDIO_PEQ_09_B0_OFFSET (0x2B4) -#define AUDIO_PEQ_09_B0 AUDIO_PEQ_09_B0 -#define AUDIO_PEQ_09_B0_POS (0U) -#define AUDIO_PEQ_09_B0_LEN (20U) -#define AUDIO_PEQ_09_B0_MSK (((1U << AUDIO_PEQ_09_B0_LEN) - 1) << AUDIO_PEQ_09_B0_POS) -#define AUDIO_PEQ_09_B0_UMSK (~(((1U << AUDIO_PEQ_09_B0_LEN) - 1) << AUDIO_PEQ_09_B0_POS)) -#define AUDIO_PEQ_09_BYP AUDIO_PEQ_09_BYP -#define AUDIO_PEQ_09_BYP_POS (20U) -#define AUDIO_PEQ_09_BYP_LEN (1U) -#define AUDIO_PEQ_09_BYP_MSK (((1U << AUDIO_PEQ_09_BYP_LEN) - 1) << AUDIO_PEQ_09_BYP_POS) -#define AUDIO_PEQ_09_BYP_UMSK (~(((1U << AUDIO_PEQ_09_BYP_LEN) - 1) << AUDIO_PEQ_09_BYP_POS)) -#define AUDIO_PEQ_09_QFMT AUDIO_PEQ_09_QFMT -#define AUDIO_PEQ_09_QFMT_POS (21U) -#define AUDIO_PEQ_09_QFMT_LEN (1U) -#define AUDIO_PEQ_09_QFMT_MSK (((1U << AUDIO_PEQ_09_QFMT_LEN) - 1) << AUDIO_PEQ_09_QFMT_POS) -#define AUDIO_PEQ_09_QFMT_UMSK (~(((1U << AUDIO_PEQ_09_QFMT_LEN) - 1) << AUDIO_PEQ_09_QFMT_POS)) - -/* 0x2B8 : peq_09_b1 */ -#define AUDIO_PEQ_09_B1_OFFSET (0x2B8) -#define AUDIO_PEQ_09_B1 AUDIO_PEQ_09_B1 -#define AUDIO_PEQ_09_B1_POS (0U) -#define AUDIO_PEQ_09_B1_LEN (20U) -#define AUDIO_PEQ_09_B1_MSK (((1U << AUDIO_PEQ_09_B1_LEN) - 1) << AUDIO_PEQ_09_B1_POS) -#define AUDIO_PEQ_09_B1_UMSK (~(((1U << AUDIO_PEQ_09_B1_LEN) - 1) << AUDIO_PEQ_09_B1_POS)) - -/* 0x2BC : peq_09_b2 */ -#define AUDIO_PEQ_09_B2_OFFSET (0x2BC) -#define AUDIO_PEQ_09_B2 AUDIO_PEQ_09_B2 -#define AUDIO_PEQ_09_B2_POS (0U) -#define AUDIO_PEQ_09_B2_LEN (20U) -#define AUDIO_PEQ_09_B2_MSK (((1U << AUDIO_PEQ_09_B2_LEN) - 1) << AUDIO_PEQ_09_B2_POS) -#define AUDIO_PEQ_09_B2_UMSK (~(((1U << AUDIO_PEQ_09_B2_LEN) - 1) << AUDIO_PEQ_09_B2_POS)) - -/* 0x2C0 : peq_09_a1 */ -#define AUDIO_PEQ_09_A1_OFFSET (0x2C0) -#define AUDIO_PEQ_09_A1 AUDIO_PEQ_09_A1 -#define AUDIO_PEQ_09_A1_POS (0U) -#define AUDIO_PEQ_09_A1_LEN (20U) -#define AUDIO_PEQ_09_A1_MSK (((1U << AUDIO_PEQ_09_A1_LEN) - 1) << AUDIO_PEQ_09_A1_POS) -#define AUDIO_PEQ_09_A1_UMSK (~(((1U << AUDIO_PEQ_09_A1_LEN) - 1) << AUDIO_PEQ_09_A1_POS)) - -/* 0x2C4 : peq_09_a2 */ -#define AUDIO_PEQ_09_A2_OFFSET (0x2C4) -#define AUDIO_PEQ_09_A2 AUDIO_PEQ_09_A2 -#define AUDIO_PEQ_09_A2_POS (0U) -#define AUDIO_PEQ_09_A2_LEN (20U) -#define AUDIO_PEQ_09_A2_MSK (((1U << AUDIO_PEQ_09_A2_LEN) - 1) << AUDIO_PEQ_09_A2_POS) -#define AUDIO_PEQ_09_A2_UMSK (~(((1U << AUDIO_PEQ_09_A2_LEN) - 1) << AUDIO_PEQ_09_A2_POS)) - -/* 0x2C8 : peq_10_b0 */ -#define AUDIO_PEQ_10_B0_OFFSET (0x2C8) -#define AUDIO_PEQ_10_B0 AUDIO_PEQ_10_B0 -#define AUDIO_PEQ_10_B0_POS (0U) -#define AUDIO_PEQ_10_B0_LEN (20U) -#define AUDIO_PEQ_10_B0_MSK (((1U << AUDIO_PEQ_10_B0_LEN) - 1) << AUDIO_PEQ_10_B0_POS) -#define AUDIO_PEQ_10_B0_UMSK (~(((1U << AUDIO_PEQ_10_B0_LEN) - 1) << AUDIO_PEQ_10_B0_POS)) -#define AUDIO_PEQ_10_BYP AUDIO_PEQ_10_BYP -#define AUDIO_PEQ_10_BYP_POS (20U) -#define AUDIO_PEQ_10_BYP_LEN (1U) -#define AUDIO_PEQ_10_BYP_MSK (((1U << AUDIO_PEQ_10_BYP_LEN) - 1) << AUDIO_PEQ_10_BYP_POS) -#define AUDIO_PEQ_10_BYP_UMSK (~(((1U << AUDIO_PEQ_10_BYP_LEN) - 1) << AUDIO_PEQ_10_BYP_POS)) -#define AUDIO_PEQ_10_QFMT AUDIO_PEQ_10_QFMT -#define AUDIO_PEQ_10_QFMT_POS (21U) -#define AUDIO_PEQ_10_QFMT_LEN (1U) -#define AUDIO_PEQ_10_QFMT_MSK (((1U << AUDIO_PEQ_10_QFMT_LEN) - 1) << AUDIO_PEQ_10_QFMT_POS) -#define AUDIO_PEQ_10_QFMT_UMSK (~(((1U << AUDIO_PEQ_10_QFMT_LEN) - 1) << AUDIO_PEQ_10_QFMT_POS)) - -/* 0x2CC : peq_10_b1 */ -#define AUDIO_PEQ_10_B1_OFFSET (0x2CC) -#define AUDIO_PEQ_10_B1 AUDIO_PEQ_10_B1 -#define AUDIO_PEQ_10_B1_POS (0U) -#define AUDIO_PEQ_10_B1_LEN (20U) -#define AUDIO_PEQ_10_B1_MSK (((1U << AUDIO_PEQ_10_B1_LEN) - 1) << AUDIO_PEQ_10_B1_POS) -#define AUDIO_PEQ_10_B1_UMSK (~(((1U << AUDIO_PEQ_10_B1_LEN) - 1) << AUDIO_PEQ_10_B1_POS)) - -/* 0x2D0 : peq_10_b2 */ -#define AUDIO_PEQ_10_B2_OFFSET (0x2D0) -#define AUDIO_PEQ_10_B2 AUDIO_PEQ_10_B2 -#define AUDIO_PEQ_10_B2_POS (0U) -#define AUDIO_PEQ_10_B2_LEN (20U) -#define AUDIO_PEQ_10_B2_MSK (((1U << AUDIO_PEQ_10_B2_LEN) - 1) << AUDIO_PEQ_10_B2_POS) -#define AUDIO_PEQ_10_B2_UMSK (~(((1U << AUDIO_PEQ_10_B2_LEN) - 1) << AUDIO_PEQ_10_B2_POS)) - -/* 0x2D4 : peq_10_a1 */ -#define AUDIO_PEQ_10_A1_OFFSET (0x2D4) -#define AUDIO_PEQ_10_A1 AUDIO_PEQ_10_A1 -#define AUDIO_PEQ_10_A1_POS (0U) -#define AUDIO_PEQ_10_A1_LEN (20U) -#define AUDIO_PEQ_10_A1_MSK (((1U << AUDIO_PEQ_10_A1_LEN) - 1) << AUDIO_PEQ_10_A1_POS) -#define AUDIO_PEQ_10_A1_UMSK (~(((1U << AUDIO_PEQ_10_A1_LEN) - 1) << AUDIO_PEQ_10_A1_POS)) - -/* 0x2D8 : peq_10_a2 */ -#define AUDIO_PEQ_10_A2_OFFSET (0x2D8) -#define AUDIO_PEQ_10_A2 AUDIO_PEQ_10_A2 -#define AUDIO_PEQ_10_A2_POS (0U) -#define AUDIO_PEQ_10_A2_LEN (20U) -#define AUDIO_PEQ_10_A2_MSK (((1U << AUDIO_PEQ_10_A2_LEN) - 1) << AUDIO_PEQ_10_A2_POS) -#define AUDIO_PEQ_10_A2_UMSK (~(((1U << AUDIO_PEQ_10_A2_LEN) - 1) << AUDIO_PEQ_10_A2_POS)) - -/* 0x2DC : peq_11_b0 */ -#define AUDIO_PEQ_11_B0_OFFSET (0x2DC) -#define AUDIO_PEQ_11_B0 AUDIO_PEQ_11_B0 -#define AUDIO_PEQ_11_B0_POS (0U) -#define AUDIO_PEQ_11_B0_LEN (20U) -#define AUDIO_PEQ_11_B0_MSK (((1U << AUDIO_PEQ_11_B0_LEN) - 1) << AUDIO_PEQ_11_B0_POS) -#define AUDIO_PEQ_11_B0_UMSK (~(((1U << AUDIO_PEQ_11_B0_LEN) - 1) << AUDIO_PEQ_11_B0_POS)) -#define AUDIO_PEQ_11_BYP AUDIO_PEQ_11_BYP -#define AUDIO_PEQ_11_BYP_POS (20U) -#define AUDIO_PEQ_11_BYP_LEN (1U) -#define AUDIO_PEQ_11_BYP_MSK (((1U << AUDIO_PEQ_11_BYP_LEN) - 1) << AUDIO_PEQ_11_BYP_POS) -#define AUDIO_PEQ_11_BYP_UMSK (~(((1U << AUDIO_PEQ_11_BYP_LEN) - 1) << AUDIO_PEQ_11_BYP_POS)) -#define AUDIO_PEQ_11_QFMT AUDIO_PEQ_11_QFMT -#define AUDIO_PEQ_11_QFMT_POS (21U) -#define AUDIO_PEQ_11_QFMT_LEN (1U) -#define AUDIO_PEQ_11_QFMT_MSK (((1U << AUDIO_PEQ_11_QFMT_LEN) - 1) << AUDIO_PEQ_11_QFMT_POS) -#define AUDIO_PEQ_11_QFMT_UMSK (~(((1U << AUDIO_PEQ_11_QFMT_LEN) - 1) << AUDIO_PEQ_11_QFMT_POS)) - -/* 0x2E0 : peq_11_b1 */ -#define AUDIO_PEQ_11_B1_OFFSET (0x2E0) -#define AUDIO_PEQ_11_B1 AUDIO_PEQ_11_B1 -#define AUDIO_PEQ_11_B1_POS (0U) -#define AUDIO_PEQ_11_B1_LEN (20U) -#define AUDIO_PEQ_11_B1_MSK (((1U << AUDIO_PEQ_11_B1_LEN) - 1) << AUDIO_PEQ_11_B1_POS) -#define AUDIO_PEQ_11_B1_UMSK (~(((1U << AUDIO_PEQ_11_B1_LEN) - 1) << AUDIO_PEQ_11_B1_POS)) - -/* 0x2E4 : peq_11_b2 */ -#define AUDIO_PEQ_11_B2_OFFSET (0x2E4) -#define AUDIO_PEQ_11_B2 AUDIO_PEQ_11_B2 -#define AUDIO_PEQ_11_B2_POS (0U) -#define AUDIO_PEQ_11_B2_LEN (20U) -#define AUDIO_PEQ_11_B2_MSK (((1U << AUDIO_PEQ_11_B2_LEN) - 1) << AUDIO_PEQ_11_B2_POS) -#define AUDIO_PEQ_11_B2_UMSK (~(((1U << AUDIO_PEQ_11_B2_LEN) - 1) << AUDIO_PEQ_11_B2_POS)) - -/* 0x2E8 : peq_11_a1 */ -#define AUDIO_PEQ_11_A1_OFFSET (0x2E8) -#define AUDIO_PEQ_11_A1 AUDIO_PEQ_11_A1 -#define AUDIO_PEQ_11_A1_POS (0U) -#define AUDIO_PEQ_11_A1_LEN (20U) -#define AUDIO_PEQ_11_A1_MSK (((1U << AUDIO_PEQ_11_A1_LEN) - 1) << AUDIO_PEQ_11_A1_POS) -#define AUDIO_PEQ_11_A1_UMSK (~(((1U << AUDIO_PEQ_11_A1_LEN) - 1) << AUDIO_PEQ_11_A1_POS)) - -/* 0x2EC : peq_11_a2 */ -#define AUDIO_PEQ_11_A2_OFFSET (0x2EC) -#define AUDIO_PEQ_11_A2 AUDIO_PEQ_11_A2 -#define AUDIO_PEQ_11_A2_POS (0U) -#define AUDIO_PEQ_11_A2_LEN (20U) -#define AUDIO_PEQ_11_A2_MSK (((1U << AUDIO_PEQ_11_A2_LEN) - 1) << AUDIO_PEQ_11_A2_POS) -#define AUDIO_PEQ_11_A2_UMSK (~(((1U << AUDIO_PEQ_11_A2_LEN) - 1) << AUDIO_PEQ_11_A2_POS)) - -/* 0x2F0 : peq_12_b0 */ -#define AUDIO_PEQ_12_B0_OFFSET (0x2F0) -#define AUDIO_PEQ_12_B0 AUDIO_PEQ_12_B0 -#define AUDIO_PEQ_12_B0_POS (0U) -#define AUDIO_PEQ_12_B0_LEN (20U) -#define AUDIO_PEQ_12_B0_MSK (((1U << AUDIO_PEQ_12_B0_LEN) - 1) << AUDIO_PEQ_12_B0_POS) -#define AUDIO_PEQ_12_B0_UMSK (~(((1U << AUDIO_PEQ_12_B0_LEN) - 1) << AUDIO_PEQ_12_B0_POS)) -#define AUDIO_PEQ_12_BYP AUDIO_PEQ_12_BYP -#define AUDIO_PEQ_12_BYP_POS (20U) -#define AUDIO_PEQ_12_BYP_LEN (1U) -#define AUDIO_PEQ_12_BYP_MSK (((1U << AUDIO_PEQ_12_BYP_LEN) - 1) << AUDIO_PEQ_12_BYP_POS) -#define AUDIO_PEQ_12_BYP_UMSK (~(((1U << AUDIO_PEQ_12_BYP_LEN) - 1) << AUDIO_PEQ_12_BYP_POS)) -#define AUDIO_PEQ_12_QFMT AUDIO_PEQ_12_QFMT -#define AUDIO_PEQ_12_QFMT_POS (21U) -#define AUDIO_PEQ_12_QFMT_LEN (1U) -#define AUDIO_PEQ_12_QFMT_MSK (((1U << AUDIO_PEQ_12_QFMT_LEN) - 1) << AUDIO_PEQ_12_QFMT_POS) -#define AUDIO_PEQ_12_QFMT_UMSK (~(((1U << AUDIO_PEQ_12_QFMT_LEN) - 1) << AUDIO_PEQ_12_QFMT_POS)) - -/* 0x2F4 : peq_12_b1 */ -#define AUDIO_PEQ_12_B1_OFFSET (0x2F4) -#define AUDIO_PEQ_12_B1 AUDIO_PEQ_12_B1 -#define AUDIO_PEQ_12_B1_POS (0U) -#define AUDIO_PEQ_12_B1_LEN (20U) -#define AUDIO_PEQ_12_B1_MSK (((1U << AUDIO_PEQ_12_B1_LEN) - 1) << AUDIO_PEQ_12_B1_POS) -#define AUDIO_PEQ_12_B1_UMSK (~(((1U << AUDIO_PEQ_12_B1_LEN) - 1) << AUDIO_PEQ_12_B1_POS)) - -/* 0x2F8 : peq_12_b2 */ -#define AUDIO_PEQ_12_B2_OFFSET (0x2F8) -#define AUDIO_PEQ_12_B2 AUDIO_PEQ_12_B2 -#define AUDIO_PEQ_12_B2_POS (0U) -#define AUDIO_PEQ_12_B2_LEN (20U) -#define AUDIO_PEQ_12_B2_MSK (((1U << AUDIO_PEQ_12_B2_LEN) - 1) << AUDIO_PEQ_12_B2_POS) -#define AUDIO_PEQ_12_B2_UMSK (~(((1U << AUDIO_PEQ_12_B2_LEN) - 1) << AUDIO_PEQ_12_B2_POS)) - -/* 0x2FC : peq_12_a1 */ -#define AUDIO_PEQ_12_A1_OFFSET (0x2FC) -#define AUDIO_PEQ_12_A1 AUDIO_PEQ_12_A1 -#define AUDIO_PEQ_12_A1_POS (0U) -#define AUDIO_PEQ_12_A1_LEN (20U) -#define AUDIO_PEQ_12_A1_MSK (((1U << AUDIO_PEQ_12_A1_LEN) - 1) << AUDIO_PEQ_12_A1_POS) -#define AUDIO_PEQ_12_A1_UMSK (~(((1U << AUDIO_PEQ_12_A1_LEN) - 1) << AUDIO_PEQ_12_A1_POS)) - -/* 0x300 : peq_12_a2 */ -#define AUDIO_PEQ_12_A2_OFFSET (0x300) -#define AUDIO_PEQ_12_A2 AUDIO_PEQ_12_A2 -#define AUDIO_PEQ_12_A2_POS (0U) -#define AUDIO_PEQ_12_A2_LEN (20U) -#define AUDIO_PEQ_12_A2_MSK (((1U << AUDIO_PEQ_12_A2_LEN) - 1) << AUDIO_PEQ_12_A2_POS) -#define AUDIO_PEQ_12_A2_UMSK (~(((1U << AUDIO_PEQ_12_A2_LEN) - 1) << AUDIO_PEQ_12_A2_POS)) - -/* 0x304 : peq_13_b0 */ -#define AUDIO_PEQ_13_B0_OFFSET (0x304) -#define AUDIO_PEQ_13_B0 AUDIO_PEQ_13_B0 -#define AUDIO_PEQ_13_B0_POS (0U) -#define AUDIO_PEQ_13_B0_LEN (20U) -#define AUDIO_PEQ_13_B0_MSK (((1U << AUDIO_PEQ_13_B0_LEN) - 1) << AUDIO_PEQ_13_B0_POS) -#define AUDIO_PEQ_13_B0_UMSK (~(((1U << AUDIO_PEQ_13_B0_LEN) - 1) << AUDIO_PEQ_13_B0_POS)) -#define AUDIO_PEQ_13_BYP AUDIO_PEQ_13_BYP -#define AUDIO_PEQ_13_BYP_POS (20U) -#define AUDIO_PEQ_13_BYP_LEN (1U) -#define AUDIO_PEQ_13_BYP_MSK (((1U << AUDIO_PEQ_13_BYP_LEN) - 1) << AUDIO_PEQ_13_BYP_POS) -#define AUDIO_PEQ_13_BYP_UMSK (~(((1U << AUDIO_PEQ_13_BYP_LEN) - 1) << AUDIO_PEQ_13_BYP_POS)) -#define AUDIO_PEQ_13_QFMT AUDIO_PEQ_13_QFMT -#define AUDIO_PEQ_13_QFMT_POS (21U) -#define AUDIO_PEQ_13_QFMT_LEN (1U) -#define AUDIO_PEQ_13_QFMT_MSK (((1U << AUDIO_PEQ_13_QFMT_LEN) - 1) << AUDIO_PEQ_13_QFMT_POS) -#define AUDIO_PEQ_13_QFMT_UMSK (~(((1U << AUDIO_PEQ_13_QFMT_LEN) - 1) << AUDIO_PEQ_13_QFMT_POS)) - -/* 0x308 : peq_13_b1 */ -#define AUDIO_PEQ_13_B1_OFFSET (0x308) -#define AUDIO_PEQ_13_B1 AUDIO_PEQ_13_B1 -#define AUDIO_PEQ_13_B1_POS (0U) -#define AUDIO_PEQ_13_B1_LEN (20U) -#define AUDIO_PEQ_13_B1_MSK (((1U << AUDIO_PEQ_13_B1_LEN) - 1) << AUDIO_PEQ_13_B1_POS) -#define AUDIO_PEQ_13_B1_UMSK (~(((1U << AUDIO_PEQ_13_B1_LEN) - 1) << AUDIO_PEQ_13_B1_POS)) - -/* 0x30C : peq_13_b2 */ -#define AUDIO_PEQ_13_B2_OFFSET (0x30C) -#define AUDIO_PEQ_13_B2 AUDIO_PEQ_13_B2 -#define AUDIO_PEQ_13_B2_POS (0U) -#define AUDIO_PEQ_13_B2_LEN (20U) -#define AUDIO_PEQ_13_B2_MSK (((1U << AUDIO_PEQ_13_B2_LEN) - 1) << AUDIO_PEQ_13_B2_POS) -#define AUDIO_PEQ_13_B2_UMSK (~(((1U << AUDIO_PEQ_13_B2_LEN) - 1) << AUDIO_PEQ_13_B2_POS)) - -/* 0x310 : peq_13_a1 */ -#define AUDIO_PEQ_13_A1_OFFSET (0x310) -#define AUDIO_PEQ_13_A1 AUDIO_PEQ_13_A1 -#define AUDIO_PEQ_13_A1_POS (0U) -#define AUDIO_PEQ_13_A1_LEN (20U) -#define AUDIO_PEQ_13_A1_MSK (((1U << AUDIO_PEQ_13_A1_LEN) - 1) << AUDIO_PEQ_13_A1_POS) -#define AUDIO_PEQ_13_A1_UMSK (~(((1U << AUDIO_PEQ_13_A1_LEN) - 1) << AUDIO_PEQ_13_A1_POS)) - -/* 0x314 : peq_13_a2 */ -#define AUDIO_PEQ_13_A2_OFFSET (0x314) -#define AUDIO_PEQ_13_A2 AUDIO_PEQ_13_A2 -#define AUDIO_PEQ_13_A2_POS (0U) -#define AUDIO_PEQ_13_A2_LEN (20U) -#define AUDIO_PEQ_13_A2_MSK (((1U << AUDIO_PEQ_13_A2_LEN) - 1) << AUDIO_PEQ_13_A2_POS) -#define AUDIO_PEQ_13_A2_UMSK (~(((1U << AUDIO_PEQ_13_A2_LEN) - 1) << AUDIO_PEQ_13_A2_POS)) - -/* 0x318 : peq_14_b0 */ -#define AUDIO_PEQ_14_B0_OFFSET (0x318) -#define AUDIO_PEQ_14_B0 AUDIO_PEQ_14_B0 -#define AUDIO_PEQ_14_B0_POS (0U) -#define AUDIO_PEQ_14_B0_LEN (20U) -#define AUDIO_PEQ_14_B0_MSK (((1U << AUDIO_PEQ_14_B0_LEN) - 1) << AUDIO_PEQ_14_B0_POS) -#define AUDIO_PEQ_14_B0_UMSK (~(((1U << AUDIO_PEQ_14_B0_LEN) - 1) << AUDIO_PEQ_14_B0_POS)) -#define AUDIO_PEQ_14_BYP AUDIO_PEQ_14_BYP -#define AUDIO_PEQ_14_BYP_POS (20U) -#define AUDIO_PEQ_14_BYP_LEN (1U) -#define AUDIO_PEQ_14_BYP_MSK (((1U << AUDIO_PEQ_14_BYP_LEN) - 1) << AUDIO_PEQ_14_BYP_POS) -#define AUDIO_PEQ_14_BYP_UMSK (~(((1U << AUDIO_PEQ_14_BYP_LEN) - 1) << AUDIO_PEQ_14_BYP_POS)) -#define AUDIO_PEQ_14_QFMT AUDIO_PEQ_14_QFMT -#define AUDIO_PEQ_14_QFMT_POS (21U) -#define AUDIO_PEQ_14_QFMT_LEN (1U) -#define AUDIO_PEQ_14_QFMT_MSK (((1U << AUDIO_PEQ_14_QFMT_LEN) - 1) << AUDIO_PEQ_14_QFMT_POS) -#define AUDIO_PEQ_14_QFMT_UMSK (~(((1U << AUDIO_PEQ_14_QFMT_LEN) - 1) << AUDIO_PEQ_14_QFMT_POS)) - -/* 0x31C : peq_14_b1 */ -#define AUDIO_PEQ_14_B1_OFFSET (0x31C) -#define AUDIO_PEQ_14_B1 AUDIO_PEQ_14_B1 -#define AUDIO_PEQ_14_B1_POS (0U) -#define AUDIO_PEQ_14_B1_LEN (20U) -#define AUDIO_PEQ_14_B1_MSK (((1U << AUDIO_PEQ_14_B1_LEN) - 1) << AUDIO_PEQ_14_B1_POS) -#define AUDIO_PEQ_14_B1_UMSK (~(((1U << AUDIO_PEQ_14_B1_LEN) - 1) << AUDIO_PEQ_14_B1_POS)) - -/* 0x320 : peq_14_b2 */ -#define AUDIO_PEQ_14_B2_OFFSET (0x320) -#define AUDIO_PEQ_14_B2 AUDIO_PEQ_14_B2 -#define AUDIO_PEQ_14_B2_POS (0U) -#define AUDIO_PEQ_14_B2_LEN (20U) -#define AUDIO_PEQ_14_B2_MSK (((1U << AUDIO_PEQ_14_B2_LEN) - 1) << AUDIO_PEQ_14_B2_POS) -#define AUDIO_PEQ_14_B2_UMSK (~(((1U << AUDIO_PEQ_14_B2_LEN) - 1) << AUDIO_PEQ_14_B2_POS)) - -/* 0x324 : peq_14_a1 */ -#define AUDIO_PEQ_14_A1_OFFSET (0x324) -#define AUDIO_PEQ_14_A1 AUDIO_PEQ_14_A1 -#define AUDIO_PEQ_14_A1_POS (0U) -#define AUDIO_PEQ_14_A1_LEN (20U) -#define AUDIO_PEQ_14_A1_MSK (((1U << AUDIO_PEQ_14_A1_LEN) - 1) << AUDIO_PEQ_14_A1_POS) -#define AUDIO_PEQ_14_A1_UMSK (~(((1U << AUDIO_PEQ_14_A1_LEN) - 1) << AUDIO_PEQ_14_A1_POS)) - -/* 0x328 : peq_14_a2 */ -#define AUDIO_PEQ_14_A2_OFFSET (0x328) -#define AUDIO_PEQ_14_A2 AUDIO_PEQ_14_A2 -#define AUDIO_PEQ_14_A2_POS (0U) -#define AUDIO_PEQ_14_A2_LEN (20U) -#define AUDIO_PEQ_14_A2_MSK (((1U << AUDIO_PEQ_14_A2_LEN) - 1) << AUDIO_PEQ_14_A2_POS) -#define AUDIO_PEQ_14_A2_UMSK (~(((1U << AUDIO_PEQ_14_A2_LEN) - 1) << AUDIO_PEQ_14_A2_POS)) - -/* 0x32C : peq_15_b0 */ -#define AUDIO_PEQ_15_B0_OFFSET (0x32C) -#define AUDIO_PEQ_15_B0 AUDIO_PEQ_15_B0 -#define AUDIO_PEQ_15_B0_POS (0U) -#define AUDIO_PEQ_15_B0_LEN (20U) -#define AUDIO_PEQ_15_B0_MSK (((1U << AUDIO_PEQ_15_B0_LEN) - 1) << AUDIO_PEQ_15_B0_POS) -#define AUDIO_PEQ_15_B0_UMSK (~(((1U << AUDIO_PEQ_15_B0_LEN) - 1) << AUDIO_PEQ_15_B0_POS)) -#define AUDIO_PEQ_15_BYP AUDIO_PEQ_15_BYP -#define AUDIO_PEQ_15_BYP_POS (20U) -#define AUDIO_PEQ_15_BYP_LEN (1U) -#define AUDIO_PEQ_15_BYP_MSK (((1U << AUDIO_PEQ_15_BYP_LEN) - 1) << AUDIO_PEQ_15_BYP_POS) -#define AUDIO_PEQ_15_BYP_UMSK (~(((1U << AUDIO_PEQ_15_BYP_LEN) - 1) << AUDIO_PEQ_15_BYP_POS)) -#define AUDIO_PEQ_15_QFMT AUDIO_PEQ_15_QFMT -#define AUDIO_PEQ_15_QFMT_POS (21U) -#define AUDIO_PEQ_15_QFMT_LEN (1U) -#define AUDIO_PEQ_15_QFMT_MSK (((1U << AUDIO_PEQ_15_QFMT_LEN) - 1) << AUDIO_PEQ_15_QFMT_POS) -#define AUDIO_PEQ_15_QFMT_UMSK (~(((1U << AUDIO_PEQ_15_QFMT_LEN) - 1) << AUDIO_PEQ_15_QFMT_POS)) - -/* 0x330 : peq_15_b1 */ -#define AUDIO_PEQ_15_B1_OFFSET (0x330) -#define AUDIO_PEQ_15_B1 AUDIO_PEQ_15_B1 -#define AUDIO_PEQ_15_B1_POS (0U) -#define AUDIO_PEQ_15_B1_LEN (20U) -#define AUDIO_PEQ_15_B1_MSK (((1U << AUDIO_PEQ_15_B1_LEN) - 1) << AUDIO_PEQ_15_B1_POS) -#define AUDIO_PEQ_15_B1_UMSK (~(((1U << AUDIO_PEQ_15_B1_LEN) - 1) << AUDIO_PEQ_15_B1_POS)) - -/* 0x334 : peq_15_b2 */ -#define AUDIO_PEQ_15_B2_OFFSET (0x334) -#define AUDIO_PEQ_15_B2 AUDIO_PEQ_15_B2 -#define AUDIO_PEQ_15_B2_POS (0U) -#define AUDIO_PEQ_15_B2_LEN (20U) -#define AUDIO_PEQ_15_B2_MSK (((1U << AUDIO_PEQ_15_B2_LEN) - 1) << AUDIO_PEQ_15_B2_POS) -#define AUDIO_PEQ_15_B2_UMSK (~(((1U << AUDIO_PEQ_15_B2_LEN) - 1) << AUDIO_PEQ_15_B2_POS)) - -/* 0x338 : peq_15_a1 */ -#define AUDIO_PEQ_15_A1_OFFSET (0x338) -#define AUDIO_PEQ_15_A1 AUDIO_PEQ_15_A1 -#define AUDIO_PEQ_15_A1_POS (0U) -#define AUDIO_PEQ_15_A1_LEN (20U) -#define AUDIO_PEQ_15_A1_MSK (((1U << AUDIO_PEQ_15_A1_LEN) - 1) << AUDIO_PEQ_15_A1_POS) -#define AUDIO_PEQ_15_A1_UMSK (~(((1U << AUDIO_PEQ_15_A1_LEN) - 1) << AUDIO_PEQ_15_A1_POS)) - -/* 0x33C : peq_15_a2 */ -#define AUDIO_PEQ_15_A2_OFFSET (0x33C) -#define AUDIO_PEQ_15_A2 AUDIO_PEQ_15_A2 -#define AUDIO_PEQ_15_A2_POS (0U) -#define AUDIO_PEQ_15_A2_LEN (20U) -#define AUDIO_PEQ_15_A2_MSK (((1U << AUDIO_PEQ_15_A2_LEN) - 1) << AUDIO_PEQ_15_A2_POS) -#define AUDIO_PEQ_15_A2_UMSK (~(((1U << AUDIO_PEQ_15_A2_LEN) - 1) << AUDIO_PEQ_15_A2_POS)) - -/* 0x340 : peq_16_b0 */ -#define AUDIO_PEQ_16_B0_OFFSET (0x340) -#define AUDIO_PEQ_16_B0 AUDIO_PEQ_16_B0 -#define AUDIO_PEQ_16_B0_POS (0U) -#define AUDIO_PEQ_16_B0_LEN (20U) -#define AUDIO_PEQ_16_B0_MSK (((1U << AUDIO_PEQ_16_B0_LEN) - 1) << AUDIO_PEQ_16_B0_POS) -#define AUDIO_PEQ_16_B0_UMSK (~(((1U << AUDIO_PEQ_16_B0_LEN) - 1) << AUDIO_PEQ_16_B0_POS)) -#define AUDIO_PEQ_16_BYP AUDIO_PEQ_16_BYP -#define AUDIO_PEQ_16_BYP_POS (20U) -#define AUDIO_PEQ_16_BYP_LEN (1U) -#define AUDIO_PEQ_16_BYP_MSK (((1U << AUDIO_PEQ_16_BYP_LEN) - 1) << AUDIO_PEQ_16_BYP_POS) -#define AUDIO_PEQ_16_BYP_UMSK (~(((1U << AUDIO_PEQ_16_BYP_LEN) - 1) << AUDIO_PEQ_16_BYP_POS)) -#define AUDIO_PEQ_16_QFMT AUDIO_PEQ_16_QFMT -#define AUDIO_PEQ_16_QFMT_POS (21U) -#define AUDIO_PEQ_16_QFMT_LEN (1U) -#define AUDIO_PEQ_16_QFMT_MSK (((1U << AUDIO_PEQ_16_QFMT_LEN) - 1) << AUDIO_PEQ_16_QFMT_POS) -#define AUDIO_PEQ_16_QFMT_UMSK (~(((1U << AUDIO_PEQ_16_QFMT_LEN) - 1) << AUDIO_PEQ_16_QFMT_POS)) - -/* 0x344 : peq_16_b1 */ -#define AUDIO_PEQ_16_B1_OFFSET (0x344) -#define AUDIO_PEQ_16_B1 AUDIO_PEQ_16_B1 -#define AUDIO_PEQ_16_B1_POS (0U) -#define AUDIO_PEQ_16_B1_LEN (20U) -#define AUDIO_PEQ_16_B1_MSK (((1U << AUDIO_PEQ_16_B1_LEN) - 1) << AUDIO_PEQ_16_B1_POS) -#define AUDIO_PEQ_16_B1_UMSK (~(((1U << AUDIO_PEQ_16_B1_LEN) - 1) << AUDIO_PEQ_16_B1_POS)) - -/* 0x348 : peq_16_b2 */ -#define AUDIO_PEQ_16_B2_OFFSET (0x348) -#define AUDIO_PEQ_16_B2 AUDIO_PEQ_16_B2 -#define AUDIO_PEQ_16_B2_POS (0U) -#define AUDIO_PEQ_16_B2_LEN (20U) -#define AUDIO_PEQ_16_B2_MSK (((1U << AUDIO_PEQ_16_B2_LEN) - 1) << AUDIO_PEQ_16_B2_POS) -#define AUDIO_PEQ_16_B2_UMSK (~(((1U << AUDIO_PEQ_16_B2_LEN) - 1) << AUDIO_PEQ_16_B2_POS)) - -/* 0x34C : peq_16_a1 */ -#define AUDIO_PEQ_16_A1_OFFSET (0x34C) -#define AUDIO_PEQ_16_A1 AUDIO_PEQ_16_A1 -#define AUDIO_PEQ_16_A1_POS (0U) -#define AUDIO_PEQ_16_A1_LEN (20U) -#define AUDIO_PEQ_16_A1_MSK (((1U << AUDIO_PEQ_16_A1_LEN) - 1) << AUDIO_PEQ_16_A1_POS) -#define AUDIO_PEQ_16_A1_UMSK (~(((1U << AUDIO_PEQ_16_A1_LEN) - 1) << AUDIO_PEQ_16_A1_POS)) - -/* 0x350 : peq_16_a2 */ -#define AUDIO_PEQ_16_A2_OFFSET (0x350) -#define AUDIO_PEQ_16_A2 AUDIO_PEQ_16_A2 -#define AUDIO_PEQ_16_A2_POS (0U) -#define AUDIO_PEQ_16_A2_LEN (20U) -#define AUDIO_PEQ_16_A2_MSK (((1U << AUDIO_PEQ_16_A2_LEN) - 1) << AUDIO_PEQ_16_A2_POS) -#define AUDIO_PEQ_16_A2_UMSK (~(((1U << AUDIO_PEQ_16_A2_LEN) - 1) << AUDIO_PEQ_16_A2_POS)) - -/* 0x354 : peq_17_b0 */ -#define AUDIO_PEQ_17_B0_OFFSET (0x354) -#define AUDIO_PEQ_17_B0 AUDIO_PEQ_17_B0 -#define AUDIO_PEQ_17_B0_POS (0U) -#define AUDIO_PEQ_17_B0_LEN (20U) -#define AUDIO_PEQ_17_B0_MSK (((1U << AUDIO_PEQ_17_B0_LEN) - 1) << AUDIO_PEQ_17_B0_POS) -#define AUDIO_PEQ_17_B0_UMSK (~(((1U << AUDIO_PEQ_17_B0_LEN) - 1) << AUDIO_PEQ_17_B0_POS)) -#define AUDIO_PEQ_17_BYP AUDIO_PEQ_17_BYP -#define AUDIO_PEQ_17_BYP_POS (20U) -#define AUDIO_PEQ_17_BYP_LEN (1U) -#define AUDIO_PEQ_17_BYP_MSK (((1U << AUDIO_PEQ_17_BYP_LEN) - 1) << AUDIO_PEQ_17_BYP_POS) -#define AUDIO_PEQ_17_BYP_UMSK (~(((1U << AUDIO_PEQ_17_BYP_LEN) - 1) << AUDIO_PEQ_17_BYP_POS)) -#define AUDIO_PEQ_17_QFMT AUDIO_PEQ_17_QFMT -#define AUDIO_PEQ_17_QFMT_POS (21U) -#define AUDIO_PEQ_17_QFMT_LEN (1U) -#define AUDIO_PEQ_17_QFMT_MSK (((1U << AUDIO_PEQ_17_QFMT_LEN) - 1) << AUDIO_PEQ_17_QFMT_POS) -#define AUDIO_PEQ_17_QFMT_UMSK (~(((1U << AUDIO_PEQ_17_QFMT_LEN) - 1) << AUDIO_PEQ_17_QFMT_POS)) - -/* 0x358 : peq_17_b1 */ -#define AUDIO_PEQ_17_B1_OFFSET (0x358) -#define AUDIO_PEQ_17_B1 AUDIO_PEQ_17_B1 -#define AUDIO_PEQ_17_B1_POS (0U) -#define AUDIO_PEQ_17_B1_LEN (20U) -#define AUDIO_PEQ_17_B1_MSK (((1U << AUDIO_PEQ_17_B1_LEN) - 1) << AUDIO_PEQ_17_B1_POS) -#define AUDIO_PEQ_17_B1_UMSK (~(((1U << AUDIO_PEQ_17_B1_LEN) - 1) << AUDIO_PEQ_17_B1_POS)) - -/* 0x35C : peq_17_b2 */ -#define AUDIO_PEQ_17_B2_OFFSET (0x35C) -#define AUDIO_PEQ_17_B2 AUDIO_PEQ_17_B2 -#define AUDIO_PEQ_17_B2_POS (0U) -#define AUDIO_PEQ_17_B2_LEN (20U) -#define AUDIO_PEQ_17_B2_MSK (((1U << AUDIO_PEQ_17_B2_LEN) - 1) << AUDIO_PEQ_17_B2_POS) -#define AUDIO_PEQ_17_B2_UMSK (~(((1U << AUDIO_PEQ_17_B2_LEN) - 1) << AUDIO_PEQ_17_B2_POS)) - -/* 0x360 : peq_17_a1 */ -#define AUDIO_PEQ_17_A1_OFFSET (0x360) -#define AUDIO_PEQ_17_A1 AUDIO_PEQ_17_A1 -#define AUDIO_PEQ_17_A1_POS (0U) -#define AUDIO_PEQ_17_A1_LEN (20U) -#define AUDIO_PEQ_17_A1_MSK (((1U << AUDIO_PEQ_17_A1_LEN) - 1) << AUDIO_PEQ_17_A1_POS) -#define AUDIO_PEQ_17_A1_UMSK (~(((1U << AUDIO_PEQ_17_A1_LEN) - 1) << AUDIO_PEQ_17_A1_POS)) - -/* 0x364 : peq_17_a2 */ -#define AUDIO_PEQ_17_A2_OFFSET (0x364) -#define AUDIO_PEQ_17_A2 AUDIO_PEQ_17_A2 -#define AUDIO_PEQ_17_A2_POS (0U) -#define AUDIO_PEQ_17_A2_LEN (20U) -#define AUDIO_PEQ_17_A2_MSK (((1U << AUDIO_PEQ_17_A2_LEN) - 1) << AUDIO_PEQ_17_A2_POS) -#define AUDIO_PEQ_17_A2_UMSK (~(((1U << AUDIO_PEQ_17_A2_LEN) - 1) << AUDIO_PEQ_17_A2_POS)) - -/* 0x368 : peq_18_b0 */ -#define AUDIO_PEQ_18_B0_OFFSET (0x368) -#define AUDIO_PEQ_18_B0 AUDIO_PEQ_18_B0 -#define AUDIO_PEQ_18_B0_POS (0U) -#define AUDIO_PEQ_18_B0_LEN (20U) -#define AUDIO_PEQ_18_B0_MSK (((1U << AUDIO_PEQ_18_B0_LEN) - 1) << AUDIO_PEQ_18_B0_POS) -#define AUDIO_PEQ_18_B0_UMSK (~(((1U << AUDIO_PEQ_18_B0_LEN) - 1) << AUDIO_PEQ_18_B0_POS)) -#define AUDIO_PEQ_18_BYP AUDIO_PEQ_18_BYP -#define AUDIO_PEQ_18_BYP_POS (20U) -#define AUDIO_PEQ_18_BYP_LEN (1U) -#define AUDIO_PEQ_18_BYP_MSK (((1U << AUDIO_PEQ_18_BYP_LEN) - 1) << AUDIO_PEQ_18_BYP_POS) -#define AUDIO_PEQ_18_BYP_UMSK (~(((1U << AUDIO_PEQ_18_BYP_LEN) - 1) << AUDIO_PEQ_18_BYP_POS)) -#define AUDIO_PEQ_18_QFMT AUDIO_PEQ_18_QFMT -#define AUDIO_PEQ_18_QFMT_POS (21U) -#define AUDIO_PEQ_18_QFMT_LEN (1U) -#define AUDIO_PEQ_18_QFMT_MSK (((1U << AUDIO_PEQ_18_QFMT_LEN) - 1) << AUDIO_PEQ_18_QFMT_POS) -#define AUDIO_PEQ_18_QFMT_UMSK (~(((1U << AUDIO_PEQ_18_QFMT_LEN) - 1) << AUDIO_PEQ_18_QFMT_POS)) - -/* 0x36C : peq_18_b1 */ -#define AUDIO_PEQ_18_B1_OFFSET (0x36C) -#define AUDIO_PEQ_18_B1 AUDIO_PEQ_18_B1 -#define AUDIO_PEQ_18_B1_POS (0U) -#define AUDIO_PEQ_18_B1_LEN (20U) -#define AUDIO_PEQ_18_B1_MSK (((1U << AUDIO_PEQ_18_B1_LEN) - 1) << AUDIO_PEQ_18_B1_POS) -#define AUDIO_PEQ_18_B1_UMSK (~(((1U << AUDIO_PEQ_18_B1_LEN) - 1) << AUDIO_PEQ_18_B1_POS)) - -/* 0x370 : peq_18_b2 */ -#define AUDIO_PEQ_18_B2_OFFSET (0x370) -#define AUDIO_PEQ_18_B2 AUDIO_PEQ_18_B2 -#define AUDIO_PEQ_18_B2_POS (0U) -#define AUDIO_PEQ_18_B2_LEN (20U) -#define AUDIO_PEQ_18_B2_MSK (((1U << AUDIO_PEQ_18_B2_LEN) - 1) << AUDIO_PEQ_18_B2_POS) -#define AUDIO_PEQ_18_B2_UMSK (~(((1U << AUDIO_PEQ_18_B2_LEN) - 1) << AUDIO_PEQ_18_B2_POS)) - -/* 0x374 : peq_18_a1 */ -#define AUDIO_PEQ_18_A1_OFFSET (0x374) -#define AUDIO_PEQ_18_A1 AUDIO_PEQ_18_A1 -#define AUDIO_PEQ_18_A1_POS (0U) -#define AUDIO_PEQ_18_A1_LEN (20U) -#define AUDIO_PEQ_18_A1_MSK (((1U << AUDIO_PEQ_18_A1_LEN) - 1) << AUDIO_PEQ_18_A1_POS) -#define AUDIO_PEQ_18_A1_UMSK (~(((1U << AUDIO_PEQ_18_A1_LEN) - 1) << AUDIO_PEQ_18_A1_POS)) - -/* 0x378 : peq_18_a2 */ -#define AUDIO_PEQ_18_A2_OFFSET (0x378) -#define AUDIO_PEQ_18_A2 AUDIO_PEQ_18_A2 -#define AUDIO_PEQ_18_A2_POS (0U) -#define AUDIO_PEQ_18_A2_LEN (20U) -#define AUDIO_PEQ_18_A2_MSK (((1U << AUDIO_PEQ_18_A2_LEN) - 1) << AUDIO_PEQ_18_A2_POS) -#define AUDIO_PEQ_18_A2_UMSK (~(((1U << AUDIO_PEQ_18_A2_LEN) - 1) << AUDIO_PEQ_18_A2_POS)) - -/* 0x37C : peq_19_b0 */ -#define AUDIO_PEQ_19_B0_OFFSET (0x37C) -#define AUDIO_PEQ_19_B0 AUDIO_PEQ_19_B0 -#define AUDIO_PEQ_19_B0_POS (0U) -#define AUDIO_PEQ_19_B0_LEN (20U) -#define AUDIO_PEQ_19_B0_MSK (((1U << AUDIO_PEQ_19_B0_LEN) - 1) << AUDIO_PEQ_19_B0_POS) -#define AUDIO_PEQ_19_B0_UMSK (~(((1U << AUDIO_PEQ_19_B0_LEN) - 1) << AUDIO_PEQ_19_B0_POS)) -#define AUDIO_PEQ_19_BYP AUDIO_PEQ_19_BYP -#define AUDIO_PEQ_19_BYP_POS (20U) -#define AUDIO_PEQ_19_BYP_LEN (1U) -#define AUDIO_PEQ_19_BYP_MSK (((1U << AUDIO_PEQ_19_BYP_LEN) - 1) << AUDIO_PEQ_19_BYP_POS) -#define AUDIO_PEQ_19_BYP_UMSK (~(((1U << AUDIO_PEQ_19_BYP_LEN) - 1) << AUDIO_PEQ_19_BYP_POS)) -#define AUDIO_PEQ_19_QFMT AUDIO_PEQ_19_QFMT -#define AUDIO_PEQ_19_QFMT_POS (21U) -#define AUDIO_PEQ_19_QFMT_LEN (1U) -#define AUDIO_PEQ_19_QFMT_MSK (((1U << AUDIO_PEQ_19_QFMT_LEN) - 1) << AUDIO_PEQ_19_QFMT_POS) -#define AUDIO_PEQ_19_QFMT_UMSK (~(((1U << AUDIO_PEQ_19_QFMT_LEN) - 1) << AUDIO_PEQ_19_QFMT_POS)) - -/* 0x380 : peq_19_b1 */ -#define AUDIO_PEQ_19_B1_OFFSET (0x380) -#define AUDIO_PEQ_19_B1 AUDIO_PEQ_19_B1 -#define AUDIO_PEQ_19_B1_POS (0U) -#define AUDIO_PEQ_19_B1_LEN (20U) -#define AUDIO_PEQ_19_B1_MSK (((1U << AUDIO_PEQ_19_B1_LEN) - 1) << AUDIO_PEQ_19_B1_POS) -#define AUDIO_PEQ_19_B1_UMSK (~(((1U << AUDIO_PEQ_19_B1_LEN) - 1) << AUDIO_PEQ_19_B1_POS)) - -/* 0x384 : peq_19_b2 */ -#define AUDIO_PEQ_19_B2_OFFSET (0x384) -#define AUDIO_PEQ_19_B2 AUDIO_PEQ_19_B2 -#define AUDIO_PEQ_19_B2_POS (0U) -#define AUDIO_PEQ_19_B2_LEN (20U) -#define AUDIO_PEQ_19_B2_MSK (((1U << AUDIO_PEQ_19_B2_LEN) - 1) << AUDIO_PEQ_19_B2_POS) -#define AUDIO_PEQ_19_B2_UMSK (~(((1U << AUDIO_PEQ_19_B2_LEN) - 1) << AUDIO_PEQ_19_B2_POS)) - -/* 0x388 : peq_19_a1 */ -#define AUDIO_PEQ_19_A1_OFFSET (0x388) -#define AUDIO_PEQ_19_A1 AUDIO_PEQ_19_A1 -#define AUDIO_PEQ_19_A1_POS (0U) -#define AUDIO_PEQ_19_A1_LEN (20U) -#define AUDIO_PEQ_19_A1_MSK (((1U << AUDIO_PEQ_19_A1_LEN) - 1) << AUDIO_PEQ_19_A1_POS) -#define AUDIO_PEQ_19_A1_UMSK (~(((1U << AUDIO_PEQ_19_A1_LEN) - 1) << AUDIO_PEQ_19_A1_POS)) - -/* 0x38C : peq_19_a2 */ -#define AUDIO_PEQ_19_A2_OFFSET (0x38C) -#define AUDIO_PEQ_19_A2 AUDIO_PEQ_19_A2 -#define AUDIO_PEQ_19_A2_POS (0U) -#define AUDIO_PEQ_19_A2_LEN (20U) -#define AUDIO_PEQ_19_A2_MSK (((1U << AUDIO_PEQ_19_A2_LEN) - 1) << AUDIO_PEQ_19_A2_POS) -#define AUDIO_PEQ_19_A2_UMSK (~(((1U << AUDIO_PEQ_19_A2_LEN) - 1) << AUDIO_PEQ_19_A2_POS)) - -/* 0x390 : peq_20_b0 */ -#define AUDIO_PEQ_20_B0_OFFSET (0x390) -#define AUDIO_PEQ_20_B0 AUDIO_PEQ_20_B0 -#define AUDIO_PEQ_20_B0_POS (0U) -#define AUDIO_PEQ_20_B0_LEN (20U) -#define AUDIO_PEQ_20_B0_MSK (((1U << AUDIO_PEQ_20_B0_LEN) - 1) << AUDIO_PEQ_20_B0_POS) -#define AUDIO_PEQ_20_B0_UMSK (~(((1U << AUDIO_PEQ_20_B0_LEN) - 1) << AUDIO_PEQ_20_B0_POS)) -#define AUDIO_PEQ_20_BYP AUDIO_PEQ_20_BYP -#define AUDIO_PEQ_20_BYP_POS (20U) -#define AUDIO_PEQ_20_BYP_LEN (1U) -#define AUDIO_PEQ_20_BYP_MSK (((1U << AUDIO_PEQ_20_BYP_LEN) - 1) << AUDIO_PEQ_20_BYP_POS) -#define AUDIO_PEQ_20_BYP_UMSK (~(((1U << AUDIO_PEQ_20_BYP_LEN) - 1) << AUDIO_PEQ_20_BYP_POS)) -#define AUDIO_PEQ_20_QFMT AUDIO_PEQ_20_QFMT -#define AUDIO_PEQ_20_QFMT_POS (21U) -#define AUDIO_PEQ_20_QFMT_LEN (1U) -#define AUDIO_PEQ_20_QFMT_MSK (((1U << AUDIO_PEQ_20_QFMT_LEN) - 1) << AUDIO_PEQ_20_QFMT_POS) -#define AUDIO_PEQ_20_QFMT_UMSK (~(((1U << AUDIO_PEQ_20_QFMT_LEN) - 1) << AUDIO_PEQ_20_QFMT_POS)) -#define AUDIO_ADC_PEQ_IN_SEL AUDIO_ADC_PEQ_IN_SEL -#define AUDIO_ADC_PEQ_IN_SEL_POS (30U) -#define AUDIO_ADC_PEQ_IN_SEL_LEN (2U) -#define AUDIO_ADC_PEQ_IN_SEL_MSK (((1U << AUDIO_ADC_PEQ_IN_SEL_LEN) - 1) << AUDIO_ADC_PEQ_IN_SEL_POS) -#define AUDIO_ADC_PEQ_IN_SEL_UMSK (~(((1U << AUDIO_ADC_PEQ_IN_SEL_LEN) - 1) << AUDIO_ADC_PEQ_IN_SEL_POS)) - -/* 0x394 : peq_20_b1 */ -#define AUDIO_PEQ_20_B1_OFFSET (0x394) -#define AUDIO_PEQ_20_B1 AUDIO_PEQ_20_B1 -#define AUDIO_PEQ_20_B1_POS (0U) -#define AUDIO_PEQ_20_B1_LEN (20U) -#define AUDIO_PEQ_20_B1_MSK (((1U << AUDIO_PEQ_20_B1_LEN) - 1) << AUDIO_PEQ_20_B1_POS) -#define AUDIO_PEQ_20_B1_UMSK (~(((1U << AUDIO_PEQ_20_B1_LEN) - 1) << AUDIO_PEQ_20_B1_POS)) - -/* 0x398 : peq_20_b2 */ -#define AUDIO_PEQ_20_B2_OFFSET (0x398) -#define AUDIO_PEQ_20_B2 AUDIO_PEQ_20_B2 -#define AUDIO_PEQ_20_B2_POS (0U) -#define AUDIO_PEQ_20_B2_LEN (20U) -#define AUDIO_PEQ_20_B2_MSK (((1U << AUDIO_PEQ_20_B2_LEN) - 1) << AUDIO_PEQ_20_B2_POS) -#define AUDIO_PEQ_20_B2_UMSK (~(((1U << AUDIO_PEQ_20_B2_LEN) - 1) << AUDIO_PEQ_20_B2_POS)) - -/* 0x39C : peq_20_a1 */ -#define AUDIO_PEQ_20_A1_OFFSET (0x39C) -#define AUDIO_PEQ_20_A1 AUDIO_PEQ_20_A1 -#define AUDIO_PEQ_20_A1_POS (0U) -#define AUDIO_PEQ_20_A1_LEN (20U) -#define AUDIO_PEQ_20_A1_MSK (((1U << AUDIO_PEQ_20_A1_LEN) - 1) << AUDIO_PEQ_20_A1_POS) -#define AUDIO_PEQ_20_A1_UMSK (~(((1U << AUDIO_PEQ_20_A1_LEN) - 1) << AUDIO_PEQ_20_A1_POS)) - -/* 0x3A0 : peq_20_a2 */ -#define AUDIO_PEQ_20_A2_OFFSET (0x3A0) -#define AUDIO_PEQ_20_A2 AUDIO_PEQ_20_A2 -#define AUDIO_PEQ_20_A2_POS (0U) -#define AUDIO_PEQ_20_A2_LEN (20U) -#define AUDIO_PEQ_20_A2_MSK (((1U << AUDIO_PEQ_20_A2_LEN) - 1) << AUDIO_PEQ_20_A2_POS) -#define AUDIO_PEQ_20_A2_UMSK (~(((1U << AUDIO_PEQ_20_A2_LEN) - 1) << AUDIO_PEQ_20_A2_POS)) - -/* 0x3A4 : peq_21_b0 */ -#define AUDIO_PEQ_21_B0_OFFSET (0x3A4) -#define AUDIO_PEQ_21_B0 AUDIO_PEQ_21_B0 -#define AUDIO_PEQ_21_B0_POS (0U) -#define AUDIO_PEQ_21_B0_LEN (20U) -#define AUDIO_PEQ_21_B0_MSK (((1U << AUDIO_PEQ_21_B0_LEN) - 1) << AUDIO_PEQ_21_B0_POS) -#define AUDIO_PEQ_21_B0_UMSK (~(((1U << AUDIO_PEQ_21_B0_LEN) - 1) << AUDIO_PEQ_21_B0_POS)) -#define AUDIO_PEQ_21_BYP AUDIO_PEQ_21_BYP -#define AUDIO_PEQ_21_BYP_POS (20U) -#define AUDIO_PEQ_21_BYP_LEN (1U) -#define AUDIO_PEQ_21_BYP_MSK (((1U << AUDIO_PEQ_21_BYP_LEN) - 1) << AUDIO_PEQ_21_BYP_POS) -#define AUDIO_PEQ_21_BYP_UMSK (~(((1U << AUDIO_PEQ_21_BYP_LEN) - 1) << AUDIO_PEQ_21_BYP_POS)) -#define AUDIO_PEQ_21_QFMT AUDIO_PEQ_21_QFMT -#define AUDIO_PEQ_21_QFMT_POS (21U) -#define AUDIO_PEQ_21_QFMT_LEN (1U) -#define AUDIO_PEQ_21_QFMT_MSK (((1U << AUDIO_PEQ_21_QFMT_LEN) - 1) << AUDIO_PEQ_21_QFMT_POS) -#define AUDIO_PEQ_21_QFMT_UMSK (~(((1U << AUDIO_PEQ_21_QFMT_LEN) - 1) << AUDIO_PEQ_21_QFMT_POS)) - -/* 0x3A8 : peq_21_b1 */ -#define AUDIO_PEQ_21_B1_OFFSET (0x3A8) -#define AUDIO_PEQ_21_B1 AUDIO_PEQ_21_B1 -#define AUDIO_PEQ_21_B1_POS (0U) -#define AUDIO_PEQ_21_B1_LEN (20U) -#define AUDIO_PEQ_21_B1_MSK (((1U << AUDIO_PEQ_21_B1_LEN) - 1) << AUDIO_PEQ_21_B1_POS) -#define AUDIO_PEQ_21_B1_UMSK (~(((1U << AUDIO_PEQ_21_B1_LEN) - 1) << AUDIO_PEQ_21_B1_POS)) - -/* 0x3AC : peq_21_b2 */ -#define AUDIO_PEQ_21_B2_OFFSET (0x3AC) -#define AUDIO_PEQ_21_B2 AUDIO_PEQ_21_B2 -#define AUDIO_PEQ_21_B2_POS (0U) -#define AUDIO_PEQ_21_B2_LEN (20U) -#define AUDIO_PEQ_21_B2_MSK (((1U << AUDIO_PEQ_21_B2_LEN) - 1) << AUDIO_PEQ_21_B2_POS) -#define AUDIO_PEQ_21_B2_UMSK (~(((1U << AUDIO_PEQ_21_B2_LEN) - 1) << AUDIO_PEQ_21_B2_POS)) - -/* 0x3B0 : peq_21_a1 */ -#define AUDIO_PEQ_21_A1_OFFSET (0x3B0) -#define AUDIO_PEQ_21_A1 AUDIO_PEQ_21_A1 -#define AUDIO_PEQ_21_A1_POS (0U) -#define AUDIO_PEQ_21_A1_LEN (20U) -#define AUDIO_PEQ_21_A1_MSK (((1U << AUDIO_PEQ_21_A1_LEN) - 1) << AUDIO_PEQ_21_A1_POS) -#define AUDIO_PEQ_21_A1_UMSK (~(((1U << AUDIO_PEQ_21_A1_LEN) - 1) << AUDIO_PEQ_21_A1_POS)) - -/* 0x3B4 : peq_21_a2 */ -#define AUDIO_PEQ_21_A2_OFFSET (0x3B4) -#define AUDIO_PEQ_21_A2 AUDIO_PEQ_21_A2 -#define AUDIO_PEQ_21_A2_POS (0U) -#define AUDIO_PEQ_21_A2_LEN (20U) -#define AUDIO_PEQ_21_A2_MSK (((1U << AUDIO_PEQ_21_A2_LEN) - 1) << AUDIO_PEQ_21_A2_POS) -#define AUDIO_PEQ_21_A2_UMSK (~(((1U << AUDIO_PEQ_21_A2_LEN) - 1) << AUDIO_PEQ_21_A2_POS)) - -/* 0x3B8 : peq_22_b0 */ -#define AUDIO_PEQ_22_B0_OFFSET (0x3B8) -#define AUDIO_PEQ_22_B0 AUDIO_PEQ_22_B0 -#define AUDIO_PEQ_22_B0_POS (0U) -#define AUDIO_PEQ_22_B0_LEN (20U) -#define AUDIO_PEQ_22_B0_MSK (((1U << AUDIO_PEQ_22_B0_LEN) - 1) << AUDIO_PEQ_22_B0_POS) -#define AUDIO_PEQ_22_B0_UMSK (~(((1U << AUDIO_PEQ_22_B0_LEN) - 1) << AUDIO_PEQ_22_B0_POS)) -#define AUDIO_PEQ_22_BYP AUDIO_PEQ_22_BYP -#define AUDIO_PEQ_22_BYP_POS (20U) -#define AUDIO_PEQ_22_BYP_LEN (1U) -#define AUDIO_PEQ_22_BYP_MSK (((1U << AUDIO_PEQ_22_BYP_LEN) - 1) << AUDIO_PEQ_22_BYP_POS) -#define AUDIO_PEQ_22_BYP_UMSK (~(((1U << AUDIO_PEQ_22_BYP_LEN) - 1) << AUDIO_PEQ_22_BYP_POS)) -#define AUDIO_PEQ_22_QFMT AUDIO_PEQ_22_QFMT -#define AUDIO_PEQ_22_QFMT_POS (21U) -#define AUDIO_PEQ_22_QFMT_LEN (1U) -#define AUDIO_PEQ_22_QFMT_MSK (((1U << AUDIO_PEQ_22_QFMT_LEN) - 1) << AUDIO_PEQ_22_QFMT_POS) -#define AUDIO_PEQ_22_QFMT_UMSK (~(((1U << AUDIO_PEQ_22_QFMT_LEN) - 1) << AUDIO_PEQ_22_QFMT_POS)) - -/* 0x3BC : peq_22_b1 */ -#define AUDIO_PEQ_22_B1_OFFSET (0x3BC) -#define AUDIO_PEQ_22_B1 AUDIO_PEQ_22_B1 -#define AUDIO_PEQ_22_B1_POS (0U) -#define AUDIO_PEQ_22_B1_LEN (20U) -#define AUDIO_PEQ_22_B1_MSK (((1U << AUDIO_PEQ_22_B1_LEN) - 1) << AUDIO_PEQ_22_B1_POS) -#define AUDIO_PEQ_22_B1_UMSK (~(((1U << AUDIO_PEQ_22_B1_LEN) - 1) << AUDIO_PEQ_22_B1_POS)) - -/* 0x3C0 : peq_22_b2 */ -#define AUDIO_PEQ_22_B2_OFFSET (0x3C0) -#define AUDIO_PEQ_22_B2 AUDIO_PEQ_22_B2 -#define AUDIO_PEQ_22_B2_POS (0U) -#define AUDIO_PEQ_22_B2_LEN (20U) -#define AUDIO_PEQ_22_B2_MSK (((1U << AUDIO_PEQ_22_B2_LEN) - 1) << AUDIO_PEQ_22_B2_POS) -#define AUDIO_PEQ_22_B2_UMSK (~(((1U << AUDIO_PEQ_22_B2_LEN) - 1) << AUDIO_PEQ_22_B2_POS)) - -/* 0x3C4 : peq_22_a1 */ -#define AUDIO_PEQ_22_A1_OFFSET (0x3C4) -#define AUDIO_PEQ_22_A1 AUDIO_PEQ_22_A1 -#define AUDIO_PEQ_22_A1_POS (0U) -#define AUDIO_PEQ_22_A1_LEN (20U) -#define AUDIO_PEQ_22_A1_MSK (((1U << AUDIO_PEQ_22_A1_LEN) - 1) << AUDIO_PEQ_22_A1_POS) -#define AUDIO_PEQ_22_A1_UMSK (~(((1U << AUDIO_PEQ_22_A1_LEN) - 1) << AUDIO_PEQ_22_A1_POS)) - -/* 0x3C8 : peq_22_a2 */ -#define AUDIO_PEQ_22_A2_OFFSET (0x3C8) -#define AUDIO_PEQ_22_A2 AUDIO_PEQ_22_A2 -#define AUDIO_PEQ_22_A2_POS (0U) -#define AUDIO_PEQ_22_A2_LEN (20U) -#define AUDIO_PEQ_22_A2_MSK (((1U << AUDIO_PEQ_22_A2_LEN) - 1) << AUDIO_PEQ_22_A2_POS) -#define AUDIO_PEQ_22_A2_UMSK (~(((1U << AUDIO_PEQ_22_A2_LEN) - 1) << AUDIO_PEQ_22_A2_POS)) - -/* 0x3CC : peq_23_b0 */ -#define AUDIO_PEQ_23_B0_OFFSET (0x3CC) -#define AUDIO_PEQ_23_B0 AUDIO_PEQ_23_B0 -#define AUDIO_PEQ_23_B0_POS (0U) -#define AUDIO_PEQ_23_B0_LEN (20U) -#define AUDIO_PEQ_23_B0_MSK (((1U << AUDIO_PEQ_23_B0_LEN) - 1) << AUDIO_PEQ_23_B0_POS) -#define AUDIO_PEQ_23_B0_UMSK (~(((1U << AUDIO_PEQ_23_B0_LEN) - 1) << AUDIO_PEQ_23_B0_POS)) -#define AUDIO_PEQ_23_BYP AUDIO_PEQ_23_BYP -#define AUDIO_PEQ_23_BYP_POS (20U) -#define AUDIO_PEQ_23_BYP_LEN (1U) -#define AUDIO_PEQ_23_BYP_MSK (((1U << AUDIO_PEQ_23_BYP_LEN) - 1) << AUDIO_PEQ_23_BYP_POS) -#define AUDIO_PEQ_23_BYP_UMSK (~(((1U << AUDIO_PEQ_23_BYP_LEN) - 1) << AUDIO_PEQ_23_BYP_POS)) -#define AUDIO_PEQ_23_QFMT AUDIO_PEQ_23_QFMT -#define AUDIO_PEQ_23_QFMT_POS (21U) -#define AUDIO_PEQ_23_QFMT_LEN (1U) -#define AUDIO_PEQ_23_QFMT_MSK (((1U << AUDIO_PEQ_23_QFMT_LEN) - 1) << AUDIO_PEQ_23_QFMT_POS) -#define AUDIO_PEQ_23_QFMT_UMSK (~(((1U << AUDIO_PEQ_23_QFMT_LEN) - 1) << AUDIO_PEQ_23_QFMT_POS)) - -/* 0x3D0 : peq_23_b1 */ -#define AUDIO_PEQ_23_B1_OFFSET (0x3D0) -#define AUDIO_PEQ_23_B1 AUDIO_PEQ_23_B1 -#define AUDIO_PEQ_23_B1_POS (0U) -#define AUDIO_PEQ_23_B1_LEN (20U) -#define AUDIO_PEQ_23_B1_MSK (((1U << AUDIO_PEQ_23_B1_LEN) - 1) << AUDIO_PEQ_23_B1_POS) -#define AUDIO_PEQ_23_B1_UMSK (~(((1U << AUDIO_PEQ_23_B1_LEN) - 1) << AUDIO_PEQ_23_B1_POS)) - -/* 0x3D4 : peq_23_b2 */ -#define AUDIO_PEQ_23_B2_OFFSET (0x3D4) -#define AUDIO_PEQ_23_B2 AUDIO_PEQ_23_B2 -#define AUDIO_PEQ_23_B2_POS (0U) -#define AUDIO_PEQ_23_B2_LEN (20U) -#define AUDIO_PEQ_23_B2_MSK (((1U << AUDIO_PEQ_23_B2_LEN) - 1) << AUDIO_PEQ_23_B2_POS) -#define AUDIO_PEQ_23_B2_UMSK (~(((1U << AUDIO_PEQ_23_B2_LEN) - 1) << AUDIO_PEQ_23_B2_POS)) - -/* 0x3D8 : peq_23_a1 */ -#define AUDIO_PEQ_23_A1_OFFSET (0x3D8) -#define AUDIO_PEQ_23_A1 AUDIO_PEQ_23_A1 -#define AUDIO_PEQ_23_A1_POS (0U) -#define AUDIO_PEQ_23_A1_LEN (20U) -#define AUDIO_PEQ_23_A1_MSK (((1U << AUDIO_PEQ_23_A1_LEN) - 1) << AUDIO_PEQ_23_A1_POS) -#define AUDIO_PEQ_23_A1_UMSK (~(((1U << AUDIO_PEQ_23_A1_LEN) - 1) << AUDIO_PEQ_23_A1_POS)) - -/* 0x3DC : peq_23_a2 */ -#define AUDIO_PEQ_23_A2_OFFSET (0x3DC) -#define AUDIO_PEQ_23_A2 AUDIO_PEQ_23_A2 -#define AUDIO_PEQ_23_A2_POS (0U) -#define AUDIO_PEQ_23_A2_LEN (20U) -#define AUDIO_PEQ_23_A2_MSK (((1U << AUDIO_PEQ_23_A2_LEN) - 1) << AUDIO_PEQ_23_A2_POS) -#define AUDIO_PEQ_23_A2_UMSK (~(((1U << AUDIO_PEQ_23_A2_LEN) - 1) << AUDIO_PEQ_23_A2_POS)) - -/* 0x3E0 : peq_24_b0 */ -#define AUDIO_PEQ_24_B0_OFFSET (0x3E0) -#define AUDIO_PEQ_24_B0 AUDIO_PEQ_24_B0 -#define AUDIO_PEQ_24_B0_POS (0U) -#define AUDIO_PEQ_24_B0_LEN (20U) -#define AUDIO_PEQ_24_B0_MSK (((1U << AUDIO_PEQ_24_B0_LEN) - 1) << AUDIO_PEQ_24_B0_POS) -#define AUDIO_PEQ_24_B0_UMSK (~(((1U << AUDIO_PEQ_24_B0_LEN) - 1) << AUDIO_PEQ_24_B0_POS)) -#define AUDIO_PEQ_24_BYP AUDIO_PEQ_24_BYP -#define AUDIO_PEQ_24_BYP_POS (20U) -#define AUDIO_PEQ_24_BYP_LEN (1U) -#define AUDIO_PEQ_24_BYP_MSK (((1U << AUDIO_PEQ_24_BYP_LEN) - 1) << AUDIO_PEQ_24_BYP_POS) -#define AUDIO_PEQ_24_BYP_UMSK (~(((1U << AUDIO_PEQ_24_BYP_LEN) - 1) << AUDIO_PEQ_24_BYP_POS)) -#define AUDIO_PEQ_24_QFMT AUDIO_PEQ_24_QFMT -#define AUDIO_PEQ_24_QFMT_POS (21U) -#define AUDIO_PEQ_24_QFMT_LEN (1U) -#define AUDIO_PEQ_24_QFMT_MSK (((1U << AUDIO_PEQ_24_QFMT_LEN) - 1) << AUDIO_PEQ_24_QFMT_POS) -#define AUDIO_PEQ_24_QFMT_UMSK (~(((1U << AUDIO_PEQ_24_QFMT_LEN) - 1) << AUDIO_PEQ_24_QFMT_POS)) - -/* 0x3E4 : peq_24_b1 */ -#define AUDIO_PEQ_24_B1_OFFSET (0x3E4) -#define AUDIO_PEQ_24_B1 AUDIO_PEQ_24_B1 -#define AUDIO_PEQ_24_B1_POS (0U) -#define AUDIO_PEQ_24_B1_LEN (20U) -#define AUDIO_PEQ_24_B1_MSK (((1U << AUDIO_PEQ_24_B1_LEN) - 1) << AUDIO_PEQ_24_B1_POS) -#define AUDIO_PEQ_24_B1_UMSK (~(((1U << AUDIO_PEQ_24_B1_LEN) - 1) << AUDIO_PEQ_24_B1_POS)) - -/* 0x3E8 : peq_24_b2 */ -#define AUDIO_PEQ_24_B2_OFFSET (0x3E8) -#define AUDIO_PEQ_24_B2 AUDIO_PEQ_24_B2 -#define AUDIO_PEQ_24_B2_POS (0U) -#define AUDIO_PEQ_24_B2_LEN (20U) -#define AUDIO_PEQ_24_B2_MSK (((1U << AUDIO_PEQ_24_B2_LEN) - 1) << AUDIO_PEQ_24_B2_POS) -#define AUDIO_PEQ_24_B2_UMSK (~(((1U << AUDIO_PEQ_24_B2_LEN) - 1) << AUDIO_PEQ_24_B2_POS)) - -/* 0x3EC : peq_24_a1 */ -#define AUDIO_PEQ_24_A1_OFFSET (0x3EC) -#define AUDIO_PEQ_24_A1 AUDIO_PEQ_24_A1 -#define AUDIO_PEQ_24_A1_POS (0U) -#define AUDIO_PEQ_24_A1_LEN (20U) -#define AUDIO_PEQ_24_A1_MSK (((1U << AUDIO_PEQ_24_A1_LEN) - 1) << AUDIO_PEQ_24_A1_POS) -#define AUDIO_PEQ_24_A1_UMSK (~(((1U << AUDIO_PEQ_24_A1_LEN) - 1) << AUDIO_PEQ_24_A1_POS)) - -/* 0x3F0 : peq_24_a2 */ -#define AUDIO_PEQ_24_A2_OFFSET (0x3F0) -#define AUDIO_PEQ_24_A2 AUDIO_PEQ_24_A2 -#define AUDIO_PEQ_24_A2_POS (0U) -#define AUDIO_PEQ_24_A2_LEN (20U) -#define AUDIO_PEQ_24_A2_MSK (((1U << AUDIO_PEQ_24_A2_LEN) - 1) << AUDIO_PEQ_24_A2_POS) -#define AUDIO_PEQ_24_A2_UMSK (~(((1U << AUDIO_PEQ_24_A2_LEN) - 1) << AUDIO_PEQ_24_A2_POS)) - -/* 0x400 : adc_h */ -#define AUDIO_ADC_H_OFFSET (0x400) -#define AUDIO_ADC_H_CTRL_RMP_RATE AUDIO_ADC_H_CTRL_RMP_RATE -#define AUDIO_ADC_H_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_H_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_H_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_H_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_H_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_H_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_H_CTRL_ZCD_RATE AUDIO_ADC_H_CTRL_ZCD_RATE -#define AUDIO_ADC_H_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_H_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_H_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_H_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_H_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_H_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_H_CTRL_MODE AUDIO_ADC_H_CTRL_MODE -#define AUDIO_ADC_H_CTRL_MODE_POS (10U) -#define AUDIO_ADC_H_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_H_CTRL_MODE_MSK (((1U << AUDIO_ADC_H_CTRL_MODE_LEN) - 1) << AUDIO_ADC_H_CTRL_MODE_POS) -#define AUDIO_ADC_H_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_H_CTRL_MODE_LEN) - 1) << AUDIO_ADC_H_CTRL_MODE_POS)) -#define AUDIO_ADC_H_VOLUME_UPDATE AUDIO_ADC_H_VOLUME_UPDATE -#define AUDIO_ADC_H_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_H_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_H_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_H_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_H_VOLUME_UPDATE_POS) -#define AUDIO_ADC_H_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_H_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_H_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_H_VOLUME AUDIO_ADC_H_VOLUME -#define AUDIO_ADC_H_VOLUME_POS (13U) -#define AUDIO_ADC_H_VOLUME_LEN (9U) -#define AUDIO_ADC_H_VOLUME_MSK (((1U << AUDIO_ADC_H_VOLUME_LEN) - 1) << AUDIO_ADC_H_VOLUME_POS) -#define AUDIO_ADC_H_VOLUME_UMSK (~(((1U << AUDIO_ADC_H_VOLUME_LEN) - 1) << AUDIO_ADC_H_VOLUME_POS)) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE AUDIO_ADC_H_MUTE_RMPUP_RATE -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_H_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_H_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE AUDIO_ADC_H_MUTE_RMPDN_RATE -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_H_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_H_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_H_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_H_MUTE_SOFTMODE AUDIO_ADC_H_MUTE_SOFTMODE -#define AUDIO_ADC_H_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_H_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_H_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_H_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_H_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_H_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_H_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_H_MUTE AUDIO_ADC_H_MUTE -#define AUDIO_ADC_H_MUTE_POS (31U) -#define AUDIO_ADC_H_MUTE_LEN (1U) -#define AUDIO_ADC_H_MUTE_MSK (((1U << AUDIO_ADC_H_MUTE_LEN) - 1) << AUDIO_ADC_H_MUTE_POS) -#define AUDIO_ADC_H_MUTE_UMSK (~(((1U << AUDIO_ADC_H_MUTE_LEN) - 1) << AUDIO_ADC_H_MUTE_POS)) - -/* 0x404 : adc_h_misc */ -#define AUDIO_ADC_H_MISC_OFFSET (0x404) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT AUDIO_ADC_H_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_H_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x408 : adc_s0 */ -#define AUDIO_ADC_S0_OFFSET (0x408) -#define AUDIO_ADC_S0_CTRL_RMP_RATE AUDIO_ADC_S0_CTRL_RMP_RATE -#define AUDIO_ADC_S0_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_S0_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_S0_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_S0_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE AUDIO_ADC_S0_CTRL_ZCD_RATE -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_S0_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_S0_CTRL_MODE AUDIO_ADC_S0_CTRL_MODE -#define AUDIO_ADC_S0_CTRL_MODE_POS (10U) -#define AUDIO_ADC_S0_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_S0_CTRL_MODE_MSK (((1U << AUDIO_ADC_S0_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S0_CTRL_MODE_POS) -#define AUDIO_ADC_S0_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S0_CTRL_MODE_POS)) -#define AUDIO_ADC_S0_VOLUME_UPDATE AUDIO_ADC_S0_VOLUME_UPDATE -#define AUDIO_ADC_S0_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_S0_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S0_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S0_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S0_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S0_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S0_VOLUME AUDIO_ADC_S0_VOLUME -#define AUDIO_ADC_S0_VOLUME_POS (13U) -#define AUDIO_ADC_S0_VOLUME_LEN (9U) -#define AUDIO_ADC_S0_VOLUME_MSK (((1U << AUDIO_ADC_S0_VOLUME_LEN) - 1) << AUDIO_ADC_S0_VOLUME_POS) -#define AUDIO_ADC_S0_VOLUME_UMSK (~(((1U << AUDIO_ADC_S0_VOLUME_LEN) - 1) << AUDIO_ADC_S0_VOLUME_POS)) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE AUDIO_ADC_S0_MUTE_RMPUP_RATE -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_S0_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE AUDIO_ADC_S0_MUTE_RMPDN_RATE -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_S0_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S0_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_S0_MUTE_SOFTMODE AUDIO_ADC_S0_MUTE_SOFTMODE -#define AUDIO_ADC_S0_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_S0_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_S0_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S0_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_S0_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S0_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_S0_MUTE AUDIO_ADC_S0_MUTE -#define AUDIO_ADC_S0_MUTE_POS (31U) -#define AUDIO_ADC_S0_MUTE_LEN (1U) -#define AUDIO_ADC_S0_MUTE_MSK (((1U << AUDIO_ADC_S0_MUTE_LEN) - 1) << AUDIO_ADC_S0_MUTE_POS) -#define AUDIO_ADC_S0_MUTE_UMSK (~(((1U << AUDIO_ADC_S0_MUTE_LEN) - 1) << AUDIO_ADC_S0_MUTE_POS)) - -/* 0x40C : adc_s0_misc */ -#define AUDIO_ADC_S0_MISC_OFFSET (0x40C) -#define AUDIO_ADC_S012_VOLUME_UPDATE AUDIO_ADC_S012_VOLUME_UPDATE -#define AUDIO_ADC_S012_VOLUME_UPDATE_POS (0U) -#define AUDIO_ADC_S012_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S012_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S012_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S012_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S012_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S012_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S012_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S012_MUTE AUDIO_ADC_S012_MUTE -#define AUDIO_ADC_S012_MUTE_POS (1U) -#define AUDIO_ADC_S012_MUTE_LEN (1U) -#define AUDIO_ADC_S012_MUTE_MSK (((1U << AUDIO_ADC_S012_MUTE_LEN) - 1) << AUDIO_ADC_S012_MUTE_POS) -#define AUDIO_ADC_S012_MUTE_UMSK (~(((1U << AUDIO_ADC_S012_MUTE_LEN) - 1) << AUDIO_ADC_S012_MUTE_POS)) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x410 : adc_s1 */ -#define AUDIO_ADC_S1_OFFSET (0x410) -#define AUDIO_ADC_S1_CTRL_RMP_RATE AUDIO_ADC_S1_CTRL_RMP_RATE -#define AUDIO_ADC_S1_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_S1_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_S1_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_S1_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE AUDIO_ADC_S1_CTRL_ZCD_RATE -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_S1_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_S1_CTRL_MODE AUDIO_ADC_S1_CTRL_MODE -#define AUDIO_ADC_S1_CTRL_MODE_POS (10U) -#define AUDIO_ADC_S1_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_S1_CTRL_MODE_MSK (((1U << AUDIO_ADC_S1_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S1_CTRL_MODE_POS) -#define AUDIO_ADC_S1_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S1_CTRL_MODE_POS)) -#define AUDIO_ADC_S1_VOLUME_UPDATE AUDIO_ADC_S1_VOLUME_UPDATE -#define AUDIO_ADC_S1_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_S1_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S1_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S1_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S1_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S1_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S1_VOLUME AUDIO_ADC_S1_VOLUME -#define AUDIO_ADC_S1_VOLUME_POS (13U) -#define AUDIO_ADC_S1_VOLUME_LEN (9U) -#define AUDIO_ADC_S1_VOLUME_MSK (((1U << AUDIO_ADC_S1_VOLUME_LEN) - 1) << AUDIO_ADC_S1_VOLUME_POS) -#define AUDIO_ADC_S1_VOLUME_UMSK (~(((1U << AUDIO_ADC_S1_VOLUME_LEN) - 1) << AUDIO_ADC_S1_VOLUME_POS)) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE AUDIO_ADC_S1_MUTE_RMPUP_RATE -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_S1_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE AUDIO_ADC_S1_MUTE_RMPDN_RATE -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_S1_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S1_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_S1_MUTE_SOFTMODE AUDIO_ADC_S1_MUTE_SOFTMODE -#define AUDIO_ADC_S1_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_S1_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_S1_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S1_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_S1_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S1_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_S1_MUTE AUDIO_ADC_S1_MUTE -#define AUDIO_ADC_S1_MUTE_POS (31U) -#define AUDIO_ADC_S1_MUTE_LEN (1U) -#define AUDIO_ADC_S1_MUTE_MSK (((1U << AUDIO_ADC_S1_MUTE_LEN) - 1) << AUDIO_ADC_S1_MUTE_POS) -#define AUDIO_ADC_S1_MUTE_UMSK (~(((1U << AUDIO_ADC_S1_MUTE_LEN) - 1) << AUDIO_ADC_S1_MUTE_POS)) - -/* 0x414 : adc_s1_misc */ -#define AUDIO_ADC_S1_MISC_OFFSET (0x414) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S1_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x418 : adc_s2 */ -#define AUDIO_ADC_S2_OFFSET (0x418) -#define AUDIO_ADC_S2_CTRL_RMP_RATE AUDIO_ADC_S2_CTRL_RMP_RATE -#define AUDIO_ADC_S2_CTRL_RMP_RATE_POS (2U) -#define AUDIO_ADC_S2_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_ADC_S2_CTRL_RMP_RATE_MSK (((1U << AUDIO_ADC_S2_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_RMP_RATE_POS) -#define AUDIO_ADC_S2_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_RMP_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_RMP_RATE_POS)) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE AUDIO_ADC_S2_CTRL_ZCD_RATE -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_MSK (((1U << AUDIO_ADC_S2_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_RATE_POS) -#define AUDIO_ADC_S2_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_RATE_POS)) -#define AUDIO_ADC_S2_CTRL_MODE AUDIO_ADC_S2_CTRL_MODE -#define AUDIO_ADC_S2_CTRL_MODE_POS (10U) -#define AUDIO_ADC_S2_CTRL_MODE_LEN (2U) -#define AUDIO_ADC_S2_CTRL_MODE_MSK (((1U << AUDIO_ADC_S2_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S2_CTRL_MODE_POS) -#define AUDIO_ADC_S2_CTRL_MODE_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_MODE_LEN) - 1) << AUDIO_ADC_S2_CTRL_MODE_POS)) -#define AUDIO_ADC_S2_VOLUME_UPDATE AUDIO_ADC_S2_VOLUME_UPDATE -#define AUDIO_ADC_S2_VOLUME_UPDATE_POS (12U) -#define AUDIO_ADC_S2_VOLUME_UPDATE_LEN (1U) -#define AUDIO_ADC_S2_VOLUME_UPDATE_MSK (((1U << AUDIO_ADC_S2_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S2_VOLUME_UPDATE_POS) -#define AUDIO_ADC_S2_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_ADC_S2_VOLUME_UPDATE_LEN) - 1) << AUDIO_ADC_S2_VOLUME_UPDATE_POS)) -#define AUDIO_ADC_S2_VOLUME AUDIO_ADC_S2_VOLUME -#define AUDIO_ADC_S2_VOLUME_POS (13U) -#define AUDIO_ADC_S2_VOLUME_LEN (9U) -#define AUDIO_ADC_S2_VOLUME_MSK (((1U << AUDIO_ADC_S2_VOLUME_LEN) - 1) << AUDIO_ADC_S2_VOLUME_POS) -#define AUDIO_ADC_S2_VOLUME_UMSK (~(((1U << AUDIO_ADC_S2_VOLUME_LEN) - 1) << AUDIO_ADC_S2_VOLUME_POS)) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE AUDIO_ADC_S2_MUTE_RMPUP_RATE -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_ADC_S2_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPUP_RATE_POS) -#define AUDIO_ADC_S2_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPUP_RATE_POS)) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE AUDIO_ADC_S2_MUTE_RMPDN_RATE -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_ADC_S2_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPDN_RATE_POS) -#define AUDIO_ADC_S2_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_ADC_S2_MUTE_RMPDN_RATE_POS)) -#define AUDIO_ADC_S2_MUTE_SOFTMODE AUDIO_ADC_S2_MUTE_SOFTMODE -#define AUDIO_ADC_S2_MUTE_SOFTMODE_POS (30U) -#define AUDIO_ADC_S2_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_ADC_S2_MUTE_SOFTMODE_MSK (((1U << AUDIO_ADC_S2_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S2_MUTE_SOFTMODE_POS) -#define AUDIO_ADC_S2_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_SOFTMODE_LEN) - 1) << AUDIO_ADC_S2_MUTE_SOFTMODE_POS)) -#define AUDIO_ADC_S2_MUTE AUDIO_ADC_S2_MUTE -#define AUDIO_ADC_S2_MUTE_POS (31U) -#define AUDIO_ADC_S2_MUTE_LEN (1U) -#define AUDIO_ADC_S2_MUTE_MSK (((1U << AUDIO_ADC_S2_MUTE_LEN) - 1) << AUDIO_ADC_S2_MUTE_POS) -#define AUDIO_ADC_S2_MUTE_UMSK (~(((1U << AUDIO_ADC_S2_MUTE_LEN) - 1) << AUDIO_ADC_S2_MUTE_POS)) - -/* 0x41C : adc_s2_misc */ -#define AUDIO_ADC_S2_MISC_OFFSET (0x41C) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_ADC_S2_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x420 : adc_agc_0 */ -#define AUDIO_ADC_AGC_0_OFFSET (0x420) -#define AUDIO_ADC_AGC_EN AUDIO_ADC_AGC_EN -#define AUDIO_ADC_AGC_EN_POS (0U) -#define AUDIO_ADC_AGC_EN_LEN (1U) -#define AUDIO_ADC_AGC_EN_MSK (((1U << AUDIO_ADC_AGC_EN_LEN) - 1) << AUDIO_ADC_AGC_EN_POS) -#define AUDIO_ADC_AGC_EN_UMSK (~(((1U << AUDIO_ADC_AGC_EN_LEN) - 1) << AUDIO_ADC_AGC_EN_POS)) -#define AUDIO_AGC_MIN_GAIN_QDB AUDIO_AGC_MIN_GAIN_QDB -#define AUDIO_AGC_MIN_GAIN_QDB_POS (3U) -#define AUDIO_AGC_MIN_GAIN_QDB_LEN (9U) -#define AUDIO_AGC_MIN_GAIN_QDB_MSK (((1U << AUDIO_AGC_MIN_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MIN_GAIN_QDB_POS) -#define AUDIO_AGC_MIN_GAIN_QDB_UMSK (~(((1U << AUDIO_AGC_MIN_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MIN_GAIN_QDB_POS)) -#define AUDIO_AGC_MAX_GAIN_QDB AUDIO_AGC_MAX_GAIN_QDB -#define AUDIO_AGC_MAX_GAIN_QDB_POS (12U) -#define AUDIO_AGC_MAX_GAIN_QDB_LEN (9U) -#define AUDIO_AGC_MAX_GAIN_QDB_MSK (((1U << AUDIO_AGC_MAX_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MAX_GAIN_QDB_POS) -#define AUDIO_AGC_MAX_GAIN_QDB_UMSK (~(((1U << AUDIO_AGC_MAX_GAIN_QDB_LEN) - 1) << AUDIO_AGC_MAX_GAIN_QDB_POS)) -#define AUDIO_AGC_FORCE_GAIN_IND AUDIO_AGC_FORCE_GAIN_IND -#define AUDIO_AGC_FORCE_GAIN_IND_POS (21U) -#define AUDIO_AGC_FORCE_GAIN_IND_LEN (10U) -#define AUDIO_AGC_FORCE_GAIN_IND_MSK (((1U << AUDIO_AGC_FORCE_GAIN_IND_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_IND_POS) -#define AUDIO_AGC_FORCE_GAIN_IND_UMSK (~(((1U << AUDIO_AGC_FORCE_GAIN_IND_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_IND_POS)) -#define AUDIO_AGC_FORCE_GAIN_EN AUDIO_AGC_FORCE_GAIN_EN -#define AUDIO_AGC_FORCE_GAIN_EN_POS (31U) -#define AUDIO_AGC_FORCE_GAIN_EN_LEN (1U) -#define AUDIO_AGC_FORCE_GAIN_EN_MSK (((1U << AUDIO_AGC_FORCE_GAIN_EN_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_EN_POS) -#define AUDIO_AGC_FORCE_GAIN_EN_UMSK (~(((1U << AUDIO_AGC_FORCE_GAIN_EN_LEN) - 1) << AUDIO_AGC_FORCE_GAIN_EN_POS)) - -/* 0x424 : adc_agc_1 */ -#define AUDIO_ADC_AGC_1_OFFSET (0x424) -#define AUDIO_ADC0_PGA_HW_CTRL AUDIO_ADC0_PGA_HW_CTRL -#define AUDIO_ADC0_PGA_HW_CTRL_POS (0U) -#define AUDIO_ADC0_PGA_HW_CTRL_LEN (1U) -#define AUDIO_ADC0_PGA_HW_CTRL_MSK (((1U << AUDIO_ADC0_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC0_PGA_HW_CTRL_POS) -#define AUDIO_ADC0_PGA_HW_CTRL_UMSK (~(((1U << AUDIO_ADC0_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC0_PGA_HW_CTRL_POS)) -#define AUDIO_ADC1_PGA_HW_CTRL AUDIO_ADC1_PGA_HW_CTRL -#define AUDIO_ADC1_PGA_HW_CTRL_POS (1U) -#define AUDIO_ADC1_PGA_HW_CTRL_LEN (1U) -#define AUDIO_ADC1_PGA_HW_CTRL_MSK (((1U << AUDIO_ADC1_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC1_PGA_HW_CTRL_POS) -#define AUDIO_ADC1_PGA_HW_CTRL_UMSK (~(((1U << AUDIO_ADC1_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC1_PGA_HW_CTRL_POS)) -#define AUDIO_ADC2_PGA_HW_CTRL AUDIO_ADC2_PGA_HW_CTRL -#define AUDIO_ADC2_PGA_HW_CTRL_POS (2U) -#define AUDIO_ADC2_PGA_HW_CTRL_LEN (1U) -#define AUDIO_ADC2_PGA_HW_CTRL_MSK (((1U << AUDIO_ADC2_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC2_PGA_HW_CTRL_POS) -#define AUDIO_ADC2_PGA_HW_CTRL_UMSK (~(((1U << AUDIO_ADC2_PGA_HW_CTRL_LEN) - 1) << AUDIO_ADC2_PGA_HW_CTRL_POS)) -#define AUDIO_AGC_ATTACK_TIME_MS AUDIO_AGC_ATTACK_TIME_MS -#define AUDIO_AGC_ATTACK_TIME_MS_POS (4U) -#define AUDIO_AGC_ATTACK_TIME_MS_LEN (4U) -#define AUDIO_AGC_ATTACK_TIME_MS_MSK (((1U << AUDIO_AGC_ATTACK_TIME_MS_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_MS_POS) -#define AUDIO_AGC_ATTACK_TIME_MS_UMSK (~(((1U << AUDIO_AGC_ATTACK_TIME_MS_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_MS_POS)) -#define AUDIO_AGC_DECAY_TIME_MS AUDIO_AGC_DECAY_TIME_MS -#define AUDIO_AGC_DECAY_TIME_MS_POS (8U) -#define AUDIO_AGC_DECAY_TIME_MS_LEN (4U) -#define AUDIO_AGC_DECAY_TIME_MS_MSK (((1U << AUDIO_AGC_DECAY_TIME_MS_LEN) - 1) << AUDIO_AGC_DECAY_TIME_MS_POS) -#define AUDIO_AGC_DECAY_TIME_MS_UMSK (~(((1U << AUDIO_AGC_DECAY_TIME_MS_LEN) - 1) << AUDIO_AGC_DECAY_TIME_MS_POS)) -#define AUDIO_AGC_HOLD_TIME_MS AUDIO_AGC_HOLD_TIME_MS -#define AUDIO_AGC_HOLD_TIME_MS_POS (12U) -#define AUDIO_AGC_HOLD_TIME_MS_LEN (4U) -#define AUDIO_AGC_HOLD_TIME_MS_MSK (((1U << AUDIO_AGC_HOLD_TIME_MS_LEN) - 1) << AUDIO_AGC_HOLD_TIME_MS_POS) -#define AUDIO_AGC_HOLD_TIME_MS_UMSK (~(((1U << AUDIO_AGC_HOLD_TIME_MS_LEN) - 1) << AUDIO_AGC_HOLD_TIME_MS_POS)) -#define AUDIO_AGC_LEVEL_HYST_DECAY AUDIO_AGC_LEVEL_HYST_DECAY -#define AUDIO_AGC_LEVEL_HYST_DECAY_POS (16U) -#define AUDIO_AGC_LEVEL_HYST_DECAY_LEN (5U) -#define AUDIO_AGC_LEVEL_HYST_DECAY_MSK (((1U << AUDIO_AGC_LEVEL_HYST_DECAY_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_DECAY_POS) -#define AUDIO_AGC_LEVEL_HYST_DECAY_UMSK (~(((1U << AUDIO_AGC_LEVEL_HYST_DECAY_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_DECAY_POS)) -#define AUDIO_AGC_LEVEL_HYST_ATTACK AUDIO_AGC_LEVEL_HYST_ATTACK -#define AUDIO_AGC_LEVEL_HYST_ATTACK_POS (21U) -#define AUDIO_AGC_LEVEL_HYST_ATTACK_LEN (5U) -#define AUDIO_AGC_LEVEL_HYST_ATTACK_MSK (((1U << AUDIO_AGC_LEVEL_HYST_ATTACK_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_ATTACK_POS) -#define AUDIO_AGC_LEVEL_HYST_ATTACK_UMSK (~(((1U << AUDIO_AGC_LEVEL_HYST_ATTACK_LEN) - 1) << AUDIO_AGC_LEVEL_HYST_ATTACK_POS)) -#define AUDIO_AGC_LEVEL_TARGET AUDIO_AGC_LEVEL_TARGET -#define AUDIO_AGC_LEVEL_TARGET_POS (26U) -#define AUDIO_AGC_LEVEL_TARGET_LEN (6U) -#define AUDIO_AGC_LEVEL_TARGET_MSK (((1U << AUDIO_AGC_LEVEL_TARGET_LEN) - 1) << AUDIO_AGC_LEVEL_TARGET_POS) -#define AUDIO_AGC_LEVEL_TARGET_UMSK (~(((1U << AUDIO_AGC_LEVEL_TARGET_LEN) - 1) << AUDIO_AGC_LEVEL_TARGET_POS)) - -/* 0x428 : adc_agc_2 */ -#define AUDIO_ADC_AGC_2_OFFSET (0x428) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS AUDIO_AGC_NOISE_ENTER_TIME_MS -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_POS (0U) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_LEN (7U) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_MSK (((1U << AUDIO_AGC_NOISE_ENTER_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_ENTER_TIME_MS_POS) -#define AUDIO_AGC_NOISE_ENTER_TIME_MS_UMSK (~(((1U << AUDIO_AGC_NOISE_ENTER_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_ENTER_TIME_MS_POS)) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS AUDIO_AGC_SILENCE_GAIN_WAIT_MS -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_POS (7U) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_LEN (4U) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_MSK (((1U << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_POS) -#define AUDIO_AGC_SILENCE_GAIN_WAIT_MS_UMSK (~(((1U << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_WAIT_MS_POS)) -#define AUDIO_AGC_SILENCE_GAIN_QDB AUDIO_AGC_SILENCE_GAIN_QDB -#define AUDIO_AGC_SILENCE_GAIN_QDB_POS (11U) -#define AUDIO_AGC_SILENCE_GAIN_QDB_LEN (10U) -#define AUDIO_AGC_SILENCE_GAIN_QDB_MSK (((1U << AUDIO_AGC_SILENCE_GAIN_QDB_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_QDB_POS) -#define AUDIO_AGC_SILENCE_GAIN_QDB_UMSK (~(((1U << AUDIO_AGC_SILENCE_GAIN_QDB_LEN) - 1) << AUDIO_AGC_SILENCE_GAIN_QDB_POS)) -#define AUDIO_AGC_NOISE_GATE_HYST AUDIO_AGC_NOISE_GATE_HYST -#define AUDIO_AGC_NOISE_GATE_HYST_POS (21U) -#define AUDIO_AGC_NOISE_GATE_HYST_LEN (3U) -#define AUDIO_AGC_NOISE_GATE_HYST_MSK (((1U << AUDIO_AGC_NOISE_GATE_HYST_LEN) - 1) << AUDIO_AGC_NOISE_GATE_HYST_POS) -#define AUDIO_AGC_NOISE_GATE_HYST_UMSK (~(((1U << AUDIO_AGC_NOISE_GATE_HYST_LEN) - 1) << AUDIO_AGC_NOISE_GATE_HYST_POS)) -#define AUDIO_AGC_NOISE_GATE_TH AUDIO_AGC_NOISE_GATE_TH -#define AUDIO_AGC_NOISE_GATE_TH_POS (24U) -#define AUDIO_AGC_NOISE_GATE_TH_LEN (8U) -#define AUDIO_AGC_NOISE_GATE_TH_MSK (((1U << AUDIO_AGC_NOISE_GATE_TH_LEN) - 1) << AUDIO_AGC_NOISE_GATE_TH_POS) -#define AUDIO_AGC_NOISE_GATE_TH_UMSK (~(((1U << AUDIO_AGC_NOISE_GATE_TH_LEN) - 1) << AUDIO_AGC_NOISE_GATE_TH_POS)) - -/* 0x42C : adc_agc_3 */ -#define AUDIO_ADC_AGC_3_OFFSET (0x42C) -#define AUDIO_AGC_PGA_CTRL_EN AUDIO_AGC_PGA_CTRL_EN -#define AUDIO_AGC_PGA_CTRL_EN_POS (2U) -#define AUDIO_AGC_PGA_CTRL_EN_LEN (1U) -#define AUDIO_AGC_PGA_CTRL_EN_MSK (((1U << AUDIO_AGC_PGA_CTRL_EN_LEN) - 1) << AUDIO_AGC_PGA_CTRL_EN_POS) -#define AUDIO_AGC_PGA_CTRL_EN_UMSK (~(((1U << AUDIO_AGC_PGA_CTRL_EN_LEN) - 1) << AUDIO_AGC_PGA_CTRL_EN_POS)) -#define AUDIO_AGC_AVERAGE_TIME AUDIO_AGC_AVERAGE_TIME -#define AUDIO_AGC_AVERAGE_TIME_POS (3U) -#define AUDIO_AGC_AVERAGE_TIME_LEN (5U) -#define AUDIO_AGC_AVERAGE_TIME_MSK (((1U << AUDIO_AGC_AVERAGE_TIME_LEN) - 1) << AUDIO_AGC_AVERAGE_TIME_POS) -#define AUDIO_AGC_AVERAGE_TIME_UMSK (~(((1U << AUDIO_AGC_AVERAGE_TIME_LEN) - 1) << AUDIO_AGC_AVERAGE_TIME_POS)) -#define AUDIO_AGC_RELEASE_TIME AUDIO_AGC_RELEASE_TIME -#define AUDIO_AGC_RELEASE_TIME_POS (8U) -#define AUDIO_AGC_RELEASE_TIME_LEN (5U) -#define AUDIO_AGC_RELEASE_TIME_MSK (((1U << AUDIO_AGC_RELEASE_TIME_LEN) - 1) << AUDIO_AGC_RELEASE_TIME_POS) -#define AUDIO_AGC_RELEASE_TIME_UMSK (~(((1U << AUDIO_AGC_RELEASE_TIME_LEN) - 1) << AUDIO_AGC_RELEASE_TIME_POS)) -#define AUDIO_AGC_ATTACK_TIME AUDIO_AGC_ATTACK_TIME -#define AUDIO_AGC_ATTACK_TIME_POS (13U) -#define AUDIO_AGC_ATTACK_TIME_LEN (5U) -#define AUDIO_AGC_ATTACK_TIME_MSK (((1U << AUDIO_AGC_ATTACK_TIME_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_POS) -#define AUDIO_AGC_ATTACK_TIME_UMSK (~(((1U << AUDIO_AGC_ATTACK_TIME_LEN) - 1) << AUDIO_AGC_ATTACK_TIME_POS)) -#define AUDIO_AGC_DETECT_MODE AUDIO_AGC_DETECT_MODE -#define AUDIO_AGC_DETECT_MODE_POS (18U) -#define AUDIO_AGC_DETECT_MODE_LEN (1U) -#define AUDIO_AGC_DETECT_MODE_MSK (((1U << AUDIO_AGC_DETECT_MODE_LEN) - 1) << AUDIO_AGC_DETECT_MODE_POS) -#define AUDIO_AGC_DETECT_MODE_UMSK (~(((1U << AUDIO_AGC_DETECT_MODE_LEN) - 1) << AUDIO_AGC_DETECT_MODE_POS)) -#define AUDIO_AGC_SRC_SELECT AUDIO_AGC_SRC_SELECT -#define AUDIO_AGC_SRC_SELECT_POS (19U) -#define AUDIO_AGC_SRC_SELECT_LEN (2U) -#define AUDIO_AGC_SRC_SELECT_MSK (((1U << AUDIO_AGC_SRC_SELECT_LEN) - 1) << AUDIO_AGC_SRC_SELECT_POS) -#define AUDIO_AGC_SRC_SELECT_UMSK (~(((1U << AUDIO_AGC_SRC_SELECT_LEN) - 1) << AUDIO_AGC_SRC_SELECT_POS)) -#define AUDIO_AGC_DBV_SETTLE_TIME AUDIO_AGC_DBV_SETTLE_TIME -#define AUDIO_AGC_DBV_SETTLE_TIME_POS (21U) -#define AUDIO_AGC_DBV_SETTLE_TIME_LEN (4U) -#define AUDIO_AGC_DBV_SETTLE_TIME_MSK (((1U << AUDIO_AGC_DBV_SETTLE_TIME_LEN) - 1) << AUDIO_AGC_DBV_SETTLE_TIME_POS) -#define AUDIO_AGC_DBV_SETTLE_TIME_UMSK (~(((1U << AUDIO_AGC_DBV_SETTLE_TIME_LEN) - 1) << AUDIO_AGC_DBV_SETTLE_TIME_POS)) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS AUDIO_AGC_NOISE_EXIT_TIME_MS -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_POS (25U) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_LEN (7U) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_MSK (((1U << AUDIO_AGC_NOISE_EXIT_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_EXIT_TIME_MS_POS) -#define AUDIO_AGC_NOISE_EXIT_TIME_MS_UMSK (~(((1U << AUDIO_AGC_NOISE_EXIT_TIME_MS_LEN) - 1) << AUDIO_AGC_NOISE_EXIT_TIME_MS_POS)) - -/* 0x430 : audio_status */ -#define AUDIO_STATUS_OFFSET (0x430) -#define AUDIO_ADC_H0_BUSY AUDIO_ADC_H0_BUSY -#define AUDIO_ADC_H0_BUSY_POS (0U) -#define AUDIO_ADC_H0_BUSY_LEN (1U) -#define AUDIO_ADC_H0_BUSY_MSK (((1U << AUDIO_ADC_H0_BUSY_LEN) - 1) << AUDIO_ADC_H0_BUSY_POS) -#define AUDIO_ADC_H0_BUSY_UMSK (~(((1U << AUDIO_ADC_H0_BUSY_LEN) - 1) << AUDIO_ADC_H0_BUSY_POS)) -#define AUDIO_ADC_H0_MUTE_DONE AUDIO_ADC_H0_MUTE_DONE -#define AUDIO_ADC_H0_MUTE_DONE_POS (1U) -#define AUDIO_ADC_H0_MUTE_DONE_LEN (1U) -#define AUDIO_ADC_H0_MUTE_DONE_MSK (((1U << AUDIO_ADC_H0_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H0_MUTE_DONE_POS) -#define AUDIO_ADC_H0_MUTE_DONE_UMSK (~(((1U << AUDIO_ADC_H0_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H0_MUTE_DONE_POS)) -#define AUDIO_ADC_H1_BUSY AUDIO_ADC_H1_BUSY -#define AUDIO_ADC_H1_BUSY_POS (2U) -#define AUDIO_ADC_H1_BUSY_LEN (1U) -#define AUDIO_ADC_H1_BUSY_MSK (((1U << AUDIO_ADC_H1_BUSY_LEN) - 1) << AUDIO_ADC_H1_BUSY_POS) -#define AUDIO_ADC_H1_BUSY_UMSK (~(((1U << AUDIO_ADC_H1_BUSY_LEN) - 1) << AUDIO_ADC_H1_BUSY_POS)) -#define AUDIO_ADC_H1_MUTE_DONE AUDIO_ADC_H1_MUTE_DONE -#define AUDIO_ADC_H1_MUTE_DONE_POS (3U) -#define AUDIO_ADC_H1_MUTE_DONE_LEN (1U) -#define AUDIO_ADC_H1_MUTE_DONE_MSK (((1U << AUDIO_ADC_H1_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H1_MUTE_DONE_POS) -#define AUDIO_ADC_H1_MUTE_DONE_UMSK (~(((1U << AUDIO_ADC_H1_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H1_MUTE_DONE_POS)) -#define AUDIO_ADC_H2_BUSY AUDIO_ADC_H2_BUSY -#define AUDIO_ADC_H2_BUSY_POS (4U) -#define AUDIO_ADC_H2_BUSY_LEN (1U) -#define AUDIO_ADC_H2_BUSY_MSK (((1U << AUDIO_ADC_H2_BUSY_LEN) - 1) << AUDIO_ADC_H2_BUSY_POS) -#define AUDIO_ADC_H2_BUSY_UMSK (~(((1U << AUDIO_ADC_H2_BUSY_LEN) - 1) << AUDIO_ADC_H2_BUSY_POS)) -#define AUDIO_ADC_H2_MUTE_DONE AUDIO_ADC_H2_MUTE_DONE -#define AUDIO_ADC_H2_MUTE_DONE_POS (5U) -#define AUDIO_ADC_H2_MUTE_DONE_LEN (1U) -#define AUDIO_ADC_H2_MUTE_DONE_MSK (((1U << AUDIO_ADC_H2_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H2_MUTE_DONE_POS) -#define AUDIO_ADC_H2_MUTE_DONE_UMSK (~(((1U << AUDIO_ADC_H2_MUTE_DONE_LEN) - 1) << AUDIO_ADC_H2_MUTE_DONE_POS)) -#define AUDIO_ADC_S0_INT AUDIO_ADC_S0_INT -#define AUDIO_ADC_S0_INT_POS (6U) -#define AUDIO_ADC_S0_INT_LEN (1U) -#define AUDIO_ADC_S0_INT_MSK (((1U << AUDIO_ADC_S0_INT_LEN) - 1) << AUDIO_ADC_S0_INT_POS) -#define AUDIO_ADC_S0_INT_UMSK (~(((1U << AUDIO_ADC_S0_INT_LEN) - 1) << AUDIO_ADC_S0_INT_POS)) -#define AUDIO_ADC_S0_INT_CLR AUDIO_ADC_S0_INT_CLR -#define AUDIO_ADC_S0_INT_CLR_POS (7U) -#define AUDIO_ADC_S0_INT_CLR_LEN (1U) -#define AUDIO_ADC_S0_INT_CLR_MSK (((1U << AUDIO_ADC_S0_INT_CLR_LEN) - 1) << AUDIO_ADC_S0_INT_CLR_POS) -#define AUDIO_ADC_S0_INT_CLR_UMSK (~(((1U << AUDIO_ADC_S0_INT_CLR_LEN) - 1) << AUDIO_ADC_S0_INT_CLR_POS)) -#define AUDIO_ADC_S1_INT AUDIO_ADC_S1_INT -#define AUDIO_ADC_S1_INT_POS (8U) -#define AUDIO_ADC_S1_INT_LEN (1U) -#define AUDIO_ADC_S1_INT_MSK (((1U << AUDIO_ADC_S1_INT_LEN) - 1) << AUDIO_ADC_S1_INT_POS) -#define AUDIO_ADC_S1_INT_UMSK (~(((1U << AUDIO_ADC_S1_INT_LEN) - 1) << AUDIO_ADC_S1_INT_POS)) -#define AUDIO_ADC_S1_INT_CLR AUDIO_ADC_S1_INT_CLR -#define AUDIO_ADC_S1_INT_CLR_POS (9U) -#define AUDIO_ADC_S1_INT_CLR_LEN (1U) -#define AUDIO_ADC_S1_INT_CLR_MSK (((1U << AUDIO_ADC_S1_INT_CLR_LEN) - 1) << AUDIO_ADC_S1_INT_CLR_POS) -#define AUDIO_ADC_S1_INT_CLR_UMSK (~(((1U << AUDIO_ADC_S1_INT_CLR_LEN) - 1) << AUDIO_ADC_S1_INT_CLR_POS)) -#define AUDIO_ADC_S2_INT AUDIO_ADC_S2_INT -#define AUDIO_ADC_S2_INT_POS (10U) -#define AUDIO_ADC_S2_INT_LEN (1U) -#define AUDIO_ADC_S2_INT_MSK (((1U << AUDIO_ADC_S2_INT_LEN) - 1) << AUDIO_ADC_S2_INT_POS) -#define AUDIO_ADC_S2_INT_UMSK (~(((1U << AUDIO_ADC_S2_INT_LEN) - 1) << AUDIO_ADC_S2_INT_POS)) -#define AUDIO_ADC_S2_INT_CLR AUDIO_ADC_S2_INT_CLR -#define AUDIO_ADC_S2_INT_CLR_POS (11U) -#define AUDIO_ADC_S2_INT_CLR_LEN (1U) -#define AUDIO_ADC_S2_INT_CLR_MSK (((1U << AUDIO_ADC_S2_INT_CLR_LEN) - 1) << AUDIO_ADC_S2_INT_CLR_POS) -#define AUDIO_ADC_S2_INT_CLR_UMSK (~(((1U << AUDIO_ADC_S2_INT_CLR_LEN) - 1) << AUDIO_ADC_S2_INT_CLR_POS)) -#define AUDIO_DAC_H0_BUSY AUDIO_DAC_H0_BUSY -#define AUDIO_DAC_H0_BUSY_POS (12U) -#define AUDIO_DAC_H0_BUSY_LEN (1U) -#define AUDIO_DAC_H0_BUSY_MSK (((1U << AUDIO_DAC_H0_BUSY_LEN) - 1) << AUDIO_DAC_H0_BUSY_POS) -#define AUDIO_DAC_H0_BUSY_UMSK (~(((1U << AUDIO_DAC_H0_BUSY_LEN) - 1) << AUDIO_DAC_H0_BUSY_POS)) -#define AUDIO_DAC_H0_MUTE_DONE AUDIO_DAC_H0_MUTE_DONE -#define AUDIO_DAC_H0_MUTE_DONE_POS (13U) -#define AUDIO_DAC_H0_MUTE_DONE_LEN (1U) -#define AUDIO_DAC_H0_MUTE_DONE_MSK (((1U << AUDIO_DAC_H0_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H0_MUTE_DONE_POS) -#define AUDIO_DAC_H0_MUTE_DONE_UMSK (~(((1U << AUDIO_DAC_H0_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H0_MUTE_DONE_POS)) -#define AUDIO_DAC_H1_BUSY AUDIO_DAC_H1_BUSY -#define AUDIO_DAC_H1_BUSY_POS (14U) -#define AUDIO_DAC_H1_BUSY_LEN (1U) -#define AUDIO_DAC_H1_BUSY_MSK (((1U << AUDIO_DAC_H1_BUSY_LEN) - 1) << AUDIO_DAC_H1_BUSY_POS) -#define AUDIO_DAC_H1_BUSY_UMSK (~(((1U << AUDIO_DAC_H1_BUSY_LEN) - 1) << AUDIO_DAC_H1_BUSY_POS)) -#define AUDIO_DAC_H1_MUTE_DONE AUDIO_DAC_H1_MUTE_DONE -#define AUDIO_DAC_H1_MUTE_DONE_POS (15U) -#define AUDIO_DAC_H1_MUTE_DONE_LEN (1U) -#define AUDIO_DAC_H1_MUTE_DONE_MSK (((1U << AUDIO_DAC_H1_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H1_MUTE_DONE_POS) -#define AUDIO_DAC_H1_MUTE_DONE_UMSK (~(((1U << AUDIO_DAC_H1_MUTE_DONE_LEN) - 1) << AUDIO_DAC_H1_MUTE_DONE_POS)) -#define AUDIO_DAC_S0_INT AUDIO_DAC_S0_INT -#define AUDIO_DAC_S0_INT_POS (16U) -#define AUDIO_DAC_S0_INT_LEN (1U) -#define AUDIO_DAC_S0_INT_MSK (((1U << AUDIO_DAC_S0_INT_LEN) - 1) << AUDIO_DAC_S0_INT_POS) -#define AUDIO_DAC_S0_INT_UMSK (~(((1U << AUDIO_DAC_S0_INT_LEN) - 1) << AUDIO_DAC_S0_INT_POS)) -#define AUDIO_DAC_S0_INT_CLR AUDIO_DAC_S0_INT_CLR -#define AUDIO_DAC_S0_INT_CLR_POS (17U) -#define AUDIO_DAC_S0_INT_CLR_LEN (1U) -#define AUDIO_DAC_S0_INT_CLR_MSK (((1U << AUDIO_DAC_S0_INT_CLR_LEN) - 1) << AUDIO_DAC_S0_INT_CLR_POS) -#define AUDIO_DAC_S0_INT_CLR_UMSK (~(((1U << AUDIO_DAC_S0_INT_CLR_LEN) - 1) << AUDIO_DAC_S0_INT_CLR_POS)) -#define AUDIO_DAC_S1_INT AUDIO_DAC_S1_INT -#define AUDIO_DAC_S1_INT_POS (18U) -#define AUDIO_DAC_S1_INT_LEN (1U) -#define AUDIO_DAC_S1_INT_MSK (((1U << AUDIO_DAC_S1_INT_LEN) - 1) << AUDIO_DAC_S1_INT_POS) -#define AUDIO_DAC_S1_INT_UMSK (~(((1U << AUDIO_DAC_S1_INT_LEN) - 1) << AUDIO_DAC_S1_INT_POS)) -#define AUDIO_DAC_S1_INT_CLR AUDIO_DAC_S1_INT_CLR -#define AUDIO_DAC_S1_INT_CLR_POS (19U) -#define AUDIO_DAC_S1_INT_CLR_LEN (1U) -#define AUDIO_DAC_S1_INT_CLR_MSK (((1U << AUDIO_DAC_S1_INT_CLR_LEN) - 1) << AUDIO_DAC_S1_INT_CLR_POS) -#define AUDIO_DAC_S1_INT_CLR_UMSK (~(((1U << AUDIO_DAC_S1_INT_CLR_LEN) - 1) << AUDIO_DAC_S1_INT_CLR_POS)) -#define AUDIO_NGT_AMUTE AUDIO_NGT_AMUTE -#define AUDIO_NGT_AMUTE_POS (20U) -#define AUDIO_NGT_AMUTE_LEN (1U) -#define AUDIO_NGT_AMUTE_MSK (((1U << AUDIO_NGT_AMUTE_LEN) - 1) << AUDIO_NGT_AMUTE_POS) -#define AUDIO_NGT_AMUTE_UMSK (~(((1U << AUDIO_NGT_AMUTE_LEN) - 1) << AUDIO_NGT_AMUTE_POS)) -#define AUDIO_NGT_DMUTE AUDIO_NGT_DMUTE -#define AUDIO_NGT_DMUTE_POS (21U) -#define AUDIO_NGT_DMUTE_LEN (1U) -#define AUDIO_NGT_DMUTE_MSK (((1U << AUDIO_NGT_DMUTE_LEN) - 1) << AUDIO_NGT_DMUTE_POS) -#define AUDIO_NGT_DMUTE_UMSK (~(((1U << AUDIO_NGT_DMUTE_LEN) - 1) << AUDIO_NGT_DMUTE_POS)) -#define AUDIO_NGT_DMUTE_DONE AUDIO_NGT_DMUTE_DONE -#define AUDIO_NGT_DMUTE_DONE_POS (22U) -#define AUDIO_NGT_DMUTE_DONE_LEN (1U) -#define AUDIO_NGT_DMUTE_DONE_MSK (((1U << AUDIO_NGT_DMUTE_DONE_LEN) - 1) << AUDIO_NGT_DMUTE_DONE_POS) -#define AUDIO_NGT_DMUTE_DONE_UMSK (~(((1U << AUDIO_NGT_DMUTE_DONE_LEN) - 1) << AUDIO_NGT_DMUTE_DONE_POS)) -#define AUDIO_ZD_AMUTE AUDIO_ZD_AMUTE -#define AUDIO_ZD_AMUTE_POS (23U) -#define AUDIO_ZD_AMUTE_LEN (1U) -#define AUDIO_ZD_AMUTE_MSK (((1U << AUDIO_ZD_AMUTE_LEN) - 1) << AUDIO_ZD_AMUTE_POS) -#define AUDIO_ZD_AMUTE_UMSK (~(((1U << AUDIO_ZD_AMUTE_LEN) - 1) << AUDIO_ZD_AMUTE_POS)) -#define AUDIO_INT_ALL AUDIO_INT_ALL -#define AUDIO_INT_ALL_POS (24U) -#define AUDIO_INT_ALL_LEN (1U) -#define AUDIO_INT_ALL_MSK (((1U << AUDIO_INT_ALL_LEN) - 1) << AUDIO_INT_ALL_POS) -#define AUDIO_INT_ALL_UMSK (~(((1U << AUDIO_INT_ALL_LEN) - 1) << AUDIO_INT_ALL_POS)) -#define AUDIO_VAD_INT AUDIO_VAD_INT -#define AUDIO_VAD_INT_POS (25U) -#define AUDIO_VAD_INT_LEN (1U) -#define AUDIO_VAD_INT_MSK (((1U << AUDIO_VAD_INT_LEN) - 1) << AUDIO_VAD_INT_POS) -#define AUDIO_VAD_INT_UMSK (~(((1U << AUDIO_VAD_INT_LEN) - 1) << AUDIO_VAD_INT_POS)) -#define AUDIO_VAD_INT_CLR AUDIO_VAD_INT_CLR -#define AUDIO_VAD_INT_CLR_POS (26U) -#define AUDIO_VAD_INT_CLR_LEN (1U) -#define AUDIO_VAD_INT_CLR_MSK (((1U << AUDIO_VAD_INT_CLR_LEN) - 1) << AUDIO_VAD_INT_CLR_POS) -#define AUDIO_VAD_INT_CLR_UMSK (~(((1U << AUDIO_VAD_INT_CLR_LEN) - 1) << AUDIO_VAD_INT_CLR_POS)) -#define AUDIO_VAD_INT_SET AUDIO_VAD_INT_SET -#define AUDIO_VAD_INT_SET_POS (27U) -#define AUDIO_VAD_INT_SET_LEN (1U) -#define AUDIO_VAD_INT_SET_MSK (((1U << AUDIO_VAD_INT_SET_LEN) - 1) << AUDIO_VAD_INT_SET_POS) -#define AUDIO_VAD_INT_SET_UMSK (~(((1U << AUDIO_VAD_INT_SET_LEN) - 1) << AUDIO_VAD_INT_SET_POS)) - -/* 0x434 : dac_s0 */ -#define AUDIO_DAC_S0_OFFSET (0x434) -#define AUDIO_DAC_S0_CTRL_RMP_RATE AUDIO_DAC_S0_CTRL_RMP_RATE -#define AUDIO_DAC_S0_CTRL_RMP_RATE_POS (2U) -#define AUDIO_DAC_S0_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_DAC_S0_CTRL_RMP_RATE_MSK (((1U << AUDIO_DAC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_RMP_RATE_POS) -#define AUDIO_DAC_S0_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_RMP_RATE_POS)) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE AUDIO_DAC_S0_CTRL_ZCD_RATE -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_MSK (((1U << AUDIO_DAC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_RATE_POS) -#define AUDIO_DAC_S0_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_RATE_POS)) -#define AUDIO_DAC_S0_CTRL_MODE AUDIO_DAC_S0_CTRL_MODE -#define AUDIO_DAC_S0_CTRL_MODE_POS (10U) -#define AUDIO_DAC_S0_CTRL_MODE_LEN (2U) -#define AUDIO_DAC_S0_CTRL_MODE_MSK (((1U << AUDIO_DAC_S0_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S0_CTRL_MODE_POS) -#define AUDIO_DAC_S0_CTRL_MODE_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S0_CTRL_MODE_POS)) -#define AUDIO_DAC_S0_VOLUME_UPDATE AUDIO_DAC_S0_VOLUME_UPDATE -#define AUDIO_DAC_S0_VOLUME_UPDATE_POS (12U) -#define AUDIO_DAC_S0_VOLUME_UPDATE_LEN (1U) -#define AUDIO_DAC_S0_VOLUME_UPDATE_MSK (((1U << AUDIO_DAC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S0_VOLUME_UPDATE_POS) -#define AUDIO_DAC_S0_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_DAC_S0_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S0_VOLUME_UPDATE_POS)) -#define AUDIO_DAC_S0_VOLUME AUDIO_DAC_S0_VOLUME -#define AUDIO_DAC_S0_VOLUME_POS (13U) -#define AUDIO_DAC_S0_VOLUME_LEN (9U) -#define AUDIO_DAC_S0_VOLUME_MSK (((1U << AUDIO_DAC_S0_VOLUME_LEN) - 1) << AUDIO_DAC_S0_VOLUME_POS) -#define AUDIO_DAC_S0_VOLUME_UMSK (~(((1U << AUDIO_DAC_S0_VOLUME_LEN) - 1) << AUDIO_DAC_S0_VOLUME_POS)) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE AUDIO_DAC_S0_MUTE_RMPUP_RATE -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_DAC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPUP_RATE_POS) -#define AUDIO_DAC_S0_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPUP_RATE_POS)) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE AUDIO_DAC_S0_MUTE_RMPDN_RATE -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_DAC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPDN_RATE_POS) -#define AUDIO_DAC_S0_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S0_MUTE_RMPDN_RATE_POS)) -#define AUDIO_DAC_S0_MUTE_SOFTMODE AUDIO_DAC_S0_MUTE_SOFTMODE -#define AUDIO_DAC_S0_MUTE_SOFTMODE_POS (30U) -#define AUDIO_DAC_S0_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_DAC_S0_MUTE_SOFTMODE_MSK (((1U << AUDIO_DAC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S0_MUTE_SOFTMODE_POS) -#define AUDIO_DAC_S0_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S0_MUTE_SOFTMODE_POS)) -#define AUDIO_DAC_S0_MUTE AUDIO_DAC_S0_MUTE -#define AUDIO_DAC_S0_MUTE_POS (31U) -#define AUDIO_DAC_S0_MUTE_LEN (1U) -#define AUDIO_DAC_S0_MUTE_MSK (((1U << AUDIO_DAC_S0_MUTE_LEN) - 1) << AUDIO_DAC_S0_MUTE_POS) -#define AUDIO_DAC_S0_MUTE_UMSK (~(((1U << AUDIO_DAC_S0_MUTE_LEN) - 1) << AUDIO_DAC_S0_MUTE_POS)) - -/* 0x438 : dac_s0_misc */ -#define AUDIO_DAC_S0_MISC_OFFSET (0x438) -#define AUDIO_DAC_S01_VOLUME_UPDATE AUDIO_DAC_S01_VOLUME_UPDATE -#define AUDIO_DAC_S01_VOLUME_UPDATE_POS (0U) -#define AUDIO_DAC_S01_VOLUME_UPDATE_LEN (1U) -#define AUDIO_DAC_S01_VOLUME_UPDATE_MSK (((1U << AUDIO_DAC_S01_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S01_VOLUME_UPDATE_POS) -#define AUDIO_DAC_S01_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_DAC_S01_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S01_VOLUME_UPDATE_POS)) -#define AUDIO_DAC_S01_MUTE AUDIO_DAC_S01_MUTE -#define AUDIO_DAC_S01_MUTE_POS (1U) -#define AUDIO_DAC_S01_MUTE_LEN (1U) -#define AUDIO_DAC_S01_MUTE_MSK (((1U << AUDIO_DAC_S01_MUTE_LEN) - 1) << AUDIO_DAC_S01_MUTE_POS) -#define AUDIO_DAC_S01_MUTE_UMSK (~(((1U << AUDIO_DAC_S01_MUTE_LEN) - 1) << AUDIO_DAC_S01_MUTE_POS)) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x43C : dac_s1 */ -#define AUDIO_DAC_S1_OFFSET (0x43C) -#define AUDIO_DAC_S1_CTRL_RMP_RATE AUDIO_DAC_S1_CTRL_RMP_RATE -#define AUDIO_DAC_S1_CTRL_RMP_RATE_POS (2U) -#define AUDIO_DAC_S1_CTRL_RMP_RATE_LEN (4U) -#define AUDIO_DAC_S1_CTRL_RMP_RATE_MSK (((1U << AUDIO_DAC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_RMP_RATE_POS) -#define AUDIO_DAC_S1_CTRL_RMP_RATE_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_RMP_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_RMP_RATE_POS)) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE AUDIO_DAC_S1_CTRL_ZCD_RATE -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_POS (6U) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_LEN (4U) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_MSK (((1U << AUDIO_DAC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_RATE_POS) -#define AUDIO_DAC_S1_CTRL_ZCD_RATE_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_ZCD_RATE_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_RATE_POS)) -#define AUDIO_DAC_S1_CTRL_MODE AUDIO_DAC_S1_CTRL_MODE -#define AUDIO_DAC_S1_CTRL_MODE_POS (10U) -#define AUDIO_DAC_S1_CTRL_MODE_LEN (2U) -#define AUDIO_DAC_S1_CTRL_MODE_MSK (((1U << AUDIO_DAC_S1_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S1_CTRL_MODE_POS) -#define AUDIO_DAC_S1_CTRL_MODE_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_MODE_LEN) - 1) << AUDIO_DAC_S1_CTRL_MODE_POS)) -#define AUDIO_DAC_S1_VOLUME_UPDATE AUDIO_DAC_S1_VOLUME_UPDATE -#define AUDIO_DAC_S1_VOLUME_UPDATE_POS (12U) -#define AUDIO_DAC_S1_VOLUME_UPDATE_LEN (1U) -#define AUDIO_DAC_S1_VOLUME_UPDATE_MSK (((1U << AUDIO_DAC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S1_VOLUME_UPDATE_POS) -#define AUDIO_DAC_S1_VOLUME_UPDATE_UMSK (~(((1U << AUDIO_DAC_S1_VOLUME_UPDATE_LEN) - 1) << AUDIO_DAC_S1_VOLUME_UPDATE_POS)) -#define AUDIO_DAC_S1_VOLUME AUDIO_DAC_S1_VOLUME -#define AUDIO_DAC_S1_VOLUME_POS (13U) -#define AUDIO_DAC_S1_VOLUME_LEN (9U) -#define AUDIO_DAC_S1_VOLUME_MSK (((1U << AUDIO_DAC_S1_VOLUME_LEN) - 1) << AUDIO_DAC_S1_VOLUME_POS) -#define AUDIO_DAC_S1_VOLUME_UMSK (~(((1U << AUDIO_DAC_S1_VOLUME_LEN) - 1) << AUDIO_DAC_S1_VOLUME_POS)) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE AUDIO_DAC_S1_MUTE_RMPUP_RATE -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_POS (22U) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_LEN (4U) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_MSK (((1U << AUDIO_DAC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPUP_RATE_POS) -#define AUDIO_DAC_S1_MUTE_RMPUP_RATE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_RMPUP_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPUP_RATE_POS)) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE AUDIO_DAC_S1_MUTE_RMPDN_RATE -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_POS (26U) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_LEN (4U) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_MSK (((1U << AUDIO_DAC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPDN_RATE_POS) -#define AUDIO_DAC_S1_MUTE_RMPDN_RATE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_RMPDN_RATE_LEN) - 1) << AUDIO_DAC_S1_MUTE_RMPDN_RATE_POS)) -#define AUDIO_DAC_S1_MUTE_SOFTMODE AUDIO_DAC_S1_MUTE_SOFTMODE -#define AUDIO_DAC_S1_MUTE_SOFTMODE_POS (30U) -#define AUDIO_DAC_S1_MUTE_SOFTMODE_LEN (1U) -#define AUDIO_DAC_S1_MUTE_SOFTMODE_MSK (((1U << AUDIO_DAC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S1_MUTE_SOFTMODE_POS) -#define AUDIO_DAC_S1_MUTE_SOFTMODE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_SOFTMODE_LEN) - 1) << AUDIO_DAC_S1_MUTE_SOFTMODE_POS)) -#define AUDIO_DAC_S1_MUTE AUDIO_DAC_S1_MUTE -#define AUDIO_DAC_S1_MUTE_POS (31U) -#define AUDIO_DAC_S1_MUTE_LEN (1U) -#define AUDIO_DAC_S1_MUTE_MSK (((1U << AUDIO_DAC_S1_MUTE_LEN) - 1) << AUDIO_DAC_S1_MUTE_POS) -#define AUDIO_DAC_S1_MUTE_UMSK (~(((1U << AUDIO_DAC_S1_MUTE_LEN) - 1) << AUDIO_DAC_S1_MUTE_POS)) - -/* 0x440 : dac_s1_misc */ -#define AUDIO_DAC_S1_MISC_OFFSET (0x440) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_POS (28U) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_LEN (4U) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_MSK (((1U << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_POS) -#define AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_UMSK (~(((1U << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_LEN) - 1) << AUDIO_DAC_S1_CTRL_ZCD_TIMEOUT_POS)) - -/* 0x444 : dac_drc_0 */ -#define AUDIO_DAC_DRC_0_OFFSET (0x444) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN AUDIO_DRC_NGT_DOWNSAMPLE_EN -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_POS (8U) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_LEN (1U) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_MSK (((1U << AUDIO_DRC_NGT_DOWNSAMPLE_EN_LEN) - 1) << AUDIO_DRC_NGT_DOWNSAMPLE_EN_POS) -#define AUDIO_DRC_NGT_DOWNSAMPLE_EN_UMSK (~(((1U << AUDIO_DRC_NGT_DOWNSAMPLE_EN_LEN) - 1) << AUDIO_DRC_NGT_DOWNSAMPLE_EN_POS)) -#define AUDIO_DRC_RLS_TIME AUDIO_DRC_RLS_TIME -#define AUDIO_DRC_RLS_TIME_POS (9U) -#define AUDIO_DRC_RLS_TIME_LEN (5U) -#define AUDIO_DRC_RLS_TIME_MSK (((1U << AUDIO_DRC_RLS_TIME_LEN) - 1) << AUDIO_DRC_RLS_TIME_POS) -#define AUDIO_DRC_RLS_TIME_UMSK (~(((1U << AUDIO_DRC_RLS_TIME_LEN) - 1) << AUDIO_DRC_RLS_TIME_POS)) -#define AUDIO_DRC_ATT_TIME AUDIO_DRC_ATT_TIME -#define AUDIO_DRC_ATT_TIME_POS (14U) -#define AUDIO_DRC_ATT_TIME_LEN (5U) -#define AUDIO_DRC_ATT_TIME_MSK (((1U << AUDIO_DRC_ATT_TIME_LEN) - 1) << AUDIO_DRC_ATT_TIME_POS) -#define AUDIO_DRC_ATT_TIME_UMSK (~(((1U << AUDIO_DRC_ATT_TIME_LEN) - 1) << AUDIO_DRC_ATT_TIME_POS)) -#define AUDIO_DRC_AVG_TIME AUDIO_DRC_AVG_TIME -#define AUDIO_DRC_AVG_TIME_POS (19U) -#define AUDIO_DRC_AVG_TIME_LEN (5U) -#define AUDIO_DRC_AVG_TIME_MSK (((1U << AUDIO_DRC_AVG_TIME_LEN) - 1) << AUDIO_DRC_AVG_TIME_POS) -#define AUDIO_DRC_AVG_TIME_UMSK (~(((1U << AUDIO_DRC_AVG_TIME_LEN) - 1) << AUDIO_DRC_AVG_TIME_POS)) -#define AUDIO_DRC_AVG_EN AUDIO_DRC_AVG_EN -#define AUDIO_DRC_AVG_EN_POS (24U) -#define AUDIO_DRC_AVG_EN_LEN (1U) -#define AUDIO_DRC_AVG_EN_MSK (((1U << AUDIO_DRC_AVG_EN_LEN) - 1) << AUDIO_DRC_AVG_EN_POS) -#define AUDIO_DRC_AVG_EN_UMSK (~(((1U << AUDIO_DRC_AVG_EN_LEN) - 1) << AUDIO_DRC_AVG_EN_POS)) -#define AUDIO_DRC_AVG_SEL AUDIO_DRC_AVG_SEL -#define AUDIO_DRC_AVG_SEL_POS (25U) -#define AUDIO_DRC_AVG_SEL_LEN (2U) -#define AUDIO_DRC_AVG_SEL_MSK (((1U << AUDIO_DRC_AVG_SEL_LEN) - 1) << AUDIO_DRC_AVG_SEL_POS) -#define AUDIO_DRC_AVG_SEL_UMSK (~(((1U << AUDIO_DRC_AVG_SEL_LEN) - 1) << AUDIO_DRC_AVG_SEL_POS)) -#define AUDIO_DRC_PEAK_SEL AUDIO_DRC_PEAK_SEL -#define AUDIO_DRC_PEAK_SEL_POS (27U) -#define AUDIO_DRC_PEAK_SEL_LEN (2U) -#define AUDIO_DRC_PEAK_SEL_MSK (((1U << AUDIO_DRC_PEAK_SEL_LEN) - 1) << AUDIO_DRC_PEAK_SEL_POS) -#define AUDIO_DRC_PEAK_SEL_UMSK (~(((1U << AUDIO_DRC_PEAK_SEL_LEN) - 1) << AUDIO_DRC_PEAK_SEL_POS)) -#define AUDIO_DRC_RAW_SEL AUDIO_DRC_RAW_SEL -#define AUDIO_DRC_RAW_SEL_POS (29U) -#define AUDIO_DRC_RAW_SEL_LEN (2U) -#define AUDIO_DRC_RAW_SEL_MSK (((1U << AUDIO_DRC_RAW_SEL_LEN) - 1) << AUDIO_DRC_RAW_SEL_POS) -#define AUDIO_DRC_RAW_SEL_UMSK (~(((1U << AUDIO_DRC_RAW_SEL_LEN) - 1) << AUDIO_DRC_RAW_SEL_POS)) -#define AUDIO_DRC_EN AUDIO_DRC_EN -#define AUDIO_DRC_EN_POS (31U) -#define AUDIO_DRC_EN_LEN (1U) -#define AUDIO_DRC_EN_MSK (((1U << AUDIO_DRC_EN_LEN) - 1) << AUDIO_DRC_EN_POS) -#define AUDIO_DRC_EN_UMSK (~(((1U << AUDIO_DRC_EN_LEN) - 1) << AUDIO_DRC_EN_POS)) - -/* 0x448 : dac_drc_1 */ -#define AUDIO_DAC_DRC_1_OFFSET (0x448) -#define AUDIO_DRC_RELEASE_TIME AUDIO_DRC_RELEASE_TIME -#define AUDIO_DRC_RELEASE_TIME_POS (0U) -#define AUDIO_DRC_RELEASE_TIME_LEN (4U) -#define AUDIO_DRC_RELEASE_TIME_MSK (((1U << AUDIO_DRC_RELEASE_TIME_LEN) - 1) << AUDIO_DRC_RELEASE_TIME_POS) -#define AUDIO_DRC_RELEASE_TIME_UMSK (~(((1U << AUDIO_DRC_RELEASE_TIME_LEN) - 1) << AUDIO_DRC_RELEASE_TIME_POS)) -#define AUDIO_DRC_ATTACK_TIME AUDIO_DRC_ATTACK_TIME -#define AUDIO_DRC_ATTACK_TIME_POS (4U) -#define AUDIO_DRC_ATTACK_TIME_LEN (4U) -#define AUDIO_DRC_ATTACK_TIME_MSK (((1U << AUDIO_DRC_ATTACK_TIME_LEN) - 1) << AUDIO_DRC_ATTACK_TIME_POS) -#define AUDIO_DRC_ATTACK_TIME_UMSK (~(((1U << AUDIO_DRC_ATTACK_TIME_LEN) - 1) << AUDIO_DRC_ATTACK_TIME_POS)) -#define AUDIO_DRC_MAKEUP_GAIN AUDIO_DRC_MAKEUP_GAIN -#define AUDIO_DRC_MAKEUP_GAIN_POS (8U) -#define AUDIO_DRC_MAKEUP_GAIN_LEN (4U) -#define AUDIO_DRC_MAKEUP_GAIN_MSK (((1U << AUDIO_DRC_MAKEUP_GAIN_LEN) - 1) << AUDIO_DRC_MAKEUP_GAIN_POS) -#define AUDIO_DRC_MAKEUP_GAIN_UMSK (~(((1U << AUDIO_DRC_MAKEUP_GAIN_LEN) - 1) << AUDIO_DRC_MAKEUP_GAIN_POS)) -#define AUDIO_DRC_SLOPE_MODE_E AUDIO_DRC_SLOPE_MODE_E -#define AUDIO_DRC_SLOPE_MODE_E_POS (12U) -#define AUDIO_DRC_SLOPE_MODE_E_LEN (2U) -#define AUDIO_DRC_SLOPE_MODE_E_MSK (((1U << AUDIO_DRC_SLOPE_MODE_E_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_E_POS) -#define AUDIO_DRC_SLOPE_MODE_E_UMSK (~(((1U << AUDIO_DRC_SLOPE_MODE_E_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_E_POS)) -#define AUDIO_DRC_SLOPE_MODE_C AUDIO_DRC_SLOPE_MODE_C -#define AUDIO_DRC_SLOPE_MODE_C_POS (14U) -#define AUDIO_DRC_SLOPE_MODE_C_LEN (2U) -#define AUDIO_DRC_SLOPE_MODE_C_MSK (((1U << AUDIO_DRC_SLOPE_MODE_C_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_C_POS) -#define AUDIO_DRC_SLOPE_MODE_C_UMSK (~(((1U << AUDIO_DRC_SLOPE_MODE_C_LEN) - 1) << AUDIO_DRC_SLOPE_MODE_C_POS)) -#define AUDIO_DRC_THRESHOLD_E AUDIO_DRC_THRESHOLD_E -#define AUDIO_DRC_THRESHOLD_E_POS (16U) -#define AUDIO_DRC_THRESHOLD_E_LEN (6U) -#define AUDIO_DRC_THRESHOLD_E_MSK (((1U << AUDIO_DRC_THRESHOLD_E_LEN) - 1) << AUDIO_DRC_THRESHOLD_E_POS) -#define AUDIO_DRC_THRESHOLD_E_UMSK (~(((1U << AUDIO_DRC_THRESHOLD_E_LEN) - 1) << AUDIO_DRC_THRESHOLD_E_POS)) -#define AUDIO_DRC_THRESHOLD_C AUDIO_DRC_THRESHOLD_C -#define AUDIO_DRC_THRESHOLD_C_POS (22U) -#define AUDIO_DRC_THRESHOLD_C_LEN (5U) -#define AUDIO_DRC_THRESHOLD_C_MSK (((1U << AUDIO_DRC_THRESHOLD_C_LEN) - 1) << AUDIO_DRC_THRESHOLD_C_POS) -#define AUDIO_DRC_THRESHOLD_C_UMSK (~(((1U << AUDIO_DRC_THRESHOLD_C_LEN) - 1) << AUDIO_DRC_THRESHOLD_C_POS)) -#define AUDIO_DRC_THRESHOLD_L AUDIO_DRC_THRESHOLD_L -#define AUDIO_DRC_THRESHOLD_L_POS (27U) -#define AUDIO_DRC_THRESHOLD_L_LEN (5U) -#define AUDIO_DRC_THRESHOLD_L_MSK (((1U << AUDIO_DRC_THRESHOLD_L_LEN) - 1) << AUDIO_DRC_THRESHOLD_L_POS) -#define AUDIO_DRC_THRESHOLD_L_UMSK (~(((1U << AUDIO_DRC_THRESHOLD_L_LEN) - 1) << AUDIO_DRC_THRESHOLD_L_POS)) - -/* 0x44C : dac_ngt_0 */ -#define AUDIO_DAC_NGT_0_OFFSET (0x44C) -#define AUDIO_NGT_AMUTE_ON AUDIO_NGT_AMUTE_ON -#define AUDIO_NGT_AMUTE_ON_POS (2U) -#define AUDIO_NGT_AMUTE_ON_LEN (1U) -#define AUDIO_NGT_AMUTE_ON_MSK (((1U << AUDIO_NGT_AMUTE_ON_LEN) - 1) << AUDIO_NGT_AMUTE_ON_POS) -#define AUDIO_NGT_AMUTE_ON_UMSK (~(((1U << AUDIO_NGT_AMUTE_ON_LEN) - 1) << AUDIO_NGT_AMUTE_ON_POS)) -#define AUDIO_NGT_DMUTE_ON AUDIO_NGT_DMUTE_ON -#define AUDIO_NGT_DMUTE_ON_POS (3U) -#define AUDIO_NGT_DMUTE_ON_LEN (1U) -#define AUDIO_NGT_DMUTE_ON_MSK (((1U << AUDIO_NGT_DMUTE_ON_LEN) - 1) << AUDIO_NGT_DMUTE_ON_POS) -#define AUDIO_NGT_DMUTE_ON_UMSK (~(((1U << AUDIO_NGT_DMUTE_ON_LEN) - 1) << AUDIO_NGT_DMUTE_ON_POS)) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K AUDIO_NGT_SIGNAL_HOLD_TIME_K -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_POS (4U) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_LEN (4U) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_MSK (((1U << AUDIO_NGT_SIGNAL_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_TIME_K_POS) -#define AUDIO_NGT_SIGNAL_HOLD_TIME_K_UMSK (~(((1U << AUDIO_NGT_SIGNAL_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_TIME_K_POS)) -#define AUDIO_NGT_SIGNAL_HOLD_EN AUDIO_NGT_SIGNAL_HOLD_EN -#define AUDIO_NGT_SIGNAL_HOLD_EN_POS (8U) -#define AUDIO_NGT_SIGNAL_HOLD_EN_LEN (1U) -#define AUDIO_NGT_SIGNAL_HOLD_EN_MSK (((1U << AUDIO_NGT_SIGNAL_HOLD_EN_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_EN_POS) -#define AUDIO_NGT_SIGNAL_HOLD_EN_UMSK (~(((1U << AUDIO_NGT_SIGNAL_HOLD_EN_LEN) - 1) << AUDIO_NGT_SIGNAL_HOLD_EN_POS)) -#define AUDIO_NGT_NOISE_HOLD_TIME_K AUDIO_NGT_NOISE_HOLD_TIME_K -#define AUDIO_NGT_NOISE_HOLD_TIME_K_POS (9U) -#define AUDIO_NGT_NOISE_HOLD_TIME_K_LEN (4U) -#define AUDIO_NGT_NOISE_HOLD_TIME_K_MSK (((1U << AUDIO_NGT_NOISE_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_TIME_K_POS) -#define AUDIO_NGT_NOISE_HOLD_TIME_K_UMSK (~(((1U << AUDIO_NGT_NOISE_HOLD_TIME_K_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_TIME_K_POS)) -#define AUDIO_NGT_NOISE_HOLD_EN AUDIO_NGT_NOISE_HOLD_EN -#define AUDIO_NGT_NOISE_HOLD_EN_POS (13U) -#define AUDIO_NGT_NOISE_HOLD_EN_LEN (1U) -#define AUDIO_NGT_NOISE_HOLD_EN_MSK (((1U << AUDIO_NGT_NOISE_HOLD_EN_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_EN_POS) -#define AUDIO_NGT_NOISE_HOLD_EN_UMSK (~(((1U << AUDIO_NGT_NOISE_HOLD_EN_LEN) - 1) << AUDIO_NGT_NOISE_HOLD_EN_POS)) -#define AUDIO_NGT_HYSTERESIS AUDIO_NGT_HYSTERESIS -#define AUDIO_NGT_HYSTERESIS_POS (14U) -#define AUDIO_NGT_HYSTERESIS_LEN (2U) -#define AUDIO_NGT_HYSTERESIS_MSK (((1U << AUDIO_NGT_HYSTERESIS_LEN) - 1) << AUDIO_NGT_HYSTERESIS_POS) -#define AUDIO_NGT_HYSTERESIS_UMSK (~(((1U << AUDIO_NGT_HYSTERESIS_LEN) - 1) << AUDIO_NGT_HYSTERESIS_POS)) -#define AUDIO_NGT_THRESHOLD AUDIO_NGT_THRESHOLD -#define AUDIO_NGT_THRESHOLD_POS (16U) -#define AUDIO_NGT_THRESHOLD_LEN (8U) -#define AUDIO_NGT_THRESHOLD_MSK (((1U << AUDIO_NGT_THRESHOLD_LEN) - 1) << AUDIO_NGT_THRESHOLD_POS) -#define AUDIO_NGT_THRESHOLD_UMSK (~(((1U << AUDIO_NGT_THRESHOLD_LEN) - 1) << AUDIO_NGT_THRESHOLD_POS)) -#define AUDIO_NGT_AVG_TIME AUDIO_NGT_AVG_TIME -#define AUDIO_NGT_AVG_TIME_POS (24U) -#define AUDIO_NGT_AVG_TIME_LEN (5U) -#define AUDIO_NGT_AVG_TIME_MSK (((1U << AUDIO_NGT_AVG_TIME_LEN) - 1) << AUDIO_NGT_AVG_TIME_POS) -#define AUDIO_NGT_AVG_TIME_UMSK (~(((1U << AUDIO_NGT_AVG_TIME_LEN) - 1) << AUDIO_NGT_AVG_TIME_POS)) -#define AUDIO_NGT_SRC_SEL AUDIO_NGT_SRC_SEL -#define AUDIO_NGT_SRC_SEL_POS (29U) -#define AUDIO_NGT_SRC_SEL_LEN (2U) -#define AUDIO_NGT_SRC_SEL_MSK (((1U << AUDIO_NGT_SRC_SEL_LEN) - 1) << AUDIO_NGT_SRC_SEL_POS) -#define AUDIO_NGT_SRC_SEL_UMSK (~(((1U << AUDIO_NGT_SRC_SEL_LEN) - 1) << AUDIO_NGT_SRC_SEL_POS)) -#define AUDIO_NGT_EN AUDIO_NGT_EN -#define AUDIO_NGT_EN_POS (31U) -#define AUDIO_NGT_EN_LEN (1U) -#define AUDIO_NGT_EN_MSK (((1U << AUDIO_NGT_EN_LEN) - 1) << AUDIO_NGT_EN_POS) -#define AUDIO_NGT_EN_UMSK (~(((1U << AUDIO_NGT_EN_LEN) - 1) << AUDIO_NGT_EN_POS)) - -/* 0x450 : dac_zd_0 */ -#define AUDIO_DAC_ZD_0_OFFSET (0x450) -#define AUDIO_ZD_TIME AUDIO_ZD_TIME -#define AUDIO_ZD_TIME_POS (0U) -#define AUDIO_ZD_TIME_LEN (15U) -#define AUDIO_ZD_TIME_MSK (((1U << AUDIO_ZD_TIME_LEN) - 1) << AUDIO_ZD_TIME_POS) -#define AUDIO_ZD_TIME_UMSK (~(((1U << AUDIO_ZD_TIME_LEN) - 1) << AUDIO_ZD_TIME_POS)) -#define AUDIO_ZD_EN AUDIO_ZD_EN -#define AUDIO_ZD_EN_POS (16U) -#define AUDIO_ZD_EN_LEN (2U) -#define AUDIO_ZD_EN_MSK (((1U << AUDIO_ZD_EN_LEN) - 1) << AUDIO_ZD_EN_POS) -#define AUDIO_ZD_EN_UMSK (~(((1U << AUDIO_ZD_EN_LEN) - 1) << AUDIO_ZD_EN_POS)) -#define AUDIO_DAC_MUTE_HW_CTRL AUDIO_DAC_MUTE_HW_CTRL -#define AUDIO_DAC_MUTE_HW_CTRL_POS (30U) -#define AUDIO_DAC_MUTE_HW_CTRL_LEN (1U) -#define AUDIO_DAC_MUTE_HW_CTRL_MSK (((1U << AUDIO_DAC_MUTE_HW_CTRL_LEN) - 1) << AUDIO_DAC_MUTE_HW_CTRL_POS) -#define AUDIO_DAC_MUTE_HW_CTRL_UMSK (~(((1U << AUDIO_DAC_MUTE_HW_CTRL_LEN) - 1) << AUDIO_DAC_MUTE_HW_CTRL_POS)) -#define AUDIO_DAC_MUTE AUDIO_DAC_MUTE -#define AUDIO_DAC_MUTE_POS (31U) -#define AUDIO_DAC_MUTE_LEN (1U) -#define AUDIO_DAC_MUTE_MSK (((1U << AUDIO_DAC_MUTE_LEN) - 1) << AUDIO_DAC_MUTE_POS) -#define AUDIO_DAC_MUTE_UMSK (~(((1U << AUDIO_DAC_MUTE_LEN) - 1) << AUDIO_DAC_MUTE_POS)) - -/* 0x600 : vad_ctrl_0 */ -#define AUDIO_VAD_CTRL_0_OFFSET (0x600) -#define AUDIO_VAD_NTH_MINLMT_EN AUDIO_VAD_NTH_MINLMT_EN -#define AUDIO_VAD_NTH_MINLMT_EN_POS (0U) -#define AUDIO_VAD_NTH_MINLMT_EN_LEN (1U) -#define AUDIO_VAD_NTH_MINLMT_EN_MSK (((1U << AUDIO_VAD_NTH_MINLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_EN_POS) -#define AUDIO_VAD_NTH_MINLMT_EN_UMSK (~(((1U << AUDIO_VAD_NTH_MINLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_EN_POS)) -#define AUDIO_VAD_NTH_MAXLMT_EN AUDIO_VAD_NTH_MAXLMT_EN -#define AUDIO_VAD_NTH_MAXLMT_EN_POS (1U) -#define AUDIO_VAD_NTH_MAXLMT_EN_LEN (1U) -#define AUDIO_VAD_NTH_MAXLMT_EN_MSK (((1U << AUDIO_VAD_NTH_MAXLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_EN_POS) -#define AUDIO_VAD_NTH_MAXLMT_EN_UMSK (~(((1U << AUDIO_VAD_NTH_MAXLMT_EN_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_EN_POS)) -#define AUDIO_VAD_NBUF_MONIT_EN AUDIO_VAD_NBUF_MONIT_EN -#define AUDIO_VAD_NBUF_MONIT_EN_POS (2U) -#define AUDIO_VAD_NBUF_MONIT_EN_LEN (1U) -#define AUDIO_VAD_NBUF_MONIT_EN_MSK (((1U << AUDIO_VAD_NBUF_MONIT_EN_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_EN_POS) -#define AUDIO_VAD_NBUF_MONIT_EN_UMSK (~(((1U << AUDIO_VAD_NBUF_MONIT_EN_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_EN_POS)) -#define AUDIO_VAD_NBUF_MONIT_CTRL AUDIO_VAD_NBUF_MONIT_CTRL -#define AUDIO_VAD_NBUF_MONIT_CTRL_POS (4U) -#define AUDIO_VAD_NBUF_MONIT_CTRL_LEN (2U) -#define AUDIO_VAD_NBUF_MONIT_CTRL_MSK (((1U << AUDIO_VAD_NBUF_MONIT_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_CTRL_POS) -#define AUDIO_VAD_NBUF_MONIT_CTRL_UMSK (~(((1U << AUDIO_VAD_NBUF_MONIT_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_MONIT_CTRL_POS)) -#define AUDIO_VAD_NBUF_LEN_CTRL AUDIO_VAD_NBUF_LEN_CTRL -#define AUDIO_VAD_NBUF_LEN_CTRL_POS (8U) -#define AUDIO_VAD_NBUF_LEN_CTRL_LEN (3U) -#define AUDIO_VAD_NBUF_LEN_CTRL_MSK (((1U << AUDIO_VAD_NBUF_LEN_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_LEN_CTRL_POS) -#define AUDIO_VAD_NBUF_LEN_CTRL_UMSK (~(((1U << AUDIO_VAD_NBUF_LEN_CTRL_LEN) - 1) << AUDIO_VAD_NBUF_LEN_CTRL_POS)) -#define AUDIO_VAD_OUT_SEL AUDIO_VAD_OUT_SEL -#define AUDIO_VAD_OUT_SEL_POS (12U) -#define AUDIO_VAD_OUT_SEL_LEN (2U) -#define AUDIO_VAD_OUT_SEL_MSK (((1U << AUDIO_VAD_OUT_SEL_LEN) - 1) << AUDIO_VAD_OUT_SEL_POS) -#define AUDIO_VAD_OUT_SEL_UMSK (~(((1U << AUDIO_VAD_OUT_SEL_LEN) - 1) << AUDIO_VAD_OUT_SEL_POS)) -#define AUDIO_VAD_FRAMETIME_CTRL AUDIO_VAD_FRAMETIME_CTRL -#define AUDIO_VAD_FRAMETIME_CTRL_POS (14U) -#define AUDIO_VAD_FRAMETIME_CTRL_LEN (2U) -#define AUDIO_VAD_FRAMETIME_CTRL_MSK (((1U << AUDIO_VAD_FRAMETIME_CTRL_LEN) - 1) << AUDIO_VAD_FRAMETIME_CTRL_POS) -#define AUDIO_VAD_FRAMETIME_CTRL_UMSK (~(((1U << AUDIO_VAD_FRAMETIME_CTRL_LEN) - 1) << AUDIO_VAD_FRAMETIME_CTRL_POS)) -#define AUDIO_VAD_FRAMESHIFT_CTRL AUDIO_VAD_FRAMESHIFT_CTRL -#define AUDIO_VAD_FRAMESHIFT_CTRL_POS (16U) -#define AUDIO_VAD_FRAMESHIFT_CTRL_LEN (3U) -#define AUDIO_VAD_FRAMESHIFT_CTRL_MSK (((1U << AUDIO_VAD_FRAMESHIFT_CTRL_LEN) - 1) << AUDIO_VAD_FRAMESHIFT_CTRL_POS) -#define AUDIO_VAD_FRAMESHIFT_CTRL_UMSK (~(((1U << AUDIO_VAD_FRAMESHIFT_CTRL_LEN) - 1) << AUDIO_VAD_FRAMESHIFT_CTRL_POS)) -#define AUDIO_VAD_OUT AUDIO_VAD_OUT -#define AUDIO_VAD_OUT_POS (19U) -#define AUDIO_VAD_OUT_LEN (1U) -#define AUDIO_VAD_OUT_MSK (((1U << AUDIO_VAD_OUT_LEN) - 1) << AUDIO_VAD_OUT_POS) -#define AUDIO_VAD_OUT_UMSK (~(((1U << AUDIO_VAD_OUT_LEN) - 1) << AUDIO_VAD_OUT_POS)) -#define AUDIO_VAD_IN_SEL AUDIO_VAD_IN_SEL -#define AUDIO_VAD_IN_SEL_POS (20U) -#define AUDIO_VAD_IN_SEL_LEN (3U) -#define AUDIO_VAD_IN_SEL_MSK (((1U << AUDIO_VAD_IN_SEL_LEN) - 1) << AUDIO_VAD_IN_SEL_POS) -#define AUDIO_VAD_IN_SEL_UMSK (~(((1U << AUDIO_VAD_IN_SEL_LEN) - 1) << AUDIO_VAD_IN_SEL_POS)) -#define AUDIO_VAD_EN AUDIO_VAD_EN -#define AUDIO_VAD_EN_POS (23U) -#define AUDIO_VAD_EN_LEN (1U) -#define AUDIO_VAD_EN_MSK (((1U << AUDIO_VAD_EN_LEN) - 1) << AUDIO_VAD_EN_POS) -#define AUDIO_VAD_EN_UMSK (~(((1U << AUDIO_VAD_EN_LEN) - 1) << AUDIO_VAD_EN_POS)) - -/* 0x604 : vad_ctrl_1 */ -#define AUDIO_VAD_CTRL_1_OFFSET (0x604) -#define AUDIO_VAD_NTH_SCALE AUDIO_VAD_NTH_SCALE -#define AUDIO_VAD_NTH_SCALE_POS (0U) -#define AUDIO_VAD_NTH_SCALE_LEN (8U) -#define AUDIO_VAD_NTH_SCALE_MSK (((1U << AUDIO_VAD_NTH_SCALE_LEN) - 1) << AUDIO_VAD_NTH_SCALE_POS) -#define AUDIO_VAD_NTH_SCALE_UMSK (~(((1U << AUDIO_VAD_NTH_SCALE_LEN) - 1) << AUDIO_VAD_NTH_SCALE_POS)) -#define AUDIO_VAD_NTH_BIAS AUDIO_VAD_NTH_BIAS -#define AUDIO_VAD_NTH_BIAS_POS (8U) -#define AUDIO_VAD_NTH_BIAS_LEN (16U) -#define AUDIO_VAD_NTH_BIAS_MSK (((1U << AUDIO_VAD_NTH_BIAS_LEN) - 1) << AUDIO_VAD_NTH_BIAS_POS) -#define AUDIO_VAD_NTH_BIAS_UMSK (~(((1U << AUDIO_VAD_NTH_BIAS_LEN) - 1) << AUDIO_VAD_NTH_BIAS_POS)) -#define AUDIO_VAD_NBUF_DISCARD AUDIO_VAD_NBUF_DISCARD -#define AUDIO_VAD_NBUF_DISCARD_POS (24U) -#define AUDIO_VAD_NBUF_DISCARD_LEN (8U) -#define AUDIO_VAD_NBUF_DISCARD_MSK (((1U << AUDIO_VAD_NBUF_DISCARD_LEN) - 1) << AUDIO_VAD_NBUF_DISCARD_POS) -#define AUDIO_VAD_NBUF_DISCARD_UMSK (~(((1U << AUDIO_VAD_NBUF_DISCARD_LEN) - 1) << AUDIO_VAD_NBUF_DISCARD_POS)) - -/* 0x608 : vad_ctrl_2 */ -#define AUDIO_VAD_CTRL_2_OFFSET (0x608) -#define AUDIO_VAD_NTH_MINLMT AUDIO_VAD_NTH_MINLMT -#define AUDIO_VAD_NTH_MINLMT_POS (0U) -#define AUDIO_VAD_NTH_MINLMT_LEN (16U) -#define AUDIO_VAD_NTH_MINLMT_MSK (((1U << AUDIO_VAD_NTH_MINLMT_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_POS) -#define AUDIO_VAD_NTH_MINLMT_UMSK (~(((1U << AUDIO_VAD_NTH_MINLMT_LEN) - 1) << AUDIO_VAD_NTH_MINLMT_POS)) -#define AUDIO_VAD_NTH_MAXLMT AUDIO_VAD_NTH_MAXLMT -#define AUDIO_VAD_NTH_MAXLMT_POS (16U) -#define AUDIO_VAD_NTH_MAXLMT_LEN (16U) -#define AUDIO_VAD_NTH_MAXLMT_MSK (((1U << AUDIO_VAD_NTH_MAXLMT_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_POS) -#define AUDIO_VAD_NTH_MAXLMT_UMSK (~(((1U << AUDIO_VAD_NTH_MAXLMT_LEN) - 1) << AUDIO_VAD_NTH_MAXLMT_POS)) - -/* 0x60C : vad_ctrl_3 */ -#define AUDIO_VAD_CTRL_3_OFFSET (0x60C) -#define AUDIO_VAD_SMOOTH_FALL AUDIO_VAD_SMOOTH_FALL -#define AUDIO_VAD_SMOOTH_FALL_POS (0U) -#define AUDIO_VAD_SMOOTH_FALL_LEN (8U) -#define AUDIO_VAD_SMOOTH_FALL_MSK (((1U << AUDIO_VAD_SMOOTH_FALL_LEN) - 1) << AUDIO_VAD_SMOOTH_FALL_POS) -#define AUDIO_VAD_SMOOTH_FALL_UMSK (~(((1U << AUDIO_VAD_SMOOTH_FALL_LEN) - 1) << AUDIO_VAD_SMOOTH_FALL_POS)) -#define AUDIO_VAD_SMOOTH_RISE AUDIO_VAD_SMOOTH_RISE -#define AUDIO_VAD_SMOOTH_RISE_POS (8U) -#define AUDIO_VAD_SMOOTH_RISE_LEN (8U) -#define AUDIO_VAD_SMOOTH_RISE_MSK (((1U << AUDIO_VAD_SMOOTH_RISE_LEN) - 1) << AUDIO_VAD_SMOOTH_RISE_POS) -#define AUDIO_VAD_SMOOTH_RISE_UMSK (~(((1U << AUDIO_VAD_SMOOTH_RISE_LEN) - 1) << AUDIO_VAD_SMOOTH_RISE_POS)) - -/* 0x610 : vad_ctrl_4 */ -#define AUDIO_VAD_CTRL_4_OFFSET (0x610) -#define AUDIO_VAD_EK AUDIO_VAD_EK -#define AUDIO_VAD_EK_POS (0U) -#define AUDIO_VAD_EK_LEN (24U) -#define AUDIO_VAD_EK_MSK (((1U << AUDIO_VAD_EK_LEN) - 1) << AUDIO_VAD_EK_POS) -#define AUDIO_VAD_EK_UMSK (~(((1U << AUDIO_VAD_EK_LEN) - 1) << AUDIO_VAD_EK_POS)) - -/* 0x614 : vad_ctrl_5 */ -#define AUDIO_VAD_CTRL_5_OFFSET (0x614) -#define AUDIO_VAD_NOISE_TH AUDIO_VAD_NOISE_TH -#define AUDIO_VAD_NOISE_TH_POS (0U) -#define AUDIO_VAD_NOISE_TH_LEN (24U) -#define AUDIO_VAD_NOISE_TH_MSK (((1U << AUDIO_VAD_NOISE_TH_LEN) - 1) << AUDIO_VAD_NOISE_TH_POS) -#define AUDIO_VAD_NOISE_TH_UMSK (~(((1U << AUDIO_VAD_NOISE_TH_LEN) - 1) << AUDIO_VAD_NOISE_TH_POS)) - -/* 0x700 : codec_power1 */ -#define AUDIO_CODEC_POWER1_OFFSET (0x700) -#define AUDIO_MICBIAS_PU AUDIO_MICBIAS_PU -#define AUDIO_MICBIAS_PU_POS (0U) -#define AUDIO_MICBIAS_PU_LEN (1U) -#define AUDIO_MICBIAS_PU_MSK (((1U << AUDIO_MICBIAS_PU_LEN) - 1) << AUDIO_MICBIAS_PU_POS) -#define AUDIO_MICBIAS_PU_UMSK (~(((1U << AUDIO_MICBIAS_PU_LEN) - 1) << AUDIO_MICBIAS_PU_POS)) -#define AUDIO_MICBIAS_CHOP_EN AUDIO_MICBIAS_CHOP_EN -#define AUDIO_MICBIAS_CHOP_EN_POS (1U) -#define AUDIO_MICBIAS_CHOP_EN_LEN (1U) -#define AUDIO_MICBIAS_CHOP_EN_MSK (((1U << AUDIO_MICBIAS_CHOP_EN_LEN) - 1) << AUDIO_MICBIAS_CHOP_EN_POS) -#define AUDIO_MICBIAS_CHOP_EN_UMSK (~(((1U << AUDIO_MICBIAS_CHOP_EN_LEN) - 1) << AUDIO_MICBIAS_CHOP_EN_POS)) -#define AUDIO_MICBIAS_CLK_CHOP_SEL AUDIO_MICBIAS_CLK_CHOP_SEL -#define AUDIO_MICBIAS_CLK_CHOP_SEL_POS (2U) -#define AUDIO_MICBIAS_CLK_CHOP_SEL_LEN (2U) -#define AUDIO_MICBIAS_CLK_CHOP_SEL_MSK (((1U << AUDIO_MICBIAS_CLK_CHOP_SEL_LEN) - 1) << AUDIO_MICBIAS_CLK_CHOP_SEL_POS) -#define AUDIO_MICBIAS_CLK_CHOP_SEL_UMSK (~(((1U << AUDIO_MICBIAS_CLK_CHOP_SEL_LEN) - 1) << AUDIO_MICBIAS_CLK_CHOP_SEL_POS)) -#define AUDIO_MICBIAS_VSEL AUDIO_MICBIAS_VSEL -#define AUDIO_MICBIAS_VSEL_POS (4U) -#define AUDIO_MICBIAS_VSEL_LEN (2U) -#define AUDIO_MICBIAS_VSEL_MSK (((1U << AUDIO_MICBIAS_VSEL_LEN) - 1) << AUDIO_MICBIAS_VSEL_POS) -#define AUDIO_MICBIAS_VSEL_UMSK (~(((1U << AUDIO_MICBIAS_VSEL_LEN) - 1) << AUDIO_MICBIAS_VSEL_POS)) -#define AUDIO_PADC_IBIAS_SOURCE AUDIO_PADC_IBIAS_SOURCE -#define AUDIO_PADC_IBIAS_SOURCE_POS (6U) -#define AUDIO_PADC_IBIAS_SOURCE_LEN (1U) -#define AUDIO_PADC_IBIAS_SOURCE_MSK (((1U << AUDIO_PADC_IBIAS_SOURCE_LEN) - 1) << AUDIO_PADC_IBIAS_SOURCE_POS) -#define AUDIO_PADC_IBIAS_SOURCE_UMSK (~(((1U << AUDIO_PADC_IBIAS_SOURCE_LEN) - 1) << AUDIO_PADC_IBIAS_SOURCE_POS)) -#define AUDIO_PADC_POWER_TEN AUDIO_PADC_POWER_TEN -#define AUDIO_PADC_POWER_TEN_POS (7U) -#define AUDIO_PADC_POWER_TEN_LEN (1U) -#define AUDIO_PADC_POWER_TEN_MSK (((1U << AUDIO_PADC_POWER_TEN_LEN) - 1) << AUDIO_PADC_POWER_TEN_POS) -#define AUDIO_PADC_POWER_TEN_UMSK (~(((1U << AUDIO_PADC_POWER_TEN_LEN) - 1) << AUDIO_PADC_POWER_TEN_POS)) -#define AUDIO_PADC_POWER_TMUX AUDIO_PADC_POWER_TMUX -#define AUDIO_PADC_POWER_TMUX_POS (8U) -#define AUDIO_PADC_POWER_TMUX_LEN (3U) -#define AUDIO_PADC_POWER_TMUX_MSK (((1U << AUDIO_PADC_POWER_TMUX_LEN) - 1) << AUDIO_PADC_POWER_TMUX_POS) -#define AUDIO_PADC_POWER_TMUX_UMSK (~(((1U << AUDIO_PADC_POWER_TMUX_LEN) - 1) << AUDIO_PADC_POWER_TMUX_POS)) -#define AUDIO_CODEC_VRDA_EN AUDIO_CODEC_VRDA_EN -#define AUDIO_CODEC_VRDA_EN_POS (12U) -#define AUDIO_CODEC_VRDA_EN_LEN (1U) -#define AUDIO_CODEC_VRDA_EN_MSK (((1U << AUDIO_CODEC_VRDA_EN_LEN) - 1) << AUDIO_CODEC_VRDA_EN_POS) -#define AUDIO_CODEC_VRDA_EN_UMSK (~(((1U << AUDIO_CODEC_VRDA_EN_LEN) - 1) << AUDIO_CODEC_VRDA_EN_POS)) -#define AUDIO_CODEC_ICTRL_VCM AUDIO_CODEC_ICTRL_VCM -#define AUDIO_CODEC_ICTRL_VCM_POS (13U) -#define AUDIO_CODEC_ICTRL_VCM_LEN (2U) -#define AUDIO_CODEC_ICTRL_VCM_MSK (((1U << AUDIO_CODEC_ICTRL_VCM_LEN) - 1) << AUDIO_CODEC_ICTRL_VCM_POS) -#define AUDIO_CODEC_ICTRL_VCM_UMSK (~(((1U << AUDIO_CODEC_ICTRL_VCM_LEN) - 1) << AUDIO_CODEC_ICTRL_VCM_POS)) -#define AUDIO_CODEC_IBIAS_CTRL AUDIO_CODEC_IBIAS_CTRL -#define AUDIO_CODEC_IBIAS_CTRL_POS (16U) -#define AUDIO_CODEC_IBIAS_CTRL_LEN (3U) -#define AUDIO_CODEC_IBIAS_CTRL_MSK (((1U << AUDIO_CODEC_IBIAS_CTRL_LEN) - 1) << AUDIO_CODEC_IBIAS_CTRL_POS) -#define AUDIO_CODEC_IBIAS_CTRL_UMSK (~(((1U << AUDIO_CODEC_IBIAS_CTRL_LEN) - 1) << AUDIO_CODEC_IBIAS_CTRL_POS)) - -/* 0x704 : codec_power2 */ -#define AUDIO_CODEC_POWER2_OFFSET (0x704) -#define AUDIO_HPBG_CHOP_SEL AUDIO_HPBG_CHOP_SEL -#define AUDIO_HPBG_CHOP_SEL_POS (0U) -#define AUDIO_HPBG_CHOP_SEL_LEN (3U) -#define AUDIO_HPBG_CHOP_SEL_MSK (((1U << AUDIO_HPBG_CHOP_SEL_LEN) - 1) << AUDIO_HPBG_CHOP_SEL_POS) -#define AUDIO_HPBG_CHOP_SEL_UMSK (~(((1U << AUDIO_HPBG_CHOP_SEL_LEN) - 1) << AUDIO_HPBG_CHOP_SEL_POS)) -#define AUDIO_HPBG_CHOP_EN AUDIO_HPBG_CHOP_EN -#define AUDIO_HPBG_CHOP_EN_POS (3U) -#define AUDIO_HPBG_CHOP_EN_LEN (1U) -#define AUDIO_HPBG_CHOP_EN_MSK (((1U << AUDIO_HPBG_CHOP_EN_LEN) - 1) << AUDIO_HPBG_CHOP_EN_POS) -#define AUDIO_HPBG_CHOP_EN_UMSK (~(((1U << AUDIO_HPBG_CHOP_EN_LEN) - 1) << AUDIO_HPBG_CHOP_EN_POS)) -#define AUDIO_HPBG_PU AUDIO_HPBG_PU -#define AUDIO_HPBG_PU_POS (4U) -#define AUDIO_HPBG_PU_LEN (1U) -#define AUDIO_HPBG_PU_MSK (((1U << AUDIO_HPBG_PU_LEN) - 1) << AUDIO_HPBG_PU_POS) -#define AUDIO_HPBG_PU_UMSK (~(((1U << AUDIO_HPBG_PU_LEN) - 1) << AUDIO_HPBG_PU_POS)) -#define AUDIO_HPBG_FILT_RSEL AUDIO_HPBG_FILT_RSEL -#define AUDIO_HPBG_FILT_RSEL_POS (5U) -#define AUDIO_HPBG_FILT_RSEL_LEN (2U) -#define AUDIO_HPBG_FILT_RSEL_MSK (((1U << AUDIO_HPBG_FILT_RSEL_LEN) - 1) << AUDIO_HPBG_FILT_RSEL_POS) -#define AUDIO_HPBG_FILT_RSEL_UMSK (~(((1U << AUDIO_HPBG_FILT_RSEL_LEN) - 1) << AUDIO_HPBG_FILT_RSEL_POS)) -#define AUDIO_HPBG_BYPASS AUDIO_HPBG_BYPASS -#define AUDIO_HPBG_BYPASS_POS (7U) -#define AUDIO_HPBG_BYPASS_LEN (1U) -#define AUDIO_HPBG_BYPASS_MSK (((1U << AUDIO_HPBG_BYPASS_LEN) - 1) << AUDIO_HPBG_BYPASS_POS) -#define AUDIO_HPBG_BYPASS_UMSK (~(((1U << AUDIO_HPBG_BYPASS_LEN) - 1) << AUDIO_HPBG_BYPASS_POS)) -#define AUDIO_HPBG_ADJUST_FINE AUDIO_HPBG_ADJUST_FINE -#define AUDIO_HPBG_ADJUST_FINE_POS (8U) -#define AUDIO_HPBG_ADJUST_FINE_LEN (4U) -#define AUDIO_HPBG_ADJUST_FINE_MSK (((1U << AUDIO_HPBG_ADJUST_FINE_LEN) - 1) << AUDIO_HPBG_ADJUST_FINE_POS) -#define AUDIO_HPBG_ADJUST_FINE_UMSK (~(((1U << AUDIO_HPBG_ADJUST_FINE_LEN) - 1) << AUDIO_HPBG_ADJUST_FINE_POS)) -#define AUDIO_HPBG_ADJUST_COARSE AUDIO_HPBG_ADJUST_COARSE -#define AUDIO_HPBG_ADJUST_COARSE_POS (12U) -#define AUDIO_HPBG_ADJUST_COARSE_LEN (4U) -#define AUDIO_HPBG_ADJUST_COARSE_MSK (((1U << AUDIO_HPBG_ADJUST_COARSE_LEN) - 1) << AUDIO_HPBG_ADJUST_COARSE_POS) -#define AUDIO_HPBG_ADJUST_COARSE_UMSK (~(((1U << AUDIO_HPBG_ADJUST_COARSE_LEN) - 1) << AUDIO_HPBG_ADJUST_COARSE_POS)) -#define AUDIO_HPBG_COMPST_EN AUDIO_HPBG_COMPST_EN -#define AUDIO_HPBG_COMPST_EN_POS (16U) -#define AUDIO_HPBG_COMPST_EN_LEN (1U) -#define AUDIO_HPBG_COMPST_EN_MSK (((1U << AUDIO_HPBG_COMPST_EN_LEN) - 1) << AUDIO_HPBG_COMPST_EN_POS) -#define AUDIO_HPBG_COMPST_EN_UMSK (~(((1U << AUDIO_HPBG_COMPST_EN_LEN) - 1) << AUDIO_HPBG_COMPST_EN_POS)) -#define AUDIO_LDO25_SSTART_EN AUDIO_LDO25_SSTART_EN -#define AUDIO_LDO25_SSTART_EN_POS (17U) -#define AUDIO_LDO25_SSTART_EN_LEN (1U) -#define AUDIO_LDO25_SSTART_EN_MSK (((1U << AUDIO_LDO25_SSTART_EN_LEN) - 1) << AUDIO_LDO25_SSTART_EN_POS) -#define AUDIO_LDO25_SSTART_EN_UMSK (~(((1U << AUDIO_LDO25_SSTART_EN_LEN) - 1) << AUDIO_LDO25_SSTART_EN_POS)) -#define AUDIO_LDO25_SSTART_DELAY AUDIO_LDO25_SSTART_DELAY -#define AUDIO_LDO25_SSTART_DELAY_POS (18U) -#define AUDIO_LDO25_SSTART_DELAY_LEN (2U) -#define AUDIO_LDO25_SSTART_DELAY_MSK (((1U << AUDIO_LDO25_SSTART_DELAY_LEN) - 1) << AUDIO_LDO25_SSTART_DELAY_POS) -#define AUDIO_LDO25_SSTART_DELAY_UMSK (~(((1U << AUDIO_LDO25_SSTART_DELAY_LEN) - 1) << AUDIO_LDO25_SSTART_DELAY_POS)) -#define AUDIO_LDO25_PULLDOWN_SEL AUDIO_LDO25_PULLDOWN_SEL -#define AUDIO_LDO25_PULLDOWN_SEL_POS (20U) -#define AUDIO_LDO25_PULLDOWN_SEL_LEN (1U) -#define AUDIO_LDO25_PULLDOWN_SEL_MSK (((1U << AUDIO_LDO25_PULLDOWN_SEL_LEN) - 1) << AUDIO_LDO25_PULLDOWN_SEL_POS) -#define AUDIO_LDO25_PULLDOWN_SEL_UMSK (~(((1U << AUDIO_LDO25_PULLDOWN_SEL_LEN) - 1) << AUDIO_LDO25_PULLDOWN_SEL_POS)) -#define AUDIO_LDO25_PULLDOWN AUDIO_LDO25_PULLDOWN -#define AUDIO_LDO25_PULLDOWN_POS (21U) -#define AUDIO_LDO25_PULLDOWN_LEN (1U) -#define AUDIO_LDO25_PULLDOWN_MSK (((1U << AUDIO_LDO25_PULLDOWN_LEN) - 1) << AUDIO_LDO25_PULLDOWN_POS) -#define AUDIO_LDO25_PULLDOWN_UMSK (~(((1U << AUDIO_LDO25_PULLDOWN_LEN) - 1) << AUDIO_LDO25_PULLDOWN_POS)) -#define AUDIO_LDO25_PU AUDIO_LDO25_PU -#define AUDIO_LDO25_PU_POS (22U) -#define AUDIO_LDO25_PU_LEN (1U) -#define AUDIO_LDO25_PU_MSK (((1U << AUDIO_LDO25_PU_LEN) - 1) << AUDIO_LDO25_PU_POS) -#define AUDIO_LDO25_PU_UMSK (~(((1U << AUDIO_LDO25_PU_LEN) - 1) << AUDIO_LDO25_PU_POS)) -#define AUDIO_LDO25_CHOP_SEL AUDIO_LDO25_CHOP_SEL -#define AUDIO_LDO25_CHOP_SEL_POS (24U) -#define AUDIO_LDO25_CHOP_SEL_LEN (3U) -#define AUDIO_LDO25_CHOP_SEL_MSK (((1U << AUDIO_LDO25_CHOP_SEL_LEN) - 1) << AUDIO_LDO25_CHOP_SEL_POS) -#define AUDIO_LDO25_CHOP_SEL_UMSK (~(((1U << AUDIO_LDO25_CHOP_SEL_LEN) - 1) << AUDIO_LDO25_CHOP_SEL_POS)) -#define AUDIO_LDO25_CHOP_EN AUDIO_LDO25_CHOP_EN -#define AUDIO_LDO25_CHOP_EN_POS (27U) -#define AUDIO_LDO25_CHOP_EN_LEN (1U) -#define AUDIO_LDO25_CHOP_EN_MSK (((1U << AUDIO_LDO25_CHOP_EN_LEN) - 1) << AUDIO_LDO25_CHOP_EN_POS) -#define AUDIO_LDO25_CHOP_EN_UMSK (~(((1U << AUDIO_LDO25_CHOP_EN_LEN) - 1) << AUDIO_LDO25_CHOP_EN_POS)) -#define AUDIO_LDO25_CC_SEL AUDIO_LDO25_CC_SEL -#define AUDIO_LDO25_CC_SEL_POS (28U) -#define AUDIO_LDO25_CC_SEL_LEN (3U) -#define AUDIO_LDO25_CC_SEL_MSK (((1U << AUDIO_LDO25_CC_SEL_LEN) - 1) << AUDIO_LDO25_CC_SEL_POS) -#define AUDIO_LDO25_CC_SEL_UMSK (~(((1U << AUDIO_LDO25_CC_SEL_LEN) - 1) << AUDIO_LDO25_CC_SEL_POS)) - -/* 0x708 : codec_dac */ -#define AUDIO_CODEC_DAC_OFFSET (0x708) -#define AUDIO_DACR_LINEOUT_GAIN AUDIO_DACR_LINEOUT_GAIN -#define AUDIO_DACR_LINEOUT_GAIN_POS (0U) -#define AUDIO_DACR_LINEOUT_GAIN_LEN (3U) -#define AUDIO_DACR_LINEOUT_GAIN_MSK (((1U << AUDIO_DACR_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACR_LINEOUT_GAIN_POS) -#define AUDIO_DACR_LINEOUT_GAIN_UMSK (~(((1U << AUDIO_DACR_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACR_LINEOUT_GAIN_POS)) -#define AUDIO_DACR_EN_LINEOUT AUDIO_DACR_EN_LINEOUT -#define AUDIO_DACR_EN_LINEOUT_POS (3U) -#define AUDIO_DACR_EN_LINEOUT_LEN (1U) -#define AUDIO_DACR_EN_LINEOUT_MSK (((1U << AUDIO_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DACR_EN_LINEOUT_POS) -#define AUDIO_DACR_EN_LINEOUT_UMSK (~(((1U << AUDIO_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DACR_EN_LINEOUT_POS)) -#define AUDIO_DACR_EN_DAC AUDIO_DACR_EN_DAC -#define AUDIO_DACR_EN_DAC_POS (4U) -#define AUDIO_DACR_EN_DAC_LEN (1U) -#define AUDIO_DACR_EN_DAC_MSK (((1U << AUDIO_DACR_EN_DAC_LEN) - 1) << AUDIO_DACR_EN_DAC_POS) -#define AUDIO_DACR_EN_DAC_UMSK (~(((1U << AUDIO_DACR_EN_DAC_LEN) - 1) << AUDIO_DACR_EN_DAC_POS)) -#define AUDIO_DACR_LINEOUT_MODE AUDIO_DACR_LINEOUT_MODE -#define AUDIO_DACR_LINEOUT_MODE_POS (6U) -#define AUDIO_DACR_LINEOUT_MODE_LEN (1U) -#define AUDIO_DACR_LINEOUT_MODE_MSK (((1U << AUDIO_DACR_LINEOUT_MODE_LEN) - 1) << AUDIO_DACR_LINEOUT_MODE_POS) -#define AUDIO_DACR_LINEOUT_MODE_UMSK (~(((1U << AUDIO_DACR_LINEOUT_MODE_LEN) - 1) << AUDIO_DACR_LINEOUT_MODE_POS)) -#define AUDIO_DACR_ICTRL_LINEOUT AUDIO_DACR_ICTRL_LINEOUT -#define AUDIO_DACR_ICTRL_LINEOUT_POS (8U) -#define AUDIO_DACR_ICTRL_LINEOUT_LEN (2U) -#define AUDIO_DACR_ICTRL_LINEOUT_MSK (((1U << AUDIO_DACR_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACR_ICTRL_LINEOUT_POS) -#define AUDIO_DACR_ICTRL_LINEOUT_UMSK (~(((1U << AUDIO_DACR_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACR_ICTRL_LINEOUT_POS)) -#define AUDIO_DACR_SDAC_LINEOUT AUDIO_DACR_SDAC_LINEOUT -#define AUDIO_DACR_SDAC_LINEOUT_POS (10U) -#define AUDIO_DACR_SDAC_LINEOUT_LEN (1U) -#define AUDIO_DACR_SDAC_LINEOUT_MSK (((1U << AUDIO_DACR_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACR_SDAC_LINEOUT_POS) -#define AUDIO_DACR_SDAC_LINEOUT_UMSK (~(((1U << AUDIO_DACR_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACR_SDAC_LINEOUT_POS)) -#define AUDIO_DACR_SDEBUG_LINEOUT AUDIO_DACR_SDEBUG_LINEOUT -#define AUDIO_DACR_SDEBUG_LINEOUT_POS (11U) -#define AUDIO_DACR_SDEBUG_LINEOUT_LEN (1U) -#define AUDIO_DACR_SDEBUG_LINEOUT_MSK (((1U << AUDIO_DACR_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACR_SDEBUG_LINEOUT_POS) -#define AUDIO_DACR_SDEBUG_LINEOUT_UMSK (~(((1U << AUDIO_DACR_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACR_SDEBUG_LINEOUT_POS)) -#define AUDIO_DACR_ICTRL_DAC AUDIO_DACR_ICTRL_DAC -#define AUDIO_DACR_ICTRL_DAC_POS (12U) -#define AUDIO_DACR_ICTRL_DAC_LEN (2U) -#define AUDIO_DACR_ICTRL_DAC_MSK (((1U << AUDIO_DACR_ICTRL_DAC_LEN) - 1) << AUDIO_DACR_ICTRL_DAC_POS) -#define AUDIO_DACR_ICTRL_DAC_UMSK (~(((1U << AUDIO_DACR_ICTRL_DAC_LEN) - 1) << AUDIO_DACR_ICTRL_DAC_POS)) -#define AUDIO_DACR_CKB_EN AUDIO_DACR_CKB_EN -#define AUDIO_DACR_CKB_EN_POS (14U) -#define AUDIO_DACR_CKB_EN_LEN (1U) -#define AUDIO_DACR_CKB_EN_MSK (((1U << AUDIO_DACR_CKB_EN_LEN) - 1) << AUDIO_DACR_CKB_EN_POS) -#define AUDIO_DACR_CKB_EN_UMSK (~(((1U << AUDIO_DACR_CKB_EN_LEN) - 1) << AUDIO_DACR_CKB_EN_POS)) -#define AUDIO_DACL_LINEOUT_GAIN AUDIO_DACL_LINEOUT_GAIN -#define AUDIO_DACL_LINEOUT_GAIN_POS (16U) -#define AUDIO_DACL_LINEOUT_GAIN_LEN (3U) -#define AUDIO_DACL_LINEOUT_GAIN_MSK (((1U << AUDIO_DACL_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACL_LINEOUT_GAIN_POS) -#define AUDIO_DACL_LINEOUT_GAIN_UMSK (~(((1U << AUDIO_DACL_LINEOUT_GAIN_LEN) - 1) << AUDIO_DACL_LINEOUT_GAIN_POS)) -#define AUDIO_DACL_EN_LINEOUT AUDIO_DACL_EN_LINEOUT -#define AUDIO_DACL_EN_LINEOUT_POS (19U) -#define AUDIO_DACL_EN_LINEOUT_LEN (1U) -#define AUDIO_DACL_EN_LINEOUT_MSK (((1U << AUDIO_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DACL_EN_LINEOUT_POS) -#define AUDIO_DACL_EN_LINEOUT_UMSK (~(((1U << AUDIO_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DACL_EN_LINEOUT_POS)) -#define AUDIO_DACL_EN_DAC AUDIO_DACL_EN_DAC -#define AUDIO_DACL_EN_DAC_POS (20U) -#define AUDIO_DACL_EN_DAC_LEN (1U) -#define AUDIO_DACL_EN_DAC_MSK (((1U << AUDIO_DACL_EN_DAC_LEN) - 1) << AUDIO_DACL_EN_DAC_POS) -#define AUDIO_DACL_EN_DAC_UMSK (~(((1U << AUDIO_DACL_EN_DAC_LEN) - 1) << AUDIO_DACL_EN_DAC_POS)) -#define AUDIO_DACL_LINEOUT_MODE AUDIO_DACL_LINEOUT_MODE -#define AUDIO_DACL_LINEOUT_MODE_POS (22U) -#define AUDIO_DACL_LINEOUT_MODE_LEN (1U) -#define AUDIO_DACL_LINEOUT_MODE_MSK (((1U << AUDIO_DACL_LINEOUT_MODE_LEN) - 1) << AUDIO_DACL_LINEOUT_MODE_POS) -#define AUDIO_DACL_LINEOUT_MODE_UMSK (~(((1U << AUDIO_DACL_LINEOUT_MODE_LEN) - 1) << AUDIO_DACL_LINEOUT_MODE_POS)) -#define AUDIO_DACL_ICTRL_LINEOUT AUDIO_DACL_ICTRL_LINEOUT -#define AUDIO_DACL_ICTRL_LINEOUT_POS (24U) -#define AUDIO_DACL_ICTRL_LINEOUT_LEN (2U) -#define AUDIO_DACL_ICTRL_LINEOUT_MSK (((1U << AUDIO_DACL_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACL_ICTRL_LINEOUT_POS) -#define AUDIO_DACL_ICTRL_LINEOUT_UMSK (~(((1U << AUDIO_DACL_ICTRL_LINEOUT_LEN) - 1) << AUDIO_DACL_ICTRL_LINEOUT_POS)) -#define AUDIO_DACL_SDAC_LINEOUT AUDIO_DACL_SDAC_LINEOUT -#define AUDIO_DACL_SDAC_LINEOUT_POS (26U) -#define AUDIO_DACL_SDAC_LINEOUT_LEN (1U) -#define AUDIO_DACL_SDAC_LINEOUT_MSK (((1U << AUDIO_DACL_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACL_SDAC_LINEOUT_POS) -#define AUDIO_DACL_SDAC_LINEOUT_UMSK (~(((1U << AUDIO_DACL_SDAC_LINEOUT_LEN) - 1) << AUDIO_DACL_SDAC_LINEOUT_POS)) -#define AUDIO_DACL_SDEBUG_LINEOUT AUDIO_DACL_SDEBUG_LINEOUT -#define AUDIO_DACL_SDEBUG_LINEOUT_POS (27U) -#define AUDIO_DACL_SDEBUG_LINEOUT_LEN (1U) -#define AUDIO_DACL_SDEBUG_LINEOUT_MSK (((1U << AUDIO_DACL_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACL_SDEBUG_LINEOUT_POS) -#define AUDIO_DACL_SDEBUG_LINEOUT_UMSK (~(((1U << AUDIO_DACL_SDEBUG_LINEOUT_LEN) - 1) << AUDIO_DACL_SDEBUG_LINEOUT_POS)) -#define AUDIO_DACL_ICTRL_DAC AUDIO_DACL_ICTRL_DAC -#define AUDIO_DACL_ICTRL_DAC_POS (28U) -#define AUDIO_DACL_ICTRL_DAC_LEN (2U) -#define AUDIO_DACL_ICTRL_DAC_MSK (((1U << AUDIO_DACL_ICTRL_DAC_LEN) - 1) << AUDIO_DACL_ICTRL_DAC_POS) -#define AUDIO_DACL_ICTRL_DAC_UMSK (~(((1U << AUDIO_DACL_ICTRL_DAC_LEN) - 1) << AUDIO_DACL_ICTRL_DAC_POS)) -#define AUDIO_DACL_CKB_EN AUDIO_DACL_CKB_EN -#define AUDIO_DACL_CKB_EN_POS (30U) -#define AUDIO_DACL_CKB_EN_LEN (1U) -#define AUDIO_DACL_CKB_EN_MSK (((1U << AUDIO_DACL_CKB_EN_LEN) - 1) << AUDIO_DACL_CKB_EN_POS) -#define AUDIO_DACL_CKB_EN_UMSK (~(((1U << AUDIO_DACL_CKB_EN_LEN) - 1) << AUDIO_DACL_CKB_EN_POS)) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_POS (31U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_LEN (1U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_MSK (((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_POS) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_UMSK (~(((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_BUSY_POS)) - -/* 0x70C : codec_dac_ramp */ -#define AUDIO_CODEC_DAC_RAMP_OFFSET (0x70C) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_POS (0U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_LEN (1U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_MSK (((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_POS) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_UMSK (~(((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN_POS)) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_POS (1U) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_LEN (1U) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_MSK (((1U << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_LEN) - 1) << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_POS) -#define AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_UMSK (~(((1U << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_LEN) - 1) << AUDIO_DAC_RG_LINEOUT_VO_PULLDOWN_POS)) -#define AUDIO_DAC_RG_PU_VREF_RAMP AUDIO_DAC_RG_PU_VREF_RAMP -#define AUDIO_DAC_RG_PU_VREF_RAMP_POS (2U) -#define AUDIO_DAC_RG_PU_VREF_RAMP_LEN (1U) -#define AUDIO_DAC_RG_PU_VREF_RAMP_MSK (((1U << AUDIO_DAC_RG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DAC_RG_PU_VREF_RAMP_POS) -#define AUDIO_DAC_RG_PU_VREF_RAMP_UMSK (~(((1U << AUDIO_DAC_RG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DAC_RG_PU_VREF_RAMP_POS)) -#define AUDIO_DAC_RG_PU_LINEOUT AUDIO_DAC_RG_PU_LINEOUT -#define AUDIO_DAC_RG_PU_LINEOUT_POS (3U) -#define AUDIO_DAC_RG_PU_LINEOUT_LEN (1U) -#define AUDIO_DAC_RG_PU_LINEOUT_MSK (((1U << AUDIO_DAC_RG_PU_LINEOUT_LEN) - 1) << AUDIO_DAC_RG_PU_LINEOUT_POS) -#define AUDIO_DAC_RG_PU_LINEOUT_UMSK (~(((1U << AUDIO_DAC_RG_PU_LINEOUT_LEN) - 1) << AUDIO_DAC_RG_PU_LINEOUT_POS)) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T AUDIO_DAC_RG_VREF_RAMP_STEP_T -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_POS (4U) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_LEN (3U) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_MSK (((1U << AUDIO_DAC_RG_VREF_RAMP_STEP_T_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_STEP_T_POS) -#define AUDIO_DAC_RG_VREF_RAMP_STEP_T_UMSK (~(((1U << AUDIO_DAC_RG_VREF_RAMP_STEP_T_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_STEP_T_POS)) -#define AUDIO_DAC_RG_SW_VREF AUDIO_DAC_RG_SW_VREF -#define AUDIO_DAC_RG_SW_VREF_POS (7U) -#define AUDIO_DAC_RG_SW_VREF_LEN (1U) -#define AUDIO_DAC_RG_SW_VREF_MSK (((1U << AUDIO_DAC_RG_SW_VREF_LEN) - 1) << AUDIO_DAC_RG_SW_VREF_POS) -#define AUDIO_DAC_RG_SW_VREF_UMSK (~(((1U << AUDIO_DAC_RG_SW_VREF_LEN) - 1) << AUDIO_DAC_RG_SW_VREF_POS)) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY AUDIO_DAC_RG_VREF_RAMP_DELAY -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_POS (8U) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_LEN (2U) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_MSK (((1U << AUDIO_DAC_RG_VREF_RAMP_DELAY_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DELAY_POS) -#define AUDIO_DAC_RG_VREF_RAMP_DELAY_UMSK (~(((1U << AUDIO_DAC_RG_VREF_RAMP_DELAY_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DELAY_POS)) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD AUDIO_DAC_RG_LO_VREF_RAMP_DVLD -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_POS (10U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_LEN (1U) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_MSK (((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_POS) -#define AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_UMSK (~(((1U << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_LEN) - 1) << AUDIO_DAC_RG_LO_VREF_RAMP_DVLD_POS)) -#define AUDIO_DAC_AUTOMUTE_EN AUDIO_DAC_AUTOMUTE_EN -#define AUDIO_DAC_AUTOMUTE_EN_POS (11U) -#define AUDIO_DAC_AUTOMUTE_EN_LEN (1U) -#define AUDIO_DAC_AUTOMUTE_EN_MSK (((1U << AUDIO_DAC_AUTOMUTE_EN_LEN) - 1) << AUDIO_DAC_AUTOMUTE_EN_POS) -#define AUDIO_DAC_AUTOMUTE_EN_UMSK (~(((1U << AUDIO_DAC_AUTOMUTE_EN_LEN) - 1) << AUDIO_DAC_AUTOMUTE_EN_POS)) -#define AUDIO_DG_DAC_MUTE AUDIO_DG_DAC_MUTE -#define AUDIO_DG_DAC_MUTE_POS (12U) -#define AUDIO_DG_DAC_MUTE_LEN (1U) -#define AUDIO_DG_DAC_MUTE_MSK (((1U << AUDIO_DG_DAC_MUTE_LEN) - 1) << AUDIO_DG_DAC_MUTE_POS) -#define AUDIO_DG_DAC_MUTE_UMSK (~(((1U << AUDIO_DG_DAC_MUTE_LEN) - 1) << AUDIO_DG_DAC_MUTE_POS)) -#define AUDIO_DG_VO_PULLDOWN AUDIO_DG_VO_PULLDOWN -#define AUDIO_DG_VO_PULLDOWN_POS (13U) -#define AUDIO_DG_VO_PULLDOWN_LEN (1U) -#define AUDIO_DG_VO_PULLDOWN_MSK (((1U << AUDIO_DG_VO_PULLDOWN_LEN) - 1) << AUDIO_DG_VO_PULLDOWN_POS) -#define AUDIO_DG_VO_PULLDOWN_UMSK (~(((1U << AUDIO_DG_VO_PULLDOWN_LEN) - 1) << AUDIO_DG_VO_PULLDOWN_POS)) -#define AUDIO_DG_PU_VREF_RAMP AUDIO_DG_PU_VREF_RAMP -#define AUDIO_DG_PU_VREF_RAMP_POS (14U) -#define AUDIO_DG_PU_VREF_RAMP_LEN (1U) -#define AUDIO_DG_PU_VREF_RAMP_MSK (((1U << AUDIO_DG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DG_PU_VREF_RAMP_POS) -#define AUDIO_DG_PU_VREF_RAMP_UMSK (~(((1U << AUDIO_DG_PU_VREF_RAMP_LEN) - 1) << AUDIO_DG_PU_VREF_RAMP_POS)) -#define AUDIO_DG_VREF_RAMP_STEP AUDIO_DG_VREF_RAMP_STEP -#define AUDIO_DG_VREF_RAMP_STEP_POS (15U) -#define AUDIO_DG_VREF_RAMP_STEP_LEN (12U) -#define AUDIO_DG_VREF_RAMP_STEP_MSK (((1U << AUDIO_DG_VREF_RAMP_STEP_LEN) - 1) << AUDIO_DG_VREF_RAMP_STEP_POS) -#define AUDIO_DG_VREF_RAMP_STEP_UMSK (~(((1U << AUDIO_DG_VREF_RAMP_STEP_LEN) - 1) << AUDIO_DG_VREF_RAMP_STEP_POS)) -#define AUDIO_DG_SW_VREF AUDIO_DG_SW_VREF -#define AUDIO_DG_SW_VREF_POS (27U) -#define AUDIO_DG_SW_VREF_LEN (1U) -#define AUDIO_DG_SW_VREF_MSK (((1U << AUDIO_DG_SW_VREF_LEN) - 1) << AUDIO_DG_SW_VREF_POS) -#define AUDIO_DG_SW_VREF_UMSK (~(((1U << AUDIO_DG_SW_VREF_LEN) - 1) << AUDIO_DG_SW_VREF_POS)) -#define AUDIO_DG_DACR_EN_LINEOUT AUDIO_DG_DACR_EN_LINEOUT -#define AUDIO_DG_DACR_EN_LINEOUT_POS (28U) -#define AUDIO_DG_DACR_EN_LINEOUT_LEN (1U) -#define AUDIO_DG_DACR_EN_LINEOUT_MSK (((1U << AUDIO_DG_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACR_EN_LINEOUT_POS) -#define AUDIO_DG_DACR_EN_LINEOUT_UMSK (~(((1U << AUDIO_DG_DACR_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACR_EN_LINEOUT_POS)) -#define AUDIO_DG_DACL_EN_LINEOUT AUDIO_DG_DACL_EN_LINEOUT -#define AUDIO_DG_DACL_EN_LINEOUT_POS (29U) -#define AUDIO_DG_DACL_EN_LINEOUT_LEN (1U) -#define AUDIO_DG_DACL_EN_LINEOUT_MSK (((1U << AUDIO_DG_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACL_EN_LINEOUT_POS) -#define AUDIO_DG_DACL_EN_LINEOUT_UMSK (~(((1U << AUDIO_DG_DACL_EN_LINEOUT_LEN) - 1) << AUDIO_DG_DACL_EN_LINEOUT_POS)) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE AUDIO_DAC_RG_VREF_RAMP_DCL_MODE -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_POS (30U) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_LEN (2U) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_MSK (((1U << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_POS) -#define AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_UMSK (~(((1U << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_LEN) - 1) << AUDIO_DAC_RG_VREF_RAMP_DCL_MODE_POS)) - -/* 0x710 : codec_adc0 */ -#define AUDIO_CODEC_ADC0_OFFSET (0x710) -#define AUDIO_ADC0_SDM_LP AUDIO_ADC0_SDM_LP -#define AUDIO_ADC0_SDM_LP_POS (0U) -#define AUDIO_ADC0_SDM_LP_LEN (1U) -#define AUDIO_ADC0_SDM_LP_MSK (((1U << AUDIO_ADC0_SDM_LP_LEN) - 1) << AUDIO_ADC0_SDM_LP_POS) -#define AUDIO_ADC0_SDM_LP_UMSK (~(((1U << AUDIO_ADC0_SDM_LP_LEN) - 1) << AUDIO_ADC0_SDM_LP_POS)) -#define AUDIO_ADC0_CKB_EN AUDIO_ADC0_CKB_EN -#define AUDIO_ADC0_CKB_EN_POS (1U) -#define AUDIO_ADC0_CKB_EN_LEN (1U) -#define AUDIO_ADC0_CKB_EN_MSK (((1U << AUDIO_ADC0_CKB_EN_LEN) - 1) << AUDIO_ADC0_CKB_EN_POS) -#define AUDIO_ADC0_CKB_EN_UMSK (~(((1U << AUDIO_ADC0_CKB_EN_LEN) - 1) << AUDIO_ADC0_CKB_EN_POS)) -#define AUDIO_ADC0_REG_RESEV AUDIO_ADC0_REG_RESEV -#define AUDIO_ADC0_REG_RESEV_POS (2U) -#define AUDIO_ADC0_REG_RESEV_LEN (1U) -#define AUDIO_ADC0_REG_RESEV_MSK (((1U << AUDIO_ADC0_REG_RESEV_LEN) - 1) << AUDIO_ADC0_REG_RESEV_POS) -#define AUDIO_ADC0_REG_RESEV_UMSK (~(((1U << AUDIO_ADC0_REG_RESEV_LEN) - 1) << AUDIO_ADC0_REG_RESEV_POS)) -#define AUDIO_ADC0_PGA_RCM_SEL AUDIO_ADC0_PGA_RCM_SEL -#define AUDIO_ADC0_PGA_RCM_SEL_POS (4U) -#define AUDIO_ADC0_PGA_RCM_SEL_LEN (2U) -#define AUDIO_ADC0_PGA_RCM_SEL_MSK (((1U << AUDIO_ADC0_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC0_PGA_RCM_SEL_POS) -#define AUDIO_ADC0_PGA_RCM_SEL_UMSK (~(((1U << AUDIO_ADC0_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC0_PGA_RCM_SEL_POS)) -#define AUDIO_ADC0_PGA_GAIN AUDIO_ADC0_PGA_GAIN -#define AUDIO_ADC0_PGA_GAIN_POS (8U) -#define AUDIO_ADC0_PGA_GAIN_LEN (4U) -#define AUDIO_ADC0_PGA_GAIN_MSK (((1U << AUDIO_ADC0_PGA_GAIN_LEN) - 1) << AUDIO_ADC0_PGA_GAIN_POS) -#define AUDIO_ADC0_PGA_GAIN_UMSK (~(((1U << AUDIO_ADC0_PGA_GAIN_LEN) - 1) << AUDIO_ADC0_PGA_GAIN_POS)) -#define AUDIO_ADC0_ICTRL_MIC AUDIO_ADC0_ICTRL_MIC -#define AUDIO_ADC0_ICTRL_MIC_POS (12U) -#define AUDIO_ADC0_ICTRL_MIC_LEN (2U) -#define AUDIO_ADC0_ICTRL_MIC_MSK (((1U << AUDIO_ADC0_ICTRL_MIC_LEN) - 1) << AUDIO_ADC0_ICTRL_MIC_POS) -#define AUDIO_ADC0_ICTRL_MIC_UMSK (~(((1U << AUDIO_ADC0_ICTRL_MIC_LEN) - 1) << AUDIO_ADC0_ICTRL_MIC_POS)) -#define AUDIO_ADC0_ICTRL_ADC2 AUDIO_ADC0_ICTRL_ADC2 -#define AUDIO_ADC0_ICTRL_ADC2_POS (14U) -#define AUDIO_ADC0_ICTRL_ADC2_LEN (2U) -#define AUDIO_ADC0_ICTRL_ADC2_MSK (((1U << AUDIO_ADC0_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC2_POS) -#define AUDIO_ADC0_ICTRL_ADC2_UMSK (~(((1U << AUDIO_ADC0_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC2_POS)) -#define AUDIO_ADC0_ICTRL_ADC1 AUDIO_ADC0_ICTRL_ADC1 -#define AUDIO_ADC0_ICTRL_ADC1_POS (16U) -#define AUDIO_ADC0_ICTRL_ADC1_LEN (2U) -#define AUDIO_ADC0_ICTRL_ADC1_MSK (((1U << AUDIO_ADC0_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC1_POS) -#define AUDIO_ADC0_ICTRL_ADC1_UMSK (~(((1U << AUDIO_ADC0_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC0_ICTRL_ADC1_POS)) -#define AUDIO_ADC0_ICTRL_AAF AUDIO_ADC0_ICTRL_AAF -#define AUDIO_ADC0_ICTRL_AAF_POS (18U) -#define AUDIO_ADC0_ICTRL_AAF_LEN (2U) -#define AUDIO_ADC0_ICTRL_AAF_MSK (((1U << AUDIO_ADC0_ICTRL_AAF_LEN) - 1) << AUDIO_ADC0_ICTRL_AAF_POS) -#define AUDIO_ADC0_ICTRL_AAF_UMSK (~(((1U << AUDIO_ADC0_ICTRL_AAF_LEN) - 1) << AUDIO_ADC0_ICTRL_AAF_POS)) -#define AUDIO_ADC0_EN_SDM AUDIO_ADC0_EN_SDM -#define AUDIO_ADC0_EN_SDM_POS (20U) -#define AUDIO_ADC0_EN_SDM_LEN (1U) -#define AUDIO_ADC0_EN_SDM_MSK (((1U << AUDIO_ADC0_EN_SDM_LEN) - 1) << AUDIO_ADC0_EN_SDM_POS) -#define AUDIO_ADC0_EN_SDM_UMSK (~(((1U << AUDIO_ADC0_EN_SDM_LEN) - 1) << AUDIO_ADC0_EN_SDM_POS)) -#define AUDIO_ADC0_EN_PGA AUDIO_ADC0_EN_PGA -#define AUDIO_ADC0_EN_PGA_POS (21U) -#define AUDIO_ADC0_EN_PGA_LEN (1U) -#define AUDIO_ADC0_EN_PGA_MSK (((1U << AUDIO_ADC0_EN_PGA_LEN) - 1) << AUDIO_ADC0_EN_PGA_POS) -#define AUDIO_ADC0_EN_PGA_UMSK (~(((1U << AUDIO_ADC0_EN_PGA_LEN) - 1) << AUDIO_ADC0_EN_PGA_POS)) -#define AUDIO_ADC_DITHER_SEL AUDIO_ADC_DITHER_SEL -#define AUDIO_ADC_DITHER_SEL_POS (22U) -#define AUDIO_ADC_DITHER_SEL_LEN (2U) -#define AUDIO_ADC_DITHER_SEL_MSK (((1U << AUDIO_ADC_DITHER_SEL_LEN) - 1) << AUDIO_ADC_DITHER_SEL_POS) -#define AUDIO_ADC_DITHER_SEL_UMSK (~(((1U << AUDIO_ADC_DITHER_SEL_LEN) - 1) << AUDIO_ADC_DITHER_SEL_POS)) - -/* 0x714 : codec_adc1 */ -#define AUDIO_CODEC_ADC1_OFFSET (0x714) -#define AUDIO_ADC1_SDM_LP AUDIO_ADC1_SDM_LP -#define AUDIO_ADC1_SDM_LP_POS (0U) -#define AUDIO_ADC1_SDM_LP_LEN (1U) -#define AUDIO_ADC1_SDM_LP_MSK (((1U << AUDIO_ADC1_SDM_LP_LEN) - 1) << AUDIO_ADC1_SDM_LP_POS) -#define AUDIO_ADC1_SDM_LP_UMSK (~(((1U << AUDIO_ADC1_SDM_LP_LEN) - 1) << AUDIO_ADC1_SDM_LP_POS)) -#define AUDIO_ADC1_CKB_EN AUDIO_ADC1_CKB_EN -#define AUDIO_ADC1_CKB_EN_POS (1U) -#define AUDIO_ADC1_CKB_EN_LEN (1U) -#define AUDIO_ADC1_CKB_EN_MSK (((1U << AUDIO_ADC1_CKB_EN_LEN) - 1) << AUDIO_ADC1_CKB_EN_POS) -#define AUDIO_ADC1_CKB_EN_UMSK (~(((1U << AUDIO_ADC1_CKB_EN_LEN) - 1) << AUDIO_ADC1_CKB_EN_POS)) -#define AUDIO_ADC1_REG_RESEV AUDIO_ADC1_REG_RESEV -#define AUDIO_ADC1_REG_RESEV_POS (2U) -#define AUDIO_ADC1_REG_RESEV_LEN (1U) -#define AUDIO_ADC1_REG_RESEV_MSK (((1U << AUDIO_ADC1_REG_RESEV_LEN) - 1) << AUDIO_ADC1_REG_RESEV_POS) -#define AUDIO_ADC1_REG_RESEV_UMSK (~(((1U << AUDIO_ADC1_REG_RESEV_LEN) - 1) << AUDIO_ADC1_REG_RESEV_POS)) -#define AUDIO_ADC1_PGA_RCM_SEL AUDIO_ADC1_PGA_RCM_SEL -#define AUDIO_ADC1_PGA_RCM_SEL_POS (4U) -#define AUDIO_ADC1_PGA_RCM_SEL_LEN (2U) -#define AUDIO_ADC1_PGA_RCM_SEL_MSK (((1U << AUDIO_ADC1_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC1_PGA_RCM_SEL_POS) -#define AUDIO_ADC1_PGA_RCM_SEL_UMSK (~(((1U << AUDIO_ADC1_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC1_PGA_RCM_SEL_POS)) -#define AUDIO_ADC1_PGA_GAIN AUDIO_ADC1_PGA_GAIN -#define AUDIO_ADC1_PGA_GAIN_POS (8U) -#define AUDIO_ADC1_PGA_GAIN_LEN (4U) -#define AUDIO_ADC1_PGA_GAIN_MSK (((1U << AUDIO_ADC1_PGA_GAIN_LEN) - 1) << AUDIO_ADC1_PGA_GAIN_POS) -#define AUDIO_ADC1_PGA_GAIN_UMSK (~(((1U << AUDIO_ADC1_PGA_GAIN_LEN) - 1) << AUDIO_ADC1_PGA_GAIN_POS)) -#define AUDIO_ADC1_ICTRL_MIC AUDIO_ADC1_ICTRL_MIC -#define AUDIO_ADC1_ICTRL_MIC_POS (12U) -#define AUDIO_ADC1_ICTRL_MIC_LEN (2U) -#define AUDIO_ADC1_ICTRL_MIC_MSK (((1U << AUDIO_ADC1_ICTRL_MIC_LEN) - 1) << AUDIO_ADC1_ICTRL_MIC_POS) -#define AUDIO_ADC1_ICTRL_MIC_UMSK (~(((1U << AUDIO_ADC1_ICTRL_MIC_LEN) - 1) << AUDIO_ADC1_ICTRL_MIC_POS)) -#define AUDIO_ADC1_ICTRL_ADC2 AUDIO_ADC1_ICTRL_ADC2 -#define AUDIO_ADC1_ICTRL_ADC2_POS (14U) -#define AUDIO_ADC1_ICTRL_ADC2_LEN (2U) -#define AUDIO_ADC1_ICTRL_ADC2_MSK (((1U << AUDIO_ADC1_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC2_POS) -#define AUDIO_ADC1_ICTRL_ADC2_UMSK (~(((1U << AUDIO_ADC1_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC2_POS)) -#define AUDIO_ADC1_ICTRL_ADC1 AUDIO_ADC1_ICTRL_ADC1 -#define AUDIO_ADC1_ICTRL_ADC1_POS (16U) -#define AUDIO_ADC1_ICTRL_ADC1_LEN (2U) -#define AUDIO_ADC1_ICTRL_ADC1_MSK (((1U << AUDIO_ADC1_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC1_POS) -#define AUDIO_ADC1_ICTRL_ADC1_UMSK (~(((1U << AUDIO_ADC1_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC1_ICTRL_ADC1_POS)) -#define AUDIO_ADC1_ICTRL_AAF AUDIO_ADC1_ICTRL_AAF -#define AUDIO_ADC1_ICTRL_AAF_POS (18U) -#define AUDIO_ADC1_ICTRL_AAF_LEN (2U) -#define AUDIO_ADC1_ICTRL_AAF_MSK (((1U << AUDIO_ADC1_ICTRL_AAF_LEN) - 1) << AUDIO_ADC1_ICTRL_AAF_POS) -#define AUDIO_ADC1_ICTRL_AAF_UMSK (~(((1U << AUDIO_ADC1_ICTRL_AAF_LEN) - 1) << AUDIO_ADC1_ICTRL_AAF_POS)) -#define AUDIO_ADC1_EN_SDM AUDIO_ADC1_EN_SDM -#define AUDIO_ADC1_EN_SDM_POS (20U) -#define AUDIO_ADC1_EN_SDM_LEN (1U) -#define AUDIO_ADC1_EN_SDM_MSK (((1U << AUDIO_ADC1_EN_SDM_LEN) - 1) << AUDIO_ADC1_EN_SDM_POS) -#define AUDIO_ADC1_EN_SDM_UMSK (~(((1U << AUDIO_ADC1_EN_SDM_LEN) - 1) << AUDIO_ADC1_EN_SDM_POS)) -#define AUDIO_ADC1_EN_PGA AUDIO_ADC1_EN_PGA -#define AUDIO_ADC1_EN_PGA_POS (21U) -#define AUDIO_ADC1_EN_PGA_LEN (1U) -#define AUDIO_ADC1_EN_PGA_MSK (((1U << AUDIO_ADC1_EN_PGA_LEN) - 1) << AUDIO_ADC1_EN_PGA_POS) -#define AUDIO_ADC1_EN_PGA_UMSK (~(((1U << AUDIO_ADC1_EN_PGA_LEN) - 1) << AUDIO_ADC1_EN_PGA_POS)) - -/* 0x718 : codec_adc2 */ -#define AUDIO_CODEC_ADC2_OFFSET (0x718) -#define AUDIO_ADC2_SDM_LP AUDIO_ADC2_SDM_LP -#define AUDIO_ADC2_SDM_LP_POS (0U) -#define AUDIO_ADC2_SDM_LP_LEN (1U) -#define AUDIO_ADC2_SDM_LP_MSK (((1U << AUDIO_ADC2_SDM_LP_LEN) - 1) << AUDIO_ADC2_SDM_LP_POS) -#define AUDIO_ADC2_SDM_LP_UMSK (~(((1U << AUDIO_ADC2_SDM_LP_LEN) - 1) << AUDIO_ADC2_SDM_LP_POS)) -#define AUDIO_ADC2_CKB_EN AUDIO_ADC2_CKB_EN -#define AUDIO_ADC2_CKB_EN_POS (1U) -#define AUDIO_ADC2_CKB_EN_LEN (1U) -#define AUDIO_ADC2_CKB_EN_MSK (((1U << AUDIO_ADC2_CKB_EN_LEN) - 1) << AUDIO_ADC2_CKB_EN_POS) -#define AUDIO_ADC2_CKB_EN_UMSK (~(((1U << AUDIO_ADC2_CKB_EN_LEN) - 1) << AUDIO_ADC2_CKB_EN_POS)) -#define AUDIO_ADC2_REG_RESEV AUDIO_ADC2_REG_RESEV -#define AUDIO_ADC2_REG_RESEV_POS (2U) -#define AUDIO_ADC2_REG_RESEV_LEN (1U) -#define AUDIO_ADC2_REG_RESEV_MSK (((1U << AUDIO_ADC2_REG_RESEV_LEN) - 1) << AUDIO_ADC2_REG_RESEV_POS) -#define AUDIO_ADC2_REG_RESEV_UMSK (~(((1U << AUDIO_ADC2_REG_RESEV_LEN) - 1) << AUDIO_ADC2_REG_RESEV_POS)) -#define AUDIO_ADC2_PGA_RCM_SEL AUDIO_ADC2_PGA_RCM_SEL -#define AUDIO_ADC2_PGA_RCM_SEL_POS (4U) -#define AUDIO_ADC2_PGA_RCM_SEL_LEN (2U) -#define AUDIO_ADC2_PGA_RCM_SEL_MSK (((1U << AUDIO_ADC2_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC2_PGA_RCM_SEL_POS) -#define AUDIO_ADC2_PGA_RCM_SEL_UMSK (~(((1U << AUDIO_ADC2_PGA_RCM_SEL_LEN) - 1) << AUDIO_ADC2_PGA_RCM_SEL_POS)) -#define AUDIO_ADC2_PGA_GAIN AUDIO_ADC2_PGA_GAIN -#define AUDIO_ADC2_PGA_GAIN_POS (8U) -#define AUDIO_ADC2_PGA_GAIN_LEN (4U) -#define AUDIO_ADC2_PGA_GAIN_MSK (((1U << AUDIO_ADC2_PGA_GAIN_LEN) - 1) << AUDIO_ADC2_PGA_GAIN_POS) -#define AUDIO_ADC2_PGA_GAIN_UMSK (~(((1U << AUDIO_ADC2_PGA_GAIN_LEN) - 1) << AUDIO_ADC2_PGA_GAIN_POS)) -#define AUDIO_ADC2_ICTRL_MIC AUDIO_ADC2_ICTRL_MIC -#define AUDIO_ADC2_ICTRL_MIC_POS (12U) -#define AUDIO_ADC2_ICTRL_MIC_LEN (2U) -#define AUDIO_ADC2_ICTRL_MIC_MSK (((1U << AUDIO_ADC2_ICTRL_MIC_LEN) - 1) << AUDIO_ADC2_ICTRL_MIC_POS) -#define AUDIO_ADC2_ICTRL_MIC_UMSK (~(((1U << AUDIO_ADC2_ICTRL_MIC_LEN) - 1) << AUDIO_ADC2_ICTRL_MIC_POS)) -#define AUDIO_ADC2_ICTRL_ADC2 AUDIO_ADC2_ICTRL_ADC2 -#define AUDIO_ADC2_ICTRL_ADC2_POS (14U) -#define AUDIO_ADC2_ICTRL_ADC2_LEN (2U) -#define AUDIO_ADC2_ICTRL_ADC2_MSK (((1U << AUDIO_ADC2_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC2_POS) -#define AUDIO_ADC2_ICTRL_ADC2_UMSK (~(((1U << AUDIO_ADC2_ICTRL_ADC2_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC2_POS)) -#define AUDIO_ADC2_ICTRL_ADC1 AUDIO_ADC2_ICTRL_ADC1 -#define AUDIO_ADC2_ICTRL_ADC1_POS (16U) -#define AUDIO_ADC2_ICTRL_ADC1_LEN (2U) -#define AUDIO_ADC2_ICTRL_ADC1_MSK (((1U << AUDIO_ADC2_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC1_POS) -#define AUDIO_ADC2_ICTRL_ADC1_UMSK (~(((1U << AUDIO_ADC2_ICTRL_ADC1_LEN) - 1) << AUDIO_ADC2_ICTRL_ADC1_POS)) -#define AUDIO_ADC2_ICTRL_AAF AUDIO_ADC2_ICTRL_AAF -#define AUDIO_ADC2_ICTRL_AAF_POS (18U) -#define AUDIO_ADC2_ICTRL_AAF_LEN (2U) -#define AUDIO_ADC2_ICTRL_AAF_MSK (((1U << AUDIO_ADC2_ICTRL_AAF_LEN) - 1) << AUDIO_ADC2_ICTRL_AAF_POS) -#define AUDIO_ADC2_ICTRL_AAF_UMSK (~(((1U << AUDIO_ADC2_ICTRL_AAF_LEN) - 1) << AUDIO_ADC2_ICTRL_AAF_POS)) -#define AUDIO_ADC2_EN_SDM AUDIO_ADC2_EN_SDM -#define AUDIO_ADC2_EN_SDM_POS (20U) -#define AUDIO_ADC2_EN_SDM_LEN (1U) -#define AUDIO_ADC2_EN_SDM_MSK (((1U << AUDIO_ADC2_EN_SDM_LEN) - 1) << AUDIO_ADC2_EN_SDM_POS) -#define AUDIO_ADC2_EN_SDM_UMSK (~(((1U << AUDIO_ADC2_EN_SDM_LEN) - 1) << AUDIO_ADC2_EN_SDM_POS)) -#define AUDIO_ADC2_EN_PGA AUDIO_ADC2_EN_PGA -#define AUDIO_ADC2_EN_PGA_POS (21U) -#define AUDIO_ADC2_EN_PGA_LEN (1U) -#define AUDIO_ADC2_EN_PGA_MSK (((1U << AUDIO_ADC2_EN_PGA_LEN) - 1) << AUDIO_ADC2_EN_PGA_POS) -#define AUDIO_ADC2_EN_PGA_UMSK (~(((1U << AUDIO_ADC2_EN_PGA_LEN) - 1) << AUDIO_ADC2_EN_PGA_POS)) - -/* 0x800 : padc_ana_cfg1 */ -#define AUDIO_PADC_ANA_CFG1_OFFSET (0x800) -#define AUDIO_PADC_PGA_CHOP_CKSEL AUDIO_PADC_PGA_CHOP_CKSEL -#define AUDIO_PADC_PGA_CHOP_CKSEL_POS (0U) -#define AUDIO_PADC_PGA_CHOP_CKSEL_LEN (1U) -#define AUDIO_PADC_PGA_CHOP_CKSEL_MSK (((1U << AUDIO_PADC_PGA_CHOP_CKSEL_LEN) - 1) << AUDIO_PADC_PGA_CHOP_CKSEL_POS) -#define AUDIO_PADC_PGA_CHOP_CKSEL_UMSK (~(((1U << AUDIO_PADC_PGA_CHOP_CKSEL_LEN) - 1) << AUDIO_PADC_PGA_CHOP_CKSEL_POS)) -#define AUDIO_PADC_PGA_CHOP_FREQ AUDIO_PADC_PGA_CHOP_FREQ -#define AUDIO_PADC_PGA_CHOP_FREQ_POS (1U) -#define AUDIO_PADC_PGA_CHOP_FREQ_LEN (3U) -#define AUDIO_PADC_PGA_CHOP_FREQ_MSK (((1U << AUDIO_PADC_PGA_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_PGA_CHOP_FREQ_POS) -#define AUDIO_PADC_PGA_CHOP_FREQ_UMSK (~(((1U << AUDIO_PADC_PGA_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_PGA_CHOP_FREQ_POS)) -#define AUDIO_PADC_PGA_CHOP_EN AUDIO_PADC_PGA_CHOP_EN -#define AUDIO_PADC_PGA_CHOP_EN_POS (4U) -#define AUDIO_PADC_PGA_CHOP_EN_LEN (1U) -#define AUDIO_PADC_PGA_CHOP_EN_MSK (((1U << AUDIO_PADC_PGA_CHOP_EN_LEN) - 1) << AUDIO_PADC_PGA_CHOP_EN_POS) -#define AUDIO_PADC_PGA_CHOP_EN_UMSK (~(((1U << AUDIO_PADC_PGA_CHOP_EN_LEN) - 1) << AUDIO_PADC_PGA_CHOP_EN_POS)) -#define AUDIO_PADC_PGA_NOISCTRL AUDIO_PADC_PGA_NOISCTRL -#define AUDIO_PADC_PGA_NOISCTRL_POS (5U) -#define AUDIO_PADC_PGA_NOISCTRL_LEN (2U) -#define AUDIO_PADC_PGA_NOISCTRL_MSK (((1U << AUDIO_PADC_PGA_NOISCTRL_LEN) - 1) << AUDIO_PADC_PGA_NOISCTRL_POS) -#define AUDIO_PADC_PGA_NOISCTRL_UMSK (~(((1U << AUDIO_PADC_PGA_NOISCTRL_LEN) - 1) << AUDIO_PADC_PGA_NOISCTRL_POS)) -#define AUDIO_PADC_ICTRL_PGA_BUF AUDIO_PADC_ICTRL_PGA_BUF -#define AUDIO_PADC_ICTRL_PGA_BUF_POS (7U) -#define AUDIO_PADC_ICTRL_PGA_BUF_LEN (2U) -#define AUDIO_PADC_ICTRL_PGA_BUF_MSK (((1U << AUDIO_PADC_ICTRL_PGA_BUF_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_BUF_POS) -#define AUDIO_PADC_ICTRL_PGA_BUF_UMSK (~(((1U << AUDIO_PADC_ICTRL_PGA_BUF_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_BUF_POS)) -#define AUDIO_PADC_ICTRL_PGA_IA AUDIO_PADC_ICTRL_PGA_IA -#define AUDIO_PADC_ICTRL_PGA_IA_POS (9U) -#define AUDIO_PADC_ICTRL_PGA_IA_LEN (2U) -#define AUDIO_PADC_ICTRL_PGA_IA_MSK (((1U << AUDIO_PADC_ICTRL_PGA_IA_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_IA_POS) -#define AUDIO_PADC_ICTRL_PGA_IA_UMSK (~(((1U << AUDIO_PADC_ICTRL_PGA_IA_LEN) - 1) << AUDIO_PADC_ICTRL_PGA_IA_POS)) -#define AUDIO_PADC_PGA_FORCE AUDIO_PADC_PGA_FORCE -#define AUDIO_PADC_PGA_FORCE_POS (11U) -#define AUDIO_PADC_PGA_FORCE_LEN (1U) -#define AUDIO_PADC_PGA_FORCE_MSK (((1U << AUDIO_PADC_PGA_FORCE_LEN) - 1) << AUDIO_PADC_PGA_FORCE_POS) -#define AUDIO_PADC_PGA_FORCE_UMSK (~(((1U << AUDIO_PADC_PGA_FORCE_LEN) - 1) << AUDIO_PADC_PGA_FORCE_POS)) -#define AUDIO_PADC_PGA_AUTOBPS_BUF AUDIO_PADC_PGA_AUTOBPS_BUF -#define AUDIO_PADC_PGA_AUTOBPS_BUF_POS (12U) -#define AUDIO_PADC_PGA_AUTOBPS_BUF_LEN (1U) -#define AUDIO_PADC_PGA_AUTOBPS_BUF_MSK (((1U << AUDIO_PADC_PGA_AUTOBPS_BUF_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_BUF_POS) -#define AUDIO_PADC_PGA_AUTOBPS_BUF_UMSK (~(((1U << AUDIO_PADC_PGA_AUTOBPS_BUF_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_BUF_POS)) -#define AUDIO_PADC_PGA_AUTOBPS_IA AUDIO_PADC_PGA_AUTOBPS_IA -#define AUDIO_PADC_PGA_AUTOBPS_IA_POS (13U) -#define AUDIO_PADC_PGA_AUTOBPS_IA_LEN (1U) -#define AUDIO_PADC_PGA_AUTOBPS_IA_MSK (((1U << AUDIO_PADC_PGA_AUTOBPS_IA_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_IA_POS) -#define AUDIO_PADC_PGA_AUTOBPS_IA_UMSK (~(((1U << AUDIO_PADC_PGA_AUTOBPS_IA_LEN) - 1) << AUDIO_PADC_PGA_AUTOBPS_IA_POS)) -#define AUDIO_PADC_PGA_MODE AUDIO_PADC_PGA_MODE -#define AUDIO_PADC_PGA_MODE_POS (14U) -#define AUDIO_PADC_PGA_MODE_LEN (2U) -#define AUDIO_PADC_PGA_MODE_MSK (((1U << AUDIO_PADC_PGA_MODE_LEN) - 1) << AUDIO_PADC_PGA_MODE_POS) -#define AUDIO_PADC_PGA_MODE_UMSK (~(((1U << AUDIO_PADC_PGA_MODE_LEN) - 1) << AUDIO_PADC_PGA_MODE_POS)) -#define AUDIO_PADC_AFEVCM_ROUT AUDIO_PADC_AFEVCM_ROUT -#define AUDIO_PADC_AFEVCM_ROUT_POS (16U) -#define AUDIO_PADC_AFEVCM_ROUT_LEN (2U) -#define AUDIO_PADC_AFEVCM_ROUT_MSK (((1U << AUDIO_PADC_AFEVCM_ROUT_LEN) - 1) << AUDIO_PADC_AFEVCM_ROUT_POS) -#define AUDIO_PADC_AFEVCM_ROUT_UMSK (~(((1U << AUDIO_PADC_AFEVCM_ROUT_LEN) - 1) << AUDIO_PADC_AFEVCM_ROUT_POS)) -#define AUDIO_PADC_AFEVCM_SEL AUDIO_PADC_AFEVCM_SEL -#define AUDIO_PADC_AFEVCM_SEL_POS (18U) -#define AUDIO_PADC_AFEVCM_SEL_LEN (1U) -#define AUDIO_PADC_AFEVCM_SEL_MSK (((1U << AUDIO_PADC_AFEVCM_SEL_LEN) - 1) << AUDIO_PADC_AFEVCM_SEL_POS) -#define AUDIO_PADC_AFEVCM_SEL_UMSK (~(((1U << AUDIO_PADC_AFEVCM_SEL_LEN) - 1) << AUDIO_PADC_AFEVCM_SEL_POS)) -#define AUDIO_PADC_CKB_EN AUDIO_PADC_CKB_EN -#define AUDIO_PADC_CKB_EN_POS (19U) -#define AUDIO_PADC_CKB_EN_LEN (1U) -#define AUDIO_PADC_CKB_EN_MSK (((1U << AUDIO_PADC_CKB_EN_LEN) - 1) << AUDIO_PADC_CKB_EN_POS) -#define AUDIO_PADC_CKB_EN_UMSK (~(((1U << AUDIO_PADC_CKB_EN_LEN) - 1) << AUDIO_PADC_CKB_EN_POS)) -#define AUDIO_PADC_SEL_EDGE AUDIO_PADC_SEL_EDGE -#define AUDIO_PADC_SEL_EDGE_POS (20U) -#define AUDIO_PADC_SEL_EDGE_LEN (1U) -#define AUDIO_PADC_SEL_EDGE_MSK (((1U << AUDIO_PADC_SEL_EDGE_LEN) - 1) << AUDIO_PADC_SEL_EDGE_POS) -#define AUDIO_PADC_SEL_EDGE_UMSK (~(((1U << AUDIO_PADC_SEL_EDGE_LEN) - 1) << AUDIO_PADC_SEL_EDGE_POS)) - -/* 0x804 : padc_ana_cfg2 */ -#define AUDIO_PADC_ANA_CFG2_OFFSET (0x804) -#define AUDIO_PADC_SDM_CHOP_PHAS AUDIO_PADC_SDM_CHOP_PHAS -#define AUDIO_PADC_SDM_CHOP_PHAS_POS (0U) -#define AUDIO_PADC_SDM_CHOP_PHAS_LEN (1U) -#define AUDIO_PADC_SDM_CHOP_PHAS_MSK (((1U << AUDIO_PADC_SDM_CHOP_PHAS_LEN) - 1) << AUDIO_PADC_SDM_CHOP_PHAS_POS) -#define AUDIO_PADC_SDM_CHOP_PHAS_UMSK (~(((1U << AUDIO_PADC_SDM_CHOP_PHAS_LEN) - 1) << AUDIO_PADC_SDM_CHOP_PHAS_POS)) -#define AUDIO_PADC_SDM_CHOP_FREQ AUDIO_PADC_SDM_CHOP_FREQ -#define AUDIO_PADC_SDM_CHOP_FREQ_POS (1U) -#define AUDIO_PADC_SDM_CHOP_FREQ_LEN (3U) -#define AUDIO_PADC_SDM_CHOP_FREQ_MSK (((1U << AUDIO_PADC_SDM_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_SDM_CHOP_FREQ_POS) -#define AUDIO_PADC_SDM_CHOP_FREQ_UMSK (~(((1U << AUDIO_PADC_SDM_CHOP_FREQ_LEN) - 1) << AUDIO_PADC_SDM_CHOP_FREQ_POS)) -#define AUDIO_PADC_SDM_CHOP_EN AUDIO_PADC_SDM_CHOP_EN -#define AUDIO_PADC_SDM_CHOP_EN_POS (4U) -#define AUDIO_PADC_SDM_CHOP_EN_LEN (1U) -#define AUDIO_PADC_SDM_CHOP_EN_MSK (((1U << AUDIO_PADC_SDM_CHOP_EN_LEN) - 1) << AUDIO_PADC_SDM_CHOP_EN_POS) -#define AUDIO_PADC_SDM_CHOP_EN_UMSK (~(((1U << AUDIO_PADC_SDM_CHOP_EN_LEN) - 1) << AUDIO_PADC_SDM_CHOP_EN_POS)) -#define AUDIO_PADC_DITHER_ORDER AUDIO_PADC_DITHER_ORDER -#define AUDIO_PADC_DITHER_ORDER_POS (5U) -#define AUDIO_PADC_DITHER_ORDER_LEN (1U) -#define AUDIO_PADC_DITHER_ORDER_MSK (((1U << AUDIO_PADC_DITHER_ORDER_LEN) - 1) << AUDIO_PADC_DITHER_ORDER_POS) -#define AUDIO_PADC_DITHER_ORDER_UMSK (~(((1U << AUDIO_PADC_DITHER_ORDER_LEN) - 1) << AUDIO_PADC_DITHER_ORDER_POS)) -#define AUDIO_PADC_DITHER_SEL AUDIO_PADC_DITHER_SEL -#define AUDIO_PADC_DITHER_SEL_POS (6U) -#define AUDIO_PADC_DITHER_SEL_LEN (2U) -#define AUDIO_PADC_DITHER_SEL_MSK (((1U << AUDIO_PADC_DITHER_SEL_LEN) - 1) << AUDIO_PADC_DITHER_SEL_POS) -#define AUDIO_PADC_DITHER_SEL_UMSK (~(((1U << AUDIO_PADC_DITHER_SEL_LEN) - 1) << AUDIO_PADC_DITHER_SEL_POS)) -#define AUDIO_PADC_QUAN_GAIN AUDIO_PADC_QUAN_GAIN -#define AUDIO_PADC_QUAN_GAIN_POS (8U) -#define AUDIO_PADC_QUAN_GAIN_LEN (2U) -#define AUDIO_PADC_QUAN_GAIN_MSK (((1U << AUDIO_PADC_QUAN_GAIN_LEN) - 1) << AUDIO_PADC_QUAN_GAIN_POS) -#define AUDIO_PADC_QUAN_GAIN_UMSK (~(((1U << AUDIO_PADC_QUAN_GAIN_LEN) - 1) << AUDIO_PADC_QUAN_GAIN_POS)) -#define AUDIO_PADC_DEM_EN AUDIO_PADC_DEM_EN -#define AUDIO_PADC_DEM_EN_POS (10U) -#define AUDIO_PADC_DEM_EN_LEN (1U) -#define AUDIO_PADC_DEM_EN_MSK (((1U << AUDIO_PADC_DEM_EN_LEN) - 1) << AUDIO_PADC_DEM_EN_POS) -#define AUDIO_PADC_DEM_EN_UMSK (~(((1U << AUDIO_PADC_DEM_EN_LEN) - 1) << AUDIO_PADC_DEM_EN_POS)) -#define AUDIO_PADC_NCTRL_ADC2 AUDIO_PADC_NCTRL_ADC2 -#define AUDIO_PADC_NCTRL_ADC2_POS (11U) -#define AUDIO_PADC_NCTRL_ADC2_LEN (1U) -#define AUDIO_PADC_NCTRL_ADC2_MSK (((1U << AUDIO_PADC_NCTRL_ADC2_LEN) - 1) << AUDIO_PADC_NCTRL_ADC2_POS) -#define AUDIO_PADC_NCTRL_ADC2_UMSK (~(((1U << AUDIO_PADC_NCTRL_ADC2_LEN) - 1) << AUDIO_PADC_NCTRL_ADC2_POS)) -#define AUDIO_PADC_NCTRL_ADC1 AUDIO_PADC_NCTRL_ADC1 -#define AUDIO_PADC_NCTRL_ADC1_POS (13U) -#define AUDIO_PADC_NCTRL_ADC1_LEN (2U) -#define AUDIO_PADC_NCTRL_ADC1_MSK (((1U << AUDIO_PADC_NCTRL_ADC1_LEN) - 1) << AUDIO_PADC_NCTRL_ADC1_POS) -#define AUDIO_PADC_NCTRL_ADC1_UMSK (~(((1U << AUDIO_PADC_NCTRL_ADC1_LEN) - 1) << AUDIO_PADC_NCTRL_ADC1_POS)) -#define AUDIO_PADC_ICTRL_ADC AUDIO_PADC_ICTRL_ADC -#define AUDIO_PADC_ICTRL_ADC_POS (15U) -#define AUDIO_PADC_ICTRL_ADC_LEN (2U) -#define AUDIO_PADC_ICTRL_ADC_MSK (((1U << AUDIO_PADC_ICTRL_ADC_LEN) - 1) << AUDIO_PADC_ICTRL_ADC_POS) -#define AUDIO_PADC_ICTRL_ADC_UMSK (~(((1U << AUDIO_PADC_ICTRL_ADC_LEN) - 1) << AUDIO_PADC_ICTRL_ADC_POS)) -#define AUDIO_PADC_RESERVED AUDIO_PADC_RESERVED -#define AUDIO_PADC_RESERVED_POS (17U) -#define AUDIO_PADC_RESERVED_LEN (4U) -#define AUDIO_PADC_RESERVED_MSK (((1U << AUDIO_PADC_RESERVED_LEN) - 1) << AUDIO_PADC_RESERVED_POS) -#define AUDIO_PADC_RESERVED_UMSK (~(((1U << AUDIO_PADC_RESERVED_LEN) - 1) << AUDIO_PADC_RESERVED_POS)) - -/* 0x808 : padc_ana_cmd */ -#define AUDIO_PADC_ANA_CMD_OFFSET (0x808) -#define AUDIO_PADC_SELF_TEST_EN AUDIO_PADC_SELF_TEST_EN -#define AUDIO_PADC_SELF_TEST_EN_POS (2U) -#define AUDIO_PADC_SELF_TEST_EN_LEN (1U) -#define AUDIO_PADC_SELF_TEST_EN_MSK (((1U << AUDIO_PADC_SELF_TEST_EN_LEN) - 1) << AUDIO_PADC_SELF_TEST_EN_POS) -#define AUDIO_PADC_SELF_TEST_EN_UMSK (~(((1U << AUDIO_PADC_SELF_TEST_EN_LEN) - 1) << AUDIO_PADC_SELF_TEST_EN_POS)) -#define AUDIO_PADC_SDM_LP_EN AUDIO_PADC_SDM_LP_EN -#define AUDIO_PADC_SDM_LP_EN_POS (3U) -#define AUDIO_PADC_SDM_LP_EN_LEN (1U) -#define AUDIO_PADC_SDM_LP_EN_MSK (((1U << AUDIO_PADC_SDM_LP_EN_LEN) - 1) << AUDIO_PADC_SDM_LP_EN_POS) -#define AUDIO_PADC_SDM_LP_EN_UMSK (~(((1U << AUDIO_PADC_SDM_LP_EN_LEN) - 1) << AUDIO_PADC_SDM_LP_EN_POS)) -#define AUDIO_PADC_PGA_LP_EN AUDIO_PADC_PGA_LP_EN -#define AUDIO_PADC_PGA_LP_EN_POS (4U) -#define AUDIO_PADC_PGA_LP_EN_LEN (1U) -#define AUDIO_PADC_PGA_LP_EN_MSK (((1U << AUDIO_PADC_PGA_LP_EN_LEN) - 1) << AUDIO_PADC_PGA_LP_EN_POS) -#define AUDIO_PADC_PGA_LP_EN_UMSK (~(((1U << AUDIO_PADC_PGA_LP_EN_LEN) - 1) << AUDIO_PADC_PGA_LP_EN_POS)) -#define AUDIO_PADC_DIAG_GSW AUDIO_PADC_DIAG_GSW -#define AUDIO_PADC_DIAG_GSW_POS (5U) -#define AUDIO_PADC_DIAG_GSW_LEN (2U) -#define AUDIO_PADC_DIAG_GSW_MSK (((1U << AUDIO_PADC_DIAG_GSW_LEN) - 1) << AUDIO_PADC_DIAG_GSW_POS) -#define AUDIO_PADC_DIAG_GSW_UMSK (~(((1U << AUDIO_PADC_DIAG_GSW_LEN) - 1) << AUDIO_PADC_DIAG_GSW_POS)) -#define AUDIO_PADC_DIAG_PSW AUDIO_PADC_DIAG_PSW -#define AUDIO_PADC_DIAG_PSW_POS (7U) -#define AUDIO_PADC_DIAG_PSW_LEN (2U) -#define AUDIO_PADC_DIAG_PSW_MSK (((1U << AUDIO_PADC_DIAG_PSW_LEN) - 1) << AUDIO_PADC_DIAG_PSW_POS) -#define AUDIO_PADC_DIAG_PSW_UMSK (~(((1U << AUDIO_PADC_DIAG_PSW_LEN) - 1) << AUDIO_PADC_DIAG_PSW_POS)) -#define AUDIO_PADC_ICTRL_DIAG AUDIO_PADC_ICTRL_DIAG -#define AUDIO_PADC_ICTRL_DIAG_POS (9U) -#define AUDIO_PADC_ICTRL_DIAG_LEN (2U) -#define AUDIO_PADC_ICTRL_DIAG_MSK (((1U << AUDIO_PADC_ICTRL_DIAG_LEN) - 1) << AUDIO_PADC_ICTRL_DIAG_POS) -#define AUDIO_PADC_ICTRL_DIAG_UMSK (~(((1U << AUDIO_PADC_ICTRL_DIAG_LEN) - 1) << AUDIO_PADC_ICTRL_DIAG_POS)) -#define AUDIO_PADC_PGA_GAIN AUDIO_PADC_PGA_GAIN -#define AUDIO_PADC_PGA_GAIN_POS (11U) -#define AUDIO_PADC_PGA_GAIN_LEN (3U) -#define AUDIO_PADC_PGA_GAIN_MSK (((1U << AUDIO_PADC_PGA_GAIN_LEN) - 1) << AUDIO_PADC_PGA_GAIN_POS) -#define AUDIO_PADC_PGA_GAIN_UMSK (~(((1U << AUDIO_PADC_PGA_GAIN_LEN) - 1) << AUDIO_PADC_PGA_GAIN_POS)) -#define AUDIO_PADC_INV_SIG AUDIO_PADC_INV_SIG -#define AUDIO_PADC_INV_SIG_POS (14U) -#define AUDIO_PADC_INV_SIG_LEN (1U) -#define AUDIO_PADC_INV_SIG_MSK (((1U << AUDIO_PADC_INV_SIG_LEN) - 1) << AUDIO_PADC_INV_SIG_POS) -#define AUDIO_PADC_INV_SIG_UMSK (~(((1U << AUDIO_PADC_INV_SIG_LEN) - 1) << AUDIO_PADC_INV_SIG_POS)) -#define AUDIO_PADC_SINGLE_MODE AUDIO_PADC_SINGLE_MODE -#define AUDIO_PADC_SINGLE_MODE_POS (15U) -#define AUDIO_PADC_SINGLE_MODE_LEN (2U) -#define AUDIO_PADC_SINGLE_MODE_MSK (((1U << AUDIO_PADC_SINGLE_MODE_LEN) - 1) << AUDIO_PADC_SINGLE_MODE_POS) -#define AUDIO_PADC_SINGLE_MODE_UMSK (~(((1U << AUDIO_PADC_SINGLE_MODE_LEN) - 1) << AUDIO_PADC_SINGLE_MODE_POS)) -#define AUDIO_PADC_SINGLE_CFG AUDIO_PADC_SINGLE_CFG -#define AUDIO_PADC_SINGLE_CFG_POS (17U) -#define AUDIO_PADC_SINGLE_CFG_LEN (4U) -#define AUDIO_PADC_SINGLE_CFG_MSK (((1U << AUDIO_PADC_SINGLE_CFG_LEN) - 1) << AUDIO_PADC_SINGLE_CFG_POS) -#define AUDIO_PADC_SINGLE_CFG_UMSK (~(((1U << AUDIO_PADC_SINGLE_CFG_LEN) - 1) << AUDIO_PADC_SINGLE_CFG_POS)) -#define AUDIO_PADC_CHANNEL_SEL AUDIO_PADC_CHANNEL_SEL -#define AUDIO_PADC_CHANNEL_SEL_POS (21U) -#define AUDIO_PADC_CHANNEL_SEL_LEN (2U) -#define AUDIO_PADC_CHANNEL_SEL_MSK (((1U << AUDIO_PADC_CHANNEL_SEL_LEN) - 1) << AUDIO_PADC_CHANNEL_SEL_POS) -#define AUDIO_PADC_CHANNEL_SEL_UMSK (~(((1U << AUDIO_PADC_CHANNEL_SEL_LEN) - 1) << AUDIO_PADC_CHANNEL_SEL_POS)) -#define AUDIO_PADC_CHANNEL_EN AUDIO_PADC_CHANNEL_EN -#define AUDIO_PADC_CHANNEL_EN_POS (23U) -#define AUDIO_PADC_CHANNEL_EN_LEN (1U) -#define AUDIO_PADC_CHANNEL_EN_MSK (((1U << AUDIO_PADC_CHANNEL_EN_LEN) - 1) << AUDIO_PADC_CHANNEL_EN_POS) -#define AUDIO_PADC_CHANNEL_EN_UMSK (~(((1U << AUDIO_PADC_CHANNEL_EN_LEN) - 1) << AUDIO_PADC_CHANNEL_EN_POS)) -#define AUDIO_PADC_CONV_DELAY AUDIO_PADC_CONV_DELAY -#define AUDIO_PADC_CONV_DELAY_POS (24U) -#define AUDIO_PADC_CONV_DELAY_LEN (4U) -#define AUDIO_PADC_CONV_DELAY_MSK (((1U << AUDIO_PADC_CONV_DELAY_LEN) - 1) << AUDIO_PADC_CONV_DELAY_POS) -#define AUDIO_PADC_CONV_DELAY_UMSK (~(((1U << AUDIO_PADC_CONV_DELAY_LEN) - 1) << AUDIO_PADC_CONV_DELAY_POS)) -#define AUDIO_PADC_CONV AUDIO_PADC_CONV -#define AUDIO_PADC_CONV_POS (28U) -#define AUDIO_PADC_CONV_LEN (1U) -#define AUDIO_PADC_CONV_MSK (((1U << AUDIO_PADC_CONV_LEN) - 1) << AUDIO_PADC_CONV_POS) -#define AUDIO_PADC_CONV_UMSK (~(((1U << AUDIO_PADC_CONV_LEN) - 1) << AUDIO_PADC_CONV_POS)) -#define AUDIO_PADC_EN_CALDAC AUDIO_PADC_EN_CALDAC -#define AUDIO_PADC_EN_CALDAC_POS (29U) -#define AUDIO_PADC_EN_CALDAC_LEN (1U) -#define AUDIO_PADC_EN_CALDAC_MSK (((1U << AUDIO_PADC_EN_CALDAC_LEN) - 1) << AUDIO_PADC_EN_CALDAC_POS) -#define AUDIO_PADC_EN_CALDAC_UMSK (~(((1U << AUDIO_PADC_EN_CALDAC_LEN) - 1) << AUDIO_PADC_EN_CALDAC_POS)) -#define AUDIO_PADC_SDM_PU AUDIO_PADC_SDM_PU -#define AUDIO_PADC_SDM_PU_POS (30U) -#define AUDIO_PADC_SDM_PU_LEN (1U) -#define AUDIO_PADC_SDM_PU_MSK (((1U << AUDIO_PADC_SDM_PU_LEN) - 1) << AUDIO_PADC_SDM_PU_POS) -#define AUDIO_PADC_SDM_PU_UMSK (~(((1U << AUDIO_PADC_SDM_PU_LEN) - 1) << AUDIO_PADC_SDM_PU_POS)) -#define AUDIO_PADC_PGA_PU AUDIO_PADC_PGA_PU -#define AUDIO_PADC_PGA_PU_POS (31U) -#define AUDIO_PADC_PGA_PU_LEN (1U) -#define AUDIO_PADC_PGA_PU_MSK (((1U << AUDIO_PADC_PGA_PU_LEN) - 1) << AUDIO_PADC_PGA_PU_POS) -#define AUDIO_PADC_PGA_PU_UMSK (~(((1U << AUDIO_PADC_PGA_PU_LEN) - 1) << AUDIO_PADC_PGA_PU_POS)) - -/* 0x80C : padc_out_cfg */ -#define AUDIO_PADC_OUT_CFG_OFFSET (0x80C) -#define AUDIO_PADC_VALID_4S_VAL AUDIO_PADC_VALID_4S_VAL -#define AUDIO_PADC_VALID_4S_VAL_POS (21U) -#define AUDIO_PADC_VALID_4S_VAL_LEN (1U) -#define AUDIO_PADC_VALID_4S_VAL_MSK (((1U << AUDIO_PADC_VALID_4S_VAL_LEN) - 1) << AUDIO_PADC_VALID_4S_VAL_POS) -#define AUDIO_PADC_VALID_4S_VAL_UMSK (~(((1U << AUDIO_PADC_VALID_4S_VAL_LEN) - 1) << AUDIO_PADC_VALID_4S_VAL_POS)) -#define AUDIO_PADC_VALID_4S_EN AUDIO_PADC_VALID_4S_EN -#define AUDIO_PADC_VALID_4S_EN_POS (22U) -#define AUDIO_PADC_VALID_4S_EN_LEN (1U) -#define AUDIO_PADC_VALID_4S_EN_MSK (((1U << AUDIO_PADC_VALID_4S_EN_LEN) - 1) << AUDIO_PADC_VALID_4S_EN_POS) -#define AUDIO_PADC_VALID_4S_EN_UMSK (~(((1U << AUDIO_PADC_VALID_4S_EN_LEN) - 1) << AUDIO_PADC_VALID_4S_EN_POS)) -#define AUDIO_PADC_GLOBAL_CHOP_EN AUDIO_PADC_GLOBAL_CHOP_EN -#define AUDIO_PADC_GLOBAL_CHOP_EN_POS (23U) -#define AUDIO_PADC_GLOBAL_CHOP_EN_LEN (1U) -#define AUDIO_PADC_GLOBAL_CHOP_EN_MSK (((1U << AUDIO_PADC_GLOBAL_CHOP_EN_LEN) - 1) << AUDIO_PADC_GLOBAL_CHOP_EN_POS) -#define AUDIO_PADC_GLOBAL_CHOP_EN_UMSK (~(((1U << AUDIO_PADC_GLOBAL_CHOP_EN_LEN) - 1) << AUDIO_PADC_GLOBAL_CHOP_EN_POS)) -#define AUDIO_PADC_FILTER_TYPE AUDIO_PADC_FILTER_TYPE -#define AUDIO_PADC_FILTER_TYPE_POS (24U) -#define AUDIO_PADC_FILTER_TYPE_LEN (1U) -#define AUDIO_PADC_FILTER_TYPE_MSK (((1U << AUDIO_PADC_FILTER_TYPE_LEN) - 1) << AUDIO_PADC_FILTER_TYPE_POS) -#define AUDIO_PADC_FILTER_TYPE_UMSK (~(((1U << AUDIO_PADC_FILTER_TYPE_LEN) - 1) << AUDIO_PADC_FILTER_TYPE_POS)) -#define AUDIO_PADC_ODR AUDIO_PADC_ODR -#define AUDIO_PADC_ODR_POS (25U) -#define AUDIO_PADC_ODR_LEN (4U) -#define AUDIO_PADC_ODR_MSK (((1U << AUDIO_PADC_ODR_LEN) - 1) << AUDIO_PADC_ODR_POS) -#define AUDIO_PADC_ODR_UMSK (~(((1U << AUDIO_PADC_ODR_LEN) - 1) << AUDIO_PADC_ODR_POS)) - -/* 0x810 : padc_calib_cmd */ -#define AUDIO_PADC_CALIB_CMD_OFFSET (0x810) -#define AUDIO_PADC_CALIB_AVERAGE AUDIO_PADC_CALIB_AVERAGE -#define AUDIO_PADC_CALIB_AVERAGE_POS (16U) -#define AUDIO_PADC_CALIB_AVERAGE_LEN (3U) -#define AUDIO_PADC_CALIB_AVERAGE_MSK (((1U << AUDIO_PADC_CALIB_AVERAGE_LEN) - 1) << AUDIO_PADC_CALIB_AVERAGE_POS) -#define AUDIO_PADC_CALIB_AVERAGE_UMSK (~(((1U << AUDIO_PADC_CALIB_AVERAGE_LEN) - 1) << AUDIO_PADC_CALIB_AVERAGE_POS)) -#define AUDIO_PADC_CALIB_DISCARD AUDIO_PADC_CALIB_DISCARD -#define AUDIO_PADC_CALIB_DISCARD_POS (19U) -#define AUDIO_PADC_CALIB_DISCARD_LEN (3U) -#define AUDIO_PADC_CALIB_DISCARD_MSK (((1U << AUDIO_PADC_CALIB_DISCARD_LEN) - 1) << AUDIO_PADC_CALIB_DISCARD_POS) -#define AUDIO_PADC_CALIB_DISCARD_UMSK (~(((1U << AUDIO_PADC_CALIB_DISCARD_LEN) - 1) << AUDIO_PADC_CALIB_DISCARD_POS)) -#define AUDIO_PADC_CALIB_RUN AUDIO_PADC_CALIB_RUN -#define AUDIO_PADC_CALIB_RUN_POS (22U) -#define AUDIO_PADC_CALIB_RUN_LEN (1U) -#define AUDIO_PADC_CALIB_RUN_MSK (((1U << AUDIO_PADC_CALIB_RUN_LEN) - 1) << AUDIO_PADC_CALIB_RUN_POS) -#define AUDIO_PADC_CALIB_RUN_UMSK (~(((1U << AUDIO_PADC_CALIB_RUN_LEN) - 1) << AUDIO_PADC_CALIB_RUN_POS)) -#define AUDIO_PADC_CALIB_LVL AUDIO_PADC_CALIB_LVL -#define AUDIO_PADC_CALIB_LVL_POS (23U) -#define AUDIO_PADC_CALIB_LVL_LEN (2U) -#define AUDIO_PADC_CALIB_LVL_MSK (((1U << AUDIO_PADC_CALIB_LVL_LEN) - 1) << AUDIO_PADC_CALIB_LVL_POS) -#define AUDIO_PADC_CALIB_LVL_UMSK (~(((1U << AUDIO_PADC_CALIB_LVL_LEN) - 1) << AUDIO_PADC_CALIB_LVL_POS)) -#define AUDIO_PADC_CALIB_GAIN AUDIO_PADC_CALIB_GAIN -#define AUDIO_PADC_CALIB_GAIN_POS (25U) -#define AUDIO_PADC_CALIB_GAIN_LEN (3U) -#define AUDIO_PADC_CALIB_GAIN_MSK (((1U << AUDIO_PADC_CALIB_GAIN_LEN) - 1) << AUDIO_PADC_CALIB_GAIN_POS) -#define AUDIO_PADC_CALIB_GAIN_UMSK (~(((1U << AUDIO_PADC_CALIB_GAIN_LEN) - 1) << AUDIO_PADC_CALIB_GAIN_POS)) -#define AUDIO_PADC_CALIB_MODE AUDIO_PADC_CALIB_MODE -#define AUDIO_PADC_CALIB_MODE_POS (28U) -#define AUDIO_PADC_CALIB_MODE_LEN (2U) -#define AUDIO_PADC_CALIB_MODE_MSK (((1U << AUDIO_PADC_CALIB_MODE_LEN) - 1) << AUDIO_PADC_CALIB_MODE_POS) -#define AUDIO_PADC_CALIB_MODE_UMSK (~(((1U << AUDIO_PADC_CALIB_MODE_LEN) - 1) << AUDIO_PADC_CALIB_MODE_POS)) -#define AUDIO_PADC_CALIB_START AUDIO_PADC_CALIB_START -#define AUDIO_PADC_CALIB_START_POS (30U) -#define AUDIO_PADC_CALIB_START_LEN (1U) -#define AUDIO_PADC_CALIB_START_MSK (((1U << AUDIO_PADC_CALIB_START_LEN) - 1) << AUDIO_PADC_CALIB_START_POS) -#define AUDIO_PADC_CALIB_START_UMSK (~(((1U << AUDIO_PADC_CALIB_START_LEN) - 1) << AUDIO_PADC_CALIB_START_POS)) -#define AUDIO_PADC_CALIB_METHOD AUDIO_PADC_CALIB_METHOD -#define AUDIO_PADC_CALIB_METHOD_POS (31U) -#define AUDIO_PADC_CALIB_METHOD_LEN (1U) -#define AUDIO_PADC_CALIB_METHOD_MSK (((1U << AUDIO_PADC_CALIB_METHOD_LEN) - 1) << AUDIO_PADC_CALIB_METHOD_POS) -#define AUDIO_PADC_CALIB_METHOD_UMSK (~(((1U << AUDIO_PADC_CALIB_METHOD_LEN) - 1) << AUDIO_PADC_CALIB_METHOD_POS)) - -/* 0x814 : padc_status */ -#define AUDIO_PADC_STATUS_OFFSET (0x814) -#define AUDIO_PADC_SOFT_RST AUDIO_PADC_SOFT_RST -#define AUDIO_PADC_SOFT_RST_POS (2U) -#define AUDIO_PADC_SOFT_RST_LEN (1U) -#define AUDIO_PADC_SOFT_RST_MSK (((1U << AUDIO_PADC_SOFT_RST_LEN) - 1) << AUDIO_PADC_SOFT_RST_POS) -#define AUDIO_PADC_SOFT_RST_UMSK (~(((1U << AUDIO_PADC_SOFT_RST_LEN) - 1) << AUDIO_PADC_SOFT_RST_POS)) -#define AUDIO_PADC_FILTER_RDY AUDIO_PADC_FILTER_RDY -#define AUDIO_PADC_FILTER_RDY_POS (3U) -#define AUDIO_PADC_FILTER_RDY_LEN (1U) -#define AUDIO_PADC_FILTER_RDY_MSK (((1U << AUDIO_PADC_FILTER_RDY_LEN) - 1) << AUDIO_PADC_FILTER_RDY_POS) -#define AUDIO_PADC_FILTER_RDY_UMSK (~(((1U << AUDIO_PADC_FILTER_RDY_LEN) - 1) << AUDIO_PADC_FILTER_RDY_POS)) -#define AUDIO_PADC_CALIB_ST AUDIO_PADC_CALIB_ST -#define AUDIO_PADC_CALIB_ST_POS (24U) -#define AUDIO_PADC_CALIB_ST_LEN (3U) -#define AUDIO_PADC_CALIB_ST_MSK (((1U << AUDIO_PADC_CALIB_ST_LEN) - 1) << AUDIO_PADC_CALIB_ST_POS) -#define AUDIO_PADC_CALIB_ST_UMSK (~(((1U << AUDIO_PADC_CALIB_ST_LEN) - 1) << AUDIO_PADC_CALIB_ST_POS)) -#define AUDIO_PADC_CALIB_BUSY AUDIO_PADC_CALIB_BUSY -#define AUDIO_PADC_CALIB_BUSY_POS (27U) -#define AUDIO_PADC_CALIB_BUSY_LEN (1U) -#define AUDIO_PADC_CALIB_BUSY_MSK (((1U << AUDIO_PADC_CALIB_BUSY_LEN) - 1) << AUDIO_PADC_CALIB_BUSY_POS) -#define AUDIO_PADC_CALIB_BUSY_UMSK (~(((1U << AUDIO_PADC_CALIB_BUSY_LEN) - 1) << AUDIO_PADC_CALIB_BUSY_POS)) -#define AUDIO_PADC_INT AUDIO_PADC_INT -#define AUDIO_PADC_INT_POS (28U) -#define AUDIO_PADC_INT_LEN (1U) -#define AUDIO_PADC_INT_MSK (((1U << AUDIO_PADC_INT_LEN) - 1) << AUDIO_PADC_INT_POS) -#define AUDIO_PADC_INT_UMSK (~(((1U << AUDIO_PADC_INT_LEN) - 1) << AUDIO_PADC_INT_POS)) -#define AUDIO_PADC_INT_CLR AUDIO_PADC_INT_CLR -#define AUDIO_PADC_INT_CLR_POS (29U) -#define AUDIO_PADC_INT_CLR_LEN (1U) -#define AUDIO_PADC_INT_CLR_MSK (((1U << AUDIO_PADC_INT_CLR_LEN) - 1) << AUDIO_PADC_INT_CLR_POS) -#define AUDIO_PADC_INT_CLR_UMSK (~(((1U << AUDIO_PADC_INT_CLR_LEN) - 1) << AUDIO_PADC_INT_CLR_POS)) -#define AUDIO_PADC_INT_SET AUDIO_PADC_INT_SET -#define AUDIO_PADC_INT_SET_POS (30U) -#define AUDIO_PADC_INT_SET_LEN (1U) -#define AUDIO_PADC_INT_SET_MSK (((1U << AUDIO_PADC_INT_SET_LEN) - 1) << AUDIO_PADC_INT_SET_POS) -#define AUDIO_PADC_INT_SET_UMSK (~(((1U << AUDIO_PADC_INT_SET_LEN) - 1) << AUDIO_PADC_INT_SET_POS)) - -/* 0x818 : padc_data */ -#define AUDIO_PADC_DATA_OFFSET (0x818) -#define AUDIO_PADC_RAW_DATA AUDIO_PADC_RAW_DATA -#define AUDIO_PADC_RAW_DATA_POS (0U) -#define AUDIO_PADC_RAW_DATA_LEN (24U) -#define AUDIO_PADC_RAW_DATA_MSK (((1U << AUDIO_PADC_RAW_DATA_LEN) - 1) << AUDIO_PADC_RAW_DATA_POS) -#define AUDIO_PADC_RAW_DATA_UMSK (~(((1U << AUDIO_PADC_RAW_DATA_LEN) - 1) << AUDIO_PADC_RAW_DATA_POS)) - -/* 0x81C : padc_calib_cfg1 */ -#define AUDIO_PADC_CALIB_CFG1_OFFSET (0x81C) -#define AUDIO_PADC_OEC AUDIO_PADC_OEC -#define AUDIO_PADC_OEC_POS (0U) -#define AUDIO_PADC_OEC_LEN (24U) -#define AUDIO_PADC_OEC_MSK (((1U << AUDIO_PADC_OEC_LEN) - 1) << AUDIO_PADC_OEC_POS) -#define AUDIO_PADC_OEC_UMSK (~(((1U << AUDIO_PADC_OEC_LEN) - 1) << AUDIO_PADC_OEC_POS)) - -/* 0x820 : padc_calib_cfg2 */ -#define AUDIO_PADC_CALIB_CFG2_OFFSET (0x820) -#define AUDIO_PADC_GEC AUDIO_PADC_GEC -#define AUDIO_PADC_GEC_POS (0U) -#define AUDIO_PADC_GEC_LEN (24U) -#define AUDIO_PADC_GEC_MSK (((1U << AUDIO_PADC_GEC_LEN) - 1) << AUDIO_PADC_GEC_POS) -#define AUDIO_PADC_GEC_UMSK (~(((1U << AUDIO_PADC_GEC_LEN) - 1) << AUDIO_PADC_GEC_POS)) - -/* 0x824 : padc_calib_cfg3 */ -#define AUDIO_PADC_CALIB_CFG3_OFFSET (0x824) - -/* 0x828 : padc_calib_cfg4 */ -#define AUDIO_PADC_CALIB_CFG4_OFFSET (0x828) - -/* 0x82C : padc_calib_cfg5 */ -#define AUDIO_PADC_CALIB_CFG5_OFFSET (0x82C) -#define AUDIO_PADC_GAINCAL_REF AUDIO_PADC_GAINCAL_REF -#define AUDIO_PADC_GAINCAL_REF_POS (0U) -#define AUDIO_PADC_GAINCAL_REF_LEN (24U) -#define AUDIO_PADC_GAINCAL_REF_MSK (((1U << AUDIO_PADC_GAINCAL_REF_LEN) - 1) << AUDIO_PADC_GAINCAL_REF_POS) -#define AUDIO_PADC_GAINCAL_REF_UMSK (~(((1U << AUDIO_PADC_GAINCAL_REF_LEN) - 1) << AUDIO_PADC_GAINCAL_REF_POS)) - -/* 0x830 : padc_calib_cfg6 */ -#define AUDIO_PADC_CALIB_CFG6_OFFSET (0x830) - -/* 0x834 : padc_calib_cfg7 */ -#define AUDIO_PADC_CALIB_CFG7_OFFSET (0x834) - -/* 0x838 : padc_oec_w1p */ -#define AUDIO_PADC_OEC_W1P_OFFSET (0x838) -#define AUDIO_PADC_WR_OEC AUDIO_PADC_WR_OEC -#define AUDIO_PADC_WR_OEC_POS (0U) -#define AUDIO_PADC_WR_OEC_LEN (24U) -#define AUDIO_PADC_WR_OEC_MSK (((1U << AUDIO_PADC_WR_OEC_LEN) - 1) << AUDIO_PADC_WR_OEC_POS) -#define AUDIO_PADC_WR_OEC_UMSK (~(((1U << AUDIO_PADC_WR_OEC_LEN) - 1) << AUDIO_PADC_WR_OEC_POS)) -#define AUDIO_PADC_OEC_W1P_G0 AUDIO_PADC_OEC_W1P_G0 -#define AUDIO_PADC_OEC_W1P_G0_POS (24U) -#define AUDIO_PADC_OEC_W1P_G0_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G0_MSK (((1U << AUDIO_PADC_OEC_W1P_G0_LEN) - 1) << AUDIO_PADC_OEC_W1P_G0_POS) -#define AUDIO_PADC_OEC_W1P_G0_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G0_LEN) - 1) << AUDIO_PADC_OEC_W1P_G0_POS)) -#define AUDIO_PADC_OEC_W1P_G1 AUDIO_PADC_OEC_W1P_G1 -#define AUDIO_PADC_OEC_W1P_G1_POS (25U) -#define AUDIO_PADC_OEC_W1P_G1_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G1_MSK (((1U << AUDIO_PADC_OEC_W1P_G1_LEN) - 1) << AUDIO_PADC_OEC_W1P_G1_POS) -#define AUDIO_PADC_OEC_W1P_G1_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G1_LEN) - 1) << AUDIO_PADC_OEC_W1P_G1_POS)) -#define AUDIO_PADC_OEC_W1P_G2 AUDIO_PADC_OEC_W1P_G2 -#define AUDIO_PADC_OEC_W1P_G2_POS (26U) -#define AUDIO_PADC_OEC_W1P_G2_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G2_MSK (((1U << AUDIO_PADC_OEC_W1P_G2_LEN) - 1) << AUDIO_PADC_OEC_W1P_G2_POS) -#define AUDIO_PADC_OEC_W1P_G2_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G2_LEN) - 1) << AUDIO_PADC_OEC_W1P_G2_POS)) -#define AUDIO_PADC_OEC_W1P_G3 AUDIO_PADC_OEC_W1P_G3 -#define AUDIO_PADC_OEC_W1P_G3_POS (27U) -#define AUDIO_PADC_OEC_W1P_G3_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G3_MSK (((1U << AUDIO_PADC_OEC_W1P_G3_LEN) - 1) << AUDIO_PADC_OEC_W1P_G3_POS) -#define AUDIO_PADC_OEC_W1P_G3_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G3_LEN) - 1) << AUDIO_PADC_OEC_W1P_G3_POS)) -#define AUDIO_PADC_OEC_W1P_G4 AUDIO_PADC_OEC_W1P_G4 -#define AUDIO_PADC_OEC_W1P_G4_POS (28U) -#define AUDIO_PADC_OEC_W1P_G4_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G4_MSK (((1U << AUDIO_PADC_OEC_W1P_G4_LEN) - 1) << AUDIO_PADC_OEC_W1P_G4_POS) -#define AUDIO_PADC_OEC_W1P_G4_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G4_LEN) - 1) << AUDIO_PADC_OEC_W1P_G4_POS)) -#define AUDIO_PADC_OEC_W1P_G5 AUDIO_PADC_OEC_W1P_G5 -#define AUDIO_PADC_OEC_W1P_G5_POS (29U) -#define AUDIO_PADC_OEC_W1P_G5_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G5_MSK (((1U << AUDIO_PADC_OEC_W1P_G5_LEN) - 1) << AUDIO_PADC_OEC_W1P_G5_POS) -#define AUDIO_PADC_OEC_W1P_G5_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G5_LEN) - 1) << AUDIO_PADC_OEC_W1P_G5_POS)) -#define AUDIO_PADC_OEC_W1P_G6 AUDIO_PADC_OEC_W1P_G6 -#define AUDIO_PADC_OEC_W1P_G6_POS (30U) -#define AUDIO_PADC_OEC_W1P_G6_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G6_MSK (((1U << AUDIO_PADC_OEC_W1P_G6_LEN) - 1) << AUDIO_PADC_OEC_W1P_G6_POS) -#define AUDIO_PADC_OEC_W1P_G6_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G6_LEN) - 1) << AUDIO_PADC_OEC_W1P_G6_POS)) -#define AUDIO_PADC_OEC_W1P_G7 AUDIO_PADC_OEC_W1P_G7 -#define AUDIO_PADC_OEC_W1P_G7_POS (31U) -#define AUDIO_PADC_OEC_W1P_G7_LEN (1U) -#define AUDIO_PADC_OEC_W1P_G7_MSK (((1U << AUDIO_PADC_OEC_W1P_G7_LEN) - 1) << AUDIO_PADC_OEC_W1P_G7_POS) -#define AUDIO_PADC_OEC_W1P_G7_UMSK (~(((1U << AUDIO_PADC_OEC_W1P_G7_LEN) - 1) << AUDIO_PADC_OEC_W1P_G7_POS)) - -/* 0x83C : padc_gec_w1p */ -#define AUDIO_PADC_GEC_W1P_OFFSET (0x83C) -#define AUDIO_PADC_WR_GEC AUDIO_PADC_WR_GEC -#define AUDIO_PADC_WR_GEC_POS (0U) -#define AUDIO_PADC_WR_GEC_LEN (24U) -#define AUDIO_PADC_WR_GEC_MSK (((1U << AUDIO_PADC_WR_GEC_LEN) - 1) << AUDIO_PADC_WR_GEC_POS) -#define AUDIO_PADC_WR_GEC_UMSK (~(((1U << AUDIO_PADC_WR_GEC_LEN) - 1) << AUDIO_PADC_WR_GEC_POS)) -#define AUDIO_PADC_GEC_W1P_G0 AUDIO_PADC_GEC_W1P_G0 -#define AUDIO_PADC_GEC_W1P_G0_POS (24U) -#define AUDIO_PADC_GEC_W1P_G0_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G0_MSK (((1U << AUDIO_PADC_GEC_W1P_G0_LEN) - 1) << AUDIO_PADC_GEC_W1P_G0_POS) -#define AUDIO_PADC_GEC_W1P_G0_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G0_LEN) - 1) << AUDIO_PADC_GEC_W1P_G0_POS)) -#define AUDIO_PADC_GEC_W1P_G1 AUDIO_PADC_GEC_W1P_G1 -#define AUDIO_PADC_GEC_W1P_G1_POS (25U) -#define AUDIO_PADC_GEC_W1P_G1_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G1_MSK (((1U << AUDIO_PADC_GEC_W1P_G1_LEN) - 1) << AUDIO_PADC_GEC_W1P_G1_POS) -#define AUDIO_PADC_GEC_W1P_G1_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G1_LEN) - 1) << AUDIO_PADC_GEC_W1P_G1_POS)) -#define AUDIO_PADC_GEC_W1P_G2 AUDIO_PADC_GEC_W1P_G2 -#define AUDIO_PADC_GEC_W1P_G2_POS (26U) -#define AUDIO_PADC_GEC_W1P_G2_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G2_MSK (((1U << AUDIO_PADC_GEC_W1P_G2_LEN) - 1) << AUDIO_PADC_GEC_W1P_G2_POS) -#define AUDIO_PADC_GEC_W1P_G2_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G2_LEN) - 1) << AUDIO_PADC_GEC_W1P_G2_POS)) -#define AUDIO_PADC_GEC_W1P_G3 AUDIO_PADC_GEC_W1P_G3 -#define AUDIO_PADC_GEC_W1P_G3_POS (27U) -#define AUDIO_PADC_GEC_W1P_G3_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G3_MSK (((1U << AUDIO_PADC_GEC_W1P_G3_LEN) - 1) << AUDIO_PADC_GEC_W1P_G3_POS) -#define AUDIO_PADC_GEC_W1P_G3_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G3_LEN) - 1) << AUDIO_PADC_GEC_W1P_G3_POS)) -#define AUDIO_PADC_GEC_W1P_G4 AUDIO_PADC_GEC_W1P_G4 -#define AUDIO_PADC_GEC_W1P_G4_POS (28U) -#define AUDIO_PADC_GEC_W1P_G4_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G4_MSK (((1U << AUDIO_PADC_GEC_W1P_G4_LEN) - 1) << AUDIO_PADC_GEC_W1P_G4_POS) -#define AUDIO_PADC_GEC_W1P_G4_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G4_LEN) - 1) << AUDIO_PADC_GEC_W1P_G4_POS)) -#define AUDIO_PADC_GEC_W1P_G5 AUDIO_PADC_GEC_W1P_G5 -#define AUDIO_PADC_GEC_W1P_G5_POS (29U) -#define AUDIO_PADC_GEC_W1P_G5_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G5_MSK (((1U << AUDIO_PADC_GEC_W1P_G5_LEN) - 1) << AUDIO_PADC_GEC_W1P_G5_POS) -#define AUDIO_PADC_GEC_W1P_G5_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G5_LEN) - 1) << AUDIO_PADC_GEC_W1P_G5_POS)) -#define AUDIO_PADC_GEC_W1P_G6 AUDIO_PADC_GEC_W1P_G6 -#define AUDIO_PADC_GEC_W1P_G6_POS (30U) -#define AUDIO_PADC_GEC_W1P_G6_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G6_MSK (((1U << AUDIO_PADC_GEC_W1P_G6_LEN) - 1) << AUDIO_PADC_GEC_W1P_G6_POS) -#define AUDIO_PADC_GEC_W1P_G6_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G6_LEN) - 1) << AUDIO_PADC_GEC_W1P_G6_POS)) -#define AUDIO_PADC_GEC_W1P_G7 AUDIO_PADC_GEC_W1P_G7 -#define AUDIO_PADC_GEC_W1P_G7_POS (31U) -#define AUDIO_PADC_GEC_W1P_G7_LEN (1U) -#define AUDIO_PADC_GEC_W1P_G7_MSK (((1U << AUDIO_PADC_GEC_W1P_G7_LEN) - 1) << AUDIO_PADC_GEC_W1P_G7_POS) -#define AUDIO_PADC_GEC_W1P_G7_UMSK (~(((1U << AUDIO_PADC_GEC_W1P_G7_LEN) - 1) << AUDIO_PADC_GEC_W1P_G7_POS)) - -/* 0x840 : padc_oec_cfg0 */ -#define AUDIO_PADC_OEC_CFG0_OFFSET (0x840) -#define AUDIO_PADC_OEC_G0 AUDIO_PADC_OEC_G0 -#define AUDIO_PADC_OEC_G0_POS (0U) -#define AUDIO_PADC_OEC_G0_LEN (24U) -#define AUDIO_PADC_OEC_G0_MSK (((1U << AUDIO_PADC_OEC_G0_LEN) - 1) << AUDIO_PADC_OEC_G0_POS) -#define AUDIO_PADC_OEC_G0_UMSK (~(((1U << AUDIO_PADC_OEC_G0_LEN) - 1) << AUDIO_PADC_OEC_G0_POS)) - -/* 0x844 : padc_oec_cfg1 */ -#define AUDIO_PADC_OEC_CFG1_OFFSET (0x844) -#define AUDIO_PADC_OEC_G1 AUDIO_PADC_OEC_G1 -#define AUDIO_PADC_OEC_G1_POS (0U) -#define AUDIO_PADC_OEC_G1_LEN (24U) -#define AUDIO_PADC_OEC_G1_MSK (((1U << AUDIO_PADC_OEC_G1_LEN) - 1) << AUDIO_PADC_OEC_G1_POS) -#define AUDIO_PADC_OEC_G1_UMSK (~(((1U << AUDIO_PADC_OEC_G1_LEN) - 1) << AUDIO_PADC_OEC_G1_POS)) - -/* 0x848 : padc_oec_cfg2 */ -#define AUDIO_PADC_OEC_CFG2_OFFSET (0x848) -#define AUDIO_PADC_OEC_G2 AUDIO_PADC_OEC_G2 -#define AUDIO_PADC_OEC_G2_POS (0U) -#define AUDIO_PADC_OEC_G2_LEN (24U) -#define AUDIO_PADC_OEC_G2_MSK (((1U << AUDIO_PADC_OEC_G2_LEN) - 1) << AUDIO_PADC_OEC_G2_POS) -#define AUDIO_PADC_OEC_G2_UMSK (~(((1U << AUDIO_PADC_OEC_G2_LEN) - 1) << AUDIO_PADC_OEC_G2_POS)) - -/* 0x84C : padc_oec_cfg3 */ -#define AUDIO_PADC_OEC_CFG3_OFFSET (0x84C) -#define AUDIO_PADC_OEC_G3 AUDIO_PADC_OEC_G3 -#define AUDIO_PADC_OEC_G3_POS (0U) -#define AUDIO_PADC_OEC_G3_LEN (24U) -#define AUDIO_PADC_OEC_G3_MSK (((1U << AUDIO_PADC_OEC_G3_LEN) - 1) << AUDIO_PADC_OEC_G3_POS) -#define AUDIO_PADC_OEC_G3_UMSK (~(((1U << AUDIO_PADC_OEC_G3_LEN) - 1) << AUDIO_PADC_OEC_G3_POS)) - -/* 0x850 : padc_oec_cfg4 */ -#define AUDIO_PADC_OEC_CFG4_OFFSET (0x850) -#define AUDIO_PADC_OEC_G4 AUDIO_PADC_OEC_G4 -#define AUDIO_PADC_OEC_G4_POS (0U) -#define AUDIO_PADC_OEC_G4_LEN (24U) -#define AUDIO_PADC_OEC_G4_MSK (((1U << AUDIO_PADC_OEC_G4_LEN) - 1) << AUDIO_PADC_OEC_G4_POS) -#define AUDIO_PADC_OEC_G4_UMSK (~(((1U << AUDIO_PADC_OEC_G4_LEN) - 1) << AUDIO_PADC_OEC_G4_POS)) - -/* 0x854 : padc_oec_cfg5 */ -#define AUDIO_PADC_OEC_CFG5_OFFSET (0x854) -#define AUDIO_PADC_OEC_G5 AUDIO_PADC_OEC_G5 -#define AUDIO_PADC_OEC_G5_POS (0U) -#define AUDIO_PADC_OEC_G5_LEN (24U) -#define AUDIO_PADC_OEC_G5_MSK (((1U << AUDIO_PADC_OEC_G5_LEN) - 1) << AUDIO_PADC_OEC_G5_POS) -#define AUDIO_PADC_OEC_G5_UMSK (~(((1U << AUDIO_PADC_OEC_G5_LEN) - 1) << AUDIO_PADC_OEC_G5_POS)) - -/* 0x858 : padc_oec_cfg6 */ -#define AUDIO_PADC_OEC_CFG6_OFFSET (0x858) -#define AUDIO_PADC_OEC_G6 AUDIO_PADC_OEC_G6 -#define AUDIO_PADC_OEC_G6_POS (0U) -#define AUDIO_PADC_OEC_G6_LEN (24U) -#define AUDIO_PADC_OEC_G6_MSK (((1U << AUDIO_PADC_OEC_G6_LEN) - 1) << AUDIO_PADC_OEC_G6_POS) -#define AUDIO_PADC_OEC_G6_UMSK (~(((1U << AUDIO_PADC_OEC_G6_LEN) - 1) << AUDIO_PADC_OEC_G6_POS)) - -/* 0x85C : padc_oec_cfg7 */ -#define AUDIO_PADC_OEC_CFG7_OFFSET (0x85C) -#define AUDIO_PADC_OEC_G7 AUDIO_PADC_OEC_G7 -#define AUDIO_PADC_OEC_G7_POS (0U) -#define AUDIO_PADC_OEC_G7_LEN (24U) -#define AUDIO_PADC_OEC_G7_MSK (((1U << AUDIO_PADC_OEC_G7_LEN) - 1) << AUDIO_PADC_OEC_G7_POS) -#define AUDIO_PADC_OEC_G7_UMSK (~(((1U << AUDIO_PADC_OEC_G7_LEN) - 1) << AUDIO_PADC_OEC_G7_POS)) - -/* 0x860 : padc_gec_cfg0 */ -#define AUDIO_PADC_GEC_CFG0_OFFSET (0x860) -#define AUDIO_PADC_GEC_G0 AUDIO_PADC_GEC_G0 -#define AUDIO_PADC_GEC_G0_POS (0U) -#define AUDIO_PADC_GEC_G0_LEN (24U) -#define AUDIO_PADC_GEC_G0_MSK (((1U << AUDIO_PADC_GEC_G0_LEN) - 1) << AUDIO_PADC_GEC_G0_POS) -#define AUDIO_PADC_GEC_G0_UMSK (~(((1U << AUDIO_PADC_GEC_G0_LEN) - 1) << AUDIO_PADC_GEC_G0_POS)) - -/* 0x864 : padc_gec_cfg1 */ -#define AUDIO_PADC_GEC_CFG1_OFFSET (0x864) -#define AUDIO_PADC_GEC_G1 AUDIO_PADC_GEC_G1 -#define AUDIO_PADC_GEC_G1_POS (0U) -#define AUDIO_PADC_GEC_G1_LEN (24U) -#define AUDIO_PADC_GEC_G1_MSK (((1U << AUDIO_PADC_GEC_G1_LEN) - 1) << AUDIO_PADC_GEC_G1_POS) -#define AUDIO_PADC_GEC_G1_UMSK (~(((1U << AUDIO_PADC_GEC_G1_LEN) - 1) << AUDIO_PADC_GEC_G1_POS)) - -/* 0x868 : padc_gec_cfg2 */ -#define AUDIO_PADC_GEC_CFG2_OFFSET (0x868) -#define AUDIO_PADC_GEC_G2 AUDIO_PADC_GEC_G2 -#define AUDIO_PADC_GEC_G2_POS (0U) -#define AUDIO_PADC_GEC_G2_LEN (24U) -#define AUDIO_PADC_GEC_G2_MSK (((1U << AUDIO_PADC_GEC_G2_LEN) - 1) << AUDIO_PADC_GEC_G2_POS) -#define AUDIO_PADC_GEC_G2_UMSK (~(((1U << AUDIO_PADC_GEC_G2_LEN) - 1) << AUDIO_PADC_GEC_G2_POS)) - -/* 0x86C : padc_gec_cfg3 */ -#define AUDIO_PADC_GEC_CFG3_OFFSET (0x86C) -#define AUDIO_PADC_GEC_G3 AUDIO_PADC_GEC_G3 -#define AUDIO_PADC_GEC_G3_POS (0U) -#define AUDIO_PADC_GEC_G3_LEN (24U) -#define AUDIO_PADC_GEC_G3_MSK (((1U << AUDIO_PADC_GEC_G3_LEN) - 1) << AUDIO_PADC_GEC_G3_POS) -#define AUDIO_PADC_GEC_G3_UMSK (~(((1U << AUDIO_PADC_GEC_G3_LEN) - 1) << AUDIO_PADC_GEC_G3_POS)) - -/* 0x870 : padc_gec_cfg4 */ -#define AUDIO_PADC_GEC_CFG4_OFFSET (0x870) -#define AUDIO_PADC_GEC_G4 AUDIO_PADC_GEC_G4 -#define AUDIO_PADC_GEC_G4_POS (0U) -#define AUDIO_PADC_GEC_G4_LEN (24U) -#define AUDIO_PADC_GEC_G4_MSK (((1U << AUDIO_PADC_GEC_G4_LEN) - 1) << AUDIO_PADC_GEC_G4_POS) -#define AUDIO_PADC_GEC_G4_UMSK (~(((1U << AUDIO_PADC_GEC_G4_LEN) - 1) << AUDIO_PADC_GEC_G4_POS)) - -/* 0x874 : padc_gec_cfg5 */ -#define AUDIO_PADC_GEC_CFG5_OFFSET (0x874) -#define AUDIO_PADC_GEC_G5 AUDIO_PADC_GEC_G5 -#define AUDIO_PADC_GEC_G5_POS (0U) -#define AUDIO_PADC_GEC_G5_LEN (24U) -#define AUDIO_PADC_GEC_G5_MSK (((1U << AUDIO_PADC_GEC_G5_LEN) - 1) << AUDIO_PADC_GEC_G5_POS) -#define AUDIO_PADC_GEC_G5_UMSK (~(((1U << AUDIO_PADC_GEC_G5_LEN) - 1) << AUDIO_PADC_GEC_G5_POS)) - -/* 0x878 : padc_gec_cfg6 */ -#define AUDIO_PADC_GEC_CFG6_OFFSET (0x878) -#define AUDIO_PADC_GEC_G6 AUDIO_PADC_GEC_G6 -#define AUDIO_PADC_GEC_G6_POS (0U) -#define AUDIO_PADC_GEC_G6_LEN (24U) -#define AUDIO_PADC_GEC_G6_MSK (((1U << AUDIO_PADC_GEC_G6_LEN) - 1) << AUDIO_PADC_GEC_G6_POS) -#define AUDIO_PADC_GEC_G6_UMSK (~(((1U << AUDIO_PADC_GEC_G6_LEN) - 1) << AUDIO_PADC_GEC_G6_POS)) - -/* 0x87C : padc_gec_cfg7 */ -#define AUDIO_PADC_GEC_CFG7_OFFSET (0x87C) -#define AUDIO_PADC_GEC_G7 AUDIO_PADC_GEC_G7 -#define AUDIO_PADC_GEC_G7_POS (0U) -#define AUDIO_PADC_GEC_G7_LEN (24U) -#define AUDIO_PADC_GEC_G7_MSK (((1U << AUDIO_PADC_GEC_G7_LEN) - 1) << AUDIO_PADC_GEC_G7_POS) -#define AUDIO_PADC_GEC_G7_UMSK (~(((1U << AUDIO_PADC_GEC_G7_LEN) - 1) << AUDIO_PADC_GEC_G7_POS)) - -/* 0x900 : padc_rx_fifo_ctrl */ -#define AUDIO_PADC_RX_FIFO_CTRL_OFFSET (0x900) -#define AUDIO_PADC_RX_FIFO_FLUSH AUDIO_PADC_RX_FIFO_FLUSH -#define AUDIO_PADC_RX_FIFO_FLUSH_POS (0U) -#define AUDIO_PADC_RX_FIFO_FLUSH_LEN (1U) -#define AUDIO_PADC_RX_FIFO_FLUSH_MSK (((1U << AUDIO_PADC_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_PADC_RX_FIFO_FLUSH_POS) -#define AUDIO_PADC_RX_FIFO_FLUSH_UMSK (~(((1U << AUDIO_PADC_RX_FIFO_FLUSH_LEN) - 1) << AUDIO_PADC_RX_FIFO_FLUSH_POS)) -#define AUDIO_PADC_RXO_INT_EN AUDIO_PADC_RXO_INT_EN -#define AUDIO_PADC_RXO_INT_EN_POS (1U) -#define AUDIO_PADC_RXO_INT_EN_LEN (1U) -#define AUDIO_PADC_RXO_INT_EN_MSK (((1U << AUDIO_PADC_RXO_INT_EN_LEN) - 1) << AUDIO_PADC_RXO_INT_EN_POS) -#define AUDIO_PADC_RXO_INT_EN_UMSK (~(((1U << AUDIO_PADC_RXO_INT_EN_LEN) - 1) << AUDIO_PADC_RXO_INT_EN_POS)) -#define AUDIO_PADC_RXU_INT_EN AUDIO_PADC_RXU_INT_EN -#define AUDIO_PADC_RXU_INT_EN_POS (2U) -#define AUDIO_PADC_RXU_INT_EN_LEN (1U) -#define AUDIO_PADC_RXU_INT_EN_MSK (((1U << AUDIO_PADC_RXU_INT_EN_LEN) - 1) << AUDIO_PADC_RXU_INT_EN_POS) -#define AUDIO_PADC_RXU_INT_EN_UMSK (~(((1U << AUDIO_PADC_RXU_INT_EN_LEN) - 1) << AUDIO_PADC_RXU_INT_EN_POS)) -#define AUDIO_PADC_RXA_INT_EN AUDIO_PADC_RXA_INT_EN -#define AUDIO_PADC_RXA_INT_EN_POS (3U) -#define AUDIO_PADC_RXA_INT_EN_LEN (1U) -#define AUDIO_PADC_RXA_INT_EN_MSK (((1U << AUDIO_PADC_RXA_INT_EN_LEN) - 1) << AUDIO_PADC_RXA_INT_EN_POS) -#define AUDIO_PADC_RXA_INT_EN_UMSK (~(((1U << AUDIO_PADC_RXA_INT_EN_LEN) - 1) << AUDIO_PADC_RXA_INT_EN_POS)) -#define AUDIO_PADC_RX_DRQ_EN AUDIO_PADC_RX_DRQ_EN -#define AUDIO_PADC_RX_DRQ_EN_POS (4U) -#define AUDIO_PADC_RX_DRQ_EN_LEN (1U) -#define AUDIO_PADC_RX_DRQ_EN_MSK (((1U << AUDIO_PADC_RX_DRQ_EN_LEN) - 1) << AUDIO_PADC_RX_DRQ_EN_POS) -#define AUDIO_PADC_RX_DRQ_EN_UMSK (~(((1U << AUDIO_PADC_RX_DRQ_EN_LEN) - 1) << AUDIO_PADC_RX_DRQ_EN_POS)) -#define AUDIO_PADC_RX_DATA_RES AUDIO_PADC_RX_DATA_RES -#define AUDIO_PADC_RX_DATA_RES_POS (5U) -#define AUDIO_PADC_RX_DATA_RES_LEN (1U) -#define AUDIO_PADC_RX_DATA_RES_MSK (((1U << AUDIO_PADC_RX_DATA_RES_LEN) - 1) << AUDIO_PADC_RX_DATA_RES_POS) -#define AUDIO_PADC_RX_DATA_RES_UMSK (~(((1U << AUDIO_PADC_RX_DATA_RES_LEN) - 1) << AUDIO_PADC_RX_DATA_RES_POS)) -#define AUDIO_PADC_RX_CH_EN AUDIO_PADC_RX_CH_EN -#define AUDIO_PADC_RX_CH_EN_POS (8U) -#define AUDIO_PADC_RX_CH_EN_LEN (1U) -#define AUDIO_PADC_RX_CH_EN_MSK (((1U << AUDIO_PADC_RX_CH_EN_LEN) - 1) << AUDIO_PADC_RX_CH_EN_POS) -#define AUDIO_PADC_RX_CH_EN_UMSK (~(((1U << AUDIO_PADC_RX_CH_EN_LEN) - 1) << AUDIO_PADC_RX_CH_EN_POS)) -#define AUDIO_PADC_RX_DRQ_CNT AUDIO_PADC_RX_DRQ_CNT -#define AUDIO_PADC_RX_DRQ_CNT_POS (14U) -#define AUDIO_PADC_RX_DRQ_CNT_LEN (2U) -#define AUDIO_PADC_RX_DRQ_CNT_MSK (((1U << AUDIO_PADC_RX_DRQ_CNT_LEN) - 1) << AUDIO_PADC_RX_DRQ_CNT_POS) -#define AUDIO_PADC_RX_DRQ_CNT_UMSK (~(((1U << AUDIO_PADC_RX_DRQ_CNT_LEN) - 1) << AUDIO_PADC_RX_DRQ_CNT_POS)) -#define AUDIO_PADC_RX_TRG_LEVEL AUDIO_PADC_RX_TRG_LEVEL -#define AUDIO_PADC_RX_TRG_LEVEL_POS (16U) -#define AUDIO_PADC_RX_TRG_LEVEL_LEN (4U) -#define AUDIO_PADC_RX_TRG_LEVEL_MSK (((1U << AUDIO_PADC_RX_TRG_LEVEL_LEN) - 1) << AUDIO_PADC_RX_TRG_LEVEL_POS) -#define AUDIO_PADC_RX_TRG_LEVEL_UMSK (~(((1U << AUDIO_PADC_RX_TRG_LEVEL_LEN) - 1) << AUDIO_PADC_RX_TRG_LEVEL_POS)) -#define AUDIO_PADC_RX_DATA_MODE AUDIO_PADC_RX_DATA_MODE -#define AUDIO_PADC_RX_DATA_MODE_POS (24U) -#define AUDIO_PADC_RX_DATA_MODE_LEN (2U) -#define AUDIO_PADC_RX_DATA_MODE_MSK (((1U << AUDIO_PADC_RX_DATA_MODE_LEN) - 1) << AUDIO_PADC_RX_DATA_MODE_POS) -#define AUDIO_PADC_RX_DATA_MODE_UMSK (~(((1U << AUDIO_PADC_RX_DATA_MODE_LEN) - 1) << AUDIO_PADC_RX_DATA_MODE_POS)) - -/* 0x904 : padc_rx_fifo_status */ -#define AUDIO_PADC_RX_FIFO_STATUS_OFFSET (0x904) -#define AUDIO_PADC_RXO_INT AUDIO_PADC_RXO_INT -#define AUDIO_PADC_RXO_INT_POS (1U) -#define AUDIO_PADC_RXO_INT_LEN (1U) -#define AUDIO_PADC_RXO_INT_MSK (((1U << AUDIO_PADC_RXO_INT_LEN) - 1) << AUDIO_PADC_RXO_INT_POS) -#define AUDIO_PADC_RXO_INT_UMSK (~(((1U << AUDIO_PADC_RXO_INT_LEN) - 1) << AUDIO_PADC_RXO_INT_POS)) -#define AUDIO_PADC_RXU_INT AUDIO_PADC_RXU_INT -#define AUDIO_PADC_RXU_INT_POS (2U) -#define AUDIO_PADC_RXU_INT_LEN (1U) -#define AUDIO_PADC_RXU_INT_MSK (((1U << AUDIO_PADC_RXU_INT_LEN) - 1) << AUDIO_PADC_RXU_INT_POS) -#define AUDIO_PADC_RXU_INT_UMSK (~(((1U << AUDIO_PADC_RXU_INT_LEN) - 1) << AUDIO_PADC_RXU_INT_POS)) -#define AUDIO_PADC_RXA_INT AUDIO_PADC_RXA_INT -#define AUDIO_PADC_RXA_INT_POS (4U) -#define AUDIO_PADC_RXA_INT_LEN (1U) -#define AUDIO_PADC_RXA_INT_MSK (((1U << AUDIO_PADC_RXA_INT_LEN) - 1) << AUDIO_PADC_RXA_INT_POS) -#define AUDIO_PADC_RXA_INT_UMSK (~(((1U << AUDIO_PADC_RXA_INT_LEN) - 1) << AUDIO_PADC_RXA_INT_POS)) -#define AUDIO_PADC_RXA_CNT AUDIO_PADC_RXA_CNT -#define AUDIO_PADC_RXA_CNT_POS (16U) -#define AUDIO_PADC_RXA_CNT_LEN (4U) -#define AUDIO_PADC_RXA_CNT_MSK (((1U << AUDIO_PADC_RXA_CNT_LEN) - 1) << AUDIO_PADC_RXA_CNT_POS) -#define AUDIO_PADC_RXA_CNT_UMSK (~(((1U << AUDIO_PADC_RXA_CNT_LEN) - 1) << AUDIO_PADC_RXA_CNT_POS)) -#define AUDIO_PADC_RXA AUDIO_PADC_RXA -#define AUDIO_PADC_RXA_POS (24U) -#define AUDIO_PADC_RXA_LEN (1U) -#define AUDIO_PADC_RXA_MSK (((1U << AUDIO_PADC_RXA_LEN) - 1) << AUDIO_PADC_RXA_POS) -#define AUDIO_PADC_RXA_UMSK (~(((1U << AUDIO_PADC_RXA_LEN) - 1) << AUDIO_PADC_RXA_POS)) - -/* 0x908 : padc_rx_fifo_data */ -#define AUDIO_PADC_RX_FIFO_DATA_OFFSET (0x908) -#define AUDIO_PADC_RX_DATA AUDIO_PADC_RX_DATA -#define AUDIO_PADC_RX_DATA_POS (0U) -#define AUDIO_PADC_RX_DATA_LEN (32U) -#define AUDIO_PADC_RX_DATA_MSK (((1U << AUDIO_PADC_RX_DATA_LEN) - 1) << AUDIO_PADC_RX_DATA_POS) -#define AUDIO_PADC_RX_DATA_UMSK (~(((1U << AUDIO_PADC_RX_DATA_LEN) - 1) << AUDIO_PADC_RX_DATA_POS)) - -struct audio_reg { - /* 0x0 : aud_top */ - union { - struct { - uint32_t audio_ckg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t dac_itf_inv_sel : 1; /* [ 1], r/w, 0x1 */ - uint32_t adc_itf_inv_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t pdm_itf_inv_sel : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_23 : 20; /* [23: 4], rsvd, 0x0 */ - uint32_t dac_rate : 3; /* [26:24], r/w, 0x4 */ - uint32_t reserved_27 : 1; /* [ 27], rsvd, 0x0 */ - uint32_t adc_rate : 3; /* [30:28], r/w, 0x1 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } aud_top; - - /* 0x4 : aud_itf */ - union { - struct { - uint32_t adc_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t dac_0_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t dac_1_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t aec_0_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t aec_1_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_12 : 6; /* [12: 7], rsvd, 0x0 */ - uint32_t aud_rx0_sel : 3; /* [15:13], r/w, 0x0 */ - uint32_t aud_rx1_sel : 3; /* [18:16], r/w, 0x1 */ - uint32_t aud_rx2_sel : 3; /* [21:19], r/w, 0x2 */ - uint32_t aud_rx3_sel : 3; /* [24:22], r/w, 0x3 */ - uint32_t aud_rx4_sel : 3; /* [27:25], r/w, 0x4 */ - uint32_t aud_tx0_sel : 1; /* [ 28], r/w, 0x0 */ - uint32_t aud_tx1_sel : 1; /* [ 29], r/w, 0x1 */ - uint32_t adc_itf_en : 1; /* [ 30], r/w, 0x0 */ - uint32_t dac_itf_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } aud_itf; - - /* 0x8 : adc_0 */ - union { - struct { - uint32_t adc_0_fir_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_fir_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_fir_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_scal : 6; /* [ 8: 3], r/w, 0x20 */ - uint32_t adc_1_scal : 6; /* [14: 9], r/w, 0x20 */ - uint32_t adc_2_scal : 6; /* [20:15], r/w, 0x20 */ - uint32_t reserved_21_28 : 8; /* [28:21], rsvd, 0x0 */ - uint32_t adc_dither_data : 1; /* [ 29], r, 0x1 */ - uint32_t adc_lfsr_mode : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_0; - - /* 0xC : adc_1 */ - union { - struct { - uint32_t adc_0_k1 : 4; /* [ 3: 0], r/w, 0x8 */ - uint32_t adc_0_k1_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t adc_0_k2 : 4; /* [ 8: 5], r/w, 0xd */ - uint32_t adc_0_k2_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t adc_1_k1 : 4; /* [13:10], r/w, 0x8 */ - uint32_t adc_1_k1_en : 1; /* [ 14], r/w, 0x1 */ - uint32_t adc_1_k2 : 4; /* [18:15], r/w, 0xd */ - uint32_t adc_1_k2_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t adc_2_k1 : 4; /* [23:20], r/w, 0x8 */ - uint32_t adc_2_k1_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t adc_2_k2 : 4; /* [28:25], r/w, 0xd */ - uint32_t adc_2_k2_en : 1; /* [ 29], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } adc_1; - - /* 0x10 : dac_0 */ - union { - struct { - uint32_t adc_pdm_h : 6; /* [ 5: 0], r/w, 0x1 */ - uint32_t adc_pdm_l : 6; /* [11: 6], r/w, 0x3f */ - uint32_t adc_0_src : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_0_pdm_lvl_swap : 1; /* [ 13], r/w, 0x0 */ - uint32_t adc_0_mash_bit_swap : 1; /* [ 14], r/w, 0x0 */ - uint32_t adc_1_src : 1; /* [ 15], r/w, 0x0 */ - uint32_t adc_1_pdm_lvl_swap : 1; /* [ 16], r/w, 0x0 */ - uint32_t adc_1_mash_bit_swap : 1; /* [ 17], r/w, 0x0 */ - uint32_t adc_2_src : 1; /* [ 18], r/w, 0x0 */ - uint32_t adc_2_pdm_lvl_swap : 1; /* [ 19], r/w, 0x0 */ - uint32_t adc_2_mash_bit_swap : 1; /* [ 20], r/w, 0x0 */ - uint32_t mix_0_sel : 2; /* [22:21], r/w, 0x0 */ - uint32_t mix_0_mode : 2; /* [24:23], r/w, 0x0 */ - uint32_t mix_0_att_mode1 : 3; /* [27:25], r/w, 0x0 */ - uint32_t mix_0_att_mode2 : 3; /* [30:28], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dac_0; - - /* 0x14 : dac_1 */ - union { - struct { - uint32_t dac_dem_bypass : 1; /* [ 0], r/w, 0x0 */ - uint32_t dac_dem_out_swap : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_4 : 3; /* [ 4: 2], rsvd, 0x0 */ - uint32_t dac_dsm_order : 1; /* [ 5], r/w, 0x0 */ - uint32_t dac_dsm_scaling_factor : 4; /* [ 9: 6], r/w, 0xf */ - uint32_t dac_dsm_scaling_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t dac_dsm_dither_amp : 3; /* [13:11], r/w, 0x0 */ - uint32_t dac_dsm_dither_en : 1; /* [ 14], r/w, 0x1 */ - uint32_t dac_dsm_dither_prbs_mode : 2; /* [16:15], r/w, 0x0 */ - uint32_t reserved_17_20 : 4; /* [20:17], rsvd, 0x0 */ - uint32_t mix_1_sel : 2; /* [22:21], r/w, 0x0 */ - uint32_t mix_1_mode : 2; /* [24:23], r/w, 0x0 */ - uint32_t mix_1_att_mode1 : 3; /* [27:25], r/w, 0x0 */ - uint32_t mix_1_att_mode2 : 3; /* [30:28], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dac_1; - - /* 0x18 : aec_0 */ - union { - struct { - uint32_t reserved_0_4 : 5; /* [ 4: 0], rsvd, 0x0 */ - uint32_t aec_0_atten_mode : 3; /* [ 7: 5], r/w, 0x0 */ - uint32_t aec_1_atten_mode : 3; /* [10: 8], r/w, 0x0 */ - uint32_t aec_record_vld_4s_div : 2; /* [12:11], r/w, 0x0 */ - uint32_t aec_record_vld_4s_en : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } aec_0; - - /* 0x1C : pdm_0 */ - union { - struct { - uint32_t pdm_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t pdm_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t pdm_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_pdm_sel : 3; /* [ 5: 3], r/w, 0x0 */ - uint32_t adc_1_pdm_sel : 3; /* [ 8: 6], r/w, 0x1 */ - uint32_t adc_2_pdm_sel : 3; /* [11: 9], r/w, 0x2 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_0; - - /* 0x20 : rsvd0 */ - union { - struct { - uint32_t rsvd0 : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } rsvd0; - - /* 0x24 : dbg_0 */ - union { - struct { - uint32_t aud_sin_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t aud_sin_step : 3; /* [ 3: 1], r/w, 0x2 */ - uint32_t reserved_4_17 : 14; /* [17: 4], rsvd, 0x0 */ - uint32_t audio_test_out_sel : 2; /* [19:18], r/w, 0x0 */ - uint32_t dac_test_clkin_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc_test_clkin_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t dac_test_din_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t adc_test_din_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t aud_test_read_sel : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_0; - - /* 0x28 : dbg_1 */ - union { - struct { - uint32_t aud_test_read : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } dbg_1; - - /* 0x2C : dbg_2 */ - union { - struct { - uint32_t adc_fir_4s_val : 20; /* [19: 0], r/w, 0x0 */ - uint32_t adc_0_fir_4s_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc_1_fir_4s_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t adc_2_fir_4s_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t adc_in_0_test_sel : 1; /* [ 23], r/w, 0x0 */ - uint32_t adc_in_1_test_sel : 1; /* [ 24], r/w, 0x0 */ - uint32_t adc_in_2_test_sel : 1; /* [ 25], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_2; - - /* 0x30 : dbg_3 */ - union { - struct { - uint32_t dac_4s_val : 20; /* [19: 0], r/w, 0x0 */ - uint32_t dac_dwa_0_4s_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t dac_dwa_1_4s_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t dac_in_0_test_sel : 1; /* [ 22], r/w, 0x0 */ - uint32_t dac_in_1_test_sel : 1; /* [ 23], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_3; - - /* 0x34 : dbg_4 */ - union { - struct { - uint32_t adc_in_ratio_4s_val : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_in_ch0_ratio_4s_val : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_in_ch1_ratio_4s_val : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_in_ch2_ratio_4s_val : 1; /* [ 3], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s_val : 1; /* [ 4], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s : 1; /* [ 5], r/w, 0x0 */ - uint32_t dac_out_ratio_4s_val : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t aec_fs_rate_4s_val : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbg_4; - - /* 0x38 reserved */ - uint8_t RESERVED0x38[72]; - - /* 0x80 : rx_fifo_ctrl */ - union { - struct { - uint32_t rx_fifo_flush : 1; /* [ 0], w1p, 0x0 */ - uint32_t rxo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t rxu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t rxa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t rx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_ch_en : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13 : 1; /* [ 13], rsvd, 0x0 */ - uint32_t rx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t rx_trg_level : 7; /* [22:16], r/w, 0x27 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t rx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_fifo_ctrl; - - /* 0x84 : rx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t rxo_int : 1; /* [ 1], r, 0x0 */ - uint32_t rxu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t rxa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t rxa_cnt : 7; /* [22:16], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t rxa : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_fifo_status; - - /* 0x88 : rx_fifo_data */ - union { - struct { - uint32_t rx_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } rx_fifo_data; - - /* 0x8C : tx_fifo_ctrl */ - union { - struct { - uint32_t tx_fifo_flush : 1; /* [ 0], w1p, 0x0 */ - uint32_t txo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t txu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t txa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t tx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t tx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t tx_ch_en : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t reserved_10_13 : 4; /* [13:10], rsvd, 0x0 */ - uint32_t tx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t tx_trg_level : 6; /* [21:16], r/w, 0xf */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t tx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_fifo_ctrl; - - /* 0x90 : tx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t txo_int : 1; /* [ 1], r, 0x0 */ - uint32_t txu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t txa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t txa_cnt : 6; /* [21:16], r, 0x20 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t txa : 1; /* [ 24], r, 0x1 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_fifo_status; - - /* 0x94 : tx_fifo_data */ - union { - struct { - uint32_t tx_data : 32; /* [31: 0], w, 0x0 */ - } BF; - uint32_t WORD; - } tx_fifo_data; - - /* 0x98 reserved */ - uint8_t RESERVED0x98[360]; - - /* 0x200 : peq_00_b0 */ - union { - struct { - uint32_t peq_00_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_00_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_00_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_b0; - - /* 0x204 : peq_00_b1 */ - union { - struct { - uint32_t peq_00_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_b1; - - /* 0x208 : peq_00_b2 */ - union { - struct { - uint32_t peq_00_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_b2; - - /* 0x20C : peq_00_a1 */ - union { - struct { - uint32_t peq_00_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_a1; - - /* 0x210 : peq_00_a2 */ - union { - struct { - uint32_t peq_00_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_00_a2; - - /* 0x214 : peq_01_b0 */ - union { - struct { - uint32_t peq_01_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_01_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_01_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_b0; - - /* 0x218 : peq_01_b1 */ - union { - struct { - uint32_t peq_01_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_b1; - - /* 0x21C : peq_01_b2 */ - union { - struct { - uint32_t peq_01_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_b2; - - /* 0x220 : peq_01_a1 */ - union { - struct { - uint32_t peq_01_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_a1; - - /* 0x224 : peq_01_a2 */ - union { - struct { - uint32_t peq_01_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_01_a2; - - /* 0x228 : peq_02_b0 */ - union { - struct { - uint32_t peq_02_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_02_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_02_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_b0; - - /* 0x22C : peq_02_b1 */ - union { - struct { - uint32_t peq_02_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_b1; - - /* 0x230 : peq_02_b2 */ - union { - struct { - uint32_t peq_02_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_b2; - - /* 0x234 : peq_02_a1 */ - union { - struct { - uint32_t peq_02_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_a1; - - /* 0x238 : peq_02_a2 */ - union { - struct { - uint32_t peq_02_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_02_a2; - - /* 0x23C : peq_03_b0 */ - union { - struct { - uint32_t peq_03_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_03_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_03_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_b0; - - /* 0x240 : peq_03_b1 */ - union { - struct { - uint32_t peq_03_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_b1; - - /* 0x244 : peq_03_b2 */ - union { - struct { - uint32_t peq_03_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_b2; - - /* 0x248 : peq_03_a1 */ - union { - struct { - uint32_t peq_03_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_a1; - - /* 0x24C : peq_03_a2 */ - union { - struct { - uint32_t peq_03_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_03_a2; - - /* 0x250 : peq_04_b0 */ - union { - struct { - uint32_t peq_04_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_04_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_04_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_b0; - - /* 0x254 : peq_04_b1 */ - union { - struct { - uint32_t peq_04_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_b1; - - /* 0x258 : peq_04_b2 */ - union { - struct { - uint32_t peq_04_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_b2; - - /* 0x25C : peq_04_a1 */ - union { - struct { - uint32_t peq_04_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_a1; - - /* 0x260 : peq_04_a2 */ - union { - struct { - uint32_t peq_04_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_04_a2; - - /* 0x264 : peq_05_b0 */ - union { - struct { - uint32_t peq_05_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_05_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_05_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_b0; - - /* 0x268 : peq_05_b1 */ - union { - struct { - uint32_t peq_05_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_b1; - - /* 0x26C : peq_05_b2 */ - union { - struct { - uint32_t peq_05_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_b2; - - /* 0x270 : peq_05_a1 */ - union { - struct { - uint32_t peq_05_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_a1; - - /* 0x274 : peq_05_a2 */ - union { - struct { - uint32_t peq_05_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_05_a2; - - /* 0x278 : peq_06_b0 */ - union { - struct { - uint32_t peq_06_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_06_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_06_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_b0; - - /* 0x27C : peq_06_b1 */ - union { - struct { - uint32_t peq_06_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_b1; - - /* 0x280 : peq_06_b2 */ - union { - struct { - uint32_t peq_06_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_b2; - - /* 0x284 : peq_06_a1 */ - union { - struct { - uint32_t peq_06_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_a1; - - /* 0x288 : peq_06_a2 */ - union { - struct { - uint32_t peq_06_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_06_a2; - - /* 0x28C : peq_07_b0 */ - union { - struct { - uint32_t peq_07_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_07_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_07_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_b0; - - /* 0x290 : peq_07_b1 */ - union { - struct { - uint32_t peq_07_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_b1; - - /* 0x294 : peq_07_b2 */ - union { - struct { - uint32_t peq_07_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_b2; - - /* 0x298 : peq_07_a1 */ - union { - struct { - uint32_t peq_07_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_a1; - - /* 0x29C : peq_07_a2 */ - union { - struct { - uint32_t peq_07_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_07_a2; - - /* 0x2A0 : peq_08_b0 */ - union { - struct { - uint32_t peq_08_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_08_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_08_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_b0; - - /* 0x2A4 : peq_08_b1 */ - union { - struct { - uint32_t peq_08_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_b1; - - /* 0x2A8 : peq_08_b2 */ - union { - struct { - uint32_t peq_08_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_b2; - - /* 0x2AC : peq_08_a1 */ - union { - struct { - uint32_t peq_08_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_a1; - - /* 0x2B0 : peq_08_a2 */ - union { - struct { - uint32_t peq_08_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_08_a2; - - /* 0x2B4 : peq_09_b0 */ - union { - struct { - uint32_t peq_09_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_09_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_09_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_b0; - - /* 0x2B8 : peq_09_b1 */ - union { - struct { - uint32_t peq_09_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_b1; - - /* 0x2BC : peq_09_b2 */ - union { - struct { - uint32_t peq_09_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_b2; - - /* 0x2C0 : peq_09_a1 */ - union { - struct { - uint32_t peq_09_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_a1; - - /* 0x2C4 : peq_09_a2 */ - union { - struct { - uint32_t peq_09_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_09_a2; - - /* 0x2C8 : peq_10_b0 */ - union { - struct { - uint32_t peq_10_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_10_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_10_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_b0; - - /* 0x2CC : peq_10_b1 */ - union { - struct { - uint32_t peq_10_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_b1; - - /* 0x2D0 : peq_10_b2 */ - union { - struct { - uint32_t peq_10_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_b2; - - /* 0x2D4 : peq_10_a1 */ - union { - struct { - uint32_t peq_10_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_a1; - - /* 0x2D8 : peq_10_a2 */ - union { - struct { - uint32_t peq_10_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_10_a2; - - /* 0x2DC : peq_11_b0 */ - union { - struct { - uint32_t peq_11_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_11_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_11_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_b0; - - /* 0x2E0 : peq_11_b1 */ - union { - struct { - uint32_t peq_11_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_b1; - - /* 0x2E4 : peq_11_b2 */ - union { - struct { - uint32_t peq_11_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_b2; - - /* 0x2E8 : peq_11_a1 */ - union { - struct { - uint32_t peq_11_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_a1; - - /* 0x2EC : peq_11_a2 */ - union { - struct { - uint32_t peq_11_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_11_a2; - - /* 0x2F0 : peq_12_b0 */ - union { - struct { - uint32_t peq_12_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_12_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_12_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_b0; - - /* 0x2F4 : peq_12_b1 */ - union { - struct { - uint32_t peq_12_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_b1; - - /* 0x2F8 : peq_12_b2 */ - union { - struct { - uint32_t peq_12_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_b2; - - /* 0x2FC : peq_12_a1 */ - union { - struct { - uint32_t peq_12_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_a1; - - /* 0x300 : peq_12_a2 */ - union { - struct { - uint32_t peq_12_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_12_a2; - - /* 0x304 : peq_13_b0 */ - union { - struct { - uint32_t peq_13_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_13_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_13_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_b0; - - /* 0x308 : peq_13_b1 */ - union { - struct { - uint32_t peq_13_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_b1; - - /* 0x30C : peq_13_b2 */ - union { - struct { - uint32_t peq_13_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_b2; - - /* 0x310 : peq_13_a1 */ - union { - struct { - uint32_t peq_13_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_a1; - - /* 0x314 : peq_13_a2 */ - union { - struct { - uint32_t peq_13_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_13_a2; - - /* 0x318 : peq_14_b0 */ - union { - struct { - uint32_t peq_14_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_14_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_14_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_b0; - - /* 0x31C : peq_14_b1 */ - union { - struct { - uint32_t peq_14_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_b1; - - /* 0x320 : peq_14_b2 */ - union { - struct { - uint32_t peq_14_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_b2; - - /* 0x324 : peq_14_a1 */ - union { - struct { - uint32_t peq_14_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_a1; - - /* 0x328 : peq_14_a2 */ - union { - struct { - uint32_t peq_14_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_14_a2; - - /* 0x32C : peq_15_b0 */ - union { - struct { - uint32_t peq_15_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_15_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_15_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_b0; - - /* 0x330 : peq_15_b1 */ - union { - struct { - uint32_t peq_15_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_b1; - - /* 0x334 : peq_15_b2 */ - union { - struct { - uint32_t peq_15_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_b2; - - /* 0x338 : peq_15_a1 */ - union { - struct { - uint32_t peq_15_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_a1; - - /* 0x33C : peq_15_a2 */ - union { - struct { - uint32_t peq_15_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_15_a2; - - /* 0x340 : peq_16_b0 */ - union { - struct { - uint32_t peq_16_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_16_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_16_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_b0; - - /* 0x344 : peq_16_b1 */ - union { - struct { - uint32_t peq_16_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_b1; - - /* 0x348 : peq_16_b2 */ - union { - struct { - uint32_t peq_16_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_b2; - - /* 0x34C : peq_16_a1 */ - union { - struct { - uint32_t peq_16_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_a1; - - /* 0x350 : peq_16_a2 */ - union { - struct { - uint32_t peq_16_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_16_a2; - - /* 0x354 : peq_17_b0 */ - union { - struct { - uint32_t peq_17_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_17_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_17_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_b0; - - /* 0x358 : peq_17_b1 */ - union { - struct { - uint32_t peq_17_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_b1; - - /* 0x35C : peq_17_b2 */ - union { - struct { - uint32_t peq_17_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_b2; - - /* 0x360 : peq_17_a1 */ - union { - struct { - uint32_t peq_17_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_a1; - - /* 0x364 : peq_17_a2 */ - union { - struct { - uint32_t peq_17_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_17_a2; - - /* 0x368 : peq_18_b0 */ - union { - struct { - uint32_t peq_18_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_18_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_18_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_b0; - - /* 0x36C : peq_18_b1 */ - union { - struct { - uint32_t peq_18_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_b1; - - /* 0x370 : peq_18_b2 */ - union { - struct { - uint32_t peq_18_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_b2; - - /* 0x374 : peq_18_a1 */ - union { - struct { - uint32_t peq_18_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_a1; - - /* 0x378 : peq_18_a2 */ - union { - struct { - uint32_t peq_18_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_18_a2; - - /* 0x37C : peq_19_b0 */ - union { - struct { - uint32_t peq_19_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_19_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_19_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_b0; - - /* 0x380 : peq_19_b1 */ - union { - struct { - uint32_t peq_19_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_b1; - - /* 0x384 : peq_19_b2 */ - union { - struct { - uint32_t peq_19_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_b2; - - /* 0x388 : peq_19_a1 */ - union { - struct { - uint32_t peq_19_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_a1; - - /* 0x38C : peq_19_a2 */ - union { - struct { - uint32_t peq_19_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_19_a2; - - /* 0x390 : peq_20_b0 */ - union { - struct { - uint32_t peq_20_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_20_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_20_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_29 : 8; /* [29:22], rsvd, 0x0 */ - uint32_t adc_peq_in_sel : 2; /* [31:30], r/w, 0x3 */ - } BF; - uint32_t WORD; - } peq_20_b0; - - /* 0x394 : peq_20_b1 */ - union { - struct { - uint32_t peq_20_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_b1; - - /* 0x398 : peq_20_b2 */ - union { - struct { - uint32_t peq_20_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_b2; - - /* 0x39C : peq_20_a1 */ - union { - struct { - uint32_t peq_20_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_a1; - - /* 0x3A0 : peq_20_a2 */ - union { - struct { - uint32_t peq_20_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_20_a2; - - /* 0x3A4 : peq_21_b0 */ - union { - struct { - uint32_t peq_21_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_21_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_21_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_b0; - - /* 0x3A8 : peq_21_b1 */ - union { - struct { - uint32_t peq_21_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_b1; - - /* 0x3AC : peq_21_b2 */ - union { - struct { - uint32_t peq_21_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_b2; - - /* 0x3B0 : peq_21_a1 */ - union { - struct { - uint32_t peq_21_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_a1; - - /* 0x3B4 : peq_21_a2 */ - union { - struct { - uint32_t peq_21_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_21_a2; - - /* 0x3B8 : peq_22_b0 */ - union { - struct { - uint32_t peq_22_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_22_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_22_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_b0; - - /* 0x3BC : peq_22_b1 */ - union { - struct { - uint32_t peq_22_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_b1; - - /* 0x3C0 : peq_22_b2 */ - union { - struct { - uint32_t peq_22_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_b2; - - /* 0x3C4 : peq_22_a1 */ - union { - struct { - uint32_t peq_22_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_a1; - - /* 0x3C8 : peq_22_a2 */ - union { - struct { - uint32_t peq_22_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_22_a2; - - /* 0x3CC : peq_23_b0 */ - union { - struct { - uint32_t peq_23_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_23_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_23_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_b0; - - /* 0x3D0 : peq_23_b1 */ - union { - struct { - uint32_t peq_23_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_b1; - - /* 0x3D4 : peq_23_b2 */ - union { - struct { - uint32_t peq_23_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_b2; - - /* 0x3D8 : peq_23_a1 */ - union { - struct { - uint32_t peq_23_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_a1; - - /* 0x3DC : peq_23_a2 */ - union { - struct { - uint32_t peq_23_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_23_a2; - - /* 0x3E0 : peq_24_b0 */ - union { - struct { - uint32_t peq_24_b0 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t peq_24_byp : 1; /* [ 20], r/w, 0x1 */ - uint32_t peq_24_qfmt : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_b0; - - /* 0x3E4 : peq_24_b1 */ - union { - struct { - uint32_t peq_24_b1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_b1; - - /* 0x3E8 : peq_24_b2 */ - union { - struct { - uint32_t peq_24_b2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_b2; - - /* 0x3EC : peq_24_a1 */ - union { - struct { - uint32_t peq_24_a1 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_a1; - - /* 0x3F0 : peq_24_a2 */ - union { - struct { - uint32_t peq_24_a2 : 20; /* [19: 0], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } peq_24_a2; - - /* 0x3f4 reserved */ - uint8_t RESERVED0x3f4[12]; - - /* 0x400 : adc_h */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_h_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_h_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_h_ctrl_mode : 2; /* [11:10], r/w, 0x0 */ - uint32_t adc_h_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_h_volume : 9; /* [21:13], r, 0x0 */ - uint32_t adc_h_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_h_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_h_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_h_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_h; - - /* 0x404 : adc_h_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t adc_h_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_h_misc; - - /* 0x408 : adc_s0 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_s0_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_s0_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_s0_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t adc_s0_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_s0_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t adc_s0_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_s0_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_s0_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_s0_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_s0; - - /* 0x40C : adc_s0_misc */ - union { - struct { - uint32_t adc_s012_volume_update : 1; /* [ 0], r/w, 0x1 */ - uint32_t adc_s012_mute : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_27 : 26; /* [27: 2], rsvd, 0x0 */ - uint32_t adc_s0_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_s0_misc; - - /* 0x410 : adc_s1 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_s1_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_s1_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_s1_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t adc_s1_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_s1_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t adc_s1_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_s1_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_s1_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_s1_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_s1; - - /* 0x414 : adc_s1_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t adc_s1_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_s1_misc; - - /* 0x418 : adc_s2 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t adc_s2_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x1 */ - uint32_t adc_s2_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t adc_s2_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t adc_s2_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t adc_s2_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t adc_s2_mute_rmpup_rate : 4; /* [25:22], r/w, 0x1 */ - uint32_t adc_s2_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x1 */ - uint32_t adc_s2_mute_softmode : 1; /* [ 30], r/w, 0x0 */ - uint32_t adc_s2_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_s2; - - /* 0x41C : adc_s2_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t adc_s2_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } adc_s2_misc; - - /* 0x420 : adc_agc_0 */ - union { - struct { - uint32_t adc_agc_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_2 : 2; /* [ 2: 1], rsvd, 0x0 */ - uint32_t agc_min_gain_qdb : 9; /* [11: 3], r/w, 0x1a0 */ - uint32_t agc_max_gain_qdb : 9; /* [20:12], r/w, 0x18 */ - uint32_t agc_force_gain_ind : 10; /* [30:21], r/w, 0x0 */ - uint32_t agc_force_gain_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } adc_agc_0; - - /* 0x424 : adc_agc_1 */ - union { - struct { - uint32_t adc0_pga_hw_ctrl : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc1_pga_hw_ctrl : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc2_pga_hw_ctrl : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t agc_attack_time_ms : 4; /* [ 7: 4], r/w, 0x1 */ - uint32_t agc_decay_time_ms : 4; /* [11: 8], r/w, 0x5 */ - uint32_t agc_hold_time_ms : 4; /* [15:12], r/w, 0x6 */ - uint32_t agc_level_hyst_decay : 5; /* [20:16], r/w, 0x4 */ - uint32_t agc_level_hyst_attack : 5; /* [25:21], r/w, 0x4 */ - uint32_t agc_level_target : 6; /* [31:26], r/w, 0x34 */ - } BF; - uint32_t WORD; - } adc_agc_1; - - /* 0x428 : adc_agc_2 */ - union { - struct { - uint32_t agc_noise_enter_time_ms : 7; /* [ 6: 0], r/w, 0x32 */ - uint32_t agc_silence_gain_wait_ms : 4; /* [10: 7], r/w, 0x0 */ - uint32_t agc_silence_gain_qdb : 10; /* [20:11], r/w, 0x0 */ - uint32_t agc_noise_gate_hyst : 3; /* [23:21], r/w, 0x2 */ - uint32_t agc_noise_gate_th : 8; /* [31:24], r/w, 0xba */ - } BF; - uint32_t WORD; - } adc_agc_2; - - /* 0x42C : adc_agc_3 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t agc_pga_ctrl_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t agc_average_time : 5; /* [ 7: 3], r/w, 0x4 */ - uint32_t agc_release_time : 5; /* [12: 8], r/w, 0x10 */ - uint32_t agc_attack_time : 5; /* [17:13], r/w, 0x6 */ - uint32_t agc_detect_mode : 1; /* [ 18], r/w, 0x0 */ - uint32_t agc_src_select : 2; /* [20:19], r/w, 0x3 */ - uint32_t agc_dbv_settle_time : 4; /* [24:21], r/w, 0x5 */ - uint32_t agc_noise_exit_time_ms : 7; /* [31:25], r/w, 0x1 */ - } BF; - uint32_t WORD; - } adc_agc_3; - - /* 0x430 : audio_status */ - union { - struct { - uint32_t adc_h0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t adc_h0_mute_done : 1; /* [ 1], r, 0x1 */ - uint32_t adc_h1_busy : 1; /* [ 2], r, 0x0 */ - uint32_t adc_h1_mute_done : 1; /* [ 3], r, 0x1 */ - uint32_t adc_h2_busy : 1; /* [ 4], r, 0x0 */ - uint32_t adc_h2_mute_done : 1; /* [ 5], r, 0x1 */ - uint32_t adc_s0_int : 1; /* [ 6], r, 0x0 */ - uint32_t adc_s0_int_clr : 1; /* [ 7], r/w, 0x0 */ - uint32_t adc_s1_int : 1; /* [ 8], r, 0x0 */ - uint32_t adc_s1_int_clr : 1; /* [ 9], r/w, 0x0 */ - uint32_t adc_s2_int : 1; /* [ 10], r, 0x0 */ - uint32_t adc_s2_int_clr : 1; /* [ 11], r/w, 0x0 */ - uint32_t dac_h0_busy : 1; /* [ 12], r, 0x0 */ - uint32_t dac_h0_mute_done : 1; /* [ 13], r, 0x1 */ - uint32_t dac_h1_busy : 1; /* [ 14], r, 0x0 */ - uint32_t dac_h1_mute_done : 1; /* [ 15], r, 0x1 */ - uint32_t dac_s0_int : 1; /* [ 16], r, 0x0 */ - uint32_t dac_s0_int_clr : 1; /* [ 17], r/w, 0x0 */ - uint32_t dac_s1_int : 1; /* [ 18], r, 0x0 */ - uint32_t dac_s1_int_clr : 1; /* [ 19], r/w, 0x0 */ - uint32_t ngt_amute : 1; /* [ 20], r, 0x0 */ - uint32_t ngt_dmute : 1; /* [ 21], r, 0x0 */ - uint32_t ngt_dmute_done : 1; /* [ 22], r, 0x1 */ - uint32_t zd_amute : 1; /* [ 23], r, 0x0 */ - uint32_t audio_int_all : 1; /* [ 24], r, 0x0 */ - uint32_t vad_int : 1; /* [ 25], r, 0x0 */ - uint32_t vad_int_clr : 1; /* [ 26], r/w, 0x0 */ - uint32_t vad_int_set : 1; /* [ 27], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } audio_status; - - /* 0x434 : dac_s0 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t dac_s0_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x6 */ - uint32_t dac_s0_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t dac_s0_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t dac_s0_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t dac_s0_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t dac_s0_mute_rmpup_rate : 4; /* [25:22], r/w, 0x0 */ - uint32_t dac_s0_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x6 */ - uint32_t dac_s0_mute_softmode : 1; /* [ 30], r/w, 0x1 */ - uint32_t dac_s0_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_s0; - - /* 0x438 : dac_s0_misc */ - union { - struct { - uint32_t dac_s01_volume_update : 1; /* [ 0], r/w, 0x1 */ - uint32_t dac_s01_mute : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_27 : 26; /* [27: 2], rsvd, 0x0 */ - uint32_t dac_s0_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } dac_s0_misc; - - /* 0x43C : dac_s1 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t dac_s1_ctrl_rmp_rate : 4; /* [ 5: 2], r/w, 0x6 */ - uint32_t dac_s1_ctrl_zcd_rate : 4; /* [ 9: 6], r/w, 0x2 */ - uint32_t dac_s1_ctrl_mode : 2; /* [11:10], r/w, 0x2 */ - uint32_t dac_s1_volume_update : 1; /* [ 12], r/w, 0x0 */ - uint32_t dac_s1_volume : 9; /* [21:13], r/w, 0x0 */ - uint32_t dac_s1_mute_rmpup_rate : 4; /* [25:22], r/w, 0x0 */ - uint32_t dac_s1_mute_rmpdn_rate : 4; /* [29:26], r/w, 0x6 */ - uint32_t dac_s1_mute_softmode : 1; /* [ 30], r/w, 0x1 */ - uint32_t dac_s1_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_s1; - - /* 0x440 : dac_s1_misc */ - union { - struct { - uint32_t reserved_0_27 : 28; /* [27: 0], rsvd, 0x0 */ - uint32_t dac_s1_ctrl_zcd_timeout : 4; /* [31:28], r/w, 0x4 */ - } BF; - uint32_t WORD; - } dac_s1_misc; - - /* 0x444 : dac_drc_0 */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t drc_ngt_downsample_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t drc_rls_time : 5; /* [13: 9], r/w, 0x4 */ - uint32_t drc_att_time : 5; /* [18:14], r/w, 0xa */ - uint32_t drc_avg_time : 5; /* [23:19], r/w, 0x8 */ - uint32_t drc_avg_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t drc_avg_sel : 2; /* [26:25], r/w, 0x3 */ - uint32_t drc_peak_sel : 2; /* [28:27], r/w, 0x3 */ - uint32_t drc_raw_sel : 2; /* [30:29], r/w, 0x3 */ - uint32_t drc_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_drc_0; - - /* 0x448 : dac_drc_1 */ - union { - struct { - uint32_t drc_release_time : 4; /* [ 3: 0], r/w, 0x1 */ - uint32_t drc_attack_time : 4; /* [ 7: 4], r/w, 0x1 */ - uint32_t drc_makeup_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t drc_slope_mode_e : 2; /* [13:12], r/w, 0x1 */ - uint32_t drc_slope_mode_c : 2; /* [15:14], r/w, 0x1 */ - uint32_t drc_threshold_e : 6; /* [21:16], r/w, 0x24 */ - uint32_t drc_threshold_c : 5; /* [26:22], r/w, 0x10 */ - uint32_t drc_threshold_l : 5; /* [31:27], r/w, 0x8 */ - } BF; - uint32_t WORD; - } dac_drc_1; - - /* 0x44C : dac_ngt_0 */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t ngt_amute_on : 1; /* [ 2], r/w, 0x0 */ - uint32_t ngt_dmute_on : 1; /* [ 3], r/w, 0x0 */ - uint32_t ngt_signal_hold_time_k : 4; /* [ 7: 4], r/w, 0x2 */ - uint32_t ngt_signal_hold_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t ngt_noise_hold_time_k : 4; /* [12: 9], r/w, 0x8 */ - uint32_t ngt_noise_hold_en : 1; /* [ 13], r/w, 0x1 */ - uint32_t ngt_hysteresis : 2; /* [15:14], r/w, 0x2 */ - uint32_t ngt_threshold : 8; /* [23:16], r/w, 0xb5 */ - uint32_t ngt_avg_time : 5; /* [28:24], r/w, 0x2 */ - uint32_t ngt_src_sel : 2; /* [30:29], r/w, 0x3 */ - uint32_t ngt_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_ngt_0; - - /* 0x450 : dac_zd_0 */ - union { - struct { - uint32_t zd_time : 15; /* [14: 0], r/w, 0x200 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t zd_en : 2; /* [17:16], r/w, 0x0 */ - uint32_t reserved_18_29 : 12; /* [29:18], rsvd, 0x0 */ - uint32_t dac_mute_hw_ctrl : 1; /* [ 30], r/w, 0x1 */ - uint32_t dac_mute : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dac_zd_0; - - /* 0x454 reserved */ - uint8_t RESERVED0x454[428]; - - /* 0x600 : vad_ctrl_0 */ - union { - struct { - uint32_t vad_nth_minlmt_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t vad_nth_maxlmt_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t vad_nbuf_monit_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t vad_nbuf_monit_ctrl : 2; /* [ 5: 4], r/w, 0x1 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t vad_nbuf_len_ctrl : 3; /* [10: 8], r/w, 0x2 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t vad_out_sel : 2; /* [13:12], r/w, 0x1 */ - uint32_t vad_frametime_ctrl : 2; /* [15:14], r/w, 0x1 */ - uint32_t vad_frameshift_ctrl : 3; /* [18:16], r/w, 0x0 */ - uint32_t vad_out : 1; /* [ 19], r, 0x0 */ - uint32_t vad_in_sel : 3; /* [22:20], r/w, 0x0 */ - uint32_t vad_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_0; - - /* 0x604 : vad_ctrl_1 */ - union { - struct { - uint32_t vad_nth_scale : 8; /* [ 7: 0], r/w, 0x33 */ - uint32_t vad_nth_bias : 16; /* [23: 8], r/w, 0x33 */ - uint32_t vad_nbuf_discard : 8; /* [31:24], r/w, 0x10 */ - } BF; - uint32_t WORD; - } vad_ctrl_1; - - /* 0x608 : vad_ctrl_2 */ - union { - struct { - uint32_t vad_nth_minlmt : 16; /* [15: 0], r/w, 0x66 */ - uint32_t vad_nth_maxlmt : 16; /* [31:16], r/w, 0x1400 */ - } BF; - uint32_t WORD; - } vad_ctrl_2; - - /* 0x60C : vad_ctrl_3 */ - union { - struct { - uint32_t vad_smooth_fall : 8; /* [ 7: 0], r/w, 0x80 */ - uint32_t vad_smooth_rise : 8; /* [15: 8], r/w, 0x10 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_3; - - /* 0x610 : vad_ctrl_4 */ - union { - struct { - uint32_t vad_ek : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_4; - - /* 0x614 : vad_ctrl_5 */ - union { - struct { - uint32_t vad_noise_th : 24; /* [23: 0], r, 0x6600 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } vad_ctrl_5; - - /* 0x618 reserved */ - uint8_t RESERVED0x618[232]; - - /* 0x700 : codec_power1 */ - union { - struct { - uint32_t micbias_pu : 1; /* [ 0], r/w, 0x0 */ - uint32_t micbias_chop_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t micbias_clk_chop_sel : 2; /* [ 3: 2], r/w, 0x2 */ - uint32_t micbias_vsel : 2; /* [ 5: 4], r/w, 0x2 */ - uint32_t padc_ibias_source : 1; /* [ 6], r/w, 0x0 */ - uint32_t padc_power_ten : 1; /* [ 7], r/w, 0x0 */ - uint32_t padc_power_tmux : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t codec_vrda_en : 1; /* [ 12], r/w, 0x0 */ - uint32_t codec_ictrl_vcm : 2; /* [14:13], r/w, 0x2 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t codec_ibias_ctrl : 3; /* [18:16], r/w, 0x4 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_power1; - - /* 0x704 : codec_power2 */ - union { - struct { - uint32_t hpbg_chop_sel : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t hpbg_chop_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t hpbg_pu : 1; /* [ 4], r/w, 0x1 */ - uint32_t hpbg_filt_rsel : 2; /* [ 6: 5], r/w, 0x1 */ - uint32_t hpbg_bypass : 1; /* [ 7], r/w, 0x0 */ - uint32_t hpbg_adjust_fine : 4; /* [11: 8], r/w, 0x1 */ - uint32_t hpbg_adjust_coarse : 4; /* [15:12], r/w, 0x1 */ - uint32_t hpbg_compst_en : 1; /* [ 16], r/w, 0x1 */ - uint32_t ldo25_sstart_en : 1; /* [ 17], r/w, 0x1 */ - uint32_t ldo25_sstart_delay : 2; /* [19:18], r/w, 0x1 */ - uint32_t ldo25_pulldown_sel : 1; /* [ 20], r/w, 0x0 */ - uint32_t ldo25_pulldown : 1; /* [ 21], r/w, 0x0 */ - uint32_t ldo25_pu : 1; /* [ 22], r/w, 0x1 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t ldo25_chop_sel : 3; /* [26:24], r/w, 0x1 */ - uint32_t ldo25_chop_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t ldo25_cc_sel : 3; /* [30:28], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_power2; - - /* 0x708 : codec_dac */ - union { - struct { - uint32_t dacr_lineout_gain : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t dacr_en_lineout : 1; /* [ 3], r/w, 0x0 */ - uint32_t dacr_en_dac : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ - uint32_t dacr_lineout_mode : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t dacr_ictrl_lineout : 2; /* [ 9: 8], r/w, 0x2 */ - uint32_t dacr_sdac_lineout : 1; /* [ 10], r/w, 0x0 */ - uint32_t dacr_sdebug_lineout : 1; /* [ 11], r/w, 0x0 */ - uint32_t dacr_ictrl_dac : 2; /* [13:12], r/w, 0x1 */ - uint32_t dacr_ckb_en : 1; /* [ 14], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t dacl_lineout_gain : 3; /* [18:16], r/w, 0x0 */ - uint32_t dacl_en_lineout : 1; /* [ 19], r/w, 0x0 */ - uint32_t dacl_en_dac : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t dacl_lineout_mode : 1; /* [ 22], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t dacl_ictrl_lineout : 2; /* [25:24], r/w, 0x2 */ - uint32_t dacl_sdac_lineout : 1; /* [ 26], r/w, 0x0 */ - uint32_t dacl_sdebug_lineout : 1; /* [ 27], r/w, 0x0 */ - uint32_t dacl_ictrl_dac : 2; /* [29:28], r/w, 0x1 */ - uint32_t dacl_ckb_en : 1; /* [ 30], r/w, 0x0 */ - uint32_t dac_rg_lo_vref_ramp_dcl_busy : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } codec_dac; - - /* 0x70C : codec_dac_ramp */ - union { - struct { - uint32_t dac_rg_lo_vref_ramp_dcl_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t dac_rg_lineout_vo_pulldown : 1; /* [ 1], r/w, 0x0 */ - uint32_t dac_rg_pu_vref_ramp : 1; /* [ 2], r/w, 0x0 */ - uint32_t dac_rg_pu_lineout : 1; /* [ 3], r/w, 0x0 */ - uint32_t dac_rg_vref_ramp_step_t : 3; /* [ 6: 4], r/w, 0x0 */ - uint32_t dac_rg_sw_vref : 1; /* [ 7], r/w, 0x0 */ - uint32_t dac_rg_vref_ramp_delay : 2; /* [ 9: 8], r/w, 0x1 */ - uint32_t dac_rg_lo_vref_ramp_dvld : 1; /* [ 10], r, 0x0 */ - uint32_t dac_automute_en : 1; /* [ 11], r/w, 0x0 */ - uint32_t dg_dac_mute : 1; /* [ 12], r, 0x0 */ - uint32_t dg_vo_pulldown : 1; /* [ 13], r, 0x0 */ - uint32_t dg_pu_vref_ramp : 1; /* [ 14], r, 0x0 */ - uint32_t dg_vref_ramp_step : 12; /* [26:15], r, 0x0 */ - uint32_t dg_sw_vref : 1; /* [ 27], r, 0x0 */ - uint32_t dg_dacr_en_lineout : 1; /* [ 28], r, 0x0 */ - uint32_t dg_dacl_en_lineout : 1; /* [ 29], r, 0x0 */ - uint32_t dac_rg_vref_ramp_dcl_mode : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } codec_dac_ramp; - - /* 0x710 : codec_adc0 */ - union { - struct { - uint32_t adc0_sdm_lp : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc0_ckb_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc0_reg_resev : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t adc0_pga_rcm_sel : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t adc0_pga_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t adc0_ictrl_mic : 2; /* [13:12], r/w, 0x2 */ - uint32_t adc0_ictrl_adc2 : 2; /* [15:14], r/w, 0x2 */ - uint32_t adc0_ictrl_adc1 : 2; /* [17:16], r/w, 0x2 */ - uint32_t adc0_ictrl_aaf : 2; /* [19:18], r/w, 0x2 */ - uint32_t adc0_en_sdm : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc0_en_pga : 1; /* [ 21], r/w, 0x0 */ - uint32_t adc_dither_sel : 2; /* [23:22], r/w, 0x2 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_adc0; - - /* 0x714 : codec_adc1 */ - union { - struct { - uint32_t adc1_sdm_lp : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc1_ckb_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc1_reg_resev : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t adc1_pga_rcm_sel : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t adc1_pga_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t adc1_ictrl_mic : 2; /* [13:12], r/w, 0x2 */ - uint32_t adc1_ictrl_adc2 : 2; /* [15:14], r/w, 0x2 */ - uint32_t adc1_ictrl_adc1 : 2; /* [17:16], r/w, 0x2 */ - uint32_t adc1_ictrl_aaf : 2; /* [19:18], r/w, 0x2 */ - uint32_t adc1_en_sdm : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc1_en_pga : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_adc1; - - /* 0x718 : codec_adc2 */ - union { - struct { - uint32_t adc2_sdm_lp : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc2_ckb_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc2_reg_resev : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t adc2_pga_rcm_sel : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t adc2_pga_gain : 4; /* [11: 8], r/w, 0x0 */ - uint32_t adc2_ictrl_mic : 2; /* [13:12], r/w, 0x2 */ - uint32_t adc2_ictrl_adc2 : 2; /* [15:14], r/w, 0x2 */ - uint32_t adc2_ictrl_adc1 : 2; /* [17:16], r/w, 0x2 */ - uint32_t adc2_ictrl_aaf : 2; /* [19:18], r/w, 0x2 */ - uint32_t adc2_en_sdm : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc2_en_pga : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } codec_adc2; - - /* 0x71c reserved */ - uint8_t RESERVED0x71c[228]; - - /* 0x800 : padc_ana_cfg1 */ - union { - struct { - uint32_t padc_pga_chop_cksel : 1; /* [ 0], r/w, 0x1 */ - uint32_t padc_pga_chop_freq : 3; /* [ 3: 1], r/w, 0x4 */ - uint32_t padc_pga_chop_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t padc_pga_noisctrl : 2; /* [ 6: 5], r/w, 0x3 */ - uint32_t padc_ictrl_pga_buf : 2; /* [ 8: 7], r/w, 0x1 */ - uint32_t padc_ictrl_pga_ia : 2; /* [10: 9], r/w, 0x1 */ - uint32_t padc_pga_force : 1; /* [ 11], r/w, 0x0 */ - uint32_t padc_pga_autobps_buf : 1; /* [ 12], r/w, 0x0 */ - uint32_t padc_pga_autobps_ia : 1; /* [ 13], r/w, 0x0 */ - uint32_t padc_pga_mode : 2; /* [15:14], r/w, 0x2 */ - uint32_t padc_afevcm_rout : 2; /* [17:16], r/w, 0x0 */ - uint32_t padc_afevcm_sel : 1; /* [ 18], r/w, 0x0 */ - uint32_t padc_ckb_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t padc_sel_edge : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_ana_cfg1; - - /* 0x804 : padc_ana_cfg2 */ - union { - struct { - uint32_t padc_sdm_chop_phas : 1; /* [ 0], r/w, 0x1 */ - uint32_t padc_sdm_chop_freq : 3; /* [ 3: 1], r/w, 0x4 */ - uint32_t padc_sdm_chop_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t padc_dither_order : 1; /* [ 5], r/w, 0x0 */ - uint32_t padc_dither_sel : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t padc_quan_gain : 2; /* [ 9: 8], r/w, 0x1 */ - uint32_t padc_dem_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t padc_nctrl_adc2 : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t padc_nctrl_adc1 : 2; /* [14:13], r/w, 0x0 */ - uint32_t padc_ictrl_adc : 2; /* [16:15], r/w, 0x1 */ - uint32_t padc_reserved : 4; /* [20:17], r/w, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_ana_cfg2; - - /* 0x808 : padc_ana_cmd */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t padc_self_test_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t padc_sdm_lp_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t padc_pga_lp_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t padc_diag_gsw : 2; /* [ 6: 5], r/w, 0x0 */ - uint32_t padc_diag_psw : 2; /* [ 8: 7], r/w, 0x0 */ - uint32_t padc_ictrl_diag : 2; /* [10: 9], r/w, 0x0 */ - uint32_t padc_pga_gain : 3; /* [13:11], r/w, 0x0 */ - uint32_t padc_inv_sig : 1; /* [ 14], r/w, 0x0 */ - uint32_t padc_single_mode : 2; /* [16:15], r/w, 0x0 */ - uint32_t padc_single_cfg : 4; /* [20:17], r/w, 0x0 */ - uint32_t padc_channel_sel : 2; /* [22:21], r/w, 0x0 */ - uint32_t padc_channel_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t padc_conv_delay : 4; /* [27:24], r/w, 0x3 */ - uint32_t padc_conv : 1; /* [ 28], r/w, 0x0 */ - uint32_t padc_en_caldac : 1; /* [ 29], r/w, 0x0 */ - uint32_t padc_sdm_pu : 1; /* [ 30], r/w, 0x0 */ - uint32_t padc_pga_pu : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } padc_ana_cmd; - - /* 0x80C : padc_out_cfg */ - union { - struct { - uint32_t reserved_0_20 : 21; /* [20: 0], rsvd, 0x0 */ - uint32_t padc_valid_4s_val : 1; /* [ 21], r/w, 0x0 */ - uint32_t padc_valid_4s_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t padc_global_chop_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t padc_filter_type : 1; /* [ 24], r/w, 0x0 */ - uint32_t padc_odr : 4; /* [28:25], r/w, 0x3 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_out_cfg; - - /* 0x810 : padc_calib_cmd */ - union { - struct { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t padc_calib_average : 3; /* [18:16], r/w, 0x4 */ - uint32_t padc_calib_discard : 3; /* [21:19], r/w, 0x4 */ - uint32_t padc_calib_run : 1; /* [ 22], r/w, 0x0 */ - uint32_t padc_calib_lvl : 2; /* [24:23], r/w, 0x2 */ - uint32_t padc_calib_gain : 3; /* [27:25], r/w, 0x0 */ - uint32_t padc_calib_mode : 2; /* [29:28], r/w, 0x0 */ - uint32_t padc_calib_start : 1; /* [ 30], w1p, 0x0 */ - uint32_t padc_calib_method : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cmd; - - /* 0x814 : padc_status */ - union { - struct { - uint32_t reserved_0_1 : 2; /* [ 1: 0], rsvd, 0x0 */ - uint32_t padc_soft_rst : 1; /* [ 2], r/w, 0x0 */ - uint32_t padc_filter_rdy : 1; /* [ 3], r, 0x0 */ - uint32_t reserved_4_23 : 20; /* [23: 4], rsvd, 0x0 */ - uint32_t padc_calib_st : 3; /* [26:24], r, 0x0 */ - uint32_t padc_calib_busy : 1; /* [ 27], r, 0x0 */ - uint32_t padc_int : 1; /* [ 28], r, 0x0 */ - uint32_t padc_int_clr : 1; /* [ 29], r/w, 0x0 */ - uint32_t padc_int_set : 1; /* [ 30], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_status; - - /* 0x818 : padc_data */ - union { - struct { - uint32_t padc_raw_data : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_data; - - /* 0x81C : padc_calib_cfg1 */ - union { - struct { - uint32_t padc_oec : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg1; - - /* 0x820 : padc_calib_cfg2 */ - union { - struct { - uint32_t padc_gec : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg2; - - /* 0x824 : padc_calib_cfg3 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg3; - - /* 0x828 : padc_calib_cfg4 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg4; - - /* 0x82C : padc_calib_cfg5 */ - union { - struct { - uint32_t padc_gaincal_ref : 24; /* [23: 0], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg5; - - /* 0x830 : padc_calib_cfg6 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg6; - - /* 0x834 : padc_calib_cfg7 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_calib_cfg7; - - /* 0x838 : padc_oec_w1p */ - union { - struct { - uint32_t padc_wr_oec : 24; /* [23: 0], r/w, 0x0 */ - uint32_t padc_oec_w1p_g0 : 1; /* [ 24], w1p, 0x0 */ - uint32_t padc_oec_w1p_g1 : 1; /* [ 25], w1p, 0x0 */ - uint32_t padc_oec_w1p_g2 : 1; /* [ 26], w1p, 0x0 */ - uint32_t padc_oec_w1p_g3 : 1; /* [ 27], w1p, 0x0 */ - uint32_t padc_oec_w1p_g4 : 1; /* [ 28], w1p, 0x0 */ - uint32_t padc_oec_w1p_g5 : 1; /* [ 29], w1p, 0x0 */ - uint32_t padc_oec_w1p_g6 : 1; /* [ 30], w1p, 0x0 */ - uint32_t padc_oec_w1p_g7 : 1; /* [ 31], w1p, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_w1p; - - /* 0x83C : padc_gec_w1p */ - union { - struct { - uint32_t padc_wr_gec : 24; /* [23: 0], r/w, 0x0 */ - uint32_t padc_gec_w1p_g0 : 1; /* [ 24], w1p, 0x0 */ - uint32_t padc_gec_w1p_g1 : 1; /* [ 25], w1p, 0x0 */ - uint32_t padc_gec_w1p_g2 : 1; /* [ 26], w1p, 0x0 */ - uint32_t padc_gec_w1p_g3 : 1; /* [ 27], w1p, 0x0 */ - uint32_t padc_gec_w1p_g4 : 1; /* [ 28], w1p, 0x0 */ - uint32_t padc_gec_w1p_g5 : 1; /* [ 29], w1p, 0x0 */ - uint32_t padc_gec_w1p_g6 : 1; /* [ 30], w1p, 0x0 */ - uint32_t padc_gec_w1p_g7 : 1; /* [ 31], w1p, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_w1p; - - /* 0x840 : padc_oec_cfg0 */ - union { - struct { - uint32_t padc_oec_g0 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg0; - - /* 0x844 : padc_oec_cfg1 */ - union { - struct { - uint32_t padc_oec_g1 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg1; - - /* 0x848 : padc_oec_cfg2 */ - union { - struct { - uint32_t padc_oec_g2 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg2; - - /* 0x84C : padc_oec_cfg3 */ - union { - struct { - uint32_t padc_oec_g3 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg3; - - /* 0x850 : padc_oec_cfg4 */ - union { - struct { - uint32_t padc_oec_g4 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg4; - - /* 0x854 : padc_oec_cfg5 */ - union { - struct { - uint32_t padc_oec_g5 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg5; - - /* 0x858 : padc_oec_cfg6 */ - union { - struct { - uint32_t padc_oec_g6 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg6; - - /* 0x85C : padc_oec_cfg7 */ - union { - struct { - uint32_t padc_oec_g7 : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_oec_cfg7; - - /* 0x860 : padc_gec_cfg0 */ - union { - struct { - uint32_t padc_gec_g0 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg0; - - /* 0x864 : padc_gec_cfg1 */ - union { - struct { - uint32_t padc_gec_g1 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg1; - - /* 0x868 : padc_gec_cfg2 */ - union { - struct { - uint32_t padc_gec_g2 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg2; - - /* 0x86C : padc_gec_cfg3 */ - union { - struct { - uint32_t padc_gec_g3 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg3; - - /* 0x870 : padc_gec_cfg4 */ - union { - struct { - uint32_t padc_gec_g4 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg4; - - /* 0x874 : padc_gec_cfg5 */ - union { - struct { - uint32_t padc_gec_g5 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg5; - - /* 0x878 : padc_gec_cfg6 */ - union { - struct { - uint32_t padc_gec_g6 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg6; - - /* 0x87C : padc_gec_cfg7 */ - union { - struct { - uint32_t padc_gec_g7 : 24; /* [23: 0], r, 0x800000 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_gec_cfg7; - - /* 0x880 reserved */ - uint8_t RESERVED0x880[128]; - - /* 0x900 : padc_rx_fifo_ctrl */ - union { - struct { - uint32_t padc_rx_fifo_flush : 1; /* [ 0], w1p, 0x0 */ - uint32_t padc_rxo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t padc_rxu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t padc_rxa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t padc_rx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t padc_rx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t padc_rx_ch_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_13 : 5; /* [13: 9], rsvd, 0x0 */ - uint32_t padc_rx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t padc_rx_trg_level : 4; /* [19:16], r/w, 0x3 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t padc_rx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_rx_fifo_ctrl; - - /* 0x904 : padc_rx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t padc_rxo_int : 1; /* [ 1], r, 0x0 */ - uint32_t padc_rxu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t padc_rxa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t padc_rxa_cnt : 4; /* [19:16], r, 0x0 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t padc_rxa : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } padc_rx_fifo_status; - - /* 0x908 : padc_rx_fifo_data */ - union { - struct { - uint32_t padc_rx_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } padc_rx_fifo_data; -}; - -typedef volatile struct audio_reg audio_reg_t; - -#endif /* __AUDIO_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cam_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cam_reg.h deleted file mode 100644 index 1a7c5372eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cam_reg.h +++ /dev/null @@ -1,689 +0,0 @@ -/** - ****************************************************************************** - * @file cam_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CAM_REG_H__ -#define __CAM_REG_H__ - -#include "bl808.h" - -/* 0x0 : dvp2axi_configue */ -#define CAM_DVP2AXI_CONFIGUE_OFFSET (0x0) -#define CAM_REG_DVP_ENABLE CAM_REG_DVP_ENABLE -#define CAM_REG_DVP_ENABLE_POS (0U) -#define CAM_REG_DVP_ENABLE_LEN (1U) -#define CAM_REG_DVP_ENABLE_MSK (((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS) -#define CAM_REG_DVP_ENABLE_UMSK (~(((1U << CAM_REG_DVP_ENABLE_LEN) - 1) << CAM_REG_DVP_ENABLE_POS)) -#define CAM_REG_SW_MODE CAM_REG_SW_MODE -#define CAM_REG_SW_MODE_POS (1U) -#define CAM_REG_SW_MODE_LEN (1U) -#define CAM_REG_SW_MODE_MSK (((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS) -#define CAM_REG_SW_MODE_UMSK (~(((1U << CAM_REG_SW_MODE_LEN) - 1) << CAM_REG_SW_MODE_POS)) -#define CAM_REG_FRAM_VLD_POL CAM_REG_FRAM_VLD_POL -#define CAM_REG_FRAM_VLD_POL_POS (2U) -#define CAM_REG_FRAM_VLD_POL_LEN (1U) -#define CAM_REG_FRAM_VLD_POL_MSK (((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS) -#define CAM_REG_FRAM_VLD_POL_UMSK (~(((1U << CAM_REG_FRAM_VLD_POL_LEN) - 1) << CAM_REG_FRAM_VLD_POL_POS)) -#define CAM_REG_LINE_VLD_POL CAM_REG_LINE_VLD_POL -#define CAM_REG_LINE_VLD_POL_POS (3U) -#define CAM_REG_LINE_VLD_POL_LEN (1U) -#define CAM_REG_LINE_VLD_POL_MSK (((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS) -#define CAM_REG_LINE_VLD_POL_UMSK (~(((1U << CAM_REG_LINE_VLD_POL_LEN) - 1) << CAM_REG_LINE_VLD_POL_POS)) -#define CAM_REG_XLEN CAM_REG_XLEN -#define CAM_REG_XLEN_POS (4U) -#define CAM_REG_XLEN_LEN (3U) -#define CAM_REG_XLEN_MSK (((1U << CAM_REG_XLEN_LEN) - 1) << CAM_REG_XLEN_POS) -#define CAM_REG_XLEN_UMSK (~(((1U << CAM_REG_XLEN_LEN) - 1) << CAM_REG_XLEN_POS)) -#define CAM_REG_DVP_MODE CAM_REG_DVP_MODE -#define CAM_REG_DVP_MODE_POS (8U) -#define CAM_REG_DVP_MODE_LEN (3U) -#define CAM_REG_DVP_MODE_MSK (((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS) -#define CAM_REG_DVP_MODE_UMSK (~(((1U << CAM_REG_DVP_MODE_LEN) - 1) << CAM_REG_DVP_MODE_POS)) -#define CAM_REG_HW_MODE_FWRAP CAM_REG_HW_MODE_FWRAP -#define CAM_REG_HW_MODE_FWRAP_POS (11U) -#define CAM_REG_HW_MODE_FWRAP_LEN (1U) -#define CAM_REG_HW_MODE_FWRAP_MSK (((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS) -#define CAM_REG_HW_MODE_FWRAP_UMSK (~(((1U << CAM_REG_HW_MODE_FWRAP_LEN) - 1) << CAM_REG_HW_MODE_FWRAP_POS)) -#define CAM_REG_DROP_EN CAM_REG_DROP_EN -#define CAM_REG_DROP_EN_POS (12U) -#define CAM_REG_DROP_EN_LEN (1U) -#define CAM_REG_DROP_EN_MSK (((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS) -#define CAM_REG_DROP_EN_UMSK (~(((1U << CAM_REG_DROP_EN_LEN) - 1) << CAM_REG_DROP_EN_POS)) -#define CAM_REG_DROP_EVEN CAM_REG_DROP_EVEN -#define CAM_REG_DROP_EVEN_POS (13U) -#define CAM_REG_DROP_EVEN_LEN (1U) -#define CAM_REG_DROP_EVEN_MSK (((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS) -#define CAM_REG_DROP_EVEN_UMSK (~(((1U << CAM_REG_DROP_EVEN_LEN) - 1) << CAM_REG_DROP_EVEN_POS)) -#define CAM_REG_QOS_SW_MODE CAM_REG_QOS_SW_MODE -#define CAM_REG_QOS_SW_MODE_POS (14U) -#define CAM_REG_QOS_SW_MODE_LEN (1U) -#define CAM_REG_QOS_SW_MODE_MSK (((1U << CAM_REG_QOS_SW_MODE_LEN) - 1) << CAM_REG_QOS_SW_MODE_POS) -#define CAM_REG_QOS_SW_MODE_UMSK (~(((1U << CAM_REG_QOS_SW_MODE_LEN) - 1) << CAM_REG_QOS_SW_MODE_POS)) -#define CAM_REG_QOS_SW CAM_REG_QOS_SW -#define CAM_REG_QOS_SW_POS (15U) -#define CAM_REG_QOS_SW_LEN (1U) -#define CAM_REG_QOS_SW_MSK (((1U << CAM_REG_QOS_SW_LEN) - 1) << CAM_REG_QOS_SW_POS) -#define CAM_REG_QOS_SW_UMSK (~(((1U << CAM_REG_QOS_SW_LEN) - 1) << CAM_REG_QOS_SW_POS)) -#define CAM_REG_DVP_DATA_MODE CAM_REG_DVP_DATA_MODE -#define CAM_REG_DVP_DATA_MODE_POS (16U) -#define CAM_REG_DVP_DATA_MODE_LEN (3U) -#define CAM_REG_DVP_DATA_MODE_MSK (((1U << CAM_REG_DVP_DATA_MODE_LEN) - 1) << CAM_REG_DVP_DATA_MODE_POS) -#define CAM_REG_DVP_DATA_MODE_UMSK (~(((1U << CAM_REG_DVP_DATA_MODE_LEN) - 1) << CAM_REG_DVP_DATA_MODE_POS)) -#define CAM_REG_DVP_DATA_BSEL CAM_REG_DVP_DATA_BSEL -#define CAM_REG_DVP_DATA_BSEL_POS (19U) -#define CAM_REG_DVP_DATA_BSEL_LEN (1U) -#define CAM_REG_DVP_DATA_BSEL_MSK (((1U << CAM_REG_DVP_DATA_BSEL_LEN) - 1) << CAM_REG_DVP_DATA_BSEL_POS) -#define CAM_REG_DVP_DATA_BSEL_UMSK (~(((1U << CAM_REG_DVP_DATA_BSEL_LEN) - 1) << CAM_REG_DVP_DATA_BSEL_POS)) -#define CAM_REG_DVP_PIX_CLK_CG CAM_REG_DVP_PIX_CLK_CG -#define CAM_REG_DVP_PIX_CLK_CG_POS (20U) -#define CAM_REG_DVP_PIX_CLK_CG_LEN (1U) -#define CAM_REG_DVP_PIX_CLK_CG_MSK (((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS) -#define CAM_REG_DVP_PIX_CLK_CG_UMSK (~(((1U << CAM_REG_DVP_PIX_CLK_CG_LEN) - 1) << CAM_REG_DVP_PIX_CLK_CG_POS)) -#define CAM_REG_V_SUBSAMPLE_EN CAM_REG_V_SUBSAMPLE_EN -#define CAM_REG_V_SUBSAMPLE_EN_POS (22U) -#define CAM_REG_V_SUBSAMPLE_EN_LEN (1U) -#define CAM_REG_V_SUBSAMPLE_EN_MSK (((1U << CAM_REG_V_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_V_SUBSAMPLE_EN_POS) -#define CAM_REG_V_SUBSAMPLE_EN_UMSK (~(((1U << CAM_REG_V_SUBSAMPLE_EN_LEN) - 1) << CAM_REG_V_SUBSAMPLE_EN_POS)) -#define CAM_REG_V_SUBSAMPLE_POL CAM_REG_V_SUBSAMPLE_POL -#define CAM_REG_V_SUBSAMPLE_POL_POS (23U) -#define CAM_REG_V_SUBSAMPLE_POL_LEN (1U) -#define CAM_REG_V_SUBSAMPLE_POL_MSK (((1U << CAM_REG_V_SUBSAMPLE_POL_LEN) - 1) << CAM_REG_V_SUBSAMPLE_POL_POS) -#define CAM_REG_V_SUBSAMPLE_POL_UMSK (~(((1U << CAM_REG_V_SUBSAMPLE_POL_LEN) - 1) << CAM_REG_V_SUBSAMPLE_POL_POS)) -#define CAM_REG_DVP_WAIT_CYCLE CAM_REG_DVP_WAIT_CYCLE -#define CAM_REG_DVP_WAIT_CYCLE_POS (24U) -#define CAM_REG_DVP_WAIT_CYCLE_LEN (8U) -#define CAM_REG_DVP_WAIT_CYCLE_MSK (((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS) -#define CAM_REG_DVP_WAIT_CYCLE_UMSK (~(((1U << CAM_REG_DVP_WAIT_CYCLE_LEN) - 1) << CAM_REG_DVP_WAIT_CYCLE_POS)) - -/* 0x4 : dvp2axi_addr_start */ -#define CAM_DVP2AXI_ADDR_START_OFFSET (0x4) -#define CAM_REG_ADDR_START CAM_REG_ADDR_START -#define CAM_REG_ADDR_START_POS (0U) -#define CAM_REG_ADDR_START_LEN (32U) -#define CAM_REG_ADDR_START_MSK (((1U << CAM_REG_ADDR_START_LEN) - 1) << CAM_REG_ADDR_START_POS) -#define CAM_REG_ADDR_START_UMSK (~(((1U << CAM_REG_ADDR_START_LEN) - 1) << CAM_REG_ADDR_START_POS)) - -/* 0x8 : dvp2axi_mem_bcnt */ -#define CAM_DVP2AXI_MEM_BCNT_OFFSET (0x8) -#define CAM_REG_MEM_BURST_CNT CAM_REG_MEM_BURST_CNT -#define CAM_REG_MEM_BURST_CNT_POS (0U) -#define CAM_REG_MEM_BURST_CNT_LEN (32U) -#define CAM_REG_MEM_BURST_CNT_MSK (((1U << CAM_REG_MEM_BURST_CNT_LEN) - 1) << CAM_REG_MEM_BURST_CNT_POS) -#define CAM_REG_MEM_BURST_CNT_UMSK (~(((1U << CAM_REG_MEM_BURST_CNT_LEN) - 1) << CAM_REG_MEM_BURST_CNT_POS)) - -/* 0xC : dvp_status_and_error */ -#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0xC) -#define CAM_REG_FRAME_CNT_TRGR_INT CAM_REG_FRAME_CNT_TRGR_INT -#define CAM_REG_FRAME_CNT_TRGR_INT_POS (0U) -#define CAM_REG_FRAME_CNT_TRGR_INT_LEN (5U) -#define CAM_REG_FRAME_CNT_TRGR_INT_MSK (((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS) -#define CAM_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << CAM_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << CAM_REG_FRAME_CNT_TRGR_INT_POS)) -#define CAM_REG_INT_HCNT_EN CAM_REG_INT_HCNT_EN -#define CAM_REG_INT_HCNT_EN_POS (6U) -#define CAM_REG_INT_HCNT_EN_LEN (1U) -#define CAM_REG_INT_HCNT_EN_MSK (((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS) -#define CAM_REG_INT_HCNT_EN_UMSK (~(((1U << CAM_REG_INT_HCNT_EN_LEN) - 1) << CAM_REG_INT_HCNT_EN_POS)) -#define CAM_REG_INT_VCNT_EN CAM_REG_INT_VCNT_EN -#define CAM_REG_INT_VCNT_EN_POS (7U) -#define CAM_REG_INT_VCNT_EN_LEN (1U) -#define CAM_REG_INT_VCNT_EN_MSK (((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS) -#define CAM_REG_INT_VCNT_EN_UMSK (~(((1U << CAM_REG_INT_VCNT_EN_LEN) - 1) << CAM_REG_INT_VCNT_EN_POS)) -#define CAM_REG_INT_NORMAL_EN CAM_REG_INT_NORMAL_EN -#define CAM_REG_INT_NORMAL_EN_POS (8U) -#define CAM_REG_INT_NORMAL_EN_LEN (1U) -#define CAM_REG_INT_NORMAL_EN_MSK (((1U << CAM_REG_INT_NORMAL_EN_LEN) - 1) << CAM_REG_INT_NORMAL_EN_POS) -#define CAM_REG_INT_NORMAL_EN_UMSK (~(((1U << CAM_REG_INT_NORMAL_EN_LEN) - 1) << CAM_REG_INT_NORMAL_EN_POS)) -#define CAM_REG_INT_MEM_EN CAM_REG_INT_MEM_EN -#define CAM_REG_INT_MEM_EN_POS (9U) -#define CAM_REG_INT_MEM_EN_LEN (1U) -#define CAM_REG_INT_MEM_EN_MSK (((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS) -#define CAM_REG_INT_MEM_EN_UMSK (~(((1U << CAM_REG_INT_MEM_EN_LEN) - 1) << CAM_REG_INT_MEM_EN_POS)) -#define CAM_REG_INT_FRAME_EN CAM_REG_INT_FRAME_EN -#define CAM_REG_INT_FRAME_EN_POS (10U) -#define CAM_REG_INT_FRAME_EN_LEN (1U) -#define CAM_REG_INT_FRAME_EN_MSK (((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS) -#define CAM_REG_INT_FRAME_EN_UMSK (~(((1U << CAM_REG_INT_FRAME_EN_LEN) - 1) << CAM_REG_INT_FRAME_EN_POS)) -#define CAM_REG_INT_FIFO_EN CAM_REG_INT_FIFO_EN -#define CAM_REG_INT_FIFO_EN_POS (11U) -#define CAM_REG_INT_FIFO_EN_LEN (1U) -#define CAM_REG_INT_FIFO_EN_MSK (((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS) -#define CAM_REG_INT_FIFO_EN_UMSK (~(((1U << CAM_REG_INT_FIFO_EN_LEN) - 1) << CAM_REG_INT_FIFO_EN_POS)) -#define CAM_STS_NORMAL_INT CAM_STS_NORMAL_INT -#define CAM_STS_NORMAL_INT_POS (12U) -#define CAM_STS_NORMAL_INT_LEN (1U) -#define CAM_STS_NORMAL_INT_MSK (((1U << CAM_STS_NORMAL_INT_LEN) - 1) << CAM_STS_NORMAL_INT_POS) -#define CAM_STS_NORMAL_INT_UMSK (~(((1U << CAM_STS_NORMAL_INT_LEN) - 1) << CAM_STS_NORMAL_INT_POS)) -#define CAM_STS_MEM_INT CAM_STS_MEM_INT -#define CAM_STS_MEM_INT_POS (13U) -#define CAM_STS_MEM_INT_LEN (1U) -#define CAM_STS_MEM_INT_MSK (((1U << CAM_STS_MEM_INT_LEN) - 1) << CAM_STS_MEM_INT_POS) -#define CAM_STS_MEM_INT_UMSK (~(((1U << CAM_STS_MEM_INT_LEN) - 1) << CAM_STS_MEM_INT_POS)) -#define CAM_STS_FRAME_INT CAM_STS_FRAME_INT -#define CAM_STS_FRAME_INT_POS (14U) -#define CAM_STS_FRAME_INT_LEN (1U) -#define CAM_STS_FRAME_INT_MSK (((1U << CAM_STS_FRAME_INT_LEN) - 1) << CAM_STS_FRAME_INT_POS) -#define CAM_STS_FRAME_INT_UMSK (~(((1U << CAM_STS_FRAME_INT_LEN) - 1) << CAM_STS_FRAME_INT_POS)) -#define CAM_STS_FIFO_INT CAM_STS_FIFO_INT -#define CAM_STS_FIFO_INT_POS (15U) -#define CAM_STS_FIFO_INT_LEN (1U) -#define CAM_STS_FIFO_INT_MSK (((1U << CAM_STS_FIFO_INT_LEN) - 1) << CAM_STS_FIFO_INT_POS) -#define CAM_STS_FIFO_INT_UMSK (~(((1U << CAM_STS_FIFO_INT_LEN) - 1) << CAM_STS_FIFO_INT_POS)) -#define CAM_FRAME_VALID_CNT CAM_FRAME_VALID_CNT -#define CAM_FRAME_VALID_CNT_POS (16U) -#define CAM_FRAME_VALID_CNT_LEN (5U) -#define CAM_FRAME_VALID_CNT_MSK (((1U << CAM_FRAME_VALID_CNT_LEN) - 1) << CAM_FRAME_VALID_CNT_POS) -#define CAM_FRAME_VALID_CNT_UMSK (~(((1U << CAM_FRAME_VALID_CNT_LEN) - 1) << CAM_FRAME_VALID_CNT_POS)) -#define CAM_STS_HCNT_INT CAM_STS_HCNT_INT -#define CAM_STS_HCNT_INT_POS (21U) -#define CAM_STS_HCNT_INT_LEN (1U) -#define CAM_STS_HCNT_INT_MSK (((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS) -#define CAM_STS_HCNT_INT_UMSK (~(((1U << CAM_STS_HCNT_INT_LEN) - 1) << CAM_STS_HCNT_INT_POS)) -#define CAM_STS_VCNT_INT CAM_STS_VCNT_INT -#define CAM_STS_VCNT_INT_POS (22U) -#define CAM_STS_VCNT_INT_LEN (1U) -#define CAM_STS_VCNT_INT_MSK (((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS) -#define CAM_STS_VCNT_INT_UMSK (~(((1U << CAM_STS_VCNT_INT_LEN) - 1) << CAM_STS_VCNT_INT_POS)) -#define CAM_ST_BUS_IDLE CAM_ST_BUS_IDLE -#define CAM_ST_BUS_IDLE_POS (24U) -#define CAM_ST_BUS_IDLE_LEN (1U) -#define CAM_ST_BUS_IDLE_MSK (((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS) -#define CAM_ST_BUS_IDLE_UMSK (~(((1U << CAM_ST_BUS_IDLE_LEN) - 1) << CAM_ST_BUS_IDLE_POS)) -#define CAM_ST_BUS_FUNC CAM_ST_BUS_FUNC -#define CAM_ST_BUS_FUNC_POS (25U) -#define CAM_ST_BUS_FUNC_LEN (1U) -#define CAM_ST_BUS_FUNC_MSK (((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS) -#define CAM_ST_BUS_FUNC_UMSK (~(((1U << CAM_ST_BUS_FUNC_LEN) - 1) << CAM_ST_BUS_FUNC_POS)) -#define CAM_ST_BUS_WAIT CAM_ST_BUS_WAIT -#define CAM_ST_BUS_WAIT_POS (26U) -#define CAM_ST_BUS_WAIT_LEN (1U) -#define CAM_ST_BUS_WAIT_MSK (((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS) -#define CAM_ST_BUS_WAIT_UMSK (~(((1U << CAM_ST_BUS_WAIT_LEN) - 1) << CAM_ST_BUS_WAIT_POS)) -#define CAM_ST_BUS_FLSH CAM_ST_BUS_FLSH -#define CAM_ST_BUS_FLSH_POS (27U) -#define CAM_ST_BUS_FLSH_LEN (1U) -#define CAM_ST_BUS_FLSH_MSK (((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS) -#define CAM_ST_BUS_FLSH_UMSK (~(((1U << CAM_ST_BUS_FLSH_LEN) - 1) << CAM_ST_BUS_FLSH_POS)) -#define CAM_AXI_IDLE CAM_AXI_IDLE -#define CAM_AXI_IDLE_POS (28U) -#define CAM_AXI_IDLE_LEN (1U) -#define CAM_AXI_IDLE_MSK (((1U << CAM_AXI_IDLE_LEN) - 1) << CAM_AXI_IDLE_POS) -#define CAM_AXI_IDLE_UMSK (~(((1U << CAM_AXI_IDLE_LEN) - 1) << CAM_AXI_IDLE_POS)) -#define CAM_ST_DVP_IDLE CAM_ST_DVP_IDLE -#define CAM_ST_DVP_IDLE_POS (29U) -#define CAM_ST_DVP_IDLE_LEN (1U) -#define CAM_ST_DVP_IDLE_MSK (((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS) -#define CAM_ST_DVP_IDLE_UMSK (~(((1U << CAM_ST_DVP_IDLE_LEN) - 1) << CAM_ST_DVP_IDLE_POS)) - -/* 0x10 : dvp2axi_frame_bcnt */ -#define CAM_DVP2AXI_FRAME_BCNT_OFFSET (0x10) -#define CAM_REG_FRAME_BYTE_CNT CAM_REG_FRAME_BYTE_CNT -#define CAM_REG_FRAME_BYTE_CNT_POS (0U) -#define CAM_REG_FRAME_BYTE_CNT_LEN (32U) -#define CAM_REG_FRAME_BYTE_CNT_MSK (((1U << CAM_REG_FRAME_BYTE_CNT_LEN) - 1) << CAM_REG_FRAME_BYTE_CNT_POS) -#define CAM_REG_FRAME_BYTE_CNT_UMSK (~(((1U << CAM_REG_FRAME_BYTE_CNT_LEN) - 1) << CAM_REG_FRAME_BYTE_CNT_POS)) - -/* 0x14 : dvp_frame_fifo_pop */ -#define CAM_DVP_FRAME_FIFO_POP_OFFSET (0x14) -#define CAM_RFIFO_POP CAM_RFIFO_POP -#define CAM_RFIFO_POP_POS (0U) -#define CAM_RFIFO_POP_LEN (1U) -#define CAM_RFIFO_POP_MSK (((1U << CAM_RFIFO_POP_LEN) - 1) << CAM_RFIFO_POP_POS) -#define CAM_RFIFO_POP_UMSK (~(((1U << CAM_RFIFO_POP_LEN) - 1) << CAM_RFIFO_POP_POS)) -#define CAM_REG_INT_NORMAL_CLR CAM_REG_INT_NORMAL_CLR -#define CAM_REG_INT_NORMAL_CLR_POS (4U) -#define CAM_REG_INT_NORMAL_CLR_LEN (1U) -#define CAM_REG_INT_NORMAL_CLR_MSK (((1U << CAM_REG_INT_NORMAL_CLR_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_POS) -#define CAM_REG_INT_NORMAL_CLR_UMSK (~(((1U << CAM_REG_INT_NORMAL_CLR_LEN) - 1) << CAM_REG_INT_NORMAL_CLR_POS)) -#define CAM_REG_INT_MEM_CLR CAM_REG_INT_MEM_CLR -#define CAM_REG_INT_MEM_CLR_POS (5U) -#define CAM_REG_INT_MEM_CLR_LEN (1U) -#define CAM_REG_INT_MEM_CLR_MSK (((1U << CAM_REG_INT_MEM_CLR_LEN) - 1) << CAM_REG_INT_MEM_CLR_POS) -#define CAM_REG_INT_MEM_CLR_UMSK (~(((1U << CAM_REG_INT_MEM_CLR_LEN) - 1) << CAM_REG_INT_MEM_CLR_POS)) -#define CAM_REG_INT_FRAME_CLR CAM_REG_INT_FRAME_CLR -#define CAM_REG_INT_FRAME_CLR_POS (6U) -#define CAM_REG_INT_FRAME_CLR_LEN (1U) -#define CAM_REG_INT_FRAME_CLR_MSK (((1U << CAM_REG_INT_FRAME_CLR_LEN) - 1) << CAM_REG_INT_FRAME_CLR_POS) -#define CAM_REG_INT_FRAME_CLR_UMSK (~(((1U << CAM_REG_INT_FRAME_CLR_LEN) - 1) << CAM_REG_INT_FRAME_CLR_POS)) -#define CAM_REG_INT_FIFO_CLR CAM_REG_INT_FIFO_CLR -#define CAM_REG_INT_FIFO_CLR_POS (7U) -#define CAM_REG_INT_FIFO_CLR_LEN (1U) -#define CAM_REG_INT_FIFO_CLR_MSK (((1U << CAM_REG_INT_FIFO_CLR_LEN) - 1) << CAM_REG_INT_FIFO_CLR_POS) -#define CAM_REG_INT_FIFO_CLR_UMSK (~(((1U << CAM_REG_INT_FIFO_CLR_LEN) - 1) << CAM_REG_INT_FIFO_CLR_POS)) -#define CAM_REG_INT_HCNT_CLR CAM_REG_INT_HCNT_CLR -#define CAM_REG_INT_HCNT_CLR_POS (8U) -#define CAM_REG_INT_HCNT_CLR_LEN (1U) -#define CAM_REG_INT_HCNT_CLR_MSK (((1U << CAM_REG_INT_HCNT_CLR_LEN) - 1) << CAM_REG_INT_HCNT_CLR_POS) -#define CAM_REG_INT_HCNT_CLR_UMSK (~(((1U << CAM_REG_INT_HCNT_CLR_LEN) - 1) << CAM_REG_INT_HCNT_CLR_POS)) -#define CAM_REG_INT_VCNT_CLR CAM_REG_INT_VCNT_CLR -#define CAM_REG_INT_VCNT_CLR_POS (9U) -#define CAM_REG_INT_VCNT_CLR_LEN (1U) -#define CAM_REG_INT_VCNT_CLR_MSK (((1U << CAM_REG_INT_VCNT_CLR_LEN) - 1) << CAM_REG_INT_VCNT_CLR_POS) -#define CAM_REG_INT_VCNT_CLR_UMSK (~(((1U << CAM_REG_INT_VCNT_CLR_LEN) - 1) << CAM_REG_INT_VCNT_CLR_POS)) - -/* 0x18 : dvp2axi_frame_vld */ -#define CAM_DVP2AXI_FRAME_VLD_OFFSET (0x18) -#define CAM_REG_FRAME_N_VLD CAM_REG_FRAME_N_VLD -#define CAM_REG_FRAME_N_VLD_POS (0U) -#define CAM_REG_FRAME_N_VLD_LEN (32U) -#define CAM_REG_FRAME_N_VLD_MSK (((1U << CAM_REG_FRAME_N_VLD_LEN) - 1) << CAM_REG_FRAME_N_VLD_POS) -#define CAM_REG_FRAME_N_VLD_UMSK (~(((1U << CAM_REG_FRAME_N_VLD_LEN) - 1) << CAM_REG_FRAME_N_VLD_POS)) - -/* 0x1C : dvp2axi_frame_period */ -#define CAM_DVP2AXI_FRAME_PERIOD_OFFSET (0x1C) -#define CAM_REG_FRAME_PERIOD CAM_REG_FRAME_PERIOD -#define CAM_REG_FRAME_PERIOD_POS (0U) -#define CAM_REG_FRAME_PERIOD_LEN (5U) -#define CAM_REG_FRAME_PERIOD_MSK (((1U << CAM_REG_FRAME_PERIOD_LEN) - 1) << CAM_REG_FRAME_PERIOD_POS) -#define CAM_REG_FRAME_PERIOD_UMSK (~(((1U << CAM_REG_FRAME_PERIOD_LEN) - 1) << CAM_REG_FRAME_PERIOD_POS)) - -/* 0x20 : dvp2axi_misc */ -#define CAM_DVP2AXI_MISC_OFFSET (0x20) -#define CAM_REG_ALPHA CAM_REG_ALPHA -#define CAM_REG_ALPHA_POS (0U) -#define CAM_REG_ALPHA_LEN (8U) -#define CAM_REG_ALPHA_MSK (((1U << CAM_REG_ALPHA_LEN) - 1) << CAM_REG_ALPHA_POS) -#define CAM_REG_ALPHA_UMSK (~(((1U << CAM_REG_ALPHA_LEN) - 1) << CAM_REG_ALPHA_POS)) -#define CAM_REG_FORMAT_565 CAM_REG_FORMAT_565 -#define CAM_REG_FORMAT_565_POS (8U) -#define CAM_REG_FORMAT_565_LEN (3U) -#define CAM_REG_FORMAT_565_MSK (((1U << CAM_REG_FORMAT_565_LEN) - 1) << CAM_REG_FORMAT_565_POS) -#define CAM_REG_FORMAT_565_UMSK (~(((1U << CAM_REG_FORMAT_565_LEN) - 1) << CAM_REG_FORMAT_565_POS)) - -/* 0x30 : dvp2axi_hsync_crop */ -#define CAM_DVP2AXI_HSYNC_CROP_OFFSET (0x30) -#define CAM_REG_HSYNC_ACT_END CAM_REG_HSYNC_ACT_END -#define CAM_REG_HSYNC_ACT_END_POS (0U) -#define CAM_REG_HSYNC_ACT_END_LEN (16U) -#define CAM_REG_HSYNC_ACT_END_MSK (((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS) -#define CAM_REG_HSYNC_ACT_END_UMSK (~(((1U << CAM_REG_HSYNC_ACT_END_LEN) - 1) << CAM_REG_HSYNC_ACT_END_POS)) -#define CAM_REG_HSYNC_ACT_START CAM_REG_HSYNC_ACT_START -#define CAM_REG_HSYNC_ACT_START_POS (16U) -#define CAM_REG_HSYNC_ACT_START_LEN (16U) -#define CAM_REG_HSYNC_ACT_START_MSK (((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS) -#define CAM_REG_HSYNC_ACT_START_UMSK (~(((1U << CAM_REG_HSYNC_ACT_START_LEN) - 1) << CAM_REG_HSYNC_ACT_START_POS)) - -/* 0x34 : dvp2axi_vsync_crop */ -#define CAM_DVP2AXI_VSYNC_CROP_OFFSET (0x34) -#define CAM_REG_VSYNC_ACT_END CAM_REG_VSYNC_ACT_END -#define CAM_REG_VSYNC_ACT_END_POS (0U) -#define CAM_REG_VSYNC_ACT_END_LEN (16U) -#define CAM_REG_VSYNC_ACT_END_MSK (((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS) -#define CAM_REG_VSYNC_ACT_END_UMSK (~(((1U << CAM_REG_VSYNC_ACT_END_LEN) - 1) << CAM_REG_VSYNC_ACT_END_POS)) -#define CAM_REG_VSYNC_ACT_START CAM_REG_VSYNC_ACT_START -#define CAM_REG_VSYNC_ACT_START_POS (16U) -#define CAM_REG_VSYNC_ACT_START_LEN (16U) -#define CAM_REG_VSYNC_ACT_START_MSK (((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS) -#define CAM_REG_VSYNC_ACT_START_UMSK (~(((1U << CAM_REG_VSYNC_ACT_START_LEN) - 1) << CAM_REG_VSYNC_ACT_START_POS)) - -/* 0x38 : dvp2axi_fram_exm */ -#define CAM_DVP2AXI_FRAM_EXM_OFFSET (0x38) -#define CAM_REG_TOTAL_HCNT CAM_REG_TOTAL_HCNT -#define CAM_REG_TOTAL_HCNT_POS (0U) -#define CAM_REG_TOTAL_HCNT_LEN (16U) -#define CAM_REG_TOTAL_HCNT_MSK (((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS) -#define CAM_REG_TOTAL_HCNT_UMSK (~(((1U << CAM_REG_TOTAL_HCNT_LEN) - 1) << CAM_REG_TOTAL_HCNT_POS)) -#define CAM_REG_TOTAL_VCNT CAM_REG_TOTAL_VCNT -#define CAM_REG_TOTAL_VCNT_POS (16U) -#define CAM_REG_TOTAL_VCNT_LEN (16U) -#define CAM_REG_TOTAL_VCNT_MSK (((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS) -#define CAM_REG_TOTAL_VCNT_UMSK (~(((1U << CAM_REG_TOTAL_VCNT_LEN) - 1) << CAM_REG_TOTAL_VCNT_POS)) - -/* 0x40 : frame_start_addr0 */ -#define CAM_FRAME_START_ADDR0_OFFSET (0x40) -#define CAM_FRAME_START_ADDR_0 CAM_FRAME_START_ADDR_0 -#define CAM_FRAME_START_ADDR_0_POS (0U) -#define CAM_FRAME_START_ADDR_0_LEN (32U) -#define CAM_FRAME_START_ADDR_0_MSK (((1U << CAM_FRAME_START_ADDR_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_POS) -#define CAM_FRAME_START_ADDR_0_UMSK (~(((1U << CAM_FRAME_START_ADDR_0_LEN) - 1) << CAM_FRAME_START_ADDR_0_POS)) - -/* 0x48 : frame_start_addr1 */ -#define CAM_FRAME_START_ADDR1_OFFSET (0x48) -#define CAM_FRAME_START_ADDR_1 CAM_FRAME_START_ADDR_1 -#define CAM_FRAME_START_ADDR_1_POS (0U) -#define CAM_FRAME_START_ADDR_1_LEN (32U) -#define CAM_FRAME_START_ADDR_1_MSK (((1U << CAM_FRAME_START_ADDR_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_POS) -#define CAM_FRAME_START_ADDR_1_UMSK (~(((1U << CAM_FRAME_START_ADDR_1_LEN) - 1) << CAM_FRAME_START_ADDR_1_POS)) - -/* 0x50 : frame_start_addr2 */ -#define CAM_FRAME_START_ADDR2_OFFSET (0x50) -#define CAM_FRAME_START_ADDR_2 CAM_FRAME_START_ADDR_2 -#define CAM_FRAME_START_ADDR_2_POS (0U) -#define CAM_FRAME_START_ADDR_2_LEN (32U) -#define CAM_FRAME_START_ADDR_2_MSK (((1U << CAM_FRAME_START_ADDR_2_LEN) - 1) << CAM_FRAME_START_ADDR_2_POS) -#define CAM_FRAME_START_ADDR_2_UMSK (~(((1U << CAM_FRAME_START_ADDR_2_LEN) - 1) << CAM_FRAME_START_ADDR_2_POS)) - -/* 0x58 : frame_start_addr3 */ -#define CAM_FRAME_START_ADDR3_OFFSET (0x58) -#define CAM_FRAME_START_ADDR_3 CAM_FRAME_START_ADDR_3 -#define CAM_FRAME_START_ADDR_3_POS (0U) -#define CAM_FRAME_START_ADDR_3_LEN (32U) -#define CAM_FRAME_START_ADDR_3_MSK (((1U << CAM_FRAME_START_ADDR_3_LEN) - 1) << CAM_FRAME_START_ADDR_3_POS) -#define CAM_FRAME_START_ADDR_3_UMSK (~(((1U << CAM_FRAME_START_ADDR_3_LEN) - 1) << CAM_FRAME_START_ADDR_3_POS)) - -/* 0x60 : frame_id_sts01 */ -#define CAM_FRAME_ID_STS01_OFFSET (0x60) -#define CAM_FRAME_ID_0 CAM_FRAME_ID_0 -#define CAM_FRAME_ID_0_POS (0U) -#define CAM_FRAME_ID_0_LEN (16U) -#define CAM_FRAME_ID_0_MSK (((1U << CAM_FRAME_ID_0_LEN) - 1) << CAM_FRAME_ID_0_POS) -#define CAM_FRAME_ID_0_UMSK (~(((1U << CAM_FRAME_ID_0_LEN) - 1) << CAM_FRAME_ID_0_POS)) -#define CAM_FRAME_ID_1 CAM_FRAME_ID_1 -#define CAM_FRAME_ID_1_POS (16U) -#define CAM_FRAME_ID_1_LEN (16U) -#define CAM_FRAME_ID_1_MSK (((1U << CAM_FRAME_ID_1_LEN) - 1) << CAM_FRAME_ID_1_POS) -#define CAM_FRAME_ID_1_UMSK (~(((1U << CAM_FRAME_ID_1_LEN) - 1) << CAM_FRAME_ID_1_POS)) - -/* 0x64 : frame_id_sts23 */ -#define CAM_FRAME_ID_STS23_OFFSET (0x64) -#define CAM_FRAME_ID_2 CAM_FRAME_ID_2 -#define CAM_FRAME_ID_2_POS (0U) -#define CAM_FRAME_ID_2_LEN (16U) -#define CAM_FRAME_ID_2_MSK (((1U << CAM_FRAME_ID_2_LEN) - 1) << CAM_FRAME_ID_2_POS) -#define CAM_FRAME_ID_2_UMSK (~(((1U << CAM_FRAME_ID_2_LEN) - 1) << CAM_FRAME_ID_2_POS)) -#define CAM_FRAME_ID_3 CAM_FRAME_ID_3 -#define CAM_FRAME_ID_3_POS (16U) -#define CAM_FRAME_ID_3_LEN (16U) -#define CAM_FRAME_ID_3_MSK (((1U << CAM_FRAME_ID_3_LEN) - 1) << CAM_FRAME_ID_3_POS) -#define CAM_FRAME_ID_3_UMSK (~(((1U << CAM_FRAME_ID_3_LEN) - 1) << CAM_FRAME_ID_3_POS)) - -/* 0xF0 : dvp_debug */ -#define CAM_DVP_DEBUG_OFFSET (0xF0) -#define CAM_REG_DVP_DBG_EN CAM_REG_DVP_DBG_EN -#define CAM_REG_DVP_DBG_EN_POS (0U) -#define CAM_REG_DVP_DBG_EN_LEN (1U) -#define CAM_REG_DVP_DBG_EN_MSK (((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS) -#define CAM_REG_DVP_DBG_EN_UMSK (~(((1U << CAM_REG_DVP_DBG_EN_LEN) - 1) << CAM_REG_DVP_DBG_EN_POS)) -#define CAM_REG_DVP_DBG_SEL CAM_REG_DVP_DBG_SEL -#define CAM_REG_DVP_DBG_SEL_POS (1U) -#define CAM_REG_DVP_DBG_SEL_LEN (3U) -#define CAM_REG_DVP_DBG_SEL_MSK (((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS) -#define CAM_REG_DVP_DBG_SEL_UMSK (~(((1U << CAM_REG_DVP_DBG_SEL_LEN) - 1) << CAM_REG_DVP_DBG_SEL_POS)) -#define CAM_REG_ID_LATCH_LINE CAM_REG_ID_LATCH_LINE -#define CAM_REG_ID_LATCH_LINE_POS (8U) -#define CAM_REG_ID_LATCH_LINE_LEN (4U) -#define CAM_REG_ID_LATCH_LINE_MSK (((1U << CAM_REG_ID_LATCH_LINE_LEN) - 1) << CAM_REG_ID_LATCH_LINE_POS) -#define CAM_REG_ID_LATCH_LINE_UMSK (~(((1U << CAM_REG_ID_LATCH_LINE_LEN) - 1) << CAM_REG_ID_LATCH_LINE_POS)) - -/* 0xFC : dvp_dummy_reg */ -#define CAM_DVP_DUMMY_REG_OFFSET (0xFC) - -struct cam_reg { - /* 0x0 : dvp2axi_configue */ - union { - struct { - uint32_t reg_dvp_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_sw_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_fram_vld_pol : 1; /* [ 2], r/w, 0x1 */ - uint32_t reg_line_vld_pol : 1; /* [ 3], r/w, 0x1 */ - uint32_t reg_xlen : 3; /* [ 6: 4], r/w, 0x3 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t reg_dvp_mode : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reg_hw_mode_fwrap : 1; /* [ 11], r/w, 0x1 */ - uint32_t reg_drop_en : 1; /* [ 12], r/w, 0x0 */ - uint32_t reg_drop_even : 1; /* [ 13], r/w, 0x0 */ - uint32_t reg_qos_sw_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t reg_qos_sw : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_dvp_data_mode : 3; /* [18:16], r/w, 0x0 */ - uint32_t reg_dvp_data_bsel : 1; /* [ 19], r/w, 0x0 */ - uint32_t reg_dvp_pix_clk_cg : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t reg_v_subsample_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t reg_v_subsample_pol : 1; /* [ 23], r/w, 0x0 */ - uint32_t reg_dvp_wait_cycle : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } dvp2axi_configue; - - /* 0x4 : dvp2axi_addr_start */ - union { - struct { - uint32_t reg_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } dvp2axi_addr_start; - - /* 0x8 : dvp2axi_mem_bcnt */ - union { - struct { - uint32_t reg_mem_burst_cnt : 32; /* [31: 0], r/w, 0xc000 */ - } BF; - uint32_t WORD; - } dvp2axi_mem_bcnt; - - /* 0xC : dvp_status_and_error */ - union { - struct { - uint32_t reg_frame_cnt_trgr_int : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ - uint32_t reg_int_hcnt_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_int_vcnt_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reg_int_normal_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_int_mem_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_int_frame_en : 1; /* [ 10], r/w, 0x0 */ - uint32_t reg_int_fifo_en : 1; /* [ 11], r/w, 0x1 */ - uint32_t sts_normal_int : 1; /* [ 12], r, 0x0 */ - uint32_t sts_mem_int : 1; /* [ 13], r, 0x0 */ - uint32_t sts_frame_int : 1; /* [ 14], r, 0x0 */ - uint32_t sts_fifo_int : 1; /* [ 15], r, 0x0 */ - uint32_t frame_valid_cnt : 5; /* [20:16], r, 0x0 */ - uint32_t sts_hcnt_int : 1; /* [ 21], r, 0x0 */ - uint32_t sts_vcnt_int : 1; /* [ 22], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t st_bus_idle : 1; /* [ 24], r, 0x1 */ - uint32_t st_bus_func : 1; /* [ 25], r, 0x0 */ - uint32_t st_bus_wait : 1; /* [ 26], r, 0x0 */ - uint32_t st_bus_flsh : 1; /* [ 27], r, 0x0 */ - uint32_t axi_idle : 1; /* [ 28], r, 0x1 */ - uint32_t st_dvp_idle : 1; /* [ 29], r, 0x1 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_status_and_error; - - /* 0x10 : dvp2axi_frame_bcnt */ - union { - struct { - uint32_t reg_frame_byte_cnt : 32; /* [31: 0], r/w, 0x7e90 */ - } BF; - uint32_t WORD; - } dvp2axi_frame_bcnt; - - /* 0x14 : dvp_frame_fifo_pop */ - union { - struct { - uint32_t rfifo_pop : 1; /* [ 0], w1p, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_int_normal_clr : 1; /* [ 4], w1p, 0x0 */ - uint32_t reg_int_mem_clr : 1; /* [ 5], w1p, 0x0 */ - uint32_t reg_int_frame_clr : 1; /* [ 6], w1p, 0x0 */ - uint32_t reg_int_fifo_clr : 1; /* [ 7], w1p, 0x0 */ - uint32_t reg_int_hcnt_clr : 1; /* [ 8], w1p, 0x0 */ - uint32_t reg_int_vcnt_clr : 1; /* [ 9], w1p, 0x0 */ - uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_frame_fifo_pop; - - /* 0x18 : dvp2axi_frame_vld */ - union { - struct { - uint32_t reg_frame_n_vld : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } dvp2axi_frame_vld; - - /* 0x1C : dvp2axi_frame_period */ - union { - struct { - uint32_t reg_frame_period : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_frame_period; - - /* 0x20 : dvp2axi_misc */ - union { - struct { - uint32_t reg_alpha : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_format_565 : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_misc; - - /* 0x24 reserved */ - uint8_t RESERVED0x24[12]; - - /* 0x30 : dvp2axi_hsync_crop */ - union { - struct { - uint32_t reg_hsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_hsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_hsync_crop; - - /* 0x34 : dvp2axi_vsync_crop */ - union { - struct { - uint32_t reg_vsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_vsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_vsync_crop; - - /* 0x38 : dvp2axi_fram_exm */ - union { - struct { - uint32_t reg_total_hcnt : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_total_vcnt : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2axi_fram_exm; - - /* 0x3c reserved */ - uint8_t RESERVED0x3c[4]; - - /* 0x40 : frame_start_addr0 */ - union { - struct { - uint32_t frame_start_addr_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr0; - - /* 0x44 reserved */ - uint8_t RESERVED0x44[4]; - - /* 0x48 : frame_start_addr1 */ - union { - struct { - uint32_t frame_start_addr_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr1; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : frame_start_addr2 */ - union { - struct { - uint32_t frame_start_addr_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr2; - - /* 0x54 reserved */ - uint8_t RESERVED0x54[4]; - - /* 0x58 : frame_start_addr3 */ - union { - struct { - uint32_t frame_start_addr_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_start_addr3; - - /* 0x5c reserved */ - uint8_t RESERVED0x5c[4]; - - /* 0x60 : frame_id_sts01 */ - union { - struct { - uint32_t frame_id_0 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_1 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_id_sts01; - - /* 0x64 : frame_id_sts23 */ - union { - struct { - uint32_t frame_id_2 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_3 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } frame_id_sts23; - - /* 0x68 reserved */ - uint8_t RESERVED0x68[136]; - - /* 0xF0 : dvp_debug */ - union { - struct { - uint32_t reg_dvp_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_dvp_dbg_sel : 3; /* [ 3: 1], r/w, 0x0 */ - uint32_t reserved_4_7 : 4; /* [ 7: 4], rsvd, 0x0 */ - uint32_t reg_id_latch_line : 4; /* [11: 8], r/w, 0x5 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_debug; - - /* 0xf4 reserved */ - uint8_t RESERVED0xf4[8]; - - /* 0xFC : dvp_dummy_reg */ - union { - struct { - uint32_t RESERVED_31_0 : 32; /* [31: 0], rsvd, 0xf0f0f0f0 */ - } BF; - uint32_t WORD; - } dvp_dummy_reg; -}; - -typedef volatile struct cam_reg cam_reg_t; - -#endif /* __CAM_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/can_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/can_reg.h deleted file mode 100644 index 11516e591c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/can_reg.h +++ /dev/null @@ -1,807 +0,0 @@ -/** - ****************************************************************************** - * @file can_reg.h - * @version V1.0 - * @date 2020-12-29 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CAN_REG_H__ -#define __CAN_REG_H__ - -#include "bl808.h" - -/* 0x0 : op mode:rw reset mode:rw */ -#define CAN_MODE_OFFSET (0x0) -#define CAN_RESET_REQUEST CAN_RESET_REQUEST -#define CAN_RESET_REQUEST_POS (0U) -#define CAN_RESET_REQUEST_LEN (1U) -#define CAN_RESET_REQUEST_MSK (((1U << CAN_RESET_REQUEST_LEN) - 1) << CAN_RESET_REQUEST_POS) -#define CAN_RESET_REQUEST_UMSK (~(((1U << CAN_RESET_REQUEST_LEN) - 1) << CAN_RESET_REQUEST_POS)) -#define CAN_LISTEN_ONLY CAN_LISTEN_ONLY -#define CAN_LISTEN_ONLY_POS (1U) -#define CAN_LISTEN_ONLY_LEN (1U) -#define CAN_LISTEN_ONLY_MSK (((1U << CAN_LISTEN_ONLY_LEN) - 1) << CAN_LISTEN_ONLY_POS) -#define CAN_LISTEN_ONLY_UMSK (~(((1U << CAN_LISTEN_ONLY_LEN) - 1) << CAN_LISTEN_ONLY_POS)) -#define CAN_SELT_TEST CAN_SELT_TEST -#define CAN_SELT_TEST_POS (2U) -#define CAN_SELT_TEST_LEN (1U) -#define CAN_SELT_TEST_MSK (((1U << CAN_SELT_TEST_LEN) - 1) << CAN_SELT_TEST_POS) -#define CAN_SELT_TEST_UMSK (~(((1U << CAN_SELT_TEST_LEN) - 1) << CAN_SELT_TEST_POS)) -#define CAN_ACCEPTANCE_FILTER CAN_ACCEPTANCE_FILTER -#define CAN_ACCEPTANCE_FILTER_POS (3U) -#define CAN_ACCEPTANCE_FILTER_LEN (1U) -#define CAN_ACCEPTANCE_FILTER_MSK (((1U << CAN_ACCEPTANCE_FILTER_LEN) - 1) << CAN_ACCEPTANCE_FILTER_POS) -#define CAN_ACCEPTANCE_FILTER_UMSK (~(((1U << CAN_ACCEPTANCE_FILTER_LEN) - 1) << CAN_ACCEPTANCE_FILTER_POS)) - -/* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ -#define CAN_COMMAND_OFFSET (0x4) -#define CAN_TRANSMIT_REQUEST CAN_TRANSMIT_REQUEST -#define CAN_TRANSMIT_REQUEST_POS (0U) -#define CAN_TRANSMIT_REQUEST_LEN (1U) -#define CAN_TRANSMIT_REQUEST_MSK (((1U << CAN_TRANSMIT_REQUEST_LEN) - 1) << CAN_TRANSMIT_REQUEST_POS) -#define CAN_TRANSMIT_REQUEST_UMSK (~(((1U << CAN_TRANSMIT_REQUEST_LEN) - 1) << CAN_TRANSMIT_REQUEST_POS)) -#define CAN_ABORT_TRANSMISSION CAN_ABORT_TRANSMISSION -#define CAN_ABORT_TRANSMISSION_POS (1U) -#define CAN_ABORT_TRANSMISSION_LEN (1U) -#define CAN_ABORT_TRANSMISSION_MSK (((1U << CAN_ABORT_TRANSMISSION_LEN) - 1) << CAN_ABORT_TRANSMISSION_POS) -#define CAN_ABORT_TRANSMISSION_UMSK (~(((1U << CAN_ABORT_TRANSMISSION_LEN) - 1) << CAN_ABORT_TRANSMISSION_POS)) -#define CAN_RELEASE_RECEIVE_BUFFER CAN_RELEASE_RECEIVE_BUFFER -#define CAN_RELEASE_RECEIVE_BUFFER_POS (2U) -#define CAN_RELEASE_RECEIVE_BUFFER_LEN (1U) -#define CAN_RELEASE_RECEIVE_BUFFER_MSK (((1U << CAN_RELEASE_RECEIVE_BUFFER_LEN) - 1) << CAN_RELEASE_RECEIVE_BUFFER_POS) -#define CAN_RELEASE_RECEIVE_BUFFER_UMSK (~(((1U << CAN_RELEASE_RECEIVE_BUFFER_LEN) - 1) << CAN_RELEASE_RECEIVE_BUFFER_POS)) -#define CAN_CLEAR_DATA_OVERRUN CAN_CLEAR_DATA_OVERRUN -#define CAN_CLEAR_DATA_OVERRUN_POS (3U) -#define CAN_CLEAR_DATA_OVERRUN_LEN (1U) -#define CAN_CLEAR_DATA_OVERRUN_MSK (((1U << CAN_CLEAR_DATA_OVERRUN_LEN) - 1) << CAN_CLEAR_DATA_OVERRUN_POS) -#define CAN_CLEAR_DATA_OVERRUN_UMSK (~(((1U << CAN_CLEAR_DATA_OVERRUN_LEN) - 1) << CAN_CLEAR_DATA_OVERRUN_POS)) -#define CAN_SELF_REQUEST CAN_SELF_REQUEST -#define CAN_SELF_REQUEST_POS (4U) -#define CAN_SELF_REQUEST_LEN (1U) -#define CAN_SELF_REQUEST_MSK (((1U << CAN_SELF_REQUEST_LEN) - 1) << CAN_SELF_REQUEST_POS) -#define CAN_SELF_REQUEST_UMSK (~(((1U << CAN_SELF_REQUEST_LEN) - 1) << CAN_SELF_REQUEST_POS)) - -/* 0x8 : op mode:r reset mode:r */ -#define CAN_STATUS_OFFSET (0x8) -#define CAN_RECEIVE_BUFFER_STS CAN_RECEIVE_BUFFER_STS -#define CAN_RECEIVE_BUFFER_STS_POS (0U) -#define CAN_RECEIVE_BUFFER_STS_LEN (1U) -#define CAN_RECEIVE_BUFFER_STS_MSK (((1U << CAN_RECEIVE_BUFFER_STS_LEN) - 1) << CAN_RECEIVE_BUFFER_STS_POS) -#define CAN_RECEIVE_BUFFER_STS_UMSK (~(((1U << CAN_RECEIVE_BUFFER_STS_LEN) - 1) << CAN_RECEIVE_BUFFER_STS_POS)) -#define CAN_DATA_OVERRUN_STS CAN_DATA_OVERRUN_STS -#define CAN_DATA_OVERRUN_STS_POS (1U) -#define CAN_DATA_OVERRUN_STS_LEN (1U) -#define CAN_DATA_OVERRUN_STS_MSK (((1U << CAN_DATA_OVERRUN_STS_LEN) - 1) << CAN_DATA_OVERRUN_STS_POS) -#define CAN_DATA_OVERRUN_STS_UMSK (~(((1U << CAN_DATA_OVERRUN_STS_LEN) - 1) << CAN_DATA_OVERRUN_STS_POS)) -#define CAN_TRANSMIT_BUFFER_STS CAN_TRANSMIT_BUFFER_STS -#define CAN_TRANSMIT_BUFFER_STS_POS (2U) -#define CAN_TRANSMIT_BUFFER_STS_LEN (1U) -#define CAN_TRANSMIT_BUFFER_STS_MSK (((1U << CAN_TRANSMIT_BUFFER_STS_LEN) - 1) << CAN_TRANSMIT_BUFFER_STS_POS) -#define CAN_TRANSMIT_BUFFER_STS_UMSK (~(((1U << CAN_TRANSMIT_BUFFER_STS_LEN) - 1) << CAN_TRANSMIT_BUFFER_STS_POS)) -#define CAN_TRANSMIT_COMPLETE_STS CAN_TRANSMIT_COMPLETE_STS -#define CAN_TRANSMIT_COMPLETE_STS_POS (3U) -#define CAN_TRANSMIT_COMPLETE_STS_LEN (1U) -#define CAN_TRANSMIT_COMPLETE_STS_MSK (((1U << CAN_TRANSMIT_COMPLETE_STS_LEN) - 1) << CAN_TRANSMIT_COMPLETE_STS_POS) -#define CAN_TRANSMIT_COMPLETE_STS_UMSK (~(((1U << CAN_TRANSMIT_COMPLETE_STS_LEN) - 1) << CAN_TRANSMIT_COMPLETE_STS_POS)) -#define CAN_RECEIVE_STS CAN_RECEIVE_STS -#define CAN_RECEIVE_STS_POS (4U) -#define CAN_RECEIVE_STS_LEN (1U) -#define CAN_RECEIVE_STS_MSK (((1U << CAN_RECEIVE_STS_LEN) - 1) << CAN_RECEIVE_STS_POS) -#define CAN_RECEIVE_STS_UMSK (~(((1U << CAN_RECEIVE_STS_LEN) - 1) << CAN_RECEIVE_STS_POS)) -#define CAN_TRANSMIT_STS CAN_TRANSMIT_STS -#define CAN_TRANSMIT_STS_POS (5U) -#define CAN_TRANSMIT_STS_LEN (1U) -#define CAN_TRANSMIT_STS_MSK (((1U << CAN_TRANSMIT_STS_LEN) - 1) << CAN_TRANSMIT_STS_POS) -#define CAN_TRANSMIT_STS_UMSK (~(((1U << CAN_TRANSMIT_STS_LEN) - 1) << CAN_TRANSMIT_STS_POS)) -#define CAN_ERROR_STS CAN_ERROR_STS -#define CAN_ERROR_STS_POS (6U) -#define CAN_ERROR_STS_LEN (1U) -#define CAN_ERROR_STS_MSK (((1U << CAN_ERROR_STS_LEN) - 1) << CAN_ERROR_STS_POS) -#define CAN_ERROR_STS_UMSK (~(((1U << CAN_ERROR_STS_LEN) - 1) << CAN_ERROR_STS_POS)) -#define CAN_BUS_STS CAN_BUS_STS -#define CAN_BUS_STS_POS (7U) -#define CAN_BUS_STS_LEN (1U) -#define CAN_BUS_STS_MSK (((1U << CAN_BUS_STS_LEN) - 1) << CAN_BUS_STS_POS) -#define CAN_BUS_STS_UMSK (~(((1U << CAN_BUS_STS_LEN) - 1) << CAN_BUS_STS_POS)) - -/* 0xc : op mode:r reset mode:r when be read,all bits are reseted and can_int disappear */ -#define CAN_INTERRUPT_OFFSET (0xc) -#define CAN_RECEIVE_INT CAN_RECEIVE_INT -#define CAN_RECEIVE_INT_POS (0U) -#define CAN_RECEIVE_INT_LEN (1U) -#define CAN_RECEIVE_INT_MSK (((1U << CAN_RECEIVE_INT_LEN) - 1) << CAN_RECEIVE_INT_POS) -#define CAN_RECEIVE_INT_UMSK (~(((1U << CAN_RECEIVE_INT_LEN) - 1) << CAN_RECEIVE_INT_POS)) -#define CAN_TRANSMIT_INT CAN_TRANSMIT_INT -#define CAN_TRANSMIT_INT_POS (1U) -#define CAN_TRANSMIT_INT_LEN (1U) -#define CAN_TRANSMIT_INT_MSK (((1U << CAN_TRANSMIT_INT_LEN) - 1) << CAN_TRANSMIT_INT_POS) -#define CAN_TRANSMIT_INT_UMSK (~(((1U << CAN_TRANSMIT_INT_LEN) - 1) << CAN_TRANSMIT_INT_POS)) -#define CAN_ERROR_INT CAN_ERROR_INT -#define CAN_ERROR_INT_POS (2U) -#define CAN_ERROR_INT_LEN (1U) -#define CAN_ERROR_INT_MSK (((1U << CAN_ERROR_INT_LEN) - 1) << CAN_ERROR_INT_POS) -#define CAN_ERROR_INT_UMSK (~(((1U << CAN_ERROR_INT_LEN) - 1) << CAN_ERROR_INT_POS)) -#define CAN_DATA_OVERRUN_INT CAN_DATA_OVERRUN_INT -#define CAN_DATA_OVERRUN_INT_POS (3U) -#define CAN_DATA_OVERRUN_INT_LEN (1U) -#define CAN_DATA_OVERRUN_INT_MSK (((1U << CAN_DATA_OVERRUN_INT_LEN) - 1) << CAN_DATA_OVERRUN_INT_POS) -#define CAN_DATA_OVERRUN_INT_UMSK (~(((1U << CAN_DATA_OVERRUN_INT_LEN) - 1) << CAN_DATA_OVERRUN_INT_POS)) -#define CAN_ERROR_PASSIVE_INT CAN_ERROR_PASSIVE_INT -#define CAN_ERROR_PASSIVE_INT_POS (5U) -#define CAN_ERROR_PASSIVE_INT_LEN (1U) -#define CAN_ERROR_PASSIVE_INT_MSK (((1U << CAN_ERROR_PASSIVE_INT_LEN) - 1) << CAN_ERROR_PASSIVE_INT_POS) -#define CAN_ERROR_PASSIVE_INT_UMSK (~(((1U << CAN_ERROR_PASSIVE_INT_LEN) - 1) << CAN_ERROR_PASSIVE_INT_POS)) -#define CAN_ARB_LOST_INT CAN_ARB_LOST_INT -#define CAN_ARB_LOST_INT_POS (6U) -#define CAN_ARB_LOST_INT_LEN (1U) -#define CAN_ARB_LOST_INT_MSK (((1U << CAN_ARB_LOST_INT_LEN) - 1) << CAN_ARB_LOST_INT_POS) -#define CAN_ARB_LOST_INT_UMSK (~(((1U << CAN_ARB_LOST_INT_LEN) - 1) << CAN_ARB_LOST_INT_POS)) -#define CAN_BUS_ERROR_INT CAN_BUS_ERROR_INT -#define CAN_BUS_ERROR_INT_POS (7U) -#define CAN_BUS_ERROR_INT_LEN (1U) -#define CAN_BUS_ERROR_INT_MSK (((1U << CAN_BUS_ERROR_INT_LEN) - 1) << CAN_BUS_ERROR_INT_POS) -#define CAN_BUS_ERROR_INT_UMSK (~(((1U << CAN_BUS_ERROR_INT_LEN) - 1) << CAN_BUS_ERROR_INT_POS)) - -/* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and can_int disappear */ -#define CAN_INTERRUPT_ENABLE_OFFSET (0x10) -#define CAN_RECEIVE_INT_EN CAN_RECEIVE_INT_EN -#define CAN_RECEIVE_INT_EN_POS (0U) -#define CAN_RECEIVE_INT_EN_LEN (1U) -#define CAN_RECEIVE_INT_EN_MSK (((1U << CAN_RECEIVE_INT_EN_LEN) - 1) << CAN_RECEIVE_INT_EN_POS) -#define CAN_RECEIVE_INT_EN_UMSK (~(((1U << CAN_RECEIVE_INT_EN_LEN) - 1) << CAN_RECEIVE_INT_EN_POS)) -#define CAN_TRANSMIT_INT_EN CAN_TRANSMIT_INT_EN -#define CAN_TRANSMIT_INT_EN_POS (1U) -#define CAN_TRANSMIT_INT_EN_LEN (1U) -#define CAN_TRANSMIT_INT_EN_MSK (((1U << CAN_TRANSMIT_INT_EN_LEN) - 1) << CAN_TRANSMIT_INT_EN_POS) -#define CAN_TRANSMIT_INT_EN_UMSK (~(((1U << CAN_TRANSMIT_INT_EN_LEN) - 1) << CAN_TRANSMIT_INT_EN_POS)) -#define CAN_ERROR_INT_EN CAN_ERROR_INT_EN -#define CAN_ERROR_INT_EN_POS (2U) -#define CAN_ERROR_INT_EN_LEN (1U) -#define CAN_ERROR_INT_EN_MSK (((1U << CAN_ERROR_INT_EN_LEN) - 1) << CAN_ERROR_INT_EN_POS) -#define CAN_ERROR_INT_EN_UMSK (~(((1U << CAN_ERROR_INT_EN_LEN) - 1) << CAN_ERROR_INT_EN_POS)) -#define CAN_DATA_OVERRUN_INT_EN CAN_DATA_OVERRUN_INT_EN -#define CAN_DATA_OVERRUN_INT_EN_POS (3U) -#define CAN_DATA_OVERRUN_INT_EN_LEN (1U) -#define CAN_DATA_OVERRUN_INT_EN_MSK (((1U << CAN_DATA_OVERRUN_INT_EN_LEN) - 1) << CAN_DATA_OVERRUN_INT_EN_POS) -#define CAN_DATA_OVERRUN_INT_EN_UMSK (~(((1U << CAN_DATA_OVERRUN_INT_EN_LEN) - 1) << CAN_DATA_OVERRUN_INT_EN_POS)) -#define CAN_ERROR_PASSIVE_INT_EN CAN_ERROR_PASSIVE_INT_EN -#define CAN_ERROR_PASSIVE_INT_EN_POS (5U) -#define CAN_ERROR_PASSIVE_INT_EN_LEN (1U) -#define CAN_ERROR_PASSIVE_INT_EN_MSK (((1U << CAN_ERROR_PASSIVE_INT_EN_LEN) - 1) << CAN_ERROR_PASSIVE_INT_EN_POS) -#define CAN_ERROR_PASSIVE_INT_EN_UMSK (~(((1U << CAN_ERROR_PASSIVE_INT_EN_LEN) - 1) << CAN_ERROR_PASSIVE_INT_EN_POS)) -#define CAN_ARB_LOST_INT_EN CAN_ARB_LOST_INT_EN -#define CAN_ARB_LOST_INT_EN_POS (6U) -#define CAN_ARB_LOST_INT_EN_LEN (1U) -#define CAN_ARB_LOST_INT_EN_MSK (((1U << CAN_ARB_LOST_INT_EN_LEN) - 1) << CAN_ARB_LOST_INT_EN_POS) -#define CAN_ARB_LOST_INT_EN_UMSK (~(((1U << CAN_ARB_LOST_INT_EN_LEN) - 1) << CAN_ARB_LOST_INT_EN_POS)) -#define CAN_BUS_ERROR_INT_EN CAN_BUS_ERROR_INT_EN -#define CAN_BUS_ERROR_INT_EN_POS (7U) -#define CAN_BUS_ERROR_INT_EN_LEN (1U) -#define CAN_BUS_ERROR_INT_EN_MSK (((1U << CAN_BUS_ERROR_INT_EN_LEN) - 1) << CAN_BUS_ERROR_INT_EN_POS) -#define CAN_BUS_ERROR_INT_EN_UMSK (~(((1U << CAN_BUS_ERROR_INT_EN_LEN) - 1) << CAN_BUS_ERROR_INT_EN_POS)) - -/* 0x18 : op mode:r reset mode:rw */ -#define CAN_BUS_TIMING_0_OFFSET (0x18) -#define CAN_BAUD_RATE_PRESCALER CAN_BAUD_RATE_PRESCALER -#define CAN_BAUD_RATE_PRESCALER_POS (0U) -#define CAN_BAUD_RATE_PRESCALER_LEN (6U) -#define CAN_BAUD_RATE_PRESCALER_MSK (((1U << CAN_BAUD_RATE_PRESCALER_LEN) - 1) << CAN_BAUD_RATE_PRESCALER_POS) -#define CAN_BAUD_RATE_PRESCALER_UMSK (~(((1U << CAN_BAUD_RATE_PRESCALER_LEN) - 1) << CAN_BAUD_RATE_PRESCALER_POS)) -#define CAN_SYNC_JUMP_WIDTH CAN_SYNC_JUMP_WIDTH -#define CAN_SYNC_JUMP_WIDTH_POS (6U) -#define CAN_SYNC_JUMP_WIDTH_LEN (2U) -#define CAN_SYNC_JUMP_WIDTH_MSK (((1U << CAN_SYNC_JUMP_WIDTH_LEN) - 1) << CAN_SYNC_JUMP_WIDTH_POS) -#define CAN_SYNC_JUMP_WIDTH_UMSK (~(((1U << CAN_SYNC_JUMP_WIDTH_LEN) - 1) << CAN_SYNC_JUMP_WIDTH_POS)) - -/* 0x1c : op mode:r reset mode:rw */ -#define CAN_BUS_TIMING_1_OFFSET (0x1c) -#define CAN_TIME_SEGMENT_1 CAN_TIME_SEGMENT_1 -#define CAN_TIME_SEGMENT_1_POS (0U) -#define CAN_TIME_SEGMENT_1_LEN (4U) -#define CAN_TIME_SEGMENT_1_MSK (((1U << CAN_TIME_SEGMENT_1_LEN) - 1) << CAN_TIME_SEGMENT_1_POS) -#define CAN_TIME_SEGMENT_1_UMSK (~(((1U << CAN_TIME_SEGMENT_1_LEN) - 1) << CAN_TIME_SEGMENT_1_POS)) -#define CAN_TIME_SEGMENT_2 CAN_TIME_SEGMENT_2 -#define CAN_TIME_SEGMENT_2_POS (4U) -#define CAN_TIME_SEGMENT_2_LEN (3U) -#define CAN_TIME_SEGMENT_2_MSK (((1U << CAN_TIME_SEGMENT_2_LEN) - 1) << CAN_TIME_SEGMENT_2_POS) -#define CAN_TIME_SEGMENT_2_UMSK (~(((1U << CAN_TIME_SEGMENT_2_LEN) - 1) << CAN_TIME_SEGMENT_2_POS)) -#define CAN_SAMPLING CAN_SAMPLING -#define CAN_SAMPLING_POS (7U) -#define CAN_SAMPLING_LEN (1U) -#define CAN_SAMPLING_MSK (((1U << CAN_SAMPLING_LEN) - 1) << CAN_SAMPLING_POS) -#define CAN_SAMPLING_UMSK (~(((1U << CAN_SAMPLING_LEN) - 1) << CAN_SAMPLING_POS)) - -/* 0x2c : op mode:r reset mode:r */ -#define CAN_ARB_LOST_CAPTURE_OFFSET (0x2c) -#define CAN_ALC4_0 CAN_ALC4_0 -#define CAN_ALC4_0_POS (0U) -#define CAN_ALC4_0_LEN (5U) -#define CAN_ALC4_0_MSK (((1U << CAN_ALC4_0_LEN) - 1) << CAN_ALC4_0_POS) -#define CAN_ALC4_0_UMSK (~(((1U << CAN_ALC4_0_LEN) - 1) << CAN_ALC4_0_POS)) - -/* 0x30 : op mode:r reset mode:r */ -#define CAN_ERROR_CODE_CAPTURE_OFFSET (0x30) -#define CAN_SEGMENT4_0 CAN_SEGMENT4_0 -#define CAN_SEGMENT4_0_POS (0U) -#define CAN_SEGMENT4_0_LEN (5U) -#define CAN_SEGMENT4_0_MSK (((1U << CAN_SEGMENT4_0_LEN) - 1) << CAN_SEGMENT4_0_POS) -#define CAN_SEGMENT4_0_UMSK (~(((1U << CAN_SEGMENT4_0_LEN) - 1) << CAN_SEGMENT4_0_POS)) -#define CAN_DIR CAN_DIR -#define CAN_DIR_POS (5U) -#define CAN_DIR_LEN (1U) -#define CAN_DIR_MSK (((1U << CAN_DIR_LEN) - 1) << CAN_DIR_POS) -#define CAN_DIR_UMSK (~(((1U << CAN_DIR_LEN) - 1) << CAN_DIR_POS)) -#define CAN_ERR_CODE CAN_ERR_CODE -#define CAN_ERR_CODE_POS (6U) -#define CAN_ERR_CODE_LEN (2U) -#define CAN_ERR_CODE_MSK (((1U << CAN_ERR_CODE_LEN) - 1) << CAN_ERR_CODE_POS) -#define CAN_ERR_CODE_UMSK (~(((1U << CAN_ERR_CODE_LEN) - 1) << CAN_ERR_CODE_POS)) - -/* 0x34 : op mode:r reset mode:rw */ -#define CAN_ERROR_WARNING_LIMIT_OFFSET (0x34) -#define CAN_ERR_WARNING_LIMIT CAN_ERR_WARNING_LIMIT -#define CAN_ERR_WARNING_LIMIT_POS (0U) -#define CAN_ERR_WARNING_LIMIT_LEN (8U) -#define CAN_ERR_WARNING_LIMIT_MSK (((1U << CAN_ERR_WARNING_LIMIT_LEN) - 1) << CAN_ERR_WARNING_LIMIT_POS) -#define CAN_ERR_WARNING_LIMIT_UMSK (~(((1U << CAN_ERR_WARNING_LIMIT_LEN) - 1) << CAN_ERR_WARNING_LIMIT_POS)) - -/* 0x38 : op mode:r reset mode:rw */ -#define CAN_RX_ERR_COUNT_OFFSET (0x38) -#define CAN_RX_ERR_CNT CAN_RX_ERR_CNT -#define CAN_RX_ERR_CNT_POS (0U) -#define CAN_RX_ERR_CNT_LEN (8U) -#define CAN_RX_ERR_CNT_MSK (((1U << CAN_RX_ERR_CNT_LEN) - 1) << CAN_RX_ERR_CNT_POS) -#define CAN_RX_ERR_CNT_UMSK (~(((1U << CAN_RX_ERR_CNT_LEN) - 1) << CAN_RX_ERR_CNT_POS)) - -/* 0x3c : op mode:r reset mode:rw */ -#define CAN_TX_ERR_COUNT_OFFSET (0x3c) -#define CAN_TX_ERR_CNT CAN_TX_ERR_CNT -#define CAN_TX_ERR_CNT_POS (0U) -#define CAN_TX_ERR_CNT_LEN (8U) -#define CAN_TX_ERR_CNT_MSK (((1U << CAN_TX_ERR_CNT_LEN) - 1) << CAN_TX_ERR_CNT_POS) -#define CAN_TX_ERR_CNT_UMSK (~(((1U << CAN_TX_ERR_CNT_LEN) - 1) << CAN_TX_ERR_CNT_POS)) - -/* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_OFFSET (0x40) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS (0U) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN (8U) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_MSK (((1U << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS) -#define CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_UMSK (~(((1U << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << CAN_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS)) - -/* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_OFFSET (0x44) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1 CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1 -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS (0U) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN (8U) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_MSK (((1U << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS) -#define CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_UMSK (~(((1U << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << CAN_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS)) - -/* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_OFFSET (0x48) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2 CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2 -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS (0U) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN (8U) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_MSK (((1U << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS) -#define CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_UMSK (~(((1U << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << CAN_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS)) - -/* 0x74 : op mode:r reset mode:r */ -#define CAN_RX_MESSAGE_COUNT_OFFSET (0x74) -#define CAN_RX_MESSAGE_CNT CAN_RX_MESSAGE_CNT -#define CAN_RX_MESSAGE_CNT_POS (0U) -#define CAN_RX_MESSAGE_CNT_LEN (5U) -#define CAN_RX_MESSAGE_CNT_MSK (((1U << CAN_RX_MESSAGE_CNT_LEN) - 1) << CAN_RX_MESSAGE_CNT_POS) -#define CAN_RX_MESSAGE_CNT_UMSK (~(((1U << CAN_RX_MESSAGE_CNT_LEN) - 1) << CAN_RX_MESSAGE_CNT_POS)) - -/* 0x7c : op mode:rw reset mode:rw can_mode and cbp can be write in reset mode only */ -#define CAN_CLOCK_DIVIDER_OFFSET (0x7c) -#define CAN_CD CAN_CD -#define CAN_CD_POS (0U) -#define CAN_CD_LEN (3U) -#define CAN_CD_MSK (((1U << CAN_CD_LEN) - 1) << CAN_CD_POS) -#define CAN_CD_UMSK (~(((1U << CAN_CD_LEN) - 1) << CAN_CD_POS)) -#define CAN_CLOCKOFF CAN_CLOCKOFF -#define CAN_CLOCKOFF_POS (3U) -#define CAN_CLOCKOFF_LEN (1U) -#define CAN_CLOCKOFF_MSK (((1U << CAN_CLOCKOFF_LEN) - 1) << CAN_CLOCKOFF_POS) -#define CAN_CLOCKOFF_UMSK (~(((1U << CAN_CLOCKOFF_LEN) - 1) << CAN_CLOCKOFF_POS)) -#define CAN_READONLY CAN_READONLY -#define CAN_READONLY_POS (4U) -#define CAN_READONLY_LEN (1U) -#define CAN_READONLY_MSK (((1U << CAN_READONLY_LEN) - 1) << CAN_READONLY_POS) -#define CAN_READONLY_UMSK (~(((1U << CAN_READONLY_LEN) - 1) << CAN_READONLY_POS)) -#define CAN_RXINTEN CAN_RXINTEN -#define CAN_RXINTEN_POS (5U) -#define CAN_RXINTEN_LEN (1U) -#define CAN_RXINTEN_MSK (((1U << CAN_RXINTEN_LEN) - 1) << CAN_RXINTEN_POS) -#define CAN_RXINTEN_UMSK (~(((1U << CAN_RXINTEN_LEN) - 1) << CAN_RXINTEN_POS)) -#define CAN_CBP CAN_CBP -#define CAN_CBP_POS (6U) -#define CAN_CBP_LEN (1U) -#define CAN_CBP_MSK (((1U << CAN_CBP_LEN) - 1) << CAN_CBP_POS) -#define CAN_CBP_UMSK (~(((1U << CAN_CBP_LEN) - 1) << CAN_CBP_POS)) -#define CAN_MODE CAN_MODE -#define CAN_MODE_POS (7U) -#define CAN_MODE_LEN (1U) -#define CAN_MODE_MSK (((1U << CAN_MODE_LEN) - 1) << CAN_MODE_POS) -#define CAN_MODE_UMSK (~(((1U << CAN_MODE_LEN) - 1) << CAN_MODE_POS)) - -/* 0x40 : Frame information */ -#define CAN_INFORMATION_OFFSET (0x40) -#define CAN_INF_DLC CAN_INF_DLC -#define CAN_INF_DLC_POS (0U) -#define CAN_INF_DLC_LEN (4U) -#define CAN_INF_DLC_MSK (((1U << CAN_INF_DLC_LEN) - 1) << CAN_INF_DLC_POS) -#define CAN_INF_DLC_UMSK (~(((1U << CAN_INF_DLC_LEN) - 1) << CAN_INF_DLC_POS)) -#define CAN_INF_RTR CAN_INF_RTR -#define CAN_INF_RTR_POS (6U) -#define CAN_INF_RTR_LEN (1U) -#define CAN_INF_RTR_MSK (((1U << CAN_INF_RTR_LEN) - 1) << CAN_INF_RTR_POS) -#define CAN_INF_RTR_UMSK (~(((1U << CAN_INF_RTR_LEN) - 1) << CAN_INF_RTR_POS)) -#define CAN_INF_FF CAN_INF_FF -#define CAN_INF_FF_POS (7U) -#define CAN_INF_FF_LEN (1U) -#define CAN_INF_FF_MSK (((1U << CAN_INF_FF_LEN) - 1) << CAN_INF_FF_POS) -#define CAN_INF_FF_UMSK (~(((1U << CAN_INF_FF_LEN) - 1) << CAN_INF_FF_POS)) - -/* 0x44 : Identifier 1, ID28~21 */ -#define CAN_IDENTIFIER_1_OFFSET (0x44) - -/* 0x48 : Identifier 2, ID20~13, SFF Only use ID20~18 */ -#define CAN_IDENTIFIER_2_OFFSET (0x48) - -/* 0x4C : Identifier 3, ID12~5, only for EFF */ -#define CAN_IDENTIFIER_3_OFFSET (0x4C) - -/* 0x50 : Identifier 4, ID4~0, only for EFF */ -#define CAN_IDENTIFIER_4_OFFSET (0x50) - -/* 0x4C : Standard Format Data 1 buffer */ -#define CAN_SFF_DATA_1_OFFSET (0x4C) - -/* 0x50 : Standard Format Data 2 buffer */ -#define CAN_SFF_DATA_2_OFFSET (0x50) - -/* 0x54 : Standard Format Data 3 buffer */ -#define CAN_SFF_DATA_3_OFFSET (0x54) - -/* 0x58 : Standard Format Data 4 buffer */ -#define CAN_SFF_DATA_4_OFFSET (0x58) - -/* 0x5C : Standard Format Data 5 buffer */ -#define CAN_SFF_DATA_5_OFFSET (0x5C) - -/* 0x60 : Standard Format Data 6 buffer */ -#define CAN_SFF_DATA_6_OFFSET (0x60) - -/* 0x64 : Standard Format Data 7 buffer */ -#define CAN_SFF_DATA_7_OFFSET (0x64) - -/* 0x68 : Standard Format Data 8 buffer */ -#define CAN_SFF_DATA_8_OFFSET (0x68) - -/* 0x54 : Extended Format Data 1 buffer */ -#define CAN_EFF_DATA_1_OFFSET (0x54) - -/* 0x58 : Extended Format Data 2 buffer */ -#define CAN_EFF_DATA_2_OFFSET (0x58) - -/* 0x5C : Extended Format Data 3 buffer */ -#define CAN_EFF_DATA_3_OFFSET (0x5C) - -/* 0x60 : Extended Format Data 4 buffer */ -#define CAN_EFF_DATA_4_OFFSET (0x60) - -/* 0x64 : Extended Format Data 5 buffer */ -#define CAN_EFF_DATA_5_OFFSET (0x64) - -/* 0x68 : Extended Format Data 6 buffer */ -#define CAN_EFF_DATA_6_OFFSET (0x68) - -/* 0x6C : Extended Format Data 7 buffer */ -#define CAN_EFF_DATA_7_OFFSET (0x6C) - -/* 0x70 : Extended Format Data 8 buffer */ -#define CAN_EFF_DATA_8_OFFSET (0x70) - -/* 0x70 : Extended Format Data 8 buffer */ -#define CAN_EFF_DATA_8_OFFSET (0x70) - -/* 0x40 : Filter Acceptance 0 */ -#define CAN_FILTER_ACCEPTANCE_0_OFFSET (0x40) - -/* 0x44 : Filter Acceptance 1 */ -#define CAN_FILTER_ACCEPTANCE_1_OFFSET (0x44) - -/* 0x48 : Filter Acceptance 2 */ -#define CAN_FILTER_ACCEPTANCE_2_OFFSET (0x48) - -/* 0x4C : Filter Acceptance 3 */ -#define CAN_FILTER_ACCEPTANCE_3_OFFSET (0x4C) - -/* 0x50 : Filter Mask 0 */ -#define CAN_FILTER_Mask_0_OFFSET (0x50) - -/* 0x54 : Filter Mask 1 */ -#define CAN_FILTER_Mask_1_OFFSET (0x54) - -/* 0x58 : Filter Mask 2 */ -#define CAN_FILTER_Mask_2_OFFSET (0x58) - -/* 0x5C : Filter Mask 3 */ -#define CAN_FILTER_Mask_3_OFFSET (0x5C) - -/* 0x4C : Extended Format, Tx information 5, ID4~0 */ -#define CAN_IDENTIFIER_4_OFFSET (0x50) - -struct can_reg { - /* 0x0 : op mode:rw reset mode:rw */ - union { - struct { - uint32_t reset_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t listen_only : 1; /* [ 1], w1c, 0x0 */ - uint32_t selt_test : 1; /* [ 2], w1c, 0x0 */ - uint32_t acceptance_filter : 1; /* [ 3], w1c, 0x0 */ - uint32_t rsvd_7_4 : 4; /* [ 7: 4], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mode; - - /* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ - union { - struct { - uint32_t transmit_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t abort_transmission : 1; /* [ 1], w1c, 0x0 */ - uint32_t release_receive_buffer : 1; /* [ 2], w1c, 0x0 */ - uint32_t clear_data_overrun : 1; /* [ 3], w1c, 0x0 */ - uint32_t self_request : 1; /* [ 4], w1c, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } command; - - /* 0x8 : op mode:r reset mode:r */ - union { - struct { - uint32_t receive_buffer_sts : 1; /* [ 0], r, 0x0 */ - uint32_t data_overrun_sts : 1; /* [ 1], r, 0x0 */ - uint32_t transmit_buffer_sts : 1; /* [ 2], r, 0x0 */ - uint32_t transmit_complete_sts : 1; /* [ 3], r, 0x0 */ - uint32_t receive_sts : 1; /* [ 4], r, 0x0 */ - uint32_t transmit_sts : 1; /* [ 5], r, 0x0 */ - uint32_t error_sts : 1; /* [ 6], r, 0x0 */ - uint32_t bus_sts : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } status; - - /* 0xc : op mode:r reset mode:r when be read,all bits are reseted and can_int disappear */ - union { - struct { - uint32_t receive_int : 1; /* [ 0], r, 0x0 */ - uint32_t transmit_int : 1; /* [ 1], r, 0x0 */ - uint32_t error_int : 1; /* [ 2], r, 0x0 */ - uint32_t data_overrun_int : 1; /* [ 3], r, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int : 1; /* [ 5], r, 0x0 */ - uint32_t arb_lost_int : 1; /* [ 6], r, 0x0 */ - uint32_t bus_error_int : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt; - - /* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and can_int disappear */ - union { - struct { - uint32_t receive_int_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t transmit_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t error_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t data_overrun_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t arb_lost_int_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t bus_error_int_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt_enable; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[4]; - - /* 0x18 : op mode:r reset mode:rw */ - union { - struct { - uint32_t baud_rate_prescaler_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t baud_rate_prescaler_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t baud_rate_prescaler_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t baud_rate_prescaler_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t baud_rate_prescaler_4 : 1; /* [ 4], r/w, 0x0 */ - uint32_t baud_rate_prescaler_5 : 1; /* [ 5], r/w, 0x0 */ - uint32_t sync_jump_width_0 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sync_jump_width_1 : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_0; - - /* 0x1c : op mode:r reset mode:rw */ - union { - struct { - uint32_t time_segment_1_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t time_segment_1_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t time_segment_1_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t time_segment_1_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t time_segment_2_0 : 1; /* [ 4], r/w, 0x0 */ - uint32_t time_segment_2_1 : 1; /* [ 5], r/w, 0x0 */ - uint32_t time_segment_2_2 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sampling : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_1; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[12]; - - /* 0x2c : op mode:r reset mode:r */ - union { - struct { - uint32_t ALC4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } arb_lost_capture; - - /* 0x30 : op mode:r reset mode:r */ - union { - struct { - uint32_t segment4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t dir : 1; /* [ 5], r, 0x0 */ - uint32_t err_code : 2; /* [ 7: 6], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_code_capture; - - /* 0x34 : op mode:r reset mode:rw */ - union { - struct { - uint32_t err_warning_limit : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_warning_limit; - - /* 0x38 : op mode:r reset mode:rw */ - union { - struct { - uint32_t rx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_err_count; - - /* 0x3c : op mode:r reset mode:rw */ - union { - struct { - uint32_t tx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_err_count; - - /* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ - union { - struct { - uint32_t txrx_frm_info_or_acceptance_code0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_frm_info_or_acceptance_code0; - - /* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ - union { - struct { - uint32_t txrx_id1_or_acceptance_code1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id1_or_acceptance_code1; - - /* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ - union { - struct { - uint32_t txrx_id2_or_acceptance_code2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id2_or_acceptance_code2; - - /* 0x4c : op mode:w -> tx_data1_s or tx_id3 - r -> rx_data1_s or rx_id3 - reset mode:rw -> acceptance_code3 */ - union { - struct { - uint32_t txrx_data1_s_or_txrx_id3_e_or_acceptance_code3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data1_s_or_txrx_id3_e_or_acceptance_code3; - - /* 0x50 : op mode:w -> tx_data2_s or tx_id4 - r -> rx_data2_s or rx_id4 -reset mode:rw -> acceptance_mask0 */ - union { - struct { - uint32_t txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0; - - /* 0x54 : op mode:w -> tx_data3_s or tx_data1_e - r -> rx_data3_s or rx_data1_e -reset mode:rw -> acceptance_mask1 */ - union { - struct { - uint32_t txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1; - - /* 0x58 : op mode:w -> tx_data4_s or tx_data2_e - r -> rx_data4_s or rx_data2_e -reset mode:rw -> acceptance_mask2 */ - union { - struct { - uint32_t txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2; - - /* 0x5c : op mode:w -> tx_data5_s or tx_data3_e - r -> rx_data5_s or rx_data3_e -reset mode:rw -> acceptance_mask3 */ - union { - struct { - uint32_t txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3; - - /* 0x60 : op mode:w -> tx_data6_s or tx_data4_e - r -> rx_data6_s or rx_data4_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data6_s_or_txrx_data4_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data6_s_or_txrx_data4_e; - - /* 0x64 : op mode:w -> tx_data7_s or tx_data5_e - r -> rx_data7_s or rx_data5_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_s_or_txrx_data5_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_s_or_txrx_data5_e; - - /* 0x68 : op mode:w -> tx_data8_s or tx_data6_e - r -> rx_data8_s or rx_data6_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_s_or_txrx_data6_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_s_or_txrx_data6_e; - - /* 0x6c : op mode:w -> tx_data7_e - r -> rx_data7_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_e; - - /* 0x70 : op mode:w -> tx_data8_e - r -> rx_data8_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_e; - - /* 0x74 : op mode:r reset mode:r */ - union { - struct { - uint32_t rx_message_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_message_count; - - /* 0x78 reserved */ - uint8_t RESERVED0x78[4]; - - /* 0x7c : op mode:rw reset mode:rw can_mode and cbp can be write in reset mode only */ - union { - struct { - uint32_t cd : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t clockoff : 1; /* [ 3], r/w, 0x0 */ - uint32_t readonly : 1; /* [ 4], r, 0x0 */ - uint32_t rxinten : 1; /* [ 5], r/w, 0x0 */ - uint32_t cbp : 1; /* [ 6], r/w, 0x0 */ - uint32_t can_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } clock_divider; -}; - -typedef volatile struct can_reg can_reg_t; - -#endif /* __CAN_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cnn_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cnn_reg.h deleted file mode 100644 index 1f4c662611..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cnn_reg.h +++ /dev/null @@ -1,241 +0,0 @@ -/** - ****************************************************************************** - * @file cnn_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CNN_REG_H__ -#define __CNN_REG_H__ - -#include "bl808.h" - -/* 0x00 : bl_cnn_cfg */ -#define CNN_BL_CNN_CFG_OFFSET (0x00) -#define CNN_REG_INT_CLR CNN_REG_INT_CLR -#define CNN_REG_INT_CLR_POS (24U) -#define CNN_REG_INT_CLR_LEN (1U) -#define CNN_REG_INT_CLR_MSK (((1U << CNN_REG_INT_CLR_LEN) - 1) << CNN_REG_INT_CLR_POS) -#define CNN_REG_INT_CLR_UMSK (~(((1U << CNN_REG_INT_CLR_LEN) - 1) << CNN_REG_INT_CLR_POS)) -#define CNN_INT CNN_INT -#define CNN_INT_POS (25U) -#define CNN_INT_LEN (1U) -#define CNN_INT_MSK (((1U << CNN_INT_LEN) - 1) << CNN_INT_POS) -#define CNN_INT_UMSK (~(((1U << CNN_INT_LEN) - 1) << CNN_INT_POS)) -#define CNN_REG_BUS_RST CNN_REG_BUS_RST -#define CNN_REG_BUS_RST_POS (27U) -#define CNN_REG_BUS_RST_LEN (1U) -#define CNN_REG_BUS_RST_MSK (((1U << CNN_REG_BUS_RST_LEN) - 1) << CNN_REG_BUS_RST_POS) -#define CNN_REG_BUS_RST_UMSK (~(((1U << CNN_REG_BUS_RST_LEN) - 1) << CNN_REG_BUS_RST_POS)) -#define CNN_AXI_IDLE CNN_AXI_IDLE -#define CNN_AXI_IDLE_POS (31U) -#define CNN_AXI_IDLE_LEN (1U) -#define CNN_AXI_IDLE_MSK (((1U << CNN_AXI_IDLE_LEN) - 1) << CNN_AXI_IDLE_POS) -#define CNN_AXI_IDLE_UMSK (~(((1U << CNN_AXI_IDLE_LEN) - 1) << CNN_AXI_IDLE_POS)) - -/* 0x04 : bl_cnn_weig_addr */ -#define CNN_BL_CNN_WEIG_ADDR_OFFSET (0x04) -#define CNN_WEIG_ADDR_BASE CNN_WEIG_ADDR_BASE -#define CNN_WEIG_ADDR_BASE_POS (0U) -#define CNN_WEIG_ADDR_BASE_LEN (32U) -#define CNN_WEIG_ADDR_BASE_MSK (((1U << CNN_WEIG_ADDR_BASE_LEN) - 1) << CNN_WEIG_ADDR_BASE_POS) -#define CNN_WEIG_ADDR_BASE_UMSK (~(((1U << CNN_WEIG_ADDR_BASE_LEN) - 1) << CNN_WEIG_ADDR_BASE_POS)) - -/* 0x08 : bl_cnn_img_addr */ -#define CNN_BL_CNN_IMG_ADDR_OFFSET (0x08) -#define CNN_IMG_ADDR_BASE CNN_IMG_ADDR_BASE -#define CNN_IMG_ADDR_BASE_POS (0U) -#define CNN_IMG_ADDR_BASE_LEN (32U) -#define CNN_IMG_ADDR_BASE_MSK (((1U << CNN_IMG_ADDR_BASE_LEN) - 1) << CNN_IMG_ADDR_BASE_POS) -#define CNN_IMG_ADDR_BASE_UMSK (~(((1U << CNN_IMG_ADDR_BASE_LEN) - 1) << CNN_IMG_ADDR_BASE_POS)) - -/* 0x0C : bl_cnn_bias_addr */ -#define CNN_BL_CNN_BIAS_ADDR_OFFSET (0x0C) -#define CNN_BIAS_ADDR_BASE CNN_BIAS_ADDR_BASE -#define CNN_BIAS_ADDR_BASE_POS (0U) -#define CNN_BIAS_ADDR_BASE_LEN (32U) -#define CNN_BIAS_ADDR_BASE_MSK (((1U << CNN_BIAS_ADDR_BASE_LEN) - 1) << CNN_BIAS_ADDR_BASE_POS) -#define CNN_BIAS_ADDR_BASE_UMSK (~(((1U << CNN_BIAS_ADDR_BASE_LEN) - 1) << CNN_BIAS_ADDR_BASE_POS)) - -/* 0x10 : bl_cnn_inst_addr */ -#define CNN_BL_CNN_INST_ADDR_OFFSET (0x10) -#define CNN_INST_ADDR_BASE CNN_INST_ADDR_BASE -#define CNN_INST_ADDR_BASE_POS (0U) -#define CNN_INST_ADDR_BASE_LEN (32U) -#define CNN_INST_ADDR_BASE_MSK (((1U << CNN_INST_ADDR_BASE_LEN) - 1) << CNN_INST_ADDR_BASE_POS) -#define CNN_INST_ADDR_BASE_UMSK (~(((1U << CNN_INST_ADDR_BASE_LEN) - 1) << CNN_INST_ADDR_BASE_POS)) - -/* 0x14 : bl_cnn_out_addr */ -#define CNN_BL_CNN_OUT_ADDR_OFFSET (0x14) -#define CNN_OUT_ADDR_BASE CNN_OUT_ADDR_BASE -#define CNN_OUT_ADDR_BASE_POS (0U) -#define CNN_OUT_ADDR_BASE_LEN (32U) -#define CNN_OUT_ADDR_BASE_MSK (((1U << CNN_OUT_ADDR_BASE_LEN) - 1) << CNN_OUT_ADDR_BASE_POS) -#define CNN_OUT_ADDR_BASE_UMSK (~(((1U << CNN_OUT_ADDR_BASE_LEN) - 1) << CNN_OUT_ADDR_BASE_POS)) - -/* 0x18 : bl_cnn_num1 */ -#define CNN_BL_CNN_NUM1_OFFSET (0x18) -#define CNN_WEIG_NUM CNN_WEIG_NUM -#define CNN_WEIG_NUM_POS (0U) -#define CNN_WEIG_NUM_LEN (16U) -#define CNN_WEIG_NUM_MSK (((1U << CNN_WEIG_NUM_LEN) - 1) << CNN_WEIG_NUM_POS) -#define CNN_WEIG_NUM_UMSK (~(((1U << CNN_WEIG_NUM_LEN) - 1) << CNN_WEIG_NUM_POS)) -#define CNN_IMG_NUM CNN_IMG_NUM -#define CNN_IMG_NUM_POS (16U) -#define CNN_IMG_NUM_LEN (16U) -#define CNN_IMG_NUM_MSK (((1U << CNN_IMG_NUM_LEN) - 1) << CNN_IMG_NUM_POS) -#define CNN_IMG_NUM_UMSK (~(((1U << CNN_IMG_NUM_LEN) - 1) << CNN_IMG_NUM_POS)) - -/* 0x1C : bl_cnn_num2 */ -#define CNN_BL_CNN_NUM2_OFFSET (0x1C) -#define CNN_BIAS_NUM CNN_BIAS_NUM -#define CNN_BIAS_NUM_POS (0U) -#define CNN_BIAS_NUM_LEN (16U) -#define CNN_BIAS_NUM_MSK (((1U << CNN_BIAS_NUM_LEN) - 1) << CNN_BIAS_NUM_POS) -#define CNN_BIAS_NUM_UMSK (~(((1U << CNN_BIAS_NUM_LEN) - 1) << CNN_BIAS_NUM_POS)) -#define CNN_OUT_NUM CNN_OUT_NUM -#define CNN_OUT_NUM_POS (16U) -#define CNN_OUT_NUM_LEN (16U) -#define CNN_OUT_NUM_MSK (((1U << CNN_OUT_NUM_LEN) - 1) << CNN_OUT_NUM_POS) -#define CNN_OUT_NUM_UMSK (~(((1U << CNN_OUT_NUM_LEN) - 1) << CNN_OUT_NUM_POS)) - -/* 0x20 : bl_cnn_num3 */ -#define CNN_BL_CNN_NUM3_OFFSET (0x20) -#define CNN_INST_NUM CNN_INST_NUM -#define CNN_INST_NUM_POS (0U) -#define CNN_INST_NUM_LEN (16U) -#define CNN_INST_NUM_MSK (((1U << CNN_INST_NUM_LEN) - 1) << CNN_INST_NUM_POS) -#define CNN_INST_NUM_UMSK (~(((1U << CNN_INST_NUM_LEN) - 1) << CNN_INST_NUM_POS)) -#define CNN_START CNN_START -#define CNN_START_POS (16U) -#define CNN_START_LEN (1U) -#define CNN_START_MSK (((1U << CNN_START_LEN) - 1) << CNN_START_POS) -#define CNN_START_UMSK (~(((1U << CNN_START_LEN) - 1) << CNN_START_POS)) -#define CNN_RST CNN_RST -#define CNN_RST_POS (17U) -#define CNN_RST_LEN (1U) -#define CNN_RST_MSK (((1U << CNN_RST_LEN) - 1) << CNN_RST_POS) -#define CNN_RST_UMSK (~(((1U << CNN_RST_LEN) - 1) << CNN_RST_POS)) -#define CNN_INPUT_CHANNEL CNN_INPUT_CHANNEL -#define CNN_INPUT_CHANNEL_POS (18U) -#define CNN_INPUT_CHANNEL_LEN (2U) -#define CNN_INPUT_CHANNEL_MSK (((1U << CNN_INPUT_CHANNEL_LEN) - 1) << CNN_INPUT_CHANNEL_POS) -#define CNN_INPUT_CHANNEL_UMSK (~(((1U << CNN_INPUT_CHANNEL_LEN) - 1) << CNN_INPUT_CHANNEL_POS)) - -struct cnn_reg { - /* 0x00 : bl_cnn_cfg */ - union { - struct { - uint32_t reserved_0_23 : 24; /* [23: 0], rsvd, 0x0 */ - uint32_t reg_int_clr : 1; /* [ 24], w1p, 0x0 */ - uint32_t cnn_int : 1; /* [ 25], r, 0x0 */ - uint32_t reserved_26 : 1; /* [ 26], rsvd, 0x0 */ - uint32_t reg_bus_rst : 1; /* [ 27], w1p, 0x0 */ - uint32_t reserved_28_30 : 3; /* [30:28], rsvd, 0x0 */ - uint32_t axi_idle : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_cfg; - - /* 0x04 : bl_cnn_weig_addr */ - union { - struct { - uint32_t WEIG_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_weig_addr; - - /* 0x08 : bl_cnn_img_addr */ - union { - struct { - uint32_t IMG_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_img_addr; - - /* 0x0C : bl_cnn_bias_addr */ - union { - struct { - uint32_t BIAS_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_bias_addr; - - /* 0x10 : bl_cnn_inst_addr */ - union { - struct { - uint32_t INST_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_inst_addr; - - /* 0x14 : bl_cnn_out_addr */ - union { - struct { - uint32_t OUT_addr_base : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_out_addr; - - /* 0x18 : bl_cnn_num1 */ - union { - struct { - uint32_t WEIG_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t IMG_num : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_num1; - - /* 0x1C : bl_cnn_num2 */ - union { - struct { - uint32_t BIAS_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t OUT_num : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_num2; - - /* 0x20 : bl_cnn_num3 */ - union { - struct { - uint32_t INST_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t CNN_start : 1; /* [ 16], r/w, 0x0 */ - uint32_t CNN_rst : 1; /* [ 17], r/w, 0x0 */ - uint32_t input_channel : 2; /* [19:18], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bl_cnn_num3; -}; - -typedef volatile struct cnn_reg cnn_reg_t; - -#endif /* __CNN_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/csi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/csi_reg.h deleted file mode 100644 index 52df1ae765..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/csi_reg.h +++ /dev/null @@ -1,528 +0,0 @@ -/** - ****************************************************************************** - * @file csi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __CSI_REG_H__ -#define __CSI_REG_H__ - -#include "bl808.h" - -/* 0x0 : mipi_config */ -#define CSI_MIPI_CONFIG_OFFSET (0x0) -#define CSI_CR_CSI_EN CSI_CR_CSI_EN -#define CSI_CR_CSI_EN_POS (0U) -#define CSI_CR_CSI_EN_LEN (1U) -#define CSI_CR_CSI_EN_MSK (((1U << CSI_CR_CSI_EN_LEN) - 1) << CSI_CR_CSI_EN_POS) -#define CSI_CR_CSI_EN_UMSK (~(((1U << CSI_CR_CSI_EN_LEN) - 1) << CSI_CR_CSI_EN_POS)) -#define CSI_CR_LANE_NUM CSI_CR_LANE_NUM -#define CSI_CR_LANE_NUM_POS (1U) -#define CSI_CR_LANE_NUM_LEN (1U) -#define CSI_CR_LANE_NUM_MSK (((1U << CSI_CR_LANE_NUM_LEN) - 1) << CSI_CR_LANE_NUM_POS) -#define CSI_CR_LANE_NUM_UMSK (~(((1U << CSI_CR_LANE_NUM_LEN) - 1) << CSI_CR_LANE_NUM_POS)) -#define CSI_CR_LANE_INV CSI_CR_LANE_INV -#define CSI_CR_LANE_INV_POS (3U) -#define CSI_CR_LANE_INV_LEN (1U) -#define CSI_CR_LANE_INV_MSK (((1U << CSI_CR_LANE_INV_LEN) - 1) << CSI_CR_LANE_INV_POS) -#define CSI_CR_LANE_INV_UMSK (~(((1U << CSI_CR_LANE_INV_LEN) - 1) << CSI_CR_LANE_INV_POS)) -#define CSI_CR_DATA_BIT_INV CSI_CR_DATA_BIT_INV -#define CSI_CR_DATA_BIT_INV_POS (4U) -#define CSI_CR_DATA_BIT_INV_LEN (1U) -#define CSI_CR_DATA_BIT_INV_MSK (((1U << CSI_CR_DATA_BIT_INV_LEN) - 1) << CSI_CR_DATA_BIT_INV_POS) -#define CSI_CR_DATA_BIT_INV_UMSK (~(((1U << CSI_CR_DATA_BIT_INV_LEN) - 1) << CSI_CR_DATA_BIT_INV_POS)) -#define CSI_CR_SYNC_SP_EN CSI_CR_SYNC_SP_EN -#define CSI_CR_SYNC_SP_EN_POS (5U) -#define CSI_CR_SYNC_SP_EN_LEN (1U) -#define CSI_CR_SYNC_SP_EN_MSK (((1U << CSI_CR_SYNC_SP_EN_LEN) - 1) << CSI_CR_SYNC_SP_EN_POS) -#define CSI_CR_SYNC_SP_EN_UMSK (~(((1U << CSI_CR_SYNC_SP_EN_LEN) - 1) << CSI_CR_SYNC_SP_EN_POS)) -#define CSI_CR_UNPACK_EN CSI_CR_UNPACK_EN -#define CSI_CR_UNPACK_EN_POS (6U) -#define CSI_CR_UNPACK_EN_LEN (1U) -#define CSI_CR_UNPACK_EN_MSK (((1U << CSI_CR_UNPACK_EN_LEN) - 1) << CSI_CR_UNPACK_EN_POS) -#define CSI_CR_UNPACK_EN_UMSK (~(((1U << CSI_CR_UNPACK_EN_LEN) - 1) << CSI_CR_UNPACK_EN_POS)) -#define CSI_CR_VC_DVP0 CSI_CR_VC_DVP0 -#define CSI_CR_VC_DVP0_POS (12U) -#define CSI_CR_VC_DVP0_LEN (2U) -#define CSI_CR_VC_DVP0_MSK (((1U << CSI_CR_VC_DVP0_LEN) - 1) << CSI_CR_VC_DVP0_POS) -#define CSI_CR_VC_DVP0_UMSK (~(((1U << CSI_CR_VC_DVP0_LEN) - 1) << CSI_CR_VC_DVP0_POS)) -#define CSI_CR_VC_DVP1 CSI_CR_VC_DVP1 -#define CSI_CR_VC_DVP1_POS (14U) -#define CSI_CR_VC_DVP1_LEN (2U) -#define CSI_CR_VC_DVP1_MSK (((1U << CSI_CR_VC_DVP1_LEN) - 1) << CSI_CR_VC_DVP1_POS) -#define CSI_CR_VC_DVP1_UMSK (~(((1U << CSI_CR_VC_DVP1_LEN) - 1) << CSI_CR_VC_DVP1_POS)) - -/* 0x10 : csi_int_status */ -#define CSI_INT_STATUS_OFFSET (0x10) -#define CSI_INT_STATUS CSI_INT_STATUS -#define CSI_INT_STATUS_POS (0U) -#define CSI_INT_STATUS_LEN (6U) -#define CSI_INT_STATUS_MSK (((1U << CSI_INT_STATUS_LEN) - 1) << CSI_INT_STATUS_POS) -#define CSI_INT_STATUS_UMSK (~(((1U << CSI_INT_STATUS_LEN) - 1) << CSI_INT_STATUS_POS)) - -/* 0x14 : csi_int_mask */ -#define CSI_INT_MASK_OFFSET (0x14) -#define CSI_INT_MASK CSI_INT_MASK -#define CSI_INT_MASK_POS (0U) -#define CSI_INT_MASK_LEN (6U) -#define CSI_INT_MASK_MSK (((1U << CSI_INT_MASK_LEN) - 1) << CSI_INT_MASK_POS) -#define CSI_INT_MASK_UMSK (~(((1U << CSI_INT_MASK_LEN) - 1) << CSI_INT_MASK_POS)) - -/* 0x18 : csi_int_clear */ -#define CSI_INT_CLEAR_OFFSET (0x18) -#define CSI_INT_CLEAR CSI_INT_CLEAR -#define CSI_INT_CLEAR_POS (0U) -#define CSI_INT_CLEAR_LEN (6U) -#define CSI_INT_CLEAR_MSK (((1U << CSI_INT_CLEAR_LEN) - 1) << CSI_INT_CLEAR_POS) -#define CSI_INT_CLEAR_UMSK (~(((1U << CSI_INT_CLEAR_LEN) - 1) << CSI_INT_CLEAR_POS)) - -/* 0x1C : csi_int_enable */ -#define CSI_INT_ENABLE_OFFSET (0x1C) -#define CSI_INT_ENABLE CSI_INT_ENABLE -#define CSI_INT_ENABLE_POS (0U) -#define CSI_INT_ENABLE_LEN (6U) -#define CSI_INT_ENABLE_MSK (((1U << CSI_INT_ENABLE_LEN) - 1) << CSI_INT_ENABLE_POS) -#define CSI_INT_ENABLE_UMSK (~(((1U << CSI_INT_ENABLE_LEN) - 1) << CSI_INT_ENABLE_POS)) - -/* 0x20 : gnr_buf_status */ -#define CSI_GNR_BUF_STATUS_OFFSET (0x20) -#define CSI_ST_GNR_FIFO_CNT CSI_ST_GNR_FIFO_CNT -#define CSI_ST_GNR_FIFO_CNT_POS (0U) -#define CSI_ST_GNR_FIFO_CNT_LEN (4U) -#define CSI_ST_GNR_FIFO_CNT_MSK (((1U << CSI_ST_GNR_FIFO_CNT_LEN) - 1) << CSI_ST_GNR_FIFO_CNT_POS) -#define CSI_ST_GNR_FIFO_CNT_UMSK (~(((1U << CSI_ST_GNR_FIFO_CNT_LEN) - 1) << CSI_ST_GNR_FIFO_CNT_POS)) - -/* 0x24 : gnr_buf_rdata */ -#define CSI_GNR_BUF_RDATA_OFFSET (0x24) -#define CSI_GNR_BUF_RDATA CSI_GNR_BUF_RDATA -#define CSI_GNR_BUF_RDATA_POS (0U) -#define CSI_GNR_BUF_RDATA_LEN (32U) -#define CSI_GNR_BUF_RDATA_MSK (((1U << CSI_GNR_BUF_RDATA_LEN) - 1) << CSI_GNR_BUF_RDATA_POS) -#define CSI_GNR_BUF_RDATA_UMSK (~(((1U << CSI_GNR_BUF_RDATA_LEN) - 1) << CSI_GNR_BUF_RDATA_POS)) - -/* 0x80 : dphy_config_0 */ -#define CSI_DPHY_CONFIG_0_OFFSET (0x80) -#define CSI_DL0_ENABLE CSI_DL0_ENABLE -#define CSI_DL0_ENABLE_POS (0U) -#define CSI_DL0_ENABLE_LEN (1U) -#define CSI_DL0_ENABLE_MSK (((1U << CSI_DL0_ENABLE_LEN) - 1) << CSI_DL0_ENABLE_POS) -#define CSI_DL0_ENABLE_UMSK (~(((1U << CSI_DL0_ENABLE_LEN) - 1) << CSI_DL0_ENABLE_POS)) -#define CSI_DL1_ENABLE CSI_DL1_ENABLE -#define CSI_DL1_ENABLE_POS (1U) -#define CSI_DL1_ENABLE_LEN (1U) -#define CSI_DL1_ENABLE_MSK (((1U << CSI_DL1_ENABLE_LEN) - 1) << CSI_DL1_ENABLE_POS) -#define CSI_DL1_ENABLE_UMSK (~(((1U << CSI_DL1_ENABLE_LEN) - 1) << CSI_DL1_ENABLE_POS)) -#define CSI_CL_ENABLE CSI_CL_ENABLE -#define CSI_CL_ENABLE_POS (2U) -#define CSI_CL_ENABLE_LEN (1U) -#define CSI_CL_ENABLE_MSK (((1U << CSI_CL_ENABLE_LEN) - 1) << CSI_CL_ENABLE_POS) -#define CSI_CL_ENABLE_UMSK (~(((1U << CSI_CL_ENABLE_LEN) - 1) << CSI_CL_ENABLE_POS)) -#define CSI_DL0_STOPSTATE CSI_DL0_STOPSTATE -#define CSI_DL0_STOPSTATE_POS (4U) -#define CSI_DL0_STOPSTATE_LEN (1U) -#define CSI_DL0_STOPSTATE_MSK (((1U << CSI_DL0_STOPSTATE_LEN) - 1) << CSI_DL0_STOPSTATE_POS) -#define CSI_DL0_STOPSTATE_UMSK (~(((1U << CSI_DL0_STOPSTATE_LEN) - 1) << CSI_DL0_STOPSTATE_POS)) -#define CSI_DL1_STOPSTATE CSI_DL1_STOPSTATE -#define CSI_DL1_STOPSTATE_POS (5U) -#define CSI_DL1_STOPSTATE_LEN (1U) -#define CSI_DL1_STOPSTATE_MSK (((1U << CSI_DL1_STOPSTATE_LEN) - 1) << CSI_DL1_STOPSTATE_POS) -#define CSI_DL1_STOPSTATE_UMSK (~(((1U << CSI_DL1_STOPSTATE_LEN) - 1) << CSI_DL1_STOPSTATE_POS)) -#define CSI_CL_STOPSTATE CSI_CL_STOPSTATE -#define CSI_CL_STOPSTATE_POS (6U) -#define CSI_CL_STOPSTATE_LEN (1U) -#define CSI_CL_STOPSTATE_MSK (((1U << CSI_CL_STOPSTATE_LEN) - 1) << CSI_CL_STOPSTATE_POS) -#define CSI_CL_STOPSTATE_UMSK (~(((1U << CSI_CL_STOPSTATE_LEN) - 1) << CSI_CL_STOPSTATE_POS)) -#define CSI_DL0_ULPSACTIVENOT CSI_DL0_ULPSACTIVENOT -#define CSI_DL0_ULPSACTIVENOT_POS (8U) -#define CSI_DL0_ULPSACTIVENOT_LEN (1U) -#define CSI_DL0_ULPSACTIVENOT_MSK (((1U << CSI_DL0_ULPSACTIVENOT_LEN) - 1) << CSI_DL0_ULPSACTIVENOT_POS) -#define CSI_DL0_ULPSACTIVENOT_UMSK (~(((1U << CSI_DL0_ULPSACTIVENOT_LEN) - 1) << CSI_DL0_ULPSACTIVENOT_POS)) -#define CSI_DL1_ULPSACTIVENOT CSI_DL1_ULPSACTIVENOT -#define CSI_DL1_ULPSACTIVENOT_POS (9U) -#define CSI_DL1_ULPSACTIVENOT_LEN (1U) -#define CSI_DL1_ULPSACTIVENOT_MSK (((1U << CSI_DL1_ULPSACTIVENOT_LEN) - 1) << CSI_DL1_ULPSACTIVENOT_POS) -#define CSI_DL1_ULPSACTIVENOT_UMSK (~(((1U << CSI_DL1_ULPSACTIVENOT_LEN) - 1) << CSI_DL1_ULPSACTIVENOT_POS)) -#define CSI_CL_ULPSACTIVENOT CSI_CL_ULPSACTIVENOT -#define CSI_CL_ULPSACTIVENOT_POS (10U) -#define CSI_CL_ULPSACTIVENOT_LEN (1U) -#define CSI_CL_ULPSACTIVENOT_MSK (((1U << CSI_CL_ULPSACTIVENOT_LEN) - 1) << CSI_CL_ULPSACTIVENOT_POS) -#define CSI_CL_ULPSACTIVENOT_UMSK (~(((1U << CSI_CL_ULPSACTIVENOT_LEN) - 1) << CSI_CL_ULPSACTIVENOT_POS)) -#define CSI_DL0_FORCERXMODE CSI_DL0_FORCERXMODE -#define CSI_DL0_FORCERXMODE_POS (12U) -#define CSI_DL0_FORCERXMODE_LEN (1U) -#define CSI_DL0_FORCERXMODE_MSK (((1U << CSI_DL0_FORCERXMODE_LEN) - 1) << CSI_DL0_FORCERXMODE_POS) -#define CSI_DL0_FORCERXMODE_UMSK (~(((1U << CSI_DL0_FORCERXMODE_LEN) - 1) << CSI_DL0_FORCERXMODE_POS)) -#define CSI_DL1_FORCERXMODE CSI_DL1_FORCERXMODE -#define CSI_DL1_FORCERXMODE_POS (13U) -#define CSI_DL1_FORCERXMODE_LEN (1U) -#define CSI_DL1_FORCERXMODE_MSK (((1U << CSI_DL1_FORCERXMODE_LEN) - 1) << CSI_DL1_FORCERXMODE_POS) -#define CSI_DL1_FORCERXMODE_UMSK (~(((1U << CSI_DL1_FORCERXMODE_LEN) - 1) << CSI_DL1_FORCERXMODE_POS)) -#define CSI_CL_RXCLKACTIVEHS CSI_CL_RXCLKACTIVEHS -#define CSI_CL_RXCLKACTIVEHS_POS (14U) -#define CSI_CL_RXCLKACTIVEHS_LEN (1U) -#define CSI_CL_RXCLKACTIVEHS_MSK (((1U << CSI_CL_RXCLKACTIVEHS_LEN) - 1) << CSI_CL_RXCLKACTIVEHS_POS) -#define CSI_CL_RXCLKACTIVEHS_UMSK (~(((1U << CSI_CL_RXCLKACTIVEHS_LEN) - 1) << CSI_CL_RXCLKACTIVEHS_POS)) -#define CSI_CL_RXULPSCLKNOT CSI_CL_RXULPSCLKNOT -#define CSI_CL_RXULPSCLKNOT_POS (15U) -#define CSI_CL_RXULPSCLKNOT_LEN (1U) -#define CSI_CL_RXULPSCLKNOT_MSK (((1U << CSI_CL_RXULPSCLKNOT_LEN) - 1) << CSI_CL_RXULPSCLKNOT_POS) -#define CSI_CL_RXULPSCLKNOT_UMSK (~(((1U << CSI_CL_RXULPSCLKNOT_LEN) - 1) << CSI_CL_RXULPSCLKNOT_POS)) -#define CSI_RESET_N CSI_RESET_N -#define CSI_RESET_N_POS (31U) -#define CSI_RESET_N_LEN (1U) -#define CSI_RESET_N_MSK (((1U << CSI_RESET_N_LEN) - 1) << CSI_RESET_N_POS) -#define CSI_RESET_N_UMSK (~(((1U << CSI_RESET_N_LEN) - 1) << CSI_RESET_N_POS)) - -/* 0x84 : dphy_config_1 */ -#define CSI_DPHY_CONFIG_1_OFFSET (0x84) -#define CSI_REG_TIME_CK_SETTLE CSI_REG_TIME_CK_SETTLE -#define CSI_REG_TIME_CK_SETTLE_POS (0U) -#define CSI_REG_TIME_CK_SETTLE_LEN (8U) -#define CSI_REG_TIME_CK_SETTLE_MSK (((1U << CSI_REG_TIME_CK_SETTLE_LEN) - 1) << CSI_REG_TIME_CK_SETTLE_POS) -#define CSI_REG_TIME_CK_SETTLE_UMSK (~(((1U << CSI_REG_TIME_CK_SETTLE_LEN) - 1) << CSI_REG_TIME_CK_SETTLE_POS)) -#define CSI_REG_TIME_CK_TERM_EN CSI_REG_TIME_CK_TERM_EN -#define CSI_REG_TIME_CK_TERM_EN_POS (8U) -#define CSI_REG_TIME_CK_TERM_EN_LEN (8U) -#define CSI_REG_TIME_CK_TERM_EN_MSK (((1U << CSI_REG_TIME_CK_TERM_EN_LEN) - 1) << CSI_REG_TIME_CK_TERM_EN_POS) -#define CSI_REG_TIME_CK_TERM_EN_UMSK (~(((1U << CSI_REG_TIME_CK_TERM_EN_LEN) - 1) << CSI_REG_TIME_CK_TERM_EN_POS)) -#define CSI_REG_TIME_HS_SETTLE CSI_REG_TIME_HS_SETTLE -#define CSI_REG_TIME_HS_SETTLE_POS (16U) -#define CSI_REG_TIME_HS_SETTLE_LEN (8U) -#define CSI_REG_TIME_HS_SETTLE_MSK (((1U << CSI_REG_TIME_HS_SETTLE_LEN) - 1) << CSI_REG_TIME_HS_SETTLE_POS) -#define CSI_REG_TIME_HS_SETTLE_UMSK (~(((1U << CSI_REG_TIME_HS_SETTLE_LEN) - 1) << CSI_REG_TIME_HS_SETTLE_POS)) -#define CSI_REG_TIME_HS_TERM_EN CSI_REG_TIME_HS_TERM_EN -#define CSI_REG_TIME_HS_TERM_EN_POS (24U) -#define CSI_REG_TIME_HS_TERM_EN_LEN (8U) -#define CSI_REG_TIME_HS_TERM_EN_MSK (((1U << CSI_REG_TIME_HS_TERM_EN_LEN) - 1) << CSI_REG_TIME_HS_TERM_EN_POS) -#define CSI_REG_TIME_HS_TERM_EN_UMSK (~(((1U << CSI_REG_TIME_HS_TERM_EN_LEN) - 1) << CSI_REG_TIME_HS_TERM_EN_POS)) - -/* 0x88 : dphy_config_2 */ -#define CSI_DPHY_CONFIG_2_OFFSET (0x88) -#define CSI_REG_ANA_LPRXEN_CLK CSI_REG_ANA_LPRXEN_CLK -#define CSI_REG_ANA_LPRXEN_CLK_POS (0U) -#define CSI_REG_ANA_LPRXEN_CLK_LEN (1U) -#define CSI_REG_ANA_LPRXEN_CLK_MSK (((1U << CSI_REG_ANA_LPRXEN_CLK_LEN) - 1) << CSI_REG_ANA_LPRXEN_CLK_POS) -#define CSI_REG_ANA_LPRXEN_CLK_UMSK (~(((1U << CSI_REG_ANA_LPRXEN_CLK_LEN) - 1) << CSI_REG_ANA_LPRXEN_CLK_POS)) -#define CSI_REG_ANA_HSRXEN_CLK CSI_REG_ANA_HSRXEN_CLK -#define CSI_REG_ANA_HSRXEN_CLK_POS (1U) -#define CSI_REG_ANA_HSRXEN_CLK_LEN (1U) -#define CSI_REG_ANA_HSRXEN_CLK_MSK (((1U << CSI_REG_ANA_HSRXEN_CLK_LEN) - 1) << CSI_REG_ANA_HSRXEN_CLK_POS) -#define CSI_REG_ANA_HSRXEN_CLK_UMSK (~(((1U << CSI_REG_ANA_HSRXEN_CLK_LEN) - 1) << CSI_REG_ANA_HSRXEN_CLK_POS)) -#define CSI_REG_ANA_HSRX_STOP_STATE CSI_REG_ANA_HSRX_STOP_STATE -#define CSI_REG_ANA_HSRX_STOP_STATE_POS (2U) -#define CSI_REG_ANA_HSRX_STOP_STATE_LEN (2U) -#define CSI_REG_ANA_HSRX_STOP_STATE_MSK (((1U << CSI_REG_ANA_HSRX_STOP_STATE_LEN) - 1) << CSI_REG_ANA_HSRX_STOP_STATE_POS) -#define CSI_REG_ANA_HSRX_STOP_STATE_UMSK (~(((1U << CSI_REG_ANA_HSRX_STOP_STATE_LEN) - 1) << CSI_REG_ANA_HSRX_STOP_STATE_POS)) -#define CSI_REG_ANA_HSRX_SYNC_EN CSI_REG_ANA_HSRX_SYNC_EN -#define CSI_REG_ANA_HSRX_SYNC_EN_POS (4U) -#define CSI_REG_ANA_HSRX_SYNC_EN_LEN (2U) -#define CSI_REG_ANA_HSRX_SYNC_EN_MSK (((1U << CSI_REG_ANA_HSRX_SYNC_EN_LEN) - 1) << CSI_REG_ANA_HSRX_SYNC_EN_POS) -#define CSI_REG_ANA_HSRX_SYNC_EN_UMSK (~(((1U << CSI_REG_ANA_HSRX_SYNC_EN_LEN) - 1) << CSI_REG_ANA_HSRX_SYNC_EN_POS)) -#define CSI_REG_ANA_LPRXEN CSI_REG_ANA_LPRXEN -#define CSI_REG_ANA_LPRXEN_POS (6U) -#define CSI_REG_ANA_LPRXEN_LEN (2U) -#define CSI_REG_ANA_LPRXEN_MSK (((1U << CSI_REG_ANA_LPRXEN_LEN) - 1) << CSI_REG_ANA_LPRXEN_POS) -#define CSI_REG_ANA_LPRXEN_UMSK (~(((1U << CSI_REG_ANA_LPRXEN_LEN) - 1) << CSI_REG_ANA_LPRXEN_POS)) -#define CSI_REG_ANA_HSRXEN CSI_REG_ANA_HSRXEN -#define CSI_REG_ANA_HSRXEN_POS (8U) -#define CSI_REG_ANA_HSRXEN_LEN (2U) -#define CSI_REG_ANA_HSRXEN_MSK (((1U << CSI_REG_ANA_HSRXEN_LEN) - 1) << CSI_REG_ANA_HSRXEN_POS) -#define CSI_REG_ANA_HSRXEN_UMSK (~(((1U << CSI_REG_ANA_HSRXEN_LEN) - 1) << CSI_REG_ANA_HSRXEN_POS)) -#define CSI_REG_ANA_TERM_EN CSI_REG_ANA_TERM_EN -#define CSI_REG_ANA_TERM_EN_POS (10U) -#define CSI_REG_ANA_TERM_EN_LEN (5U) -#define CSI_REG_ANA_TERM_EN_MSK (((1U << CSI_REG_ANA_TERM_EN_LEN) - 1) << CSI_REG_ANA_TERM_EN_POS) -#define CSI_REG_ANA_TERM_EN_UMSK (~(((1U << CSI_REG_ANA_TERM_EN_LEN) - 1) << CSI_REG_ANA_TERM_EN_POS)) -#define CSI_REG_ANA_TEST_EN CSI_REG_ANA_TEST_EN -#define CSI_REG_ANA_TEST_EN_POS (15U) -#define CSI_REG_ANA_TEST_EN_LEN (1U) -#define CSI_REG_ANA_TEST_EN_MSK (((1U << CSI_REG_ANA_TEST_EN_LEN) - 1) << CSI_REG_ANA_TEST_EN_POS) -#define CSI_REG_ANA_TEST_EN_UMSK (~(((1U << CSI_REG_ANA_TEST_EN_LEN) - 1) << CSI_REG_ANA_TEST_EN_POS)) -#define CSI_REG_PT_LOCK_COUNTER CSI_REG_PT_LOCK_COUNTER -#define CSI_REG_PT_LOCK_COUNTER_POS (16U) -#define CSI_REG_PT_LOCK_COUNTER_LEN (4U) -#define CSI_REG_PT_LOCK_COUNTER_MSK (((1U << CSI_REG_PT_LOCK_COUNTER_LEN) - 1) << CSI_REG_PT_LOCK_COUNTER_POS) -#define CSI_REG_PT_LOCK_COUNTER_UMSK (~(((1U << CSI_REG_PT_LOCK_COUNTER_LEN) - 1) << CSI_REG_PT_LOCK_COUNTER_POS)) -#define CSI_REG_PT_PRBS_OR_JITT CSI_REG_PT_PRBS_OR_JITT -#define CSI_REG_PT_PRBS_OR_JITT_POS (20U) -#define CSI_REG_PT_PRBS_OR_JITT_LEN (1U) -#define CSI_REG_PT_PRBS_OR_JITT_MSK (((1U << CSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << CSI_REG_PT_PRBS_OR_JITT_POS) -#define CSI_REG_PT_PRBS_OR_JITT_UMSK (~(((1U << CSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << CSI_REG_PT_PRBS_OR_JITT_POS)) -#define CSI_REG_PT_LP_MODE CSI_REG_PT_LP_MODE -#define CSI_REG_PT_LP_MODE_POS (21U) -#define CSI_REG_PT_LP_MODE_LEN (1U) -#define CSI_REG_PT_LP_MODE_MSK (((1U << CSI_REG_PT_LP_MODE_LEN) - 1) << CSI_REG_PT_LP_MODE_POS) -#define CSI_REG_PT_LP_MODE_UMSK (~(((1U << CSI_REG_PT_LP_MODE_LEN) - 1) << CSI_REG_PT_LP_MODE_POS)) -#define CSI_REG_PT_EN CSI_REG_PT_EN -#define CSI_REG_PT_EN_POS (22U) -#define CSI_REG_PT_EN_LEN (1U) -#define CSI_REG_PT_EN_MSK (((1U << CSI_REG_PT_EN_LEN) - 1) << CSI_REG_PT_EN_POS) -#define CSI_REG_PT_EN_UMSK (~(((1U << CSI_REG_PT_EN_LEN) - 1) << CSI_REG_PT_EN_POS)) -#define CSI_REG_PT_LOCK CSI_REG_PT_LOCK -#define CSI_REG_PT_LOCK_POS (23U) -#define CSI_REG_PT_LOCK_LEN (1U) -#define CSI_REG_PT_LOCK_MSK (((1U << CSI_REG_PT_LOCK_LEN) - 1) << CSI_REG_PT_LOCK_POS) -#define CSI_REG_PT_LOCK_UMSK (~(((1U << CSI_REG_PT_LOCK_LEN) - 1) << CSI_REG_PT_LOCK_POS)) -#define CSI_REG_PT_PASS CSI_REG_PT_PASS -#define CSI_REG_PT_PASS_POS (24U) -#define CSI_REG_PT_PASS_LEN (1U) -#define CSI_REG_PT_PASS_MSK (((1U << CSI_REG_PT_PASS_LEN) - 1) << CSI_REG_PT_PASS_POS) -#define CSI_REG_PT_PASS_UMSK (~(((1U << CSI_REG_PT_PASS_LEN) - 1) << CSI_REG_PT_PASS_POS)) - -/* 0x8C : dphy_config_3 */ -#define CSI_DPHY_CONFIG_3_OFFSET (0x8C) -#define CSI_REG_CSI_ANA_1 CSI_REG_CSI_ANA_1 -#define CSI_REG_CSI_ANA_1_POS (0U) -#define CSI_REG_CSI_ANA_1_LEN (16U) -#define CSI_REG_CSI_ANA_1_MSK (((1U << CSI_REG_CSI_ANA_1_LEN) - 1) << CSI_REG_CSI_ANA_1_POS) -#define CSI_REG_CSI_ANA_1_UMSK (~(((1U << CSI_REG_CSI_ANA_1_LEN) - 1) << CSI_REG_CSI_ANA_1_POS)) -#define CSI_REG_CSI_ANA_0 CSI_REG_CSI_ANA_0 -#define CSI_REG_CSI_ANA_0_POS (16U) -#define CSI_REG_CSI_ANA_0_LEN (16U) -#define CSI_REG_CSI_ANA_0_MSK (((1U << CSI_REG_CSI_ANA_0_LEN) - 1) << CSI_REG_CSI_ANA_0_POS) -#define CSI_REG_CSI_ANA_0_UMSK (~(((1U << CSI_REG_CSI_ANA_0_LEN) - 1) << CSI_REG_CSI_ANA_0_POS)) - -/* 0x90 : dphy_config_4 */ -#define CSI_DPHY_CONFIG_4_OFFSET (0x90) -#define CSI_REG_CSI_DC_TP_OUT_EN CSI_REG_CSI_DC_TP_OUT_EN -#define CSI_REG_CSI_DC_TP_OUT_EN_POS (0U) -#define CSI_REG_CSI_DC_TP_OUT_EN_LEN (1U) -#define CSI_REG_CSI_DC_TP_OUT_EN_MSK (((1U << CSI_REG_CSI_DC_TP_OUT_EN_LEN) - 1) << CSI_REG_CSI_DC_TP_OUT_EN_POS) -#define CSI_REG_CSI_DC_TP_OUT_EN_UMSK (~(((1U << CSI_REG_CSI_DC_TP_OUT_EN_LEN) - 1) << CSI_REG_CSI_DC_TP_OUT_EN_POS)) -#define CSI_REG_CSI_PW_AVDD1815 CSI_REG_CSI_PW_AVDD1815 -#define CSI_REG_CSI_PW_AVDD1815_POS (4U) -#define CSI_REG_CSI_PW_AVDD1815_LEN (1U) -#define CSI_REG_CSI_PW_AVDD1815_MSK (((1U << CSI_REG_CSI_PW_AVDD1815_LEN) - 1) << CSI_REG_CSI_PW_AVDD1815_POS) -#define CSI_REG_CSI_PW_AVDD1815_UMSK (~(((1U << CSI_REG_CSI_PW_AVDD1815_LEN) - 1) << CSI_REG_CSI_PW_AVDD1815_POS)) - -/* 0x94 : dphy_config_5 */ -#define CSI_DPHY_CONFIG_5_OFFSET (0x94) -#define CSI_REG_CSI_BYTE_CLK_INV CSI_REG_CSI_BYTE_CLK_INV -#define CSI_REG_CSI_BYTE_CLK_INV_POS (0U) -#define CSI_REG_CSI_BYTE_CLK_INV_LEN (1U) -#define CSI_REG_CSI_BYTE_CLK_INV_MSK (((1U << CSI_REG_CSI_BYTE_CLK_INV_LEN) - 1) << CSI_REG_CSI_BYTE_CLK_INV_POS) -#define CSI_REG_CSI_BYTE_CLK_INV_UMSK (~(((1U << CSI_REG_CSI_BYTE_CLK_INV_LEN) - 1) << CSI_REG_CSI_BYTE_CLK_INV_POS)) -#define CSI_REG_CSI_DDR_CLK_INV CSI_REG_CSI_DDR_CLK_INV -#define CSI_REG_CSI_DDR_CLK_INV_POS (1U) -#define CSI_REG_CSI_DDR_CLK_INV_LEN (1U) -#define CSI_REG_CSI_DDR_CLK_INV_MSK (((1U << CSI_REG_CSI_DDR_CLK_INV_LEN) - 1) << CSI_REG_CSI_DDR_CLK_INV_POS) -#define CSI_REG_CSI_DDR_CLK_INV_UMSK (~(((1U << CSI_REG_CSI_DDR_CLK_INV_LEN) - 1) << CSI_REG_CSI_DDR_CLK_INV_POS)) - -/* 0xFC : dummy_reg */ -#define CSI_DUMMY_REG_OFFSET (0xFC) -#define CSI_DUMMY_REG CSI_DUMMY_REG -#define CSI_DUMMY_REG_POS (0U) -#define CSI_DUMMY_REG_LEN (32U) -#define CSI_DUMMY_REG_MSK (((1U << CSI_DUMMY_REG_LEN) - 1) << CSI_DUMMY_REG_POS) -#define CSI_DUMMY_REG_UMSK (~(((1U << CSI_DUMMY_REG_LEN) - 1) << CSI_DUMMY_REG_POS)) - -struct csi_reg { - /* 0x0 : mipi_config */ - union { - struct { - uint32_t cr_csi_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_lane_num : 1; /* [ 1], r/w, 0x1 */ - uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */ - uint32_t cr_lane_inv : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_data_bit_inv : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_sync_sp_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_unpack_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t reserved_7_11 : 5; /* [11: 7], rsvd, 0x0 */ - uint32_t cr_vc_dvp0 : 2; /* [13:12], r/w, 0x0 */ - uint32_t cr_vc_dvp1 : 2; /* [15:14], r/w, 0x1 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mipi_config; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[12]; - - /* 0x10 : csi_int_status */ - union { - struct { - uint32_t csi_int_status : 6; /* [ 5: 0], r, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_status; - - /* 0x14 : csi_int_mask */ - union { - struct { - uint32_t csi_int_mask : 6; /* [ 5: 0], r/w, 0x3f */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_mask; - - /* 0x18 : csi_int_clear */ - union { - struct { - uint32_t csi_int_clear : 6; /* [ 5: 0], w1p, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_clear; - - /* 0x1C : csi_int_enable */ - union { - struct { - uint32_t csi_int_enable : 6; /* [ 5: 0], r/w, 0x3f */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } csi_int_enable; - - /* 0x20 : gnr_buf_status */ - union { - struct { - uint32_t st_gnr_fifo_cnt : 4; /* [ 3: 0], r, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gnr_buf_status; - - /* 0x24 : gnr_buf_rdata */ - union { - struct { - uint32_t gnr_buf_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } gnr_buf_rdata; - - /* 0x28 reserved */ - uint8_t RESERVED0x28[88]; - - /* 0x80 : dphy_config_0 */ - union { - struct { - uint32_t dl0_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t dl1_enable : 1; /* [ 1], r/w, 0x0 */ - uint32_t cl_enable : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t dl0_stopstate : 1; /* [ 4], r, 0x1 */ - uint32_t dl1_stopstate : 1; /* [ 5], r, 0x1 */ - uint32_t cl_stopstate : 1; /* [ 6], r, 0x1 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t dl0_ulpsactivenot : 1; /* [ 8], r, 0x1 */ - uint32_t dl1_ulpsactivenot : 1; /* [ 9], r, 0x1 */ - uint32_t cl_ulpsactivenot : 1; /* [ 10], r, 0x1 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t dl0_forcerxmode : 1; /* [ 12], r/w, 0x0 */ - uint32_t dl1_forcerxmode : 1; /* [ 13], r/w, 0x0 */ - uint32_t cl_rxclkactivehs : 1; /* [ 14], r, 0x0 */ - uint32_t cl_rxulpsclknot : 1; /* [ 15], r, 0x1 */ - uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */ - uint32_t csi_reset_n : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_0; - - /* 0x84 : dphy_config_1 */ - union { - struct { - uint32_t reg_time_ck_settle : 8; /* [ 7: 0], r/w, 0xa */ - uint32_t reg_time_ck_term_en : 8; /* [15: 8], r/w, 0x1 */ - uint32_t reg_time_hs_settle : 8; /* [23:16], r/w, 0x2f */ - uint32_t reg_time_hs_term_en : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } dphy_config_1; - - /* 0x88 : dphy_config_2 */ - union { - struct { - uint32_t reg_ana_lprxen_clk : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_ana_hsrxen_clk : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_ana_hsrx_stop_state : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reg_ana_hsrx_sync_en : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reg_ana_lprxen : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t reg_ana_hsrxen : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t reg_ana_term_en : 5; /* [14:10], r/w, 0x0 */ - uint32_t reg_ana_test_en : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_pt_lock_counter : 4; /* [19:16], r/w, 0x0 */ - uint32_t reg_pt_prbs_or_jitt : 1; /* [ 20], r/w, 0x0 */ - uint32_t reg_pt_lp_mode : 1; /* [ 21], r/w, 0x0 */ - uint32_t reg_pt_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t reg_pt_lock : 1; /* [ 23], r, 0x0 */ - uint32_t reg_pt_pass : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_2; - - /* 0x8C : dphy_config_3 */ - union { - struct { - uint32_t reg_csi_ana_1 : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_csi_ana_0 : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_3; - - /* 0x90 : dphy_config_4 */ - union { - struct { - uint32_t reg_csi_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_csi_pw_avdd1815 : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_4; - - /* 0x94 : dphy_config_5 */ - union { - struct { - uint32_t reg_csi_byte_clk_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_csi_ddr_clk_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_5; - - /* 0x98 reserved */ - uint8_t RESERVED0x98[100]; - - /* 0xFC : dummy_reg */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dummy_reg; -}; - -typedef volatile struct csi_reg csi_reg_t; - -#endif /* __CSI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dbi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dbi_reg.h deleted file mode 100644 index cf982e4c80..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dbi_reg.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - ****************************************************************************** - * @file dbi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DBI_REG_H__ -#define __DBI_REG_H__ - -#include "bl808.h" - -/* 0x0 : dbi_config */ -#define DBI_CONFIG_OFFSET (0x0) -#define DBI_CR_DBI_EN DBI_CR_DBI_EN -#define DBI_CR_DBI_EN_POS (0U) -#define DBI_CR_DBI_EN_LEN (1U) -#define DBI_CR_DBI_EN_MSK (((1U << DBI_CR_DBI_EN_LEN) - 1) << DBI_CR_DBI_EN_POS) -#define DBI_CR_DBI_EN_UMSK (~(((1U << DBI_CR_DBI_EN_LEN) - 1) << DBI_CR_DBI_EN_POS)) -#define DBI_CR_DBI_SEL DBI_CR_DBI_SEL -#define DBI_CR_DBI_SEL_POS (1U) -#define DBI_CR_DBI_SEL_LEN (1U) -#define DBI_CR_DBI_SEL_MSK (((1U << DBI_CR_DBI_SEL_LEN) - 1) << DBI_CR_DBI_SEL_POS) -#define DBI_CR_DBI_SEL_UMSK (~(((1U << DBI_CR_DBI_SEL_LEN) - 1) << DBI_CR_DBI_SEL_POS)) -#define DBI_CR_DBI_CMD_EN DBI_CR_DBI_CMD_EN -#define DBI_CR_DBI_CMD_EN_POS (2U) -#define DBI_CR_DBI_CMD_EN_LEN (1U) -#define DBI_CR_DBI_CMD_EN_MSK (((1U << DBI_CR_DBI_CMD_EN_LEN) - 1) << DBI_CR_DBI_CMD_EN_POS) -#define DBI_CR_DBI_CMD_EN_UMSK (~(((1U << DBI_CR_DBI_CMD_EN_LEN) - 1) << DBI_CR_DBI_CMD_EN_POS)) -#define DBI_CR_DBI_DAT_EN DBI_CR_DBI_DAT_EN -#define DBI_CR_DBI_DAT_EN_POS (3U) -#define DBI_CR_DBI_DAT_EN_LEN (1U) -#define DBI_CR_DBI_DAT_EN_MSK (((1U << DBI_CR_DBI_DAT_EN_LEN) - 1) << DBI_CR_DBI_DAT_EN_POS) -#define DBI_CR_DBI_DAT_EN_UMSK (~(((1U << DBI_CR_DBI_DAT_EN_LEN) - 1) << DBI_CR_DBI_DAT_EN_POS)) -#define DBI_CR_DBI_DAT_WR DBI_CR_DBI_DAT_WR -#define DBI_CR_DBI_DAT_WR_POS (4U) -#define DBI_CR_DBI_DAT_WR_LEN (1U) -#define DBI_CR_DBI_DAT_WR_MSK (((1U << DBI_CR_DBI_DAT_WR_LEN) - 1) << DBI_CR_DBI_DAT_WR_POS) -#define DBI_CR_DBI_DAT_WR_UMSK (~(((1U << DBI_CR_DBI_DAT_WR_LEN) - 1) << DBI_CR_DBI_DAT_WR_POS)) -#define DBI_CR_DBI_DAT_TP DBI_CR_DBI_DAT_TP -#define DBI_CR_DBI_DAT_TP_POS (5U) -#define DBI_CR_DBI_DAT_TP_LEN (1U) -#define DBI_CR_DBI_DAT_TP_MSK (((1U << DBI_CR_DBI_DAT_TP_LEN) - 1) << DBI_CR_DBI_DAT_TP_POS) -#define DBI_CR_DBI_DAT_TP_UMSK (~(((1U << DBI_CR_DBI_DAT_TP_LEN) - 1) << DBI_CR_DBI_DAT_TP_POS)) -#define DBI_CR_DBI_DAT_BC DBI_CR_DBI_DAT_BC -#define DBI_CR_DBI_DAT_BC_POS (6U) -#define DBI_CR_DBI_DAT_BC_LEN (2U) -#define DBI_CR_DBI_DAT_BC_MSK (((1U << DBI_CR_DBI_DAT_BC_LEN) - 1) << DBI_CR_DBI_DAT_BC_POS) -#define DBI_CR_DBI_DAT_BC_UMSK (~(((1U << DBI_CR_DBI_DAT_BC_LEN) - 1) << DBI_CR_DBI_DAT_BC_POS)) -#define DBI_CR_DBI_CMD DBI_CR_DBI_CMD -#define DBI_CR_DBI_CMD_POS (8U) -#define DBI_CR_DBI_CMD_LEN (8U) -#define DBI_CR_DBI_CMD_MSK (((1U << DBI_CR_DBI_CMD_LEN) - 1) << DBI_CR_DBI_CMD_POS) -#define DBI_CR_DBI_CMD_UMSK (~(((1U << DBI_CR_DBI_CMD_LEN) - 1) << DBI_CR_DBI_CMD_POS)) -#define DBI_CR_DBI_SCL_POL DBI_CR_DBI_SCL_POL -#define DBI_CR_DBI_SCL_POL_POS (16U) -#define DBI_CR_DBI_SCL_POL_LEN (1U) -#define DBI_CR_DBI_SCL_POL_MSK (((1U << DBI_CR_DBI_SCL_POL_LEN) - 1) << DBI_CR_DBI_SCL_POL_POS) -#define DBI_CR_DBI_SCL_POL_UMSK (~(((1U << DBI_CR_DBI_SCL_POL_LEN) - 1) << DBI_CR_DBI_SCL_POL_POS)) -#define DBI_CR_DBI_SCL_PH DBI_CR_DBI_SCL_PH -#define DBI_CR_DBI_SCL_PH_POS (17U) -#define DBI_CR_DBI_SCL_PH_LEN (1U) -#define DBI_CR_DBI_SCL_PH_MSK (((1U << DBI_CR_DBI_SCL_PH_LEN) - 1) << DBI_CR_DBI_SCL_PH_POS) -#define DBI_CR_DBI_SCL_PH_UMSK (~(((1U << DBI_CR_DBI_SCL_PH_LEN) - 1) << DBI_CR_DBI_SCL_PH_POS)) -#define DBI_CR_DBI_CONT_EN DBI_CR_DBI_CONT_EN -#define DBI_CR_DBI_CONT_EN_POS (18U) -#define DBI_CR_DBI_CONT_EN_LEN (1U) -#define DBI_CR_DBI_CONT_EN_MSK (((1U << DBI_CR_DBI_CONT_EN_LEN) - 1) << DBI_CR_DBI_CONT_EN_POS) -#define DBI_CR_DBI_CONT_EN_UMSK (~(((1U << DBI_CR_DBI_CONT_EN_LEN) - 1) << DBI_CR_DBI_CONT_EN_POS)) -#define DBI_CR_DBI_DMY_EN DBI_CR_DBI_DMY_EN -#define DBI_CR_DBI_DMY_EN_POS (19U) -#define DBI_CR_DBI_DMY_EN_LEN (1U) -#define DBI_CR_DBI_DMY_EN_MSK (((1U << DBI_CR_DBI_DMY_EN_LEN) - 1) << DBI_CR_DBI_DMY_EN_POS) -#define DBI_CR_DBI_DMY_EN_UMSK (~(((1U << DBI_CR_DBI_DMY_EN_LEN) - 1) << DBI_CR_DBI_DMY_EN_POS)) -#define DBI_CR_DBI_DMY_CNT DBI_CR_DBI_DMY_CNT -#define DBI_CR_DBI_DMY_CNT_POS (20U) -#define DBI_CR_DBI_DMY_CNT_LEN (4U) -#define DBI_CR_DBI_DMY_CNT_MSK (((1U << DBI_CR_DBI_DMY_CNT_LEN) - 1) << DBI_CR_DBI_DMY_CNT_POS) -#define DBI_CR_DBI_DMY_CNT_UMSK (~(((1U << DBI_CR_DBI_DMY_CNT_LEN) - 1) << DBI_CR_DBI_DMY_CNT_POS)) -#define DBI_CR_DBI_TC_3W_MODE DBI_CR_DBI_TC_3W_MODE -#define DBI_CR_DBI_TC_3W_MODE_POS (27U) -#define DBI_CR_DBI_TC_3W_MODE_LEN (1U) -#define DBI_CR_DBI_TC_3W_MODE_MSK (((1U << DBI_CR_DBI_TC_3W_MODE_LEN) - 1) << DBI_CR_DBI_TC_3W_MODE_POS) -#define DBI_CR_DBI_TC_3W_MODE_UMSK (~(((1U << DBI_CR_DBI_TC_3W_MODE_LEN) - 1) << DBI_CR_DBI_TC_3W_MODE_POS)) -#define DBI_CR_DBI_TC_DEG_EN DBI_CR_DBI_TC_DEG_EN -#define DBI_CR_DBI_TC_DEG_EN_POS (28U) -#define DBI_CR_DBI_TC_DEG_EN_LEN (1U) -#define DBI_CR_DBI_TC_DEG_EN_MSK (((1U << DBI_CR_DBI_TC_DEG_EN_LEN) - 1) << DBI_CR_DBI_TC_DEG_EN_POS) -#define DBI_CR_DBI_TC_DEG_EN_UMSK (~(((1U << DBI_CR_DBI_TC_DEG_EN_LEN) - 1) << DBI_CR_DBI_TC_DEG_EN_POS)) -#define DBI_CR_DBI_TC_DEG_CNT DBI_CR_DBI_TC_DEG_CNT -#define DBI_CR_DBI_TC_DEG_CNT_POS (29U) -#define DBI_CR_DBI_TC_DEG_CNT_LEN (3U) -#define DBI_CR_DBI_TC_DEG_CNT_MSK (((1U << DBI_CR_DBI_TC_DEG_CNT_LEN) - 1) << DBI_CR_DBI_TC_DEG_CNT_POS) -#define DBI_CR_DBI_TC_DEG_CNT_UMSK (~(((1U << DBI_CR_DBI_TC_DEG_CNT_LEN) - 1) << DBI_CR_DBI_TC_DEG_CNT_POS)) - -/* 0x4 : dbi_int_sts */ -#define DBI_INT_STS_OFFSET (0x4) -#define DBI_END_INT DBI_END_INT -#define DBI_END_INT_POS (0U) -#define DBI_END_INT_LEN (1U) -#define DBI_END_INT_MSK (((1U << DBI_END_INT_LEN) - 1) << DBI_END_INT_POS) -#define DBI_END_INT_UMSK (~(((1U << DBI_END_INT_LEN) - 1) << DBI_END_INT_POS)) -#define DBI_TXF_INT DBI_TXF_INT -#define DBI_TXF_INT_POS (1U) -#define DBI_TXF_INT_LEN (1U) -#define DBI_TXF_INT_MSK (((1U << DBI_TXF_INT_LEN) - 1) << DBI_TXF_INT_POS) -#define DBI_TXF_INT_UMSK (~(((1U << DBI_TXF_INT_LEN) - 1) << DBI_TXF_INT_POS)) -#define DBI_FER_INT DBI_FER_INT -#define DBI_FER_INT_POS (2U) -#define DBI_FER_INT_LEN (1U) -#define DBI_FER_INT_MSK (((1U << DBI_FER_INT_LEN) - 1) << DBI_FER_INT_POS) -#define DBI_FER_INT_UMSK (~(((1U << DBI_FER_INT_LEN) - 1) << DBI_FER_INT_POS)) -#define DBI_CR_DBI_END_MASK DBI_CR_DBI_END_MASK -#define DBI_CR_DBI_END_MASK_POS (8U) -#define DBI_CR_DBI_END_MASK_LEN (1U) -#define DBI_CR_DBI_END_MASK_MSK (((1U << DBI_CR_DBI_END_MASK_LEN) - 1) << DBI_CR_DBI_END_MASK_POS) -#define DBI_CR_DBI_END_MASK_UMSK (~(((1U << DBI_CR_DBI_END_MASK_LEN) - 1) << DBI_CR_DBI_END_MASK_POS)) -#define DBI_CR_DBI_TXF_MASK DBI_CR_DBI_TXF_MASK -#define DBI_CR_DBI_TXF_MASK_POS (9U) -#define DBI_CR_DBI_TXF_MASK_LEN (1U) -#define DBI_CR_DBI_TXF_MASK_MSK (((1U << DBI_CR_DBI_TXF_MASK_LEN) - 1) << DBI_CR_DBI_TXF_MASK_POS) -#define DBI_CR_DBI_TXF_MASK_UMSK (~(((1U << DBI_CR_DBI_TXF_MASK_LEN) - 1) << DBI_CR_DBI_TXF_MASK_POS)) -#define DBI_CR_DBI_FER_MASK DBI_CR_DBI_FER_MASK -#define DBI_CR_DBI_FER_MASK_POS (10U) -#define DBI_CR_DBI_FER_MASK_LEN (1U) -#define DBI_CR_DBI_FER_MASK_MSK (((1U << DBI_CR_DBI_FER_MASK_LEN) - 1) << DBI_CR_DBI_FER_MASK_POS) -#define DBI_CR_DBI_FER_MASK_UMSK (~(((1U << DBI_CR_DBI_FER_MASK_LEN) - 1) << DBI_CR_DBI_FER_MASK_POS)) -#define DBI_CR_DBI_END_CLR DBI_CR_DBI_END_CLR -#define DBI_CR_DBI_END_CLR_POS (16U) -#define DBI_CR_DBI_END_CLR_LEN (1U) -#define DBI_CR_DBI_END_CLR_MSK (((1U << DBI_CR_DBI_END_CLR_LEN) - 1) << DBI_CR_DBI_END_CLR_POS) -#define DBI_CR_DBI_END_CLR_UMSK (~(((1U << DBI_CR_DBI_END_CLR_LEN) - 1) << DBI_CR_DBI_END_CLR_POS)) -#define DBI_CR_DBI_END_EN DBI_CR_DBI_END_EN -#define DBI_CR_DBI_END_EN_POS (24U) -#define DBI_CR_DBI_END_EN_LEN (1U) -#define DBI_CR_DBI_END_EN_MSK (((1U << DBI_CR_DBI_END_EN_LEN) - 1) << DBI_CR_DBI_END_EN_POS) -#define DBI_CR_DBI_END_EN_UMSK (~(((1U << DBI_CR_DBI_END_EN_LEN) - 1) << DBI_CR_DBI_END_EN_POS)) -#define DBI_CR_DBI_TXF_EN DBI_CR_DBI_TXF_EN -#define DBI_CR_DBI_TXF_EN_POS (25U) -#define DBI_CR_DBI_TXF_EN_LEN (1U) -#define DBI_CR_DBI_TXF_EN_MSK (((1U << DBI_CR_DBI_TXF_EN_LEN) - 1) << DBI_CR_DBI_TXF_EN_POS) -#define DBI_CR_DBI_TXF_EN_UMSK (~(((1U << DBI_CR_DBI_TXF_EN_LEN) - 1) << DBI_CR_DBI_TXF_EN_POS)) -#define DBI_CR_DBI_FER_EN DBI_CR_DBI_FER_EN -#define DBI_CR_DBI_FER_EN_POS (26U) -#define DBI_CR_DBI_FER_EN_LEN (1U) -#define DBI_CR_DBI_FER_EN_MSK (((1U << DBI_CR_DBI_FER_EN_LEN) - 1) << DBI_CR_DBI_FER_EN_POS) -#define DBI_CR_DBI_FER_EN_UMSK (~(((1U << DBI_CR_DBI_FER_EN_LEN) - 1) << DBI_CR_DBI_FER_EN_POS)) - -/* 0x8 : dbi_bus_busy */ -#define DBI_BUS_BUSY_OFFSET (0x8) -#define DBI_STS_DBI_BUS_BUSY DBI_STS_DBI_BUS_BUSY -#define DBI_STS_DBI_BUS_BUSY_POS (0U) -#define DBI_STS_DBI_BUS_BUSY_LEN (1U) -#define DBI_STS_DBI_BUS_BUSY_MSK (((1U << DBI_STS_DBI_BUS_BUSY_LEN) - 1) << DBI_STS_DBI_BUS_BUSY_POS) -#define DBI_STS_DBI_BUS_BUSY_UMSK (~(((1U << DBI_STS_DBI_BUS_BUSY_LEN) - 1) << DBI_STS_DBI_BUS_BUSY_POS)) - -/* 0xC : dbi_pix_cnt */ -#define DBI_PIX_CNT_OFFSET (0xC) -#define DBI_CR_DBI_PIX_CNT DBI_CR_DBI_PIX_CNT -#define DBI_CR_DBI_PIX_CNT_POS (0U) -#define DBI_CR_DBI_PIX_CNT_LEN (24U) -#define DBI_CR_DBI_PIX_CNT_MSK (((1U << DBI_CR_DBI_PIX_CNT_LEN) - 1) << DBI_CR_DBI_PIX_CNT_POS) -#define DBI_CR_DBI_PIX_CNT_UMSK (~(((1U << DBI_CR_DBI_PIX_CNT_LEN) - 1) << DBI_CR_DBI_PIX_CNT_POS)) -#define DBI_CR_DBI_PIX_FORMAT DBI_CR_DBI_PIX_FORMAT -#define DBI_CR_DBI_PIX_FORMAT_POS (31U) -#define DBI_CR_DBI_PIX_FORMAT_LEN (1U) -#define DBI_CR_DBI_PIX_FORMAT_MSK (((1U << DBI_CR_DBI_PIX_FORMAT_LEN) - 1) << DBI_CR_DBI_PIX_FORMAT_POS) -#define DBI_CR_DBI_PIX_FORMAT_UMSK (~(((1U << DBI_CR_DBI_PIX_FORMAT_LEN) - 1) << DBI_CR_DBI_PIX_FORMAT_POS)) - -/* 0x10 : dbi_prd */ -#define DBI_PRD_OFFSET (0x10) -#define DBI_CR_DBI_PRD_S DBI_CR_DBI_PRD_S -#define DBI_CR_DBI_PRD_S_POS (0U) -#define DBI_CR_DBI_PRD_S_LEN (8U) -#define DBI_CR_DBI_PRD_S_MSK (((1U << DBI_CR_DBI_PRD_S_LEN) - 1) << DBI_CR_DBI_PRD_S_POS) -#define DBI_CR_DBI_PRD_S_UMSK (~(((1U << DBI_CR_DBI_PRD_S_LEN) - 1) << DBI_CR_DBI_PRD_S_POS)) -#define DBI_CR_DBI_PRD_I DBI_CR_DBI_PRD_I -#define DBI_CR_DBI_PRD_I_POS (8U) -#define DBI_CR_DBI_PRD_I_LEN (8U) -#define DBI_CR_DBI_PRD_I_MSK (((1U << DBI_CR_DBI_PRD_I_LEN) - 1) << DBI_CR_DBI_PRD_I_POS) -#define DBI_CR_DBI_PRD_I_UMSK (~(((1U << DBI_CR_DBI_PRD_I_LEN) - 1) << DBI_CR_DBI_PRD_I_POS)) -#define DBI_CR_DBI_PRD_D_PH_0 DBI_CR_DBI_PRD_D_PH_0 -#define DBI_CR_DBI_PRD_D_PH_0_POS (16U) -#define DBI_CR_DBI_PRD_D_PH_0_LEN (8U) -#define DBI_CR_DBI_PRD_D_PH_0_MSK (((1U << DBI_CR_DBI_PRD_D_PH_0_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_0_POS) -#define DBI_CR_DBI_PRD_D_PH_0_UMSK (~(((1U << DBI_CR_DBI_PRD_D_PH_0_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_0_POS)) -#define DBI_CR_DBI_PRD_D_PH_1 DBI_CR_DBI_PRD_D_PH_1 -#define DBI_CR_DBI_PRD_D_PH_1_POS (24U) -#define DBI_CR_DBI_PRD_D_PH_1_LEN (8U) -#define DBI_CR_DBI_PRD_D_PH_1_MSK (((1U << DBI_CR_DBI_PRD_D_PH_1_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_1_POS) -#define DBI_CR_DBI_PRD_D_PH_1_UMSK (~(((1U << DBI_CR_DBI_PRD_D_PH_1_LEN) - 1) << DBI_CR_DBI_PRD_D_PH_1_POS)) - -/* 0x18 : dbi_wdata */ -#define DBI_WDATA_OFFSET (0x18) -#define DBI_CR_DBI_WDATA DBI_CR_DBI_WDATA -#define DBI_CR_DBI_WDATA_POS (0U) -#define DBI_CR_DBI_WDATA_LEN (32U) -#define DBI_CR_DBI_WDATA_MSK (((1U << DBI_CR_DBI_WDATA_LEN) - 1) << DBI_CR_DBI_WDATA_POS) -#define DBI_CR_DBI_WDATA_UMSK (~(((1U << DBI_CR_DBI_WDATA_LEN) - 1) << DBI_CR_DBI_WDATA_POS)) - -/* 0x1C : dbi_rdata */ -#define DBI_RDATA_OFFSET (0x1C) -#define DBI_STS_DBI_RDATA DBI_STS_DBI_RDATA -#define DBI_STS_DBI_RDATA_POS (0U) -#define DBI_STS_DBI_RDATA_LEN (32U) -#define DBI_STS_DBI_RDATA_MSK (((1U << DBI_STS_DBI_RDATA_LEN) - 1) << DBI_STS_DBI_RDATA_POS) -#define DBI_STS_DBI_RDATA_UMSK (~(((1U << DBI_STS_DBI_RDATA_LEN) - 1) << DBI_STS_DBI_RDATA_POS)) - -/* 0x80 : dbi_fifo_config_0 */ -#define DBI_FIFO_CONFIG_0_OFFSET (0x80) -#define DBI_DMA_TX_EN DBI_DMA_TX_EN -#define DBI_DMA_TX_EN_POS (0U) -#define DBI_DMA_TX_EN_LEN (1U) -#define DBI_DMA_TX_EN_MSK (((1U << DBI_DMA_TX_EN_LEN) - 1) << DBI_DMA_TX_EN_POS) -#define DBI_DMA_TX_EN_UMSK (~(((1U << DBI_DMA_TX_EN_LEN) - 1) << DBI_DMA_TX_EN_POS)) -#define DBI_TX_FIFO_CLR DBI_TX_FIFO_CLR -#define DBI_TX_FIFO_CLR_POS (2U) -#define DBI_TX_FIFO_CLR_LEN (1U) -#define DBI_TX_FIFO_CLR_MSK (((1U << DBI_TX_FIFO_CLR_LEN) - 1) << DBI_TX_FIFO_CLR_POS) -#define DBI_TX_FIFO_CLR_UMSK (~(((1U << DBI_TX_FIFO_CLR_LEN) - 1) << DBI_TX_FIFO_CLR_POS)) -#define DBI_TX_FIFO_OVERFLOW DBI_TX_FIFO_OVERFLOW -#define DBI_TX_FIFO_OVERFLOW_POS (4U) -#define DBI_TX_FIFO_OVERFLOW_LEN (1U) -#define DBI_TX_FIFO_OVERFLOW_MSK (((1U << DBI_TX_FIFO_OVERFLOW_LEN) - 1) << DBI_TX_FIFO_OVERFLOW_POS) -#define DBI_TX_FIFO_OVERFLOW_UMSK (~(((1U << DBI_TX_FIFO_OVERFLOW_LEN) - 1) << DBI_TX_FIFO_OVERFLOW_POS)) -#define DBI_TX_FIFO_UNDERFLOW DBI_TX_FIFO_UNDERFLOW -#define DBI_TX_FIFO_UNDERFLOW_POS (5U) -#define DBI_TX_FIFO_UNDERFLOW_LEN (1U) -#define DBI_TX_FIFO_UNDERFLOW_MSK (((1U << DBI_TX_FIFO_UNDERFLOW_LEN) - 1) << DBI_TX_FIFO_UNDERFLOW_POS) -#define DBI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << DBI_TX_FIFO_UNDERFLOW_LEN) - 1) << DBI_TX_FIFO_UNDERFLOW_POS)) -#define DBI_FIFO_FORMAT DBI_FIFO_FORMAT -#define DBI_FIFO_FORMAT_POS (29U) -#define DBI_FIFO_FORMAT_LEN (3U) -#define DBI_FIFO_FORMAT_MSK (((1U << DBI_FIFO_FORMAT_LEN) - 1) << DBI_FIFO_FORMAT_POS) -#define DBI_FIFO_FORMAT_UMSK (~(((1U << DBI_FIFO_FORMAT_LEN) - 1) << DBI_FIFO_FORMAT_POS)) - -/* 0x84 : dbi_fifo_config_1 */ -#define DBI_FIFO_CONFIG_1_OFFSET (0x84) -#define DBI_TX_FIFO_CNT DBI_TX_FIFO_CNT -#define DBI_TX_FIFO_CNT_POS (0U) -#define DBI_TX_FIFO_CNT_LEN (4U) -#define DBI_TX_FIFO_CNT_MSK (((1U << DBI_TX_FIFO_CNT_LEN) - 1) << DBI_TX_FIFO_CNT_POS) -#define DBI_TX_FIFO_CNT_UMSK (~(((1U << DBI_TX_FIFO_CNT_LEN) - 1) << DBI_TX_FIFO_CNT_POS)) -#define DBI_TX_FIFO_TH DBI_TX_FIFO_TH -#define DBI_TX_FIFO_TH_POS (16U) -#define DBI_TX_FIFO_TH_LEN (3U) -#define DBI_TX_FIFO_TH_MSK (((1U << DBI_TX_FIFO_TH_LEN) - 1) << DBI_TX_FIFO_TH_POS) -#define DBI_TX_FIFO_TH_UMSK (~(((1U << DBI_TX_FIFO_TH_LEN) - 1) << DBI_TX_FIFO_TH_POS)) - -/* 0x88 : dbi_fifo_wdata */ -#define DBI_FIFO_WDATA_OFFSET (0x88) -#define DBI_FIFO_WDATA DBI_FIFO_WDATA -#define DBI_FIFO_WDATA_POS (0U) -#define DBI_FIFO_WDATA_LEN (32U) -#define DBI_FIFO_WDATA_MSK (((1U << DBI_FIFO_WDATA_LEN) - 1) << DBI_FIFO_WDATA_POS) -#define DBI_FIFO_WDATA_UMSK (~(((1U << DBI_FIFO_WDATA_LEN) - 1) << DBI_FIFO_WDATA_POS)) - -struct dbi_reg { - /* 0x0 : dbi_config */ - union { - struct { - uint32_t cr_dbi_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_dbi_sel : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_dbi_cmd_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_dbi_dat_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_dbi_dat_wr : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_dbi_dat_tp : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_dbi_dat_bc : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t cr_dbi_cmd : 8; /* [15: 8], r/w, 0x2c */ - uint32_t cr_dbi_scl_pol : 1; /* [ 16], r/w, 0x1 */ - uint32_t cr_dbi_scl_ph : 1; /* [ 17], r/w, 0x0 */ - uint32_t cr_dbi_cont_en : 1; /* [ 18], r/w, 0x1 */ - uint32_t cr_dbi_dmy_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t cr_dbi_dmy_cnt : 4; /* [23:20], r/w, 0x0 */ - uint32_t rsvd_26_24 : 3; /* [26:24], rsvd, 0x0 */ - uint32_t cr_dbi_tc_3w_mode : 1; /* [ 27], r/w, 0x0 */ - uint32_t cr_dbi_tc_deg_en : 1; /* [ 28], r/w, 0x0 */ - uint32_t cr_dbi_tc_deg_cnt : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_config; - - /* 0x4 : dbi_int_sts */ - union { - struct { - uint32_t dbi_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t dbi_txf_int : 1; /* [ 1], r, 0x1 */ - uint32_t dbi_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_dbi_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_dbi_txf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_dbi_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_dbi_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ - uint32_t cr_dbi_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_dbi_txf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_dbi_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbi_int_sts; - - /* 0x8 : dbi_bus_busy */ - union { - struct { - uint32_t sts_dbi_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbi_bus_busy; - - /* 0xC : dbi_pix_cnt */ - union { - struct { - uint32_t cr_dbi_pix_cnt : 24; /* [23: 0], r/w, 0x0 */ - uint32_t reserved_24_30 : 7; /* [30:24], rsvd, 0x0 */ - uint32_t cr_dbi_pix_format : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_pix_cnt; - - /* 0x10 : dbi_prd */ - union { - struct { - uint32_t cr_dbi_prd_s : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_dbi_prd_i : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_dbi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_dbi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } dbi_prd; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[4]; - - /* 0x18 : dbi_wdata */ - union { - struct { - uint32_t cr_dbi_wdata : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_wdata; - - /* 0x1C : dbi_rdata */ - union { - struct { - uint32_t sts_dbi_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } dbi_rdata; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[96]; - - /* 0x80 : dbi_fifo_config_0 */ - union { - struct { - uint32_t dbi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_28 : 23; /* [28: 6], rsvd, 0x0 */ - uint32_t fifo_format : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dbi_fifo_config_0; - - /* 0x84 : dbi_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 4; /* [ 3: 0], r, 0x8 */ - uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ - uint32_t tx_fifo_th : 3; /* [18:16], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dbi_fifo_config_1; - - /* 0x88 : dbi_fifo_wdata */ - union { - struct { - uint32_t dbi_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } dbi_fifo_wdata; -}; - -typedef volatile struct dbi_reg dbi_reg_t; - -#endif /* __DBI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma2d_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma2d_reg.h deleted file mode 100644 index ff2e90c3dd..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma2d_reg.h +++ /dev/null @@ -1,574 +0,0 @@ -/** - ****************************************************************************** - * @file dma2d_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DMA2D_REG_H__ -#define __DMA2D_REG_H__ - -#include "bl808.h" - -/* 0x0 : DMA_IntStatus */ -#define DMA2D_DMA_INTSTATUS_OFFSET (0x0) -#define DMA2D_INTSTATUS DMA2D_INTSTATUS -#define DMA2D_INTSTATUS_POS (0U) -#define DMA2D_INTSTATUS_LEN (8U) -#define DMA2D_INTSTATUS_MSK (((1U << DMA2D_INTSTATUS_LEN) - 1) << DMA2D_INTSTATUS_POS) -#define DMA2D_INTSTATUS_UMSK (~(((1U << DMA2D_INTSTATUS_LEN) - 1) << DMA2D_INTSTATUS_POS)) - -/* 0x4 : DMA_IntTCStatus */ -#define DMA2D_DMA_INTTCSTATUS_OFFSET (0x4) -#define DMA2D_INTTCSTATUS DMA2D_INTTCSTATUS -#define DMA2D_INTTCSTATUS_POS (0U) -#define DMA2D_INTTCSTATUS_LEN (8U) -#define DMA2D_INTTCSTATUS_MSK (((1U << DMA2D_INTTCSTATUS_LEN) - 1) << DMA2D_INTTCSTATUS_POS) -#define DMA2D_INTTCSTATUS_UMSK (~(((1U << DMA2D_INTTCSTATUS_LEN) - 1) << DMA2D_INTTCSTATUS_POS)) - -/* 0x8 : DMA_IntTCClear */ -#define DMA2D_DMA_INTTCCLEAR_OFFSET (0x8) -#define DMA2D_INTTCCLEAR DMA2D_INTTCCLEAR -#define DMA2D_INTTCCLEAR_POS (0U) -#define DMA2D_INTTCCLEAR_LEN (8U) -#define DMA2D_INTTCCLEAR_MSK (((1U << DMA2D_INTTCCLEAR_LEN) - 1) << DMA2D_INTTCCLEAR_POS) -#define DMA2D_INTTCCLEAR_UMSK (~(((1U << DMA2D_INTTCCLEAR_LEN) - 1) << DMA2D_INTTCCLEAR_POS)) - -/* 0xC : DMA_EnbldChns */ -#define DMA2D_DMA_ENBLDCHNS_OFFSET (0xC) -#define DMA2D_ENABLEDCHANNELS DMA2D_ENABLEDCHANNELS -#define DMA2D_ENABLEDCHANNELS_POS (0U) -#define DMA2D_ENABLEDCHANNELS_LEN (8U) -#define DMA2D_ENABLEDCHANNELS_MSK (((1U << DMA2D_ENABLEDCHANNELS_LEN) - 1) << DMA2D_ENABLEDCHANNELS_POS) -#define DMA2D_ENABLEDCHANNELS_UMSK (~(((1U << DMA2D_ENABLEDCHANNELS_LEN) - 1) << DMA2D_ENABLEDCHANNELS_POS)) - -/* 0x10 : DMA_Config */ -#define DMA2D_DMA_CONFIG_OFFSET (0x10) -#define DMA2D_E DMA2D_E -#define DMA2D_E_POS (0U) -#define DMA2D_E_LEN (1U) -#define DMA2D_E_MSK (((1U << DMA2D_E_LEN) - 1) << DMA2D_E_POS) -#define DMA2D_E_UMSK (~(((1U << DMA2D_E_LEN) - 1) << DMA2D_E_POS)) -#define DMA2D_CHCLKCG DMA2D_CHCLKCG -#define DMA2D_CHCLKCG_POS (16U) -#define DMA2D_CHCLKCG_LEN (8U) -#define DMA2D_CHCLKCG_MSK (((1U << DMA2D_CHCLKCG_LEN) - 1) << DMA2D_CHCLKCG_POS) -#define DMA2D_CHCLKCG_UMSK (~(((1U << DMA2D_CHCLKCG_LEN) - 1) << DMA2D_CHCLKCG_POS)) - -/* 0x14 : DMA_Sync */ -#define DMA2D_DMA_SYNC_OFFSET (0x14) -#define DMA2D_DMA_SYNC DMA2D_DMA_SYNC -#define DMA2D_DMA_SYNC_POS (0U) -#define DMA2D_DMA_SYNC_LEN (32U) -#define DMA2D_DMA_SYNC_MSK (((1U << DMA2D_DMA_SYNC_LEN) - 1) << DMA2D_DMA_SYNC_POS) -#define DMA2D_DMA_SYNC_UMSK (~(((1U << DMA2D_DMA_SYNC_LEN) - 1) << DMA2D_DMA_SYNC_POS)) - -/* 0x18 : DMA_SoftBReq */ -#define DMA2D_DMA_SOFTBREQ_OFFSET (0x18) -#define DMA2D_SOFTBREQ DMA2D_SOFTBREQ -#define DMA2D_SOFTBREQ_POS (0U) -#define DMA2D_SOFTBREQ_LEN (32U) -#define DMA2D_SOFTBREQ_MSK (((1U << DMA2D_SOFTBREQ_LEN) - 1) << DMA2D_SOFTBREQ_POS) -#define DMA2D_SOFTBREQ_UMSK (~(((1U << DMA2D_SOFTBREQ_LEN) - 1) << DMA2D_SOFTBREQ_POS)) - -/* 0x1C : DMA_SoftLBReq */ -#define DMA2D_DMA_SOFTLBREQ_OFFSET (0x1C) -#define DMA2D_SOFTLBREQ DMA2D_SOFTLBREQ -#define DMA2D_SOFTLBREQ_POS (0U) -#define DMA2D_SOFTLBREQ_LEN (32U) -#define DMA2D_SOFTLBREQ_MSK (((1U << DMA2D_SOFTLBREQ_LEN) - 1) << DMA2D_SOFTLBREQ_POS) -#define DMA2D_SOFTLBREQ_UMSK (~(((1U << DMA2D_SOFTLBREQ_LEN) - 1) << DMA2D_SOFTLBREQ_POS)) - -/* 0x20 : DMA_SoftSReq */ -#define DMA2D_DMA_SOFTSREQ_OFFSET (0x20) -#define DMA2D_SOFTSREQ DMA2D_SOFTSREQ -#define DMA2D_SOFTSREQ_POS (0U) -#define DMA2D_SOFTSREQ_LEN (32U) -#define DMA2D_SOFTSREQ_MSK (((1U << DMA2D_SOFTSREQ_LEN) - 1) << DMA2D_SOFTSREQ_POS) -#define DMA2D_SOFTSREQ_UMSK (~(((1U << DMA2D_SOFTSREQ_LEN) - 1) << DMA2D_SOFTSREQ_POS)) - -/* 0x24 : DMA_SoftLSReq */ -#define DMA2D_DMA_SOFTLSREQ_OFFSET (0x24) -#define DMA2D_SOFTLSREQ DMA2D_SOFTLSREQ -#define DMA2D_SOFTLSREQ_POS (0U) -#define DMA2D_SOFTLSREQ_LEN (32U) -#define DMA2D_SOFTLSREQ_MSK (((1U << DMA2D_SOFTLSREQ_LEN) - 1) << DMA2D_SOFTLSREQ_POS) -#define DMA2D_SOFTLSREQ_UMSK (~(((1U << DMA2D_SOFTLSREQ_LEN) - 1) << DMA2D_SOFTLSREQ_POS)) - -/* 0x100 : DMA2D_C0SrcAddr */ -#define DMA2D_C0SRCADDR_OFFSET (0x100) -#define DMA2D_SRCADDR DMA2D_SRCADDR -#define DMA2D_SRCADDR_POS (0U) -#define DMA2D_SRCADDR_LEN (32U) -#define DMA2D_SRCADDR_MSK (((1U << DMA2D_SRCADDR_LEN) - 1) << DMA2D_SRCADDR_POS) -#define DMA2D_SRCADDR_UMSK (~(((1U << DMA2D_SRCADDR_LEN) - 1) << DMA2D_SRCADDR_POS)) - -/* 0x104 : DMA2D_C0DstAddr */ -#define DMA2D_C0DSTADDR_OFFSET (0x104) -#define DMA2D_DSTADDR DMA2D_DSTADDR -#define DMA2D_DSTADDR_POS (0U) -#define DMA2D_DSTADDR_LEN (32U) -#define DMA2D_DSTADDR_MSK (((1U << DMA2D_DSTADDR_LEN) - 1) << DMA2D_DSTADDR_POS) -#define DMA2D_DSTADDR_UMSK (~(((1U << DMA2D_DSTADDR_LEN) - 1) << DMA2D_DSTADDR_POS)) - -/* 0x108 : DMA2D_C0LLI */ -#define DMA2D_C0LLI_OFFSET (0x108) -#define DMA2D_LLI_EN DMA2D_LLI_EN -#define DMA2D_LLI_EN_POS (0U) -#define DMA2D_LLI_EN_LEN (1U) -#define DMA2D_LLI_EN_MSK (((1U << DMA2D_LLI_EN_LEN) - 1) << DMA2D_LLI_EN_POS) -#define DMA2D_LLI_EN_UMSK (~(((1U << DMA2D_LLI_EN_LEN) - 1) << DMA2D_LLI_EN_POS)) -#define DMA2D_LLI_ADDR DMA2D_LLI_ADDR -#define DMA2D_LLI_ADDR_POS (2U) -#define DMA2D_LLI_ADDR_LEN (30U) -#define DMA2D_LLI_ADDR_MSK (((1U << DMA2D_LLI_ADDR_LEN) - 1) << DMA2D_LLI_ADDR_POS) -#define DMA2D_LLI_ADDR_UMSK (~(((1U << DMA2D_LLI_ADDR_LEN) - 1) << DMA2D_LLI_ADDR_POS)) - -/* 0x10C : DMA2D_C0_BUS */ -#define DMA2D_C0_BUS_OFFSET (0x10C) -#define DMA2D_TRANSFERSIZE DMA2D_TRANSFERSIZE -#define DMA2D_TRANSFERSIZE_POS (0U) -#define DMA2D_TRANSFERSIZE_LEN (12U) -#define DMA2D_TRANSFERSIZE_MSK (((1U << DMA2D_TRANSFERSIZE_LEN) - 1) << DMA2D_TRANSFERSIZE_POS) -#define DMA2D_TRANSFERSIZE_UMSK (~(((1U << DMA2D_TRANSFERSIZE_LEN) - 1) << DMA2D_TRANSFERSIZE_POS)) -#define DMA2D_SRC_BURST DMA2D_SRC_BURST -#define DMA2D_SRC_BURST_POS (12U) -#define DMA2D_SRC_BURST_LEN (2U) -#define DMA2D_SRC_BURST_MSK (((1U << DMA2D_SRC_BURST_LEN) - 1) << DMA2D_SRC_BURST_POS) -#define DMA2D_SRC_BURST_UMSK (~(((1U << DMA2D_SRC_BURST_LEN) - 1) << DMA2D_SRC_BURST_POS)) -#define DMA2D_DST_BURST DMA2D_DST_BURST -#define DMA2D_DST_BURST_POS (15U) -#define DMA2D_DST_BURST_LEN (2U) -#define DMA2D_DST_BURST_MSK (((1U << DMA2D_DST_BURST_LEN) - 1) << DMA2D_DST_BURST_POS) -#define DMA2D_DST_BURST_UMSK (~(((1U << DMA2D_DST_BURST_LEN) - 1) << DMA2D_DST_BURST_POS)) -#define DMA2D_SRC_SIZE DMA2D_SRC_SIZE -#define DMA2D_SRC_SIZE_POS (18U) -#define DMA2D_SRC_SIZE_LEN (2U) -#define DMA2D_SRC_SIZE_MSK (((1U << DMA2D_SRC_SIZE_LEN) - 1) << DMA2D_SRC_SIZE_POS) -#define DMA2D_SRC_SIZE_UMSK (~(((1U << DMA2D_SRC_SIZE_LEN) - 1) << DMA2D_SRC_SIZE_POS)) -#define DMA2D_DST_SIZE DMA2D_DST_SIZE -#define DMA2D_DST_SIZE_POS (21U) -#define DMA2D_DST_SIZE_LEN (2U) -#define DMA2D_DST_SIZE_MSK (((1U << DMA2D_DST_SIZE_LEN) - 1) << DMA2D_DST_SIZE_POS) -#define DMA2D_DST_SIZE_UMSK (~(((1U << DMA2D_DST_SIZE_LEN) - 1) << DMA2D_DST_SIZE_POS)) -#define DMA2D_SI DMA2D_SI -#define DMA2D_SI_POS (26U) -#define DMA2D_SI_LEN (1U) -#define DMA2D_SI_MSK (((1U << DMA2D_SI_LEN) - 1) << DMA2D_SI_POS) -#define DMA2D_SI_UMSK (~(((1U << DMA2D_SI_LEN) - 1) << DMA2D_SI_POS)) -#define DMA2D_DI DMA2D_DI -#define DMA2D_DI_POS (27U) -#define DMA2D_DI_LEN (1U) -#define DMA2D_DI_MSK (((1U << DMA2D_DI_LEN) - 1) << DMA2D_DI_POS) -#define DMA2D_DI_UMSK (~(((1U << DMA2D_DI_LEN) - 1) << DMA2D_DI_POS)) -#define DMA2D_PROT DMA2D_PROT -#define DMA2D_PROT_POS (28U) -#define DMA2D_PROT_LEN (3U) -#define DMA2D_PROT_MSK (((1U << DMA2D_PROT_LEN) - 1) << DMA2D_PROT_POS) -#define DMA2D_PROT_UMSK (~(((1U << DMA2D_PROT_LEN) - 1) << DMA2D_PROT_POS)) -#define DMA2D_I DMA2D_I -#define DMA2D_I_POS (31U) -#define DMA2D_I_LEN (1U) -#define DMA2D_I_MSK (((1U << DMA2D_I_LEN) - 1) << DMA2D_I_POS) -#define DMA2D_I_UMSK (~(((1U << DMA2D_I_LEN) - 1) << DMA2D_I_POS)) - -/* 0x110 : DMA2D_C0_SRC_CNT */ -#define DMA2D_C0_SRC_CNT_OFFSET (0x110) -#define DMA2D_SRC_X_CNT DMA2D_SRC_X_CNT -#define DMA2D_SRC_X_CNT_POS (0U) -#define DMA2D_SRC_X_CNT_LEN (16U) -#define DMA2D_SRC_X_CNT_MSK (((1U << DMA2D_SRC_X_CNT_LEN) - 1) << DMA2D_SRC_X_CNT_POS) -#define DMA2D_SRC_X_CNT_UMSK (~(((1U << DMA2D_SRC_X_CNT_LEN) - 1) << DMA2D_SRC_X_CNT_POS)) -#define DMA2D_SRC_Y_CNT DMA2D_SRC_Y_CNT -#define DMA2D_SRC_Y_CNT_POS (16U) -#define DMA2D_SRC_Y_CNT_LEN (16U) -#define DMA2D_SRC_Y_CNT_MSK (((1U << DMA2D_SRC_Y_CNT_LEN) - 1) << DMA2D_SRC_Y_CNT_POS) -#define DMA2D_SRC_Y_CNT_UMSK (~(((1U << DMA2D_SRC_Y_CNT_LEN) - 1) << DMA2D_SRC_Y_CNT_POS)) - -/* 0x114 : DMA2D_C0_SRC_XIC */ -#define DMA2D_C0_SRC_XIC_OFFSET (0x114) -#define DMA2D_SRC_X_INCR DMA2D_SRC_X_INCR -#define DMA2D_SRC_X_INCR_POS (0U) -#define DMA2D_SRC_X_INCR_LEN (32U) -#define DMA2D_SRC_X_INCR_MSK (((1U << DMA2D_SRC_X_INCR_LEN) - 1) << DMA2D_SRC_X_INCR_POS) -#define DMA2D_SRC_X_INCR_UMSK (~(((1U << DMA2D_SRC_X_INCR_LEN) - 1) << DMA2D_SRC_X_INCR_POS)) - -/* 0x118 : DMA2D_C0_SRC_YIC */ -#define DMA2D_C0_SRC_YIC_OFFSET (0x118) -#define DMA2D_SRC_Y_INCR DMA2D_SRC_Y_INCR -#define DMA2D_SRC_Y_INCR_POS (0U) -#define DMA2D_SRC_Y_INCR_LEN (32U) -#define DMA2D_SRC_Y_INCR_MSK (((1U << DMA2D_SRC_Y_INCR_LEN) - 1) << DMA2D_SRC_Y_INCR_POS) -#define DMA2D_SRC_Y_INCR_UMSK (~(((1U << DMA2D_SRC_Y_INCR_LEN) - 1) << DMA2D_SRC_Y_INCR_POS)) - -/* 0x11C : DMA2D_C0_DST_CNT */ -#define DMA2D_C0_DST_CNT_OFFSET (0x11C) -#define DMA2D_DST_X_CNT DMA2D_DST_X_CNT -#define DMA2D_DST_X_CNT_POS (0U) -#define DMA2D_DST_X_CNT_LEN (16U) -#define DMA2D_DST_X_CNT_MSK (((1U << DMA2D_DST_X_CNT_LEN) - 1) << DMA2D_DST_X_CNT_POS) -#define DMA2D_DST_X_CNT_UMSK (~(((1U << DMA2D_DST_X_CNT_LEN) - 1) << DMA2D_DST_X_CNT_POS)) - -/* 0x120 : DMA2D_C0_DST_XIC */ -#define DMA2D_C0_DST_XIC_OFFSET (0x120) -#define DMA2D_DST_X_INCR DMA2D_DST_X_INCR -#define DMA2D_DST_X_INCR_POS (0U) -#define DMA2D_DST_X_INCR_LEN (32U) -#define DMA2D_DST_X_INCR_MSK (((1U << DMA2D_DST_X_INCR_LEN) - 1) << DMA2D_DST_X_INCR_POS) -#define DMA2D_DST_X_INCR_UMSK (~(((1U << DMA2D_DST_X_INCR_LEN) - 1) << DMA2D_DST_X_INCR_POS)) - -/* 0x124 : DMA2D_C0_DST_YIC */ -#define DMA2D_C0_DST_YIC_OFFSET (0x124) -#define DMA2D_DST_Y_INCR DMA2D_DST_Y_INCR -#define DMA2D_DST_Y_INCR_POS (0U) -#define DMA2D_DST_Y_INCR_LEN (32U) -#define DMA2D_DST_Y_INCR_MSK (((1U << DMA2D_DST_Y_INCR_LEN) - 1) << DMA2D_DST_Y_INCR_POS) -#define DMA2D_DST_Y_INCR_UMSK (~(((1U << DMA2D_DST_Y_INCR_LEN) - 1) << DMA2D_DST_Y_INCR_POS)) - -/* 0x174 : DMA2D_C0_KEY */ -#define DMA2D_C0_KEY_OFFSET (0x174) -#define DMA2D_KEY0 DMA2D_KEY0 -#define DMA2D_KEY0_POS (0U) -#define DMA2D_KEY0_LEN (8U) -#define DMA2D_KEY0_MSK (((1U << DMA2D_KEY0_LEN) - 1) << DMA2D_KEY0_POS) -#define DMA2D_KEY0_UMSK (~(((1U << DMA2D_KEY0_LEN) - 1) << DMA2D_KEY0_POS)) -#define DMA2D_KEY1 DMA2D_KEY1 -#define DMA2D_KEY1_POS (8U) -#define DMA2D_KEY1_LEN (8U) -#define DMA2D_KEY1_MSK (((1U << DMA2D_KEY1_LEN) - 1) << DMA2D_KEY1_POS) -#define DMA2D_KEY1_UMSK (~(((1U << DMA2D_KEY1_LEN) - 1) << DMA2D_KEY1_POS)) -#define DMA2D_KEY2 DMA2D_KEY2 -#define DMA2D_KEY2_POS (16U) -#define DMA2D_KEY2_LEN (8U) -#define DMA2D_KEY2_MSK (((1U << DMA2D_KEY2_LEN) - 1) << DMA2D_KEY2_POS) -#define DMA2D_KEY2_UMSK (~(((1U << DMA2D_KEY2_LEN) - 1) << DMA2D_KEY2_POS)) -#define DMA2D_KEY3 DMA2D_KEY3 -#define DMA2D_KEY3_POS (24U) -#define DMA2D_KEY3_LEN (8U) -#define DMA2D_KEY3_MSK (((1U << DMA2D_KEY3_LEN) - 1) << DMA2D_KEY3_POS) -#define DMA2D_KEY3_UMSK (~(((1U << DMA2D_KEY3_LEN) - 1) << DMA2D_KEY3_POS)) - -/* 0x178 : DMA2D_C0_KEY_EN */ -#define DMA2D_C0_KEY_EN_OFFSET (0x178) -#define DMA2D_KEY_EN DMA2D_KEY_EN -#define DMA2D_KEY_EN_POS (0U) -#define DMA2D_KEY_EN_LEN (1U) -#define DMA2D_KEY_EN_MSK (((1U << DMA2D_KEY_EN_LEN) - 1) << DMA2D_KEY_EN_POS) -#define DMA2D_KEY_EN_UMSK (~(((1U << DMA2D_KEY_EN_LEN) - 1) << DMA2D_KEY_EN_POS)) -#define DMA2D_KEY_MODE DMA2D_KEY_MODE -#define DMA2D_KEY_MODE_POS (1U) -#define DMA2D_KEY_MODE_LEN (2U) -#define DMA2D_KEY_MODE_MSK (((1U << DMA2D_KEY_MODE_LEN) - 1) << DMA2D_KEY_MODE_POS) -#define DMA2D_KEY_MODE_UMSK (~(((1U << DMA2D_KEY_MODE_LEN) - 1) << DMA2D_KEY_MODE_POS)) -#define DMA2D_KEY_STRB DMA2D_KEY_STRB -#define DMA2D_KEY_STRB_POS (4U) -#define DMA2D_KEY_STRB_LEN (4U) -#define DMA2D_KEY_STRB_MSK (((1U << DMA2D_KEY_STRB_LEN) - 1) << DMA2D_KEY_STRB_POS) -#define DMA2D_KEY_STRB_UMSK (~(((1U << DMA2D_KEY_STRB_LEN) - 1) << DMA2D_KEY_STRB_POS)) - -/* 0x17C : DMA2D_C0_CFG */ -#define DMA2D_C0_CFG_OFFSET (0x17C) -#define DMA2D_CH_EN DMA2D_CH_EN -#define DMA2D_CH_EN_POS (0U) -#define DMA2D_CH_EN_LEN (1U) -#define DMA2D_CH_EN_MSK (((1U << DMA2D_CH_EN_LEN) - 1) << DMA2D_CH_EN_POS) -#define DMA2D_CH_EN_UMSK (~(((1U << DMA2D_CH_EN_LEN) - 1) << DMA2D_CH_EN_POS)) -#define DMA2D_SRCPERIPHERAL DMA2D_SRCPERIPHERAL -#define DMA2D_SRCPERIPHERAL_POS (1U) -#define DMA2D_SRCPERIPHERAL_LEN (5U) -#define DMA2D_SRCPERIPHERAL_MSK (((1U << DMA2D_SRCPERIPHERAL_LEN) - 1) << DMA2D_SRCPERIPHERAL_POS) -#define DMA2D_SRCPERIPHERAL_UMSK (~(((1U << DMA2D_SRCPERIPHERAL_LEN) - 1) << DMA2D_SRCPERIPHERAL_POS)) -#define DMA2D_DSTPERIPHERAL DMA2D_DSTPERIPHERAL -#define DMA2D_DSTPERIPHERAL_POS (6U) -#define DMA2D_DSTPERIPHERAL_LEN (5U) -#define DMA2D_DSTPERIPHERAL_MSK (((1U << DMA2D_DSTPERIPHERAL_LEN) - 1) << DMA2D_DSTPERIPHERAL_POS) -#define DMA2D_DSTPERIPHERAL_UMSK (~(((1U << DMA2D_DSTPERIPHERAL_LEN) - 1) << DMA2D_DSTPERIPHERAL_POS)) -#define DMA2D_FLOWCNTRL DMA2D_FLOWCNTRL -#define DMA2D_FLOWCNTRL_POS (11U) -#define DMA2D_FLOWCNTRL_LEN (3U) -#define DMA2D_FLOWCNTRL_MSK (((1U << DMA2D_FLOWCNTRL_LEN) - 1) << DMA2D_FLOWCNTRL_POS) -#define DMA2D_FLOWCNTRL_UMSK (~(((1U << DMA2D_FLOWCNTRL_LEN) - 1) << DMA2D_FLOWCNTRL_POS)) -#define DMA2D_AHB_B2B DMA2D_AHB_B2B -#define DMA2D_AHB_B2B_POS (14U) -#define DMA2D_AHB_B2B_LEN (1U) -#define DMA2D_AHB_B2B_MSK (((1U << DMA2D_AHB_B2B_LEN) - 1) << DMA2D_AHB_B2B_POS) -#define DMA2D_AHB_B2B_UMSK (~(((1U << DMA2D_AHB_B2B_LEN) - 1) << DMA2D_AHB_B2B_POS)) -#define DMA2D_FIFO_EMPTY DMA2D_FIFO_EMPTY -#define DMA2D_FIFO_EMPTY_POS (16U) -#define DMA2D_FIFO_EMPTY_LEN (1U) -#define DMA2D_FIFO_EMPTY_MSK (((1U << DMA2D_FIFO_EMPTY_LEN) - 1) << DMA2D_FIFO_EMPTY_POS) -#define DMA2D_FIFO_EMPTY_UMSK (~(((1U << DMA2D_FIFO_EMPTY_LEN) - 1) << DMA2D_FIFO_EMPTY_POS)) -#define DMA2D_LLICOUNTER DMA2D_LLICOUNTER -#define DMA2D_LLICOUNTER_POS (20U) -#define DMA2D_LLICOUNTER_LEN (10U) -#define DMA2D_LLICOUNTER_MSK (((1U << DMA2D_LLICOUNTER_LEN) - 1) << DMA2D_LLICOUNTER_POS) -#define DMA2D_LLICOUNTER_UMSK (~(((1U << DMA2D_LLICOUNTER_LEN) - 1) << DMA2D_LLICOUNTER_POS)) -#define DMA2D_REG_DMA_2D_EN DMA2D_REG_DMA_2D_EN -#define DMA2D_REG_DMA_2D_EN_POS (31U) -#define DMA2D_REG_DMA_2D_EN_LEN (1U) -#define DMA2D_REG_DMA_2D_EN_MSK (((1U << DMA2D_REG_DMA_2D_EN_LEN) - 1) << DMA2D_REG_DMA_2D_EN_POS) -#define DMA2D_REG_DMA_2D_EN_UMSK (~(((1U << DMA2D_REG_DMA_2D_EN_LEN) - 1) << DMA2D_REG_DMA_2D_EN_POS)) - -struct dma2d_reg { - /* 0x0 : DMA_IntStatus */ - union { - struct { - uint32_t IntStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntStatus; - - /* 0x4 : DMA_IntTCStatus */ - union { - struct { - uint32_t IntTCStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCStatus; - - /* 0x8 : DMA_IntTCClear */ - union { - struct { - uint32_t IntTCClear : 8; /* [ 7: 0], w1p, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCClear; - - /* 0xC : DMA_EnbldChns */ - union { - struct { - uint32_t EnabledChannels : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_EnbldChns; - - /* 0x10 : DMA_Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ - uint32_t ChClkCG : 8; /* [23:16], r/w, 0xff */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Config; - - /* 0x14 : DMA_Sync */ - union { - struct { - uint32_t DMA_Sync : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Sync; - - /* 0x18 : DMA_SoftBReq */ - union { - struct { - uint32_t SoftBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftBReq; - - /* 0x1C : DMA_SoftLBReq */ - union { - struct { - uint32_t SoftLBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLBReq; - - /* 0x20 : DMA_SoftSReq */ - union { - struct { - uint32_t SoftSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftSReq; - - /* 0x24 : DMA_SoftLSReq */ - union { - struct { - uint32_t SoftLSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLSReq; - - /* 0x28 reserved */ - uint8_t RESERVED0x28[216]; - - /* 0x100 : DMA2D_C0SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0SrcAddr; - - /* 0x104 : DMA2D_C0DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0DstAddr; - - /* 0x108 : DMA2D_C0LLI */ - union { - struct { - uint32_t LLI_EN : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t LLI_ADDR : 30; /* [31: 2], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0LLI; - - /* 0x10C : DMA2D_C0_BUS */ - union { - struct DMA2D_Control_Reg { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SRC_BURST : 2; /* [13:12], r/w, 0x1 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t DST_BURST : 2; /* [16:15], r/w, 0x1 */ - uint32_t reserved_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t SRC_SIZE : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DST_SIZE : 2; /* [22:21], r/w, 0x2 */ - uint32_t reserved_23_25 : 3; /* [25:23], rsvd, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_BUS; - - /* 0x110 : DMA2D_C0_SRC_CNT */ - union { - struct { - uint32_t SRC_X_CNT : 16; /* [15: 0], r/w, 0x0 */ - uint32_t SRC_Y_CNT : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_SRC_CNT; - - /* 0x114 : DMA2D_C0_SRC_XIC */ - union { - struct { - uint32_t SRC_X_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_SRC_XIC; - - /* 0x118 : DMA2D_C0_SRC_YIC */ - union { - struct { - uint32_t SRC_Y_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_SRC_YIC; - - /* 0x11C : DMA2D_C0_DST_CNT */ - union { - struct { - uint32_t DST_X_CNT : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_DST_CNT; - - /* 0x120 : DMA2D_C0_DST_XIC */ - union { - struct { - uint32_t DST_X_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_DST_XIC; - - /* 0x124 : DMA2D_C0_DST_YIC */ - union { - struct { - uint32_t DST_Y_INCR : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_DST_YIC; - - /* 0x128 reserved */ - uint8_t RESERVED0x128[76]; - - /* 0x174 : DMA2D_C0_KEY */ - union { - struct { - uint32_t KEY0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t KEY1 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t KEY2 : 8; /* [23:16], r/w, 0x0 */ - uint32_t KEY3 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_KEY; - - /* 0x178 : DMA2D_C0_KEY_EN */ - union { - struct { - uint32_t KEY_EN : 1; /* [ 0], r/w, 0x0 */ - uint32_t KEY_MODE : 2; /* [ 2: 1], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t KEY_STRB : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_KEY_EN; - - /* 0x17C : DMA2D_C0_CFG */ - union { - struct { - uint32_t CH_EN : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t AHB_B2B : 1; /* [ 14], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t FIFO_Empty : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ - uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ - uint32_t reg_dma_2d_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA2D_C0_CFG; -}; - -typedef volatile struct dma2d_reg dma2d_reg_t; - -#endif /* __DMA2D_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma_reg.h deleted file mode 100644 index 9c544259b5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dma_reg.h +++ /dev/null @@ -1,2084 +0,0 @@ -/** - ****************************************************************************** - * @file dma_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DMA_REG_H__ -#define __DMA_REG_H__ - -#include "bl808.h" - -/* 0x0 : DMA_IntStatus */ -#define DMA_INTSTATUS_OFFSET (0x0) -#define DMA_INTSTATUS DMA_INTSTATUS -#define DMA_INTSTATUS_POS (0U) -#define DMA_INTSTATUS_LEN (8U) -#define DMA_INTSTATUS_MSK (((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS) -#define DMA_INTSTATUS_UMSK (~(((1U << DMA_INTSTATUS_LEN) - 1) << DMA_INTSTATUS_POS)) - -/* 0x4 : DMA_IntTCStatus */ -#define DMA_INTTCSTATUS_OFFSET (0x4) -#define DMA_INTTCSTATUS DMA_INTTCSTATUS -#define DMA_INTTCSTATUS_POS (0U) -#define DMA_INTTCSTATUS_LEN (8U) -#define DMA_INTTCSTATUS_MSK (((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS) -#define DMA_INTTCSTATUS_UMSK (~(((1U << DMA_INTTCSTATUS_LEN) - 1) << DMA_INTTCSTATUS_POS)) - -/* 0x8 : DMA_IntTCClear */ -#define DMA_INTTCCLEAR_OFFSET (0x8) -#define DMA_INTTCCLEAR DMA_INTTCCLEAR -#define DMA_INTTCCLEAR_POS (0U) -#define DMA_INTTCCLEAR_LEN (8U) -#define DMA_INTTCCLEAR_MSK (((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS) -#define DMA_INTTCCLEAR_UMSK (~(((1U << DMA_INTTCCLEAR_LEN) - 1) << DMA_INTTCCLEAR_POS)) - -/* 0xC : DMA_IntErrorStatus */ -#define DMA_INTERRORSTATUS_OFFSET (0xC) -#define DMA_INTERRORSTATUS DMA_INTERRORSTATUS -#define DMA_INTERRORSTATUS_POS (0U) -#define DMA_INTERRORSTATUS_LEN (8U) -#define DMA_INTERRORSTATUS_MSK (((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS) -#define DMA_INTERRORSTATUS_UMSK (~(((1U << DMA_INTERRORSTATUS_LEN) - 1) << DMA_INTERRORSTATUS_POS)) - -/* 0x10 : DMA_IntErrClr */ -#define DMA_INTERRCLR_OFFSET (0x10) -#define DMA_INTERRCLR DMA_INTERRCLR -#define DMA_INTERRCLR_POS (0U) -#define DMA_INTERRCLR_LEN (8U) -#define DMA_INTERRCLR_MSK (((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS) -#define DMA_INTERRCLR_UMSK (~(((1U << DMA_INTERRCLR_LEN) - 1) << DMA_INTERRCLR_POS)) - -/* 0x14 : DMA_RawIntTCStatus */ -#define DMA_RAWINTTCSTATUS_OFFSET (0x14) -#define DMA_RAWINTTCSTATUS DMA_RAWINTTCSTATUS -#define DMA_RAWINTTCSTATUS_POS (0U) -#define DMA_RAWINTTCSTATUS_LEN (8U) -#define DMA_RAWINTTCSTATUS_MSK (((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS) -#define DMA_RAWINTTCSTATUS_UMSK (~(((1U << DMA_RAWINTTCSTATUS_LEN) - 1) << DMA_RAWINTTCSTATUS_POS)) - -/* 0x18 : DMA_RawIntErrorStatus */ -#define DMA_RAWINTERRORSTATUS_OFFSET (0x18) -#define DMA_RAWINTERRORSTATUS DMA_RAWINTERRORSTATUS -#define DMA_RAWINTERRORSTATUS_POS (0U) -#define DMA_RAWINTERRORSTATUS_LEN (8U) -#define DMA_RAWINTERRORSTATUS_MSK (((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS) -#define DMA_RAWINTERRORSTATUS_UMSK (~(((1U << DMA_RAWINTERRORSTATUS_LEN) - 1) << DMA_RAWINTERRORSTATUS_POS)) - -/* 0x1C : DMA_EnbldChns */ -#define DMA_ENBLDCHNS_OFFSET (0x1C) -#define DMA_ENABLEDCHANNELS DMA_ENABLEDCHANNELS -#define DMA_ENABLEDCHANNELS_POS (0U) -#define DMA_ENABLEDCHANNELS_LEN (8U) -#define DMA_ENABLEDCHANNELS_MSK (((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS) -#define DMA_ENABLEDCHANNELS_UMSK (~(((1U << DMA_ENABLEDCHANNELS_LEN) - 1) << DMA_ENABLEDCHANNELS_POS)) - -/* 0x20 : DMA_SoftBReq */ -#define DMA_SOFTBREQ_OFFSET (0x20) -#define DMA_SOFTBREQ DMA_SOFTBREQ -#define DMA_SOFTBREQ_POS (0U) -#define DMA_SOFTBREQ_LEN (32U) -#define DMA_SOFTBREQ_MSK (((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS) -#define DMA_SOFTBREQ_UMSK (~(((1U << DMA_SOFTBREQ_LEN) - 1) << DMA_SOFTBREQ_POS)) - -/* 0x24 : DMA_SoftSReq */ -#define DMA_SOFTSREQ_OFFSET (0x24) -#define DMA_SOFTSREQ DMA_SOFTSREQ -#define DMA_SOFTSREQ_POS (0U) -#define DMA_SOFTSREQ_LEN (32U) -#define DMA_SOFTSREQ_MSK (((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS) -#define DMA_SOFTSREQ_UMSK (~(((1U << DMA_SOFTSREQ_LEN) - 1) << DMA_SOFTSREQ_POS)) - -/* 0x28 : DMA_SoftLBReq */ -#define DMA_SOFTLBREQ_OFFSET (0x28) -#define DMA_SOFTLBREQ DMA_SOFTLBREQ -#define DMA_SOFTLBREQ_POS (0U) -#define DMA_SOFTLBREQ_LEN (32U) -#define DMA_SOFTLBREQ_MSK (((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS) -#define DMA_SOFTLBREQ_UMSK (~(((1U << DMA_SOFTLBREQ_LEN) - 1) << DMA_SOFTLBREQ_POS)) - -/* 0x2C : DMA_SoftLSReq */ -#define DMA_SOFTLSREQ_OFFSET (0x2C) -#define DMA_SOFTLSREQ DMA_SOFTLSREQ -#define DMA_SOFTLSREQ_POS (0U) -#define DMA_SOFTLSREQ_LEN (32U) -#define DMA_SOFTLSREQ_MSK (((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS) -#define DMA_SOFTLSREQ_UMSK (~(((1U << DMA_SOFTLSREQ_LEN) - 1) << DMA_SOFTLSREQ_POS)) - -/* 0x30 : DMA_Top_Config */ -#define DMA_TOP_CONFIG_OFFSET (0x30) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_M DMA_M -#define DMA_M_POS (1U) -#define DMA_M_LEN (1U) -#define DMA_M_MSK (((1U << DMA_M_LEN) - 1) << DMA_M_POS) -#define DMA_M_UMSK (~(((1U << DMA_M_LEN) - 1) << DMA_M_POS)) - -/* 0x34 : DMA_Sync */ -#define DMA_SYNC_OFFSET (0x34) -#define DMA_SYNC DMA_SYNC -#define DMA_SYNC_POS (0U) -#define DMA_SYNC_LEN (32U) -#define DMA_SYNC_MSK (((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS) -#define DMA_SYNC_UMSK (~(((1U << DMA_SYNC_LEN) - 1) << DMA_SYNC_POS)) - -/* 0x100 : DMA_C0SrcAddr */ -#define DMA_C0SRCADDR_OFFSET (0x100) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x104 : DMA_C0DstAddr */ -#define DMA_C0DSTADDR_OFFSET (0x104) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x108 : DMA_C0LLI */ -#define DMA_C0LLI_OFFSET (0x108) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x10C : DMA_C0Control */ -#define DMA_C0CONTROL_OFFSET (0x10C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x110 : DMA_C0Config */ -#define DMA_C0CONFIG_OFFSET (0x110) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) -#define DMA_LLICOUNTER DMA_LLICOUNTER -#define DMA_LLICOUNTER_POS (20U) -#define DMA_LLICOUNTER_LEN (10U) -#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) -#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) - -/* 0x11C : DMA_C0RSVD */ -#define DMA_C0RSVD_OFFSET (0x11C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x200 : DMA_C1SrcAddr */ -#define DMA_C1SRCADDR_OFFSET (0x200) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x204 : DMA_C1DstAddr */ -#define DMA_C1DSTADDR_OFFSET (0x204) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x208 : DMA_C1LLI */ -#define DMA_C1LLI_OFFSET (0x208) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x20C : DMA_C1Control */ -#define DMA_C1CONTROL_OFFSET (0x20C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x210 : DMA_C1Config */ -#define DMA_C1CONFIG_OFFSET (0x210) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x21C : DMA_C1RSVD */ -#define DMA_C1RSVD_OFFSET (0x21C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x300 : DMA_C2SrcAddr */ -#define DMA_C2SRCADDR_OFFSET (0x300) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x304 : DMA_C2DstAddr */ -#define DMA_C2DSTADDR_OFFSET (0x304) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x308 : DMA_C2LLI */ -#define DMA_C2LLI_OFFSET (0x308) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x30C : DMA_C2Control */ -#define DMA_C2CONTROL_OFFSET (0x30C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x310 : DMA_C3Config */ -#define DMA_C3CONFIG_OFFSET (0x310) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x31C : DMA_C3RSVD */ -#define DMA_C3RSVD_OFFSET (0x31C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x500 : DMA_C4SrcAddr */ -#define DMA_C4SRCADDR_OFFSET (0x500) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x504 : DMA_C4DstAddr */ -#define DMA_C4DSTADDR_OFFSET (0x504) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x508 : DMA_C4LLI */ -#define DMA_C4LLI_OFFSET (0x508) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x50C : DMA_C4Control */ -#define DMA_C4CONTROL_OFFSET (0x50C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x510 : DMA_C4Config */ -#define DMA_C4CONFIG_OFFSET (0x510) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x51C : DMA_C4RSVD */ -#define DMA_C4RSVD_OFFSET (0x51C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x600 : DMA_C5SrcAddr */ -#define DMA_C5SRCADDR_OFFSET (0x600) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x604 : DMA_C5DstAddr */ -#define DMA_C5DSTADDR_OFFSET (0x604) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x608 : DMA_C5LLI */ -#define DMA_C5LLI_OFFSET (0x608) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x60C : DMA_C5Control */ -#define DMA_C5CONTROL_OFFSET (0x60C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x610 : DMA_C5Config */ -#define DMA_C5CONFIG_OFFSET (0x610) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x61C : DMA_C5RSVD */ -#define DMA_C5RSVD_OFFSET (0x61C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x700 : DMA_C6SrcAddr */ -#define DMA_C6SRCADDR_OFFSET (0x700) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x704 : DMA_C6DstAddr */ -#define DMA_C6DSTADDR_OFFSET (0x704) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x708 : DMA_C6LLI */ -#define DMA_C6LLI_OFFSET (0x708) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x70C : DMA_C6Control */ -#define DMA_C6CONTROL_OFFSET (0x70C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x710 : DMA_C6Config */ -#define DMA_C6CONFIG_OFFSET (0x710) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x71C : DMA_C6RSVD */ -#define DMA_C6RSVD_OFFSET (0x71C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -/* 0x800 : DMA_C7SrcAddr */ -#define DMA_C7SRCADDR_OFFSET (0x800) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x804 : DMA_C7DstAddr */ -#define DMA_C7DSTADDR_OFFSET (0x804) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x808 : DMA_C7LLI */ -#define DMA_C7LLI_OFFSET (0x808) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0x80C : DMA_C7Control */ -#define DMA_C7CONTROL_OFFSET (0x80C) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x810 : DMA_C7Config */ -#define DMA_C7CONFIG_OFFSET (0x810) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) - -/* 0x81C : DMA_C7RSVD */ -#define DMA_C7RSVD_OFFSET (0x81C) -#define DMA_DSTREMNSGLE DMA_DSTREMNSGLE -#define DMA_DSTREMNSGLE_POS (3U) -#define DMA_DSTREMNSGLE_LEN (1U) -#define DMA_DSTREMNSGLE_MSK (((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS) -#define DMA_DSTREMNSGLE_UMSK (~(((1U << DMA_DSTREMNSGLE_LEN) - 1) << DMA_DSTREMNSGLE_POS)) -#define DMA_SRCREMNSGLE DMA_SRCREMNSGLE -#define DMA_SRCREMNSGLE_POS (4U) -#define DMA_SRCREMNSGLE_LEN (1U) -#define DMA_SRCREMNSGLE_MSK (((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS) -#define DMA_SRCREMNSGLE_UMSK (~(((1U << DMA_SRCREMNSGLE_LEN) - 1) << DMA_SRCREMNSGLE_POS)) - -struct dma_reg { - /* 0x0 : DMA_IntStatus */ - union { - struct { - uint32_t IntStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntStatus; - - /* 0x4 : DMA_IntTCStatus */ - union { - struct { - uint32_t IntTCStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCStatus; - - /* 0x8 : DMA_IntTCClear */ - union { - struct { - uint32_t IntTCClear : 8; /* [ 7: 0], w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntTCClear; - - /* 0xC : DMA_IntErrorStatus */ - union { - struct { - uint32_t IntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntErrorStatus; - - /* 0x10 : DMA_IntErrClr */ - union { - struct { - uint32_t IntErrClr : 8; /* [ 7: 0], w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_IntErrClr; - - /* 0x14 : DMA_RawIntTCStatus */ - union { - struct { - uint32_t RawIntTCStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_RawIntTCStatus; - - /* 0x18 : DMA_RawIntErrorStatus */ - union { - struct { - uint32_t RawIntErrorStatus : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_RawIntErrorStatus; - - /* 0x1C : DMA_EnbldChns */ - union { - struct { - uint32_t EnabledChannels : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_EnbldChns; - - /* 0x20 : DMA_SoftBReq */ - union { - struct { - uint32_t SoftBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftBReq; - - /* 0x24 : DMA_SoftSReq */ - union { - struct { - uint32_t SoftSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftSReq; - - /* 0x28 : DMA_SoftLBReq */ - union { - struct { - uint32_t SoftLBReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLBReq; - - /* 0x2C : DMA_SoftLSReq */ - union { - struct { - uint32_t SoftLSReq : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SoftLSReq; - - /* 0x30 : DMA_Top_Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t M : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Top_Config; - - /* 0x34 : DMA_Sync */ - union { - struct { - uint32_t DMA_Sync : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Sync; - - /* 0x38 reserved */ - uint8_t RESERVED0x38[200]; - - /* 0x100 : DMA_C0SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0SrcAddr; - - /* 0x104 : DMA_C0DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0DstAddr; - - /* 0x108 : DMA_C0LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0LLI; - - /* 0x10C : DMA_C0Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0Control; - - /* 0x110 : DMA_C0Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0Config; - - /* 0x114 reserved */ - uint8_t RESERVED0x114[8]; - - /* 0x11C : DMA_C0RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C0RSVD; - - /* 0x120 reserved */ - uint8_t RESERVED0x120[224]; - - /* 0x200 : DMA_C1SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1SrcAddr; - - /* 0x204 : DMA_C1DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1DstAddr; - - /* 0x208 : DMA_C1LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1LLI; - - /* 0x20C : DMA_C1Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1Control; - - /* 0x210 : DMA_C1Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1Config; - - /* 0x214 reserved */ - uint8_t RESERVED0x214[8]; - - /* 0x21C : DMA_C1RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C1RSVD; - - /* 0x220 reserved */ - uint8_t RESERVED0x220[224]; - - /* 0x300 : DMA_C2SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2SrcAddr; - - /* 0x304 : DMA_C2DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2DstAddr; - - /* 0x308 : DMA_C2LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2LLI; - - /* 0x30C : DMA_C2Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C2Control; - - /* 0x310 : DMA_C3Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C3Config; - - /* 0x314 reserved */ - uint8_t RESERVED0x314[8]; - - /* 0x31C : DMA_C3RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C3RSVD; - - /* 0x320 reserved */ - uint8_t RESERVED0x320[480]; - - /* 0x500 : DMA_C4SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4SrcAddr; - - /* 0x504 : DMA_C4DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4DstAddr; - - /* 0x508 : DMA_C4LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4LLI; - - /* 0x50C : DMA_C4Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4Control; - - /* 0x510 : DMA_C4Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4Config; - - /* 0x514 reserved */ - uint8_t RESERVED0x514[8]; - - /* 0x51C : DMA_C4RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C4RSVD; - - /* 0x520 reserved */ - uint8_t RESERVED0x520[224]; - - /* 0x600 : DMA_C5SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5SrcAddr; - - /* 0x604 : DMA_C5DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5DstAddr; - - /* 0x608 : DMA_C5LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5LLI; - - /* 0x60C : DMA_C5Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5Control; - - /* 0x610 : DMA_C5Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5Config; - - /* 0x614 reserved */ - uint8_t RESERVED0x614[8]; - - /* 0x61C : DMA_C5RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C5RSVD; - - /* 0x620 reserved */ - uint8_t RESERVED0x620[224]; - - /* 0x700 : DMA_C6SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6SrcAddr; - - /* 0x704 : DMA_C6DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6DstAddr; - - /* 0x708 : DMA_C6LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6LLI; - - /* 0x70C : DMA_C6Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6Control; - - /* 0x710 : DMA_C6Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6Config; - - /* 0x714 reserved */ - uint8_t RESERVED0x714[8]; - - /* 0x71C : DMA_C6RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C6RSVD; - - /* 0x720 reserved */ - uint8_t RESERVED0x720[224]; - - /* 0x800 : DMA_C7SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7SrcAddr; - - /* 0x804 : DMA_C7DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7DstAddr; - - /* 0x808 : DMA_C7LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7LLI; - - /* 0x80C : DMA_C7Control */ - union { - struct { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7Control; - - /* 0x810 : DMA_C7Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19_31 : 13; /* [31:19], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7Config; - - /* 0x814 reserved */ - uint8_t RESERVED0x814[8]; - - /* 0x81C : DMA_C7RSVD */ - union { - struct { - uint32_t reserved_0_2 : 3; /* [ 2: 0], rsvd, 0x0 */ - uint32_t DstRemnSgle : 1; /* [ 3], r/w, 0x0 */ - uint32_t SrcRemnSgle : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_C7RSVD; -}; - -typedef volatile struct dma_reg dma_reg_t; - -/*Following is reg patch*/ - -/* 0x0 : DMA_SrcAddr */ -#define DMA_SRCADDR_OFFSET (0x0) -#define DMA_SRCADDR DMA_SRCADDR -#define DMA_SRCADDR_POS (0U) -#define DMA_SRCADDR_LEN (32U) -#define DMA_SRCADDR_MSK (((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS) -#define DMA_SRCADDR_UMSK (~(((1U << DMA_SRCADDR_LEN) - 1) << DMA_SRCADDR_POS)) - -/* 0x4 : DMA_DstAddr */ -#define DMA_DSTADDR_OFFSET (0x4) -#define DMA_DSTADDR DMA_DSTADDR -#define DMA_DSTADDR_POS (0U) -#define DMA_DSTADDR_LEN (32U) -#define DMA_DSTADDR_MSK (((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS) -#define DMA_DSTADDR_UMSK (~(((1U << DMA_DSTADDR_LEN) - 1) << DMA_DSTADDR_POS)) - -/* 0x8 : DMA_LLI */ -#define DMA_LLI_OFFSET (0x8) -#define DMA_LLI DMA_LLI -#define DMA_LLI_POS (0U) -#define DMA_LLI_LEN (32U) -#define DMA_LLI_MSK (((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS) -#define DMA_LLI_UMSK (~(((1U << DMA_LLI_LEN) - 1) << DMA_LLI_POS)) - -/* 0xc : DMA_Control */ -#define DMA_CONTROL_OFFSET (0xc) -#define DMA_TRANSFERSIZE DMA_TRANSFERSIZE -#define DMA_TRANSFERSIZE_POS (0U) -#define DMA_TRANSFERSIZE_LEN (12U) -#define DMA_TRANSFERSIZE_MSK (((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS) -#define DMA_TRANSFERSIZE_UMSK (~(((1U << DMA_TRANSFERSIZE_LEN) - 1) << DMA_TRANSFERSIZE_POS)) -#define DMA_SBSIZE DMA_SBSIZE -#define DMA_SBSIZE_POS (12U) -#define DMA_SBSIZE_LEN (2U) -#define DMA_SBSIZE_MSK (((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS) -#define DMA_SBSIZE_UMSK (~(((1U << DMA_SBSIZE_LEN) - 1) << DMA_SBSIZE_POS)) -#define DMA_DST_MIN_MODE DMA_DST_MIN_MODE -#define DMA_DST_MIN_MODE_POS (14U) -#define DMA_DST_MIN_MODE_LEN (1U) -#define DMA_DST_MIN_MODE_MSK (((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS) -#define DMA_DST_MIN_MODE_UMSK (~(((1U << DMA_DST_MIN_MODE_LEN) - 1) << DMA_DST_MIN_MODE_POS)) -#define DMA_DBSIZE DMA_DBSIZE -#define DMA_DBSIZE_POS (15U) -#define DMA_DBSIZE_LEN (2U) -#define DMA_DBSIZE_MSK (((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS) -#define DMA_DBSIZE_UMSK (~(((1U << DMA_DBSIZE_LEN) - 1) << DMA_DBSIZE_POS)) -#define DMA_DST_ADD_MODE DMA_DST_ADD_MODE -#define DMA_DST_ADD_MODE_POS (17U) -#define DMA_DST_ADD_MODE_LEN (1U) -#define DMA_DST_ADD_MODE_MSK (((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS) -#define DMA_DST_ADD_MODE_UMSK (~(((1U << DMA_DST_ADD_MODE_LEN) - 1) << DMA_DST_ADD_MODE_POS)) -#define DMA_SWIDTH DMA_SWIDTH -#define DMA_SWIDTH_POS (18U) -#define DMA_SWIDTH_LEN (2U) -#define DMA_SWIDTH_MSK (((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS) -#define DMA_SWIDTH_UMSK (~(((1U << DMA_SWIDTH_LEN) - 1) << DMA_SWIDTH_POS)) -#define DMA_DWIDTH DMA_DWIDTH -#define DMA_DWIDTH_POS (21U) -#define DMA_DWIDTH_LEN (2U) -#define DMA_DWIDTH_MSK (((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS) -#define DMA_DWIDTH_UMSK (~(((1U << DMA_DWIDTH_LEN) - 1) << DMA_DWIDTH_POS)) -#define DMA_FIX_CNT DMA_FIX_CNT -#define DMA_FIX_CNT_POS (23U) -#define DMA_FIX_CNT_LEN (3U) -#define DMA_FIX_CNT_MSK (((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS) -#define DMA_FIX_CNT_UMSK (~(((1U << DMA_FIX_CNT_LEN) - 1) << DMA_FIX_CNT_POS)) -#define DMA_SI DMA_SI -#define DMA_SI_POS (26U) -#define DMA_SI_LEN (1U) -#define DMA_SI_MSK (((1U << DMA_SI_LEN) - 1) << DMA_SI_POS) -#define DMA_SI_UMSK (~(((1U << DMA_SI_LEN) - 1) << DMA_SI_POS)) -#define DMA_DI DMA_DI -#define DMA_DI_POS (27U) -#define DMA_DI_LEN (1U) -#define DMA_DI_MSK (((1U << DMA_DI_LEN) - 1) << DMA_DI_POS) -#define DMA_DI_UMSK (~(((1U << DMA_DI_LEN) - 1) << DMA_DI_POS)) -#define DMA_PROT DMA_PROT -#define DMA_PROT_POS (28U) -#define DMA_PROT_LEN (3U) -#define DMA_PROT_MSK (((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS) -#define DMA_PROT_UMSK (~(((1U << DMA_PROT_LEN) - 1) << DMA_PROT_POS)) -#define DMA_I DMA_I -#define DMA_I_POS (31U) -#define DMA_I_LEN (1U) -#define DMA_I_MSK (((1U << DMA_I_LEN) - 1) << DMA_I_POS) -#define DMA_I_UMSK (~(((1U << DMA_I_LEN) - 1) << DMA_I_POS)) - -/* 0x10 : DMA_Config */ -#define DMA_CONFIG_OFFSET (0x10) -#define DMA_E DMA_E -#define DMA_E_POS (0U) -#define DMA_E_LEN (1U) -#define DMA_E_MSK (((1U << DMA_E_LEN) - 1) << DMA_E_POS) -#define DMA_E_UMSK (~(((1U << DMA_E_LEN) - 1) << DMA_E_POS)) -#define DMA_SRCPERIPHERAL DMA_SRCPERIPHERAL -#define DMA_SRCPERIPHERAL_POS (1U) -#define DMA_SRCPERIPHERAL_LEN (5U) -#define DMA_SRCPERIPHERAL_MSK (((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS) -#define DMA_SRCPERIPHERAL_UMSK (~(((1U << DMA_SRCPERIPHERAL_LEN) - 1) << DMA_SRCPERIPHERAL_POS)) -#define DMA_DSTPERIPHERAL DMA_DSTPERIPHERAL -#define DMA_DSTPERIPHERAL_POS (6U) -#define DMA_DSTPERIPHERAL_LEN (5U) -#define DMA_DSTPERIPHERAL_MSK (((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS) -#define DMA_DSTPERIPHERAL_UMSK (~(((1U << DMA_DSTPERIPHERAL_LEN) - 1) << DMA_DSTPERIPHERAL_POS)) -#define DMA_FLOWCNTRL DMA_FLOWCNTRL -#define DMA_FLOWCNTRL_POS (11U) -#define DMA_FLOWCNTRL_LEN (3U) -#define DMA_FLOWCNTRL_MSK (((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS) -#define DMA_FLOWCNTRL_UMSK (~(((1U << DMA_FLOWCNTRL_LEN) - 1) << DMA_FLOWCNTRL_POS)) -#define DMA_IE DMA_IE -#define DMA_IE_POS (14U) -#define DMA_IE_LEN (1U) -#define DMA_IE_MSK (((1U << DMA_IE_LEN) - 1) << DMA_IE_POS) -#define DMA_IE_UMSK (~(((1U << DMA_IE_LEN) - 1) << DMA_IE_POS)) -#define DMA_ITC DMA_ITC -#define DMA_ITC_POS (15U) -#define DMA_ITC_LEN (1U) -#define DMA_ITC_MSK (((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS) -#define DMA_ITC_UMSK (~(((1U << DMA_ITC_LEN) - 1) << DMA_ITC_POS)) -#define DMA_L DMA_L -#define DMA_L_POS (16U) -#define DMA_L_LEN (1U) -#define DMA_L_MSK (((1U << DMA_L_LEN) - 1) << DMA_L_POS) -#define DMA_L_UMSK (~(((1U << DMA_L_LEN) - 1) << DMA_L_POS)) -#define DMA_A DMA_A -#define DMA_A_POS (17U) -#define DMA_A_LEN (1U) -#define DMA_A_MSK (((1U << DMA_A_LEN) - 1) << DMA_A_POS) -#define DMA_A_UMSK (~(((1U << DMA_A_LEN) - 1) << DMA_A_POS)) -#define DMA_H DMA_H -#define DMA_H_POS (18U) -#define DMA_H_LEN (1U) -#define DMA_H_MSK (((1U << DMA_H_LEN) - 1) << DMA_H_POS) -#define DMA_H_UMSK (~(((1U << DMA_H_LEN) - 1) << DMA_H_POS)) -#define DMA_LLICOUNTER DMA_LLICOUNTER -#define DMA_LLICOUNTER_POS (20U) -#define DMA_LLICOUNTER_LEN (10U) -#define DMA_LLICOUNTER_MSK (((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS) -#define DMA_LLICOUNTER_UMSK (~(((1U << DMA_LLICOUNTER_LEN) - 1) << DMA_LLICOUNTER_POS)) - -struct dma_channel_reg { - /* 0x0 : DMA_SrcAddr */ - union { - struct { - uint32_t SrcAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_SrcAddr; - - /* 0x4 : DMA_DstAddr */ - union { - struct { - uint32_t DstAddr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_DstAddr; - - /* 0x8 : DMA_LLI */ - union { - struct { - uint32_t LLI : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_LLI; - - /* 0xc : DMA_Control */ - union { - struct DMA_Control_Reg { - uint32_t TransferSize : 12; /* [11: 0], r/w, 0x0 */ - uint32_t SBSize : 2; /* [13:12], r/w, 0x1 */ - uint32_t dst_min_mode : 1; /* [ 14], r/w, 0x0 */ - uint32_t DBSize : 2; /* [16:15], r/w, 0x1 */ - uint32_t dst_add_mode : 1; /* [ 17], r/w, 0x0 */ - uint32_t SWidth : 2; /* [19:18], r/w, 0x2 */ - uint32_t reserved_20 : 1; /* [ 20], rsvd, 0x0 */ - uint32_t DWidth : 2; /* [22:21], r/w, 0x2 */ - uint32_t fix_cnt : 3; /* [25:23], r/w, 0x0 */ - uint32_t SI : 1; /* [ 26], r/w, 0x1 */ - uint32_t DI : 1; /* [ 27], r/w, 0x1 */ - uint32_t Prot : 3; /* [30:28], r/w, 0x0 */ - uint32_t I : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Control; - - /* 0x10 : DMA_Config */ - union { - struct { - uint32_t E : 1; /* [ 0], r/w, 0x0 */ - uint32_t SrcPeripheral : 5; /* [ 5: 1], r/w, 0x0 */ - uint32_t DstPeripheral : 5; /* [10: 6], r/w, 0x0 */ - uint32_t FlowCntrl : 3; /* [13:11], r/w, 0x0 */ - uint32_t IE : 1; /* [ 14], r/w, 0x0 */ - uint32_t ITC : 1; /* [ 15], r/w, 0x0 */ - uint32_t L : 1; /* [ 16], r/w, 0x0 */ - uint32_t A : 1; /* [ 17], r, 0x0 */ - uint32_t H : 1; /* [ 18], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t LLICounter : 10; /* [29:20], r, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_Config; -}; - -typedef volatile struct dma_channel_reg dma_channel_reg_t; - -#define DMA_CHANNEL_OFFSET 0x100 - -#endif /* __DMA_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsi_reg.h deleted file mode 100644 index d7154f0ba8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsi_reg.h +++ /dev/null @@ -1,1231 +0,0 @@ -/** - ****************************************************************************** - * @file dsi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSI_REG_H__ -#define __DSI_REG_H__ - -#include "bl808.h" - -/* 0x0 : dsi_config */ -#define DSI_CONFIG_OFFSET (0x0) -#define DSI_CR_HSTX_EN DSI_CR_HSTX_EN -#define DSI_CR_HSTX_EN_POS (0U) -#define DSI_CR_HSTX_EN_LEN (1U) -#define DSI_CR_HSTX_EN_MSK (((1U << DSI_CR_HSTX_EN_LEN) - 1) << DSI_CR_HSTX_EN_POS) -#define DSI_CR_HSTX_EN_UMSK (~(((1U << DSI_CR_HSTX_EN_LEN) - 1) << DSI_CR_HSTX_EN_POS)) -#define DSI_CR_LANE_NUM DSI_CR_LANE_NUM -#define DSI_CR_LANE_NUM_POS (1U) -#define DSI_CR_LANE_NUM_LEN (2U) -#define DSI_CR_LANE_NUM_MSK (((1U << DSI_CR_LANE_NUM_LEN) - 1) << DSI_CR_LANE_NUM_POS) -#define DSI_CR_LANE_NUM_UMSK (~(((1U << DSI_CR_LANE_NUM_LEN) - 1) << DSI_CR_LANE_NUM_POS)) -#define DSI_CR_HSTX_MODE DSI_CR_HSTX_MODE -#define DSI_CR_HSTX_MODE_POS (4U) -#define DSI_CR_HSTX_MODE_LEN (1U) -#define DSI_CR_HSTX_MODE_MSK (((1U << DSI_CR_HSTX_MODE_LEN) - 1) << DSI_CR_HSTX_MODE_POS) -#define DSI_CR_HSTX_MODE_UMSK (~(((1U << DSI_CR_HSTX_MODE_LEN) - 1) << DSI_CR_HSTX_MODE_POS)) -#define DSI_CR_LSE_PKT_EN DSI_CR_LSE_PKT_EN -#define DSI_CR_LSE_PKT_EN_POS (5U) -#define DSI_CR_LSE_PKT_EN_LEN (1U) -#define DSI_CR_LSE_PKT_EN_MSK (((1U << DSI_CR_LSE_PKT_EN_LEN) - 1) << DSI_CR_LSE_PKT_EN_POS) -#define DSI_CR_LSE_PKT_EN_UMSK (~(((1U << DSI_CR_LSE_PKT_EN_LEN) - 1) << DSI_CR_LSE_PKT_EN_POS)) -#define DSI_CR_LANE_MUX_SEL DSI_CR_LANE_MUX_SEL -#define DSI_CR_LANE_MUX_SEL_POS (6U) -#define DSI_CR_LANE_MUX_SEL_LEN (2U) -#define DSI_CR_LANE_MUX_SEL_MSK (((1U << DSI_CR_LANE_MUX_SEL_LEN) - 1) << DSI_CR_LANE_MUX_SEL_POS) -#define DSI_CR_LANE_MUX_SEL_UMSK (~(((1U << DSI_CR_LANE_MUX_SEL_LEN) - 1) << DSI_CR_LANE_MUX_SEL_POS)) -#define DSI_CR_DT DSI_CR_DT -#define DSI_CR_DT_POS (8U) -#define DSI_CR_DT_LEN (6U) -#define DSI_CR_DT_MSK (((1U << DSI_CR_DT_LEN) - 1) << DSI_CR_DT_POS) -#define DSI_CR_DT_UMSK (~(((1U << DSI_CR_DT_LEN) - 1) << DSI_CR_DT_POS)) -#define DSI_CR_VC DSI_CR_VC -#define DSI_CR_VC_POS (14U) -#define DSI_CR_VC_LEN (2U) -#define DSI_CR_VC_MSK (((1U << DSI_CR_VC_LEN) - 1) << DSI_CR_VC_POS) -#define DSI_CR_VC_UMSK (~(((1U << DSI_CR_VC_LEN) - 1) << DSI_CR_VC_POS)) -#define DSI_CR_HSTX_VFP DSI_CR_HSTX_VFP -#define DSI_CR_HSTX_VFP_POS (16U) -#define DSI_CR_HSTX_VFP_LEN (8U) -#define DSI_CR_HSTX_VFP_MSK (((1U << DSI_CR_HSTX_VFP_LEN) - 1) << DSI_CR_HSTX_VFP_POS) -#define DSI_CR_HSTX_VFP_UMSK (~(((1U << DSI_CR_HSTX_VFP_LEN) - 1) << DSI_CR_HSTX_VFP_POS)) -#define DSI_CR_HSTX_VSA DSI_CR_HSTX_VSA -#define DSI_CR_HSTX_VSA_POS (24U) -#define DSI_CR_HSTX_VSA_LEN (8U) -#define DSI_CR_HSTX_VSA_MSK (((1U << DSI_CR_HSTX_VSA_LEN) - 1) << DSI_CR_HSTX_VSA_POS) -#define DSI_CR_HSTX_VSA_UMSK (~(((1U << DSI_CR_HSTX_VSA_LEN) - 1) << DSI_CR_HSTX_VSA_POS)) - -/* 0x4 : dsi_esc_config */ -#define DSI_ESC_CONFIG_OFFSET (0x4) -#define DSI_CR_ESC_TX_EN DSI_CR_ESC_TX_EN -#define DSI_CR_ESC_TX_EN_POS (0U) -#define DSI_CR_ESC_TX_EN_LEN (1U) -#define DSI_CR_ESC_TX_EN_MSK (((1U << DSI_CR_ESC_TX_EN_LEN) - 1) << DSI_CR_ESC_TX_EN_POS) -#define DSI_CR_ESC_TX_EN_UMSK (~(((1U << DSI_CR_ESC_TX_EN_LEN) - 1) << DSI_CR_ESC_TX_EN_POS)) -#define DSI_CR_ESC_TX_MODE DSI_CR_ESC_TX_MODE -#define DSI_CR_ESC_TX_MODE_POS (1U) -#define DSI_CR_ESC_TX_MODE_LEN (2U) -#define DSI_CR_ESC_TX_MODE_MSK (((1U << DSI_CR_ESC_TX_MODE_LEN) - 1) << DSI_CR_ESC_TX_MODE_POS) -#define DSI_CR_ESC_TX_MODE_UMSK (~(((1U << DSI_CR_ESC_TX_MODE_LEN) - 1) << DSI_CR_ESC_TX_MODE_POS)) -#define DSI_CR_ESC_TX_ULPS_EXIT DSI_CR_ESC_TX_ULPS_EXIT -#define DSI_CR_ESC_TX_ULPS_EXIT_POS (3U) -#define DSI_CR_ESC_TX_ULPS_EXIT_LEN (1U) -#define DSI_CR_ESC_TX_ULPS_EXIT_MSK (((1U << DSI_CR_ESC_TX_ULPS_EXIT_LEN) - 1) << DSI_CR_ESC_TX_ULPS_EXIT_POS) -#define DSI_CR_ESC_TX_ULPS_EXIT_UMSK (~(((1U << DSI_CR_ESC_TX_ULPS_EXIT_LEN) - 1) << DSI_CR_ESC_TX_ULPS_EXIT_POS)) -#define DSI_CR_ESC_TX_TRIG DSI_CR_ESC_TX_TRIG -#define DSI_CR_ESC_TX_TRIG_POS (4U) -#define DSI_CR_ESC_TX_TRIG_LEN (4U) -#define DSI_CR_ESC_TX_TRIG_MSK (((1U << DSI_CR_ESC_TX_TRIG_LEN) - 1) << DSI_CR_ESC_TX_TRIG_POS) -#define DSI_CR_ESC_TX_TRIG_UMSK (~(((1U << DSI_CR_ESC_TX_TRIG_LEN) - 1) << DSI_CR_ESC_TX_TRIG_POS)) -#define DSI_CR_ESC_RX_EN DSI_CR_ESC_RX_EN -#define DSI_CR_ESC_RX_EN_POS (16U) -#define DSI_CR_ESC_RX_EN_LEN (1U) -#define DSI_CR_ESC_RX_EN_MSK (((1U << DSI_CR_ESC_RX_EN_LEN) - 1) << DSI_CR_ESC_RX_EN_POS) -#define DSI_CR_ESC_RX_EN_UMSK (~(((1U << DSI_CR_ESC_RX_EN_LEN) - 1) << DSI_CR_ESC_RX_EN_POS)) -#define DSI_ST_ESC_RX_LEN DSI_ST_ESC_RX_LEN -#define DSI_ST_ESC_RX_LEN_POS (24U) -#define DSI_ST_ESC_RX_LEN_LEN (8U) -#define DSI_ST_ESC_RX_LEN_MSK (((1U << DSI_ST_ESC_RX_LEN_LEN) - 1) << DSI_ST_ESC_RX_LEN_POS) -#define DSI_ST_ESC_RX_LEN_UMSK (~(((1U << DSI_ST_ESC_RX_LEN_LEN) - 1) << DSI_ST_ESC_RX_LEN_POS)) - -/* 0x8 : dsi_lpdt_tx_config */ -#define DSI_LPDT_TX_CONFIG_OFFSET (0x8) -#define DSI_CR_LPDT_PDLEN DSI_CR_LPDT_PDLEN -#define DSI_CR_LPDT_PDLEN_POS (0U) -#define DSI_CR_LPDT_PDLEN_LEN (8U) -#define DSI_CR_LPDT_PDLEN_MSK (((1U << DSI_CR_LPDT_PDLEN_LEN) - 1) << DSI_CR_LPDT_PDLEN_POS) -#define DSI_CR_LPDT_PDLEN_UMSK (~(((1U << DSI_CR_LPDT_PDLEN_LEN) - 1) << DSI_CR_LPDT_PDLEN_POS)) -#define DSI_CR_LPDT_VC DSI_CR_LPDT_VC -#define DSI_CR_LPDT_VC_POS (8U) -#define DSI_CR_LPDT_VC_LEN (2U) -#define DSI_CR_LPDT_VC_MSK (((1U << DSI_CR_LPDT_VC_LEN) - 1) << DSI_CR_LPDT_VC_POS) -#define DSI_CR_LPDT_VC_UMSK (~(((1U << DSI_CR_LPDT_VC_LEN) - 1) << DSI_CR_LPDT_VC_POS)) -#define DSI_CR_LPDT_DI DSI_CR_LPDT_DI -#define DSI_CR_LPDT_DI_POS (10U) -#define DSI_CR_LPDT_DI_LEN (6U) -#define DSI_CR_LPDT_DI_MSK (((1U << DSI_CR_LPDT_DI_LEN) - 1) << DSI_CR_LPDT_DI_POS) -#define DSI_CR_LPDT_DI_UMSK (~(((1U << DSI_CR_LPDT_DI_LEN) - 1) << DSI_CR_LPDT_DI_POS)) -#define DSI_CR_LPDT_WORD0 DSI_CR_LPDT_WORD0 -#define DSI_CR_LPDT_WORD0_POS (16U) -#define DSI_CR_LPDT_WORD0_LEN (8U) -#define DSI_CR_LPDT_WORD0_MSK (((1U << DSI_CR_LPDT_WORD0_LEN) - 1) << DSI_CR_LPDT_WORD0_POS) -#define DSI_CR_LPDT_WORD0_UMSK (~(((1U << DSI_CR_LPDT_WORD0_LEN) - 1) << DSI_CR_LPDT_WORD0_POS)) -#define DSI_CR_LPDT_WORD1 DSI_CR_LPDT_WORD1 -#define DSI_CR_LPDT_WORD1_POS (24U) -#define DSI_CR_LPDT_WORD1_LEN (8U) -#define DSI_CR_LPDT_WORD1_MSK (((1U << DSI_CR_LPDT_WORD1_LEN) - 1) << DSI_CR_LPDT_WORD1_POS) -#define DSI_CR_LPDT_WORD1_UMSK (~(((1U << DSI_CR_LPDT_WORD1_LEN) - 1) << DSI_CR_LPDT_WORD1_POS)) - -/* 0xC : dsi_hstx_config */ -#define DSI_HSTX_CONFIG_OFFSET (0xC) -#define DSI_CR_HSTX_PC DSI_CR_HSTX_PC -#define DSI_CR_HSTX_PC_POS (0U) -#define DSI_CR_HSTX_PC_LEN (11U) -#define DSI_CR_HSTX_PC_MSK (((1U << DSI_CR_HSTX_PC_LEN) - 1) << DSI_CR_HSTX_PC_POS) -#define DSI_CR_HSTX_PC_UMSK (~(((1U << DSI_CR_HSTX_PC_LEN) - 1) << DSI_CR_HSTX_PC_POS)) -#define DSI_CR_HSTX_OUT_TH DSI_CR_HSTX_OUT_TH -#define DSI_CR_HSTX_OUT_TH_POS (16U) -#define DSI_CR_HSTX_OUT_TH_LEN (11U) -#define DSI_CR_HSTX_OUT_TH_MSK (((1U << DSI_CR_HSTX_OUT_TH_LEN) - 1) << DSI_CR_HSTX_OUT_TH_POS) -#define DSI_CR_HSTX_OUT_TH_UMSK (~(((1U << DSI_CR_HSTX_OUT_TH_LEN) - 1) << DSI_CR_HSTX_OUT_TH_POS)) - -/* 0x10 : dsi_int_status */ -#define DSI_INT_STATUS_OFFSET (0x10) -#define DSI_INT_STATUS DSI_INT_STATUS -#define DSI_INT_STATUS_POS (0U) -#define DSI_INT_STATUS_LEN (14U) -#define DSI_INT_STATUS_MSK (((1U << DSI_INT_STATUS_LEN) - 1) << DSI_INT_STATUS_POS) -#define DSI_INT_STATUS_UMSK (~(((1U << DSI_INT_STATUS_LEN) - 1) << DSI_INT_STATUS_POS)) - -/* 0x14 : dsi_int_mask */ -#define DSI_INT_MASK_OFFSET (0x14) -#define DSI_INT_MASK DSI_INT_MASK -#define DSI_INT_MASK_POS (0U) -#define DSI_INT_MASK_LEN (14U) -#define DSI_INT_MASK_MSK (((1U << DSI_INT_MASK_LEN) - 1) << DSI_INT_MASK_POS) -#define DSI_INT_MASK_UMSK (~(((1U << DSI_INT_MASK_LEN) - 1) << DSI_INT_MASK_POS)) - -/* 0x18 : dsi_int_clear */ -#define DSI_INT_CLEAR_OFFSET (0x18) -#define DSI_INT_CLEAR DSI_INT_CLEAR -#define DSI_INT_CLEAR_POS (0U) -#define DSI_INT_CLEAR_LEN (14U) -#define DSI_INT_CLEAR_MSK (((1U << DSI_INT_CLEAR_LEN) - 1) << DSI_INT_CLEAR_POS) -#define DSI_INT_CLEAR_UMSK (~(((1U << DSI_INT_CLEAR_LEN) - 1) << DSI_INT_CLEAR_POS)) - -/* 0x1C : dsi_int_enable */ -#define DSI_INT_ENABLE_OFFSET (0x1C) -#define DSI_INT_ENABLE DSI_INT_ENABLE -#define DSI_INT_ENABLE_POS (0U) -#define DSI_INT_ENABLE_LEN (14U) -#define DSI_INT_ENABLE_MSK (((1U << DSI_INT_ENABLE_LEN) - 1) << DSI_INT_ENABLE_POS) -#define DSI_INT_ENABLE_UMSK (~(((1U << DSI_INT_ENABLE_LEN) - 1) << DSI_INT_ENABLE_POS)) - -/* 0x20 : dsi_frame_num */ -#define DSI_FRAME_NUM_OFFSET (0x20) -#define DSI_CR_FRAME_NUM DSI_CR_FRAME_NUM -#define DSI_CR_FRAME_NUM_POS (0U) -#define DSI_CR_FRAME_NUM_LEN (16U) -#define DSI_CR_FRAME_NUM_MSK (((1U << DSI_CR_FRAME_NUM_LEN) - 1) << DSI_CR_FRAME_NUM_POS) -#define DSI_CR_FRAME_NUM_UMSK (~(((1U << DSI_CR_FRAME_NUM_LEN) - 1) << DSI_CR_FRAME_NUM_POS)) -#define DSI_CR_FRAME_UPD DSI_CR_FRAME_UPD -#define DSI_CR_FRAME_UPD_POS (31U) -#define DSI_CR_FRAME_UPD_LEN (1U) -#define DSI_CR_FRAME_UPD_MSK (((1U << DSI_CR_FRAME_UPD_LEN) - 1) << DSI_CR_FRAME_UPD_POS) -#define DSI_CR_FRAME_UPD_UMSK (~(((1U << DSI_CR_FRAME_UPD_LEN) - 1) << DSI_CR_FRAME_UPD_POS)) - -/* 0x60 : dsi_fifo_config_0 */ -#define DSI_FIFO_CONFIG_0_OFFSET (0x60) -#define DSI_DMA_TX_EN DSI_DMA_TX_EN -#define DSI_DMA_TX_EN_POS (0U) -#define DSI_DMA_TX_EN_LEN (1U) -#define DSI_DMA_TX_EN_MSK (((1U << DSI_DMA_TX_EN_LEN) - 1) << DSI_DMA_TX_EN_POS) -#define DSI_DMA_TX_EN_UMSK (~(((1U << DSI_DMA_TX_EN_LEN) - 1) << DSI_DMA_TX_EN_POS)) -#define DSI_DMA_RX_EN DSI_DMA_RX_EN -#define DSI_DMA_RX_EN_POS (1U) -#define DSI_DMA_RX_EN_LEN (1U) -#define DSI_DMA_RX_EN_MSK (((1U << DSI_DMA_RX_EN_LEN) - 1) << DSI_DMA_RX_EN_POS) -#define DSI_DMA_RX_EN_UMSK (~(((1U << DSI_DMA_RX_EN_LEN) - 1) << DSI_DMA_RX_EN_POS)) -#define DSI_TX_FIFO_CLR DSI_TX_FIFO_CLR -#define DSI_TX_FIFO_CLR_POS (2U) -#define DSI_TX_FIFO_CLR_LEN (1U) -#define DSI_TX_FIFO_CLR_MSK (((1U << DSI_TX_FIFO_CLR_LEN) - 1) << DSI_TX_FIFO_CLR_POS) -#define DSI_TX_FIFO_CLR_UMSK (~(((1U << DSI_TX_FIFO_CLR_LEN) - 1) << DSI_TX_FIFO_CLR_POS)) -#define DSI_RX_FIFO_CLR DSI_RX_FIFO_CLR -#define DSI_RX_FIFO_CLR_POS (3U) -#define DSI_RX_FIFO_CLR_LEN (1U) -#define DSI_RX_FIFO_CLR_MSK (((1U << DSI_RX_FIFO_CLR_LEN) - 1) << DSI_RX_FIFO_CLR_POS) -#define DSI_RX_FIFO_CLR_UMSK (~(((1U << DSI_RX_FIFO_CLR_LEN) - 1) << DSI_RX_FIFO_CLR_POS)) -#define DSI_TX_FIFO_OVERFLOW DSI_TX_FIFO_OVERFLOW -#define DSI_TX_FIFO_OVERFLOW_POS (4U) -#define DSI_TX_FIFO_OVERFLOW_LEN (1U) -#define DSI_TX_FIFO_OVERFLOW_MSK (((1U << DSI_TX_FIFO_OVERFLOW_LEN) - 1) << DSI_TX_FIFO_OVERFLOW_POS) -#define DSI_TX_FIFO_OVERFLOW_UMSK (~(((1U << DSI_TX_FIFO_OVERFLOW_LEN) - 1) << DSI_TX_FIFO_OVERFLOW_POS)) -#define DSI_TX_FIFO_UNDERFLOW DSI_TX_FIFO_UNDERFLOW -#define DSI_TX_FIFO_UNDERFLOW_POS (5U) -#define DSI_TX_FIFO_UNDERFLOW_LEN (1U) -#define DSI_TX_FIFO_UNDERFLOW_MSK (((1U << DSI_TX_FIFO_UNDERFLOW_LEN) - 1) << DSI_TX_FIFO_UNDERFLOW_POS) -#define DSI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << DSI_TX_FIFO_UNDERFLOW_LEN) - 1) << DSI_TX_FIFO_UNDERFLOW_POS)) -#define DSI_RX_FIFO_OVERFLOW DSI_RX_FIFO_OVERFLOW -#define DSI_RX_FIFO_OVERFLOW_POS (6U) -#define DSI_RX_FIFO_OVERFLOW_LEN (1U) -#define DSI_RX_FIFO_OVERFLOW_MSK (((1U << DSI_RX_FIFO_OVERFLOW_LEN) - 1) << DSI_RX_FIFO_OVERFLOW_POS) -#define DSI_RX_FIFO_OVERFLOW_UMSK (~(((1U << DSI_RX_FIFO_OVERFLOW_LEN) - 1) << DSI_RX_FIFO_OVERFLOW_POS)) -#define DSI_RX_FIFO_UNDERFLOW DSI_RX_FIFO_UNDERFLOW -#define DSI_RX_FIFO_UNDERFLOW_POS (7U) -#define DSI_RX_FIFO_UNDERFLOW_LEN (1U) -#define DSI_RX_FIFO_UNDERFLOW_MSK (((1U << DSI_RX_FIFO_UNDERFLOW_LEN) - 1) << DSI_RX_FIFO_UNDERFLOW_POS) -#define DSI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << DSI_RX_FIFO_UNDERFLOW_LEN) - 1) << DSI_RX_FIFO_UNDERFLOW_POS)) - -/* 0x64 : dsi_fifo_config_1 */ -#define DSI_FIFO_CONFIG_1_OFFSET (0x64) -#define DSI_TX_FIFO_CNT DSI_TX_FIFO_CNT -#define DSI_TX_FIFO_CNT_POS (0U) -#define DSI_TX_FIFO_CNT_LEN (3U) -#define DSI_TX_FIFO_CNT_MSK (((1U << DSI_TX_FIFO_CNT_LEN) - 1) << DSI_TX_FIFO_CNT_POS) -#define DSI_TX_FIFO_CNT_UMSK (~(((1U << DSI_TX_FIFO_CNT_LEN) - 1) << DSI_TX_FIFO_CNT_POS)) -#define DSI_RX_FIFO_CNT DSI_RX_FIFO_CNT -#define DSI_RX_FIFO_CNT_POS (8U) -#define DSI_RX_FIFO_CNT_LEN (3U) -#define DSI_RX_FIFO_CNT_MSK (((1U << DSI_RX_FIFO_CNT_LEN) - 1) << DSI_RX_FIFO_CNT_POS) -#define DSI_RX_FIFO_CNT_UMSK (~(((1U << DSI_RX_FIFO_CNT_LEN) - 1) << DSI_RX_FIFO_CNT_POS)) -#define DSI_TX_FIFO_TH DSI_TX_FIFO_TH -#define DSI_TX_FIFO_TH_POS (16U) -#define DSI_TX_FIFO_TH_LEN (2U) -#define DSI_TX_FIFO_TH_MSK (((1U << DSI_TX_FIFO_TH_LEN) - 1) << DSI_TX_FIFO_TH_POS) -#define DSI_TX_FIFO_TH_UMSK (~(((1U << DSI_TX_FIFO_TH_LEN) - 1) << DSI_TX_FIFO_TH_POS)) -#define DSI_RX_FIFO_TH DSI_RX_FIFO_TH -#define DSI_RX_FIFO_TH_POS (24U) -#define DSI_RX_FIFO_TH_LEN (2U) -#define DSI_RX_FIFO_TH_MSK (((1U << DSI_RX_FIFO_TH_LEN) - 1) << DSI_RX_FIFO_TH_POS) -#define DSI_RX_FIFO_TH_UMSK (~(((1U << DSI_RX_FIFO_TH_LEN) - 1) << DSI_RX_FIFO_TH_POS)) - -/* 0x68 : dsi_fifo_wdata */ -#define DSI_FIFO_WDATA_OFFSET (0x68) -#define DSI_FIFO_WDATA DSI_FIFO_WDATA -#define DSI_FIFO_WDATA_POS (0U) -#define DSI_FIFO_WDATA_LEN (32U) -#define DSI_FIFO_WDATA_MSK (((1U << DSI_FIFO_WDATA_LEN) - 1) << DSI_FIFO_WDATA_POS) -#define DSI_FIFO_WDATA_UMSK (~(((1U << DSI_FIFO_WDATA_LEN) - 1) << DSI_FIFO_WDATA_POS)) - -/* 0x6C : dsi_fifo_rdata */ -#define DSI_FIFO_RDATA_OFFSET (0x6C) -#define DSI_FIFO_RDATA DSI_FIFO_RDATA -#define DSI_FIFO_RDATA_POS (0U) -#define DSI_FIFO_RDATA_LEN (32U) -#define DSI_FIFO_RDATA_MSK (((1U << DSI_FIFO_RDATA_LEN) - 1) << DSI_FIFO_RDATA_POS) -#define DSI_FIFO_RDATA_UMSK (~(((1U << DSI_FIFO_RDATA_LEN) - 1) << DSI_FIFO_RDATA_POS)) - -/* 0x80 : dphy_config_0 */ -#define DSI_DPHY_CONFIG_0_OFFSET (0x80) -#define DSI_CL_ENABLE DSI_CL_ENABLE -#define DSI_CL_ENABLE_POS (0U) -#define DSI_CL_ENABLE_LEN (1U) -#define DSI_CL_ENABLE_MSK (((1U << DSI_CL_ENABLE_LEN) - 1) << DSI_CL_ENABLE_POS) -#define DSI_CL_ENABLE_UMSK (~(((1U << DSI_CL_ENABLE_LEN) - 1) << DSI_CL_ENABLE_POS)) -#define DSI_CL_TXREQUESTHS DSI_CL_TXREQUESTHS -#define DSI_CL_TXREQUESTHS_POS (1U) -#define DSI_CL_TXREQUESTHS_LEN (1U) -#define DSI_CL_TXREQUESTHS_MSK (((1U << DSI_CL_TXREQUESTHS_LEN) - 1) << DSI_CL_TXREQUESTHS_POS) -#define DSI_CL_TXREQUESTHS_UMSK (~(((1U << DSI_CL_TXREQUESTHS_LEN) - 1) << DSI_CL_TXREQUESTHS_POS)) -#define DSI_CL_TXULPSCLK DSI_CL_TXULPSCLK -#define DSI_CL_TXULPSCLK_POS (2U) -#define DSI_CL_TXULPSCLK_LEN (1U) -#define DSI_CL_TXULPSCLK_MSK (((1U << DSI_CL_TXULPSCLK_LEN) - 1) << DSI_CL_TXULPSCLK_POS) -#define DSI_CL_TXULPSCLK_UMSK (~(((1U << DSI_CL_TXULPSCLK_LEN) - 1) << DSI_CL_TXULPSCLK_POS)) -#define DSI_CL_TXULPSEXIT DSI_CL_TXULPSEXIT -#define DSI_CL_TXULPSEXIT_POS (3U) -#define DSI_CL_TXULPSEXIT_LEN (1U) -#define DSI_CL_TXULPSEXIT_MSK (((1U << DSI_CL_TXULPSEXIT_LEN) - 1) << DSI_CL_TXULPSEXIT_POS) -#define DSI_CL_TXULPSEXIT_UMSK (~(((1U << DSI_CL_TXULPSEXIT_LEN) - 1) << DSI_CL_TXULPSEXIT_POS)) -#define DSI_CL_STOPSTATE DSI_CL_STOPSTATE -#define DSI_CL_STOPSTATE_POS (4U) -#define DSI_CL_STOPSTATE_LEN (1U) -#define DSI_CL_STOPSTATE_MSK (((1U << DSI_CL_STOPSTATE_LEN) - 1) << DSI_CL_STOPSTATE_POS) -#define DSI_CL_STOPSTATE_UMSK (~(((1U << DSI_CL_STOPSTATE_LEN) - 1) << DSI_CL_STOPSTATE_POS)) -#define DSI_CL_ULPSACTIVENOT DSI_CL_ULPSACTIVENOT -#define DSI_CL_ULPSACTIVENOT_POS (5U) -#define DSI_CL_ULPSACTIVENOT_LEN (1U) -#define DSI_CL_ULPSACTIVENOT_MSK (((1U << DSI_CL_ULPSACTIVENOT_LEN) - 1) << DSI_CL_ULPSACTIVENOT_POS) -#define DSI_CL_ULPSACTIVENOT_UMSK (~(((1U << DSI_CL_ULPSACTIVENOT_LEN) - 1) << DSI_CL_ULPSACTIVENOT_POS)) -#define DSI_DL0_ENABLE DSI_DL0_ENABLE -#define DSI_DL0_ENABLE_POS (8U) -#define DSI_DL0_ENABLE_LEN (1U) -#define DSI_DL0_ENABLE_MSK (((1U << DSI_DL0_ENABLE_LEN) - 1) << DSI_DL0_ENABLE_POS) -#define DSI_DL0_ENABLE_UMSK (~(((1U << DSI_DL0_ENABLE_LEN) - 1) << DSI_DL0_ENABLE_POS)) -#define DSI_DL1_ENABLE DSI_DL1_ENABLE -#define DSI_DL1_ENABLE_POS (9U) -#define DSI_DL1_ENABLE_LEN (1U) -#define DSI_DL1_ENABLE_MSK (((1U << DSI_DL1_ENABLE_LEN) - 1) << DSI_DL1_ENABLE_POS) -#define DSI_DL1_ENABLE_UMSK (~(((1U << DSI_DL1_ENABLE_LEN) - 1) << DSI_DL1_ENABLE_POS)) -#define DSI_DL2_ENABLE DSI_DL2_ENABLE -#define DSI_DL2_ENABLE_POS (10U) -#define DSI_DL2_ENABLE_LEN (1U) -#define DSI_DL2_ENABLE_MSK (((1U << DSI_DL2_ENABLE_LEN) - 1) << DSI_DL2_ENABLE_POS) -#define DSI_DL2_ENABLE_UMSK (~(((1U << DSI_DL2_ENABLE_LEN) - 1) << DSI_DL2_ENABLE_POS)) -#define DSI_DL3_ENABLE DSI_DL3_ENABLE -#define DSI_DL3_ENABLE_POS (11U) -#define DSI_DL3_ENABLE_LEN (1U) -#define DSI_DL3_ENABLE_MSK (((1U << DSI_DL3_ENABLE_LEN) - 1) << DSI_DL3_ENABLE_POS) -#define DSI_DL3_ENABLE_UMSK (~(((1U << DSI_DL3_ENABLE_LEN) - 1) << DSI_DL3_ENABLE_POS)) -#define DSI_DL0_STOPSTATE DSI_DL0_STOPSTATE -#define DSI_DL0_STOPSTATE_POS (12U) -#define DSI_DL0_STOPSTATE_LEN (1U) -#define DSI_DL0_STOPSTATE_MSK (((1U << DSI_DL0_STOPSTATE_LEN) - 1) << DSI_DL0_STOPSTATE_POS) -#define DSI_DL0_STOPSTATE_UMSK (~(((1U << DSI_DL0_STOPSTATE_LEN) - 1) << DSI_DL0_STOPSTATE_POS)) -#define DSI_DL1_STOPSTATE DSI_DL1_STOPSTATE -#define DSI_DL1_STOPSTATE_POS (13U) -#define DSI_DL1_STOPSTATE_LEN (1U) -#define DSI_DL1_STOPSTATE_MSK (((1U << DSI_DL1_STOPSTATE_LEN) - 1) << DSI_DL1_STOPSTATE_POS) -#define DSI_DL1_STOPSTATE_UMSK (~(((1U << DSI_DL1_STOPSTATE_LEN) - 1) << DSI_DL1_STOPSTATE_POS)) -#define DSI_DL2_STOPSTATE DSI_DL2_STOPSTATE -#define DSI_DL2_STOPSTATE_POS (14U) -#define DSI_DL2_STOPSTATE_LEN (1U) -#define DSI_DL2_STOPSTATE_MSK (((1U << DSI_DL2_STOPSTATE_LEN) - 1) << DSI_DL2_STOPSTATE_POS) -#define DSI_DL2_STOPSTATE_UMSK (~(((1U << DSI_DL2_STOPSTATE_LEN) - 1) << DSI_DL2_STOPSTATE_POS)) -#define DSI_DL3_STOPSTATE DSI_DL3_STOPSTATE -#define DSI_DL3_STOPSTATE_POS (15U) -#define DSI_DL3_STOPSTATE_LEN (1U) -#define DSI_DL3_STOPSTATE_MSK (((1U << DSI_DL3_STOPSTATE_LEN) - 1) << DSI_DL3_STOPSTATE_POS) -#define DSI_DL3_STOPSTATE_UMSK (~(((1U << DSI_DL3_STOPSTATE_LEN) - 1) << DSI_DL3_STOPSTATE_POS)) -#define DSI_DL0_ULPSACTIVENOT DSI_DL0_ULPSACTIVENOT -#define DSI_DL0_ULPSACTIVENOT_POS (16U) -#define DSI_DL0_ULPSACTIVENOT_LEN (1U) -#define DSI_DL0_ULPSACTIVENOT_MSK (((1U << DSI_DL0_ULPSACTIVENOT_LEN) - 1) << DSI_DL0_ULPSACTIVENOT_POS) -#define DSI_DL0_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL0_ULPSACTIVENOT_LEN) - 1) << DSI_DL0_ULPSACTIVENOT_POS)) -#define DSI_DL1_ULPSACTIVENOT DSI_DL1_ULPSACTIVENOT -#define DSI_DL1_ULPSACTIVENOT_POS (17U) -#define DSI_DL1_ULPSACTIVENOT_LEN (1U) -#define DSI_DL1_ULPSACTIVENOT_MSK (((1U << DSI_DL1_ULPSACTIVENOT_LEN) - 1) << DSI_DL1_ULPSACTIVENOT_POS) -#define DSI_DL1_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL1_ULPSACTIVENOT_LEN) - 1) << DSI_DL1_ULPSACTIVENOT_POS)) -#define DSI_DL2_ULPSACTIVENOT DSI_DL2_ULPSACTIVENOT -#define DSI_DL2_ULPSACTIVENOT_POS (18U) -#define DSI_DL2_ULPSACTIVENOT_LEN (1U) -#define DSI_DL2_ULPSACTIVENOT_MSK (((1U << DSI_DL2_ULPSACTIVENOT_LEN) - 1) << DSI_DL2_ULPSACTIVENOT_POS) -#define DSI_DL2_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL2_ULPSACTIVENOT_LEN) - 1) << DSI_DL2_ULPSACTIVENOT_POS)) -#define DSI_DL3_ULPSACTIVENOT DSI_DL3_ULPSACTIVENOT -#define DSI_DL3_ULPSACTIVENOT_POS (19U) -#define DSI_DL3_ULPSACTIVENOT_LEN (1U) -#define DSI_DL3_ULPSACTIVENOT_MSK (((1U << DSI_DL3_ULPSACTIVENOT_LEN) - 1) << DSI_DL3_ULPSACTIVENOT_POS) -#define DSI_DL3_ULPSACTIVENOT_UMSK (~(((1U << DSI_DL3_ULPSACTIVENOT_LEN) - 1) << DSI_DL3_ULPSACTIVENOT_POS)) -#define DSI_DL0_FORCERXMODE DSI_DL0_FORCERXMODE -#define DSI_DL0_FORCERXMODE_POS (20U) -#define DSI_DL0_FORCERXMODE_LEN (1U) -#define DSI_DL0_FORCERXMODE_MSK (((1U << DSI_DL0_FORCERXMODE_LEN) - 1) << DSI_DL0_FORCERXMODE_POS) -#define DSI_DL0_FORCERXMODE_UMSK (~(((1U << DSI_DL0_FORCERXMODE_LEN) - 1) << DSI_DL0_FORCERXMODE_POS)) -#define DSI_DL1_FORCERXMODE DSI_DL1_FORCERXMODE -#define DSI_DL1_FORCERXMODE_POS (21U) -#define DSI_DL1_FORCERXMODE_LEN (1U) -#define DSI_DL1_FORCERXMODE_MSK (((1U << DSI_DL1_FORCERXMODE_LEN) - 1) << DSI_DL1_FORCERXMODE_POS) -#define DSI_DL1_FORCERXMODE_UMSK (~(((1U << DSI_DL1_FORCERXMODE_LEN) - 1) << DSI_DL1_FORCERXMODE_POS)) -#define DSI_DL2_FORCERXMODE DSI_DL2_FORCERXMODE -#define DSI_DL2_FORCERXMODE_POS (22U) -#define DSI_DL2_FORCERXMODE_LEN (1U) -#define DSI_DL2_FORCERXMODE_MSK (((1U << DSI_DL2_FORCERXMODE_LEN) - 1) << DSI_DL2_FORCERXMODE_POS) -#define DSI_DL2_FORCERXMODE_UMSK (~(((1U << DSI_DL2_FORCERXMODE_LEN) - 1) << DSI_DL2_FORCERXMODE_POS)) -#define DSI_DL3_FORCERXMODE DSI_DL3_FORCERXMODE -#define DSI_DL3_FORCERXMODE_POS (23U) -#define DSI_DL3_FORCERXMODE_LEN (1U) -#define DSI_DL3_FORCERXMODE_MSK (((1U << DSI_DL3_FORCERXMODE_LEN) - 1) << DSI_DL3_FORCERXMODE_POS) -#define DSI_DL3_FORCERXMODE_UMSK (~(((1U << DSI_DL3_FORCERXMODE_LEN) - 1) << DSI_DL3_FORCERXMODE_POS)) -#define DSI_DL0_FORCETXSTOPMODE DSI_DL0_FORCETXSTOPMODE -#define DSI_DL0_FORCETXSTOPMODE_POS (24U) -#define DSI_DL0_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL0_FORCETXSTOPMODE_MSK (((1U << DSI_DL0_FORCETXSTOPMODE_LEN) - 1) << DSI_DL0_FORCETXSTOPMODE_POS) -#define DSI_DL0_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL0_FORCETXSTOPMODE_LEN) - 1) << DSI_DL0_FORCETXSTOPMODE_POS)) -#define DSI_DL1_FORCETXSTOPMODE DSI_DL1_FORCETXSTOPMODE -#define DSI_DL1_FORCETXSTOPMODE_POS (25U) -#define DSI_DL1_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL1_FORCETXSTOPMODE_MSK (((1U << DSI_DL1_FORCETXSTOPMODE_LEN) - 1) << DSI_DL1_FORCETXSTOPMODE_POS) -#define DSI_DL1_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL1_FORCETXSTOPMODE_LEN) - 1) << DSI_DL1_FORCETXSTOPMODE_POS)) -#define DSI_DL2_FORCETXSTOPMODE DSI_DL2_FORCETXSTOPMODE -#define DSI_DL2_FORCETXSTOPMODE_POS (26U) -#define DSI_DL2_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL2_FORCETXSTOPMODE_MSK (((1U << DSI_DL2_FORCETXSTOPMODE_LEN) - 1) << DSI_DL2_FORCETXSTOPMODE_POS) -#define DSI_DL2_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL2_FORCETXSTOPMODE_LEN) - 1) << DSI_DL2_FORCETXSTOPMODE_POS)) -#define DSI_DL3_FORCETXSTOPMODE DSI_DL3_FORCETXSTOPMODE -#define DSI_DL3_FORCETXSTOPMODE_POS (27U) -#define DSI_DL3_FORCETXSTOPMODE_LEN (1U) -#define DSI_DL3_FORCETXSTOPMODE_MSK (((1U << DSI_DL3_FORCETXSTOPMODE_LEN) - 1) << DSI_DL3_FORCETXSTOPMODE_POS) -#define DSI_DL3_FORCETXSTOPMODE_UMSK (~(((1U << DSI_DL3_FORCETXSTOPMODE_LEN) - 1) << DSI_DL3_FORCETXSTOPMODE_POS)) -#define DSI_DL0_TURNESC DSI_DL0_TURNESC -#define DSI_DL0_TURNESC_POS (30U) -#define DSI_DL0_TURNESC_LEN (1U) -#define DSI_DL0_TURNESC_MSK (((1U << DSI_DL0_TURNESC_LEN) - 1) << DSI_DL0_TURNESC_POS) -#define DSI_DL0_TURNESC_UMSK (~(((1U << DSI_DL0_TURNESC_LEN) - 1) << DSI_DL0_TURNESC_POS)) -#define DSI_RESET_N DSI_RESET_N -#define DSI_RESET_N_POS (31U) -#define DSI_RESET_N_LEN (1U) -#define DSI_RESET_N_MSK (((1U << DSI_RESET_N_LEN) - 1) << DSI_RESET_N_POS) -#define DSI_RESET_N_UMSK (~(((1U << DSI_RESET_N_LEN) - 1) << DSI_RESET_N_POS)) - -/* 0x84 : dphy_config_1 */ -#define DSI_DPHY_CONFIG_1_OFFSET (0x84) -#define DSI_REG_TIME_CK_ZERO DSI_REG_TIME_CK_ZERO -#define DSI_REG_TIME_CK_ZERO_POS (0U) -#define DSI_REG_TIME_CK_ZERO_LEN (8U) -#define DSI_REG_TIME_CK_ZERO_MSK (((1U << DSI_REG_TIME_CK_ZERO_LEN) - 1) << DSI_REG_TIME_CK_ZERO_POS) -#define DSI_REG_TIME_CK_ZERO_UMSK (~(((1U << DSI_REG_TIME_CK_ZERO_LEN) - 1) << DSI_REG_TIME_CK_ZERO_POS)) -#define DSI_REG_TIME_CK_TRAIL DSI_REG_TIME_CK_TRAIL -#define DSI_REG_TIME_CK_TRAIL_POS (8U) -#define DSI_REG_TIME_CK_TRAIL_LEN (8U) -#define DSI_REG_TIME_CK_TRAIL_MSK (((1U << DSI_REG_TIME_CK_TRAIL_LEN) - 1) << DSI_REG_TIME_CK_TRAIL_POS) -#define DSI_REG_TIME_CK_TRAIL_UMSK (~(((1U << DSI_REG_TIME_CK_TRAIL_LEN) - 1) << DSI_REG_TIME_CK_TRAIL_POS)) -#define DSI_REG_TIME_CK_EXIT DSI_REG_TIME_CK_EXIT -#define DSI_REG_TIME_CK_EXIT_POS (16U) -#define DSI_REG_TIME_CK_EXIT_LEN (8U) -#define DSI_REG_TIME_CK_EXIT_MSK (((1U << DSI_REG_TIME_CK_EXIT_LEN) - 1) << DSI_REG_TIME_CK_EXIT_POS) -#define DSI_REG_TIME_CK_EXIT_UMSK (~(((1U << DSI_REG_TIME_CK_EXIT_LEN) - 1) << DSI_REG_TIME_CK_EXIT_POS)) -#define DSI_REG_EN_LPRX_AT_ULPS DSI_REG_EN_LPRX_AT_ULPS -#define DSI_REG_EN_LPRX_AT_ULPS_POS (24U) -#define DSI_REG_EN_LPRX_AT_ULPS_LEN (1U) -#define DSI_REG_EN_LPRX_AT_ULPS_MSK (((1U << DSI_REG_EN_LPRX_AT_ULPS_LEN) - 1) << DSI_REG_EN_LPRX_AT_ULPS_POS) -#define DSI_REG_EN_LPRX_AT_ULPS_UMSK (~(((1U << DSI_REG_EN_LPRX_AT_ULPS_LEN) - 1) << DSI_REG_EN_LPRX_AT_ULPS_POS)) - -/* 0x88 : dphy_config_2 */ -#define DSI_DPHY_CONFIG_2_OFFSET (0x88) -#define DSI_REG_TIME_HS_ZERO DSI_REG_TIME_HS_ZERO -#define DSI_REG_TIME_HS_ZERO_POS (0U) -#define DSI_REG_TIME_HS_ZERO_LEN (8U) -#define DSI_REG_TIME_HS_ZERO_MSK (((1U << DSI_REG_TIME_HS_ZERO_LEN) - 1) << DSI_REG_TIME_HS_ZERO_POS) -#define DSI_REG_TIME_HS_ZERO_UMSK (~(((1U << DSI_REG_TIME_HS_ZERO_LEN) - 1) << DSI_REG_TIME_HS_ZERO_POS)) -#define DSI_REG_TIME_HS_TRAIL DSI_REG_TIME_HS_TRAIL -#define DSI_REG_TIME_HS_TRAIL_POS (8U) -#define DSI_REG_TIME_HS_TRAIL_LEN (8U) -#define DSI_REG_TIME_HS_TRAIL_MSK (((1U << DSI_REG_TIME_HS_TRAIL_LEN) - 1) << DSI_REG_TIME_HS_TRAIL_POS) -#define DSI_REG_TIME_HS_TRAIL_UMSK (~(((1U << DSI_REG_TIME_HS_TRAIL_LEN) - 1) << DSI_REG_TIME_HS_TRAIL_POS)) -#define DSI_REG_TIME_HS_PREP DSI_REG_TIME_HS_PREP -#define DSI_REG_TIME_HS_PREP_POS (16U) -#define DSI_REG_TIME_HS_PREP_LEN (8U) -#define DSI_REG_TIME_HS_PREP_MSK (((1U << DSI_REG_TIME_HS_PREP_LEN) - 1) << DSI_REG_TIME_HS_PREP_POS) -#define DSI_REG_TIME_HS_PREP_UMSK (~(((1U << DSI_REG_TIME_HS_PREP_LEN) - 1) << DSI_REG_TIME_HS_PREP_POS)) -#define DSI_REG_TIME_HS_EXIT DSI_REG_TIME_HS_EXIT -#define DSI_REG_TIME_HS_EXIT_POS (24U) -#define DSI_REG_TIME_HS_EXIT_LEN (8U) -#define DSI_REG_TIME_HS_EXIT_MSK (((1U << DSI_REG_TIME_HS_EXIT_LEN) - 1) << DSI_REG_TIME_HS_EXIT_POS) -#define DSI_REG_TIME_HS_EXIT_UMSK (~(((1U << DSI_REG_TIME_HS_EXIT_LEN) - 1) << DSI_REG_TIME_HS_EXIT_POS)) - -/* 0x8C : dphy_config_3 */ -#define DSI_DPHY_CONFIG_3_OFFSET (0x8C) -#define DSI_REG_TIME_TA_GO DSI_REG_TIME_TA_GO -#define DSI_REG_TIME_TA_GO_POS (0U) -#define DSI_REG_TIME_TA_GO_LEN (8U) -#define DSI_REG_TIME_TA_GO_MSK (((1U << DSI_REG_TIME_TA_GO_LEN) - 1) << DSI_REG_TIME_TA_GO_POS) -#define DSI_REG_TIME_TA_GO_UMSK (~(((1U << DSI_REG_TIME_TA_GO_LEN) - 1) << DSI_REG_TIME_TA_GO_POS)) -#define DSI_REG_TIME_TA_GET DSI_REG_TIME_TA_GET -#define DSI_REG_TIME_TA_GET_POS (8U) -#define DSI_REG_TIME_TA_GET_LEN (8U) -#define DSI_REG_TIME_TA_GET_MSK (((1U << DSI_REG_TIME_TA_GET_LEN) - 1) << DSI_REG_TIME_TA_GET_POS) -#define DSI_REG_TIME_TA_GET_UMSK (~(((1U << DSI_REG_TIME_TA_GET_LEN) - 1) << DSI_REG_TIME_TA_GET_POS)) -#define DSI_REG_TIME_REQRDY DSI_REG_TIME_REQRDY -#define DSI_REG_TIME_REQRDY_POS (16U) -#define DSI_REG_TIME_REQRDY_LEN (8U) -#define DSI_REG_TIME_REQRDY_MSK (((1U << DSI_REG_TIME_REQRDY_LEN) - 1) << DSI_REG_TIME_REQRDY_POS) -#define DSI_REG_TIME_REQRDY_UMSK (~(((1U << DSI_REG_TIME_REQRDY_LEN) - 1) << DSI_REG_TIME_REQRDY_POS)) -#define DSI_REG_TIME_LPX DSI_REG_TIME_LPX -#define DSI_REG_TIME_LPX_POS (24U) -#define DSI_REG_TIME_LPX_LEN (8U) -#define DSI_REG_TIME_LPX_MSK (((1U << DSI_REG_TIME_LPX_LEN) - 1) << DSI_REG_TIME_LPX_POS) -#define DSI_REG_TIME_LPX_UMSK (~(((1U << DSI_REG_TIME_LPX_LEN) - 1) << DSI_REG_TIME_LPX_POS)) - -/* 0x90 : dphy_config_4 */ -#define DSI_DPHY_CONFIG_4_OFFSET (0x90) -#define DSI_REG_TIME_WAKEUP DSI_REG_TIME_WAKEUP -#define DSI_REG_TIME_WAKEUP_POS (0U) -#define DSI_REG_TIME_WAKEUP_LEN (16U) -#define DSI_REG_TIME_WAKEUP_MSK (((1U << DSI_REG_TIME_WAKEUP_LEN) - 1) << DSI_REG_TIME_WAKEUP_POS) -#define DSI_REG_TIME_WAKEUP_UMSK (~(((1U << DSI_REG_TIME_WAKEUP_LEN) - 1) << DSI_REG_TIME_WAKEUP_POS)) - -/* 0x94 : dphy_config_5 */ -#define DSI_DPHY_CONFIG_5_OFFSET (0x94) -#define DSI_REG_TRIG3_CODE DSI_REG_TRIG3_CODE -#define DSI_REG_TRIG3_CODE_POS (0U) -#define DSI_REG_TRIG3_CODE_LEN (8U) -#define DSI_REG_TRIG3_CODE_MSK (((1U << DSI_REG_TRIG3_CODE_LEN) - 1) << DSI_REG_TRIG3_CODE_POS) -#define DSI_REG_TRIG3_CODE_UMSK (~(((1U << DSI_REG_TRIG3_CODE_LEN) - 1) << DSI_REG_TRIG3_CODE_POS)) -#define DSI_REG_TRIG2_CODE DSI_REG_TRIG2_CODE -#define DSI_REG_TRIG2_CODE_POS (8U) -#define DSI_REG_TRIG2_CODE_LEN (8U) -#define DSI_REG_TRIG2_CODE_MSK (((1U << DSI_REG_TRIG2_CODE_LEN) - 1) << DSI_REG_TRIG2_CODE_POS) -#define DSI_REG_TRIG2_CODE_UMSK (~(((1U << DSI_REG_TRIG2_CODE_LEN) - 1) << DSI_REG_TRIG2_CODE_POS)) -#define DSI_REG_TRIG1_CODE DSI_REG_TRIG1_CODE -#define DSI_REG_TRIG1_CODE_POS (16U) -#define DSI_REG_TRIG1_CODE_LEN (8U) -#define DSI_REG_TRIG1_CODE_MSK (((1U << DSI_REG_TRIG1_CODE_LEN) - 1) << DSI_REG_TRIG1_CODE_POS) -#define DSI_REG_TRIG1_CODE_UMSK (~(((1U << DSI_REG_TRIG1_CODE_LEN) - 1) << DSI_REG_TRIG1_CODE_POS)) -#define DSI_REG_TRIG0_CODE DSI_REG_TRIG0_CODE -#define DSI_REG_TRIG0_CODE_POS (24U) -#define DSI_REG_TRIG0_CODE_LEN (8U) -#define DSI_REG_TRIG0_CODE_MSK (((1U << DSI_REG_TRIG0_CODE_LEN) - 1) << DSI_REG_TRIG0_CODE_POS) -#define DSI_REG_TRIG0_CODE_UMSK (~(((1U << DSI_REG_TRIG0_CODE_LEN) - 1) << DSI_REG_TRIG0_CODE_POS)) - -/* 0x98 : dphy_config_6 */ -#define DSI_DPHY_CONFIG_6_OFFSET (0x98) -#define DSI_REG_ULPS_CODE DSI_REG_ULPS_CODE -#define DSI_REG_ULPS_CODE_POS (0U) -#define DSI_REG_ULPS_CODE_LEN (8U) -#define DSI_REG_ULPS_CODE_MSK (((1U << DSI_REG_ULPS_CODE_LEN) - 1) << DSI_REG_ULPS_CODE_POS) -#define DSI_REG_ULPS_CODE_UMSK (~(((1U << DSI_REG_ULPS_CODE_LEN) - 1) << DSI_REG_ULPS_CODE_POS)) -#define DSI_REG_LPDT_CODE DSI_REG_LPDT_CODE -#define DSI_REG_LPDT_CODE_POS (8U) -#define DSI_REG_LPDT_CODE_LEN (8U) -#define DSI_REG_LPDT_CODE_MSK (((1U << DSI_REG_LPDT_CODE_LEN) - 1) << DSI_REG_LPDT_CODE_POS) -#define DSI_REG_LPDT_CODE_UMSK (~(((1U << DSI_REG_LPDT_CODE_LEN) - 1) << DSI_REG_LPDT_CODE_POS)) - -/* 0x9C : dphy_config_7 */ -#define DSI_DPHY_CONFIG_7_OFFSET (0x9C) -#define DSI_REG_ANA_TEST_EN DSI_REG_ANA_TEST_EN -#define DSI_REG_ANA_TEST_EN_POS (0U) -#define DSI_REG_ANA_TEST_EN_LEN (1U) -#define DSI_REG_ANA_TEST_EN_MSK (((1U << DSI_REG_ANA_TEST_EN_LEN) - 1) << DSI_REG_ANA_TEST_EN_POS) -#define DSI_REG_ANA_TEST_EN_UMSK (~(((1U << DSI_REG_ANA_TEST_EN_LEN) - 1) << DSI_REG_ANA_TEST_EN_POS)) -#define DSI_REG_PT_EN DSI_REG_PT_EN -#define DSI_REG_PT_EN_POS (1U) -#define DSI_REG_PT_EN_LEN (1U) -#define DSI_REG_PT_EN_MSK (((1U << DSI_REG_PT_EN_LEN) - 1) << DSI_REG_PT_EN_POS) -#define DSI_REG_PT_EN_UMSK (~(((1U << DSI_REG_PT_EN_LEN) - 1) << DSI_REG_PT_EN_POS)) -#define DSI_REG_PT_LP_MODE DSI_REG_PT_LP_MODE -#define DSI_REG_PT_LP_MODE_POS (2U) -#define DSI_REG_PT_LP_MODE_LEN (1U) -#define DSI_REG_PT_LP_MODE_MSK (((1U << DSI_REG_PT_LP_MODE_LEN) - 1) << DSI_REG_PT_LP_MODE_POS) -#define DSI_REG_PT_LP_MODE_UMSK (~(((1U << DSI_REG_PT_LP_MODE_LEN) - 1) << DSI_REG_PT_LP_MODE_POS)) -#define DSI_REG_PT_PRBS_OR_JITT DSI_REG_PT_PRBS_OR_JITT -#define DSI_REG_PT_PRBS_OR_JITT_POS (3U) -#define DSI_REG_PT_PRBS_OR_JITT_LEN (1U) -#define DSI_REG_PT_PRBS_OR_JITT_MSK (((1U << DSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << DSI_REG_PT_PRBS_OR_JITT_POS) -#define DSI_REG_PT_PRBS_OR_JITT_UMSK (~(((1U << DSI_REG_PT_PRBS_OR_JITT_LEN) - 1) << DSI_REG_PT_PRBS_OR_JITT_POS)) -#define DSI_REG_FORCE_HIZ_LP DSI_REG_FORCE_HIZ_LP -#define DSI_REG_FORCE_HIZ_LP_POS (4U) -#define DSI_REG_FORCE_HIZ_LP_LEN (4U) -#define DSI_REG_FORCE_HIZ_LP_MSK (((1U << DSI_REG_FORCE_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_HIZ_LP_POS) -#define DSI_REG_FORCE_HIZ_LP_UMSK (~(((1U << DSI_REG_FORCE_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_HIZ_LP_POS)) -#define DSI_REG_FORCE_HIZ_HS DSI_REG_FORCE_HIZ_HS -#define DSI_REG_FORCE_HIZ_HS_POS (8U) -#define DSI_REG_FORCE_HIZ_HS_LEN (4U) -#define DSI_REG_FORCE_HIZ_HS_MSK (((1U << DSI_REG_FORCE_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_HIZ_HS_POS) -#define DSI_REG_FORCE_HIZ_HS_UMSK (~(((1U << DSI_REG_FORCE_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_HIZ_HS_POS)) -#define DSI_REG_FORCE_CLK_HIZ_LP DSI_REG_FORCE_CLK_HIZ_LP -#define DSI_REG_FORCE_CLK_HIZ_LP_POS (12U) -#define DSI_REG_FORCE_CLK_HIZ_LP_LEN (1U) -#define DSI_REG_FORCE_CLK_HIZ_LP_MSK (((1U << DSI_REG_FORCE_CLK_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_LP_POS) -#define DSI_REG_FORCE_CLK_HIZ_LP_UMSK (~(((1U << DSI_REG_FORCE_CLK_HIZ_LP_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_LP_POS)) -#define DSI_REG_FORCE_CLK_HIZ_HS DSI_REG_FORCE_CLK_HIZ_HS -#define DSI_REG_FORCE_CLK_HIZ_HS_POS (13U) -#define DSI_REG_FORCE_CLK_HIZ_HS_LEN (1U) -#define DSI_REG_FORCE_CLK_HIZ_HS_MSK (((1U << DSI_REG_FORCE_CLK_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_HS_POS) -#define DSI_REG_FORCE_CLK_HIZ_HS_UMSK (~(((1U << DSI_REG_FORCE_CLK_HIZ_HS_LEN) - 1) << DSI_REG_FORCE_CLK_HIZ_HS_POS)) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC DSI_REG_ANA_LP_TXEN_CLKLANE_ESC -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_POS (14U) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_POS) -#define DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_TXEN_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_POS (15U) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_POS) -#define DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DPTXDATA_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_POS (16U) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_POS) -#define DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_LP_DNTXDATA_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC DSI_REG_ANA_HS_TXEN_CLKLANE_ESC -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_POS (17U) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_LEN (1U) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_MSK (((1U << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_POS) -#define DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_UMSK (~(((1U << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_LEN) - 1) << DSI_REG_ANA_HS_TXEN_CLKLANE_ESC_POS)) -#define DSI_REG_ANA_CLK_EN_ESC DSI_REG_ANA_CLK_EN_ESC -#define DSI_REG_ANA_CLK_EN_ESC_POS (18U) -#define DSI_REG_ANA_CLK_EN_ESC_LEN (1U) -#define DSI_REG_ANA_CLK_EN_ESC_MSK (((1U << DSI_REG_ANA_CLK_EN_ESC_LEN) - 1) << DSI_REG_ANA_CLK_EN_ESC_POS) -#define DSI_REG_ANA_CLK_EN_ESC_UMSK (~(((1U << DSI_REG_ANA_CLK_EN_ESC_LEN) - 1) << DSI_REG_ANA_CLK_EN_ESC_POS)) -#define DSI_REG_ANA_BYTE_REV DSI_REG_ANA_BYTE_REV -#define DSI_REG_ANA_BYTE_REV_POS (19U) -#define DSI_REG_ANA_BYTE_REV_LEN (1U) -#define DSI_REG_ANA_BYTE_REV_MSK (((1U << DSI_REG_ANA_BYTE_REV_LEN) - 1) << DSI_REG_ANA_BYTE_REV_POS) -#define DSI_REG_ANA_BYTE_REV_UMSK (~(((1U << DSI_REG_ANA_BYTE_REV_LEN) - 1) << DSI_REG_ANA_BYTE_REV_POS)) - -/* 0xA0 : dphy_config_8 */ -#define DSI_DPHY_CONFIG_8_OFFSET (0xA0) -#define DSI_REG_ANA_LPTXP_DATA DSI_REG_ANA_LPTXP_DATA -#define DSI_REG_ANA_LPTXP_DATA_POS (0U) -#define DSI_REG_ANA_LPTXP_DATA_LEN (4U) -#define DSI_REG_ANA_LPTXP_DATA_MSK (((1U << DSI_REG_ANA_LPTXP_DATA_LEN) - 1) << DSI_REG_ANA_LPTXP_DATA_POS) -#define DSI_REG_ANA_LPTXP_DATA_UMSK (~(((1U << DSI_REG_ANA_LPTXP_DATA_LEN) - 1) << DSI_REG_ANA_LPTXP_DATA_POS)) -#define DSI_REG_ANA_LPTXN_DATA DSI_REG_ANA_LPTXN_DATA -#define DSI_REG_ANA_LPTXN_DATA_POS (4U) -#define DSI_REG_ANA_LPTXN_DATA_LEN (4U) -#define DSI_REG_ANA_LPTXN_DATA_MSK (((1U << DSI_REG_ANA_LPTXN_DATA_LEN) - 1) << DSI_REG_ANA_LPTXN_DATA_POS) -#define DSI_REG_ANA_LPTXN_DATA_UMSK (~(((1U << DSI_REG_ANA_LPTXN_DATA_LEN) - 1) << DSI_REG_ANA_LPTXN_DATA_POS)) -#define DSI_REG_ANA_LPTXEN DSI_REG_ANA_LPTXEN -#define DSI_REG_ANA_LPTXEN_POS (8U) -#define DSI_REG_ANA_LPTXEN_LEN (4U) -#define DSI_REG_ANA_LPTXEN_MSK (((1U << DSI_REG_ANA_LPTXEN_LEN) - 1) << DSI_REG_ANA_LPTXEN_POS) -#define DSI_REG_ANA_LPTXEN_UMSK (~(((1U << DSI_REG_ANA_LPTXEN_LEN) - 1) << DSI_REG_ANA_LPTXEN_POS)) -#define DSI_REG_ANA_LPRXEN DSI_REG_ANA_LPRXEN -#define DSI_REG_ANA_LPRXEN_POS (12U) -#define DSI_REG_ANA_LPRXEN_LEN (4U) -#define DSI_REG_ANA_LPRXEN_MSK (((1U << DSI_REG_ANA_LPRXEN_LEN) - 1) << DSI_REG_ANA_LPRXEN_POS) -#define DSI_REG_ANA_LPRXEN_UMSK (~(((1U << DSI_REG_ANA_LPRXEN_LEN) - 1) << DSI_REG_ANA_LPRXEN_POS)) -#define DSI_REG_ANA_HSTXEN DSI_REG_ANA_HSTXEN -#define DSI_REG_ANA_HSTXEN_POS (16U) -#define DSI_REG_ANA_HSTXEN_LEN (4U) -#define DSI_REG_ANA_HSTXEN_MSK (((1U << DSI_REG_ANA_HSTXEN_LEN) - 1) << DSI_REG_ANA_HSTXEN_POS) -#define DSI_REG_ANA_HSTXEN_UMSK (~(((1U << DSI_REG_ANA_HSTXEN_LEN) - 1) << DSI_REG_ANA_HSTXEN_POS)) -#define DSI_REG_ANA_HS_TRAIL_BYTE DSI_REG_ANA_HS_TRAIL_BYTE -#define DSI_REG_ANA_HS_TRAIL_BYTE_POS (20U) -#define DSI_REG_ANA_HS_TRAIL_BYTE_LEN (4U) -#define DSI_REG_ANA_HS_TRAIL_BYTE_MSK (((1U << DSI_REG_ANA_HS_TRAIL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_TRAIL_BYTE_POS) -#define DSI_REG_ANA_HS_TRAIL_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_TRAIL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_TRAIL_BYTE_POS)) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE DSI_REG_ANA_HS_SYNC_LD_BYTE -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_POS (24U) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_LEN (4U) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_MSK (((1U << DSI_REG_ANA_HS_SYNC_LD_BYTE_LEN) - 1) << DSI_REG_ANA_HS_SYNC_LD_BYTE_POS) -#define DSI_REG_ANA_HS_SYNC_LD_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_SYNC_LD_BYTE_LEN) - 1) << DSI_REG_ANA_HS_SYNC_LD_BYTE_POS)) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE DSI_REG_ANA_HS_P2S_SEL_BYTE -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_POS (28U) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_LEN (4U) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_MSK (((1U << DSI_REG_ANA_HS_P2S_SEL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_P2S_SEL_BYTE_POS) -#define DSI_REG_ANA_HS_P2S_SEL_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_P2S_SEL_BYTE_LEN) - 1) << DSI_REG_ANA_HS_P2S_SEL_BYTE_POS)) - -/* 0xA4 : dphy_config_9 */ -#define DSI_DPHY_CONFIG_9_OFFSET (0xA4) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE DSI_REG_ANA_HS_DATA_OUT_BYTE -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_POS (0U) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_LEN (32U) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_MSK (((1U << DSI_REG_ANA_HS_DATA_OUT_BYTE_LEN) - 1) << DSI_REG_ANA_HS_DATA_OUT_BYTE_POS) -#define DSI_REG_ANA_HS_DATA_OUT_BYTE_UMSK (~(((1U << DSI_REG_ANA_HS_DATA_OUT_BYTE_LEN) - 1) << DSI_REG_ANA_HS_DATA_OUT_BYTE_POS)) - -/* 0xA8 : dphy_config_10 */ -#define DSI_DPHY_CONFIG_10_OFFSET (0xA8) -#define DSI_REG_TESTBUS_SEL_LO DSI_REG_TESTBUS_SEL_LO -#define DSI_REG_TESTBUS_SEL_LO_POS (0U) -#define DSI_REG_TESTBUS_SEL_LO_LEN (4U) -#define DSI_REG_TESTBUS_SEL_LO_MSK (((1U << DSI_REG_TESTBUS_SEL_LO_LEN) - 1) << DSI_REG_TESTBUS_SEL_LO_POS) -#define DSI_REG_TESTBUS_SEL_LO_UMSK (~(((1U << DSI_REG_TESTBUS_SEL_LO_LEN) - 1) << DSI_REG_TESTBUS_SEL_LO_POS)) -#define DSI_REG_TESTBUS_SEL_HI DSI_REG_TESTBUS_SEL_HI -#define DSI_REG_TESTBUS_SEL_HI_POS (4U) -#define DSI_REG_TESTBUS_SEL_HI_LEN (4U) -#define DSI_REG_TESTBUS_SEL_HI_MSK (((1U << DSI_REG_TESTBUS_SEL_HI_LEN) - 1) << DSI_REG_TESTBUS_SEL_HI_POS) -#define DSI_REG_TESTBUS_SEL_HI_UMSK (~(((1U << DSI_REG_TESTBUS_SEL_HI_LEN) - 1) << DSI_REG_TESTBUS_SEL_HI_POS)) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE DSI_REG_TESTBUS_HI8BSEL_8BMODE -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_POS (8U) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_LEN (1U) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_MSK (((1U << DSI_REG_TESTBUS_HI8BSEL_8BMODE_LEN) - 1) << DSI_REG_TESTBUS_HI8BSEL_8BMODE_POS) -#define DSI_REG_TESTBUS_HI8BSEL_8BMODE_UMSK (~(((1U << DSI_REG_TESTBUS_HI8BSEL_8BMODE_LEN) - 1) << DSI_REG_TESTBUS_HI8BSEL_8BMODE_POS)) -#define DSI_REG_IMP_PU_CODE DSI_REG_IMP_PU_CODE -#define DSI_REG_IMP_PU_CODE_POS (9U) -#define DSI_REG_IMP_PU_CODE_LEN (5U) -#define DSI_REG_IMP_PU_CODE_MSK (((1U << DSI_REG_IMP_PU_CODE_LEN) - 1) << DSI_REG_IMP_PU_CODE_POS) -#define DSI_REG_IMP_PU_CODE_UMSK (~(((1U << DSI_REG_IMP_PU_CODE_LEN) - 1) << DSI_REG_IMP_PU_CODE_POS)) -#define DSI_REG_IMP_PD_CODE DSI_REG_IMP_PD_CODE -#define DSI_REG_IMP_PD_CODE_POS (14U) -#define DSI_REG_IMP_PD_CODE_LEN (5U) -#define DSI_REG_IMP_PD_CODE_MSK (((1U << DSI_REG_IMP_PD_CODE_LEN) - 1) << DSI_REG_IMP_PD_CODE_POS) -#define DSI_REG_IMP_PD_CODE_UMSK (~(((1U << DSI_REG_IMP_PD_CODE_LEN) - 1) << DSI_REG_IMP_PD_CODE_POS)) -#define DSI_REG_DPHY_VREG400MV_TRIM DSI_REG_DPHY_VREG400MV_TRIM -#define DSI_REG_DPHY_VREG400MV_TRIM_POS (19U) -#define DSI_REG_DPHY_VREG400MV_TRIM_LEN (3U) -#define DSI_REG_DPHY_VREG400MV_TRIM_MSK (((1U << DSI_REG_DPHY_VREG400MV_TRIM_LEN) - 1) << DSI_REG_DPHY_VREG400MV_TRIM_POS) -#define DSI_REG_DPHY_VREG400MV_TRIM_UMSK (~(((1U << DSI_REG_DPHY_VREG400MV_TRIM_LEN) - 1) << DSI_REG_DPHY_VREG400MV_TRIM_POS)) -#define DSI_REG_DPHY_BG_VREF_EN DSI_REG_DPHY_BG_VREF_EN -#define DSI_REG_DPHY_BG_VREF_EN_POS (22U) -#define DSI_REG_DPHY_BG_VREF_EN_LEN (1U) -#define DSI_REG_DPHY_BG_VREF_EN_MSK (((1U << DSI_REG_DPHY_BG_VREF_EN_LEN) - 1) << DSI_REG_DPHY_BG_VREF_EN_POS) -#define DSI_REG_DPHY_BG_VREF_EN_UMSK (~(((1U << DSI_REG_DPHY_BG_VREF_EN_LEN) - 1) << DSI_REG_DPHY_BG_VREF_EN_POS)) -#define DSI_REG_ANA_BG_VREF_EN DSI_REG_ANA_BG_VREF_EN -#define DSI_REG_ANA_BG_VREF_EN_POS (23U) -#define DSI_REG_ANA_BG_VREF_EN_LEN (1U) -#define DSI_REG_ANA_BG_VREF_EN_MSK (((1U << DSI_REG_ANA_BG_VREF_EN_LEN) - 1) << DSI_REG_ANA_BG_VREF_EN_POS) -#define DSI_REG_ANA_BG_VREF_EN_UMSK (~(((1U << DSI_REG_ANA_BG_VREF_EN_LEN) - 1) << DSI_REG_ANA_BG_VREF_EN_POS)) -#define DSI_REG_ANA_VREG400MV_TRIM DSI_REG_ANA_VREG400MV_TRIM -#define DSI_REG_ANA_VREG400MV_TRIM_POS (24U) -#define DSI_REG_ANA_VREG400MV_TRIM_LEN (3U) -#define DSI_REG_ANA_VREG400MV_TRIM_MSK (((1U << DSI_REG_ANA_VREG400MV_TRIM_LEN) - 1) << DSI_REG_ANA_VREG400MV_TRIM_POS) -#define DSI_REG_ANA_VREG400MV_TRIM_UMSK (~(((1U << DSI_REG_ANA_VREG400MV_TRIM_LEN) - 1) << DSI_REG_ANA_VREG400MV_TRIM_POS)) -#define DSI_REG_ANA_VREF_EN DSI_REG_ANA_VREF_EN -#define DSI_REG_ANA_VREF_EN_POS (27U) -#define DSI_REG_ANA_VREF_EN_LEN (1U) -#define DSI_REG_ANA_VREF_EN_MSK (((1U << DSI_REG_ANA_VREF_EN_LEN) - 1) << DSI_REG_ANA_VREF_EN_POS) -#define DSI_REG_ANA_VREF_EN_UMSK (~(((1U << DSI_REG_ANA_VREF_EN_LEN) - 1) << DSI_REG_ANA_VREF_EN_POS)) - -/* 0xAC : dphy_config_11 */ -#define DSI_DPHY_CONFIG_11_OFFSET (0xAC) -#define DSI_REG_DSI_ANA_0 DSI_REG_DSI_ANA_0 -#define DSI_REG_DSI_ANA_0_POS (0U) -#define DSI_REG_DSI_ANA_0_LEN (16U) -#define DSI_REG_DSI_ANA_0_MSK (((1U << DSI_REG_DSI_ANA_0_LEN) - 1) << DSI_REG_DSI_ANA_0_POS) -#define DSI_REG_DSI_ANA_0_UMSK (~(((1U << DSI_REG_DSI_ANA_0_LEN) - 1) << DSI_REG_DSI_ANA_0_POS)) -#define DSI_REG_DSI_ANA_1 DSI_REG_DSI_ANA_1 -#define DSI_REG_DSI_ANA_1_POS (16U) -#define DSI_REG_DSI_ANA_1_LEN (16U) -#define DSI_REG_DSI_ANA_1_MSK (((1U << DSI_REG_DSI_ANA_1_LEN) - 1) << DSI_REG_DSI_ANA_1_POS) -#define DSI_REG_DSI_ANA_1_UMSK (~(((1U << DSI_REG_DSI_ANA_1_LEN) - 1) << DSI_REG_DSI_ANA_1_POS)) - -/* 0xB0 : dphy_config_12 */ -#define DSI_DPHY_CONFIG_12_OFFSET (0xB0) -#define DSI_REG_DSI_ANA_2 DSI_REG_DSI_ANA_2 -#define DSI_REG_DSI_ANA_2_POS (0U) -#define DSI_REG_DSI_ANA_2_LEN (16U) -#define DSI_REG_DSI_ANA_2_MSK (((1U << DSI_REG_DSI_ANA_2_LEN) - 1) << DSI_REG_DSI_ANA_2_POS) -#define DSI_REG_DSI_ANA_2_UMSK (~(((1U << DSI_REG_DSI_ANA_2_LEN) - 1) << DSI_REG_DSI_ANA_2_POS)) - -/* 0xB4 : dphy_config_13 */ -#define DSI_DPHY_CONFIG_13_OFFSET (0xB4) -#define DSI_REG_RD_DIG_TEST_BUS DSI_REG_RD_DIG_TEST_BUS -#define DSI_REG_RD_DIG_TEST_BUS_POS (0U) -#define DSI_REG_RD_DIG_TEST_BUS_LEN (16U) -#define DSI_REG_RD_DIG_TEST_BUS_MSK (((1U << DSI_REG_RD_DIG_TEST_BUS_LEN) - 1) << DSI_REG_RD_DIG_TEST_BUS_POS) -#define DSI_REG_RD_DIG_TEST_BUS_UMSK (~(((1U << DSI_REG_RD_DIG_TEST_BUS_LEN) - 1) << DSI_REG_RD_DIG_TEST_BUS_POS)) - -/* 0xB8 : dphy_config_14 */ -#define DSI_DPHY_CONFIG_14_OFFSET (0xB8) -#define DSI_REG_PT_FREE_REP_PAT DSI_REG_PT_FREE_REP_PAT -#define DSI_REG_PT_FREE_REP_PAT_POS (0U) -#define DSI_REG_PT_FREE_REP_PAT_LEN (32U) -#define DSI_REG_PT_FREE_REP_PAT_MSK (((1U << DSI_REG_PT_FREE_REP_PAT_LEN) - 1) << DSI_REG_PT_FREE_REP_PAT_POS) -#define DSI_REG_PT_FREE_REP_PAT_UMSK (~(((1U << DSI_REG_PT_FREE_REP_PAT_LEN) - 1) << DSI_REG_PT_FREE_REP_PAT_POS)) - -/* 0xBC : dphy_config_15 */ -#define DSI_DPHY_CONFIG_15_OFFSET (0xBC) -#define DSI_REG_DSI_DC_TP_OUT_EN DSI_REG_DSI_DC_TP_OUT_EN -#define DSI_REG_DSI_DC_TP_OUT_EN_POS (0U) -#define DSI_REG_DSI_DC_TP_OUT_EN_LEN (1U) -#define DSI_REG_DSI_DC_TP_OUT_EN_MSK (((1U << DSI_REG_DSI_DC_TP_OUT_EN_LEN) - 1) << DSI_REG_DSI_DC_TP_OUT_EN_POS) -#define DSI_REG_DSI_DC_TP_OUT_EN_UMSK (~(((1U << DSI_REG_DSI_DC_TP_OUT_EN_LEN) - 1) << DSI_REG_DSI_DC_TP_OUT_EN_POS)) -#define DSI_REG_DSI_PW_AVDD1815 DSI_REG_DSI_PW_AVDD1815 -#define DSI_REG_DSI_PW_AVDD1815_POS (4U) -#define DSI_REG_DSI_PW_AVDD1815_LEN (1U) -#define DSI_REG_DSI_PW_AVDD1815_MSK (((1U << DSI_REG_DSI_PW_AVDD1815_LEN) - 1) << DSI_REG_DSI_PW_AVDD1815_POS) -#define DSI_REG_DSI_PW_AVDD1815_UMSK (~(((1U << DSI_REG_DSI_PW_AVDD1815_LEN) - 1) << DSI_REG_DSI_PW_AVDD1815_POS)) -#define DSI_REG_DPHY_PU_LDO11 DSI_REG_DPHY_PU_LDO11 -#define DSI_REG_DPHY_PU_LDO11_POS (8U) -#define DSI_REG_DPHY_PU_LDO11_LEN (1U) -#define DSI_REG_DPHY_PU_LDO11_MSK (((1U << DSI_REG_DPHY_PU_LDO11_LEN) - 1) << DSI_REG_DPHY_PU_LDO11_POS) -#define DSI_REG_DPHY_PU_LDO11_UMSK (~(((1U << DSI_REG_DPHY_PU_LDO11_LEN) - 1) << DSI_REG_DPHY_PU_LDO11_POS)) -#define DSI_REG_DPHY_SHORT_LDO11 DSI_REG_DPHY_SHORT_LDO11 -#define DSI_REG_DPHY_SHORT_LDO11_POS (12U) -#define DSI_REG_DPHY_SHORT_LDO11_LEN (1U) -#define DSI_REG_DPHY_SHORT_LDO11_MSK (((1U << DSI_REG_DPHY_SHORT_LDO11_LEN) - 1) << DSI_REG_DPHY_SHORT_LDO11_POS) -#define DSI_REG_DPHY_SHORT_LDO11_UMSK (~(((1U << DSI_REG_DPHY_SHORT_LDO11_LEN) - 1) << DSI_REG_DPHY_SHORT_LDO11_POS)) -#define DSI_REG_DPHY_LDO11_RFB_SW DSI_REG_DPHY_LDO11_RFB_SW -#define DSI_REG_DPHY_LDO11_RFB_SW_POS (16U) -#define DSI_REG_DPHY_LDO11_RFB_SW_LEN (3U) -#define DSI_REG_DPHY_LDO11_RFB_SW_MSK (((1U << DSI_REG_DPHY_LDO11_RFB_SW_LEN) - 1) << DSI_REG_DPHY_LDO11_RFB_SW_POS) -#define DSI_REG_DPHY_LDO11_RFB_SW_UMSK (~(((1U << DSI_REG_DPHY_LDO11_RFB_SW_LEN) - 1) << DSI_REG_DPHY_LDO11_RFB_SW_POS)) -#define DSI_REG_TEN_DSI_LDO DSI_REG_TEN_DSI_LDO -#define DSI_REG_TEN_DSI_LDO_POS (20U) -#define DSI_REG_TEN_DSI_LDO_LEN (1U) -#define DSI_REG_TEN_DSI_LDO_MSK (((1U << DSI_REG_TEN_DSI_LDO_LEN) - 1) << DSI_REG_TEN_DSI_LDO_POS) -#define DSI_REG_TEN_DSI_LDO_UMSK (~(((1U << DSI_REG_TEN_DSI_LDO_LEN) - 1) << DSI_REG_TEN_DSI_LDO_POS)) -#define DSI_REG_MIPI_LDO_FAST DSI_REG_MIPI_LDO_FAST -#define DSI_REG_MIPI_LDO_FAST_POS (24U) -#define DSI_REG_MIPI_LDO_FAST_LEN (1U) -#define DSI_REG_MIPI_LDO_FAST_MSK (((1U << DSI_REG_MIPI_LDO_FAST_LEN) - 1) << DSI_REG_MIPI_LDO_FAST_POS) -#define DSI_REG_MIPI_LDO_FAST_UMSK (~(((1U << DSI_REG_MIPI_LDO_FAST_LEN) - 1) << DSI_REG_MIPI_LDO_FAST_POS)) -#define DSI_REG_DSI_RST_N_PRE DSI_REG_DSI_RST_N_PRE -#define DSI_REG_DSI_RST_N_PRE_POS (28U) -#define DSI_REG_DSI_RST_N_PRE_LEN (1U) -#define DSI_REG_DSI_RST_N_PRE_MSK (((1U << DSI_REG_DSI_RST_N_PRE_LEN) - 1) << DSI_REG_DSI_RST_N_PRE_POS) -#define DSI_REG_DSI_RST_N_PRE_UMSK (~(((1U << DSI_REG_DSI_RST_N_PRE_LEN) - 1) << DSI_REG_DSI_RST_N_PRE_POS)) -#define DSI_REG_CSI_RST_N_PRE DSI_REG_CSI_RST_N_PRE -#define DSI_REG_CSI_RST_N_PRE_POS (29U) -#define DSI_REG_CSI_RST_N_PRE_LEN (1U) -#define DSI_REG_CSI_RST_N_PRE_MSK (((1U << DSI_REG_CSI_RST_N_PRE_LEN) - 1) << DSI_REG_CSI_RST_N_PRE_POS) -#define DSI_REG_CSI_RST_N_PRE_UMSK (~(((1U << DSI_REG_CSI_RST_N_PRE_LEN) - 1) << DSI_REG_CSI_RST_N_PRE_POS)) - -/* 0xC0 : dphy_config_16 */ -#define DSI_DPHY_CONFIG_16_OFFSET (0xC0) -#define DSI_REG_DSI_BYTE_CLK_INV DSI_REG_DSI_BYTE_CLK_INV -#define DSI_REG_DSI_BYTE_CLK_INV_POS (0U) -#define DSI_REG_DSI_BYTE_CLK_INV_LEN (1U) -#define DSI_REG_DSI_BYTE_CLK_INV_MSK (((1U << DSI_REG_DSI_BYTE_CLK_INV_LEN) - 1) << DSI_REG_DSI_BYTE_CLK_INV_POS) -#define DSI_REG_DSI_BYTE_CLK_INV_UMSK (~(((1U << DSI_REG_DSI_BYTE_CLK_INV_LEN) - 1) << DSI_REG_DSI_BYTE_CLK_INV_POS)) -#define DSI_REG_DSI_LPRX_CLK_INV DSI_REG_DSI_LPRX_CLK_INV -#define DSI_REG_DSI_LPRX_CLK_INV_POS (1U) -#define DSI_REG_DSI_LPRX_CLK_INV_LEN (1U) -#define DSI_REG_DSI_LPRX_CLK_INV_MSK (((1U << DSI_REG_DSI_LPRX_CLK_INV_LEN) - 1) << DSI_REG_DSI_LPRX_CLK_INV_POS) -#define DSI_REG_DSI_LPRX_CLK_INV_UMSK (~(((1U << DSI_REG_DSI_LPRX_CLK_INV_LEN) - 1) << DSI_REG_DSI_LPRX_CLK_INV_POS)) - -/* 0xFC : dummy_reg */ -#define DSI_DUMMY_REG_OFFSET (0xFC) -#define DSI_DUMMY_REG DSI_DUMMY_REG -#define DSI_DUMMY_REG_POS (0U) -#define DSI_DUMMY_REG_LEN (32U) -#define DSI_DUMMY_REG_MSK (((1U << DSI_DUMMY_REG_LEN) - 1) << DSI_DUMMY_REG_POS) -#define DSI_DUMMY_REG_UMSK (~(((1U << DSI_DUMMY_REG_LEN) - 1) << DSI_DUMMY_REG_POS)) - -struct dsi_reg { - /* 0x0 : dsi_config */ - union { - struct { - uint32_t cr_hstx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_lane_num : 2; /* [ 2: 1], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_hstx_mode : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_lse_pkt_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_lane_mux_sel : 2; /* [ 7: 6], r/w, 0x0 */ - uint32_t cr_dt : 6; /* [13: 8], r/w, 0x3e */ - uint32_t cr_vc : 2; /* [15:14], r/w, 0x0 */ - uint32_t cr_hstx_vfp : 8; /* [23:16], r/w, 0x2 */ - uint32_t cr_hstx_vsa : 8; /* [31:24], r/w, 0x2 */ - } BF; - uint32_t WORD; - } dsi_config; - - /* 0x4 : dsi_esc_config */ - union { - struct { - uint32_t cr_esc_tx_en : 1; /* [ 0], w1p, 0x0 */ - uint32_t cr_esc_tx_mode : 2; /* [ 2: 1], r/w, 0x0 */ - uint32_t cr_esc_tx_ulps_exit : 1; /* [ 3], w1p, 0x0 */ - uint32_t cr_esc_tx_trig : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t cr_esc_rx_en : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t st_esc_rx_len : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } dsi_esc_config; - - /* 0x8 : dsi_lpdt_tx_config */ - union { - struct { - uint32_t cr_lpdt_pdlen : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t cr_lpdt_vc : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t cr_lpdt_di : 6; /* [15:10], r/w, 0x0 */ - uint32_t cr_lpdt_word0 : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_lpdt_word1 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsi_lpdt_tx_config; - - /* 0xC : dsi_hstx_config */ - union { - struct { - uint32_t cr_hstx_pc : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_hstx_out_th : 11; /* [26:16], r/w, 0x348 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_hstx_config; - - /* 0x10 : dsi_int_status */ - union { - struct { - uint32_t dsi_int_status : 14; /* [13: 0], r, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_status; - - /* 0x14 : dsi_int_mask */ - union { - struct { - uint32_t dsi_int_mask : 14; /* [13: 0], r/w, 0x3fff */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_mask; - - /* 0x18 : dsi_int_clear */ - union { - struct { - uint32_t dsi_int_clear : 14; /* [13: 0], w1p, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_clear; - - /* 0x1C : dsi_int_enable */ - union { - struct { - uint32_t dsi_int_enable : 14; /* [13: 0], r/w, 0x3fff */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_int_enable; - - /* 0x20 : dsi_frame_num */ - union { - struct { - uint32_t cr_frame_num : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_30 : 15; /* [30:16], rsvd, 0x0 */ - uint32_t cr_frame_upd : 1; /* [ 31], w1p, 0x0 */ - } BF; - uint32_t WORD; - } dsi_frame_num; - - /* 0x24 reserved */ - uint8_t RESERVED0x24[60]; - - /* 0x60 : dsi_fifo_config_0 */ - union { - struct { - uint32_t dsi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t dsi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1p, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1p, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_fifo_config_0; - - /* 0x64 : dsi_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 3; /* [10: 8], r, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */ - uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */ - uint32_t rx_fifo_th : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsi_fifo_config_1; - - /* 0x68 : dsi_fifo_wdata */ - union { - struct { - uint32_t dsi_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } dsi_fifo_wdata; - - /* 0x6C : dsi_fifo_rdata */ - union { - struct { - uint32_t dsi_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } dsi_fifo_rdata; - - /* 0x70 reserved */ - uint8_t RESERVED0x70[16]; - - /* 0x80 : dphy_config_0 */ - union { - struct { - uint32_t cl_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t cl_txrequesths : 1; /* [ 1], r/w, 0x0 */ - uint32_t cl_txulpsclk : 1; /* [ 2], r/w, 0x0 */ - uint32_t cl_txulpsexit : 1; /* [ 3], w1p, 0x0 */ - uint32_t cl_stopstate : 1; /* [ 4], r, 0x1 */ - uint32_t cl_ulpsactivenot : 1; /* [ 5], r, 0x1 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t dl0_enable : 1; /* [ 8], r/w, 0x0 */ - uint32_t dl1_enable : 1; /* [ 9], r/w, 0x0 */ - uint32_t dl2_enable : 1; /* [ 10], r/w, 0x0 */ - uint32_t dl3_enable : 1; /* [ 11], r/w, 0x0 */ - uint32_t dl0_stopstate : 1; /* [ 12], r, 0x1 */ - uint32_t dl1_stopstate : 1; /* [ 13], r, 0x1 */ - uint32_t dl2_stopstate : 1; /* [ 14], r, 0x1 */ - uint32_t dl3_stopstate : 1; /* [ 15], r, 0x1 */ - uint32_t dl0_ulpsactivenot : 1; /* [ 16], r, 0x1 */ - uint32_t dl1_ulpsactivenot : 1; /* [ 17], r, 0x1 */ - uint32_t dl2_ulpsactivenot : 1; /* [ 18], r, 0x1 */ - uint32_t dl3_ulpsactivenot : 1; /* [ 19], r, 0x1 */ - uint32_t dl0_forcerxmode : 1; /* [ 20], r/w, 0x0 */ - uint32_t dl1_forcerxmode : 1; /* [ 21], r/w, 0x0 */ - uint32_t dl2_forcerxmode : 1; /* [ 22], r/w, 0x0 */ - uint32_t dl3_forcerxmode : 1; /* [ 23], r/w, 0x0 */ - uint32_t dl0_forcetxstopmode : 1; /* [ 24], r/w, 0x0 */ - uint32_t dl1_forcetxstopmode : 1; /* [ 25], r/w, 0x0 */ - uint32_t dl2_forcetxstopmode : 1; /* [ 26], r/w, 0x0 */ - uint32_t dl3_forcetxstopmode : 1; /* [ 27], r/w, 0x0 */ - uint32_t reserved_28_29 : 2; /* [29:28], rsvd, 0x0 */ - uint32_t dl0_turnesc : 1; /* [ 30], w1p, 0x0 */ - uint32_t dsi_reset_n : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_0; - - /* 0x84 : dphy_config_1 */ - union { - struct { - uint32_t reg_time_ck_zero : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t reg_time_ck_trail : 8; /* [15: 8], r/w, 0x3 */ - uint32_t reg_time_ck_exit : 8; /* [23:16], r/w, 0x5 */ - uint32_t reg_en_lprx_at_ulps : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_1; - - /* 0x88 : dphy_config_2 */ - union { - struct { - uint32_t reg_time_hs_zero : 8; /* [ 7: 0], r/w, 0x5 */ - uint32_t reg_time_hs_trail : 8; /* [15: 8], r/w, 0x3 */ - uint32_t reg_time_hs_prep : 8; /* [23:16], r/w, 0x2 */ - uint32_t reg_time_hs_exit : 8; /* [31:24], r/w, 0x5 */ - } BF; - uint32_t WORD; - } dphy_config_2; - - /* 0x8C : dphy_config_3 */ - union { - struct { - uint32_t reg_time_ta_go : 8; /* [ 7: 0], r/w, 0xc */ - uint32_t reg_time_ta_get : 8; /* [15: 8], r/w, 0xf */ - uint32_t reg_time_reqrdy : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_time_lpx : 8; /* [31:24], r/w, 0x3 */ - } BF; - uint32_t WORD; - } dphy_config_3; - - /* 0x90 : dphy_config_4 */ - union { - struct { - uint32_t reg_time_wakeup : 16; /* [15: 0], r/w, 0x9c41 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_4; - - /* 0x94 : dphy_config_5 */ - union { - struct { - uint32_t reg_trig3_code : 8; /* [ 7: 0], r/w, 0x5 */ - uint32_t reg_trig2_code : 8; /* [15: 8], r/w, 0x84 */ - uint32_t reg_trig1_code : 8; /* [23:16], r/w, 0xba */ - uint32_t reg_trig0_code : 8; /* [31:24], r/w, 0x46 */ - } BF; - uint32_t WORD; - } dphy_config_5; - - /* 0x98 : dphy_config_6 */ - union { - struct { - uint32_t reg_ulps_code : 8; /* [ 7: 0], r/w, 0x78 */ - uint32_t reg_lpdt_code : 8; /* [15: 8], r/w, 0x87 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_6; - - /* 0x9C : dphy_config_7 */ - union { - struct { - uint32_t reg_ana_test_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_pt_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_pt_lp_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_pt_prbs_or_jitt : 1; /* [ 3], r/w, 0x0 */ - uint32_t reg_force_hiz_lp : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_force_hiz_hs : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reg_force_clk_hiz_lp : 1; /* [ 12], r/w, 0x0 */ - uint32_t reg_force_clk_hiz_hs : 1; /* [ 13], r/w, 0x0 */ - uint32_t reg_ana_lp_txen_clklane_esc : 1; /* [ 14], r/w, 0x0 */ - uint32_t reg_ana_lp_dptxdata_clklane_esc : 1; /* [ 15], r/w, 0x0 */ - uint32_t reg_ana_lp_dntxdata_clklane_esc : 1; /* [ 16], r/w, 0x0 */ - uint32_t reg_ana_hs_txen_clklane_esc : 1; /* [ 17], r/w, 0x0 */ - uint32_t reg_ana_clk_en_esc : 1; /* [ 18], r/w, 0x0 */ - uint32_t reg_ana_byte_rev : 1; /* [ 19], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_7; - - /* 0xA0 : dphy_config_8 */ - union { - struct { - uint32_t reg_ana_lptxp_data : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reg_ana_lptxn_data : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_ana_lptxen : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reg_ana_lprxen : 4; /* [15:12], r/w, 0x0 */ - uint32_t reg_ana_hstxen : 4; /* [19:16], r/w, 0x0 */ - uint32_t reg_ana_hs_trail_byte : 4; /* [23:20], r/w, 0x0 */ - uint32_t reg_ana_hs_sync_ld_byte : 4; /* [27:24], r/w, 0x0 */ - uint32_t reg_ana_hs_p2s_sel_byte : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_8; - - /* 0xA4 : dphy_config_9 */ - union { - struct { - uint32_t reg_ana_hs_data_out_byte : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_9; - - /* 0xA8 : dphy_config_10 */ - union { - struct { - uint32_t reg_testbus_sel_lo : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reg_testbus_sel_hi : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_testbus_hi8bsel_8bmode : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_imp_pu_code : 5; /* [13: 9], r/w, 0x8 */ - uint32_t reg_imp_pd_code : 5; /* [18:14], r/w, 0x9 */ - uint32_t reg_dphy_vreg400mv_trim : 3; /* [21:19], r/w, 0x0 */ - uint32_t reg_dphy_bg_vref_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t reg_ana_bg_vref_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t reg_ana_vreg400mv_trim : 3; /* [26:24], r/w, 0x0 */ - uint32_t reg_ana_vref_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_10; - - /* 0xAC : dphy_config_11 */ - union { - struct { - uint32_t reg_dsi_ana_0 : 16; /* [15: 0], r/w, 0xc14 */ - uint32_t reg_dsi_ana_1 : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_11; - - /* 0xB0 : dphy_config_12 */ - union { - struct { - uint32_t reg_dsi_ana_2 : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_12; - - /* 0xB4 : dphy_config_13 */ - union { - struct { - uint32_t reg_rd_dig_test_bus : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_13; - - /* 0xB8 : dphy_config_14 */ - union { - struct { - uint32_t reg_pt_free_rep_pat : 32; /* [31: 0], r/w, 0x87654321 */ - } BF; - uint32_t WORD; - } dphy_config_14; - - /* 0xBC : dphy_config_15 */ - union { - struct { - uint32_t reg_dsi_dc_tp_out_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_dsi_pw_avdd1815 : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reg_dphy_pu_ldo11 : 1; /* [ 8], r/w, 0x1 */ - uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ - uint32_t reg_dphy_short_ldo11 : 1; /* [ 12], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t reg_dphy_ldo11_rfb_sw : 3; /* [18:16], r/w, 0x4 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t reg_ten_dsi_ldo : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t reg_mipi_ldo_fast : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_27 : 3; /* [27:25], rsvd, 0x0 */ - uint32_t reg_dsi_rst_n_pre : 1; /* [ 28], r/w, 0x0 */ - uint32_t reg_csi_rst_n_pre : 1; /* [ 29], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_15; - - /* 0xC0 : dphy_config_16 */ - union { - struct { - uint32_t reg_dsi_byte_clk_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_dsi_lprx_clk_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dphy_config_16; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[56]; - - /* 0xFC : dummy_reg */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dummy_reg; -}; - -typedef volatile struct dsi_reg dsi_reg_t; - -#endif /* __DSI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_auto_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_auto_reg.h deleted file mode 100644 index 9602494e27..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_auto_reg.h +++ /dev/null @@ -1,201 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_auto_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_AUTO_REG_H__ -#define __DSP2_AUTO_REG_H__ - -#include "bl808.h" - -/* 0x444 : afwas */ -#define DSP2_AUTO_AFWAS_OFFSET (0x444) -#define DSP2_AUTO_AFWASX_W DSP2_AUTO_AFWASX_W -#define DSP2_AUTO_AFWASX_W_POS (16U) -#define DSP2_AUTO_AFWASX_W_LEN (8U) -#define DSP2_AUTO_AFWASX_W_MSK (((1U << DSP2_AUTO_AFWASX_W_LEN) - 1) << DSP2_AUTO_AFWASX_W_POS) -#define DSP2_AUTO_AFWASX_W_UMSK (~(((1U << DSP2_AUTO_AFWASX_W_LEN) - 1) << DSP2_AUTO_AFWASX_W_POS)) -#define DSP2_AUTO_AFWASY_W DSP2_AUTO_AFWASY_W -#define DSP2_AUTO_AFWASY_W_POS (24U) -#define DSP2_AUTO_AFWASY_W_LEN (8U) -#define DSP2_AUTO_AFWASY_W_MSK (((1U << DSP2_AUTO_AFWASY_W_LEN) - 1) << DSP2_AUTO_AFWASY_W_POS) -#define DSP2_AUTO_AFWASY_W_UMSK (~(((1U << DSP2_AUTO_AFWASY_W_LEN) - 1) << DSP2_AUTO_AFWASY_W_POS)) - -/* 0x448 : afwae_afwbs */ -#define DSP2_AUTO_AFWAE_AFWBS_OFFSET (0x448) -#define DSP2_AUTO_AFWAEX_W DSP2_AUTO_AFWAEX_W -#define DSP2_AUTO_AFWAEX_W_POS (0U) -#define DSP2_AUTO_AFWAEX_W_LEN (8U) -#define DSP2_AUTO_AFWAEX_W_MSK (((1U << DSP2_AUTO_AFWAEX_W_LEN) - 1) << DSP2_AUTO_AFWAEX_W_POS) -#define DSP2_AUTO_AFWAEX_W_UMSK (~(((1U << DSP2_AUTO_AFWAEX_W_LEN) - 1) << DSP2_AUTO_AFWAEX_W_POS)) -#define DSP2_AUTO_AFWAEY_W DSP2_AUTO_AFWAEY_W -#define DSP2_AUTO_AFWAEY_W_POS (8U) -#define DSP2_AUTO_AFWAEY_W_LEN (8U) -#define DSP2_AUTO_AFWAEY_W_MSK (((1U << DSP2_AUTO_AFWAEY_W_LEN) - 1) << DSP2_AUTO_AFWAEY_W_POS) -#define DSP2_AUTO_AFWAEY_W_UMSK (~(((1U << DSP2_AUTO_AFWAEY_W_LEN) - 1) << DSP2_AUTO_AFWAEY_W_POS)) -#define DSP2_AUTO_AFWBSX_W DSP2_AUTO_AFWBSX_W -#define DSP2_AUTO_AFWBSX_W_POS (16U) -#define DSP2_AUTO_AFWBSX_W_LEN (8U) -#define DSP2_AUTO_AFWBSX_W_MSK (((1U << DSP2_AUTO_AFWBSX_W_LEN) - 1) << DSP2_AUTO_AFWBSX_W_POS) -#define DSP2_AUTO_AFWBSX_W_UMSK (~(((1U << DSP2_AUTO_AFWBSX_W_LEN) - 1) << DSP2_AUTO_AFWBSX_W_POS)) -#define DSP2_AUTO_AFWBSY_W DSP2_AUTO_AFWBSY_W -#define DSP2_AUTO_AFWBSY_W_POS (24U) -#define DSP2_AUTO_AFWBSY_W_LEN (8U) -#define DSP2_AUTO_AFWBSY_W_MSK (((1U << DSP2_AUTO_AFWBSY_W_LEN) - 1) << DSP2_AUTO_AFWBSY_W_POS) -#define DSP2_AUTO_AFWBSY_W_UMSK (~(((1U << DSP2_AUTO_AFWBSY_W_LEN) - 1) << DSP2_AUTO_AFWBSY_W_POS)) - -/* 0x44C : afbae_afmisc */ -#define DSP2_AUTO_AFBAE_AFMISC_OFFSET (0x44C) -#define DSP2_AUTO_AFWBEX_W DSP2_AUTO_AFWBEX_W -#define DSP2_AUTO_AFWBEX_W_POS (0U) -#define DSP2_AUTO_AFWBEX_W_LEN (8U) -#define DSP2_AUTO_AFWBEX_W_MSK (((1U << DSP2_AUTO_AFWBEX_W_LEN) - 1) << DSP2_AUTO_AFWBEX_W_POS) -#define DSP2_AUTO_AFWBEX_W_UMSK (~(((1U << DSP2_AUTO_AFWBEX_W_LEN) - 1) << DSP2_AUTO_AFWBEX_W_POS)) -#define DSP2_AUTO_AFWBEY_W DSP2_AUTO_AFWBEY_W -#define DSP2_AUTO_AFWBEY_W_POS (8U) -#define DSP2_AUTO_AFWBEY_W_LEN (8U) -#define DSP2_AUTO_AFWBEY_W_MSK (((1U << DSP2_AUTO_AFWBEY_W_LEN) - 1) << DSP2_AUTO_AFWBEY_W_POS) -#define DSP2_AUTO_AFWBEY_W_UMSK (~(((1U << DSP2_AUTO_AFWBEY_W_LEN) - 1) << DSP2_AUTO_AFWBEY_W_POS)) -#define DSP2_AUTO_FCORE2_W DSP2_AUTO_FCORE2_W -#define DSP2_AUTO_FCORE2_W_POS (16U) -#define DSP2_AUTO_FCORE2_W_LEN (4U) -#define DSP2_AUTO_FCORE2_W_MSK (((1U << DSP2_AUTO_FCORE2_W_LEN) - 1) << DSP2_AUTO_FCORE2_W_POS) -#define DSP2_AUTO_FCORE2_W_UMSK (~(((1U << DSP2_AUTO_FCORE2_W_LEN) - 1) << DSP2_AUTO_FCORE2_W_POS)) -#define DSP2_AUTO_FCORE1_W DSP2_AUTO_FCORE1_W -#define DSP2_AUTO_FCORE1_W_POS (20U) -#define DSP2_AUTO_FCORE1_W_LEN (4U) -#define DSP2_AUTO_FCORE1_W_MSK (((1U << DSP2_AUTO_FCORE1_W_LEN) - 1) << DSP2_AUTO_FCORE1_W_POS) -#define DSP2_AUTO_FCORE1_W_UMSK (~(((1U << DSP2_AUTO_FCORE1_W_LEN) - 1) << DSP2_AUTO_FCORE1_W_POS)) -#define DSP2_AUTO_AFGAMMA_W DSP2_AUTO_AFGAMMA_W -#define DSP2_AUTO_AFGAMMA_W_POS (24U) -#define DSP2_AUTO_AFGAMMA_W_LEN (3U) -#define DSP2_AUTO_AFGAMMA_W_MSK (((1U << DSP2_AUTO_AFGAMMA_W_LEN) - 1) << DSP2_AUTO_AFGAMMA_W_POS) -#define DSP2_AUTO_AFGAMMA_W_UMSK (~(((1U << DSP2_AUTO_AFGAMMA_W_LEN) - 1) << DSP2_AUTO_AFGAMMA_W_POS)) -#define DSP2_AUTO_SUM_SHIFT_B_W DSP2_AUTO_SUM_SHIFT_B_W -#define DSP2_AUTO_SUM_SHIFT_B_W_POS (27U) -#define DSP2_AUTO_SUM_SHIFT_B_W_LEN (3U) -#define DSP2_AUTO_SUM_SHIFT_B_W_MSK (((1U << DSP2_AUTO_SUM_SHIFT_B_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_B_W_POS) -#define DSP2_AUTO_SUM_SHIFT_B_W_UMSK (~(((1U << DSP2_AUTO_SUM_SHIFT_B_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_B_W_POS)) -#define DSP2_AUTO_SUM_SHIFT_A_W DSP2_AUTO_SUM_SHIFT_A_W -#define DSP2_AUTO_SUM_SHIFT_A_W_POS (30U) -#define DSP2_AUTO_SUM_SHIFT_A_W_LEN (2U) -#define DSP2_AUTO_SUM_SHIFT_A_W_MSK (((1U << DSP2_AUTO_SUM_SHIFT_A_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_A_W_POS) -#define DSP2_AUTO_SUM_SHIFT_A_W_UMSK (~(((1U << DSP2_AUTO_SUM_SHIFT_A_W_LEN) - 1) << DSP2_AUTO_SUM_SHIFT_A_W_POS)) - -/* 0x450 : afwah */ -#define DSP2_AUTO_AFWAH_OFFSET (0x450) -#define DSP2_AUTO_AFWAH1_R DSP2_AUTO_AFWAH1_R -#define DSP2_AUTO_AFWAH1_R_POS (0U) -#define DSP2_AUTO_AFWAH1_R_LEN (16U) -#define DSP2_AUTO_AFWAH1_R_MSK (((1U << DSP2_AUTO_AFWAH1_R_LEN) - 1) << DSP2_AUTO_AFWAH1_R_POS) -#define DSP2_AUTO_AFWAH1_R_UMSK (~(((1U << DSP2_AUTO_AFWAH1_R_LEN) - 1) << DSP2_AUTO_AFWAH1_R_POS)) -#define DSP2_AUTO_AFWAH2_R DSP2_AUTO_AFWAH2_R -#define DSP2_AUTO_AFWAH2_R_POS (16U) -#define DSP2_AUTO_AFWAH2_R_LEN (16U) -#define DSP2_AUTO_AFWAH2_R_MSK (((1U << DSP2_AUTO_AFWAH2_R_LEN) - 1) << DSP2_AUTO_AFWAH2_R_POS) -#define DSP2_AUTO_AFWAH2_R_UMSK (~(((1U << DSP2_AUTO_AFWAH2_R_LEN) - 1) << DSP2_AUTO_AFWAH2_R_POS)) - -/* 0x454 : afwbh */ -#define DSP2_AUTO_AFWBH_OFFSET (0x454) -#define DSP2_AUTO_AFWBH1_R DSP2_AUTO_AFWBH1_R -#define DSP2_AUTO_AFWBH1_R_POS (0U) -#define DSP2_AUTO_AFWBH1_R_LEN (16U) -#define DSP2_AUTO_AFWBH1_R_MSK (((1U << DSP2_AUTO_AFWBH1_R_LEN) - 1) << DSP2_AUTO_AFWBH1_R_POS) -#define DSP2_AUTO_AFWBH1_R_UMSK (~(((1U << DSP2_AUTO_AFWBH1_R_LEN) - 1) << DSP2_AUTO_AFWBH1_R_POS)) -#define DSP2_AUTO_AFWBH2_R DSP2_AUTO_AFWBH2_R -#define DSP2_AUTO_AFWBH2_R_POS (16U) -#define DSP2_AUTO_AFWBH2_R_LEN (16U) -#define DSP2_AUTO_AFWBH2_R_MSK (((1U << DSP2_AUTO_AFWBH2_R_LEN) - 1) << DSP2_AUTO_AFWBH2_R_POS) -#define DSP2_AUTO_AFWBH2_R_UMSK (~(((1U << DSP2_AUTO_AFWBH2_R_LEN) - 1) << DSP2_AUTO_AFWBH2_R_POS)) - -struct dsp2_auto_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1092]; - - /* 0x444 : afwas */ - union { - struct { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t afwasx_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t afwasy_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } afwas; - - /* 0x448 : afwae_afwbs */ - union { - struct { - uint32_t afwaex_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t afwaey_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t afwbsx_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t afwbsy_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } afwae_afwbs; - - /* 0x44C : afbae_afmisc */ - union { - struct { - uint32_t afwbex_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t afwbey_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t fcore2_w : 4; /* [19:16], r/w, 0x0 */ - uint32_t fcore1_w : 4; /* [23:20], r/w, 0x0 */ - uint32_t AFGamma_w : 3; /* [26:24], r/w, 0x0 */ - uint32_t sum_shift_b_w : 3; /* [29:27], r/w, 0x0 */ - uint32_t sum_shift_a_w : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } afbae_afmisc; - - /* 0x450 : afwah */ - union { - struct { - uint32_t afwah1_r : 16; /* [15: 0], r, 0x0 */ - uint32_t afwah2_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } afwah; - - /* 0x454 : afwbh */ - union { - struct { - uint32_t afwbh1_r : 16; /* [15: 0], r, 0x0 */ - uint32_t afwbh2_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } afwbh; -}; - -typedef volatile struct dsp2_auto_reg dsp2_auto_reg_t; - -#endif /* __DSP2_AUTO_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_axi_ctrl_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_axi_ctrl_reg.h deleted file mode 100644 index 8d4e6b4e64..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_axi_ctrl_reg.h +++ /dev/null @@ -1,336 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_axi_ctrl_reg.h - * @version V1.0 - * @date 2021-07-19 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_AXI_CTRL_REG_H__ -#define __DSP2_AXI_CTRL_REG_H__ - -#include "bl808.h" - -/* 0x0 : nr_control */ -#define DSP2_AXI_CTRL_NR_CONTROL_OFFSET (0x0) -#define DSP2_AXI_CTRL_REG_ENABLE DSP2_AXI_CTRL_REG_ENABLE -#define DSP2_AXI_CTRL_REG_ENABLE_POS (0U) -#define DSP2_AXI_CTRL_REG_ENABLE_LEN (1U) -#define DSP2_AXI_CTRL_REG_ENABLE_MSK (((1U << DSP2_AXI_CTRL_REG_ENABLE_LEN) - 1) << DSP2_AXI_CTRL_REG_ENABLE_POS) -#define DSP2_AXI_CTRL_REG_ENABLE_UMSK (~(((1U << DSP2_AXI_CTRL_REG_ENABLE_LEN) - 1) << DSP2_AXI_CTRL_REG_ENABLE_POS)) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR DSP2_AXI_CTRL_REG_DRAIN_CLR -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_POS (1U) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_LEN (1U) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_MSK (((1U << DSP2_AXI_CTRL_REG_DRAIN_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_DRAIN_CLR_POS) -#define DSP2_AXI_CTRL_REG_DRAIN_CLR_UMSK (~(((1U << DSP2_AXI_CTRL_REG_DRAIN_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_DRAIN_CLR_POS)) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR DSP2_AXI_CTRL_REG_OVERFLOW_CLR -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_POS (2U) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_LEN (1U) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_MSK (((1U << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_POS) -#define DSP2_AXI_CTRL_REG_OVERFLOW_CLR_UMSK (~(((1U << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_LEN) - 1) << DSP2_AXI_CTRL_REG_OVERFLOW_CLR_POS)) -#define DSP2_AXI_CTRL_REG_XLEN DSP2_AXI_CTRL_REG_XLEN -#define DSP2_AXI_CTRL_REG_XLEN_POS (4U) -#define DSP2_AXI_CTRL_REG_XLEN_LEN (3U) -#define DSP2_AXI_CTRL_REG_XLEN_MSK (((1U << DSP2_AXI_CTRL_REG_XLEN_LEN) - 1) << DSP2_AXI_CTRL_REG_XLEN_POS) -#define DSP2_AXI_CTRL_REG_XLEN_UMSK (~(((1U << DSP2_AXI_CTRL_REG_XLEN_LEN) - 1) << DSP2_AXI_CTRL_REG_XLEN_POS)) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE DSP2_AXI_CTRL_REG_QOS_SW_MODE -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_POS (8U) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_LEN (1U) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_MSK (((1U << DSP2_AXI_CTRL_REG_QOS_SW_MODE_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_MODE_POS) -#define DSP2_AXI_CTRL_REG_QOS_SW_MODE_UMSK (~(((1U << DSP2_AXI_CTRL_REG_QOS_SW_MODE_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_MODE_POS)) -#define DSP2_AXI_CTRL_REG_QOS_SW DSP2_AXI_CTRL_REG_QOS_SW -#define DSP2_AXI_CTRL_REG_QOS_SW_POS (9U) -#define DSP2_AXI_CTRL_REG_QOS_SW_LEN (1U) -#define DSP2_AXI_CTRL_REG_QOS_SW_MSK (((1U << DSP2_AXI_CTRL_REG_QOS_SW_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_POS) -#define DSP2_AXI_CTRL_REG_QOS_SW_UMSK (~(((1U << DSP2_AXI_CTRL_REG_QOS_SW_LEN) - 1) << DSP2_AXI_CTRL_REG_QOS_SW_POS)) - -/* 0x4 : nr_haddr_start_address */ -#define DSP2_AXI_CTRL_NR_HADDR_START_ADDRESS_OFFSET (0x4) -#define DSP2_AXI_CTRL_REG_ADDR_START DSP2_AXI_CTRL_REG_ADDR_START -#define DSP2_AXI_CTRL_REG_ADDR_START_POS (0U) -#define DSP2_AXI_CTRL_REG_ADDR_START_LEN (32U) -#define DSP2_AXI_CTRL_REG_ADDR_START_MSK (((1U << DSP2_AXI_CTRL_REG_ADDR_START_LEN) - 1) << DSP2_AXI_CTRL_REG_ADDR_START_POS) -#define DSP2_AXI_CTRL_REG_ADDR_START_UMSK (~(((1U << DSP2_AXI_CTRL_REG_ADDR_START_LEN) - 1) << DSP2_AXI_CTRL_REG_ADDR_START_POS)) - -/* 0x8 : nr_memory_burst_count */ -#define DSP2_AXI_CTRL_NR_MEMORY_BURST_COUNT_OFFSET (0x8) -#define DSP2_AXI_CTRL_REG_BURST_CNT DSP2_AXI_CTRL_REG_BURST_CNT -#define DSP2_AXI_CTRL_REG_BURST_CNT_POS (0U) -#define DSP2_AXI_CTRL_REG_BURST_CNT_LEN (32U) -#define DSP2_AXI_CTRL_REG_BURST_CNT_MSK (((1U << DSP2_AXI_CTRL_REG_BURST_CNT_LEN) - 1) << DSP2_AXI_CTRL_REG_BURST_CNT_POS) -#define DSP2_AXI_CTRL_REG_BURST_CNT_UMSK (~(((1U << DSP2_AXI_CTRL_REG_BURST_CNT_LEN) - 1) << DSP2_AXI_CTRL_REG_BURST_CNT_POS)) - -/* 0xC : nr_hsync_control */ -#define DSP2_AXI_CTRL_NR_HSYNC_CONTROL_OFFSET (0xC) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END DSP2_AXI_CTRL_REG_HSYNC_ACT_END -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_POS (0U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_LEN (16U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_MSK (((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_POS) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_END_UMSK (~(((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_END_POS)) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START DSP2_AXI_CTRL_REG_HSYNC_ACT_START -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_POS (16U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_LEN (16U) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_MSK (((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_POS) -#define DSP2_AXI_CTRL_REG_HSYNC_ACT_START_UMSK (~(((1U << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_HSYNC_ACT_START_POS)) - -/* 0x10 : nr_vsync_control */ -#define DSP2_AXI_CTRL_NR_VSYNC_CONTROL_OFFSET (0x10) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END DSP2_AXI_CTRL_REG_VSYNC_ACT_END -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_POS (0U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_LEN (16U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_MSK (((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_POS) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_END_UMSK (~(((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_END_POS)) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START DSP2_AXI_CTRL_REG_VSYNC_ACT_START -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_POS (16U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_LEN (16U) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_MSK (((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_POS) -#define DSP2_AXI_CTRL_REG_VSYNC_ACT_START_UMSK (~(((1U << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_LEN) - 1) << DSP2_AXI_CTRL_REG_VSYNC_ACT_START_POS)) - -/* 0x14 : nr_status */ -#define DSP2_AXI_CTRL_NR_STATUS_OFFSET (0x14) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN DSP2_AXI_CTRL_STATUS_R_DRAIN -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_POS (4U) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_LEN (1U) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_MSK (((1U << DSP2_AXI_CTRL_STATUS_R_DRAIN_LEN) - 1) << DSP2_AXI_CTRL_STATUS_R_DRAIN_POS) -#define DSP2_AXI_CTRL_STATUS_R_DRAIN_UMSK (~(((1U << DSP2_AXI_CTRL_STATUS_R_DRAIN_LEN) - 1) << DSP2_AXI_CTRL_STATUS_R_DRAIN_POS)) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW DSP2_AXI_CTRL_STATUS_W_OVERFLOW -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_POS (5U) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_LEN (1U) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_MSK (((1U << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_LEN) - 1) << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_POS) -#define DSP2_AXI_CTRL_STATUS_W_OVERFLOW_UMSK (~(((1U << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_LEN) - 1) << DSP2_AXI_CTRL_STATUS_W_OVERFLOW_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE DSP2_AXI_CTRL_STATE_W_DVP_IDLE -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_POS (8U) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST DSP2_AXI_CTRL_STATE_W_DVP_WTST -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_POS (9U) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_WTST_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_WTST_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_WTST_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC DSP2_AXI_CTRL_STATE_W_DVP_FUNC -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_POS (10U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND DSP2_AXI_CTRL_STATE_W_DVP_FEND -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_POS (11U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FEND_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH DSP2_AXI_CTRL_STATE_W_DVP_FLSH -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_POS (12U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_W_DVP_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_DVP_FLSH_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE DSP2_AXI_CTRL_STATE_W_BUS_IDLE -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_POS (13U) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC DSP2_AXI_CTRL_STATE_W_BUS_FUNC -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_POS (14U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND DSP2_AXI_CTRL_STATE_W_BUS_FEND -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_POS (15U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FEND_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH DSP2_AXI_CTRL_STATE_W_BUS_FLSH -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_POS (16U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_W_BUS_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_W_BUS_FLSH_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE DSP2_AXI_CTRL_STATE_R_DVP_IDLE -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_POS (17U) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST DSP2_AXI_CTRL_STATE_R_DVP_WTST -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_POS (18U) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_WTST_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_WTST_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_WTST_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_WTST_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC DSP2_AXI_CTRL_STATE_R_DVP_FUNC -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_POS (19U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND DSP2_AXI_CTRL_STATE_R_DVP_FEND -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_POS (20U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FEND_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH DSP2_AXI_CTRL_STATE_R_DVP_FLSH -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_POS (21U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_R_DVP_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_DVP_FLSH_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE DSP2_AXI_CTRL_STATE_R_BUS_IDLE -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_POS (22U) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_IDLE_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC DSP2_AXI_CTRL_STATE_R_BUS_FUNC -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_POS (23U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_FUNC_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FUNC_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND DSP2_AXI_CTRL_STATE_R_BUS_FEND -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_POS (24U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FEND_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_FEND_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_FEND_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FEND_POS)) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH DSP2_AXI_CTRL_STATE_R_BUS_FLSH -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_POS (25U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_LEN (1U) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_MSK (((1U << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_POS) -#define DSP2_AXI_CTRL_STATE_R_BUS_FLSH_UMSK (~(((1U << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_LEN) - 1) << DSP2_AXI_CTRL_STATE_R_BUS_FLSH_POS)) -#define DSP2_AXI_CTRL_AXI_R_IDLE DSP2_AXI_CTRL_AXI_R_IDLE -#define DSP2_AXI_CTRL_AXI_R_IDLE_POS (26U) -#define DSP2_AXI_CTRL_AXI_R_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_AXI_R_IDLE_MSK (((1U << DSP2_AXI_CTRL_AXI_R_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_R_IDLE_POS) -#define DSP2_AXI_CTRL_AXI_R_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_AXI_R_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_R_IDLE_POS)) -#define DSP2_AXI_CTRL_AXI_W_IDLE DSP2_AXI_CTRL_AXI_W_IDLE -#define DSP2_AXI_CTRL_AXI_W_IDLE_POS (27U) -#define DSP2_AXI_CTRL_AXI_W_IDLE_LEN (1U) -#define DSP2_AXI_CTRL_AXI_W_IDLE_MSK (((1U << DSP2_AXI_CTRL_AXI_W_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_W_IDLE_POS) -#define DSP2_AXI_CTRL_AXI_W_IDLE_UMSK (~(((1U << DSP2_AXI_CTRL_AXI_W_IDLE_LEN) - 1) << DSP2_AXI_CTRL_AXI_W_IDLE_POS)) - -/* 0xFC : nr_RSVD */ -#define DSP2_AXI_CTRL_NR_RSVD_OFFSET (0xFC) - -struct dsp2_axi_ctrl_reg { - /* 0x0 : nr_control */ - union { - struct - { - uint32_t reg_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_drain_clr : 1; /* [ 1], w1p, 0x0 */ - uint32_t reg_overflow_clr : 1; /* [ 2], w1p, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t reg_xlen : 3; /* [ 6: 4], r/w, 0x3 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t reg_qos_sw_mode : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_qos_sw : 1; /* [ 9], r/w, 0x0 */ - uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } nr_control; - - /* 0x4 : nr_haddr_start_address */ - union { - struct - { - uint32_t reg_addr_start : 32; /* [31: 0], r/w, 0x70000000 */ - } BF; - uint32_t WORD; - } nr_haddr_start_address; - - /* 0x8 : nr_memory_burst_count */ - union { - struct - { - uint32_t reg_burst_cnt : 32; /* [31: 0], r/w, 0x80 */ - } BF; - uint32_t WORD; - } nr_memory_burst_count; - - /* 0xC : nr_hsync_control */ - union { - struct - { - uint32_t reg_hsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_hsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } nr_hsync_control; - - /* 0x10 : nr_vsync_control */ - union { - struct - { - uint32_t reg_vsync_act_end : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reg_vsync_act_start : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } nr_vsync_control; - - /* 0x14 : nr_status */ - union { - struct - { - uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */ - uint32_t status_r_drain : 1; /* [ 4], r, 0x0 */ - uint32_t status_w_overflow : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t state_w_dvp_idle : 1; /* [ 8], r, 0x1 */ - uint32_t state_w_dvp_wtst : 1; /* [ 9], r, 0x0 */ - uint32_t state_w_dvp_func : 1; /* [ 10], r, 0x0 */ - uint32_t state_w_dvp_fend : 1; /* [ 11], r, 0x0 */ - uint32_t state_w_dvp_flsh : 1; /* [ 12], r, 0x0 */ - uint32_t state_w_bus_idle : 1; /* [ 13], r, 0x1 */ - uint32_t state_w_bus_func : 1; /* [ 14], r, 0x0 */ - uint32_t state_w_bus_fend : 1; /* [ 15], r, 0x0 */ - uint32_t state_w_bus_flsh : 1; /* [ 16], r, 0x0 */ - uint32_t state_r_dvp_idle : 1; /* [ 17], r, 0x1 */ - uint32_t state_r_dvp_wtst : 1; /* [ 18], r, 0x0 */ - uint32_t state_r_dvp_func : 1; /* [ 19], r, 0x0 */ - uint32_t state_r_dvp_fend : 1; /* [ 20], r, 0x0 */ - uint32_t state_r_dvp_flsh : 1; /* [ 21], r, 0x0 */ - uint32_t state_r_bus_idle : 1; /* [ 22], r, 0x1 */ - uint32_t state_r_bus_func : 1; /* [ 23], r, 0x0 */ - uint32_t state_r_bus_fend : 1; /* [ 24], r, 0x0 */ - uint32_t state_r_bus_flsh : 1; /* [ 25], r, 0x0 */ - uint32_t axi_r_idle : 1; /* [ 26], r, 0x0 */ - uint32_t axi_w_idle : 1; /* [ 27], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } nr_status; - - /* 0x18 reserved */ - uint8_t RESERVED0x18[228]; - - /* 0xFC : nr_RSVD */ - union { - struct - { - uint32_t RESERVED_31_0 : 32; /* [31: 0], rsvd, 0xffff0000 */ - } BF; - uint32_t WORD; - } nr_RSVD; -}; - -typedef volatile struct dsp2_axi_ctrl_reg dsp2_axi_ctrl_reg_t; - -#endif /* __DSP2_AXI_CTRL_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_back_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_back_reg.h deleted file mode 100644 index 5fbbbaf25e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_back_reg.h +++ /dev/null @@ -1,574 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_back_reg.h - * @version V1.0 - * @date 2021-02-05 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BACK_REG_H__ -#define __DSP2_BACK_REG_H__ - -#include "bl808.h" - -/* 0x314 : ccr_coef_A */ -#define DSP2_BACK_CCR_COEF_A_OFFSET (0x314) -#define DSP2_BACK_A11_PRE DSP2_BACK_A11_PRE -#define DSP2_BACK_A11_PRE_POS (16U) -#define DSP2_BACK_A11_PRE_LEN (12U) -#define DSP2_BACK_A11_PRE_MSK (((1U << DSP2_BACK_A11_PRE_LEN) - 1) << DSP2_BACK_A11_PRE_POS) -#define DSP2_BACK_A11_PRE_UMSK (~(((1U << DSP2_BACK_A11_PRE_LEN) - 1) << DSP2_BACK_A11_PRE_POS)) - -/* 0x318 : ccr_coef_B */ -#define DSP2_BACK_CCR_COEF_B_OFFSET (0x318) -#define DSP2_BACK_A12_PRE DSP2_BACK_A12_PRE -#define DSP2_BACK_A12_PRE_POS (0U) -#define DSP2_BACK_A12_PRE_LEN (12U) -#define DSP2_BACK_A12_PRE_MSK (((1U << DSP2_BACK_A12_PRE_LEN) - 1) << DSP2_BACK_A12_PRE_POS) -#define DSP2_BACK_A12_PRE_UMSK (~(((1U << DSP2_BACK_A12_PRE_LEN) - 1) << DSP2_BACK_A12_PRE_POS)) -#define DSP2_BACK_A13_PRE DSP2_BACK_A13_PRE -#define DSP2_BACK_A13_PRE_POS (16U) -#define DSP2_BACK_A13_PRE_LEN (12U) -#define DSP2_BACK_A13_PRE_MSK (((1U << DSP2_BACK_A13_PRE_LEN) - 1) << DSP2_BACK_A13_PRE_POS) -#define DSP2_BACK_A13_PRE_UMSK (~(((1U << DSP2_BACK_A13_PRE_LEN) - 1) << DSP2_BACK_A13_PRE_POS)) - -/* 0x31C : ccr_coef_C */ -#define DSP2_BACK_CCR_COEF_C_OFFSET (0x31C) -#define DSP2_BACK_A21_PRE DSP2_BACK_A21_PRE -#define DSP2_BACK_A21_PRE_POS (0U) -#define DSP2_BACK_A21_PRE_LEN (12U) -#define DSP2_BACK_A21_PRE_MSK (((1U << DSP2_BACK_A21_PRE_LEN) - 1) << DSP2_BACK_A21_PRE_POS) -#define DSP2_BACK_A21_PRE_UMSK (~(((1U << DSP2_BACK_A21_PRE_LEN) - 1) << DSP2_BACK_A21_PRE_POS)) -#define DSP2_BACK_A22_PRE DSP2_BACK_A22_PRE -#define DSP2_BACK_A22_PRE_POS (16U) -#define DSP2_BACK_A22_PRE_LEN (12U) -#define DSP2_BACK_A22_PRE_MSK (((1U << DSP2_BACK_A22_PRE_LEN) - 1) << DSP2_BACK_A22_PRE_POS) -#define DSP2_BACK_A22_PRE_UMSK (~(((1U << DSP2_BACK_A22_PRE_LEN) - 1) << DSP2_BACK_A22_PRE_POS)) - -/* 0x320 : ccr_coef_D */ -#define DSP2_BACK_CCR_COEF_D_OFFSET (0x320) -#define DSP2_BACK_A23_PRE DSP2_BACK_A23_PRE -#define DSP2_BACK_A23_PRE_POS (0U) -#define DSP2_BACK_A23_PRE_LEN (12U) -#define DSP2_BACK_A23_PRE_MSK (((1U << DSP2_BACK_A23_PRE_LEN) - 1) << DSP2_BACK_A23_PRE_POS) -#define DSP2_BACK_A23_PRE_UMSK (~(((1U << DSP2_BACK_A23_PRE_LEN) - 1) << DSP2_BACK_A23_PRE_POS)) -#define DSP2_BACK_A31_PRE DSP2_BACK_A31_PRE -#define DSP2_BACK_A31_PRE_POS (16U) -#define DSP2_BACK_A31_PRE_LEN (12U) -#define DSP2_BACK_A31_PRE_MSK (((1U << DSP2_BACK_A31_PRE_LEN) - 1) << DSP2_BACK_A31_PRE_POS) -#define DSP2_BACK_A31_PRE_UMSK (~(((1U << DSP2_BACK_A31_PRE_LEN) - 1) << DSP2_BACK_A31_PRE_POS)) - -/* 0x324 : ccr_coef_E */ -#define DSP2_BACK_CCR_COEF_E_OFFSET (0x324) -#define DSP2_BACK_A32_PRE DSP2_BACK_A32_PRE -#define DSP2_BACK_A32_PRE_POS (0U) -#define DSP2_BACK_A32_PRE_LEN (12U) -#define DSP2_BACK_A32_PRE_MSK (((1U << DSP2_BACK_A32_PRE_LEN) - 1) << DSP2_BACK_A32_PRE_POS) -#define DSP2_BACK_A32_PRE_UMSK (~(((1U << DSP2_BACK_A32_PRE_LEN) - 1) << DSP2_BACK_A32_PRE_POS)) -#define DSP2_BACK_A33_PRE DSP2_BACK_A33_PRE -#define DSP2_BACK_A33_PRE_POS (16U) -#define DSP2_BACK_A33_PRE_LEN (12U) -#define DSP2_BACK_A33_PRE_MSK (((1U << DSP2_BACK_A33_PRE_LEN) - 1) << DSP2_BACK_A33_PRE_POS) -#define DSP2_BACK_A33_PRE_UMSK (~(((1U << DSP2_BACK_A33_PRE_LEN) - 1) << DSP2_BACK_A33_PRE_POS)) - -/* 0x328 : gamma_A */ -#define DSP2_BACK_GAMMA_A_OFFSET (0x328) -#define DSP2_BACK_GAMMA_ON_PRE DSP2_BACK_GAMMA_ON_PRE -#define DSP2_BACK_GAMMA_ON_PRE_POS (0U) -#define DSP2_BACK_GAMMA_ON_PRE_LEN (1U) -#define DSP2_BACK_GAMMA_ON_PRE_MSK (((1U << DSP2_BACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BACK_GAMMA_ON_PRE_POS) -#define DSP2_BACK_GAMMA_ON_PRE_UMSK (~(((1U << DSP2_BACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BACK_GAMMA_ON_PRE_POS)) -#define DSP2_BACK_GAMMA_EB_PRE DSP2_BACK_GAMMA_EB_PRE -#define DSP2_BACK_GAMMA_EB_PRE_POS (1U) -#define DSP2_BACK_GAMMA_EB_PRE_LEN (1U) -#define DSP2_BACK_GAMMA_EB_PRE_MSK (((1U << DSP2_BACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BACK_GAMMA_EB_PRE_POS) -#define DSP2_BACK_GAMMA_EB_PRE_UMSK (~(((1U << DSP2_BACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BACK_GAMMA_EB_PRE_POS)) -#define DSP2_BACK_B0_PRE DSP2_BACK_B0_PRE -#define DSP2_BACK_B0_PRE_POS (8U) -#define DSP2_BACK_B0_PRE_LEN (8U) -#define DSP2_BACK_B0_PRE_MSK (((1U << DSP2_BACK_B0_PRE_LEN) - 1) << DSP2_BACK_B0_PRE_POS) -#define DSP2_BACK_B0_PRE_UMSK (~(((1U << DSP2_BACK_B0_PRE_LEN) - 1) << DSP2_BACK_B0_PRE_POS)) -#define DSP2_BACK_B1_PRE DSP2_BACK_B1_PRE -#define DSP2_BACK_B1_PRE_POS (16U) -#define DSP2_BACK_B1_PRE_LEN (8U) -#define DSP2_BACK_B1_PRE_MSK (((1U << DSP2_BACK_B1_PRE_LEN) - 1) << DSP2_BACK_B1_PRE_POS) -#define DSP2_BACK_B1_PRE_UMSK (~(((1U << DSP2_BACK_B1_PRE_LEN) - 1) << DSP2_BACK_B1_PRE_POS)) -#define DSP2_BACK_B2_PRE DSP2_BACK_B2_PRE -#define DSP2_BACK_B2_PRE_POS (24U) -#define DSP2_BACK_B2_PRE_LEN (8U) -#define DSP2_BACK_B2_PRE_MSK (((1U << DSP2_BACK_B2_PRE_LEN) - 1) << DSP2_BACK_B2_PRE_POS) -#define DSP2_BACK_B2_PRE_UMSK (~(((1U << DSP2_BACK_B2_PRE_LEN) - 1) << DSP2_BACK_B2_PRE_POS)) - -/* 0x32C : gamma_B */ -#define DSP2_BACK_GAMMA_B_OFFSET (0x32C) -#define DSP2_BACK_B3_PRE DSP2_BACK_B3_PRE -#define DSP2_BACK_B3_PRE_POS (0U) -#define DSP2_BACK_B3_PRE_LEN (8U) -#define DSP2_BACK_B3_PRE_MSK (((1U << DSP2_BACK_B3_PRE_LEN) - 1) << DSP2_BACK_B3_PRE_POS) -#define DSP2_BACK_B3_PRE_UMSK (~(((1U << DSP2_BACK_B3_PRE_LEN) - 1) << DSP2_BACK_B3_PRE_POS)) -#define DSP2_BACK_B4_PRE DSP2_BACK_B4_PRE -#define DSP2_BACK_B4_PRE_POS (8U) -#define DSP2_BACK_B4_PRE_LEN (8U) -#define DSP2_BACK_B4_PRE_MSK (((1U << DSP2_BACK_B4_PRE_LEN) - 1) << DSP2_BACK_B4_PRE_POS) -#define DSP2_BACK_B4_PRE_UMSK (~(((1U << DSP2_BACK_B4_PRE_LEN) - 1) << DSP2_BACK_B4_PRE_POS)) -#define DSP2_BACK_B5_PRE DSP2_BACK_B5_PRE -#define DSP2_BACK_B5_PRE_POS (16U) -#define DSP2_BACK_B5_PRE_LEN (8U) -#define DSP2_BACK_B5_PRE_MSK (((1U << DSP2_BACK_B5_PRE_LEN) - 1) << DSP2_BACK_B5_PRE_POS) -#define DSP2_BACK_B5_PRE_UMSK (~(((1U << DSP2_BACK_B5_PRE_LEN) - 1) << DSP2_BACK_B5_PRE_POS)) -#define DSP2_BACK_B6_PRE DSP2_BACK_B6_PRE -#define DSP2_BACK_B6_PRE_POS (24U) -#define DSP2_BACK_B6_PRE_LEN (8U) -#define DSP2_BACK_B6_PRE_MSK (((1U << DSP2_BACK_B6_PRE_LEN) - 1) << DSP2_BACK_B6_PRE_POS) -#define DSP2_BACK_B6_PRE_UMSK (~(((1U << DSP2_BACK_B6_PRE_LEN) - 1) << DSP2_BACK_B6_PRE_POS)) - -/* 0x330 : gamma_C */ -#define DSP2_BACK_GAMMA_C_OFFSET (0x330) -#define DSP2_BACK_B7_PRE DSP2_BACK_B7_PRE -#define DSP2_BACK_B7_PRE_POS (0U) -#define DSP2_BACK_B7_PRE_LEN (8U) -#define DSP2_BACK_B7_PRE_MSK (((1U << DSP2_BACK_B7_PRE_LEN) - 1) << DSP2_BACK_B7_PRE_POS) -#define DSP2_BACK_B7_PRE_UMSK (~(((1U << DSP2_BACK_B7_PRE_LEN) - 1) << DSP2_BACK_B7_PRE_POS)) -#define DSP2_BACK_B8_PRE DSP2_BACK_B8_PRE -#define DSP2_BACK_B8_PRE_POS (8U) -#define DSP2_BACK_B8_PRE_LEN (8U) -#define DSP2_BACK_B8_PRE_MSK (((1U << DSP2_BACK_B8_PRE_LEN) - 1) << DSP2_BACK_B8_PRE_POS) -#define DSP2_BACK_B8_PRE_UMSK (~(((1U << DSP2_BACK_B8_PRE_LEN) - 1) << DSP2_BACK_B8_PRE_POS)) -#define DSP2_BACK_B9_PRE DSP2_BACK_B9_PRE -#define DSP2_BACK_B9_PRE_POS (16U) -#define DSP2_BACK_B9_PRE_LEN (8U) -#define DSP2_BACK_B9_PRE_MSK (((1U << DSP2_BACK_B9_PRE_LEN) - 1) << DSP2_BACK_B9_PRE_POS) -#define DSP2_BACK_B9_PRE_UMSK (~(((1U << DSP2_BACK_B9_PRE_LEN) - 1) << DSP2_BACK_B9_PRE_POS)) -#define DSP2_BACK_B10_PRE DSP2_BACK_B10_PRE -#define DSP2_BACK_B10_PRE_POS (24U) -#define DSP2_BACK_B10_PRE_LEN (8U) -#define DSP2_BACK_B10_PRE_MSK (((1U << DSP2_BACK_B10_PRE_LEN) - 1) << DSP2_BACK_B10_PRE_POS) -#define DSP2_BACK_B10_PRE_UMSK (~(((1U << DSP2_BACK_B10_PRE_LEN) - 1) << DSP2_BACK_B10_PRE_POS)) - -/* 0x334 : gamma_D */ -#define DSP2_BACK_GAMMA_D_OFFSET (0x334) -#define DSP2_BACK_B11_PRE DSP2_BACK_B11_PRE -#define DSP2_BACK_B11_PRE_POS (0U) -#define DSP2_BACK_B11_PRE_LEN (8U) -#define DSP2_BACK_B11_PRE_MSK (((1U << DSP2_BACK_B11_PRE_LEN) - 1) << DSP2_BACK_B11_PRE_POS) -#define DSP2_BACK_B11_PRE_UMSK (~(((1U << DSP2_BACK_B11_PRE_LEN) - 1) << DSP2_BACK_B11_PRE_POS)) -#define DSP2_BACK_B12_PRE DSP2_BACK_B12_PRE -#define DSP2_BACK_B12_PRE_POS (8U) -#define DSP2_BACK_B12_PRE_LEN (8U) -#define DSP2_BACK_B12_PRE_MSK (((1U << DSP2_BACK_B12_PRE_LEN) - 1) << DSP2_BACK_B12_PRE_POS) -#define DSP2_BACK_B12_PRE_UMSK (~(((1U << DSP2_BACK_B12_PRE_LEN) - 1) << DSP2_BACK_B12_PRE_POS)) -#define DSP2_BACK_B13_PRE DSP2_BACK_B13_PRE -#define DSP2_BACK_B13_PRE_POS (16U) -#define DSP2_BACK_B13_PRE_LEN (8U) -#define DSP2_BACK_B13_PRE_MSK (((1U << DSP2_BACK_B13_PRE_LEN) - 1) << DSP2_BACK_B13_PRE_POS) -#define DSP2_BACK_B13_PRE_UMSK (~(((1U << DSP2_BACK_B13_PRE_LEN) - 1) << DSP2_BACK_B13_PRE_POS)) -#define DSP2_BACK_B14_PRE DSP2_BACK_B14_PRE -#define DSP2_BACK_B14_PRE_POS (24U) -#define DSP2_BACK_B14_PRE_LEN (8U) -#define DSP2_BACK_B14_PRE_MSK (((1U << DSP2_BACK_B14_PRE_LEN) - 1) << DSP2_BACK_B14_PRE_POS) -#define DSP2_BACK_B14_PRE_UMSK (~(((1U << DSP2_BACK_B14_PRE_LEN) - 1) << DSP2_BACK_B14_PRE_POS)) - -/* 0x338 : gamma_E */ -#define DSP2_BACK_GAMMA_E_OFFSET (0x338) -#define DSP2_BACK_B15_PRE DSP2_BACK_B15_PRE -#define DSP2_BACK_B15_PRE_POS (0U) -#define DSP2_BACK_B15_PRE_LEN (8U) -#define DSP2_BACK_B15_PRE_MSK (((1U << DSP2_BACK_B15_PRE_LEN) - 1) << DSP2_BACK_B15_PRE_POS) -#define DSP2_BACK_B15_PRE_UMSK (~(((1U << DSP2_BACK_B15_PRE_LEN) - 1) << DSP2_BACK_B15_PRE_POS)) -#define DSP2_BACK_B16_PRE DSP2_BACK_B16_PRE -#define DSP2_BACK_B16_PRE_POS (8U) -#define DSP2_BACK_B16_PRE_LEN (8U) -#define DSP2_BACK_B16_PRE_MSK (((1U << DSP2_BACK_B16_PRE_LEN) - 1) << DSP2_BACK_B16_PRE_POS) -#define DSP2_BACK_B16_PRE_UMSK (~(((1U << DSP2_BACK_B16_PRE_LEN) - 1) << DSP2_BACK_B16_PRE_POS)) -#define DSP2_BACK_B17_PRE DSP2_BACK_B17_PRE -#define DSP2_BACK_B17_PRE_POS (16U) -#define DSP2_BACK_B17_PRE_LEN (8U) -#define DSP2_BACK_B17_PRE_MSK (((1U << DSP2_BACK_B17_PRE_LEN) - 1) << DSP2_BACK_B17_PRE_POS) -#define DSP2_BACK_B17_PRE_UMSK (~(((1U << DSP2_BACK_B17_PRE_LEN) - 1) << DSP2_BACK_B17_PRE_POS)) -#define DSP2_BACK_B18_PRE DSP2_BACK_B18_PRE -#define DSP2_BACK_B18_PRE_POS (24U) -#define DSP2_BACK_B18_PRE_LEN (8U) -#define DSP2_BACK_B18_PRE_MSK (((1U << DSP2_BACK_B18_PRE_LEN) - 1) << DSP2_BACK_B18_PRE_POS) -#define DSP2_BACK_B18_PRE_UMSK (~(((1U << DSP2_BACK_B18_PRE_LEN) - 1) << DSP2_BACK_B18_PRE_POS)) - -/* 0x33C : conv_mode */ -#define DSP2_BACK_CONV_MODE_OFFSET (0x33C) -#define DSP2_BACK_CONV_MODE_W DSP2_BACK_CONV_MODE_W -#define DSP2_BACK_CONV_MODE_W_POS (0U) -#define DSP2_BACK_CONV_MODE_W_LEN (1U) -#define DSP2_BACK_CONV_MODE_W_MSK (((1U << DSP2_BACK_CONV_MODE_W_LEN) - 1) << DSP2_BACK_CONV_MODE_W_POS) -#define DSP2_BACK_CONV_MODE_W_UMSK (~(((1U << DSP2_BACK_CONV_MODE_W_LEN) - 1) << DSP2_BACK_CONV_MODE_W_POS)) - -/* 0x348 : edge_enhance */ -#define DSP2_BACK_EDGE_ENHANCE_OFFSET (0x348) -#define DSP2_BACK_ENHANCE_LEVEL_W DSP2_BACK_ENHANCE_LEVEL_W -#define DSP2_BACK_ENHANCE_LEVEL_W_POS (0U) -#define DSP2_BACK_ENHANCE_LEVEL_W_LEN (7U) -#define DSP2_BACK_ENHANCE_LEVEL_W_MSK (((1U << DSP2_BACK_ENHANCE_LEVEL_W_LEN) - 1) << DSP2_BACK_ENHANCE_LEVEL_W_POS) -#define DSP2_BACK_ENHANCE_LEVEL_W_UMSK (~(((1U << DSP2_BACK_ENHANCE_LEVEL_W_LEN) - 1) << DSP2_BACK_ENHANCE_LEVEL_W_POS)) -#define DSP2_BACK_EDGE_LIMIT_W DSP2_BACK_EDGE_LIMIT_W -#define DSP2_BACK_EDGE_LIMIT_W_POS (8U) -#define DSP2_BACK_EDGE_LIMIT_W_LEN (8U) -#define DSP2_BACK_EDGE_LIMIT_W_MSK (((1U << DSP2_BACK_EDGE_LIMIT_W_LEN) - 1) << DSP2_BACK_EDGE_LIMIT_W_POS) -#define DSP2_BACK_EDGE_LIMIT_W_UMSK (~(((1U << DSP2_BACK_EDGE_LIMIT_W_LEN) - 1) << DSP2_BACK_EDGE_LIMIT_W_POS)) -#define DSP2_BACK_HPF_RATE_W DSP2_BACK_HPF_RATE_W -#define DSP2_BACK_HPF_RATE_W_POS (16U) -#define DSP2_BACK_HPF_RATE_W_LEN (4U) -#define DSP2_BACK_HPF_RATE_W_MSK (((1U << DSP2_BACK_HPF_RATE_W_LEN) - 1) << DSP2_BACK_HPF_RATE_W_POS) -#define DSP2_BACK_HPF_RATE_W_UMSK (~(((1U << DSP2_BACK_HPF_RATE_W_LEN) - 1) << DSP2_BACK_HPF_RATE_W_POS)) -#define DSP2_BACK_NOISE_THRESHOLD_PRE DSP2_BACK_NOISE_THRESHOLD_PRE -#define DSP2_BACK_NOISE_THRESHOLD_PRE_POS (24U) -#define DSP2_BACK_NOISE_THRESHOLD_PRE_LEN (7U) -#define DSP2_BACK_NOISE_THRESHOLD_PRE_MSK (((1U << DSP2_BACK_NOISE_THRESHOLD_PRE_LEN) - 1) << DSP2_BACK_NOISE_THRESHOLD_PRE_POS) -#define DSP2_BACK_NOISE_THRESHOLD_PRE_UMSK (~(((1U << DSP2_BACK_NOISE_THRESHOLD_PRE_LEN) - 1) << DSP2_BACK_NOISE_THRESHOLD_PRE_POS)) - -/* 0x34C : YUVC_A */ -#define DSP2_BACK_YUVC_A_OFFSET (0x34C) -#define DSP2_BACK_YBRIGHTNESS_W DSP2_BACK_YBRIGHTNESS_W -#define DSP2_BACK_YBRIGHTNESS_W_POS (0U) -#define DSP2_BACK_YBRIGHTNESS_W_LEN (8U) -#define DSP2_BACK_YBRIGHTNESS_W_MSK (((1U << DSP2_BACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BACK_YBRIGHTNESS_W_POS) -#define DSP2_BACK_YBRIGHTNESS_W_UMSK (~(((1U << DSP2_BACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BACK_YBRIGHTNESS_W_POS)) -#define DSP2_BACK_YCONTRAST_W DSP2_BACK_YCONTRAST_W -#define DSP2_BACK_YCONTRAST_W_POS (8U) -#define DSP2_BACK_YCONTRAST_W_LEN (8U) -#define DSP2_BACK_YCONTRAST_W_MSK (((1U << DSP2_BACK_YCONTRAST_W_LEN) - 1) << DSP2_BACK_YCONTRAST_W_POS) -#define DSP2_BACK_YCONTRAST_W_UMSK (~(((1U << DSP2_BACK_YCONTRAST_W_LEN) - 1) << DSP2_BACK_YCONTRAST_W_POS)) -#define DSP2_BACK_CBSATURATION_PRE DSP2_BACK_CBSATURATION_PRE -#define DSP2_BACK_CBSATURATION_PRE_POS (16U) -#define DSP2_BACK_CBSATURATION_PRE_LEN (8U) -#define DSP2_BACK_CBSATURATION_PRE_MSK (((1U << DSP2_BACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BACK_CBSATURATION_PRE_POS) -#define DSP2_BACK_CBSATURATION_PRE_UMSK (~(((1U << DSP2_BACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BACK_CBSATURATION_PRE_POS)) -#define DSP2_BACK_CRSATURATION_PRE DSP2_BACK_CRSATURATION_PRE -#define DSP2_BACK_CRSATURATION_PRE_POS (24U) -#define DSP2_BACK_CRSATURATION_PRE_LEN (8U) -#define DSP2_BACK_CRSATURATION_PRE_MSK (((1U << DSP2_BACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BACK_CRSATURATION_PRE_POS) -#define DSP2_BACK_CRSATURATION_PRE_UMSK (~(((1U << DSP2_BACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BACK_CRSATURATION_PRE_POS)) - -/* 0x350 : YUVC_B */ -#define DSP2_BACK_YUVC_B_OFFSET (0x350) -#define DSP2_BACK_SPECIALMODE_W DSP2_BACK_SPECIALMODE_W -#define DSP2_BACK_SPECIALMODE_W_POS (0U) -#define DSP2_BACK_SPECIALMODE_W_LEN (3U) -#define DSP2_BACK_SPECIALMODE_W_MSK (((1U << DSP2_BACK_SPECIALMODE_W_LEN) - 1) << DSP2_BACK_SPECIALMODE_W_POS) -#define DSP2_BACK_SPECIALMODE_W_UMSK (~(((1U << DSP2_BACK_SPECIALMODE_W_LEN) - 1) << DSP2_BACK_SPECIALMODE_W_POS)) -#define DSP2_BACK_C444TO422FILTERINGMODE_W DSP2_BACK_C444TO422FILTERINGMODE_W -#define DSP2_BACK_C444TO422FILTERINGMODE_W_POS (4U) -#define DSP2_BACK_C444TO422FILTERINGMODE_W_LEN (1U) -#define DSP2_BACK_C444TO422FILTERINGMODE_W_MSK (((1U << DSP2_BACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BACK_C444TO422FILTERINGMODE_W_POS) -#define DSP2_BACK_C444TO422FILTERINGMODE_W_UMSK (~(((1U << DSP2_BACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BACK_C444TO422FILTERINGMODE_W_POS)) -#define DSP2_BACK_SEPIACB_W DSP2_BACK_SEPIACB_W -#define DSP2_BACK_SEPIACB_W_POS (8U) -#define DSP2_BACK_SEPIACB_W_LEN (8U) -#define DSP2_BACK_SEPIACB_W_MSK (((1U << DSP2_BACK_SEPIACB_W_LEN) - 1) << DSP2_BACK_SEPIACB_W_POS) -#define DSP2_BACK_SEPIACB_W_UMSK (~(((1U << DSP2_BACK_SEPIACB_W_LEN) - 1) << DSP2_BACK_SEPIACB_W_POS)) -#define DSP2_BACK_SEPIACR_W DSP2_BACK_SEPIACR_W -#define DSP2_BACK_SEPIACR_W_POS (16U) -#define DSP2_BACK_SEPIACR_W_LEN (8U) -#define DSP2_BACK_SEPIACR_W_MSK (((1U << DSP2_BACK_SEPIACR_W_LEN) - 1) << DSP2_BACK_SEPIACR_W_POS) -#define DSP2_BACK_SEPIACR_W_UMSK (~(((1U << DSP2_BACK_SEPIACR_W_LEN) - 1) << DSP2_BACK_SEPIACR_W_POS)) -#define DSP2_BACK_SOLARTHRED_W DSP2_BACK_SOLARTHRED_W -#define DSP2_BACK_SOLARTHRED_W_POS (24U) -#define DSP2_BACK_SOLARTHRED_W_LEN (8U) -#define DSP2_BACK_SOLARTHRED_W_MSK (((1U << DSP2_BACK_SOLARTHRED_W_LEN) - 1) << DSP2_BACK_SOLARTHRED_W_POS) -#define DSP2_BACK_SOLARTHRED_W_UMSK (~(((1U << DSP2_BACK_SOLARTHRED_W_LEN) - 1) << DSP2_BACK_SOLARTHRED_W_POS)) - -/* 0x354 : DNR_A */ -#define DSP2_BACK_DNR_A_OFFSET (0x354) -#define DSP2_BACK_NOISE_LEVEL_PRE DSP2_BACK_NOISE_LEVEL_PRE -#define DSP2_BACK_NOISE_LEVEL_PRE_POS (0U) -#define DSP2_BACK_NOISE_LEVEL_PRE_LEN (6U) -#define DSP2_BACK_NOISE_LEVEL_PRE_MSK (((1U << DSP2_BACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BACK_NOISE_LEVEL_PRE_POS) -#define DSP2_BACK_NOISE_LEVEL_PRE_UMSK (~(((1U << DSP2_BACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BACK_NOISE_LEVEL_PRE_POS)) -#define DSP2_BACK_NR_HSIZE_PRE DSP2_BACK_NR_HSIZE_PRE -#define DSP2_BACK_NR_HSIZE_PRE_POS (8U) -#define DSP2_BACK_NR_HSIZE_PRE_LEN (16U) -#define DSP2_BACK_NR_HSIZE_PRE_MSK (((1U << DSP2_BACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BACK_NR_HSIZE_PRE_POS) -#define DSP2_BACK_NR_HSIZE_PRE_UMSK (~(((1U << DSP2_BACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BACK_NR_HSIZE_PRE_POS)) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE DSP2_BACK_FILT_STRENGTH_2D_PRE -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_POS (24U) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_LEN (4U) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_MSK (((1U << DSP2_BACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_2D_PRE_POS) -#define DSP2_BACK_FILT_STRENGTH_2D_PRE_UMSK (~(((1U << DSP2_BACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_2D_PRE_POS)) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE DSP2_BACK_FILT_STRENGTH_3D_PRE -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_POS (28U) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_LEN (4U) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_MSK (((1U << DSP2_BACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_3D_PRE_POS) -#define DSP2_BACK_FILT_STRENGTH_3D_PRE_UMSK (~(((1U << DSP2_BACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BACK_FILT_STRENGTH_3D_PRE_POS)) - -/* 0x358 : DNR_B */ -#define DSP2_BACK_DNR_B_OFFSET (0x358) -#define DSP2_BACK_DELAYNUM3DNR_W DSP2_BACK_DELAYNUM3DNR_W -#define DSP2_BACK_DELAYNUM3DNR_W_POS (0U) -#define DSP2_BACK_DELAYNUM3DNR_W_LEN (3U) -#define DSP2_BACK_DELAYNUM3DNR_W_MSK (((1U << DSP2_BACK_DELAYNUM3DNR_W_LEN) - 1) << DSP2_BACK_DELAYNUM3DNR_W_POS) -#define DSP2_BACK_DELAYNUM3DNR_W_UMSK (~(((1U << DSP2_BACK_DELAYNUM3DNR_W_LEN) - 1) << DSP2_BACK_DELAYNUM3DNR_W_POS)) -#define DSP2_BACK_CBCR_SELECT_W DSP2_BACK_CBCR_SELECT_W -#define DSP2_BACK_CBCR_SELECT_W_POS (8U) -#define DSP2_BACK_CBCR_SELECT_W_LEN (1U) -#define DSP2_BACK_CBCR_SELECT_W_MSK (((1U << DSP2_BACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BACK_CBCR_SELECT_W_POS) -#define DSP2_BACK_CBCR_SELECT_W_UMSK (~(((1U << DSP2_BACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BACK_CBCR_SELECT_W_POS)) -#define DSP2_BACK_OUT_FORMAT_W DSP2_BACK_OUT_FORMAT_W -#define DSP2_BACK_OUT_FORMAT_W_POS (9U) -#define DSP2_BACK_OUT_FORMAT_W_LEN (2U) -#define DSP2_BACK_OUT_FORMAT_W_MSK (((1U << DSP2_BACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BACK_OUT_FORMAT_W_POS) -#define DSP2_BACK_OUT_FORMAT_W_UMSK (~(((1U << DSP2_BACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BACK_OUT_FORMAT_W_POS)) - -/* 0x3FF : DVI_HDMI_MODE */ -#define DSP2_BACK_DVI_HDMI_MODE_OFFSET (0x3FF) -#define DSP2_BACK_DVI_HDMI_MODE_W DSP2_BACK_DVI_HDMI_MODE_W -#define DSP2_BACK_DVI_HDMI_MODE_W_POS (0U) -#define DSP2_BACK_DVI_HDMI_MODE_W_LEN (1U) -#define DSP2_BACK_DVI_HDMI_MODE_W_MSK (((1U << DSP2_BACK_DVI_HDMI_MODE_W_LEN) - 1) << DSP2_BACK_DVI_HDMI_MODE_W_POS) -#define DSP2_BACK_DVI_HDMI_MODE_W_UMSK (~(((1U << DSP2_BACK_DVI_HDMI_MODE_W_LEN) - 1) << DSP2_BACK_DVI_HDMI_MODE_W_POS)) - -struct dsp2_back_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[788]; - - /* 0x314 : ccr_coef_A */ - union { - struct - { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t a11_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_A; - - /* 0x318 : ccr_coef_B */ - union { - struct - { - uint32_t a12_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a13_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_B; - - /* 0x31C : ccr_coef_C */ - union { - struct - { - uint32_t a21_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a22_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_C; - - /* 0x320 : ccr_coef_D */ - union { - struct - { - uint32_t a23_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a31_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_D; - - /* 0x324 : ccr_coef_E */ - union { - struct - { - uint32_t a32_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a33_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_E; - - /* 0x328 : gamma_A */ - union { - struct - { - uint32_t gamma_on_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t gamma_eb_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t b0_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t b1_pre : 8; /* [23:16], r/w, 0x4 */ - uint32_t b2_pre : 8; /* [31:24], r/w, 0x8 */ - } BF; - uint32_t WORD; - } gamma_A; - - /* 0x32C : gamma_B */ - union { - struct - { - uint32_t b3_pre : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t b4_pre : 8; /* [15: 8], r/w, 0x20 */ - uint32_t b5_pre : 8; /* [23:16], r/w, 0x30 */ - uint32_t b6_pre : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } gamma_B; - - /* 0x330 : gamma_C */ - union { - struct - { - uint32_t b7_pre : 8; /* [ 7: 0], r/w, 0x50 */ - uint32_t b8_pre : 8; /* [15: 8], r/w, 0x60 */ - uint32_t b9_pre : 8; /* [23:16], r/w, 0x70 */ - uint32_t b10_pre : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } gamma_C; - - /* 0x334 : gamma_D */ - union { - struct - { - uint32_t b11_pre : 8; /* [ 7: 0], r/w, 0x90 */ - uint32_t b12_pre : 8; /* [15: 8], r/w, 0xa0 */ - uint32_t b13_pre : 8; /* [23:16], r/w, 0xb0 */ - uint32_t b14_pre : 8; /* [31:24], r/w, 0xc0 */ - } BF; - uint32_t WORD; - } gamma_D; - - /* 0x338 : gamma_E */ - union { - struct - { - uint32_t b15_pre : 8; /* [ 7: 0], r/w, 0xd0 */ - uint32_t b16_pre : 8; /* [15: 8], r/w, 0xe0 */ - uint32_t b17_pre : 8; /* [23:16], r/w, 0xf0 */ - uint32_t b18_pre : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } gamma_E; - - /* 0x33C : conv_mode */ - union { - struct - { - uint32_t conv_mode_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } conv_mode; - - /* 0x340 reserved */ - uint8_t RESERVED0x340[8]; - - /* 0x348 : edge_enhance */ - union { - struct - { - uint32_t enhance_level_w : 7; /* [ 6: 0], r/w, 0x69 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t edge_limit_w : 8; /* [15: 8], r/w, 0x30 */ - uint32_t HPF_rate_w : 4; /* [19:16], r/w, 0x4 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t noise_threshold_pre : 7; /* [30:24], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } edge_enhance; - - /* 0x34C : YUVC_A */ - union { - struct - { - uint32_t YBrightness_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t YContrast_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t CbSaturation_pre : 8; /* [23:16], r/w, 0x80 */ - uint32_t CrSaturation_pre : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_A; - - /* 0x350 : YUVC_B */ - union { - struct - { - uint32_t SpecialMode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t C444to422Filteringmode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t SepiaCb_w : 8; /* [15: 8], r/w, 0x73 */ - uint32_t SepiaCr_w : 8; /* [23:16], r/w, 0x89 */ - uint32_t SolarThred_w : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_B; - - /* 0x354 : DNR_A */ - union { - struct - { - uint32_t noise_level_pre : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t nr_hsize_pre : 16; /* [23: 8], r/w, 0x788 */ - uint32_t Filt_Strength_2D_pre : 4; /* [27:24], r/w, 0x6 */ - uint32_t Filt_Strength_3D_pre : 4; /* [31:28], r/w, 0x5 */ - } BF; - uint32_t WORD; - } DNR_A; - - /* 0x358 : DNR_B */ - union { - struct - { - uint32_t DelayNum3DNR_w : 3; /* [ 2: 0], r/w, 0x4 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t CbCr_select_w : 1; /* [ 8], r/w, 0x1 */ - uint32_t out_format_w : 2; /* [10: 9], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DNR_B; - - /* 0x35c reserved */ - uint8_t RESERVED0x35c[163]; - - /* 0x3FF : DVI_HDMI_MODE */ - union { - struct - { - uint32_t DVI_HDMI_MODE_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DVI_HDMI_MODE; -}; - -typedef volatile struct dsp2_back_reg dsp2_back_reg_t; - -#endif /* __DSP2_BACK_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blae_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blae_reg.h deleted file mode 100644 index f347e0fed3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blae_reg.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_blae_reg.h - * @version V1.2 - * @date 2019-03-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BLAE_REG_H__ -#define __DSP2_BLAE_REG_H__ - -#include "bl808.h" - -/* 0x500 : blae_read_grid_addr */ -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_OFFSET (0x500) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR DSP2_BLAE_BLAE_READ_GRID_ADDR -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_POS (0U) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_LEN (9U) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_MSK (((1U << DSP2_BLAE_BLAE_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAE_BLAE_READ_GRID_ADDR_POS) -#define DSP2_BLAE_BLAE_READ_GRID_ADDR_UMSK (~(((1U << DSP2_BLAE_BLAE_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAE_BLAE_READ_GRID_ADDR_POS)) -#define DSP2_BLAE_BLAE_BUF_IDX DSP2_BLAE_BLAE_BUF_IDX -#define DSP2_BLAE_BLAE_BUF_IDX_POS (16U) -#define DSP2_BLAE_BLAE_BUF_IDX_LEN (1U) -#define DSP2_BLAE_BLAE_BUF_IDX_MSK (((1U << DSP2_BLAE_BLAE_BUF_IDX_LEN) - 1) << DSP2_BLAE_BLAE_BUF_IDX_POS) -#define DSP2_BLAE_BLAE_BUF_IDX_UMSK (~(((1U << DSP2_BLAE_BLAE_BUF_IDX_LEN) - 1) << DSP2_BLAE_BLAE_BUF_IDX_POS)) -#define DSP2_BLAE_BLAE_W_CNT DSP2_BLAE_BLAE_W_CNT -#define DSP2_BLAE_BLAE_W_CNT_POS (20U) -#define DSP2_BLAE_BLAE_W_CNT_LEN (5U) -#define DSP2_BLAE_BLAE_W_CNT_MSK (((1U << DSP2_BLAE_BLAE_W_CNT_LEN) - 1) << DSP2_BLAE_BLAE_W_CNT_POS) -#define DSP2_BLAE_BLAE_W_CNT_UMSK (~(((1U << DSP2_BLAE_BLAE_W_CNT_LEN) - 1) << DSP2_BLAE_BLAE_W_CNT_POS)) - -/* 0x504 : blae_grid_data */ -#define DSP2_BLAE_BLAE_GRID_DATA_OFFSET (0x504) -#define DSP2_BLAE_BLAE_GRID_DATA DSP2_BLAE_BLAE_GRID_DATA -#define DSP2_BLAE_BLAE_GRID_DATA_POS (0U) -#define DSP2_BLAE_BLAE_GRID_DATA_LEN (32U) -#define DSP2_BLAE_BLAE_GRID_DATA_MSK (((1U << DSP2_BLAE_BLAE_GRID_DATA_LEN) - 1) << DSP2_BLAE_BLAE_GRID_DATA_POS) -#define DSP2_BLAE_BLAE_GRID_DATA_UMSK (~(((1U << DSP2_BLAE_BLAE_GRID_DATA_LEN) - 1) << DSP2_BLAE_BLAE_GRID_DATA_POS)) - -struct dsp2_blae_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1280]; - - /* 0x500 : blae_read_grid_addr */ - union { - struct { - uint32_t blae_read_grid_addr : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t blae_buf_idx : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t blae_w_cnt : 5; /* [24:20], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } blae_read_grid_addr; - - /* 0x504 : blae_grid_data */ - union { - struct { - uint32_t blae_grid_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } blae_grid_data; -}; - -typedef volatile struct dsp2_blae_reg dsp2_blae_reg_t; - -#endif /* __DSP2_BLAE_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blawb_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blawb_reg.h deleted file mode 100644 index 0ab82e1902..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blawb_reg.h +++ /dev/null @@ -1,95 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_blawb_reg.h - * @version V1.2 - * @date 2019-04-25 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BLAWB_REG_H__ -#define __DSP2_BLAWB_REG_H__ - -#include "bl808.h" - -/* 0x600 : blawb_read_grid_addr */ -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_OFFSET (0x600) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR DSP2_BLAWB_BLAWB_READ_GRID_ADDR -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_POS (0U) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_LEN (12U) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_MSK (((1U << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_POS) -#define DSP2_BLAWB_BLAWB_READ_GRID_ADDR_UMSK (~(((1U << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_LEN) - 1) << DSP2_BLAWB_BLAWB_READ_GRID_ADDR_POS)) -#define DSP2_BLAWB_BLAWB_BUF_IDX DSP2_BLAWB_BLAWB_BUF_IDX -#define DSP2_BLAWB_BLAWB_BUF_IDX_POS (16U) -#define DSP2_BLAWB_BLAWB_BUF_IDX_LEN (1U) -#define DSP2_BLAWB_BLAWB_BUF_IDX_MSK (((1U << DSP2_BLAWB_BLAWB_BUF_IDX_LEN) - 1) << DSP2_BLAWB_BLAWB_BUF_IDX_POS) -#define DSP2_BLAWB_BLAWB_BUF_IDX_UMSK (~(((1U << DSP2_BLAWB_BLAWB_BUF_IDX_LEN) - 1) << DSP2_BLAWB_BLAWB_BUF_IDX_POS)) -#define DSP2_BLAWB_BLAWB_W_CNT DSP2_BLAWB_BLAWB_W_CNT -#define DSP2_BLAWB_BLAWB_W_CNT_POS (20U) -#define DSP2_BLAWB_BLAWB_W_CNT_LEN (5U) -#define DSP2_BLAWB_BLAWB_W_CNT_MSK (((1U << DSP2_BLAWB_BLAWB_W_CNT_LEN) - 1) << DSP2_BLAWB_BLAWB_W_CNT_POS) -#define DSP2_BLAWB_BLAWB_W_CNT_UMSK (~(((1U << DSP2_BLAWB_BLAWB_W_CNT_LEN) - 1) << DSP2_BLAWB_BLAWB_W_CNT_POS)) - -/* 0x604 : blawb_grid_data */ -#define DSP2_BLAWB_BLAWB_GRID_DATA_OFFSET (0x604) -#define DSP2_BLAWB_BLAWB_GRID_DATA DSP2_BLAWB_BLAWB_GRID_DATA -#define DSP2_BLAWB_BLAWB_GRID_DATA_POS (0U) -#define DSP2_BLAWB_BLAWB_GRID_DATA_LEN (32U) -#define DSP2_BLAWB_BLAWB_GRID_DATA_MSK (((1U << DSP2_BLAWB_BLAWB_GRID_DATA_LEN) - 1) << DSP2_BLAWB_BLAWB_GRID_DATA_POS) -#define DSP2_BLAWB_BLAWB_GRID_DATA_UMSK (~(((1U << DSP2_BLAWB_BLAWB_GRID_DATA_LEN) - 1) << DSP2_BLAWB_BLAWB_GRID_DATA_POS)) - -struct dsp2_blawb_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1536]; - - /* 0x600 : blawb_read_grid_addr */ - union { - struct { - uint32_t blawb_read_grid_addr : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t blawb_buf_idx : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t blawb_w_cnt : 5; /* [24:20], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } blawb_read_grid_addr; - - /* 0x604 : blawb_grid_data */ - union { - struct { - uint32_t blawb_grid_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } blawb_grid_data; -}; - -typedef volatile struct dsp2_blawb_reg dsp2_blawb_reg_t; - -#endif /* __DSP2_BLAWB_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blback_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blback_reg.h deleted file mode 100644 index 09e0f3dc07..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_blback_reg.h +++ /dev/null @@ -1,8061 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_blback_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_BLBACK_REG_H__ -#define __DSP2_BLBACK_REG_H__ - -#include "bl808.h" - -/* 0x314 : ccr_coef_A */ -#define DSP2_BLBACK_CCR_COEF_A_OFFSET (0x314) -#define DSP2_BLBACK_A11_PRE DSP2_BLBACK_A11_PRE -#define DSP2_BLBACK_A11_PRE_POS (16U) -#define DSP2_BLBACK_A11_PRE_LEN (12U) -#define DSP2_BLBACK_A11_PRE_MSK (((1U << DSP2_BLBACK_A11_PRE_LEN) - 1) << DSP2_BLBACK_A11_PRE_POS) -#define DSP2_BLBACK_A11_PRE_UMSK (~(((1U << DSP2_BLBACK_A11_PRE_LEN) - 1) << DSP2_BLBACK_A11_PRE_POS)) - -/* 0x318 : ccr_coef_B */ -#define DSP2_BLBACK_CCR_COEF_B_OFFSET (0x318) -#define DSP2_BLBACK_A12_PRE DSP2_BLBACK_A12_PRE -#define DSP2_BLBACK_A12_PRE_POS (0U) -#define DSP2_BLBACK_A12_PRE_LEN (12U) -#define DSP2_BLBACK_A12_PRE_MSK (((1U << DSP2_BLBACK_A12_PRE_LEN) - 1) << DSP2_BLBACK_A12_PRE_POS) -#define DSP2_BLBACK_A12_PRE_UMSK (~(((1U << DSP2_BLBACK_A12_PRE_LEN) - 1) << DSP2_BLBACK_A12_PRE_POS)) -#define DSP2_BLBACK_A13_PRE DSP2_BLBACK_A13_PRE -#define DSP2_BLBACK_A13_PRE_POS (16U) -#define DSP2_BLBACK_A13_PRE_LEN (12U) -#define DSP2_BLBACK_A13_PRE_MSK (((1U << DSP2_BLBACK_A13_PRE_LEN) - 1) << DSP2_BLBACK_A13_PRE_POS) -#define DSP2_BLBACK_A13_PRE_UMSK (~(((1U << DSP2_BLBACK_A13_PRE_LEN) - 1) << DSP2_BLBACK_A13_PRE_POS)) - -/* 0x31C : ccr_coef_C */ -#define DSP2_BLBACK_CCR_COEF_C_OFFSET (0x31C) -#define DSP2_BLBACK_A21_PRE DSP2_BLBACK_A21_PRE -#define DSP2_BLBACK_A21_PRE_POS (0U) -#define DSP2_BLBACK_A21_PRE_LEN (12U) -#define DSP2_BLBACK_A21_PRE_MSK (((1U << DSP2_BLBACK_A21_PRE_LEN) - 1) << DSP2_BLBACK_A21_PRE_POS) -#define DSP2_BLBACK_A21_PRE_UMSK (~(((1U << DSP2_BLBACK_A21_PRE_LEN) - 1) << DSP2_BLBACK_A21_PRE_POS)) -#define DSP2_BLBACK_A22_PRE DSP2_BLBACK_A22_PRE -#define DSP2_BLBACK_A22_PRE_POS (16U) -#define DSP2_BLBACK_A22_PRE_LEN (12U) -#define DSP2_BLBACK_A22_PRE_MSK (((1U << DSP2_BLBACK_A22_PRE_LEN) - 1) << DSP2_BLBACK_A22_PRE_POS) -#define DSP2_BLBACK_A22_PRE_UMSK (~(((1U << DSP2_BLBACK_A22_PRE_LEN) - 1) << DSP2_BLBACK_A22_PRE_POS)) - -/* 0x320 : ccr_coef_D */ -#define DSP2_BLBACK_CCR_COEF_D_OFFSET (0x320) -#define DSP2_BLBACK_A23_PRE DSP2_BLBACK_A23_PRE -#define DSP2_BLBACK_A23_PRE_POS (0U) -#define DSP2_BLBACK_A23_PRE_LEN (12U) -#define DSP2_BLBACK_A23_PRE_MSK (((1U << DSP2_BLBACK_A23_PRE_LEN) - 1) << DSP2_BLBACK_A23_PRE_POS) -#define DSP2_BLBACK_A23_PRE_UMSK (~(((1U << DSP2_BLBACK_A23_PRE_LEN) - 1) << DSP2_BLBACK_A23_PRE_POS)) -#define DSP2_BLBACK_A31_PRE DSP2_BLBACK_A31_PRE -#define DSP2_BLBACK_A31_PRE_POS (16U) -#define DSP2_BLBACK_A31_PRE_LEN (12U) -#define DSP2_BLBACK_A31_PRE_MSK (((1U << DSP2_BLBACK_A31_PRE_LEN) - 1) << DSP2_BLBACK_A31_PRE_POS) -#define DSP2_BLBACK_A31_PRE_UMSK (~(((1U << DSP2_BLBACK_A31_PRE_LEN) - 1) << DSP2_BLBACK_A31_PRE_POS)) - -/* 0x324 : ccr_coef_E */ -#define DSP2_BLBACK_CCR_COEF_E_OFFSET (0x324) -#define DSP2_BLBACK_A32_PRE DSP2_BLBACK_A32_PRE -#define DSP2_BLBACK_A32_PRE_POS (0U) -#define DSP2_BLBACK_A32_PRE_LEN (12U) -#define DSP2_BLBACK_A32_PRE_MSK (((1U << DSP2_BLBACK_A32_PRE_LEN) - 1) << DSP2_BLBACK_A32_PRE_POS) -#define DSP2_BLBACK_A32_PRE_UMSK (~(((1U << DSP2_BLBACK_A32_PRE_LEN) - 1) << DSP2_BLBACK_A32_PRE_POS)) -#define DSP2_BLBACK_A33_PRE DSP2_BLBACK_A33_PRE -#define DSP2_BLBACK_A33_PRE_POS (16U) -#define DSP2_BLBACK_A33_PRE_LEN (12U) -#define DSP2_BLBACK_A33_PRE_MSK (((1U << DSP2_BLBACK_A33_PRE_LEN) - 1) << DSP2_BLBACK_A33_PRE_POS) -#define DSP2_BLBACK_A33_PRE_UMSK (~(((1U << DSP2_BLBACK_A33_PRE_LEN) - 1) << DSP2_BLBACK_A33_PRE_POS)) - -/* 0x328 : gamma_A */ -#define DSP2_BLBACK_GAMMA_A_OFFSET (0x328) -#define DSP2_BLBACK_GAMMA_ON_PRE DSP2_BLBACK_GAMMA_ON_PRE -#define DSP2_BLBACK_GAMMA_ON_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_ON_PRE_LEN (1U) -#define DSP2_BLBACK_GAMMA_ON_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_ON_PRE_POS) -#define DSP2_BLBACK_GAMMA_ON_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_ON_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_ON_PRE_POS)) -#define DSP2_BLBACK_GAMMA_EB_PRE DSP2_BLBACK_GAMMA_EB_PRE -#define DSP2_BLBACK_GAMMA_EB_PRE_POS (1U) -#define DSP2_BLBACK_GAMMA_EB_PRE_LEN (1U) -#define DSP2_BLBACK_GAMMA_EB_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_EB_PRE_POS) -#define DSP2_BLBACK_GAMMA_EB_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_EB_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_EB_PRE_POS)) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE DSP2_BLBACK_BL_GAMMA_EN_PRE -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_POS (4U) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_LEN (1U) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_MSK (((1U << DSP2_BLBACK_BL_GAMMA_EN_PRE_LEN) - 1) << DSP2_BLBACK_BL_GAMMA_EN_PRE_POS) -#define DSP2_BLBACK_BL_GAMMA_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_BL_GAMMA_EN_PRE_LEN) - 1) << DSP2_BLBACK_BL_GAMMA_EN_PRE_POS)) - -/* 0x33C : conv_mode */ -#define DSP2_BLBACK_CONV_MODE_OFFSET (0x33C) -#define DSP2_BLBACK_CONV_MODE_W DSP2_BLBACK_CONV_MODE_W -#define DSP2_BLBACK_CONV_MODE_W_POS (0U) -#define DSP2_BLBACK_CONV_MODE_W_LEN (1U) -#define DSP2_BLBACK_CONV_MODE_W_MSK (((1U << DSP2_BLBACK_CONV_MODE_W_LEN) - 1) << DSP2_BLBACK_CONV_MODE_W_POS) -#define DSP2_BLBACK_CONV_MODE_W_UMSK (~(((1U << DSP2_BLBACK_CONV_MODE_W_LEN) - 1) << DSP2_BLBACK_CONV_MODE_W_POS)) - -/* 0x34C : YUVC_A */ -#define DSP2_BLBACK_YUVC_A_OFFSET (0x34C) -#define DSP2_BLBACK_YBRIGHTNESS_W DSP2_BLBACK_YBRIGHTNESS_W -#define DSP2_BLBACK_YBRIGHTNESS_W_POS (0U) -#define DSP2_BLBACK_YBRIGHTNESS_W_LEN (8U) -#define DSP2_BLBACK_YBRIGHTNESS_W_MSK (((1U << DSP2_BLBACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BLBACK_YBRIGHTNESS_W_POS) -#define DSP2_BLBACK_YBRIGHTNESS_W_UMSK (~(((1U << DSP2_BLBACK_YBRIGHTNESS_W_LEN) - 1) << DSP2_BLBACK_YBRIGHTNESS_W_POS)) -#define DSP2_BLBACK_YCONTRAST_W DSP2_BLBACK_YCONTRAST_W -#define DSP2_BLBACK_YCONTRAST_W_POS (8U) -#define DSP2_BLBACK_YCONTRAST_W_LEN (8U) -#define DSP2_BLBACK_YCONTRAST_W_MSK (((1U << DSP2_BLBACK_YCONTRAST_W_LEN) - 1) << DSP2_BLBACK_YCONTRAST_W_POS) -#define DSP2_BLBACK_YCONTRAST_W_UMSK (~(((1U << DSP2_BLBACK_YCONTRAST_W_LEN) - 1) << DSP2_BLBACK_YCONTRAST_W_POS)) -#define DSP2_BLBACK_CBSATURATION_PRE DSP2_BLBACK_CBSATURATION_PRE -#define DSP2_BLBACK_CBSATURATION_PRE_POS (16U) -#define DSP2_BLBACK_CBSATURATION_PRE_LEN (8U) -#define DSP2_BLBACK_CBSATURATION_PRE_MSK (((1U << DSP2_BLBACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CBSATURATION_PRE_POS) -#define DSP2_BLBACK_CBSATURATION_PRE_UMSK (~(((1U << DSP2_BLBACK_CBSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CBSATURATION_PRE_POS)) -#define DSP2_BLBACK_CRSATURATION_PRE DSP2_BLBACK_CRSATURATION_PRE -#define DSP2_BLBACK_CRSATURATION_PRE_POS (24U) -#define DSP2_BLBACK_CRSATURATION_PRE_LEN (8U) -#define DSP2_BLBACK_CRSATURATION_PRE_MSK (((1U << DSP2_BLBACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CRSATURATION_PRE_POS) -#define DSP2_BLBACK_CRSATURATION_PRE_UMSK (~(((1U << DSP2_BLBACK_CRSATURATION_PRE_LEN) - 1) << DSP2_BLBACK_CRSATURATION_PRE_POS)) - -/* 0x350 : YUVC_B */ -#define DSP2_BLBACK_YUVC_B_OFFSET (0x350) -#define DSP2_BLBACK_SPECIALMODE_W DSP2_BLBACK_SPECIALMODE_W -#define DSP2_BLBACK_SPECIALMODE_W_POS (0U) -#define DSP2_BLBACK_SPECIALMODE_W_LEN (3U) -#define DSP2_BLBACK_SPECIALMODE_W_MSK (((1U << DSP2_BLBACK_SPECIALMODE_W_LEN) - 1) << DSP2_BLBACK_SPECIALMODE_W_POS) -#define DSP2_BLBACK_SPECIALMODE_W_UMSK (~(((1U << DSP2_BLBACK_SPECIALMODE_W_LEN) - 1) << DSP2_BLBACK_SPECIALMODE_W_POS)) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W DSP2_BLBACK_C444TO422FILTERINGMODE_W -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_POS (4U) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_LEN (1U) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_MSK (((1U << DSP2_BLBACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BLBACK_C444TO422FILTERINGMODE_W_POS) -#define DSP2_BLBACK_C444TO422FILTERINGMODE_W_UMSK (~(((1U << DSP2_BLBACK_C444TO422FILTERINGMODE_W_LEN) - 1) << DSP2_BLBACK_C444TO422FILTERINGMODE_W_POS)) -#define DSP2_BLBACK_SEPIACB_W DSP2_BLBACK_SEPIACB_W -#define DSP2_BLBACK_SEPIACB_W_POS (8U) -#define DSP2_BLBACK_SEPIACB_W_LEN (8U) -#define DSP2_BLBACK_SEPIACB_W_MSK (((1U << DSP2_BLBACK_SEPIACB_W_LEN) - 1) << DSP2_BLBACK_SEPIACB_W_POS) -#define DSP2_BLBACK_SEPIACB_W_UMSK (~(((1U << DSP2_BLBACK_SEPIACB_W_LEN) - 1) << DSP2_BLBACK_SEPIACB_W_POS)) -#define DSP2_BLBACK_SEPIACR_W DSP2_BLBACK_SEPIACR_W -#define DSP2_BLBACK_SEPIACR_W_POS (16U) -#define DSP2_BLBACK_SEPIACR_W_LEN (8U) -#define DSP2_BLBACK_SEPIACR_W_MSK (((1U << DSP2_BLBACK_SEPIACR_W_LEN) - 1) << DSP2_BLBACK_SEPIACR_W_POS) -#define DSP2_BLBACK_SEPIACR_W_UMSK (~(((1U << DSP2_BLBACK_SEPIACR_W_LEN) - 1) << DSP2_BLBACK_SEPIACR_W_POS)) -#define DSP2_BLBACK_SOLARTHRED_W DSP2_BLBACK_SOLARTHRED_W -#define DSP2_BLBACK_SOLARTHRED_W_POS (24U) -#define DSP2_BLBACK_SOLARTHRED_W_LEN (8U) -#define DSP2_BLBACK_SOLARTHRED_W_MSK (((1U << DSP2_BLBACK_SOLARTHRED_W_LEN) - 1) << DSP2_BLBACK_SOLARTHRED_W_POS) -#define DSP2_BLBACK_SOLARTHRED_W_UMSK (~(((1U << DSP2_BLBACK_SOLARTHRED_W_LEN) - 1) << DSP2_BLBACK_SOLARTHRED_W_POS)) - -/* 0x354 : DNR_A */ -#define DSP2_BLBACK_DNR_A_OFFSET (0x354) -#define DSP2_BLBACK_NOISE_LEVEL_PRE DSP2_BLBACK_NOISE_LEVEL_PRE -#define DSP2_BLBACK_NOISE_LEVEL_PRE_POS (0U) -#define DSP2_BLBACK_NOISE_LEVEL_PRE_LEN (6U) -#define DSP2_BLBACK_NOISE_LEVEL_PRE_MSK (((1U << DSP2_BLBACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BLBACK_NOISE_LEVEL_PRE_POS) -#define DSP2_BLBACK_NOISE_LEVEL_PRE_UMSK (~(((1U << DSP2_BLBACK_NOISE_LEVEL_PRE_LEN) - 1) << DSP2_BLBACK_NOISE_LEVEL_PRE_POS)) -#define DSP2_BLBACK_NR_HSIZE_PRE DSP2_BLBACK_NR_HSIZE_PRE -#define DSP2_BLBACK_NR_HSIZE_PRE_POS (8U) -#define DSP2_BLBACK_NR_HSIZE_PRE_LEN (16U) -#define DSP2_BLBACK_NR_HSIZE_PRE_MSK (((1U << DSP2_BLBACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BLBACK_NR_HSIZE_PRE_POS) -#define DSP2_BLBACK_NR_HSIZE_PRE_UMSK (~(((1U << DSP2_BLBACK_NR_HSIZE_PRE_LEN) - 1) << DSP2_BLBACK_NR_HSIZE_PRE_POS)) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE DSP2_BLBACK_FILT_STRENGTH_2D_PRE -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_POS (24U) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_LEN (4U) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_MSK (((1U << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_POS) -#define DSP2_BLBACK_FILT_STRENGTH_2D_PRE_UMSK (~(((1U << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_2D_PRE_POS)) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE DSP2_BLBACK_FILT_STRENGTH_3D_PRE -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_POS (28U) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_LEN (4U) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_MSK (((1U << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_POS) -#define DSP2_BLBACK_FILT_STRENGTH_3D_PRE_UMSK (~(((1U << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_LEN) - 1) << DSP2_BLBACK_FILT_STRENGTH_3D_PRE_POS)) - -/* 0x358 : DNR_B */ -#define DSP2_BLBACK_DNR_B_OFFSET (0x358) -#define DSP2_BLBACK_CBCR_SELECT_W DSP2_BLBACK_CBCR_SELECT_W -#define DSP2_BLBACK_CBCR_SELECT_W_POS (8U) -#define DSP2_BLBACK_CBCR_SELECT_W_LEN (1U) -#define DSP2_BLBACK_CBCR_SELECT_W_MSK (((1U << DSP2_BLBACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BLBACK_CBCR_SELECT_W_POS) -#define DSP2_BLBACK_CBCR_SELECT_W_UMSK (~(((1U << DSP2_BLBACK_CBCR_SELECT_W_LEN) - 1) << DSP2_BLBACK_CBCR_SELECT_W_POS)) -#define DSP2_BLBACK_OUT_FORMAT_W DSP2_BLBACK_OUT_FORMAT_W -#define DSP2_BLBACK_OUT_FORMAT_W_POS (9U) -#define DSP2_BLBACK_OUT_FORMAT_W_LEN (2U) -#define DSP2_BLBACK_OUT_FORMAT_W_MSK (((1U << DSP2_BLBACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BLBACK_OUT_FORMAT_W_POS) -#define DSP2_BLBACK_OUT_FORMAT_W_UMSK (~(((1U << DSP2_BLBACK_OUT_FORMAT_W_LEN) - 1) << DSP2_BLBACK_OUT_FORMAT_W_POS)) - -/* 0x360 : BLEE_0 */ -#define DSP2_BLBACK_BLEE_0_OFFSET (0x360) -#define DSP2_BLBACK_EE_EB_PRE DSP2_BLBACK_EE_EB_PRE -#define DSP2_BLBACK_EE_EB_PRE_POS (0U) -#define DSP2_BLBACK_EE_EB_PRE_LEN (1U) -#define DSP2_BLBACK_EE_EB_PRE_MSK (((1U << DSP2_BLBACK_EE_EB_PRE_LEN) - 1) << DSP2_BLBACK_EE_EB_PRE_POS) -#define DSP2_BLBACK_EE_EB_PRE_UMSK (~(((1U << DSP2_BLBACK_EE_EB_PRE_LEN) - 1) << DSP2_BLBACK_EE_EB_PRE_POS)) -#define DSP2_BLBACK_OVRSHT_EB_PRE DSP2_BLBACK_OVRSHT_EB_PRE -#define DSP2_BLBACK_OVRSHT_EB_PRE_POS (1U) -#define DSP2_BLBACK_OVRSHT_EB_PRE_LEN (1U) -#define DSP2_BLBACK_OVRSHT_EB_PRE_MSK (((1U << DSP2_BLBACK_OVRSHT_EB_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_EB_PRE_POS) -#define DSP2_BLBACK_OVRSHT_EB_PRE_UMSK (~(((1U << DSP2_BLBACK_OVRSHT_EB_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_EB_PRE_POS)) -#define DSP2_BLBACK_TXT_THR_PRE DSP2_BLBACK_TXT_THR_PRE -#define DSP2_BLBACK_TXT_THR_PRE_POS (16U) -#define DSP2_BLBACK_TXT_THR_PRE_LEN (9U) -#define DSP2_BLBACK_TXT_THR_PRE_MSK (((1U << DSP2_BLBACK_TXT_THR_PRE_LEN) - 1) << DSP2_BLBACK_TXT_THR_PRE_POS) -#define DSP2_BLBACK_TXT_THR_PRE_UMSK (~(((1U << DSP2_BLBACK_TXT_THR_PRE_LEN) - 1) << DSP2_BLBACK_TXT_THR_PRE_POS)) - -/* 0x364 : BLEE_1 */ -#define DSP2_BLBACK_BLEE_1_OFFSET (0x364) -#define DSP2_BLBACK_THRESH1_PRE DSP2_BLBACK_THRESH1_PRE -#define DSP2_BLBACK_THRESH1_PRE_POS (0U) -#define DSP2_BLBACK_THRESH1_PRE_LEN (7U) -#define DSP2_BLBACK_THRESH1_PRE_MSK (((1U << DSP2_BLBACK_THRESH1_PRE_LEN) - 1) << DSP2_BLBACK_THRESH1_PRE_POS) -#define DSP2_BLBACK_THRESH1_PRE_UMSK (~(((1U << DSP2_BLBACK_THRESH1_PRE_LEN) - 1) << DSP2_BLBACK_THRESH1_PRE_POS)) -#define DSP2_BLBACK_THRESH2_PRE DSP2_BLBACK_THRESH2_PRE -#define DSP2_BLBACK_THRESH2_PRE_POS (8U) -#define DSP2_BLBACK_THRESH2_PRE_LEN (7U) -#define DSP2_BLBACK_THRESH2_PRE_MSK (((1U << DSP2_BLBACK_THRESH2_PRE_LEN) - 1) << DSP2_BLBACK_THRESH2_PRE_POS) -#define DSP2_BLBACK_THRESH2_PRE_UMSK (~(((1U << DSP2_BLBACK_THRESH2_PRE_LEN) - 1) << DSP2_BLBACK_THRESH2_PRE_POS)) -#define DSP2_BLBACK_FLAT_THR_PRE DSP2_BLBACK_FLAT_THR_PRE -#define DSP2_BLBACK_FLAT_THR_PRE_POS (16U) -#define DSP2_BLBACK_FLAT_THR_PRE_LEN (8U) -#define DSP2_BLBACK_FLAT_THR_PRE_MSK (((1U << DSP2_BLBACK_FLAT_THR_PRE_LEN) - 1) << DSP2_BLBACK_FLAT_THR_PRE_POS) -#define DSP2_BLBACK_FLAT_THR_PRE_UMSK (~(((1U << DSP2_BLBACK_FLAT_THR_PRE_LEN) - 1) << DSP2_BLBACK_FLAT_THR_PRE_POS)) - -/* 0x368 : BLEE_2 */ -#define DSP2_BLBACK_BLEE_2_OFFSET (0x368) -#define DSP2_BLBACK_OVRSHT_POS_PRE DSP2_BLBACK_OVRSHT_POS_PRE -#define DSP2_BLBACK_OVRSHT_POS_PRE_POS (0U) -#define DSP2_BLBACK_OVRSHT_POS_PRE_LEN (7U) -#define DSP2_BLBACK_OVRSHT_POS_PRE_MSK (((1U << DSP2_BLBACK_OVRSHT_POS_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_POS_PRE_POS) -#define DSP2_BLBACK_OVRSHT_POS_PRE_UMSK (~(((1U << DSP2_BLBACK_OVRSHT_POS_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_POS_PRE_POS)) -#define DSP2_BLBACK_OVRSHT_NEG_PRE DSP2_BLBACK_OVRSHT_NEG_PRE -#define DSP2_BLBACK_OVRSHT_NEG_PRE_POS (8U) -#define DSP2_BLBACK_OVRSHT_NEG_PRE_LEN (7U) -#define DSP2_BLBACK_OVRSHT_NEG_PRE_MSK (((1U << DSP2_BLBACK_OVRSHT_NEG_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_NEG_PRE_POS) -#define DSP2_BLBACK_OVRSHT_NEG_PRE_UMSK (~(((1U << DSP2_BLBACK_OVRSHT_NEG_PRE_LEN) - 1) << DSP2_BLBACK_OVRSHT_NEG_PRE_POS)) -#define DSP2_BLBACK_POSEE_STR_PRE DSP2_BLBACK_POSEE_STR_PRE -#define DSP2_BLBACK_POSEE_STR_PRE_POS (16U) -#define DSP2_BLBACK_POSEE_STR_PRE_LEN (7U) -#define DSP2_BLBACK_POSEE_STR_PRE_MSK (((1U << DSP2_BLBACK_POSEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_POSEE_STR_PRE_POS) -#define DSP2_BLBACK_POSEE_STR_PRE_UMSK (~(((1U << DSP2_BLBACK_POSEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_POSEE_STR_PRE_POS)) -#define DSP2_BLBACK_NEGEE_STR_PRE DSP2_BLBACK_NEGEE_STR_PRE -#define DSP2_BLBACK_NEGEE_STR_PRE_POS (24U) -#define DSP2_BLBACK_NEGEE_STR_PRE_LEN (7U) -#define DSP2_BLBACK_NEGEE_STR_PRE_MSK (((1U << DSP2_BLBACK_NEGEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_NEGEE_STR_PRE_POS) -#define DSP2_BLBACK_NEGEE_STR_PRE_UMSK (~(((1U << DSP2_BLBACK_NEGEE_STR_PRE_LEN) - 1) << DSP2_BLBACK_NEGEE_STR_PRE_POS)) - -/* 0x36C : BLEE_3 */ -#define DSP2_BLBACK_BLEE_3_OFFSET (0x36C) -#define DSP2_BLBACK_EDGE_THR_PRE DSP2_BLBACK_EDGE_THR_PRE -#define DSP2_BLBACK_EDGE_THR_PRE_POS (0U) -#define DSP2_BLBACK_EDGE_THR_PRE_LEN (16U) -#define DSP2_BLBACK_EDGE_THR_PRE_MSK (((1U << DSP2_BLBACK_EDGE_THR_PRE_LEN) - 1) << DSP2_BLBACK_EDGE_THR_PRE_POS) -#define DSP2_BLBACK_EDGE_THR_PRE_UMSK (~(((1U << DSP2_BLBACK_EDGE_THR_PRE_LEN) - 1) << DSP2_BLBACK_EDGE_THR_PRE_POS)) -#define DSP2_BLBACK_NR_STR_PRE DSP2_BLBACK_NR_STR_PRE -#define DSP2_BLBACK_NR_STR_PRE_POS (16U) -#define DSP2_BLBACK_NR_STR_PRE_LEN (8U) -#define DSP2_BLBACK_NR_STR_PRE_MSK (((1U << DSP2_BLBACK_NR_STR_PRE_LEN) - 1) << DSP2_BLBACK_NR_STR_PRE_POS) -#define DSP2_BLBACK_NR_STR_PRE_UMSK (~(((1U << DSP2_BLBACK_NR_STR_PRE_LEN) - 1) << DSP2_BLBACK_NR_STR_PRE_POS)) - -/* 0x370 : BLEE_4 */ -#define DSP2_BLBACK_BLEE_4_OFFSET (0x370) -#define DSP2_BLBACK_LUMA_WGT0_PRE DSP2_BLBACK_LUMA_WGT0_PRE -#define DSP2_BLBACK_LUMA_WGT0_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT0_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT0_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT0_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT0_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT0_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT0_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT0_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT1_PRE DSP2_BLBACK_LUMA_WGT1_PRE -#define DSP2_BLBACK_LUMA_WGT1_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT1_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT1_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT1_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT1_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT1_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT1_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT1_PRE_POS)) - -/* 0x374 : BLEE_5 */ -#define DSP2_BLBACK_BLEE_5_OFFSET (0x374) -#define DSP2_BLBACK_LUMA_WGT2_PRE DSP2_BLBACK_LUMA_WGT2_PRE -#define DSP2_BLBACK_LUMA_WGT2_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT2_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT2_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT2_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT2_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT2_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT2_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT2_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT3_PRE DSP2_BLBACK_LUMA_WGT3_PRE -#define DSP2_BLBACK_LUMA_WGT3_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT3_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT3_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT3_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT3_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT3_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT3_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT3_PRE_POS)) - -/* 0x378 : BLEE_6 */ -#define DSP2_BLBACK_BLEE_6_OFFSET (0x378) -#define DSP2_BLBACK_LUMA_WGT4_PRE DSP2_BLBACK_LUMA_WGT4_PRE -#define DSP2_BLBACK_LUMA_WGT4_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT4_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT4_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT4_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT4_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT4_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT4_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT4_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT5_PRE DSP2_BLBACK_LUMA_WGT5_PRE -#define DSP2_BLBACK_LUMA_WGT5_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT5_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT5_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT5_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT5_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT5_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT5_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT5_PRE_POS)) - -/* 0x37C : BLEE_7 */ -#define DSP2_BLBACK_BLEE_7_OFFSET (0x37C) -#define DSP2_BLBACK_LUMA_WGT6_PRE DSP2_BLBACK_LUMA_WGT6_PRE -#define DSP2_BLBACK_LUMA_WGT6_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT6_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT6_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT6_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT6_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT6_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT6_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT6_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT7_PRE DSP2_BLBACK_LUMA_WGT7_PRE -#define DSP2_BLBACK_LUMA_WGT7_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT7_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT7_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT7_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT7_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT7_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT7_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT7_PRE_POS)) - -/* 0x380 : BLEE_8 */ -#define DSP2_BLBACK_BLEE_8_OFFSET (0x380) -#define DSP2_BLBACK_LUMA_WGT8_PRE DSP2_BLBACK_LUMA_WGT8_PRE -#define DSP2_BLBACK_LUMA_WGT8_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT8_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT8_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT8_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT8_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT8_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT8_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT8_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT9_PRE DSP2_BLBACK_LUMA_WGT9_PRE -#define DSP2_BLBACK_LUMA_WGT9_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT9_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT9_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT9_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT9_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT9_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT9_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT9_PRE_POS)) - -/* 0x384 : BLEE_9 */ -#define DSP2_BLBACK_BLEE_9_OFFSET (0x384) -#define DSP2_BLBACK_LUMA_WGT10_PRE DSP2_BLBACK_LUMA_WGT10_PRE -#define DSP2_BLBACK_LUMA_WGT10_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT10_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT10_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT10_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT10_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT10_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT10_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT10_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT11_PRE DSP2_BLBACK_LUMA_WGT11_PRE -#define DSP2_BLBACK_LUMA_WGT11_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT11_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT11_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT11_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT11_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT11_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT11_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT11_PRE_POS)) - -/* 0x388 : BLEE_A */ -#define DSP2_BLBACK_BLEE_A_OFFSET (0x388) -#define DSP2_BLBACK_LUMA_WGT12_PRE DSP2_BLBACK_LUMA_WGT12_PRE -#define DSP2_BLBACK_LUMA_WGT12_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT12_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT12_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT12_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT12_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT12_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT12_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT12_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT13_PRE DSP2_BLBACK_LUMA_WGT13_PRE -#define DSP2_BLBACK_LUMA_WGT13_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT13_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT13_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT13_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT13_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT13_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT13_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT13_PRE_POS)) - -/* 0x38C : BLEE_B */ -#define DSP2_BLBACK_BLEE_B_OFFSET (0x38C) -#define DSP2_BLBACK_LUMA_WGT14_PRE DSP2_BLBACK_LUMA_WGT14_PRE -#define DSP2_BLBACK_LUMA_WGT14_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT14_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT14_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT14_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT14_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT14_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT14_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT14_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT15_PRE DSP2_BLBACK_LUMA_WGT15_PRE -#define DSP2_BLBACK_LUMA_WGT15_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT15_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT15_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT15_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT15_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT15_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT15_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT15_PRE_POS)) - -/* 0x390 : BLEE_C */ -#define DSP2_BLBACK_BLEE_C_OFFSET (0x390) -#define DSP2_BLBACK_LUMA_WGT16_PRE DSP2_BLBACK_LUMA_WGT16_PRE -#define DSP2_BLBACK_LUMA_WGT16_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT16_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT16_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT16_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT16_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT16_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT16_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT16_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT17_PRE DSP2_BLBACK_LUMA_WGT17_PRE -#define DSP2_BLBACK_LUMA_WGT17_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT17_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT17_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT17_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT17_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT17_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT17_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT17_PRE_POS)) - -/* 0x394 : BLEE_D */ -#define DSP2_BLBACK_BLEE_D_OFFSET (0x394) -#define DSP2_BLBACK_LUMA_WGT18_PRE DSP2_BLBACK_LUMA_WGT18_PRE -#define DSP2_BLBACK_LUMA_WGT18_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT18_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT18_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT18_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT18_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT18_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT18_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT18_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT19_PRE DSP2_BLBACK_LUMA_WGT19_PRE -#define DSP2_BLBACK_LUMA_WGT19_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT19_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT19_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT19_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT19_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT19_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT19_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT19_PRE_POS)) - -/* 0x398 : BLEE_E */ -#define DSP2_BLBACK_BLEE_E_OFFSET (0x398) -#define DSP2_BLBACK_LUMA_WGT20_PRE DSP2_BLBACK_LUMA_WGT20_PRE -#define DSP2_BLBACK_LUMA_WGT20_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT20_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT20_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT20_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT20_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT20_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT20_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT20_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT21_PRE DSP2_BLBACK_LUMA_WGT21_PRE -#define DSP2_BLBACK_LUMA_WGT21_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT21_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT21_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT21_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT21_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT21_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT21_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT21_PRE_POS)) - -/* 0x39C : BLEE_F */ -#define DSP2_BLBACK_BLEE_F_OFFSET (0x39C) -#define DSP2_BLBACK_LUMA_WGT22_PRE DSP2_BLBACK_LUMA_WGT22_PRE -#define DSP2_BLBACK_LUMA_WGT22_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT22_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT22_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT22_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT22_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT22_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT22_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT22_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT23_PRE DSP2_BLBACK_LUMA_WGT23_PRE -#define DSP2_BLBACK_LUMA_WGT23_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT23_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT23_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT23_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT23_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT23_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT23_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT23_PRE_POS)) - -/* 0x3A0 : BLEE_10 */ -#define DSP2_BLBACK_BLEE_10_OFFSET (0x3A0) -#define DSP2_BLBACK_LUMA_WGT24_PRE DSP2_BLBACK_LUMA_WGT24_PRE -#define DSP2_BLBACK_LUMA_WGT24_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT24_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT24_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT24_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT24_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT24_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT24_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT24_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT25_PRE DSP2_BLBACK_LUMA_WGT25_PRE -#define DSP2_BLBACK_LUMA_WGT25_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT25_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT25_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT25_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT25_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT25_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT25_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT25_PRE_POS)) - -/* 0x3A4 : BLEE_11 */ -#define DSP2_BLBACK_BLEE_11_OFFSET (0x3A4) -#define DSP2_BLBACK_LUMA_WGT26_PRE DSP2_BLBACK_LUMA_WGT26_PRE -#define DSP2_BLBACK_LUMA_WGT26_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT26_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT26_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT26_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT26_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT26_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT26_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT26_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT27_PRE DSP2_BLBACK_LUMA_WGT27_PRE -#define DSP2_BLBACK_LUMA_WGT27_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT27_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT27_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT27_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT27_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT27_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT27_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT27_PRE_POS)) - -/* 0x3A8 : BLEE_12 */ -#define DSP2_BLBACK_BLEE_12_OFFSET (0x3A8) -#define DSP2_BLBACK_LUMA_WGT28_PRE DSP2_BLBACK_LUMA_WGT28_PRE -#define DSP2_BLBACK_LUMA_WGT28_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT28_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT28_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT28_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT28_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT28_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT28_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT28_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT29_PRE DSP2_BLBACK_LUMA_WGT29_PRE -#define DSP2_BLBACK_LUMA_WGT29_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT29_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT29_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT29_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT29_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT29_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT29_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT29_PRE_POS)) - -/* 0x3AC : BLEE_13 */ -#define DSP2_BLBACK_BLEE_13_OFFSET (0x3AC) -#define DSP2_BLBACK_LUMA_WGT30_PRE DSP2_BLBACK_LUMA_WGT30_PRE -#define DSP2_BLBACK_LUMA_WGT30_PRE_POS (0U) -#define DSP2_BLBACK_LUMA_WGT30_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT30_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT30_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT30_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT30_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT30_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT30_PRE_POS)) -#define DSP2_BLBACK_LUMA_WGT31_PRE DSP2_BLBACK_LUMA_WGT31_PRE -#define DSP2_BLBACK_LUMA_WGT31_PRE_POS (16U) -#define DSP2_BLBACK_LUMA_WGT31_PRE_LEN (10U) -#define DSP2_BLBACK_LUMA_WGT31_PRE_MSK (((1U << DSP2_BLBACK_LUMA_WGT31_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT31_PRE_POS) -#define DSP2_BLBACK_LUMA_WGT31_PRE_UMSK (~(((1U << DSP2_BLBACK_LUMA_WGT31_PRE_LEN) - 1) << DSP2_BLBACK_LUMA_WGT31_PRE_POS)) - -/* 0x3B0 : CS1 */ -#define DSP2_BLBACK_CS1_OFFSET (0x3B0) -#define DSP2_BLBACK_CS1_GREY_TH_PRE DSP2_BLBACK_CS1_GREY_TH_PRE -#define DSP2_BLBACK_CS1_GREY_TH_PRE_POS (0U) -#define DSP2_BLBACK_CS1_GREY_TH_PRE_LEN (4U) -#define DSP2_BLBACK_CS1_GREY_TH_PRE_MSK (((1U << DSP2_BLBACK_CS1_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GREY_TH_PRE_POS) -#define DSP2_BLBACK_CS1_GREY_TH_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GREY_TH_PRE_POS)) -#define DSP2_BLBACK_CS1_ENABLE_PRE DSP2_BLBACK_CS1_ENABLE_PRE -#define DSP2_BLBACK_CS1_ENABLE_PRE_POS (4U) -#define DSP2_BLBACK_CS1_ENABLE_PRE_LEN (1U) -#define DSP2_BLBACK_CS1_ENABLE_PRE_MSK (((1U << DSP2_BLBACK_CS1_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS1_ENABLE_PRE_POS) -#define DSP2_BLBACK_CS1_ENABLE_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS1_ENABLE_PRE_POS)) -#define DSP2_BLBACK_CS1_WEIGHT_PRE DSP2_BLBACK_CS1_WEIGHT_PRE -#define DSP2_BLBACK_CS1_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_CS1_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_CS1_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_CS1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS1_WEIGHT_PRE_POS) -#define DSP2_BLBACK_CS1_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS1_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_CS1_GAIN_PRE DSP2_BLBACK_CS1_GAIN_PRE -#define DSP2_BLBACK_CS1_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_CS1_GAIN_PRE_LEN (9U) -#define DSP2_BLBACK_CS1_GAIN_PRE_MSK (((1U << DSP2_BLBACK_CS1_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GAIN_PRE_POS) -#define DSP2_BLBACK_CS1_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_CS1_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS1_GAIN_PRE_POS)) - -/* 0x3B4 : CS2 */ -#define DSP2_BLBACK_CS2_OFFSET (0x3B4) -#define DSP2_BLBACK_CS2_GREY_TH_PRE DSP2_BLBACK_CS2_GREY_TH_PRE -#define DSP2_BLBACK_CS2_GREY_TH_PRE_POS (0U) -#define DSP2_BLBACK_CS2_GREY_TH_PRE_LEN (4U) -#define DSP2_BLBACK_CS2_GREY_TH_PRE_MSK (((1U << DSP2_BLBACK_CS2_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GREY_TH_PRE_POS) -#define DSP2_BLBACK_CS2_GREY_TH_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GREY_TH_PRE_POS)) -#define DSP2_BLBACK_CS2_ENABLE_PRE DSP2_BLBACK_CS2_ENABLE_PRE -#define DSP2_BLBACK_CS2_ENABLE_PRE_POS (4U) -#define DSP2_BLBACK_CS2_ENABLE_PRE_LEN (1U) -#define DSP2_BLBACK_CS2_ENABLE_PRE_MSK (((1U << DSP2_BLBACK_CS2_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS2_ENABLE_PRE_POS) -#define DSP2_BLBACK_CS2_ENABLE_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CS2_ENABLE_PRE_POS)) -#define DSP2_BLBACK_CS2_WEIGHT_PRE DSP2_BLBACK_CS2_WEIGHT_PRE -#define DSP2_BLBACK_CS2_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_CS2_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_CS2_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_CS2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS2_WEIGHT_PRE_POS) -#define DSP2_BLBACK_CS2_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CS2_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_CS2_GAIN_PRE DSP2_BLBACK_CS2_GAIN_PRE -#define DSP2_BLBACK_CS2_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_CS2_GAIN_PRE_LEN (9U) -#define DSP2_BLBACK_CS2_GAIN_PRE_MSK (((1U << DSP2_BLBACK_CS2_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GAIN_PRE_POS) -#define DSP2_BLBACK_CS2_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_CS2_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_CS2_GAIN_PRE_POS)) - -/* 0x3FC : DUMMY_CTRL */ -#define DSP2_BLBACK_DUMMY_CTRL_OFFSET (0x3FC) -#define DSP2_BLBACK_REG_BL444TO422_EN_W DSP2_BLBACK_REG_BL444TO422_EN_W -#define DSP2_BLBACK_REG_BL444TO422_EN_W_POS (0U) -#define DSP2_BLBACK_REG_BL444TO422_EN_W_LEN (1U) -#define DSP2_BLBACK_REG_BL444TO422_EN_W_MSK (((1U << DSP2_BLBACK_REG_BL444TO422_EN_W_LEN) - 1) << DSP2_BLBACK_REG_BL444TO422_EN_W_POS) -#define DSP2_BLBACK_REG_BL444TO422_EN_W_UMSK (~(((1U << DSP2_BLBACK_REG_BL444TO422_EN_W_LEN) - 1) << DSP2_BLBACK_REG_BL444TO422_EN_W_POS)) - -/* 0x900 : WDR_0 */ -#define DSP2_BLBACK_WDR_0_OFFSET (0x900) -#define DSP2_BLBACK_WDR_EN_PRE DSP2_BLBACK_WDR_EN_PRE -#define DSP2_BLBACK_WDR_EN_PRE_POS (0U) -#define DSP2_BLBACK_WDR_EN_PRE_LEN (1U) -#define DSP2_BLBACK_WDR_EN_PRE_MSK (((1U << DSP2_BLBACK_WDR_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_EN_PRE_POS) -#define DSP2_BLBACK_WDR_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_EN_PRE_POS)) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R DSP2_BLBACK_BLWDR_BUF_IDX_R -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_POS (1U) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_LEN (1U) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_MSK (((1U << DSP2_BLBACK_BLWDR_BUF_IDX_R_LEN) - 1) << DSP2_BLBACK_BLWDR_BUF_IDX_R_POS) -#define DSP2_BLBACK_BLWDR_BUF_IDX_R_UMSK (~(((1U << DSP2_BLBACK_BLWDR_BUF_IDX_R_LEN) - 1) << DSP2_BLBACK_BLWDR_BUF_IDX_R_POS)) -#define DSP2_BLBACK_BLWDR_W_CNT_R DSP2_BLBACK_BLWDR_W_CNT_R -#define DSP2_BLBACK_BLWDR_W_CNT_R_POS (4U) -#define DSP2_BLBACK_BLWDR_W_CNT_R_LEN (5U) -#define DSP2_BLBACK_BLWDR_W_CNT_R_MSK (((1U << DSP2_BLBACK_BLWDR_W_CNT_R_LEN) - 1) << DSP2_BLBACK_BLWDR_W_CNT_R_POS) -#define DSP2_BLBACK_BLWDR_W_CNT_R_UMSK (~(((1U << DSP2_BLBACK_BLWDR_W_CNT_R_LEN) - 1) << DSP2_BLBACK_BLWDR_W_CNT_R_POS)) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE DSP2_BLBACK_WDR_CS_GAIN_PRE -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_LEN (13U) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GAIN_PRE_POS) -#define DSP2_BLBACK_WDR_CS_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GAIN_PRE_POS)) - -/* 0x904 : WDR_CS_0 */ -#define DSP2_BLBACK_WDR_CS_0_OFFSET (0x904) -#define DSP2_BLBACK_WDR_CS_EN_PRE DSP2_BLBACK_WDR_CS_EN_PRE -#define DSP2_BLBACK_WDR_CS_EN_PRE_POS (0U) -#define DSP2_BLBACK_WDR_CS_EN_PRE_LEN (1U) -#define DSP2_BLBACK_WDR_CS_EN_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_EN_PRE_POS) -#define DSP2_BLBACK_WDR_CS_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_EN_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_EN_PRE_POS)) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE DSP2_BLBACK_WDR_CS_WEIGHT_PRE -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_POS) -#define DSP2_BLBACK_WDR_CS_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE DSP2_BLBACK_WDR_CS_GREY_TH_PRE -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_POS (16U) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_LEN (8U) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_MSK (((1U << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_POS) -#define DSP2_BLBACK_WDR_CS_GREY_TH_PRE_UMSK (~(((1U << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_LEN) - 1) << DSP2_BLBACK_WDR_CS_GREY_TH_PRE_POS)) - -/* 0x908 : WDR_HIST_1 */ -#define DSP2_BLBACK_WDR_HIST_1_OFFSET (0x908) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE DSP2_BLBACK_HIST_ROI0_EN_PRE -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI0_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI0_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI0_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE DSP2_BLBACK_HIST_ROI1_EN_PRE -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI1_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI1_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI1_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE_POS)) - -/* 0x90C : WDR_HIST_2 */ -#define DSP2_BLBACK_WDR_HIST_2_OFFSET (0x90C) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE DSP2_BLBACK_HIST_ROI2_EN_PRE -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI2_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI2_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI2_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE DSP2_BLBACK_HIST_ROI3_EN_PRE -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI3_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI3_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI3_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE_POS)) - -/* 0x910 : WDR_HIST_3 */ -#define DSP2_BLBACK_WDR_HIST_3_OFFSET (0x910) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE DSP2_BLBACK_HIST_ROI4_EN_PRE -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI4_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI4_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI4_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE DSP2_BLBACK_HIST_ROI5_EN_PRE -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI5_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI5_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI5_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE_POS)) - -/* 0x914 : WDR_HIST_4 */ -#define DSP2_BLBACK_WDR_HIST_4_OFFSET (0x914) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE DSP2_BLBACK_HIST_ROI6_EN_PRE -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_POS (0U) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI6_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI6_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI6_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE DSP2_BLBACK_HIST_ROI7_EN_PRE -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_LEN (1U) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI7_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_EN_PRE_POS) -#define DSP2_BLBACK_HIST_ROI7_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI7_EN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_EN_PRE_POS)) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_POS (24U) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_LEN (4U) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_POS) -#define DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE_POS)) - -/* 0x918 : WDR_HIST_5 */ -#define DSP2_BLBACK_WDR_HIST_5_OFFSET (0x918) -#define DSP2_BLBACK_HIST_X0_MAX_PRE DSP2_BLBACK_HIST_X0_MAX_PRE -#define DSP2_BLBACK_HIST_X0_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X0_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X0_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X0_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X0_MIN_PRE DSP2_BLBACK_HIST_X0_MIN_PRE -#define DSP2_BLBACK_HIST_X0_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X0_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X0_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X0_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X0_MIN_PRE_POS)) - -/* 0x91C : WDR_HIST_6 */ -#define DSP2_BLBACK_WDR_HIST_6_OFFSET (0x91C) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE DSP2_BLBACK_HIST_Y0_MAX_PRE -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y0_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y0_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE DSP2_BLBACK_HIST_Y0_MIN_PRE -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y0_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y0_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y0_MIN_PRE_POS)) - -/* 0x920 : WDR_HIST_7 */ -#define DSP2_BLBACK_WDR_HIST_7_OFFSET (0x920) -#define DSP2_BLBACK_HIST_X1_MAX_PRE DSP2_BLBACK_HIST_X1_MAX_PRE -#define DSP2_BLBACK_HIST_X1_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X1_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X1_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X1_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X1_MIN_PRE DSP2_BLBACK_HIST_X1_MIN_PRE -#define DSP2_BLBACK_HIST_X1_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X1_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X1_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X1_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X1_MIN_PRE_POS)) - -/* 0x924 : WDR_HIST_8 */ -#define DSP2_BLBACK_WDR_HIST_8_OFFSET (0x924) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE DSP2_BLBACK_HIST_Y1_MAX_PRE -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y1_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y1_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE DSP2_BLBACK_HIST_Y1_MIN_PRE -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y1_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y1_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y1_MIN_PRE_POS)) - -/* 0x928 : WDR_HIST_9 */ -#define DSP2_BLBACK_WDR_HIST_9_OFFSET (0x928) -#define DSP2_BLBACK_HIST_X2_MAX_PRE DSP2_BLBACK_HIST_X2_MAX_PRE -#define DSP2_BLBACK_HIST_X2_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X2_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X2_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X2_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X2_MIN_PRE DSP2_BLBACK_HIST_X2_MIN_PRE -#define DSP2_BLBACK_HIST_X2_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X2_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X2_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X2_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X2_MIN_PRE_POS)) - -/* 0x92C : WDR_HIST_10 */ -#define DSP2_BLBACK_WDR_HIST_10_OFFSET (0x92C) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE DSP2_BLBACK_HIST_Y2_MAX_PRE -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y2_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y2_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE DSP2_BLBACK_HIST_Y2_MIN_PRE -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y2_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y2_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y2_MIN_PRE_POS)) - -/* 0x930 : WDR_HIST_11 */ -#define DSP2_BLBACK_WDR_HIST_11_OFFSET (0x930) -#define DSP2_BLBACK_HIST_X3_MAX_PRE DSP2_BLBACK_HIST_X3_MAX_PRE -#define DSP2_BLBACK_HIST_X3_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X3_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X3_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X3_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X3_MIN_PRE DSP2_BLBACK_HIST_X3_MIN_PRE -#define DSP2_BLBACK_HIST_X3_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X3_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X3_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X3_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X3_MIN_PRE_POS)) - -/* 0x934 : WDR_HIST_12 */ -#define DSP2_BLBACK_WDR_HIST_12_OFFSET (0x934) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE DSP2_BLBACK_HIST_Y3_MAX_PRE -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y3_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y3_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE DSP2_BLBACK_HIST_Y3_MIN_PRE -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y3_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y3_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y3_MIN_PRE_POS)) - -/* 0x938 : WDR_HIST_13 */ -#define DSP2_BLBACK_WDR_HIST_13_OFFSET (0x938) -#define DSP2_BLBACK_HIST_X4_MAX_PRE DSP2_BLBACK_HIST_X4_MAX_PRE -#define DSP2_BLBACK_HIST_X4_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X4_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X4_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X4_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X4_MIN_PRE DSP2_BLBACK_HIST_X4_MIN_PRE -#define DSP2_BLBACK_HIST_X4_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X4_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X4_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X4_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X4_MIN_PRE_POS)) - -/* 0x93C : WDR_HIST_14 */ -#define DSP2_BLBACK_WDR_HIST_14_OFFSET (0x93C) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE DSP2_BLBACK_HIST_Y4_MAX_PRE -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y4_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y4_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE DSP2_BLBACK_HIST_Y4_MIN_PRE -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y4_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y4_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y4_MIN_PRE_POS)) - -/* 0x940 : WDR_HIST_15 */ -#define DSP2_BLBACK_WDR_HIST_15_OFFSET (0x940) -#define DSP2_BLBACK_HIST_X5_MAX_PRE DSP2_BLBACK_HIST_X5_MAX_PRE -#define DSP2_BLBACK_HIST_X5_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X5_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X5_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X5_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X5_MIN_PRE DSP2_BLBACK_HIST_X5_MIN_PRE -#define DSP2_BLBACK_HIST_X5_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X5_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X5_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X5_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X5_MIN_PRE_POS)) - -/* 0x944 : WDR_HIST_16 */ -#define DSP2_BLBACK_WDR_HIST_16_OFFSET (0x944) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE DSP2_BLBACK_HIST_Y5_MAX_PRE -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y5_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y5_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE DSP2_BLBACK_HIST_Y5_MIN_PRE -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y5_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y5_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y5_MIN_PRE_POS)) - -/* 0x948 : WDR_HIST_17 */ -#define DSP2_BLBACK_WDR_HIST_17_OFFSET (0x948) -#define DSP2_BLBACK_HIST_X6_MAX_PRE DSP2_BLBACK_HIST_X6_MAX_PRE -#define DSP2_BLBACK_HIST_X6_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X6_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X6_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X6_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X6_MIN_PRE DSP2_BLBACK_HIST_X6_MIN_PRE -#define DSP2_BLBACK_HIST_X6_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X6_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X6_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X6_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X6_MIN_PRE_POS)) - -/* 0x94C : WDR_HIST_18 */ -#define DSP2_BLBACK_WDR_HIST_18_OFFSET (0x94C) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE DSP2_BLBACK_HIST_Y6_MAX_PRE -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y6_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y6_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE DSP2_BLBACK_HIST_Y6_MIN_PRE -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y6_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y6_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y6_MIN_PRE_POS)) - -/* 0x950 : WDR_HIST_19 */ -#define DSP2_BLBACK_WDR_HIST_19_OFFSET (0x950) -#define DSP2_BLBACK_HIST_X7_MAX_PRE DSP2_BLBACK_HIST_X7_MAX_PRE -#define DSP2_BLBACK_HIST_X7_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_X7_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X7_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_X7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_X7_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_X7_MIN_PRE DSP2_BLBACK_HIST_X7_MIN_PRE -#define DSP2_BLBACK_HIST_X7_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_X7_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_X7_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_X7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_X7_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_X7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_X7_MIN_PRE_POS)) - -/* 0x954 : WDR_HIST_20 */ -#define DSP2_BLBACK_WDR_HIST_20_OFFSET (0x954) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE DSP2_BLBACK_HIST_Y7_MAX_PRE -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_POS (0U) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MAX_PRE_POS) -#define DSP2_BLBACK_HIST_Y7_MAX_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y7_MAX_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MAX_PRE_POS)) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE DSP2_BLBACK_HIST_Y7_MIN_PRE -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_POS (16U) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_LEN (11U) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_MSK (((1U << DSP2_BLBACK_HIST_Y7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MIN_PRE_POS) -#define DSP2_BLBACK_HIST_Y7_MIN_PRE_UMSK (~(((1U << DSP2_BLBACK_HIST_Y7_MIN_PRE_LEN) - 1) << DSP2_BLBACK_HIST_Y7_MIN_PRE_POS)) - -/* 0x958 : REG_HIST0_64 */ -#define DSP2_BLBACK_REG_HIST0_64_OFFSET (0x958) -#define DSP2_BLBACK_HIST0_64_R DSP2_BLBACK_HIST0_64_R -#define DSP2_BLBACK_HIST0_64_R_POS (0U) -#define DSP2_BLBACK_HIST0_64_R_LEN (24U) -#define DSP2_BLBACK_HIST0_64_R_MSK (((1U << DSP2_BLBACK_HIST0_64_R_LEN) - 1) << DSP2_BLBACK_HIST0_64_R_POS) -#define DSP2_BLBACK_HIST0_64_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_64_R_LEN) - 1) << DSP2_BLBACK_HIST0_64_R_POS)) - -/* 0x95C : REG_HIST1_64 */ -#define DSP2_BLBACK_REG_HIST1_64_OFFSET (0x95C) -#define DSP2_BLBACK_HIST1_64_R DSP2_BLBACK_HIST1_64_R -#define DSP2_BLBACK_HIST1_64_R_POS (0U) -#define DSP2_BLBACK_HIST1_64_R_LEN (24U) -#define DSP2_BLBACK_HIST1_64_R_MSK (((1U << DSP2_BLBACK_HIST1_64_R_LEN) - 1) << DSP2_BLBACK_HIST1_64_R_POS) -#define DSP2_BLBACK_HIST1_64_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_64_R_LEN) - 1) << DSP2_BLBACK_HIST1_64_R_POS)) - -/* 0xA00 : REG_HIST0_0 */ -#define DSP2_BLBACK_REG_HIST0_0_OFFSET (0xA00) -#define DSP2_BLBACK_HIST0_0_R DSP2_BLBACK_HIST0_0_R -#define DSP2_BLBACK_HIST0_0_R_POS (0U) -#define DSP2_BLBACK_HIST0_0_R_LEN (24U) -#define DSP2_BLBACK_HIST0_0_R_MSK (((1U << DSP2_BLBACK_HIST0_0_R_LEN) - 1) << DSP2_BLBACK_HIST0_0_R_POS) -#define DSP2_BLBACK_HIST0_0_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_0_R_LEN) - 1) << DSP2_BLBACK_HIST0_0_R_POS)) - -/* 0xA04 : REG_HIST0_1 */ -#define DSP2_BLBACK_REG_HIST0_1_OFFSET (0xA04) -#define DSP2_BLBACK_HIST0_1_R DSP2_BLBACK_HIST0_1_R -#define DSP2_BLBACK_HIST0_1_R_POS (0U) -#define DSP2_BLBACK_HIST0_1_R_LEN (24U) -#define DSP2_BLBACK_HIST0_1_R_MSK (((1U << DSP2_BLBACK_HIST0_1_R_LEN) - 1) << DSP2_BLBACK_HIST0_1_R_POS) -#define DSP2_BLBACK_HIST0_1_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_1_R_LEN) - 1) << DSP2_BLBACK_HIST0_1_R_POS)) - -/* 0xA08 : REG_HIST0_2 */ -#define DSP2_BLBACK_REG_HIST0_2_OFFSET (0xA08) -#define DSP2_BLBACK_HIST0_2_R DSP2_BLBACK_HIST0_2_R -#define DSP2_BLBACK_HIST0_2_R_POS (0U) -#define DSP2_BLBACK_HIST0_2_R_LEN (24U) -#define DSP2_BLBACK_HIST0_2_R_MSK (((1U << DSP2_BLBACK_HIST0_2_R_LEN) - 1) << DSP2_BLBACK_HIST0_2_R_POS) -#define DSP2_BLBACK_HIST0_2_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_2_R_LEN) - 1) << DSP2_BLBACK_HIST0_2_R_POS)) - -/* 0xA0C : REG_HIST0_3 */ -#define DSP2_BLBACK_REG_HIST0_3_OFFSET (0xA0C) -#define DSP2_BLBACK_HIST0_3_R DSP2_BLBACK_HIST0_3_R -#define DSP2_BLBACK_HIST0_3_R_POS (0U) -#define DSP2_BLBACK_HIST0_3_R_LEN (24U) -#define DSP2_BLBACK_HIST0_3_R_MSK (((1U << DSP2_BLBACK_HIST0_3_R_LEN) - 1) << DSP2_BLBACK_HIST0_3_R_POS) -#define DSP2_BLBACK_HIST0_3_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_3_R_LEN) - 1) << DSP2_BLBACK_HIST0_3_R_POS)) - -/* 0xA10 : REG_HIST0_4 */ -#define DSP2_BLBACK_REG_HIST0_4_OFFSET (0xA10) -#define DSP2_BLBACK_HIST0_4_R DSP2_BLBACK_HIST0_4_R -#define DSP2_BLBACK_HIST0_4_R_POS (0U) -#define DSP2_BLBACK_HIST0_4_R_LEN (24U) -#define DSP2_BLBACK_HIST0_4_R_MSK (((1U << DSP2_BLBACK_HIST0_4_R_LEN) - 1) << DSP2_BLBACK_HIST0_4_R_POS) -#define DSP2_BLBACK_HIST0_4_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_4_R_LEN) - 1) << DSP2_BLBACK_HIST0_4_R_POS)) - -/* 0xA14 : REG_HIST0_5 */ -#define DSP2_BLBACK_REG_HIST0_5_OFFSET (0xA14) -#define DSP2_BLBACK_HIST0_5_R DSP2_BLBACK_HIST0_5_R -#define DSP2_BLBACK_HIST0_5_R_POS (0U) -#define DSP2_BLBACK_HIST0_5_R_LEN (24U) -#define DSP2_BLBACK_HIST0_5_R_MSK (((1U << DSP2_BLBACK_HIST0_5_R_LEN) - 1) << DSP2_BLBACK_HIST0_5_R_POS) -#define DSP2_BLBACK_HIST0_5_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_5_R_LEN) - 1) << DSP2_BLBACK_HIST0_5_R_POS)) - -/* 0xA18 : REG_HIST0_6 */ -#define DSP2_BLBACK_REG_HIST0_6_OFFSET (0xA18) -#define DSP2_BLBACK_HIST0_6_R DSP2_BLBACK_HIST0_6_R -#define DSP2_BLBACK_HIST0_6_R_POS (0U) -#define DSP2_BLBACK_HIST0_6_R_LEN (24U) -#define DSP2_BLBACK_HIST0_6_R_MSK (((1U << DSP2_BLBACK_HIST0_6_R_LEN) - 1) << DSP2_BLBACK_HIST0_6_R_POS) -#define DSP2_BLBACK_HIST0_6_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_6_R_LEN) - 1) << DSP2_BLBACK_HIST0_6_R_POS)) - -/* 0xA1C : REG_HIST0_7 */ -#define DSP2_BLBACK_REG_HIST0_7_OFFSET (0xA1C) -#define DSP2_BLBACK_HIST0_7_R DSP2_BLBACK_HIST0_7_R -#define DSP2_BLBACK_HIST0_7_R_POS (0U) -#define DSP2_BLBACK_HIST0_7_R_LEN (24U) -#define DSP2_BLBACK_HIST0_7_R_MSK (((1U << DSP2_BLBACK_HIST0_7_R_LEN) - 1) << DSP2_BLBACK_HIST0_7_R_POS) -#define DSP2_BLBACK_HIST0_7_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_7_R_LEN) - 1) << DSP2_BLBACK_HIST0_7_R_POS)) - -/* 0xA20 : REG_HIST0_8 */ -#define DSP2_BLBACK_REG_HIST0_8_OFFSET (0xA20) -#define DSP2_BLBACK_HIST0_8_R DSP2_BLBACK_HIST0_8_R -#define DSP2_BLBACK_HIST0_8_R_POS (0U) -#define DSP2_BLBACK_HIST0_8_R_LEN (24U) -#define DSP2_BLBACK_HIST0_8_R_MSK (((1U << DSP2_BLBACK_HIST0_8_R_LEN) - 1) << DSP2_BLBACK_HIST0_8_R_POS) -#define DSP2_BLBACK_HIST0_8_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_8_R_LEN) - 1) << DSP2_BLBACK_HIST0_8_R_POS)) - -/* 0xA24 : REG_HIST0_9 */ -#define DSP2_BLBACK_REG_HIST0_9_OFFSET (0xA24) -#define DSP2_BLBACK_HIST0_9_R DSP2_BLBACK_HIST0_9_R -#define DSP2_BLBACK_HIST0_9_R_POS (0U) -#define DSP2_BLBACK_HIST0_9_R_LEN (24U) -#define DSP2_BLBACK_HIST0_9_R_MSK (((1U << DSP2_BLBACK_HIST0_9_R_LEN) - 1) << DSP2_BLBACK_HIST0_9_R_POS) -#define DSP2_BLBACK_HIST0_9_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_9_R_LEN) - 1) << DSP2_BLBACK_HIST0_9_R_POS)) - -/* 0xA28 : REG_HIST0_10 */ -#define DSP2_BLBACK_REG_HIST0_10_OFFSET (0xA28) -#define DSP2_BLBACK_HIST0_10_R DSP2_BLBACK_HIST0_10_R -#define DSP2_BLBACK_HIST0_10_R_POS (0U) -#define DSP2_BLBACK_HIST0_10_R_LEN (24U) -#define DSP2_BLBACK_HIST0_10_R_MSK (((1U << DSP2_BLBACK_HIST0_10_R_LEN) - 1) << DSP2_BLBACK_HIST0_10_R_POS) -#define DSP2_BLBACK_HIST0_10_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_10_R_LEN) - 1) << DSP2_BLBACK_HIST0_10_R_POS)) - -/* 0xA2C : REG_HIST0_11 */ -#define DSP2_BLBACK_REG_HIST0_11_OFFSET (0xA2C) -#define DSP2_BLBACK_HIST0_11_R DSP2_BLBACK_HIST0_11_R -#define DSP2_BLBACK_HIST0_11_R_POS (0U) -#define DSP2_BLBACK_HIST0_11_R_LEN (24U) -#define DSP2_BLBACK_HIST0_11_R_MSK (((1U << DSP2_BLBACK_HIST0_11_R_LEN) - 1) << DSP2_BLBACK_HIST0_11_R_POS) -#define DSP2_BLBACK_HIST0_11_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_11_R_LEN) - 1) << DSP2_BLBACK_HIST0_11_R_POS)) - -/* 0xA30 : REG_HIST0_12 */ -#define DSP2_BLBACK_REG_HIST0_12_OFFSET (0xA30) -#define DSP2_BLBACK_HIST0_12_R DSP2_BLBACK_HIST0_12_R -#define DSP2_BLBACK_HIST0_12_R_POS (0U) -#define DSP2_BLBACK_HIST0_12_R_LEN (24U) -#define DSP2_BLBACK_HIST0_12_R_MSK (((1U << DSP2_BLBACK_HIST0_12_R_LEN) - 1) << DSP2_BLBACK_HIST0_12_R_POS) -#define DSP2_BLBACK_HIST0_12_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_12_R_LEN) - 1) << DSP2_BLBACK_HIST0_12_R_POS)) - -/* 0xA34 : REG_HIST0_13 */ -#define DSP2_BLBACK_REG_HIST0_13_OFFSET (0xA34) -#define DSP2_BLBACK_HIST0_13_R DSP2_BLBACK_HIST0_13_R -#define DSP2_BLBACK_HIST0_13_R_POS (0U) -#define DSP2_BLBACK_HIST0_13_R_LEN (24U) -#define DSP2_BLBACK_HIST0_13_R_MSK (((1U << DSP2_BLBACK_HIST0_13_R_LEN) - 1) << DSP2_BLBACK_HIST0_13_R_POS) -#define DSP2_BLBACK_HIST0_13_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_13_R_LEN) - 1) << DSP2_BLBACK_HIST0_13_R_POS)) - -/* 0xA38 : REG_HIST0_14 */ -#define DSP2_BLBACK_REG_HIST0_14_OFFSET (0xA38) -#define DSP2_BLBACK_HIST0_14_R DSP2_BLBACK_HIST0_14_R -#define DSP2_BLBACK_HIST0_14_R_POS (0U) -#define DSP2_BLBACK_HIST0_14_R_LEN (24U) -#define DSP2_BLBACK_HIST0_14_R_MSK (((1U << DSP2_BLBACK_HIST0_14_R_LEN) - 1) << DSP2_BLBACK_HIST0_14_R_POS) -#define DSP2_BLBACK_HIST0_14_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_14_R_LEN) - 1) << DSP2_BLBACK_HIST0_14_R_POS)) - -/* 0xA3C : REG_HIST0_15 */ -#define DSP2_BLBACK_REG_HIST0_15_OFFSET (0xA3C) -#define DSP2_BLBACK_HIST0_15_R DSP2_BLBACK_HIST0_15_R -#define DSP2_BLBACK_HIST0_15_R_POS (0U) -#define DSP2_BLBACK_HIST0_15_R_LEN (24U) -#define DSP2_BLBACK_HIST0_15_R_MSK (((1U << DSP2_BLBACK_HIST0_15_R_LEN) - 1) << DSP2_BLBACK_HIST0_15_R_POS) -#define DSP2_BLBACK_HIST0_15_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_15_R_LEN) - 1) << DSP2_BLBACK_HIST0_15_R_POS)) - -/* 0xA40 : REG_HIST0_16 */ -#define DSP2_BLBACK_REG_HIST0_16_OFFSET (0xA40) -#define DSP2_BLBACK_HIST0_16_R DSP2_BLBACK_HIST0_16_R -#define DSP2_BLBACK_HIST0_16_R_POS (0U) -#define DSP2_BLBACK_HIST0_16_R_LEN (24U) -#define DSP2_BLBACK_HIST0_16_R_MSK (((1U << DSP2_BLBACK_HIST0_16_R_LEN) - 1) << DSP2_BLBACK_HIST0_16_R_POS) -#define DSP2_BLBACK_HIST0_16_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_16_R_LEN) - 1) << DSP2_BLBACK_HIST0_16_R_POS)) - -/* 0xA44 : REG_HIST0_17 */ -#define DSP2_BLBACK_REG_HIST0_17_OFFSET (0xA44) -#define DSP2_BLBACK_HIST0_17_R DSP2_BLBACK_HIST0_17_R -#define DSP2_BLBACK_HIST0_17_R_POS (0U) -#define DSP2_BLBACK_HIST0_17_R_LEN (24U) -#define DSP2_BLBACK_HIST0_17_R_MSK (((1U << DSP2_BLBACK_HIST0_17_R_LEN) - 1) << DSP2_BLBACK_HIST0_17_R_POS) -#define DSP2_BLBACK_HIST0_17_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_17_R_LEN) - 1) << DSP2_BLBACK_HIST0_17_R_POS)) - -/* 0xA48 : REG_HIST0_18 */ -#define DSP2_BLBACK_REG_HIST0_18_OFFSET (0xA48) -#define DSP2_BLBACK_HIST0_18_R DSP2_BLBACK_HIST0_18_R -#define DSP2_BLBACK_HIST0_18_R_POS (0U) -#define DSP2_BLBACK_HIST0_18_R_LEN (24U) -#define DSP2_BLBACK_HIST0_18_R_MSK (((1U << DSP2_BLBACK_HIST0_18_R_LEN) - 1) << DSP2_BLBACK_HIST0_18_R_POS) -#define DSP2_BLBACK_HIST0_18_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_18_R_LEN) - 1) << DSP2_BLBACK_HIST0_18_R_POS)) - -/* 0xA4C : REG_HIST0_19 */ -#define DSP2_BLBACK_REG_HIST0_19_OFFSET (0xA4C) -#define DSP2_BLBACK_HIST0_19_R DSP2_BLBACK_HIST0_19_R -#define DSP2_BLBACK_HIST0_19_R_POS (0U) -#define DSP2_BLBACK_HIST0_19_R_LEN (24U) -#define DSP2_BLBACK_HIST0_19_R_MSK (((1U << DSP2_BLBACK_HIST0_19_R_LEN) - 1) << DSP2_BLBACK_HIST0_19_R_POS) -#define DSP2_BLBACK_HIST0_19_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_19_R_LEN) - 1) << DSP2_BLBACK_HIST0_19_R_POS)) - -/* 0xA50 : REG_HIST0_20 */ -#define DSP2_BLBACK_REG_HIST0_20_OFFSET (0xA50) -#define DSP2_BLBACK_HIST0_20_R DSP2_BLBACK_HIST0_20_R -#define DSP2_BLBACK_HIST0_20_R_POS (0U) -#define DSP2_BLBACK_HIST0_20_R_LEN (24U) -#define DSP2_BLBACK_HIST0_20_R_MSK (((1U << DSP2_BLBACK_HIST0_20_R_LEN) - 1) << DSP2_BLBACK_HIST0_20_R_POS) -#define DSP2_BLBACK_HIST0_20_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_20_R_LEN) - 1) << DSP2_BLBACK_HIST0_20_R_POS)) - -/* 0xA54 : REG_HIST0_21 */ -#define DSP2_BLBACK_REG_HIST0_21_OFFSET (0xA54) -#define DSP2_BLBACK_HIST0_21_R DSP2_BLBACK_HIST0_21_R -#define DSP2_BLBACK_HIST0_21_R_POS (0U) -#define DSP2_BLBACK_HIST0_21_R_LEN (24U) -#define DSP2_BLBACK_HIST0_21_R_MSK (((1U << DSP2_BLBACK_HIST0_21_R_LEN) - 1) << DSP2_BLBACK_HIST0_21_R_POS) -#define DSP2_BLBACK_HIST0_21_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_21_R_LEN) - 1) << DSP2_BLBACK_HIST0_21_R_POS)) - -/* 0xA58 : REG_HIST0_22 */ -#define DSP2_BLBACK_REG_HIST0_22_OFFSET (0xA58) -#define DSP2_BLBACK_HIST0_22_R DSP2_BLBACK_HIST0_22_R -#define DSP2_BLBACK_HIST0_22_R_POS (0U) -#define DSP2_BLBACK_HIST0_22_R_LEN (24U) -#define DSP2_BLBACK_HIST0_22_R_MSK (((1U << DSP2_BLBACK_HIST0_22_R_LEN) - 1) << DSP2_BLBACK_HIST0_22_R_POS) -#define DSP2_BLBACK_HIST0_22_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_22_R_LEN) - 1) << DSP2_BLBACK_HIST0_22_R_POS)) - -/* 0xA5C : REG_HIST0_23 */ -#define DSP2_BLBACK_REG_HIST0_23_OFFSET (0xA5C) -#define DSP2_BLBACK_HIST0_23_R DSP2_BLBACK_HIST0_23_R -#define DSP2_BLBACK_HIST0_23_R_POS (0U) -#define DSP2_BLBACK_HIST0_23_R_LEN (24U) -#define DSP2_BLBACK_HIST0_23_R_MSK (((1U << DSP2_BLBACK_HIST0_23_R_LEN) - 1) << DSP2_BLBACK_HIST0_23_R_POS) -#define DSP2_BLBACK_HIST0_23_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_23_R_LEN) - 1) << DSP2_BLBACK_HIST0_23_R_POS)) - -/* 0xA60 : REG_HIST0_24 */ -#define DSP2_BLBACK_REG_HIST0_24_OFFSET (0xA60) -#define DSP2_BLBACK_HIST0_24_R DSP2_BLBACK_HIST0_24_R -#define DSP2_BLBACK_HIST0_24_R_POS (0U) -#define DSP2_BLBACK_HIST0_24_R_LEN (24U) -#define DSP2_BLBACK_HIST0_24_R_MSK (((1U << DSP2_BLBACK_HIST0_24_R_LEN) - 1) << DSP2_BLBACK_HIST0_24_R_POS) -#define DSP2_BLBACK_HIST0_24_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_24_R_LEN) - 1) << DSP2_BLBACK_HIST0_24_R_POS)) - -/* 0xA64 : REG_HIST0_25 */ -#define DSP2_BLBACK_REG_HIST0_25_OFFSET (0xA64) -#define DSP2_BLBACK_HIST0_25_R DSP2_BLBACK_HIST0_25_R -#define DSP2_BLBACK_HIST0_25_R_POS (0U) -#define DSP2_BLBACK_HIST0_25_R_LEN (24U) -#define DSP2_BLBACK_HIST0_25_R_MSK (((1U << DSP2_BLBACK_HIST0_25_R_LEN) - 1) << DSP2_BLBACK_HIST0_25_R_POS) -#define DSP2_BLBACK_HIST0_25_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_25_R_LEN) - 1) << DSP2_BLBACK_HIST0_25_R_POS)) - -/* 0xA68 : REG_HIST0_26 */ -#define DSP2_BLBACK_REG_HIST0_26_OFFSET (0xA68) -#define DSP2_BLBACK_HIST0_26_R DSP2_BLBACK_HIST0_26_R -#define DSP2_BLBACK_HIST0_26_R_POS (0U) -#define DSP2_BLBACK_HIST0_26_R_LEN (24U) -#define DSP2_BLBACK_HIST0_26_R_MSK (((1U << DSP2_BLBACK_HIST0_26_R_LEN) - 1) << DSP2_BLBACK_HIST0_26_R_POS) -#define DSP2_BLBACK_HIST0_26_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_26_R_LEN) - 1) << DSP2_BLBACK_HIST0_26_R_POS)) - -/* 0xA6C : REG_HIST0_27 */ -#define DSP2_BLBACK_REG_HIST0_27_OFFSET (0xA6C) -#define DSP2_BLBACK_HIST0_27_R DSP2_BLBACK_HIST0_27_R -#define DSP2_BLBACK_HIST0_27_R_POS (0U) -#define DSP2_BLBACK_HIST0_27_R_LEN (24U) -#define DSP2_BLBACK_HIST0_27_R_MSK (((1U << DSP2_BLBACK_HIST0_27_R_LEN) - 1) << DSP2_BLBACK_HIST0_27_R_POS) -#define DSP2_BLBACK_HIST0_27_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_27_R_LEN) - 1) << DSP2_BLBACK_HIST0_27_R_POS)) - -/* 0xA70 : REG_HIST0_28 */ -#define DSP2_BLBACK_REG_HIST0_28_OFFSET (0xA70) -#define DSP2_BLBACK_HIST0_28_R DSP2_BLBACK_HIST0_28_R -#define DSP2_BLBACK_HIST0_28_R_POS (0U) -#define DSP2_BLBACK_HIST0_28_R_LEN (24U) -#define DSP2_BLBACK_HIST0_28_R_MSK (((1U << DSP2_BLBACK_HIST0_28_R_LEN) - 1) << DSP2_BLBACK_HIST0_28_R_POS) -#define DSP2_BLBACK_HIST0_28_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_28_R_LEN) - 1) << DSP2_BLBACK_HIST0_28_R_POS)) - -/* 0xA74 : REG_HIST0_29 */ -#define DSP2_BLBACK_REG_HIST0_29_OFFSET (0xA74) -#define DSP2_BLBACK_HIST0_29_R DSP2_BLBACK_HIST0_29_R -#define DSP2_BLBACK_HIST0_29_R_POS (0U) -#define DSP2_BLBACK_HIST0_29_R_LEN (24U) -#define DSP2_BLBACK_HIST0_29_R_MSK (((1U << DSP2_BLBACK_HIST0_29_R_LEN) - 1) << DSP2_BLBACK_HIST0_29_R_POS) -#define DSP2_BLBACK_HIST0_29_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_29_R_LEN) - 1) << DSP2_BLBACK_HIST0_29_R_POS)) - -/* 0xA78 : REG_HIST0_30 */ -#define DSP2_BLBACK_REG_HIST0_30_OFFSET (0xA78) -#define DSP2_BLBACK_HIST0_30_R DSP2_BLBACK_HIST0_30_R -#define DSP2_BLBACK_HIST0_30_R_POS (0U) -#define DSP2_BLBACK_HIST0_30_R_LEN (24U) -#define DSP2_BLBACK_HIST0_30_R_MSK (((1U << DSP2_BLBACK_HIST0_30_R_LEN) - 1) << DSP2_BLBACK_HIST0_30_R_POS) -#define DSP2_BLBACK_HIST0_30_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_30_R_LEN) - 1) << DSP2_BLBACK_HIST0_30_R_POS)) - -/* 0xA7C : REG_HIST0_31 */ -#define DSP2_BLBACK_REG_HIST0_31_OFFSET (0xA7C) -#define DSP2_BLBACK_HIST0_31_R DSP2_BLBACK_HIST0_31_R -#define DSP2_BLBACK_HIST0_31_R_POS (0U) -#define DSP2_BLBACK_HIST0_31_R_LEN (24U) -#define DSP2_BLBACK_HIST0_31_R_MSK (((1U << DSP2_BLBACK_HIST0_31_R_LEN) - 1) << DSP2_BLBACK_HIST0_31_R_POS) -#define DSP2_BLBACK_HIST0_31_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_31_R_LEN) - 1) << DSP2_BLBACK_HIST0_31_R_POS)) - -/* 0xA80 : REG_HIST0_32 */ -#define DSP2_BLBACK_REG_HIST0_32_OFFSET (0xA80) -#define DSP2_BLBACK_HIST0_32_R DSP2_BLBACK_HIST0_32_R -#define DSP2_BLBACK_HIST0_32_R_POS (0U) -#define DSP2_BLBACK_HIST0_32_R_LEN (24U) -#define DSP2_BLBACK_HIST0_32_R_MSK (((1U << DSP2_BLBACK_HIST0_32_R_LEN) - 1) << DSP2_BLBACK_HIST0_32_R_POS) -#define DSP2_BLBACK_HIST0_32_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_32_R_LEN) - 1) << DSP2_BLBACK_HIST0_32_R_POS)) - -/* 0xA84 : REG_HIST0_33 */ -#define DSP2_BLBACK_REG_HIST0_33_OFFSET (0xA84) -#define DSP2_BLBACK_HIST0_33_R DSP2_BLBACK_HIST0_33_R -#define DSP2_BLBACK_HIST0_33_R_POS (0U) -#define DSP2_BLBACK_HIST0_33_R_LEN (24U) -#define DSP2_BLBACK_HIST0_33_R_MSK (((1U << DSP2_BLBACK_HIST0_33_R_LEN) - 1) << DSP2_BLBACK_HIST0_33_R_POS) -#define DSP2_BLBACK_HIST0_33_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_33_R_LEN) - 1) << DSP2_BLBACK_HIST0_33_R_POS)) - -/* 0xA88 : REG_HIST0_34 */ -#define DSP2_BLBACK_REG_HIST0_34_OFFSET (0xA88) -#define DSP2_BLBACK_HIST0_34_R DSP2_BLBACK_HIST0_34_R -#define DSP2_BLBACK_HIST0_34_R_POS (0U) -#define DSP2_BLBACK_HIST0_34_R_LEN (24U) -#define DSP2_BLBACK_HIST0_34_R_MSK (((1U << DSP2_BLBACK_HIST0_34_R_LEN) - 1) << DSP2_BLBACK_HIST0_34_R_POS) -#define DSP2_BLBACK_HIST0_34_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_34_R_LEN) - 1) << DSP2_BLBACK_HIST0_34_R_POS)) - -/* 0xA8C : REG_HIST0_35 */ -#define DSP2_BLBACK_REG_HIST0_35_OFFSET (0xA8C) -#define DSP2_BLBACK_HIST0_35_R DSP2_BLBACK_HIST0_35_R -#define DSP2_BLBACK_HIST0_35_R_POS (0U) -#define DSP2_BLBACK_HIST0_35_R_LEN (24U) -#define DSP2_BLBACK_HIST0_35_R_MSK (((1U << DSP2_BLBACK_HIST0_35_R_LEN) - 1) << DSP2_BLBACK_HIST0_35_R_POS) -#define DSP2_BLBACK_HIST0_35_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_35_R_LEN) - 1) << DSP2_BLBACK_HIST0_35_R_POS)) - -/* 0xA90 : REG_HIST0_36 */ -#define DSP2_BLBACK_REG_HIST0_36_OFFSET (0xA90) -#define DSP2_BLBACK_HIST0_36_R DSP2_BLBACK_HIST0_36_R -#define DSP2_BLBACK_HIST0_36_R_POS (0U) -#define DSP2_BLBACK_HIST0_36_R_LEN (24U) -#define DSP2_BLBACK_HIST0_36_R_MSK (((1U << DSP2_BLBACK_HIST0_36_R_LEN) - 1) << DSP2_BLBACK_HIST0_36_R_POS) -#define DSP2_BLBACK_HIST0_36_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_36_R_LEN) - 1) << DSP2_BLBACK_HIST0_36_R_POS)) - -/* 0xA94 : REG_HIST0_37 */ -#define DSP2_BLBACK_REG_HIST0_37_OFFSET (0xA94) -#define DSP2_BLBACK_HIST0_37_R DSP2_BLBACK_HIST0_37_R -#define DSP2_BLBACK_HIST0_37_R_POS (0U) -#define DSP2_BLBACK_HIST0_37_R_LEN (24U) -#define DSP2_BLBACK_HIST0_37_R_MSK (((1U << DSP2_BLBACK_HIST0_37_R_LEN) - 1) << DSP2_BLBACK_HIST0_37_R_POS) -#define DSP2_BLBACK_HIST0_37_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_37_R_LEN) - 1) << DSP2_BLBACK_HIST0_37_R_POS)) - -/* 0xA98 : REG_HIST0_38 */ -#define DSP2_BLBACK_REG_HIST0_38_OFFSET (0xA98) -#define DSP2_BLBACK_HIST0_38_R DSP2_BLBACK_HIST0_38_R -#define DSP2_BLBACK_HIST0_38_R_POS (0U) -#define DSP2_BLBACK_HIST0_38_R_LEN (24U) -#define DSP2_BLBACK_HIST0_38_R_MSK (((1U << DSP2_BLBACK_HIST0_38_R_LEN) - 1) << DSP2_BLBACK_HIST0_38_R_POS) -#define DSP2_BLBACK_HIST0_38_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_38_R_LEN) - 1) << DSP2_BLBACK_HIST0_38_R_POS)) - -/* 0xA9C : REG_HIST0_39 */ -#define DSP2_BLBACK_REG_HIST0_39_OFFSET (0xA9C) -#define DSP2_BLBACK_HIST0_39_R DSP2_BLBACK_HIST0_39_R -#define DSP2_BLBACK_HIST0_39_R_POS (0U) -#define DSP2_BLBACK_HIST0_39_R_LEN (24U) -#define DSP2_BLBACK_HIST0_39_R_MSK (((1U << DSP2_BLBACK_HIST0_39_R_LEN) - 1) << DSP2_BLBACK_HIST0_39_R_POS) -#define DSP2_BLBACK_HIST0_39_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_39_R_LEN) - 1) << DSP2_BLBACK_HIST0_39_R_POS)) - -/* 0xAA0 : REG_HIST0_40 */ -#define DSP2_BLBACK_REG_HIST0_40_OFFSET (0xAA0) -#define DSP2_BLBACK_HIST0_40_R DSP2_BLBACK_HIST0_40_R -#define DSP2_BLBACK_HIST0_40_R_POS (0U) -#define DSP2_BLBACK_HIST0_40_R_LEN (24U) -#define DSP2_BLBACK_HIST0_40_R_MSK (((1U << DSP2_BLBACK_HIST0_40_R_LEN) - 1) << DSP2_BLBACK_HIST0_40_R_POS) -#define DSP2_BLBACK_HIST0_40_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_40_R_LEN) - 1) << DSP2_BLBACK_HIST0_40_R_POS)) - -/* 0xAA4 : REG_HIST0_41 */ -#define DSP2_BLBACK_REG_HIST0_41_OFFSET (0xAA4) -#define DSP2_BLBACK_HIST0_41_R DSP2_BLBACK_HIST0_41_R -#define DSP2_BLBACK_HIST0_41_R_POS (0U) -#define DSP2_BLBACK_HIST0_41_R_LEN (24U) -#define DSP2_BLBACK_HIST0_41_R_MSK (((1U << DSP2_BLBACK_HIST0_41_R_LEN) - 1) << DSP2_BLBACK_HIST0_41_R_POS) -#define DSP2_BLBACK_HIST0_41_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_41_R_LEN) - 1) << DSP2_BLBACK_HIST0_41_R_POS)) - -/* 0xAA8 : REG_HIST0_42 */ -#define DSP2_BLBACK_REG_HIST0_42_OFFSET (0xAA8) -#define DSP2_BLBACK_HIST0_42_R DSP2_BLBACK_HIST0_42_R -#define DSP2_BLBACK_HIST0_42_R_POS (0U) -#define DSP2_BLBACK_HIST0_42_R_LEN (24U) -#define DSP2_BLBACK_HIST0_42_R_MSK (((1U << DSP2_BLBACK_HIST0_42_R_LEN) - 1) << DSP2_BLBACK_HIST0_42_R_POS) -#define DSP2_BLBACK_HIST0_42_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_42_R_LEN) - 1) << DSP2_BLBACK_HIST0_42_R_POS)) - -/* 0xAAC : REG_HIST0_43 */ -#define DSP2_BLBACK_REG_HIST0_43_OFFSET (0xAAC) -#define DSP2_BLBACK_HIST0_43_R DSP2_BLBACK_HIST0_43_R -#define DSP2_BLBACK_HIST0_43_R_POS (0U) -#define DSP2_BLBACK_HIST0_43_R_LEN (24U) -#define DSP2_BLBACK_HIST0_43_R_MSK (((1U << DSP2_BLBACK_HIST0_43_R_LEN) - 1) << DSP2_BLBACK_HIST0_43_R_POS) -#define DSP2_BLBACK_HIST0_43_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_43_R_LEN) - 1) << DSP2_BLBACK_HIST0_43_R_POS)) - -/* 0xAB0 : REG_HIST0_44 */ -#define DSP2_BLBACK_REG_HIST0_44_OFFSET (0xAB0) -#define DSP2_BLBACK_HIST0_44_R DSP2_BLBACK_HIST0_44_R -#define DSP2_BLBACK_HIST0_44_R_POS (0U) -#define DSP2_BLBACK_HIST0_44_R_LEN (24U) -#define DSP2_BLBACK_HIST0_44_R_MSK (((1U << DSP2_BLBACK_HIST0_44_R_LEN) - 1) << DSP2_BLBACK_HIST0_44_R_POS) -#define DSP2_BLBACK_HIST0_44_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_44_R_LEN) - 1) << DSP2_BLBACK_HIST0_44_R_POS)) - -/* 0xAB4 : REG_HIST0_45 */ -#define DSP2_BLBACK_REG_HIST0_45_OFFSET (0xAB4) -#define DSP2_BLBACK_HIST0_45_R DSP2_BLBACK_HIST0_45_R -#define DSP2_BLBACK_HIST0_45_R_POS (0U) -#define DSP2_BLBACK_HIST0_45_R_LEN (24U) -#define DSP2_BLBACK_HIST0_45_R_MSK (((1U << DSP2_BLBACK_HIST0_45_R_LEN) - 1) << DSP2_BLBACK_HIST0_45_R_POS) -#define DSP2_BLBACK_HIST0_45_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_45_R_LEN) - 1) << DSP2_BLBACK_HIST0_45_R_POS)) - -/* 0xAB8 : REG_HIST0_46 */ -#define DSP2_BLBACK_REG_HIST0_46_OFFSET (0xAB8) -#define DSP2_BLBACK_HIST0_46_R DSP2_BLBACK_HIST0_46_R -#define DSP2_BLBACK_HIST0_46_R_POS (0U) -#define DSP2_BLBACK_HIST0_46_R_LEN (24U) -#define DSP2_BLBACK_HIST0_46_R_MSK (((1U << DSP2_BLBACK_HIST0_46_R_LEN) - 1) << DSP2_BLBACK_HIST0_46_R_POS) -#define DSP2_BLBACK_HIST0_46_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_46_R_LEN) - 1) << DSP2_BLBACK_HIST0_46_R_POS)) - -/* 0xABC : REG_HIST0_47 */ -#define DSP2_BLBACK_REG_HIST0_47_OFFSET (0xABC) -#define DSP2_BLBACK_HIST0_47_R DSP2_BLBACK_HIST0_47_R -#define DSP2_BLBACK_HIST0_47_R_POS (0U) -#define DSP2_BLBACK_HIST0_47_R_LEN (24U) -#define DSP2_BLBACK_HIST0_47_R_MSK (((1U << DSP2_BLBACK_HIST0_47_R_LEN) - 1) << DSP2_BLBACK_HIST0_47_R_POS) -#define DSP2_BLBACK_HIST0_47_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_47_R_LEN) - 1) << DSP2_BLBACK_HIST0_47_R_POS)) - -/* 0xAC0 : REG_HIST0_48 */ -#define DSP2_BLBACK_REG_HIST0_48_OFFSET (0xAC0) -#define DSP2_BLBACK_HIST0_48_R DSP2_BLBACK_HIST0_48_R -#define DSP2_BLBACK_HIST0_48_R_POS (0U) -#define DSP2_BLBACK_HIST0_48_R_LEN (24U) -#define DSP2_BLBACK_HIST0_48_R_MSK (((1U << DSP2_BLBACK_HIST0_48_R_LEN) - 1) << DSP2_BLBACK_HIST0_48_R_POS) -#define DSP2_BLBACK_HIST0_48_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_48_R_LEN) - 1) << DSP2_BLBACK_HIST0_48_R_POS)) - -/* 0xAC4 : REG_HIST0_49 */ -#define DSP2_BLBACK_REG_HIST0_49_OFFSET (0xAC4) -#define DSP2_BLBACK_HIST0_49_R DSP2_BLBACK_HIST0_49_R -#define DSP2_BLBACK_HIST0_49_R_POS (0U) -#define DSP2_BLBACK_HIST0_49_R_LEN (24U) -#define DSP2_BLBACK_HIST0_49_R_MSK (((1U << DSP2_BLBACK_HIST0_49_R_LEN) - 1) << DSP2_BLBACK_HIST0_49_R_POS) -#define DSP2_BLBACK_HIST0_49_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_49_R_LEN) - 1) << DSP2_BLBACK_HIST0_49_R_POS)) - -/* 0xAC8 : REG_HIST0_50 */ -#define DSP2_BLBACK_REG_HIST0_50_OFFSET (0xAC8) -#define DSP2_BLBACK_HIST0_50_R DSP2_BLBACK_HIST0_50_R -#define DSP2_BLBACK_HIST0_50_R_POS (0U) -#define DSP2_BLBACK_HIST0_50_R_LEN (24U) -#define DSP2_BLBACK_HIST0_50_R_MSK (((1U << DSP2_BLBACK_HIST0_50_R_LEN) - 1) << DSP2_BLBACK_HIST0_50_R_POS) -#define DSP2_BLBACK_HIST0_50_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_50_R_LEN) - 1) << DSP2_BLBACK_HIST0_50_R_POS)) - -/* 0xACC : REG_HIST0_51 */ -#define DSP2_BLBACK_REG_HIST0_51_OFFSET (0xACC) -#define DSP2_BLBACK_HIST0_51_R DSP2_BLBACK_HIST0_51_R -#define DSP2_BLBACK_HIST0_51_R_POS (0U) -#define DSP2_BLBACK_HIST0_51_R_LEN (24U) -#define DSP2_BLBACK_HIST0_51_R_MSK (((1U << DSP2_BLBACK_HIST0_51_R_LEN) - 1) << DSP2_BLBACK_HIST0_51_R_POS) -#define DSP2_BLBACK_HIST0_51_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_51_R_LEN) - 1) << DSP2_BLBACK_HIST0_51_R_POS)) - -/* 0xAD0 : REG_HIST0_52 */ -#define DSP2_BLBACK_REG_HIST0_52_OFFSET (0xAD0) -#define DSP2_BLBACK_HIST0_52_R DSP2_BLBACK_HIST0_52_R -#define DSP2_BLBACK_HIST0_52_R_POS (0U) -#define DSP2_BLBACK_HIST0_52_R_LEN (24U) -#define DSP2_BLBACK_HIST0_52_R_MSK (((1U << DSP2_BLBACK_HIST0_52_R_LEN) - 1) << DSP2_BLBACK_HIST0_52_R_POS) -#define DSP2_BLBACK_HIST0_52_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_52_R_LEN) - 1) << DSP2_BLBACK_HIST0_52_R_POS)) - -/* 0xAD4 : REG_HIST0_53 */ -#define DSP2_BLBACK_REG_HIST0_53_OFFSET (0xAD4) -#define DSP2_BLBACK_HIST0_53_R DSP2_BLBACK_HIST0_53_R -#define DSP2_BLBACK_HIST0_53_R_POS (0U) -#define DSP2_BLBACK_HIST0_53_R_LEN (24U) -#define DSP2_BLBACK_HIST0_53_R_MSK (((1U << DSP2_BLBACK_HIST0_53_R_LEN) - 1) << DSP2_BLBACK_HIST0_53_R_POS) -#define DSP2_BLBACK_HIST0_53_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_53_R_LEN) - 1) << DSP2_BLBACK_HIST0_53_R_POS)) - -/* 0xAD8 : REG_HIST0_54 */ -#define DSP2_BLBACK_REG_HIST0_54_OFFSET (0xAD8) -#define DSP2_BLBACK_HIST0_54_R DSP2_BLBACK_HIST0_54_R -#define DSP2_BLBACK_HIST0_54_R_POS (0U) -#define DSP2_BLBACK_HIST0_54_R_LEN (24U) -#define DSP2_BLBACK_HIST0_54_R_MSK (((1U << DSP2_BLBACK_HIST0_54_R_LEN) - 1) << DSP2_BLBACK_HIST0_54_R_POS) -#define DSP2_BLBACK_HIST0_54_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_54_R_LEN) - 1) << DSP2_BLBACK_HIST0_54_R_POS)) - -/* 0xADC : REG_HIST0_55 */ -#define DSP2_BLBACK_REG_HIST0_55_OFFSET (0xADC) -#define DSP2_BLBACK_HIST0_55_R DSP2_BLBACK_HIST0_55_R -#define DSP2_BLBACK_HIST0_55_R_POS (0U) -#define DSP2_BLBACK_HIST0_55_R_LEN (24U) -#define DSP2_BLBACK_HIST0_55_R_MSK (((1U << DSP2_BLBACK_HIST0_55_R_LEN) - 1) << DSP2_BLBACK_HIST0_55_R_POS) -#define DSP2_BLBACK_HIST0_55_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_55_R_LEN) - 1) << DSP2_BLBACK_HIST0_55_R_POS)) - -/* 0xAE0 : REG_HIST0_56 */ -#define DSP2_BLBACK_REG_HIST0_56_OFFSET (0xAE0) -#define DSP2_BLBACK_HIST0_56_R DSP2_BLBACK_HIST0_56_R -#define DSP2_BLBACK_HIST0_56_R_POS (0U) -#define DSP2_BLBACK_HIST0_56_R_LEN (24U) -#define DSP2_BLBACK_HIST0_56_R_MSK (((1U << DSP2_BLBACK_HIST0_56_R_LEN) - 1) << DSP2_BLBACK_HIST0_56_R_POS) -#define DSP2_BLBACK_HIST0_56_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_56_R_LEN) - 1) << DSP2_BLBACK_HIST0_56_R_POS)) - -/* 0xAE4 : REG_HIST0_57 */ -#define DSP2_BLBACK_REG_HIST0_57_OFFSET (0xAE4) -#define DSP2_BLBACK_HIST0_57_R DSP2_BLBACK_HIST0_57_R -#define DSP2_BLBACK_HIST0_57_R_POS (0U) -#define DSP2_BLBACK_HIST0_57_R_LEN (24U) -#define DSP2_BLBACK_HIST0_57_R_MSK (((1U << DSP2_BLBACK_HIST0_57_R_LEN) - 1) << DSP2_BLBACK_HIST0_57_R_POS) -#define DSP2_BLBACK_HIST0_57_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_57_R_LEN) - 1) << DSP2_BLBACK_HIST0_57_R_POS)) - -/* 0xAE8 : REG_HIST0_58 */ -#define DSP2_BLBACK_REG_HIST0_58_OFFSET (0xAE8) -#define DSP2_BLBACK_HIST0_58_R DSP2_BLBACK_HIST0_58_R -#define DSP2_BLBACK_HIST0_58_R_POS (0U) -#define DSP2_BLBACK_HIST0_58_R_LEN (24U) -#define DSP2_BLBACK_HIST0_58_R_MSK (((1U << DSP2_BLBACK_HIST0_58_R_LEN) - 1) << DSP2_BLBACK_HIST0_58_R_POS) -#define DSP2_BLBACK_HIST0_58_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_58_R_LEN) - 1) << DSP2_BLBACK_HIST0_58_R_POS)) - -/* 0xAEC : REG_HIST0_59 */ -#define DSP2_BLBACK_REG_HIST0_59_OFFSET (0xAEC) -#define DSP2_BLBACK_HIST0_59_R DSP2_BLBACK_HIST0_59_R -#define DSP2_BLBACK_HIST0_59_R_POS (0U) -#define DSP2_BLBACK_HIST0_59_R_LEN (24U) -#define DSP2_BLBACK_HIST0_59_R_MSK (((1U << DSP2_BLBACK_HIST0_59_R_LEN) - 1) << DSP2_BLBACK_HIST0_59_R_POS) -#define DSP2_BLBACK_HIST0_59_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_59_R_LEN) - 1) << DSP2_BLBACK_HIST0_59_R_POS)) - -/* 0xAF0 : REG_HIST0_60 */ -#define DSP2_BLBACK_REG_HIST0_60_OFFSET (0xAF0) -#define DSP2_BLBACK_HIST0_60_R DSP2_BLBACK_HIST0_60_R -#define DSP2_BLBACK_HIST0_60_R_POS (0U) -#define DSP2_BLBACK_HIST0_60_R_LEN (24U) -#define DSP2_BLBACK_HIST0_60_R_MSK (((1U << DSP2_BLBACK_HIST0_60_R_LEN) - 1) << DSP2_BLBACK_HIST0_60_R_POS) -#define DSP2_BLBACK_HIST0_60_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_60_R_LEN) - 1) << DSP2_BLBACK_HIST0_60_R_POS)) - -/* 0xAF4 : REG_HIST0_61 */ -#define DSP2_BLBACK_REG_HIST0_61_OFFSET (0xAF4) -#define DSP2_BLBACK_HIST0_61_R DSP2_BLBACK_HIST0_61_R -#define DSP2_BLBACK_HIST0_61_R_POS (0U) -#define DSP2_BLBACK_HIST0_61_R_LEN (24U) -#define DSP2_BLBACK_HIST0_61_R_MSK (((1U << DSP2_BLBACK_HIST0_61_R_LEN) - 1) << DSP2_BLBACK_HIST0_61_R_POS) -#define DSP2_BLBACK_HIST0_61_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_61_R_LEN) - 1) << DSP2_BLBACK_HIST0_61_R_POS)) - -/* 0xAF8 : REG_HIST0_62 */ -#define DSP2_BLBACK_REG_HIST0_62_OFFSET (0xAF8) -#define DSP2_BLBACK_HIST0_62_R DSP2_BLBACK_HIST0_62_R -#define DSP2_BLBACK_HIST0_62_R_POS (0U) -#define DSP2_BLBACK_HIST0_62_R_LEN (24U) -#define DSP2_BLBACK_HIST0_62_R_MSK (((1U << DSP2_BLBACK_HIST0_62_R_LEN) - 1) << DSP2_BLBACK_HIST0_62_R_POS) -#define DSP2_BLBACK_HIST0_62_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_62_R_LEN) - 1) << DSP2_BLBACK_HIST0_62_R_POS)) - -/* 0xAFC : REG_HIST0_63 */ -#define DSP2_BLBACK_REG_HIST0_63_OFFSET (0xAFC) -#define DSP2_BLBACK_HIST0_63_R DSP2_BLBACK_HIST0_63_R -#define DSP2_BLBACK_HIST0_63_R_POS (0U) -#define DSP2_BLBACK_HIST0_63_R_LEN (24U) -#define DSP2_BLBACK_HIST0_63_R_MSK (((1U << DSP2_BLBACK_HIST0_63_R_LEN) - 1) << DSP2_BLBACK_HIST0_63_R_POS) -#define DSP2_BLBACK_HIST0_63_R_UMSK (~(((1U << DSP2_BLBACK_HIST0_63_R_LEN) - 1) << DSP2_BLBACK_HIST0_63_R_POS)) - -/* 0xB00 : REG_HIST1_0 */ -#define DSP2_BLBACK_REG_HIST1_0_OFFSET (0xB00) -#define DSP2_BLBACK_HIST1_0_R DSP2_BLBACK_HIST1_0_R -#define DSP2_BLBACK_HIST1_0_R_POS (0U) -#define DSP2_BLBACK_HIST1_0_R_LEN (24U) -#define DSP2_BLBACK_HIST1_0_R_MSK (((1U << DSP2_BLBACK_HIST1_0_R_LEN) - 1) << DSP2_BLBACK_HIST1_0_R_POS) -#define DSP2_BLBACK_HIST1_0_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_0_R_LEN) - 1) << DSP2_BLBACK_HIST1_0_R_POS)) - -/* 0xB04 : REG_HIST1_1 */ -#define DSP2_BLBACK_REG_HIST1_1_OFFSET (0xB04) -#define DSP2_BLBACK_HIST1_1_R DSP2_BLBACK_HIST1_1_R -#define DSP2_BLBACK_HIST1_1_R_POS (0U) -#define DSP2_BLBACK_HIST1_1_R_LEN (24U) -#define DSP2_BLBACK_HIST1_1_R_MSK (((1U << DSP2_BLBACK_HIST1_1_R_LEN) - 1) << DSP2_BLBACK_HIST1_1_R_POS) -#define DSP2_BLBACK_HIST1_1_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_1_R_LEN) - 1) << DSP2_BLBACK_HIST1_1_R_POS)) - -/* 0xB08 : REG_HIST1_2 */ -#define DSP2_BLBACK_REG_HIST1_2_OFFSET (0xB08) -#define DSP2_BLBACK_HIST1_2_R DSP2_BLBACK_HIST1_2_R -#define DSP2_BLBACK_HIST1_2_R_POS (0U) -#define DSP2_BLBACK_HIST1_2_R_LEN (24U) -#define DSP2_BLBACK_HIST1_2_R_MSK (((1U << DSP2_BLBACK_HIST1_2_R_LEN) - 1) << DSP2_BLBACK_HIST1_2_R_POS) -#define DSP2_BLBACK_HIST1_2_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_2_R_LEN) - 1) << DSP2_BLBACK_HIST1_2_R_POS)) - -/* 0xB0C : REG_HIST1_3 */ -#define DSP2_BLBACK_REG_HIST1_3_OFFSET (0xB0C) -#define DSP2_BLBACK_HIST1_3_R DSP2_BLBACK_HIST1_3_R -#define DSP2_BLBACK_HIST1_3_R_POS (0U) -#define DSP2_BLBACK_HIST1_3_R_LEN (24U) -#define DSP2_BLBACK_HIST1_3_R_MSK (((1U << DSP2_BLBACK_HIST1_3_R_LEN) - 1) << DSP2_BLBACK_HIST1_3_R_POS) -#define DSP2_BLBACK_HIST1_3_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_3_R_LEN) - 1) << DSP2_BLBACK_HIST1_3_R_POS)) - -/* 0xB10 : REG_HIST1_4 */ -#define DSP2_BLBACK_REG_HIST1_4_OFFSET (0xB10) -#define DSP2_BLBACK_HIST1_4_R DSP2_BLBACK_HIST1_4_R -#define DSP2_BLBACK_HIST1_4_R_POS (0U) -#define DSP2_BLBACK_HIST1_4_R_LEN (24U) -#define DSP2_BLBACK_HIST1_4_R_MSK (((1U << DSP2_BLBACK_HIST1_4_R_LEN) - 1) << DSP2_BLBACK_HIST1_4_R_POS) -#define DSP2_BLBACK_HIST1_4_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_4_R_LEN) - 1) << DSP2_BLBACK_HIST1_4_R_POS)) - -/* 0xB14 : REG_HIST1_5 */ -#define DSP2_BLBACK_REG_HIST1_5_OFFSET (0xB14) -#define DSP2_BLBACK_HIST1_5_R DSP2_BLBACK_HIST1_5_R -#define DSP2_BLBACK_HIST1_5_R_POS (0U) -#define DSP2_BLBACK_HIST1_5_R_LEN (24U) -#define DSP2_BLBACK_HIST1_5_R_MSK (((1U << DSP2_BLBACK_HIST1_5_R_LEN) - 1) << DSP2_BLBACK_HIST1_5_R_POS) -#define DSP2_BLBACK_HIST1_5_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_5_R_LEN) - 1) << DSP2_BLBACK_HIST1_5_R_POS)) - -/* 0xB18 : REG_HIST1_6 */ -#define DSP2_BLBACK_REG_HIST1_6_OFFSET (0xB18) -#define DSP2_BLBACK_HIST1_6_R DSP2_BLBACK_HIST1_6_R -#define DSP2_BLBACK_HIST1_6_R_POS (0U) -#define DSP2_BLBACK_HIST1_6_R_LEN (24U) -#define DSP2_BLBACK_HIST1_6_R_MSK (((1U << DSP2_BLBACK_HIST1_6_R_LEN) - 1) << DSP2_BLBACK_HIST1_6_R_POS) -#define DSP2_BLBACK_HIST1_6_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_6_R_LEN) - 1) << DSP2_BLBACK_HIST1_6_R_POS)) - -/* 0xB1C : REG_HIST1_7 */ -#define DSP2_BLBACK_REG_HIST1_7_OFFSET (0xB1C) -#define DSP2_BLBACK_HIST1_7_R DSP2_BLBACK_HIST1_7_R -#define DSP2_BLBACK_HIST1_7_R_POS (0U) -#define DSP2_BLBACK_HIST1_7_R_LEN (24U) -#define DSP2_BLBACK_HIST1_7_R_MSK (((1U << DSP2_BLBACK_HIST1_7_R_LEN) - 1) << DSP2_BLBACK_HIST1_7_R_POS) -#define DSP2_BLBACK_HIST1_7_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_7_R_LEN) - 1) << DSP2_BLBACK_HIST1_7_R_POS)) - -/* 0xB20 : REG_HIST1_8 */ -#define DSP2_BLBACK_REG_HIST1_8_OFFSET (0xB20) -#define DSP2_BLBACK_HIST1_8_R DSP2_BLBACK_HIST1_8_R -#define DSP2_BLBACK_HIST1_8_R_POS (0U) -#define DSP2_BLBACK_HIST1_8_R_LEN (24U) -#define DSP2_BLBACK_HIST1_8_R_MSK (((1U << DSP2_BLBACK_HIST1_8_R_LEN) - 1) << DSP2_BLBACK_HIST1_8_R_POS) -#define DSP2_BLBACK_HIST1_8_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_8_R_LEN) - 1) << DSP2_BLBACK_HIST1_8_R_POS)) - -/* 0xB24 : REG_HIST1_9 */ -#define DSP2_BLBACK_REG_HIST1_9_OFFSET (0xB24) -#define DSP2_BLBACK_HIST1_9_R DSP2_BLBACK_HIST1_9_R -#define DSP2_BLBACK_HIST1_9_R_POS (0U) -#define DSP2_BLBACK_HIST1_9_R_LEN (24U) -#define DSP2_BLBACK_HIST1_9_R_MSK (((1U << DSP2_BLBACK_HIST1_9_R_LEN) - 1) << DSP2_BLBACK_HIST1_9_R_POS) -#define DSP2_BLBACK_HIST1_9_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_9_R_LEN) - 1) << DSP2_BLBACK_HIST1_9_R_POS)) - -/* 0xB28 : REG_HIST1_10 */ -#define DSP2_BLBACK_REG_HIST1_10_OFFSET (0xB28) -#define DSP2_BLBACK_HIST1_10_R DSP2_BLBACK_HIST1_10_R -#define DSP2_BLBACK_HIST1_10_R_POS (0U) -#define DSP2_BLBACK_HIST1_10_R_LEN (24U) -#define DSP2_BLBACK_HIST1_10_R_MSK (((1U << DSP2_BLBACK_HIST1_10_R_LEN) - 1) << DSP2_BLBACK_HIST1_10_R_POS) -#define DSP2_BLBACK_HIST1_10_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_10_R_LEN) - 1) << DSP2_BLBACK_HIST1_10_R_POS)) - -/* 0xB2C : REG_HIST1_11 */ -#define DSP2_BLBACK_REG_HIST1_11_OFFSET (0xB2C) -#define DSP2_BLBACK_HIST1_11_R DSP2_BLBACK_HIST1_11_R -#define DSP2_BLBACK_HIST1_11_R_POS (0U) -#define DSP2_BLBACK_HIST1_11_R_LEN (24U) -#define DSP2_BLBACK_HIST1_11_R_MSK (((1U << DSP2_BLBACK_HIST1_11_R_LEN) - 1) << DSP2_BLBACK_HIST1_11_R_POS) -#define DSP2_BLBACK_HIST1_11_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_11_R_LEN) - 1) << DSP2_BLBACK_HIST1_11_R_POS)) - -/* 0xB30 : REG_HIST1_12 */ -#define DSP2_BLBACK_REG_HIST1_12_OFFSET (0xB30) -#define DSP2_BLBACK_HIST1_12_R DSP2_BLBACK_HIST1_12_R -#define DSP2_BLBACK_HIST1_12_R_POS (0U) -#define DSP2_BLBACK_HIST1_12_R_LEN (24U) -#define DSP2_BLBACK_HIST1_12_R_MSK (((1U << DSP2_BLBACK_HIST1_12_R_LEN) - 1) << DSP2_BLBACK_HIST1_12_R_POS) -#define DSP2_BLBACK_HIST1_12_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_12_R_LEN) - 1) << DSP2_BLBACK_HIST1_12_R_POS)) - -/* 0xB34 : REG_HIST1_13 */ -#define DSP2_BLBACK_REG_HIST1_13_OFFSET (0xB34) -#define DSP2_BLBACK_HIST1_13_R DSP2_BLBACK_HIST1_13_R -#define DSP2_BLBACK_HIST1_13_R_POS (0U) -#define DSP2_BLBACK_HIST1_13_R_LEN (24U) -#define DSP2_BLBACK_HIST1_13_R_MSK (((1U << DSP2_BLBACK_HIST1_13_R_LEN) - 1) << DSP2_BLBACK_HIST1_13_R_POS) -#define DSP2_BLBACK_HIST1_13_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_13_R_LEN) - 1) << DSP2_BLBACK_HIST1_13_R_POS)) - -/* 0xB38 : REG_HIST1_14 */ -#define DSP2_BLBACK_REG_HIST1_14_OFFSET (0xB38) -#define DSP2_BLBACK_HIST1_14_R DSP2_BLBACK_HIST1_14_R -#define DSP2_BLBACK_HIST1_14_R_POS (0U) -#define DSP2_BLBACK_HIST1_14_R_LEN (24U) -#define DSP2_BLBACK_HIST1_14_R_MSK (((1U << DSP2_BLBACK_HIST1_14_R_LEN) - 1) << DSP2_BLBACK_HIST1_14_R_POS) -#define DSP2_BLBACK_HIST1_14_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_14_R_LEN) - 1) << DSP2_BLBACK_HIST1_14_R_POS)) - -/* 0xB3C : REG_HIST1_15 */ -#define DSP2_BLBACK_REG_HIST1_15_OFFSET (0xB3C) -#define DSP2_BLBACK_HIST1_15_R DSP2_BLBACK_HIST1_15_R -#define DSP2_BLBACK_HIST1_15_R_POS (0U) -#define DSP2_BLBACK_HIST1_15_R_LEN (24U) -#define DSP2_BLBACK_HIST1_15_R_MSK (((1U << DSP2_BLBACK_HIST1_15_R_LEN) - 1) << DSP2_BLBACK_HIST1_15_R_POS) -#define DSP2_BLBACK_HIST1_15_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_15_R_LEN) - 1) << DSP2_BLBACK_HIST1_15_R_POS)) - -/* 0xB40 : REG_HIST1_16 */ -#define DSP2_BLBACK_REG_HIST1_16_OFFSET (0xB40) -#define DSP2_BLBACK_HIST1_16_R DSP2_BLBACK_HIST1_16_R -#define DSP2_BLBACK_HIST1_16_R_POS (0U) -#define DSP2_BLBACK_HIST1_16_R_LEN (24U) -#define DSP2_BLBACK_HIST1_16_R_MSK (((1U << DSP2_BLBACK_HIST1_16_R_LEN) - 1) << DSP2_BLBACK_HIST1_16_R_POS) -#define DSP2_BLBACK_HIST1_16_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_16_R_LEN) - 1) << DSP2_BLBACK_HIST1_16_R_POS)) - -/* 0xB44 : REG_HIST1_17 */ -#define DSP2_BLBACK_REG_HIST1_17_OFFSET (0xB44) -#define DSP2_BLBACK_HIST1_17_R DSP2_BLBACK_HIST1_17_R -#define DSP2_BLBACK_HIST1_17_R_POS (0U) -#define DSP2_BLBACK_HIST1_17_R_LEN (24U) -#define DSP2_BLBACK_HIST1_17_R_MSK (((1U << DSP2_BLBACK_HIST1_17_R_LEN) - 1) << DSP2_BLBACK_HIST1_17_R_POS) -#define DSP2_BLBACK_HIST1_17_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_17_R_LEN) - 1) << DSP2_BLBACK_HIST1_17_R_POS)) - -/* 0xB48 : REG_HIST1_18 */ -#define DSP2_BLBACK_REG_HIST1_18_OFFSET (0xB48) -#define DSP2_BLBACK_HIST1_18_R DSP2_BLBACK_HIST1_18_R -#define DSP2_BLBACK_HIST1_18_R_POS (0U) -#define DSP2_BLBACK_HIST1_18_R_LEN (24U) -#define DSP2_BLBACK_HIST1_18_R_MSK (((1U << DSP2_BLBACK_HIST1_18_R_LEN) - 1) << DSP2_BLBACK_HIST1_18_R_POS) -#define DSP2_BLBACK_HIST1_18_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_18_R_LEN) - 1) << DSP2_BLBACK_HIST1_18_R_POS)) - -/* 0xB4C : REG_HIST1_19 */ -#define DSP2_BLBACK_REG_HIST1_19_OFFSET (0xB4C) -#define DSP2_BLBACK_HIST1_19_R DSP2_BLBACK_HIST1_19_R -#define DSP2_BLBACK_HIST1_19_R_POS (0U) -#define DSP2_BLBACK_HIST1_19_R_LEN (24U) -#define DSP2_BLBACK_HIST1_19_R_MSK (((1U << DSP2_BLBACK_HIST1_19_R_LEN) - 1) << DSP2_BLBACK_HIST1_19_R_POS) -#define DSP2_BLBACK_HIST1_19_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_19_R_LEN) - 1) << DSP2_BLBACK_HIST1_19_R_POS)) - -/* 0xB50 : REG_HIST1_20 */ -#define DSP2_BLBACK_REG_HIST1_20_OFFSET (0xB50) -#define DSP2_BLBACK_HIST1_20_R DSP2_BLBACK_HIST1_20_R -#define DSP2_BLBACK_HIST1_20_R_POS (0U) -#define DSP2_BLBACK_HIST1_20_R_LEN (24U) -#define DSP2_BLBACK_HIST1_20_R_MSK (((1U << DSP2_BLBACK_HIST1_20_R_LEN) - 1) << DSP2_BLBACK_HIST1_20_R_POS) -#define DSP2_BLBACK_HIST1_20_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_20_R_LEN) - 1) << DSP2_BLBACK_HIST1_20_R_POS)) - -/* 0xB54 : REG_HIST1_21 */ -#define DSP2_BLBACK_REG_HIST1_21_OFFSET (0xB54) -#define DSP2_BLBACK_HIST1_21_R DSP2_BLBACK_HIST1_21_R -#define DSP2_BLBACK_HIST1_21_R_POS (0U) -#define DSP2_BLBACK_HIST1_21_R_LEN (24U) -#define DSP2_BLBACK_HIST1_21_R_MSK (((1U << DSP2_BLBACK_HIST1_21_R_LEN) - 1) << DSP2_BLBACK_HIST1_21_R_POS) -#define DSP2_BLBACK_HIST1_21_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_21_R_LEN) - 1) << DSP2_BLBACK_HIST1_21_R_POS)) - -/* 0xB58 : REG_HIST1_22 */ -#define DSP2_BLBACK_REG_HIST1_22_OFFSET (0xB58) -#define DSP2_BLBACK_HIST1_22_R DSP2_BLBACK_HIST1_22_R -#define DSP2_BLBACK_HIST1_22_R_POS (0U) -#define DSP2_BLBACK_HIST1_22_R_LEN (24U) -#define DSP2_BLBACK_HIST1_22_R_MSK (((1U << DSP2_BLBACK_HIST1_22_R_LEN) - 1) << DSP2_BLBACK_HIST1_22_R_POS) -#define DSP2_BLBACK_HIST1_22_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_22_R_LEN) - 1) << DSP2_BLBACK_HIST1_22_R_POS)) - -/* 0xB5C : REG_HIST1_23 */ -#define DSP2_BLBACK_REG_HIST1_23_OFFSET (0xB5C) -#define DSP2_BLBACK_HIST1_23_R DSP2_BLBACK_HIST1_23_R -#define DSP2_BLBACK_HIST1_23_R_POS (0U) -#define DSP2_BLBACK_HIST1_23_R_LEN (24U) -#define DSP2_BLBACK_HIST1_23_R_MSK (((1U << DSP2_BLBACK_HIST1_23_R_LEN) - 1) << DSP2_BLBACK_HIST1_23_R_POS) -#define DSP2_BLBACK_HIST1_23_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_23_R_LEN) - 1) << DSP2_BLBACK_HIST1_23_R_POS)) - -/* 0xB60 : REG_HIST1_24 */ -#define DSP2_BLBACK_REG_HIST1_24_OFFSET (0xB60) -#define DSP2_BLBACK_HIST1_24_R DSP2_BLBACK_HIST1_24_R -#define DSP2_BLBACK_HIST1_24_R_POS (0U) -#define DSP2_BLBACK_HIST1_24_R_LEN (24U) -#define DSP2_BLBACK_HIST1_24_R_MSK (((1U << DSP2_BLBACK_HIST1_24_R_LEN) - 1) << DSP2_BLBACK_HIST1_24_R_POS) -#define DSP2_BLBACK_HIST1_24_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_24_R_LEN) - 1) << DSP2_BLBACK_HIST1_24_R_POS)) - -/* 0xB64 : REG_HIST1_25 */ -#define DSP2_BLBACK_REG_HIST1_25_OFFSET (0xB64) -#define DSP2_BLBACK_HIST1_25_R DSP2_BLBACK_HIST1_25_R -#define DSP2_BLBACK_HIST1_25_R_POS (0U) -#define DSP2_BLBACK_HIST1_25_R_LEN (24U) -#define DSP2_BLBACK_HIST1_25_R_MSK (((1U << DSP2_BLBACK_HIST1_25_R_LEN) - 1) << DSP2_BLBACK_HIST1_25_R_POS) -#define DSP2_BLBACK_HIST1_25_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_25_R_LEN) - 1) << DSP2_BLBACK_HIST1_25_R_POS)) - -/* 0xB68 : REG_HIST1_26 */ -#define DSP2_BLBACK_REG_HIST1_26_OFFSET (0xB68) -#define DSP2_BLBACK_HIST1_26_R DSP2_BLBACK_HIST1_26_R -#define DSP2_BLBACK_HIST1_26_R_POS (0U) -#define DSP2_BLBACK_HIST1_26_R_LEN (24U) -#define DSP2_BLBACK_HIST1_26_R_MSK (((1U << DSP2_BLBACK_HIST1_26_R_LEN) - 1) << DSP2_BLBACK_HIST1_26_R_POS) -#define DSP2_BLBACK_HIST1_26_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_26_R_LEN) - 1) << DSP2_BLBACK_HIST1_26_R_POS)) - -/* 0xB6C : REG_HIST1_27 */ -#define DSP2_BLBACK_REG_HIST1_27_OFFSET (0xB6C) -#define DSP2_BLBACK_HIST1_27_R DSP2_BLBACK_HIST1_27_R -#define DSP2_BLBACK_HIST1_27_R_POS (0U) -#define DSP2_BLBACK_HIST1_27_R_LEN (24U) -#define DSP2_BLBACK_HIST1_27_R_MSK (((1U << DSP2_BLBACK_HIST1_27_R_LEN) - 1) << DSP2_BLBACK_HIST1_27_R_POS) -#define DSP2_BLBACK_HIST1_27_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_27_R_LEN) - 1) << DSP2_BLBACK_HIST1_27_R_POS)) - -/* 0xB70 : REG_HIST1_28 */ -#define DSP2_BLBACK_REG_HIST1_28_OFFSET (0xB70) -#define DSP2_BLBACK_HIST1_28_R DSP2_BLBACK_HIST1_28_R -#define DSP2_BLBACK_HIST1_28_R_POS (0U) -#define DSP2_BLBACK_HIST1_28_R_LEN (24U) -#define DSP2_BLBACK_HIST1_28_R_MSK (((1U << DSP2_BLBACK_HIST1_28_R_LEN) - 1) << DSP2_BLBACK_HIST1_28_R_POS) -#define DSP2_BLBACK_HIST1_28_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_28_R_LEN) - 1) << DSP2_BLBACK_HIST1_28_R_POS)) - -/* 0xB74 : REG_HIST1_29 */ -#define DSP2_BLBACK_REG_HIST1_29_OFFSET (0xB74) -#define DSP2_BLBACK_HIST1_29_R DSP2_BLBACK_HIST1_29_R -#define DSP2_BLBACK_HIST1_29_R_POS (0U) -#define DSP2_BLBACK_HIST1_29_R_LEN (24U) -#define DSP2_BLBACK_HIST1_29_R_MSK (((1U << DSP2_BLBACK_HIST1_29_R_LEN) - 1) << DSP2_BLBACK_HIST1_29_R_POS) -#define DSP2_BLBACK_HIST1_29_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_29_R_LEN) - 1) << DSP2_BLBACK_HIST1_29_R_POS)) - -/* 0xB78 : REG_HIST1_30 */ -#define DSP2_BLBACK_REG_HIST1_30_OFFSET (0xB78) -#define DSP2_BLBACK_HIST1_30_R DSP2_BLBACK_HIST1_30_R -#define DSP2_BLBACK_HIST1_30_R_POS (0U) -#define DSP2_BLBACK_HIST1_30_R_LEN (24U) -#define DSP2_BLBACK_HIST1_30_R_MSK (((1U << DSP2_BLBACK_HIST1_30_R_LEN) - 1) << DSP2_BLBACK_HIST1_30_R_POS) -#define DSP2_BLBACK_HIST1_30_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_30_R_LEN) - 1) << DSP2_BLBACK_HIST1_30_R_POS)) - -/* 0xB7C : REG_HIST1_31 */ -#define DSP2_BLBACK_REG_HIST1_31_OFFSET (0xB7C) -#define DSP2_BLBACK_HIST1_31_R DSP2_BLBACK_HIST1_31_R -#define DSP2_BLBACK_HIST1_31_R_POS (0U) -#define DSP2_BLBACK_HIST1_31_R_LEN (24U) -#define DSP2_BLBACK_HIST1_31_R_MSK (((1U << DSP2_BLBACK_HIST1_31_R_LEN) - 1) << DSP2_BLBACK_HIST1_31_R_POS) -#define DSP2_BLBACK_HIST1_31_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_31_R_LEN) - 1) << DSP2_BLBACK_HIST1_31_R_POS)) - -/* 0xB80 : REG_HIST1_32 */ -#define DSP2_BLBACK_REG_HIST1_32_OFFSET (0xB80) -#define DSP2_BLBACK_HIST1_32_R DSP2_BLBACK_HIST1_32_R -#define DSP2_BLBACK_HIST1_32_R_POS (0U) -#define DSP2_BLBACK_HIST1_32_R_LEN (24U) -#define DSP2_BLBACK_HIST1_32_R_MSK (((1U << DSP2_BLBACK_HIST1_32_R_LEN) - 1) << DSP2_BLBACK_HIST1_32_R_POS) -#define DSP2_BLBACK_HIST1_32_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_32_R_LEN) - 1) << DSP2_BLBACK_HIST1_32_R_POS)) - -/* 0xB84 : REG_HIST1_33 */ -#define DSP2_BLBACK_REG_HIST1_33_OFFSET (0xB84) -#define DSP2_BLBACK_HIST1_33_R DSP2_BLBACK_HIST1_33_R -#define DSP2_BLBACK_HIST1_33_R_POS (0U) -#define DSP2_BLBACK_HIST1_33_R_LEN (24U) -#define DSP2_BLBACK_HIST1_33_R_MSK (((1U << DSP2_BLBACK_HIST1_33_R_LEN) - 1) << DSP2_BLBACK_HIST1_33_R_POS) -#define DSP2_BLBACK_HIST1_33_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_33_R_LEN) - 1) << DSP2_BLBACK_HIST1_33_R_POS)) - -/* 0xB88 : REG_HIST1_34 */ -#define DSP2_BLBACK_REG_HIST1_34_OFFSET (0xB88) -#define DSP2_BLBACK_HIST1_34_R DSP2_BLBACK_HIST1_34_R -#define DSP2_BLBACK_HIST1_34_R_POS (0U) -#define DSP2_BLBACK_HIST1_34_R_LEN (24U) -#define DSP2_BLBACK_HIST1_34_R_MSK (((1U << DSP2_BLBACK_HIST1_34_R_LEN) - 1) << DSP2_BLBACK_HIST1_34_R_POS) -#define DSP2_BLBACK_HIST1_34_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_34_R_LEN) - 1) << DSP2_BLBACK_HIST1_34_R_POS)) - -/* 0xB8C : REG_HIST1_35 */ -#define DSP2_BLBACK_REG_HIST1_35_OFFSET (0xB8C) -#define DSP2_BLBACK_HIST1_35_R DSP2_BLBACK_HIST1_35_R -#define DSP2_BLBACK_HIST1_35_R_POS (0U) -#define DSP2_BLBACK_HIST1_35_R_LEN (24U) -#define DSP2_BLBACK_HIST1_35_R_MSK (((1U << DSP2_BLBACK_HIST1_35_R_LEN) - 1) << DSP2_BLBACK_HIST1_35_R_POS) -#define DSP2_BLBACK_HIST1_35_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_35_R_LEN) - 1) << DSP2_BLBACK_HIST1_35_R_POS)) - -/* 0xB90 : REG_HIST1_36 */ -#define DSP2_BLBACK_REG_HIST1_36_OFFSET (0xB90) -#define DSP2_BLBACK_HIST1_36_R DSP2_BLBACK_HIST1_36_R -#define DSP2_BLBACK_HIST1_36_R_POS (0U) -#define DSP2_BLBACK_HIST1_36_R_LEN (24U) -#define DSP2_BLBACK_HIST1_36_R_MSK (((1U << DSP2_BLBACK_HIST1_36_R_LEN) - 1) << DSP2_BLBACK_HIST1_36_R_POS) -#define DSP2_BLBACK_HIST1_36_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_36_R_LEN) - 1) << DSP2_BLBACK_HIST1_36_R_POS)) - -/* 0xB94 : REG_HIST1_37 */ -#define DSP2_BLBACK_REG_HIST1_37_OFFSET (0xB94) -#define DSP2_BLBACK_HIST1_37_R DSP2_BLBACK_HIST1_37_R -#define DSP2_BLBACK_HIST1_37_R_POS (0U) -#define DSP2_BLBACK_HIST1_37_R_LEN (24U) -#define DSP2_BLBACK_HIST1_37_R_MSK (((1U << DSP2_BLBACK_HIST1_37_R_LEN) - 1) << DSP2_BLBACK_HIST1_37_R_POS) -#define DSP2_BLBACK_HIST1_37_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_37_R_LEN) - 1) << DSP2_BLBACK_HIST1_37_R_POS)) - -/* 0xB98 : REG_HIST1_38 */ -#define DSP2_BLBACK_REG_HIST1_38_OFFSET (0xB98) -#define DSP2_BLBACK_HIST1_38_R DSP2_BLBACK_HIST1_38_R -#define DSP2_BLBACK_HIST1_38_R_POS (0U) -#define DSP2_BLBACK_HIST1_38_R_LEN (24U) -#define DSP2_BLBACK_HIST1_38_R_MSK (((1U << DSP2_BLBACK_HIST1_38_R_LEN) - 1) << DSP2_BLBACK_HIST1_38_R_POS) -#define DSP2_BLBACK_HIST1_38_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_38_R_LEN) - 1) << DSP2_BLBACK_HIST1_38_R_POS)) - -/* 0xB9C : REG_HIST1_39 */ -#define DSP2_BLBACK_REG_HIST1_39_OFFSET (0xB9C) -#define DSP2_BLBACK_HIST1_39_R DSP2_BLBACK_HIST1_39_R -#define DSP2_BLBACK_HIST1_39_R_POS (0U) -#define DSP2_BLBACK_HIST1_39_R_LEN (24U) -#define DSP2_BLBACK_HIST1_39_R_MSK (((1U << DSP2_BLBACK_HIST1_39_R_LEN) - 1) << DSP2_BLBACK_HIST1_39_R_POS) -#define DSP2_BLBACK_HIST1_39_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_39_R_LEN) - 1) << DSP2_BLBACK_HIST1_39_R_POS)) - -/* 0xBA0 : REG_HIST1_40 */ -#define DSP2_BLBACK_REG_HIST1_40_OFFSET (0xBA0) -#define DSP2_BLBACK_HIST1_40_R DSP2_BLBACK_HIST1_40_R -#define DSP2_BLBACK_HIST1_40_R_POS (0U) -#define DSP2_BLBACK_HIST1_40_R_LEN (24U) -#define DSP2_BLBACK_HIST1_40_R_MSK (((1U << DSP2_BLBACK_HIST1_40_R_LEN) - 1) << DSP2_BLBACK_HIST1_40_R_POS) -#define DSP2_BLBACK_HIST1_40_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_40_R_LEN) - 1) << DSP2_BLBACK_HIST1_40_R_POS)) - -/* 0xBA4 : REG_HIST1_41 */ -#define DSP2_BLBACK_REG_HIST1_41_OFFSET (0xBA4) -#define DSP2_BLBACK_HIST1_41_R DSP2_BLBACK_HIST1_41_R -#define DSP2_BLBACK_HIST1_41_R_POS (0U) -#define DSP2_BLBACK_HIST1_41_R_LEN (24U) -#define DSP2_BLBACK_HIST1_41_R_MSK (((1U << DSP2_BLBACK_HIST1_41_R_LEN) - 1) << DSP2_BLBACK_HIST1_41_R_POS) -#define DSP2_BLBACK_HIST1_41_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_41_R_LEN) - 1) << DSP2_BLBACK_HIST1_41_R_POS)) - -/* 0xBA8 : REG_HIST1_42 */ -#define DSP2_BLBACK_REG_HIST1_42_OFFSET (0xBA8) -#define DSP2_BLBACK_HIST1_42_R DSP2_BLBACK_HIST1_42_R -#define DSP2_BLBACK_HIST1_42_R_POS (0U) -#define DSP2_BLBACK_HIST1_42_R_LEN (24U) -#define DSP2_BLBACK_HIST1_42_R_MSK (((1U << DSP2_BLBACK_HIST1_42_R_LEN) - 1) << DSP2_BLBACK_HIST1_42_R_POS) -#define DSP2_BLBACK_HIST1_42_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_42_R_LEN) - 1) << DSP2_BLBACK_HIST1_42_R_POS)) - -/* 0xBAC : REG_HIST1_43 */ -#define DSP2_BLBACK_REG_HIST1_43_OFFSET (0xBAC) -#define DSP2_BLBACK_HIST1_43_R DSP2_BLBACK_HIST1_43_R -#define DSP2_BLBACK_HIST1_43_R_POS (0U) -#define DSP2_BLBACK_HIST1_43_R_LEN (24U) -#define DSP2_BLBACK_HIST1_43_R_MSK (((1U << DSP2_BLBACK_HIST1_43_R_LEN) - 1) << DSP2_BLBACK_HIST1_43_R_POS) -#define DSP2_BLBACK_HIST1_43_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_43_R_LEN) - 1) << DSP2_BLBACK_HIST1_43_R_POS)) - -/* 0xBB0 : REG_HIST1_44 */ -#define DSP2_BLBACK_REG_HIST1_44_OFFSET (0xBB0) -#define DSP2_BLBACK_HIST1_44_R DSP2_BLBACK_HIST1_44_R -#define DSP2_BLBACK_HIST1_44_R_POS (0U) -#define DSP2_BLBACK_HIST1_44_R_LEN (24U) -#define DSP2_BLBACK_HIST1_44_R_MSK (((1U << DSP2_BLBACK_HIST1_44_R_LEN) - 1) << DSP2_BLBACK_HIST1_44_R_POS) -#define DSP2_BLBACK_HIST1_44_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_44_R_LEN) - 1) << DSP2_BLBACK_HIST1_44_R_POS)) - -/* 0xBB4 : REG_HIST1_45 */ -#define DSP2_BLBACK_REG_HIST1_45_OFFSET (0xBB4) -#define DSP2_BLBACK_HIST1_45_R DSP2_BLBACK_HIST1_45_R -#define DSP2_BLBACK_HIST1_45_R_POS (0U) -#define DSP2_BLBACK_HIST1_45_R_LEN (24U) -#define DSP2_BLBACK_HIST1_45_R_MSK (((1U << DSP2_BLBACK_HIST1_45_R_LEN) - 1) << DSP2_BLBACK_HIST1_45_R_POS) -#define DSP2_BLBACK_HIST1_45_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_45_R_LEN) - 1) << DSP2_BLBACK_HIST1_45_R_POS)) - -/* 0xBB8 : REG_HIST1_46 */ -#define DSP2_BLBACK_REG_HIST1_46_OFFSET (0xBB8) -#define DSP2_BLBACK_HIST1_46_R DSP2_BLBACK_HIST1_46_R -#define DSP2_BLBACK_HIST1_46_R_POS (0U) -#define DSP2_BLBACK_HIST1_46_R_LEN (24U) -#define DSP2_BLBACK_HIST1_46_R_MSK (((1U << DSP2_BLBACK_HIST1_46_R_LEN) - 1) << DSP2_BLBACK_HIST1_46_R_POS) -#define DSP2_BLBACK_HIST1_46_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_46_R_LEN) - 1) << DSP2_BLBACK_HIST1_46_R_POS)) - -/* 0xBBC : REG_HIST1_47 */ -#define DSP2_BLBACK_REG_HIST1_47_OFFSET (0xBBC) -#define DSP2_BLBACK_HIST1_47_R DSP2_BLBACK_HIST1_47_R -#define DSP2_BLBACK_HIST1_47_R_POS (0U) -#define DSP2_BLBACK_HIST1_47_R_LEN (24U) -#define DSP2_BLBACK_HIST1_47_R_MSK (((1U << DSP2_BLBACK_HIST1_47_R_LEN) - 1) << DSP2_BLBACK_HIST1_47_R_POS) -#define DSP2_BLBACK_HIST1_47_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_47_R_LEN) - 1) << DSP2_BLBACK_HIST1_47_R_POS)) - -/* 0xBC0 : REG_HIST1_48 */ -#define DSP2_BLBACK_REG_HIST1_48_OFFSET (0xBC0) -#define DSP2_BLBACK_HIST1_48_R DSP2_BLBACK_HIST1_48_R -#define DSP2_BLBACK_HIST1_48_R_POS (0U) -#define DSP2_BLBACK_HIST1_48_R_LEN (24U) -#define DSP2_BLBACK_HIST1_48_R_MSK (((1U << DSP2_BLBACK_HIST1_48_R_LEN) - 1) << DSP2_BLBACK_HIST1_48_R_POS) -#define DSP2_BLBACK_HIST1_48_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_48_R_LEN) - 1) << DSP2_BLBACK_HIST1_48_R_POS)) - -/* 0xBC4 : REG_HIST1_49 */ -#define DSP2_BLBACK_REG_HIST1_49_OFFSET (0xBC4) -#define DSP2_BLBACK_HIST1_49_R DSP2_BLBACK_HIST1_49_R -#define DSP2_BLBACK_HIST1_49_R_POS (0U) -#define DSP2_BLBACK_HIST1_49_R_LEN (24U) -#define DSP2_BLBACK_HIST1_49_R_MSK (((1U << DSP2_BLBACK_HIST1_49_R_LEN) - 1) << DSP2_BLBACK_HIST1_49_R_POS) -#define DSP2_BLBACK_HIST1_49_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_49_R_LEN) - 1) << DSP2_BLBACK_HIST1_49_R_POS)) - -/* 0xBC8 : REG_HIST1_50 */ -#define DSP2_BLBACK_REG_HIST1_50_OFFSET (0xBC8) -#define DSP2_BLBACK_HIST1_50_R DSP2_BLBACK_HIST1_50_R -#define DSP2_BLBACK_HIST1_50_R_POS (0U) -#define DSP2_BLBACK_HIST1_50_R_LEN (24U) -#define DSP2_BLBACK_HIST1_50_R_MSK (((1U << DSP2_BLBACK_HIST1_50_R_LEN) - 1) << DSP2_BLBACK_HIST1_50_R_POS) -#define DSP2_BLBACK_HIST1_50_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_50_R_LEN) - 1) << DSP2_BLBACK_HIST1_50_R_POS)) - -/* 0xBCC : REG_HIST1_51 */ -#define DSP2_BLBACK_REG_HIST1_51_OFFSET (0xBCC) -#define DSP2_BLBACK_HIST1_51_R DSP2_BLBACK_HIST1_51_R -#define DSP2_BLBACK_HIST1_51_R_POS (0U) -#define DSP2_BLBACK_HIST1_51_R_LEN (24U) -#define DSP2_BLBACK_HIST1_51_R_MSK (((1U << DSP2_BLBACK_HIST1_51_R_LEN) - 1) << DSP2_BLBACK_HIST1_51_R_POS) -#define DSP2_BLBACK_HIST1_51_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_51_R_LEN) - 1) << DSP2_BLBACK_HIST1_51_R_POS)) - -/* 0xBD0 : REG_HIST1_52 */ -#define DSP2_BLBACK_REG_HIST1_52_OFFSET (0xBD0) -#define DSP2_BLBACK_HIST1_52_R DSP2_BLBACK_HIST1_52_R -#define DSP2_BLBACK_HIST1_52_R_POS (0U) -#define DSP2_BLBACK_HIST1_52_R_LEN (24U) -#define DSP2_BLBACK_HIST1_52_R_MSK (((1U << DSP2_BLBACK_HIST1_52_R_LEN) - 1) << DSP2_BLBACK_HIST1_52_R_POS) -#define DSP2_BLBACK_HIST1_52_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_52_R_LEN) - 1) << DSP2_BLBACK_HIST1_52_R_POS)) - -/* 0xBD4 : REG_HIST1_53 */ -#define DSP2_BLBACK_REG_HIST1_53_OFFSET (0xBD4) -#define DSP2_BLBACK_HIST1_53_R DSP2_BLBACK_HIST1_53_R -#define DSP2_BLBACK_HIST1_53_R_POS (0U) -#define DSP2_BLBACK_HIST1_53_R_LEN (24U) -#define DSP2_BLBACK_HIST1_53_R_MSK (((1U << DSP2_BLBACK_HIST1_53_R_LEN) - 1) << DSP2_BLBACK_HIST1_53_R_POS) -#define DSP2_BLBACK_HIST1_53_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_53_R_LEN) - 1) << DSP2_BLBACK_HIST1_53_R_POS)) - -/* 0xBD8 : REG_HIST1_54 */ -#define DSP2_BLBACK_REG_HIST1_54_OFFSET (0xBD8) -#define DSP2_BLBACK_HIST1_54_R DSP2_BLBACK_HIST1_54_R -#define DSP2_BLBACK_HIST1_54_R_POS (0U) -#define DSP2_BLBACK_HIST1_54_R_LEN (24U) -#define DSP2_BLBACK_HIST1_54_R_MSK (((1U << DSP2_BLBACK_HIST1_54_R_LEN) - 1) << DSP2_BLBACK_HIST1_54_R_POS) -#define DSP2_BLBACK_HIST1_54_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_54_R_LEN) - 1) << DSP2_BLBACK_HIST1_54_R_POS)) - -/* 0xBDC : REG_HIST1_55 */ -#define DSP2_BLBACK_REG_HIST1_55_OFFSET (0xBDC) -#define DSP2_BLBACK_HIST1_55_R DSP2_BLBACK_HIST1_55_R -#define DSP2_BLBACK_HIST1_55_R_POS (0U) -#define DSP2_BLBACK_HIST1_55_R_LEN (24U) -#define DSP2_BLBACK_HIST1_55_R_MSK (((1U << DSP2_BLBACK_HIST1_55_R_LEN) - 1) << DSP2_BLBACK_HIST1_55_R_POS) -#define DSP2_BLBACK_HIST1_55_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_55_R_LEN) - 1) << DSP2_BLBACK_HIST1_55_R_POS)) - -/* 0xBE0 : REG_HIST1_56 */ -#define DSP2_BLBACK_REG_HIST1_56_OFFSET (0xBE0) -#define DSP2_BLBACK_HIST1_56_R DSP2_BLBACK_HIST1_56_R -#define DSP2_BLBACK_HIST1_56_R_POS (0U) -#define DSP2_BLBACK_HIST1_56_R_LEN (24U) -#define DSP2_BLBACK_HIST1_56_R_MSK (((1U << DSP2_BLBACK_HIST1_56_R_LEN) - 1) << DSP2_BLBACK_HIST1_56_R_POS) -#define DSP2_BLBACK_HIST1_56_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_56_R_LEN) - 1) << DSP2_BLBACK_HIST1_56_R_POS)) - -/* 0xBE4 : REG_HIST1_57 */ -#define DSP2_BLBACK_REG_HIST1_57_OFFSET (0xBE4) -#define DSP2_BLBACK_HIST1_57_R DSP2_BLBACK_HIST1_57_R -#define DSP2_BLBACK_HIST1_57_R_POS (0U) -#define DSP2_BLBACK_HIST1_57_R_LEN (24U) -#define DSP2_BLBACK_HIST1_57_R_MSK (((1U << DSP2_BLBACK_HIST1_57_R_LEN) - 1) << DSP2_BLBACK_HIST1_57_R_POS) -#define DSP2_BLBACK_HIST1_57_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_57_R_LEN) - 1) << DSP2_BLBACK_HIST1_57_R_POS)) - -/* 0xBE8 : REG_HIST1_58 */ -#define DSP2_BLBACK_REG_HIST1_58_OFFSET (0xBE8) -#define DSP2_BLBACK_HIST1_58_R DSP2_BLBACK_HIST1_58_R -#define DSP2_BLBACK_HIST1_58_R_POS (0U) -#define DSP2_BLBACK_HIST1_58_R_LEN (24U) -#define DSP2_BLBACK_HIST1_58_R_MSK (((1U << DSP2_BLBACK_HIST1_58_R_LEN) - 1) << DSP2_BLBACK_HIST1_58_R_POS) -#define DSP2_BLBACK_HIST1_58_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_58_R_LEN) - 1) << DSP2_BLBACK_HIST1_58_R_POS)) - -/* 0xBEC : REG_HIST1_59 */ -#define DSP2_BLBACK_REG_HIST1_59_OFFSET (0xBEC) -#define DSP2_BLBACK_HIST1_59_R DSP2_BLBACK_HIST1_59_R -#define DSP2_BLBACK_HIST1_59_R_POS (0U) -#define DSP2_BLBACK_HIST1_59_R_LEN (24U) -#define DSP2_BLBACK_HIST1_59_R_MSK (((1U << DSP2_BLBACK_HIST1_59_R_LEN) - 1) << DSP2_BLBACK_HIST1_59_R_POS) -#define DSP2_BLBACK_HIST1_59_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_59_R_LEN) - 1) << DSP2_BLBACK_HIST1_59_R_POS)) - -/* 0xBF0 : REG_HIST1_60 */ -#define DSP2_BLBACK_REG_HIST1_60_OFFSET (0xBF0) -#define DSP2_BLBACK_HIST1_60_R DSP2_BLBACK_HIST1_60_R -#define DSP2_BLBACK_HIST1_60_R_POS (0U) -#define DSP2_BLBACK_HIST1_60_R_LEN (24U) -#define DSP2_BLBACK_HIST1_60_R_MSK (((1U << DSP2_BLBACK_HIST1_60_R_LEN) - 1) << DSP2_BLBACK_HIST1_60_R_POS) -#define DSP2_BLBACK_HIST1_60_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_60_R_LEN) - 1) << DSP2_BLBACK_HIST1_60_R_POS)) - -/* 0xBF4 : REG_HIST1_61 */ -#define DSP2_BLBACK_REG_HIST1_61_OFFSET (0xBF4) -#define DSP2_BLBACK_HIST1_61_R DSP2_BLBACK_HIST1_61_R -#define DSP2_BLBACK_HIST1_61_R_POS (0U) -#define DSP2_BLBACK_HIST1_61_R_LEN (24U) -#define DSP2_BLBACK_HIST1_61_R_MSK (((1U << DSP2_BLBACK_HIST1_61_R_LEN) - 1) << DSP2_BLBACK_HIST1_61_R_POS) -#define DSP2_BLBACK_HIST1_61_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_61_R_LEN) - 1) << DSP2_BLBACK_HIST1_61_R_POS)) - -/* 0xBF8 : REG_HIST1_62 */ -#define DSP2_BLBACK_REG_HIST1_62_OFFSET (0xBF8) -#define DSP2_BLBACK_HIST1_62_R DSP2_BLBACK_HIST1_62_R -#define DSP2_BLBACK_HIST1_62_R_POS (0U) -#define DSP2_BLBACK_HIST1_62_R_LEN (24U) -#define DSP2_BLBACK_HIST1_62_R_MSK (((1U << DSP2_BLBACK_HIST1_62_R_LEN) - 1) << DSP2_BLBACK_HIST1_62_R_POS) -#define DSP2_BLBACK_HIST1_62_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_62_R_LEN) - 1) << DSP2_BLBACK_HIST1_62_R_POS)) - -/* 0xBFC : REG_HIST1_63 */ -#define DSP2_BLBACK_REG_HIST1_63_OFFSET (0xBFC) -#define DSP2_BLBACK_HIST1_63_R DSP2_BLBACK_HIST1_63_R -#define DSP2_BLBACK_HIST1_63_R_POS (0U) -#define DSP2_BLBACK_HIST1_63_R_LEN (24U) -#define DSP2_BLBACK_HIST1_63_R_MSK (((1U << DSP2_BLBACK_HIST1_63_R_LEN) - 1) << DSP2_BLBACK_HIST1_63_R_POS) -#define DSP2_BLBACK_HIST1_63_R_UMSK (~(((1U << DSP2_BLBACK_HIST1_63_R_LEN) - 1) << DSP2_BLBACK_HIST1_63_R_POS)) - -/* 0xC00 : WDR_CURVE_1 */ -#define DSP2_BLBACK_WDR_CURVE_1_OFFSET (0xC00) -#define DSP2_BLBACK_CURVE_0_PRE DSP2_BLBACK_CURVE_0_PRE -#define DSP2_BLBACK_CURVE_0_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_0_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_0_PRE_MSK (((1U << DSP2_BLBACK_CURVE_0_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_0_PRE_POS) -#define DSP2_BLBACK_CURVE_0_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_0_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_0_PRE_POS)) -#define DSP2_BLBACK_CURVE_1_PRE DSP2_BLBACK_CURVE_1_PRE -#define DSP2_BLBACK_CURVE_1_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_1_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_1_PRE_MSK (((1U << DSP2_BLBACK_CURVE_1_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_1_PRE_POS) -#define DSP2_BLBACK_CURVE_1_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_1_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_1_PRE_POS)) - -/* 0xC04 : WDR_CURVE_2 */ -#define DSP2_BLBACK_WDR_CURVE_2_OFFSET (0xC04) -#define DSP2_BLBACK_CURVE_2_PRE DSP2_BLBACK_CURVE_2_PRE -#define DSP2_BLBACK_CURVE_2_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_2_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_2_PRE_MSK (((1U << DSP2_BLBACK_CURVE_2_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_2_PRE_POS) -#define DSP2_BLBACK_CURVE_2_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_2_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_2_PRE_POS)) -#define DSP2_BLBACK_CURVE_3_PRE DSP2_BLBACK_CURVE_3_PRE -#define DSP2_BLBACK_CURVE_3_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_3_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_3_PRE_MSK (((1U << DSP2_BLBACK_CURVE_3_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_3_PRE_POS) -#define DSP2_BLBACK_CURVE_3_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_3_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_3_PRE_POS)) - -/* 0xC08 : WDR_CURVE_3 */ -#define DSP2_BLBACK_WDR_CURVE_3_OFFSET (0xC08) -#define DSP2_BLBACK_CURVE_4_PRE DSP2_BLBACK_CURVE_4_PRE -#define DSP2_BLBACK_CURVE_4_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_4_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_4_PRE_MSK (((1U << DSP2_BLBACK_CURVE_4_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_4_PRE_POS) -#define DSP2_BLBACK_CURVE_4_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_4_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_4_PRE_POS)) -#define DSP2_BLBACK_CURVE_5_PRE DSP2_BLBACK_CURVE_5_PRE -#define DSP2_BLBACK_CURVE_5_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_5_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_5_PRE_MSK (((1U << DSP2_BLBACK_CURVE_5_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_5_PRE_POS) -#define DSP2_BLBACK_CURVE_5_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_5_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_5_PRE_POS)) - -/* 0xC0C : WDR_CURVE_4 */ -#define DSP2_BLBACK_WDR_CURVE_4_OFFSET (0xC0C) -#define DSP2_BLBACK_CURVE_6_PRE DSP2_BLBACK_CURVE_6_PRE -#define DSP2_BLBACK_CURVE_6_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_6_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_6_PRE_MSK (((1U << DSP2_BLBACK_CURVE_6_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_6_PRE_POS) -#define DSP2_BLBACK_CURVE_6_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_6_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_6_PRE_POS)) -#define DSP2_BLBACK_CURVE_7_PRE DSP2_BLBACK_CURVE_7_PRE -#define DSP2_BLBACK_CURVE_7_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_7_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_7_PRE_MSK (((1U << DSP2_BLBACK_CURVE_7_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_7_PRE_POS) -#define DSP2_BLBACK_CURVE_7_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_7_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_7_PRE_POS)) - -/* 0xC10 : WDR_CURVE_5 */ -#define DSP2_BLBACK_WDR_CURVE_5_OFFSET (0xC10) -#define DSP2_BLBACK_CURVE_8_PRE DSP2_BLBACK_CURVE_8_PRE -#define DSP2_BLBACK_CURVE_8_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_8_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_8_PRE_MSK (((1U << DSP2_BLBACK_CURVE_8_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_8_PRE_POS) -#define DSP2_BLBACK_CURVE_8_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_8_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_8_PRE_POS)) -#define DSP2_BLBACK_CURVE_9_PRE DSP2_BLBACK_CURVE_9_PRE -#define DSP2_BLBACK_CURVE_9_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_9_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_9_PRE_MSK (((1U << DSP2_BLBACK_CURVE_9_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_9_PRE_POS) -#define DSP2_BLBACK_CURVE_9_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_9_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_9_PRE_POS)) - -/* 0xC14 : WDR_CURVE_6 */ -#define DSP2_BLBACK_WDR_CURVE_6_OFFSET (0xC14) -#define DSP2_BLBACK_CURVE_10_PRE DSP2_BLBACK_CURVE_10_PRE -#define DSP2_BLBACK_CURVE_10_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_10_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_10_PRE_MSK (((1U << DSP2_BLBACK_CURVE_10_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_10_PRE_POS) -#define DSP2_BLBACK_CURVE_10_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_10_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_10_PRE_POS)) -#define DSP2_BLBACK_CURVE_11_PRE DSP2_BLBACK_CURVE_11_PRE -#define DSP2_BLBACK_CURVE_11_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_11_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_11_PRE_MSK (((1U << DSP2_BLBACK_CURVE_11_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_11_PRE_POS) -#define DSP2_BLBACK_CURVE_11_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_11_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_11_PRE_POS)) - -/* 0xC18 : WDR_CURVE_7 */ -#define DSP2_BLBACK_WDR_CURVE_7_OFFSET (0xC18) -#define DSP2_BLBACK_CURVE_12_PRE DSP2_BLBACK_CURVE_12_PRE -#define DSP2_BLBACK_CURVE_12_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_12_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_12_PRE_MSK (((1U << DSP2_BLBACK_CURVE_12_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_12_PRE_POS) -#define DSP2_BLBACK_CURVE_12_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_12_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_12_PRE_POS)) -#define DSP2_BLBACK_CURVE_13_PRE DSP2_BLBACK_CURVE_13_PRE -#define DSP2_BLBACK_CURVE_13_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_13_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_13_PRE_MSK (((1U << DSP2_BLBACK_CURVE_13_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_13_PRE_POS) -#define DSP2_BLBACK_CURVE_13_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_13_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_13_PRE_POS)) - -/* 0xC1C : WDR_CURVE_8 */ -#define DSP2_BLBACK_WDR_CURVE_8_OFFSET (0xC1C) -#define DSP2_BLBACK_CURVE_14_PRE DSP2_BLBACK_CURVE_14_PRE -#define DSP2_BLBACK_CURVE_14_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_14_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_14_PRE_MSK (((1U << DSP2_BLBACK_CURVE_14_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_14_PRE_POS) -#define DSP2_BLBACK_CURVE_14_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_14_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_14_PRE_POS)) -#define DSP2_BLBACK_CURVE_15_PRE DSP2_BLBACK_CURVE_15_PRE -#define DSP2_BLBACK_CURVE_15_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_15_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_15_PRE_MSK (((1U << DSP2_BLBACK_CURVE_15_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_15_PRE_POS) -#define DSP2_BLBACK_CURVE_15_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_15_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_15_PRE_POS)) - -/* 0xC20 : WDR_CURVE_9 */ -#define DSP2_BLBACK_WDR_CURVE_9_OFFSET (0xC20) -#define DSP2_BLBACK_CURVE_16_PRE DSP2_BLBACK_CURVE_16_PRE -#define DSP2_BLBACK_CURVE_16_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_16_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_16_PRE_MSK (((1U << DSP2_BLBACK_CURVE_16_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_16_PRE_POS) -#define DSP2_BLBACK_CURVE_16_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_16_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_16_PRE_POS)) -#define DSP2_BLBACK_CURVE_17_PRE DSP2_BLBACK_CURVE_17_PRE -#define DSP2_BLBACK_CURVE_17_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_17_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_17_PRE_MSK (((1U << DSP2_BLBACK_CURVE_17_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_17_PRE_POS) -#define DSP2_BLBACK_CURVE_17_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_17_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_17_PRE_POS)) - -/* 0xC24 : WDR_CURVE_10 */ -#define DSP2_BLBACK_WDR_CURVE_10_OFFSET (0xC24) -#define DSP2_BLBACK_CURVE_18_PRE DSP2_BLBACK_CURVE_18_PRE -#define DSP2_BLBACK_CURVE_18_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_18_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_18_PRE_MSK (((1U << DSP2_BLBACK_CURVE_18_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_18_PRE_POS) -#define DSP2_BLBACK_CURVE_18_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_18_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_18_PRE_POS)) -#define DSP2_BLBACK_CURVE_19_PRE DSP2_BLBACK_CURVE_19_PRE -#define DSP2_BLBACK_CURVE_19_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_19_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_19_PRE_MSK (((1U << DSP2_BLBACK_CURVE_19_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_19_PRE_POS) -#define DSP2_BLBACK_CURVE_19_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_19_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_19_PRE_POS)) - -/* 0xC28 : WDR_CURVE_11 */ -#define DSP2_BLBACK_WDR_CURVE_11_OFFSET (0xC28) -#define DSP2_BLBACK_CURVE_20_PRE DSP2_BLBACK_CURVE_20_PRE -#define DSP2_BLBACK_CURVE_20_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_20_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_20_PRE_MSK (((1U << DSP2_BLBACK_CURVE_20_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_20_PRE_POS) -#define DSP2_BLBACK_CURVE_20_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_20_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_20_PRE_POS)) -#define DSP2_BLBACK_CURVE_21_PRE DSP2_BLBACK_CURVE_21_PRE -#define DSP2_BLBACK_CURVE_21_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_21_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_21_PRE_MSK (((1U << DSP2_BLBACK_CURVE_21_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_21_PRE_POS) -#define DSP2_BLBACK_CURVE_21_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_21_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_21_PRE_POS)) - -/* 0xC2C : WDR_CURVE_12 */ -#define DSP2_BLBACK_WDR_CURVE_12_OFFSET (0xC2C) -#define DSP2_BLBACK_CURVE_22_PRE DSP2_BLBACK_CURVE_22_PRE -#define DSP2_BLBACK_CURVE_22_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_22_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_22_PRE_MSK (((1U << DSP2_BLBACK_CURVE_22_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_22_PRE_POS) -#define DSP2_BLBACK_CURVE_22_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_22_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_22_PRE_POS)) -#define DSP2_BLBACK_CURVE_23_PRE DSP2_BLBACK_CURVE_23_PRE -#define DSP2_BLBACK_CURVE_23_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_23_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_23_PRE_MSK (((1U << DSP2_BLBACK_CURVE_23_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_23_PRE_POS) -#define DSP2_BLBACK_CURVE_23_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_23_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_23_PRE_POS)) - -/* 0xC30 : WDR_CURVE_13 */ -#define DSP2_BLBACK_WDR_CURVE_13_OFFSET (0xC30) -#define DSP2_BLBACK_CURVE_24_PRE DSP2_BLBACK_CURVE_24_PRE -#define DSP2_BLBACK_CURVE_24_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_24_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_24_PRE_MSK (((1U << DSP2_BLBACK_CURVE_24_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_24_PRE_POS) -#define DSP2_BLBACK_CURVE_24_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_24_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_24_PRE_POS)) -#define DSP2_BLBACK_CURVE_25_PRE DSP2_BLBACK_CURVE_25_PRE -#define DSP2_BLBACK_CURVE_25_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_25_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_25_PRE_MSK (((1U << DSP2_BLBACK_CURVE_25_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_25_PRE_POS) -#define DSP2_BLBACK_CURVE_25_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_25_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_25_PRE_POS)) - -/* 0xC34 : WDR_CURVE_14 */ -#define DSP2_BLBACK_WDR_CURVE_14_OFFSET (0xC34) -#define DSP2_BLBACK_CURVE_26_PRE DSP2_BLBACK_CURVE_26_PRE -#define DSP2_BLBACK_CURVE_26_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_26_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_26_PRE_MSK (((1U << DSP2_BLBACK_CURVE_26_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_26_PRE_POS) -#define DSP2_BLBACK_CURVE_26_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_26_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_26_PRE_POS)) -#define DSP2_BLBACK_CURVE_27_PRE DSP2_BLBACK_CURVE_27_PRE -#define DSP2_BLBACK_CURVE_27_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_27_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_27_PRE_MSK (((1U << DSP2_BLBACK_CURVE_27_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_27_PRE_POS) -#define DSP2_BLBACK_CURVE_27_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_27_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_27_PRE_POS)) - -/* 0xC38 : WDR_CURVE_15 */ -#define DSP2_BLBACK_WDR_CURVE_15_OFFSET (0xC38) -#define DSP2_BLBACK_CURVE_28_PRE DSP2_BLBACK_CURVE_28_PRE -#define DSP2_BLBACK_CURVE_28_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_28_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_28_PRE_MSK (((1U << DSP2_BLBACK_CURVE_28_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_28_PRE_POS) -#define DSP2_BLBACK_CURVE_28_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_28_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_28_PRE_POS)) -#define DSP2_BLBACK_CURVE_29_PRE DSP2_BLBACK_CURVE_29_PRE -#define DSP2_BLBACK_CURVE_29_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_29_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_29_PRE_MSK (((1U << DSP2_BLBACK_CURVE_29_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_29_PRE_POS) -#define DSP2_BLBACK_CURVE_29_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_29_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_29_PRE_POS)) - -/* 0xC3C : WDR_CURVE_16 */ -#define DSP2_BLBACK_WDR_CURVE_16_OFFSET (0xC3C) -#define DSP2_BLBACK_CURVE_30_PRE DSP2_BLBACK_CURVE_30_PRE -#define DSP2_BLBACK_CURVE_30_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_30_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_30_PRE_MSK (((1U << DSP2_BLBACK_CURVE_30_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_30_PRE_POS) -#define DSP2_BLBACK_CURVE_30_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_30_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_30_PRE_POS)) -#define DSP2_BLBACK_CURVE_31_PRE DSP2_BLBACK_CURVE_31_PRE -#define DSP2_BLBACK_CURVE_31_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_31_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_31_PRE_MSK (((1U << DSP2_BLBACK_CURVE_31_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_31_PRE_POS) -#define DSP2_BLBACK_CURVE_31_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_31_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_31_PRE_POS)) - -/* 0xC40 : WDR_CURVE_17 */ -#define DSP2_BLBACK_WDR_CURVE_17_OFFSET (0xC40) -#define DSP2_BLBACK_CURVE_32_PRE DSP2_BLBACK_CURVE_32_PRE -#define DSP2_BLBACK_CURVE_32_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_32_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_32_PRE_MSK (((1U << DSP2_BLBACK_CURVE_32_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_32_PRE_POS) -#define DSP2_BLBACK_CURVE_32_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_32_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_32_PRE_POS)) -#define DSP2_BLBACK_CURVE_33_PRE DSP2_BLBACK_CURVE_33_PRE -#define DSP2_BLBACK_CURVE_33_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_33_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_33_PRE_MSK (((1U << DSP2_BLBACK_CURVE_33_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_33_PRE_POS) -#define DSP2_BLBACK_CURVE_33_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_33_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_33_PRE_POS)) - -/* 0xC44 : WDR_CURVE_18 */ -#define DSP2_BLBACK_WDR_CURVE_18_OFFSET (0xC44) -#define DSP2_BLBACK_CURVE_34_PRE DSP2_BLBACK_CURVE_34_PRE -#define DSP2_BLBACK_CURVE_34_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_34_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_34_PRE_MSK (((1U << DSP2_BLBACK_CURVE_34_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_34_PRE_POS) -#define DSP2_BLBACK_CURVE_34_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_34_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_34_PRE_POS)) -#define DSP2_BLBACK_CURVE_35_PRE DSP2_BLBACK_CURVE_35_PRE -#define DSP2_BLBACK_CURVE_35_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_35_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_35_PRE_MSK (((1U << DSP2_BLBACK_CURVE_35_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_35_PRE_POS) -#define DSP2_BLBACK_CURVE_35_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_35_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_35_PRE_POS)) - -/* 0xC48 : WDR_CURVE_19 */ -#define DSP2_BLBACK_WDR_CURVE_19_OFFSET (0xC48) -#define DSP2_BLBACK_CURVE_36_PRE DSP2_BLBACK_CURVE_36_PRE -#define DSP2_BLBACK_CURVE_36_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_36_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_36_PRE_MSK (((1U << DSP2_BLBACK_CURVE_36_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_36_PRE_POS) -#define DSP2_BLBACK_CURVE_36_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_36_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_36_PRE_POS)) -#define DSP2_BLBACK_CURVE_37_PRE DSP2_BLBACK_CURVE_37_PRE -#define DSP2_BLBACK_CURVE_37_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_37_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_37_PRE_MSK (((1U << DSP2_BLBACK_CURVE_37_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_37_PRE_POS) -#define DSP2_BLBACK_CURVE_37_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_37_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_37_PRE_POS)) - -/* 0xC4C : WDR_CURVE_20 */ -#define DSP2_BLBACK_WDR_CURVE_20_OFFSET (0xC4C) -#define DSP2_BLBACK_CURVE_38_PRE DSP2_BLBACK_CURVE_38_PRE -#define DSP2_BLBACK_CURVE_38_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_38_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_38_PRE_MSK (((1U << DSP2_BLBACK_CURVE_38_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_38_PRE_POS) -#define DSP2_BLBACK_CURVE_38_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_38_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_38_PRE_POS)) -#define DSP2_BLBACK_CURVE_39_PRE DSP2_BLBACK_CURVE_39_PRE -#define DSP2_BLBACK_CURVE_39_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_39_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_39_PRE_MSK (((1U << DSP2_BLBACK_CURVE_39_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_39_PRE_POS) -#define DSP2_BLBACK_CURVE_39_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_39_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_39_PRE_POS)) - -/* 0xC50 : WDR_CURVE_21 */ -#define DSP2_BLBACK_WDR_CURVE_21_OFFSET (0xC50) -#define DSP2_BLBACK_CURVE_40_PRE DSP2_BLBACK_CURVE_40_PRE -#define DSP2_BLBACK_CURVE_40_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_40_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_40_PRE_MSK (((1U << DSP2_BLBACK_CURVE_40_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_40_PRE_POS) -#define DSP2_BLBACK_CURVE_40_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_40_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_40_PRE_POS)) -#define DSP2_BLBACK_CURVE_41_PRE DSP2_BLBACK_CURVE_41_PRE -#define DSP2_BLBACK_CURVE_41_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_41_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_41_PRE_MSK (((1U << DSP2_BLBACK_CURVE_41_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_41_PRE_POS) -#define DSP2_BLBACK_CURVE_41_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_41_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_41_PRE_POS)) - -/* 0xC54 : WDR_CURVE_22 */ -#define DSP2_BLBACK_WDR_CURVE_22_OFFSET (0xC54) -#define DSP2_BLBACK_CURVE_42_PRE DSP2_BLBACK_CURVE_42_PRE -#define DSP2_BLBACK_CURVE_42_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_42_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_42_PRE_MSK (((1U << DSP2_BLBACK_CURVE_42_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_42_PRE_POS) -#define DSP2_BLBACK_CURVE_42_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_42_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_42_PRE_POS)) -#define DSP2_BLBACK_CURVE_43_PRE DSP2_BLBACK_CURVE_43_PRE -#define DSP2_BLBACK_CURVE_43_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_43_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_43_PRE_MSK (((1U << DSP2_BLBACK_CURVE_43_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_43_PRE_POS) -#define DSP2_BLBACK_CURVE_43_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_43_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_43_PRE_POS)) - -/* 0xC58 : WDR_CURVE_23 */ -#define DSP2_BLBACK_WDR_CURVE_23_OFFSET (0xC58) -#define DSP2_BLBACK_CURVE_44_PRE DSP2_BLBACK_CURVE_44_PRE -#define DSP2_BLBACK_CURVE_44_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_44_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_44_PRE_MSK (((1U << DSP2_BLBACK_CURVE_44_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_44_PRE_POS) -#define DSP2_BLBACK_CURVE_44_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_44_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_44_PRE_POS)) -#define DSP2_BLBACK_CURVE_45_PRE DSP2_BLBACK_CURVE_45_PRE -#define DSP2_BLBACK_CURVE_45_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_45_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_45_PRE_MSK (((1U << DSP2_BLBACK_CURVE_45_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_45_PRE_POS) -#define DSP2_BLBACK_CURVE_45_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_45_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_45_PRE_POS)) - -/* 0xC5C : WDR_CURVE_24 */ -#define DSP2_BLBACK_WDR_CURVE_24_OFFSET (0xC5C) -#define DSP2_BLBACK_CURVE_46_PRE DSP2_BLBACK_CURVE_46_PRE -#define DSP2_BLBACK_CURVE_46_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_46_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_46_PRE_MSK (((1U << DSP2_BLBACK_CURVE_46_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_46_PRE_POS) -#define DSP2_BLBACK_CURVE_46_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_46_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_46_PRE_POS)) -#define DSP2_BLBACK_CURVE_47_PRE DSP2_BLBACK_CURVE_47_PRE -#define DSP2_BLBACK_CURVE_47_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_47_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_47_PRE_MSK (((1U << DSP2_BLBACK_CURVE_47_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_47_PRE_POS) -#define DSP2_BLBACK_CURVE_47_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_47_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_47_PRE_POS)) - -/* 0xC60 : WDR_CURVE_25 */ -#define DSP2_BLBACK_WDR_CURVE_25_OFFSET (0xC60) -#define DSP2_BLBACK_CURVE_48_PRE DSP2_BLBACK_CURVE_48_PRE -#define DSP2_BLBACK_CURVE_48_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_48_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_48_PRE_MSK (((1U << DSP2_BLBACK_CURVE_48_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_48_PRE_POS) -#define DSP2_BLBACK_CURVE_48_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_48_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_48_PRE_POS)) -#define DSP2_BLBACK_CURVE_49_PRE DSP2_BLBACK_CURVE_49_PRE -#define DSP2_BLBACK_CURVE_49_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_49_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_49_PRE_MSK (((1U << DSP2_BLBACK_CURVE_49_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_49_PRE_POS) -#define DSP2_BLBACK_CURVE_49_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_49_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_49_PRE_POS)) - -/* 0xC64 : WDR_CURVE_26 */ -#define DSP2_BLBACK_WDR_CURVE_26_OFFSET (0xC64) -#define DSP2_BLBACK_CURVE_50_PRE DSP2_BLBACK_CURVE_50_PRE -#define DSP2_BLBACK_CURVE_50_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_50_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_50_PRE_MSK (((1U << DSP2_BLBACK_CURVE_50_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_50_PRE_POS) -#define DSP2_BLBACK_CURVE_50_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_50_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_50_PRE_POS)) -#define DSP2_BLBACK_CURVE_51_PRE DSP2_BLBACK_CURVE_51_PRE -#define DSP2_BLBACK_CURVE_51_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_51_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_51_PRE_MSK (((1U << DSP2_BLBACK_CURVE_51_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_51_PRE_POS) -#define DSP2_BLBACK_CURVE_51_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_51_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_51_PRE_POS)) - -/* 0xC68 : WDR_CURVE_27 */ -#define DSP2_BLBACK_WDR_CURVE_27_OFFSET (0xC68) -#define DSP2_BLBACK_CURVE_52_PRE DSP2_BLBACK_CURVE_52_PRE -#define DSP2_BLBACK_CURVE_52_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_52_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_52_PRE_MSK (((1U << DSP2_BLBACK_CURVE_52_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_52_PRE_POS) -#define DSP2_BLBACK_CURVE_52_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_52_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_52_PRE_POS)) -#define DSP2_BLBACK_CURVE_53_PRE DSP2_BLBACK_CURVE_53_PRE -#define DSP2_BLBACK_CURVE_53_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_53_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_53_PRE_MSK (((1U << DSP2_BLBACK_CURVE_53_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_53_PRE_POS) -#define DSP2_BLBACK_CURVE_53_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_53_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_53_PRE_POS)) - -/* 0xC6C : WDR_CURVE_28 */ -#define DSP2_BLBACK_WDR_CURVE_28_OFFSET (0xC6C) -#define DSP2_BLBACK_CURVE_54_PRE DSP2_BLBACK_CURVE_54_PRE -#define DSP2_BLBACK_CURVE_54_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_54_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_54_PRE_MSK (((1U << DSP2_BLBACK_CURVE_54_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_54_PRE_POS) -#define DSP2_BLBACK_CURVE_54_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_54_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_54_PRE_POS)) -#define DSP2_BLBACK_CURVE_55_PRE DSP2_BLBACK_CURVE_55_PRE -#define DSP2_BLBACK_CURVE_55_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_55_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_55_PRE_MSK (((1U << DSP2_BLBACK_CURVE_55_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_55_PRE_POS) -#define DSP2_BLBACK_CURVE_55_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_55_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_55_PRE_POS)) - -/* 0xC70 : WDR_CURVE_29 */ -#define DSP2_BLBACK_WDR_CURVE_29_OFFSET (0xC70) -#define DSP2_BLBACK_CURVE_56_PRE DSP2_BLBACK_CURVE_56_PRE -#define DSP2_BLBACK_CURVE_56_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_56_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_56_PRE_MSK (((1U << DSP2_BLBACK_CURVE_56_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_56_PRE_POS) -#define DSP2_BLBACK_CURVE_56_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_56_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_56_PRE_POS)) -#define DSP2_BLBACK_CURVE_57_PRE DSP2_BLBACK_CURVE_57_PRE -#define DSP2_BLBACK_CURVE_57_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_57_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_57_PRE_MSK (((1U << DSP2_BLBACK_CURVE_57_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_57_PRE_POS) -#define DSP2_BLBACK_CURVE_57_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_57_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_57_PRE_POS)) - -/* 0xC74 : WDR_CURVE_30 */ -#define DSP2_BLBACK_WDR_CURVE_30_OFFSET (0xC74) -#define DSP2_BLBACK_CURVE_58_PRE DSP2_BLBACK_CURVE_58_PRE -#define DSP2_BLBACK_CURVE_58_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_58_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_58_PRE_MSK (((1U << DSP2_BLBACK_CURVE_58_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_58_PRE_POS) -#define DSP2_BLBACK_CURVE_58_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_58_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_58_PRE_POS)) -#define DSP2_BLBACK_CURVE_59_PRE DSP2_BLBACK_CURVE_59_PRE -#define DSP2_BLBACK_CURVE_59_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_59_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_59_PRE_MSK (((1U << DSP2_BLBACK_CURVE_59_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_59_PRE_POS) -#define DSP2_BLBACK_CURVE_59_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_59_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_59_PRE_POS)) - -/* 0xC78 : WDR_CURVE_31 */ -#define DSP2_BLBACK_WDR_CURVE_31_OFFSET (0xC78) -#define DSP2_BLBACK_CURVE_60_PRE DSP2_BLBACK_CURVE_60_PRE -#define DSP2_BLBACK_CURVE_60_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_60_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_60_PRE_MSK (((1U << DSP2_BLBACK_CURVE_60_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_60_PRE_POS) -#define DSP2_BLBACK_CURVE_60_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_60_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_60_PRE_POS)) -#define DSP2_BLBACK_CURVE_61_PRE DSP2_BLBACK_CURVE_61_PRE -#define DSP2_BLBACK_CURVE_61_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_61_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_61_PRE_MSK (((1U << DSP2_BLBACK_CURVE_61_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_61_PRE_POS) -#define DSP2_BLBACK_CURVE_61_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_61_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_61_PRE_POS)) - -/* 0xC7C : WDR_CURVE_32 */ -#define DSP2_BLBACK_WDR_CURVE_32_OFFSET (0xC7C) -#define DSP2_BLBACK_CURVE_62_PRE DSP2_BLBACK_CURVE_62_PRE -#define DSP2_BLBACK_CURVE_62_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_62_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_62_PRE_MSK (((1U << DSP2_BLBACK_CURVE_62_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_62_PRE_POS) -#define DSP2_BLBACK_CURVE_62_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_62_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_62_PRE_POS)) -#define DSP2_BLBACK_CURVE_63_PRE DSP2_BLBACK_CURVE_63_PRE -#define DSP2_BLBACK_CURVE_63_PRE_POS (16U) -#define DSP2_BLBACK_CURVE_63_PRE_LEN (10U) -#define DSP2_BLBACK_CURVE_63_PRE_MSK (((1U << DSP2_BLBACK_CURVE_63_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_63_PRE_POS) -#define DSP2_BLBACK_CURVE_63_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_63_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_63_PRE_POS)) - -/* 0xC80 : WDR_CURVE_33 */ -#define DSP2_BLBACK_WDR_CURVE_33_OFFSET (0xC80) -#define DSP2_BLBACK_CURVE_EN_PRE DSP2_BLBACK_CURVE_EN_PRE -#define DSP2_BLBACK_CURVE_EN_PRE_POS (0U) -#define DSP2_BLBACK_CURVE_EN_PRE_LEN (1U) -#define DSP2_BLBACK_CURVE_EN_PRE_MSK (((1U << DSP2_BLBACK_CURVE_EN_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_EN_PRE_POS) -#define DSP2_BLBACK_CURVE_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_EN_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_EN_PRE_POS)) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE DSP2_BLBACK_CURVE_WEIGHT_PRE -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_CURVE_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_WEIGHT_PRE_POS) -#define DSP2_BLBACK_CURVE_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_CURVE_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_CURVE_WEIGHT_PRE_POS)) - -/* 0xC84 : WDR_ENH_1 */ -#define DSP2_BLBACK_WDR_ENH_1_OFFSET (0xC84) -#define DSP2_BLBACK_ENH_EN_PRE DSP2_BLBACK_ENH_EN_PRE -#define DSP2_BLBACK_ENH_EN_PRE_POS (0U) -#define DSP2_BLBACK_ENH_EN_PRE_LEN (1U) -#define DSP2_BLBACK_ENH_EN_PRE_MSK (((1U << DSP2_BLBACK_ENH_EN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_EN_PRE_POS) -#define DSP2_BLBACK_ENH_EN_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_EN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_EN_PRE_POS)) -#define DSP2_BLBACK_ENH_WEIGHT_PRE DSP2_BLBACK_ENH_WEIGHT_PRE -#define DSP2_BLBACK_ENH_WEIGHT_PRE_POS (8U) -#define DSP2_BLBACK_ENH_WEIGHT_PRE_LEN (5U) -#define DSP2_BLBACK_ENH_WEIGHT_PRE_MSK (((1U << DSP2_BLBACK_ENH_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_ENH_WEIGHT_PRE_POS) -#define DSP2_BLBACK_ENH_WEIGHT_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_WEIGHT_PRE_LEN) - 1) << DSP2_BLBACK_ENH_WEIGHT_PRE_POS)) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE DSP2_BLBACK_ENH_Y_OFFSET_PRE -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_POS (16U) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_LEN (12U) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_MSK (((1U << DSP2_BLBACK_ENH_Y_OFFSET_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_OFFSET_PRE_POS) -#define DSP2_BLBACK_ENH_Y_OFFSET_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_Y_OFFSET_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_OFFSET_PRE_POS)) - -/* 0xC88 : WDR_ENH_2 */ -#define DSP2_BLBACK_WDR_ENH_2_OFFSET (0xC88) -#define DSP2_BLBACK_ENH_C_GAIN_PRE DSP2_BLBACK_ENH_C_GAIN_PRE -#define DSP2_BLBACK_ENH_C_GAIN_PRE_POS (0U) -#define DSP2_BLBACK_ENH_C_GAIN_PRE_LEN (15U) -#define DSP2_BLBACK_ENH_C_GAIN_PRE_MSK (((1U << DSP2_BLBACK_ENH_C_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_C_GAIN_PRE_POS) -#define DSP2_BLBACK_ENH_C_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_C_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_C_GAIN_PRE_POS)) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE DSP2_BLBACK_ENH_Y_GAIN_PRE -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_POS (16U) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_LEN (15U) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_MSK (((1U << DSP2_BLBACK_ENH_Y_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_GAIN_PRE_POS) -#define DSP2_BLBACK_ENH_Y_GAIN_PRE_UMSK (~(((1U << DSP2_BLBACK_ENH_Y_GAIN_PRE_LEN) - 1) << DSP2_BLBACK_ENH_Y_GAIN_PRE_POS)) - -/* 0xD00 : BL_GAMMA_TABLE_1 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET (0xD00) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE DSP2_BLBACK_GAMMA_TABLE0_PRE -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE0_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE0_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE0_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE0_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE0_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE DSP2_BLBACK_GAMMA_TABLE1_PRE -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE1_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE1_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE1_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE1_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE1_PRE_POS)) - -/* 0xD04 : BL_GAMMA_TABLE_2 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_2_OFFSET (0xD04) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE DSP2_BLBACK_GAMMA_TABLE2_PRE -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE2_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE2_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE2_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE2_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE2_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE DSP2_BLBACK_GAMMA_TABLE3_PRE -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE3_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE3_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE3_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE3_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE3_PRE_POS)) - -/* 0xD08 : BL_GAMMA_TABLE_3 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_3_OFFSET (0xD08) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE DSP2_BLBACK_GAMMA_TABLE4_PRE -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE4_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE4_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE4_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE4_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE4_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE DSP2_BLBACK_GAMMA_TABLE5_PRE -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE5_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE5_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE5_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE5_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE5_PRE_POS)) - -/* 0xD0C : BL_GAMMA_TABLE_4 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_4_OFFSET (0xD0C) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE DSP2_BLBACK_GAMMA_TABLE6_PRE -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE6_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE6_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE6_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE6_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE6_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE DSP2_BLBACK_GAMMA_TABLE7_PRE -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE7_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE7_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE7_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE7_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE7_PRE_POS)) - -/* 0xD10 : BL_GAMMA_TABLE_5 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_5_OFFSET (0xD10) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE DSP2_BLBACK_GAMMA_TABLE8_PRE -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE8_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE8_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE8_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE8_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE8_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE DSP2_BLBACK_GAMMA_TABLE9_PRE -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE9_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE9_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE9_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE9_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE9_PRE_POS)) - -/* 0xD14 : BL_GAMMA_TABLE_6 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_6_OFFSET (0xD14) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE DSP2_BLBACK_GAMMA_TABLE10_PRE -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE10_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE10_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE10_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE10_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE10_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE DSP2_BLBACK_GAMMA_TABLE11_PRE -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE11_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE11_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE11_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE11_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE11_PRE_POS)) - -/* 0xD18 : BL_GAMMA_TABLE_7 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_7_OFFSET (0xD18) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE DSP2_BLBACK_GAMMA_TABLE12_PRE -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE12_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE12_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE12_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE12_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE12_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE DSP2_BLBACK_GAMMA_TABLE13_PRE -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE13_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE13_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE13_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE13_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE13_PRE_POS)) - -/* 0xD1C : BL_GAMMA_TABLE_8 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_8_OFFSET (0xD1C) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE DSP2_BLBACK_GAMMA_TABLE14_PRE -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE14_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE14_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE14_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE14_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE14_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE DSP2_BLBACK_GAMMA_TABLE15_PRE -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE15_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE15_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE15_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE15_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE15_PRE_POS)) - -/* 0xD20 : BL_GAMMA_TABLE_9 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_9_OFFSET (0xD20) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE DSP2_BLBACK_GAMMA_TABLE16_PRE -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE16_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE16_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE16_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE16_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE16_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE DSP2_BLBACK_GAMMA_TABLE17_PRE -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE17_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE17_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE17_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE17_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE17_PRE_POS)) - -/* 0xD24 : BL_GAMMA_TABLE_10 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_10_OFFSET (0xD24) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE DSP2_BLBACK_GAMMA_TABLE18_PRE -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE18_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE18_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE18_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE18_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE18_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE DSP2_BLBACK_GAMMA_TABLE19_PRE -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE19_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE19_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE19_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE19_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE19_PRE_POS)) - -/* 0xD28 : BL_GAMMA_TABLE_11 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_11_OFFSET (0xD28) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE DSP2_BLBACK_GAMMA_TABLE20_PRE -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE20_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE20_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE20_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE20_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE20_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE DSP2_BLBACK_GAMMA_TABLE21_PRE -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE21_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE21_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE21_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE21_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE21_PRE_POS)) - -/* 0xD2C : BL_GAMMA_TABLE_12 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_12_OFFSET (0xD2C) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE DSP2_BLBACK_GAMMA_TABLE22_PRE -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE22_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE22_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE22_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE22_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE22_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE DSP2_BLBACK_GAMMA_TABLE23_PRE -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE23_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE23_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE23_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE23_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE23_PRE_POS)) - -/* 0xD30 : BL_GAMMA_TABLE_13 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_13_OFFSET (0xD30) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE DSP2_BLBACK_GAMMA_TABLE24_PRE -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE24_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE24_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE24_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE24_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE24_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE DSP2_BLBACK_GAMMA_TABLE25_PRE -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE25_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE25_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE25_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE25_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE25_PRE_POS)) - -/* 0xD34 : BL_GAMMA_TABLE_14 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_14_OFFSET (0xD34) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE DSP2_BLBACK_GAMMA_TABLE26_PRE -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE26_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE26_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE26_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE26_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE26_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE DSP2_BLBACK_GAMMA_TABLE27_PRE -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE27_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE27_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE27_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE27_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE27_PRE_POS)) - -/* 0xD38 : BL_GAMMA_TABLE_15 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_15_OFFSET (0xD38) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE DSP2_BLBACK_GAMMA_TABLE28_PRE -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE28_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE28_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE28_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE28_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE28_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE DSP2_BLBACK_GAMMA_TABLE29_PRE -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE29_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE29_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE29_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE29_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE29_PRE_POS)) - -/* 0xD3C : BL_GAMMA_TABLE_16 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_16_OFFSET (0xD3C) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE DSP2_BLBACK_GAMMA_TABLE30_PRE -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE30_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE30_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE30_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE30_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE30_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE DSP2_BLBACK_GAMMA_TABLE31_PRE -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE31_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE31_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE31_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE31_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE31_PRE_POS)) - -/* 0xD40 : BL_GAMMA_TABLE_17 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_17_OFFSET (0xD40) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE DSP2_BLBACK_GAMMA_TABLE32_PRE -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE32_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE32_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE32_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE32_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE32_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE DSP2_BLBACK_GAMMA_TABLE33_PRE -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE33_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE33_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE33_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE33_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE33_PRE_POS)) - -/* 0xD44 : BL_GAMMA_TABLE_18 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_18_OFFSET (0xD44) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE DSP2_BLBACK_GAMMA_TABLE34_PRE -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE34_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE34_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE34_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE34_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE34_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE DSP2_BLBACK_GAMMA_TABLE35_PRE -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE35_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE35_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE35_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE35_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE35_PRE_POS)) - -/* 0xD48 : BL_GAMMA_TABLE_19 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_19_OFFSET (0xD48) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE DSP2_BLBACK_GAMMA_TABLE36_PRE -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE36_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE36_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE36_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE36_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE36_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE DSP2_BLBACK_GAMMA_TABLE37_PRE -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE37_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE37_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE37_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE37_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE37_PRE_POS)) - -/* 0xD4C : BL_GAMMA_TABLE_20 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_20_OFFSET (0xD4C) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE DSP2_BLBACK_GAMMA_TABLE38_PRE -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE38_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE38_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE38_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE38_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE38_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE DSP2_BLBACK_GAMMA_TABLE39_PRE -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE39_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE39_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE39_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE39_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE39_PRE_POS)) - -/* 0xD50 : BL_GAMMA_TABLE_21 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_21_OFFSET (0xD50) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE DSP2_BLBACK_GAMMA_TABLE40_PRE -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE40_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE40_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE40_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE40_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE40_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE DSP2_BLBACK_GAMMA_TABLE41_PRE -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE41_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE41_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE41_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE41_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE41_PRE_POS)) - -/* 0xD54 : BL_GAMMA_TABLE_22 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_22_OFFSET (0xD54) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE DSP2_BLBACK_GAMMA_TABLE42_PRE -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE42_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE42_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE42_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE42_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE42_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE DSP2_BLBACK_GAMMA_TABLE43_PRE -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE43_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE43_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE43_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE43_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE43_PRE_POS)) - -/* 0xD58 : BL_GAMMA_TABLE_23 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_23_OFFSET (0xD58) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE DSP2_BLBACK_GAMMA_TABLE44_PRE -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE44_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE44_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE44_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE44_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE44_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE DSP2_BLBACK_GAMMA_TABLE45_PRE -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE45_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE45_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE45_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE45_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE45_PRE_POS)) - -/* 0xD5C : BL_GAMMA_TABLE_24 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_24_OFFSET (0xD5C) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE DSP2_BLBACK_GAMMA_TABLE46_PRE -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE46_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE46_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE46_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE46_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE46_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE DSP2_BLBACK_GAMMA_TABLE47_PRE -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE47_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE47_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE47_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE47_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE47_PRE_POS)) - -/* 0xD60 : BL_GAMMA_TABLE_25 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_25_OFFSET (0xD60) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE DSP2_BLBACK_GAMMA_TABLE48_PRE -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE48_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE48_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE48_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE48_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE48_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE DSP2_BLBACK_GAMMA_TABLE49_PRE -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE49_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE49_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE49_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE49_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE49_PRE_POS)) - -/* 0xD64 : BL_GAMMA_TABLE_26 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_26_OFFSET (0xD64) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE DSP2_BLBACK_GAMMA_TABLE50_PRE -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE50_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE50_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE50_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE50_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE50_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE DSP2_BLBACK_GAMMA_TABLE51_PRE -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE51_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE51_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE51_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE51_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE51_PRE_POS)) - -/* 0xD68 : BL_GAMMA_TABLE_27 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_27_OFFSET (0xD68) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE DSP2_BLBACK_GAMMA_TABLE52_PRE -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE52_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE52_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE52_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE52_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE52_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE DSP2_BLBACK_GAMMA_TABLE53_PRE -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE53_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE53_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE53_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE53_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE53_PRE_POS)) - -/* 0xD6C : BL_GAMMA_TABLE_28 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_28_OFFSET (0xD6C) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE DSP2_BLBACK_GAMMA_TABLE54_PRE -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE54_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE54_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE54_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE54_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE54_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE DSP2_BLBACK_GAMMA_TABLE55_PRE -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE55_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE55_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE55_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE55_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE55_PRE_POS)) - -/* 0xD70 : BL_GAMMA_TABLE_29 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_29_OFFSET (0xD70) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE DSP2_BLBACK_GAMMA_TABLE56_PRE -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE56_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE56_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE56_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE56_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE56_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE DSP2_BLBACK_GAMMA_TABLE57_PRE -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE57_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE57_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE57_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE57_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE57_PRE_POS)) - -/* 0xD74 : BL_GAMMA_TABLE_30 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_30_OFFSET (0xD74) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE DSP2_BLBACK_GAMMA_TABLE58_PRE -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE58_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE58_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE58_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE58_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE58_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE DSP2_BLBACK_GAMMA_TABLE59_PRE -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE59_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE59_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE59_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE59_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE59_PRE_POS)) - -/* 0xD78 : BL_GAMMA_TABLE_31 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_31_OFFSET (0xD78) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE DSP2_BLBACK_GAMMA_TABLE60_PRE -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE60_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE60_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE60_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE60_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE60_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE DSP2_BLBACK_GAMMA_TABLE61_PRE -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE61_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE61_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE61_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE61_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE61_PRE_POS)) - -/* 0xD7C : BL_GAMMA_TABLE_32 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_32_OFFSET (0xD7C) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE DSP2_BLBACK_GAMMA_TABLE62_PRE -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE62_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE62_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE62_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE62_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE62_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE DSP2_BLBACK_GAMMA_TABLE63_PRE -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE63_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE63_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE63_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE63_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE63_PRE_POS)) - -/* 0xD80 : BL_GAMMA_TABLE_33 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_33_OFFSET (0xD80) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE DSP2_BLBACK_GAMMA_TABLE64_PRE -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE64_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE64_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE64_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE64_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE64_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE DSP2_BLBACK_GAMMA_TABLE65_PRE -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE65_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE65_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE65_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE65_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE65_PRE_POS)) - -/* 0xD84 : BL_GAMMA_TABLE_34 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_34_OFFSET (0xD84) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE DSP2_BLBACK_GAMMA_TABLE66_PRE -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE66_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE66_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE66_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE66_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE66_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE DSP2_BLBACK_GAMMA_TABLE67_PRE -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE67_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE67_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE67_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE67_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE67_PRE_POS)) - -/* 0xD88 : BL_GAMMA_TABLE_35 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_35_OFFSET (0xD88) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE DSP2_BLBACK_GAMMA_TABLE68_PRE -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE68_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE68_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE68_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE68_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE68_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE DSP2_BLBACK_GAMMA_TABLE69_PRE -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE69_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE69_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE69_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE69_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE69_PRE_POS)) - -/* 0xD8C : BL_GAMMA_TABLE_36 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_36_OFFSET (0xD8C) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE DSP2_BLBACK_GAMMA_TABLE70_PRE -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE70_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE70_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE70_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE70_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE70_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE DSP2_BLBACK_GAMMA_TABLE71_PRE -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE71_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE71_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE71_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE71_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE71_PRE_POS)) - -/* 0xD90 : BL_GAMMA_TABLE_37 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_37_OFFSET (0xD90) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE DSP2_BLBACK_GAMMA_TABLE72_PRE -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE72_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE72_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE72_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE72_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE72_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE DSP2_BLBACK_GAMMA_TABLE73_PRE -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE73_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE73_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE73_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE73_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE73_PRE_POS)) - -/* 0xD94 : BL_GAMMA_TABLE_38 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_38_OFFSET (0xD94) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE DSP2_BLBACK_GAMMA_TABLE74_PRE -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE74_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE74_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE74_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE74_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE74_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE DSP2_BLBACK_GAMMA_TABLE75_PRE -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE75_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE75_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE75_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE75_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE75_PRE_POS)) - -/* 0xD98 : BL_GAMMA_TABLE_39 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_39_OFFSET (0xD98) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE DSP2_BLBACK_GAMMA_TABLE76_PRE -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE76_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE76_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE76_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE76_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE76_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE DSP2_BLBACK_GAMMA_TABLE77_PRE -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE77_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE77_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE77_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE77_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE77_PRE_POS)) - -/* 0xD9C : BL_GAMMA_TABLE_40 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_40_OFFSET (0xD9C) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE DSP2_BLBACK_GAMMA_TABLE78_PRE -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE78_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE78_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE78_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE78_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE78_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE DSP2_BLBACK_GAMMA_TABLE79_PRE -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE79_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE79_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE79_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE79_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE79_PRE_POS)) - -/* 0xDA0 : BL_GAMMA_TABLE_41 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_41_OFFSET (0xDA0) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE DSP2_BLBACK_GAMMA_TABLE80_PRE -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE80_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE80_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE80_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE80_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE80_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE DSP2_BLBACK_GAMMA_TABLE81_PRE -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE81_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE81_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE81_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE81_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE81_PRE_POS)) - -/* 0xDA4 : BL_GAMMA_TABLE_42 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_42_OFFSET (0xDA4) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE DSP2_BLBACK_GAMMA_TABLE82_PRE -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE82_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE82_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE82_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE82_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE82_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE DSP2_BLBACK_GAMMA_TABLE83_PRE -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE83_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE83_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE83_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE83_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE83_PRE_POS)) - -/* 0xDA8 : BL_GAMMA_TABLE_43 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_43_OFFSET (0xDA8) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE DSP2_BLBACK_GAMMA_TABLE84_PRE -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE84_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE84_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE84_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE84_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE84_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE DSP2_BLBACK_GAMMA_TABLE85_PRE -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE85_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE85_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE85_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE85_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE85_PRE_POS)) - -/* 0xDAC : BL_GAMMA_TABLE_44 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_44_OFFSET (0xDAC) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE DSP2_BLBACK_GAMMA_TABLE86_PRE -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE86_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE86_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE86_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE86_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE86_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE DSP2_BLBACK_GAMMA_TABLE87_PRE -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE87_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE87_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE87_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE87_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE87_PRE_POS)) - -/* 0xDB0 : BL_GAMMA_TABLE_45 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_45_OFFSET (0xDB0) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE DSP2_BLBACK_GAMMA_TABLE88_PRE -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE88_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE88_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE88_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE88_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE88_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE DSP2_BLBACK_GAMMA_TABLE89_PRE -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE89_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE89_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE89_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE89_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE89_PRE_POS)) - -/* 0xDB4 : BL_GAMMA_TABLE_46 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_46_OFFSET (0xDB4) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE DSP2_BLBACK_GAMMA_TABLE90_PRE -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE90_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE90_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE90_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE90_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE90_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE DSP2_BLBACK_GAMMA_TABLE91_PRE -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE91_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE91_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE91_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE91_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE91_PRE_POS)) - -/* 0xDB8 : BL_GAMMA_TABLE_47 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_47_OFFSET (0xDB8) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE DSP2_BLBACK_GAMMA_TABLE92_PRE -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE92_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE92_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE92_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE92_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE92_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE DSP2_BLBACK_GAMMA_TABLE93_PRE -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE93_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE93_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE93_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE93_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE93_PRE_POS)) - -/* 0xDBC : BL_GAMMA_TABLE_48 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_48_OFFSET (0xDBC) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE DSP2_BLBACK_GAMMA_TABLE94_PRE -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE94_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE94_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE94_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE94_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE94_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE DSP2_BLBACK_GAMMA_TABLE95_PRE -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE95_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE95_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE95_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE95_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE95_PRE_POS)) - -/* 0xDC0 : BL_GAMMA_TABLE_49 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_49_OFFSET (0xDC0) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE DSP2_BLBACK_GAMMA_TABLE96_PRE -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE96_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE96_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE96_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE96_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE96_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE DSP2_BLBACK_GAMMA_TABLE97_PRE -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE97_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE97_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE97_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE97_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE97_PRE_POS)) - -/* 0xDC4 : BL_GAMMA_TABLE_50 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_50_OFFSET (0xDC4) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE DSP2_BLBACK_GAMMA_TABLE98_PRE -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE98_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE98_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE98_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE98_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE98_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE DSP2_BLBACK_GAMMA_TABLE99_PRE -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE99_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE99_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE99_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE99_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE99_PRE_POS)) - -/* 0xDC8 : BL_GAMMA_TABLE_51 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_51_OFFSET (0xDC8) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE DSP2_BLBACK_GAMMA_TABLE100_PRE -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE100_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE100_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE100_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE100_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE100_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE DSP2_BLBACK_GAMMA_TABLE101_PRE -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE101_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE101_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE101_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE101_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE101_PRE_POS)) - -/* 0xDCC : BL_GAMMA_TABLE_52 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_52_OFFSET (0xDCC) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE DSP2_BLBACK_GAMMA_TABLE102_PRE -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE102_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE102_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE102_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE102_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE102_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE DSP2_BLBACK_GAMMA_TABLE103_PRE -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE103_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE103_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE103_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE103_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE103_PRE_POS)) - -/* 0xDD0 : BL_GAMMA_TABLE_53 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_53_OFFSET (0xDD0) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE DSP2_BLBACK_GAMMA_TABLE104_PRE -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE104_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE104_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE104_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE104_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE104_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE DSP2_BLBACK_GAMMA_TABLE105_PRE -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE105_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE105_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE105_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE105_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE105_PRE_POS)) - -/* 0xDD4 : BL_GAMMA_TABLE_54 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_54_OFFSET (0xDD4) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE DSP2_BLBACK_GAMMA_TABLE106_PRE -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE106_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE106_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE106_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE106_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE106_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE DSP2_BLBACK_GAMMA_TABLE107_PRE -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE107_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE107_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE107_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE107_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE107_PRE_POS)) - -/* 0xDD8 : BL_GAMMA_TABLE_55 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_55_OFFSET (0xDD8) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE DSP2_BLBACK_GAMMA_TABLE108_PRE -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE108_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE108_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE108_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE108_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE108_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE DSP2_BLBACK_GAMMA_TABLE109_PRE -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE109_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE109_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE109_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE109_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE109_PRE_POS)) - -/* 0xDDC : BL_GAMMA_TABLE_56 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_56_OFFSET (0xDDC) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE DSP2_BLBACK_GAMMA_TABLE110_PRE -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE110_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE110_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE110_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE110_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE110_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE DSP2_BLBACK_GAMMA_TABLE111_PRE -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE111_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE111_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE111_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE111_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE111_PRE_POS)) - -/* 0xDE0 : BL_GAMMA_TABLE_57 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_57_OFFSET (0xDE0) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE DSP2_BLBACK_GAMMA_TABLE112_PRE -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE112_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE112_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE112_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE112_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE112_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE DSP2_BLBACK_GAMMA_TABLE113_PRE -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE113_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE113_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE113_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE113_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE113_PRE_POS)) - -/* 0xDE4 : BL_GAMMA_TABLE_58 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_58_OFFSET (0xDE4) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE DSP2_BLBACK_GAMMA_TABLE114_PRE -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE114_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE114_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE114_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE114_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE114_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE DSP2_BLBACK_GAMMA_TABLE115_PRE -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE115_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE115_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE115_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE115_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE115_PRE_POS)) - -/* 0xDE8 : BL_GAMMA_TABLE_59 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_59_OFFSET (0xDE8) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE DSP2_BLBACK_GAMMA_TABLE116_PRE -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE116_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE116_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE116_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE116_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE116_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE DSP2_BLBACK_GAMMA_TABLE117_PRE -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE117_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE117_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE117_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE117_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE117_PRE_POS)) - -/* 0xDEC : BL_GAMMA_TABLE_60 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_60_OFFSET (0xDEC) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE DSP2_BLBACK_GAMMA_TABLE118_PRE -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE118_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE118_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE118_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE118_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE118_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE DSP2_BLBACK_GAMMA_TABLE119_PRE -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE119_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE119_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE119_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE119_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE119_PRE_POS)) - -/* 0xDF0 : BL_GAMMA_TABLE_61 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_61_OFFSET (0xDF0) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE DSP2_BLBACK_GAMMA_TABLE120_PRE -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE120_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE120_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE120_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE120_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE120_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE DSP2_BLBACK_GAMMA_TABLE121_PRE -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE121_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE121_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE121_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE121_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE121_PRE_POS)) - -/* 0xDF4 : BL_GAMMA_TABLE_62 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_62_OFFSET (0xDF4) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE DSP2_BLBACK_GAMMA_TABLE122_PRE -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE122_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE122_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE122_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE122_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE122_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE DSP2_BLBACK_GAMMA_TABLE123_PRE -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE123_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE123_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE123_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE123_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE123_PRE_POS)) - -/* 0xDF8 : BL_GAMMA_TABLE_63 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_63_OFFSET (0xDF8) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE DSP2_BLBACK_GAMMA_TABLE124_PRE -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE124_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE124_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE124_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE124_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE124_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE DSP2_BLBACK_GAMMA_TABLE125_PRE -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE125_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE125_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE125_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE125_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE125_PRE_POS)) - -/* 0xDFC : BL_GAMMA_TABLE_64 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_64_OFFSET (0xDFC) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE DSP2_BLBACK_GAMMA_TABLE126_PRE -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE126_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE126_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE126_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE126_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE126_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE DSP2_BLBACK_GAMMA_TABLE127_PRE -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE127_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE127_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE127_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE127_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE127_PRE_POS)) - -/* 0xE00 : BL_GAMMA_TABLE_65 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_65_OFFSET (0xE00) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE DSP2_BLBACK_GAMMA_TABLE128_PRE -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE128_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE128_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE128_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE128_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE128_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE DSP2_BLBACK_GAMMA_TABLE129_PRE -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE129_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE129_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE129_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE129_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE129_PRE_POS)) - -/* 0xE04 : BL_GAMMA_TABLE_66 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_66_OFFSET (0xE04) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE DSP2_BLBACK_GAMMA_TABLE130_PRE -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE130_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE130_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE130_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE130_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE130_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE DSP2_BLBACK_GAMMA_TABLE131_PRE -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE131_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE131_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE131_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE131_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE131_PRE_POS)) - -/* 0xE08 : BL_GAMMA_TABLE_67 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_67_OFFSET (0xE08) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE DSP2_BLBACK_GAMMA_TABLE132_PRE -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE132_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE132_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE132_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE132_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE132_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE DSP2_BLBACK_GAMMA_TABLE133_PRE -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE133_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE133_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE133_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE133_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE133_PRE_POS)) - -/* 0xE0C : BL_GAMMA_TABLE_68 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_68_OFFSET (0xE0C) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE DSP2_BLBACK_GAMMA_TABLE134_PRE -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE134_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE134_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE134_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE134_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE134_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE DSP2_BLBACK_GAMMA_TABLE135_PRE -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE135_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE135_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE135_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE135_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE135_PRE_POS)) - -/* 0xE10 : BL_GAMMA_TABLE_69 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_69_OFFSET (0xE10) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE DSP2_BLBACK_GAMMA_TABLE136_PRE -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE136_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE136_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE136_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE136_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE136_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE DSP2_BLBACK_GAMMA_TABLE137_PRE -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE137_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE137_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE137_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE137_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE137_PRE_POS)) - -/* 0xE14 : BL_GAMMA_TABLE_70 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_70_OFFSET (0xE14) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE DSP2_BLBACK_GAMMA_TABLE138_PRE -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE138_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE138_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE138_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE138_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE138_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE DSP2_BLBACK_GAMMA_TABLE139_PRE -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE139_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE139_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE139_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE139_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE139_PRE_POS)) - -/* 0xE18 : BL_GAMMA_TABLE_71 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_71_OFFSET (0xE18) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE DSP2_BLBACK_GAMMA_TABLE140_PRE -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE140_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE140_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE140_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE140_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE140_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE DSP2_BLBACK_GAMMA_TABLE141_PRE -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE141_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE141_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE141_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE141_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE141_PRE_POS)) - -/* 0xE1C : BL_GAMMA_TABLE_72 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_72_OFFSET (0xE1C) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE DSP2_BLBACK_GAMMA_TABLE142_PRE -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE142_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE142_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE142_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE142_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE142_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE DSP2_BLBACK_GAMMA_TABLE143_PRE -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE143_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE143_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE143_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE143_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE143_PRE_POS)) - -/* 0xE20 : BL_GAMMA_TABLE_73 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_73_OFFSET (0xE20) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE DSP2_BLBACK_GAMMA_TABLE144_PRE -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE144_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE144_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE144_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE144_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE144_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE DSP2_BLBACK_GAMMA_TABLE145_PRE -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE145_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE145_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE145_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE145_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE145_PRE_POS)) - -/* 0xE24 : BL_GAMMA_TABLE_74 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_74_OFFSET (0xE24) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE DSP2_BLBACK_GAMMA_TABLE146_PRE -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE146_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE146_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE146_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE146_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE146_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE DSP2_BLBACK_GAMMA_TABLE147_PRE -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE147_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE147_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE147_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE147_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE147_PRE_POS)) - -/* 0xE28 : BL_GAMMA_TABLE_75 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_75_OFFSET (0xE28) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE DSP2_BLBACK_GAMMA_TABLE148_PRE -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE148_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE148_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE148_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE148_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE148_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE DSP2_BLBACK_GAMMA_TABLE149_PRE -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE149_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE149_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE149_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE149_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE149_PRE_POS)) - -/* 0xE2C : BL_GAMMA_TABLE_76 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_76_OFFSET (0xE2C) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE DSP2_BLBACK_GAMMA_TABLE150_PRE -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE150_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE150_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE150_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE150_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE150_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE DSP2_BLBACK_GAMMA_TABLE151_PRE -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE151_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE151_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE151_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE151_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE151_PRE_POS)) - -/* 0xE30 : BL_GAMMA_TABLE_77 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_77_OFFSET (0xE30) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE DSP2_BLBACK_GAMMA_TABLE152_PRE -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE152_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE152_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE152_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE152_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE152_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE DSP2_BLBACK_GAMMA_TABLE153_PRE -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE153_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE153_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE153_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE153_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE153_PRE_POS)) - -/* 0xE34 : BL_GAMMA_TABLE_78 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_78_OFFSET (0xE34) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE DSP2_BLBACK_GAMMA_TABLE154_PRE -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE154_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE154_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE154_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE154_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE154_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE DSP2_BLBACK_GAMMA_TABLE155_PRE -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE155_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE155_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE155_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE155_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE155_PRE_POS)) - -/* 0xE38 : BL_GAMMA_TABLE_79 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_79_OFFSET (0xE38) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE DSP2_BLBACK_GAMMA_TABLE156_PRE -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE156_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE156_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE156_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE156_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE156_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE DSP2_BLBACK_GAMMA_TABLE157_PRE -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE157_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE157_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE157_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE157_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE157_PRE_POS)) - -/* 0xE3C : BL_GAMMA_TABLE_80 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_80_OFFSET (0xE3C) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE DSP2_BLBACK_GAMMA_TABLE158_PRE -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE158_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE158_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE158_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE158_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE158_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE DSP2_BLBACK_GAMMA_TABLE159_PRE -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE159_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE159_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE159_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE159_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE159_PRE_POS)) - -/* 0xE40 : BL_GAMMA_TABLE_81 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_81_OFFSET (0xE40) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE DSP2_BLBACK_GAMMA_TABLE160_PRE -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE160_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE160_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE160_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE160_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE160_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE DSP2_BLBACK_GAMMA_TABLE161_PRE -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE161_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE161_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE161_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE161_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE161_PRE_POS)) - -/* 0xE44 : BL_GAMMA_TABLE_82 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_82_OFFSET (0xE44) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE DSP2_BLBACK_GAMMA_TABLE162_PRE -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE162_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE162_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE162_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE162_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE162_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE DSP2_BLBACK_GAMMA_TABLE163_PRE -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE163_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE163_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE163_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE163_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE163_PRE_POS)) - -/* 0xE48 : BL_GAMMA_TABLE_83 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_83_OFFSET (0xE48) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE DSP2_BLBACK_GAMMA_TABLE164_PRE -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE164_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE164_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE164_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE164_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE164_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE DSP2_BLBACK_GAMMA_TABLE165_PRE -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE165_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE165_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE165_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE165_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE165_PRE_POS)) - -/* 0xE4C : BL_GAMMA_TABLE_84 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_84_OFFSET (0xE4C) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE DSP2_BLBACK_GAMMA_TABLE166_PRE -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE166_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE166_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE166_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE166_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE166_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE DSP2_BLBACK_GAMMA_TABLE167_PRE -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE167_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE167_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE167_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE167_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE167_PRE_POS)) - -/* 0xE50 : BL_GAMMA_TABLE_85 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_85_OFFSET (0xE50) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE DSP2_BLBACK_GAMMA_TABLE168_PRE -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE168_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE168_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE168_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE168_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE168_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE DSP2_BLBACK_GAMMA_TABLE169_PRE -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE169_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE169_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE169_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE169_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE169_PRE_POS)) - -/* 0xE54 : BL_GAMMA_TABLE_86 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_86_OFFSET (0xE54) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE DSP2_BLBACK_GAMMA_TABLE170_PRE -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE170_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE170_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE170_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE170_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE170_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE DSP2_BLBACK_GAMMA_TABLE171_PRE -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE171_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE171_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE171_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE171_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE171_PRE_POS)) - -/* 0xE58 : BL_GAMMA_TABLE_87 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_87_OFFSET (0xE58) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE DSP2_BLBACK_GAMMA_TABLE172_PRE -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE172_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE172_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE172_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE172_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE172_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE DSP2_BLBACK_GAMMA_TABLE173_PRE -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE173_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE173_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE173_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE173_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE173_PRE_POS)) - -/* 0xE5C : BL_GAMMA_TABLE_88 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_88_OFFSET (0xE5C) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE DSP2_BLBACK_GAMMA_TABLE174_PRE -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE174_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE174_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE174_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE174_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE174_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE DSP2_BLBACK_GAMMA_TABLE175_PRE -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE175_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE175_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE175_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE175_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE175_PRE_POS)) - -/* 0xE60 : BL_GAMMA_TABLE_89 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_89_OFFSET (0xE60) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE DSP2_BLBACK_GAMMA_TABLE176_PRE -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE176_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE176_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE176_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE176_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE176_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE DSP2_BLBACK_GAMMA_TABLE177_PRE -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE177_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE177_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE177_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE177_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE177_PRE_POS)) - -/* 0xE64 : BL_GAMMA_TABLE_90 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_90_OFFSET (0xE64) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE DSP2_BLBACK_GAMMA_TABLE178_PRE -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE178_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE178_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE178_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE178_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE178_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE DSP2_BLBACK_GAMMA_TABLE179_PRE -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE179_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE179_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE179_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE179_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE179_PRE_POS)) - -/* 0xE68 : BL_GAMMA_TABLE_91 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_91_OFFSET (0xE68) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE DSP2_BLBACK_GAMMA_TABLE180_PRE -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE180_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE180_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE180_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE180_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE180_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE DSP2_BLBACK_GAMMA_TABLE181_PRE -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE181_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE181_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE181_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE181_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE181_PRE_POS)) - -/* 0xE6C : BL_GAMMA_TABLE_92 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_92_OFFSET (0xE6C) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE DSP2_BLBACK_GAMMA_TABLE182_PRE -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE182_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE182_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE182_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE182_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE182_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE DSP2_BLBACK_GAMMA_TABLE183_PRE -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE183_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE183_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE183_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE183_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE183_PRE_POS)) - -/* 0xE70 : BL_GAMMA_TABLE_93 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_93_OFFSET (0xE70) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE DSP2_BLBACK_GAMMA_TABLE184_PRE -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE184_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE184_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE184_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE184_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE184_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE DSP2_BLBACK_GAMMA_TABLE185_PRE -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE185_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE185_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE185_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE185_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE185_PRE_POS)) - -/* 0xE74 : BL_GAMMA_TABLE_94 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_94_OFFSET (0xE74) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE DSP2_BLBACK_GAMMA_TABLE186_PRE -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE186_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE186_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE186_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE186_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE186_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE DSP2_BLBACK_GAMMA_TABLE187_PRE -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE187_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE187_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE187_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE187_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE187_PRE_POS)) - -/* 0xE78 : BL_GAMMA_TABLE_95 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_95_OFFSET (0xE78) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE DSP2_BLBACK_GAMMA_TABLE188_PRE -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE188_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE188_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE188_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE188_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE188_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE DSP2_BLBACK_GAMMA_TABLE189_PRE -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE189_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE189_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE189_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE189_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE189_PRE_POS)) - -/* 0xE7C : BL_GAMMA_TABLE_96 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_96_OFFSET (0xE7C) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE DSP2_BLBACK_GAMMA_TABLE190_PRE -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE190_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE190_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE190_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE190_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE190_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE DSP2_BLBACK_GAMMA_TABLE191_PRE -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE191_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE191_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE191_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE191_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE191_PRE_POS)) - -/* 0xE80 : BL_GAMMA_TABLE_97 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_97_OFFSET (0xE80) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE DSP2_BLBACK_GAMMA_TABLE192_PRE -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE192_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE192_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE192_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE192_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE192_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE DSP2_BLBACK_GAMMA_TABLE193_PRE -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE193_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE193_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE193_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE193_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE193_PRE_POS)) - -/* 0xE84 : BL_GAMMA_TABLE_98 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_98_OFFSET (0xE84) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE DSP2_BLBACK_GAMMA_TABLE194_PRE -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE194_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE194_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE194_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE194_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE194_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE DSP2_BLBACK_GAMMA_TABLE195_PRE -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE195_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE195_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE195_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE195_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE195_PRE_POS)) - -/* 0xE88 : BL_GAMMA_TABLE_99 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_99_OFFSET (0xE88) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE DSP2_BLBACK_GAMMA_TABLE196_PRE -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE196_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE196_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE196_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE196_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE196_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE DSP2_BLBACK_GAMMA_TABLE197_PRE -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE197_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE197_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE197_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE197_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE197_PRE_POS)) - -/* 0xE8C : BL_GAMMA_TABLE_100 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_100_OFFSET (0xE8C) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE DSP2_BLBACK_GAMMA_TABLE198_PRE -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE198_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE198_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE198_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE198_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE198_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE DSP2_BLBACK_GAMMA_TABLE199_PRE -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE199_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE199_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE199_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE199_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE199_PRE_POS)) - -/* 0xE90 : BL_GAMMA_TABLE_101 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_101_OFFSET (0xE90) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE DSP2_BLBACK_GAMMA_TABLE200_PRE -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE200_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE200_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE200_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE200_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE200_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE DSP2_BLBACK_GAMMA_TABLE201_PRE -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE201_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE201_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE201_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE201_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE201_PRE_POS)) - -/* 0xE94 : BL_GAMMA_TABLE_102 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_102_OFFSET (0xE94) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE DSP2_BLBACK_GAMMA_TABLE202_PRE -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE202_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE202_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE202_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE202_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE202_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE DSP2_BLBACK_GAMMA_TABLE203_PRE -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE203_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE203_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE203_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE203_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE203_PRE_POS)) - -/* 0xE98 : BL_GAMMA_TABLE_103 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_103_OFFSET (0xE98) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE DSP2_BLBACK_GAMMA_TABLE204_PRE -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE204_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE204_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE204_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE204_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE204_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE DSP2_BLBACK_GAMMA_TABLE205_PRE -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE205_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE205_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE205_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE205_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE205_PRE_POS)) - -/* 0xE9C : BL_GAMMA_TABLE_104 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_104_OFFSET (0xE9C) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE DSP2_BLBACK_GAMMA_TABLE206_PRE -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE206_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE206_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE206_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE206_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE206_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE DSP2_BLBACK_GAMMA_TABLE207_PRE -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE207_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE207_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE207_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE207_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE207_PRE_POS)) - -/* 0xEA0 : BL_GAMMA_TABLE_105 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_105_OFFSET (0xEA0) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE DSP2_BLBACK_GAMMA_TABLE208_PRE -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE208_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE208_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE208_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE208_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE208_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE DSP2_BLBACK_GAMMA_TABLE209_PRE -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE209_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE209_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE209_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE209_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE209_PRE_POS)) - -/* 0xEA4 : BL_GAMMA_TABLE_106 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_106_OFFSET (0xEA4) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE DSP2_BLBACK_GAMMA_TABLE210_PRE -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE210_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE210_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE210_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE210_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE210_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE DSP2_BLBACK_GAMMA_TABLE211_PRE -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE211_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE211_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE211_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE211_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE211_PRE_POS)) - -/* 0xEA8 : BL_GAMMA_TABLE_107 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_107_OFFSET (0xEA8) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE DSP2_BLBACK_GAMMA_TABLE212_PRE -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE212_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE212_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE212_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE212_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE212_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE DSP2_BLBACK_GAMMA_TABLE213_PRE -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE213_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE213_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE213_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE213_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE213_PRE_POS)) - -/* 0xEAC : BL_GAMMA_TABLE_108 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_108_OFFSET (0xEAC) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE DSP2_BLBACK_GAMMA_TABLE214_PRE -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE214_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE214_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE214_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE214_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE214_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE DSP2_BLBACK_GAMMA_TABLE215_PRE -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE215_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE215_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE215_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE215_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE215_PRE_POS)) - -/* 0xEB0 : BL_GAMMA_TABLE_109 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_109_OFFSET (0xEB0) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE DSP2_BLBACK_GAMMA_TABLE216_PRE -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE216_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE216_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE216_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE216_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE216_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE DSP2_BLBACK_GAMMA_TABLE217_PRE -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE217_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE217_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE217_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE217_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE217_PRE_POS)) - -/* 0xEB4 : BL_GAMMA_TABLE_110 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_110_OFFSET (0xEB4) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE DSP2_BLBACK_GAMMA_TABLE218_PRE -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE218_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE218_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE218_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE218_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE218_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE DSP2_BLBACK_GAMMA_TABLE219_PRE -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE219_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE219_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE219_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE219_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE219_PRE_POS)) - -/* 0xEB8 : BL_GAMMA_TABLE_111 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_111_OFFSET (0xEB8) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE DSP2_BLBACK_GAMMA_TABLE220_PRE -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE220_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE220_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE220_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE220_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE220_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE DSP2_BLBACK_GAMMA_TABLE221_PRE -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE221_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE221_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE221_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE221_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE221_PRE_POS)) - -/* 0xEBC : BL_GAMMA_TABLE_112 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_112_OFFSET (0xEBC) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE DSP2_BLBACK_GAMMA_TABLE222_PRE -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE222_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE222_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE222_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE222_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE222_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE DSP2_BLBACK_GAMMA_TABLE223_PRE -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE223_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE223_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE223_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE223_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE223_PRE_POS)) - -/* 0xEC0 : BL_GAMMA_TABLE_113 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_113_OFFSET (0xEC0) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE DSP2_BLBACK_GAMMA_TABLE224_PRE -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE224_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE224_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE224_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE224_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE224_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE DSP2_BLBACK_GAMMA_TABLE225_PRE -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE225_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE225_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE225_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE225_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE225_PRE_POS)) - -/* 0xEC4 : BL_GAMMA_TABLE_114 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_114_OFFSET (0xEC4) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE DSP2_BLBACK_GAMMA_TABLE226_PRE -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE226_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE226_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE226_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE226_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE226_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE DSP2_BLBACK_GAMMA_TABLE227_PRE -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE227_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE227_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE227_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE227_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE227_PRE_POS)) - -/* 0xEC8 : BL_GAMMA_TABLE_115 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_115_OFFSET (0xEC8) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE DSP2_BLBACK_GAMMA_TABLE228_PRE -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE228_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE228_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE228_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE228_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE228_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE DSP2_BLBACK_GAMMA_TABLE229_PRE -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE229_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE229_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE229_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE229_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE229_PRE_POS)) - -/* 0xECC : BL_GAMMA_TABLE_116 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_116_OFFSET (0xECC) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE DSP2_BLBACK_GAMMA_TABLE230_PRE -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE230_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE230_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE230_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE230_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE230_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE DSP2_BLBACK_GAMMA_TABLE231_PRE -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE231_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE231_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE231_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE231_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE231_PRE_POS)) - -/* 0xED0 : BL_GAMMA_TABLE_117 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_117_OFFSET (0xED0) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE DSP2_BLBACK_GAMMA_TABLE232_PRE -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE232_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE232_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE232_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE232_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE232_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE DSP2_BLBACK_GAMMA_TABLE233_PRE -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE233_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE233_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE233_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE233_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE233_PRE_POS)) - -/* 0xED4 : BL_GAMMA_TABLE_118 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_118_OFFSET (0xED4) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE DSP2_BLBACK_GAMMA_TABLE234_PRE -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE234_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE234_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE234_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE234_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE234_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE DSP2_BLBACK_GAMMA_TABLE235_PRE -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE235_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE235_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE235_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE235_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE235_PRE_POS)) - -/* 0xED8 : BL_GAMMA_TABLE_119 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_119_OFFSET (0xED8) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE DSP2_BLBACK_GAMMA_TABLE236_PRE -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE236_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE236_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE236_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE236_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE236_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE DSP2_BLBACK_GAMMA_TABLE237_PRE -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE237_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE237_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE237_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE237_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE237_PRE_POS)) - -/* 0xEDC : BL_GAMMA_TABLE_120 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_120_OFFSET (0xEDC) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE DSP2_BLBACK_GAMMA_TABLE238_PRE -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE238_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE238_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE238_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE238_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE238_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE DSP2_BLBACK_GAMMA_TABLE239_PRE -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE239_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE239_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE239_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE239_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE239_PRE_POS)) - -/* 0xEE0 : BL_GAMMA_TABLE_121 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_121_OFFSET (0xEE0) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE DSP2_BLBACK_GAMMA_TABLE240_PRE -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE240_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE240_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE240_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE240_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE240_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE DSP2_BLBACK_GAMMA_TABLE241_PRE -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE241_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE241_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE241_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE241_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE241_PRE_POS)) - -/* 0xEE4 : BL_GAMMA_TABLE_122 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_122_OFFSET (0xEE4) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE DSP2_BLBACK_GAMMA_TABLE242_PRE -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE242_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE242_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE242_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE242_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE242_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE DSP2_BLBACK_GAMMA_TABLE243_PRE -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE243_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE243_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE243_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE243_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE243_PRE_POS)) - -/* 0xEE8 : BL_GAMMA_TABLE_123 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_123_OFFSET (0xEE8) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE DSP2_BLBACK_GAMMA_TABLE244_PRE -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE244_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE244_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE244_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE244_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE244_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE DSP2_BLBACK_GAMMA_TABLE245_PRE -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE245_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE245_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE245_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE245_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE245_PRE_POS)) - -/* 0xEEC : BL_GAMMA_TABLE_124 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_124_OFFSET (0xEEC) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE DSP2_BLBACK_GAMMA_TABLE246_PRE -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE246_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE246_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE246_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE246_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE246_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE DSP2_BLBACK_GAMMA_TABLE247_PRE -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE247_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE247_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE247_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE247_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE247_PRE_POS)) - -/* 0xEF0 : BL_GAMMA_TABLE_125 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_125_OFFSET (0xEF0) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE DSP2_BLBACK_GAMMA_TABLE248_PRE -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE248_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE248_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE248_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE248_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE248_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE DSP2_BLBACK_GAMMA_TABLE249_PRE -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE249_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE249_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE249_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE249_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE249_PRE_POS)) - -/* 0xEF4 : BL_GAMMA_TABLE_126 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_126_OFFSET (0xEF4) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE DSP2_BLBACK_GAMMA_TABLE250_PRE -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE250_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE250_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE250_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE250_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE250_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE DSP2_BLBACK_GAMMA_TABLE251_PRE -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE251_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE251_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE251_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE251_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE251_PRE_POS)) - -/* 0xEF8 : BL_GAMMA_TABLE_127 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_127_OFFSET (0xEF8) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE DSP2_BLBACK_GAMMA_TABLE252_PRE -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE252_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE252_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE252_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE252_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE252_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE DSP2_BLBACK_GAMMA_TABLE253_PRE -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE253_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE253_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE253_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE253_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE253_PRE_POS)) - -/* 0xEFC : BL_GAMMA_TABLE_128 */ -#define DSP2_BLBACK_BL_GAMMA_TABLE_128_OFFSET (0xEFC) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE DSP2_BLBACK_GAMMA_TABLE254_PRE -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_POS (0U) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE254_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE254_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE254_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE254_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE254_PRE_POS)) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE DSP2_BLBACK_GAMMA_TABLE255_PRE -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_POS (16U) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_LEN (12U) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_MSK (((1U << DSP2_BLBACK_GAMMA_TABLE255_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE255_PRE_POS) -#define DSP2_BLBACK_GAMMA_TABLE255_PRE_UMSK (~(((1U << DSP2_BLBACK_GAMMA_TABLE255_PRE_LEN) - 1) << DSP2_BLBACK_GAMMA_TABLE255_PRE_POS)) - -/* 0xF00 : CC_OFFSET_0 */ -#define DSP2_BLBACK_CC_OFFSET_0_OFFSET (0xF00) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE DSP2_BLBACK_CC_PRE_OFFSET0_PRE -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CC_PRE_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE DSP2_BLBACK_CC_PRE_OFFSET1_PRE -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CC_PRE_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET1_PRE_POS)) -#define DSP2_BLBACK_CC_ENABLE_PRE DSP2_BLBACK_CC_ENABLE_PRE -#define DSP2_BLBACK_CC_ENABLE_PRE_POS (31U) -#define DSP2_BLBACK_CC_ENABLE_PRE_LEN (1U) -#define DSP2_BLBACK_CC_ENABLE_PRE_MSK (((1U << DSP2_BLBACK_CC_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CC_ENABLE_PRE_POS) -#define DSP2_BLBACK_CC_ENABLE_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_ENABLE_PRE_LEN) - 1) << DSP2_BLBACK_CC_ENABLE_PRE_POS)) - -/* 0xF04 : CC_OFFSET_1 */ -#define DSP2_BLBACK_CC_OFFSET_1_OFFSET (0xF04) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE DSP2_BLBACK_CC_PRE_OFFSET2_PRE -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_POS (0U) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CC_PRE_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_PRE_OFFSET2_PRE_POS)) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE DSP2_BLBACK_CC_POST_OFFSET2_PRE -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_POS (16U) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CC_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CC_POST_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET2_PRE_POS)) - -/* 0xF08 : CC_OFFSET_2 */ -#define DSP2_BLBACK_CC_OFFSET_2_OFFSET (0xF08) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE DSP2_BLBACK_CC_POST_OFFSET0_PRE -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CC_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CC_POST_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE DSP2_BLBACK_CC_POST_OFFSET1_PRE -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CC_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CC_POST_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CC_POST_OFFSET1_PRE_POS)) - -/* 0xF0C : CC_MATRIX_0 */ -#define DSP2_BLBACK_CC_MATRIX_0_OFFSET (0xF0C) -#define DSP2_BLBACK_CC_MATRIX00_PRE DSP2_BLBACK_CC_MATRIX00_PRE -#define DSP2_BLBACK_CC_MATRIX00_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX00_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX00_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX00_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX00_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX00_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX01_PRE DSP2_BLBACK_CC_MATRIX01_PRE -#define DSP2_BLBACK_CC_MATRIX01_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX01_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX01_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX01_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX01_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX01_PRE_POS)) - -/* 0xF10 : CC_MATRIX_1 */ -#define DSP2_BLBACK_CC_MATRIX_1_OFFSET (0xF10) -#define DSP2_BLBACK_CC_MATRIX10_PRE DSP2_BLBACK_CC_MATRIX10_PRE -#define DSP2_BLBACK_CC_MATRIX10_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX10_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX10_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX10_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX10_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX10_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX02_PRE DSP2_BLBACK_CC_MATRIX02_PRE -#define DSP2_BLBACK_CC_MATRIX02_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX02_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX02_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX02_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX02_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX02_PRE_POS)) - -/* 0xF14 : CC_MATRIX_2 */ -#define DSP2_BLBACK_CC_MATRIX_2_OFFSET (0xF14) -#define DSP2_BLBACK_CC_MATRIX11_PRE DSP2_BLBACK_CC_MATRIX11_PRE -#define DSP2_BLBACK_CC_MATRIX11_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX11_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX11_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX11_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX11_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX11_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX12_PRE DSP2_BLBACK_CC_MATRIX12_PRE -#define DSP2_BLBACK_CC_MATRIX12_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX12_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX12_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX12_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX12_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX12_PRE_POS)) - -/* 0xF18 : CC_MATRIX_3 */ -#define DSP2_BLBACK_CC_MATRIX_3_OFFSET (0xF18) -#define DSP2_BLBACK_CC_MATRIX20_PRE DSP2_BLBACK_CC_MATRIX20_PRE -#define DSP2_BLBACK_CC_MATRIX20_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX20_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX20_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX20_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX20_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX20_PRE_POS)) -#define DSP2_BLBACK_CC_MATRIX21_PRE DSP2_BLBACK_CC_MATRIX21_PRE -#define DSP2_BLBACK_CC_MATRIX21_PRE_POS (16U) -#define DSP2_BLBACK_CC_MATRIX21_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX21_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX21_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX21_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX21_PRE_POS)) - -/* 0xF1C : CC_CE_MATRIX */ -#define DSP2_BLBACK_CC_CE_MATRIX_OFFSET (0xF1C) -#define DSP2_BLBACK_CC_MATRIX22_PRE DSP2_BLBACK_CC_MATRIX22_PRE -#define DSP2_BLBACK_CC_MATRIX22_PRE_POS (0U) -#define DSP2_BLBACK_CC_MATRIX22_PRE_LEN (12U) -#define DSP2_BLBACK_CC_MATRIX22_PRE_MSK (((1U << DSP2_BLBACK_CC_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX22_PRE_POS) -#define DSP2_BLBACK_CC_MATRIX22_PRE_UMSK (~(((1U << DSP2_BLBACK_CC_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CC_MATRIX22_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX02_PRE DSP2_BLBACK_CE_MATRIX02_PRE -#define DSP2_BLBACK_CE_MATRIX02_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX02_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX02_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX02_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX02_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX02_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX02_PRE_POS)) - -/* 0xF20 : CE_MATRIX_0 */ -#define DSP2_BLBACK_CE_MATRIX_0_OFFSET (0xF20) -#define DSP2_BLBACK_CE_MATRIX00_PRE DSP2_BLBACK_CE_MATRIX00_PRE -#define DSP2_BLBACK_CE_MATRIX00_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX00_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX00_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX00_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX00_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX00_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX00_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX01_PRE DSP2_BLBACK_CE_MATRIX01_PRE -#define DSP2_BLBACK_CE_MATRIX01_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX01_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX01_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX01_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX01_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX01_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX01_PRE_POS)) - -/* 0xF24 : CE_MATRIX_1 */ -#define DSP2_BLBACK_CE_MATRIX_1_OFFSET (0xF24) -#define DSP2_BLBACK_CE_MATRIX10_PRE DSP2_BLBACK_CE_MATRIX10_PRE -#define DSP2_BLBACK_CE_MATRIX10_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX10_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX10_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX10_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX10_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX10_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX10_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX11_PRE DSP2_BLBACK_CE_MATRIX11_PRE -#define DSP2_BLBACK_CE_MATRIX11_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX11_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX11_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX11_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX11_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX11_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX11_PRE_POS)) - -/* 0xF28 : CE_MATRIX_2 */ -#define DSP2_BLBACK_CE_MATRIX_2_OFFSET (0xF28) -#define DSP2_BLBACK_CE_MATRIX20_PRE DSP2_BLBACK_CE_MATRIX20_PRE -#define DSP2_BLBACK_CE_MATRIX20_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX20_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX20_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX20_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX20_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX20_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX20_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX12_PRE DSP2_BLBACK_CE_MATRIX12_PRE -#define DSP2_BLBACK_CE_MATRIX12_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX12_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX12_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX12_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX12_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX12_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX12_PRE_POS)) - -/* 0xF2C : CE_MATRIX_3 */ -#define DSP2_BLBACK_CE_MATRIX_3_OFFSET (0xF2C) -#define DSP2_BLBACK_CE_MATRIX21_PRE DSP2_BLBACK_CE_MATRIX21_PRE -#define DSP2_BLBACK_CE_MATRIX21_PRE_POS (0U) -#define DSP2_BLBACK_CE_MATRIX21_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX21_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX21_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX21_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX21_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX21_PRE_POS)) -#define DSP2_BLBACK_CE_MATRIX22_PRE DSP2_BLBACK_CE_MATRIX22_PRE -#define DSP2_BLBACK_CE_MATRIX22_PRE_POS (16U) -#define DSP2_BLBACK_CE_MATRIX22_PRE_LEN (12U) -#define DSP2_BLBACK_CE_MATRIX22_PRE_MSK (((1U << DSP2_BLBACK_CE_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX22_PRE_POS) -#define DSP2_BLBACK_CE_MATRIX22_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_MATRIX22_PRE_LEN) - 1) << DSP2_BLBACK_CE_MATRIX22_PRE_POS)) - -/* 0xF30 : CE_OFFSET_0 */ -#define DSP2_BLBACK_CE_OFFSET_0_OFFSET (0xF30) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE DSP2_BLBACK_CE_PRE_OFFSET0_PRE -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CE_PRE_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE DSP2_BLBACK_CE_PRE_OFFSET1_PRE -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CE_PRE_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET1_PRE_POS)) - -/* 0xF34 : CE_OFFSET_1 */ -#define DSP2_BLBACK_CE_OFFSET_1_OFFSET (0xF34) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE DSP2_BLBACK_CE_PRE_OFFSET2_PRE -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_POS (0U) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CE_PRE_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_PRE_OFFSET2_PRE_POS)) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE DSP2_BLBACK_CE_POST_OFFSET2_PRE -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_POS (16U) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_LEN (13U) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_MSK (((1U << DSP2_BLBACK_CE_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET2_PRE_POS) -#define DSP2_BLBACK_CE_POST_OFFSET2_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_POST_OFFSET2_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET2_PRE_POS)) - -/* 0xF38 : CE_OFFSET_2 */ -#define DSP2_BLBACK_CE_OFFSET_2_OFFSET (0xF38) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE DSP2_BLBACK_CE_POST_OFFSET0_PRE -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_POS (0U) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_LEN (13U) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_MSK (((1U << DSP2_BLBACK_CE_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET0_PRE_POS) -#define DSP2_BLBACK_CE_POST_OFFSET0_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_POST_OFFSET0_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET0_PRE_POS)) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE DSP2_BLBACK_CE_POST_OFFSET1_PRE -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_POS (16U) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_LEN (13U) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_MSK (((1U << DSP2_BLBACK_CE_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET1_PRE_POS) -#define DSP2_BLBACK_CE_POST_OFFSET1_PRE_UMSK (~(((1U << DSP2_BLBACK_CE_POST_OFFSET1_PRE_LEN) - 1) << DSP2_BLBACK_CE_POST_OFFSET1_PRE_POS)) - -struct dsp2_blback_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[788]; - - /* 0x314 : ccr_coef_A */ - union { - struct { - uint32_t reserved_0_15 : 16; /* [15: 0], rsvd, 0x0 */ - uint32_t a11_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_A; - - /* 0x318 : ccr_coef_B */ - union { - struct { - uint32_t a12_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a13_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_B; - - /* 0x31C : ccr_coef_C */ - union { - struct { - uint32_t a21_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a22_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_C; - - /* 0x320 : ccr_coef_D */ - union { - struct { - uint32_t a23_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a31_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_D; - - /* 0x324 : ccr_coef_E */ - union { - struct { - uint32_t a32_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t a33_pre : 12; /* [27:16], r/w, 0x200 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ccr_coef_E; - - /* 0x328 : gamma_A */ - union { - struct { - uint32_t gamma_on_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t gamma_eb_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t bl_gamma_en_pre : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gamma_A; - - /* 0x32c reserved */ - uint8_t RESERVED0x32c[16]; - - /* 0x33C : conv_mode */ - union { - struct { - uint32_t conv_mode_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } conv_mode; - - /* 0x340 reserved */ - uint8_t RESERVED0x340[12]; - - /* 0x34C : YUVC_A */ - union { - struct { - uint32_t YBrightness_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t YContrast_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t CbSaturation_pre : 8; /* [23:16], r/w, 0x80 */ - uint32_t CrSaturation_pre : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_A; - - /* 0x350 : YUVC_B */ - union { - struct { - uint32_t SpecialMode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t C444to422Filteringmode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t SepiaCb_w : 8; /* [15: 8], r/w, 0x73 */ - uint32_t SepiaCr_w : 8; /* [23:16], r/w, 0x89 */ - uint32_t SolarThred_w : 8; /* [31:24], r/w, 0x80 */ - } BF; - uint32_t WORD; - } YUVC_B; - - /* 0x354 : DNR_A */ - union { - struct { - uint32_t noise_level_pre : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t nr_hsize_pre : 16; /* [23: 8], r/w, 0x788 */ - uint32_t Filt_Strength_2D_pre : 4; /* [27:24], r/w, 0x6 */ - uint32_t Filt_Strength_3D_pre : 4; /* [31:28], r/w, 0x5 */ - } BF; - uint32_t WORD; - } DNR_A; - - /* 0x358 : DNR_B */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t CbCr_select_w : 1; /* [ 8], r/w, 0x1 */ - uint32_t out_format_w : 2; /* [10: 9], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DNR_B; - - /* 0x35c reserved */ - uint8_t RESERVED0x35c[4]; - - /* 0x360 : BLEE_0 */ - union { - struct { - uint32_t ee_eb_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t ovrsht_eb_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t txt_thr_pre : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_0; - - /* 0x364 : BLEE_1 */ - union { - struct { - uint32_t thresh1_pre : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t thresh2_pre : 7; /* [14: 8], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t flat_thr_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_1; - - /* 0x368 : BLEE_2 */ - union { - struct { - uint32_t ovrsht_pos_pre : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t ovrsht_neg_pre : 7; /* [14: 8], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t posee_str_pre : 7; /* [22:16], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t negee_str_pre : 7; /* [30:24], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_2; - - /* 0x36C : BLEE_3 */ - union { - struct { - uint32_t edge_thr_pre : 16; /* [15: 0], r/w, 0x0 */ - uint32_t nr_str_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_3; - - /* 0x370 : BLEE_4 */ - union { - struct { - uint32_t luma_wgt0_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt1_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_4; - - /* 0x374 : BLEE_5 */ - union { - struct { - uint32_t luma_wgt2_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt3_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_5; - - /* 0x378 : BLEE_6 */ - union { - struct { - uint32_t luma_wgt4_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt5_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_6; - - /* 0x37C : BLEE_7 */ - union { - struct { - uint32_t luma_wgt6_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt7_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_7; - - /* 0x380 : BLEE_8 */ - union { - struct { - uint32_t luma_wgt8_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt9_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_8; - - /* 0x384 : BLEE_9 */ - union { - struct { - uint32_t luma_wgt10_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt11_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_9; - - /* 0x388 : BLEE_A */ - union { - struct { - uint32_t luma_wgt12_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt13_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_A; - - /* 0x38C : BLEE_B */ - union { - struct { - uint32_t luma_wgt14_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt15_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_B; - - /* 0x390 : BLEE_C */ - union { - struct { - uint32_t luma_wgt16_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt17_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_C; - - /* 0x394 : BLEE_D */ - union { - struct { - uint32_t luma_wgt18_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt19_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_D; - - /* 0x398 : BLEE_E */ - union { - struct { - uint32_t luma_wgt20_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt21_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_E; - - /* 0x39C : BLEE_F */ - union { - struct { - uint32_t luma_wgt22_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt23_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_F; - - /* 0x3A0 : BLEE_10 */ - union { - struct { - uint32_t luma_wgt24_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt25_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_10; - - /* 0x3A4 : BLEE_11 */ - union { - struct { - uint32_t luma_wgt26_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt27_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_11; - - /* 0x3A8 : BLEE_12 */ - union { - struct { - uint32_t luma_wgt28_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt29_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_12; - - /* 0x3AC : BLEE_13 */ - union { - struct { - uint32_t luma_wgt30_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t luma_wgt31_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BLEE_13; - - /* 0x3B0 : CS1 */ - union { - struct { - uint32_t cs1_grey_th_pre : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t cs1_enable_pre : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cs1_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cs1_gain_pre : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CS1; - - /* 0x3B4 : CS2 */ - union { - struct { - uint32_t cs2_grey_th_pre : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t cs2_enable_pre : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cs2_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cs2_gain_pre : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CS2; - - /* 0x3b8 reserved */ - uint8_t RESERVED0x3b8[68]; - - /* 0x3FC : DUMMY_CTRL */ - union { - struct { - uint32_t reg_bl444to422_en_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DUMMY_CTRL; - - /* 0x400 reserved */ - uint8_t RESERVED0x400[1280]; - - /* 0x900 : WDR_0 */ - union { - struct { - uint32_t wdr_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t blwdr_buf_idx_r : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t blwdr_w_cnt_r : 5; /* [ 8: 4], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t wdr_cs_gain_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_0; - - /* 0x904 : WDR_CS_0 */ - union { - struct { - uint32_t wdr_cs_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t wdr_cs_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t wdr_cs_grey_th_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CS_0; - - /* 0x908 : WDR_HIST_1 */ - union { - struct { - uint32_t hist_roi0_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi0_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi1_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi1_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_1; - - /* 0x90C : WDR_HIST_2 */ - union { - struct { - uint32_t hist_roi2_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi2_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi3_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi3_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_2; - - /* 0x910 : WDR_HIST_3 */ - union { - struct { - uint32_t hist_roi4_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi4_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi5_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi5_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_3; - - /* 0x914 : WDR_HIST_4 */ - union { - struct { - uint32_t hist_roi6_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t hist_roi6_weight_pre : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t hist_roi7_en_pre : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t hist_roi7_weight_pre : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_4; - - /* 0x918 : WDR_HIST_5 */ - union { - struct { - uint32_t hist_x0_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x0_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_5; - - /* 0x91C : WDR_HIST_6 */ - union { - struct { - uint32_t hist_y0_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y0_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_6; - - /* 0x920 : WDR_HIST_7 */ - union { - struct { - uint32_t hist_x1_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x1_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_7; - - /* 0x924 : WDR_HIST_8 */ - union { - struct { - uint32_t hist_y1_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y1_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_8; - - /* 0x928 : WDR_HIST_9 */ - union { - struct { - uint32_t hist_x2_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x2_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_9; - - /* 0x92C : WDR_HIST_10 */ - union { - struct { - uint32_t hist_y2_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y2_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_10; - - /* 0x930 : WDR_HIST_11 */ - union { - struct { - uint32_t hist_x3_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x3_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_11; - - /* 0x934 : WDR_HIST_12 */ - union { - struct { - uint32_t hist_y3_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y3_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_12; - - /* 0x938 : WDR_HIST_13 */ - union { - struct { - uint32_t hist_x4_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x4_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_13; - - /* 0x93C : WDR_HIST_14 */ - union { - struct { - uint32_t hist_y4_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y4_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_14; - - /* 0x940 : WDR_HIST_15 */ - union { - struct { - uint32_t hist_x5_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x5_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_15; - - /* 0x944 : WDR_HIST_16 */ - union { - struct { - uint32_t hist_y5_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y5_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_16; - - /* 0x948 : WDR_HIST_17 */ - union { - struct { - uint32_t hist_x6_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x6_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_17; - - /* 0x94C : WDR_HIST_18 */ - union { - struct { - uint32_t hist_y6_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y6_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_18; - - /* 0x950 : WDR_HIST_19 */ - union { - struct { - uint32_t hist_x7_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_x7_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_19; - - /* 0x954 : WDR_HIST_20 */ - union { - struct { - uint32_t hist_y7_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t hist_y7_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_HIST_20; - - /* 0x958 : REG_HIST0_64 */ - union { - struct { - uint32_t hist0_64_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_64; - - /* 0x95C : REG_HIST1_64 */ - union { - struct { - uint32_t hist1_64_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_64; - - /* 0x960 reserved */ - uint8_t RESERVED0x960[160]; - - /* 0xA00 : REG_HIST0_0 */ - union { - struct { - uint32_t hist0_0_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_0; - - /* 0xA04 : REG_HIST0_1 */ - union { - struct { - uint32_t hist0_1_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_1; - - /* 0xA08 : REG_HIST0_2 */ - union { - struct { - uint32_t hist0_2_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_2; - - /* 0xA0C : REG_HIST0_3 */ - union { - struct { - uint32_t hist0_3_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_3; - - /* 0xA10 : REG_HIST0_4 */ - union { - struct { - uint32_t hist0_4_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_4; - - /* 0xA14 : REG_HIST0_5 */ - union { - struct { - uint32_t hist0_5_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_5; - - /* 0xA18 : REG_HIST0_6 */ - union { - struct { - uint32_t hist0_6_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_6; - - /* 0xA1C : REG_HIST0_7 */ - union { - struct { - uint32_t hist0_7_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_7; - - /* 0xA20 : REG_HIST0_8 */ - union { - struct { - uint32_t hist0_8_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_8; - - /* 0xA24 : REG_HIST0_9 */ - union { - struct { - uint32_t hist0_9_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_9; - - /* 0xA28 : REG_HIST0_10 */ - union { - struct { - uint32_t hist0_10_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_10; - - /* 0xA2C : REG_HIST0_11 */ - union { - struct { - uint32_t hist0_11_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_11; - - /* 0xA30 : REG_HIST0_12 */ - union { - struct { - uint32_t hist0_12_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_12; - - /* 0xA34 : REG_HIST0_13 */ - union { - struct { - uint32_t hist0_13_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_13; - - /* 0xA38 : REG_HIST0_14 */ - union { - struct { - uint32_t hist0_14_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_14; - - /* 0xA3C : REG_HIST0_15 */ - union { - struct { - uint32_t hist0_15_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_15; - - /* 0xA40 : REG_HIST0_16 */ - union { - struct { - uint32_t hist0_16_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_16; - - /* 0xA44 : REG_HIST0_17 */ - union { - struct { - uint32_t hist0_17_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_17; - - /* 0xA48 : REG_HIST0_18 */ - union { - struct { - uint32_t hist0_18_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_18; - - /* 0xA4C : REG_HIST0_19 */ - union { - struct { - uint32_t hist0_19_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_19; - - /* 0xA50 : REG_HIST0_20 */ - union { - struct { - uint32_t hist0_20_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_20; - - /* 0xA54 : REG_HIST0_21 */ - union { - struct { - uint32_t hist0_21_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_21; - - /* 0xA58 : REG_HIST0_22 */ - union { - struct { - uint32_t hist0_22_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_22; - - /* 0xA5C : REG_HIST0_23 */ - union { - struct { - uint32_t hist0_23_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_23; - - /* 0xA60 : REG_HIST0_24 */ - union { - struct { - uint32_t hist0_24_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_24; - - /* 0xA64 : REG_HIST0_25 */ - union { - struct { - uint32_t hist0_25_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_25; - - /* 0xA68 : REG_HIST0_26 */ - union { - struct { - uint32_t hist0_26_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_26; - - /* 0xA6C : REG_HIST0_27 */ - union { - struct { - uint32_t hist0_27_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_27; - - /* 0xA70 : REG_HIST0_28 */ - union { - struct { - uint32_t hist0_28_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_28; - - /* 0xA74 : REG_HIST0_29 */ - union { - struct { - uint32_t hist0_29_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_29; - - /* 0xA78 : REG_HIST0_30 */ - union { - struct { - uint32_t hist0_30_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_30; - - /* 0xA7C : REG_HIST0_31 */ - union { - struct { - uint32_t hist0_31_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_31; - - /* 0xA80 : REG_HIST0_32 */ - union { - struct { - uint32_t hist0_32_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_32; - - /* 0xA84 : REG_HIST0_33 */ - union { - struct { - uint32_t hist0_33_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_33; - - /* 0xA88 : REG_HIST0_34 */ - union { - struct { - uint32_t hist0_34_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_34; - - /* 0xA8C : REG_HIST0_35 */ - union { - struct { - uint32_t hist0_35_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_35; - - /* 0xA90 : REG_HIST0_36 */ - union { - struct { - uint32_t hist0_36_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_36; - - /* 0xA94 : REG_HIST0_37 */ - union { - struct { - uint32_t hist0_37_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_37; - - /* 0xA98 : REG_HIST0_38 */ - union { - struct { - uint32_t hist0_38_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_38; - - /* 0xA9C : REG_HIST0_39 */ - union { - struct { - uint32_t hist0_39_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_39; - - /* 0xAA0 : REG_HIST0_40 */ - union { - struct { - uint32_t hist0_40_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_40; - - /* 0xAA4 : REG_HIST0_41 */ - union { - struct { - uint32_t hist0_41_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_41; - - /* 0xAA8 : REG_HIST0_42 */ - union { - struct { - uint32_t hist0_42_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_42; - - /* 0xAAC : REG_HIST0_43 */ - union { - struct { - uint32_t hist0_43_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_43; - - /* 0xAB0 : REG_HIST0_44 */ - union { - struct { - uint32_t hist0_44_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_44; - - /* 0xAB4 : REG_HIST0_45 */ - union { - struct { - uint32_t hist0_45_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_45; - - /* 0xAB8 : REG_HIST0_46 */ - union { - struct { - uint32_t hist0_46_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_46; - - /* 0xABC : REG_HIST0_47 */ - union { - struct { - uint32_t hist0_47_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_47; - - /* 0xAC0 : REG_HIST0_48 */ - union { - struct { - uint32_t hist0_48_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_48; - - /* 0xAC4 : REG_HIST0_49 */ - union { - struct { - uint32_t hist0_49_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_49; - - /* 0xAC8 : REG_HIST0_50 */ - union { - struct { - uint32_t hist0_50_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_50; - - /* 0xACC : REG_HIST0_51 */ - union { - struct { - uint32_t hist0_51_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_51; - - /* 0xAD0 : REG_HIST0_52 */ - union { - struct { - uint32_t hist0_52_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_52; - - /* 0xAD4 : REG_HIST0_53 */ - union { - struct { - uint32_t hist0_53_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_53; - - /* 0xAD8 : REG_HIST0_54 */ - union { - struct { - uint32_t hist0_54_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_54; - - /* 0xADC : REG_HIST0_55 */ - union { - struct { - uint32_t hist0_55_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_55; - - /* 0xAE0 : REG_HIST0_56 */ - union { - struct { - uint32_t hist0_56_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_56; - - /* 0xAE4 : REG_HIST0_57 */ - union { - struct { - uint32_t hist0_57_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_57; - - /* 0xAE8 : REG_HIST0_58 */ - union { - struct { - uint32_t hist0_58_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_58; - - /* 0xAEC : REG_HIST0_59 */ - union { - struct { - uint32_t hist0_59_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_59; - - /* 0xAF0 : REG_HIST0_60 */ - union { - struct { - uint32_t hist0_60_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_60; - - /* 0xAF4 : REG_HIST0_61 */ - union { - struct { - uint32_t hist0_61_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_61; - - /* 0xAF8 : REG_HIST0_62 */ - union { - struct { - uint32_t hist0_62_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_62; - - /* 0xAFC : REG_HIST0_63 */ - union { - struct { - uint32_t hist0_63_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST0_63; - - /* 0xB00 : REG_HIST1_0 */ - union { - struct { - uint32_t hist1_0_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_0; - - /* 0xB04 : REG_HIST1_1 */ - union { - struct { - uint32_t hist1_1_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_1; - - /* 0xB08 : REG_HIST1_2 */ - union { - struct { - uint32_t hist1_2_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_2; - - /* 0xB0C : REG_HIST1_3 */ - union { - struct { - uint32_t hist1_3_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_3; - - /* 0xB10 : REG_HIST1_4 */ - union { - struct { - uint32_t hist1_4_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_4; - - /* 0xB14 : REG_HIST1_5 */ - union { - struct { - uint32_t hist1_5_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_5; - - /* 0xB18 : REG_HIST1_6 */ - union { - struct { - uint32_t hist1_6_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_6; - - /* 0xB1C : REG_HIST1_7 */ - union { - struct { - uint32_t hist1_7_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_7; - - /* 0xB20 : REG_HIST1_8 */ - union { - struct { - uint32_t hist1_8_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_8; - - /* 0xB24 : REG_HIST1_9 */ - union { - struct { - uint32_t hist1_9_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_9; - - /* 0xB28 : REG_HIST1_10 */ - union { - struct { - uint32_t hist1_10_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_10; - - /* 0xB2C : REG_HIST1_11 */ - union { - struct { - uint32_t hist1_11_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_11; - - /* 0xB30 : REG_HIST1_12 */ - union { - struct { - uint32_t hist1_12_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_12; - - /* 0xB34 : REG_HIST1_13 */ - union { - struct { - uint32_t hist1_13_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_13; - - /* 0xB38 : REG_HIST1_14 */ - union { - struct { - uint32_t hist1_14_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_14; - - /* 0xB3C : REG_HIST1_15 */ - union { - struct { - uint32_t hist1_15_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_15; - - /* 0xB40 : REG_HIST1_16 */ - union { - struct { - uint32_t hist1_16_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_16; - - /* 0xB44 : REG_HIST1_17 */ - union { - struct { - uint32_t hist1_17_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_17; - - /* 0xB48 : REG_HIST1_18 */ - union { - struct { - uint32_t hist1_18_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_18; - - /* 0xB4C : REG_HIST1_19 */ - union { - struct { - uint32_t hist1_19_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_19; - - /* 0xB50 : REG_HIST1_20 */ - union { - struct { - uint32_t hist1_20_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_20; - - /* 0xB54 : REG_HIST1_21 */ - union { - struct { - uint32_t hist1_21_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_21; - - /* 0xB58 : REG_HIST1_22 */ - union { - struct { - uint32_t hist1_22_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_22; - - /* 0xB5C : REG_HIST1_23 */ - union { - struct { - uint32_t hist1_23_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_23; - - /* 0xB60 : REG_HIST1_24 */ - union { - struct { - uint32_t hist1_24_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_24; - - /* 0xB64 : REG_HIST1_25 */ - union { - struct { - uint32_t hist1_25_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_25; - - /* 0xB68 : REG_HIST1_26 */ - union { - struct { - uint32_t hist1_26_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_26; - - /* 0xB6C : REG_HIST1_27 */ - union { - struct { - uint32_t hist1_27_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_27; - - /* 0xB70 : REG_HIST1_28 */ - union { - struct { - uint32_t hist1_28_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_28; - - /* 0xB74 : REG_HIST1_29 */ - union { - struct { - uint32_t hist1_29_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_29; - - /* 0xB78 : REG_HIST1_30 */ - union { - struct { - uint32_t hist1_30_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_30; - - /* 0xB7C : REG_HIST1_31 */ - union { - struct { - uint32_t hist1_31_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_31; - - /* 0xB80 : REG_HIST1_32 */ - union { - struct { - uint32_t hist1_32_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_32; - - /* 0xB84 : REG_HIST1_33 */ - union { - struct { - uint32_t hist1_33_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_33; - - /* 0xB88 : REG_HIST1_34 */ - union { - struct { - uint32_t hist1_34_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_34; - - /* 0xB8C : REG_HIST1_35 */ - union { - struct { - uint32_t hist1_35_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_35; - - /* 0xB90 : REG_HIST1_36 */ - union { - struct { - uint32_t hist1_36_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_36; - - /* 0xB94 : REG_HIST1_37 */ - union { - struct { - uint32_t hist1_37_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_37; - - /* 0xB98 : REG_HIST1_38 */ - union { - struct { - uint32_t hist1_38_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_38; - - /* 0xB9C : REG_HIST1_39 */ - union { - struct { - uint32_t hist1_39_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_39; - - /* 0xBA0 : REG_HIST1_40 */ - union { - struct { - uint32_t hist1_40_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_40; - - /* 0xBA4 : REG_HIST1_41 */ - union { - struct { - uint32_t hist1_41_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_41; - - /* 0xBA8 : REG_HIST1_42 */ - union { - struct { - uint32_t hist1_42_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_42; - - /* 0xBAC : REG_HIST1_43 */ - union { - struct { - uint32_t hist1_43_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_43; - - /* 0xBB0 : REG_HIST1_44 */ - union { - struct { - uint32_t hist1_44_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_44; - - /* 0xBB4 : REG_HIST1_45 */ - union { - struct { - uint32_t hist1_45_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_45; - - /* 0xBB8 : REG_HIST1_46 */ - union { - struct { - uint32_t hist1_46_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_46; - - /* 0xBBC : REG_HIST1_47 */ - union { - struct { - uint32_t hist1_47_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_47; - - /* 0xBC0 : REG_HIST1_48 */ - union { - struct { - uint32_t hist1_48_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_48; - - /* 0xBC4 : REG_HIST1_49 */ - union { - struct { - uint32_t hist1_49_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_49; - - /* 0xBC8 : REG_HIST1_50 */ - union { - struct { - uint32_t hist1_50_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_50; - - /* 0xBCC : REG_HIST1_51 */ - union { - struct { - uint32_t hist1_51_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_51; - - /* 0xBD0 : REG_HIST1_52 */ - union { - struct { - uint32_t hist1_52_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_52; - - /* 0xBD4 : REG_HIST1_53 */ - union { - struct { - uint32_t hist1_53_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_53; - - /* 0xBD8 : REG_HIST1_54 */ - union { - struct { - uint32_t hist1_54_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_54; - - /* 0xBDC : REG_HIST1_55 */ - union { - struct { - uint32_t hist1_55_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_55; - - /* 0xBE0 : REG_HIST1_56 */ - union { - struct { - uint32_t hist1_56_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_56; - - /* 0xBE4 : REG_HIST1_57 */ - union { - struct { - uint32_t hist1_57_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_57; - - /* 0xBE8 : REG_HIST1_58 */ - union { - struct { - uint32_t hist1_58_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_58; - - /* 0xBEC : REG_HIST1_59 */ - union { - struct { - uint32_t hist1_59_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_59; - - /* 0xBF0 : REG_HIST1_60 */ - union { - struct { - uint32_t hist1_60_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_60; - - /* 0xBF4 : REG_HIST1_61 */ - union { - struct { - uint32_t hist1_61_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_61; - - /* 0xBF8 : REG_HIST1_62 */ - union { - struct { - uint32_t hist1_62_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_62; - - /* 0xBFC : REG_HIST1_63 */ - union { - struct { - uint32_t hist1_63_r : 24; /* [23: 0], r, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } REG_HIST1_63; - - /* 0xC00 : WDR_CURVE_1 */ - union { - struct { - uint32_t curve_0_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_1_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_1; - - /* 0xC04 : WDR_CURVE_2 */ - union { - struct { - uint32_t curve_2_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_3_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_2; - - /* 0xC08 : WDR_CURVE_3 */ - union { - struct { - uint32_t curve_4_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_5_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_3; - - /* 0xC0C : WDR_CURVE_4 */ - union { - struct { - uint32_t curve_6_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_7_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_4; - - /* 0xC10 : WDR_CURVE_5 */ - union { - struct { - uint32_t curve_8_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_9_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_5; - - /* 0xC14 : WDR_CURVE_6 */ - union { - struct { - uint32_t curve_10_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_11_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_6; - - /* 0xC18 : WDR_CURVE_7 */ - union { - struct { - uint32_t curve_12_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_13_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_7; - - /* 0xC1C : WDR_CURVE_8 */ - union { - struct { - uint32_t curve_14_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_15_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_8; - - /* 0xC20 : WDR_CURVE_9 */ - union { - struct { - uint32_t curve_16_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_17_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_9; - - /* 0xC24 : WDR_CURVE_10 */ - union { - struct { - uint32_t curve_18_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_19_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_10; - - /* 0xC28 : WDR_CURVE_11 */ - union { - struct { - uint32_t curve_20_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_21_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_11; - - /* 0xC2C : WDR_CURVE_12 */ - union { - struct { - uint32_t curve_22_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_23_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_12; - - /* 0xC30 : WDR_CURVE_13 */ - union { - struct { - uint32_t curve_24_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_25_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_13; - - /* 0xC34 : WDR_CURVE_14 */ - union { - struct { - uint32_t curve_26_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_27_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_14; - - /* 0xC38 : WDR_CURVE_15 */ - union { - struct { - uint32_t curve_28_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_29_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_15; - - /* 0xC3C : WDR_CURVE_16 */ - union { - struct { - uint32_t curve_30_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_31_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_16; - - /* 0xC40 : WDR_CURVE_17 */ - union { - struct { - uint32_t curve_32_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_33_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_17; - - /* 0xC44 : WDR_CURVE_18 */ - union { - struct { - uint32_t curve_34_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_35_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_18; - - /* 0xC48 : WDR_CURVE_19 */ - union { - struct { - uint32_t curve_36_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_37_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_19; - - /* 0xC4C : WDR_CURVE_20 */ - union { - struct { - uint32_t curve_38_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_39_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_20; - - /* 0xC50 : WDR_CURVE_21 */ - union { - struct { - uint32_t curve_40_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_41_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_21; - - /* 0xC54 : WDR_CURVE_22 */ - union { - struct { - uint32_t curve_42_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_43_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_22; - - /* 0xC58 : WDR_CURVE_23 */ - union { - struct { - uint32_t curve_44_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_45_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_23; - - /* 0xC5C : WDR_CURVE_24 */ - union { - struct { - uint32_t curve_46_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_47_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_24; - - /* 0xC60 : WDR_CURVE_25 */ - union { - struct { - uint32_t curve_48_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_49_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_25; - - /* 0xC64 : WDR_CURVE_26 */ - union { - struct { - uint32_t curve_50_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_51_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_26; - - /* 0xC68 : WDR_CURVE_27 */ - union { - struct { - uint32_t curve_52_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_53_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_27; - - /* 0xC6C : WDR_CURVE_28 */ - union { - struct { - uint32_t curve_54_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_55_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_28; - - /* 0xC70 : WDR_CURVE_29 */ - union { - struct { - uint32_t curve_56_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_57_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_29; - - /* 0xC74 : WDR_CURVE_30 */ - union { - struct { - uint32_t curve_58_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_59_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_30; - - /* 0xC78 : WDR_CURVE_31 */ - union { - struct { - uint32_t curve_60_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_61_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_31; - - /* 0xC7C : WDR_CURVE_32 */ - union { - struct { - uint32_t curve_62_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t curve_63_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_32; - - /* 0xC80 : WDR_CURVE_33 */ - union { - struct { - uint32_t curve_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t curve_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_CURVE_33; - - /* 0xC84 : WDR_ENH_1 */ - union { - struct { - uint32_t enh_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t enh_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t enh_y_offset_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_ENH_1; - - /* 0xC88 : WDR_ENH_2 */ - union { - struct { - uint32_t enh_c_gain_pre : 15; /* [14: 0], r/w, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t enh_y_gain_pre : 15; /* [30:16], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WDR_ENH_2; - - /* 0xc8c reserved */ - uint8_t RESERVED0xc8c[116]; - - /* 0xD00 : BL_GAMMA_TABLE_1 */ - union { - struct { - uint32_t gamma_table0_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table1_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_1; - - /* 0xD04 : BL_GAMMA_TABLE_2 */ - union { - struct { - uint32_t gamma_table2_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table3_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_2; - - /* 0xD08 : BL_GAMMA_TABLE_3 */ - union { - struct { - uint32_t gamma_table4_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table5_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_3; - - /* 0xD0C : BL_GAMMA_TABLE_4 */ - union { - struct { - uint32_t gamma_table6_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table7_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_4; - - /* 0xD10 : BL_GAMMA_TABLE_5 */ - union { - struct { - uint32_t gamma_table8_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table9_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_5; - - /* 0xD14 : BL_GAMMA_TABLE_6 */ - union { - struct { - uint32_t gamma_table10_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table11_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_6; - - /* 0xD18 : BL_GAMMA_TABLE_7 */ - union { - struct { - uint32_t gamma_table12_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table13_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_7; - - /* 0xD1C : BL_GAMMA_TABLE_8 */ - union { - struct { - uint32_t gamma_table14_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table15_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_8; - - /* 0xD20 : BL_GAMMA_TABLE_9 */ - union { - struct { - uint32_t gamma_table16_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table17_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_9; - - /* 0xD24 : BL_GAMMA_TABLE_10 */ - union { - struct { - uint32_t gamma_table18_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table19_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_10; - - /* 0xD28 : BL_GAMMA_TABLE_11 */ - union { - struct { - uint32_t gamma_table20_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table21_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_11; - - /* 0xD2C : BL_GAMMA_TABLE_12 */ - union { - struct { - uint32_t gamma_table22_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table23_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_12; - - /* 0xD30 : BL_GAMMA_TABLE_13 */ - union { - struct { - uint32_t gamma_table24_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table25_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_13; - - /* 0xD34 : BL_GAMMA_TABLE_14 */ - union { - struct { - uint32_t gamma_table26_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table27_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_14; - - /* 0xD38 : BL_GAMMA_TABLE_15 */ - union { - struct { - uint32_t gamma_table28_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table29_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_15; - - /* 0xD3C : BL_GAMMA_TABLE_16 */ - union { - struct { - uint32_t gamma_table30_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table31_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_16; - - /* 0xD40 : BL_GAMMA_TABLE_17 */ - union { - struct { - uint32_t gamma_table32_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table33_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_17; - - /* 0xD44 : BL_GAMMA_TABLE_18 */ - union { - struct { - uint32_t gamma_table34_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table35_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_18; - - /* 0xD48 : BL_GAMMA_TABLE_19 */ - union { - struct { - uint32_t gamma_table36_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table37_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_19; - - /* 0xD4C : BL_GAMMA_TABLE_20 */ - union { - struct { - uint32_t gamma_table38_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table39_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_20; - - /* 0xD50 : BL_GAMMA_TABLE_21 */ - union { - struct { - uint32_t gamma_table40_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table41_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_21; - - /* 0xD54 : BL_GAMMA_TABLE_22 */ - union { - struct { - uint32_t gamma_table42_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table43_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_22; - - /* 0xD58 : BL_GAMMA_TABLE_23 */ - union { - struct { - uint32_t gamma_table44_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table45_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_23; - - /* 0xD5C : BL_GAMMA_TABLE_24 */ - union { - struct { - uint32_t gamma_table46_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table47_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_24; - - /* 0xD60 : BL_GAMMA_TABLE_25 */ - union { - struct { - uint32_t gamma_table48_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table49_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_25; - - /* 0xD64 : BL_GAMMA_TABLE_26 */ - union { - struct { - uint32_t gamma_table50_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table51_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_26; - - /* 0xD68 : BL_GAMMA_TABLE_27 */ - union { - struct { - uint32_t gamma_table52_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table53_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_27; - - /* 0xD6C : BL_GAMMA_TABLE_28 */ - union { - struct { - uint32_t gamma_table54_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table55_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_28; - - /* 0xD70 : BL_GAMMA_TABLE_29 */ - union { - struct { - uint32_t gamma_table56_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table57_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_29; - - /* 0xD74 : BL_GAMMA_TABLE_30 */ - union { - struct { - uint32_t gamma_table58_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table59_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_30; - - /* 0xD78 : BL_GAMMA_TABLE_31 */ - union { - struct { - uint32_t gamma_table60_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table61_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_31; - - /* 0xD7C : BL_GAMMA_TABLE_32 */ - union { - struct { - uint32_t gamma_table62_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table63_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_32; - - /* 0xD80 : BL_GAMMA_TABLE_33 */ - union { - struct { - uint32_t gamma_table64_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table65_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_33; - - /* 0xD84 : BL_GAMMA_TABLE_34 */ - union { - struct { - uint32_t gamma_table66_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table67_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_34; - - /* 0xD88 : BL_GAMMA_TABLE_35 */ - union { - struct { - uint32_t gamma_table68_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table69_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_35; - - /* 0xD8C : BL_GAMMA_TABLE_36 */ - union { - struct { - uint32_t gamma_table70_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table71_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_36; - - /* 0xD90 : BL_GAMMA_TABLE_37 */ - union { - struct { - uint32_t gamma_table72_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table73_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_37; - - /* 0xD94 : BL_GAMMA_TABLE_38 */ - union { - struct { - uint32_t gamma_table74_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table75_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_38; - - /* 0xD98 : BL_GAMMA_TABLE_39 */ - union { - struct { - uint32_t gamma_table76_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table77_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_39; - - /* 0xD9C : BL_GAMMA_TABLE_40 */ - union { - struct { - uint32_t gamma_table78_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table79_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_40; - - /* 0xDA0 : BL_GAMMA_TABLE_41 */ - union { - struct { - uint32_t gamma_table80_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table81_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_41; - - /* 0xDA4 : BL_GAMMA_TABLE_42 */ - union { - struct { - uint32_t gamma_table82_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table83_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_42; - - /* 0xDA8 : BL_GAMMA_TABLE_43 */ - union { - struct { - uint32_t gamma_table84_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table85_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_43; - - /* 0xDAC : BL_GAMMA_TABLE_44 */ - union { - struct { - uint32_t gamma_table86_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table87_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_44; - - /* 0xDB0 : BL_GAMMA_TABLE_45 */ - union { - struct { - uint32_t gamma_table88_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table89_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_45; - - /* 0xDB4 : BL_GAMMA_TABLE_46 */ - union { - struct { - uint32_t gamma_table90_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table91_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_46; - - /* 0xDB8 : BL_GAMMA_TABLE_47 */ - union { - struct { - uint32_t gamma_table92_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table93_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_47; - - /* 0xDBC : BL_GAMMA_TABLE_48 */ - union { - struct { - uint32_t gamma_table94_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table95_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_48; - - /* 0xDC0 : BL_GAMMA_TABLE_49 */ - union { - struct { - uint32_t gamma_table96_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table97_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_49; - - /* 0xDC4 : BL_GAMMA_TABLE_50 */ - union { - struct { - uint32_t gamma_table98_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table99_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_50; - - /* 0xDC8 : BL_GAMMA_TABLE_51 */ - union { - struct { - uint32_t gamma_table100_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table101_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_51; - - /* 0xDCC : BL_GAMMA_TABLE_52 */ - union { - struct { - uint32_t gamma_table102_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table103_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_52; - - /* 0xDD0 : BL_GAMMA_TABLE_53 */ - union { - struct { - uint32_t gamma_table104_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table105_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_53; - - /* 0xDD4 : BL_GAMMA_TABLE_54 */ - union { - struct { - uint32_t gamma_table106_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table107_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_54; - - /* 0xDD8 : BL_GAMMA_TABLE_55 */ - union { - struct { - uint32_t gamma_table108_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table109_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_55; - - /* 0xDDC : BL_GAMMA_TABLE_56 */ - union { - struct { - uint32_t gamma_table110_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table111_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_56; - - /* 0xDE0 : BL_GAMMA_TABLE_57 */ - union { - struct { - uint32_t gamma_table112_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table113_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_57; - - /* 0xDE4 : BL_GAMMA_TABLE_58 */ - union { - struct { - uint32_t gamma_table114_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table115_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_58; - - /* 0xDE8 : BL_GAMMA_TABLE_59 */ - union { - struct { - uint32_t gamma_table116_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table117_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_59; - - /* 0xDEC : BL_GAMMA_TABLE_60 */ - union { - struct { - uint32_t gamma_table118_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table119_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_60; - - /* 0xDF0 : BL_GAMMA_TABLE_61 */ - union { - struct { - uint32_t gamma_table120_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table121_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_61; - - /* 0xDF4 : BL_GAMMA_TABLE_62 */ - union { - struct { - uint32_t gamma_table122_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table123_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_62; - - /* 0xDF8 : BL_GAMMA_TABLE_63 */ - union { - struct { - uint32_t gamma_table124_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table125_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_63; - - /* 0xDFC : BL_GAMMA_TABLE_64 */ - union { - struct { - uint32_t gamma_table126_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table127_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_64; - - /* 0xE00 : BL_GAMMA_TABLE_65 */ - union { - struct { - uint32_t gamma_table128_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table129_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_65; - - /* 0xE04 : BL_GAMMA_TABLE_66 */ - union { - struct { - uint32_t gamma_table130_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table131_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_66; - - /* 0xE08 : BL_GAMMA_TABLE_67 */ - union { - struct { - uint32_t gamma_table132_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table133_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_67; - - /* 0xE0C : BL_GAMMA_TABLE_68 */ - union { - struct { - uint32_t gamma_table134_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table135_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_68; - - /* 0xE10 : BL_GAMMA_TABLE_69 */ - union { - struct { - uint32_t gamma_table136_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table137_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_69; - - /* 0xE14 : BL_GAMMA_TABLE_70 */ - union { - struct { - uint32_t gamma_table138_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table139_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_70; - - /* 0xE18 : BL_GAMMA_TABLE_71 */ - union { - struct { - uint32_t gamma_table140_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table141_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_71; - - /* 0xE1C : BL_GAMMA_TABLE_72 */ - union { - struct { - uint32_t gamma_table142_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table143_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_72; - - /* 0xE20 : BL_GAMMA_TABLE_73 */ - union { - struct { - uint32_t gamma_table144_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table145_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_73; - - /* 0xE24 : BL_GAMMA_TABLE_74 */ - union { - struct { - uint32_t gamma_table146_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table147_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_74; - - /* 0xE28 : BL_GAMMA_TABLE_75 */ - union { - struct { - uint32_t gamma_table148_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table149_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_75; - - /* 0xE2C : BL_GAMMA_TABLE_76 */ - union { - struct { - uint32_t gamma_table150_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table151_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_76; - - /* 0xE30 : BL_GAMMA_TABLE_77 */ - union { - struct { - uint32_t gamma_table152_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table153_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_77; - - /* 0xE34 : BL_GAMMA_TABLE_78 */ - union { - struct { - uint32_t gamma_table154_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table155_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_78; - - /* 0xE38 : BL_GAMMA_TABLE_79 */ - union { - struct { - uint32_t gamma_table156_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table157_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_79; - - /* 0xE3C : BL_GAMMA_TABLE_80 */ - union { - struct { - uint32_t gamma_table158_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table159_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_80; - - /* 0xE40 : BL_GAMMA_TABLE_81 */ - union { - struct { - uint32_t gamma_table160_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table161_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_81; - - /* 0xE44 : BL_GAMMA_TABLE_82 */ - union { - struct { - uint32_t gamma_table162_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table163_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_82; - - /* 0xE48 : BL_GAMMA_TABLE_83 */ - union { - struct { - uint32_t gamma_table164_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table165_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_83; - - /* 0xE4C : BL_GAMMA_TABLE_84 */ - union { - struct { - uint32_t gamma_table166_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table167_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_84; - - /* 0xE50 : BL_GAMMA_TABLE_85 */ - union { - struct { - uint32_t gamma_table168_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table169_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_85; - - /* 0xE54 : BL_GAMMA_TABLE_86 */ - union { - struct { - uint32_t gamma_table170_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table171_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_86; - - /* 0xE58 : BL_GAMMA_TABLE_87 */ - union { - struct { - uint32_t gamma_table172_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table173_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_87; - - /* 0xE5C : BL_GAMMA_TABLE_88 */ - union { - struct { - uint32_t gamma_table174_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table175_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_88; - - /* 0xE60 : BL_GAMMA_TABLE_89 */ - union { - struct { - uint32_t gamma_table176_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table177_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_89; - - /* 0xE64 : BL_GAMMA_TABLE_90 */ - union { - struct { - uint32_t gamma_table178_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table179_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_90; - - /* 0xE68 : BL_GAMMA_TABLE_91 */ - union { - struct { - uint32_t gamma_table180_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table181_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_91; - - /* 0xE6C : BL_GAMMA_TABLE_92 */ - union { - struct { - uint32_t gamma_table182_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table183_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_92; - - /* 0xE70 : BL_GAMMA_TABLE_93 */ - union { - struct { - uint32_t gamma_table184_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table185_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_93; - - /* 0xE74 : BL_GAMMA_TABLE_94 */ - union { - struct { - uint32_t gamma_table186_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table187_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_94; - - /* 0xE78 : BL_GAMMA_TABLE_95 */ - union { - struct { - uint32_t gamma_table188_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table189_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_95; - - /* 0xE7C : BL_GAMMA_TABLE_96 */ - union { - struct { - uint32_t gamma_table190_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table191_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_96; - - /* 0xE80 : BL_GAMMA_TABLE_97 */ - union { - struct { - uint32_t gamma_table192_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table193_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_97; - - /* 0xE84 : BL_GAMMA_TABLE_98 */ - union { - struct { - uint32_t gamma_table194_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table195_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_98; - - /* 0xE88 : BL_GAMMA_TABLE_99 */ - union { - struct { - uint32_t gamma_table196_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table197_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_99; - - /* 0xE8C : BL_GAMMA_TABLE_100 */ - union { - struct { - uint32_t gamma_table198_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table199_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_100; - - /* 0xE90 : BL_GAMMA_TABLE_101 */ - union { - struct { - uint32_t gamma_table200_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table201_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_101; - - /* 0xE94 : BL_GAMMA_TABLE_102 */ - union { - struct { - uint32_t gamma_table202_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table203_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_102; - - /* 0xE98 : BL_GAMMA_TABLE_103 */ - union { - struct { - uint32_t gamma_table204_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table205_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_103; - - /* 0xE9C : BL_GAMMA_TABLE_104 */ - union { - struct { - uint32_t gamma_table206_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table207_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_104; - - /* 0xEA0 : BL_GAMMA_TABLE_105 */ - union { - struct { - uint32_t gamma_table208_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table209_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_105; - - /* 0xEA4 : BL_GAMMA_TABLE_106 */ - union { - struct { - uint32_t gamma_table210_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table211_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_106; - - /* 0xEA8 : BL_GAMMA_TABLE_107 */ - union { - struct { - uint32_t gamma_table212_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table213_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_107; - - /* 0xEAC : BL_GAMMA_TABLE_108 */ - union { - struct { - uint32_t gamma_table214_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table215_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_108; - - /* 0xEB0 : BL_GAMMA_TABLE_109 */ - union { - struct { - uint32_t gamma_table216_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table217_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_109; - - /* 0xEB4 : BL_GAMMA_TABLE_110 */ - union { - struct { - uint32_t gamma_table218_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table219_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_110; - - /* 0xEB8 : BL_GAMMA_TABLE_111 */ - union { - struct { - uint32_t gamma_table220_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table221_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_111; - - /* 0xEBC : BL_GAMMA_TABLE_112 */ - union { - struct { - uint32_t gamma_table222_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table223_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_112; - - /* 0xEC0 : BL_GAMMA_TABLE_113 */ - union { - struct { - uint32_t gamma_table224_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table225_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_113; - - /* 0xEC4 : BL_GAMMA_TABLE_114 */ - union { - struct { - uint32_t gamma_table226_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table227_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_114; - - /* 0xEC8 : BL_GAMMA_TABLE_115 */ - union { - struct { - uint32_t gamma_table228_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table229_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_115; - - /* 0xECC : BL_GAMMA_TABLE_116 */ - union { - struct { - uint32_t gamma_table230_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table231_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_116; - - /* 0xED0 : BL_GAMMA_TABLE_117 */ - union { - struct { - uint32_t gamma_table232_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table233_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_117; - - /* 0xED4 : BL_GAMMA_TABLE_118 */ - union { - struct { - uint32_t gamma_table234_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table235_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_118; - - /* 0xED8 : BL_GAMMA_TABLE_119 */ - union { - struct { - uint32_t gamma_table236_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table237_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_119; - - /* 0xEDC : BL_GAMMA_TABLE_120 */ - union { - struct { - uint32_t gamma_table238_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table239_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_120; - - /* 0xEE0 : BL_GAMMA_TABLE_121 */ - union { - struct { - uint32_t gamma_table240_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table241_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_121; - - /* 0xEE4 : BL_GAMMA_TABLE_122 */ - union { - struct { - uint32_t gamma_table242_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table243_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_122; - - /* 0xEE8 : BL_GAMMA_TABLE_123 */ - union { - struct { - uint32_t gamma_table244_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table245_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_123; - - /* 0xEEC : BL_GAMMA_TABLE_124 */ - union { - struct { - uint32_t gamma_table246_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table247_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_124; - - /* 0xEF0 : BL_GAMMA_TABLE_125 */ - union { - struct { - uint32_t gamma_table248_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table249_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_125; - - /* 0xEF4 : BL_GAMMA_TABLE_126 */ - union { - struct { - uint32_t gamma_table250_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table251_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_126; - - /* 0xEF8 : BL_GAMMA_TABLE_127 */ - union { - struct { - uint32_t gamma_table252_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table253_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_127; - - /* 0xEFC : BL_GAMMA_TABLE_128 */ - union { - struct { - uint32_t gamma_table254_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t gamma_table255_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BL_GAMMA_TABLE_128; - - /* 0xF00 : CC_OFFSET_0 */ - union { - struct { - uint32_t cc_pre_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cc_pre_offset1_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t cc_enable_pre : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } CC_OFFSET_0; - - /* 0xF04 : CC_OFFSET_1 */ - union { - struct { - uint32_t cc_pre_offset2_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cc_post_offset2_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_OFFSET_1; - - /* 0xF08 : CC_OFFSET_2 */ - union { - struct { - uint32_t cc_post_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t cc_post_offset1_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_OFFSET_2; - - /* 0xF0C : CC_MATRIX_0 */ - union { - struct { - uint32_t cc_matrix00_pre : 12; /* [11: 0], r/w, 0x200 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix01_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_0; - - /* 0xF10 : CC_MATRIX_1 */ - union { - struct { - uint32_t cc_matrix10_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix02_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_1; - - /* 0xF14 : CC_MATRIX_2 */ - union { - struct { - uint32_t cc_matrix11_pre : 12; /* [11: 0], r/w, 0x200 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix12_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_2; - - /* 0xF18 : CC_MATRIX_3 */ - union { - struct { - uint32_t cc_matrix20_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cc_matrix21_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_MATRIX_3; - - /* 0xF1C : CC_CE_MATRIX */ - union { - struct { - uint32_t cc_matrix22_pre : 12; /* [11: 0], r/w, 0x200 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix02_pre : 12; /* [27:16], r/w, 0x3a */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CC_CE_MATRIX; - - /* 0xF20 : CE_MATRIX_0 */ - union { - struct { - uint32_t ce_matrix00_pre : 12; /* [11: 0], r/w, 0x99 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix01_pre : 12; /* [27:16], r/w, 0x12d */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_0; - - /* 0xF24 : CE_MATRIX_1 */ - union { - struct { - uint32_t ce_matrix10_pre : 12; /* [11: 0], r/w, 0xfa9 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix11_pre : 12; /* [27:16], r/w, 0xf57 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_1; - - /* 0xF28 : CE_MATRIX_2 */ - union { - struct { - uint32_t ce_matrix20_pre : 12; /* [11: 0], r/w, 0x100 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix12_pre : 12; /* [27:16], r/w, 0x100 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_2; - - /* 0xF2C : CE_MATRIX_3 */ - union { - struct { - uint32_t ce_matrix21_pre : 12; /* [11: 0], r/w, 0xf29 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t ce_matrix22_pre : 12; /* [27:16], r/w, 0xfd7 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_MATRIX_3; - - /* 0xF30 : CE_OFFSET_0 */ - union { - struct { - uint32_t ce_pre_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t ce_pre_offset1_pre : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_OFFSET_0; - - /* 0xF34 : CE_OFFSET_1 */ - union { - struct { - uint32_t ce_pre_offset2_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t ce_post_offset2_pre : 13; /* [28:16], r/w, 0x800 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_OFFSET_1; - - /* 0xF38 : CE_OFFSET_2 */ - union { - struct { - uint32_t ce_post_offset0_pre : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t ce_post_offset1_pre : 13; /* [28:16], r/w, 0x800 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } CE_OFFSET_2; -}; - -typedef volatile struct dsp2_blback_reg dsp2_blback_reg_t; - -#endif /* __DSP2_BLBACK_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_front_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_front_reg.h deleted file mode 100644 index f3f6383110..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_front_reg.h +++ /dev/null @@ -1,346 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_front_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_FRONT_REG_H__ -#define __DSP2_FRONT_REG_H__ - -#include "bl808.h" - -/* 0x110 : pattern_mode */ -#define DSP2_FRONT_PATTERN_MODE_OFFSET (0x110) -#define DSP2_FRONT_PATTERN_MODE_W DSP2_FRONT_PATTERN_MODE_W -#define DSP2_FRONT_PATTERN_MODE_W_POS (0U) -#define DSP2_FRONT_PATTERN_MODE_W_LEN (3U) -#define DSP2_FRONT_PATTERN_MODE_W_MSK (((1U << DSP2_FRONT_PATTERN_MODE_W_LEN) - 1) << DSP2_FRONT_PATTERN_MODE_W_POS) -#define DSP2_FRONT_PATTERN_MODE_W_UMSK (~(((1U << DSP2_FRONT_PATTERN_MODE_W_LEN) - 1) << DSP2_FRONT_PATTERN_MODE_W_POS)) -#define DSP2_FRONT_PID_INV_RGB_PRE DSP2_FRONT_PID_INV_RGB_PRE -#define DSP2_FRONT_PID_INV_RGB_PRE_POS (8U) -#define DSP2_FRONT_PID_INV_RGB_PRE_LEN (1U) -#define DSP2_FRONT_PID_INV_RGB_PRE_MSK (((1U << DSP2_FRONT_PID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_PID_INV_RGB_PRE_POS) -#define DSP2_FRONT_PID_INV_RGB_PRE_UMSK (~(((1U << DSP2_FRONT_PID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_PID_INV_RGB_PRE_POS)) -#define DSP2_FRONT_LID_INV_RGB_PRE DSP2_FRONT_LID_INV_RGB_PRE -#define DSP2_FRONT_LID_INV_RGB_PRE_POS (9U) -#define DSP2_FRONT_LID_INV_RGB_PRE_LEN (1U) -#define DSP2_FRONT_LID_INV_RGB_PRE_MSK (((1U << DSP2_FRONT_LID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_LID_INV_RGB_PRE_POS) -#define DSP2_FRONT_LID_INV_RGB_PRE_UMSK (~(((1U << DSP2_FRONT_LID_INV_RGB_PRE_LEN) - 1) << DSP2_FRONT_LID_INV_RGB_PRE_POS)) -#define DSP2_FRONT_REG_BL_LPID_SEL_W DSP2_FRONT_REG_BL_LPID_SEL_W -#define DSP2_FRONT_REG_BL_LPID_SEL_W_POS (10U) -#define DSP2_FRONT_REG_BL_LPID_SEL_W_LEN (1U) -#define DSP2_FRONT_REG_BL_LPID_SEL_W_MSK (((1U << DSP2_FRONT_REG_BL_LPID_SEL_W_LEN) - 1) << DSP2_FRONT_REG_BL_LPID_SEL_W_POS) -#define DSP2_FRONT_REG_BL_LPID_SEL_W_UMSK (~(((1U << DSP2_FRONT_REG_BL_LPID_SEL_W_LEN) - 1) << DSP2_FRONT_REG_BL_LPID_SEL_W_POS)) -#define DSP2_FRONT_ACT_HSIZE_W DSP2_FRONT_ACT_HSIZE_W -#define DSP2_FRONT_ACT_HSIZE_W_POS (16U) -#define DSP2_FRONT_ACT_HSIZE_W_LEN (16U) -#define DSP2_FRONT_ACT_HSIZE_W_MSK (((1U << DSP2_FRONT_ACT_HSIZE_W_LEN) - 1) << DSP2_FRONT_ACT_HSIZE_W_POS) -#define DSP2_FRONT_ACT_HSIZE_W_UMSK (~(((1U << DSP2_FRONT_ACT_HSIZE_W_LEN) - 1) << DSP2_FRONT_ACT_HSIZE_W_POS)) - -/* 0x114 : clamp_R_Gr */ -#define DSP2_FRONT_CLAMP_R_GR_OFFSET (0x114) -#define DSP2_FRONT_CLP_R_PRE DSP2_FRONT_CLP_R_PRE -#define DSP2_FRONT_CLP_R_PRE_POS (0U) -#define DSP2_FRONT_CLP_R_PRE_LEN (16U) -#define DSP2_FRONT_CLP_R_PRE_MSK (((1U << DSP2_FRONT_CLP_R_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_PRE_POS) -#define DSP2_FRONT_CLP_R_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_R_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_PRE_POS)) -#define DSP2_FRONT_CLP_GR_PRE DSP2_FRONT_CLP_GR_PRE -#define DSP2_FRONT_CLP_GR_PRE_POS (16U) -#define DSP2_FRONT_CLP_GR_PRE_LEN (16U) -#define DSP2_FRONT_CLP_GR_PRE_MSK (((1U << DSP2_FRONT_CLP_GR_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_PRE_POS) -#define DSP2_FRONT_CLP_GR_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GR_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_PRE_POS)) - -/* 0x118 : clamp_B_Gb */ -#define DSP2_FRONT_CLAMP_B_GB_OFFSET (0x118) -#define DSP2_FRONT_CLP_GB_PRE DSP2_FRONT_CLP_GB_PRE -#define DSP2_FRONT_CLP_GB_PRE_POS (0U) -#define DSP2_FRONT_CLP_GB_PRE_LEN (16U) -#define DSP2_FRONT_CLP_GB_PRE_MSK (((1U << DSP2_FRONT_CLP_GB_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_PRE_POS) -#define DSP2_FRONT_CLP_GB_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GB_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_PRE_POS)) -#define DSP2_FRONT_CLP_B_PRE DSP2_FRONT_CLP_B_PRE -#define DSP2_FRONT_CLP_B_PRE_POS (16U) -#define DSP2_FRONT_CLP_B_PRE_LEN (16U) -#define DSP2_FRONT_CLP_B_PRE_MSK (((1U << DSP2_FRONT_CLP_B_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_PRE_POS) -#define DSP2_FRONT_CLP_B_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_B_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_PRE_POS)) - -/* 0x130 : ob_win */ -#define DSP2_FRONT_OB_WIN_OFFSET (0x130) -#define DSP2_FRONT_OB_WIN_STARTX_W DSP2_FRONT_OB_WIN_STARTX_W -#define DSP2_FRONT_OB_WIN_STARTX_W_POS (0U) -#define DSP2_FRONT_OB_WIN_STARTX_W_LEN (16U) -#define DSP2_FRONT_OB_WIN_STARTX_W_MSK (((1U << DSP2_FRONT_OB_WIN_STARTX_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTX_W_POS) -#define DSP2_FRONT_OB_WIN_STARTX_W_UMSK (~(((1U << DSP2_FRONT_OB_WIN_STARTX_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTX_W_POS)) -#define DSP2_FRONT_OB_WIN_STARTY_W DSP2_FRONT_OB_WIN_STARTY_W -#define DSP2_FRONT_OB_WIN_STARTY_W_POS (16U) -#define DSP2_FRONT_OB_WIN_STARTY_W_LEN (16U) -#define DSP2_FRONT_OB_WIN_STARTY_W_MSK (((1U << DSP2_FRONT_OB_WIN_STARTY_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTY_W_POS) -#define DSP2_FRONT_OB_WIN_STARTY_W_UMSK (~(((1U << DSP2_FRONT_OB_WIN_STARTY_W_LEN) - 1) << DSP2_FRONT_OB_WIN_STARTY_W_POS)) - -/* 0x134 : black_columns_bit */ -#define DSP2_FRONT_BLACK_COLUMNS_BIT_OFFSET (0x134) -#define DSP2_FRONT_BLACK_ROWS_BIT_W DSP2_FRONT_BLACK_ROWS_BIT_W -#define DSP2_FRONT_BLACK_ROWS_BIT_W_POS (0U) -#define DSP2_FRONT_BLACK_ROWS_BIT_W_LEN (4U) -#define DSP2_FRONT_BLACK_ROWS_BIT_W_MSK (((1U << DSP2_FRONT_BLACK_ROWS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_ROWS_BIT_W_POS) -#define DSP2_FRONT_BLACK_ROWS_BIT_W_UMSK (~(((1U << DSP2_FRONT_BLACK_ROWS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_ROWS_BIT_W_POS)) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W DSP2_FRONT_BLACK_COLUMNS_BIT_W -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_POS (4U) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_LEN (4U) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_MSK (((1U << DSP2_FRONT_BLACK_COLUMNS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_COLUMNS_BIT_W_POS) -#define DSP2_FRONT_BLACK_COLUMNS_BIT_W_UMSK (~(((1U << DSP2_FRONT_BLACK_COLUMNS_BIT_W_LEN) - 1) << DSP2_FRONT_BLACK_COLUMNS_BIT_W_POS)) - -/* 0x138 : Ob_R_Gr */ -#define DSP2_FRONT_OB_R_GR_OFFSET (0x138) -#define DSP2_FRONT_OB_R_R DSP2_FRONT_OB_R_R -#define DSP2_FRONT_OB_R_R_POS (0U) -#define DSP2_FRONT_OB_R_R_LEN (16U) -#define DSP2_FRONT_OB_R_R_MSK (((1U << DSP2_FRONT_OB_R_R_LEN) - 1) << DSP2_FRONT_OB_R_R_POS) -#define DSP2_FRONT_OB_R_R_UMSK (~(((1U << DSP2_FRONT_OB_R_R_LEN) - 1) << DSP2_FRONT_OB_R_R_POS)) -#define DSP2_FRONT_OB_GR_R DSP2_FRONT_OB_GR_R -#define DSP2_FRONT_OB_GR_R_POS (16U) -#define DSP2_FRONT_OB_GR_R_LEN (16U) -#define DSP2_FRONT_OB_GR_R_MSK (((1U << DSP2_FRONT_OB_GR_R_LEN) - 1) << DSP2_FRONT_OB_GR_R_POS) -#define DSP2_FRONT_OB_GR_R_UMSK (~(((1U << DSP2_FRONT_OB_GR_R_LEN) - 1) << DSP2_FRONT_OB_GR_R_POS)) - -/* 0x13C : Ob_B_Gb */ -#define DSP2_FRONT_OB_B_GB_OFFSET (0x13C) -#define DSP2_FRONT_OB_GB_R DSP2_FRONT_OB_GB_R -#define DSP2_FRONT_OB_GB_R_POS (0U) -#define DSP2_FRONT_OB_GB_R_LEN (16U) -#define DSP2_FRONT_OB_GB_R_MSK (((1U << DSP2_FRONT_OB_GB_R_LEN) - 1) << DSP2_FRONT_OB_GB_R_POS) -#define DSP2_FRONT_OB_GB_R_UMSK (~(((1U << DSP2_FRONT_OB_GB_R_LEN) - 1) << DSP2_FRONT_OB_GB_R_POS)) -#define DSP2_FRONT_OB_B_R DSP2_FRONT_OB_B_R -#define DSP2_FRONT_OB_B_R_POS (16U) -#define DSP2_FRONT_OB_B_R_LEN (16U) -#define DSP2_FRONT_OB_B_R_MSK (((1U << DSP2_FRONT_OB_B_R_LEN) - 1) << DSP2_FRONT_OB_B_R_POS) -#define DSP2_FRONT_OB_B_R_UMSK (~(((1U << DSP2_FRONT_OB_B_R_LEN) - 1) << DSP2_FRONT_OB_B_R_POS)) - -/* 0x150 : gain_R_G */ -#define DSP2_FRONT_GAIN_R_G_OFFSET (0x150) -#define DSP2_FRONT_RGAIN1_PRE DSP2_FRONT_RGAIN1_PRE -#define DSP2_FRONT_RGAIN1_PRE_POS (0U) -#define DSP2_FRONT_RGAIN1_PRE_LEN (11U) -#define DSP2_FRONT_RGAIN1_PRE_MSK (((1U << DSP2_FRONT_RGAIN1_PRE_LEN) - 1) << DSP2_FRONT_RGAIN1_PRE_POS) -#define DSP2_FRONT_RGAIN1_PRE_UMSK (~(((1U << DSP2_FRONT_RGAIN1_PRE_LEN) - 1) << DSP2_FRONT_RGAIN1_PRE_POS)) -#define DSP2_FRONT_GGAIN1_PRE DSP2_FRONT_GGAIN1_PRE -#define DSP2_FRONT_GGAIN1_PRE_POS (16U) -#define DSP2_FRONT_GGAIN1_PRE_LEN (11U) -#define DSP2_FRONT_GGAIN1_PRE_MSK (((1U << DSP2_FRONT_GGAIN1_PRE_LEN) - 1) << DSP2_FRONT_GGAIN1_PRE_POS) -#define DSP2_FRONT_GGAIN1_PRE_UMSK (~(((1U << DSP2_FRONT_GGAIN1_PRE_LEN) - 1) << DSP2_FRONT_GGAIN1_PRE_POS)) - -/* 0x154 : gain_B */ -#define DSP2_FRONT_GAIN_B_OFFSET (0x154) -#define DSP2_FRONT_BGAIN1_PRE DSP2_FRONT_BGAIN1_PRE -#define DSP2_FRONT_BGAIN1_PRE_POS (0U) -#define DSP2_FRONT_BGAIN1_PRE_LEN (11U) -#define DSP2_FRONT_BGAIN1_PRE_MSK (((1U << DSP2_FRONT_BGAIN1_PRE_LEN) - 1) << DSP2_FRONT_BGAIN1_PRE_POS) -#define DSP2_FRONT_BGAIN1_PRE_UMSK (~(((1U << DSP2_FRONT_BGAIN1_PRE_LEN) - 1) << DSP2_FRONT_BGAIN1_PRE_POS)) - -/* 0x1D0 : clp_rgr_gain */ -#define DSP2_FRONT_CLP_RGR_GAIN_OFFSET (0x1D0) -#define DSP2_FRONT_CLP_GR_GAIN_PRE DSP2_FRONT_CLP_GR_GAIN_PRE -#define DSP2_FRONT_CLP_GR_GAIN_PRE_POS (0U) -#define DSP2_FRONT_CLP_GR_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_GR_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_GR_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_GR_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GR_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GR_GAIN_PRE_POS)) -#define DSP2_FRONT_CLP_R_GAIN_PRE DSP2_FRONT_CLP_R_GAIN_PRE -#define DSP2_FRONT_CLP_R_GAIN_PRE_POS (16U) -#define DSP2_FRONT_CLP_R_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_R_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_R_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_R_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_R_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_R_GAIN_PRE_POS)) -#define DSP2_FRONT_CLP_GAIN_EN_PRE DSP2_FRONT_CLP_GAIN_EN_PRE -#define DSP2_FRONT_CLP_GAIN_EN_PRE_POS (31U) -#define DSP2_FRONT_CLP_GAIN_EN_PRE_LEN (1U) -#define DSP2_FRONT_CLP_GAIN_EN_PRE_MSK (((1U << DSP2_FRONT_CLP_GAIN_EN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GAIN_EN_PRE_POS) -#define DSP2_FRONT_CLP_GAIN_EN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GAIN_EN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GAIN_EN_PRE_POS)) - -/* 0x1D4 : clp_bgb_gain */ -#define DSP2_FRONT_CLP_BGB_GAIN_OFFSET (0x1D4) -#define DSP2_FRONT_CLP_GB_GAIN_PRE DSP2_FRONT_CLP_GB_GAIN_PRE -#define DSP2_FRONT_CLP_GB_GAIN_PRE_POS (0U) -#define DSP2_FRONT_CLP_GB_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_GB_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_GB_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_GB_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_GB_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_GB_GAIN_PRE_POS)) -#define DSP2_FRONT_CLP_B_GAIN_PRE DSP2_FRONT_CLP_B_GAIN_PRE -#define DSP2_FRONT_CLP_B_GAIN_PRE_POS (16U) -#define DSP2_FRONT_CLP_B_GAIN_PRE_LEN (15U) -#define DSP2_FRONT_CLP_B_GAIN_PRE_MSK (((1U << DSP2_FRONT_CLP_B_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_GAIN_PRE_POS) -#define DSP2_FRONT_CLP_B_GAIN_PRE_UMSK (~(((1U << DSP2_FRONT_CLP_B_GAIN_PRE_LEN) - 1) << DSP2_FRONT_CLP_B_GAIN_PRE_POS)) - -/* 0x1F0 : Image_select */ -#define DSP2_FRONT_IMAGE_SELECT_OFFSET (0x1F0) -#define DSP2_FRONT_IMAGE_SELECT_PRE DSP2_FRONT_IMAGE_SELECT_PRE -#define DSP2_FRONT_IMAGE_SELECT_PRE_POS (0U) -#define DSP2_FRONT_IMAGE_SELECT_PRE_LEN (2U) -#define DSP2_FRONT_IMAGE_SELECT_PRE_MSK (((1U << DSP2_FRONT_IMAGE_SELECT_PRE_LEN) - 1) << DSP2_FRONT_IMAGE_SELECT_PRE_POS) -#define DSP2_FRONT_IMAGE_SELECT_PRE_UMSK (~(((1U << DSP2_FRONT_IMAGE_SELECT_PRE_LEN) - 1) << DSP2_FRONT_IMAGE_SELECT_PRE_POS)) - -struct dsp2_front_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[272]; - - /* 0x110 : pattern_mode */ - union { - struct { - uint32_t pattern_mode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t pid_inv_rgb_pre : 1; /* [ 8], r/w, 0x0 */ - uint32_t lid_inv_rgb_pre : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_bl_lpid_sel_w : 1; /* [ 10], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t act_hsize_w : 16; /* [31:16], r/w, 0x788 */ - } BF; - uint32_t WORD; - } pattern_mode; - - /* 0x114 : clamp_R_Gr */ - union { - struct { - uint32_t clp_R_pre : 16; /* [15: 0], r/w, 0x0 */ - uint32_t clp_Gr_pre : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } clamp_R_Gr; - - /* 0x118 : clamp_B_Gb */ - union { - struct { - uint32_t clp_Gb_pre : 16; /* [15: 0], r/w, 0x0 */ - uint32_t clp_B_pre : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } clamp_B_Gb; - - /* 0x11c reserved */ - uint8_t RESERVED0x11c[20]; - - /* 0x130 : ob_win */ - union { - struct { - uint32_t ob_win_startx_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t ob_win_starty_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } ob_win; - - /* 0x134 : black_columns_bit */ - union { - struct { - uint32_t black_rows_bit_w : 4; /* [ 3: 0], r/w, 0x2 */ - uint32_t black_columns_bit_w : 4; /* [ 7: 4], r/w, 0x8 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } black_columns_bit; - - /* 0x138 : Ob_R_Gr */ - union { - struct { - uint32_t Ob_R_r : 16; /* [15: 0], r, 0x0 */ - uint32_t Ob_Gr_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } Ob_R_Gr; - - /* 0x13C : Ob_B_Gb */ - union { - struct { - uint32_t Ob_Gb_r : 16; /* [15: 0], r, 0x0 */ - uint32_t Ob_B_r : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } Ob_B_Gb; - - /* 0x140 reserved */ - uint8_t RESERVED0x140[16]; - - /* 0x150 : gain_R_G */ - union { - struct { - uint32_t rgain1_pre : 11; /* [10: 0], r/w, 0x80 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ggain1_pre : 11; /* [26:16], r/w, 0x80 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gain_R_G; - - /* 0x154 : gain_B */ - union { - struct { - uint32_t bgain1_pre : 11; /* [10: 0], r/w, 0x80 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } gain_B; - - /* 0x158 reserved */ - uint8_t RESERVED0x158[120]; - - /* 0x1D0 : clp_rgr_gain */ - union { - struct { - uint32_t clp_gr_gain_pre : 15; /* [14: 0], r/w, 0x1000 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t clp_r_gain_pre : 15; /* [30:16], r/w, 0x1000 */ - uint32_t clp_gain_en_pre : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } clp_rgr_gain; - - /* 0x1D4 : clp_bgb_gain */ - union { - struct { - uint32_t clp_gb_gain_pre : 15; /* [14: 0], r/w, 0x1000 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t clp_b_gain_pre : 15; /* [30:16], r/w, 0x1000 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } clp_bgb_gain; - - /* 0x1d8 reserved */ - uint8_t RESERVED0x1d8[24]; - - /* 0x1F0 : Image_select */ - union { - struct { - uint32_t Image_Select_pre : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } Image_select; -}; - -typedef volatile struct dsp2_front_reg dsp2_front_reg_t; - -#endif /* __DSP2_FRONT_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_gamma_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_gamma_reg.h deleted file mode 100644 index 6b0ffa8ec5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_gamma_reg.h +++ /dev/null @@ -1,2288 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_gamma_reg.h - * @version V1.0 - * @date 2021-02-05 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_GAMMA_REG_H__ -#define __DSP2_GAMMA_REG_H__ - -#include "bl808.h" - -/* 0x700 : GAMMA_CRUVE_1 */ -#define DSP2_GAMMA_GAMMA_CRUVE_1_OFFSET (0x700) -#define DSP2_GAMMA_C0_PRE DSP2_GAMMA_C0_PRE -#define DSP2_GAMMA_C0_PRE_POS (0U) -#define DSP2_GAMMA_C0_PRE_LEN (8U) -#define DSP2_GAMMA_C0_PRE_MSK (((1U << DSP2_GAMMA_C0_PRE_LEN) - 1) << DSP2_GAMMA_C0_PRE_POS) -#define DSP2_GAMMA_C0_PRE_UMSK (~(((1U << DSP2_GAMMA_C0_PRE_LEN) - 1) << DSP2_GAMMA_C0_PRE_POS)) -#define DSP2_GAMMA_C1_PRE DSP2_GAMMA_C1_PRE -#define DSP2_GAMMA_C1_PRE_POS (8U) -#define DSP2_GAMMA_C1_PRE_LEN (8U) -#define DSP2_GAMMA_C1_PRE_MSK (((1U << DSP2_GAMMA_C1_PRE_LEN) - 1) << DSP2_GAMMA_C1_PRE_POS) -#define DSP2_GAMMA_C1_PRE_UMSK (~(((1U << DSP2_GAMMA_C1_PRE_LEN) - 1) << DSP2_GAMMA_C1_PRE_POS)) -#define DSP2_GAMMA_C2_PRE DSP2_GAMMA_C2_PRE -#define DSP2_GAMMA_C2_PRE_POS (16U) -#define DSP2_GAMMA_C2_PRE_LEN (8U) -#define DSP2_GAMMA_C2_PRE_MSK (((1U << DSP2_GAMMA_C2_PRE_LEN) - 1) << DSP2_GAMMA_C2_PRE_POS) -#define DSP2_GAMMA_C2_PRE_UMSK (~(((1U << DSP2_GAMMA_C2_PRE_LEN) - 1) << DSP2_GAMMA_C2_PRE_POS)) -#define DSP2_GAMMA_C3_PRE DSP2_GAMMA_C3_PRE -#define DSP2_GAMMA_C3_PRE_POS (24U) -#define DSP2_GAMMA_C3_PRE_LEN (8U) -#define DSP2_GAMMA_C3_PRE_MSK (((1U << DSP2_GAMMA_C3_PRE_LEN) - 1) << DSP2_GAMMA_C3_PRE_POS) -#define DSP2_GAMMA_C3_PRE_UMSK (~(((1U << DSP2_GAMMA_C3_PRE_LEN) - 1) << DSP2_GAMMA_C3_PRE_POS)) - -/* 0x704 : GAMMA_CRUVE_2 */ -#define DSP2_GAMMA_GAMMA_CRUVE_2_OFFSET (0x704) -#define DSP2_GAMMA_C4_PRE DSP2_GAMMA_C4_PRE -#define DSP2_GAMMA_C4_PRE_POS (0U) -#define DSP2_GAMMA_C4_PRE_LEN (8U) -#define DSP2_GAMMA_C4_PRE_MSK (((1U << DSP2_GAMMA_C4_PRE_LEN) - 1) << DSP2_GAMMA_C4_PRE_POS) -#define DSP2_GAMMA_C4_PRE_UMSK (~(((1U << DSP2_GAMMA_C4_PRE_LEN) - 1) << DSP2_GAMMA_C4_PRE_POS)) -#define DSP2_GAMMA_C5_PRE DSP2_GAMMA_C5_PRE -#define DSP2_GAMMA_C5_PRE_POS (8U) -#define DSP2_GAMMA_C5_PRE_LEN (8U) -#define DSP2_GAMMA_C5_PRE_MSK (((1U << DSP2_GAMMA_C5_PRE_LEN) - 1) << DSP2_GAMMA_C5_PRE_POS) -#define DSP2_GAMMA_C5_PRE_UMSK (~(((1U << DSP2_GAMMA_C5_PRE_LEN) - 1) << DSP2_GAMMA_C5_PRE_POS)) -#define DSP2_GAMMA_C6_PRE DSP2_GAMMA_C6_PRE -#define DSP2_GAMMA_C6_PRE_POS (16U) -#define DSP2_GAMMA_C6_PRE_LEN (8U) -#define DSP2_GAMMA_C6_PRE_MSK (((1U << DSP2_GAMMA_C6_PRE_LEN) - 1) << DSP2_GAMMA_C6_PRE_POS) -#define DSP2_GAMMA_C6_PRE_UMSK (~(((1U << DSP2_GAMMA_C6_PRE_LEN) - 1) << DSP2_GAMMA_C6_PRE_POS)) -#define DSP2_GAMMA_C7_PRE DSP2_GAMMA_C7_PRE -#define DSP2_GAMMA_C7_PRE_POS (24U) -#define DSP2_GAMMA_C7_PRE_LEN (8U) -#define DSP2_GAMMA_C7_PRE_MSK (((1U << DSP2_GAMMA_C7_PRE_LEN) - 1) << DSP2_GAMMA_C7_PRE_POS) -#define DSP2_GAMMA_C7_PRE_UMSK (~(((1U << DSP2_GAMMA_C7_PRE_LEN) - 1) << DSP2_GAMMA_C7_PRE_POS)) - -/* 0x708 : GAMMA_CRUVE_3 */ -#define DSP2_GAMMA_GAMMA_CRUVE_3_OFFSET (0x708) -#define DSP2_GAMMA_C8_PRE DSP2_GAMMA_C8_PRE -#define DSP2_GAMMA_C8_PRE_POS (0U) -#define DSP2_GAMMA_C8_PRE_LEN (8U) -#define DSP2_GAMMA_C8_PRE_MSK (((1U << DSP2_GAMMA_C8_PRE_LEN) - 1) << DSP2_GAMMA_C8_PRE_POS) -#define DSP2_GAMMA_C8_PRE_UMSK (~(((1U << DSP2_GAMMA_C8_PRE_LEN) - 1) << DSP2_GAMMA_C8_PRE_POS)) -#define DSP2_GAMMA_C9_PRE DSP2_GAMMA_C9_PRE -#define DSP2_GAMMA_C9_PRE_POS (8U) -#define DSP2_GAMMA_C9_PRE_LEN (8U) -#define DSP2_GAMMA_C9_PRE_MSK (((1U << DSP2_GAMMA_C9_PRE_LEN) - 1) << DSP2_GAMMA_C9_PRE_POS) -#define DSP2_GAMMA_C9_PRE_UMSK (~(((1U << DSP2_GAMMA_C9_PRE_LEN) - 1) << DSP2_GAMMA_C9_PRE_POS)) -#define DSP2_GAMMA_C10_PRE DSP2_GAMMA_C10_PRE -#define DSP2_GAMMA_C10_PRE_POS (16U) -#define DSP2_GAMMA_C10_PRE_LEN (8U) -#define DSP2_GAMMA_C10_PRE_MSK (((1U << DSP2_GAMMA_C10_PRE_LEN) - 1) << DSP2_GAMMA_C10_PRE_POS) -#define DSP2_GAMMA_C10_PRE_UMSK (~(((1U << DSP2_GAMMA_C10_PRE_LEN) - 1) << DSP2_GAMMA_C10_PRE_POS)) -#define DSP2_GAMMA_C11_PRE DSP2_GAMMA_C11_PRE -#define DSP2_GAMMA_C11_PRE_POS (24U) -#define DSP2_GAMMA_C11_PRE_LEN (8U) -#define DSP2_GAMMA_C11_PRE_MSK (((1U << DSP2_GAMMA_C11_PRE_LEN) - 1) << DSP2_GAMMA_C11_PRE_POS) -#define DSP2_GAMMA_C11_PRE_UMSK (~(((1U << DSP2_GAMMA_C11_PRE_LEN) - 1) << DSP2_GAMMA_C11_PRE_POS)) - -/* 0x70C : GAMMA_CRUVE_4 */ -#define DSP2_GAMMA_GAMMA_CRUVE_4_OFFSET (0x70C) -#define DSP2_GAMMA_C12_PRE DSP2_GAMMA_C12_PRE -#define DSP2_GAMMA_C12_PRE_POS (0U) -#define DSP2_GAMMA_C12_PRE_LEN (8U) -#define DSP2_GAMMA_C12_PRE_MSK (((1U << DSP2_GAMMA_C12_PRE_LEN) - 1) << DSP2_GAMMA_C12_PRE_POS) -#define DSP2_GAMMA_C12_PRE_UMSK (~(((1U << DSP2_GAMMA_C12_PRE_LEN) - 1) << DSP2_GAMMA_C12_PRE_POS)) -#define DSP2_GAMMA_C13_PRE DSP2_GAMMA_C13_PRE -#define DSP2_GAMMA_C13_PRE_POS (8U) -#define DSP2_GAMMA_C13_PRE_LEN (8U) -#define DSP2_GAMMA_C13_PRE_MSK (((1U << DSP2_GAMMA_C13_PRE_LEN) - 1) << DSP2_GAMMA_C13_PRE_POS) -#define DSP2_GAMMA_C13_PRE_UMSK (~(((1U << DSP2_GAMMA_C13_PRE_LEN) - 1) << DSP2_GAMMA_C13_PRE_POS)) -#define DSP2_GAMMA_C14_PRE DSP2_GAMMA_C14_PRE -#define DSP2_GAMMA_C14_PRE_POS (16U) -#define DSP2_GAMMA_C14_PRE_LEN (8U) -#define DSP2_GAMMA_C14_PRE_MSK (((1U << DSP2_GAMMA_C14_PRE_LEN) - 1) << DSP2_GAMMA_C14_PRE_POS) -#define DSP2_GAMMA_C14_PRE_UMSK (~(((1U << DSP2_GAMMA_C14_PRE_LEN) - 1) << DSP2_GAMMA_C14_PRE_POS)) -#define DSP2_GAMMA_C15_PRE DSP2_GAMMA_C15_PRE -#define DSP2_GAMMA_C15_PRE_POS (24U) -#define DSP2_GAMMA_C15_PRE_LEN (8U) -#define DSP2_GAMMA_C15_PRE_MSK (((1U << DSP2_GAMMA_C15_PRE_LEN) - 1) << DSP2_GAMMA_C15_PRE_POS) -#define DSP2_GAMMA_C15_PRE_UMSK (~(((1U << DSP2_GAMMA_C15_PRE_LEN) - 1) << DSP2_GAMMA_C15_PRE_POS)) - -/* 0x710 : GAMMA_CRUVE_5 */ -#define DSP2_GAMMA_GAMMA_CRUVE_5_OFFSET (0x710) -#define DSP2_GAMMA_C16_PRE DSP2_GAMMA_C16_PRE -#define DSP2_GAMMA_C16_PRE_POS (0U) -#define DSP2_GAMMA_C16_PRE_LEN (8U) -#define DSP2_GAMMA_C16_PRE_MSK (((1U << DSP2_GAMMA_C16_PRE_LEN) - 1) << DSP2_GAMMA_C16_PRE_POS) -#define DSP2_GAMMA_C16_PRE_UMSK (~(((1U << DSP2_GAMMA_C16_PRE_LEN) - 1) << DSP2_GAMMA_C16_PRE_POS)) -#define DSP2_GAMMA_C17_PRE DSP2_GAMMA_C17_PRE -#define DSP2_GAMMA_C17_PRE_POS (8U) -#define DSP2_GAMMA_C17_PRE_LEN (8U) -#define DSP2_GAMMA_C17_PRE_MSK (((1U << DSP2_GAMMA_C17_PRE_LEN) - 1) << DSP2_GAMMA_C17_PRE_POS) -#define DSP2_GAMMA_C17_PRE_UMSK (~(((1U << DSP2_GAMMA_C17_PRE_LEN) - 1) << DSP2_GAMMA_C17_PRE_POS)) -#define DSP2_GAMMA_C18_PRE DSP2_GAMMA_C18_PRE -#define DSP2_GAMMA_C18_PRE_POS (16U) -#define DSP2_GAMMA_C18_PRE_LEN (8U) -#define DSP2_GAMMA_C18_PRE_MSK (((1U << DSP2_GAMMA_C18_PRE_LEN) - 1) << DSP2_GAMMA_C18_PRE_POS) -#define DSP2_GAMMA_C18_PRE_UMSK (~(((1U << DSP2_GAMMA_C18_PRE_LEN) - 1) << DSP2_GAMMA_C18_PRE_POS)) -#define DSP2_GAMMA_C19_PRE DSP2_GAMMA_C19_PRE -#define DSP2_GAMMA_C19_PRE_POS (24U) -#define DSP2_GAMMA_C19_PRE_LEN (8U) -#define DSP2_GAMMA_C19_PRE_MSK (((1U << DSP2_GAMMA_C19_PRE_LEN) - 1) << DSP2_GAMMA_C19_PRE_POS) -#define DSP2_GAMMA_C19_PRE_UMSK (~(((1U << DSP2_GAMMA_C19_PRE_LEN) - 1) << DSP2_GAMMA_C19_PRE_POS)) - -/* 0x714 : GAMMA_CRUVE_6 */ -#define DSP2_GAMMA_GAMMA_CRUVE_6_OFFSET (0x714) -#define DSP2_GAMMA_C20_PRE DSP2_GAMMA_C20_PRE -#define DSP2_GAMMA_C20_PRE_POS (0U) -#define DSP2_GAMMA_C20_PRE_LEN (8U) -#define DSP2_GAMMA_C20_PRE_MSK (((1U << DSP2_GAMMA_C20_PRE_LEN) - 1) << DSP2_GAMMA_C20_PRE_POS) -#define DSP2_GAMMA_C20_PRE_UMSK (~(((1U << DSP2_GAMMA_C20_PRE_LEN) - 1) << DSP2_GAMMA_C20_PRE_POS)) -#define DSP2_GAMMA_C21_PRE DSP2_GAMMA_C21_PRE -#define DSP2_GAMMA_C21_PRE_POS (8U) -#define DSP2_GAMMA_C21_PRE_LEN (8U) -#define DSP2_GAMMA_C21_PRE_MSK (((1U << DSP2_GAMMA_C21_PRE_LEN) - 1) << DSP2_GAMMA_C21_PRE_POS) -#define DSP2_GAMMA_C21_PRE_UMSK (~(((1U << DSP2_GAMMA_C21_PRE_LEN) - 1) << DSP2_GAMMA_C21_PRE_POS)) -#define DSP2_GAMMA_C22_PRE DSP2_GAMMA_C22_PRE -#define DSP2_GAMMA_C22_PRE_POS (16U) -#define DSP2_GAMMA_C22_PRE_LEN (8U) -#define DSP2_GAMMA_C22_PRE_MSK (((1U << DSP2_GAMMA_C22_PRE_LEN) - 1) << DSP2_GAMMA_C22_PRE_POS) -#define DSP2_GAMMA_C22_PRE_UMSK (~(((1U << DSP2_GAMMA_C22_PRE_LEN) - 1) << DSP2_GAMMA_C22_PRE_POS)) -#define DSP2_GAMMA_C23_PRE DSP2_GAMMA_C23_PRE -#define DSP2_GAMMA_C23_PRE_POS (24U) -#define DSP2_GAMMA_C23_PRE_LEN (8U) -#define DSP2_GAMMA_C23_PRE_MSK (((1U << DSP2_GAMMA_C23_PRE_LEN) - 1) << DSP2_GAMMA_C23_PRE_POS) -#define DSP2_GAMMA_C23_PRE_UMSK (~(((1U << DSP2_GAMMA_C23_PRE_LEN) - 1) << DSP2_GAMMA_C23_PRE_POS)) - -/* 0x718 : GAMMA_CRUVE_7 */ -#define DSP2_GAMMA_GAMMA_CRUVE_7_OFFSET (0x718) -#define DSP2_GAMMA_C24_PRE DSP2_GAMMA_C24_PRE -#define DSP2_GAMMA_C24_PRE_POS (0U) -#define DSP2_GAMMA_C24_PRE_LEN (8U) -#define DSP2_GAMMA_C24_PRE_MSK (((1U << DSP2_GAMMA_C24_PRE_LEN) - 1) << DSP2_GAMMA_C24_PRE_POS) -#define DSP2_GAMMA_C24_PRE_UMSK (~(((1U << DSP2_GAMMA_C24_PRE_LEN) - 1) << DSP2_GAMMA_C24_PRE_POS)) -#define DSP2_GAMMA_C25_PRE DSP2_GAMMA_C25_PRE -#define DSP2_GAMMA_C25_PRE_POS (8U) -#define DSP2_GAMMA_C25_PRE_LEN (8U) -#define DSP2_GAMMA_C25_PRE_MSK (((1U << DSP2_GAMMA_C25_PRE_LEN) - 1) << DSP2_GAMMA_C25_PRE_POS) -#define DSP2_GAMMA_C25_PRE_UMSK (~(((1U << DSP2_GAMMA_C25_PRE_LEN) - 1) << DSP2_GAMMA_C25_PRE_POS)) -#define DSP2_GAMMA_C26_PRE DSP2_GAMMA_C26_PRE -#define DSP2_GAMMA_C26_PRE_POS (16U) -#define DSP2_GAMMA_C26_PRE_LEN (8U) -#define DSP2_GAMMA_C26_PRE_MSK (((1U << DSP2_GAMMA_C26_PRE_LEN) - 1) << DSP2_GAMMA_C26_PRE_POS) -#define DSP2_GAMMA_C26_PRE_UMSK (~(((1U << DSP2_GAMMA_C26_PRE_LEN) - 1) << DSP2_GAMMA_C26_PRE_POS)) -#define DSP2_GAMMA_C27_PRE DSP2_GAMMA_C27_PRE -#define DSP2_GAMMA_C27_PRE_POS (24U) -#define DSP2_GAMMA_C27_PRE_LEN (8U) -#define DSP2_GAMMA_C27_PRE_MSK (((1U << DSP2_GAMMA_C27_PRE_LEN) - 1) << DSP2_GAMMA_C27_PRE_POS) -#define DSP2_GAMMA_C27_PRE_UMSK (~(((1U << DSP2_GAMMA_C27_PRE_LEN) - 1) << DSP2_GAMMA_C27_PRE_POS)) - -/* 0x71C : GAMMA_CRUVE_8 */ -#define DSP2_GAMMA_GAMMA_CRUVE_8_OFFSET (0x71C) -#define DSP2_GAMMA_C28_PRE DSP2_GAMMA_C28_PRE -#define DSP2_GAMMA_C28_PRE_POS (0U) -#define DSP2_GAMMA_C28_PRE_LEN (8U) -#define DSP2_GAMMA_C28_PRE_MSK (((1U << DSP2_GAMMA_C28_PRE_LEN) - 1) << DSP2_GAMMA_C28_PRE_POS) -#define DSP2_GAMMA_C28_PRE_UMSK (~(((1U << DSP2_GAMMA_C28_PRE_LEN) - 1) << DSP2_GAMMA_C28_PRE_POS)) -#define DSP2_GAMMA_C29_PRE DSP2_GAMMA_C29_PRE -#define DSP2_GAMMA_C29_PRE_POS (8U) -#define DSP2_GAMMA_C29_PRE_LEN (8U) -#define DSP2_GAMMA_C29_PRE_MSK (((1U << DSP2_GAMMA_C29_PRE_LEN) - 1) << DSP2_GAMMA_C29_PRE_POS) -#define DSP2_GAMMA_C29_PRE_UMSK (~(((1U << DSP2_GAMMA_C29_PRE_LEN) - 1) << DSP2_GAMMA_C29_PRE_POS)) -#define DSP2_GAMMA_C30_PRE DSP2_GAMMA_C30_PRE -#define DSP2_GAMMA_C30_PRE_POS (16U) -#define DSP2_GAMMA_C30_PRE_LEN (8U) -#define DSP2_GAMMA_C30_PRE_MSK (((1U << DSP2_GAMMA_C30_PRE_LEN) - 1) << DSP2_GAMMA_C30_PRE_POS) -#define DSP2_GAMMA_C30_PRE_UMSK (~(((1U << DSP2_GAMMA_C30_PRE_LEN) - 1) << DSP2_GAMMA_C30_PRE_POS)) -#define DSP2_GAMMA_C31_PRE DSP2_GAMMA_C31_PRE -#define DSP2_GAMMA_C31_PRE_POS (24U) -#define DSP2_GAMMA_C31_PRE_LEN (8U) -#define DSP2_GAMMA_C31_PRE_MSK (((1U << DSP2_GAMMA_C31_PRE_LEN) - 1) << DSP2_GAMMA_C31_PRE_POS) -#define DSP2_GAMMA_C31_PRE_UMSK (~(((1U << DSP2_GAMMA_C31_PRE_LEN) - 1) << DSP2_GAMMA_C31_PRE_POS)) - -/* 0x720 : GAMMA_CRUVE_9 */ -#define DSP2_GAMMA_GAMMA_CRUVE_9_OFFSET (0x720) -#define DSP2_GAMMA_C32_PRE DSP2_GAMMA_C32_PRE -#define DSP2_GAMMA_C32_PRE_POS (0U) -#define DSP2_GAMMA_C32_PRE_LEN (8U) -#define DSP2_GAMMA_C32_PRE_MSK (((1U << DSP2_GAMMA_C32_PRE_LEN) - 1) << DSP2_GAMMA_C32_PRE_POS) -#define DSP2_GAMMA_C32_PRE_UMSK (~(((1U << DSP2_GAMMA_C32_PRE_LEN) - 1) << DSP2_GAMMA_C32_PRE_POS)) -#define DSP2_GAMMA_C33_PRE DSP2_GAMMA_C33_PRE -#define DSP2_GAMMA_C33_PRE_POS (8U) -#define DSP2_GAMMA_C33_PRE_LEN (8U) -#define DSP2_GAMMA_C33_PRE_MSK (((1U << DSP2_GAMMA_C33_PRE_LEN) - 1) << DSP2_GAMMA_C33_PRE_POS) -#define DSP2_GAMMA_C33_PRE_UMSK (~(((1U << DSP2_GAMMA_C33_PRE_LEN) - 1) << DSP2_GAMMA_C33_PRE_POS)) -#define DSP2_GAMMA_C34_PRE DSP2_GAMMA_C34_PRE -#define DSP2_GAMMA_C34_PRE_POS (16U) -#define DSP2_GAMMA_C34_PRE_LEN (8U) -#define DSP2_GAMMA_C34_PRE_MSK (((1U << DSP2_GAMMA_C34_PRE_LEN) - 1) << DSP2_GAMMA_C34_PRE_POS) -#define DSP2_GAMMA_C34_PRE_UMSK (~(((1U << DSP2_GAMMA_C34_PRE_LEN) - 1) << DSP2_GAMMA_C34_PRE_POS)) -#define DSP2_GAMMA_C35_PRE DSP2_GAMMA_C35_PRE -#define DSP2_GAMMA_C35_PRE_POS (24U) -#define DSP2_GAMMA_C35_PRE_LEN (8U) -#define DSP2_GAMMA_C35_PRE_MSK (((1U << DSP2_GAMMA_C35_PRE_LEN) - 1) << DSP2_GAMMA_C35_PRE_POS) -#define DSP2_GAMMA_C35_PRE_UMSK (~(((1U << DSP2_GAMMA_C35_PRE_LEN) - 1) << DSP2_GAMMA_C35_PRE_POS)) - -/* 0x724 : GAMMA_CRUVE_10 */ -#define DSP2_GAMMA_GAMMA_CRUVE_10_OFFSET (0x724) -#define DSP2_GAMMA_C36_PRE DSP2_GAMMA_C36_PRE -#define DSP2_GAMMA_C36_PRE_POS (0U) -#define DSP2_GAMMA_C36_PRE_LEN (8U) -#define DSP2_GAMMA_C36_PRE_MSK (((1U << DSP2_GAMMA_C36_PRE_LEN) - 1) << DSP2_GAMMA_C36_PRE_POS) -#define DSP2_GAMMA_C36_PRE_UMSK (~(((1U << DSP2_GAMMA_C36_PRE_LEN) - 1) << DSP2_GAMMA_C36_PRE_POS)) -#define DSP2_GAMMA_C37_PRE DSP2_GAMMA_C37_PRE -#define DSP2_GAMMA_C37_PRE_POS (8U) -#define DSP2_GAMMA_C37_PRE_LEN (8U) -#define DSP2_GAMMA_C37_PRE_MSK (((1U << DSP2_GAMMA_C37_PRE_LEN) - 1) << DSP2_GAMMA_C37_PRE_POS) -#define DSP2_GAMMA_C37_PRE_UMSK (~(((1U << DSP2_GAMMA_C37_PRE_LEN) - 1) << DSP2_GAMMA_C37_PRE_POS)) -#define DSP2_GAMMA_C38_PRE DSP2_GAMMA_C38_PRE -#define DSP2_GAMMA_C38_PRE_POS (16U) -#define DSP2_GAMMA_C38_PRE_LEN (8U) -#define DSP2_GAMMA_C38_PRE_MSK (((1U << DSP2_GAMMA_C38_PRE_LEN) - 1) << DSP2_GAMMA_C38_PRE_POS) -#define DSP2_GAMMA_C38_PRE_UMSK (~(((1U << DSP2_GAMMA_C38_PRE_LEN) - 1) << DSP2_GAMMA_C38_PRE_POS)) -#define DSP2_GAMMA_C39_PRE DSP2_GAMMA_C39_PRE -#define DSP2_GAMMA_C39_PRE_POS (24U) -#define DSP2_GAMMA_C39_PRE_LEN (8U) -#define DSP2_GAMMA_C39_PRE_MSK (((1U << DSP2_GAMMA_C39_PRE_LEN) - 1) << DSP2_GAMMA_C39_PRE_POS) -#define DSP2_GAMMA_C39_PRE_UMSK (~(((1U << DSP2_GAMMA_C39_PRE_LEN) - 1) << DSP2_GAMMA_C39_PRE_POS)) - -/* 0x728 : GAMMA_CRUVE_11 */ -#define DSP2_GAMMA_GAMMA_CRUVE_11_OFFSET (0x728) -#define DSP2_GAMMA_C40_PRE DSP2_GAMMA_C40_PRE -#define DSP2_GAMMA_C40_PRE_POS (0U) -#define DSP2_GAMMA_C40_PRE_LEN (8U) -#define DSP2_GAMMA_C40_PRE_MSK (((1U << DSP2_GAMMA_C40_PRE_LEN) - 1) << DSP2_GAMMA_C40_PRE_POS) -#define DSP2_GAMMA_C40_PRE_UMSK (~(((1U << DSP2_GAMMA_C40_PRE_LEN) - 1) << DSP2_GAMMA_C40_PRE_POS)) -#define DSP2_GAMMA_C41_PRE DSP2_GAMMA_C41_PRE -#define DSP2_GAMMA_C41_PRE_POS (8U) -#define DSP2_GAMMA_C41_PRE_LEN (8U) -#define DSP2_GAMMA_C41_PRE_MSK (((1U << DSP2_GAMMA_C41_PRE_LEN) - 1) << DSP2_GAMMA_C41_PRE_POS) -#define DSP2_GAMMA_C41_PRE_UMSK (~(((1U << DSP2_GAMMA_C41_PRE_LEN) - 1) << DSP2_GAMMA_C41_PRE_POS)) -#define DSP2_GAMMA_C42_PRE DSP2_GAMMA_C42_PRE -#define DSP2_GAMMA_C42_PRE_POS (16U) -#define DSP2_GAMMA_C42_PRE_LEN (8U) -#define DSP2_GAMMA_C42_PRE_MSK (((1U << DSP2_GAMMA_C42_PRE_LEN) - 1) << DSP2_GAMMA_C42_PRE_POS) -#define DSP2_GAMMA_C42_PRE_UMSK (~(((1U << DSP2_GAMMA_C42_PRE_LEN) - 1) << DSP2_GAMMA_C42_PRE_POS)) -#define DSP2_GAMMA_C43_PRE DSP2_GAMMA_C43_PRE -#define DSP2_GAMMA_C43_PRE_POS (24U) -#define DSP2_GAMMA_C43_PRE_LEN (8U) -#define DSP2_GAMMA_C43_PRE_MSK (((1U << DSP2_GAMMA_C43_PRE_LEN) - 1) << DSP2_GAMMA_C43_PRE_POS) -#define DSP2_GAMMA_C43_PRE_UMSK (~(((1U << DSP2_GAMMA_C43_PRE_LEN) - 1) << DSP2_GAMMA_C43_PRE_POS)) - -/* 0x72C : GAMMA_CRUVE_12 */ -#define DSP2_GAMMA_GAMMA_CRUVE_12_OFFSET (0x72C) -#define DSP2_GAMMA_C44_PRE DSP2_GAMMA_C44_PRE -#define DSP2_GAMMA_C44_PRE_POS (0U) -#define DSP2_GAMMA_C44_PRE_LEN (8U) -#define DSP2_GAMMA_C44_PRE_MSK (((1U << DSP2_GAMMA_C44_PRE_LEN) - 1) << DSP2_GAMMA_C44_PRE_POS) -#define DSP2_GAMMA_C44_PRE_UMSK (~(((1U << DSP2_GAMMA_C44_PRE_LEN) - 1) << DSP2_GAMMA_C44_PRE_POS)) -#define DSP2_GAMMA_C45_PRE DSP2_GAMMA_C45_PRE -#define DSP2_GAMMA_C45_PRE_POS (8U) -#define DSP2_GAMMA_C45_PRE_LEN (8U) -#define DSP2_GAMMA_C45_PRE_MSK (((1U << DSP2_GAMMA_C45_PRE_LEN) - 1) << DSP2_GAMMA_C45_PRE_POS) -#define DSP2_GAMMA_C45_PRE_UMSK (~(((1U << DSP2_GAMMA_C45_PRE_LEN) - 1) << DSP2_GAMMA_C45_PRE_POS)) -#define DSP2_GAMMA_C46_PRE DSP2_GAMMA_C46_PRE -#define DSP2_GAMMA_C46_PRE_POS (16U) -#define DSP2_GAMMA_C46_PRE_LEN (8U) -#define DSP2_GAMMA_C46_PRE_MSK (((1U << DSP2_GAMMA_C46_PRE_LEN) - 1) << DSP2_GAMMA_C46_PRE_POS) -#define DSP2_GAMMA_C46_PRE_UMSK (~(((1U << DSP2_GAMMA_C46_PRE_LEN) - 1) << DSP2_GAMMA_C46_PRE_POS)) -#define DSP2_GAMMA_C47_PRE DSP2_GAMMA_C47_PRE -#define DSP2_GAMMA_C47_PRE_POS (24U) -#define DSP2_GAMMA_C47_PRE_LEN (8U) -#define DSP2_GAMMA_C47_PRE_MSK (((1U << DSP2_GAMMA_C47_PRE_LEN) - 1) << DSP2_GAMMA_C47_PRE_POS) -#define DSP2_GAMMA_C47_PRE_UMSK (~(((1U << DSP2_GAMMA_C47_PRE_LEN) - 1) << DSP2_GAMMA_C47_PRE_POS)) - -/* 0x730 : GAMMA_CRUVE_13 */ -#define DSP2_GAMMA_GAMMA_CRUVE_13_OFFSET (0x730) -#define DSP2_GAMMA_C48_PRE DSP2_GAMMA_C48_PRE -#define DSP2_GAMMA_C48_PRE_POS (0U) -#define DSP2_GAMMA_C48_PRE_LEN (8U) -#define DSP2_GAMMA_C48_PRE_MSK (((1U << DSP2_GAMMA_C48_PRE_LEN) - 1) << DSP2_GAMMA_C48_PRE_POS) -#define DSP2_GAMMA_C48_PRE_UMSK (~(((1U << DSP2_GAMMA_C48_PRE_LEN) - 1) << DSP2_GAMMA_C48_PRE_POS)) -#define DSP2_GAMMA_C49_PRE DSP2_GAMMA_C49_PRE -#define DSP2_GAMMA_C49_PRE_POS (8U) -#define DSP2_GAMMA_C49_PRE_LEN (8U) -#define DSP2_GAMMA_C49_PRE_MSK (((1U << DSP2_GAMMA_C49_PRE_LEN) - 1) << DSP2_GAMMA_C49_PRE_POS) -#define DSP2_GAMMA_C49_PRE_UMSK (~(((1U << DSP2_GAMMA_C49_PRE_LEN) - 1) << DSP2_GAMMA_C49_PRE_POS)) -#define DSP2_GAMMA_C50_PRE DSP2_GAMMA_C50_PRE -#define DSP2_GAMMA_C50_PRE_POS (16U) -#define DSP2_GAMMA_C50_PRE_LEN (8U) -#define DSP2_GAMMA_C50_PRE_MSK (((1U << DSP2_GAMMA_C50_PRE_LEN) - 1) << DSP2_GAMMA_C50_PRE_POS) -#define DSP2_GAMMA_C50_PRE_UMSK (~(((1U << DSP2_GAMMA_C50_PRE_LEN) - 1) << DSP2_GAMMA_C50_PRE_POS)) -#define DSP2_GAMMA_C51_PRE DSP2_GAMMA_C51_PRE -#define DSP2_GAMMA_C51_PRE_POS (24U) -#define DSP2_GAMMA_C51_PRE_LEN (8U) -#define DSP2_GAMMA_C51_PRE_MSK (((1U << DSP2_GAMMA_C51_PRE_LEN) - 1) << DSP2_GAMMA_C51_PRE_POS) -#define DSP2_GAMMA_C51_PRE_UMSK (~(((1U << DSP2_GAMMA_C51_PRE_LEN) - 1) << DSP2_GAMMA_C51_PRE_POS)) - -/* 0x734 : GAMMA_CRUVE_14 */ -#define DSP2_GAMMA_GAMMA_CRUVE_14_OFFSET (0x734) -#define DSP2_GAMMA_C52_PRE DSP2_GAMMA_C52_PRE -#define DSP2_GAMMA_C52_PRE_POS (0U) -#define DSP2_GAMMA_C52_PRE_LEN (8U) -#define DSP2_GAMMA_C52_PRE_MSK (((1U << DSP2_GAMMA_C52_PRE_LEN) - 1) << DSP2_GAMMA_C52_PRE_POS) -#define DSP2_GAMMA_C52_PRE_UMSK (~(((1U << DSP2_GAMMA_C52_PRE_LEN) - 1) << DSP2_GAMMA_C52_PRE_POS)) -#define DSP2_GAMMA_C53_PRE DSP2_GAMMA_C53_PRE -#define DSP2_GAMMA_C53_PRE_POS (8U) -#define DSP2_GAMMA_C53_PRE_LEN (8U) -#define DSP2_GAMMA_C53_PRE_MSK (((1U << DSP2_GAMMA_C53_PRE_LEN) - 1) << DSP2_GAMMA_C53_PRE_POS) -#define DSP2_GAMMA_C53_PRE_UMSK (~(((1U << DSP2_GAMMA_C53_PRE_LEN) - 1) << DSP2_GAMMA_C53_PRE_POS)) -#define DSP2_GAMMA_C54_PRE DSP2_GAMMA_C54_PRE -#define DSP2_GAMMA_C54_PRE_POS (16U) -#define DSP2_GAMMA_C54_PRE_LEN (8U) -#define DSP2_GAMMA_C54_PRE_MSK (((1U << DSP2_GAMMA_C54_PRE_LEN) - 1) << DSP2_GAMMA_C54_PRE_POS) -#define DSP2_GAMMA_C54_PRE_UMSK (~(((1U << DSP2_GAMMA_C54_PRE_LEN) - 1) << DSP2_GAMMA_C54_PRE_POS)) -#define DSP2_GAMMA_C55_PRE DSP2_GAMMA_C55_PRE -#define DSP2_GAMMA_C55_PRE_POS (24U) -#define DSP2_GAMMA_C55_PRE_LEN (8U) -#define DSP2_GAMMA_C55_PRE_MSK (((1U << DSP2_GAMMA_C55_PRE_LEN) - 1) << DSP2_GAMMA_C55_PRE_POS) -#define DSP2_GAMMA_C55_PRE_UMSK (~(((1U << DSP2_GAMMA_C55_PRE_LEN) - 1) << DSP2_GAMMA_C55_PRE_POS)) - -/* 0x738 : GAMMA_CRUVE_15 */ -#define DSP2_GAMMA_GAMMA_CRUVE_15_OFFSET (0x738) -#define DSP2_GAMMA_C56_PRE DSP2_GAMMA_C56_PRE -#define DSP2_GAMMA_C56_PRE_POS (0U) -#define DSP2_GAMMA_C56_PRE_LEN (8U) -#define DSP2_GAMMA_C56_PRE_MSK (((1U << DSP2_GAMMA_C56_PRE_LEN) - 1) << DSP2_GAMMA_C56_PRE_POS) -#define DSP2_GAMMA_C56_PRE_UMSK (~(((1U << DSP2_GAMMA_C56_PRE_LEN) - 1) << DSP2_GAMMA_C56_PRE_POS)) -#define DSP2_GAMMA_C57_PRE DSP2_GAMMA_C57_PRE -#define DSP2_GAMMA_C57_PRE_POS (8U) -#define DSP2_GAMMA_C57_PRE_LEN (8U) -#define DSP2_GAMMA_C57_PRE_MSK (((1U << DSP2_GAMMA_C57_PRE_LEN) - 1) << DSP2_GAMMA_C57_PRE_POS) -#define DSP2_GAMMA_C57_PRE_UMSK (~(((1U << DSP2_GAMMA_C57_PRE_LEN) - 1) << DSP2_GAMMA_C57_PRE_POS)) -#define DSP2_GAMMA_C58_PRE DSP2_GAMMA_C58_PRE -#define DSP2_GAMMA_C58_PRE_POS (16U) -#define DSP2_GAMMA_C58_PRE_LEN (8U) -#define DSP2_GAMMA_C58_PRE_MSK (((1U << DSP2_GAMMA_C58_PRE_LEN) - 1) << DSP2_GAMMA_C58_PRE_POS) -#define DSP2_GAMMA_C58_PRE_UMSK (~(((1U << DSP2_GAMMA_C58_PRE_LEN) - 1) << DSP2_GAMMA_C58_PRE_POS)) -#define DSP2_GAMMA_C59_PRE DSP2_GAMMA_C59_PRE -#define DSP2_GAMMA_C59_PRE_POS (24U) -#define DSP2_GAMMA_C59_PRE_LEN (8U) -#define DSP2_GAMMA_C59_PRE_MSK (((1U << DSP2_GAMMA_C59_PRE_LEN) - 1) << DSP2_GAMMA_C59_PRE_POS) -#define DSP2_GAMMA_C59_PRE_UMSK (~(((1U << DSP2_GAMMA_C59_PRE_LEN) - 1) << DSP2_GAMMA_C59_PRE_POS)) - -/* 0x73C : GAMMA_CRUVE_16 */ -#define DSP2_GAMMA_GAMMA_CRUVE_16_OFFSET (0x73C) -#define DSP2_GAMMA_C60_PRE DSP2_GAMMA_C60_PRE -#define DSP2_GAMMA_C60_PRE_POS (0U) -#define DSP2_GAMMA_C60_PRE_LEN (8U) -#define DSP2_GAMMA_C60_PRE_MSK (((1U << DSP2_GAMMA_C60_PRE_LEN) - 1) << DSP2_GAMMA_C60_PRE_POS) -#define DSP2_GAMMA_C60_PRE_UMSK (~(((1U << DSP2_GAMMA_C60_PRE_LEN) - 1) << DSP2_GAMMA_C60_PRE_POS)) -#define DSP2_GAMMA_C61_PRE DSP2_GAMMA_C61_PRE -#define DSP2_GAMMA_C61_PRE_POS (8U) -#define DSP2_GAMMA_C61_PRE_LEN (8U) -#define DSP2_GAMMA_C61_PRE_MSK (((1U << DSP2_GAMMA_C61_PRE_LEN) - 1) << DSP2_GAMMA_C61_PRE_POS) -#define DSP2_GAMMA_C61_PRE_UMSK (~(((1U << DSP2_GAMMA_C61_PRE_LEN) - 1) << DSP2_GAMMA_C61_PRE_POS)) -#define DSP2_GAMMA_C62_PRE DSP2_GAMMA_C62_PRE -#define DSP2_GAMMA_C62_PRE_POS (16U) -#define DSP2_GAMMA_C62_PRE_LEN (8U) -#define DSP2_GAMMA_C62_PRE_MSK (((1U << DSP2_GAMMA_C62_PRE_LEN) - 1) << DSP2_GAMMA_C62_PRE_POS) -#define DSP2_GAMMA_C62_PRE_UMSK (~(((1U << DSP2_GAMMA_C62_PRE_LEN) - 1) << DSP2_GAMMA_C62_PRE_POS)) -#define DSP2_GAMMA_C63_PRE DSP2_GAMMA_C63_PRE -#define DSP2_GAMMA_C63_PRE_POS (24U) -#define DSP2_GAMMA_C63_PRE_LEN (8U) -#define DSP2_GAMMA_C63_PRE_MSK (((1U << DSP2_GAMMA_C63_PRE_LEN) - 1) << DSP2_GAMMA_C63_PRE_POS) -#define DSP2_GAMMA_C63_PRE_UMSK (~(((1U << DSP2_GAMMA_C63_PRE_LEN) - 1) << DSP2_GAMMA_C63_PRE_POS)) - -/* 0x740 : GAMMA_CRUVE_17 */ -#define DSP2_GAMMA_GAMMA_CRUVE_17_OFFSET (0x740) -#define DSP2_GAMMA_C64_PRE DSP2_GAMMA_C64_PRE -#define DSP2_GAMMA_C64_PRE_POS (0U) -#define DSP2_GAMMA_C64_PRE_LEN (8U) -#define DSP2_GAMMA_C64_PRE_MSK (((1U << DSP2_GAMMA_C64_PRE_LEN) - 1) << DSP2_GAMMA_C64_PRE_POS) -#define DSP2_GAMMA_C64_PRE_UMSK (~(((1U << DSP2_GAMMA_C64_PRE_LEN) - 1) << DSP2_GAMMA_C64_PRE_POS)) -#define DSP2_GAMMA_C65_PRE DSP2_GAMMA_C65_PRE -#define DSP2_GAMMA_C65_PRE_POS (8U) -#define DSP2_GAMMA_C65_PRE_LEN (8U) -#define DSP2_GAMMA_C65_PRE_MSK (((1U << DSP2_GAMMA_C65_PRE_LEN) - 1) << DSP2_GAMMA_C65_PRE_POS) -#define DSP2_GAMMA_C65_PRE_UMSK (~(((1U << DSP2_GAMMA_C65_PRE_LEN) - 1) << DSP2_GAMMA_C65_PRE_POS)) -#define DSP2_GAMMA_C66_PRE DSP2_GAMMA_C66_PRE -#define DSP2_GAMMA_C66_PRE_POS (16U) -#define DSP2_GAMMA_C66_PRE_LEN (8U) -#define DSP2_GAMMA_C66_PRE_MSK (((1U << DSP2_GAMMA_C66_PRE_LEN) - 1) << DSP2_GAMMA_C66_PRE_POS) -#define DSP2_GAMMA_C66_PRE_UMSK (~(((1U << DSP2_GAMMA_C66_PRE_LEN) - 1) << DSP2_GAMMA_C66_PRE_POS)) -#define DSP2_GAMMA_C67_PRE DSP2_GAMMA_C67_PRE -#define DSP2_GAMMA_C67_PRE_POS (24U) -#define DSP2_GAMMA_C67_PRE_LEN (8U) -#define DSP2_GAMMA_C67_PRE_MSK (((1U << DSP2_GAMMA_C67_PRE_LEN) - 1) << DSP2_GAMMA_C67_PRE_POS) -#define DSP2_GAMMA_C67_PRE_UMSK (~(((1U << DSP2_GAMMA_C67_PRE_LEN) - 1) << DSP2_GAMMA_C67_PRE_POS)) - -/* 0x744 : GAMMA_CRUVE_18 */ -#define DSP2_GAMMA_GAMMA_CRUVE_18_OFFSET (0x744) -#define DSP2_GAMMA_C68_PRE DSP2_GAMMA_C68_PRE -#define DSP2_GAMMA_C68_PRE_POS (0U) -#define DSP2_GAMMA_C68_PRE_LEN (8U) -#define DSP2_GAMMA_C68_PRE_MSK (((1U << DSP2_GAMMA_C68_PRE_LEN) - 1) << DSP2_GAMMA_C68_PRE_POS) -#define DSP2_GAMMA_C68_PRE_UMSK (~(((1U << DSP2_GAMMA_C68_PRE_LEN) - 1) << DSP2_GAMMA_C68_PRE_POS)) -#define DSP2_GAMMA_C69_PRE DSP2_GAMMA_C69_PRE -#define DSP2_GAMMA_C69_PRE_POS (8U) -#define DSP2_GAMMA_C69_PRE_LEN (8U) -#define DSP2_GAMMA_C69_PRE_MSK (((1U << DSP2_GAMMA_C69_PRE_LEN) - 1) << DSP2_GAMMA_C69_PRE_POS) -#define DSP2_GAMMA_C69_PRE_UMSK (~(((1U << DSP2_GAMMA_C69_PRE_LEN) - 1) << DSP2_GAMMA_C69_PRE_POS)) -#define DSP2_GAMMA_C70_PRE DSP2_GAMMA_C70_PRE -#define DSP2_GAMMA_C70_PRE_POS (16U) -#define DSP2_GAMMA_C70_PRE_LEN (8U) -#define DSP2_GAMMA_C70_PRE_MSK (((1U << DSP2_GAMMA_C70_PRE_LEN) - 1) << DSP2_GAMMA_C70_PRE_POS) -#define DSP2_GAMMA_C70_PRE_UMSK (~(((1U << DSP2_GAMMA_C70_PRE_LEN) - 1) << DSP2_GAMMA_C70_PRE_POS)) -#define DSP2_GAMMA_C71_PRE DSP2_GAMMA_C71_PRE -#define DSP2_GAMMA_C71_PRE_POS (24U) -#define DSP2_GAMMA_C71_PRE_LEN (8U) -#define DSP2_GAMMA_C71_PRE_MSK (((1U << DSP2_GAMMA_C71_PRE_LEN) - 1) << DSP2_GAMMA_C71_PRE_POS) -#define DSP2_GAMMA_C71_PRE_UMSK (~(((1U << DSP2_GAMMA_C71_PRE_LEN) - 1) << DSP2_GAMMA_C71_PRE_POS)) - -/* 0x748 : GAMMA_CRUVE_19 */ -#define DSP2_GAMMA_GAMMA_CRUVE_19_OFFSET (0x748) -#define DSP2_GAMMA_C72_PRE DSP2_GAMMA_C72_PRE -#define DSP2_GAMMA_C72_PRE_POS (0U) -#define DSP2_GAMMA_C72_PRE_LEN (8U) -#define DSP2_GAMMA_C72_PRE_MSK (((1U << DSP2_GAMMA_C72_PRE_LEN) - 1) << DSP2_GAMMA_C72_PRE_POS) -#define DSP2_GAMMA_C72_PRE_UMSK (~(((1U << DSP2_GAMMA_C72_PRE_LEN) - 1) << DSP2_GAMMA_C72_PRE_POS)) -#define DSP2_GAMMA_C73_PRE DSP2_GAMMA_C73_PRE -#define DSP2_GAMMA_C73_PRE_POS (8U) -#define DSP2_GAMMA_C73_PRE_LEN (8U) -#define DSP2_GAMMA_C73_PRE_MSK (((1U << DSP2_GAMMA_C73_PRE_LEN) - 1) << DSP2_GAMMA_C73_PRE_POS) -#define DSP2_GAMMA_C73_PRE_UMSK (~(((1U << DSP2_GAMMA_C73_PRE_LEN) - 1) << DSP2_GAMMA_C73_PRE_POS)) -#define DSP2_GAMMA_C74_PRE DSP2_GAMMA_C74_PRE -#define DSP2_GAMMA_C74_PRE_POS (16U) -#define DSP2_GAMMA_C74_PRE_LEN (8U) -#define DSP2_GAMMA_C74_PRE_MSK (((1U << DSP2_GAMMA_C74_PRE_LEN) - 1) << DSP2_GAMMA_C74_PRE_POS) -#define DSP2_GAMMA_C74_PRE_UMSK (~(((1U << DSP2_GAMMA_C74_PRE_LEN) - 1) << DSP2_GAMMA_C74_PRE_POS)) -#define DSP2_GAMMA_C75_PRE DSP2_GAMMA_C75_PRE -#define DSP2_GAMMA_C75_PRE_POS (24U) -#define DSP2_GAMMA_C75_PRE_LEN (8U) -#define DSP2_GAMMA_C75_PRE_MSK (((1U << DSP2_GAMMA_C75_PRE_LEN) - 1) << DSP2_GAMMA_C75_PRE_POS) -#define DSP2_GAMMA_C75_PRE_UMSK (~(((1U << DSP2_GAMMA_C75_PRE_LEN) - 1) << DSP2_GAMMA_C75_PRE_POS)) - -/* 0x74C : GAMMA_CRUVE_20 */ -#define DSP2_GAMMA_GAMMA_CRUVE_20_OFFSET (0x74C) -#define DSP2_GAMMA_C76_PRE DSP2_GAMMA_C76_PRE -#define DSP2_GAMMA_C76_PRE_POS (0U) -#define DSP2_GAMMA_C76_PRE_LEN (8U) -#define DSP2_GAMMA_C76_PRE_MSK (((1U << DSP2_GAMMA_C76_PRE_LEN) - 1) << DSP2_GAMMA_C76_PRE_POS) -#define DSP2_GAMMA_C76_PRE_UMSK (~(((1U << DSP2_GAMMA_C76_PRE_LEN) - 1) << DSP2_GAMMA_C76_PRE_POS)) -#define DSP2_GAMMA_C77_PRE DSP2_GAMMA_C77_PRE -#define DSP2_GAMMA_C77_PRE_POS (8U) -#define DSP2_GAMMA_C77_PRE_LEN (8U) -#define DSP2_GAMMA_C77_PRE_MSK (((1U << DSP2_GAMMA_C77_PRE_LEN) - 1) << DSP2_GAMMA_C77_PRE_POS) -#define DSP2_GAMMA_C77_PRE_UMSK (~(((1U << DSP2_GAMMA_C77_PRE_LEN) - 1) << DSP2_GAMMA_C77_PRE_POS)) -#define DSP2_GAMMA_C78_PRE DSP2_GAMMA_C78_PRE -#define DSP2_GAMMA_C78_PRE_POS (16U) -#define DSP2_GAMMA_C78_PRE_LEN (8U) -#define DSP2_GAMMA_C78_PRE_MSK (((1U << DSP2_GAMMA_C78_PRE_LEN) - 1) << DSP2_GAMMA_C78_PRE_POS) -#define DSP2_GAMMA_C78_PRE_UMSK (~(((1U << DSP2_GAMMA_C78_PRE_LEN) - 1) << DSP2_GAMMA_C78_PRE_POS)) -#define DSP2_GAMMA_C79_PRE DSP2_GAMMA_C79_PRE -#define DSP2_GAMMA_C79_PRE_POS (24U) -#define DSP2_GAMMA_C79_PRE_LEN (8U) -#define DSP2_GAMMA_C79_PRE_MSK (((1U << DSP2_GAMMA_C79_PRE_LEN) - 1) << DSP2_GAMMA_C79_PRE_POS) -#define DSP2_GAMMA_C79_PRE_UMSK (~(((1U << DSP2_GAMMA_C79_PRE_LEN) - 1) << DSP2_GAMMA_C79_PRE_POS)) - -/* 0x750 : GAMMA_CRUVE_21 */ -#define DSP2_GAMMA_GAMMA_CRUVE_21_OFFSET (0x750) -#define DSP2_GAMMA_C80_PRE DSP2_GAMMA_C80_PRE -#define DSP2_GAMMA_C80_PRE_POS (0U) -#define DSP2_GAMMA_C80_PRE_LEN (8U) -#define DSP2_GAMMA_C80_PRE_MSK (((1U << DSP2_GAMMA_C80_PRE_LEN) - 1) << DSP2_GAMMA_C80_PRE_POS) -#define DSP2_GAMMA_C80_PRE_UMSK (~(((1U << DSP2_GAMMA_C80_PRE_LEN) - 1) << DSP2_GAMMA_C80_PRE_POS)) -#define DSP2_GAMMA_C81_PRE DSP2_GAMMA_C81_PRE -#define DSP2_GAMMA_C81_PRE_POS (8U) -#define DSP2_GAMMA_C81_PRE_LEN (8U) -#define DSP2_GAMMA_C81_PRE_MSK (((1U << DSP2_GAMMA_C81_PRE_LEN) - 1) << DSP2_GAMMA_C81_PRE_POS) -#define DSP2_GAMMA_C81_PRE_UMSK (~(((1U << DSP2_GAMMA_C81_PRE_LEN) - 1) << DSP2_GAMMA_C81_PRE_POS)) -#define DSP2_GAMMA_C82_PRE DSP2_GAMMA_C82_PRE -#define DSP2_GAMMA_C82_PRE_POS (16U) -#define DSP2_GAMMA_C82_PRE_LEN (8U) -#define DSP2_GAMMA_C82_PRE_MSK (((1U << DSP2_GAMMA_C82_PRE_LEN) - 1) << DSP2_GAMMA_C82_PRE_POS) -#define DSP2_GAMMA_C82_PRE_UMSK (~(((1U << DSP2_GAMMA_C82_PRE_LEN) - 1) << DSP2_GAMMA_C82_PRE_POS)) -#define DSP2_GAMMA_C83_PRE DSP2_GAMMA_C83_PRE -#define DSP2_GAMMA_C83_PRE_POS (24U) -#define DSP2_GAMMA_C83_PRE_LEN (8U) -#define DSP2_GAMMA_C83_PRE_MSK (((1U << DSP2_GAMMA_C83_PRE_LEN) - 1) << DSP2_GAMMA_C83_PRE_POS) -#define DSP2_GAMMA_C83_PRE_UMSK (~(((1U << DSP2_GAMMA_C83_PRE_LEN) - 1) << DSP2_GAMMA_C83_PRE_POS)) - -/* 0x754 : GAMMA_CRUVE_22 */ -#define DSP2_GAMMA_GAMMA_CRUVE_22_OFFSET (0x754) -#define DSP2_GAMMA_C84_PRE DSP2_GAMMA_C84_PRE -#define DSP2_GAMMA_C84_PRE_POS (0U) -#define DSP2_GAMMA_C84_PRE_LEN (8U) -#define DSP2_GAMMA_C84_PRE_MSK (((1U << DSP2_GAMMA_C84_PRE_LEN) - 1) << DSP2_GAMMA_C84_PRE_POS) -#define DSP2_GAMMA_C84_PRE_UMSK (~(((1U << DSP2_GAMMA_C84_PRE_LEN) - 1) << DSP2_GAMMA_C84_PRE_POS)) -#define DSP2_GAMMA_C85_PRE DSP2_GAMMA_C85_PRE -#define DSP2_GAMMA_C85_PRE_POS (8U) -#define DSP2_GAMMA_C85_PRE_LEN (8U) -#define DSP2_GAMMA_C85_PRE_MSK (((1U << DSP2_GAMMA_C85_PRE_LEN) - 1) << DSP2_GAMMA_C85_PRE_POS) -#define DSP2_GAMMA_C85_PRE_UMSK (~(((1U << DSP2_GAMMA_C85_PRE_LEN) - 1) << DSP2_GAMMA_C85_PRE_POS)) -#define DSP2_GAMMA_C86_PRE DSP2_GAMMA_C86_PRE -#define DSP2_GAMMA_C86_PRE_POS (16U) -#define DSP2_GAMMA_C86_PRE_LEN (8U) -#define DSP2_GAMMA_C86_PRE_MSK (((1U << DSP2_GAMMA_C86_PRE_LEN) - 1) << DSP2_GAMMA_C86_PRE_POS) -#define DSP2_GAMMA_C86_PRE_UMSK (~(((1U << DSP2_GAMMA_C86_PRE_LEN) - 1) << DSP2_GAMMA_C86_PRE_POS)) -#define DSP2_GAMMA_C87_PRE DSP2_GAMMA_C87_PRE -#define DSP2_GAMMA_C87_PRE_POS (24U) -#define DSP2_GAMMA_C87_PRE_LEN (8U) -#define DSP2_GAMMA_C87_PRE_MSK (((1U << DSP2_GAMMA_C87_PRE_LEN) - 1) << DSP2_GAMMA_C87_PRE_POS) -#define DSP2_GAMMA_C87_PRE_UMSK (~(((1U << DSP2_GAMMA_C87_PRE_LEN) - 1) << DSP2_GAMMA_C87_PRE_POS)) - -/* 0x758 : GAMMA_CRUVE_23 */ -#define DSP2_GAMMA_GAMMA_CRUVE_23_OFFSET (0x758) -#define DSP2_GAMMA_C88_PRE DSP2_GAMMA_C88_PRE -#define DSP2_GAMMA_C88_PRE_POS (0U) -#define DSP2_GAMMA_C88_PRE_LEN (8U) -#define DSP2_GAMMA_C88_PRE_MSK (((1U << DSP2_GAMMA_C88_PRE_LEN) - 1) << DSP2_GAMMA_C88_PRE_POS) -#define DSP2_GAMMA_C88_PRE_UMSK (~(((1U << DSP2_GAMMA_C88_PRE_LEN) - 1) << DSP2_GAMMA_C88_PRE_POS)) -#define DSP2_GAMMA_C89_PRE DSP2_GAMMA_C89_PRE -#define DSP2_GAMMA_C89_PRE_POS (8U) -#define DSP2_GAMMA_C89_PRE_LEN (8U) -#define DSP2_GAMMA_C89_PRE_MSK (((1U << DSP2_GAMMA_C89_PRE_LEN) - 1) << DSP2_GAMMA_C89_PRE_POS) -#define DSP2_GAMMA_C89_PRE_UMSK (~(((1U << DSP2_GAMMA_C89_PRE_LEN) - 1) << DSP2_GAMMA_C89_PRE_POS)) -#define DSP2_GAMMA_C90_PRE DSP2_GAMMA_C90_PRE -#define DSP2_GAMMA_C90_PRE_POS (16U) -#define DSP2_GAMMA_C90_PRE_LEN (8U) -#define DSP2_GAMMA_C90_PRE_MSK (((1U << DSP2_GAMMA_C90_PRE_LEN) - 1) << DSP2_GAMMA_C90_PRE_POS) -#define DSP2_GAMMA_C90_PRE_UMSK (~(((1U << DSP2_GAMMA_C90_PRE_LEN) - 1) << DSP2_GAMMA_C90_PRE_POS)) -#define DSP2_GAMMA_C91_PRE DSP2_GAMMA_C91_PRE -#define DSP2_GAMMA_C91_PRE_POS (24U) -#define DSP2_GAMMA_C91_PRE_LEN (8U) -#define DSP2_GAMMA_C91_PRE_MSK (((1U << DSP2_GAMMA_C91_PRE_LEN) - 1) << DSP2_GAMMA_C91_PRE_POS) -#define DSP2_GAMMA_C91_PRE_UMSK (~(((1U << DSP2_GAMMA_C91_PRE_LEN) - 1) << DSP2_GAMMA_C91_PRE_POS)) - -/* 0x75C : GAMMA_CRUVE_24 */ -#define DSP2_GAMMA_GAMMA_CRUVE_24_OFFSET (0x75C) -#define DSP2_GAMMA_C92_PRE DSP2_GAMMA_C92_PRE -#define DSP2_GAMMA_C92_PRE_POS (0U) -#define DSP2_GAMMA_C92_PRE_LEN (8U) -#define DSP2_GAMMA_C92_PRE_MSK (((1U << DSP2_GAMMA_C92_PRE_LEN) - 1) << DSP2_GAMMA_C92_PRE_POS) -#define DSP2_GAMMA_C92_PRE_UMSK (~(((1U << DSP2_GAMMA_C92_PRE_LEN) - 1) << DSP2_GAMMA_C92_PRE_POS)) -#define DSP2_GAMMA_C93_PRE DSP2_GAMMA_C93_PRE -#define DSP2_GAMMA_C93_PRE_POS (8U) -#define DSP2_GAMMA_C93_PRE_LEN (8U) -#define DSP2_GAMMA_C93_PRE_MSK (((1U << DSP2_GAMMA_C93_PRE_LEN) - 1) << DSP2_GAMMA_C93_PRE_POS) -#define DSP2_GAMMA_C93_PRE_UMSK (~(((1U << DSP2_GAMMA_C93_PRE_LEN) - 1) << DSP2_GAMMA_C93_PRE_POS)) -#define DSP2_GAMMA_C94_PRE DSP2_GAMMA_C94_PRE -#define DSP2_GAMMA_C94_PRE_POS (16U) -#define DSP2_GAMMA_C94_PRE_LEN (8U) -#define DSP2_GAMMA_C94_PRE_MSK (((1U << DSP2_GAMMA_C94_PRE_LEN) - 1) << DSP2_GAMMA_C94_PRE_POS) -#define DSP2_GAMMA_C94_PRE_UMSK (~(((1U << DSP2_GAMMA_C94_PRE_LEN) - 1) << DSP2_GAMMA_C94_PRE_POS)) -#define DSP2_GAMMA_C95_PRE DSP2_GAMMA_C95_PRE -#define DSP2_GAMMA_C95_PRE_POS (24U) -#define DSP2_GAMMA_C95_PRE_LEN (8U) -#define DSP2_GAMMA_C95_PRE_MSK (((1U << DSP2_GAMMA_C95_PRE_LEN) - 1) << DSP2_GAMMA_C95_PRE_POS) -#define DSP2_GAMMA_C95_PRE_UMSK (~(((1U << DSP2_GAMMA_C95_PRE_LEN) - 1) << DSP2_GAMMA_C95_PRE_POS)) - -/* 0x760 : GAMMA_CRUVE_25 */ -#define DSP2_GAMMA_GAMMA_CRUVE_25_OFFSET (0x760) -#define DSP2_GAMMA_C96_PRE DSP2_GAMMA_C96_PRE -#define DSP2_GAMMA_C96_PRE_POS (0U) -#define DSP2_GAMMA_C96_PRE_LEN (8U) -#define DSP2_GAMMA_C96_PRE_MSK (((1U << DSP2_GAMMA_C96_PRE_LEN) - 1) << DSP2_GAMMA_C96_PRE_POS) -#define DSP2_GAMMA_C96_PRE_UMSK (~(((1U << DSP2_GAMMA_C96_PRE_LEN) - 1) << DSP2_GAMMA_C96_PRE_POS)) -#define DSP2_GAMMA_C97_PRE DSP2_GAMMA_C97_PRE -#define DSP2_GAMMA_C97_PRE_POS (8U) -#define DSP2_GAMMA_C97_PRE_LEN (8U) -#define DSP2_GAMMA_C97_PRE_MSK (((1U << DSP2_GAMMA_C97_PRE_LEN) - 1) << DSP2_GAMMA_C97_PRE_POS) -#define DSP2_GAMMA_C97_PRE_UMSK (~(((1U << DSP2_GAMMA_C97_PRE_LEN) - 1) << DSP2_GAMMA_C97_PRE_POS)) -#define DSP2_GAMMA_C98_PRE DSP2_GAMMA_C98_PRE -#define DSP2_GAMMA_C98_PRE_POS (16U) -#define DSP2_GAMMA_C98_PRE_LEN (8U) -#define DSP2_GAMMA_C98_PRE_MSK (((1U << DSP2_GAMMA_C98_PRE_LEN) - 1) << DSP2_GAMMA_C98_PRE_POS) -#define DSP2_GAMMA_C98_PRE_UMSK (~(((1U << DSP2_GAMMA_C98_PRE_LEN) - 1) << DSP2_GAMMA_C98_PRE_POS)) -#define DSP2_GAMMA_C99_PRE DSP2_GAMMA_C99_PRE -#define DSP2_GAMMA_C99_PRE_POS (24U) -#define DSP2_GAMMA_C99_PRE_LEN (8U) -#define DSP2_GAMMA_C99_PRE_MSK (((1U << DSP2_GAMMA_C99_PRE_LEN) - 1) << DSP2_GAMMA_C99_PRE_POS) -#define DSP2_GAMMA_C99_PRE_UMSK (~(((1U << DSP2_GAMMA_C99_PRE_LEN) - 1) << DSP2_GAMMA_C99_PRE_POS)) - -/* 0x764 : GAMMA_CRUVE_26 */ -#define DSP2_GAMMA_GAMMA_CRUVE_26_OFFSET (0x764) -#define DSP2_GAMMA_C100_PRE DSP2_GAMMA_C100_PRE -#define DSP2_GAMMA_C100_PRE_POS (0U) -#define DSP2_GAMMA_C100_PRE_LEN (8U) -#define DSP2_GAMMA_C100_PRE_MSK (((1U << DSP2_GAMMA_C100_PRE_LEN) - 1) << DSP2_GAMMA_C100_PRE_POS) -#define DSP2_GAMMA_C100_PRE_UMSK (~(((1U << DSP2_GAMMA_C100_PRE_LEN) - 1) << DSP2_GAMMA_C100_PRE_POS)) -#define DSP2_GAMMA_C101_PRE DSP2_GAMMA_C101_PRE -#define DSP2_GAMMA_C101_PRE_POS (8U) -#define DSP2_GAMMA_C101_PRE_LEN (8U) -#define DSP2_GAMMA_C101_PRE_MSK (((1U << DSP2_GAMMA_C101_PRE_LEN) - 1) << DSP2_GAMMA_C101_PRE_POS) -#define DSP2_GAMMA_C101_PRE_UMSK (~(((1U << DSP2_GAMMA_C101_PRE_LEN) - 1) << DSP2_GAMMA_C101_PRE_POS)) -#define DSP2_GAMMA_C102_PRE DSP2_GAMMA_C102_PRE -#define DSP2_GAMMA_C102_PRE_POS (16U) -#define DSP2_GAMMA_C102_PRE_LEN (8U) -#define DSP2_GAMMA_C102_PRE_MSK (((1U << DSP2_GAMMA_C102_PRE_LEN) - 1) << DSP2_GAMMA_C102_PRE_POS) -#define DSP2_GAMMA_C102_PRE_UMSK (~(((1U << DSP2_GAMMA_C102_PRE_LEN) - 1) << DSP2_GAMMA_C102_PRE_POS)) -#define DSP2_GAMMA_C103_PRE DSP2_GAMMA_C103_PRE -#define DSP2_GAMMA_C103_PRE_POS (24U) -#define DSP2_GAMMA_C103_PRE_LEN (8U) -#define DSP2_GAMMA_C103_PRE_MSK (((1U << DSP2_GAMMA_C103_PRE_LEN) - 1) << DSP2_GAMMA_C103_PRE_POS) -#define DSP2_GAMMA_C103_PRE_UMSK (~(((1U << DSP2_GAMMA_C103_PRE_LEN) - 1) << DSP2_GAMMA_C103_PRE_POS)) - -/* 0x768 : GAMMA_CRUVE_27 */ -#define DSP2_GAMMA_GAMMA_CRUVE_27_OFFSET (0x768) -#define DSP2_GAMMA_C104_PRE DSP2_GAMMA_C104_PRE -#define DSP2_GAMMA_C104_PRE_POS (0U) -#define DSP2_GAMMA_C104_PRE_LEN (8U) -#define DSP2_GAMMA_C104_PRE_MSK (((1U << DSP2_GAMMA_C104_PRE_LEN) - 1) << DSP2_GAMMA_C104_PRE_POS) -#define DSP2_GAMMA_C104_PRE_UMSK (~(((1U << DSP2_GAMMA_C104_PRE_LEN) - 1) << DSP2_GAMMA_C104_PRE_POS)) -#define DSP2_GAMMA_C105_PRE DSP2_GAMMA_C105_PRE -#define DSP2_GAMMA_C105_PRE_POS (8U) -#define DSP2_GAMMA_C105_PRE_LEN (8U) -#define DSP2_GAMMA_C105_PRE_MSK (((1U << DSP2_GAMMA_C105_PRE_LEN) - 1) << DSP2_GAMMA_C105_PRE_POS) -#define DSP2_GAMMA_C105_PRE_UMSK (~(((1U << DSP2_GAMMA_C105_PRE_LEN) - 1) << DSP2_GAMMA_C105_PRE_POS)) -#define DSP2_GAMMA_C106_PRE DSP2_GAMMA_C106_PRE -#define DSP2_GAMMA_C106_PRE_POS (16U) -#define DSP2_GAMMA_C106_PRE_LEN (8U) -#define DSP2_GAMMA_C106_PRE_MSK (((1U << DSP2_GAMMA_C106_PRE_LEN) - 1) << DSP2_GAMMA_C106_PRE_POS) -#define DSP2_GAMMA_C106_PRE_UMSK (~(((1U << DSP2_GAMMA_C106_PRE_LEN) - 1) << DSP2_GAMMA_C106_PRE_POS)) -#define DSP2_GAMMA_C107_PRE DSP2_GAMMA_C107_PRE -#define DSP2_GAMMA_C107_PRE_POS (24U) -#define DSP2_GAMMA_C107_PRE_LEN (8U) -#define DSP2_GAMMA_C107_PRE_MSK (((1U << DSP2_GAMMA_C107_PRE_LEN) - 1) << DSP2_GAMMA_C107_PRE_POS) -#define DSP2_GAMMA_C107_PRE_UMSK (~(((1U << DSP2_GAMMA_C107_PRE_LEN) - 1) << DSP2_GAMMA_C107_PRE_POS)) - -/* 0x76C : GAMMA_CRUVE_28 */ -#define DSP2_GAMMA_GAMMA_CRUVE_28_OFFSET (0x76C) -#define DSP2_GAMMA_C108_PRE DSP2_GAMMA_C108_PRE -#define DSP2_GAMMA_C108_PRE_POS (0U) -#define DSP2_GAMMA_C108_PRE_LEN (8U) -#define DSP2_GAMMA_C108_PRE_MSK (((1U << DSP2_GAMMA_C108_PRE_LEN) - 1) << DSP2_GAMMA_C108_PRE_POS) -#define DSP2_GAMMA_C108_PRE_UMSK (~(((1U << DSP2_GAMMA_C108_PRE_LEN) - 1) << DSP2_GAMMA_C108_PRE_POS)) -#define DSP2_GAMMA_C109_PRE DSP2_GAMMA_C109_PRE -#define DSP2_GAMMA_C109_PRE_POS (8U) -#define DSP2_GAMMA_C109_PRE_LEN (8U) -#define DSP2_GAMMA_C109_PRE_MSK (((1U << DSP2_GAMMA_C109_PRE_LEN) - 1) << DSP2_GAMMA_C109_PRE_POS) -#define DSP2_GAMMA_C109_PRE_UMSK (~(((1U << DSP2_GAMMA_C109_PRE_LEN) - 1) << DSP2_GAMMA_C109_PRE_POS)) -#define DSP2_GAMMA_C110_PRE DSP2_GAMMA_C110_PRE -#define DSP2_GAMMA_C110_PRE_POS (16U) -#define DSP2_GAMMA_C110_PRE_LEN (8U) -#define DSP2_GAMMA_C110_PRE_MSK (((1U << DSP2_GAMMA_C110_PRE_LEN) - 1) << DSP2_GAMMA_C110_PRE_POS) -#define DSP2_GAMMA_C110_PRE_UMSK (~(((1U << DSP2_GAMMA_C110_PRE_LEN) - 1) << DSP2_GAMMA_C110_PRE_POS)) -#define DSP2_GAMMA_C111_PRE DSP2_GAMMA_C111_PRE -#define DSP2_GAMMA_C111_PRE_POS (24U) -#define DSP2_GAMMA_C111_PRE_LEN (8U) -#define DSP2_GAMMA_C111_PRE_MSK (((1U << DSP2_GAMMA_C111_PRE_LEN) - 1) << DSP2_GAMMA_C111_PRE_POS) -#define DSP2_GAMMA_C111_PRE_UMSK (~(((1U << DSP2_GAMMA_C111_PRE_LEN) - 1) << DSP2_GAMMA_C111_PRE_POS)) - -/* 0x770 : GAMMA_CRUVE_29 */ -#define DSP2_GAMMA_GAMMA_CRUVE_29_OFFSET (0x770) -#define DSP2_GAMMA_C112_PRE DSP2_GAMMA_C112_PRE -#define DSP2_GAMMA_C112_PRE_POS (0U) -#define DSP2_GAMMA_C112_PRE_LEN (8U) -#define DSP2_GAMMA_C112_PRE_MSK (((1U << DSP2_GAMMA_C112_PRE_LEN) - 1) << DSP2_GAMMA_C112_PRE_POS) -#define DSP2_GAMMA_C112_PRE_UMSK (~(((1U << DSP2_GAMMA_C112_PRE_LEN) - 1) << DSP2_GAMMA_C112_PRE_POS)) -#define DSP2_GAMMA_C113_PRE DSP2_GAMMA_C113_PRE -#define DSP2_GAMMA_C113_PRE_POS (8U) -#define DSP2_GAMMA_C113_PRE_LEN (8U) -#define DSP2_GAMMA_C113_PRE_MSK (((1U << DSP2_GAMMA_C113_PRE_LEN) - 1) << DSP2_GAMMA_C113_PRE_POS) -#define DSP2_GAMMA_C113_PRE_UMSK (~(((1U << DSP2_GAMMA_C113_PRE_LEN) - 1) << DSP2_GAMMA_C113_PRE_POS)) -#define DSP2_GAMMA_C114_PRE DSP2_GAMMA_C114_PRE -#define DSP2_GAMMA_C114_PRE_POS (16U) -#define DSP2_GAMMA_C114_PRE_LEN (8U) -#define DSP2_GAMMA_C114_PRE_MSK (((1U << DSP2_GAMMA_C114_PRE_LEN) - 1) << DSP2_GAMMA_C114_PRE_POS) -#define DSP2_GAMMA_C114_PRE_UMSK (~(((1U << DSP2_GAMMA_C114_PRE_LEN) - 1) << DSP2_GAMMA_C114_PRE_POS)) -#define DSP2_GAMMA_C115_PRE DSP2_GAMMA_C115_PRE -#define DSP2_GAMMA_C115_PRE_POS (24U) -#define DSP2_GAMMA_C115_PRE_LEN (8U) -#define DSP2_GAMMA_C115_PRE_MSK (((1U << DSP2_GAMMA_C115_PRE_LEN) - 1) << DSP2_GAMMA_C115_PRE_POS) -#define DSP2_GAMMA_C115_PRE_UMSK (~(((1U << DSP2_GAMMA_C115_PRE_LEN) - 1) << DSP2_GAMMA_C115_PRE_POS)) - -/* 0x774 : GAMMA_CRUVE_30 */ -#define DSP2_GAMMA_GAMMA_CRUVE_30_OFFSET (0x774) -#define DSP2_GAMMA_C116_PRE DSP2_GAMMA_C116_PRE -#define DSP2_GAMMA_C116_PRE_POS (0U) -#define DSP2_GAMMA_C116_PRE_LEN (8U) -#define DSP2_GAMMA_C116_PRE_MSK (((1U << DSP2_GAMMA_C116_PRE_LEN) - 1) << DSP2_GAMMA_C116_PRE_POS) -#define DSP2_GAMMA_C116_PRE_UMSK (~(((1U << DSP2_GAMMA_C116_PRE_LEN) - 1) << DSP2_GAMMA_C116_PRE_POS)) -#define DSP2_GAMMA_C117_PRE DSP2_GAMMA_C117_PRE -#define DSP2_GAMMA_C117_PRE_POS (8U) -#define DSP2_GAMMA_C117_PRE_LEN (8U) -#define DSP2_GAMMA_C117_PRE_MSK (((1U << DSP2_GAMMA_C117_PRE_LEN) - 1) << DSP2_GAMMA_C117_PRE_POS) -#define DSP2_GAMMA_C117_PRE_UMSK (~(((1U << DSP2_GAMMA_C117_PRE_LEN) - 1) << DSP2_GAMMA_C117_PRE_POS)) -#define DSP2_GAMMA_C118_PRE DSP2_GAMMA_C118_PRE -#define DSP2_GAMMA_C118_PRE_POS (16U) -#define DSP2_GAMMA_C118_PRE_LEN (8U) -#define DSP2_GAMMA_C118_PRE_MSK (((1U << DSP2_GAMMA_C118_PRE_LEN) - 1) << DSP2_GAMMA_C118_PRE_POS) -#define DSP2_GAMMA_C118_PRE_UMSK (~(((1U << DSP2_GAMMA_C118_PRE_LEN) - 1) << DSP2_GAMMA_C118_PRE_POS)) -#define DSP2_GAMMA_C119_PRE DSP2_GAMMA_C119_PRE -#define DSP2_GAMMA_C119_PRE_POS (24U) -#define DSP2_GAMMA_C119_PRE_LEN (8U) -#define DSP2_GAMMA_C119_PRE_MSK (((1U << DSP2_GAMMA_C119_PRE_LEN) - 1) << DSP2_GAMMA_C119_PRE_POS) -#define DSP2_GAMMA_C119_PRE_UMSK (~(((1U << DSP2_GAMMA_C119_PRE_LEN) - 1) << DSP2_GAMMA_C119_PRE_POS)) - -/* 0x778 : GAMMA_CRUVE_31 */ -#define DSP2_GAMMA_GAMMA_CRUVE_31_OFFSET (0x778) -#define DSP2_GAMMA_C120_PRE DSP2_GAMMA_C120_PRE -#define DSP2_GAMMA_C120_PRE_POS (0U) -#define DSP2_GAMMA_C120_PRE_LEN (8U) -#define DSP2_GAMMA_C120_PRE_MSK (((1U << DSP2_GAMMA_C120_PRE_LEN) - 1) << DSP2_GAMMA_C120_PRE_POS) -#define DSP2_GAMMA_C120_PRE_UMSK (~(((1U << DSP2_GAMMA_C120_PRE_LEN) - 1) << DSP2_GAMMA_C120_PRE_POS)) -#define DSP2_GAMMA_C121_PRE DSP2_GAMMA_C121_PRE -#define DSP2_GAMMA_C121_PRE_POS (8U) -#define DSP2_GAMMA_C121_PRE_LEN (8U) -#define DSP2_GAMMA_C121_PRE_MSK (((1U << DSP2_GAMMA_C121_PRE_LEN) - 1) << DSP2_GAMMA_C121_PRE_POS) -#define DSP2_GAMMA_C121_PRE_UMSK (~(((1U << DSP2_GAMMA_C121_PRE_LEN) - 1) << DSP2_GAMMA_C121_PRE_POS)) -#define DSP2_GAMMA_C122_PRE DSP2_GAMMA_C122_PRE -#define DSP2_GAMMA_C122_PRE_POS (16U) -#define DSP2_GAMMA_C122_PRE_LEN (8U) -#define DSP2_GAMMA_C122_PRE_MSK (((1U << DSP2_GAMMA_C122_PRE_LEN) - 1) << DSP2_GAMMA_C122_PRE_POS) -#define DSP2_GAMMA_C122_PRE_UMSK (~(((1U << DSP2_GAMMA_C122_PRE_LEN) - 1) << DSP2_GAMMA_C122_PRE_POS)) -#define DSP2_GAMMA_C123_PRE DSP2_GAMMA_C123_PRE -#define DSP2_GAMMA_C123_PRE_POS (24U) -#define DSP2_GAMMA_C123_PRE_LEN (8U) -#define DSP2_GAMMA_C123_PRE_MSK (((1U << DSP2_GAMMA_C123_PRE_LEN) - 1) << DSP2_GAMMA_C123_PRE_POS) -#define DSP2_GAMMA_C123_PRE_UMSK (~(((1U << DSP2_GAMMA_C123_PRE_LEN) - 1) << DSP2_GAMMA_C123_PRE_POS)) - -/* 0x77C : GAMMA_CRUVE_32 */ -#define DSP2_GAMMA_GAMMA_CRUVE_32_OFFSET (0x77C) -#define DSP2_GAMMA_C124_PRE DSP2_GAMMA_C124_PRE -#define DSP2_GAMMA_C124_PRE_POS (0U) -#define DSP2_GAMMA_C124_PRE_LEN (8U) -#define DSP2_GAMMA_C124_PRE_MSK (((1U << DSP2_GAMMA_C124_PRE_LEN) - 1) << DSP2_GAMMA_C124_PRE_POS) -#define DSP2_GAMMA_C124_PRE_UMSK (~(((1U << DSP2_GAMMA_C124_PRE_LEN) - 1) << DSP2_GAMMA_C124_PRE_POS)) -#define DSP2_GAMMA_C125_PRE DSP2_GAMMA_C125_PRE -#define DSP2_GAMMA_C125_PRE_POS (8U) -#define DSP2_GAMMA_C125_PRE_LEN (8U) -#define DSP2_GAMMA_C125_PRE_MSK (((1U << DSP2_GAMMA_C125_PRE_LEN) - 1) << DSP2_GAMMA_C125_PRE_POS) -#define DSP2_GAMMA_C125_PRE_UMSK (~(((1U << DSP2_GAMMA_C125_PRE_LEN) - 1) << DSP2_GAMMA_C125_PRE_POS)) -#define DSP2_GAMMA_C126_PRE DSP2_GAMMA_C126_PRE -#define DSP2_GAMMA_C126_PRE_POS (16U) -#define DSP2_GAMMA_C126_PRE_LEN (8U) -#define DSP2_GAMMA_C126_PRE_MSK (((1U << DSP2_GAMMA_C126_PRE_LEN) - 1) << DSP2_GAMMA_C126_PRE_POS) -#define DSP2_GAMMA_C126_PRE_UMSK (~(((1U << DSP2_GAMMA_C126_PRE_LEN) - 1) << DSP2_GAMMA_C126_PRE_POS)) -#define DSP2_GAMMA_C127_PRE DSP2_GAMMA_C127_PRE -#define DSP2_GAMMA_C127_PRE_POS (24U) -#define DSP2_GAMMA_C127_PRE_LEN (8U) -#define DSP2_GAMMA_C127_PRE_MSK (((1U << DSP2_GAMMA_C127_PRE_LEN) - 1) << DSP2_GAMMA_C127_PRE_POS) -#define DSP2_GAMMA_C127_PRE_UMSK (~(((1U << DSP2_GAMMA_C127_PRE_LEN) - 1) << DSP2_GAMMA_C127_PRE_POS)) - -/* 0x780 : GAMMA_CRUVE_33 */ -#define DSP2_GAMMA_GAMMA_CRUVE_33_OFFSET (0x780) -#define DSP2_GAMMA_C128_PRE DSP2_GAMMA_C128_PRE -#define DSP2_GAMMA_C128_PRE_POS (0U) -#define DSP2_GAMMA_C128_PRE_LEN (8U) -#define DSP2_GAMMA_C128_PRE_MSK (((1U << DSP2_GAMMA_C128_PRE_LEN) - 1) << DSP2_GAMMA_C128_PRE_POS) -#define DSP2_GAMMA_C128_PRE_UMSK (~(((1U << DSP2_GAMMA_C128_PRE_LEN) - 1) << DSP2_GAMMA_C128_PRE_POS)) -#define DSP2_GAMMA_C129_PRE DSP2_GAMMA_C129_PRE -#define DSP2_GAMMA_C129_PRE_POS (8U) -#define DSP2_GAMMA_C129_PRE_LEN (8U) -#define DSP2_GAMMA_C129_PRE_MSK (((1U << DSP2_GAMMA_C129_PRE_LEN) - 1) << DSP2_GAMMA_C129_PRE_POS) -#define DSP2_GAMMA_C129_PRE_UMSK (~(((1U << DSP2_GAMMA_C129_PRE_LEN) - 1) << DSP2_GAMMA_C129_PRE_POS)) -#define DSP2_GAMMA_C130_PRE DSP2_GAMMA_C130_PRE -#define DSP2_GAMMA_C130_PRE_POS (16U) -#define DSP2_GAMMA_C130_PRE_LEN (8U) -#define DSP2_GAMMA_C130_PRE_MSK (((1U << DSP2_GAMMA_C130_PRE_LEN) - 1) << DSP2_GAMMA_C130_PRE_POS) -#define DSP2_GAMMA_C130_PRE_UMSK (~(((1U << DSP2_GAMMA_C130_PRE_LEN) - 1) << DSP2_GAMMA_C130_PRE_POS)) -#define DSP2_GAMMA_C131_PRE DSP2_GAMMA_C131_PRE -#define DSP2_GAMMA_C131_PRE_POS (24U) -#define DSP2_GAMMA_C131_PRE_LEN (8U) -#define DSP2_GAMMA_C131_PRE_MSK (((1U << DSP2_GAMMA_C131_PRE_LEN) - 1) << DSP2_GAMMA_C131_PRE_POS) -#define DSP2_GAMMA_C131_PRE_UMSK (~(((1U << DSP2_GAMMA_C131_PRE_LEN) - 1) << DSP2_GAMMA_C131_PRE_POS)) - -/* 0x784 : GAMMA_CRUVE_34 */ -#define DSP2_GAMMA_GAMMA_CRUVE_34_OFFSET (0x784) -#define DSP2_GAMMA_C132_PRE DSP2_GAMMA_C132_PRE -#define DSP2_GAMMA_C132_PRE_POS (0U) -#define DSP2_GAMMA_C132_PRE_LEN (8U) -#define DSP2_GAMMA_C132_PRE_MSK (((1U << DSP2_GAMMA_C132_PRE_LEN) - 1) << DSP2_GAMMA_C132_PRE_POS) -#define DSP2_GAMMA_C132_PRE_UMSK (~(((1U << DSP2_GAMMA_C132_PRE_LEN) - 1) << DSP2_GAMMA_C132_PRE_POS)) -#define DSP2_GAMMA_C133_PRE DSP2_GAMMA_C133_PRE -#define DSP2_GAMMA_C133_PRE_POS (8U) -#define DSP2_GAMMA_C133_PRE_LEN (8U) -#define DSP2_GAMMA_C133_PRE_MSK (((1U << DSP2_GAMMA_C133_PRE_LEN) - 1) << DSP2_GAMMA_C133_PRE_POS) -#define DSP2_GAMMA_C133_PRE_UMSK (~(((1U << DSP2_GAMMA_C133_PRE_LEN) - 1) << DSP2_GAMMA_C133_PRE_POS)) -#define DSP2_GAMMA_C134_PRE DSP2_GAMMA_C134_PRE -#define DSP2_GAMMA_C134_PRE_POS (16U) -#define DSP2_GAMMA_C134_PRE_LEN (8U) -#define DSP2_GAMMA_C134_PRE_MSK (((1U << DSP2_GAMMA_C134_PRE_LEN) - 1) << DSP2_GAMMA_C134_PRE_POS) -#define DSP2_GAMMA_C134_PRE_UMSK (~(((1U << DSP2_GAMMA_C134_PRE_LEN) - 1) << DSP2_GAMMA_C134_PRE_POS)) -#define DSP2_GAMMA_C135_PRE DSP2_GAMMA_C135_PRE -#define DSP2_GAMMA_C135_PRE_POS (24U) -#define DSP2_GAMMA_C135_PRE_LEN (8U) -#define DSP2_GAMMA_C135_PRE_MSK (((1U << DSP2_GAMMA_C135_PRE_LEN) - 1) << DSP2_GAMMA_C135_PRE_POS) -#define DSP2_GAMMA_C135_PRE_UMSK (~(((1U << DSP2_GAMMA_C135_PRE_LEN) - 1) << DSP2_GAMMA_C135_PRE_POS)) - -/* 0x788 : GAMMA_CRUVE_35 */ -#define DSP2_GAMMA_GAMMA_CRUVE_35_OFFSET (0x788) -#define DSP2_GAMMA_C136_PRE DSP2_GAMMA_C136_PRE -#define DSP2_GAMMA_C136_PRE_POS (0U) -#define DSP2_GAMMA_C136_PRE_LEN (8U) -#define DSP2_GAMMA_C136_PRE_MSK (((1U << DSP2_GAMMA_C136_PRE_LEN) - 1) << DSP2_GAMMA_C136_PRE_POS) -#define DSP2_GAMMA_C136_PRE_UMSK (~(((1U << DSP2_GAMMA_C136_PRE_LEN) - 1) << DSP2_GAMMA_C136_PRE_POS)) -#define DSP2_GAMMA_C137_PRE DSP2_GAMMA_C137_PRE -#define DSP2_GAMMA_C137_PRE_POS (8U) -#define DSP2_GAMMA_C137_PRE_LEN (8U) -#define DSP2_GAMMA_C137_PRE_MSK (((1U << DSP2_GAMMA_C137_PRE_LEN) - 1) << DSP2_GAMMA_C137_PRE_POS) -#define DSP2_GAMMA_C137_PRE_UMSK (~(((1U << DSP2_GAMMA_C137_PRE_LEN) - 1) << DSP2_GAMMA_C137_PRE_POS)) -#define DSP2_GAMMA_C138_PRE DSP2_GAMMA_C138_PRE -#define DSP2_GAMMA_C138_PRE_POS (16U) -#define DSP2_GAMMA_C138_PRE_LEN (8U) -#define DSP2_GAMMA_C138_PRE_MSK (((1U << DSP2_GAMMA_C138_PRE_LEN) - 1) << DSP2_GAMMA_C138_PRE_POS) -#define DSP2_GAMMA_C138_PRE_UMSK (~(((1U << DSP2_GAMMA_C138_PRE_LEN) - 1) << DSP2_GAMMA_C138_PRE_POS)) -#define DSP2_GAMMA_C139_PRE DSP2_GAMMA_C139_PRE -#define DSP2_GAMMA_C139_PRE_POS (24U) -#define DSP2_GAMMA_C139_PRE_LEN (8U) -#define DSP2_GAMMA_C139_PRE_MSK (((1U << DSP2_GAMMA_C139_PRE_LEN) - 1) << DSP2_GAMMA_C139_PRE_POS) -#define DSP2_GAMMA_C139_PRE_UMSK (~(((1U << DSP2_GAMMA_C139_PRE_LEN) - 1) << DSP2_GAMMA_C139_PRE_POS)) - -/* 0x78C : GAMMA_CRUVE_36 */ -#define DSP2_GAMMA_GAMMA_CRUVE_36_OFFSET (0x78C) -#define DSP2_GAMMA_C140_PRE DSP2_GAMMA_C140_PRE -#define DSP2_GAMMA_C140_PRE_POS (0U) -#define DSP2_GAMMA_C140_PRE_LEN (8U) -#define DSP2_GAMMA_C140_PRE_MSK (((1U << DSP2_GAMMA_C140_PRE_LEN) - 1) << DSP2_GAMMA_C140_PRE_POS) -#define DSP2_GAMMA_C140_PRE_UMSK (~(((1U << DSP2_GAMMA_C140_PRE_LEN) - 1) << DSP2_GAMMA_C140_PRE_POS)) -#define DSP2_GAMMA_C141_PRE DSP2_GAMMA_C141_PRE -#define DSP2_GAMMA_C141_PRE_POS (8U) -#define DSP2_GAMMA_C141_PRE_LEN (8U) -#define DSP2_GAMMA_C141_PRE_MSK (((1U << DSP2_GAMMA_C141_PRE_LEN) - 1) << DSP2_GAMMA_C141_PRE_POS) -#define DSP2_GAMMA_C141_PRE_UMSK (~(((1U << DSP2_GAMMA_C141_PRE_LEN) - 1) << DSP2_GAMMA_C141_PRE_POS)) -#define DSP2_GAMMA_C142_PRE DSP2_GAMMA_C142_PRE -#define DSP2_GAMMA_C142_PRE_POS (16U) -#define DSP2_GAMMA_C142_PRE_LEN (8U) -#define DSP2_GAMMA_C142_PRE_MSK (((1U << DSP2_GAMMA_C142_PRE_LEN) - 1) << DSP2_GAMMA_C142_PRE_POS) -#define DSP2_GAMMA_C142_PRE_UMSK (~(((1U << DSP2_GAMMA_C142_PRE_LEN) - 1) << DSP2_GAMMA_C142_PRE_POS)) -#define DSP2_GAMMA_C143_PRE DSP2_GAMMA_C143_PRE -#define DSP2_GAMMA_C143_PRE_POS (24U) -#define DSP2_GAMMA_C143_PRE_LEN (8U) -#define DSP2_GAMMA_C143_PRE_MSK (((1U << DSP2_GAMMA_C143_PRE_LEN) - 1) << DSP2_GAMMA_C143_PRE_POS) -#define DSP2_GAMMA_C143_PRE_UMSK (~(((1U << DSP2_GAMMA_C143_PRE_LEN) - 1) << DSP2_GAMMA_C143_PRE_POS)) - -/* 0x790 : GAMMA_CRUVE_37 */ -#define DSP2_GAMMA_GAMMA_CRUVE_37_OFFSET (0x790) -#define DSP2_GAMMA_C144_PRE DSP2_GAMMA_C144_PRE -#define DSP2_GAMMA_C144_PRE_POS (0U) -#define DSP2_GAMMA_C144_PRE_LEN (8U) -#define DSP2_GAMMA_C144_PRE_MSK (((1U << DSP2_GAMMA_C144_PRE_LEN) - 1) << DSP2_GAMMA_C144_PRE_POS) -#define DSP2_GAMMA_C144_PRE_UMSK (~(((1U << DSP2_GAMMA_C144_PRE_LEN) - 1) << DSP2_GAMMA_C144_PRE_POS)) -#define DSP2_GAMMA_C145_PRE DSP2_GAMMA_C145_PRE -#define DSP2_GAMMA_C145_PRE_POS (8U) -#define DSP2_GAMMA_C145_PRE_LEN (8U) -#define DSP2_GAMMA_C145_PRE_MSK (((1U << DSP2_GAMMA_C145_PRE_LEN) - 1) << DSP2_GAMMA_C145_PRE_POS) -#define DSP2_GAMMA_C145_PRE_UMSK (~(((1U << DSP2_GAMMA_C145_PRE_LEN) - 1) << DSP2_GAMMA_C145_PRE_POS)) -#define DSP2_GAMMA_C146_PRE DSP2_GAMMA_C146_PRE -#define DSP2_GAMMA_C146_PRE_POS (16U) -#define DSP2_GAMMA_C146_PRE_LEN (8U) -#define DSP2_GAMMA_C146_PRE_MSK (((1U << DSP2_GAMMA_C146_PRE_LEN) - 1) << DSP2_GAMMA_C146_PRE_POS) -#define DSP2_GAMMA_C146_PRE_UMSK (~(((1U << DSP2_GAMMA_C146_PRE_LEN) - 1) << DSP2_GAMMA_C146_PRE_POS)) -#define DSP2_GAMMA_C147_PRE DSP2_GAMMA_C147_PRE -#define DSP2_GAMMA_C147_PRE_POS (24U) -#define DSP2_GAMMA_C147_PRE_LEN (8U) -#define DSP2_GAMMA_C147_PRE_MSK (((1U << DSP2_GAMMA_C147_PRE_LEN) - 1) << DSP2_GAMMA_C147_PRE_POS) -#define DSP2_GAMMA_C147_PRE_UMSK (~(((1U << DSP2_GAMMA_C147_PRE_LEN) - 1) << DSP2_GAMMA_C147_PRE_POS)) - -/* 0x794 : GAMMA_CRUVE_38 */ -#define DSP2_GAMMA_GAMMA_CRUVE_38_OFFSET (0x794) -#define DSP2_GAMMA_C148_PRE DSP2_GAMMA_C148_PRE -#define DSP2_GAMMA_C148_PRE_POS (0U) -#define DSP2_GAMMA_C148_PRE_LEN (8U) -#define DSP2_GAMMA_C148_PRE_MSK (((1U << DSP2_GAMMA_C148_PRE_LEN) - 1) << DSP2_GAMMA_C148_PRE_POS) -#define DSP2_GAMMA_C148_PRE_UMSK (~(((1U << DSP2_GAMMA_C148_PRE_LEN) - 1) << DSP2_GAMMA_C148_PRE_POS)) -#define DSP2_GAMMA_C149_PRE DSP2_GAMMA_C149_PRE -#define DSP2_GAMMA_C149_PRE_POS (8U) -#define DSP2_GAMMA_C149_PRE_LEN (8U) -#define DSP2_GAMMA_C149_PRE_MSK (((1U << DSP2_GAMMA_C149_PRE_LEN) - 1) << DSP2_GAMMA_C149_PRE_POS) -#define DSP2_GAMMA_C149_PRE_UMSK (~(((1U << DSP2_GAMMA_C149_PRE_LEN) - 1) << DSP2_GAMMA_C149_PRE_POS)) -#define DSP2_GAMMA_C150_PRE DSP2_GAMMA_C150_PRE -#define DSP2_GAMMA_C150_PRE_POS (16U) -#define DSP2_GAMMA_C150_PRE_LEN (8U) -#define DSP2_GAMMA_C150_PRE_MSK (((1U << DSP2_GAMMA_C150_PRE_LEN) - 1) << DSP2_GAMMA_C150_PRE_POS) -#define DSP2_GAMMA_C150_PRE_UMSK (~(((1U << DSP2_GAMMA_C150_PRE_LEN) - 1) << DSP2_GAMMA_C150_PRE_POS)) -#define DSP2_GAMMA_C151_PRE DSP2_GAMMA_C151_PRE -#define DSP2_GAMMA_C151_PRE_POS (24U) -#define DSP2_GAMMA_C151_PRE_LEN (8U) -#define DSP2_GAMMA_C151_PRE_MSK (((1U << DSP2_GAMMA_C151_PRE_LEN) - 1) << DSP2_GAMMA_C151_PRE_POS) -#define DSP2_GAMMA_C151_PRE_UMSK (~(((1U << DSP2_GAMMA_C151_PRE_LEN) - 1) << DSP2_GAMMA_C151_PRE_POS)) - -/* 0x798 : GAMMA_CRUVE_39 */ -#define DSP2_GAMMA_GAMMA_CRUVE_39_OFFSET (0x798) -#define DSP2_GAMMA_C152_PRE DSP2_GAMMA_C152_PRE -#define DSP2_GAMMA_C152_PRE_POS (0U) -#define DSP2_GAMMA_C152_PRE_LEN (8U) -#define DSP2_GAMMA_C152_PRE_MSK (((1U << DSP2_GAMMA_C152_PRE_LEN) - 1) << DSP2_GAMMA_C152_PRE_POS) -#define DSP2_GAMMA_C152_PRE_UMSK (~(((1U << DSP2_GAMMA_C152_PRE_LEN) - 1) << DSP2_GAMMA_C152_PRE_POS)) -#define DSP2_GAMMA_C153_PRE DSP2_GAMMA_C153_PRE -#define DSP2_GAMMA_C153_PRE_POS (8U) -#define DSP2_GAMMA_C153_PRE_LEN (8U) -#define DSP2_GAMMA_C153_PRE_MSK (((1U << DSP2_GAMMA_C153_PRE_LEN) - 1) << DSP2_GAMMA_C153_PRE_POS) -#define DSP2_GAMMA_C153_PRE_UMSK (~(((1U << DSP2_GAMMA_C153_PRE_LEN) - 1) << DSP2_GAMMA_C153_PRE_POS)) -#define DSP2_GAMMA_C154_PRE DSP2_GAMMA_C154_PRE -#define DSP2_GAMMA_C154_PRE_POS (16U) -#define DSP2_GAMMA_C154_PRE_LEN (8U) -#define DSP2_GAMMA_C154_PRE_MSK (((1U << DSP2_GAMMA_C154_PRE_LEN) - 1) << DSP2_GAMMA_C154_PRE_POS) -#define DSP2_GAMMA_C154_PRE_UMSK (~(((1U << DSP2_GAMMA_C154_PRE_LEN) - 1) << DSP2_GAMMA_C154_PRE_POS)) -#define DSP2_GAMMA_C155_PRE DSP2_GAMMA_C155_PRE -#define DSP2_GAMMA_C155_PRE_POS (24U) -#define DSP2_GAMMA_C155_PRE_LEN (8U) -#define DSP2_GAMMA_C155_PRE_MSK (((1U << DSP2_GAMMA_C155_PRE_LEN) - 1) << DSP2_GAMMA_C155_PRE_POS) -#define DSP2_GAMMA_C155_PRE_UMSK (~(((1U << DSP2_GAMMA_C155_PRE_LEN) - 1) << DSP2_GAMMA_C155_PRE_POS)) - -/* 0x79C : GAMMA_CRUVE_40 */ -#define DSP2_GAMMA_GAMMA_CRUVE_40_OFFSET (0x79C) -#define DSP2_GAMMA_C156_PRE DSP2_GAMMA_C156_PRE -#define DSP2_GAMMA_C156_PRE_POS (0U) -#define DSP2_GAMMA_C156_PRE_LEN (8U) -#define DSP2_GAMMA_C156_PRE_MSK (((1U << DSP2_GAMMA_C156_PRE_LEN) - 1) << DSP2_GAMMA_C156_PRE_POS) -#define DSP2_GAMMA_C156_PRE_UMSK (~(((1U << DSP2_GAMMA_C156_PRE_LEN) - 1) << DSP2_GAMMA_C156_PRE_POS)) -#define DSP2_GAMMA_C157_PRE DSP2_GAMMA_C157_PRE -#define DSP2_GAMMA_C157_PRE_POS (8U) -#define DSP2_GAMMA_C157_PRE_LEN (8U) -#define DSP2_GAMMA_C157_PRE_MSK (((1U << DSP2_GAMMA_C157_PRE_LEN) - 1) << DSP2_GAMMA_C157_PRE_POS) -#define DSP2_GAMMA_C157_PRE_UMSK (~(((1U << DSP2_GAMMA_C157_PRE_LEN) - 1) << DSP2_GAMMA_C157_PRE_POS)) -#define DSP2_GAMMA_C158_PRE DSP2_GAMMA_C158_PRE -#define DSP2_GAMMA_C158_PRE_POS (16U) -#define DSP2_GAMMA_C158_PRE_LEN (8U) -#define DSP2_GAMMA_C158_PRE_MSK (((1U << DSP2_GAMMA_C158_PRE_LEN) - 1) << DSP2_GAMMA_C158_PRE_POS) -#define DSP2_GAMMA_C158_PRE_UMSK (~(((1U << DSP2_GAMMA_C158_PRE_LEN) - 1) << DSP2_GAMMA_C158_PRE_POS)) -#define DSP2_GAMMA_C159_PRE DSP2_GAMMA_C159_PRE -#define DSP2_GAMMA_C159_PRE_POS (24U) -#define DSP2_GAMMA_C159_PRE_LEN (8U) -#define DSP2_GAMMA_C159_PRE_MSK (((1U << DSP2_GAMMA_C159_PRE_LEN) - 1) << DSP2_GAMMA_C159_PRE_POS) -#define DSP2_GAMMA_C159_PRE_UMSK (~(((1U << DSP2_GAMMA_C159_PRE_LEN) - 1) << DSP2_GAMMA_C159_PRE_POS)) - -/* 0x7A0 : GAMMA_CRUVE_41 */ -#define DSP2_GAMMA_GAMMA_CRUVE_41_OFFSET (0x7A0) -#define DSP2_GAMMA_C160_PRE DSP2_GAMMA_C160_PRE -#define DSP2_GAMMA_C160_PRE_POS (0U) -#define DSP2_GAMMA_C160_PRE_LEN (8U) -#define DSP2_GAMMA_C160_PRE_MSK (((1U << DSP2_GAMMA_C160_PRE_LEN) - 1) << DSP2_GAMMA_C160_PRE_POS) -#define DSP2_GAMMA_C160_PRE_UMSK (~(((1U << DSP2_GAMMA_C160_PRE_LEN) - 1) << DSP2_GAMMA_C160_PRE_POS)) -#define DSP2_GAMMA_C161_PRE DSP2_GAMMA_C161_PRE -#define DSP2_GAMMA_C161_PRE_POS (8U) -#define DSP2_GAMMA_C161_PRE_LEN (8U) -#define DSP2_GAMMA_C161_PRE_MSK (((1U << DSP2_GAMMA_C161_PRE_LEN) - 1) << DSP2_GAMMA_C161_PRE_POS) -#define DSP2_GAMMA_C161_PRE_UMSK (~(((1U << DSP2_GAMMA_C161_PRE_LEN) - 1) << DSP2_GAMMA_C161_PRE_POS)) -#define DSP2_GAMMA_C162_PRE DSP2_GAMMA_C162_PRE -#define DSP2_GAMMA_C162_PRE_POS (16U) -#define DSP2_GAMMA_C162_PRE_LEN (8U) -#define DSP2_GAMMA_C162_PRE_MSK (((1U << DSP2_GAMMA_C162_PRE_LEN) - 1) << DSP2_GAMMA_C162_PRE_POS) -#define DSP2_GAMMA_C162_PRE_UMSK (~(((1U << DSP2_GAMMA_C162_PRE_LEN) - 1) << DSP2_GAMMA_C162_PRE_POS)) -#define DSP2_GAMMA_C163_PRE DSP2_GAMMA_C163_PRE -#define DSP2_GAMMA_C163_PRE_POS (24U) -#define DSP2_GAMMA_C163_PRE_LEN (8U) -#define DSP2_GAMMA_C163_PRE_MSK (((1U << DSP2_GAMMA_C163_PRE_LEN) - 1) << DSP2_GAMMA_C163_PRE_POS) -#define DSP2_GAMMA_C163_PRE_UMSK (~(((1U << DSP2_GAMMA_C163_PRE_LEN) - 1) << DSP2_GAMMA_C163_PRE_POS)) - -/* 0x7A4 : GAMMA_CRUVE_42 */ -#define DSP2_GAMMA_GAMMA_CRUVE_42_OFFSET (0x7A4) -#define DSP2_GAMMA_C164_PRE DSP2_GAMMA_C164_PRE -#define DSP2_GAMMA_C164_PRE_POS (0U) -#define DSP2_GAMMA_C164_PRE_LEN (8U) -#define DSP2_GAMMA_C164_PRE_MSK (((1U << DSP2_GAMMA_C164_PRE_LEN) - 1) << DSP2_GAMMA_C164_PRE_POS) -#define DSP2_GAMMA_C164_PRE_UMSK (~(((1U << DSP2_GAMMA_C164_PRE_LEN) - 1) << DSP2_GAMMA_C164_PRE_POS)) -#define DSP2_GAMMA_C165_PRE DSP2_GAMMA_C165_PRE -#define DSP2_GAMMA_C165_PRE_POS (8U) -#define DSP2_GAMMA_C165_PRE_LEN (8U) -#define DSP2_GAMMA_C165_PRE_MSK (((1U << DSP2_GAMMA_C165_PRE_LEN) - 1) << DSP2_GAMMA_C165_PRE_POS) -#define DSP2_GAMMA_C165_PRE_UMSK (~(((1U << DSP2_GAMMA_C165_PRE_LEN) - 1) << DSP2_GAMMA_C165_PRE_POS)) -#define DSP2_GAMMA_C166_PRE DSP2_GAMMA_C166_PRE -#define DSP2_GAMMA_C166_PRE_POS (16U) -#define DSP2_GAMMA_C166_PRE_LEN (8U) -#define DSP2_GAMMA_C166_PRE_MSK (((1U << DSP2_GAMMA_C166_PRE_LEN) - 1) << DSP2_GAMMA_C166_PRE_POS) -#define DSP2_GAMMA_C166_PRE_UMSK (~(((1U << DSP2_GAMMA_C166_PRE_LEN) - 1) << DSP2_GAMMA_C166_PRE_POS)) -#define DSP2_GAMMA_C167_PRE DSP2_GAMMA_C167_PRE -#define DSP2_GAMMA_C167_PRE_POS (24U) -#define DSP2_GAMMA_C167_PRE_LEN (8U) -#define DSP2_GAMMA_C167_PRE_MSK (((1U << DSP2_GAMMA_C167_PRE_LEN) - 1) << DSP2_GAMMA_C167_PRE_POS) -#define DSP2_GAMMA_C167_PRE_UMSK (~(((1U << DSP2_GAMMA_C167_PRE_LEN) - 1) << DSP2_GAMMA_C167_PRE_POS)) - -/* 0x7A8 : GAMMA_CRUVE_43 */ -#define DSP2_GAMMA_GAMMA_CRUVE_43_OFFSET (0x7A8) -#define DSP2_GAMMA_C168_PRE DSP2_GAMMA_C168_PRE -#define DSP2_GAMMA_C168_PRE_POS (0U) -#define DSP2_GAMMA_C168_PRE_LEN (8U) -#define DSP2_GAMMA_C168_PRE_MSK (((1U << DSP2_GAMMA_C168_PRE_LEN) - 1) << DSP2_GAMMA_C168_PRE_POS) -#define DSP2_GAMMA_C168_PRE_UMSK (~(((1U << DSP2_GAMMA_C168_PRE_LEN) - 1) << DSP2_GAMMA_C168_PRE_POS)) -#define DSP2_GAMMA_C169_PRE DSP2_GAMMA_C169_PRE -#define DSP2_GAMMA_C169_PRE_POS (8U) -#define DSP2_GAMMA_C169_PRE_LEN (8U) -#define DSP2_GAMMA_C169_PRE_MSK (((1U << DSP2_GAMMA_C169_PRE_LEN) - 1) << DSP2_GAMMA_C169_PRE_POS) -#define DSP2_GAMMA_C169_PRE_UMSK (~(((1U << DSP2_GAMMA_C169_PRE_LEN) - 1) << DSP2_GAMMA_C169_PRE_POS)) -#define DSP2_GAMMA_C170_PRE DSP2_GAMMA_C170_PRE -#define DSP2_GAMMA_C170_PRE_POS (16U) -#define DSP2_GAMMA_C170_PRE_LEN (8U) -#define DSP2_GAMMA_C170_PRE_MSK (((1U << DSP2_GAMMA_C170_PRE_LEN) - 1) << DSP2_GAMMA_C170_PRE_POS) -#define DSP2_GAMMA_C170_PRE_UMSK (~(((1U << DSP2_GAMMA_C170_PRE_LEN) - 1) << DSP2_GAMMA_C170_PRE_POS)) -#define DSP2_GAMMA_C171_PRE DSP2_GAMMA_C171_PRE -#define DSP2_GAMMA_C171_PRE_POS (24U) -#define DSP2_GAMMA_C171_PRE_LEN (8U) -#define DSP2_GAMMA_C171_PRE_MSK (((1U << DSP2_GAMMA_C171_PRE_LEN) - 1) << DSP2_GAMMA_C171_PRE_POS) -#define DSP2_GAMMA_C171_PRE_UMSK (~(((1U << DSP2_GAMMA_C171_PRE_LEN) - 1) << DSP2_GAMMA_C171_PRE_POS)) - -/* 0x7AC : GAMMA_CRUVE_44 */ -#define DSP2_GAMMA_GAMMA_CRUVE_44_OFFSET (0x7AC) -#define DSP2_GAMMA_C172_PRE DSP2_GAMMA_C172_PRE -#define DSP2_GAMMA_C172_PRE_POS (0U) -#define DSP2_GAMMA_C172_PRE_LEN (8U) -#define DSP2_GAMMA_C172_PRE_MSK (((1U << DSP2_GAMMA_C172_PRE_LEN) - 1) << DSP2_GAMMA_C172_PRE_POS) -#define DSP2_GAMMA_C172_PRE_UMSK (~(((1U << DSP2_GAMMA_C172_PRE_LEN) - 1) << DSP2_GAMMA_C172_PRE_POS)) -#define DSP2_GAMMA_C173_PRE DSP2_GAMMA_C173_PRE -#define DSP2_GAMMA_C173_PRE_POS (8U) -#define DSP2_GAMMA_C173_PRE_LEN (8U) -#define DSP2_GAMMA_C173_PRE_MSK (((1U << DSP2_GAMMA_C173_PRE_LEN) - 1) << DSP2_GAMMA_C173_PRE_POS) -#define DSP2_GAMMA_C173_PRE_UMSK (~(((1U << DSP2_GAMMA_C173_PRE_LEN) - 1) << DSP2_GAMMA_C173_PRE_POS)) -#define DSP2_GAMMA_C174_PRE DSP2_GAMMA_C174_PRE -#define DSP2_GAMMA_C174_PRE_POS (16U) -#define DSP2_GAMMA_C174_PRE_LEN (8U) -#define DSP2_GAMMA_C174_PRE_MSK (((1U << DSP2_GAMMA_C174_PRE_LEN) - 1) << DSP2_GAMMA_C174_PRE_POS) -#define DSP2_GAMMA_C174_PRE_UMSK (~(((1U << DSP2_GAMMA_C174_PRE_LEN) - 1) << DSP2_GAMMA_C174_PRE_POS)) -#define DSP2_GAMMA_C175_PRE DSP2_GAMMA_C175_PRE -#define DSP2_GAMMA_C175_PRE_POS (24U) -#define DSP2_GAMMA_C175_PRE_LEN (8U) -#define DSP2_GAMMA_C175_PRE_MSK (((1U << DSP2_GAMMA_C175_PRE_LEN) - 1) << DSP2_GAMMA_C175_PRE_POS) -#define DSP2_GAMMA_C175_PRE_UMSK (~(((1U << DSP2_GAMMA_C175_PRE_LEN) - 1) << DSP2_GAMMA_C175_PRE_POS)) - -/* 0x7B0 : GAMMA_CRUVE_45 */ -#define DSP2_GAMMA_GAMMA_CRUVE_45_OFFSET (0x7B0) -#define DSP2_GAMMA_C176_PRE DSP2_GAMMA_C176_PRE -#define DSP2_GAMMA_C176_PRE_POS (0U) -#define DSP2_GAMMA_C176_PRE_LEN (8U) -#define DSP2_GAMMA_C176_PRE_MSK (((1U << DSP2_GAMMA_C176_PRE_LEN) - 1) << DSP2_GAMMA_C176_PRE_POS) -#define DSP2_GAMMA_C176_PRE_UMSK (~(((1U << DSP2_GAMMA_C176_PRE_LEN) - 1) << DSP2_GAMMA_C176_PRE_POS)) -#define DSP2_GAMMA_C177_PRE DSP2_GAMMA_C177_PRE -#define DSP2_GAMMA_C177_PRE_POS (8U) -#define DSP2_GAMMA_C177_PRE_LEN (8U) -#define DSP2_GAMMA_C177_PRE_MSK (((1U << DSP2_GAMMA_C177_PRE_LEN) - 1) << DSP2_GAMMA_C177_PRE_POS) -#define DSP2_GAMMA_C177_PRE_UMSK (~(((1U << DSP2_GAMMA_C177_PRE_LEN) - 1) << DSP2_GAMMA_C177_PRE_POS)) -#define DSP2_GAMMA_C178_PRE DSP2_GAMMA_C178_PRE -#define DSP2_GAMMA_C178_PRE_POS (16U) -#define DSP2_GAMMA_C178_PRE_LEN (8U) -#define DSP2_GAMMA_C178_PRE_MSK (((1U << DSP2_GAMMA_C178_PRE_LEN) - 1) << DSP2_GAMMA_C178_PRE_POS) -#define DSP2_GAMMA_C178_PRE_UMSK (~(((1U << DSP2_GAMMA_C178_PRE_LEN) - 1) << DSP2_GAMMA_C178_PRE_POS)) -#define DSP2_GAMMA_C179_PRE DSP2_GAMMA_C179_PRE -#define DSP2_GAMMA_C179_PRE_POS (24U) -#define DSP2_GAMMA_C179_PRE_LEN (8U) -#define DSP2_GAMMA_C179_PRE_MSK (((1U << DSP2_GAMMA_C179_PRE_LEN) - 1) << DSP2_GAMMA_C179_PRE_POS) -#define DSP2_GAMMA_C179_PRE_UMSK (~(((1U << DSP2_GAMMA_C179_PRE_LEN) - 1) << DSP2_GAMMA_C179_PRE_POS)) - -/* 0x7B4 : GAMMA_CRUVE_46 */ -#define DSP2_GAMMA_GAMMA_CRUVE_46_OFFSET (0x7B4) -#define DSP2_GAMMA_C180_PRE DSP2_GAMMA_C180_PRE -#define DSP2_GAMMA_C180_PRE_POS (0U) -#define DSP2_GAMMA_C180_PRE_LEN (8U) -#define DSP2_GAMMA_C180_PRE_MSK (((1U << DSP2_GAMMA_C180_PRE_LEN) - 1) << DSP2_GAMMA_C180_PRE_POS) -#define DSP2_GAMMA_C180_PRE_UMSK (~(((1U << DSP2_GAMMA_C180_PRE_LEN) - 1) << DSP2_GAMMA_C180_PRE_POS)) -#define DSP2_GAMMA_C181_PRE DSP2_GAMMA_C181_PRE -#define DSP2_GAMMA_C181_PRE_POS (8U) -#define DSP2_GAMMA_C181_PRE_LEN (8U) -#define DSP2_GAMMA_C181_PRE_MSK (((1U << DSP2_GAMMA_C181_PRE_LEN) - 1) << DSP2_GAMMA_C181_PRE_POS) -#define DSP2_GAMMA_C181_PRE_UMSK (~(((1U << DSP2_GAMMA_C181_PRE_LEN) - 1) << DSP2_GAMMA_C181_PRE_POS)) -#define DSP2_GAMMA_C182_PRE DSP2_GAMMA_C182_PRE -#define DSP2_GAMMA_C182_PRE_POS (16U) -#define DSP2_GAMMA_C182_PRE_LEN (8U) -#define DSP2_GAMMA_C182_PRE_MSK (((1U << DSP2_GAMMA_C182_PRE_LEN) - 1) << DSP2_GAMMA_C182_PRE_POS) -#define DSP2_GAMMA_C182_PRE_UMSK (~(((1U << DSP2_GAMMA_C182_PRE_LEN) - 1) << DSP2_GAMMA_C182_PRE_POS)) -#define DSP2_GAMMA_C183_PRE DSP2_GAMMA_C183_PRE -#define DSP2_GAMMA_C183_PRE_POS (24U) -#define DSP2_GAMMA_C183_PRE_LEN (8U) -#define DSP2_GAMMA_C183_PRE_MSK (((1U << DSP2_GAMMA_C183_PRE_LEN) - 1) << DSP2_GAMMA_C183_PRE_POS) -#define DSP2_GAMMA_C183_PRE_UMSK (~(((1U << DSP2_GAMMA_C183_PRE_LEN) - 1) << DSP2_GAMMA_C183_PRE_POS)) - -/* 0x7B8 : GAMMA_CRUVE_47 */ -#define DSP2_GAMMA_GAMMA_CRUVE_47_OFFSET (0x7B8) -#define DSP2_GAMMA_C184_PRE DSP2_GAMMA_C184_PRE -#define DSP2_GAMMA_C184_PRE_POS (0U) -#define DSP2_GAMMA_C184_PRE_LEN (8U) -#define DSP2_GAMMA_C184_PRE_MSK (((1U << DSP2_GAMMA_C184_PRE_LEN) - 1) << DSP2_GAMMA_C184_PRE_POS) -#define DSP2_GAMMA_C184_PRE_UMSK (~(((1U << DSP2_GAMMA_C184_PRE_LEN) - 1) << DSP2_GAMMA_C184_PRE_POS)) -#define DSP2_GAMMA_C185_PRE DSP2_GAMMA_C185_PRE -#define DSP2_GAMMA_C185_PRE_POS (8U) -#define DSP2_GAMMA_C185_PRE_LEN (8U) -#define DSP2_GAMMA_C185_PRE_MSK (((1U << DSP2_GAMMA_C185_PRE_LEN) - 1) << DSP2_GAMMA_C185_PRE_POS) -#define DSP2_GAMMA_C185_PRE_UMSK (~(((1U << DSP2_GAMMA_C185_PRE_LEN) - 1) << DSP2_GAMMA_C185_PRE_POS)) -#define DSP2_GAMMA_C186_PRE DSP2_GAMMA_C186_PRE -#define DSP2_GAMMA_C186_PRE_POS (16U) -#define DSP2_GAMMA_C186_PRE_LEN (8U) -#define DSP2_GAMMA_C186_PRE_MSK (((1U << DSP2_GAMMA_C186_PRE_LEN) - 1) << DSP2_GAMMA_C186_PRE_POS) -#define DSP2_GAMMA_C186_PRE_UMSK (~(((1U << DSP2_GAMMA_C186_PRE_LEN) - 1) << DSP2_GAMMA_C186_PRE_POS)) -#define DSP2_GAMMA_C187_PRE DSP2_GAMMA_C187_PRE -#define DSP2_GAMMA_C187_PRE_POS (24U) -#define DSP2_GAMMA_C187_PRE_LEN (8U) -#define DSP2_GAMMA_C187_PRE_MSK (((1U << DSP2_GAMMA_C187_PRE_LEN) - 1) << DSP2_GAMMA_C187_PRE_POS) -#define DSP2_GAMMA_C187_PRE_UMSK (~(((1U << DSP2_GAMMA_C187_PRE_LEN) - 1) << DSP2_GAMMA_C187_PRE_POS)) - -/* 0x7BC : GAMMA_CRUVE_48 */ -#define DSP2_GAMMA_GAMMA_CRUVE_48_OFFSET (0x7BC) -#define DSP2_GAMMA_C188_PRE DSP2_GAMMA_C188_PRE -#define DSP2_GAMMA_C188_PRE_POS (0U) -#define DSP2_GAMMA_C188_PRE_LEN (8U) -#define DSP2_GAMMA_C188_PRE_MSK (((1U << DSP2_GAMMA_C188_PRE_LEN) - 1) << DSP2_GAMMA_C188_PRE_POS) -#define DSP2_GAMMA_C188_PRE_UMSK (~(((1U << DSP2_GAMMA_C188_PRE_LEN) - 1) << DSP2_GAMMA_C188_PRE_POS)) -#define DSP2_GAMMA_C189_PRE DSP2_GAMMA_C189_PRE -#define DSP2_GAMMA_C189_PRE_POS (8U) -#define DSP2_GAMMA_C189_PRE_LEN (8U) -#define DSP2_GAMMA_C189_PRE_MSK (((1U << DSP2_GAMMA_C189_PRE_LEN) - 1) << DSP2_GAMMA_C189_PRE_POS) -#define DSP2_GAMMA_C189_PRE_UMSK (~(((1U << DSP2_GAMMA_C189_PRE_LEN) - 1) << DSP2_GAMMA_C189_PRE_POS)) -#define DSP2_GAMMA_C190_PRE DSP2_GAMMA_C190_PRE -#define DSP2_GAMMA_C190_PRE_POS (16U) -#define DSP2_GAMMA_C190_PRE_LEN (8U) -#define DSP2_GAMMA_C190_PRE_MSK (((1U << DSP2_GAMMA_C190_PRE_LEN) - 1) << DSP2_GAMMA_C190_PRE_POS) -#define DSP2_GAMMA_C190_PRE_UMSK (~(((1U << DSP2_GAMMA_C190_PRE_LEN) - 1) << DSP2_GAMMA_C190_PRE_POS)) -#define DSP2_GAMMA_C191_PRE DSP2_GAMMA_C191_PRE -#define DSP2_GAMMA_C191_PRE_POS (24U) -#define DSP2_GAMMA_C191_PRE_LEN (8U) -#define DSP2_GAMMA_C191_PRE_MSK (((1U << DSP2_GAMMA_C191_PRE_LEN) - 1) << DSP2_GAMMA_C191_PRE_POS) -#define DSP2_GAMMA_C191_PRE_UMSK (~(((1U << DSP2_GAMMA_C191_PRE_LEN) - 1) << DSP2_GAMMA_C191_PRE_POS)) - -/* 0x7C0 : GAMMA_CRUVE_49 */ -#define DSP2_GAMMA_GAMMA_CRUVE_49_OFFSET (0x7C0) -#define DSP2_GAMMA_C192_PRE DSP2_GAMMA_C192_PRE -#define DSP2_GAMMA_C192_PRE_POS (0U) -#define DSP2_GAMMA_C192_PRE_LEN (8U) -#define DSP2_GAMMA_C192_PRE_MSK (((1U << DSP2_GAMMA_C192_PRE_LEN) - 1) << DSP2_GAMMA_C192_PRE_POS) -#define DSP2_GAMMA_C192_PRE_UMSK (~(((1U << DSP2_GAMMA_C192_PRE_LEN) - 1) << DSP2_GAMMA_C192_PRE_POS)) -#define DSP2_GAMMA_C193_PRE DSP2_GAMMA_C193_PRE -#define DSP2_GAMMA_C193_PRE_POS (8U) -#define DSP2_GAMMA_C193_PRE_LEN (8U) -#define DSP2_GAMMA_C193_PRE_MSK (((1U << DSP2_GAMMA_C193_PRE_LEN) - 1) << DSP2_GAMMA_C193_PRE_POS) -#define DSP2_GAMMA_C193_PRE_UMSK (~(((1U << DSP2_GAMMA_C193_PRE_LEN) - 1) << DSP2_GAMMA_C193_PRE_POS)) -#define DSP2_GAMMA_C194_PRE DSP2_GAMMA_C194_PRE -#define DSP2_GAMMA_C194_PRE_POS (16U) -#define DSP2_GAMMA_C194_PRE_LEN (8U) -#define DSP2_GAMMA_C194_PRE_MSK (((1U << DSP2_GAMMA_C194_PRE_LEN) - 1) << DSP2_GAMMA_C194_PRE_POS) -#define DSP2_GAMMA_C194_PRE_UMSK (~(((1U << DSP2_GAMMA_C194_PRE_LEN) - 1) << DSP2_GAMMA_C194_PRE_POS)) -#define DSP2_GAMMA_C195_PRE DSP2_GAMMA_C195_PRE -#define DSP2_GAMMA_C195_PRE_POS (24U) -#define DSP2_GAMMA_C195_PRE_LEN (8U) -#define DSP2_GAMMA_C195_PRE_MSK (((1U << DSP2_GAMMA_C195_PRE_LEN) - 1) << DSP2_GAMMA_C195_PRE_POS) -#define DSP2_GAMMA_C195_PRE_UMSK (~(((1U << DSP2_GAMMA_C195_PRE_LEN) - 1) << DSP2_GAMMA_C195_PRE_POS)) - -/* 0x7C4 : GAMMA_CRUVE_50 */ -#define DSP2_GAMMA_GAMMA_CRUVE_50_OFFSET (0x7C4) -#define DSP2_GAMMA_C196_PRE DSP2_GAMMA_C196_PRE -#define DSP2_GAMMA_C196_PRE_POS (0U) -#define DSP2_GAMMA_C196_PRE_LEN (8U) -#define DSP2_GAMMA_C196_PRE_MSK (((1U << DSP2_GAMMA_C196_PRE_LEN) - 1) << DSP2_GAMMA_C196_PRE_POS) -#define DSP2_GAMMA_C196_PRE_UMSK (~(((1U << DSP2_GAMMA_C196_PRE_LEN) - 1) << DSP2_GAMMA_C196_PRE_POS)) -#define DSP2_GAMMA_C197_PRE DSP2_GAMMA_C197_PRE -#define DSP2_GAMMA_C197_PRE_POS (8U) -#define DSP2_GAMMA_C197_PRE_LEN (8U) -#define DSP2_GAMMA_C197_PRE_MSK (((1U << DSP2_GAMMA_C197_PRE_LEN) - 1) << DSP2_GAMMA_C197_PRE_POS) -#define DSP2_GAMMA_C197_PRE_UMSK (~(((1U << DSP2_GAMMA_C197_PRE_LEN) - 1) << DSP2_GAMMA_C197_PRE_POS)) -#define DSP2_GAMMA_C198_PRE DSP2_GAMMA_C198_PRE -#define DSP2_GAMMA_C198_PRE_POS (16U) -#define DSP2_GAMMA_C198_PRE_LEN (8U) -#define DSP2_GAMMA_C198_PRE_MSK (((1U << DSP2_GAMMA_C198_PRE_LEN) - 1) << DSP2_GAMMA_C198_PRE_POS) -#define DSP2_GAMMA_C198_PRE_UMSK (~(((1U << DSP2_GAMMA_C198_PRE_LEN) - 1) << DSP2_GAMMA_C198_PRE_POS)) -#define DSP2_GAMMA_C199_PRE DSP2_GAMMA_C199_PRE -#define DSP2_GAMMA_C199_PRE_POS (24U) -#define DSP2_GAMMA_C199_PRE_LEN (8U) -#define DSP2_GAMMA_C199_PRE_MSK (((1U << DSP2_GAMMA_C199_PRE_LEN) - 1) << DSP2_GAMMA_C199_PRE_POS) -#define DSP2_GAMMA_C199_PRE_UMSK (~(((1U << DSP2_GAMMA_C199_PRE_LEN) - 1) << DSP2_GAMMA_C199_PRE_POS)) - -/* 0x7C8 : GAMMA_CRUVE_51 */ -#define DSP2_GAMMA_GAMMA_CRUVE_51_OFFSET (0x7C8) -#define DSP2_GAMMA_C200_PRE DSP2_GAMMA_C200_PRE -#define DSP2_GAMMA_C200_PRE_POS (0U) -#define DSP2_GAMMA_C200_PRE_LEN (8U) -#define DSP2_GAMMA_C200_PRE_MSK (((1U << DSP2_GAMMA_C200_PRE_LEN) - 1) << DSP2_GAMMA_C200_PRE_POS) -#define DSP2_GAMMA_C200_PRE_UMSK (~(((1U << DSP2_GAMMA_C200_PRE_LEN) - 1) << DSP2_GAMMA_C200_PRE_POS)) -#define DSP2_GAMMA_C201_PRE DSP2_GAMMA_C201_PRE -#define DSP2_GAMMA_C201_PRE_POS (8U) -#define DSP2_GAMMA_C201_PRE_LEN (8U) -#define DSP2_GAMMA_C201_PRE_MSK (((1U << DSP2_GAMMA_C201_PRE_LEN) - 1) << DSP2_GAMMA_C201_PRE_POS) -#define DSP2_GAMMA_C201_PRE_UMSK (~(((1U << DSP2_GAMMA_C201_PRE_LEN) - 1) << DSP2_GAMMA_C201_PRE_POS)) -#define DSP2_GAMMA_C202_PRE DSP2_GAMMA_C202_PRE -#define DSP2_GAMMA_C202_PRE_POS (16U) -#define DSP2_GAMMA_C202_PRE_LEN (8U) -#define DSP2_GAMMA_C202_PRE_MSK (((1U << DSP2_GAMMA_C202_PRE_LEN) - 1) << DSP2_GAMMA_C202_PRE_POS) -#define DSP2_GAMMA_C202_PRE_UMSK (~(((1U << DSP2_GAMMA_C202_PRE_LEN) - 1) << DSP2_GAMMA_C202_PRE_POS)) -#define DSP2_GAMMA_C203_PRE DSP2_GAMMA_C203_PRE -#define DSP2_GAMMA_C203_PRE_POS (24U) -#define DSP2_GAMMA_C203_PRE_LEN (8U) -#define DSP2_GAMMA_C203_PRE_MSK (((1U << DSP2_GAMMA_C203_PRE_LEN) - 1) << DSP2_GAMMA_C203_PRE_POS) -#define DSP2_GAMMA_C203_PRE_UMSK (~(((1U << DSP2_GAMMA_C203_PRE_LEN) - 1) << DSP2_GAMMA_C203_PRE_POS)) - -/* 0x7CC : GAMMA_CRUVE_52 */ -#define DSP2_GAMMA_GAMMA_CRUVE_52_OFFSET (0x7CC) -#define DSP2_GAMMA_C204_PRE DSP2_GAMMA_C204_PRE -#define DSP2_GAMMA_C204_PRE_POS (0U) -#define DSP2_GAMMA_C204_PRE_LEN (8U) -#define DSP2_GAMMA_C204_PRE_MSK (((1U << DSP2_GAMMA_C204_PRE_LEN) - 1) << DSP2_GAMMA_C204_PRE_POS) -#define DSP2_GAMMA_C204_PRE_UMSK (~(((1U << DSP2_GAMMA_C204_PRE_LEN) - 1) << DSP2_GAMMA_C204_PRE_POS)) -#define DSP2_GAMMA_C205_PRE DSP2_GAMMA_C205_PRE -#define DSP2_GAMMA_C205_PRE_POS (8U) -#define DSP2_GAMMA_C205_PRE_LEN (8U) -#define DSP2_GAMMA_C205_PRE_MSK (((1U << DSP2_GAMMA_C205_PRE_LEN) - 1) << DSP2_GAMMA_C205_PRE_POS) -#define DSP2_GAMMA_C205_PRE_UMSK (~(((1U << DSP2_GAMMA_C205_PRE_LEN) - 1) << DSP2_GAMMA_C205_PRE_POS)) -#define DSP2_GAMMA_C206_PRE DSP2_GAMMA_C206_PRE -#define DSP2_GAMMA_C206_PRE_POS (16U) -#define DSP2_GAMMA_C206_PRE_LEN (8U) -#define DSP2_GAMMA_C206_PRE_MSK (((1U << DSP2_GAMMA_C206_PRE_LEN) - 1) << DSP2_GAMMA_C206_PRE_POS) -#define DSP2_GAMMA_C206_PRE_UMSK (~(((1U << DSP2_GAMMA_C206_PRE_LEN) - 1) << DSP2_GAMMA_C206_PRE_POS)) -#define DSP2_GAMMA_C207_PRE DSP2_GAMMA_C207_PRE -#define DSP2_GAMMA_C207_PRE_POS (24U) -#define DSP2_GAMMA_C207_PRE_LEN (8U) -#define DSP2_GAMMA_C207_PRE_MSK (((1U << DSP2_GAMMA_C207_PRE_LEN) - 1) << DSP2_GAMMA_C207_PRE_POS) -#define DSP2_GAMMA_C207_PRE_UMSK (~(((1U << DSP2_GAMMA_C207_PRE_LEN) - 1) << DSP2_GAMMA_C207_PRE_POS)) - -/* 0x7D0 : GAMMA_CRUVE_53 */ -#define DSP2_GAMMA_GAMMA_CRUVE_53_OFFSET (0x7D0) -#define DSP2_GAMMA_C208_PRE DSP2_GAMMA_C208_PRE -#define DSP2_GAMMA_C208_PRE_POS (0U) -#define DSP2_GAMMA_C208_PRE_LEN (8U) -#define DSP2_GAMMA_C208_PRE_MSK (((1U << DSP2_GAMMA_C208_PRE_LEN) - 1) << DSP2_GAMMA_C208_PRE_POS) -#define DSP2_GAMMA_C208_PRE_UMSK (~(((1U << DSP2_GAMMA_C208_PRE_LEN) - 1) << DSP2_GAMMA_C208_PRE_POS)) -#define DSP2_GAMMA_C209_PRE DSP2_GAMMA_C209_PRE -#define DSP2_GAMMA_C209_PRE_POS (8U) -#define DSP2_GAMMA_C209_PRE_LEN (8U) -#define DSP2_GAMMA_C209_PRE_MSK (((1U << DSP2_GAMMA_C209_PRE_LEN) - 1) << DSP2_GAMMA_C209_PRE_POS) -#define DSP2_GAMMA_C209_PRE_UMSK (~(((1U << DSP2_GAMMA_C209_PRE_LEN) - 1) << DSP2_GAMMA_C209_PRE_POS)) -#define DSP2_GAMMA_C210_PRE DSP2_GAMMA_C210_PRE -#define DSP2_GAMMA_C210_PRE_POS (16U) -#define DSP2_GAMMA_C210_PRE_LEN (8U) -#define DSP2_GAMMA_C210_PRE_MSK (((1U << DSP2_GAMMA_C210_PRE_LEN) - 1) << DSP2_GAMMA_C210_PRE_POS) -#define DSP2_GAMMA_C210_PRE_UMSK (~(((1U << DSP2_GAMMA_C210_PRE_LEN) - 1) << DSP2_GAMMA_C210_PRE_POS)) -#define DSP2_GAMMA_C211_PRE DSP2_GAMMA_C211_PRE -#define DSP2_GAMMA_C211_PRE_POS (24U) -#define DSP2_GAMMA_C211_PRE_LEN (8U) -#define DSP2_GAMMA_C211_PRE_MSK (((1U << DSP2_GAMMA_C211_PRE_LEN) - 1) << DSP2_GAMMA_C211_PRE_POS) -#define DSP2_GAMMA_C211_PRE_UMSK (~(((1U << DSP2_GAMMA_C211_PRE_LEN) - 1) << DSP2_GAMMA_C211_PRE_POS)) - -/* 0x7D4 : GAMMA_CRUVE_54 */ -#define DSP2_GAMMA_GAMMA_CRUVE_54_OFFSET (0x7D4) -#define DSP2_GAMMA_C212_PRE DSP2_GAMMA_C212_PRE -#define DSP2_GAMMA_C212_PRE_POS (0U) -#define DSP2_GAMMA_C212_PRE_LEN (8U) -#define DSP2_GAMMA_C212_PRE_MSK (((1U << DSP2_GAMMA_C212_PRE_LEN) - 1) << DSP2_GAMMA_C212_PRE_POS) -#define DSP2_GAMMA_C212_PRE_UMSK (~(((1U << DSP2_GAMMA_C212_PRE_LEN) - 1) << DSP2_GAMMA_C212_PRE_POS)) -#define DSP2_GAMMA_C213_PRE DSP2_GAMMA_C213_PRE -#define DSP2_GAMMA_C213_PRE_POS (8U) -#define DSP2_GAMMA_C213_PRE_LEN (8U) -#define DSP2_GAMMA_C213_PRE_MSK (((1U << DSP2_GAMMA_C213_PRE_LEN) - 1) << DSP2_GAMMA_C213_PRE_POS) -#define DSP2_GAMMA_C213_PRE_UMSK (~(((1U << DSP2_GAMMA_C213_PRE_LEN) - 1) << DSP2_GAMMA_C213_PRE_POS)) -#define DSP2_GAMMA_C214_PRE DSP2_GAMMA_C214_PRE -#define DSP2_GAMMA_C214_PRE_POS (16U) -#define DSP2_GAMMA_C214_PRE_LEN (8U) -#define DSP2_GAMMA_C214_PRE_MSK (((1U << DSP2_GAMMA_C214_PRE_LEN) - 1) << DSP2_GAMMA_C214_PRE_POS) -#define DSP2_GAMMA_C214_PRE_UMSK (~(((1U << DSP2_GAMMA_C214_PRE_LEN) - 1) << DSP2_GAMMA_C214_PRE_POS)) -#define DSP2_GAMMA_C215_PRE DSP2_GAMMA_C215_PRE -#define DSP2_GAMMA_C215_PRE_POS (24U) -#define DSP2_GAMMA_C215_PRE_LEN (8U) -#define DSP2_GAMMA_C215_PRE_MSK (((1U << DSP2_GAMMA_C215_PRE_LEN) - 1) << DSP2_GAMMA_C215_PRE_POS) -#define DSP2_GAMMA_C215_PRE_UMSK (~(((1U << DSP2_GAMMA_C215_PRE_LEN) - 1) << DSP2_GAMMA_C215_PRE_POS)) - -/* 0x7D8 : GAMMA_CRUVE_55 */ -#define DSP2_GAMMA_GAMMA_CRUVE_55_OFFSET (0x7D8) -#define DSP2_GAMMA_C216_PRE DSP2_GAMMA_C216_PRE -#define DSP2_GAMMA_C216_PRE_POS (0U) -#define DSP2_GAMMA_C216_PRE_LEN (8U) -#define DSP2_GAMMA_C216_PRE_MSK (((1U << DSP2_GAMMA_C216_PRE_LEN) - 1) << DSP2_GAMMA_C216_PRE_POS) -#define DSP2_GAMMA_C216_PRE_UMSK (~(((1U << DSP2_GAMMA_C216_PRE_LEN) - 1) << DSP2_GAMMA_C216_PRE_POS)) -#define DSP2_GAMMA_C217_PRE DSP2_GAMMA_C217_PRE -#define DSP2_GAMMA_C217_PRE_POS (8U) -#define DSP2_GAMMA_C217_PRE_LEN (8U) -#define DSP2_GAMMA_C217_PRE_MSK (((1U << DSP2_GAMMA_C217_PRE_LEN) - 1) << DSP2_GAMMA_C217_PRE_POS) -#define DSP2_GAMMA_C217_PRE_UMSK (~(((1U << DSP2_GAMMA_C217_PRE_LEN) - 1) << DSP2_GAMMA_C217_PRE_POS)) -#define DSP2_GAMMA_C218_PRE DSP2_GAMMA_C218_PRE -#define DSP2_GAMMA_C218_PRE_POS (16U) -#define DSP2_GAMMA_C218_PRE_LEN (8U) -#define DSP2_GAMMA_C218_PRE_MSK (((1U << DSP2_GAMMA_C218_PRE_LEN) - 1) << DSP2_GAMMA_C218_PRE_POS) -#define DSP2_GAMMA_C218_PRE_UMSK (~(((1U << DSP2_GAMMA_C218_PRE_LEN) - 1) << DSP2_GAMMA_C218_PRE_POS)) -#define DSP2_GAMMA_C219_PRE DSP2_GAMMA_C219_PRE -#define DSP2_GAMMA_C219_PRE_POS (24U) -#define DSP2_GAMMA_C219_PRE_LEN (8U) -#define DSP2_GAMMA_C219_PRE_MSK (((1U << DSP2_GAMMA_C219_PRE_LEN) - 1) << DSP2_GAMMA_C219_PRE_POS) -#define DSP2_GAMMA_C219_PRE_UMSK (~(((1U << DSP2_GAMMA_C219_PRE_LEN) - 1) << DSP2_GAMMA_C219_PRE_POS)) - -/* 0x7DC : GAMMA_CRUVE_56 */ -#define DSP2_GAMMA_GAMMA_CRUVE_56_OFFSET (0x7DC) -#define DSP2_GAMMA_C220_PRE DSP2_GAMMA_C220_PRE -#define DSP2_GAMMA_C220_PRE_POS (0U) -#define DSP2_GAMMA_C220_PRE_LEN (8U) -#define DSP2_GAMMA_C220_PRE_MSK (((1U << DSP2_GAMMA_C220_PRE_LEN) - 1) << DSP2_GAMMA_C220_PRE_POS) -#define DSP2_GAMMA_C220_PRE_UMSK (~(((1U << DSP2_GAMMA_C220_PRE_LEN) - 1) << DSP2_GAMMA_C220_PRE_POS)) -#define DSP2_GAMMA_C221_PRE DSP2_GAMMA_C221_PRE -#define DSP2_GAMMA_C221_PRE_POS (8U) -#define DSP2_GAMMA_C221_PRE_LEN (8U) -#define DSP2_GAMMA_C221_PRE_MSK (((1U << DSP2_GAMMA_C221_PRE_LEN) - 1) << DSP2_GAMMA_C221_PRE_POS) -#define DSP2_GAMMA_C221_PRE_UMSK (~(((1U << DSP2_GAMMA_C221_PRE_LEN) - 1) << DSP2_GAMMA_C221_PRE_POS)) -#define DSP2_GAMMA_C222_PRE DSP2_GAMMA_C222_PRE -#define DSP2_GAMMA_C222_PRE_POS (16U) -#define DSP2_GAMMA_C222_PRE_LEN (8U) -#define DSP2_GAMMA_C222_PRE_MSK (((1U << DSP2_GAMMA_C222_PRE_LEN) - 1) << DSP2_GAMMA_C222_PRE_POS) -#define DSP2_GAMMA_C222_PRE_UMSK (~(((1U << DSP2_GAMMA_C222_PRE_LEN) - 1) << DSP2_GAMMA_C222_PRE_POS)) -#define DSP2_GAMMA_C223_PRE DSP2_GAMMA_C223_PRE -#define DSP2_GAMMA_C223_PRE_POS (24U) -#define DSP2_GAMMA_C223_PRE_LEN (8U) -#define DSP2_GAMMA_C223_PRE_MSK (((1U << DSP2_GAMMA_C223_PRE_LEN) - 1) << DSP2_GAMMA_C223_PRE_POS) -#define DSP2_GAMMA_C223_PRE_UMSK (~(((1U << DSP2_GAMMA_C223_PRE_LEN) - 1) << DSP2_GAMMA_C223_PRE_POS)) - -/* 0x7E0 : GAMMA_CRUVE_57 */ -#define DSP2_GAMMA_GAMMA_CRUVE_57_OFFSET (0x7E0) -#define DSP2_GAMMA_C224_PRE DSP2_GAMMA_C224_PRE -#define DSP2_GAMMA_C224_PRE_POS (0U) -#define DSP2_GAMMA_C224_PRE_LEN (8U) -#define DSP2_GAMMA_C224_PRE_MSK (((1U << DSP2_GAMMA_C224_PRE_LEN) - 1) << DSP2_GAMMA_C224_PRE_POS) -#define DSP2_GAMMA_C224_PRE_UMSK (~(((1U << DSP2_GAMMA_C224_PRE_LEN) - 1) << DSP2_GAMMA_C224_PRE_POS)) -#define DSP2_GAMMA_C225_PRE DSP2_GAMMA_C225_PRE -#define DSP2_GAMMA_C225_PRE_POS (8U) -#define DSP2_GAMMA_C225_PRE_LEN (8U) -#define DSP2_GAMMA_C225_PRE_MSK (((1U << DSP2_GAMMA_C225_PRE_LEN) - 1) << DSP2_GAMMA_C225_PRE_POS) -#define DSP2_GAMMA_C225_PRE_UMSK (~(((1U << DSP2_GAMMA_C225_PRE_LEN) - 1) << DSP2_GAMMA_C225_PRE_POS)) -#define DSP2_GAMMA_C226_PRE DSP2_GAMMA_C226_PRE -#define DSP2_GAMMA_C226_PRE_POS (16U) -#define DSP2_GAMMA_C226_PRE_LEN (8U) -#define DSP2_GAMMA_C226_PRE_MSK (((1U << DSP2_GAMMA_C226_PRE_LEN) - 1) << DSP2_GAMMA_C226_PRE_POS) -#define DSP2_GAMMA_C226_PRE_UMSK (~(((1U << DSP2_GAMMA_C226_PRE_LEN) - 1) << DSP2_GAMMA_C226_PRE_POS)) -#define DSP2_GAMMA_C227_PRE DSP2_GAMMA_C227_PRE -#define DSP2_GAMMA_C227_PRE_POS (24U) -#define DSP2_GAMMA_C227_PRE_LEN (8U) -#define DSP2_GAMMA_C227_PRE_MSK (((1U << DSP2_GAMMA_C227_PRE_LEN) - 1) << DSP2_GAMMA_C227_PRE_POS) -#define DSP2_GAMMA_C227_PRE_UMSK (~(((1U << DSP2_GAMMA_C227_PRE_LEN) - 1) << DSP2_GAMMA_C227_PRE_POS)) - -/* 0x7E4 : GAMMA_CRUVE_58 */ -#define DSP2_GAMMA_GAMMA_CRUVE_58_OFFSET (0x7E4) -#define DSP2_GAMMA_C228_PRE DSP2_GAMMA_C228_PRE -#define DSP2_GAMMA_C228_PRE_POS (0U) -#define DSP2_GAMMA_C228_PRE_LEN (8U) -#define DSP2_GAMMA_C228_PRE_MSK (((1U << DSP2_GAMMA_C228_PRE_LEN) - 1) << DSP2_GAMMA_C228_PRE_POS) -#define DSP2_GAMMA_C228_PRE_UMSK (~(((1U << DSP2_GAMMA_C228_PRE_LEN) - 1) << DSP2_GAMMA_C228_PRE_POS)) -#define DSP2_GAMMA_C229_PRE DSP2_GAMMA_C229_PRE -#define DSP2_GAMMA_C229_PRE_POS (8U) -#define DSP2_GAMMA_C229_PRE_LEN (8U) -#define DSP2_GAMMA_C229_PRE_MSK (((1U << DSP2_GAMMA_C229_PRE_LEN) - 1) << DSP2_GAMMA_C229_PRE_POS) -#define DSP2_GAMMA_C229_PRE_UMSK (~(((1U << DSP2_GAMMA_C229_PRE_LEN) - 1) << DSP2_GAMMA_C229_PRE_POS)) -#define DSP2_GAMMA_C230_PRE DSP2_GAMMA_C230_PRE -#define DSP2_GAMMA_C230_PRE_POS (16U) -#define DSP2_GAMMA_C230_PRE_LEN (8U) -#define DSP2_GAMMA_C230_PRE_MSK (((1U << DSP2_GAMMA_C230_PRE_LEN) - 1) << DSP2_GAMMA_C230_PRE_POS) -#define DSP2_GAMMA_C230_PRE_UMSK (~(((1U << DSP2_GAMMA_C230_PRE_LEN) - 1) << DSP2_GAMMA_C230_PRE_POS)) -#define DSP2_GAMMA_C231_PRE DSP2_GAMMA_C231_PRE -#define DSP2_GAMMA_C231_PRE_POS (24U) -#define DSP2_GAMMA_C231_PRE_LEN (8U) -#define DSP2_GAMMA_C231_PRE_MSK (((1U << DSP2_GAMMA_C231_PRE_LEN) - 1) << DSP2_GAMMA_C231_PRE_POS) -#define DSP2_GAMMA_C231_PRE_UMSK (~(((1U << DSP2_GAMMA_C231_PRE_LEN) - 1) << DSP2_GAMMA_C231_PRE_POS)) - -/* 0x7E8 : GAMMA_CRUVE_59 */ -#define DSP2_GAMMA_GAMMA_CRUVE_59_OFFSET (0x7E8) -#define DSP2_GAMMA_C232_PRE DSP2_GAMMA_C232_PRE -#define DSP2_GAMMA_C232_PRE_POS (0U) -#define DSP2_GAMMA_C232_PRE_LEN (8U) -#define DSP2_GAMMA_C232_PRE_MSK (((1U << DSP2_GAMMA_C232_PRE_LEN) - 1) << DSP2_GAMMA_C232_PRE_POS) -#define DSP2_GAMMA_C232_PRE_UMSK (~(((1U << DSP2_GAMMA_C232_PRE_LEN) - 1) << DSP2_GAMMA_C232_PRE_POS)) -#define DSP2_GAMMA_C233_PRE DSP2_GAMMA_C233_PRE -#define DSP2_GAMMA_C233_PRE_POS (8U) -#define DSP2_GAMMA_C233_PRE_LEN (8U) -#define DSP2_GAMMA_C233_PRE_MSK (((1U << DSP2_GAMMA_C233_PRE_LEN) - 1) << DSP2_GAMMA_C233_PRE_POS) -#define DSP2_GAMMA_C233_PRE_UMSK (~(((1U << DSP2_GAMMA_C233_PRE_LEN) - 1) << DSP2_GAMMA_C233_PRE_POS)) -#define DSP2_GAMMA_C234_PRE DSP2_GAMMA_C234_PRE -#define DSP2_GAMMA_C234_PRE_POS (16U) -#define DSP2_GAMMA_C234_PRE_LEN (8U) -#define DSP2_GAMMA_C234_PRE_MSK (((1U << DSP2_GAMMA_C234_PRE_LEN) - 1) << DSP2_GAMMA_C234_PRE_POS) -#define DSP2_GAMMA_C234_PRE_UMSK (~(((1U << DSP2_GAMMA_C234_PRE_LEN) - 1) << DSP2_GAMMA_C234_PRE_POS)) -#define DSP2_GAMMA_C235_PRE DSP2_GAMMA_C235_PRE -#define DSP2_GAMMA_C235_PRE_POS (24U) -#define DSP2_GAMMA_C235_PRE_LEN (8U) -#define DSP2_GAMMA_C235_PRE_MSK (((1U << DSP2_GAMMA_C235_PRE_LEN) - 1) << DSP2_GAMMA_C235_PRE_POS) -#define DSP2_GAMMA_C235_PRE_UMSK (~(((1U << DSP2_GAMMA_C235_PRE_LEN) - 1) << DSP2_GAMMA_C235_PRE_POS)) - -/* 0x7EC : GAMMA_CRUVE_60 */ -#define DSP2_GAMMA_GAMMA_CRUVE_60_OFFSET (0x7EC) -#define DSP2_GAMMA_C236_PRE DSP2_GAMMA_C236_PRE -#define DSP2_GAMMA_C236_PRE_POS (0U) -#define DSP2_GAMMA_C236_PRE_LEN (8U) -#define DSP2_GAMMA_C236_PRE_MSK (((1U << DSP2_GAMMA_C236_PRE_LEN) - 1) << DSP2_GAMMA_C236_PRE_POS) -#define DSP2_GAMMA_C236_PRE_UMSK (~(((1U << DSP2_GAMMA_C236_PRE_LEN) - 1) << DSP2_GAMMA_C236_PRE_POS)) -#define DSP2_GAMMA_C237_PRE DSP2_GAMMA_C237_PRE -#define DSP2_GAMMA_C237_PRE_POS (8U) -#define DSP2_GAMMA_C237_PRE_LEN (8U) -#define DSP2_GAMMA_C237_PRE_MSK (((1U << DSP2_GAMMA_C237_PRE_LEN) - 1) << DSP2_GAMMA_C237_PRE_POS) -#define DSP2_GAMMA_C237_PRE_UMSK (~(((1U << DSP2_GAMMA_C237_PRE_LEN) - 1) << DSP2_GAMMA_C237_PRE_POS)) -#define DSP2_GAMMA_C238_PRE DSP2_GAMMA_C238_PRE -#define DSP2_GAMMA_C238_PRE_POS (16U) -#define DSP2_GAMMA_C238_PRE_LEN (8U) -#define DSP2_GAMMA_C238_PRE_MSK (((1U << DSP2_GAMMA_C238_PRE_LEN) - 1) << DSP2_GAMMA_C238_PRE_POS) -#define DSP2_GAMMA_C238_PRE_UMSK (~(((1U << DSP2_GAMMA_C238_PRE_LEN) - 1) << DSP2_GAMMA_C238_PRE_POS)) -#define DSP2_GAMMA_C239_PRE DSP2_GAMMA_C239_PRE -#define DSP2_GAMMA_C239_PRE_POS (24U) -#define DSP2_GAMMA_C239_PRE_LEN (8U) -#define DSP2_GAMMA_C239_PRE_MSK (((1U << DSP2_GAMMA_C239_PRE_LEN) - 1) << DSP2_GAMMA_C239_PRE_POS) -#define DSP2_GAMMA_C239_PRE_UMSK (~(((1U << DSP2_GAMMA_C239_PRE_LEN) - 1) << DSP2_GAMMA_C239_PRE_POS)) - -/* 0x7F0 : GAMMA_CRUVE_61 */ -#define DSP2_GAMMA_GAMMA_CRUVE_61_OFFSET (0x7F0) -#define DSP2_GAMMA_C240_PRE DSP2_GAMMA_C240_PRE -#define DSP2_GAMMA_C240_PRE_POS (0U) -#define DSP2_GAMMA_C240_PRE_LEN (8U) -#define DSP2_GAMMA_C240_PRE_MSK (((1U << DSP2_GAMMA_C240_PRE_LEN) - 1) << DSP2_GAMMA_C240_PRE_POS) -#define DSP2_GAMMA_C240_PRE_UMSK (~(((1U << DSP2_GAMMA_C240_PRE_LEN) - 1) << DSP2_GAMMA_C240_PRE_POS)) -#define DSP2_GAMMA_C241_PRE DSP2_GAMMA_C241_PRE -#define DSP2_GAMMA_C241_PRE_POS (8U) -#define DSP2_GAMMA_C241_PRE_LEN (8U) -#define DSP2_GAMMA_C241_PRE_MSK (((1U << DSP2_GAMMA_C241_PRE_LEN) - 1) << DSP2_GAMMA_C241_PRE_POS) -#define DSP2_GAMMA_C241_PRE_UMSK (~(((1U << DSP2_GAMMA_C241_PRE_LEN) - 1) << DSP2_GAMMA_C241_PRE_POS)) -#define DSP2_GAMMA_C242_PRE DSP2_GAMMA_C242_PRE -#define DSP2_GAMMA_C242_PRE_POS (16U) -#define DSP2_GAMMA_C242_PRE_LEN (8U) -#define DSP2_GAMMA_C242_PRE_MSK (((1U << DSP2_GAMMA_C242_PRE_LEN) - 1) << DSP2_GAMMA_C242_PRE_POS) -#define DSP2_GAMMA_C242_PRE_UMSK (~(((1U << DSP2_GAMMA_C242_PRE_LEN) - 1) << DSP2_GAMMA_C242_PRE_POS)) -#define DSP2_GAMMA_C243_PRE DSP2_GAMMA_C243_PRE -#define DSP2_GAMMA_C243_PRE_POS (24U) -#define DSP2_GAMMA_C243_PRE_LEN (8U) -#define DSP2_GAMMA_C243_PRE_MSK (((1U << DSP2_GAMMA_C243_PRE_LEN) - 1) << DSP2_GAMMA_C243_PRE_POS) -#define DSP2_GAMMA_C243_PRE_UMSK (~(((1U << DSP2_GAMMA_C243_PRE_LEN) - 1) << DSP2_GAMMA_C243_PRE_POS)) - -/* 0x7F4 : GAMMA_CRUVE_62 */ -#define DSP2_GAMMA_GAMMA_CRUVE_62_OFFSET (0x7F4) -#define DSP2_GAMMA_C244_PRE DSP2_GAMMA_C244_PRE -#define DSP2_GAMMA_C244_PRE_POS (0U) -#define DSP2_GAMMA_C244_PRE_LEN (8U) -#define DSP2_GAMMA_C244_PRE_MSK (((1U << DSP2_GAMMA_C244_PRE_LEN) - 1) << DSP2_GAMMA_C244_PRE_POS) -#define DSP2_GAMMA_C244_PRE_UMSK (~(((1U << DSP2_GAMMA_C244_PRE_LEN) - 1) << DSP2_GAMMA_C244_PRE_POS)) -#define DSP2_GAMMA_C245_PRE DSP2_GAMMA_C245_PRE -#define DSP2_GAMMA_C245_PRE_POS (8U) -#define DSP2_GAMMA_C245_PRE_LEN (8U) -#define DSP2_GAMMA_C245_PRE_MSK (((1U << DSP2_GAMMA_C245_PRE_LEN) - 1) << DSP2_GAMMA_C245_PRE_POS) -#define DSP2_GAMMA_C245_PRE_UMSK (~(((1U << DSP2_GAMMA_C245_PRE_LEN) - 1) << DSP2_GAMMA_C245_PRE_POS)) -#define DSP2_GAMMA_C246_PRE DSP2_GAMMA_C246_PRE -#define DSP2_GAMMA_C246_PRE_POS (16U) -#define DSP2_GAMMA_C246_PRE_LEN (8U) -#define DSP2_GAMMA_C246_PRE_MSK (((1U << DSP2_GAMMA_C246_PRE_LEN) - 1) << DSP2_GAMMA_C246_PRE_POS) -#define DSP2_GAMMA_C246_PRE_UMSK (~(((1U << DSP2_GAMMA_C246_PRE_LEN) - 1) << DSP2_GAMMA_C246_PRE_POS)) -#define DSP2_GAMMA_C247_PRE DSP2_GAMMA_C247_PRE -#define DSP2_GAMMA_C247_PRE_POS (24U) -#define DSP2_GAMMA_C247_PRE_LEN (8U) -#define DSP2_GAMMA_C247_PRE_MSK (((1U << DSP2_GAMMA_C247_PRE_LEN) - 1) << DSP2_GAMMA_C247_PRE_POS) -#define DSP2_GAMMA_C247_PRE_UMSK (~(((1U << DSP2_GAMMA_C247_PRE_LEN) - 1) << DSP2_GAMMA_C247_PRE_POS)) - -/* 0x7F8 : GAMMA_CRUVE_63 */ -#define DSP2_GAMMA_GAMMA_CRUVE_63_OFFSET (0x7F8) -#define DSP2_GAMMA_C248_PRE DSP2_GAMMA_C248_PRE -#define DSP2_GAMMA_C248_PRE_POS (0U) -#define DSP2_GAMMA_C248_PRE_LEN (8U) -#define DSP2_GAMMA_C248_PRE_MSK (((1U << DSP2_GAMMA_C248_PRE_LEN) - 1) << DSP2_GAMMA_C248_PRE_POS) -#define DSP2_GAMMA_C248_PRE_UMSK (~(((1U << DSP2_GAMMA_C248_PRE_LEN) - 1) << DSP2_GAMMA_C248_PRE_POS)) -#define DSP2_GAMMA_C249_PRE DSP2_GAMMA_C249_PRE -#define DSP2_GAMMA_C249_PRE_POS (8U) -#define DSP2_GAMMA_C249_PRE_LEN (8U) -#define DSP2_GAMMA_C249_PRE_MSK (((1U << DSP2_GAMMA_C249_PRE_LEN) - 1) << DSP2_GAMMA_C249_PRE_POS) -#define DSP2_GAMMA_C249_PRE_UMSK (~(((1U << DSP2_GAMMA_C249_PRE_LEN) - 1) << DSP2_GAMMA_C249_PRE_POS)) -#define DSP2_GAMMA_C250_PRE DSP2_GAMMA_C250_PRE -#define DSP2_GAMMA_C250_PRE_POS (16U) -#define DSP2_GAMMA_C250_PRE_LEN (8U) -#define DSP2_GAMMA_C250_PRE_MSK (((1U << DSP2_GAMMA_C250_PRE_LEN) - 1) << DSP2_GAMMA_C250_PRE_POS) -#define DSP2_GAMMA_C250_PRE_UMSK (~(((1U << DSP2_GAMMA_C250_PRE_LEN) - 1) << DSP2_GAMMA_C250_PRE_POS)) -#define DSP2_GAMMA_C251_PRE DSP2_GAMMA_C251_PRE -#define DSP2_GAMMA_C251_PRE_POS (24U) -#define DSP2_GAMMA_C251_PRE_LEN (8U) -#define DSP2_GAMMA_C251_PRE_MSK (((1U << DSP2_GAMMA_C251_PRE_LEN) - 1) << DSP2_GAMMA_C251_PRE_POS) -#define DSP2_GAMMA_C251_PRE_UMSK (~(((1U << DSP2_GAMMA_C251_PRE_LEN) - 1) << DSP2_GAMMA_C251_PRE_POS)) - -/* 0x7FC : GAMMA_CRUVE_64 */ -#define DSP2_GAMMA_GAMMA_CRUVE_64_OFFSET (0x7FC) -#define DSP2_GAMMA_C252_PRE DSP2_GAMMA_C252_PRE -#define DSP2_GAMMA_C252_PRE_POS (0U) -#define DSP2_GAMMA_C252_PRE_LEN (8U) -#define DSP2_GAMMA_C252_PRE_MSK (((1U << DSP2_GAMMA_C252_PRE_LEN) - 1) << DSP2_GAMMA_C252_PRE_POS) -#define DSP2_GAMMA_C252_PRE_UMSK (~(((1U << DSP2_GAMMA_C252_PRE_LEN) - 1) << DSP2_GAMMA_C252_PRE_POS)) -#define DSP2_GAMMA_C253_PRE DSP2_GAMMA_C253_PRE -#define DSP2_GAMMA_C253_PRE_POS (8U) -#define DSP2_GAMMA_C253_PRE_LEN (8U) -#define DSP2_GAMMA_C253_PRE_MSK (((1U << DSP2_GAMMA_C253_PRE_LEN) - 1) << DSP2_GAMMA_C253_PRE_POS) -#define DSP2_GAMMA_C253_PRE_UMSK (~(((1U << DSP2_GAMMA_C253_PRE_LEN) - 1) << DSP2_GAMMA_C253_PRE_POS)) -#define DSP2_GAMMA_C254_PRE DSP2_GAMMA_C254_PRE -#define DSP2_GAMMA_C254_PRE_POS (16U) -#define DSP2_GAMMA_C254_PRE_LEN (8U) -#define DSP2_GAMMA_C254_PRE_MSK (((1U << DSP2_GAMMA_C254_PRE_LEN) - 1) << DSP2_GAMMA_C254_PRE_POS) -#define DSP2_GAMMA_C254_PRE_UMSK (~(((1U << DSP2_GAMMA_C254_PRE_LEN) - 1) << DSP2_GAMMA_C254_PRE_POS)) -#define DSP2_GAMMA_C255_PRE DSP2_GAMMA_C255_PRE -#define DSP2_GAMMA_C255_PRE_POS (24U) -#define DSP2_GAMMA_C255_PRE_LEN (8U) -#define DSP2_GAMMA_C255_PRE_MSK (((1U << DSP2_GAMMA_C255_PRE_LEN) - 1) << DSP2_GAMMA_C255_PRE_POS) -#define DSP2_GAMMA_C255_PRE_UMSK (~(((1U << DSP2_GAMMA_C255_PRE_LEN) - 1) << DSP2_GAMMA_C255_PRE_POS)) - -struct dsp2_gamma_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1792]; - - /* 0x700 : GAMMA_CRUVE_1 */ - union { - struct - { - uint32_t c0_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t c1_pre : 8; /* [15: 8], r/w, 0x5 */ - uint32_t c2_pre : 8; /* [23:16], r/w, 0x7 */ - uint32_t c3_pre : 8; /* [31:24], r/w, 0xa */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_1; - - /* 0x704 : GAMMA_CRUVE_2 */ - union { - struct - { - uint32_t c4_pre : 8; /* [ 7: 0], r/w, 0xd */ - uint32_t c5_pre : 8; /* [15: 8], r/w, 0x11 */ - uint32_t c6_pre : 8; /* [23:16], r/w, 0x14 */ - uint32_t c7_pre : 8; /* [31:24], r/w, 0x17 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_2; - - /* 0x708 : GAMMA_CRUVE_3 */ - union { - struct - { - uint32_t c8_pre : 8; /* [ 7: 0], r/w, 0x1a */ - uint32_t c9_pre : 8; /* [15: 8], r/w, 0x1e */ - uint32_t c10_pre : 8; /* [23:16], r/w, 0x21 */ - uint32_t c11_pre : 8; /* [31:24], r/w, 0x24 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_3; - - /* 0x70C : GAMMA_CRUVE_4 */ - union { - struct - { - uint32_t c12_pre : 8; /* [ 7: 0], r/w, 0x27 */ - uint32_t c13_pre : 8; /* [15: 8], r/w, 0x2a */ - uint32_t c14_pre : 8; /* [23:16], r/w, 0x2d */ - uint32_t c15_pre : 8; /* [31:24], r/w, 0x30 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_4; - - /* 0x710 : GAMMA_CRUVE_5 */ - union { - struct - { - uint32_t c16_pre : 8; /* [ 7: 0], r/w, 0x34 */ - uint32_t c17_pre : 8; /* [15: 8], r/w, 0x36 */ - uint32_t c18_pre : 8; /* [23:16], r/w, 0x39 */ - uint32_t c19_pre : 8; /* [31:24], r/w, 0x3c */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_5; - - /* 0x714 : GAMMA_CRUVE_6 */ - union { - struct - { - uint32_t c20_pre : 8; /* [ 7: 0], r/w, 0x3f */ - uint32_t c21_pre : 8; /* [15: 8], r/w, 0x42 */ - uint32_t c22_pre : 8; /* [23:16], r/w, 0x45 */ - uint32_t c23_pre : 8; /* [31:24], r/w, 0x47 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_6; - - /* 0x718 : GAMMA_CRUVE_7 */ - union { - struct - { - uint32_t c24_pre : 8; /* [ 7: 0], r/w, 0x4a */ - uint32_t c25_pre : 8; /* [15: 8], r/w, 0x4d */ - uint32_t c26_pre : 8; /* [23:16], r/w, 0x4f */ - uint32_t c27_pre : 8; /* [31:24], r/w, 0x52 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_7; - - /* 0x71C : GAMMA_CRUVE_8 */ - union { - struct - { - uint32_t c28_pre : 8; /* [ 7: 0], r/w, 0x54 */ - uint32_t c29_pre : 8; /* [15: 8], r/w, 0x57 */ - uint32_t c30_pre : 8; /* [23:16], r/w, 0x59 */ - uint32_t c31_pre : 8; /* [31:24], r/w, 0x5b */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_8; - - /* 0x720 : GAMMA_CRUVE_9 */ - union { - struct - { - uint32_t c32_pre : 8; /* [ 7: 0], r/w, 0x5e */ - uint32_t c33_pre : 8; /* [15: 8], r/w, 0x60 */ - uint32_t c34_pre : 8; /* [23:16], r/w, 0x62 */ - uint32_t c35_pre : 8; /* [31:24], r/w, 0x64 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_9; - - /* 0x724 : GAMMA_CRUVE_10 */ - union { - struct - { - uint32_t c36_pre : 8; /* [ 7: 0], r/w, 0x66 */ - uint32_t c37_pre : 8; /* [15: 8], r/w, 0x68 */ - uint32_t c38_pre : 8; /* [23:16], r/w, 0x6a */ - uint32_t c39_pre : 8; /* [31:24], r/w, 0x6c */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_10; - - /* 0x728 : GAMMA_CRUVE_11 */ - union { - struct - { - uint32_t c40_pre : 8; /* [ 7: 0], r/w, 0x6e */ - uint32_t c41_pre : 8; /* [15: 8], r/w, 0x70 */ - uint32_t c42_pre : 8; /* [23:16], r/w, 0x72 */ - uint32_t c43_pre : 8; /* [31:24], r/w, 0x74 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_11; - - /* 0x72C : GAMMA_CRUVE_12 */ - union { - struct - { - uint32_t c44_pre : 8; /* [ 7: 0], r/w, 0x76 */ - uint32_t c45_pre : 8; /* [15: 8], r/w, 0x78 */ - uint32_t c46_pre : 8; /* [23:16], r/w, 0x7a */ - uint32_t c47_pre : 8; /* [31:24], r/w, 0x7b */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_12; - - /* 0x730 : GAMMA_CRUVE_13 */ - union { - struct - { - uint32_t c48_pre : 8; /* [ 7: 0], r/w, 0x7d */ - uint32_t c49_pre : 8; /* [15: 8], r/w, 0x7f */ - uint32_t c50_pre : 8; /* [23:16], r/w, 0x80 */ - uint32_t c51_pre : 8; /* [31:24], r/w, 0x82 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_13; - - /* 0x734 : GAMMA_CRUVE_14 */ - union { - struct - { - uint32_t c52_pre : 8; /* [ 7: 0], r/w, 0x84 */ - uint32_t c53_pre : 8; /* [15: 8], r/w, 0x85 */ - uint32_t c54_pre : 8; /* [23:16], r/w, 0x87 */ - uint32_t c55_pre : 8; /* [31:24], r/w, 0x88 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_14; - - /* 0x738 : GAMMA_CRUVE_15 */ - union { - struct - { - uint32_t c56_pre : 8; /* [ 7: 0], r/w, 0x8a */ - uint32_t c57_pre : 8; /* [15: 8], r/w, 0x8b */ - uint32_t c58_pre : 8; /* [23:16], r/w, 0x8d */ - uint32_t c59_pre : 8; /* [31:24], r/w, 0x8e */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_15; - - /* 0x73C : GAMMA_CRUVE_16 */ - union { - struct - { - uint32_t c60_pre : 8; /* [ 7: 0], r/w, 0x90 */ - uint32_t c61_pre : 8; /* [15: 8], r/w, 0x91 */ - uint32_t c62_pre : 8; /* [23:16], r/w, 0x92 */ - uint32_t c63_pre : 8; /* [31:24], r/w, 0x94 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_16; - - /* 0x740 : GAMMA_CRUVE_17 */ - union { - struct - { - uint32_t c64_pre : 8; /* [ 7: 0], r/w, 0x95 */ - uint32_t c65_pre : 8; /* [15: 8], r/w, 0x96 */ - uint32_t c66_pre : 8; /* [23:16], r/w, 0x98 */ - uint32_t c67_pre : 8; /* [31:24], r/w, 0x99 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_17; - - /* 0x744 : GAMMA_CRUVE_18 */ - union { - struct - { - uint32_t c68_pre : 8; /* [ 7: 0], r/w, 0x9a */ - uint32_t c69_pre : 8; /* [15: 8], r/w, 0x9c */ - uint32_t c70_pre : 8; /* [23:16], r/w, 0x9d */ - uint32_t c71_pre : 8; /* [31:24], r/w, 0x9e */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_18; - - /* 0x748 : GAMMA_CRUVE_19 */ - union { - struct - { - uint32_t c72_pre : 8; /* [ 7: 0], r/w, 0xa0 */ - uint32_t c73_pre : 8; /* [15: 8], r/w, 0xa1 */ - uint32_t c74_pre : 8; /* [23:16], r/w, 0xa2 */ - uint32_t c75_pre : 8; /* [31:24], r/w, 0xa3 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_19; - - /* 0x74C : GAMMA_CRUVE_20 */ - union { - struct - { - uint32_t c76_pre : 8; /* [ 7: 0], r/w, 0xa5 */ - uint32_t c77_pre : 8; /* [15: 8], r/w, 0xa6 */ - uint32_t c78_pre : 8; /* [23:16], r/w, 0xa7 */ - uint32_t c79_pre : 8; /* [31:24], r/w, 0xa8 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_20; - - /* 0x750 : GAMMA_CRUVE_21 */ - union { - struct - { - uint32_t c80_pre : 8; /* [ 7: 0], r/w, 0xa9 */ - uint32_t c81_pre : 8; /* [15: 8], r/w, 0xab */ - uint32_t c82_pre : 8; /* [23:16], r/w, 0xac */ - uint32_t c83_pre : 8; /* [31:24], r/w, 0xad */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_21; - - /* 0x754 : GAMMA_CRUVE_22 */ - union { - struct - { - uint32_t c84_pre : 8; /* [ 7: 0], r/w, 0xae */ - uint32_t c85_pre : 8; /* [15: 8], r/w, 0xaf */ - uint32_t c86_pre : 8; /* [23:16], r/w, 0xb0 */ - uint32_t c87_pre : 8; /* [31:24], r/w, 0xb1 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_22; - - /* 0x758 : GAMMA_CRUVE_23 */ - union { - struct - { - uint32_t c88_pre : 8; /* [ 7: 0], r/w, 0xb3 */ - uint32_t c89_pre : 8; /* [15: 8], r/w, 0xb4 */ - uint32_t c90_pre : 8; /* [23:16], r/w, 0xb5 */ - uint32_t c91_pre : 8; /* [31:24], r/w, 0xb6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_23; - - /* 0x75C : GAMMA_CRUVE_24 */ - union { - struct - { - uint32_t c92_pre : 8; /* [ 7: 0], r/w, 0xb7 */ - uint32_t c93_pre : 8; /* [15: 8], r/w, 0xb8 */ - uint32_t c94_pre : 8; /* [23:16], r/w, 0xb9 */ - uint32_t c95_pre : 8; /* [31:24], r/w, 0xba */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_24; - - /* 0x760 : GAMMA_CRUVE_25 */ - union { - struct - { - uint32_t c96_pre : 8; /* [ 7: 0], r/w, 0xbb */ - uint32_t c97_pre : 8; /* [15: 8], r/w, 0xbc */ - uint32_t c98_pre : 8; /* [23:16], r/w, 0xbd */ - uint32_t c99_pre : 8; /* [31:24], r/w, 0xbe */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_25; - - /* 0x764 : GAMMA_CRUVE_26 */ - union { - struct - { - uint32_t c100_pre : 8; /* [ 7: 0], r/w, 0xbf */ - uint32_t c101_pre : 8; /* [15: 8], r/w, 0xc0 */ - uint32_t c102_pre : 8; /* [23:16], r/w, 0xc1 */ - uint32_t c103_pre : 8; /* [31:24], r/w, 0xc2 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_26; - - /* 0x768 : GAMMA_CRUVE_27 */ - union { - struct - { - uint32_t c104_pre : 8; /* [ 7: 0], r/w, 0xc3 */ - uint32_t c105_pre : 8; /* [15: 8], r/w, 0xc4 */ - uint32_t c106_pre : 8; /* [23:16], r/w, 0xc5 */ - uint32_t c107_pre : 8; /* [31:24], r/w, 0xc6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_27; - - /* 0x76C : GAMMA_CRUVE_28 */ - union { - struct - { - uint32_t c108_pre : 8; /* [ 7: 0], r/w, 0xc7 */ - uint32_t c109_pre : 8; /* [15: 8], r/w, 0xc8 */ - uint32_t c110_pre : 8; /* [23:16], r/w, 0xc8 */ - uint32_t c111_pre : 8; /* [31:24], r/w, 0xc9 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_28; - - /* 0x770 : GAMMA_CRUVE_29 */ - union { - struct - { - uint32_t c112_pre : 8; /* [ 7: 0], r/w, 0xca */ - uint32_t c113_pre : 8; /* [15: 8], r/w, 0xcb */ - uint32_t c114_pre : 8; /* [23:16], r/w, 0xcc */ - uint32_t c115_pre : 8; /* [31:24], r/w, 0xcd */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_29; - - /* 0x774 : GAMMA_CRUVE_30 */ - union { - struct - { - uint32_t c116_pre : 8; /* [ 7: 0], r/w, 0xcd */ - uint32_t c117_pre : 8; /* [15: 8], r/w, 0xce */ - uint32_t c118_pre : 8; /* [23:16], r/w, 0xcf */ - uint32_t c119_pre : 8; /* [31:24], r/w, 0xd0 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_30; - - /* 0x778 : GAMMA_CRUVE_31 */ - union { - struct - { - uint32_t c120_pre : 8; /* [ 7: 0], r/w, 0xd1 */ - uint32_t c121_pre : 8; /* [15: 8], r/w, 0xd1 */ - uint32_t c122_pre : 8; /* [23:16], r/w, 0xd2 */ - uint32_t c123_pre : 8; /* [31:24], r/w, 0xd3 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_31; - - /* 0x77C : GAMMA_CRUVE_32 */ - union { - struct - { - uint32_t c124_pre : 8; /* [ 7: 0], r/w, 0xd4 */ - uint32_t c125_pre : 8; /* [15: 8], r/w, 0xd4 */ - uint32_t c126_pre : 8; /* [23:16], r/w, 0xd5 */ - uint32_t c127_pre : 8; /* [31:24], r/w, 0xd6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_32; - - /* 0x780 : GAMMA_CRUVE_33 */ - union { - struct - { - uint32_t c128_pre : 8; /* [ 7: 0], r/w, 0xd6 */ - uint32_t c129_pre : 8; /* [15: 8], r/w, 0xd7 */ - uint32_t c130_pre : 8; /* [23:16], r/w, 0xd8 */ - uint32_t c131_pre : 8; /* [31:24], r/w, 0xd8 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_33; - - /* 0x784 : GAMMA_CRUVE_34 */ - union { - struct - { - uint32_t c132_pre : 8; /* [ 7: 0], r/w, 0xd9 */ - uint32_t c133_pre : 8; /* [15: 8], r/w, 0xda */ - uint32_t c134_pre : 8; /* [23:16], r/w, 0xda */ - uint32_t c135_pre : 8; /* [31:24], r/w, 0xdb */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_34; - - /* 0x788 : GAMMA_CRUVE_35 */ - union { - struct - { - uint32_t c136_pre : 8; /* [ 7: 0], r/w, 0xdb */ - uint32_t c137_pre : 8; /* [15: 8], r/w, 0xdc */ - uint32_t c138_pre : 8; /* [23:16], r/w, 0xdd */ - uint32_t c139_pre : 8; /* [31:24], r/w, 0xdd */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_35; - - /* 0x78C : GAMMA_CRUVE_36 */ - union { - struct - { - uint32_t c140_pre : 8; /* [ 7: 0], r/w, 0xde */ - uint32_t c141_pre : 8; /* [15: 8], r/w, 0xde */ - uint32_t c142_pre : 8; /* [23:16], r/w, 0xdf */ - uint32_t c143_pre : 8; /* [31:24], r/w, 0xdf */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_36; - - /* 0x790 : GAMMA_CRUVE_37 */ - union { - struct - { - uint32_t c144_pre : 8; /* [ 7: 0], r/w, 0xe0 */ - uint32_t c145_pre : 8; /* [15: 8], r/w, 0xe1 */ - uint32_t c146_pre : 8; /* [23:16], r/w, 0xe1 */ - uint32_t c147_pre : 8; /* [31:24], r/w, 0xe2 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_37; - - /* 0x794 : GAMMA_CRUVE_38 */ - union { - struct - { - uint32_t c148_pre : 8; /* [ 7: 0], r/w, 0xe2 */ - uint32_t c149_pre : 8; /* [15: 8], r/w, 0xe3 */ - uint32_t c150_pre : 8; /* [23:16], r/w, 0xe3 */ - uint32_t c151_pre : 8; /* [31:24], r/w, 0xe4 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_38; - - /* 0x798 : GAMMA_CRUVE_39 */ - union { - struct - { - uint32_t c152_pre : 8; /* [ 7: 0], r/w, 0xe4 */ - uint32_t c153_pre : 8; /* [15: 8], r/w, 0xe5 */ - uint32_t c154_pre : 8; /* [23:16], r/w, 0xe5 */ - uint32_t c155_pre : 8; /* [31:24], r/w, 0xe5 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_39; - - /* 0x79C : GAMMA_CRUVE_40 */ - union { - struct - { - uint32_t c156_pre : 8; /* [ 7: 0], r/w, 0xe6 */ - uint32_t c157_pre : 8; /* [15: 8], r/w, 0xe6 */ - uint32_t c158_pre : 8; /* [23:16], r/w, 0xe7 */ - uint32_t c159_pre : 8; /* [31:24], r/w, 0xe7 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_40; - - /* 0x7A0 : GAMMA_CRUVE_41 */ - union { - struct - { - uint32_t c160_pre : 8; /* [ 7: 0], r/w, 0xe8 */ - uint32_t c161_pre : 8; /* [15: 8], r/w, 0xe8 */ - uint32_t c162_pre : 8; /* [23:16], r/w, 0xe9 */ - uint32_t c163_pre : 8; /* [31:24], r/w, 0xe9 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_41; - - /* 0x7A4 : GAMMA_CRUVE_42 */ - union { - struct - { - uint32_t c164_pre : 8; /* [ 7: 0], r/w, 0xe9 */ - uint32_t c165_pre : 8; /* [15: 8], r/w, 0xea */ - uint32_t c166_pre : 8; /* [23:16], r/w, 0xea */ - uint32_t c167_pre : 8; /* [31:24], r/w, 0xeb */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_42; - - /* 0x7A8 : GAMMA_CRUVE_43 */ - union { - struct - { - uint32_t c168_pre : 8; /* [ 7: 0], r/w, 0xeb */ - uint32_t c169_pre : 8; /* [15: 8], r/w, 0xeb */ - uint32_t c170_pre : 8; /* [23:16], r/w, 0xec */ - uint32_t c171_pre : 8; /* [31:24], r/w, 0xec */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_43; - - /* 0x7AC : GAMMA_CRUVE_44 */ - union { - struct - { - uint32_t c172_pre : 8; /* [ 7: 0], r/w, 0xec */ - uint32_t c173_pre : 8; /* [15: 8], r/w, 0xed */ - uint32_t c174_pre : 8; /* [23:16], r/w, 0xed */ - uint32_t c175_pre : 8; /* [31:24], r/w, 0xed */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_44; - - /* 0x7B0 : GAMMA_CRUVE_45 */ - union { - struct - { - uint32_t c176_pre : 8; /* [ 7: 0], r/w, 0xee */ - uint32_t c177_pre : 8; /* [15: 8], r/w, 0xee */ - uint32_t c178_pre : 8; /* [23:16], r/w, 0xee */ - uint32_t c179_pre : 8; /* [31:24], r/w, 0xef */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_45; - - /* 0x7B4 : GAMMA_CRUVE_46 */ - union { - struct - { - uint32_t c180_pre : 8; /* [ 7: 0], r/w, 0xef */ - uint32_t c181_pre : 8; /* [15: 8], r/w, 0xef */ - uint32_t c182_pre : 8; /* [23:16], r/w, 0xf0 */ - uint32_t c183_pre : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_46; - - /* 0x7B8 : GAMMA_CRUVE_47 */ - union { - struct - { - uint32_t c184_pre : 8; /* [ 7: 0], r/w, 0xf0 */ - uint32_t c185_pre : 8; /* [15: 8], r/w, 0xf1 */ - uint32_t c186_pre : 8; /* [23:16], r/w, 0xf1 */ - uint32_t c187_pre : 8; /* [31:24], r/w, 0xf1 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_47; - - /* 0x7BC : GAMMA_CRUVE_48 */ - union { - struct - { - uint32_t c188_pre : 8; /* [ 7: 0], r/w, 0xf2 */ - uint32_t c189_pre : 8; /* [15: 8], r/w, 0xf2 */ - uint32_t c190_pre : 8; /* [23:16], r/w, 0xf2 */ - uint32_t c191_pre : 8; /* [31:24], r/w, 0xf2 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_48; - - /* 0x7C0 : GAMMA_CRUVE_49 */ - union { - struct - { - uint32_t c192_pre : 8; /* [ 7: 0], r/w, 0xf3 */ - uint32_t c193_pre : 8; /* [15: 8], r/w, 0xf3 */ - uint32_t c194_pre : 8; /* [23:16], r/w, 0xf3 */ - uint32_t c195_pre : 8; /* [31:24], r/w, 0xf3 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_49; - - /* 0x7C4 : GAMMA_CRUVE_50 */ - union { - struct - { - uint32_t c196_pre : 8; /* [ 7: 0], r/w, 0xf4 */ - uint32_t c197_pre : 8; /* [15: 8], r/w, 0xf4 */ - uint32_t c198_pre : 8; /* [23:16], r/w, 0xf4 */ - uint32_t c199_pre : 8; /* [31:24], r/w, 0xf4 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_50; - - /* 0x7C8 : GAMMA_CRUVE_51 */ - union { - struct - { - uint32_t c200_pre : 8; /* [ 7: 0], r/w, 0xf5 */ - uint32_t c201_pre : 8; /* [15: 8], r/w, 0xf5 */ - uint32_t c202_pre : 8; /* [23:16], r/w, 0xf5 */ - uint32_t c203_pre : 8; /* [31:24], r/w, 0xf5 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_51; - - /* 0x7CC : GAMMA_CRUVE_52 */ - union { - struct - { - uint32_t c204_pre : 8; /* [ 7: 0], r/w, 0xf6 */ - uint32_t c205_pre : 8; /* [15: 8], r/w, 0xf6 */ - uint32_t c206_pre : 8; /* [23:16], r/w, 0xf6 */ - uint32_t c207_pre : 8; /* [31:24], r/w, 0xf6 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_52; - - /* 0x7D0 : GAMMA_CRUVE_53 */ - union { - struct - { - uint32_t c208_pre : 8; /* [ 7: 0], r/w, 0xf7 */ - uint32_t c209_pre : 8; /* [15: 8], r/w, 0xf7 */ - uint32_t c210_pre : 8; /* [23:16], r/w, 0xf7 */ - uint32_t c211_pre : 8; /* [31:24], r/w, 0xf7 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_53; - - /* 0x7D4 : GAMMA_CRUVE_54 */ - union { - struct - { - uint32_t c212_pre : 8; /* [ 7: 0], r/w, 0xf7 */ - uint32_t c213_pre : 8; /* [15: 8], r/w, 0xf8 */ - uint32_t c214_pre : 8; /* [23:16], r/w, 0xf8 */ - uint32_t c215_pre : 8; /* [31:24], r/w, 0xf8 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_54; - - /* 0x7D8 : GAMMA_CRUVE_55 */ - union { - struct - { - uint32_t c216_pre : 8; /* [ 7: 0], r/w, 0xf8 */ - uint32_t c217_pre : 8; /* [15: 8], r/w, 0xf8 */ - uint32_t c218_pre : 8; /* [23:16], r/w, 0xf9 */ - uint32_t c219_pre : 8; /* [31:24], r/w, 0xf9 */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_55; - - /* 0x7DC : GAMMA_CRUVE_56 */ - union { - struct - { - uint32_t c220_pre : 8; /* [ 7: 0], r/w, 0xf9 */ - uint32_t c221_pre : 8; /* [15: 8], r/w, 0xf9 */ - uint32_t c222_pre : 8; /* [23:16], r/w, 0xf9 */ - uint32_t c223_pre : 8; /* [31:24], r/w, 0xfa */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_56; - - /* 0x7E0 : GAMMA_CRUVE_57 */ - union { - struct - { - uint32_t c224_pre : 8; /* [ 7: 0], r/w, 0xfa */ - uint32_t c225_pre : 8; /* [15: 8], r/w, 0xfa */ - uint32_t c226_pre : 8; /* [23:16], r/w, 0xfa */ - uint32_t c227_pre : 8; /* [31:24], r/w, 0xfa */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_57; - - /* 0x7E4 : GAMMA_CRUVE_58 */ - union { - struct - { - uint32_t c228_pre : 8; /* [ 7: 0], r/w, 0xfb */ - uint32_t c229_pre : 8; /* [15: 8], r/w, 0xfb */ - uint32_t c230_pre : 8; /* [23:16], r/w, 0xfb */ - uint32_t c231_pre : 8; /* [31:24], r/w, 0xfb */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_58; - - /* 0x7E8 : GAMMA_CRUVE_59 */ - union { - struct - { - uint32_t c232_pre : 8; /* [ 7: 0], r/w, 0xfb */ - uint32_t c233_pre : 8; /* [15: 8], r/w, 0xfb */ - uint32_t c234_pre : 8; /* [23:16], r/w, 0xfc */ - uint32_t c235_pre : 8; /* [31:24], r/w, 0xfc */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_59; - - /* 0x7EC : GAMMA_CRUVE_60 */ - union { - struct - { - uint32_t c236_pre : 8; /* [ 7: 0], r/w, 0xfc */ - uint32_t c237_pre : 8; /* [15: 8], r/w, 0xfc */ - uint32_t c238_pre : 8; /* [23:16], r/w, 0xfc */ - uint32_t c239_pre : 8; /* [31:24], r/w, 0xfc */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_60; - - /* 0x7F0 : GAMMA_CRUVE_61 */ - union { - struct - { - uint32_t c240_pre : 8; /* [ 7: 0], r/w, 0xfd */ - uint32_t c241_pre : 8; /* [15: 8], r/w, 0xfd */ - uint32_t c242_pre : 8; /* [23:16], r/w, 0xfd */ - uint32_t c243_pre : 8; /* [31:24], r/w, 0xfd */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_61; - - /* 0x7F4 : GAMMA_CRUVE_62 */ - union { - struct - { - uint32_t c244_pre : 8; /* [ 7: 0], r/w, 0xfd */ - uint32_t c245_pre : 8; /* [15: 8], r/w, 0xfd */ - uint32_t c246_pre : 8; /* [23:16], r/w, 0xfe */ - uint32_t c247_pre : 8; /* [31:24], r/w, 0xfe */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_62; - - /* 0x7F8 : GAMMA_CRUVE_63 */ - union { - struct - { - uint32_t c248_pre : 8; /* [ 7: 0], r/w, 0xfe */ - uint32_t c249_pre : 8; /* [15: 8], r/w, 0xfe */ - uint32_t c250_pre : 8; /* [23:16], r/w, 0xfe */ - uint32_t c251_pre : 8; /* [31:24], r/w, 0xfe */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_63; - - /* 0x7FC : GAMMA_CRUVE_64 */ - union { - struct - { - uint32_t c252_pre : 8; /* [ 7: 0], r/w, 0xff */ - uint32_t c253_pre : 8; /* [15: 8], r/w, 0xff */ - uint32_t c254_pre : 8; /* [23:16], r/w, 0xff */ - uint32_t c255_pre : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } GAMMA_CRUVE_64; -}; - -typedef volatile struct dsp2_gamma_reg dsp2_gamma_reg_t; - -#endif /* __DSP2_GAMMA_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle2_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle2_reg.h deleted file mode 100644 index 993d5844b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle2_reg.h +++ /dev/null @@ -1,1115 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle2_reg.h - * @version V1.0 - * @date 2021-02-05 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE2_REG_H__ -#define __DSP2_MIDDLE2_REG_H__ - -#include "bl808.h" - -/* 0x800 : BDM_1 */ -#define DSP2_MIDDLE2_BDM_1_OFFSET (0x800) -#define DSP2_MIDDLE2_BDM_EB_PRE DSP2_MIDDLE2_BDM_EB_PRE -#define DSP2_MIDDLE2_BDM_EB_PRE_POS (0U) -#define DSP2_MIDDLE2_BDM_EB_PRE_LEN (1U) -#define DSP2_MIDDLE2_BDM_EB_PRE_MSK (((1U << DSP2_MIDDLE2_BDM_EB_PRE_LEN) - 1) << DSP2_MIDDLE2_BDM_EB_PRE_POS) -#define DSP2_MIDDLE2_BDM_EB_PRE_UMSK (~(((1U << DSP2_MIDDLE2_BDM_EB_PRE_LEN) - 1) << DSP2_MIDDLE2_BDM_EB_PRE_POS)) -#define DSP2_MIDDLE2_GW_THR_PRE DSP2_MIDDLE2_GW_THR_PRE -#define DSP2_MIDDLE2_GW_THR_PRE_POS (8U) -#define DSP2_MIDDLE2_GW_THR_PRE_LEN (5U) -#define DSP2_MIDDLE2_GW_THR_PRE_MSK (((1U << DSP2_MIDDLE2_GW_THR_PRE_LEN) - 1) << DSP2_MIDDLE2_GW_THR_PRE_POS) -#define DSP2_MIDDLE2_GW_THR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_GW_THR_PRE_LEN) - 1) << DSP2_MIDDLE2_GW_THR_PRE_POS)) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE DSP2_MIDDLE2_G_SCAL_FACTOR_PRE -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_POS (16U) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_LEN (9U) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_MSK (((1U << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_POS) -#define DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_G_SCAL_FACTOR_PRE_POS)) - -/* 0x804 : BDM_2 */ -#define DSP2_MIDDLE2_BDM_2_OFFSET (0x804) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE DSP2_MIDDLE2_R_SCAL_FACTOR_PRE -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_POS (0U) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_LEN (9U) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_MSK (((1U << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_POS) -#define DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_R_SCAL_FACTOR_PRE_POS)) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE DSP2_MIDDLE2_B_SCAL_FACTOR_PRE -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_POS (16U) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_LEN (9U) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_MSK (((1U << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_POS) -#define DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_UMSK (~(((1U << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_LEN) - 1) << DSP2_MIDDLE2_B_SCAL_FACTOR_PRE_POS)) - -/* 0x808 : BDM_3 */ -#define DSP2_MIDDLE2_BDM_3_OFFSET (0x808) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE DSP2_MIDDLE2_NR_PROFILE10_PRE -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE10_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE10_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE10_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE10_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE10_PRE_POS)) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE DSP2_MIDDLE2_NR_PROFILE00_PRE -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_POS (16U) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE00_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE00_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE00_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE00_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE00_PRE_POS)) - -/* 0x80C : BDM_4 */ -#define DSP2_MIDDLE2_BDM_4_OFFSET (0x80C) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE DSP2_MIDDLE2_NR_PROFILE30_PRE -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE30_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE30_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE30_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE30_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE30_PRE_POS)) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE DSP2_MIDDLE2_NR_PROFILE20_PRE -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_POS (16U) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE20_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE20_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE20_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE20_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE20_PRE_POS)) - -/* 0x810 : BDM_5 */ -#define DSP2_MIDDLE2_BDM_5_OFFSET (0x810) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE DSP2_MIDDLE2_NR_PROFILE50_PRE -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE50_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE50_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE50_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE50_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE50_PRE_POS)) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE DSP2_MIDDLE2_NR_PROFILE40_PRE -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_POS (16U) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_LEN (12U) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE40_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE40_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE40_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE40_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE40_PRE_POS)) - -/* 0x814 : BDM_6 */ -#define DSP2_MIDDLE2_BDM_6_OFFSET (0x814) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE DSP2_MIDDLE2_NR_PROFILE01_PRE -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE01_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE01_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE01_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE01_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE01_PRE_POS)) - -/* 0x818 : BDM_7 */ -#define DSP2_MIDDLE2_BDM_7_OFFSET (0x818) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE DSP2_MIDDLE2_NR_PROFILE11_PRE -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE11_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE11_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE11_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE11_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE11_PRE_POS)) - -/* 0x81C : BDM_8 */ -#define DSP2_MIDDLE2_BDM_8_OFFSET (0x81C) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE DSP2_MIDDLE2_NR_PROFILE21_PRE -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE21_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE21_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE21_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE21_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE21_PRE_POS)) - -/* 0x820 : BDM_9 */ -#define DSP2_MIDDLE2_BDM_9_OFFSET (0x820) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE DSP2_MIDDLE2_NR_PROFILE31_PRE -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE31_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE31_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE31_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE31_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE31_PRE_POS)) - -/* 0x824 : BDM_10 */ -#define DSP2_MIDDLE2_BDM_10_OFFSET (0x824) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE DSP2_MIDDLE2_NR_PROFILE41_PRE -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE41_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE41_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE41_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE41_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE41_PRE_POS)) - -/* 0x828 : BDM_11 */ -#define DSP2_MIDDLE2_BDM_11_OFFSET (0x828) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE DSP2_MIDDLE2_NR_PROFILE51_PRE -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_POS (0U) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_LEN (17U) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_MSK (((1U << DSP2_MIDDLE2_NR_PROFILE51_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE51_PRE_POS) -#define DSP2_MIDDLE2_NR_PROFILE51_PRE_UMSK (~(((1U << DSP2_MIDDLE2_NR_PROFILE51_PRE_LEN) - 1) << DSP2_MIDDLE2_NR_PROFILE51_PRE_POS)) - -/* 0x82C : BDM_12 */ -#define DSP2_MIDDLE2_BDM_12_OFFSET (0x82C) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE DSP2_MIDDLE2_LUMA_G_W1_PRE -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W1_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W1_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W1_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE DSP2_MIDDLE2_LUMA_G_W0_PRE -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W0_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W0_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W0_PRE_POS)) - -/* 0x830 : BDM_13 */ -#define DSP2_MIDDLE2_BDM_13_OFFSET (0x830) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE DSP2_MIDDLE2_LUMA_G_W3_PRE -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W3_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W3_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W3_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE DSP2_MIDDLE2_LUMA_G_W2_PRE -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W2_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W2_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W2_PRE_POS)) - -/* 0x834 : BDM_14 */ -#define DSP2_MIDDLE2_BDM_14_OFFSET (0x834) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE DSP2_MIDDLE2_LUMA_G_W5_PRE -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W5_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W5_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W5_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE DSP2_MIDDLE2_LUMA_G_W4_PRE -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W4_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W4_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W4_PRE_POS)) - -/* 0x838 : BDM_15 */ -#define DSP2_MIDDLE2_BDM_15_OFFSET (0x838) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE DSP2_MIDDLE2_LUMA_G_W7_PRE -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W7_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W7_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W7_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE DSP2_MIDDLE2_LUMA_G_W6_PRE -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W6_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W6_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W6_PRE_POS)) - -/* 0x83C : BDM_16 */ -#define DSP2_MIDDLE2_BDM_16_OFFSET (0x83C) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE DSP2_MIDDLE2_LUMA_G_W9_PRE -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W9_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W9_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W9_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE DSP2_MIDDLE2_LUMA_G_W8_PRE -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W8_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W8_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W8_PRE_POS)) - -/* 0x840 : BDM_17 */ -#define DSP2_MIDDLE2_BDM_17_OFFSET (0x840) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE DSP2_MIDDLE2_LUMA_G_W11_PRE -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W11_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W11_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W11_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE DSP2_MIDDLE2_LUMA_G_W10_PRE -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W10_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W10_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W10_PRE_POS)) - -/* 0x844 : BDM_18 */ -#define DSP2_MIDDLE2_BDM_18_OFFSET (0x844) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE DSP2_MIDDLE2_LUMA_G_W13_PRE -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W13_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W13_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W13_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE DSP2_MIDDLE2_LUMA_G_W12_PRE -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W12_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W12_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W12_PRE_POS)) - -/* 0x848 : BDM_19 */ -#define DSP2_MIDDLE2_BDM_19_OFFSET (0x848) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE DSP2_MIDDLE2_LUMA_G_W15_PRE -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W15_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W15_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W15_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE DSP2_MIDDLE2_LUMA_G_W14_PRE -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W14_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W14_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W14_PRE_POS)) - -/* 0x84C : BDM_20 */ -#define DSP2_MIDDLE2_BDM_20_OFFSET (0x84C) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE DSP2_MIDDLE2_LUMA_G_W17_PRE -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W17_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W17_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W17_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE DSP2_MIDDLE2_LUMA_G_W16_PRE -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W16_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W16_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W16_PRE_POS)) - -/* 0x850 : BDM_21 */ -#define DSP2_MIDDLE2_BDM_21_OFFSET (0x850) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE DSP2_MIDDLE2_LUMA_G_W19_PRE -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W19_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W19_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W19_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE DSP2_MIDDLE2_LUMA_G_W18_PRE -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W18_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W18_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W18_PRE_POS)) - -/* 0x854 : BDM_22 */ -#define DSP2_MIDDLE2_BDM_22_OFFSET (0x854) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE DSP2_MIDDLE2_LUMA_G_W21_PRE -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W21_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W21_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W21_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE DSP2_MIDDLE2_LUMA_G_W20_PRE -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W20_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W20_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W20_PRE_POS)) - -/* 0x858 : BDM_23 */ -#define DSP2_MIDDLE2_BDM_23_OFFSET (0x858) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE DSP2_MIDDLE2_LUMA_G_W23_PRE -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W23_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W23_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W23_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE DSP2_MIDDLE2_LUMA_G_W22_PRE -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W22_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W22_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W22_PRE_POS)) - -/* 0x85C : BDM_24 */ -#define DSP2_MIDDLE2_BDM_24_OFFSET (0x85C) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE DSP2_MIDDLE2_LUMA_G_W25_PRE -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W25_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W25_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W25_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE DSP2_MIDDLE2_LUMA_G_W24_PRE -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W24_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W24_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W24_PRE_POS)) - -/* 0x860 : BDM_25 */ -#define DSP2_MIDDLE2_BDM_25_OFFSET (0x860) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE DSP2_MIDDLE2_LUMA_G_W27_PRE -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W27_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W27_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W27_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE DSP2_MIDDLE2_LUMA_G_W26_PRE -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W26_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W26_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W26_PRE_POS)) - -/* 0x864 : BDM_26 */ -#define DSP2_MIDDLE2_BDM_26_OFFSET (0x864) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE DSP2_MIDDLE2_LUMA_G_W29_PRE -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W29_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W29_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W29_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE DSP2_MIDDLE2_LUMA_G_W28_PRE -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W28_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W28_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W28_PRE_POS)) - -/* 0x868 : BDM_27 */ -#define DSP2_MIDDLE2_BDM_27_OFFSET (0x868) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE DSP2_MIDDLE2_LUMA_G_W31_PRE -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W31_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W31_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W31_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE DSP2_MIDDLE2_LUMA_G_W30_PRE -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_G_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W30_PRE_POS) -#define DSP2_MIDDLE2_LUMA_G_W30_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_G_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_G_W30_PRE_POS)) - -/* 0x870 : BDM_28 */ -#define DSP2_MIDDLE2_BDM_28_OFFSET (0x870) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE DSP2_MIDDLE2_LUMA_BR_W1_PRE -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W1_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W1_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W1_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W1_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE DSP2_MIDDLE2_LUMA_BR_W0_PRE -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W0_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W0_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W0_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W0_PRE_POS)) - -/* 0x874 : BDM_29 */ -#define DSP2_MIDDLE2_BDM_29_OFFSET (0x874) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE DSP2_MIDDLE2_LUMA_BR_W3_PRE -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W3_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W3_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W3_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W3_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE DSP2_MIDDLE2_LUMA_BR_W2_PRE -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W2_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W2_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W2_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W2_PRE_POS)) - -/* 0x878 : BDM_30 */ -#define DSP2_MIDDLE2_BDM_30_OFFSET (0x878) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE DSP2_MIDDLE2_LUMA_BR_W5_PRE -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W5_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W5_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W5_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W5_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE DSP2_MIDDLE2_LUMA_BR_W4_PRE -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W4_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W4_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W4_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W4_PRE_POS)) - -/* 0x87C : BDM_31 */ -#define DSP2_MIDDLE2_BDM_31_OFFSET (0x87C) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE DSP2_MIDDLE2_LUMA_BR_W7_PRE -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W7_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W7_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W7_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W7_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE DSP2_MIDDLE2_LUMA_BR_W6_PRE -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W6_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W6_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W6_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W6_PRE_POS)) - -/* 0x880 : BDM_32 */ -#define DSP2_MIDDLE2_BDM_32_OFFSET (0x880) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE DSP2_MIDDLE2_LUMA_BR_W9_PRE -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W9_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W9_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W9_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W9_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE DSP2_MIDDLE2_LUMA_BR_W8_PRE -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W8_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W8_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W8_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W8_PRE_POS)) - -/* 0x884 : BDM_33 */ -#define DSP2_MIDDLE2_BDM_33_OFFSET (0x884) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE DSP2_MIDDLE2_LUMA_BR_W11_PRE -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W11_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W11_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W11_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W11_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE DSP2_MIDDLE2_LUMA_BR_W10_PRE -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W10_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W10_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W10_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W10_PRE_POS)) - -/* 0x888 : BDM_34 */ -#define DSP2_MIDDLE2_BDM_34_OFFSET (0x888) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE DSP2_MIDDLE2_LUMA_BR_W13_PRE -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W13_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W13_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W13_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W13_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE DSP2_MIDDLE2_LUMA_BR_W12_PRE -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W12_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W12_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W12_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W12_PRE_POS)) - -/* 0x88C : BDM_35 */ -#define DSP2_MIDDLE2_BDM_35_OFFSET (0x88C) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE DSP2_MIDDLE2_LUMA_BR_W15_PRE -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W15_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W15_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W15_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W15_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE DSP2_MIDDLE2_LUMA_BR_W14_PRE -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W14_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W14_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W14_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W14_PRE_POS)) - -/* 0x890 : BDM_36 */ -#define DSP2_MIDDLE2_BDM_36_OFFSET (0x890) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE DSP2_MIDDLE2_LUMA_BR_W17_PRE -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W17_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W17_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W17_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W17_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE DSP2_MIDDLE2_LUMA_BR_W16_PRE -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W16_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W16_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W16_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W16_PRE_POS)) - -/* 0x894 : BDM_37 */ -#define DSP2_MIDDLE2_BDM_37_OFFSET (0x894) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE DSP2_MIDDLE2_LUMA_BR_W19_PRE -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W19_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W19_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W19_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W19_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE DSP2_MIDDLE2_LUMA_BR_W18_PRE -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W18_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W18_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W18_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W18_PRE_POS)) - -/* 0x898 : BDM_38 */ -#define DSP2_MIDDLE2_BDM_38_OFFSET (0x898) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE DSP2_MIDDLE2_LUMA_BR_W21_PRE -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W21_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W21_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W21_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W21_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE DSP2_MIDDLE2_LUMA_BR_W20_PRE -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W20_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W20_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W20_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W20_PRE_POS)) - -/* 0x89C : BDM_39 */ -#define DSP2_MIDDLE2_BDM_39_OFFSET (0x89C) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE DSP2_MIDDLE2_LUMA_BR_W23_PRE -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W23_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W23_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W23_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W23_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE DSP2_MIDDLE2_LUMA_BR_W22_PRE -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W22_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W22_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W22_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W22_PRE_POS)) - -/* 0x8A0 : BDM_40 */ -#define DSP2_MIDDLE2_BDM_40_OFFSET (0x8A0) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE DSP2_MIDDLE2_LUMA_BR_W25_PRE -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W25_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W25_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W25_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W25_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE DSP2_MIDDLE2_LUMA_BR_W24_PRE -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W24_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W24_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W24_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W24_PRE_POS)) - -/* 0x8A4 : BDM_41 */ -#define DSP2_MIDDLE2_BDM_41_OFFSET (0x8A4) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE DSP2_MIDDLE2_LUMA_BR_W27_PRE -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W27_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W27_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W27_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W27_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE DSP2_MIDDLE2_LUMA_BR_W26_PRE -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W26_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W26_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W26_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W26_PRE_POS)) - -/* 0x8A8 : BDM_42 */ -#define DSP2_MIDDLE2_BDM_42_OFFSET (0x8A8) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE DSP2_MIDDLE2_LUMA_BR_W29_PRE -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W29_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W29_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W29_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W29_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE DSP2_MIDDLE2_LUMA_BR_W28_PRE -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W28_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W28_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W28_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W28_PRE_POS)) - -/* 0x8AC : BDM_43 */ -#define DSP2_MIDDLE2_BDM_43_OFFSET (0x8AC) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE DSP2_MIDDLE2_LUMA_BR_W31_PRE -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_POS (0U) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W31_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W31_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W31_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W31_PRE_POS)) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE DSP2_MIDDLE2_LUMA_BR_W30_PRE -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_POS (16U) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_LEN (9U) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_MSK (((1U << DSP2_MIDDLE2_LUMA_BR_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W30_PRE_POS) -#define DSP2_MIDDLE2_LUMA_BR_W30_PRE_UMSK (~(((1U << DSP2_MIDDLE2_LUMA_BR_W30_PRE_LEN) - 1) << DSP2_MIDDLE2_LUMA_BR_W30_PRE_POS)) - -/* 0x8B0 : BDM_44 */ -#define DSP2_MIDDLE2_BDM_44_OFFSET (0x8B0) -#define DSP2_MIDDLE2_G_COREW_PRE DSP2_MIDDLE2_G_COREW_PRE -#define DSP2_MIDDLE2_G_COREW_PRE_POS (0U) -#define DSP2_MIDDLE2_G_COREW_PRE_LEN (8U) -#define DSP2_MIDDLE2_G_COREW_PRE_MSK (((1U << DSP2_MIDDLE2_G_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_G_COREW_PRE_POS) -#define DSP2_MIDDLE2_G_COREW_PRE_UMSK (~(((1U << DSP2_MIDDLE2_G_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_G_COREW_PRE_POS)) -#define DSP2_MIDDLE2_BR_COREW_PRE DSP2_MIDDLE2_BR_COREW_PRE -#define DSP2_MIDDLE2_BR_COREW_PRE_POS (8U) -#define DSP2_MIDDLE2_BR_COREW_PRE_LEN (8U) -#define DSP2_MIDDLE2_BR_COREW_PRE_MSK (((1U << DSP2_MIDDLE2_BR_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_BR_COREW_PRE_POS) -#define DSP2_MIDDLE2_BR_COREW_PRE_UMSK (~(((1U << DSP2_MIDDLE2_BR_COREW_PRE_LEN) - 1) << DSP2_MIDDLE2_BR_COREW_PRE_POS)) - -struct dsp2_middle2_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[2048]; - - /* 0x800 : BDM_1 */ - union { - struct - { - uint32_t bdm_eb_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t gw_thr_pre : 5; /* [12: 8], r/w, 0x5 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t g_scal_factor_pre : 9; /* [24:16], r/w, 0x40 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_1; - - /* 0x804 : BDM_2 */ - union { - struct - { - uint32_t r_scal_factor_pre : 9; /* [ 8: 0], r/w, 0x40 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t b_scal_factor_pre : 9; /* [24:16], r/w, 0x40 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_2; - - /* 0x808 : BDM_3 */ - union { - struct - { - uint32_t nr_profile10_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t nr_profile00_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_3; - - /* 0x80C : BDM_4 */ - union { - struct - { - uint32_t nr_profile30_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t nr_profile20_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_4; - - /* 0x810 : BDM_5 */ - union { - struct - { - uint32_t nr_profile50_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t nr_profile40_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_5; - - /* 0x814 : BDM_6 */ - union { - struct - { - uint32_t nr_profile01_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_6; - - /* 0x818 : BDM_7 */ - union { - struct - { - uint32_t nr_profile11_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_7; - - /* 0x81C : BDM_8 */ - union { - struct - { - uint32_t nr_profile21_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_8; - - /* 0x820 : BDM_9 */ - union { - struct - { - uint32_t nr_profile31_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_9; - - /* 0x824 : BDM_10 */ - union { - struct - { - uint32_t nr_profile41_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_10; - - /* 0x828 : BDM_11 */ - union { - struct - { - uint32_t nr_profile51_pre : 17; /* [16: 0], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_11; - - /* 0x82C : BDM_12 */ - union { - struct - { - uint32_t luma_g_w1_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w0_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_12; - - /* 0x830 : BDM_13 */ - union { - struct - { - uint32_t luma_g_w3_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w2_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_13; - - /* 0x834 : BDM_14 */ - union { - struct - { - uint32_t luma_g_w5_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w4_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_14; - - /* 0x838 : BDM_15 */ - union { - struct - { - uint32_t luma_g_w7_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w6_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_15; - - /* 0x83C : BDM_16 */ - union { - struct - { - uint32_t luma_g_w9_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w8_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_16; - - /* 0x840 : BDM_17 */ - union { - struct - { - uint32_t luma_g_w11_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w10_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_17; - - /* 0x844 : BDM_18 */ - union { - struct - { - uint32_t luma_g_w13_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w12_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_18; - - /* 0x848 : BDM_19 */ - union { - struct - { - uint32_t luma_g_w15_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w14_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_19; - - /* 0x84C : BDM_20 */ - union { - struct - { - uint32_t luma_g_w17_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w16_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_20; - - /* 0x850 : BDM_21 */ - union { - struct - { - uint32_t luma_g_w19_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w18_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_21; - - /* 0x854 : BDM_22 */ - union { - struct - { - uint32_t luma_g_w21_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w20_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_22; - - /* 0x858 : BDM_23 */ - union { - struct - { - uint32_t luma_g_w23_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w22_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_23; - - /* 0x85C : BDM_24 */ - union { - struct - { - uint32_t luma_g_w25_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w24_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_24; - - /* 0x860 : BDM_25 */ - union { - struct - { - uint32_t luma_g_w27_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w26_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_25; - - /* 0x864 : BDM_26 */ - union { - struct - { - uint32_t luma_g_w29_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w28_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_26; - - /* 0x868 : BDM_27 */ - union { - struct - { - uint32_t luma_g_w31_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_g_w30_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_27; - - /* 0x86c reserved */ - uint8_t RESERVED0x86c[4]; - - /* 0x870 : BDM_28 */ - union { - struct - { - uint32_t luma_br_w1_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w0_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_28; - - /* 0x874 : BDM_29 */ - union { - struct - { - uint32_t luma_br_w3_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w2_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_29; - - /* 0x878 : BDM_30 */ - union { - struct - { - uint32_t luma_br_w5_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w4_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_30; - - /* 0x87C : BDM_31 */ - union { - struct - { - uint32_t luma_br_w7_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w6_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_31; - - /* 0x880 : BDM_32 */ - union { - struct - { - uint32_t luma_br_w9_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w8_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_32; - - /* 0x884 : BDM_33 */ - union { - struct - { - uint32_t luma_br_w11_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w10_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_33; - - /* 0x888 : BDM_34 */ - union { - struct - { - uint32_t luma_br_w13_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w12_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_34; - - /* 0x88C : BDM_35 */ - union { - struct - { - uint32_t luma_br_w15_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w14_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_35; - - /* 0x890 : BDM_36 */ - union { - struct - { - uint32_t luma_br_w17_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w16_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_36; - - /* 0x894 : BDM_37 */ - union { - struct - { - uint32_t luma_br_w19_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w18_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_37; - - /* 0x898 : BDM_38 */ - union { - struct - { - uint32_t luma_br_w21_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w20_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_38; - - /* 0x89C : BDM_39 */ - union { - struct - { - uint32_t luma_br_w23_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w22_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_39; - - /* 0x8A0 : BDM_40 */ - union { - struct - { - uint32_t luma_br_w25_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w24_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_40; - - /* 0x8A4 : BDM_41 */ - union { - struct - { - uint32_t luma_br_w27_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w26_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_41; - - /* 0x8A8 : BDM_42 */ - union { - struct - { - uint32_t luma_br_w29_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w28_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_42; - - /* 0x8AC : BDM_43 */ - union { - struct - { - uint32_t luma_br_w31_pre : 9; /* [ 8: 0], r/w, 0x80 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t luma_br_w30_pre : 9; /* [24:16], r/w, 0x80 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_43; - - /* 0x8B0 : BDM_44 */ - union { - struct - { - uint32_t g_corew_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t br_corew_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } BDM_44; -}; - -typedef volatile struct dsp2_middle2_reg dsp2_middle2_reg_t; - -#endif /* __DSP2_MIDDLE2_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle3_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle3_reg.h deleted file mode 100644 index 147fee7bb7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle3_reg.h +++ /dev/null @@ -1,928 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle3_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE3_REG_H__ -#define __DSP2_MIDDLE3_REG_H__ - -#include "bl808.h" - -/* 0x500 : awb2_sta_xaxis */ -#define DSP2_MIDDLE3_AWB2_STA_XAXIS_OFFSET (0x500) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE DSP2_MIDDLE3_AWB2_X_MIN_PRE -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_X_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE DSP2_MIDDLE3_AWB2_X_MAX_PRE -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MAX_PRE_POS) -#define DSP2_MIDDLE3_AWB2_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_X_MAX_PRE_POS)) - -/* 0x504 : awb2_sta_yaxis */ -#define DSP2_MIDDLE3_AWB2_STA_YAXIS_OFFSET (0x504) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE DSP2_MIDDLE3_AWB2_Y_MIN_PRE -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_Y_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE DSP2_MIDDLE3_AWB2_Y_MAX_PRE -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_POS) -#define DSP2_MIDDLE3_AWB2_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_Y_MAX_PRE_POS)) - -/* 0x508 : awb2_sta_pixel_num */ -#define DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM_OFFSET (0x508) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_LEN (21U) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_POS) -#define DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE_POS)) - -/* 0x50C : awb2_sta_gain0 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN0_OFFSET (0x50C) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE_POS)) - -/* 0x510 : awb2_sta_gain1 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN1_OFFSET (0x510) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE DSP2_MIDDLE3_AWB2_RGAIN_PRE -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_RGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_RGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_RGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_RGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE_POS)) - -/* 0x514 : awb2_sta_gain2 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN2_OFFSET (0x514) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE DSP2_MIDDLE3_AWB2_BGAIN_PRE -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_BGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_BGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_BGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_BGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE DSP2_MIDDLE3_AWB2_GGAIN_PRE -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_LEN (16U) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_GGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_GGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GGAIN_PRE_POS)) - -/* 0x518 : awb2_sta_gain3 */ -#define DSP2_MIDDLE3_AWB2_STA_GAIN3_OFFSET (0x518) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE DSP2_MIDDLE3_AWB2_VGAIN_PRE -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_LEN (10U) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VGAIN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE DSP2_MIDDLE3_AWB2_UGAIN_PRE -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_LEN (10U) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UGAIN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UGAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UGAIN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UGAIN_PRE_POS)) - -/* 0x51C : awb2_sta_l0 */ -#define DSP2_MIDDLE3_AWB2_STA_L0_OFFSET (0x51C) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE DSP2_MIDDLE3_AWB2_YTH1_PRE -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE DSP2_MIDDLE3_AWB2_YTH2_PRE -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE DSP2_MIDDLE3_AWB2_YTH3_PRE -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH3_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE DSP2_MIDDLE3_AWB2_YTH4_PRE -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH4_PRE_POS)) - -/* 0x520 : awb2_sta_l1 */ -#define DSP2_MIDDLE3_AWB2_STA_L1_OFFSET (0x520) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE DSP2_MIDDLE3_AWB2_YTH0_PRE -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YTH0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YTH0_PRE_POS)) - -/* 0x524 : awb2_sta_l2 */ -#define DSP2_MIDDLE3_AWB2_STA_L2_OFFSET (0x524) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE DSP2_MIDDLE3_AWB2_YSLOPE4_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE_POS)) - -/* 0x528 : awb2_sta_l3 */ -#define DSP2_MIDDLE3_AWB2_STA_L3_OFFSET (0x528) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE DSP2_MIDDLE3_AWB2_YSLOPE2_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE DSP2_MIDDLE3_AWB2_YSLOPE3_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE3_PRE_POS)) - -/* 0x52C : awb2_sta_l4 */ -#define DSP2_MIDDLE3_AWB2_STA_L4_OFFSET (0x52C) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE DSP2_MIDDLE3_AWB2_YSLOPE0_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE DSP2_MIDDLE3_AWB2_YSLOPE1_PRE -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_LEN (9U) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_YSLOPE1_PRE_POS)) - -/* 0x530 : awb2_sta_c0 */ -#define DSP2_MIDDLE3_AWB2_STA_C0_OFFSET (0x530) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE DSP2_MIDDLE3_AWB2_UREG4_PRE -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE DSP2_MIDDLE3_AWB2_UREG5_PRE -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE DSP2_MIDDLE3_AWB2_UREG6_PRE -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE DSP2_MIDDLE3_AWB2_UREG7_PRE -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG7_PRE_POS)) - -/* 0x534 : awb2_sta_c1 */ -#define DSP2_MIDDLE3_AWB2_STA_C1_OFFSET (0x534) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE DSP2_MIDDLE3_AWB2_UREG0_PRE -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE DSP2_MIDDLE3_AWB2_UREG1_PRE -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE DSP2_MIDDLE3_AWB2_UREG2_PRE -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE DSP2_MIDDLE3_AWB2_UREG3_PRE -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_UREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_UREG3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_UREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_UREG3_PRE_POS)) - -/* 0x538 : awb2_sta_c2 */ -#define DSP2_MIDDLE3_AWB2_STA_C2_OFFSET (0x538) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE DSP2_MIDDLE3_AWB2_VREG4_PRE -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE DSP2_MIDDLE3_AWB2_VREG5_PRE -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE DSP2_MIDDLE3_AWB2_VREG6_PRE -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE DSP2_MIDDLE3_AWB2_VREG7_PRE -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG7_PRE_POS)) - -/* 0x53C : awb2_sta_c3 */ -#define DSP2_MIDDLE3_AWB2_STA_C3_OFFSET (0x53C) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE DSP2_MIDDLE3_AWB2_VREG0_PRE -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE DSP2_MIDDLE3_AWB2_VREG1_PRE -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE DSP2_MIDDLE3_AWB2_VREG2_PRE -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE DSP2_MIDDLE3_AWB2_VREG3_PRE -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_VREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_VREG3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_VREG3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_VREG3_PRE_POS)) - -/* 0x540 : awb2_sta_c4 */ -#define DSP2_MIDDLE3_AWB2_STA_C4_OFFSET (0x540) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE DSP2_MIDDLE3_AWB2_CTH4_PRE -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE DSP2_MIDDLE3_AWB2_CTH5_PRE -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE DSP2_MIDDLE3_AWB2_CTH6_PRE -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE DSP2_MIDDLE3_AWB2_CTH7_PRE -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH7_PRE_POS)) - -/* 0x544 : awb2_sta_c5 */ -#define DSP2_MIDDLE3_AWB2_STA_C5_OFFSET (0x544) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE DSP2_MIDDLE3_AWB2_CTH0_PRE -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE DSP2_MIDDLE3_AWB2_CTH1_PRE -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE DSP2_MIDDLE3_AWB2_CTH2_PRE -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE DSP2_MIDDLE3_AWB2_CTH3_PRE -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_LEN (6U) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CTH3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CTH3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CTH3_PRE_POS)) - -/* 0x548 : awb2_sta_c6 */ -#define DSP2_MIDDLE3_AWB2_STA_C6_OFFSET (0x548) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE DSP2_MIDDLE3_AWB2_CSLOPE4_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE4_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE DSP2_MIDDLE3_AWB2_CSLOPE5_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE5_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE DSP2_MIDDLE3_AWB2_CSLOPE6_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE6_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE DSP2_MIDDLE3_AWB2_CSLOPE7_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE7_PRE_POS)) - -/* 0x54C : awb2_sta_c7 */ -#define DSP2_MIDDLE3_AWB2_STA_C7_OFFSET (0x54C) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE DSP2_MIDDLE3_AWB2_CSLOPE0_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE0_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE DSP2_MIDDLE3_AWB2_CSLOPE1_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_POS (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE1_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE DSP2_MIDDLE3_AWB2_CSLOPE2_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_POS (16U) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE2_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE DSP2_MIDDLE3_AWB2_CSLOPE3_PRE -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_POS (24U) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_LEN (8U) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_POS) -#define DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_CSLOPE3_PRE_POS)) - -/* 0x550 : awb2_sta_r0 */ -#define DSP2_MIDDLE3_AWB2_STA_R0_OFFSET (0x550) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R DSP2_MIDDLE3_AWB2_G_AVG0_R -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_G_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG0_R_POS) -#define DSP2_MIDDLE3_AWB2_G_AVG0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_G_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG0_R_POS)) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R DSP2_MIDDLE3_AWB2_R_AVG0_R -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_R_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG0_R_POS) -#define DSP2_MIDDLE3_AWB2_R_AVG0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_R_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG0_R_POS)) - -/* 0x554 : awb2_sta_r1 */ -#define DSP2_MIDDLE3_AWB2_STA_R1_OFFSET (0x554) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_LEN (15U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R_POS)) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R DSP2_MIDDLE3_AWB2_B_AVG0_R -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_B_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG0_R_POS) -#define DSP2_MIDDLE3_AWB2_B_AVG0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_B_AVG0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG0_R_POS)) - -/* 0x558 : awb2_sta_r2 */ -#define DSP2_MIDDLE3_AWB2_STA_R2_OFFSET (0x558) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R DSP2_MIDDLE3_AWB2_G_AVG1_R -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_G_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG1_R_POS) -#define DSP2_MIDDLE3_AWB2_G_AVG1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_G_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_G_AVG1_R_POS)) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R DSP2_MIDDLE3_AWB2_R_AVG1_R -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_R_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG1_R_POS) -#define DSP2_MIDDLE3_AWB2_R_AVG1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_R_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_R_AVG1_R_POS)) - -/* 0x55C : awb2_sta_r3 */ -#define DSP2_MIDDLE3_AWB2_STA_R3_OFFSET (0x55C) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_LEN (15U) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R_POS)) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R DSP2_MIDDLE3_AWB2_B_AVG1_R -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_LEN (12U) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_B_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG1_R_POS) -#define DSP2_MIDDLE3_AWB2_B_AVG1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_B_AVG1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_B_AVG1_R_POS)) - -/* 0x560 : awb2_sta_r4 */ -#define DSP2_MIDDLE3_AWB2_STA_R4_OFFSET (0x560) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH0_R_POS)) - -/* 0x564 : awb2_sta_r5 */ -#define DSP2_MIDDLE3_AWB2_STA_R5_OFFSET (0x564) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R DSP2_MIDDLE3_AWB2_WHITER_SUML1_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML1_R_POS)) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R DSP2_MIDDLE3_AWB2_WHITER_SUML0_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUML0_R_POS)) - -/* 0x568 : awb2_sta_r6 */ -#define DSP2_MIDDLE3_AWB2_STA_R6_OFFSET (0x568) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITER_SUMH1_R_POS)) - -/* 0x56C : awb2_sta_r7 */ -#define DSP2_MIDDLE3_AWB2_STA_R7_OFFSET (0x56C) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH0_R_POS)) - -/* 0x570 : awb2_sta_r8 */ -#define DSP2_MIDDLE3_AWB2_STA_R8_OFFSET (0x570) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R_POS)) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R_POS)) - -/* 0x574 : awb2_sta_r9 */ -#define DSP2_MIDDLE3_AWB2_STA_R9_OFFSET (0x574) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEG_SUMH1_R_POS)) - -/* 0x578 : awb2_sta_ra */ -#define DSP2_MIDDLE3_AWB2_STA_RA_OFFSET (0x578) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH0_R_POS)) - -/* 0x57C : awb2_sta_rb */ -#define DSP2_MIDDLE3_AWB2_STA_RB_OFFSET (0x57C) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R_POS)) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_POS (16U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_LEN (9U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R_POS)) - -/* 0x580 : awb2_sta_rc */ -#define DSP2_MIDDLE3_AWB2_STA_RC_OFFSET (0x580) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_POS (0U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_LEN (32U) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_MSK (((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_POS) -#define DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_WHITEB_SUMH1_R_POS)) - -/* 0x584 : awb2_sta_int */ -#define DSP2_MIDDLE3_AWB2_STA_INT_OFFSET (0x584) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE DSP2_MIDDLE3_AWB2_GAIN_EN_PRE -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_POS (0U) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_LEN (1U) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_GAIN_EN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE DSP2_MIDDLE3_AWB2_STAT_EN_PRE -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_POS (1U) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_LEN (1U) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_MSK (((1U << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_POS) -#define DSP2_MIDDLE3_AWB2_STAT_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE3_AWB2_STAT_EN_PRE_POS)) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R DSP2_MIDDLE3_AWB2_BUF_IDX_R -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_POS (2U) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE3_AWB2_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_BUF_IDX_R_POS) -#define DSP2_MIDDLE3_AWB2_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_BUF_IDX_R_POS)) -#define DSP2_MIDDLE3_AWB2_W_CNT_R DSP2_MIDDLE3_AWB2_W_CNT_R -#define DSP2_MIDDLE3_AWB2_W_CNT_R_POS (8U) -#define DSP2_MIDDLE3_AWB2_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE3_AWB2_W_CNT_R_MSK (((1U << DSP2_MIDDLE3_AWB2_W_CNT_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_W_CNT_R_POS) -#define DSP2_MIDDLE3_AWB2_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE3_AWB2_W_CNT_R_LEN) - 1) << DSP2_MIDDLE3_AWB2_W_CNT_R_POS)) - -struct dsp2_middle3_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1280]; - - /* 0x500 : awb2_sta_xaxis */ - union { - struct { - uint32_t awb2_x_min_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb2_x_max_pre : 11; /* [26:16], r/w, 0x77f */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_xaxis; - - /* 0x504 : awb2_sta_yaxis */ - union { - struct { - uint32_t awb2_y_min_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb2_y_max_pre : 11; /* [26:16], r/w, 0x437 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_yaxis; - - /* 0x508 : awb2_sta_pixel_num */ - union { - struct { - uint32_t awb2_pixel_num_pre : 21; /* [20: 0], r/w, 0x1fa400 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_pixel_num; - - /* 0x50C : awb2_sta_gain0 */ - union { - struct { - uint32_t awb2_stat_ggain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb2_stat_rgain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb2_sta_gain0; - - /* 0x510 : awb2_sta_gain1 */ - union { - struct { - uint32_t awb2_rgain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb2_stat_bgain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb2_sta_gain1; - - /* 0x514 : awb2_sta_gain2 */ - union { - struct { - uint32_t awb2_bgain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb2_ggain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb2_sta_gain2; - - /* 0x518 : awb2_sta_gain3 */ - union { - struct { - uint32_t awb2_vgain_pre : 10; /* [ 9: 0], r/w, 0x100 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t awb2_ugain_pre : 10; /* [25:16], r/w, 0x100 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_gain3; - - /* 0x51C : awb2_sta_l0 */ - union { - struct { - uint32_t awb2_yth1_pre : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t awb2_yth2_pre : 8; /* [15: 8], r/w, 0x30 */ - uint32_t awb2_yth3_pre : 8; /* [23:16], r/w, 0xd0 */ - uint32_t awb2_yth4_pre : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } awb2_sta_l0; - - /* 0x520 : awb2_sta_l1 */ - union { - struct { - uint32_t awb2_yweight2_pre : 8; /* [ 7: 0], r/w, 0xff */ - uint32_t awb2_yweight3_pre : 8; /* [15: 8], r/w, 0xff */ - uint32_t awb2_yweight4_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_yth0_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l1; - - /* 0x524 : awb2_sta_l2 */ - union { - struct { - uint32_t awb2_yslope4_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_yweight0_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_yweight1_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l2; - - /* 0x528 : awb2_sta_l3 */ - union { - struct { - uint32_t awb2_yslope2_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_yslope3_pre : 9; /* [24:16], r/w, 0x1e0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l3; - - /* 0x52C : awb2_sta_l4 */ - union { - struct { - uint32_t awb2_yslope0_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_yslope1_pre : 9; /* [24:16], r/w, 0x20 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_l4; - - /* 0x530 : awb2_sta_c0 */ - union { - struct { - uint32_t awb2_ureg4_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_ureg5_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_ureg6_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_ureg7_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c0; - - /* 0x534 : awb2_sta_c1 */ - union { - struct { - uint32_t awb2_ureg0_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_ureg1_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_ureg2_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_ureg3_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c1; - - /* 0x538 : awb2_sta_c2 */ - union { - struct { - uint32_t awb2_vreg4_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_vreg5_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_vreg6_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_vreg7_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c2; - - /* 0x53C : awb2_sta_c3 */ - union { - struct { - uint32_t awb2_vreg0_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb2_vreg1_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb2_vreg2_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t awb2_vreg3_pre : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c3; - - /* 0x540 : awb2_sta_c4 */ - union { - struct { - uint32_t awb2_cth4_pre : 6; /* [ 5: 0], r/w, 0x10 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t awb2_cth5_pre : 6; /* [13: 8], r/w, 0x10 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t awb2_cth6_pre : 6; /* [21:16], r/w, 0x10 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t awb2_cth7_pre : 6; /* [29:24], r/w, 0x10 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c4; - - /* 0x544 : awb2_sta_c5 */ - union { - struct { - uint32_t awb2_cth0_pre : 6; /* [ 5: 0], r/w, 0x10 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t awb2_cth1_pre : 6; /* [13: 8], r/w, 0x10 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t awb2_cth2_pre : 6; /* [21:16], r/w, 0x10 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t awb2_cth3_pre : 6; /* [29:24], r/w, 0x10 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_c5; - - /* 0x548 : awb2_sta_c6 */ - union { - struct { - uint32_t awb2_cslope4_pre : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t awb2_cslope5_pre : 8; /* [15: 8], r/w, 0x40 */ - uint32_t awb2_cslope6_pre : 8; /* [23:16], r/w, 0x40 */ - uint32_t awb2_cslope7_pre : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } awb2_sta_c6; - - /* 0x54C : awb2_sta_c7 */ - union { - struct { - uint32_t awb2_cslope0_pre : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t awb2_cslope1_pre : 8; /* [15: 8], r/w, 0x40 */ - uint32_t awb2_cslope2_pre : 8; /* [23:16], r/w, 0x40 */ - uint32_t awb2_cslope3_pre : 8; /* [31:24], r/w, 0x40 */ - } BF; - uint32_t WORD; - } awb2_sta_c7; - - /* 0x550 : awb2_sta_r0 */ - union { - struct { - uint32_t awb2_g_avg0_r : 12; /* [11: 0], r, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb2_r_avg0_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r0; - - /* 0x554 : awb2_sta_r1 */ - union { - struct { - uint32_t awb2_white_ratio0_r : 15; /* [14: 0], r, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t awb2_b_avg0_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r1; - - /* 0x558 : awb2_sta_r2 */ - union { - struct { - uint32_t awb2_g_avg1_r : 12; /* [11: 0], r, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb2_r_avg1_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r2; - - /* 0x55C : awb2_sta_r3 */ - union { - struct { - uint32_t awb2_white_ratio1_r : 15; /* [14: 0], r, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t awb2_b_avg1_r : 12; /* [27:16], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r3; - - /* 0x560 : awb2_sta_r4 */ - union { - struct { - uint32_t awb2_whiter_sumh0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r4; - - /* 0x564 : awb2_sta_r5 */ - union { - struct { - uint32_t awb2_whiter_suml1_r : 9; /* [ 8: 0], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_whiter_suml0_r : 9; /* [24:16], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r5; - - /* 0x568 : awb2_sta_r6 */ - union { - struct { - uint32_t awb2_whiter_sumh1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r6; - - /* 0x56C : awb2_sta_r7 */ - union { - struct { - uint32_t awb2_whiteg_sumh0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r7; - - /* 0x570 : awb2_sta_r8 */ - union { - struct { - uint32_t awb2_whiteg_suml1_r : 9; /* [ 8: 0], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_whiteg_suml0_r : 9; /* [24:16], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r8; - - /* 0x574 : awb2_sta_r9 */ - union { - struct { - uint32_t awb2_whiteg_sumh1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_r9; - - /* 0x578 : awb2_sta_ra */ - union { - struct { - uint32_t awb2_whiteb_sumh0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_ra; - - /* 0x57C : awb2_sta_rb */ - union { - struct { - uint32_t awb2_whiteb_suml1_r : 9; /* [ 8: 0], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t awb2_whiteb_suml0_r : 9; /* [24:16], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_rb; - - /* 0x580 : awb2_sta_rc */ - union { - struct { - uint32_t awb2_whiteb_sumh1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_rc; - - /* 0x584 : awb2_sta_int */ - union { - struct { - uint32_t awb2_gain_en_pre : 1; /* [ 0], r/w, 0x0 */ - uint32_t awb2_stat_en_pre : 1; /* [ 1], r/w, 0x0 */ - uint32_t awb2_buf_idx_r : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t awb2_w_cnt_r : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb2_sta_int; -}; - -typedef volatile struct dsp2_middle3_reg dsp2_middle3_reg_t; - -#endif /* __DSP2_MIDDLE3_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle4_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle4_reg.h deleted file mode 100644 index 21a7c189b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle4_reg.h +++ /dev/null @@ -1,167 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle4_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE4_REG_H__ -#define __DSP2_MIDDLE4_REG_H__ - -#include "bl808.h" - -/* 0x600 : bnr_config_0 */ -#define DSP2_MIDDLE4_BNR_CONFIG_0_OFFSET (0x600) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE DSP2_MIDDLE4_BNR_WEIGHT_PRE -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_POS (0U) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_LEN (7U) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_MSK (((1U << DSP2_MIDDLE4_BNR_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_WEIGHT_PRE_POS) -#define DSP2_MIDDLE4_BNR_WEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE4_BNR_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_WEIGHT_PRE_POS)) -#define DSP2_MIDDLE4_BNR_EN_PRE DSP2_MIDDLE4_BNR_EN_PRE -#define DSP2_MIDDLE4_BNR_EN_PRE_POS (7U) -#define DSP2_MIDDLE4_BNR_EN_PRE_LEN (1U) -#define DSP2_MIDDLE4_BNR_EN_PRE_MSK (((1U << DSP2_MIDDLE4_BNR_EN_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_EN_PRE_POS) -#define DSP2_MIDDLE4_BNR_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE4_BNR_EN_PRE_LEN) - 1) << DSP2_MIDDLE4_BNR_EN_PRE_POS)) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE DSP2_MIDDLE4_LPF_WEIGHT_PRE -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_POS (8U) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_LEN (5U) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_MSK (((1U << DSP2_MIDDLE4_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_LPF_WEIGHT_PRE_POS) -#define DSP2_MIDDLE4_LPF_WEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE4_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_LPF_WEIGHT_PRE_POS)) -#define DSP2_MIDDLE4_TH_BASE_B_PRE DSP2_MIDDLE4_TH_BASE_B_PRE -#define DSP2_MIDDLE4_TH_BASE_B_PRE_POS (16U) -#define DSP2_MIDDLE4_TH_BASE_B_PRE_LEN (10U) -#define DSP2_MIDDLE4_TH_BASE_B_PRE_MSK (((1U << DSP2_MIDDLE4_TH_BASE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_B_PRE_POS) -#define DSP2_MIDDLE4_TH_BASE_B_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_BASE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_B_PRE_POS)) - -/* 0x604 : bnr_config_1 */ -#define DSP2_MIDDLE4_BNR_CONFIG_1_OFFSET (0x604) -#define DSP2_MIDDLE4_TH_BASE_R_PRE DSP2_MIDDLE4_TH_BASE_R_PRE -#define DSP2_MIDDLE4_TH_BASE_R_PRE_POS (0U) -#define DSP2_MIDDLE4_TH_BASE_R_PRE_LEN (10U) -#define DSP2_MIDDLE4_TH_BASE_R_PRE_MSK (((1U << DSP2_MIDDLE4_TH_BASE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_R_PRE_POS) -#define DSP2_MIDDLE4_TH_BASE_R_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_BASE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_R_PRE_POS)) -#define DSP2_MIDDLE4_TH_BASE_G_PRE DSP2_MIDDLE4_TH_BASE_G_PRE -#define DSP2_MIDDLE4_TH_BASE_G_PRE_POS (16U) -#define DSP2_MIDDLE4_TH_BASE_G_PRE_LEN (10U) -#define DSP2_MIDDLE4_TH_BASE_G_PRE_MSK (((1U << DSP2_MIDDLE4_TH_BASE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_G_PRE_POS) -#define DSP2_MIDDLE4_TH_BASE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_BASE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_BASE_G_PRE_POS)) - -/* 0x608 : bnr_config_2 */ -#define DSP2_MIDDLE4_BNR_CONFIG_2_OFFSET (0x608) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE DSP2_MIDDLE4_TH_SLOPE_R_PRE -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_POS (0U) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_LEN (8U) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_MSK (((1U << DSP2_MIDDLE4_TH_SLOPE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_R_PRE_POS) -#define DSP2_MIDDLE4_TH_SLOPE_R_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_SLOPE_R_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_R_PRE_POS)) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE DSP2_MIDDLE4_TH_SLOPE_G_PRE -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_POS (8U) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_LEN (8U) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_MSK (((1U << DSP2_MIDDLE4_TH_SLOPE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_G_PRE_POS) -#define DSP2_MIDDLE4_TH_SLOPE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_SLOPE_G_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_G_PRE_POS)) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE DSP2_MIDDLE4_TH_SLOPE_B_PRE -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_POS (16U) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_LEN (8U) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_MSK (((1U << DSP2_MIDDLE4_TH_SLOPE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_B_PRE_POS) -#define DSP2_MIDDLE4_TH_SLOPE_B_PRE_UMSK (~(((1U << DSP2_MIDDLE4_TH_SLOPE_B_PRE_LEN) - 1) << DSP2_MIDDLE4_TH_SLOPE_B_PRE_POS)) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE DSP2_MIDDLE4_SLOPE_GAIN_PRE -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_POS (24U) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_LEN (6U) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_MSK (((1U << DSP2_MIDDLE4_SLOPE_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE4_SLOPE_GAIN_PRE_POS) -#define DSP2_MIDDLE4_SLOPE_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE4_SLOPE_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE4_SLOPE_GAIN_PRE_POS)) - -/* 0x60C : bnr_config_3 */ -#define DSP2_MIDDLE4_BNR_CONFIG_3_OFFSET (0x60C) -#define DSP2_MIDDLE4_FB_LEVEL_PRE DSP2_MIDDLE4_FB_LEVEL_PRE -#define DSP2_MIDDLE4_FB_LEVEL_PRE_POS (0U) -#define DSP2_MIDDLE4_FB_LEVEL_PRE_LEN (3U) -#define DSP2_MIDDLE4_FB_LEVEL_PRE_MSK (((1U << DSP2_MIDDLE4_FB_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LEVEL_PRE_POS) -#define DSP2_MIDDLE4_FB_LEVEL_PRE_UMSK (~(((1U << DSP2_MIDDLE4_FB_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LEVEL_PRE_POS)) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_POS (8U) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_LEN (5U) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_MSK (((1U << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_POS) -#define DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE_POS)) - -struct dsp2_middle4_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1536]; - - /* 0x600 : bnr_config_0 */ - union { - struct { - uint32_t bnr_weight_pre : 7; /* [ 6: 0], r/w, 0x0 */ - uint32_t bnr_en_pre : 1; /* [ 7], r/w, 0x0 */ - uint32_t lpf_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t th_base_b_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_0; - - /* 0x604 : bnr_config_1 */ - union { - struct { - uint32_t th_base_r_pre : 10; /* [ 9: 0], r/w, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t th_base_g_pre : 10; /* [25:16], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_1; - - /* 0x608 : bnr_config_2 */ - union { - struct { - uint32_t th_slope_r_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t th_slope_g_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t th_slope_b_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t slope_gain_pre : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_2; - - /* 0x60C : bnr_config_3 */ - union { - struct { - uint32_t fb_level_pre : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t fb_lpf_weight_pre : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bnr_config_3; -}; - -typedef volatile struct dsp2_middle4_reg dsp2_middle4_reg_t; - -#endif /* __DSP2_MIDDLE4_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle5_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle5_reg.h deleted file mode 100644 index df2fc9add1..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle5_reg.h +++ /dev/null @@ -1,2589 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle5_reg.h - * @version V1.2 - * @date 2021-07-15 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE5_REG_H__ -#define __DSP2_MIDDLE5_REG_H__ - -#include "bl808.h" - -/* 0x000 : awb3_config_0 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_0_OFFSET (0x000) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MAX_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_X_MIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE DSP2_MIDDLE5_AWB3_STAT_EN_PRE -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_POS (31U) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_EN_PRE_POS)) - -/* 0x004 : awb3_config_1 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_1_OFFSET (0x004) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MAX_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_STAT_Y_MIN_PRE_POS)) - -/* 0x008 : awb3_config_2 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_2_OFFSET (0x008) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_OFST_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_OFST_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_POS (31U) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_POS) -#define DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_DIVISOR_PRE_POS)) - -/* 0x00C : awb3_config_3 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_3_OFFSET (0x00C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_MULT_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_MULT_PRE_POS)) - -/* 0x010 : awb3_config_4 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_4_OFFSET (0x010) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_LEN (9U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_POS) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MAX_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_POS (9U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_LEN (9U) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_RATIO_SUM_MIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_POS (18U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_GAIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_POS (26U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_EN_PRE_POS)) - -/* 0x014 : awb3_config_5 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_5_OFFSET (0x014) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_00_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_01_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_02_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_03_PRE_POS)) - -/* 0x018 : awb3_config_6 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_6_OFFSET (0x018) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_04_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_05_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_06_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_07_PRE_POS)) - -/* 0x01C : awb3_config_7 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_7_OFFSET (0x01C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_08_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_10_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_11_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_12_PRE_POS)) - -/* 0x020 : awb3_config_8 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_8_OFFSET (0x020) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_13_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_14_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_15_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_16_PRE_POS)) - -/* 0x024 : awb3_config_9 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_9_OFFSET (0x024) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_17_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_18_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_20_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_21_PRE_POS)) - -/* 0x028 : awb3_config_10 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_10_OFFSET (0x028) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_22_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_23_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_24_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_25_PRE_POS)) - -/* 0x02C : awb3_config_11 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_11_OFFSET (0x02C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_26_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_27_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_28_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_30_PRE_POS)) - -/* 0x030 : awb3_config_12 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_12_OFFSET (0x030) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_31_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_32_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_33_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_34_PRE_POS)) - -/* 0x034 : awb3_config_13 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_13_OFFSET (0x034) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_35_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_36_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_37_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_38_PRE_POS)) - -/* 0x038 : awb3_config_14 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_14_OFFSET (0x038) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_40_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_41_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_42_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_43_PRE_POS)) - -/* 0x03C : awb3_config_15 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_15_OFFSET (0x03C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_44_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_45_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_46_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_47_PRE_POS)) - -/* 0x040 : awb3_config_16 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_16_OFFSET (0x040) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_48_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_50_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_51_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_52_PRE_POS)) - -/* 0x044 : awb3_config_17 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_17_OFFSET (0x044) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_53_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_54_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_55_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_56_PRE_POS)) - -/* 0x048 : awb3_config_18 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_18_OFFSET (0x048) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_57_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_58_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_60_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_61_PRE_POS)) - -/* 0x04C : awb3_config_19 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_19_OFFSET (0x04C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_62_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_63_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_64_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_65_PRE_POS)) - -/* 0x050 : awb3_config_20 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_20_OFFSET (0x050) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_66_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_67_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_68_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_70_PRE_POS)) - -/* 0x054 : awb3_config_21 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_21_OFFSET (0x054) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_71_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_72_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_73_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_74_PRE_POS)) - -/* 0x058 : awb3_config_22 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_22_OFFSET (0x058) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_75_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_76_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_77_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_78_PRE_POS)) - -/* 0x05C : awb3_config_23 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_23_OFFSET (0x05C) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_80_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_81_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_82_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_83_PRE_POS)) - -/* 0x060 : awb3_config_24 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_24_OFFSET (0x060) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_84_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_85_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_86_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_87_PRE_POS)) - -/* 0x064 : awb3_config_25 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_25_OFFSET (0x064) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_RATIO_88_PRE_POS)) - -/* 0x068 : awb3_config_26 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_26_OFFSET (0x068) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_POS) -#define DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_R_COEFF_PRE_POS)) - -/* 0x06C : awb3_config_27 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_27_OFFSET (0x06C) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_POS) -#define DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_G_COEFF_PRE_POS)) - -/* 0x070 : awb3_config_28 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_28_OFFSET (0x070) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_LEN (12U) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_POS) -#define DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_Y_B_COEFF_PRE_POS)) - -/* 0x074 : awb3_config_29 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_29_OFFSET (0x074) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_GAIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_EN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_POS (12U) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_USE_G_PRE_POS)) - -/* 0x078 : awb3_config_30 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_30_OFFSET (0x078) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE DSP2_MIDDLE5_AWB3_WT_Y_00_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_00_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE DSP2_MIDDLE5_AWB3_WT_Y_01_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_01_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE DSP2_MIDDLE5_AWB3_WT_Y_02_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_02_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE DSP2_MIDDLE5_AWB3_WT_Y_03_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_03_PRE_POS)) - -/* 0x07C : awb3_config_31 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_31_OFFSET (0x07C) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE DSP2_MIDDLE5_AWB3_WT_Y_04_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_04_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE DSP2_MIDDLE5_AWB3_WT_Y_05_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_05_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE DSP2_MIDDLE5_AWB3_WT_Y_06_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_06_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE DSP2_MIDDLE5_AWB3_WT_Y_07_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_07_PRE_POS)) - -/* 0x080 : awb3_config_32 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_32_OFFSET (0x080) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE DSP2_MIDDLE5_AWB3_WT_Y_08_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_08_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE DSP2_MIDDLE5_AWB3_WT_Y_10_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_10_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE DSP2_MIDDLE5_AWB3_WT_Y_11_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_11_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE DSP2_MIDDLE5_AWB3_WT_Y_12_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_12_PRE_POS)) - -/* 0x084 : awb3_config_33 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_33_OFFSET (0x084) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE DSP2_MIDDLE5_AWB3_WT_Y_13_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_13_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE DSP2_MIDDLE5_AWB3_WT_Y_14_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_14_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE DSP2_MIDDLE5_AWB3_WT_Y_15_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_15_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE DSP2_MIDDLE5_AWB3_WT_Y_16_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_16_PRE_POS)) - -/* 0x088 : awb3_config_34 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_34_OFFSET (0x088) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE DSP2_MIDDLE5_AWB3_WT_Y_17_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_17_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE DSP2_MIDDLE5_AWB3_WT_Y_18_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_18_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE DSP2_MIDDLE5_AWB3_WT_Y_20_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_20_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE DSP2_MIDDLE5_AWB3_WT_Y_21_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_21_PRE_POS)) - -/* 0x08C : awb3_config_35 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_35_OFFSET (0x08C) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE DSP2_MIDDLE5_AWB3_WT_Y_22_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_22_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE DSP2_MIDDLE5_AWB3_WT_Y_23_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_23_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE DSP2_MIDDLE5_AWB3_WT_Y_24_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_24_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE DSP2_MIDDLE5_AWB3_WT_Y_25_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_25_PRE_POS)) - -/* 0x090 : awb3_config_36 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_36_OFFSET (0x090) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE DSP2_MIDDLE5_AWB3_WT_Y_26_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_26_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE DSP2_MIDDLE5_AWB3_WT_Y_27_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_27_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE DSP2_MIDDLE5_AWB3_WT_Y_28_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_28_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE DSP2_MIDDLE5_AWB3_WT_Y_30_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_30_PRE_POS)) - -/* 0x094 : awb3_config_37 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_37_OFFSET (0x094) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE DSP2_MIDDLE5_AWB3_WT_Y_31_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_31_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE DSP2_MIDDLE5_AWB3_WT_Y_32_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_32_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE DSP2_MIDDLE5_AWB3_WT_Y_33_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_33_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE DSP2_MIDDLE5_AWB3_WT_Y_34_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_34_PRE_POS)) - -/* 0x098 : awb3_config_38 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_38_OFFSET (0x098) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE DSP2_MIDDLE5_AWB3_WT_Y_35_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_35_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE DSP2_MIDDLE5_AWB3_WT_Y_36_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_36_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE DSP2_MIDDLE5_AWB3_WT_Y_37_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_37_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE DSP2_MIDDLE5_AWB3_WT_Y_38_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_38_PRE_POS)) - -/* 0x09C : awb3_config_39 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_39_OFFSET (0x09C) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE DSP2_MIDDLE5_AWB3_WT_Y_40_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_40_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE DSP2_MIDDLE5_AWB3_WT_Y_41_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_41_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE DSP2_MIDDLE5_AWB3_WT_Y_42_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_42_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE DSP2_MIDDLE5_AWB3_WT_Y_43_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_43_PRE_POS)) - -/* 0x0A0 : awb3_config_40 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_40_OFFSET (0x0A0) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE DSP2_MIDDLE5_AWB3_WT_Y_44_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_44_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE DSP2_MIDDLE5_AWB3_WT_Y_45_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_45_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE DSP2_MIDDLE5_AWB3_WT_Y_46_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_46_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE DSP2_MIDDLE5_AWB3_WT_Y_47_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_47_PRE_POS)) - -/* 0x0A4 : awb3_config_41 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_41_OFFSET (0x0A4) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE DSP2_MIDDLE5_AWB3_WT_Y_48_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_48_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE DSP2_MIDDLE5_AWB3_WT_Y_50_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_50_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE DSP2_MIDDLE5_AWB3_WT_Y_51_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_51_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE DSP2_MIDDLE5_AWB3_WT_Y_52_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_52_PRE_POS)) - -/* 0x0A8 : awb3_config_42 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_42_OFFSET (0x0A8) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE DSP2_MIDDLE5_AWB3_WT_Y_53_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_53_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE DSP2_MIDDLE5_AWB3_WT_Y_54_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_54_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE DSP2_MIDDLE5_AWB3_WT_Y_55_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_55_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE DSP2_MIDDLE5_AWB3_WT_Y_56_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_56_PRE_POS)) - -/* 0x0AC : awb3_config_43 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_43_OFFSET (0x0AC) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE DSP2_MIDDLE5_AWB3_WT_Y_57_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_57_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE DSP2_MIDDLE5_AWB3_WT_Y_58_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_58_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE DSP2_MIDDLE5_AWB3_WT_Y_60_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_60_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE DSP2_MIDDLE5_AWB3_WT_Y_61_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_61_PRE_POS)) - -/* 0x0B0 : awb3_config_44 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_44_OFFSET (0x0B0) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE DSP2_MIDDLE5_AWB3_WT_Y_62_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_62_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE DSP2_MIDDLE5_AWB3_WT_Y_63_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_63_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE DSP2_MIDDLE5_AWB3_WT_Y_64_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_64_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE DSP2_MIDDLE5_AWB3_WT_Y_65_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_65_PRE_POS)) - -/* 0x0B4 : awb3_config_45 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_45_OFFSET (0x0B4) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE DSP2_MIDDLE5_AWB3_WT_Y_66_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_66_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE DSP2_MIDDLE5_AWB3_WT_Y_67_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_67_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE DSP2_MIDDLE5_AWB3_WT_Y_68_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_68_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE DSP2_MIDDLE5_AWB3_WT_Y_70_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_70_PRE_POS)) - -/* 0x0B8 : awb3_config_46 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_46_OFFSET (0x0B8) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE DSP2_MIDDLE5_AWB3_WT_Y_71_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_71_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE DSP2_MIDDLE5_AWB3_WT_Y_72_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_72_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE DSP2_MIDDLE5_AWB3_WT_Y_73_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_73_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE DSP2_MIDDLE5_AWB3_WT_Y_74_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_74_PRE_POS)) - -/* 0x0BC : awb3_config_47 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_47_OFFSET (0x0BC) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE DSP2_MIDDLE5_AWB3_WT_Y_75_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_75_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE DSP2_MIDDLE5_AWB3_WT_Y_76_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_76_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE DSP2_MIDDLE5_AWB3_WT_Y_77_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_77_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE DSP2_MIDDLE5_AWB3_WT_Y_78_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_78_PRE_POS)) - -/* 0x0C0 : awb3_config_48 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_48_OFFSET (0x0C0) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE DSP2_MIDDLE5_AWB3_WT_Y_80_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_80_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE DSP2_MIDDLE5_AWB3_WT_Y_81_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_81_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE DSP2_MIDDLE5_AWB3_WT_Y_82_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_82_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE DSP2_MIDDLE5_AWB3_WT_Y_83_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_83_PRE_POS)) - -/* 0x0C4 : awb3_config_49 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_49_OFFSET (0x0C4) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE DSP2_MIDDLE5_AWB3_WT_Y_84_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_84_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE DSP2_MIDDLE5_AWB3_WT_Y_85_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_POS (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_85_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE DSP2_MIDDLE5_AWB3_WT_Y_86_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_POS (16U) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_86_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE DSP2_MIDDLE5_AWB3_WT_Y_87_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_POS (24U) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_87_PRE_POS)) - -/* 0x0C8 : awb3_config_50 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_50_OFFSET (0x0C8) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE DSP2_MIDDLE5_AWB3_WT_Y_88_PRE -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_LEN (8U) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_POS) -#define DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_Y_88_PRE_POS)) - -/* 0x0CC : awb3_config_51 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_51_OFFSET (0x0CC) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE DSP2_MIDDLE5_AWB3_BIN_MODE_PRE -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_LEN (2U) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_MODE_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_POS (2U) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_LEN (20U) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_PIXEL_CLIP_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_POS (22U) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_CLIP_EN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_POS (23U) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_LEN (3U) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_RATIO_LEVEL_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_POS (26U) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_LEN (3U) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_POS) -#define DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_BIN_Y_LEVEL_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_POS (29U) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_POS) -#define DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_HIST_Y_USE_G_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_POS (30U) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_LEN (1U) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_POS) -#define DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_COUNT_ZERO_WT_PRE_POS)) - -/* 0x0D0 : awb3_config_52 */ -#define DSP2_MIDDLE5_AWB3_CONFIG_52_OFFSET (0x0D0) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE DSP2_MIDDLE5_AWB3_INK_GAIN_PRE -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_LEN (4U) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_POS) -#define DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_GAIN_PRE_POS)) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE DSP2_MIDDLE5_AWB3_INK_TYPE_PRE -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_POS (4U) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_LEN (2U) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_MSK (((1U << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_POS) -#define DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_LEN) - 1) << DSP2_MIDDLE5_AWB3_INK_TYPE_PRE_POS)) - -/* 0x0D4 : awb3_sta_0 */ -#define DSP2_MIDDLE5_AWB3_STA_0_OFFSET (0x0D4) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R DSP2_MIDDLE5_AWB3_R_SUM0_R -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM0_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM0_R_POS)) - -/* 0x0D8 : awb3_sta_1 */ -#define DSP2_MIDDLE5_AWB3_STA_1_OFFSET (0x0D8) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R DSP2_MIDDLE5_AWB3_G_SUM0_R -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM0_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM0_R_POS)) - -/* 0x0DC : awb3_sta_2 */ -#define DSP2_MIDDLE5_AWB3_STA_2_OFFSET (0x0DC) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R DSP2_MIDDLE5_AWB3_B_SUM0_R -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM0_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM0_R_POS)) - -/* 0x0E0 : awb3_sta_3 */ -#define DSP2_MIDDLE5_AWB3_STA_3_OFFSET (0x0E0) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX0_R_POS)) - -/* 0x0E4 : awb3_sta_4 */ -#define DSP2_MIDDLE5_AWB3_STA_4_OFFSET (0x0E4) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX0_R_POS)) - -/* 0x0E8 : awb3_sta_5 */ -#define DSP2_MIDDLE5_AWB3_STA_5_OFFSET (0x0E8) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX0_R_POS)) - -/* 0x0EC : awb3_sta_6 */ -#define DSP2_MIDDLE5_AWB3_STA_6_OFFSET (0x0EC) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX0_R_POS)) - -/* 0x0F0 : awb3_sta_7 */ -#define DSP2_MIDDLE5_AWB3_STA_7_OFFSET (0x0F0) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0U_R_POS)) - -/* 0x0F4 : awb3_sta_8 */ -#define DSP2_MIDDLE5_AWB3_STA_8_OFFSET (0x0F4) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y0L_R_POS)) - -/* 0x0F8 : awb3_sta_9 */ -#define DSP2_MIDDLE5_AWB3_STA_9_OFFSET (0x0F8) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0U_R_POS)) - -/* 0x0FC : awb3_sta_10 */ -#define DSP2_MIDDLE5_AWB3_STA_10_OFFSET (0x0FC) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y0L_R_POS)) - -/* 0x100 : awb3_sta_11 */ -#define DSP2_MIDDLE5_AWB3_STA_11_OFFSET (0x100) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y0_R_POS)) - -/* 0x104 : awb3_sta_12 */ -#define DSP2_MIDDLE5_AWB3_STA_12_OFFSET (0x104) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y0_R_POS)) - -/* 0x108 : awb3_sta_13 */ -#define DSP2_MIDDLE5_AWB3_STA_13_OFFSET (0x108) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0U_R_POS)) - -/* 0x10C : awb3_sta_14 */ -#define DSP2_MIDDLE5_AWB3_STA_14_OFFSET (0x10C) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST0L_R_POS)) - -/* 0x110 : awb3_sta_15 */ -#define DSP2_MIDDLE5_AWB3_STA_15_OFFSET (0x110) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0U_R_POS)) - -/* 0x114 : awb3_sta_16 */ -#define DSP2_MIDDLE5_AWB3_STA_16_OFFSET (0x114) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST0L_R_POS)) - -/* 0x118 : awb3_sta_17 */ -#define DSP2_MIDDLE5_AWB3_STA_17_OFFSET (0x118) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R DSP2_MIDDLE5_AWB3_WT_HIST0_R -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST0_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST0_R_POS)) - -/* 0x11C : awb3_sta_18 */ -#define DSP2_MIDDLE5_AWB3_STA_18_OFFSET (0x11C) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST0_R_POS)) - -/* 0x120 : awb3_sta_19 */ -#define DSP2_MIDDLE5_AWB3_STA_19_OFFSET (0x120) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0U_R_POS)) - -/* 0x124 : awb3_sta_20 */ -#define DSP2_MIDDLE5_AWB3_STA_20_OFFSET (0x124) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP0L_R_POS)) - -/* 0x128 : awb3_sta_21 */ -#define DSP2_MIDDLE5_AWB3_STA_21_OFFSET (0x128) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0U_R_POS)) - -/* 0x12C : awb3_sta_22 */ -#define DSP2_MIDDLE5_AWB3_STA_22_OFFSET (0x12C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP0L_R_POS)) - -/* 0x130 : awb3_sta_23 */ -#define DSP2_MIDDLE5_AWB3_STA_23_OFFSET (0x130) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP0_R_POS)) - -/* 0x134 : awb3_sta_24 */ -#define DSP2_MIDDLE5_AWB3_STA_24_OFFSET (0x134) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP0_R_POS)) - -/* 0x138 : awb3_sta_25 */ -#define DSP2_MIDDLE5_AWB3_STA_25_OFFSET (0x138) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R DSP2_MIDDLE5_AWB3_R_SUM1_R -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM1_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM1_R_POS)) - -/* 0x13C : awb3_sta_26 */ -#define DSP2_MIDDLE5_AWB3_STA_26_OFFSET (0x13C) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R DSP2_MIDDLE5_AWB3_G_SUM1_R -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM1_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM1_R_POS)) - -/* 0x140 : awb3_sta_27 */ -#define DSP2_MIDDLE5_AWB3_STA_27_OFFSET (0x140) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R DSP2_MIDDLE5_AWB3_B_SUM1_R -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM1_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM1_R_POS)) - -/* 0x144 : awb3_sta_28 */ -#define DSP2_MIDDLE5_AWB3_STA_28_OFFSET (0x144) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_SUM_HEX1_R_POS)) - -/* 0x148 : awb3_sta_29 */ -#define DSP2_MIDDLE5_AWB3_STA_29_OFFSET (0x148) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_G_SUM_HEX1_R_POS)) - -/* 0x14C : awb3_sta_30 */ -#define DSP2_MIDDLE5_AWB3_STA_30_OFFSET (0x14C) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_SUM_HEX1_R_POS)) - -/* 0x150 : awb3_sta_31 */ -#define DSP2_MIDDLE5_AWB3_STA_31_OFFSET (0x150) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX1_R_POS)) - -/* 0x154 : awb3_sta_32 */ -#define DSP2_MIDDLE5_AWB3_STA_32_OFFSET (0x154) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1U_R_POS)) - -/* 0x158 : awb3_sta_33 */ -#define DSP2_MIDDLE5_AWB3_STA_33_OFFSET (0x158) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HEX_Y1L_R_POS)) - -/* 0x15C : awb3_sta_34 */ -#define DSP2_MIDDLE5_AWB3_STA_34_OFFSET (0x15C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1U_R_POS)) - -/* 0x160 : awb3_sta_35 */ -#define DSP2_MIDDLE5_AWB3_STA_35_OFFSET (0x160) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HEX_Y1L_R_POS)) - -/* 0x164 : awb3_sta_36 */ -#define DSP2_MIDDLE5_AWB3_STA_36_OFFSET (0x164) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HEX_Y1_R_POS)) - -/* 0x168 : awb3_sta_37 */ -#define DSP2_MIDDLE5_AWB3_STA_37_OFFSET (0x168) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HEX_Y1_R_POS)) - -/* 0x16C : awb3_sta_38 */ -#define DSP2_MIDDLE5_AWB3_STA_38_OFFSET (0x16C) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1U_R_POS)) - -/* 0x170 : awb3_sta_39 */ -#define DSP2_MIDDLE5_AWB3_STA_39_OFFSET (0x170) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST1L_R_POS)) - -/* 0x174 : awb3_sta_40 */ -#define DSP2_MIDDLE5_AWB3_STA_40_OFFSET (0x174) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1U_R_POS)) - -/* 0x178 : awb3_sta_41 */ -#define DSP2_MIDDLE5_AWB3_STA_41_OFFSET (0x178) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST1L_R_POS)) - -/* 0x17C : awb3_sta_42 */ -#define DSP2_MIDDLE5_AWB3_STA_42_OFFSET (0x17C) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R DSP2_MIDDLE5_AWB3_WT_HIST1_R -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST1_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST1_R_POS)) - -/* 0x180 : awb3_sta_43 */ -#define DSP2_MIDDLE5_AWB3_STA_43_OFFSET (0x180) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST1_R_POS)) - -/* 0x184 : awb3_sta_44 */ -#define DSP2_MIDDLE5_AWB3_STA_44_OFFSET (0x184) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_LEN (8U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1U_R_POS)) - -/* 0x188 : awb3_sta_45 */ -#define DSP2_MIDDLE5_AWB3_STA_45_OFFSET (0x188) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_POS) -#define DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_R_RATIO_HIST_CLIP1L_R_POS)) - -/* 0x18C : awb3_sta_46 */ -#define DSP2_MIDDLE5_AWB3_STA_46_OFFSET (0x18C) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_LEN (17U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1U_R_POS)) - -/* 0x190 : awb3_sta_47 */ -#define DSP2_MIDDLE5_AWB3_STA_47_OFFSET (0x190) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_LEN (32U) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_MSK (((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_POS) -#define DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_B_RATIO_HIST_CLIP1L_R_POS)) - -/* 0x194 : awb3_sta_48 */ -#define DSP2_MIDDLE5_AWB3_STA_48_OFFSET (0x194) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_LEN (28U) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_POS) -#define DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_WT_HIST_CLIP1_R_POS)) - -/* 0x198 : awb3_sta_49 */ -#define DSP2_MIDDLE5_AWB3_STA_49_OFFSET (0x198) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_LEN (20U) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_MSK (((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_POS) -#define DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_PIXEL_HIST_CLIP1_R_POS)) - -/* 0x19C : awb3_status_0 */ -#define DSP2_MIDDLE5_AWB3_STATUS_0_OFFSET (0x19C) -#define DSP2_MIDDLE5_AWB3_W_CNT_R DSP2_MIDDLE5_AWB3_W_CNT_R -#define DSP2_MIDDLE5_AWB3_W_CNT_R_POS (0U) -#define DSP2_MIDDLE5_AWB3_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE5_AWB3_W_CNT_R_MSK (((1U << DSP2_MIDDLE5_AWB3_W_CNT_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_W_CNT_R_POS) -#define DSP2_MIDDLE5_AWB3_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_W_CNT_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_W_CNT_R_POS)) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R DSP2_MIDDLE5_AWB3_BUF_IDX_R -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_POS (8U) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE5_AWB3_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_BUF_IDX_R_POS) -#define DSP2_MIDDLE5_AWB3_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE5_AWB3_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE5_AWB3_BUF_IDX_R_POS)) - -struct dsp2_middle5_reg { - /* 0x000 : awb3_config_0 */ - union { - struct { - uint32_t awb3_stat_x_max_pre : 11; /* [10: 0], r/w, 0x77f */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb3_stat_x_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ - uint32_t awb3_stat_en_pre : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_0; - - /* 0x004 : awb3_config_1 */ - union { - struct { - uint32_t awb3_stat_y_max_pre : 11; /* [10: 0], r/w, 0x437 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb3_stat_y_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_1; - - /* 0x008 : awb3_config_2 */ - union { - struct { - uint32_t awb3_b_ratio_ofst_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb3_r_ratio_ofst_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_30 : 3; /* [30:28], rsvd, 0x0 */ - uint32_t awb3_g_divisor_pre : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_2; - - /* 0x00C : awb3_config_3 */ - union { - struct { - uint32_t awb3_b_ratio_mult_pre : 12; /* [11: 0], r/w, 0x100 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb3_r_ratio_mult_pre : 12; /* [27:16], r/w, 0x100 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_3; - - /* 0x010 : awb3_config_4 */ - union { - struct { - uint32_t awb3_ratio_sum_max_pre : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t awb3_ratio_sum_min_pre : 9; /* [17: 9], r/w, 0x0 */ - uint32_t awb3_wt_ratio_gain_pre : 8; /* [25:18], r/w, 0x0 */ - uint32_t awb3_wt_ratio_en_pre : 1; /* [ 26], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_4; - - /* 0x014 : awb3_config_5 */ - union { - struct { - uint32_t awb3_wt_ratio_00_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_01_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_02_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_03_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_5; - - /* 0x018 : awb3_config_6 */ - union { - struct { - uint32_t awb3_wt_ratio_04_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_05_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_06_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_07_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_6; - - /* 0x01C : awb3_config_7 */ - union { - struct { - uint32_t awb3_wt_ratio_08_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_10_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_11_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_12_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_7; - - /* 0x020 : awb3_config_8 */ - union { - struct { - uint32_t awb3_wt_ratio_13_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_14_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_15_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_16_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_8; - - /* 0x024 : awb3_config_9 */ - union { - struct { - uint32_t awb3_wt_ratio_17_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_18_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_20_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_21_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_9; - - /* 0x028 : awb3_config_10 */ - union { - struct { - uint32_t awb3_wt_ratio_22_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_23_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_24_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_25_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_10; - - /* 0x02C : awb3_config_11 */ - union { - struct { - uint32_t awb3_wt_ratio_26_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_27_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_28_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_30_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_11; - - /* 0x030 : awb3_config_12 */ - union { - struct { - uint32_t awb3_wt_ratio_31_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_32_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_33_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_34_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_12; - - /* 0x034 : awb3_config_13 */ - union { - struct { - uint32_t awb3_wt_ratio_35_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_36_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_37_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_38_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_13; - - /* 0x038 : awb3_config_14 */ - union { - struct { - uint32_t awb3_wt_ratio_40_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_41_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_42_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_43_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_14; - - /* 0x03C : awb3_config_15 */ - union { - struct { - uint32_t awb3_wt_ratio_44_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_45_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_46_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_47_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_15; - - /* 0x040 : awb3_config_16 */ - union { - struct { - uint32_t awb3_wt_ratio_48_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_50_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_51_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_52_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_16; - - /* 0x044 : awb3_config_17 */ - union { - struct { - uint32_t awb3_wt_ratio_53_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_54_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_55_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_56_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_17; - - /* 0x048 : awb3_config_18 */ - union { - struct { - uint32_t awb3_wt_ratio_57_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_58_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_60_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_61_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_18; - - /* 0x04C : awb3_config_19 */ - union { - struct { - uint32_t awb3_wt_ratio_62_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_63_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_64_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_65_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_19; - - /* 0x050 : awb3_config_20 */ - union { - struct { - uint32_t awb3_wt_ratio_66_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_67_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_68_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_70_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_20; - - /* 0x054 : awb3_config_21 */ - union { - struct { - uint32_t awb3_wt_ratio_71_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_72_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_73_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_74_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_21; - - /* 0x058 : awb3_config_22 */ - union { - struct { - uint32_t awb3_wt_ratio_75_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_76_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_77_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_78_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_22; - - /* 0x05C : awb3_config_23 */ - union { - struct { - uint32_t awb3_wt_ratio_80_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_81_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_82_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_83_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_23; - - /* 0x060 : awb3_config_24 */ - union { - struct { - uint32_t awb3_wt_ratio_84_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_ratio_85_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_ratio_86_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_ratio_87_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_24; - - /* 0x064 : awb3_config_25 */ - union { - struct { - uint32_t awb3_wt_ratio_88_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_25; - - /* 0x068 : awb3_config_26 */ - union { - struct { - uint32_t awb3_y_r_coeff_pre : 12; /* [11: 0], r/w, 0x4d */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_26; - - /* 0x06C : awb3_config_27 */ - union { - struct { - uint32_t awb3_y_g_coeff_pre : 12; /* [11: 0], r/w, 0x96 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_27; - - /* 0x070 : awb3_config_28 */ - union { - struct { - uint32_t awb3_y_b_coeff_pre : 12; /* [11: 0], r/w, 0x1d */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_28; - - /* 0x074 : awb3_config_29 */ - union { - struct { - uint32_t awb3_wt_y_gain_pre : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t awb3_wt_y_en_pre : 1; /* [ 8], r/w, 0x1 */ - uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ - uint32_t awb3_wt_y_use_g_pre : 1; /* [ 12], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_29; - - /* 0x078 : awb3_config_30 */ - union { - struct { - uint32_t awb3_wt_y_00_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_01_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_02_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_03_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_30; - - /* 0x07C : awb3_config_31 */ - union { - struct { - uint32_t awb3_wt_y_04_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_05_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_06_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_07_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_31; - - /* 0x080 : awb3_config_32 */ - union { - struct { - uint32_t awb3_wt_y_08_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_10_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_11_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_12_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_32; - - /* 0x084 : awb3_config_33 */ - union { - struct { - uint32_t awb3_wt_y_13_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_14_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_15_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_16_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_33; - - /* 0x088 : awb3_config_34 */ - union { - struct { - uint32_t awb3_wt_y_17_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_18_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_20_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_21_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_34; - - /* 0x08C : awb3_config_35 */ - union { - struct { - uint32_t awb3_wt_y_22_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_23_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_24_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_25_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_35; - - /* 0x090 : awb3_config_36 */ - union { - struct { - uint32_t awb3_wt_y_26_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_27_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_28_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_30_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_36; - - /* 0x094 : awb3_config_37 */ - union { - struct { - uint32_t awb3_wt_y_31_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_32_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_33_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_34_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_37; - - /* 0x098 : awb3_config_38 */ - union { - struct { - uint32_t awb3_wt_y_35_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_36_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_37_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_38_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_38; - - /* 0x09C : awb3_config_39 */ - union { - struct { - uint32_t awb3_wt_y_40_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_41_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_42_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_43_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_39; - - /* 0x0A0 : awb3_config_40 */ - union { - struct { - uint32_t awb3_wt_y_44_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_45_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_46_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_47_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_40; - - /* 0x0A4 : awb3_config_41 */ - union { - struct { - uint32_t awb3_wt_y_48_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_50_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_51_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_52_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_41; - - /* 0x0A8 : awb3_config_42 */ - union { - struct { - uint32_t awb3_wt_y_53_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_54_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_55_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_56_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_42; - - /* 0x0AC : awb3_config_43 */ - union { - struct { - uint32_t awb3_wt_y_57_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_58_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_60_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_61_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_43; - - /* 0x0B0 : awb3_config_44 */ - union { - struct { - uint32_t awb3_wt_y_62_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_63_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_64_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_65_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_44; - - /* 0x0B4 : awb3_config_45 */ - union { - struct { - uint32_t awb3_wt_y_66_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_67_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_68_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_70_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_45; - - /* 0x0B8 : awb3_config_46 */ - union { - struct { - uint32_t awb3_wt_y_71_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_72_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_73_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_74_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_46; - - /* 0x0BC : awb3_config_47 */ - union { - struct { - uint32_t awb3_wt_y_75_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_76_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_77_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_78_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_47; - - /* 0x0C0 : awb3_config_48 */ - union { - struct { - uint32_t awb3_wt_y_80_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_81_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_82_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_83_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_48; - - /* 0x0C4 : awb3_config_49 */ - union { - struct { - uint32_t awb3_wt_y_84_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t awb3_wt_y_85_pre : 8; /* [15: 8], r/w, 0x1 */ - uint32_t awb3_wt_y_86_pre : 8; /* [23:16], r/w, 0x1 */ - uint32_t awb3_wt_y_87_pre : 8; /* [31:24], r/w, 0x1 */ - } BF; - uint32_t WORD; - } awb3_config_49; - - /* 0x0C8 : awb3_config_50 */ - union { - struct { - uint32_t awb3_wt_y_88_pre : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_50; - - /* 0x0CC : awb3_config_51 */ - union { - struct { - uint32_t awb3_bin_mode_pre : 2; /* [ 1: 0], r/w, 0x3 */ - uint32_t awb3_bin_pixel_clip_pre : 20; /* [21: 2], r/w, 0xfd200 */ - uint32_t awb3_bin_clip_en_pre : 1; /* [ 22], r/w, 0x0 */ - uint32_t awb3_bin_ratio_level_pre : 3; /* [25:23], r/w, 0x3 */ - uint32_t awb3_bin_y_level_pre : 3; /* [28:26], r/w, 0x3 */ - uint32_t awb3_hist_y_use_g_pre : 1; /* [ 29], r/w, 0x0 */ - uint32_t awb3_count_zero_wt_pre : 1; /* [ 30], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_51; - - /* 0x0D0 : awb3_config_52 */ - union { - struct { - uint32_t awb3_ink_gain_pre : 4; /* [ 3: 0], r/w, 0x1 */ - uint32_t awb3_ink_type_pre : 2; /* [ 5: 4], r/w, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_config_52; - - /* 0x0D4 : awb3_sta_0 */ - union { - struct { - uint32_t awb3_r_sum0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_0; - - /* 0x0D8 : awb3_sta_1 */ - union { - struct { - uint32_t awb3_g_sum0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_1; - - /* 0x0DC : awb3_sta_2 */ - union { - struct { - uint32_t awb3_b_sum0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_2; - - /* 0x0E0 : awb3_sta_3 */ - union { - struct { - uint32_t awb3_r_sum_hex0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_3; - - /* 0x0E4 : awb3_sta_4 */ - union { - struct { - uint32_t awb3_g_sum_hex0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_4; - - /* 0x0E8 : awb3_sta_5 */ - union { - struct { - uint32_t awb3_b_sum_hex0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_5; - - /* 0x0EC : awb3_sta_6 */ - union { - struct { - uint32_t awb3_pixel_hex0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_6; - - /* 0x0F0 : awb3_sta_7 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_7; - - /* 0x0F4 : awb3_sta_8 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_8; - - /* 0x0F8 : awb3_sta_9 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_9; - - /* 0x0FC : awb3_sta_10 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_10; - - /* 0x100 : awb3_sta_11 */ - union { - struct { - uint32_t awb3_wt_hex_y0_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_11; - - /* 0x104 : awb3_sta_12 */ - union { - struct { - uint32_t awb3_pixel_hex_y0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_12; - - /* 0x108 : awb3_sta_13 */ - union { - struct { - uint32_t awb3_r_ratio_hist0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_13; - - /* 0x10C : awb3_sta_14 */ - union { - struct { - uint32_t awb3_r_ratio_hist0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_14; - - /* 0x110 : awb3_sta_15 */ - union { - struct { - uint32_t awb3_b_ratio_hist0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_15; - - /* 0x114 : awb3_sta_16 */ - union { - struct { - uint32_t awb3_b_ratio_hist0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_16; - - /* 0x118 : awb3_sta_17 */ - union { - struct { - uint32_t awb3_wt_hist0_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_17; - - /* 0x11C : awb3_sta_18 */ - union { - struct { - uint32_t awb3_pixel_hist0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_18; - - /* 0x120 : awb3_sta_19 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_19; - - /* 0x124 : awb3_sta_20 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_20; - - /* 0x128 : awb3_sta_21 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip0u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_21; - - /* 0x12C : awb3_sta_22 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip0l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_22; - - /* 0x130 : awb3_sta_23 */ - union { - struct { - uint32_t awb3_wt_hist_clip0_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_23; - - /* 0x134 : awb3_sta_24 */ - union { - struct { - uint32_t awb3_pixel_hist_clip0_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_24; - - /* 0x138 : awb3_sta_25 */ - union { - struct { - uint32_t awb3_r_sum1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_25; - - /* 0x13C : awb3_sta_26 */ - union { - struct { - uint32_t awb3_g_sum1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_26; - - /* 0x140 : awb3_sta_27 */ - union { - struct { - uint32_t awb3_b_sum1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_27; - - /* 0x144 : awb3_sta_28 */ - union { - struct { - uint32_t awb3_r_sum_hex1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_28; - - /* 0x148 : awb3_sta_29 */ - union { - struct { - uint32_t awb3_g_sum_hex1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_29; - - /* 0x14C : awb3_sta_30 */ - union { - struct { - uint32_t awb3_b_sum_hex1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_30; - - /* 0x150 : awb3_sta_31 */ - union { - struct { - uint32_t awb3_pixel_hex1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_31; - - /* 0x154 : awb3_sta_32 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_32; - - /* 0x158 : awb3_sta_33 */ - union { - struct { - uint32_t awb3_r_ratio_hex_y1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_33; - - /* 0x15C : awb3_sta_34 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_34; - - /* 0x160 : awb3_sta_35 */ - union { - struct { - uint32_t awb3_b_ratio_hex_y1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_35; - - /* 0x164 : awb3_sta_36 */ - union { - struct { - uint32_t awb3_wt_hex_y1_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_36; - - /* 0x168 : awb3_sta_37 */ - union { - struct { - uint32_t awb3_pixel_hex_y1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_37; - - /* 0x16C : awb3_sta_38 */ - union { - struct { - uint32_t awb3_r_ratio_hist1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_38; - - /* 0x170 : awb3_sta_39 */ - union { - struct { - uint32_t awb3_r_ratio_hist1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_39; - - /* 0x174 : awb3_sta_40 */ - union { - struct { - uint32_t awb3_b_ratio_hist1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_40; - - /* 0x178 : awb3_sta_41 */ - union { - struct { - uint32_t awb3_b_ratio_hist1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_41; - - /* 0x17C : awb3_sta_42 */ - union { - struct { - uint32_t awb3_wt_hist1_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_42; - - /* 0x180 : awb3_sta_43 */ - union { - struct { - uint32_t awb3_pixel_hist1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_43; - - /* 0x184 : awb3_sta_44 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip1u_r : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_44; - - /* 0x188 : awb3_sta_45 */ - union { - struct { - uint32_t awb3_r_ratio_hist_clip1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_45; - - /* 0x18C : awb3_sta_46 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip1u_r : 17; /* [16: 0], r, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_46; - - /* 0x190 : awb3_sta_47 */ - union { - struct { - uint32_t awb3_b_ratio_hist_clip1l_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_47; - - /* 0x194 : awb3_sta_48 */ - union { - struct { - uint32_t awb3_wt_hist_clip1_r : 28; /* [27: 0], r, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_48; - - /* 0x198 : awb3_sta_49 */ - union { - struct { - uint32_t awb3_pixel_hist_clip1_r : 20; /* [19: 0], r, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_sta_49; - - /* 0x19C : awb3_status_0 */ - union { - struct { - uint32_t awb3_w_cnt_r : 5; /* [ 4: 0], r, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t awb3_buf_idx_r : 1; /* [ 8], r, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb3_status_0; -}; - -typedef volatile struct dsp2_middle5_reg dsp2_middle5_reg_t; - -#endif /* __DSP2_MIDDLE5_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle_reg.h deleted file mode 100644 index c36d1c464f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_middle_reg.h +++ /dev/null @@ -1,1278 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_middle_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MIDDLE_REG_H__ -#define __DSP2_MIDDLE_REG_H__ - -#include "bl808.h" - -/* 0x224 : LSC_setting */ -#define DSP2_MIDDLE_LSC_SETTING_OFFSET (0x224) -#define DSP2_MIDDLE_LSC_ON_W DSP2_MIDDLE_LSC_ON_W -#define DSP2_MIDDLE_LSC_ON_W_POS (8U) -#define DSP2_MIDDLE_LSC_ON_W_LEN (1U) -#define DSP2_MIDDLE_LSC_ON_W_MSK (((1U << DSP2_MIDDLE_LSC_ON_W_LEN) - 1) << DSP2_MIDDLE_LSC_ON_W_POS) -#define DSP2_MIDDLE_LSC_ON_W_UMSK (~(((1U << DSP2_MIDDLE_LSC_ON_W_LEN) - 1) << DSP2_MIDDLE_LSC_ON_W_POS)) -#define DSP2_MIDDLE_X_OFFSET_W DSP2_MIDDLE_X_OFFSET_W -#define DSP2_MIDDLE_X_OFFSET_W_POS (16U) -#define DSP2_MIDDLE_X_OFFSET_W_LEN (8U) -#define DSP2_MIDDLE_X_OFFSET_W_MSK (((1U << DSP2_MIDDLE_X_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_X_OFFSET_W_POS) -#define DSP2_MIDDLE_X_OFFSET_W_UMSK (~(((1U << DSP2_MIDDLE_X_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_X_OFFSET_W_POS)) -#define DSP2_MIDDLE_Y_OFFSET_W DSP2_MIDDLE_Y_OFFSET_W -#define DSP2_MIDDLE_Y_OFFSET_W_POS (24U) -#define DSP2_MIDDLE_Y_OFFSET_W_LEN (8U) -#define DSP2_MIDDLE_Y_OFFSET_W_MSK (((1U << DSP2_MIDDLE_Y_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_Y_OFFSET_W_POS) -#define DSP2_MIDDLE_Y_OFFSET_W_UMSK (~(((1U << DSP2_MIDDLE_Y_OFFSET_W_LEN) - 1) << DSP2_MIDDLE_Y_OFFSET_W_POS)) - -/* 0x228 : LSC_coeff_R_A */ -#define DSP2_MIDDLE_LSC_COEFF_R_A_OFFSET (0x228) -#define DSP2_MIDDLE_R_ACOEFF_W DSP2_MIDDLE_R_ACOEFF_W -#define DSP2_MIDDLE_R_ACOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_ACOEFF_W_LEN (23U) -#define DSP2_MIDDLE_R_ACOEFF_W_MSK (((1U << DSP2_MIDDLE_R_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ACOEFF_W_POS) -#define DSP2_MIDDLE_R_ACOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ACOEFF_W_POS)) - -/* 0x22C : LSC_coeff_R_BE */ -#define DSP2_MIDDLE_LSC_COEFF_R_BE_OFFSET (0x22C) -#define DSP2_MIDDLE_R_BCOEFF_W DSP2_MIDDLE_R_BCOEFF_W -#define DSP2_MIDDLE_R_BCOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_BCOEFF_W_LEN (13U) -#define DSP2_MIDDLE_R_BCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_BCOEFF_W_POS) -#define DSP2_MIDDLE_R_BCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_BCOEFF_W_POS)) -#define DSP2_MIDDLE_R_ECOEFF_W DSP2_MIDDLE_R_ECOEFF_W -#define DSP2_MIDDLE_R_ECOEFF_W_POS (16U) -#define DSP2_MIDDLE_R_ECOEFF_W_LEN (13U) -#define DSP2_MIDDLE_R_ECOEFF_W_MSK (((1U << DSP2_MIDDLE_R_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ECOEFF_W_POS) -#define DSP2_MIDDLE_R_ECOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_ECOEFF_W_POS)) - -/* 0x230 : LSC_coeff_R_CD */ -#define DSP2_MIDDLE_LSC_COEFF_R_CD_OFFSET (0x230) -#define DSP2_MIDDLE_R_DCOEFF_W DSP2_MIDDLE_R_DCOEFF_W -#define DSP2_MIDDLE_R_DCOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_DCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_R_DCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_DCOEFF_W_POS) -#define DSP2_MIDDLE_R_DCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_DCOEFF_W_POS)) -#define DSP2_MIDDLE_R_CCOEFF_W DSP2_MIDDLE_R_CCOEFF_W -#define DSP2_MIDDLE_R_CCOEFF_W_POS (24U) -#define DSP2_MIDDLE_R_CCOEFF_W_LEN (8U) -#define DSP2_MIDDLE_R_CCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_CCOEFF_W_POS) -#define DSP2_MIDDLE_R_CCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_CCOEFF_W_POS)) - -/* 0x234 : LSC_coeff_R_G */ -#define DSP2_MIDDLE_LSC_COEFF_R_G_OFFSET (0x234) -#define DSP2_MIDDLE_R_GCOEFF_W DSP2_MIDDLE_R_GCOEFF_W -#define DSP2_MIDDLE_R_GCOEFF_W_POS (0U) -#define DSP2_MIDDLE_R_GCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_R_GCOEFF_W_MSK (((1U << DSP2_MIDDLE_R_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_GCOEFF_W_POS) -#define DSP2_MIDDLE_R_GCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_R_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_R_GCOEFF_W_POS)) - -/* 0x238 : LSC_coeff_G_A */ -#define DSP2_MIDDLE_LSC_COEFF_G_A_OFFSET (0x238) -#define DSP2_MIDDLE_G_ACOEFF_W DSP2_MIDDLE_G_ACOEFF_W -#define DSP2_MIDDLE_G_ACOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_ACOEFF_W_LEN (23U) -#define DSP2_MIDDLE_G_ACOEFF_W_MSK (((1U << DSP2_MIDDLE_G_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ACOEFF_W_POS) -#define DSP2_MIDDLE_G_ACOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ACOEFF_W_POS)) - -/* 0x23C : LSC_coeff_G_BE */ -#define DSP2_MIDDLE_LSC_COEFF_G_BE_OFFSET (0x23C) -#define DSP2_MIDDLE_G_BCOEFF_W DSP2_MIDDLE_G_BCOEFF_W -#define DSP2_MIDDLE_G_BCOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_BCOEFF_W_LEN (13U) -#define DSP2_MIDDLE_G_BCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_BCOEFF_W_POS) -#define DSP2_MIDDLE_G_BCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_BCOEFF_W_POS)) -#define DSP2_MIDDLE_G_ECOEFF_W DSP2_MIDDLE_G_ECOEFF_W -#define DSP2_MIDDLE_G_ECOEFF_W_POS (16U) -#define DSP2_MIDDLE_G_ECOEFF_W_LEN (13U) -#define DSP2_MIDDLE_G_ECOEFF_W_MSK (((1U << DSP2_MIDDLE_G_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ECOEFF_W_POS) -#define DSP2_MIDDLE_G_ECOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_ECOEFF_W_POS)) - -/* 0x240 : LSC_coeff_G_CD */ -#define DSP2_MIDDLE_LSC_COEFF_G_CD_OFFSET (0x240) -#define DSP2_MIDDLE_G_DCOEFF_W DSP2_MIDDLE_G_DCOEFF_W -#define DSP2_MIDDLE_G_DCOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_DCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_G_DCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_DCOEFF_W_POS) -#define DSP2_MIDDLE_G_DCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_DCOEFF_W_POS)) -#define DSP2_MIDDLE_G_CCOEFF_W DSP2_MIDDLE_G_CCOEFF_W -#define DSP2_MIDDLE_G_CCOEFF_W_POS (24U) -#define DSP2_MIDDLE_G_CCOEFF_W_LEN (8U) -#define DSP2_MIDDLE_G_CCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_CCOEFF_W_POS) -#define DSP2_MIDDLE_G_CCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_CCOEFF_W_POS)) - -/* 0x244 : LSC_coeff_G_G */ -#define DSP2_MIDDLE_LSC_COEFF_G_G_OFFSET (0x244) -#define DSP2_MIDDLE_G_GCOEFF_W DSP2_MIDDLE_G_GCOEFF_W -#define DSP2_MIDDLE_G_GCOEFF_W_POS (0U) -#define DSP2_MIDDLE_G_GCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_G_GCOEFF_W_MSK (((1U << DSP2_MIDDLE_G_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_GCOEFF_W_POS) -#define DSP2_MIDDLE_G_GCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_G_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_G_GCOEFF_W_POS)) - -/* 0x248 : LSC_coeff_B_A */ -#define DSP2_MIDDLE_LSC_COEFF_B_A_OFFSET (0x248) -#define DSP2_MIDDLE_B_ACOEFF_W DSP2_MIDDLE_B_ACOEFF_W -#define DSP2_MIDDLE_B_ACOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_ACOEFF_W_LEN (23U) -#define DSP2_MIDDLE_B_ACOEFF_W_MSK (((1U << DSP2_MIDDLE_B_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ACOEFF_W_POS) -#define DSP2_MIDDLE_B_ACOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_ACOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ACOEFF_W_POS)) - -/* 0x24C : LSC_coeff_B_BE */ -#define DSP2_MIDDLE_LSC_COEFF_B_BE_OFFSET (0x24C) -#define DSP2_MIDDLE_B_BCOEFF_W DSP2_MIDDLE_B_BCOEFF_W -#define DSP2_MIDDLE_B_BCOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_BCOEFF_W_LEN (13U) -#define DSP2_MIDDLE_B_BCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_BCOEFF_W_POS) -#define DSP2_MIDDLE_B_BCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_BCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_BCOEFF_W_POS)) -#define DSP2_MIDDLE_B_ECOEFF_W DSP2_MIDDLE_B_ECOEFF_W -#define DSP2_MIDDLE_B_ECOEFF_W_POS (16U) -#define DSP2_MIDDLE_B_ECOEFF_W_LEN (13U) -#define DSP2_MIDDLE_B_ECOEFF_W_MSK (((1U << DSP2_MIDDLE_B_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ECOEFF_W_POS) -#define DSP2_MIDDLE_B_ECOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_ECOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_ECOEFF_W_POS)) - -/* 0x250 : LSC_coeff_B_CD */ -#define DSP2_MIDDLE_LSC_COEFF_B_CD_OFFSET (0x250) -#define DSP2_MIDDLE_B_DCOEFF_W DSP2_MIDDLE_B_DCOEFF_W -#define DSP2_MIDDLE_B_DCOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_DCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_B_DCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_DCOEFF_W_POS) -#define DSP2_MIDDLE_B_DCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_DCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_DCOEFF_W_POS)) -#define DSP2_MIDDLE_B_CCOEFF_W DSP2_MIDDLE_B_CCOEFF_W -#define DSP2_MIDDLE_B_CCOEFF_W_POS (24U) -#define DSP2_MIDDLE_B_CCOEFF_W_LEN (8U) -#define DSP2_MIDDLE_B_CCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_CCOEFF_W_POS) -#define DSP2_MIDDLE_B_CCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_CCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_CCOEFF_W_POS)) - -/* 0x254 : LSC_coeff_B_G */ -#define DSP2_MIDDLE_LSC_COEFF_B_G_OFFSET (0x254) -#define DSP2_MIDDLE_B_GCOEFF_W DSP2_MIDDLE_B_GCOEFF_W -#define DSP2_MIDDLE_B_GCOEFF_W_POS (0U) -#define DSP2_MIDDLE_B_GCOEFF_W_LEN (23U) -#define DSP2_MIDDLE_B_GCOEFF_W_MSK (((1U << DSP2_MIDDLE_B_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_GCOEFF_W_POS) -#define DSP2_MIDDLE_B_GCOEFF_W_UMSK (~(((1U << DSP2_MIDDLE_B_GCOEFF_W_LEN) - 1) << DSP2_MIDDLE_B_GCOEFF_W_POS)) - -/* 0x258 : MAX_R_G */ -#define DSP2_MIDDLE_MAX_R_G_OFFSET (0x258) -#define DSP2_MIDDLE_MAXR_W DSP2_MIDDLE_MAXR_W -#define DSP2_MIDDLE_MAXR_W_POS (0U) -#define DSP2_MIDDLE_MAXR_W_LEN (16U) -#define DSP2_MIDDLE_MAXR_W_MSK (((1U << DSP2_MIDDLE_MAXR_W_LEN) - 1) << DSP2_MIDDLE_MAXR_W_POS) -#define DSP2_MIDDLE_MAXR_W_UMSK (~(((1U << DSP2_MIDDLE_MAXR_W_LEN) - 1) << DSP2_MIDDLE_MAXR_W_POS)) -#define DSP2_MIDDLE_MAXG_W DSP2_MIDDLE_MAXG_W -#define DSP2_MIDDLE_MAXG_W_POS (16U) -#define DSP2_MIDDLE_MAXG_W_LEN (16U) -#define DSP2_MIDDLE_MAXG_W_MSK (((1U << DSP2_MIDDLE_MAXG_W_LEN) - 1) << DSP2_MIDDLE_MAXG_W_POS) -#define DSP2_MIDDLE_MAXG_W_UMSK (~(((1U << DSP2_MIDDLE_MAXG_W_LEN) - 1) << DSP2_MIDDLE_MAXG_W_POS)) - -/* 0x25C : MAX_B */ -#define DSP2_MIDDLE_MAX_B_OFFSET (0x25C) -#define DSP2_MIDDLE_MAXB_W DSP2_MIDDLE_MAXB_W -#define DSP2_MIDDLE_MAXB_W_POS (0U) -#define DSP2_MIDDLE_MAXB_W_LEN (16U) -#define DSP2_MIDDLE_MAXB_W_MSK (((1U << DSP2_MIDDLE_MAXB_W_LEN) - 1) << DSP2_MIDDLE_MAXB_W_POS) -#define DSP2_MIDDLE_MAXB_W_UMSK (~(((1U << DSP2_MIDDLE_MAXB_W_LEN) - 1) << DSP2_MIDDLE_MAXB_W_POS)) - -/* 0x260 : defect_setting */ -#define DSP2_MIDDLE_DEFECT_SETTING_OFFSET (0x260) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W DSP2_MIDDLE_DEFECT_CORRECT_MODE_W -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_POS (0U) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_LEN (3U) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_MSK (((1U << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_POS) -#define DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_CORRECT_MODE_W_POS)) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W DSP2_MIDDLE_RESOLUTION_ENHANCE1_W -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_POS (8U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_LEN (1U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_MSK (((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_POS) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_UMSK (~(((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE1_W_POS)) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W DSP2_MIDDLE_RESOLUTION_ENHANCE2_W -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_POS (9U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_LEN (1U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_MSK (((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_POS) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_UMSK (~(((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE2_W_POS)) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W DSP2_MIDDLE_RESOLUTION_ENHANCE3_W -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_POS (10U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_LEN (1U) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_MSK (((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_POS) -#define DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_UMSK (~(((1U << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_LEN) - 1) << DSP2_MIDDLE_RESOLUTION_ENHANCE3_W_POS)) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W DSP2_MIDDLE_DEFECT_ADDRESS_W -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_POS (16U) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_MSK (((1U << DSP2_MIDDLE_DEFECT_ADDRESS_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_ADDRESS_W_POS) -#define DSP2_MIDDLE_DEFECT_ADDRESS_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_ADDRESS_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_ADDRESS_W_POS)) - -/* 0x264 : defect_position */ -#define DSP2_MIDDLE_DEFECT_POSITION_OFFSET (0x264) -#define DSP2_MIDDLE_X_POSITION_W DSP2_MIDDLE_X_POSITION_W -#define DSP2_MIDDLE_X_POSITION_W_POS (0U) -#define DSP2_MIDDLE_X_POSITION_W_LEN (16U) -#define DSP2_MIDDLE_X_POSITION_W_MSK (((1U << DSP2_MIDDLE_X_POSITION_W_LEN) - 1) << DSP2_MIDDLE_X_POSITION_W_POS) -#define DSP2_MIDDLE_X_POSITION_W_UMSK (~(((1U << DSP2_MIDDLE_X_POSITION_W_LEN) - 1) << DSP2_MIDDLE_X_POSITION_W_POS)) -#define DSP2_MIDDLE_Y_POSITION_W DSP2_MIDDLE_Y_POSITION_W -#define DSP2_MIDDLE_Y_POSITION_W_POS (16U) -#define DSP2_MIDDLE_Y_POSITION_W_LEN (16U) -#define DSP2_MIDDLE_Y_POSITION_W_MSK (((1U << DSP2_MIDDLE_Y_POSITION_W_LEN) - 1) << DSP2_MIDDLE_Y_POSITION_W_POS) -#define DSP2_MIDDLE_Y_POSITION_W_UMSK (~(((1U << DSP2_MIDDLE_Y_POSITION_W_LEN) - 1) << DSP2_MIDDLE_Y_POSITION_W_POS)) - -/* 0x268 : defect_th_A */ -#define DSP2_MIDDLE_DEFECT_TH_A_OFFSET (0x268) -#define DSP2_MIDDLE_DEFECT_TH1_W DSP2_MIDDLE_DEFECT_TH1_W -#define DSP2_MIDDLE_DEFECT_TH1_W_POS (0U) -#define DSP2_MIDDLE_DEFECT_TH1_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH1_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH1_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH1_W_POS) -#define DSP2_MIDDLE_DEFECT_TH1_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH1_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH1_W_POS)) -#define DSP2_MIDDLE_DEFECT_TH2_W DSP2_MIDDLE_DEFECT_TH2_W -#define DSP2_MIDDLE_DEFECT_TH2_W_POS (8U) -#define DSP2_MIDDLE_DEFECT_TH2_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH2_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH2_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH2_W_POS) -#define DSP2_MIDDLE_DEFECT_TH2_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH2_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH2_W_POS)) -#define DSP2_MIDDLE_DEFECT_TH3_W DSP2_MIDDLE_DEFECT_TH3_W -#define DSP2_MIDDLE_DEFECT_TH3_W_POS (16U) -#define DSP2_MIDDLE_DEFECT_TH3_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH3_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH3_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH3_W_POS) -#define DSP2_MIDDLE_DEFECT_TH3_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH3_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH3_W_POS)) -#define DSP2_MIDDLE_DEFECT_TH4_W DSP2_MIDDLE_DEFECT_TH4_W -#define DSP2_MIDDLE_DEFECT_TH4_W_POS (24U) -#define DSP2_MIDDLE_DEFECT_TH4_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH4_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH4_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH4_W_POS) -#define DSP2_MIDDLE_DEFECT_TH4_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH4_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH4_W_POS)) - -/* 0x26C : defect_th_B */ -#define DSP2_MIDDLE_DEFECT_TH_B_OFFSET (0x26C) -#define DSP2_MIDDLE_DEFECT_TH5_W DSP2_MIDDLE_DEFECT_TH5_W -#define DSP2_MIDDLE_DEFECT_TH5_W_POS (0U) -#define DSP2_MIDDLE_DEFECT_TH5_W_LEN (8U) -#define DSP2_MIDDLE_DEFECT_TH5_W_MSK (((1U << DSP2_MIDDLE_DEFECT_TH5_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH5_W_POS) -#define DSP2_MIDDLE_DEFECT_TH5_W_UMSK (~(((1U << DSP2_MIDDLE_DEFECT_TH5_W_LEN) - 1) << DSP2_MIDDLE_DEFECT_TH5_W_POS)) - -/* 0x270 : awb_setting */ -#define DSP2_MIDDLE_AWB_SETTING_OFFSET (0x270) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_POS (0U) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_LEN (1U) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_MSK (((1U << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_LEN) - 1) << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_POS) -#define DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_LEN) - 1) << DSP2_MIDDLE_AWB_SWITCH_BANK_EN_W_POS)) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_POS (1U) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_LEN (1U) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_MSK (((1U << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_POS) -#define DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_UMSK (~(((1U << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W_POS)) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W DSP2_MIDDLE_BL_AWB_GAIN_SEL_W -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_POS (2U) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_LEN (1U) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_MSK (((1U << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_POS) -#define DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_UMSK (~(((1U << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_AWB_GAIN_SEL_W_POS)) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_POS (3U) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_LEN (1U) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_MSK (((1U << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_POS) -#define DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_UMSK (~(((1U << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_LEN) - 1) << DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W_POS)) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_POS (16U) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_LEN (11U) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_MSK (((1U << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_LEN) - 1) << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_POS) -#define DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_UMSK (~(((1U << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_LEN) - 1) << DSP2_MIDDLE_GRID_CNT_WITHIN_THRE_R_POS)) - -/* 0x274 : awb_roi_x */ -#define DSP2_MIDDLE_AWB_ROI_X_OFFSET (0x274) -#define DSP2_MIDDLE_AWB_ROI_START_X_W DSP2_MIDDLE_AWB_ROI_START_X_W -#define DSP2_MIDDLE_AWB_ROI_START_X_W_POS (0U) -#define DSP2_MIDDLE_AWB_ROI_START_X_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_START_X_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_START_X_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_X_W_POS) -#define DSP2_MIDDLE_AWB_ROI_START_X_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_START_X_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_X_W_POS)) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W DSP2_MIDDLE_AWB_ROI_WIDTH_W -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_POS (16U) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_WIDTH_W_POS) -#define DSP2_MIDDLE_AWB_ROI_WIDTH_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_WIDTH_W_POS)) - -/* 0x278 : awb_roi_y */ -#define DSP2_MIDDLE_AWB_ROI_Y_OFFSET (0x278) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W DSP2_MIDDLE_AWB_ROI_START_Y_W -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_POS (0U) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_START_Y_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_Y_W_POS) -#define DSP2_MIDDLE_AWB_ROI_START_Y_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_START_Y_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_START_Y_W_POS)) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W DSP2_MIDDLE_AWB_ROI_HEIGHT_W -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_POS (16U) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_LEN (11U) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_MSK (((1U << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_POS) -#define DSP2_MIDDLE_AWB_ROI_HEIGHT_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_ROI_HEIGHT_W_POS)) - -/* 0x27C : awb_image_size */ -#define DSP2_MIDDLE_AWB_IMAGE_SIZE_OFFSET (0x27C) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W DSP2_MIDDLE_AWB_IMAGE_WIDTH_W -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_POS (0U) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_LEN (11U) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_MSK (((1U << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_POS) -#define DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_WIDTH_W_POS)) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_POS (16U) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_LEN (11U) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_MSK (((1U << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_POS) -#define DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_IMAGE_HEIGHT_W_POS)) - -/* 0x280 : awb_grid_size */ -#define DSP2_MIDDLE_AWB_GRID_SIZE_OFFSET (0x280) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W DSP2_MIDDLE_AWB_GRID_WIDTH_W -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_POS (0U) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_LEN (8U) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_WIDTH_W_POS) -#define DSP2_MIDDLE_AWB_GRID_WIDTH_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_WIDTH_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_WIDTH_W_POS)) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W DSP2_MIDDLE_AWB_GRID_HEIGHT_W -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_POS (8U) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_LEN (8U) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_POS) -#define DSP2_MIDDLE_AWB_GRID_HEIGHT_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_HEIGHT_W_POS)) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W DSP2_MIDDLE_AWB_GRID_X_MAX_W -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_POS (16U) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_LEN (6U) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_X_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_X_MAX_W_POS) -#define DSP2_MIDDLE_AWB_GRID_X_MAX_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_X_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_X_MAX_W_POS)) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W DSP2_MIDDLE_AWB_GRID_Y_MAX_W -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_POS (24U) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_LEN (6U) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_MSK (((1U << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_POS) -#define DSP2_MIDDLE_AWB_GRID_Y_MAX_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_Y_MAX_W_POS)) - -/* 0x284 : awb_r_thre */ -#define DSP2_MIDDLE_AWB_R_THRE_OFFSET (0x284) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W DSP2_MIDDLE_AWB_R_MAX_THR_W -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_POS (0U) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_R_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MAX_THR_W_POS) -#define DSP2_MIDDLE_AWB_R_MAX_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MAX_THR_W_POS)) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W DSP2_MIDDLE_AWB_R_MIN_THR_W -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_POS (16U) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_R_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MIN_THR_W_POS) -#define DSP2_MIDDLE_AWB_R_MIN_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_R_MIN_THR_W_POS)) - -/* 0x288 : awb_g_thre */ -#define DSP2_MIDDLE_AWB_G_THRE_OFFSET (0x288) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W DSP2_MIDDLE_AWB_G_MAX_THR_W -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_POS (0U) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_G_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MAX_THR_W_POS) -#define DSP2_MIDDLE_AWB_G_MAX_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_G_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MAX_THR_W_POS)) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W DSP2_MIDDLE_AWB_G_MIN_THR_W -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_POS (16U) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_G_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MIN_THR_W_POS) -#define DSP2_MIDDLE_AWB_G_MIN_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_G_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_G_MIN_THR_W_POS)) - -/* 0x28C : awb_b_thre */ -#define DSP2_MIDDLE_AWB_B_THRE_OFFSET (0x28C) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W DSP2_MIDDLE_AWB_B_MAX_THR_W -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_POS (0U) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_B_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MAX_THR_W_POS) -#define DSP2_MIDDLE_AWB_B_MAX_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_MAX_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MAX_THR_W_POS)) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W DSP2_MIDDLE_AWB_B_MIN_THR_W -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_POS (16U) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_LEN (12U) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_MSK (((1U << DSP2_MIDDLE_AWB_B_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MIN_THR_W_POS) -#define DSP2_MIDDLE_AWB_B_MIN_THR_W_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_MIN_THR_W_LEN) - 1) << DSP2_MIDDLE_AWB_B_MIN_THR_W_POS)) - -/* 0x290 : awb_rgr_gain */ -#define DSP2_MIDDLE_AWB_RGR_GAIN_OFFSET (0x290) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE DSP2_MIDDLE_AWB_GR_GAIN_PRE -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_GR_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_GAIN_PRE_POS)) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE DSP2_MIDDLE_AWB_R_GAIN_PRE -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_R_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_GAIN_PRE_POS)) - -/* 0x294 : awb_bgb_gain */ -#define DSP2_MIDDLE_AWB_BGB_GAIN_OFFSET (0x294) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE DSP2_MIDDLE_AWB_GB_GAIN_PRE -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_GB_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_GAIN_PRE_POS)) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE DSP2_MIDDLE_AWB_B_GAIN_PRE -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_AWB_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_GAIN_PRE_POS) -#define DSP2_MIDDLE_AWB_B_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_GAIN_PRE_POS)) - -/* 0x298 : awb_rgr_offset */ -#define DSP2_MIDDLE_AWB_RGR_OFFSET_OFFSET (0x298) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE DSP2_MIDDLE_AWB_GR_OFFSET_PRE -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_GR_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GR_OFFSET_PRE_POS)) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE DSP2_MIDDLE_AWB_R_OFFSET_PRE -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_R_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_R_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_R_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_R_OFFSET_PRE_POS)) - -/* 0x29C : awb_bgb_offset */ -#define DSP2_MIDDLE_AWB_BGB_OFFSET_OFFSET (0x29C) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE DSP2_MIDDLE_AWB_GB_OFFSET_PRE -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_POS (0U) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_GB_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_GB_OFFSET_PRE_POS)) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE DSP2_MIDDLE_AWB_B_OFFSET_PRE -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_POS (16U) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_LEN (12U) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_MSK (((1U << DSP2_MIDDLE_AWB_B_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_OFFSET_PRE_POS) -#define DSP2_MIDDLE_AWB_B_OFFSET_PRE_UMSK (~(((1U << DSP2_MIDDLE_AWB_B_OFFSET_PRE_LEN) - 1) << DSP2_MIDDLE_AWB_B_OFFSET_PRE_POS)) - -/* 0x2A0 : cfa_int_1 */ -#define DSP2_MIDDLE_CFA_INT_1_OFFSET (0x2A0) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W DSP2_MIDDLE_REG_CFA_FRINGE_ON_W -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_POS (0U) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_LEN (1U) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_MSK (((1U << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_LEN) - 1) << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_POS) -#define DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_UMSK (~(((1U << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_LEN) - 1) << DSP2_MIDDLE_REG_CFA_FRINGE_ON_W_POS)) - -/* 0x2A8 : digital_rgr_gain */ -#define DSP2_MIDDLE_DIGITAL_RGR_GAIN_OFFSET (0x2A8) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE_POS)) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE DSP2_MIDDLE_DIGITAL_R_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_R_GAIN_PRE_POS)) - -/* 0x2AC : digital_bgb_gain */ -#define DSP2_MIDDLE_DIGITAL_BGB_GAIN_OFFSET (0x2AC) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_POS (0U) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE_POS)) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE DSP2_MIDDLE_DIGITAL_B_GAIN_PRE -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_POS (16U) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_LEN (16U) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_MSK (((1U << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_POS) -#define DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_LEN) - 1) << DSP2_MIDDLE_DIGITAL_B_GAIN_PRE_POS)) - -/* 0x2BC : ae_roi_x */ -#define DSP2_MIDDLE_AE_ROI_X_OFFSET (0x2BC) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE DSP2_MIDDLE_AE_ROI_START_X_PRE -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_POS (0U) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_START_X_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_X_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_START_X_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_START_X_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_X_PRE_POS)) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE DSP2_MIDDLE_AE_ROI_WIDTH_PRE -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_POS (16U) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_WIDTH_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_WIDTH_PRE_POS)) - -/* 0x2C0 : ae_roi_y */ -#define DSP2_MIDDLE_AE_ROI_Y_OFFSET (0x2C0) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE DSP2_MIDDLE_AE_ROI_START_Y_PRE -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_POS (0U) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_START_Y_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_Y_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_START_Y_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_START_Y_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_START_Y_PRE_POS)) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE DSP2_MIDDLE_AE_ROI_HEIGHT_PRE -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_POS (16U) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_MSK (((1U << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_POS) -#define DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_ROI_HEIGHT_PRE_POS)) - -/* 0x2C4 : ae_image_size */ -#define DSP2_MIDDLE_AE_IMAGE_SIZE_OFFSET (0x2C4) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_POS (0U) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_MSK (((1U << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_POS) -#define DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE_POS)) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_POS (16U) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_MSK (((1U << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_POS) -#define DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE_POS)) - -/* 0x2C8 : ae_grid_size */ -#define DSP2_MIDDLE_AE_GRID_SIZE_OFFSET (0x2C8) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE DSP2_MIDDLE_AE_GRID_WIDTH_PRE -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_POS (0U) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_WIDTH_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_WIDTH_PRE_POS)) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE DSP2_MIDDLE_AE_GRID_HEIGHT_PRE -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_POS (8U) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_HEIGHT_PRE_POS)) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE DSP2_MIDDLE_AE_GRID_Y_MAX_PRE -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_POS (16U) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_LEN (4U) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_Y_MAX_PRE_POS)) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE DSP2_MIDDLE_AE_GRID_X_MAX_PRE -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_POS (20U) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_LEN (4U) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_GRID_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_GRID_X_MAX_PRE_POS)) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W DSP2_MIDDLE_NEW_AE_STA_ENABLE_W -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_POS (24U) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_LEN (1U) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_MSK (((1U << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_POS) -#define DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_UMSK (~(((1U << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_LEN) - 1) << DSP2_MIDDLE_NEW_AE_STA_ENABLE_W_POS)) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_POS (25U) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_MSK (((1U << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_POS) -#define DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_EN_PRE DSP2_MIDDLE_AE_HIST_EN_PRE -#define DSP2_MIDDLE_AE_HIST_EN_PRE_POS (26U) -#define DSP2_MIDDLE_AE_HIST_EN_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_HIST_EN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_EN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_EN_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE DSP2_MIDDLE_AE_HIST_MODE_PRE -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_POS (27U) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_MODE_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_MODE_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_MODE_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_MODE_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_MODE_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE DSP2_MIDDLE_AE_HIST_ROI_EN_PRE -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_POS (28U) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_LEN (1U) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_ROI_EN_PRE_POS)) - -/* 0x2CC : ae_coeff */ -#define DSP2_MIDDLE_AE_COEFF_OFFSET (0x2CC) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_POS (0U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_MSK (((1U << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_POS) -#define DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE_POS)) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_POS (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_MSK (((1U << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_POS) -#define DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE_POS)) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_POS (16U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_LEN (8U) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_MSK (((1U << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_POS) -#define DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_LEN) - 1) << DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE_POS)) - -/* 0x2D0 : ae2_roi_x */ -#define DSP2_MIDDLE_AE2_ROI_X_OFFSET (0x2D0) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE DSP2_MIDDLE_AE_HIST_X_MAX_PRE -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_POS (0U) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_X_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MAX_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE DSP2_MIDDLE_AE_HIST_X_MIN_PRE -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_POS (16U) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_X_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_X_MIN_PRE_POS)) - -/* 0x2D4 : ae2_roi_y */ -#define DSP2_MIDDLE_AE2_ROI_Y_OFFSET (0x2D4) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE DSP2_MIDDLE_AE_HIST_Y_MAX_PRE -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_POS (0U) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MAX_PRE_POS)) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE DSP2_MIDDLE_AE_HIST_Y_MIN_PRE -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_POS (16U) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_LEN (11U) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_MSK (((1U << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_POS) -#define DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_LEN) - 1) << DSP2_MIDDLE_AE_HIST_Y_MIN_PRE_POS)) - -/* 0x2E8 : ae_status */ -#define DSP2_MIDDLE_AE_STATUS_OFFSET (0x2E8) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R DSP2_MIDDLE_AE_HIST_W_CNT_R -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_POS (4U) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_MSK (((1U << DSP2_MIDDLE_AE_HIST_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_AE_HIST_W_CNT_R_POS) -#define DSP2_MIDDLE_AE_HIST_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE_AE_HIST_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_AE_HIST_W_CNT_R_POS)) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R DSP2_MIDDLE_BLAE_BUF_IDX_R -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_POS (16U) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE_BLAE_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAE_BUF_IDX_R_POS) -#define DSP2_MIDDLE_BLAE_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE_BLAE_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAE_BUF_IDX_R_POS)) -#define DSP2_MIDDLE_BLAE_W_CNT_R DSP2_MIDDLE_BLAE_W_CNT_R -#define DSP2_MIDDLE_BLAE_W_CNT_R_POS (20U) -#define DSP2_MIDDLE_BLAE_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE_BLAE_W_CNT_R_MSK (((1U << DSP2_MIDDLE_BLAE_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAE_W_CNT_R_POS) -#define DSP2_MIDDLE_BLAE_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE_BLAE_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAE_W_CNT_R_POS)) - -/* 0x2EC : ae_sta_dbg */ -#define DSP2_MIDDLE_AE_STA_DBG_OFFSET (0x2EC) -#define DSP2_MIDDLE_AE_GRID_CNT DSP2_MIDDLE_AE_GRID_CNT -#define DSP2_MIDDLE_AE_GRID_CNT_POS (0U) -#define DSP2_MIDDLE_AE_GRID_CNT_LEN (7U) -#define DSP2_MIDDLE_AE_GRID_CNT_MSK (((1U << DSP2_MIDDLE_AE_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_POS) -#define DSP2_MIDDLE_AE_GRID_CNT_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_POS)) -#define DSP2_MIDDLE_AE_STA_DONE DSP2_MIDDLE_AE_STA_DONE -#define DSP2_MIDDLE_AE_STA_DONE_POS (7U) -#define DSP2_MIDDLE_AE_STA_DONE_LEN (1U) -#define DSP2_MIDDLE_AE_STA_DONE_MSK (((1U << DSP2_MIDDLE_AE_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AE_STA_DONE_POS) -#define DSP2_MIDDLE_AE_STA_DONE_UMSK (~(((1U << DSP2_MIDDLE_AE_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AE_STA_DONE_POS)) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT DSP2_MIDDLE_AE_WRITE_DATA_CNT -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_POS (8U) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_LEN (8U) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_MSK (((1U << DSP2_MIDDLE_AE_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AE_WRITE_DATA_CNT_POS) -#define DSP2_MIDDLE_AE_WRITE_DATA_CNT_UMSK (~(((1U << DSP2_MIDDLE_AE_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AE_WRITE_DATA_CNT_POS)) -#define DSP2_MIDDLE_AE_STA_INT_FLAG DSP2_MIDDLE_AE_STA_INT_FLAG -#define DSP2_MIDDLE_AE_STA_INT_FLAG_POS (16U) -#define DSP2_MIDDLE_AE_STA_INT_FLAG_LEN (1U) -#define DSP2_MIDDLE_AE_STA_INT_FLAG_MSK (((1U << DSP2_MIDDLE_AE_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AE_STA_INT_FLAG_POS) -#define DSP2_MIDDLE_AE_STA_INT_FLAG_UMSK (~(((1U << DSP2_MIDDLE_AE_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AE_STA_INT_FLAG_POS)) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX DSP2_MIDDLE_AE_GRID_CNT_MAX -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_POS (17U) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_LEN (7U) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_MSK (((1U << DSP2_MIDDLE_AE_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_MAX_POS) -#define DSP2_MIDDLE_AE_GRID_CNT_MAX_UMSK (~(((1U << DSP2_MIDDLE_AE_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AE_GRID_CNT_MAX_POS)) -#define DSP2_MIDDLE_AE_FIFO_FULL DSP2_MIDDLE_AE_FIFO_FULL -#define DSP2_MIDDLE_AE_FIFO_FULL_POS (24U) -#define DSP2_MIDDLE_AE_FIFO_FULL_LEN (1U) -#define DSP2_MIDDLE_AE_FIFO_FULL_MSK (((1U << DSP2_MIDDLE_AE_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_FULL_POS) -#define DSP2_MIDDLE_AE_FIFO_FULL_UMSK (~(((1U << DSP2_MIDDLE_AE_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_FULL_POS)) -#define DSP2_MIDDLE_AE_CONTROL_STATUS DSP2_MIDDLE_AE_CONTROL_STATUS -#define DSP2_MIDDLE_AE_CONTROL_STATUS_POS (25U) -#define DSP2_MIDDLE_AE_CONTROL_STATUS_LEN (4U) -#define DSP2_MIDDLE_AE_CONTROL_STATUS_MSK (((1U << DSP2_MIDDLE_AE_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AE_CONTROL_STATUS_POS) -#define DSP2_MIDDLE_AE_CONTROL_STATUS_UMSK (~(((1U << DSP2_MIDDLE_AE_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AE_CONTROL_STATUS_POS)) -#define DSP2_MIDDLE_AE_OPERATION_DONE DSP2_MIDDLE_AE_OPERATION_DONE -#define DSP2_MIDDLE_AE_OPERATION_DONE_POS (29U) -#define DSP2_MIDDLE_AE_OPERATION_DONE_LEN (1U) -#define DSP2_MIDDLE_AE_OPERATION_DONE_MSK (((1U << DSP2_MIDDLE_AE_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AE_OPERATION_DONE_POS) -#define DSP2_MIDDLE_AE_OPERATION_DONE_UMSK (~(((1U << DSP2_MIDDLE_AE_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AE_OPERATION_DONE_POS)) -#define DSP2_MIDDLE_AE_FIFO_EMPTY DSP2_MIDDLE_AE_FIFO_EMPTY -#define DSP2_MIDDLE_AE_FIFO_EMPTY_POS (30U) -#define DSP2_MIDDLE_AE_FIFO_EMPTY_LEN (1U) -#define DSP2_MIDDLE_AE_FIFO_EMPTY_MSK (((1U << DSP2_MIDDLE_AE_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_EMPTY_POS) -#define DSP2_MIDDLE_AE_FIFO_EMPTY_UMSK (~(((1U << DSP2_MIDDLE_AE_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AE_FIFO_EMPTY_POS)) - -/* 0x2F4 : awb_sta_dbg1 */ -#define DSP2_MIDDLE_AWB_STA_DBG1_OFFSET (0x2F4) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX DSP2_MIDDLE_AWB_GRID_CNT_MAX -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_POS (0U) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_LEN (11U) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_MSK (((1U << DSP2_MIDDLE_AWB_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_MAX_POS) -#define DSP2_MIDDLE_AWB_GRID_CNT_MAX_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_CNT_MAX_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_MAX_POS)) -#define DSP2_MIDDLE_AWB_FIFO_FULL DSP2_MIDDLE_AWB_FIFO_FULL -#define DSP2_MIDDLE_AWB_FIFO_FULL_POS (12U) -#define DSP2_MIDDLE_AWB_FIFO_FULL_LEN (1U) -#define DSP2_MIDDLE_AWB_FIFO_FULL_MSK (((1U << DSP2_MIDDLE_AWB_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_FULL_POS) -#define DSP2_MIDDLE_AWB_FIFO_FULL_UMSK (~(((1U << DSP2_MIDDLE_AWB_FIFO_FULL_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_FULL_POS)) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS DSP2_MIDDLE_AWB_CONTROL_STATUS -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_POS (16U) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_LEN (4U) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_MSK (((1U << DSP2_MIDDLE_AWB_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AWB_CONTROL_STATUS_POS) -#define DSP2_MIDDLE_AWB_CONTROL_STATUS_UMSK (~(((1U << DSP2_MIDDLE_AWB_CONTROL_STATUS_LEN) - 1) << DSP2_MIDDLE_AWB_CONTROL_STATUS_POS)) -#define DSP2_MIDDLE_AWB_OPERATION_DONE DSP2_MIDDLE_AWB_OPERATION_DONE -#define DSP2_MIDDLE_AWB_OPERATION_DONE_POS (20U) -#define DSP2_MIDDLE_AWB_OPERATION_DONE_LEN (1U) -#define DSP2_MIDDLE_AWB_OPERATION_DONE_MSK (((1U << DSP2_MIDDLE_AWB_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_OPERATION_DONE_POS) -#define DSP2_MIDDLE_AWB_OPERATION_DONE_UMSK (~(((1U << DSP2_MIDDLE_AWB_OPERATION_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_OPERATION_DONE_POS)) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY DSP2_MIDDLE_AWB_FIFO_EMPTY -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_POS (21U) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_LEN (1U) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_MSK (((1U << DSP2_MIDDLE_AWB_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_EMPTY_POS) -#define DSP2_MIDDLE_AWB_FIFO_EMPTY_UMSK (~(((1U << DSP2_MIDDLE_AWB_FIFO_EMPTY_LEN) - 1) << DSP2_MIDDLE_AWB_FIFO_EMPTY_POS)) -#define DSP2_MIDDLE_BLAWB_W_CNT_R DSP2_MIDDLE_BLAWB_W_CNT_R -#define DSP2_MIDDLE_BLAWB_W_CNT_R_POS (24U) -#define DSP2_MIDDLE_BLAWB_W_CNT_R_LEN (5U) -#define DSP2_MIDDLE_BLAWB_W_CNT_R_MSK (((1U << DSP2_MIDDLE_BLAWB_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_W_CNT_R_POS) -#define DSP2_MIDDLE_BLAWB_W_CNT_R_UMSK (~(((1U << DSP2_MIDDLE_BLAWB_W_CNT_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_W_CNT_R_POS)) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R DSP2_MIDDLE_BLAWB_BUF_IDX_R -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_POS (31U) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_LEN (1U) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_MSK (((1U << DSP2_MIDDLE_BLAWB_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_BUF_IDX_R_POS) -#define DSP2_MIDDLE_BLAWB_BUF_IDX_R_UMSK (~(((1U << DSP2_MIDDLE_BLAWB_BUF_IDX_R_LEN) - 1) << DSP2_MIDDLE_BLAWB_BUF_IDX_R_POS)) - -/* 0x2F8 : awb_sta_dbg0 */ -#define DSP2_MIDDLE_AWB_STA_DBG0_OFFSET (0x2F8) -#define DSP2_MIDDLE_AWB_GRID_CNT DSP2_MIDDLE_AWB_GRID_CNT -#define DSP2_MIDDLE_AWB_GRID_CNT_POS (0U) -#define DSP2_MIDDLE_AWB_GRID_CNT_LEN (10U) -#define DSP2_MIDDLE_AWB_GRID_CNT_MSK (((1U << DSP2_MIDDLE_AWB_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_POS) -#define DSP2_MIDDLE_AWB_GRID_CNT_UMSK (~(((1U << DSP2_MIDDLE_AWB_GRID_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_GRID_CNT_POS)) -#define DSP2_MIDDLE_AWB_STA_DONE DSP2_MIDDLE_AWB_STA_DONE -#define DSP2_MIDDLE_AWB_STA_DONE_POS (12U) -#define DSP2_MIDDLE_AWB_STA_DONE_LEN (1U) -#define DSP2_MIDDLE_AWB_STA_DONE_MSK (((1U << DSP2_MIDDLE_AWB_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_STA_DONE_POS) -#define DSP2_MIDDLE_AWB_STA_DONE_UMSK (~(((1U << DSP2_MIDDLE_AWB_STA_DONE_LEN) - 1) << DSP2_MIDDLE_AWB_STA_DONE_POS)) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT DSP2_MIDDLE_AWB_WRITE_DATA_CNT -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_POS (16U) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_LEN (12U) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_MSK (((1U << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_POS) -#define DSP2_MIDDLE_AWB_WRITE_DATA_CNT_UMSK (~(((1U << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_LEN) - 1) << DSP2_MIDDLE_AWB_WRITE_DATA_CNT_POS)) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG DSP2_MIDDLE_AWB_STA_INT_FLAG -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_POS (28U) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_LEN (1U) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_MSK (((1U << DSP2_MIDDLE_AWB_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AWB_STA_INT_FLAG_POS) -#define DSP2_MIDDLE_AWB_STA_INT_FLAG_UMSK (~(((1U << DSP2_MIDDLE_AWB_STA_INT_FLAG_LEN) - 1) << DSP2_MIDDLE_AWB_STA_INT_FLAG_POS)) - -/* 0x2FC : dummy */ -#define DSP2_MIDDLE_DUMMY_OFFSET (0x2FC) - -struct dsp2_middle_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[548]; - - /* 0x224 : LSC_setting */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t Lsc_on_w : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t X_offset_w : 8; /* [23:16], r/w, 0x4 */ - uint32_t Y_offset_w : 8; /* [31:24], r/w, 0x4 */ - } BF; - uint32_t WORD; - } LSC_setting; - - /* 0x228 : LSC_coeff_R_A */ - union { - struct { - uint32_t R_Acoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_R_A; - - /* 0x22C : LSC_coeff_R_BE */ - union { - struct { - uint32_t R_Bcoeff_w : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t R_Ecoeff_w : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_R_BE; - - /* 0x230 : LSC_coeff_R_CD */ - union { - struct { - uint32_t R_Dcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t R_Ccoeff_w : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } LSC_coeff_R_CD; - - /* 0x234 : LSC_coeff_R_G */ - union { - struct { - uint32_t R_Gcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_R_G; - - /* 0x238 : LSC_coeff_G_A */ - union { - struct { - uint32_t G_Acoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_G_A; - - /* 0x23C : LSC_coeff_G_BE */ - union { - struct { - uint32_t G_Bcoeff_w : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t G_Ecoeff_w : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_G_BE; - - /* 0x240 : LSC_coeff_G_CD */ - union { - struct { - uint32_t G_Dcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t G_Ccoeff_w : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } LSC_coeff_G_CD; - - /* 0x244 : LSC_coeff_G_G */ - union { - struct { - uint32_t G_Gcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_G_G; - - /* 0x248 : LSC_coeff_B_A */ - union { - struct { - uint32_t B_Acoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_B_A; - - /* 0x24C : LSC_coeff_B_BE */ - union { - struct { - uint32_t B_Bcoeff_w : 13; /* [12: 0], r/w, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t B_Ecoeff_w : 13; /* [28:16], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_B_BE; - - /* 0x250 : LSC_coeff_B_CD */ - union { - struct { - uint32_t B_Dcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t B_Ccoeff_w : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } LSC_coeff_B_CD; - - /* 0x254 : LSC_coeff_B_G */ - union { - struct { - uint32_t B_Gcoeff_w : 23; /* [22: 0], r/w, 0x0 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LSC_coeff_B_G; - - /* 0x258 : MAX_R_G */ - union { - struct { - uint32_t MAXR_w : 16; /* [15: 0], r/w, 0xff */ - uint32_t MAXG_w : 16; /* [31:16], r/w, 0xff */ - } BF; - uint32_t WORD; - } MAX_R_G; - - /* 0x25C : MAX_B */ - union { - struct { - uint32_t MAXB_w : 16; /* [15: 0], r/w, 0xff */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MAX_B; - - /* 0x260 : defect_setting */ - union { - struct { - uint32_t defect_correct_mode_w : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t resolution_enhance1_w : 1; /* [ 8], r/w, 0x1 */ - uint32_t resolution_enhance2_w : 1; /* [ 9], r/w, 0x1 */ - uint32_t resolution_enhance3_w : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t defect_address_w : 8; /* [23:16], r/w, 0x4 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } defect_setting; - - /* 0x264 : defect_position */ - union { - struct { - uint32_t x_position_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t y_position_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } defect_position; - - /* 0x268 : defect_th_A */ - union { - struct { - uint32_t defect_th1_w : 8; /* [ 7: 0], r/w, 0x46 */ - uint32_t defect_th2_w : 8; /* [15: 8], r/w, 0x14 */ - uint32_t defect_th3_w : 8; /* [23:16], r/w, 0x32 */ - uint32_t defect_th4_w : 8; /* [31:24], r/w, 0x32 */ - } BF; - uint32_t WORD; - } defect_th_A; - - /* 0x26C : defect_th_B */ - union { - struct { - uint32_t defect_th5_w : 8; /* [ 7: 0], r/w, 0x14 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } defect_th_B; - - /* 0x270 : awb_setting */ - union { - struct { - uint32_t awb_switch_bank_en_w : 1; /* [ 0], r/w, 0x1 */ - uint32_t new_awb_sta_enable_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t bl_awb_gain_sel_w : 1; /* [ 2], r/w, 0x1 */ - uint32_t bl_digital_gain_sel_w : 1; /* [ 3], r/w, 0x1 */ - uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ - uint32_t grid_cnt_within_thre_r : 11; /* [26:16], r, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_setting; - - /* 0x274 : awb_roi_x */ - union { - struct { - uint32_t awb_roi_start_x_w : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb_roi_width_w : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_roi_x; - - /* 0x278 : awb_roi_y */ - union { - struct { - uint32_t awb_roi_start_y_w : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb_roi_height_w : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_roi_y; - - /* 0x27C : awb_image_size */ - union { - struct { - uint32_t awb_image_width_w : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t awb_image_height_w : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_image_size; - - /* 0x280 : awb_grid_size */ - union { - struct { - uint32_t awb_grid_width_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t awb_grid_height_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t awb_grid_x_max_w : 6; /* [21:16], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t awb_grid_y_max_w : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_grid_size; - - /* 0x284 : awb_r_thre */ - union { - struct { - uint32_t awb_r_max_thr_w : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_r_min_thr_w : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_r_thre; - - /* 0x288 : awb_g_thre */ - union { - struct { - uint32_t awb_g_max_thr_w : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_g_min_thr_w : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_g_thre; - - /* 0x28C : awb_b_thre */ - union { - struct { - uint32_t awb_b_max_thr_w : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_b_min_thr_w : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_b_thre; - - /* 0x290 : awb_rgr_gain */ - union { - struct { - uint32_t awb_gr_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb_r_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb_rgr_gain; - - /* 0x294 : awb_bgb_gain */ - union { - struct { - uint32_t awb_gb_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t awb_b_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } awb_bgb_gain; - - /* 0x298 : awb_rgr_offset */ - union { - struct { - uint32_t awb_gr_offset_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_r_offset_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_rgr_offset; - - /* 0x29C : awb_bgb_offset */ - union { - struct { - uint32_t awb_gb_offset_pre : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t awb_b_offset_pre : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_bgb_offset; - - /* 0x2A0 : cfa_int_1 */ - union { - struct { - uint32_t reg_cfa_fringe_on_w : 1; /* [ 0], r/w, 0x1 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } cfa_int_1; - - /* 0x2a4 reserved */ - uint8_t RESERVED0x2a4[4]; - - /* 0x2A8 : digital_rgr_gain */ - union { - struct { - uint32_t digital_gr_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t digital_r_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } digital_rgr_gain; - - /* 0x2AC : digital_bgb_gain */ - union { - struct { - uint32_t digital_gb_gain_pre : 16; /* [15: 0], r/w, 0x1000 */ - uint32_t digital_b_gain_pre : 16; /* [31:16], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } digital_bgb_gain; - - /* 0x2b0 reserved */ - uint8_t RESERVED0x2b0[12]; - - /* 0x2BC : ae_roi_x */ - union { - struct { - uint32_t ae_roi_start_x_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_roi_width_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_roi_x; - - /* 0x2C0 : ae_roi_y */ - union { - struct { - uint32_t ae_roi_start_y_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_roi_height_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_roi_y; - - /* 0x2C4 : ae_image_size */ - union { - struct { - uint32_t ae_image_width_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_image_height_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_image_size; - - /* 0x2C8 : ae_grid_size */ - union { - struct { - uint32_t ae_grid_width_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t ae_grid_height_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t ae_grid_y_max_pre : 4; /* [19:16], r/w, 0x0 */ - uint32_t ae_grid_x_max_pre : 4; /* [23:20], r/w, 0x0 */ - uint32_t new_ae_sta_enable_w : 1; /* [ 24], r/w, 0x0 */ - uint32_t ae_switch_bank_en_pre : 1; /* [ 25], r/w, 0x1 */ - uint32_t ae_hist_en_pre : 1; /* [ 26], r/w, 0x1 */ - uint32_t ae_hist_mode_pre : 1; /* [ 27], r/w, 0x1 */ - uint32_t ae_hist_roi_en_pre : 1; /* [ 28], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_grid_size; - - /* 0x2CC : ae_coeff */ - union { - struct { - uint32_t ae_ysum_coeff_r_pre : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t ae_ysum_coeff_g_pre : 8; /* [15: 8], r/w, 0x0 */ - uint32_t ae_ysum_coeff_b_pre : 8; /* [23:16], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_coeff; - - /* 0x2D0 : ae2_roi_x */ - union { - struct { - uint32_t ae_hist_x_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_hist_x_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae2_roi_x; - - /* 0x2D4 : ae2_roi_y */ - union { - struct { - uint32_t ae_hist_y_max_pre : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t ae_hist_y_min_pre : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae2_roi_y; - - /* 0x2d8 reserved */ - uint8_t RESERVED0x2d8[16]; - - /* 0x2E8 : ae_status */ - union { - struct { - uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */ - uint32_t ae_hist_w_cnt_r : 5; /* [ 8: 4], r, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t blae_buf_idx_r : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_19 : 3; /* [19:17], rsvd, 0x0 */ - uint32_t blae_w_cnt_r : 5; /* [24:20], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_status; - - /* 0x2EC : ae_sta_dbg */ - union { - struct { - uint32_t ae_grid_cnt : 7; /* [ 6: 0], r, 0x0 */ - uint32_t ae_sta_done : 1; /* [ 7], r, 0x0 */ - uint32_t ae_write_data_cnt : 8; /* [15: 8], r, 0x0 */ - uint32_t ae_sta_int_flag : 1; /* [ 16], r, 0x0 */ - uint32_t ae_grid_cnt_max : 7; /* [23:17], r, 0x0 */ - uint32_t ae_fifo_full : 1; /* [ 24], r, 0x0 */ - uint32_t ae_control_status : 4; /* [28:25], r, 0x0 */ - uint32_t ae_operation_done : 1; /* [ 29], r, 0x0 */ - uint32_t ae_fifo_empty : 1; /* [ 30], r, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ae_sta_dbg; - - /* 0x2f0 reserved */ - uint8_t RESERVED0x2f0[4]; - - /* 0x2F4 : awb_sta_dbg1 */ - union { - struct { - uint32_t awb_grid_cnt_max : 11; /* [10: 0], r, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t awb_fifo_full : 1; /* [ 12], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t awb_control_status : 4; /* [19:16], r, 0x0 */ - uint32_t awb_operation_done : 1; /* [ 20], r, 0x0 */ - uint32_t awb_fifo_empty : 1; /* [ 21], r, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t blawb_w_cnt_r : 5; /* [28:24], r, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t blawb_buf_idx_r : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } awb_sta_dbg1; - - /* 0x2F8 : awb_sta_dbg0 */ - union { - struct { - uint32_t awb_grid_cnt : 10; /* [ 9: 0], r, 0x0 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t awb_sta_done : 1; /* [ 12], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t awb_write_data_cnt : 12; /* [27:16], r, 0x0 */ - uint32_t awb_sta_int_flag : 1; /* [ 28], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } awb_sta_dbg0; - - /* 0x2FC : dummy */ - union { - struct { - uint32_t Reserved_31_0 : 32; /* [31: 0], r/w, 0xf0f0f0f0 */ - } BF; - uint32_t WORD; - } dummy; -}; - -typedef volatile struct dsp2_middle_reg dsp2_middle_reg_t; - -#endif /* __DSP2_MIDDLE_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_misc_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_misc_reg.h deleted file mode 100644 index f7b5371083..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_misc_reg.h +++ /dev/null @@ -1,4491 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_misc_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_MISC_REG_H__ -#define __DSP2_MISC_REG_H__ - -#include "bl808.h" - -/* 0x0 : config */ -#define DSP2_MISC_CONFIG_OFFSET (0x0) -#define DSP2_MISC_RG_DVPAS_ENABLE DSP2_MISC_RG_DVPAS_ENABLE -#define DSP2_MISC_RG_DVPAS_ENABLE_POS (0U) -#define DSP2_MISC_RG_DVPAS_ENABLE_LEN (1U) -#define DSP2_MISC_RG_DVPAS_ENABLE_MSK (((1U << DSP2_MISC_RG_DVPAS_ENABLE_LEN) - 1) << DSP2_MISC_RG_DVPAS_ENABLE_POS) -#define DSP2_MISC_RG_DVPAS_ENABLE_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_ENABLE_LEN) - 1) << DSP2_MISC_RG_DVPAS_ENABLE_POS)) -#define DSP2_MISC_RG_DVPAS_HS_INV DSP2_MISC_RG_DVPAS_HS_INV -#define DSP2_MISC_RG_DVPAS_HS_INV_POS (1U) -#define DSP2_MISC_RG_DVPAS_HS_INV_LEN (1U) -#define DSP2_MISC_RG_DVPAS_HS_INV_MSK (((1U << DSP2_MISC_RG_DVPAS_HS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_HS_INV_POS) -#define DSP2_MISC_RG_DVPAS_HS_INV_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_HS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_HS_INV_POS)) -#define DSP2_MISC_RG_DVPAS_VS_INV DSP2_MISC_RG_DVPAS_VS_INV -#define DSP2_MISC_RG_DVPAS_VS_INV_POS (2U) -#define DSP2_MISC_RG_DVPAS_VS_INV_LEN (1U) -#define DSP2_MISC_RG_DVPAS_VS_INV_MSK (((1U << DSP2_MISC_RG_DVPAS_VS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_VS_INV_POS) -#define DSP2_MISC_RG_DVPAS_VS_INV_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_VS_INV_LEN) - 1) << DSP2_MISC_RG_DVPAS_VS_INV_POS)) -#define DSP2_MISC_RG_DVPAS_DA_ORDER DSP2_MISC_RG_DVPAS_DA_ORDER -#define DSP2_MISC_RG_DVPAS_DA_ORDER_POS (3U) -#define DSP2_MISC_RG_DVPAS_DA_ORDER_LEN (1U) -#define DSP2_MISC_RG_DVPAS_DA_ORDER_MSK (((1U << DSP2_MISC_RG_DVPAS_DA_ORDER_LEN) - 1) << DSP2_MISC_RG_DVPAS_DA_ORDER_POS) -#define DSP2_MISC_RG_DVPAS_DA_ORDER_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_DA_ORDER_LEN) - 1) << DSP2_MISC_RG_DVPAS_DA_ORDER_POS)) -#define DSP2_MISC_RG_DVPAS_FIFO_TH DSP2_MISC_RG_DVPAS_FIFO_TH -#define DSP2_MISC_RG_DVPAS_FIFO_TH_POS (16U) -#define DSP2_MISC_RG_DVPAS_FIFO_TH_LEN (11U) -#define DSP2_MISC_RG_DVPAS_FIFO_TH_MSK (((1U << DSP2_MISC_RG_DVPAS_FIFO_TH_LEN) - 1) << DSP2_MISC_RG_DVPAS_FIFO_TH_POS) -#define DSP2_MISC_RG_DVPAS_FIFO_TH_UMSK (~(((1U << DSP2_MISC_RG_DVPAS_FIFO_TH_LEN) - 1) << DSP2_MISC_RG_DVPAS_FIFO_TH_POS)) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC DSP2_MISC_CR_DSP2_DE_AS_HSYNC -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_POS (30U) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_LEN (1U) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_MSK (((1U << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_LEN) - 1) << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_POS) -#define DSP2_MISC_CR_DSP2_DE_AS_HSYNC_UMSK (~(((1U << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_LEN) - 1) << DSP2_MISC_CR_DSP2_DE_AS_HSYNC_POS)) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON DSP2_MISC_REG_DSP2_PCLK_FORCE_ON -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_POS (31U) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_LEN (1U) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_MSK (((1U << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_POS) -#define DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_UMSK (~(((1U << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_REG_DSP2_PCLK_FORCE_ON_POS)) - -/* 0x4 : pix_data_ctrl */ -#define DSP2_MISC_PIX_DATA_CTRL_OFFSET (0x4) -#define DSP2_MISC_REG_PIX_DATA_CTRL DSP2_MISC_REG_PIX_DATA_CTRL -#define DSP2_MISC_REG_PIX_DATA_CTRL_POS (0U) -#define DSP2_MISC_REG_PIX_DATA_CTRL_LEN (12U) -#define DSP2_MISC_REG_PIX_DATA_CTRL_MSK (((1U << DSP2_MISC_REG_PIX_DATA_CTRL_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_CTRL_POS) -#define DSP2_MISC_REG_PIX_DATA_CTRL_UMSK (~(((1U << DSP2_MISC_REG_PIX_DATA_CTRL_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_CTRL_POS)) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT DSP2_MISC_REG_PIX_DATA_SHT_BIT -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_POS (16U) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_LEN (4U) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_MSK (((1U << DSP2_MISC_REG_PIX_DATA_SHT_BIT_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_BIT_POS) -#define DSP2_MISC_REG_PIX_DATA_SHT_BIT_UMSK (~(((1U << DSP2_MISC_REG_PIX_DATA_SHT_BIT_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_BIT_POS)) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR DSP2_MISC_REG_PIX_DATA_SHT_DIR -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_POS (20U) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_LEN (1U) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_MSK (((1U << DSP2_MISC_REG_PIX_DATA_SHT_DIR_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_DIR_POS) -#define DSP2_MISC_REG_PIX_DATA_SHT_DIR_UMSK (~(((1U << DSP2_MISC_REG_PIX_DATA_SHT_DIR_LEN) - 1) << DSP2_MISC_REG_PIX_DATA_SHT_DIR_POS)) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC DSP2_MISC_REG_DSP2_DTSRC_SRC -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_POS (31U) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_LEN (1U) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_MSK (((1U << DSP2_MISC_REG_DSP2_DTSRC_SRC_LEN) - 1) << DSP2_MISC_REG_DSP2_DTSRC_SRC_POS) -#define DSP2_MISC_REG_DSP2_DTSRC_SRC_UMSK (~(((1U << DSP2_MISC_REG_DSP2_DTSRC_SRC_LEN) - 1) << DSP2_MISC_REG_DSP2_DTSRC_SRC_POS)) - -/* 0x8 : dvp2bus_src_sel_1 */ -#define DSP2_MISC_DVP2BUS_SRC_SEL_1_OFFSET (0x8) -#define DSP2_MISC_RG_D2B_DVP_SEL_A DSP2_MISC_RG_D2B_DVP_SEL_A -#define DSP2_MISC_RG_D2B_DVP_SEL_A_POS (0U) -#define DSP2_MISC_RG_D2B_DVP_SEL_A_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_A_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_A_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_A_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_A_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_A DSP2_MISC_RG_D2X_ID_SEL_A -#define DSP2_MISC_RG_D2X_ID_SEL_A_POS (7U) -#define DSP2_MISC_RG_D2X_ID_SEL_A_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_A_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_A_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_A_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_A_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_A_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_B DSP2_MISC_RG_D2B_DVP_SEL_B -#define DSP2_MISC_RG_D2B_DVP_SEL_B_POS (8U) -#define DSP2_MISC_RG_D2B_DVP_SEL_B_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_B_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_B_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_B_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_B_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_B DSP2_MISC_RG_D2X_ID_SEL_B -#define DSP2_MISC_RG_D2X_ID_SEL_B_POS (15U) -#define DSP2_MISC_RG_D2X_ID_SEL_B_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_B_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_B_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_B_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_B_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_B_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_C DSP2_MISC_RG_D2B_DVP_SEL_C -#define DSP2_MISC_RG_D2B_DVP_SEL_C_POS (16U) -#define DSP2_MISC_RG_D2B_DVP_SEL_C_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_C_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_C_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_C_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_C_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_C DSP2_MISC_RG_D2X_ID_SEL_C -#define DSP2_MISC_RG_D2X_ID_SEL_C_POS (23U) -#define DSP2_MISC_RG_D2X_ID_SEL_C_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_C_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_C_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_C_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_C_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_C_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_D DSP2_MISC_RG_D2B_DVP_SEL_D -#define DSP2_MISC_RG_D2B_DVP_SEL_D_POS (24U) -#define DSP2_MISC_RG_D2B_DVP_SEL_D_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_D_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_D_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_D_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_D_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_D DSP2_MISC_RG_D2X_ID_SEL_D -#define DSP2_MISC_RG_D2X_ID_SEL_D_POS (31U) -#define DSP2_MISC_RG_D2X_ID_SEL_D_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_D_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_D_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_D_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_D_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_D_POS)) - -/* 0xC : dvp_frame_m_to_n */ -#define DSP2_MISC_DVP_FRAME_M_TO_N_OFFSET (0xC) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN DSP2_MISC_CR_FRAME_M_TO_N_EN -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_POS (0U) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_LEN (1U) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_MSK (((1U << DSP2_MISC_CR_FRAME_M_TO_N_EN_LEN) - 1) << DSP2_MISC_CR_FRAME_M_TO_N_EN_POS) -#define DSP2_MISC_CR_FRAME_M_TO_N_EN_UMSK (~(((1U << DSP2_MISC_CR_FRAME_M_TO_N_EN_LEN) - 1) << DSP2_MISC_CR_FRAME_M_TO_N_EN_POS)) -#define DSP2_MISC_CR_FRAME_INTERVAL DSP2_MISC_CR_FRAME_INTERVAL -#define DSP2_MISC_CR_FRAME_INTERVAL_POS (4U) -#define DSP2_MISC_CR_FRAME_INTERVAL_LEN (4U) -#define DSP2_MISC_CR_FRAME_INTERVAL_MSK (((1U << DSP2_MISC_CR_FRAME_INTERVAL_LEN) - 1) << DSP2_MISC_CR_FRAME_INTERVAL_POS) -#define DSP2_MISC_CR_FRAME_INTERVAL_UMSK (~(((1U << DSP2_MISC_CR_FRAME_INTERVAL_LEN) - 1) << DSP2_MISC_CR_FRAME_INTERVAL_POS)) -#define DSP2_MISC_CR_FRAME_CNT_N DSP2_MISC_CR_FRAME_CNT_N -#define DSP2_MISC_CR_FRAME_CNT_N_POS (8U) -#define DSP2_MISC_CR_FRAME_CNT_N_LEN (4U) -#define DSP2_MISC_CR_FRAME_CNT_N_MSK (((1U << DSP2_MISC_CR_FRAME_CNT_N_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_N_POS) -#define DSP2_MISC_CR_FRAME_CNT_N_UMSK (~(((1U << DSP2_MISC_CR_FRAME_CNT_N_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_N_POS)) -#define DSP2_MISC_CR_FRAME_CNT_M DSP2_MISC_CR_FRAME_CNT_M -#define DSP2_MISC_CR_FRAME_CNT_M_POS (12U) -#define DSP2_MISC_CR_FRAME_CNT_M_LEN (4U) -#define DSP2_MISC_CR_FRAME_CNT_M_MSK (((1U << DSP2_MISC_CR_FRAME_CNT_M_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_M_POS) -#define DSP2_MISC_CR_FRAME_CNT_M_UMSK (~(((1U << DSP2_MISC_CR_FRAME_CNT_M_LEN) - 1) << DSP2_MISC_CR_FRAME_CNT_M_POS)) - -/* 0x10 : dsp2_id_bayer */ -#define DSP2_MISC_DSP2_ID_BAYER_OFFSET (0x10) -#define DSP2_MISC_REG_BAYER_IDGEN_RST DSP2_MISC_REG_BAYER_IDGEN_RST -#define DSP2_MISC_REG_BAYER_IDGEN_RST_POS (0U) -#define DSP2_MISC_REG_BAYER_IDGEN_RST_LEN (1U) -#define DSP2_MISC_REG_BAYER_IDGEN_RST_MSK (((1U << DSP2_MISC_REG_BAYER_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_RST_POS) -#define DSP2_MISC_REG_BAYER_IDGEN_RST_UMSK (~(((1U << DSP2_MISC_REG_BAYER_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_RST_POS)) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE DSP2_MISC_REG_BAYER_IDGEN_EDGE -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_POS (1U) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_LEN (1U) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_MSK (((1U << DSP2_MISC_REG_BAYER_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_EDGE_POS) -#define DSP2_MISC_REG_BAYER_IDGEN_EDGE_UMSK (~(((1U << DSP2_MISC_REG_BAYER_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_EDGE_POS)) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_POS (16U) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_LEN (16U) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_MSK (((1U << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_POS) -#define DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_UMSK (~(((1U << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR_POS)) - -/* 0x14 : dvp2bus_src_sel_2 */ -#define DSP2_MISC_DVP2BUS_SRC_SEL_2_OFFSET (0x14) -#define DSP2_MISC_RG_D2B_DVP_SEL_E DSP2_MISC_RG_D2B_DVP_SEL_E -#define DSP2_MISC_RG_D2B_DVP_SEL_E_POS (0U) -#define DSP2_MISC_RG_D2B_DVP_SEL_E_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_E_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_E_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_E_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_E_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_E DSP2_MISC_RG_D2X_ID_SEL_E -#define DSP2_MISC_RG_D2X_ID_SEL_E_POS (7U) -#define DSP2_MISC_RG_D2X_ID_SEL_E_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_E_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_E_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_E_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_E_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_E_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_F DSP2_MISC_RG_D2B_DVP_SEL_F -#define DSP2_MISC_RG_D2B_DVP_SEL_F_POS (8U) -#define DSP2_MISC_RG_D2B_DVP_SEL_F_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_F_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_F_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_F_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_F_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_F DSP2_MISC_RG_D2X_ID_SEL_F -#define DSP2_MISC_RG_D2X_ID_SEL_F_POS (15U) -#define DSP2_MISC_RG_D2X_ID_SEL_F_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_F_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_F_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_F_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_F_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_F_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_G DSP2_MISC_RG_D2B_DVP_SEL_G -#define DSP2_MISC_RG_D2B_DVP_SEL_G_POS (16U) -#define DSP2_MISC_RG_D2B_DVP_SEL_G_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_G_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_G_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_G_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_G_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_G DSP2_MISC_RG_D2X_ID_SEL_G -#define DSP2_MISC_RG_D2X_ID_SEL_G_POS (23U) -#define DSP2_MISC_RG_D2X_ID_SEL_G_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_G_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_G_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_G_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_G_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_G_POS)) -#define DSP2_MISC_RG_D2B_DVP_SEL_H DSP2_MISC_RG_D2B_DVP_SEL_H -#define DSP2_MISC_RG_D2B_DVP_SEL_H_POS (24U) -#define DSP2_MISC_RG_D2B_DVP_SEL_H_LEN (6U) -#define DSP2_MISC_RG_D2B_DVP_SEL_H_MSK (((1U << DSP2_MISC_RG_D2B_DVP_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_H_POS) -#define DSP2_MISC_RG_D2B_DVP_SEL_H_UMSK (~(((1U << DSP2_MISC_RG_D2B_DVP_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2B_DVP_SEL_H_POS)) -#define DSP2_MISC_RG_D2X_ID_SEL_H DSP2_MISC_RG_D2X_ID_SEL_H -#define DSP2_MISC_RG_D2X_ID_SEL_H_POS (31U) -#define DSP2_MISC_RG_D2X_ID_SEL_H_LEN (1U) -#define DSP2_MISC_RG_D2X_ID_SEL_H_MSK (((1U << DSP2_MISC_RG_D2X_ID_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_H_POS) -#define DSP2_MISC_RG_D2X_ID_SEL_H_UMSK (~(((1U << DSP2_MISC_RG_D2X_ID_SEL_H_LEN) - 1) << DSP2_MISC_RG_D2X_ID_SEL_H_POS)) - -/* 0x20 : int_clr */ -#define DSP2_MISC_INT_CLR_OFFSET (0x20) -#define DSP2_MISC_RG_AWB_INT_CLR DSP2_MISC_RG_AWB_INT_CLR -#define DSP2_MISC_RG_AWB_INT_CLR_POS (0U) -#define DSP2_MISC_RG_AWB_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AWB_INT_CLR_MSK (((1U << DSP2_MISC_RG_AWB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB_INT_CLR_POS) -#define DSP2_MISC_RG_AWB_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AWB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB_INT_CLR_POS)) -#define DSP2_MISC_RG_AE_INT_CLR DSP2_MISC_RG_AE_INT_CLR -#define DSP2_MISC_RG_AE_INT_CLR_POS (1U) -#define DSP2_MISC_RG_AE_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AE_INT_CLR_MSK (((1U << DSP2_MISC_RG_AE_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_INT_CLR_POS) -#define DSP2_MISC_RG_AE_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AE_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_INT_CLR_POS)) -#define DSP2_MISC_RG_WDR_INT_CLR DSP2_MISC_RG_WDR_INT_CLR -#define DSP2_MISC_RG_WDR_INT_CLR_POS (2U) -#define DSP2_MISC_RG_WDR_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_WDR_INT_CLR_MSK (((1U << DSP2_MISC_RG_WDR_INT_CLR_LEN) - 1) << DSP2_MISC_RG_WDR_INT_CLR_POS) -#define DSP2_MISC_RG_WDR_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_WDR_INT_CLR_LEN) - 1) << DSP2_MISC_RG_WDR_INT_CLR_POS)) -#define DSP2_MISC_RG_AWB2_INT_CLR DSP2_MISC_RG_AWB2_INT_CLR -#define DSP2_MISC_RG_AWB2_INT_CLR_POS (3U) -#define DSP2_MISC_RG_AWB2_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AWB2_INT_CLR_MSK (((1U << DSP2_MISC_RG_AWB2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_CLR_POS) -#define DSP2_MISC_RG_AWB2_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AWB2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_CLR_POS)) -#define DSP2_MISC_RG_OSD_PB_INT_CLR DSP2_MISC_RG_OSD_PB_INT_CLR -#define DSP2_MISC_RG_OSD_PB_INT_CLR_POS (4U) -#define DSP2_MISC_RG_OSD_PB_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_OSD_PB_INT_CLR_MSK (((1U << DSP2_MISC_RG_OSD_PB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_CLR_POS) -#define DSP2_MISC_RG_OSD_PB_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_OSD_PB_INT_CLR_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF1_INT_CLR DSP2_MISC_RG_SEOF1_INT_CLR -#define DSP2_MISC_RG_SEOF1_INT_CLR_POS (8U) -#define DSP2_MISC_RG_SEOF1_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF1_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF1_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF2_INT_CLR DSP2_MISC_RG_SEOF2_INT_CLR -#define DSP2_MISC_RG_SEOF2_INT_CLR_POS (9U) -#define DSP2_MISC_RG_SEOF2_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF2_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF2_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF3_INT_CLR DSP2_MISC_RG_SEOF3_INT_CLR -#define DSP2_MISC_RG_SEOF3_INT_CLR_POS (10U) -#define DSP2_MISC_RG_SEOF3_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF3_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF3_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_CLR_POS)) -#define DSP2_MISC_RG_AE_HIST_INT_CLR DSP2_MISC_RG_AE_HIST_INT_CLR -#define DSP2_MISC_RG_AE_HIST_INT_CLR_POS (11U) -#define DSP2_MISC_RG_AE_HIST_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AE_HIST_INT_CLR_MSK (((1U << DSP2_MISC_RG_AE_HIST_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_CLR_POS) -#define DSP2_MISC_RG_AE_HIST_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AE_HIST_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_CLR_POS)) -#define DSP2_MISC_RG_AWB3_INT_CLR DSP2_MISC_RG_AWB3_INT_CLR -#define DSP2_MISC_RG_AWB3_INT_CLR_POS (12U) -#define DSP2_MISC_RG_AWB3_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_AWB3_INT_CLR_MSK (((1U << DSP2_MISC_RG_AWB3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_CLR_POS) -#define DSP2_MISC_RG_AWB3_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_AWB3_INT_CLR_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_CLR_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR DSP2_MISC_RG_DP_SEOF0_INT_CLR -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_POS (13U) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_CLR_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_CLR_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_CLR_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_CLR_POS)) -#define DSP2_MISC_RG_SEOF4_INT_CLR DSP2_MISC_RG_SEOF4_INT_CLR -#define DSP2_MISC_RG_SEOF4_INT_CLR_POS (14U) -#define DSP2_MISC_RG_SEOF4_INT_CLR_LEN (1U) -#define DSP2_MISC_RG_SEOF4_INT_CLR_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_CLR_POS) -#define DSP2_MISC_RG_SEOF4_INT_CLR_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_CLR_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_CLR_POS)) - -/* 0x24 : int_ctrl */ -#define DSP2_MISC_INT_CTRL_OFFSET (0x24) -#define DSP2_MISC_RG_AE_INT_MASK DSP2_MISC_RG_AE_INT_MASK -#define DSP2_MISC_RG_AE_INT_MASK_POS (0U) -#define DSP2_MISC_RG_AE_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AE_INT_MASK_MSK (((1U << DSP2_MISC_RG_AE_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_INT_MASK_POS) -#define DSP2_MISC_RG_AE_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AE_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_INT_MASK_POS)) -#define DSP2_MISC_RG_AWB_INT_MASK DSP2_MISC_RG_AWB_INT_MASK -#define DSP2_MISC_RG_AWB_INT_MASK_POS (1U) -#define DSP2_MISC_RG_AWB_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AWB_INT_MASK_MSK (((1U << DSP2_MISC_RG_AWB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB_INT_MASK_POS) -#define DSP2_MISC_RG_AWB_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AWB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB_INT_MASK_POS)) -#define DSP2_MISC_RG_WDR_INT_MASK DSP2_MISC_RG_WDR_INT_MASK -#define DSP2_MISC_RG_WDR_INT_MASK_POS (2U) -#define DSP2_MISC_RG_WDR_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_WDR_INT_MASK_MSK (((1U << DSP2_MISC_RG_WDR_INT_MASK_LEN) - 1) << DSP2_MISC_RG_WDR_INT_MASK_POS) -#define DSP2_MISC_RG_WDR_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_WDR_INT_MASK_LEN) - 1) << DSP2_MISC_RG_WDR_INT_MASK_POS)) -#define DSP2_MISC_RG_AWB2_INT_MASK DSP2_MISC_RG_AWB2_INT_MASK -#define DSP2_MISC_RG_AWB2_INT_MASK_POS (3U) -#define DSP2_MISC_RG_AWB2_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AWB2_INT_MASK_MSK (((1U << DSP2_MISC_RG_AWB2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_MASK_POS) -#define DSP2_MISC_RG_AWB2_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AWB2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB2_INT_MASK_POS)) -#define DSP2_MISC_RG_OSD_PB_INT_MASK DSP2_MISC_RG_OSD_PB_INT_MASK -#define DSP2_MISC_RG_OSD_PB_INT_MASK_POS (4U) -#define DSP2_MISC_RG_OSD_PB_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_OSD_PB_INT_MASK_MSK (((1U << DSP2_MISC_RG_OSD_PB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_MASK_POS) -#define DSP2_MISC_RG_OSD_PB_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_OSD_PB_INT_MASK_LEN) - 1) << DSP2_MISC_RG_OSD_PB_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF1_INT_MASK DSP2_MISC_RG_SEOF1_INT_MASK -#define DSP2_MISC_RG_SEOF1_INT_MASK_POS (8U) -#define DSP2_MISC_RG_SEOF1_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF1_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF1_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF1_INT_EDGE DSP2_MISC_RG_SEOF1_INT_EDGE -#define DSP2_MISC_RG_SEOF1_INT_EDGE_POS (9U) -#define DSP2_MISC_RG_SEOF1_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF1_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF1_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF1_INT_SRC DSP2_MISC_RG_SEOF1_INT_SRC -#define DSP2_MISC_RG_SEOF1_INT_SRC_POS (10U) -#define DSP2_MISC_RG_SEOF1_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF1_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF1_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF1_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF1_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF1_INT_SRC_POS)) -#define DSP2_MISC_RG_SEOF2_INT_MASK DSP2_MISC_RG_SEOF2_INT_MASK -#define DSP2_MISC_RG_SEOF2_INT_MASK_POS (12U) -#define DSP2_MISC_RG_SEOF2_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF2_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF2_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF2_INT_EDGE DSP2_MISC_RG_SEOF2_INT_EDGE -#define DSP2_MISC_RG_SEOF2_INT_EDGE_POS (13U) -#define DSP2_MISC_RG_SEOF2_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF2_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF2_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF2_INT_SRC DSP2_MISC_RG_SEOF2_INT_SRC -#define DSP2_MISC_RG_SEOF2_INT_SRC_POS (14U) -#define DSP2_MISC_RG_SEOF2_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF2_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF2_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF2_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF2_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF2_INT_SRC_POS)) -#define DSP2_MISC_RG_SEOF3_INT_MASK DSP2_MISC_RG_SEOF3_INT_MASK -#define DSP2_MISC_RG_SEOF3_INT_MASK_POS (16U) -#define DSP2_MISC_RG_SEOF3_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF3_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF3_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF3_INT_EDGE DSP2_MISC_RG_SEOF3_INT_EDGE -#define DSP2_MISC_RG_SEOF3_INT_EDGE_POS (17U) -#define DSP2_MISC_RG_SEOF3_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF3_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF3_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF3_INT_SRC DSP2_MISC_RG_SEOF3_INT_SRC -#define DSP2_MISC_RG_SEOF3_INT_SRC_POS (18U) -#define DSP2_MISC_RG_SEOF3_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF3_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF3_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF3_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF3_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF3_INT_SRC_POS)) -#define DSP2_MISC_RG_AE_HIST_INT_MASK DSP2_MISC_RG_AE_HIST_INT_MASK -#define DSP2_MISC_RG_AE_HIST_INT_MASK_POS (20U) -#define DSP2_MISC_RG_AE_HIST_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AE_HIST_INT_MASK_MSK (((1U << DSP2_MISC_RG_AE_HIST_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_MASK_POS) -#define DSP2_MISC_RG_AE_HIST_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AE_HIST_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AE_HIST_INT_MASK_POS)) -#define DSP2_MISC_RG_AWB3_INT_MASK DSP2_MISC_RG_AWB3_INT_MASK -#define DSP2_MISC_RG_AWB3_INT_MASK_POS (21U) -#define DSP2_MISC_RG_AWB3_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_AWB3_INT_MASK_MSK (((1U << DSP2_MISC_RG_AWB3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_MASK_POS) -#define DSP2_MISC_RG_AWB3_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_AWB3_INT_MASK_LEN) - 1) << DSP2_MISC_RG_AWB3_INT_MASK_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC DSP2_MISC_RG_DP_SEOF0_INT_SRC -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_POS (22U) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_SRC_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_SRC_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_SRC_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_SRC_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE DSP2_MISC_RG_DP_SEOF0_INT_EDGE -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_POS (23U) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_EDGE_POS)) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK DSP2_MISC_RG_DP_SEOF0_INT_MASK -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_POS (24U) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_MSK (((1U << DSP2_MISC_RG_DP_SEOF0_INT_MASK_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_MASK_POS) -#define DSP2_MISC_RG_DP_SEOF0_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_DP_SEOF0_INT_MASK_LEN) - 1) << DSP2_MISC_RG_DP_SEOF0_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF4_INT_MASK DSP2_MISC_RG_SEOF4_INT_MASK -#define DSP2_MISC_RG_SEOF4_INT_MASK_POS (28U) -#define DSP2_MISC_RG_SEOF4_INT_MASK_LEN (1U) -#define DSP2_MISC_RG_SEOF4_INT_MASK_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_MASK_POS) -#define DSP2_MISC_RG_SEOF4_INT_MASK_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_MASK_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_MASK_POS)) -#define DSP2_MISC_RG_SEOF4_INT_EDGE DSP2_MISC_RG_SEOF4_INT_EDGE -#define DSP2_MISC_RG_SEOF4_INT_EDGE_POS (29U) -#define DSP2_MISC_RG_SEOF4_INT_EDGE_LEN (1U) -#define DSP2_MISC_RG_SEOF4_INT_EDGE_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_EDGE_POS) -#define DSP2_MISC_RG_SEOF4_INT_EDGE_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_EDGE_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_EDGE_POS)) -#define DSP2_MISC_RG_SEOF4_INT_SRC DSP2_MISC_RG_SEOF4_INT_SRC -#define DSP2_MISC_RG_SEOF4_INT_SRC_POS (30U) -#define DSP2_MISC_RG_SEOF4_INT_SRC_LEN (2U) -#define DSP2_MISC_RG_SEOF4_INT_SRC_MSK (((1U << DSP2_MISC_RG_SEOF4_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_SRC_POS) -#define DSP2_MISC_RG_SEOF4_INT_SRC_UMSK (~(((1U << DSP2_MISC_RG_SEOF4_INT_SRC_LEN) - 1) << DSP2_MISC_RG_SEOF4_INT_SRC_POS)) - -/* 0x28 : dsp2_id_yuv */ -#define DSP2_MISC_DSP2_ID_YUV_OFFSET (0x28) -#define DSP2_MISC_REG_YUV_IDGEN_RST DSP2_MISC_REG_YUV_IDGEN_RST -#define DSP2_MISC_REG_YUV_IDGEN_RST_POS (0U) -#define DSP2_MISC_REG_YUV_IDGEN_RST_LEN (1U) -#define DSP2_MISC_REG_YUV_IDGEN_RST_MSK (((1U << DSP2_MISC_REG_YUV_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_RST_POS) -#define DSP2_MISC_REG_YUV_IDGEN_RST_UMSK (~(((1U << DSP2_MISC_REG_YUV_IDGEN_RST_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_RST_POS)) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE DSP2_MISC_REG_YUV_IDGEN_EDGE -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_POS (1U) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_LEN (1U) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_MSK (((1U << DSP2_MISC_REG_YUV_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_EDGE_POS) -#define DSP2_MISC_REG_YUV_IDGEN_EDGE_UMSK (~(((1U << DSP2_MISC_REG_YUV_IDGEN_EDGE_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_EDGE_POS)) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR DSP2_MISC_REG_YUV_IDGEN_CNT_INCR -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_POS (16U) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_LEN (16U) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_MSK (((1U << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_POS) -#define DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_UMSK (~(((1U << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_LEN) - 1) << DSP2_MISC_REG_YUV_IDGEN_CNT_INCR_POS)) - -/* 0x2C : dvp_reshape */ -#define DSP2_MISC_DVP_RESHAPE_OFFSET (0x2C) -#define DSP2_MISC_REG_RSHP_TGL_COUNT DSP2_MISC_REG_RSHP_TGL_COUNT -#define DSP2_MISC_REG_RSHP_TGL_COUNT_POS (0U) -#define DSP2_MISC_REG_RSHP_TGL_COUNT_LEN (5U) -#define DSP2_MISC_REG_RSHP_TGL_COUNT_MSK (((1U << DSP2_MISC_REG_RSHP_TGL_COUNT_LEN) - 1) << DSP2_MISC_REG_RSHP_TGL_COUNT_POS) -#define DSP2_MISC_REG_RSHP_TGL_COUNT_UMSK (~(((1U << DSP2_MISC_REG_RSHP_TGL_COUNT_LEN) - 1) << DSP2_MISC_REG_RSHP_TGL_COUNT_POS)) -#define DSP2_MISC_REG_RSHP_HSYNC_INV DSP2_MISC_REG_RSHP_HSYNC_INV -#define DSP2_MISC_REG_RSHP_HSYNC_INV_POS (5U) -#define DSP2_MISC_REG_RSHP_HSYNC_INV_LEN (1U) -#define DSP2_MISC_REG_RSHP_HSYNC_INV_MSK (((1U << DSP2_MISC_REG_RSHP_HSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_HSYNC_INV_POS) -#define DSP2_MISC_REG_RSHP_HSYNC_INV_UMSK (~(((1U << DSP2_MISC_REG_RSHP_HSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_HSYNC_INV_POS)) -#define DSP2_MISC_REG_RSHP_VSYNC_INV DSP2_MISC_REG_RSHP_VSYNC_INV -#define DSP2_MISC_REG_RSHP_VSYNC_INV_POS (6U) -#define DSP2_MISC_REG_RSHP_VSYNC_INV_LEN (1U) -#define DSP2_MISC_REG_RSHP_VSYNC_INV_MSK (((1U << DSP2_MISC_REG_RSHP_VSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_VSYNC_INV_POS) -#define DSP2_MISC_REG_RSHP_VSYNC_INV_UMSK (~(((1U << DSP2_MISC_REG_RSHP_VSYNC_INV_LEN) - 1) << DSP2_MISC_REG_RSHP_VSYNC_INV_POS)) -#define DSP2_MISC_REG_RSHP_CLR DSP2_MISC_REG_RSHP_CLR -#define DSP2_MISC_REG_RSHP_CLR_POS (7U) -#define DSP2_MISC_REG_RSHP_CLR_LEN (1U) -#define DSP2_MISC_REG_RSHP_CLR_MSK (((1U << DSP2_MISC_REG_RSHP_CLR_LEN) - 1) << DSP2_MISC_REG_RSHP_CLR_POS) -#define DSP2_MISC_REG_RSHP_CLR_UMSK (~(((1U << DSP2_MISC_REG_RSHP_CLR_LEN) - 1) << DSP2_MISC_REG_RSHP_CLR_POS)) -#define DSP2_MISC_REG_RSHP_EN DSP2_MISC_REG_RSHP_EN -#define DSP2_MISC_REG_RSHP_EN_POS (8U) -#define DSP2_MISC_REG_RSHP_EN_LEN (1U) -#define DSP2_MISC_REG_RSHP_EN_MSK (((1U << DSP2_MISC_REG_RSHP_EN_LEN) - 1) << DSP2_MISC_REG_RSHP_EN_POS) -#define DSP2_MISC_REG_RSHP_EN_UMSK (~(((1U << DSP2_MISC_REG_RSHP_EN_LEN) - 1) << DSP2_MISC_REG_RSHP_EN_POS)) - -/* 0x40 : scalerA_i_size */ -#define DSP2_MISC_SCALERA_I_SIZE_OFFSET (0x40) -#define DSP2_MISC_RG_SCALERA_I_W DSP2_MISC_RG_SCALERA_I_W -#define DSP2_MISC_RG_SCALERA_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERA_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERA_I_W_MSK (((1U << DSP2_MISC_RG_SCALERA_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_W_POS) -#define DSP2_MISC_RG_SCALERA_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_W_POS)) -#define DSP2_MISC_RG_SCALERA_I_H DSP2_MISC_RG_SCALERA_I_H -#define DSP2_MISC_RG_SCALERA_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERA_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERA_I_H_MSK (((1U << DSP2_MISC_RG_SCALERA_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_H_POS) -#define DSP2_MISC_RG_SCALERA_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_I_H_POS)) -#define DSP2_MISC_RG_SCLRA_SW_SH DSP2_MISC_RG_SCLRA_SW_SH -#define DSP2_MISC_RG_SCLRA_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRA_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRA_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRA_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRA_SW_SH_POS) -#define DSP2_MISC_RG_SCLRA_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRA_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRA_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERA_BYPASS DSP2_MISC_RG_SCALERA_BYPASS -#define DSP2_MISC_RG_SCALERA_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERA_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERA_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERA_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERA_BYPASS_POS) -#define DSP2_MISC_RG_SCALERA_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERA_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERA_SEL DSP2_MISC_RG_SCALERA_SEL -#define DSP2_MISC_RG_SCALERA_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERA_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERA_SEL_MSK (((1U << DSP2_MISC_RG_SCALERA_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERA_SEL_POS) -#define DSP2_MISC_RG_SCALERA_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERA_SEL_POS)) - -/* 0x44 : scalerA_o_size */ -#define DSP2_MISC_SCALERA_O_SIZE_OFFSET (0x44) -#define DSP2_MISC_RG_SCALERA_O_W DSP2_MISC_RG_SCALERA_O_W -#define DSP2_MISC_RG_SCALERA_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERA_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERA_O_W_MSK (((1U << DSP2_MISC_RG_SCALERA_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_W_POS) -#define DSP2_MISC_RG_SCALERA_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_W_POS)) -#define DSP2_MISC_RG_SCALERA_O_H DSP2_MISC_RG_SCALERA_O_H -#define DSP2_MISC_RG_SCALERA_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERA_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERA_O_H_MSK (((1U << DSP2_MISC_RG_SCALERA_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_H_POS) -#define DSP2_MISC_RG_SCALERA_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERA_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERA_O_H_POS)) - -/* 0x48 : scalerB_i_size */ -#define DSP2_MISC_SCALERB_I_SIZE_OFFSET (0x48) -#define DSP2_MISC_RG_SCALERB_I_W DSP2_MISC_RG_SCALERB_I_W -#define DSP2_MISC_RG_SCALERB_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERB_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERB_I_W_MSK (((1U << DSP2_MISC_RG_SCALERB_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_W_POS) -#define DSP2_MISC_RG_SCALERB_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_W_POS)) -#define DSP2_MISC_RG_SCALERB_I_H DSP2_MISC_RG_SCALERB_I_H -#define DSP2_MISC_RG_SCALERB_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERB_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERB_I_H_MSK (((1U << DSP2_MISC_RG_SCALERB_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_H_POS) -#define DSP2_MISC_RG_SCALERB_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_I_H_POS)) -#define DSP2_MISC_RG_SCLRB_SW_SH DSP2_MISC_RG_SCLRB_SW_SH -#define DSP2_MISC_RG_SCLRB_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRB_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRB_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRB_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRB_SW_SH_POS) -#define DSP2_MISC_RG_SCLRB_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRB_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRB_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERB_BYPASS DSP2_MISC_RG_SCALERB_BYPASS -#define DSP2_MISC_RG_SCALERB_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERB_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERB_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERB_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERB_BYPASS_POS) -#define DSP2_MISC_RG_SCALERB_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERB_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERB_SEL DSP2_MISC_RG_SCALERB_SEL -#define DSP2_MISC_RG_SCALERB_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERB_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERB_SEL_MSK (((1U << DSP2_MISC_RG_SCALERB_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERB_SEL_POS) -#define DSP2_MISC_RG_SCALERB_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERB_SEL_POS)) - -/* 0x4C : scalerB_o_size */ -#define DSP2_MISC_SCALERB_O_SIZE_OFFSET (0x4C) -#define DSP2_MISC_RG_SCALERB_O_W DSP2_MISC_RG_SCALERB_O_W -#define DSP2_MISC_RG_SCALERB_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERB_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERB_O_W_MSK (((1U << DSP2_MISC_RG_SCALERB_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_W_POS) -#define DSP2_MISC_RG_SCALERB_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_W_POS)) -#define DSP2_MISC_RG_SCALERB_O_H DSP2_MISC_RG_SCALERB_O_H -#define DSP2_MISC_RG_SCALERB_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERB_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERB_O_H_MSK (((1U << DSP2_MISC_RG_SCALERB_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_H_POS) -#define DSP2_MISC_RG_SCALERB_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERB_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERB_O_H_POS)) - -/* 0x50 : scalerC_i_size */ -#define DSP2_MISC_SCALERC_I_SIZE_OFFSET (0x50) -#define DSP2_MISC_RG_SCALERC_I_W DSP2_MISC_RG_SCALERC_I_W -#define DSP2_MISC_RG_SCALERC_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERC_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERC_I_W_MSK (((1U << DSP2_MISC_RG_SCALERC_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_W_POS) -#define DSP2_MISC_RG_SCALERC_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_W_POS)) -#define DSP2_MISC_RG_SCALERC_I_H DSP2_MISC_RG_SCALERC_I_H -#define DSP2_MISC_RG_SCALERC_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERC_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERC_I_H_MSK (((1U << DSP2_MISC_RG_SCALERC_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_H_POS) -#define DSP2_MISC_RG_SCALERC_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_I_H_POS)) -#define DSP2_MISC_RG_SCLRC_SW_SH DSP2_MISC_RG_SCLRC_SW_SH -#define DSP2_MISC_RG_SCLRC_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRC_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRC_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRC_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRC_SW_SH_POS) -#define DSP2_MISC_RG_SCLRC_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRC_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRC_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERC_BYPASS DSP2_MISC_RG_SCALERC_BYPASS -#define DSP2_MISC_RG_SCALERC_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERC_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERC_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERC_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERC_BYPASS_POS) -#define DSP2_MISC_RG_SCALERC_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERC_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERC_SEL DSP2_MISC_RG_SCALERC_SEL -#define DSP2_MISC_RG_SCALERC_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERC_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERC_SEL_MSK (((1U << DSP2_MISC_RG_SCALERC_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERC_SEL_POS) -#define DSP2_MISC_RG_SCALERC_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERC_SEL_POS)) - -/* 0x54 : scalerC_o_size */ -#define DSP2_MISC_SCALERC_O_SIZE_OFFSET (0x54) -#define DSP2_MISC_RG_SCALERC_O_W DSP2_MISC_RG_SCALERC_O_W -#define DSP2_MISC_RG_SCALERC_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERC_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERC_O_W_MSK (((1U << DSP2_MISC_RG_SCALERC_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_W_POS) -#define DSP2_MISC_RG_SCALERC_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_W_POS)) -#define DSP2_MISC_RG_SCALERC_O_H DSP2_MISC_RG_SCALERC_O_H -#define DSP2_MISC_RG_SCALERC_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERC_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERC_O_H_MSK (((1U << DSP2_MISC_RG_SCALERC_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_H_POS) -#define DSP2_MISC_RG_SCALERC_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERC_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERC_O_H_POS)) - -/* 0x58 : scalerD_i_size */ -#define DSP2_MISC_SCALERD_I_SIZE_OFFSET (0x58) -#define DSP2_MISC_RG_SCALERD_I_W DSP2_MISC_RG_SCALERD_I_W -#define DSP2_MISC_RG_SCALERD_I_W_POS (0U) -#define DSP2_MISC_RG_SCALERD_I_W_LEN (11U) -#define DSP2_MISC_RG_SCALERD_I_W_MSK (((1U << DSP2_MISC_RG_SCALERD_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_W_POS) -#define DSP2_MISC_RG_SCALERD_I_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_I_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_W_POS)) -#define DSP2_MISC_RG_SCALERD_I_H DSP2_MISC_RG_SCALERD_I_H -#define DSP2_MISC_RG_SCALERD_I_H_POS (16U) -#define DSP2_MISC_RG_SCALERD_I_H_LEN (11U) -#define DSP2_MISC_RG_SCALERD_I_H_MSK (((1U << DSP2_MISC_RG_SCALERD_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_H_POS) -#define DSP2_MISC_RG_SCALERD_I_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_I_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_I_H_POS)) -#define DSP2_MISC_RG_SCLRD_SW_SH DSP2_MISC_RG_SCLRD_SW_SH -#define DSP2_MISC_RG_SCLRD_SW_SH_POS (27U) -#define DSP2_MISC_RG_SCLRD_SW_SH_LEN (1U) -#define DSP2_MISC_RG_SCLRD_SW_SH_MSK (((1U << DSP2_MISC_RG_SCLRD_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRD_SW_SH_POS) -#define DSP2_MISC_RG_SCLRD_SW_SH_UMSK (~(((1U << DSP2_MISC_RG_SCLRD_SW_SH_LEN) - 1) << DSP2_MISC_RG_SCLRD_SW_SH_POS)) -#define DSP2_MISC_RG_SCALERD_BYPASS DSP2_MISC_RG_SCALERD_BYPASS -#define DSP2_MISC_RG_SCALERD_BYPASS_POS (28U) -#define DSP2_MISC_RG_SCALERD_BYPASS_LEN (1U) -#define DSP2_MISC_RG_SCALERD_BYPASS_MSK (((1U << DSP2_MISC_RG_SCALERD_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERD_BYPASS_POS) -#define DSP2_MISC_RG_SCALERD_BYPASS_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_BYPASS_LEN) - 1) << DSP2_MISC_RG_SCALERD_BYPASS_POS)) -#define DSP2_MISC_RG_SCALERD_SEL DSP2_MISC_RG_SCALERD_SEL -#define DSP2_MISC_RG_SCALERD_SEL_POS (29U) -#define DSP2_MISC_RG_SCALERD_SEL_LEN (3U) -#define DSP2_MISC_RG_SCALERD_SEL_MSK (((1U << DSP2_MISC_RG_SCALERD_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERD_SEL_POS) -#define DSP2_MISC_RG_SCALERD_SEL_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_SEL_LEN) - 1) << DSP2_MISC_RG_SCALERD_SEL_POS)) - -/* 0x5C : scalerD_o_size */ -#define DSP2_MISC_SCALERD_O_SIZE_OFFSET (0x5C) -#define DSP2_MISC_RG_SCALERD_O_W DSP2_MISC_RG_SCALERD_O_W -#define DSP2_MISC_RG_SCALERD_O_W_POS (0U) -#define DSP2_MISC_RG_SCALERD_O_W_LEN (11U) -#define DSP2_MISC_RG_SCALERD_O_W_MSK (((1U << DSP2_MISC_RG_SCALERD_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_W_POS) -#define DSP2_MISC_RG_SCALERD_O_W_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_O_W_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_W_POS)) -#define DSP2_MISC_RG_SCALERD_O_H DSP2_MISC_RG_SCALERD_O_H -#define DSP2_MISC_RG_SCALERD_O_H_POS (16U) -#define DSP2_MISC_RG_SCALERD_O_H_LEN (11U) -#define DSP2_MISC_RG_SCALERD_O_H_MSK (((1U << DSP2_MISC_RG_SCALERD_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_H_POS) -#define DSP2_MISC_RG_SCALERD_O_H_UMSK (~(((1U << DSP2_MISC_RG_SCALERD_O_H_LEN) - 1) << DSP2_MISC_RG_SCALERD_O_H_POS)) - -/* 0x60 : disp_config */ -#define DSP2_MISC_DISP_CONFIG_OFFSET (0x60) -#define DSP2_MISC_RG_DISP_BT656_EN DSP2_MISC_RG_DISP_BT656_EN -#define DSP2_MISC_RG_DISP_BT656_EN_POS (4U) -#define DSP2_MISC_RG_DISP_BT656_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_BT656_EN_MSK (((1U << DSP2_MISC_RG_DISP_BT656_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT656_EN_POS) -#define DSP2_MISC_RG_DISP_BT656_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_BT656_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT656_EN_POS)) -#define DSP2_MISC_RG_DISP_BT1120_EN DSP2_MISC_RG_DISP_BT1120_EN -#define DSP2_MISC_RG_DISP_BT1120_EN_POS (5U) -#define DSP2_MISC_RG_DISP_BT1120_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_BT1120_EN_MSK (((1U << DSP2_MISC_RG_DISP_BT1120_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT1120_EN_POS) -#define DSP2_MISC_RG_DISP_BT1120_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_BT1120_EN_LEN) - 1) << DSP2_MISC_RG_DISP_BT1120_EN_POS)) -#define DSP2_MISC_RG_DISP_DPI_EN DSP2_MISC_RG_DISP_DPI_EN -#define DSP2_MISC_RG_DISP_DPI_EN_POS (6U) -#define DSP2_MISC_RG_DISP_DPI_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_DPI_EN_MSK (((1U << DSP2_MISC_RG_DISP_DPI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_EN_POS) -#define DSP2_MISC_RG_DISP_DPI_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_EN_POS)) -#define DSP2_MISC_RG_DISP_HDMI_EN DSP2_MISC_RG_DISP_HDMI_EN -#define DSP2_MISC_RG_DISP_HDMI_EN_POS (7U) -#define DSP2_MISC_RG_DISP_HDMI_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_HDMI_EN_MSK (((1U << DSP2_MISC_RG_DISP_HDMI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_HDMI_EN_POS) -#define DSP2_MISC_RG_DISP_HDMI_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_HDMI_EN_LEN) - 1) << DSP2_MISC_RG_DISP_HDMI_EN_POS)) -#define DSP2_MISC_RG_DISP_MUX_SEL DSP2_MISC_RG_DISP_MUX_SEL -#define DSP2_MISC_RG_DISP_MUX_SEL_POS (8U) -#define DSP2_MISC_RG_DISP_MUX_SEL_LEN (2U) -#define DSP2_MISC_RG_DISP_MUX_SEL_MSK (((1U << DSP2_MISC_RG_DISP_MUX_SEL_LEN) - 1) << DSP2_MISC_RG_DISP_MUX_SEL_POS) -#define DSP2_MISC_RG_DISP_MUX_SEL_UMSK (~(((1U << DSP2_MISC_RG_DISP_MUX_SEL_LEN) - 1) << DSP2_MISC_RG_DISP_MUX_SEL_POS)) -#define DSP2_MISC_RG_OSDDP_SEL DSP2_MISC_RG_OSDDP_SEL -#define DSP2_MISC_RG_OSDDP_SEL_POS (12U) -#define DSP2_MISC_RG_OSDDP_SEL_LEN (2U) -#define DSP2_MISC_RG_OSDDP_SEL_MSK (((1U << DSP2_MISC_RG_OSDDP_SEL_LEN) - 1) << DSP2_MISC_RG_OSDDP_SEL_POS) -#define DSP2_MISC_RG_OSDDP_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDDP_SEL_LEN) - 1) << DSP2_MISC_RG_OSDDP_SEL_POS)) -#define DSP2_MISC_RG_DISP_CLKO_INV DSP2_MISC_RG_DISP_CLKO_INV -#define DSP2_MISC_RG_DISP_CLKO_INV_POS (31U) -#define DSP2_MISC_RG_DISP_CLKO_INV_LEN (1U) -#define DSP2_MISC_RG_DISP_CLKO_INV_MSK (((1U << DSP2_MISC_RG_DISP_CLKO_INV_LEN) - 1) << DSP2_MISC_RG_DISP_CLKO_INV_POS) -#define DSP2_MISC_RG_DISP_CLKO_INV_UMSK (~(((1U << DSP2_MISC_RG_DISP_CLKO_INV_LEN) - 1) << DSP2_MISC_RG_DISP_CLKO_INV_POS)) - -/* 0x64 : disp_dpi_config */ -#define DSP2_MISC_DISP_DPI_CONFIG_OFFSET (0x64) -#define DSP2_MISC_RG_DISP_DPI_HS_W DSP2_MISC_RG_DISP_DPI_HS_W -#define DSP2_MISC_RG_DISP_DPI_HS_W_POS (0U) -#define DSP2_MISC_RG_DISP_DPI_HS_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_HS_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_HS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HS_W_POS) -#define DSP2_MISC_RG_DISP_DPI_HS_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_HS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HS_W_POS)) -#define DSP2_MISC_RG_DISP_DPI_HFP_W DSP2_MISC_RG_DISP_DPI_HFP_W -#define DSP2_MISC_RG_DISP_DPI_HFP_W_POS (8U) -#define DSP2_MISC_RG_DISP_DPI_HFP_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_HFP_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_HFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HFP_W_POS) -#define DSP2_MISC_RG_DISP_DPI_HFP_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_HFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_HFP_W_POS)) -#define DSP2_MISC_RG_DISP_DPI_VS_W DSP2_MISC_RG_DISP_DPI_VS_W -#define DSP2_MISC_RG_DISP_DPI_VS_W_POS (16U) -#define DSP2_MISC_RG_DISP_DPI_VS_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_VS_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_VS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VS_W_POS) -#define DSP2_MISC_RG_DISP_DPI_VS_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_VS_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VS_W_POS)) -#define DSP2_MISC_RG_DISP_DPI_VFP_W DSP2_MISC_RG_DISP_DPI_VFP_W -#define DSP2_MISC_RG_DISP_DPI_VFP_W_POS (24U) -#define DSP2_MISC_RG_DISP_DPI_VFP_W_LEN (8U) -#define DSP2_MISC_RG_DISP_DPI_VFP_W_MSK (((1U << DSP2_MISC_RG_DISP_DPI_VFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VFP_W_POS) -#define DSP2_MISC_RG_DISP_DPI_VFP_W_UMSK (~(((1U << DSP2_MISC_RG_DISP_DPI_VFP_W_LEN) - 1) << DSP2_MISC_RG_DISP_DPI_VFP_W_POS)) - -/* 0x68 : disp_yuv_rgb_config_0 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_0_OFFSET (0x68) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0 DSP2_MISC_RG_DISP_Y2R_PRE_0 -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_0_POS) -#define DSP2_MISC_RG_DISP_Y2R_PRE_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_0_POS)) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1 DSP2_MISC_RG_DISP_Y2R_PRE_1 -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_POS (10U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_1_POS) -#define DSP2_MISC_RG_DISP_Y2R_PRE_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_1_POS)) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2 DSP2_MISC_RG_DISP_Y2R_PRE_2 -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_POS (20U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_2_POS) -#define DSP2_MISC_RG_DISP_Y2R_PRE_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_PRE_2_POS)) -#define DSP2_MISC_RG_DISP_Y2R_EN DSP2_MISC_RG_DISP_Y2R_EN -#define DSP2_MISC_RG_DISP_Y2R_EN_POS (31U) -#define DSP2_MISC_RG_DISP_Y2R_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_Y2R_EN_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_EN_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_EN_POS) -#define DSP2_MISC_RG_DISP_Y2R_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_EN_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_EN_POS)) - -/* 0x6C : disp_yuv_rgb_config_1 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_1_OFFSET (0x6C) -#define DSP2_MISC_RG_DISP_Y2R_POS_0 DSP2_MISC_RG_DISP_Y2R_POS_0 -#define DSP2_MISC_RG_DISP_Y2R_POS_0_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_POS_0_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_POS_0_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_0_POS) -#define DSP2_MISC_RG_DISP_Y2R_POS_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_0_POS)) -#define DSP2_MISC_RG_DISP_Y2R_POS_1 DSP2_MISC_RG_DISP_Y2R_POS_1 -#define DSP2_MISC_RG_DISP_Y2R_POS_1_POS (10U) -#define DSP2_MISC_RG_DISP_Y2R_POS_1_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_POS_1_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_1_POS) -#define DSP2_MISC_RG_DISP_Y2R_POS_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_1_POS)) -#define DSP2_MISC_RG_DISP_Y2R_POS_2 DSP2_MISC_RG_DISP_Y2R_POS_2 -#define DSP2_MISC_RG_DISP_Y2R_POS_2_POS (20U) -#define DSP2_MISC_RG_DISP_Y2R_POS_2_LEN (9U) -#define DSP2_MISC_RG_DISP_Y2R_POS_2_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_2_POS) -#define DSP2_MISC_RG_DISP_Y2R_POS_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_POS_2_POS)) - -/* 0x70 : disp_yuv_rgb_config_2 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_2_OFFSET (0x70) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00 DSP2_MISC_RG_DISP_Y2R_MTX_00 -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_00_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_00_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_00_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01 DSP2_MISC_RG_DISP_Y2R_MTX_01 -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_POS (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_01_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_01_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_01_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L DSP2_MISC_RG_DISP_Y2R_MTX_02_L -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_POS (24U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_LEN (8U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_L_POS)) - -/* 0x74 : disp_yuv_rgb_config_3 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_3_OFFSET (0x74) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U DSP2_MISC_RG_DISP_Y2R_MTX_02_U -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_LEN (4U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_02_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_02_U_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10 DSP2_MISC_RG_DISP_Y2R_MTX_10 -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_POS (4U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_10_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_10_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_10_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11 DSP2_MISC_RG_DISP_Y2R_MTX_11 -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_POS (16U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_11_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_11_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_11_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L DSP2_MISC_RG_DISP_Y2R_MTX_12_L -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_POS (28U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_LEN (4U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_L_POS)) - -/* 0x78 : disp_yuv_rgb_config_4 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_4_OFFSET (0x78) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U DSP2_MISC_RG_DISP_Y2R_MTX_12_U -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_LEN (8U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_12_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_12_U_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20 DSP2_MISC_RG_DISP_Y2R_MTX_20 -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_POS (8U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_20_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_20_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_20_POS)) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21 DSP2_MISC_RG_DISP_Y2R_MTX_21 -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_POS (20U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_21_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_21_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_21_POS)) - -/* 0x7C : disp_yuv_rgb_config_5 */ -#define DSP2_MISC_DISP_YUV_RGB_CONFIG_5_OFFSET (0x7C) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22 DSP2_MISC_RG_DISP_Y2R_MTX_22 -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_POS (0U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_LEN (12U) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_MSK (((1U << DSP2_MISC_RG_DISP_Y2R_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_22_POS) -#define DSP2_MISC_RG_DISP_Y2R_MTX_22_UMSK (~(((1U << DSP2_MISC_RG_DISP_Y2R_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_Y2R_MTX_22_POS)) - -/* 0x80 : dsp2_subsys_bus_ctrl */ -#define DSP2_MISC_DSP2_SUBSYS_BUS_CTRL_OFFSET (0x80) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_POS (0U) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_LEN (16U) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_MSK (((1U << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_POS) -#define DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_UMSK (~(((1U << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_SUB_PCLK_FORCE_ON_POS)) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_POS (16U) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_LEN (16U) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_MSK (((1U << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_POS) -#define DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_UMSK (~(((1U << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_LEN) - 1) << DSP2_MISC_RG_DSP2_PERI_PCLK_FORCE_ON_POS)) - -/* 0xA0 : osdA_i_ctrl */ -#define DSP2_MISC_OSDA_I_CTRL_OFFSET (0xA0) -#define DSP2_MISC_RG_OSD_PB_SEL DSP2_MISC_RG_OSD_PB_SEL -#define DSP2_MISC_RG_OSD_PB_SEL_POS (0U) -#define DSP2_MISC_RG_OSD_PB_SEL_LEN (1U) -#define DSP2_MISC_RG_OSD_PB_SEL_MSK (((1U << DSP2_MISC_RG_OSD_PB_SEL_LEN) - 1) << DSP2_MISC_RG_OSD_PB_SEL_POS) -#define DSP2_MISC_RG_OSD_PB_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSD_PB_SEL_LEN) - 1) << DSP2_MISC_RG_OSD_PB_SEL_POS)) -#define DSP2_MISC_RG_OSDA_SEL DSP2_MISC_RG_OSDA_SEL -#define DSP2_MISC_RG_OSDA_SEL_POS (29U) -#define DSP2_MISC_RG_OSDA_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDA_SEL_MSK (((1U << DSP2_MISC_RG_OSDA_SEL_LEN) - 1) << DSP2_MISC_RG_OSDA_SEL_POS) -#define DSP2_MISC_RG_OSDA_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDA_SEL_LEN) - 1) << DSP2_MISC_RG_OSDA_SEL_POS)) - -/* 0xA4 : osdB_i_ctrl */ -#define DSP2_MISC_OSDB_I_CTRL_OFFSET (0xA4) -#define DSP2_MISC_RG_OSDB_SEL DSP2_MISC_RG_OSDB_SEL -#define DSP2_MISC_RG_OSDB_SEL_POS (29U) -#define DSP2_MISC_RG_OSDB_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDB_SEL_MSK (((1U << DSP2_MISC_RG_OSDB_SEL_LEN) - 1) << DSP2_MISC_RG_OSDB_SEL_POS) -#define DSP2_MISC_RG_OSDB_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDB_SEL_LEN) - 1) << DSP2_MISC_RG_OSDB_SEL_POS)) - -/* 0xA8 : osdC_i_ctrl */ -#define DSP2_MISC_OSDC_I_CTRL_OFFSET (0xA8) -#define DSP2_MISC_RG_OSDC_SEL DSP2_MISC_RG_OSDC_SEL -#define DSP2_MISC_RG_OSDC_SEL_POS (29U) -#define DSP2_MISC_RG_OSDC_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDC_SEL_MSK (((1U << DSP2_MISC_RG_OSDC_SEL_LEN) - 1) << DSP2_MISC_RG_OSDC_SEL_POS) -#define DSP2_MISC_RG_OSDC_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDC_SEL_LEN) - 1) << DSP2_MISC_RG_OSDC_SEL_POS)) - -/* 0xAC : osdD_i_ctrl */ -#define DSP2_MISC_OSDD_I_CTRL_OFFSET (0xAC) -#define DSP2_MISC_RG_OSDD_SEL DSP2_MISC_RG_OSDD_SEL -#define DSP2_MISC_RG_OSDD_SEL_POS (29U) -#define DSP2_MISC_RG_OSDD_SEL_LEN (3U) -#define DSP2_MISC_RG_OSDD_SEL_MSK (((1U << DSP2_MISC_RG_OSDD_SEL_LEN) - 1) << DSP2_MISC_RG_OSDD_SEL_POS) -#define DSP2_MISC_RG_OSDD_SEL_UMSK (~(((1U << DSP2_MISC_RG_OSDD_SEL_LEN) - 1) << DSP2_MISC_RG_OSDD_SEL_POS)) - -/* 0xC0 : dsp2_subsys_dbg_sel */ -#define DSP2_MISC_DSP2_SUBSYS_DBG_SEL_OFFSET (0xC0) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN DSP2_MISC_REG_DSP2_SUB_DBG_EN -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_POS (0U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_LEN (1U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_MSK (((1U << DSP2_MISC_REG_DSP2_SUB_DBG_EN_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_EN_POS) -#define DSP2_MISC_REG_DSP2_SUB_DBG_EN_UMSK (~(((1U << DSP2_MISC_REG_DSP2_SUB_DBG_EN_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_EN_POS)) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL DSP2_MISC_REG_DSP2_SUB_DBG_SEL -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_POS (4U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_LEN (4U) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_MSK (((1U << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_POS) -#define DSP2_MISC_REG_DSP2_SUB_DBG_SEL_UMSK (~(((1U << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_LEN) - 1) << DSP2_MISC_REG_DSP2_SUB_DBG_SEL_POS)) - -/* 0xFC : DSP2_MISC_Dummy */ -#define DSP2_MISC_DUMMY_OFFSET (0xFC) -#define DSP2_MISC_DUMMY_REG DSP2_MISC_DUMMY_REG -#define DSP2_MISC_DUMMY_REG_POS (0U) -#define DSP2_MISC_DUMMY_REG_LEN (32U) -#define DSP2_MISC_DUMMY_REG_MSK (((1U << DSP2_MISC_DUMMY_REG_LEN) - 1) << DSP2_MISC_DUMMY_REG_POS) -#define DSP2_MISC_DUMMY_REG_UMSK (~(((1U << DSP2_MISC_DUMMY_REG_LEN) - 1) << DSP2_MISC_DUMMY_REG_POS)) - -/* 0x100 : adjA_ctrl_0 */ -#define DSP2_MISC_ADJA_CTRL_0_OFFSET (0x100) -#define DSP2_MISC_REG_ADJA_ADJ_EB DSP2_MISC_REG_ADJA_ADJ_EB -#define DSP2_MISC_REG_ADJA_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJA_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJA_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJA_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJA_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJA_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJA_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJA_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJA_Y_LUMA DSP2_MISC_REG_ADJA_Y_LUMA -#define DSP2_MISC_REG_ADJA_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJA_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJA_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJA_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJA_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJA_Y_MUL0 DSP2_MISC_REG_ADJA_Y_MUL0 -#define DSP2_MISC_REG_ADJA_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJA_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJA_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJA_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJA_Y_MUL1 DSP2_MISC_REG_ADJA_Y_MUL1 -#define DSP2_MISC_REG_ADJA_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJA_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJA_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJA_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MUL1_POS)) - -/* 0x104 : adjA_ctrl_1 */ -#define DSP2_MISC_ADJA_CTRL_1_OFFSET (0x104) -#define DSP2_MISC_REG_ADJA_Y_MIN DSP2_MISC_REG_ADJA_Y_MIN -#define DSP2_MISC_REG_ADJA_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJA_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJA_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MIN_POS) -#define DSP2_MISC_REG_ADJA_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJA_Y_MAX DSP2_MISC_REG_ADJA_Y_MAX -#define DSP2_MISC_REG_ADJA_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJA_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJA_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJA_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MAX_POS) -#define DSP2_MISC_REG_ADJA_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJA_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJA_UV_MIN DSP2_MISC_REG_ADJA_UV_MIN -#define DSP2_MISC_REG_ADJA_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJA_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJA_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MIN_POS) -#define DSP2_MISC_REG_ADJA_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJA_UV_MAX DSP2_MISC_REG_ADJA_UV_MAX -#define DSP2_MISC_REG_ADJA_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJA_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJA_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MAX_POS) -#define DSP2_MISC_REG_ADJA_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MAX_POS)) - -/* 0x108 : adjA_ctrl_2 */ -#define DSP2_MISC_ADJA_CTRL_2_OFFSET (0x108) -#define DSP2_MISC_RG_ADJA_SEL DSP2_MISC_RG_ADJA_SEL -#define DSP2_MISC_RG_ADJA_SEL_POS (0U) -#define DSP2_MISC_RG_ADJA_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJA_SEL_MSK (((1U << DSP2_MISC_RG_ADJA_SEL_LEN) - 1) << DSP2_MISC_RG_ADJA_SEL_POS) -#define DSP2_MISC_RG_ADJA_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJA_SEL_LEN) - 1) << DSP2_MISC_RG_ADJA_SEL_POS)) -#define DSP2_MISC_REG_ADJA_UV_MUL0 DSP2_MISC_REG_ADJA_UV_MUL0 -#define DSP2_MISC_REG_ADJA_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJA_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJA_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJA_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJA_UV_MUL1 DSP2_MISC_REG_ADJA_UV_MUL1 -#define DSP2_MISC_REG_ADJA_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJA_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJA_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJA_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJA_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJA_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJA_UV_MUL1_POS)) - -/* 0x110 : adjB_ctrl_0 */ -#define DSP2_MISC_ADJB_CTRL_0_OFFSET (0x110) -#define DSP2_MISC_REG_ADJB_ADJ_EB DSP2_MISC_REG_ADJB_ADJ_EB -#define DSP2_MISC_REG_ADJB_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJB_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJB_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJB_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJB_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJB_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJB_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJB_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJB_Y_LUMA DSP2_MISC_REG_ADJB_Y_LUMA -#define DSP2_MISC_REG_ADJB_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJB_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJB_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJB_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJB_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJB_Y_MUL0 DSP2_MISC_REG_ADJB_Y_MUL0 -#define DSP2_MISC_REG_ADJB_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJB_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJB_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJB_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJB_Y_MUL1 DSP2_MISC_REG_ADJB_Y_MUL1 -#define DSP2_MISC_REG_ADJB_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJB_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJB_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJB_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MUL1_POS)) - -/* 0x114 : adjB_ctrl_1 */ -#define DSP2_MISC_ADJB_CTRL_1_OFFSET (0x114) -#define DSP2_MISC_REG_ADJB_Y_MIN DSP2_MISC_REG_ADJB_Y_MIN -#define DSP2_MISC_REG_ADJB_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJB_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJB_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MIN_POS) -#define DSP2_MISC_REG_ADJB_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJB_Y_MAX DSP2_MISC_REG_ADJB_Y_MAX -#define DSP2_MISC_REG_ADJB_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJB_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJB_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJB_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MAX_POS) -#define DSP2_MISC_REG_ADJB_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJB_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJB_UV_MIN DSP2_MISC_REG_ADJB_UV_MIN -#define DSP2_MISC_REG_ADJB_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJB_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJB_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MIN_POS) -#define DSP2_MISC_REG_ADJB_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJB_UV_MAX DSP2_MISC_REG_ADJB_UV_MAX -#define DSP2_MISC_REG_ADJB_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJB_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJB_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MAX_POS) -#define DSP2_MISC_REG_ADJB_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MAX_POS)) - -/* 0x118 : adjB_ctrl_2 */ -#define DSP2_MISC_ADJB_CTRL_2_OFFSET (0x118) -#define DSP2_MISC_RG_ADJB_SEL DSP2_MISC_RG_ADJB_SEL -#define DSP2_MISC_RG_ADJB_SEL_POS (0U) -#define DSP2_MISC_RG_ADJB_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJB_SEL_MSK (((1U << DSP2_MISC_RG_ADJB_SEL_LEN) - 1) << DSP2_MISC_RG_ADJB_SEL_POS) -#define DSP2_MISC_RG_ADJB_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJB_SEL_LEN) - 1) << DSP2_MISC_RG_ADJB_SEL_POS)) -#define DSP2_MISC_REG_ADJB_UV_MUL0 DSP2_MISC_REG_ADJB_UV_MUL0 -#define DSP2_MISC_REG_ADJB_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJB_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJB_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJB_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJB_UV_MUL1 DSP2_MISC_REG_ADJB_UV_MUL1 -#define DSP2_MISC_REG_ADJB_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJB_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJB_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJB_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJB_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJB_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJB_UV_MUL1_POS)) - -/* 0x120 : adjC_ctrl_0 */ -#define DSP2_MISC_ADJC_CTRL_0_OFFSET (0x120) -#define DSP2_MISC_REG_ADJC_ADJ_EB DSP2_MISC_REG_ADJC_ADJ_EB -#define DSP2_MISC_REG_ADJC_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJC_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJC_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJC_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJC_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJC_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJC_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJC_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJC_Y_LUMA DSP2_MISC_REG_ADJC_Y_LUMA -#define DSP2_MISC_REG_ADJC_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJC_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJC_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJC_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJC_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJC_Y_MUL0 DSP2_MISC_REG_ADJC_Y_MUL0 -#define DSP2_MISC_REG_ADJC_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJC_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJC_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJC_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJC_Y_MUL1 DSP2_MISC_REG_ADJC_Y_MUL1 -#define DSP2_MISC_REG_ADJC_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJC_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJC_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJC_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MUL1_POS)) - -/* 0x124 : adjC_ctrl_1 */ -#define DSP2_MISC_ADJC_CTRL_1_OFFSET (0x124) -#define DSP2_MISC_REG_ADJC_Y_MIN DSP2_MISC_REG_ADJC_Y_MIN -#define DSP2_MISC_REG_ADJC_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJC_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJC_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MIN_POS) -#define DSP2_MISC_REG_ADJC_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJC_Y_MAX DSP2_MISC_REG_ADJC_Y_MAX -#define DSP2_MISC_REG_ADJC_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJC_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJC_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJC_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MAX_POS) -#define DSP2_MISC_REG_ADJC_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJC_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJC_UV_MIN DSP2_MISC_REG_ADJC_UV_MIN -#define DSP2_MISC_REG_ADJC_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJC_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJC_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MIN_POS) -#define DSP2_MISC_REG_ADJC_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJC_UV_MAX DSP2_MISC_REG_ADJC_UV_MAX -#define DSP2_MISC_REG_ADJC_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJC_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJC_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MAX_POS) -#define DSP2_MISC_REG_ADJC_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MAX_POS)) - -/* 0x128 : adjC_ctrl_2 */ -#define DSP2_MISC_ADJC_CTRL_2_OFFSET (0x128) -#define DSP2_MISC_RG_ADJC_SEL DSP2_MISC_RG_ADJC_SEL -#define DSP2_MISC_RG_ADJC_SEL_POS (0U) -#define DSP2_MISC_RG_ADJC_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJC_SEL_MSK (((1U << DSP2_MISC_RG_ADJC_SEL_LEN) - 1) << DSP2_MISC_RG_ADJC_SEL_POS) -#define DSP2_MISC_RG_ADJC_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJC_SEL_LEN) - 1) << DSP2_MISC_RG_ADJC_SEL_POS)) -#define DSP2_MISC_REG_ADJC_UV_MUL0 DSP2_MISC_REG_ADJC_UV_MUL0 -#define DSP2_MISC_REG_ADJC_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJC_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJC_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJC_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJC_UV_MUL1 DSP2_MISC_REG_ADJC_UV_MUL1 -#define DSP2_MISC_REG_ADJC_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJC_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJC_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJC_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJC_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJC_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJC_UV_MUL1_POS)) - -/* 0x130 : adjD_ctrl_0 */ -#define DSP2_MISC_ADJD_CTRL_0_OFFSET (0x130) -#define DSP2_MISC_REG_ADJD_ADJ_EB DSP2_MISC_REG_ADJD_ADJ_EB -#define DSP2_MISC_REG_ADJD_ADJ_EB_POS (0U) -#define DSP2_MISC_REG_ADJD_ADJ_EB_LEN (1U) -#define DSP2_MISC_REG_ADJD_ADJ_EB_MSK (((1U << DSP2_MISC_REG_ADJD_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJD_ADJ_EB_POS) -#define DSP2_MISC_REG_ADJD_ADJ_EB_UMSK (~(((1U << DSP2_MISC_REG_ADJD_ADJ_EB_LEN) - 1) << DSP2_MISC_REG_ADJD_ADJ_EB_POS)) -#define DSP2_MISC_REG_ADJD_Y_LUMA DSP2_MISC_REG_ADJD_Y_LUMA -#define DSP2_MISC_REG_ADJD_Y_LUMA_POS (1U) -#define DSP2_MISC_REG_ADJD_Y_LUMA_LEN (9U) -#define DSP2_MISC_REG_ADJD_Y_LUMA_MSK (((1U << DSP2_MISC_REG_ADJD_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_LUMA_POS) -#define DSP2_MISC_REG_ADJD_Y_LUMA_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_LUMA_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_LUMA_POS)) -#define DSP2_MISC_REG_ADJD_Y_MUL0 DSP2_MISC_REG_ADJD_Y_MUL0 -#define DSP2_MISC_REG_ADJD_Y_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJD_Y_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJD_Y_MUL0_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL0_POS) -#define DSP2_MISC_REG_ADJD_Y_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL0_POS)) -#define DSP2_MISC_REG_ADJD_Y_MUL1 DSP2_MISC_REG_ADJD_Y_MUL1 -#define DSP2_MISC_REG_ADJD_Y_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJD_Y_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJD_Y_MUL1_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL1_POS) -#define DSP2_MISC_REG_ADJD_Y_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MUL1_POS)) - -/* 0x134 : adjD_ctrl_1 */ -#define DSP2_MISC_ADJD_CTRL_1_OFFSET (0x134) -#define DSP2_MISC_REG_ADJD_Y_MIN DSP2_MISC_REG_ADJD_Y_MIN -#define DSP2_MISC_REG_ADJD_Y_MIN_POS (0U) -#define DSP2_MISC_REG_ADJD_Y_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJD_Y_MIN_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MIN_POS) -#define DSP2_MISC_REG_ADJD_Y_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MIN_POS)) -#define DSP2_MISC_REG_ADJD_Y_MAX DSP2_MISC_REG_ADJD_Y_MAX -#define DSP2_MISC_REG_ADJD_Y_MAX_POS (8U) -#define DSP2_MISC_REG_ADJD_Y_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJD_Y_MAX_MSK (((1U << DSP2_MISC_REG_ADJD_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MAX_POS) -#define DSP2_MISC_REG_ADJD_Y_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJD_Y_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_Y_MAX_POS)) -#define DSP2_MISC_REG_ADJD_UV_MIN DSP2_MISC_REG_ADJD_UV_MIN -#define DSP2_MISC_REG_ADJD_UV_MIN_POS (16U) -#define DSP2_MISC_REG_ADJD_UV_MIN_LEN (8U) -#define DSP2_MISC_REG_ADJD_UV_MIN_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MIN_POS) -#define DSP2_MISC_REG_ADJD_UV_MIN_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MIN_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MIN_POS)) -#define DSP2_MISC_REG_ADJD_UV_MAX DSP2_MISC_REG_ADJD_UV_MAX -#define DSP2_MISC_REG_ADJD_UV_MAX_POS (24U) -#define DSP2_MISC_REG_ADJD_UV_MAX_LEN (8U) -#define DSP2_MISC_REG_ADJD_UV_MAX_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MAX_POS) -#define DSP2_MISC_REG_ADJD_UV_MAX_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MAX_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MAX_POS)) - -/* 0x138 : adjD_ctrl_2 */ -#define DSP2_MISC_ADJD_CTRL_2_OFFSET (0x138) -#define DSP2_MISC_RG_ADJD_SEL DSP2_MISC_RG_ADJD_SEL -#define DSP2_MISC_RG_ADJD_SEL_POS (0U) -#define DSP2_MISC_RG_ADJD_SEL_LEN (4U) -#define DSP2_MISC_RG_ADJD_SEL_MSK (((1U << DSP2_MISC_RG_ADJD_SEL_LEN) - 1) << DSP2_MISC_RG_ADJD_SEL_POS) -#define DSP2_MISC_RG_ADJD_SEL_UMSK (~(((1U << DSP2_MISC_RG_ADJD_SEL_LEN) - 1) << DSP2_MISC_RG_ADJD_SEL_POS)) -#define DSP2_MISC_REG_ADJD_UV_MUL0 DSP2_MISC_REG_ADJD_UV_MUL0 -#define DSP2_MISC_REG_ADJD_UV_MUL0_POS (10U) -#define DSP2_MISC_REG_ADJD_UV_MUL0_LEN (11U) -#define DSP2_MISC_REG_ADJD_UV_MUL0_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL0_POS) -#define DSP2_MISC_REG_ADJD_UV_MUL0_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MUL0_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL0_POS)) -#define DSP2_MISC_REG_ADJD_UV_MUL1 DSP2_MISC_REG_ADJD_UV_MUL1 -#define DSP2_MISC_REG_ADJD_UV_MUL1_POS (21U) -#define DSP2_MISC_REG_ADJD_UV_MUL1_LEN (11U) -#define DSP2_MISC_REG_ADJD_UV_MUL1_MSK (((1U << DSP2_MISC_REG_ADJD_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL1_POS) -#define DSP2_MISC_REG_ADJD_UV_MUL1_UMSK (~(((1U << DSP2_MISC_REG_ADJD_UV_MUL1_LEN) - 1) << DSP2_MISC_REG_ADJD_UV_MUL1_POS)) - -/* 0x160 : y2rA_config_0 */ -#define DSP2_MISC_Y2RA_CONFIG_0_OFFSET (0x160) -#define DSP2_MISC_RG_Y2RA_PRE_0 DSP2_MISC_RG_Y2RA_PRE_0 -#define DSP2_MISC_RG_Y2RA_PRE_0_POS (0U) -#define DSP2_MISC_RG_Y2RA_PRE_0_LEN (9U) -#define DSP2_MISC_RG_Y2RA_PRE_0_MSK (((1U << DSP2_MISC_RG_Y2RA_PRE_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_0_POS) -#define DSP2_MISC_RG_Y2RA_PRE_0_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_PRE_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_0_POS)) -#define DSP2_MISC_RG_Y2RA_POS_0 DSP2_MISC_RG_Y2RA_POS_0 -#define DSP2_MISC_RG_Y2RA_POS_0_POS (16U) -#define DSP2_MISC_RG_Y2RA_POS_0_LEN (9U) -#define DSP2_MISC_RG_Y2RA_POS_0_MSK (((1U << DSP2_MISC_RG_Y2RA_POS_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_0_POS) -#define DSP2_MISC_RG_Y2RA_POS_0_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_POS_0_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_0_POS)) -#define DSP2_MISC_RG_Y2RA_EN DSP2_MISC_RG_Y2RA_EN -#define DSP2_MISC_RG_Y2RA_EN_POS (27U) -#define DSP2_MISC_RG_Y2RA_EN_LEN (1U) -#define DSP2_MISC_RG_Y2RA_EN_MSK (((1U << DSP2_MISC_RG_Y2RA_EN_LEN) - 1) << DSP2_MISC_RG_Y2RA_EN_POS) -#define DSP2_MISC_RG_Y2RA_EN_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_EN_LEN) - 1) << DSP2_MISC_RG_Y2RA_EN_POS)) -#define DSP2_MISC_RG_Y2RA_SEL DSP2_MISC_RG_Y2RA_SEL -#define DSP2_MISC_RG_Y2RA_SEL_POS (28U) -#define DSP2_MISC_RG_Y2RA_SEL_LEN (4U) -#define DSP2_MISC_RG_Y2RA_SEL_MSK (((1U << DSP2_MISC_RG_Y2RA_SEL_LEN) - 1) << DSP2_MISC_RG_Y2RA_SEL_POS) -#define DSP2_MISC_RG_Y2RA_SEL_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_SEL_LEN) - 1) << DSP2_MISC_RG_Y2RA_SEL_POS)) - -/* 0x164 : y2rA_config_1 */ -#define DSP2_MISC_Y2RA_CONFIG_1_OFFSET (0x164) -#define DSP2_MISC_RG_Y2RA_PRE_1 DSP2_MISC_RG_Y2RA_PRE_1 -#define DSP2_MISC_RG_Y2RA_PRE_1_POS (0U) -#define DSP2_MISC_RG_Y2RA_PRE_1_LEN (9U) -#define DSP2_MISC_RG_Y2RA_PRE_1_MSK (((1U << DSP2_MISC_RG_Y2RA_PRE_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_1_POS) -#define DSP2_MISC_RG_Y2RA_PRE_1_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_PRE_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_1_POS)) -#define DSP2_MISC_RG_Y2RA_POS_1 DSP2_MISC_RG_Y2RA_POS_1 -#define DSP2_MISC_RG_Y2RA_POS_1_POS (16U) -#define DSP2_MISC_RG_Y2RA_POS_1_LEN (9U) -#define DSP2_MISC_RG_Y2RA_POS_1_MSK (((1U << DSP2_MISC_RG_Y2RA_POS_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_1_POS) -#define DSP2_MISC_RG_Y2RA_POS_1_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_POS_1_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_1_POS)) - -/* 0x168 : y2rA_config_2 */ -#define DSP2_MISC_Y2RA_CONFIG_2_OFFSET (0x168) -#define DSP2_MISC_RG_Y2RA_PRE_2 DSP2_MISC_RG_Y2RA_PRE_2 -#define DSP2_MISC_RG_Y2RA_PRE_2_POS (0U) -#define DSP2_MISC_RG_Y2RA_PRE_2_LEN (9U) -#define DSP2_MISC_RG_Y2RA_PRE_2_MSK (((1U << DSP2_MISC_RG_Y2RA_PRE_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_2_POS) -#define DSP2_MISC_RG_Y2RA_PRE_2_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_PRE_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_PRE_2_POS)) -#define DSP2_MISC_RG_Y2RA_POS_2 DSP2_MISC_RG_Y2RA_POS_2 -#define DSP2_MISC_RG_Y2RA_POS_2_POS (16U) -#define DSP2_MISC_RG_Y2RA_POS_2_LEN (9U) -#define DSP2_MISC_RG_Y2RA_POS_2_MSK (((1U << DSP2_MISC_RG_Y2RA_POS_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_2_POS) -#define DSP2_MISC_RG_Y2RA_POS_2_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_POS_2_LEN) - 1) << DSP2_MISC_RG_Y2RA_POS_2_POS)) - -/* 0x16C : y2rA_config_3 */ -#define DSP2_MISC_Y2RA_CONFIG_3_OFFSET (0x16C) -#define DSP2_MISC_RG_Y2RA_MTX_00 DSP2_MISC_RG_Y2RA_MTX_00 -#define DSP2_MISC_RG_Y2RA_MTX_00_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_00_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_00_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_00_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_00_POS) -#define DSP2_MISC_RG_Y2RA_MTX_00_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_00_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_00_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_01 DSP2_MISC_RG_Y2RA_MTX_01 -#define DSP2_MISC_RG_Y2RA_MTX_01_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_01_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_01_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_01_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_01_POS) -#define DSP2_MISC_RG_Y2RA_MTX_01_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_01_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_01_POS)) - -/* 0x170 : y2rA_config_4 */ -#define DSP2_MISC_Y2RA_CONFIG_4_OFFSET (0x170) -#define DSP2_MISC_RG_Y2RA_MTX_02 DSP2_MISC_RG_Y2RA_MTX_02 -#define DSP2_MISC_RG_Y2RA_MTX_02_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_02_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_02_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_02_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_02_POS) -#define DSP2_MISC_RG_Y2RA_MTX_02_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_02_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_02_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_10 DSP2_MISC_RG_Y2RA_MTX_10 -#define DSP2_MISC_RG_Y2RA_MTX_10_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_10_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_10_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_10_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_10_POS) -#define DSP2_MISC_RG_Y2RA_MTX_10_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_10_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_10_POS)) - -/* 0x174 : y2rA_config_5 */ -#define DSP2_MISC_Y2RA_CONFIG_5_OFFSET (0x174) -#define DSP2_MISC_RG_Y2RA_MTX_11 DSP2_MISC_RG_Y2RA_MTX_11 -#define DSP2_MISC_RG_Y2RA_MTX_11_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_11_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_11_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_11_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_11_POS) -#define DSP2_MISC_RG_Y2RA_MTX_11_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_11_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_11_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_12 DSP2_MISC_RG_Y2RA_MTX_12 -#define DSP2_MISC_RG_Y2RA_MTX_12_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_12_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_12_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_12_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_12_POS) -#define DSP2_MISC_RG_Y2RA_MTX_12_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_12_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_12_POS)) - -/* 0x178 : y2rA_config_6 */ -#define DSP2_MISC_Y2RA_CONFIG_6_OFFSET (0x178) -#define DSP2_MISC_RG_Y2RA_MTX_20 DSP2_MISC_RG_Y2RA_MTX_20 -#define DSP2_MISC_RG_Y2RA_MTX_20_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_20_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_20_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_20_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_20_POS) -#define DSP2_MISC_RG_Y2RA_MTX_20_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_20_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_20_POS)) -#define DSP2_MISC_RG_Y2RA_MTX_21 DSP2_MISC_RG_Y2RA_MTX_21 -#define DSP2_MISC_RG_Y2RA_MTX_21_POS (16U) -#define DSP2_MISC_RG_Y2RA_MTX_21_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_21_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_21_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_21_POS) -#define DSP2_MISC_RG_Y2RA_MTX_21_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_21_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_21_POS)) - -/* 0x17C : y2rA_config_7 */ -#define DSP2_MISC_Y2RA_CONFIG_7_OFFSET (0x17C) -#define DSP2_MISC_RG_Y2RA_MTX_22 DSP2_MISC_RG_Y2RA_MTX_22 -#define DSP2_MISC_RG_Y2RA_MTX_22_POS (0U) -#define DSP2_MISC_RG_Y2RA_MTX_22_LEN (12U) -#define DSP2_MISC_RG_Y2RA_MTX_22_MSK (((1U << DSP2_MISC_RG_Y2RA_MTX_22_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_22_POS) -#define DSP2_MISC_RG_Y2RA_MTX_22_UMSK (~(((1U << DSP2_MISC_RG_Y2RA_MTX_22_LEN) - 1) << DSP2_MISC_RG_Y2RA_MTX_22_POS)) - -/* 0x180 : disp_rgb2yuv_config_0 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_0_OFFSET (0x180) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0 DSP2_MISC_RG_DISP_R2Y_PRE_0 -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_0_POS) -#define DSP2_MISC_RG_DISP_R2Y_PRE_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_PRE_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_0_POS)) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1 DSP2_MISC_RG_DISP_R2Y_PRE_1 -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_POS (10U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_1_POS) -#define DSP2_MISC_RG_DISP_R2Y_PRE_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_PRE_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_1_POS)) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2 DSP2_MISC_RG_DISP_R2Y_PRE_2 -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_POS (20U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_2_POS) -#define DSP2_MISC_RG_DISP_R2Y_PRE_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_PRE_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_PRE_2_POS)) -#define DSP2_MISC_RG_DISP_R2Y_EN DSP2_MISC_RG_DISP_R2Y_EN -#define DSP2_MISC_RG_DISP_R2Y_EN_POS (31U) -#define DSP2_MISC_RG_DISP_R2Y_EN_LEN (1U) -#define DSP2_MISC_RG_DISP_R2Y_EN_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_EN_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_EN_POS) -#define DSP2_MISC_RG_DISP_R2Y_EN_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_EN_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_EN_POS)) - -/* 0x184 : disp_rgb2yuv_config_1 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_1_OFFSET (0x184) -#define DSP2_MISC_RG_DISP_R2Y_POS_0 DSP2_MISC_RG_DISP_R2Y_POS_0 -#define DSP2_MISC_RG_DISP_R2Y_POS_0_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_POS_0_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_POS_0_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_0_POS) -#define DSP2_MISC_RG_DISP_R2Y_POS_0_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_POS_0_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_0_POS)) -#define DSP2_MISC_RG_DISP_R2Y_POS_1 DSP2_MISC_RG_DISP_R2Y_POS_1 -#define DSP2_MISC_RG_DISP_R2Y_POS_1_POS (10U) -#define DSP2_MISC_RG_DISP_R2Y_POS_1_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_POS_1_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_1_POS) -#define DSP2_MISC_RG_DISP_R2Y_POS_1_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_POS_1_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_1_POS)) -#define DSP2_MISC_RG_DISP_R2Y_POS_2 DSP2_MISC_RG_DISP_R2Y_POS_2 -#define DSP2_MISC_RG_DISP_R2Y_POS_2_POS (20U) -#define DSP2_MISC_RG_DISP_R2Y_POS_2_LEN (9U) -#define DSP2_MISC_RG_DISP_R2Y_POS_2_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_2_POS) -#define DSP2_MISC_RG_DISP_R2Y_POS_2_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_POS_2_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_POS_2_POS)) - -/* 0x188 : disp_rgb2yuv_config_2 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_2_OFFSET (0x188) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00 DSP2_MISC_RG_DISP_R2Y_MTX_00 -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_00_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_00_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_00_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_00_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01 DSP2_MISC_RG_DISP_R2Y_MTX_01 -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_POS (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_01_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_01_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_01_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_01_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L DSP2_MISC_RG_DISP_R2Y_MTX_02_L -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_POS (24U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_LEN (8U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_L_POS)) - -/* 0x18C : disp_rgb2yuv_config_3 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_3_OFFSET (0x18C) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U DSP2_MISC_RG_DISP_R2Y_MTX_02_U -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_LEN (4U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_02_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_02_U_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10 DSP2_MISC_RG_DISP_R2Y_MTX_10 -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_POS (4U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_10_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_10_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_10_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_10_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11 DSP2_MISC_RG_DISP_R2Y_MTX_11 -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_POS (16U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_11_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_11_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_11_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_11_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L DSP2_MISC_RG_DISP_R2Y_MTX_12_L -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_POS (28U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_LEN (4U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_L_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_L_POS)) - -/* 0x190 : disp_rgb2yuv_config_4 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_4_OFFSET (0x190) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U DSP2_MISC_RG_DISP_R2Y_MTX_12_U -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_LEN (8U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_12_U_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_12_U_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20 DSP2_MISC_RG_DISP_R2Y_MTX_20 -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_POS (8U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_20_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_20_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_20_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_20_POS)) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21 DSP2_MISC_RG_DISP_R2Y_MTX_21 -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_POS (20U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_21_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_21_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_21_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_21_POS)) - -/* 0x194 : disp_rgb2yuv_config_5 */ -#define DSP2_MISC_DISP_RGB2YUV_CONFIG_5_OFFSET (0x194) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22 DSP2_MISC_RG_DISP_R2Y_MTX_22 -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_POS (0U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_LEN (12U) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_MSK (((1U << DSP2_MISC_RG_DISP_R2Y_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_22_POS) -#define DSP2_MISC_RG_DISP_R2Y_MTX_22_UMSK (~(((1U << DSP2_MISC_RG_DISP_R2Y_MTX_22_LEN) - 1) << DSP2_MISC_RG_DISP_R2Y_MTX_22_POS)) - -/* 0x1C0 : cropA_hsync */ -#define DSP2_MISC_CROPA_HSYNC_OFFSET (0x1C0) -#define DSP2_MISC_REG_CROPA_HSYNC_START DSP2_MISC_REG_CROPA_HSYNC_START -#define DSP2_MISC_REG_CROPA_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPA_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPA_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPA_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPA_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPA_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPA_HSYNC_END DSP2_MISC_REG_CROPA_HSYNC_END -#define DSP2_MISC_REG_CROPA_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPA_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPA_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPA_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPA_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPA_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_HSYNC_END_POS)) - -/* 0x1C4 : cropA_vsync */ -#define DSP2_MISC_CROPA_VSYNC_OFFSET (0x1C4) -#define DSP2_MISC_REG_CROPA_VSYNC_START DSP2_MISC_REG_CROPA_VSYNC_START -#define DSP2_MISC_REG_CROPA_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPA_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPA_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPA_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPA_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPA_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPA_VSYNC_END DSP2_MISC_REG_CROPA_VSYNC_END -#define DSP2_MISC_REG_CROPA_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPA_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPA_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPA_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPA_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPA_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPA_VSYNC_END_POS)) - -/* 0x1C8 : cropB_hsync */ -#define DSP2_MISC_CROPB_HSYNC_OFFSET (0x1C8) -#define DSP2_MISC_REG_CROPB_HSYNC_START DSP2_MISC_REG_CROPB_HSYNC_START -#define DSP2_MISC_REG_CROPB_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPB_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPB_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPB_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPB_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPB_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPB_HSYNC_END DSP2_MISC_REG_CROPB_HSYNC_END -#define DSP2_MISC_REG_CROPB_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPB_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPB_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPB_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPB_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPB_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_HSYNC_END_POS)) - -/* 0x1CC : cropB_vsync */ -#define DSP2_MISC_CROPB_VSYNC_OFFSET (0x1CC) -#define DSP2_MISC_REG_CROPB_VSYNC_START DSP2_MISC_REG_CROPB_VSYNC_START -#define DSP2_MISC_REG_CROPB_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPB_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPB_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPB_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPB_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPB_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPB_VSYNC_END DSP2_MISC_REG_CROPB_VSYNC_END -#define DSP2_MISC_REG_CROPB_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPB_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPB_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPB_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPB_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPB_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPB_VSYNC_END_POS)) - -/* 0x1D0 : cropC_hsync */ -#define DSP2_MISC_CROPC_HSYNC_OFFSET (0x1D0) -#define DSP2_MISC_REG_CROPC_HSYNC_START DSP2_MISC_REG_CROPC_HSYNC_START -#define DSP2_MISC_REG_CROPC_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPC_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPC_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPC_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPC_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPC_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPC_HSYNC_END DSP2_MISC_REG_CROPC_HSYNC_END -#define DSP2_MISC_REG_CROPC_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPC_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPC_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPC_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPC_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPC_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_HSYNC_END_POS)) - -/* 0x1D4 : cropC_vsync */ -#define DSP2_MISC_CROPC_VSYNC_OFFSET (0x1D4) -#define DSP2_MISC_REG_CROPC_VSYNC_START DSP2_MISC_REG_CROPC_VSYNC_START -#define DSP2_MISC_REG_CROPC_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPC_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPC_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPC_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPC_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPC_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPC_VSYNC_END DSP2_MISC_REG_CROPC_VSYNC_END -#define DSP2_MISC_REG_CROPC_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPC_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPC_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPC_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPC_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPC_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPC_VSYNC_END_POS)) - -/* 0x1D8 : cropD_hsync */ -#define DSP2_MISC_CROPD_HSYNC_OFFSET (0x1D8) -#define DSP2_MISC_REG_CROPD_HSYNC_START DSP2_MISC_REG_CROPD_HSYNC_START -#define DSP2_MISC_REG_CROPD_HSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPD_HSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPD_HSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPD_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_START_POS) -#define DSP2_MISC_REG_CROPD_HSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPD_HSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_START_POS)) -#define DSP2_MISC_REG_CROPD_HSYNC_END DSP2_MISC_REG_CROPD_HSYNC_END -#define DSP2_MISC_REG_CROPD_HSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPD_HSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPD_HSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPD_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_END_POS) -#define DSP2_MISC_REG_CROPD_HSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPD_HSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_HSYNC_END_POS)) - -/* 0x1DC : cropD_vsync */ -#define DSP2_MISC_CROPD_VSYNC_OFFSET (0x1DC) -#define DSP2_MISC_REG_CROPD_VSYNC_START DSP2_MISC_REG_CROPD_VSYNC_START -#define DSP2_MISC_REG_CROPD_VSYNC_START_POS (0U) -#define DSP2_MISC_REG_CROPD_VSYNC_START_LEN (16U) -#define DSP2_MISC_REG_CROPD_VSYNC_START_MSK (((1U << DSP2_MISC_REG_CROPD_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_START_POS) -#define DSP2_MISC_REG_CROPD_VSYNC_START_UMSK (~(((1U << DSP2_MISC_REG_CROPD_VSYNC_START_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_START_POS)) -#define DSP2_MISC_REG_CROPD_VSYNC_END DSP2_MISC_REG_CROPD_VSYNC_END -#define DSP2_MISC_REG_CROPD_VSYNC_END_POS (16U) -#define DSP2_MISC_REG_CROPD_VSYNC_END_LEN (16U) -#define DSP2_MISC_REG_CROPD_VSYNC_END_MSK (((1U << DSP2_MISC_REG_CROPD_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_END_POS) -#define DSP2_MISC_REG_CROPD_VSYNC_END_UMSK (~(((1U << DSP2_MISC_REG_CROPD_VSYNC_END_LEN) - 1) << DSP2_MISC_REG_CROPD_VSYNC_END_POS)) - -/* 0x1E0 : crop_enable */ -#define DSP2_MISC_CROP_ENABLE_OFFSET (0x1E0) -#define DSP2_MISC_REG_CROPA_ENABLE DSP2_MISC_REG_CROPA_ENABLE -#define DSP2_MISC_REG_CROPA_ENABLE_POS (0U) -#define DSP2_MISC_REG_CROPA_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPA_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPA_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPA_ENABLE_POS) -#define DSP2_MISC_REG_CROPA_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPA_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPA_ENABLE_POS)) -#define DSP2_MISC_REG_CROPB_ENABLE DSP2_MISC_REG_CROPB_ENABLE -#define DSP2_MISC_REG_CROPB_ENABLE_POS (1U) -#define DSP2_MISC_REG_CROPB_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPB_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPB_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPB_ENABLE_POS) -#define DSP2_MISC_REG_CROPB_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPB_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPB_ENABLE_POS)) -#define DSP2_MISC_REG_CROPC_ENABLE DSP2_MISC_REG_CROPC_ENABLE -#define DSP2_MISC_REG_CROPC_ENABLE_POS (2U) -#define DSP2_MISC_REG_CROPC_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPC_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPC_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPC_ENABLE_POS) -#define DSP2_MISC_REG_CROPC_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPC_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPC_ENABLE_POS)) -#define DSP2_MISC_REG_CROPD_ENABLE DSP2_MISC_REG_CROPD_ENABLE -#define DSP2_MISC_REG_CROPD_ENABLE_POS (3U) -#define DSP2_MISC_REG_CROPD_ENABLE_LEN (1U) -#define DSP2_MISC_REG_CROPD_ENABLE_MSK (((1U << DSP2_MISC_REG_CROPD_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPD_ENABLE_POS) -#define DSP2_MISC_REG_CROPD_ENABLE_UMSK (~(((1U << DSP2_MISC_REG_CROPD_ENABLE_LEN) - 1) << DSP2_MISC_REG_CROPD_ENABLE_POS)) - -/* 0x1FC : disp_gma_cfg */ -#define DSP2_MISC_DISP_GMA_CFG_OFFSET (0x1FC) -#define DSP2_MISC_REG_DP_GMA_CH0_EN DSP2_MISC_REG_DP_GMA_CH0_EN -#define DSP2_MISC_REG_DP_GMA_CH0_EN_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CH0_EN_LEN (1U) -#define DSP2_MISC_REG_DP_GMA_CH0_EN_MSK (((1U << DSP2_MISC_REG_DP_GMA_CH0_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH0_EN_POS) -#define DSP2_MISC_REG_DP_GMA_CH0_EN_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CH0_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH0_EN_POS)) -#define DSP2_MISC_REG_DP_GMA_CH1_EN DSP2_MISC_REG_DP_GMA_CH1_EN -#define DSP2_MISC_REG_DP_GMA_CH1_EN_POS (1U) -#define DSP2_MISC_REG_DP_GMA_CH1_EN_LEN (1U) -#define DSP2_MISC_REG_DP_GMA_CH1_EN_MSK (((1U << DSP2_MISC_REG_DP_GMA_CH1_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH1_EN_POS) -#define DSP2_MISC_REG_DP_GMA_CH1_EN_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CH1_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH1_EN_POS)) -#define DSP2_MISC_REG_DP_GMA_CH2_EN DSP2_MISC_REG_DP_GMA_CH2_EN -#define DSP2_MISC_REG_DP_GMA_CH2_EN_POS (2U) -#define DSP2_MISC_REG_DP_GMA_CH2_EN_LEN (1U) -#define DSP2_MISC_REG_DP_GMA_CH2_EN_MSK (((1U << DSP2_MISC_REG_DP_GMA_CH2_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH2_EN_POS) -#define DSP2_MISC_REG_DP_GMA_CH2_EN_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CH2_EN_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CH2_EN_POS)) - -/* 0x200 : disp_gma_curve_00 */ -#define DSP2_MISC_DISP_GMA_CURVE_00_OFFSET (0x200) -#define DSP2_MISC_REG_DP_GMA_CURVE_00 DSP2_MISC_REG_DP_GMA_CURVE_00 -#define DSP2_MISC_REG_DP_GMA_CURVE_00_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_00_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_00_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_00_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_00_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_00_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_00_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_00_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_01 DSP2_MISC_REG_DP_GMA_CURVE_01 -#define DSP2_MISC_REG_DP_GMA_CURVE_01_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_01_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_01_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_01_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_01_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_01_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_01_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_01_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_02 DSP2_MISC_REG_DP_GMA_CURVE_02 -#define DSP2_MISC_REG_DP_GMA_CURVE_02_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_02_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_02_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_02_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_02_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_02_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_02_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_02_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_03 DSP2_MISC_REG_DP_GMA_CURVE_03 -#define DSP2_MISC_REG_DP_GMA_CURVE_03_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_03_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_03_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_03_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_03_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_03_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_03_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_03_POS)) - -/* 0x204 : disp_gma_curve_04 */ -#define DSP2_MISC_DISP_GMA_CURVE_04_OFFSET (0x204) -#define DSP2_MISC_REG_DP_GMA_CURVE_04 DSP2_MISC_REG_DP_GMA_CURVE_04 -#define DSP2_MISC_REG_DP_GMA_CURVE_04_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_04_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_04_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_04_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_04_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_04_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_04_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_04_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_05 DSP2_MISC_REG_DP_GMA_CURVE_05 -#define DSP2_MISC_REG_DP_GMA_CURVE_05_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_05_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_05_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_05_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_05_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_05_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_05_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_05_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_06 DSP2_MISC_REG_DP_GMA_CURVE_06 -#define DSP2_MISC_REG_DP_GMA_CURVE_06_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_06_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_06_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_06_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_06_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_06_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_06_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_06_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_07 DSP2_MISC_REG_DP_GMA_CURVE_07 -#define DSP2_MISC_REG_DP_GMA_CURVE_07_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_07_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_07_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_07_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_07_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_07_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_07_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_07_POS)) - -/* 0x208 : disp_gma_curve_08 */ -#define DSP2_MISC_DISP_GMA_CURVE_08_OFFSET (0x208) -#define DSP2_MISC_REG_DP_GMA_CURVE_08 DSP2_MISC_REG_DP_GMA_CURVE_08 -#define DSP2_MISC_REG_DP_GMA_CURVE_08_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_08_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_08_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_08_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_08_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_08_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_08_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_08_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_09 DSP2_MISC_REG_DP_GMA_CURVE_09 -#define DSP2_MISC_REG_DP_GMA_CURVE_09_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_09_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_09_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_09_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_09_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_09_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_09_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_09_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A DSP2_MISC_REG_DP_GMA_CURVE_0A -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B DSP2_MISC_REG_DP_GMA_CURVE_0B -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0B_POS)) - -/* 0x20C : disp_gma_curve_0c */ -#define DSP2_MISC_DISP_GMA_CURVE_0C_OFFSET (0x20C) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C DSP2_MISC_REG_DP_GMA_CURVE_0C -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D DSP2_MISC_REG_DP_GMA_CURVE_0D -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E DSP2_MISC_REG_DP_GMA_CURVE_0E -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F DSP2_MISC_REG_DP_GMA_CURVE_0F -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_0F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_0F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_0F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_0F_POS)) - -/* 0x210 : disp_gma_curve_10 */ -#define DSP2_MISC_DISP_GMA_CURVE_10_OFFSET (0x210) -#define DSP2_MISC_REG_DP_GMA_CURVE_10 DSP2_MISC_REG_DP_GMA_CURVE_10 -#define DSP2_MISC_REG_DP_GMA_CURVE_10_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_10_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_10_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_10_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_10_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_10_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_10_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_10_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_11 DSP2_MISC_REG_DP_GMA_CURVE_11 -#define DSP2_MISC_REG_DP_GMA_CURVE_11_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_11_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_11_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_11_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_11_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_11_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_11_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_11_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_12 DSP2_MISC_REG_DP_GMA_CURVE_12 -#define DSP2_MISC_REG_DP_GMA_CURVE_12_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_12_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_12_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_12_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_12_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_12_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_12_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_12_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_13 DSP2_MISC_REG_DP_GMA_CURVE_13 -#define DSP2_MISC_REG_DP_GMA_CURVE_13_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_13_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_13_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_13_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_13_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_13_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_13_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_13_POS)) - -/* 0x214 : disp_gma_curve_14 */ -#define DSP2_MISC_DISP_GMA_CURVE_14_OFFSET (0x214) -#define DSP2_MISC_REG_DP_GMA_CURVE_14 DSP2_MISC_REG_DP_GMA_CURVE_14 -#define DSP2_MISC_REG_DP_GMA_CURVE_14_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_14_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_14_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_14_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_14_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_14_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_14_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_14_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_15 DSP2_MISC_REG_DP_GMA_CURVE_15 -#define DSP2_MISC_REG_DP_GMA_CURVE_15_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_15_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_15_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_15_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_15_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_15_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_15_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_15_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_16 DSP2_MISC_REG_DP_GMA_CURVE_16 -#define DSP2_MISC_REG_DP_GMA_CURVE_16_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_16_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_16_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_16_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_16_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_16_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_16_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_16_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_17 DSP2_MISC_REG_DP_GMA_CURVE_17 -#define DSP2_MISC_REG_DP_GMA_CURVE_17_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_17_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_17_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_17_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_17_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_17_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_17_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_17_POS)) - -/* 0x218 : disp_gma_curve_18 */ -#define DSP2_MISC_DISP_GMA_CURVE_18_OFFSET (0x218) -#define DSP2_MISC_REG_DP_GMA_CURVE_18 DSP2_MISC_REG_DP_GMA_CURVE_18 -#define DSP2_MISC_REG_DP_GMA_CURVE_18_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_18_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_18_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_18_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_18_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_18_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_18_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_18_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_19 DSP2_MISC_REG_DP_GMA_CURVE_19 -#define DSP2_MISC_REG_DP_GMA_CURVE_19_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_19_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_19_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_19_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_19_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_19_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_19_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_19_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A DSP2_MISC_REG_DP_GMA_CURVE_1A -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B DSP2_MISC_REG_DP_GMA_CURVE_1B -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1B_POS)) - -/* 0x21C : disp_gma_curve_1c */ -#define DSP2_MISC_DISP_GMA_CURVE_1C_OFFSET (0x21C) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C DSP2_MISC_REG_DP_GMA_CURVE_1C -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D DSP2_MISC_REG_DP_GMA_CURVE_1D -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E DSP2_MISC_REG_DP_GMA_CURVE_1E -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F DSP2_MISC_REG_DP_GMA_CURVE_1F -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_1F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_1F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_1F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_1F_POS)) - -/* 0x220 : disp_gma_curve_20 */ -#define DSP2_MISC_DISP_GMA_CURVE_20_OFFSET (0x220) -#define DSP2_MISC_REG_DP_GMA_CURVE_20 DSP2_MISC_REG_DP_GMA_CURVE_20 -#define DSP2_MISC_REG_DP_GMA_CURVE_20_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_20_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_20_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_20_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_20_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_20_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_20_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_20_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_21 DSP2_MISC_REG_DP_GMA_CURVE_21 -#define DSP2_MISC_REG_DP_GMA_CURVE_21_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_21_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_21_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_21_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_21_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_21_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_21_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_21_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_22 DSP2_MISC_REG_DP_GMA_CURVE_22 -#define DSP2_MISC_REG_DP_GMA_CURVE_22_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_22_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_22_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_22_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_22_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_22_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_22_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_22_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_23 DSP2_MISC_REG_DP_GMA_CURVE_23 -#define DSP2_MISC_REG_DP_GMA_CURVE_23_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_23_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_23_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_23_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_23_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_23_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_23_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_23_POS)) - -/* 0x224 : disp_gma_curve_24 */ -#define DSP2_MISC_DISP_GMA_CURVE_24_OFFSET (0x224) -#define DSP2_MISC_REG_DP_GMA_CURVE_24 DSP2_MISC_REG_DP_GMA_CURVE_24 -#define DSP2_MISC_REG_DP_GMA_CURVE_24_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_24_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_24_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_24_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_24_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_24_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_24_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_24_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_25 DSP2_MISC_REG_DP_GMA_CURVE_25 -#define DSP2_MISC_REG_DP_GMA_CURVE_25_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_25_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_25_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_25_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_25_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_25_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_25_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_25_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_26 DSP2_MISC_REG_DP_GMA_CURVE_26 -#define DSP2_MISC_REG_DP_GMA_CURVE_26_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_26_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_26_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_26_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_26_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_26_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_26_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_26_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_27 DSP2_MISC_REG_DP_GMA_CURVE_27 -#define DSP2_MISC_REG_DP_GMA_CURVE_27_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_27_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_27_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_27_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_27_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_27_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_27_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_27_POS)) - -/* 0x228 : disp_gma_curve_28 */ -#define DSP2_MISC_DISP_GMA_CURVE_28_OFFSET (0x228) -#define DSP2_MISC_REG_DP_GMA_CURVE_28 DSP2_MISC_REG_DP_GMA_CURVE_28 -#define DSP2_MISC_REG_DP_GMA_CURVE_28_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_28_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_28_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_28_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_28_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_28_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_28_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_28_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_29 DSP2_MISC_REG_DP_GMA_CURVE_29 -#define DSP2_MISC_REG_DP_GMA_CURVE_29_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_29_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_29_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_29_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_29_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_29_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_29_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_29_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A DSP2_MISC_REG_DP_GMA_CURVE_2A -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B DSP2_MISC_REG_DP_GMA_CURVE_2B -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2B_POS)) - -/* 0x22C : disp_gma_curve_2c */ -#define DSP2_MISC_DISP_GMA_CURVE_2C_OFFSET (0x22C) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C DSP2_MISC_REG_DP_GMA_CURVE_2C -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D DSP2_MISC_REG_DP_GMA_CURVE_2D -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E DSP2_MISC_REG_DP_GMA_CURVE_2E -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F DSP2_MISC_REG_DP_GMA_CURVE_2F -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_2F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_2F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_2F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_2F_POS)) - -/* 0x230 : disp_gma_curve_30 */ -#define DSP2_MISC_DISP_GMA_CURVE_30_OFFSET (0x230) -#define DSP2_MISC_REG_DP_GMA_CURVE_30 DSP2_MISC_REG_DP_GMA_CURVE_30 -#define DSP2_MISC_REG_DP_GMA_CURVE_30_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_30_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_30_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_30_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_30_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_30_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_30_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_30_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_31 DSP2_MISC_REG_DP_GMA_CURVE_31 -#define DSP2_MISC_REG_DP_GMA_CURVE_31_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_31_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_31_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_31_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_31_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_31_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_31_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_31_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_32 DSP2_MISC_REG_DP_GMA_CURVE_32 -#define DSP2_MISC_REG_DP_GMA_CURVE_32_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_32_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_32_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_32_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_32_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_32_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_32_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_32_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_33 DSP2_MISC_REG_DP_GMA_CURVE_33 -#define DSP2_MISC_REG_DP_GMA_CURVE_33_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_33_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_33_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_33_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_33_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_33_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_33_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_33_POS)) - -/* 0x234 : disp_gma_curve_34 */ -#define DSP2_MISC_DISP_GMA_CURVE_34_OFFSET (0x234) -#define DSP2_MISC_REG_DP_GMA_CURVE_34 DSP2_MISC_REG_DP_GMA_CURVE_34 -#define DSP2_MISC_REG_DP_GMA_CURVE_34_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_34_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_34_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_34_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_34_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_34_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_34_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_34_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_35 DSP2_MISC_REG_DP_GMA_CURVE_35 -#define DSP2_MISC_REG_DP_GMA_CURVE_35_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_35_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_35_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_35_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_35_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_35_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_35_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_35_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_36 DSP2_MISC_REG_DP_GMA_CURVE_36 -#define DSP2_MISC_REG_DP_GMA_CURVE_36_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_36_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_36_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_36_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_36_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_36_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_36_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_36_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_37 DSP2_MISC_REG_DP_GMA_CURVE_37 -#define DSP2_MISC_REG_DP_GMA_CURVE_37_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_37_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_37_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_37_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_37_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_37_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_37_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_37_POS)) - -/* 0x238 : disp_gma_curve_38 */ -#define DSP2_MISC_DISP_GMA_CURVE_38_OFFSET (0x238) -#define DSP2_MISC_REG_DP_GMA_CURVE_38 DSP2_MISC_REG_DP_GMA_CURVE_38 -#define DSP2_MISC_REG_DP_GMA_CURVE_38_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_38_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_38_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_38_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_38_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_38_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_38_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_38_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_39 DSP2_MISC_REG_DP_GMA_CURVE_39 -#define DSP2_MISC_REG_DP_GMA_CURVE_39_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_39_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_39_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_39_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_39_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_39_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_39_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_39_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A DSP2_MISC_REG_DP_GMA_CURVE_3A -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B DSP2_MISC_REG_DP_GMA_CURVE_3B -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3B_POS)) - -/* 0x23C : disp_gma_curve_3c */ -#define DSP2_MISC_DISP_GMA_CURVE_3C_OFFSET (0x23C) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C DSP2_MISC_REG_DP_GMA_CURVE_3C -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D DSP2_MISC_REG_DP_GMA_CURVE_3D -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E DSP2_MISC_REG_DP_GMA_CURVE_3E -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F DSP2_MISC_REG_DP_GMA_CURVE_3F -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_3F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_3F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_3F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_3F_POS)) - -/* 0x240 : disp_gma_curve_40 */ -#define DSP2_MISC_DISP_GMA_CURVE_40_OFFSET (0x240) -#define DSP2_MISC_REG_DP_GMA_CURVE_40 DSP2_MISC_REG_DP_GMA_CURVE_40 -#define DSP2_MISC_REG_DP_GMA_CURVE_40_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_40_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_40_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_40_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_40_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_40_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_40_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_40_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_41 DSP2_MISC_REG_DP_GMA_CURVE_41 -#define DSP2_MISC_REG_DP_GMA_CURVE_41_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_41_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_41_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_41_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_41_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_41_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_41_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_41_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_42 DSP2_MISC_REG_DP_GMA_CURVE_42 -#define DSP2_MISC_REG_DP_GMA_CURVE_42_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_42_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_42_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_42_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_42_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_42_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_42_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_42_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_43 DSP2_MISC_REG_DP_GMA_CURVE_43 -#define DSP2_MISC_REG_DP_GMA_CURVE_43_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_43_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_43_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_43_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_43_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_43_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_43_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_43_POS)) - -/* 0x244 : disp_gma_curve_44 */ -#define DSP2_MISC_DISP_GMA_CURVE_44_OFFSET (0x244) -#define DSP2_MISC_REG_DP_GMA_CURVE_44 DSP2_MISC_REG_DP_GMA_CURVE_44 -#define DSP2_MISC_REG_DP_GMA_CURVE_44_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_44_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_44_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_44_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_44_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_44_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_44_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_44_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_45 DSP2_MISC_REG_DP_GMA_CURVE_45 -#define DSP2_MISC_REG_DP_GMA_CURVE_45_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_45_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_45_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_45_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_45_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_45_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_45_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_45_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_46 DSP2_MISC_REG_DP_GMA_CURVE_46 -#define DSP2_MISC_REG_DP_GMA_CURVE_46_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_46_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_46_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_46_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_46_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_46_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_46_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_46_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_47 DSP2_MISC_REG_DP_GMA_CURVE_47 -#define DSP2_MISC_REG_DP_GMA_CURVE_47_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_47_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_47_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_47_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_47_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_47_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_47_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_47_POS)) - -/* 0x248 : disp_gma_curve_48 */ -#define DSP2_MISC_DISP_GMA_CURVE_48_OFFSET (0x248) -#define DSP2_MISC_REG_DP_GMA_CURVE_48 DSP2_MISC_REG_DP_GMA_CURVE_48 -#define DSP2_MISC_REG_DP_GMA_CURVE_48_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_48_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_48_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_48_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_48_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_48_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_48_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_48_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_49 DSP2_MISC_REG_DP_GMA_CURVE_49 -#define DSP2_MISC_REG_DP_GMA_CURVE_49_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_49_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_49_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_49_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_49_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_49_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_49_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_49_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A DSP2_MISC_REG_DP_GMA_CURVE_4A -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B DSP2_MISC_REG_DP_GMA_CURVE_4B -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4B_POS)) - -/* 0x24C : disp_gma_curve_4c */ -#define DSP2_MISC_DISP_GMA_CURVE_4C_OFFSET (0x24C) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C DSP2_MISC_REG_DP_GMA_CURVE_4C -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D DSP2_MISC_REG_DP_GMA_CURVE_4D -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E DSP2_MISC_REG_DP_GMA_CURVE_4E -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F DSP2_MISC_REG_DP_GMA_CURVE_4F -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_4F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_4F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_4F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_4F_POS)) - -/* 0x250 : disp_gma_curve_50 */ -#define DSP2_MISC_DISP_GMA_CURVE_50_OFFSET (0x250) -#define DSP2_MISC_REG_DP_GMA_CURVE_50 DSP2_MISC_REG_DP_GMA_CURVE_50 -#define DSP2_MISC_REG_DP_GMA_CURVE_50_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_50_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_50_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_50_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_50_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_50_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_50_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_50_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_51 DSP2_MISC_REG_DP_GMA_CURVE_51 -#define DSP2_MISC_REG_DP_GMA_CURVE_51_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_51_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_51_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_51_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_51_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_51_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_51_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_51_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_52 DSP2_MISC_REG_DP_GMA_CURVE_52 -#define DSP2_MISC_REG_DP_GMA_CURVE_52_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_52_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_52_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_52_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_52_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_52_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_52_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_52_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_53 DSP2_MISC_REG_DP_GMA_CURVE_53 -#define DSP2_MISC_REG_DP_GMA_CURVE_53_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_53_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_53_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_53_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_53_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_53_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_53_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_53_POS)) - -/* 0x254 : disp_gma_curve_54 */ -#define DSP2_MISC_DISP_GMA_CURVE_54_OFFSET (0x254) -#define DSP2_MISC_REG_DP_GMA_CURVE_54 DSP2_MISC_REG_DP_GMA_CURVE_54 -#define DSP2_MISC_REG_DP_GMA_CURVE_54_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_54_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_54_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_54_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_54_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_54_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_54_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_54_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_55 DSP2_MISC_REG_DP_GMA_CURVE_55 -#define DSP2_MISC_REG_DP_GMA_CURVE_55_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_55_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_55_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_55_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_55_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_55_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_55_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_55_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_56 DSP2_MISC_REG_DP_GMA_CURVE_56 -#define DSP2_MISC_REG_DP_GMA_CURVE_56_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_56_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_56_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_56_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_56_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_56_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_56_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_56_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_57 DSP2_MISC_REG_DP_GMA_CURVE_57 -#define DSP2_MISC_REG_DP_GMA_CURVE_57_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_57_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_57_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_57_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_57_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_57_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_57_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_57_POS)) - -/* 0x258 : disp_gma_curve_58 */ -#define DSP2_MISC_DISP_GMA_CURVE_58_OFFSET (0x258) -#define DSP2_MISC_REG_DP_GMA_CURVE_58 DSP2_MISC_REG_DP_GMA_CURVE_58 -#define DSP2_MISC_REG_DP_GMA_CURVE_58_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_58_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_58_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_58_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_58_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_58_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_58_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_58_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_59 DSP2_MISC_REG_DP_GMA_CURVE_59 -#define DSP2_MISC_REG_DP_GMA_CURVE_59_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_59_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_59_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_59_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_59_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_59_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_59_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_59_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A DSP2_MISC_REG_DP_GMA_CURVE_5A -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B DSP2_MISC_REG_DP_GMA_CURVE_5B -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5B_POS)) - -/* 0x25C : disp_gma_curve_5c */ -#define DSP2_MISC_DISP_GMA_CURVE_5C_OFFSET (0x25C) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C DSP2_MISC_REG_DP_GMA_CURVE_5C -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D DSP2_MISC_REG_DP_GMA_CURVE_5D -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E DSP2_MISC_REG_DP_GMA_CURVE_5E -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F DSP2_MISC_REG_DP_GMA_CURVE_5F -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_5F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_5F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_5F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_5F_POS)) - -/* 0x260 : disp_gma_curve_60 */ -#define DSP2_MISC_DISP_GMA_CURVE_60_OFFSET (0x260) -#define DSP2_MISC_REG_DP_GMA_CURVE_60 DSP2_MISC_REG_DP_GMA_CURVE_60 -#define DSP2_MISC_REG_DP_GMA_CURVE_60_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_60_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_60_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_60_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_60_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_60_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_60_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_60_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_61 DSP2_MISC_REG_DP_GMA_CURVE_61 -#define DSP2_MISC_REG_DP_GMA_CURVE_61_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_61_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_61_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_61_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_61_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_61_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_61_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_61_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_62 DSP2_MISC_REG_DP_GMA_CURVE_62 -#define DSP2_MISC_REG_DP_GMA_CURVE_62_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_62_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_62_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_62_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_62_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_62_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_62_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_62_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_63 DSP2_MISC_REG_DP_GMA_CURVE_63 -#define DSP2_MISC_REG_DP_GMA_CURVE_63_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_63_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_63_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_63_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_63_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_63_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_63_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_63_POS)) - -/* 0x264 : disp_gma_curve_64 */ -#define DSP2_MISC_DISP_GMA_CURVE_64_OFFSET (0x264) -#define DSP2_MISC_REG_DP_GMA_CURVE_64 DSP2_MISC_REG_DP_GMA_CURVE_64 -#define DSP2_MISC_REG_DP_GMA_CURVE_64_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_64_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_64_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_64_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_64_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_64_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_64_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_64_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_65 DSP2_MISC_REG_DP_GMA_CURVE_65 -#define DSP2_MISC_REG_DP_GMA_CURVE_65_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_65_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_65_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_65_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_65_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_65_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_65_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_65_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_66 DSP2_MISC_REG_DP_GMA_CURVE_66 -#define DSP2_MISC_REG_DP_GMA_CURVE_66_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_66_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_66_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_66_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_66_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_66_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_66_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_66_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_67 DSP2_MISC_REG_DP_GMA_CURVE_67 -#define DSP2_MISC_REG_DP_GMA_CURVE_67_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_67_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_67_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_67_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_67_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_67_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_67_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_67_POS)) - -/* 0x268 : disp_gma_curve_68 */ -#define DSP2_MISC_DISP_GMA_CURVE_68_OFFSET (0x268) -#define DSP2_MISC_REG_DP_GMA_CURVE_68 DSP2_MISC_REG_DP_GMA_CURVE_68 -#define DSP2_MISC_REG_DP_GMA_CURVE_68_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_68_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_68_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_68_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_68_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_68_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_68_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_68_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_69 DSP2_MISC_REG_DP_GMA_CURVE_69 -#define DSP2_MISC_REG_DP_GMA_CURVE_69_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_69_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_69_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_69_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_69_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_69_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_69_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_69_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A DSP2_MISC_REG_DP_GMA_CURVE_6A -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B DSP2_MISC_REG_DP_GMA_CURVE_6B -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6B_POS)) - -/* 0x26C : disp_gma_curve_6c */ -#define DSP2_MISC_DISP_GMA_CURVE_6C_OFFSET (0x26C) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C DSP2_MISC_REG_DP_GMA_CURVE_6C -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D DSP2_MISC_REG_DP_GMA_CURVE_6D -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E DSP2_MISC_REG_DP_GMA_CURVE_6E -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F DSP2_MISC_REG_DP_GMA_CURVE_6F -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_6F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_6F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_6F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_6F_POS)) - -/* 0x270 : disp_gma_curve_70 */ -#define DSP2_MISC_DISP_GMA_CURVE_70_OFFSET (0x270) -#define DSP2_MISC_REG_DP_GMA_CURVE_70 DSP2_MISC_REG_DP_GMA_CURVE_70 -#define DSP2_MISC_REG_DP_GMA_CURVE_70_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_70_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_70_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_70_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_70_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_70_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_70_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_70_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_71 DSP2_MISC_REG_DP_GMA_CURVE_71 -#define DSP2_MISC_REG_DP_GMA_CURVE_71_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_71_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_71_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_71_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_71_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_71_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_71_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_71_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_72 DSP2_MISC_REG_DP_GMA_CURVE_72 -#define DSP2_MISC_REG_DP_GMA_CURVE_72_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_72_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_72_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_72_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_72_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_72_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_72_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_72_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_73 DSP2_MISC_REG_DP_GMA_CURVE_73 -#define DSP2_MISC_REG_DP_GMA_CURVE_73_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_73_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_73_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_73_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_73_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_73_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_73_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_73_POS)) - -/* 0x274 : disp_gma_curve_74 */ -#define DSP2_MISC_DISP_GMA_CURVE_74_OFFSET (0x274) -#define DSP2_MISC_REG_DP_GMA_CURVE_74 DSP2_MISC_REG_DP_GMA_CURVE_74 -#define DSP2_MISC_REG_DP_GMA_CURVE_74_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_74_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_74_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_74_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_74_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_74_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_74_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_74_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_75 DSP2_MISC_REG_DP_GMA_CURVE_75 -#define DSP2_MISC_REG_DP_GMA_CURVE_75_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_75_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_75_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_75_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_75_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_75_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_75_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_75_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_76 DSP2_MISC_REG_DP_GMA_CURVE_76 -#define DSP2_MISC_REG_DP_GMA_CURVE_76_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_76_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_76_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_76_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_76_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_76_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_76_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_76_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_77 DSP2_MISC_REG_DP_GMA_CURVE_77 -#define DSP2_MISC_REG_DP_GMA_CURVE_77_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_77_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_77_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_77_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_77_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_77_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_77_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_77_POS)) - -/* 0x278 : disp_gma_curve_78 */ -#define DSP2_MISC_DISP_GMA_CURVE_78_OFFSET (0x278) -#define DSP2_MISC_REG_DP_GMA_CURVE_78 DSP2_MISC_REG_DP_GMA_CURVE_78 -#define DSP2_MISC_REG_DP_GMA_CURVE_78_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_78_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_78_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_78_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_78_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_78_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_78_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_78_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_79 DSP2_MISC_REG_DP_GMA_CURVE_79 -#define DSP2_MISC_REG_DP_GMA_CURVE_79_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_79_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_79_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_79_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_79_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_79_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_79_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_79_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A DSP2_MISC_REG_DP_GMA_CURVE_7A -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B DSP2_MISC_REG_DP_GMA_CURVE_7B -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7B_POS)) - -/* 0x27C : disp_gma_curve_7c */ -#define DSP2_MISC_DISP_GMA_CURVE_7C_OFFSET (0x27C) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C DSP2_MISC_REG_DP_GMA_CURVE_7C -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D DSP2_MISC_REG_DP_GMA_CURVE_7D -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E DSP2_MISC_REG_DP_GMA_CURVE_7E -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F DSP2_MISC_REG_DP_GMA_CURVE_7F -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_7F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_7F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_7F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_7F_POS)) - -/* 0x280 : disp_gma_curve_80 */ -#define DSP2_MISC_DISP_GMA_CURVE_80_OFFSET (0x280) -#define DSP2_MISC_REG_DP_GMA_CURVE_80 DSP2_MISC_REG_DP_GMA_CURVE_80 -#define DSP2_MISC_REG_DP_GMA_CURVE_80_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_80_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_80_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_80_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_80_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_80_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_80_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_80_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_81 DSP2_MISC_REG_DP_GMA_CURVE_81 -#define DSP2_MISC_REG_DP_GMA_CURVE_81_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_81_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_81_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_81_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_81_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_81_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_81_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_81_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_82 DSP2_MISC_REG_DP_GMA_CURVE_82 -#define DSP2_MISC_REG_DP_GMA_CURVE_82_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_82_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_82_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_82_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_82_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_82_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_82_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_82_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_83 DSP2_MISC_REG_DP_GMA_CURVE_83 -#define DSP2_MISC_REG_DP_GMA_CURVE_83_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_83_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_83_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_83_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_83_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_83_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_83_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_83_POS)) - -/* 0x284 : disp_gma_curve_84 */ -#define DSP2_MISC_DISP_GMA_CURVE_84_OFFSET (0x284) -#define DSP2_MISC_REG_DP_GMA_CURVE_84 DSP2_MISC_REG_DP_GMA_CURVE_84 -#define DSP2_MISC_REG_DP_GMA_CURVE_84_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_84_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_84_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_84_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_84_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_84_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_84_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_84_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_85 DSP2_MISC_REG_DP_GMA_CURVE_85 -#define DSP2_MISC_REG_DP_GMA_CURVE_85_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_85_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_85_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_85_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_85_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_85_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_85_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_85_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_86 DSP2_MISC_REG_DP_GMA_CURVE_86 -#define DSP2_MISC_REG_DP_GMA_CURVE_86_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_86_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_86_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_86_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_86_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_86_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_86_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_86_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_87 DSP2_MISC_REG_DP_GMA_CURVE_87 -#define DSP2_MISC_REG_DP_GMA_CURVE_87_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_87_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_87_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_87_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_87_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_87_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_87_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_87_POS)) - -/* 0x288 : disp_gma_curve_88 */ -#define DSP2_MISC_DISP_GMA_CURVE_88_OFFSET (0x288) -#define DSP2_MISC_REG_DP_GMA_CURVE_88 DSP2_MISC_REG_DP_GMA_CURVE_88 -#define DSP2_MISC_REG_DP_GMA_CURVE_88_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_88_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_88_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_88_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_88_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_88_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_88_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_88_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_89 DSP2_MISC_REG_DP_GMA_CURVE_89 -#define DSP2_MISC_REG_DP_GMA_CURVE_89_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_89_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_89_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_89_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_89_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_89_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_89_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_89_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A DSP2_MISC_REG_DP_GMA_CURVE_8A -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B DSP2_MISC_REG_DP_GMA_CURVE_8B -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8B_POS)) - -/* 0x28C : disp_gma_curve_8c */ -#define DSP2_MISC_DISP_GMA_CURVE_8C_OFFSET (0x28C) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C DSP2_MISC_REG_DP_GMA_CURVE_8C -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D DSP2_MISC_REG_DP_GMA_CURVE_8D -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E DSP2_MISC_REG_DP_GMA_CURVE_8E -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F DSP2_MISC_REG_DP_GMA_CURVE_8F -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_8F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_8F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_8F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_8F_POS)) - -/* 0x290 : disp_gma_curve_90 */ -#define DSP2_MISC_DISP_GMA_CURVE_90_OFFSET (0x290) -#define DSP2_MISC_REG_DP_GMA_CURVE_90 DSP2_MISC_REG_DP_GMA_CURVE_90 -#define DSP2_MISC_REG_DP_GMA_CURVE_90_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_90_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_90_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_90_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_90_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_90_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_90_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_90_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_91 DSP2_MISC_REG_DP_GMA_CURVE_91 -#define DSP2_MISC_REG_DP_GMA_CURVE_91_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_91_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_91_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_91_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_91_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_91_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_91_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_91_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_92 DSP2_MISC_REG_DP_GMA_CURVE_92 -#define DSP2_MISC_REG_DP_GMA_CURVE_92_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_92_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_92_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_92_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_92_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_92_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_92_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_92_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_93 DSP2_MISC_REG_DP_GMA_CURVE_93 -#define DSP2_MISC_REG_DP_GMA_CURVE_93_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_93_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_93_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_93_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_93_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_93_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_93_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_93_POS)) - -/* 0x294 : disp_gma_curve_94 */ -#define DSP2_MISC_DISP_GMA_CURVE_94_OFFSET (0x294) -#define DSP2_MISC_REG_DP_GMA_CURVE_94 DSP2_MISC_REG_DP_GMA_CURVE_94 -#define DSP2_MISC_REG_DP_GMA_CURVE_94_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_94_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_94_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_94_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_94_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_94_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_94_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_94_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_95 DSP2_MISC_REG_DP_GMA_CURVE_95 -#define DSP2_MISC_REG_DP_GMA_CURVE_95_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_95_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_95_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_95_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_95_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_95_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_95_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_95_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_96 DSP2_MISC_REG_DP_GMA_CURVE_96 -#define DSP2_MISC_REG_DP_GMA_CURVE_96_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_96_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_96_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_96_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_96_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_96_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_96_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_96_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_97 DSP2_MISC_REG_DP_GMA_CURVE_97 -#define DSP2_MISC_REG_DP_GMA_CURVE_97_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_97_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_97_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_97_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_97_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_97_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_97_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_97_POS)) - -/* 0x298 : disp_gma_curve_98 */ -#define DSP2_MISC_DISP_GMA_CURVE_98_OFFSET (0x298) -#define DSP2_MISC_REG_DP_GMA_CURVE_98 DSP2_MISC_REG_DP_GMA_CURVE_98 -#define DSP2_MISC_REG_DP_GMA_CURVE_98_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_98_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_98_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_98_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_98_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_98_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_98_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_98_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_99 DSP2_MISC_REG_DP_GMA_CURVE_99 -#define DSP2_MISC_REG_DP_GMA_CURVE_99_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_99_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_99_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_99_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_99_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_99_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_99_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_99_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A DSP2_MISC_REG_DP_GMA_CURVE_9A -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9A_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9A_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9A_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9A_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B DSP2_MISC_REG_DP_GMA_CURVE_9B -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9B_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9B_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9B_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9B_POS)) - -/* 0x29C : disp_gma_curve_9c */ -#define DSP2_MISC_DISP_GMA_CURVE_9C_OFFSET (0x29C) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C DSP2_MISC_REG_DP_GMA_CURVE_9C -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9C_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9C_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9C_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9C_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D DSP2_MISC_REG_DP_GMA_CURVE_9D -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9D_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9D_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9D_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9D_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E DSP2_MISC_REG_DP_GMA_CURVE_9E -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9E_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9E_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9E_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9E_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F DSP2_MISC_REG_DP_GMA_CURVE_9F -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_9F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9F_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_9F_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_9F_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_9F_POS)) - -/* 0x2A0 : disp_gma_curve_a0 */ -#define DSP2_MISC_DISP_GMA_CURVE_A0_OFFSET (0x2A0) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0 DSP2_MISC_REG_DP_GMA_CURVE_A0 -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1 DSP2_MISC_REG_DP_GMA_CURVE_A1 -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2 DSP2_MISC_REG_DP_GMA_CURVE_A2 -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3 DSP2_MISC_REG_DP_GMA_CURVE_A3 -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A3_POS)) - -/* 0x2A4 : disp_gma_curve_a4 */ -#define DSP2_MISC_DISP_GMA_CURVE_A4_OFFSET (0x2A4) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4 DSP2_MISC_REG_DP_GMA_CURVE_A4 -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5 DSP2_MISC_REG_DP_GMA_CURVE_A5 -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6 DSP2_MISC_REG_DP_GMA_CURVE_A6 -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7 DSP2_MISC_REG_DP_GMA_CURVE_A7 -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A7_POS)) - -/* 0x2A8 : disp_gma_curve_a8 */ -#define DSP2_MISC_DISP_GMA_CURVE_A8_OFFSET (0x2A8) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8 DSP2_MISC_REG_DP_GMA_CURVE_A8 -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9 DSP2_MISC_REG_DP_GMA_CURVE_A9 -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_A9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_A9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_A9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_A9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA DSP2_MISC_REG_DP_GMA_CURVE_AA -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB DSP2_MISC_REG_DP_GMA_CURVE_AB -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AB_POS)) - -/* 0x2AC : disp_gma_curve_ac */ -#define DSP2_MISC_DISP_GMA_CURVE_AC_OFFSET (0x2AC) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC DSP2_MISC_REG_DP_GMA_CURVE_AC -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD DSP2_MISC_REG_DP_GMA_CURVE_AD -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE DSP2_MISC_REG_DP_GMA_CURVE_AE -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF DSP2_MISC_REG_DP_GMA_CURVE_AF -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_AF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_AF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_AF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_AF_POS)) - -/* 0x2B0 : disp_gma_curve_b0 */ -#define DSP2_MISC_DISP_GMA_CURVE_B0_OFFSET (0x2B0) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0 DSP2_MISC_REG_DP_GMA_CURVE_B0 -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1 DSP2_MISC_REG_DP_GMA_CURVE_B1 -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2 DSP2_MISC_REG_DP_GMA_CURVE_B2 -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3 DSP2_MISC_REG_DP_GMA_CURVE_B3 -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B3_POS)) - -/* 0x2B4 : disp_gma_curve_b4 */ -#define DSP2_MISC_DISP_GMA_CURVE_B4_OFFSET (0x2B4) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4 DSP2_MISC_REG_DP_GMA_CURVE_B4 -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5 DSP2_MISC_REG_DP_GMA_CURVE_B5 -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6 DSP2_MISC_REG_DP_GMA_CURVE_B6 -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7 DSP2_MISC_REG_DP_GMA_CURVE_B7 -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B7_POS)) - -/* 0x2B8 : disp_gma_curve_b8 */ -#define DSP2_MISC_DISP_GMA_CURVE_B8_OFFSET (0x2B8) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8 DSP2_MISC_REG_DP_GMA_CURVE_B8 -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9 DSP2_MISC_REG_DP_GMA_CURVE_B9 -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_B9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_B9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_B9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_B9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA DSP2_MISC_REG_DP_GMA_CURVE_BA -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB DSP2_MISC_REG_DP_GMA_CURVE_BB -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BB_POS)) - -/* 0x2BC : disp_gma_curve_bc */ -#define DSP2_MISC_DISP_GMA_CURVE_BC_OFFSET (0x2BC) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC DSP2_MISC_REG_DP_GMA_CURVE_BC -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD DSP2_MISC_REG_DP_GMA_CURVE_BD -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE DSP2_MISC_REG_DP_GMA_CURVE_BE -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF DSP2_MISC_REG_DP_GMA_CURVE_BF -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_BF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_BF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_BF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_BF_POS)) - -/* 0x2C0 : disp_gma_curve_c0 */ -#define DSP2_MISC_DISP_GMA_CURVE_C0_OFFSET (0x2C0) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0 DSP2_MISC_REG_DP_GMA_CURVE_C0 -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1 DSP2_MISC_REG_DP_GMA_CURVE_C1 -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2 DSP2_MISC_REG_DP_GMA_CURVE_C2 -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3 DSP2_MISC_REG_DP_GMA_CURVE_C3 -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C3_POS)) - -/* 0x2C4 : disp_gma_curve_c4 */ -#define DSP2_MISC_DISP_GMA_CURVE_C4_OFFSET (0x2C4) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4 DSP2_MISC_REG_DP_GMA_CURVE_C4 -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5 DSP2_MISC_REG_DP_GMA_CURVE_C5 -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6 DSP2_MISC_REG_DP_GMA_CURVE_C6 -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7 DSP2_MISC_REG_DP_GMA_CURVE_C7 -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C7_POS)) - -/* 0x2C8 : disp_gma_curve_c8 */ -#define DSP2_MISC_DISP_GMA_CURVE_C8_OFFSET (0x2C8) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8 DSP2_MISC_REG_DP_GMA_CURVE_C8 -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9 DSP2_MISC_REG_DP_GMA_CURVE_C9 -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_C9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_C9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_C9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_C9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA DSP2_MISC_REG_DP_GMA_CURVE_CA -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB DSP2_MISC_REG_DP_GMA_CURVE_CB -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CB_POS)) - -/* 0x2CC : disp_gma_curve_cc */ -#define DSP2_MISC_DISP_GMA_CURVE_CC_OFFSET (0x2CC) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC DSP2_MISC_REG_DP_GMA_CURVE_CC -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD DSP2_MISC_REG_DP_GMA_CURVE_CD -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE DSP2_MISC_REG_DP_GMA_CURVE_CE -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF DSP2_MISC_REG_DP_GMA_CURVE_CF -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_CF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_CF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_CF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_CF_POS)) - -/* 0x2D0 : disp_gma_curve_d0 */ -#define DSP2_MISC_DISP_GMA_CURVE_D0_OFFSET (0x2D0) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0 DSP2_MISC_REG_DP_GMA_CURVE_D0 -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1 DSP2_MISC_REG_DP_GMA_CURVE_D1 -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2 DSP2_MISC_REG_DP_GMA_CURVE_D2 -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3 DSP2_MISC_REG_DP_GMA_CURVE_D3 -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D3_POS)) - -/* 0x2D4 : disp_gma_curve_d4 */ -#define DSP2_MISC_DISP_GMA_CURVE_D4_OFFSET (0x2D4) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4 DSP2_MISC_REG_DP_GMA_CURVE_D4 -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5 DSP2_MISC_REG_DP_GMA_CURVE_D5 -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6 DSP2_MISC_REG_DP_GMA_CURVE_D6 -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7 DSP2_MISC_REG_DP_GMA_CURVE_D7 -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D7_POS)) - -/* 0x2D8 : disp_gma_curve_d8 */ -#define DSP2_MISC_DISP_GMA_CURVE_D8_OFFSET (0x2D8) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8 DSP2_MISC_REG_DP_GMA_CURVE_D8 -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9 DSP2_MISC_REG_DP_GMA_CURVE_D9 -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_D9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_D9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_D9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_D9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA DSP2_MISC_REG_DP_GMA_CURVE_DA -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB DSP2_MISC_REG_DP_GMA_CURVE_DB -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DB_POS)) - -/* 0x2DC : disp_gma_curve_dc */ -#define DSP2_MISC_DISP_GMA_CURVE_DC_OFFSET (0x2DC) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC DSP2_MISC_REG_DP_GMA_CURVE_DC -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD DSP2_MISC_REG_DP_GMA_CURVE_DD -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE DSP2_MISC_REG_DP_GMA_CURVE_DE -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF DSP2_MISC_REG_DP_GMA_CURVE_DF -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_DF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_DF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_DF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_DF_POS)) - -/* 0x2E0 : disp_gma_curve_e0 */ -#define DSP2_MISC_DISP_GMA_CURVE_E0_OFFSET (0x2E0) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0 DSP2_MISC_REG_DP_GMA_CURVE_E0 -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1 DSP2_MISC_REG_DP_GMA_CURVE_E1 -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2 DSP2_MISC_REG_DP_GMA_CURVE_E2 -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3 DSP2_MISC_REG_DP_GMA_CURVE_E3 -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E3_POS)) - -/* 0x2E4 : disp_gma_curve_e4 */ -#define DSP2_MISC_DISP_GMA_CURVE_E4_OFFSET (0x2E4) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4 DSP2_MISC_REG_DP_GMA_CURVE_E4 -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5 DSP2_MISC_REG_DP_GMA_CURVE_E5 -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6 DSP2_MISC_REG_DP_GMA_CURVE_E6 -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7 DSP2_MISC_REG_DP_GMA_CURVE_E7 -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E7_POS)) - -/* 0x2E8 : disp_gma_curve_e8 */ -#define DSP2_MISC_DISP_GMA_CURVE_E8_OFFSET (0x2E8) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8 DSP2_MISC_REG_DP_GMA_CURVE_E8 -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9 DSP2_MISC_REG_DP_GMA_CURVE_E9 -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_E9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_E9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_E9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_E9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA DSP2_MISC_REG_DP_GMA_CURVE_EA -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB DSP2_MISC_REG_DP_GMA_CURVE_EB -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EB_POS)) - -/* 0x2EC : disp_gma_curve_ec */ -#define DSP2_MISC_DISP_GMA_CURVE_EC_OFFSET (0x2EC) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC DSP2_MISC_REG_DP_GMA_CURVE_EC -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED DSP2_MISC_REG_DP_GMA_CURVE_ED -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_ED_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_ED_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_ED_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_ED_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_ED_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE DSP2_MISC_REG_DP_GMA_CURVE_EE -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF DSP2_MISC_REG_DP_GMA_CURVE_EF -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_EF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_EF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_EF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_EF_POS)) - -/* 0x2F0 : disp_gma_curve_f0 */ -#define DSP2_MISC_DISP_GMA_CURVE_F0_OFFSET (0x2F0) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0 DSP2_MISC_REG_DP_GMA_CURVE_F0 -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F0_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F0_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F0_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F0_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1 DSP2_MISC_REG_DP_GMA_CURVE_F1 -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F1_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F1_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F1_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F1_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2 DSP2_MISC_REG_DP_GMA_CURVE_F2 -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F2_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F2_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F2_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F2_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3 DSP2_MISC_REG_DP_GMA_CURVE_F3 -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F3_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F3_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F3_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F3_POS)) - -/* 0x2F4 : disp_gma_curve_f4 */ -#define DSP2_MISC_DISP_GMA_CURVE_F4_OFFSET (0x2F4) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4 DSP2_MISC_REG_DP_GMA_CURVE_F4 -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F4_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F4_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F4_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F4_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5 DSP2_MISC_REG_DP_GMA_CURVE_F5 -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F5_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F5_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F5_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F5_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6 DSP2_MISC_REG_DP_GMA_CURVE_F6 -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F6_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F6_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F6_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F6_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7 DSP2_MISC_REG_DP_GMA_CURVE_F7 -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F7_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F7_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F7_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F7_POS)) - -/* 0x2F8 : disp_gma_curve_f8 */ -#define DSP2_MISC_DISP_GMA_CURVE_F8_OFFSET (0x2F8) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8 DSP2_MISC_REG_DP_GMA_CURVE_F8 -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F8_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F8_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F8_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F8_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9 DSP2_MISC_REG_DP_GMA_CURVE_F9 -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_F9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F9_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_F9_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_F9_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_F9_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA DSP2_MISC_REG_DP_GMA_CURVE_FA -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FA_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FA_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FA_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FA_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB DSP2_MISC_REG_DP_GMA_CURVE_FB -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FB_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FB_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FB_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FB_POS)) - -/* 0x2FC : disp_gma_curve_fc */ -#define DSP2_MISC_DISP_GMA_CURVE_FC_OFFSET (0x2FC) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC DSP2_MISC_REG_DP_GMA_CURVE_FC -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_POS (0U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FC_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FC_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FC_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FC_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD DSP2_MISC_REG_DP_GMA_CURVE_FD -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_POS (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FD_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FD_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FD_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FD_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE DSP2_MISC_REG_DP_GMA_CURVE_FE -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_POS (16U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FE_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FE_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FE_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FE_POS)) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF DSP2_MISC_REG_DP_GMA_CURVE_FF -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_POS (24U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_LEN (8U) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_MSK (((1U << DSP2_MISC_REG_DP_GMA_CURVE_FF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FF_POS) -#define DSP2_MISC_REG_DP_GMA_CURVE_FF_UMSK (~(((1U << DSP2_MISC_REG_DP_GMA_CURVE_FF_LEN) - 1) << DSP2_MISC_REG_DP_GMA_CURVE_FF_POS)) - -struct dsp2_misc_reg { - /* 0x0 : config */ - union { - struct { - uint32_t rg_dvpas_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t rg_dvpas_hs_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t rg_dvpas_vs_inv : 1; /* [ 2], r/w, 0x0 */ - uint32_t rg_dvpas_da_order : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_15 : 12; /* [15: 4], rsvd, 0x0 */ - uint32_t rg_dvpas_fifo_th : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_29 : 3; /* [29:27], rsvd, 0x0 */ - uint32_t cr_dsp2_de_as_hsync : 1; /* [ 30], r/w, 0x0 */ - uint32_t reg_dsp2_pclk_force_on : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } config; - - /* 0x4 : pix_data_ctrl */ - union { - struct { - uint32_t reg_pix_data_ctrl : 12; /* [11: 0], r/w, 0xfff */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_pix_data_sht_bit : 4; /* [19:16], r/w, 0x0 */ - uint32_t reg_pix_data_sht_dir : 1; /* [ 20], r/w, 0x0 */ - uint32_t reserved_21_30 : 10; /* [30:21], rsvd, 0x0 */ - uint32_t reg_dsp2_dtsrc_src : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pix_data_ctrl; - - /* 0x8 : dvp2bus_src_sel_1 */ - union { - struct { - uint32_t rg_d2b_dvp_sel_a : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_a : 1; /* [ 7], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_b : 6; /* [13: 8], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_b : 1; /* [ 15], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_c : 6; /* [21:16], r/w, 0x0 */ - uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_c : 1; /* [ 23], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_d : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_d : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2bus_src_sel_1; - - /* 0xC : dvp_frame_m_to_n */ - union { - struct { - uint32_t cr_frame_m_to_n_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t cr_frame_interval : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t cr_frame_cnt_n : 4; /* [11: 8], r/w, 0x0 */ - uint32_t cr_frame_cnt_m : 4; /* [15:12], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_frame_m_to_n; - - /* 0x10 : dsp2_id_bayer */ - union { - struct { - uint32_t reg_bayer_idgen_rst : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_bayer_idgen_edge : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t reg_bayer_idgen_cnt_incr : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_id_bayer; - - /* 0x14 : dvp2bus_src_sel_2 */ - union { - struct { - uint32_t rg_d2b_dvp_sel_e : 6; /* [ 5: 0], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_e : 1; /* [ 7], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_f : 6; /* [13: 8], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_f : 1; /* [ 15], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_g : 6; /* [21:16], r/w, 0x0 */ - uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_g : 1; /* [ 23], r/w, 0x0 */ - uint32_t rg_d2b_dvp_sel_h : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30 : 1; /* [ 30], rsvd, 0x0 */ - uint32_t rg_d2x_id_sel_h : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dvp2bus_src_sel_2; - - /* 0x18 reserved */ - uint8_t RESERVED0x18[8]; - - /* 0x20 : int_clr */ - union { - struct { - uint32_t rg_awb_int_clr : 1; /* [ 0], w1p, 0x0 */ - uint32_t rg_ae_int_clr : 1; /* [ 1], w1p, 0x0 */ - uint32_t rg_wdr_int_clr : 1; /* [ 2], w1p, 0x0 */ - uint32_t rg_awb2_int_clr : 1; /* [ 3], w1p, 0x0 */ - uint32_t rg_osd_pb_int_clr : 1; /* [ 4], w1p, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t rg_seof1_int_clr : 1; /* [ 8], w1p, 0x0 */ - uint32_t rg_seof2_int_clr : 1; /* [ 9], w1p, 0x0 */ - uint32_t rg_seof3_int_clr : 1; /* [ 10], w1p, 0x0 */ - uint32_t rg_ae_hist_int_clr : 1; /* [ 11], w1p, 0x0 */ - uint32_t rg_awb3_int_clr : 1; /* [ 12], w1p, 0x0 */ - uint32_t rg_dp_seof0_int_clr : 1; /* [ 13], w1p, 0x0 */ - uint32_t rg_seof4_int_clr : 1; /* [ 14], w1p, 0x0 */ - uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } int_clr; - - /* 0x24 : int_ctrl */ - union { - struct { - uint32_t rg_ae_int_mask : 1; /* [ 0], r/w, 0x0 */ - uint32_t rg_awb_int_mask : 1; /* [ 1], r/w, 0x0 */ - uint32_t rg_wdr_int_mask : 1; /* [ 2], r/w, 0x0 */ - uint32_t rg_awb2_int_mask : 1; /* [ 3], r/w, 0x0 */ - uint32_t rg_osd_pb_int_mask : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t rg_seof1_int_mask : 1; /* [ 8], r/w, 0x0 */ - uint32_t rg_seof1_int_edge : 1; /* [ 9], r/w, 0x0 */ - uint32_t rg_seof1_int_src : 2; /* [11:10], r/w, 0x2 */ - uint32_t rg_seof2_int_mask : 1; /* [ 12], r/w, 0x0 */ - uint32_t rg_seof2_int_edge : 1; /* [ 13], r/w, 0x0 */ - uint32_t rg_seof2_int_src : 2; /* [15:14], r/w, 0x2 */ - uint32_t rg_seof3_int_mask : 1; /* [ 16], r/w, 0x0 */ - uint32_t rg_seof3_int_edge : 1; /* [ 17], r/w, 0x0 */ - uint32_t rg_seof3_int_src : 2; /* [19:18], r/w, 0x2 */ - uint32_t rg_ae_hist_int_mask : 1; /* [ 20], r/w, 0x0 */ - uint32_t rg_awb3_int_mask : 1; /* [ 21], r/w, 0x0 */ - uint32_t rg_dp_seof0_int_src : 1; /* [ 22], r/w, 0x0 */ - uint32_t rg_dp_seof0_int_edge : 1; /* [ 23], r/w, 0x0 */ - uint32_t rg_dp_seof0_int_mask : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_27 : 3; /* [27:25], rsvd, 0x0 */ - uint32_t rg_seof4_int_mask : 1; /* [ 28], r/w, 0x0 */ - uint32_t rg_seof4_int_edge : 1; /* [ 29], r/w, 0x0 */ - uint32_t rg_seof4_int_src : 2; /* [31:30], r/w, 0x2 */ - } BF; - uint32_t WORD; - } int_ctrl; - - /* 0x28 : dsp2_id_yuv */ - union { - struct { - uint32_t reg_yuv_idgen_rst : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_yuv_idgen_edge : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t reg_yuv_idgen_cnt_incr : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_id_yuv; - - /* 0x2C : dvp_reshape */ - union { - struct { - uint32_t reg_rshp_tgl_count : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reg_rshp_hsync_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_rshp_vsync_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_rshp_clr : 1; /* [ 7], w1p, 0x0 */ - uint32_t reg_rshp_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_reshape; - - /* 0x30 reserved */ - uint8_t RESERVED0x30[16]; - - /* 0x40 : scalerA_i_size */ - union { - struct { - uint32_t rg_scalerA_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerA_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrA_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerA_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerA_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerA_i_size; - - /* 0x44 : scalerA_o_size */ - union { - struct { - uint32_t rg_scalerA_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerA_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerA_o_size; - - /* 0x48 : scalerB_i_size */ - union { - struct { - uint32_t rg_scalerB_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerB_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrB_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerB_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerB_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerB_i_size; - - /* 0x4C : scalerB_o_size */ - union { - struct { - uint32_t rg_scalerB_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerB_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerB_o_size; - - /* 0x50 : scalerC_i_size */ - union { - struct { - uint32_t rg_scalerC_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerC_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrC_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerC_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerC_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerC_i_size; - - /* 0x54 : scalerC_o_size */ - union { - struct { - uint32_t rg_scalerC_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerC_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerC_o_size; - - /* 0x58 : scalerD_i_size */ - union { - struct { - uint32_t rg_scalerD_i_w : 11; /* [10: 0], r/w, 0x780 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerD_i_h : 11; /* [26:16], r/w, 0x438 */ - uint32_t rg_sclrD_sw_sh : 1; /* [ 27], w1p, 0x0 */ - uint32_t rg_scalerD_bypass : 1; /* [ 28], r/w, 0x1 */ - uint32_t rg_scalerD_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } scalerD_i_size; - - /* 0x5C : scalerD_o_size */ - union { - struct { - uint32_t rg_scalerD_o_w : 11; /* [10: 0], r/w, 0x500 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t rg_scalerD_o_h : 11; /* [26:16], r/w, 0x2d0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } scalerD_o_size; - - /* 0x60 : disp_config */ - union { - struct { - uint32_t reserved_0_3 : 4; /* [ 3: 0], rsvd, 0x0 */ - uint32_t rg_disp_bt656_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t rg_disp_bt1120_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t rg_disp_dpi_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t rg_disp_hdmi_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t rg_disp_mux_sel : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t rg_osdDP_sel : 2; /* [13:12], r/w, 0x0 */ - uint32_t reserved_14_30 : 17; /* [30:14], rsvd, 0x0 */ - uint32_t rg_disp_clko_inv : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_config; - - /* 0x64 : disp_dpi_config */ - union { - struct { - uint32_t rg_disp_dpi_hs_w : 8; /* [ 7: 0], r/w, 0x8 */ - uint32_t rg_disp_dpi_hfp_w : 8; /* [15: 8], r/w, 0x10 */ - uint32_t rg_disp_dpi_vs_w : 8; /* [23:16], r/w, 0x2 */ - uint32_t rg_disp_dpi_vfp_w : 8; /* [31:24], r/w, 0x4 */ - } BF; - uint32_t WORD; - } disp_dpi_config; - - /* 0x68 : disp_yuv_rgb_config_0 */ - union { - struct { - uint32_t rg_disp_y2r_pre_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pre_1 : 9; /* [18:10], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pre_2 : 9; /* [28:20], r/w, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t rg_disp_y2r_en : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_0; - - /* 0x6C : disp_yuv_rgb_config_1 */ - union { - struct { - uint32_t rg_disp_y2r_pos_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pos_1 : 9; /* [18:10], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_y2r_pos_2 : 9; /* [28:20], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_1; - - /* 0x70 : disp_yuv_rgb_config_2 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_01 : 12; /* [23:12], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_02_l : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_2; - - /* 0x74 : disp_yuv_rgb_config_3 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_02_u : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_10 : 12; /* [15: 4], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_11 : 12; /* [27:16], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_12_l : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_3; - - /* 0x78 : disp_yuv_rgb_config_4 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_12_u : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_20 : 12; /* [19: 8], r/w, 0x0 */ - uint32_t rg_disp_y2r_mtx_21 : 12; /* [31:20], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_4; - - /* 0x7C : disp_yuv_rgb_config_5 */ - union { - struct { - uint32_t rg_disp_y2r_mtx_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_yuv_rgb_config_5; - - /* 0x80 : dsp2_subsys_bus_ctrl */ - union { - struct { - uint32_t rg_dsp2_sub_pclk_force_on : 16; /* [15: 0], r/w, 0x0 */ - uint32_t rg_dsp2_peri_pclk_force_on : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_subsys_bus_ctrl; - - /* 0x84 reserved */ - uint8_t RESERVED0x84[28]; - - /* 0xA0 : osdA_i_ctrl */ - union { - struct { - uint32_t rg_osd_pb_sel : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_28 : 28; /* [28: 1], rsvd, 0x0 */ - uint32_t rg_osdA_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdA_i_ctrl; - - /* 0xA4 : osdB_i_ctrl */ - union { - struct { - uint32_t reserved_0_28 : 29; /* [28: 0], rsvd, 0x0 */ - uint32_t rg_osdB_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdB_i_ctrl; - - /* 0xA8 : osdC_i_ctrl */ - union { - struct { - uint32_t reserved_0_28 : 29; /* [28: 0], rsvd, 0x0 */ - uint32_t rg_osdC_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdC_i_ctrl; - - /* 0xAC : osdD_i_ctrl */ - union { - struct { - uint32_t reserved_0_28 : 29; /* [28: 0], rsvd, 0x0 */ - uint32_t rg_osdD_sel : 3; /* [31:29], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osdD_i_ctrl; - - /* 0xb0 reserved */ - uint8_t RESERVED0xb0[16]; - - /* 0xC0 : dsp2_subsys_dbg_sel */ - union { - struct { - uint32_t reg_dsp2_sub_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_dsp2_sub_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_subsys_dbg_sel; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[56]; - - /* 0xFC : DSP2_MISC_Dummy */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */ - } BF; - uint32_t WORD; - } DSP2_MISC_Dummy; - - /* 0x100 : adjA_ctrl_0 */ - union { - struct { - uint32_t reg_adjA_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjA_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjA_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjA_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjA_ctrl_0; - - /* 0x104 : adjA_ctrl_1 */ - union { - struct { - uint32_t reg_adjA_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjA_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjA_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjA_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjA_ctrl_1; - - /* 0x108 : adjA_ctrl_2 */ - union { - struct { - uint32_t rg_adjA_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjA_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjA_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjA_ctrl_2; - - /* 0x10c reserved */ - uint8_t RESERVED0x10c[4]; - - /* 0x110 : adjB_ctrl_0 */ - union { - struct { - uint32_t reg_adjB_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjB_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjB_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjB_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjB_ctrl_0; - - /* 0x114 : adjB_ctrl_1 */ - union { - struct { - uint32_t reg_adjB_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjB_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjB_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjB_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjB_ctrl_1; - - /* 0x118 : adjB_ctrl_2 */ - union { - struct { - uint32_t rg_adjB_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjB_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjB_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjB_ctrl_2; - - /* 0x11c reserved */ - uint8_t RESERVED0x11c[4]; - - /* 0x120 : adjC_ctrl_0 */ - union { - struct { - uint32_t reg_adjC_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjC_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjC_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjC_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjC_ctrl_0; - - /* 0x124 : adjC_ctrl_1 */ - union { - struct { - uint32_t reg_adjC_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjC_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjC_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjC_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjC_ctrl_1; - - /* 0x128 : adjC_ctrl_2 */ - union { - struct { - uint32_t rg_adjC_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjC_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjC_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjC_ctrl_2; - - /* 0x12c reserved */ - uint8_t RESERVED0x12c[4]; - - /* 0x130 : adjD_ctrl_0 */ - union { - struct { - uint32_t reg_adjD_adj_eb : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_adjD_y_luma : 9; /* [ 9: 1], r/w, 0x0 */ - uint32_t reg_adjD_y_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjD_y_mul1 : 11; /* [31:21], r/w, 0x35e */ - } BF; - uint32_t WORD; - } adjD_ctrl_0; - - /* 0x134 : adjD_ctrl_1 */ - union { - struct { - uint32_t reg_adjD_y_min : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_adjD_y_max : 8; /* [15: 8], r/w, 0xeb */ - uint32_t reg_adjD_uv_min : 8; /* [23:16], r/w, 0x10 */ - uint32_t reg_adjD_uv_max : 8; /* [31:24], r/w, 0xf0 */ - } BF; - uint32_t WORD; - } adjD_ctrl_1; - - /* 0x138 : adjD_ctrl_2 */ - union { - struct { - uint32_t rg_adjD_sel : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t reserved_4_9 : 6; /* [ 9: 4], rsvd, 0x0 */ - uint32_t reg_adjD_uv_mul0 : 11; /* [20:10], r/w, 0x380 */ - uint32_t reg_adjD_uv_mul1 : 11; /* [31:21], r/w, 0x387 */ - } BF; - uint32_t WORD; - } adjD_ctrl_2; - - /* 0x13c reserved */ - uint8_t RESERVED0x13c[36]; - - /* 0x160 : y2rA_config_0 */ - union { - struct { - uint32_t rg_y2rA_pre_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t rg_y2rA_pos_0 : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_26 : 2; /* [26:25], rsvd, 0x0 */ - uint32_t rg_y2rA_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t rg_y2rA_sel : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_0; - - /* 0x164 : y2rA_config_1 */ - union { - struct { - uint32_t rg_y2rA_pre_1 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t rg_y2rA_pos_1 : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_1; - - /* 0x168 : y2rA_config_2 */ - union { - struct { - uint32_t rg_y2rA_pre_2 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_15 : 7; /* [15: 9], rsvd, 0x0 */ - uint32_t rg_y2rA_pos_2 : 9; /* [24:16], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_2; - - /* 0x16C : y2rA_config_3 */ - union { - struct { - uint32_t rg_y2rA_mtx_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_01 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_3; - - /* 0x170 : y2rA_config_4 */ - union { - struct { - uint32_t rg_y2rA_mtx_02 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_10 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_4; - - /* 0x174 : y2rA_config_5 */ - union { - struct { - uint32_t rg_y2rA_mtx_11 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_12 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_5; - - /* 0x178 : y2rA_config_6 */ - union { - struct { - uint32_t rg_y2rA_mtx_20 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t rg_y2rA_mtx_21 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_6; - - /* 0x17C : y2rA_config_7 */ - union { - struct { - uint32_t rg_y2rA_mtx_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } y2rA_config_7; - - /* 0x180 : disp_rgb2yuv_config_0 */ - union { - struct { - uint32_t rg_disp_r2y_pre_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pre_1 : 9; /* [18:10], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pre_2 : 9; /* [28:20], r/w, 0x0 */ - uint32_t reserved_29_30 : 2; /* [30:29], rsvd, 0x0 */ - uint32_t rg_disp_r2y_en : 1; /* [ 31], r/w, 0x1 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_0; - - /* 0x184 : disp_rgb2yuv_config_1 */ - union { - struct { - uint32_t rg_disp_r2y_pos_0 : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pos_1 : 9; /* [18:10], r/w, 0x80 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t rg_disp_r2y_pos_2 : 9; /* [28:20], r/w, 0x80 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_1; - - /* 0x188 : disp_rgb2yuv_config_2 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_00 : 12; /* [11: 0], r/w, 0x99 */ - uint32_t rg_disp_r2y_mtx_01 : 12; /* [23:12], r/w, 0x12d */ - uint32_t rg_disp_r2y_mtx_02_l : 8; /* [31:24], r/w, 0x3a */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_2; - - /* 0x18C : disp_rgb2yuv_config_3 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_02_u : 4; /* [ 3: 0], r/w, 0x0 */ - uint32_t rg_disp_r2y_mtx_10 : 12; /* [15: 4], r/w, 0xfa9 */ - uint32_t rg_disp_r2y_mtx_11 : 12; /* [27:16], r/w, 0xf57 */ - uint32_t rg_disp_r2y_mtx_12_l : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_3; - - /* 0x190 : disp_rgb2yuv_config_4 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_12_u : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t rg_disp_r2y_mtx_20 : 12; /* [19: 8], r/w, 0x100 */ - uint32_t rg_disp_r2y_mtx_21 : 12; /* [31:20], r/w, 0xf29 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_4; - - /* 0x194 : disp_rgb2yuv_config_5 */ - union { - struct { - uint32_t rg_disp_r2y_mtx_22 : 12; /* [11: 0], r/w, 0xfd7 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_rgb2yuv_config_5; - - /* 0x198 reserved */ - uint8_t RESERVED0x198[40]; - - /* 0x1C0 : cropA_hsync */ - union { - struct { - uint32_t reg_cropA_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropA_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropA_hsync; - - /* 0x1C4 : cropA_vsync */ - union { - struct { - uint32_t reg_cropA_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropA_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropA_vsync; - - /* 0x1C8 : cropB_hsync */ - union { - struct { - uint32_t reg_cropB_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropB_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropB_hsync; - - /* 0x1CC : cropB_vsync */ - union { - struct { - uint32_t reg_cropB_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropB_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropB_vsync; - - /* 0x1D0 : cropC_hsync */ - union { - struct { - uint32_t reg_cropC_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropC_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropC_hsync; - - /* 0x1D4 : cropC_vsync */ - union { - struct { - uint32_t reg_cropC_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropC_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropC_vsync; - - /* 0x1D8 : cropD_hsync */ - union { - struct { - uint32_t reg_cropD_hsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropD_hsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropD_hsync; - - /* 0x1DC : cropD_vsync */ - union { - struct { - uint32_t reg_cropD_vsync_start : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_cropD_vsync_end : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } cropD_vsync; - - /* 0x1E0 : crop_enable */ - union { - struct { - uint32_t reg_cropA_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_cropB_enable : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_cropC_enable : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_cropD_enable : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } crop_enable; - - /* 0x1e4 reserved */ - uint8_t RESERVED0x1e4[24]; - - /* 0x1FC : disp_gma_cfg */ - union { - struct { - uint32_t reg_dp_gma_ch0_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_dp_gma_ch1_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_dp_gma_ch2_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } disp_gma_cfg; - - /* 0x200 : disp_gma_curve_00 */ - union { - struct { - uint32_t reg_dp_gma_curve_00 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_dp_gma_curve_01 : 8; /* [15: 8], r/w, 0x1 */ - uint32_t reg_dp_gma_curve_02 : 8; /* [23:16], r/w, 0x2 */ - uint32_t reg_dp_gma_curve_03 : 8; /* [31:24], r/w, 0x3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_00; - - /* 0x204 : disp_gma_curve_04 */ - union { - struct { - uint32_t reg_dp_gma_curve_04 : 8; /* [ 7: 0], r/w, 0x4 */ - uint32_t reg_dp_gma_curve_05 : 8; /* [15: 8], r/w, 0x5 */ - uint32_t reg_dp_gma_curve_06 : 8; /* [23:16], r/w, 0x6 */ - uint32_t reg_dp_gma_curve_07 : 8; /* [31:24], r/w, 0x7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_04; - - /* 0x208 : disp_gma_curve_08 */ - union { - struct { - uint32_t reg_dp_gma_curve_08 : 8; /* [ 7: 0], r/w, 0x8 */ - uint32_t reg_dp_gma_curve_09 : 8; /* [15: 8], r/w, 0x9 */ - uint32_t reg_dp_gma_curve_0a : 8; /* [23:16], r/w, 0xa */ - uint32_t reg_dp_gma_curve_0b : 8; /* [31:24], r/w, 0xb */ - } BF; - uint32_t WORD; - } disp_gma_curve_08; - - /* 0x20C : disp_gma_curve_0c */ - union { - struct { - uint32_t reg_dp_gma_curve_0c : 8; /* [ 7: 0], r/w, 0xc */ - uint32_t reg_dp_gma_curve_0d : 8; /* [15: 8], r/w, 0xd */ - uint32_t reg_dp_gma_curve_0e : 8; /* [23:16], r/w, 0xe */ - uint32_t reg_dp_gma_curve_0f : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } disp_gma_curve_0c; - - /* 0x210 : disp_gma_curve_10 */ - union { - struct { - uint32_t reg_dp_gma_curve_10 : 8; /* [ 7: 0], r/w, 0x10 */ - uint32_t reg_dp_gma_curve_11 : 8; /* [15: 8], r/w, 0x11 */ - uint32_t reg_dp_gma_curve_12 : 8; /* [23:16], r/w, 0x12 */ - uint32_t reg_dp_gma_curve_13 : 8; /* [31:24], r/w, 0x13 */ - } BF; - uint32_t WORD; - } disp_gma_curve_10; - - /* 0x214 : disp_gma_curve_14 */ - union { - struct { - uint32_t reg_dp_gma_curve_14 : 8; /* [ 7: 0], r/w, 0x14 */ - uint32_t reg_dp_gma_curve_15 : 8; /* [15: 8], r/w, 0x15 */ - uint32_t reg_dp_gma_curve_16 : 8; /* [23:16], r/w, 0x16 */ - uint32_t reg_dp_gma_curve_17 : 8; /* [31:24], r/w, 0x17 */ - } BF; - uint32_t WORD; - } disp_gma_curve_14; - - /* 0x218 : disp_gma_curve_18 */ - union { - struct { - uint32_t reg_dp_gma_curve_18 : 8; /* [ 7: 0], r/w, 0x18 */ - uint32_t reg_dp_gma_curve_19 : 8; /* [15: 8], r/w, 0x19 */ - uint32_t reg_dp_gma_curve_1a : 8; /* [23:16], r/w, 0x1a */ - uint32_t reg_dp_gma_curve_1b : 8; /* [31:24], r/w, 0x1b */ - } BF; - uint32_t WORD; - } disp_gma_curve_18; - - /* 0x21C : disp_gma_curve_1c */ - union { - struct { - uint32_t reg_dp_gma_curve_1c : 8; /* [ 7: 0], r/w, 0x1c */ - uint32_t reg_dp_gma_curve_1d : 8; /* [15: 8], r/w, 0x1d */ - uint32_t reg_dp_gma_curve_1e : 8; /* [23:16], r/w, 0x1e */ - uint32_t reg_dp_gma_curve_1f : 8; /* [31:24], r/w, 0x1f */ - } BF; - uint32_t WORD; - } disp_gma_curve_1c; - - /* 0x220 : disp_gma_curve_20 */ - union { - struct { - uint32_t reg_dp_gma_curve_20 : 8; /* [ 7: 0], r/w, 0x20 */ - uint32_t reg_dp_gma_curve_21 : 8; /* [15: 8], r/w, 0x21 */ - uint32_t reg_dp_gma_curve_22 : 8; /* [23:16], r/w, 0x22 */ - uint32_t reg_dp_gma_curve_23 : 8; /* [31:24], r/w, 0x23 */ - } BF; - uint32_t WORD; - } disp_gma_curve_20; - - /* 0x224 : disp_gma_curve_24 */ - union { - struct { - uint32_t reg_dp_gma_curve_24 : 8; /* [ 7: 0], r/w, 0x24 */ - uint32_t reg_dp_gma_curve_25 : 8; /* [15: 8], r/w, 0x25 */ - uint32_t reg_dp_gma_curve_26 : 8; /* [23:16], r/w, 0x26 */ - uint32_t reg_dp_gma_curve_27 : 8; /* [31:24], r/w, 0x27 */ - } BF; - uint32_t WORD; - } disp_gma_curve_24; - - /* 0x228 : disp_gma_curve_28 */ - union { - struct { - uint32_t reg_dp_gma_curve_28 : 8; /* [ 7: 0], r/w, 0x28 */ - uint32_t reg_dp_gma_curve_29 : 8; /* [15: 8], r/w, 0x29 */ - uint32_t reg_dp_gma_curve_2a : 8; /* [23:16], r/w, 0x2a */ - uint32_t reg_dp_gma_curve_2b : 8; /* [31:24], r/w, 0x2b */ - } BF; - uint32_t WORD; - } disp_gma_curve_28; - - /* 0x22C : disp_gma_curve_2c */ - union { - struct { - uint32_t reg_dp_gma_curve_2c : 8; /* [ 7: 0], r/w, 0x2c */ - uint32_t reg_dp_gma_curve_2d : 8; /* [15: 8], r/w, 0x2d */ - uint32_t reg_dp_gma_curve_2e : 8; /* [23:16], r/w, 0x2e */ - uint32_t reg_dp_gma_curve_2f : 8; /* [31:24], r/w, 0x2f */ - } BF; - uint32_t WORD; - } disp_gma_curve_2c; - - /* 0x230 : disp_gma_curve_30 */ - union { - struct { - uint32_t reg_dp_gma_curve_30 : 8; /* [ 7: 0], r/w, 0x30 */ - uint32_t reg_dp_gma_curve_31 : 8; /* [15: 8], r/w, 0x31 */ - uint32_t reg_dp_gma_curve_32 : 8; /* [23:16], r/w, 0x32 */ - uint32_t reg_dp_gma_curve_33 : 8; /* [31:24], r/w, 0x33 */ - } BF; - uint32_t WORD; - } disp_gma_curve_30; - - /* 0x234 : disp_gma_curve_34 */ - union { - struct { - uint32_t reg_dp_gma_curve_34 : 8; /* [ 7: 0], r/w, 0x34 */ - uint32_t reg_dp_gma_curve_35 : 8; /* [15: 8], r/w, 0x35 */ - uint32_t reg_dp_gma_curve_36 : 8; /* [23:16], r/w, 0x36 */ - uint32_t reg_dp_gma_curve_37 : 8; /* [31:24], r/w, 0x37 */ - } BF; - uint32_t WORD; - } disp_gma_curve_34; - - /* 0x238 : disp_gma_curve_38 */ - union { - struct { - uint32_t reg_dp_gma_curve_38 : 8; /* [ 7: 0], r/w, 0x38 */ - uint32_t reg_dp_gma_curve_39 : 8; /* [15: 8], r/w, 0x39 */ - uint32_t reg_dp_gma_curve_3a : 8; /* [23:16], r/w, 0x3a */ - uint32_t reg_dp_gma_curve_3b : 8; /* [31:24], r/w, 0x3b */ - } BF; - uint32_t WORD; - } disp_gma_curve_38; - - /* 0x23C : disp_gma_curve_3c */ - union { - struct { - uint32_t reg_dp_gma_curve_3c : 8; /* [ 7: 0], r/w, 0x3c */ - uint32_t reg_dp_gma_curve_3d : 8; /* [15: 8], r/w, 0x3d */ - uint32_t reg_dp_gma_curve_3e : 8; /* [23:16], r/w, 0x3e */ - uint32_t reg_dp_gma_curve_3f : 8; /* [31:24], r/w, 0x3f */ - } BF; - uint32_t WORD; - } disp_gma_curve_3c; - - /* 0x240 : disp_gma_curve_40 */ - union { - struct { - uint32_t reg_dp_gma_curve_40 : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t reg_dp_gma_curve_41 : 8; /* [15: 8], r/w, 0x41 */ - uint32_t reg_dp_gma_curve_42 : 8; /* [23:16], r/w, 0x42 */ - uint32_t reg_dp_gma_curve_43 : 8; /* [31:24], r/w, 0x43 */ - } BF; - uint32_t WORD; - } disp_gma_curve_40; - - /* 0x244 : disp_gma_curve_44 */ - union { - struct { - uint32_t reg_dp_gma_curve_44 : 8; /* [ 7: 0], r/w, 0x44 */ - uint32_t reg_dp_gma_curve_45 : 8; /* [15: 8], r/w, 0x45 */ - uint32_t reg_dp_gma_curve_46 : 8; /* [23:16], r/w, 0x46 */ - uint32_t reg_dp_gma_curve_47 : 8; /* [31:24], r/w, 0x47 */ - } BF; - uint32_t WORD; - } disp_gma_curve_44; - - /* 0x248 : disp_gma_curve_48 */ - union { - struct { - uint32_t reg_dp_gma_curve_48 : 8; /* [ 7: 0], r/w, 0x48 */ - uint32_t reg_dp_gma_curve_49 : 8; /* [15: 8], r/w, 0x49 */ - uint32_t reg_dp_gma_curve_4a : 8; /* [23:16], r/w, 0x4a */ - uint32_t reg_dp_gma_curve_4b : 8; /* [31:24], r/w, 0x4b */ - } BF; - uint32_t WORD; - } disp_gma_curve_48; - - /* 0x24C : disp_gma_curve_4c */ - union { - struct { - uint32_t reg_dp_gma_curve_4c : 8; /* [ 7: 0], r/w, 0x4c */ - uint32_t reg_dp_gma_curve_4d : 8; /* [15: 8], r/w, 0x4d */ - uint32_t reg_dp_gma_curve_4e : 8; /* [23:16], r/w, 0x4e */ - uint32_t reg_dp_gma_curve_4f : 8; /* [31:24], r/w, 0x4f */ - } BF; - uint32_t WORD; - } disp_gma_curve_4c; - - /* 0x250 : disp_gma_curve_50 */ - union { - struct { - uint32_t reg_dp_gma_curve_50 : 8; /* [ 7: 0], r/w, 0x50 */ - uint32_t reg_dp_gma_curve_51 : 8; /* [15: 8], r/w, 0x51 */ - uint32_t reg_dp_gma_curve_52 : 8; /* [23:16], r/w, 0x52 */ - uint32_t reg_dp_gma_curve_53 : 8; /* [31:24], r/w, 0x53 */ - } BF; - uint32_t WORD; - } disp_gma_curve_50; - - /* 0x254 : disp_gma_curve_54 */ - union { - struct { - uint32_t reg_dp_gma_curve_54 : 8; /* [ 7: 0], r/w, 0x54 */ - uint32_t reg_dp_gma_curve_55 : 8; /* [15: 8], r/w, 0x55 */ - uint32_t reg_dp_gma_curve_56 : 8; /* [23:16], r/w, 0x56 */ - uint32_t reg_dp_gma_curve_57 : 8; /* [31:24], r/w, 0x57 */ - } BF; - uint32_t WORD; - } disp_gma_curve_54; - - /* 0x258 : disp_gma_curve_58 */ - union { - struct { - uint32_t reg_dp_gma_curve_58 : 8; /* [ 7: 0], r/w, 0x58 */ - uint32_t reg_dp_gma_curve_59 : 8; /* [15: 8], r/w, 0x59 */ - uint32_t reg_dp_gma_curve_5a : 8; /* [23:16], r/w, 0x5a */ - uint32_t reg_dp_gma_curve_5b : 8; /* [31:24], r/w, 0x5b */ - } BF; - uint32_t WORD; - } disp_gma_curve_58; - - /* 0x25C : disp_gma_curve_5c */ - union { - struct { - uint32_t reg_dp_gma_curve_5c : 8; /* [ 7: 0], r/w, 0x5c */ - uint32_t reg_dp_gma_curve_5d : 8; /* [15: 8], r/w, 0x5d */ - uint32_t reg_dp_gma_curve_5e : 8; /* [23:16], r/w, 0x5e */ - uint32_t reg_dp_gma_curve_5f : 8; /* [31:24], r/w, 0x5f */ - } BF; - uint32_t WORD; - } disp_gma_curve_5c; - - /* 0x260 : disp_gma_curve_60 */ - union { - struct { - uint32_t reg_dp_gma_curve_60 : 8; /* [ 7: 0], r/w, 0x60 */ - uint32_t reg_dp_gma_curve_61 : 8; /* [15: 8], r/w, 0x61 */ - uint32_t reg_dp_gma_curve_62 : 8; /* [23:16], r/w, 0x62 */ - uint32_t reg_dp_gma_curve_63 : 8; /* [31:24], r/w, 0x63 */ - } BF; - uint32_t WORD; - } disp_gma_curve_60; - - /* 0x264 : disp_gma_curve_64 */ - union { - struct { - uint32_t reg_dp_gma_curve_64 : 8; /* [ 7: 0], r/w, 0x64 */ - uint32_t reg_dp_gma_curve_65 : 8; /* [15: 8], r/w, 0x65 */ - uint32_t reg_dp_gma_curve_66 : 8; /* [23:16], r/w, 0x66 */ - uint32_t reg_dp_gma_curve_67 : 8; /* [31:24], r/w, 0x67 */ - } BF; - uint32_t WORD; - } disp_gma_curve_64; - - /* 0x268 : disp_gma_curve_68 */ - union { - struct { - uint32_t reg_dp_gma_curve_68 : 8; /* [ 7: 0], r/w, 0x68 */ - uint32_t reg_dp_gma_curve_69 : 8; /* [15: 8], r/w, 0x69 */ - uint32_t reg_dp_gma_curve_6a : 8; /* [23:16], r/w, 0x6a */ - uint32_t reg_dp_gma_curve_6b : 8; /* [31:24], r/w, 0x6b */ - } BF; - uint32_t WORD; - } disp_gma_curve_68; - - /* 0x26C : disp_gma_curve_6c */ - union { - struct { - uint32_t reg_dp_gma_curve_6c : 8; /* [ 7: 0], r/w, 0x6c */ - uint32_t reg_dp_gma_curve_6d : 8; /* [15: 8], r/w, 0x6d */ - uint32_t reg_dp_gma_curve_6e : 8; /* [23:16], r/w, 0x6e */ - uint32_t reg_dp_gma_curve_6f : 8; /* [31:24], r/w, 0x6f */ - } BF; - uint32_t WORD; - } disp_gma_curve_6c; - - /* 0x270 : disp_gma_curve_70 */ - union { - struct { - uint32_t reg_dp_gma_curve_70 : 8; /* [ 7: 0], r/w, 0x70 */ - uint32_t reg_dp_gma_curve_71 : 8; /* [15: 8], r/w, 0x71 */ - uint32_t reg_dp_gma_curve_72 : 8; /* [23:16], r/w, 0x72 */ - uint32_t reg_dp_gma_curve_73 : 8; /* [31:24], r/w, 0x73 */ - } BF; - uint32_t WORD; - } disp_gma_curve_70; - - /* 0x274 : disp_gma_curve_74 */ - union { - struct { - uint32_t reg_dp_gma_curve_74 : 8; /* [ 7: 0], r/w, 0x74 */ - uint32_t reg_dp_gma_curve_75 : 8; /* [15: 8], r/w, 0x75 */ - uint32_t reg_dp_gma_curve_76 : 8; /* [23:16], r/w, 0x76 */ - uint32_t reg_dp_gma_curve_77 : 8; /* [31:24], r/w, 0x77 */ - } BF; - uint32_t WORD; - } disp_gma_curve_74; - - /* 0x278 : disp_gma_curve_78 */ - union { - struct { - uint32_t reg_dp_gma_curve_78 : 8; /* [ 7: 0], r/w, 0x78 */ - uint32_t reg_dp_gma_curve_79 : 8; /* [15: 8], r/w, 0x79 */ - uint32_t reg_dp_gma_curve_7a : 8; /* [23:16], r/w, 0x7a */ - uint32_t reg_dp_gma_curve_7b : 8; /* [31:24], r/w, 0x7b */ - } BF; - uint32_t WORD; - } disp_gma_curve_78; - - /* 0x27C : disp_gma_curve_7c */ - union { - struct { - uint32_t reg_dp_gma_curve_7c : 8; /* [ 7: 0], r/w, 0x7c */ - uint32_t reg_dp_gma_curve_7d : 8; /* [15: 8], r/w, 0x7d */ - uint32_t reg_dp_gma_curve_7e : 8; /* [23:16], r/w, 0x7e */ - uint32_t reg_dp_gma_curve_7f : 8; /* [31:24], r/w, 0x7f */ - } BF; - uint32_t WORD; - } disp_gma_curve_7c; - - /* 0x280 : disp_gma_curve_80 */ - union { - struct { - uint32_t reg_dp_gma_curve_80 : 8; /* [ 7: 0], r/w, 0x80 */ - uint32_t reg_dp_gma_curve_81 : 8; /* [15: 8], r/w, 0x81 */ - uint32_t reg_dp_gma_curve_82 : 8; /* [23:16], r/w, 0x82 */ - uint32_t reg_dp_gma_curve_83 : 8; /* [31:24], r/w, 0x83 */ - } BF; - uint32_t WORD; - } disp_gma_curve_80; - - /* 0x284 : disp_gma_curve_84 */ - union { - struct { - uint32_t reg_dp_gma_curve_84 : 8; /* [ 7: 0], r/w, 0x84 */ - uint32_t reg_dp_gma_curve_85 : 8; /* [15: 8], r/w, 0x85 */ - uint32_t reg_dp_gma_curve_86 : 8; /* [23:16], r/w, 0x86 */ - uint32_t reg_dp_gma_curve_87 : 8; /* [31:24], r/w, 0x87 */ - } BF; - uint32_t WORD; - } disp_gma_curve_84; - - /* 0x288 : disp_gma_curve_88 */ - union { - struct { - uint32_t reg_dp_gma_curve_88 : 8; /* [ 7: 0], r/w, 0x88 */ - uint32_t reg_dp_gma_curve_89 : 8; /* [15: 8], r/w, 0x89 */ - uint32_t reg_dp_gma_curve_8a : 8; /* [23:16], r/w, 0x8a */ - uint32_t reg_dp_gma_curve_8b : 8; /* [31:24], r/w, 0x8b */ - } BF; - uint32_t WORD; - } disp_gma_curve_88; - - /* 0x28C : disp_gma_curve_8c */ - union { - struct { - uint32_t reg_dp_gma_curve_8c : 8; /* [ 7: 0], r/w, 0x8c */ - uint32_t reg_dp_gma_curve_8d : 8; /* [15: 8], r/w, 0x8d */ - uint32_t reg_dp_gma_curve_8e : 8; /* [23:16], r/w, 0x8e */ - uint32_t reg_dp_gma_curve_8f : 8; /* [31:24], r/w, 0x8f */ - } BF; - uint32_t WORD; - } disp_gma_curve_8c; - - /* 0x290 : disp_gma_curve_90 */ - union { - struct { - uint32_t reg_dp_gma_curve_90 : 8; /* [ 7: 0], r/w, 0x90 */ - uint32_t reg_dp_gma_curve_91 : 8; /* [15: 8], r/w, 0x91 */ - uint32_t reg_dp_gma_curve_92 : 8; /* [23:16], r/w, 0x92 */ - uint32_t reg_dp_gma_curve_93 : 8; /* [31:24], r/w, 0x93 */ - } BF; - uint32_t WORD; - } disp_gma_curve_90; - - /* 0x294 : disp_gma_curve_94 */ - union { - struct { - uint32_t reg_dp_gma_curve_94 : 8; /* [ 7: 0], r/w, 0x94 */ - uint32_t reg_dp_gma_curve_95 : 8; /* [15: 8], r/w, 0x95 */ - uint32_t reg_dp_gma_curve_96 : 8; /* [23:16], r/w, 0x96 */ - uint32_t reg_dp_gma_curve_97 : 8; /* [31:24], r/w, 0x97 */ - } BF; - uint32_t WORD; - } disp_gma_curve_94; - - /* 0x298 : disp_gma_curve_98 */ - union { - struct { - uint32_t reg_dp_gma_curve_98 : 8; /* [ 7: 0], r/w, 0x98 */ - uint32_t reg_dp_gma_curve_99 : 8; /* [15: 8], r/w, 0x99 */ - uint32_t reg_dp_gma_curve_9a : 8; /* [23:16], r/w, 0x9a */ - uint32_t reg_dp_gma_curve_9b : 8; /* [31:24], r/w, 0x9b */ - } BF; - uint32_t WORD; - } disp_gma_curve_98; - - /* 0x29C : disp_gma_curve_9c */ - union { - struct { - uint32_t reg_dp_gma_curve_9c : 8; /* [ 7: 0], r/w, 0x9c */ - uint32_t reg_dp_gma_curve_9d : 8; /* [15: 8], r/w, 0x9d */ - uint32_t reg_dp_gma_curve_9e : 8; /* [23:16], r/w, 0x9e */ - uint32_t reg_dp_gma_curve_9f : 8; /* [31:24], r/w, 0x9f */ - } BF; - uint32_t WORD; - } disp_gma_curve_9c; - - /* 0x2A0 : disp_gma_curve_a0 */ - union { - struct { - uint32_t reg_dp_gma_curve_a0 : 8; /* [ 7: 0], r/w, 0xa0 */ - uint32_t reg_dp_gma_curve_a1 : 8; /* [15: 8], r/w, 0xa1 */ - uint32_t reg_dp_gma_curve_a2 : 8; /* [23:16], r/w, 0xa2 */ - uint32_t reg_dp_gma_curve_a3 : 8; /* [31:24], r/w, 0xa3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_a0; - - /* 0x2A4 : disp_gma_curve_a4 */ - union { - struct { - uint32_t reg_dp_gma_curve_a4 : 8; /* [ 7: 0], r/w, 0xa4 */ - uint32_t reg_dp_gma_curve_a5 : 8; /* [15: 8], r/w, 0xa5 */ - uint32_t reg_dp_gma_curve_a6 : 8; /* [23:16], r/w, 0xa6 */ - uint32_t reg_dp_gma_curve_a7 : 8; /* [31:24], r/w, 0xa7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_a4; - - /* 0x2A8 : disp_gma_curve_a8 */ - union { - struct { - uint32_t reg_dp_gma_curve_a8 : 8; /* [ 7: 0], r/w, 0xa8 */ - uint32_t reg_dp_gma_curve_a9 : 8; /* [15: 8], r/w, 0xa9 */ - uint32_t reg_dp_gma_curve_aa : 8; /* [23:16], r/w, 0xaa */ - uint32_t reg_dp_gma_curve_ab : 8; /* [31:24], r/w, 0xab */ - } BF; - uint32_t WORD; - } disp_gma_curve_a8; - - /* 0x2AC : disp_gma_curve_ac */ - union { - struct { - uint32_t reg_dp_gma_curve_ac : 8; /* [ 7: 0], r/w, 0xac */ - uint32_t reg_dp_gma_curve_ad : 8; /* [15: 8], r/w, 0xad */ - uint32_t reg_dp_gma_curve_ae : 8; /* [23:16], r/w, 0xae */ - uint32_t reg_dp_gma_curve_af : 8; /* [31:24], r/w, 0xaf */ - } BF; - uint32_t WORD; - } disp_gma_curve_ac; - - /* 0x2B0 : disp_gma_curve_b0 */ - union { - struct { - uint32_t reg_dp_gma_curve_b0 : 8; /* [ 7: 0], r/w, 0xb0 */ - uint32_t reg_dp_gma_curve_b1 : 8; /* [15: 8], r/w, 0xb1 */ - uint32_t reg_dp_gma_curve_b2 : 8; /* [23:16], r/w, 0xb2 */ - uint32_t reg_dp_gma_curve_b3 : 8; /* [31:24], r/w, 0xb3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_b0; - - /* 0x2B4 : disp_gma_curve_b4 */ - union { - struct { - uint32_t reg_dp_gma_curve_b4 : 8; /* [ 7: 0], r/w, 0xb4 */ - uint32_t reg_dp_gma_curve_b5 : 8; /* [15: 8], r/w, 0xb5 */ - uint32_t reg_dp_gma_curve_b6 : 8; /* [23:16], r/w, 0xb6 */ - uint32_t reg_dp_gma_curve_b7 : 8; /* [31:24], r/w, 0xb7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_b4; - - /* 0x2B8 : disp_gma_curve_b8 */ - union { - struct { - uint32_t reg_dp_gma_curve_b8 : 8; /* [ 7: 0], r/w, 0xb8 */ - uint32_t reg_dp_gma_curve_b9 : 8; /* [15: 8], r/w, 0xb9 */ - uint32_t reg_dp_gma_curve_ba : 8; /* [23:16], r/w, 0xba */ - uint32_t reg_dp_gma_curve_bb : 8; /* [31:24], r/w, 0xbb */ - } BF; - uint32_t WORD; - } disp_gma_curve_b8; - - /* 0x2BC : disp_gma_curve_bc */ - union { - struct { - uint32_t reg_dp_gma_curve_bc : 8; /* [ 7: 0], r/w, 0xbc */ - uint32_t reg_dp_gma_curve_bd : 8; /* [15: 8], r/w, 0xbd */ - uint32_t reg_dp_gma_curve_be : 8; /* [23:16], r/w, 0xbe */ - uint32_t reg_dp_gma_curve_bf : 8; /* [31:24], r/w, 0xbf */ - } BF; - uint32_t WORD; - } disp_gma_curve_bc; - - /* 0x2C0 : disp_gma_curve_c0 */ - union { - struct { - uint32_t reg_dp_gma_curve_c0 : 8; /* [ 7: 0], r/w, 0xc0 */ - uint32_t reg_dp_gma_curve_c1 : 8; /* [15: 8], r/w, 0xc1 */ - uint32_t reg_dp_gma_curve_c2 : 8; /* [23:16], r/w, 0xc2 */ - uint32_t reg_dp_gma_curve_c3 : 8; /* [31:24], r/w, 0xc3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_c0; - - /* 0x2C4 : disp_gma_curve_c4 */ - union { - struct { - uint32_t reg_dp_gma_curve_c4 : 8; /* [ 7: 0], r/w, 0xc4 */ - uint32_t reg_dp_gma_curve_c5 : 8; /* [15: 8], r/w, 0xc5 */ - uint32_t reg_dp_gma_curve_c6 : 8; /* [23:16], r/w, 0xc6 */ - uint32_t reg_dp_gma_curve_c7 : 8; /* [31:24], r/w, 0xc7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_c4; - - /* 0x2C8 : disp_gma_curve_c8 */ - union { - struct { - uint32_t reg_dp_gma_curve_c8 : 8; /* [ 7: 0], r/w, 0xc8 */ - uint32_t reg_dp_gma_curve_c9 : 8; /* [15: 8], r/w, 0xc9 */ - uint32_t reg_dp_gma_curve_ca : 8; /* [23:16], r/w, 0xca */ - uint32_t reg_dp_gma_curve_cb : 8; /* [31:24], r/w, 0xcb */ - } BF; - uint32_t WORD; - } disp_gma_curve_c8; - - /* 0x2CC : disp_gma_curve_cc */ - union { - struct { - uint32_t reg_dp_gma_curve_cc : 8; /* [ 7: 0], r/w, 0xcc */ - uint32_t reg_dp_gma_curve_cd : 8; /* [15: 8], r/w, 0xcd */ - uint32_t reg_dp_gma_curve_ce : 8; /* [23:16], r/w, 0xce */ - uint32_t reg_dp_gma_curve_cf : 8; /* [31:24], r/w, 0xcf */ - } BF; - uint32_t WORD; - } disp_gma_curve_cc; - - /* 0x2D0 : disp_gma_curve_d0 */ - union { - struct { - uint32_t reg_dp_gma_curve_d0 : 8; /* [ 7: 0], r/w, 0xd0 */ - uint32_t reg_dp_gma_curve_d1 : 8; /* [15: 8], r/w, 0xd1 */ - uint32_t reg_dp_gma_curve_d2 : 8; /* [23:16], r/w, 0xd2 */ - uint32_t reg_dp_gma_curve_d3 : 8; /* [31:24], r/w, 0xd3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_d0; - - /* 0x2D4 : disp_gma_curve_d4 */ - union { - struct { - uint32_t reg_dp_gma_curve_d4 : 8; /* [ 7: 0], r/w, 0xd4 */ - uint32_t reg_dp_gma_curve_d5 : 8; /* [15: 8], r/w, 0xd5 */ - uint32_t reg_dp_gma_curve_d6 : 8; /* [23:16], r/w, 0xd6 */ - uint32_t reg_dp_gma_curve_d7 : 8; /* [31:24], r/w, 0xd7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_d4; - - /* 0x2D8 : disp_gma_curve_d8 */ - union { - struct { - uint32_t reg_dp_gma_curve_d8 : 8; /* [ 7: 0], r/w, 0xd8 */ - uint32_t reg_dp_gma_curve_d9 : 8; /* [15: 8], r/w, 0xd9 */ - uint32_t reg_dp_gma_curve_da : 8; /* [23:16], r/w, 0xda */ - uint32_t reg_dp_gma_curve_db : 8; /* [31:24], r/w, 0xdb */ - } BF; - uint32_t WORD; - } disp_gma_curve_d8; - - /* 0x2DC : disp_gma_curve_dc */ - union { - struct { - uint32_t reg_dp_gma_curve_dc : 8; /* [ 7: 0], r/w, 0xdc */ - uint32_t reg_dp_gma_curve_dd : 8; /* [15: 8], r/w, 0xdd */ - uint32_t reg_dp_gma_curve_de : 8; /* [23:16], r/w, 0xde */ - uint32_t reg_dp_gma_curve_df : 8; /* [31:24], r/w, 0xdf */ - } BF; - uint32_t WORD; - } disp_gma_curve_dc; - - /* 0x2E0 : disp_gma_curve_e0 */ - union { - struct { - uint32_t reg_dp_gma_curve_e0 : 8; /* [ 7: 0], r/w, 0xe0 */ - uint32_t reg_dp_gma_curve_e1 : 8; /* [15: 8], r/w, 0xe1 */ - uint32_t reg_dp_gma_curve_e2 : 8; /* [23:16], r/w, 0xe2 */ - uint32_t reg_dp_gma_curve_e3 : 8; /* [31:24], r/w, 0xe3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_e0; - - /* 0x2E4 : disp_gma_curve_e4 */ - union { - struct { - uint32_t reg_dp_gma_curve_e4 : 8; /* [ 7: 0], r/w, 0xe4 */ - uint32_t reg_dp_gma_curve_e5 : 8; /* [15: 8], r/w, 0xe5 */ - uint32_t reg_dp_gma_curve_e6 : 8; /* [23:16], r/w, 0xe6 */ - uint32_t reg_dp_gma_curve_e7 : 8; /* [31:24], r/w, 0xe7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_e4; - - /* 0x2E8 : disp_gma_curve_e8 */ - union { - struct { - uint32_t reg_dp_gma_curve_e8 : 8; /* [ 7: 0], r/w, 0xe8 */ - uint32_t reg_dp_gma_curve_e9 : 8; /* [15: 8], r/w, 0xe9 */ - uint32_t reg_dp_gma_curve_ea : 8; /* [23:16], r/w, 0xea */ - uint32_t reg_dp_gma_curve_eb : 8; /* [31:24], r/w, 0xeb */ - } BF; - uint32_t WORD; - } disp_gma_curve_e8; - - /* 0x2EC : disp_gma_curve_ec */ - union { - struct { - uint32_t reg_dp_gma_curve_ec : 8; /* [ 7: 0], r/w, 0xec */ - uint32_t reg_dp_gma_curve_ed : 8; /* [15: 8], r/w, 0xed */ - uint32_t reg_dp_gma_curve_ee : 8; /* [23:16], r/w, 0xee */ - uint32_t reg_dp_gma_curve_ef : 8; /* [31:24], r/w, 0xef */ - } BF; - uint32_t WORD; - } disp_gma_curve_ec; - - /* 0x2F0 : disp_gma_curve_f0 */ - union { - struct { - uint32_t reg_dp_gma_curve_f0 : 8; /* [ 7: 0], r/w, 0xf0 */ - uint32_t reg_dp_gma_curve_f1 : 8; /* [15: 8], r/w, 0xf1 */ - uint32_t reg_dp_gma_curve_f2 : 8; /* [23:16], r/w, 0xf2 */ - uint32_t reg_dp_gma_curve_f3 : 8; /* [31:24], r/w, 0xf3 */ - } BF; - uint32_t WORD; - } disp_gma_curve_f0; - - /* 0x2F4 : disp_gma_curve_f4 */ - union { - struct { - uint32_t reg_dp_gma_curve_f4 : 8; /* [ 7: 0], r/w, 0xf4 */ - uint32_t reg_dp_gma_curve_f5 : 8; /* [15: 8], r/w, 0xf5 */ - uint32_t reg_dp_gma_curve_f6 : 8; /* [23:16], r/w, 0xf6 */ - uint32_t reg_dp_gma_curve_f7 : 8; /* [31:24], r/w, 0xf7 */ - } BF; - uint32_t WORD; - } disp_gma_curve_f4; - - /* 0x2F8 : disp_gma_curve_f8 */ - union { - struct { - uint32_t reg_dp_gma_curve_f8 : 8; /* [ 7: 0], r/w, 0xf8 */ - uint32_t reg_dp_gma_curve_f9 : 8; /* [15: 8], r/w, 0xf9 */ - uint32_t reg_dp_gma_curve_fa : 8; /* [23:16], r/w, 0xfa */ - uint32_t reg_dp_gma_curve_fb : 8; /* [31:24], r/w, 0xfb */ - } BF; - uint32_t WORD; - } disp_gma_curve_f8; - - /* 0x2FC : disp_gma_curve_fc */ - union { - struct { - uint32_t reg_dp_gma_curve_fc : 8; /* [ 7: 0], r/w, 0xfc */ - uint32_t reg_dp_gma_curve_fd : 8; /* [15: 8], r/w, 0xfd */ - uint32_t reg_dp_gma_curve_fe : 8; /* [23:16], r/w, 0xfe */ - uint32_t reg_dp_gma_curve_ff : 8; /* [31:24], r/w, 0xff */ - } BF; - uint32_t WORD; - } disp_gma_curve_fc; -}; - -typedef volatile struct dsp2_misc_reg dsp2_misc_reg_t; - -#endif /* __DSP2_MISC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_tg_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_tg_reg.h deleted file mode 100644 index 48584252ba..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dsp2_tg_reg.h +++ /dev/null @@ -1,423 +0,0 @@ -/** - ****************************************************************************** - * @file dsp2_tg_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DSP2_TG_REG_H__ -#define __DSP2_TG_REG_H__ - -#include "bl808.h" - -/* 0x00 : ip_info */ -#define DSP2_TG_IP_INFO_OFFSET (0x00) -#define DSP2_TG_IP_ID_R DSP2_TG_IP_ID_R -#define DSP2_TG_IP_ID_R_POS (8U) -#define DSP2_TG_IP_ID_R_LEN (8U) -#define DSP2_TG_IP_ID_R_MSK (((1U << DSP2_TG_IP_ID_R_LEN) - 1) << DSP2_TG_IP_ID_R_POS) -#define DSP2_TG_IP_ID_R_UMSK (~(((1U << DSP2_TG_IP_ID_R_LEN) - 1) << DSP2_TG_IP_ID_R_POS)) -#define DSP2_TG_VERSION_R DSP2_TG_VERSION_R -#define DSP2_TG_VERSION_R_POS (16U) -#define DSP2_TG_VERSION_R_LEN (8U) -#define DSP2_TG_VERSION_R_MSK (((1U << DSP2_TG_VERSION_R_LEN) - 1) << DSP2_TG_VERSION_R_POS) -#define DSP2_TG_VERSION_R_UMSK (~(((1U << DSP2_TG_VERSION_R_LEN) - 1) << DSP2_TG_VERSION_R_POS)) - -/* 0x08 : dvp_mode */ -#define DSP2_TG_DVP_MODE_OFFSET (0x08) -#define DSP2_TG_FHBLK_LINE_ON_W DSP2_TG_FHBLK_LINE_ON_W -#define DSP2_TG_FHBLK_LINE_ON_W_POS (0U) -#define DSP2_TG_FHBLK_LINE_ON_W_LEN (1U) -#define DSP2_TG_FHBLK_LINE_ON_W_MSK (((1U << DSP2_TG_FHBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_FHBLK_LINE_ON_W_POS) -#define DSP2_TG_FHBLK_LINE_ON_W_UMSK (~(((1U << DSP2_TG_FHBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_FHBLK_LINE_ON_W_POS)) -#define DSP2_TG_HBLK_LINE_ON_W DSP2_TG_HBLK_LINE_ON_W -#define DSP2_TG_HBLK_LINE_ON_W_POS (1U) -#define DSP2_TG_HBLK_LINE_ON_W_LEN (1U) -#define DSP2_TG_HBLK_LINE_ON_W_MSK (((1U << DSP2_TG_HBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_HBLK_LINE_ON_W_POS) -#define DSP2_TG_HBLK_LINE_ON_W_UMSK (~(((1U << DSP2_TG_HBLK_LINE_ON_W_LEN) - 1) << DSP2_TG_HBLK_LINE_ON_W_POS)) -#define DSP2_TG_VCNT_RST_MODE_W DSP2_TG_VCNT_RST_MODE_W -#define DSP2_TG_VCNT_RST_MODE_W_POS (16U) -#define DSP2_TG_VCNT_RST_MODE_W_LEN (1U) -#define DSP2_TG_VCNT_RST_MODE_W_MSK (((1U << DSP2_TG_VCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_VCNT_RST_MODE_W_POS) -#define DSP2_TG_VCNT_RST_MODE_W_UMSK (~(((1U << DSP2_TG_VCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_VCNT_RST_MODE_W_POS)) -#define DSP2_TG_HCNT_RST_MODE_W DSP2_TG_HCNT_RST_MODE_W -#define DSP2_TG_HCNT_RST_MODE_W_POS (17U) -#define DSP2_TG_HCNT_RST_MODE_W_LEN (1U) -#define DSP2_TG_HCNT_RST_MODE_W_MSK (((1U << DSP2_TG_HCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_HCNT_RST_MODE_W_POS) -#define DSP2_TG_HCNT_RST_MODE_W_UMSK (~(((1U << DSP2_TG_HCNT_RST_MODE_W_LEN) - 1) << DSP2_TG_HCNT_RST_MODE_W_POS)) -#define DSP2_TG_VSYNC_IN_INV_W DSP2_TG_VSYNC_IN_INV_W -#define DSP2_TG_VSYNC_IN_INV_W_POS (18U) -#define DSP2_TG_VSYNC_IN_INV_W_LEN (1U) -#define DSP2_TG_VSYNC_IN_INV_W_MSK (((1U << DSP2_TG_VSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_VSYNC_IN_INV_W_POS) -#define DSP2_TG_VSYNC_IN_INV_W_UMSK (~(((1U << DSP2_TG_VSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_VSYNC_IN_INV_W_POS)) -#define DSP2_TG_HSYNC_IN_INV_W DSP2_TG_HSYNC_IN_INV_W -#define DSP2_TG_HSYNC_IN_INV_W_POS (19U) -#define DSP2_TG_HSYNC_IN_INV_W_LEN (1U) -#define DSP2_TG_HSYNC_IN_INV_W_MSK (((1U << DSP2_TG_HSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_HSYNC_IN_INV_W_POS) -#define DSP2_TG_HSYNC_IN_INV_W_UMSK (~(((1U << DSP2_TG_HSYNC_IN_INV_W_LEN) - 1) << DSP2_TG_HSYNC_IN_INV_W_POS)) -#define DSP2_TG_SYNC_MODE_W DSP2_TG_SYNC_MODE_W -#define DSP2_TG_SYNC_MODE_W_POS (20U) -#define DSP2_TG_SYNC_MODE_W_LEN (2U) -#define DSP2_TG_SYNC_MODE_W_MSK (((1U << DSP2_TG_SYNC_MODE_W_LEN) - 1) << DSP2_TG_SYNC_MODE_W_POS) -#define DSP2_TG_SYNC_MODE_W_UMSK (~(((1U << DSP2_TG_SYNC_MODE_W_LEN) - 1) << DSP2_TG_SYNC_MODE_W_POS)) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W DSP2_TG_REG_ACT_VSYNC_RST_EN_W -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_POS (24U) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_LEN (1U) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_MSK (((1U << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_LEN) - 1) << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_POS) -#define DSP2_TG_REG_ACT_VSYNC_RST_EN_W_UMSK (~(((1U << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_LEN) - 1) << DSP2_TG_REG_ACT_VSYNC_RST_EN_W_POS)) - -/* 0x0C : total_pixels */ -#define DSP2_TG_TOTAL_PIXELS_OFFSET (0x0C) -#define DSP2_TG_TOTAL_HPIXELS_W DSP2_TG_TOTAL_HPIXELS_W -#define DSP2_TG_TOTAL_HPIXELS_W_POS (0U) -#define DSP2_TG_TOTAL_HPIXELS_W_LEN (16U) -#define DSP2_TG_TOTAL_HPIXELS_W_MSK (((1U << DSP2_TG_TOTAL_HPIXELS_W_LEN) - 1) << DSP2_TG_TOTAL_HPIXELS_W_POS) -#define DSP2_TG_TOTAL_HPIXELS_W_UMSK (~(((1U << DSP2_TG_TOTAL_HPIXELS_W_LEN) - 1) << DSP2_TG_TOTAL_HPIXELS_W_POS)) -#define DSP2_TG_TOTAL_VLINES_W DSP2_TG_TOTAL_VLINES_W -#define DSP2_TG_TOTAL_VLINES_W_POS (16U) -#define DSP2_TG_TOTAL_VLINES_W_LEN (16U) -#define DSP2_TG_TOTAL_VLINES_W_MSK (((1U << DSP2_TG_TOTAL_VLINES_W_LEN) - 1) << DSP2_TG_TOTAL_VLINES_W_POS) -#define DSP2_TG_TOTAL_VLINES_W_UMSK (~(((1U << DSP2_TG_TOTAL_VLINES_W_LEN) - 1) << DSP2_TG_TOTAL_VLINES_W_POS)) - -/* 0x10 : act_pixels_1 */ -#define DSP2_TG_ACT_PIXELS_1_OFFSET (0x10) -#define DSP2_TG_ACT_START_PIXEL_W DSP2_TG_ACT_START_PIXEL_W -#define DSP2_TG_ACT_START_PIXEL_W_POS (0U) -#define DSP2_TG_ACT_START_PIXEL_W_LEN (16U) -#define DSP2_TG_ACT_START_PIXEL_W_MSK (((1U << DSP2_TG_ACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_ACT_START_PIXEL_W_POS) -#define DSP2_TG_ACT_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_ACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_ACT_START_PIXEL_W_POS)) -#define DSP2_TG_ACT_PIXEL_WIDTH_W DSP2_TG_ACT_PIXEL_WIDTH_W -#define DSP2_TG_ACT_PIXEL_WIDTH_W_POS (16U) -#define DSP2_TG_ACT_PIXEL_WIDTH_W_LEN (16U) -#define DSP2_TG_ACT_PIXEL_WIDTH_W_MSK (((1U << DSP2_TG_ACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_ACT_PIXEL_WIDTH_W_POS) -#define DSP2_TG_ACT_PIXEL_WIDTH_W_UMSK (~(((1U << DSP2_TG_ACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_ACT_PIXEL_WIDTH_W_POS)) - -/* 0x14 : act_pixels_2 */ -#define DSP2_TG_ACT_PIXELS_2_OFFSET (0x14) -#define DSP2_TG_ACT_START_LINE_W DSP2_TG_ACT_START_LINE_W -#define DSP2_TG_ACT_START_LINE_W_POS (0U) -#define DSP2_TG_ACT_START_LINE_W_LEN (16U) -#define DSP2_TG_ACT_START_LINE_W_MSK (((1U << DSP2_TG_ACT_START_LINE_W_LEN) - 1) << DSP2_TG_ACT_START_LINE_W_POS) -#define DSP2_TG_ACT_START_LINE_W_UMSK (~(((1U << DSP2_TG_ACT_START_LINE_W_LEN) - 1) << DSP2_TG_ACT_START_LINE_W_POS)) -#define DSP2_TG_ACT_LINE_HEIGHT_W DSP2_TG_ACT_LINE_HEIGHT_W -#define DSP2_TG_ACT_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_ACT_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_ACT_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_ACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_ACT_LINE_HEIGHT_W_POS) -#define DSP2_TG_ACT_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_ACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_ACT_LINE_HEIGHT_W_POS)) - -/* 0x18 : fact_pixels_1 */ -#define DSP2_TG_FACT_PIXELS_1_OFFSET (0x18) -#define DSP2_TG_FACT_START_PIXEL_W DSP2_TG_FACT_START_PIXEL_W -#define DSP2_TG_FACT_START_PIXEL_W_POS (0U) -#define DSP2_TG_FACT_START_PIXEL_W_LEN (16U) -#define DSP2_TG_FACT_START_PIXEL_W_MSK (((1U << DSP2_TG_FACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_FACT_START_PIXEL_W_POS) -#define DSP2_TG_FACT_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_FACT_START_PIXEL_W_LEN) - 1) << DSP2_TG_FACT_START_PIXEL_W_POS)) -#define DSP2_TG_FACT_PIXEL_WIDTH_W DSP2_TG_FACT_PIXEL_WIDTH_W -#define DSP2_TG_FACT_PIXEL_WIDTH_W_POS (16U) -#define DSP2_TG_FACT_PIXEL_WIDTH_W_LEN (16U) -#define DSP2_TG_FACT_PIXEL_WIDTH_W_MSK (((1U << DSP2_TG_FACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_FACT_PIXEL_WIDTH_W_POS) -#define DSP2_TG_FACT_PIXEL_WIDTH_W_UMSK (~(((1U << DSP2_TG_FACT_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_FACT_PIXEL_WIDTH_W_POS)) - -/* 0x1C : fact_pixels_2 */ -#define DSP2_TG_FACT_PIXELS_2_OFFSET (0x1C) -#define DSP2_TG_FACT_START_LINE_W DSP2_TG_FACT_START_LINE_W -#define DSP2_TG_FACT_START_LINE_W_POS (0U) -#define DSP2_TG_FACT_START_LINE_W_LEN (16U) -#define DSP2_TG_FACT_START_LINE_W_MSK (((1U << DSP2_TG_FACT_START_LINE_W_LEN) - 1) << DSP2_TG_FACT_START_LINE_W_POS) -#define DSP2_TG_FACT_START_LINE_W_UMSK (~(((1U << DSP2_TG_FACT_START_LINE_W_LEN) - 1) << DSP2_TG_FACT_START_LINE_W_POS)) -#define DSP2_TG_FACT_LINE_HEIGHT_W DSP2_TG_FACT_LINE_HEIGHT_W -#define DSP2_TG_FACT_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_FACT_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_FACT_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_FACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_FACT_LINE_HEIGHT_W_POS) -#define DSP2_TG_FACT_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_FACT_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_FACT_LINE_HEIGHT_W_POS)) - -/* 0x20 : hsync_pixel */ -#define DSP2_TG_HSYNC_PIXEL_OFFSET (0x20) -#define DSP2_TG_HSYNC_START_PIXEL_W DSP2_TG_HSYNC_START_PIXEL_W -#define DSP2_TG_HSYNC_START_PIXEL_W_POS (0U) -#define DSP2_TG_HSYNC_START_PIXEL_W_LEN (16U) -#define DSP2_TG_HSYNC_START_PIXEL_W_MSK (((1U << DSP2_TG_HSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_HSYNC_START_PIXEL_W_POS) -#define DSP2_TG_HSYNC_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_HSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_HSYNC_START_PIXEL_W_POS)) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W DSP2_TG_HSYNC_PIXEL_WIDTH_W -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_POS (16U) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_LEN (16U) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_MSK (((1U << DSP2_TG_HSYNC_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_HSYNC_PIXEL_WIDTH_W_POS) -#define DSP2_TG_HSYNC_PIXEL_WIDTH_W_UMSK (~(((1U << DSP2_TG_HSYNC_PIXEL_WIDTH_W_LEN) - 1) << DSP2_TG_HSYNC_PIXEL_WIDTH_W_POS)) - -/* 0x24 : hsync_line */ -#define DSP2_TG_HSYNC_LINE_OFFSET (0x24) -#define DSP2_TG_HSYNC_START_LINE_W DSP2_TG_HSYNC_START_LINE_W -#define DSP2_TG_HSYNC_START_LINE_W_POS (0U) -#define DSP2_TG_HSYNC_START_LINE_W_LEN (16U) -#define DSP2_TG_HSYNC_START_LINE_W_MSK (((1U << DSP2_TG_HSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_HSYNC_START_LINE_W_POS) -#define DSP2_TG_HSYNC_START_LINE_W_UMSK (~(((1U << DSP2_TG_HSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_HSYNC_START_LINE_W_POS)) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W DSP2_TG_HSYNC_LINE_HEIGHT_W -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_HSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_HSYNC_LINE_HEIGHT_W_POS) -#define DSP2_TG_HSYNC_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_HSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_HSYNC_LINE_HEIGHT_W_POS)) - -/* 0x28 : vsync_line */ -#define DSP2_TG_VSYNC_LINE_OFFSET (0x28) -#define DSP2_TG_VSYNC_START_LINE_W DSP2_TG_VSYNC_START_LINE_W -#define DSP2_TG_VSYNC_START_LINE_W_POS (0U) -#define DSP2_TG_VSYNC_START_LINE_W_LEN (16U) -#define DSP2_TG_VSYNC_START_LINE_W_MSK (((1U << DSP2_TG_VSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_VSYNC_START_LINE_W_POS) -#define DSP2_TG_VSYNC_START_LINE_W_UMSK (~(((1U << DSP2_TG_VSYNC_START_LINE_W_LEN) - 1) << DSP2_TG_VSYNC_START_LINE_W_POS)) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W DSP2_TG_VSYNC_LINE_HEIGHT_W -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_POS (16U) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_LEN (16U) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_MSK (((1U << DSP2_TG_VSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_VSYNC_LINE_HEIGHT_W_POS) -#define DSP2_TG_VSYNC_LINE_HEIGHT_W_UMSK (~(((1U << DSP2_TG_VSYNC_LINE_HEIGHT_W_LEN) - 1) << DSP2_TG_VSYNC_LINE_HEIGHT_W_POS)) - -/* 0x2C : vsync_pixel */ -#define DSP2_TG_VSYNC_PIXEL_OFFSET (0x2C) -#define DSP2_TG_VSYNC_START_PIXEL_W DSP2_TG_VSYNC_START_PIXEL_W -#define DSP2_TG_VSYNC_START_PIXEL_W_POS (0U) -#define DSP2_TG_VSYNC_START_PIXEL_W_LEN (16U) -#define DSP2_TG_VSYNC_START_PIXEL_W_MSK (((1U << DSP2_TG_VSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_START_PIXEL_W_POS) -#define DSP2_TG_VSYNC_START_PIXEL_W_UMSK (~(((1U << DSP2_TG_VSYNC_START_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_START_PIXEL_W_POS)) -#define DSP2_TG_VSYNC_END_PIXEL_W DSP2_TG_VSYNC_END_PIXEL_W -#define DSP2_TG_VSYNC_END_PIXEL_W_POS (16U) -#define DSP2_TG_VSYNC_END_PIXEL_W_LEN (16U) -#define DSP2_TG_VSYNC_END_PIXEL_W_MSK (((1U << DSP2_TG_VSYNC_END_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_END_PIXEL_W_POS) -#define DSP2_TG_VSYNC_END_PIXEL_W_UMSK (~(((1U << DSP2_TG_VSYNC_END_PIXEL_W_LEN) - 1) << DSP2_TG_VSYNC_END_PIXEL_W_POS)) - -/* 0x30 : sync_out_inv */ -#define DSP2_TG_SYNC_OUT_INV_OFFSET (0x30) -#define DSP2_TG_VSYNC_OUT_INV_W DSP2_TG_VSYNC_OUT_INV_W -#define DSP2_TG_VSYNC_OUT_INV_W_POS (10U) -#define DSP2_TG_VSYNC_OUT_INV_W_LEN (1U) -#define DSP2_TG_VSYNC_OUT_INV_W_MSK (((1U << DSP2_TG_VSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_VSYNC_OUT_INV_W_POS) -#define DSP2_TG_VSYNC_OUT_INV_W_UMSK (~(((1U << DSP2_TG_VSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_VSYNC_OUT_INV_W_POS)) -#define DSP2_TG_HSYNC_OUT_INV_W DSP2_TG_HSYNC_OUT_INV_W -#define DSP2_TG_HSYNC_OUT_INV_W_POS (11U) -#define DSP2_TG_HSYNC_OUT_INV_W_LEN (1U) -#define DSP2_TG_HSYNC_OUT_INV_W_MSK (((1U << DSP2_TG_HSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_HSYNC_OUT_INV_W_POS) -#define DSP2_TG_HSYNC_OUT_INV_W_UMSK (~(((1U << DSP2_TG_HSYNC_OUT_INV_W_LEN) - 1) << DSP2_TG_HSYNC_OUT_INV_W_POS)) - -/* 0x34 : hvcount_ctrl */ -#define DSP2_TG_HVCOUNT_CTRL_OFFSET (0x34) -#define DSP2_TG_AUTO_HVSYNC_GEN_W DSP2_TG_AUTO_HVSYNC_GEN_W -#define DSP2_TG_AUTO_HVSYNC_GEN_W_POS (0U) -#define DSP2_TG_AUTO_HVSYNC_GEN_W_LEN (1U) -#define DSP2_TG_AUTO_HVSYNC_GEN_W_MSK (((1U << DSP2_TG_AUTO_HVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_HVSYNC_GEN_W_POS) -#define DSP2_TG_AUTO_HVSYNC_GEN_W_UMSK (~(((1U << DSP2_TG_AUTO_HVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_HVSYNC_GEN_W_POS)) -#define DSP2_TG_RSHP_VSYNC_INV_W DSP2_TG_RSHP_VSYNC_INV_W -#define DSP2_TG_RSHP_VSYNC_INV_W_POS (1U) -#define DSP2_TG_RSHP_VSYNC_INV_W_LEN (1U) -#define DSP2_TG_RSHP_VSYNC_INV_W_MSK (((1U << DSP2_TG_RSHP_VSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_VSYNC_INV_W_POS) -#define DSP2_TG_RSHP_VSYNC_INV_W_UMSK (~(((1U << DSP2_TG_RSHP_VSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_VSYNC_INV_W_POS)) -#define DSP2_TG_RSHP_HSYNC_INV_W DSP2_TG_RSHP_HSYNC_INV_W -#define DSP2_TG_RSHP_HSYNC_INV_W_POS (2U) -#define DSP2_TG_RSHP_HSYNC_INV_W_LEN (1U) -#define DSP2_TG_RSHP_HSYNC_INV_W_MSK (((1U << DSP2_TG_RSHP_HSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_HSYNC_INV_W_POS) -#define DSP2_TG_RSHP_HSYNC_INV_W_UMSK (~(((1U << DSP2_TG_RSHP_HSYNC_INV_W_LEN) - 1) << DSP2_TG_RSHP_HSYNC_INV_W_POS)) -#define DSP2_TG_TG_CTRL_START_W DSP2_TG_TG_CTRL_START_W -#define DSP2_TG_TG_CTRL_START_W_POS (3U) -#define DSP2_TG_TG_CTRL_START_W_LEN (1U) -#define DSP2_TG_TG_CTRL_START_W_MSK (((1U << DSP2_TG_TG_CTRL_START_W_LEN) - 1) << DSP2_TG_TG_CTRL_START_W_POS) -#define DSP2_TG_TG_CTRL_START_W_UMSK (~(((1U << DSP2_TG_TG_CTRL_START_W_LEN) - 1) << DSP2_TG_TG_CTRL_START_W_POS)) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W DSP2_TG_AUTO_OHVSYNC_GEN_W -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_POS (4U) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_LEN (1U) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_MSK (((1U << DSP2_TG_AUTO_OHVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_OHVSYNC_GEN_W_POS) -#define DSP2_TG_AUTO_OHVSYNC_GEN_W_UMSK (~(((1U << DSP2_TG_AUTO_OHVSYNC_GEN_W_LEN) - 1) << DSP2_TG_AUTO_OHVSYNC_GEN_W_POS)) -#define DSP2_TG_TG_CTRL_OSTART_W DSP2_TG_TG_CTRL_OSTART_W -#define DSP2_TG_TG_CTRL_OSTART_W_POS (7U) -#define DSP2_TG_TG_CTRL_OSTART_W_LEN (1U) -#define DSP2_TG_TG_CTRL_OSTART_W_MSK (((1U << DSP2_TG_TG_CTRL_OSTART_W_LEN) - 1) << DSP2_TG_TG_CTRL_OSTART_W_POS) -#define DSP2_TG_TG_CTRL_OSTART_W_UMSK (~(((1U << DSP2_TG_TG_CTRL_OSTART_W_LEN) - 1) << DSP2_TG_TG_CTRL_OSTART_W_POS)) - -/* 0xFC : dsp2_apb_ctrl */ -#define DSP2_TG_DSP2_APB_CTRL_OFFSET (0xFC) -#define DSP2_TG_RG_PCLK_FORCE_ON_W DSP2_TG_RG_PCLK_FORCE_ON_W -#define DSP2_TG_RG_PCLK_FORCE_ON_W_POS (0U) -#define DSP2_TG_RG_PCLK_FORCE_ON_W_LEN (16U) -#define DSP2_TG_RG_PCLK_FORCE_ON_W_MSK (((1U << DSP2_TG_RG_PCLK_FORCE_ON_W_LEN) - 1) << DSP2_TG_RG_PCLK_FORCE_ON_W_POS) -#define DSP2_TG_RG_PCLK_FORCE_ON_W_UMSK (~(((1U << DSP2_TG_RG_PCLK_FORCE_ON_W_LEN) - 1) << DSP2_TG_RG_PCLK_FORCE_ON_W_POS)) - -struct dsp2_tg_reg { - /* 0x00 : ip_info */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t IP_ID_r : 8; /* [15: 8], r, 0x13 */ - uint32_t Version_r : 8; /* [23:16], r, 0x28 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ip_info; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[4]; - - /* 0x08 : dvp_mode */ - union { - struct { - uint32_t fhblk_line_on_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t hblk_line_on_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t vcnt_rst_mode_w : 1; /* [ 16], r/w, 0x1 */ - uint32_t hcnt_rst_mode_w : 1; /* [ 17], r/w, 0x1 */ - uint32_t vsync_in_inv_w : 1; /* [ 18], r/w, 0x0 */ - uint32_t hsync_in_inv_w : 1; /* [ 19], r/w, 0x0 */ - uint32_t sync_mode_w : 2; /* [21:20], r/w, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t reg_act_vsync_rst_en_w : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dvp_mode; - - /* 0x0C : total_pixels */ - union { - struct { - uint32_t total_hpixels_w : 16; /* [15: 0], r/w, 0xb0c */ - uint32_t total_vlines_w : 16; /* [31:16], r/w, 0x45a */ - } BF; - uint32_t WORD; - } total_pixels; - - /* 0x10 : act_pixels_1 */ - union { - struct { - uint32_t act_start_pixel_w : 16; /* [15: 0], r/w, 0x384 */ - uint32_t act_pixel_width_w : 16; /* [31:16], r/w, 0x5dc */ - } BF; - uint32_t WORD; - } act_pixels_1; - - /* 0x14 : act_pixels_2 */ - union { - struct { - uint32_t act_start_line_w : 16; /* [15: 0], r/w, 0x1a */ - uint32_t act_line_height_w : 16; /* [31:16], r/w, 0x440 */ - } BF; - uint32_t WORD; - } act_pixels_2; - - /* 0x18 : fact_pixels_1 */ - union { - struct { - uint32_t fact_start_pixel_w : 16; /* [15: 0], r/w, 0x43c */ - uint32_t fact_pixel_width_w : 16; /* [31:16], r/w, 0x780 */ - } BF; - uint32_t WORD; - } fact_pixels_1; - - /* 0x1C : fact_pixels_2 */ - union { - struct { - uint32_t fact_start_line_w : 16; /* [15: 0], r/w, 0x438 */ - uint32_t fact_line_height_w : 16; /* [31:16], r/w, 0x26 */ - } BF; - uint32_t WORD; - } fact_pixels_2; - - /* 0x20 : hsync_pixel */ - union { - struct { - uint32_t hsync_start_pixel_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t hsync_pixel_width_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } hsync_pixel; - - /* 0x24 : hsync_line */ - union { - struct { - uint32_t hsync_start_line_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t hsync_line_height_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } hsync_line; - - /* 0x28 : vsync_line */ - union { - struct { - uint32_t vsync_start_line_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t vsync_line_height_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } vsync_line; - - /* 0x2C : vsync_pixel */ - union { - struct { - uint32_t vsync_start_pixel_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t vsync_end_pixel_w : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } vsync_pixel; - - /* 0x30 : sync_out_inv */ - union { - struct { - uint32_t reserved_0_9 : 10; /* [ 9: 0], rsvd, 0x0 */ - uint32_t vsync_out_inv_w : 1; /* [ 10], r/w, 0x0 */ - uint32_t hsync_out_inv_w : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } sync_out_inv; - - /* 0x34 : hvcount_ctrl */ - union { - struct { - uint32_t auto_hvsync_gen_w : 1; /* [ 0], r/w, 0x0 */ - uint32_t rshp_vsync_inv_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t rshp_hsync_inv_w : 1; /* [ 2], r/w, 0x0 */ - uint32_t tg_ctrl_start_w : 1; /* [ 3], w1p, 0x0 */ - uint32_t auto_ohvsync_gen_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_6 : 2; /* [ 6: 5], rsvd, 0x0 */ - uint32_t tg_ctrl_ostart_w : 1; /* [ 7], w1p, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } hvcount_ctrl; - - /* 0x38 reserved */ - uint8_t RESERVED0x38[196]; - - /* 0xFC : dsp2_apb_ctrl */ - union { - struct { - uint32_t rg_pclk_force_on_w : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } dsp2_apb_ctrl; -}; - -typedef volatile struct dsp2_tg_reg dsp2_tg_reg_t; - -#endif /* __DSP2_TG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dtsrc_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dtsrc_reg.h deleted file mode 100644 index 879e0ebbe8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/dtsrc_reg.h +++ /dev/null @@ -1,505 +0,0 @@ -/** - ****************************************************************************** - * @file dtsrc_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __DTSRC_REG_H__ -#define __DTSRC_REG_H__ - -#include "bl808.h" - -/* 0x0 : config */ -#define DTSRC_CONFIG_OFFSET (0x0) -#define DTSRC_CR_ENABLE DTSRC_CR_ENABLE -#define DTSRC_CR_ENABLE_POS (0U) -#define DTSRC_CR_ENABLE_LEN (1U) -#define DTSRC_CR_ENABLE_MSK (((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS) -#define DTSRC_CR_ENABLE_UMSK (~(((1U << DTSRC_CR_ENABLE_LEN) - 1) << DTSRC_CR_ENABLE_POS)) -#define DTSRC_CR_AXI_EN DTSRC_CR_AXI_EN -#define DTSRC_CR_AXI_EN_POS (1U) -#define DTSRC_CR_AXI_EN_LEN (1U) -#define DTSRC_CR_AXI_EN_MSK (((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS) -#define DTSRC_CR_AXI_EN_UMSK (~(((1U << DTSRC_CR_AXI_EN_LEN) - 1) << DTSRC_CR_AXI_EN_POS)) -#define DTSRC_CR_MODE_CEA_861 DTSRC_CR_MODE_CEA_861 -#define DTSRC_CR_MODE_CEA_861_POS (2U) -#define DTSRC_CR_MODE_CEA_861_LEN (1U) -#define DTSRC_CR_MODE_CEA_861_MSK (((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS) -#define DTSRC_CR_MODE_CEA_861_UMSK (~(((1U << DTSRC_CR_MODE_CEA_861_LEN) - 1) << DTSRC_CR_MODE_CEA_861_POS)) -#define DTSRC_CR_SNSR_EN DTSRC_CR_SNSR_EN -#define DTSRC_CR_SNSR_EN_POS (3U) -#define DTSRC_CR_SNSR_EN_LEN (1U) -#define DTSRC_CR_SNSR_EN_MSK (((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS) -#define DTSRC_CR_SNSR_EN_UMSK (~(((1U << DTSRC_CR_SNSR_EN_LEN) - 1) << DTSRC_CR_SNSR_EN_POS)) -#define DTSRC_CR_SNSR_HSYNC_INV DTSRC_CR_SNSR_HSYNC_INV -#define DTSRC_CR_SNSR_HSYNC_INV_POS (4U) -#define DTSRC_CR_SNSR_HSYNC_INV_LEN (1U) -#define DTSRC_CR_SNSR_HSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS) -#define DTSRC_CR_SNSR_HSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_HSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_HSYNC_INV_POS)) -#define DTSRC_CR_SNSR_VSYNC_INV DTSRC_CR_SNSR_VSYNC_INV -#define DTSRC_CR_SNSR_VSYNC_INV_POS (5U) -#define DTSRC_CR_SNSR_VSYNC_INV_LEN (1U) -#define DTSRC_CR_SNSR_VSYNC_INV_MSK (((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS) -#define DTSRC_CR_SNSR_VSYNC_INV_UMSK (~(((1U << DTSRC_CR_SNSR_VSYNC_INV_LEN) - 1) << DTSRC_CR_SNSR_VSYNC_INV_POS)) -#define DTSRC_CR_AXI_SWAP_MODE DTSRC_CR_AXI_SWAP_MODE -#define DTSRC_CR_AXI_SWAP_MODE_POS (7U) -#define DTSRC_CR_AXI_SWAP_MODE_LEN (1U) -#define DTSRC_CR_AXI_SWAP_MODE_MSK (((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS) -#define DTSRC_CR_AXI_SWAP_MODE_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_MODE_LEN) - 1) << DTSRC_CR_AXI_SWAP_MODE_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SEL DTSRC_CR_AXI_SWAP_IDX_SEL -#define DTSRC_CR_AXI_SWAP_IDX_SEL_POS (8U) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_LEN (4U) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SEL_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SEL_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SEL_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SWM DTSRC_CR_AXI_SWAP_IDX_SWM -#define DTSRC_CR_AXI_SWAP_IDX_SWM_POS (12U) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_LEN (1U) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SWM_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWM_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWM_POS)) -#define DTSRC_CR_AXI_SWAP_IDX_SWV DTSRC_CR_AXI_SWAP_IDX_SWV -#define DTSRC_CR_AXI_SWAP_IDX_SWV_POS (13U) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_LEN (1U) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_MSK (((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS) -#define DTSRC_CR_AXI_SWAP_IDX_SWV_UMSK (~(((1U << DTSRC_CR_AXI_SWAP_IDX_SWV_LEN) - 1) << DTSRC_CR_AXI_SWAP_IDX_SWV_POS)) -#define DTSRC_CR_AXI_DVP_DATA_MODE DTSRC_CR_AXI_DVP_DATA_MODE -#define DTSRC_CR_AXI_DVP_DATA_MODE_POS (16U) -#define DTSRC_CR_AXI_DVP_DATA_MODE_LEN (3U) -#define DTSRC_CR_AXI_DVP_DATA_MODE_MSK (((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS) -#define DTSRC_CR_AXI_DVP_DATA_MODE_UMSK (~(((1U << DTSRC_CR_AXI_DVP_DATA_MODE_LEN) - 1) << DTSRC_CR_AXI_DVP_DATA_MODE_POS)) -#define DTSRC_CR_AXI_B0_SEL DTSRC_CR_AXI_B0_SEL -#define DTSRC_CR_AXI_B0_SEL_POS (20U) -#define DTSRC_CR_AXI_B0_SEL_LEN (2U) -#define DTSRC_CR_AXI_B0_SEL_MSK (((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS) -#define DTSRC_CR_AXI_B0_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B0_SEL_LEN) - 1) << DTSRC_CR_AXI_B0_SEL_POS)) -#define DTSRC_CR_AXI_B1_SEL DTSRC_CR_AXI_B1_SEL -#define DTSRC_CR_AXI_B1_SEL_POS (22U) -#define DTSRC_CR_AXI_B1_SEL_LEN (2U) -#define DTSRC_CR_AXI_B1_SEL_MSK (((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS) -#define DTSRC_CR_AXI_B1_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B1_SEL_LEN) - 1) << DTSRC_CR_AXI_B1_SEL_POS)) -#define DTSRC_CR_AXI_B2_SEL DTSRC_CR_AXI_B2_SEL -#define DTSRC_CR_AXI_B2_SEL_POS (24U) -#define DTSRC_CR_AXI_B2_SEL_LEN (2U) -#define DTSRC_CR_AXI_B2_SEL_MSK (((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS) -#define DTSRC_CR_AXI_B2_SEL_UMSK (~(((1U << DTSRC_CR_AXI_B2_SEL_LEN) - 1) << DTSRC_CR_AXI_B2_SEL_POS)) - -/* 0x4 : frame_size_h */ -#define DTSRC_FRAME_SIZE_H_OFFSET (0x4) -#define DTSRC_CR_TOTAL_H DTSRC_CR_TOTAL_H -#define DTSRC_CR_TOTAL_H_POS (0U) -#define DTSRC_CR_TOTAL_H_LEN (12U) -#define DTSRC_CR_TOTAL_H_MSK (((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS) -#define DTSRC_CR_TOTAL_H_UMSK (~(((1U << DTSRC_CR_TOTAL_H_LEN) - 1) << DTSRC_CR_TOTAL_H_POS)) -#define DTSRC_CR_BLANK_H DTSRC_CR_BLANK_H -#define DTSRC_CR_BLANK_H_POS (16U) -#define DTSRC_CR_BLANK_H_LEN (12U) -#define DTSRC_CR_BLANK_H_MSK (((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS) -#define DTSRC_CR_BLANK_H_UMSK (~(((1U << DTSRC_CR_BLANK_H_LEN) - 1) << DTSRC_CR_BLANK_H_POS)) - -/* 0x8 : frame_size_v */ -#define DTSRC_FRAME_SIZE_V_OFFSET (0x8) -#define DTSRC_CR_TOTAL_V DTSRC_CR_TOTAL_V -#define DTSRC_CR_TOTAL_V_POS (0U) -#define DTSRC_CR_TOTAL_V_LEN (12U) -#define DTSRC_CR_TOTAL_V_MSK (((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS) -#define DTSRC_CR_TOTAL_V_UMSK (~(((1U << DTSRC_CR_TOTAL_V_LEN) - 1) << DTSRC_CR_TOTAL_V_POS)) -#define DTSRC_CR_BLANK_V DTSRC_CR_BLANK_V -#define DTSRC_CR_BLANK_V_POS (16U) -#define DTSRC_CR_BLANK_V_LEN (12U) -#define DTSRC_CR_BLANK_V_MSK (((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS) -#define DTSRC_CR_BLANK_V_UMSK (~(((1U << DTSRC_CR_BLANK_V_LEN) - 1) << DTSRC_CR_BLANK_V_POS)) - -/* 0xC : frame_size_cea_861 */ -#define DTSRC_FRAME_SIZE_CEA_861_OFFSET (0xC) -#define DTSRC_CR_H_DURATION DTSRC_CR_H_DURATION -#define DTSRC_CR_H_DURATION_POS (0U) -#define DTSRC_CR_H_DURATION_LEN (8U) -#define DTSRC_CR_H_DURATION_MSK (((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS) -#define DTSRC_CR_H_DURATION_UMSK (~(((1U << DTSRC_CR_H_DURATION_LEN) - 1) << DTSRC_CR_H_DURATION_POS)) -#define DTSRC_CR_H_PLACEMENT DTSRC_CR_H_PLACEMENT -#define DTSRC_CR_H_PLACEMENT_POS (8U) -#define DTSRC_CR_H_PLACEMENT_LEN (8U) -#define DTSRC_CR_H_PLACEMENT_MSK (((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS) -#define DTSRC_CR_H_PLACEMENT_UMSK (~(((1U << DTSRC_CR_H_PLACEMENT_LEN) - 1) << DTSRC_CR_H_PLACEMENT_POS)) -#define DTSRC_CR_V_DURATION DTSRC_CR_V_DURATION -#define DTSRC_CR_V_DURATION_POS (16U) -#define DTSRC_CR_V_DURATION_LEN (8U) -#define DTSRC_CR_V_DURATION_MSK (((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS) -#define DTSRC_CR_V_DURATION_UMSK (~(((1U << DTSRC_CR_V_DURATION_LEN) - 1) << DTSRC_CR_V_DURATION_POS)) -#define DTSRC_CR_V_PLACEMENT DTSRC_CR_V_PLACEMENT -#define DTSRC_CR_V_PLACEMENT_POS (24U) -#define DTSRC_CR_V_PLACEMENT_LEN (8U) -#define DTSRC_CR_V_PLACEMENT_MSK (((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS) -#define DTSRC_CR_V_PLACEMENT_UMSK (~(((1U << DTSRC_CR_V_PLACEMENT_LEN) - 1) << DTSRC_CR_V_PLACEMENT_POS)) - -/* 0x10 : pix_data_range */ -#define DTSRC_PIX_DATA_RANGE_OFFSET (0x10) -#define DTSRC_CR_DATA_MIN DTSRC_CR_DATA_MIN -#define DTSRC_CR_DATA_MIN_POS (0U) -#define DTSRC_CR_DATA_MIN_LEN (16U) -#define DTSRC_CR_DATA_MIN_MSK (((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS) -#define DTSRC_CR_DATA_MIN_UMSK (~(((1U << DTSRC_CR_DATA_MIN_LEN) - 1) << DTSRC_CR_DATA_MIN_POS)) -#define DTSRC_CR_DATA_MAX DTSRC_CR_DATA_MAX -#define DTSRC_CR_DATA_MAX_POS (16U) -#define DTSRC_CR_DATA_MAX_LEN (16U) -#define DTSRC_CR_DATA_MAX_MSK (((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS) -#define DTSRC_CR_DATA_MAX_UMSK (~(((1U << DTSRC_CR_DATA_MAX_LEN) - 1) << DTSRC_CR_DATA_MAX_POS)) - -/* 0x14 : pix_data_step */ -#define DTSRC_PIX_DATA_STEP_OFFSET (0x14) -#define DTSRC_CR_DATA_STEP DTSRC_CR_DATA_STEP -#define DTSRC_CR_DATA_STEP_POS (0U) -#define DTSRC_CR_DATA_STEP_LEN (8U) -#define DTSRC_CR_DATA_STEP_MSK (((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS) -#define DTSRC_CR_DATA_STEP_UMSK (~(((1U << DTSRC_CR_DATA_STEP_LEN) - 1) << DTSRC_CR_DATA_STEP_POS)) - -/* 0x20 : axi2dvp_setting */ -#define DTSRC_AXI2DVP_SETTING_OFFSET (0x20) -#define DTSRC_CR_AXI_XLEN DTSRC_CR_AXI_XLEN -#define DTSRC_CR_AXI_XLEN_POS (0U) -#define DTSRC_CR_AXI_XLEN_LEN (3U) -#define DTSRC_CR_AXI_XLEN_MSK (((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS) -#define DTSRC_CR_AXI_XLEN_UMSK (~(((1U << DTSRC_CR_AXI_XLEN_LEN) - 1) << DTSRC_CR_AXI_XLEN_POS)) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR DTSRC_CR_AXI_DRAIN_ERR_CLR -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_POS (4U) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN (1U) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_MSK (((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS) -#define DTSRC_CR_AXI_DRAIN_ERR_CLR_UMSK (~(((1U << DTSRC_CR_AXI_DRAIN_ERR_CLR_LEN) - 1) << DTSRC_CR_AXI_DRAIN_ERR_CLR_POS)) -#define DTSRC_CR_AXI_420_MODE DTSRC_CR_AXI_420_MODE -#define DTSRC_CR_AXI_420_MODE_POS (8U) -#define DTSRC_CR_AXI_420_MODE_LEN (1U) -#define DTSRC_CR_AXI_420_MODE_MSK (((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS) -#define DTSRC_CR_AXI_420_MODE_UMSK (~(((1U << DTSRC_CR_AXI_420_MODE_LEN) - 1) << DTSRC_CR_AXI_420_MODE_POS)) -#define DTSRC_CR_AXI_420_UD_SEL DTSRC_CR_AXI_420_UD_SEL -#define DTSRC_CR_AXI_420_UD_SEL_POS (9U) -#define DTSRC_CR_AXI_420_UD_SEL_LEN (1U) -#define DTSRC_CR_AXI_420_UD_SEL_MSK (((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS) -#define DTSRC_CR_AXI_420_UD_SEL_UMSK (~(((1U << DTSRC_CR_AXI_420_UD_SEL_LEN) - 1) << DTSRC_CR_AXI_420_UD_SEL_POS)) -#define DTSRC_CR_QOS_SW_MODE DTSRC_CR_QOS_SW_MODE -#define DTSRC_CR_QOS_SW_MODE_POS (10U) -#define DTSRC_CR_QOS_SW_MODE_LEN (1U) -#define DTSRC_CR_QOS_SW_MODE_MSK (((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS) -#define DTSRC_CR_QOS_SW_MODE_UMSK (~(((1U << DTSRC_CR_QOS_SW_MODE_LEN) - 1) << DTSRC_CR_QOS_SW_MODE_POS)) -#define DTSRC_CR_QOS_SW DTSRC_CR_QOS_SW -#define DTSRC_CR_QOS_SW_POS (11U) -#define DTSRC_CR_QOS_SW_LEN (1U) -#define DTSRC_CR_QOS_SW_MSK (((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS) -#define DTSRC_CR_QOS_SW_UMSK (~(((1U << DTSRC_CR_QOS_SW_LEN) - 1) << DTSRC_CR_QOS_SW_POS)) - -/* 0x24 : axi2dvp_start_addr_by */ -#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET (0x24) -#define DTSRC_CR_AXI_ADDR_START_BY DTSRC_CR_AXI_ADDR_START_BY -#define DTSRC_CR_AXI_ADDR_START_BY_POS (0U) -#define DTSRC_CR_AXI_ADDR_START_BY_LEN (32U) -#define DTSRC_CR_AXI_ADDR_START_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS) -#define DTSRC_CR_AXI_ADDR_START_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_BY_POS)) - -/* 0x28 : axi2dvp_burst_cnt */ -#define DTSRC_AXI2DVP_BURST_CNT_OFFSET (0x28) -#define DTSRC_CR_AXI_FRAME_BC DTSRC_CR_AXI_FRAME_BC -#define DTSRC_CR_AXI_FRAME_BC_POS (0U) -#define DTSRC_CR_AXI_FRAME_BC_LEN (32U) -#define DTSRC_CR_AXI_FRAME_BC_MSK (((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS) -#define DTSRC_CR_AXI_FRAME_BC_UMSK (~(((1U << DTSRC_CR_AXI_FRAME_BC_LEN) - 1) << DTSRC_CR_AXI_FRAME_BC_POS)) - -/* 0x2C : axi2dvp_status */ -#define DTSRC_AXI2DVP_STATUS_OFFSET (0x2C) -#define DTSRC_ST_AXI_FIFO_CNT_BY DTSRC_ST_AXI_FIFO_CNT_BY -#define DTSRC_ST_AXI_FIFO_CNT_BY_POS (0U) -#define DTSRC_ST_AXI_FIFO_CNT_BY_LEN (7U) -#define DTSRC_ST_AXI_FIFO_CNT_BY_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS) -#define DTSRC_ST_AXI_FIFO_CNT_BY_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_BY_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_BY_POS)) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY DTSRC_ST_AXI_DRAIN_ERROR_BY -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_POS (7U) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN (1U) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS) -#define DTSRC_ST_AXI_DRAIN_ERROR_BY_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_BY_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_BY_POS)) -#define DTSRC_ST_AXI_STATE_IDLE_BY DTSRC_ST_AXI_STATE_IDLE_BY -#define DTSRC_ST_AXI_STATE_IDLE_BY_POS (8U) -#define DTSRC_ST_AXI_STATE_IDLE_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_IDLE_BY_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS) -#define DTSRC_ST_AXI_STATE_IDLE_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_BY_POS)) -#define DTSRC_ST_AXI_STATE_FUNC_BY DTSRC_ST_AXI_STATE_FUNC_BY -#define DTSRC_ST_AXI_STATE_FUNC_BY_POS (9U) -#define DTSRC_ST_AXI_STATE_FUNC_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_FUNC_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS) -#define DTSRC_ST_AXI_STATE_FUNC_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_BY_POS)) -#define DTSRC_ST_AXI_STATE_FLSH_BY DTSRC_ST_AXI_STATE_FLSH_BY -#define DTSRC_ST_AXI_STATE_FLSH_BY_POS (10U) -#define DTSRC_ST_AXI_STATE_FLSH_BY_LEN (1U) -#define DTSRC_ST_AXI_STATE_FLSH_BY_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS) -#define DTSRC_ST_AXI_STATE_FLSH_BY_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_BY_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_BY_POS)) -#define DTSRC_ST_AXI_FIFO_CNT_UV DTSRC_ST_AXI_FIFO_CNT_UV -#define DTSRC_ST_AXI_FIFO_CNT_UV_POS (16U) -#define DTSRC_ST_AXI_FIFO_CNT_UV_LEN (7U) -#define DTSRC_ST_AXI_FIFO_CNT_UV_MSK (((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS) -#define DTSRC_ST_AXI_FIFO_CNT_UV_UMSK (~(((1U << DTSRC_ST_AXI_FIFO_CNT_UV_LEN) - 1) << DTSRC_ST_AXI_FIFO_CNT_UV_POS)) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV DTSRC_ST_AXI_DRAIN_ERROR_UV -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_POS (23U) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN (1U) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_MSK (((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS) -#define DTSRC_ST_AXI_DRAIN_ERROR_UV_UMSK (~(((1U << DTSRC_ST_AXI_DRAIN_ERROR_UV_LEN) - 1) << DTSRC_ST_AXI_DRAIN_ERROR_UV_POS)) -#define DTSRC_ST_AXI_STATE_IDLE_UV DTSRC_ST_AXI_STATE_IDLE_UV -#define DTSRC_ST_AXI_STATE_IDLE_UV_POS (24U) -#define DTSRC_ST_AXI_STATE_IDLE_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_IDLE_UV_MSK (((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS) -#define DTSRC_ST_AXI_STATE_IDLE_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_IDLE_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_IDLE_UV_POS)) -#define DTSRC_ST_AXI_STATE_FUNC_UV DTSRC_ST_AXI_STATE_FUNC_UV -#define DTSRC_ST_AXI_STATE_FUNC_UV_POS (25U) -#define DTSRC_ST_AXI_STATE_FUNC_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_FUNC_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS) -#define DTSRC_ST_AXI_STATE_FUNC_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FUNC_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FUNC_UV_POS)) -#define DTSRC_ST_AXI_STATE_FLSH_UV DTSRC_ST_AXI_STATE_FLSH_UV -#define DTSRC_ST_AXI_STATE_FLSH_UV_POS (26U) -#define DTSRC_ST_AXI_STATE_FLSH_UV_LEN (1U) -#define DTSRC_ST_AXI_STATE_FLSH_UV_MSK (((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS) -#define DTSRC_ST_AXI_STATE_FLSH_UV_UMSK (~(((1U << DTSRC_ST_AXI_STATE_FLSH_UV_LEN) - 1) << DTSRC_ST_AXI_STATE_FLSH_UV_POS)) - -/* 0x30 : axi2dvp_swap_addr_by */ -#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET (0x30) -#define DTSRC_CR_AXI_ADDR_SWAP_BY DTSRC_CR_AXI_ADDR_SWAP_BY -#define DTSRC_CR_AXI_ADDR_SWAP_BY_POS (0U) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_LEN (32U) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS) -#define DTSRC_CR_AXI_ADDR_SWAP_BY_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_BY_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_BY_POS)) - -/* 0x34 : axi2dvp_prefetch */ -#define DTSRC_AXI2DVP_PREFETCH_OFFSET (0x34) -#define DTSRC_CR_PREFETCH_V DTSRC_CR_PREFETCH_V -#define DTSRC_CR_PREFETCH_V_POS (0U) -#define DTSRC_CR_PREFETCH_V_LEN (12U) -#define DTSRC_CR_PREFETCH_V_MSK (((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS) -#define DTSRC_CR_PREFETCH_V_UMSK (~(((1U << DTSRC_CR_PREFETCH_V_LEN) - 1) << DTSRC_CR_PREFETCH_V_POS)) - -/* 0x38 : snsr2dvp_wait_pos */ -#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET (0x38) -#define DTSRC_CR_SNSR_FIFO_TH DTSRC_CR_SNSR_FIFO_TH -#define DTSRC_CR_SNSR_FIFO_TH_POS (0U) -#define DTSRC_CR_SNSR_FIFO_TH_LEN (11U) -#define DTSRC_CR_SNSR_FIFO_TH_MSK (((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS) -#define DTSRC_CR_SNSR_FIFO_TH_UMSK (~(((1U << DTSRC_CR_SNSR_FIFO_TH_LEN) - 1) << DTSRC_CR_SNSR_FIFO_TH_POS)) - -/* 0x40 : axi2dvp_start_addr_uv */ -#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET (0x40) -#define DTSRC_CR_AXI_ADDR_START_UV DTSRC_CR_AXI_ADDR_START_UV -#define DTSRC_CR_AXI_ADDR_START_UV_POS (0U) -#define DTSRC_CR_AXI_ADDR_START_UV_LEN (32U) -#define DTSRC_CR_AXI_ADDR_START_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS) -#define DTSRC_CR_AXI_ADDR_START_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_START_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_START_UV_POS)) - -/* 0x44 : axi2dvp_swap_addr_uv */ -#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET (0x44) -#define DTSRC_CR_AXI_ADDR_SWAP_UV DTSRC_CR_AXI_ADDR_SWAP_UV -#define DTSRC_CR_AXI_ADDR_SWAP_UV_POS (0U) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_LEN (32U) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_MSK (((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS) -#define DTSRC_CR_AXI_ADDR_SWAP_UV_UMSK (~(((1U << DTSRC_CR_AXI_ADDR_SWAP_UV_LEN) - 1) << DTSRC_CR_AXI_ADDR_SWAP_UV_POS)) - -struct dtsrc_reg { - /* 0x0 : config */ - union { - struct { - uint32_t cr_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_axi_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_mode_cea_861 : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_snsr_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_snsr_hsync_inv : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_snsr_vsync_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t cr_axi_swap_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_sel : 4; /* [11: 8], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_swm : 1; /* [ 12], r/w, 0x0 */ - uint32_t cr_axi_swap_idx_swv : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_axi_dvp_data_mode : 3; /* [18:16], r/w, 0x0 */ - uint32_t reserved_19 : 1; /* [ 19], rsvd, 0x0 */ - uint32_t cr_axi_b0_sel : 2; /* [21:20], r/w, 0x0 */ - uint32_t cr_axi_b1_sel : 2; /* [23:22], r/w, 0x1 */ - uint32_t cr_axi_b2_sel : 2; /* [25:24], r/w, 0x2 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } config; - - /* 0x4 : frame_size_h */ - union { - struct { - uint32_t cr_total_h : 12; /* [11: 0], r/w, 0x897 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_blank_h : 12; /* [27:16], r/w, 0x117 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } frame_size_h; - - /* 0x8 : frame_size_v */ - union { - struct { - uint32_t cr_total_v : 12; /* [11: 0], r/w, 0x464 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_blank_v : 12; /* [27:16], r/w, 0x2c */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } frame_size_v; - - /* 0xC : frame_size_cea_861 */ - union { - struct { - uint32_t cr_h_duration : 8; /* [ 7: 0], r/w, 0x83 */ - uint32_t cr_h_placement : 8; /* [15: 8], r/w, 0x57 */ - uint32_t cr_v_duration : 8; /* [23:16], r/w, 0x8 */ - uint32_t cr_v_placement : 8; /* [31:24], r/w, 0x3 */ - } BF; - uint32_t WORD; - } frame_size_cea_861; - - /* 0x10 : pix_data_range */ - union { - struct { - uint32_t cr_data_min : 16; /* [15: 0], r/w, 0x0 */ - uint32_t cr_data_max : 16; /* [31:16], r/w, 0xffff */ - } BF; - uint32_t WORD; - } pix_data_range; - - /* 0x14 : pix_data_step */ - union { - struct { - uint32_t cr_data_step : 8; /* [ 7: 0], r/w, 0x1 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pix_data_step; - - /* 0x18 reserved */ - uint8_t RESERVED0x18[8]; - - /* 0x20 : axi2dvp_setting */ - union { - struct { - uint32_t cr_axi_xlen : 3; /* [ 2: 0], r/w, 0x3 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_axi_drain_err_clr : 1; /* [ 4], w1p, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cr_axi_420_mode : 1; /* [ 8], r/w, 0x0 */ - uint32_t cr_axi_420_ud_sel : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_qos_sw_mode : 1; /* [ 10], r/w, 0x0 */ - uint32_t cr_qos_sw : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_setting; - - /* 0x24 : axi2dvp_start_addr_by */ - union { - struct { - uint32_t cr_axi_addr_start_by : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_start_addr_by; - - /* 0x28 : axi2dvp_burst_cnt */ - union { - struct { - uint32_t cr_axi_frame_bc : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_burst_cnt; - - /* 0x2C : axi2dvp_status */ - union { - struct { - uint32_t st_axi_fifo_cnt_by : 7; /* [ 6: 0], r, 0x0 */ - uint32_t st_axi_drain_error_by : 1; /* [ 7], r, 0x0 */ - uint32_t st_axi_state_idle_by : 1; /* [ 8], r, 0x0 */ - uint32_t st_axi_state_func_by : 1; /* [ 9], r, 0x0 */ - uint32_t st_axi_state_flsh_by : 1; /* [ 10], r, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t st_axi_fifo_cnt_uv : 7; /* [22:16], r, 0x0 */ - uint32_t st_axi_drain_error_uv : 1; /* [ 23], r, 0x0 */ - uint32_t st_axi_state_idle_uv : 1; /* [ 24], r, 0x0 */ - uint32_t st_axi_state_func_uv : 1; /* [ 25], r, 0x0 */ - uint32_t st_axi_state_flsh_uv : 1; /* [ 26], r, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_status; - - /* 0x30 : axi2dvp_swap_addr_by */ - union { - struct { - uint32_t cr_axi_addr_swap_by : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_swap_addr_by; - - /* 0x34 : axi2dvp_prefetch */ - union { - struct { - uint32_t cr_prefetch_v : 12; /* [11: 0], r/w, 0x28 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_prefetch; - - /* 0x38 : snsr2dvp_wait_pos */ - union { - struct { - uint32_t cr_snsr_fifo_th : 11; /* [10: 0], r/w, 0x8b */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } snsr2dvp_wait_pos; - - /* 0x3c reserved */ - uint8_t RESERVED0x3c[4]; - - /* 0x40 : axi2dvp_start_addr_uv */ - union { - struct { - uint32_t cr_axi_addr_start_uv : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_start_addr_uv; - - /* 0x44 : axi2dvp_swap_addr_uv */ - union { - struct { - uint32_t cr_axi_addr_swap_uv : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } axi2dvp_swap_addr_uv; -}; - -typedef volatile struct dtsrc_reg dtsrc_reg_t; - -#endif /* __DTSRC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emac_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emac_reg.h deleted file mode 100644 index afb93d6598..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emac_reg.h +++ /dev/null @@ -1,583 +0,0 @@ -/** - ****************************************************************************** - * @file emac_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __EMAC_REG_H__ -#define __EMAC_REG_H__ - -#include "bl808.h" - -/* 0x0 : MODE */ -#define EMAC_MODE_OFFSET (0x0) -#define EMAC_RXEN EMAC_RXEN -#define EMAC_RXEN_POS (0U) -#define EMAC_RXEN_LEN (1U) -#define EMAC_RXEN_MSK (((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS) -#define EMAC_RXEN_UMSK (~(((1U << EMAC_RXEN_LEN) - 1) << EMAC_RXEN_POS)) -#define EMAC_TXEN EMAC_TXEN -#define EMAC_TXEN_POS (1U) -#define EMAC_TXEN_LEN (1U) -#define EMAC_TXEN_MSK (((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS) -#define EMAC_TXEN_UMSK (~(((1U << EMAC_TXEN_LEN) - 1) << EMAC_TXEN_POS)) -#define EMAC_NOPRE EMAC_NOPRE -#define EMAC_NOPRE_POS (2U) -#define EMAC_NOPRE_LEN (1U) -#define EMAC_NOPRE_MSK (((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS) -#define EMAC_NOPRE_UMSK (~(((1U << EMAC_NOPRE_LEN) - 1) << EMAC_NOPRE_POS)) -#define EMAC_BRO EMAC_BRO -#define EMAC_BRO_POS (3U) -#define EMAC_BRO_LEN (1U) -#define EMAC_BRO_MSK (((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS) -#define EMAC_BRO_UMSK (~(((1U << EMAC_BRO_LEN) - 1) << EMAC_BRO_POS)) -#define EMAC_PRO EMAC_PRO -#define EMAC_PRO_POS (5U) -#define EMAC_PRO_LEN (1U) -#define EMAC_PRO_MSK (((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS) -#define EMAC_PRO_UMSK (~(((1U << EMAC_PRO_LEN) - 1) << EMAC_PRO_POS)) -#define EMAC_IFG EMAC_IFG -#define EMAC_IFG_POS (6U) -#define EMAC_IFG_LEN (1U) -#define EMAC_IFG_MSK (((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS) -#define EMAC_IFG_UMSK (~(((1U << EMAC_IFG_LEN) - 1) << EMAC_IFG_POS)) -#define EMAC_FULLD EMAC_FULLD -#define EMAC_FULLD_POS (10U) -#define EMAC_FULLD_LEN (1U) -#define EMAC_FULLD_MSK (((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS) -#define EMAC_FULLD_UMSK (~(((1U << EMAC_FULLD_LEN) - 1) << EMAC_FULLD_POS)) -#define EMAC_CRCEN EMAC_CRCEN -#define EMAC_CRCEN_POS (13U) -#define EMAC_CRCEN_LEN (1U) -#define EMAC_CRCEN_MSK (((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS) -#define EMAC_CRCEN_UMSK (~(((1U << EMAC_CRCEN_LEN) - 1) << EMAC_CRCEN_POS)) -#define EMAC_HUGEN EMAC_HUGEN -#define EMAC_HUGEN_POS (14U) -#define EMAC_HUGEN_LEN (1U) -#define EMAC_HUGEN_MSK (((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS) -#define EMAC_HUGEN_UMSK (~(((1U << EMAC_HUGEN_LEN) - 1) << EMAC_HUGEN_POS)) -#define EMAC_PAD EMAC_PAD -#define EMAC_PAD_POS (15U) -#define EMAC_PAD_LEN (1U) -#define EMAC_PAD_MSK (((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS) -#define EMAC_PAD_UMSK (~(((1U << EMAC_PAD_LEN) - 1) << EMAC_PAD_POS)) -#define EMAC_RECSMALL EMAC_RECSMALL -#define EMAC_RECSMALL_POS (16U) -#define EMAC_RECSMALL_LEN (1U) -#define EMAC_RECSMALL_MSK (((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS) -#define EMAC_RECSMALL_UMSK (~(((1U << EMAC_RECSMALL_LEN) - 1) << EMAC_RECSMALL_POS)) -#define EMAC_RMII_EN EMAC_RMII_EN -#define EMAC_RMII_EN_POS (17U) -#define EMAC_RMII_EN_LEN (1U) -#define EMAC_RMII_EN_MSK (((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS) -#define EMAC_RMII_EN_UMSK (~(((1U << EMAC_RMII_EN_LEN) - 1) << EMAC_RMII_EN_POS)) - -/* 0x4 : INT_SOURCE */ -#define EMAC_INT_SOURCE_OFFSET (0x4) -#define EMAC_TXB EMAC_TXB -#define EMAC_TXB_POS (0U) -#define EMAC_TXB_LEN (1U) -#define EMAC_TXB_MSK (((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS) -#define EMAC_TXB_UMSK (~(((1U << EMAC_TXB_LEN) - 1) << EMAC_TXB_POS)) -#define EMAC_TXE EMAC_TXE -#define EMAC_TXE_POS (1U) -#define EMAC_TXE_LEN (1U) -#define EMAC_TXE_MSK (((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS) -#define EMAC_TXE_UMSK (~(((1U << EMAC_TXE_LEN) - 1) << EMAC_TXE_POS)) -#define EMAC_RXB EMAC_RXB -#define EMAC_RXB_POS (2U) -#define EMAC_RXB_LEN (1U) -#define EMAC_RXB_MSK (((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS) -#define EMAC_RXB_UMSK (~(((1U << EMAC_RXB_LEN) - 1) << EMAC_RXB_POS)) -#define EMAC_RXE EMAC_RXE -#define EMAC_RXE_POS (3U) -#define EMAC_RXE_LEN (1U) -#define EMAC_RXE_MSK (((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS) -#define EMAC_RXE_UMSK (~(((1U << EMAC_RXE_LEN) - 1) << EMAC_RXE_POS)) -#define EMAC_BUSY EMAC_BUSY -#define EMAC_BUSY_POS (4U) -#define EMAC_BUSY_LEN (1U) -#define EMAC_BUSY_MSK (((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS) -#define EMAC_BUSY_UMSK (~(((1U << EMAC_BUSY_LEN) - 1) << EMAC_BUSY_POS)) -#define EMAC_TXC EMAC_TXC -#define EMAC_TXC_POS (5U) -#define EMAC_TXC_LEN (1U) -#define EMAC_TXC_MSK (((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS) -#define EMAC_TXC_UMSK (~(((1U << EMAC_TXC_LEN) - 1) << EMAC_TXC_POS)) -#define EMAC_RXC EMAC_RXC -#define EMAC_RXC_POS (6U) -#define EMAC_RXC_LEN (1U) -#define EMAC_RXC_MSK (((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS) -#define EMAC_RXC_UMSK (~(((1U << EMAC_RXC_LEN) - 1) << EMAC_RXC_POS)) - -/* 0x8 : INT_MASK */ -#define EMAC_INT_MASK_OFFSET (0x8) -#define EMAC_TXB_M EMAC_TXB_M -#define EMAC_TXB_M_POS (0U) -#define EMAC_TXB_M_LEN (1U) -#define EMAC_TXB_M_MSK (((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS) -#define EMAC_TXB_M_UMSK (~(((1U << EMAC_TXB_M_LEN) - 1) << EMAC_TXB_M_POS)) -#define EMAC_TXE_M EMAC_TXE_M -#define EMAC_TXE_M_POS (1U) -#define EMAC_TXE_M_LEN (1U) -#define EMAC_TXE_M_MSK (((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS) -#define EMAC_TXE_M_UMSK (~(((1U << EMAC_TXE_M_LEN) - 1) << EMAC_TXE_M_POS)) -#define EMAC_RXB_M EMAC_RXB_M -#define EMAC_RXB_M_POS (2U) -#define EMAC_RXB_M_LEN (1U) -#define EMAC_RXB_M_MSK (((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS) -#define EMAC_RXB_M_UMSK (~(((1U << EMAC_RXB_M_LEN) - 1) << EMAC_RXB_M_POS)) -#define EMAC_RXE_M EMAC_RXE_M -#define EMAC_RXE_M_POS (3U) -#define EMAC_RXE_M_LEN (1U) -#define EMAC_RXE_M_MSK (((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS) -#define EMAC_RXE_M_UMSK (~(((1U << EMAC_RXE_M_LEN) - 1) << EMAC_RXE_M_POS)) -#define EMAC_BUSY_M EMAC_BUSY_M -#define EMAC_BUSY_M_POS (4U) -#define EMAC_BUSY_M_LEN (1U) -#define EMAC_BUSY_M_MSK (((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS) -#define EMAC_BUSY_M_UMSK (~(((1U << EMAC_BUSY_M_LEN) - 1) << EMAC_BUSY_M_POS)) -#define EMAC_TXC_M EMAC_TXC_M -#define EMAC_TXC_M_POS (5U) -#define EMAC_TXC_M_LEN (1U) -#define EMAC_TXC_M_MSK (((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS) -#define EMAC_TXC_M_UMSK (~(((1U << EMAC_TXC_M_LEN) - 1) << EMAC_TXC_M_POS)) -#define EMAC_RXC_M EMAC_RXC_M -#define EMAC_RXC_M_POS (6U) -#define EMAC_RXC_M_LEN (1U) -#define EMAC_RXC_M_MSK (((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS) -#define EMAC_RXC_M_UMSK (~(((1U << EMAC_RXC_M_LEN) - 1) << EMAC_RXC_M_POS)) - -/* 0xC : IPGT */ -#define EMAC_IPGT_OFFSET (0xC) -#define EMAC_IPGT EMAC_IPGT -#define EMAC_IPGT_POS (0U) -#define EMAC_IPGT_LEN (7U) -#define EMAC_IPGT_MSK (((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS) -#define EMAC_IPGT_UMSK (~(((1U << EMAC_IPGT_LEN) - 1) << EMAC_IPGT_POS)) - -/* 0x18 : PACKETLEN */ -#define EMAC_PACKETLEN_OFFSET (0x18) -#define EMAC_MAXFL EMAC_MAXFL -#define EMAC_MAXFL_POS (0U) -#define EMAC_MAXFL_LEN (16U) -#define EMAC_MAXFL_MSK (((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS) -#define EMAC_MAXFL_UMSK (~(((1U << EMAC_MAXFL_LEN) - 1) << EMAC_MAXFL_POS)) -#define EMAC_MINFL EMAC_MINFL -#define EMAC_MINFL_POS (16U) -#define EMAC_MINFL_LEN (16U) -#define EMAC_MINFL_MSK (((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS) -#define EMAC_MINFL_UMSK (~(((1U << EMAC_MINFL_LEN) - 1) << EMAC_MINFL_POS)) - -/* 0x1C : COLLCONFIG */ -#define EMAC_COLLCONFIG_OFFSET (0x1C) -#define EMAC_COLLVALID EMAC_COLLVALID -#define EMAC_COLLVALID_POS (0U) -#define EMAC_COLLVALID_LEN (6U) -#define EMAC_COLLVALID_MSK (((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS) -#define EMAC_COLLVALID_UMSK (~(((1U << EMAC_COLLVALID_LEN) - 1) << EMAC_COLLVALID_POS)) -#define EMAC_MAXRET EMAC_MAXRET -#define EMAC_MAXRET_POS (16U) -#define EMAC_MAXRET_LEN (4U) -#define EMAC_MAXRET_MSK (((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS) -#define EMAC_MAXRET_UMSK (~(((1U << EMAC_MAXRET_LEN) - 1) << EMAC_MAXRET_POS)) - -/* 0x20 : TX_BD_NUM */ -#define EMAC_TX_BD_NUM_OFFSET (0x20) -#define EMAC_TXBDNUM EMAC_TXBDNUM -#define EMAC_TXBDNUM_POS (0U) -#define EMAC_TXBDNUM_LEN (8U) -#define EMAC_TXBDNUM_MSK (((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS) -#define EMAC_TXBDNUM_UMSK (~(((1U << EMAC_TXBDNUM_LEN) - 1) << EMAC_TXBDNUM_POS)) -#define EMAC_TXBDPTR EMAC_TXBDPTR -#define EMAC_TXBDPTR_POS (16U) -#define EMAC_TXBDPTR_LEN (7U) -#define EMAC_TXBDPTR_MSK (((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS) -#define EMAC_TXBDPTR_UMSK (~(((1U << EMAC_TXBDPTR_LEN) - 1) << EMAC_TXBDPTR_POS)) -#define EMAC_RXBDPTR EMAC_RXBDPTR -#define EMAC_RXBDPTR_POS (24U) -#define EMAC_RXBDPTR_LEN (7U) -#define EMAC_RXBDPTR_MSK (((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS) -#define EMAC_RXBDPTR_UMSK (~(((1U << EMAC_RXBDPTR_LEN) - 1) << EMAC_RXBDPTR_POS)) - -/* 0x28 : MIIMODE */ -#define EMAC_MIIMODE_OFFSET (0x28) -#define EMAC_CLKDIV EMAC_CLKDIV -#define EMAC_CLKDIV_POS (0U) -#define EMAC_CLKDIV_LEN (8U) -#define EMAC_CLKDIV_MSK (((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS) -#define EMAC_CLKDIV_UMSK (~(((1U << EMAC_CLKDIV_LEN) - 1) << EMAC_CLKDIV_POS)) -#define EMAC_MIINOPRE EMAC_MIINOPRE -#define EMAC_MIINOPRE_POS (8U) -#define EMAC_MIINOPRE_LEN (1U) -#define EMAC_MIINOPRE_MSK (((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS) -#define EMAC_MIINOPRE_UMSK (~(((1U << EMAC_MIINOPRE_LEN) - 1) << EMAC_MIINOPRE_POS)) - -/* 0x2C : MIICOMMAND */ -#define EMAC_MIICOMMAND_OFFSET (0x2C) -#define EMAC_SCANSTAT EMAC_SCANSTAT -#define EMAC_SCANSTAT_POS (0U) -#define EMAC_SCANSTAT_LEN (1U) -#define EMAC_SCANSTAT_MSK (((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS) -#define EMAC_SCANSTAT_UMSK (~(((1U << EMAC_SCANSTAT_LEN) - 1) << EMAC_SCANSTAT_POS)) -#define EMAC_RSTAT EMAC_RSTAT -#define EMAC_RSTAT_POS (1U) -#define EMAC_RSTAT_LEN (1U) -#define EMAC_RSTAT_MSK (((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS) -#define EMAC_RSTAT_UMSK (~(((1U << EMAC_RSTAT_LEN) - 1) << EMAC_RSTAT_POS)) -#define EMAC_WCTRLDATA EMAC_WCTRLDATA -#define EMAC_WCTRLDATA_POS (2U) -#define EMAC_WCTRLDATA_LEN (1U) -#define EMAC_WCTRLDATA_MSK (((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS) -#define EMAC_WCTRLDATA_UMSK (~(((1U << EMAC_WCTRLDATA_LEN) - 1) << EMAC_WCTRLDATA_POS)) - -/* 0x30 : MIIADDRESS */ -#define EMAC_MIIADDRESS_OFFSET (0x30) -#define EMAC_FIAD EMAC_FIAD -#define EMAC_FIAD_POS (0U) -#define EMAC_FIAD_LEN (5U) -#define EMAC_FIAD_MSK (((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS) -#define EMAC_FIAD_UMSK (~(((1U << EMAC_FIAD_LEN) - 1) << EMAC_FIAD_POS)) -#define EMAC_RGAD EMAC_RGAD -#define EMAC_RGAD_POS (8U) -#define EMAC_RGAD_LEN (5U) -#define EMAC_RGAD_MSK (((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS) -#define EMAC_RGAD_UMSK (~(((1U << EMAC_RGAD_LEN) - 1) << EMAC_RGAD_POS)) - -/* 0x34 : MIITX_DATA */ -#define EMAC_MIITX_DATA_OFFSET (0x34) -#define EMAC_CTRLDATA EMAC_CTRLDATA -#define EMAC_CTRLDATA_POS (0U) -#define EMAC_CTRLDATA_LEN (16U) -#define EMAC_CTRLDATA_MSK (((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS) -#define EMAC_CTRLDATA_UMSK (~(((1U << EMAC_CTRLDATA_LEN) - 1) << EMAC_CTRLDATA_POS)) - -/* 0x38 : MIIRX_DATA */ -#define EMAC_MIIRX_DATA_OFFSET (0x38) -#define EMAC_PRSD EMAC_PRSD -#define EMAC_PRSD_POS (0U) -#define EMAC_PRSD_LEN (16U) -#define EMAC_PRSD_MSK (((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS) -#define EMAC_PRSD_UMSK (~(((1U << EMAC_PRSD_LEN) - 1) << EMAC_PRSD_POS)) - -/* 0x3C : MIISTATUS */ -#define EMAC_MIISTATUS_OFFSET (0x3C) -#define EMAC_MIIM_LINKFAIL EMAC_MIIM_LINKFAIL -#define EMAC_MIIM_LINKFAIL_POS (0U) -#define EMAC_MIIM_LINKFAIL_LEN (1U) -#define EMAC_MIIM_LINKFAIL_MSK (((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS) -#define EMAC_MIIM_LINKFAIL_UMSK (~(((1U << EMAC_MIIM_LINKFAIL_LEN) - 1) << EMAC_MIIM_LINKFAIL_POS)) -#define EMAC_MIIM_BUSY EMAC_MIIM_BUSY -#define EMAC_MIIM_BUSY_POS (1U) -#define EMAC_MIIM_BUSY_LEN (1U) -#define EMAC_MIIM_BUSY_MSK (((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS) -#define EMAC_MIIM_BUSY_UMSK (~(((1U << EMAC_MIIM_BUSY_LEN) - 1) << EMAC_MIIM_BUSY_POS)) - -/* 0x40 : MAC_ADDR0 */ -#define EMAC_MAC_ADDR0_OFFSET (0x40) -#define EMAC_MAC_B5 EMAC_MAC_B5 -#define EMAC_MAC_B5_POS (0U) -#define EMAC_MAC_B5_LEN (8U) -#define EMAC_MAC_B5_MSK (((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS) -#define EMAC_MAC_B5_UMSK (~(((1U << EMAC_MAC_B5_LEN) - 1) << EMAC_MAC_B5_POS)) -#define EMAC_MAC_B4 EMAC_MAC_B4 -#define EMAC_MAC_B4_POS (8U) -#define EMAC_MAC_B4_LEN (8U) -#define EMAC_MAC_B4_MSK (((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS) -#define EMAC_MAC_B4_UMSK (~(((1U << EMAC_MAC_B4_LEN) - 1) << EMAC_MAC_B4_POS)) -#define EMAC_MAC_B3 EMAC_MAC_B3 -#define EMAC_MAC_B3_POS (16U) -#define EMAC_MAC_B3_LEN (8U) -#define EMAC_MAC_B3_MSK (((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS) -#define EMAC_MAC_B3_UMSK (~(((1U << EMAC_MAC_B3_LEN) - 1) << EMAC_MAC_B3_POS)) -#define EMAC_MAC_B2 EMAC_MAC_B2 -#define EMAC_MAC_B2_POS (24U) -#define EMAC_MAC_B2_LEN (8U) -#define EMAC_MAC_B2_MSK (((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS) -#define EMAC_MAC_B2_UMSK (~(((1U << EMAC_MAC_B2_LEN) - 1) << EMAC_MAC_B2_POS)) - -/* 0x44 : MAC_ADDR1 */ -#define EMAC_MAC_ADDR1_OFFSET (0x44) -#define EMAC_MAC_B1 EMAC_MAC_B1 -#define EMAC_MAC_B1_POS (0U) -#define EMAC_MAC_B1_LEN (8U) -#define EMAC_MAC_B1_MSK (((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS) -#define EMAC_MAC_B1_UMSK (~(((1U << EMAC_MAC_B1_LEN) - 1) << EMAC_MAC_B1_POS)) -#define EMAC_MAC_B0 EMAC_MAC_B0 -#define EMAC_MAC_B0_POS (8U) -#define EMAC_MAC_B0_LEN (8U) -#define EMAC_MAC_B0_MSK (((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS) -#define EMAC_MAC_B0_UMSK (~(((1U << EMAC_MAC_B0_LEN) - 1) << EMAC_MAC_B0_POS)) - -/* 0x48 : HASH0_ADDR */ -#define EMAC_HASH0_ADDR_OFFSET (0x48) -#define EMAC_HASH0 EMAC_HASH0 -#define EMAC_HASH0_POS (0U) -#define EMAC_HASH0_LEN (32U) -#define EMAC_HASH0_MSK (((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS) -#define EMAC_HASH0_UMSK (~(((1U << EMAC_HASH0_LEN) - 1) << EMAC_HASH0_POS)) - -/* 0x4C : HASH1_ADDR */ -#define EMAC_HASH1_ADDR_OFFSET (0x4C) -#define EMAC_HASH1 EMAC_HASH1 -#define EMAC_HASH1_POS (0U) -#define EMAC_HASH1_LEN (32U) -#define EMAC_HASH1_MSK (((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS) -#define EMAC_HASH1_UMSK (~(((1U << EMAC_HASH1_LEN) - 1) << EMAC_HASH1_POS)) - -/* 0x50 : TXCTRL */ -#define EMAC_TXCTRL_OFFSET (0x50) -#define EMAC_TXPAUSETV EMAC_TXPAUSETV -#define EMAC_TXPAUSETV_POS (0U) -#define EMAC_TXPAUSETV_LEN (16U) -#define EMAC_TXPAUSETV_MSK (((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS) -#define EMAC_TXPAUSETV_UMSK (~(((1U << EMAC_TXPAUSETV_LEN) - 1) << EMAC_TXPAUSETV_POS)) -#define EMAC_TXPAUSERQ EMAC_TXPAUSERQ -#define EMAC_TXPAUSERQ_POS (16U) -#define EMAC_TXPAUSERQ_LEN (1U) -#define EMAC_TXPAUSERQ_MSK (((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS) -#define EMAC_TXPAUSERQ_UMSK (~(((1U << EMAC_TXPAUSERQ_LEN) - 1) << EMAC_TXPAUSERQ_POS)) - -struct emac_reg { - /* 0x0 : MODE */ - union { - struct { - uint32_t RXEN : 1; /* [ 0], r/w, 0x0 */ - uint32_t TXEN : 1; /* [ 1], r/w, 0x0 */ - uint32_t NOPRE : 1; /* [ 2], r/w, 0x0 */ - uint32_t BRO : 1; /* [ 3], r/w, 0x1 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t PRO : 1; /* [ 5], r/w, 0x0 */ - uint32_t IFG : 1; /* [ 6], r/w, 0x0 */ - uint32_t rsvd_9_7 : 3; /* [ 9: 7], rsvd, 0x0 */ - uint32_t FULLD : 1; /* [ 10], r/w, 0x0 */ - uint32_t rsvd_12_11 : 2; /* [12:11], rsvd, 0x0 */ - uint32_t CRCEN : 1; /* [ 13], r/w, 0x1 */ - uint32_t HUGEN : 1; /* [ 14], r/w, 0x0 */ - uint32_t PAD : 1; /* [ 15], r/w, 0x1 */ - uint32_t RECSMALL : 1; /* [ 16], r/w, 0x0 */ - uint32_t RMII_EN : 1; /* [ 17], r/w, 0x0 */ - uint32_t rsvd_23_18 : 6; /* [23:18], rsvd, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MODE; - - /* 0x4 : INT_SOURCE */ - union { - struct { - uint32_t TXB : 1; /* [ 0], r/w, 0x0 */ - uint32_t TXE : 1; /* [ 1], r/w, 0x0 */ - uint32_t RXB : 1; /* [ 2], r/w, 0x0 */ - uint32_t RXE : 1; /* [ 3], r/w, 0x0 */ - uint32_t BUSY : 1; /* [ 4], r/w, 0x0 */ - uint32_t TXC : 1; /* [ 5], r/w, 0x0 */ - uint32_t RXC : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } INT_SOURCE; - - /* 0x8 : INT_MASK */ - union { - struct { - uint32_t TXB_M : 1; /* [ 0], r/w, 0x1 */ - uint32_t TXE_M : 1; /* [ 1], r/w, 0x1 */ - uint32_t RXB_M : 1; /* [ 2], r/w, 0x1 */ - uint32_t RXE_M : 1; /* [ 3], r/w, 0x1 */ - uint32_t BUSY_M : 1; /* [ 4], r/w, 0x1 */ - uint32_t TXC_M : 1; /* [ 5], r/w, 0x1 */ - uint32_t RXC_M : 1; /* [ 6], r/w, 0x1 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } INT_MASK; - - /* 0xC : IPGT */ - union { - struct { - uint32_t IPGT : 7; /* [ 6: 0], r/w, 0x18 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } IPGT; - - /* 0x10 reserved */ - uint8_t RESERVED0x10[8]; - - /* 0x18 : PACKETLEN */ - union { - struct { - uint32_t MAXFL : 16; /* [15: 0], r/w, 0x600 */ - uint32_t MINFL : 16; /* [31:16], r/w, 0x40 */ - } BF; - uint32_t WORD; - } PACKETLEN; - - /* 0x1C : COLLCONFIG */ - union { - struct { - uint32_t COLLVALID : 6; /* [ 5: 0], r/w, 0x3f */ - uint32_t reserved_6_15 : 10; /* [15: 6], rsvd, 0x0 */ - uint32_t MAXRET : 4; /* [19:16], r/w, 0xf */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } COLLCONFIG; - - /* 0x20 : TX_BD_NUM */ - union { - struct { - uint32_t TXBDNUM : 8; /* [ 7: 0], r/w, 0x40 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t TXBDPTR : 7; /* [22:16], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t RXBDPTR : 7; /* [30:24], r, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TX_BD_NUM; - - /* 0x24 reserved */ - uint8_t RESERVED0x24[4]; - - /* 0x28 : MIIMODE */ - union { - struct { - uint32_t CLKDIV : 8; /* [ 7: 0], r/w, 0x64 */ - uint32_t MIINOPRE : 1; /* [ 8], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIIMODE; - - /* 0x2C : MIICOMMAND */ - union { - struct { - uint32_t SCANSTAT : 1; /* [ 0], r/w, 0x0 */ - uint32_t RSTAT : 1; /* [ 1], r/w, 0x0 */ - uint32_t WCTRLDATA : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIICOMMAND; - - /* 0x30 : MIIADDRESS */ - union { - struct { - uint32_t FIAD : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t RGAD : 5; /* [12: 8], r/w, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIIADDRESS; - - /* 0x34 : MIITX_DATA */ - union { - struct { - uint32_t CTRLDATA : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIITX_DATA; - - /* 0x38 : MIIRX_DATA */ - union { - struct { - uint32_t PRSD : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIIRX_DATA; - - /* 0x3C : MIISTATUS */ - union { - struct { - uint32_t MIIM_LINKFAIL : 1; /* [ 0], r, 0x0 */ - uint32_t MIIM_BUSY : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MIISTATUS; - - /* 0x40 : MAC_ADDR0 */ - union { - struct { - uint32_t MAC_B5 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t MAC_B4 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t MAC_B3 : 8; /* [23:16], r/w, 0x0 */ - uint32_t MAC_B2 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } MAC_ADDR0; - - /* 0x44 : MAC_ADDR1 */ - union { - struct { - uint32_t MAC_B1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t MAC_B0 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } MAC_ADDR1; - - /* 0x48 : HASH0_ADDR */ - union { - struct { - uint32_t HASH0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } HASH0_ADDR; - - /* 0x4C : HASH1_ADDR */ - union { - struct { - uint32_t HASH1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } HASH1_ADDR; - - /* 0x50 : TXCTRL */ - union { - struct { - uint32_t TXPAUSETV : 16; /* [15: 0], r/w, 0x0 */ - uint32_t TXPAUSERQ : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TXCTRL; -}; - -typedef volatile struct emac_reg emac_reg_t; - -#endif /* __EMAC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emi_misc_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emi_misc_reg.h deleted file mode 100644 index acb7637206..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/emi_misc_reg.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file emi_misc_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __EMI_MISC_REG_H__ -#define __EMI_MISC_REG_H__ - -#include "bl808.h" - -/* 0x00 : emi_bus_ctrl */ -#define EMI_MISC_EMI_BUS_CTRL_OFFSET (0x00) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON EMI_MISC_RG_EMI_PCLK_FORCE_ON -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_POS (0U) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_LEN (16U) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_MSK (((1U << EMI_MISC_RG_EMI_PCLK_FORCE_ON_LEN) - 1) << EMI_MISC_RG_EMI_PCLK_FORCE_ON_POS) -#define EMI_MISC_RG_EMI_PCLK_FORCE_ON_UMSK (~(((1U << EMI_MISC_RG_EMI_PCLK_FORCE_ON_LEN) - 1) << EMI_MISC_RG_EMI_PCLK_FORCE_ON_POS)) - -/* 0x04 : emi_bus_ctrl2 */ -#define EMI_MISC_EMI_BUS_CTRL2_OFFSET (0x04) -#define EMI_MISC_REG_SF_HARB_MODE EMI_MISC_REG_SF_HARB_MODE -#define EMI_MISC_REG_SF_HARB_MODE_POS (0U) -#define EMI_MISC_REG_SF_HARB_MODE_LEN (1U) -#define EMI_MISC_REG_SF_HARB_MODE_MSK (((1U << EMI_MISC_REG_SF_HARB_MODE_LEN) - 1) << EMI_MISC_REG_SF_HARB_MODE_POS) -#define EMI_MISC_REG_SF_HARB_MODE_UMSK (~(((1U << EMI_MISC_REG_SF_HARB_MODE_LEN) - 1) << EMI_MISC_REG_SF_HARB_MODE_POS)) - -/* 0x08 : emi_bus_thre */ -#define EMI_MISC_EMI_BUS_THRE_OFFSET (0x08) -#define EMI_MISC_REG_X_WTHRE_PB EMI_MISC_REG_X_WTHRE_PB -#define EMI_MISC_REG_X_WTHRE_PB_POS (0U) -#define EMI_MISC_REG_X_WTHRE_PB_LEN (2U) -#define EMI_MISC_REG_X_WTHRE_PB_MSK (((1U << EMI_MISC_REG_X_WTHRE_PB_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PB_POS) -#define EMI_MISC_REG_X_WTHRE_PB_UMSK (~(((1U << EMI_MISC_REG_X_WTHRE_PB_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PB_POS)) -#define EMI_MISC_REG_X_WTHRE_PA EMI_MISC_REG_X_WTHRE_PA -#define EMI_MISC_REG_X_WTHRE_PA_POS (2U) -#define EMI_MISC_REG_X_WTHRE_PA_LEN (2U) -#define EMI_MISC_REG_X_WTHRE_PA_MSK (((1U << EMI_MISC_REG_X_WTHRE_PA_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PA_POS) -#define EMI_MISC_REG_X_WTHRE_PA_UMSK (~(((1U << EMI_MISC_REG_X_WTHRE_PA_LEN) - 1) << EMI_MISC_REG_X_WTHRE_PA_POS)) - -/* 0xFC : emi_misc_dummy */ -#define EMI_MISC_DUMMY_OFFSET (0xFC) -#define EMI_MISC_DUMMY_REG EMI_MISC_DUMMY_REG -#define EMI_MISC_DUMMY_REG_POS (0U) -#define EMI_MISC_DUMMY_REG_LEN (32U) -#define EMI_MISC_DUMMY_REG_MSK (((1U << EMI_MISC_DUMMY_REG_LEN) - 1) << EMI_MISC_DUMMY_REG_POS) -#define EMI_MISC_DUMMY_REG_UMSK (~(((1U << EMI_MISC_DUMMY_REG_LEN) - 1) << EMI_MISC_DUMMY_REG_POS)) - -struct emi_misc_reg { - /* 0x00 : emi_bus_ctrl */ - union { - struct { - uint32_t rg_emi_pclk_force_on : 16; /* [15: 0], r/w, 0xffff */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } emi_bus_ctrl; - - /* 0x04 : emi_bus_ctrl2 */ - union { - struct { - uint32_t reg_sf_harb_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } emi_bus_ctrl2; - - /* 0x08 : emi_bus_thre */ - union { - struct { - uint32_t reg_x_wthre_pB : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reg_x_wthre_pA : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } emi_bus_thre; - - /* 0xc reserved */ - uint8_t RESERVED0xc[240]; - - /* 0xFC : emi_misc_dummy */ - union { - struct { - uint32_t dummy_reg : 32; /* [31: 0], r/w, 0xffff0000 */ - } BF; - uint32_t WORD; - } emi_misc_dummy; -}; - -typedef volatile struct emi_misc_reg emi_misc_reg_t; - -#endif /* __EMI_MISC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2c_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2c_reg.h deleted file mode 100644 index 0f498e244f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2c_reg.h +++ /dev/null @@ -1,550 +0,0 @@ -/** - ****************************************************************************** - * @file i2c_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __I2C_REG_H__ -#define __I2C_REG_H__ - -#include "bl808.h" - -/* 0x0 : i2c_config */ -#define I2C_CONFIG_OFFSET (0x0) -#define I2C_CR_I2C_M_EN I2C_CR_I2C_M_EN -#define I2C_CR_I2C_M_EN_POS (0U) -#define I2C_CR_I2C_M_EN_LEN (1U) -#define I2C_CR_I2C_M_EN_MSK (((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS) -#define I2C_CR_I2C_M_EN_UMSK (~(((1U << I2C_CR_I2C_M_EN_LEN) - 1) << I2C_CR_I2C_M_EN_POS)) -#define I2C_CR_I2C_PKT_DIR I2C_CR_I2C_PKT_DIR -#define I2C_CR_I2C_PKT_DIR_POS (1U) -#define I2C_CR_I2C_PKT_DIR_LEN (1U) -#define I2C_CR_I2C_PKT_DIR_MSK (((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS) -#define I2C_CR_I2C_PKT_DIR_UMSK (~(((1U << I2C_CR_I2C_PKT_DIR_LEN) - 1) << I2C_CR_I2C_PKT_DIR_POS)) -#define I2C_CR_I2C_DEG_EN I2C_CR_I2C_DEG_EN -#define I2C_CR_I2C_DEG_EN_POS (2U) -#define I2C_CR_I2C_DEG_EN_LEN (1U) -#define I2C_CR_I2C_DEG_EN_MSK (((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS) -#define I2C_CR_I2C_DEG_EN_UMSK (~(((1U << I2C_CR_I2C_DEG_EN_LEN) - 1) << I2C_CR_I2C_DEG_EN_POS)) -#define I2C_CR_I2C_SCL_SYNC_EN I2C_CR_I2C_SCL_SYNC_EN -#define I2C_CR_I2C_SCL_SYNC_EN_POS (3U) -#define I2C_CR_I2C_SCL_SYNC_EN_LEN (1U) -#define I2C_CR_I2C_SCL_SYNC_EN_MSK (((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS) -#define I2C_CR_I2C_SCL_SYNC_EN_UMSK (~(((1U << I2C_CR_I2C_SCL_SYNC_EN_LEN) - 1) << I2C_CR_I2C_SCL_SYNC_EN_POS)) -#define I2C_CR_I2C_SUB_ADDR_EN I2C_CR_I2C_SUB_ADDR_EN -#define I2C_CR_I2C_SUB_ADDR_EN_POS (4U) -#define I2C_CR_I2C_SUB_ADDR_EN_LEN (1U) -#define I2C_CR_I2C_SUB_ADDR_EN_MSK (((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS) -#define I2C_CR_I2C_SUB_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_EN_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_EN_POS)) -#define I2C_CR_I2C_SUB_ADDR_BC I2C_CR_I2C_SUB_ADDR_BC -#define I2C_CR_I2C_SUB_ADDR_BC_POS (5U) -#define I2C_CR_I2C_SUB_ADDR_BC_LEN (2U) -#define I2C_CR_I2C_SUB_ADDR_BC_MSK (((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS) -#define I2C_CR_I2C_SUB_ADDR_BC_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_BC_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_BC_POS)) -#define I2C_CR_I2C_10B_ADDR_EN I2C_CR_I2C_10B_ADDR_EN -#define I2C_CR_I2C_10B_ADDR_EN_POS (7U) -#define I2C_CR_I2C_10B_ADDR_EN_LEN (1U) -#define I2C_CR_I2C_10B_ADDR_EN_MSK (((1U << I2C_CR_I2C_10B_ADDR_EN_LEN) - 1) << I2C_CR_I2C_10B_ADDR_EN_POS) -#define I2C_CR_I2C_10B_ADDR_EN_UMSK (~(((1U << I2C_CR_I2C_10B_ADDR_EN_LEN) - 1) << I2C_CR_I2C_10B_ADDR_EN_POS)) -#define I2C_CR_I2C_SLV_ADDR I2C_CR_I2C_SLV_ADDR -#define I2C_CR_I2C_SLV_ADDR_POS (8U) -#define I2C_CR_I2C_SLV_ADDR_LEN (10U) -#define I2C_CR_I2C_SLV_ADDR_MSK (((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS) -#define I2C_CR_I2C_SLV_ADDR_UMSK (~(((1U << I2C_CR_I2C_SLV_ADDR_LEN) - 1) << I2C_CR_I2C_SLV_ADDR_POS)) -#define I2C_CR_I2C_PKT_LEN I2C_CR_I2C_PKT_LEN -#define I2C_CR_I2C_PKT_LEN_POS (20U) -#define I2C_CR_I2C_PKT_LEN_LEN (8U) -#define I2C_CR_I2C_PKT_LEN_MSK (((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS) -#define I2C_CR_I2C_PKT_LEN_UMSK (~(((1U << I2C_CR_I2C_PKT_LEN_LEN) - 1) << I2C_CR_I2C_PKT_LEN_POS)) -#define I2C_CR_I2C_DEG_CNT I2C_CR_I2C_DEG_CNT -#define I2C_CR_I2C_DEG_CNT_POS (28U) -#define I2C_CR_I2C_DEG_CNT_LEN (4U) -#define I2C_CR_I2C_DEG_CNT_MSK (((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS) -#define I2C_CR_I2C_DEG_CNT_UMSK (~(((1U << I2C_CR_I2C_DEG_CNT_LEN) - 1) << I2C_CR_I2C_DEG_CNT_POS)) - -/* 0x4 : i2c_int_sts */ -#define I2C_INT_STS_OFFSET (0x4) -#define I2C_END_INT I2C_END_INT -#define I2C_END_INT_POS (0U) -#define I2C_END_INT_LEN (1U) -#define I2C_END_INT_MSK (((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS) -#define I2C_END_INT_UMSK (~(((1U << I2C_END_INT_LEN) - 1) << I2C_END_INT_POS)) -#define I2C_TXF_INT I2C_TXF_INT -#define I2C_TXF_INT_POS (1U) -#define I2C_TXF_INT_LEN (1U) -#define I2C_TXF_INT_MSK (((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS) -#define I2C_TXF_INT_UMSK (~(((1U << I2C_TXF_INT_LEN) - 1) << I2C_TXF_INT_POS)) -#define I2C_RXF_INT I2C_RXF_INT -#define I2C_RXF_INT_POS (2U) -#define I2C_RXF_INT_LEN (1U) -#define I2C_RXF_INT_MSK (((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS) -#define I2C_RXF_INT_UMSK (~(((1U << I2C_RXF_INT_LEN) - 1) << I2C_RXF_INT_POS)) -#define I2C_NAK_INT I2C_NAK_INT -#define I2C_NAK_INT_POS (3U) -#define I2C_NAK_INT_LEN (1U) -#define I2C_NAK_INT_MSK (((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS) -#define I2C_NAK_INT_UMSK (~(((1U << I2C_NAK_INT_LEN) - 1) << I2C_NAK_INT_POS)) -#define I2C_ARB_INT I2C_ARB_INT -#define I2C_ARB_INT_POS (4U) -#define I2C_ARB_INT_LEN (1U) -#define I2C_ARB_INT_MSK (((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS) -#define I2C_ARB_INT_UMSK (~(((1U << I2C_ARB_INT_LEN) - 1) << I2C_ARB_INT_POS)) -#define I2C_FER_INT I2C_FER_INT -#define I2C_FER_INT_POS (5U) -#define I2C_FER_INT_LEN (1U) -#define I2C_FER_INT_MSK (((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS) -#define I2C_FER_INT_UMSK (~(((1U << I2C_FER_INT_LEN) - 1) << I2C_FER_INT_POS)) -#define I2C_CR_I2C_END_MASK I2C_CR_I2C_END_MASK -#define I2C_CR_I2C_END_MASK_POS (8U) -#define I2C_CR_I2C_END_MASK_LEN (1U) -#define I2C_CR_I2C_END_MASK_MSK (((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS) -#define I2C_CR_I2C_END_MASK_UMSK (~(((1U << I2C_CR_I2C_END_MASK_LEN) - 1) << I2C_CR_I2C_END_MASK_POS)) -#define I2C_CR_I2C_TXF_MASK I2C_CR_I2C_TXF_MASK -#define I2C_CR_I2C_TXF_MASK_POS (9U) -#define I2C_CR_I2C_TXF_MASK_LEN (1U) -#define I2C_CR_I2C_TXF_MASK_MSK (((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS) -#define I2C_CR_I2C_TXF_MASK_UMSK (~(((1U << I2C_CR_I2C_TXF_MASK_LEN) - 1) << I2C_CR_I2C_TXF_MASK_POS)) -#define I2C_CR_I2C_RXF_MASK I2C_CR_I2C_RXF_MASK -#define I2C_CR_I2C_RXF_MASK_POS (10U) -#define I2C_CR_I2C_RXF_MASK_LEN (1U) -#define I2C_CR_I2C_RXF_MASK_MSK (((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS) -#define I2C_CR_I2C_RXF_MASK_UMSK (~(((1U << I2C_CR_I2C_RXF_MASK_LEN) - 1) << I2C_CR_I2C_RXF_MASK_POS)) -#define I2C_CR_I2C_NAK_MASK I2C_CR_I2C_NAK_MASK -#define I2C_CR_I2C_NAK_MASK_POS (11U) -#define I2C_CR_I2C_NAK_MASK_LEN (1U) -#define I2C_CR_I2C_NAK_MASK_MSK (((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS) -#define I2C_CR_I2C_NAK_MASK_UMSK (~(((1U << I2C_CR_I2C_NAK_MASK_LEN) - 1) << I2C_CR_I2C_NAK_MASK_POS)) -#define I2C_CR_I2C_ARB_MASK I2C_CR_I2C_ARB_MASK -#define I2C_CR_I2C_ARB_MASK_POS (12U) -#define I2C_CR_I2C_ARB_MASK_LEN (1U) -#define I2C_CR_I2C_ARB_MASK_MSK (((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS) -#define I2C_CR_I2C_ARB_MASK_UMSK (~(((1U << I2C_CR_I2C_ARB_MASK_LEN) - 1) << I2C_CR_I2C_ARB_MASK_POS)) -#define I2C_CR_I2C_FER_MASK I2C_CR_I2C_FER_MASK -#define I2C_CR_I2C_FER_MASK_POS (13U) -#define I2C_CR_I2C_FER_MASK_LEN (1U) -#define I2C_CR_I2C_FER_MASK_MSK (((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS) -#define I2C_CR_I2C_FER_MASK_UMSK (~(((1U << I2C_CR_I2C_FER_MASK_LEN) - 1) << I2C_CR_I2C_FER_MASK_POS)) -#define I2C_CR_I2C_END_CLR I2C_CR_I2C_END_CLR -#define I2C_CR_I2C_END_CLR_POS (16U) -#define I2C_CR_I2C_END_CLR_LEN (1U) -#define I2C_CR_I2C_END_CLR_MSK (((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS) -#define I2C_CR_I2C_END_CLR_UMSK (~(((1U << I2C_CR_I2C_END_CLR_LEN) - 1) << I2C_CR_I2C_END_CLR_POS)) -#define I2C_CR_I2C_NAK_CLR I2C_CR_I2C_NAK_CLR -#define I2C_CR_I2C_NAK_CLR_POS (19U) -#define I2C_CR_I2C_NAK_CLR_LEN (1U) -#define I2C_CR_I2C_NAK_CLR_MSK (((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS) -#define I2C_CR_I2C_NAK_CLR_UMSK (~(((1U << I2C_CR_I2C_NAK_CLR_LEN) - 1) << I2C_CR_I2C_NAK_CLR_POS)) -#define I2C_CR_I2C_ARB_CLR I2C_CR_I2C_ARB_CLR -#define I2C_CR_I2C_ARB_CLR_POS (20U) -#define I2C_CR_I2C_ARB_CLR_LEN (1U) -#define I2C_CR_I2C_ARB_CLR_MSK (((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS) -#define I2C_CR_I2C_ARB_CLR_UMSK (~(((1U << I2C_CR_I2C_ARB_CLR_LEN) - 1) << I2C_CR_I2C_ARB_CLR_POS)) -#define I2C_CR_I2C_END_EN I2C_CR_I2C_END_EN -#define I2C_CR_I2C_END_EN_POS (24U) -#define I2C_CR_I2C_END_EN_LEN (1U) -#define I2C_CR_I2C_END_EN_MSK (((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS) -#define I2C_CR_I2C_END_EN_UMSK (~(((1U << I2C_CR_I2C_END_EN_LEN) - 1) << I2C_CR_I2C_END_EN_POS)) -#define I2C_CR_I2C_TXF_EN I2C_CR_I2C_TXF_EN -#define I2C_CR_I2C_TXF_EN_POS (25U) -#define I2C_CR_I2C_TXF_EN_LEN (1U) -#define I2C_CR_I2C_TXF_EN_MSK (((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS) -#define I2C_CR_I2C_TXF_EN_UMSK (~(((1U << I2C_CR_I2C_TXF_EN_LEN) - 1) << I2C_CR_I2C_TXF_EN_POS)) -#define I2C_CR_I2C_RXF_EN I2C_CR_I2C_RXF_EN -#define I2C_CR_I2C_RXF_EN_POS (26U) -#define I2C_CR_I2C_RXF_EN_LEN (1U) -#define I2C_CR_I2C_RXF_EN_MSK (((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS) -#define I2C_CR_I2C_RXF_EN_UMSK (~(((1U << I2C_CR_I2C_RXF_EN_LEN) - 1) << I2C_CR_I2C_RXF_EN_POS)) -#define I2C_CR_I2C_NAK_EN I2C_CR_I2C_NAK_EN -#define I2C_CR_I2C_NAK_EN_POS (27U) -#define I2C_CR_I2C_NAK_EN_LEN (1U) -#define I2C_CR_I2C_NAK_EN_MSK (((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS) -#define I2C_CR_I2C_NAK_EN_UMSK (~(((1U << I2C_CR_I2C_NAK_EN_LEN) - 1) << I2C_CR_I2C_NAK_EN_POS)) -#define I2C_CR_I2C_ARB_EN I2C_CR_I2C_ARB_EN -#define I2C_CR_I2C_ARB_EN_POS (28U) -#define I2C_CR_I2C_ARB_EN_LEN (1U) -#define I2C_CR_I2C_ARB_EN_MSK (((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS) -#define I2C_CR_I2C_ARB_EN_UMSK (~(((1U << I2C_CR_I2C_ARB_EN_LEN) - 1) << I2C_CR_I2C_ARB_EN_POS)) -#define I2C_CR_I2C_FER_EN I2C_CR_I2C_FER_EN -#define I2C_CR_I2C_FER_EN_POS (29U) -#define I2C_CR_I2C_FER_EN_LEN (1U) -#define I2C_CR_I2C_FER_EN_MSK (((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS) -#define I2C_CR_I2C_FER_EN_UMSK (~(((1U << I2C_CR_I2C_FER_EN_LEN) - 1) << I2C_CR_I2C_FER_EN_POS)) - -/* 0x8 : i2c_sub_addr */ -#define I2C_SUB_ADDR_OFFSET (0x8) -#define I2C_CR_I2C_SUB_ADDR_B0 I2C_CR_I2C_SUB_ADDR_B0 -#define I2C_CR_I2C_SUB_ADDR_B0_POS (0U) -#define I2C_CR_I2C_SUB_ADDR_B0_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B0_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS) -#define I2C_CR_I2C_SUB_ADDR_B0_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B0_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B0_POS)) -#define I2C_CR_I2C_SUB_ADDR_B1 I2C_CR_I2C_SUB_ADDR_B1 -#define I2C_CR_I2C_SUB_ADDR_B1_POS (8U) -#define I2C_CR_I2C_SUB_ADDR_B1_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B1_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS) -#define I2C_CR_I2C_SUB_ADDR_B1_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B1_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B1_POS)) -#define I2C_CR_I2C_SUB_ADDR_B2 I2C_CR_I2C_SUB_ADDR_B2 -#define I2C_CR_I2C_SUB_ADDR_B2_POS (16U) -#define I2C_CR_I2C_SUB_ADDR_B2_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B2_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS) -#define I2C_CR_I2C_SUB_ADDR_B2_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B2_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B2_POS)) -#define I2C_CR_I2C_SUB_ADDR_B3 I2C_CR_I2C_SUB_ADDR_B3 -#define I2C_CR_I2C_SUB_ADDR_B3_POS (24U) -#define I2C_CR_I2C_SUB_ADDR_B3_LEN (8U) -#define I2C_CR_I2C_SUB_ADDR_B3_MSK (((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS) -#define I2C_CR_I2C_SUB_ADDR_B3_UMSK (~(((1U << I2C_CR_I2C_SUB_ADDR_B3_LEN) - 1) << I2C_CR_I2C_SUB_ADDR_B3_POS)) - -/* 0xC : i2c_bus_busy */ -#define I2C_BUS_BUSY_OFFSET (0xC) -#define I2C_STS_I2C_BUS_BUSY I2C_STS_I2C_BUS_BUSY -#define I2C_STS_I2C_BUS_BUSY_POS (0U) -#define I2C_STS_I2C_BUS_BUSY_LEN (1U) -#define I2C_STS_I2C_BUS_BUSY_MSK (((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS) -#define I2C_STS_I2C_BUS_BUSY_UMSK (~(((1U << I2C_STS_I2C_BUS_BUSY_LEN) - 1) << I2C_STS_I2C_BUS_BUSY_POS)) -#define I2C_CR_I2C_BUS_BUSY_CLR I2C_CR_I2C_BUS_BUSY_CLR -#define I2C_CR_I2C_BUS_BUSY_CLR_POS (1U) -#define I2C_CR_I2C_BUS_BUSY_CLR_LEN (1U) -#define I2C_CR_I2C_BUS_BUSY_CLR_MSK (((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS) -#define I2C_CR_I2C_BUS_BUSY_CLR_UMSK (~(((1U << I2C_CR_I2C_BUS_BUSY_CLR_LEN) - 1) << I2C_CR_I2C_BUS_BUSY_CLR_POS)) - -/* 0x10 : i2c_prd_start */ -#define I2C_PRD_START_OFFSET (0x10) -#define I2C_CR_I2C_PRD_S_PH_0 I2C_CR_I2C_PRD_S_PH_0 -#define I2C_CR_I2C_PRD_S_PH_0_POS (0U) -#define I2C_CR_I2C_PRD_S_PH_0_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_0_MSK (((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS) -#define I2C_CR_I2C_PRD_S_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_0_POS)) -#define I2C_CR_I2C_PRD_S_PH_1 I2C_CR_I2C_PRD_S_PH_1 -#define I2C_CR_I2C_PRD_S_PH_1_POS (8U) -#define I2C_CR_I2C_PRD_S_PH_1_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_1_MSK (((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS) -#define I2C_CR_I2C_PRD_S_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_1_POS)) -#define I2C_CR_I2C_PRD_S_PH_2 I2C_CR_I2C_PRD_S_PH_2 -#define I2C_CR_I2C_PRD_S_PH_2_POS (16U) -#define I2C_CR_I2C_PRD_S_PH_2_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_2_MSK (((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS) -#define I2C_CR_I2C_PRD_S_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_2_POS)) -#define I2C_CR_I2C_PRD_S_PH_3 I2C_CR_I2C_PRD_S_PH_3 -#define I2C_CR_I2C_PRD_S_PH_3_POS (24U) -#define I2C_CR_I2C_PRD_S_PH_3_LEN (8U) -#define I2C_CR_I2C_PRD_S_PH_3_MSK (((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS) -#define I2C_CR_I2C_PRD_S_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_S_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_S_PH_3_POS)) - -/* 0x14 : i2c_prd_stop */ -#define I2C_PRD_STOP_OFFSET (0x14) -#define I2C_CR_I2C_PRD_P_PH_0 I2C_CR_I2C_PRD_P_PH_0 -#define I2C_CR_I2C_PRD_P_PH_0_POS (0U) -#define I2C_CR_I2C_PRD_P_PH_0_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_0_MSK (((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS) -#define I2C_CR_I2C_PRD_P_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_0_POS)) -#define I2C_CR_I2C_PRD_P_PH_1 I2C_CR_I2C_PRD_P_PH_1 -#define I2C_CR_I2C_PRD_P_PH_1_POS (8U) -#define I2C_CR_I2C_PRD_P_PH_1_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_1_MSK (((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS) -#define I2C_CR_I2C_PRD_P_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_1_POS)) -#define I2C_CR_I2C_PRD_P_PH_2 I2C_CR_I2C_PRD_P_PH_2 -#define I2C_CR_I2C_PRD_P_PH_2_POS (16U) -#define I2C_CR_I2C_PRD_P_PH_2_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_2_MSK (((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS) -#define I2C_CR_I2C_PRD_P_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_2_POS)) -#define I2C_CR_I2C_PRD_P_PH_3 I2C_CR_I2C_PRD_P_PH_3 -#define I2C_CR_I2C_PRD_P_PH_3_POS (24U) -#define I2C_CR_I2C_PRD_P_PH_3_LEN (8U) -#define I2C_CR_I2C_PRD_P_PH_3_MSK (((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS) -#define I2C_CR_I2C_PRD_P_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_P_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_P_PH_3_POS)) - -/* 0x18 : i2c_prd_data */ -#define I2C_PRD_DATA_OFFSET (0x18) -#define I2C_CR_I2C_PRD_D_PH_0 I2C_CR_I2C_PRD_D_PH_0 -#define I2C_CR_I2C_PRD_D_PH_0_POS (0U) -#define I2C_CR_I2C_PRD_D_PH_0_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_0_MSK (((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS) -#define I2C_CR_I2C_PRD_D_PH_0_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_0_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_0_POS)) -#define I2C_CR_I2C_PRD_D_PH_1 I2C_CR_I2C_PRD_D_PH_1 -#define I2C_CR_I2C_PRD_D_PH_1_POS (8U) -#define I2C_CR_I2C_PRD_D_PH_1_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_1_MSK (((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS) -#define I2C_CR_I2C_PRD_D_PH_1_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_1_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_1_POS)) -#define I2C_CR_I2C_PRD_D_PH_2 I2C_CR_I2C_PRD_D_PH_2 -#define I2C_CR_I2C_PRD_D_PH_2_POS (16U) -#define I2C_CR_I2C_PRD_D_PH_2_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_2_MSK (((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS) -#define I2C_CR_I2C_PRD_D_PH_2_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_2_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_2_POS)) -#define I2C_CR_I2C_PRD_D_PH_3 I2C_CR_I2C_PRD_D_PH_3 -#define I2C_CR_I2C_PRD_D_PH_3_POS (24U) -#define I2C_CR_I2C_PRD_D_PH_3_LEN (8U) -#define I2C_CR_I2C_PRD_D_PH_3_MSK (((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS) -#define I2C_CR_I2C_PRD_D_PH_3_UMSK (~(((1U << I2C_CR_I2C_PRD_D_PH_3_LEN) - 1) << I2C_CR_I2C_PRD_D_PH_3_POS)) - -/* 0x80 : i2c_fifo_config_0 */ -#define I2C_FIFO_CONFIG_0_OFFSET (0x80) -#define I2C_DMA_TX_EN I2C_DMA_TX_EN -#define I2C_DMA_TX_EN_POS (0U) -#define I2C_DMA_TX_EN_LEN (1U) -#define I2C_DMA_TX_EN_MSK (((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS) -#define I2C_DMA_TX_EN_UMSK (~(((1U << I2C_DMA_TX_EN_LEN) - 1) << I2C_DMA_TX_EN_POS)) -#define I2C_DMA_RX_EN I2C_DMA_RX_EN -#define I2C_DMA_RX_EN_POS (1U) -#define I2C_DMA_RX_EN_LEN (1U) -#define I2C_DMA_RX_EN_MSK (((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS) -#define I2C_DMA_RX_EN_UMSK (~(((1U << I2C_DMA_RX_EN_LEN) - 1) << I2C_DMA_RX_EN_POS)) -#define I2C_TX_FIFO_CLR I2C_TX_FIFO_CLR -#define I2C_TX_FIFO_CLR_POS (2U) -#define I2C_TX_FIFO_CLR_LEN (1U) -#define I2C_TX_FIFO_CLR_MSK (((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS) -#define I2C_TX_FIFO_CLR_UMSK (~(((1U << I2C_TX_FIFO_CLR_LEN) - 1) << I2C_TX_FIFO_CLR_POS)) -#define I2C_RX_FIFO_CLR I2C_RX_FIFO_CLR -#define I2C_RX_FIFO_CLR_POS (3U) -#define I2C_RX_FIFO_CLR_LEN (1U) -#define I2C_RX_FIFO_CLR_MSK (((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS) -#define I2C_RX_FIFO_CLR_UMSK (~(((1U << I2C_RX_FIFO_CLR_LEN) - 1) << I2C_RX_FIFO_CLR_POS)) -#define I2C_TX_FIFO_OVERFLOW I2C_TX_FIFO_OVERFLOW -#define I2C_TX_FIFO_OVERFLOW_POS (4U) -#define I2C_TX_FIFO_OVERFLOW_LEN (1U) -#define I2C_TX_FIFO_OVERFLOW_MSK (((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS) -#define I2C_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_TX_FIFO_OVERFLOW_LEN) - 1) << I2C_TX_FIFO_OVERFLOW_POS)) -#define I2C_TX_FIFO_UNDERFLOW I2C_TX_FIFO_UNDERFLOW -#define I2C_TX_FIFO_UNDERFLOW_POS (5U) -#define I2C_TX_FIFO_UNDERFLOW_LEN (1U) -#define I2C_TX_FIFO_UNDERFLOW_MSK (((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS) -#define I2C_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_TX_FIFO_UNDERFLOW_LEN) - 1) << I2C_TX_FIFO_UNDERFLOW_POS)) -#define I2C_RX_FIFO_OVERFLOW I2C_RX_FIFO_OVERFLOW -#define I2C_RX_FIFO_OVERFLOW_POS (6U) -#define I2C_RX_FIFO_OVERFLOW_LEN (1U) -#define I2C_RX_FIFO_OVERFLOW_MSK (((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS) -#define I2C_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2C_RX_FIFO_OVERFLOW_LEN) - 1) << I2C_RX_FIFO_OVERFLOW_POS)) -#define I2C_RX_FIFO_UNDERFLOW I2C_RX_FIFO_UNDERFLOW -#define I2C_RX_FIFO_UNDERFLOW_POS (7U) -#define I2C_RX_FIFO_UNDERFLOW_LEN (1U) -#define I2C_RX_FIFO_UNDERFLOW_MSK (((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS) -#define I2C_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2C_RX_FIFO_UNDERFLOW_LEN) - 1) << I2C_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : i2c_fifo_config_1 */ -#define I2C_FIFO_CONFIG_1_OFFSET (0x84) -#define I2C_TX_FIFO_CNT I2C_TX_FIFO_CNT -#define I2C_TX_FIFO_CNT_POS (0U) -#define I2C_TX_FIFO_CNT_LEN (2U) -#define I2C_TX_FIFO_CNT_MSK (((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS) -#define I2C_TX_FIFO_CNT_UMSK (~(((1U << I2C_TX_FIFO_CNT_LEN) - 1) << I2C_TX_FIFO_CNT_POS)) -#define I2C_RX_FIFO_CNT I2C_RX_FIFO_CNT -#define I2C_RX_FIFO_CNT_POS (8U) -#define I2C_RX_FIFO_CNT_LEN (2U) -#define I2C_RX_FIFO_CNT_MSK (((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS) -#define I2C_RX_FIFO_CNT_UMSK (~(((1U << I2C_RX_FIFO_CNT_LEN) - 1) << I2C_RX_FIFO_CNT_POS)) -#define I2C_TX_FIFO_TH I2C_TX_FIFO_TH -#define I2C_TX_FIFO_TH_POS (16U) -#define I2C_TX_FIFO_TH_LEN (1U) -#define I2C_TX_FIFO_TH_MSK (((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS) -#define I2C_TX_FIFO_TH_UMSK (~(((1U << I2C_TX_FIFO_TH_LEN) - 1) << I2C_TX_FIFO_TH_POS)) -#define I2C_RX_FIFO_TH I2C_RX_FIFO_TH -#define I2C_RX_FIFO_TH_POS (24U) -#define I2C_RX_FIFO_TH_LEN (1U) -#define I2C_RX_FIFO_TH_MSK (((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS) -#define I2C_RX_FIFO_TH_UMSK (~(((1U << I2C_RX_FIFO_TH_LEN) - 1) << I2C_RX_FIFO_TH_POS)) - -/* 0x88 : i2c_fifo_wdata */ -#define I2C_FIFO_WDATA_OFFSET (0x88) -#define I2C_FIFO_WDATA I2C_FIFO_WDATA -#define I2C_FIFO_WDATA_POS (0U) -#define I2C_FIFO_WDATA_LEN (32U) -#define I2C_FIFO_WDATA_MSK (((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS) -#define I2C_FIFO_WDATA_UMSK (~(((1U << I2C_FIFO_WDATA_LEN) - 1) << I2C_FIFO_WDATA_POS)) - -/* 0x8C : i2c_fifo_rdata */ -#define I2C_FIFO_RDATA_OFFSET (0x8C) -#define I2C_FIFO_RDATA I2C_FIFO_RDATA -#define I2C_FIFO_RDATA_POS (0U) -#define I2C_FIFO_RDATA_LEN (32U) -#define I2C_FIFO_RDATA_MSK (((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS) -#define I2C_FIFO_RDATA_UMSK (~(((1U << I2C_FIFO_RDATA_LEN) - 1) << I2C_FIFO_RDATA_POS)) - -struct i2c_reg { - /* 0x0 : i2c_config */ - union { - struct { - uint32_t cr_i2c_m_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_i2c_pkt_dir : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_i2c_deg_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_i2c_scl_sync_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_i2c_sub_addr_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_bc : 2; /* [ 6: 5], r/w, 0x0 */ - uint32_t cr_i2c_10b_addr_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_i2c_slv_addr : 10; /* [17: 8], r/w, 0x0 */ - uint32_t reserved_18_19 : 2; /* [19:18], rsvd, 0x0 */ - uint32_t cr_i2c_pkt_len : 8; /* [27:20], r/w, 0x0 */ - uint32_t cr_i2c_deg_cnt : 4; /* [31:28], r/w, 0x0 */ - } BF; - uint32_t WORD; - } i2c_config; - - /* 0x4 : i2c_int_sts */ - union { - struct { - uint32_t i2c_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t i2c_txf_int : 1; /* [ 1], r, 0x1 */ - uint32_t i2c_rxf_int : 1; /* [ 2], r, 0x0 */ - uint32_t i2c_nak_int : 1; /* [ 3], r, 0x0 */ - uint32_t i2c_arb_int : 1; /* [ 4], r, 0x0 */ - uint32_t i2c_fer_int : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t cr_i2c_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_i2c_txf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_i2c_rxf_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_i2c_nak_mask : 1; /* [ 11], r/w, 0x1 */ - uint32_t cr_i2c_arb_mask : 1; /* [ 12], r/w, 0x1 */ - uint32_t cr_i2c_fer_mask : 1; /* [ 13], r/w, 0x1 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_i2c_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t cr_i2c_nak_clr : 1; /* [ 19], w1c, 0x0 */ - uint32_t cr_i2c_arb_clr : 1; /* [ 20], w1c, 0x0 */ - uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t cr_i2c_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_i2c_txf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_i2c_rxf_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t cr_i2c_nak_en : 1; /* [ 27], r/w, 0x1 */ - uint32_t cr_i2c_arb_en : 1; /* [ 28], r/w, 0x1 */ - uint32_t cr_i2c_fer_en : 1; /* [ 29], r/w, 0x1 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_int_sts; - - /* 0x8 : i2c_sub_addr */ - union { - struct { - uint32_t cr_i2c_sub_addr_b0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_b1 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_b2 : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_i2c_sub_addr_b3 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } i2c_sub_addr; - - /* 0xC : i2c_bus_busy */ - union { - struct { - uint32_t sts_i2c_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t cr_i2c_bus_busy_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_bus_busy; - - /* 0x10 : i2c_prd_start */ - union { - struct { - uint32_t cr_i2c_prd_s_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_i2c_prd_s_ph_1 : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_i2c_prd_s_ph_2 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_i2c_prd_s_ph_3 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } i2c_prd_start; - - /* 0x14 : i2c_prd_stop */ - union { - struct { - uint32_t cr_i2c_prd_p_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_i2c_prd_p_ph_1 : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_i2c_prd_p_ph_2 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_i2c_prd_p_ph_3 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } i2c_prd_stop; - - /* 0x18 : i2c_prd_data */ - union { - struct { - uint32_t cr_i2c_prd_d_ph_0 : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_i2c_prd_d_ph_1 : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_i2c_prd_d_ph_2 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_i2c_prd_d_ph_3 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } i2c_prd_data; - - /* 0x1c reserved */ - uint8_t RESERVED0x1c[100]; - - /* 0x80 : i2c_fifo_config_0 */ - union { - struct { - uint32_t i2c_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t i2c_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_fifo_config_0; - - /* 0x84 : i2c_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 2; /* [ 1: 0], r, 0x2 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 2; /* [ 9: 8], r, 0x0 */ - uint32_t reserved_10_15 : 6; /* [15:10], rsvd, 0x0 */ - uint32_t tx_fifo_th : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t rx_fifo_th : 1; /* [ 24], r/w, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2c_fifo_config_1; - - /* 0x88 : i2c_fifo_wdata */ - union { - struct { - uint32_t i2c_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } i2c_fifo_wdata; - - /* 0x8C : i2c_fifo_rdata */ - union { - struct { - uint32_t i2c_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } i2c_fifo_rdata; -}; - -typedef volatile struct i2c_reg i2c_reg_t; - -#endif /* __I2C_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2s_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2s_reg.h deleted file mode 100644 index b4250520d6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/i2s_reg.h +++ /dev/null @@ -1,441 +0,0 @@ -/** - ****************************************************************************** - * @file i2s_reg.h - * @version V1.0 - * @date 2021-06-22 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __I2S_REG_H__ -#define __I2S_REG_H__ - -#include "bl808.h" - -/* 0x0 : i2s_config */ -#define I2S_CONFIG_OFFSET (0x0) -#define I2S_CR_I2S_M_EN I2S_CR_I2S_M_EN -#define I2S_CR_I2S_M_EN_POS (0U) -#define I2S_CR_I2S_M_EN_LEN (1U) -#define I2S_CR_I2S_M_EN_MSK (((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS) -#define I2S_CR_I2S_M_EN_UMSK (~(((1U << I2S_CR_I2S_M_EN_LEN) - 1) << I2S_CR_I2S_M_EN_POS)) -#define I2S_CR_I2S_S_EN I2S_CR_I2S_S_EN -#define I2S_CR_I2S_S_EN_POS (1U) -#define I2S_CR_I2S_S_EN_LEN (1U) -#define I2S_CR_I2S_S_EN_MSK (((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS) -#define I2S_CR_I2S_S_EN_UMSK (~(((1U << I2S_CR_I2S_S_EN_LEN) - 1) << I2S_CR_I2S_S_EN_POS)) -#define I2S_CR_I2S_TXD_EN I2S_CR_I2S_TXD_EN -#define I2S_CR_I2S_TXD_EN_POS (2U) -#define I2S_CR_I2S_TXD_EN_LEN (1U) -#define I2S_CR_I2S_TXD_EN_MSK (((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS) -#define I2S_CR_I2S_TXD_EN_UMSK (~(((1U << I2S_CR_I2S_TXD_EN_LEN) - 1) << I2S_CR_I2S_TXD_EN_POS)) -#define I2S_CR_I2S_RXD_EN I2S_CR_I2S_RXD_EN -#define I2S_CR_I2S_RXD_EN_POS (3U) -#define I2S_CR_I2S_RXD_EN_LEN (1U) -#define I2S_CR_I2S_RXD_EN_MSK (((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS) -#define I2S_CR_I2S_RXD_EN_UMSK (~(((1U << I2S_CR_I2S_RXD_EN_LEN) - 1) << I2S_CR_I2S_RXD_EN_POS)) -#define I2S_CR_MONO_MODE I2S_CR_MONO_MODE -#define I2S_CR_MONO_MODE_POS (4U) -#define I2S_CR_MONO_MODE_LEN (1U) -#define I2S_CR_MONO_MODE_MSK (((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS) -#define I2S_CR_MONO_MODE_UMSK (~(((1U << I2S_CR_MONO_MODE_LEN) - 1) << I2S_CR_MONO_MODE_POS)) -#define I2S_CR_MUTE_MODE I2S_CR_MUTE_MODE -#define I2S_CR_MUTE_MODE_POS (5U) -#define I2S_CR_MUTE_MODE_LEN (1U) -#define I2S_CR_MUTE_MODE_MSK (((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS) -#define I2S_CR_MUTE_MODE_UMSK (~(((1U << I2S_CR_MUTE_MODE_LEN) - 1) << I2S_CR_MUTE_MODE_POS)) -#define I2S_CR_FS_1T_MODE I2S_CR_FS_1T_MODE -#define I2S_CR_FS_1T_MODE_POS (6U) -#define I2S_CR_FS_1T_MODE_LEN (1U) -#define I2S_CR_FS_1T_MODE_MSK (((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS) -#define I2S_CR_FS_1T_MODE_UMSK (~(((1U << I2S_CR_FS_1T_MODE_LEN) - 1) << I2S_CR_FS_1T_MODE_POS)) -#define I2S_CR_FS_CH_CNT I2S_CR_FS_CH_CNT -#define I2S_CR_FS_CH_CNT_POS (7U) -#define I2S_CR_FS_CH_CNT_LEN (2U) -#define I2S_CR_FS_CH_CNT_MSK (((1U << I2S_CR_FS_CH_CNT_LEN) - 1) << I2S_CR_FS_CH_CNT_POS) -#define I2S_CR_FS_CH_CNT_UMSK (~(((1U << I2S_CR_FS_CH_CNT_LEN) - 1) << I2S_CR_FS_CH_CNT_POS)) -#define I2S_CR_FRAME_SIZE I2S_CR_FRAME_SIZE -#define I2S_CR_FRAME_SIZE_POS (12U) -#define I2S_CR_FRAME_SIZE_LEN (2U) -#define I2S_CR_FRAME_SIZE_MSK (((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS) -#define I2S_CR_FRAME_SIZE_UMSK (~(((1U << I2S_CR_FRAME_SIZE_LEN) - 1) << I2S_CR_FRAME_SIZE_POS)) -#define I2S_CR_DATA_SIZE I2S_CR_DATA_SIZE -#define I2S_CR_DATA_SIZE_POS (14U) -#define I2S_CR_DATA_SIZE_LEN (2U) -#define I2S_CR_DATA_SIZE_MSK (((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS) -#define I2S_CR_DATA_SIZE_UMSK (~(((1U << I2S_CR_DATA_SIZE_LEN) - 1) << I2S_CR_DATA_SIZE_POS)) -#define I2S_CR_I2S_MODE I2S_CR_I2S_MODE -#define I2S_CR_I2S_MODE_POS (16U) -#define I2S_CR_I2S_MODE_LEN (2U) -#define I2S_CR_I2S_MODE_MSK (((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS) -#define I2S_CR_I2S_MODE_UMSK (~(((1U << I2S_CR_I2S_MODE_LEN) - 1) << I2S_CR_I2S_MODE_POS)) -#define I2S_CR_ENDIAN I2S_CR_ENDIAN -#define I2S_CR_ENDIAN_POS (18U) -#define I2S_CR_ENDIAN_LEN (1U) -#define I2S_CR_ENDIAN_MSK (((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS) -#define I2S_CR_ENDIAN_UMSK (~(((1U << I2S_CR_ENDIAN_LEN) - 1) << I2S_CR_ENDIAN_POS)) -#define I2S_CR_MONO_RX_CH I2S_CR_MONO_RX_CH -#define I2S_CR_MONO_RX_CH_POS (19U) -#define I2S_CR_MONO_RX_CH_LEN (1U) -#define I2S_CR_MONO_RX_CH_MSK (((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS) -#define I2S_CR_MONO_RX_CH_UMSK (~(((1U << I2S_CR_MONO_RX_CH_LEN) - 1) << I2S_CR_MONO_RX_CH_POS)) -#define I2S_CR_OFS_CNT I2S_CR_OFS_CNT -#define I2S_CR_OFS_CNT_POS (20U) -#define I2S_CR_OFS_CNT_LEN (5U) -#define I2S_CR_OFS_CNT_MSK (((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS) -#define I2S_CR_OFS_CNT_UMSK (~(((1U << I2S_CR_OFS_CNT_LEN) - 1) << I2S_CR_OFS_CNT_POS)) -#define I2S_CR_OFS_EN I2S_CR_OFS_EN -#define I2S_CR_OFS_EN_POS (25U) -#define I2S_CR_OFS_EN_LEN (1U) -#define I2S_CR_OFS_EN_MSK (((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS) -#define I2S_CR_OFS_EN_UMSK (~(((1U << I2S_CR_OFS_EN_LEN) - 1) << I2S_CR_OFS_EN_POS)) - -/* 0x4 : i2s_int_sts */ -#define I2S_INT_STS_OFFSET (0x4) -#define I2S_TXF_INT I2S_TXF_INT -#define I2S_TXF_INT_POS (0U) -#define I2S_TXF_INT_LEN (1U) -#define I2S_TXF_INT_MSK (((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS) -#define I2S_TXF_INT_UMSK (~(((1U << I2S_TXF_INT_LEN) - 1) << I2S_TXF_INT_POS)) -#define I2S_RXF_INT I2S_RXF_INT -#define I2S_RXF_INT_POS (1U) -#define I2S_RXF_INT_LEN (1U) -#define I2S_RXF_INT_MSK (((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS) -#define I2S_RXF_INT_UMSK (~(((1U << I2S_RXF_INT_LEN) - 1) << I2S_RXF_INT_POS)) -#define I2S_FER_INT I2S_FER_INT -#define I2S_FER_INT_POS (2U) -#define I2S_FER_INT_LEN (1U) -#define I2S_FER_INT_MSK (((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS) -#define I2S_FER_INT_UMSK (~(((1U << I2S_FER_INT_LEN) - 1) << I2S_FER_INT_POS)) -#define I2S_CR_I2S_TXF_MASK I2S_CR_I2S_TXF_MASK -#define I2S_CR_I2S_TXF_MASK_POS (8U) -#define I2S_CR_I2S_TXF_MASK_LEN (1U) -#define I2S_CR_I2S_TXF_MASK_MSK (((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS) -#define I2S_CR_I2S_TXF_MASK_UMSK (~(((1U << I2S_CR_I2S_TXF_MASK_LEN) - 1) << I2S_CR_I2S_TXF_MASK_POS)) -#define I2S_CR_I2S_RXF_MASK I2S_CR_I2S_RXF_MASK -#define I2S_CR_I2S_RXF_MASK_POS (9U) -#define I2S_CR_I2S_RXF_MASK_LEN (1U) -#define I2S_CR_I2S_RXF_MASK_MSK (((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS) -#define I2S_CR_I2S_RXF_MASK_UMSK (~(((1U << I2S_CR_I2S_RXF_MASK_LEN) - 1) << I2S_CR_I2S_RXF_MASK_POS)) -#define I2S_CR_I2S_FER_MASK I2S_CR_I2S_FER_MASK -#define I2S_CR_I2S_FER_MASK_POS (10U) -#define I2S_CR_I2S_FER_MASK_LEN (1U) -#define I2S_CR_I2S_FER_MASK_MSK (((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS) -#define I2S_CR_I2S_FER_MASK_UMSK (~(((1U << I2S_CR_I2S_FER_MASK_LEN) - 1) << I2S_CR_I2S_FER_MASK_POS)) -#define I2S_CR_I2S_TXF_EN I2S_CR_I2S_TXF_EN -#define I2S_CR_I2S_TXF_EN_POS (24U) -#define I2S_CR_I2S_TXF_EN_LEN (1U) -#define I2S_CR_I2S_TXF_EN_MSK (((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS) -#define I2S_CR_I2S_TXF_EN_UMSK (~(((1U << I2S_CR_I2S_TXF_EN_LEN) - 1) << I2S_CR_I2S_TXF_EN_POS)) -#define I2S_CR_I2S_RXF_EN I2S_CR_I2S_RXF_EN -#define I2S_CR_I2S_RXF_EN_POS (25U) -#define I2S_CR_I2S_RXF_EN_LEN (1U) -#define I2S_CR_I2S_RXF_EN_MSK (((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS) -#define I2S_CR_I2S_RXF_EN_UMSK (~(((1U << I2S_CR_I2S_RXF_EN_LEN) - 1) << I2S_CR_I2S_RXF_EN_POS)) -#define I2S_CR_I2S_FER_EN I2S_CR_I2S_FER_EN -#define I2S_CR_I2S_FER_EN_POS (26U) -#define I2S_CR_I2S_FER_EN_LEN (1U) -#define I2S_CR_I2S_FER_EN_MSK (((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS) -#define I2S_CR_I2S_FER_EN_UMSK (~(((1U << I2S_CR_I2S_FER_EN_LEN) - 1) << I2S_CR_I2S_FER_EN_POS)) - -/* 0x10 : i2s_bclk_config */ -#define I2S_BCLK_CONFIG_OFFSET (0x10) -#define I2S_CR_BCLK_DIV_L I2S_CR_BCLK_DIV_L -#define I2S_CR_BCLK_DIV_L_POS (0U) -#define I2S_CR_BCLK_DIV_L_LEN (12U) -#define I2S_CR_BCLK_DIV_L_MSK (((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS) -#define I2S_CR_BCLK_DIV_L_UMSK (~(((1U << I2S_CR_BCLK_DIV_L_LEN) - 1) << I2S_CR_BCLK_DIV_L_POS)) -#define I2S_CR_BCLK_DIV_H I2S_CR_BCLK_DIV_H -#define I2S_CR_BCLK_DIV_H_POS (16U) -#define I2S_CR_BCLK_DIV_H_LEN (12U) -#define I2S_CR_BCLK_DIV_H_MSK (((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS) -#define I2S_CR_BCLK_DIV_H_UMSK (~(((1U << I2S_CR_BCLK_DIV_H_LEN) - 1) << I2S_CR_BCLK_DIV_H_POS)) - -/* 0x80 : i2s_fifo_config_0 */ -#define I2S_FIFO_CONFIG_0_OFFSET (0x80) -#define I2S_DMA_TX_EN I2S_DMA_TX_EN -#define I2S_DMA_TX_EN_POS (0U) -#define I2S_DMA_TX_EN_LEN (1U) -#define I2S_DMA_TX_EN_MSK (((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS) -#define I2S_DMA_TX_EN_UMSK (~(((1U << I2S_DMA_TX_EN_LEN) - 1) << I2S_DMA_TX_EN_POS)) -#define I2S_DMA_RX_EN I2S_DMA_RX_EN -#define I2S_DMA_RX_EN_POS (1U) -#define I2S_DMA_RX_EN_LEN (1U) -#define I2S_DMA_RX_EN_MSK (((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS) -#define I2S_DMA_RX_EN_UMSK (~(((1U << I2S_DMA_RX_EN_LEN) - 1) << I2S_DMA_RX_EN_POS)) -#define I2S_TX_FIFO_CLR I2S_TX_FIFO_CLR -#define I2S_TX_FIFO_CLR_POS (2U) -#define I2S_TX_FIFO_CLR_LEN (1U) -#define I2S_TX_FIFO_CLR_MSK (((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS) -#define I2S_TX_FIFO_CLR_UMSK (~(((1U << I2S_TX_FIFO_CLR_LEN) - 1) << I2S_TX_FIFO_CLR_POS)) -#define I2S_RX_FIFO_CLR I2S_RX_FIFO_CLR -#define I2S_RX_FIFO_CLR_POS (3U) -#define I2S_RX_FIFO_CLR_LEN (1U) -#define I2S_RX_FIFO_CLR_MSK (((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS) -#define I2S_RX_FIFO_CLR_UMSK (~(((1U << I2S_RX_FIFO_CLR_LEN) - 1) << I2S_RX_FIFO_CLR_POS)) -#define I2S_TX_FIFO_OVERFLOW I2S_TX_FIFO_OVERFLOW -#define I2S_TX_FIFO_OVERFLOW_POS (4U) -#define I2S_TX_FIFO_OVERFLOW_LEN (1U) -#define I2S_TX_FIFO_OVERFLOW_MSK (((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS) -#define I2S_TX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_TX_FIFO_OVERFLOW_LEN) - 1) << I2S_TX_FIFO_OVERFLOW_POS)) -#define I2S_TX_FIFO_UNDERFLOW I2S_TX_FIFO_UNDERFLOW -#define I2S_TX_FIFO_UNDERFLOW_POS (5U) -#define I2S_TX_FIFO_UNDERFLOW_LEN (1U) -#define I2S_TX_FIFO_UNDERFLOW_MSK (((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS) -#define I2S_TX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_TX_FIFO_UNDERFLOW_LEN) - 1) << I2S_TX_FIFO_UNDERFLOW_POS)) -#define I2S_RX_FIFO_OVERFLOW I2S_RX_FIFO_OVERFLOW -#define I2S_RX_FIFO_OVERFLOW_POS (6U) -#define I2S_RX_FIFO_OVERFLOW_LEN (1U) -#define I2S_RX_FIFO_OVERFLOW_MSK (((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS) -#define I2S_RX_FIFO_OVERFLOW_UMSK (~(((1U << I2S_RX_FIFO_OVERFLOW_LEN) - 1) << I2S_RX_FIFO_OVERFLOW_POS)) -#define I2S_RX_FIFO_UNDERFLOW I2S_RX_FIFO_UNDERFLOW -#define I2S_RX_FIFO_UNDERFLOW_POS (7U) -#define I2S_RX_FIFO_UNDERFLOW_LEN (1U) -#define I2S_RX_FIFO_UNDERFLOW_MSK (((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS) -#define I2S_RX_FIFO_UNDERFLOW_UMSK (~(((1U << I2S_RX_FIFO_UNDERFLOW_LEN) - 1) << I2S_RX_FIFO_UNDERFLOW_POS)) -#define I2S_CR_FIFO_LR_MERGE I2S_CR_FIFO_LR_MERGE -#define I2S_CR_FIFO_LR_MERGE_POS (8U) -#define I2S_CR_FIFO_LR_MERGE_LEN (1U) -#define I2S_CR_FIFO_LR_MERGE_MSK (((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS) -#define I2S_CR_FIFO_LR_MERGE_UMSK (~(((1U << I2S_CR_FIFO_LR_MERGE_LEN) - 1) << I2S_CR_FIFO_LR_MERGE_POS)) -#define I2S_CR_FIFO_LR_EXCHG I2S_CR_FIFO_LR_EXCHG -#define I2S_CR_FIFO_LR_EXCHG_POS (9U) -#define I2S_CR_FIFO_LR_EXCHG_LEN (1U) -#define I2S_CR_FIFO_LR_EXCHG_MSK (((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS) -#define I2S_CR_FIFO_LR_EXCHG_UMSK (~(((1U << I2S_CR_FIFO_LR_EXCHG_LEN) - 1) << I2S_CR_FIFO_LR_EXCHG_POS)) -#define I2S_CR_FIFO_24B_LJ I2S_CR_FIFO_24B_LJ -#define I2S_CR_FIFO_24B_LJ_POS (10U) -#define I2S_CR_FIFO_24B_LJ_LEN (1U) -#define I2S_CR_FIFO_24B_LJ_MSK (((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS) -#define I2S_CR_FIFO_24B_LJ_UMSK (~(((1U << I2S_CR_FIFO_24B_LJ_LEN) - 1) << I2S_CR_FIFO_24B_LJ_POS)) - -/* 0x84 : i2s_fifo_config_1 */ -#define I2S_FIFO_CONFIG_1_OFFSET (0x84) -#define I2S_TX_FIFO_CNT I2S_TX_FIFO_CNT -#define I2S_TX_FIFO_CNT_POS (0U) -#define I2S_TX_FIFO_CNT_LEN (5U) -#define I2S_TX_FIFO_CNT_MSK (((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS) -#define I2S_TX_FIFO_CNT_UMSK (~(((1U << I2S_TX_FIFO_CNT_LEN) - 1) << I2S_TX_FIFO_CNT_POS)) -#define I2S_RX_FIFO_CNT I2S_RX_FIFO_CNT -#define I2S_RX_FIFO_CNT_POS (8U) -#define I2S_RX_FIFO_CNT_LEN (5U) -#define I2S_RX_FIFO_CNT_MSK (((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS) -#define I2S_RX_FIFO_CNT_UMSK (~(((1U << I2S_RX_FIFO_CNT_LEN) - 1) << I2S_RX_FIFO_CNT_POS)) -#define I2S_TX_FIFO_TH I2S_TX_FIFO_TH -#define I2S_TX_FIFO_TH_POS (16U) -#define I2S_TX_FIFO_TH_LEN (4U) -#define I2S_TX_FIFO_TH_MSK (((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS) -#define I2S_TX_FIFO_TH_UMSK (~(((1U << I2S_TX_FIFO_TH_LEN) - 1) << I2S_TX_FIFO_TH_POS)) -#define I2S_RX_FIFO_TH I2S_RX_FIFO_TH -#define I2S_RX_FIFO_TH_POS (24U) -#define I2S_RX_FIFO_TH_LEN (4U) -#define I2S_RX_FIFO_TH_MSK (((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS) -#define I2S_RX_FIFO_TH_UMSK (~(((1U << I2S_RX_FIFO_TH_LEN) - 1) << I2S_RX_FIFO_TH_POS)) - -/* 0x88 : i2s_fifo_wdata */ -#define I2S_FIFO_WDATA_OFFSET (0x88) -#define I2S_FIFO_WDATA I2S_FIFO_WDATA -#define I2S_FIFO_WDATA_POS (0U) -#define I2S_FIFO_WDATA_LEN (32U) -#define I2S_FIFO_WDATA_MSK (((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS) -#define I2S_FIFO_WDATA_UMSK (~(((1U << I2S_FIFO_WDATA_LEN) - 1) << I2S_FIFO_WDATA_POS)) - -/* 0x8C : i2s_fifo_rdata */ -#define I2S_FIFO_RDATA_OFFSET (0x8C) -#define I2S_FIFO_RDATA I2S_FIFO_RDATA -#define I2S_FIFO_RDATA_POS (0U) -#define I2S_FIFO_RDATA_LEN (32U) -#define I2S_FIFO_RDATA_MSK (((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS) -#define I2S_FIFO_RDATA_UMSK (~(((1U << I2S_FIFO_RDATA_LEN) - 1) << I2S_FIFO_RDATA_POS)) - -/* 0xFC : i2s_io_config */ -#define I2S_IO_CONFIG_OFFSET (0xFC) -#define I2S_CR_I2S_TXD_INV I2S_CR_I2S_TXD_INV -#define I2S_CR_I2S_TXD_INV_POS (0U) -#define I2S_CR_I2S_TXD_INV_LEN (1U) -#define I2S_CR_I2S_TXD_INV_MSK (((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS) -#define I2S_CR_I2S_TXD_INV_UMSK (~(((1U << I2S_CR_I2S_TXD_INV_LEN) - 1) << I2S_CR_I2S_TXD_INV_POS)) -#define I2S_CR_I2S_RXD_INV I2S_CR_I2S_RXD_INV -#define I2S_CR_I2S_RXD_INV_POS (1U) -#define I2S_CR_I2S_RXD_INV_LEN (1U) -#define I2S_CR_I2S_RXD_INV_MSK (((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS) -#define I2S_CR_I2S_RXD_INV_UMSK (~(((1U << I2S_CR_I2S_RXD_INV_LEN) - 1) << I2S_CR_I2S_RXD_INV_POS)) -#define I2S_CR_I2S_FS_INV I2S_CR_I2S_FS_INV -#define I2S_CR_I2S_FS_INV_POS (2U) -#define I2S_CR_I2S_FS_INV_LEN (1U) -#define I2S_CR_I2S_FS_INV_MSK (((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS) -#define I2S_CR_I2S_FS_INV_UMSK (~(((1U << I2S_CR_I2S_FS_INV_LEN) - 1) << I2S_CR_I2S_FS_INV_POS)) -#define I2S_CR_I2S_BCLK_INV I2S_CR_I2S_BCLK_INV -#define I2S_CR_I2S_BCLK_INV_POS (3U) -#define I2S_CR_I2S_BCLK_INV_LEN (1U) -#define I2S_CR_I2S_BCLK_INV_MSK (((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS) -#define I2S_CR_I2S_BCLK_INV_UMSK (~(((1U << I2S_CR_I2S_BCLK_INV_LEN) - 1) << I2S_CR_I2S_BCLK_INV_POS)) -#define I2S_CR_DEG_CNT I2S_CR_DEG_CNT -#define I2S_CR_DEG_CNT_POS (4U) -#define I2S_CR_DEG_CNT_LEN (3U) -#define I2S_CR_DEG_CNT_MSK (((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS) -#define I2S_CR_DEG_CNT_UMSK (~(((1U << I2S_CR_DEG_CNT_LEN) - 1) << I2S_CR_DEG_CNT_POS)) -#define I2S_CR_DEG_EN I2S_CR_DEG_EN -#define I2S_CR_DEG_EN_POS (7U) -#define I2S_CR_DEG_EN_LEN (1U) -#define I2S_CR_DEG_EN_MSK (((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS) -#define I2S_CR_DEG_EN_UMSK (~(((1U << I2S_CR_DEG_EN_LEN) - 1) << I2S_CR_DEG_EN_POS)) - -struct i2s_reg { - /* 0x0 : i2s_config */ - union { - struct { - uint32_t cr_i2s_m_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_i2s_s_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_i2s_txd_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_i2s_rxd_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_mono_mode : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_mute_mode : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_fs_1t_mode : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_fs_ch_cnt : 2; /* [ 8: 7], r/w, 0x0 */ - uint32_t reserved_9_11 : 3; /* [11: 9], rsvd, 0x0 */ - uint32_t cr_frame_size : 2; /* [13:12], r/w, 0x1 */ - uint32_t cr_data_size : 2; /* [15:14], r/w, 0x1 */ - uint32_t cr_i2s_mode : 2; /* [17:16], r/w, 0x0 */ - uint32_t cr_endian : 1; /* [ 18], r/w, 0x0 */ - uint32_t cr_mono_rx_ch : 1; /* [ 19], r/w, 0x0 */ - uint32_t cr_ofs_cnt : 5; /* [24:20], r/w, 0x0 */ - uint32_t cr_ofs_en : 1; /* [ 25], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_config; - - /* 0x4 : i2s_int_sts */ - union { - struct { - uint32_t i2s_txf_int : 1; /* [ 0], r, 0x1 */ - uint32_t i2s_rxf_int : 1; /* [ 1], r, 0x0 */ - uint32_t i2s_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_i2s_txf_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_i2s_rxf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_i2s_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_23 : 13; /* [23:11], rsvd, 0x0 */ - uint32_t cr_i2s_txf_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_i2s_rxf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_i2s_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_int_sts; - - /* 0x8 reserved */ - uint8_t RESERVED0x8[8]; - - /* 0x10 : i2s_bclk_config */ - union { - struct { - uint32_t cr_bclk_div_l : 12; /* [11: 0], r/w, 0x1 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_bclk_div_h : 12; /* [27:16], r/w, 0x1 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_bclk_config; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[108]; - - /* 0x80 : i2s_fifo_config_0 */ - union { - struct { - uint32_t i2s_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t i2s_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t cr_fifo_lr_merge : 1; /* [ 8], r/w, 0x0 */ - uint32_t cr_fifo_lr_exchg : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_fifo_24b_lj : 1; /* [ 10], r/w, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_fifo_config_0; - - /* 0x84 : i2s_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 5; /* [ 4: 0], r, 0x10 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t tx_fifo_th : 4; /* [19:16], r/w, 0x0 */ - uint32_t reserved_20_23 : 4; /* [23:20], rsvd, 0x0 */ - uint32_t rx_fifo_th : 4; /* [27:24], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_fifo_config_1; - - /* 0x88 : i2s_fifo_wdata */ - union { - struct { - uint32_t i2s_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } i2s_fifo_wdata; - - /* 0x8C : i2s_fifo_rdata */ - union { - struct { - uint32_t i2s_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } i2s_fifo_rdata; - - /* 0x90 reserved */ - uint8_t RESERVED0x90[108]; - - /* 0xFC : i2s_io_config */ - union { - struct { - uint32_t cr_i2s_txd_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_i2s_rxd_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_i2s_fs_inv : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_i2s_bclk_inv : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_deg_cnt : 3; /* [ 6: 4], r/w, 0x0 */ - uint32_t cr_deg_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } i2s_io_config; -}; - -typedef volatile struct i2s_reg i2s_reg_t; - -#endif /* __I2S_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ir_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ir_reg.h deleted file mode 100644 index 8cffd08359..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ir_reg.h +++ /dev/null @@ -1,646 +0,0 @@ -/** - ****************************************************************************** - * @file ir_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __IR_REG_H__ -#define __IR_REG_H__ - -#include "bl808.h" - -/* 0x0 : irtx_config */ -#define IRTX_CONFIG_OFFSET (0x0) -#define IR_CR_IRTX_EN IR_CR_IRTX_EN -#define IR_CR_IRTX_EN_POS (0U) -#define IR_CR_IRTX_EN_LEN (1U) -#define IR_CR_IRTX_EN_MSK (((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS) -#define IR_CR_IRTX_EN_UMSK (~(((1U << IR_CR_IRTX_EN_LEN) - 1) << IR_CR_IRTX_EN_POS)) -#define IR_CR_IRTX_OUT_INV IR_CR_IRTX_OUT_INV -#define IR_CR_IRTX_OUT_INV_POS (1U) -#define IR_CR_IRTX_OUT_INV_LEN (1U) -#define IR_CR_IRTX_OUT_INV_MSK (((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS) -#define IR_CR_IRTX_OUT_INV_UMSK (~(((1U << IR_CR_IRTX_OUT_INV_LEN) - 1) << IR_CR_IRTX_OUT_INV_POS)) -#define IR_CR_IRTX_MOD_EN IR_CR_IRTX_MOD_EN -#define IR_CR_IRTX_MOD_EN_POS (2U) -#define IR_CR_IRTX_MOD_EN_LEN (1U) -#define IR_CR_IRTX_MOD_EN_MSK (((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS) -#define IR_CR_IRTX_MOD_EN_UMSK (~(((1U << IR_CR_IRTX_MOD_EN_LEN) - 1) << IR_CR_IRTX_MOD_EN_POS)) -#define IR_CR_IRTX_SWM_EN IR_CR_IRTX_SWM_EN -#define IR_CR_IRTX_SWM_EN_POS (3U) -#define IR_CR_IRTX_SWM_EN_LEN (1U) -#define IR_CR_IRTX_SWM_EN_MSK (((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS) -#define IR_CR_IRTX_SWM_EN_UMSK (~(((1U << IR_CR_IRTX_SWM_EN_LEN) - 1) << IR_CR_IRTX_SWM_EN_POS)) -#define IR_CR_IRTX_DATA_EN IR_CR_IRTX_DATA_EN -#define IR_CR_IRTX_DATA_EN_POS (4U) -#define IR_CR_IRTX_DATA_EN_LEN (1U) -#define IR_CR_IRTX_DATA_EN_MSK (((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS) -#define IR_CR_IRTX_DATA_EN_UMSK (~(((1U << IR_CR_IRTX_DATA_EN_LEN) - 1) << IR_CR_IRTX_DATA_EN_POS)) -#define IR_CR_IRTX_LOGIC0_HL_INV IR_CR_IRTX_LOGIC0_HL_INV -#define IR_CR_IRTX_LOGIC0_HL_INV_POS (5U) -#define IR_CR_IRTX_LOGIC0_HL_INV_LEN (1U) -#define IR_CR_IRTX_LOGIC0_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS) -#define IR_CR_IRTX_LOGIC0_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC0_HL_INV_POS)) -#define IR_CR_IRTX_LOGIC1_HL_INV IR_CR_IRTX_LOGIC1_HL_INV -#define IR_CR_IRTX_LOGIC1_HL_INV_POS (6U) -#define IR_CR_IRTX_LOGIC1_HL_INV_LEN (1U) -#define IR_CR_IRTX_LOGIC1_HL_INV_MSK (((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS) -#define IR_CR_IRTX_LOGIC1_HL_INV_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_HL_INV_LEN) - 1) << IR_CR_IRTX_LOGIC1_HL_INV_POS)) -#define IR_CR_IRTX_HEAD_EN IR_CR_IRTX_HEAD_EN -#define IR_CR_IRTX_HEAD_EN_POS (8U) -#define IR_CR_IRTX_HEAD_EN_LEN (1U) -#define IR_CR_IRTX_HEAD_EN_MSK (((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS) -#define IR_CR_IRTX_HEAD_EN_UMSK (~(((1U << IR_CR_IRTX_HEAD_EN_LEN) - 1) << IR_CR_IRTX_HEAD_EN_POS)) -#define IR_CR_IRTX_HEAD_HL_INV IR_CR_IRTX_HEAD_HL_INV -#define IR_CR_IRTX_HEAD_HL_INV_POS (9U) -#define IR_CR_IRTX_HEAD_HL_INV_LEN (1U) -#define IR_CR_IRTX_HEAD_HL_INV_MSK (((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS) -#define IR_CR_IRTX_HEAD_HL_INV_UMSK (~(((1U << IR_CR_IRTX_HEAD_HL_INV_LEN) - 1) << IR_CR_IRTX_HEAD_HL_INV_POS)) -#define IR_CR_IRTX_TAIL_EN IR_CR_IRTX_TAIL_EN -#define IR_CR_IRTX_TAIL_EN_POS (10U) -#define IR_CR_IRTX_TAIL_EN_LEN (1U) -#define IR_CR_IRTX_TAIL_EN_MSK (((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS) -#define IR_CR_IRTX_TAIL_EN_UMSK (~(((1U << IR_CR_IRTX_TAIL_EN_LEN) - 1) << IR_CR_IRTX_TAIL_EN_POS)) -#define IR_CR_IRTX_TAIL_HL_INV IR_CR_IRTX_TAIL_HL_INV -#define IR_CR_IRTX_TAIL_HL_INV_POS (11U) -#define IR_CR_IRTX_TAIL_HL_INV_LEN (1U) -#define IR_CR_IRTX_TAIL_HL_INV_MSK (((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS) -#define IR_CR_IRTX_TAIL_HL_INV_UMSK (~(((1U << IR_CR_IRTX_TAIL_HL_INV_LEN) - 1) << IR_CR_IRTX_TAIL_HL_INV_POS)) -#define IR_CR_IRTX_FRM_EN IR_CR_IRTX_FRM_EN -#define IR_CR_IRTX_FRM_EN_POS (12U) -#define IR_CR_IRTX_FRM_EN_LEN (1U) -#define IR_CR_IRTX_FRM_EN_MSK (((1U << IR_CR_IRTX_FRM_EN_LEN) - 1) << IR_CR_IRTX_FRM_EN_POS) -#define IR_CR_IRTX_FRM_EN_UMSK (~(((1U << IR_CR_IRTX_FRM_EN_LEN) - 1) << IR_CR_IRTX_FRM_EN_POS)) -#define IR_CR_IRTX_FRM_CONT_EN IR_CR_IRTX_FRM_CONT_EN -#define IR_CR_IRTX_FRM_CONT_EN_POS (13U) -#define IR_CR_IRTX_FRM_CONT_EN_LEN (1U) -#define IR_CR_IRTX_FRM_CONT_EN_MSK (((1U << IR_CR_IRTX_FRM_CONT_EN_LEN) - 1) << IR_CR_IRTX_FRM_CONT_EN_POS) -#define IR_CR_IRTX_FRM_CONT_EN_UMSK (~(((1U << IR_CR_IRTX_FRM_CONT_EN_LEN) - 1) << IR_CR_IRTX_FRM_CONT_EN_POS)) -#define IR_CR_IRTX_FRM_FRAME_SIZE IR_CR_IRTX_FRM_FRAME_SIZE -#define IR_CR_IRTX_FRM_FRAME_SIZE_POS (14U) -#define IR_CR_IRTX_FRM_FRAME_SIZE_LEN (2U) -#define IR_CR_IRTX_FRM_FRAME_SIZE_MSK (((1U << IR_CR_IRTX_FRM_FRAME_SIZE_LEN) - 1) << IR_CR_IRTX_FRM_FRAME_SIZE_POS) -#define IR_CR_IRTX_FRM_FRAME_SIZE_UMSK (~(((1U << IR_CR_IRTX_FRM_FRAME_SIZE_LEN) - 1) << IR_CR_IRTX_FRM_FRAME_SIZE_POS)) -#define IR_CR_IRTX_DATA_NUM IR_CR_IRTX_DATA_NUM -#define IR_CR_IRTX_DATA_NUM_POS (16U) -#define IR_CR_IRTX_DATA_NUM_LEN (7U) -#define IR_CR_IRTX_DATA_NUM_MSK (((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS) -#define IR_CR_IRTX_DATA_NUM_UMSK (~(((1U << IR_CR_IRTX_DATA_NUM_LEN) - 1) << IR_CR_IRTX_DATA_NUM_POS)) - -/* 0x4 : irtx_int_sts */ -#define IRTX_INT_STS_OFFSET (0x4) -#define IRTX_END_INT IRTX_END_INT -#define IRTX_END_INT_POS (0U) -#define IRTX_END_INT_LEN (1U) -#define IRTX_END_INT_MSK (((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS) -#define IRTX_END_INT_UMSK (~(((1U << IRTX_END_INT_LEN) - 1) << IRTX_END_INT_POS)) -#define IRTX_FRDY_INT IRTX_FRDY_INT -#define IRTX_FRDY_INT_POS (1U) -#define IRTX_FRDY_INT_LEN (1U) -#define IRTX_FRDY_INT_MSK (((1U << IRTX_FRDY_INT_LEN) - 1) << IRTX_FRDY_INT_POS) -#define IRTX_FRDY_INT_UMSK (~(((1U << IRTX_FRDY_INT_LEN) - 1) << IRTX_FRDY_INT_POS)) -#define IRTX_FER_INT IRTX_FER_INT -#define IRTX_FER_INT_POS (2U) -#define IRTX_FER_INT_LEN (1U) -#define IRTX_FER_INT_MSK (((1U << IRTX_FER_INT_LEN) - 1) << IRTX_FER_INT_POS) -#define IRTX_FER_INT_UMSK (~(((1U << IRTX_FER_INT_LEN) - 1) << IRTX_FER_INT_POS)) -#define IR_CR_IRTX_END_MASK IR_CR_IRTX_END_MASK -#define IR_CR_IRTX_END_MASK_POS (8U) -#define IR_CR_IRTX_END_MASK_LEN (1U) -#define IR_CR_IRTX_END_MASK_MSK (((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS) -#define IR_CR_IRTX_END_MASK_UMSK (~(((1U << IR_CR_IRTX_END_MASK_LEN) - 1) << IR_CR_IRTX_END_MASK_POS)) -#define IR_CR_IRTX_FRDY_MASK IR_CR_IRTX_FRDY_MASK -#define IR_CR_IRTX_FRDY_MASK_POS (9U) -#define IR_CR_IRTX_FRDY_MASK_LEN (1U) -#define IR_CR_IRTX_FRDY_MASK_MSK (((1U << IR_CR_IRTX_FRDY_MASK_LEN) - 1) << IR_CR_IRTX_FRDY_MASK_POS) -#define IR_CR_IRTX_FRDY_MASK_UMSK (~(((1U << IR_CR_IRTX_FRDY_MASK_LEN) - 1) << IR_CR_IRTX_FRDY_MASK_POS)) -#define IR_CR_IRTX_FER_MASK IR_CR_IRTX_FER_MASK -#define IR_CR_IRTX_FER_MASK_POS (10U) -#define IR_CR_IRTX_FER_MASK_LEN (1U) -#define IR_CR_IRTX_FER_MASK_MSK (((1U << IR_CR_IRTX_FER_MASK_LEN) - 1) << IR_CR_IRTX_FER_MASK_POS) -#define IR_CR_IRTX_FER_MASK_UMSK (~(((1U << IR_CR_IRTX_FER_MASK_LEN) - 1) << IR_CR_IRTX_FER_MASK_POS)) -#define IR_CR_IRTX_END_CLR IR_CR_IRTX_END_CLR -#define IR_CR_IRTX_END_CLR_POS (16U) -#define IR_CR_IRTX_END_CLR_LEN (1U) -#define IR_CR_IRTX_END_CLR_MSK (((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS) -#define IR_CR_IRTX_END_CLR_UMSK (~(((1U << IR_CR_IRTX_END_CLR_LEN) - 1) << IR_CR_IRTX_END_CLR_POS)) -#define IR_CR_IRTX_END_EN IR_CR_IRTX_END_EN -#define IR_CR_IRTX_END_EN_POS (24U) -#define IR_CR_IRTX_END_EN_LEN (1U) -#define IR_CR_IRTX_END_EN_MSK (((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS) -#define IR_CR_IRTX_END_EN_UMSK (~(((1U << IR_CR_IRTX_END_EN_LEN) - 1) << IR_CR_IRTX_END_EN_POS)) -#define IR_CR_IRTX_FRDY_EN IR_CR_IRTX_FRDY_EN -#define IR_CR_IRTX_FRDY_EN_POS (25U) -#define IR_CR_IRTX_FRDY_EN_LEN (1U) -#define IR_CR_IRTX_FRDY_EN_MSK (((1U << IR_CR_IRTX_FRDY_EN_LEN) - 1) << IR_CR_IRTX_FRDY_EN_POS) -#define IR_CR_IRTX_FRDY_EN_UMSK (~(((1U << IR_CR_IRTX_FRDY_EN_LEN) - 1) << IR_CR_IRTX_FRDY_EN_POS)) -#define IR_CR_IRTX_FER_EN IR_CR_IRTX_FER_EN -#define IR_CR_IRTX_FER_EN_POS (26U) -#define IR_CR_IRTX_FER_EN_LEN (1U) -#define IR_CR_IRTX_FER_EN_MSK (((1U << IR_CR_IRTX_FER_EN_LEN) - 1) << IR_CR_IRTX_FER_EN_POS) -#define IR_CR_IRTX_FER_EN_UMSK (~(((1U << IR_CR_IRTX_FER_EN_LEN) - 1) << IR_CR_IRTX_FER_EN_POS)) - -/* 0x10 : irtx_pulse_width */ -#define IRTX_PULSE_WIDTH_OFFSET (0x10) -#define IR_CR_IRTX_PW_UNIT IR_CR_IRTX_PW_UNIT -#define IR_CR_IRTX_PW_UNIT_POS (0U) -#define IR_CR_IRTX_PW_UNIT_LEN (12U) -#define IR_CR_IRTX_PW_UNIT_MSK (((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS) -#define IR_CR_IRTX_PW_UNIT_UMSK (~(((1U << IR_CR_IRTX_PW_UNIT_LEN) - 1) << IR_CR_IRTX_PW_UNIT_POS)) -#define IR_CR_IRTX_MOD_PH0_W IR_CR_IRTX_MOD_PH0_W -#define IR_CR_IRTX_MOD_PH0_W_POS (16U) -#define IR_CR_IRTX_MOD_PH0_W_LEN (8U) -#define IR_CR_IRTX_MOD_PH0_W_MSK (((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS) -#define IR_CR_IRTX_MOD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH0_W_LEN) - 1) << IR_CR_IRTX_MOD_PH0_W_POS)) -#define IR_CR_IRTX_MOD_PH1_W IR_CR_IRTX_MOD_PH1_W -#define IR_CR_IRTX_MOD_PH1_W_POS (24U) -#define IR_CR_IRTX_MOD_PH1_W_LEN (8U) -#define IR_CR_IRTX_MOD_PH1_W_MSK (((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS) -#define IR_CR_IRTX_MOD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_MOD_PH1_W_LEN) - 1) << IR_CR_IRTX_MOD_PH1_W_POS)) - -/* 0x14 : irtx_pw_0 */ -#define IRTX_PW_0_OFFSET (0x14) -#define IR_CR_IRTX_LOGIC0_PH0_W IR_CR_IRTX_LOGIC0_PH0_W -#define IR_CR_IRTX_LOGIC0_PH0_W_POS (0U) -#define IR_CR_IRTX_LOGIC0_PH0_W_LEN (8U) -#define IR_CR_IRTX_LOGIC0_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS) -#define IR_CR_IRTX_LOGIC0_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH0_W_POS)) -#define IR_CR_IRTX_LOGIC0_PH1_W IR_CR_IRTX_LOGIC0_PH1_W -#define IR_CR_IRTX_LOGIC0_PH1_W_POS (8U) -#define IR_CR_IRTX_LOGIC0_PH1_W_LEN (8U) -#define IR_CR_IRTX_LOGIC0_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS) -#define IR_CR_IRTX_LOGIC0_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC0_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC0_PH1_W_POS)) -#define IR_CR_IRTX_LOGIC1_PH0_W IR_CR_IRTX_LOGIC1_PH0_W -#define IR_CR_IRTX_LOGIC1_PH0_W_POS (16U) -#define IR_CR_IRTX_LOGIC1_PH0_W_LEN (8U) -#define IR_CR_IRTX_LOGIC1_PH0_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS) -#define IR_CR_IRTX_LOGIC1_PH0_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH0_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH0_W_POS)) -#define IR_CR_IRTX_LOGIC1_PH1_W IR_CR_IRTX_LOGIC1_PH1_W -#define IR_CR_IRTX_LOGIC1_PH1_W_POS (24U) -#define IR_CR_IRTX_LOGIC1_PH1_W_LEN (8U) -#define IR_CR_IRTX_LOGIC1_PH1_W_MSK (((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS) -#define IR_CR_IRTX_LOGIC1_PH1_W_UMSK (~(((1U << IR_CR_IRTX_LOGIC1_PH1_W_LEN) - 1) << IR_CR_IRTX_LOGIC1_PH1_W_POS)) - -/* 0x18 : irtx_pw_1 */ -#define IRTX_PW_1_OFFSET (0x18) -#define IR_CR_IRTX_HEAD_PH0_W IR_CR_IRTX_HEAD_PH0_W -#define IR_CR_IRTX_HEAD_PH0_W_POS (0U) -#define IR_CR_IRTX_HEAD_PH0_W_LEN (8U) -#define IR_CR_IRTX_HEAD_PH0_W_MSK (((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS) -#define IR_CR_IRTX_HEAD_PH0_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH0_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH0_W_POS)) -#define IR_CR_IRTX_HEAD_PH1_W IR_CR_IRTX_HEAD_PH1_W -#define IR_CR_IRTX_HEAD_PH1_W_POS (8U) -#define IR_CR_IRTX_HEAD_PH1_W_LEN (8U) -#define IR_CR_IRTX_HEAD_PH1_W_MSK (((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS) -#define IR_CR_IRTX_HEAD_PH1_W_UMSK (~(((1U << IR_CR_IRTX_HEAD_PH1_W_LEN) - 1) << IR_CR_IRTX_HEAD_PH1_W_POS)) -#define IR_CR_IRTX_TAIL_PH0_W IR_CR_IRTX_TAIL_PH0_W -#define IR_CR_IRTX_TAIL_PH0_W_POS (16U) -#define IR_CR_IRTX_TAIL_PH0_W_LEN (8U) -#define IR_CR_IRTX_TAIL_PH0_W_MSK (((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS) -#define IR_CR_IRTX_TAIL_PH0_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH0_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH0_W_POS)) -#define IR_CR_IRTX_TAIL_PH1_W IR_CR_IRTX_TAIL_PH1_W -#define IR_CR_IRTX_TAIL_PH1_W_POS (24U) -#define IR_CR_IRTX_TAIL_PH1_W_LEN (8U) -#define IR_CR_IRTX_TAIL_PH1_W_MSK (((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS) -#define IR_CR_IRTX_TAIL_PH1_W_UMSK (~(((1U << IR_CR_IRTX_TAIL_PH1_W_LEN) - 1) << IR_CR_IRTX_TAIL_PH1_W_POS)) - -/* 0x40 : irrx_config */ -#define IRRX_CONFIG_OFFSET (0x40) -#define IR_CR_IRRX_EN IR_CR_IRRX_EN -#define IR_CR_IRRX_EN_POS (0U) -#define IR_CR_IRRX_EN_LEN (1U) -#define IR_CR_IRRX_EN_MSK (((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS) -#define IR_CR_IRRX_EN_UMSK (~(((1U << IR_CR_IRRX_EN_LEN) - 1) << IR_CR_IRRX_EN_POS)) -#define IR_CR_IRRX_IN_INV IR_CR_IRRX_IN_INV -#define IR_CR_IRRX_IN_INV_POS (1U) -#define IR_CR_IRRX_IN_INV_LEN (1U) -#define IR_CR_IRRX_IN_INV_MSK (((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS) -#define IR_CR_IRRX_IN_INV_UMSK (~(((1U << IR_CR_IRRX_IN_INV_LEN) - 1) << IR_CR_IRRX_IN_INV_POS)) -#define IR_CR_IRRX_MODE IR_CR_IRRX_MODE -#define IR_CR_IRRX_MODE_POS (2U) -#define IR_CR_IRRX_MODE_LEN (2U) -#define IR_CR_IRRX_MODE_MSK (((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS) -#define IR_CR_IRRX_MODE_UMSK (~(((1U << IR_CR_IRRX_MODE_LEN) - 1) << IR_CR_IRRX_MODE_POS)) -#define IR_CR_IRRX_DEG_EN IR_CR_IRRX_DEG_EN -#define IR_CR_IRRX_DEG_EN_POS (4U) -#define IR_CR_IRRX_DEG_EN_LEN (1U) -#define IR_CR_IRRX_DEG_EN_MSK (((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS) -#define IR_CR_IRRX_DEG_EN_UMSK (~(((1U << IR_CR_IRRX_DEG_EN_LEN) - 1) << IR_CR_IRRX_DEG_EN_POS)) -#define IR_CR_IRRX_DEG_CNT IR_CR_IRRX_DEG_CNT -#define IR_CR_IRRX_DEG_CNT_POS (8U) -#define IR_CR_IRRX_DEG_CNT_LEN (4U) -#define IR_CR_IRRX_DEG_CNT_MSK (((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS) -#define IR_CR_IRRX_DEG_CNT_UMSK (~(((1U << IR_CR_IRRX_DEG_CNT_LEN) - 1) << IR_CR_IRRX_DEG_CNT_POS)) - -/* 0x44 : irrx_int_sts */ -#define IRRX_INT_STS_OFFSET (0x44) -#define IRRX_END_INT IRRX_END_INT -#define IRRX_END_INT_POS (0U) -#define IRRX_END_INT_LEN (1U) -#define IRRX_END_INT_MSK (((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS) -#define IRRX_END_INT_UMSK (~(((1U << IRRX_END_INT_LEN) - 1) << IRRX_END_INT_POS)) -#define IRRX_FRDY_INT IRRX_FRDY_INT -#define IRRX_FRDY_INT_POS (1U) -#define IRRX_FRDY_INT_LEN (1U) -#define IRRX_FRDY_INT_MSK (((1U << IRRX_FRDY_INT_LEN) - 1) << IRRX_FRDY_INT_POS) -#define IRRX_FRDY_INT_UMSK (~(((1U << IRRX_FRDY_INT_LEN) - 1) << IRRX_FRDY_INT_POS)) -#define IRRX_FER_INT IRRX_FER_INT -#define IRRX_FER_INT_POS (2U) -#define IRRX_FER_INT_LEN (1U) -#define IRRX_FER_INT_MSK (((1U << IRRX_FER_INT_LEN) - 1) << IRRX_FER_INT_POS) -#define IRRX_FER_INT_UMSK (~(((1U << IRRX_FER_INT_LEN) - 1) << IRRX_FER_INT_POS)) -#define IR_CR_IRRX_END_MASK IR_CR_IRRX_END_MASK -#define IR_CR_IRRX_END_MASK_POS (8U) -#define IR_CR_IRRX_END_MASK_LEN (1U) -#define IR_CR_IRRX_END_MASK_MSK (((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS) -#define IR_CR_IRRX_END_MASK_UMSK (~(((1U << IR_CR_IRRX_END_MASK_LEN) - 1) << IR_CR_IRRX_END_MASK_POS)) -#define IR_CR_IRRX_FRDY_MASK IR_CR_IRRX_FRDY_MASK -#define IR_CR_IRRX_FRDY_MASK_POS (9U) -#define IR_CR_IRRX_FRDY_MASK_LEN (1U) -#define IR_CR_IRRX_FRDY_MASK_MSK (((1U << IR_CR_IRRX_FRDY_MASK_LEN) - 1) << IR_CR_IRRX_FRDY_MASK_POS) -#define IR_CR_IRRX_FRDY_MASK_UMSK (~(((1U << IR_CR_IRRX_FRDY_MASK_LEN) - 1) << IR_CR_IRRX_FRDY_MASK_POS)) -#define IR_CR_IRRX_FER_MASK IR_CR_IRRX_FER_MASK -#define IR_CR_IRRX_FER_MASK_POS (10U) -#define IR_CR_IRRX_FER_MASK_LEN (1U) -#define IR_CR_IRRX_FER_MASK_MSK (((1U << IR_CR_IRRX_FER_MASK_LEN) - 1) << IR_CR_IRRX_FER_MASK_POS) -#define IR_CR_IRRX_FER_MASK_UMSK (~(((1U << IR_CR_IRRX_FER_MASK_LEN) - 1) << IR_CR_IRRX_FER_MASK_POS)) -#define IR_CR_IRRX_END_CLR IR_CR_IRRX_END_CLR -#define IR_CR_IRRX_END_CLR_POS (16U) -#define IR_CR_IRRX_END_CLR_LEN (1U) -#define IR_CR_IRRX_END_CLR_MSK (((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS) -#define IR_CR_IRRX_END_CLR_UMSK (~(((1U << IR_CR_IRRX_END_CLR_LEN) - 1) << IR_CR_IRRX_END_CLR_POS)) -#define IR_CR_IRRX_END_EN IR_CR_IRRX_END_EN -#define IR_CR_IRRX_END_EN_POS (24U) -#define IR_CR_IRRX_END_EN_LEN (1U) -#define IR_CR_IRRX_END_EN_MSK (((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS) -#define IR_CR_IRRX_END_EN_UMSK (~(((1U << IR_CR_IRRX_END_EN_LEN) - 1) << IR_CR_IRRX_END_EN_POS)) -#define IR_CR_IRRX_FRDY_EN IR_CR_IRRX_FRDY_EN -#define IR_CR_IRRX_FRDY_EN_POS (25U) -#define IR_CR_IRRX_FRDY_EN_LEN (1U) -#define IR_CR_IRRX_FRDY_EN_MSK (((1U << IR_CR_IRRX_FRDY_EN_LEN) - 1) << IR_CR_IRRX_FRDY_EN_POS) -#define IR_CR_IRRX_FRDY_EN_UMSK (~(((1U << IR_CR_IRRX_FRDY_EN_LEN) - 1) << IR_CR_IRRX_FRDY_EN_POS)) -#define IR_CR_IRRX_FER_EN IR_CR_IRRX_FER_EN -#define IR_CR_IRRX_FER_EN_POS (26U) -#define IR_CR_IRRX_FER_EN_LEN (1U) -#define IR_CR_IRRX_FER_EN_MSK (((1U << IR_CR_IRRX_FER_EN_LEN) - 1) << IR_CR_IRRX_FER_EN_POS) -#define IR_CR_IRRX_FER_EN_UMSK (~(((1U << IR_CR_IRRX_FER_EN_LEN) - 1) << IR_CR_IRRX_FER_EN_POS)) - -/* 0x48 : irrx_pw_config */ -#define IRRX_PW_CONFIG_OFFSET (0x48) -#define IR_CR_IRRX_DATA_TH IR_CR_IRRX_DATA_TH -#define IR_CR_IRRX_DATA_TH_POS (0U) -#define IR_CR_IRRX_DATA_TH_LEN (16U) -#define IR_CR_IRRX_DATA_TH_MSK (((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS) -#define IR_CR_IRRX_DATA_TH_UMSK (~(((1U << IR_CR_IRRX_DATA_TH_LEN) - 1) << IR_CR_IRRX_DATA_TH_POS)) -#define IR_CR_IRRX_END_TH IR_CR_IRRX_END_TH -#define IR_CR_IRRX_END_TH_POS (16U) -#define IR_CR_IRRX_END_TH_LEN (16U) -#define IR_CR_IRRX_END_TH_MSK (((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS) -#define IR_CR_IRRX_END_TH_UMSK (~(((1U << IR_CR_IRRX_END_TH_LEN) - 1) << IR_CR_IRRX_END_TH_POS)) - -/* 0x50 : irrx_data_count */ -#define IRRX_DATA_COUNT_OFFSET (0x50) -#define IR_STS_IRRX_DATA_CNT IR_STS_IRRX_DATA_CNT -#define IR_STS_IRRX_DATA_CNT_POS (0U) -#define IR_STS_IRRX_DATA_CNT_LEN (7U) -#define IR_STS_IRRX_DATA_CNT_MSK (((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS) -#define IR_STS_IRRX_DATA_CNT_UMSK (~(((1U << IR_STS_IRRX_DATA_CNT_LEN) - 1) << IR_STS_IRRX_DATA_CNT_POS)) - -/* 0x54 : irrx_data_word0 */ -#define IRRX_DATA_WORD0_OFFSET (0x54) -#define IR_STS_IRRX_DATA_WORD0 IR_STS_IRRX_DATA_WORD0 -#define IR_STS_IRRX_DATA_WORD0_POS (0U) -#define IR_STS_IRRX_DATA_WORD0_LEN (32U) -#define IR_STS_IRRX_DATA_WORD0_MSK (((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS) -#define IR_STS_IRRX_DATA_WORD0_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD0_LEN) - 1) << IR_STS_IRRX_DATA_WORD0_POS)) - -/* 0x58 : irrx_data_word1 */ -#define IRRX_DATA_WORD1_OFFSET (0x58) -#define IR_STS_IRRX_DATA_WORD1 IR_STS_IRRX_DATA_WORD1 -#define IR_STS_IRRX_DATA_WORD1_POS (0U) -#define IR_STS_IRRX_DATA_WORD1_LEN (32U) -#define IR_STS_IRRX_DATA_WORD1_MSK (((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS) -#define IR_STS_IRRX_DATA_WORD1_UMSK (~(((1U << IR_STS_IRRX_DATA_WORD1_LEN) - 1) << IR_STS_IRRX_DATA_WORD1_POS)) - -/* 0x80 : irtx_fifo_config_0 */ -#define IRTX_FIFO_CONFIG_0_OFFSET (0x80) -#define IRTX_DMA_EN IRTX_DMA_EN -#define IRTX_DMA_EN_POS (0U) -#define IRTX_DMA_EN_LEN (1U) -#define IRTX_DMA_EN_MSK (((1U << IRTX_DMA_EN_LEN) - 1) << IRTX_DMA_EN_POS) -#define IRTX_DMA_EN_UMSK (~(((1U << IRTX_DMA_EN_LEN) - 1) << IRTX_DMA_EN_POS)) -#define IR_TX_FIFO_CLR IR_TX_FIFO_CLR -#define IR_TX_FIFO_CLR_POS (2U) -#define IR_TX_FIFO_CLR_LEN (1U) -#define IR_TX_FIFO_CLR_MSK (((1U << IR_TX_FIFO_CLR_LEN) - 1) << IR_TX_FIFO_CLR_POS) -#define IR_TX_FIFO_CLR_UMSK (~(((1U << IR_TX_FIFO_CLR_LEN) - 1) << IR_TX_FIFO_CLR_POS)) -#define IR_RX_FIFO_CLR IR_RX_FIFO_CLR -#define IR_RX_FIFO_CLR_POS (3U) -#define IR_RX_FIFO_CLR_LEN (1U) -#define IR_RX_FIFO_CLR_MSK (((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS) -#define IR_RX_FIFO_CLR_UMSK (~(((1U << IR_RX_FIFO_CLR_LEN) - 1) << IR_RX_FIFO_CLR_POS)) -#define IR_TX_FIFO_OVERFLOW IR_TX_FIFO_OVERFLOW -#define IR_TX_FIFO_OVERFLOW_POS (4U) -#define IR_TX_FIFO_OVERFLOW_LEN (1U) -#define IR_TX_FIFO_OVERFLOW_MSK (((1U << IR_TX_FIFO_OVERFLOW_LEN) - 1) << IR_TX_FIFO_OVERFLOW_POS) -#define IR_TX_FIFO_OVERFLOW_UMSK (~(((1U << IR_TX_FIFO_OVERFLOW_LEN) - 1) << IR_TX_FIFO_OVERFLOW_POS)) -#define IR_TX_FIFO_UNDERFLOW IR_TX_FIFO_UNDERFLOW -#define IR_TX_FIFO_UNDERFLOW_POS (5U) -#define IR_TX_FIFO_UNDERFLOW_LEN (1U) -#define IR_TX_FIFO_UNDERFLOW_MSK (((1U << IR_TX_FIFO_UNDERFLOW_LEN) - 1) << IR_TX_FIFO_UNDERFLOW_POS) -#define IR_TX_FIFO_UNDERFLOW_UMSK (~(((1U << IR_TX_FIFO_UNDERFLOW_LEN) - 1) << IR_TX_FIFO_UNDERFLOW_POS)) -#define IR_RX_FIFO_OVERFLOW IR_RX_FIFO_OVERFLOW -#define IR_RX_FIFO_OVERFLOW_POS (6U) -#define IR_RX_FIFO_OVERFLOW_LEN (1U) -#define IR_RX_FIFO_OVERFLOW_MSK (((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS) -#define IR_RX_FIFO_OVERFLOW_UMSK (~(((1U << IR_RX_FIFO_OVERFLOW_LEN) - 1) << IR_RX_FIFO_OVERFLOW_POS)) -#define IR_RX_FIFO_UNDERFLOW IR_RX_FIFO_UNDERFLOW -#define IR_RX_FIFO_UNDERFLOW_POS (7U) -#define IR_RX_FIFO_UNDERFLOW_LEN (1U) -#define IR_RX_FIFO_UNDERFLOW_MSK (((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS) -#define IR_RX_FIFO_UNDERFLOW_UMSK (~(((1U << IR_RX_FIFO_UNDERFLOW_LEN) - 1) << IR_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : irtx_fifo_config_1 */ -#define IRTX_FIFO_CONFIG_1_OFFSET (0x84) -#define IR_TX_FIFO_CNT IR_TX_FIFO_CNT -#define IR_TX_FIFO_CNT_POS (0U) -#define IR_TX_FIFO_CNT_LEN (3U) -#define IR_TX_FIFO_CNT_MSK (((1U << IR_TX_FIFO_CNT_LEN) - 1) << IR_TX_FIFO_CNT_POS) -#define IR_TX_FIFO_CNT_UMSK (~(((1U << IR_TX_FIFO_CNT_LEN) - 1) << IR_TX_FIFO_CNT_POS)) -#define IR_RX_FIFO_CNT IR_RX_FIFO_CNT -#define IR_RX_FIFO_CNT_POS (8U) -#define IR_RX_FIFO_CNT_LEN (7U) -#define IR_RX_FIFO_CNT_MSK (((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS) -#define IR_RX_FIFO_CNT_UMSK (~(((1U << IR_RX_FIFO_CNT_LEN) - 1) << IR_RX_FIFO_CNT_POS)) -#define IR_TX_FIFO_TH IR_TX_FIFO_TH -#define IR_TX_FIFO_TH_POS (16U) -#define IR_TX_FIFO_TH_LEN (2U) -#define IR_TX_FIFO_TH_MSK (((1U << IR_TX_FIFO_TH_LEN) - 1) << IR_TX_FIFO_TH_POS) -#define IR_TX_FIFO_TH_UMSK (~(((1U << IR_TX_FIFO_TH_LEN) - 1) << IR_TX_FIFO_TH_POS)) -#define IR_RX_FIFO_TH IR_RX_FIFO_TH -#define IR_RX_FIFO_TH_POS (24U) -#define IR_RX_FIFO_TH_LEN (6U) -#define IR_RX_FIFO_TH_MSK (((1U << IR_RX_FIFO_TH_LEN) - 1) << IR_RX_FIFO_TH_POS) -#define IR_RX_FIFO_TH_UMSK (~(((1U << IR_RX_FIFO_TH_LEN) - 1) << IR_RX_FIFO_TH_POS)) - -/* 0x88 : ir_fifo_wdata */ -#define IR_FIFO_WDATA_OFFSET (0x88) -#define IR_TX_FIFO_WDATA IR_TX_FIFO_WDATA -#define IR_TX_FIFO_WDATA_POS (0U) -#define IR_TX_FIFO_WDATA_LEN (32U) -#define IR_TX_FIFO_WDATA_MSK (((1U << IR_TX_FIFO_WDATA_LEN) - 1) << IR_TX_FIFO_WDATA_POS) -#define IR_TX_FIFO_WDATA_UMSK (~(((1U << IR_TX_FIFO_WDATA_LEN) - 1) << IR_TX_FIFO_WDATA_POS)) - -/* 0x8C : ir_fifo_rdata */ -#define IR_FIFO_RDATA_OFFSET (0x8C) -#define IR_RX_FIFO_RDATA IR_RX_FIFO_RDATA -#define IR_RX_FIFO_RDATA_POS (0U) -#define IR_RX_FIFO_RDATA_LEN (16U) -#define IR_RX_FIFO_RDATA_MSK (((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS) -#define IR_RX_FIFO_RDATA_UMSK (~(((1U << IR_RX_FIFO_RDATA_LEN) - 1) << IR_RX_FIFO_RDATA_POS)) - -struct ir_reg { - /* 0x0 : irtx_config */ - union { - struct { - uint32_t cr_irtx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_irtx_out_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_irtx_mod_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_irtx_swm_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_irtx_data_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_irtx_logic0_hl_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_irtx_logic1_hl_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t cr_irtx_head_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_irtx_head_hl_inv : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_irtx_tail_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_irtx_tail_hl_inv : 1; /* [ 11], r/w, 0x0 */ - uint32_t cr_irtx_frm_en : 1; /* [ 12], r/w, 0x0 */ - uint32_t cr_irtx_frm_cont_en : 1; /* [ 13], r/w, 0x0 */ - uint32_t cr_irtx_frm_frame_size : 2; /* [15:14], r/w, 0x0 */ - uint32_t cr_irtx_data_num : 7; /* [22:16], r/w, 0x1f */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_config; - - /* 0x4 : irtx_int_sts */ - union { - struct { - uint32_t irtx_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t irtx_frdy_int : 1; /* [ 1], r, 0x1 */ - uint32_t irtx_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_irtx_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_irtx_frdy_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_irtx_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_irtx_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ - uint32_t cr_irtx_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_irtx_frdy_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_irtx_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_int_sts; - - /* 0x8 reserved */ - uint8_t RESERVED0x8[8]; - - /* 0x10 : irtx_pulse_width */ - union { - struct { - uint32_t cr_irtx_pw_unit : 12; /* [11: 0], r/w, 0x464 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t cr_irtx_mod_ph0_w : 8; /* [23:16], r/w, 0x11 */ - uint32_t cr_irtx_mod_ph1_w : 8; /* [31:24], r/w, 0x22 */ - } BF; - uint32_t WORD; - } irtx_pulse_width; - - /* 0x14 : irtx_pw_0 */ - union { - struct { - uint32_t cr_irtx_logic0_ph0_w : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t cr_irtx_logic0_ph1_w : 8; /* [15: 8], r/w, 0x0 */ - uint32_t cr_irtx_logic1_ph0_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_irtx_logic1_ph1_w : 8; /* [31:24], r/w, 0x2 */ - } BF; - uint32_t WORD; - } irtx_pw_0; - - /* 0x18 : irtx_pw_1 */ - union { - struct { - uint32_t cr_irtx_head_ph0_w : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_irtx_head_ph1_w : 8; /* [15: 8], r/w, 0x7 */ - uint32_t cr_irtx_tail_ph0_w : 8; /* [23:16], r/w, 0x0 */ - uint32_t cr_irtx_tail_ph1_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } irtx_pw_1; - - /* 0x1c reserved */ - uint8_t RESERVED0x1c[36]; - - /* 0x40 : irrx_config */ - union { - struct { - uint32_t cr_irrx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_irrx_in_inv : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_irrx_mode : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t cr_irrx_deg_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t cr_irrx_deg_cnt : 4; /* [11: 8], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irrx_config; - - /* 0x44 : irrx_int_sts */ - union { - struct { - uint32_t irrx_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t irrx_frdy_int : 1; /* [ 1], r, 0x0 */ - uint32_t irrx_fer_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t cr_irrx_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_irrx_frdy_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_irrx_fer_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t cr_irrx_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t reserved_19_23 : 5; /* [23:19], rsvd, 0x0 */ - uint32_t cr_irrx_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_irrx_frdy_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_irrx_fer_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irrx_int_sts; - - /* 0x48 : irrx_pw_config */ - union { - struct { - uint32_t cr_irrx_data_th : 16; /* [15: 0], r/w, 0xd47 */ - uint32_t cr_irrx_end_th : 16; /* [31:16], r/w, 0x2327 */ - } BF; - uint32_t WORD; - } irrx_pw_config; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : irrx_data_count */ - union { - struct { - uint32_t sts_irrx_data_cnt : 7; /* [ 6: 0], r, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irrx_data_count; - - /* 0x54 : irrx_data_word0 */ - union { - struct { - uint32_t sts_irrx_data_word0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } irrx_data_word0; - - /* 0x58 : irrx_data_word1 */ - union { - struct { - uint32_t sts_irrx_data_word1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } irrx_data_word1; - - /* 0x5c reserved */ - uint8_t RESERVED0x5c[36]; - - /* 0x80 : irtx_fifo_config_0 */ - union { - struct { - uint32_t irtx_dma_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t rsvd_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_fifo_config_0; - - /* 0x84 : irtx_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 3; /* [ 2: 0], r, 0x4 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 7; /* [14: 8], r, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t tx_fifo_th : 2; /* [17:16], r/w, 0x0 */ - uint32_t reserved_18_23 : 6; /* [23:18], rsvd, 0x0 */ - uint32_t rx_fifo_th : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } irtx_fifo_config_1; - - /* 0x88 : ir_fifo_wdata */ - union { - struct { - uint32_t tx_fifo_wdata : 32; /* [31: 0], w, 0x0 */ - } BF; - uint32_t WORD; - } ir_fifo_wdata; - - /* 0x8C : ir_fifo_rdata */ - union { - struct { - uint32_t rx_fifo_rdata : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } ir_fifo_rdata; -}; - -typedef volatile struct ir_reg ir_reg_t; - -#endif /* __IR_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/iso11898_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/iso11898_reg.h deleted file mode 100644 index 96b9e9dcf2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/iso11898_reg.h +++ /dev/null @@ -1,807 +0,0 @@ -/** - ****************************************************************************** - * @file iso11898_reg.h - * @version V1.0 - * @date 2020-12-29 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __ISO11898_REG_H__ -#define __ISO11898_REG_H__ - -#include "bl808.h" - -/* 0x0 : op mode:rw reset mode:rw */ -#define ISO11898_MODE_OFFSET (0x0) -#define ISO11898_RESET_REQUEST ISO11898_RESET_REQUEST -#define ISO11898_RESET_REQUEST_POS (0U) -#define ISO11898_RESET_REQUEST_LEN (1U) -#define ISO11898_RESET_REQUEST_MSK (((1U << ISO11898_RESET_REQUEST_LEN) - 1) << ISO11898_RESET_REQUEST_POS) -#define ISO11898_RESET_REQUEST_UMSK (~(((1U << ISO11898_RESET_REQUEST_LEN) - 1) << ISO11898_RESET_REQUEST_POS)) -#define ISO11898_LISTEN_ONLY ISO11898_LISTEN_ONLY -#define ISO11898_LISTEN_ONLY_POS (1U) -#define ISO11898_LISTEN_ONLY_LEN (1U) -#define ISO11898_LISTEN_ONLY_MSK (((1U << ISO11898_LISTEN_ONLY_LEN) - 1) << ISO11898_LISTEN_ONLY_POS) -#define ISO11898_LISTEN_ONLY_UMSK (~(((1U << ISO11898_LISTEN_ONLY_LEN) - 1) << ISO11898_LISTEN_ONLY_POS)) -#define ISO11898_SELT_TEST ISO11898_SELT_TEST -#define ISO11898_SELT_TEST_POS (2U) -#define ISO11898_SELT_TEST_LEN (1U) -#define ISO11898_SELT_TEST_MSK (((1U << ISO11898_SELT_TEST_LEN) - 1) << ISO11898_SELT_TEST_POS) -#define ISO11898_SELT_TEST_UMSK (~(((1U << ISO11898_SELT_TEST_LEN) - 1) << ISO11898_SELT_TEST_POS)) -#define ISO11898_ACCEPTANCE_FILTER ISO11898_ACCEPTANCE_FILTER -#define ISO11898_ACCEPTANCE_FILTER_POS (3U) -#define ISO11898_ACCEPTANCE_FILTER_LEN (1U) -#define ISO11898_ACCEPTANCE_FILTER_MSK (((1U << ISO11898_ACCEPTANCE_FILTER_LEN) - 1) << ISO11898_ACCEPTANCE_FILTER_POS) -#define ISO11898_ACCEPTANCE_FILTER_UMSK (~(((1U << ISO11898_ACCEPTANCE_FILTER_LEN) - 1) << ISO11898_ACCEPTANCE_FILTER_POS)) - -/* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ -#define ISO11898_COMMAND_OFFSET (0x4) -#define ISO11898_TRANSMIT_REQUEST ISO11898_TRANSMIT_REQUEST -#define ISO11898_TRANSMIT_REQUEST_POS (0U) -#define ISO11898_TRANSMIT_REQUEST_LEN (1U) -#define ISO11898_TRANSMIT_REQUEST_MSK (((1U << ISO11898_TRANSMIT_REQUEST_LEN) - 1) << ISO11898_TRANSMIT_REQUEST_POS) -#define ISO11898_TRANSMIT_REQUEST_UMSK (~(((1U << ISO11898_TRANSMIT_REQUEST_LEN) - 1) << ISO11898_TRANSMIT_REQUEST_POS)) -#define ISO11898_ABORT_TRANSMISSION ISO11898_ABORT_TRANSMISSION -#define ISO11898_ABORT_TRANSMISSION_POS (1U) -#define ISO11898_ABORT_TRANSMISSION_LEN (1U) -#define ISO11898_ABORT_TRANSMISSION_MSK (((1U << ISO11898_ABORT_TRANSMISSION_LEN) - 1) << ISO11898_ABORT_TRANSMISSION_POS) -#define ISO11898_ABORT_TRANSMISSION_UMSK (~(((1U << ISO11898_ABORT_TRANSMISSION_LEN) - 1) << ISO11898_ABORT_TRANSMISSION_POS)) -#define ISO11898_RELEASE_RECEIVE_BUFFER ISO11898_RELEASE_RECEIVE_BUFFER -#define ISO11898_RELEASE_RECEIVE_BUFFER_POS (2U) -#define ISO11898_RELEASE_RECEIVE_BUFFER_LEN (1U) -#define ISO11898_RELEASE_RECEIVE_BUFFER_MSK (((1U << ISO11898_RELEASE_RECEIVE_BUFFER_LEN) - 1) << ISO11898_RELEASE_RECEIVE_BUFFER_POS) -#define ISO11898_RELEASE_RECEIVE_BUFFER_UMSK (~(((1U << ISO11898_RELEASE_RECEIVE_BUFFER_LEN) - 1) << ISO11898_RELEASE_RECEIVE_BUFFER_POS)) -#define ISO11898_CLEAR_DATA_OVERRUN ISO11898_CLEAR_DATA_OVERRUN -#define ISO11898_CLEAR_DATA_OVERRUN_POS (3U) -#define ISO11898_CLEAR_DATA_OVERRUN_LEN (1U) -#define ISO11898_CLEAR_DATA_OVERRUN_MSK (((1U << ISO11898_CLEAR_DATA_OVERRUN_LEN) - 1) << ISO11898_CLEAR_DATA_OVERRUN_POS) -#define ISO11898_CLEAR_DATA_OVERRUN_UMSK (~(((1U << ISO11898_CLEAR_DATA_OVERRUN_LEN) - 1) << ISO11898_CLEAR_DATA_OVERRUN_POS)) -#define ISO11898_SELF_REQUEST ISO11898_SELF_REQUEST -#define ISO11898_SELF_REQUEST_POS (4U) -#define ISO11898_SELF_REQUEST_LEN (1U) -#define ISO11898_SELF_REQUEST_MSK (((1U << ISO11898_SELF_REQUEST_LEN) - 1) << ISO11898_SELF_REQUEST_POS) -#define ISO11898_SELF_REQUEST_UMSK (~(((1U << ISO11898_SELF_REQUEST_LEN) - 1) << ISO11898_SELF_REQUEST_POS)) - -/* 0x8 : op mode:r reset mode:r */ -#define ISO11898_STATUS_OFFSET (0x8) -#define ISO11898_RECEIVE_BUFFER_STS ISO11898_RECEIVE_BUFFER_STS -#define ISO11898_RECEIVE_BUFFER_STS_POS (0U) -#define ISO11898_RECEIVE_BUFFER_STS_LEN (1U) -#define ISO11898_RECEIVE_BUFFER_STS_MSK (((1U << ISO11898_RECEIVE_BUFFER_STS_LEN) - 1) << ISO11898_RECEIVE_BUFFER_STS_POS) -#define ISO11898_RECEIVE_BUFFER_STS_UMSK (~(((1U << ISO11898_RECEIVE_BUFFER_STS_LEN) - 1) << ISO11898_RECEIVE_BUFFER_STS_POS)) -#define ISO11898_DATA_OVERRUN_STS ISO11898_DATA_OVERRUN_STS -#define ISO11898_DATA_OVERRUN_STS_POS (1U) -#define ISO11898_DATA_OVERRUN_STS_LEN (1U) -#define ISO11898_DATA_OVERRUN_STS_MSK (((1U << ISO11898_DATA_OVERRUN_STS_LEN) - 1) << ISO11898_DATA_OVERRUN_STS_POS) -#define ISO11898_DATA_OVERRUN_STS_UMSK (~(((1U << ISO11898_DATA_OVERRUN_STS_LEN) - 1) << ISO11898_DATA_OVERRUN_STS_POS)) -#define ISO11898_TRANSMIT_BUFFER_STS ISO11898_TRANSMIT_BUFFER_STS -#define ISO11898_TRANSMIT_BUFFER_STS_POS (2U) -#define ISO11898_TRANSMIT_BUFFER_STS_LEN (1U) -#define ISO11898_TRANSMIT_BUFFER_STS_MSK (((1U << ISO11898_TRANSMIT_BUFFER_STS_LEN) - 1) << ISO11898_TRANSMIT_BUFFER_STS_POS) -#define ISO11898_TRANSMIT_BUFFER_STS_UMSK (~(((1U << ISO11898_TRANSMIT_BUFFER_STS_LEN) - 1) << ISO11898_TRANSMIT_BUFFER_STS_POS)) -#define ISO11898_TRANSMIT_COMPLETE_STS ISO11898_TRANSMIT_COMPLETE_STS -#define ISO11898_TRANSMIT_COMPLETE_STS_POS (3U) -#define ISO11898_TRANSMIT_COMPLETE_STS_LEN (1U) -#define ISO11898_TRANSMIT_COMPLETE_STS_MSK (((1U << ISO11898_TRANSMIT_COMPLETE_STS_LEN) - 1) << ISO11898_TRANSMIT_COMPLETE_STS_POS) -#define ISO11898_TRANSMIT_COMPLETE_STS_UMSK (~(((1U << ISO11898_TRANSMIT_COMPLETE_STS_LEN) - 1) << ISO11898_TRANSMIT_COMPLETE_STS_POS)) -#define ISO11898_RECEIVE_STS ISO11898_RECEIVE_STS -#define ISO11898_RECEIVE_STS_POS (4U) -#define ISO11898_RECEIVE_STS_LEN (1U) -#define ISO11898_RECEIVE_STS_MSK (((1U << ISO11898_RECEIVE_STS_LEN) - 1) << ISO11898_RECEIVE_STS_POS) -#define ISO11898_RECEIVE_STS_UMSK (~(((1U << ISO11898_RECEIVE_STS_LEN) - 1) << ISO11898_RECEIVE_STS_POS)) -#define ISO11898_TRANSMIT_STS ISO11898_TRANSMIT_STS -#define ISO11898_TRANSMIT_STS_POS (5U) -#define ISO11898_TRANSMIT_STS_LEN (1U) -#define ISO11898_TRANSMIT_STS_MSK (((1U << ISO11898_TRANSMIT_STS_LEN) - 1) << ISO11898_TRANSMIT_STS_POS) -#define ISO11898_TRANSMIT_STS_UMSK (~(((1U << ISO11898_TRANSMIT_STS_LEN) - 1) << ISO11898_TRANSMIT_STS_POS)) -#define ISO11898_ERROR_STS ISO11898_ERROR_STS -#define ISO11898_ERROR_STS_POS (6U) -#define ISO11898_ERROR_STS_LEN (1U) -#define ISO11898_ERROR_STS_MSK (((1U << ISO11898_ERROR_STS_LEN) - 1) << ISO11898_ERROR_STS_POS) -#define ISO11898_ERROR_STS_UMSK (~(((1U << ISO11898_ERROR_STS_LEN) - 1) << ISO11898_ERROR_STS_POS)) -#define ISO11898_BUS_STS ISO11898_BUS_STS -#define ISO11898_BUS_STS_POS (7U) -#define ISO11898_BUS_STS_LEN (1U) -#define ISO11898_BUS_STS_MSK (((1U << ISO11898_BUS_STS_LEN) - 1) << ISO11898_BUS_STS_POS) -#define ISO11898_BUS_STS_UMSK (~(((1U << ISO11898_BUS_STS_LEN) - 1) << ISO11898_BUS_STS_POS)) - -/* 0xc : op mode:r reset mode:r when be read,all bits are reseted and iso11898_int disappear */ -#define ISO11898_INTERRUPT_OFFSET (0xc) -#define ISO11898_RECEIVE_INT ISO11898_RECEIVE_INT -#define ISO11898_RECEIVE_INT_POS (0U) -#define ISO11898_RECEIVE_INT_LEN (1U) -#define ISO11898_RECEIVE_INT_MSK (((1U << ISO11898_RECEIVE_INT_LEN) - 1) << ISO11898_RECEIVE_INT_POS) -#define ISO11898_RECEIVE_INT_UMSK (~(((1U << ISO11898_RECEIVE_INT_LEN) - 1) << ISO11898_RECEIVE_INT_POS)) -#define ISO11898_TRANSMIT_INT ISO11898_TRANSMIT_INT -#define ISO11898_TRANSMIT_INT_POS (1U) -#define ISO11898_TRANSMIT_INT_LEN (1U) -#define ISO11898_TRANSMIT_INT_MSK (((1U << ISO11898_TRANSMIT_INT_LEN) - 1) << ISO11898_TRANSMIT_INT_POS) -#define ISO11898_TRANSMIT_INT_UMSK (~(((1U << ISO11898_TRANSMIT_INT_LEN) - 1) << ISO11898_TRANSMIT_INT_POS)) -#define ISO11898_ERROR_INT ISO11898_ERROR_INT -#define ISO11898_ERROR_INT_POS (2U) -#define ISO11898_ERROR_INT_LEN (1U) -#define ISO11898_ERROR_INT_MSK (((1U << ISO11898_ERROR_INT_LEN) - 1) << ISO11898_ERROR_INT_POS) -#define ISO11898_ERROR_INT_UMSK (~(((1U << ISO11898_ERROR_INT_LEN) - 1) << ISO11898_ERROR_INT_POS)) -#define ISO11898_DATA_OVERRUN_INT ISO11898_DATA_OVERRUN_INT -#define ISO11898_DATA_OVERRUN_INT_POS (3U) -#define ISO11898_DATA_OVERRUN_INT_LEN (1U) -#define ISO11898_DATA_OVERRUN_INT_MSK (((1U << ISO11898_DATA_OVERRUN_INT_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_POS) -#define ISO11898_DATA_OVERRUN_INT_UMSK (~(((1U << ISO11898_DATA_OVERRUN_INT_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_POS)) -#define ISO11898_ERROR_PASSIVE_INT ISO11898_ERROR_PASSIVE_INT -#define ISO11898_ERROR_PASSIVE_INT_POS (5U) -#define ISO11898_ERROR_PASSIVE_INT_LEN (1U) -#define ISO11898_ERROR_PASSIVE_INT_MSK (((1U << ISO11898_ERROR_PASSIVE_INT_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_POS) -#define ISO11898_ERROR_PASSIVE_INT_UMSK (~(((1U << ISO11898_ERROR_PASSIVE_INT_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_POS)) -#define ISO11898_ARB_LOST_INT ISO11898_ARB_LOST_INT -#define ISO11898_ARB_LOST_INT_POS (6U) -#define ISO11898_ARB_LOST_INT_LEN (1U) -#define ISO11898_ARB_LOST_INT_MSK (((1U << ISO11898_ARB_LOST_INT_LEN) - 1) << ISO11898_ARB_LOST_INT_POS) -#define ISO11898_ARB_LOST_INT_UMSK (~(((1U << ISO11898_ARB_LOST_INT_LEN) - 1) << ISO11898_ARB_LOST_INT_POS)) -#define ISO11898_BUS_ERROR_INT ISO11898_BUS_ERROR_INT -#define ISO11898_BUS_ERROR_INT_POS (7U) -#define ISO11898_BUS_ERROR_INT_LEN (1U) -#define ISO11898_BUS_ERROR_INT_MSK (((1U << ISO11898_BUS_ERROR_INT_LEN) - 1) << ISO11898_BUS_ERROR_INT_POS) -#define ISO11898_BUS_ERROR_INT_UMSK (~(((1U << ISO11898_BUS_ERROR_INT_LEN) - 1) << ISO11898_BUS_ERROR_INT_POS)) - -/* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and iso11898_int disappear */ -#define ISO11898_INTERRUPT_ENABLE_OFFSET (0x10) -#define ISO11898_RECEIVE_INT_EN ISO11898_RECEIVE_INT_EN -#define ISO11898_RECEIVE_INT_EN_POS (0U) -#define ISO11898_RECEIVE_INT_EN_LEN (1U) -#define ISO11898_RECEIVE_INT_EN_MSK (((1U << ISO11898_RECEIVE_INT_EN_LEN) - 1) << ISO11898_RECEIVE_INT_EN_POS) -#define ISO11898_RECEIVE_INT_EN_UMSK (~(((1U << ISO11898_RECEIVE_INT_EN_LEN) - 1) << ISO11898_RECEIVE_INT_EN_POS)) -#define ISO11898_TRANSMIT_INT_EN ISO11898_TRANSMIT_INT_EN -#define ISO11898_TRANSMIT_INT_EN_POS (1U) -#define ISO11898_TRANSMIT_INT_EN_LEN (1U) -#define ISO11898_TRANSMIT_INT_EN_MSK (((1U << ISO11898_TRANSMIT_INT_EN_LEN) - 1) << ISO11898_TRANSMIT_INT_EN_POS) -#define ISO11898_TRANSMIT_INT_EN_UMSK (~(((1U << ISO11898_TRANSMIT_INT_EN_LEN) - 1) << ISO11898_TRANSMIT_INT_EN_POS)) -#define ISO11898_ERROR_INT_EN ISO11898_ERROR_INT_EN -#define ISO11898_ERROR_INT_EN_POS (2U) -#define ISO11898_ERROR_INT_EN_LEN (1U) -#define ISO11898_ERROR_INT_EN_MSK (((1U << ISO11898_ERROR_INT_EN_LEN) - 1) << ISO11898_ERROR_INT_EN_POS) -#define ISO11898_ERROR_INT_EN_UMSK (~(((1U << ISO11898_ERROR_INT_EN_LEN) - 1) << ISO11898_ERROR_INT_EN_POS)) -#define ISO11898_DATA_OVERRUN_INT_EN ISO11898_DATA_OVERRUN_INT_EN -#define ISO11898_DATA_OVERRUN_INT_EN_POS (3U) -#define ISO11898_DATA_OVERRUN_INT_EN_LEN (1U) -#define ISO11898_DATA_OVERRUN_INT_EN_MSK (((1U << ISO11898_DATA_OVERRUN_INT_EN_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_EN_POS) -#define ISO11898_DATA_OVERRUN_INT_EN_UMSK (~(((1U << ISO11898_DATA_OVERRUN_INT_EN_LEN) - 1) << ISO11898_DATA_OVERRUN_INT_EN_POS)) -#define ISO11898_ERROR_PASSIVE_INT_EN ISO11898_ERROR_PASSIVE_INT_EN -#define ISO11898_ERROR_PASSIVE_INT_EN_POS (5U) -#define ISO11898_ERROR_PASSIVE_INT_EN_LEN (1U) -#define ISO11898_ERROR_PASSIVE_INT_EN_MSK (((1U << ISO11898_ERROR_PASSIVE_INT_EN_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_EN_POS) -#define ISO11898_ERROR_PASSIVE_INT_EN_UMSK (~(((1U << ISO11898_ERROR_PASSIVE_INT_EN_LEN) - 1) << ISO11898_ERROR_PASSIVE_INT_EN_POS)) -#define ISO11898_ARB_LOST_INT_EN ISO11898_ARB_LOST_INT_EN -#define ISO11898_ARB_LOST_INT_EN_POS (6U) -#define ISO11898_ARB_LOST_INT_EN_LEN (1U) -#define ISO11898_ARB_LOST_INT_EN_MSK (((1U << ISO11898_ARB_LOST_INT_EN_LEN) - 1) << ISO11898_ARB_LOST_INT_EN_POS) -#define ISO11898_ARB_LOST_INT_EN_UMSK (~(((1U << ISO11898_ARB_LOST_INT_EN_LEN) - 1) << ISO11898_ARB_LOST_INT_EN_POS)) -#define ISO11898_BUS_ERROR_INT_EN ISO11898_BUS_ERROR_INT_EN -#define ISO11898_BUS_ERROR_INT_EN_POS (7U) -#define ISO11898_BUS_ERROR_INT_EN_LEN (1U) -#define ISO11898_BUS_ERROR_INT_EN_MSK (((1U << ISO11898_BUS_ERROR_INT_EN_LEN) - 1) << ISO11898_BUS_ERROR_INT_EN_POS) -#define ISO11898_BUS_ERROR_INT_EN_UMSK (~(((1U << ISO11898_BUS_ERROR_INT_EN_LEN) - 1) << ISO11898_BUS_ERROR_INT_EN_POS)) - -/* 0x18 : op mode:r reset mode:rw */ -#define ISO11898_BUS_TIMING_0_OFFSET (0x18) -#define ISO11898_BAUD_RATE_PRESCALER ISO11898_BAUD_RATE_PRESCALER -#define ISO11898_BAUD_RATE_PRESCALER_POS (0U) -#define ISO11898_BAUD_RATE_PRESCALER_LEN (6U) -#define ISO11898_BAUD_RATE_PRESCALER_MSK (((1U << ISO11898_BAUD_RATE_PRESCALER_LEN) - 1) << ISO11898_BAUD_RATE_PRESCALER_POS) -#define ISO11898_BAUD_RATE_PRESCALER_UMSK (~(((1U << ISO11898_BAUD_RATE_PRESCALER_LEN) - 1) << ISO11898_BAUD_RATE_PRESCALER_POS)) -#define ISO11898_SYNC_JUMP_WIDTH ISO11898_SYNC_JUMP_WIDTH -#define ISO11898_SYNC_JUMP_WIDTH_POS (6U) -#define ISO11898_SYNC_JUMP_WIDTH_LEN (2U) -#define ISO11898_SYNC_JUMP_WIDTH_MSK (((1U << ISO11898_SYNC_JUMP_WIDTH_LEN) - 1) << ISO11898_SYNC_JUMP_WIDTH_POS) -#define ISO11898_SYNC_JUMP_WIDTH_UMSK (~(((1U << ISO11898_SYNC_JUMP_WIDTH_LEN) - 1) << ISO11898_SYNC_JUMP_WIDTH_POS)) - -/* 0x1c : op mode:r reset mode:rw */ -#define ISO11898_BUS_TIMING_1_OFFSET (0x1c) -#define ISO11898_TIME_SEGMENT_1 ISO11898_TIME_SEGMENT_1 -#define ISO11898_TIME_SEGMENT_1_POS (0U) -#define ISO11898_TIME_SEGMENT_1_LEN (4U) -#define ISO11898_TIME_SEGMENT_1_MSK (((1U << ISO11898_TIME_SEGMENT_1_LEN) - 1) << ISO11898_TIME_SEGMENT_1_POS) -#define ISO11898_TIME_SEGMENT_1_UMSK (~(((1U << ISO11898_TIME_SEGMENT_1_LEN) - 1) << ISO11898_TIME_SEGMENT_1_POS)) -#define ISO11898_TIME_SEGMENT_2 ISO11898_TIME_SEGMENT_2 -#define ISO11898_TIME_SEGMENT_2_POS (4U) -#define ISO11898_TIME_SEGMENT_2_LEN (3U) -#define ISO11898_TIME_SEGMENT_2_MSK (((1U << ISO11898_TIME_SEGMENT_2_LEN) - 1) << ISO11898_TIME_SEGMENT_2_POS) -#define ISO11898_TIME_SEGMENT_2_UMSK (~(((1U << ISO11898_TIME_SEGMENT_2_LEN) - 1) << ISO11898_TIME_SEGMENT_2_POS)) -#define ISO11898_SAMPLING ISO11898_SAMPLING -#define ISO11898_SAMPLING_POS (7U) -#define ISO11898_SAMPLING_LEN (1U) -#define ISO11898_SAMPLING_MSK (((1U << ISO11898_SAMPLING_LEN) - 1) << ISO11898_SAMPLING_POS) -#define ISO11898_SAMPLING_UMSK (~(((1U << ISO11898_SAMPLING_LEN) - 1) << ISO11898_SAMPLING_POS)) - -/* 0x2c : op mode:r reset mode:r */ -#define ISO11898_ARB_LOST_CAPTURE_OFFSET (0x2c) -#define ISO11898_ALC4_0 ISO11898_ALC4_0 -#define ISO11898_ALC4_0_POS (0U) -#define ISO11898_ALC4_0_LEN (5U) -#define ISO11898_ALC4_0_MSK (((1U << ISO11898_ALC4_0_LEN) - 1) << ISO11898_ALC4_0_POS) -#define ISO11898_ALC4_0_UMSK (~(((1U << ISO11898_ALC4_0_LEN) - 1) << ISO11898_ALC4_0_POS)) - -/* 0x30 : op mode:r reset mode:r */ -#define ISO11898_ERROR_CODE_CAPTURE_OFFSET (0x30) -#define ISO11898_SEGMENT4_0 ISO11898_SEGMENT4_0 -#define ISO11898_SEGMENT4_0_POS (0U) -#define ISO11898_SEGMENT4_0_LEN (5U) -#define ISO11898_SEGMENT4_0_MSK (((1U << ISO11898_SEGMENT4_0_LEN) - 1) << ISO11898_SEGMENT4_0_POS) -#define ISO11898_SEGMENT4_0_UMSK (~(((1U << ISO11898_SEGMENT4_0_LEN) - 1) << ISO11898_SEGMENT4_0_POS)) -#define ISO11898_DIR ISO11898_DIR -#define ISO11898_DIR_POS (5U) -#define ISO11898_DIR_LEN (1U) -#define ISO11898_DIR_MSK (((1U << ISO11898_DIR_LEN) - 1) << ISO11898_DIR_POS) -#define ISO11898_DIR_UMSK (~(((1U << ISO11898_DIR_LEN) - 1) << ISO11898_DIR_POS)) -#define ISO11898_ERR_CODE ISO11898_ERR_CODE -#define ISO11898_ERR_CODE_POS (6U) -#define ISO11898_ERR_CODE_LEN (2U) -#define ISO11898_ERR_CODE_MSK (((1U << ISO11898_ERR_CODE_LEN) - 1) << ISO11898_ERR_CODE_POS) -#define ISO11898_ERR_CODE_UMSK (~(((1U << ISO11898_ERR_CODE_LEN) - 1) << ISO11898_ERR_CODE_POS)) - -/* 0x34 : op mode:r reset mode:rw */ -#define ISO11898_ERROR_WARNING_LIMIT_OFFSET (0x34) -#define ISO11898_ERR_WARNING_LIMIT ISO11898_ERR_WARNING_LIMIT -#define ISO11898_ERR_WARNING_LIMIT_POS (0U) -#define ISO11898_ERR_WARNING_LIMIT_LEN (8U) -#define ISO11898_ERR_WARNING_LIMIT_MSK (((1U << ISO11898_ERR_WARNING_LIMIT_LEN) - 1) << ISO11898_ERR_WARNING_LIMIT_POS) -#define ISO11898_ERR_WARNING_LIMIT_UMSK (~(((1U << ISO11898_ERR_WARNING_LIMIT_LEN) - 1) << ISO11898_ERR_WARNING_LIMIT_POS)) - -/* 0x38 : op mode:r reset mode:rw */ -#define ISO11898_RX_ERR_COUNT_OFFSET (0x38) -#define ISO11898_RX_ERR_CNT ISO11898_RX_ERR_CNT -#define ISO11898_RX_ERR_CNT_POS (0U) -#define ISO11898_RX_ERR_CNT_LEN (8U) -#define ISO11898_RX_ERR_CNT_MSK (((1U << ISO11898_RX_ERR_CNT_LEN) - 1) << ISO11898_RX_ERR_CNT_POS) -#define ISO11898_RX_ERR_CNT_UMSK (~(((1U << ISO11898_RX_ERR_CNT_LEN) - 1) << ISO11898_RX_ERR_CNT_POS)) - -/* 0x3c : op mode:r reset mode:rw */ -#define ISO11898_TX_ERR_COUNT_OFFSET (0x3c) -#define ISO11898_TX_ERR_CNT ISO11898_TX_ERR_CNT -#define ISO11898_TX_ERR_CNT_POS (0U) -#define ISO11898_TX_ERR_CNT_LEN (8U) -#define ISO11898_TX_ERR_CNT_MSK (((1U << ISO11898_TX_ERR_CNT_LEN) - 1) << ISO11898_TX_ERR_CNT_POS) -#define ISO11898_TX_ERR_CNT_UMSK (~(((1U << ISO11898_TX_ERR_CNT_LEN) - 1) << ISO11898_TX_ERR_CNT_POS)) - -/* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_OFFSET (0x40) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0 -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS (0U) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN (8U) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_MSK (((1U << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS) -#define ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_UMSK (~(((1U << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_LEN) - 1) << ISO11898_TXRX_FRM_INFO_OR_ACCEPTANCE_CODE0_POS)) - -/* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_OFFSET (0x44) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1 ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1 -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS (0U) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN (8U) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_MSK (((1U << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS) -#define ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_UMSK (~(((1U << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_LEN) - 1) << ISO11898_TXRX_ID1_OR_ACCEPTANCE_CODE1_POS)) - -/* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_OFFSET (0x48) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2 ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2 -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS (0U) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN (8U) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_MSK (((1U << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS) -#define ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_UMSK (~(((1U << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_LEN) - 1) << ISO11898_TXRX_ID2_OR_ACCEPTANCE_CODE2_POS)) - -/* 0x74 : op mode:r reset mode:r */ -#define ISO11898_RX_MESSAGE_COUNT_OFFSET (0x74) -#define ISO11898_RX_MESSAGE_CNT ISO11898_RX_MESSAGE_CNT -#define ISO11898_RX_MESSAGE_CNT_POS (0U) -#define ISO11898_RX_MESSAGE_CNT_LEN (5U) -#define ISO11898_RX_MESSAGE_CNT_MSK (((1U << ISO11898_RX_MESSAGE_CNT_LEN) - 1) << ISO11898_RX_MESSAGE_CNT_POS) -#define ISO11898_RX_MESSAGE_CNT_UMSK (~(((1U << ISO11898_RX_MESSAGE_CNT_LEN) - 1) << ISO11898_RX_MESSAGE_CNT_POS)) - -/* 0x7c : op mode:rw reset mode:rw iso11898_mode and cbp can be write in reset mode only */ -#define ISO11898_CLOCK_DIVIDER_OFFSET (0x7c) -#define ISO11898_CD ISO11898_CD -#define ISO11898_CD_POS (0U) -#define ISO11898_CD_LEN (3U) -#define ISO11898_CD_MSK (((1U << ISO11898_CD_LEN) - 1) << ISO11898_CD_POS) -#define ISO11898_CD_UMSK (~(((1U << ISO11898_CD_LEN) - 1) << ISO11898_CD_POS)) -#define ISO11898_CLOCKOFF ISO11898_CLOCKOFF -#define ISO11898_CLOCKOFF_POS (3U) -#define ISO11898_CLOCKOFF_LEN (1U) -#define ISO11898_CLOCKOFF_MSK (((1U << ISO11898_CLOCKOFF_LEN) - 1) << ISO11898_CLOCKOFF_POS) -#define ISO11898_CLOCKOFF_UMSK (~(((1U << ISO11898_CLOCKOFF_LEN) - 1) << ISO11898_CLOCKOFF_POS)) -#define ISO11898_READONLY ISO11898_READONLY -#define ISO11898_READONLY_POS (4U) -#define ISO11898_READONLY_LEN (1U) -#define ISO11898_READONLY_MSK (((1U << ISO11898_READONLY_LEN) - 1) << ISO11898_READONLY_POS) -#define ISO11898_READONLY_UMSK (~(((1U << ISO11898_READONLY_LEN) - 1) << ISO11898_READONLY_POS)) -#define ISO11898_RXINTEN ISO11898_RXINTEN -#define ISO11898_RXINTEN_POS (5U) -#define ISO11898_RXINTEN_LEN (1U) -#define ISO11898_RXINTEN_MSK (((1U << ISO11898_RXINTEN_LEN) - 1) << ISO11898_RXINTEN_POS) -#define ISO11898_RXINTEN_UMSK (~(((1U << ISO11898_RXINTEN_LEN) - 1) << ISO11898_RXINTEN_POS)) -#define ISO11898_CBP ISO11898_CBP -#define ISO11898_CBP_POS (6U) -#define ISO11898_CBP_LEN (1U) -#define ISO11898_CBP_MSK (((1U << ISO11898_CBP_LEN) - 1) << ISO11898_CBP_POS) -#define ISO11898_CBP_UMSK (~(((1U << ISO11898_CBP_LEN) - 1) << ISO11898_CBP_POS)) -#define ISO11898_MODE ISO11898_MODE -#define ISO11898_MODE_POS (7U) -#define ISO11898_MODE_LEN (1U) -#define ISO11898_MODE_MSK (((1U << ISO11898_MODE_LEN) - 1) << ISO11898_MODE_POS) -#define ISO11898_MODE_UMSK (~(((1U << ISO11898_MODE_LEN) - 1) << ISO11898_MODE_POS)) - -/* 0x40 : Frame information */ -#define ISO11898_INFORMATION_OFFSET (0x40) -#define ISO11898_INF_DLC ISO11898_INF_DLC -#define ISO11898_INF_DLC_POS (0U) -#define ISO11898_INF_DLC_LEN (4U) -#define ISO11898_INF_DLC_MSK (((1U << ISO11898_INF_DLC_LEN) - 1) << ISO11898_INF_DLC_POS) -#define ISO11898_INF_DLC_UMSK (~(((1U << ISO11898_INF_DLC_LEN) - 1) << ISO11898_INF_DLC_POS)) -#define ISO11898_INF_RTR ISO11898_INF_RTR -#define ISO11898_INF_RTR_POS (6U) -#define ISO11898_INF_RTR_LEN (1U) -#define ISO11898_INF_RTR_MSK (((1U << ISO11898_INF_RTR_LEN) - 1) << ISO11898_INF_RTR_POS) -#define ISO11898_INF_RTR_UMSK (~(((1U << ISO11898_INF_RTR_LEN) - 1) << ISO11898_INF_RTR_POS)) -#define ISO11898_INF_FF ISO11898_INF_FF -#define ISO11898_INF_FF_POS (7U) -#define ISO11898_INF_FF_LEN (1U) -#define ISO11898_INF_FF_MSK (((1U << ISO11898_INF_FF_LEN) - 1) << ISO11898_INF_FF_POS) -#define ISO11898_INF_FF_UMSK (~(((1U << ISO11898_INF_FF_LEN) - 1) << ISO11898_INF_FF_POS)) - -/* 0x44 : Identifier 1, ID28~21 */ -#define ISO11898_IDENTIFIER_1_OFFSET (0x44) - -/* 0x48 : Identifier 2, ID20~13, SFF Only use ID20~18 */ -#define ISO11898_IDENTIFIER_2_OFFSET (0x48) - -/* 0x4C : Identifier 3, ID12~5, only for EFF */ -#define ISO11898_IDENTIFIER_3_OFFSET (0x4C) - -/* 0x50 : Identifier 4, ID4~0, only for EFF */ -#define ISO11898_IDENTIFIER_4_OFFSET (0x50) - -/* 0x4C : Standard Format Data 1 buffer */ -#define ISO11898_SFF_DATA_1_OFFSET (0x4C) - -/* 0x50 : Standard Format Data 2 buffer */ -#define ISO11898_SFF_DATA_2_OFFSET (0x50) - -/* 0x54 : Standard Format Data 3 buffer */ -#define ISO11898_SFF_DATA_3_OFFSET (0x54) - -/* 0x58 : Standard Format Data 4 buffer */ -#define ISO11898_SFF_DATA_4_OFFSET (0x58) - -/* 0x5C : Standard Format Data 5 buffer */ -#define ISO11898_SFF_DATA_5_OFFSET (0x5C) - -/* 0x60 : Standard Format Data 6 buffer */ -#define ISO11898_SFF_DATA_6_OFFSET (0x60) - -/* 0x64 : Standard Format Data 7 buffer */ -#define ISO11898_SFF_DATA_7_OFFSET (0x64) - -/* 0x68 : Standard Format Data 8 buffer */ -#define ISO11898_SFF_DATA_8_OFFSET (0x68) - -/* 0x54 : Extended Format Data 1 buffer */ -#define ISO11898_EFF_DATA_1_OFFSET (0x54) - -/* 0x58 : Extended Format Data 2 buffer */ -#define ISO11898_EFF_DATA_2_OFFSET (0x58) - -/* 0x5C : Extended Format Data 3 buffer */ -#define ISO11898_EFF_DATA_3_OFFSET (0x5C) - -/* 0x60 : Extended Format Data 4 buffer */ -#define ISO11898_EFF_DATA_4_OFFSET (0x60) - -/* 0x64 : Extended Format Data 5 buffer */ -#define ISO11898_EFF_DATA_5_OFFSET (0x64) - -/* 0x68 : Extended Format Data 6 buffer */ -#define ISO11898_EFF_DATA_6_OFFSET (0x68) - -/* 0x6C : Extended Format Data 7 buffer */ -#define ISO11898_EFF_DATA_7_OFFSET (0x6C) - -/* 0x70 : Extended Format Data 8 buffer */ -#define ISO11898_EFF_DATA_8_OFFSET (0x70) - -/* 0x70 : Extended Format Data 8 buffer */ -#define ISO11898_EFF_DATA_8_OFFSET (0x70) - -/* 0x40 : Filter Acceptance 0 */ -#define ISO11898_FILTER_ACCEPTANCE_0_OFFSET (0x40) - -/* 0x44 : Filter Acceptance 1 */ -#define ISO11898_FILTER_ACCEPTANCE_1_OFFSET (0x44) - -/* 0x48 : Filter Acceptance 2 */ -#define ISO11898_FILTER_ACCEPTANCE_2_OFFSET (0x48) - -/* 0x4C : Filter Acceptance 3 */ -#define ISO11898_FILTER_ACCEPTANCE_3_OFFSET (0x4C) - -/* 0x50 : Filter Mask 0 */ -#define ISO11898_FILTER_Mask_0_OFFSET (0x50) - -/* 0x54 : Filter Mask 1 */ -#define ISO11898_FILTER_Mask_1_OFFSET (0x54) - -/* 0x58 : Filter Mask 2 */ -#define ISO11898_FILTER_Mask_2_OFFSET (0x58) - -/* 0x5C : Filter Mask 3 */ -#define ISO11898_FILTER_Mask_3_OFFSET (0x5C) - -/* 0x4C : Extended Format, Tx information 5, ID4~0 */ -#define ISO11898_IDENTIFIER_4_OFFSET (0x50) - -struct iso11898_reg { - /* 0x0 : op mode:rw reset mode:rw */ - union { - struct { - uint32_t reset_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t listen_only : 1; /* [ 1], w1c, 0x0 */ - uint32_t selt_test : 1; /* [ 2], w1c, 0x0 */ - uint32_t acceptance_filter : 1; /* [ 3], w1c, 0x0 */ - uint32_t rsvd_7_4 : 4; /* [ 7: 4], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mode; - - /* 0x4 : op mode:w r -> 8'h00 -reset mode:w r -> 8'h00 */ - union { - struct { - uint32_t transmit_request : 1; /* [ 0], w1c, 0x0 */ - uint32_t abort_transmission : 1; /* [ 1], w1c, 0x0 */ - uint32_t release_receive_buffer : 1; /* [ 2], w1c, 0x0 */ - uint32_t clear_data_overrun : 1; /* [ 3], w1c, 0x0 */ - uint32_t self_request : 1; /* [ 4], w1c, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } command; - - /* 0x8 : op mode:r reset mode:r */ - union { - struct { - uint32_t receive_buffer_sts : 1; /* [ 0], r, 0x0 */ - uint32_t data_overrun_sts : 1; /* [ 1], r, 0x0 */ - uint32_t transmit_buffer_sts : 1; /* [ 2], r, 0x0 */ - uint32_t transmit_complete_sts : 1; /* [ 3], r, 0x0 */ - uint32_t receive_sts : 1; /* [ 4], r, 0x0 */ - uint32_t transmit_sts : 1; /* [ 5], r, 0x0 */ - uint32_t error_sts : 1; /* [ 6], r, 0x0 */ - uint32_t bus_sts : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } status; - - /* 0xc : op mode:r reset mode:r when be read,all bits are reseted and iso11898_int disappear */ - union { - struct { - uint32_t receive_int : 1; /* [ 0], r, 0x0 */ - uint32_t transmit_int : 1; /* [ 1], r, 0x0 */ - uint32_t error_int : 1; /* [ 2], r, 0x0 */ - uint32_t data_overrun_int : 1; /* [ 3], r, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int : 1; /* [ 5], r, 0x0 */ - uint32_t arb_lost_int : 1; /* [ 6], r, 0x0 */ - uint32_t bus_error_int : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt; - - /* 0x10 : op mode:rw reset mode:rw when be read,all bits are reseted and iso11898_int disappear */ - union { - struct { - uint32_t receive_int_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t transmit_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t error_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t data_overrun_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rsvd_4 : 1; /* [ 4], rsvd, 0x0 */ - uint32_t error_passive_int_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t arb_lost_int_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t bus_error_int_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } interrupt_enable; - - /* 0x14 reserved */ - uint8_t RESERVED0x14[4]; - - /* 0x18 : op mode:r reset mode:rw */ - union { - struct { - uint32_t baud_rate_prescaler_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t baud_rate_prescaler_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t baud_rate_prescaler_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t baud_rate_prescaler_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t baud_rate_prescaler_4 : 1; /* [ 4], r/w, 0x0 */ - uint32_t baud_rate_prescaler_5 : 1; /* [ 5], r/w, 0x0 */ - uint32_t sync_jump_width_0 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sync_jump_width_1 : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_0; - - /* 0x1c : op mode:r reset mode:rw */ - union { - struct { - uint32_t time_segment_1_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t time_segment_1_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t time_segment_1_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t time_segment_1_3 : 1; /* [ 3], r/w, 0x0 */ - uint32_t time_segment_2_0 : 1; /* [ 4], r/w, 0x0 */ - uint32_t time_segment_2_1 : 1; /* [ 5], r/w, 0x0 */ - uint32_t time_segment_2_2 : 1; /* [ 6], r/w, 0x0 */ - uint32_t sampling : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } bus_timing_1; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[12]; - - /* 0x2c : op mode:r reset mode:r */ - union { - struct { - uint32_t ALC4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t rsvd_7_5 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } arb_lost_capture; - - /* 0x30 : op mode:r reset mode:r */ - union { - struct { - uint32_t segment4_0 : 5; /* [ 4: 0], r, 0x0 */ - uint32_t dir : 1; /* [ 5], r, 0x0 */ - uint32_t err_code : 2; /* [ 7: 6], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_code_capture; - - /* 0x34 : op mode:r reset mode:rw */ - union { - struct { - uint32_t err_warning_limit : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } error_warning_limit; - - /* 0x38 : op mode:r reset mode:rw */ - union { - struct { - uint32_t rx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_err_count; - - /* 0x3c : op mode:r reset mode:rw */ - union { - struct { - uint32_t tx_err_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } tx_err_count; - - /* 0x40 : op mode: w -> tx_frm_info - r -> rx_frm_info -reset mode:rw -> acceptance_code0 */ - union { - struct { - uint32_t txrx_frm_info_or_acceptance_code0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_frm_info_or_acceptance_code0; - - /* 0x44 : op mode:w -> tx_id1 - r -> rx_id1 -reset mode:rw -> acceptance_code1 */ - union { - struct { - uint32_t txrx_id1_or_acceptance_code1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id1_or_acceptance_code1; - - /* 0x48 : op mode:w -> tx_id2 - r -> rx_id2 - reset mode:rw -> acceptance_code2 */ - union { - struct { - uint32_t txrx_id2_or_acceptance_code2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_id2_or_acceptance_code2; - - /* 0x4c : op mode:w -> tx_data1_s or tx_id3 - r -> rx_data1_s or rx_id3 - reset mode:rw -> acceptance_code3 */ - union { - struct { - uint32_t txrx_data1_s_or_txrx_id3_e_or_acceptance_code3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data1_s_or_txrx_id3_e_or_acceptance_code3; - - /* 0x50 : op mode:w -> tx_data2_s or tx_id4 - r -> rx_data2_s or rx_id4 -reset mode:rw -> acceptance_mask0 */ - union { - struct { - uint32_t txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data2_s_or_txrx_id4_e_or_acceptance_mask0; - - /* 0x54 : op mode:w -> tx_data3_s or tx_data1_e - r -> rx_data3_s or rx_data1_e -reset mode:rw -> acceptance_mask1 */ - union { - struct { - uint32_t txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data3_s_or_txrx_data1_e_or_acceptance_mask1; - - /* 0x58 : op mode:w -> tx_data4_s or tx_data2_e - r -> rx_data4_s or rx_data2_e -reset mode:rw -> acceptance_mask2 */ - union { - struct { - uint32_t txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data4_s_or_txrx_data2_e_or_acceptance_mask2; - - /* 0x5c : op mode:w -> tx_data5_s or tx_data3_e - r -> rx_data5_s or rx_data3_e -reset mode:rw -> acceptance_mask3 */ - union { - struct { - uint32_t txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data5_s_or_txrx_data3_e_or_acceptance_mask3; - - /* 0x60 : op mode:w -> tx_data6_s or tx_data4_e - r -> rx_data6_s or rx_data4_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data6_s_or_txrx_data4_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data6_s_or_txrx_data4_e; - - /* 0x64 : op mode:w -> tx_data7_s or tx_data5_e - r -> rx_data7_s or rx_data5_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_s_or_txrx_data5_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_s_or_txrx_data5_e; - - /* 0x68 : op mode:w -> tx_data8_s or tx_data6_e - r -> rx_data8_s or rx_data6_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_s_or_txrx_data6_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_s_or_txrx_data6_e; - - /* 0x6c : op mode:w -> tx_data7_e - r -> rx_data7_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data7_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data7_e; - - /* 0x70 : op mode:w -> tx_data8_e - r -> rx_data8_e -reset mode:r -> 8'H00 */ - union { - struct { - uint32_t txrx_data8_e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } txrx_data8_e; - - /* 0x74 : op mode:r reset mode:r */ - union { - struct { - uint32_t rx_message_cnt : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } rx_message_count; - - /* 0x78 reserved */ - uint8_t RESERVED0x78[4]; - - /* 0x7c : op mode:rw reset mode:rw iso11898_mode and cbp can be write in reset mode only */ - union { - struct { - uint32_t cd : 3; /* [ 2: 0], r/w, 0x0 */ - uint32_t clockoff : 1; /* [ 3], r/w, 0x0 */ - uint32_t readonly : 1; /* [ 4], r, 0x0 */ - uint32_t rxinten : 1; /* [ 5], r/w, 0x0 */ - uint32_t cbp : 1; /* [ 6], r/w, 0x0 */ - uint32_t iso11898_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } clock_divider; -}; - -typedef volatile struct iso11898_reg iso11898_reg_t; - -#endif /* __ISO11898_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/lz4_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/lz4_reg.h deleted file mode 100644 index 9d21f7a184..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/lz4_reg.h +++ /dev/null @@ -1,276 +0,0 @@ -/** - ****************************************************************************** - * @file lz4_reg.h - * @version V1.0 - * @date 2021-06-15 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __LZ4_REG_H__ -#define __LZ4_REG_H__ - -#include "bl808.h" - -/* 0x0 : lz4_config */ -#define LZ4_CONFIG_OFFSET (0x0) -#define LZ4_EN LZ4_EN -#define LZ4_EN_POS (0U) -#define LZ4_EN_LEN (1U) -#define LZ4_EN_MSK (((1U << LZ4_EN_LEN) - 1) << LZ4_EN_POS) -#define LZ4_EN_UMSK (~(((1U << LZ4_EN_LEN) - 1) << LZ4_EN_POS)) -#define LZ4_SUSPEND LZ4_SUSPEND -#define LZ4_SUSPEND_POS (1U) -#define LZ4_SUSPEND_LEN (1U) -#define LZ4_SUSPEND_MSK (((1U << LZ4_SUSPEND_LEN) - 1) << LZ4_SUSPEND_POS) -#define LZ4_SUSPEND_UMSK (~(((1U << LZ4_SUSPEND_LEN) - 1) << LZ4_SUSPEND_POS)) -#define LZ4_CHECKSUM LZ4_CHECKSUM -#define LZ4_CHECKSUM_POS (4U) -#define LZ4_CHECKSUM_LEN (1U) -#define LZ4_CHECKSUM_MSK (((1U << LZ4_CHECKSUM_LEN) - 1) << LZ4_CHECKSUM_POS) -#define LZ4_CHECKSUM_UMSK (~(((1U << LZ4_CHECKSUM_LEN) - 1) << LZ4_CHECKSUM_POS)) - -/* 0x4 : lz4_src_fix */ -#define LZ4_SRC_FIX_OFFSET (0x4) -#define LZ4_SRC_FIX LZ4_SRC_FIX -#define LZ4_SRC_FIX_POS (12U) -#define LZ4_SRC_FIX_LEN (14U) -#define LZ4_SRC_FIX_MSK (((1U << LZ4_SRC_FIX_LEN) - 1) << LZ4_SRC_FIX_POS) -#define LZ4_SRC_FIX_UMSK (~(((1U << LZ4_SRC_FIX_LEN) - 1) << LZ4_SRC_FIX_POS)) - -/* 0x8 : lz4_dst_fix */ -#define LZ4_DST_FIX_OFFSET (0x8) -#define LZ4_DST_FIX LZ4_DST_FIX -#define LZ4_DST_FIX_POS (12U) -#define LZ4_DST_FIX_LEN (14U) -#define LZ4_DST_FIX_MSK (((1U << LZ4_DST_FIX_LEN) - 1) << LZ4_DST_FIX_POS) -#define LZ4_DST_FIX_UMSK (~(((1U << LZ4_DST_FIX_LEN) - 1) << LZ4_DST_FIX_POS)) - -/* 0x10 : lz4_src_start */ -#define LZ4_SRC_START_OFFSET (0x10) -#define LZ4_SRC_START LZ4_SRC_START -#define LZ4_SRC_START_POS (0U) -#define LZ4_SRC_START_LEN (26U) -#define LZ4_SRC_START_MSK (((1U << LZ4_SRC_START_LEN) - 1) << LZ4_SRC_START_POS) -#define LZ4_SRC_START_UMSK (~(((1U << LZ4_SRC_START_LEN) - 1) << LZ4_SRC_START_POS)) -#define LZ4_SRC_BASE LZ4_SRC_BASE -#define LZ4_SRC_BASE_POS (26U) -#define LZ4_SRC_BASE_LEN (6U) -#define LZ4_SRC_BASE_MSK (((1U << LZ4_SRC_BASE_LEN) - 1) << LZ4_SRC_BASE_POS) -#define LZ4_SRC_BASE_UMSK (~(((1U << LZ4_SRC_BASE_LEN) - 1) << LZ4_SRC_BASE_POS)) - -/* 0x14 : lz4_src_end */ -#define LZ4_SRC_END_OFFSET (0x14) -#define LZ4_SRC_END LZ4_SRC_END -#define LZ4_SRC_END_POS (0U) -#define LZ4_SRC_END_LEN (26U) -#define LZ4_SRC_END_MSK (((1U << LZ4_SRC_END_LEN) - 1) << LZ4_SRC_END_POS) -#define LZ4_SRC_END_UMSK (~(((1U << LZ4_SRC_END_LEN) - 1) << LZ4_SRC_END_POS)) - -/* 0x18 : lz4_dst_start */ -#define LZ4_DST_START_OFFSET (0x18) -#define LZ4_DST_START LZ4_DST_START -#define LZ4_DST_START_POS (0U) -#define LZ4_DST_START_LEN (26U) -#define LZ4_DST_START_MSK (((1U << LZ4_DST_START_LEN) - 1) << LZ4_DST_START_POS) -#define LZ4_DST_START_UMSK (~(((1U << LZ4_DST_START_LEN) - 1) << LZ4_DST_START_POS)) -#define LZ4_DST_BASE LZ4_DST_BASE -#define LZ4_DST_BASE_POS (26U) -#define LZ4_DST_BASE_LEN (6U) -#define LZ4_DST_BASE_MSK (((1U << LZ4_DST_BASE_LEN) - 1) << LZ4_DST_BASE_POS) -#define LZ4_DST_BASE_UMSK (~(((1U << LZ4_DST_BASE_LEN) - 1) << LZ4_DST_BASE_POS)) - -/* 0x1C : lz4_dst_end */ -#define LZ4_DST_END_OFFSET (0x1C) -#define LZ4_DST_END LZ4_DST_END -#define LZ4_DST_END_POS (0U) -#define LZ4_DST_END_LEN (26U) -#define LZ4_DST_END_MSK (((1U << LZ4_DST_END_LEN) - 1) << LZ4_DST_END_POS) -#define LZ4_DST_END_UMSK (~(((1U << LZ4_DST_END_LEN) - 1) << LZ4_DST_END_POS)) - -/* 0x20 : lz4_int_en */ -#define LZ4_INT_EN_OFFSET (0x20) -#define LZ4_DONE_EN LZ4_DONE_EN -#define LZ4_DONE_EN_POS (0U) -#define LZ4_DONE_EN_LEN (1U) -#define LZ4_DONE_EN_MSK (((1U << LZ4_DONE_EN_LEN) - 1) << LZ4_DONE_EN_POS) -#define LZ4_DONE_EN_UMSK (~(((1U << LZ4_DONE_EN_LEN) - 1) << LZ4_DONE_EN_POS)) -#define LZ4_ERR_EN LZ4_ERR_EN -#define LZ4_ERR_EN_POS (1U) -#define LZ4_ERR_EN_LEN (1U) -#define LZ4_ERR_EN_MSK (((1U << LZ4_ERR_EN_LEN) - 1) << LZ4_ERR_EN_POS) -#define LZ4_ERR_EN_UMSK (~(((1U << LZ4_ERR_EN_LEN) - 1) << LZ4_ERR_EN_POS)) -#define LZ4_DST_INT_EN LZ4_DST_INT_EN -#define LZ4_DST_INT_EN_POS (10U) -#define LZ4_DST_INT_EN_LEN (6U) -#define LZ4_DST_INT_EN_MSK (((1U << LZ4_DST_INT_EN_LEN) - 1) << LZ4_DST_INT_EN_POS) -#define LZ4_DST_INT_EN_UMSK (~(((1U << LZ4_DST_INT_EN_LEN) - 1) << LZ4_DST_INT_EN_POS)) -#define LZ4_DST_INT_INV LZ4_DST_INT_INV -#define LZ4_DST_INT_INV_POS (26U) -#define LZ4_DST_INT_INV_LEN (6U) -#define LZ4_DST_INT_INV_MSK (((1U << LZ4_DST_INT_INV_LEN) - 1) << LZ4_DST_INT_INV_POS) -#define LZ4_DST_INT_INV_UMSK (~(((1U << LZ4_DST_INT_INV_LEN) - 1) << LZ4_DST_INT_INV_POS)) - -/* 0x24 : lz4_int_sta */ -#define LZ4_INT_STA_OFFSET (0x24) -#define LZ4_DONE_STA LZ4_DONE_STA -#define LZ4_DONE_STA_POS (0U) -#define LZ4_DONE_STA_LEN (1U) -#define LZ4_DONE_STA_MSK (((1U << LZ4_DONE_STA_LEN) - 1) << LZ4_DONE_STA_POS) -#define LZ4_DONE_STA_UMSK (~(((1U << LZ4_DONE_STA_LEN) - 1) << LZ4_DONE_STA_POS)) -#define LZ4_ERR_STA LZ4_ERR_STA -#define LZ4_ERR_STA_POS (1U) -#define LZ4_ERR_STA_LEN (1U) -#define LZ4_ERR_STA_MSK (((1U << LZ4_ERR_STA_LEN) - 1) << LZ4_ERR_STA_POS) -#define LZ4_ERR_STA_UMSK (~(((1U << LZ4_ERR_STA_LEN) - 1) << LZ4_ERR_STA_POS)) -#define LZ4_DST_INT_STA LZ4_DST_INT_STA -#define LZ4_DST_INT_STA_POS (10U) -#define LZ4_DST_INT_STA_LEN (6U) -#define LZ4_DST_INT_STA_MSK (((1U << LZ4_DST_INT_STA_LEN) - 1) << LZ4_DST_INT_STA_POS) -#define LZ4_DST_INT_STA_UMSK (~(((1U << LZ4_DST_INT_STA_LEN) - 1) << LZ4_DST_INT_STA_POS)) - -/* 0x28 : lz4_monitor */ -#define LZ4_MONITOR_OFFSET (0x28) -#define LZ4_CS LZ4_CS -#define LZ4_CS_POS (0U) -#define LZ4_CS_LEN (4U) -#define LZ4_CS_MSK (((1U << LZ4_CS_LEN) - 1) << LZ4_CS_POS) -#define LZ4_CS_UMSK (~(((1U << LZ4_CS_LEN) - 1) << LZ4_CS_POS)) - -struct lz4_reg { - /* 0x0 : lz4_config */ - union { - struct { - uint32_t lz4_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t lz4_suspend : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t lz4_checksum : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_27 : 23; /* [27: 5], rsvd, 0x0 */ - uint32_t rsvd_31_28 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_config; - - /* 0x4 : lz4_src_fix */ - union { - struct { - uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ - uint32_t lz4_src_fix : 14; /* [25:12], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_src_fix; - - /* 0x8 : lz4_dst_fix */ - union { - struct { - uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ - uint32_t lz4_dst_fix : 14; /* [25:12], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_dst_fix; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x10 : lz4_src_start */ - union { - struct { - uint32_t lz4_src_start : 26; /* [25: 0], r/w, 0x0 */ - uint32_t lz4_src_base : 6; /* [31:26], r/w, 0x0 */ - } BF; - uint32_t WORD; - } lz4_src_start; - - /* 0x14 : lz4_src_end */ - union { - struct { - uint32_t lz4_src_end : 26; /* [25: 0], r, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_src_end; - - /* 0x18 : lz4_dst_start */ - union { - struct { - uint32_t lz4_dst_start : 26; /* [25: 0], r/w, 0x0 */ - uint32_t lz4_dst_base : 6; /* [31:26], r/w, 0x0 */ - } BF; - uint32_t WORD; - } lz4_dst_start; - - /* 0x1C : lz4_dst_end */ - union { - struct { - uint32_t lz4_dst_end : 26; /* [25: 0], r, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_dst_end; - - /* 0x20 : lz4_int_en */ - union { - struct { - uint32_t lz4_done_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t lz4_err_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_9 : 8; /* [ 9: 2], rsvd, 0x0 */ - uint32_t lz4_dst_int_en : 6; /* [15:10], r/w, 0x0 */ - uint32_t reserved_16_25 : 10; /* [25:16], rsvd, 0x0 */ - uint32_t lz4_dst_int_inv : 6; /* [31:26], r/w, 0x0 */ - } BF; - uint32_t WORD; - } lz4_int_en; - - /* 0x24 : lz4_int_sta */ - union { - struct { - uint32_t lz4_done_sta : 1; /* [ 0], r, 0x0 */ - uint32_t lz4_err_sta : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_9 : 8; /* [ 9: 2], rsvd, 0x0 */ - uint32_t lz4_dst_int_sta : 6; /* [15:10], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_int_sta; - - /* 0x28 : lz4_monitor */ - union { - struct { - uint32_t lz4_cs : 4; /* [ 3: 0], r, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } lz4_monitor; -}; - -typedef volatile struct lz4_reg lz4_reg_t; - -#endif /* __LZ4_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjdec_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjdec_reg.h deleted file mode 100644 index c92e3ed9fe..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjdec_reg.h +++ /dev/null @@ -1,652 +0,0 @@ -/** - ****************************************************************************** - * @file mjdec_reg.h - * @version V1.0 - * @date 2021-07-02 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __MJDEC_REG_H__ -#define __MJDEC_REG_H__ - -#include "bl808.h" - -/* 0x0 : jdec_control_1 */ -#define MJDEC_JDEC_CONTROL_1_OFFSET (0x0) -#define MJDEC_REG_MJ_DEC_ENABLE MJDEC_REG_MJ_DEC_ENABLE -#define MJDEC_REG_MJ_DEC_ENABLE_POS (0U) -#define MJDEC_REG_MJ_DEC_ENABLE_LEN (1U) -#define MJDEC_REG_MJ_DEC_ENABLE_MSK (((1U << MJDEC_REG_MJ_DEC_ENABLE_LEN) - 1) << MJDEC_REG_MJ_DEC_ENABLE_POS) -#define MJDEC_REG_MJ_DEC_ENABLE_UMSK (~(((1U << MJDEC_REG_MJ_DEC_ENABLE_LEN) - 1) << MJDEC_REG_MJ_DEC_ENABLE_POS)) -#define MJDEC_REG_SWAP_MODE MJDEC_REG_SWAP_MODE -#define MJDEC_REG_SWAP_MODE_POS (1U) -#define MJDEC_REG_SWAP_MODE_LEN (1U) -#define MJDEC_REG_SWAP_MODE_MSK (((1U << MJDEC_REG_SWAP_MODE_LEN) - 1) << MJDEC_REG_SWAP_MODE_POS) -#define MJDEC_REG_SWAP_MODE_UMSK (~(((1U << MJDEC_REG_SWAP_MODE_LEN) - 1) << MJDEC_REG_SWAP_MODE_POS)) -#define MJDEC_REG_U_EVEN MJDEC_REG_U_EVEN -#define MJDEC_REG_U_EVEN_POS (2U) -#define MJDEC_REG_U_EVEN_LEN (1U) -#define MJDEC_REG_U_EVEN_MSK (((1U << MJDEC_REG_U_EVEN_LEN) - 1) << MJDEC_REG_U_EVEN_POS) -#define MJDEC_REG_U_EVEN_UMSK (~(((1U << MJDEC_REG_U_EVEN_LEN) - 1) << MJDEC_REG_U_EVEN_POS)) -#define MJDEC_REG_YUV_MODE MJDEC_REG_YUV_MODE -#define MJDEC_REG_YUV_MODE_POS (3U) -#define MJDEC_REG_YUV_MODE_LEN (2U) -#define MJDEC_REG_YUV_MODE_MSK (((1U << MJDEC_REG_YUV_MODE_LEN) - 1) << MJDEC_REG_YUV_MODE_POS) -#define MJDEC_REG_YUV_MODE_UMSK (~(((1U << MJDEC_REG_YUV_MODE_LEN) - 1) << MJDEC_REG_YUV_MODE_POS)) -#define MJDEC_REG_LAST_HF_WBLK_DMY MJDEC_REG_LAST_HF_WBLK_DMY -#define MJDEC_REG_LAST_HF_WBLK_DMY_POS (5U) -#define MJDEC_REG_LAST_HF_WBLK_DMY_LEN (1U) -#define MJDEC_REG_LAST_HF_WBLK_DMY_MSK (((1U << MJDEC_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_WBLK_DMY_POS) -#define MJDEC_REG_LAST_HF_WBLK_DMY_UMSK (~(((1U << MJDEC_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_WBLK_DMY_POS)) -#define MJDEC_REG_LAST_HF_HBLK_DMY MJDEC_REG_LAST_HF_HBLK_DMY -#define MJDEC_REG_LAST_HF_HBLK_DMY_POS (6U) -#define MJDEC_REG_LAST_HF_HBLK_DMY_LEN (1U) -#define MJDEC_REG_LAST_HF_HBLK_DMY_MSK (((1U << MJDEC_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_HBLK_DMY_POS) -#define MJDEC_REG_LAST_HF_HBLK_DMY_UMSK (~(((1U << MJDEC_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_HBLK_DMY_POS)) -#define MJDEC_REG_W_XLEN MJDEC_REG_W_XLEN -#define MJDEC_REG_W_XLEN_POS (8U) -#define MJDEC_REG_W_XLEN_LEN (3U) -#define MJDEC_REG_W_XLEN_MSK (((1U << MJDEC_REG_W_XLEN_LEN) - 1) << MJDEC_REG_W_XLEN_POS) -#define MJDEC_REG_W_XLEN_UMSK (~(((1U << MJDEC_REG_W_XLEN_LEN) - 1) << MJDEC_REG_W_XLEN_POS)) -#define MJDEC_REG_LAST_HF_BLK_DMY MJDEC_REG_LAST_HF_BLK_DMY -#define MJDEC_REG_LAST_HF_BLK_DMY_POS (11U) -#define MJDEC_REG_LAST_HF_BLK_DMY_LEN (1U) -#define MJDEC_REG_LAST_HF_BLK_DMY_MSK (((1U << MJDEC_REG_LAST_HF_BLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_BLK_DMY_POS) -#define MJDEC_REG_LAST_HF_BLK_DMY_UMSK (~(((1U << MJDEC_REG_LAST_HF_BLK_DMY_LEN) - 1) << MJDEC_REG_LAST_HF_BLK_DMY_POS)) -#define MJDEC_REG_R_XLEN MJDEC_REG_R_XLEN -#define MJDEC_REG_R_XLEN_POS (12U) -#define MJDEC_REG_R_XLEN_LEN (3U) -#define MJDEC_REG_R_XLEN_MSK (((1U << MJDEC_REG_R_XLEN_LEN) - 1) << MJDEC_REG_R_XLEN_POS) -#define MJDEC_REG_R_XLEN_UMSK (~(((1U << MJDEC_REG_R_XLEN_LEN) - 1) << MJDEC_REG_R_XLEN_POS)) -#define MJDEC_REG_Q_MODE MJDEC_REG_Q_MODE -#define MJDEC_REG_Q_MODE_POS (16U) -#define MJDEC_REG_Q_MODE_LEN (7U) -#define MJDEC_REG_Q_MODE_MSK (((1U << MJDEC_REG_Q_MODE_LEN) - 1) << MJDEC_REG_Q_MODE_POS) -#define MJDEC_REG_Q_MODE_UMSK (~(((1U << MJDEC_REG_Q_MODE_LEN) - 1) << MJDEC_REG_Q_MODE_POS)) - -/* 0x08 : jdec_yy_frame_addr */ -#define MJDEC_JDEC_YY_FRAME_ADDR_OFFSET (0x08) -#define MJDEC_REG_YY_ADDR_START MJDEC_REG_YY_ADDR_START -#define MJDEC_REG_YY_ADDR_START_POS (0U) -#define MJDEC_REG_YY_ADDR_START_LEN (32U) -#define MJDEC_REG_YY_ADDR_START_MSK (((1U << MJDEC_REG_YY_ADDR_START_LEN) - 1) << MJDEC_REG_YY_ADDR_START_POS) -#define MJDEC_REG_YY_ADDR_START_UMSK (~(((1U << MJDEC_REG_YY_ADDR_START_LEN) - 1) << MJDEC_REG_YY_ADDR_START_POS)) - -/* 0x0C : jdec_uv_frame_addr */ -#define MJDEC_JDEC_UV_FRAME_ADDR_OFFSET (0x0C) -#define MJDEC_REG_UV_ADDR_START MJDEC_REG_UV_ADDR_START -#define MJDEC_REG_UV_ADDR_START_POS (0U) -#define MJDEC_REG_UV_ADDR_START_LEN (32U) -#define MJDEC_REG_UV_ADDR_START_MSK (((1U << MJDEC_REG_UV_ADDR_START_LEN) - 1) << MJDEC_REG_UV_ADDR_START_POS) -#define MJDEC_REG_UV_ADDR_START_UMSK (~(((1U << MJDEC_REG_UV_ADDR_START_LEN) - 1) << MJDEC_REG_UV_ADDR_START_POS)) - -/* 0x1C : jdec_control_3 */ -#define MJDEC_JDEC_CONTROL_3_OFFSET (0x1C) -#define MJDEC_REG_INT_NORMAL_EN MJDEC_REG_INT_NORMAL_EN -#define MJDEC_REG_INT_NORMAL_EN_POS (0U) -#define MJDEC_REG_INT_NORMAL_EN_LEN (1U) -#define MJDEC_REG_INT_NORMAL_EN_MSK (((1U << MJDEC_REG_INT_NORMAL_EN_LEN) - 1) << MJDEC_REG_INT_NORMAL_EN_POS) -#define MJDEC_REG_INT_NORMAL_EN_UMSK (~(((1U << MJDEC_REG_INT_NORMAL_EN_LEN) - 1) << MJDEC_REG_INT_NORMAL_EN_POS)) -#define MJDEC_REG_INT_IDLE_EN MJDEC_REG_INT_IDLE_EN -#define MJDEC_REG_INT_IDLE_EN_POS (1U) -#define MJDEC_REG_INT_IDLE_EN_LEN (1U) -#define MJDEC_REG_INT_IDLE_EN_MSK (((1U << MJDEC_REG_INT_IDLE_EN_LEN) - 1) << MJDEC_REG_INT_IDLE_EN_POS) -#define MJDEC_REG_INT_IDLE_EN_UMSK (~(((1U << MJDEC_REG_INT_IDLE_EN_LEN) - 1) << MJDEC_REG_INT_IDLE_EN_POS)) -#define MJDEC_STS_NORMAL_INT MJDEC_STS_NORMAL_INT -#define MJDEC_STS_NORMAL_INT_POS (4U) -#define MJDEC_STS_NORMAL_INT_LEN (1U) -#define MJDEC_STS_NORMAL_INT_MSK (((1U << MJDEC_STS_NORMAL_INT_LEN) - 1) << MJDEC_STS_NORMAL_INT_POS) -#define MJDEC_STS_NORMAL_INT_UMSK (~(((1U << MJDEC_STS_NORMAL_INT_LEN) - 1) << MJDEC_STS_NORMAL_INT_POS)) -#define MJDEC_STS_IDLE_INT MJDEC_STS_IDLE_INT -#define MJDEC_STS_IDLE_INT_POS (5U) -#define MJDEC_STS_IDLE_INT_LEN (1U) -#define MJDEC_STS_IDLE_INT_MSK (((1U << MJDEC_STS_IDLE_INT_LEN) - 1) << MJDEC_STS_IDLE_INT_POS) -#define MJDEC_STS_IDLE_INT_UMSK (~(((1U << MJDEC_STS_IDLE_INT_LEN) - 1) << MJDEC_STS_IDLE_INT_POS)) -#define MJDEC_MJPEG_IDLE MJDEC_MJPEG_IDLE -#define MJDEC_MJPEG_IDLE_POS (8U) -#define MJDEC_MJPEG_IDLE_LEN (1U) -#define MJDEC_MJPEG_IDLE_MSK (((1U << MJDEC_MJPEG_IDLE_LEN) - 1) << MJDEC_MJPEG_IDLE_POS) -#define MJDEC_MJPEG_IDLE_UMSK (~(((1U << MJDEC_MJPEG_IDLE_LEN) - 1) << MJDEC_MJPEG_IDLE_POS)) -#define MJDEC_MJPEG_FUNC MJDEC_MJPEG_FUNC -#define MJDEC_MJPEG_FUNC_POS (9U) -#define MJDEC_MJPEG_FUNC_LEN (1U) -#define MJDEC_MJPEG_FUNC_MSK (((1U << MJDEC_MJPEG_FUNC_LEN) - 1) << MJDEC_MJPEG_FUNC_POS) -#define MJDEC_MJPEG_FUNC_UMSK (~(((1U << MJDEC_MJPEG_FUNC_LEN) - 1) << MJDEC_MJPEG_FUNC_POS)) -#define MJDEC_MJPEG_FLSH MJDEC_MJPEG_FLSH -#define MJDEC_MJPEG_FLSH_POS (11U) -#define MJDEC_MJPEG_FLSH_LEN (1U) -#define MJDEC_MJPEG_FLSH_MSK (((1U << MJDEC_MJPEG_FLSH_LEN) - 1) << MJDEC_MJPEG_FLSH_POS) -#define MJDEC_MJPEG_FLSH_UMSK (~(((1U << MJDEC_MJPEG_FLSH_LEN) - 1) << MJDEC_MJPEG_FLSH_POS)) -#define MJDEC_AXI_READ_IDLE MJDEC_AXI_READ_IDLE -#define MJDEC_AXI_READ_IDLE_POS (14U) -#define MJDEC_AXI_READ_IDLE_LEN (1U) -#define MJDEC_AXI_READ_IDLE_MSK (((1U << MJDEC_AXI_READ_IDLE_LEN) - 1) << MJDEC_AXI_READ_IDLE_POS) -#define MJDEC_AXI_READ_IDLE_UMSK (~(((1U << MJDEC_AXI_READ_IDLE_LEN) - 1) << MJDEC_AXI_READ_IDLE_POS)) -#define MJDEC_AXI_WRITE_IDLE MJDEC_AXI_WRITE_IDLE -#define MJDEC_AXI_WRITE_IDLE_POS (15U) -#define MJDEC_AXI_WRITE_IDLE_LEN (1U) -#define MJDEC_AXI_WRITE_IDLE_MSK (((1U << MJDEC_AXI_WRITE_IDLE_LEN) - 1) << MJDEC_AXI_WRITE_IDLE_POS) -#define MJDEC_AXI_WRITE_IDLE_UMSK (~(((1U << MJDEC_AXI_WRITE_IDLE_LEN) - 1) << MJDEC_AXI_WRITE_IDLE_POS)) -#define MJDEC_REG_FRAME_CNT_TRGR_INT MJDEC_REG_FRAME_CNT_TRGR_INT -#define MJDEC_REG_FRAME_CNT_TRGR_INT_POS (16U) -#define MJDEC_REG_FRAME_CNT_TRGR_INT_LEN (5U) -#define MJDEC_REG_FRAME_CNT_TRGR_INT_MSK (((1U << MJDEC_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJDEC_REG_FRAME_CNT_TRGR_INT_POS) -#define MJDEC_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << MJDEC_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJDEC_REG_FRAME_CNT_TRGR_INT_POS)) -#define MJDEC_FRAME_VALID_CNT MJDEC_FRAME_VALID_CNT -#define MJDEC_FRAME_VALID_CNT_POS (24U) -#define MJDEC_FRAME_VALID_CNT_LEN (8U) -#define MJDEC_FRAME_VALID_CNT_MSK (((1U << MJDEC_FRAME_VALID_CNT_LEN) - 1) << MJDEC_FRAME_VALID_CNT_POS) -#define MJDEC_FRAME_VALID_CNT_UMSK (~(((1U << MJDEC_FRAME_VALID_CNT_LEN) - 1) << MJDEC_FRAME_VALID_CNT_POS)) - -/* 0x20 : jdec_int_clr */ -#define MJDEC_JDEC_INT_CLR_OFFSET (0x20) -#define MJDEC_REG_INT_CLR MJDEC_REG_INT_CLR -#define MJDEC_REG_INT_CLR_POS (0U) -#define MJDEC_REG_INT_CLR_LEN (1U) -#define MJDEC_REG_INT_CLR_MSK (((1U << MJDEC_REG_INT_CLR_LEN) - 1) << MJDEC_REG_INT_CLR_POS) -#define MJDEC_REG_INT_CLR_UMSK (~(((1U << MJDEC_REG_INT_CLR_LEN) - 1) << MJDEC_REG_INT_CLR_POS)) -#define MJDEC_REG_YUV_FRAME_POP MJDEC_REG_YUV_FRAME_POP -#define MJDEC_REG_YUV_FRAME_POP_POS (1U) -#define MJDEC_REG_YUV_FRAME_POP_LEN (1U) -#define MJDEC_REG_YUV_FRAME_POP_MSK (((1U << MJDEC_REG_YUV_FRAME_POP_LEN) - 1) << MJDEC_REG_YUV_FRAME_POP_POS) -#define MJDEC_REG_YUV_FRAME_POP_UMSK (~(((1U << MJDEC_REG_YUV_FRAME_POP_LEN) - 1) << MJDEC_REG_YUV_FRAME_POP_POS)) - -/* 0x24 : jdec_fram_push */ -#define MJDEC_JDEC_FRAM_PUSH_OFFSET (0x24) -#define MJDEC_REG_JP_PUSH MJDEC_REG_JP_PUSH -#define MJDEC_REG_JP_PUSH_POS (0U) -#define MJDEC_REG_JP_PUSH_LEN (1U) -#define MJDEC_REG_JP_PUSH_MSK (((1U << MJDEC_REG_JP_PUSH_LEN) - 1) << MJDEC_REG_JP_PUSH_POS) -#define MJDEC_REG_JP_PUSH_UMSK (~(((1U << MJDEC_REG_JP_PUSH_LEN) - 1) << MJDEC_REG_JP_PUSH_POS)) -#define MJDEC_REG_JP_ADDR MJDEC_REG_JP_ADDR -#define MJDEC_REG_JP_ADDR_POS (2U) -#define MJDEC_REG_JP_ADDR_LEN (30U) -#define MJDEC_REG_JP_ADDR_MSK (((1U << MJDEC_REG_JP_ADDR_LEN) - 1) << MJDEC_REG_JP_ADDR_POS) -#define MJDEC_REG_JP_ADDR_UMSK (~(((1U << MJDEC_REG_JP_ADDR_LEN) - 1) << MJDEC_REG_JP_ADDR_POS)) - -/* 0x28 : jdec_fram_sts */ -#define MJDEC_JDEC_FRAM_STS_OFFSET (0x28) -#define MJDEC_JP_FRAME_CNT MJDEC_JP_FRAME_CNT -#define MJDEC_JP_FRAME_CNT_POS (0U) -#define MJDEC_JP_FRAME_CNT_LEN (5U) -#define MJDEC_JP_FRAME_CNT_MSK (((1U << MJDEC_JP_FRAME_CNT_LEN) - 1) << MJDEC_JP_FRAME_CNT_POS) -#define MJDEC_JP_FRAME_CNT_UMSK (~(((1U << MJDEC_JP_FRAME_CNT_LEN) - 1) << MJDEC_JP_FRAME_CNT_POS)) - -/* 0x2C : jdec_frame_size */ -#define MJDEC_JDEC_FRAME_SIZE_OFFSET (0x2C) -#define MJDEC_REG_FRAME_WBLK MJDEC_REG_FRAME_WBLK -#define MJDEC_REG_FRAME_WBLK_POS (0U) -#define MJDEC_REG_FRAME_WBLK_LEN (12U) -#define MJDEC_REG_FRAME_WBLK_MSK (((1U << MJDEC_REG_FRAME_WBLK_LEN) - 1) << MJDEC_REG_FRAME_WBLK_POS) -#define MJDEC_REG_FRAME_WBLK_UMSK (~(((1U << MJDEC_REG_FRAME_WBLK_LEN) - 1) << MJDEC_REG_FRAME_WBLK_POS)) -#define MJDEC_REG_FRAME_HBLK MJDEC_REG_FRAME_HBLK -#define MJDEC_REG_FRAME_HBLK_POS (16U) -#define MJDEC_REG_FRAME_HBLK_LEN (12U) -#define MJDEC_REG_FRAME_HBLK_MSK (((1U << MJDEC_REG_FRAME_HBLK_LEN) - 1) << MJDEC_REG_FRAME_HBLK_POS) -#define MJDEC_REG_FRAME_HBLK_UMSK (~(((1U << MJDEC_REG_FRAME_HBLK_LEN) - 1) << MJDEC_REG_FRAME_HBLK_POS)) - -/* 0x30 : jdec_header_skip */ -#define MJDEC_JDEC_HEADER_SKIP_OFFSET (0x30) -#define MJDEC_REG_HDER_SKIP_BYTE MJDEC_REG_HDER_SKIP_BYTE -#define MJDEC_REG_HDER_SKIP_BYTE_POS (0U) -#define MJDEC_REG_HDER_SKIP_BYTE_LEN (16U) -#define MJDEC_REG_HDER_SKIP_BYTE_MSK (((1U << MJDEC_REG_HDER_SKIP_BYTE_LEN) - 1) << MJDEC_REG_HDER_SKIP_BYTE_POS) -#define MJDEC_REG_HDER_SKIP_BYTE_UMSK (~(((1U << MJDEC_REG_HDER_SKIP_BYTE_LEN) - 1) << MJDEC_REG_HDER_SKIP_BYTE_POS)) -#define MJDEC_REG_HDER_SKIP MJDEC_REG_HDER_SKIP -#define MJDEC_REG_HDER_SKIP_POS (16U) -#define MJDEC_REG_HDER_SKIP_LEN (1U) -#define MJDEC_REG_HDER_SKIP_MSK (((1U << MJDEC_REG_HDER_SKIP_LEN) - 1) << MJDEC_REG_HDER_SKIP_POS) -#define MJDEC_REG_HDER_SKIP_UMSK (~(((1U << MJDEC_REG_HDER_SKIP_LEN) - 1) << MJDEC_REG_HDER_SKIP_POS)) - -/* 0x40 : jp_addr0 */ -#define MJDEC_JP_ADDR0_OFFSET (0x40) -#define MJDEC_JP_ADDR_0 MJDEC_JP_ADDR_0 -#define MJDEC_JP_ADDR_0_POS (0U) -#define MJDEC_JP_ADDR_0_LEN (32U) -#define MJDEC_JP_ADDR_0_MSK (((1U << MJDEC_JP_ADDR_0_LEN) - 1) << MJDEC_JP_ADDR_0_POS) -#define MJDEC_JP_ADDR_0_UMSK (~(((1U << MJDEC_JP_ADDR_0_LEN) - 1) << MJDEC_JP_ADDR_0_POS)) - -/* 0x44 : jp_addr1 */ -#define MJDEC_JP_ADDR1_OFFSET (0x44) -#define MJDEC_JP_ADDR_1 MJDEC_JP_ADDR_1 -#define MJDEC_JP_ADDR_1_POS (0U) -#define MJDEC_JP_ADDR_1_LEN (32U) -#define MJDEC_JP_ADDR_1_MSK (((1U << MJDEC_JP_ADDR_1_LEN) - 1) << MJDEC_JP_ADDR_1_POS) -#define MJDEC_JP_ADDR_1_UMSK (~(((1U << MJDEC_JP_ADDR_1_LEN) - 1) << MJDEC_JP_ADDR_1_POS)) - -/* 0x48 : jp_addr2 */ -#define MJDEC_JP_ADDR2_OFFSET (0x48) -#define MJDEC_JP_ADDR_2 MJDEC_JP_ADDR_2 -#define MJDEC_JP_ADDR_2_POS (0U) -#define MJDEC_JP_ADDR_2_LEN (32U) -#define MJDEC_JP_ADDR_2_MSK (((1U << MJDEC_JP_ADDR_2_LEN) - 1) << MJDEC_JP_ADDR_2_POS) -#define MJDEC_JP_ADDR_2_UMSK (~(((1U << MJDEC_JP_ADDR_2_LEN) - 1) << MJDEC_JP_ADDR_2_POS)) - -/* 0x4C : jp_addr3 */ -#define MJDEC_JP_ADDR3_OFFSET (0x4C) -#define MJDEC_JP_ADDR_3 MJDEC_JP_ADDR_3 -#define MJDEC_JP_ADDR_3_POS (0U) -#define MJDEC_JP_ADDR_3_LEN (32U) -#define MJDEC_JP_ADDR_3_MSK (((1U << MJDEC_JP_ADDR_3_LEN) - 1) << MJDEC_JP_ADDR_3_POS) -#define MJDEC_JP_ADDR_3_UMSK (~(((1U << MJDEC_JP_ADDR_3_LEN) - 1) << MJDEC_JP_ADDR_3_POS)) - -/* 0x50 : jp_addr4 */ -#define MJDEC_JP_ADDR4_OFFSET (0x50) -#define MJDEC_JP_ADDR_4 MJDEC_JP_ADDR_4 -#define MJDEC_JP_ADDR_4_POS (0U) -#define MJDEC_JP_ADDR_4_LEN (32U) -#define MJDEC_JP_ADDR_4_MSK (((1U << MJDEC_JP_ADDR_4_LEN) - 1) << MJDEC_JP_ADDR_4_POS) -#define MJDEC_JP_ADDR_4_UMSK (~(((1U << MJDEC_JP_ADDR_4_LEN) - 1) << MJDEC_JP_ADDR_4_POS)) - -/* 0x54 : jp_addr5 */ -#define MJDEC_JP_ADDR5_OFFSET (0x54) -#define MJDEC_JP_ADDR_5 MJDEC_JP_ADDR_5 -#define MJDEC_JP_ADDR_5_POS (0U) -#define MJDEC_JP_ADDR_5_LEN (32U) -#define MJDEC_JP_ADDR_5_MSK (((1U << MJDEC_JP_ADDR_5_LEN) - 1) << MJDEC_JP_ADDR_5_POS) -#define MJDEC_JP_ADDR_5_UMSK (~(((1U << MJDEC_JP_ADDR_5_LEN) - 1) << MJDEC_JP_ADDR_5_POS)) - -/* 0x58 : jp_addr6 */ -#define MJDEC_JP_ADDR6_OFFSET (0x58) -#define MJDEC_JP_ADDR_6 MJDEC_JP_ADDR_6 -#define MJDEC_JP_ADDR_6_POS (0U) -#define MJDEC_JP_ADDR_6_LEN (32U) -#define MJDEC_JP_ADDR_6_MSK (((1U << MJDEC_JP_ADDR_6_LEN) - 1) << MJDEC_JP_ADDR_6_POS) -#define MJDEC_JP_ADDR_6_UMSK (~(((1U << MJDEC_JP_ADDR_6_LEN) - 1) << MJDEC_JP_ADDR_6_POS)) - -/* 0x5C : jp_addr7 */ -#define MJDEC_JP_ADDR7_OFFSET (0x5C) -#define MJDEC_JP_ADDR_7 MJDEC_JP_ADDR_7 -#define MJDEC_JP_ADDR_7_POS (0U) -#define MJDEC_JP_ADDR_7_LEN (32U) -#define MJDEC_JP_ADDR_7_MSK (((1U << MJDEC_JP_ADDR_7_LEN) - 1) << MJDEC_JP_ADDR_7_POS) -#define MJDEC_JP_ADDR_7_UMSK (~(((1U << MJDEC_JP_ADDR_7_LEN) - 1) << MJDEC_JP_ADDR_7_POS)) - -/* 0x60 : jp_addr_8 */ -#define MJDEC_JP_ADDR_8_OFFSET (0x60) -#define MJDEC_JP_ADDR_8 MJDEC_JP_ADDR_8 -#define MJDEC_JP_ADDR_8_POS (0U) -#define MJDEC_JP_ADDR_8_LEN (32U) -#define MJDEC_JP_ADDR_8_MSK (((1U << MJDEC_JP_ADDR_8_LEN) - 1) << MJDEC_JP_ADDR_8_POS) -#define MJDEC_JP_ADDR_8_UMSK (~(((1U << MJDEC_JP_ADDR_8_LEN) - 1) << MJDEC_JP_ADDR_8_POS)) - -/* 0x64 : jp_addr_9 */ -#define MJDEC_JP_ADDR_9_OFFSET (0x64) -#define MJDEC_JP_ADDR_9 MJDEC_JP_ADDR_9 -#define MJDEC_JP_ADDR_9_POS (0U) -#define MJDEC_JP_ADDR_9_LEN (32U) -#define MJDEC_JP_ADDR_9_MSK (((1U << MJDEC_JP_ADDR_9_LEN) - 1) << MJDEC_JP_ADDR_9_POS) -#define MJDEC_JP_ADDR_9_UMSK (~(((1U << MJDEC_JP_ADDR_9_LEN) - 1) << MJDEC_JP_ADDR_9_POS)) - -/* 0x68 : jp_addr_a */ -#define MJDEC_JP_ADDR_A_OFFSET (0x68) -#define MJDEC_JP_ADDR_A MJDEC_JP_ADDR_A -#define MJDEC_JP_ADDR_A_POS (0U) -#define MJDEC_JP_ADDR_A_LEN (32U) -#define MJDEC_JP_ADDR_A_MSK (((1U << MJDEC_JP_ADDR_A_LEN) - 1) << MJDEC_JP_ADDR_A_POS) -#define MJDEC_JP_ADDR_A_UMSK (~(((1U << MJDEC_JP_ADDR_A_LEN) - 1) << MJDEC_JP_ADDR_A_POS)) - -/* 0x6C : jp_addr_b */ -#define MJDEC_JP_ADDR_B_OFFSET (0x6C) -#define MJDEC_JP_ADDR_B MJDEC_JP_ADDR_B -#define MJDEC_JP_ADDR_B_POS (0U) -#define MJDEC_JP_ADDR_B_LEN (32U) -#define MJDEC_JP_ADDR_B_MSK (((1U << MJDEC_JP_ADDR_B_LEN) - 1) << MJDEC_JP_ADDR_B_POS) -#define MJDEC_JP_ADDR_B_UMSK (~(((1U << MJDEC_JP_ADDR_B_LEN) - 1) << MJDEC_JP_ADDR_B_POS)) - -/* 0x70 : jp_addr_c */ -#define MJDEC_JP_ADDR_C_OFFSET (0x70) -#define MJDEC_JP_ADDR_C MJDEC_JP_ADDR_C -#define MJDEC_JP_ADDR_C_POS (0U) -#define MJDEC_JP_ADDR_C_LEN (32U) -#define MJDEC_JP_ADDR_C_MSK (((1U << MJDEC_JP_ADDR_C_LEN) - 1) << MJDEC_JP_ADDR_C_POS) -#define MJDEC_JP_ADDR_C_UMSK (~(((1U << MJDEC_JP_ADDR_C_LEN) - 1) << MJDEC_JP_ADDR_C_POS)) - -/* 0x74 : jp_addr_d */ -#define MJDEC_JP_ADDR_D_OFFSET (0x74) -#define MJDEC_JP_ADDR_D MJDEC_JP_ADDR_D -#define MJDEC_JP_ADDR_D_POS (0U) -#define MJDEC_JP_ADDR_D_LEN (32U) -#define MJDEC_JP_ADDR_D_MSK (((1U << MJDEC_JP_ADDR_D_LEN) - 1) << MJDEC_JP_ADDR_D_POS) -#define MJDEC_JP_ADDR_D_UMSK (~(((1U << MJDEC_JP_ADDR_D_LEN) - 1) << MJDEC_JP_ADDR_D_POS)) - -/* 0x78 : jp_addr_e */ -#define MJDEC_JP_ADDR_E_OFFSET (0x78) -#define MJDEC_JP_ADDR_E MJDEC_JP_ADDR_E -#define MJDEC_JP_ADDR_E_POS (0U) -#define MJDEC_JP_ADDR_E_LEN (32U) -#define MJDEC_JP_ADDR_E_MSK (((1U << MJDEC_JP_ADDR_E_LEN) - 1) << MJDEC_JP_ADDR_E_POS) -#define MJDEC_JP_ADDR_E_UMSK (~(((1U << MJDEC_JP_ADDR_E_LEN) - 1) << MJDEC_JP_ADDR_E_POS)) - -/* 0x7C : jp_addr_f */ -#define MJDEC_JP_ADDR_F_OFFSET (0x7C) -#define MJDEC_JP_ADDR_F MJDEC_JP_ADDR_F -#define MJDEC_JP_ADDR_F_POS (0U) -#define MJDEC_JP_ADDR_F_LEN (32U) -#define MJDEC_JP_ADDR_F_MSK (((1U << MJDEC_JP_ADDR_F_LEN) - 1) << MJDEC_JP_ADDR_F_POS) -#define MJDEC_JP_ADDR_F_UMSK (~(((1U << MJDEC_JP_ADDR_F_LEN) - 1) << MJDEC_JP_ADDR_F_POS)) - -/* 0x1F0 : mjdec_debug */ -#define MJDEC_DEBUG_OFFSET (0x1F0) -#define MJDEC_REG_MJDEC_DBG_EN MJDEC_REG_MJDEC_DBG_EN -#define MJDEC_REG_MJDEC_DBG_EN_POS (0U) -#define MJDEC_REG_MJDEC_DBG_EN_LEN (1U) -#define MJDEC_REG_MJDEC_DBG_EN_MSK (((1U << MJDEC_REG_MJDEC_DBG_EN_LEN) - 1) << MJDEC_REG_MJDEC_DBG_EN_POS) -#define MJDEC_REG_MJDEC_DBG_EN_UMSK (~(((1U << MJDEC_REG_MJDEC_DBG_EN_LEN) - 1) << MJDEC_REG_MJDEC_DBG_EN_POS)) -#define MJDEC_REG_MJDEC_DBG_SEL MJDEC_REG_MJDEC_DBG_SEL -#define MJDEC_REG_MJDEC_DBG_SEL_POS (4U) -#define MJDEC_REG_MJDEC_DBG_SEL_LEN (4U) -#define MJDEC_REG_MJDEC_DBG_SEL_MSK (((1U << MJDEC_REG_MJDEC_DBG_SEL_LEN) - 1) << MJDEC_REG_MJDEC_DBG_SEL_POS) -#define MJDEC_REG_MJDEC_DBG_SEL_UMSK (~(((1U << MJDEC_REG_MJDEC_DBG_SEL_LEN) - 1) << MJDEC_REG_MJDEC_DBG_SEL_POS)) - -/* 0x1FC : mjdec_dummy_reg */ -#define MJDEC_DUMMY_REG_OFFSET (0x1FC) -#define MJDEC_JDEC_DUMMY_REG MJDEC_JDEC_DUMMY_REG -#define MJDEC_JDEC_DUMMY_REG_POS (0U) -#define MJDEC_JDEC_DUMMY_REG_LEN (32U) -#define MJDEC_JDEC_DUMMY_REG_MSK (((1U << MJDEC_JDEC_DUMMY_REG_LEN) - 1) << MJDEC_JDEC_DUMMY_REG_POS) -#define MJDEC_JDEC_DUMMY_REG_UMSK (~(((1U << MJDEC_JDEC_DUMMY_REG_LEN) - 1) << MJDEC_JDEC_DUMMY_REG_POS)) - -struct mjdec_reg { - /* 0x0 : jdec_control_1 */ - union { - struct { - uint32_t reg_mj_dec_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_swap_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_u_even : 1; /* [ 2], r/w, 0x1 */ - uint32_t reg_yuv_mode : 2; /* [ 4: 3], r/w, 0x0 */ - uint32_t reg_last_hf_wblk_dmy : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_last_hf_hblk_dmy : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t reg_w_xlen : 3; /* [10: 8], r/w, 0x3 */ - uint32_t reg_last_hf_blk_dmy : 1; /* [ 11], r/w, 0x0 */ - uint32_t reg_r_xlen : 3; /* [14:12], r/w, 0x3 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t reg_q_mode : 7; /* [22:16], r/w, 0x32 */ - uint32_t reserved_23_31 : 9; /* [31:23], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_control_1; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[4]; - - /* 0x08 : jdec_yy_frame_addr */ - union { - struct { - uint32_t reg_yy_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } jdec_yy_frame_addr; - - /* 0x0C : jdec_uv_frame_addr */ - union { - struct { - uint32_t reg_uv_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } jdec_uv_frame_addr; - - /* 0x10 reserved */ - uint8_t RESERVED0x10[12]; - - /* 0x1C : jdec_control_3 */ - union { - struct { - uint32_t reg_int_normal_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_int_idle_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t sts_normal_int : 1; /* [ 4], r, 0x0 */ - uint32_t sts_idle_int : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t mjpeg_idle : 1; /* [ 8], r, 0x1 */ - uint32_t mjpeg_func : 1; /* [ 9], r, 0x0 */ - uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ - uint32_t mjpeg_flsh : 1; /* [ 11], r, 0x0 */ - uint32_t reserved_12_13 : 2; /* [13:12], rsvd, 0x0 */ - uint32_t axi_read_idle : 1; /* [ 14], r, 0x0 */ - uint32_t axi_write_idle : 1; /* [ 15], r, 0x0 */ - uint32_t reg_frame_cnt_trgr_int : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t frame_valid_cnt : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } jdec_control_3; - - /* 0x20 : jdec_int_clr */ - union { - struct { - uint32_t reg_int_clr : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_yuv_frame_pop : 1; /* [ 1], w1p, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_int_clr; - - /* 0x24 : jdec_fram_push */ - union { - struct { - uint32_t reg_jp_push : 1; /* [ 0], w1p, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t reg_jp_addr : 30; /* [31: 2], r/w, 0x0 */ - } BF; - uint32_t WORD; - } jdec_fram_push; - - /* 0x28 : jdec_fram_sts */ - union { - struct { - uint32_t jp_frame_cnt : 5; /* [ 4: 0], r, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_fram_sts; - - /* 0x2C : jdec_frame_size */ - union { - struct { - uint32_t reg_frame_wblk : 12; /* [11: 0], r/w, 0xf */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_frame_hblk : 12; /* [27:16], r/w, 0x14 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_frame_size; - - /* 0x30 : jdec_header_skip */ - union { - struct { - uint32_t reg_hder_skip_byte : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_hder_skip : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } jdec_header_skip; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[12]; - - /* 0x40 : jp_addr0 */ - union { - struct { - uint32_t jp_addr_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr0; - - /* 0x44 : jp_addr1 */ - union { - struct { - uint32_t jp_addr_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr1; - - /* 0x48 : jp_addr2 */ - union { - struct { - uint32_t jp_addr_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr2; - - /* 0x4C : jp_addr3 */ - union { - struct { - uint32_t jp_addr_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr3; - - /* 0x50 : jp_addr4 */ - union { - struct { - uint32_t jp_addr_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr4; - - /* 0x54 : jp_addr5 */ - union { - struct { - uint32_t jp_addr_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr5; - - /* 0x58 : jp_addr6 */ - union { - struct { - uint32_t jp_addr_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr6; - - /* 0x5C : jp_addr7 */ - union { - struct { - uint32_t jp_addr_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr7; - - /* 0x60 : jp_addr_8 */ - union { - struct { - uint32_t jp_addr_8 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_8; - - /* 0x64 : jp_addr_9 */ - union { - struct { - uint32_t jp_addr_9 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_9; - - /* 0x68 : jp_addr_a */ - union { - struct { - uint32_t jp_addr_a : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_a; - - /* 0x6C : jp_addr_b */ - union { - struct { - uint32_t jp_addr_b : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_b; - - /* 0x70 : jp_addr_c */ - union { - struct { - uint32_t jp_addr_c : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_c; - - /* 0x74 : jp_addr_d */ - union { - struct { - uint32_t jp_addr_d : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_d; - - /* 0x78 : jp_addr_e */ - union { - struct { - uint32_t jp_addr_e : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_e; - - /* 0x7C : jp_addr_f */ - union { - struct { - uint32_t jp_addr_f : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } jp_addr_f; - - /* 0x80 reserved */ - uint8_t RESERVED0x80[368]; - - /* 0x1F0 : mjdec_debug */ - union { - struct { - uint32_t reg_mjdec_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_mjdec_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjdec_debug; - - /* 0x1f4 reserved */ - uint8_t RESERVED0x1f4[8]; - - /* 0x1FC : mjdec_dummy_reg */ - union { - struct { - uint32_t jdec_dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } mjdec_dummy_reg; -}; - -typedef volatile struct mjdec_reg mjdec_reg_t; - -#endif /* __MJDEC_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_q_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_q_reg.h deleted file mode 100644 index e429e76e28..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_q_reg.h +++ /dev/null @@ -1,1584 +0,0 @@ -/** - ****************************************************************************** - * @file mjpeg_q_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __MJPEG_Q_REG_H__ -#define __MJPEG_Q_REG_H__ - -#include "bl808.h" - -/* 0x400 : mjpeg_q_param_00 */ -#define MJPEG_Q_PARAM_00_OFFSET (0x400) -#define MJPEG_Q_REG_Q_0_00 MJPEG_Q_REG_Q_0_00 -#define MJPEG_Q_REG_Q_0_00_POS (0U) -#define MJPEG_Q_REG_Q_0_00_LEN (12U) -#define MJPEG_Q_REG_Q_0_00_MSK (((1U << MJPEG_Q_REG_Q_0_00_LEN) - 1) << MJPEG_Q_REG_Q_0_00_POS) -#define MJPEG_Q_REG_Q_0_00_UMSK (~(((1U << MJPEG_Q_REG_Q_0_00_LEN) - 1) << MJPEG_Q_REG_Q_0_00_POS)) -#define MJPEG_Q_REG_Q_0_01 MJPEG_Q_REG_Q_0_01 -#define MJPEG_Q_REG_Q_0_01_POS (16U) -#define MJPEG_Q_REG_Q_0_01_LEN (12U) -#define MJPEG_Q_REG_Q_0_01_MSK (((1U << MJPEG_Q_REG_Q_0_01_LEN) - 1) << MJPEG_Q_REG_Q_0_01_POS) -#define MJPEG_Q_REG_Q_0_01_UMSK (~(((1U << MJPEG_Q_REG_Q_0_01_LEN) - 1) << MJPEG_Q_REG_Q_0_01_POS)) - -/* 0x404 : mjpeg_q_param_02 */ -#define MJPEG_Q_PARAM_02_OFFSET (0x404) -#define MJPEG_Q_REG_Q_0_02 MJPEG_Q_REG_Q_0_02 -#define MJPEG_Q_REG_Q_0_02_POS (0U) -#define MJPEG_Q_REG_Q_0_02_LEN (12U) -#define MJPEG_Q_REG_Q_0_02_MSK (((1U << MJPEG_Q_REG_Q_0_02_LEN) - 1) << MJPEG_Q_REG_Q_0_02_POS) -#define MJPEG_Q_REG_Q_0_02_UMSK (~(((1U << MJPEG_Q_REG_Q_0_02_LEN) - 1) << MJPEG_Q_REG_Q_0_02_POS)) -#define MJPEG_Q_REG_Q_0_03 MJPEG_Q_REG_Q_0_03 -#define MJPEG_Q_REG_Q_0_03_POS (16U) -#define MJPEG_Q_REG_Q_0_03_LEN (12U) -#define MJPEG_Q_REG_Q_0_03_MSK (((1U << MJPEG_Q_REG_Q_0_03_LEN) - 1) << MJPEG_Q_REG_Q_0_03_POS) -#define MJPEG_Q_REG_Q_0_03_UMSK (~(((1U << MJPEG_Q_REG_Q_0_03_LEN) - 1) << MJPEG_Q_REG_Q_0_03_POS)) - -/* 0x408 : mjpeg_q_param_04 */ -#define MJPEG_Q_PARAM_04_OFFSET (0x408) -#define MJPEG_Q_REG_Q_0_04 MJPEG_Q_REG_Q_0_04 -#define MJPEG_Q_REG_Q_0_04_POS (0U) -#define MJPEG_Q_REG_Q_0_04_LEN (12U) -#define MJPEG_Q_REG_Q_0_04_MSK (((1U << MJPEG_Q_REG_Q_0_04_LEN) - 1) << MJPEG_Q_REG_Q_0_04_POS) -#define MJPEG_Q_REG_Q_0_04_UMSK (~(((1U << MJPEG_Q_REG_Q_0_04_LEN) - 1) << MJPEG_Q_REG_Q_0_04_POS)) -#define MJPEG_Q_REG_Q_0_05 MJPEG_Q_REG_Q_0_05 -#define MJPEG_Q_REG_Q_0_05_POS (16U) -#define MJPEG_Q_REG_Q_0_05_LEN (12U) -#define MJPEG_Q_REG_Q_0_05_MSK (((1U << MJPEG_Q_REG_Q_0_05_LEN) - 1) << MJPEG_Q_REG_Q_0_05_POS) -#define MJPEG_Q_REG_Q_0_05_UMSK (~(((1U << MJPEG_Q_REG_Q_0_05_LEN) - 1) << MJPEG_Q_REG_Q_0_05_POS)) - -/* 0x40C : mjpeg_q_param_06 */ -#define MJPEG_Q_PARAM_06_OFFSET (0x40C) -#define MJPEG_Q_REG_Q_0_06 MJPEG_Q_REG_Q_0_06 -#define MJPEG_Q_REG_Q_0_06_POS (0U) -#define MJPEG_Q_REG_Q_0_06_LEN (12U) -#define MJPEG_Q_REG_Q_0_06_MSK (((1U << MJPEG_Q_REG_Q_0_06_LEN) - 1) << MJPEG_Q_REG_Q_0_06_POS) -#define MJPEG_Q_REG_Q_0_06_UMSK (~(((1U << MJPEG_Q_REG_Q_0_06_LEN) - 1) << MJPEG_Q_REG_Q_0_06_POS)) -#define MJPEG_Q_REG_Q_0_07 MJPEG_Q_REG_Q_0_07 -#define MJPEG_Q_REG_Q_0_07_POS (16U) -#define MJPEG_Q_REG_Q_0_07_LEN (12U) -#define MJPEG_Q_REG_Q_0_07_MSK (((1U << MJPEG_Q_REG_Q_0_07_LEN) - 1) << MJPEG_Q_REG_Q_0_07_POS) -#define MJPEG_Q_REG_Q_0_07_UMSK (~(((1U << MJPEG_Q_REG_Q_0_07_LEN) - 1) << MJPEG_Q_REG_Q_0_07_POS)) - -/* 0x410 : mjpeg_q_param_08 */ -#define MJPEG_Q_PARAM_08_OFFSET (0x410) -#define MJPEG_Q_REG_Q_0_08 MJPEG_Q_REG_Q_0_08 -#define MJPEG_Q_REG_Q_0_08_POS (0U) -#define MJPEG_Q_REG_Q_0_08_LEN (12U) -#define MJPEG_Q_REG_Q_0_08_MSK (((1U << MJPEG_Q_REG_Q_0_08_LEN) - 1) << MJPEG_Q_REG_Q_0_08_POS) -#define MJPEG_Q_REG_Q_0_08_UMSK (~(((1U << MJPEG_Q_REG_Q_0_08_LEN) - 1) << MJPEG_Q_REG_Q_0_08_POS)) -#define MJPEG_Q_REG_Q_0_09 MJPEG_Q_REG_Q_0_09 -#define MJPEG_Q_REG_Q_0_09_POS (16U) -#define MJPEG_Q_REG_Q_0_09_LEN (12U) -#define MJPEG_Q_REG_Q_0_09_MSK (((1U << MJPEG_Q_REG_Q_0_09_LEN) - 1) << MJPEG_Q_REG_Q_0_09_POS) -#define MJPEG_Q_REG_Q_0_09_UMSK (~(((1U << MJPEG_Q_REG_Q_0_09_LEN) - 1) << MJPEG_Q_REG_Q_0_09_POS)) - -/* 0x414 : mjpeg_q_param_0a */ -#define MJPEG_Q_PARAM_0A_OFFSET (0x414) -#define MJPEG_Q_REG_Q_0_0A MJPEG_Q_REG_Q_0_0A -#define MJPEG_Q_REG_Q_0_0A_POS (0U) -#define MJPEG_Q_REG_Q_0_0A_LEN (12U) -#define MJPEG_Q_REG_Q_0_0A_MSK (((1U << MJPEG_Q_REG_Q_0_0A_LEN) - 1) << MJPEG_Q_REG_Q_0_0A_POS) -#define MJPEG_Q_REG_Q_0_0A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0A_LEN) - 1) << MJPEG_Q_REG_Q_0_0A_POS)) -#define MJPEG_Q_REG_Q_0_0B MJPEG_Q_REG_Q_0_0B -#define MJPEG_Q_REG_Q_0_0B_POS (16U) -#define MJPEG_Q_REG_Q_0_0B_LEN (12U) -#define MJPEG_Q_REG_Q_0_0B_MSK (((1U << MJPEG_Q_REG_Q_0_0B_LEN) - 1) << MJPEG_Q_REG_Q_0_0B_POS) -#define MJPEG_Q_REG_Q_0_0B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0B_LEN) - 1) << MJPEG_Q_REG_Q_0_0B_POS)) - -/* 0x418 : mjpeg_q_param_0c */ -#define MJPEG_Q_PARAM_0C_OFFSET (0x418) -#define MJPEG_Q_REG_Q_0_0C MJPEG_Q_REG_Q_0_0C -#define MJPEG_Q_REG_Q_0_0C_POS (0U) -#define MJPEG_Q_REG_Q_0_0C_LEN (12U) -#define MJPEG_Q_REG_Q_0_0C_MSK (((1U << MJPEG_Q_REG_Q_0_0C_LEN) - 1) << MJPEG_Q_REG_Q_0_0C_POS) -#define MJPEG_Q_REG_Q_0_0C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0C_LEN) - 1) << MJPEG_Q_REG_Q_0_0C_POS)) -#define MJPEG_Q_REG_Q_0_0D MJPEG_Q_REG_Q_0_0D -#define MJPEG_Q_REG_Q_0_0D_POS (16U) -#define MJPEG_Q_REG_Q_0_0D_LEN (12U) -#define MJPEG_Q_REG_Q_0_0D_MSK (((1U << MJPEG_Q_REG_Q_0_0D_LEN) - 1) << MJPEG_Q_REG_Q_0_0D_POS) -#define MJPEG_Q_REG_Q_0_0D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0D_LEN) - 1) << MJPEG_Q_REG_Q_0_0D_POS)) - -/* 0x41C : mjpeg_q_param_0e */ -#define MJPEG_Q_PARAM_0E_OFFSET (0x41C) -#define MJPEG_Q_REG_Q_0_0E MJPEG_Q_REG_Q_0_0E -#define MJPEG_Q_REG_Q_0_0E_POS (0U) -#define MJPEG_Q_REG_Q_0_0E_LEN (12U) -#define MJPEG_Q_REG_Q_0_0E_MSK (((1U << MJPEG_Q_REG_Q_0_0E_LEN) - 1) << MJPEG_Q_REG_Q_0_0E_POS) -#define MJPEG_Q_REG_Q_0_0E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0E_LEN) - 1) << MJPEG_Q_REG_Q_0_0E_POS)) -#define MJPEG_Q_REG_Q_0_0F MJPEG_Q_REG_Q_0_0F -#define MJPEG_Q_REG_Q_0_0F_POS (16U) -#define MJPEG_Q_REG_Q_0_0F_LEN (12U) -#define MJPEG_Q_REG_Q_0_0F_MSK (((1U << MJPEG_Q_REG_Q_0_0F_LEN) - 1) << MJPEG_Q_REG_Q_0_0F_POS) -#define MJPEG_Q_REG_Q_0_0F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_0F_LEN) - 1) << MJPEG_Q_REG_Q_0_0F_POS)) - -/* 0x420 : mjpeg_q_param_10 */ -#define MJPEG_Q_PARAM_10_OFFSET (0x420) -#define MJPEG_Q_REG_Q_0_10 MJPEG_Q_REG_Q_0_10 -#define MJPEG_Q_REG_Q_0_10_POS (0U) -#define MJPEG_Q_REG_Q_0_10_LEN (12U) -#define MJPEG_Q_REG_Q_0_10_MSK (((1U << MJPEG_Q_REG_Q_0_10_LEN) - 1) << MJPEG_Q_REG_Q_0_10_POS) -#define MJPEG_Q_REG_Q_0_10_UMSK (~(((1U << MJPEG_Q_REG_Q_0_10_LEN) - 1) << MJPEG_Q_REG_Q_0_10_POS)) -#define MJPEG_Q_REG_Q_0_11 MJPEG_Q_REG_Q_0_11 -#define MJPEG_Q_REG_Q_0_11_POS (16U) -#define MJPEG_Q_REG_Q_0_11_LEN (12U) -#define MJPEG_Q_REG_Q_0_11_MSK (((1U << MJPEG_Q_REG_Q_0_11_LEN) - 1) << MJPEG_Q_REG_Q_0_11_POS) -#define MJPEG_Q_REG_Q_0_11_UMSK (~(((1U << MJPEG_Q_REG_Q_0_11_LEN) - 1) << MJPEG_Q_REG_Q_0_11_POS)) - -/* 0x424 : mjpeg_q_param_12 */ -#define MJPEG_Q_PARAM_12_OFFSET (0x424) -#define MJPEG_Q_REG_Q_0_12 MJPEG_Q_REG_Q_0_12 -#define MJPEG_Q_REG_Q_0_12_POS (0U) -#define MJPEG_Q_REG_Q_0_12_LEN (12U) -#define MJPEG_Q_REG_Q_0_12_MSK (((1U << MJPEG_Q_REG_Q_0_12_LEN) - 1) << MJPEG_Q_REG_Q_0_12_POS) -#define MJPEG_Q_REG_Q_0_12_UMSK (~(((1U << MJPEG_Q_REG_Q_0_12_LEN) - 1) << MJPEG_Q_REG_Q_0_12_POS)) -#define MJPEG_Q_REG_Q_0_13 MJPEG_Q_REG_Q_0_13 -#define MJPEG_Q_REG_Q_0_13_POS (16U) -#define MJPEG_Q_REG_Q_0_13_LEN (12U) -#define MJPEG_Q_REG_Q_0_13_MSK (((1U << MJPEG_Q_REG_Q_0_13_LEN) - 1) << MJPEG_Q_REG_Q_0_13_POS) -#define MJPEG_Q_REG_Q_0_13_UMSK (~(((1U << MJPEG_Q_REG_Q_0_13_LEN) - 1) << MJPEG_Q_REG_Q_0_13_POS)) - -/* 0x428 : mjpeg_q_param_14 */ -#define MJPEG_Q_PARAM_14_OFFSET (0x428) -#define MJPEG_Q_REG_Q_0_14 MJPEG_Q_REG_Q_0_14 -#define MJPEG_Q_REG_Q_0_14_POS (0U) -#define MJPEG_Q_REG_Q_0_14_LEN (12U) -#define MJPEG_Q_REG_Q_0_14_MSK (((1U << MJPEG_Q_REG_Q_0_14_LEN) - 1) << MJPEG_Q_REG_Q_0_14_POS) -#define MJPEG_Q_REG_Q_0_14_UMSK (~(((1U << MJPEG_Q_REG_Q_0_14_LEN) - 1) << MJPEG_Q_REG_Q_0_14_POS)) -#define MJPEG_Q_REG_Q_0_15 MJPEG_Q_REG_Q_0_15 -#define MJPEG_Q_REG_Q_0_15_POS (16U) -#define MJPEG_Q_REG_Q_0_15_LEN (12U) -#define MJPEG_Q_REG_Q_0_15_MSK (((1U << MJPEG_Q_REG_Q_0_15_LEN) - 1) << MJPEG_Q_REG_Q_0_15_POS) -#define MJPEG_Q_REG_Q_0_15_UMSK (~(((1U << MJPEG_Q_REG_Q_0_15_LEN) - 1) << MJPEG_Q_REG_Q_0_15_POS)) - -/* 0x42C : mjpeg_q_param_16 */ -#define MJPEG_Q_PARAM_16_OFFSET (0x42C) -#define MJPEG_Q_REG_Q_0_16 MJPEG_Q_REG_Q_0_16 -#define MJPEG_Q_REG_Q_0_16_POS (0U) -#define MJPEG_Q_REG_Q_0_16_LEN (12U) -#define MJPEG_Q_REG_Q_0_16_MSK (((1U << MJPEG_Q_REG_Q_0_16_LEN) - 1) << MJPEG_Q_REG_Q_0_16_POS) -#define MJPEG_Q_REG_Q_0_16_UMSK (~(((1U << MJPEG_Q_REG_Q_0_16_LEN) - 1) << MJPEG_Q_REG_Q_0_16_POS)) -#define MJPEG_Q_REG_Q_0_17 MJPEG_Q_REG_Q_0_17 -#define MJPEG_Q_REG_Q_0_17_POS (16U) -#define MJPEG_Q_REG_Q_0_17_LEN (12U) -#define MJPEG_Q_REG_Q_0_17_MSK (((1U << MJPEG_Q_REG_Q_0_17_LEN) - 1) << MJPEG_Q_REG_Q_0_17_POS) -#define MJPEG_Q_REG_Q_0_17_UMSK (~(((1U << MJPEG_Q_REG_Q_0_17_LEN) - 1) << MJPEG_Q_REG_Q_0_17_POS)) - -/* 0x430 : mjpeg_q_param_18 */ -#define MJPEG_Q_PARAM_18_OFFSET (0x430) -#define MJPEG_Q_REG_Q_0_18 MJPEG_Q_REG_Q_0_18 -#define MJPEG_Q_REG_Q_0_18_POS (0U) -#define MJPEG_Q_REG_Q_0_18_LEN (12U) -#define MJPEG_Q_REG_Q_0_18_MSK (((1U << MJPEG_Q_REG_Q_0_18_LEN) - 1) << MJPEG_Q_REG_Q_0_18_POS) -#define MJPEG_Q_REG_Q_0_18_UMSK (~(((1U << MJPEG_Q_REG_Q_0_18_LEN) - 1) << MJPEG_Q_REG_Q_0_18_POS)) -#define MJPEG_Q_REG_Q_0_19 MJPEG_Q_REG_Q_0_19 -#define MJPEG_Q_REG_Q_0_19_POS (16U) -#define MJPEG_Q_REG_Q_0_19_LEN (12U) -#define MJPEG_Q_REG_Q_0_19_MSK (((1U << MJPEG_Q_REG_Q_0_19_LEN) - 1) << MJPEG_Q_REG_Q_0_19_POS) -#define MJPEG_Q_REG_Q_0_19_UMSK (~(((1U << MJPEG_Q_REG_Q_0_19_LEN) - 1) << MJPEG_Q_REG_Q_0_19_POS)) - -/* 0x434 : mjpeg_q_param_1a */ -#define MJPEG_Q_PARAM_1A_OFFSET (0x434) -#define MJPEG_Q_REG_Q_0_1A MJPEG_Q_REG_Q_0_1A -#define MJPEG_Q_REG_Q_0_1A_POS (0U) -#define MJPEG_Q_REG_Q_0_1A_LEN (12U) -#define MJPEG_Q_REG_Q_0_1A_MSK (((1U << MJPEG_Q_REG_Q_0_1A_LEN) - 1) << MJPEG_Q_REG_Q_0_1A_POS) -#define MJPEG_Q_REG_Q_0_1A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1A_LEN) - 1) << MJPEG_Q_REG_Q_0_1A_POS)) -#define MJPEG_Q_REG_Q_0_1B MJPEG_Q_REG_Q_0_1B -#define MJPEG_Q_REG_Q_0_1B_POS (16U) -#define MJPEG_Q_REG_Q_0_1B_LEN (12U) -#define MJPEG_Q_REG_Q_0_1B_MSK (((1U << MJPEG_Q_REG_Q_0_1B_LEN) - 1) << MJPEG_Q_REG_Q_0_1B_POS) -#define MJPEG_Q_REG_Q_0_1B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1B_LEN) - 1) << MJPEG_Q_REG_Q_0_1B_POS)) - -/* 0x438 : mjpeg_q_param_1c */ -#define MJPEG_Q_PARAM_1C_OFFSET (0x438) -#define MJPEG_Q_REG_Q_0_1C MJPEG_Q_REG_Q_0_1C -#define MJPEG_Q_REG_Q_0_1C_POS (0U) -#define MJPEG_Q_REG_Q_0_1C_LEN (12U) -#define MJPEG_Q_REG_Q_0_1C_MSK (((1U << MJPEG_Q_REG_Q_0_1C_LEN) - 1) << MJPEG_Q_REG_Q_0_1C_POS) -#define MJPEG_Q_REG_Q_0_1C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1C_LEN) - 1) << MJPEG_Q_REG_Q_0_1C_POS)) -#define MJPEG_Q_REG_Q_0_1D MJPEG_Q_REG_Q_0_1D -#define MJPEG_Q_REG_Q_0_1D_POS (16U) -#define MJPEG_Q_REG_Q_0_1D_LEN (12U) -#define MJPEG_Q_REG_Q_0_1D_MSK (((1U << MJPEG_Q_REG_Q_0_1D_LEN) - 1) << MJPEG_Q_REG_Q_0_1D_POS) -#define MJPEG_Q_REG_Q_0_1D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1D_LEN) - 1) << MJPEG_Q_REG_Q_0_1D_POS)) - -/* 0x43C : mjpeg_q_param_1e */ -#define MJPEG_Q_PARAM_1E_OFFSET (0x43C) -#define MJPEG_Q_REG_Q_0_1E MJPEG_Q_REG_Q_0_1E -#define MJPEG_Q_REG_Q_0_1E_POS (0U) -#define MJPEG_Q_REG_Q_0_1E_LEN (12U) -#define MJPEG_Q_REG_Q_0_1E_MSK (((1U << MJPEG_Q_REG_Q_0_1E_LEN) - 1) << MJPEG_Q_REG_Q_0_1E_POS) -#define MJPEG_Q_REG_Q_0_1E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1E_LEN) - 1) << MJPEG_Q_REG_Q_0_1E_POS)) -#define MJPEG_Q_REG_Q_0_1F MJPEG_Q_REG_Q_0_1F -#define MJPEG_Q_REG_Q_0_1F_POS (16U) -#define MJPEG_Q_REG_Q_0_1F_LEN (12U) -#define MJPEG_Q_REG_Q_0_1F_MSK (((1U << MJPEG_Q_REG_Q_0_1F_LEN) - 1) << MJPEG_Q_REG_Q_0_1F_POS) -#define MJPEG_Q_REG_Q_0_1F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_1F_LEN) - 1) << MJPEG_Q_REG_Q_0_1F_POS)) - -/* 0x440 : mjpeg_q_param_20 */ -#define MJPEG_Q_PARAM_20_OFFSET (0x440) -#define MJPEG_Q_REG_Q_0_20 MJPEG_Q_REG_Q_0_20 -#define MJPEG_Q_REG_Q_0_20_POS (0U) -#define MJPEG_Q_REG_Q_0_20_LEN (12U) -#define MJPEG_Q_REG_Q_0_20_MSK (((1U << MJPEG_Q_REG_Q_0_20_LEN) - 1) << MJPEG_Q_REG_Q_0_20_POS) -#define MJPEG_Q_REG_Q_0_20_UMSK (~(((1U << MJPEG_Q_REG_Q_0_20_LEN) - 1) << MJPEG_Q_REG_Q_0_20_POS)) -#define MJPEG_Q_REG_Q_0_21 MJPEG_Q_REG_Q_0_21 -#define MJPEG_Q_REG_Q_0_21_POS (16U) -#define MJPEG_Q_REG_Q_0_21_LEN (12U) -#define MJPEG_Q_REG_Q_0_21_MSK (((1U << MJPEG_Q_REG_Q_0_21_LEN) - 1) << MJPEG_Q_REG_Q_0_21_POS) -#define MJPEG_Q_REG_Q_0_21_UMSK (~(((1U << MJPEG_Q_REG_Q_0_21_LEN) - 1) << MJPEG_Q_REG_Q_0_21_POS)) - -/* 0x444 : mjpeg_q_param_22 */ -#define MJPEG_Q_PARAM_22_OFFSET (0x444) -#define MJPEG_Q_REG_Q_0_22 MJPEG_Q_REG_Q_0_22 -#define MJPEG_Q_REG_Q_0_22_POS (0U) -#define MJPEG_Q_REG_Q_0_22_LEN (12U) -#define MJPEG_Q_REG_Q_0_22_MSK (((1U << MJPEG_Q_REG_Q_0_22_LEN) - 1) << MJPEG_Q_REG_Q_0_22_POS) -#define MJPEG_Q_REG_Q_0_22_UMSK (~(((1U << MJPEG_Q_REG_Q_0_22_LEN) - 1) << MJPEG_Q_REG_Q_0_22_POS)) -#define MJPEG_Q_REG_Q_0_23 MJPEG_Q_REG_Q_0_23 -#define MJPEG_Q_REG_Q_0_23_POS (16U) -#define MJPEG_Q_REG_Q_0_23_LEN (12U) -#define MJPEG_Q_REG_Q_0_23_MSK (((1U << MJPEG_Q_REG_Q_0_23_LEN) - 1) << MJPEG_Q_REG_Q_0_23_POS) -#define MJPEG_Q_REG_Q_0_23_UMSK (~(((1U << MJPEG_Q_REG_Q_0_23_LEN) - 1) << MJPEG_Q_REG_Q_0_23_POS)) - -/* 0x448 : mjpeg_q_param_24 */ -#define MJPEG_Q_PARAM_24_OFFSET (0x448) -#define MJPEG_Q_REG_Q_0_24 MJPEG_Q_REG_Q_0_24 -#define MJPEG_Q_REG_Q_0_24_POS (0U) -#define MJPEG_Q_REG_Q_0_24_LEN (12U) -#define MJPEG_Q_REG_Q_0_24_MSK (((1U << MJPEG_Q_REG_Q_0_24_LEN) - 1) << MJPEG_Q_REG_Q_0_24_POS) -#define MJPEG_Q_REG_Q_0_24_UMSK (~(((1U << MJPEG_Q_REG_Q_0_24_LEN) - 1) << MJPEG_Q_REG_Q_0_24_POS)) -#define MJPEG_Q_REG_Q_0_25 MJPEG_Q_REG_Q_0_25 -#define MJPEG_Q_REG_Q_0_25_POS (16U) -#define MJPEG_Q_REG_Q_0_25_LEN (12U) -#define MJPEG_Q_REG_Q_0_25_MSK (((1U << MJPEG_Q_REG_Q_0_25_LEN) - 1) << MJPEG_Q_REG_Q_0_25_POS) -#define MJPEG_Q_REG_Q_0_25_UMSK (~(((1U << MJPEG_Q_REG_Q_0_25_LEN) - 1) << MJPEG_Q_REG_Q_0_25_POS)) - -/* 0x44C : mjpeg_q_param_26 */ -#define MJPEG_Q_PARAM_26_OFFSET (0x44C) -#define MJPEG_Q_REG_Q_0_26 MJPEG_Q_REG_Q_0_26 -#define MJPEG_Q_REG_Q_0_26_POS (0U) -#define MJPEG_Q_REG_Q_0_26_LEN (12U) -#define MJPEG_Q_REG_Q_0_26_MSK (((1U << MJPEG_Q_REG_Q_0_26_LEN) - 1) << MJPEG_Q_REG_Q_0_26_POS) -#define MJPEG_Q_REG_Q_0_26_UMSK (~(((1U << MJPEG_Q_REG_Q_0_26_LEN) - 1) << MJPEG_Q_REG_Q_0_26_POS)) -#define MJPEG_Q_REG_Q_0_27 MJPEG_Q_REG_Q_0_27 -#define MJPEG_Q_REG_Q_0_27_POS (16U) -#define MJPEG_Q_REG_Q_0_27_LEN (12U) -#define MJPEG_Q_REG_Q_0_27_MSK (((1U << MJPEG_Q_REG_Q_0_27_LEN) - 1) << MJPEG_Q_REG_Q_0_27_POS) -#define MJPEG_Q_REG_Q_0_27_UMSK (~(((1U << MJPEG_Q_REG_Q_0_27_LEN) - 1) << MJPEG_Q_REG_Q_0_27_POS)) - -/* 0x450 : mjpeg_q_param_28 */ -#define MJPEG_Q_PARAM_28_OFFSET (0x450) -#define MJPEG_Q_REG_Q_0_28 MJPEG_Q_REG_Q_0_28 -#define MJPEG_Q_REG_Q_0_28_POS (0U) -#define MJPEG_Q_REG_Q_0_28_LEN (12U) -#define MJPEG_Q_REG_Q_0_28_MSK (((1U << MJPEG_Q_REG_Q_0_28_LEN) - 1) << MJPEG_Q_REG_Q_0_28_POS) -#define MJPEG_Q_REG_Q_0_28_UMSK (~(((1U << MJPEG_Q_REG_Q_0_28_LEN) - 1) << MJPEG_Q_REG_Q_0_28_POS)) -#define MJPEG_Q_REG_Q_0_29 MJPEG_Q_REG_Q_0_29 -#define MJPEG_Q_REG_Q_0_29_POS (16U) -#define MJPEG_Q_REG_Q_0_29_LEN (12U) -#define MJPEG_Q_REG_Q_0_29_MSK (((1U << MJPEG_Q_REG_Q_0_29_LEN) - 1) << MJPEG_Q_REG_Q_0_29_POS) -#define MJPEG_Q_REG_Q_0_29_UMSK (~(((1U << MJPEG_Q_REG_Q_0_29_LEN) - 1) << MJPEG_Q_REG_Q_0_29_POS)) - -/* 0x454 : mjpeg_q_param_2a */ -#define MJPEG_Q_PARAM_2A_OFFSET (0x454) -#define MJPEG_Q_REG_Q_0_2A MJPEG_Q_REG_Q_0_2A -#define MJPEG_Q_REG_Q_0_2A_POS (0U) -#define MJPEG_Q_REG_Q_0_2A_LEN (12U) -#define MJPEG_Q_REG_Q_0_2A_MSK (((1U << MJPEG_Q_REG_Q_0_2A_LEN) - 1) << MJPEG_Q_REG_Q_0_2A_POS) -#define MJPEG_Q_REG_Q_0_2A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2A_LEN) - 1) << MJPEG_Q_REG_Q_0_2A_POS)) -#define MJPEG_Q_REG_Q_0_2B MJPEG_Q_REG_Q_0_2B -#define MJPEG_Q_REG_Q_0_2B_POS (16U) -#define MJPEG_Q_REG_Q_0_2B_LEN (12U) -#define MJPEG_Q_REG_Q_0_2B_MSK (((1U << MJPEG_Q_REG_Q_0_2B_LEN) - 1) << MJPEG_Q_REG_Q_0_2B_POS) -#define MJPEG_Q_REG_Q_0_2B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2B_LEN) - 1) << MJPEG_Q_REG_Q_0_2B_POS)) - -/* 0x458 : mjpeg_q_param_2c */ -#define MJPEG_Q_PARAM_2C_OFFSET (0x458) -#define MJPEG_Q_REG_Q_0_2C MJPEG_Q_REG_Q_0_2C -#define MJPEG_Q_REG_Q_0_2C_POS (0U) -#define MJPEG_Q_REG_Q_0_2C_LEN (12U) -#define MJPEG_Q_REG_Q_0_2C_MSK (((1U << MJPEG_Q_REG_Q_0_2C_LEN) - 1) << MJPEG_Q_REG_Q_0_2C_POS) -#define MJPEG_Q_REG_Q_0_2C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2C_LEN) - 1) << MJPEG_Q_REG_Q_0_2C_POS)) -#define MJPEG_Q_REG_Q_0_2D MJPEG_Q_REG_Q_0_2D -#define MJPEG_Q_REG_Q_0_2D_POS (16U) -#define MJPEG_Q_REG_Q_0_2D_LEN (12U) -#define MJPEG_Q_REG_Q_0_2D_MSK (((1U << MJPEG_Q_REG_Q_0_2D_LEN) - 1) << MJPEG_Q_REG_Q_0_2D_POS) -#define MJPEG_Q_REG_Q_0_2D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2D_LEN) - 1) << MJPEG_Q_REG_Q_0_2D_POS)) - -/* 0x45C : mjpeg_q_param_2e */ -#define MJPEG_Q_PARAM_2E_OFFSET (0x45C) -#define MJPEG_Q_REG_Q_0_2E MJPEG_Q_REG_Q_0_2E -#define MJPEG_Q_REG_Q_0_2E_POS (0U) -#define MJPEG_Q_REG_Q_0_2E_LEN (12U) -#define MJPEG_Q_REG_Q_0_2E_MSK (((1U << MJPEG_Q_REG_Q_0_2E_LEN) - 1) << MJPEG_Q_REG_Q_0_2E_POS) -#define MJPEG_Q_REG_Q_0_2E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2E_LEN) - 1) << MJPEG_Q_REG_Q_0_2E_POS)) -#define MJPEG_Q_REG_Q_0_2F MJPEG_Q_REG_Q_0_2F -#define MJPEG_Q_REG_Q_0_2F_POS (16U) -#define MJPEG_Q_REG_Q_0_2F_LEN (12U) -#define MJPEG_Q_REG_Q_0_2F_MSK (((1U << MJPEG_Q_REG_Q_0_2F_LEN) - 1) << MJPEG_Q_REG_Q_0_2F_POS) -#define MJPEG_Q_REG_Q_0_2F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_2F_LEN) - 1) << MJPEG_Q_REG_Q_0_2F_POS)) - -/* 0x460 : mjpeg_q_param_30 */ -#define MJPEG_Q_PARAM_30_OFFSET (0x460) -#define MJPEG_Q_REG_Q_0_30 MJPEG_Q_REG_Q_0_30 -#define MJPEG_Q_REG_Q_0_30_POS (0U) -#define MJPEG_Q_REG_Q_0_30_LEN (12U) -#define MJPEG_Q_REG_Q_0_30_MSK (((1U << MJPEG_Q_REG_Q_0_30_LEN) - 1) << MJPEG_Q_REG_Q_0_30_POS) -#define MJPEG_Q_REG_Q_0_30_UMSK (~(((1U << MJPEG_Q_REG_Q_0_30_LEN) - 1) << MJPEG_Q_REG_Q_0_30_POS)) -#define MJPEG_Q_REG_Q_0_31 MJPEG_Q_REG_Q_0_31 -#define MJPEG_Q_REG_Q_0_31_POS (16U) -#define MJPEG_Q_REG_Q_0_31_LEN (12U) -#define MJPEG_Q_REG_Q_0_31_MSK (((1U << MJPEG_Q_REG_Q_0_31_LEN) - 1) << MJPEG_Q_REG_Q_0_31_POS) -#define MJPEG_Q_REG_Q_0_31_UMSK (~(((1U << MJPEG_Q_REG_Q_0_31_LEN) - 1) << MJPEG_Q_REG_Q_0_31_POS)) - -/* 0x464 : mjpeg_q_param_32 */ -#define MJPEG_Q_PARAM_32_OFFSET (0x464) -#define MJPEG_Q_REG_Q_0_32 MJPEG_Q_REG_Q_0_32 -#define MJPEG_Q_REG_Q_0_32_POS (0U) -#define MJPEG_Q_REG_Q_0_32_LEN (12U) -#define MJPEG_Q_REG_Q_0_32_MSK (((1U << MJPEG_Q_REG_Q_0_32_LEN) - 1) << MJPEG_Q_REG_Q_0_32_POS) -#define MJPEG_Q_REG_Q_0_32_UMSK (~(((1U << MJPEG_Q_REG_Q_0_32_LEN) - 1) << MJPEG_Q_REG_Q_0_32_POS)) -#define MJPEG_Q_REG_Q_0_33 MJPEG_Q_REG_Q_0_33 -#define MJPEG_Q_REG_Q_0_33_POS (16U) -#define MJPEG_Q_REG_Q_0_33_LEN (12U) -#define MJPEG_Q_REG_Q_0_33_MSK (((1U << MJPEG_Q_REG_Q_0_33_LEN) - 1) << MJPEG_Q_REG_Q_0_33_POS) -#define MJPEG_Q_REG_Q_0_33_UMSK (~(((1U << MJPEG_Q_REG_Q_0_33_LEN) - 1) << MJPEG_Q_REG_Q_0_33_POS)) - -/* 0x468 : mjpeg_q_param_34 */ -#define MJPEG_Q_PARAM_34_OFFSET (0x468) -#define MJPEG_Q_REG_Q_0_34 MJPEG_Q_REG_Q_0_34 -#define MJPEG_Q_REG_Q_0_34_POS (0U) -#define MJPEG_Q_REG_Q_0_34_LEN (12U) -#define MJPEG_Q_REG_Q_0_34_MSK (((1U << MJPEG_Q_REG_Q_0_34_LEN) - 1) << MJPEG_Q_REG_Q_0_34_POS) -#define MJPEG_Q_REG_Q_0_34_UMSK (~(((1U << MJPEG_Q_REG_Q_0_34_LEN) - 1) << MJPEG_Q_REG_Q_0_34_POS)) -#define MJPEG_Q_REG_Q_0_35 MJPEG_Q_REG_Q_0_35 -#define MJPEG_Q_REG_Q_0_35_POS (16U) -#define MJPEG_Q_REG_Q_0_35_LEN (12U) -#define MJPEG_Q_REG_Q_0_35_MSK (((1U << MJPEG_Q_REG_Q_0_35_LEN) - 1) << MJPEG_Q_REG_Q_0_35_POS) -#define MJPEG_Q_REG_Q_0_35_UMSK (~(((1U << MJPEG_Q_REG_Q_0_35_LEN) - 1) << MJPEG_Q_REG_Q_0_35_POS)) - -/* 0x46C : mjpeg_q_param_36 */ -#define MJPEG_Q_PARAM_36_OFFSET (0x46C) -#define MJPEG_Q_REG_Q_0_36 MJPEG_Q_REG_Q_0_36 -#define MJPEG_Q_REG_Q_0_36_POS (0U) -#define MJPEG_Q_REG_Q_0_36_LEN (12U) -#define MJPEG_Q_REG_Q_0_36_MSK (((1U << MJPEG_Q_REG_Q_0_36_LEN) - 1) << MJPEG_Q_REG_Q_0_36_POS) -#define MJPEG_Q_REG_Q_0_36_UMSK (~(((1U << MJPEG_Q_REG_Q_0_36_LEN) - 1) << MJPEG_Q_REG_Q_0_36_POS)) -#define MJPEG_Q_REG_Q_0_37 MJPEG_Q_REG_Q_0_37 -#define MJPEG_Q_REG_Q_0_37_POS (16U) -#define MJPEG_Q_REG_Q_0_37_LEN (12U) -#define MJPEG_Q_REG_Q_0_37_MSK (((1U << MJPEG_Q_REG_Q_0_37_LEN) - 1) << MJPEG_Q_REG_Q_0_37_POS) -#define MJPEG_Q_REG_Q_0_37_UMSK (~(((1U << MJPEG_Q_REG_Q_0_37_LEN) - 1) << MJPEG_Q_REG_Q_0_37_POS)) - -/* 0x470 : mjpeg_q_param_38 */ -#define MJPEG_Q_PARAM_38_OFFSET (0x470) -#define MJPEG_Q_REG_Q_0_38 MJPEG_Q_REG_Q_0_38 -#define MJPEG_Q_REG_Q_0_38_POS (0U) -#define MJPEG_Q_REG_Q_0_38_LEN (12U) -#define MJPEG_Q_REG_Q_0_38_MSK (((1U << MJPEG_Q_REG_Q_0_38_LEN) - 1) << MJPEG_Q_REG_Q_0_38_POS) -#define MJPEG_Q_REG_Q_0_38_UMSK (~(((1U << MJPEG_Q_REG_Q_0_38_LEN) - 1) << MJPEG_Q_REG_Q_0_38_POS)) -#define MJPEG_Q_REG_Q_0_39 MJPEG_Q_REG_Q_0_39 -#define MJPEG_Q_REG_Q_0_39_POS (16U) -#define MJPEG_Q_REG_Q_0_39_LEN (12U) -#define MJPEG_Q_REG_Q_0_39_MSK (((1U << MJPEG_Q_REG_Q_0_39_LEN) - 1) << MJPEG_Q_REG_Q_0_39_POS) -#define MJPEG_Q_REG_Q_0_39_UMSK (~(((1U << MJPEG_Q_REG_Q_0_39_LEN) - 1) << MJPEG_Q_REG_Q_0_39_POS)) - -/* 0x474 : mjpeg_q_param_3a */ -#define MJPEG_Q_PARAM_3A_OFFSET (0x474) -#define MJPEG_Q_REG_Q_0_3A MJPEG_Q_REG_Q_0_3A -#define MJPEG_Q_REG_Q_0_3A_POS (0U) -#define MJPEG_Q_REG_Q_0_3A_LEN (12U) -#define MJPEG_Q_REG_Q_0_3A_MSK (((1U << MJPEG_Q_REG_Q_0_3A_LEN) - 1) << MJPEG_Q_REG_Q_0_3A_POS) -#define MJPEG_Q_REG_Q_0_3A_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3A_LEN) - 1) << MJPEG_Q_REG_Q_0_3A_POS)) -#define MJPEG_Q_REG_Q_0_3B MJPEG_Q_REG_Q_0_3B -#define MJPEG_Q_REG_Q_0_3B_POS (16U) -#define MJPEG_Q_REG_Q_0_3B_LEN (12U) -#define MJPEG_Q_REG_Q_0_3B_MSK (((1U << MJPEG_Q_REG_Q_0_3B_LEN) - 1) << MJPEG_Q_REG_Q_0_3B_POS) -#define MJPEG_Q_REG_Q_0_3B_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3B_LEN) - 1) << MJPEG_Q_REG_Q_0_3B_POS)) - -/* 0x478 : mjpeg_q_param_3c */ -#define MJPEG_Q_PARAM_3C_OFFSET (0x478) -#define MJPEG_Q_REG_Q_0_3C MJPEG_Q_REG_Q_0_3C -#define MJPEG_Q_REG_Q_0_3C_POS (0U) -#define MJPEG_Q_REG_Q_0_3C_LEN (12U) -#define MJPEG_Q_REG_Q_0_3C_MSK (((1U << MJPEG_Q_REG_Q_0_3C_LEN) - 1) << MJPEG_Q_REG_Q_0_3C_POS) -#define MJPEG_Q_REG_Q_0_3C_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3C_LEN) - 1) << MJPEG_Q_REG_Q_0_3C_POS)) -#define MJPEG_Q_REG_Q_0_3D MJPEG_Q_REG_Q_0_3D -#define MJPEG_Q_REG_Q_0_3D_POS (16U) -#define MJPEG_Q_REG_Q_0_3D_LEN (12U) -#define MJPEG_Q_REG_Q_0_3D_MSK (((1U << MJPEG_Q_REG_Q_0_3D_LEN) - 1) << MJPEG_Q_REG_Q_0_3D_POS) -#define MJPEG_Q_REG_Q_0_3D_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3D_LEN) - 1) << MJPEG_Q_REG_Q_0_3D_POS)) - -/* 0x47C : mjpeg_q_param_3e */ -#define MJPEG_Q_PARAM_3E_OFFSET (0x47C) -#define MJPEG_Q_REG_Q_0_3E MJPEG_Q_REG_Q_0_3E -#define MJPEG_Q_REG_Q_0_3E_POS (0U) -#define MJPEG_Q_REG_Q_0_3E_LEN (12U) -#define MJPEG_Q_REG_Q_0_3E_MSK (((1U << MJPEG_Q_REG_Q_0_3E_LEN) - 1) << MJPEG_Q_REG_Q_0_3E_POS) -#define MJPEG_Q_REG_Q_0_3E_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3E_LEN) - 1) << MJPEG_Q_REG_Q_0_3E_POS)) -#define MJPEG_Q_REG_Q_0_3F MJPEG_Q_REG_Q_0_3F -#define MJPEG_Q_REG_Q_0_3F_POS (16U) -#define MJPEG_Q_REG_Q_0_3F_LEN (12U) -#define MJPEG_Q_REG_Q_0_3F_MSK (((1U << MJPEG_Q_REG_Q_0_3F_LEN) - 1) << MJPEG_Q_REG_Q_0_3F_POS) -#define MJPEG_Q_REG_Q_0_3F_UMSK (~(((1U << MJPEG_Q_REG_Q_0_3F_LEN) - 1) << MJPEG_Q_REG_Q_0_3F_POS)) - -/* 0x480 : mjpeg_q_param_40 */ -#define MJPEG_Q_PARAM_40_OFFSET (0x480) -#define MJPEG_Q_REG_Q_1_00 MJPEG_Q_REG_Q_1_00 -#define MJPEG_Q_REG_Q_1_00_POS (0U) -#define MJPEG_Q_REG_Q_1_00_LEN (12U) -#define MJPEG_Q_REG_Q_1_00_MSK (((1U << MJPEG_Q_REG_Q_1_00_LEN) - 1) << MJPEG_Q_REG_Q_1_00_POS) -#define MJPEG_Q_REG_Q_1_00_UMSK (~(((1U << MJPEG_Q_REG_Q_1_00_LEN) - 1) << MJPEG_Q_REG_Q_1_00_POS)) -#define MJPEG_Q_REG_Q_1_01 MJPEG_Q_REG_Q_1_01 -#define MJPEG_Q_REG_Q_1_01_POS (16U) -#define MJPEG_Q_REG_Q_1_01_LEN (12U) -#define MJPEG_Q_REG_Q_1_01_MSK (((1U << MJPEG_Q_REG_Q_1_01_LEN) - 1) << MJPEG_Q_REG_Q_1_01_POS) -#define MJPEG_Q_REG_Q_1_01_UMSK (~(((1U << MJPEG_Q_REG_Q_1_01_LEN) - 1) << MJPEG_Q_REG_Q_1_01_POS)) - -/* 0x484 : mjpeg_q_param_42 */ -#define MJPEG_Q_PARAM_42_OFFSET (0x484) -#define MJPEG_Q_REG_Q_1_02 MJPEG_Q_REG_Q_1_02 -#define MJPEG_Q_REG_Q_1_02_POS (0U) -#define MJPEG_Q_REG_Q_1_02_LEN (12U) -#define MJPEG_Q_REG_Q_1_02_MSK (((1U << MJPEG_Q_REG_Q_1_02_LEN) - 1) << MJPEG_Q_REG_Q_1_02_POS) -#define MJPEG_Q_REG_Q_1_02_UMSK (~(((1U << MJPEG_Q_REG_Q_1_02_LEN) - 1) << MJPEG_Q_REG_Q_1_02_POS)) -#define MJPEG_Q_REG_Q_1_03 MJPEG_Q_REG_Q_1_03 -#define MJPEG_Q_REG_Q_1_03_POS (16U) -#define MJPEG_Q_REG_Q_1_03_LEN (12U) -#define MJPEG_Q_REG_Q_1_03_MSK (((1U << MJPEG_Q_REG_Q_1_03_LEN) - 1) << MJPEG_Q_REG_Q_1_03_POS) -#define MJPEG_Q_REG_Q_1_03_UMSK (~(((1U << MJPEG_Q_REG_Q_1_03_LEN) - 1) << MJPEG_Q_REG_Q_1_03_POS)) - -/* 0x488 : mjpeg_q_param_44 */ -#define MJPEG_Q_PARAM_44_OFFSET (0x488) -#define MJPEG_Q_REG_Q_1_04 MJPEG_Q_REG_Q_1_04 -#define MJPEG_Q_REG_Q_1_04_POS (0U) -#define MJPEG_Q_REG_Q_1_04_LEN (12U) -#define MJPEG_Q_REG_Q_1_04_MSK (((1U << MJPEG_Q_REG_Q_1_04_LEN) - 1) << MJPEG_Q_REG_Q_1_04_POS) -#define MJPEG_Q_REG_Q_1_04_UMSK (~(((1U << MJPEG_Q_REG_Q_1_04_LEN) - 1) << MJPEG_Q_REG_Q_1_04_POS)) -#define MJPEG_Q_REG_Q_1_05 MJPEG_Q_REG_Q_1_05 -#define MJPEG_Q_REG_Q_1_05_POS (16U) -#define MJPEG_Q_REG_Q_1_05_LEN (12U) -#define MJPEG_Q_REG_Q_1_05_MSK (((1U << MJPEG_Q_REG_Q_1_05_LEN) - 1) << MJPEG_Q_REG_Q_1_05_POS) -#define MJPEG_Q_REG_Q_1_05_UMSK (~(((1U << MJPEG_Q_REG_Q_1_05_LEN) - 1) << MJPEG_Q_REG_Q_1_05_POS)) - -/* 0x48C : mjpeg_q_param_46 */ -#define MJPEG_Q_PARAM_46_OFFSET (0x48C) -#define MJPEG_Q_REG_Q_1_06 MJPEG_Q_REG_Q_1_06 -#define MJPEG_Q_REG_Q_1_06_POS (0U) -#define MJPEG_Q_REG_Q_1_06_LEN (12U) -#define MJPEG_Q_REG_Q_1_06_MSK (((1U << MJPEG_Q_REG_Q_1_06_LEN) - 1) << MJPEG_Q_REG_Q_1_06_POS) -#define MJPEG_Q_REG_Q_1_06_UMSK (~(((1U << MJPEG_Q_REG_Q_1_06_LEN) - 1) << MJPEG_Q_REG_Q_1_06_POS)) -#define MJPEG_Q_REG_Q_1_07 MJPEG_Q_REG_Q_1_07 -#define MJPEG_Q_REG_Q_1_07_POS (16U) -#define MJPEG_Q_REG_Q_1_07_LEN (12U) -#define MJPEG_Q_REG_Q_1_07_MSK (((1U << MJPEG_Q_REG_Q_1_07_LEN) - 1) << MJPEG_Q_REG_Q_1_07_POS) -#define MJPEG_Q_REG_Q_1_07_UMSK (~(((1U << MJPEG_Q_REG_Q_1_07_LEN) - 1) << MJPEG_Q_REG_Q_1_07_POS)) - -/* 0x490 : mjpeg_q_param_48 */ -#define MJPEG_Q_PARAM_48_OFFSET (0x490) -#define MJPEG_Q_REG_Q_1_08 MJPEG_Q_REG_Q_1_08 -#define MJPEG_Q_REG_Q_1_08_POS (0U) -#define MJPEG_Q_REG_Q_1_08_LEN (12U) -#define MJPEG_Q_REG_Q_1_08_MSK (((1U << MJPEG_Q_REG_Q_1_08_LEN) - 1) << MJPEG_Q_REG_Q_1_08_POS) -#define MJPEG_Q_REG_Q_1_08_UMSK (~(((1U << MJPEG_Q_REG_Q_1_08_LEN) - 1) << MJPEG_Q_REG_Q_1_08_POS)) -#define MJPEG_Q_REG_Q_1_09 MJPEG_Q_REG_Q_1_09 -#define MJPEG_Q_REG_Q_1_09_POS (16U) -#define MJPEG_Q_REG_Q_1_09_LEN (12U) -#define MJPEG_Q_REG_Q_1_09_MSK (((1U << MJPEG_Q_REG_Q_1_09_LEN) - 1) << MJPEG_Q_REG_Q_1_09_POS) -#define MJPEG_Q_REG_Q_1_09_UMSK (~(((1U << MJPEG_Q_REG_Q_1_09_LEN) - 1) << MJPEG_Q_REG_Q_1_09_POS)) - -/* 0x494 : mjpeg_q_param_4a */ -#define MJPEG_Q_PARAM_4A_OFFSET (0x494) -#define MJPEG_Q_REG_Q_1_0A MJPEG_Q_REG_Q_1_0A -#define MJPEG_Q_REG_Q_1_0A_POS (0U) -#define MJPEG_Q_REG_Q_1_0A_LEN (12U) -#define MJPEG_Q_REG_Q_1_0A_MSK (((1U << MJPEG_Q_REG_Q_1_0A_LEN) - 1) << MJPEG_Q_REG_Q_1_0A_POS) -#define MJPEG_Q_REG_Q_1_0A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0A_LEN) - 1) << MJPEG_Q_REG_Q_1_0A_POS)) -#define MJPEG_Q_REG_Q_1_0B MJPEG_Q_REG_Q_1_0B -#define MJPEG_Q_REG_Q_1_0B_POS (16U) -#define MJPEG_Q_REG_Q_1_0B_LEN (12U) -#define MJPEG_Q_REG_Q_1_0B_MSK (((1U << MJPEG_Q_REG_Q_1_0B_LEN) - 1) << MJPEG_Q_REG_Q_1_0B_POS) -#define MJPEG_Q_REG_Q_1_0B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0B_LEN) - 1) << MJPEG_Q_REG_Q_1_0B_POS)) - -/* 0x498 : mjpeg_q_param_4c */ -#define MJPEG_Q_PARAM_4C_OFFSET (0x498) -#define MJPEG_Q_REG_Q_1_0C MJPEG_Q_REG_Q_1_0C -#define MJPEG_Q_REG_Q_1_0C_POS (0U) -#define MJPEG_Q_REG_Q_1_0C_LEN (12U) -#define MJPEG_Q_REG_Q_1_0C_MSK (((1U << MJPEG_Q_REG_Q_1_0C_LEN) - 1) << MJPEG_Q_REG_Q_1_0C_POS) -#define MJPEG_Q_REG_Q_1_0C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0C_LEN) - 1) << MJPEG_Q_REG_Q_1_0C_POS)) -#define MJPEG_Q_REG_Q_1_0D MJPEG_Q_REG_Q_1_0D -#define MJPEG_Q_REG_Q_1_0D_POS (16U) -#define MJPEG_Q_REG_Q_1_0D_LEN (12U) -#define MJPEG_Q_REG_Q_1_0D_MSK (((1U << MJPEG_Q_REG_Q_1_0D_LEN) - 1) << MJPEG_Q_REG_Q_1_0D_POS) -#define MJPEG_Q_REG_Q_1_0D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0D_LEN) - 1) << MJPEG_Q_REG_Q_1_0D_POS)) - -/* 0x49C : mjpeg_q_param_4e */ -#define MJPEG_Q_PARAM_4E_OFFSET (0x49C) -#define MJPEG_Q_REG_Q_1_0E MJPEG_Q_REG_Q_1_0E -#define MJPEG_Q_REG_Q_1_0E_POS (0U) -#define MJPEG_Q_REG_Q_1_0E_LEN (12U) -#define MJPEG_Q_REG_Q_1_0E_MSK (((1U << MJPEG_Q_REG_Q_1_0E_LEN) - 1) << MJPEG_Q_REG_Q_1_0E_POS) -#define MJPEG_Q_REG_Q_1_0E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0E_LEN) - 1) << MJPEG_Q_REG_Q_1_0E_POS)) -#define MJPEG_Q_REG_Q_1_0F MJPEG_Q_REG_Q_1_0F -#define MJPEG_Q_REG_Q_1_0F_POS (16U) -#define MJPEG_Q_REG_Q_1_0F_LEN (12U) -#define MJPEG_Q_REG_Q_1_0F_MSK (((1U << MJPEG_Q_REG_Q_1_0F_LEN) - 1) << MJPEG_Q_REG_Q_1_0F_POS) -#define MJPEG_Q_REG_Q_1_0F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_0F_LEN) - 1) << MJPEG_Q_REG_Q_1_0F_POS)) - -/* 0x4A0 : mjpeg_q_param_50 */ -#define MJPEG_Q_PARAM_50_OFFSET (0x4A0) -#define MJPEG_Q_REG_Q_1_10 MJPEG_Q_REG_Q_1_10 -#define MJPEG_Q_REG_Q_1_10_POS (0U) -#define MJPEG_Q_REG_Q_1_10_LEN (12U) -#define MJPEG_Q_REG_Q_1_10_MSK (((1U << MJPEG_Q_REG_Q_1_10_LEN) - 1) << MJPEG_Q_REG_Q_1_10_POS) -#define MJPEG_Q_REG_Q_1_10_UMSK (~(((1U << MJPEG_Q_REG_Q_1_10_LEN) - 1) << MJPEG_Q_REG_Q_1_10_POS)) -#define MJPEG_Q_REG_Q_1_11 MJPEG_Q_REG_Q_1_11 -#define MJPEG_Q_REG_Q_1_11_POS (16U) -#define MJPEG_Q_REG_Q_1_11_LEN (12U) -#define MJPEG_Q_REG_Q_1_11_MSK (((1U << MJPEG_Q_REG_Q_1_11_LEN) - 1) << MJPEG_Q_REG_Q_1_11_POS) -#define MJPEG_Q_REG_Q_1_11_UMSK (~(((1U << MJPEG_Q_REG_Q_1_11_LEN) - 1) << MJPEG_Q_REG_Q_1_11_POS)) - -/* 0x4A4 : mjpeg_q_param_52 */ -#define MJPEG_Q_PARAM_52_OFFSET (0x4A4) -#define MJPEG_Q_REG_Q_1_12 MJPEG_Q_REG_Q_1_12 -#define MJPEG_Q_REG_Q_1_12_POS (0U) -#define MJPEG_Q_REG_Q_1_12_LEN (12U) -#define MJPEG_Q_REG_Q_1_12_MSK (((1U << MJPEG_Q_REG_Q_1_12_LEN) - 1) << MJPEG_Q_REG_Q_1_12_POS) -#define MJPEG_Q_REG_Q_1_12_UMSK (~(((1U << MJPEG_Q_REG_Q_1_12_LEN) - 1) << MJPEG_Q_REG_Q_1_12_POS)) -#define MJPEG_Q_REG_Q_1_13 MJPEG_Q_REG_Q_1_13 -#define MJPEG_Q_REG_Q_1_13_POS (16U) -#define MJPEG_Q_REG_Q_1_13_LEN (12U) -#define MJPEG_Q_REG_Q_1_13_MSK (((1U << MJPEG_Q_REG_Q_1_13_LEN) - 1) << MJPEG_Q_REG_Q_1_13_POS) -#define MJPEG_Q_REG_Q_1_13_UMSK (~(((1U << MJPEG_Q_REG_Q_1_13_LEN) - 1) << MJPEG_Q_REG_Q_1_13_POS)) - -/* 0x4A8 : mjpeg_q_param_54 */ -#define MJPEG_Q_PARAM_54_OFFSET (0x4A8) -#define MJPEG_Q_REG_Q_1_14 MJPEG_Q_REG_Q_1_14 -#define MJPEG_Q_REG_Q_1_14_POS (0U) -#define MJPEG_Q_REG_Q_1_14_LEN (12U) -#define MJPEG_Q_REG_Q_1_14_MSK (((1U << MJPEG_Q_REG_Q_1_14_LEN) - 1) << MJPEG_Q_REG_Q_1_14_POS) -#define MJPEG_Q_REG_Q_1_14_UMSK (~(((1U << MJPEG_Q_REG_Q_1_14_LEN) - 1) << MJPEG_Q_REG_Q_1_14_POS)) -#define MJPEG_Q_REG_Q_1_15 MJPEG_Q_REG_Q_1_15 -#define MJPEG_Q_REG_Q_1_15_POS (16U) -#define MJPEG_Q_REG_Q_1_15_LEN (12U) -#define MJPEG_Q_REG_Q_1_15_MSK (((1U << MJPEG_Q_REG_Q_1_15_LEN) - 1) << MJPEG_Q_REG_Q_1_15_POS) -#define MJPEG_Q_REG_Q_1_15_UMSK (~(((1U << MJPEG_Q_REG_Q_1_15_LEN) - 1) << MJPEG_Q_REG_Q_1_15_POS)) - -/* 0x4AC : mjpeg_q_param_56 */ -#define MJPEG_Q_PARAM_56_OFFSET (0x4AC) -#define MJPEG_Q_REG_Q_1_16 MJPEG_Q_REG_Q_1_16 -#define MJPEG_Q_REG_Q_1_16_POS (0U) -#define MJPEG_Q_REG_Q_1_16_LEN (12U) -#define MJPEG_Q_REG_Q_1_16_MSK (((1U << MJPEG_Q_REG_Q_1_16_LEN) - 1) << MJPEG_Q_REG_Q_1_16_POS) -#define MJPEG_Q_REG_Q_1_16_UMSK (~(((1U << MJPEG_Q_REG_Q_1_16_LEN) - 1) << MJPEG_Q_REG_Q_1_16_POS)) -#define MJPEG_Q_REG_Q_1_17 MJPEG_Q_REG_Q_1_17 -#define MJPEG_Q_REG_Q_1_17_POS (16U) -#define MJPEG_Q_REG_Q_1_17_LEN (12U) -#define MJPEG_Q_REG_Q_1_17_MSK (((1U << MJPEG_Q_REG_Q_1_17_LEN) - 1) << MJPEG_Q_REG_Q_1_17_POS) -#define MJPEG_Q_REG_Q_1_17_UMSK (~(((1U << MJPEG_Q_REG_Q_1_17_LEN) - 1) << MJPEG_Q_REG_Q_1_17_POS)) - -/* 0x4B0 : mjpeg_q_param_58 */ -#define MJPEG_Q_PARAM_58_OFFSET (0x4B0) -#define MJPEG_Q_REG_Q_1_18 MJPEG_Q_REG_Q_1_18 -#define MJPEG_Q_REG_Q_1_18_POS (0U) -#define MJPEG_Q_REG_Q_1_18_LEN (12U) -#define MJPEG_Q_REG_Q_1_18_MSK (((1U << MJPEG_Q_REG_Q_1_18_LEN) - 1) << MJPEG_Q_REG_Q_1_18_POS) -#define MJPEG_Q_REG_Q_1_18_UMSK (~(((1U << MJPEG_Q_REG_Q_1_18_LEN) - 1) << MJPEG_Q_REG_Q_1_18_POS)) -#define MJPEG_Q_REG_Q_1_19 MJPEG_Q_REG_Q_1_19 -#define MJPEG_Q_REG_Q_1_19_POS (16U) -#define MJPEG_Q_REG_Q_1_19_LEN (12U) -#define MJPEG_Q_REG_Q_1_19_MSK (((1U << MJPEG_Q_REG_Q_1_19_LEN) - 1) << MJPEG_Q_REG_Q_1_19_POS) -#define MJPEG_Q_REG_Q_1_19_UMSK (~(((1U << MJPEG_Q_REG_Q_1_19_LEN) - 1) << MJPEG_Q_REG_Q_1_19_POS)) - -/* 0x4B4 : mjpeg_q_param_5a */ -#define MJPEG_Q_PARAM_5A_OFFSET (0x4B4) -#define MJPEG_Q_REG_Q_1_1A MJPEG_Q_REG_Q_1_1A -#define MJPEG_Q_REG_Q_1_1A_POS (0U) -#define MJPEG_Q_REG_Q_1_1A_LEN (12U) -#define MJPEG_Q_REG_Q_1_1A_MSK (((1U << MJPEG_Q_REG_Q_1_1A_LEN) - 1) << MJPEG_Q_REG_Q_1_1A_POS) -#define MJPEG_Q_REG_Q_1_1A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1A_LEN) - 1) << MJPEG_Q_REG_Q_1_1A_POS)) -#define MJPEG_Q_REG_Q_1_1B MJPEG_Q_REG_Q_1_1B -#define MJPEG_Q_REG_Q_1_1B_POS (16U) -#define MJPEG_Q_REG_Q_1_1B_LEN (12U) -#define MJPEG_Q_REG_Q_1_1B_MSK (((1U << MJPEG_Q_REG_Q_1_1B_LEN) - 1) << MJPEG_Q_REG_Q_1_1B_POS) -#define MJPEG_Q_REG_Q_1_1B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1B_LEN) - 1) << MJPEG_Q_REG_Q_1_1B_POS)) - -/* 0x4B8 : mjpeg_q_param_5c */ -#define MJPEG_Q_PARAM_5C_OFFSET (0x4B8) -#define MJPEG_Q_REG_Q_1_1C MJPEG_Q_REG_Q_1_1C -#define MJPEG_Q_REG_Q_1_1C_POS (0U) -#define MJPEG_Q_REG_Q_1_1C_LEN (12U) -#define MJPEG_Q_REG_Q_1_1C_MSK (((1U << MJPEG_Q_REG_Q_1_1C_LEN) - 1) << MJPEG_Q_REG_Q_1_1C_POS) -#define MJPEG_Q_REG_Q_1_1C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1C_LEN) - 1) << MJPEG_Q_REG_Q_1_1C_POS)) -#define MJPEG_Q_REG_Q_1_1D MJPEG_Q_REG_Q_1_1D -#define MJPEG_Q_REG_Q_1_1D_POS (16U) -#define MJPEG_Q_REG_Q_1_1D_LEN (12U) -#define MJPEG_Q_REG_Q_1_1D_MSK (((1U << MJPEG_Q_REG_Q_1_1D_LEN) - 1) << MJPEG_Q_REG_Q_1_1D_POS) -#define MJPEG_Q_REG_Q_1_1D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1D_LEN) - 1) << MJPEG_Q_REG_Q_1_1D_POS)) - -/* 0x4BC : mjpeg_q_param_5e */ -#define MJPEG_Q_PARAM_5E_OFFSET (0x4BC) -#define MJPEG_Q_REG_Q_1_1E MJPEG_Q_REG_Q_1_1E -#define MJPEG_Q_REG_Q_1_1E_POS (0U) -#define MJPEG_Q_REG_Q_1_1E_LEN (12U) -#define MJPEG_Q_REG_Q_1_1E_MSK (((1U << MJPEG_Q_REG_Q_1_1E_LEN) - 1) << MJPEG_Q_REG_Q_1_1E_POS) -#define MJPEG_Q_REG_Q_1_1E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1E_LEN) - 1) << MJPEG_Q_REG_Q_1_1E_POS)) -#define MJPEG_Q_REG_Q_1_1F MJPEG_Q_REG_Q_1_1F -#define MJPEG_Q_REG_Q_1_1F_POS (16U) -#define MJPEG_Q_REG_Q_1_1F_LEN (12U) -#define MJPEG_Q_REG_Q_1_1F_MSK (((1U << MJPEG_Q_REG_Q_1_1F_LEN) - 1) << MJPEG_Q_REG_Q_1_1F_POS) -#define MJPEG_Q_REG_Q_1_1F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_1F_LEN) - 1) << MJPEG_Q_REG_Q_1_1F_POS)) - -/* 0x4C0 : mjpeg_q_param_60 */ -#define MJPEG_Q_PARAM_60_OFFSET (0x4C0) -#define MJPEG_Q_REG_Q_1_20 MJPEG_Q_REG_Q_1_20 -#define MJPEG_Q_REG_Q_1_20_POS (0U) -#define MJPEG_Q_REG_Q_1_20_LEN (12U) -#define MJPEG_Q_REG_Q_1_20_MSK (((1U << MJPEG_Q_REG_Q_1_20_LEN) - 1) << MJPEG_Q_REG_Q_1_20_POS) -#define MJPEG_Q_REG_Q_1_20_UMSK (~(((1U << MJPEG_Q_REG_Q_1_20_LEN) - 1) << MJPEG_Q_REG_Q_1_20_POS)) -#define MJPEG_Q_REG_Q_1_21 MJPEG_Q_REG_Q_1_21 -#define MJPEG_Q_REG_Q_1_21_POS (16U) -#define MJPEG_Q_REG_Q_1_21_LEN (12U) -#define MJPEG_Q_REG_Q_1_21_MSK (((1U << MJPEG_Q_REG_Q_1_21_LEN) - 1) << MJPEG_Q_REG_Q_1_21_POS) -#define MJPEG_Q_REG_Q_1_21_UMSK (~(((1U << MJPEG_Q_REG_Q_1_21_LEN) - 1) << MJPEG_Q_REG_Q_1_21_POS)) - -/* 0x4C4 : mjpeg_q_param_62 */ -#define MJPEG_Q_PARAM_62_OFFSET (0x4C4) -#define MJPEG_Q_REG_Q_1_22 MJPEG_Q_REG_Q_1_22 -#define MJPEG_Q_REG_Q_1_22_POS (0U) -#define MJPEG_Q_REG_Q_1_22_LEN (12U) -#define MJPEG_Q_REG_Q_1_22_MSK (((1U << MJPEG_Q_REG_Q_1_22_LEN) - 1) << MJPEG_Q_REG_Q_1_22_POS) -#define MJPEG_Q_REG_Q_1_22_UMSK (~(((1U << MJPEG_Q_REG_Q_1_22_LEN) - 1) << MJPEG_Q_REG_Q_1_22_POS)) -#define MJPEG_Q_REG_Q_1_23 MJPEG_Q_REG_Q_1_23 -#define MJPEG_Q_REG_Q_1_23_POS (16U) -#define MJPEG_Q_REG_Q_1_23_LEN (12U) -#define MJPEG_Q_REG_Q_1_23_MSK (((1U << MJPEG_Q_REG_Q_1_23_LEN) - 1) << MJPEG_Q_REG_Q_1_23_POS) -#define MJPEG_Q_REG_Q_1_23_UMSK (~(((1U << MJPEG_Q_REG_Q_1_23_LEN) - 1) << MJPEG_Q_REG_Q_1_23_POS)) - -/* 0x4C8 : mjpeg_q_param_64 */ -#define MJPEG_Q_PARAM_64_OFFSET (0x4C8) -#define MJPEG_Q_REG_Q_1_24 MJPEG_Q_REG_Q_1_24 -#define MJPEG_Q_REG_Q_1_24_POS (0U) -#define MJPEG_Q_REG_Q_1_24_LEN (12U) -#define MJPEG_Q_REG_Q_1_24_MSK (((1U << MJPEG_Q_REG_Q_1_24_LEN) - 1) << MJPEG_Q_REG_Q_1_24_POS) -#define MJPEG_Q_REG_Q_1_24_UMSK (~(((1U << MJPEG_Q_REG_Q_1_24_LEN) - 1) << MJPEG_Q_REG_Q_1_24_POS)) -#define MJPEG_Q_REG_Q_1_25 MJPEG_Q_REG_Q_1_25 -#define MJPEG_Q_REG_Q_1_25_POS (16U) -#define MJPEG_Q_REG_Q_1_25_LEN (12U) -#define MJPEG_Q_REG_Q_1_25_MSK (((1U << MJPEG_Q_REG_Q_1_25_LEN) - 1) << MJPEG_Q_REG_Q_1_25_POS) -#define MJPEG_Q_REG_Q_1_25_UMSK (~(((1U << MJPEG_Q_REG_Q_1_25_LEN) - 1) << MJPEG_Q_REG_Q_1_25_POS)) - -/* 0x4CC : mjpeg_q_param_66 */ -#define MJPEG_Q_PARAM_66_OFFSET (0x4CC) -#define MJPEG_Q_REG_Q_1_26 MJPEG_Q_REG_Q_1_26 -#define MJPEG_Q_REG_Q_1_26_POS (0U) -#define MJPEG_Q_REG_Q_1_26_LEN (12U) -#define MJPEG_Q_REG_Q_1_26_MSK (((1U << MJPEG_Q_REG_Q_1_26_LEN) - 1) << MJPEG_Q_REG_Q_1_26_POS) -#define MJPEG_Q_REG_Q_1_26_UMSK (~(((1U << MJPEG_Q_REG_Q_1_26_LEN) - 1) << MJPEG_Q_REG_Q_1_26_POS)) -#define MJPEG_Q_REG_Q_1_27 MJPEG_Q_REG_Q_1_27 -#define MJPEG_Q_REG_Q_1_27_POS (16U) -#define MJPEG_Q_REG_Q_1_27_LEN (12U) -#define MJPEG_Q_REG_Q_1_27_MSK (((1U << MJPEG_Q_REG_Q_1_27_LEN) - 1) << MJPEG_Q_REG_Q_1_27_POS) -#define MJPEG_Q_REG_Q_1_27_UMSK (~(((1U << MJPEG_Q_REG_Q_1_27_LEN) - 1) << MJPEG_Q_REG_Q_1_27_POS)) - -/* 0x4D0 : mjpeg_q_param_68 */ -#define MJPEG_Q_PARAM_68_OFFSET (0x4D0) -#define MJPEG_Q_REG_Q_1_28 MJPEG_Q_REG_Q_1_28 -#define MJPEG_Q_REG_Q_1_28_POS (0U) -#define MJPEG_Q_REG_Q_1_28_LEN (12U) -#define MJPEG_Q_REG_Q_1_28_MSK (((1U << MJPEG_Q_REG_Q_1_28_LEN) - 1) << MJPEG_Q_REG_Q_1_28_POS) -#define MJPEG_Q_REG_Q_1_28_UMSK (~(((1U << MJPEG_Q_REG_Q_1_28_LEN) - 1) << MJPEG_Q_REG_Q_1_28_POS)) -#define MJPEG_Q_REG_Q_1_29 MJPEG_Q_REG_Q_1_29 -#define MJPEG_Q_REG_Q_1_29_POS (16U) -#define MJPEG_Q_REG_Q_1_29_LEN (12U) -#define MJPEG_Q_REG_Q_1_29_MSK (((1U << MJPEG_Q_REG_Q_1_29_LEN) - 1) << MJPEG_Q_REG_Q_1_29_POS) -#define MJPEG_Q_REG_Q_1_29_UMSK (~(((1U << MJPEG_Q_REG_Q_1_29_LEN) - 1) << MJPEG_Q_REG_Q_1_29_POS)) - -/* 0x4D4 : mjpeg_q_param_6a */ -#define MJPEG_Q_PARAM_6A_OFFSET (0x4D4) -#define MJPEG_Q_REG_Q_1_2A MJPEG_Q_REG_Q_1_2A -#define MJPEG_Q_REG_Q_1_2A_POS (0U) -#define MJPEG_Q_REG_Q_1_2A_LEN (12U) -#define MJPEG_Q_REG_Q_1_2A_MSK (((1U << MJPEG_Q_REG_Q_1_2A_LEN) - 1) << MJPEG_Q_REG_Q_1_2A_POS) -#define MJPEG_Q_REG_Q_1_2A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2A_LEN) - 1) << MJPEG_Q_REG_Q_1_2A_POS)) -#define MJPEG_Q_REG_Q_1_2B MJPEG_Q_REG_Q_1_2B -#define MJPEG_Q_REG_Q_1_2B_POS (16U) -#define MJPEG_Q_REG_Q_1_2B_LEN (12U) -#define MJPEG_Q_REG_Q_1_2B_MSK (((1U << MJPEG_Q_REG_Q_1_2B_LEN) - 1) << MJPEG_Q_REG_Q_1_2B_POS) -#define MJPEG_Q_REG_Q_1_2B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2B_LEN) - 1) << MJPEG_Q_REG_Q_1_2B_POS)) - -/* 0x4D8 : mjpeg_q_param_6c */ -#define MJPEG_Q_PARAM_6C_OFFSET (0x4D8) -#define MJPEG_Q_REG_Q_1_2C MJPEG_Q_REG_Q_1_2C -#define MJPEG_Q_REG_Q_1_2C_POS (0U) -#define MJPEG_Q_REG_Q_1_2C_LEN (12U) -#define MJPEG_Q_REG_Q_1_2C_MSK (((1U << MJPEG_Q_REG_Q_1_2C_LEN) - 1) << MJPEG_Q_REG_Q_1_2C_POS) -#define MJPEG_Q_REG_Q_1_2C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2C_LEN) - 1) << MJPEG_Q_REG_Q_1_2C_POS)) -#define MJPEG_Q_REG_Q_1_2D MJPEG_Q_REG_Q_1_2D -#define MJPEG_Q_REG_Q_1_2D_POS (16U) -#define MJPEG_Q_REG_Q_1_2D_LEN (12U) -#define MJPEG_Q_REG_Q_1_2D_MSK (((1U << MJPEG_Q_REG_Q_1_2D_LEN) - 1) << MJPEG_Q_REG_Q_1_2D_POS) -#define MJPEG_Q_REG_Q_1_2D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2D_LEN) - 1) << MJPEG_Q_REG_Q_1_2D_POS)) - -/* 0x4DC : mjpeg_q_param_6e */ -#define MJPEG_Q_PARAM_6E_OFFSET (0x4DC) -#define MJPEG_Q_REG_Q_1_2E MJPEG_Q_REG_Q_1_2E -#define MJPEG_Q_REG_Q_1_2E_POS (0U) -#define MJPEG_Q_REG_Q_1_2E_LEN (12U) -#define MJPEG_Q_REG_Q_1_2E_MSK (((1U << MJPEG_Q_REG_Q_1_2E_LEN) - 1) << MJPEG_Q_REG_Q_1_2E_POS) -#define MJPEG_Q_REG_Q_1_2E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2E_LEN) - 1) << MJPEG_Q_REG_Q_1_2E_POS)) -#define MJPEG_Q_REG_Q_1_2F MJPEG_Q_REG_Q_1_2F -#define MJPEG_Q_REG_Q_1_2F_POS (16U) -#define MJPEG_Q_REG_Q_1_2F_LEN (12U) -#define MJPEG_Q_REG_Q_1_2F_MSK (((1U << MJPEG_Q_REG_Q_1_2F_LEN) - 1) << MJPEG_Q_REG_Q_1_2F_POS) -#define MJPEG_Q_REG_Q_1_2F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_2F_LEN) - 1) << MJPEG_Q_REG_Q_1_2F_POS)) - -/* 0x4E0 : mjpeg_q_param_70 */ -#define MJPEG_Q_PARAM_70_OFFSET (0x4E0) -#define MJPEG_Q_REG_Q_1_30 MJPEG_Q_REG_Q_1_30 -#define MJPEG_Q_REG_Q_1_30_POS (0U) -#define MJPEG_Q_REG_Q_1_30_LEN (12U) -#define MJPEG_Q_REG_Q_1_30_MSK (((1U << MJPEG_Q_REG_Q_1_30_LEN) - 1) << MJPEG_Q_REG_Q_1_30_POS) -#define MJPEG_Q_REG_Q_1_30_UMSK (~(((1U << MJPEG_Q_REG_Q_1_30_LEN) - 1) << MJPEG_Q_REG_Q_1_30_POS)) -#define MJPEG_Q_REG_Q_1_31 MJPEG_Q_REG_Q_1_31 -#define MJPEG_Q_REG_Q_1_31_POS (16U) -#define MJPEG_Q_REG_Q_1_31_LEN (12U) -#define MJPEG_Q_REG_Q_1_31_MSK (((1U << MJPEG_Q_REG_Q_1_31_LEN) - 1) << MJPEG_Q_REG_Q_1_31_POS) -#define MJPEG_Q_REG_Q_1_31_UMSK (~(((1U << MJPEG_Q_REG_Q_1_31_LEN) - 1) << MJPEG_Q_REG_Q_1_31_POS)) - -/* 0x4E4 : mjpeg_q_param_72 */ -#define MJPEG_Q_PARAM_72_OFFSET (0x4E4) -#define MJPEG_Q_REG_Q_1_32 MJPEG_Q_REG_Q_1_32 -#define MJPEG_Q_REG_Q_1_32_POS (0U) -#define MJPEG_Q_REG_Q_1_32_LEN (12U) -#define MJPEG_Q_REG_Q_1_32_MSK (((1U << MJPEG_Q_REG_Q_1_32_LEN) - 1) << MJPEG_Q_REG_Q_1_32_POS) -#define MJPEG_Q_REG_Q_1_32_UMSK (~(((1U << MJPEG_Q_REG_Q_1_32_LEN) - 1) << MJPEG_Q_REG_Q_1_32_POS)) -#define MJPEG_Q_REG_Q_1_33 MJPEG_Q_REG_Q_1_33 -#define MJPEG_Q_REG_Q_1_33_POS (16U) -#define MJPEG_Q_REG_Q_1_33_LEN (12U) -#define MJPEG_Q_REG_Q_1_33_MSK (((1U << MJPEG_Q_REG_Q_1_33_LEN) - 1) << MJPEG_Q_REG_Q_1_33_POS) -#define MJPEG_Q_REG_Q_1_33_UMSK (~(((1U << MJPEG_Q_REG_Q_1_33_LEN) - 1) << MJPEG_Q_REG_Q_1_33_POS)) - -/* 0x4E8 : mjpeg_q_param_74 */ -#define MJPEG_Q_PARAM_74_OFFSET (0x4E8) -#define MJPEG_Q_REG_Q_1_34 MJPEG_Q_REG_Q_1_34 -#define MJPEG_Q_REG_Q_1_34_POS (0U) -#define MJPEG_Q_REG_Q_1_34_LEN (12U) -#define MJPEG_Q_REG_Q_1_34_MSK (((1U << MJPEG_Q_REG_Q_1_34_LEN) - 1) << MJPEG_Q_REG_Q_1_34_POS) -#define MJPEG_Q_REG_Q_1_34_UMSK (~(((1U << MJPEG_Q_REG_Q_1_34_LEN) - 1) << MJPEG_Q_REG_Q_1_34_POS)) -#define MJPEG_Q_REG_Q_1_35 MJPEG_Q_REG_Q_1_35 -#define MJPEG_Q_REG_Q_1_35_POS (16U) -#define MJPEG_Q_REG_Q_1_35_LEN (12U) -#define MJPEG_Q_REG_Q_1_35_MSK (((1U << MJPEG_Q_REG_Q_1_35_LEN) - 1) << MJPEG_Q_REG_Q_1_35_POS) -#define MJPEG_Q_REG_Q_1_35_UMSK (~(((1U << MJPEG_Q_REG_Q_1_35_LEN) - 1) << MJPEG_Q_REG_Q_1_35_POS)) - -/* 0x4EC : mjpeg_q_param_76 */ -#define MJPEG_Q_PARAM_76_OFFSET (0x4EC) -#define MJPEG_Q_REG_Q_1_36 MJPEG_Q_REG_Q_1_36 -#define MJPEG_Q_REG_Q_1_36_POS (0U) -#define MJPEG_Q_REG_Q_1_36_LEN (12U) -#define MJPEG_Q_REG_Q_1_36_MSK (((1U << MJPEG_Q_REG_Q_1_36_LEN) - 1) << MJPEG_Q_REG_Q_1_36_POS) -#define MJPEG_Q_REG_Q_1_36_UMSK (~(((1U << MJPEG_Q_REG_Q_1_36_LEN) - 1) << MJPEG_Q_REG_Q_1_36_POS)) -#define MJPEG_Q_REG_Q_1_37 MJPEG_Q_REG_Q_1_37 -#define MJPEG_Q_REG_Q_1_37_POS (16U) -#define MJPEG_Q_REG_Q_1_37_LEN (12U) -#define MJPEG_Q_REG_Q_1_37_MSK (((1U << MJPEG_Q_REG_Q_1_37_LEN) - 1) << MJPEG_Q_REG_Q_1_37_POS) -#define MJPEG_Q_REG_Q_1_37_UMSK (~(((1U << MJPEG_Q_REG_Q_1_37_LEN) - 1) << MJPEG_Q_REG_Q_1_37_POS)) - -/* 0x4F0 : mjpeg_q_param_78 */ -#define MJPEG_Q_PARAM_78_OFFSET (0x4F0) -#define MJPEG_Q_REG_Q_1_38 MJPEG_Q_REG_Q_1_38 -#define MJPEG_Q_REG_Q_1_38_POS (0U) -#define MJPEG_Q_REG_Q_1_38_LEN (12U) -#define MJPEG_Q_REG_Q_1_38_MSK (((1U << MJPEG_Q_REG_Q_1_38_LEN) - 1) << MJPEG_Q_REG_Q_1_38_POS) -#define MJPEG_Q_REG_Q_1_38_UMSK (~(((1U << MJPEG_Q_REG_Q_1_38_LEN) - 1) << MJPEG_Q_REG_Q_1_38_POS)) -#define MJPEG_Q_REG_Q_1_39 MJPEG_Q_REG_Q_1_39 -#define MJPEG_Q_REG_Q_1_39_POS (16U) -#define MJPEG_Q_REG_Q_1_39_LEN (12U) -#define MJPEG_Q_REG_Q_1_39_MSK (((1U << MJPEG_Q_REG_Q_1_39_LEN) - 1) << MJPEG_Q_REG_Q_1_39_POS) -#define MJPEG_Q_REG_Q_1_39_UMSK (~(((1U << MJPEG_Q_REG_Q_1_39_LEN) - 1) << MJPEG_Q_REG_Q_1_39_POS)) - -/* 0x4F4 : mjpeg_q_param_7a */ -#define MJPEG_Q_PARAM_7A_OFFSET (0x4F4) -#define MJPEG_Q_REG_Q_1_3A MJPEG_Q_REG_Q_1_3A -#define MJPEG_Q_REG_Q_1_3A_POS (0U) -#define MJPEG_Q_REG_Q_1_3A_LEN (12U) -#define MJPEG_Q_REG_Q_1_3A_MSK (((1U << MJPEG_Q_REG_Q_1_3A_LEN) - 1) << MJPEG_Q_REG_Q_1_3A_POS) -#define MJPEG_Q_REG_Q_1_3A_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3A_LEN) - 1) << MJPEG_Q_REG_Q_1_3A_POS)) -#define MJPEG_Q_REG_Q_1_3B MJPEG_Q_REG_Q_1_3B -#define MJPEG_Q_REG_Q_1_3B_POS (16U) -#define MJPEG_Q_REG_Q_1_3B_LEN (12U) -#define MJPEG_Q_REG_Q_1_3B_MSK (((1U << MJPEG_Q_REG_Q_1_3B_LEN) - 1) << MJPEG_Q_REG_Q_1_3B_POS) -#define MJPEG_Q_REG_Q_1_3B_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3B_LEN) - 1) << MJPEG_Q_REG_Q_1_3B_POS)) - -/* 0x4F8 : mjpeg_q_param_7c */ -#define MJPEG_Q_PARAM_7C_OFFSET (0x4F8) -#define MJPEG_Q_REG_Q_1_3C MJPEG_Q_REG_Q_1_3C -#define MJPEG_Q_REG_Q_1_3C_POS (0U) -#define MJPEG_Q_REG_Q_1_3C_LEN (12U) -#define MJPEG_Q_REG_Q_1_3C_MSK (((1U << MJPEG_Q_REG_Q_1_3C_LEN) - 1) << MJPEG_Q_REG_Q_1_3C_POS) -#define MJPEG_Q_REG_Q_1_3C_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3C_LEN) - 1) << MJPEG_Q_REG_Q_1_3C_POS)) -#define MJPEG_Q_REG_Q_1_3D MJPEG_Q_REG_Q_1_3D -#define MJPEG_Q_REG_Q_1_3D_POS (16U) -#define MJPEG_Q_REG_Q_1_3D_LEN (12U) -#define MJPEG_Q_REG_Q_1_3D_MSK (((1U << MJPEG_Q_REG_Q_1_3D_LEN) - 1) << MJPEG_Q_REG_Q_1_3D_POS) -#define MJPEG_Q_REG_Q_1_3D_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3D_LEN) - 1) << MJPEG_Q_REG_Q_1_3D_POS)) - -/* 0x4FC : mjpeg_q_param_7e */ -#define MJPEG_Q_PARAM_7E_OFFSET (0x4FC) -#define MJPEG_Q_REG_Q_1_3E MJPEG_Q_REG_Q_1_3E -#define MJPEG_Q_REG_Q_1_3E_POS (0U) -#define MJPEG_Q_REG_Q_1_3E_LEN (12U) -#define MJPEG_Q_REG_Q_1_3E_MSK (((1U << MJPEG_Q_REG_Q_1_3E_LEN) - 1) << MJPEG_Q_REG_Q_1_3E_POS) -#define MJPEG_Q_REG_Q_1_3E_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3E_LEN) - 1) << MJPEG_Q_REG_Q_1_3E_POS)) -#define MJPEG_Q_REG_Q_1_3F MJPEG_Q_REG_Q_1_3F -#define MJPEG_Q_REG_Q_1_3F_POS (16U) -#define MJPEG_Q_REG_Q_1_3F_LEN (12U) -#define MJPEG_Q_REG_Q_1_3F_MSK (((1U << MJPEG_Q_REG_Q_1_3F_LEN) - 1) << MJPEG_Q_REG_Q_1_3F_POS) -#define MJPEG_Q_REG_Q_1_3F_UMSK (~(((1U << MJPEG_Q_REG_Q_1_3F_LEN) - 1) << MJPEG_Q_REG_Q_1_3F_POS)) - -struct mjpeg_q_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[1024]; - - /* 0x400 : mjpeg_q_param_00 */ - union { - struct { - uint32_t reg_q_0_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_01 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_00; - - /* 0x404 : mjpeg_q_param_02 */ - union { - struct { - uint32_t reg_q_0_02 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_03 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_02; - - /* 0x408 : mjpeg_q_param_04 */ - union { - struct { - uint32_t reg_q_0_04 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_05 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_04; - - /* 0x40C : mjpeg_q_param_06 */ - union { - struct { - uint32_t reg_q_0_06 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_07 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_06; - - /* 0x410 : mjpeg_q_param_08 */ - union { - struct { - uint32_t reg_q_0_08 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_09 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_08; - - /* 0x414 : mjpeg_q_param_0a */ - union { - struct { - uint32_t reg_q_0_0a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_0b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_0a; - - /* 0x418 : mjpeg_q_param_0c */ - union { - struct { - uint32_t reg_q_0_0c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_0d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_0c; - - /* 0x41C : mjpeg_q_param_0e */ - union { - struct { - uint32_t reg_q_0_0e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_0f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_0e; - - /* 0x420 : mjpeg_q_param_10 */ - union { - struct { - uint32_t reg_q_0_10 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_11 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_10; - - /* 0x424 : mjpeg_q_param_12 */ - union { - struct { - uint32_t reg_q_0_12 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_13 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_12; - - /* 0x428 : mjpeg_q_param_14 */ - union { - struct { - uint32_t reg_q_0_14 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_15 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_14; - - /* 0x42C : mjpeg_q_param_16 */ - union { - struct { - uint32_t reg_q_0_16 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_17 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_16; - - /* 0x430 : mjpeg_q_param_18 */ - union { - struct { - uint32_t reg_q_0_18 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_19 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_18; - - /* 0x434 : mjpeg_q_param_1a */ - union { - struct { - uint32_t reg_q_0_1a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_1b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_1a; - - /* 0x438 : mjpeg_q_param_1c */ - union { - struct { - uint32_t reg_q_0_1c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_1d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_1c; - - /* 0x43C : mjpeg_q_param_1e */ - union { - struct { - uint32_t reg_q_0_1e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_1f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_1e; - - /* 0x440 : mjpeg_q_param_20 */ - union { - struct { - uint32_t reg_q_0_20 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_21 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_20; - - /* 0x444 : mjpeg_q_param_22 */ - union { - struct { - uint32_t reg_q_0_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_23 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_22; - - /* 0x448 : mjpeg_q_param_24 */ - union { - struct { - uint32_t reg_q_0_24 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_25 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_24; - - /* 0x44C : mjpeg_q_param_26 */ - union { - struct { - uint32_t reg_q_0_26 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_27 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_26; - - /* 0x450 : mjpeg_q_param_28 */ - union { - struct { - uint32_t reg_q_0_28 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_29 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_28; - - /* 0x454 : mjpeg_q_param_2a */ - union { - struct { - uint32_t reg_q_0_2a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_2b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_2a; - - /* 0x458 : mjpeg_q_param_2c */ - union { - struct { - uint32_t reg_q_0_2c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_2d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_2c; - - /* 0x45C : mjpeg_q_param_2e */ - union { - struct { - uint32_t reg_q_0_2e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_2f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_2e; - - /* 0x460 : mjpeg_q_param_30 */ - union { - struct { - uint32_t reg_q_0_30 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_31 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_30; - - /* 0x464 : mjpeg_q_param_32 */ - union { - struct { - uint32_t reg_q_0_32 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_33 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_32; - - /* 0x468 : mjpeg_q_param_34 */ - union { - struct { - uint32_t reg_q_0_34 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_35 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_34; - - /* 0x46C : mjpeg_q_param_36 */ - union { - struct { - uint32_t reg_q_0_36 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_37 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_36; - - /* 0x470 : mjpeg_q_param_38 */ - union { - struct { - uint32_t reg_q_0_38 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_39 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_38; - - /* 0x474 : mjpeg_q_param_3a */ - union { - struct { - uint32_t reg_q_0_3a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_3b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_3a; - - /* 0x478 : mjpeg_q_param_3c */ - union { - struct { - uint32_t reg_q_0_3c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_3d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_3c; - - /* 0x47C : mjpeg_q_param_3e */ - union { - struct { - uint32_t reg_q_0_3e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_0_3f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_3e; - - /* 0x480 : mjpeg_q_param_40 */ - union { - struct { - uint32_t reg_q_1_00 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_01 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_40; - - /* 0x484 : mjpeg_q_param_42 */ - union { - struct { - uint32_t reg_q_1_02 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_03 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_42; - - /* 0x488 : mjpeg_q_param_44 */ - union { - struct { - uint32_t reg_q_1_04 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_05 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_44; - - /* 0x48C : mjpeg_q_param_46 */ - union { - struct { - uint32_t reg_q_1_06 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_07 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_46; - - /* 0x490 : mjpeg_q_param_48 */ - union { - struct { - uint32_t reg_q_1_08 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_09 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_48; - - /* 0x494 : mjpeg_q_param_4a */ - union { - struct { - uint32_t reg_q_1_0a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_0b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_4a; - - /* 0x498 : mjpeg_q_param_4c */ - union { - struct { - uint32_t reg_q_1_0c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_0d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_4c; - - /* 0x49C : mjpeg_q_param_4e */ - union { - struct { - uint32_t reg_q_1_0e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_0f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_4e; - - /* 0x4A0 : mjpeg_q_param_50 */ - union { - struct { - uint32_t reg_q_1_10 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_11 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_50; - - /* 0x4A4 : mjpeg_q_param_52 */ - union { - struct { - uint32_t reg_q_1_12 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_13 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_52; - - /* 0x4A8 : mjpeg_q_param_54 */ - union { - struct { - uint32_t reg_q_1_14 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_15 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_54; - - /* 0x4AC : mjpeg_q_param_56 */ - union { - struct { - uint32_t reg_q_1_16 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_17 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_56; - - /* 0x4B0 : mjpeg_q_param_58 */ - union { - struct { - uint32_t reg_q_1_18 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_19 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_58; - - /* 0x4B4 : mjpeg_q_param_5a */ - union { - struct { - uint32_t reg_q_1_1a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_1b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_5a; - - /* 0x4B8 : mjpeg_q_param_5c */ - union { - struct { - uint32_t reg_q_1_1c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_1d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_5c; - - /* 0x4BC : mjpeg_q_param_5e */ - union { - struct { - uint32_t reg_q_1_1e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_1f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_5e; - - /* 0x4C0 : mjpeg_q_param_60 */ - union { - struct { - uint32_t reg_q_1_20 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_21 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_60; - - /* 0x4C4 : mjpeg_q_param_62 */ - union { - struct { - uint32_t reg_q_1_22 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_23 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_62; - - /* 0x4C8 : mjpeg_q_param_64 */ - union { - struct { - uint32_t reg_q_1_24 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_25 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_64; - - /* 0x4CC : mjpeg_q_param_66 */ - union { - struct { - uint32_t reg_q_1_26 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_27 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_66; - - /* 0x4D0 : mjpeg_q_param_68 */ - union { - struct { - uint32_t reg_q_1_28 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_29 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_68; - - /* 0x4D4 : mjpeg_q_param_6a */ - union { - struct { - uint32_t reg_q_1_2a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_2b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_6a; - - /* 0x4D8 : mjpeg_q_param_6c */ - union { - struct { - uint32_t reg_q_1_2c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_2d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_6c; - - /* 0x4DC : mjpeg_q_param_6e */ - union { - struct { - uint32_t reg_q_1_2e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_2f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_6e; - - /* 0x4E0 : mjpeg_q_param_70 */ - union { - struct { - uint32_t reg_q_1_30 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_31 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_70; - - /* 0x4E4 : mjpeg_q_param_72 */ - union { - struct { - uint32_t reg_q_1_32 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_33 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_72; - - /* 0x4E8 : mjpeg_q_param_74 */ - union { - struct { - uint32_t reg_q_1_34 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_35 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_74; - - /* 0x4EC : mjpeg_q_param_76 */ - union { - struct { - uint32_t reg_q_1_36 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_37 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_76; - - /* 0x4F0 : mjpeg_q_param_78 */ - union { - struct { - uint32_t reg_q_1_38 : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_39 : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_78; - - /* 0x4F4 : mjpeg_q_param_7a */ - union { - struct { - uint32_t reg_q_1_3a : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_3b : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_7a; - - /* 0x4F8 : mjpeg_q_param_7c */ - union { - struct { - uint32_t reg_q_1_3c : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_3d : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_7c; - - /* 0x4FC : mjpeg_q_param_7e */ - union { - struct { - uint32_t reg_q_1_3e : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_q_1_3f : 12; /* [27:16], r/w, 0x0 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_param_7e; -}; - -typedef volatile struct mjpeg_q_reg mjpeg_q_reg_t; - -#endif /* __MJPEG_Q_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_reg.h deleted file mode 100644 index 84d0cac053..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mjpeg_reg.h +++ /dev/null @@ -1,1098 +0,0 @@ -/** - ****************************************************************************** - * @file mjpeg_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __MJPEG_REG_H__ -#define __MJPEG_REG_H__ - -#include "bl808.h" - -/* 0x0 : mjpeg_control_1 */ -#define MJPEG_CONTROL_1_OFFSET (0x0) -#define MJPEG_REG_MJPEG_ENABLE MJPEG_REG_MJPEG_ENABLE -#define MJPEG_REG_MJPEG_ENABLE_POS (0U) -#define MJPEG_REG_MJPEG_ENABLE_LEN (1U) -#define MJPEG_REG_MJPEG_ENABLE_MSK (((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS) -#define MJPEG_REG_MJPEG_ENABLE_UMSK (~(((1U << MJPEG_REG_MJPEG_ENABLE_LEN) - 1) << MJPEG_REG_MJPEG_ENABLE_POS)) -#define MJPEG_REG_MJPEG_BIT_ORDER MJPEG_REG_MJPEG_BIT_ORDER -#define MJPEG_REG_MJPEG_BIT_ORDER_POS (1U) -#define MJPEG_REG_MJPEG_BIT_ORDER_LEN (1U) -#define MJPEG_REG_MJPEG_BIT_ORDER_MSK (((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS) -#define MJPEG_REG_MJPEG_BIT_ORDER_UMSK (~(((1U << MJPEG_REG_MJPEG_BIT_ORDER_LEN) - 1) << MJPEG_REG_MJPEG_BIT_ORDER_POS)) -#define MJPEG_REG_ORDER_U_EVEN MJPEG_REG_ORDER_U_EVEN -#define MJPEG_REG_ORDER_U_EVEN_POS (2U) -#define MJPEG_REG_ORDER_U_EVEN_LEN (1U) -#define MJPEG_REG_ORDER_U_EVEN_MSK (((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS) -#define MJPEG_REG_ORDER_U_EVEN_UMSK (~(((1U << MJPEG_REG_ORDER_U_EVEN_LEN) - 1) << MJPEG_REG_ORDER_U_EVEN_POS)) -#define MJPEG_REG_LAST_HF_WBLK_DMY MJPEG_REG_LAST_HF_WBLK_DMY -#define MJPEG_REG_LAST_HF_WBLK_DMY_POS (4U) -#define MJPEG_REG_LAST_HF_WBLK_DMY_LEN (1U) -#define MJPEG_REG_LAST_HF_WBLK_DMY_MSK (((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS) -#define MJPEG_REG_LAST_HF_WBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_WBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_WBLK_DMY_POS)) -#define MJPEG_REG_LAST_HF_HBLK_DMY MJPEG_REG_LAST_HF_HBLK_DMY -#define MJPEG_REG_LAST_HF_HBLK_DMY_POS (5U) -#define MJPEG_REG_LAST_HF_HBLK_DMY_LEN (1U) -#define MJPEG_REG_LAST_HF_HBLK_DMY_MSK (((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS) -#define MJPEG_REG_LAST_HF_HBLK_DMY_UMSK (~(((1U << MJPEG_REG_LAST_HF_HBLK_DMY_LEN) - 1) << MJPEG_REG_LAST_HF_HBLK_DMY_POS)) -#define MJPEG_REG_REFLECT_DMY MJPEG_REG_REFLECT_DMY -#define MJPEG_REG_REFLECT_DMY_POS (6U) -#define MJPEG_REG_REFLECT_DMY_LEN (1U) -#define MJPEG_REG_REFLECT_DMY_MSK (((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS) -#define MJPEG_REG_REFLECT_DMY_UMSK (~(((1U << MJPEG_REG_REFLECT_DMY_LEN) - 1) << MJPEG_REG_REFLECT_DMY_POS)) -#define MJPEG_REG_READ_FWRAP MJPEG_REG_READ_FWRAP -#define MJPEG_REG_READ_FWRAP_POS (7U) -#define MJPEG_REG_READ_FWRAP_LEN (1U) -#define MJPEG_REG_READ_FWRAP_MSK (((1U << MJPEG_REG_READ_FWRAP_LEN) - 1) << MJPEG_REG_READ_FWRAP_POS) -#define MJPEG_REG_READ_FWRAP_UMSK (~(((1U << MJPEG_REG_READ_FWRAP_LEN) - 1) << MJPEG_REG_READ_FWRAP_POS)) -#define MJPEG_REG_W_XLEN MJPEG_REG_W_XLEN -#define MJPEG_REG_W_XLEN_POS (8U) -#define MJPEG_REG_W_XLEN_LEN (3U) -#define MJPEG_REG_W_XLEN_MSK (((1U << MJPEG_REG_W_XLEN_LEN) - 1) << MJPEG_REG_W_XLEN_POS) -#define MJPEG_REG_W_XLEN_UMSK (~(((1U << MJPEG_REG_W_XLEN_LEN) - 1) << MJPEG_REG_W_XLEN_POS)) -#define MJPEG_REG_YUV_MODE MJPEG_REG_YUV_MODE -#define MJPEG_REG_YUV_MODE_POS (12U) -#define MJPEG_REG_YUV_MODE_LEN (2U) -#define MJPEG_REG_YUV_MODE_MSK (((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS) -#define MJPEG_REG_YUV_MODE_UMSK (~(((1U << MJPEG_REG_YUV_MODE_LEN) - 1) << MJPEG_REG_YUV_MODE_POS)) -#define MJPEG_REG_MJPEG_HW_FRAME MJPEG_REG_MJPEG_HW_FRAME -#define MJPEG_REG_MJPEG_HW_FRAME_POS (24U) -#define MJPEG_REG_MJPEG_HW_FRAME_LEN (6U) -#define MJPEG_REG_MJPEG_HW_FRAME_MSK (((1U << MJPEG_REG_MJPEG_HW_FRAME_LEN) - 1) << MJPEG_REG_MJPEG_HW_FRAME_POS) -#define MJPEG_REG_MJPEG_HW_FRAME_UMSK (~(((1U << MJPEG_REG_MJPEG_HW_FRAME_LEN) - 1) << MJPEG_REG_MJPEG_HW_FRAME_POS)) - -/* 0x4 : mjpeg_control_2 */ -#define MJPEG_CONTROL_2_OFFSET (0x4) -#define MJPEG_REG_SW_FRAME MJPEG_REG_SW_FRAME -#define MJPEG_REG_SW_FRAME_POS (0U) -#define MJPEG_REG_SW_FRAME_LEN (5U) -#define MJPEG_REG_SW_FRAME_MSK (((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS) -#define MJPEG_REG_SW_FRAME_UMSK (~(((1U << MJPEG_REG_SW_FRAME_LEN) - 1) << MJPEG_REG_SW_FRAME_POS)) -#define MJPEG_REG_SW_KICK MJPEG_REG_SW_KICK -#define MJPEG_REG_SW_KICK_POS (6U) -#define MJPEG_REG_SW_KICK_LEN (1U) -#define MJPEG_REG_SW_KICK_MSK (((1U << MJPEG_REG_SW_KICK_LEN) - 1) << MJPEG_REG_SW_KICK_POS) -#define MJPEG_REG_SW_KICK_UMSK (~(((1U << MJPEG_REG_SW_KICK_LEN) - 1) << MJPEG_REG_SW_KICK_POS)) -#define MJPEG_REG_SW_KICK_MODE MJPEG_REG_SW_KICK_MODE -#define MJPEG_REG_SW_KICK_MODE_POS (7U) -#define MJPEG_REG_SW_KICK_MODE_LEN (1U) -#define MJPEG_REG_SW_KICK_MODE_MSK (((1U << MJPEG_REG_SW_KICK_MODE_LEN) - 1) << MJPEG_REG_SW_KICK_MODE_POS) -#define MJPEG_REG_SW_KICK_MODE_UMSK (~(((1U << MJPEG_REG_SW_KICK_MODE_LEN) - 1) << MJPEG_REG_SW_KICK_MODE_POS)) -#define MJPEG_REG_MJPEG_SW_MODE MJPEG_REG_MJPEG_SW_MODE -#define MJPEG_REG_MJPEG_SW_MODE_POS (8U) -#define MJPEG_REG_MJPEG_SW_MODE_LEN (1U) -#define MJPEG_REG_MJPEG_SW_MODE_MSK (((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS) -#define MJPEG_REG_MJPEG_SW_MODE_UMSK (~(((1U << MJPEG_REG_MJPEG_SW_MODE_LEN) - 1) << MJPEG_REG_MJPEG_SW_MODE_POS)) -#define MJPEG_REG_MJPEG_SW_RUN MJPEG_REG_MJPEG_SW_RUN -#define MJPEG_REG_MJPEG_SW_RUN_POS (9U) -#define MJPEG_REG_MJPEG_SW_RUN_LEN (1U) -#define MJPEG_REG_MJPEG_SW_RUN_MSK (((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS) -#define MJPEG_REG_MJPEG_SW_RUN_UMSK (~(((1U << MJPEG_REG_MJPEG_SW_RUN_LEN) - 1) << MJPEG_REG_MJPEG_SW_RUN_POS)) -#define MJPEG_REG_YY_DVP2AXI_SEL MJPEG_REG_YY_DVP2AXI_SEL -#define MJPEG_REG_YY_DVP2AXI_SEL_POS (10U) -#define MJPEG_REG_YY_DVP2AXI_SEL_LEN (3U) -#define MJPEG_REG_YY_DVP2AXI_SEL_MSK (((1U << MJPEG_REG_YY_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_YY_DVP2AXI_SEL_POS) -#define MJPEG_REG_YY_DVP2AXI_SEL_UMSK (~(((1U << MJPEG_REG_YY_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_YY_DVP2AXI_SEL_POS)) -#define MJPEG_REG_UV_DVP2AXI_SEL MJPEG_REG_UV_DVP2AXI_SEL -#define MJPEG_REG_UV_DVP2AXI_SEL_POS (13U) -#define MJPEG_REG_UV_DVP2AXI_SEL_LEN (3U) -#define MJPEG_REG_UV_DVP2AXI_SEL_MSK (((1U << MJPEG_REG_UV_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_UV_DVP2AXI_SEL_POS) -#define MJPEG_REG_UV_DVP2AXI_SEL_UMSK (~(((1U << MJPEG_REG_UV_DVP2AXI_SEL_LEN) - 1) << MJPEG_REG_UV_DVP2AXI_SEL_POS)) -#define MJPEG_REG_MJPEG_WAIT_CYCLE MJPEG_REG_MJPEG_WAIT_CYCLE -#define MJPEG_REG_MJPEG_WAIT_CYCLE_POS (16U) -#define MJPEG_REG_MJPEG_WAIT_CYCLE_LEN (16U) -#define MJPEG_REG_MJPEG_WAIT_CYCLE_MSK (((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS) -#define MJPEG_REG_MJPEG_WAIT_CYCLE_UMSK (~(((1U << MJPEG_REG_MJPEG_WAIT_CYCLE_LEN) - 1) << MJPEG_REG_MJPEG_WAIT_CYCLE_POS)) - -/* 0x08 : mjpeg_yy_frame_addr */ -#define MJPEG_YY_FRAME_ADDR_OFFSET (0x08) -#define MJPEG_REG_YY_ADDR_START MJPEG_REG_YY_ADDR_START -#define MJPEG_REG_YY_ADDR_START_POS (0U) -#define MJPEG_REG_YY_ADDR_START_LEN (32U) -#define MJPEG_REG_YY_ADDR_START_MSK (((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS) -#define MJPEG_REG_YY_ADDR_START_UMSK (~(((1U << MJPEG_REG_YY_ADDR_START_LEN) - 1) << MJPEG_REG_YY_ADDR_START_POS)) - -/* 0x0C : mjpeg_uv_frame_addr */ -#define MJPEG_UV_FRAME_ADDR_OFFSET (0x0C) -#define MJPEG_REG_UV_ADDR_START MJPEG_REG_UV_ADDR_START -#define MJPEG_REG_UV_ADDR_START_POS (0U) -#define MJPEG_REG_UV_ADDR_START_LEN (32U) -#define MJPEG_REG_UV_ADDR_START_MSK (((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS) -#define MJPEG_REG_UV_ADDR_START_UMSK (~(((1U << MJPEG_REG_UV_ADDR_START_LEN) - 1) << MJPEG_REG_UV_ADDR_START_POS)) - -/* 0x10 : mjpeg_yuv_mem */ -#define MJPEG_YUV_MEM_OFFSET (0x10) -#define MJPEG_REG_YY_MEM_HBLK MJPEG_REG_YY_MEM_HBLK -#define MJPEG_REG_YY_MEM_HBLK_POS (0U) -#define MJPEG_REG_YY_MEM_HBLK_LEN (13U) -#define MJPEG_REG_YY_MEM_HBLK_MSK (((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS) -#define MJPEG_REG_YY_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_YY_MEM_HBLK_LEN) - 1) << MJPEG_REG_YY_MEM_HBLK_POS)) -#define MJPEG_REG_UV_MEM_HBLK MJPEG_REG_UV_MEM_HBLK -#define MJPEG_REG_UV_MEM_HBLK_POS (16U) -#define MJPEG_REG_UV_MEM_HBLK_LEN (13U) -#define MJPEG_REG_UV_MEM_HBLK_MSK (((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS) -#define MJPEG_REG_UV_MEM_HBLK_UMSK (~(((1U << MJPEG_REG_UV_MEM_HBLK_LEN) - 1) << MJPEG_REG_UV_MEM_HBLK_POS)) - -/* 0x14 : jpeg_frame_addr */ -#define MJPEG_JPEG_FRAME_ADDR_OFFSET (0x14) -#define MJPEG_REG_W_ADDR_START MJPEG_REG_W_ADDR_START -#define MJPEG_REG_W_ADDR_START_POS (0U) -#define MJPEG_REG_W_ADDR_START_LEN (32U) -#define MJPEG_REG_W_ADDR_START_MSK (((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS) -#define MJPEG_REG_W_ADDR_START_UMSK (~(((1U << MJPEG_REG_W_ADDR_START_LEN) - 1) << MJPEG_REG_W_ADDR_START_POS)) - -/* 0x18 : jpeg_store_memory */ -#define MJPEG_JPEG_STORE_MEMORY_OFFSET (0x18) -#define MJPEG_REG_W_BURST_CNT MJPEG_REG_W_BURST_CNT -#define MJPEG_REG_W_BURST_CNT_POS (0U) -#define MJPEG_REG_W_BURST_CNT_LEN (32U) -#define MJPEG_REG_W_BURST_CNT_MSK (((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS) -#define MJPEG_REG_W_BURST_CNT_UMSK (~(((1U << MJPEG_REG_W_BURST_CNT_LEN) - 1) << MJPEG_REG_W_BURST_CNT_POS)) - -/* 0x1C : mjpeg_control_3 */ -#define MJPEG_CONTROL_3_OFFSET (0x1C) -#define MJPEG_REG_INT_NORMAL_EN MJPEG_REG_INT_NORMAL_EN -#define MJPEG_REG_INT_NORMAL_EN_POS (0U) -#define MJPEG_REG_INT_NORMAL_EN_LEN (1U) -#define MJPEG_REG_INT_NORMAL_EN_MSK (((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS) -#define MJPEG_REG_INT_NORMAL_EN_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_EN_LEN) - 1) << MJPEG_REG_INT_NORMAL_EN_POS)) -#define MJPEG_REG_INT_CAM_EN MJPEG_REG_INT_CAM_EN -#define MJPEG_REG_INT_CAM_EN_POS (1U) -#define MJPEG_REG_INT_CAM_EN_LEN (1U) -#define MJPEG_REG_INT_CAM_EN_MSK (((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS) -#define MJPEG_REG_INT_CAM_EN_UMSK (~(((1U << MJPEG_REG_INT_CAM_EN_LEN) - 1) << MJPEG_REG_INT_CAM_EN_POS)) -#define MJPEG_REG_INT_MEM_EN MJPEG_REG_INT_MEM_EN -#define MJPEG_REG_INT_MEM_EN_POS (2U) -#define MJPEG_REG_INT_MEM_EN_LEN (1U) -#define MJPEG_REG_INT_MEM_EN_MSK (((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS) -#define MJPEG_REG_INT_MEM_EN_UMSK (~(((1U << MJPEG_REG_INT_MEM_EN_LEN) - 1) << MJPEG_REG_INT_MEM_EN_POS)) -#define MJPEG_REG_INT_FRAME_EN MJPEG_REG_INT_FRAME_EN -#define MJPEG_REG_INT_FRAME_EN_POS (3U) -#define MJPEG_REG_INT_FRAME_EN_LEN (1U) -#define MJPEG_REG_INT_FRAME_EN_MSK (((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS) -#define MJPEG_REG_INT_FRAME_EN_UMSK (~(((1U << MJPEG_REG_INT_FRAME_EN_LEN) - 1) << MJPEG_REG_INT_FRAME_EN_POS)) -#define MJPEG_STS_NORMAL_INT MJPEG_STS_NORMAL_INT -#define MJPEG_STS_NORMAL_INT_POS (4U) -#define MJPEG_STS_NORMAL_INT_LEN (1U) -#define MJPEG_STS_NORMAL_INT_MSK (((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS) -#define MJPEG_STS_NORMAL_INT_UMSK (~(((1U << MJPEG_STS_NORMAL_INT_LEN) - 1) << MJPEG_STS_NORMAL_INT_POS)) -#define MJPEG_STS_CAM_INT MJPEG_STS_CAM_INT -#define MJPEG_STS_CAM_INT_POS (5U) -#define MJPEG_STS_CAM_INT_LEN (1U) -#define MJPEG_STS_CAM_INT_MSK (((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS) -#define MJPEG_STS_CAM_INT_UMSK (~(((1U << MJPEG_STS_CAM_INT_LEN) - 1) << MJPEG_STS_CAM_INT_POS)) -#define MJPEG_STS_MEM_INT MJPEG_STS_MEM_INT -#define MJPEG_STS_MEM_INT_POS (6U) -#define MJPEG_STS_MEM_INT_LEN (1U) -#define MJPEG_STS_MEM_INT_MSK (((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS) -#define MJPEG_STS_MEM_INT_UMSK (~(((1U << MJPEG_STS_MEM_INT_LEN) - 1) << MJPEG_STS_MEM_INT_POS)) -#define MJPEG_STS_FRAME_INT MJPEG_STS_FRAME_INT -#define MJPEG_STS_FRAME_INT_POS (7U) -#define MJPEG_STS_FRAME_INT_LEN (1U) -#define MJPEG_STS_FRAME_INT_MSK (((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS) -#define MJPEG_STS_FRAME_INT_UMSK (~(((1U << MJPEG_STS_FRAME_INT_LEN) - 1) << MJPEG_STS_FRAME_INT_POS)) -#define MJPEG_IDLE MJPEG_IDLE -#define MJPEG_IDLE_POS (8U) -#define MJPEG_IDLE_LEN (1U) -#define MJPEG_IDLE_MSK (((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS) -#define MJPEG_IDLE_UMSK (~(((1U << MJPEG_IDLE_LEN) - 1) << MJPEG_IDLE_POS)) -#define MJPEG_FUNC MJPEG_FUNC -#define MJPEG_FUNC_POS (9U) -#define MJPEG_FUNC_LEN (1U) -#define MJPEG_FUNC_MSK (((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS) -#define MJPEG_FUNC_UMSK (~(((1U << MJPEG_FUNC_LEN) - 1) << MJPEG_FUNC_POS)) -#define MJPEG_WAIT MJPEG_WAIT -#define MJPEG_WAIT_POS (10U) -#define MJPEG_WAIT_LEN (1U) -#define MJPEG_WAIT_MSK (((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS) -#define MJPEG_WAIT_UMSK (~(((1U << MJPEG_WAIT_LEN) - 1) << MJPEG_WAIT_POS)) -#define MJPEG_FLSH MJPEG_FLSH -#define MJPEG_FLSH_POS (11U) -#define MJPEG_FLSH_LEN (1U) -#define MJPEG_FLSH_MSK (((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS) -#define MJPEG_FLSH_UMSK (~(((1U << MJPEG_FLSH_LEN) - 1) << MJPEG_FLSH_POS)) -#define MJPEG_MANS MJPEG_MANS -#define MJPEG_MANS_POS (12U) -#define MJPEG_MANS_LEN (1U) -#define MJPEG_MANS_MSK (((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS) -#define MJPEG_MANS_UMSK (~(((1U << MJPEG_MANS_LEN) - 1) << MJPEG_MANS_POS)) -#define MJPEG_MANF MJPEG_MANF -#define MJPEG_MANF_POS (13U) -#define MJPEG_MANF_LEN (1U) -#define MJPEG_MANF_MSK (((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS) -#define MJPEG_MANF_UMSK (~(((1U << MJPEG_MANF_LEN) - 1) << MJPEG_MANF_POS)) -#define MJPEG_AXI_READ_IDLE MJPEG_AXI_READ_IDLE -#define MJPEG_AXI_READ_IDLE_POS (14U) -#define MJPEG_AXI_READ_IDLE_LEN (1U) -#define MJPEG_AXI_READ_IDLE_MSK (((1U << MJPEG_AXI_READ_IDLE_LEN) - 1) << MJPEG_AXI_READ_IDLE_POS) -#define MJPEG_AXI_READ_IDLE_UMSK (~(((1U << MJPEG_AXI_READ_IDLE_LEN) - 1) << MJPEG_AXI_READ_IDLE_POS)) -#define MJPEG_AXI_WRITE_IDLE MJPEG_AXI_WRITE_IDLE -#define MJPEG_AXI_WRITE_IDLE_POS (15U) -#define MJPEG_AXI_WRITE_IDLE_LEN (1U) -#define MJPEG_AXI_WRITE_IDLE_MSK (((1U << MJPEG_AXI_WRITE_IDLE_LEN) - 1) << MJPEG_AXI_WRITE_IDLE_POS) -#define MJPEG_AXI_WRITE_IDLE_UMSK (~(((1U << MJPEG_AXI_WRITE_IDLE_LEN) - 1) << MJPEG_AXI_WRITE_IDLE_POS)) -#define MJPEG_REG_FRAME_CNT_TRGR_INT MJPEG_REG_FRAME_CNT_TRGR_INT -#define MJPEG_REG_FRAME_CNT_TRGR_INT_POS (16U) -#define MJPEG_REG_FRAME_CNT_TRGR_INT_LEN (5U) -#define MJPEG_REG_FRAME_CNT_TRGR_INT_MSK (((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS) -#define MJPEG_REG_FRAME_CNT_TRGR_INT_UMSK (~(((1U << MJPEG_REG_FRAME_CNT_TRGR_INT_LEN) - 1) << MJPEG_REG_FRAME_CNT_TRGR_INT_POS)) -#define MJPEG_REG_INT_IDLE_EN MJPEG_REG_INT_IDLE_EN -#define MJPEG_REG_INT_IDLE_EN_POS (21U) -#define MJPEG_REG_INT_IDLE_EN_LEN (1U) -#define MJPEG_REG_INT_IDLE_EN_MSK (((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS) -#define MJPEG_REG_INT_IDLE_EN_UMSK (~(((1U << MJPEG_REG_INT_IDLE_EN_LEN) - 1) << MJPEG_REG_INT_IDLE_EN_POS)) -#define MJPEG_STS_IDLE_INT MJPEG_STS_IDLE_INT -#define MJPEG_STS_IDLE_INT_POS (22U) -#define MJPEG_STS_IDLE_INT_LEN (1U) -#define MJPEG_STS_IDLE_INT_MSK (((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS) -#define MJPEG_STS_IDLE_INT_UMSK (~(((1U << MJPEG_STS_IDLE_INT_LEN) - 1) << MJPEG_STS_IDLE_INT_POS)) -#define MJPEG_FRAME_VALID_CNT MJPEG_FRAME_VALID_CNT -#define MJPEG_FRAME_VALID_CNT_POS (24U) -#define MJPEG_FRAME_VALID_CNT_LEN (5U) -#define MJPEG_FRAME_VALID_CNT_MSK (((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS) -#define MJPEG_FRAME_VALID_CNT_UMSK (~(((1U << MJPEG_FRAME_VALID_CNT_LEN) - 1) << MJPEG_FRAME_VALID_CNT_POS)) -#define MJPEG_REG_INT_SWAP_EN MJPEG_REG_INT_SWAP_EN -#define MJPEG_REG_INT_SWAP_EN_POS (29U) -#define MJPEG_REG_INT_SWAP_EN_LEN (1U) -#define MJPEG_REG_INT_SWAP_EN_MSK (((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS) -#define MJPEG_REG_INT_SWAP_EN_UMSK (~(((1U << MJPEG_REG_INT_SWAP_EN_LEN) - 1) << MJPEG_REG_INT_SWAP_EN_POS)) -#define MJPEG_STS_SWAP_INT MJPEG_STS_SWAP_INT -#define MJPEG_STS_SWAP_INT_POS (30U) -#define MJPEG_STS_SWAP_INT_LEN (1U) -#define MJPEG_STS_SWAP_INT_MSK (((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS) -#define MJPEG_STS_SWAP_INT_UMSK (~(((1U << MJPEG_STS_SWAP_INT_LEN) - 1) << MJPEG_STS_SWAP_INT_POS)) - -/* 0x20 : mjpeg_frame_fifo_pop */ -#define MJPEG_FRAME_FIFO_POP_OFFSET (0x20) -#define MJPEG_RFIFO_POP MJPEG_RFIFO_POP -#define MJPEG_RFIFO_POP_POS (0U) -#define MJPEG_RFIFO_POP_LEN (1U) -#define MJPEG_RFIFO_POP_MSK (((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS) -#define MJPEG_RFIFO_POP_UMSK (~(((1U << MJPEG_RFIFO_POP_LEN) - 1) << MJPEG_RFIFO_POP_POS)) -#define MJPEG_REG_W_SWAP_CLR MJPEG_REG_W_SWAP_CLR -#define MJPEG_REG_W_SWAP_CLR_POS (1U) -#define MJPEG_REG_W_SWAP_CLR_LEN (1U) -#define MJPEG_REG_W_SWAP_CLR_MSK (((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS) -#define MJPEG_REG_W_SWAP_CLR_UMSK (~(((1U << MJPEG_REG_W_SWAP_CLR_LEN) - 1) << MJPEG_REG_W_SWAP_CLR_POS)) -#define MJPEG_REG_INT_NORMAL_CLR MJPEG_REG_INT_NORMAL_CLR -#define MJPEG_REG_INT_NORMAL_CLR_POS (8U) -#define MJPEG_REG_INT_NORMAL_CLR_LEN (1U) -#define MJPEG_REG_INT_NORMAL_CLR_MSK (((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS) -#define MJPEG_REG_INT_NORMAL_CLR_UMSK (~(((1U << MJPEG_REG_INT_NORMAL_CLR_LEN) - 1) << MJPEG_REG_INT_NORMAL_CLR_POS)) -#define MJPEG_REG_INT_CAM_CLR MJPEG_REG_INT_CAM_CLR -#define MJPEG_REG_INT_CAM_CLR_POS (9U) -#define MJPEG_REG_INT_CAM_CLR_LEN (1U) -#define MJPEG_REG_INT_CAM_CLR_MSK (((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS) -#define MJPEG_REG_INT_CAM_CLR_UMSK (~(((1U << MJPEG_REG_INT_CAM_CLR_LEN) - 1) << MJPEG_REG_INT_CAM_CLR_POS)) -#define MJPEG_REG_INT_MEM_CLR MJPEG_REG_INT_MEM_CLR -#define MJPEG_REG_INT_MEM_CLR_POS (10U) -#define MJPEG_REG_INT_MEM_CLR_LEN (1U) -#define MJPEG_REG_INT_MEM_CLR_MSK (((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS) -#define MJPEG_REG_INT_MEM_CLR_UMSK (~(((1U << MJPEG_REG_INT_MEM_CLR_LEN) - 1) << MJPEG_REG_INT_MEM_CLR_POS)) -#define MJPEG_REG_INT_FRAME_CLR MJPEG_REG_INT_FRAME_CLR -#define MJPEG_REG_INT_FRAME_CLR_POS (11U) -#define MJPEG_REG_INT_FRAME_CLR_LEN (1U) -#define MJPEG_REG_INT_FRAME_CLR_MSK (((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS) -#define MJPEG_REG_INT_FRAME_CLR_UMSK (~(((1U << MJPEG_REG_INT_FRAME_CLR_LEN) - 1) << MJPEG_REG_INT_FRAME_CLR_POS)) -#define MJPEG_REG_INT_IDLE_CLR MJPEG_REG_INT_IDLE_CLR -#define MJPEG_REG_INT_IDLE_CLR_POS (12U) -#define MJPEG_REG_INT_IDLE_CLR_LEN (1U) -#define MJPEG_REG_INT_IDLE_CLR_MSK (((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS) -#define MJPEG_REG_INT_IDLE_CLR_UMSK (~(((1U << MJPEG_REG_INT_IDLE_CLR_LEN) - 1) << MJPEG_REG_INT_IDLE_CLR_POS)) -#define MJPEG_REG_INT_SWAP_CLR MJPEG_REG_INT_SWAP_CLR -#define MJPEG_REG_INT_SWAP_CLR_POS (13U) -#define MJPEG_REG_INT_SWAP_CLR_LEN (1U) -#define MJPEG_REG_INT_SWAP_CLR_MSK (((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS) -#define MJPEG_REG_INT_SWAP_CLR_UMSK (~(((1U << MJPEG_REG_INT_SWAP_CLR_LEN) - 1) << MJPEG_REG_INT_SWAP_CLR_POS)) - -/* 0x24 : mjpeg_frame_size */ -#define MJPEG_FRAME_SIZE_OFFSET (0x24) -#define MJPEG_REG_FRAME_WBLK MJPEG_REG_FRAME_WBLK -#define MJPEG_REG_FRAME_WBLK_POS (0U) -#define MJPEG_REG_FRAME_WBLK_LEN (12U) -#define MJPEG_REG_FRAME_WBLK_MSK (((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS) -#define MJPEG_REG_FRAME_WBLK_UMSK (~(((1U << MJPEG_REG_FRAME_WBLK_LEN) - 1) << MJPEG_REG_FRAME_WBLK_POS)) -#define MJPEG_REG_FRAME_HBLK MJPEG_REG_FRAME_HBLK -#define MJPEG_REG_FRAME_HBLK_POS (16U) -#define MJPEG_REG_FRAME_HBLK_LEN (12U) -#define MJPEG_REG_FRAME_HBLK_MSK (((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS) -#define MJPEG_REG_FRAME_HBLK_UMSK (~(((1U << MJPEG_REG_FRAME_HBLK_LEN) - 1) << MJPEG_REG_FRAME_HBLK_POS)) - -/* 0x28 : mjpeg_header_byte */ -#define MJPEG_HEADER_BYTE_OFFSET (0x28) -#define MJPEG_REG_HEAD_BYTE MJPEG_REG_HEAD_BYTE -#define MJPEG_REG_HEAD_BYTE_POS (0U) -#define MJPEG_REG_HEAD_BYTE_LEN (12U) -#define MJPEG_REG_HEAD_BYTE_MSK (((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS) -#define MJPEG_REG_HEAD_BYTE_UMSK (~(((1U << MJPEG_REG_HEAD_BYTE_LEN) - 1) << MJPEG_REG_HEAD_BYTE_POS)) -#define MJPEG_REG_TAIL_EXP MJPEG_REG_TAIL_EXP -#define MJPEG_REG_TAIL_EXP_POS (16U) -#define MJPEG_REG_TAIL_EXP_LEN (1U) -#define MJPEG_REG_TAIL_EXP_MSK (((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS) -#define MJPEG_REG_TAIL_EXP_UMSK (~(((1U << MJPEG_REG_TAIL_EXP_LEN) - 1) << MJPEG_REG_TAIL_EXP_POS)) -#define MJPEG_REG_Y0_ORDER MJPEG_REG_Y0_ORDER -#define MJPEG_REG_Y0_ORDER_POS (24U) -#define MJPEG_REG_Y0_ORDER_LEN (2U) -#define MJPEG_REG_Y0_ORDER_MSK (((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS) -#define MJPEG_REG_Y0_ORDER_UMSK (~(((1U << MJPEG_REG_Y0_ORDER_LEN) - 1) << MJPEG_REG_Y0_ORDER_POS)) -#define MJPEG_REG_U0_ORDER MJPEG_REG_U0_ORDER -#define MJPEG_REG_U0_ORDER_POS (26U) -#define MJPEG_REG_U0_ORDER_LEN (2U) -#define MJPEG_REG_U0_ORDER_MSK (((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS) -#define MJPEG_REG_U0_ORDER_UMSK (~(((1U << MJPEG_REG_U0_ORDER_LEN) - 1) << MJPEG_REG_U0_ORDER_POS)) -#define MJPEG_REG_Y1_ORDER MJPEG_REG_Y1_ORDER -#define MJPEG_REG_Y1_ORDER_POS (28U) -#define MJPEG_REG_Y1_ORDER_LEN (2U) -#define MJPEG_REG_Y1_ORDER_MSK (((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS) -#define MJPEG_REG_Y1_ORDER_UMSK (~(((1U << MJPEG_REG_Y1_ORDER_LEN) - 1) << MJPEG_REG_Y1_ORDER_POS)) -#define MJPEG_REG_V0_ORDER MJPEG_REG_V0_ORDER -#define MJPEG_REG_V0_ORDER_POS (30U) -#define MJPEG_REG_V0_ORDER_LEN (2U) -#define MJPEG_REG_V0_ORDER_MSK (((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS) -#define MJPEG_REG_V0_ORDER_UMSK (~(((1U << MJPEG_REG_V0_ORDER_LEN) - 1) << MJPEG_REG_V0_ORDER_POS)) - -/* 0x30 : mjpeg_swap_mode */ -#define MJPEG_SWAP_MODE_OFFSET (0x30) -#define MJPEG_REG_W_SWAP_MODE MJPEG_REG_W_SWAP_MODE -#define MJPEG_REG_W_SWAP_MODE_POS (0U) -#define MJPEG_REG_W_SWAP_MODE_LEN (1U) -#define MJPEG_REG_W_SWAP_MODE_MSK (((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS) -#define MJPEG_REG_W_SWAP_MODE_UMSK (~(((1U << MJPEG_REG_W_SWAP_MODE_LEN) - 1) << MJPEG_REG_W_SWAP_MODE_POS)) -#define MJPEG_STS_SWAP0_FULL MJPEG_STS_SWAP0_FULL -#define MJPEG_STS_SWAP0_FULL_POS (8U) -#define MJPEG_STS_SWAP0_FULL_LEN (1U) -#define MJPEG_STS_SWAP0_FULL_MSK (((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS) -#define MJPEG_STS_SWAP0_FULL_UMSK (~(((1U << MJPEG_STS_SWAP0_FULL_LEN) - 1) << MJPEG_STS_SWAP0_FULL_POS)) -#define MJPEG_STS_SWAP1_FULL MJPEG_STS_SWAP1_FULL -#define MJPEG_STS_SWAP1_FULL_POS (9U) -#define MJPEG_STS_SWAP1_FULL_LEN (1U) -#define MJPEG_STS_SWAP1_FULL_MSK (((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS) -#define MJPEG_STS_SWAP1_FULL_UMSK (~(((1U << MJPEG_STS_SWAP1_FULL_LEN) - 1) << MJPEG_STS_SWAP1_FULL_POS)) -#define MJPEG_STS_READ_SWAP_IDX MJPEG_STS_READ_SWAP_IDX -#define MJPEG_STS_READ_SWAP_IDX_POS (10U) -#define MJPEG_STS_READ_SWAP_IDX_LEN (1U) -#define MJPEG_STS_READ_SWAP_IDX_MSK (((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS) -#define MJPEG_STS_READ_SWAP_IDX_UMSK (~(((1U << MJPEG_STS_READ_SWAP_IDX_LEN) - 1) << MJPEG_STS_READ_SWAP_IDX_POS)) -#define MJPEG_STS_SWAP_FSTART MJPEG_STS_SWAP_FSTART -#define MJPEG_STS_SWAP_FSTART_POS (11U) -#define MJPEG_STS_SWAP_FSTART_LEN (1U) -#define MJPEG_STS_SWAP_FSTART_MSK (((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS) -#define MJPEG_STS_SWAP_FSTART_UMSK (~(((1U << MJPEG_STS_SWAP_FSTART_LEN) - 1) << MJPEG_STS_SWAP_FSTART_POS)) -#define MJPEG_STS_SWAP_FEND MJPEG_STS_SWAP_FEND -#define MJPEG_STS_SWAP_FEND_POS (12U) -#define MJPEG_STS_SWAP_FEND_LEN (1U) -#define MJPEG_STS_SWAP_FEND_MSK (((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS) -#define MJPEG_STS_SWAP_FEND_UMSK (~(((1U << MJPEG_STS_SWAP_FEND_LEN) - 1) << MJPEG_STS_SWAP_FEND_POS)) - -/* 0x34 : mjpeg_swap_bit_cnt */ -#define MJPEG_SWAP_BIT_CNT_OFFSET (0x34) -#define MJPEG_FRAME_SWAP_END_BIT_CNT MJPEG_FRAME_SWAP_END_BIT_CNT -#define MJPEG_FRAME_SWAP_END_BIT_CNT_POS (0U) -#define MJPEG_FRAME_SWAP_END_BIT_CNT_LEN (32U) -#define MJPEG_FRAME_SWAP_END_BIT_CNT_MSK (((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS) -#define MJPEG_FRAME_SWAP_END_BIT_CNT_UMSK (~(((1U << MJPEG_FRAME_SWAP_END_BIT_CNT_LEN) - 1) << MJPEG_FRAME_SWAP_END_BIT_CNT_POS)) - -/* 0x38 : mjpeg_yuv_mem_sw */ -#define MJPEG_YUV_MEM_SW_OFFSET (0x38) -#define MJPEG_REG_SW_KICK_HBLK MJPEG_REG_SW_KICK_HBLK -#define MJPEG_REG_SW_KICK_HBLK_POS (0U) -#define MJPEG_REG_SW_KICK_HBLK_LEN (13U) -#define MJPEG_REG_SW_KICK_HBLK_MSK (((1U << MJPEG_REG_SW_KICK_HBLK_LEN) - 1) << MJPEG_REG_SW_KICK_HBLK_POS) -#define MJPEG_REG_SW_KICK_HBLK_UMSK (~(((1U << MJPEG_REG_SW_KICK_HBLK_LEN) - 1) << MJPEG_REG_SW_KICK_HBLK_POS)) - -/* 0x40 : mjpeg_Y_frame_read_status_1 */ -#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET (0x40) -#define MJPEG_YY_MEM_HBLK_R MJPEG_YY_MEM_HBLK_R -#define MJPEG_YY_MEM_HBLK_R_POS (0U) -#define MJPEG_YY_MEM_HBLK_R_LEN (13U) -#define MJPEG_YY_MEM_HBLK_R_MSK (((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS) -#define MJPEG_YY_MEM_HBLK_R_UMSK (~(((1U << MJPEG_YY_MEM_HBLK_R_LEN) - 1) << MJPEG_YY_MEM_HBLK_R_POS)) -#define MJPEG_YY_FRM_HBLK_R MJPEG_YY_FRM_HBLK_R -#define MJPEG_YY_FRM_HBLK_R_POS (16U) -#define MJPEG_YY_FRM_HBLK_R_LEN (13U) -#define MJPEG_YY_FRM_HBLK_R_MSK (((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS) -#define MJPEG_YY_FRM_HBLK_R_UMSK (~(((1U << MJPEG_YY_FRM_HBLK_R_LEN) - 1) << MJPEG_YY_FRM_HBLK_R_POS)) - -/* 0x44 : mjpeg_Y_frame_read_status_2 */ -#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET (0x44) -#define MJPEG_YY_WBLK_R MJPEG_YY_WBLK_R -#define MJPEG_YY_WBLK_R_POS (0U) -#define MJPEG_YY_WBLK_R_LEN (13U) -#define MJPEG_YY_WBLK_R_MSK (((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS) -#define MJPEG_YY_WBLK_R_UMSK (~(((1U << MJPEG_YY_WBLK_R_LEN) - 1) << MJPEG_YY_WBLK_R_POS)) -#define MJPEG_YY_MEM_RND_R MJPEG_YY_MEM_RND_R -#define MJPEG_YY_MEM_RND_R_POS (16U) -#define MJPEG_YY_MEM_RND_R_LEN (8U) -#define MJPEG_YY_MEM_RND_R_MSK (((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS) -#define MJPEG_YY_MEM_RND_R_UMSK (~(((1U << MJPEG_YY_MEM_RND_R_LEN) - 1) << MJPEG_YY_MEM_RND_R_POS)) -#define MJPEG_YY_FRM_CNT_R MJPEG_YY_FRM_CNT_R -#define MJPEG_YY_FRM_CNT_R_POS (24U) -#define MJPEG_YY_FRM_CNT_R_LEN (8U) -#define MJPEG_YY_FRM_CNT_R_MSK (((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS) -#define MJPEG_YY_FRM_CNT_R_UMSK (~(((1U << MJPEG_YY_FRM_CNT_R_LEN) - 1) << MJPEG_YY_FRM_CNT_R_POS)) - -/* 0x48 : mjpeg_Y_frame_write_status */ -#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET (0x48) -#define MJPEG_YY_MEM_HBLK_W MJPEG_YY_MEM_HBLK_W -#define MJPEG_YY_MEM_HBLK_W_POS (0U) -#define MJPEG_YY_MEM_HBLK_W_LEN (13U) -#define MJPEG_YY_MEM_HBLK_W_MSK (((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS) -#define MJPEG_YY_MEM_HBLK_W_UMSK (~(((1U << MJPEG_YY_MEM_HBLK_W_LEN) - 1) << MJPEG_YY_MEM_HBLK_W_POS)) -#define MJPEG_YY_MEM_RND_W MJPEG_YY_MEM_RND_W -#define MJPEG_YY_MEM_RND_W_POS (16U) -#define MJPEG_YY_MEM_RND_W_LEN (8U) -#define MJPEG_YY_MEM_RND_W_MSK (((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS) -#define MJPEG_YY_MEM_RND_W_UMSK (~(((1U << MJPEG_YY_MEM_RND_W_LEN) - 1) << MJPEG_YY_MEM_RND_W_POS)) -#define MJPEG_YY_FRM_CNT_W MJPEG_YY_FRM_CNT_W -#define MJPEG_YY_FRM_CNT_W_POS (24U) -#define MJPEG_YY_FRM_CNT_W_LEN (8U) -#define MJPEG_YY_FRM_CNT_W_MSK (((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS) -#define MJPEG_YY_FRM_CNT_W_UMSK (~(((1U << MJPEG_YY_FRM_CNT_W_LEN) - 1) << MJPEG_YY_FRM_CNT_W_POS)) - -/* 0x4C : mjpeg_UV_frame_read_status_1 */ -#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET (0x4C) -#define MJPEG_UV_MEM_HBLK_R MJPEG_UV_MEM_HBLK_R -#define MJPEG_UV_MEM_HBLK_R_POS (0U) -#define MJPEG_UV_MEM_HBLK_R_LEN (13U) -#define MJPEG_UV_MEM_HBLK_R_MSK (((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS) -#define MJPEG_UV_MEM_HBLK_R_UMSK (~(((1U << MJPEG_UV_MEM_HBLK_R_LEN) - 1) << MJPEG_UV_MEM_HBLK_R_POS)) -#define MJPEG_UV_FRM_HBLK_R MJPEG_UV_FRM_HBLK_R -#define MJPEG_UV_FRM_HBLK_R_POS (16U) -#define MJPEG_UV_FRM_HBLK_R_LEN (13U) -#define MJPEG_UV_FRM_HBLK_R_MSK (((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS) -#define MJPEG_UV_FRM_HBLK_R_UMSK (~(((1U << MJPEG_UV_FRM_HBLK_R_LEN) - 1) << MJPEG_UV_FRM_HBLK_R_POS)) - -/* 0x50 : mjpeg_UV_frame_read_status_2 */ -#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET (0x50) -#define MJPEG_UV_WBLK_R MJPEG_UV_WBLK_R -#define MJPEG_UV_WBLK_R_POS (0U) -#define MJPEG_UV_WBLK_R_LEN (13U) -#define MJPEG_UV_WBLK_R_MSK (((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS) -#define MJPEG_UV_WBLK_R_UMSK (~(((1U << MJPEG_UV_WBLK_R_LEN) - 1) << MJPEG_UV_WBLK_R_POS)) -#define MJPEG_UV_MEM_RND_R MJPEG_UV_MEM_RND_R -#define MJPEG_UV_MEM_RND_R_POS (16U) -#define MJPEG_UV_MEM_RND_R_LEN (8U) -#define MJPEG_UV_MEM_RND_R_MSK (((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS) -#define MJPEG_UV_MEM_RND_R_UMSK (~(((1U << MJPEG_UV_MEM_RND_R_LEN) - 1) << MJPEG_UV_MEM_RND_R_POS)) -#define MJPEG_UV_FRM_CNT_R MJPEG_UV_FRM_CNT_R -#define MJPEG_UV_FRM_CNT_R_POS (24U) -#define MJPEG_UV_FRM_CNT_R_LEN (8U) -#define MJPEG_UV_FRM_CNT_R_MSK (((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS) -#define MJPEG_UV_FRM_CNT_R_UMSK (~(((1U << MJPEG_UV_FRM_CNT_R_LEN) - 1) << MJPEG_UV_FRM_CNT_R_POS)) - -/* 0x54 : mjpeg_UV_frame_write_status */ -#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET (0x54) -#define MJPEG_UV_MEM_HBLK_W MJPEG_UV_MEM_HBLK_W -#define MJPEG_UV_MEM_HBLK_W_POS (0U) -#define MJPEG_UV_MEM_HBLK_W_LEN (13U) -#define MJPEG_UV_MEM_HBLK_W_MSK (((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS) -#define MJPEG_UV_MEM_HBLK_W_UMSK (~(((1U << MJPEG_UV_MEM_HBLK_W_LEN) - 1) << MJPEG_UV_MEM_HBLK_W_POS)) -#define MJPEG_UV_MEM_RND_W MJPEG_UV_MEM_RND_W -#define MJPEG_UV_MEM_RND_W_POS (16U) -#define MJPEG_UV_MEM_RND_W_LEN (8U) -#define MJPEG_UV_MEM_RND_W_MSK (((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS) -#define MJPEG_UV_MEM_RND_W_UMSK (~(((1U << MJPEG_UV_MEM_RND_W_LEN) - 1) << MJPEG_UV_MEM_RND_W_POS)) -#define MJPEG_UV_FRM_CNT_W MJPEG_UV_FRM_CNT_W -#define MJPEG_UV_FRM_CNT_W_POS (24U) -#define MJPEG_UV_FRM_CNT_W_LEN (8U) -#define MJPEG_UV_FRM_CNT_W_MSK (((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS) -#define MJPEG_UV_FRM_CNT_W_UMSK (~(((1U << MJPEG_UV_FRM_CNT_W_LEN) - 1) << MJPEG_UV_FRM_CNT_W_POS)) - -/* 0x58 : mjpeg_frame_w_hblk_status */ -#define MJPEG_FRAME_W_HBLK_STATUS_OFFSET (0x58) -#define MJPEG_YY_FRM_HBLK_W MJPEG_YY_FRM_HBLK_W -#define MJPEG_YY_FRM_HBLK_W_POS (0U) -#define MJPEG_YY_FRM_HBLK_W_LEN (13U) -#define MJPEG_YY_FRM_HBLK_W_MSK (((1U << MJPEG_YY_FRM_HBLK_W_LEN) - 1) << MJPEG_YY_FRM_HBLK_W_POS) -#define MJPEG_YY_FRM_HBLK_W_UMSK (~(((1U << MJPEG_YY_FRM_HBLK_W_LEN) - 1) << MJPEG_YY_FRM_HBLK_W_POS)) -#define MJPEG_UV_FRM_HBLK_W MJPEG_UV_FRM_HBLK_W -#define MJPEG_UV_FRM_HBLK_W_POS (16U) -#define MJPEG_UV_FRM_HBLK_W_LEN (13U) -#define MJPEG_UV_FRM_HBLK_W_MSK (((1U << MJPEG_UV_FRM_HBLK_W_LEN) - 1) << MJPEG_UV_FRM_HBLK_W_POS) -#define MJPEG_UV_FRM_HBLK_W_UMSK (~(((1U << MJPEG_UV_FRM_HBLK_W_LEN) - 1) << MJPEG_UV_FRM_HBLK_W_POS)) - -/* 0x80 : mjpeg_start_addr0 */ -#define MJPEG_START_ADDR0_OFFSET (0x80) -#define MJPEG_FRAME_START_ADDR_0 MJPEG_FRAME_START_ADDR_0 -#define MJPEG_FRAME_START_ADDR_0_POS (0U) -#define MJPEG_FRAME_START_ADDR_0_LEN (32U) -#define MJPEG_FRAME_START_ADDR_0_MSK (((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS) -#define MJPEG_FRAME_START_ADDR_0_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_0_LEN) - 1) << MJPEG_FRAME_START_ADDR_0_POS)) - -/* 0x84 : mjpeg_bit_cnt0 */ -#define MJPEG_BIT_CNT0_OFFSET (0x84) -#define MJPEG_FRAME_BIT_CNT_0 MJPEG_FRAME_BIT_CNT_0 -#define MJPEG_FRAME_BIT_CNT_0_POS (0U) -#define MJPEG_FRAME_BIT_CNT_0_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_0_MSK (((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS) -#define MJPEG_FRAME_BIT_CNT_0_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_0_LEN) - 1) << MJPEG_FRAME_BIT_CNT_0_POS)) - -/* 0x88 : mjpeg_start_addr1 */ -#define MJPEG_START_ADDR1_OFFSET (0x88) -#define MJPEG_FRAME_START_ADDR_1 MJPEG_FRAME_START_ADDR_1 -#define MJPEG_FRAME_START_ADDR_1_POS (0U) -#define MJPEG_FRAME_START_ADDR_1_LEN (32U) -#define MJPEG_FRAME_START_ADDR_1_MSK (((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS) -#define MJPEG_FRAME_START_ADDR_1_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_1_LEN) - 1) << MJPEG_FRAME_START_ADDR_1_POS)) - -/* 0x8C : mjpeg_bit_cnt1 */ -#define MJPEG_BIT_CNT1_OFFSET (0x8C) -#define MJPEG_FRAME_BIT_CNT_1 MJPEG_FRAME_BIT_CNT_1 -#define MJPEG_FRAME_BIT_CNT_1_POS (0U) -#define MJPEG_FRAME_BIT_CNT_1_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_1_MSK (((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS) -#define MJPEG_FRAME_BIT_CNT_1_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_1_LEN) - 1) << MJPEG_FRAME_BIT_CNT_1_POS)) - -/* 0x90 : mjpeg_start_addr2 */ -#define MJPEG_START_ADDR2_OFFSET (0x90) -#define MJPEG_FRAME_START_ADDR_2 MJPEG_FRAME_START_ADDR_2 -#define MJPEG_FRAME_START_ADDR_2_POS (0U) -#define MJPEG_FRAME_START_ADDR_2_LEN (32U) -#define MJPEG_FRAME_START_ADDR_2_MSK (((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS) -#define MJPEG_FRAME_START_ADDR_2_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_2_LEN) - 1) << MJPEG_FRAME_START_ADDR_2_POS)) - -/* 0x94 : mjpeg_bit_cnt2 */ -#define MJPEG_BIT_CNT2_OFFSET (0x94) -#define MJPEG_FRAME_BIT_CNT_2 MJPEG_FRAME_BIT_CNT_2 -#define MJPEG_FRAME_BIT_CNT_2_POS (0U) -#define MJPEG_FRAME_BIT_CNT_2_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_2_MSK (((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS) -#define MJPEG_FRAME_BIT_CNT_2_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_2_LEN) - 1) << MJPEG_FRAME_BIT_CNT_2_POS)) - -/* 0x98 : mjpeg_start_addr3 */ -#define MJPEG_START_ADDR3_OFFSET (0x98) -#define MJPEG_FRAME_START_ADDR_3 MJPEG_FRAME_START_ADDR_3 -#define MJPEG_FRAME_START_ADDR_3_POS (0U) -#define MJPEG_FRAME_START_ADDR_3_LEN (32U) -#define MJPEG_FRAME_START_ADDR_3_MSK (((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS) -#define MJPEG_FRAME_START_ADDR_3_UMSK (~(((1U << MJPEG_FRAME_START_ADDR_3_LEN) - 1) << MJPEG_FRAME_START_ADDR_3_POS)) - -/* 0x9C : mjpeg_bit_cnt3 */ -#define MJPEG_BIT_CNT3_OFFSET (0x9C) -#define MJPEG_FRAME_BIT_CNT_3 MJPEG_FRAME_BIT_CNT_3 -#define MJPEG_FRAME_BIT_CNT_3_POS (0U) -#define MJPEG_FRAME_BIT_CNT_3_LEN (32U) -#define MJPEG_FRAME_BIT_CNT_3_MSK (((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS) -#define MJPEG_FRAME_BIT_CNT_3_UMSK (~(((1U << MJPEG_FRAME_BIT_CNT_3_LEN) - 1) << MJPEG_FRAME_BIT_CNT_3_POS)) - -/* 0x100 : mjpeg_q_enc */ -#define MJPEG_Q_ENC_OFFSET (0x100) -#define MJPEG_FRAME_Q_SRAM_0 MJPEG_FRAME_Q_SRAM_0 -#define MJPEG_FRAME_Q_SRAM_0_POS (0U) -#define MJPEG_FRAME_Q_SRAM_0_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_0_MSK (((1U << MJPEG_FRAME_Q_SRAM_0_LEN) - 1) << MJPEG_FRAME_Q_SRAM_0_POS) -#define MJPEG_FRAME_Q_SRAM_0_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_0_LEN) - 1) << MJPEG_FRAME_Q_SRAM_0_POS)) -#define MJPEG_FRAME_Q_SRAM_1 MJPEG_FRAME_Q_SRAM_1 -#define MJPEG_FRAME_Q_SRAM_1_POS (1U) -#define MJPEG_FRAME_Q_SRAM_1_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_1_MSK (((1U << MJPEG_FRAME_Q_SRAM_1_LEN) - 1) << MJPEG_FRAME_Q_SRAM_1_POS) -#define MJPEG_FRAME_Q_SRAM_1_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_1_LEN) - 1) << MJPEG_FRAME_Q_SRAM_1_POS)) -#define MJPEG_FRAME_Q_SRAM_2 MJPEG_FRAME_Q_SRAM_2 -#define MJPEG_FRAME_Q_SRAM_2_POS (2U) -#define MJPEG_FRAME_Q_SRAM_2_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_2_MSK (((1U << MJPEG_FRAME_Q_SRAM_2_LEN) - 1) << MJPEG_FRAME_Q_SRAM_2_POS) -#define MJPEG_FRAME_Q_SRAM_2_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_2_LEN) - 1) << MJPEG_FRAME_Q_SRAM_2_POS)) -#define MJPEG_FRAME_Q_SRAM_3 MJPEG_FRAME_Q_SRAM_3 -#define MJPEG_FRAME_Q_SRAM_3_POS (3U) -#define MJPEG_FRAME_Q_SRAM_3_LEN (1U) -#define MJPEG_FRAME_Q_SRAM_3_MSK (((1U << MJPEG_FRAME_Q_SRAM_3_LEN) - 1) << MJPEG_FRAME_Q_SRAM_3_POS) -#define MJPEG_FRAME_Q_SRAM_3_UMSK (~(((1U << MJPEG_FRAME_Q_SRAM_3_LEN) - 1) << MJPEG_FRAME_Q_SRAM_3_POS)) -#define MJPEG_REG_Q_SRAM_SW MJPEG_REG_Q_SRAM_SW -#define MJPEG_REG_Q_SRAM_SW_POS (24U) -#define MJPEG_REG_Q_SRAM_SW_LEN (1U) -#define MJPEG_REG_Q_SRAM_SW_MSK (((1U << MJPEG_REG_Q_SRAM_SW_LEN) - 1) << MJPEG_REG_Q_SRAM_SW_POS) -#define MJPEG_REG_Q_SRAM_SW_UMSK (~(((1U << MJPEG_REG_Q_SRAM_SW_LEN) - 1) << MJPEG_REG_Q_SRAM_SW_POS)) -#define MJPEG_STS_Q_SRAM_ENC MJPEG_STS_Q_SRAM_ENC -#define MJPEG_STS_Q_SRAM_ENC_POS (25U) -#define MJPEG_STS_Q_SRAM_ENC_LEN (1U) -#define MJPEG_STS_Q_SRAM_ENC_MSK (((1U << MJPEG_STS_Q_SRAM_ENC_LEN) - 1) << MJPEG_STS_Q_SRAM_ENC_POS) -#define MJPEG_STS_Q_SRAM_ENC_UMSK (~(((1U << MJPEG_STS_Q_SRAM_ENC_LEN) - 1) << MJPEG_STS_Q_SRAM_ENC_POS)) - -/* 0x110 : mjpeg_frame_id_10 */ -#define MJPEG_FRAME_ID_10_OFFSET (0x110) -#define MJPEG_FRAME_ID_0 MJPEG_FRAME_ID_0 -#define MJPEG_FRAME_ID_0_POS (0U) -#define MJPEG_FRAME_ID_0_LEN (16U) -#define MJPEG_FRAME_ID_0_MSK (((1U << MJPEG_FRAME_ID_0_LEN) - 1) << MJPEG_FRAME_ID_0_POS) -#define MJPEG_FRAME_ID_0_UMSK (~(((1U << MJPEG_FRAME_ID_0_LEN) - 1) << MJPEG_FRAME_ID_0_POS)) -#define MJPEG_FRAME_ID_1 MJPEG_FRAME_ID_1 -#define MJPEG_FRAME_ID_1_POS (16U) -#define MJPEG_FRAME_ID_1_LEN (16U) -#define MJPEG_FRAME_ID_1_MSK (((1U << MJPEG_FRAME_ID_1_LEN) - 1) << MJPEG_FRAME_ID_1_POS) -#define MJPEG_FRAME_ID_1_UMSK (~(((1U << MJPEG_FRAME_ID_1_LEN) - 1) << MJPEG_FRAME_ID_1_POS)) - -/* 0x114 : mjpeg_frame_id_32 */ -#define MJPEG_FRAME_ID_32_OFFSET (0x114) -#define MJPEG_FRAME_ID_2 MJPEG_FRAME_ID_2 -#define MJPEG_FRAME_ID_2_POS (0U) -#define MJPEG_FRAME_ID_2_LEN (16U) -#define MJPEG_FRAME_ID_2_MSK (((1U << MJPEG_FRAME_ID_2_LEN) - 1) << MJPEG_FRAME_ID_2_POS) -#define MJPEG_FRAME_ID_2_UMSK (~(((1U << MJPEG_FRAME_ID_2_LEN) - 1) << MJPEG_FRAME_ID_2_POS)) -#define MJPEG_FRAME_ID_3 MJPEG_FRAME_ID_3 -#define MJPEG_FRAME_ID_3_POS (16U) -#define MJPEG_FRAME_ID_3_LEN (16U) -#define MJPEG_FRAME_ID_3_MSK (((1U << MJPEG_FRAME_ID_3_LEN) - 1) << MJPEG_FRAME_ID_3_POS) -#define MJPEG_FRAME_ID_3_UMSK (~(((1U << MJPEG_FRAME_ID_3_LEN) - 1) << MJPEG_FRAME_ID_3_POS)) - -/* 0x1F0 : mjpeg_debug */ -#define MJPEG_DEBUG_OFFSET (0x1F0) -#define MJPEG_REG_MJPEG_DBG_EN MJPEG_REG_MJPEG_DBG_EN -#define MJPEG_REG_MJPEG_DBG_EN_POS (0U) -#define MJPEG_REG_MJPEG_DBG_EN_LEN (1U) -#define MJPEG_REG_MJPEG_DBG_EN_MSK (((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS) -#define MJPEG_REG_MJPEG_DBG_EN_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_EN_LEN) - 1) << MJPEG_REG_MJPEG_DBG_EN_POS)) -#define MJPEG_REG_MJPEG_DBG_SEL MJPEG_REG_MJPEG_DBG_SEL -#define MJPEG_REG_MJPEG_DBG_SEL_POS (4U) -#define MJPEG_REG_MJPEG_DBG_SEL_LEN (4U) -#define MJPEG_REG_MJPEG_DBG_SEL_MSK (((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS) -#define MJPEG_REG_MJPEG_DBG_SEL_UMSK (~(((1U << MJPEG_REG_MJPEG_DBG_SEL_LEN) - 1) << MJPEG_REG_MJPEG_DBG_SEL_POS)) -#define MJPEG_REG_ID_LATCH_HBLK MJPEG_REG_ID_LATCH_HBLK -#define MJPEG_REG_ID_LATCH_HBLK_POS (8U) -#define MJPEG_REG_ID_LATCH_HBLK_LEN (4U) -#define MJPEG_REG_ID_LATCH_HBLK_MSK (((1U << MJPEG_REG_ID_LATCH_HBLK_LEN) - 1) << MJPEG_REG_ID_LATCH_HBLK_POS) -#define MJPEG_REG_ID_LATCH_HBLK_UMSK (~(((1U << MJPEG_REG_ID_LATCH_HBLK_LEN) - 1) << MJPEG_REG_ID_LATCH_HBLK_POS)) - -/* 0x1FC : mjpeg_dummy_reg */ -#define MJPEG_DUMMY_REG_OFFSET (0x1FC) -#define MJPEG_DUMMY_REG MJPEG_DUMMY_REG -#define MJPEG_DUMMY_REG_POS (0U) -#define MJPEG_DUMMY_REG_LEN (32U) -#define MJPEG_DUMMY_REG_MSK (((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS) -#define MJPEG_DUMMY_REG_UMSK (~(((1U << MJPEG_DUMMY_REG_LEN) - 1) << MJPEG_DUMMY_REG_POS)) - -struct mjpeg_reg { - /* 0x0 : mjpeg_control_1 */ - union { - struct { - uint32_t reg_mjpeg_enable : 1; /* [ 0], r/w, 0x0 */ - uint32_t reg_mjpeg_bit_order : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_order_u_even : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t reg_last_hf_wblk_dmy : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_last_hf_hblk_dmy : 1; /* [ 5], r/w, 0x0 */ - uint32_t reg_reflect_dmy : 1; /* [ 6], r/w, 0x0 */ - uint32_t reg_read_fwrap : 1; /* [ 7], r/w, 0x1 */ - uint32_t reg_w_xlen : 3; /* [10: 8], r/w, 0x3 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t reg_yuv_mode : 2; /* [13:12], r/w, 0x0 */ - uint32_t reserved_14_23 : 10; /* [23:14], rsvd, 0x0 */ - uint32_t reg_mjpeg_hw_frame : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_control_1; - - /* 0x4 : mjpeg_control_2 */ - union { - struct { - uint32_t reg_sw_frame : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5 : 1; /* [ 5], rsvd, 0x0 */ - uint32_t reg_sw_kick : 1; /* [ 6], w1p, 0x0 */ - uint32_t reg_sw_kick_mode : 1; /* [ 7], r/w, 0x0 */ - uint32_t reg_mjpeg_sw_mode : 1; /* [ 8], r/w, 0x0 */ - uint32_t reg_mjpeg_sw_run : 1; /* [ 9], r/w, 0x0 */ - uint32_t reg_yy_dvp2axi_sel : 3; /* [12:10], r/w, 0x0 */ - uint32_t reg_uv_dvp2axi_sel : 3; /* [15:13], r/w, 0x1 */ - uint32_t reg_mjpeg_wait_cycle : 16; /* [31:16], r/w, 0x100 */ - } BF; - uint32_t WORD; - } mjpeg_control_2; - - /* 0x08 : mjpeg_yy_frame_addr */ - union { - struct { - uint32_t reg_yy_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } mjpeg_yy_frame_addr; - - /* 0x0C : mjpeg_uv_frame_addr */ - union { - struct { - uint32_t reg_uv_addr_start : 32; /* [31: 0], r/w, 0x80000000 */ - } BF; - uint32_t WORD; - } mjpeg_uv_frame_addr; - - /* 0x10 : mjpeg_yuv_mem */ - union { - struct { - uint32_t reg_yy_mem_hblk : 13; /* [12: 0], r/w, 0x2 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t reg_uv_mem_hblk : 13; /* [28:16], r/w, 0x2 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_yuv_mem; - - /* 0x14 : jpeg_frame_addr */ - union { - struct { - uint32_t reg_w_addr_start : 32; /* [31: 0], r/w, 0x80400000 */ - } BF; - uint32_t WORD; - } jpeg_frame_addr; - - /* 0x18 : jpeg_store_memory */ - union { - struct { - uint32_t reg_w_burst_cnt : 32; /* [31: 0], r/w, 0x4000 */ - } BF; - uint32_t WORD; - } jpeg_store_memory; - - /* 0x1C : mjpeg_control_3 */ - union { - struct { - uint32_t reg_int_normal_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t reg_int_cam_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t reg_int_mem_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reg_int_frame_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t sts_normal_int : 1; /* [ 4], r, 0x0 */ - uint32_t sts_cam_int : 1; /* [ 5], r, 0x0 */ - uint32_t sts_mem_int : 1; /* [ 6], r, 0x0 */ - uint32_t sts_frame_int : 1; /* [ 7], r, 0x0 */ - uint32_t mjpeg_idle : 1; /* [ 8], r, 0x1 */ - uint32_t mjpeg_func : 1; /* [ 9], r, 0x0 */ - uint32_t mjpeg_wait : 1; /* [ 10], r, 0x0 */ - uint32_t mjpeg_flsh : 1; /* [ 11], r, 0x0 */ - uint32_t mjpeg_mans : 1; /* [ 12], r, 0x0 */ - uint32_t mjpeg_manf : 1; /* [ 13], r, 0x0 */ - uint32_t axi_read_idle : 1; /* [ 14], r, 0x0 */ - uint32_t axi_write_idle : 1; /* [ 15], r, 0x0 */ - uint32_t reg_frame_cnt_trgr_int : 5; /* [20:16], r/w, 0x0 */ - uint32_t reg_int_idle_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t sts_idle_int : 1; /* [ 22], r, 0x0 */ - uint32_t reserved_23 : 1; /* [ 23], rsvd, 0x0 */ - uint32_t frame_valid_cnt : 5; /* [28:24], r, 0x0 */ - uint32_t reg_int_swap_en : 1; /* [ 29], r/w, 0x0 */ - uint32_t sts_swap_int : 1; /* [ 30], r, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_control_3; - - /* 0x20 : mjpeg_frame_fifo_pop */ - union { - struct { - uint32_t rfifo_pop : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_w_swap_clr : 1; /* [ 1], w1p, 0x0 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t reg_int_normal_clr : 1; /* [ 8], w1p, 0x0 */ - uint32_t reg_int_cam_clr : 1; /* [ 9], w1p, 0x0 */ - uint32_t reg_int_mem_clr : 1; /* [ 10], w1p, 0x0 */ - uint32_t reg_int_frame_clr : 1; /* [ 11], w1p, 0x0 */ - uint32_t reg_int_idle_clr : 1; /* [ 12], w1p, 0x0 */ - uint32_t reg_int_swap_clr : 1; /* [ 13], w1p, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_fifo_pop; - - /* 0x24 : mjpeg_frame_size */ - union { - struct { - uint32_t reg_frame_wblk : 12; /* [11: 0], r/w, 0xf */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_frame_hblk : 12; /* [27:16], r/w, 0x14 */ - uint32_t reserved_28_31 : 4; /* [31:28], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_size; - - /* 0x28 : mjpeg_header_byte */ - union { - struct { - uint32_t reg_head_byte : 12; /* [11: 0], r/w, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t reg_tail_exp : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t reg_y0_order : 2; /* [25:24], r/w, 0x0 */ - uint32_t reg_u0_order : 2; /* [27:26], r/w, 0x1 */ - uint32_t reg_y1_order : 2; /* [29:28], r/w, 0x2 */ - uint32_t reg_v0_order : 2; /* [31:30], r/w, 0x3 */ - } BF; - uint32_t WORD; - } mjpeg_header_byte; - - /* 0x2c reserved */ - uint8_t RESERVED0x2c[4]; - - /* 0x30 : mjpeg_swap_mode */ - union { - struct { - uint32_t reg_w_swap_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t sts_swap0_full : 1; /* [ 8], r, 0x0 */ - uint32_t sts_swap1_full : 1; /* [ 9], r, 0x0 */ - uint32_t sts_read_swap_idx : 1; /* [ 10], r, 0x0 */ - uint32_t sts_swap_fstart : 1; /* [ 11], r, 0x0 */ - uint32_t sts_swap_fend : 1; /* [ 12], r, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_swap_mode; - - /* 0x34 : mjpeg_swap_bit_cnt */ - union { - struct { - uint32_t frame_swap_end_bit_cnt : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_swap_bit_cnt; - - /* 0x38 : mjpeg_yuv_mem_sw */ - union { - struct { - uint32_t reg_sw_kick_hblk : 13; /* [12: 0], r/w, 0x2 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_yuv_mem_sw; - - /* 0x3c reserved */ - uint8_t RESERVED0x3c[4]; - - /* 0x40 : mjpeg_Y_frame_read_status_1 */ - union { - struct { - uint32_t yy_mem_hblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t yy_frm_hblk_r : 13; /* [28:16], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_Y_frame_read_status_1; - - /* 0x44 : mjpeg_Y_frame_read_status_2 */ - union { - struct { - uint32_t yy_wblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t yy_mem_rnd_r : 8; /* [23:16], r, 0x0 */ - uint32_t yy_frm_cnt_r : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_Y_frame_read_status_2; - - /* 0x48 : mjpeg_Y_frame_write_status */ - union { - struct { - uint32_t yy_mem_hblk_w : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t yy_mem_rnd_w : 8; /* [23:16], r, 0x0 */ - uint32_t yy_frm_cnt_w : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_Y_frame_write_status; - - /* 0x4C : mjpeg_UV_frame_read_status_1 */ - union { - struct { - uint32_t uv_mem_hblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_frm_hblk_r : 13; /* [28:16], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_UV_frame_read_status_1; - - /* 0x50 : mjpeg_UV_frame_read_status_2 */ - union { - struct { - uint32_t uv_wblk_r : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_mem_rnd_r : 8; /* [23:16], r, 0x0 */ - uint32_t uv_frm_cnt_r : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_UV_frame_read_status_2; - - /* 0x54 : mjpeg_UV_frame_write_status */ - union { - struct { - uint32_t uv_mem_hblk_w : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_mem_rnd_w : 8; /* [23:16], r, 0x0 */ - uint32_t uv_frm_cnt_w : 8; /* [31:24], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_UV_frame_write_status; - - /* 0x58 : mjpeg_frame_w_hblk_status */ - union { - struct { - uint32_t yy_frm_hblk_w : 13; /* [12: 0], r, 0x0 */ - uint32_t reserved_13_15 : 3; /* [15:13], rsvd, 0x0 */ - uint32_t uv_frm_hblk_w : 13; /* [28:16], r, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_w_hblk_status; - - /* 0x5c reserved */ - uint8_t RESERVED0x5c[36]; - - /* 0x80 : mjpeg_start_addr0 */ - union { - struct { - uint32_t frame_start_addr_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr0; - - /* 0x84 : mjpeg_bit_cnt0 */ - union { - struct { - uint32_t frame_bit_cnt_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt0; - - /* 0x88 : mjpeg_start_addr1 */ - union { - struct { - uint32_t frame_start_addr_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr1; - - /* 0x8C : mjpeg_bit_cnt1 */ - union { - struct { - uint32_t frame_bit_cnt_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt1; - - /* 0x90 : mjpeg_start_addr2 */ - union { - struct { - uint32_t frame_start_addr_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr2; - - /* 0x94 : mjpeg_bit_cnt2 */ - union { - struct { - uint32_t frame_bit_cnt_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt2; - - /* 0x98 : mjpeg_start_addr3 */ - union { - struct { - uint32_t frame_start_addr_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_start_addr3; - - /* 0x9C : mjpeg_bit_cnt3 */ - union { - struct { - uint32_t frame_bit_cnt_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_bit_cnt3; - - /* 0xa0 reserved */ - uint8_t RESERVED0xa0[96]; - - /* 0x100 : mjpeg_q_enc */ - union { - struct { - uint32_t frame_q_sram_0 : 1; /* [ 0], r, 0x0 */ - uint32_t frame_q_sram_1 : 1; /* [ 1], r, 0x0 */ - uint32_t frame_q_sram_2 : 1; /* [ 2], r, 0x0 */ - uint32_t frame_q_sram_3 : 1; /* [ 3], r, 0x0 */ - uint32_t reserved_4_23 : 20; /* [23: 4], rsvd, 0x0 */ - uint32_t reg_q_sram_sw : 1; /* [ 24], w1p, 0x0 */ - uint32_t sts_q_sram_enc : 1; /* [ 25], r, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_q_enc; - - /* 0x104 reserved */ - uint8_t RESERVED0x104[12]; - - /* 0x110 : mjpeg_frame_id_10 */ - union { - struct { - uint32_t frame_id_0 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_1 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_id_10; - - /* 0x114 : mjpeg_frame_id_32 */ - union { - struct { - uint32_t frame_id_2 : 16; /* [15: 0], r, 0x0 */ - uint32_t frame_id_3 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_frame_id_32; - - /* 0x118 reserved */ - uint8_t RESERVED0x118[216]; - - /* 0x1F0 : mjpeg_debug */ - union { - struct { - uint32_t reg_mjpeg_dbg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t reg_mjpeg_dbg_sel : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t reg_id_latch_hblk : 4; /* [11: 8], r/w, 0x1 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_debug; - - /* 0x1f4 reserved */ - uint8_t RESERVED0x1f4[8]; - - /* 0x1FC : mjpeg_dummy_reg */ - union { - struct { - uint32_t mjpeg_dummy_reg : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } mjpeg_dummy_reg; -}; - -typedef volatile struct mjpeg_reg mjpeg_reg_t; - -#endif /* __MJPEG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_blend_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_blend_reg.h deleted file mode 100644 index 89d54af045..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_blend_reg.h +++ /dev/null @@ -1,500 +0,0 @@ -/** - ****************************************************************************** - * @file osd_blend_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_BLEND_REG_H__ -#define __OSD_BLEND_REG_H__ - -#include "bl808.h" - -/* 0x0 : obnd_layer_xconfig */ -#define OSD_BLEND_OBND_LAYER_XCONFIG_OFFSET (0x0) -#define OSD_BLEND_OBND_X_MIN OSD_BLEND_OBND_X_MIN -#define OSD_BLEND_OBND_X_MIN_POS (0U) -#define OSD_BLEND_OBND_X_MIN_LEN (11U) -#define OSD_BLEND_OBND_X_MIN_MSK (((1U << OSD_BLEND_OBND_X_MIN_LEN) - 1) << OSD_BLEND_OBND_X_MIN_POS) -#define OSD_BLEND_OBND_X_MIN_UMSK (~(((1U << OSD_BLEND_OBND_X_MIN_LEN) - 1) << OSD_BLEND_OBND_X_MIN_POS)) -#define OSD_BLEND_OBND_X_MAX OSD_BLEND_OBND_X_MAX -#define OSD_BLEND_OBND_X_MAX_POS (16U) -#define OSD_BLEND_OBND_X_MAX_LEN (11U) -#define OSD_BLEND_OBND_X_MAX_MSK (((1U << OSD_BLEND_OBND_X_MAX_LEN) - 1) << OSD_BLEND_OBND_X_MAX_POS) -#define OSD_BLEND_OBND_X_MAX_UMSK (~(((1U << OSD_BLEND_OBND_X_MAX_LEN) - 1) << OSD_BLEND_OBND_X_MAX_POS)) - -/* 0x4 : obnd_layer_yconfig */ -#define OSD_BLEND_OBND_LAYER_YCONFIG_OFFSET (0x4) -#define OSD_BLEND_OBND_Y_MIN OSD_BLEND_OBND_Y_MIN -#define OSD_BLEND_OBND_Y_MIN_POS (0U) -#define OSD_BLEND_OBND_Y_MIN_LEN (11U) -#define OSD_BLEND_OBND_Y_MIN_MSK (((1U << OSD_BLEND_OBND_Y_MIN_LEN) - 1) << OSD_BLEND_OBND_Y_MIN_POS) -#define OSD_BLEND_OBND_Y_MIN_UMSK (~(((1U << OSD_BLEND_OBND_Y_MIN_LEN) - 1) << OSD_BLEND_OBND_Y_MIN_POS)) -#define OSD_BLEND_OBND_Y_MAX OSD_BLEND_OBND_Y_MAX -#define OSD_BLEND_OBND_Y_MAX_POS (16U) -#define OSD_BLEND_OBND_Y_MAX_LEN (11U) -#define OSD_BLEND_OBND_Y_MAX_MSK (((1U << OSD_BLEND_OBND_Y_MAX_LEN) - 1) << OSD_BLEND_OBND_Y_MAX_POS) -#define OSD_BLEND_OBND_Y_MAX_UMSK (~(((1U << OSD_BLEND_OBND_Y_MAX_LEN) - 1) << OSD_BLEND_OBND_Y_MAX_POS)) - -/* 0x8 : obnd_mem_config0 */ -#define OSD_BLEND_OBND_MEM_CONFIG0_OFFSET (0x8) -#define OSD_BLEND_OBND_FORCE_SH OSD_BLEND_OBND_FORCE_SH -#define OSD_BLEND_OBND_FORCE_SH_POS (0U) -#define OSD_BLEND_OBND_FORCE_SH_LEN (1U) -#define OSD_BLEND_OBND_FORCE_SH_MSK (((1U << OSD_BLEND_OBND_FORCE_SH_LEN) - 1) << OSD_BLEND_OBND_FORCE_SH_POS) -#define OSD_BLEND_OBND_FORCE_SH_UMSK (~(((1U << OSD_BLEND_OBND_FORCE_SH_LEN) - 1) << OSD_BLEND_OBND_FORCE_SH_POS)) -#define OSD_BLEND_OBND_LAYER_EN OSD_BLEND_OBND_LAYER_EN -#define OSD_BLEND_OBND_LAYER_EN_POS (15U) -#define OSD_BLEND_OBND_LAYER_EN_LEN (1U) -#define OSD_BLEND_OBND_LAYER_EN_MSK (((1U << OSD_BLEND_OBND_LAYER_EN_LEN) - 1) << OSD_BLEND_OBND_LAYER_EN_POS) -#define OSD_BLEND_OBND_LAYER_EN_UMSK (~(((1U << OSD_BLEND_OBND_LAYER_EN_LEN) - 1) << OSD_BLEND_OBND_LAYER_EN_POS)) - -/* 0xC : obnd_mem_config1 */ -#define OSD_BLEND_OBND_MEM_CONFIG1_OFFSET (0xC) -#define OSD_BLEND_OBND_MEM_ADDR OSD_BLEND_OBND_MEM_ADDR -#define OSD_BLEND_OBND_MEM_ADDR_POS (0U) -#define OSD_BLEND_OBND_MEM_ADDR_LEN (32U) -#define OSD_BLEND_OBND_MEM_ADDR_MSK (((1U << OSD_BLEND_OBND_MEM_ADDR_LEN) - 1) << OSD_BLEND_OBND_MEM_ADDR_POS) -#define OSD_BLEND_OBND_MEM_ADDR_UMSK (~(((1U << OSD_BLEND_OBND_MEM_ADDR_LEN) - 1) << OSD_BLEND_OBND_MEM_ADDR_POS)) - -/* 0x10 : obnd_mem_config2 */ -#define OSD_BLEND_OBND_MEM_CONFIG2_OFFSET (0x10) -#define OSD_BLEND_OBND_MEM_DW_CNT OSD_BLEND_OBND_MEM_DW_CNT -#define OSD_BLEND_OBND_MEM_DW_CNT_POS (0U) -#define OSD_BLEND_OBND_MEM_DW_CNT_LEN (32U) -#define OSD_BLEND_OBND_MEM_DW_CNT_MSK (((1U << OSD_BLEND_OBND_MEM_DW_CNT_LEN) - 1) << OSD_BLEND_OBND_MEM_DW_CNT_POS) -#define OSD_BLEND_OBND_MEM_DW_CNT_UMSK (~(((1U << OSD_BLEND_OBND_MEM_DW_CNT_LEN) - 1) << OSD_BLEND_OBND_MEM_DW_CNT_POS)) - -/* 0x14 : obnd_layer_config0 */ -#define OSD_BLEND_OBND_LAYER_CONFIG0_OFFSET (0x14) -#define OSD_BLEND_OBND_COLOR_FORMAT OSD_BLEND_OBND_COLOR_FORMAT -#define OSD_BLEND_OBND_COLOR_FORMAT_POS (0U) -#define OSD_BLEND_OBND_COLOR_FORMAT_LEN (5U) -#define OSD_BLEND_OBND_COLOR_FORMAT_MSK (((1U << OSD_BLEND_OBND_COLOR_FORMAT_LEN) - 1) << OSD_BLEND_OBND_COLOR_FORMAT_POS) -#define OSD_BLEND_OBND_COLOR_FORMAT_UMSK (~(((1U << OSD_BLEND_OBND_COLOR_FORMAT_LEN) - 1) << OSD_BLEND_OBND_COLOR_FORMAT_POS)) -#define OSD_BLEND_OBND_ORDER_A OSD_BLEND_OBND_ORDER_A -#define OSD_BLEND_OBND_ORDER_A_POS (8U) -#define OSD_BLEND_OBND_ORDER_A_LEN (2U) -#define OSD_BLEND_OBND_ORDER_A_MSK (((1U << OSD_BLEND_OBND_ORDER_A_LEN) - 1) << OSD_BLEND_OBND_ORDER_A_POS) -#define OSD_BLEND_OBND_ORDER_A_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_A_LEN) - 1) << OSD_BLEND_OBND_ORDER_A_POS)) -#define OSD_BLEND_OBND_ORDER_RV OSD_BLEND_OBND_ORDER_RV -#define OSD_BLEND_OBND_ORDER_RV_POS (10U) -#define OSD_BLEND_OBND_ORDER_RV_LEN (2U) -#define OSD_BLEND_OBND_ORDER_RV_MSK (((1U << OSD_BLEND_OBND_ORDER_RV_LEN) - 1) << OSD_BLEND_OBND_ORDER_RV_POS) -#define OSD_BLEND_OBND_ORDER_RV_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_RV_LEN) - 1) << OSD_BLEND_OBND_ORDER_RV_POS)) -#define OSD_BLEND_OBND_ORDER_GY OSD_BLEND_OBND_ORDER_GY -#define OSD_BLEND_OBND_ORDER_GY_POS (12U) -#define OSD_BLEND_OBND_ORDER_GY_LEN (2U) -#define OSD_BLEND_OBND_ORDER_GY_MSK (((1U << OSD_BLEND_OBND_ORDER_GY_LEN) - 1) << OSD_BLEND_OBND_ORDER_GY_POS) -#define OSD_BLEND_OBND_ORDER_GY_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_GY_LEN) - 1) << OSD_BLEND_OBND_ORDER_GY_POS)) -#define OSD_BLEND_OBND_ORDER_BU OSD_BLEND_OBND_ORDER_BU -#define OSD_BLEND_OBND_ORDER_BU_POS (14U) -#define OSD_BLEND_OBND_ORDER_BU_LEN (2U) -#define OSD_BLEND_OBND_ORDER_BU_MSK (((1U << OSD_BLEND_OBND_ORDER_BU_LEN) - 1) << OSD_BLEND_OBND_ORDER_BU_POS) -#define OSD_BLEND_OBND_ORDER_BU_UMSK (~(((1U << OSD_BLEND_OBND_ORDER_BU_LEN) - 1) << OSD_BLEND_OBND_ORDER_BU_POS)) -#define OSD_BLEND_OBND_GLOBAL_A_EN OSD_BLEND_OBND_GLOBAL_A_EN -#define OSD_BLEND_OBND_GLOBAL_A_EN_POS (16U) -#define OSD_BLEND_OBND_GLOBAL_A_EN_LEN (1U) -#define OSD_BLEND_OBND_GLOBAL_A_EN_MSK (((1U << OSD_BLEND_OBND_GLOBAL_A_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_EN_POS) -#define OSD_BLEND_OBND_GLOBAL_A_EN_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_A_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_EN_POS)) -#define OSD_BLEND_OBND_GLOBAL_A OSD_BLEND_OBND_GLOBAL_A -#define OSD_BLEND_OBND_GLOBAL_A_POS (24U) -#define OSD_BLEND_OBND_GLOBAL_A_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_A_MSK (((1U << OSD_BLEND_OBND_GLOBAL_A_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_POS) -#define OSD_BLEND_OBND_GLOBAL_A_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_A_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_A_POS)) - -/* 0x18 : obnd_layer_config1 */ -#define OSD_BLEND_OBND_LAYER_CONFIG1_OFFSET (0x18) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN OSD_BLEND_OBND_GLOBAL_COLOR_EN -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_POS (0U) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_LEN (1U) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_MSK (((1U << OSD_BLEND_OBND_GLOBAL_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_COLOR_EN_POS) -#define OSD_BLEND_OBND_GLOBAL_COLOR_EN_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_COLOR_EN_POS)) -#define OSD_BLEND_OBND_GLOBAL_RV OSD_BLEND_OBND_GLOBAL_RV -#define OSD_BLEND_OBND_GLOBAL_RV_POS (8U) -#define OSD_BLEND_OBND_GLOBAL_RV_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_RV_MSK (((1U << OSD_BLEND_OBND_GLOBAL_RV_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_RV_POS) -#define OSD_BLEND_OBND_GLOBAL_RV_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_RV_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_RV_POS)) -#define OSD_BLEND_OBND_GLOBAL_GY OSD_BLEND_OBND_GLOBAL_GY -#define OSD_BLEND_OBND_GLOBAL_GY_POS (16U) -#define OSD_BLEND_OBND_GLOBAL_GY_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_GY_MSK (((1U << OSD_BLEND_OBND_GLOBAL_GY_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_GY_POS) -#define OSD_BLEND_OBND_GLOBAL_GY_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_GY_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_GY_POS)) -#define OSD_BLEND_OBND_GLOBAL_BU OSD_BLEND_OBND_GLOBAL_BU -#define OSD_BLEND_OBND_GLOBAL_BU_POS (24U) -#define OSD_BLEND_OBND_GLOBAL_BU_LEN (8U) -#define OSD_BLEND_OBND_GLOBAL_BU_MSK (((1U << OSD_BLEND_OBND_GLOBAL_BU_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_BU_POS) -#define OSD_BLEND_OBND_GLOBAL_BU_UMSK (~(((1U << OSD_BLEND_OBND_GLOBAL_BU_LEN) - 1) << OSD_BLEND_OBND_GLOBAL_BU_POS)) - -/* 0x1C : obnd_layer_config2 */ -#define OSD_BLEND_OBND_LAYER_CONFIG2_OFFSET (0x1C) -#define OSD_BLEND_OBND_KEY_PALETTE_EN OSD_BLEND_OBND_KEY_PALETTE_EN -#define OSD_BLEND_OBND_KEY_PALETTE_EN_POS (0U) -#define OSD_BLEND_OBND_KEY_PALETTE_EN_LEN (1U) -#define OSD_BLEND_OBND_KEY_PALETTE_EN_MSK (((1U << OSD_BLEND_OBND_KEY_PALETTE_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_PALETTE_EN_POS) -#define OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_PALETTE_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_PALETTE_EN_POS)) -#define OSD_BLEND_OBND_KEY_INDEX_INV OSD_BLEND_OBND_KEY_INDEX_INV -#define OSD_BLEND_OBND_KEY_INDEX_INV_POS (1U) -#define OSD_BLEND_OBND_KEY_INDEX_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_INDEX_INV_MSK (((1U << OSD_BLEND_OBND_KEY_INDEX_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_INV_POS) -#define OSD_BLEND_OBND_KEY_INDEX_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_INDEX_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_INV_POS)) -#define OSD_BLEND_OBND_KEY_INDEX_MIN OSD_BLEND_OBND_KEY_INDEX_MIN -#define OSD_BLEND_OBND_KEY_INDEX_MIN_POS (8U) -#define OSD_BLEND_OBND_KEY_INDEX_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_INDEX_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_INDEX_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) -#define OSD_BLEND_OBND_KEY_INDEX_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_INDEX_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MIN_POS)) -#define OSD_BLEND_OBND_KEY_INDEX_MAX OSD_BLEND_OBND_KEY_INDEX_MAX -#define OSD_BLEND_OBND_KEY_INDEX_MAX_POS (16U) -#define OSD_BLEND_OBND_KEY_INDEX_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_INDEX_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_INDEX_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) -#define OSD_BLEND_OBND_KEY_INDEX_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_INDEX_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_INDEX_MAX_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX OSD_BLEND_OBND_KEY_REPLACE_INDEX -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS (24U) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_INDEX_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_INDEX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_INDEX_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS)) - -/* 0x20 : obnd_layer_config3 */ -#define OSD_BLEND_OBND_LAYER_CONFIG3_OFFSET (0x20) -#define OSD_BLEND_OBND_KEY_A_MIN OSD_BLEND_OBND_KEY_A_MIN -#define OSD_BLEND_OBND_KEY_A_MIN_POS (0U) -#define OSD_BLEND_OBND_KEY_A_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_A_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_A_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MIN_POS) -#define OSD_BLEND_OBND_KEY_A_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_A_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MIN_POS)) -#define OSD_BLEND_OBND_KEY_A_MAX OSD_BLEND_OBND_KEY_A_MAX -#define OSD_BLEND_OBND_KEY_A_MAX_POS (8U) -#define OSD_BLEND_OBND_KEY_A_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_A_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_A_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MAX_POS) -#define OSD_BLEND_OBND_KEY_A_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_A_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_A_MAX_POS)) -#define OSD_BLEND_OBND_KEY_RV_MIN OSD_BLEND_OBND_KEY_RV_MIN -#define OSD_BLEND_OBND_KEY_RV_MIN_POS (16U) -#define OSD_BLEND_OBND_KEY_RV_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_RV_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_RV_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MIN_POS) -#define OSD_BLEND_OBND_KEY_RV_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_RV_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MIN_POS)) -#define OSD_BLEND_OBND_KEY_RV_MAX OSD_BLEND_OBND_KEY_RV_MAX -#define OSD_BLEND_OBND_KEY_RV_MAX_POS (24U) -#define OSD_BLEND_OBND_KEY_RV_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_RV_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_RV_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MAX_POS) -#define OSD_BLEND_OBND_KEY_RV_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_RV_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_MAX_POS)) - -/* 0x24 : obnd_layer_config4 */ -#define OSD_BLEND_OBND_LAYER_CONFIG4_OFFSET (0x24) -#define OSD_BLEND_OBND_KEY_GY_MIN OSD_BLEND_OBND_KEY_GY_MIN -#define OSD_BLEND_OBND_KEY_GY_MIN_POS (0U) -#define OSD_BLEND_OBND_KEY_GY_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_GY_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_GY_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MIN_POS) -#define OSD_BLEND_OBND_KEY_GY_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_GY_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MIN_POS)) -#define OSD_BLEND_OBND_KEY_GY_MAX OSD_BLEND_OBND_KEY_GY_MAX -#define OSD_BLEND_OBND_KEY_GY_MAX_POS (8U) -#define OSD_BLEND_OBND_KEY_GY_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_GY_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_GY_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MAX_POS) -#define OSD_BLEND_OBND_KEY_GY_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_GY_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_MAX_POS)) -#define OSD_BLEND_OBND_KEY_BU_MIN OSD_BLEND_OBND_KEY_BU_MIN -#define OSD_BLEND_OBND_KEY_BU_MIN_POS (16U) -#define OSD_BLEND_OBND_KEY_BU_MIN_LEN (8U) -#define OSD_BLEND_OBND_KEY_BU_MIN_MSK (((1U << OSD_BLEND_OBND_KEY_BU_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MIN_POS) -#define OSD_BLEND_OBND_KEY_BU_MIN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_BU_MIN_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MIN_POS)) -#define OSD_BLEND_OBND_KEY_BU_MAX OSD_BLEND_OBND_KEY_BU_MAX -#define OSD_BLEND_OBND_KEY_BU_MAX_POS (24U) -#define OSD_BLEND_OBND_KEY_BU_MAX_LEN (8U) -#define OSD_BLEND_OBND_KEY_BU_MAX_MSK (((1U << OSD_BLEND_OBND_KEY_BU_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MAX_POS) -#define OSD_BLEND_OBND_KEY_BU_MAX_UMSK (~(((1U << OSD_BLEND_OBND_KEY_BU_MAX_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_MAX_POS)) - -/* 0x28 : obnd_layer_config5 */ -#define OSD_BLEND_OBND_LAYER_CONFIG5_OFFSET (0x28) -#define OSD_BLEND_OBND_KEY_REPLACE_A OSD_BLEND_OBND_KEY_REPLACE_A -#define OSD_BLEND_OBND_KEY_REPLACE_A_POS (0U) -#define OSD_BLEND_OBND_KEY_REPLACE_A_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_A_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_A_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_A_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_A_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_A_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_A_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_RV OSD_BLEND_OBND_KEY_REPLACE_RV -#define OSD_BLEND_OBND_KEY_REPLACE_RV_POS (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_RV_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_RV_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_RV_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_RV_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_RV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_RV_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_RV_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_GY OSD_BLEND_OBND_KEY_REPLACE_GY -#define OSD_BLEND_OBND_KEY_REPLACE_GY_POS (16U) -#define OSD_BLEND_OBND_KEY_REPLACE_GY_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_GY_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_GY_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_GY_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_GY_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_GY_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_GY_POS)) -#define OSD_BLEND_OBND_KEY_REPLACE_BU OSD_BLEND_OBND_KEY_REPLACE_BU -#define OSD_BLEND_OBND_KEY_REPLACE_BU_POS (24U) -#define OSD_BLEND_OBND_KEY_REPLACE_BU_LEN (8U) -#define OSD_BLEND_OBND_KEY_REPLACE_BU_MSK (((1U << OSD_BLEND_OBND_KEY_REPLACE_BU_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_BU_POS) -#define OSD_BLEND_OBND_KEY_REPLACE_BU_UMSK (~(((1U << OSD_BLEND_OBND_KEY_REPLACE_BU_LEN) - 1) << OSD_BLEND_OBND_KEY_REPLACE_BU_POS)) - -/* 0x2C : obnd_layer_config6 */ -#define OSD_BLEND_OBND_LAYER_CONFIG6_OFFSET (0x2C) -#define OSD_BLEND_OBND_KEY_COLOR_EN OSD_BLEND_OBND_KEY_COLOR_EN -#define OSD_BLEND_OBND_KEY_COLOR_EN_POS (0U) -#define OSD_BLEND_OBND_KEY_COLOR_EN_LEN (1U) -#define OSD_BLEND_OBND_KEY_COLOR_EN_MSK (((1U << OSD_BLEND_OBND_KEY_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_COLOR_EN_POS) -#define OSD_BLEND_OBND_KEY_COLOR_EN_UMSK (~(((1U << OSD_BLEND_OBND_KEY_COLOR_EN_LEN) - 1) << OSD_BLEND_OBND_KEY_COLOR_EN_POS)) -#define OSD_BLEND_OBND_KEY_A_INV OSD_BLEND_OBND_KEY_A_INV -#define OSD_BLEND_OBND_KEY_A_INV_POS (1U) -#define OSD_BLEND_OBND_KEY_A_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_A_INV_MSK (((1U << OSD_BLEND_OBND_KEY_A_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_A_INV_POS) -#define OSD_BLEND_OBND_KEY_A_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_A_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_A_INV_POS)) -#define OSD_BLEND_OBND_KEY_RV_INV OSD_BLEND_OBND_KEY_RV_INV -#define OSD_BLEND_OBND_KEY_RV_INV_POS (2U) -#define OSD_BLEND_OBND_KEY_RV_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_RV_INV_MSK (((1U << OSD_BLEND_OBND_KEY_RV_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_INV_POS) -#define OSD_BLEND_OBND_KEY_RV_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_RV_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_RV_INV_POS)) -#define OSD_BLEND_OBND_KEY_GY_INV OSD_BLEND_OBND_KEY_GY_INV -#define OSD_BLEND_OBND_KEY_GY_INV_POS (3U) -#define OSD_BLEND_OBND_KEY_GY_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_GY_INV_MSK (((1U << OSD_BLEND_OBND_KEY_GY_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_INV_POS) -#define OSD_BLEND_OBND_KEY_GY_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_GY_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_GY_INV_POS)) -#define OSD_BLEND_OBND_KEY_BU_INV OSD_BLEND_OBND_KEY_BU_INV -#define OSD_BLEND_OBND_KEY_BU_INV_POS (4U) -#define OSD_BLEND_OBND_KEY_BU_INV_LEN (1U) -#define OSD_BLEND_OBND_KEY_BU_INV_MSK (((1U << OSD_BLEND_OBND_KEY_BU_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_INV_POS) -#define OSD_BLEND_OBND_KEY_BU_INV_UMSK (~(((1U << OSD_BLEND_OBND_KEY_BU_INV_LEN) - 1) << OSD_BLEND_OBND_KEY_BU_INV_POS)) -#define OSD_BLEND_OBND_UPDATE_TRIGGER OSD_BLEND_OBND_UPDATE_TRIGGER -#define OSD_BLEND_OBND_UPDATE_TRIGGER_POS (5U) -#define OSD_BLEND_OBND_UPDATE_TRIGGER_LEN (1U) -#define OSD_BLEND_OBND_UPDATE_TRIGGER_MSK (((1U << OSD_BLEND_OBND_UPDATE_TRIGGER_LEN) - 1) << OSD_BLEND_OBND_UPDATE_TRIGGER_POS) -#define OSD_BLEND_OBND_UPDATE_TRIGGER_UMSK (~(((1U << OSD_BLEND_OBND_UPDATE_TRIGGER_LEN) - 1) << OSD_BLEND_OBND_UPDATE_TRIGGER_POS)) -#define OSD_BLEND_OBND_UPDATE_INDEX OSD_BLEND_OBND_UPDATE_INDEX -#define OSD_BLEND_OBND_UPDATE_INDEX_POS (8U) -#define OSD_BLEND_OBND_UPDATE_INDEX_LEN (8U) -#define OSD_BLEND_OBND_UPDATE_INDEX_MSK (((1U << OSD_BLEND_OBND_UPDATE_INDEX_LEN) - 1) << OSD_BLEND_OBND_UPDATE_INDEX_POS) -#define OSD_BLEND_OBND_UPDATE_INDEX_UMSK (~(((1U << OSD_BLEND_OBND_UPDATE_INDEX_LEN) - 1) << OSD_BLEND_OBND_UPDATE_INDEX_POS)) - -/* 0x30 : obnd_layer_config7 */ -#define OSD_BLEND_OBND_LAYER_CONFIG7_OFFSET (0x30) -#define OSD_BLEND_OBND_UPDATE_COLOR OSD_BLEND_OBND_UPDATE_COLOR -#define OSD_BLEND_OBND_UPDATE_COLOR_POS (0U) -#define OSD_BLEND_OBND_UPDATE_COLOR_LEN (32U) -#define OSD_BLEND_OBND_UPDATE_COLOR_MSK (((1U << OSD_BLEND_OBND_UPDATE_COLOR_LEN) - 1) << OSD_BLEND_OBND_UPDATE_COLOR_POS) -#define OSD_BLEND_OBND_UPDATE_COLOR_UMSK (~(((1U << OSD_BLEND_OBND_UPDATE_COLOR_LEN) - 1) << OSD_BLEND_OBND_UPDATE_COLOR_POS)) - -/* 0x40 : obnd_error */ -#define OSD_BLEND_OBND_ERROR_OFFSET (0x40) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W OSD_BLEND_REG_RFIFO_DRAIN_CLR_W -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_POS (0U) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_LEN (1U) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_MSK (((1U << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_POS) -#define OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_UMSK (~(((1U << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_CLR_W_POS)) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W OSD_BLEND_REG_RFIFO_DRAIN_MASK_W -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_POS (1U) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_LEN (1U) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_MSK (((1U << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_POS) -#define OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_UMSK (~(((1U << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_LEN) - 1) << OSD_BLEND_REG_RFIFO_DRAIN_MASK_W_POS)) -#define OSD_BLEND_STS_RFIFO_DRAIN_R OSD_BLEND_STS_RFIFO_DRAIN_R -#define OSD_BLEND_STS_RFIFO_DRAIN_R_POS (16U) -#define OSD_BLEND_STS_RFIFO_DRAIN_R_LEN (1U) -#define OSD_BLEND_STS_RFIFO_DRAIN_R_MSK (((1U << OSD_BLEND_STS_RFIFO_DRAIN_R_LEN) - 1) << OSD_BLEND_STS_RFIFO_DRAIN_R_POS) -#define OSD_BLEND_STS_RFIFO_DRAIN_R_UMSK (~(((1U << OSD_BLEND_STS_RFIFO_DRAIN_R_LEN) - 1) << OSD_BLEND_STS_RFIFO_DRAIN_R_POS)) - -/* 0x44 : obnd_sh */ -#define OSD_BLEND_OBND_SH_OFFSET (0x44) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT OSD_BLEND_OBND_LAYER_MEM_REQ_CNT -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_POS (0U) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_LEN (32U) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_MSK (((1U << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_LEN) - 1) << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_POS) -#define OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_UMSK (~(((1U << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_LEN) - 1) << OSD_BLEND_OBND_LAYER_MEM_REQ_CNT_POS)) - -struct osd_blend_reg { - /* 0x0 : obnd_layer_xconfig */ - union { - struct { - uint32_t obnd_x_min : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t obnd_x_max : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_xconfig; - - /* 0x4 : obnd_layer_yconfig */ - union { - struct { - uint32_t obnd_y_min : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t obnd_y_max : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_yconfig; - - /* 0x8 : obnd_mem_config0 */ - union { - struct { - uint32_t obnd_force_sh : 1; /* [ 0], w1p, 0x0 */ - uint32_t reserved_1_14 : 14; /* [14: 1], rsvd, 0x0 */ - uint32_t obnd_layer_en : 1; /* [ 15], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_mem_config0; - - /* 0xC : obnd_mem_config1 */ - union { - struct { - uint32_t obnd_mem_addr : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_mem_config1; - - /* 0x10 : obnd_mem_config2 */ - union { - struct { - uint32_t obnd_mem_dw_cnt : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_mem_config2; - - /* 0x14 : obnd_layer_config0 */ - union { - struct { - uint32_t obnd_color_format : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t obnd_order_a : 2; /* [ 9: 8], r/w, 0x0 */ - uint32_t obnd_order_rv : 2; /* [11:10], r/w, 0x0 */ - uint32_t obnd_order_gy : 2; /* [13:12], r/w, 0x0 */ - uint32_t obnd_order_bu : 2; /* [15:14], r/w, 0x0 */ - uint32_t obnd_global_a_en : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t obnd_global_a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config0; - - /* 0x18 : obnd_layer_config1 */ - union { - struct { - uint32_t obnd_global_color_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_7 : 7; /* [ 7: 1], rsvd, 0x0 */ - uint32_t obnd_global_rv : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_global_gy : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_global_bu : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config1; - - /* 0x1C : obnd_layer_config2 */ - union { - struct { - uint32_t obnd_key_palette_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t obnd_key_index_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_7 : 6; /* [ 7: 2], rsvd, 0x0 */ - uint32_t obnd_key_index_min : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_index_max : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_replace_index : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config2; - - /* 0x20 : obnd_layer_config3 */ - union { - struct { - uint32_t obnd_key_a_min : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t obnd_key_a_max : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_rv_min : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_rv_max : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config3; - - /* 0x24 : obnd_layer_config4 */ - union { - struct { - uint32_t obnd_key_gy_min : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t obnd_key_gy_max : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_bu_min : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_bu_max : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config4; - - /* 0x28 : obnd_layer_config5 */ - union { - struct { - uint32_t obnd_key_replace_a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t obnd_key_replace_rv : 8; /* [15: 8], r/w, 0x0 */ - uint32_t obnd_key_replace_gy : 8; /* [23:16], r/w, 0x0 */ - uint32_t obnd_key_replace_bu : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config5; - - /* 0x2C : obnd_layer_config6 */ - union { - struct { - uint32_t obnd_key_color_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t obnd_key_a_inv : 1; /* [ 1], r/w, 0x0 */ - uint32_t obnd_key_rv_inv : 1; /* [ 2], r/w, 0x0 */ - uint32_t obnd_key_gy_inv : 1; /* [ 3], r/w, 0x0 */ - uint32_t obnd_key_bu_inv : 1; /* [ 4], r/w, 0x0 */ - uint32_t obnd_update_trigger : 1; /* [ 5], w1p, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t obnd_update_index : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config6; - - /* 0x30 : obnd_layer_config7 */ - union { - struct { - uint32_t obnd_update_color : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } obnd_layer_config7; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[12]; - - /* 0x40 : obnd_error */ - union { - struct { - uint32_t reg_rfifo_drain_clr_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_rfifo_drain_mask_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_15 : 14; /* [15: 2], rsvd, 0x0 */ - uint32_t sts_rfifo_drain_r : 1; /* [ 16], r, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } obnd_error; - - /* 0x44 : obnd_sh */ - union { - struct { - uint32_t obnd_layer_mem_req_cnt : 32; /* [31: 0], r/w, 0x1000 */ - } BF; - uint32_t WORD; - } obnd_sh; -}; - -typedef volatile struct osd_blend_reg osd_blend_reg_t; - -#endif /* __OSD_BLEND_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_h_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_h_reg.h deleted file mode 100644 index c1348a356e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_h_reg.h +++ /dev/null @@ -1,1382 +0,0 @@ -/** - ****************************************************************************** - * @file osd_draw_h_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_DRAW_H_REG_H__ -#define __OSD_DRAW_H_REG_H__ - -#include "bl808.h" - -/* 0x4 : draw_partial_config */ -#define OSD_DRAW_H_DRAW_PARTIAL_CONFIG_OFFSET (0x4) -#define OSD_DRAW_H_REG_DRAW_EN_H OSD_DRAW_H_REG_DRAW_EN_H -#define OSD_DRAW_H_REG_DRAW_EN_H_POS (0U) -#define OSD_DRAW_H_REG_DRAW_EN_H_LEN (16U) -#define OSD_DRAW_H_REG_DRAW_EN_H_MSK (((1U << OSD_DRAW_H_REG_DRAW_EN_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_EN_H_POS) -#define OSD_DRAW_H_REG_DRAW_EN_H_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_EN_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_EN_H_POS)) -#define OSD_DRAW_H_REG_DRAW_TYPE_H OSD_DRAW_H_REG_DRAW_TYPE_H -#define OSD_DRAW_H_REG_DRAW_TYPE_H_POS (16U) -#define OSD_DRAW_H_REG_DRAW_TYPE_H_LEN (16U) -#define OSD_DRAW_H_REG_DRAW_TYPE_H_MSK (((1U << OSD_DRAW_H_REG_DRAW_TYPE_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TYPE_H_POS) -#define OSD_DRAW_H_REG_DRAW_TYPE_H_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TYPE_H_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TYPE_H_POS)) - -/* 0x8 : draw_partial_yuv_config10 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG10_OFFSET (0x8) -#define OSD_DRAW_H_REG_DRAW_TH_10 OSD_DRAW_H_REG_DRAW_TH_10 -#define OSD_DRAW_H_REG_DRAW_TH_10_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_10_POS) -#define OSD_DRAW_H_REG_DRAW_TH_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_10_POS)) -#define OSD_DRAW_H_REG_DRAW_V_10 OSD_DRAW_H_REG_DRAW_V_10 -#define OSD_DRAW_H_REG_DRAW_V_10_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_10_POS) -#define OSD_DRAW_H_REG_DRAW_V_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_10_POS)) -#define OSD_DRAW_H_REG_DRAW_U_10 OSD_DRAW_H_REG_DRAW_U_10 -#define OSD_DRAW_H_REG_DRAW_U_10_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_10_POS) -#define OSD_DRAW_H_REG_DRAW_U_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_10_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_10 OSD_DRAW_H_REG_DRAW_Y_10 -#define OSD_DRAW_H_REG_DRAW_Y_10_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_10_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_10_POS) -#define OSD_DRAW_H_REG_DRAW_Y_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_10_POS)) - -/* 0xC : draw_partial_x_config10 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG10_OFFSET (0xC) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10 OSD_DRAW_H_REG_DRAW_X_MIN_10 -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_10_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_10_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10 OSD_DRAW_H_REG_DRAW_X_MAX_10 -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_10_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_10_POS)) - -/* 0x10 : draw_partial_y_config10 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG10_OFFSET (0x10) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10 OSD_DRAW_H_REG_DRAW_Y_MIN_10 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_10_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_10_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10 OSD_DRAW_H_REG_DRAW_Y_MAX_10 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_10_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_10_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_10_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_10_POS)) - -/* 0x14 : draw_partial_yuv_config11 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG11_OFFSET (0x14) -#define OSD_DRAW_H_REG_DRAW_TH_11 OSD_DRAW_H_REG_DRAW_TH_11 -#define OSD_DRAW_H_REG_DRAW_TH_11_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_11_POS) -#define OSD_DRAW_H_REG_DRAW_TH_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_11_POS)) -#define OSD_DRAW_H_REG_DRAW_V_11 OSD_DRAW_H_REG_DRAW_V_11 -#define OSD_DRAW_H_REG_DRAW_V_11_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_11_POS) -#define OSD_DRAW_H_REG_DRAW_V_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_11_POS)) -#define OSD_DRAW_H_REG_DRAW_U_11 OSD_DRAW_H_REG_DRAW_U_11 -#define OSD_DRAW_H_REG_DRAW_U_11_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_11_POS) -#define OSD_DRAW_H_REG_DRAW_U_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_11_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_11 OSD_DRAW_H_REG_DRAW_Y_11 -#define OSD_DRAW_H_REG_DRAW_Y_11_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_11_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_11_POS) -#define OSD_DRAW_H_REG_DRAW_Y_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_11_POS)) - -/* 0x18 : draw_partial_x_config11 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG11_OFFSET (0x18) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11 OSD_DRAW_H_REG_DRAW_X_MIN_11 -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_11_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_11_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11 OSD_DRAW_H_REG_DRAW_X_MAX_11 -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_11_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_11_POS)) - -/* 0x1C : draw_partial_y_config11 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG11_OFFSET (0x1C) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11 OSD_DRAW_H_REG_DRAW_Y_MIN_11 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_11_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_11_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11 OSD_DRAW_H_REG_DRAW_Y_MAX_11 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_11_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_11_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_11_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_11_POS)) - -/* 0x20 : draw_partial_yuv_config12 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG12_OFFSET (0x20) -#define OSD_DRAW_H_REG_DRAW_TH_12 OSD_DRAW_H_REG_DRAW_TH_12 -#define OSD_DRAW_H_REG_DRAW_TH_12_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_12_POS) -#define OSD_DRAW_H_REG_DRAW_TH_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_12_POS)) -#define OSD_DRAW_H_REG_DRAW_V_12 OSD_DRAW_H_REG_DRAW_V_12 -#define OSD_DRAW_H_REG_DRAW_V_12_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_12_POS) -#define OSD_DRAW_H_REG_DRAW_V_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_12_POS)) -#define OSD_DRAW_H_REG_DRAW_U_12 OSD_DRAW_H_REG_DRAW_U_12 -#define OSD_DRAW_H_REG_DRAW_U_12_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_12_POS) -#define OSD_DRAW_H_REG_DRAW_U_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_12_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_12 OSD_DRAW_H_REG_DRAW_Y_12 -#define OSD_DRAW_H_REG_DRAW_Y_12_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_12_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_12_POS) -#define OSD_DRAW_H_REG_DRAW_Y_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_12_POS)) - -/* 0x24 : draw_partial_x_config12 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG12_OFFSET (0x24) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12 OSD_DRAW_H_REG_DRAW_X_MIN_12 -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_12_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_12_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12 OSD_DRAW_H_REG_DRAW_X_MAX_12 -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_12_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_12_POS)) - -/* 0x28 : draw_partial_y_config12 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG12_OFFSET (0x28) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12 OSD_DRAW_H_REG_DRAW_Y_MIN_12 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_12_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_12_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12 OSD_DRAW_H_REG_DRAW_Y_MAX_12 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_12_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_12_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_12_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_12_POS)) - -/* 0x2C : draw_partial_yuv_config13 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG13_OFFSET (0x2C) -#define OSD_DRAW_H_REG_DRAW_TH_13 OSD_DRAW_H_REG_DRAW_TH_13 -#define OSD_DRAW_H_REG_DRAW_TH_13_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_13_POS) -#define OSD_DRAW_H_REG_DRAW_TH_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_13_POS)) -#define OSD_DRAW_H_REG_DRAW_V_13 OSD_DRAW_H_REG_DRAW_V_13 -#define OSD_DRAW_H_REG_DRAW_V_13_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_13_POS) -#define OSD_DRAW_H_REG_DRAW_V_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_13_POS)) -#define OSD_DRAW_H_REG_DRAW_U_13 OSD_DRAW_H_REG_DRAW_U_13 -#define OSD_DRAW_H_REG_DRAW_U_13_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_13_POS) -#define OSD_DRAW_H_REG_DRAW_U_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_13_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_13 OSD_DRAW_H_REG_DRAW_Y_13 -#define OSD_DRAW_H_REG_DRAW_Y_13_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_13_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_13_POS) -#define OSD_DRAW_H_REG_DRAW_Y_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_13_POS)) - -/* 0x30 : draw_partial_x_config13 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG13_OFFSET (0x30) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13 OSD_DRAW_H_REG_DRAW_X_MIN_13 -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_13_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_13_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13 OSD_DRAW_H_REG_DRAW_X_MAX_13 -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_13_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_13_POS)) - -/* 0x34 : draw_partial_y_config13 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG13_OFFSET (0x34) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13 OSD_DRAW_H_REG_DRAW_Y_MIN_13 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_13_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_13_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13 OSD_DRAW_H_REG_DRAW_Y_MAX_13 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_13_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_13_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_13_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_13_POS)) - -/* 0x38 : draw_partial_yuv_config14 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG14_OFFSET (0x38) -#define OSD_DRAW_H_REG_DRAW_TH_14 OSD_DRAW_H_REG_DRAW_TH_14 -#define OSD_DRAW_H_REG_DRAW_TH_14_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_14_POS) -#define OSD_DRAW_H_REG_DRAW_TH_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_14_POS)) -#define OSD_DRAW_H_REG_DRAW_V_14 OSD_DRAW_H_REG_DRAW_V_14 -#define OSD_DRAW_H_REG_DRAW_V_14_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_14_POS) -#define OSD_DRAW_H_REG_DRAW_V_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_14_POS)) -#define OSD_DRAW_H_REG_DRAW_U_14 OSD_DRAW_H_REG_DRAW_U_14 -#define OSD_DRAW_H_REG_DRAW_U_14_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_14_POS) -#define OSD_DRAW_H_REG_DRAW_U_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_14_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_14 OSD_DRAW_H_REG_DRAW_Y_14 -#define OSD_DRAW_H_REG_DRAW_Y_14_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_14_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_14_POS) -#define OSD_DRAW_H_REG_DRAW_Y_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_14_POS)) - -/* 0x3C : draw_partial_x_config14 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG14_OFFSET (0x3C) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14 OSD_DRAW_H_REG_DRAW_X_MIN_14 -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_14_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_14_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14 OSD_DRAW_H_REG_DRAW_X_MAX_14 -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_14_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_14_POS)) - -/* 0x40 : draw_partial_y_config14 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG14_OFFSET (0x40) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14 OSD_DRAW_H_REG_DRAW_Y_MIN_14 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_14_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_14_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14 OSD_DRAW_H_REG_DRAW_Y_MAX_14 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_14_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_14_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_14_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_14_POS)) - -/* 0x44 : draw_partial_yuv_config15 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG15_OFFSET (0x44) -#define OSD_DRAW_H_REG_DRAW_TH_15 OSD_DRAW_H_REG_DRAW_TH_15 -#define OSD_DRAW_H_REG_DRAW_TH_15_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_15_POS) -#define OSD_DRAW_H_REG_DRAW_TH_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_15_POS)) -#define OSD_DRAW_H_REG_DRAW_V_15 OSD_DRAW_H_REG_DRAW_V_15 -#define OSD_DRAW_H_REG_DRAW_V_15_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_15_POS) -#define OSD_DRAW_H_REG_DRAW_V_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_15_POS)) -#define OSD_DRAW_H_REG_DRAW_U_15 OSD_DRAW_H_REG_DRAW_U_15 -#define OSD_DRAW_H_REG_DRAW_U_15_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_15_POS) -#define OSD_DRAW_H_REG_DRAW_U_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_15_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_15 OSD_DRAW_H_REG_DRAW_Y_15 -#define OSD_DRAW_H_REG_DRAW_Y_15_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_15_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_15_POS) -#define OSD_DRAW_H_REG_DRAW_Y_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_15_POS)) - -/* 0x48 : draw_partial_x_config15 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG15_OFFSET (0x48) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15 OSD_DRAW_H_REG_DRAW_X_MIN_15 -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_15_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_15_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15 OSD_DRAW_H_REG_DRAW_X_MAX_15 -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_15_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_15_POS)) - -/* 0x4C : draw_partial_y_config15 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG15_OFFSET (0x4C) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15 OSD_DRAW_H_REG_DRAW_Y_MIN_15 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_15_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_15_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15 OSD_DRAW_H_REG_DRAW_Y_MAX_15 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_15_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_15_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_15_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_15_POS)) - -/* 0x50 : draw_partial_yuv_config16 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG16_OFFSET (0x50) -#define OSD_DRAW_H_REG_DRAW_TH_16 OSD_DRAW_H_REG_DRAW_TH_16 -#define OSD_DRAW_H_REG_DRAW_TH_16_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_16_POS) -#define OSD_DRAW_H_REG_DRAW_TH_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_16_POS)) -#define OSD_DRAW_H_REG_DRAW_V_16 OSD_DRAW_H_REG_DRAW_V_16 -#define OSD_DRAW_H_REG_DRAW_V_16_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_16_POS) -#define OSD_DRAW_H_REG_DRAW_V_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_16_POS)) -#define OSD_DRAW_H_REG_DRAW_U_16 OSD_DRAW_H_REG_DRAW_U_16 -#define OSD_DRAW_H_REG_DRAW_U_16_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_16_POS) -#define OSD_DRAW_H_REG_DRAW_U_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_16_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_16 OSD_DRAW_H_REG_DRAW_Y_16 -#define OSD_DRAW_H_REG_DRAW_Y_16_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_16_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_16_POS) -#define OSD_DRAW_H_REG_DRAW_Y_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_16_POS)) - -/* 0x54 : draw_partial_x_config16 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG16_OFFSET (0x54) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16 OSD_DRAW_H_REG_DRAW_X_MIN_16 -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_16_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_16_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16 OSD_DRAW_H_REG_DRAW_X_MAX_16 -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_16_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_16_POS)) - -/* 0x58 : draw_partial_y_config16 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG16_OFFSET (0x58) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16 OSD_DRAW_H_REG_DRAW_Y_MIN_16 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_16_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_16_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16 OSD_DRAW_H_REG_DRAW_Y_MAX_16 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_16_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_16_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_16_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_16_POS)) - -/* 0x5C : draw_partial_yuv_config17 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG17_OFFSET (0x5C) -#define OSD_DRAW_H_REG_DRAW_TH_17 OSD_DRAW_H_REG_DRAW_TH_17 -#define OSD_DRAW_H_REG_DRAW_TH_17_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_17_POS) -#define OSD_DRAW_H_REG_DRAW_TH_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_17_POS)) -#define OSD_DRAW_H_REG_DRAW_V_17 OSD_DRAW_H_REG_DRAW_V_17 -#define OSD_DRAW_H_REG_DRAW_V_17_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_17_POS) -#define OSD_DRAW_H_REG_DRAW_V_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_17_POS)) -#define OSD_DRAW_H_REG_DRAW_U_17 OSD_DRAW_H_REG_DRAW_U_17 -#define OSD_DRAW_H_REG_DRAW_U_17_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_17_POS) -#define OSD_DRAW_H_REG_DRAW_U_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_17_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_17 OSD_DRAW_H_REG_DRAW_Y_17 -#define OSD_DRAW_H_REG_DRAW_Y_17_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_17_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_17_POS) -#define OSD_DRAW_H_REG_DRAW_Y_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_17_POS)) - -/* 0x60 : draw_partial_x_config17 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG17_OFFSET (0x60) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17 OSD_DRAW_H_REG_DRAW_X_MIN_17 -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_17_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_17_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17 OSD_DRAW_H_REG_DRAW_X_MAX_17 -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_17_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_17_POS)) - -/* 0x64 : draw_partial_y_config17 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG17_OFFSET (0x64) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17 OSD_DRAW_H_REG_DRAW_Y_MIN_17 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_17_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_17_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17 OSD_DRAW_H_REG_DRAW_Y_MAX_17 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_17_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_17_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_17_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_17_POS)) - -/* 0x68 : draw_partial_yuv_config18 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG18_OFFSET (0x68) -#define OSD_DRAW_H_REG_DRAW_TH_18 OSD_DRAW_H_REG_DRAW_TH_18 -#define OSD_DRAW_H_REG_DRAW_TH_18_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_18_POS) -#define OSD_DRAW_H_REG_DRAW_TH_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_18_POS)) -#define OSD_DRAW_H_REG_DRAW_V_18 OSD_DRAW_H_REG_DRAW_V_18 -#define OSD_DRAW_H_REG_DRAW_V_18_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_18_POS) -#define OSD_DRAW_H_REG_DRAW_V_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_18_POS)) -#define OSD_DRAW_H_REG_DRAW_U_18 OSD_DRAW_H_REG_DRAW_U_18 -#define OSD_DRAW_H_REG_DRAW_U_18_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_18_POS) -#define OSD_DRAW_H_REG_DRAW_U_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_18_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_18 OSD_DRAW_H_REG_DRAW_Y_18 -#define OSD_DRAW_H_REG_DRAW_Y_18_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_18_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_18_POS) -#define OSD_DRAW_H_REG_DRAW_Y_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_18_POS)) - -/* 0x6C : draw_partial_x_config18 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG18_OFFSET (0x6C) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18 OSD_DRAW_H_REG_DRAW_X_MIN_18 -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_18_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_18_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18 OSD_DRAW_H_REG_DRAW_X_MAX_18 -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_18_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_18_POS)) - -/* 0x70 : draw_partial_y_config18 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG18_OFFSET (0x70) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18 OSD_DRAW_H_REG_DRAW_Y_MIN_18 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_18_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_18_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18 OSD_DRAW_H_REG_DRAW_Y_MAX_18 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_18_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_18_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_18_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_18_POS)) - -/* 0x74 : draw_partial_yuv_config19 */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG19_OFFSET (0x74) -#define OSD_DRAW_H_REG_DRAW_TH_19 OSD_DRAW_H_REG_DRAW_TH_19 -#define OSD_DRAW_H_REG_DRAW_TH_19_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_19_POS) -#define OSD_DRAW_H_REG_DRAW_TH_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_19_POS)) -#define OSD_DRAW_H_REG_DRAW_V_19 OSD_DRAW_H_REG_DRAW_V_19 -#define OSD_DRAW_H_REG_DRAW_V_19_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_19_POS) -#define OSD_DRAW_H_REG_DRAW_V_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_19_POS)) -#define OSD_DRAW_H_REG_DRAW_U_19 OSD_DRAW_H_REG_DRAW_U_19 -#define OSD_DRAW_H_REG_DRAW_U_19_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_19_POS) -#define OSD_DRAW_H_REG_DRAW_U_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_19_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_19 OSD_DRAW_H_REG_DRAW_Y_19 -#define OSD_DRAW_H_REG_DRAW_Y_19_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_19_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_19_POS) -#define OSD_DRAW_H_REG_DRAW_Y_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_19_POS)) - -/* 0x78 : draw_partial_x_config19 */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG19_OFFSET (0x78) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19 OSD_DRAW_H_REG_DRAW_X_MIN_19 -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_19_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_19_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19 OSD_DRAW_H_REG_DRAW_X_MAX_19 -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_19_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_19_POS)) - -/* 0x7C : draw_partial_y_config19 */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG19_OFFSET (0x7C) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19 OSD_DRAW_H_REG_DRAW_Y_MIN_19 -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_19_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_19_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19 OSD_DRAW_H_REG_DRAW_Y_MAX_19 -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_19_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_19_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_19_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_19_POS)) - -/* 0x80 : draw_partial_yuv_config1a */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1A_OFFSET (0x80) -#define OSD_DRAW_H_REG_DRAW_TH_1A OSD_DRAW_H_REG_DRAW_TH_1A -#define OSD_DRAW_H_REG_DRAW_TH_1A_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1A_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1A OSD_DRAW_H_REG_DRAW_V_1A -#define OSD_DRAW_H_REG_DRAW_V_1A_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1A_POS) -#define OSD_DRAW_H_REG_DRAW_V_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1A OSD_DRAW_H_REG_DRAW_U_1A -#define OSD_DRAW_H_REG_DRAW_U_1A_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1A_POS) -#define OSD_DRAW_H_REG_DRAW_U_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1A OSD_DRAW_H_REG_DRAW_Y_1A -#define OSD_DRAW_H_REG_DRAW_Y_1A_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1A_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1A_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1A_POS)) - -/* 0x84 : draw_partial_x_config1a */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1A_OFFSET (0x84) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A OSD_DRAW_H_REG_DRAW_X_MIN_1A -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1A_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A OSD_DRAW_H_REG_DRAW_X_MAX_1A -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1A_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1A_POS)) - -/* 0x88 : draw_partial_y_config1a */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1A_OFFSET (0x88) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A OSD_DRAW_H_REG_DRAW_Y_MIN_1A -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1A_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A OSD_DRAW_H_REG_DRAW_Y_MAX_1A -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1A_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1A_POS)) - -/* 0x8C : draw_partial_yuv_config1b */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1B_OFFSET (0x8C) -#define OSD_DRAW_H_REG_DRAW_TH_1B OSD_DRAW_H_REG_DRAW_TH_1B -#define OSD_DRAW_H_REG_DRAW_TH_1B_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1B_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1B OSD_DRAW_H_REG_DRAW_V_1B -#define OSD_DRAW_H_REG_DRAW_V_1B_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1B_POS) -#define OSD_DRAW_H_REG_DRAW_V_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1B OSD_DRAW_H_REG_DRAW_U_1B -#define OSD_DRAW_H_REG_DRAW_U_1B_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1B_POS) -#define OSD_DRAW_H_REG_DRAW_U_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1B OSD_DRAW_H_REG_DRAW_Y_1B -#define OSD_DRAW_H_REG_DRAW_Y_1B_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1B_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1B_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1B_POS)) - -/* 0x90 : draw_partial_x_config1b */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1B_OFFSET (0x90) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B OSD_DRAW_H_REG_DRAW_X_MIN_1B -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1B_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B OSD_DRAW_H_REG_DRAW_X_MAX_1B -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1B_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1B_POS)) - -/* 0x94 : draw_partial_y_config1b */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1B_OFFSET (0x94) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B OSD_DRAW_H_REG_DRAW_Y_MIN_1B -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1B_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B OSD_DRAW_H_REG_DRAW_Y_MAX_1B -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1B_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1B_POS)) - -/* 0x98 : draw_partial_yuv_config1c */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1C_OFFSET (0x98) -#define OSD_DRAW_H_REG_DRAW_TH_1C OSD_DRAW_H_REG_DRAW_TH_1C -#define OSD_DRAW_H_REG_DRAW_TH_1C_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1C_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1C OSD_DRAW_H_REG_DRAW_V_1C -#define OSD_DRAW_H_REG_DRAW_V_1C_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1C_POS) -#define OSD_DRAW_H_REG_DRAW_V_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1C OSD_DRAW_H_REG_DRAW_U_1C -#define OSD_DRAW_H_REG_DRAW_U_1C_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1C_POS) -#define OSD_DRAW_H_REG_DRAW_U_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1C OSD_DRAW_H_REG_DRAW_Y_1C -#define OSD_DRAW_H_REG_DRAW_Y_1C_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1C_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1C_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1C_POS)) - -/* 0x9C : draw_partial_x_config1c */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1C_OFFSET (0x9C) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C OSD_DRAW_H_REG_DRAW_X_MIN_1C -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1C_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C OSD_DRAW_H_REG_DRAW_X_MAX_1C -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1C_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1C_POS)) - -/* 0xA0 : draw_partial_y_config1c */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1C_OFFSET (0xA0) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C OSD_DRAW_H_REG_DRAW_Y_MIN_1C -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1C_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C OSD_DRAW_H_REG_DRAW_Y_MAX_1C -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1C_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1C_POS)) - -/* 0xA4 : draw_partial_yuv_config1d */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1D_OFFSET (0xA4) -#define OSD_DRAW_H_REG_DRAW_TH_1D OSD_DRAW_H_REG_DRAW_TH_1D -#define OSD_DRAW_H_REG_DRAW_TH_1D_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1D_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1D OSD_DRAW_H_REG_DRAW_V_1D -#define OSD_DRAW_H_REG_DRAW_V_1D_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1D_POS) -#define OSD_DRAW_H_REG_DRAW_V_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1D OSD_DRAW_H_REG_DRAW_U_1D -#define OSD_DRAW_H_REG_DRAW_U_1D_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1D_POS) -#define OSD_DRAW_H_REG_DRAW_U_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1D OSD_DRAW_H_REG_DRAW_Y_1D -#define OSD_DRAW_H_REG_DRAW_Y_1D_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1D_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1D_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1D_POS)) - -/* 0xA8 : draw_partial_x_config1d */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1D_OFFSET (0xA8) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D OSD_DRAW_H_REG_DRAW_X_MIN_1D -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1D_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D OSD_DRAW_H_REG_DRAW_X_MAX_1D -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1D_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1D_POS)) - -/* 0xAC : draw_partial_y_config1d */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1D_OFFSET (0xAC) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D OSD_DRAW_H_REG_DRAW_Y_MIN_1D -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1D_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D OSD_DRAW_H_REG_DRAW_Y_MAX_1D -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1D_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1D_POS)) - -/* 0xB0 : draw_partial_yuv_config1e */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1E_OFFSET (0xB0) -#define OSD_DRAW_H_REG_DRAW_TH_1E OSD_DRAW_H_REG_DRAW_TH_1E -#define OSD_DRAW_H_REG_DRAW_TH_1E_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1E_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1E OSD_DRAW_H_REG_DRAW_V_1E -#define OSD_DRAW_H_REG_DRAW_V_1E_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1E_POS) -#define OSD_DRAW_H_REG_DRAW_V_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1E OSD_DRAW_H_REG_DRAW_U_1E -#define OSD_DRAW_H_REG_DRAW_U_1E_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1E_POS) -#define OSD_DRAW_H_REG_DRAW_U_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1E OSD_DRAW_H_REG_DRAW_Y_1E -#define OSD_DRAW_H_REG_DRAW_Y_1E_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1E_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1E_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1E_POS)) - -/* 0xB4 : draw_partial_x_config1e */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1E_OFFSET (0xB4) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E OSD_DRAW_H_REG_DRAW_X_MIN_1E -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1E_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E OSD_DRAW_H_REG_DRAW_X_MAX_1E -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1E_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1E_POS)) - -/* 0xB8 : draw_partial_y_config1e */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1E_OFFSET (0xB8) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E OSD_DRAW_H_REG_DRAW_Y_MIN_1E -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1E_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E OSD_DRAW_H_REG_DRAW_Y_MAX_1E -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1E_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1E_POS)) - -/* 0xBC : draw_partial_yuv_config1f */ -#define OSD_DRAW_H_DRAW_PARTIAL_YUV_CONFIG1F_OFFSET (0xBC) -#define OSD_DRAW_H_REG_DRAW_TH_1F OSD_DRAW_H_REG_DRAW_TH_1F -#define OSD_DRAW_H_REG_DRAW_TH_1F_POS (0U) -#define OSD_DRAW_H_REG_DRAW_TH_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_TH_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_TH_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1F_POS) -#define OSD_DRAW_H_REG_DRAW_TH_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_TH_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_TH_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_V_1F OSD_DRAW_H_REG_DRAW_V_1F -#define OSD_DRAW_H_REG_DRAW_V_1F_POS (8U) -#define OSD_DRAW_H_REG_DRAW_V_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_V_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_V_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1F_POS) -#define OSD_DRAW_H_REG_DRAW_V_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_V_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_V_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_U_1F OSD_DRAW_H_REG_DRAW_U_1F -#define OSD_DRAW_H_REG_DRAW_U_1F_POS (16U) -#define OSD_DRAW_H_REG_DRAW_U_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_U_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_U_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1F_POS) -#define OSD_DRAW_H_REG_DRAW_U_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_U_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_U_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_1F OSD_DRAW_H_REG_DRAW_Y_1F -#define OSD_DRAW_H_REG_DRAW_Y_1F_POS (24U) -#define OSD_DRAW_H_REG_DRAW_Y_1F_LEN (8U) -#define OSD_DRAW_H_REG_DRAW_Y_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1F_POS) -#define OSD_DRAW_H_REG_DRAW_Y_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_1F_POS)) - -/* 0xC0 : draw_partial_x_config1f */ -#define OSD_DRAW_H_DRAW_PARTIAL_X_CONFIG1F_OFFSET (0xC0) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F OSD_DRAW_H_REG_DRAW_X_MIN_1F -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_POS (0U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1F_POS) -#define OSD_DRAW_H_REG_DRAW_X_MIN_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MIN_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F OSD_DRAW_H_REG_DRAW_X_MAX_1F -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_POS (16U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1F_POS) -#define OSD_DRAW_H_REG_DRAW_X_MAX_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_X_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_X_MAX_1F_POS)) - -/* 0xC4 : draw_partial_y_config1f */ -#define OSD_DRAW_H_DRAW_PARTIAL_Y_CONFIG1F_OFFSET (0xC4) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F OSD_DRAW_H_REG_DRAW_Y_MIN_1F -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_POS (0U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MIN_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MIN_1F_POS)) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F OSD_DRAW_H_REG_DRAW_Y_MAX_1F -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_POS (16U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_LEN (11U) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_MSK (((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_POS) -#define OSD_DRAW_H_REG_DRAW_Y_MAX_1F_UMSK (~(((1U << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_LEN) - 1) << OSD_DRAW_H_REG_DRAW_Y_MAX_1F_POS)) - -struct osd_draw_h_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[4]; - - /* 0x4 : draw_partial_config */ - union { - struct { - uint32_t reg_draw_en_h : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_draw_type_h : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_config; - - /* 0x8 : draw_partial_yuv_config10 */ - union { - struct { - uint32_t reg_draw_th_10 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_10 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_10 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_10 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config10; - - /* 0xC : draw_partial_x_config10 */ - union { - struct { - uint32_t reg_draw_x_min_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config10; - - /* 0x10 : draw_partial_y_config10 */ - union { - struct { - uint32_t reg_draw_y_min_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config10; - - /* 0x14 : draw_partial_yuv_config11 */ - union { - struct { - uint32_t reg_draw_th_11 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_11 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_11 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_11 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config11; - - /* 0x18 : draw_partial_x_config11 */ - union { - struct { - uint32_t reg_draw_x_min_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config11; - - /* 0x1C : draw_partial_y_config11 */ - union { - struct { - uint32_t reg_draw_y_min_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config11; - - /* 0x20 : draw_partial_yuv_config12 */ - union { - struct { - uint32_t reg_draw_th_12 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_12 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_12 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_12 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config12; - - /* 0x24 : draw_partial_x_config12 */ - union { - struct { - uint32_t reg_draw_x_min_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config12; - - /* 0x28 : draw_partial_y_config12 */ - union { - struct { - uint32_t reg_draw_y_min_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config12; - - /* 0x2C : draw_partial_yuv_config13 */ - union { - struct { - uint32_t reg_draw_th_13 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_13 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_13 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_13 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config13; - - /* 0x30 : draw_partial_x_config13 */ - union { - struct { - uint32_t reg_draw_x_min_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config13; - - /* 0x34 : draw_partial_y_config13 */ - union { - struct { - uint32_t reg_draw_y_min_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config13; - - /* 0x38 : draw_partial_yuv_config14 */ - union { - struct { - uint32_t reg_draw_th_14 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_14 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_14 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_14 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config14; - - /* 0x3C : draw_partial_x_config14 */ - union { - struct { - uint32_t reg_draw_x_min_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config14; - - /* 0x40 : draw_partial_y_config14 */ - union { - struct { - uint32_t reg_draw_y_min_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config14; - - /* 0x44 : draw_partial_yuv_config15 */ - union { - struct { - uint32_t reg_draw_th_15 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_15 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_15 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_15 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config15; - - /* 0x48 : draw_partial_x_config15 */ - union { - struct { - uint32_t reg_draw_x_min_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config15; - - /* 0x4C : draw_partial_y_config15 */ - union { - struct { - uint32_t reg_draw_y_min_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config15; - - /* 0x50 : draw_partial_yuv_config16 */ - union { - struct { - uint32_t reg_draw_th_16 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_16 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_16 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_16 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config16; - - /* 0x54 : draw_partial_x_config16 */ - union { - struct { - uint32_t reg_draw_x_min_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config16; - - /* 0x58 : draw_partial_y_config16 */ - union { - struct { - uint32_t reg_draw_y_min_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config16; - - /* 0x5C : draw_partial_yuv_config17 */ - union { - struct { - uint32_t reg_draw_th_17 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_17 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_17 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_17 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config17; - - /* 0x60 : draw_partial_x_config17 */ - union { - struct { - uint32_t reg_draw_x_min_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config17; - - /* 0x64 : draw_partial_y_config17 */ - union { - struct { - uint32_t reg_draw_y_min_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config17; - - /* 0x68 : draw_partial_yuv_config18 */ - union { - struct { - uint32_t reg_draw_th_18 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_18 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_18 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_18 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config18; - - /* 0x6C : draw_partial_x_config18 */ - union { - struct { - uint32_t reg_draw_x_min_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config18; - - /* 0x70 : draw_partial_y_config18 */ - union { - struct { - uint32_t reg_draw_y_min_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config18; - - /* 0x74 : draw_partial_yuv_config19 */ - union { - struct { - uint32_t reg_draw_th_19 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_19 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_19 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_19 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config19; - - /* 0x78 : draw_partial_x_config19 */ - union { - struct { - uint32_t reg_draw_x_min_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config19; - - /* 0x7C : draw_partial_y_config19 */ - union { - struct { - uint32_t reg_draw_y_min_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config19; - - /* 0x80 : draw_partial_yuv_config1a */ - union { - struct { - uint32_t reg_draw_th_1a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1a : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1a : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1a; - - /* 0x84 : draw_partial_x_config1a */ - union { - struct { - uint32_t reg_draw_x_min_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1a; - - /* 0x88 : draw_partial_y_config1a */ - union { - struct { - uint32_t reg_draw_y_min_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1a; - - /* 0x8C : draw_partial_yuv_config1b */ - union { - struct { - uint32_t reg_draw_th_1b : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1b : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1b : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1b : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1b; - - /* 0x90 : draw_partial_x_config1b */ - union { - struct { - uint32_t reg_draw_x_min_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1b; - - /* 0x94 : draw_partial_y_config1b */ - union { - struct { - uint32_t reg_draw_y_min_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1b; - - /* 0x98 : draw_partial_yuv_config1c */ - union { - struct { - uint32_t reg_draw_th_1c : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1c : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1c : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1c : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1c; - - /* 0x9C : draw_partial_x_config1c */ - union { - struct { - uint32_t reg_draw_x_min_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1c; - - /* 0xA0 : draw_partial_y_config1c */ - union { - struct { - uint32_t reg_draw_y_min_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1c; - - /* 0xA4 : draw_partial_yuv_config1d */ - union { - struct { - uint32_t reg_draw_th_1d : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1d : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1d : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1d : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1d; - - /* 0xA8 : draw_partial_x_config1d */ - union { - struct { - uint32_t reg_draw_x_min_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1d; - - /* 0xAC : draw_partial_y_config1d */ - union { - struct { - uint32_t reg_draw_y_min_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1d; - - /* 0xB0 : draw_partial_yuv_config1e */ - union { - struct { - uint32_t reg_draw_th_1e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1e : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1e : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1e : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1e; - - /* 0xB4 : draw_partial_x_config1e */ - union { - struct { - uint32_t reg_draw_x_min_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1e; - - /* 0xB8 : draw_partial_y_config1e */ - union { - struct { - uint32_t reg_draw_y_min_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1e; - - /* 0xBC : draw_partial_yuv_config1f */ - union { - struct { - uint32_t reg_draw_th_1f : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_1f : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_1f : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_1f : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1f; - - /* 0xC0 : draw_partial_x_config1f */ - union { - struct { - uint32_t reg_draw_x_min_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1f; - - /* 0xC4 : draw_partial_y_config1f */ - union { - struct { - uint32_t reg_draw_y_min_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1f; -}; - -typedef volatile struct osd_draw_h_reg osd_draw_h_reg_t; - -#endif /* __OSD_DRAW_H_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_l_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_l_reg.h deleted file mode 100644 index 8e8e1dd23f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_l_reg.h +++ /dev/null @@ -1,1511 +0,0 @@ -/** - ****************************************************************************** - * @file osd_draw_l_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_DRAW_L_REG_H__ -#define __OSD_DRAW_L_REG_H__ - -#include "bl808.h" - -/* 0x0 : osd_draw_config */ -#define OSD_DRAW_L_OSD_DRAW_CONFIG_OFFSET (0x0) -#define OSD_DRAW_L_REG_DRAW_EN_L OSD_DRAW_L_REG_DRAW_EN_L -#define OSD_DRAW_L_REG_DRAW_EN_L_POS (0U) -#define OSD_DRAW_L_REG_DRAW_EN_L_LEN (16U) -#define OSD_DRAW_L_REG_DRAW_EN_L_MSK (((1U << OSD_DRAW_L_REG_DRAW_EN_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_EN_L_POS) -#define OSD_DRAW_L_REG_DRAW_EN_L_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_EN_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_EN_L_POS)) -#define OSD_DRAW_L_REG_DRAW_TYPE_L OSD_DRAW_L_REG_DRAW_TYPE_L -#define OSD_DRAW_L_REG_DRAW_TYPE_L_POS (16U) -#define OSD_DRAW_L_REG_DRAW_TYPE_L_LEN (16U) -#define OSD_DRAW_L_REG_DRAW_TYPE_L_MSK (((1U << OSD_DRAW_L_REG_DRAW_TYPE_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TYPE_L_POS) -#define OSD_DRAW_L_REG_DRAW_TYPE_L_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TYPE_L_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TYPE_L_POS)) - -/* 0x4 : draw_partial_yuv_config0 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG0_OFFSET (0x4) -#define OSD_DRAW_L_REG_DRAW_TH_00 OSD_DRAW_L_REG_DRAW_TH_00 -#define OSD_DRAW_L_REG_DRAW_TH_00_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_00_POS) -#define OSD_DRAW_L_REG_DRAW_TH_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_00_POS)) -#define OSD_DRAW_L_REG_DRAW_V_00 OSD_DRAW_L_REG_DRAW_V_00 -#define OSD_DRAW_L_REG_DRAW_V_00_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_00_POS) -#define OSD_DRAW_L_REG_DRAW_V_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_00_POS)) -#define OSD_DRAW_L_REG_DRAW_U_00 OSD_DRAW_L_REG_DRAW_U_00 -#define OSD_DRAW_L_REG_DRAW_U_00_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_00_POS) -#define OSD_DRAW_L_REG_DRAW_U_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_00_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_00 OSD_DRAW_L_REG_DRAW_Y_00 -#define OSD_DRAW_L_REG_DRAW_Y_00_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_00_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_00_POS) -#define OSD_DRAW_L_REG_DRAW_Y_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_00_POS)) - -/* 0x8 : draw_partial_x_config0 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG0_OFFSET (0x8) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00 OSD_DRAW_L_REG_DRAW_X_MIN_00 -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_00_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_00_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00 OSD_DRAW_L_REG_DRAW_X_MAX_00 -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_00_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_00_POS)) - -/* 0xC : draw_partial_y_config0 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG0_OFFSET (0xC) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00 OSD_DRAW_L_REG_DRAW_Y_MIN_00 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_00_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_00_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00 OSD_DRAW_L_REG_DRAW_Y_MAX_00 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_00_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_00_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_00_POS)) - -/* 0x10 : draw_partial_yuv_config1 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG1_OFFSET (0x10) -#define OSD_DRAW_L_REG_DRAW_TH_01 OSD_DRAW_L_REG_DRAW_TH_01 -#define OSD_DRAW_L_REG_DRAW_TH_01_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_01_POS) -#define OSD_DRAW_L_REG_DRAW_TH_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_01_POS)) -#define OSD_DRAW_L_REG_DRAW_V_01 OSD_DRAW_L_REG_DRAW_V_01 -#define OSD_DRAW_L_REG_DRAW_V_01_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_01_POS) -#define OSD_DRAW_L_REG_DRAW_V_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_01_POS)) -#define OSD_DRAW_L_REG_DRAW_U_01 OSD_DRAW_L_REG_DRAW_U_01 -#define OSD_DRAW_L_REG_DRAW_U_01_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_01_POS) -#define OSD_DRAW_L_REG_DRAW_U_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_01_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_01 OSD_DRAW_L_REG_DRAW_Y_01 -#define OSD_DRAW_L_REG_DRAW_Y_01_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_01_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_01_POS) -#define OSD_DRAW_L_REG_DRAW_Y_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_01_POS)) - -/* 0x14 : draw_partial_x_config1 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG1_OFFSET (0x14) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01 OSD_DRAW_L_REG_DRAW_X_MIN_01 -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_01_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_01_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01 OSD_DRAW_L_REG_DRAW_X_MAX_01 -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_01_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_01_POS)) - -/* 0x18 : draw_partial_y_config1 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG1_OFFSET (0x18) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01 OSD_DRAW_L_REG_DRAW_Y_MIN_01 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_01_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_01_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01 OSD_DRAW_L_REG_DRAW_Y_MAX_01 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_01_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_01_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_01_POS)) - -/* 0x1C : draw_partial_yuv_config2 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG2_OFFSET (0x1C) -#define OSD_DRAW_L_REG_DRAW_TH_02 OSD_DRAW_L_REG_DRAW_TH_02 -#define OSD_DRAW_L_REG_DRAW_TH_02_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_02_POS) -#define OSD_DRAW_L_REG_DRAW_TH_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_02_POS)) -#define OSD_DRAW_L_REG_DRAW_V_02 OSD_DRAW_L_REG_DRAW_V_02 -#define OSD_DRAW_L_REG_DRAW_V_02_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_02_POS) -#define OSD_DRAW_L_REG_DRAW_V_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_02_POS)) -#define OSD_DRAW_L_REG_DRAW_U_02 OSD_DRAW_L_REG_DRAW_U_02 -#define OSD_DRAW_L_REG_DRAW_U_02_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_02_POS) -#define OSD_DRAW_L_REG_DRAW_U_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_02_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_02 OSD_DRAW_L_REG_DRAW_Y_02 -#define OSD_DRAW_L_REG_DRAW_Y_02_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_02_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_02_POS) -#define OSD_DRAW_L_REG_DRAW_Y_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_02_POS)) - -/* 0x20 : draw_partial_x_config2 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG2_OFFSET (0x20) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02 OSD_DRAW_L_REG_DRAW_X_MIN_02 -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_02_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_02_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02 OSD_DRAW_L_REG_DRAW_X_MAX_02 -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_02_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_02_POS)) - -/* 0x24 : draw_partial_y_config2 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG2_OFFSET (0x24) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02 OSD_DRAW_L_REG_DRAW_Y_MIN_02 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_02_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_02_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02 OSD_DRAW_L_REG_DRAW_Y_MAX_02 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_02_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_02_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_02_POS)) - -/* 0x28 : draw_partial_yuv_config3 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG3_OFFSET (0x28) -#define OSD_DRAW_L_REG_DRAW_TH_03 OSD_DRAW_L_REG_DRAW_TH_03 -#define OSD_DRAW_L_REG_DRAW_TH_03_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_03_POS) -#define OSD_DRAW_L_REG_DRAW_TH_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_03_POS)) -#define OSD_DRAW_L_REG_DRAW_V_03 OSD_DRAW_L_REG_DRAW_V_03 -#define OSD_DRAW_L_REG_DRAW_V_03_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_03_POS) -#define OSD_DRAW_L_REG_DRAW_V_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_03_POS)) -#define OSD_DRAW_L_REG_DRAW_U_03 OSD_DRAW_L_REG_DRAW_U_03 -#define OSD_DRAW_L_REG_DRAW_U_03_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_03_POS) -#define OSD_DRAW_L_REG_DRAW_U_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_03_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_03 OSD_DRAW_L_REG_DRAW_Y_03 -#define OSD_DRAW_L_REG_DRAW_Y_03_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_03_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_03_POS) -#define OSD_DRAW_L_REG_DRAW_Y_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_03_POS)) - -/* 0x2C : draw_partial_x_config3 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG3_OFFSET (0x2C) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03 OSD_DRAW_L_REG_DRAW_X_MIN_03 -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_03_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_03_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03 OSD_DRAW_L_REG_DRAW_X_MAX_03 -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_03_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_03_POS)) - -/* 0x30 : draw_partial_y_config3 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG3_OFFSET (0x30) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03 OSD_DRAW_L_REG_DRAW_Y_MIN_03 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_03_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_03_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03 OSD_DRAW_L_REG_DRAW_Y_MAX_03 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_03_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_03_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_03_POS)) - -/* 0x34 : draw_partial_yuv_config4 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG4_OFFSET (0x34) -#define OSD_DRAW_L_REG_DRAW_TH_04 OSD_DRAW_L_REG_DRAW_TH_04 -#define OSD_DRAW_L_REG_DRAW_TH_04_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_04_POS) -#define OSD_DRAW_L_REG_DRAW_TH_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_04_POS)) -#define OSD_DRAW_L_REG_DRAW_V_04 OSD_DRAW_L_REG_DRAW_V_04 -#define OSD_DRAW_L_REG_DRAW_V_04_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_04_POS) -#define OSD_DRAW_L_REG_DRAW_V_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_04_POS)) -#define OSD_DRAW_L_REG_DRAW_U_04 OSD_DRAW_L_REG_DRAW_U_04 -#define OSD_DRAW_L_REG_DRAW_U_04_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_04_POS) -#define OSD_DRAW_L_REG_DRAW_U_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_04_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_04 OSD_DRAW_L_REG_DRAW_Y_04 -#define OSD_DRAW_L_REG_DRAW_Y_04_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_04_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_04_POS) -#define OSD_DRAW_L_REG_DRAW_Y_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_04_POS)) - -/* 0x38 : draw_partial_x_config4 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG4_OFFSET (0x38) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04 OSD_DRAW_L_REG_DRAW_X_MIN_04 -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_04_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_04_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04 OSD_DRAW_L_REG_DRAW_X_MAX_04 -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_04_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_04_POS)) - -/* 0x3C : draw_partial_y_config4 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG4_OFFSET (0x3C) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04 OSD_DRAW_L_REG_DRAW_Y_MIN_04 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_04_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_04_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04 OSD_DRAW_L_REG_DRAW_Y_MAX_04 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_04_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_04_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_04_POS)) - -/* 0x40 : draw_partial_yuv_config5 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG5_OFFSET (0x40) -#define OSD_DRAW_L_REG_DRAW_TH_05 OSD_DRAW_L_REG_DRAW_TH_05 -#define OSD_DRAW_L_REG_DRAW_TH_05_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_05_POS) -#define OSD_DRAW_L_REG_DRAW_TH_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_05_POS)) -#define OSD_DRAW_L_REG_DRAW_V_05 OSD_DRAW_L_REG_DRAW_V_05 -#define OSD_DRAW_L_REG_DRAW_V_05_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_05_POS) -#define OSD_DRAW_L_REG_DRAW_V_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_05_POS)) -#define OSD_DRAW_L_REG_DRAW_U_05 OSD_DRAW_L_REG_DRAW_U_05 -#define OSD_DRAW_L_REG_DRAW_U_05_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_05_POS) -#define OSD_DRAW_L_REG_DRAW_U_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_05_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_05 OSD_DRAW_L_REG_DRAW_Y_05 -#define OSD_DRAW_L_REG_DRAW_Y_05_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_05_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_05_POS) -#define OSD_DRAW_L_REG_DRAW_Y_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_05_POS)) - -/* 0x44 : draw_partial_x_config5 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG5_OFFSET (0x44) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05 OSD_DRAW_L_REG_DRAW_X_MIN_05 -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_05_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_05_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05 OSD_DRAW_L_REG_DRAW_X_MAX_05 -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_05_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_05_POS)) - -/* 0x48 : draw_partial_y_config5 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG5_OFFSET (0x48) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05 OSD_DRAW_L_REG_DRAW_Y_MIN_05 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_05_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_05_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05 OSD_DRAW_L_REG_DRAW_Y_MAX_05 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_05_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_05_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_05_POS)) - -/* 0x4C : draw_partial_yuv_config6 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG6_OFFSET (0x4C) -#define OSD_DRAW_L_REG_DRAW_TH_06 OSD_DRAW_L_REG_DRAW_TH_06 -#define OSD_DRAW_L_REG_DRAW_TH_06_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_06_POS) -#define OSD_DRAW_L_REG_DRAW_TH_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_06_POS)) -#define OSD_DRAW_L_REG_DRAW_V_06 OSD_DRAW_L_REG_DRAW_V_06 -#define OSD_DRAW_L_REG_DRAW_V_06_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_06_POS) -#define OSD_DRAW_L_REG_DRAW_V_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_06_POS)) -#define OSD_DRAW_L_REG_DRAW_U_06 OSD_DRAW_L_REG_DRAW_U_06 -#define OSD_DRAW_L_REG_DRAW_U_06_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_06_POS) -#define OSD_DRAW_L_REG_DRAW_U_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_06_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_06 OSD_DRAW_L_REG_DRAW_Y_06 -#define OSD_DRAW_L_REG_DRAW_Y_06_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_06_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_06_POS) -#define OSD_DRAW_L_REG_DRAW_Y_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_06_POS)) - -/* 0x50 : draw_partial_x_config6 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG6_OFFSET (0x50) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06 OSD_DRAW_L_REG_DRAW_X_MIN_06 -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_06_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_06_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06 OSD_DRAW_L_REG_DRAW_X_MAX_06 -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_06_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_06_POS)) - -/* 0x54 : draw_partial_y_config6 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG6_OFFSET (0x54) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06 OSD_DRAW_L_REG_DRAW_Y_MIN_06 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_06_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_06_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06 OSD_DRAW_L_REG_DRAW_Y_MAX_06 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_06_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_06_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_06_POS)) - -/* 0x58 : draw_partial_yuv_config7 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG7_OFFSET (0x58) -#define OSD_DRAW_L_REG_DRAW_TH_07 OSD_DRAW_L_REG_DRAW_TH_07 -#define OSD_DRAW_L_REG_DRAW_TH_07_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_07_POS) -#define OSD_DRAW_L_REG_DRAW_TH_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_07_POS)) -#define OSD_DRAW_L_REG_DRAW_V_07 OSD_DRAW_L_REG_DRAW_V_07 -#define OSD_DRAW_L_REG_DRAW_V_07_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_07_POS) -#define OSD_DRAW_L_REG_DRAW_V_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_07_POS)) -#define OSD_DRAW_L_REG_DRAW_U_07 OSD_DRAW_L_REG_DRAW_U_07 -#define OSD_DRAW_L_REG_DRAW_U_07_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_07_POS) -#define OSD_DRAW_L_REG_DRAW_U_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_07_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_07 OSD_DRAW_L_REG_DRAW_Y_07 -#define OSD_DRAW_L_REG_DRAW_Y_07_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_07_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_07_POS) -#define OSD_DRAW_L_REG_DRAW_Y_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_07_POS)) - -/* 0x5C : draw_partial_x_config7 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG7_OFFSET (0x5C) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07 OSD_DRAW_L_REG_DRAW_X_MIN_07 -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_07_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_07_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07 OSD_DRAW_L_REG_DRAW_X_MAX_07 -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_07_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_07_POS)) - -/* 0x60 : draw_partial_y_config7 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG7_OFFSET (0x60) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07 OSD_DRAW_L_REG_DRAW_Y_MIN_07 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_07_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_07_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07 OSD_DRAW_L_REG_DRAW_Y_MAX_07 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_07_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_07_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_07_POS)) - -/* 0x64 : draw_partial_yuv_config8 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG8_OFFSET (0x64) -#define OSD_DRAW_L_REG_DRAW_TH_08 OSD_DRAW_L_REG_DRAW_TH_08 -#define OSD_DRAW_L_REG_DRAW_TH_08_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_08_POS) -#define OSD_DRAW_L_REG_DRAW_TH_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_08_POS)) -#define OSD_DRAW_L_REG_DRAW_V_08 OSD_DRAW_L_REG_DRAW_V_08 -#define OSD_DRAW_L_REG_DRAW_V_08_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_08_POS) -#define OSD_DRAW_L_REG_DRAW_V_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_08_POS)) -#define OSD_DRAW_L_REG_DRAW_U_08 OSD_DRAW_L_REG_DRAW_U_08 -#define OSD_DRAW_L_REG_DRAW_U_08_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_08_POS) -#define OSD_DRAW_L_REG_DRAW_U_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_08_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_08 OSD_DRAW_L_REG_DRAW_Y_08 -#define OSD_DRAW_L_REG_DRAW_Y_08_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_08_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_08_POS) -#define OSD_DRAW_L_REG_DRAW_Y_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_08_POS)) - -/* 0x68 : draw_partial_x_config8 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG8_OFFSET (0x68) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08 OSD_DRAW_L_REG_DRAW_X_MIN_08 -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_08_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_08_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08 OSD_DRAW_L_REG_DRAW_X_MAX_08 -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_08_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_08_POS)) - -/* 0x6C : draw_partial_y_config8 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG8_OFFSET (0x6C) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08 OSD_DRAW_L_REG_DRAW_Y_MIN_08 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_08_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_08_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08 OSD_DRAW_L_REG_DRAW_Y_MAX_08 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_08_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_08_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_08_POS)) - -/* 0x70 : draw_partial_yuv_config9 */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIG9_OFFSET (0x70) -#define OSD_DRAW_L_REG_DRAW_TH_09 OSD_DRAW_L_REG_DRAW_TH_09 -#define OSD_DRAW_L_REG_DRAW_TH_09_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_09_POS) -#define OSD_DRAW_L_REG_DRAW_TH_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_09_POS)) -#define OSD_DRAW_L_REG_DRAW_V_09 OSD_DRAW_L_REG_DRAW_V_09 -#define OSD_DRAW_L_REG_DRAW_V_09_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_09_POS) -#define OSD_DRAW_L_REG_DRAW_V_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_09_POS)) -#define OSD_DRAW_L_REG_DRAW_U_09 OSD_DRAW_L_REG_DRAW_U_09 -#define OSD_DRAW_L_REG_DRAW_U_09_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_09_POS) -#define OSD_DRAW_L_REG_DRAW_U_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_09_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_09 OSD_DRAW_L_REG_DRAW_Y_09 -#define OSD_DRAW_L_REG_DRAW_Y_09_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_09_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_09_POS) -#define OSD_DRAW_L_REG_DRAW_Y_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_09_POS)) - -/* 0x74 : draw_partial_x_config9 */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIG9_OFFSET (0x74) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09 OSD_DRAW_L_REG_DRAW_X_MIN_09 -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_09_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_09_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09 OSD_DRAW_L_REG_DRAW_X_MAX_09 -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_09_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_09_POS)) - -/* 0x78 : draw_partial_y_config9 */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIG9_OFFSET (0x78) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09 OSD_DRAW_L_REG_DRAW_Y_MIN_09 -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_09_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_09_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09 OSD_DRAW_L_REG_DRAW_Y_MAX_09 -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_09_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_09_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_09_POS)) - -/* 0x7C : draw_partial_yuv_configa */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGA_OFFSET (0x7C) -#define OSD_DRAW_L_REG_DRAW_TH_0A OSD_DRAW_L_REG_DRAW_TH_0A -#define OSD_DRAW_L_REG_DRAW_TH_0A_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0A_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0A OSD_DRAW_L_REG_DRAW_V_0A -#define OSD_DRAW_L_REG_DRAW_V_0A_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0A_POS) -#define OSD_DRAW_L_REG_DRAW_V_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0A OSD_DRAW_L_REG_DRAW_U_0A -#define OSD_DRAW_L_REG_DRAW_U_0A_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0A_POS) -#define OSD_DRAW_L_REG_DRAW_U_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0A OSD_DRAW_L_REG_DRAW_Y_0A -#define OSD_DRAW_L_REG_DRAW_Y_0A_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0A_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0A_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0A_POS)) - -/* 0x80 : draw_partial_x_configa */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGA_OFFSET (0x80) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A OSD_DRAW_L_REG_DRAW_X_MIN_0A -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0A_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A OSD_DRAW_L_REG_DRAW_X_MAX_0A -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0A_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0A_POS)) - -/* 0x84 : draw_partial_y_configa */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGA_OFFSET (0x84) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A OSD_DRAW_L_REG_DRAW_Y_MIN_0A -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0A_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A OSD_DRAW_L_REG_DRAW_Y_MAX_0A -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0A_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0A_POS)) - -/* 0x88 : draw_partial_yuv_configb */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGB_OFFSET (0x88) -#define OSD_DRAW_L_REG_DRAW_TH_0B OSD_DRAW_L_REG_DRAW_TH_0B -#define OSD_DRAW_L_REG_DRAW_TH_0B_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0B_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0B OSD_DRAW_L_REG_DRAW_V_0B -#define OSD_DRAW_L_REG_DRAW_V_0B_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0B_POS) -#define OSD_DRAW_L_REG_DRAW_V_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0B OSD_DRAW_L_REG_DRAW_U_0B -#define OSD_DRAW_L_REG_DRAW_U_0B_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0B_POS) -#define OSD_DRAW_L_REG_DRAW_U_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0B OSD_DRAW_L_REG_DRAW_Y_0B -#define OSD_DRAW_L_REG_DRAW_Y_0B_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0B_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0B_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0B_POS)) - -/* 0x8C : draw_partial_x_configb */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGB_OFFSET (0x8C) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B OSD_DRAW_L_REG_DRAW_X_MIN_0B -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0B_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B OSD_DRAW_L_REG_DRAW_X_MAX_0B -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0B_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0B_POS)) - -/* 0x90 : draw_partial_y_configb */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGB_OFFSET (0x90) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B OSD_DRAW_L_REG_DRAW_Y_MIN_0B -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0B_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B OSD_DRAW_L_REG_DRAW_Y_MAX_0B -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0B_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0B_POS)) - -/* 0x94 : draw_partial_yuv_configc */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGC_OFFSET (0x94) -#define OSD_DRAW_L_REG_DRAW_TH_0C OSD_DRAW_L_REG_DRAW_TH_0C -#define OSD_DRAW_L_REG_DRAW_TH_0C_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0C_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0C OSD_DRAW_L_REG_DRAW_V_0C -#define OSD_DRAW_L_REG_DRAW_V_0C_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0C_POS) -#define OSD_DRAW_L_REG_DRAW_V_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0C OSD_DRAW_L_REG_DRAW_U_0C -#define OSD_DRAW_L_REG_DRAW_U_0C_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0C_POS) -#define OSD_DRAW_L_REG_DRAW_U_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0C OSD_DRAW_L_REG_DRAW_Y_0C -#define OSD_DRAW_L_REG_DRAW_Y_0C_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0C_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0C_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0C_POS)) - -/* 0x98 : draw_partial_x_configc */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGC_OFFSET (0x98) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C OSD_DRAW_L_REG_DRAW_X_MIN_0C -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0C_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C OSD_DRAW_L_REG_DRAW_X_MAX_0C -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0C_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0C_POS)) - -/* 0x9C : draw_partial_y_configc */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGC_OFFSET (0x9C) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C OSD_DRAW_L_REG_DRAW_Y_MIN_0C -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0C_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C OSD_DRAW_L_REG_DRAW_Y_MAX_0C -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0C_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0C_POS)) - -/* 0xA0 : draw_partial_yuv_configd */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGD_OFFSET (0xA0) -#define OSD_DRAW_L_REG_DRAW_TH_0D OSD_DRAW_L_REG_DRAW_TH_0D -#define OSD_DRAW_L_REG_DRAW_TH_0D_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0D_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0D OSD_DRAW_L_REG_DRAW_V_0D -#define OSD_DRAW_L_REG_DRAW_V_0D_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0D_POS) -#define OSD_DRAW_L_REG_DRAW_V_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0D OSD_DRAW_L_REG_DRAW_U_0D -#define OSD_DRAW_L_REG_DRAW_U_0D_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0D_POS) -#define OSD_DRAW_L_REG_DRAW_U_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0D OSD_DRAW_L_REG_DRAW_Y_0D -#define OSD_DRAW_L_REG_DRAW_Y_0D_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0D_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0D_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0D_POS)) - -/* 0xA4 : draw_partial_x_configd */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGD_OFFSET (0xA4) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D OSD_DRAW_L_REG_DRAW_X_MIN_0D -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0D_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D OSD_DRAW_L_REG_DRAW_X_MAX_0D -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0D_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0D_POS)) - -/* 0xA8 : draw_partial_y_configd */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGD_OFFSET (0xA8) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D OSD_DRAW_L_REG_DRAW_Y_MIN_0D -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0D_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D OSD_DRAW_L_REG_DRAW_Y_MAX_0D -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0D_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0D_POS)) - -/* 0xAC : draw_partial_yuv_confige */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGE_OFFSET (0xAC) -#define OSD_DRAW_L_REG_DRAW_TH_0E OSD_DRAW_L_REG_DRAW_TH_0E -#define OSD_DRAW_L_REG_DRAW_TH_0E_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0E_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0E OSD_DRAW_L_REG_DRAW_V_0E -#define OSD_DRAW_L_REG_DRAW_V_0E_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0E_POS) -#define OSD_DRAW_L_REG_DRAW_V_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0E OSD_DRAW_L_REG_DRAW_U_0E -#define OSD_DRAW_L_REG_DRAW_U_0E_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0E_POS) -#define OSD_DRAW_L_REG_DRAW_U_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0E OSD_DRAW_L_REG_DRAW_Y_0E -#define OSD_DRAW_L_REG_DRAW_Y_0E_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0E_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0E_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0E_POS)) - -/* 0xB0 : draw_partial_x_confige */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGE_OFFSET (0xB0) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E OSD_DRAW_L_REG_DRAW_X_MIN_0E -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0E_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E OSD_DRAW_L_REG_DRAW_X_MAX_0E -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0E_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0E_POS)) - -/* 0xB4 : draw_partial_y_confige */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGE_OFFSET (0xB4) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E OSD_DRAW_L_REG_DRAW_Y_MIN_0E -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0E_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E OSD_DRAW_L_REG_DRAW_Y_MAX_0E -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0E_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0E_POS)) - -/* 0xB8 : draw_partial_yuv_configf */ -#define OSD_DRAW_L_DRAW_PARTIAL_YUV_CONFIGF_OFFSET (0xB8) -#define OSD_DRAW_L_REG_DRAW_TH_0F OSD_DRAW_L_REG_DRAW_TH_0F -#define OSD_DRAW_L_REG_DRAW_TH_0F_POS (0U) -#define OSD_DRAW_L_REG_DRAW_TH_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_TH_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_TH_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0F_POS) -#define OSD_DRAW_L_REG_DRAW_TH_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_TH_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_TH_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_V_0F OSD_DRAW_L_REG_DRAW_V_0F -#define OSD_DRAW_L_REG_DRAW_V_0F_POS (8U) -#define OSD_DRAW_L_REG_DRAW_V_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_V_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_V_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0F_POS) -#define OSD_DRAW_L_REG_DRAW_V_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_V_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_V_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_U_0F OSD_DRAW_L_REG_DRAW_U_0F -#define OSD_DRAW_L_REG_DRAW_U_0F_POS (16U) -#define OSD_DRAW_L_REG_DRAW_U_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_U_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_U_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0F_POS) -#define OSD_DRAW_L_REG_DRAW_U_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_U_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_U_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_0F OSD_DRAW_L_REG_DRAW_Y_0F -#define OSD_DRAW_L_REG_DRAW_Y_0F_POS (24U) -#define OSD_DRAW_L_REG_DRAW_Y_0F_LEN (8U) -#define OSD_DRAW_L_REG_DRAW_Y_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0F_POS) -#define OSD_DRAW_L_REG_DRAW_Y_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_0F_POS)) - -/* 0xBC : draw_partial_x_configf */ -#define OSD_DRAW_L_DRAW_PARTIAL_X_CONFIGF_OFFSET (0xBC) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F OSD_DRAW_L_REG_DRAW_X_MIN_0F -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_POS (0U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0F_POS) -#define OSD_DRAW_L_REG_DRAW_X_MIN_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MIN_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F OSD_DRAW_L_REG_DRAW_X_MAX_0F -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_POS (16U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0F_POS) -#define OSD_DRAW_L_REG_DRAW_X_MAX_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_X_MAX_0F_POS)) - -/* 0xC0 : draw_partial_y_configf */ -#define OSD_DRAW_L_DRAW_PARTIAL_Y_CONFIGF_OFFSET (0xC0) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F OSD_DRAW_L_REG_DRAW_Y_MIN_0F -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_POS (0U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MIN_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MIN_0F_POS)) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F OSD_DRAW_L_REG_DRAW_Y_MAX_0F -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_POS (16U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_LEN (11U) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_MSK (((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_POS) -#define OSD_DRAW_L_REG_DRAW_Y_MAX_0F_UMSK (~(((1U << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_DRAW_L_REG_DRAW_Y_MAX_0F_POS)) - -/* 0xF8 : osd_int_sts */ -#define OSD_DRAW_L_OSD_INT_STS_OFFSET (0xF8) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_POS (0U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_MSK (((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_POS) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_CLR_W_POS)) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_POS (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_MSK (((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_POS) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_MASK_W_POS)) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_POS (2U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_MSK (((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_POS) -#define OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_SEOF_INT_EDGE_W_POS)) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R OSD_DRAW_L_STS_OSD_DRAIN_INT_R -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_POS (16U) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_LEN (4U) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_MSK (((1U << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_POS) -#define OSD_DRAW_L_STS_OSD_DRAIN_INT_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_DRAIN_INT_R_POS)) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R OSD_DRAW_L_STS_OSD_SEOF_INT_R -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_POS (20U) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_MSK (((1U << OSD_DRAW_L_STS_OSD_SEOF_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_SEOF_INT_R_POS) -#define OSD_DRAW_L_STS_OSD_SEOF_INT_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_SEOF_INT_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_SEOF_INT_R_POS)) - -/* 0xFC : osd_misc */ -#define OSD_DRAW_L_OSD_MISC_OFFSET (0xFC) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W OSD_DRAW_L_REG_OSD_BUS_STRT_W -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_POS (0U) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_MSK (((1U << OSD_DRAW_L_REG_OSD_BUS_STRT_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_BUS_STRT_W_POS) -#define OSD_DRAW_L_REG_OSD_BUS_STRT_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_BUS_STRT_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_BUS_STRT_W_POS)) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_POS (1U) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_LEN (1U) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_MSK (((1U << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_POS) -#define OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_FIFO_AUTO_CLR_W_POS)) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W OSD_DRAW_L_REG_QOS_SW_MODE_W -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_POS (4U) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_LEN (1U) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_MSK (((1U << OSD_DRAW_L_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_MODE_W_POS) -#define OSD_DRAW_L_REG_QOS_SW_MODE_W_UMSK (~(((1U << OSD_DRAW_L_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_MODE_W_POS)) -#define OSD_DRAW_L_REG_QOS_SW_W OSD_DRAW_L_REG_QOS_SW_W -#define OSD_DRAW_L_REG_QOS_SW_W_POS (5U) -#define OSD_DRAW_L_REG_QOS_SW_W_LEN (1U) -#define OSD_DRAW_L_REG_QOS_SW_W_MSK (((1U << OSD_DRAW_L_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_W_POS) -#define OSD_DRAW_L_REG_QOS_SW_W_UMSK (~(((1U << OSD_DRAW_L_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_L_REG_QOS_SW_W_POS)) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W OSD_DRAW_L_REG_OSD_OSTD_MAX_W -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_POS (8U) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_LEN (2U) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_MSK (((1U << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_POS) -#define OSD_DRAW_L_REG_OSD_OSTD_MAX_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_OSTD_MAX_W_POS)) -#define OSD_DRAW_L_REG_XLEN_W OSD_DRAW_L_REG_XLEN_W -#define OSD_DRAW_L_REG_XLEN_W_POS (12U) -#define OSD_DRAW_L_REG_XLEN_W_LEN (3U) -#define OSD_DRAW_L_REG_XLEN_W_MSK (((1U << OSD_DRAW_L_REG_XLEN_W_LEN) - 1) << OSD_DRAW_L_REG_XLEN_W_POS) -#define OSD_DRAW_L_REG_XLEN_W_UMSK (~(((1U << OSD_DRAW_L_REG_XLEN_W_LEN) - 1) << OSD_DRAW_L_REG_XLEN_W_POS)) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_POS (16U) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L0_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_POS (17U) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L1_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_POS (18U) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L2_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_POS (19U) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_L3_CMD_IDLE_R_POS)) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R OSD_DRAW_L_STS_OSD_AXI_IDLE_R -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_POS (20U) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_LEN (1U) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_MSK (((1U << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_POS) -#define OSD_DRAW_L_STS_OSD_AXI_IDLE_R_UMSK (~(((1U << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_L_STS_OSD_AXI_IDLE_R_POS)) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_POS (24U) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_LEN (8U) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_MSK (((1U << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_POS) -#define OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_UMSK (~(((1U << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_L_REG_OSD_PCLK_FORCE_ON_W_POS)) - -struct osd_draw_l_reg { - /* 0x0 : osd_draw_config */ - union { - struct { - uint32_t reg_draw_en_l : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_draw_type_l : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_draw_config; - - /* 0x4 : draw_partial_yuv_config0 */ - union { - struct { - uint32_t reg_draw_th_00 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_00 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_00 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_00 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config0; - - /* 0x8 : draw_partial_x_config0 */ - union { - struct { - uint32_t reg_draw_x_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config0; - - /* 0xC : draw_partial_y_config0 */ - union { - struct { - uint32_t reg_draw_y_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config0; - - /* 0x10 : draw_partial_yuv_config1 */ - union { - struct { - uint32_t reg_draw_th_01 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_01 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_01 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_01 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1; - - /* 0x14 : draw_partial_x_config1 */ - union { - struct { - uint32_t reg_draw_x_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1; - - /* 0x18 : draw_partial_y_config1 */ - union { - struct { - uint32_t reg_draw_y_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1; - - /* 0x1C : draw_partial_yuv_config2 */ - union { - struct { - uint32_t reg_draw_th_02 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_02 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_02 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_02 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config2; - - /* 0x20 : draw_partial_x_config2 */ - union { - struct { - uint32_t reg_draw_x_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config2; - - /* 0x24 : draw_partial_y_config2 */ - union { - struct { - uint32_t reg_draw_y_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config2; - - /* 0x28 : draw_partial_yuv_config3 */ - union { - struct { - uint32_t reg_draw_th_03 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_03 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_03 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_03 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config3; - - /* 0x2C : draw_partial_x_config3 */ - union { - struct { - uint32_t reg_draw_x_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config3; - - /* 0x30 : draw_partial_y_config3 */ - union { - struct { - uint32_t reg_draw_y_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config3; - - /* 0x34 : draw_partial_yuv_config4 */ - union { - struct { - uint32_t reg_draw_th_04 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_04 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_04 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_04 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config4; - - /* 0x38 : draw_partial_x_config4 */ - union { - struct { - uint32_t reg_draw_x_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config4; - - /* 0x3C : draw_partial_y_config4 */ - union { - struct { - uint32_t reg_draw_y_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config4; - - /* 0x40 : draw_partial_yuv_config5 */ - union { - struct { - uint32_t reg_draw_th_05 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_05 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_05 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_05 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config5; - - /* 0x44 : draw_partial_x_config5 */ - union { - struct { - uint32_t reg_draw_x_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config5; - - /* 0x48 : draw_partial_y_config5 */ - union { - struct { - uint32_t reg_draw_y_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config5; - - /* 0x4C : draw_partial_yuv_config6 */ - union { - struct { - uint32_t reg_draw_th_06 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_06 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_06 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_06 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config6; - - /* 0x50 : draw_partial_x_config6 */ - union { - struct { - uint32_t reg_draw_x_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config6; - - /* 0x54 : draw_partial_y_config6 */ - union { - struct { - uint32_t reg_draw_y_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config6; - - /* 0x58 : draw_partial_yuv_config7 */ - union { - struct { - uint32_t reg_draw_th_07 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_07 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_07 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_07 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config7; - - /* 0x5C : draw_partial_x_config7 */ - union { - struct { - uint32_t reg_draw_x_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config7; - - /* 0x60 : draw_partial_y_config7 */ - union { - struct { - uint32_t reg_draw_y_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config7; - - /* 0x64 : draw_partial_yuv_config8 */ - union { - struct { - uint32_t reg_draw_th_08 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_08 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_08 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_08 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config8; - - /* 0x68 : draw_partial_x_config8 */ - union { - struct { - uint32_t reg_draw_x_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config8; - - /* 0x6C : draw_partial_y_config8 */ - union { - struct { - uint32_t reg_draw_y_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config8; - - /* 0x70 : draw_partial_yuv_config9 */ - union { - struct { - uint32_t reg_draw_th_09 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_09 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_09 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_09 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config9; - - /* 0x74 : draw_partial_x_config9 */ - union { - struct { - uint32_t reg_draw_x_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config9; - - /* 0x78 : draw_partial_y_config9 */ - union { - struct { - uint32_t reg_draw_y_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config9; - - /* 0x7C : draw_partial_yuv_configa */ - union { - struct { - uint32_t reg_draw_th_0a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0a : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0a : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configa; - - /* 0x80 : draw_partial_x_configa */ - union { - struct { - uint32_t reg_draw_x_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configa; - - /* 0x84 : draw_partial_y_configa */ - union { - struct { - uint32_t reg_draw_y_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configa; - - /* 0x88 : draw_partial_yuv_configb */ - union { - struct { - uint32_t reg_draw_th_0b : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0b : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0b : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0b : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configb; - - /* 0x8C : draw_partial_x_configb */ - union { - struct { - uint32_t reg_draw_x_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configb; - - /* 0x90 : draw_partial_y_configb */ - union { - struct { - uint32_t reg_draw_y_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configb; - - /* 0x94 : draw_partial_yuv_configc */ - union { - struct { - uint32_t reg_draw_th_0c : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0c : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0c : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0c : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configc; - - /* 0x98 : draw_partial_x_configc */ - union { - struct { - uint32_t reg_draw_x_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configc; - - /* 0x9C : draw_partial_y_configc */ - union { - struct { - uint32_t reg_draw_y_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configc; - - /* 0xA0 : draw_partial_yuv_configd */ - union { - struct { - uint32_t reg_draw_th_0d : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0d : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0d : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0d : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configd; - - /* 0xA4 : draw_partial_x_configd */ - union { - struct { - uint32_t reg_draw_x_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configd; - - /* 0xA8 : draw_partial_y_configd */ - union { - struct { - uint32_t reg_draw_y_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configd; - - /* 0xAC : draw_partial_yuv_confige */ - union { - struct { - uint32_t reg_draw_th_0e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0e : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0e : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0e : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_confige; - - /* 0xB0 : draw_partial_x_confige */ - union { - struct { - uint32_t reg_draw_x_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_confige; - - /* 0xB4 : draw_partial_y_confige */ - union { - struct { - uint32_t reg_draw_y_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_confige; - - /* 0xB8 : draw_partial_yuv_configf */ - union { - struct { - uint32_t reg_draw_th_0f : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0f : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0f : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0f : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configf; - - /* 0xBC : draw_partial_x_configf */ - union { - struct { - uint32_t reg_draw_x_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configf; - - /* 0xC0 : draw_partial_y_configf */ - union { - struct { - uint32_t reg_draw_y_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configf; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[52]; - - /* 0xF8 : osd_int_sts */ - union { - struct { - uint32_t reg_osd_seof_int_clr_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_osd_seof_int_mask_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_osd_seof_int_edge_w : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_15 : 13; /* [15: 3], rsvd, 0x0 */ - uint32_t sts_osd_drain_int_r : 4; /* [19:16], r, 0x0 */ - uint32_t sts_osd_seof_int_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_int_sts; - - /* 0xFC : osd_misc */ - union { - struct { - uint32_t reg_osd_bus_strt_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_osd_fifo_auto_clr_w : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t reg_qos_sw_mode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_qos_sw_w : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_osd_ostd_max_w : 2; /* [ 9: 8], r/w, 0x3 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t reg_xlen_w : 3; /* [14:12], r/w, 0x4 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t sts_osd_l0_cmd_idle_r : 1; /* [ 16], r, 0x0 */ - uint32_t sts_osd_l1_cmd_idle_r : 1; /* [ 17], r, 0x0 */ - uint32_t sts_osd_l2_cmd_idle_r : 1; /* [ 18], r, 0x0 */ - uint32_t sts_osd_l3_cmd_idle_r : 1; /* [ 19], r, 0x0 */ - uint32_t sts_osd_axi_idle_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t reg_osd_pclk_force_on_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_misc; -}; - -typedef volatile struct osd_draw_l_reg osd_draw_l_reg_t; - -#endif /* __OSD_DRAW_L_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_reg.h deleted file mode 100644 index cb72bcfc1b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_draw_reg.h +++ /dev/null @@ -1,1511 +0,0 @@ -/** - ****************************************************************************** - * @file osd_reg.h - * @version V1.0 - * @date 2020-12-25 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_REG_H__ -#define __OSD_REG_H__ - -#include "bl808.h" - -/* 0x0 : osd_draw_config */ -#define OSD_DRAW_CONFIG_OFFSET (0x0) -#define OSD_REG_DRAW_EN_L OSD_REG_DRAW_EN_L -#define OSD_REG_DRAW_EN_L_POS (0U) -#define OSD_REG_DRAW_EN_L_LEN (16U) -#define OSD_REG_DRAW_EN_L_MSK (((1U << OSD_REG_DRAW_EN_L_LEN) - 1) << OSD_REG_DRAW_EN_L_POS) -#define OSD_REG_DRAW_EN_L_UMSK (~(((1U << OSD_REG_DRAW_EN_L_LEN) - 1) << OSD_REG_DRAW_EN_L_POS)) -#define OSD_REG_DRAW_TYPE_L OSD_REG_DRAW_TYPE_L -#define OSD_REG_DRAW_TYPE_L_POS (16U) -#define OSD_REG_DRAW_TYPE_L_LEN (16U) -#define OSD_REG_DRAW_TYPE_L_MSK (((1U << OSD_REG_DRAW_TYPE_L_LEN) - 1) << OSD_REG_DRAW_TYPE_L_POS) -#define OSD_REG_DRAW_TYPE_L_UMSK (~(((1U << OSD_REG_DRAW_TYPE_L_LEN) - 1) << OSD_REG_DRAW_TYPE_L_POS)) - -/* 0x4 : draw_partial_yuv_config0 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG0_OFFSET (0x4) -#define OSD_REG_DRAW_TH_00 OSD_REG_DRAW_TH_00 -#define OSD_REG_DRAW_TH_00_POS (0U) -#define OSD_REG_DRAW_TH_00_LEN (8U) -#define OSD_REG_DRAW_TH_00_MSK (((1U << OSD_REG_DRAW_TH_00_LEN) - 1) << OSD_REG_DRAW_TH_00_POS) -#define OSD_REG_DRAW_TH_00_UMSK (~(((1U << OSD_REG_DRAW_TH_00_LEN) - 1) << OSD_REG_DRAW_TH_00_POS)) -#define OSD_REG_DRAW_V_00 OSD_REG_DRAW_V_00 -#define OSD_REG_DRAW_V_00_POS (8U) -#define OSD_REG_DRAW_V_00_LEN (8U) -#define OSD_REG_DRAW_V_00_MSK (((1U << OSD_REG_DRAW_V_00_LEN) - 1) << OSD_REG_DRAW_V_00_POS) -#define OSD_REG_DRAW_V_00_UMSK (~(((1U << OSD_REG_DRAW_V_00_LEN) - 1) << OSD_REG_DRAW_V_00_POS)) -#define OSD_REG_DRAW_U_00 OSD_REG_DRAW_U_00 -#define OSD_REG_DRAW_U_00_POS (16U) -#define OSD_REG_DRAW_U_00_LEN (8U) -#define OSD_REG_DRAW_U_00_MSK (((1U << OSD_REG_DRAW_U_00_LEN) - 1) << OSD_REG_DRAW_U_00_POS) -#define OSD_REG_DRAW_U_00_UMSK (~(((1U << OSD_REG_DRAW_U_00_LEN) - 1) << OSD_REG_DRAW_U_00_POS)) -#define OSD_REG_DRAW_Y_00 OSD_REG_DRAW_Y_00 -#define OSD_REG_DRAW_Y_00_POS (24U) -#define OSD_REG_DRAW_Y_00_LEN (8U) -#define OSD_REG_DRAW_Y_00_MSK (((1U << OSD_REG_DRAW_Y_00_LEN) - 1) << OSD_REG_DRAW_Y_00_POS) -#define OSD_REG_DRAW_Y_00_UMSK (~(((1U << OSD_REG_DRAW_Y_00_LEN) - 1) << OSD_REG_DRAW_Y_00_POS)) - -/* 0x8 : draw_partial_x_config0 */ -#define OSD_DRAW_PARTIAL_X_CONFIG0_OFFSET (0x8) -#define OSD_REG_DRAW_X_MIN_00 OSD_REG_DRAW_X_MIN_00 -#define OSD_REG_DRAW_X_MIN_00_POS (0U) -#define OSD_REG_DRAW_X_MIN_00_LEN (11U) -#define OSD_REG_DRAW_X_MIN_00_MSK (((1U << OSD_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_REG_DRAW_X_MIN_00_POS) -#define OSD_REG_DRAW_X_MIN_00_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_00_LEN) - 1) << OSD_REG_DRAW_X_MIN_00_POS)) -#define OSD_REG_DRAW_X_MAX_00 OSD_REG_DRAW_X_MAX_00 -#define OSD_REG_DRAW_X_MAX_00_POS (16U) -#define OSD_REG_DRAW_X_MAX_00_LEN (11U) -#define OSD_REG_DRAW_X_MAX_00_MSK (((1U << OSD_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_REG_DRAW_X_MAX_00_POS) -#define OSD_REG_DRAW_X_MAX_00_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_00_LEN) - 1) << OSD_REG_DRAW_X_MAX_00_POS)) - -/* 0xC : draw_partial_y_config0 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG0_OFFSET (0xC) -#define OSD_REG_DRAW_Y_MIN_00 OSD_REG_DRAW_Y_MIN_00 -#define OSD_REG_DRAW_Y_MIN_00_POS (0U) -#define OSD_REG_DRAW_Y_MIN_00_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_00_MSK (((1U << OSD_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_REG_DRAW_Y_MIN_00_POS) -#define OSD_REG_DRAW_Y_MIN_00_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_00_LEN) - 1) << OSD_REG_DRAW_Y_MIN_00_POS)) -#define OSD_REG_DRAW_Y_MAX_00 OSD_REG_DRAW_Y_MAX_00 -#define OSD_REG_DRAW_Y_MAX_00_POS (16U) -#define OSD_REG_DRAW_Y_MAX_00_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_00_MSK (((1U << OSD_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_REG_DRAW_Y_MAX_00_POS) -#define OSD_REG_DRAW_Y_MAX_00_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_00_LEN) - 1) << OSD_REG_DRAW_Y_MAX_00_POS)) - -/* 0x10 : draw_partial_yuv_config1 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG1_OFFSET (0x10) -#define OSD_REG_DRAW_TH_01 OSD_REG_DRAW_TH_01 -#define OSD_REG_DRAW_TH_01_POS (0U) -#define OSD_REG_DRAW_TH_01_LEN (8U) -#define OSD_REG_DRAW_TH_01_MSK (((1U << OSD_REG_DRAW_TH_01_LEN) - 1) << OSD_REG_DRAW_TH_01_POS) -#define OSD_REG_DRAW_TH_01_UMSK (~(((1U << OSD_REG_DRAW_TH_01_LEN) - 1) << OSD_REG_DRAW_TH_01_POS)) -#define OSD_REG_DRAW_V_01 OSD_REG_DRAW_V_01 -#define OSD_REG_DRAW_V_01_POS (8U) -#define OSD_REG_DRAW_V_01_LEN (8U) -#define OSD_REG_DRAW_V_01_MSK (((1U << OSD_REG_DRAW_V_01_LEN) - 1) << OSD_REG_DRAW_V_01_POS) -#define OSD_REG_DRAW_V_01_UMSK (~(((1U << OSD_REG_DRAW_V_01_LEN) - 1) << OSD_REG_DRAW_V_01_POS)) -#define OSD_REG_DRAW_U_01 OSD_REG_DRAW_U_01 -#define OSD_REG_DRAW_U_01_POS (16U) -#define OSD_REG_DRAW_U_01_LEN (8U) -#define OSD_REG_DRAW_U_01_MSK (((1U << OSD_REG_DRAW_U_01_LEN) - 1) << OSD_REG_DRAW_U_01_POS) -#define OSD_REG_DRAW_U_01_UMSK (~(((1U << OSD_REG_DRAW_U_01_LEN) - 1) << OSD_REG_DRAW_U_01_POS)) -#define OSD_REG_DRAW_Y_01 OSD_REG_DRAW_Y_01 -#define OSD_REG_DRAW_Y_01_POS (24U) -#define OSD_REG_DRAW_Y_01_LEN (8U) -#define OSD_REG_DRAW_Y_01_MSK (((1U << OSD_REG_DRAW_Y_01_LEN) - 1) << OSD_REG_DRAW_Y_01_POS) -#define OSD_REG_DRAW_Y_01_UMSK (~(((1U << OSD_REG_DRAW_Y_01_LEN) - 1) << OSD_REG_DRAW_Y_01_POS)) - -/* 0x14 : draw_partial_x_config1 */ -#define OSD_DRAW_PARTIAL_X_CONFIG1_OFFSET (0x14) -#define OSD_REG_DRAW_X_MIN_01 OSD_REG_DRAW_X_MIN_01 -#define OSD_REG_DRAW_X_MIN_01_POS (0U) -#define OSD_REG_DRAW_X_MIN_01_LEN (11U) -#define OSD_REG_DRAW_X_MIN_01_MSK (((1U << OSD_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_REG_DRAW_X_MIN_01_POS) -#define OSD_REG_DRAW_X_MIN_01_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_01_LEN) - 1) << OSD_REG_DRAW_X_MIN_01_POS)) -#define OSD_REG_DRAW_X_MAX_01 OSD_REG_DRAW_X_MAX_01 -#define OSD_REG_DRAW_X_MAX_01_POS (16U) -#define OSD_REG_DRAW_X_MAX_01_LEN (11U) -#define OSD_REG_DRAW_X_MAX_01_MSK (((1U << OSD_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_REG_DRAW_X_MAX_01_POS) -#define OSD_REG_DRAW_X_MAX_01_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_01_LEN) - 1) << OSD_REG_DRAW_X_MAX_01_POS)) - -/* 0x18 : draw_partial_y_config1 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG1_OFFSET (0x18) -#define OSD_REG_DRAW_Y_MIN_01 OSD_REG_DRAW_Y_MIN_01 -#define OSD_REG_DRAW_Y_MIN_01_POS (0U) -#define OSD_REG_DRAW_Y_MIN_01_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_01_MSK (((1U << OSD_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_REG_DRAW_Y_MIN_01_POS) -#define OSD_REG_DRAW_Y_MIN_01_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_01_LEN) - 1) << OSD_REG_DRAW_Y_MIN_01_POS)) -#define OSD_REG_DRAW_Y_MAX_01 OSD_REG_DRAW_Y_MAX_01 -#define OSD_REG_DRAW_Y_MAX_01_POS (16U) -#define OSD_REG_DRAW_Y_MAX_01_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_01_MSK (((1U << OSD_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_REG_DRAW_Y_MAX_01_POS) -#define OSD_REG_DRAW_Y_MAX_01_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_01_LEN) - 1) << OSD_REG_DRAW_Y_MAX_01_POS)) - -/* 0x1C : draw_partial_yuv_config2 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG2_OFFSET (0x1C) -#define OSD_REG_DRAW_TH_02 OSD_REG_DRAW_TH_02 -#define OSD_REG_DRAW_TH_02_POS (0U) -#define OSD_REG_DRAW_TH_02_LEN (8U) -#define OSD_REG_DRAW_TH_02_MSK (((1U << OSD_REG_DRAW_TH_02_LEN) - 1) << OSD_REG_DRAW_TH_02_POS) -#define OSD_REG_DRAW_TH_02_UMSK (~(((1U << OSD_REG_DRAW_TH_02_LEN) - 1) << OSD_REG_DRAW_TH_02_POS)) -#define OSD_REG_DRAW_V_02 OSD_REG_DRAW_V_02 -#define OSD_REG_DRAW_V_02_POS (8U) -#define OSD_REG_DRAW_V_02_LEN (8U) -#define OSD_REG_DRAW_V_02_MSK (((1U << OSD_REG_DRAW_V_02_LEN) - 1) << OSD_REG_DRAW_V_02_POS) -#define OSD_REG_DRAW_V_02_UMSK (~(((1U << OSD_REG_DRAW_V_02_LEN) - 1) << OSD_REG_DRAW_V_02_POS)) -#define OSD_REG_DRAW_U_02 OSD_REG_DRAW_U_02 -#define OSD_REG_DRAW_U_02_POS (16U) -#define OSD_REG_DRAW_U_02_LEN (8U) -#define OSD_REG_DRAW_U_02_MSK (((1U << OSD_REG_DRAW_U_02_LEN) - 1) << OSD_REG_DRAW_U_02_POS) -#define OSD_REG_DRAW_U_02_UMSK (~(((1U << OSD_REG_DRAW_U_02_LEN) - 1) << OSD_REG_DRAW_U_02_POS)) -#define OSD_REG_DRAW_Y_02 OSD_REG_DRAW_Y_02 -#define OSD_REG_DRAW_Y_02_POS (24U) -#define OSD_REG_DRAW_Y_02_LEN (8U) -#define OSD_REG_DRAW_Y_02_MSK (((1U << OSD_REG_DRAW_Y_02_LEN) - 1) << OSD_REG_DRAW_Y_02_POS) -#define OSD_REG_DRAW_Y_02_UMSK (~(((1U << OSD_REG_DRAW_Y_02_LEN) - 1) << OSD_REG_DRAW_Y_02_POS)) - -/* 0x20 : draw_partial_x_config2 */ -#define OSD_DRAW_PARTIAL_X_CONFIG2_OFFSET (0x20) -#define OSD_REG_DRAW_X_MIN_02 OSD_REG_DRAW_X_MIN_02 -#define OSD_REG_DRAW_X_MIN_02_POS (0U) -#define OSD_REG_DRAW_X_MIN_02_LEN (11U) -#define OSD_REG_DRAW_X_MIN_02_MSK (((1U << OSD_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_REG_DRAW_X_MIN_02_POS) -#define OSD_REG_DRAW_X_MIN_02_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_02_LEN) - 1) << OSD_REG_DRAW_X_MIN_02_POS)) -#define OSD_REG_DRAW_X_MAX_02 OSD_REG_DRAW_X_MAX_02 -#define OSD_REG_DRAW_X_MAX_02_POS (16U) -#define OSD_REG_DRAW_X_MAX_02_LEN (11U) -#define OSD_REG_DRAW_X_MAX_02_MSK (((1U << OSD_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_REG_DRAW_X_MAX_02_POS) -#define OSD_REG_DRAW_X_MAX_02_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_02_LEN) - 1) << OSD_REG_DRAW_X_MAX_02_POS)) - -/* 0x24 : draw_partial_y_config2 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG2_OFFSET (0x24) -#define OSD_REG_DRAW_Y_MIN_02 OSD_REG_DRAW_Y_MIN_02 -#define OSD_REG_DRAW_Y_MIN_02_POS (0U) -#define OSD_REG_DRAW_Y_MIN_02_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_02_MSK (((1U << OSD_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_REG_DRAW_Y_MIN_02_POS) -#define OSD_REG_DRAW_Y_MIN_02_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_02_LEN) - 1) << OSD_REG_DRAW_Y_MIN_02_POS)) -#define OSD_REG_DRAW_Y_MAX_02 OSD_REG_DRAW_Y_MAX_02 -#define OSD_REG_DRAW_Y_MAX_02_POS (16U) -#define OSD_REG_DRAW_Y_MAX_02_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_02_MSK (((1U << OSD_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_REG_DRAW_Y_MAX_02_POS) -#define OSD_REG_DRAW_Y_MAX_02_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_02_LEN) - 1) << OSD_REG_DRAW_Y_MAX_02_POS)) - -/* 0x28 : draw_partial_yuv_config3 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG3_OFFSET (0x28) -#define OSD_REG_DRAW_TH_03 OSD_REG_DRAW_TH_03 -#define OSD_REG_DRAW_TH_03_POS (0U) -#define OSD_REG_DRAW_TH_03_LEN (8U) -#define OSD_REG_DRAW_TH_03_MSK (((1U << OSD_REG_DRAW_TH_03_LEN) - 1) << OSD_REG_DRAW_TH_03_POS) -#define OSD_REG_DRAW_TH_03_UMSK (~(((1U << OSD_REG_DRAW_TH_03_LEN) - 1) << OSD_REG_DRAW_TH_03_POS)) -#define OSD_REG_DRAW_V_03 OSD_REG_DRAW_V_03 -#define OSD_REG_DRAW_V_03_POS (8U) -#define OSD_REG_DRAW_V_03_LEN (8U) -#define OSD_REG_DRAW_V_03_MSK (((1U << OSD_REG_DRAW_V_03_LEN) - 1) << OSD_REG_DRAW_V_03_POS) -#define OSD_REG_DRAW_V_03_UMSK (~(((1U << OSD_REG_DRAW_V_03_LEN) - 1) << OSD_REG_DRAW_V_03_POS)) -#define OSD_REG_DRAW_U_03 OSD_REG_DRAW_U_03 -#define OSD_REG_DRAW_U_03_POS (16U) -#define OSD_REG_DRAW_U_03_LEN (8U) -#define OSD_REG_DRAW_U_03_MSK (((1U << OSD_REG_DRAW_U_03_LEN) - 1) << OSD_REG_DRAW_U_03_POS) -#define OSD_REG_DRAW_U_03_UMSK (~(((1U << OSD_REG_DRAW_U_03_LEN) - 1) << OSD_REG_DRAW_U_03_POS)) -#define OSD_REG_DRAW_Y_03 OSD_REG_DRAW_Y_03 -#define OSD_REG_DRAW_Y_03_POS (24U) -#define OSD_REG_DRAW_Y_03_LEN (8U) -#define OSD_REG_DRAW_Y_03_MSK (((1U << OSD_REG_DRAW_Y_03_LEN) - 1) << OSD_REG_DRAW_Y_03_POS) -#define OSD_REG_DRAW_Y_03_UMSK (~(((1U << OSD_REG_DRAW_Y_03_LEN) - 1) << OSD_REG_DRAW_Y_03_POS)) - -/* 0x2C : draw_partial_x_config3 */ -#define OSD_DRAW_PARTIAL_X_CONFIG3_OFFSET (0x2C) -#define OSD_REG_DRAW_X_MIN_03 OSD_REG_DRAW_X_MIN_03 -#define OSD_REG_DRAW_X_MIN_03_POS (0U) -#define OSD_REG_DRAW_X_MIN_03_LEN (11U) -#define OSD_REG_DRAW_X_MIN_03_MSK (((1U << OSD_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_REG_DRAW_X_MIN_03_POS) -#define OSD_REG_DRAW_X_MIN_03_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_03_LEN) - 1) << OSD_REG_DRAW_X_MIN_03_POS)) -#define OSD_REG_DRAW_X_MAX_03 OSD_REG_DRAW_X_MAX_03 -#define OSD_REG_DRAW_X_MAX_03_POS (16U) -#define OSD_REG_DRAW_X_MAX_03_LEN (11U) -#define OSD_REG_DRAW_X_MAX_03_MSK (((1U << OSD_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_REG_DRAW_X_MAX_03_POS) -#define OSD_REG_DRAW_X_MAX_03_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_03_LEN) - 1) << OSD_REG_DRAW_X_MAX_03_POS)) - -/* 0x30 : draw_partial_y_config3 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG3_OFFSET (0x30) -#define OSD_REG_DRAW_Y_MIN_03 OSD_REG_DRAW_Y_MIN_03 -#define OSD_REG_DRAW_Y_MIN_03_POS (0U) -#define OSD_REG_DRAW_Y_MIN_03_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_03_MSK (((1U << OSD_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_REG_DRAW_Y_MIN_03_POS) -#define OSD_REG_DRAW_Y_MIN_03_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_03_LEN) - 1) << OSD_REG_DRAW_Y_MIN_03_POS)) -#define OSD_REG_DRAW_Y_MAX_03 OSD_REG_DRAW_Y_MAX_03 -#define OSD_REG_DRAW_Y_MAX_03_POS (16U) -#define OSD_REG_DRAW_Y_MAX_03_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_03_MSK (((1U << OSD_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_REG_DRAW_Y_MAX_03_POS) -#define OSD_REG_DRAW_Y_MAX_03_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_03_LEN) - 1) << OSD_REG_DRAW_Y_MAX_03_POS)) - -/* 0x34 : draw_partial_yuv_config4 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG4_OFFSET (0x34) -#define OSD_REG_DRAW_TH_04 OSD_REG_DRAW_TH_04 -#define OSD_REG_DRAW_TH_04_POS (0U) -#define OSD_REG_DRAW_TH_04_LEN (8U) -#define OSD_REG_DRAW_TH_04_MSK (((1U << OSD_REG_DRAW_TH_04_LEN) - 1) << OSD_REG_DRAW_TH_04_POS) -#define OSD_REG_DRAW_TH_04_UMSK (~(((1U << OSD_REG_DRAW_TH_04_LEN) - 1) << OSD_REG_DRAW_TH_04_POS)) -#define OSD_REG_DRAW_V_04 OSD_REG_DRAW_V_04 -#define OSD_REG_DRAW_V_04_POS (8U) -#define OSD_REG_DRAW_V_04_LEN (8U) -#define OSD_REG_DRAW_V_04_MSK (((1U << OSD_REG_DRAW_V_04_LEN) - 1) << OSD_REG_DRAW_V_04_POS) -#define OSD_REG_DRAW_V_04_UMSK (~(((1U << OSD_REG_DRAW_V_04_LEN) - 1) << OSD_REG_DRAW_V_04_POS)) -#define OSD_REG_DRAW_U_04 OSD_REG_DRAW_U_04 -#define OSD_REG_DRAW_U_04_POS (16U) -#define OSD_REG_DRAW_U_04_LEN (8U) -#define OSD_REG_DRAW_U_04_MSK (((1U << OSD_REG_DRAW_U_04_LEN) - 1) << OSD_REG_DRAW_U_04_POS) -#define OSD_REG_DRAW_U_04_UMSK (~(((1U << OSD_REG_DRAW_U_04_LEN) - 1) << OSD_REG_DRAW_U_04_POS)) -#define OSD_REG_DRAW_Y_04 OSD_REG_DRAW_Y_04 -#define OSD_REG_DRAW_Y_04_POS (24U) -#define OSD_REG_DRAW_Y_04_LEN (8U) -#define OSD_REG_DRAW_Y_04_MSK (((1U << OSD_REG_DRAW_Y_04_LEN) - 1) << OSD_REG_DRAW_Y_04_POS) -#define OSD_REG_DRAW_Y_04_UMSK (~(((1U << OSD_REG_DRAW_Y_04_LEN) - 1) << OSD_REG_DRAW_Y_04_POS)) - -/* 0x38 : draw_partial_x_config4 */ -#define OSD_DRAW_PARTIAL_X_CONFIG4_OFFSET (0x38) -#define OSD_REG_DRAW_X_MIN_04 OSD_REG_DRAW_X_MIN_04 -#define OSD_REG_DRAW_X_MIN_04_POS (0U) -#define OSD_REG_DRAW_X_MIN_04_LEN (11U) -#define OSD_REG_DRAW_X_MIN_04_MSK (((1U << OSD_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_REG_DRAW_X_MIN_04_POS) -#define OSD_REG_DRAW_X_MIN_04_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_04_LEN) - 1) << OSD_REG_DRAW_X_MIN_04_POS)) -#define OSD_REG_DRAW_X_MAX_04 OSD_REG_DRAW_X_MAX_04 -#define OSD_REG_DRAW_X_MAX_04_POS (16U) -#define OSD_REG_DRAW_X_MAX_04_LEN (11U) -#define OSD_REG_DRAW_X_MAX_04_MSK (((1U << OSD_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_REG_DRAW_X_MAX_04_POS) -#define OSD_REG_DRAW_X_MAX_04_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_04_LEN) - 1) << OSD_REG_DRAW_X_MAX_04_POS)) - -/* 0x3C : draw_partial_y_config4 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG4_OFFSET (0x3C) -#define OSD_REG_DRAW_Y_MIN_04 OSD_REG_DRAW_Y_MIN_04 -#define OSD_REG_DRAW_Y_MIN_04_POS (0U) -#define OSD_REG_DRAW_Y_MIN_04_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_04_MSK (((1U << OSD_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_REG_DRAW_Y_MIN_04_POS) -#define OSD_REG_DRAW_Y_MIN_04_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_04_LEN) - 1) << OSD_REG_DRAW_Y_MIN_04_POS)) -#define OSD_REG_DRAW_Y_MAX_04 OSD_REG_DRAW_Y_MAX_04 -#define OSD_REG_DRAW_Y_MAX_04_POS (16U) -#define OSD_REG_DRAW_Y_MAX_04_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_04_MSK (((1U << OSD_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_REG_DRAW_Y_MAX_04_POS) -#define OSD_REG_DRAW_Y_MAX_04_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_04_LEN) - 1) << OSD_REG_DRAW_Y_MAX_04_POS)) - -/* 0x40 : draw_partial_yuv_config5 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG5_OFFSET (0x40) -#define OSD_REG_DRAW_TH_05 OSD_REG_DRAW_TH_05 -#define OSD_REG_DRAW_TH_05_POS (0U) -#define OSD_REG_DRAW_TH_05_LEN (8U) -#define OSD_REG_DRAW_TH_05_MSK (((1U << OSD_REG_DRAW_TH_05_LEN) - 1) << OSD_REG_DRAW_TH_05_POS) -#define OSD_REG_DRAW_TH_05_UMSK (~(((1U << OSD_REG_DRAW_TH_05_LEN) - 1) << OSD_REG_DRAW_TH_05_POS)) -#define OSD_REG_DRAW_V_05 OSD_REG_DRAW_V_05 -#define OSD_REG_DRAW_V_05_POS (8U) -#define OSD_REG_DRAW_V_05_LEN (8U) -#define OSD_REG_DRAW_V_05_MSK (((1U << OSD_REG_DRAW_V_05_LEN) - 1) << OSD_REG_DRAW_V_05_POS) -#define OSD_REG_DRAW_V_05_UMSK (~(((1U << OSD_REG_DRAW_V_05_LEN) - 1) << OSD_REG_DRAW_V_05_POS)) -#define OSD_REG_DRAW_U_05 OSD_REG_DRAW_U_05 -#define OSD_REG_DRAW_U_05_POS (16U) -#define OSD_REG_DRAW_U_05_LEN (8U) -#define OSD_REG_DRAW_U_05_MSK (((1U << OSD_REG_DRAW_U_05_LEN) - 1) << OSD_REG_DRAW_U_05_POS) -#define OSD_REG_DRAW_U_05_UMSK (~(((1U << OSD_REG_DRAW_U_05_LEN) - 1) << OSD_REG_DRAW_U_05_POS)) -#define OSD_REG_DRAW_Y_05 OSD_REG_DRAW_Y_05 -#define OSD_REG_DRAW_Y_05_POS (24U) -#define OSD_REG_DRAW_Y_05_LEN (8U) -#define OSD_REG_DRAW_Y_05_MSK (((1U << OSD_REG_DRAW_Y_05_LEN) - 1) << OSD_REG_DRAW_Y_05_POS) -#define OSD_REG_DRAW_Y_05_UMSK (~(((1U << OSD_REG_DRAW_Y_05_LEN) - 1) << OSD_REG_DRAW_Y_05_POS)) - -/* 0x44 : draw_partial_x_config5 */ -#define OSD_DRAW_PARTIAL_X_CONFIG5_OFFSET (0x44) -#define OSD_REG_DRAW_X_MIN_05 OSD_REG_DRAW_X_MIN_05 -#define OSD_REG_DRAW_X_MIN_05_POS (0U) -#define OSD_REG_DRAW_X_MIN_05_LEN (11U) -#define OSD_REG_DRAW_X_MIN_05_MSK (((1U << OSD_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_REG_DRAW_X_MIN_05_POS) -#define OSD_REG_DRAW_X_MIN_05_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_05_LEN) - 1) << OSD_REG_DRAW_X_MIN_05_POS)) -#define OSD_REG_DRAW_X_MAX_05 OSD_REG_DRAW_X_MAX_05 -#define OSD_REG_DRAW_X_MAX_05_POS (16U) -#define OSD_REG_DRAW_X_MAX_05_LEN (11U) -#define OSD_REG_DRAW_X_MAX_05_MSK (((1U << OSD_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_REG_DRAW_X_MAX_05_POS) -#define OSD_REG_DRAW_X_MAX_05_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_05_LEN) - 1) << OSD_REG_DRAW_X_MAX_05_POS)) - -/* 0x48 : draw_partial_y_config5 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG5_OFFSET (0x48) -#define OSD_REG_DRAW_Y_MIN_05 OSD_REG_DRAW_Y_MIN_05 -#define OSD_REG_DRAW_Y_MIN_05_POS (0U) -#define OSD_REG_DRAW_Y_MIN_05_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_05_MSK (((1U << OSD_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_REG_DRAW_Y_MIN_05_POS) -#define OSD_REG_DRAW_Y_MIN_05_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_05_LEN) - 1) << OSD_REG_DRAW_Y_MIN_05_POS)) -#define OSD_REG_DRAW_Y_MAX_05 OSD_REG_DRAW_Y_MAX_05 -#define OSD_REG_DRAW_Y_MAX_05_POS (16U) -#define OSD_REG_DRAW_Y_MAX_05_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_05_MSK (((1U << OSD_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_REG_DRAW_Y_MAX_05_POS) -#define OSD_REG_DRAW_Y_MAX_05_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_05_LEN) - 1) << OSD_REG_DRAW_Y_MAX_05_POS)) - -/* 0x4C : draw_partial_yuv_config6 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG6_OFFSET (0x4C) -#define OSD_REG_DRAW_TH_06 OSD_REG_DRAW_TH_06 -#define OSD_REG_DRAW_TH_06_POS (0U) -#define OSD_REG_DRAW_TH_06_LEN (8U) -#define OSD_REG_DRAW_TH_06_MSK (((1U << OSD_REG_DRAW_TH_06_LEN) - 1) << OSD_REG_DRAW_TH_06_POS) -#define OSD_REG_DRAW_TH_06_UMSK (~(((1U << OSD_REG_DRAW_TH_06_LEN) - 1) << OSD_REG_DRAW_TH_06_POS)) -#define OSD_REG_DRAW_V_06 OSD_REG_DRAW_V_06 -#define OSD_REG_DRAW_V_06_POS (8U) -#define OSD_REG_DRAW_V_06_LEN (8U) -#define OSD_REG_DRAW_V_06_MSK (((1U << OSD_REG_DRAW_V_06_LEN) - 1) << OSD_REG_DRAW_V_06_POS) -#define OSD_REG_DRAW_V_06_UMSK (~(((1U << OSD_REG_DRAW_V_06_LEN) - 1) << OSD_REG_DRAW_V_06_POS)) -#define OSD_REG_DRAW_U_06 OSD_REG_DRAW_U_06 -#define OSD_REG_DRAW_U_06_POS (16U) -#define OSD_REG_DRAW_U_06_LEN (8U) -#define OSD_REG_DRAW_U_06_MSK (((1U << OSD_REG_DRAW_U_06_LEN) - 1) << OSD_REG_DRAW_U_06_POS) -#define OSD_REG_DRAW_U_06_UMSK (~(((1U << OSD_REG_DRAW_U_06_LEN) - 1) << OSD_REG_DRAW_U_06_POS)) -#define OSD_REG_DRAW_Y_06 OSD_REG_DRAW_Y_06 -#define OSD_REG_DRAW_Y_06_POS (24U) -#define OSD_REG_DRAW_Y_06_LEN (8U) -#define OSD_REG_DRAW_Y_06_MSK (((1U << OSD_REG_DRAW_Y_06_LEN) - 1) << OSD_REG_DRAW_Y_06_POS) -#define OSD_REG_DRAW_Y_06_UMSK (~(((1U << OSD_REG_DRAW_Y_06_LEN) - 1) << OSD_REG_DRAW_Y_06_POS)) - -/* 0x50 : draw_partial_x_config6 */ -#define OSD_DRAW_PARTIAL_X_CONFIG6_OFFSET (0x50) -#define OSD_REG_DRAW_X_MIN_06 OSD_REG_DRAW_X_MIN_06 -#define OSD_REG_DRAW_X_MIN_06_POS (0U) -#define OSD_REG_DRAW_X_MIN_06_LEN (11U) -#define OSD_REG_DRAW_X_MIN_06_MSK (((1U << OSD_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_REG_DRAW_X_MIN_06_POS) -#define OSD_REG_DRAW_X_MIN_06_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_06_LEN) - 1) << OSD_REG_DRAW_X_MIN_06_POS)) -#define OSD_REG_DRAW_X_MAX_06 OSD_REG_DRAW_X_MAX_06 -#define OSD_REG_DRAW_X_MAX_06_POS (16U) -#define OSD_REG_DRAW_X_MAX_06_LEN (11U) -#define OSD_REG_DRAW_X_MAX_06_MSK (((1U << OSD_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_REG_DRAW_X_MAX_06_POS) -#define OSD_REG_DRAW_X_MAX_06_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_06_LEN) - 1) << OSD_REG_DRAW_X_MAX_06_POS)) - -/* 0x54 : draw_partial_y_config6 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG6_OFFSET (0x54) -#define OSD_REG_DRAW_Y_MIN_06 OSD_REG_DRAW_Y_MIN_06 -#define OSD_REG_DRAW_Y_MIN_06_POS (0U) -#define OSD_REG_DRAW_Y_MIN_06_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_06_MSK (((1U << OSD_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_REG_DRAW_Y_MIN_06_POS) -#define OSD_REG_DRAW_Y_MIN_06_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_06_LEN) - 1) << OSD_REG_DRAW_Y_MIN_06_POS)) -#define OSD_REG_DRAW_Y_MAX_06 OSD_REG_DRAW_Y_MAX_06 -#define OSD_REG_DRAW_Y_MAX_06_POS (16U) -#define OSD_REG_DRAW_Y_MAX_06_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_06_MSK (((1U << OSD_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_REG_DRAW_Y_MAX_06_POS) -#define OSD_REG_DRAW_Y_MAX_06_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_06_LEN) - 1) << OSD_REG_DRAW_Y_MAX_06_POS)) - -/* 0x58 : draw_partial_yuv_config7 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG7_OFFSET (0x58) -#define OSD_REG_DRAW_TH_07 OSD_REG_DRAW_TH_07 -#define OSD_REG_DRAW_TH_07_POS (0U) -#define OSD_REG_DRAW_TH_07_LEN (8U) -#define OSD_REG_DRAW_TH_07_MSK (((1U << OSD_REG_DRAW_TH_07_LEN) - 1) << OSD_REG_DRAW_TH_07_POS) -#define OSD_REG_DRAW_TH_07_UMSK (~(((1U << OSD_REG_DRAW_TH_07_LEN) - 1) << OSD_REG_DRAW_TH_07_POS)) -#define OSD_REG_DRAW_V_07 OSD_REG_DRAW_V_07 -#define OSD_REG_DRAW_V_07_POS (8U) -#define OSD_REG_DRAW_V_07_LEN (8U) -#define OSD_REG_DRAW_V_07_MSK (((1U << OSD_REG_DRAW_V_07_LEN) - 1) << OSD_REG_DRAW_V_07_POS) -#define OSD_REG_DRAW_V_07_UMSK (~(((1U << OSD_REG_DRAW_V_07_LEN) - 1) << OSD_REG_DRAW_V_07_POS)) -#define OSD_REG_DRAW_U_07 OSD_REG_DRAW_U_07 -#define OSD_REG_DRAW_U_07_POS (16U) -#define OSD_REG_DRAW_U_07_LEN (8U) -#define OSD_REG_DRAW_U_07_MSK (((1U << OSD_REG_DRAW_U_07_LEN) - 1) << OSD_REG_DRAW_U_07_POS) -#define OSD_REG_DRAW_U_07_UMSK (~(((1U << OSD_REG_DRAW_U_07_LEN) - 1) << OSD_REG_DRAW_U_07_POS)) -#define OSD_REG_DRAW_Y_07 OSD_REG_DRAW_Y_07 -#define OSD_REG_DRAW_Y_07_POS (24U) -#define OSD_REG_DRAW_Y_07_LEN (8U) -#define OSD_REG_DRAW_Y_07_MSK (((1U << OSD_REG_DRAW_Y_07_LEN) - 1) << OSD_REG_DRAW_Y_07_POS) -#define OSD_REG_DRAW_Y_07_UMSK (~(((1U << OSD_REG_DRAW_Y_07_LEN) - 1) << OSD_REG_DRAW_Y_07_POS)) - -/* 0x5C : draw_partial_x_config7 */ -#define OSD_DRAW_PARTIAL_X_CONFIG7_OFFSET (0x5C) -#define OSD_REG_DRAW_X_MIN_07 OSD_REG_DRAW_X_MIN_07 -#define OSD_REG_DRAW_X_MIN_07_POS (0U) -#define OSD_REG_DRAW_X_MIN_07_LEN (11U) -#define OSD_REG_DRAW_X_MIN_07_MSK (((1U << OSD_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_REG_DRAW_X_MIN_07_POS) -#define OSD_REG_DRAW_X_MIN_07_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_07_LEN) - 1) << OSD_REG_DRAW_X_MIN_07_POS)) -#define OSD_REG_DRAW_X_MAX_07 OSD_REG_DRAW_X_MAX_07 -#define OSD_REG_DRAW_X_MAX_07_POS (16U) -#define OSD_REG_DRAW_X_MAX_07_LEN (11U) -#define OSD_REG_DRAW_X_MAX_07_MSK (((1U << OSD_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_REG_DRAW_X_MAX_07_POS) -#define OSD_REG_DRAW_X_MAX_07_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_07_LEN) - 1) << OSD_REG_DRAW_X_MAX_07_POS)) - -/* 0x60 : draw_partial_y_config7 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG7_OFFSET (0x60) -#define OSD_REG_DRAW_Y_MIN_07 OSD_REG_DRAW_Y_MIN_07 -#define OSD_REG_DRAW_Y_MIN_07_POS (0U) -#define OSD_REG_DRAW_Y_MIN_07_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_07_MSK (((1U << OSD_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_REG_DRAW_Y_MIN_07_POS) -#define OSD_REG_DRAW_Y_MIN_07_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_07_LEN) - 1) << OSD_REG_DRAW_Y_MIN_07_POS)) -#define OSD_REG_DRAW_Y_MAX_07 OSD_REG_DRAW_Y_MAX_07 -#define OSD_REG_DRAW_Y_MAX_07_POS (16U) -#define OSD_REG_DRAW_Y_MAX_07_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_07_MSK (((1U << OSD_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_REG_DRAW_Y_MAX_07_POS) -#define OSD_REG_DRAW_Y_MAX_07_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_07_LEN) - 1) << OSD_REG_DRAW_Y_MAX_07_POS)) - -/* 0x64 : draw_partial_yuv_config8 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG8_OFFSET (0x64) -#define OSD_REG_DRAW_TH_08 OSD_REG_DRAW_TH_08 -#define OSD_REG_DRAW_TH_08_POS (0U) -#define OSD_REG_DRAW_TH_08_LEN (8U) -#define OSD_REG_DRAW_TH_08_MSK (((1U << OSD_REG_DRAW_TH_08_LEN) - 1) << OSD_REG_DRAW_TH_08_POS) -#define OSD_REG_DRAW_TH_08_UMSK (~(((1U << OSD_REG_DRAW_TH_08_LEN) - 1) << OSD_REG_DRAW_TH_08_POS)) -#define OSD_REG_DRAW_V_08 OSD_REG_DRAW_V_08 -#define OSD_REG_DRAW_V_08_POS (8U) -#define OSD_REG_DRAW_V_08_LEN (8U) -#define OSD_REG_DRAW_V_08_MSK (((1U << OSD_REG_DRAW_V_08_LEN) - 1) << OSD_REG_DRAW_V_08_POS) -#define OSD_REG_DRAW_V_08_UMSK (~(((1U << OSD_REG_DRAW_V_08_LEN) - 1) << OSD_REG_DRAW_V_08_POS)) -#define OSD_REG_DRAW_U_08 OSD_REG_DRAW_U_08 -#define OSD_REG_DRAW_U_08_POS (16U) -#define OSD_REG_DRAW_U_08_LEN (8U) -#define OSD_REG_DRAW_U_08_MSK (((1U << OSD_REG_DRAW_U_08_LEN) - 1) << OSD_REG_DRAW_U_08_POS) -#define OSD_REG_DRAW_U_08_UMSK (~(((1U << OSD_REG_DRAW_U_08_LEN) - 1) << OSD_REG_DRAW_U_08_POS)) -#define OSD_REG_DRAW_Y_08 OSD_REG_DRAW_Y_08 -#define OSD_REG_DRAW_Y_08_POS (24U) -#define OSD_REG_DRAW_Y_08_LEN (8U) -#define OSD_REG_DRAW_Y_08_MSK (((1U << OSD_REG_DRAW_Y_08_LEN) - 1) << OSD_REG_DRAW_Y_08_POS) -#define OSD_REG_DRAW_Y_08_UMSK (~(((1U << OSD_REG_DRAW_Y_08_LEN) - 1) << OSD_REG_DRAW_Y_08_POS)) - -/* 0x68 : draw_partial_x_config8 */ -#define OSD_DRAW_PARTIAL_X_CONFIG8_OFFSET (0x68) -#define OSD_REG_DRAW_X_MIN_08 OSD_REG_DRAW_X_MIN_08 -#define OSD_REG_DRAW_X_MIN_08_POS (0U) -#define OSD_REG_DRAW_X_MIN_08_LEN (11U) -#define OSD_REG_DRAW_X_MIN_08_MSK (((1U << OSD_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_REG_DRAW_X_MIN_08_POS) -#define OSD_REG_DRAW_X_MIN_08_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_08_LEN) - 1) << OSD_REG_DRAW_X_MIN_08_POS)) -#define OSD_REG_DRAW_X_MAX_08 OSD_REG_DRAW_X_MAX_08 -#define OSD_REG_DRAW_X_MAX_08_POS (16U) -#define OSD_REG_DRAW_X_MAX_08_LEN (11U) -#define OSD_REG_DRAW_X_MAX_08_MSK (((1U << OSD_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_REG_DRAW_X_MAX_08_POS) -#define OSD_REG_DRAW_X_MAX_08_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_08_LEN) - 1) << OSD_REG_DRAW_X_MAX_08_POS)) - -/* 0x6C : draw_partial_y_config8 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG8_OFFSET (0x6C) -#define OSD_REG_DRAW_Y_MIN_08 OSD_REG_DRAW_Y_MIN_08 -#define OSD_REG_DRAW_Y_MIN_08_POS (0U) -#define OSD_REG_DRAW_Y_MIN_08_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_08_MSK (((1U << OSD_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_REG_DRAW_Y_MIN_08_POS) -#define OSD_REG_DRAW_Y_MIN_08_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_08_LEN) - 1) << OSD_REG_DRAW_Y_MIN_08_POS)) -#define OSD_REG_DRAW_Y_MAX_08 OSD_REG_DRAW_Y_MAX_08 -#define OSD_REG_DRAW_Y_MAX_08_POS (16U) -#define OSD_REG_DRAW_Y_MAX_08_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_08_MSK (((1U << OSD_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_REG_DRAW_Y_MAX_08_POS) -#define OSD_REG_DRAW_Y_MAX_08_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_08_LEN) - 1) << OSD_REG_DRAW_Y_MAX_08_POS)) - -/* 0x70 : draw_partial_yuv_config9 */ -#define OSD_DRAW_PARTIAL_YUV_CONFIG9_OFFSET (0x70) -#define OSD_REG_DRAW_TH_09 OSD_REG_DRAW_TH_09 -#define OSD_REG_DRAW_TH_09_POS (0U) -#define OSD_REG_DRAW_TH_09_LEN (8U) -#define OSD_REG_DRAW_TH_09_MSK (((1U << OSD_REG_DRAW_TH_09_LEN) - 1) << OSD_REG_DRAW_TH_09_POS) -#define OSD_REG_DRAW_TH_09_UMSK (~(((1U << OSD_REG_DRAW_TH_09_LEN) - 1) << OSD_REG_DRAW_TH_09_POS)) -#define OSD_REG_DRAW_V_09 OSD_REG_DRAW_V_09 -#define OSD_REG_DRAW_V_09_POS (8U) -#define OSD_REG_DRAW_V_09_LEN (8U) -#define OSD_REG_DRAW_V_09_MSK (((1U << OSD_REG_DRAW_V_09_LEN) - 1) << OSD_REG_DRAW_V_09_POS) -#define OSD_REG_DRAW_V_09_UMSK (~(((1U << OSD_REG_DRAW_V_09_LEN) - 1) << OSD_REG_DRAW_V_09_POS)) -#define OSD_REG_DRAW_U_09 OSD_REG_DRAW_U_09 -#define OSD_REG_DRAW_U_09_POS (16U) -#define OSD_REG_DRAW_U_09_LEN (8U) -#define OSD_REG_DRAW_U_09_MSK (((1U << OSD_REG_DRAW_U_09_LEN) - 1) << OSD_REG_DRAW_U_09_POS) -#define OSD_REG_DRAW_U_09_UMSK (~(((1U << OSD_REG_DRAW_U_09_LEN) - 1) << OSD_REG_DRAW_U_09_POS)) -#define OSD_REG_DRAW_Y_09 OSD_REG_DRAW_Y_09 -#define OSD_REG_DRAW_Y_09_POS (24U) -#define OSD_REG_DRAW_Y_09_LEN (8U) -#define OSD_REG_DRAW_Y_09_MSK (((1U << OSD_REG_DRAW_Y_09_LEN) - 1) << OSD_REG_DRAW_Y_09_POS) -#define OSD_REG_DRAW_Y_09_UMSK (~(((1U << OSD_REG_DRAW_Y_09_LEN) - 1) << OSD_REG_DRAW_Y_09_POS)) - -/* 0x74 : draw_partial_x_config9 */ -#define OSD_DRAW_PARTIAL_X_CONFIG9_OFFSET (0x74) -#define OSD_REG_DRAW_X_MIN_09 OSD_REG_DRAW_X_MIN_09 -#define OSD_REG_DRAW_X_MIN_09_POS (0U) -#define OSD_REG_DRAW_X_MIN_09_LEN (11U) -#define OSD_REG_DRAW_X_MIN_09_MSK (((1U << OSD_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_REG_DRAW_X_MIN_09_POS) -#define OSD_REG_DRAW_X_MIN_09_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_09_LEN) - 1) << OSD_REG_DRAW_X_MIN_09_POS)) -#define OSD_REG_DRAW_X_MAX_09 OSD_REG_DRAW_X_MAX_09 -#define OSD_REG_DRAW_X_MAX_09_POS (16U) -#define OSD_REG_DRAW_X_MAX_09_LEN (11U) -#define OSD_REG_DRAW_X_MAX_09_MSK (((1U << OSD_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_REG_DRAW_X_MAX_09_POS) -#define OSD_REG_DRAW_X_MAX_09_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_09_LEN) - 1) << OSD_REG_DRAW_X_MAX_09_POS)) - -/* 0x78 : draw_partial_y_config9 */ -#define OSD_DRAW_PARTIAL_Y_CONFIG9_OFFSET (0x78) -#define OSD_REG_DRAW_Y_MIN_09 OSD_REG_DRAW_Y_MIN_09 -#define OSD_REG_DRAW_Y_MIN_09_POS (0U) -#define OSD_REG_DRAW_Y_MIN_09_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_09_MSK (((1U << OSD_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_REG_DRAW_Y_MIN_09_POS) -#define OSD_REG_DRAW_Y_MIN_09_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_09_LEN) - 1) << OSD_REG_DRAW_Y_MIN_09_POS)) -#define OSD_REG_DRAW_Y_MAX_09 OSD_REG_DRAW_Y_MAX_09 -#define OSD_REG_DRAW_Y_MAX_09_POS (16U) -#define OSD_REG_DRAW_Y_MAX_09_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_09_MSK (((1U << OSD_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_REG_DRAW_Y_MAX_09_POS) -#define OSD_REG_DRAW_Y_MAX_09_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_09_LEN) - 1) << OSD_REG_DRAW_Y_MAX_09_POS)) - -/* 0x7C : draw_partial_yuv_configa */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGA_OFFSET (0x7C) -#define OSD_REG_DRAW_TH_0A OSD_REG_DRAW_TH_0A -#define OSD_REG_DRAW_TH_0A_POS (0U) -#define OSD_REG_DRAW_TH_0A_LEN (8U) -#define OSD_REG_DRAW_TH_0A_MSK (((1U << OSD_REG_DRAW_TH_0A_LEN) - 1) << OSD_REG_DRAW_TH_0A_POS) -#define OSD_REG_DRAW_TH_0A_UMSK (~(((1U << OSD_REG_DRAW_TH_0A_LEN) - 1) << OSD_REG_DRAW_TH_0A_POS)) -#define OSD_REG_DRAW_V_0A OSD_REG_DRAW_V_0A -#define OSD_REG_DRAW_V_0A_POS (8U) -#define OSD_REG_DRAW_V_0A_LEN (8U) -#define OSD_REG_DRAW_V_0A_MSK (((1U << OSD_REG_DRAW_V_0A_LEN) - 1) << OSD_REG_DRAW_V_0A_POS) -#define OSD_REG_DRAW_V_0A_UMSK (~(((1U << OSD_REG_DRAW_V_0A_LEN) - 1) << OSD_REG_DRAW_V_0A_POS)) -#define OSD_REG_DRAW_U_0A OSD_REG_DRAW_U_0A -#define OSD_REG_DRAW_U_0A_POS (16U) -#define OSD_REG_DRAW_U_0A_LEN (8U) -#define OSD_REG_DRAW_U_0A_MSK (((1U << OSD_REG_DRAW_U_0A_LEN) - 1) << OSD_REG_DRAW_U_0A_POS) -#define OSD_REG_DRAW_U_0A_UMSK (~(((1U << OSD_REG_DRAW_U_0A_LEN) - 1) << OSD_REG_DRAW_U_0A_POS)) -#define OSD_REG_DRAW_Y_0A OSD_REG_DRAW_Y_0A -#define OSD_REG_DRAW_Y_0A_POS (24U) -#define OSD_REG_DRAW_Y_0A_LEN (8U) -#define OSD_REG_DRAW_Y_0A_MSK (((1U << OSD_REG_DRAW_Y_0A_LEN) - 1) << OSD_REG_DRAW_Y_0A_POS) -#define OSD_REG_DRAW_Y_0A_UMSK (~(((1U << OSD_REG_DRAW_Y_0A_LEN) - 1) << OSD_REG_DRAW_Y_0A_POS)) - -/* 0x80 : draw_partial_x_configa */ -#define OSD_DRAW_PARTIAL_X_CONFIGA_OFFSET (0x80) -#define OSD_REG_DRAW_X_MIN_0A OSD_REG_DRAW_X_MIN_0A -#define OSD_REG_DRAW_X_MIN_0A_POS (0U) -#define OSD_REG_DRAW_X_MIN_0A_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0A_MSK (((1U << OSD_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_REG_DRAW_X_MIN_0A_POS) -#define OSD_REG_DRAW_X_MIN_0A_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0A_LEN) - 1) << OSD_REG_DRAW_X_MIN_0A_POS)) -#define OSD_REG_DRAW_X_MAX_0A OSD_REG_DRAW_X_MAX_0A -#define OSD_REG_DRAW_X_MAX_0A_POS (16U) -#define OSD_REG_DRAW_X_MAX_0A_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0A_MSK (((1U << OSD_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_REG_DRAW_X_MAX_0A_POS) -#define OSD_REG_DRAW_X_MAX_0A_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0A_LEN) - 1) << OSD_REG_DRAW_X_MAX_0A_POS)) - -/* 0x84 : draw_partial_y_configa */ -#define OSD_DRAW_PARTIAL_Y_CONFIGA_OFFSET (0x84) -#define OSD_REG_DRAW_Y_MIN_0A OSD_REG_DRAW_Y_MIN_0A -#define OSD_REG_DRAW_Y_MIN_0A_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0A_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0A_MSK (((1U << OSD_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0A_POS) -#define OSD_REG_DRAW_Y_MIN_0A_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0A_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0A_POS)) -#define OSD_REG_DRAW_Y_MAX_0A OSD_REG_DRAW_Y_MAX_0A -#define OSD_REG_DRAW_Y_MAX_0A_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0A_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0A_MSK (((1U << OSD_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0A_POS) -#define OSD_REG_DRAW_Y_MAX_0A_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0A_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0A_POS)) - -/* 0x88 : draw_partial_yuv_configb */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGB_OFFSET (0x88) -#define OSD_REG_DRAW_TH_0B OSD_REG_DRAW_TH_0B -#define OSD_REG_DRAW_TH_0B_POS (0U) -#define OSD_REG_DRAW_TH_0B_LEN (8U) -#define OSD_REG_DRAW_TH_0B_MSK (((1U << OSD_REG_DRAW_TH_0B_LEN) - 1) << OSD_REG_DRAW_TH_0B_POS) -#define OSD_REG_DRAW_TH_0B_UMSK (~(((1U << OSD_REG_DRAW_TH_0B_LEN) - 1) << OSD_REG_DRAW_TH_0B_POS)) -#define OSD_REG_DRAW_V_0B OSD_REG_DRAW_V_0B -#define OSD_REG_DRAW_V_0B_POS (8U) -#define OSD_REG_DRAW_V_0B_LEN (8U) -#define OSD_REG_DRAW_V_0B_MSK (((1U << OSD_REG_DRAW_V_0B_LEN) - 1) << OSD_REG_DRAW_V_0B_POS) -#define OSD_REG_DRAW_V_0B_UMSK (~(((1U << OSD_REG_DRAW_V_0B_LEN) - 1) << OSD_REG_DRAW_V_0B_POS)) -#define OSD_REG_DRAW_U_0B OSD_REG_DRAW_U_0B -#define OSD_REG_DRAW_U_0B_POS (16U) -#define OSD_REG_DRAW_U_0B_LEN (8U) -#define OSD_REG_DRAW_U_0B_MSK (((1U << OSD_REG_DRAW_U_0B_LEN) - 1) << OSD_REG_DRAW_U_0B_POS) -#define OSD_REG_DRAW_U_0B_UMSK (~(((1U << OSD_REG_DRAW_U_0B_LEN) - 1) << OSD_REG_DRAW_U_0B_POS)) -#define OSD_REG_DRAW_Y_0B OSD_REG_DRAW_Y_0B -#define OSD_REG_DRAW_Y_0B_POS (24U) -#define OSD_REG_DRAW_Y_0B_LEN (8U) -#define OSD_REG_DRAW_Y_0B_MSK (((1U << OSD_REG_DRAW_Y_0B_LEN) - 1) << OSD_REG_DRAW_Y_0B_POS) -#define OSD_REG_DRAW_Y_0B_UMSK (~(((1U << OSD_REG_DRAW_Y_0B_LEN) - 1) << OSD_REG_DRAW_Y_0B_POS)) - -/* 0x8C : draw_partial_x_configb */ -#define OSD_DRAW_PARTIAL_X_CONFIGB_OFFSET (0x8C) -#define OSD_REG_DRAW_X_MIN_0B OSD_REG_DRAW_X_MIN_0B -#define OSD_REG_DRAW_X_MIN_0B_POS (0U) -#define OSD_REG_DRAW_X_MIN_0B_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0B_MSK (((1U << OSD_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_REG_DRAW_X_MIN_0B_POS) -#define OSD_REG_DRAW_X_MIN_0B_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0B_LEN) - 1) << OSD_REG_DRAW_X_MIN_0B_POS)) -#define OSD_REG_DRAW_X_MAX_0B OSD_REG_DRAW_X_MAX_0B -#define OSD_REG_DRAW_X_MAX_0B_POS (16U) -#define OSD_REG_DRAW_X_MAX_0B_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0B_MSK (((1U << OSD_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_REG_DRAW_X_MAX_0B_POS) -#define OSD_REG_DRAW_X_MAX_0B_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0B_LEN) - 1) << OSD_REG_DRAW_X_MAX_0B_POS)) - -/* 0x90 : draw_partial_y_configb */ -#define OSD_DRAW_PARTIAL_Y_CONFIGB_OFFSET (0x90) -#define OSD_REG_DRAW_Y_MIN_0B OSD_REG_DRAW_Y_MIN_0B -#define OSD_REG_DRAW_Y_MIN_0B_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0B_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0B_MSK (((1U << OSD_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0B_POS) -#define OSD_REG_DRAW_Y_MIN_0B_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0B_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0B_POS)) -#define OSD_REG_DRAW_Y_MAX_0B OSD_REG_DRAW_Y_MAX_0B -#define OSD_REG_DRAW_Y_MAX_0B_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0B_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0B_MSK (((1U << OSD_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0B_POS) -#define OSD_REG_DRAW_Y_MAX_0B_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0B_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0B_POS)) - -/* 0x94 : draw_partial_yuv_configc */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGC_OFFSET (0x94) -#define OSD_REG_DRAW_TH_0C OSD_REG_DRAW_TH_0C -#define OSD_REG_DRAW_TH_0C_POS (0U) -#define OSD_REG_DRAW_TH_0C_LEN (8U) -#define OSD_REG_DRAW_TH_0C_MSK (((1U << OSD_REG_DRAW_TH_0C_LEN) - 1) << OSD_REG_DRAW_TH_0C_POS) -#define OSD_REG_DRAW_TH_0C_UMSK (~(((1U << OSD_REG_DRAW_TH_0C_LEN) - 1) << OSD_REG_DRAW_TH_0C_POS)) -#define OSD_REG_DRAW_V_0C OSD_REG_DRAW_V_0C -#define OSD_REG_DRAW_V_0C_POS (8U) -#define OSD_REG_DRAW_V_0C_LEN (8U) -#define OSD_REG_DRAW_V_0C_MSK (((1U << OSD_REG_DRAW_V_0C_LEN) - 1) << OSD_REG_DRAW_V_0C_POS) -#define OSD_REG_DRAW_V_0C_UMSK (~(((1U << OSD_REG_DRAW_V_0C_LEN) - 1) << OSD_REG_DRAW_V_0C_POS)) -#define OSD_REG_DRAW_U_0C OSD_REG_DRAW_U_0C -#define OSD_REG_DRAW_U_0C_POS (16U) -#define OSD_REG_DRAW_U_0C_LEN (8U) -#define OSD_REG_DRAW_U_0C_MSK (((1U << OSD_REG_DRAW_U_0C_LEN) - 1) << OSD_REG_DRAW_U_0C_POS) -#define OSD_REG_DRAW_U_0C_UMSK (~(((1U << OSD_REG_DRAW_U_0C_LEN) - 1) << OSD_REG_DRAW_U_0C_POS)) -#define OSD_REG_DRAW_Y_0C OSD_REG_DRAW_Y_0C -#define OSD_REG_DRAW_Y_0C_POS (24U) -#define OSD_REG_DRAW_Y_0C_LEN (8U) -#define OSD_REG_DRAW_Y_0C_MSK (((1U << OSD_REG_DRAW_Y_0C_LEN) - 1) << OSD_REG_DRAW_Y_0C_POS) -#define OSD_REG_DRAW_Y_0C_UMSK (~(((1U << OSD_REG_DRAW_Y_0C_LEN) - 1) << OSD_REG_DRAW_Y_0C_POS)) - -/* 0x98 : draw_partial_x_configc */ -#define OSD_DRAW_PARTIAL_X_CONFIGC_OFFSET (0x98) -#define OSD_REG_DRAW_X_MIN_0C OSD_REG_DRAW_X_MIN_0C -#define OSD_REG_DRAW_X_MIN_0C_POS (0U) -#define OSD_REG_DRAW_X_MIN_0C_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0C_MSK (((1U << OSD_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_REG_DRAW_X_MIN_0C_POS) -#define OSD_REG_DRAW_X_MIN_0C_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0C_LEN) - 1) << OSD_REG_DRAW_X_MIN_0C_POS)) -#define OSD_REG_DRAW_X_MAX_0C OSD_REG_DRAW_X_MAX_0C -#define OSD_REG_DRAW_X_MAX_0C_POS (16U) -#define OSD_REG_DRAW_X_MAX_0C_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0C_MSK (((1U << OSD_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_REG_DRAW_X_MAX_0C_POS) -#define OSD_REG_DRAW_X_MAX_0C_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0C_LEN) - 1) << OSD_REG_DRAW_X_MAX_0C_POS)) - -/* 0x9C : draw_partial_y_configc */ -#define OSD_DRAW_PARTIAL_Y_CONFIGC_OFFSET (0x9C) -#define OSD_REG_DRAW_Y_MIN_0C OSD_REG_DRAW_Y_MIN_0C -#define OSD_REG_DRAW_Y_MIN_0C_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0C_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0C_MSK (((1U << OSD_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0C_POS) -#define OSD_REG_DRAW_Y_MIN_0C_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0C_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0C_POS)) -#define OSD_REG_DRAW_Y_MAX_0C OSD_REG_DRAW_Y_MAX_0C -#define OSD_REG_DRAW_Y_MAX_0C_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0C_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0C_MSK (((1U << OSD_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0C_POS) -#define OSD_REG_DRAW_Y_MAX_0C_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0C_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0C_POS)) - -/* 0xA0 : draw_partial_yuv_configd */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGD_OFFSET (0xA0) -#define OSD_REG_DRAW_TH_0D OSD_REG_DRAW_TH_0D -#define OSD_REG_DRAW_TH_0D_POS (0U) -#define OSD_REG_DRAW_TH_0D_LEN (8U) -#define OSD_REG_DRAW_TH_0D_MSK (((1U << OSD_REG_DRAW_TH_0D_LEN) - 1) << OSD_REG_DRAW_TH_0D_POS) -#define OSD_REG_DRAW_TH_0D_UMSK (~(((1U << OSD_REG_DRAW_TH_0D_LEN) - 1) << OSD_REG_DRAW_TH_0D_POS)) -#define OSD_REG_DRAW_V_0D OSD_REG_DRAW_V_0D -#define OSD_REG_DRAW_V_0D_POS (8U) -#define OSD_REG_DRAW_V_0D_LEN (8U) -#define OSD_REG_DRAW_V_0D_MSK (((1U << OSD_REG_DRAW_V_0D_LEN) - 1) << OSD_REG_DRAW_V_0D_POS) -#define OSD_REG_DRAW_V_0D_UMSK (~(((1U << OSD_REG_DRAW_V_0D_LEN) - 1) << OSD_REG_DRAW_V_0D_POS)) -#define OSD_REG_DRAW_U_0D OSD_REG_DRAW_U_0D -#define OSD_REG_DRAW_U_0D_POS (16U) -#define OSD_REG_DRAW_U_0D_LEN (8U) -#define OSD_REG_DRAW_U_0D_MSK (((1U << OSD_REG_DRAW_U_0D_LEN) - 1) << OSD_REG_DRAW_U_0D_POS) -#define OSD_REG_DRAW_U_0D_UMSK (~(((1U << OSD_REG_DRAW_U_0D_LEN) - 1) << OSD_REG_DRAW_U_0D_POS)) -#define OSD_REG_DRAW_Y_0D OSD_REG_DRAW_Y_0D -#define OSD_REG_DRAW_Y_0D_POS (24U) -#define OSD_REG_DRAW_Y_0D_LEN (8U) -#define OSD_REG_DRAW_Y_0D_MSK (((1U << OSD_REG_DRAW_Y_0D_LEN) - 1) << OSD_REG_DRAW_Y_0D_POS) -#define OSD_REG_DRAW_Y_0D_UMSK (~(((1U << OSD_REG_DRAW_Y_0D_LEN) - 1) << OSD_REG_DRAW_Y_0D_POS)) - -/* 0xA4 : draw_partial_x_configd */ -#define OSD_DRAW_PARTIAL_X_CONFIGD_OFFSET (0xA4) -#define OSD_REG_DRAW_X_MIN_0D OSD_REG_DRAW_X_MIN_0D -#define OSD_REG_DRAW_X_MIN_0D_POS (0U) -#define OSD_REG_DRAW_X_MIN_0D_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0D_MSK (((1U << OSD_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_REG_DRAW_X_MIN_0D_POS) -#define OSD_REG_DRAW_X_MIN_0D_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0D_LEN) - 1) << OSD_REG_DRAW_X_MIN_0D_POS)) -#define OSD_REG_DRAW_X_MAX_0D OSD_REG_DRAW_X_MAX_0D -#define OSD_REG_DRAW_X_MAX_0D_POS (16U) -#define OSD_REG_DRAW_X_MAX_0D_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0D_MSK (((1U << OSD_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_REG_DRAW_X_MAX_0D_POS) -#define OSD_REG_DRAW_X_MAX_0D_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0D_LEN) - 1) << OSD_REG_DRAW_X_MAX_0D_POS)) - -/* 0xA8 : draw_partial_y_configd */ -#define OSD_DRAW_PARTIAL_Y_CONFIGD_OFFSET (0xA8) -#define OSD_REG_DRAW_Y_MIN_0D OSD_REG_DRAW_Y_MIN_0D -#define OSD_REG_DRAW_Y_MIN_0D_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0D_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0D_MSK (((1U << OSD_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0D_POS) -#define OSD_REG_DRAW_Y_MIN_0D_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0D_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0D_POS)) -#define OSD_REG_DRAW_Y_MAX_0D OSD_REG_DRAW_Y_MAX_0D -#define OSD_REG_DRAW_Y_MAX_0D_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0D_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0D_MSK (((1U << OSD_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0D_POS) -#define OSD_REG_DRAW_Y_MAX_0D_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0D_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0D_POS)) - -/* 0xAC : draw_partial_yuv_confige */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGE_OFFSET (0xAC) -#define OSD_REG_DRAW_TH_0E OSD_REG_DRAW_TH_0E -#define OSD_REG_DRAW_TH_0E_POS (0U) -#define OSD_REG_DRAW_TH_0E_LEN (8U) -#define OSD_REG_DRAW_TH_0E_MSK (((1U << OSD_REG_DRAW_TH_0E_LEN) - 1) << OSD_REG_DRAW_TH_0E_POS) -#define OSD_REG_DRAW_TH_0E_UMSK (~(((1U << OSD_REG_DRAW_TH_0E_LEN) - 1) << OSD_REG_DRAW_TH_0E_POS)) -#define OSD_REG_DRAW_V_0E OSD_REG_DRAW_V_0E -#define OSD_REG_DRAW_V_0E_POS (8U) -#define OSD_REG_DRAW_V_0E_LEN (8U) -#define OSD_REG_DRAW_V_0E_MSK (((1U << OSD_REG_DRAW_V_0E_LEN) - 1) << OSD_REG_DRAW_V_0E_POS) -#define OSD_REG_DRAW_V_0E_UMSK (~(((1U << OSD_REG_DRAW_V_0E_LEN) - 1) << OSD_REG_DRAW_V_0E_POS)) -#define OSD_REG_DRAW_U_0E OSD_REG_DRAW_U_0E -#define OSD_REG_DRAW_U_0E_POS (16U) -#define OSD_REG_DRAW_U_0E_LEN (8U) -#define OSD_REG_DRAW_U_0E_MSK (((1U << OSD_REG_DRAW_U_0E_LEN) - 1) << OSD_REG_DRAW_U_0E_POS) -#define OSD_REG_DRAW_U_0E_UMSK (~(((1U << OSD_REG_DRAW_U_0E_LEN) - 1) << OSD_REG_DRAW_U_0E_POS)) -#define OSD_REG_DRAW_Y_0E OSD_REG_DRAW_Y_0E -#define OSD_REG_DRAW_Y_0E_POS (24U) -#define OSD_REG_DRAW_Y_0E_LEN (8U) -#define OSD_REG_DRAW_Y_0E_MSK (((1U << OSD_REG_DRAW_Y_0E_LEN) - 1) << OSD_REG_DRAW_Y_0E_POS) -#define OSD_REG_DRAW_Y_0E_UMSK (~(((1U << OSD_REG_DRAW_Y_0E_LEN) - 1) << OSD_REG_DRAW_Y_0E_POS)) - -/* 0xB0 : draw_partial_x_confige */ -#define OSD_DRAW_PARTIAL_X_CONFIGE_OFFSET (0xB0) -#define OSD_REG_DRAW_X_MIN_0E OSD_REG_DRAW_X_MIN_0E -#define OSD_REG_DRAW_X_MIN_0E_POS (0U) -#define OSD_REG_DRAW_X_MIN_0E_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0E_MSK (((1U << OSD_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_REG_DRAW_X_MIN_0E_POS) -#define OSD_REG_DRAW_X_MIN_0E_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0E_LEN) - 1) << OSD_REG_DRAW_X_MIN_0E_POS)) -#define OSD_REG_DRAW_X_MAX_0E OSD_REG_DRAW_X_MAX_0E -#define OSD_REG_DRAW_X_MAX_0E_POS (16U) -#define OSD_REG_DRAW_X_MAX_0E_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0E_MSK (((1U << OSD_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_REG_DRAW_X_MAX_0E_POS) -#define OSD_REG_DRAW_X_MAX_0E_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0E_LEN) - 1) << OSD_REG_DRAW_X_MAX_0E_POS)) - -/* 0xB4 : draw_partial_y_confige */ -#define OSD_DRAW_PARTIAL_Y_CONFIGE_OFFSET (0xB4) -#define OSD_REG_DRAW_Y_MIN_0E OSD_REG_DRAW_Y_MIN_0E -#define OSD_REG_DRAW_Y_MIN_0E_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0E_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0E_MSK (((1U << OSD_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0E_POS) -#define OSD_REG_DRAW_Y_MIN_0E_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0E_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0E_POS)) -#define OSD_REG_DRAW_Y_MAX_0E OSD_REG_DRAW_Y_MAX_0E -#define OSD_REG_DRAW_Y_MAX_0E_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0E_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0E_MSK (((1U << OSD_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0E_POS) -#define OSD_REG_DRAW_Y_MAX_0E_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0E_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0E_POS)) - -/* 0xB8 : draw_partial_yuv_configf */ -#define OSD_DRAW_PARTIAL_YUV_CONFIGF_OFFSET (0xB8) -#define OSD_REG_DRAW_TH_0F OSD_REG_DRAW_TH_0F -#define OSD_REG_DRAW_TH_0F_POS (0U) -#define OSD_REG_DRAW_TH_0F_LEN (8U) -#define OSD_REG_DRAW_TH_0F_MSK (((1U << OSD_REG_DRAW_TH_0F_LEN) - 1) << OSD_REG_DRAW_TH_0F_POS) -#define OSD_REG_DRAW_TH_0F_UMSK (~(((1U << OSD_REG_DRAW_TH_0F_LEN) - 1) << OSD_REG_DRAW_TH_0F_POS)) -#define OSD_REG_DRAW_V_0F OSD_REG_DRAW_V_0F -#define OSD_REG_DRAW_V_0F_POS (8U) -#define OSD_REG_DRAW_V_0F_LEN (8U) -#define OSD_REG_DRAW_V_0F_MSK (((1U << OSD_REG_DRAW_V_0F_LEN) - 1) << OSD_REG_DRAW_V_0F_POS) -#define OSD_REG_DRAW_V_0F_UMSK (~(((1U << OSD_REG_DRAW_V_0F_LEN) - 1) << OSD_REG_DRAW_V_0F_POS)) -#define OSD_REG_DRAW_U_0F OSD_REG_DRAW_U_0F -#define OSD_REG_DRAW_U_0F_POS (16U) -#define OSD_REG_DRAW_U_0F_LEN (8U) -#define OSD_REG_DRAW_U_0F_MSK (((1U << OSD_REG_DRAW_U_0F_LEN) - 1) << OSD_REG_DRAW_U_0F_POS) -#define OSD_REG_DRAW_U_0F_UMSK (~(((1U << OSD_REG_DRAW_U_0F_LEN) - 1) << OSD_REG_DRAW_U_0F_POS)) -#define OSD_REG_DRAW_Y_0F OSD_REG_DRAW_Y_0F -#define OSD_REG_DRAW_Y_0F_POS (24U) -#define OSD_REG_DRAW_Y_0F_LEN (8U) -#define OSD_REG_DRAW_Y_0F_MSK (((1U << OSD_REG_DRAW_Y_0F_LEN) - 1) << OSD_REG_DRAW_Y_0F_POS) -#define OSD_REG_DRAW_Y_0F_UMSK (~(((1U << OSD_REG_DRAW_Y_0F_LEN) - 1) << OSD_REG_DRAW_Y_0F_POS)) - -/* 0xBC : draw_partial_x_configf */ -#define OSD_DRAW_PARTIAL_X_CONFIGF_OFFSET (0xBC) -#define OSD_REG_DRAW_X_MIN_0F OSD_REG_DRAW_X_MIN_0F -#define OSD_REG_DRAW_X_MIN_0F_POS (0U) -#define OSD_REG_DRAW_X_MIN_0F_LEN (11U) -#define OSD_REG_DRAW_X_MIN_0F_MSK (((1U << OSD_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_REG_DRAW_X_MIN_0F_POS) -#define OSD_REG_DRAW_X_MIN_0F_UMSK (~(((1U << OSD_REG_DRAW_X_MIN_0F_LEN) - 1) << OSD_REG_DRAW_X_MIN_0F_POS)) -#define OSD_REG_DRAW_X_MAX_0F OSD_REG_DRAW_X_MAX_0F -#define OSD_REG_DRAW_X_MAX_0F_POS (16U) -#define OSD_REG_DRAW_X_MAX_0F_LEN (11U) -#define OSD_REG_DRAW_X_MAX_0F_MSK (((1U << OSD_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_REG_DRAW_X_MAX_0F_POS) -#define OSD_REG_DRAW_X_MAX_0F_UMSK (~(((1U << OSD_REG_DRAW_X_MAX_0F_LEN) - 1) << OSD_REG_DRAW_X_MAX_0F_POS)) - -/* 0xC0 : draw_partial_y_configf */ -#define OSD_DRAW_PARTIAL_Y_CONFIGF_OFFSET (0xC0) -#define OSD_REG_DRAW_Y_MIN_0F OSD_REG_DRAW_Y_MIN_0F -#define OSD_REG_DRAW_Y_MIN_0F_POS (0U) -#define OSD_REG_DRAW_Y_MIN_0F_LEN (11U) -#define OSD_REG_DRAW_Y_MIN_0F_MSK (((1U << OSD_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0F_POS) -#define OSD_REG_DRAW_Y_MIN_0F_UMSK (~(((1U << OSD_REG_DRAW_Y_MIN_0F_LEN) - 1) << OSD_REG_DRAW_Y_MIN_0F_POS)) -#define OSD_REG_DRAW_Y_MAX_0F OSD_REG_DRAW_Y_MAX_0F -#define OSD_REG_DRAW_Y_MAX_0F_POS (16U) -#define OSD_REG_DRAW_Y_MAX_0F_LEN (11U) -#define OSD_REG_DRAW_Y_MAX_0F_MSK (((1U << OSD_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0F_POS) -#define OSD_REG_DRAW_Y_MAX_0F_UMSK (~(((1U << OSD_REG_DRAW_Y_MAX_0F_LEN) - 1) << OSD_REG_DRAW_Y_MAX_0F_POS)) - -/* 0xF8 : osd_int_sts */ -#define OSD_DRAW_INT_STS_OFFSET (0xF8) -#define OSD_DRAW_REG_SEOF_INT_CLR_W OSD_DRAW_REG_SEOF_INT_CLR_W -#define OSD_DRAW_REG_SEOF_INT_CLR_W_POS (0U) -#define OSD_DRAW_REG_SEOF_INT_CLR_W_LEN (1U) -#define OSD_DRAW_REG_SEOF_INT_CLR_W_MSK (((1U << OSD_DRAW_REG_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_CLR_W_POS) -#define OSD_DRAW_REG_SEOF_INT_CLR_W_UMSK (~(((1U << OSD_DRAW_REG_SEOF_INT_CLR_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_CLR_W_POS)) -#define OSD_DRAW_REG_SEOF_INT_MASK_W OSD_DRAW_REG_SEOF_INT_MASK_W -#define OSD_DRAW_REG_SEOF_INT_MASK_W_POS (1U) -#define OSD_DRAW_REG_SEOF_INT_MASK_W_LEN (1U) -#define OSD_DRAW_REG_SEOF_INT_MASK_W_MSK (((1U << OSD_DRAW_REG_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_MASK_W_POS) -#define OSD_DRAW_REG_SEOF_INT_MASK_W_UMSK (~(((1U << OSD_DRAW_REG_SEOF_INT_MASK_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_MASK_W_POS)) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W OSD_DRAW_REG_SEOF_INT_EDGE_W -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_POS (2U) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_LEN (1U) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_MSK (((1U << OSD_DRAW_REG_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_EDGE_W_POS) -#define OSD_DRAW_REG_SEOF_INT_EDGE_W_UMSK (~(((1U << OSD_DRAW_REG_SEOF_INT_EDGE_W_LEN) - 1) << OSD_DRAW_REG_SEOF_INT_EDGE_W_POS)) -#define OSD_DRAW_STS_DRAIN_INT_R OSD_DRAW_STS_DRAIN_INT_R -#define OSD_DRAW_STS_DRAIN_INT_R_POS (16U) -#define OSD_DRAW_STS_DRAIN_INT_R_LEN (4U) -#define OSD_DRAW_STS_DRAIN_INT_R_MSK (((1U << OSD_DRAW_STS_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_STS_DRAIN_INT_R_POS) -#define OSD_DRAW_STS_DRAIN_INT_R_UMSK (~(((1U << OSD_DRAW_STS_DRAIN_INT_R_LEN) - 1) << OSD_DRAW_STS_DRAIN_INT_R_POS)) -#define OSD_DRAW_STS_SEOF_INT_R OSD_DRAW_STS_SEOF_INT_R -#define OSD_DRAW_STS_SEOF_INT_R_POS (20U) -#define OSD_DRAW_STS_SEOF_INT_R_LEN (1U) -#define OSD_DRAW_STS_SEOF_INT_R_MSK (((1U << OSD_DRAW_STS_SEOF_INT_R_LEN) - 1) << OSD_DRAW_STS_SEOF_INT_R_POS) -#define OSD_DRAW_STS_SEOF_INT_R_UMSK (~(((1U << OSD_DRAW_STS_SEOF_INT_R_LEN) - 1) << OSD_DRAW_STS_SEOF_INT_R_POS)) - -/* 0xFC : osd_misc */ -#define OSD_DRAW_MISC_OFFSET (0xFC) -#define OSD_DRAW_REG_BUS_STRT_W OSD_DRAW_REG_BUS_STRT_W -#define OSD_DRAW_REG_BUS_STRT_W_POS (0U) -#define OSD_DRAW_REG_BUS_STRT_W_LEN (1U) -#define OSD_DRAW_REG_BUS_STRT_W_MSK (((1U << OSD_DRAW_REG_BUS_STRT_W_LEN) - 1) << OSD_DRAW_REG_BUS_STRT_W_POS) -#define OSD_DRAW_REG_BUS_STRT_W_UMSK (~(((1U << OSD_DRAW_REG_BUS_STRT_W_LEN) - 1) << OSD_DRAW_REG_BUS_STRT_W_POS)) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W OSD_DRAW_REG_FIFO_AUTO_CLR_W -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_POS (1U) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_LEN (1U) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_MSK (((1U << OSD_DRAW_REG_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_REG_FIFO_AUTO_CLR_W_POS) -#define OSD_DRAW_REG_FIFO_AUTO_CLR_W_UMSK (~(((1U << OSD_DRAW_REG_FIFO_AUTO_CLR_W_LEN) - 1) << OSD_DRAW_REG_FIFO_AUTO_CLR_W_POS)) -#define OSD_DRAW_REG_QOS_SW_MODE_W OSD_DRAW_REG_QOS_SW_MODE_W -#define OSD_DRAW_REG_QOS_SW_MODE_W_POS (4U) -#define OSD_DRAW_REG_QOS_SW_MODE_W_LEN (1U) -#define OSD_DRAW_REG_QOS_SW_MODE_W_MSK (((1U << OSD_DRAW_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_MODE_W_POS) -#define OSD_DRAW_REG_QOS_SW_MODE_W_UMSK (~(((1U << OSD_DRAW_REG_QOS_SW_MODE_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_MODE_W_POS)) -#define OSD_DRAW_REG_QOS_SW_W OSD_DRAW_REG_QOS_SW_W -#define OSD_DRAW_REG_QOS_SW_W_POS (5U) -#define OSD_DRAW_REG_QOS_SW_W_LEN (1U) -#define OSD_DRAW_REG_QOS_SW_W_MSK (((1U << OSD_DRAW_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_W_POS) -#define OSD_DRAW_REG_QOS_SW_W_UMSK (~(((1U << OSD_DRAW_REG_QOS_SW_W_LEN) - 1) << OSD_DRAW_REG_QOS_SW_W_POS)) -#define OSD_DRAW_REG_OSTD_MAX_W OSD_DRAW_REG_OSTD_MAX_W -#define OSD_DRAW_REG_OSTD_MAX_W_POS (8U) -#define OSD_DRAW_REG_OSTD_MAX_W_LEN (2U) -#define OSD_DRAW_REG_OSTD_MAX_W_MSK (((1U << OSD_DRAW_REG_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_REG_OSTD_MAX_W_POS) -#define OSD_DRAW_REG_OSTD_MAX_W_UMSK (~(((1U << OSD_DRAW_REG_OSTD_MAX_W_LEN) - 1) << OSD_DRAW_REG_OSTD_MAX_W_POS)) -#define OSD_DRAW_REG_XLEN_W OSD_DRAW_REG_XLEN_W -#define OSD_DRAW_REG_XLEN_W_POS (12U) -#define OSD_DRAW_REG_XLEN_W_LEN (3U) -#define OSD_DRAW_REG_XLEN_W_MSK (((1U << OSD_DRAW_REG_XLEN_W_LEN) - 1) << OSD_DRAW_REG_XLEN_W_POS) -#define OSD_DRAW_REG_XLEN_W_UMSK (~(((1U << OSD_DRAW_REG_XLEN_W_LEN) - 1) << OSD_DRAW_REG_XLEN_W_POS)) -#define OSD_DRAW_STS_L0_CMD_IDLE_R OSD_DRAW_STS_L0_CMD_IDLE_R -#define OSD_DRAW_STS_L0_CMD_IDLE_R_POS (16U) -#define OSD_DRAW_STS_L0_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L0_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L0_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L0_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L0_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L0_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_L1_CMD_IDLE_R OSD_DRAW_STS_L1_CMD_IDLE_R -#define OSD_DRAW_STS_L1_CMD_IDLE_R_POS (17U) -#define OSD_DRAW_STS_L1_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L1_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L1_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L1_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L1_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L1_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_L2_CMD_IDLE_R OSD_DRAW_STS_L2_CMD_IDLE_R -#define OSD_DRAW_STS_L2_CMD_IDLE_R_POS (18U) -#define OSD_DRAW_STS_L2_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L2_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L2_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L2_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L2_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L2_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_L3_CMD_IDLE_R OSD_DRAW_STS_L3_CMD_IDLE_R -#define OSD_DRAW_STS_L3_CMD_IDLE_R_POS (19U) -#define OSD_DRAW_STS_L3_CMD_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_L3_CMD_IDLE_R_MSK (((1U << OSD_DRAW_STS_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L3_CMD_IDLE_R_POS) -#define OSD_DRAW_STS_L3_CMD_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_L3_CMD_IDLE_R_LEN) - 1) << OSD_DRAW_STS_L3_CMD_IDLE_R_POS)) -#define OSD_DRAW_STS_AXI_IDLE_R OSD_DRAW_STS_AXI_IDLE_R -#define OSD_DRAW_STS_AXI_IDLE_R_POS (20U) -#define OSD_DRAW_STS_AXI_IDLE_R_LEN (1U) -#define OSD_DRAW_STS_AXI_IDLE_R_MSK (((1U << OSD_DRAW_STS_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_STS_AXI_IDLE_R_POS) -#define OSD_DRAW_STS_AXI_IDLE_R_UMSK (~(((1U << OSD_DRAW_STS_AXI_IDLE_R_LEN) - 1) << OSD_DRAW_STS_AXI_IDLE_R_POS)) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W OSD_DRAW_REG_PCLK_FORCE_ON_W -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_POS (24U) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_LEN (8U) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_MSK (((1U << OSD_DRAW_REG_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_REG_PCLK_FORCE_ON_W_POS) -#define OSD_DRAW_REG_PCLK_FORCE_ON_W_UMSK (~(((1U << OSD_DRAW_REG_PCLK_FORCE_ON_W_LEN) - 1) << OSD_DRAW_REG_PCLK_FORCE_ON_W_POS)) - -struct osd_draw_reg { - /* 0x0 : osd_draw_config */ - union { - struct { - uint32_t reg_draw_en_l : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reg_draw_type_l : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_draw_config; - - /* 0x4 : draw_partial_yuv_config0 */ - union { - struct { - uint32_t reg_draw_th_00 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_00 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_00 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_00 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config0; - - /* 0x8 : draw_partial_x_config0 */ - union { - struct { - uint32_t reg_draw_x_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config0; - - /* 0xC : draw_partial_y_config0 */ - union { - struct { - uint32_t reg_draw_y_min_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config0; - - /* 0x10 : draw_partial_yuv_config1 */ - union { - struct { - uint32_t reg_draw_th_01 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_01 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_01 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_01 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config1; - - /* 0x14 : draw_partial_x_config1 */ - union { - struct { - uint32_t reg_draw_x_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config1; - - /* 0x18 : draw_partial_y_config1 */ - union { - struct { - uint32_t reg_draw_y_min_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config1; - - /* 0x1C : draw_partial_yuv_config2 */ - union { - struct { - uint32_t reg_draw_th_02 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_02 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_02 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_02 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config2; - - /* 0x20 : draw_partial_x_config2 */ - union { - struct { - uint32_t reg_draw_x_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config2; - - /* 0x24 : draw_partial_y_config2 */ - union { - struct { - uint32_t reg_draw_y_min_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config2; - - /* 0x28 : draw_partial_yuv_config3 */ - union { - struct { - uint32_t reg_draw_th_03 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_03 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_03 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_03 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config3; - - /* 0x2C : draw_partial_x_config3 */ - union { - struct { - uint32_t reg_draw_x_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config3; - - /* 0x30 : draw_partial_y_config3 */ - union { - struct { - uint32_t reg_draw_y_min_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config3; - - /* 0x34 : draw_partial_yuv_config4 */ - union { - struct { - uint32_t reg_draw_th_04 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_04 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_04 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_04 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config4; - - /* 0x38 : draw_partial_x_config4 */ - union { - struct { - uint32_t reg_draw_x_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config4; - - /* 0x3C : draw_partial_y_config4 */ - union { - struct { - uint32_t reg_draw_y_min_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config4; - - /* 0x40 : draw_partial_yuv_config5 */ - union { - struct { - uint32_t reg_draw_th_05 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_05 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_05 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_05 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config5; - - /* 0x44 : draw_partial_x_config5 */ - union { - struct { - uint32_t reg_draw_x_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config5; - - /* 0x48 : draw_partial_y_config5 */ - union { - struct { - uint32_t reg_draw_y_min_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config5; - - /* 0x4C : draw_partial_yuv_config6 */ - union { - struct { - uint32_t reg_draw_th_06 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_06 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_06 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_06 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config6; - - /* 0x50 : draw_partial_x_config6 */ - union { - struct { - uint32_t reg_draw_x_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config6; - - /* 0x54 : draw_partial_y_config6 */ - union { - struct { - uint32_t reg_draw_y_min_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config6; - - /* 0x58 : draw_partial_yuv_config7 */ - union { - struct { - uint32_t reg_draw_th_07 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_07 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_07 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_07 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config7; - - /* 0x5C : draw_partial_x_config7 */ - union { - struct { - uint32_t reg_draw_x_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config7; - - /* 0x60 : draw_partial_y_config7 */ - union { - struct { - uint32_t reg_draw_y_min_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config7; - - /* 0x64 : draw_partial_yuv_config8 */ - union { - struct { - uint32_t reg_draw_th_08 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_08 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_08 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_08 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config8; - - /* 0x68 : draw_partial_x_config8 */ - union { - struct { - uint32_t reg_draw_x_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config8; - - /* 0x6C : draw_partial_y_config8 */ - union { - struct { - uint32_t reg_draw_y_min_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config8; - - /* 0x70 : draw_partial_yuv_config9 */ - union { - struct { - uint32_t reg_draw_th_09 : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_09 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_09 : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_09 : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_config9; - - /* 0x74 : draw_partial_x_config9 */ - union { - struct { - uint32_t reg_draw_x_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_config9; - - /* 0x78 : draw_partial_y_config9 */ - union { - struct { - uint32_t reg_draw_y_min_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_config9; - - /* 0x7C : draw_partial_yuv_configa */ - union { - struct { - uint32_t reg_draw_th_0a : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0a : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0a : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0a : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configa; - - /* 0x80 : draw_partial_x_configa */ - union { - struct { - uint32_t reg_draw_x_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configa; - - /* 0x84 : draw_partial_y_configa */ - union { - struct { - uint32_t reg_draw_y_min_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configa; - - /* 0x88 : draw_partial_yuv_configb */ - union { - struct { - uint32_t reg_draw_th_0b : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0b : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0b : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0b : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configb; - - /* 0x8C : draw_partial_x_configb */ - union { - struct { - uint32_t reg_draw_x_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configb; - - /* 0x90 : draw_partial_y_configb */ - union { - struct { - uint32_t reg_draw_y_min_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configb; - - /* 0x94 : draw_partial_yuv_configc */ - union { - struct { - uint32_t reg_draw_th_0c : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0c : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0c : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0c : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configc; - - /* 0x98 : draw_partial_x_configc */ - union { - struct { - uint32_t reg_draw_x_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configc; - - /* 0x9C : draw_partial_y_configc */ - union { - struct { - uint32_t reg_draw_y_min_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configc; - - /* 0xA0 : draw_partial_yuv_configd */ - union { - struct { - uint32_t reg_draw_th_0d : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0d : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0d : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0d : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configd; - - /* 0xA4 : draw_partial_x_configd */ - union { - struct { - uint32_t reg_draw_x_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configd; - - /* 0xA8 : draw_partial_y_configd */ - union { - struct { - uint32_t reg_draw_y_min_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configd; - - /* 0xAC : draw_partial_yuv_confige */ - union { - struct { - uint32_t reg_draw_th_0e : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0e : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0e : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0e : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_confige; - - /* 0xB0 : draw_partial_x_confige */ - union { - struct { - uint32_t reg_draw_x_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_confige; - - /* 0xB4 : draw_partial_y_confige */ - union { - struct { - uint32_t reg_draw_y_min_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_confige; - - /* 0xB8 : draw_partial_yuv_configf */ - union { - struct { - uint32_t reg_draw_th_0f : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t reg_draw_v_0f : 8; /* [15: 8], r/w, 0x0 */ - uint32_t reg_draw_u_0f : 8; /* [23:16], r/w, 0x0 */ - uint32_t reg_draw_y_0f : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_yuv_configf; - - /* 0xBC : draw_partial_x_configf */ - union { - struct { - uint32_t reg_draw_x_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_x_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_x_configf; - - /* 0xC0 : draw_partial_y_configf */ - union { - struct { - uint32_t reg_draw_y_min_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_draw_y_max_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } draw_partial_y_configf; - - /* 0xc4 reserved */ - uint8_t RESERVED0xc4[52]; - - /* 0xF8 : osd_int_sts */ - union { - struct { - uint32_t reg_seof_int_clr_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_seof_int_mask_w : 1; /* [ 1], r/w, 0x0 */ - uint32_t reg_seof_int_edge_w : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_15 : 13; /* [15: 3], rsvd, 0x0 */ - uint32_t sts_drain_int_r : 4; /* [19:16], r, 0x0 */ - uint32_t sts_seof_int_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_int_sts; - - /* 0xFC : osd_misc */ - union { - struct { - uint32_t reg_bus_strt_w : 1; /* [ 0], w1p, 0x0 */ - uint32_t reg_fifo_auto_clr_w : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_3 : 2; /* [ 3: 2], rsvd, 0x0 */ - uint32_t reg_qos_sw_mode_w : 1; /* [ 4], r/w, 0x0 */ - uint32_t reg_qos_sw_w : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t reg_ostd_max_w : 2; /* [ 9: 8], r/w, 0x3 */ - uint32_t reserved_10_11 : 2; /* [11:10], rsvd, 0x0 */ - uint32_t reg_xlen_w : 3; /* [14:12], r/w, 0x4 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t sts_l0_cmd_idle_r : 1; /* [ 16], r, 0x0 */ - uint32_t sts_l1_cmd_idle_r : 1; /* [ 17], r, 0x0 */ - uint32_t sts_l2_cmd_idle_r : 1; /* [ 18], r, 0x0 */ - uint32_t sts_l3_cmd_idle_r : 1; /* [ 19], r, 0x0 */ - uint32_t sts_axi_idle_r : 1; /* [ 20], r, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t reg_pclk_force_on_w : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } osd_misc; -}; - -typedef volatile struct osd_draw_reg osd_draw_reg_t; - -#endif /* __OSD_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_pb_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_pb_reg.h deleted file mode 100644 index 0ab8b710d0..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_pb_reg.h +++ /dev/null @@ -1,878 +0,0 @@ -/** - ****************************************************************************** - * @file osd_pb_reg.h - * @version V1.0 - * @date 2021-06-28 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_PB_REG_H__ -#define __OSD_PB_REG_H__ - -#include "bl808.h" - -/* 0x000 : osd_pb_ctrl_reg */ -#define OSD_PB_CTRL_REG_OFFSET (0x000) -#define OSD_PB_REG_OSD_PB_LUMA_TH OSD_PB_REG_OSD_PB_LUMA_TH -#define OSD_PB_REG_OSD_PB_LUMA_TH_POS (0U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_LEN (8U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_MSK (((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS) -#define OSD_PB_REG_OSD_PB_LUMA_TH_UMSK (~(((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS)) -#define OSD_PB_STS_OSD_PB_W_CNT_R OSD_PB_STS_OSD_PB_W_CNT_R -#define OSD_PB_STS_OSD_PB_W_CNT_R_POS (8U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_LEN (5U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_MSK (((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS) -#define OSD_PB_STS_OSD_PB_W_CNT_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS)) -#define OSD_PB_STS_OSD_PB_IDX_R OSD_PB_STS_OSD_PB_IDX_R -#define OSD_PB_STS_OSD_PB_IDX_R_POS (15U) -#define OSD_PB_STS_OSD_PB_IDX_R_LEN (1U) -#define OSD_PB_STS_OSD_PB_IDX_R_MSK (((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS) -#define OSD_PB_STS_OSD_PB_IDX_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS)) - -/* 0x004 : osd_pb_result0 */ -#define OSD_PB_RESULT0_OFFSET (0x004) -#define OSD_PB_STS_OSD_PB_RESULT_0_R OSD_PB_STS_OSD_PB_RESULT_0_R -#define OSD_PB_STS_OSD_PB_RESULT_0_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS)) - -/* 0x008 : osd_pb_result1 */ -#define OSD_PB_RESULT1_OFFSET (0x008) -#define OSD_PB_STS_OSD_PB_RESULT_1_R OSD_PB_STS_OSD_PB_RESULT_1_R -#define OSD_PB_STS_OSD_PB_RESULT_1_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS)) - -/* 0x010 : osd_pb_addr_00 */ -#define OSD_PB_ADDR_00_OFFSET (0x010) -#define OSD_PB_REG_OSD_PB_X_00 OSD_PB_REG_OSD_PB_X_00 -#define OSD_PB_REG_OSD_PB_X_00_POS (0U) -#define OSD_PB_REG_OSD_PB_X_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_00_MSK (((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS) -#define OSD_PB_REG_OSD_PB_X_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS)) -#define OSD_PB_REG_OSD_PB_Y_00 OSD_PB_REG_OSD_PB_Y_00 -#define OSD_PB_REG_OSD_PB_Y_00_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_00_MSK (((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS) -#define OSD_PB_REG_OSD_PB_Y_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS)) - -/* 0x014 : osd_pb_addr_01 */ -#define OSD_PB_ADDR_01_OFFSET (0x014) -#define OSD_PB_REG_OSD_PB_X_01 OSD_PB_REG_OSD_PB_X_01 -#define OSD_PB_REG_OSD_PB_X_01_POS (0U) -#define OSD_PB_REG_OSD_PB_X_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_01_MSK (((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS) -#define OSD_PB_REG_OSD_PB_X_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS)) -#define OSD_PB_REG_OSD_PB_Y_01 OSD_PB_REG_OSD_PB_Y_01 -#define OSD_PB_REG_OSD_PB_Y_01_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_01_MSK (((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS) -#define OSD_PB_REG_OSD_PB_Y_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS)) - -/* 0x018 : osd_pb_addr_02 */ -#define OSD_PB_ADDR_02_OFFSET (0x018) -#define OSD_PB_REG_OSD_PB_X_02 OSD_PB_REG_OSD_PB_X_02 -#define OSD_PB_REG_OSD_PB_X_02_POS (0U) -#define OSD_PB_REG_OSD_PB_X_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_02_MSK (((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS) -#define OSD_PB_REG_OSD_PB_X_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS)) -#define OSD_PB_REG_OSD_PB_Y_02 OSD_PB_REG_OSD_PB_Y_02 -#define OSD_PB_REG_OSD_PB_Y_02_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_02_MSK (((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS) -#define OSD_PB_REG_OSD_PB_Y_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS)) - -/* 0x01C : osd_pb_addr_03 */ -#define OSD_PB_ADDR_03_OFFSET (0x01C) -#define OSD_PB_REG_OSD_PB_X_03 OSD_PB_REG_OSD_PB_X_03 -#define OSD_PB_REG_OSD_PB_X_03_POS (0U) -#define OSD_PB_REG_OSD_PB_X_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_03_MSK (((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS) -#define OSD_PB_REG_OSD_PB_X_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS)) -#define OSD_PB_REG_OSD_PB_Y_03 OSD_PB_REG_OSD_PB_Y_03 -#define OSD_PB_REG_OSD_PB_Y_03_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_03_MSK (((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS) -#define OSD_PB_REG_OSD_PB_Y_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS)) - -/* 0x020 : osd_pb_addr_04 */ -#define OSD_PB_ADDR_04_OFFSET (0x020) -#define OSD_PB_REG_OSD_PB_X_04 OSD_PB_REG_OSD_PB_X_04 -#define OSD_PB_REG_OSD_PB_X_04_POS (0U) -#define OSD_PB_REG_OSD_PB_X_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_04_MSK (((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS) -#define OSD_PB_REG_OSD_PB_X_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS)) -#define OSD_PB_REG_OSD_PB_Y_04 OSD_PB_REG_OSD_PB_Y_04 -#define OSD_PB_REG_OSD_PB_Y_04_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_04_MSK (((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS) -#define OSD_PB_REG_OSD_PB_Y_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS)) - -/* 0x024 : osd_pb_addr_05 */ -#define OSD_PB_ADDR_05_OFFSET (0x024) -#define OSD_PB_REG_OSD_PB_X_05 OSD_PB_REG_OSD_PB_X_05 -#define OSD_PB_REG_OSD_PB_X_05_POS (0U) -#define OSD_PB_REG_OSD_PB_X_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_05_MSK (((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS) -#define OSD_PB_REG_OSD_PB_X_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS)) -#define OSD_PB_REG_OSD_PB_Y_05 OSD_PB_REG_OSD_PB_Y_05 -#define OSD_PB_REG_OSD_PB_Y_05_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_05_MSK (((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS) -#define OSD_PB_REG_OSD_PB_Y_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS)) - -/* 0x028 : osd_pb_addr_06 */ -#define OSD_PB_ADDR_06_OFFSET (0x028) -#define OSD_PB_REG_OSD_PB_X_06 OSD_PB_REG_OSD_PB_X_06 -#define OSD_PB_REG_OSD_PB_X_06_POS (0U) -#define OSD_PB_REG_OSD_PB_X_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_06_MSK (((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS) -#define OSD_PB_REG_OSD_PB_X_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS)) -#define OSD_PB_REG_OSD_PB_Y_06 OSD_PB_REG_OSD_PB_Y_06 -#define OSD_PB_REG_OSD_PB_Y_06_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_06_MSK (((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS) -#define OSD_PB_REG_OSD_PB_Y_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS)) - -/* 0x02C : osd_pb_addr_07 */ -#define OSD_PB_ADDR_07_OFFSET (0x02C) -#define OSD_PB_REG_OSD_PB_X_07 OSD_PB_REG_OSD_PB_X_07 -#define OSD_PB_REG_OSD_PB_X_07_POS (0U) -#define OSD_PB_REG_OSD_PB_X_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_07_MSK (((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS) -#define OSD_PB_REG_OSD_PB_X_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS)) -#define OSD_PB_REG_OSD_PB_Y_07 OSD_PB_REG_OSD_PB_Y_07 -#define OSD_PB_REG_OSD_PB_Y_07_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_07_MSK (((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS) -#define OSD_PB_REG_OSD_PB_Y_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS)) - -/* 0x030 : osd_pb_addr_08 */ -#define OSD_PB_ADDR_08_OFFSET (0x030) -#define OSD_PB_REG_OSD_PB_X_08 OSD_PB_REG_OSD_PB_X_08 -#define OSD_PB_REG_OSD_PB_X_08_POS (0U) -#define OSD_PB_REG_OSD_PB_X_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_08_MSK (((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS) -#define OSD_PB_REG_OSD_PB_X_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS)) -#define OSD_PB_REG_OSD_PB_Y_08 OSD_PB_REG_OSD_PB_Y_08 -#define OSD_PB_REG_OSD_PB_Y_08_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_08_MSK (((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS) -#define OSD_PB_REG_OSD_PB_Y_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS)) - -/* 0x034 : osd_pb_addr_09 */ -#define OSD_PB_ADDR_09_OFFSET (0x034) -#define OSD_PB_REG_OSD_PB_X_09 OSD_PB_REG_OSD_PB_X_09 -#define OSD_PB_REG_OSD_PB_X_09_POS (0U) -#define OSD_PB_REG_OSD_PB_X_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_09_MSK (((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS) -#define OSD_PB_REG_OSD_PB_X_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS)) -#define OSD_PB_REG_OSD_PB_Y_09 OSD_PB_REG_OSD_PB_Y_09 -#define OSD_PB_REG_OSD_PB_Y_09_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_09_MSK (((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS) -#define OSD_PB_REG_OSD_PB_Y_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS)) - -/* 0x038 : osd_pb_addr_0a */ -#define OSD_PB_ADDR_0A_OFFSET (0x038) -#define OSD_PB_REG_OSD_PB_X_0A OSD_PB_REG_OSD_PB_X_0A -#define OSD_PB_REG_OSD_PB_X_0A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0A_MSK (((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS) -#define OSD_PB_REG_OSD_PB_X_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS)) -#define OSD_PB_REG_OSD_PB_Y_0A OSD_PB_REG_OSD_PB_Y_0A -#define OSD_PB_REG_OSD_PB_Y_0A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS) -#define OSD_PB_REG_OSD_PB_Y_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS)) - -/* 0x03C : osd_pb_addr_0b */ -#define OSD_PB_ADDR_0B_OFFSET (0x03C) -#define OSD_PB_REG_OSD_PB_X_0B OSD_PB_REG_OSD_PB_X_0B -#define OSD_PB_REG_OSD_PB_X_0B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0B_MSK (((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS) -#define OSD_PB_REG_OSD_PB_X_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS)) -#define OSD_PB_REG_OSD_PB_Y_0B OSD_PB_REG_OSD_PB_Y_0B -#define OSD_PB_REG_OSD_PB_Y_0B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS) -#define OSD_PB_REG_OSD_PB_Y_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS)) - -/* 0x040 : osd_pb_addr_0c */ -#define OSD_PB_ADDR_0C_OFFSET (0x040) -#define OSD_PB_REG_OSD_PB_X_0C OSD_PB_REG_OSD_PB_X_0C -#define OSD_PB_REG_OSD_PB_X_0C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0C_MSK (((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS) -#define OSD_PB_REG_OSD_PB_X_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS)) -#define OSD_PB_REG_OSD_PB_Y_0C OSD_PB_REG_OSD_PB_Y_0C -#define OSD_PB_REG_OSD_PB_Y_0C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS) -#define OSD_PB_REG_OSD_PB_Y_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS)) - -/* 0x044 : osd_pb_addr_0d */ -#define OSD_PB_ADDR_0D_OFFSET (0x044) -#define OSD_PB_REG_OSD_PB_X_0D OSD_PB_REG_OSD_PB_X_0D -#define OSD_PB_REG_OSD_PB_X_0D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0D_MSK (((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS) -#define OSD_PB_REG_OSD_PB_X_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS)) -#define OSD_PB_REG_OSD_PB_Y_0D OSD_PB_REG_OSD_PB_Y_0D -#define OSD_PB_REG_OSD_PB_Y_0D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS) -#define OSD_PB_REG_OSD_PB_Y_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS)) - -/* 0x048 : osd_pb_addr_0e */ -#define OSD_PB_ADDR_0E_OFFSET (0x048) -#define OSD_PB_REG_OSD_PB_X_0E OSD_PB_REG_OSD_PB_X_0E -#define OSD_PB_REG_OSD_PB_X_0E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0E_MSK (((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS) -#define OSD_PB_REG_OSD_PB_X_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS)) -#define OSD_PB_REG_OSD_PB_Y_0E OSD_PB_REG_OSD_PB_Y_0E -#define OSD_PB_REG_OSD_PB_Y_0E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS) -#define OSD_PB_REG_OSD_PB_Y_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS)) - -/* 0x04C : osd_pb_addr_0f */ -#define OSD_PB_ADDR_0F_OFFSET (0x04C) -#define OSD_PB_REG_OSD_PB_X_0F OSD_PB_REG_OSD_PB_X_0F -#define OSD_PB_REG_OSD_PB_X_0F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0F_MSK (((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS) -#define OSD_PB_REG_OSD_PB_X_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS)) -#define OSD_PB_REG_OSD_PB_Y_0F OSD_PB_REG_OSD_PB_Y_0F -#define OSD_PB_REG_OSD_PB_Y_0F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS) -#define OSD_PB_REG_OSD_PB_Y_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS)) - -/* 0x050 : osd_pb_addr_10 */ -#define OSD_PB_ADDR_10_OFFSET (0x050) -#define OSD_PB_REG_OSD_PB_X_10 OSD_PB_REG_OSD_PB_X_10 -#define OSD_PB_REG_OSD_PB_X_10_POS (0U) -#define OSD_PB_REG_OSD_PB_X_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_10_MSK (((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS) -#define OSD_PB_REG_OSD_PB_X_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS)) -#define OSD_PB_REG_OSD_PB_Y_10 OSD_PB_REG_OSD_PB_Y_10 -#define OSD_PB_REG_OSD_PB_Y_10_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_10_MSK (((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS) -#define OSD_PB_REG_OSD_PB_Y_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS)) - -/* 0x054 : osd_pb_addr_11 */ -#define OSD_PB_ADDR_11_OFFSET (0x054) -#define OSD_PB_REG_OSD_PB_X_11 OSD_PB_REG_OSD_PB_X_11 -#define OSD_PB_REG_OSD_PB_X_11_POS (0U) -#define OSD_PB_REG_OSD_PB_X_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_11_MSK (((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS) -#define OSD_PB_REG_OSD_PB_X_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS)) -#define OSD_PB_REG_OSD_PB_Y_11 OSD_PB_REG_OSD_PB_Y_11 -#define OSD_PB_REG_OSD_PB_Y_11_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_11_MSK (((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS) -#define OSD_PB_REG_OSD_PB_Y_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS)) - -/* 0x058 : osd_pb_addr_12 */ -#define OSD_PB_ADDR_12_OFFSET (0x058) -#define OSD_PB_REG_OSD_PB_X_12 OSD_PB_REG_OSD_PB_X_12 -#define OSD_PB_REG_OSD_PB_X_12_POS (0U) -#define OSD_PB_REG_OSD_PB_X_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_12_MSK (((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS) -#define OSD_PB_REG_OSD_PB_X_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS)) -#define OSD_PB_REG_OSD_PB_Y_12 OSD_PB_REG_OSD_PB_Y_12 -#define OSD_PB_REG_OSD_PB_Y_12_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_12_MSK (((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS) -#define OSD_PB_REG_OSD_PB_Y_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS)) - -/* 0x05C : osd_pb_addr_13 */ -#define OSD_PB_ADDR_13_OFFSET (0x05C) -#define OSD_PB_REG_OSD_PB_X_13 OSD_PB_REG_OSD_PB_X_13 -#define OSD_PB_REG_OSD_PB_X_13_POS (0U) -#define OSD_PB_REG_OSD_PB_X_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_13_MSK (((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS) -#define OSD_PB_REG_OSD_PB_X_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS)) -#define OSD_PB_REG_OSD_PB_Y_13 OSD_PB_REG_OSD_PB_Y_13 -#define OSD_PB_REG_OSD_PB_Y_13_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_13_MSK (((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS) -#define OSD_PB_REG_OSD_PB_Y_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS)) - -/* 0x060 : osd_pb_addr_14 */ -#define OSD_PB_ADDR_14_OFFSET (0x060) -#define OSD_PB_REG_OSD_PB_X_14 OSD_PB_REG_OSD_PB_X_14 -#define OSD_PB_REG_OSD_PB_X_14_POS (0U) -#define OSD_PB_REG_OSD_PB_X_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_14_MSK (((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS) -#define OSD_PB_REG_OSD_PB_X_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS)) -#define OSD_PB_REG_OSD_PB_Y_14 OSD_PB_REG_OSD_PB_Y_14 -#define OSD_PB_REG_OSD_PB_Y_14_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_14_MSK (((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS) -#define OSD_PB_REG_OSD_PB_Y_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS)) - -/* 0x064 : osd_pb_addr_15 */ -#define OSD_PB_ADDR_15_OFFSET (0x064) -#define OSD_PB_REG_OSD_PB_X_15 OSD_PB_REG_OSD_PB_X_15 -#define OSD_PB_REG_OSD_PB_X_15_POS (0U) -#define OSD_PB_REG_OSD_PB_X_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_15_MSK (((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS) -#define OSD_PB_REG_OSD_PB_X_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS)) -#define OSD_PB_REG_OSD_PB_Y_15 OSD_PB_REG_OSD_PB_Y_15 -#define OSD_PB_REG_OSD_PB_Y_15_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_15_MSK (((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS) -#define OSD_PB_REG_OSD_PB_Y_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS)) - -/* 0x068 : osd_pb_addr_16 */ -#define OSD_PB_ADDR_16_OFFSET (0x068) -#define OSD_PB_REG_OSD_PB_X_16 OSD_PB_REG_OSD_PB_X_16 -#define OSD_PB_REG_OSD_PB_X_16_POS (0U) -#define OSD_PB_REG_OSD_PB_X_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_16_MSK (((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS) -#define OSD_PB_REG_OSD_PB_X_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS)) -#define OSD_PB_REG_OSD_PB_Y_16 OSD_PB_REG_OSD_PB_Y_16 -#define OSD_PB_REG_OSD_PB_Y_16_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_16_MSK (((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS) -#define OSD_PB_REG_OSD_PB_Y_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS)) - -/* 0x06C : osd_pb_addr_17 */ -#define OSD_PB_ADDR_17_OFFSET (0x06C) -#define OSD_PB_REG_OSD_PB_X_17 OSD_PB_REG_OSD_PB_X_17 -#define OSD_PB_REG_OSD_PB_X_17_POS (0U) -#define OSD_PB_REG_OSD_PB_X_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_17_MSK (((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS) -#define OSD_PB_REG_OSD_PB_X_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS)) -#define OSD_PB_REG_OSD_PB_Y_17 OSD_PB_REG_OSD_PB_Y_17 -#define OSD_PB_REG_OSD_PB_Y_17_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_17_MSK (((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS) -#define OSD_PB_REG_OSD_PB_Y_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS)) - -/* 0x070 : osd_pb_addr_18 */ -#define OSD_PB_ADDR_18_OFFSET (0x070) -#define OSD_PB_REG_OSD_PB_X_18 OSD_PB_REG_OSD_PB_X_18 -#define OSD_PB_REG_OSD_PB_X_18_POS (0U) -#define OSD_PB_REG_OSD_PB_X_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_18_MSK (((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS) -#define OSD_PB_REG_OSD_PB_X_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS)) -#define OSD_PB_REG_OSD_PB_Y_18 OSD_PB_REG_OSD_PB_Y_18 -#define OSD_PB_REG_OSD_PB_Y_18_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_18_MSK (((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS) -#define OSD_PB_REG_OSD_PB_Y_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS)) - -/* 0x074 : osd_pb_addr_19 */ -#define OSD_PB_ADDR_19_OFFSET (0x074) -#define OSD_PB_REG_OSD_PB_X_19 OSD_PB_REG_OSD_PB_X_19 -#define OSD_PB_REG_OSD_PB_X_19_POS (0U) -#define OSD_PB_REG_OSD_PB_X_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_19_MSK (((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS) -#define OSD_PB_REG_OSD_PB_X_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS)) -#define OSD_PB_REG_OSD_PB_Y_19 OSD_PB_REG_OSD_PB_Y_19 -#define OSD_PB_REG_OSD_PB_Y_19_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_19_MSK (((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS) -#define OSD_PB_REG_OSD_PB_Y_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS)) - -/* 0x078 : osd_pb_addr_1a */ -#define OSD_PB_ADDR_1A_OFFSET (0x078) -#define OSD_PB_REG_OSD_PB_X_1A OSD_PB_REG_OSD_PB_X_1A -#define OSD_PB_REG_OSD_PB_X_1A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1A_MSK (((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS) -#define OSD_PB_REG_OSD_PB_X_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS)) -#define OSD_PB_REG_OSD_PB_Y_1A OSD_PB_REG_OSD_PB_Y_1A -#define OSD_PB_REG_OSD_PB_Y_1A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS) -#define OSD_PB_REG_OSD_PB_Y_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS)) - -/* 0x07C : osd_pb_addr_1b */ -#define OSD_PB_ADDR_1B_OFFSET (0x07C) -#define OSD_PB_REG_OSD_PB_X_1B OSD_PB_REG_OSD_PB_X_1B -#define OSD_PB_REG_OSD_PB_X_1B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1B_MSK (((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS) -#define OSD_PB_REG_OSD_PB_X_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS)) -#define OSD_PB_REG_OSD_PB_Y_1B OSD_PB_REG_OSD_PB_Y_1B -#define OSD_PB_REG_OSD_PB_Y_1B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS) -#define OSD_PB_REG_OSD_PB_Y_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS)) - -/* 0x080 : osd_pb_addr_1c */ -#define OSD_PB_ADDR_1C_OFFSET (0x080) -#define OSD_PB_REG_OSD_PB_X_1C OSD_PB_REG_OSD_PB_X_1C -#define OSD_PB_REG_OSD_PB_X_1C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1C_MSK (((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS) -#define OSD_PB_REG_OSD_PB_X_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS)) -#define OSD_PB_REG_OSD_PB_Y_1C OSD_PB_REG_OSD_PB_Y_1C -#define OSD_PB_REG_OSD_PB_Y_1C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS) -#define OSD_PB_REG_OSD_PB_Y_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS)) - -/* 0x084 : osd_pb_addr_1d */ -#define OSD_PB_ADDR_1D_OFFSET (0x084) -#define OSD_PB_REG_OSD_PB_X_1D OSD_PB_REG_OSD_PB_X_1D -#define OSD_PB_REG_OSD_PB_X_1D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1D_MSK (((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS) -#define OSD_PB_REG_OSD_PB_X_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS)) -#define OSD_PB_REG_OSD_PB_Y_1D OSD_PB_REG_OSD_PB_Y_1D -#define OSD_PB_REG_OSD_PB_Y_1D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS) -#define OSD_PB_REG_OSD_PB_Y_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS)) - -/* 0x088 : osd_pb_addr_1e */ -#define OSD_PB_ADDR_1E_OFFSET (0x088) -#define OSD_PB_REG_OSD_PB_X_1E OSD_PB_REG_OSD_PB_X_1E -#define OSD_PB_REG_OSD_PB_X_1E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1E_MSK (((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS) -#define OSD_PB_REG_OSD_PB_X_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS)) -#define OSD_PB_REG_OSD_PB_Y_1E OSD_PB_REG_OSD_PB_Y_1E -#define OSD_PB_REG_OSD_PB_Y_1E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS) -#define OSD_PB_REG_OSD_PB_Y_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS)) - -/* 0x08C : osd_pb_addr_1f */ -#define OSD_PB_ADDR_1F_OFFSET (0x08C) -#define OSD_PB_REG_OSD_PB_X_1F OSD_PB_REG_OSD_PB_X_1F -#define OSD_PB_REG_OSD_PB_X_1F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1F_MSK (((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS) -#define OSD_PB_REG_OSD_PB_X_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS)) -#define OSD_PB_REG_OSD_PB_Y_1F OSD_PB_REG_OSD_PB_Y_1F -#define OSD_PB_REG_OSD_PB_Y_1F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS) -#define OSD_PB_REG_OSD_PB_Y_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS)) - -struct osd_pb_reg { - /* 0x000 : osd_pb_ctrl_reg */ - union { - struct { - uint32_t reg_osd_pb_luma_th : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t sts_osd_pb_w_cnt_r : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_14 : 2; /* [14:13], rsvd, 0x0 */ - uint32_t sts_osd_pb_idx_r : 1; /* [ 15], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_ctrl_reg; - - /* 0x004 : osd_pb_result0 */ - union { - struct { - uint32_t sts_osd_pb_result_0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result0; - - /* 0x008 : osd_pb_result1 */ - union { - struct { - uint32_t sts_osd_pb_result_1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result1; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x010 : osd_pb_addr_00 */ - union { - struct { - uint32_t reg_osd_pb_x_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_00; - - /* 0x014 : osd_pb_addr_01 */ - union { - struct { - uint32_t reg_osd_pb_x_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_01; - - /* 0x018 : osd_pb_addr_02 */ - union { - struct { - uint32_t reg_osd_pb_x_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_02; - - /* 0x01C : osd_pb_addr_03 */ - union { - struct { - uint32_t reg_osd_pb_x_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_03; - - /* 0x020 : osd_pb_addr_04 */ - union { - struct { - uint32_t reg_osd_pb_x_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_04; - - /* 0x024 : osd_pb_addr_05 */ - union { - struct { - uint32_t reg_osd_pb_x_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_05; - - /* 0x028 : osd_pb_addr_06 */ - union { - struct { - uint32_t reg_osd_pb_x_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_06; - - /* 0x02C : osd_pb_addr_07 */ - union { - struct { - uint32_t reg_osd_pb_x_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_07; - - /* 0x030 : osd_pb_addr_08 */ - union { - struct { - uint32_t reg_osd_pb_x_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_08; - - /* 0x034 : osd_pb_addr_09 */ - union { - struct { - uint32_t reg_osd_pb_x_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_09; - - /* 0x038 : osd_pb_addr_0a */ - union { - struct { - uint32_t reg_osd_pb_x_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0a; - - /* 0x03C : osd_pb_addr_0b */ - union { - struct { - uint32_t reg_osd_pb_x_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0b; - - /* 0x040 : osd_pb_addr_0c */ - union { - struct { - uint32_t reg_osd_pb_x_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0c; - - /* 0x044 : osd_pb_addr_0d */ - union { - struct { - uint32_t reg_osd_pb_x_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0d; - - /* 0x048 : osd_pb_addr_0e */ - union { - struct { - uint32_t reg_osd_pb_x_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0e; - - /* 0x04C : osd_pb_addr_0f */ - union { - struct { - uint32_t reg_osd_pb_x_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0f; - - /* 0x050 : osd_pb_addr_10 */ - union { - struct { - uint32_t reg_osd_pb_x_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_10; - - /* 0x054 : osd_pb_addr_11 */ - union { - struct { - uint32_t reg_osd_pb_x_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_11; - - /* 0x058 : osd_pb_addr_12 */ - union { - struct { - uint32_t reg_osd_pb_x_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_12; - - /* 0x05C : osd_pb_addr_13 */ - union { - struct { - uint32_t reg_osd_pb_x_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_13; - - /* 0x060 : osd_pb_addr_14 */ - union { - struct { - uint32_t reg_osd_pb_x_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_14; - - /* 0x064 : osd_pb_addr_15 */ - union { - struct { - uint32_t reg_osd_pb_x_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_15; - - /* 0x068 : osd_pb_addr_16 */ - union { - struct { - uint32_t reg_osd_pb_x_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_16; - - /* 0x06C : osd_pb_addr_17 */ - union { - struct { - uint32_t reg_osd_pb_x_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_17; - - /* 0x070 : osd_pb_addr_18 */ - union { - struct { - uint32_t reg_osd_pb_x_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_18; - - /* 0x074 : osd_pb_addr_19 */ - union { - struct { - uint32_t reg_osd_pb_x_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_19; - - /* 0x078 : osd_pb_addr_1a */ - union { - struct { - uint32_t reg_osd_pb_x_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1a; - - /* 0x07C : osd_pb_addr_1b */ - union { - struct { - uint32_t reg_osd_pb_x_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1b; - - /* 0x080 : osd_pb_addr_1c */ - union { - struct { - uint32_t reg_osd_pb_x_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1c; - - /* 0x084 : osd_pb_addr_1d */ - union { - struct { - uint32_t reg_osd_pb_x_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1d; - - /* 0x088 : osd_pb_addr_1e */ - union { - struct { - uint32_t reg_osd_pb_x_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1e; - - /* 0x08C : osd_pb_addr_1f */ - union { - struct { - uint32_t reg_osd_pb_x_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1f; -}; - -typedef volatile struct osd_pb_reg osd_pb_reg_t; - -#endif /* __OSD_PB_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_probe_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_probe_reg.h deleted file mode 100644 index e9db19a3fc..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/osd_probe_reg.h +++ /dev/null @@ -1,913 +0,0 @@ -/** - ****************************************************************************** - * @file osd_probe_reg.h - * @version V1.0 - * @date 2021-03-30 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __OSD_PROBE_REG_H__ -#define __OSD_PROBE_REG_H__ - -#include "bl808.h" - -/* 0x000 : osd_pb_ctrl_reg */ -#define OSD_PB_CTRL_REG_OFFSET (0x000) -#define OSD_PB_REG_OSD_PB_LUMA_TH OSD_PB_REG_OSD_PB_LUMA_TH -#define OSD_PB_REG_OSD_PB_LUMA_TH_POS (0U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_LEN (8U) -#define OSD_PB_REG_OSD_PB_LUMA_TH_MSK (((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS) -#define OSD_PB_REG_OSD_PB_LUMA_TH_UMSK (~(((1U << OSD_PB_REG_OSD_PB_LUMA_TH_LEN) - 1) << OSD_PB_REG_OSD_PB_LUMA_TH_POS)) -#define OSD_PB_STS_OSD_PB_W_CNT_R OSD_PB_STS_OSD_PB_W_CNT_R -#define OSD_PB_STS_OSD_PB_W_CNT_R_POS (8U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_LEN (5U) -#define OSD_PB_STS_OSD_PB_W_CNT_R_MSK (((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS) -#define OSD_PB_STS_OSD_PB_W_CNT_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_W_CNT_R_LEN) - 1) << OSD_PB_STS_OSD_PB_W_CNT_R_POS)) -#define OSD_PB_STS_OSD_PB_IDX_R OSD_PB_STS_OSD_PB_IDX_R -#define OSD_PB_STS_OSD_PB_IDX_R_POS (15U) -#define OSD_PB_STS_OSD_PB_IDX_R_LEN (1U) -#define OSD_PB_STS_OSD_PB_IDX_R_MSK (((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS) -#define OSD_PB_STS_OSD_PB_IDX_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_IDX_R_LEN) - 1) << OSD_PB_STS_OSD_PB_IDX_R_POS)) - -/* 0x004 : osd_pb_result0 */ -#define OSD_PB_RESULT0_OFFSET (0x004) -#define OSD_PB_STS_OSD_PB_RESULT_0_R OSD_PB_STS_OSD_PB_RESULT_0_R -#define OSD_PB_STS_OSD_PB_RESULT_0_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_0_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_0_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_0_R_POS)) - -/* 0x008 : osd_pb_result1 */ -#define OSD_PB_RESULT1_OFFSET (0x008) -#define OSD_PB_STS_OSD_PB_RESULT_1_R OSD_PB_STS_OSD_PB_RESULT_1_R -#define OSD_PB_STS_OSD_PB_RESULT_1_R_POS (0U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_LEN (32U) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_MSK (((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS) -#define OSD_PB_STS_OSD_PB_RESULT_1_R_UMSK (~(((1U << OSD_PB_STS_OSD_PB_RESULT_1_R_LEN) - 1) << OSD_PB_STS_OSD_PB_RESULT_1_R_POS)) - -/* 0x010 : osd_pb_addr_00 */ -#define OSD_PB_ADDR_00_OFFSET (0x010) -#define OSD_PB_REG_OSD_PB_X_00 OSD_PB_REG_OSD_PB_X_00 -#define OSD_PB_REG_OSD_PB_X_00_POS (0U) -#define OSD_PB_REG_OSD_PB_X_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_00_MSK (((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS) -#define OSD_PB_REG_OSD_PB_X_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_00_LEN) - 1) << OSD_PB_REG_OSD_PB_X_00_POS)) -#define OSD_PB_REG_OSD_PB_Y_00 OSD_PB_REG_OSD_PB_Y_00 -#define OSD_PB_REG_OSD_PB_Y_00_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_00_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_00_MSK (((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS) -#define OSD_PB_REG_OSD_PB_Y_00_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_00_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_00_POS)) - -/* 0x014 : osd_pb_addr_01 */ -#define OSD_PB_ADDR_01_OFFSET (0x014) -#define OSD_PB_REG_OSD_PB_X_01 OSD_PB_REG_OSD_PB_X_01 -#define OSD_PB_REG_OSD_PB_X_01_POS (0U) -#define OSD_PB_REG_OSD_PB_X_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_01_MSK (((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS) -#define OSD_PB_REG_OSD_PB_X_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_01_LEN) - 1) << OSD_PB_REG_OSD_PB_X_01_POS)) -#define OSD_PB_REG_OSD_PB_Y_01 OSD_PB_REG_OSD_PB_Y_01 -#define OSD_PB_REG_OSD_PB_Y_01_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_01_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_01_MSK (((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS) -#define OSD_PB_REG_OSD_PB_Y_01_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_01_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_01_POS)) - -/* 0x018 : osd_pb_addr_02 */ -#define OSD_PB_ADDR_02_OFFSET (0x018) -#define OSD_PB_REG_OSD_PB_X_02 OSD_PB_REG_OSD_PB_X_02 -#define OSD_PB_REG_OSD_PB_X_02_POS (0U) -#define OSD_PB_REG_OSD_PB_X_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_02_MSK (((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS) -#define OSD_PB_REG_OSD_PB_X_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_02_LEN) - 1) << OSD_PB_REG_OSD_PB_X_02_POS)) -#define OSD_PB_REG_OSD_PB_Y_02 OSD_PB_REG_OSD_PB_Y_02 -#define OSD_PB_REG_OSD_PB_Y_02_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_02_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_02_MSK (((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS) -#define OSD_PB_REG_OSD_PB_Y_02_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_02_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_02_POS)) - -/* 0x01C : osd_pb_addr_03 */ -#define OSD_PB_ADDR_03_OFFSET (0x01C) -#define OSD_PB_REG_OSD_PB_X_03 OSD_PB_REG_OSD_PB_X_03 -#define OSD_PB_REG_OSD_PB_X_03_POS (0U) -#define OSD_PB_REG_OSD_PB_X_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_03_MSK (((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS) -#define OSD_PB_REG_OSD_PB_X_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_03_LEN) - 1) << OSD_PB_REG_OSD_PB_X_03_POS)) -#define OSD_PB_REG_OSD_PB_Y_03 OSD_PB_REG_OSD_PB_Y_03 -#define OSD_PB_REG_OSD_PB_Y_03_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_03_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_03_MSK (((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS) -#define OSD_PB_REG_OSD_PB_Y_03_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_03_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_03_POS)) - -/* 0x020 : osd_pb_addr_04 */ -#define OSD_PB_ADDR_04_OFFSET (0x020) -#define OSD_PB_REG_OSD_PB_X_04 OSD_PB_REG_OSD_PB_X_04 -#define OSD_PB_REG_OSD_PB_X_04_POS (0U) -#define OSD_PB_REG_OSD_PB_X_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_04_MSK (((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS) -#define OSD_PB_REG_OSD_PB_X_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_04_LEN) - 1) << OSD_PB_REG_OSD_PB_X_04_POS)) -#define OSD_PB_REG_OSD_PB_Y_04 OSD_PB_REG_OSD_PB_Y_04 -#define OSD_PB_REG_OSD_PB_Y_04_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_04_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_04_MSK (((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS) -#define OSD_PB_REG_OSD_PB_Y_04_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_04_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_04_POS)) - -/* 0x024 : osd_pb_addr_05 */ -#define OSD_PB_ADDR_05_OFFSET (0x024) -#define OSD_PB_REG_OSD_PB_X_05 OSD_PB_REG_OSD_PB_X_05 -#define OSD_PB_REG_OSD_PB_X_05_POS (0U) -#define OSD_PB_REG_OSD_PB_X_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_05_MSK (((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS) -#define OSD_PB_REG_OSD_PB_X_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_05_LEN) - 1) << OSD_PB_REG_OSD_PB_X_05_POS)) -#define OSD_PB_REG_OSD_PB_Y_05 OSD_PB_REG_OSD_PB_Y_05 -#define OSD_PB_REG_OSD_PB_Y_05_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_05_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_05_MSK (((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS) -#define OSD_PB_REG_OSD_PB_Y_05_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_05_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_05_POS)) - -/* 0x028 : osd_pb_addr_06 */ -#define OSD_PB_ADDR_06_OFFSET (0x028) -#define OSD_PB_REG_OSD_PB_X_06 OSD_PB_REG_OSD_PB_X_06 -#define OSD_PB_REG_OSD_PB_X_06_POS (0U) -#define OSD_PB_REG_OSD_PB_X_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_06_MSK (((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS) -#define OSD_PB_REG_OSD_PB_X_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_06_LEN) - 1) << OSD_PB_REG_OSD_PB_X_06_POS)) -#define OSD_PB_REG_OSD_PB_Y_06 OSD_PB_REG_OSD_PB_Y_06 -#define OSD_PB_REG_OSD_PB_Y_06_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_06_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_06_MSK (((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS) -#define OSD_PB_REG_OSD_PB_Y_06_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_06_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_06_POS)) - -/* 0x02C : osd_pb_addr_07 */ -#define OSD_PB_ADDR_07_OFFSET (0x02C) -#define OSD_PB_REG_OSD_PB_X_07 OSD_PB_REG_OSD_PB_X_07 -#define OSD_PB_REG_OSD_PB_X_07_POS (0U) -#define OSD_PB_REG_OSD_PB_X_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_07_MSK (((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS) -#define OSD_PB_REG_OSD_PB_X_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_07_LEN) - 1) << OSD_PB_REG_OSD_PB_X_07_POS)) -#define OSD_PB_REG_OSD_PB_Y_07 OSD_PB_REG_OSD_PB_Y_07 -#define OSD_PB_REG_OSD_PB_Y_07_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_07_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_07_MSK (((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS) -#define OSD_PB_REG_OSD_PB_Y_07_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_07_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_07_POS)) - -/* 0x030 : osd_pb_addr_08 */ -#define OSD_PB_ADDR_08_OFFSET (0x030) -#define OSD_PB_REG_OSD_PB_X_08 OSD_PB_REG_OSD_PB_X_08 -#define OSD_PB_REG_OSD_PB_X_08_POS (0U) -#define OSD_PB_REG_OSD_PB_X_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_08_MSK (((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS) -#define OSD_PB_REG_OSD_PB_X_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_08_LEN) - 1) << OSD_PB_REG_OSD_PB_X_08_POS)) -#define OSD_PB_REG_OSD_PB_Y_08 OSD_PB_REG_OSD_PB_Y_08 -#define OSD_PB_REG_OSD_PB_Y_08_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_08_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_08_MSK (((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS) -#define OSD_PB_REG_OSD_PB_Y_08_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_08_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_08_POS)) - -/* 0x034 : osd_pb_addr_09 */ -#define OSD_PB_ADDR_09_OFFSET (0x034) -#define OSD_PB_REG_OSD_PB_X_09 OSD_PB_REG_OSD_PB_X_09 -#define OSD_PB_REG_OSD_PB_X_09_POS (0U) -#define OSD_PB_REG_OSD_PB_X_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_09_MSK (((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS) -#define OSD_PB_REG_OSD_PB_X_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_09_LEN) - 1) << OSD_PB_REG_OSD_PB_X_09_POS)) -#define OSD_PB_REG_OSD_PB_Y_09 OSD_PB_REG_OSD_PB_Y_09 -#define OSD_PB_REG_OSD_PB_Y_09_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_09_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_09_MSK (((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS) -#define OSD_PB_REG_OSD_PB_Y_09_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_09_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_09_POS)) - -/* 0x038 : osd_pb_addr_0a */ -#define OSD_PB_ADDR_0A_OFFSET (0x038) -#define OSD_PB_REG_OSD_PB_X_0A OSD_PB_REG_OSD_PB_X_0A -#define OSD_PB_REG_OSD_PB_X_0A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0A_MSK (((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS) -#define OSD_PB_REG_OSD_PB_X_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0A_POS)) -#define OSD_PB_REG_OSD_PB_Y_0A OSD_PB_REG_OSD_PB_Y_0A -#define OSD_PB_REG_OSD_PB_Y_0A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS) -#define OSD_PB_REG_OSD_PB_Y_0A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0A_POS)) - -/* 0x03C : osd_pb_addr_0b */ -#define OSD_PB_ADDR_0B_OFFSET (0x03C) -#define OSD_PB_REG_OSD_PB_X_0B OSD_PB_REG_OSD_PB_X_0B -#define OSD_PB_REG_OSD_PB_X_0B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0B_MSK (((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS) -#define OSD_PB_REG_OSD_PB_X_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0B_POS)) -#define OSD_PB_REG_OSD_PB_Y_0B OSD_PB_REG_OSD_PB_Y_0B -#define OSD_PB_REG_OSD_PB_Y_0B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS) -#define OSD_PB_REG_OSD_PB_Y_0B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0B_POS)) - -/* 0x040 : osd_pb_addr_0c */ -#define OSD_PB_ADDR_0C_OFFSET (0x040) -#define OSD_PB_REG_OSD_PB_X_0C OSD_PB_REG_OSD_PB_X_0C -#define OSD_PB_REG_OSD_PB_X_0C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0C_MSK (((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS) -#define OSD_PB_REG_OSD_PB_X_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0C_POS)) -#define OSD_PB_REG_OSD_PB_Y_0C OSD_PB_REG_OSD_PB_Y_0C -#define OSD_PB_REG_OSD_PB_Y_0C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS) -#define OSD_PB_REG_OSD_PB_Y_0C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0C_POS)) - -/* 0x044 : osd_pb_addr_0d */ -#define OSD_PB_ADDR_0D_OFFSET (0x044) -#define OSD_PB_REG_OSD_PB_X_0D OSD_PB_REG_OSD_PB_X_0D -#define OSD_PB_REG_OSD_PB_X_0D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0D_MSK (((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS) -#define OSD_PB_REG_OSD_PB_X_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0D_POS)) -#define OSD_PB_REG_OSD_PB_Y_0D OSD_PB_REG_OSD_PB_Y_0D -#define OSD_PB_REG_OSD_PB_Y_0D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS) -#define OSD_PB_REG_OSD_PB_Y_0D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0D_POS)) - -/* 0x048 : osd_pb_addr_0e */ -#define OSD_PB_ADDR_0E_OFFSET (0x048) -#define OSD_PB_REG_OSD_PB_X_0E OSD_PB_REG_OSD_PB_X_0E -#define OSD_PB_REG_OSD_PB_X_0E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0E_MSK (((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS) -#define OSD_PB_REG_OSD_PB_X_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0E_POS)) -#define OSD_PB_REG_OSD_PB_Y_0E OSD_PB_REG_OSD_PB_Y_0E -#define OSD_PB_REG_OSD_PB_Y_0E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS) -#define OSD_PB_REG_OSD_PB_Y_0E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0E_POS)) - -/* 0x04C : osd_pb_addr_0f */ -#define OSD_PB_ADDR_0F_OFFSET (0x04C) -#define OSD_PB_REG_OSD_PB_X_0F OSD_PB_REG_OSD_PB_X_0F -#define OSD_PB_REG_OSD_PB_X_0F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_0F_MSK (((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS) -#define OSD_PB_REG_OSD_PB_X_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_0F_POS)) -#define OSD_PB_REG_OSD_PB_Y_0F OSD_PB_REG_OSD_PB_Y_0F -#define OSD_PB_REG_OSD_PB_Y_0F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_0F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_0F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS) -#define OSD_PB_REG_OSD_PB_Y_0F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_0F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_0F_POS)) - -/* 0x050 : osd_pb_addr_10 */ -#define OSD_PB_ADDR_10_OFFSET (0x050) -#define OSD_PB_REG_OSD_PB_X_10 OSD_PB_REG_OSD_PB_X_10 -#define OSD_PB_REG_OSD_PB_X_10_POS (0U) -#define OSD_PB_REG_OSD_PB_X_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_10_MSK (((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS) -#define OSD_PB_REG_OSD_PB_X_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_10_LEN) - 1) << OSD_PB_REG_OSD_PB_X_10_POS)) -#define OSD_PB_REG_OSD_PB_Y_10 OSD_PB_REG_OSD_PB_Y_10 -#define OSD_PB_REG_OSD_PB_Y_10_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_10_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_10_MSK (((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS) -#define OSD_PB_REG_OSD_PB_Y_10_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_10_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_10_POS)) - -/* 0x054 : osd_pb_addr_11 */ -#define OSD_PB_ADDR_11_OFFSET (0x054) -#define OSD_PB_REG_OSD_PB_X_11 OSD_PB_REG_OSD_PB_X_11 -#define OSD_PB_REG_OSD_PB_X_11_POS (0U) -#define OSD_PB_REG_OSD_PB_X_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_11_MSK (((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS) -#define OSD_PB_REG_OSD_PB_X_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_11_LEN) - 1) << OSD_PB_REG_OSD_PB_X_11_POS)) -#define OSD_PB_REG_OSD_PB_Y_11 OSD_PB_REG_OSD_PB_Y_11 -#define OSD_PB_REG_OSD_PB_Y_11_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_11_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_11_MSK (((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS) -#define OSD_PB_REG_OSD_PB_Y_11_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_11_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_11_POS)) - -/* 0x058 : osd_pb_addr_12 */ -#define OSD_PB_ADDR_12_OFFSET (0x058) -#define OSD_PB_REG_OSD_PB_X_12 OSD_PB_REG_OSD_PB_X_12 -#define OSD_PB_REG_OSD_PB_X_12_POS (0U) -#define OSD_PB_REG_OSD_PB_X_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_12_MSK (((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS) -#define OSD_PB_REG_OSD_PB_X_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_12_LEN) - 1) << OSD_PB_REG_OSD_PB_X_12_POS)) -#define OSD_PB_REG_OSD_PB_Y_12 OSD_PB_REG_OSD_PB_Y_12 -#define OSD_PB_REG_OSD_PB_Y_12_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_12_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_12_MSK (((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS) -#define OSD_PB_REG_OSD_PB_Y_12_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_12_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_12_POS)) - -/* 0x05C : osd_pb_addr_13 */ -#define OSD_PB_ADDR_13_OFFSET (0x05C) -#define OSD_PB_REG_OSD_PB_X_13 OSD_PB_REG_OSD_PB_X_13 -#define OSD_PB_REG_OSD_PB_X_13_POS (0U) -#define OSD_PB_REG_OSD_PB_X_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_13_MSK (((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS) -#define OSD_PB_REG_OSD_PB_X_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_13_LEN) - 1) << OSD_PB_REG_OSD_PB_X_13_POS)) -#define OSD_PB_REG_OSD_PB_Y_13 OSD_PB_REG_OSD_PB_Y_13 -#define OSD_PB_REG_OSD_PB_Y_13_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_13_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_13_MSK (((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS) -#define OSD_PB_REG_OSD_PB_Y_13_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_13_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_13_POS)) - -/* 0x060 : osd_pb_addr_14 */ -#define OSD_PB_ADDR_14_OFFSET (0x060) -#define OSD_PB_REG_OSD_PB_X_14 OSD_PB_REG_OSD_PB_X_14 -#define OSD_PB_REG_OSD_PB_X_14_POS (0U) -#define OSD_PB_REG_OSD_PB_X_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_14_MSK (((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS) -#define OSD_PB_REG_OSD_PB_X_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_14_LEN) - 1) << OSD_PB_REG_OSD_PB_X_14_POS)) -#define OSD_PB_REG_OSD_PB_Y_14 OSD_PB_REG_OSD_PB_Y_14 -#define OSD_PB_REG_OSD_PB_Y_14_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_14_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_14_MSK (((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS) -#define OSD_PB_REG_OSD_PB_Y_14_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_14_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_14_POS)) - -/* 0x064 : osd_pb_addr_15 */ -#define OSD_PB_ADDR_15_OFFSET (0x064) -#define OSD_PB_REG_OSD_PB_X_15 OSD_PB_REG_OSD_PB_X_15 -#define OSD_PB_REG_OSD_PB_X_15_POS (0U) -#define OSD_PB_REG_OSD_PB_X_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_15_MSK (((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS) -#define OSD_PB_REG_OSD_PB_X_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_15_LEN) - 1) << OSD_PB_REG_OSD_PB_X_15_POS)) -#define OSD_PB_REG_OSD_PB_Y_15 OSD_PB_REG_OSD_PB_Y_15 -#define OSD_PB_REG_OSD_PB_Y_15_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_15_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_15_MSK (((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS) -#define OSD_PB_REG_OSD_PB_Y_15_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_15_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_15_POS)) - -/* 0x068 : osd_pb_addr_16 */ -#define OSD_PB_ADDR_16_OFFSET (0x068) -#define OSD_PB_REG_OSD_PB_X_16 OSD_PB_REG_OSD_PB_X_16 -#define OSD_PB_REG_OSD_PB_X_16_POS (0U) -#define OSD_PB_REG_OSD_PB_X_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_16_MSK (((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS) -#define OSD_PB_REG_OSD_PB_X_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_16_LEN) - 1) << OSD_PB_REG_OSD_PB_X_16_POS)) -#define OSD_PB_REG_OSD_PB_Y_16 OSD_PB_REG_OSD_PB_Y_16 -#define OSD_PB_REG_OSD_PB_Y_16_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_16_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_16_MSK (((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS) -#define OSD_PB_REG_OSD_PB_Y_16_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_16_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_16_POS)) - -/* 0x06C : osd_pb_addr_17 */ -#define OSD_PB_ADDR_17_OFFSET (0x06C) -#define OSD_PB_REG_OSD_PB_X_17 OSD_PB_REG_OSD_PB_X_17 -#define OSD_PB_REG_OSD_PB_X_17_POS (0U) -#define OSD_PB_REG_OSD_PB_X_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_17_MSK (((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS) -#define OSD_PB_REG_OSD_PB_X_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_17_LEN) - 1) << OSD_PB_REG_OSD_PB_X_17_POS)) -#define OSD_PB_REG_OSD_PB_Y_17 OSD_PB_REG_OSD_PB_Y_17 -#define OSD_PB_REG_OSD_PB_Y_17_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_17_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_17_MSK (((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS) -#define OSD_PB_REG_OSD_PB_Y_17_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_17_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_17_POS)) - -/* 0x070 : osd_pb_addr_18 */ -#define OSD_PB_ADDR_18_OFFSET (0x070) -#define OSD_PB_REG_OSD_PB_X_18 OSD_PB_REG_OSD_PB_X_18 -#define OSD_PB_REG_OSD_PB_X_18_POS (0U) -#define OSD_PB_REG_OSD_PB_X_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_18_MSK (((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS) -#define OSD_PB_REG_OSD_PB_X_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_18_LEN) - 1) << OSD_PB_REG_OSD_PB_X_18_POS)) -#define OSD_PB_REG_OSD_PB_Y_18 OSD_PB_REG_OSD_PB_Y_18 -#define OSD_PB_REG_OSD_PB_Y_18_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_18_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_18_MSK (((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS) -#define OSD_PB_REG_OSD_PB_Y_18_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_18_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_18_POS)) - -/* 0x074 : osd_pb_addr_19 */ -#define OSD_PB_ADDR_19_OFFSET (0x074) -#define OSD_PB_REG_OSD_PB_X_19 OSD_PB_REG_OSD_PB_X_19 -#define OSD_PB_REG_OSD_PB_X_19_POS (0U) -#define OSD_PB_REG_OSD_PB_X_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_19_MSK (((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS) -#define OSD_PB_REG_OSD_PB_X_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_19_LEN) - 1) << OSD_PB_REG_OSD_PB_X_19_POS)) -#define OSD_PB_REG_OSD_PB_Y_19 OSD_PB_REG_OSD_PB_Y_19 -#define OSD_PB_REG_OSD_PB_Y_19_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_19_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_19_MSK (((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS) -#define OSD_PB_REG_OSD_PB_Y_19_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_19_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_19_POS)) - -/* 0x078 : osd_pb_addr_1a */ -#define OSD_PB_ADDR_1A_OFFSET (0x078) -#define OSD_PB_REG_OSD_PB_X_1A OSD_PB_REG_OSD_PB_X_1A -#define OSD_PB_REG_OSD_PB_X_1A_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1A_MSK (((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS) -#define OSD_PB_REG_OSD_PB_X_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1A_POS)) -#define OSD_PB_REG_OSD_PB_Y_1A OSD_PB_REG_OSD_PB_Y_1A -#define OSD_PB_REG_OSD_PB_Y_1A_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1A_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1A_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS) -#define OSD_PB_REG_OSD_PB_Y_1A_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1A_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1A_POS)) - -/* 0x07C : osd_pb_addr_1b */ -#define OSD_PB_ADDR_1B_OFFSET (0x07C) -#define OSD_PB_REG_OSD_PB_X_1B OSD_PB_REG_OSD_PB_X_1B -#define OSD_PB_REG_OSD_PB_X_1B_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1B_MSK (((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS) -#define OSD_PB_REG_OSD_PB_X_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1B_POS)) -#define OSD_PB_REG_OSD_PB_Y_1B OSD_PB_REG_OSD_PB_Y_1B -#define OSD_PB_REG_OSD_PB_Y_1B_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1B_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1B_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS) -#define OSD_PB_REG_OSD_PB_Y_1B_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1B_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1B_POS)) - -/* 0x080 : osd_pb_addr_1c */ -#define OSD_PB_ADDR_1C_OFFSET (0x080) -#define OSD_PB_REG_OSD_PB_X_1C OSD_PB_REG_OSD_PB_X_1C -#define OSD_PB_REG_OSD_PB_X_1C_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1C_MSK (((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS) -#define OSD_PB_REG_OSD_PB_X_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1C_POS)) -#define OSD_PB_REG_OSD_PB_Y_1C OSD_PB_REG_OSD_PB_Y_1C -#define OSD_PB_REG_OSD_PB_Y_1C_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1C_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1C_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS) -#define OSD_PB_REG_OSD_PB_Y_1C_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1C_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1C_POS)) - -/* 0x084 : osd_pb_addr_1d */ -#define OSD_PB_ADDR_1D_OFFSET (0x084) -#define OSD_PB_REG_OSD_PB_X_1D OSD_PB_REG_OSD_PB_X_1D -#define OSD_PB_REG_OSD_PB_X_1D_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1D_MSK (((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS) -#define OSD_PB_REG_OSD_PB_X_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1D_POS)) -#define OSD_PB_REG_OSD_PB_Y_1D OSD_PB_REG_OSD_PB_Y_1D -#define OSD_PB_REG_OSD_PB_Y_1D_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1D_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1D_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS) -#define OSD_PB_REG_OSD_PB_Y_1D_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1D_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1D_POS)) - -/* 0x088 : osd_pb_addr_1e */ -#define OSD_PB_ADDR_1E_OFFSET (0x088) -#define OSD_PB_REG_OSD_PB_X_1E OSD_PB_REG_OSD_PB_X_1E -#define OSD_PB_REG_OSD_PB_X_1E_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1E_MSK (((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS) -#define OSD_PB_REG_OSD_PB_X_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1E_POS)) -#define OSD_PB_REG_OSD_PB_Y_1E OSD_PB_REG_OSD_PB_Y_1E -#define OSD_PB_REG_OSD_PB_Y_1E_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1E_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1E_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS) -#define OSD_PB_REG_OSD_PB_Y_1E_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1E_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1E_POS)) - -/* 0x08C : osd_pb_addr_1f */ -#define OSD_PB_ADDR_1F_OFFSET (0x08C) -#define OSD_PB_REG_OSD_PB_X_1F OSD_PB_REG_OSD_PB_X_1F -#define OSD_PB_REG_OSD_PB_X_1F_POS (0U) -#define OSD_PB_REG_OSD_PB_X_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_X_1F_MSK (((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS) -#define OSD_PB_REG_OSD_PB_X_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_X_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_X_1F_POS)) -#define OSD_PB_REG_OSD_PB_Y_1F OSD_PB_REG_OSD_PB_Y_1F -#define OSD_PB_REG_OSD_PB_Y_1F_POS (16U) -#define OSD_PB_REG_OSD_PB_Y_1F_LEN (11U) -#define OSD_PB_REG_OSD_PB_Y_1F_MSK (((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS) -#define OSD_PB_REG_OSD_PB_Y_1F_UMSK (~(((1U << OSD_PB_REG_OSD_PB_Y_1F_LEN) - 1) << OSD_PB_REG_OSD_PB_Y_1F_POS)) - -struct osd_pb_reg { - /* 0x000 : osd_pb_ctrl_reg */ - union { - struct - { - uint32_t reg_osd_pb_luma_th : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t sts_osd_pb_w_cnt_r : 5; /* [12: 8], r, 0x0 */ - uint32_t reserved_13_14 : 2; /* [14:13], rsvd, 0x0 */ - uint32_t sts_osd_pb_idx_r : 1; /* [ 15], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_ctrl_reg; - - /* 0x004 : osd_pb_result0 */ - union { - struct - { - uint32_t sts_osd_pb_result_0_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result0; - - /* 0x008 : osd_pb_result1 */ - union { - struct - { - uint32_t sts_osd_pb_result_1_r : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_result1; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x010 : osd_pb_addr_00 */ - union { - struct - { - uint32_t reg_osd_pb_x_00 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_00 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_00; - - /* 0x014 : osd_pb_addr_01 */ - union { - struct - { - uint32_t reg_osd_pb_x_01 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_01 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_01; - - /* 0x018 : osd_pb_addr_02 */ - union { - struct - { - uint32_t reg_osd_pb_x_02 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_02 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_02; - - /* 0x01C : osd_pb_addr_03 */ - union { - struct - { - uint32_t reg_osd_pb_x_03 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_03 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_03; - - /* 0x020 : osd_pb_addr_04 */ - union { - struct - { - uint32_t reg_osd_pb_x_04 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_04 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_04; - - /* 0x024 : osd_pb_addr_05 */ - union { - struct - { - uint32_t reg_osd_pb_x_05 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_05 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_05; - - /* 0x028 : osd_pb_addr_06 */ - union { - struct - { - uint32_t reg_osd_pb_x_06 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_06 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_06; - - /* 0x02C : osd_pb_addr_07 */ - union { - struct - { - uint32_t reg_osd_pb_x_07 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_07 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_07; - - /* 0x030 : osd_pb_addr_08 */ - union { - struct - { - uint32_t reg_osd_pb_x_08 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_08 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_08; - - /* 0x034 : osd_pb_addr_09 */ - union { - struct - { - uint32_t reg_osd_pb_x_09 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_09 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_09; - - /* 0x038 : osd_pb_addr_0a */ - union { - struct - { - uint32_t reg_osd_pb_x_0a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0a; - - /* 0x03C : osd_pb_addr_0b */ - union { - struct - { - uint32_t reg_osd_pb_x_0b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0b; - - /* 0x040 : osd_pb_addr_0c */ - union { - struct - { - uint32_t reg_osd_pb_x_0c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0c; - - /* 0x044 : osd_pb_addr_0d */ - union { - struct - { - uint32_t reg_osd_pb_x_0d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0d; - - /* 0x048 : osd_pb_addr_0e */ - union { - struct - { - uint32_t reg_osd_pb_x_0e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0e; - - /* 0x04C : osd_pb_addr_0f */ - union { - struct - { - uint32_t reg_osd_pb_x_0f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_0f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_0f; - - /* 0x050 : osd_pb_addr_10 */ - union { - struct - { - uint32_t reg_osd_pb_x_10 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_10 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_10; - - /* 0x054 : osd_pb_addr_11 */ - union { - struct - { - uint32_t reg_osd_pb_x_11 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_11 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_11; - - /* 0x058 : osd_pb_addr_12 */ - union { - struct - { - uint32_t reg_osd_pb_x_12 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_12 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_12; - - /* 0x05C : osd_pb_addr_13 */ - union { - struct - { - uint32_t reg_osd_pb_x_13 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_13 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_13; - - /* 0x060 : osd_pb_addr_14 */ - union { - struct - { - uint32_t reg_osd_pb_x_14 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_14 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_14; - - /* 0x064 : osd_pb_addr_15 */ - union { - struct - { - uint32_t reg_osd_pb_x_15 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_15 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_15; - - /* 0x068 : osd_pb_addr_16 */ - union { - struct - { - uint32_t reg_osd_pb_x_16 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_16 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_16; - - /* 0x06C : osd_pb_addr_17 */ - union { - struct - { - uint32_t reg_osd_pb_x_17 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_17 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_17; - - /* 0x070 : osd_pb_addr_18 */ - union { - struct - { - uint32_t reg_osd_pb_x_18 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_18 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_18; - - /* 0x074 : osd_pb_addr_19 */ - union { - struct - { - uint32_t reg_osd_pb_x_19 : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_19 : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_19; - - /* 0x078 : osd_pb_addr_1a */ - union { - struct - { - uint32_t reg_osd_pb_x_1a : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1a : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1a; - - /* 0x07C : osd_pb_addr_1b */ - union { - struct - { - uint32_t reg_osd_pb_x_1b : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1b : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1b; - - /* 0x080 : osd_pb_addr_1c */ - union { - struct - { - uint32_t reg_osd_pb_x_1c : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1c : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1c; - - /* 0x084 : osd_pb_addr_1d */ - union { - struct - { - uint32_t reg_osd_pb_x_1d : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1d : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1d; - - /* 0x088 : osd_pb_addr_1e */ - union { - struct - { - uint32_t reg_osd_pb_x_1e : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1e : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1e; - - /* 0x08C : osd_pb_addr_1f */ - union { - struct - { - uint32_t reg_osd_pb_x_1f : 11; /* [10: 0], r/w, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t reg_osd_pb_y_1f : 11; /* [26:16], r/w, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } osd_pb_addr_1f; -}; - -typedef volatile struct osd_pb_reg osd_pb_reg_t; - -#endif /* __OSD_PROBE_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pdm_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pdm_reg.h deleted file mode 100644 index f5ad643be6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pdm_reg.h +++ /dev/null @@ -1,722 +0,0 @@ -/** - ****************************************************************************** - * @file pdm_reg.h - * @version V1.0 - * @date 2021-07-19 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __PDM_REG_H__ -#define __PDM_REG_H__ - -#include "bl808.h" - -/* 0xC00 : audpdm_top */ -#define PDM_AUDPDM_TOP_OFFSET (0xC00) -#define PDM_AUDIO_CKG_EN PDM_AUDIO_CKG_EN -#define PDM_AUDIO_CKG_EN_POS (0U) -#define PDM_AUDIO_CKG_EN_LEN (1U) -#define PDM_AUDIO_CKG_EN_MSK (((1U << PDM_AUDIO_CKG_EN_LEN) - 1) << PDM_AUDIO_CKG_EN_POS) -#define PDM_AUDIO_CKG_EN_UMSK (~(((1U << PDM_AUDIO_CKG_EN_LEN) - 1) << PDM_AUDIO_CKG_EN_POS)) -#define PDM_ADC_ITF_INV_SEL PDM_ADC_ITF_INV_SEL -#define PDM_ADC_ITF_INV_SEL_POS (2U) -#define PDM_ADC_ITF_INV_SEL_LEN (1U) -#define PDM_ADC_ITF_INV_SEL_MSK (((1U << PDM_ADC_ITF_INV_SEL_LEN) - 1) << PDM_ADC_ITF_INV_SEL_POS) -#define PDM_ADC_ITF_INV_SEL_UMSK (~(((1U << PDM_ADC_ITF_INV_SEL_LEN) - 1) << PDM_ADC_ITF_INV_SEL_POS)) -#define PDM_ITF_INV_SEL PDM_ITF_INV_SEL -#define PDM_ITF_INV_SEL_POS (3U) -#define PDM_ITF_INV_SEL_LEN (1U) -#define PDM_ITF_INV_SEL_MSK (((1U << PDM_ITF_INV_SEL_LEN) - 1) << PDM_ITF_INV_SEL_POS) -#define PDM_ITF_INV_SEL_UMSK (~(((1U << PDM_ITF_INV_SEL_LEN) - 1) << PDM_ITF_INV_SEL_POS)) -#define PDM_ADC_RATE PDM_ADC_RATE -#define PDM_ADC_RATE_POS (28U) -#define PDM_ADC_RATE_LEN (3U) -#define PDM_ADC_RATE_MSK (((1U << PDM_ADC_RATE_LEN) - 1) << PDM_ADC_RATE_POS) -#define PDM_ADC_RATE_UMSK (~(((1U << PDM_ADC_RATE_LEN) - 1) << PDM_ADC_RATE_POS)) - -/* 0xC04 : audpdm_itf */ -#define PDM_AUDPDM_ITF_OFFSET (0xC04) -#define PDM_ADC_0_EN PDM_ADC_0_EN -#define PDM_ADC_0_EN_POS (0U) -#define PDM_ADC_0_EN_LEN (1U) -#define PDM_ADC_0_EN_MSK (((1U << PDM_ADC_0_EN_LEN) - 1) << PDM_ADC_0_EN_POS) -#define PDM_ADC_0_EN_UMSK (~(((1U << PDM_ADC_0_EN_LEN) - 1) << PDM_ADC_0_EN_POS)) -#define PDM_ADC_1_EN PDM_ADC_1_EN -#define PDM_ADC_1_EN_POS (1U) -#define PDM_ADC_1_EN_LEN (1U) -#define PDM_ADC_1_EN_MSK (((1U << PDM_ADC_1_EN_LEN) - 1) << PDM_ADC_1_EN_POS) -#define PDM_ADC_1_EN_UMSK (~(((1U << PDM_ADC_1_EN_LEN) - 1) << PDM_ADC_1_EN_POS)) -#define PDM_ADC_2_EN PDM_ADC_2_EN -#define PDM_ADC_2_EN_POS (2U) -#define PDM_ADC_2_EN_LEN (1U) -#define PDM_ADC_2_EN_MSK (((1U << PDM_ADC_2_EN_LEN) - 1) << PDM_ADC_2_EN_POS) -#define PDM_ADC_2_EN_UMSK (~(((1U << PDM_ADC_2_EN_LEN) - 1) << PDM_ADC_2_EN_POS)) -#define PDM_AUD_RX0_SEL PDM_AUD_RX0_SEL -#define PDM_AUD_RX0_SEL_POS (13U) -#define PDM_AUD_RX0_SEL_LEN (3U) -#define PDM_AUD_RX0_SEL_MSK (((1U << PDM_AUD_RX0_SEL_LEN) - 1) << PDM_AUD_RX0_SEL_POS) -#define PDM_AUD_RX0_SEL_UMSK (~(((1U << PDM_AUD_RX0_SEL_LEN) - 1) << PDM_AUD_RX0_SEL_POS)) -#define PDM_AUD_RX1_SEL PDM_AUD_RX1_SEL -#define PDM_AUD_RX1_SEL_POS (16U) -#define PDM_AUD_RX1_SEL_LEN (3U) -#define PDM_AUD_RX1_SEL_MSK (((1U << PDM_AUD_RX1_SEL_LEN) - 1) << PDM_AUD_RX1_SEL_POS) -#define PDM_AUD_RX1_SEL_UMSK (~(((1U << PDM_AUD_RX1_SEL_LEN) - 1) << PDM_AUD_RX1_SEL_POS)) -#define PDM_AUD_RX2_SEL PDM_AUD_RX2_SEL -#define PDM_AUD_RX2_SEL_POS (19U) -#define PDM_AUD_RX2_SEL_LEN (3U) -#define PDM_AUD_RX2_SEL_MSK (((1U << PDM_AUD_RX2_SEL_LEN) - 1) << PDM_AUD_RX2_SEL_POS) -#define PDM_AUD_RX2_SEL_UMSK (~(((1U << PDM_AUD_RX2_SEL_LEN) - 1) << PDM_AUD_RX2_SEL_POS)) -#define PDM_ADC_ITF_EN PDM_ADC_ITF_EN -#define PDM_ADC_ITF_EN_POS (30U) -#define PDM_ADC_ITF_EN_LEN (1U) -#define PDM_ADC_ITF_EN_MSK (((1U << PDM_ADC_ITF_EN_LEN) - 1) << PDM_ADC_ITF_EN_POS) -#define PDM_ADC_ITF_EN_UMSK (~(((1U << PDM_ADC_ITF_EN_LEN) - 1) << PDM_ADC_ITF_EN_POS)) - -/* 0xC08 : pdm_adc_0 */ -#define PDM_ADC_0_OFFSET (0xC08) -#define PDM_ADC_0_FIR_MODE PDM_ADC_0_FIR_MODE -#define PDM_ADC_0_FIR_MODE_POS (0U) -#define PDM_ADC_0_FIR_MODE_LEN (1U) -#define PDM_ADC_0_FIR_MODE_MSK (((1U << PDM_ADC_0_FIR_MODE_LEN) - 1) << PDM_ADC_0_FIR_MODE_POS) -#define PDM_ADC_0_FIR_MODE_UMSK (~(((1U << PDM_ADC_0_FIR_MODE_LEN) - 1) << PDM_ADC_0_FIR_MODE_POS)) -#define PDM_ADC_1_FIR_MODE PDM_ADC_1_FIR_MODE -#define PDM_ADC_1_FIR_MODE_POS (1U) -#define PDM_ADC_1_FIR_MODE_LEN (1U) -#define PDM_ADC_1_FIR_MODE_MSK (((1U << PDM_ADC_1_FIR_MODE_LEN) - 1) << PDM_ADC_1_FIR_MODE_POS) -#define PDM_ADC_1_FIR_MODE_UMSK (~(((1U << PDM_ADC_1_FIR_MODE_LEN) - 1) << PDM_ADC_1_FIR_MODE_POS)) -#define PDM_ADC_2_FIR_MODE PDM_ADC_2_FIR_MODE -#define PDM_ADC_2_FIR_MODE_POS (2U) -#define PDM_ADC_2_FIR_MODE_LEN (1U) -#define PDM_ADC_2_FIR_MODE_MSK (((1U << PDM_ADC_2_FIR_MODE_LEN) - 1) << PDM_ADC_2_FIR_MODE_POS) -#define PDM_ADC_2_FIR_MODE_UMSK (~(((1U << PDM_ADC_2_FIR_MODE_LEN) - 1) << PDM_ADC_2_FIR_MODE_POS)) -#define PDM_ADC_0_SCAL PDM_ADC_0_SCAL -#define PDM_ADC_0_SCAL_POS (3U) -#define PDM_ADC_0_SCAL_LEN (6U) -#define PDM_ADC_0_SCAL_MSK (((1U << PDM_ADC_0_SCAL_LEN) - 1) << PDM_ADC_0_SCAL_POS) -#define PDM_ADC_0_SCAL_UMSK (~(((1U << PDM_ADC_0_SCAL_LEN) - 1) << PDM_ADC_0_SCAL_POS)) -#define PDM_ADC_1_SCAL PDM_ADC_1_SCAL -#define PDM_ADC_1_SCAL_POS (9U) -#define PDM_ADC_1_SCAL_LEN (6U) -#define PDM_ADC_1_SCAL_MSK (((1U << PDM_ADC_1_SCAL_LEN) - 1) << PDM_ADC_1_SCAL_POS) -#define PDM_ADC_1_SCAL_UMSK (~(((1U << PDM_ADC_1_SCAL_LEN) - 1) << PDM_ADC_1_SCAL_POS)) -#define PDM_ADC_2_SCAL PDM_ADC_2_SCAL -#define PDM_ADC_2_SCAL_POS (15U) -#define PDM_ADC_2_SCAL_LEN (6U) -#define PDM_ADC_2_SCAL_MSK (((1U << PDM_ADC_2_SCAL_LEN) - 1) << PDM_ADC_2_SCAL_POS) -#define PDM_ADC_2_SCAL_UMSK (~(((1U << PDM_ADC_2_SCAL_LEN) - 1) << PDM_ADC_2_SCAL_POS)) - -/* 0xC0C : pdm_adc_1 */ -#define PDM_ADC_1_OFFSET (0xC0C) -#define PDM_ADC_0_K1 PDM_ADC_0_K1 -#define PDM_ADC_0_K1_POS (0U) -#define PDM_ADC_0_K1_LEN (4U) -#define PDM_ADC_0_K1_MSK (((1U << PDM_ADC_0_K1_LEN) - 1) << PDM_ADC_0_K1_POS) -#define PDM_ADC_0_K1_UMSK (~(((1U << PDM_ADC_0_K1_LEN) - 1) << PDM_ADC_0_K1_POS)) -#define PDM_ADC_0_K1_EN PDM_ADC_0_K1_EN -#define PDM_ADC_0_K1_EN_POS (4U) -#define PDM_ADC_0_K1_EN_LEN (1U) -#define PDM_ADC_0_K1_EN_MSK (((1U << PDM_ADC_0_K1_EN_LEN) - 1) << PDM_ADC_0_K1_EN_POS) -#define PDM_ADC_0_K1_EN_UMSK (~(((1U << PDM_ADC_0_K1_EN_LEN) - 1) << PDM_ADC_0_K1_EN_POS)) -#define PDM_ADC_0_K2 PDM_ADC_0_K2 -#define PDM_ADC_0_K2_POS (5U) -#define PDM_ADC_0_K2_LEN (4U) -#define PDM_ADC_0_K2_MSK (((1U << PDM_ADC_0_K2_LEN) - 1) << PDM_ADC_0_K2_POS) -#define PDM_ADC_0_K2_UMSK (~(((1U << PDM_ADC_0_K2_LEN) - 1) << PDM_ADC_0_K2_POS)) -#define PDM_ADC_0_K2_EN PDM_ADC_0_K2_EN -#define PDM_ADC_0_K2_EN_POS (9U) -#define PDM_ADC_0_K2_EN_LEN (1U) -#define PDM_ADC_0_K2_EN_MSK (((1U << PDM_ADC_0_K2_EN_LEN) - 1) << PDM_ADC_0_K2_EN_POS) -#define PDM_ADC_0_K2_EN_UMSK (~(((1U << PDM_ADC_0_K2_EN_LEN) - 1) << PDM_ADC_0_K2_EN_POS)) -#define PDM_ADC_1_K1 PDM_ADC_1_K1 -#define PDM_ADC_1_K1_POS (10U) -#define PDM_ADC_1_K1_LEN (4U) -#define PDM_ADC_1_K1_MSK (((1U << PDM_ADC_1_K1_LEN) - 1) << PDM_ADC_1_K1_POS) -#define PDM_ADC_1_K1_UMSK (~(((1U << PDM_ADC_1_K1_LEN) - 1) << PDM_ADC_1_K1_POS)) -#define PDM_ADC_1_K1_EN PDM_ADC_1_K1_EN -#define PDM_ADC_1_K1_EN_POS (14U) -#define PDM_ADC_1_K1_EN_LEN (1U) -#define PDM_ADC_1_K1_EN_MSK (((1U << PDM_ADC_1_K1_EN_LEN) - 1) << PDM_ADC_1_K1_EN_POS) -#define PDM_ADC_1_K1_EN_UMSK (~(((1U << PDM_ADC_1_K1_EN_LEN) - 1) << PDM_ADC_1_K1_EN_POS)) -#define PDM_ADC_1_K2 PDM_ADC_1_K2 -#define PDM_ADC_1_K2_POS (15U) -#define PDM_ADC_1_K2_LEN (4U) -#define PDM_ADC_1_K2_MSK (((1U << PDM_ADC_1_K2_LEN) - 1) << PDM_ADC_1_K2_POS) -#define PDM_ADC_1_K2_UMSK (~(((1U << PDM_ADC_1_K2_LEN) - 1) << PDM_ADC_1_K2_POS)) -#define PDM_ADC_1_K2_EN PDM_ADC_1_K2_EN -#define PDM_ADC_1_K2_EN_POS (19U) -#define PDM_ADC_1_K2_EN_LEN (1U) -#define PDM_ADC_1_K2_EN_MSK (((1U << PDM_ADC_1_K2_EN_LEN) - 1) << PDM_ADC_1_K2_EN_POS) -#define PDM_ADC_1_K2_EN_UMSK (~(((1U << PDM_ADC_1_K2_EN_LEN) - 1) << PDM_ADC_1_K2_EN_POS)) -#define PDM_ADC_2_K1 PDM_ADC_2_K1 -#define PDM_ADC_2_K1_POS (20U) -#define PDM_ADC_2_K1_LEN (4U) -#define PDM_ADC_2_K1_MSK (((1U << PDM_ADC_2_K1_LEN) - 1) << PDM_ADC_2_K1_POS) -#define PDM_ADC_2_K1_UMSK (~(((1U << PDM_ADC_2_K1_LEN) - 1) << PDM_ADC_2_K1_POS)) -#define PDM_ADC_2_K1_EN PDM_ADC_2_K1_EN -#define PDM_ADC_2_K1_EN_POS (24U) -#define PDM_ADC_2_K1_EN_LEN (1U) -#define PDM_ADC_2_K1_EN_MSK (((1U << PDM_ADC_2_K1_EN_LEN) - 1) << PDM_ADC_2_K1_EN_POS) -#define PDM_ADC_2_K1_EN_UMSK (~(((1U << PDM_ADC_2_K1_EN_LEN) - 1) << PDM_ADC_2_K1_EN_POS)) -#define PDM_ADC_2_K2 PDM_ADC_2_K2 -#define PDM_ADC_2_K2_POS (25U) -#define PDM_ADC_2_K2_LEN (4U) -#define PDM_ADC_2_K2_MSK (((1U << PDM_ADC_2_K2_LEN) - 1) << PDM_ADC_2_K2_POS) -#define PDM_ADC_2_K2_UMSK (~(((1U << PDM_ADC_2_K2_LEN) - 1) << PDM_ADC_2_K2_POS)) -#define PDM_ADC_2_K2_EN PDM_ADC_2_K2_EN -#define PDM_ADC_2_K2_EN_POS (29U) -#define PDM_ADC_2_K2_EN_LEN (1U) -#define PDM_ADC_2_K2_EN_MSK (((1U << PDM_ADC_2_K2_EN_LEN) - 1) << PDM_ADC_2_K2_EN_POS) -#define PDM_ADC_2_K2_EN_UMSK (~(((1U << PDM_ADC_2_K2_EN_LEN) - 1) << PDM_ADC_2_K2_EN_POS)) - -/* 0xC10 : pdm_dac_0 */ -#define PDM_DAC_0_OFFSET (0xC10) -#define PDM_ADC_PDM_H PDM_ADC_PDM_H -#define PDM_ADC_PDM_H_POS (0U) -#define PDM_ADC_PDM_H_LEN (6U) -#define PDM_ADC_PDM_H_MSK (((1U << PDM_ADC_PDM_H_LEN) - 1) << PDM_ADC_PDM_H_POS) -#define PDM_ADC_PDM_H_UMSK (~(((1U << PDM_ADC_PDM_H_LEN) - 1) << PDM_ADC_PDM_H_POS)) -#define PDM_ADC_PDM_L PDM_ADC_PDM_L -#define PDM_ADC_PDM_L_POS (6U) -#define PDM_ADC_PDM_L_LEN (6U) -#define PDM_ADC_PDM_L_MSK (((1U << PDM_ADC_PDM_L_LEN) - 1) << PDM_ADC_PDM_L_POS) -#define PDM_ADC_PDM_L_UMSK (~(((1U << PDM_ADC_PDM_L_LEN) - 1) << PDM_ADC_PDM_L_POS)) -#define PDM_ADC_0_PDM_LVL_SWAP PDM_ADC_0_PDM_LVL_SWAP -#define PDM_ADC_0_PDM_LVL_SWAP_POS (13U) -#define PDM_ADC_0_PDM_LVL_SWAP_LEN (1U) -#define PDM_ADC_0_PDM_LVL_SWAP_MSK (((1U << PDM_ADC_0_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_0_PDM_LVL_SWAP_POS) -#define PDM_ADC_0_PDM_LVL_SWAP_UMSK (~(((1U << PDM_ADC_0_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_0_PDM_LVL_SWAP_POS)) -#define PDM_ADC_1_PDM_LVL_SWAP PDM_ADC_1_PDM_LVL_SWAP -#define PDM_ADC_1_PDM_LVL_SWAP_POS (16U) -#define PDM_ADC_1_PDM_LVL_SWAP_LEN (1U) -#define PDM_ADC_1_PDM_LVL_SWAP_MSK (((1U << PDM_ADC_1_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_1_PDM_LVL_SWAP_POS) -#define PDM_ADC_1_PDM_LVL_SWAP_UMSK (~(((1U << PDM_ADC_1_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_1_PDM_LVL_SWAP_POS)) -#define PDM_ADC_2_PDM_LVL_SWAP PDM_ADC_2_PDM_LVL_SWAP -#define PDM_ADC_2_PDM_LVL_SWAP_POS (19U) -#define PDM_ADC_2_PDM_LVL_SWAP_LEN (1U) -#define PDM_ADC_2_PDM_LVL_SWAP_MSK (((1U << PDM_ADC_2_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_2_PDM_LVL_SWAP_POS) -#define PDM_ADC_2_PDM_LVL_SWAP_UMSK (~(((1U << PDM_ADC_2_PDM_LVL_SWAP_LEN) - 1) << PDM_ADC_2_PDM_LVL_SWAP_POS)) - -/* 0xC1C : pdm_pdm_0 */ -#define PDM_PDM_0_OFFSET (0xC1C) -#define PDM_0_EN PDM_0_EN -#define PDM_0_EN_POS (0U) -#define PDM_0_EN_LEN (1U) -#define PDM_0_EN_MSK (((1U << PDM_0_EN_LEN) - 1) << PDM_0_EN_POS) -#define PDM_0_EN_UMSK (~(((1U << PDM_0_EN_LEN) - 1) << PDM_0_EN_POS)) -#define PDM_1_EN PDM_1_EN -#define PDM_1_EN_POS (1U) -#define PDM_1_EN_LEN (1U) -#define PDM_1_EN_MSK (((1U << PDM_1_EN_LEN) - 1) << PDM_1_EN_POS) -#define PDM_1_EN_UMSK (~(((1U << PDM_1_EN_LEN) - 1) << PDM_1_EN_POS)) -#define PDM_2_EN PDM_2_EN -#define PDM_2_EN_POS (2U) -#define PDM_2_EN_LEN (1U) -#define PDM_2_EN_MSK (((1U << PDM_2_EN_LEN) - 1) << PDM_2_EN_POS) -#define PDM_2_EN_UMSK (~(((1U << PDM_2_EN_LEN) - 1) << PDM_2_EN_POS)) -#define PDM_ADC_0_PDM_SEL PDM_ADC_0_PDM_SEL -#define PDM_ADC_0_PDM_SEL_POS (3U) -#define PDM_ADC_0_PDM_SEL_LEN (3U) -#define PDM_ADC_0_PDM_SEL_MSK (((1U << PDM_ADC_0_PDM_SEL_LEN) - 1) << PDM_ADC_0_PDM_SEL_POS) -#define PDM_ADC_0_PDM_SEL_UMSK (~(((1U << PDM_ADC_0_PDM_SEL_LEN) - 1) << PDM_ADC_0_PDM_SEL_POS)) -#define PDM_ADC_1_PDM_SEL PDM_ADC_1_PDM_SEL -#define PDM_ADC_1_PDM_SEL_POS (6U) -#define PDM_ADC_1_PDM_SEL_LEN (3U) -#define PDM_ADC_1_PDM_SEL_MSK (((1U << PDM_ADC_1_PDM_SEL_LEN) - 1) << PDM_ADC_1_PDM_SEL_POS) -#define PDM_ADC_1_PDM_SEL_UMSK (~(((1U << PDM_ADC_1_PDM_SEL_LEN) - 1) << PDM_ADC_1_PDM_SEL_POS)) -#define PDM_ADC_2_PDM_SEL PDM_ADC_2_PDM_SEL -#define PDM_ADC_2_PDM_SEL_POS (9U) -#define PDM_ADC_2_PDM_SEL_LEN (3U) -#define PDM_ADC_2_PDM_SEL_MSK (((1U << PDM_ADC_2_PDM_SEL_LEN) - 1) << PDM_ADC_2_PDM_SEL_POS) -#define PDM_ADC_2_PDM_SEL_UMSK (~(((1U << PDM_ADC_2_PDM_SEL_LEN) - 1) << PDM_ADC_2_PDM_SEL_POS)) - -/* 0xC20 : pdm_rsvd0 */ -#define PDM_RSVD0_OFFSET (0xC20) - -/* 0xC24 : pdm_dbg_0 */ -#define PDM_DBG_0_OFFSET (0xC24) -#define PDM_ADC_TEST_CLKIN_EN PDM_ADC_TEST_CLKIN_EN -#define PDM_ADC_TEST_CLKIN_EN_POS (21U) -#define PDM_ADC_TEST_CLKIN_EN_LEN (1U) -#define PDM_ADC_TEST_CLKIN_EN_MSK (((1U << PDM_ADC_TEST_CLKIN_EN_LEN) - 1) << PDM_ADC_TEST_CLKIN_EN_POS) -#define PDM_ADC_TEST_CLKIN_EN_UMSK (~(((1U << PDM_ADC_TEST_CLKIN_EN_LEN) - 1) << PDM_ADC_TEST_CLKIN_EN_POS)) -#define PDM_ADC_TEST_DIN_EN PDM_ADC_TEST_DIN_EN -#define PDM_ADC_TEST_DIN_EN_POS (23U) -#define PDM_ADC_TEST_DIN_EN_LEN (1U) -#define PDM_ADC_TEST_DIN_EN_MSK (((1U << PDM_ADC_TEST_DIN_EN_LEN) - 1) << PDM_ADC_TEST_DIN_EN_POS) -#define PDM_ADC_TEST_DIN_EN_UMSK (~(((1U << PDM_ADC_TEST_DIN_EN_LEN) - 1) << PDM_ADC_TEST_DIN_EN_POS)) -#define PDM_AUD_TEST_READ_SEL PDM_AUD_TEST_READ_SEL -#define PDM_AUD_TEST_READ_SEL_POS (24U) -#define PDM_AUD_TEST_READ_SEL_LEN (6U) -#define PDM_AUD_TEST_READ_SEL_MSK (((1U << PDM_AUD_TEST_READ_SEL_LEN) - 1) << PDM_AUD_TEST_READ_SEL_POS) -#define PDM_AUD_TEST_READ_SEL_UMSK (~(((1U << PDM_AUD_TEST_READ_SEL_LEN) - 1) << PDM_AUD_TEST_READ_SEL_POS)) - -/* 0xC28 : pdm_dbg_1 */ -#define PDM_DBG_1_OFFSET (0xC28) -#define PDM_AUD_TEST_READ PDM_AUD_TEST_READ -#define PDM_AUD_TEST_READ_POS (0U) -#define PDM_AUD_TEST_READ_LEN (32U) -#define PDM_AUD_TEST_READ_MSK (((1U << PDM_AUD_TEST_READ_LEN) - 1) << PDM_AUD_TEST_READ_POS) -#define PDM_AUD_TEST_READ_UMSK (~(((1U << PDM_AUD_TEST_READ_LEN) - 1) << PDM_AUD_TEST_READ_POS)) - -/* 0xC2C : pdm_dbg_2 */ -#define PDM_DBG_2_OFFSET (0xC2C) -#define PDM_ADC_FIR_4S_VAL PDM_ADC_FIR_4S_VAL -#define PDM_ADC_FIR_4S_VAL_POS (0U) -#define PDM_ADC_FIR_4S_VAL_LEN (20U) -#define PDM_ADC_FIR_4S_VAL_MSK (((1U << PDM_ADC_FIR_4S_VAL_LEN) - 1) << PDM_ADC_FIR_4S_VAL_POS) -#define PDM_ADC_FIR_4S_VAL_UMSK (~(((1U << PDM_ADC_FIR_4S_VAL_LEN) - 1) << PDM_ADC_FIR_4S_VAL_POS)) -#define PDM_ADC_0_FIR_4S_EN PDM_ADC_0_FIR_4S_EN -#define PDM_ADC_0_FIR_4S_EN_POS (20U) -#define PDM_ADC_0_FIR_4S_EN_LEN (1U) -#define PDM_ADC_0_FIR_4S_EN_MSK (((1U << PDM_ADC_0_FIR_4S_EN_LEN) - 1) << PDM_ADC_0_FIR_4S_EN_POS) -#define PDM_ADC_0_FIR_4S_EN_UMSK (~(((1U << PDM_ADC_0_FIR_4S_EN_LEN) - 1) << PDM_ADC_0_FIR_4S_EN_POS)) -#define PDM_ADC_1_FIR_4S_EN PDM_ADC_1_FIR_4S_EN -#define PDM_ADC_1_FIR_4S_EN_POS (21U) -#define PDM_ADC_1_FIR_4S_EN_LEN (1U) -#define PDM_ADC_1_FIR_4S_EN_MSK (((1U << PDM_ADC_1_FIR_4S_EN_LEN) - 1) << PDM_ADC_1_FIR_4S_EN_POS) -#define PDM_ADC_1_FIR_4S_EN_UMSK (~(((1U << PDM_ADC_1_FIR_4S_EN_LEN) - 1) << PDM_ADC_1_FIR_4S_EN_POS)) -#define PDM_ADC_2_FIR_4S_EN PDM_ADC_2_FIR_4S_EN -#define PDM_ADC_2_FIR_4S_EN_POS (22U) -#define PDM_ADC_2_FIR_4S_EN_LEN (1U) -#define PDM_ADC_2_FIR_4S_EN_MSK (((1U << PDM_ADC_2_FIR_4S_EN_LEN) - 1) << PDM_ADC_2_FIR_4S_EN_POS) -#define PDM_ADC_2_FIR_4S_EN_UMSK (~(((1U << PDM_ADC_2_FIR_4S_EN_LEN) - 1) << PDM_ADC_2_FIR_4S_EN_POS)) -#define PDM_ADC_IN_0_TEST_SEL PDM_ADC_IN_0_TEST_SEL -#define PDM_ADC_IN_0_TEST_SEL_POS (23U) -#define PDM_ADC_IN_0_TEST_SEL_LEN (1U) -#define PDM_ADC_IN_0_TEST_SEL_MSK (((1U << PDM_ADC_IN_0_TEST_SEL_LEN) - 1) << PDM_ADC_IN_0_TEST_SEL_POS) -#define PDM_ADC_IN_0_TEST_SEL_UMSK (~(((1U << PDM_ADC_IN_0_TEST_SEL_LEN) - 1) << PDM_ADC_IN_0_TEST_SEL_POS)) -#define PDM_ADC_IN_1_TEST_SEL PDM_ADC_IN_1_TEST_SEL -#define PDM_ADC_IN_1_TEST_SEL_POS (24U) -#define PDM_ADC_IN_1_TEST_SEL_LEN (1U) -#define PDM_ADC_IN_1_TEST_SEL_MSK (((1U << PDM_ADC_IN_1_TEST_SEL_LEN) - 1) << PDM_ADC_IN_1_TEST_SEL_POS) -#define PDM_ADC_IN_1_TEST_SEL_UMSK (~(((1U << PDM_ADC_IN_1_TEST_SEL_LEN) - 1) << PDM_ADC_IN_1_TEST_SEL_POS)) -#define PDM_ADC_IN_2_TEST_SEL PDM_ADC_IN_2_TEST_SEL -#define PDM_ADC_IN_2_TEST_SEL_POS (25U) -#define PDM_ADC_IN_2_TEST_SEL_LEN (1U) -#define PDM_ADC_IN_2_TEST_SEL_MSK (((1U << PDM_ADC_IN_2_TEST_SEL_LEN) - 1) << PDM_ADC_IN_2_TEST_SEL_POS) -#define PDM_ADC_IN_2_TEST_SEL_UMSK (~(((1U << PDM_ADC_IN_2_TEST_SEL_LEN) - 1) << PDM_ADC_IN_2_TEST_SEL_POS)) - -/* 0xC30 : pdm_dbg_3 */ -#define PDM_DBG_3_OFFSET (0xC30) - -/* 0xC34 : pdm_dbg_4 */ -#define PDM_DBG_4_OFFSET (0xC34) -#define PDM_ADC_IN_RATIO_4S_VAL PDM_ADC_IN_RATIO_4S_VAL -#define PDM_ADC_IN_RATIO_4S_VAL_POS (0U) -#define PDM_ADC_IN_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_RATIO_4S_VAL_POS)) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL PDM_ADC_IN_CH0_RATIO_4S_VAL -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_POS (1U) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH0_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_CH0_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_CH0_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH0_RATIO_4S_VAL_POS)) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL PDM_ADC_IN_CH1_RATIO_4S_VAL -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_POS (2U) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH1_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_CH1_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_CH1_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH1_RATIO_4S_VAL_POS)) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL PDM_ADC_IN_CH2_RATIO_4S_VAL -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_POS (3U) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_LEN (1U) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_MSK (((1U << PDM_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH2_RATIO_4S_VAL_POS) -#define PDM_ADC_IN_CH2_RATIO_4S_VAL_UMSK (~(((1U << PDM_ADC_IN_CH2_RATIO_4S_VAL_LEN) - 1) << PDM_ADC_IN_CH2_RATIO_4S_VAL_POS)) -#define PDM_IN_RATIO_4S_VAL PDM_IN_RATIO_4S_VAL -#define PDM_IN_RATIO_4S_VAL_POS (4U) -#define PDM_IN_RATIO_4S_VAL_LEN (1U) -#define PDM_IN_RATIO_4S_VAL_MSK (((1U << PDM_IN_RATIO_4S_VAL_LEN) - 1) << PDM_IN_RATIO_4S_VAL_POS) -#define PDM_IN_RATIO_4S_VAL_UMSK (~(((1U << PDM_IN_RATIO_4S_VAL_LEN) - 1) << PDM_IN_RATIO_4S_VAL_POS)) -#define PDM_IN_RATIO_4S PDM_IN_RATIO_4S -#define PDM_IN_RATIO_4S_POS (5U) -#define PDM_IN_RATIO_4S_LEN (1U) -#define PDM_IN_RATIO_4S_MSK (((1U << PDM_IN_RATIO_4S_LEN) - 1) << PDM_IN_RATIO_4S_POS) -#define PDM_IN_RATIO_4S_UMSK (~(((1U << PDM_IN_RATIO_4S_LEN) - 1) << PDM_IN_RATIO_4S_POS)) - -/* 0xC38 : pdm_adc_s0 */ -#define PDM_ADC_S0_OFFSET (0xC38) -#define PDM_ADC_S0_VOLUME PDM_ADC_S0_VOLUME -#define PDM_ADC_S0_VOLUME_POS (0U) -#define PDM_ADC_S0_VOLUME_LEN (9U) -#define PDM_ADC_S0_VOLUME_MSK (((1U << PDM_ADC_S0_VOLUME_LEN) - 1) << PDM_ADC_S0_VOLUME_POS) -#define PDM_ADC_S0_VOLUME_UMSK (~(((1U << PDM_ADC_S0_VOLUME_LEN) - 1) << PDM_ADC_S0_VOLUME_POS)) - -/* 0xC3C : pdm_adc_s1 */ -#define PDM_ADC_S1_OFFSET (0xC3C) -#define PDM_ADC_S1_VOLUME PDM_ADC_S1_VOLUME -#define PDM_ADC_S1_VOLUME_POS (0U) -#define PDM_ADC_S1_VOLUME_LEN (9U) -#define PDM_ADC_S1_VOLUME_MSK (((1U << PDM_ADC_S1_VOLUME_LEN) - 1) << PDM_ADC_S1_VOLUME_POS) -#define PDM_ADC_S1_VOLUME_UMSK (~(((1U << PDM_ADC_S1_VOLUME_LEN) - 1) << PDM_ADC_S1_VOLUME_POS)) - -/* 0xC40 : pdm_adc_s2 */ -#define PDM_ADC_S2_OFFSET (0xC40) -#define PDM_ADC_S2_VOLUME PDM_ADC_S2_VOLUME -#define PDM_ADC_S2_VOLUME_POS (0U) -#define PDM_ADC_S2_VOLUME_LEN (9U) -#define PDM_ADC_S2_VOLUME_MSK (((1U << PDM_ADC_S2_VOLUME_LEN) - 1) << PDM_ADC_S2_VOLUME_POS) -#define PDM_ADC_S2_VOLUME_UMSK (~(((1U << PDM_ADC_S2_VOLUME_LEN) - 1) << PDM_ADC_S2_VOLUME_POS)) - -/* 0xC80 : pdm_rx_fifo_ctrl */ -#define PDM_RX_FIFO_CTRL_OFFSET (0xC80) -#define PDM_RX_FIFO_FLUSH PDM_RX_FIFO_FLUSH -#define PDM_RX_FIFO_FLUSH_POS (0U) -#define PDM_RX_FIFO_FLUSH_LEN (1U) -#define PDM_RX_FIFO_FLUSH_MSK (((1U << PDM_RX_FIFO_FLUSH_LEN) - 1) << PDM_RX_FIFO_FLUSH_POS) -#define PDM_RX_FIFO_FLUSH_UMSK (~(((1U << PDM_RX_FIFO_FLUSH_LEN) - 1) << PDM_RX_FIFO_FLUSH_POS)) -#define PDM_RXO_INT_EN PDM_RXO_INT_EN -#define PDM_RXO_INT_EN_POS (1U) -#define PDM_RXO_INT_EN_LEN (1U) -#define PDM_RXO_INT_EN_MSK (((1U << PDM_RXO_INT_EN_LEN) - 1) << PDM_RXO_INT_EN_POS) -#define PDM_RXO_INT_EN_UMSK (~(((1U << PDM_RXO_INT_EN_LEN) - 1) << PDM_RXO_INT_EN_POS)) -#define PDM_RXU_INT_EN PDM_RXU_INT_EN -#define PDM_RXU_INT_EN_POS (2U) -#define PDM_RXU_INT_EN_LEN (1U) -#define PDM_RXU_INT_EN_MSK (((1U << PDM_RXU_INT_EN_LEN) - 1) << PDM_RXU_INT_EN_POS) -#define PDM_RXU_INT_EN_UMSK (~(((1U << PDM_RXU_INT_EN_LEN) - 1) << PDM_RXU_INT_EN_POS)) -#define PDM_RXA_INT_EN PDM_RXA_INT_EN -#define PDM_RXA_INT_EN_POS (3U) -#define PDM_RXA_INT_EN_LEN (1U) -#define PDM_RXA_INT_EN_MSK (((1U << PDM_RXA_INT_EN_LEN) - 1) << PDM_RXA_INT_EN_POS) -#define PDM_RXA_INT_EN_UMSK (~(((1U << PDM_RXA_INT_EN_LEN) - 1) << PDM_RXA_INT_EN_POS)) -#define PDM_RX_DRQ_EN PDM_RX_DRQ_EN -#define PDM_RX_DRQ_EN_POS (4U) -#define PDM_RX_DRQ_EN_LEN (1U) -#define PDM_RX_DRQ_EN_MSK (((1U << PDM_RX_DRQ_EN_LEN) - 1) << PDM_RX_DRQ_EN_POS) -#define PDM_RX_DRQ_EN_UMSK (~(((1U << PDM_RX_DRQ_EN_LEN) - 1) << PDM_RX_DRQ_EN_POS)) -#define PDM_RX_DATA_RES PDM_RX_DATA_RES -#define PDM_RX_DATA_RES_POS (5U) -#define PDM_RX_DATA_RES_LEN (1U) -#define PDM_RX_DATA_RES_MSK (((1U << PDM_RX_DATA_RES_LEN) - 1) << PDM_RX_DATA_RES_POS) -#define PDM_RX_DATA_RES_UMSK (~(((1U << PDM_RX_DATA_RES_LEN) - 1) << PDM_RX_DATA_RES_POS)) -#define PDM_RX_CH_EN PDM_RX_CH_EN -#define PDM_RX_CH_EN_POS (8U) -#define PDM_RX_CH_EN_LEN (3U) -#define PDM_RX_CH_EN_MSK (((1U << PDM_RX_CH_EN_LEN) - 1) << PDM_RX_CH_EN_POS) -#define PDM_RX_CH_EN_UMSK (~(((1U << PDM_RX_CH_EN_LEN) - 1) << PDM_RX_CH_EN_POS)) -#define PDM_RX_DRQ_CNT PDM_RX_DRQ_CNT -#define PDM_RX_DRQ_CNT_POS (14U) -#define PDM_RX_DRQ_CNT_LEN (2U) -#define PDM_RX_DRQ_CNT_MSK (((1U << PDM_RX_DRQ_CNT_LEN) - 1) << PDM_RX_DRQ_CNT_POS) -#define PDM_RX_DRQ_CNT_UMSK (~(((1U << PDM_RX_DRQ_CNT_LEN) - 1) << PDM_RX_DRQ_CNT_POS)) -#define PDM_RX_TRG_LEVEL PDM_RX_TRG_LEVEL -#define PDM_RX_TRG_LEVEL_POS (16U) -#define PDM_RX_TRG_LEVEL_LEN (6U) -#define PDM_RX_TRG_LEVEL_MSK (((1U << PDM_RX_TRG_LEVEL_LEN) - 1) << PDM_RX_TRG_LEVEL_POS) -#define PDM_RX_TRG_LEVEL_UMSK (~(((1U << PDM_RX_TRG_LEVEL_LEN) - 1) << PDM_RX_TRG_LEVEL_POS)) -#define PDM_RX_DATA_MODE PDM_RX_DATA_MODE -#define PDM_RX_DATA_MODE_POS (24U) -#define PDM_RX_DATA_MODE_LEN (2U) -#define PDM_RX_DATA_MODE_MSK (((1U << PDM_RX_DATA_MODE_LEN) - 1) << PDM_RX_DATA_MODE_POS) -#define PDM_RX_DATA_MODE_UMSK (~(((1U << PDM_RX_DATA_MODE_LEN) - 1) << PDM_RX_DATA_MODE_POS)) - -/* 0xC84 : pdm_rx_fifo_status */ -#define PDM_RX_FIFO_STATUS_OFFSET (0xC84) -#define PDM_RXO_INT PDM_RXO_INT -#define PDM_RXO_INT_POS (1U) -#define PDM_RXO_INT_LEN (1U) -#define PDM_RXO_INT_MSK (((1U << PDM_RXO_INT_LEN) - 1) << PDM_RXO_INT_POS) -#define PDM_RXO_INT_UMSK (~(((1U << PDM_RXO_INT_LEN) - 1) << PDM_RXO_INT_POS)) -#define PDM_RXU_INT PDM_RXU_INT -#define PDM_RXU_INT_POS (2U) -#define PDM_RXU_INT_LEN (1U) -#define PDM_RXU_INT_MSK (((1U << PDM_RXU_INT_LEN) - 1) << PDM_RXU_INT_POS) -#define PDM_RXU_INT_UMSK (~(((1U << PDM_RXU_INT_LEN) - 1) << PDM_RXU_INT_POS)) -#define PDM_RXA_INT PDM_RXA_INT -#define PDM_RXA_INT_POS (4U) -#define PDM_RXA_INT_LEN (1U) -#define PDM_RXA_INT_MSK (((1U << PDM_RXA_INT_LEN) - 1) << PDM_RXA_INT_POS) -#define PDM_RXA_INT_UMSK (~(((1U << PDM_RXA_INT_LEN) - 1) << PDM_RXA_INT_POS)) -#define PDM_RXA_CNT PDM_RXA_CNT -#define PDM_RXA_CNT_POS (16U) -#define PDM_RXA_CNT_LEN (6U) -#define PDM_RXA_CNT_MSK (((1U << PDM_RXA_CNT_LEN) - 1) << PDM_RXA_CNT_POS) -#define PDM_RXA_CNT_UMSK (~(((1U << PDM_RXA_CNT_LEN) - 1) << PDM_RXA_CNT_POS)) -#define PDM_RXA PDM_RXA -#define PDM_RXA_POS (24U) -#define PDM_RXA_LEN (1U) -#define PDM_RXA_MSK (((1U << PDM_RXA_LEN) - 1) << PDM_RXA_POS) -#define PDM_RXA_UMSK (~(((1U << PDM_RXA_LEN) - 1) << PDM_RXA_POS)) - -/* 0xC88 : pdm_rx_fifo_data */ -#define PDM_RX_FIFO_DATA_OFFSET (0xC88) -#define PDM_RX_DATA PDM_RX_DATA -#define PDM_RX_DATA_POS (0U) -#define PDM_RX_DATA_LEN (32U) -#define PDM_RX_DATA_MSK (((1U << PDM_RX_DATA_LEN) - 1) << PDM_RX_DATA_POS) -#define PDM_RX_DATA_UMSK (~(((1U << PDM_RX_DATA_LEN) - 1) << PDM_RX_DATA_POS)) - -struct pdm_reg { - /* 0x0 reserved */ - uint8_t RESERVED0x0[3072]; - - /* 0xC00 : audpdm_top */ - union { - struct { - uint32_t audio_ckg_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1 : 1; /* [ 1], rsvd, 0x0 */ - uint32_t adc_itf_inv_sel : 1; /* [ 2], r/w, 0x0 */ - uint32_t pdm_itf_inv_sel : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_27 : 24; /* [27: 4], rsvd, 0x0 */ - uint32_t adc_rate : 3; /* [30:28], r/w, 0x1 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } audpdm_top; - - /* 0xC04 : audpdm_itf */ - union { - struct { - uint32_t adc_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_12 : 10; /* [12: 3], rsvd, 0x0 */ - uint32_t aud_rx0_sel : 3; /* [15:13], r/w, 0x0 */ - uint32_t aud_rx1_sel : 3; /* [18:16], r/w, 0x1 */ - uint32_t aud_rx2_sel : 3; /* [21:19], r/w, 0x2 */ - uint32_t reserved_22_29 : 8; /* [29:22], rsvd, 0x0 */ - uint32_t adc_itf_en : 1; /* [ 30], r/w, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } audpdm_itf; - - /* 0xC08 : pdm_adc_0 */ - union { - struct { - uint32_t adc_0_fir_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_1_fir_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_2_fir_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_scal : 6; /* [ 8: 3], r/w, 0x20 */ - uint32_t adc_1_scal : 6; /* [14: 9], r/w, 0x20 */ - uint32_t adc_2_scal : 6; /* [20:15], r/w, 0x20 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_0; - - /* 0xC0C : pdm_adc_1 */ - union { - struct { - uint32_t adc_0_k1 : 4; /* [ 3: 0], r/w, 0x8 */ - uint32_t adc_0_k1_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t adc_0_k2 : 4; /* [ 8: 5], r/w, 0xd */ - uint32_t adc_0_k2_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t adc_1_k1 : 4; /* [13:10], r/w, 0x8 */ - uint32_t adc_1_k1_en : 1; /* [ 14], r/w, 0x1 */ - uint32_t adc_1_k2 : 4; /* [18:15], r/w, 0xd */ - uint32_t adc_1_k2_en : 1; /* [ 19], r/w, 0x0 */ - uint32_t adc_2_k1 : 4; /* [23:20], r/w, 0x8 */ - uint32_t adc_2_k1_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t adc_2_k2 : 4; /* [28:25], r/w, 0xd */ - uint32_t adc_2_k2_en : 1; /* [ 29], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_1; - - /* 0xC10 : pdm_dac_0 */ - union { - struct { - uint32_t adc_pdm_h : 6; /* [ 5: 0], r/w, 0x1 */ - uint32_t adc_pdm_l : 6; /* [11: 6], r/w, 0x3f */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t adc_0_pdm_lvl_swap : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t adc_1_pdm_lvl_swap : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_18 : 2; /* [18:17], rsvd, 0x0 */ - uint32_t adc_2_pdm_lvl_swap : 1; /* [ 19], r/w, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dac_0; - - /* 0xc14 reserved */ - uint8_t RESERVED0xc14[8]; - - /* 0xC1C : pdm_pdm_0 */ - union { - struct { - uint32_t pdm_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t pdm_1_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t pdm_2_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_0_pdm_sel : 3; /* [ 5: 3], r/w, 0x0 */ - uint32_t adc_1_pdm_sel : 3; /* [ 8: 6], r/w, 0x1 */ - uint32_t adc_2_pdm_sel : 3; /* [11: 9], r/w, 0x2 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_pdm_0; - - /* 0xC20 : pdm_rsvd0 */ - union { - struct { - uint32_t rsvd0 : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } pdm_rsvd0; - - /* 0xC24 : pdm_dbg_0 */ - union { - struct { - uint32_t reserved_0_20 : 21; /* [20: 0], rsvd, 0x0 */ - uint32_t adc_test_clkin_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t reserved_22 : 1; /* [ 22], rsvd, 0x0 */ - uint32_t adc_test_din_en : 1; /* [ 23], r/w, 0x0 */ - uint32_t aud_test_read_sel : 6; /* [29:24], r/w, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_0; - - /* 0xC28 : pdm_dbg_1 */ - union { - struct { - uint32_t aud_test_read : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_1; - - /* 0xC2C : pdm_dbg_2 */ - union { - struct { - uint32_t adc_fir_4s_val : 20; /* [19: 0], r/w, 0x0 */ - uint32_t adc_0_fir_4s_en : 1; /* [ 20], r/w, 0x0 */ - uint32_t adc_1_fir_4s_en : 1; /* [ 21], r/w, 0x0 */ - uint32_t adc_2_fir_4s_en : 1; /* [ 22], r/w, 0x0 */ - uint32_t adc_in_0_test_sel : 1; /* [ 23], r/w, 0x0 */ - uint32_t adc_in_1_test_sel : 1; /* [ 24], r/w, 0x0 */ - uint32_t adc_in_2_test_sel : 1; /* [ 25], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_2; - - /* 0xC30 : pdm_dbg_3 */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_3; - - /* 0xC34 : pdm_dbg_4 */ - union { - struct { - uint32_t adc_in_ratio_4s_val : 1; /* [ 0], r/w, 0x0 */ - uint32_t adc_in_ch0_ratio_4s_val : 1; /* [ 1], r/w, 0x0 */ - uint32_t adc_in_ch1_ratio_4s_val : 1; /* [ 2], r/w, 0x0 */ - uint32_t adc_in_ch2_ratio_4s_val : 1; /* [ 3], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s_val : 1; /* [ 4], r/w, 0x0 */ - uint32_t pdm_in_ratio_4s : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_dbg_4; - - /* 0xC38 : pdm_adc_s0 */ - union { - struct { - uint32_t adc_s0_volume : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_s0; - - /* 0xC3C : pdm_adc_s1 */ - union { - struct { - uint32_t adc_s1_volume : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_s1; - - /* 0xC40 : pdm_adc_s2 */ - union { - struct { - uint32_t adc_s2_volume : 9; /* [ 8: 0], r/w, 0x0 */ - uint32_t reserved_9_31 : 23; /* [31: 9], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_adc_s2; - - /* 0xc44 reserved */ - uint8_t RESERVED0xc44[60]; - - /* 0xC80 : pdm_rx_fifo_ctrl */ - union { - struct { - uint32_t rx_fifo_flush : 1; /* [ 0], w1c, 0x0 */ - uint32_t rxo_int_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t rxu_int_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t rxa_int_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t rx_drq_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t rx_data_res : 1; /* [ 5], r/w, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_ch_en : 3; /* [10: 8], r/w, 0x0 */ - uint32_t reserved_11_13 : 3; /* [13:11], rsvd, 0x0 */ - uint32_t rx_drq_cnt : 2; /* [15:14], r/w, 0x0 */ - uint32_t rx_trg_level : 6; /* [21:16], r/w, 0x17 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t rx_data_mode : 2; /* [25:24], r/w, 0x0 */ - uint32_t reserved_26_31 : 6; /* [31:26], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_rx_fifo_ctrl; - - /* 0xC84 : pdm_rx_fifo_status */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t rxo_int : 1; /* [ 1], r, 0x0 */ - uint32_t rxu_int : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t rxa_int : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t rxa_cnt : 6; /* [21:16], r, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t rxa : 1; /* [ 24], r, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pdm_rx_fifo_status; - - /* 0xC88 : pdm_rx_fifo_data */ - union { - struct { - uint32_t rx_data : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } pdm_rx_fifo_data; -}; - -typedef volatile struct pdm_reg pdm_reg_t; - -#endif /* __PDM_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pwm_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pwm_reg.h deleted file mode 100644 index cd1d6bc6db..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pwm_reg.h +++ /dev/null @@ -1,1502 +0,0 @@ -/** - ****************************************************************************** - * @file pwm_reg.h - * @version V1.0 - * @date 2020-11-24 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __PWM_REG_H__ -#define __PWM_REG_H__ - -#include "bl808.h" - -/* 0x00 : pwm0_config0 */ -#define PWM0_CONFIG0_OFFSET (0x00) -#define PWM_CLK_DIV PWM_CLK_DIV -#define PWM_CLK_DIV_POS (0U) -#define PWM_CLK_DIV_LEN (16U) -#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) -#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) -#define PWM_STOP_ON_REPT PWM_STOP_ON_REPT -#define PWM_STOP_ON_REPT_POS (19U) -#define PWM_STOP_ON_REPT_LEN (1U) -#define PWM_STOP_ON_REPT_MSK (((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS) -#define PWM_STOP_ON_REPT_UMSK (~(((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS)) -#define PWM_ADC_TRG_SRC PWM_ADC_TRG_SRC -#define PWM_ADC_TRG_SRC_POS (20U) -#define PWM_ADC_TRG_SRC_LEN (4U) -#define PWM_ADC_TRG_SRC_MSK (((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS) -#define PWM_ADC_TRG_SRC_UMSK (~(((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS)) -#define PWM_SW_BREAK_EN PWM_SW_BREAK_EN -#define PWM_SW_BREAK_EN_POS (24U) -#define PWM_SW_BREAK_EN_LEN (1U) -#define PWM_SW_BREAK_EN_MSK (((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS) -#define PWM_SW_BREAK_EN_UMSK (~(((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS)) -#define PWM_EXT_BREAK_EN PWM_EXT_BREAK_EN -#define PWM_EXT_BREAK_EN_POS (25U) -#define PWM_EXT_BREAK_EN_LEN (1U) -#define PWM_EXT_BREAK_EN_MSK (((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS) -#define PWM_EXT_BREAK_EN_UMSK (~(((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS)) -#define PWM_EXT_BREAK_PL PWM_EXT_BREAK_PL -#define PWM_EXT_BREAK_PL_POS (26U) -#define PWM_EXT_BREAK_PL_LEN (1U) -#define PWM_EXT_BREAK_PL_MSK (((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS) -#define PWM_EXT_BREAK_PL_UMSK (~(((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS)) -#define PWM_STOP_EN PWM_STOP_EN -#define PWM_STOP_EN_POS (27U) -#define PWM_STOP_EN_LEN (1U) -#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) -#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) -#define PWM_STOP_MODE PWM_STOP_MODE -#define PWM_STOP_MODE_POS (28U) -#define PWM_STOP_MODE_LEN (1U) -#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) -#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) -#define PWM_STS_STOP PWM_STS_STOP -#define PWM_STS_STOP_POS (29U) -#define PWM_STS_STOP_LEN (1U) -#define PWM_STS_STOP_MSK (((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS) -#define PWM_STS_STOP_UMSK (~(((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS)) -#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL -#define PWM_REG_CLK_SEL_POS (30U) -#define PWM_REG_CLK_SEL_LEN (2U) -#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) -#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) - -/* 0x04 : pwm0_config1 */ -#define PWM0_CONFIG1_OFFSET (0x04) -#define PWM_CH0_PEN PWM_CH0_PEN -#define PWM_CH0_PEN_POS (0U) -#define PWM_CH0_PEN_LEN (1U) -#define PWM_CH0_PEN_MSK (((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS) -#define PWM_CH0_PEN_UMSK (~(((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS)) -#define PWM_CH0_PSI PWM_CH0_PSI -#define PWM_CH0_PSI_POS (1U) -#define PWM_CH0_PSI_LEN (1U) -#define PWM_CH0_PSI_MSK (((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS) -#define PWM_CH0_PSI_UMSK (~(((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS)) -#define PWM_CH0_NEN PWM_CH0_NEN -#define PWM_CH0_NEN_POS (2U) -#define PWM_CH0_NEN_LEN (1U) -#define PWM_CH0_NEN_MSK (((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS) -#define PWM_CH0_NEN_UMSK (~(((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS)) -#define PWM_CH0_NSI PWM_CH0_NSI -#define PWM_CH0_NSI_POS (3U) -#define PWM_CH0_NSI_LEN (1U) -#define PWM_CH0_NSI_MSK (((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS) -#define PWM_CH0_NSI_UMSK (~(((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS)) -#define PWM_CH1_PEN PWM_CH1_PEN -#define PWM_CH1_PEN_POS (4U) -#define PWM_CH1_PEN_LEN (1U) -#define PWM_CH1_PEN_MSK (((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS) -#define PWM_CH1_PEN_UMSK (~(((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS)) -#define PWM_CH1_PSI PWM_CH1_PSI -#define PWM_CH1_PSI_POS (5U) -#define PWM_CH1_PSI_LEN (1U) -#define PWM_CH1_PSI_MSK (((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS) -#define PWM_CH1_PSI_UMSK (~(((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS)) -#define PWM_CH1_NEN PWM_CH1_NEN -#define PWM_CH1_NEN_POS (6U) -#define PWM_CH1_NEN_LEN (1U) -#define PWM_CH1_NEN_MSK (((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS) -#define PWM_CH1_NEN_UMSK (~(((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS)) -#define PWM_CH1_NSI PWM_CH1_NSI -#define PWM_CH1_NSI_POS (7U) -#define PWM_CH1_NSI_LEN (1U) -#define PWM_CH1_NSI_MSK (((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS) -#define PWM_CH1_NSI_UMSK (~(((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS)) -#define PWM_CH2_PEN PWM_CH2_PEN -#define PWM_CH2_PEN_POS (8U) -#define PWM_CH2_PEN_LEN (1U) -#define PWM_CH2_PEN_MSK (((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS) -#define PWM_CH2_PEN_UMSK (~(((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS)) -#define PWM_CH2_PSI PWM_CH2_PSI -#define PWM_CH2_PSI_POS (9U) -#define PWM_CH2_PSI_LEN (1U) -#define PWM_CH2_PSI_MSK (((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS) -#define PWM_CH2_PSI_UMSK (~(((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS)) -#define PWM_CH2_NEN PWM_CH2_NEN -#define PWM_CH2_NEN_POS (10U) -#define PWM_CH2_NEN_LEN (1U) -#define PWM_CH2_NEN_MSK (((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS) -#define PWM_CH2_NEN_UMSK (~(((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS)) -#define PWM_CH2_NSI PWM_CH2_NSI -#define PWM_CH2_NSI_POS (11U) -#define PWM_CH2_NSI_LEN (1U) -#define PWM_CH2_NSI_MSK (((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS) -#define PWM_CH2_NSI_UMSK (~(((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS)) -#define PWM_CH3_PEN PWM_CH3_PEN -#define PWM_CH3_PEN_POS (12U) -#define PWM_CH3_PEN_LEN (1U) -#define PWM_CH3_PEN_MSK (((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS) -#define PWM_CH3_PEN_UMSK (~(((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS)) -#define PWM_CH3_PSI PWM_CH3_PSI -#define PWM_CH3_PSI_POS (13U) -#define PWM_CH3_PSI_LEN (1U) -#define PWM_CH3_PSI_MSK (((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS) -#define PWM_CH3_PSI_UMSK (~(((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS)) -#define PWM_CH3_NEN PWM_CH3_NEN -#define PWM_CH3_NEN_POS (14U) -#define PWM_CH3_NEN_LEN (1U) -#define PWM_CH3_NEN_MSK (((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS) -#define PWM_CH3_NEN_UMSK (~(((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS)) -#define PWM_CH3_NSI PWM_CH3_NSI -#define PWM_CH3_NSI_POS (15U) -#define PWM_CH3_NSI_LEN (1U) -#define PWM_CH3_NSI_MSK (((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS) -#define PWM_CH3_NSI_UMSK (~(((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS)) -#define PWM_CH0_PPL PWM_CH0_PPL -#define PWM_CH0_PPL_POS (16U) -#define PWM_CH0_PPL_LEN (1U) -#define PWM_CH0_PPL_MSK (((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS) -#define PWM_CH0_PPL_UMSK (~(((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS)) -#define PWM_CH0_NPL PWM_CH0_NPL -#define PWM_CH0_NPL_POS (17U) -#define PWM_CH0_NPL_LEN (1U) -#define PWM_CH0_NPL_MSK (((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS) -#define PWM_CH0_NPL_UMSK (~(((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS)) -#define PWM_CH1_PPL PWM_CH1_PPL -#define PWM_CH1_PPL_POS (18U) -#define PWM_CH1_PPL_LEN (1U) -#define PWM_CH1_PPL_MSK (((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS) -#define PWM_CH1_PPL_UMSK (~(((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS)) -#define PWM_CH1_NPL PWM_CH1_NPL -#define PWM_CH1_NPL_POS (19U) -#define PWM_CH1_NPL_LEN (1U) -#define PWM_CH1_NPL_MSK (((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS) -#define PWM_CH1_NPL_UMSK (~(((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS)) -#define PWM_CH2_PPL PWM_CH2_PPL -#define PWM_CH2_PPL_POS (20U) -#define PWM_CH2_PPL_LEN (1U) -#define PWM_CH2_PPL_MSK (((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS) -#define PWM_CH2_PPL_UMSK (~(((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS)) -#define PWM_CH2_NPL PWM_CH2_NPL -#define PWM_CH2_NPL_POS (21U) -#define PWM_CH2_NPL_LEN (1U) -#define PWM_CH2_NPL_MSK (((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS) -#define PWM_CH2_NPL_UMSK (~(((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS)) -#define PWM_CH3_PPL PWM_CH3_PPL -#define PWM_CH3_PPL_POS (22U) -#define PWM_CH3_PPL_LEN (1U) -#define PWM_CH3_PPL_MSK (((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS) -#define PWM_CH3_PPL_UMSK (~(((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS)) -#define PWM_CH3_NPL PWM_CH3_NPL -#define PWM_CH3_NPL_POS (23U) -#define PWM_CH3_NPL_LEN (1U) -#define PWM_CH3_NPL_MSK (((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS) -#define PWM_CH3_NPL_UMSK (~(((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS)) -#define PWM_CH0_PBS PWM_CH0_PBS -#define PWM_CH0_PBS_POS (24U) -#define PWM_CH0_PBS_LEN (1U) -#define PWM_CH0_PBS_MSK (((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS) -#define PWM_CH0_PBS_UMSK (~(((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS)) -#define PWM_CH0_NBS PWM_CH0_NBS -#define PWM_CH0_NBS_POS (25U) -#define PWM_CH0_NBS_LEN (1U) -#define PWM_CH0_NBS_MSK (((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS) -#define PWM_CH0_NBS_UMSK (~(((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS)) -#define PWM_CH1_PBS PWM_CH1_PBS -#define PWM_CH1_PBS_POS (26U) -#define PWM_CH1_PBS_LEN (1U) -#define PWM_CH1_PBS_MSK (((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS) -#define PWM_CH1_PBS_UMSK (~(((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS)) -#define PWM_CH1_NBS PWM_CH1_NBS -#define PWM_CH1_NBS_POS (27U) -#define PWM_CH1_NBS_LEN (1U) -#define PWM_CH1_NBS_MSK (((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS) -#define PWM_CH1_NBS_UMSK (~(((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS)) -#define PWM_CH2_PBS PWM_CH2_PBS -#define PWM_CH2_PBS_POS (28U) -#define PWM_CH2_PBS_LEN (1U) -#define PWM_CH2_PBS_MSK (((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS) -#define PWM_CH2_PBS_UMSK (~(((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS)) -#define PWM_CH2_NBS PWM_CH2_NBS -#define PWM_CH2_NBS_POS (29U) -#define PWM_CH2_NBS_LEN (1U) -#define PWM_CH2_NBS_MSK (((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS) -#define PWM_CH2_NBS_UMSK (~(((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS)) -#define PWM_CH3_PBS PWM_CH3_PBS -#define PWM_CH3_PBS_POS (30U) -#define PWM_CH3_PBS_LEN (1U) -#define PWM_CH3_PBS_MSK (((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS) -#define PWM_CH3_PBS_UMSK (~(((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS)) -#define PWM_CH3_NBS PWM_CH3_NBS -#define PWM_CH3_NBS_POS (31U) -#define PWM_CH3_NBS_LEN (1U) -#define PWM_CH3_NBS_MSK (((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS) -#define PWM_CH3_NBS_UMSK (~(((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS)) -/* 0x08 : pwm0_period */ -#define PWM0_PERIOD_OFFSET (0x08) -#define PWM_PERIOD PWM_PERIOD -#define PWM_PERIOD_POS (0U) -#define PWM_PERIOD_LEN (16U) -#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) -#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) -#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT -#define PWM_INT_PERIOD_CNT_POS (16U) -#define PWM_INT_PERIOD_CNT_LEN (16U) -#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) -#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) - -/* 0x0C : pwm0_dead_time */ -#define PWM0_DEAD_TIME_OFFSET (0x0C) -#define PWM_CH0_DTG PWM_CH0_DTG -#define PWM_CH0_DTG_POS (0U) -#define PWM_CH0_DTG_LEN (8U) -#define PWM_CH0_DTG_MSK (((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS) -#define PWM_CH0_DTG_UMSK (~(((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS)) -#define PWM_CH1_DTG PWM_CH1_DTG -#define PWM_CH1_DTG_POS (8U) -#define PWM_CH1_DTG_LEN (8U) -#define PWM_CH1_DTG_MSK (((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS) -#define PWM_CH1_DTG_UMSK (~(((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS)) -#define PWM_CH2_DTG PWM_CH2_DTG -#define PWM_CH2_DTG_POS (16U) -#define PWM_CH2_DTG_LEN (8U) -#define PWM_CH2_DTG_MSK (((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS) -#define PWM_CH2_DTG_UMSK (~(((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS)) -#define PWM_CH3_DTG PWM_CH3_DTG -#define PWM_CH3_DTG_POS (24U) -#define PWM_CH3_DTG_LEN (8U) -#define PWM_CH3_DTG_MSK (((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS) -#define PWM_CH3_DTG_UMSK (~(((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS)) - -/* 0x10 : pwm0_ch0_thre */ -#define PWM0_CH0_THRE_OFFSET (0x10) -#define PWM_CH0_THREL PWM_CH0_THREL -#define PWM_CH0_THREL_POS (0U) -#define PWM_CH0_THREL_LEN (16U) -#define PWM_CH0_THREL_MSK (((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS) -#define PWM_CH0_THREL_UMSK (~(((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS)) -#define PWM_CH0_THREH PWM_CH0_THREH -#define PWM_CH0_THREH_POS (16U) -#define PWM_CH0_THREH_LEN (16U) -#define PWM_CH0_THREH_MSK (((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS) -#define PWM_CH0_THREH_UMSK (~(((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS)) - -/* 0x14 : pwm0_ch1_thre */ -#define PWM0_CH1_THRE_OFFSET (0x14) -#define PWM_CH1_THREL PWM_CH1_THREL -#define PWM_CH1_THREL_POS (0U) -#define PWM_CH1_THREL_LEN (16U) -#define PWM_CH1_THREL_MSK (((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS) -#define PWM_CH1_THREL_UMSK (~(((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS)) -#define PWM_CH1_THREH PWM_CH1_THREH -#define PWM_CH1_THREH_POS (16U) -#define PWM_CH1_THREH_LEN (16U) -#define PWM_CH1_THREH_MSK (((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS) -#define PWM_CH1_THREH_UMSK (~(((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS)) - -/* 0x18 : pwm0_ch2_thre */ -#define PWM0_CH2_THRE_OFFSET (0x18) -#define PWM_CH2_THREL PWM_CH2_THREL -#define PWM_CH2_THREL_POS (0U) -#define PWM_CH2_THREL_LEN (16U) -#define PWM_CH2_THREL_MSK (((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS) -#define PWM_CH2_THREL_UMSK (~(((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS)) -#define PWM_CH2_THREH PWM_CH2_THREH -#define PWM_CH2_THREH_POS (16U) -#define PWM_CH2_THREH_LEN (16U) -#define PWM_CH2_THREH_MSK (((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS) -#define PWM_CH2_THREH_UMSK (~(((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS)) - -/* 0x1C : pwm0_ch3_thre */ -#define PWM0_CH3_THRE_OFFSET (0x1C) -#define PWM_CH3_THREL PWM_CH3_THREL -#define PWM_CH3_THREL_POS (0U) -#define PWM_CH3_THREL_LEN (16U) -#define PWM_CH3_THREL_MSK (((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS) -#define PWM_CH3_THREL_UMSK (~(((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS)) -#define PWM_CH3_THREH PWM_CH3_THREH -#define PWM_CH3_THREH_POS (16U) -#define PWM_CH3_THREH_LEN (16U) -#define PWM_CH3_THREH_MSK (((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS) -#define PWM_CH3_THREH_UMSK (~(((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS)) - -/* 0x20 : pwm0_int_sts */ -#define PWM0_INT_STS_OFFSET (0x20) -#define PWM_CH0L_INT PWM_CH0L_INT -#define PWM_CH0L_INT_POS (0U) -#define PWM_CH0L_INT_LEN (1U) -#define PWM_CH0L_INT_MSK (((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS) -#define PWM_CH0L_INT_UMSK (~(((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS)) -#define PWM_CH0H_INT PWM_CH0H_INT -#define PWM_CH0H_INT_POS (1U) -#define PWM_CH0H_INT_LEN (1U) -#define PWM_CH0H_INT_MSK (((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS) -#define PWM_CH0H_INT_UMSK (~(((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS)) -#define PWM_CH1L_INT PWM_CH1L_INT -#define PWM_CH1L_INT_POS (2U) -#define PWM_CH1L_INT_LEN (1U) -#define PWM_CH1L_INT_MSK (((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS) -#define PWM_CH1L_INT_UMSK (~(((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS)) -#define PWM_CH1H_INT PWM_CH1H_INT -#define PWM_CH1H_INT_POS (3U) -#define PWM_CH1H_INT_LEN (1U) -#define PWM_CH1H_INT_MSK (((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS) -#define PWM_CH1H_INT_UMSK (~(((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS)) -#define PWM_CH2L_INT PWM_CH2L_INT -#define PWM_CH2L_INT_POS (4U) -#define PWM_CH2L_INT_LEN (1U) -#define PWM_CH2L_INT_MSK (((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS) -#define PWM_CH2L_INT_UMSK (~(((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS)) -#define PWM_CH2H_INT PWM_CH2H_INT -#define PWM_CH2H_INT_POS (5U) -#define PWM_CH2H_INT_LEN (1U) -#define PWM_CH2H_INT_MSK (((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS) -#define PWM_CH2H_INT_UMSK (~(((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS)) -#define PWM_CH3L_INT PWM_CH3L_INT -#define PWM_CH3L_INT_POS (6U) -#define PWM_CH3L_INT_LEN (1U) -#define PWM_CH3L_INT_MSK (((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS) -#define PWM_CH3L_INT_UMSK (~(((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS)) -#define PWM_CH3H_INT PWM_CH3H_INT -#define PWM_CH3H_INT_POS (7U) -#define PWM_CH3H_INT_LEN (1U) -#define PWM_CH3H_INT_MSK (((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS) -#define PWM_CH3H_INT_UMSK (~(((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS)) -#define PWM_PRDE_INT PWM_PRDE_INT -#define PWM_PRDE_INT_POS (8U) -#define PWM_PRDE_INT_LEN (1U) -#define PWM_PRDE_INT_MSK (((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS) -#define PWM_PRDE_INT_UMSK (~(((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS)) -#define PWM_BRK_INT PWM_BRK_INT -#define PWM_BRK_INT_POS (9U) -#define PWM_BRK_INT_LEN (1U) -#define PWM_BRK_INT_MSK (((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS) -#define PWM_BRK_INT_UMSK (~(((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS)) -#define PWM_REPT_INT PWM_REPT_INT -#define PWM_REPT_INT_POS (10U) -#define PWM_REPT_INT_LEN (1U) -#define PWM_REPT_INT_MSK (((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS) -#define PWM_REPT_INT_UMSK (~(((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS)) - -/* 0x24 : pwm0_int_mask */ -#define PWM0_INT_MASK_OFFSET (0x24) -#define PWM_CR_PWM_CH0L_MASK PWM_CR_PWM_CH0L_MASK -#define PWM_CR_PWM_CH0L_MASK_POS (0U) -#define PWM_CR_PWM_CH0L_MASK_LEN (1U) -#define PWM_CR_PWM_CH0L_MASK_MSK (((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS) -#define PWM_CR_PWM_CH0L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS)) -#define PWM_CR_PWM_CH0H_MASK PWM_CR_PWM_CH0H_MASK -#define PWM_CR_PWM_CH0H_MASK_POS (1U) -#define PWM_CR_PWM_CH0H_MASK_LEN (1U) -#define PWM_CR_PWM_CH0H_MASK_MSK (((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS) -#define PWM_CR_PWM_CH0H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS)) -#define PWM_CR_PWM_CH1L_MASK PWM_CR_PWM_CH1L_MASK -#define PWM_CR_PWM_CH1L_MASK_POS (2U) -#define PWM_CR_PWM_CH1L_MASK_LEN (1U) -#define PWM_CR_PWM_CH1L_MASK_MSK (((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS) -#define PWM_CR_PWM_CH1L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS)) -#define PWM_CR_PWM_CH1H_MASK PWM_CR_PWM_CH1H_MASK -#define PWM_CR_PWM_CH1H_MASK_POS (3U) -#define PWM_CR_PWM_CH1H_MASK_LEN (1U) -#define PWM_CR_PWM_CH1H_MASK_MSK (((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS) -#define PWM_CR_PWM_CH1H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS)) -#define PWM_CR_PWM_CH2L_MASK PWM_CR_PWM_CH2L_MASK -#define PWM_CR_PWM_CH2L_MASK_POS (4U) -#define PWM_CR_PWM_CH2L_MASK_LEN (1U) -#define PWM_CR_PWM_CH2L_MASK_MSK (((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS) -#define PWM_CR_PWM_CH2L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS)) -#define PWM_CR_PWM_CH2H_MASK PWM_CR_PWM_CH2H_MASK -#define PWM_CR_PWM_CH2H_MASK_POS (5U) -#define PWM_CR_PWM_CH2H_MASK_LEN (1U) -#define PWM_CR_PWM_CH2H_MASK_MSK (((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS) -#define PWM_CR_PWM_CH2H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS)) -#define PWM_CR_PWM_CH3L_MASK PWM_CR_PWM_CH3L_MASK -#define PWM_CR_PWM_CH3L_MASK_POS (6U) -#define PWM_CR_PWM_CH3L_MASK_LEN (1U) -#define PWM_CR_PWM_CH3L_MASK_MSK (((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS) -#define PWM_CR_PWM_CH3L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS)) -#define PWM_CR_PWM_CH3H_MASK PWM_CR_PWM_CH3H_MASK -#define PWM_CR_PWM_CH3H_MASK_POS (7U) -#define PWM_CR_PWM_CH3H_MASK_LEN (1U) -#define PWM_CR_PWM_CH3H_MASK_MSK (((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS) -#define PWM_CR_PWM_CH3H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS)) -#define PWM_CR_PWM_PRDE_MASK PWM_CR_PWM_PRDE_MASK -#define PWM_CR_PWM_PRDE_MASK_POS (8U) -#define PWM_CR_PWM_PRDE_MASK_LEN (1U) -#define PWM_CR_PWM_PRDE_MASK_MSK (((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS) -#define PWM_CR_PWM_PRDE_MASK_UMSK (~(((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS)) -#define PWM_CR_PWM_BRK_MASK PWM_CR_PWM_BRK_MASK -#define PWM_CR_PWM_BRK_MASK_POS (9U) -#define PWM_CR_PWM_BRK_MASK_LEN (1U) -#define PWM_CR_PWM_BRK_MASK_MSK (((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS) -#define PWM_CR_PWM_BRK_MASK_UMSK (~(((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS)) -#define PWM_CR_PWM_REPT_MASK PWM_CR_PWM_REPT_MASK -#define PWM_CR_PWM_REPT_MASK_POS (10U) -#define PWM_CR_PWM_REPT_MASK_LEN (1U) -#define PWM_CR_PWM_REPT_MASK_MSK (((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS) -#define PWM_CR_PWM_REPT_MASK_UMSK (~(((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS)) - -/* 0x28 : pwm0_int_clear */ -#define PWM0_INT_CLEAR_OFFSET (0x28) -#define PWM_CR_PWM_CH0L_CLR PWM_CR_PWM_CH0L_CLR -#define PWM_CR_PWM_CH0L_CLR_POS (0U) -#define PWM_CR_PWM_CH0L_CLR_LEN (1U) -#define PWM_CR_PWM_CH0L_CLR_MSK (((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS) -#define PWM_CR_PWM_CH0L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS)) -#define PWM_CR_PWM_CH0H_CLR PWM_CR_PWM_CH0H_CLR -#define PWM_CR_PWM_CH0H_CLR_POS (1U) -#define PWM_CR_PWM_CH0H_CLR_LEN (1U) -#define PWM_CR_PWM_CH0H_CLR_MSK (((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS) -#define PWM_CR_PWM_CH0H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS)) -#define PWM_CR_PWM_CH1L_CLR PWM_CR_PWM_CH1L_CLR -#define PWM_CR_PWM_CH1L_CLR_POS (2U) -#define PWM_CR_PWM_CH1L_CLR_LEN (1U) -#define PWM_CR_PWM_CH1L_CLR_MSK (((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS) -#define PWM_CR_PWM_CH1L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS)) -#define PWM_CR_PWM_CH1H_CLR PWM_CR_PWM_CH1H_CLR -#define PWM_CR_PWM_CH1H_CLR_POS (3U) -#define PWM_CR_PWM_CH1H_CLR_LEN (1U) -#define PWM_CR_PWM_CH1H_CLR_MSK (((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS) -#define PWM_CR_PWM_CH1H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS)) -#define PWM_CR_PWM_CH2L_CLR PWM_CR_PWM_CH2L_CLR -#define PWM_CR_PWM_CH2L_CLR_POS (4U) -#define PWM_CR_PWM_CH2L_CLR_LEN (1U) -#define PWM_CR_PWM_CH2L_CLR_MSK (((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS) -#define PWM_CR_PWM_CH2L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS)) -#define PWM_CR_PWM_CH2H_CLR PWM_CR_PWM_CH2H_CLR -#define PWM_CR_PWM_CH2H_CLR_POS (5U) -#define PWM_CR_PWM_CH2H_CLR_LEN (1U) -#define PWM_CR_PWM_CH2H_CLR_MSK (((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS) -#define PWM_CR_PWM_CH2H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS)) -#define PWM_CR_PWM_CH3L_CLR PWM_CR_PWM_CH3L_CLR -#define PWM_CR_PWM_CH3L_CLR_POS (6U) -#define PWM_CR_PWM_CH3L_CLR_LEN (1U) -#define PWM_CR_PWM_CH3L_CLR_MSK (((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS) -#define PWM_CR_PWM_CH3L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS)) -#define PWM_CR_PWM_CH3H_CLR PWM_CR_PWM_CH3H_CLR -#define PWM_CR_PWM_CH3H_CLR_POS (7U) -#define PWM_CR_PWM_CH3H_CLR_LEN (1U) -#define PWM_CR_PWM_CH3H_CLR_MSK (((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS) -#define PWM_CR_PWM_CH3H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS)) -#define PWM_CR_PWM_PRDE_CLR PWM_CR_PWM_PRDE_CLR -#define PWM_CR_PWM_PRDE_CLR_POS (8U) -#define PWM_CR_PWM_PRDE_CLR_LEN (1U) -#define PWM_CR_PWM_PRDE_CLR_MSK (((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS) -#define PWM_CR_PWM_PRDE_CLR_UMSK (~(((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS)) -#define PWM_CR_PWM_BRK_CLR PWM_CR_PWM_BRK_CLR -#define PWM_CR_PWM_BRK_CLR_POS (9U) -#define PWM_CR_PWM_BRK_CLR_LEN (1U) -#define PWM_CR_PWM_BRK_CLR_MSK (((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS) -#define PWM_CR_PWM_BRK_CLR_UMSK (~(((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS)) -#define PWM_CR_PWM_REPT_CLR PWM_CR_PWM_REPT_CLR -#define PWM_CR_PWM_REPT_CLR_POS (10U) -#define PWM_CR_PWM_REPT_CLR_LEN (1U) -#define PWM_CR_PWM_REPT_CLR_MSK (((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS) -#define PWM_CR_PWM_REPT_CLR_UMSK (~(((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS)) - -/* 0x2C : pwm0_int_en */ -#define PWM0_INT_EN_OFFSET (0x2C) -#define PWM_CR_PWM_CH0L_EN PWM_CR_PWM_CH0L_EN -#define PWM_CR_PWM_CH0L_EN_POS (0U) -#define PWM_CR_PWM_CH0L_EN_LEN (1U) -#define PWM_CR_PWM_CH0L_EN_MSK (((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS) -#define PWM_CR_PWM_CH0L_EN_UMSK (~(((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS)) -#define PWM_CR_PWM_CH0H_EN PWM_CR_PWM_CH0H_EN -#define PWM_CR_PWM_CH0H_EN_POS (1U) -#define PWM_CR_PWM_CH0H_EN_LEN (1U) -#define PWM_CR_PWM_CH0H_EN_MSK (((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS) -#define PWM_CR_PWM_CH0H_EN_UMSK (~(((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS)) -#define PWM_CR_PWM_CH1L_EN PWM_CR_PWM_CH1L_EN -#define PWM_CR_PWM_CH1L_EN_POS (2U) -#define PWM_CR_PWM_CH1L_EN_LEN (1U) -#define PWM_CR_PWM_CH1L_EN_MSK (((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS) -#define PWM_CR_PWM_CH1L_EN_UMSK (~(((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS)) -#define PWM_CR_PWM_CH1H_EN PWM_CR_PWM_CH1H_EN -#define PWM_CR_PWM_CH1H_EN_POS (3U) -#define PWM_CR_PWM_CH1H_EN_LEN (1U) -#define PWM_CR_PWM_CH1H_EN_MSK (((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS) -#define PWM_CR_PWM_CH1H_EN_UMSK (~(((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS)) -#define PWM_CR_PWM_CH2L_EN PWM_CR_PWM_CH2L_EN -#define PWM_CR_PWM_CH2L_EN_POS (4U) -#define PWM_CR_PWM_CH2L_EN_LEN (1U) -#define PWM_CR_PWM_CH2L_EN_MSK (((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS) -#define PWM_CR_PWM_CH2L_EN_UMSK (~(((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS)) -#define PWM_CR_PWM_CH2H_EN PWM_CR_PWM_CH2H_EN -#define PWM_CR_PWM_CH2H_EN_POS (5U) -#define PWM_CR_PWM_CH2H_EN_LEN (1U) -#define PWM_CR_PWM_CH2H_EN_MSK (((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS) -#define PWM_CR_PWM_CH2H_EN_UMSK (~(((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS)) -#define PWM_CR_PWM_CH3L_EN PWM_CR_PWM_CH3L_EN -#define PWM_CR_PWM_CH3L_EN_POS (6U) -#define PWM_CR_PWM_CH3L_EN_LEN (1U) -#define PWM_CR_PWM_CH3L_EN_MSK (((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS) -#define PWM_CR_PWM_CH3L_EN_UMSK (~(((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS)) -#define PWM_CR_PWM_CH3H_EN PWM_CR_PWM_CH3H_EN -#define PWM_CR_PWM_CH3H_EN_POS (7U) -#define PWM_CR_PWM_CH3H_EN_LEN (1U) -#define PWM_CR_PWM_CH3H_EN_MSK (((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS) -#define PWM_CR_PWM_CH3H_EN_UMSK (~(((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS)) -#define PWM_CR_PWM_PRDE_EN PWM_CR_PWM_PRDE_EN -#define PWM_CR_PWM_PRDE_EN_POS (8U) -#define PWM_CR_PWM_PRDE_EN_LEN (1U) -#define PWM_CR_PWM_PRDE_EN_MSK (((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS) -#define PWM_CR_PWM_PRDE_EN_UMSK (~(((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS)) -#define PWM_CR_PWM_BRK_EN PWM_CR_PWM_BRK_EN -#define PWM_CR_PWM_BRK_EN_POS (9U) -#define PWM_CR_PWM_BRK_EN_LEN (1U) -#define PWM_CR_PWM_BRK_EN_MSK (((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS) -#define PWM_CR_PWM_BRK_EN_UMSK (~(((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS)) -#define PWM_CR_PWM_REPT_EN PWM_CR_PWM_REPT_EN -#define PWM_CR_PWM_REPT_EN_POS (10U) -#define PWM_CR_PWM_REPT_EN_LEN (1U) -#define PWM_CR_PWM_REPT_EN_MSK (((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS) -#define PWM_CR_PWM_REPT_EN_UMSK (~(((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS)) - -struct pwm_reg { - /* 0x00 : pwm0_config0 */ - union { - struct { - uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_18 : 3; /* [18:16], rsvd, 0x0 */ - uint32_t pwm_stop_on_rept : 1; /* [ 19], r/w, 0x0 */ - uint32_t pwm_adc_trg_src : 4; /* [23:20], r/w, 0xf */ - uint32_t pwm_sw_break_en : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ext_break_en : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ext_break_pl : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_stop_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_stop_mode : 1; /* [ 28], r/w, 0x1 */ - uint32_t pwm_sts_stop : 1; /* [ 29], r, 0x0 */ - uint32_t reg_clk_sel : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_config0; - - /* 0x04 : pwm0_config1 */ - union { - struct { - uint32_t pwm_ch0_pen : 1; /* [ 0], r/w, 0x0 */ - uint32_t pwm_ch0_psi : 1; /* [ 1], r/w, 0x0 */ - uint32_t pwm_ch0_nen : 1; /* [ 2], r/w, 0x0 */ - uint32_t pwm_ch0_nsi : 1; /* [ 3], r/w, 0x1 */ - uint32_t pwm_ch1_pen : 1; /* [ 4], r/w, 0x0 */ - uint32_t pwm_ch1_psi : 1; /* [ 5], r/w, 0x0 */ - uint32_t pwm_ch1_nen : 1; /* [ 6], r/w, 0x0 */ - uint32_t pwm_ch1_nsi : 1; /* [ 7], r/w, 0x1 */ - uint32_t pwm_ch2_pen : 1; /* [ 8], r/w, 0x0 */ - uint32_t pwm_ch2_psi : 1; /* [ 9], r/w, 0x0 */ - uint32_t pwm_ch2_nen : 1; /* [ 10], r/w, 0x0 */ - uint32_t pwm_ch2_nsi : 1; /* [ 11], r/w, 0x1 */ - uint32_t pwm_ch3_pen : 1; /* [ 12], r/w, 0x0 */ - uint32_t pwm_ch3_psi : 1; /* [ 13], r/w, 0x0 */ - uint32_t pwm_ch3_nen : 1; /* [ 14], r/w, 0x0 */ - uint32_t pwm_ch3_nsi : 1; /* [ 15], r/w, 0x1 */ - uint32_t pwm_ch0_ppl : 1; /* [ 16], r/w, 0x1 */ - uint32_t pwm_ch0_npl : 1; /* [ 17], r/w, 0x1 */ - uint32_t pwm_ch1_ppl : 1; /* [ 18], r/w, 0x1 */ - uint32_t pwm_ch1_npl : 1; /* [ 19], r/w, 0x1 */ - uint32_t pwm_ch2_ppl : 1; /* [ 20], r/w, 0x1 */ - uint32_t pwm_ch2_npl : 1; /* [ 21], r/w, 0x1 */ - uint32_t pwm_ch3_ppl : 1; /* [ 22], r/w, 0x1 */ - uint32_t pwm_ch3_npl : 1; /* [ 23], r/w, 0x1 */ - uint32_t pwm_ch0_pbs : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ch0_nbs : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ch1_pbs : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_ch1_nbs : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_ch2_pbs : 1; /* [ 28], r/w, 0x0 */ - uint32_t pwm_ch2_nbs : 1; /* [ 29], r/w, 0x0 */ - uint32_t pwm_ch3_pbs : 1; /* [ 30], r/w, 0x0 */ - uint32_t pwm_ch3_nbs : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_config1; - - /* 0x08 : pwm0_period */ - union { - struct { - uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_int_period_cnt : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_period; - - /* 0x0C : pwm0_dead_time */ - union { - struct { - uint32_t pwm_ch0_dtg : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t pwm_ch1_dtg : 8; /* [15: 8], r/w, 0x0 */ - uint32_t pwm_ch2_dtg : 8; /* [23:16], r/w, 0x0 */ - uint32_t pwm_ch3_dtg : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_dead_time; - - /* 0x10 : pwm0_ch0_thre */ - union { - struct { - uint32_t pwm_ch0_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch0_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch0_thre; - - /* 0x14 : pwm0_ch1_thre */ - union { - struct { - uint32_t pwm_ch1_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch1_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch1_thre; - - /* 0x18 : pwm0_ch2_thre */ - union { - struct { - uint32_t pwm_ch2_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch2_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch2_thre; - - /* 0x1C : pwm0_ch3_thre */ - union { - struct { - uint32_t pwm_ch3_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch3_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_ch3_thre; - - /* 0x20 : pwm0_int_sts */ - union { - struct { - uint32_t pwm_ch0l_int : 1; /* [ 0], r, 0x0 */ - uint32_t pwm_ch0h_int : 1; /* [ 1], r, 0x0 */ - uint32_t pwm_ch1l_int : 1; /* [ 2], r, 0x0 */ - uint32_t pwm_ch1h_int : 1; /* [ 3], r, 0x0 */ - uint32_t pwm_ch2l_int : 1; /* [ 4], r, 0x0 */ - uint32_t pwm_ch2h_int : 1; /* [ 5], r, 0x0 */ - uint32_t pwm_ch3l_int : 1; /* [ 6], r, 0x0 */ - uint32_t pwm_ch3h_int : 1; /* [ 7], r, 0x0 */ - uint32_t pwm_prde_int : 1; /* [ 8], r, 0x0 */ - uint32_t pwm_brk_int : 1; /* [ 9], r, 0x0 */ - uint32_t pwm_rept_int : 1; /* [ 10], r, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_sts; - - /* 0x24 : pwm0_int_mask */ - union { - struct { - uint32_t cr_pwm_ch0l_mask : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_mask : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_mask : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_mask : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_mask : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_mask : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_mask : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_mask : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_pwm_rept_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_mask; - - /* 0x28 : pwm0_int_clear */ - union { - struct { - uint32_t cr_pwm_ch0l_clr : 1; /* [ 0], w1c, 0x0 */ - uint32_t cr_pwm_ch0h_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t cr_pwm_ch1l_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t cr_pwm_ch1h_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t cr_pwm_ch2l_clr : 1; /* [ 4], w1c, 0x0 */ - uint32_t cr_pwm_ch2h_clr : 1; /* [ 5], w1c, 0x0 */ - uint32_t cr_pwm_ch3l_clr : 1; /* [ 6], w1c, 0x0 */ - uint32_t cr_pwm_ch3h_clr : 1; /* [ 7], w1c, 0x0 */ - uint32_t cr_pwm_prde_clr : 1; /* [ 8], w1c, 0x0 */ - uint32_t cr_pwm_brk_clr : 1; /* [ 9], w1c, 0x0 */ - uint32_t cr_pwm_rept_clr : 1; /* [ 10], w1c, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_clear; - - /* 0x2C : pwm0_int_en */ - union { - struct { - uint32_t cr_pwm_ch0l_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_en : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_en : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_pwm_rept_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm0_int_en; -}; - -typedef volatile struct pwm_reg pwm_reg_t; - -/*Following is reg patch*/ - -/* 0x00 : pwm_config0 */ -#define PWM_CONFIG0_OFFSET (0x00) -#define PWM_CLK_DIV PWM_CLK_DIV -#define PWM_CLK_DIV_POS (0U) -#define PWM_CLK_DIV_LEN (16U) -#define PWM_CLK_DIV_MSK (((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS) -#define PWM_CLK_DIV_UMSK (~(((1U << PWM_CLK_DIV_LEN) - 1) << PWM_CLK_DIV_POS)) -#define PWM_STOP_ON_REPT PWM_STOP_ON_REPT -#define PWM_STOP_ON_REPT_POS (19U) -#define PWM_STOP_ON_REPT_LEN (1U) -#define PWM_STOP_ON_REPT_MSK (((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS) -#define PWM_STOP_ON_REPT_UMSK (~(((1U << PWM_STOP_ON_REPT_LEN) - 1) << PWM_STOP_ON_REPT_POS)) -#define PWM_ADC_TRG_SRC PWM_ADC_TRG_SRC -#define PWM_ADC_TRG_SRC_POS (20U) -#define PWM_ADC_TRG_SRC_LEN (4U) -#define PWM_ADC_TRG_SRC_MSK (((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS) -#define PWM_ADC_TRG_SRC_UMSK (~(((1U << PWM_ADC_TRG_SRC_LEN) - 1) << PWM_ADC_TRG_SRC_POS)) -#define PWM_SW_BREAK_EN PWM_SW_BREAK_EN -#define PWM_SW_BREAK_EN_POS (24U) -#define PWM_SW_BREAK_EN_LEN (1U) -#define PWM_SW_BREAK_EN_MSK (((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS) -#define PWM_SW_BREAK_EN_UMSK (~(((1U << PWM_SW_BREAK_EN_LEN) - 1) << PWM_SW_BREAK_EN_POS)) -#define PWM_EXT_BREAK_EN PWM_EXT_BREAK_EN -#define PWM_EXT_BREAK_EN_POS (25U) -#define PWM_EXT_BREAK_EN_LEN (1U) -#define PWM_EXT_BREAK_EN_MSK (((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS) -#define PWM_EXT_BREAK_EN_UMSK (~(((1U << PWM_EXT_BREAK_EN_LEN) - 1) << PWM_EXT_BREAK_EN_POS)) -#define PWM_EXT_BREAK_PL PWM_EXT_BREAK_PL -#define PWM_EXT_BREAK_PL_POS (26U) -#define PWM_EXT_BREAK_PL_LEN (1U) -#define PWM_EXT_BREAK_PL_MSK (((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS) -#define PWM_EXT_BREAK_PL_UMSK (~(((1U << PWM_EXT_BREAK_PL_LEN) - 1) << PWM_EXT_BREAK_PL_POS)) -#define PWM_STOP_EN PWM_STOP_EN -#define PWM_STOP_EN_POS (27U) -#define PWM_STOP_EN_LEN (1U) -#define PWM_STOP_EN_MSK (((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS) -#define PWM_STOP_EN_UMSK (~(((1U << PWM_STOP_EN_LEN) - 1) << PWM_STOP_EN_POS)) -#define PWM_STOP_MODE PWM_STOP_MODE -#define PWM_STOP_MODE_POS (28U) -#define PWM_STOP_MODE_LEN (1U) -#define PWM_STOP_MODE_MSK (((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS) -#define PWM_STOP_MODE_UMSK (~(((1U << PWM_STOP_MODE_LEN) - 1) << PWM_STOP_MODE_POS)) -#define PWM_STS_STOP PWM_STS_STOP -#define PWM_STS_STOP_POS (29U) -#define PWM_STS_STOP_LEN (1U) -#define PWM_STS_STOP_MSK (((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS) -#define PWM_STS_STOP_UMSK (~(((1U << PWM_STS_STOP_LEN) - 1) << PWM_STS_STOP_POS)) -#define PWM_REG_CLK_SEL PWM_REG_CLK_SEL -#define PWM_REG_CLK_SEL_POS (30U) -#define PWM_REG_CLK_SEL_LEN (2U) -#define PWM_REG_CLK_SEL_MSK (((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS) -#define PWM_REG_CLK_SEL_UMSK (~(((1U << PWM_REG_CLK_SEL_LEN) - 1) << PWM_REG_CLK_SEL_POS)) - -/* 0x04 : pwm_config1 */ -#define PWM_CONFIG1_OFFSET (0x04) -#define PWM_CH0_PEN PWM_CH0_PEN -#define PWM_CH0_PEN_POS (0U) -#define PWM_CH0_PEN_LEN (1U) -#define PWM_CH0_PEN_MSK (((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS) -#define PWM_CH0_PEN_UMSK (~(((1U << PWM_CH0_PEN_LEN) - 1) << PWM_CH0_PEN_POS)) -#define PWM_CH0_PSI PWM_CH0_PSI -#define PWM_CH0_PSI_POS (1U) -#define PWM_CH0_PSI_LEN (1U) -#define PWM_CH0_PSI_MSK (((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS) -#define PWM_CH0_PSI_UMSK (~(((1U << PWM_CH0_PSI_LEN) - 1) << PWM_CH0_PSI_POS)) -#define PWM_CH0_NEN PWM_CH0_NEN -#define PWM_CH0_NEN_POS (2U) -#define PWM_CH0_NEN_LEN (1U) -#define PWM_CH0_NEN_MSK (((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS) -#define PWM_CH0_NEN_UMSK (~(((1U << PWM_CH0_NEN_LEN) - 1) << PWM_CH0_NEN_POS)) -#define PWM_CH0_NSI PWM_CH0_NSI -#define PWM_CH0_NSI_POS (3U) -#define PWM_CH0_NSI_LEN (1U) -#define PWM_CH0_NSI_MSK (((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS) -#define PWM_CH0_NSI_UMSK (~(((1U << PWM_CH0_NSI_LEN) - 1) << PWM_CH0_NSI_POS)) -#define PWM_CH1_PEN PWM_CH1_PEN -#define PWM_CH1_PEN_POS (4U) -#define PWM_CH1_PEN_LEN (1U) -#define PWM_CH1_PEN_MSK (((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS) -#define PWM_CH1_PEN_UMSK (~(((1U << PWM_CH1_PEN_LEN) - 1) << PWM_CH1_PEN_POS)) -#define PWM_CH1_PSI PWM_CH1_PSI -#define PWM_CH1_PSI_POS (5U) -#define PWM_CH1_PSI_LEN (1U) -#define PWM_CH1_PSI_MSK (((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS) -#define PWM_CH1_PSI_UMSK (~(((1U << PWM_CH1_PSI_LEN) - 1) << PWM_CH1_PSI_POS)) -#define PWM_CH1_NEN PWM_CH1_NEN -#define PWM_CH1_NEN_POS (6U) -#define PWM_CH1_NEN_LEN (1U) -#define PWM_CH1_NEN_MSK (((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS) -#define PWM_CH1_NEN_UMSK (~(((1U << PWM_CH1_NEN_LEN) - 1) << PWM_CH1_NEN_POS)) -#define PWM_CH1_NSI PWM_CH1_NSI -#define PWM_CH1_NSI_POS (7U) -#define PWM_CH1_NSI_LEN (1U) -#define PWM_CH1_NSI_MSK (((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS) -#define PWM_CH1_NSI_UMSK (~(((1U << PWM_CH1_NSI_LEN) - 1) << PWM_CH1_NSI_POS)) -#define PWM_CH2_PEN PWM_CH2_PEN -#define PWM_CH2_PEN_POS (8U) -#define PWM_CH2_PEN_LEN (1U) -#define PWM_CH2_PEN_MSK (((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS) -#define PWM_CH2_PEN_UMSK (~(((1U << PWM_CH2_PEN_LEN) - 1) << PWM_CH2_PEN_POS)) -#define PWM_CH2_PSI PWM_CH2_PSI -#define PWM_CH2_PSI_POS (9U) -#define PWM_CH2_PSI_LEN (1U) -#define PWM_CH2_PSI_MSK (((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS) -#define PWM_CH2_PSI_UMSK (~(((1U << PWM_CH2_PSI_LEN) - 1) << PWM_CH2_PSI_POS)) -#define PWM_CH2_NEN PWM_CH2_NEN -#define PWM_CH2_NEN_POS (10U) -#define PWM_CH2_NEN_LEN (1U) -#define PWM_CH2_NEN_MSK (((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS) -#define PWM_CH2_NEN_UMSK (~(((1U << PWM_CH2_NEN_LEN) - 1) << PWM_CH2_NEN_POS)) -#define PWM_CH2_NSI PWM_CH2_NSI -#define PWM_CH2_NSI_POS (11U) -#define PWM_CH2_NSI_LEN (1U) -#define PWM_CH2_NSI_MSK (((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS) -#define PWM_CH2_NSI_UMSK (~(((1U << PWM_CH2_NSI_LEN) - 1) << PWM_CH2_NSI_POS)) -#define PWM_CH3_PEN PWM_CH3_PEN -#define PWM_CH3_PEN_POS (12U) -#define PWM_CH3_PEN_LEN (1U) -#define PWM_CH3_PEN_MSK (((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS) -#define PWM_CH3_PEN_UMSK (~(((1U << PWM_CH3_PEN_LEN) - 1) << PWM_CH3_PEN_POS)) -#define PWM_CH3_PSI PWM_CH3_PSI -#define PWM_CH3_PSI_POS (13U) -#define PWM_CH3_PSI_LEN (1U) -#define PWM_CH3_PSI_MSK (((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS) -#define PWM_CH3_PSI_UMSK (~(((1U << PWM_CH3_PSI_LEN) - 1) << PWM_CH3_PSI_POS)) -#define PWM_CH3_NEN PWM_CH3_NEN -#define PWM_CH3_NEN_POS (14U) -#define PWM_CH3_NEN_LEN (1U) -#define PWM_CH3_NEN_MSK (((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS) -#define PWM_CH3_NEN_UMSK (~(((1U << PWM_CH3_NEN_LEN) - 1) << PWM_CH3_NEN_POS)) -#define PWM_CH3_NSI PWM_CH3_NSI -#define PWM_CH3_NSI_POS (15U) -#define PWM_CH3_NSI_LEN (1U) -#define PWM_CH3_NSI_MSK (((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS) -#define PWM_CH3_NSI_UMSK (~(((1U << PWM_CH3_NSI_LEN) - 1) << PWM_CH3_NSI_POS)) -#define PWM_CH0_PPL PWM_CH0_PPL -#define PWM_CH0_PPL_POS (16U) -#define PWM_CH0_PPL_LEN (1U) -#define PWM_CH0_PPL_MSK (((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS) -#define PWM_CH0_PPL_UMSK (~(((1U << PWM_CH0_PPL_LEN) - 1) << PWM_CH0_PPL_POS)) -#define PWM_CH0_NPL PWM_CH0_NPL -#define PWM_CH0_NPL_POS (17U) -#define PWM_CH0_NPL_LEN (1U) -#define PWM_CH0_NPL_MSK (((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS) -#define PWM_CH0_NPL_UMSK (~(((1U << PWM_CH0_NPL_LEN) - 1) << PWM_CH0_NPL_POS)) -#define PWM_CH1_PPL PWM_CH1_PPL -#define PWM_CH1_PPL_POS (18U) -#define PWM_CH1_PPL_LEN (1U) -#define PWM_CH1_PPL_MSK (((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS) -#define PWM_CH1_PPL_UMSK (~(((1U << PWM_CH1_PPL_LEN) - 1) << PWM_CH1_PPL_POS)) -#define PWM_CH1_NPL PWM_CH1_NPL -#define PWM_CH1_NPL_POS (19U) -#define PWM_CH1_NPL_LEN (1U) -#define PWM_CH1_NPL_MSK (((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS) -#define PWM_CH1_NPL_UMSK (~(((1U << PWM_CH1_NPL_LEN) - 1) << PWM_CH1_NPL_POS)) -#define PWM_CH2_PPL PWM_CH2_PPL -#define PWM_CH2_PPL_POS (20U) -#define PWM_CH2_PPL_LEN (1U) -#define PWM_CH2_PPL_MSK (((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS) -#define PWM_CH2_PPL_UMSK (~(((1U << PWM_CH2_PPL_LEN) - 1) << PWM_CH2_PPL_POS)) -#define PWM_CH2_NPL PWM_CH2_NPL -#define PWM_CH2_NPL_POS (21U) -#define PWM_CH2_NPL_LEN (1U) -#define PWM_CH2_NPL_MSK (((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS) -#define PWM_CH2_NPL_UMSK (~(((1U << PWM_CH2_NPL_LEN) - 1) << PWM_CH2_NPL_POS)) -#define PWM_CH3_PPL PWM_CH3_PPL -#define PWM_CH3_PPL_POS (22U) -#define PWM_CH3_PPL_LEN (1U) -#define PWM_CH3_PPL_MSK (((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS) -#define PWM_CH3_PPL_UMSK (~(((1U << PWM_CH3_PPL_LEN) - 1) << PWM_CH3_PPL_POS)) -#define PWM_CH3_NPL PWM_CH3_NPL -#define PWM_CH3_NPL_POS (23U) -#define PWM_CH3_NPL_LEN (1U) -#define PWM_CH3_NPL_MSK (((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS) -#define PWM_CH3_NPL_UMSK (~(((1U << PWM_CH3_NPL_LEN) - 1) << PWM_CH3_NPL_POS)) -#define PWM_CH0_PBS PWM_CH0_PBS -#define PWM_CH0_PBS_POS (24U) -#define PWM_CH0_PBS_LEN (1U) -#define PWM_CH0_PBS_MSK (((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS) -#define PWM_CH0_PBS_UMSK (~(((1U << PWM_CH0_PBS_LEN) - 1) << PWM_CH0_PBS_POS)) -#define PWM_CH0_NBS PWM_CH0_NBS -#define PWM_CH0_NBS_POS (25U) -#define PWM_CH0_NBS_LEN (1U) -#define PWM_CH0_NBS_MSK (((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS) -#define PWM_CH0_NBS_UMSK (~(((1U << PWM_CH0_NBS_LEN) - 1) << PWM_CH0_NBS_POS)) -#define PWM_CH1_PBS PWM_CH1_PBS -#define PWM_CH1_PBS_POS (26U) -#define PWM_CH1_PBS_LEN (1U) -#define PWM_CH1_PBS_MSK (((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS) -#define PWM_CH1_PBS_UMSK (~(((1U << PWM_CH1_PBS_LEN) - 1) << PWM_CH1_PBS_POS)) -#define PWM_CH1_NBS PWM_CH1_NBS -#define PWM_CH1_NBS_POS (27U) -#define PWM_CH1_NBS_LEN (1U) -#define PWM_CH1_NBS_MSK (((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS) -#define PWM_CH1_NBS_UMSK (~(((1U << PWM_CH1_NBS_LEN) - 1) << PWM_CH1_NBS_POS)) -#define PWM_CH2_PBS PWM_CH2_PBS -#define PWM_CH2_PBS_POS (28U) -#define PWM_CH2_PBS_LEN (1U) -#define PWM_CH2_PBS_MSK (((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS) -#define PWM_CH2_PBS_UMSK (~(((1U << PWM_CH2_PBS_LEN) - 1) << PWM_CH2_PBS_POS)) -#define PWM_CH2_NBS PWM_CH2_NBS -#define PWM_CH2_NBS_POS (29U) -#define PWM_CH2_NBS_LEN (1U) -#define PWM_CH2_NBS_MSK (((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS) -#define PWM_CH2_NBS_UMSK (~(((1U << PWM_CH2_NBS_LEN) - 1) << PWM_CH2_NBS_POS)) -#define PWM_CH3_PBS PWM_CH3_PBS -#define PWM_CH3_PBS_POS (30U) -#define PWM_CH3_PBS_LEN (1U) -#define PWM_CH3_PBS_MSK (((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS) -#define PWM_CH3_PBS_UMSK (~(((1U << PWM_CH3_PBS_LEN) - 1) << PWM_CH3_PBS_POS)) -#define PWM_CH3_NBS PWM_CH3_NBS -#define PWM_CH3_NBS_POS (31U) -#define PWM_CH3_NBS_LEN (1U) -#define PWM_CH3_NBS_MSK (((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS) -#define PWM_CH3_NBS_UMSK (~(((1U << PWM_CH3_NBS_LEN) - 1) << PWM_CH3_NBS_POS)) - -/* 0x08 : pwm_period */ -#define PWM_PERIOD_OFFSET (0x08) -#define PWM_PERIOD PWM_PERIOD -#define PWM_PERIOD_POS (0U) -#define PWM_PERIOD_LEN (16U) -#define PWM_PERIOD_MSK (((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS) -#define PWM_PERIOD_UMSK (~(((1U << PWM_PERIOD_LEN) - 1) << PWM_PERIOD_POS)) -#define PWM_INT_PERIOD_CNT PWM_INT_PERIOD_CNT -#define PWM_INT_PERIOD_CNT_POS (16U) -#define PWM_INT_PERIOD_CNT_LEN (16U) -#define PWM_INT_PERIOD_CNT_MSK (((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS) -#define PWM_INT_PERIOD_CNT_UMSK (~(((1U << PWM_INT_PERIOD_CNT_LEN) - 1) << PWM_INT_PERIOD_CNT_POS)) - -/* 0x0C : pwm_dead_time */ -#define PWM_DEAD_TIME_OFFSET (0x0C) -#define PWM_CH0_DTG PWM_CH0_DTG -#define PWM_CH0_DTG_POS (0U) -#define PWM_CH0_DTG_LEN (8U) -#define PWM_CH0_DTG_MSK (((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS) -#define PWM_CH0_DTG_UMSK (~(((1U << PWM_CH0_DTG_LEN) - 1) << PWM_CH0_DTG_POS)) -#define PWM_CH1_DTG PWM_CH1_DTG -#define PWM_CH1_DTG_POS (8U) -#define PWM_CH1_DTG_LEN (8U) -#define PWM_CH1_DTG_MSK (((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS) -#define PWM_CH1_DTG_UMSK (~(((1U << PWM_CH1_DTG_LEN) - 1) << PWM_CH1_DTG_POS)) -#define PWM_CH2_DTG PWM_CH2_DTG -#define PWM_CH2_DTG_POS (16U) -#define PWM_CH2_DTG_LEN (8U) -#define PWM_CH2_DTG_MSK (((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS) -#define PWM_CH2_DTG_UMSK (~(((1U << PWM_CH2_DTG_LEN) - 1) << PWM_CH2_DTG_POS)) -#define PWM_CH3_DTG PWM_CH3_DTG -#define PWM_CH3_DTG_POS (24U) -#define PWM_CH3_DTG_LEN (8U) -#define PWM_CH3_DTG_MSK (((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS) -#define PWM_CH3_DTG_UMSK (~(((1U << PWM_CH3_DTG_LEN) - 1) << PWM_CH3_DTG_POS)) - -/* 0x10 : pwm_ch0_thre */ -#define PWM_CH0_THRE_OFFSET (0x10) -#define PWM_CH0_THREL PWM_CH0_THREL -#define PWM_CH0_THREL_POS (0U) -#define PWM_CH0_THREL_LEN (16U) -#define PWM_CH0_THREL_MSK (((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS) -#define PWM_CH0_THREL_UMSK (~(((1U << PWM_CH0_THREL_LEN) - 1) << PWM_CH0_THREL_POS)) -#define PWM_CH0_THREH PWM_CH0_THREH -#define PWM_CH0_THREH_POS (16U) -#define PWM_CH0_THREH_LEN (16U) -#define PWM_CH0_THREH_MSK (((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS) -#define PWM_CH0_THREH_UMSK (~(((1U << PWM_CH0_THREH_LEN) - 1) << PWM_CH0_THREH_POS)) - -/* 0x14 : pwm_ch1_thre */ -#define PWM_CH1_THRE_OFFSET (0x14) -#define PWM_CH1_THREL PWM_CH1_THREL -#define PWM_CH1_THREL_POS (0U) -#define PWM_CH1_THREL_LEN (16U) -#define PWM_CH1_THREL_MSK (((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS) -#define PWM_CH1_THREL_UMSK (~(((1U << PWM_CH1_THREL_LEN) - 1) << PWM_CH1_THREL_POS)) -#define PWM_CH1_THREH PWM_CH1_THREH -#define PWM_CH1_THREH_POS (16U) -#define PWM_CH1_THREH_LEN (16U) -#define PWM_CH1_THREH_MSK (((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS) -#define PWM_CH1_THREH_UMSK (~(((1U << PWM_CH1_THREH_LEN) - 1) << PWM_CH1_THREH_POS)) - -/* 0x18 : pwm_ch2_thre */ -#define PWM_CH2_THRE_OFFSET (0x18) -#define PWM_CH2_THREL PWM_CH2_THREL -#define PWM_CH2_THREL_POS (0U) -#define PWM_CH2_THREL_LEN (16U) -#define PWM_CH2_THREL_MSK (((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS) -#define PWM_CH2_THREL_UMSK (~(((1U << PWM_CH2_THREL_LEN) - 1) << PWM_CH2_THREL_POS)) -#define PWM_CH2_THREH PWM_CH2_THREH -#define PWM_CH2_THREH_POS (16U) -#define PWM_CH2_THREH_LEN (16U) -#define PWM_CH2_THREH_MSK (((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS) -#define PWM_CH2_THREH_UMSK (~(((1U << PWM_CH2_THREH_LEN) - 1) << PWM_CH2_THREH_POS)) - -/* 0x1C : pwm_ch3_thre */ -#define PWM_CH3_THRE_OFFSET (0x1C) -#define PWM_CH3_THREL PWM_CH3_THREL -#define PWM_CH3_THREL_POS (0U) -#define PWM_CH3_THREL_LEN (16U) -#define PWM_CH3_THREL_MSK (((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS) -#define PWM_CH3_THREL_UMSK (~(((1U << PWM_CH3_THREL_LEN) - 1) << PWM_CH3_THREL_POS)) -#define PWM_CH3_THREH PWM_CH3_THREH -#define PWM_CH3_THREH_POS (16U) -#define PWM_CH3_THREH_LEN (16U) -#define PWM_CH3_THREH_MSK (((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS) -#define PWM_CH3_THREH_UMSK (~(((1U << PWM_CH3_THREH_LEN) - 1) << PWM_CH3_THREH_POS)) - -/* 0x20 : pwm_int_sts */ -#define PWM_INT_STS_OFFSET (0x20) -#define PWM_CH0L_INT PWM_CH0L_INT -#define PWM_CH0L_INT_POS (0U) -#define PWM_CH0L_INT_LEN (1U) -#define PWM_CH0L_INT_MSK (((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS) -#define PWM_CH0L_INT_UMSK (~(((1U << PWM_CH0L_INT_LEN) - 1) << PWM_CH0L_INT_POS)) -#define PWM_CH0H_INT PWM_CH0H_INT -#define PWM_CH0H_INT_POS (1U) -#define PWM_CH0H_INT_LEN (1U) -#define PWM_CH0H_INT_MSK (((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS) -#define PWM_CH0H_INT_UMSK (~(((1U << PWM_CH0H_INT_LEN) - 1) << PWM_CH0H_INT_POS)) -#define PWM_CH1L_INT PWM_CH1L_INT -#define PWM_CH1L_INT_POS (2U) -#define PWM_CH1L_INT_LEN (1U) -#define PWM_CH1L_INT_MSK (((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS) -#define PWM_CH1L_INT_UMSK (~(((1U << PWM_CH1L_INT_LEN) - 1) << PWM_CH1L_INT_POS)) -#define PWM_CH1H_INT PWM_CH1H_INT -#define PWM_CH1H_INT_POS (3U) -#define PWM_CH1H_INT_LEN (1U) -#define PWM_CH1H_INT_MSK (((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS) -#define PWM_CH1H_INT_UMSK (~(((1U << PWM_CH1H_INT_LEN) - 1) << PWM_CH1H_INT_POS)) -#define PWM_CH2L_INT PWM_CH2L_INT -#define PWM_CH2L_INT_POS (4U) -#define PWM_CH2L_INT_LEN (1U) -#define PWM_CH2L_INT_MSK (((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS) -#define PWM_CH2L_INT_UMSK (~(((1U << PWM_CH2L_INT_LEN) - 1) << PWM_CH2L_INT_POS)) -#define PWM_CH2H_INT PWM_CH2H_INT -#define PWM_CH2H_INT_POS (5U) -#define PWM_CH2H_INT_LEN (1U) -#define PWM_CH2H_INT_MSK (((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS) -#define PWM_CH2H_INT_UMSK (~(((1U << PWM_CH2H_INT_LEN) - 1) << PWM_CH2H_INT_POS)) -#define PWM_CH3L_INT PWM_CH3L_INT -#define PWM_CH3L_INT_POS (6U) -#define PWM_CH3L_INT_LEN (1U) -#define PWM_CH3L_INT_MSK (((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS) -#define PWM_CH3L_INT_UMSK (~(((1U << PWM_CH3L_INT_LEN) - 1) << PWM_CH3L_INT_POS)) -#define PWM_CH3H_INT PWM_CH3H_INT -#define PWM_CH3H_INT_POS (7U) -#define PWM_CH3H_INT_LEN (1U) -#define PWM_CH3H_INT_MSK (((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS) -#define PWM_CH3H_INT_UMSK (~(((1U << PWM_CH3H_INT_LEN) - 1) << PWM_CH3H_INT_POS)) -#define PWM_PRDE_INT PWM_PRDE_INT -#define PWM_PRDE_INT_POS (8U) -#define PWM_PRDE_INT_LEN (1U) -#define PWM_PRDE_INT_MSK (((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS) -#define PWM_PRDE_INT_UMSK (~(((1U << PWM_PRDE_INT_LEN) - 1) << PWM_PRDE_INT_POS)) -#define PWM_BRK_INT PWM_BRK_INT -#define PWM_BRK_INT_POS (9U) -#define PWM_BRK_INT_LEN (1U) -#define PWM_BRK_INT_MSK (((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS) -#define PWM_BRK_INT_UMSK (~(((1U << PWM_BRK_INT_LEN) - 1) << PWM_BRK_INT_POS)) -#define PWM_REPT_INT PWM_REPT_INT -#define PWM_REPT_INT_POS (10U) -#define PWM_REPT_INT_LEN (1U) -#define PWM_REPT_INT_MSK (((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS) -#define PWM_REPT_INT_UMSK (~(((1U << PWM_REPT_INT_LEN) - 1) << PWM_REPT_INT_POS)) - -/* 0x24 : pwm_int_mask */ -#define PWM_INT_MASK_OFFSET (0x24) -#define PWM_CR_PWM_CH0L_MASK PWM_CR_PWM_CH0L_MASK -#define PWM_CR_PWM_CH0L_MASK_POS (0U) -#define PWM_CR_PWM_CH0L_MASK_LEN (1U) -#define PWM_CR_PWM_CH0L_MASK_MSK (((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS) -#define PWM_CR_PWM_CH0L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0L_MASK_LEN) - 1) << PWM_CR_PWM_CH0L_MASK_POS)) -#define PWM_CR_PWM_CH0H_MASK PWM_CR_PWM_CH0H_MASK -#define PWM_CR_PWM_CH0H_MASK_POS (1U) -#define PWM_CR_PWM_CH0H_MASK_LEN (1U) -#define PWM_CR_PWM_CH0H_MASK_MSK (((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS) -#define PWM_CR_PWM_CH0H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH0H_MASK_LEN) - 1) << PWM_CR_PWM_CH0H_MASK_POS)) -#define PWM_CR_PWM_CH1L_MASK PWM_CR_PWM_CH1L_MASK -#define PWM_CR_PWM_CH1L_MASK_POS (2U) -#define PWM_CR_PWM_CH1L_MASK_LEN (1U) -#define PWM_CR_PWM_CH1L_MASK_MSK (((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS) -#define PWM_CR_PWM_CH1L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1L_MASK_LEN) - 1) << PWM_CR_PWM_CH1L_MASK_POS)) -#define PWM_CR_PWM_CH1H_MASK PWM_CR_PWM_CH1H_MASK -#define PWM_CR_PWM_CH1H_MASK_POS (3U) -#define PWM_CR_PWM_CH1H_MASK_LEN (1U) -#define PWM_CR_PWM_CH1H_MASK_MSK (((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS) -#define PWM_CR_PWM_CH1H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH1H_MASK_LEN) - 1) << PWM_CR_PWM_CH1H_MASK_POS)) -#define PWM_CR_PWM_CH2L_MASK PWM_CR_PWM_CH2L_MASK -#define PWM_CR_PWM_CH2L_MASK_POS (4U) -#define PWM_CR_PWM_CH2L_MASK_LEN (1U) -#define PWM_CR_PWM_CH2L_MASK_MSK (((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS) -#define PWM_CR_PWM_CH2L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2L_MASK_LEN) - 1) << PWM_CR_PWM_CH2L_MASK_POS)) -#define PWM_CR_PWM_CH2H_MASK PWM_CR_PWM_CH2H_MASK -#define PWM_CR_PWM_CH2H_MASK_POS (5U) -#define PWM_CR_PWM_CH2H_MASK_LEN (1U) -#define PWM_CR_PWM_CH2H_MASK_MSK (((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS) -#define PWM_CR_PWM_CH2H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH2H_MASK_LEN) - 1) << PWM_CR_PWM_CH2H_MASK_POS)) -#define PWM_CR_PWM_CH3L_MASK PWM_CR_PWM_CH3L_MASK -#define PWM_CR_PWM_CH3L_MASK_POS (6U) -#define PWM_CR_PWM_CH3L_MASK_LEN (1U) -#define PWM_CR_PWM_CH3L_MASK_MSK (((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS) -#define PWM_CR_PWM_CH3L_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3L_MASK_LEN) - 1) << PWM_CR_PWM_CH3L_MASK_POS)) -#define PWM_CR_PWM_CH3H_MASK PWM_CR_PWM_CH3H_MASK -#define PWM_CR_PWM_CH3H_MASK_POS (7U) -#define PWM_CR_PWM_CH3H_MASK_LEN (1U) -#define PWM_CR_PWM_CH3H_MASK_MSK (((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS) -#define PWM_CR_PWM_CH3H_MASK_UMSK (~(((1U << PWM_CR_PWM_CH3H_MASK_LEN) - 1) << PWM_CR_PWM_CH3H_MASK_POS)) -#define PWM_CR_PWM_PRDE_MASK PWM_CR_PWM_PRDE_MASK -#define PWM_CR_PWM_PRDE_MASK_POS (8U) -#define PWM_CR_PWM_PRDE_MASK_LEN (1U) -#define PWM_CR_PWM_PRDE_MASK_MSK (((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS) -#define PWM_CR_PWM_PRDE_MASK_UMSK (~(((1U << PWM_CR_PWM_PRDE_MASK_LEN) - 1) << PWM_CR_PWM_PRDE_MASK_POS)) -#define PWM_CR_PWM_BRK_MASK PWM_CR_PWM_BRK_MASK -#define PWM_CR_PWM_BRK_MASK_POS (9U) -#define PWM_CR_PWM_BRK_MASK_LEN (1U) -#define PWM_CR_PWM_BRK_MASK_MSK (((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS) -#define PWM_CR_PWM_BRK_MASK_UMSK (~(((1U << PWM_CR_PWM_BRK_MASK_LEN) - 1) << PWM_CR_PWM_BRK_MASK_POS)) -#define PWM_CR_PWM_REPT_MASK PWM_CR_PWM_REPT_MASK -#define PWM_CR_PWM_REPT_MASK_POS (10U) -#define PWM_CR_PWM_REPT_MASK_LEN (1U) -#define PWM_CR_PWM_REPT_MASK_MSK (((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS) -#define PWM_CR_PWM_REPT_MASK_UMSK (~(((1U << PWM_CR_PWM_REPT_MASK_LEN) - 1) << PWM_CR_PWM_REPT_MASK_POS)) - -/* 0x28 : pwm_int_clear */ -#define PWM_INT_CLEAR_OFFSET (0x28) -#define PWM_CR_PWM_CH0L_CLR PWM_CR_PWM_CH0L_CLR -#define PWM_CR_PWM_CH0L_CLR_POS (0U) -#define PWM_CR_PWM_CH0L_CLR_LEN (1U) -#define PWM_CR_PWM_CH0L_CLR_MSK (((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS) -#define PWM_CR_PWM_CH0L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0L_CLR_LEN) - 1) << PWM_CR_PWM_CH0L_CLR_POS)) -#define PWM_CR_PWM_CH0H_CLR PWM_CR_PWM_CH0H_CLR -#define PWM_CR_PWM_CH0H_CLR_POS (1U) -#define PWM_CR_PWM_CH0H_CLR_LEN (1U) -#define PWM_CR_PWM_CH0H_CLR_MSK (((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS) -#define PWM_CR_PWM_CH0H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH0H_CLR_LEN) - 1) << PWM_CR_PWM_CH0H_CLR_POS)) -#define PWM_CR_PWM_CH1L_CLR PWM_CR_PWM_CH1L_CLR -#define PWM_CR_PWM_CH1L_CLR_POS (2U) -#define PWM_CR_PWM_CH1L_CLR_LEN (1U) -#define PWM_CR_PWM_CH1L_CLR_MSK (((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS) -#define PWM_CR_PWM_CH1L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1L_CLR_LEN) - 1) << PWM_CR_PWM_CH1L_CLR_POS)) -#define PWM_CR_PWM_CH1H_CLR PWM_CR_PWM_CH1H_CLR -#define PWM_CR_PWM_CH1H_CLR_POS (3U) -#define PWM_CR_PWM_CH1H_CLR_LEN (1U) -#define PWM_CR_PWM_CH1H_CLR_MSK (((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS) -#define PWM_CR_PWM_CH1H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH1H_CLR_LEN) - 1) << PWM_CR_PWM_CH1H_CLR_POS)) -#define PWM_CR_PWM_CH2L_CLR PWM_CR_PWM_CH2L_CLR -#define PWM_CR_PWM_CH2L_CLR_POS (4U) -#define PWM_CR_PWM_CH2L_CLR_LEN (1U) -#define PWM_CR_PWM_CH2L_CLR_MSK (((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS) -#define PWM_CR_PWM_CH2L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2L_CLR_LEN) - 1) << PWM_CR_PWM_CH2L_CLR_POS)) -#define PWM_CR_PWM_CH2H_CLR PWM_CR_PWM_CH2H_CLR -#define PWM_CR_PWM_CH2H_CLR_POS (5U) -#define PWM_CR_PWM_CH2H_CLR_LEN (1U) -#define PWM_CR_PWM_CH2H_CLR_MSK (((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS) -#define PWM_CR_PWM_CH2H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH2H_CLR_LEN) - 1) << PWM_CR_PWM_CH2H_CLR_POS)) -#define PWM_CR_PWM_CH3L_CLR PWM_CR_PWM_CH3L_CLR -#define PWM_CR_PWM_CH3L_CLR_POS (6U) -#define PWM_CR_PWM_CH3L_CLR_LEN (1U) -#define PWM_CR_PWM_CH3L_CLR_MSK (((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS) -#define PWM_CR_PWM_CH3L_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3L_CLR_LEN) - 1) << PWM_CR_PWM_CH3L_CLR_POS)) -#define PWM_CR_PWM_CH3H_CLR PWM_CR_PWM_CH3H_CLR -#define PWM_CR_PWM_CH3H_CLR_POS (7U) -#define PWM_CR_PWM_CH3H_CLR_LEN (1U) -#define PWM_CR_PWM_CH3H_CLR_MSK (((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS) -#define PWM_CR_PWM_CH3H_CLR_UMSK (~(((1U << PWM_CR_PWM_CH3H_CLR_LEN) - 1) << PWM_CR_PWM_CH3H_CLR_POS)) -#define PWM_CR_PWM_PRDE_CLR PWM_CR_PWM_PRDE_CLR -#define PWM_CR_PWM_PRDE_CLR_POS (8U) -#define PWM_CR_PWM_PRDE_CLR_LEN (1U) -#define PWM_CR_PWM_PRDE_CLR_MSK (((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS) -#define PWM_CR_PWM_PRDE_CLR_UMSK (~(((1U << PWM_CR_PWM_PRDE_CLR_LEN) - 1) << PWM_CR_PWM_PRDE_CLR_POS)) -#define PWM_CR_PWM_BRK_CLR PWM_CR_PWM_BRK_CLR -#define PWM_CR_PWM_BRK_CLR_POS (9U) -#define PWM_CR_PWM_BRK_CLR_LEN (1U) -#define PWM_CR_PWM_BRK_CLR_MSK (((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS) -#define PWM_CR_PWM_BRK_CLR_UMSK (~(((1U << PWM_CR_PWM_BRK_CLR_LEN) - 1) << PWM_CR_PWM_BRK_CLR_POS)) -#define PWM_CR_PWM_REPT_CLR PWM_CR_PWM_REPT_CLR -#define PWM_CR_PWM_REPT_CLR_POS (10U) -#define PWM_CR_PWM_REPT_CLR_LEN (1U) -#define PWM_CR_PWM_REPT_CLR_MSK (((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS) -#define PWM_CR_PWM_REPT_CLR_UMSK (~(((1U << PWM_CR_PWM_REPT_CLR_LEN) - 1) << PWM_CR_PWM_REPT_CLR_POS)) - -/* 0x2C : pwm_int_en */ -#define PWM_INT_EN_OFFSET (0x2C) -#define PWM_CR_PWM_CH0L_EN PWM_CR_PWM_CH0L_EN -#define PWM_CR_PWM_CH0L_EN_POS (0U) -#define PWM_CR_PWM_CH0L_EN_LEN (1U) -#define PWM_CR_PWM_CH0L_EN_MSK (((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS) -#define PWM_CR_PWM_CH0L_EN_UMSK (~(((1U << PWM_CR_PWM_CH0L_EN_LEN) - 1) << PWM_CR_PWM_CH0L_EN_POS)) -#define PWM_CR_PWM_CH0H_EN PWM_CR_PWM_CH0H_EN -#define PWM_CR_PWM_CH0H_EN_POS (1U) -#define PWM_CR_PWM_CH0H_EN_LEN (1U) -#define PWM_CR_PWM_CH0H_EN_MSK (((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS) -#define PWM_CR_PWM_CH0H_EN_UMSK (~(((1U << PWM_CR_PWM_CH0H_EN_LEN) - 1) << PWM_CR_PWM_CH0H_EN_POS)) -#define PWM_CR_PWM_CH1L_EN PWM_CR_PWM_CH1L_EN -#define PWM_CR_PWM_CH1L_EN_POS (2U) -#define PWM_CR_PWM_CH1L_EN_LEN (1U) -#define PWM_CR_PWM_CH1L_EN_MSK (((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS) -#define PWM_CR_PWM_CH1L_EN_UMSK (~(((1U << PWM_CR_PWM_CH1L_EN_LEN) - 1) << PWM_CR_PWM_CH1L_EN_POS)) -#define PWM_CR_PWM_CH1H_EN PWM_CR_PWM_CH1H_EN -#define PWM_CR_PWM_CH1H_EN_POS (3U) -#define PWM_CR_PWM_CH1H_EN_LEN (1U) -#define PWM_CR_PWM_CH1H_EN_MSK (((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS) -#define PWM_CR_PWM_CH1H_EN_UMSK (~(((1U << PWM_CR_PWM_CH1H_EN_LEN) - 1) << PWM_CR_PWM_CH1H_EN_POS)) -#define PWM_CR_PWM_CH2L_EN PWM_CR_PWM_CH2L_EN -#define PWM_CR_PWM_CH2L_EN_POS (4U) -#define PWM_CR_PWM_CH2L_EN_LEN (1U) -#define PWM_CR_PWM_CH2L_EN_MSK (((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS) -#define PWM_CR_PWM_CH2L_EN_UMSK (~(((1U << PWM_CR_PWM_CH2L_EN_LEN) - 1) << PWM_CR_PWM_CH2L_EN_POS)) -#define PWM_CR_PWM_CH2H_EN PWM_CR_PWM_CH2H_EN -#define PWM_CR_PWM_CH2H_EN_POS (5U) -#define PWM_CR_PWM_CH2H_EN_LEN (1U) -#define PWM_CR_PWM_CH2H_EN_MSK (((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS) -#define PWM_CR_PWM_CH2H_EN_UMSK (~(((1U << PWM_CR_PWM_CH2H_EN_LEN) - 1) << PWM_CR_PWM_CH2H_EN_POS)) -#define PWM_CR_PWM_CH3L_EN PWM_CR_PWM_CH3L_EN -#define PWM_CR_PWM_CH3L_EN_POS (6U) -#define PWM_CR_PWM_CH3L_EN_LEN (1U) -#define PWM_CR_PWM_CH3L_EN_MSK (((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS) -#define PWM_CR_PWM_CH3L_EN_UMSK (~(((1U << PWM_CR_PWM_CH3L_EN_LEN) - 1) << PWM_CR_PWM_CH3L_EN_POS)) -#define PWM_CR_PWM_CH3H_EN PWM_CR_PWM_CH3H_EN -#define PWM_CR_PWM_CH3H_EN_POS (7U) -#define PWM_CR_PWM_CH3H_EN_LEN (1U) -#define PWM_CR_PWM_CH3H_EN_MSK (((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS) -#define PWM_CR_PWM_CH3H_EN_UMSK (~(((1U << PWM_CR_PWM_CH3H_EN_LEN) - 1) << PWM_CR_PWM_CH3H_EN_POS)) -#define PWM_CR_PWM_PRDE_EN PWM_CR_PWM_PRDE_EN -#define PWM_CR_PWM_PRDE_EN_POS (8U) -#define PWM_CR_PWM_PRDE_EN_LEN (1U) -#define PWM_CR_PWM_PRDE_EN_MSK (((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS) -#define PWM_CR_PWM_PRDE_EN_UMSK (~(((1U << PWM_CR_PWM_PRDE_EN_LEN) - 1) << PWM_CR_PWM_PRDE_EN_POS)) -#define PWM_CR_PWM_BRK_EN PWM_CR_PWM_BRK_EN -#define PWM_CR_PWM_BRK_EN_POS (9U) -#define PWM_CR_PWM_BRK_EN_LEN (1U) -#define PWM_CR_PWM_BRK_EN_MSK (((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS) -#define PWM_CR_PWM_BRK_EN_UMSK (~(((1U << PWM_CR_PWM_BRK_EN_LEN) - 1) << PWM_CR_PWM_BRK_EN_POS)) -#define PWM_CR_PWM_REPT_EN PWM_CR_PWM_REPT_EN -#define PWM_CR_PWM_REPT_EN_POS (10U) -#define PWM_CR_PWM_REPT_EN_LEN (1U) -#define PWM_CR_PWM_REPT_EN_MSK (((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS) -#define PWM_CR_PWM_REPT_EN_UMSK (~(((1U << PWM_CR_PWM_REPT_EN_LEN) - 1) << PWM_CR_PWM_REPT_EN_POS)) - -struct pwm_channel_reg { - /* 0x00 : pwm_config0 */ - union { - struct { - uint32_t pwm_clk_div : 16; /* [15: 0], r/w, 0x0 */ - uint32_t reserved_16_18 : 3; /* [18:16], rsvd, 0x0 */ - uint32_t pwm_stop_on_rept : 1; /* [ 19], r/w, 0x0 */ - uint32_t pwm_adc_trg_src : 4; /* [23:20], r/w, 0xf */ - uint32_t pwm_sw_break_en : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ext_break_en : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ext_break_pl : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_stop_en : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_stop_mode : 1; /* [ 28], r/w, 0x1 */ - uint32_t pwm_sts_stop : 1; /* [ 29], r, 0x0 */ - uint32_t reg_clk_sel : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_config0; - - /* 0x04 : pwm_config1 */ - union { - struct { - uint32_t pwm_ch0_pen : 1; /* [ 0], r/w, 0x0 */ - uint32_t pwm_ch0_psi : 1; /* [ 1], r/w, 0x0 */ - uint32_t pwm_ch0_nen : 1; /* [ 2], r/w, 0x0 */ - uint32_t pwm_ch0_nsi : 1; /* [ 3], r/w, 0x1 */ - uint32_t pwm_ch1_pen : 1; /* [ 4], r/w, 0x0 */ - uint32_t pwm_ch1_psi : 1; /* [ 5], r/w, 0x0 */ - uint32_t pwm_ch1_nen : 1; /* [ 6], r/w, 0x0 */ - uint32_t pwm_ch1_nsi : 1; /* [ 7], r/w, 0x1 */ - uint32_t pwm_ch2_pen : 1; /* [ 8], r/w, 0x0 */ - uint32_t pwm_ch2_psi : 1; /* [ 9], r/w, 0x0 */ - uint32_t pwm_ch2_nen : 1; /* [ 10], r/w, 0x0 */ - uint32_t pwm_ch2_nsi : 1; /* [ 11], r/w, 0x1 */ - uint32_t pwm_ch3_pen : 1; /* [ 12], r/w, 0x0 */ - uint32_t pwm_ch3_psi : 1; /* [ 13], r/w, 0x0 */ - uint32_t pwm_ch3_nen : 1; /* [ 14], r/w, 0x0 */ - uint32_t pwm_ch3_nsi : 1; /* [ 15], r/w, 0x1 */ - uint32_t pwm_ch0_ppl : 1; /* [ 16], r/w, 0x1 */ - uint32_t pwm_ch0_npl : 1; /* [ 17], r/w, 0x1 */ - uint32_t pwm_ch1_ppl : 1; /* [ 18], r/w, 0x1 */ - uint32_t pwm_ch1_npl : 1; /* [ 19], r/w, 0x1 */ - uint32_t pwm_ch2_ppl : 1; /* [ 20], r/w, 0x1 */ - uint32_t pwm_ch2_npl : 1; /* [ 21], r/w, 0x1 */ - uint32_t pwm_ch3_ppl : 1; /* [ 22], r/w, 0x1 */ - uint32_t pwm_ch3_npl : 1; /* [ 23], r/w, 0x1 */ - uint32_t pwm_ch0_pbs : 1; /* [ 24], r/w, 0x0 */ - uint32_t pwm_ch0_nbs : 1; /* [ 25], r/w, 0x0 */ - uint32_t pwm_ch1_pbs : 1; /* [ 26], r/w, 0x0 */ - uint32_t pwm_ch1_nbs : 1; /* [ 27], r/w, 0x0 */ - uint32_t pwm_ch2_pbs : 1; /* [ 28], r/w, 0x0 */ - uint32_t pwm_ch2_nbs : 1; /* [ 29], r/w, 0x0 */ - uint32_t pwm_ch3_pbs : 1; /* [ 30], r/w, 0x0 */ - uint32_t pwm_ch3_nbs : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_config1; - - /* 0x08 : pwm_period */ - union { - struct { - uint32_t pwm_period : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_int_period_cnt : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_period; - - /* 0x0C : pwm_dead_time */ - union { - struct { - uint32_t pwm_ch0_dtg : 8; /* [ 7: 0], r/w, 0x0 */ - uint32_t pwm_ch1_dtg : 8; /* [15: 8], r/w, 0x0 */ - uint32_t pwm_ch2_dtg : 8; /* [23:16], r/w, 0x0 */ - uint32_t pwm_ch3_dtg : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_dead_time; - - /* 0x10 : pwm_ch0_thre */ - union { - struct { - uint32_t pwm_ch0_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch0_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch0_thre; - - /* 0x14 : pwm_ch1_thre */ - union { - struct { - uint32_t pwm_ch1_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch1_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch1_thre; - - /* 0x18 : pwm_ch2_thre */ - union { - struct { - uint32_t pwm_ch2_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch2_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch2_thre; - - /* 0x1C : pwm_ch3_thre */ - union { - struct { - uint32_t pwm_ch3_threL : 16; /* [15: 0], r/w, 0x0 */ - uint32_t pwm_ch3_threH : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } pwm_ch3_thre; - - /* 0x20 : pwm_int_sts */ - union { - struct { - uint32_t pwm_ch0l_int : 1; /* [ 0], r, 0x0 */ - uint32_t pwm_ch0h_int : 1; /* [ 1], r, 0x0 */ - uint32_t pwm_ch1l_int : 1; /* [ 2], r, 0x0 */ - uint32_t pwm_ch1h_int : 1; /* [ 3], r, 0x0 */ - uint32_t pwm_ch2l_int : 1; /* [ 4], r, 0x0 */ - uint32_t pwm_ch2h_int : 1; /* [ 5], r, 0x0 */ - uint32_t pwm_ch3l_int : 1; /* [ 6], r, 0x0 */ - uint32_t pwm_ch3h_int : 1; /* [ 7], r, 0x0 */ - uint32_t pwm_prde_int : 1; /* [ 8], r, 0x0 */ - uint32_t pwm_brk_int : 1; /* [ 9], r, 0x0 */ - uint32_t pwm_rept_int : 1; /* [ 10], r, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_sts; - - /* 0x24 : pwm_int_mask */ - union { - struct { - uint32_t cr_pwm_ch0l_mask : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_mask : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_mask : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_mask : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_mask : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_mask : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_mask : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_mask : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_pwm_rept_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_mask; - - /* 0x28 : pwm_int_clear */ - union { - struct { - uint32_t cr_pwm_ch0l_clr : 1; /* [ 0], w1c, 0x0 */ - uint32_t cr_pwm_ch0h_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t cr_pwm_ch1l_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t cr_pwm_ch1h_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t cr_pwm_ch2l_clr : 1; /* [ 4], w1c, 0x0 */ - uint32_t cr_pwm_ch2h_clr : 1; /* [ 5], w1c, 0x0 */ - uint32_t cr_pwm_ch3l_clr : 1; /* [ 6], w1c, 0x0 */ - uint32_t cr_pwm_ch3h_clr : 1; /* [ 7], w1c, 0x0 */ - uint32_t cr_pwm_prde_clr : 1; /* [ 8], w1c, 0x0 */ - uint32_t cr_pwm_brk_clr : 1; /* [ 9], w1c, 0x0 */ - uint32_t cr_pwm_rept_clr : 1; /* [ 10], w1c, 0x0 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_clear; - - /* 0x2C : pwm_int_en */ - union { - struct { - uint32_t cr_pwm_ch0l_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_pwm_ch0h_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_pwm_ch1l_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_pwm_ch1h_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_pwm_ch2l_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_pwm_ch2h_en : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_pwm_ch3l_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_pwm_ch3h_en : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_pwm_prde_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_pwm_brk_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_pwm_rept_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t reserved_11_31 : 21; /* [31:11], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } pwm_int_en; -}; - -typedef volatile struct pwm_channel_reg pwm_channel_reg_t; - -#define PWM_CHANNEL_OFFSET 0x40 - -#endif /* __PWM_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_dbg_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_dbg_reg.h deleted file mode 100644 index acde0e77f7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_dbg_reg.h +++ /dev/null @@ -1,209 +0,0 @@ -/** - ****************************************************************************** - * @file sec_dbg_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __SEC_DBG_REG_H__ -#define __SEC_DBG_REG_H__ - -#include "bl808.h" - -/* 0x0 : sd_chip_id_low */ -#define SEC_DBG_SD_CHIP_ID_LOW_OFFSET (0x0) -#define SEC_DBG_SD_CHIP_ID_LOW SEC_DBG_SD_CHIP_ID_LOW -#define SEC_DBG_SD_CHIP_ID_LOW_POS (0U) -#define SEC_DBG_SD_CHIP_ID_LOW_LEN (32U) -#define SEC_DBG_SD_CHIP_ID_LOW_MSK (((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS) -#define SEC_DBG_SD_CHIP_ID_LOW_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_LOW_LEN) - 1) << SEC_DBG_SD_CHIP_ID_LOW_POS)) - -/* 0x4 : sd_chip_id_high */ -#define SEC_DBG_SD_CHIP_ID_HIGH_OFFSET (0x4) -#define SEC_DBG_SD_CHIP_ID_HIGH SEC_DBG_SD_CHIP_ID_HIGH -#define SEC_DBG_SD_CHIP_ID_HIGH_POS (0U) -#define SEC_DBG_SD_CHIP_ID_HIGH_LEN (32U) -#define SEC_DBG_SD_CHIP_ID_HIGH_MSK (((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS) -#define SEC_DBG_SD_CHIP_ID_HIGH_UMSK (~(((1U << SEC_DBG_SD_CHIP_ID_HIGH_LEN) - 1) << SEC_DBG_SD_CHIP_ID_HIGH_POS)) - -/* 0x8 : sd_dbg_pwd_low */ -#define SEC_DBG_SD_DBG_PWD_LOW_OFFSET (0x8) -#define SEC_DBG_SD_DBG_PWD_LOW SEC_DBG_SD_DBG_PWD_LOW -#define SEC_DBG_SD_DBG_PWD_LOW_POS (0U) -#define SEC_DBG_SD_DBG_PWD_LOW_LEN (32U) -#define SEC_DBG_SD_DBG_PWD_LOW_MSK (((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS) -#define SEC_DBG_SD_DBG_PWD_LOW_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD_LOW_POS)) - -/* 0xC : sd_dbg_pwd_high */ -#define SEC_DBG_SD_DBG_PWD_HIGH_OFFSET (0xC) -#define SEC_DBG_SD_DBG_PWD_HIGH SEC_DBG_SD_DBG_PWD_HIGH -#define SEC_DBG_SD_DBG_PWD_HIGH_POS (0U) -#define SEC_DBG_SD_DBG_PWD_HIGH_LEN (32U) -#define SEC_DBG_SD_DBG_PWD_HIGH_MSK (((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS) -#define SEC_DBG_SD_DBG_PWD_HIGH_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD_HIGH_POS)) - -/* 0x10 : sd_dbg_pwd2_low */ -#define SEC_DBG_SD_DBG_PWD2_LOW_OFFSET (0x10) -#define SEC_DBG_SD_DBG_PWD2_LOW SEC_DBG_SD_DBG_PWD2_LOW -#define SEC_DBG_SD_DBG_PWD2_LOW_POS (0U) -#define SEC_DBG_SD_DBG_PWD2_LOW_LEN (32U) -#define SEC_DBG_SD_DBG_PWD2_LOW_MSK (((1U << SEC_DBG_SD_DBG_PWD2_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_LOW_POS) -#define SEC_DBG_SD_DBG_PWD2_LOW_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD2_LOW_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_LOW_POS)) - -/* 0x14 : sd_dbg_pwd2_high */ -#define SEC_DBG_SD_DBG_PWD2_HIGH_OFFSET (0x14) -#define SEC_DBG_SD_DBG_PWD2_HIGH SEC_DBG_SD_DBG_PWD2_HIGH -#define SEC_DBG_SD_DBG_PWD2_HIGH_POS (0U) -#define SEC_DBG_SD_DBG_PWD2_HIGH_LEN (32U) -#define SEC_DBG_SD_DBG_PWD2_HIGH_MSK (((1U << SEC_DBG_SD_DBG_PWD2_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_HIGH_POS) -#define SEC_DBG_SD_DBG_PWD2_HIGH_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD2_HIGH_LEN) - 1) << SEC_DBG_SD_DBG_PWD2_HIGH_POS)) - -/* 0x18 : sd_status */ -#define SEC_DBG_SD_STATUS_OFFSET (0x18) -#define SEC_DBG_SD_DBG_PWD_BUSY SEC_DBG_SD_DBG_PWD_BUSY -#define SEC_DBG_SD_DBG_PWD_BUSY_POS (0U) -#define SEC_DBG_SD_DBG_PWD_BUSY_LEN (1U) -#define SEC_DBG_SD_DBG_PWD_BUSY_MSK (((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS) -#define SEC_DBG_SD_DBG_PWD_BUSY_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_BUSY_LEN) - 1) << SEC_DBG_SD_DBG_PWD_BUSY_POS)) -#define SEC_DBG_SD_DBG_PWD_TRIG SEC_DBG_SD_DBG_PWD_TRIG -#define SEC_DBG_SD_DBG_PWD_TRIG_POS (1U) -#define SEC_DBG_SD_DBG_PWD_TRIG_LEN (1U) -#define SEC_DBG_SD_DBG_PWD_TRIG_MSK (((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS) -#define SEC_DBG_SD_DBG_PWD_TRIG_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_TRIG_LEN) - 1) << SEC_DBG_SD_DBG_PWD_TRIG_POS)) -#define SEC_DBG_SD_DBG_CCI_READ_EN SEC_DBG_SD_DBG_CCI_READ_EN -#define SEC_DBG_SD_DBG_CCI_READ_EN_POS (2U) -#define SEC_DBG_SD_DBG_CCI_READ_EN_LEN (1U) -#define SEC_DBG_SD_DBG_CCI_READ_EN_MSK (((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS) -#define SEC_DBG_SD_DBG_CCI_READ_EN_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_READ_EN_LEN) - 1) << SEC_DBG_SD_DBG_CCI_READ_EN_POS)) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL SEC_DBG_SD_DBG_CCI_CLK_SEL -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_POS (3U) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN (1U) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_MSK (((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS) -#define SEC_DBG_SD_DBG_CCI_CLK_SEL_UMSK (~(((1U << SEC_DBG_SD_DBG_CCI_CLK_SEL_LEN) - 1) << SEC_DBG_SD_DBG_CCI_CLK_SEL_POS)) -#define SEC_DBG_SD_DBG_PWD_CNT SEC_DBG_SD_DBG_PWD_CNT -#define SEC_DBG_SD_DBG_PWD_CNT_POS (4U) -#define SEC_DBG_SD_DBG_PWD_CNT_LEN (20U) -#define SEC_DBG_SD_DBG_PWD_CNT_MSK (((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS) -#define SEC_DBG_SD_DBG_PWD_CNT_UMSK (~(((1U << SEC_DBG_SD_DBG_PWD_CNT_LEN) - 1) << SEC_DBG_SD_DBG_PWD_CNT_POS)) -#define SEC_DBG_SD_DBG_MODE SEC_DBG_SD_DBG_MODE -#define SEC_DBG_SD_DBG_MODE_POS (24U) -#define SEC_DBG_SD_DBG_MODE_LEN (4U) -#define SEC_DBG_SD_DBG_MODE_MSK (((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS) -#define SEC_DBG_SD_DBG_MODE_UMSK (~(((1U << SEC_DBG_SD_DBG_MODE_LEN) - 1) << SEC_DBG_SD_DBG_MODE_POS)) -#define SEC_DBG_SD_DBG_ENA SEC_DBG_SD_DBG_ENA -#define SEC_DBG_SD_DBG_ENA_POS (28U) -#define SEC_DBG_SD_DBG_ENA_LEN (4U) -#define SEC_DBG_SD_DBG_ENA_MSK (((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS) -#define SEC_DBG_SD_DBG_ENA_UMSK (~(((1U << SEC_DBG_SD_DBG_ENA_LEN) - 1) << SEC_DBG_SD_DBG_ENA_POS)) - -/* 0x1C : sd_dbg_reserved */ -#define SEC_DBG_SD_DBG_RESERVED_OFFSET (0x1C) -#define SEC_DBG_SD_DBG_RESERVED SEC_DBG_SD_DBG_RESERVED -#define SEC_DBG_SD_DBG_RESERVED_POS (0U) -#define SEC_DBG_SD_DBG_RESERVED_LEN (32U) -#define SEC_DBG_SD_DBG_RESERVED_MSK (((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS) -#define SEC_DBG_SD_DBG_RESERVED_UMSK (~(((1U << SEC_DBG_SD_DBG_RESERVED_LEN) - 1) << SEC_DBG_SD_DBG_RESERVED_POS)) - -struct sec_dbg_reg { - /* 0x0 : sd_chip_id_low */ - union { - struct { - uint32_t sd_chip_id_low : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } sd_chip_id_low; - - /* 0x4 : sd_chip_id_high */ - union { - struct { - uint32_t sd_chip_id_high : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } sd_chip_id_high; - - /* 0x8 : sd_dbg_pwd_low */ - union { - struct { - uint32_t sd_dbg_pwd_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd_low; - - /* 0xC : sd_dbg_pwd_high */ - union { - struct { - uint32_t sd_dbg_pwd_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd_high; - - /* 0x10 : sd_dbg_pwd2_low */ - union { - struct { - uint32_t sd_dbg_pwd2_low : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd2_low; - - /* 0x14 : sd_dbg_pwd2_high */ - union { - struct { - uint32_t sd_dbg_pwd2_high : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } sd_dbg_pwd2_high; - - /* 0x18 : sd_status */ - union { - struct { - uint32_t sd_dbg_pwd_busy : 1; /* [ 0], r, 0x0 */ - uint32_t sd_dbg_pwd_trig : 1; /* [ 1], r/w, 0x0 */ - uint32_t sd_dbg_cci_read_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t sd_dbg_cci_clk_sel : 1; /* [ 3], r/w, 0x0 */ - uint32_t sd_dbg_pwd_cnt : 20; /* [23: 4], r, 0x0 */ - uint32_t sd_dbg_mode : 4; /* [27:24], r, 0x0 */ - uint32_t sd_dbg_ena : 4; /* [31:28], r, 0x0 */ - } BF; - uint32_t WORD; - } sd_status; - - /* 0x1C : sd_dbg_reserved */ - union { - struct { - uint32_t sd_dbg_reserved : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } sd_dbg_reserved; -}; - -typedef volatile struct sec_dbg_reg sec_dbg_reg_t; - -#endif /* __SEC_DBG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_eng_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_eng_reg.h deleted file mode 100644 index e3ea2ef9e9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sec_eng_reg.h +++ /dev/null @@ -1,1966 +0,0 @@ -/** - ****************************************************************************** - * @file sec_eng_reg.h - * @version V1.0 - * @date 2021-07-13 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __SEC_ENG_REG_H__ -#define __SEC_ENG_REG_H__ - -#include "bl808.h" - -/* 0x0 : se_sha_0_ctrl */ -#define SEC_ENG_SE_SHA_0_CTRL_OFFSET (0x0) -#define SEC_ENG_SE_SHA_0_BUSY SEC_ENG_SE_SHA_0_BUSY -#define SEC_ENG_SE_SHA_0_BUSY_POS (0U) -#define SEC_ENG_SE_SHA_0_BUSY_LEN (1U) -#define SEC_ENG_SE_SHA_0_BUSY_MSK (((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS) -#define SEC_ENG_SE_SHA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_SHA_0_BUSY_LEN) - 1) << SEC_ENG_SE_SHA_0_BUSY_POS)) -#define SEC_ENG_SE_SHA_0_TRIG_1T SEC_ENG_SE_SHA_0_TRIG_1T -#define SEC_ENG_SE_SHA_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_SHA_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_SHA_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS) -#define SEC_ENG_SE_SHA_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_TRIG_1T_POS)) -#define SEC_ENG_SE_SHA_0_MODE SEC_ENG_SE_SHA_0_MODE -#define SEC_ENG_SE_SHA_0_MODE_POS (2U) -#define SEC_ENG_SE_SHA_0_MODE_LEN (3U) -#define SEC_ENG_SE_SHA_0_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS) -#define SEC_ENG_SE_SHA_0_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_POS)) -#define SEC_ENG_SE_SHA_0_EN SEC_ENG_SE_SHA_0_EN -#define SEC_ENG_SE_SHA_0_EN_POS (5U) -#define SEC_ENG_SE_SHA_0_EN_LEN (1U) -#define SEC_ENG_SE_SHA_0_EN_MSK (((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS) -#define SEC_ENG_SE_SHA_0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_EN_LEN) - 1) << SEC_ENG_SE_SHA_0_EN_POS)) -#define SEC_ENG_SE_SHA_0_HASH_SEL SEC_ENG_SE_SHA_0_HASH_SEL -#define SEC_ENG_SE_SHA_0_HASH_SEL_POS (6U) -#define SEC_ENG_SE_SHA_0_HASH_SEL_LEN (1U) -#define SEC_ENG_SE_SHA_0_HASH_SEL_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS) -#define SEC_ENG_SE_SHA_0_HASH_SEL_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_SEL_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_SEL_POS)) -#define SEC_ENG_SE_SHA_0_INT SEC_ENG_SE_SHA_0_INT -#define SEC_ENG_SE_SHA_0_INT_POS (8U) -#define SEC_ENG_SE_SHA_0_INT_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_MSK (((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS) -#define SEC_ENG_SE_SHA_0_INT_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_POS)) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T SEC_ENG_SE_SHA_0_INT_CLR_1T -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_SHA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_SHA_0_INT_SET_1T SEC_ENG_SE_SHA_0_INT_SET_1T -#define SEC_ENG_SE_SHA_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_SHA_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS) -#define SEC_ENG_SE_SHA_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_SHA_0_INT_MASK SEC_ENG_SE_SHA_0_INT_MASK -#define SEC_ENG_SE_SHA_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_SHA_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_SHA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS) -#define SEC_ENG_SE_SHA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_SHA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_SHA_0_INT_MASK_POS)) -#define SEC_ENG_SE_SHA_0_MODE_EXT SEC_ENG_SE_SHA_0_MODE_EXT -#define SEC_ENG_SE_SHA_0_MODE_EXT_POS (12U) -#define SEC_ENG_SE_SHA_0_MODE_EXT_LEN (2U) -#define SEC_ENG_SE_SHA_0_MODE_EXT_MSK (((1U << SEC_ENG_SE_SHA_0_MODE_EXT_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_EXT_POS) -#define SEC_ENG_SE_SHA_0_MODE_EXT_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MODE_EXT_LEN) - 1) << SEC_ENG_SE_SHA_0_MODE_EXT_POS)) -#define SEC_ENG_SE_SHA_0_LINK_MODE SEC_ENG_SE_SHA_0_LINK_MODE -#define SEC_ENG_SE_SHA_0_LINK_MODE_POS (15U) -#define SEC_ENG_SE_SHA_0_LINK_MODE_LEN (1U) -#define SEC_ENG_SE_SHA_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS) -#define SEC_ENG_SE_SHA_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_SHA_0_LINK_MODE_POS)) -#define SEC_ENG_SE_SHA_0_MSG_LEN SEC_ENG_SE_SHA_0_MSG_LEN -#define SEC_ENG_SE_SHA_0_MSG_LEN_POS (16U) -#define SEC_ENG_SE_SHA_0_MSG_LEN_LEN (16U) -#define SEC_ENG_SE_SHA_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS) -#define SEC_ENG_SE_SHA_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_SHA_0_MSG_LEN_POS)) - -/* 0x4 : se_sha_0_msa */ -#define SEC_ENG_SE_SHA_0_MSA_OFFSET (0x4) -#define SEC_ENG_SE_SHA_0_MSA SEC_ENG_SE_SHA_0_MSA -#define SEC_ENG_SE_SHA_0_MSA_POS (0U) -#define SEC_ENG_SE_SHA_0_MSA_LEN (32U) -#define SEC_ENG_SE_SHA_0_MSA_MSK (((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS) -#define SEC_ENG_SE_SHA_0_MSA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_MSA_LEN) - 1) << SEC_ENG_SE_SHA_0_MSA_POS)) - -/* 0x8 : se_sha_0_status */ -#define SEC_ENG_SE_SHA_0_STATUS_OFFSET (0x8) -#define SEC_ENG_SE_SHA_0_STATUS SEC_ENG_SE_SHA_0_STATUS -#define SEC_ENG_SE_SHA_0_STATUS_POS (0U) -#define SEC_ENG_SE_SHA_0_STATUS_LEN (32U) -#define SEC_ENG_SE_SHA_0_STATUS_MSK (((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS) -#define SEC_ENG_SE_SHA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_SHA_0_STATUS_LEN) - 1) << SEC_ENG_SE_SHA_0_STATUS_POS)) - -/* 0xC : se_sha_0_endian */ -#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET (0xC) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN SEC_ENG_SE_SHA_0_DOUT_ENDIAN -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS (0U) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN (1U) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS) -#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_SHA_0_DOUT_ENDIAN_POS)) - -/* 0x10 : se_sha_0_hash_l_0 */ -#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET (0x10) -#define SEC_ENG_SE_SHA_0_HASH_L_0 SEC_ENG_SE_SHA_0_HASH_L_0 -#define SEC_ENG_SE_SHA_0_HASH_L_0_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_0_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_0_POS)) - -/* 0x14 : se_sha_0_hash_l_1 */ -#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET (0x14) -#define SEC_ENG_SE_SHA_0_HASH_L_1 SEC_ENG_SE_SHA_0_HASH_L_1 -#define SEC_ENG_SE_SHA_0_HASH_L_1_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_1_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_1_POS)) - -/* 0x18 : se_sha_0_hash_l_2 */ -#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET (0x18) -#define SEC_ENG_SE_SHA_0_HASH_L_2 SEC_ENG_SE_SHA_0_HASH_L_2 -#define SEC_ENG_SE_SHA_0_HASH_L_2_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_2_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_2_POS)) - -/* 0x1C : se_sha_0_hash_l_3 */ -#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET (0x1C) -#define SEC_ENG_SE_SHA_0_HASH_L_3 SEC_ENG_SE_SHA_0_HASH_L_3 -#define SEC_ENG_SE_SHA_0_HASH_L_3_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_3_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_3_POS)) - -/* 0x20 : se_sha_0_hash_l_4 */ -#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET (0x20) -#define SEC_ENG_SE_SHA_0_HASH_L_4 SEC_ENG_SE_SHA_0_HASH_L_4 -#define SEC_ENG_SE_SHA_0_HASH_L_4_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_4_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_4_POS)) - -/* 0x24 : se_sha_0_hash_l_5 */ -#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET (0x24) -#define SEC_ENG_SE_SHA_0_HASH_L_5 SEC_ENG_SE_SHA_0_HASH_L_5 -#define SEC_ENG_SE_SHA_0_HASH_L_5_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_5_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_5_POS)) - -/* 0x28 : se_sha_0_hash_l_6 */ -#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET (0x28) -#define SEC_ENG_SE_SHA_0_HASH_L_6 SEC_ENG_SE_SHA_0_HASH_L_6 -#define SEC_ENG_SE_SHA_0_HASH_L_6_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_6_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_6_POS)) - -/* 0x2C : se_sha_0_hash_l_7 */ -#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET (0x2C) -#define SEC_ENG_SE_SHA_0_HASH_L_7 SEC_ENG_SE_SHA_0_HASH_L_7 -#define SEC_ENG_SE_SHA_0_HASH_L_7_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_L_7_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_L_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS) -#define SEC_ENG_SE_SHA_0_HASH_L_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_L_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_L_7_POS)) - -/* 0x30 : se_sha_0_hash_h_0 */ -#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET (0x30) -#define SEC_ENG_SE_SHA_0_HASH_H_0 SEC_ENG_SE_SHA_0_HASH_H_0 -#define SEC_ENG_SE_SHA_0_HASH_H_0_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_0_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_0_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_0_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_0_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_0_POS)) - -/* 0x34 : se_sha_0_hash_h_1 */ -#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET (0x34) -#define SEC_ENG_SE_SHA_0_HASH_H_1 SEC_ENG_SE_SHA_0_HASH_H_1 -#define SEC_ENG_SE_SHA_0_HASH_H_1_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_1_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_1_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_1_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_1_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_1_POS)) - -/* 0x38 : se_sha_0_hash_h_2 */ -#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET (0x38) -#define SEC_ENG_SE_SHA_0_HASH_H_2 SEC_ENG_SE_SHA_0_HASH_H_2 -#define SEC_ENG_SE_SHA_0_HASH_H_2_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_2_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_2_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_2_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_2_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_2_POS)) - -/* 0x3C : se_sha_0_hash_h_3 */ -#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET (0x3C) -#define SEC_ENG_SE_SHA_0_HASH_H_3 SEC_ENG_SE_SHA_0_HASH_H_3 -#define SEC_ENG_SE_SHA_0_HASH_H_3_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_3_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_3_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_3_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_3_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_3_POS)) - -/* 0x40 : se_sha_0_hash_h_4 */ -#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET (0x40) -#define SEC_ENG_SE_SHA_0_HASH_H_4 SEC_ENG_SE_SHA_0_HASH_H_4 -#define SEC_ENG_SE_SHA_0_HASH_H_4_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_4_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_4_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_4_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_4_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_4_POS)) - -/* 0x44 : se_sha_0_hash_h_5 */ -#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET (0x44) -#define SEC_ENG_SE_SHA_0_HASH_H_5 SEC_ENG_SE_SHA_0_HASH_H_5 -#define SEC_ENG_SE_SHA_0_HASH_H_5_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_5_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_5_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_5_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_5_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_5_POS)) - -/* 0x48 : se_sha_0_hash_h_6 */ -#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET (0x48) -#define SEC_ENG_SE_SHA_0_HASH_H_6 SEC_ENG_SE_SHA_0_HASH_H_6 -#define SEC_ENG_SE_SHA_0_HASH_H_6_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_6_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_6_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_6_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_6_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_6_POS)) - -/* 0x4C : se_sha_0_hash_h_7 */ -#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET (0x4C) -#define SEC_ENG_SE_SHA_0_HASH_H_7 SEC_ENG_SE_SHA_0_HASH_H_7 -#define SEC_ENG_SE_SHA_0_HASH_H_7_POS (0U) -#define SEC_ENG_SE_SHA_0_HASH_H_7_LEN (32U) -#define SEC_ENG_SE_SHA_0_HASH_H_7_MSK (((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS) -#define SEC_ENG_SE_SHA_0_HASH_H_7_UMSK (~(((1U << SEC_ENG_SE_SHA_0_HASH_H_7_LEN) - 1) << SEC_ENG_SE_SHA_0_HASH_H_7_POS)) - -/* 0x50 : se_sha_0_link */ -#define SEC_ENG_SE_SHA_0_LINK_OFFSET (0x50) -#define SEC_ENG_SE_SHA_0_LCA SEC_ENG_SE_SHA_0_LCA -#define SEC_ENG_SE_SHA_0_LCA_POS (0U) -#define SEC_ENG_SE_SHA_0_LCA_LEN (32U) -#define SEC_ENG_SE_SHA_0_LCA_MSK (((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS) -#define SEC_ENG_SE_SHA_0_LCA_UMSK (~(((1U << SEC_ENG_SE_SHA_0_LCA_LEN) - 1) << SEC_ENG_SE_SHA_0_LCA_POS)) - -/* 0xFC : se_sha_0_ctrl_prot */ -#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET (0xFC) -#define SEC_ENG_SE_SHA_ID0_EN SEC_ENG_SE_SHA_ID0_EN -#define SEC_ENG_SE_SHA_ID0_EN_POS (1U) -#define SEC_ENG_SE_SHA_ID0_EN_LEN (1U) -#define SEC_ENG_SE_SHA_ID0_EN_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS) -#define SEC_ENG_SE_SHA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_POS)) -#define SEC_ENG_SE_SHA_ID1_EN SEC_ENG_SE_SHA_ID1_EN -#define SEC_ENG_SE_SHA_ID1_EN_POS (2U) -#define SEC_ENG_SE_SHA_ID1_EN_LEN (1U) -#define SEC_ENG_SE_SHA_ID1_EN_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS) -#define SEC_ENG_SE_SHA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_POS)) - -/* 0x100 : se_aes_0_ctrl */ -#define SEC_ENG_SE_AES_0_CTRL_OFFSET (0x100) -#define SEC_ENG_SE_AES_0_BUSY SEC_ENG_SE_AES_0_BUSY -#define SEC_ENG_SE_AES_0_BUSY_POS (0U) -#define SEC_ENG_SE_AES_0_BUSY_LEN (1U) -#define SEC_ENG_SE_AES_0_BUSY_MSK (((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS) -#define SEC_ENG_SE_AES_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_AES_0_BUSY_LEN) - 1) << SEC_ENG_SE_AES_0_BUSY_POS)) -#define SEC_ENG_SE_AES_0_TRIG_1T SEC_ENG_SE_AES_0_TRIG_1T -#define SEC_ENG_SE_AES_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_AES_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_AES_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS) -#define SEC_ENG_SE_AES_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_AES_0_TRIG_1T_POS)) -#define SEC_ENG_SE_AES_0_EN SEC_ENG_SE_AES_0_EN -#define SEC_ENG_SE_AES_0_EN_POS (2U) -#define SEC_ENG_SE_AES_0_EN_LEN (1U) -#define SEC_ENG_SE_AES_0_EN_MSK (((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS) -#define SEC_ENG_SE_AES_0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_EN_LEN) - 1) << SEC_ENG_SE_AES_0_EN_POS)) -#define SEC_ENG_SE_AES_0_MODE SEC_ENG_SE_AES_0_MODE -#define SEC_ENG_SE_AES_0_MODE_POS (3U) -#define SEC_ENG_SE_AES_0_MODE_LEN (2U) -#define SEC_ENG_SE_AES_0_MODE_MSK (((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS) -#define SEC_ENG_SE_AES_0_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_MODE_POS)) -#define SEC_ENG_SE_AES_0_DEC_EN SEC_ENG_SE_AES_0_DEC_EN -#define SEC_ENG_SE_AES_0_DEC_EN_POS (5U) -#define SEC_ENG_SE_AES_0_DEC_EN_LEN (1U) -#define SEC_ENG_SE_AES_0_DEC_EN_MSK (((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS) -#define SEC_ENG_SE_AES_0_DEC_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_EN_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_EN_POS)) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL SEC_ENG_SE_AES_0_DEC_KEY_SEL -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS (6U) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN (1U) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS) -#define SEC_ENG_SE_AES_0_DEC_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_DEC_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_DEC_KEY_SEL_POS)) -#define SEC_ENG_SE_AES_0_HW_KEY_EN SEC_ENG_SE_AES_0_HW_KEY_EN -#define SEC_ENG_SE_AES_0_HW_KEY_EN_POS (7U) -#define SEC_ENG_SE_AES_0_HW_KEY_EN_LEN (1U) -#define SEC_ENG_SE_AES_0_HW_KEY_EN_MSK (((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS) -#define SEC_ENG_SE_AES_0_HW_KEY_EN_UMSK (~(((1U << SEC_ENG_SE_AES_0_HW_KEY_EN_LEN) - 1) << SEC_ENG_SE_AES_0_HW_KEY_EN_POS)) -#define SEC_ENG_SE_AES_0_INT SEC_ENG_SE_AES_0_INT -#define SEC_ENG_SE_AES_0_INT_POS (8U) -#define SEC_ENG_SE_AES_0_INT_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_MSK (((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS) -#define SEC_ENG_SE_AES_0_INT_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_LEN) - 1) << SEC_ENG_SE_AES_0_INT_POS)) -#define SEC_ENG_SE_AES_0_INT_CLR_1T SEC_ENG_SE_AES_0_INT_CLR_1T -#define SEC_ENG_SE_AES_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_AES_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_AES_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_AES_0_INT_SET_1T SEC_ENG_SE_AES_0_INT_SET_1T -#define SEC_ENG_SE_AES_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_AES_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS) -#define SEC_ENG_SE_AES_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_AES_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_AES_0_INT_MASK SEC_ENG_SE_AES_0_INT_MASK -#define SEC_ENG_SE_AES_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_AES_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_AES_0_INT_MASK_MSK (((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS) -#define SEC_ENG_SE_AES_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_AES_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_AES_0_INT_MASK_POS)) -#define SEC_ENG_SE_AES_0_BLOCK_MODE SEC_ENG_SE_AES_0_BLOCK_MODE -#define SEC_ENG_SE_AES_0_BLOCK_MODE_POS (12U) -#define SEC_ENG_SE_AES_0_BLOCK_MODE_LEN (2U) -#define SEC_ENG_SE_AES_0_BLOCK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS) -#define SEC_ENG_SE_AES_0_BLOCK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_BLOCK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_BLOCK_MODE_POS)) -#define SEC_ENG_SE_AES_0_IV_SEL SEC_ENG_SE_AES_0_IV_SEL -#define SEC_ENG_SE_AES_0_IV_SEL_POS (14U) -#define SEC_ENG_SE_AES_0_IV_SEL_LEN (1U) -#define SEC_ENG_SE_AES_0_IV_SEL_MSK (((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS) -#define SEC_ENG_SE_AES_0_IV_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_IV_SEL_POS)) -#define SEC_ENG_SE_AES_0_LINK_MODE SEC_ENG_SE_AES_0_LINK_MODE -#define SEC_ENG_SE_AES_0_LINK_MODE_POS (15U) -#define SEC_ENG_SE_AES_0_LINK_MODE_LEN (1U) -#define SEC_ENG_SE_AES_0_LINK_MODE_MSK (((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS) -#define SEC_ENG_SE_AES_0_LINK_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_LINK_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_LINK_MODE_POS)) -#define SEC_ENG_SE_AES_0_MSG_LEN SEC_ENG_SE_AES_0_MSG_LEN -#define SEC_ENG_SE_AES_0_MSG_LEN_POS (16U) -#define SEC_ENG_SE_AES_0_MSG_LEN_LEN (16U) -#define SEC_ENG_SE_AES_0_MSG_LEN_MSK (((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS) -#define SEC_ENG_SE_AES_0_MSG_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSG_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_MSG_LEN_POS)) - -/* 0x104 : se_aes_0_msa */ -#define SEC_ENG_SE_AES_0_MSA_OFFSET (0x104) -#define SEC_ENG_SE_AES_0_MSA SEC_ENG_SE_AES_0_MSA -#define SEC_ENG_SE_AES_0_MSA_POS (0U) -#define SEC_ENG_SE_AES_0_MSA_LEN (32U) -#define SEC_ENG_SE_AES_0_MSA_MSK (((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS) -#define SEC_ENG_SE_AES_0_MSA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MSA_LEN) - 1) << SEC_ENG_SE_AES_0_MSA_POS)) - -/* 0x108 : se_aes_0_mda */ -#define SEC_ENG_SE_AES_0_MDA_OFFSET (0x108) -#define SEC_ENG_SE_AES_0_MDA SEC_ENG_SE_AES_0_MDA -#define SEC_ENG_SE_AES_0_MDA_POS (0U) -#define SEC_ENG_SE_AES_0_MDA_LEN (32U) -#define SEC_ENG_SE_AES_0_MDA_MSK (((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS) -#define SEC_ENG_SE_AES_0_MDA_UMSK (~(((1U << SEC_ENG_SE_AES_0_MDA_LEN) - 1) << SEC_ENG_SE_AES_0_MDA_POS)) - -/* 0x10C : se_aes_0_status */ -#define SEC_ENG_SE_AES_0_STATUS_OFFSET (0x10C) -#define SEC_ENG_SE_AES_0_STATUS SEC_ENG_SE_AES_0_STATUS -#define SEC_ENG_SE_AES_0_STATUS_POS (0U) -#define SEC_ENG_SE_AES_0_STATUS_LEN (32U) -#define SEC_ENG_SE_AES_0_STATUS_MSK (((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS) -#define SEC_ENG_SE_AES_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_AES_0_STATUS_LEN) - 1) << SEC_ENG_SE_AES_0_STATUS_POS)) - -/* 0x110 : se_aes_0_iv_0 */ -#define SEC_ENG_SE_AES_0_IV_0_OFFSET (0x110) -#define SEC_ENG_SE_AES_0_IV_0 SEC_ENG_SE_AES_0_IV_0 -#define SEC_ENG_SE_AES_0_IV_0_POS (0U) -#define SEC_ENG_SE_AES_0_IV_0_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_0_MSK (((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS) -#define SEC_ENG_SE_AES_0_IV_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_0_LEN) - 1) << SEC_ENG_SE_AES_0_IV_0_POS)) - -/* 0x114 : se_aes_0_iv_1 */ -#define SEC_ENG_SE_AES_0_IV_1_OFFSET (0x114) -#define SEC_ENG_SE_AES_0_IV_1 SEC_ENG_SE_AES_0_IV_1 -#define SEC_ENG_SE_AES_0_IV_1_POS (0U) -#define SEC_ENG_SE_AES_0_IV_1_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_1_MSK (((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS) -#define SEC_ENG_SE_AES_0_IV_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_1_LEN) - 1) << SEC_ENG_SE_AES_0_IV_1_POS)) - -/* 0x118 : se_aes_0_iv_2 */ -#define SEC_ENG_SE_AES_0_IV_2_OFFSET (0x118) -#define SEC_ENG_SE_AES_0_IV_2 SEC_ENG_SE_AES_0_IV_2 -#define SEC_ENG_SE_AES_0_IV_2_POS (0U) -#define SEC_ENG_SE_AES_0_IV_2_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_2_MSK (((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS) -#define SEC_ENG_SE_AES_0_IV_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_2_LEN) - 1) << SEC_ENG_SE_AES_0_IV_2_POS)) - -/* 0x11C : se_aes_0_iv_3 */ -#define SEC_ENG_SE_AES_0_IV_3_OFFSET (0x11C) -#define SEC_ENG_SE_AES_0_IV_3 SEC_ENG_SE_AES_0_IV_3 -#define SEC_ENG_SE_AES_0_IV_3_POS (0U) -#define SEC_ENG_SE_AES_0_IV_3_LEN (32U) -#define SEC_ENG_SE_AES_0_IV_3_MSK (((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS) -#define SEC_ENG_SE_AES_0_IV_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_3_LEN) - 1) << SEC_ENG_SE_AES_0_IV_3_POS)) - -/* 0x120 : se_aes_0_key_0 */ -#define SEC_ENG_SE_AES_0_KEY_0_OFFSET (0x120) -#define SEC_ENG_SE_AES_0_KEY_0 SEC_ENG_SE_AES_0_KEY_0 -#define SEC_ENG_SE_AES_0_KEY_0_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_0_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_0_MSK (((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS) -#define SEC_ENG_SE_AES_0_KEY_0_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_0_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_0_POS)) - -/* 0x124 : se_aes_0_key_1 */ -#define SEC_ENG_SE_AES_0_KEY_1_OFFSET (0x124) -#define SEC_ENG_SE_AES_0_KEY_1 SEC_ENG_SE_AES_0_KEY_1 -#define SEC_ENG_SE_AES_0_KEY_1_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_1_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_1_MSK (((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS) -#define SEC_ENG_SE_AES_0_KEY_1_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_1_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_1_POS)) - -/* 0x128 : se_aes_0_key_2 */ -#define SEC_ENG_SE_AES_0_KEY_2_OFFSET (0x128) -#define SEC_ENG_SE_AES_0_KEY_2 SEC_ENG_SE_AES_0_KEY_2 -#define SEC_ENG_SE_AES_0_KEY_2_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_2_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_2_MSK (((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS) -#define SEC_ENG_SE_AES_0_KEY_2_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_2_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_2_POS)) - -/* 0x12C : se_aes_0_key_3 */ -#define SEC_ENG_SE_AES_0_KEY_3_OFFSET (0x12C) -#define SEC_ENG_SE_AES_0_KEY_3 SEC_ENG_SE_AES_0_KEY_3 -#define SEC_ENG_SE_AES_0_KEY_3_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_3_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_3_MSK (((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS) -#define SEC_ENG_SE_AES_0_KEY_3_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_3_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_3_POS)) - -/* 0x130 : se_aes_0_key_4 */ -#define SEC_ENG_SE_AES_0_KEY_4_OFFSET (0x130) -#define SEC_ENG_SE_AES_0_KEY_4 SEC_ENG_SE_AES_0_KEY_4 -#define SEC_ENG_SE_AES_0_KEY_4_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_4_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_4_MSK (((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS) -#define SEC_ENG_SE_AES_0_KEY_4_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_4_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_4_POS)) - -/* 0x134 : se_aes_0_key_5 */ -#define SEC_ENG_SE_AES_0_KEY_5_OFFSET (0x134) -#define SEC_ENG_SE_AES_0_KEY_5 SEC_ENG_SE_AES_0_KEY_5 -#define SEC_ENG_SE_AES_0_KEY_5_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_5_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_5_MSK (((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS) -#define SEC_ENG_SE_AES_0_KEY_5_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_5_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_5_POS)) - -/* 0x138 : se_aes_0_key_6 */ -#define SEC_ENG_SE_AES_0_KEY_6_OFFSET (0x138) -#define SEC_ENG_SE_AES_0_KEY_6 SEC_ENG_SE_AES_0_KEY_6 -#define SEC_ENG_SE_AES_0_KEY_6_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_6_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_6_MSK (((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS) -#define SEC_ENG_SE_AES_0_KEY_6_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_6_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_6_POS)) - -/* 0x13C : se_aes_0_key_7 */ -#define SEC_ENG_SE_AES_0_KEY_7_OFFSET (0x13C) -#define SEC_ENG_SE_AES_0_KEY_7 SEC_ENG_SE_AES_0_KEY_7 -#define SEC_ENG_SE_AES_0_KEY_7_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_7_LEN (32U) -#define SEC_ENG_SE_AES_0_KEY_7_MSK (((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS) -#define SEC_ENG_SE_AES_0_KEY_7_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_7_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_7_POS)) - -/* 0x140 : se_aes_0_key_sel */ -#define SEC_ENG_SE_AES_0_KEY_SEL_OFFSET (0x140) -#define SEC_ENG_SE_AES_0_KEY_SEL SEC_ENG_SE_AES_0_KEY_SEL -#define SEC_ENG_SE_AES_0_KEY_SEL_POS (0U) -#define SEC_ENG_SE_AES_0_KEY_SEL_LEN (2U) -#define SEC_ENG_SE_AES_0_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_POS) -#define SEC_ENG_SE_AES_0_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_SEL_POS)) - -/* 0x144 : se_aes_1_key_sel */ -#define SEC_ENG_SE_AES_1_KEY_SEL_OFFSET (0x144) -#define SEC_ENG_SE_AES_1_KEY_SEL SEC_ENG_SE_AES_1_KEY_SEL -#define SEC_ENG_SE_AES_1_KEY_SEL_POS (0U) -#define SEC_ENG_SE_AES_1_KEY_SEL_LEN (2U) -#define SEC_ENG_SE_AES_1_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_1_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_1_KEY_SEL_POS) -#define SEC_ENG_SE_AES_1_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_1_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_1_KEY_SEL_POS)) - -/* 0x148 : se_aes_0_endian */ -#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET (0x148) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN SEC_ENG_SE_AES_0_DOUT_ENDIAN -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS (0U) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_DOUT_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DOUT_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DOUT_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN SEC_ENG_SE_AES_0_DIN_ENDIAN -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_POS (1U) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_DIN_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_DIN_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_DIN_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN SEC_ENG_SE_AES_0_KEY_ENDIAN -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_POS (2U) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_KEY_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_KEY_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_KEY_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_IV_ENDIAN SEC_ENG_SE_AES_0_IV_ENDIAN -#define SEC_ENG_SE_AES_0_IV_ENDIAN_POS (3U) -#define SEC_ENG_SE_AES_0_IV_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_IV_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_IV_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_IV_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_IV_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN SEC_ENG_SE_AES_0_TWK_ENDIAN -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_POS (4U) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_LEN (1U) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_MSK (((1U << SEC_ENG_SE_AES_0_TWK_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_TWK_ENDIAN_POS) -#define SEC_ENG_SE_AES_0_TWK_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_AES_0_TWK_ENDIAN_LEN) - 1) << SEC_ENG_SE_AES_0_TWK_ENDIAN_POS)) -#define SEC_ENG_SE_AES_0_CTR_LEN SEC_ENG_SE_AES_0_CTR_LEN -#define SEC_ENG_SE_AES_0_CTR_LEN_POS (30U) -#define SEC_ENG_SE_AES_0_CTR_LEN_LEN (2U) -#define SEC_ENG_SE_AES_0_CTR_LEN_MSK (((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS) -#define SEC_ENG_SE_AES_0_CTR_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_CTR_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_CTR_LEN_POS)) - -/* 0x14C : se_aes_sboot */ -#define SEC_ENG_SE_AES_0_SBOOT_OFFSET (0x14C) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL SEC_ENG_SE_AES_0_SBOOT_KEY_SEL -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS (0U) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN (1U) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_MSK (((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS) -#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_UMSK (~(((1U << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_LEN) - 1) << SEC_ENG_SE_AES_0_SBOOT_KEY_SEL_POS)) -#define SEC_ENG_SE_AES_0_XTS_MODE SEC_ENG_SE_AES_0_XTS_MODE -#define SEC_ENG_SE_AES_0_XTS_MODE_POS (15U) -#define SEC_ENG_SE_AES_0_XTS_MODE_LEN (1U) -#define SEC_ENG_SE_AES_0_XTS_MODE_MSK (((1U << SEC_ENG_SE_AES_0_XTS_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_XTS_MODE_POS) -#define SEC_ENG_SE_AES_0_XTS_MODE_UMSK (~(((1U << SEC_ENG_SE_AES_0_XTS_MODE_LEN) - 1) << SEC_ENG_SE_AES_0_XTS_MODE_POS)) -#define SEC_ENG_SE_AES_0_UNI_LEN SEC_ENG_SE_AES_0_UNI_LEN -#define SEC_ENG_SE_AES_0_UNI_LEN_POS (16U) -#define SEC_ENG_SE_AES_0_UNI_LEN_LEN (16U) -#define SEC_ENG_SE_AES_0_UNI_LEN_MSK (((1U << SEC_ENG_SE_AES_0_UNI_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_UNI_LEN_POS) -#define SEC_ENG_SE_AES_0_UNI_LEN_UMSK (~(((1U << SEC_ENG_SE_AES_0_UNI_LEN_LEN) - 1) << SEC_ENG_SE_AES_0_UNI_LEN_POS)) - -/* 0x150 : se_aes_0_link */ -#define SEC_ENG_SE_AES_0_LINK_OFFSET (0x150) -#define SEC_ENG_SE_AES_0_LCA SEC_ENG_SE_AES_0_LCA -#define SEC_ENG_SE_AES_0_LCA_POS (0U) -#define SEC_ENG_SE_AES_0_LCA_LEN (32U) -#define SEC_ENG_SE_AES_0_LCA_MSK (((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS) -#define SEC_ENG_SE_AES_0_LCA_UMSK (~(((1U << SEC_ENG_SE_AES_0_LCA_LEN) - 1) << SEC_ENG_SE_AES_0_LCA_POS)) - -/* 0x1FC : se_aes_0_ctrl_prot */ -#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET (0x1FC) -#define SEC_ENG_SE_AES_ID0_EN SEC_ENG_SE_AES_ID0_EN -#define SEC_ENG_SE_AES_ID0_EN_POS (1U) -#define SEC_ENG_SE_AES_ID0_EN_LEN (1U) -#define SEC_ENG_SE_AES_ID0_EN_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS) -#define SEC_ENG_SE_AES_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_POS)) -#define SEC_ENG_SE_AES_ID1_EN SEC_ENG_SE_AES_ID1_EN -#define SEC_ENG_SE_AES_ID1_EN_POS (2U) -#define SEC_ENG_SE_AES_ID1_EN_LEN (1U) -#define SEC_ENG_SE_AES_ID1_EN_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS) -#define SEC_ENG_SE_AES_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_POS)) - -/* 0x200 : se_trng_0_ctrl_0 */ -#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET (0x200) -#define SEC_ENG_SE_TRNG_0_BUSY SEC_ENG_SE_TRNG_0_BUSY -#define SEC_ENG_SE_TRNG_0_BUSY_POS (0U) -#define SEC_ENG_SE_TRNG_0_BUSY_LEN (1U) -#define SEC_ENG_SE_TRNG_0_BUSY_MSK (((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS) -#define SEC_ENG_SE_TRNG_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_BUSY_LEN) - 1) << SEC_ENG_SE_TRNG_0_BUSY_POS)) -#define SEC_ENG_SE_TRNG_0_TRIG_1T SEC_ENG_SE_TRNG_0_TRIG_1T -#define SEC_ENG_SE_TRNG_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_TRNG_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS) -#define SEC_ENG_SE_TRNG_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_TRIG_1T_POS)) -#define SEC_ENG_SE_TRNG_0_EN SEC_ENG_SE_TRNG_0_EN -#define SEC_ENG_SE_TRNG_0_EN_POS (2U) -#define SEC_ENG_SE_TRNG_0_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS) -#define SEC_ENG_SE_TRNG_0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_EN_POS)) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T SEC_ENG_SE_TRNG_0_DOUT_CLR_1T -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS (3U) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_CLR_1T_POS)) -#define SEC_ENG_SE_TRNG_0_HT_ERROR SEC_ENG_SE_TRNG_0_HT_ERROR -#define SEC_ENG_SE_TRNG_0_HT_ERROR_POS (4U) -#define SEC_ENG_SE_TRNG_0_HT_ERROR_LEN (1U) -#define SEC_ENG_SE_TRNG_0_HT_ERROR_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS) -#define SEC_ENG_SE_TRNG_0_HT_ERROR_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ERROR_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ERROR_POS)) -#define SEC_ENG_SE_TRNG_0_INT SEC_ENG_SE_TRNG_0_INT -#define SEC_ENG_SE_TRNG_0_INT_POS (8U) -#define SEC_ENG_SE_TRNG_0_INT_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS) -#define SEC_ENG_SE_TRNG_0_INT_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_POS)) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T SEC_ENG_SE_TRNG_0_INT_CLR_1T -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_TRNG_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T SEC_ENG_SE_TRNG_0_INT_SET_1T -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS) -#define SEC_ENG_SE_TRNG_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_TRNG_0_INT_MASK SEC_ENG_SE_TRNG_0_INT_MASK -#define SEC_ENG_SE_TRNG_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_TRNG_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_TRNG_0_INT_MASK_MSK (((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS) -#define SEC_ENG_SE_TRNG_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_TRNG_0_INT_MASK_POS)) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS (13U) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN (1U) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS) -#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL_POS)) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED SEC_ENG_SE_TRNG_0_MANUAL_RESEED -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS (14U) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN (1U) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS) -#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_RESEED_POS)) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN SEC_ENG_SE_TRNG_0_MANUAL_EN -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_POS (15U) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS) -#define SEC_ENG_SE_TRNG_0_MANUAL_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_MANUAL_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_MANUAL_EN_POS)) - -/* 0x204 : se_trng_0_status */ -#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET (0x204) -#define SEC_ENG_SE_TRNG_0_STATUS SEC_ENG_SE_TRNG_0_STATUS -#define SEC_ENG_SE_TRNG_0_STATUS_POS (0U) -#define SEC_ENG_SE_TRNG_0_STATUS_LEN (32U) -#define SEC_ENG_SE_TRNG_0_STATUS_MSK (((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS) -#define SEC_ENG_SE_TRNG_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_STATUS_LEN) - 1) << SEC_ENG_SE_TRNG_0_STATUS_POS)) - -/* 0x208 : se_trng_0_dout_0 */ -#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET (0x208) -#define SEC_ENG_SE_TRNG_0_DOUT_0 SEC_ENG_SE_TRNG_0_DOUT_0 -#define SEC_ENG_SE_TRNG_0_DOUT_0_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_0_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_0_POS)) - -/* 0x20C : se_trng_0_dout_1 */ -#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET (0x20C) -#define SEC_ENG_SE_TRNG_0_DOUT_1 SEC_ENG_SE_TRNG_0_DOUT_1 -#define SEC_ENG_SE_TRNG_0_DOUT_1_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_1_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_1_POS)) - -/* 0x210 : se_trng_0_dout_2 */ -#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET (0x210) -#define SEC_ENG_SE_TRNG_0_DOUT_2 SEC_ENG_SE_TRNG_0_DOUT_2 -#define SEC_ENG_SE_TRNG_0_DOUT_2_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_2_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_2_POS)) - -/* 0x214 : se_trng_0_dout_3 */ -#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET (0x214) -#define SEC_ENG_SE_TRNG_0_DOUT_3 SEC_ENG_SE_TRNG_0_DOUT_3 -#define SEC_ENG_SE_TRNG_0_DOUT_3_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_3_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_3_POS)) - -/* 0x218 : se_trng_0_dout_4 */ -#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET (0x218) -#define SEC_ENG_SE_TRNG_0_DOUT_4 SEC_ENG_SE_TRNG_0_DOUT_4 -#define SEC_ENG_SE_TRNG_0_DOUT_4_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_4_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_4_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_4_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_4_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_4_POS)) - -/* 0x21C : se_trng_0_dout_5 */ -#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET (0x21C) -#define SEC_ENG_SE_TRNG_0_DOUT_5 SEC_ENG_SE_TRNG_0_DOUT_5 -#define SEC_ENG_SE_TRNG_0_DOUT_5_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_5_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_5_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_5_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_5_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_5_POS)) - -/* 0x220 : se_trng_0_dout_6 */ -#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET (0x220) -#define SEC_ENG_SE_TRNG_0_DOUT_6 SEC_ENG_SE_TRNG_0_DOUT_6 -#define SEC_ENG_SE_TRNG_0_DOUT_6_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_6_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_6_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_6_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_6_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_6_POS)) - -/* 0x224 : se_trng_0_dout_7 */ -#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET (0x224) -#define SEC_ENG_SE_TRNG_0_DOUT_7 SEC_ENG_SE_TRNG_0_DOUT_7 -#define SEC_ENG_SE_TRNG_0_DOUT_7_POS (0U) -#define SEC_ENG_SE_TRNG_0_DOUT_7_LEN (32U) -#define SEC_ENG_SE_TRNG_0_DOUT_7_MSK (((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS) -#define SEC_ENG_SE_TRNG_0_DOUT_7_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_DOUT_7_LEN) - 1) << SEC_ENG_SE_TRNG_0_DOUT_7_POS)) - -/* 0x228 : se_trng_0_test */ -#define SEC_ENG_SE_TRNG_0_TEST_OFFSET (0x228) -#define SEC_ENG_SE_TRNG_0_TEST_EN SEC_ENG_SE_TRNG_0_TEST_EN -#define SEC_ENG_SE_TRNG_0_TEST_EN_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS) -#define SEC_ENG_SE_TRNG_0_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_EN_POS)) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN SEC_ENG_SE_TRNG_0_CP_TEST_EN -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS (1U) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS) -#define SEC_ENG_SE_TRNG_0_CP_TEST_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_TEST_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_TEST_EN_POS)) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS SEC_ENG_SE_TRNG_0_CP_BYPASS -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_POS (2U) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN (1U) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS) -#define SEC_ENG_SE_TRNG_0_CP_BYPASS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_BYPASS_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_BYPASS_POS)) -#define SEC_ENG_SE_TRNG_0_HT_DIS SEC_ENG_SE_TRNG_0_HT_DIS -#define SEC_ENG_SE_TRNG_0_HT_DIS_POS (3U) -#define SEC_ENG_SE_TRNG_0_HT_DIS_LEN (1U) -#define SEC_ENG_SE_TRNG_0_HT_DIS_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS) -#define SEC_ENG_SE_TRNG_0_HT_DIS_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_DIS_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_DIS_POS)) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N SEC_ENG_SE_TRNG_0_HT_ALARM_N -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS (4U) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN (8U) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS) -#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_ALARM_N_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_ALARM_N_POS)) - -/* 0x22C : se_trng_0_ctrl_1 */ -#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET (0x22C) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB SEC_ENG_SE_TRNG_0_RESEED_N_LSB -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS (0U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN (32U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS) -#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_POS)) - -/* 0x230 : se_trng_0_ctrl_2 */ -#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET (0x230) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB SEC_ENG_SE_TRNG_0_RESEED_N_MSB -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS (0U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN (16U) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MSK (((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS) -#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_LEN) - 1) << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_POS)) - -/* 0x234 : se_trng_0_ctrl_3 */ -#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET (0x234) -#define SEC_ENG_SE_TRNG_0_CP_RATIO SEC_ENG_SE_TRNG_0_CP_RATIO -#define SEC_ENG_SE_TRNG_0_CP_RATIO_POS (0U) -#define SEC_ENG_SE_TRNG_0_CP_RATIO_LEN (8U) -#define SEC_ENG_SE_TRNG_0_CP_RATIO_MSK (((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS) -#define SEC_ENG_SE_TRNG_0_CP_RATIO_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_CP_RATIO_LEN) - 1) << SEC_ENG_SE_TRNG_0_CP_RATIO_POS)) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C SEC_ENG_SE_TRNG_0_HT_RCT_C -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_POS (8U) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN (8U) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS) -#define SEC_ENG_SE_TRNG_0_HT_RCT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_RCT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_RCT_C_POS)) -#define SEC_ENG_SE_TRNG_0_HT_APT_C SEC_ENG_SE_TRNG_0_HT_APT_C -#define SEC_ENG_SE_TRNG_0_HT_APT_C_POS (16U) -#define SEC_ENG_SE_TRNG_0_HT_APT_C_LEN (10U) -#define SEC_ENG_SE_TRNG_0_HT_APT_C_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS) -#define SEC_ENG_SE_TRNG_0_HT_APT_C_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_APT_C_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_APT_C_POS)) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN SEC_ENG_SE_TRNG_0_HT_OD_EN -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_POS (26U) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS) -#define SEC_ENG_SE_TRNG_0_HT_OD_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_HT_OD_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_HT_OD_EN_POS)) -#define SEC_ENG_SE_TRNG_0_ROSC_EN SEC_ENG_SE_TRNG_0_ROSC_EN -#define SEC_ENG_SE_TRNG_0_ROSC_EN_POS (31U) -#define SEC_ENG_SE_TRNG_0_ROSC_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_0_ROSC_EN_MSK (((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS) -#define SEC_ENG_SE_TRNG_0_ROSC_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_ROSC_EN_LEN) - 1) << SEC_ENG_SE_TRNG_0_ROSC_EN_POS)) - -/* 0x240 : se_trng_0_test_out_0 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0 SEC_ENG_SE_TRNG_0_TEST_OUT_0 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_0_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_0_POS)) - -/* 0x244 : se_trng_0_test_out_1 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1 SEC_ENG_SE_TRNG_0_TEST_OUT_1 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_1_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_1_POS)) - -/* 0x248 : se_trng_0_test_out_2 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2 SEC_ENG_SE_TRNG_0_TEST_OUT_2 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_2_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_2_POS)) - -/* 0x24C : se_trng_0_test_out_3 */ -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3 SEC_ENG_SE_TRNG_0_TEST_OUT_3 -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS (0U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN (32U) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MSK (((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS) -#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_UMSK (~(((1U << SEC_ENG_SE_TRNG_0_TEST_OUT_3_LEN) - 1) << SEC_ENG_SE_TRNG_0_TEST_OUT_3_POS)) - -/* 0x2FC : se_trng_0_ctrl_prot */ -#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET (0x2FC) -#define SEC_ENG_SE_TRNG_ID0_EN SEC_ENG_SE_TRNG_ID0_EN -#define SEC_ENG_SE_TRNG_ID0_EN_POS (1U) -#define SEC_ENG_SE_TRNG_ID0_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_ID0_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS) -#define SEC_ENG_SE_TRNG_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_POS)) -#define SEC_ENG_SE_TRNG_ID1_EN SEC_ENG_SE_TRNG_ID1_EN -#define SEC_ENG_SE_TRNG_ID1_EN_POS (2U) -#define SEC_ENG_SE_TRNG_ID1_EN_LEN (1U) -#define SEC_ENG_SE_TRNG_ID1_EN_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS) -#define SEC_ENG_SE_TRNG_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_POS)) - -/* 0x300 : se_pka_0_ctrl_0 */ -#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET (0x300) -#define SEC_ENG_SE_PKA_0_DONE SEC_ENG_SE_PKA_0_DONE -#define SEC_ENG_SE_PKA_0_DONE_POS (0U) -#define SEC_ENG_SE_PKA_0_DONE_LEN (1U) -#define SEC_ENG_SE_PKA_0_DONE_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS) -#define SEC_ENG_SE_PKA_0_DONE_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_POS)) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T SEC_ENG_SE_PKA_0_DONE_CLR_1T -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS (1U) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN (1U) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS) -#define SEC_ENG_SE_PKA_0_DONE_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_DONE_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_DONE_CLR_1T_POS)) -#define SEC_ENG_SE_PKA_0_BUSY SEC_ENG_SE_PKA_0_BUSY -#define SEC_ENG_SE_PKA_0_BUSY_POS (2U) -#define SEC_ENG_SE_PKA_0_BUSY_LEN (1U) -#define SEC_ENG_SE_PKA_0_BUSY_MSK (((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS) -#define SEC_ENG_SE_PKA_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_PKA_0_BUSY_LEN) - 1) << SEC_ENG_SE_PKA_0_BUSY_POS)) -#define SEC_ENG_SE_PKA_0_EN SEC_ENG_SE_PKA_0_EN -#define SEC_ENG_SE_PKA_0_EN_POS (3U) -#define SEC_ENG_SE_PKA_0_EN_LEN (1U) -#define SEC_ENG_SE_PKA_0_EN_MSK (((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS) -#define SEC_ENG_SE_PKA_0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_EN_LEN) - 1) << SEC_ENG_SE_PKA_0_EN_POS)) -#define SEC_ENG_SE_PKA_0_PROT_MD SEC_ENG_SE_PKA_0_PROT_MD -#define SEC_ENG_SE_PKA_0_PROT_MD_POS (4U) -#define SEC_ENG_SE_PKA_0_PROT_MD_LEN (4U) -#define SEC_ENG_SE_PKA_0_PROT_MD_MSK (((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS) -#define SEC_ENG_SE_PKA_0_PROT_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_PROT_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_PROT_MD_POS)) -#define SEC_ENG_SE_PKA_0_INT SEC_ENG_SE_PKA_0_INT -#define SEC_ENG_SE_PKA_0_INT_POS (8U) -#define SEC_ENG_SE_PKA_0_INT_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_MSK (((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS) -#define SEC_ENG_SE_PKA_0_INT_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_POS)) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T SEC_ENG_SE_PKA_0_INT_CLR_1T -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_PKA_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_PKA_0_INT_SET SEC_ENG_SE_PKA_0_INT_SET -#define SEC_ENG_SE_PKA_0_INT_SET_POS (10U) -#define SEC_ENG_SE_PKA_0_INT_SET_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_SET_MSK (((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS) -#define SEC_ENG_SE_PKA_0_INT_SET_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_SET_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_SET_POS)) -#define SEC_ENG_SE_PKA_0_INT_MASK SEC_ENG_SE_PKA_0_INT_MASK -#define SEC_ENG_SE_PKA_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_PKA_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_PKA_0_INT_MASK_MSK (((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS) -#define SEC_ENG_SE_PKA_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_PKA_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_PKA_0_INT_MASK_POS)) -#define SEC_ENG_SE_PKA_0_ENDIAN SEC_ENG_SE_PKA_0_ENDIAN -#define SEC_ENG_SE_PKA_0_ENDIAN_POS (12U) -#define SEC_ENG_SE_PKA_0_ENDIAN_LEN (1U) -#define SEC_ENG_SE_PKA_0_ENDIAN_MSK (((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS) -#define SEC_ENG_SE_PKA_0_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_PKA_0_ENDIAN_LEN) - 1) << SEC_ENG_SE_PKA_0_ENDIAN_POS)) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD SEC_ENG_SE_PKA_0_RAM_CLR_MD -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS (13U) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN (1U) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_MSK (((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS) -#define SEC_ENG_SE_PKA_0_RAM_CLR_MD_UMSK (~(((1U << SEC_ENG_SE_PKA_0_RAM_CLR_MD_LEN) - 1) << SEC_ENG_SE_PKA_0_RAM_CLR_MD_POS)) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T SEC_ENG_SE_PKA_0_STATUS_CLR_1T -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS (15U) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN (1U) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS) -#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_CLR_1T_POS)) -#define SEC_ENG_SE_PKA_0_STATUS SEC_ENG_SE_PKA_0_STATUS -#define SEC_ENG_SE_PKA_0_STATUS_POS (16U) -#define SEC_ENG_SE_PKA_0_STATUS_LEN (16U) -#define SEC_ENG_SE_PKA_0_STATUS_MSK (((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS) -#define SEC_ENG_SE_PKA_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_STATUS_LEN) - 1) << SEC_ENG_SE_PKA_0_STATUS_POS)) - -/* 0x30C : se_pka_0_seed */ -#define SEC_ENG_SE_PKA_0_SEED_OFFSET (0x30C) -#define SEC_ENG_SE_PKA_0_SEED SEC_ENG_SE_PKA_0_SEED -#define SEC_ENG_SE_PKA_0_SEED_POS (0U) -#define SEC_ENG_SE_PKA_0_SEED_LEN (32U) -#define SEC_ENG_SE_PKA_0_SEED_MSK (((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS) -#define SEC_ENG_SE_PKA_0_SEED_UMSK (~(((1U << SEC_ENG_SE_PKA_0_SEED_LEN) - 1) << SEC_ENG_SE_PKA_0_SEED_POS)) - -/* 0x310 : se_pka_0_ctrl_1 */ -#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET (0x310) -#define SEC_ENG_SE_PKA_0_HBURST SEC_ENG_SE_PKA_0_HBURST -#define SEC_ENG_SE_PKA_0_HBURST_POS (0U) -#define SEC_ENG_SE_PKA_0_HBURST_LEN (3U) -#define SEC_ENG_SE_PKA_0_HBURST_MSK (((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS) -#define SEC_ENG_SE_PKA_0_HBURST_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBURST_LEN) - 1) << SEC_ENG_SE_PKA_0_HBURST_POS)) -#define SEC_ENG_SE_PKA_0_HBYPASS SEC_ENG_SE_PKA_0_HBYPASS -#define SEC_ENG_SE_PKA_0_HBYPASS_POS (3U) -#define SEC_ENG_SE_PKA_0_HBYPASS_LEN (1U) -#define SEC_ENG_SE_PKA_0_HBYPASS_MSK (((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS) -#define SEC_ENG_SE_PKA_0_HBYPASS_UMSK (~(((1U << SEC_ENG_SE_PKA_0_HBYPASS_LEN) - 1) << SEC_ENG_SE_PKA_0_HBYPASS_POS)) - -/* 0x340 : se_pka_0_rw */ -#define SEC_ENG_SE_PKA_0_RW_OFFSET (0x340) - -/* 0x360 : se_pka_0_rw_burst */ -#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET (0x360) - -/* 0x3FC : se_pka_0_ctrl_prot */ -#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET (0x3FC) -#define SEC_ENG_SE_PKA_ID0_EN SEC_ENG_SE_PKA_ID0_EN -#define SEC_ENG_SE_PKA_ID0_EN_POS (1U) -#define SEC_ENG_SE_PKA_ID0_EN_LEN (1U) -#define SEC_ENG_SE_PKA_ID0_EN_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS) -#define SEC_ENG_SE_PKA_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_POS)) -#define SEC_ENG_SE_PKA_ID1_EN SEC_ENG_SE_PKA_ID1_EN -#define SEC_ENG_SE_PKA_ID1_EN_POS (2U) -#define SEC_ENG_SE_PKA_ID1_EN_LEN (1U) -#define SEC_ENG_SE_PKA_ID1_EN_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS) -#define SEC_ENG_SE_PKA_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_POS)) - -/* 0x400 : se_cdet_0_ctrl_0 */ -#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET (0x400) -#define SEC_ENG_SE_CDET_0_EN SEC_ENG_SE_CDET_0_EN -#define SEC_ENG_SE_CDET_0_EN_POS (0U) -#define SEC_ENG_SE_CDET_0_EN_LEN (1U) -#define SEC_ENG_SE_CDET_0_EN_MSK (((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS) -#define SEC_ENG_SE_CDET_0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_EN_LEN) - 1) << SEC_ENG_SE_CDET_0_EN_POS)) -#define SEC_ENG_SE_CDET_0_ERROR SEC_ENG_SE_CDET_0_ERROR -#define SEC_ENG_SE_CDET_0_ERROR_POS (1U) -#define SEC_ENG_SE_CDET_0_ERROR_LEN (1U) -#define SEC_ENG_SE_CDET_0_ERROR_MSK (((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS) -#define SEC_ENG_SE_CDET_0_ERROR_UMSK (~(((1U << SEC_ENG_SE_CDET_0_ERROR_LEN) - 1) << SEC_ENG_SE_CDET_0_ERROR_POS)) -#define SEC_ENG_SE_CDET_0_STATUS SEC_ENG_SE_CDET_0_STATUS -#define SEC_ENG_SE_CDET_0_STATUS_POS (2U) -#define SEC_ENG_SE_CDET_0_STATUS_LEN (14U) -#define SEC_ENG_SE_CDET_0_STATUS_MSK (((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS) -#define SEC_ENG_SE_CDET_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_CDET_0_STATUS_LEN) - 1) << SEC_ENG_SE_CDET_0_STATUS_POS)) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX SEC_ENG_SE_CDET_0_G_LOOP_MAX -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS (16U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN (8U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS) -#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MAX_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MAX_POS)) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN SEC_ENG_SE_CDET_0_G_LOOP_MIN -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS (24U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN (8U) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MSK (((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS) -#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_LOOP_MIN_LEN) - 1) << SEC_ENG_SE_CDET_0_G_LOOP_MIN_POS)) - -/* 0x404 : se_cdet_0_ctrl_1 */ -#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET (0x404) -#define SEC_ENG_SE_CDET_0_T_LOOP_N SEC_ENG_SE_CDET_0_T_LOOP_N -#define SEC_ENG_SE_CDET_0_T_LOOP_N_POS (0U) -#define SEC_ENG_SE_CDET_0_T_LOOP_N_LEN (8U) -#define SEC_ENG_SE_CDET_0_T_LOOP_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS) -#define SEC_ENG_SE_CDET_0_T_LOOP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_LOOP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_LOOP_N_POS)) -#define SEC_ENG_SE_CDET_0_T_DLY_N SEC_ENG_SE_CDET_0_T_DLY_N -#define SEC_ENG_SE_CDET_0_T_DLY_N_POS (8U) -#define SEC_ENG_SE_CDET_0_T_DLY_N_LEN (8U) -#define SEC_ENG_SE_CDET_0_T_DLY_N_MSK (((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS) -#define SEC_ENG_SE_CDET_0_T_DLY_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_T_DLY_N_LEN) - 1) << SEC_ENG_SE_CDET_0_T_DLY_N_POS)) -#define SEC_ENG_SE_CDET_0_G_SLP_N SEC_ENG_SE_CDET_0_G_SLP_N -#define SEC_ENG_SE_CDET_0_G_SLP_N_POS (16U) -#define SEC_ENG_SE_CDET_0_G_SLP_N_LEN (8U) -#define SEC_ENG_SE_CDET_0_G_SLP_N_MSK (((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS) -#define SEC_ENG_SE_CDET_0_G_SLP_N_UMSK (~(((1U << SEC_ENG_SE_CDET_0_G_SLP_N_LEN) - 1) << SEC_ENG_SE_CDET_0_G_SLP_N_POS)) - -/* 0x4FC : se_cdet_0_ctrl_prot */ -#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET (0x4FC) -#define SEC_ENG_SE_CDET_PROT_EN SEC_ENG_SE_CDET_PROT_EN -#define SEC_ENG_SE_CDET_PROT_EN_POS (0U) -#define SEC_ENG_SE_CDET_PROT_EN_LEN (1U) -#define SEC_ENG_SE_CDET_PROT_EN_MSK (((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS) -#define SEC_ENG_SE_CDET_PROT_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_PROT_EN_LEN) - 1) << SEC_ENG_SE_CDET_PROT_EN_POS)) -#define SEC_ENG_SE_CDET_ID0_EN SEC_ENG_SE_CDET_ID0_EN -#define SEC_ENG_SE_CDET_ID0_EN_POS (1U) -#define SEC_ENG_SE_CDET_ID0_EN_LEN (1U) -#define SEC_ENG_SE_CDET_ID0_EN_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS) -#define SEC_ENG_SE_CDET_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_POS)) -#define SEC_ENG_SE_CDET_ID1_EN SEC_ENG_SE_CDET_ID1_EN -#define SEC_ENG_SE_CDET_ID1_EN_POS (2U) -#define SEC_ENG_SE_CDET_ID1_EN_LEN (1U) -#define SEC_ENG_SE_CDET_ID1_EN_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS) -#define SEC_ENG_SE_CDET_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_POS)) - -/* 0x500 : se_gmac_0_ctrl_0 */ -#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET (0x500) -#define SEC_ENG_SE_GMAC_0_BUSY SEC_ENG_SE_GMAC_0_BUSY -#define SEC_ENG_SE_GMAC_0_BUSY_POS (0U) -#define SEC_ENG_SE_GMAC_0_BUSY_LEN (1U) -#define SEC_ENG_SE_GMAC_0_BUSY_MSK (((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS) -#define SEC_ENG_SE_GMAC_0_BUSY_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_BUSY_LEN) - 1) << SEC_ENG_SE_GMAC_0_BUSY_POS)) -#define SEC_ENG_SE_GMAC_0_TRIG_1T SEC_ENG_SE_GMAC_0_TRIG_1T -#define SEC_ENG_SE_GMAC_0_TRIG_1T_POS (1U) -#define SEC_ENG_SE_GMAC_0_TRIG_1T_LEN (1U) -#define SEC_ENG_SE_GMAC_0_TRIG_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS) -#define SEC_ENG_SE_GMAC_0_TRIG_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_TRIG_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_TRIG_1T_POS)) -#define SEC_ENG_SE_GMAC_0_EN SEC_ENG_SE_GMAC_0_EN -#define SEC_ENG_SE_GMAC_0_EN_POS (2U) -#define SEC_ENG_SE_GMAC_0_EN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_EN_MSK (((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS) -#define SEC_ENG_SE_GMAC_0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_0_EN_POS)) -#define SEC_ENG_SE_GMAC_0_INT SEC_ENG_SE_GMAC_0_INT -#define SEC_ENG_SE_GMAC_0_INT_POS (8U) -#define SEC_ENG_SE_GMAC_0_INT_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS) -#define SEC_ENG_SE_GMAC_0_INT_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_POS)) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T SEC_ENG_SE_GMAC_0_INT_CLR_1T -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS (9U) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS) -#define SEC_ENG_SE_GMAC_0_INT_CLR_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_CLR_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_CLR_1T_POS)) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T SEC_ENG_SE_GMAC_0_INT_SET_1T -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_POS (10U) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS) -#define SEC_ENG_SE_GMAC_0_INT_SET_1T_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_SET_1T_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_SET_1T_POS)) -#define SEC_ENG_SE_GMAC_0_INT_MASK SEC_ENG_SE_GMAC_0_INT_MASK -#define SEC_ENG_SE_GMAC_0_INT_MASK_POS (11U) -#define SEC_ENG_SE_GMAC_0_INT_MASK_LEN (1U) -#define SEC_ENG_SE_GMAC_0_INT_MASK_MSK (((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS) -#define SEC_ENG_SE_GMAC_0_INT_MASK_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_INT_MASK_LEN) - 1) << SEC_ENG_SE_GMAC_0_INT_MASK_POS)) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN SEC_ENG_SE_GMAC_0_T_ENDIAN -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_POS (12U) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS) -#define SEC_ENG_SE_GMAC_0_T_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_T_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_T_ENDIAN_POS)) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN SEC_ENG_SE_GMAC_0_H_ENDIAN -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_POS (13U) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS) -#define SEC_ENG_SE_GMAC_0_H_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_H_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_H_ENDIAN_POS)) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN SEC_ENG_SE_GMAC_0_X_ENDIAN -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_POS (14U) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN (1U) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_MSK (((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS) -#define SEC_ENG_SE_GMAC_0_X_ENDIAN_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_X_ENDIAN_LEN) - 1) << SEC_ENG_SE_GMAC_0_X_ENDIAN_POS)) - -/* 0x504 : se_gmac_0_lca */ -#define SEC_ENG_SE_GMAC_0_LCA_OFFSET (0x504) -#define SEC_ENG_SE_GMAC_0_LCA SEC_ENG_SE_GMAC_0_LCA -#define SEC_ENG_SE_GMAC_0_LCA_POS (0U) -#define SEC_ENG_SE_GMAC_0_LCA_LEN (32U) -#define SEC_ENG_SE_GMAC_0_LCA_MSK (((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS) -#define SEC_ENG_SE_GMAC_0_LCA_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_LCA_LEN) - 1) << SEC_ENG_SE_GMAC_0_LCA_POS)) - -/* 0x508 : se_gmac_0_status */ -#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET (0x508) -#define SEC_ENG_SE_GMAC_0_STATUS SEC_ENG_SE_GMAC_0_STATUS -#define SEC_ENG_SE_GMAC_0_STATUS_POS (0U) -#define SEC_ENG_SE_GMAC_0_STATUS_LEN (32U) -#define SEC_ENG_SE_GMAC_0_STATUS_MSK (((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS) -#define SEC_ENG_SE_GMAC_0_STATUS_UMSK (~(((1U << SEC_ENG_SE_GMAC_0_STATUS_LEN) - 1) << SEC_ENG_SE_GMAC_0_STATUS_POS)) - -/* 0x5FC : se_gmac_0_ctrl_prot */ -#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET (0x5FC) -#define SEC_ENG_SE_GMAC_ID0_EN SEC_ENG_SE_GMAC_ID0_EN -#define SEC_ENG_SE_GMAC_ID0_EN_POS (1U) -#define SEC_ENG_SE_GMAC_ID0_EN_LEN (1U) -#define SEC_ENG_SE_GMAC_ID0_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS) -#define SEC_ENG_SE_GMAC_ID0_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_POS)) -#define SEC_ENG_SE_GMAC_ID1_EN SEC_ENG_SE_GMAC_ID1_EN -#define SEC_ENG_SE_GMAC_ID1_EN_POS (2U) -#define SEC_ENG_SE_GMAC_ID1_EN_LEN (1U) -#define SEC_ENG_SE_GMAC_ID1_EN_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS) -#define SEC_ENG_SE_GMAC_ID1_EN_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_POS)) - -/* 0xF00 : se_ctrl_prot_rd */ -#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET (0xF00) -#define SEC_ENG_SE_SHA_ID0_EN_RD SEC_ENG_SE_SHA_ID0_EN_RD -#define SEC_ENG_SE_SHA_ID0_EN_RD_POS (0U) -#define SEC_ENG_SE_SHA_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_SHA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS) -#define SEC_ENG_SE_SHA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID0_EN_RD_POS)) -#define SEC_ENG_SE_SHA_ID1_EN_RD SEC_ENG_SE_SHA_ID1_EN_RD -#define SEC_ENG_SE_SHA_ID1_EN_RD_POS (1U) -#define SEC_ENG_SE_SHA_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_SHA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS) -#define SEC_ENG_SE_SHA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_SHA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_SHA_ID1_EN_RD_POS)) -#define SEC_ENG_SE_AES_ID0_EN_RD SEC_ENG_SE_AES_ID0_EN_RD -#define SEC_ENG_SE_AES_ID0_EN_RD_POS (2U) -#define SEC_ENG_SE_AES_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_AES_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS) -#define SEC_ENG_SE_AES_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID0_EN_RD_POS)) -#define SEC_ENG_SE_AES_ID1_EN_RD SEC_ENG_SE_AES_ID1_EN_RD -#define SEC_ENG_SE_AES_ID1_EN_RD_POS (3U) -#define SEC_ENG_SE_AES_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_AES_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS) -#define SEC_ENG_SE_AES_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_AES_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_AES_ID1_EN_RD_POS)) -#define SEC_ENG_SE_TRNG_ID0_EN_RD SEC_ENG_SE_TRNG_ID0_EN_RD -#define SEC_ENG_SE_TRNG_ID0_EN_RD_POS (4U) -#define SEC_ENG_SE_TRNG_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_TRNG_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS) -#define SEC_ENG_SE_TRNG_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID0_EN_RD_POS)) -#define SEC_ENG_SE_TRNG_ID1_EN_RD SEC_ENG_SE_TRNG_ID1_EN_RD -#define SEC_ENG_SE_TRNG_ID1_EN_RD_POS (5U) -#define SEC_ENG_SE_TRNG_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_TRNG_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS) -#define SEC_ENG_SE_TRNG_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_TRNG_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_TRNG_ID1_EN_RD_POS)) -#define SEC_ENG_SE_PKA_ID0_EN_RD SEC_ENG_SE_PKA_ID0_EN_RD -#define SEC_ENG_SE_PKA_ID0_EN_RD_POS (6U) -#define SEC_ENG_SE_PKA_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_PKA_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS) -#define SEC_ENG_SE_PKA_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID0_EN_RD_POS)) -#define SEC_ENG_SE_PKA_ID1_EN_RD SEC_ENG_SE_PKA_ID1_EN_RD -#define SEC_ENG_SE_PKA_ID1_EN_RD_POS (7U) -#define SEC_ENG_SE_PKA_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_PKA_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS) -#define SEC_ENG_SE_PKA_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_PKA_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_PKA_ID1_EN_RD_POS)) -#define SEC_ENG_SE_CDET_ID0_EN_RD SEC_ENG_SE_CDET_ID0_EN_RD -#define SEC_ENG_SE_CDET_ID0_EN_RD_POS (8U) -#define SEC_ENG_SE_CDET_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_CDET_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS) -#define SEC_ENG_SE_CDET_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID0_EN_RD_POS)) -#define SEC_ENG_SE_CDET_ID1_EN_RD SEC_ENG_SE_CDET_ID1_EN_RD -#define SEC_ENG_SE_CDET_ID1_EN_RD_POS (9U) -#define SEC_ENG_SE_CDET_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_CDET_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS) -#define SEC_ENG_SE_CDET_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_CDET_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_CDET_ID1_EN_RD_POS)) -#define SEC_ENG_SE_GMAC_ID0_EN_RD SEC_ENG_SE_GMAC_ID0_EN_RD -#define SEC_ENG_SE_GMAC_ID0_EN_RD_POS (10U) -#define SEC_ENG_SE_GMAC_ID0_EN_RD_LEN (1U) -#define SEC_ENG_SE_GMAC_ID0_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS) -#define SEC_ENG_SE_GMAC_ID0_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID0_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID0_EN_RD_POS)) -#define SEC_ENG_SE_GMAC_ID1_EN_RD SEC_ENG_SE_GMAC_ID1_EN_RD -#define SEC_ENG_SE_GMAC_ID1_EN_RD_POS (11U) -#define SEC_ENG_SE_GMAC_ID1_EN_RD_LEN (1U) -#define SEC_ENG_SE_GMAC_ID1_EN_RD_MSK (((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS) -#define SEC_ENG_SE_GMAC_ID1_EN_RD_UMSK (~(((1U << SEC_ENG_SE_GMAC_ID1_EN_RD_LEN) - 1) << SEC_ENG_SE_GMAC_ID1_EN_RD_POS)) -#define SEC_ENG_SE_DBG_DIS SEC_ENG_SE_DBG_DIS -#define SEC_ENG_SE_DBG_DIS_POS (31U) -#define SEC_ENG_SE_DBG_DIS_LEN (1U) -#define SEC_ENG_SE_DBG_DIS_MSK (((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS) -#define SEC_ENG_SE_DBG_DIS_UMSK (~(((1U << SEC_ENG_SE_DBG_DIS_LEN) - 1) << SEC_ENG_SE_DBG_DIS_POS)) - -/* 0xF04 : se_ctrl_reserved_0 */ -#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET (0xF04) -#define SEC_ENG_SE_CTRL_RESERVED_0 SEC_ENG_SE_CTRL_RESERVED_0 -#define SEC_ENG_SE_CTRL_RESERVED_0_POS (0U) -#define SEC_ENG_SE_CTRL_RESERVED_0_LEN (32U) -#define SEC_ENG_SE_CTRL_RESERVED_0_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS) -#define SEC_ENG_SE_CTRL_RESERVED_0_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_0_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_0_POS)) - -/* 0xF08 : se_ctrl_reserved_1 */ -#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET (0xF08) -#define SEC_ENG_SE_CTRL_RESERVED_1 SEC_ENG_SE_CTRL_RESERVED_1 -#define SEC_ENG_SE_CTRL_RESERVED_1_POS (0U) -#define SEC_ENG_SE_CTRL_RESERVED_1_LEN (32U) -#define SEC_ENG_SE_CTRL_RESERVED_1_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS) -#define SEC_ENG_SE_CTRL_RESERVED_1_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_1_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_1_POS)) - -/* 0xF0C : se_ctrl_reserved_2 */ -#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET (0xF0C) -#define SEC_ENG_SE_CTRL_RESERVED_2 SEC_ENG_SE_CTRL_RESERVED_2 -#define SEC_ENG_SE_CTRL_RESERVED_2_POS (0U) -#define SEC_ENG_SE_CTRL_RESERVED_2_LEN (32U) -#define SEC_ENG_SE_CTRL_RESERVED_2_MSK (((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS) -#define SEC_ENG_SE_CTRL_RESERVED_2_UMSK (~(((1U << SEC_ENG_SE_CTRL_RESERVED_2_LEN) - 1) << SEC_ENG_SE_CTRL_RESERVED_2_POS)) - -struct sec_eng_reg { - /* 0x0 : se_sha_0_ctrl */ - union { - struct { - uint32_t se_sha_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_sha_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_sha_0_mode : 3; /* [ 4: 2], r/w, 0x0 */ - uint32_t se_sha_0_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t se_sha_0_hash_sel : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t se_sha_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_sha_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_sha_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_sha_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_sha_0_mode_ext : 2; /* [13:12], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t se_sha_0_link_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t se_sha_0_msg_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_ctrl; - - /* 0x4 : se_sha_0_msa */ - union { - struct { - uint32_t se_sha_0_msa : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_msa; - - /* 0x8 : se_sha_0_status */ - union { - struct { - uint32_t se_sha_0_status : 32; /* [31: 0], r, 0x41 */ - } BF; - uint32_t WORD; - } se_sha_0_status; - - /* 0xC : se_sha_0_endian */ - union { - struct { - uint32_t se_sha_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_endian; - - /* 0x10 : se_sha_0_hash_l_0 */ - union { - struct { - uint32_t se_sha_0_hash_l_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_0; - - /* 0x14 : se_sha_0_hash_l_1 */ - union { - struct { - uint32_t se_sha_0_hash_l_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_1; - - /* 0x18 : se_sha_0_hash_l_2 */ - union { - struct { - uint32_t se_sha_0_hash_l_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_2; - - /* 0x1C : se_sha_0_hash_l_3 */ - union { - struct { - uint32_t se_sha_0_hash_l_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_3; - - /* 0x20 : se_sha_0_hash_l_4 */ - union { - struct { - uint32_t se_sha_0_hash_l_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_4; - - /* 0x24 : se_sha_0_hash_l_5 */ - union { - struct { - uint32_t se_sha_0_hash_l_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_5; - - /* 0x28 : se_sha_0_hash_l_6 */ - union { - struct { - uint32_t se_sha_0_hash_l_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_6; - - /* 0x2C : se_sha_0_hash_l_7 */ - union { - struct { - uint32_t se_sha_0_hash_l_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_l_7; - - /* 0x30 : se_sha_0_hash_h_0 */ - union { - struct { - uint32_t se_sha_0_hash_h_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_0; - - /* 0x34 : se_sha_0_hash_h_1 */ - union { - struct { - uint32_t se_sha_0_hash_h_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_1; - - /* 0x38 : se_sha_0_hash_h_2 */ - union { - struct { - uint32_t se_sha_0_hash_h_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_2; - - /* 0x3C : se_sha_0_hash_h_3 */ - union { - struct { - uint32_t se_sha_0_hash_h_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_3; - - /* 0x40 : se_sha_0_hash_h_4 */ - union { - struct { - uint32_t se_sha_0_hash_h_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_4; - - /* 0x44 : se_sha_0_hash_h_5 */ - union { - struct { - uint32_t se_sha_0_hash_h_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_5; - - /* 0x48 : se_sha_0_hash_h_6 */ - union { - struct { - uint32_t se_sha_0_hash_h_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_6; - - /* 0x4C : se_sha_0_hash_h_7 */ - union { - struct { - uint32_t se_sha_0_hash_h_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_hash_h_7; - - /* 0x50 : se_sha_0_link */ - union { - struct { - uint32_t se_sha_0_lca : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_link; - - /* 0x54 reserved */ - uint8_t RESERVED0x54[168]; - - /* 0xFC : se_sha_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_sha_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_sha_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_sha_0_ctrl_prot; - - /* 0x100 : se_aes_0_ctrl */ - union { - struct { - uint32_t se_aes_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_aes_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_aes_0_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t se_aes_0_mode : 2; /* [ 4: 3], r/w, 0x0 */ - uint32_t se_aes_0_dec_en : 1; /* [ 5], r/w, 0x0 */ - uint32_t se_aes_0_dec_key_sel : 1; /* [ 6], r/w, 0x0 */ - uint32_t se_aes_0_hw_key_en : 1; /* [ 7], r/w, 0x0 */ - uint32_t se_aes_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_aes_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_aes_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_aes_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_aes_0_block_mode : 2; /* [13:12], r/w, 0x0 */ - uint32_t se_aes_0_iv_sel : 1; /* [ 14], r/w, 0x0 */ - uint32_t se_aes_0_link_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t se_aes_0_msg_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_ctrl; - - /* 0x104 : se_aes_0_msa */ - union { - struct { - uint32_t se_aes_0_msa : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_msa; - - /* 0x108 : se_aes_0_mda */ - union { - struct { - uint32_t se_aes_0_mda : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_mda; - - /* 0x10C : se_aes_0_status */ - union { - struct { - uint32_t se_aes_0_status : 32; /* [31: 0], r, 0x4100 */ - } BF; - uint32_t WORD; - } se_aes_0_status; - - /* 0x110 : se_aes_0_iv_0 */ - union { - struct { - uint32_t se_aes_0_iv_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_0; - - /* 0x114 : se_aes_0_iv_1 */ - union { - struct { - uint32_t se_aes_0_iv_1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_1; - - /* 0x118 : se_aes_0_iv_2 */ - union { - struct { - uint32_t se_aes_0_iv_2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_2; - - /* 0x11C : se_aes_0_iv_3 */ - union { - struct { - uint32_t se_aes_0_iv_3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_iv_3; - - /* 0x120 : se_aes_0_key_0 */ - union { - struct { - uint32_t se_aes_0_key_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_0; - - /* 0x124 : se_aes_0_key_1 */ - union { - struct { - uint32_t se_aes_0_key_1 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_1; - - /* 0x128 : se_aes_0_key_2 */ - union { - struct { - uint32_t se_aes_0_key_2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_2; - - /* 0x12C : se_aes_0_key_3 */ - union { - struct { - uint32_t se_aes_0_key_3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_3; - - /* 0x130 : se_aes_0_key_4 */ - union { - struct { - uint32_t se_aes_0_key_4 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_4; - - /* 0x134 : se_aes_0_key_5 */ - union { - struct { - uint32_t se_aes_0_key_5 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_5; - - /* 0x138 : se_aes_0_key_6 */ - union { - struct { - uint32_t se_aes_0_key_6 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_6; - - /* 0x13C : se_aes_0_key_7 */ - union { - struct { - uint32_t se_aes_0_key_7 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_7; - - /* 0x140 : se_aes_0_key_sel */ - union { - struct { - uint32_t se_aes_0_key_sel : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_key_sel; - - /* 0x144 : se_aes_1_key_sel */ - union { - struct { - uint32_t se_aes_1_key_sel : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_1_key_sel; - - /* 0x148 : se_aes_0_endian */ - union { - struct { - uint32_t se_aes_0_dout_endian : 1; /* [ 0], r/w, 0x1 */ - uint32_t se_aes_0_din_endian : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_aes_0_key_endian : 1; /* [ 2], r/w, 0x1 */ - uint32_t se_aes_0_iv_endian : 1; /* [ 3], r/w, 0x1 */ - uint32_t se_aes_0_twk_endian : 1; /* [ 4], r/w, 0x1 */ - uint32_t reserved_5_29 : 25; /* [29: 5], rsvd, 0x0 */ - uint32_t se_aes_0_ctr_len : 2; /* [31:30], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_endian; - - /* 0x14C : se_aes_sboot */ - union { - struct { - uint32_t se_aes_sboot_key_sel : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_14 : 14; /* [14: 1], rsvd, 0x0 */ - uint32_t se_aes_0_xts_mode : 1; /* [ 15], r/w, 0x0 */ - uint32_t se_aes_0_uni_len : 16; /* [31:16], r/w, 0x2 */ - } BF; - uint32_t WORD; - } se_aes_sboot; - - /* 0x150 : se_aes_0_link */ - union { - struct { - uint32_t se_aes_0_lca : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_link; - - /* 0x154 reserved */ - uint8_t RESERVED0x154[168]; - - /* 0x1FC : se_aes_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_aes_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_aes_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_aes_0_ctrl_prot; - - /* 0x200 : se_trng_0_ctrl_0 */ - union { - struct { - uint32_t se_trng_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_trng_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_trng_0_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t se_trng_0_dout_clr_1t : 1; /* [ 3], w1p, 0x0 */ - uint32_t se_trng_0_ht_error : 1; /* [ 4], r, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t se_trng_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_trng_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_trng_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_trng_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t se_trng_0_manual_fun_sel : 1; /* [ 13], r/w, 0x0 */ - uint32_t se_trng_0_manual_reseed : 1; /* [ 14], r/w, 0x0 */ - uint32_t se_trng_0_manual_en : 1; /* [ 15], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_0; - - /* 0x204 : se_trng_0_status */ - union { - struct { - uint32_t se_trng_0_status : 32; /* [31: 0], r, 0x100020 */ - } BF; - uint32_t WORD; - } se_trng_0_status; - - /* 0x208 : se_trng_0_dout_0 */ - union { - struct { - uint32_t se_trng_0_dout_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_0; - - /* 0x20C : se_trng_0_dout_1 */ - union { - struct { - uint32_t se_trng_0_dout_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_1; - - /* 0x210 : se_trng_0_dout_2 */ - union { - struct { - uint32_t se_trng_0_dout_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_2; - - /* 0x214 : se_trng_0_dout_3 */ - union { - struct { - uint32_t se_trng_0_dout_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_3; - - /* 0x218 : se_trng_0_dout_4 */ - union { - struct { - uint32_t se_trng_0_dout_4 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_4; - - /* 0x21C : se_trng_0_dout_5 */ - union { - struct { - uint32_t se_trng_0_dout_5 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_5; - - /* 0x220 : se_trng_0_dout_6 */ - union { - struct { - uint32_t se_trng_0_dout_6 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_6; - - /* 0x224 : se_trng_0_dout_7 */ - union { - struct { - uint32_t se_trng_0_dout_7 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_dout_7; - - /* 0x228 : se_trng_0_test */ - union { - struct { - uint32_t se_trng_0_test_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t se_trng_0_cp_test_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t se_trng_0_cp_bypass : 1; /* [ 2], r/w, 0x0 */ - uint32_t se_trng_0_ht_dis : 1; /* [ 3], r/w, 0x0 */ - uint32_t se_trng_0_ht_alarm_n : 8; /* [11: 4], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test; - - /* 0x22C : se_trng_0_ctrl_1 */ - union { - struct { - uint32_t se_trng_0_reseed_n_lsb : 32; /* [31: 0], r/w, 0xffff */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_1; - - /* 0x230 : se_trng_0_ctrl_2 */ - union { - struct { - uint32_t se_trng_0_reseed_n_msb : 16; /* [15: 0], r/w, 0xff */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_2; - - /* 0x234 : se_trng_0_ctrl_3 */ - union { - struct { - uint32_t se_trng_0_cp_ratio : 8; /* [ 7: 0], r/w, 0x3 */ - uint32_t se_trng_0_ht_rct_c : 8; /* [15: 8], r/w, 0x42 */ - uint32_t se_trng_0_ht_apt_c : 10; /* [25:16], r/w, 0x37a */ - uint32_t se_trng_0_ht_od_en : 1; /* [ 26], r/w, 0x0 */ - uint32_t reserved_27_30 : 4; /* [30:27], rsvd, 0x0 */ - uint32_t se_trng_0_rosc_en : 1; /* [ 31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_3; - - /* 0x238 reserved */ - uint8_t RESERVED0x238[8]; - - /* 0x240 : se_trng_0_test_out_0 */ - union { - struct { - uint32_t se_trng_0_test_out_0 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_0; - - /* 0x244 : se_trng_0_test_out_1 */ - union { - struct { - uint32_t se_trng_0_test_out_1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_1; - - /* 0x248 : se_trng_0_test_out_2 */ - union { - struct { - uint32_t se_trng_0_test_out_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_2; - - /* 0x24C : se_trng_0_test_out_3 */ - union { - struct { - uint32_t se_trng_0_test_out_3 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_test_out_3; - - /* 0x250 reserved */ - uint8_t RESERVED0x250[172]; - - /* 0x2FC : se_trng_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_trng_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_trng_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_trng_0_ctrl_prot; - - /* 0x300 : se_pka_0_ctrl_0 */ - union { - struct { - uint32_t se_pka_0_done : 1; /* [ 0], r, 0x0 */ - uint32_t se_pka_0_done_clr_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_pka_0_busy : 1; /* [ 2], r, 0x0 */ - uint32_t se_pka_0_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t se_pka_0_prot_md : 4; /* [ 7: 4], r/w, 0x0 */ - uint32_t se_pka_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_pka_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_pka_0_int_set : 1; /* [ 10], r/w, 0x0 */ - uint32_t se_pka_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_pka_0_endian : 1; /* [ 12], r/w, 0x0 */ - uint32_t se_pka_0_ram_clr_md : 1; /* [ 13], r/w, 0x0 */ - uint32_t reserved_14 : 1; /* [ 14], rsvd, 0x0 */ - uint32_t se_pka_0_status_clr_1t : 1; /* [ 15], w1p, 0x0 */ - uint32_t se_pka_0_status : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_ctrl_0; - - /* 0x304 reserved */ - uint8_t RESERVED0x304[8]; - - /* 0x30C : se_pka_0_seed */ - union { - struct { - uint32_t se_pka_0_seed : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_seed; - - /* 0x310 : se_pka_0_ctrl_1 */ - union { - struct { - uint32_t se_pka_0_hburst : 3; /* [ 2: 0], r/w, 0x5 */ - uint32_t se_pka_0_hbypass : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_ctrl_1; - - /* 0x314 reserved */ - uint8_t RESERVED0x314[44]; - - /* 0x340 : se_pka_0_rw */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_rw; - - /* 0x344 reserved */ - uint8_t RESERVED0x344[28]; - - /* 0x360 : se_pka_0_rw_burst */ - union { - struct { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_rw_burst; - - /* 0x364 reserved */ - uint8_t RESERVED0x364[152]; - - /* 0x3FC : se_pka_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_pka_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_pka_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_pka_0_ctrl_prot; - - /* 0x400 : se_cdet_0_ctrl_0 */ - union { - struct { - uint32_t se_cdet_0_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t se_cdet_0_error : 1; /* [ 1], r, 0x0 */ - uint32_t se_cdet_0_status : 14; /* [15: 2], r, 0x1 */ - uint32_t se_cdet_0_g_loop_max : 8; /* [23:16], r/w, 0x64 */ - uint32_t se_cdet_0_g_loop_min : 8; /* [31:24], r/w, 0x21 */ - } BF; - uint32_t WORD; - } se_cdet_0_ctrl_0; - - /* 0x404 : se_cdet_0_ctrl_1 */ - union { - struct { - uint32_t se_cdet_0_t_loop_n : 8; /* [ 7: 0], r/w, 0x32 */ - uint32_t se_cdet_0_t_dly_n : 8; /* [15: 8], r/w, 0x3 */ - uint32_t se_cdet_0_g_slp_n : 8; /* [23:16], r/w, 0xff */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_cdet_0_ctrl_1; - - /* 0x408 reserved */ - uint8_t RESERVED0x408[244]; - - /* 0x4FC : se_cdet_0_ctrl_prot */ - union { - struct { - uint32_t se_cdet_prot_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t se_cdet_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_cdet_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_cdet_0_ctrl_prot; - - /* 0x500 : se_gmac_0_ctrl_0 */ - union { - struct { - uint32_t se_gmac_0_busy : 1; /* [ 0], r, 0x0 */ - uint32_t se_gmac_0_trig_1t : 1; /* [ 1], w1p, 0x0 */ - uint32_t se_gmac_0_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t se_gmac_0_int : 1; /* [ 8], r, 0x0 */ - uint32_t se_gmac_0_int_clr_1t : 1; /* [ 9], w1p, 0x0 */ - uint32_t se_gmac_0_int_set_1t : 1; /* [ 10], w1p, 0x0 */ - uint32_t se_gmac_0_int_mask : 1; /* [ 11], r/w, 0x0 */ - uint32_t se_gmac_0_t_endian : 1; /* [ 12], r/w, 0x1 */ - uint32_t se_gmac_0_h_endian : 1; /* [ 13], r/w, 0x1 */ - uint32_t se_gmac_0_x_endian : 1; /* [ 14], r/w, 0x1 */ - uint32_t reserved_15_31 : 17; /* [31:15], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_gmac_0_ctrl_0; - - /* 0x504 : se_gmac_0_lca */ - union { - struct { - uint32_t se_gmac_0_lca : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_gmac_0_lca; - - /* 0x508 : se_gmac_0_status */ - union { - struct { - uint32_t se_gmac_0_status : 32; /* [31: 0], r, 0xf1000000 */ - } BF; - uint32_t WORD; - } se_gmac_0_status; - - /* 0x50c reserved */ - uint8_t RESERVED0x50c[240]; - - /* 0x5FC : se_gmac_0_ctrl_prot */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t se_gmac_id0_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t se_gmac_id1_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } se_gmac_0_ctrl_prot; - - /* 0x600 reserved */ - uint8_t RESERVED0x600[2304]; - - /* 0xF00 : se_ctrl_prot_rd */ - union { - struct { - uint32_t se_sha_id0_en_rd : 1; /* [ 0], r, 0x1 */ - uint32_t se_sha_id1_en_rd : 1; /* [ 1], r, 0x1 */ - uint32_t se_aes_id0_en_rd : 1; /* [ 2], r, 0x1 */ - uint32_t se_aes_id1_en_rd : 1; /* [ 3], r, 0x1 */ - uint32_t se_trng_id0_en_rd : 1; /* [ 4], r, 0x1 */ - uint32_t se_trng_id1_en_rd : 1; /* [ 5], r, 0x1 */ - uint32_t se_pka_id0_en_rd : 1; /* [ 6], r, 0x1 */ - uint32_t se_pka_id1_en_rd : 1; /* [ 7], r, 0x1 */ - uint32_t se_cdet_id0_en_rd : 1; /* [ 8], r, 0x1 */ - uint32_t se_cdet_id1_en_rd : 1; /* [ 9], r, 0x1 */ - uint32_t se_gmac_id0_en_rd : 1; /* [ 10], r, 0x1 */ - uint32_t se_gmac_id1_en_rd : 1; /* [ 11], r, 0x1 */ - uint32_t reserved_12_30 : 19; /* [30:12], rsvd, 0x0 */ - uint32_t se_dbg_dis : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } se_ctrl_prot_rd; - - /* 0xF04 : se_ctrl_reserved_0 */ - union { - struct { - uint32_t se_ctrl_reserved_0 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } se_ctrl_reserved_0; - - /* 0xF08 : se_ctrl_reserved_1 */ - union { - struct { - uint32_t se_ctrl_reserved_1 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } se_ctrl_reserved_1; - - /* 0xF0C : se_ctrl_reserved_2 */ - union { - struct { - uint32_t se_ctrl_reserved_2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } se_ctrl_reserved_2; -}; - -typedef volatile struct sec_eng_reg sec_eng_reg_t; - -#endif /* __SEC_ENG_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/spi_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/spi_reg.h deleted file mode 100644 index f1e92fd357..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/spi_reg.h +++ /dev/null @@ -1,535 +0,0 @@ -/** - ****************************************************************************** - * @file spi_reg.h - * @version V1.0 - * @date 2021-09-10 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __SPI_REG_H__ -#define __SPI_REG_H__ - -#include "bl808.h" - -/* 0x0 : spi_config */ -#define SPI_CONFIG_OFFSET (0x0) -#define SPI_CR_SPI_M_EN SPI_CR_SPI_M_EN -#define SPI_CR_SPI_M_EN_POS (0U) -#define SPI_CR_SPI_M_EN_LEN (1U) -#define SPI_CR_SPI_M_EN_MSK (((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS) -#define SPI_CR_SPI_M_EN_UMSK (~(((1U << SPI_CR_SPI_M_EN_LEN) - 1) << SPI_CR_SPI_M_EN_POS)) -#define SPI_CR_SPI_S_EN SPI_CR_SPI_S_EN -#define SPI_CR_SPI_S_EN_POS (1U) -#define SPI_CR_SPI_S_EN_LEN (1U) -#define SPI_CR_SPI_S_EN_MSK (((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS) -#define SPI_CR_SPI_S_EN_UMSK (~(((1U << SPI_CR_SPI_S_EN_LEN) - 1) << SPI_CR_SPI_S_EN_POS)) -#define SPI_CR_SPI_FRAME_SIZE SPI_CR_SPI_FRAME_SIZE -#define SPI_CR_SPI_FRAME_SIZE_POS (2U) -#define SPI_CR_SPI_FRAME_SIZE_LEN (2U) -#define SPI_CR_SPI_FRAME_SIZE_MSK (((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS) -#define SPI_CR_SPI_FRAME_SIZE_UMSK (~(((1U << SPI_CR_SPI_FRAME_SIZE_LEN) - 1) << SPI_CR_SPI_FRAME_SIZE_POS)) -#define SPI_CR_SPI_SCLK_POL SPI_CR_SPI_SCLK_POL -#define SPI_CR_SPI_SCLK_POL_POS (4U) -#define SPI_CR_SPI_SCLK_POL_LEN (1U) -#define SPI_CR_SPI_SCLK_POL_MSK (((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS) -#define SPI_CR_SPI_SCLK_POL_UMSK (~(((1U << SPI_CR_SPI_SCLK_POL_LEN) - 1) << SPI_CR_SPI_SCLK_POL_POS)) -#define SPI_CR_SPI_SCLK_PH SPI_CR_SPI_SCLK_PH -#define SPI_CR_SPI_SCLK_PH_POS (5U) -#define SPI_CR_SPI_SCLK_PH_LEN (1U) -#define SPI_CR_SPI_SCLK_PH_MSK (((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS) -#define SPI_CR_SPI_SCLK_PH_UMSK (~(((1U << SPI_CR_SPI_SCLK_PH_LEN) - 1) << SPI_CR_SPI_SCLK_PH_POS)) -#define SPI_CR_SPI_BIT_INV SPI_CR_SPI_BIT_INV -#define SPI_CR_SPI_BIT_INV_POS (6U) -#define SPI_CR_SPI_BIT_INV_LEN (1U) -#define SPI_CR_SPI_BIT_INV_MSK (((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS) -#define SPI_CR_SPI_BIT_INV_UMSK (~(((1U << SPI_CR_SPI_BIT_INV_LEN) - 1) << SPI_CR_SPI_BIT_INV_POS)) -#define SPI_CR_SPI_BYTE_INV SPI_CR_SPI_BYTE_INV -#define SPI_CR_SPI_BYTE_INV_POS (7U) -#define SPI_CR_SPI_BYTE_INV_LEN (1U) -#define SPI_CR_SPI_BYTE_INV_MSK (((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS) -#define SPI_CR_SPI_BYTE_INV_UMSK (~(((1U << SPI_CR_SPI_BYTE_INV_LEN) - 1) << SPI_CR_SPI_BYTE_INV_POS)) -#define SPI_CR_SPI_RXD_IGNR_EN SPI_CR_SPI_RXD_IGNR_EN -#define SPI_CR_SPI_RXD_IGNR_EN_POS (8U) -#define SPI_CR_SPI_RXD_IGNR_EN_LEN (1U) -#define SPI_CR_SPI_RXD_IGNR_EN_MSK (((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS) -#define SPI_CR_SPI_RXD_IGNR_EN_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_EN_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_EN_POS)) -#define SPI_CR_SPI_M_CONT_EN SPI_CR_SPI_M_CONT_EN -#define SPI_CR_SPI_M_CONT_EN_POS (9U) -#define SPI_CR_SPI_M_CONT_EN_LEN (1U) -#define SPI_CR_SPI_M_CONT_EN_MSK (((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS) -#define SPI_CR_SPI_M_CONT_EN_UMSK (~(((1U << SPI_CR_SPI_M_CONT_EN_LEN) - 1) << SPI_CR_SPI_M_CONT_EN_POS)) -#define SPI_CR_SPI_S_3PIN_MODE SPI_CR_SPI_S_3PIN_MODE -#define SPI_CR_SPI_S_3PIN_MODE_POS (10U) -#define SPI_CR_SPI_S_3PIN_MODE_LEN (1U) -#define SPI_CR_SPI_S_3PIN_MODE_MSK (((1U << SPI_CR_SPI_S_3PIN_MODE_LEN) - 1) << SPI_CR_SPI_S_3PIN_MODE_POS) -#define SPI_CR_SPI_S_3PIN_MODE_UMSK (~(((1U << SPI_CR_SPI_S_3PIN_MODE_LEN) - 1) << SPI_CR_SPI_S_3PIN_MODE_POS)) -#define SPI_CR_SPI_DEG_EN SPI_CR_SPI_DEG_EN -#define SPI_CR_SPI_DEG_EN_POS (11U) -#define SPI_CR_SPI_DEG_EN_LEN (1U) -#define SPI_CR_SPI_DEG_EN_MSK (((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS) -#define SPI_CR_SPI_DEG_EN_UMSK (~(((1U << SPI_CR_SPI_DEG_EN_LEN) - 1) << SPI_CR_SPI_DEG_EN_POS)) -#define SPI_CR_SPI_DEG_CNT SPI_CR_SPI_DEG_CNT -#define SPI_CR_SPI_DEG_CNT_POS (12U) -#define SPI_CR_SPI_DEG_CNT_LEN (4U) -#define SPI_CR_SPI_DEG_CNT_MSK (((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS) -#define SPI_CR_SPI_DEG_CNT_UMSK (~(((1U << SPI_CR_SPI_DEG_CNT_LEN) - 1) << SPI_CR_SPI_DEG_CNT_POS)) - -/* 0x4 : spi_int_sts */ -#define SPI_INT_STS_OFFSET (0x4) -#define SPI_END_INT SPI_END_INT -#define SPI_END_INT_POS (0U) -#define SPI_END_INT_LEN (1U) -#define SPI_END_INT_MSK (((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS) -#define SPI_END_INT_UMSK (~(((1U << SPI_END_INT_LEN) - 1) << SPI_END_INT_POS)) -#define SPI_TXF_INT SPI_TXF_INT -#define SPI_TXF_INT_POS (1U) -#define SPI_TXF_INT_LEN (1U) -#define SPI_TXF_INT_MSK (((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS) -#define SPI_TXF_INT_UMSK (~(((1U << SPI_TXF_INT_LEN) - 1) << SPI_TXF_INT_POS)) -#define SPI_RXF_INT SPI_RXF_INT -#define SPI_RXF_INT_POS (2U) -#define SPI_RXF_INT_LEN (1U) -#define SPI_RXF_INT_MSK (((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS) -#define SPI_RXF_INT_UMSK (~(((1U << SPI_RXF_INT_LEN) - 1) << SPI_RXF_INT_POS)) -#define SPI_STO_INT SPI_STO_INT -#define SPI_STO_INT_POS (3U) -#define SPI_STO_INT_LEN (1U) -#define SPI_STO_INT_MSK (((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS) -#define SPI_STO_INT_UMSK (~(((1U << SPI_STO_INT_LEN) - 1) << SPI_STO_INT_POS)) -#define SPI_TXU_INT SPI_TXU_INT -#define SPI_TXU_INT_POS (4U) -#define SPI_TXU_INT_LEN (1U) -#define SPI_TXU_INT_MSK (((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS) -#define SPI_TXU_INT_UMSK (~(((1U << SPI_TXU_INT_LEN) - 1) << SPI_TXU_INT_POS)) -#define SPI_FER_INT SPI_FER_INT -#define SPI_FER_INT_POS (5U) -#define SPI_FER_INT_LEN (1U) -#define SPI_FER_INT_MSK (((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS) -#define SPI_FER_INT_UMSK (~(((1U << SPI_FER_INT_LEN) - 1) << SPI_FER_INT_POS)) -#define SPI_CR_SPI_END_MASK SPI_CR_SPI_END_MASK -#define SPI_CR_SPI_END_MASK_POS (8U) -#define SPI_CR_SPI_END_MASK_LEN (1U) -#define SPI_CR_SPI_END_MASK_MSK (((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS) -#define SPI_CR_SPI_END_MASK_UMSK (~(((1U << SPI_CR_SPI_END_MASK_LEN) - 1) << SPI_CR_SPI_END_MASK_POS)) -#define SPI_CR_SPI_TXF_MASK SPI_CR_SPI_TXF_MASK -#define SPI_CR_SPI_TXF_MASK_POS (9U) -#define SPI_CR_SPI_TXF_MASK_LEN (1U) -#define SPI_CR_SPI_TXF_MASK_MSK (((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS) -#define SPI_CR_SPI_TXF_MASK_UMSK (~(((1U << SPI_CR_SPI_TXF_MASK_LEN) - 1) << SPI_CR_SPI_TXF_MASK_POS)) -#define SPI_CR_SPI_RXF_MASK SPI_CR_SPI_RXF_MASK -#define SPI_CR_SPI_RXF_MASK_POS (10U) -#define SPI_CR_SPI_RXF_MASK_LEN (1U) -#define SPI_CR_SPI_RXF_MASK_MSK (((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS) -#define SPI_CR_SPI_RXF_MASK_UMSK (~(((1U << SPI_CR_SPI_RXF_MASK_LEN) - 1) << SPI_CR_SPI_RXF_MASK_POS)) -#define SPI_CR_SPI_STO_MASK SPI_CR_SPI_STO_MASK -#define SPI_CR_SPI_STO_MASK_POS (11U) -#define SPI_CR_SPI_STO_MASK_LEN (1U) -#define SPI_CR_SPI_STO_MASK_MSK (((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS) -#define SPI_CR_SPI_STO_MASK_UMSK (~(((1U << SPI_CR_SPI_STO_MASK_LEN) - 1) << SPI_CR_SPI_STO_MASK_POS)) -#define SPI_CR_SPI_TXU_MASK SPI_CR_SPI_TXU_MASK -#define SPI_CR_SPI_TXU_MASK_POS (12U) -#define SPI_CR_SPI_TXU_MASK_LEN (1U) -#define SPI_CR_SPI_TXU_MASK_MSK (((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS) -#define SPI_CR_SPI_TXU_MASK_UMSK (~(((1U << SPI_CR_SPI_TXU_MASK_LEN) - 1) << SPI_CR_SPI_TXU_MASK_POS)) -#define SPI_CR_SPI_FER_MASK SPI_CR_SPI_FER_MASK -#define SPI_CR_SPI_FER_MASK_POS (13U) -#define SPI_CR_SPI_FER_MASK_LEN (1U) -#define SPI_CR_SPI_FER_MASK_MSK (((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS) -#define SPI_CR_SPI_FER_MASK_UMSK (~(((1U << SPI_CR_SPI_FER_MASK_LEN) - 1) << SPI_CR_SPI_FER_MASK_POS)) -#define SPI_CR_SPI_END_CLR SPI_CR_SPI_END_CLR -#define SPI_CR_SPI_END_CLR_POS (16U) -#define SPI_CR_SPI_END_CLR_LEN (1U) -#define SPI_CR_SPI_END_CLR_MSK (((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS) -#define SPI_CR_SPI_END_CLR_UMSK (~(((1U << SPI_CR_SPI_END_CLR_LEN) - 1) << SPI_CR_SPI_END_CLR_POS)) -#define SPI_CR_SPI_STO_CLR SPI_CR_SPI_STO_CLR -#define SPI_CR_SPI_STO_CLR_POS (19U) -#define SPI_CR_SPI_STO_CLR_LEN (1U) -#define SPI_CR_SPI_STO_CLR_MSK (((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS) -#define SPI_CR_SPI_STO_CLR_UMSK (~(((1U << SPI_CR_SPI_STO_CLR_LEN) - 1) << SPI_CR_SPI_STO_CLR_POS)) -#define SPI_CR_SPI_TXU_CLR SPI_CR_SPI_TXU_CLR -#define SPI_CR_SPI_TXU_CLR_POS (20U) -#define SPI_CR_SPI_TXU_CLR_LEN (1U) -#define SPI_CR_SPI_TXU_CLR_MSK (((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS) -#define SPI_CR_SPI_TXU_CLR_UMSK (~(((1U << SPI_CR_SPI_TXU_CLR_LEN) - 1) << SPI_CR_SPI_TXU_CLR_POS)) -#define SPI_CR_SPI_END_EN SPI_CR_SPI_END_EN -#define SPI_CR_SPI_END_EN_POS (24U) -#define SPI_CR_SPI_END_EN_LEN (1U) -#define SPI_CR_SPI_END_EN_MSK (((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS) -#define SPI_CR_SPI_END_EN_UMSK (~(((1U << SPI_CR_SPI_END_EN_LEN) - 1) << SPI_CR_SPI_END_EN_POS)) -#define SPI_CR_SPI_TXF_EN SPI_CR_SPI_TXF_EN -#define SPI_CR_SPI_TXF_EN_POS (25U) -#define SPI_CR_SPI_TXF_EN_LEN (1U) -#define SPI_CR_SPI_TXF_EN_MSK (((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS) -#define SPI_CR_SPI_TXF_EN_UMSK (~(((1U << SPI_CR_SPI_TXF_EN_LEN) - 1) << SPI_CR_SPI_TXF_EN_POS)) -#define SPI_CR_SPI_RXF_EN SPI_CR_SPI_RXF_EN -#define SPI_CR_SPI_RXF_EN_POS (26U) -#define SPI_CR_SPI_RXF_EN_LEN (1U) -#define SPI_CR_SPI_RXF_EN_MSK (((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS) -#define SPI_CR_SPI_RXF_EN_UMSK (~(((1U << SPI_CR_SPI_RXF_EN_LEN) - 1) << SPI_CR_SPI_RXF_EN_POS)) -#define SPI_CR_SPI_STO_EN SPI_CR_SPI_STO_EN -#define SPI_CR_SPI_STO_EN_POS (27U) -#define SPI_CR_SPI_STO_EN_LEN (1U) -#define SPI_CR_SPI_STO_EN_MSK (((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS) -#define SPI_CR_SPI_STO_EN_UMSK (~(((1U << SPI_CR_SPI_STO_EN_LEN) - 1) << SPI_CR_SPI_STO_EN_POS)) -#define SPI_CR_SPI_TXU_EN SPI_CR_SPI_TXU_EN -#define SPI_CR_SPI_TXU_EN_POS (28U) -#define SPI_CR_SPI_TXU_EN_LEN (1U) -#define SPI_CR_SPI_TXU_EN_MSK (((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS) -#define SPI_CR_SPI_TXU_EN_UMSK (~(((1U << SPI_CR_SPI_TXU_EN_LEN) - 1) << SPI_CR_SPI_TXU_EN_POS)) -#define SPI_CR_SPI_FER_EN SPI_CR_SPI_FER_EN -#define SPI_CR_SPI_FER_EN_POS (29U) -#define SPI_CR_SPI_FER_EN_LEN (1U) -#define SPI_CR_SPI_FER_EN_MSK (((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS) -#define SPI_CR_SPI_FER_EN_UMSK (~(((1U << SPI_CR_SPI_FER_EN_LEN) - 1) << SPI_CR_SPI_FER_EN_POS)) - -/* 0x8 : spi_bus_busy */ -#define SPI_BUS_BUSY_OFFSET (0x8) -#define SPI_STS_SPI_BUS_BUSY SPI_STS_SPI_BUS_BUSY -#define SPI_STS_SPI_BUS_BUSY_POS (0U) -#define SPI_STS_SPI_BUS_BUSY_LEN (1U) -#define SPI_STS_SPI_BUS_BUSY_MSK (((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS) -#define SPI_STS_SPI_BUS_BUSY_UMSK (~(((1U << SPI_STS_SPI_BUS_BUSY_LEN) - 1) << SPI_STS_SPI_BUS_BUSY_POS)) - -/* 0x10 : spi_prd_0 */ -#define SPI_PRD_0_OFFSET (0x10) -#define SPI_CR_SPI_PRD_S SPI_CR_SPI_PRD_S -#define SPI_CR_SPI_PRD_S_POS (0U) -#define SPI_CR_SPI_PRD_S_LEN (8U) -#define SPI_CR_SPI_PRD_S_MSK (((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS) -#define SPI_CR_SPI_PRD_S_UMSK (~(((1U << SPI_CR_SPI_PRD_S_LEN) - 1) << SPI_CR_SPI_PRD_S_POS)) -#define SPI_CR_SPI_PRD_P SPI_CR_SPI_PRD_P -#define SPI_CR_SPI_PRD_P_POS (8U) -#define SPI_CR_SPI_PRD_P_LEN (8U) -#define SPI_CR_SPI_PRD_P_MSK (((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS) -#define SPI_CR_SPI_PRD_P_UMSK (~(((1U << SPI_CR_SPI_PRD_P_LEN) - 1) << SPI_CR_SPI_PRD_P_POS)) -#define SPI_CR_SPI_PRD_D_PH_0 SPI_CR_SPI_PRD_D_PH_0 -#define SPI_CR_SPI_PRD_D_PH_0_POS (16U) -#define SPI_CR_SPI_PRD_D_PH_0_LEN (8U) -#define SPI_CR_SPI_PRD_D_PH_0_MSK (((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS) -#define SPI_CR_SPI_PRD_D_PH_0_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_0_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_0_POS)) -#define SPI_CR_SPI_PRD_D_PH_1 SPI_CR_SPI_PRD_D_PH_1 -#define SPI_CR_SPI_PRD_D_PH_1_POS (24U) -#define SPI_CR_SPI_PRD_D_PH_1_LEN (8U) -#define SPI_CR_SPI_PRD_D_PH_1_MSK (((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS) -#define SPI_CR_SPI_PRD_D_PH_1_UMSK (~(((1U << SPI_CR_SPI_PRD_D_PH_1_LEN) - 1) << SPI_CR_SPI_PRD_D_PH_1_POS)) - -/* 0x14 : spi_prd_1 */ -#define SPI_PRD_1_OFFSET (0x14) -#define SPI_CR_SPI_PRD_I SPI_CR_SPI_PRD_I -#define SPI_CR_SPI_PRD_I_POS (0U) -#define SPI_CR_SPI_PRD_I_LEN (8U) -#define SPI_CR_SPI_PRD_I_MSK (((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS) -#define SPI_CR_SPI_PRD_I_UMSK (~(((1U << SPI_CR_SPI_PRD_I_LEN) - 1) << SPI_CR_SPI_PRD_I_POS)) - -/* 0x18 : spi_rxd_ignr */ -#define SPI_RXD_IGNR_OFFSET (0x18) -#define SPI_CR_SPI_RXD_IGNR_P SPI_CR_SPI_RXD_IGNR_P -#define SPI_CR_SPI_RXD_IGNR_P_POS (0U) -#define SPI_CR_SPI_RXD_IGNR_P_LEN (5U) -#define SPI_CR_SPI_RXD_IGNR_P_MSK (((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS) -#define SPI_CR_SPI_RXD_IGNR_P_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_P_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_P_POS)) -#define SPI_CR_SPI_RXD_IGNR_S SPI_CR_SPI_RXD_IGNR_S -#define SPI_CR_SPI_RXD_IGNR_S_POS (16U) -#define SPI_CR_SPI_RXD_IGNR_S_LEN (5U) -#define SPI_CR_SPI_RXD_IGNR_S_MSK (((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS) -#define SPI_CR_SPI_RXD_IGNR_S_UMSK (~(((1U << SPI_CR_SPI_RXD_IGNR_S_LEN) - 1) << SPI_CR_SPI_RXD_IGNR_S_POS)) - -/* 0x1C : spi_sto_value */ -#define SPI_STO_VALUE_OFFSET (0x1C) -#define SPI_CR_SPI_STO_VALUE SPI_CR_SPI_STO_VALUE -#define SPI_CR_SPI_STO_VALUE_POS (0U) -#define SPI_CR_SPI_STO_VALUE_LEN (12U) -#define SPI_CR_SPI_STO_VALUE_MSK (((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS) -#define SPI_CR_SPI_STO_VALUE_UMSK (~(((1U << SPI_CR_SPI_STO_VALUE_LEN) - 1) << SPI_CR_SPI_STO_VALUE_POS)) - -/* 0x80 : spi_fifo_config_0 */ -#define SPI_FIFO_CONFIG_0_OFFSET (0x80) -#define SPI_DMA_TX_EN SPI_DMA_TX_EN -#define SPI_DMA_TX_EN_POS (0U) -#define SPI_DMA_TX_EN_LEN (1U) -#define SPI_DMA_TX_EN_MSK (((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS) -#define SPI_DMA_TX_EN_UMSK (~(((1U << SPI_DMA_TX_EN_LEN) - 1) << SPI_DMA_TX_EN_POS)) -#define SPI_DMA_RX_EN SPI_DMA_RX_EN -#define SPI_DMA_RX_EN_POS (1U) -#define SPI_DMA_RX_EN_LEN (1U) -#define SPI_DMA_RX_EN_MSK (((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS) -#define SPI_DMA_RX_EN_UMSK (~(((1U << SPI_DMA_RX_EN_LEN) - 1) << SPI_DMA_RX_EN_POS)) -#define SPI_TX_FIFO_CLR SPI_TX_FIFO_CLR -#define SPI_TX_FIFO_CLR_POS (2U) -#define SPI_TX_FIFO_CLR_LEN (1U) -#define SPI_TX_FIFO_CLR_MSK (((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS) -#define SPI_TX_FIFO_CLR_UMSK (~(((1U << SPI_TX_FIFO_CLR_LEN) - 1) << SPI_TX_FIFO_CLR_POS)) -#define SPI_RX_FIFO_CLR SPI_RX_FIFO_CLR -#define SPI_RX_FIFO_CLR_POS (3U) -#define SPI_RX_FIFO_CLR_LEN (1U) -#define SPI_RX_FIFO_CLR_MSK (((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS) -#define SPI_RX_FIFO_CLR_UMSK (~(((1U << SPI_RX_FIFO_CLR_LEN) - 1) << SPI_RX_FIFO_CLR_POS)) -#define SPI_TX_FIFO_OVERFLOW SPI_TX_FIFO_OVERFLOW -#define SPI_TX_FIFO_OVERFLOW_POS (4U) -#define SPI_TX_FIFO_OVERFLOW_LEN (1U) -#define SPI_TX_FIFO_OVERFLOW_MSK (((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS) -#define SPI_TX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_TX_FIFO_OVERFLOW_LEN) - 1) << SPI_TX_FIFO_OVERFLOW_POS)) -#define SPI_TX_FIFO_UNDERFLOW SPI_TX_FIFO_UNDERFLOW -#define SPI_TX_FIFO_UNDERFLOW_POS (5U) -#define SPI_TX_FIFO_UNDERFLOW_LEN (1U) -#define SPI_TX_FIFO_UNDERFLOW_MSK (((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS) -#define SPI_TX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_TX_FIFO_UNDERFLOW_LEN) - 1) << SPI_TX_FIFO_UNDERFLOW_POS)) -#define SPI_RX_FIFO_OVERFLOW SPI_RX_FIFO_OVERFLOW -#define SPI_RX_FIFO_OVERFLOW_POS (6U) -#define SPI_RX_FIFO_OVERFLOW_LEN (1U) -#define SPI_RX_FIFO_OVERFLOW_MSK (((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS) -#define SPI_RX_FIFO_OVERFLOW_UMSK (~(((1U << SPI_RX_FIFO_OVERFLOW_LEN) - 1) << SPI_RX_FIFO_OVERFLOW_POS)) -#define SPI_RX_FIFO_UNDERFLOW SPI_RX_FIFO_UNDERFLOW -#define SPI_RX_FIFO_UNDERFLOW_POS (7U) -#define SPI_RX_FIFO_UNDERFLOW_LEN (1U) -#define SPI_RX_FIFO_UNDERFLOW_MSK (((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS) -#define SPI_RX_FIFO_UNDERFLOW_UMSK (~(((1U << SPI_RX_FIFO_UNDERFLOW_LEN) - 1) << SPI_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : spi_fifo_config_1 */ -#define SPI_FIFO_CONFIG_1_OFFSET (0x84) -#define SPI_TX_FIFO_CNT SPI_TX_FIFO_CNT -#define SPI_TX_FIFO_CNT_POS (0U) -#define SPI_TX_FIFO_CNT_LEN (6U) -#define SPI_TX_FIFO_CNT_MSK (((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS) -#define SPI_TX_FIFO_CNT_UMSK (~(((1U << SPI_TX_FIFO_CNT_LEN) - 1) << SPI_TX_FIFO_CNT_POS)) -#define SPI_RX_FIFO_CNT SPI_RX_FIFO_CNT -#define SPI_RX_FIFO_CNT_POS (8U) -#define SPI_RX_FIFO_CNT_LEN (6U) -#define SPI_RX_FIFO_CNT_MSK (((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS) -#define SPI_RX_FIFO_CNT_UMSK (~(((1U << SPI_RX_FIFO_CNT_LEN) - 1) << SPI_RX_FIFO_CNT_POS)) -#define SPI_TX_FIFO_TH SPI_TX_FIFO_TH -#define SPI_TX_FIFO_TH_POS (16U) -#define SPI_TX_FIFO_TH_LEN (5U) -#define SPI_TX_FIFO_TH_MSK (((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS) -#define SPI_TX_FIFO_TH_UMSK (~(((1U << SPI_TX_FIFO_TH_LEN) - 1) << SPI_TX_FIFO_TH_POS)) -#define SPI_RX_FIFO_TH SPI_RX_FIFO_TH -#define SPI_RX_FIFO_TH_POS (24U) -#define SPI_RX_FIFO_TH_LEN (5U) -#define SPI_RX_FIFO_TH_MSK (((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS) -#define SPI_RX_FIFO_TH_UMSK (~(((1U << SPI_RX_FIFO_TH_LEN) - 1) << SPI_RX_FIFO_TH_POS)) - -/* 0x88 : spi_fifo_wdata */ -#define SPI_FIFO_WDATA_OFFSET (0x88) -#define SPI_FIFO_WDATA SPI_FIFO_WDATA -#define SPI_FIFO_WDATA_POS (0U) -#define SPI_FIFO_WDATA_LEN (32U) -#define SPI_FIFO_WDATA_MSK (((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS) -#define SPI_FIFO_WDATA_UMSK (~(((1U << SPI_FIFO_WDATA_LEN) - 1) << SPI_FIFO_WDATA_POS)) - -/* 0x8C : spi_fifo_rdata */ -#define SPI_FIFO_RDATA_OFFSET (0x8C) -#define SPI_FIFO_RDATA SPI_FIFO_RDATA -#define SPI_FIFO_RDATA_POS (0U) -#define SPI_FIFO_RDATA_LEN (32U) -#define SPI_FIFO_RDATA_MSK (((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS) -#define SPI_FIFO_RDATA_UMSK (~(((1U << SPI_FIFO_RDATA_LEN) - 1) << SPI_FIFO_RDATA_POS)) - -/* 0xFC : backup_io_en */ -#define SPI_BACKUP_IO_EN_OFFSET (0xFC) -#define SPI_BACKUP_IO_EN SPI_BACKUP_IO_EN -#define SPI_BACKUP_IO_EN_POS (0U) -#define SPI_BACKUP_IO_EN_LEN (1U) -#define SPI_BACKUP_IO_EN_MSK (((1U << SPI_BACKUP_IO_EN_LEN) - 1) << SPI_BACKUP_IO_EN_POS) -#define SPI_BACKUP_IO_EN_UMSK (~(((1U << SPI_BACKUP_IO_EN_LEN) - 1) << SPI_BACKUP_IO_EN_POS)) - -struct spi_reg { - /* 0x0 : spi_config */ - union { - struct { - uint32_t cr_spi_m_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_spi_s_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_spi_frame_size : 2; /* [ 3: 2], r/w, 0x0 */ - uint32_t cr_spi_sclk_pol : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_spi_sclk_ph : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_spi_bit_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_spi_byte_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_spi_rxd_ignr_en : 1; /* [ 8], r/w, 0x0 */ - uint32_t cr_spi_m_cont_en : 1; /* [ 9], r/w, 0x0 */ - uint32_t cr_spi_s_3pin_mode : 1; /* [ 10], r/w, 0x0 */ - uint32_t cr_spi_deg_en : 1; /* [ 11], r/w, 0x0 */ - uint32_t cr_spi_deg_cnt : 4; /* [15:12], r/w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_config; - - /* 0x4 : spi_int_sts */ - union { - struct { - uint32_t spi_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t spi_txf_int : 1; /* [ 1], r, 0x1 */ - uint32_t spi_rxf_int : 1; /* [ 2], r, 0x0 */ - uint32_t spi_sto_int : 1; /* [ 3], r, 0x0 */ - uint32_t spi_txu_int : 1; /* [ 4], r, 0x0 */ - uint32_t spi_fer_int : 1; /* [ 5], r, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t cr_spi_end_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_spi_txf_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_spi_rxf_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_spi_sto_mask : 1; /* [ 11], r/w, 0x1 */ - uint32_t cr_spi_txu_mask : 1; /* [ 12], r/w, 0x1 */ - uint32_t cr_spi_fer_mask : 1; /* [ 13], r/w, 0x1 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t cr_spi_end_clr : 1; /* [ 16], w1c, 0x0 */ - uint32_t rsvd_17 : 1; /* [ 17], rsvd, 0x0 */ - uint32_t rsvd_18 : 1; /* [ 18], rsvd, 0x0 */ - uint32_t cr_spi_sto_clr : 1; /* [ 19], w1c, 0x0 */ - uint32_t cr_spi_txu_clr : 1; /* [ 20], w1c, 0x0 */ - uint32_t rsvd_21 : 1; /* [ 21], rsvd, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t cr_spi_end_en : 1; /* [ 24], r/w, 0x1 */ - uint32_t cr_spi_txf_en : 1; /* [ 25], r/w, 0x1 */ - uint32_t cr_spi_rxf_en : 1; /* [ 26], r/w, 0x1 */ - uint32_t cr_spi_sto_en : 1; /* [ 27], r/w, 0x1 */ - uint32_t cr_spi_txu_en : 1; /* [ 28], r/w, 0x1 */ - uint32_t cr_spi_fer_en : 1; /* [ 29], r/w, 0x1 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_int_sts; - - /* 0x8 : spi_bus_busy */ - union { - struct { - uint32_t sts_spi_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_bus_busy; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x10 : spi_prd_0 */ - union { - struct { - uint32_t cr_spi_prd_s : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t cr_spi_prd_p : 8; /* [15: 8], r/w, 0xf */ - uint32_t cr_spi_prd_d_ph_0 : 8; /* [23:16], r/w, 0xf */ - uint32_t cr_spi_prd_d_ph_1 : 8; /* [31:24], r/w, 0xf */ - } BF; - uint32_t WORD; - } spi_prd_0; - - /* 0x14 : spi_prd_1 */ - union { - struct { - uint32_t cr_spi_prd_i : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_prd_1; - - /* 0x18 : spi_rxd_ignr */ - union { - struct { - uint32_t cr_spi_rxd_ignr_p : 5; /* [ 4: 0], r/w, 0x0 */ - uint32_t reserved_5_15 : 11; /* [15: 5], rsvd, 0x0 */ - uint32_t cr_spi_rxd_ignr_s : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_rxd_ignr; - - /* 0x1C : spi_sto_value */ - union { - struct { - uint32_t cr_spi_sto_value : 12; /* [11: 0], r/w, 0xfff */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_sto_value; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[96]; - - /* 0x80 : spi_fifo_config_0 */ - union { - struct { - uint32_t spi_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t spi_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_fifo_config_0; - - /* 0x84 : spi_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } spi_fifo_config_1; - - /* 0x88 : spi_fifo_wdata */ - union { - struct { - uint32_t spi_fifo_wdata : 32; /* [31: 0], w, x */ - } BF; - uint32_t WORD; - } spi_fifo_wdata; - - /* 0x8C : spi_fifo_rdata */ - union { - struct { - uint32_t spi_fifo_rdata : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } spi_fifo_rdata; - - /* 0x90 reserved */ - uint8_t RESERVED0x90[108]; - - /* 0xFC : backup_io_en */ - union { - struct { - uint32_t backup_io_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } backup_io_en; -}; - -typedef volatile struct spi_reg spi_reg_t; - -#endif /* __SPI_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/timer_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/timer_reg.h deleted file mode 100644 index 9f07d690a2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/timer_reg.h +++ /dev/null @@ -1,963 +0,0 @@ -/** - ****************************************************************************** - * @file timer_reg.h - * @version V1.0 - * @date 2022-03-03 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __TIMER_REG_H__ -#define __TIMER_REG_H__ - -#include "bl808.h" - -/* 0x0 : Timer Clock Source */ -#define TIMER_TCCR_OFFSET (0x0) -#define TIMER_CS_2 TIMER_CS_2 -#define TIMER_CS_2_POS (0U) -#define TIMER_CS_2_LEN (4U) -#define TIMER_CS_2_MSK (((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS) -#define TIMER_CS_2_UMSK (~(((1U << TIMER_CS_2_LEN) - 1) << TIMER_CS_2_POS)) -#define TIMER_CS_3 TIMER_CS_3 -#define TIMER_CS_3_POS (4U) -#define TIMER_CS_3_LEN (4U) -#define TIMER_CS_3_MSK (((1U << TIMER_CS_3_LEN) - 1) << TIMER_CS_3_POS) -#define TIMER_CS_3_UMSK (~(((1U << TIMER_CS_3_LEN) - 1) << TIMER_CS_3_POS)) -#define TIMER_CS_WDT TIMER_CS_WDT -#define TIMER_CS_WDT_POS (8U) -#define TIMER_CS_WDT_LEN (4U) -#define TIMER_CS_WDT_MSK (((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS) -#define TIMER_CS_WDT_UMSK (~(((1U << TIMER_CS_WDT_LEN) - 1) << TIMER_CS_WDT_POS)) -#define TIMER_TMR_RSV TIMER_TMR_RSV -#define TIMER_TMR_RSV_POS (16U) -#define TIMER_TMR_RSV_LEN (8U) -#define TIMER_TMR_RSV_MSK (((1U << TIMER_TMR_RSV_LEN) - 1) << TIMER_TMR_RSV_POS) -#define TIMER_TMR_RSV_UMSK (~(((1U << TIMER_TMR_RSV_LEN) - 1) << TIMER_TMR_RSV_POS)) -#define TIMER_ID TIMER_ID -#define TIMER_ID_POS (24U) -#define TIMER_ID_LEN (8U) -#define TIMER_ID_MSK (((1U << TIMER_ID_LEN) - 1) << TIMER_ID_POS) -#define TIMER_ID_UMSK (~(((1U << TIMER_ID_LEN) - 1) << TIMER_ID_POS)) - -/* 0x10 : Timer2 Match Value 0 */ -#define TIMER_TMR2_0_OFFSET (0x10) -#define TIMER_TMR2_0 TIMER_TMR2_0 -#define TIMER_TMR2_0_POS (0U) -#define TIMER_TMR2_0_LEN (32U) -#define TIMER_TMR2_0_MSK (((1U << TIMER_TMR2_0_LEN) - 1) << TIMER_TMR2_0_POS) -#define TIMER_TMR2_0_UMSK (~(((1U << TIMER_TMR2_0_LEN) - 1) << TIMER_TMR2_0_POS)) - -/* 0x14 : Timer2 Match Value 1 */ -#define TIMER_TMR2_1_OFFSET (0x14) -#define TIMER_TMR2_1 TIMER_TMR2_1 -#define TIMER_TMR2_1_POS (0U) -#define TIMER_TMR2_1_LEN (32U) -#define TIMER_TMR2_1_MSK (((1U << TIMER_TMR2_1_LEN) - 1) << TIMER_TMR2_1_POS) -#define TIMER_TMR2_1_UMSK (~(((1U << TIMER_TMR2_1_LEN) - 1) << TIMER_TMR2_1_POS)) - -/* 0x18 : Timer2 Match Value 2 */ -#define TIMER_TMR2_2_OFFSET (0x18) -#define TIMER_TMR2_2 TIMER_TMR2_2 -#define TIMER_TMR2_2_POS (0U) -#define TIMER_TMR2_2_LEN (32U) -#define TIMER_TMR2_2_MSK (((1U << TIMER_TMR2_2_LEN) - 1) << TIMER_TMR2_2_POS) -#define TIMER_TMR2_2_UMSK (~(((1U << TIMER_TMR2_2_LEN) - 1) << TIMER_TMR2_2_POS)) - -/* 0x1C : Timer3 Match Value 0 */ -#define TIMER_TMR3_0_OFFSET (0x1C) -#define TIMER_TMR3_0 TIMER_TMR3_0 -#define TIMER_TMR3_0_POS (0U) -#define TIMER_TMR3_0_LEN (32U) -#define TIMER_TMR3_0_MSK (((1U << TIMER_TMR3_0_LEN) - 1) << TIMER_TMR3_0_POS) -#define TIMER_TMR3_0_UMSK (~(((1U << TIMER_TMR3_0_LEN) - 1) << TIMER_TMR3_0_POS)) - -/* 0x20 : Timer3 Match Value 1 */ -#define TIMER_TMR3_1_OFFSET (0x20) -#define TIMER_TMR3_1 TIMER_TMR3_1 -#define TIMER_TMR3_1_POS (0U) -#define TIMER_TMR3_1_LEN (32U) -#define TIMER_TMR3_1_MSK (((1U << TIMER_TMR3_1_LEN) - 1) << TIMER_TMR3_1_POS) -#define TIMER_TMR3_1_UMSK (~(((1U << TIMER_TMR3_1_LEN) - 1) << TIMER_TMR3_1_POS)) - -/* 0x24 : Timer3 Match Value 2 */ -#define TIMER_TMR3_2_OFFSET (0x24) -#define TIMER_TMR3_2 TIMER_TMR3_2 -#define TIMER_TMR3_2_POS (0U) -#define TIMER_TMR3_2_LEN (32U) -#define TIMER_TMR3_2_MSK (((1U << TIMER_TMR3_2_LEN) - 1) << TIMER_TMR3_2_POS) -#define TIMER_TMR3_2_UMSK (~(((1U << TIMER_TMR3_2_LEN) - 1) << TIMER_TMR3_2_POS)) - -/* 0x2C : Timer2 Counter Value */ -#define TIMER_TCR2_OFFSET (0x2C) -#define TIMER_TCR2_CNT TIMER_TCR2_CNT -#define TIMER_TCR2_CNT_POS (0U) -#define TIMER_TCR2_CNT_LEN (32U) -#define TIMER_TCR2_CNT_MSK (((1U << TIMER_TCR2_CNT_LEN) - 1) << TIMER_TCR2_CNT_POS) -#define TIMER_TCR2_CNT_UMSK (~(((1U << TIMER_TCR2_CNT_LEN) - 1) << TIMER_TCR2_CNT_POS)) - -/* 0x30 : Timer3 Counter Value */ -#define TIMER_TCR3_OFFSET (0x30) -#define TIMER_TCR3_CNT TIMER_TCR3_CNT -#define TIMER_TCR3_CNT_POS (0U) -#define TIMER_TCR3_CNT_LEN (32U) -#define TIMER_TCR3_CNT_MSK (((1U << TIMER_TCR3_CNT_LEN) - 1) << TIMER_TCR3_CNT_POS) -#define TIMER_TCR3_CNT_UMSK (~(((1U << TIMER_TCR3_CNT_LEN) - 1) << TIMER_TCR3_CNT_POS)) - -/* 0x38 : Timer2 Match Status */ -#define TIMER_TSR2_OFFSET (0x38) -#define TIMER_TSR2_0 TIMER_TSR2_0 -#define TIMER_TSR2_0_POS (0U) -#define TIMER_TSR2_0_LEN (1U) -#define TIMER_TSR2_0_MSK (((1U << TIMER_TSR2_0_LEN) - 1) << TIMER_TSR2_0_POS) -#define TIMER_TSR2_0_UMSK (~(((1U << TIMER_TSR2_0_LEN) - 1) << TIMER_TSR2_0_POS)) -#define TIMER_TSR2_1 TIMER_TSR2_1 -#define TIMER_TSR2_1_POS (1U) -#define TIMER_TSR2_1_LEN (1U) -#define TIMER_TSR2_1_MSK (((1U << TIMER_TSR2_1_LEN) - 1) << TIMER_TSR2_1_POS) -#define TIMER_TSR2_1_UMSK (~(((1U << TIMER_TSR2_1_LEN) - 1) << TIMER_TSR2_1_POS)) -#define TIMER_TSR2_2 TIMER_TSR2_2 -#define TIMER_TSR2_2_POS (2U) -#define TIMER_TSR2_2_LEN (1U) -#define TIMER_TSR2_2_MSK (((1U << TIMER_TSR2_2_LEN) - 1) << TIMER_TSR2_2_POS) -#define TIMER_TSR2_2_UMSK (~(((1U << TIMER_TSR2_2_LEN) - 1) << TIMER_TSR2_2_POS)) - -/* 0x3C : Timer3 Match Status */ -#define TIMER_TSR3_OFFSET (0x3C) -#define TIMER_TSR3_0 TIMER_TSR3_0 -#define TIMER_TSR3_0_POS (0U) -#define TIMER_TSR3_0_LEN (1U) -#define TIMER_TSR3_0_MSK (((1U << TIMER_TSR3_0_LEN) - 1) << TIMER_TSR3_0_POS) -#define TIMER_TSR3_0_UMSK (~(((1U << TIMER_TSR3_0_LEN) - 1) << TIMER_TSR3_0_POS)) -#define TIMER_TSR3_1 TIMER_TSR3_1 -#define TIMER_TSR3_1_POS (1U) -#define TIMER_TSR3_1_LEN (1U) -#define TIMER_TSR3_1_MSK (((1U << TIMER_TSR3_1_LEN) - 1) << TIMER_TSR3_1_POS) -#define TIMER_TSR3_1_UMSK (~(((1U << TIMER_TSR3_1_LEN) - 1) << TIMER_TSR3_1_POS)) -#define TIMER_TSR3_2 TIMER_TSR3_2 -#define TIMER_TSR3_2_POS (2U) -#define TIMER_TSR3_2_LEN (1U) -#define TIMER_TSR3_2_MSK (((1U << TIMER_TSR3_2_LEN) - 1) << TIMER_TSR3_2_POS) -#define TIMER_TSR3_2_UMSK (~(((1U << TIMER_TSR3_2_LEN) - 1) << TIMER_TSR3_2_POS)) - -/* 0x44 : Timer2 Match Interrupt Enable */ -#define TIMER_TIER2_OFFSET (0x44) -#define TIMER_TIER2_0 TIMER_TIER2_0 -#define TIMER_TIER2_0_POS (0U) -#define TIMER_TIER2_0_LEN (1U) -#define TIMER_TIER2_0_MSK (((1U << TIMER_TIER2_0_LEN) - 1) << TIMER_TIER2_0_POS) -#define TIMER_TIER2_0_UMSK (~(((1U << TIMER_TIER2_0_LEN) - 1) << TIMER_TIER2_0_POS)) -#define TIMER_TIER2_1 TIMER_TIER2_1 -#define TIMER_TIER2_1_POS (1U) -#define TIMER_TIER2_1_LEN (1U) -#define TIMER_TIER2_1_MSK (((1U << TIMER_TIER2_1_LEN) - 1) << TIMER_TIER2_1_POS) -#define TIMER_TIER2_1_UMSK (~(((1U << TIMER_TIER2_1_LEN) - 1) << TIMER_TIER2_1_POS)) -#define TIMER_TIER2_2 TIMER_TIER2_2 -#define TIMER_TIER2_2_POS (2U) -#define TIMER_TIER2_2_LEN (1U) -#define TIMER_TIER2_2_MSK (((1U << TIMER_TIER2_2_LEN) - 1) << TIMER_TIER2_2_POS) -#define TIMER_TIER2_2_UMSK (~(((1U << TIMER_TIER2_2_LEN) - 1) << TIMER_TIER2_2_POS)) - -/* 0x48 : Timer3 Match Interrupt Enable */ -#define TIMER_TIER3_OFFSET (0x48) -#define TIMER_TIER3_0 TIMER_TIER3_0 -#define TIMER_TIER3_0_POS (0U) -#define TIMER_TIER3_0_LEN (1U) -#define TIMER_TIER3_0_MSK (((1U << TIMER_TIER3_0_LEN) - 1) << TIMER_TIER3_0_POS) -#define TIMER_TIER3_0_UMSK (~(((1U << TIMER_TIER3_0_LEN) - 1) << TIMER_TIER3_0_POS)) -#define TIMER_TIER3_1 TIMER_TIER3_1 -#define TIMER_TIER3_1_POS (1U) -#define TIMER_TIER3_1_LEN (1U) -#define TIMER_TIER3_1_MSK (((1U << TIMER_TIER3_1_LEN) - 1) << TIMER_TIER3_1_POS) -#define TIMER_TIER3_1_UMSK (~(((1U << TIMER_TIER3_1_LEN) - 1) << TIMER_TIER3_1_POS)) -#define TIMER_TIER3_2 TIMER_TIER3_2 -#define TIMER_TIER3_2_POS (2U) -#define TIMER_TIER3_2_LEN (1U) -#define TIMER_TIER3_2_MSK (((1U << TIMER_TIER3_2_LEN) - 1) << TIMER_TIER3_2_POS) -#define TIMER_TIER3_2_UMSK (~(((1U << TIMER_TIER3_2_LEN) - 1) << TIMER_TIER3_2_POS)) - -/* 0x50 : Timer2 Pre-Load Value */ -#define TIMER_TPLVR2_OFFSET (0x50) -#define TIMER_TPLVR2 TIMER_TPLVR2 -#define TIMER_TPLVR2_POS (0U) -#define TIMER_TPLVR2_LEN (32U) -#define TIMER_TPLVR2_MSK (((1U << TIMER_TPLVR2_LEN) - 1) << TIMER_TPLVR2_POS) -#define TIMER_TPLVR2_UMSK (~(((1U << TIMER_TPLVR2_LEN) - 1) << TIMER_TPLVR2_POS)) - -/* 0x54 : Timer3 Pre-Load Value */ -#define TIMER_TPLVR3_OFFSET (0x54) -#define TIMER_TPLVR3 TIMER_TPLVR3 -#define TIMER_TPLVR3_POS (0U) -#define TIMER_TPLVR3_LEN (32U) -#define TIMER_TPLVR3_MSK (((1U << TIMER_TPLVR3_LEN) - 1) << TIMER_TPLVR3_POS) -#define TIMER_TPLVR3_UMSK (~(((1U << TIMER_TPLVR3_LEN) - 1) << TIMER_TPLVR3_POS)) - -/* 0x5C : Timer2 Pre-Load Control */ -#define TIMER_TPLCR2_OFFSET (0x5C) -#define TIMER_TPLCR2 TIMER_TPLCR2 -#define TIMER_TPLCR2_POS (0U) -#define TIMER_TPLCR2_LEN (2U) -#define TIMER_TPLCR2_MSK (((1U << TIMER_TPLCR2_LEN) - 1) << TIMER_TPLCR2_POS) -#define TIMER_TPLCR2_UMSK (~(((1U << TIMER_TPLCR2_LEN) - 1) << TIMER_TPLCR2_POS)) - -/* 0x60 : Timer3 Pre-Load Control */ -#define TIMER_TPLCR3_OFFSET (0x60) -#define TIMER_TPLCR3 TIMER_TPLCR3 -#define TIMER_TPLCR3_POS (0U) -#define TIMER_TPLCR3_LEN (2U) -#define TIMER_TPLCR3_MSK (((1U << TIMER_TPLCR3_LEN) - 1) << TIMER_TPLCR3_POS) -#define TIMER_TPLCR3_UMSK (~(((1U << TIMER_TPLCR3_LEN) - 1) << TIMER_TPLCR3_POS)) - -/* 0x64 : Watch-dog reset/interrupt Mode */ -#define TIMER_WMER_OFFSET (0x64) -#define TIMER_WE TIMER_WE -#define TIMER_WE_POS (0U) -#define TIMER_WE_LEN (1U) -#define TIMER_WE_MSK (((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS) -#define TIMER_WE_UMSK (~(((1U << TIMER_WE_LEN) - 1) << TIMER_WE_POS)) -#define TIMER_WRIE TIMER_WRIE -#define TIMER_WRIE_POS (1U) -#define TIMER_WRIE_LEN (1U) -#define TIMER_WRIE_MSK (((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS) -#define TIMER_WRIE_UMSK (~(((1U << TIMER_WRIE_LEN) - 1) << TIMER_WRIE_POS)) - -/* 0x68 : Watch-dog Match Value */ -#define TIMER_WMR_OFFSET (0x68) -#define TIMER_WMR TIMER_WMR -#define TIMER_WMR_POS (0U) -#define TIMER_WMR_LEN (16U) -#define TIMER_WMR_MSK (((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS) -#define TIMER_WMR_UMSK (~(((1U << TIMER_WMR_LEN) - 1) << TIMER_WMR_POS)) -#define TIMER_WDT_ALIGN TIMER_WDT_ALIGN -#define TIMER_WDT_ALIGN_POS (16U) -#define TIMER_WDT_ALIGN_LEN (1U) -#define TIMER_WDT_ALIGN_MSK (((1U << TIMER_WDT_ALIGN_LEN) - 1) << TIMER_WDT_ALIGN_POS) -#define TIMER_WDT_ALIGN_UMSK (~(((1U << TIMER_WDT_ALIGN_LEN) - 1) << TIMER_WDT_ALIGN_POS)) - -/* 0x6C : Watch-dog Counter Value */ -#define TIMER_WVR_OFFSET (0x6C) -#define TIMER_WDT_CNT TIMER_WDT_CNT -#define TIMER_WDT_CNT_POS (0U) -#define TIMER_WDT_CNT_LEN (16U) -#define TIMER_WDT_CNT_MSK (((1U << TIMER_WDT_CNT_LEN) - 1) << TIMER_WDT_CNT_POS) -#define TIMER_WDT_CNT_UMSK (~(((1U << TIMER_WDT_CNT_LEN) - 1) << TIMER_WDT_CNT_POS)) - -/* 0x70 : Watch-dog Reset Status */ -#define TIMER_WSR_OFFSET (0x70) -#define TIMER_WTS TIMER_WTS -#define TIMER_WTS_POS (0U) -#define TIMER_WTS_LEN (1U) -#define TIMER_WTS_MSK (((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS) -#define TIMER_WTS_UMSK (~(((1U << TIMER_WTS_LEN) - 1) << TIMER_WTS_POS)) - -/* 0x78 : Timer2 Interrupt Clear */ -#define TIMER_TICR2_OFFSET (0x78) -#define TIMER_TCLR2_0 TIMER_TCLR2_0 -#define TIMER_TCLR2_0_POS (0U) -#define TIMER_TCLR2_0_LEN (1U) -#define TIMER_TCLR2_0_MSK (((1U << TIMER_TCLR2_0_LEN) - 1) << TIMER_TCLR2_0_POS) -#define TIMER_TCLR2_0_UMSK (~(((1U << TIMER_TCLR2_0_LEN) - 1) << TIMER_TCLR2_0_POS)) -#define TIMER_TCLR2_1 TIMER_TCLR2_1 -#define TIMER_TCLR2_1_POS (1U) -#define TIMER_TCLR2_1_LEN (1U) -#define TIMER_TCLR2_1_MSK (((1U << TIMER_TCLR2_1_LEN) - 1) << TIMER_TCLR2_1_POS) -#define TIMER_TCLR2_1_UMSK (~(((1U << TIMER_TCLR2_1_LEN) - 1) << TIMER_TCLR2_1_POS)) -#define TIMER_TCLR2_2 TIMER_TCLR2_2 -#define TIMER_TCLR2_2_POS (2U) -#define TIMER_TCLR2_2_LEN (1U) -#define TIMER_TCLR2_2_MSK (((1U << TIMER_TCLR2_2_LEN) - 1) << TIMER_TCLR2_2_POS) -#define TIMER_TCLR2_2_UMSK (~(((1U << TIMER_TCLR2_2_LEN) - 1) << TIMER_TCLR2_2_POS)) - -/* 0x7C : Timer3 Interrupt Clear */ -#define TIMER_TICR3_OFFSET (0x7C) -#define TIMER_TCLR3_0 TIMER_TCLR3_0 -#define TIMER_TCLR3_0_POS (0U) -#define TIMER_TCLR3_0_LEN (1U) -#define TIMER_TCLR3_0_MSK (((1U << TIMER_TCLR3_0_LEN) - 1) << TIMER_TCLR3_0_POS) -#define TIMER_TCLR3_0_UMSK (~(((1U << TIMER_TCLR3_0_LEN) - 1) << TIMER_TCLR3_0_POS)) -#define TIMER_TCLR3_1 TIMER_TCLR3_1 -#define TIMER_TCLR3_1_POS (1U) -#define TIMER_TCLR3_1_LEN (1U) -#define TIMER_TCLR3_1_MSK (((1U << TIMER_TCLR3_1_LEN) - 1) << TIMER_TCLR3_1_POS) -#define TIMER_TCLR3_1_UMSK (~(((1U << TIMER_TCLR3_1_LEN) - 1) << TIMER_TCLR3_1_POS)) -#define TIMER_TCLR3_2 TIMER_TCLR3_2 -#define TIMER_TCLR3_2_POS (2U) -#define TIMER_TCLR3_2_LEN (1U) -#define TIMER_TCLR3_2_MSK (((1U << TIMER_TCLR3_2_LEN) - 1) << TIMER_TCLR3_2_POS) -#define TIMER_TCLR3_2_UMSK (~(((1U << TIMER_TCLR3_2_LEN) - 1) << TIMER_TCLR3_2_POS)) - -/* 0x80 : WDT Interrupt Clear */ -#define TIMER_WICR_OFFSET (0x80) -#define TIMER_WICLR TIMER_WICLR -#define TIMER_WICLR_POS (0U) -#define TIMER_WICLR_LEN (1U) -#define TIMER_WICLR_MSK (((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS) -#define TIMER_WICLR_UMSK (~(((1U << TIMER_WICLR_LEN) - 1) << TIMER_WICLR_POS)) - -/* 0x84 : Timer Counter Enable/Clear */ -#define TIMER_TCER_OFFSET (0x84) -#define TIMER2_EN TIMER2_EN -#define TIMER2_EN_POS (1U) -#define TIMER2_EN_LEN (1U) -#define TIMER2_EN_MSK (((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS) -#define TIMER2_EN_UMSK (~(((1U << TIMER2_EN_LEN) - 1) << TIMER2_EN_POS)) -#define TIMER3_EN TIMER3_EN -#define TIMER3_EN_POS (2U) -#define TIMER3_EN_LEN (1U) -#define TIMER3_EN_MSK (((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS) -#define TIMER3_EN_UMSK (~(((1U << TIMER3_EN_LEN) - 1) << TIMER3_EN_POS)) -#define TIMER_TCR2_CNT_CLR TIMER_TCR2_CNT_CLR -#define TIMER_TCR2_CNT_CLR_POS (5U) -#define TIMER_TCR2_CNT_CLR_LEN (1U) -#define TIMER_TCR2_CNT_CLR_MSK (((1U << TIMER_TCR2_CNT_CLR_LEN) - 1) << TIMER_TCR2_CNT_CLR_POS) -#define TIMER_TCR2_CNT_CLR_UMSK (~(((1U << TIMER_TCR2_CNT_CLR_LEN) - 1) << TIMER_TCR2_CNT_CLR_POS)) -#define TIMER_TCR3_CNT_CLR TIMER_TCR3_CNT_CLR -#define TIMER_TCR3_CNT_CLR_POS (6U) -#define TIMER_TCR3_CNT_CLR_LEN (1U) -#define TIMER_TCR3_CNT_CLR_MSK (((1U << TIMER_TCR3_CNT_CLR_LEN) - 1) << TIMER_TCR3_CNT_CLR_POS) -#define TIMER_TCR3_CNT_CLR_UMSK (~(((1U << TIMER_TCR3_CNT_CLR_LEN) - 1) << TIMER_TCR3_CNT_CLR_POS)) - -/* 0x88 : Timer Counter Mode */ -#define TIMER_TCMR_OFFSET (0x88) -#define TIMER2_MODE TIMER2_MODE -#define TIMER2_MODE_POS (1U) -#define TIMER2_MODE_LEN (1U) -#define TIMER2_MODE_MSK (((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS) -#define TIMER2_MODE_UMSK (~(((1U << TIMER2_MODE_LEN) - 1) << TIMER2_MODE_POS)) -#define TIMER3_MODE TIMER3_MODE -#define TIMER3_MODE_POS (2U) -#define TIMER3_MODE_LEN (1U) -#define TIMER3_MODE_MSK (((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS) -#define TIMER3_MODE_UMSK (~(((1U << TIMER3_MODE_LEN) - 1) << TIMER3_MODE_POS)) -#define TIMER2_ALIGN TIMER2_ALIGN -#define TIMER2_ALIGN_POS (5U) -#define TIMER2_ALIGN_LEN (1U) -#define TIMER2_ALIGN_MSK (((1U << TIMER2_ALIGN_LEN) - 1) << TIMER2_ALIGN_POS) -#define TIMER2_ALIGN_UMSK (~(((1U << TIMER2_ALIGN_LEN) - 1) << TIMER2_ALIGN_POS)) -#define TIMER3_ALIGN TIMER3_ALIGN -#define TIMER3_ALIGN_POS (6U) -#define TIMER3_ALIGN_LEN (1U) -#define TIMER3_ALIGN_MSK (((1U << TIMER3_ALIGN_LEN) - 1) << TIMER3_ALIGN_POS) -#define TIMER3_ALIGN_UMSK (~(((1U << TIMER3_ALIGN_LEN) - 1) << TIMER3_ALIGN_POS)) - -/* 0x90 : Timer2 Match Interrupt Mode */ -#define TIMER_TILR2_OFFSET (0x90) -#define TIMER_TILR2_0 TIMER_TILR2_0 -#define TIMER_TILR2_0_POS (0U) -#define TIMER_TILR2_0_LEN (1U) -#define TIMER_TILR2_0_MSK (((1U << TIMER_TILR2_0_LEN) - 1) << TIMER_TILR2_0_POS) -#define TIMER_TILR2_0_UMSK (~(((1U << TIMER_TILR2_0_LEN) - 1) << TIMER_TILR2_0_POS)) -#define TIMER_TILR2_1 TIMER_TILR2_1 -#define TIMER_TILR2_1_POS (1U) -#define TIMER_TILR2_1_LEN (1U) -#define TIMER_TILR2_1_MSK (((1U << TIMER_TILR2_1_LEN) - 1) << TIMER_TILR2_1_POS) -#define TIMER_TILR2_1_UMSK (~(((1U << TIMER_TILR2_1_LEN) - 1) << TIMER_TILR2_1_POS)) -#define TIMER_TILR2_2 TIMER_TILR2_2 -#define TIMER_TILR2_2_POS (2U) -#define TIMER_TILR2_2_LEN (1U) -#define TIMER_TILR2_2_MSK (((1U << TIMER_TILR2_2_LEN) - 1) << TIMER_TILR2_2_POS) -#define TIMER_TILR2_2_UMSK (~(((1U << TIMER_TILR2_2_LEN) - 1) << TIMER_TILR2_2_POS)) - -/* 0x94 : Timer3 Match Interrupt Mode */ -#define TIMER_TILR3_OFFSET (0x94) -#define TIMER_TILR3_0 TIMER_TILR3_0 -#define TIMER_TILR3_0_POS (0U) -#define TIMER_TILR3_0_LEN (1U) -#define TIMER_TILR3_0_MSK (((1U << TIMER_TILR3_0_LEN) - 1) << TIMER_TILR3_0_POS) -#define TIMER_TILR3_0_UMSK (~(((1U << TIMER_TILR3_0_LEN) - 1) << TIMER_TILR3_0_POS)) -#define TIMER_TILR3_1 TIMER_TILR3_1 -#define TIMER_TILR3_1_POS (1U) -#define TIMER_TILR3_1_LEN (1U) -#define TIMER_TILR3_1_MSK (((1U << TIMER_TILR3_1_LEN) - 1) << TIMER_TILR3_1_POS) -#define TIMER_TILR3_1_UMSK (~(((1U << TIMER_TILR3_1_LEN) - 1) << TIMER_TILR3_1_POS)) -#define TIMER_TILR3_2 TIMER_TILR3_2 -#define TIMER_TILR3_2_POS (2U) -#define TIMER_TILR3_2_LEN (1U) -#define TIMER_TILR3_2_MSK (((1U << TIMER_TILR3_2_LEN) - 1) << TIMER_TILR3_2_POS) -#define TIMER_TILR3_2_UMSK (~(((1U << TIMER_TILR3_2_LEN) - 1) << TIMER_TILR3_2_POS)) - -/* 0x98 : WDT Counter Reset */ -#define TIMER_WCR_OFFSET (0x98) -#define TIMER_WCR TIMER_WCR -#define TIMER_WCR_POS (0U) -#define TIMER_WCR_LEN (1U) -#define TIMER_WCR_MSK (((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS) -#define TIMER_WCR_UMSK (~(((1U << TIMER_WCR_LEN) - 1) << TIMER_WCR_POS)) - -/* 0x9C : WDT Access Key1 */ -#define TIMER_WFAR_OFFSET (0x9C) -#define TIMER_WFAR TIMER_WFAR -#define TIMER_WFAR_POS (0U) -#define TIMER_WFAR_LEN (16U) -#define TIMER_WFAR_MSK (((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS) -#define TIMER_WFAR_UMSK (~(((1U << TIMER_WFAR_LEN) - 1) << TIMER_WFAR_POS)) - -/* 0xA0 : WDT Access Key2 */ -#define TIMER_WSAR_OFFSET (0xA0) -#define TIMER_WSAR TIMER_WSAR -#define TIMER_WSAR_POS (0U) -#define TIMER_WSAR_LEN (16U) -#define TIMER_WSAR_MSK (((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS) -#define TIMER_WSAR_UMSK (~(((1U << TIMER_WSAR_LEN) - 1) << TIMER_WSAR_POS)) - -/* 0xA8 : Timer2 Counter Latch Value */ -#define TIMER_TCVWR2_OFFSET (0xA8) -#define TIMER_TCR2_CNT_LAT TIMER_TCR2_CNT_LAT -#define TIMER_TCR2_CNT_LAT_POS (0U) -#define TIMER_TCR2_CNT_LAT_LEN (32U) -#define TIMER_TCR2_CNT_LAT_MSK (((1U << TIMER_TCR2_CNT_LAT_LEN) - 1) << TIMER_TCR2_CNT_LAT_POS) -#define TIMER_TCR2_CNT_LAT_UMSK (~(((1U << TIMER_TCR2_CNT_LAT_LEN) - 1) << TIMER_TCR2_CNT_LAT_POS)) - -/* 0xAC : Timer3 Counter Latch Value */ -#define TIMER_TCVWR3_OFFSET (0xAC) -#define TIMER_TCR3_CNT_LAT TIMER_TCR3_CNT_LAT -#define TIMER_TCR3_CNT_LAT_POS (0U) -#define TIMER_TCR3_CNT_LAT_LEN (32U) -#define TIMER_TCR3_CNT_LAT_MSK (((1U << TIMER_TCR3_CNT_LAT_LEN) - 1) << TIMER_TCR3_CNT_LAT_POS) -#define TIMER_TCR3_CNT_LAT_UMSK (~(((1U << TIMER_TCR3_CNT_LAT_LEN) - 1) << TIMER_TCR3_CNT_LAT_POS)) - -/* 0xB4 : Timer2 Counter Sync Value */ -#define TIMER_TCVSYN2_OFFSET (0xB4) -#define TIMER_TCR2_CNT_SYNC TIMER_TCR2_CNT_SYNC -#define TIMER_TCR2_CNT_SYNC_POS (0U) -#define TIMER_TCR2_CNT_SYNC_LEN (32U) -#define TIMER_TCR2_CNT_SYNC_MSK (((1U << TIMER_TCR2_CNT_SYNC_LEN) - 1) << TIMER_TCR2_CNT_SYNC_POS) -#define TIMER_TCR2_CNT_SYNC_UMSK (~(((1U << TIMER_TCR2_CNT_SYNC_LEN) - 1) << TIMER_TCR2_CNT_SYNC_POS)) - -/* 0xB8 : Timer3 Counter Sync Value */ -#define TIMER_TCVSYN3_OFFSET (0xB8) -#define TIMER_TCR3_CNT_SYNC TIMER_TCR3_CNT_SYNC -#define TIMER_TCR3_CNT_SYNC_POS (0U) -#define TIMER_TCR3_CNT_SYNC_LEN (32U) -#define TIMER_TCR3_CNT_SYNC_MSK (((1U << TIMER_TCR3_CNT_SYNC_LEN) - 1) << TIMER_TCR3_CNT_SYNC_POS) -#define TIMER_TCR3_CNT_SYNC_UMSK (~(((1U << TIMER_TCR3_CNT_SYNC_LEN) - 1) << TIMER_TCR3_CNT_SYNC_POS)) - -/* 0xBC : Timer Division */ -#define TIMER_TCDR_OFFSET (0xBC) -#define TIMER_TCDR2 TIMER_TCDR2 -#define TIMER_TCDR2_POS (8U) -#define TIMER_TCDR2_LEN (8U) -#define TIMER_TCDR2_MSK (((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS) -#define TIMER_TCDR2_UMSK (~(((1U << TIMER_TCDR2_LEN) - 1) << TIMER_TCDR2_POS)) -#define TIMER_TCDR3 TIMER_TCDR3 -#define TIMER_TCDR3_POS (16U) -#define TIMER_TCDR3_LEN (8U) -#define TIMER_TCDR3_MSK (((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS) -#define TIMER_TCDR3_UMSK (~(((1U << TIMER_TCDR3_LEN) - 1) << TIMER_TCDR3_POS)) -#define TIMER_WCDR TIMER_WCDR -#define TIMER_WCDR_POS (24U) -#define TIMER_WCDR_LEN (8U) -#define TIMER_WCDR_MSK (((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS) -#define TIMER_WCDR_UMSK (~(((1U << TIMER_WCDR_LEN) - 1) << TIMER_WCDR_POS)) - -/* 0xC0 : GPIO Mode */ -#define TIMER_GPIO_OFFSET (0xC0) -#define TIMER2_GPIO_EN TIMER2_GPIO_EN -#define TIMER2_GPIO_EN_POS (1U) -#define TIMER2_GPIO_EN_LEN (1U) -#define TIMER2_GPIO_EN_MSK (((1U << TIMER2_GPIO_EN_LEN) - 1) << TIMER2_GPIO_EN_POS) -#define TIMER2_GPIO_EN_UMSK (~(((1U << TIMER2_GPIO_EN_LEN) - 1) << TIMER2_GPIO_EN_POS)) -#define TIMER2_GPIO_INV TIMER2_GPIO_INV -#define TIMER2_GPIO_INV_POS (5U) -#define TIMER2_GPIO_INV_LEN (1U) -#define TIMER2_GPIO_INV_MSK (((1U << TIMER2_GPIO_INV_LEN) - 1) << TIMER2_GPIO_INV_POS) -#define TIMER2_GPIO_INV_UMSK (~(((1U << TIMER2_GPIO_INV_LEN) - 1) << TIMER2_GPIO_INV_POS)) -#define TIMER3_GPIO_INV TIMER3_GPIO_INV -#define TIMER3_GPIO_INV_POS (6U) -#define TIMER3_GPIO_INV_LEN (1U) -#define TIMER3_GPIO_INV_MSK (((1U << TIMER3_GPIO_INV_LEN) - 1) << TIMER3_GPIO_INV_POS) -#define TIMER3_GPIO_INV_UMSK (~(((1U << TIMER3_GPIO_INV_LEN) - 1) << TIMER3_GPIO_INV_POS)) -#define TIMER_WDT_GPIO_INV TIMER_WDT_GPIO_INV -#define TIMER_WDT_GPIO_INV_POS (7U) -#define TIMER_WDT_GPIO_INV_LEN (1U) -#define TIMER_WDT_GPIO_INV_MSK (((1U << TIMER_WDT_GPIO_INV_LEN) - 1) << TIMER_WDT_GPIO_INV_POS) -#define TIMER_WDT_GPIO_INV_UMSK (~(((1U << TIMER_WDT_GPIO_INV_LEN) - 1) << TIMER_WDT_GPIO_INV_POS)) -#define TIMER_GPIO_LAT_OK TIMER_GPIO_LAT_OK -#define TIMER_GPIO_LAT_OK_POS (31U) -#define TIMER_GPIO_LAT_OK_LEN (1U) -#define TIMER_GPIO_LAT_OK_MSK (((1U << TIMER_GPIO_LAT_OK_LEN) - 1) << TIMER_GPIO_LAT_OK_POS) -#define TIMER_GPIO_LAT_OK_UMSK (~(((1U << TIMER_GPIO_LAT_OK_LEN) - 1) << TIMER_GPIO_LAT_OK_POS)) - -/* 0xC4 : GPIO Latch Value1 */ -#define TIMER_GPIO_LAT1_OFFSET (0xC4) -#define TIMER_GPIO_LAT1 TIMER_GPIO_LAT1 -#define TIMER_GPIO_LAT1_POS (0U) -#define TIMER_GPIO_LAT1_LEN (32U) -#define TIMER_GPIO_LAT1_MSK (((1U << TIMER_GPIO_LAT1_LEN) - 1) << TIMER_GPIO_LAT1_POS) -#define TIMER_GPIO_LAT1_UMSK (~(((1U << TIMER_GPIO_LAT1_LEN) - 1) << TIMER_GPIO_LAT1_POS)) - -/* 0xC8 : GPIO Latch Value2 */ -#define TIMER_GPIO_LAT2_OFFSET (0xC8) -#define TIMER_GPIO_LAT2 TIMER_GPIO_LAT2 -#define TIMER_GPIO_LAT2_POS (0U) -#define TIMER_GPIO_LAT2_LEN (32U) -#define TIMER_GPIO_LAT2_MSK (((1U << TIMER_GPIO_LAT2_LEN) - 1) << TIMER_GPIO_LAT2_POS) -#define TIMER_GPIO_LAT2_UMSK (~(((1U << TIMER_GPIO_LAT2_LEN) - 1) << TIMER_GPIO_LAT2_POS)) - -/* 0xCC : Timer Division Force */ -#define TIMER_TCDR_FORCE_OFFSET (0xCC) -#define TIMER_TCDR2_FORCE TIMER_TCDR2_FORCE -#define TIMER_TCDR2_FORCE_POS (1U) -#define TIMER_TCDR2_FORCE_LEN (1U) -#define TIMER_TCDR2_FORCE_MSK (((1U << TIMER_TCDR2_FORCE_LEN) - 1) << TIMER_TCDR2_FORCE_POS) -#define TIMER_TCDR2_FORCE_UMSK (~(((1U << TIMER_TCDR2_FORCE_LEN) - 1) << TIMER_TCDR2_FORCE_POS)) -#define TIMER_TCDR3_FORCE TIMER_TCDR3_FORCE -#define TIMER_TCDR3_FORCE_POS (2U) -#define TIMER_TCDR3_FORCE_LEN (1U) -#define TIMER_TCDR3_FORCE_MSK (((1U << TIMER_TCDR3_FORCE_LEN) - 1) << TIMER_TCDR3_FORCE_POS) -#define TIMER_TCDR3_FORCE_UMSK (~(((1U << TIMER_TCDR3_FORCE_LEN) - 1) << TIMER_TCDR3_FORCE_POS)) -#define TIMER_WCDR_FORCE TIMER_WCDR_FORCE -#define TIMER_WCDR_FORCE_POS (4U) -#define TIMER_WCDR_FORCE_LEN (1U) -#define TIMER_WCDR_FORCE_MSK (((1U << TIMER_WCDR_FORCE_LEN) - 1) << TIMER_WCDR_FORCE_POS) -#define TIMER_WCDR_FORCE_UMSK (~(((1U << TIMER_WCDR_FORCE_LEN) - 1) << TIMER_WCDR_FORCE_POS)) - -struct timer_reg { - /* 0x0 : Timer Clock Source */ - union { - struct { - uint32_t cs_2 : 4; /* [ 3: 0], r/w, 0x5 */ - uint32_t cs_3 : 4; /* [ 7: 4], r/w, 0x5 */ - uint32_t cs_wdt : 4; /* [11: 8], r/w, 0x1 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t tmr_rsv : 8; /* [23:16], rsvd, 0x0 */ - uint32_t ID : 8; /* [31:24], r, 0xa5 */ - } BF; - uint32_t WORD; - } TCCR; - - /* 0x4 reserved */ - uint8_t RESERVED0x4[12]; - - /* 0x10 : Timer2 Match Value 0 */ - union { - struct { - uint32_t tmr2_0 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR2_0; - - /* 0x14 : Timer2 Match Value 1 */ - union { - struct { - uint32_t tmr2_1 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR2_1; - - /* 0x18 : Timer2 Match Value 2 */ - union { - struct { - uint32_t tmr2_2 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR2_2; - - /* 0x1C : Timer3 Match Value 0 */ - union { - struct { - uint32_t tmr3_0 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR3_0; - - /* 0x20 : Timer3 Match Value 1 */ - union { - struct { - uint32_t tmr3_1 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR3_1; - - /* 0x24 : Timer3 Match Value 2 */ - union { - struct { - uint32_t tmr3_2 : 32; /* [31: 0], r/w, 0xffffffff */ - } BF; - uint32_t WORD; - } TMR3_2; - - /* 0x28 reserved */ - uint8_t RESERVED0x28[4]; - - /* 0x2C : Timer2 Counter Value */ - union { - struct { - uint32_t tcr2_cnt : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCR2; - - /* 0x30 : Timer3 Counter Value */ - union { - struct { - uint32_t tcr3_cnt : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCR3; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[4]; - - /* 0x38 : Timer2 Match Status */ - union { - struct { - uint32_t tsr2_0 : 1; /* [ 0], r, 0x0 */ - uint32_t tsr2_1 : 1; /* [ 1], r, 0x0 */ - uint32_t tsr2_2 : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TSR2; - - /* 0x3C : Timer3 Match Status */ - union { - struct { - uint32_t tsr3_0 : 1; /* [ 0], r, 0x0 */ - uint32_t tsr3_1 : 1; /* [ 1], r, 0x0 */ - uint32_t tsr3_2 : 1; /* [ 2], r, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TSR3; - - /* 0x40 reserved */ - uint8_t RESERVED0x40[4]; - - /* 0x44 : Timer2 Match Interrupt Enable */ - union { - struct { - uint32_t tier2_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tier2_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tier2_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TIER2; - - /* 0x48 : Timer3 Match Interrupt Enable */ - union { - struct { - uint32_t tier3_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tier3_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tier3_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TIER3; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : Timer2 Pre-Load Value */ - union { - struct { - uint32_t tplvr2 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } TPLVR2; - - /* 0x54 : Timer3 Pre-Load Value */ - union { - struct { - uint32_t tplvr3 : 32; /* [31: 0], r/w, 0x0 */ - } BF; - uint32_t WORD; - } TPLVR3; - - /* 0x58 reserved */ - uint8_t RESERVED0x58[4]; - - /* 0x5C : Timer2 Pre-Load Control */ - union { - struct { - uint32_t tplcr2 : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TPLCR2; - - /* 0x60 : Timer3 Pre-Load Control */ - union { - struct { - uint32_t tplcr3 : 2; /* [ 1: 0], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TPLCR3; - - /* 0x64 : Watch-dog reset/interrupt Mode */ - union { - struct { - uint32_t we : 1; /* [ 0], r/w, 0x0 */ - uint32_t wrie : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WMER; - - /* 0x68 : Watch-dog Match Value */ - union { - struct { - uint32_t wmr : 16; /* [15: 0], r/w, 0xffff */ - uint32_t wdt_align : 1; /* [ 16], r/w, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WMR; - - /* 0x6C : Watch-dog Counter Value */ - union { - struct { - uint32_t wdt_cnt : 16; /* [15: 0], r, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WVR; - - /* 0x70 : Watch-dog Reset Status */ - union { - struct { - uint32_t wts : 1; /* [ 0], w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WSR; - - /* 0x74 reserved */ - uint8_t RESERVED0x74[4]; - - /* 0x78 : Timer2 Interrupt Clear */ - union { - struct { - uint32_t tclr2_0 : 1; /* [ 0], w, 0x0 */ - uint32_t tclr2_1 : 1; /* [ 1], w, 0x0 */ - uint32_t tclr2_2 : 1; /* [ 2], w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TICR2; - - /* 0x7C : Timer3 Interrupt Clear */ - union { - struct { - uint32_t tclr3_0 : 1; /* [ 0], w, 0x0 */ - uint32_t tclr3_1 : 1; /* [ 1], w, 0x0 */ - uint32_t tclr3_2 : 1; /* [ 2], w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TICR3; - - /* 0x80 : WDT Interrupt Clear */ - union { - struct { - uint32_t wiclr : 1; /* [ 0], w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WICR; - - /* 0x84 : Timer Counter Enable/Clear */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t timer2_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t timer3_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */ - uint32_t tcr2_cnt_clr : 1; /* [ 5], r/w, 0x0 */ - uint32_t tcr3_cnt_clr : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TCER; - - /* 0x88 : Timer Counter Mode */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t timer2_mode : 1; /* [ 1], r/w, 0x0 */ - uint32_t timer3_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_4 : 2; /* [ 4: 3], rsvd, 0x0 */ - uint32_t timer2_align : 1; /* [ 5], r/w, 0x0 */ - uint32_t timer3_align : 1; /* [ 6], r/w, 0x0 */ - uint32_t reserved_7_31 : 25; /* [31: 7], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TCMR; - - /* 0x8c reserved */ - uint8_t RESERVED0x8c[4]; - - /* 0x90 : Timer2 Match Interrupt Mode */ - union { - struct { - uint32_t tilr2_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tilr2_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tilr2_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TILR2; - - /* 0x94 : Timer3 Match Interrupt Mode */ - union { - struct { - uint32_t tilr3_0 : 1; /* [ 0], r/w, 0x0 */ - uint32_t tilr3_1 : 1; /* [ 1], r/w, 0x0 */ - uint32_t tilr3_2 : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TILR3; - - /* 0x98 : WDT Counter Reset */ - union { - struct { - uint32_t wcr : 1; /* [ 0], w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WCR; - - /* 0x9C : WDT Access Key1 */ - union { - struct { - uint32_t wfar : 16; /* [15: 0], w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WFAR; - - /* 0xA0 : WDT Access Key2 */ - union { - struct { - uint32_t wsar : 16; /* [15: 0], w, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } WSAR; - - /* 0xa4 reserved */ - uint8_t RESERVED0xa4[4]; - - /* 0xA8 : Timer2 Counter Latch Value */ - union { - struct { - uint32_t tcr2_cnt_lat : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVWR2; - - /* 0xAC : Timer3 Counter Latch Value */ - union { - struct { - uint32_t tcr3_cnt_lat : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVWR3; - - /* 0xb0 reserved */ - uint8_t RESERVED0xb0[4]; - - /* 0xB4 : Timer2 Counter Sync Value */ - union { - struct { - uint32_t tcr2_cnt_sync : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVSYN2; - - /* 0xB8 : Timer3 Counter Sync Value */ - union { - struct { - uint32_t tcr3_cnt_sync : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } TCVSYN3; - - /* 0xBC : Timer Division */ - union { - struct { - uint32_t reserved_0_7 : 8; /* [ 7: 0], rsvd, 0x0 */ - uint32_t tcdr2 : 8; /* [15: 8], r/w, 0x0 */ - uint32_t tcdr3 : 8; /* [23:16], r/w, 0x0 */ - uint32_t wcdr : 8; /* [31:24], r/w, 0x0 */ - } BF; - uint32_t WORD; - } TCDR; - - /* 0xC0 : GPIO Mode */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t timer2_gpio_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2_4 : 3; /* [ 4: 2], rsvd, 0x0 */ - uint32_t timer2_gpio_inv : 1; /* [ 5], r/w, 0x0 */ - uint32_t timer3_gpio_inv : 1; /* [ 6], r/w, 0x0 */ - uint32_t wdt_gpio_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t reserved_8_30 : 23; /* [30: 8], rsvd, 0x0 */ - uint32_t gpio_lat_ok : 1; /* [ 31], r, 0x0 */ - } BF; - uint32_t WORD; - } GPIO; - - /* 0xC4 : GPIO Latch Value1 */ - union { - struct { - uint32_t gpio_lat1 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } GPIO_LAT1; - - /* 0xC8 : GPIO Latch Value2 */ - union { - struct { - uint32_t gpio_lat2 : 32; /* [31: 0], r, 0x0 */ - } BF; - uint32_t WORD; - } GPIO_LAT2; - - /* 0xCC : Timer Division Force */ - union { - struct { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t tcdr2_force : 1; /* [ 1], r/w, 0x0 */ - uint32_t tcdr3_force : 1; /* [ 2], r/w, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t wcdr_force : 1; /* [ 4], r/w, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } TCDR_FORCE; -}; - -typedef volatile struct timer_reg timer_reg_t; - -#endif /* __TIMER_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/uart_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/uart_reg.h deleted file mode 100644 index 81c34e6234..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/uart_reg.h +++ /dev/null @@ -1,978 +0,0 @@ -/** - ****************************************************************************** - * @file uart_reg.h - * @version V1.0 - * @date 2021-07-08 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __UART_REG_H__ -#define __UART_REG_H__ - -#include "bl808.h" - -/* 0x0 : utx_config */ -#define UART_UTX_CONFIG_OFFSET (0x0) -#define UART_CR_UTX_EN UART_CR_UTX_EN -#define UART_CR_UTX_EN_POS (0U) -#define UART_CR_UTX_EN_LEN (1U) -#define UART_CR_UTX_EN_MSK (((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS) -#define UART_CR_UTX_EN_UMSK (~(((1U << UART_CR_UTX_EN_LEN) - 1) << UART_CR_UTX_EN_POS)) -#define UART_CR_UTX_CTS_EN UART_CR_UTX_CTS_EN -#define UART_CR_UTX_CTS_EN_POS (1U) -#define UART_CR_UTX_CTS_EN_LEN (1U) -#define UART_CR_UTX_CTS_EN_MSK (((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS) -#define UART_CR_UTX_CTS_EN_UMSK (~(((1U << UART_CR_UTX_CTS_EN_LEN) - 1) << UART_CR_UTX_CTS_EN_POS)) -#define UART_CR_UTX_FRM_EN UART_CR_UTX_FRM_EN -#define UART_CR_UTX_FRM_EN_POS (2U) -#define UART_CR_UTX_FRM_EN_LEN (1U) -#define UART_CR_UTX_FRM_EN_MSK (((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS) -#define UART_CR_UTX_FRM_EN_UMSK (~(((1U << UART_CR_UTX_FRM_EN_LEN) - 1) << UART_CR_UTX_FRM_EN_POS)) -#define UART_CR_UTX_LIN_EN UART_CR_UTX_LIN_EN -#define UART_CR_UTX_LIN_EN_POS (3U) -#define UART_CR_UTX_LIN_EN_LEN (1U) -#define UART_CR_UTX_LIN_EN_MSK (((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS) -#define UART_CR_UTX_LIN_EN_UMSK (~(((1U << UART_CR_UTX_LIN_EN_LEN) - 1) << UART_CR_UTX_LIN_EN_POS)) -#define UART_CR_UTX_PRT_EN UART_CR_UTX_PRT_EN -#define UART_CR_UTX_PRT_EN_POS (4U) -#define UART_CR_UTX_PRT_EN_LEN (1U) -#define UART_CR_UTX_PRT_EN_MSK (((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS) -#define UART_CR_UTX_PRT_EN_UMSK (~(((1U << UART_CR_UTX_PRT_EN_LEN) - 1) << UART_CR_UTX_PRT_EN_POS)) -#define UART_CR_UTX_PRT_SEL UART_CR_UTX_PRT_SEL -#define UART_CR_UTX_PRT_SEL_POS (5U) -#define UART_CR_UTX_PRT_SEL_LEN (1U) -#define UART_CR_UTX_PRT_SEL_MSK (((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS) -#define UART_CR_UTX_PRT_SEL_UMSK (~(((1U << UART_CR_UTX_PRT_SEL_LEN) - 1) << UART_CR_UTX_PRT_SEL_POS)) -#define UART_CR_UTX_IR_EN UART_CR_UTX_IR_EN -#define UART_CR_UTX_IR_EN_POS (6U) -#define UART_CR_UTX_IR_EN_LEN (1U) -#define UART_CR_UTX_IR_EN_MSK (((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS) -#define UART_CR_UTX_IR_EN_UMSK (~(((1U << UART_CR_UTX_IR_EN_LEN) - 1) << UART_CR_UTX_IR_EN_POS)) -#define UART_CR_UTX_IR_INV UART_CR_UTX_IR_INV -#define UART_CR_UTX_IR_INV_POS (7U) -#define UART_CR_UTX_IR_INV_LEN (1U) -#define UART_CR_UTX_IR_INV_MSK (((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS) -#define UART_CR_UTX_IR_INV_UMSK (~(((1U << UART_CR_UTX_IR_INV_LEN) - 1) << UART_CR_UTX_IR_INV_POS)) -#define UART_CR_UTX_BIT_CNT_D UART_CR_UTX_BIT_CNT_D -#define UART_CR_UTX_BIT_CNT_D_POS (8U) -#define UART_CR_UTX_BIT_CNT_D_LEN (3U) -#define UART_CR_UTX_BIT_CNT_D_MSK (((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS) -#define UART_CR_UTX_BIT_CNT_D_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_D_LEN) - 1) << UART_CR_UTX_BIT_CNT_D_POS)) -#define UART_CR_UTX_BIT_CNT_P UART_CR_UTX_BIT_CNT_P -#define UART_CR_UTX_BIT_CNT_P_POS (11U) -#define UART_CR_UTX_BIT_CNT_P_LEN (2U) -#define UART_CR_UTX_BIT_CNT_P_MSK (((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS) -#define UART_CR_UTX_BIT_CNT_P_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_P_LEN) - 1) << UART_CR_UTX_BIT_CNT_P_POS)) -#define UART_CR_UTX_BIT_CNT_B UART_CR_UTX_BIT_CNT_B -#define UART_CR_UTX_BIT_CNT_B_POS (13U) -#define UART_CR_UTX_BIT_CNT_B_LEN (3U) -#define UART_CR_UTX_BIT_CNT_B_MSK (((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS) -#define UART_CR_UTX_BIT_CNT_B_UMSK (~(((1U << UART_CR_UTX_BIT_CNT_B_LEN) - 1) << UART_CR_UTX_BIT_CNT_B_POS)) -#define UART_CR_UTX_LEN UART_CR_UTX_LEN -#define UART_CR_UTX_LEN_POS (16U) -#define UART_CR_UTX_LEN_LEN (16U) -#define UART_CR_UTX_LEN_MSK (((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS) -#define UART_CR_UTX_LEN_UMSK (~(((1U << UART_CR_UTX_LEN_LEN) - 1) << UART_CR_UTX_LEN_POS)) - -/* 0x4 : urx_config */ -#define UART_URX_CONFIG_OFFSET (0x4) -#define UART_CR_URX_EN UART_CR_URX_EN -#define UART_CR_URX_EN_POS (0U) -#define UART_CR_URX_EN_LEN (1U) -#define UART_CR_URX_EN_MSK (((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS) -#define UART_CR_URX_EN_UMSK (~(((1U << UART_CR_URX_EN_LEN) - 1) << UART_CR_URX_EN_POS)) -#define UART_CR_URX_ABR_EN UART_CR_URX_ABR_EN -#define UART_CR_URX_ABR_EN_POS (1U) -#define UART_CR_URX_ABR_EN_LEN (1U) -#define UART_CR_URX_ABR_EN_MSK (((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS) -#define UART_CR_URX_ABR_EN_UMSK (~(((1U << UART_CR_URX_ABR_EN_LEN) - 1) << UART_CR_URX_ABR_EN_POS)) -#define UART_CR_URX_LIN_EN UART_CR_URX_LIN_EN -#define UART_CR_URX_LIN_EN_POS (3U) -#define UART_CR_URX_LIN_EN_LEN (1U) -#define UART_CR_URX_LIN_EN_MSK (((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS) -#define UART_CR_URX_LIN_EN_UMSK (~(((1U << UART_CR_URX_LIN_EN_LEN) - 1) << UART_CR_URX_LIN_EN_POS)) -#define UART_CR_URX_PRT_EN UART_CR_URX_PRT_EN -#define UART_CR_URX_PRT_EN_POS (4U) -#define UART_CR_URX_PRT_EN_LEN (1U) -#define UART_CR_URX_PRT_EN_MSK (((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS) -#define UART_CR_URX_PRT_EN_UMSK (~(((1U << UART_CR_URX_PRT_EN_LEN) - 1) << UART_CR_URX_PRT_EN_POS)) -#define UART_CR_URX_PRT_SEL UART_CR_URX_PRT_SEL -#define UART_CR_URX_PRT_SEL_POS (5U) -#define UART_CR_URX_PRT_SEL_LEN (1U) -#define UART_CR_URX_PRT_SEL_MSK (((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS) -#define UART_CR_URX_PRT_SEL_UMSK (~(((1U << UART_CR_URX_PRT_SEL_LEN) - 1) << UART_CR_URX_PRT_SEL_POS)) -#define UART_CR_URX_IR_EN UART_CR_URX_IR_EN -#define UART_CR_URX_IR_EN_POS (6U) -#define UART_CR_URX_IR_EN_LEN (1U) -#define UART_CR_URX_IR_EN_MSK (((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS) -#define UART_CR_URX_IR_EN_UMSK (~(((1U << UART_CR_URX_IR_EN_LEN) - 1) << UART_CR_URX_IR_EN_POS)) -#define UART_CR_URX_IR_INV UART_CR_URX_IR_INV -#define UART_CR_URX_IR_INV_POS (7U) -#define UART_CR_URX_IR_INV_LEN (1U) -#define UART_CR_URX_IR_INV_MSK (((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS) -#define UART_CR_URX_IR_INV_UMSK (~(((1U << UART_CR_URX_IR_INV_LEN) - 1) << UART_CR_URX_IR_INV_POS)) -#define UART_CR_URX_BIT_CNT_D UART_CR_URX_BIT_CNT_D -#define UART_CR_URX_BIT_CNT_D_POS (8U) -#define UART_CR_URX_BIT_CNT_D_LEN (3U) -#define UART_CR_URX_BIT_CNT_D_MSK (((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS) -#define UART_CR_URX_BIT_CNT_D_UMSK (~(((1U << UART_CR_URX_BIT_CNT_D_LEN) - 1) << UART_CR_URX_BIT_CNT_D_POS)) -#define UART_CR_URX_DEG_EN UART_CR_URX_DEG_EN -#define UART_CR_URX_DEG_EN_POS (11U) -#define UART_CR_URX_DEG_EN_LEN (1U) -#define UART_CR_URX_DEG_EN_MSK (((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS) -#define UART_CR_URX_DEG_EN_UMSK (~(((1U << UART_CR_URX_DEG_EN_LEN) - 1) << UART_CR_URX_DEG_EN_POS)) -#define UART_CR_URX_DEG_CNT UART_CR_URX_DEG_CNT -#define UART_CR_URX_DEG_CNT_POS (12U) -#define UART_CR_URX_DEG_CNT_LEN (4U) -#define UART_CR_URX_DEG_CNT_MSK (((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS) -#define UART_CR_URX_DEG_CNT_UMSK (~(((1U << UART_CR_URX_DEG_CNT_LEN) - 1) << UART_CR_URX_DEG_CNT_POS)) -#define UART_CR_URX_LEN UART_CR_URX_LEN -#define UART_CR_URX_LEN_POS (16U) -#define UART_CR_URX_LEN_LEN (16U) -#define UART_CR_URX_LEN_MSK (((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS) -#define UART_CR_URX_LEN_UMSK (~(((1U << UART_CR_URX_LEN_LEN) - 1) << UART_CR_URX_LEN_POS)) - -/* 0x8 : uart_bit_prd */ -#define UART_BIT_PRD_OFFSET (0x8) -#define UART_CR_UTX_BIT_PRD UART_CR_UTX_BIT_PRD -#define UART_CR_UTX_BIT_PRD_POS (0U) -#define UART_CR_UTX_BIT_PRD_LEN (16U) -#define UART_CR_UTX_BIT_PRD_MSK (((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS) -#define UART_CR_UTX_BIT_PRD_UMSK (~(((1U << UART_CR_UTX_BIT_PRD_LEN) - 1) << UART_CR_UTX_BIT_PRD_POS)) -#define UART_CR_URX_BIT_PRD UART_CR_URX_BIT_PRD -#define UART_CR_URX_BIT_PRD_POS (16U) -#define UART_CR_URX_BIT_PRD_LEN (16U) -#define UART_CR_URX_BIT_PRD_MSK (((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS) -#define UART_CR_URX_BIT_PRD_UMSK (~(((1U << UART_CR_URX_BIT_PRD_LEN) - 1) << UART_CR_URX_BIT_PRD_POS)) - -/* 0xC : data_config */ -#define UART_DATA_CONFIG_OFFSET (0xC) -#define UART_CR_UART_BIT_INV UART_CR_UART_BIT_INV -#define UART_CR_UART_BIT_INV_POS (0U) -#define UART_CR_UART_BIT_INV_LEN (1U) -#define UART_CR_UART_BIT_INV_MSK (((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS) -#define UART_CR_UART_BIT_INV_UMSK (~(((1U << UART_CR_UART_BIT_INV_LEN) - 1) << UART_CR_UART_BIT_INV_POS)) - -/* 0x10 : utx_ir_position */ -#define UART_UTX_IR_POSITION_OFFSET (0x10) -#define UART_CR_UTX_IR_POS_S UART_CR_UTX_IR_POS_S -#define UART_CR_UTX_IR_POS_S_POS (0U) -#define UART_CR_UTX_IR_POS_S_LEN (16U) -#define UART_CR_UTX_IR_POS_S_MSK (((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS) -#define UART_CR_UTX_IR_POS_S_UMSK (~(((1U << UART_CR_UTX_IR_POS_S_LEN) - 1) << UART_CR_UTX_IR_POS_S_POS)) -#define UART_CR_UTX_IR_POS_P UART_CR_UTX_IR_POS_P -#define UART_CR_UTX_IR_POS_P_POS (16U) -#define UART_CR_UTX_IR_POS_P_LEN (16U) -#define UART_CR_UTX_IR_POS_P_MSK (((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS) -#define UART_CR_UTX_IR_POS_P_UMSK (~(((1U << UART_CR_UTX_IR_POS_P_LEN) - 1) << UART_CR_UTX_IR_POS_P_POS)) - -/* 0x14 : urx_ir_position */ -#define UART_URX_IR_POSITION_OFFSET (0x14) -#define UART_CR_URX_IR_POS_S UART_CR_URX_IR_POS_S -#define UART_CR_URX_IR_POS_S_POS (0U) -#define UART_CR_URX_IR_POS_S_LEN (16U) -#define UART_CR_URX_IR_POS_S_MSK (((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS) -#define UART_CR_URX_IR_POS_S_UMSK (~(((1U << UART_CR_URX_IR_POS_S_LEN) - 1) << UART_CR_URX_IR_POS_S_POS)) - -/* 0x18 : urx_rto_timer */ -#define UART_URX_RTO_TIMER_OFFSET (0x18) -#define UART_CR_URX_RTO_VALUE UART_CR_URX_RTO_VALUE -#define UART_CR_URX_RTO_VALUE_POS (0U) -#define UART_CR_URX_RTO_VALUE_LEN (8U) -#define UART_CR_URX_RTO_VALUE_MSK (((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS) -#define UART_CR_URX_RTO_VALUE_UMSK (~(((1U << UART_CR_URX_RTO_VALUE_LEN) - 1) << UART_CR_URX_RTO_VALUE_POS)) - -/* 0x1C : uart_sw_mode */ -#define UART_SW_MODE_OFFSET (0x1C) -#define UART_CR_UTX_TXD_SW_MODE UART_CR_UTX_TXD_SW_MODE -#define UART_CR_UTX_TXD_SW_MODE_POS (0U) -#define UART_CR_UTX_TXD_SW_MODE_LEN (1U) -#define UART_CR_UTX_TXD_SW_MODE_MSK (((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS) -#define UART_CR_UTX_TXD_SW_MODE_UMSK (~(((1U << UART_CR_UTX_TXD_SW_MODE_LEN) - 1) << UART_CR_UTX_TXD_SW_MODE_POS)) -#define UART_CR_UTX_TXD_SW_VAL UART_CR_UTX_TXD_SW_VAL -#define UART_CR_UTX_TXD_SW_VAL_POS (1U) -#define UART_CR_UTX_TXD_SW_VAL_LEN (1U) -#define UART_CR_UTX_TXD_SW_VAL_MSK (((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS) -#define UART_CR_UTX_TXD_SW_VAL_UMSK (~(((1U << UART_CR_UTX_TXD_SW_VAL_LEN) - 1) << UART_CR_UTX_TXD_SW_VAL_POS)) -#define UART_CR_URX_RTS_SW_MODE UART_CR_URX_RTS_SW_MODE -#define UART_CR_URX_RTS_SW_MODE_POS (2U) -#define UART_CR_URX_RTS_SW_MODE_LEN (1U) -#define UART_CR_URX_RTS_SW_MODE_MSK (((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS) -#define UART_CR_URX_RTS_SW_MODE_UMSK (~(((1U << UART_CR_URX_RTS_SW_MODE_LEN) - 1) << UART_CR_URX_RTS_SW_MODE_POS)) -#define UART_CR_URX_RTS_SW_VAL UART_CR_URX_RTS_SW_VAL -#define UART_CR_URX_RTS_SW_VAL_POS (3U) -#define UART_CR_URX_RTS_SW_VAL_LEN (1U) -#define UART_CR_URX_RTS_SW_VAL_MSK (((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS) -#define UART_CR_URX_RTS_SW_VAL_UMSK (~(((1U << UART_CR_URX_RTS_SW_VAL_LEN) - 1) << UART_CR_URX_RTS_SW_VAL_POS)) - -/* 0x20 : UART interrupt status */ -#define UART_INT_STS_OFFSET (0x20) -#define UART_UTX_END_INT UART_UTX_END_INT -#define UART_UTX_END_INT_POS (0U) -#define UART_UTX_END_INT_LEN (1U) -#define UART_UTX_END_INT_MSK (((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS) -#define UART_UTX_END_INT_UMSK (~(((1U << UART_UTX_END_INT_LEN) - 1) << UART_UTX_END_INT_POS)) -#define UART_URX_END_INT UART_URX_END_INT -#define UART_URX_END_INT_POS (1U) -#define UART_URX_END_INT_LEN (1U) -#define UART_URX_END_INT_MSK (((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS) -#define UART_URX_END_INT_UMSK (~(((1U << UART_URX_END_INT_LEN) - 1) << UART_URX_END_INT_POS)) -#define UART_UTX_FRDY_INT UART_UTX_FRDY_INT -#define UART_UTX_FRDY_INT_POS (2U) -#define UART_UTX_FRDY_INT_LEN (1U) -#define UART_UTX_FRDY_INT_MSK (((1U << UART_UTX_FRDY_INT_LEN) - 1) << UART_UTX_FRDY_INT_POS) -#define UART_UTX_FRDY_INT_UMSK (~(((1U << UART_UTX_FRDY_INT_LEN) - 1) << UART_UTX_FRDY_INT_POS)) -#define UART_URX_FRDY_INT UART_URX_FRDY_INT -#define UART_URX_FRDY_INT_POS (3U) -#define UART_URX_FRDY_INT_LEN (1U) -#define UART_URX_FRDY_INT_MSK (((1U << UART_URX_FRDY_INT_LEN) - 1) << UART_URX_FRDY_INT_POS) -#define UART_URX_FRDY_INT_UMSK (~(((1U << UART_URX_FRDY_INT_LEN) - 1) << UART_URX_FRDY_INT_POS)) -#define UART_URX_RTO_INT UART_URX_RTO_INT -#define UART_URX_RTO_INT_POS (4U) -#define UART_URX_RTO_INT_LEN (1U) -#define UART_URX_RTO_INT_MSK (((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS) -#define UART_URX_RTO_INT_UMSK (~(((1U << UART_URX_RTO_INT_LEN) - 1) << UART_URX_RTO_INT_POS)) -#define UART_URX_PCE_INT UART_URX_PCE_INT -#define UART_URX_PCE_INT_POS (5U) -#define UART_URX_PCE_INT_LEN (1U) -#define UART_URX_PCE_INT_MSK (((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS) -#define UART_URX_PCE_INT_UMSK (~(((1U << UART_URX_PCE_INT_LEN) - 1) << UART_URX_PCE_INT_POS)) -#define UART_UTX_FER_INT UART_UTX_FER_INT -#define UART_UTX_FER_INT_POS (6U) -#define UART_UTX_FER_INT_LEN (1U) -#define UART_UTX_FER_INT_MSK (((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS) -#define UART_UTX_FER_INT_UMSK (~(((1U << UART_UTX_FER_INT_LEN) - 1) << UART_UTX_FER_INT_POS)) -#define UART_URX_FER_INT UART_URX_FER_INT -#define UART_URX_FER_INT_POS (7U) -#define UART_URX_FER_INT_LEN (1U) -#define UART_URX_FER_INT_MSK (((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS) -#define UART_URX_FER_INT_UMSK (~(((1U << UART_URX_FER_INT_LEN) - 1) << UART_URX_FER_INT_POS)) -#define UART_URX_LSE_INT UART_URX_LSE_INT -#define UART_URX_LSE_INT_POS (8U) -#define UART_URX_LSE_INT_LEN (1U) -#define UART_URX_LSE_INT_MSK (((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS) -#define UART_URX_LSE_INT_UMSK (~(((1U << UART_URX_LSE_INT_LEN) - 1) << UART_URX_LSE_INT_POS)) -#define UART_URX_BCR_INT UART_URX_BCR_INT -#define UART_URX_BCR_INT_POS (9U) -#define UART_URX_BCR_INT_LEN (1U) -#define UART_URX_BCR_INT_MSK (((1U << UART_URX_BCR_INT_LEN) - 1) << UART_URX_BCR_INT_POS) -#define UART_URX_BCR_INT_UMSK (~(((1U << UART_URX_BCR_INT_LEN) - 1) << UART_URX_BCR_INT_POS)) -#define UART_URX_ADS_INT UART_URX_ADS_INT -#define UART_URX_ADS_INT_POS (10U) -#define UART_URX_ADS_INT_LEN (1U) -#define UART_URX_ADS_INT_MSK (((1U << UART_URX_ADS_INT_LEN) - 1) << UART_URX_ADS_INT_POS) -#define UART_URX_ADS_INT_UMSK (~(((1U << UART_URX_ADS_INT_LEN) - 1) << UART_URX_ADS_INT_POS)) -#define UART_URX_AD5_INT UART_URX_AD5_INT -#define UART_URX_AD5_INT_POS (11U) -#define UART_URX_AD5_INT_LEN (1U) -#define UART_URX_AD5_INT_MSK (((1U << UART_URX_AD5_INT_LEN) - 1) << UART_URX_AD5_INT_POS) -#define UART_URX_AD5_INT_UMSK (~(((1U << UART_URX_AD5_INT_LEN) - 1) << UART_URX_AD5_INT_POS)) - -/* 0x24 : UART interrupt mask */ -#define UART_INT_MASK_OFFSET (0x24) -#define UART_CR_UTX_END_MASK UART_CR_UTX_END_MASK -#define UART_CR_UTX_END_MASK_POS (0U) -#define UART_CR_UTX_END_MASK_LEN (1U) -#define UART_CR_UTX_END_MASK_MSK (((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS) -#define UART_CR_UTX_END_MASK_UMSK (~(((1U << UART_CR_UTX_END_MASK_LEN) - 1) << UART_CR_UTX_END_MASK_POS)) -#define UART_CR_URX_END_MASK UART_CR_URX_END_MASK -#define UART_CR_URX_END_MASK_POS (1U) -#define UART_CR_URX_END_MASK_LEN (1U) -#define UART_CR_URX_END_MASK_MSK (((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS) -#define UART_CR_URX_END_MASK_UMSK (~(((1U << UART_CR_URX_END_MASK_LEN) - 1) << UART_CR_URX_END_MASK_POS)) -#define UART_CR_UTX_FRDY_MASK UART_CR_UTX_FRDY_MASK -#define UART_CR_UTX_FRDY_MASK_POS (2U) -#define UART_CR_UTX_FRDY_MASK_LEN (1U) -#define UART_CR_UTX_FRDY_MASK_MSK (((1U << UART_CR_UTX_FRDY_MASK_LEN) - 1) << UART_CR_UTX_FRDY_MASK_POS) -#define UART_CR_UTX_FRDY_MASK_UMSK (~(((1U << UART_CR_UTX_FRDY_MASK_LEN) - 1) << UART_CR_UTX_FRDY_MASK_POS)) -#define UART_CR_URX_FRDY_MASK UART_CR_URX_FRDY_MASK -#define UART_CR_URX_FRDY_MASK_POS (3U) -#define UART_CR_URX_FRDY_MASK_LEN (1U) -#define UART_CR_URX_FRDY_MASK_MSK (((1U << UART_CR_URX_FRDY_MASK_LEN) - 1) << UART_CR_URX_FRDY_MASK_POS) -#define UART_CR_URX_FRDY_MASK_UMSK (~(((1U << UART_CR_URX_FRDY_MASK_LEN) - 1) << UART_CR_URX_FRDY_MASK_POS)) -#define UART_CR_URX_RTO_MASK UART_CR_URX_RTO_MASK -#define UART_CR_URX_RTO_MASK_POS (4U) -#define UART_CR_URX_RTO_MASK_LEN (1U) -#define UART_CR_URX_RTO_MASK_MSK (((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS) -#define UART_CR_URX_RTO_MASK_UMSK (~(((1U << UART_CR_URX_RTO_MASK_LEN) - 1) << UART_CR_URX_RTO_MASK_POS)) -#define UART_CR_URX_PCE_MASK UART_CR_URX_PCE_MASK -#define UART_CR_URX_PCE_MASK_POS (5U) -#define UART_CR_URX_PCE_MASK_LEN (1U) -#define UART_CR_URX_PCE_MASK_MSK (((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS) -#define UART_CR_URX_PCE_MASK_UMSK (~(((1U << UART_CR_URX_PCE_MASK_LEN) - 1) << UART_CR_URX_PCE_MASK_POS)) -#define UART_CR_UTX_FER_MASK UART_CR_UTX_FER_MASK -#define UART_CR_UTX_FER_MASK_POS (6U) -#define UART_CR_UTX_FER_MASK_LEN (1U) -#define UART_CR_UTX_FER_MASK_MSK (((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS) -#define UART_CR_UTX_FER_MASK_UMSK (~(((1U << UART_CR_UTX_FER_MASK_LEN) - 1) << UART_CR_UTX_FER_MASK_POS)) -#define UART_CR_URX_FER_MASK UART_CR_URX_FER_MASK -#define UART_CR_URX_FER_MASK_POS (7U) -#define UART_CR_URX_FER_MASK_LEN (1U) -#define UART_CR_URX_FER_MASK_MSK (((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS) -#define UART_CR_URX_FER_MASK_UMSK (~(((1U << UART_CR_URX_FER_MASK_LEN) - 1) << UART_CR_URX_FER_MASK_POS)) -#define UART_CR_URX_LSE_MASK UART_CR_URX_LSE_MASK -#define UART_CR_URX_LSE_MASK_POS (8U) -#define UART_CR_URX_LSE_MASK_LEN (1U) -#define UART_CR_URX_LSE_MASK_MSK (((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS) -#define UART_CR_URX_LSE_MASK_UMSK (~(((1U << UART_CR_URX_LSE_MASK_LEN) - 1) << UART_CR_URX_LSE_MASK_POS)) -#define UART_CR_URX_BCR_MASK UART_CR_URX_BCR_MASK -#define UART_CR_URX_BCR_MASK_POS (9U) -#define UART_CR_URX_BCR_MASK_LEN (1U) -#define UART_CR_URX_BCR_MASK_MSK (((1U << UART_CR_URX_BCR_MASK_LEN) - 1) << UART_CR_URX_BCR_MASK_POS) -#define UART_CR_URX_BCR_MASK_UMSK (~(((1U << UART_CR_URX_BCR_MASK_LEN) - 1) << UART_CR_URX_BCR_MASK_POS)) -#define UART_CR_URX_ADS_MASK UART_CR_URX_ADS_MASK -#define UART_CR_URX_ADS_MASK_POS (10U) -#define UART_CR_URX_ADS_MASK_LEN (1U) -#define UART_CR_URX_ADS_MASK_MSK (((1U << UART_CR_URX_ADS_MASK_LEN) - 1) << UART_CR_URX_ADS_MASK_POS) -#define UART_CR_URX_ADS_MASK_UMSK (~(((1U << UART_CR_URX_ADS_MASK_LEN) - 1) << UART_CR_URX_ADS_MASK_POS)) -#define UART_CR_URX_AD5_MASK UART_CR_URX_AD5_MASK -#define UART_CR_URX_AD5_MASK_POS (11U) -#define UART_CR_URX_AD5_MASK_LEN (1U) -#define UART_CR_URX_AD5_MASK_MSK (((1U << UART_CR_URX_AD5_MASK_LEN) - 1) << UART_CR_URX_AD5_MASK_POS) -#define UART_CR_URX_AD5_MASK_UMSK (~(((1U << UART_CR_URX_AD5_MASK_LEN) - 1) << UART_CR_URX_AD5_MASK_POS)) - -/* 0x28 : UART interrupt clear */ -#define UART_INT_CLEAR_OFFSET (0x28) -#define UART_CR_UTX_END_CLR UART_CR_UTX_END_CLR -#define UART_CR_UTX_END_CLR_POS (0U) -#define UART_CR_UTX_END_CLR_LEN (1U) -#define UART_CR_UTX_END_CLR_MSK (((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS) -#define UART_CR_UTX_END_CLR_UMSK (~(((1U << UART_CR_UTX_END_CLR_LEN) - 1) << UART_CR_UTX_END_CLR_POS)) -#define UART_CR_URX_END_CLR UART_CR_URX_END_CLR -#define UART_CR_URX_END_CLR_POS (1U) -#define UART_CR_URX_END_CLR_LEN (1U) -#define UART_CR_URX_END_CLR_MSK (((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS) -#define UART_CR_URX_END_CLR_UMSK (~(((1U << UART_CR_URX_END_CLR_LEN) - 1) << UART_CR_URX_END_CLR_POS)) -#define UART_CR_URX_RTO_CLR UART_CR_URX_RTO_CLR -#define UART_CR_URX_RTO_CLR_POS (4U) -#define UART_CR_URX_RTO_CLR_LEN (1U) -#define UART_CR_URX_RTO_CLR_MSK (((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS) -#define UART_CR_URX_RTO_CLR_UMSK (~(((1U << UART_CR_URX_RTO_CLR_LEN) - 1) << UART_CR_URX_RTO_CLR_POS)) -#define UART_CR_URX_PCE_CLR UART_CR_URX_PCE_CLR -#define UART_CR_URX_PCE_CLR_POS (5U) -#define UART_CR_URX_PCE_CLR_LEN (1U) -#define UART_CR_URX_PCE_CLR_MSK (((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS) -#define UART_CR_URX_PCE_CLR_UMSK (~(((1U << UART_CR_URX_PCE_CLR_LEN) - 1) << UART_CR_URX_PCE_CLR_POS)) -#define UART_CR_URX_LSE_CLR UART_CR_URX_LSE_CLR -#define UART_CR_URX_LSE_CLR_POS (8U) -#define UART_CR_URX_LSE_CLR_LEN (1U) -#define UART_CR_URX_LSE_CLR_MSK (((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS) -#define UART_CR_URX_LSE_CLR_UMSK (~(((1U << UART_CR_URX_LSE_CLR_LEN) - 1) << UART_CR_URX_LSE_CLR_POS)) -#define UART_CR_URX_BCR_CLR UART_CR_URX_BCR_CLR -#define UART_CR_URX_BCR_CLR_POS (9U) -#define UART_CR_URX_BCR_CLR_LEN (1U) -#define UART_CR_URX_BCR_CLR_MSK (((1U << UART_CR_URX_BCR_CLR_LEN) - 1) << UART_CR_URX_BCR_CLR_POS) -#define UART_CR_URX_BCR_CLR_UMSK (~(((1U << UART_CR_URX_BCR_CLR_LEN) - 1) << UART_CR_URX_BCR_CLR_POS)) -#define UART_CR_URX_ADS_CLR UART_CR_URX_ADS_CLR -#define UART_CR_URX_ADS_CLR_POS (10U) -#define UART_CR_URX_ADS_CLR_LEN (1U) -#define UART_CR_URX_ADS_CLR_MSK (((1U << UART_CR_URX_ADS_CLR_LEN) - 1) << UART_CR_URX_ADS_CLR_POS) -#define UART_CR_URX_ADS_CLR_UMSK (~(((1U << UART_CR_URX_ADS_CLR_LEN) - 1) << UART_CR_URX_ADS_CLR_POS)) -#define UART_CR_URX_AD5_CLR UART_CR_URX_AD5_CLR -#define UART_CR_URX_AD5_CLR_POS (11U) -#define UART_CR_URX_AD5_CLR_LEN (1U) -#define UART_CR_URX_AD5_CLR_MSK (((1U << UART_CR_URX_AD5_CLR_LEN) - 1) << UART_CR_URX_AD5_CLR_POS) -#define UART_CR_URX_AD5_CLR_UMSK (~(((1U << UART_CR_URX_AD5_CLR_LEN) - 1) << UART_CR_URX_AD5_CLR_POS)) - -/* 0x2C : UART interrupt enable */ -#define UART_INT_EN_OFFSET (0x2C) -#define UART_CR_UTX_END_EN UART_CR_UTX_END_EN -#define UART_CR_UTX_END_EN_POS (0U) -#define UART_CR_UTX_END_EN_LEN (1U) -#define UART_CR_UTX_END_EN_MSK (((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS) -#define UART_CR_UTX_END_EN_UMSK (~(((1U << UART_CR_UTX_END_EN_LEN) - 1) << UART_CR_UTX_END_EN_POS)) -#define UART_CR_URX_END_EN UART_CR_URX_END_EN -#define UART_CR_URX_END_EN_POS (1U) -#define UART_CR_URX_END_EN_LEN (1U) -#define UART_CR_URX_END_EN_MSK (((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS) -#define UART_CR_URX_END_EN_UMSK (~(((1U << UART_CR_URX_END_EN_LEN) - 1) << UART_CR_URX_END_EN_POS)) -#define UART_CR_UTX_FRDY_EN UART_CR_UTX_FRDY_EN -#define UART_CR_UTX_FRDY_EN_POS (2U) -#define UART_CR_UTX_FRDY_EN_LEN (1U) -#define UART_CR_UTX_FRDY_EN_MSK (((1U << UART_CR_UTX_FRDY_EN_LEN) - 1) << UART_CR_UTX_FRDY_EN_POS) -#define UART_CR_UTX_FRDY_EN_UMSK (~(((1U << UART_CR_UTX_FRDY_EN_LEN) - 1) << UART_CR_UTX_FRDY_EN_POS)) -#define UART_CR_URX_FRDY_EN UART_CR_URX_FRDY_EN -#define UART_CR_URX_FRDY_EN_POS (3U) -#define UART_CR_URX_FRDY_EN_LEN (1U) -#define UART_CR_URX_FRDY_EN_MSK (((1U << UART_CR_URX_FRDY_EN_LEN) - 1) << UART_CR_URX_FRDY_EN_POS) -#define UART_CR_URX_FRDY_EN_UMSK (~(((1U << UART_CR_URX_FRDY_EN_LEN) - 1) << UART_CR_URX_FRDY_EN_POS)) -#define UART_CR_URX_RTO_EN UART_CR_URX_RTO_EN -#define UART_CR_URX_RTO_EN_POS (4U) -#define UART_CR_URX_RTO_EN_LEN (1U) -#define UART_CR_URX_RTO_EN_MSK (((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS) -#define UART_CR_URX_RTO_EN_UMSK (~(((1U << UART_CR_URX_RTO_EN_LEN) - 1) << UART_CR_URX_RTO_EN_POS)) -#define UART_CR_URX_PCE_EN UART_CR_URX_PCE_EN -#define UART_CR_URX_PCE_EN_POS (5U) -#define UART_CR_URX_PCE_EN_LEN (1U) -#define UART_CR_URX_PCE_EN_MSK (((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS) -#define UART_CR_URX_PCE_EN_UMSK (~(((1U << UART_CR_URX_PCE_EN_LEN) - 1) << UART_CR_URX_PCE_EN_POS)) -#define UART_CR_UTX_FER_EN UART_CR_UTX_FER_EN -#define UART_CR_UTX_FER_EN_POS (6U) -#define UART_CR_UTX_FER_EN_LEN (1U) -#define UART_CR_UTX_FER_EN_MSK (((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS) -#define UART_CR_UTX_FER_EN_UMSK (~(((1U << UART_CR_UTX_FER_EN_LEN) - 1) << UART_CR_UTX_FER_EN_POS)) -#define UART_CR_URX_FER_EN UART_CR_URX_FER_EN -#define UART_CR_URX_FER_EN_POS (7U) -#define UART_CR_URX_FER_EN_LEN (1U) -#define UART_CR_URX_FER_EN_MSK (((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS) -#define UART_CR_URX_FER_EN_UMSK (~(((1U << UART_CR_URX_FER_EN_LEN) - 1) << UART_CR_URX_FER_EN_POS)) -#define UART_CR_URX_LSE_EN UART_CR_URX_LSE_EN -#define UART_CR_URX_LSE_EN_POS (8U) -#define UART_CR_URX_LSE_EN_LEN (1U) -#define UART_CR_URX_LSE_EN_MSK (((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS) -#define UART_CR_URX_LSE_EN_UMSK (~(((1U << UART_CR_URX_LSE_EN_LEN) - 1) << UART_CR_URX_LSE_EN_POS)) -#define UART_CR_URX_BCR_EN UART_CR_URX_BCR_EN -#define UART_CR_URX_BCR_EN_POS (9U) -#define UART_CR_URX_BCR_EN_LEN (1U) -#define UART_CR_URX_BCR_EN_MSK (((1U << UART_CR_URX_BCR_EN_LEN) - 1) << UART_CR_URX_BCR_EN_POS) -#define UART_CR_URX_BCR_EN_UMSK (~(((1U << UART_CR_URX_BCR_EN_LEN) - 1) << UART_CR_URX_BCR_EN_POS)) -#define UART_CR_URX_ADS_EN UART_CR_URX_ADS_EN -#define UART_CR_URX_ADS_EN_POS (10U) -#define UART_CR_URX_ADS_EN_LEN (1U) -#define UART_CR_URX_ADS_EN_MSK (((1U << UART_CR_URX_ADS_EN_LEN) - 1) << UART_CR_URX_ADS_EN_POS) -#define UART_CR_URX_ADS_EN_UMSK (~(((1U << UART_CR_URX_ADS_EN_LEN) - 1) << UART_CR_URX_ADS_EN_POS)) -#define UART_CR_URX_AD5_EN UART_CR_URX_AD5_EN -#define UART_CR_URX_AD5_EN_POS (11U) -#define UART_CR_URX_AD5_EN_LEN (1U) -#define UART_CR_URX_AD5_EN_MSK (((1U << UART_CR_URX_AD5_EN_LEN) - 1) << UART_CR_URX_AD5_EN_POS) -#define UART_CR_URX_AD5_EN_UMSK (~(((1U << UART_CR_URX_AD5_EN_LEN) - 1) << UART_CR_URX_AD5_EN_POS)) - -/* 0x30 : uart_status */ -#define UART_STATUS_OFFSET (0x30) -#define UART_STS_UTX_BUS_BUSY UART_STS_UTX_BUS_BUSY -#define UART_STS_UTX_BUS_BUSY_POS (0U) -#define UART_STS_UTX_BUS_BUSY_LEN (1U) -#define UART_STS_UTX_BUS_BUSY_MSK (((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS) -#define UART_STS_UTX_BUS_BUSY_UMSK (~(((1U << UART_STS_UTX_BUS_BUSY_LEN) - 1) << UART_STS_UTX_BUS_BUSY_POS)) -#define UART_STS_URX_BUS_BUSY UART_STS_URX_BUS_BUSY -#define UART_STS_URX_BUS_BUSY_POS (1U) -#define UART_STS_URX_BUS_BUSY_LEN (1U) -#define UART_STS_URX_BUS_BUSY_MSK (((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS) -#define UART_STS_URX_BUS_BUSY_UMSK (~(((1U << UART_STS_URX_BUS_BUSY_LEN) - 1) << UART_STS_URX_BUS_BUSY_POS)) - -/* 0x34 : sts_urx_abr_prd */ -#define UART_STS_URX_ABR_PRD_OFFSET (0x34) -#define UART_STS_URX_ABR_PRD_START UART_STS_URX_ABR_PRD_START -#define UART_STS_URX_ABR_PRD_START_POS (0U) -#define UART_STS_URX_ABR_PRD_START_LEN (16U) -#define UART_STS_URX_ABR_PRD_START_MSK (((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS) -#define UART_STS_URX_ABR_PRD_START_UMSK (~(((1U << UART_STS_URX_ABR_PRD_START_LEN) - 1) << UART_STS_URX_ABR_PRD_START_POS)) -#define UART_STS_URX_ABR_PRD_0X55 UART_STS_URX_ABR_PRD_0X55 -#define UART_STS_URX_ABR_PRD_0X55_POS (16U) -#define UART_STS_URX_ABR_PRD_0X55_LEN (16U) -#define UART_STS_URX_ABR_PRD_0X55_MSK (((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS) -#define UART_STS_URX_ABR_PRD_0X55_UMSK (~(((1U << UART_STS_URX_ABR_PRD_0X55_LEN) - 1) << UART_STS_URX_ABR_PRD_0X55_POS)) - -/* 0x38 : urx_abr_prd_b01 */ -#define UART_URX_ABR_PRD_B01_OFFSET (0x38) -#define UART_STS_URX_ABR_PRD_BIT0 UART_STS_URX_ABR_PRD_BIT0 -#define UART_STS_URX_ABR_PRD_BIT0_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT0_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT0_MSK (((1U << UART_STS_URX_ABR_PRD_BIT0_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT0_POS) -#define UART_STS_URX_ABR_PRD_BIT0_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT0_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT0_POS)) -#define UART_STS_URX_ABR_PRD_BIT1 UART_STS_URX_ABR_PRD_BIT1 -#define UART_STS_URX_ABR_PRD_BIT1_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT1_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT1_MSK (((1U << UART_STS_URX_ABR_PRD_BIT1_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT1_POS) -#define UART_STS_URX_ABR_PRD_BIT1_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT1_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT1_POS)) - -/* 0x3C : urx_abr_prd_b23 */ -#define UART_URX_ABR_PRD_B23_OFFSET (0x3C) -#define UART_STS_URX_ABR_PRD_BIT2 UART_STS_URX_ABR_PRD_BIT2 -#define UART_STS_URX_ABR_PRD_BIT2_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT2_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT2_MSK (((1U << UART_STS_URX_ABR_PRD_BIT2_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT2_POS) -#define UART_STS_URX_ABR_PRD_BIT2_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT2_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT2_POS)) -#define UART_STS_URX_ABR_PRD_BIT3 UART_STS_URX_ABR_PRD_BIT3 -#define UART_STS_URX_ABR_PRD_BIT3_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT3_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT3_MSK (((1U << UART_STS_URX_ABR_PRD_BIT3_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT3_POS) -#define UART_STS_URX_ABR_PRD_BIT3_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT3_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT3_POS)) - -/* 0x40 : urx_abr_prd_b45 */ -#define UART_URX_ABR_PRD_B45_OFFSET (0x40) -#define UART_STS_URX_ABR_PRD_BIT4 UART_STS_URX_ABR_PRD_BIT4 -#define UART_STS_URX_ABR_PRD_BIT4_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT4_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT4_MSK (((1U << UART_STS_URX_ABR_PRD_BIT4_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT4_POS) -#define UART_STS_URX_ABR_PRD_BIT4_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT4_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT4_POS)) -#define UART_STS_URX_ABR_PRD_BIT5 UART_STS_URX_ABR_PRD_BIT5 -#define UART_STS_URX_ABR_PRD_BIT5_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT5_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT5_MSK (((1U << UART_STS_URX_ABR_PRD_BIT5_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT5_POS) -#define UART_STS_URX_ABR_PRD_BIT5_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT5_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT5_POS)) - -/* 0x44 : urx_abr_prd_b67 */ -#define UART_URX_ABR_PRD_B67_OFFSET (0x44) -#define UART_STS_URX_ABR_PRD_BIT6 UART_STS_URX_ABR_PRD_BIT6 -#define UART_STS_URX_ABR_PRD_BIT6_POS (0U) -#define UART_STS_URX_ABR_PRD_BIT6_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT6_MSK (((1U << UART_STS_URX_ABR_PRD_BIT6_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT6_POS) -#define UART_STS_URX_ABR_PRD_BIT6_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT6_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT6_POS)) -#define UART_STS_URX_ABR_PRD_BIT7 UART_STS_URX_ABR_PRD_BIT7 -#define UART_STS_URX_ABR_PRD_BIT7_POS (16U) -#define UART_STS_URX_ABR_PRD_BIT7_LEN (16U) -#define UART_STS_URX_ABR_PRD_BIT7_MSK (((1U << UART_STS_URX_ABR_PRD_BIT7_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT7_POS) -#define UART_STS_URX_ABR_PRD_BIT7_UMSK (~(((1U << UART_STS_URX_ABR_PRD_BIT7_LEN) - 1) << UART_STS_URX_ABR_PRD_BIT7_POS)) - -/* 0x48 : urx_abr_pw_tol */ -#define UART_URX_ABR_PW_TOL_OFFSET (0x48) -#define UART_CR_URX_ABR_PW_TOL UART_CR_URX_ABR_PW_TOL -#define UART_CR_URX_ABR_PW_TOL_POS (0U) -#define UART_CR_URX_ABR_PW_TOL_LEN (8U) -#define UART_CR_URX_ABR_PW_TOL_MSK (((1U << UART_CR_URX_ABR_PW_TOL_LEN) - 1) << UART_CR_URX_ABR_PW_TOL_POS) -#define UART_CR_URX_ABR_PW_TOL_UMSK (~(((1U << UART_CR_URX_ABR_PW_TOL_LEN) - 1) << UART_CR_URX_ABR_PW_TOL_POS)) - -/* 0x50 : urx_bcr_int_cfg */ -#define UART_URX_BCR_INT_CFG_OFFSET (0x50) -#define UART_CR_URX_BCR_VALUE UART_CR_URX_BCR_VALUE -#define UART_CR_URX_BCR_VALUE_POS (0U) -#define UART_CR_URX_BCR_VALUE_LEN (16U) -#define UART_CR_URX_BCR_VALUE_MSK (((1U << UART_CR_URX_BCR_VALUE_LEN) - 1) << UART_CR_URX_BCR_VALUE_POS) -#define UART_CR_URX_BCR_VALUE_UMSK (~(((1U << UART_CR_URX_BCR_VALUE_LEN) - 1) << UART_CR_URX_BCR_VALUE_POS)) -#define UART_STS_URX_BCR_COUNT UART_STS_URX_BCR_COUNT -#define UART_STS_URX_BCR_COUNT_POS (16U) -#define UART_STS_URX_BCR_COUNT_LEN (16U) -#define UART_STS_URX_BCR_COUNT_MSK (((1U << UART_STS_URX_BCR_COUNT_LEN) - 1) << UART_STS_URX_BCR_COUNT_POS) -#define UART_STS_URX_BCR_COUNT_UMSK (~(((1U << UART_STS_URX_BCR_COUNT_LEN) - 1) << UART_STS_URX_BCR_COUNT_POS)) - -/* 0x54 : utx_rs485_cfg */ -#define UART_UTX_RS485_CFG_OFFSET (0x54) -#define UART_CR_UTX_RS485_EN UART_CR_UTX_RS485_EN -#define UART_CR_UTX_RS485_EN_POS (0U) -#define UART_CR_UTX_RS485_EN_LEN (1U) -#define UART_CR_UTX_RS485_EN_MSK (((1U << UART_CR_UTX_RS485_EN_LEN) - 1) << UART_CR_UTX_RS485_EN_POS) -#define UART_CR_UTX_RS485_EN_UMSK (~(((1U << UART_CR_UTX_RS485_EN_LEN) - 1) << UART_CR_UTX_RS485_EN_POS)) -#define UART_CR_UTX_RS485_POL UART_CR_UTX_RS485_POL -#define UART_CR_UTX_RS485_POL_POS (1U) -#define UART_CR_UTX_RS485_POL_LEN (1U) -#define UART_CR_UTX_RS485_POL_MSK (((1U << UART_CR_UTX_RS485_POL_LEN) - 1) << UART_CR_UTX_RS485_POL_POS) -#define UART_CR_UTX_RS485_POL_UMSK (~(((1U << UART_CR_UTX_RS485_POL_LEN) - 1) << UART_CR_UTX_RS485_POL_POS)) - -/* 0x80 : uart_fifo_config_0 */ -#define UART_FIFO_CONFIG_0_OFFSET (0x80) -#define UART_DMA_TX_EN UART_DMA_TX_EN -#define UART_DMA_TX_EN_POS (0U) -#define UART_DMA_TX_EN_LEN (1U) -#define UART_DMA_TX_EN_MSK (((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS) -#define UART_DMA_TX_EN_UMSK (~(((1U << UART_DMA_TX_EN_LEN) - 1) << UART_DMA_TX_EN_POS)) -#define UART_DMA_RX_EN UART_DMA_RX_EN -#define UART_DMA_RX_EN_POS (1U) -#define UART_DMA_RX_EN_LEN (1U) -#define UART_DMA_RX_EN_MSK (((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS) -#define UART_DMA_RX_EN_UMSK (~(((1U << UART_DMA_RX_EN_LEN) - 1) << UART_DMA_RX_EN_POS)) -#define UART_TX_FIFO_CLR UART_TX_FIFO_CLR -#define UART_TX_FIFO_CLR_POS (2U) -#define UART_TX_FIFO_CLR_LEN (1U) -#define UART_TX_FIFO_CLR_MSK (((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS) -#define UART_TX_FIFO_CLR_UMSK (~(((1U << UART_TX_FIFO_CLR_LEN) - 1) << UART_TX_FIFO_CLR_POS)) -#define UART_RX_FIFO_CLR UART_RX_FIFO_CLR -#define UART_RX_FIFO_CLR_POS (3U) -#define UART_RX_FIFO_CLR_LEN (1U) -#define UART_RX_FIFO_CLR_MSK (((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS) -#define UART_RX_FIFO_CLR_UMSK (~(((1U << UART_RX_FIFO_CLR_LEN) - 1) << UART_RX_FIFO_CLR_POS)) -#define UART_TX_FIFO_OVERFLOW UART_TX_FIFO_OVERFLOW -#define UART_TX_FIFO_OVERFLOW_POS (4U) -#define UART_TX_FIFO_OVERFLOW_LEN (1U) -#define UART_TX_FIFO_OVERFLOW_MSK (((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS) -#define UART_TX_FIFO_OVERFLOW_UMSK (~(((1U << UART_TX_FIFO_OVERFLOW_LEN) - 1) << UART_TX_FIFO_OVERFLOW_POS)) -#define UART_TX_FIFO_UNDERFLOW UART_TX_FIFO_UNDERFLOW -#define UART_TX_FIFO_UNDERFLOW_POS (5U) -#define UART_TX_FIFO_UNDERFLOW_LEN (1U) -#define UART_TX_FIFO_UNDERFLOW_MSK (((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS) -#define UART_TX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_TX_FIFO_UNDERFLOW_LEN) - 1) << UART_TX_FIFO_UNDERFLOW_POS)) -#define UART_RX_FIFO_OVERFLOW UART_RX_FIFO_OVERFLOW -#define UART_RX_FIFO_OVERFLOW_POS (6U) -#define UART_RX_FIFO_OVERFLOW_LEN (1U) -#define UART_RX_FIFO_OVERFLOW_MSK (((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS) -#define UART_RX_FIFO_OVERFLOW_UMSK (~(((1U << UART_RX_FIFO_OVERFLOW_LEN) - 1) << UART_RX_FIFO_OVERFLOW_POS)) -#define UART_RX_FIFO_UNDERFLOW UART_RX_FIFO_UNDERFLOW -#define UART_RX_FIFO_UNDERFLOW_POS (7U) -#define UART_RX_FIFO_UNDERFLOW_LEN (1U) -#define UART_RX_FIFO_UNDERFLOW_MSK (((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS) -#define UART_RX_FIFO_UNDERFLOW_UMSK (~(((1U << UART_RX_FIFO_UNDERFLOW_LEN) - 1) << UART_RX_FIFO_UNDERFLOW_POS)) - -/* 0x84 : uart_fifo_config_1 */ -#define UART_FIFO_CONFIG_1_OFFSET (0x84) -#define UART_TX_FIFO_CNT UART_TX_FIFO_CNT -#define UART_TX_FIFO_CNT_POS (0U) -#define UART_TX_FIFO_CNT_LEN (6U) -#define UART_TX_FIFO_CNT_MSK (((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS) -#define UART_TX_FIFO_CNT_UMSK (~(((1U << UART_TX_FIFO_CNT_LEN) - 1) << UART_TX_FIFO_CNT_POS)) -#define UART_RX_FIFO_CNT UART_RX_FIFO_CNT -#define UART_RX_FIFO_CNT_POS (8U) -#define UART_RX_FIFO_CNT_LEN (6U) -#define UART_RX_FIFO_CNT_MSK (((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS) -#define UART_RX_FIFO_CNT_UMSK (~(((1U << UART_RX_FIFO_CNT_LEN) - 1) << UART_RX_FIFO_CNT_POS)) -#define UART_TX_FIFO_TH UART_TX_FIFO_TH -#define UART_TX_FIFO_TH_POS (16U) -#define UART_TX_FIFO_TH_LEN (5U) -#define UART_TX_FIFO_TH_MSK (((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS) -#define UART_TX_FIFO_TH_UMSK (~(((1U << UART_TX_FIFO_TH_LEN) - 1) << UART_TX_FIFO_TH_POS)) -#define UART_RX_FIFO_TH UART_RX_FIFO_TH -#define UART_RX_FIFO_TH_POS (24U) -#define UART_RX_FIFO_TH_LEN (5U) -#define UART_RX_FIFO_TH_MSK (((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS) -#define UART_RX_FIFO_TH_UMSK (~(((1U << UART_RX_FIFO_TH_LEN) - 1) << UART_RX_FIFO_TH_POS)) - -/* 0x88 : uart_fifo_wdata */ -#define UART_FIFO_WDATA_OFFSET (0x88) -#define UART_FIFO_WDATA UART_FIFO_WDATA -#define UART_FIFO_WDATA_POS (0U) -#define UART_FIFO_WDATA_LEN (8U) -#define UART_FIFO_WDATA_MSK (((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS) -#define UART_FIFO_WDATA_UMSK (~(((1U << UART_FIFO_WDATA_LEN) - 1) << UART_FIFO_WDATA_POS)) - -/* 0x8C : uart_fifo_rdata */ -#define UART_FIFO_RDATA_OFFSET (0x8C) -#define UART_FIFO_RDATA UART_FIFO_RDATA -#define UART_FIFO_RDATA_POS (0U) -#define UART_FIFO_RDATA_LEN (8U) -#define UART_FIFO_RDATA_MSK (((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS) -#define UART_FIFO_RDATA_UMSK (~(((1U << UART_FIFO_RDATA_LEN) - 1) << UART_FIFO_RDATA_POS)) - -struct uart_reg { - /* 0x0 : utx_config */ - union { - struct { - uint32_t cr_utx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_utx_cts_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_utx_frm_en : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_utx_lin_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_utx_prt_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_utx_prt_sel : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_utx_ir_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_utx_ir_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_utx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ - uint32_t cr_utx_bit_cnt_p : 2; /* [12:11], r/w, 0x1 */ - uint32_t cr_utx_bit_cnt_b : 3; /* [15:13], r/w, 0x4 */ - uint32_t cr_utx_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } utx_config; - - /* 0x4 : urx_config */ - union { - struct { - uint32_t cr_urx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_urx_abr_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t reserved_2 : 1; /* [ 2], rsvd, 0x0 */ - uint32_t cr_urx_lin_en : 1; /* [ 3], r/w, 0x0 */ - uint32_t cr_urx_prt_en : 1; /* [ 4], r/w, 0x0 */ - uint32_t cr_urx_prt_sel : 1; /* [ 5], r/w, 0x0 */ - uint32_t cr_urx_ir_en : 1; /* [ 6], r/w, 0x0 */ - uint32_t cr_urx_ir_inv : 1; /* [ 7], r/w, 0x0 */ - uint32_t cr_urx_bit_cnt_d : 3; /* [10: 8], r/w, 0x7 */ - uint32_t cr_urx_deg_en : 1; /* [ 11], r/w, 0x0 */ - uint32_t cr_urx_deg_cnt : 4; /* [15:12], r/w, 0x0 */ - uint32_t cr_urx_len : 16; /* [31:16], r/w, 0x0 */ - } BF; - uint32_t WORD; - } urx_config; - - /* 0x8 : uart_bit_prd */ - union { - struct { - uint32_t cr_utx_bit_prd : 16; /* [15: 0], r/w, 0xff */ - uint32_t cr_urx_bit_prd : 16; /* [31:16], r/w, 0xff */ - } BF; - uint32_t WORD; - } uart_bit_prd; - - /* 0xC : data_config */ - union { - struct { - uint32_t cr_uart_bit_inv : 1; /* [ 0], r/w, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } data_config; - - /* 0x10 : utx_ir_position */ - union { - struct { - uint32_t cr_utx_ir_pos_s : 16; /* [15: 0], r/w, 0x70 */ - uint32_t cr_utx_ir_pos_p : 16; /* [31:16], r/w, 0x9f */ - } BF; - uint32_t WORD; - } utx_ir_position; - - /* 0x14 : urx_ir_position */ - union { - struct { - uint32_t cr_urx_ir_pos_s : 16; /* [15: 0], r/w, 0x6f */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } urx_ir_position; - - /* 0x18 : urx_rto_timer */ - union { - struct { - uint32_t cr_urx_rto_value : 8; /* [ 7: 0], r/w, 0xf */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } urx_rto_timer; - - /* 0x1C : uart_sw_mode */ - union { - struct { - uint32_t cr_utx_txd_sw_mode : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_utx_txd_sw_val : 1; /* [ 1], r/w, 0x0 */ - uint32_t cr_urx_rts_sw_mode : 1; /* [ 2], r/w, 0x0 */ - uint32_t cr_urx_rts_sw_val : 1; /* [ 3], r/w, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_sw_mode; - - /* 0x20 : UART interrupt status */ - union { - struct { - uint32_t utx_end_int : 1; /* [ 0], r, 0x0 */ - uint32_t urx_end_int : 1; /* [ 1], r, 0x0 */ - uint32_t utx_frdy_int : 1; /* [ 2], r, 0x1 */ - uint32_t urx_frdy_int : 1; /* [ 3], r, 0x0 */ - uint32_t urx_rto_int : 1; /* [ 4], r, 0x0 */ - uint32_t urx_pce_int : 1; /* [ 5], r, 0x0 */ - uint32_t utx_fer_int : 1; /* [ 6], r, 0x0 */ - uint32_t urx_fer_int : 1; /* [ 7], r, 0x0 */ - uint32_t urx_lse_int : 1; /* [ 8], r, 0x0 */ - uint32_t urx_bcr_int : 1; /* [ 9], r, 0x0 */ - uint32_t urx_ads_int : 1; /* [ 10], r, 0x0 */ - uint32_t urx_ad5_int : 1; /* [ 11], r, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_sts; - - /* 0x24 : UART interrupt mask */ - union { - struct { - uint32_t cr_utx_end_mask : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_urx_end_mask : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_utx_frdy_mask : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_urx_frdy_mask : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_urx_rto_mask : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_urx_pce_mask : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_utx_fer_mask : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_urx_fer_mask : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_urx_lse_mask : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_urx_bcr_mask : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_urx_ads_mask : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_urx_ad5_mask : 1; /* [ 11], r/w, 0x1 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_mask; - - /* 0x28 : UART interrupt clear */ - union { - struct { - uint32_t cr_utx_end_clr : 1; /* [ 0], w1c, 0x0 */ - uint32_t cr_urx_end_clr : 1; /* [ 1], w1c, 0x0 */ - uint32_t rsvd_2 : 1; /* [ 2], rsvd, 0x0 */ - uint32_t rsvd_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t cr_urx_rto_clr : 1; /* [ 4], w1c, 0x0 */ - uint32_t cr_urx_pce_clr : 1; /* [ 5], w1c, 0x0 */ - uint32_t rsvd_6 : 1; /* [ 6], rsvd, 0x0 */ - uint32_t rsvd_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t cr_urx_lse_clr : 1; /* [ 8], w1c, 0x0 */ - uint32_t cr_urx_bcr_clr : 1; /* [ 9], w1c, 0x0 */ - uint32_t cr_urx_ads_clr : 1; /* [ 10], w1c, 0x0 */ - uint32_t cr_urx_ad5_clr : 1; /* [ 11], w1c, 0x0 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_clear; - - /* 0x2C : UART interrupt enable */ - union { - struct { - uint32_t cr_utx_end_en : 1; /* [ 0], r/w, 0x1 */ - uint32_t cr_urx_end_en : 1; /* [ 1], r/w, 0x1 */ - uint32_t cr_utx_frdy_en : 1; /* [ 2], r/w, 0x1 */ - uint32_t cr_urx_frdy_en : 1; /* [ 3], r/w, 0x1 */ - uint32_t cr_urx_rto_en : 1; /* [ 4], r/w, 0x1 */ - uint32_t cr_urx_pce_en : 1; /* [ 5], r/w, 0x1 */ - uint32_t cr_utx_fer_en : 1; /* [ 6], r/w, 0x1 */ - uint32_t cr_urx_fer_en : 1; /* [ 7], r/w, 0x1 */ - uint32_t cr_urx_lse_en : 1; /* [ 8], r/w, 0x1 */ - uint32_t cr_urx_bcr_en : 1; /* [ 9], r/w, 0x1 */ - uint32_t cr_urx_ads_en : 1; /* [ 10], r/w, 0x1 */ - uint32_t cr_urx_ad5_en : 1; /* [ 11], r/w, 0x1 */ - uint32_t reserved_12_31 : 20; /* [31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_int_en; - - /* 0x30 : uart_status */ - union { - struct { - uint32_t sts_utx_bus_busy : 1; /* [ 0], r, 0x0 */ - uint32_t sts_urx_bus_busy : 1; /* [ 1], r, 0x0 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_status; - - /* 0x34 : sts_urx_abr_prd */ - union { - struct { - uint32_t sts_urx_abr_prd_start : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_0x55 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } sts_urx_abr_prd; - - /* 0x38 : urx_abr_prd_b01 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit0 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit1 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b01; - - /* 0x3C : urx_abr_prd_b23 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit2 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit3 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b23; - - /* 0x40 : urx_abr_prd_b45 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit4 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit5 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b45; - - /* 0x44 : urx_abr_prd_b67 */ - union { - struct { - uint32_t sts_urx_abr_prd_bit6 : 16; /* [15: 0], r, 0x0 */ - uint32_t sts_urx_abr_prd_bit7 : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_prd_b67; - - /* 0x48 : urx_abr_pw_tol */ - union { - struct { - uint32_t cr_urx_abr_pw_tol : 8; /* [ 7: 0], r/w, 0x3 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } urx_abr_pw_tol; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[4]; - - /* 0x50 : urx_bcr_int_cfg */ - union { - struct { - uint32_t cr_urx_bcr_value : 16; /* [15: 0], r/w, 0xffff */ - uint32_t sts_urx_bcr_count : 16; /* [31:16], r, 0x0 */ - } BF; - uint32_t WORD; - } urx_bcr_int_cfg; - - /* 0x54 : utx_rs485_cfg */ - union { - struct { - uint32_t cr_utx_rs485_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t cr_utx_rs485_pol : 1; /* [ 1], r/w, 0x1 */ - uint32_t reserved_2_31 : 30; /* [31: 2], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } utx_rs485_cfg; - - /* 0x58 reserved */ - uint8_t RESERVED0x58[40]; - - /* 0x80 : uart_fifo_config_0 */ - union { - struct { - uint32_t uart_dma_tx_en : 1; /* [ 0], r/w, 0x0 */ - uint32_t uart_dma_rx_en : 1; /* [ 1], r/w, 0x0 */ - uint32_t tx_fifo_clr : 1; /* [ 2], w1c, 0x0 */ - uint32_t rx_fifo_clr : 1; /* [ 3], w1c, 0x0 */ - uint32_t tx_fifo_overflow : 1; /* [ 4], r, 0x0 */ - uint32_t tx_fifo_underflow : 1; /* [ 5], r, 0x0 */ - uint32_t rx_fifo_overflow : 1; /* [ 6], r, 0x0 */ - uint32_t rx_fifo_underflow : 1; /* [ 7], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_config_0; - - /* 0x84 : uart_fifo_config_1 */ - union { - struct { - uint32_t tx_fifo_cnt : 6; /* [ 5: 0], r, 0x20 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t rx_fifo_cnt : 6; /* [13: 8], r, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t tx_fifo_th : 5; /* [20:16], r/w, 0x0 */ - uint32_t reserved_21_23 : 3; /* [23:21], rsvd, 0x0 */ - uint32_t rx_fifo_th : 5; /* [28:24], r/w, 0x0 */ - uint32_t reserved_29_31 : 3; /* [31:29], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_config_1; - - /* 0x88 : uart_fifo_wdata */ - union { - struct { - uint32_t uart_fifo_wdata : 8; /* [ 7: 0], w, x */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_wdata; - - /* 0x8C : uart_fifo_rdata */ - union { - struct { - uint32_t uart_fifo_rdata : 8; /* [ 7: 0], r, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } uart_fifo_rdata; -}; - -typedef volatile struct uart_reg uart_reg_t; - -#endif /* __UART_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/usb_reg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/usb_reg.h deleted file mode 100644 index 32c552ef54..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/usb_reg.h +++ /dev/null @@ -1,5352 +0,0 @@ -/** - ****************************************************************************** - * @file usb_reg.h - * @version V1.0 - * @date 2021-04-20 - * @brief This file is the description of.IP register - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __USB_REG_H__ -#define __USB_REG_H__ - -#include "bl808.h" - -/* 0x000 : HCCAP */ -#define USB_HCCAP_OFFSET (0x000) -#define USB_CAPLENGTH USB_CAPLENGTH -#define USB_CAPLENGTH_POS (0U) -#define USB_CAPLENGTH_LEN (8U) -#define USB_CAPLENGTH_MSK (((1U << USB_CAPLENGTH_LEN) - 1) << USB_CAPLENGTH_POS) -#define USB_CAPLENGTH_UMSK (~(((1U << USB_CAPLENGTH_LEN) - 1) << USB_CAPLENGTH_POS)) -#define USB_HCIVERSION USB_HCIVERSION -#define USB_HCIVERSION_POS (16U) -#define USB_HCIVERSION_LEN (16U) -#define USB_HCIVERSION_MSK (((1U << USB_HCIVERSION_LEN) - 1) << USB_HCIVERSION_POS) -#define USB_HCIVERSION_UMSK (~(((1U << USB_HCIVERSION_LEN) - 1) << USB_HCIVERSION_POS)) - -/* 0x004 : HCSPARAMS */ -#define USB_HCSPARAMS_OFFSET (0x004) -#define USB_N_PORTS USB_N_PORTS -#define USB_N_PORTS_POS (0U) -#define USB_N_PORTS_LEN (4U) -#define USB_N_PORTS_MSK (((1U << USB_N_PORTS_LEN) - 1) << USB_N_PORTS_POS) -#define USB_N_PORTS_UMSK (~(((1U << USB_N_PORTS_LEN) - 1) << USB_N_PORTS_POS)) - -/* 0x008 : HCCPARAMS */ -#define USB_HCCPARAMS_OFFSET (0x008) -#define USB_PROG_FR_LIST_FLAG USB_PROG_FR_LIST_FLAG -#define USB_PROG_FR_LIST_FLAG_POS (1U) -#define USB_PROG_FR_LIST_FLAG_LEN (1U) -#define USB_PROG_FR_LIST_FLAG_MSK (((1U << USB_PROG_FR_LIST_FLAG_LEN) - 1) << USB_PROG_FR_LIST_FLAG_POS) -#define USB_PROG_FR_LIST_FLAG_UMSK (~(((1U << USB_PROG_FR_LIST_FLAG_LEN) - 1) << USB_PROG_FR_LIST_FLAG_POS)) -#define USB_ASYN_SCH_PARK_CAP USB_ASYN_SCH_PARK_CAP -#define USB_ASYN_SCH_PARK_CAP_POS (2U) -#define USB_ASYN_SCH_PARK_CAP_LEN (1U) -#define USB_ASYN_SCH_PARK_CAP_MSK (((1U << USB_ASYN_SCH_PARK_CAP_LEN) - 1) << USB_ASYN_SCH_PARK_CAP_POS) -#define USB_ASYN_SCH_PARK_CAP_UMSK (~(((1U << USB_ASYN_SCH_PARK_CAP_LEN) - 1) << USB_ASYN_SCH_PARK_CAP_POS)) - -/* 0x010 : USBCMD */ -#define USBCMD_OFFSET (0x010) -#define USB_RS USB_RS -#define USB_RS_POS (0U) -#define USB_RS_LEN (1U) -#define USB_RS_MSK (((1U << USB_RS_LEN) - 1) << USB_RS_POS) -#define USB_RS_UMSK (~(((1U << USB_RS_LEN) - 1) << USB_RS_POS)) -#define USB_HC_RESET USB_HC_RESET -#define USB_HC_RESET_POS (1U) -#define USB_HC_RESET_LEN (1U) -#define USB_HC_RESET_MSK (((1U << USB_HC_RESET_LEN) - 1) << USB_HC_RESET_POS) -#define USB_HC_RESET_UMSK (~(((1U << USB_HC_RESET_LEN) - 1) << USB_HC_RESET_POS)) -#define USB_FRL_SIZE USB_FRL_SIZE -#define USB_FRL_SIZE_POS (2U) -#define USB_FRL_SIZE_LEN (2U) -#define USB_FRL_SIZE_MSK (((1U << USB_FRL_SIZE_LEN) - 1) << USB_FRL_SIZE_POS) -#define USB_FRL_SIZE_UMSK (~(((1U << USB_FRL_SIZE_LEN) - 1) << USB_FRL_SIZE_POS)) -#define USB_PSCH_EN USB_PSCH_EN -#define USB_PSCH_EN_POS (4U) -#define USB_PSCH_EN_LEN (1U) -#define USB_PSCH_EN_MSK (((1U << USB_PSCH_EN_LEN) - 1) << USB_PSCH_EN_POS) -#define USB_PSCH_EN_UMSK (~(((1U << USB_PSCH_EN_LEN) - 1) << USB_PSCH_EN_POS)) -#define USB_ASCH_EN USB_ASCH_EN -#define USB_ASCH_EN_POS (5U) -#define USB_ASCH_EN_LEN (1U) -#define USB_ASCH_EN_MSK (((1U << USB_ASCH_EN_LEN) - 1) << USB_ASCH_EN_POS) -#define USB_ASCH_EN_UMSK (~(((1U << USB_ASCH_EN_LEN) - 1) << USB_ASCH_EN_POS)) -#define USB_INT_OAAD USB_INT_OAAD -#define USB_INT_OAAD_POS (6U) -#define USB_INT_OAAD_LEN (1U) -#define USB_INT_OAAD_MSK (((1U << USB_INT_OAAD_LEN) - 1) << USB_INT_OAAD_POS) -#define USB_INT_OAAD_UMSK (~(((1U << USB_INT_OAAD_LEN) - 1) << USB_INT_OAAD_POS)) -#define USB_ASYN_PK_CNT USB_ASYN_PK_CNT -#define USB_ASYN_PK_CNT_POS (8U) -#define USB_ASYN_PK_CNT_LEN (2U) -#define USB_ASYN_PK_CNT_MSK (((1U << USB_ASYN_PK_CNT_LEN) - 1) << USB_ASYN_PK_CNT_POS) -#define USB_ASYN_PK_CNT_UMSK (~(((1U << USB_ASYN_PK_CNT_LEN) - 1) << USB_ASYN_PK_CNT_POS)) -#define USB_ASYN_PK_EN USB_ASYN_PK_EN -#define USB_ASYN_PK_EN_POS (11U) -#define USB_ASYN_PK_EN_LEN (1U) -#define USB_ASYN_PK_EN_MSK (((1U << USB_ASYN_PK_EN_LEN) - 1) << USB_ASYN_PK_EN_POS) -#define USB_ASYN_PK_EN_UMSK (~(((1U << USB_ASYN_PK_EN_LEN) - 1) << USB_ASYN_PK_EN_POS)) -#define USB_INT_THRC USB_INT_THRC -#define USB_INT_THRC_POS (16U) -#define USB_INT_THRC_LEN (8U) -#define USB_INT_THRC_MSK (((1U << USB_INT_THRC_LEN) - 1) << USB_INT_THRC_POS) -#define USB_INT_THRC_UMSK (~(((1U << USB_INT_THRC_LEN) - 1) << USB_INT_THRC_POS)) - -/* 0x014 : USBSTS */ -#define USBSTS_OFFSET (0x014) -#define USB_INT USB_INT -#define USB_INT_POS (0U) -#define USB_INT_LEN (1U) -#define USB_INT_MSK (((1U << USB_INT_LEN) - 1) << USB_INT_POS) -#define USB_INT_UMSK (~(((1U << USB_INT_LEN) - 1) << USB_INT_POS)) -#define USBERR_INT USBERR_INT -#define USBERR_INT_POS (1U) -#define USBERR_INT_LEN (1U) -#define USBERR_INT_MSK (((1U << USBERR_INT_LEN) - 1) << USBERR_INT_POS) -#define USBERR_INT_UMSK (~(((1U << USBERR_INT_LEN) - 1) << USBERR_INT_POS)) -#define USB_PO_CHG_DET USB_PO_CHG_DET -#define USB_PO_CHG_DET_POS (2U) -#define USB_PO_CHG_DET_LEN (1U) -#define USB_PO_CHG_DET_MSK (((1U << USB_PO_CHG_DET_LEN) - 1) << USB_PO_CHG_DET_POS) -#define USB_PO_CHG_DET_UMSK (~(((1U << USB_PO_CHG_DET_LEN) - 1) << USB_PO_CHG_DET_POS)) -#define USB_FRL_ROL USB_FRL_ROL -#define USB_FRL_ROL_POS (3U) -#define USB_FRL_ROL_LEN (1U) -#define USB_FRL_ROL_MSK (((1U << USB_FRL_ROL_LEN) - 1) << USB_FRL_ROL_POS) -#define USB_FRL_ROL_UMSK (~(((1U << USB_FRL_ROL_LEN) - 1) << USB_FRL_ROL_POS)) -#define USB_H_SYSERR USB_H_SYSERR -#define USB_H_SYSERR_POS (4U) -#define USB_H_SYSERR_LEN (1U) -#define USB_H_SYSERR_MSK (((1U << USB_H_SYSERR_LEN) - 1) << USB_H_SYSERR_POS) -#define USB_H_SYSERR_UMSK (~(((1U << USB_H_SYSERR_LEN) - 1) << USB_H_SYSERR_POS)) -#define USB_INT_OAA USB_INT_OAA -#define USB_INT_OAA_POS (5U) -#define USB_INT_OAA_LEN (1U) -#define USB_INT_OAA_MSK (((1U << USB_INT_OAA_LEN) - 1) << USB_INT_OAA_POS) -#define USB_INT_OAA_UMSK (~(((1U << USB_INT_OAA_LEN) - 1) << USB_INT_OAA_POS)) -#define USB_HCHALTED USB_HCHALTED -#define USB_HCHALTED_POS (12U) -#define USB_HCHALTED_LEN (1U) -#define USB_HCHALTED_MSK (((1U << USB_HCHALTED_LEN) - 1) << USB_HCHALTED_POS) -#define USB_HCHALTED_UMSK (~(((1U << USB_HCHALTED_LEN) - 1) << USB_HCHALTED_POS)) -#define USB_RECLAMATION USB_RECLAMATION -#define USB_RECLAMATION_POS (13U) -#define USB_RECLAMATION_LEN (1U) -#define USB_RECLAMATION_MSK (((1U << USB_RECLAMATION_LEN) - 1) << USB_RECLAMATION_POS) -#define USB_RECLAMATION_UMSK (~(((1U << USB_RECLAMATION_LEN) - 1) << USB_RECLAMATION_POS)) -#define USB_PSCH_STS USB_PSCH_STS -#define USB_PSCH_STS_POS (14U) -#define USB_PSCH_STS_LEN (1U) -#define USB_PSCH_STS_MSK (((1U << USB_PSCH_STS_LEN) - 1) << USB_PSCH_STS_POS) -#define USB_PSCH_STS_UMSK (~(((1U << USB_PSCH_STS_LEN) - 1) << USB_PSCH_STS_POS)) -#define USB_ASCH_STS USB_ASCH_STS -#define USB_ASCH_STS_POS (15U) -#define USB_ASCH_STS_LEN (1U) -#define USB_ASCH_STS_MSK (((1U << USB_ASCH_STS_LEN) - 1) << USB_ASCH_STS_POS) -#define USB_ASCH_STS_UMSK (~(((1U << USB_ASCH_STS_LEN) - 1) << USB_ASCH_STS_POS)) - -/* 0x018 : USBINTR */ -#define USBINTR_OFFSET (0x018) -#define USB_INT_EN USB_INT_EN -#define USB_INT_EN_POS (0U) -#define USB_INT_EN_LEN (1U) -#define USB_INT_EN_MSK (((1U << USB_INT_EN_LEN) - 1) << USB_INT_EN_POS) -#define USB_INT_EN_UMSK (~(((1U << USB_INT_EN_LEN) - 1) << USB_INT_EN_POS)) -#define USBERR_INT_EN USBERR_INT_EN -#define USBERR_INT_EN_POS (1U) -#define USBERR_INT_EN_LEN (1U) -#define USBERR_INT_EN_MSK (((1U << USBERR_INT_EN_LEN) - 1) << USBERR_INT_EN_POS) -#define USBERR_INT_EN_UMSK (~(((1U << USBERR_INT_EN_LEN) - 1) << USBERR_INT_EN_POS)) -#define USB_PO_CHG_INT_EN USB_PO_CHG_INT_EN -#define USB_PO_CHG_INT_EN_POS (2U) -#define USB_PO_CHG_INT_EN_LEN (1U) -#define USB_PO_CHG_INT_EN_MSK (((1U << USB_PO_CHG_INT_EN_LEN) - 1) << USB_PO_CHG_INT_EN_POS) -#define USB_PO_CHG_INT_EN_UMSK (~(((1U << USB_PO_CHG_INT_EN_LEN) - 1) << USB_PO_CHG_INT_EN_POS)) -#define USB_FRL_ROL_EN USB_FRL_ROL_EN -#define USB_FRL_ROL_EN_POS (3U) -#define USB_FRL_ROL_EN_LEN (1U) -#define USB_FRL_ROL_EN_MSK (((1U << USB_FRL_ROL_EN_LEN) - 1) << USB_FRL_ROL_EN_POS) -#define USB_FRL_ROL_EN_UMSK (~(((1U << USB_FRL_ROL_EN_LEN) - 1) << USB_FRL_ROL_EN_POS)) -#define USB_H_SYSERR_EN USB_H_SYSERR_EN -#define USB_H_SYSERR_EN_POS (4U) -#define USB_H_SYSERR_EN_LEN (1U) -#define USB_H_SYSERR_EN_MSK (((1U << USB_H_SYSERR_EN_LEN) - 1) << USB_H_SYSERR_EN_POS) -#define USB_H_SYSERR_EN_UMSK (~(((1U << USB_H_SYSERR_EN_LEN) - 1) << USB_H_SYSERR_EN_POS)) -#define USB_INT_OAA_EN USB_INT_OAA_EN -#define USB_INT_OAA_EN_POS (5U) -#define USB_INT_OAA_EN_LEN (1U) -#define USB_INT_OAA_EN_MSK (((1U << USB_INT_OAA_EN_LEN) - 1) << USB_INT_OAA_EN_POS) -#define USB_INT_OAA_EN_UMSK (~(((1U << USB_INT_OAA_EN_LEN) - 1) << USB_INT_OAA_EN_POS)) - -/* 0x01C : FRINDEX */ -#define USB_FRINDEX_OFFSET (0x01C) -#define USB_FRINDEX USB_FRINDEX -#define USB_FRINDEX_POS (0U) -#define USB_FRINDEX_LEN (14U) -#define USB_FRINDEX_MSK (((1U << USB_FRINDEX_LEN) - 1) << USB_FRINDEX_POS) -#define USB_FRINDEX_UMSK (~(((1U << USB_FRINDEX_LEN) - 1) << USB_FRINDEX_POS)) - -/* 0x024 : PERIODICLISTBASE */ -#define USB_PERIODICLISTBASE_OFFSET (0x024) -#define USB_PERI_BASADR USB_PERI_BASADR -#define USB_PERI_BASADR_POS (12U) -#define USB_PERI_BASADR_LEN (20U) -#define USB_PERI_BASADR_MSK (((1U << USB_PERI_BASADR_LEN) - 1) << USB_PERI_BASADR_POS) -#define USB_PERI_BASADR_UMSK (~(((1U << USB_PERI_BASADR_LEN) - 1) << USB_PERI_BASADR_POS)) - -/* 0x028 : ASYNCLISTADDR */ -#define USB_ASYNCLISTADDR_OFFSET (0x028) -#define USB_ASYNC_LADR USB_ASYNC_LADR -#define USB_ASYNC_LADR_POS (5U) -#define USB_ASYNC_LADR_LEN (27U) -#define USB_ASYNC_LADR_MSK (((1U << USB_ASYNC_LADR_LEN) - 1) << USB_ASYNC_LADR_POS) -#define USB_ASYNC_LADR_UMSK (~(((1U << USB_ASYNC_LADR_LEN) - 1) << USB_ASYNC_LADR_POS)) - -/* 0x030 : PORTSC */ -#define USB_PORTSC_OFFSET (0x030) -#define USB_CONN_STS USB_CONN_STS -#define USB_CONN_STS_POS (0U) -#define USB_CONN_STS_LEN (1U) -#define USB_CONN_STS_MSK (((1U << USB_CONN_STS_LEN) - 1) << USB_CONN_STS_POS) -#define USB_CONN_STS_UMSK (~(((1U << USB_CONN_STS_LEN) - 1) << USB_CONN_STS_POS)) -#define USB_CONN_CHG USB_CONN_CHG -#define USB_CONN_CHG_POS (1U) -#define USB_CONN_CHG_LEN (1U) -#define USB_CONN_CHG_MSK (((1U << USB_CONN_CHG_LEN) - 1) << USB_CONN_CHG_POS) -#define USB_CONN_CHG_UMSK (~(((1U << USB_CONN_CHG_LEN) - 1) << USB_CONN_CHG_POS)) -#define USB_PO_EN USB_PO_EN -#define USB_PO_EN_POS (2U) -#define USB_PO_EN_LEN (1U) -#define USB_PO_EN_MSK (((1U << USB_PO_EN_LEN) - 1) << USB_PO_EN_POS) -#define USB_PO_EN_UMSK (~(((1U << USB_PO_EN_LEN) - 1) << USB_PO_EN_POS)) -#define USB_PO_EN_CHG USB_PO_EN_CHG -#define USB_PO_EN_CHG_POS (3U) -#define USB_PO_EN_CHG_LEN (1U) -#define USB_PO_EN_CHG_MSK (((1U << USB_PO_EN_CHG_LEN) - 1) << USB_PO_EN_CHG_POS) -#define USB_PO_EN_CHG_UMSK (~(((1U << USB_PO_EN_CHG_LEN) - 1) << USB_PO_EN_CHG_POS)) -#define USB_F_PO_RESM USB_F_PO_RESM -#define USB_F_PO_RESM_POS (6U) -#define USB_F_PO_RESM_LEN (1U) -#define USB_F_PO_RESM_MSK (((1U << USB_F_PO_RESM_LEN) - 1) << USB_F_PO_RESM_POS) -#define USB_F_PO_RESM_UMSK (~(((1U << USB_F_PO_RESM_LEN) - 1) << USB_F_PO_RESM_POS)) -#define USB_PO_SUSP USB_PO_SUSP -#define USB_PO_SUSP_POS (7U) -#define USB_PO_SUSP_LEN (1U) -#define USB_PO_SUSP_MSK (((1U << USB_PO_SUSP_LEN) - 1) << USB_PO_SUSP_POS) -#define USB_PO_SUSP_UMSK (~(((1U << USB_PO_SUSP_LEN) - 1) << USB_PO_SUSP_POS)) -#define USB_PO_RESET USB_PO_RESET -#define USB_PO_RESET_POS (8U) -#define USB_PO_RESET_LEN (1U) -#define USB_PO_RESET_MSK (((1U << USB_PO_RESET_LEN) - 1) << USB_PO_RESET_POS) -#define USB_PO_RESET_UMSK (~(((1U << USB_PO_RESET_LEN) - 1) << USB_PO_RESET_POS)) -#define USB_LINE_STS USB_LINE_STS -#define USB_LINE_STS_POS (10U) -#define USB_LINE_STS_LEN (2U) -#define USB_LINE_STS_MSK (((1U << USB_LINE_STS_LEN) - 1) << USB_LINE_STS_POS) -#define USB_LINE_STS_UMSK (~(((1U << USB_LINE_STS_LEN) - 1) << USB_LINE_STS_POS)) -#define USB_PORT_TEST USB_PORT_TEST -#define USB_PORT_TEST_POS (16U) -#define USB_PORT_TEST_LEN (4U) -#define USB_PORT_TEST_MSK (((1U << USB_PORT_TEST_LEN) - 1) << USB_PORT_TEST_POS) -#define USB_PORT_TEST_UMSK (~(((1U << USB_PORT_TEST_LEN) - 1) << USB_PORT_TEST_POS)) -#define USB_HC_TST_PKDONE USB_HC_TST_PKDONE -#define USB_HC_TST_PKDONE_POS (20U) -#define USB_HC_TST_PKDONE_LEN (1U) -#define USB_HC_TST_PKDONE_MSK (((1U << USB_HC_TST_PKDONE_LEN) - 1) << USB_HC_TST_PKDONE_POS) -#define USB_HC_TST_PKDONE_UMSK (~(((1U << USB_HC_TST_PKDONE_LEN) - 1) << USB_HC_TST_PKDONE_POS)) - -/* 0x040 : HCMISC */ -#define USB_HCMISC_OFFSET (0x040) -#define USB_ASYN_SCH_SLPT USB_ASYN_SCH_SLPT -#define USB_ASYN_SCH_SLPT_POS (0U) -#define USB_ASYN_SCH_SLPT_LEN (2U) -#define USB_ASYN_SCH_SLPT_MSK (((1U << USB_ASYN_SCH_SLPT_LEN) - 1) << USB_ASYN_SCH_SLPT_POS) -#define USB_ASYN_SCH_SLPT_UMSK (~(((1U << USB_ASYN_SCH_SLPT_LEN) - 1) << USB_ASYN_SCH_SLPT_POS)) -#define USB_EOF1_TIME USB_EOF1_TIME -#define USB_EOF1_TIME_POS (2U) -#define USB_EOF1_TIME_LEN (2U) -#define USB_EOF1_TIME_MSK (((1U << USB_EOF1_TIME_LEN) - 1) << USB_EOF1_TIME_POS) -#define USB_EOF1_TIME_UMSK (~(((1U << USB_EOF1_TIME_LEN) - 1) << USB_EOF1_TIME_POS)) -#define USB_EOF2_TIME USB_EOF2_TIME -#define USB_EOF2_TIME_POS (4U) -#define USB_EOF2_TIME_LEN (2U) -#define USB_EOF2_TIME_MSK (((1U << USB_EOF2_TIME_LEN) - 1) << USB_EOF2_TIME_POS) -#define USB_EOF2_TIME_UMSK (~(((1U << USB_EOF2_TIME_LEN) - 1) << USB_EOF2_TIME_POS)) -#define USB_HOSTPHY_SUSPEND USB_HOSTPHY_SUSPEND -#define USB_HOSTPHY_SUSPEND_POS (6U) -#define USB_HOSTPHY_SUSPEND_LEN (1U) -#define USB_HOSTPHY_SUSPEND_MSK (((1U << USB_HOSTPHY_SUSPEND_LEN) - 1) << USB_HOSTPHY_SUSPEND_POS) -#define USB_HOSTPHY_SUSPEND_UMSK (~(((1U << USB_HOSTPHY_SUSPEND_LEN) - 1) << USB_HOSTPHY_SUSPEND_POS)) -#define USB_HC_WKP_DET_EN USB_HC_WKP_DET_EN -#define USB_HC_WKP_DET_EN_POS (8U) -#define USB_HC_WKP_DET_EN_LEN (1U) -#define USB_HC_WKP_DET_EN_MSK (((1U << USB_HC_WKP_DET_EN_LEN) - 1) << USB_HC_WKP_DET_EN_POS) -#define USB_HC_WKP_DET_EN_UMSK (~(((1U << USB_HC_WKP_DET_EN_LEN) - 1) << USB_HC_WKP_DET_EN_POS)) -#define USB_HC_CONN_DET_EN USB_HC_CONN_DET_EN -#define USB_HC_CONN_DET_EN_POS (9U) -#define USB_HC_CONN_DET_EN_LEN (1U) -#define USB_HC_CONN_DET_EN_MSK (((1U << USB_HC_CONN_DET_EN_LEN) - 1) << USB_HC_CONN_DET_EN_POS) -#define USB_HC_CONN_DET_EN_UMSK (~(((1U << USB_HC_CONN_DET_EN_LEN) - 1) << USB_HC_CONN_DET_EN_POS)) - -/* 0x044 : FS_EOF */ -#define USB_FS_EOF_OFFSET (0x044) -#define USB_FS_EOF1_TIME USB_FS_EOF1_TIME -#define USB_FS_EOF1_TIME_POS (0U) -#define USB_FS_EOF1_TIME_LEN (12U) -#define USB_FS_EOF1_TIME_MSK (((1U << USB_FS_EOF1_TIME_LEN) - 1) << USB_FS_EOF1_TIME_POS) -#define USB_FS_EOF1_TIME_UMSK (~(((1U << USB_FS_EOF1_TIME_LEN) - 1) << USB_FS_EOF1_TIME_POS)) -#define USB_FS_EOF1_TIME_125US USB_FS_EOF1_TIME_125US -#define USB_FS_EOF1_TIME_125US_POS (12U) -#define USB_FS_EOF1_TIME_125US_LEN (3U) -#define USB_FS_EOF1_TIME_125US_MSK (((1U << USB_FS_EOF1_TIME_125US_LEN) - 1) << USB_FS_EOF1_TIME_125US_POS) -#define USB_FS_EOF1_TIME_125US_UMSK (~(((1U << USB_FS_EOF1_TIME_125US_LEN) - 1) << USB_FS_EOF1_TIME_125US_POS)) -#define USB_ITDDMASM USB_ITDDMASM -#define USB_ITDDMASM_POS (16U) -#define USB_ITDDMASM_LEN (4U) -#define USB_ITDDMASM_MSK (((1U << USB_ITDDMASM_LEN) - 1) << USB_ITDDMASM_POS) -#define USB_ITDDMASM_UMSK (~(((1U << USB_ITDDMASM_LEN) - 1) << USB_ITDDMASM_POS)) -#define USB_ITDTRAVSM USB_ITDTRAVSM -#define USB_ITDTRAVSM_POS (20U) -#define USB_ITDTRAVSM_LEN (2U) -#define USB_ITDTRAVSM_MSK (((1U << USB_ITDTRAVSM_LEN) - 1) << USB_ITDTRAVSM_POS) -#define USB_ITDTRAVSM_UMSK (~(((1U << USB_ITDTRAVSM_LEN) - 1) << USB_ITDTRAVSM_POS)) -#define USB_DMADMSM USB_DMADMSM -#define USB_DMADMSM_POS (22U) -#define USB_DMADMSM_LEN (4U) -#define USB_DMADMSM_MSK (((1U << USB_DMADMSM_LEN) - 1) << USB_DMADMSM_POS) -#define USB_DMADMSM_UMSK (~(((1U << USB_DMADMSM_LEN) - 1) << USB_DMADMSM_POS)) -#define USB_QHTTRSM USB_QHTTRSM -#define USB_QHTTRSM_POS (26U) -#define USB_QHTTRSM_LEN (3U) -#define USB_QHTTRSM_MSK (((1U << USB_QHTTRSM_LEN) - 1) << USB_QHTTRSM_POS) -#define USB_QHTTRSM_UMSK (~(((1U << USB_QHTTRSM_LEN) - 1) << USB_QHTTRSM_POS)) -#define USB_QHTRAVSM USB_QHTRAVSM -#define USB_QHTRAVSM_POS (29U) -#define USB_QHTRAVSM_LEN (3U) -#define USB_QHTRAVSM_MSK (((1U << USB_QHTRAVSM_LEN) - 1) << USB_QHTRAVSM_POS) -#define USB_QHTRAVSM_UMSK (~(((1U << USB_QHTRAVSM_LEN) - 1) << USB_QHTRAVSM_POS)) - -/* 0x048 : HS_EOF */ -#define USB_HS_EOF_OFFSET (0x048) -#define USB_HS_EOF1_TIME USB_HS_EOF1_TIME -#define USB_HS_EOF1_TIME_POS (0U) -#define USB_HS_EOF1_TIME_LEN (12U) -#define USB_HS_EOF1_TIME_MSK (((1U << USB_HS_EOF1_TIME_LEN) - 1) << USB_HS_EOF1_TIME_POS) -#define USB_HS_EOF1_TIME_UMSK (~(((1U << USB_HS_EOF1_TIME_LEN) - 1) << USB_HS_EOF1_TIME_POS)) -#define USB_SITDDMASM USB_SITDDMASM -#define USB_SITDDMASM_POS (16U) -#define USB_SITDDMASM_LEN (4U) -#define USB_SITDDMASM_MSK (((1U << USB_SITDDMASM_LEN) - 1) << USB_SITDDMASM_POS) -#define USB_SITDDMASM_UMSK (~(((1U << USB_SITDDMASM_LEN) - 1) << USB_SITDDMASM_POS)) -#define USB_SITDTRAVSM USB_SITDTRAVSM -#define USB_SITDTRAVSM_POS (20U) -#define USB_SITDTRAVSM_LEN (2U) -#define USB_SITDTRAVSM_MSK (((1U << USB_SITDTRAVSM_LEN) - 1) << USB_SITDTRAVSM_POS) -#define USB_SITDTRAVSM_UMSK (~(((1U << USB_SITDTRAVSM_LEN) - 1) << USB_SITDTRAVSM_POS)) - -/* 0x080 : OTG_CSR */ -#define USB_OTG_CSR_OFFSET (0x080) -#define USB_B_BUS_REQ USB_B_BUS_REQ -#define USB_B_BUS_REQ_POS (0U) -#define USB_B_BUS_REQ_LEN (1U) -#define USB_B_BUS_REQ_MSK (((1U << USB_B_BUS_REQ_LEN) - 1) << USB_B_BUS_REQ_POS) -#define USB_B_BUS_REQ_UMSK (~(((1U << USB_B_BUS_REQ_LEN) - 1) << USB_B_BUS_REQ_POS)) -#define USB_B_HNP_EN USB_B_HNP_EN -#define USB_B_HNP_EN_POS (1U) -#define USB_B_HNP_EN_LEN (1U) -#define USB_B_HNP_EN_MSK (((1U << USB_B_HNP_EN_LEN) - 1) << USB_B_HNP_EN_POS) -#define USB_B_HNP_EN_UMSK (~(((1U << USB_B_HNP_EN_LEN) - 1) << USB_B_HNP_EN_POS)) -#define USB_B_DSCHRG_VBUS USB_B_DSCHRG_VBUS -#define USB_B_DSCHRG_VBUS_POS (2U) -#define USB_B_DSCHRG_VBUS_LEN (1U) -#define USB_B_DSCHRG_VBUS_MSK (((1U << USB_B_DSCHRG_VBUS_LEN) - 1) << USB_B_DSCHRG_VBUS_POS) -#define USB_B_DSCHRG_VBUS_UMSK (~(((1U << USB_B_DSCHRG_VBUS_LEN) - 1) << USB_B_DSCHRG_VBUS_POS)) -#define USB_A_BUS_REQ_HOV USB_A_BUS_REQ_HOV -#define USB_A_BUS_REQ_HOV_POS (4U) -#define USB_A_BUS_REQ_HOV_LEN (1U) -#define USB_A_BUS_REQ_HOV_MSK (((1U << USB_A_BUS_REQ_HOV_LEN) - 1) << USB_A_BUS_REQ_HOV_POS) -#define USB_A_BUS_REQ_HOV_UMSK (~(((1U << USB_A_BUS_REQ_HOV_LEN) - 1) << USB_A_BUS_REQ_HOV_POS)) -#define USB_A_BUS_DROP_HOV USB_A_BUS_DROP_HOV -#define USB_A_BUS_DROP_HOV_POS (5U) -#define USB_A_BUS_DROP_HOV_LEN (1U) -#define USB_A_BUS_DROP_HOV_MSK (((1U << USB_A_BUS_DROP_HOV_LEN) - 1) << USB_A_BUS_DROP_HOV_POS) -#define USB_A_BUS_DROP_HOV_UMSK (~(((1U << USB_A_BUS_DROP_HOV_LEN) - 1) << USB_A_BUS_DROP_HOV_POS)) -#define USB_A_SET_B_HNP_EN USB_A_SET_B_HNP_EN -#define USB_A_SET_B_HNP_EN_POS (6U) -#define USB_A_SET_B_HNP_EN_LEN (1U) -#define USB_A_SET_B_HNP_EN_MSK (((1U << USB_A_SET_B_HNP_EN_LEN) - 1) << USB_A_SET_B_HNP_EN_POS) -#define USB_A_SET_B_HNP_EN_UMSK (~(((1U << USB_A_SET_B_HNP_EN_LEN) - 1) << USB_A_SET_B_HNP_EN_POS)) -#define USB_A_SRP_DET_EN USB_A_SRP_DET_EN -#define USB_A_SRP_DET_EN_POS (7U) -#define USB_A_SRP_DET_EN_LEN (1U) -#define USB_A_SRP_DET_EN_MSK (((1U << USB_A_SRP_DET_EN_LEN) - 1) << USB_A_SRP_DET_EN_POS) -#define USB_A_SRP_DET_EN_UMSK (~(((1U << USB_A_SRP_DET_EN_LEN) - 1) << USB_A_SRP_DET_EN_POS)) -#define USB_A_SRP_RESP_TYP USB_A_SRP_RESP_TYP -#define USB_A_SRP_RESP_TYP_POS (8U) -#define USB_A_SRP_RESP_TYP_LEN (1U) -#define USB_A_SRP_RESP_TYP_MSK (((1U << USB_A_SRP_RESP_TYP_LEN) - 1) << USB_A_SRP_RESP_TYP_POS) -#define USB_A_SRP_RESP_TYP_UMSK (~(((1U << USB_A_SRP_RESP_TYP_LEN) - 1) << USB_A_SRP_RESP_TYP_POS)) -#define USB_ID_FLT_SEL USB_ID_FLT_SEL -#define USB_ID_FLT_SEL_POS (9U) -#define USB_ID_FLT_SEL_LEN (1U) -#define USB_ID_FLT_SEL_MSK (((1U << USB_ID_FLT_SEL_LEN) - 1) << USB_ID_FLT_SEL_POS) -#define USB_ID_FLT_SEL_UMSK (~(((1U << USB_ID_FLT_SEL_LEN) - 1) << USB_ID_FLT_SEL_POS)) -#define USB_VBUS_FLT_SEL_HOV_POV USB_VBUS_FLT_SEL_HOV_POV -#define USB_VBUS_FLT_SEL_HOV_POV_POS (10U) -#define USB_VBUS_FLT_SEL_HOV_POV_LEN (1U) -#define USB_VBUS_FLT_SEL_HOV_POV_MSK (((1U << USB_VBUS_FLT_SEL_HOV_POV_LEN) - 1) << USB_VBUS_FLT_SEL_HOV_POV_POS) -#define USB_VBUS_FLT_SEL_HOV_POV_UMSK (~(((1U << USB_VBUS_FLT_SEL_HOV_POV_LEN) - 1) << USB_VBUS_FLT_SEL_HOV_POV_POS)) -#define USB_HDISCON_FLT_SEL_HOV USB_HDISCON_FLT_SEL_HOV -#define USB_HDISCON_FLT_SEL_HOV_POS (11U) -#define USB_HDISCON_FLT_SEL_HOV_LEN (1U) -#define USB_HDISCON_FLT_SEL_HOV_MSK (((1U << USB_HDISCON_FLT_SEL_HOV_LEN) - 1) << USB_HDISCON_FLT_SEL_HOV_POS) -#define USB_HDISCON_FLT_SEL_HOV_UMSK (~(((1U << USB_HDISCON_FLT_SEL_HOV_LEN) - 1) << USB_HDISCON_FLT_SEL_HOV_POS)) -#define USB_IDPULUP_HOV_POV USB_IDPULUP_HOV_POV -#define USB_IDPULUP_HOV_POV_POS (13U) -#define USB_IDPULUP_HOV_POV_LEN (1U) -#define USB_IDPULUP_HOV_POV_MSK (((1U << USB_IDPULUP_HOV_POV_LEN) - 1) << USB_IDPULUP_HOV_POV_POS) -#define USB_IDPULUP_HOV_POV_UMSK (~(((1U << USB_IDPULUP_HOV_POV_LEN) - 1) << USB_IDPULUP_HOV_POV_POS)) -#define USB_B_SESS_END_POV USB_B_SESS_END_POV -#define USB_B_SESS_END_POV_POS (16U) -#define USB_B_SESS_END_POV_LEN (1U) -#define USB_B_SESS_END_POV_MSK (((1U << USB_B_SESS_END_POV_LEN) - 1) << USB_B_SESS_END_POV_POS) -#define USB_B_SESS_END_POV_UMSK (~(((1U << USB_B_SESS_END_POV_LEN) - 1) << USB_B_SESS_END_POV_POS)) -#define USB_B_SESS_VLD_POV USB_B_SESS_VLD_POV -#define USB_B_SESS_VLD_POV_POS (17U) -#define USB_B_SESS_VLD_POV_LEN (1U) -#define USB_B_SESS_VLD_POV_MSK (((1U << USB_B_SESS_VLD_POV_LEN) - 1) << USB_B_SESS_VLD_POV_POS) -#define USB_B_SESS_VLD_POV_UMSK (~(((1U << USB_B_SESS_VLD_POV_LEN) - 1) << USB_B_SESS_VLD_POV_POS)) -#define USB_A_SESS_VLD USB_A_SESS_VLD -#define USB_A_SESS_VLD_POS (18U) -#define USB_A_SESS_VLD_LEN (1U) -#define USB_A_SESS_VLD_MSK (((1U << USB_A_SESS_VLD_LEN) - 1) << USB_A_SESS_VLD_POS) -#define USB_A_SESS_VLD_UMSK (~(((1U << USB_A_SESS_VLD_LEN) - 1) << USB_A_SESS_VLD_POS)) -#define USB_VBUS_VLD_HOV USB_VBUS_VLD_HOV -#define USB_VBUS_VLD_HOV_POS (19U) -#define USB_VBUS_VLD_HOV_LEN (1U) -#define USB_VBUS_VLD_HOV_MSK (((1U << USB_VBUS_VLD_HOV_LEN) - 1) << USB_VBUS_VLD_HOV_POS) -#define USB_VBUS_VLD_HOV_UMSK (~(((1U << USB_VBUS_VLD_HOV_LEN) - 1) << USB_VBUS_VLD_HOV_POS)) -#define USB_CROLE_HOV_POV USB_CROLE_HOV_POV -#define USB_CROLE_HOV_POV_POS (20U) -#define USB_CROLE_HOV_POV_LEN (1U) -#define USB_CROLE_HOV_POV_MSK (((1U << USB_CROLE_HOV_POV_LEN) - 1) << USB_CROLE_HOV_POV_POS) -#define USB_CROLE_HOV_POV_UMSK (~(((1U << USB_CROLE_HOV_POV_LEN) - 1) << USB_CROLE_HOV_POV_POS)) -#define USB_ID_HOV_POV USB_ID_HOV_POV -#define USB_ID_HOV_POV_POS (21U) -#define USB_ID_HOV_POV_LEN (1U) -#define USB_ID_HOV_POV_MSK (((1U << USB_ID_HOV_POV_LEN) - 1) << USB_ID_HOV_POV_POS) -#define USB_ID_HOV_POV_UMSK (~(((1U << USB_ID_HOV_POV_LEN) - 1) << USB_ID_HOV_POV_POS)) -#define USB_SPD_TYP_HOV_POV USB_SPD_TYP_HOV_POV -#define USB_SPD_TYP_HOV_POV_POS (22U) -#define USB_SPD_TYP_HOV_POV_LEN (2U) -#define USB_SPD_TYP_HOV_POV_MSK (((1U << USB_SPD_TYP_HOV_POV_LEN) - 1) << USB_SPD_TYP_HOV_POV_POS) -#define USB_SPD_TYP_HOV_POV_UMSK (~(((1U << USB_SPD_TYP_HOV_POV_LEN) - 1) << USB_SPD_TYP_HOV_POV_POS)) - -/* 0x084 : OTG_ISR */ -#define USB_OTG_ISR_OFFSET (0x084) -#define USB_B_SRP_DN USB_B_SRP_DN -#define USB_B_SRP_DN_POS (0U) -#define USB_B_SRP_DN_LEN (1U) -#define USB_B_SRP_DN_MSK (((1U << USB_B_SRP_DN_LEN) - 1) << USB_B_SRP_DN_POS) -#define USB_B_SRP_DN_UMSK (~(((1U << USB_B_SRP_DN_LEN) - 1) << USB_B_SRP_DN_POS)) -#define USB_A_SRP_DET USB_A_SRP_DET -#define USB_A_SRP_DET_POS (4U) -#define USB_A_SRP_DET_LEN (1U) -#define USB_A_SRP_DET_MSK (((1U << USB_A_SRP_DET_LEN) - 1) << USB_A_SRP_DET_POS) -#define USB_A_SRP_DET_UMSK (~(((1U << USB_A_SRP_DET_LEN) - 1) << USB_A_SRP_DET_POS)) -#define USB_A_VBUS_ERR_HOV USB_A_VBUS_ERR_HOV -#define USB_A_VBUS_ERR_HOV_POS (5U) -#define USB_A_VBUS_ERR_HOV_LEN (1U) -#define USB_A_VBUS_ERR_HOV_MSK (((1U << USB_A_VBUS_ERR_HOV_LEN) - 1) << USB_A_VBUS_ERR_HOV_POS) -#define USB_A_VBUS_ERR_HOV_UMSK (~(((1U << USB_A_VBUS_ERR_HOV_LEN) - 1) << USB_A_VBUS_ERR_HOV_POS)) -#define USB_B_SESS_END_INT_POV USB_B_SESS_END_INT_POV -#define USB_B_SESS_END_INT_POV_POS (6U) -#define USB_B_SESS_END_INT_POV_LEN (1U) -#define USB_B_SESS_END_INT_POV_MSK (((1U << USB_B_SESS_END_INT_POV_LEN) - 1) << USB_B_SESS_END_INT_POV_POS) -#define USB_B_SESS_END_INT_POV_UMSK (~(((1U << USB_B_SESS_END_INT_POV_LEN) - 1) << USB_B_SESS_END_INT_POV_POS)) -#define USB_RLCHG USB_RLCHG -#define USB_RLCHG_POS (8U) -#define USB_RLCHG_LEN (1U) -#define USB_RLCHG_MSK (((1U << USB_RLCHG_LEN) - 1) << USB_RLCHG_POS) -#define USB_RLCHG_UMSK (~(((1U << USB_RLCHG_LEN) - 1) << USB_RLCHG_POS)) -#define USB_IDCHG USB_IDCHG -#define USB_IDCHG_POS (9U) -#define USB_IDCHG_LEN (1U) -#define USB_IDCHG_MSK (((1U << USB_IDCHG_LEN) - 1) << USB_IDCHG_POS) -#define USB_IDCHG_UMSK (~(((1U << USB_IDCHG_LEN) - 1) << USB_IDCHG_POS)) -#define USB_OVC_HOV USB_OVC_HOV -#define USB_OVC_HOV_POS (10U) -#define USB_OVC_HOV_LEN (1U) -#define USB_OVC_HOV_MSK (((1U << USB_OVC_HOV_LEN) - 1) << USB_OVC_HOV_POS) -#define USB_OVC_HOV_UMSK (~(((1U << USB_OVC_HOV_LEN) - 1) << USB_OVC_HOV_POS)) -#define USB_A_WAIT_CON_HOV USB_A_WAIT_CON_HOV -#define USB_A_WAIT_CON_HOV_POS (11U) -#define USB_A_WAIT_CON_HOV_LEN (1U) -#define USB_A_WAIT_CON_HOV_MSK (((1U << USB_A_WAIT_CON_HOV_LEN) - 1) << USB_A_WAIT_CON_HOV_POS) -#define USB_A_WAIT_CON_HOV_UMSK (~(((1U << USB_A_WAIT_CON_HOV_LEN) - 1) << USB_A_WAIT_CON_HOV_POS)) -#define USB_APLGRMV USB_APLGRMV -#define USB_APLGRMV_POS (12U) -#define USB_APLGRMV_LEN (1U) -#define USB_APLGRMV_MSK (((1U << USB_APLGRMV_LEN) - 1) << USB_APLGRMV_POS) -#define USB_APLGRMV_UMSK (~(((1U << USB_APLGRMV_LEN) - 1) << USB_APLGRMV_POS)) - -/* 0x088 : OTG_IER */ -#define USB_OTG_IER_OFFSET (0x088) -#define USB_B_SRP_DN_EN USB_B_SRP_DN_EN -#define USB_B_SRP_DN_EN_POS (0U) -#define USB_B_SRP_DN_EN_LEN (1U) -#define USB_B_SRP_DN_EN_MSK (((1U << USB_B_SRP_DN_EN_LEN) - 1) << USB_B_SRP_DN_EN_POS) -#define USB_B_SRP_DN_EN_UMSK (~(((1U << USB_B_SRP_DN_EN_LEN) - 1) << USB_B_SRP_DN_EN_POS)) -#define USB_A_SRP_DET_INT_EN USB_A_SRP_DET_INT_EN -#define USB_A_SRP_DET_INT_EN_POS (4U) -#define USB_A_SRP_DET_INT_EN_LEN (1U) -#define USB_A_SRP_DET_INT_EN_MSK (((1U << USB_A_SRP_DET_INT_EN_LEN) - 1) << USB_A_SRP_DET_INT_EN_POS) -#define USB_A_SRP_DET_INT_EN_UMSK (~(((1U << USB_A_SRP_DET_INT_EN_LEN) - 1) << USB_A_SRP_DET_INT_EN_POS)) -#define USB_A_VBUS_ERR_EN_HOV USB_A_VBUS_ERR_EN_HOV -#define USB_A_VBUS_ERR_EN_HOV_POS (5U) -#define USB_A_VBUS_ERR_EN_HOV_LEN (1U) -#define USB_A_VBUS_ERR_EN_HOV_MSK (((1U << USB_A_VBUS_ERR_EN_HOV_LEN) - 1) << USB_A_VBUS_ERR_EN_HOV_POS) -#define USB_A_VBUS_ERR_EN_HOV_UMSK (~(((1U << USB_A_VBUS_ERR_EN_HOV_LEN) - 1) << USB_A_VBUS_ERR_EN_HOV_POS)) -#define USB_B_SESS_END_EN_POV USB_B_SESS_END_EN_POV -#define USB_B_SESS_END_EN_POV_POS (6U) -#define USB_B_SESS_END_EN_POV_LEN (1U) -#define USB_B_SESS_END_EN_POV_MSK (((1U << USB_B_SESS_END_EN_POV_LEN) - 1) << USB_B_SESS_END_EN_POV_POS) -#define USB_B_SESS_END_EN_POV_UMSK (~(((1U << USB_B_SESS_END_EN_POV_LEN) - 1) << USB_B_SESS_END_EN_POV_POS)) -#define USB_RLCHG_EN USB_RLCHG_EN -#define USB_RLCHG_EN_POS (8U) -#define USB_RLCHG_EN_LEN (1U) -#define USB_RLCHG_EN_MSK (((1U << USB_RLCHG_EN_LEN) - 1) << USB_RLCHG_EN_POS) -#define USB_RLCHG_EN_UMSK (~(((1U << USB_RLCHG_EN_LEN) - 1) << USB_RLCHG_EN_POS)) -#define USB_IDCHG_EN USB_IDCHG_EN -#define USB_IDCHG_EN_POS (9U) -#define USB_IDCHG_EN_LEN (1U) -#define USB_IDCHG_EN_MSK (((1U << USB_IDCHG_EN_LEN) - 1) << USB_IDCHG_EN_POS) -#define USB_IDCHG_EN_UMSK (~(((1U << USB_IDCHG_EN_LEN) - 1) << USB_IDCHG_EN_POS)) -#define USB_OVC_EN_HOV USB_OVC_EN_HOV -#define USB_OVC_EN_HOV_POS (10U) -#define USB_OVC_EN_HOV_LEN (1U) -#define USB_OVC_EN_HOV_MSK (((1U << USB_OVC_EN_HOV_LEN) - 1) << USB_OVC_EN_HOV_POS) -#define USB_OVC_EN_HOV_UMSK (~(((1U << USB_OVC_EN_HOV_LEN) - 1) << USB_OVC_EN_HOV_POS)) -#define USB_A_WAIT_CON_EN_HOV USB_A_WAIT_CON_EN_HOV -#define USB_A_WAIT_CON_EN_HOV_POS (11U) -#define USB_A_WAIT_CON_EN_HOV_LEN (1U) -#define USB_A_WAIT_CON_EN_HOV_MSK (((1U << USB_A_WAIT_CON_EN_HOV_LEN) - 1) << USB_A_WAIT_CON_EN_HOV_POS) -#define USB_A_WAIT_CON_EN_HOV_UMSK (~(((1U << USB_A_WAIT_CON_EN_HOV_LEN) - 1) << USB_A_WAIT_CON_EN_HOV_POS)) -#define USB_APLGRMV_EN USB_APLGRMV_EN -#define USB_APLGRMV_EN_POS (12U) -#define USB_APLGRMV_EN_LEN (1U) -#define USB_APLGRMV_EN_MSK (((1U << USB_APLGRMV_EN_LEN) - 1) << USB_APLGRMV_EN_POS) -#define USB_APLGRMV_EN_UMSK (~(((1U << USB_APLGRMV_EN_LEN) - 1) << USB_APLGRMV_EN_POS)) - -/* 0x0C0 : GLB_ISR */ -#define USB_GLB_ISR_OFFSET (0x0C0) -#define USB_DEV_INT USB_DEV_INT -#define USB_DEV_INT_POS (0U) -#define USB_DEV_INT_LEN (1U) -#define USB_DEV_INT_MSK (((1U << USB_DEV_INT_LEN) - 1) << USB_DEV_INT_POS) -#define USB_DEV_INT_UMSK (~(((1U << USB_DEV_INT_LEN) - 1) << USB_DEV_INT_POS)) -#define USB_OTG_INT USB_OTG_INT -#define USB_OTG_INT_POS (1U) -#define USB_OTG_INT_LEN (1U) -#define USB_OTG_INT_MSK (((1U << USB_OTG_INT_LEN) - 1) << USB_OTG_INT_POS) -#define USB_OTG_INT_UMSK (~(((1U << USB_OTG_INT_LEN) - 1) << USB_OTG_INT_POS)) -#define USB_HC_INT USB_HC_INT -#define USB_HC_INT_POS (2U) -#define USB_HC_INT_LEN (1U) -#define USB_HC_INT_MSK (((1U << USB_HC_INT_LEN) - 1) << USB_HC_INT_POS) -#define USB_HC_INT_UMSK (~(((1U << USB_HC_INT_LEN) - 1) << USB_HC_INT_POS)) - -/* 0x0C4 : GLB_INT */ -#define USB_GLB_INT_OFFSET (0x0C4) -#define USB_MDEV_INT USB_MDEV_INT -#define USB_MDEV_INT_POS (0U) -#define USB_MDEV_INT_LEN (1U) -#define USB_MDEV_INT_MSK (((1U << USB_MDEV_INT_LEN) - 1) << USB_MDEV_INT_POS) -#define USB_MDEV_INT_UMSK (~(((1U << USB_MDEV_INT_LEN) - 1) << USB_MDEV_INT_POS)) -#define USB_MOTG_INT USB_MOTG_INT -#define USB_MOTG_INT_POS (1U) -#define USB_MOTG_INT_LEN (1U) -#define USB_MOTG_INT_MSK (((1U << USB_MOTG_INT_LEN) - 1) << USB_MOTG_INT_POS) -#define USB_MOTG_INT_UMSK (~(((1U << USB_MOTG_INT_LEN) - 1) << USB_MOTG_INT_POS)) -#define USB_MHC_INT USB_MHC_INT -#define USB_MHC_INT_POS (2U) -#define USB_MHC_INT_LEN (1U) -#define USB_MHC_INT_MSK (((1U << USB_MHC_INT_LEN) - 1) << USB_MHC_INT_POS) -#define USB_MHC_INT_UMSK (~(((1U << USB_MHC_INT_LEN) - 1) << USB_MHC_INT_POS)) -#define USB_INT_POLARITY USB_INT_POLARITY -#define USB_INT_POLARITY_POS (3U) -#define USB_INT_POLARITY_LEN (1U) -#define USB_INT_POLARITY_MSK (((1U << USB_INT_POLARITY_LEN) - 1) << USB_INT_POLARITY_POS) -#define USB_INT_POLARITY_UMSK (~(((1U << USB_INT_POLARITY_LEN) - 1) << USB_INT_POLARITY_POS)) - -/* 0x0E0 : REVISION */ -#define USB_REVISION_OFFSET (0x0E0) -#define USB_REVISION USB_REVISION -#define USB_REVISION_POS (0U) -#define USB_REVISION_LEN (32U) -#define USB_REVISION_MSK (((1U << USB_REVISION_LEN) - 1) << USB_REVISION_POS) -#define USB_REVISION_UMSK (~(((1U << USB_REVISION_LEN) - 1) << USB_REVISION_POS)) - -/* 0x0E4 : FEATURE */ -#define USB_FEATURE_OFFSET (0x0E4) -#define USB_DMABUFSIZE USB_DMABUFSIZE -#define USB_DMABUFSIZE_POS (0U) -#define USB_DMABUFSIZE_LEN (5U) -#define USB_DMABUFSIZE_MSK (((1U << USB_DMABUFSIZE_LEN) - 1) << USB_DMABUFSIZE_POS) -#define USB_DMABUFSIZE_UMSK (~(((1U << USB_DMABUFSIZE_LEN) - 1) << USB_DMABUFSIZE_POS)) -#define USB_FIFO_NUM USB_FIFO_NUM -#define USB_FIFO_NUM_POS (5U) -#define USB_FIFO_NUM_LEN (5U) -#define USB_FIFO_NUM_MSK (((1U << USB_FIFO_NUM_LEN) - 1) << USB_FIFO_NUM_POS) -#define USB_FIFO_NUM_UMSK (~(((1U << USB_FIFO_NUM_LEN) - 1) << USB_FIFO_NUM_POS)) -#define USB_EP_NUM USB_EP_NUM -#define USB_EP_NUM_POS (10U) -#define USB_EP_NUM_LEN (5U) -#define USB_EP_NUM_MSK (((1U << USB_EP_NUM_LEN) - 1) << USB_EP_NUM_POS) -#define USB_EP_NUM_UMSK (~(((1U << USB_EP_NUM_LEN) - 1) << USB_EP_NUM_POS)) -#define USB_DEV_ONLY USB_DEV_ONLY -#define USB_DEV_ONLY_POS (15U) -#define USB_DEV_ONLY_LEN (1U) -#define USB_DEV_ONLY_MSK (((1U << USB_DEV_ONLY_LEN) - 1) << USB_DEV_ONLY_POS) -#define USB_DEV_ONLY_UMSK (~(((1U << USB_DEV_ONLY_LEN) - 1) << USB_DEV_ONLY_POS)) -#define USB_HOST_ONLY USB_HOST_ONLY -#define USB_HOST_ONLY_POS (16U) -#define USB_HOST_ONLY_LEN (1U) -#define USB_HOST_ONLY_MSK (((1U << USB_HOST_ONLY_LEN) - 1) << USB_HOST_ONLY_POS) -#define USB_HOST_ONLY_UMSK (~(((1U << USB_HOST_ONLY_LEN) - 1) << USB_HOST_ONLY_POS)) - -/* 0x0E8 : AXI_CR */ -#define USB_AXI_CR_OFFSET (0x0E8) -#define USB_AXI_SGLBST USB_AXI_SGLBST -#define USB_AXI_SGLBST_POS (0U) -#define USB_AXI_SGLBST_LEN (1U) -#define USB_AXI_SGLBST_MSK (((1U << USB_AXI_SGLBST_LEN) - 1) << USB_AXI_SGLBST_POS) -#define USB_AXI_SGLBST_UMSK (~(((1U << USB_AXI_SGLBST_LEN) - 1) << USB_AXI_SGLBST_POS)) - -/* 0x100 : DEV_CTL */ -#define USB_DEV_CTL_OFFSET (0x100) -#define USB_CAP_RMWAKUP USB_CAP_RMWAKUP -#define USB_CAP_RMWAKUP_POS (0U) -#define USB_CAP_RMWAKUP_LEN (1U) -#define USB_CAP_RMWAKUP_MSK (((1U << USB_CAP_RMWAKUP_LEN) - 1) << USB_CAP_RMWAKUP_POS) -#define USB_CAP_RMWAKUP_UMSK (~(((1U << USB_CAP_RMWAKUP_LEN) - 1) << USB_CAP_RMWAKUP_POS)) -#define USB_HALF_SPEED_HOV USB_HALF_SPEED_HOV -#define USB_HALF_SPEED_HOV_POS (1U) -#define USB_HALF_SPEED_HOV_LEN (1U) -#define USB_HALF_SPEED_HOV_MSK (((1U << USB_HALF_SPEED_HOV_LEN) - 1) << USB_HALF_SPEED_HOV_POS) -#define USB_HALF_SPEED_HOV_UMSK (~(((1U << USB_HALF_SPEED_HOV_LEN) - 1) << USB_HALF_SPEED_HOV_POS)) -#define USB_GLINT_EN_HOV USB_GLINT_EN_HOV -#define USB_GLINT_EN_HOV_POS (2U) -#define USB_GLINT_EN_HOV_LEN (1U) -#define USB_GLINT_EN_HOV_MSK (((1U << USB_GLINT_EN_HOV_LEN) - 1) << USB_GLINT_EN_HOV_POS) -#define USB_GLINT_EN_HOV_UMSK (~(((1U << USB_GLINT_EN_HOV_LEN) - 1) << USB_GLINT_EN_HOV_POS)) -#define USB_GOSUSP USB_GOSUSP -#define USB_GOSUSP_POS (3U) -#define USB_GOSUSP_LEN (1U) -#define USB_GOSUSP_MSK (((1U << USB_GOSUSP_LEN) - 1) << USB_GOSUSP_POS) -#define USB_GOSUSP_UMSK (~(((1U << USB_GOSUSP_LEN) - 1) << USB_GOSUSP_POS)) -#define USB_SFRST_HOV USB_SFRST_HOV -#define USB_SFRST_HOV_POS (4U) -#define USB_SFRST_HOV_LEN (1U) -#define USB_SFRST_HOV_MSK (((1U << USB_SFRST_HOV_LEN) - 1) << USB_SFRST_HOV_POS) -#define USB_SFRST_HOV_UMSK (~(((1U << USB_SFRST_HOV_LEN) - 1) << USB_SFRST_HOV_POS)) -#define USB_CHIP_EN_HOV USB_CHIP_EN_HOV -#define USB_CHIP_EN_HOV_POS (5U) -#define USB_CHIP_EN_HOV_LEN (1U) -#define USB_CHIP_EN_HOV_MSK (((1U << USB_CHIP_EN_HOV_LEN) - 1) << USB_CHIP_EN_HOV_POS) -#define USB_CHIP_EN_HOV_UMSK (~(((1U << USB_CHIP_EN_HOV_LEN) - 1) << USB_CHIP_EN_HOV_POS)) -#define USB_HS_EN_HOV USB_HS_EN_HOV -#define USB_HS_EN_HOV_POS (6U) -#define USB_HS_EN_HOV_LEN (1U) -#define USB_HS_EN_HOV_MSK (((1U << USB_HS_EN_HOV_LEN) - 1) << USB_HS_EN_HOV_POS) -#define USB_HS_EN_HOV_UMSK (~(((1U << USB_HS_EN_HOV_LEN) - 1) << USB_HS_EN_HOV_POS)) -#define USB_SYSBUS_WIDTH_HOV USB_SYSBUS_WIDTH_HOV -#define USB_SYSBUS_WIDTH_HOV_POS (7U) -#define USB_SYSBUS_WIDTH_HOV_LEN (1U) -#define USB_SYSBUS_WIDTH_HOV_MSK (((1U << USB_SYSBUS_WIDTH_HOV_LEN) - 1) << USB_SYSBUS_WIDTH_HOV_POS) -#define USB_SYSBUS_WIDTH_HOV_UMSK (~(((1U << USB_SYSBUS_WIDTH_HOV_LEN) - 1) << USB_SYSBUS_WIDTH_HOV_POS)) -#define USB_FORCE_FS USB_FORCE_FS -#define USB_FORCE_FS_POS (9U) -#define USB_FORCE_FS_LEN (1U) -#define USB_FORCE_FS_MSK (((1U << USB_FORCE_FS_LEN) - 1) << USB_FORCE_FS_POS) -#define USB_FORCE_FS_UMSK (~(((1U << USB_FORCE_FS_LEN) - 1) << USB_FORCE_FS_POS)) -#define USB_IDLE_DEGLITCH_HOV USB_IDLE_DEGLITCH_HOV -#define USB_IDLE_DEGLITCH_HOV_POS (10U) -#define USB_IDLE_DEGLITCH_HOV_LEN (2U) -#define USB_IDLE_DEGLITCH_HOV_MSK (((1U << USB_IDLE_DEGLITCH_HOV_LEN) - 1) << USB_IDLE_DEGLITCH_HOV_POS) -#define USB_IDLE_DEGLITCH_HOV_UMSK (~(((1U << USB_IDLE_DEGLITCH_HOV_LEN) - 1) << USB_IDLE_DEGLITCH_HOV_POS)) -#define USB_LPM_BESL_MAX USB_LPM_BESL_MAX -#define USB_LPM_BESL_MAX_POS (12U) -#define USB_LPM_BESL_MAX_LEN (4U) -#define USB_LPM_BESL_MAX_MSK (((1U << USB_LPM_BESL_MAX_LEN) - 1) << USB_LPM_BESL_MAX_POS) -#define USB_LPM_BESL_MAX_UMSK (~(((1U << USB_LPM_BESL_MAX_LEN) - 1) << USB_LPM_BESL_MAX_POS)) -#define USB_LPM_BESL_MIN USB_LPM_BESL_MIN -#define USB_LPM_BESL_MIN_POS (16U) -#define USB_LPM_BESL_MIN_LEN (4U) -#define USB_LPM_BESL_MIN_MSK (((1U << USB_LPM_BESL_MIN_LEN) - 1) << USB_LPM_BESL_MIN_POS) -#define USB_LPM_BESL_MIN_UMSK (~(((1U << USB_LPM_BESL_MIN_LEN) - 1) << USB_LPM_BESL_MIN_POS)) -#define USB_LPM_BESL USB_LPM_BESL -#define USB_LPM_BESL_POS (20U) -#define USB_LPM_BESL_LEN (4U) -#define USB_LPM_BESL_MSK (((1U << USB_LPM_BESL_LEN) - 1) << USB_LPM_BESL_POS) -#define USB_LPM_BESL_UMSK (~(((1U << USB_LPM_BESL_LEN) - 1) << USB_LPM_BESL_POS)) -#define USB_LPM_EN USB_LPM_EN -#define USB_LPM_EN_POS (25U) -#define USB_LPM_EN_LEN (1U) -#define USB_LPM_EN_MSK (((1U << USB_LPM_EN_LEN) - 1) << USB_LPM_EN_POS) -#define USB_LPM_EN_UMSK (~(((1U << USB_LPM_EN_LEN) - 1) << USB_LPM_EN_POS)) -#define USB_LPM_ACCEPT USB_LPM_ACCEPT -#define USB_LPM_ACCEPT_POS (26U) -#define USB_LPM_ACCEPT_LEN (1U) -#define USB_LPM_ACCEPT_MSK (((1U << USB_LPM_ACCEPT_LEN) - 1) << USB_LPM_ACCEPT_POS) -#define USB_LPM_ACCEPT_UMSK (~(((1U << USB_LPM_ACCEPT_LEN) - 1) << USB_LPM_ACCEPT_POS)) - -/* 0x104 : DEV_ADR */ -#define USB_DEV_ADR_OFFSET (0x104) -#define USB_DEVADR USB_DEVADR -#define USB_DEVADR_POS (0U) -#define USB_DEVADR_LEN (7U) -#define USB_DEVADR_MSK (((1U << USB_DEVADR_LEN) - 1) << USB_DEVADR_POS) -#define USB_DEVADR_UMSK (~(((1U << USB_DEVADR_LEN) - 1) << USB_DEVADR_POS)) -#define USB_AFT_CONF USB_AFT_CONF -#define USB_AFT_CONF_POS (7U) -#define USB_AFT_CONF_LEN (1U) -#define USB_AFT_CONF_MSK (((1U << USB_AFT_CONF_LEN) - 1) << USB_AFT_CONF_POS) -#define USB_AFT_CONF_UMSK (~(((1U << USB_AFT_CONF_LEN) - 1) << USB_AFT_CONF_POS)) - -/* 0x108 : DEV_TST */ -#define USB_DEV_TST_OFFSET (0x108) -#define USB_TST_CLRFF_HOV USB_TST_CLRFF_HOV -#define USB_TST_CLRFF_HOV_POS (0U) -#define USB_TST_CLRFF_HOV_LEN (1U) -#define USB_TST_CLRFF_HOV_MSK (((1U << USB_TST_CLRFF_HOV_LEN) - 1) << USB_TST_CLRFF_HOV_POS) -#define USB_TST_CLRFF_HOV_UMSK (~(((1U << USB_TST_CLRFF_HOV_LEN) - 1) << USB_TST_CLRFF_HOV_POS)) -#define USB_TST_LPCX USB_TST_LPCX -#define USB_TST_LPCX_POS (1U) -#define USB_TST_LPCX_LEN (1U) -#define USB_TST_LPCX_MSK (((1U << USB_TST_LPCX_LEN) - 1) << USB_TST_LPCX_POS) -#define USB_TST_LPCX_UMSK (~(((1U << USB_TST_LPCX_LEN) - 1) << USB_TST_LPCX_POS)) -#define USB_TST_CLREA USB_TST_CLREA -#define USB_TST_CLREA_POS (2U) -#define USB_TST_CLREA_LEN (1U) -#define USB_TST_CLREA_MSK (((1U << USB_TST_CLREA_LEN) - 1) << USB_TST_CLREA_POS) -#define USB_TST_CLREA_UMSK (~(((1U << USB_TST_CLREA_LEN) - 1) << USB_TST_CLREA_POS)) -#define USB_TST_DISTO_HOV USB_TST_DISTO_HOV -#define USB_TST_DISTO_HOV_POS (4U) -#define USB_TST_DISTO_HOV_LEN (1U) -#define USB_TST_DISTO_HOV_MSK (((1U << USB_TST_DISTO_HOV_LEN) - 1) << USB_TST_DISTO_HOV_POS) -#define USB_TST_DISTO_HOV_UMSK (~(((1U << USB_TST_DISTO_HOV_LEN) - 1) << USB_TST_DISTO_HOV_POS)) -#define USB_TST_MOD_HOV USB_TST_MOD_HOV -#define USB_TST_MOD_HOV_POS (5U) -#define USB_TST_MOD_HOV_LEN (1U) -#define USB_TST_MOD_HOV_MSK (((1U << USB_TST_MOD_HOV_LEN) - 1) << USB_TST_MOD_HOV_POS) -#define USB_TST_MOD_HOV_UMSK (~(((1U << USB_TST_MOD_HOV_LEN) - 1) << USB_TST_MOD_HOV_POS)) -#define USB_DISGENSOF USB_DISGENSOF -#define USB_DISGENSOF_POS (6U) -#define USB_DISGENSOF_LEN (1U) -#define USB_DISGENSOF_MSK (((1U << USB_DISGENSOF_LEN) - 1) << USB_DISGENSOF_POS) -#define USB_DISGENSOF_UMSK (~(((1U << USB_DISGENSOF_LEN) - 1) << USB_DISGENSOF_POS)) -#define USB_TST_MOD_TYP_HOV USB_TST_MOD_TYP_HOV -#define USB_TST_MOD_TYP_HOV_POS (7U) -#define USB_TST_MOD_TYP_HOV_LEN (1U) -#define USB_TST_MOD_TYP_HOV_MSK (((1U << USB_TST_MOD_TYP_HOV_LEN) - 1) << USB_TST_MOD_TYP_HOV_POS) -#define USB_TST_MOD_TYP_HOV_UMSK (~(((1U << USB_TST_MOD_TYP_HOV_LEN) - 1) << USB_TST_MOD_TYP_HOV_POS)) - -/* 0x10C : DEV_SFN */ -#define USB_DEV_SFN_OFFSET (0x10C) -#define USB_SOFN USB_SOFN -#define USB_SOFN_POS (0U) -#define USB_SOFN_LEN (11U) -#define USB_SOFN_MSK (((1U << USB_SOFN_LEN) - 1) << USB_SOFN_POS) -#define USB_SOFN_UMSK (~(((1U << USB_SOFN_LEN) - 1) << USB_SOFN_POS)) -#define USB_USOFN USB_USOFN -#define USB_USOFN_POS (11U) -#define USB_USOFN_LEN (3U) -#define USB_USOFN_MSK (((1U << USB_USOFN_LEN) - 1) << USB_USOFN_POS) -#define USB_USOFN_UMSK (~(((1U << USB_USOFN_LEN) - 1) << USB_USOFN_POS)) - -/* 0x110 : DEV_SMT */ -#define USB_DEV_SMT_OFFSET (0x110) -#define USB_SOFMT USB_SOFMT -#define USB_SOFMT_POS (0U) -#define USB_SOFMT_LEN (16U) -#define USB_SOFMT_MSK (((1U << USB_SOFMT_LEN) - 1) << USB_SOFMT_POS) -#define USB_SOFMT_UMSK (~(((1U << USB_SOFMT_LEN) - 1) << USB_SOFMT_POS)) - -/* 0x114 : PHY_TST */ -#define USB_PHY_TST_OFFSET (0x114) -#define USB_UNPLUG USB_UNPLUG -#define USB_UNPLUG_POS (0U) -#define USB_UNPLUG_LEN (1U) -#define USB_UNPLUG_MSK (((1U << USB_UNPLUG_LEN) - 1) << USB_UNPLUG_POS) -#define USB_UNPLUG_UMSK (~(((1U << USB_UNPLUG_LEN) - 1) << USB_UNPLUG_POS)) -#define USB_TST_JSTA USB_TST_JSTA -#define USB_TST_JSTA_POS (1U) -#define USB_TST_JSTA_LEN (1U) -#define USB_TST_JSTA_MSK (((1U << USB_TST_JSTA_LEN) - 1) << USB_TST_JSTA_POS) -#define USB_TST_JSTA_UMSK (~(((1U << USB_TST_JSTA_LEN) - 1) << USB_TST_JSTA_POS)) -#define USB_TST_KSTA USB_TST_KSTA -#define USB_TST_KSTA_POS (2U) -#define USB_TST_KSTA_LEN (1U) -#define USB_TST_KSTA_MSK (((1U << USB_TST_KSTA_LEN) - 1) << USB_TST_KSTA_POS) -#define USB_TST_KSTA_UMSK (~(((1U << USB_TST_KSTA_LEN) - 1) << USB_TST_KSTA_POS)) -#define USB_TST_SE0NAK USB_TST_SE0NAK -#define USB_TST_SE0NAK_POS (3U) -#define USB_TST_SE0NAK_LEN (1U) -#define USB_TST_SE0NAK_MSK (((1U << USB_TST_SE0NAK_LEN) - 1) << USB_TST_SE0NAK_POS) -#define USB_TST_SE0NAK_UMSK (~(((1U << USB_TST_SE0NAK_LEN) - 1) << USB_TST_SE0NAK_POS)) -#define USB_TST_PKT USB_TST_PKT -#define USB_TST_PKT_POS (4U) -#define USB_TST_PKT_LEN (1U) -#define USB_TST_PKT_MSK (((1U << USB_TST_PKT_LEN) - 1) << USB_TST_PKT_POS) -#define USB_TST_PKT_UMSK (~(((1U << USB_TST_PKT_LEN) - 1) << USB_TST_PKT_POS)) - -/* 0x118 : DEV_VCTL */ -#define USB_DEV_VCTL_OFFSET (0x118) -#define USB_VCTL_HOV USB_VCTL_HOV -#define USB_VCTL_HOV_POS (0U) -#define USB_VCTL_HOV_LEN (5U) -#define USB_VCTL_HOV_MSK (((1U << USB_VCTL_HOV_LEN) - 1) << USB_VCTL_HOV_POS) -#define USB_VCTL_HOV_UMSK (~(((1U << USB_VCTL_HOV_LEN) - 1) << USB_VCTL_HOV_POS)) -#define USB_VCTLOAD_N_HOV USB_VCTLOAD_N_HOV -#define USB_VCTLOAD_N_HOV_POS (5U) -#define USB_VCTLOAD_N_HOV_LEN (1U) -#define USB_VCTLOAD_N_HOV_MSK (((1U << USB_VCTLOAD_N_HOV_LEN) - 1) << USB_VCTLOAD_N_HOV_POS) -#define USB_VCTLOAD_N_HOV_UMSK (~(((1U << USB_VCTLOAD_N_HOV_LEN) - 1) << USB_VCTLOAD_N_HOV_POS)) - -/* 0x11C : DEV_CXCFG */ -#define USB_DEV_CXCFG_OFFSET (0x11C) -#define USB_VSTA_HOV USB_VSTA_HOV -#define USB_VSTA_HOV_POS (0U) -#define USB_VSTA_HOV_LEN (8U) -#define USB_VSTA_HOV_MSK (((1U << USB_VSTA_HOV_LEN) - 1) << USB_VSTA_HOV_POS) -#define USB_VSTA_HOV_UMSK (~(((1U << USB_VSTA_HOV_LEN) - 1) << USB_VSTA_HOV_POS)) - -/* 0x120 : DEV_CXCFE */ -#define USB_DEV_CXCFE_OFFSET (0x120) -#define USB_CX_DONE USB_CX_DONE -#define USB_CX_DONE_POS (0U) -#define USB_CX_DONE_LEN (1U) -#define USB_CX_DONE_MSK (((1U << USB_CX_DONE_LEN) - 1) << USB_CX_DONE_POS) -#define USB_CX_DONE_UMSK (~(((1U << USB_CX_DONE_LEN) - 1) << USB_CX_DONE_POS)) -#define USB_TST_PKDONE USB_TST_PKDONE -#define USB_TST_PKDONE_POS (1U) -#define USB_TST_PKDONE_LEN (1U) -#define USB_TST_PKDONE_MSK (((1U << USB_TST_PKDONE_LEN) - 1) << USB_TST_PKDONE_POS) -#define USB_TST_PKDONE_UMSK (~(((1U << USB_TST_PKDONE_LEN) - 1) << USB_TST_PKDONE_POS)) -#define USB_CX_STL USB_CX_STL -#define USB_CX_STL_POS (2U) -#define USB_CX_STL_LEN (1U) -#define USB_CX_STL_MSK (((1U << USB_CX_STL_LEN) - 1) << USB_CX_STL_POS) -#define USB_CX_STL_UMSK (~(((1U << USB_CX_STL_LEN) - 1) << USB_CX_STL_POS)) -#define USB_CX_CLR USB_CX_CLR -#define USB_CX_CLR_POS (3U) -#define USB_CX_CLR_LEN (1U) -#define USB_CX_CLR_MSK (((1U << USB_CX_CLR_LEN) - 1) << USB_CX_CLR_POS) -#define USB_CX_CLR_UMSK (~(((1U << USB_CX_CLR_LEN) - 1) << USB_CX_CLR_POS)) -#define USB_CX_FUL USB_CX_FUL -#define USB_CX_FUL_POS (4U) -#define USB_CX_FUL_LEN (1U) -#define USB_CX_FUL_MSK (((1U << USB_CX_FUL_LEN) - 1) << USB_CX_FUL_POS) -#define USB_CX_FUL_UMSK (~(((1U << USB_CX_FUL_LEN) - 1) << USB_CX_FUL_POS)) -#define USB_CX_EMP USB_CX_EMP -#define USB_CX_EMP_POS (5U) -#define USB_CX_EMP_LEN (1U) -#define USB_CX_EMP_MSK (((1U << USB_CX_EMP_LEN) - 1) << USB_CX_EMP_POS) -#define USB_CX_EMP_UMSK (~(((1U << USB_CX_EMP_LEN) - 1) << USB_CX_EMP_POS)) -#define USB_F0_EMP USB_F0_EMP -#define USB_F0_EMP_POS (8U) -#define USB_F0_EMP_LEN (1U) -#define USB_F0_EMP_MSK (((1U << USB_F0_EMP_LEN) - 1) << USB_F0_EMP_POS) -#define USB_F0_EMP_UMSK (~(((1U << USB_F0_EMP_LEN) - 1) << USB_F0_EMP_POS)) -#define USB_F1_EMP USB_F1_EMP -#define USB_F1_EMP_POS (9U) -#define USB_F1_EMP_LEN (1U) -#define USB_F1_EMP_MSK (((1U << USB_F1_EMP_LEN) - 1) << USB_F1_EMP_POS) -#define USB_F1_EMP_UMSK (~(((1U << USB_F1_EMP_LEN) - 1) << USB_F1_EMP_POS)) -#define USB_F2_EMP USB_F2_EMP -#define USB_F2_EMP_POS (10U) -#define USB_F2_EMP_LEN (1U) -#define USB_F2_EMP_MSK (((1U << USB_F2_EMP_LEN) - 1) << USB_F2_EMP_POS) -#define USB_F2_EMP_UMSK (~(((1U << USB_F2_EMP_LEN) - 1) << USB_F2_EMP_POS)) -#define USB_F3_EMP USB_F3_EMP -#define USB_F3_EMP_POS (11U) -#define USB_F3_EMP_LEN (1U) -#define USB_F3_EMP_MSK (((1U << USB_F3_EMP_LEN) - 1) << USB_F3_EMP_POS) -#define USB_F3_EMP_UMSK (~(((1U << USB_F3_EMP_LEN) - 1) << USB_F3_EMP_POS)) -#define USB_F4_EMP USB_F4_EMP -#define USB_F4_EMP_POS (12U) -#define USB_F4_EMP_LEN (1U) -#define USB_F4_EMP_MSK (((1U << USB_F4_EMP_LEN) - 1) << USB_F4_EMP_POS) -#define USB_F4_EMP_UMSK (~(((1U << USB_F4_EMP_LEN) - 1) << USB_F4_EMP_POS)) -#define USB_F5_EMP USB_F5_EMP -#define USB_F5_EMP_POS (13U) -#define USB_F5_EMP_LEN (1U) -#define USB_F5_EMP_MSK (((1U << USB_F5_EMP_LEN) - 1) << USB_F5_EMP_POS) -#define USB_F5_EMP_UMSK (~(((1U << USB_F5_EMP_LEN) - 1) << USB_F5_EMP_POS)) -#define USB_F6_EMP USB_F6_EMP -#define USB_F6_EMP_POS (14U) -#define USB_F6_EMP_LEN (1U) -#define USB_F6_EMP_MSK (((1U << USB_F6_EMP_LEN) - 1) << USB_F6_EMP_POS) -#define USB_F6_EMP_UMSK (~(((1U << USB_F6_EMP_LEN) - 1) << USB_F6_EMP_POS)) -#define USB_F7_EMP USB_F7_EMP -#define USB_F7_EMP_POS (15U) -#define USB_F7_EMP_LEN (1U) -#define USB_F7_EMP_MSK (((1U << USB_F7_EMP_LEN) - 1) << USB_F7_EMP_POS) -#define USB_F7_EMP_UMSK (~(((1U << USB_F7_EMP_LEN) - 1) << USB_F7_EMP_POS)) -#define USB_F8_EMP USB_F8_EMP -#define USB_F8_EMP_POS (16U) -#define USB_F8_EMP_LEN (1U) -#define USB_F8_EMP_MSK (((1U << USB_F8_EMP_LEN) - 1) << USB_F8_EMP_POS) -#define USB_F8_EMP_UMSK (~(((1U << USB_F8_EMP_LEN) - 1) << USB_F8_EMP_POS)) -#define USB_F9_EMP USB_F9_EMP -#define USB_F9_EMP_POS (17U) -#define USB_F9_EMP_LEN (1U) -#define USB_F9_EMP_MSK (((1U << USB_F9_EMP_LEN) - 1) << USB_F9_EMP_POS) -#define USB_F9_EMP_UMSK (~(((1U << USB_F9_EMP_LEN) - 1) << USB_F9_EMP_POS)) -#define USB_F10_EMP USB_F10_EMP -#define USB_F10_EMP_POS (18U) -#define USB_F10_EMP_LEN (1U) -#define USB_F10_EMP_MSK (((1U << USB_F10_EMP_LEN) - 1) << USB_F10_EMP_POS) -#define USB_F10_EMP_UMSK (~(((1U << USB_F10_EMP_LEN) - 1) << USB_F10_EMP_POS)) -#define USB_F11_EMP USB_F11_EMP -#define USB_F11_EMP_POS (19U) -#define USB_F11_EMP_LEN (1U) -#define USB_F11_EMP_MSK (((1U << USB_F11_EMP_LEN) - 1) << USB_F11_EMP_POS) -#define USB_F11_EMP_UMSK (~(((1U << USB_F11_EMP_LEN) - 1) << USB_F11_EMP_POS)) -#define USB_F12_EMP USB_F12_EMP -#define USB_F12_EMP_POS (20U) -#define USB_F12_EMP_LEN (1U) -#define USB_F12_EMP_MSK (((1U << USB_F12_EMP_LEN) - 1) << USB_F12_EMP_POS) -#define USB_F12_EMP_UMSK (~(((1U << USB_F12_EMP_LEN) - 1) << USB_F12_EMP_POS)) -#define USB_F13_EMP USB_F13_EMP -#define USB_F13_EMP_POS (21U) -#define USB_F13_EMP_LEN (1U) -#define USB_F13_EMP_MSK (((1U << USB_F13_EMP_LEN) - 1) << USB_F13_EMP_POS) -#define USB_F13_EMP_UMSK (~(((1U << USB_F13_EMP_LEN) - 1) << USB_F13_EMP_POS)) -#define USB_F14_EMP USB_F14_EMP -#define USB_F14_EMP_POS (22U) -#define USB_F14_EMP_LEN (1U) -#define USB_F14_EMP_MSK (((1U << USB_F14_EMP_LEN) - 1) << USB_F14_EMP_POS) -#define USB_F14_EMP_UMSK (~(((1U << USB_F14_EMP_LEN) - 1) << USB_F14_EMP_POS)) -#define USB_F15_EMP USB_F15_EMP -#define USB_F15_EMP_POS (23U) -#define USB_F15_EMP_LEN (1U) -#define USB_F15_EMP_MSK (((1U << USB_F15_EMP_LEN) - 1) << USB_F15_EMP_POS) -#define USB_F15_EMP_UMSK (~(((1U << USB_F15_EMP_LEN) - 1) << USB_F15_EMP_POS)) -#define USB_CX_FNT USB_CX_FNT -#define USB_CX_FNT_POS (24U) -#define USB_CX_FNT_LEN (7U) -#define USB_CX_FNT_MSK (((1U << USB_CX_FNT_LEN) - 1) << USB_CX_FNT_POS) -#define USB_CX_FNT_UMSK (~(((1U << USB_CX_FNT_LEN) - 1) << USB_CX_FNT_POS)) - -/* 0x124 : DEV_ICR */ -#define USB_DEV_ICR_OFFSET (0x124) -#define USB_IDLE_CNT USB_IDLE_CNT -#define USB_IDLE_CNT_POS (0U) -#define USB_IDLE_CNT_LEN (3U) -#define USB_IDLE_CNT_MSK (((1U << USB_IDLE_CNT_LEN) - 1) << USB_IDLE_CNT_POS) -#define USB_IDLE_CNT_UMSK (~(((1U << USB_IDLE_CNT_LEN) - 1) << USB_IDLE_CNT_POS)) - -/* 0x130 : DEV_MIGR */ -#define USB_DEV_MIGR_OFFSET (0x130) -#define USB_MINT_G0 USB_MINT_G0 -#define USB_MINT_G0_POS (0U) -#define USB_MINT_G0_LEN (1U) -#define USB_MINT_G0_MSK (((1U << USB_MINT_G0_LEN) - 1) << USB_MINT_G0_POS) -#define USB_MINT_G0_UMSK (~(((1U << USB_MINT_G0_LEN) - 1) << USB_MINT_G0_POS)) -#define USB_MINT_G1 USB_MINT_G1 -#define USB_MINT_G1_POS (1U) -#define USB_MINT_G1_LEN (1U) -#define USB_MINT_G1_MSK (((1U << USB_MINT_G1_LEN) - 1) << USB_MINT_G1_POS) -#define USB_MINT_G1_UMSK (~(((1U << USB_MINT_G1_LEN) - 1) << USB_MINT_G1_POS)) -#define USB_MINT_G2 USB_MINT_G2 -#define USB_MINT_G2_POS (2U) -#define USB_MINT_G2_LEN (1U) -#define USB_MINT_G2_MSK (((1U << USB_MINT_G2_LEN) - 1) << USB_MINT_G2_POS) -#define USB_MINT_G2_UMSK (~(((1U << USB_MINT_G2_LEN) - 1) << USB_MINT_G2_POS)) -#define USB_MINT_G3 USB_MINT_G3 -#define USB_MINT_G3_POS (3U) -#define USB_MINT_G3_LEN (1U) -#define USB_MINT_G3_MSK (((1U << USB_MINT_G3_LEN) - 1) << USB_MINT_G3_POS) -#define USB_MINT_G3_UMSK (~(((1U << USB_MINT_G3_LEN) - 1) << USB_MINT_G3_POS)) -#define USB_MINT_G4 USB_MINT_G4 -#define USB_MINT_G4_POS (4U) -#define USB_MINT_G4_LEN (1U) -#define USB_MINT_G4_MSK (((1U << USB_MINT_G4_LEN) - 1) << USB_MINT_G4_POS) -#define USB_MINT_G4_UMSK (~(((1U << USB_MINT_G4_LEN) - 1) << USB_MINT_G4_POS)) - -/* 0x134 : DEV_MISG0 */ -#define USB_DEV_MISG0_OFFSET (0x134) -#define USB_MCX_SETUP_INT USB_MCX_SETUP_INT -#define USB_MCX_SETUP_INT_POS (0U) -#define USB_MCX_SETUP_INT_LEN (1U) -#define USB_MCX_SETUP_INT_MSK (((1U << USB_MCX_SETUP_INT_LEN) - 1) << USB_MCX_SETUP_INT_POS) -#define USB_MCX_SETUP_INT_UMSK (~(((1U << USB_MCX_SETUP_INT_LEN) - 1) << USB_MCX_SETUP_INT_POS)) -#define USB_MCX_IN_INT USB_MCX_IN_INT -#define USB_MCX_IN_INT_POS (1U) -#define USB_MCX_IN_INT_LEN (1U) -#define USB_MCX_IN_INT_MSK (((1U << USB_MCX_IN_INT_LEN) - 1) << USB_MCX_IN_INT_POS) -#define USB_MCX_IN_INT_UMSK (~(((1U << USB_MCX_IN_INT_LEN) - 1) << USB_MCX_IN_INT_POS)) -#define USB_MCX_OUT_INT USB_MCX_OUT_INT -#define USB_MCX_OUT_INT_POS (2U) -#define USB_MCX_OUT_INT_LEN (1U) -#define USB_MCX_OUT_INT_MSK (((1U << USB_MCX_OUT_INT_LEN) - 1) << USB_MCX_OUT_INT_POS) -#define USB_MCX_OUT_INT_UMSK (~(((1U << USB_MCX_OUT_INT_LEN) - 1) << USB_MCX_OUT_INT_POS)) -#define USB_MCX_COMFAIL_INT USB_MCX_COMFAIL_INT -#define USB_MCX_COMFAIL_INT_POS (4U) -#define USB_MCX_COMFAIL_INT_LEN (1U) -#define USB_MCX_COMFAIL_INT_MSK (((1U << USB_MCX_COMFAIL_INT_LEN) - 1) << USB_MCX_COMFAIL_INT_POS) -#define USB_MCX_COMFAIL_INT_UMSK (~(((1U << USB_MCX_COMFAIL_INT_LEN) - 1) << USB_MCX_COMFAIL_INT_POS)) -#define USB_MCX_COMABORT_INT USB_MCX_COMABORT_INT -#define USB_MCX_COMABORT_INT_POS (5U) -#define USB_MCX_COMABORT_INT_LEN (1U) -#define USB_MCX_COMABORT_INT_MSK (((1U << USB_MCX_COMABORT_INT_LEN) - 1) << USB_MCX_COMABORT_INT_POS) -#define USB_MCX_COMABORT_INT_UMSK (~(((1U << USB_MCX_COMABORT_INT_LEN) - 1) << USB_MCX_COMABORT_INT_POS)) - -/* 0x138 : DEV_MISG1 */ -#define USB_DEV_MISG1_OFFSET (0x138) -#define USB_MF0_OUT_INT USB_MF0_OUT_INT -#define USB_MF0_OUT_INT_POS (0U) -#define USB_MF0_OUT_INT_LEN (1U) -#define USB_MF0_OUT_INT_MSK (((1U << USB_MF0_OUT_INT_LEN) - 1) << USB_MF0_OUT_INT_POS) -#define USB_MF0_OUT_INT_UMSK (~(((1U << USB_MF0_OUT_INT_LEN) - 1) << USB_MF0_OUT_INT_POS)) -#define USB_MF0_SPK_INT USB_MF0_SPK_INT -#define USB_MF0_SPK_INT_POS (1U) -#define USB_MF0_SPK_INT_LEN (1U) -#define USB_MF0_SPK_INT_MSK (((1U << USB_MF0_SPK_INT_LEN) - 1) << USB_MF0_SPK_INT_POS) -#define USB_MF0_SPK_INT_UMSK (~(((1U << USB_MF0_SPK_INT_LEN) - 1) << USB_MF0_SPK_INT_POS)) -#define USB_MF1_OUT_INT USB_MF1_OUT_INT -#define USB_MF1_OUT_INT_POS (2U) -#define USB_MF1_OUT_INT_LEN (1U) -#define USB_MF1_OUT_INT_MSK (((1U << USB_MF1_OUT_INT_LEN) - 1) << USB_MF1_OUT_INT_POS) -#define USB_MF1_OUT_INT_UMSK (~(((1U << USB_MF1_OUT_INT_LEN) - 1) << USB_MF1_OUT_INT_POS)) -#define USB_MF1_SPK_INT USB_MF1_SPK_INT -#define USB_MF1_SPK_INT_POS (3U) -#define USB_MF1_SPK_INT_LEN (1U) -#define USB_MF1_SPK_INT_MSK (((1U << USB_MF1_SPK_INT_LEN) - 1) << USB_MF1_SPK_INT_POS) -#define USB_MF1_SPK_INT_UMSK (~(((1U << USB_MF1_SPK_INT_LEN) - 1) << USB_MF1_SPK_INT_POS)) -#define USB_MF2_OUT_INT USB_MF2_OUT_INT -#define USB_MF2_OUT_INT_POS (4U) -#define USB_MF2_OUT_INT_LEN (1U) -#define USB_MF2_OUT_INT_MSK (((1U << USB_MF2_OUT_INT_LEN) - 1) << USB_MF2_OUT_INT_POS) -#define USB_MF2_OUT_INT_UMSK (~(((1U << USB_MF2_OUT_INT_LEN) - 1) << USB_MF2_OUT_INT_POS)) -#define USB_MF2_SPK_INT USB_MF2_SPK_INT -#define USB_MF2_SPK_INT_POS (5U) -#define USB_MF2_SPK_INT_LEN (1U) -#define USB_MF2_SPK_INT_MSK (((1U << USB_MF2_SPK_INT_LEN) - 1) << USB_MF2_SPK_INT_POS) -#define USB_MF2_SPK_INT_UMSK (~(((1U << USB_MF2_SPK_INT_LEN) - 1) << USB_MF2_SPK_INT_POS)) -#define USB_MF3_OUT_INT USB_MF3_OUT_INT -#define USB_MF3_OUT_INT_POS (6U) -#define USB_MF3_OUT_INT_LEN (1U) -#define USB_MF3_OUT_INT_MSK (((1U << USB_MF3_OUT_INT_LEN) - 1) << USB_MF3_OUT_INT_POS) -#define USB_MF3_OUT_INT_UMSK (~(((1U << USB_MF3_OUT_INT_LEN) - 1) << USB_MF3_OUT_INT_POS)) -#define USB_MF3_SPK_INT USB_MF3_SPK_INT -#define USB_MF3_SPK_INT_POS (7U) -#define USB_MF3_SPK_INT_LEN (1U) -#define USB_MF3_SPK_INT_MSK (((1U << USB_MF3_SPK_INT_LEN) - 1) << USB_MF3_SPK_INT_POS) -#define USB_MF3_SPK_INT_UMSK (~(((1U << USB_MF3_SPK_INT_LEN) - 1) << USB_MF3_SPK_INT_POS)) -#define USB_MF4_OUT_INT USB_MF4_OUT_INT -#define USB_MF4_OUT_INT_POS (8U) -#define USB_MF4_OUT_INT_LEN (1U) -#define USB_MF4_OUT_INT_MSK (((1U << USB_MF4_OUT_INT_LEN) - 1) << USB_MF4_OUT_INT_POS) -#define USB_MF4_OUT_INT_UMSK (~(((1U << USB_MF4_OUT_INT_LEN) - 1) << USB_MF4_OUT_INT_POS)) -#define USB_MF4_SPK_INT USB_MF4_SPK_INT -#define USB_MF4_SPK_INT_POS (9U) -#define USB_MF4_SPK_INT_LEN (1U) -#define USB_MF4_SPK_INT_MSK (((1U << USB_MF4_SPK_INT_LEN) - 1) << USB_MF4_SPK_INT_POS) -#define USB_MF4_SPK_INT_UMSK (~(((1U << USB_MF4_SPK_INT_LEN) - 1) << USB_MF4_SPK_INT_POS)) -#define USB_MF5_OUT_INT USB_MF5_OUT_INT -#define USB_MF5_OUT_INT_POS (10U) -#define USB_MF5_OUT_INT_LEN (1U) -#define USB_MF5_OUT_INT_MSK (((1U << USB_MF5_OUT_INT_LEN) - 1) << USB_MF5_OUT_INT_POS) -#define USB_MF5_OUT_INT_UMSK (~(((1U << USB_MF5_OUT_INT_LEN) - 1) << USB_MF5_OUT_INT_POS)) -#define USB_MF5_SPK_INT USB_MF5_SPK_INT -#define USB_MF5_SPK_INT_POS (11U) -#define USB_MF5_SPK_INT_LEN (1U) -#define USB_MF5_SPK_INT_MSK (((1U << USB_MF5_SPK_INT_LEN) - 1) << USB_MF5_SPK_INT_POS) -#define USB_MF5_SPK_INT_UMSK (~(((1U << USB_MF5_SPK_INT_LEN) - 1) << USB_MF5_SPK_INT_POS)) -#define USB_MF6_OUT_INT USB_MF6_OUT_INT -#define USB_MF6_OUT_INT_POS (12U) -#define USB_MF6_OUT_INT_LEN (1U) -#define USB_MF6_OUT_INT_MSK (((1U << USB_MF6_OUT_INT_LEN) - 1) << USB_MF6_OUT_INT_POS) -#define USB_MF6_OUT_INT_UMSK (~(((1U << USB_MF6_OUT_INT_LEN) - 1) << USB_MF6_OUT_INT_POS)) -#define USB_MF6_SPK_INT USB_MF6_SPK_INT -#define USB_MF6_SPK_INT_POS (13U) -#define USB_MF6_SPK_INT_LEN (1U) -#define USB_MF6_SPK_INT_MSK (((1U << USB_MF6_SPK_INT_LEN) - 1) << USB_MF6_SPK_INT_POS) -#define USB_MF6_SPK_INT_UMSK (~(((1U << USB_MF6_SPK_INT_LEN) - 1) << USB_MF6_SPK_INT_POS)) -#define USB_MF7_OUT_INT USB_MF7_OUT_INT -#define USB_MF7_OUT_INT_POS (14U) -#define USB_MF7_OUT_INT_LEN (1U) -#define USB_MF7_OUT_INT_MSK (((1U << USB_MF7_OUT_INT_LEN) - 1) << USB_MF7_OUT_INT_POS) -#define USB_MF7_OUT_INT_UMSK (~(((1U << USB_MF7_OUT_INT_LEN) - 1) << USB_MF7_OUT_INT_POS)) -#define USB_MF7_SPK_INT USB_MF7_SPK_INT -#define USB_MF7_SPK_INT_POS (15U) -#define USB_MF7_SPK_INT_LEN (1U) -#define USB_MF7_SPK_INT_MSK (((1U << USB_MF7_SPK_INT_LEN) - 1) << USB_MF7_SPK_INT_POS) -#define USB_MF7_SPK_INT_UMSK (~(((1U << USB_MF7_SPK_INT_LEN) - 1) << USB_MF7_SPK_INT_POS)) -#define USB_MF0_IN_INT USB_MF0_IN_INT -#define USB_MF0_IN_INT_POS (16U) -#define USB_MF0_IN_INT_LEN (1U) -#define USB_MF0_IN_INT_MSK (((1U << USB_MF0_IN_INT_LEN) - 1) << USB_MF0_IN_INT_POS) -#define USB_MF0_IN_INT_UMSK (~(((1U << USB_MF0_IN_INT_LEN) - 1) << USB_MF0_IN_INT_POS)) -#define USB_MF1_IN_INT USB_MF1_IN_INT -#define USB_MF1_IN_INT_POS (17U) -#define USB_MF1_IN_INT_LEN (1U) -#define USB_MF1_IN_INT_MSK (((1U << USB_MF1_IN_INT_LEN) - 1) << USB_MF1_IN_INT_POS) -#define USB_MF1_IN_INT_UMSK (~(((1U << USB_MF1_IN_INT_LEN) - 1) << USB_MF1_IN_INT_POS)) -#define USB_MF2_IN_INT USB_MF2_IN_INT -#define USB_MF2_IN_INT_POS (18U) -#define USB_MF2_IN_INT_LEN (1U) -#define USB_MF2_IN_INT_MSK (((1U << USB_MF2_IN_INT_LEN) - 1) << USB_MF2_IN_INT_POS) -#define USB_MF2_IN_INT_UMSK (~(((1U << USB_MF2_IN_INT_LEN) - 1) << USB_MF2_IN_INT_POS)) -#define USB_MF3_IN_INT USB_MF3_IN_INT -#define USB_MF3_IN_INT_POS (19U) -#define USB_MF3_IN_INT_LEN (1U) -#define USB_MF3_IN_INT_MSK (((1U << USB_MF3_IN_INT_LEN) - 1) << USB_MF3_IN_INT_POS) -#define USB_MF3_IN_INT_UMSK (~(((1U << USB_MF3_IN_INT_LEN) - 1) << USB_MF3_IN_INT_POS)) -#define USB_MF4_IN_INT USB_MF4_IN_INT -#define USB_MF4_IN_INT_POS (20U) -#define USB_MF4_IN_INT_LEN (1U) -#define USB_MF4_IN_INT_MSK (((1U << USB_MF4_IN_INT_LEN) - 1) << USB_MF4_IN_INT_POS) -#define USB_MF4_IN_INT_UMSK (~(((1U << USB_MF4_IN_INT_LEN) - 1) << USB_MF4_IN_INT_POS)) -#define USB_MF5_IN_INT USB_MF5_IN_INT -#define USB_MF5_IN_INT_POS (21U) -#define USB_MF5_IN_INT_LEN (1U) -#define USB_MF5_IN_INT_MSK (((1U << USB_MF5_IN_INT_LEN) - 1) << USB_MF5_IN_INT_POS) -#define USB_MF5_IN_INT_UMSK (~(((1U << USB_MF5_IN_INT_LEN) - 1) << USB_MF5_IN_INT_POS)) -#define USB_MF6_IN_INT USB_MF6_IN_INT -#define USB_MF6_IN_INT_POS (22U) -#define USB_MF6_IN_INT_LEN (1U) -#define USB_MF6_IN_INT_MSK (((1U << USB_MF6_IN_INT_LEN) - 1) << USB_MF6_IN_INT_POS) -#define USB_MF6_IN_INT_UMSK (~(((1U << USB_MF6_IN_INT_LEN) - 1) << USB_MF6_IN_INT_POS)) -#define USB_MF7_IN_INT USB_MF7_IN_INT -#define USB_MF7_IN_INT_POS (23U) -#define USB_MF7_IN_INT_LEN (1U) -#define USB_MF7_IN_INT_MSK (((1U << USB_MF7_IN_INT_LEN) - 1) << USB_MF7_IN_INT_POS) -#define USB_MF7_IN_INT_UMSK (~(((1U << USB_MF7_IN_INT_LEN) - 1) << USB_MF7_IN_INT_POS)) -#define USB_MF8_IN_INT USB_MF8_IN_INT -#define USB_MF8_IN_INT_POS (24U) -#define USB_MF8_IN_INT_LEN (1U) -#define USB_MF8_IN_INT_MSK (((1U << USB_MF8_IN_INT_LEN) - 1) << USB_MF8_IN_INT_POS) -#define USB_MF8_IN_INT_UMSK (~(((1U << USB_MF8_IN_INT_LEN) - 1) << USB_MF8_IN_INT_POS)) -#define USB_MF9_IN_INT USB_MF9_IN_INT -#define USB_MF9_IN_INT_POS (25U) -#define USB_MF9_IN_INT_LEN (1U) -#define USB_MF9_IN_INT_MSK (((1U << USB_MF9_IN_INT_LEN) - 1) << USB_MF9_IN_INT_POS) -#define USB_MF9_IN_INT_UMSK (~(((1U << USB_MF9_IN_INT_LEN) - 1) << USB_MF9_IN_INT_POS)) -#define USB_MF10_IN_INT USB_MF10_IN_INT -#define USB_MF10_IN_INT_POS (26U) -#define USB_MF10_IN_INT_LEN (1U) -#define USB_MF10_IN_INT_MSK (((1U << USB_MF10_IN_INT_LEN) - 1) << USB_MF10_IN_INT_POS) -#define USB_MF10_IN_INT_UMSK (~(((1U << USB_MF10_IN_INT_LEN) - 1) << USB_MF10_IN_INT_POS)) -#define USB_MF11_IN_INT USB_MF11_IN_INT -#define USB_MF11_IN_INT_POS (27U) -#define USB_MF11_IN_INT_LEN (1U) -#define USB_MF11_IN_INT_MSK (((1U << USB_MF11_IN_INT_LEN) - 1) << USB_MF11_IN_INT_POS) -#define USB_MF11_IN_INT_UMSK (~(((1U << USB_MF11_IN_INT_LEN) - 1) << USB_MF11_IN_INT_POS)) -#define USB_MF12_IN_INT USB_MF12_IN_INT -#define USB_MF12_IN_INT_POS (28U) -#define USB_MF12_IN_INT_LEN (1U) -#define USB_MF12_IN_INT_MSK (((1U << USB_MF12_IN_INT_LEN) - 1) << USB_MF12_IN_INT_POS) -#define USB_MF12_IN_INT_UMSK (~(((1U << USB_MF12_IN_INT_LEN) - 1) << USB_MF12_IN_INT_POS)) -#define USB_MF13_IN_INT USB_MF13_IN_INT -#define USB_MF13_IN_INT_POS (29U) -#define USB_MF13_IN_INT_LEN (1U) -#define USB_MF13_IN_INT_MSK (((1U << USB_MF13_IN_INT_LEN) - 1) << USB_MF13_IN_INT_POS) -#define USB_MF13_IN_INT_UMSK (~(((1U << USB_MF13_IN_INT_LEN) - 1) << USB_MF13_IN_INT_POS)) -#define USB_MF14_IN_INT USB_MF14_IN_INT -#define USB_MF14_IN_INT_POS (30U) -#define USB_MF14_IN_INT_LEN (1U) -#define USB_MF14_IN_INT_MSK (((1U << USB_MF14_IN_INT_LEN) - 1) << USB_MF14_IN_INT_POS) -#define USB_MF14_IN_INT_UMSK (~(((1U << USB_MF14_IN_INT_LEN) - 1) << USB_MF14_IN_INT_POS)) -#define USB_MF15_IN_INT USB_MF15_IN_INT -#define USB_MF15_IN_INT_POS (31U) -#define USB_MF15_IN_INT_LEN (1U) -#define USB_MF15_IN_INT_MSK (((1U << USB_MF15_IN_INT_LEN) - 1) << USB_MF15_IN_INT_POS) -#define USB_MF15_IN_INT_UMSK (~(((1U << USB_MF15_IN_INT_LEN) - 1) << USB_MF15_IN_INT_POS)) - -/* 0x13C : DEV_MISG2 */ -#define USB_DEV_MISG2_OFFSET (0x13C) -#define USB_MUSBRST_INT USB_MUSBRST_INT -#define USB_MUSBRST_INT_POS (0U) -#define USB_MUSBRST_INT_LEN (1U) -#define USB_MUSBRST_INT_MSK (((1U << USB_MUSBRST_INT_LEN) - 1) << USB_MUSBRST_INT_POS) -#define USB_MUSBRST_INT_UMSK (~(((1U << USB_MUSBRST_INT_LEN) - 1) << USB_MUSBRST_INT_POS)) -#define USB_MSUSP_INT USB_MSUSP_INT -#define USB_MSUSP_INT_POS (1U) -#define USB_MSUSP_INT_LEN (1U) -#define USB_MSUSP_INT_MSK (((1U << USB_MSUSP_INT_LEN) - 1) << USB_MSUSP_INT_POS) -#define USB_MSUSP_INT_UMSK (~(((1U << USB_MSUSP_INT_LEN) - 1) << USB_MSUSP_INT_POS)) -#define USB_MRESM_INT USB_MRESM_INT -#define USB_MRESM_INT_POS (2U) -#define USB_MRESM_INT_LEN (1U) -#define USB_MRESM_INT_MSK (((1U << USB_MRESM_INT_LEN) - 1) << USB_MRESM_INT_POS) -#define USB_MRESM_INT_UMSK (~(((1U << USB_MRESM_INT_LEN) - 1) << USB_MRESM_INT_POS)) -#define USB_MSEQ_ERR_INT USB_MSEQ_ERR_INT -#define USB_MSEQ_ERR_INT_POS (3U) -#define USB_MSEQ_ERR_INT_LEN (1U) -#define USB_MSEQ_ERR_INT_MSK (((1U << USB_MSEQ_ERR_INT_LEN) - 1) << USB_MSEQ_ERR_INT_POS) -#define USB_MSEQ_ERR_INT_UMSK (~(((1U << USB_MSEQ_ERR_INT_LEN) - 1) << USB_MSEQ_ERR_INT_POS)) -#define USB_MSEQ_ABORT_INT USB_MSEQ_ABORT_INT -#define USB_MSEQ_ABORT_INT_POS (4U) -#define USB_MSEQ_ABORT_INT_LEN (1U) -#define USB_MSEQ_ABORT_INT_MSK (((1U << USB_MSEQ_ABORT_INT_LEN) - 1) << USB_MSEQ_ABORT_INT_POS) -#define USB_MSEQ_ABORT_INT_UMSK (~(((1U << USB_MSEQ_ABORT_INT_LEN) - 1) << USB_MSEQ_ABORT_INT_POS)) -#define USB_MTX0BYTE_INT USB_MTX0BYTE_INT -#define USB_MTX0BYTE_INT_POS (5U) -#define USB_MTX0BYTE_INT_LEN (1U) -#define USB_MTX0BYTE_INT_MSK (((1U << USB_MTX0BYTE_INT_LEN) - 1) << USB_MTX0BYTE_INT_POS) -#define USB_MTX0BYTE_INT_UMSK (~(((1U << USB_MTX0BYTE_INT_LEN) - 1) << USB_MTX0BYTE_INT_POS)) -#define USB_MRX0BYTE_INT USB_MRX0BYTE_INT -#define USB_MRX0BYTE_INT_POS (6U) -#define USB_MRX0BYTE_INT_LEN (1U) -#define USB_MRX0BYTE_INT_MSK (((1U << USB_MRX0BYTE_INT_LEN) - 1) << USB_MRX0BYTE_INT_POS) -#define USB_MRX0BYTE_INT_UMSK (~(((1U << USB_MRX0BYTE_INT_LEN) - 1) << USB_MRX0BYTE_INT_POS)) -#define USB_MDMA_CMPLT_HOV USB_MDMA_CMPLT_HOV -#define USB_MDMA_CMPLT_HOV_POS (7U) -#define USB_MDMA_CMPLT_HOV_LEN (1U) -#define USB_MDMA_CMPLT_HOV_MSK (((1U << USB_MDMA_CMPLT_HOV_LEN) - 1) << USB_MDMA_CMPLT_HOV_POS) -#define USB_MDMA_CMPLT_HOV_UMSK (~(((1U << USB_MDMA_CMPLT_HOV_LEN) - 1) << USB_MDMA_CMPLT_HOV_POS)) -#define USB_MDMA_ERROR_HOV USB_MDMA_ERROR_HOV -#define USB_MDMA_ERROR_HOV_POS (8U) -#define USB_MDMA_ERROR_HOV_LEN (1U) -#define USB_MDMA_ERROR_HOV_MSK (((1U << USB_MDMA_ERROR_HOV_LEN) - 1) << USB_MDMA_ERROR_HOV_POS) -#define USB_MDMA_ERROR_HOV_UMSK (~(((1U << USB_MDMA_ERROR_HOV_LEN) - 1) << USB_MDMA_ERROR_HOV_POS)) -#define USB_MDEV_IDLE_HOV USB_MDEV_IDLE_HOV -#define USB_MDEV_IDLE_HOV_POS (9U) -#define USB_MDEV_IDLE_HOV_LEN (1U) -#define USB_MDEV_IDLE_HOV_MSK (((1U << USB_MDEV_IDLE_HOV_LEN) - 1) << USB_MDEV_IDLE_HOV_POS) -#define USB_MDEV_IDLE_HOV_UMSK (~(((1U << USB_MDEV_IDLE_HOV_LEN) - 1) << USB_MDEV_IDLE_HOV_POS)) -#define USB_MDEV_WAKEUP_BYVBUS USB_MDEV_WAKEUP_BYVBUS -#define USB_MDEV_WAKEUP_BYVBUS_POS (10U) -#define USB_MDEV_WAKEUP_BYVBUS_LEN (1U) -#define USB_MDEV_WAKEUP_BYVBUS_MSK (((1U << USB_MDEV_WAKEUP_BYVBUS_LEN) - 1) << USB_MDEV_WAKEUP_BYVBUS_POS) -#define USB_MDEV_WAKEUP_BYVBUS_UMSK (~(((1U << USB_MDEV_WAKEUP_BYVBUS_LEN) - 1) << USB_MDEV_WAKEUP_BYVBUS_POS)) -#define USB_MF8_OUT_INT USB_MF8_OUT_INT -#define USB_MF8_OUT_INT_POS (16U) -#define USB_MF8_OUT_INT_LEN (1U) -#define USB_MF8_OUT_INT_MSK (((1U << USB_MF8_OUT_INT_LEN) - 1) << USB_MF8_OUT_INT_POS) -#define USB_MF8_OUT_INT_UMSK (~(((1U << USB_MF8_OUT_INT_LEN) - 1) << USB_MF8_OUT_INT_POS)) -#define USB_MF8_SPK_INT USB_MF8_SPK_INT -#define USB_MF8_SPK_INT_POS (17U) -#define USB_MF8_SPK_INT_LEN (1U) -#define USB_MF8_SPK_INT_MSK (((1U << USB_MF8_SPK_INT_LEN) - 1) << USB_MF8_SPK_INT_POS) -#define USB_MF8_SPK_INT_UMSK (~(((1U << USB_MF8_SPK_INT_LEN) - 1) << USB_MF8_SPK_INT_POS)) -#define USB_MF9_OUT_INT USB_MF9_OUT_INT -#define USB_MF9_OUT_INT_POS (18U) -#define USB_MF9_OUT_INT_LEN (1U) -#define USB_MF9_OUT_INT_MSK (((1U << USB_MF9_OUT_INT_LEN) - 1) << USB_MF9_OUT_INT_POS) -#define USB_MF9_OUT_INT_UMSK (~(((1U << USB_MF9_OUT_INT_LEN) - 1) << USB_MF9_OUT_INT_POS)) -#define USB_MF9_SPK_INT USB_MF9_SPK_INT -#define USB_MF9_SPK_INT_POS (19U) -#define USB_MF9_SPK_INT_LEN (1U) -#define USB_MF9_SPK_INT_MSK (((1U << USB_MF9_SPK_INT_LEN) - 1) << USB_MF9_SPK_INT_POS) -#define USB_MF9_SPK_INT_UMSK (~(((1U << USB_MF9_SPK_INT_LEN) - 1) << USB_MF9_SPK_INT_POS)) -#define USB_MF10_OUT_INT USB_MF10_OUT_INT -#define USB_MF10_OUT_INT_POS (20U) -#define USB_MF10_OUT_INT_LEN (1U) -#define USB_MF10_OUT_INT_MSK (((1U << USB_MF10_OUT_INT_LEN) - 1) << USB_MF10_OUT_INT_POS) -#define USB_MF10_OUT_INT_UMSK (~(((1U << USB_MF10_OUT_INT_LEN) - 1) << USB_MF10_OUT_INT_POS)) -#define USB_MF10_SPK_INT USB_MF10_SPK_INT -#define USB_MF10_SPK_INT_POS (21U) -#define USB_MF10_SPK_INT_LEN (1U) -#define USB_MF10_SPK_INT_MSK (((1U << USB_MF10_SPK_INT_LEN) - 1) << USB_MF10_SPK_INT_POS) -#define USB_MF10_SPK_INT_UMSK (~(((1U << USB_MF10_SPK_INT_LEN) - 1) << USB_MF10_SPK_INT_POS)) -#define USB_MF11_OUT_INT USB_MF11_OUT_INT -#define USB_MF11_OUT_INT_POS (22U) -#define USB_MF11_OUT_INT_LEN (1U) -#define USB_MF11_OUT_INT_MSK (((1U << USB_MF11_OUT_INT_LEN) - 1) << USB_MF11_OUT_INT_POS) -#define USB_MF11_OUT_INT_UMSK (~(((1U << USB_MF11_OUT_INT_LEN) - 1) << USB_MF11_OUT_INT_POS)) -#define USB_MF11_SPK_INT USB_MF11_SPK_INT -#define USB_MF11_SPK_INT_POS (23U) -#define USB_MF11_SPK_INT_LEN (1U) -#define USB_MF11_SPK_INT_MSK (((1U << USB_MF11_SPK_INT_LEN) - 1) << USB_MF11_SPK_INT_POS) -#define USB_MF11_SPK_INT_UMSK (~(((1U << USB_MF11_SPK_INT_LEN) - 1) << USB_MF11_SPK_INT_POS)) -#define USB_MF12_OUT_INT USB_MF12_OUT_INT -#define USB_MF12_OUT_INT_POS (24U) -#define USB_MF12_OUT_INT_LEN (1U) -#define USB_MF12_OUT_INT_MSK (((1U << USB_MF12_OUT_INT_LEN) - 1) << USB_MF12_OUT_INT_POS) -#define USB_MF12_OUT_INT_UMSK (~(((1U << USB_MF12_OUT_INT_LEN) - 1) << USB_MF12_OUT_INT_POS)) -#define USB_MF12_SPK_INT USB_MF12_SPK_INT -#define USB_MF12_SPK_INT_POS (25U) -#define USB_MF12_SPK_INT_LEN (1U) -#define USB_MF12_SPK_INT_MSK (((1U << USB_MF12_SPK_INT_LEN) - 1) << USB_MF12_SPK_INT_POS) -#define USB_MF12_SPK_INT_UMSK (~(((1U << USB_MF12_SPK_INT_LEN) - 1) << USB_MF12_SPK_INT_POS)) -#define USB_MF13_OUT_INT USB_MF13_OUT_INT -#define USB_MF13_OUT_INT_POS (26U) -#define USB_MF13_OUT_INT_LEN (1U) -#define USB_MF13_OUT_INT_MSK (((1U << USB_MF13_OUT_INT_LEN) - 1) << USB_MF13_OUT_INT_POS) -#define USB_MF13_OUT_INT_UMSK (~(((1U << USB_MF13_OUT_INT_LEN) - 1) << USB_MF13_OUT_INT_POS)) -#define USB_MF13_SPK_INT USB_MF13_SPK_INT -#define USB_MF13_SPK_INT_POS (27U) -#define USB_MF13_SPK_INT_LEN (1U) -#define USB_MF13_SPK_INT_MSK (((1U << USB_MF13_SPK_INT_LEN) - 1) << USB_MF13_SPK_INT_POS) -#define USB_MF13_SPK_INT_UMSK (~(((1U << USB_MF13_SPK_INT_LEN) - 1) << USB_MF13_SPK_INT_POS)) -#define USB_MF14_OUT_INT USB_MF14_OUT_INT -#define USB_MF14_OUT_INT_POS (28U) -#define USB_MF14_OUT_INT_LEN (1U) -#define USB_MF14_OUT_INT_MSK (((1U << USB_MF14_OUT_INT_LEN) - 1) << USB_MF14_OUT_INT_POS) -#define USB_MF14_OUT_INT_UMSK (~(((1U << USB_MF14_OUT_INT_LEN) - 1) << USB_MF14_OUT_INT_POS)) -#define USB_MF14_SPK_INT USB_MF14_SPK_INT -#define USB_MF14_SPK_INT_POS (29U) -#define USB_MF14_SPK_INT_LEN (1U) -#define USB_MF14_SPK_INT_MSK (((1U << USB_MF14_SPK_INT_LEN) - 1) << USB_MF14_SPK_INT_POS) -#define USB_MF14_SPK_INT_UMSK (~(((1U << USB_MF14_SPK_INT_LEN) - 1) << USB_MF14_SPK_INT_POS)) -#define USB_MF15_OUT_INT USB_MF15_OUT_INT -#define USB_MF15_OUT_INT_POS (30U) -#define USB_MF15_OUT_INT_LEN (1U) -#define USB_MF15_OUT_INT_MSK (((1U << USB_MF15_OUT_INT_LEN) - 1) << USB_MF15_OUT_INT_POS) -#define USB_MF15_OUT_INT_UMSK (~(((1U << USB_MF15_OUT_INT_LEN) - 1) << USB_MF15_OUT_INT_POS)) -#define USB_MF15_SPK_INT USB_MF15_SPK_INT -#define USB_MF15_SPK_INT_POS (31U) -#define USB_MF15_SPK_INT_LEN (1U) -#define USB_MF15_SPK_INT_MSK (((1U << USB_MF15_SPK_INT_LEN) - 1) << USB_MF15_SPK_INT_POS) -#define USB_MF15_SPK_INT_UMSK (~(((1U << USB_MF15_SPK_INT_LEN) - 1) << USB_MF15_SPK_INT_POS)) - -/* 0x140 : DEV_IGR */ -#define USB_DEV_IGR_OFFSET (0x140) -#define USB_INT_G0 USB_INT_G0 -#define USB_INT_G0_POS (0U) -#define USB_INT_G0_LEN (1U) -#define USB_INT_G0_MSK (((1U << USB_INT_G0_LEN) - 1) << USB_INT_G0_POS) -#define USB_INT_G0_UMSK (~(((1U << USB_INT_G0_LEN) - 1) << USB_INT_G0_POS)) -#define USB_INT_G1 USB_INT_G1 -#define USB_INT_G1_POS (1U) -#define USB_INT_G1_LEN (1U) -#define USB_INT_G1_MSK (((1U << USB_INT_G1_LEN) - 1) << USB_INT_G1_POS) -#define USB_INT_G1_UMSK (~(((1U << USB_INT_G1_LEN) - 1) << USB_INT_G1_POS)) -#define USB_INT_G2_HOV USB_INT_G2_HOV -#define USB_INT_G2_HOV_POS (2U) -#define USB_INT_G2_HOV_LEN (1U) -#define USB_INT_G2_HOV_MSK (((1U << USB_INT_G2_HOV_LEN) - 1) << USB_INT_G2_HOV_POS) -#define USB_INT_G2_HOV_UMSK (~(((1U << USB_INT_G2_HOV_LEN) - 1) << USB_INT_G2_HOV_POS)) -#define USB_INT_G3 USB_INT_G3 -#define USB_INT_G3_POS (3U) -#define USB_INT_G3_LEN (1U) -#define USB_INT_G3_MSK (((1U << USB_INT_G3_LEN) - 1) << USB_INT_G3_POS) -#define USB_INT_G3_UMSK (~(((1U << USB_INT_G3_LEN) - 1) << USB_INT_G3_POS)) -#define USB_INT_G4 USB_INT_G4 -#define USB_INT_G4_POS (4U) -#define USB_INT_G4_LEN (1U) -#define USB_INT_G4_MSK (((1U << USB_INT_G4_LEN) - 1) << USB_INT_G4_POS) -#define USB_INT_G4_UMSK (~(((1U << USB_INT_G4_LEN) - 1) << USB_INT_G4_POS)) - -/* 0x144 : DEV_ISG0 */ -#define USB_DEV_ISG0_OFFSET (0x144) -#define USB_CX_SETUP_INT USB_CX_SETUP_INT -#define USB_CX_SETUP_INT_POS (0U) -#define USB_CX_SETUP_INT_LEN (1U) -#define USB_CX_SETUP_INT_MSK (((1U << USB_CX_SETUP_INT_LEN) - 1) << USB_CX_SETUP_INT_POS) -#define USB_CX_SETUP_INT_UMSK (~(((1U << USB_CX_SETUP_INT_LEN) - 1) << USB_CX_SETUP_INT_POS)) -#define USB_CX_IN_INT USB_CX_IN_INT -#define USB_CX_IN_INT_POS (1U) -#define USB_CX_IN_INT_LEN (1U) -#define USB_CX_IN_INT_MSK (((1U << USB_CX_IN_INT_LEN) - 1) << USB_CX_IN_INT_POS) -#define USB_CX_IN_INT_UMSK (~(((1U << USB_CX_IN_INT_LEN) - 1) << USB_CX_IN_INT_POS)) -#define USB_CX_OUT_INT USB_CX_OUT_INT -#define USB_CX_OUT_INT_POS (2U) -#define USB_CX_OUT_INT_LEN (1U) -#define USB_CX_OUT_INT_MSK (((1U << USB_CX_OUT_INT_LEN) - 1) << USB_CX_OUT_INT_POS) -#define USB_CX_OUT_INT_UMSK (~(((1U << USB_CX_OUT_INT_LEN) - 1) << USB_CX_OUT_INT_POS)) -#define USB_CX_COMFAIL_INT USB_CX_COMFAIL_INT -#define USB_CX_COMFAIL_INT_POS (4U) -#define USB_CX_COMFAIL_INT_LEN (1U) -#define USB_CX_COMFAIL_INT_MSK (((1U << USB_CX_COMFAIL_INT_LEN) - 1) << USB_CX_COMFAIL_INT_POS) -#define USB_CX_COMFAIL_INT_UMSK (~(((1U << USB_CX_COMFAIL_INT_LEN) - 1) << USB_CX_COMFAIL_INT_POS)) -#define USB_CX_COMABT_INT USB_CX_COMABT_INT -#define USB_CX_COMABT_INT_POS (5U) -#define USB_CX_COMABT_INT_LEN (1U) -#define USB_CX_COMABT_INT_MSK (((1U << USB_CX_COMABT_INT_LEN) - 1) << USB_CX_COMABT_INT_POS) -#define USB_CX_COMABT_INT_UMSK (~(((1U << USB_CX_COMABT_INT_LEN) - 1) << USB_CX_COMABT_INT_POS)) - -/* 0x148 : DEV_ISG1 */ -#define USB_DEV_ISG1_OFFSET (0x148) -#define USB_F0_OUT_INT USB_F0_OUT_INT -#define USB_F0_OUT_INT_POS (0U) -#define USB_F0_OUT_INT_LEN (1U) -#define USB_F0_OUT_INT_MSK (((1U << USB_F0_OUT_INT_LEN) - 1) << USB_F0_OUT_INT_POS) -#define USB_F0_OUT_INT_UMSK (~(((1U << USB_F0_OUT_INT_LEN) - 1) << USB_F0_OUT_INT_POS)) -#define USB_F0_SPK_INT USB_F0_SPK_INT -#define USB_F0_SPK_INT_POS (1U) -#define USB_F0_SPK_INT_LEN (1U) -#define USB_F0_SPK_INT_MSK (((1U << USB_F0_SPK_INT_LEN) - 1) << USB_F0_SPK_INT_POS) -#define USB_F0_SPK_INT_UMSK (~(((1U << USB_F0_SPK_INT_LEN) - 1) << USB_F0_SPK_INT_POS)) -#define USB_F1_OUT_INT USB_F1_OUT_INT -#define USB_F1_OUT_INT_POS (2U) -#define USB_F1_OUT_INT_LEN (1U) -#define USB_F1_OUT_INT_MSK (((1U << USB_F1_OUT_INT_LEN) - 1) << USB_F1_OUT_INT_POS) -#define USB_F1_OUT_INT_UMSK (~(((1U << USB_F1_OUT_INT_LEN) - 1) << USB_F1_OUT_INT_POS)) -#define USB_F1_SPK_INT USB_F1_SPK_INT -#define USB_F1_SPK_INT_POS (3U) -#define USB_F1_SPK_INT_LEN (1U) -#define USB_F1_SPK_INT_MSK (((1U << USB_F1_SPK_INT_LEN) - 1) << USB_F1_SPK_INT_POS) -#define USB_F1_SPK_INT_UMSK (~(((1U << USB_F1_SPK_INT_LEN) - 1) << USB_F1_SPK_INT_POS)) -#define USB_F2_OUT_INT USB_F2_OUT_INT -#define USB_F2_OUT_INT_POS (4U) -#define USB_F2_OUT_INT_LEN (1U) -#define USB_F2_OUT_INT_MSK (((1U << USB_F2_OUT_INT_LEN) - 1) << USB_F2_OUT_INT_POS) -#define USB_F2_OUT_INT_UMSK (~(((1U << USB_F2_OUT_INT_LEN) - 1) << USB_F2_OUT_INT_POS)) -#define USB_F2_SPK_INT USB_F2_SPK_INT -#define USB_F2_SPK_INT_POS (5U) -#define USB_F2_SPK_INT_LEN (1U) -#define USB_F2_SPK_INT_MSK (((1U << USB_F2_SPK_INT_LEN) - 1) << USB_F2_SPK_INT_POS) -#define USB_F2_SPK_INT_UMSK (~(((1U << USB_F2_SPK_INT_LEN) - 1) << USB_F2_SPK_INT_POS)) -#define USB_F3_OUT_INT USB_F3_OUT_INT -#define USB_F3_OUT_INT_POS (6U) -#define USB_F3_OUT_INT_LEN (1U) -#define USB_F3_OUT_INT_MSK (((1U << USB_F3_OUT_INT_LEN) - 1) << USB_F3_OUT_INT_POS) -#define USB_F3_OUT_INT_UMSK (~(((1U << USB_F3_OUT_INT_LEN) - 1) << USB_F3_OUT_INT_POS)) -#define USB_F3_SPK_INT USB_F3_SPK_INT -#define USB_F3_SPK_INT_POS (7U) -#define USB_F3_SPK_INT_LEN (1U) -#define USB_F3_SPK_INT_MSK (((1U << USB_F3_SPK_INT_LEN) - 1) << USB_F3_SPK_INT_POS) -#define USB_F3_SPK_INT_UMSK (~(((1U << USB_F3_SPK_INT_LEN) - 1) << USB_F3_SPK_INT_POS)) -#define USB_F4_OUT_INT USB_F4_OUT_INT -#define USB_F4_OUT_INT_POS (8U) -#define USB_F4_OUT_INT_LEN (1U) -#define USB_F4_OUT_INT_MSK (((1U << USB_F4_OUT_INT_LEN) - 1) << USB_F4_OUT_INT_POS) -#define USB_F4_OUT_INT_UMSK (~(((1U << USB_F4_OUT_INT_LEN) - 1) << USB_F4_OUT_INT_POS)) -#define USB_F4_SPK_INT USB_F4_SPK_INT -#define USB_F4_SPK_INT_POS (9U) -#define USB_F4_SPK_INT_LEN (1U) -#define USB_F4_SPK_INT_MSK (((1U << USB_F4_SPK_INT_LEN) - 1) << USB_F4_SPK_INT_POS) -#define USB_F4_SPK_INT_UMSK (~(((1U << USB_F4_SPK_INT_LEN) - 1) << USB_F4_SPK_INT_POS)) -#define USB_F5_OUT_INT USB_F5_OUT_INT -#define USB_F5_OUT_INT_POS (10U) -#define USB_F5_OUT_INT_LEN (1U) -#define USB_F5_OUT_INT_MSK (((1U << USB_F5_OUT_INT_LEN) - 1) << USB_F5_OUT_INT_POS) -#define USB_F5_OUT_INT_UMSK (~(((1U << USB_F5_OUT_INT_LEN) - 1) << USB_F5_OUT_INT_POS)) -#define USB_F5_SPK_INT USB_F5_SPK_INT -#define USB_F5_SPK_INT_POS (11U) -#define USB_F5_SPK_INT_LEN (1U) -#define USB_F5_SPK_INT_MSK (((1U << USB_F5_SPK_INT_LEN) - 1) << USB_F5_SPK_INT_POS) -#define USB_F5_SPK_INT_UMSK (~(((1U << USB_F5_SPK_INT_LEN) - 1) << USB_F5_SPK_INT_POS)) -#define USB_F6_OUT_INT USB_F6_OUT_INT -#define USB_F6_OUT_INT_POS (12U) -#define USB_F6_OUT_INT_LEN (1U) -#define USB_F6_OUT_INT_MSK (((1U << USB_F6_OUT_INT_LEN) - 1) << USB_F6_OUT_INT_POS) -#define USB_F6_OUT_INT_UMSK (~(((1U << USB_F6_OUT_INT_LEN) - 1) << USB_F6_OUT_INT_POS)) -#define USB_F6_SPK_INT USB_F6_SPK_INT -#define USB_F6_SPK_INT_POS (13U) -#define USB_F6_SPK_INT_LEN (1U) -#define USB_F6_SPK_INT_MSK (((1U << USB_F6_SPK_INT_LEN) - 1) << USB_F6_SPK_INT_POS) -#define USB_F6_SPK_INT_UMSK (~(((1U << USB_F6_SPK_INT_LEN) - 1) << USB_F6_SPK_INT_POS)) -#define USB_F7_OUT_INT USB_F7_OUT_INT -#define USB_F7_OUT_INT_POS (14U) -#define USB_F7_OUT_INT_LEN (1U) -#define USB_F7_OUT_INT_MSK (((1U << USB_F7_OUT_INT_LEN) - 1) << USB_F7_OUT_INT_POS) -#define USB_F7_OUT_INT_UMSK (~(((1U << USB_F7_OUT_INT_LEN) - 1) << USB_F7_OUT_INT_POS)) -#define USB_F7_SPK_INT USB_F7_SPK_INT -#define USB_F7_SPK_INT_POS (15U) -#define USB_F7_SPK_INT_LEN (1U) -#define USB_F7_SPK_INT_MSK (((1U << USB_F7_SPK_INT_LEN) - 1) << USB_F7_SPK_INT_POS) -#define USB_F7_SPK_INT_UMSK (~(((1U << USB_F7_SPK_INT_LEN) - 1) << USB_F7_SPK_INT_POS)) -#define USB_F0_IN_INT USB_F0_IN_INT -#define USB_F0_IN_INT_POS (16U) -#define USB_F0_IN_INT_LEN (1U) -#define USB_F0_IN_INT_MSK (((1U << USB_F0_IN_INT_LEN) - 1) << USB_F0_IN_INT_POS) -#define USB_F0_IN_INT_UMSK (~(((1U << USB_F0_IN_INT_LEN) - 1) << USB_F0_IN_INT_POS)) -#define USB_F1_IN_INT USB_F1_IN_INT -#define USB_F1_IN_INT_POS (17U) -#define USB_F1_IN_INT_LEN (1U) -#define USB_F1_IN_INT_MSK (((1U << USB_F1_IN_INT_LEN) - 1) << USB_F1_IN_INT_POS) -#define USB_F1_IN_INT_UMSK (~(((1U << USB_F1_IN_INT_LEN) - 1) << USB_F1_IN_INT_POS)) -#define USB_F2_IN_INT USB_F2_IN_INT -#define USB_F2_IN_INT_POS (18U) -#define USB_F2_IN_INT_LEN (1U) -#define USB_F2_IN_INT_MSK (((1U << USB_F2_IN_INT_LEN) - 1) << USB_F2_IN_INT_POS) -#define USB_F2_IN_INT_UMSK (~(((1U << USB_F2_IN_INT_LEN) - 1) << USB_F2_IN_INT_POS)) -#define USB_F3_IN_INT USB_F3_IN_INT -#define USB_F3_IN_INT_POS (19U) -#define USB_F3_IN_INT_LEN (1U) -#define USB_F3_IN_INT_MSK (((1U << USB_F3_IN_INT_LEN) - 1) << USB_F3_IN_INT_POS) -#define USB_F3_IN_INT_UMSK (~(((1U << USB_F3_IN_INT_LEN) - 1) << USB_F3_IN_INT_POS)) -#define USB_F4_IN_INT USB_F4_IN_INT -#define USB_F4_IN_INT_POS (20U) -#define USB_F4_IN_INT_LEN (1U) -#define USB_F4_IN_INT_MSK (((1U << USB_F4_IN_INT_LEN) - 1) << USB_F4_IN_INT_POS) -#define USB_F4_IN_INT_UMSK (~(((1U << USB_F4_IN_INT_LEN) - 1) << USB_F4_IN_INT_POS)) -#define USB_F5_IN_INT USB_F5_IN_INT -#define USB_F5_IN_INT_POS (21U) -#define USB_F5_IN_INT_LEN (1U) -#define USB_F5_IN_INT_MSK (((1U << USB_F5_IN_INT_LEN) - 1) << USB_F5_IN_INT_POS) -#define USB_F5_IN_INT_UMSK (~(((1U << USB_F5_IN_INT_LEN) - 1) << USB_F5_IN_INT_POS)) -#define USB_F6_IN_INT USB_F6_IN_INT -#define USB_F6_IN_INT_POS (22U) -#define USB_F6_IN_INT_LEN (1U) -#define USB_F6_IN_INT_MSK (((1U << USB_F6_IN_INT_LEN) - 1) << USB_F6_IN_INT_POS) -#define USB_F6_IN_INT_UMSK (~(((1U << USB_F6_IN_INT_LEN) - 1) << USB_F6_IN_INT_POS)) -#define USB_F7_IN_INT USB_F7_IN_INT -#define USB_F7_IN_INT_POS (23U) -#define USB_F7_IN_INT_LEN (1U) -#define USB_F7_IN_INT_MSK (((1U << USB_F7_IN_INT_LEN) - 1) << USB_F7_IN_INT_POS) -#define USB_F7_IN_INT_UMSK (~(((1U << USB_F7_IN_INT_LEN) - 1) << USB_F7_IN_INT_POS)) -#define USB_F8_IN_INT USB_F8_IN_INT -#define USB_F8_IN_INT_POS (24U) -#define USB_F8_IN_INT_LEN (1U) -#define USB_F8_IN_INT_MSK (((1U << USB_F8_IN_INT_LEN) - 1) << USB_F8_IN_INT_POS) -#define USB_F8_IN_INT_UMSK (~(((1U << USB_F8_IN_INT_LEN) - 1) << USB_F8_IN_INT_POS)) -#define USB_F9_IN_INT USB_F9_IN_INT -#define USB_F9_IN_INT_POS (25U) -#define USB_F9_IN_INT_LEN (1U) -#define USB_F9_IN_INT_MSK (((1U << USB_F9_IN_INT_LEN) - 1) << USB_F9_IN_INT_POS) -#define USB_F9_IN_INT_UMSK (~(((1U << USB_F9_IN_INT_LEN) - 1) << USB_F9_IN_INT_POS)) -#define USB_F10_IN_INT USB_F10_IN_INT -#define USB_F10_IN_INT_POS (26U) -#define USB_F10_IN_INT_LEN (1U) -#define USB_F10_IN_INT_MSK (((1U << USB_F10_IN_INT_LEN) - 1) << USB_F10_IN_INT_POS) -#define USB_F10_IN_INT_UMSK (~(((1U << USB_F10_IN_INT_LEN) - 1) << USB_F10_IN_INT_POS)) -#define USB_F11_IN_INT USB_F11_IN_INT -#define USB_F11_IN_INT_POS (27U) -#define USB_F11_IN_INT_LEN (1U) -#define USB_F11_IN_INT_MSK (((1U << USB_F11_IN_INT_LEN) - 1) << USB_F11_IN_INT_POS) -#define USB_F11_IN_INT_UMSK (~(((1U << USB_F11_IN_INT_LEN) - 1) << USB_F11_IN_INT_POS)) -#define USB_F12_IN_INT USB_F12_IN_INT -#define USB_F12_IN_INT_POS (28U) -#define USB_F12_IN_INT_LEN (1U) -#define USB_F12_IN_INT_MSK (((1U << USB_F12_IN_INT_LEN) - 1) << USB_F12_IN_INT_POS) -#define USB_F12_IN_INT_UMSK (~(((1U << USB_F12_IN_INT_LEN) - 1) << USB_F12_IN_INT_POS)) -#define USB_F13_IN_INT USB_F13_IN_INT -#define USB_F13_IN_INT_POS (29U) -#define USB_F13_IN_INT_LEN (1U) -#define USB_F13_IN_INT_MSK (((1U << USB_F13_IN_INT_LEN) - 1) << USB_F13_IN_INT_POS) -#define USB_F13_IN_INT_UMSK (~(((1U << USB_F13_IN_INT_LEN) - 1) << USB_F13_IN_INT_POS)) -#define USB_F14_IN_INT USB_F14_IN_INT -#define USB_F14_IN_INT_POS (30U) -#define USB_F14_IN_INT_LEN (1U) -#define USB_F14_IN_INT_MSK (((1U << USB_F14_IN_INT_LEN) - 1) << USB_F14_IN_INT_POS) -#define USB_F14_IN_INT_UMSK (~(((1U << USB_F14_IN_INT_LEN) - 1) << USB_F14_IN_INT_POS)) -#define USB_F15_IN_INT USB_F15_IN_INT -#define USB_F15_IN_INT_POS (31U) -#define USB_F15_IN_INT_LEN (1U) -#define USB_F15_IN_INT_MSK (((1U << USB_F15_IN_INT_LEN) - 1) << USB_F15_IN_INT_POS) -#define USB_F15_IN_INT_UMSK (~(((1U << USB_F15_IN_INT_LEN) - 1) << USB_F15_IN_INT_POS)) - -/* 0x14C : DEV_ISG2 */ -#define USB_DEV_ISG2_OFFSET (0x14C) -#define USBRST_INT USBRST_INT -#define USBRST_INT_POS (0U) -#define USBRST_INT_LEN (1U) -#define USBRST_INT_MSK (((1U << USBRST_INT_LEN) - 1) << USBRST_INT_POS) -#define USBRST_INT_UMSK (~(((1U << USBRST_INT_LEN) - 1) << USBRST_INT_POS)) -#define USB_SUSP_INT USB_SUSP_INT -#define USB_SUSP_INT_POS (1U) -#define USB_SUSP_INT_LEN (1U) -#define USB_SUSP_INT_MSK (((1U << USB_SUSP_INT_LEN) - 1) << USB_SUSP_INT_POS) -#define USB_SUSP_INT_UMSK (~(((1U << USB_SUSP_INT_LEN) - 1) << USB_SUSP_INT_POS)) -#define USB_RESM_INT USB_RESM_INT -#define USB_RESM_INT_POS (2U) -#define USB_RESM_INT_LEN (1U) -#define USB_RESM_INT_MSK (((1U << USB_RESM_INT_LEN) - 1) << USB_RESM_INT_POS) -#define USB_RESM_INT_UMSK (~(((1U << USB_RESM_INT_LEN) - 1) << USB_RESM_INT_POS)) -#define USB_ISO_SEQ_ERR_INT USB_ISO_SEQ_ERR_INT -#define USB_ISO_SEQ_ERR_INT_POS (3U) -#define USB_ISO_SEQ_ERR_INT_LEN (1U) -#define USB_ISO_SEQ_ERR_INT_MSK (((1U << USB_ISO_SEQ_ERR_INT_LEN) - 1) << USB_ISO_SEQ_ERR_INT_POS) -#define USB_ISO_SEQ_ERR_INT_UMSK (~(((1U << USB_ISO_SEQ_ERR_INT_LEN) - 1) << USB_ISO_SEQ_ERR_INT_POS)) -#define USB_ISO_SEQ_ABORT_INT USB_ISO_SEQ_ABORT_INT -#define USB_ISO_SEQ_ABORT_INT_POS (4U) -#define USB_ISO_SEQ_ABORT_INT_LEN (1U) -#define USB_ISO_SEQ_ABORT_INT_MSK (((1U << USB_ISO_SEQ_ABORT_INT_LEN) - 1) << USB_ISO_SEQ_ABORT_INT_POS) -#define USB_ISO_SEQ_ABORT_INT_UMSK (~(((1U << USB_ISO_SEQ_ABORT_INT_LEN) - 1) << USB_ISO_SEQ_ABORT_INT_POS)) -#define USB_TX0BYTE_INT USB_TX0BYTE_INT -#define USB_TX0BYTE_INT_POS (5U) -#define USB_TX0BYTE_INT_LEN (1U) -#define USB_TX0BYTE_INT_MSK (((1U << USB_TX0BYTE_INT_LEN) - 1) << USB_TX0BYTE_INT_POS) -#define USB_TX0BYTE_INT_UMSK (~(((1U << USB_TX0BYTE_INT_LEN) - 1) << USB_TX0BYTE_INT_POS)) -#define USB_RX0BYTE_INT USB_RX0BYTE_INT -#define USB_RX0BYTE_INT_POS (6U) -#define USB_RX0BYTE_INT_LEN (1U) -#define USB_RX0BYTE_INT_MSK (((1U << USB_RX0BYTE_INT_LEN) - 1) << USB_RX0BYTE_INT_POS) -#define USB_RX0BYTE_INT_UMSK (~(((1U << USB_RX0BYTE_INT_LEN) - 1) << USB_RX0BYTE_INT_POS)) -#define USB_DMA_CMPLT_HOV USB_DMA_CMPLT_HOV -#define USB_DMA_CMPLT_HOV_POS (7U) -#define USB_DMA_CMPLT_HOV_LEN (1U) -#define USB_DMA_CMPLT_HOV_MSK (((1U << USB_DMA_CMPLT_HOV_LEN) - 1) << USB_DMA_CMPLT_HOV_POS) -#define USB_DMA_CMPLT_HOV_UMSK (~(((1U << USB_DMA_CMPLT_HOV_LEN) - 1) << USB_DMA_CMPLT_HOV_POS)) -#define USB_DMA_ERROR_HOV USB_DMA_ERROR_HOV -#define USB_DMA_ERROR_HOV_POS (8U) -#define USB_DMA_ERROR_HOV_LEN (1U) -#define USB_DMA_ERROR_HOV_MSK (((1U << USB_DMA_ERROR_HOV_LEN) - 1) << USB_DMA_ERROR_HOV_POS) -#define USB_DMA_ERROR_HOV_UMSK (~(((1U << USB_DMA_ERROR_HOV_LEN) - 1) << USB_DMA_ERROR_HOV_POS)) -#define USB_DEV_IDLE_HOV USB_DEV_IDLE_HOV -#define USB_DEV_IDLE_HOV_POS (9U) -#define USB_DEV_IDLE_HOV_LEN (1U) -#define USB_DEV_IDLE_HOV_MSK (((1U << USB_DEV_IDLE_HOV_LEN) - 1) << USB_DEV_IDLE_HOV_POS) -#define USB_DEV_IDLE_HOV_UMSK (~(((1U << USB_DEV_IDLE_HOV_LEN) - 1) << USB_DEV_IDLE_HOV_POS)) -#define USB_DEV_WAKEUP_BYVBUS USB_DEV_WAKEUP_BYVBUS -#define USB_DEV_WAKEUP_BYVBUS_POS (10U) -#define USB_DEV_WAKEUP_BYVBUS_LEN (1U) -#define USB_DEV_WAKEUP_BYVBUS_MSK (((1U << USB_DEV_WAKEUP_BYVBUS_LEN) - 1) << USB_DEV_WAKEUP_BYVBUS_POS) -#define USB_DEV_WAKEUP_BYVBUS_UMSK (~(((1U << USB_DEV_WAKEUP_BYVBUS_LEN) - 1) << USB_DEV_WAKEUP_BYVBUS_POS)) -#define USB_F8_OUT_INT USB_F8_OUT_INT -#define USB_F8_OUT_INT_POS (16U) -#define USB_F8_OUT_INT_LEN (1U) -#define USB_F8_OUT_INT_MSK (((1U << USB_F8_OUT_INT_LEN) - 1) << USB_F8_OUT_INT_POS) -#define USB_F8_OUT_INT_UMSK (~(((1U << USB_F8_OUT_INT_LEN) - 1) << USB_F8_OUT_INT_POS)) -#define USB_F8_SPK_INT USB_F8_SPK_INT -#define USB_F8_SPK_INT_POS (17U) -#define USB_F8_SPK_INT_LEN (1U) -#define USB_F8_SPK_INT_MSK (((1U << USB_F8_SPK_INT_LEN) - 1) << USB_F8_SPK_INT_POS) -#define USB_F8_SPK_INT_UMSK (~(((1U << USB_F8_SPK_INT_LEN) - 1) << USB_F8_SPK_INT_POS)) -#define USB_F9_OUT_INT USB_F9_OUT_INT -#define USB_F9_OUT_INT_POS (18U) -#define USB_F9_OUT_INT_LEN (1U) -#define USB_F9_OUT_INT_MSK (((1U << USB_F9_OUT_INT_LEN) - 1) << USB_F9_OUT_INT_POS) -#define USB_F9_OUT_INT_UMSK (~(((1U << USB_F9_OUT_INT_LEN) - 1) << USB_F9_OUT_INT_POS)) -#define USB_F9_SPK_INT USB_F9_SPK_INT -#define USB_F9_SPK_INT_POS (19U) -#define USB_F9_SPK_INT_LEN (1U) -#define USB_F9_SPK_INT_MSK (((1U << USB_F9_SPK_INT_LEN) - 1) << USB_F9_SPK_INT_POS) -#define USB_F9_SPK_INT_UMSK (~(((1U << USB_F9_SPK_INT_LEN) - 1) << USB_F9_SPK_INT_POS)) -#define USB_F10_OUT_INT USB_F10_OUT_INT -#define USB_F10_OUT_INT_POS (20U) -#define USB_F10_OUT_INT_LEN (1U) -#define USB_F10_OUT_INT_MSK (((1U << USB_F10_OUT_INT_LEN) - 1) << USB_F10_OUT_INT_POS) -#define USB_F10_OUT_INT_UMSK (~(((1U << USB_F10_OUT_INT_LEN) - 1) << USB_F10_OUT_INT_POS)) -#define USB_F10_SPK_INT USB_F10_SPK_INT -#define USB_F10_SPK_INT_POS (21U) -#define USB_F10_SPK_INT_LEN (1U) -#define USB_F10_SPK_INT_MSK (((1U << USB_F10_SPK_INT_LEN) - 1) << USB_F10_SPK_INT_POS) -#define USB_F10_SPK_INT_UMSK (~(((1U << USB_F10_SPK_INT_LEN) - 1) << USB_F10_SPK_INT_POS)) -#define USB_F11_OUT_INT USB_F11_OUT_INT -#define USB_F11_OUT_INT_POS (22U) -#define USB_F11_OUT_INT_LEN (1U) -#define USB_F11_OUT_INT_MSK (((1U << USB_F11_OUT_INT_LEN) - 1) << USB_F11_OUT_INT_POS) -#define USB_F11_OUT_INT_UMSK (~(((1U << USB_F11_OUT_INT_LEN) - 1) << USB_F11_OUT_INT_POS)) -#define USB_F11_SPK_INT USB_F11_SPK_INT -#define USB_F11_SPK_INT_POS (23U) -#define USB_F11_SPK_INT_LEN (1U) -#define USB_F11_SPK_INT_MSK (((1U << USB_F11_SPK_INT_LEN) - 1) << USB_F11_SPK_INT_POS) -#define USB_F11_SPK_INT_UMSK (~(((1U << USB_F11_SPK_INT_LEN) - 1) << USB_F11_SPK_INT_POS)) -#define USB_F12_OUT_INT USB_F12_OUT_INT -#define USB_F12_OUT_INT_POS (24U) -#define USB_F12_OUT_INT_LEN (1U) -#define USB_F12_OUT_INT_MSK (((1U << USB_F12_OUT_INT_LEN) - 1) << USB_F12_OUT_INT_POS) -#define USB_F12_OUT_INT_UMSK (~(((1U << USB_F12_OUT_INT_LEN) - 1) << USB_F12_OUT_INT_POS)) -#define USB_F12_SPK_INT USB_F12_SPK_INT -#define USB_F12_SPK_INT_POS (25U) -#define USB_F12_SPK_INT_LEN (1U) -#define USB_F12_SPK_INT_MSK (((1U << USB_F12_SPK_INT_LEN) - 1) << USB_F12_SPK_INT_POS) -#define USB_F12_SPK_INT_UMSK (~(((1U << USB_F12_SPK_INT_LEN) - 1) << USB_F12_SPK_INT_POS)) -#define USB_F13_OUT_INT USB_F13_OUT_INT -#define USB_F13_OUT_INT_POS (26U) -#define USB_F13_OUT_INT_LEN (1U) -#define USB_F13_OUT_INT_MSK (((1U << USB_F13_OUT_INT_LEN) - 1) << USB_F13_OUT_INT_POS) -#define USB_F13_OUT_INT_UMSK (~(((1U << USB_F13_OUT_INT_LEN) - 1) << USB_F13_OUT_INT_POS)) -#define USB_F13_SPK_INT USB_F13_SPK_INT -#define USB_F13_SPK_INT_POS (27U) -#define USB_F13_SPK_INT_LEN (1U) -#define USB_F13_SPK_INT_MSK (((1U << USB_F13_SPK_INT_LEN) - 1) << USB_F13_SPK_INT_POS) -#define USB_F13_SPK_INT_UMSK (~(((1U << USB_F13_SPK_INT_LEN) - 1) << USB_F13_SPK_INT_POS)) -#define USB_F14_OUT_INT USB_F14_OUT_INT -#define USB_F14_OUT_INT_POS (28U) -#define USB_F14_OUT_INT_LEN (1U) -#define USB_F14_OUT_INT_MSK (((1U << USB_F14_OUT_INT_LEN) - 1) << USB_F14_OUT_INT_POS) -#define USB_F14_OUT_INT_UMSK (~(((1U << USB_F14_OUT_INT_LEN) - 1) << USB_F14_OUT_INT_POS)) -#define USB_F14_SPK_INT USB_F14_SPK_INT -#define USB_F14_SPK_INT_POS (29U) -#define USB_F14_SPK_INT_LEN (1U) -#define USB_F14_SPK_INT_MSK (((1U << USB_F14_SPK_INT_LEN) - 1) << USB_F14_SPK_INT_POS) -#define USB_F14_SPK_INT_UMSK (~(((1U << USB_F14_SPK_INT_LEN) - 1) << USB_F14_SPK_INT_POS)) -#define USB_F15_OUT_INT USB_F15_OUT_INT -#define USB_F15_OUT_INT_POS (30U) -#define USB_F15_OUT_INT_LEN (1U) -#define USB_F15_OUT_INT_MSK (((1U << USB_F15_OUT_INT_LEN) - 1) << USB_F15_OUT_INT_POS) -#define USB_F15_OUT_INT_UMSK (~(((1U << USB_F15_OUT_INT_LEN) - 1) << USB_F15_OUT_INT_POS)) -#define USB_F15_SPK_INT USB_F15_SPK_INT -#define USB_F15_SPK_INT_POS (31U) -#define USB_F15_SPK_INT_LEN (1U) -#define USB_F15_SPK_INT_MSK (((1U << USB_F15_SPK_INT_LEN) - 1) << USB_F15_SPK_INT_POS) -#define USB_F15_SPK_INT_UMSK (~(((1U << USB_F15_SPK_INT_LEN) - 1) << USB_F15_SPK_INT_POS)) - -/* 0x150 : DEV_RXZ */ -#define USB_DEV_RXZ_OFFSET (0x150) -#define USB_RX0BYTE_EP1 USB_RX0BYTE_EP1 -#define USB_RX0BYTE_EP1_POS (0U) -#define USB_RX0BYTE_EP1_LEN (1U) -#define USB_RX0BYTE_EP1_MSK (((1U << USB_RX0BYTE_EP1_LEN) - 1) << USB_RX0BYTE_EP1_POS) -#define USB_RX0BYTE_EP1_UMSK (~(((1U << USB_RX0BYTE_EP1_LEN) - 1) << USB_RX0BYTE_EP1_POS)) -#define USB_RX0BYTE_EP2 USB_RX0BYTE_EP2 -#define USB_RX0BYTE_EP2_POS (1U) -#define USB_RX0BYTE_EP2_LEN (1U) -#define USB_RX0BYTE_EP2_MSK (((1U << USB_RX0BYTE_EP2_LEN) - 1) << USB_RX0BYTE_EP2_POS) -#define USB_RX0BYTE_EP2_UMSK (~(((1U << USB_RX0BYTE_EP2_LEN) - 1) << USB_RX0BYTE_EP2_POS)) -#define USB_RX0BYTE_EP3 USB_RX0BYTE_EP3 -#define USB_RX0BYTE_EP3_POS (2U) -#define USB_RX0BYTE_EP3_LEN (1U) -#define USB_RX0BYTE_EP3_MSK (((1U << USB_RX0BYTE_EP3_LEN) - 1) << USB_RX0BYTE_EP3_POS) -#define USB_RX0BYTE_EP3_UMSK (~(((1U << USB_RX0BYTE_EP3_LEN) - 1) << USB_RX0BYTE_EP3_POS)) -#define USB_RX0BYTE_EP4 USB_RX0BYTE_EP4 -#define USB_RX0BYTE_EP4_POS (3U) -#define USB_RX0BYTE_EP4_LEN (1U) -#define USB_RX0BYTE_EP4_MSK (((1U << USB_RX0BYTE_EP4_LEN) - 1) << USB_RX0BYTE_EP4_POS) -#define USB_RX0BYTE_EP4_UMSK (~(((1U << USB_RX0BYTE_EP4_LEN) - 1) << USB_RX0BYTE_EP4_POS)) -#define USB_RX0BYTE_EP5 USB_RX0BYTE_EP5 -#define USB_RX0BYTE_EP5_POS (4U) -#define USB_RX0BYTE_EP5_LEN (1U) -#define USB_RX0BYTE_EP5_MSK (((1U << USB_RX0BYTE_EP5_LEN) - 1) << USB_RX0BYTE_EP5_POS) -#define USB_RX0BYTE_EP5_UMSK (~(((1U << USB_RX0BYTE_EP5_LEN) - 1) << USB_RX0BYTE_EP5_POS)) -#define USB_RX0BYTE_EP6 USB_RX0BYTE_EP6 -#define USB_RX0BYTE_EP6_POS (5U) -#define USB_RX0BYTE_EP6_LEN (1U) -#define USB_RX0BYTE_EP6_MSK (((1U << USB_RX0BYTE_EP6_LEN) - 1) << USB_RX0BYTE_EP6_POS) -#define USB_RX0BYTE_EP6_UMSK (~(((1U << USB_RX0BYTE_EP6_LEN) - 1) << USB_RX0BYTE_EP6_POS)) -#define USB_RX0BYTE_EP7 USB_RX0BYTE_EP7 -#define USB_RX0BYTE_EP7_POS (6U) -#define USB_RX0BYTE_EP7_LEN (1U) -#define USB_RX0BYTE_EP7_MSK (((1U << USB_RX0BYTE_EP7_LEN) - 1) << USB_RX0BYTE_EP7_POS) -#define USB_RX0BYTE_EP7_UMSK (~(((1U << USB_RX0BYTE_EP7_LEN) - 1) << USB_RX0BYTE_EP7_POS)) -#define USB_RX0BYTE_EP8 USB_RX0BYTE_EP8 -#define USB_RX0BYTE_EP8_POS (7U) -#define USB_RX0BYTE_EP8_LEN (1U) -#define USB_RX0BYTE_EP8_MSK (((1U << USB_RX0BYTE_EP8_LEN) - 1) << USB_RX0BYTE_EP8_POS) -#define USB_RX0BYTE_EP8_UMSK (~(((1U << USB_RX0BYTE_EP8_LEN) - 1) << USB_RX0BYTE_EP8_POS)) - -/* 0x154 : DEV_TXZ */ -#define USB_DEV_TXZ_OFFSET (0x154) -#define USB_TX0BYTE_EP1 USB_TX0BYTE_EP1 -#define USB_TX0BYTE_EP1_POS (0U) -#define USB_TX0BYTE_EP1_LEN (1U) -#define USB_TX0BYTE_EP1_MSK (((1U << USB_TX0BYTE_EP1_LEN) - 1) << USB_TX0BYTE_EP1_POS) -#define USB_TX0BYTE_EP1_UMSK (~(((1U << USB_TX0BYTE_EP1_LEN) - 1) << USB_TX0BYTE_EP1_POS)) -#define USB_TX0BYTE_EP2 USB_TX0BYTE_EP2 -#define USB_TX0BYTE_EP2_POS (1U) -#define USB_TX0BYTE_EP2_LEN (1U) -#define USB_TX0BYTE_EP2_MSK (((1U << USB_TX0BYTE_EP2_LEN) - 1) << USB_TX0BYTE_EP2_POS) -#define USB_TX0BYTE_EP2_UMSK (~(((1U << USB_TX0BYTE_EP2_LEN) - 1) << USB_TX0BYTE_EP2_POS)) -#define USB_TX0BYTE_EP3 USB_TX0BYTE_EP3 -#define USB_TX0BYTE_EP3_POS (2U) -#define USB_TX0BYTE_EP3_LEN (1U) -#define USB_TX0BYTE_EP3_MSK (((1U << USB_TX0BYTE_EP3_LEN) - 1) << USB_TX0BYTE_EP3_POS) -#define USB_TX0BYTE_EP3_UMSK (~(((1U << USB_TX0BYTE_EP3_LEN) - 1) << USB_TX0BYTE_EP3_POS)) -#define USB_TX0BYTE_EP4 USB_TX0BYTE_EP4 -#define USB_TX0BYTE_EP4_POS (3U) -#define USB_TX0BYTE_EP4_LEN (1U) -#define USB_TX0BYTE_EP4_MSK (((1U << USB_TX0BYTE_EP4_LEN) - 1) << USB_TX0BYTE_EP4_POS) -#define USB_TX0BYTE_EP4_UMSK (~(((1U << USB_TX0BYTE_EP4_LEN) - 1) << USB_TX0BYTE_EP4_POS)) -#define USB_TX0BYTE_EP5 USB_TX0BYTE_EP5 -#define USB_TX0BYTE_EP5_POS (4U) -#define USB_TX0BYTE_EP5_LEN (1U) -#define USB_TX0BYTE_EP5_MSK (((1U << USB_TX0BYTE_EP5_LEN) - 1) << USB_TX0BYTE_EP5_POS) -#define USB_TX0BYTE_EP5_UMSK (~(((1U << USB_TX0BYTE_EP5_LEN) - 1) << USB_TX0BYTE_EP5_POS)) -#define USB_TX0BYTE_EP6 USB_TX0BYTE_EP6 -#define USB_TX0BYTE_EP6_POS (5U) -#define USB_TX0BYTE_EP6_LEN (1U) -#define USB_TX0BYTE_EP6_MSK (((1U << USB_TX0BYTE_EP6_LEN) - 1) << USB_TX0BYTE_EP6_POS) -#define USB_TX0BYTE_EP6_UMSK (~(((1U << USB_TX0BYTE_EP6_LEN) - 1) << USB_TX0BYTE_EP6_POS)) -#define USB_TX0BYTE_EP7 USB_TX0BYTE_EP7 -#define USB_TX0BYTE_EP7_POS (6U) -#define USB_TX0BYTE_EP7_LEN (1U) -#define USB_TX0BYTE_EP7_MSK (((1U << USB_TX0BYTE_EP7_LEN) - 1) << USB_TX0BYTE_EP7_POS) -#define USB_TX0BYTE_EP7_UMSK (~(((1U << USB_TX0BYTE_EP7_LEN) - 1) << USB_TX0BYTE_EP7_POS)) -#define USB_TX0BYTE_EP8 USB_TX0BYTE_EP8 -#define USB_TX0BYTE_EP8_POS (7U) -#define USB_TX0BYTE_EP8_LEN (1U) -#define USB_TX0BYTE_EP8_MSK (((1U << USB_TX0BYTE_EP8_LEN) - 1) << USB_TX0BYTE_EP8_POS) -#define USB_TX0BYTE_EP8_UMSK (~(((1U << USB_TX0BYTE_EP8_LEN) - 1) << USB_TX0BYTE_EP8_POS)) - -/* 0x158 : DEV_ISE */ -#define USB_DEV_ISE_OFFSET (0x158) -#define USB_ISO_ABT_ERR_EP1 USB_ISO_ABT_ERR_EP1 -#define USB_ISO_ABT_ERR_EP1_POS (0U) -#define USB_ISO_ABT_ERR_EP1_LEN (1U) -#define USB_ISO_ABT_ERR_EP1_MSK (((1U << USB_ISO_ABT_ERR_EP1_LEN) - 1) << USB_ISO_ABT_ERR_EP1_POS) -#define USB_ISO_ABT_ERR_EP1_UMSK (~(((1U << USB_ISO_ABT_ERR_EP1_LEN) - 1) << USB_ISO_ABT_ERR_EP1_POS)) -#define USB_ISO_ABT_ERR_EP2 USB_ISO_ABT_ERR_EP2 -#define USB_ISO_ABT_ERR_EP2_POS (1U) -#define USB_ISO_ABT_ERR_EP2_LEN (1U) -#define USB_ISO_ABT_ERR_EP2_MSK (((1U << USB_ISO_ABT_ERR_EP2_LEN) - 1) << USB_ISO_ABT_ERR_EP2_POS) -#define USB_ISO_ABT_ERR_EP2_UMSK (~(((1U << USB_ISO_ABT_ERR_EP2_LEN) - 1) << USB_ISO_ABT_ERR_EP2_POS)) -#define USB_ISO_ABT_ERR_EP3 USB_ISO_ABT_ERR_EP3 -#define USB_ISO_ABT_ERR_EP3_POS (2U) -#define USB_ISO_ABT_ERR_EP3_LEN (1U) -#define USB_ISO_ABT_ERR_EP3_MSK (((1U << USB_ISO_ABT_ERR_EP3_LEN) - 1) << USB_ISO_ABT_ERR_EP3_POS) -#define USB_ISO_ABT_ERR_EP3_UMSK (~(((1U << USB_ISO_ABT_ERR_EP3_LEN) - 1) << USB_ISO_ABT_ERR_EP3_POS)) -#define USB_ISO_ABT_ERR_EP4 USB_ISO_ABT_ERR_EP4 -#define USB_ISO_ABT_ERR_EP4_POS (3U) -#define USB_ISO_ABT_ERR_EP4_LEN (1U) -#define USB_ISO_ABT_ERR_EP4_MSK (((1U << USB_ISO_ABT_ERR_EP4_LEN) - 1) << USB_ISO_ABT_ERR_EP4_POS) -#define USB_ISO_ABT_ERR_EP4_UMSK (~(((1U << USB_ISO_ABT_ERR_EP4_LEN) - 1) << USB_ISO_ABT_ERR_EP4_POS)) -#define USB_ISO_ABT_ERR_EP5 USB_ISO_ABT_ERR_EP5 -#define USB_ISO_ABT_ERR_EP5_POS (4U) -#define USB_ISO_ABT_ERR_EP5_LEN (1U) -#define USB_ISO_ABT_ERR_EP5_MSK (((1U << USB_ISO_ABT_ERR_EP5_LEN) - 1) << USB_ISO_ABT_ERR_EP5_POS) -#define USB_ISO_ABT_ERR_EP5_UMSK (~(((1U << USB_ISO_ABT_ERR_EP5_LEN) - 1) << USB_ISO_ABT_ERR_EP5_POS)) -#define USB_ISO_ABT_ERR_EP6 USB_ISO_ABT_ERR_EP6 -#define USB_ISO_ABT_ERR_EP6_POS (5U) -#define USB_ISO_ABT_ERR_EP6_LEN (1U) -#define USB_ISO_ABT_ERR_EP6_MSK (((1U << USB_ISO_ABT_ERR_EP6_LEN) - 1) << USB_ISO_ABT_ERR_EP6_POS) -#define USB_ISO_ABT_ERR_EP6_UMSK (~(((1U << USB_ISO_ABT_ERR_EP6_LEN) - 1) << USB_ISO_ABT_ERR_EP6_POS)) -#define USB_ISO_ABT_ERR_EP7 USB_ISO_ABT_ERR_EP7 -#define USB_ISO_ABT_ERR_EP7_POS (6U) -#define USB_ISO_ABT_ERR_EP7_LEN (1U) -#define USB_ISO_ABT_ERR_EP7_MSK (((1U << USB_ISO_ABT_ERR_EP7_LEN) - 1) << USB_ISO_ABT_ERR_EP7_POS) -#define USB_ISO_ABT_ERR_EP7_UMSK (~(((1U << USB_ISO_ABT_ERR_EP7_LEN) - 1) << USB_ISO_ABT_ERR_EP7_POS)) -#define USB_ISO_ABT_ERR_EP8 USB_ISO_ABT_ERR_EP8 -#define USB_ISO_ABT_ERR_EP8_POS (7U) -#define USB_ISO_ABT_ERR_EP8_LEN (1U) -#define USB_ISO_ABT_ERR_EP8_MSK (((1U << USB_ISO_ABT_ERR_EP8_LEN) - 1) << USB_ISO_ABT_ERR_EP8_POS) -#define USB_ISO_ABT_ERR_EP8_UMSK (~(((1U << USB_ISO_ABT_ERR_EP8_LEN) - 1) << USB_ISO_ABT_ERR_EP8_POS)) -#define USB_ISO_SEQ_ERR_EP1 USB_ISO_SEQ_ERR_EP1 -#define USB_ISO_SEQ_ERR_EP1_POS (16U) -#define USB_ISO_SEQ_ERR_EP1_LEN (1U) -#define USB_ISO_SEQ_ERR_EP1_MSK (((1U << USB_ISO_SEQ_ERR_EP1_LEN) - 1) << USB_ISO_SEQ_ERR_EP1_POS) -#define USB_ISO_SEQ_ERR_EP1_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP1_LEN) - 1) << USB_ISO_SEQ_ERR_EP1_POS)) -#define USB_ISO_SEQ_ERR_EP2 USB_ISO_SEQ_ERR_EP2 -#define USB_ISO_SEQ_ERR_EP2_POS (17U) -#define USB_ISO_SEQ_ERR_EP2_LEN (1U) -#define USB_ISO_SEQ_ERR_EP2_MSK (((1U << USB_ISO_SEQ_ERR_EP2_LEN) - 1) << USB_ISO_SEQ_ERR_EP2_POS) -#define USB_ISO_SEQ_ERR_EP2_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP2_LEN) - 1) << USB_ISO_SEQ_ERR_EP2_POS)) -#define USB_ISO_SEQ_ERR_EP3 USB_ISO_SEQ_ERR_EP3 -#define USB_ISO_SEQ_ERR_EP3_POS (18U) -#define USB_ISO_SEQ_ERR_EP3_LEN (1U) -#define USB_ISO_SEQ_ERR_EP3_MSK (((1U << USB_ISO_SEQ_ERR_EP3_LEN) - 1) << USB_ISO_SEQ_ERR_EP3_POS) -#define USB_ISO_SEQ_ERR_EP3_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP3_LEN) - 1) << USB_ISO_SEQ_ERR_EP3_POS)) -#define USB_ISO_SEQ_ERR_EP4 USB_ISO_SEQ_ERR_EP4 -#define USB_ISO_SEQ_ERR_EP4_POS (19U) -#define USB_ISO_SEQ_ERR_EP4_LEN (1U) -#define USB_ISO_SEQ_ERR_EP4_MSK (((1U << USB_ISO_SEQ_ERR_EP4_LEN) - 1) << USB_ISO_SEQ_ERR_EP4_POS) -#define USB_ISO_SEQ_ERR_EP4_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP4_LEN) - 1) << USB_ISO_SEQ_ERR_EP4_POS)) -#define USB_ISO_SEQ_ERR_EP5 USB_ISO_SEQ_ERR_EP5 -#define USB_ISO_SEQ_ERR_EP5_POS (20U) -#define USB_ISO_SEQ_ERR_EP5_LEN (1U) -#define USB_ISO_SEQ_ERR_EP5_MSK (((1U << USB_ISO_SEQ_ERR_EP5_LEN) - 1) << USB_ISO_SEQ_ERR_EP5_POS) -#define USB_ISO_SEQ_ERR_EP5_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP5_LEN) - 1) << USB_ISO_SEQ_ERR_EP5_POS)) -#define USB_ISO_SEQ_ERR_EP6 USB_ISO_SEQ_ERR_EP6 -#define USB_ISO_SEQ_ERR_EP6_POS (21U) -#define USB_ISO_SEQ_ERR_EP6_LEN (1U) -#define USB_ISO_SEQ_ERR_EP6_MSK (((1U << USB_ISO_SEQ_ERR_EP6_LEN) - 1) << USB_ISO_SEQ_ERR_EP6_POS) -#define USB_ISO_SEQ_ERR_EP6_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP6_LEN) - 1) << USB_ISO_SEQ_ERR_EP6_POS)) -#define USB_ISO_SEQ_ERR_EP7 USB_ISO_SEQ_ERR_EP7 -#define USB_ISO_SEQ_ERR_EP7_POS (22U) -#define USB_ISO_SEQ_ERR_EP7_LEN (1U) -#define USB_ISO_SEQ_ERR_EP7_MSK (((1U << USB_ISO_SEQ_ERR_EP7_LEN) - 1) << USB_ISO_SEQ_ERR_EP7_POS) -#define USB_ISO_SEQ_ERR_EP7_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP7_LEN) - 1) << USB_ISO_SEQ_ERR_EP7_POS)) -#define USB_ISO_SEQ_ERR_EP8 USB_ISO_SEQ_ERR_EP8 -#define USB_ISO_SEQ_ERR_EP8_POS (23U) -#define USB_ISO_SEQ_ERR_EP8_LEN (1U) -#define USB_ISO_SEQ_ERR_EP8_MSK (((1U << USB_ISO_SEQ_ERR_EP8_LEN) - 1) << USB_ISO_SEQ_ERR_EP8_POS) -#define USB_ISO_SEQ_ERR_EP8_UMSK (~(((1U << USB_ISO_SEQ_ERR_EP8_LEN) - 1) << USB_ISO_SEQ_ERR_EP8_POS)) - -/* 0x160 : DEV_INMPS1 */ -#define USB_DEV_INMPS1_OFFSET (0x160) -#define USB_MAXPS_IEP1 USB_MAXPS_IEP1 -#define USB_MAXPS_IEP1_POS (0U) -#define USB_MAXPS_IEP1_LEN (11U) -#define USB_MAXPS_IEP1_MSK (((1U << USB_MAXPS_IEP1_LEN) - 1) << USB_MAXPS_IEP1_POS) -#define USB_MAXPS_IEP1_UMSK (~(((1U << USB_MAXPS_IEP1_LEN) - 1) << USB_MAXPS_IEP1_POS)) -#define USB_STL_IEP1 USB_STL_IEP1 -#define USB_STL_IEP1_POS (11U) -#define USB_STL_IEP1_LEN (1U) -#define USB_STL_IEP1_MSK (((1U << USB_STL_IEP1_LEN) - 1) << USB_STL_IEP1_POS) -#define USB_STL_IEP1_UMSK (~(((1U << USB_STL_IEP1_LEN) - 1) << USB_STL_IEP1_POS)) -#define USB_RSTG_IEP1 USB_RSTG_IEP1 -#define USB_RSTG_IEP1_POS (12U) -#define USB_RSTG_IEP1_LEN (1U) -#define USB_RSTG_IEP1_MSK (((1U << USB_RSTG_IEP1_LEN) - 1) << USB_RSTG_IEP1_POS) -#define USB_RSTG_IEP1_UMSK (~(((1U << USB_RSTG_IEP1_LEN) - 1) << USB_RSTG_IEP1_POS)) -#define USB_TX_NUM_HBW_IEP1 USB_TX_NUM_HBW_IEP1 -#define USB_TX_NUM_HBW_IEP1_POS (13U) -#define USB_TX_NUM_HBW_IEP1_LEN (2U) -#define USB_TX_NUM_HBW_IEP1_MSK (((1U << USB_TX_NUM_HBW_IEP1_LEN) - 1) << USB_TX_NUM_HBW_IEP1_POS) -#define USB_TX_NUM_HBW_IEP1_UMSK (~(((1U << USB_TX_NUM_HBW_IEP1_LEN) - 1) << USB_TX_NUM_HBW_IEP1_POS)) -#define USB_TX0BYTE_IEP1 USB_TX0BYTE_IEP1 -#define USB_TX0BYTE_IEP1_POS (15U) -#define USB_TX0BYTE_IEP1_LEN (1U) -#define USB_TX0BYTE_IEP1_MSK (((1U << USB_TX0BYTE_IEP1_LEN) - 1) << USB_TX0BYTE_IEP1_POS) -#define USB_TX0BYTE_IEP1_UMSK (~(((1U << USB_TX0BYTE_IEP1_LEN) - 1) << USB_TX0BYTE_IEP1_POS)) - -/* 0x164 : DEV_INMPS2 */ -#define USB_DEV_INMPS2_OFFSET (0x164) -#define USB_MAXPS_IEP2 USB_MAXPS_IEP2 -#define USB_MAXPS_IEP2_POS (0U) -#define USB_MAXPS_IEP2_LEN (11U) -#define USB_MAXPS_IEP2_MSK (((1U << USB_MAXPS_IEP2_LEN) - 1) << USB_MAXPS_IEP2_POS) -#define USB_MAXPS_IEP2_UMSK (~(((1U << USB_MAXPS_IEP2_LEN) - 1) << USB_MAXPS_IEP2_POS)) -#define USB_STL_IEP2 USB_STL_IEP2 -#define USB_STL_IEP2_POS (11U) -#define USB_STL_IEP2_LEN (1U) -#define USB_STL_IEP2_MSK (((1U << USB_STL_IEP2_LEN) - 1) << USB_STL_IEP2_POS) -#define USB_STL_IEP2_UMSK (~(((1U << USB_STL_IEP2_LEN) - 1) << USB_STL_IEP2_POS)) -#define USB_RSTG_IEP2 USB_RSTG_IEP2 -#define USB_RSTG_IEP2_POS (12U) -#define USB_RSTG_IEP2_LEN (1U) -#define USB_RSTG_IEP2_MSK (((1U << USB_RSTG_IEP2_LEN) - 1) << USB_RSTG_IEP2_POS) -#define USB_RSTG_IEP2_UMSK (~(((1U << USB_RSTG_IEP2_LEN) - 1) << USB_RSTG_IEP2_POS)) -#define USB_TX_NUM_HBW_IEP2 USB_TX_NUM_HBW_IEP2 -#define USB_TX_NUM_HBW_IEP2_POS (13U) -#define USB_TX_NUM_HBW_IEP2_LEN (2U) -#define USB_TX_NUM_HBW_IEP2_MSK (((1U << USB_TX_NUM_HBW_IEP2_LEN) - 1) << USB_TX_NUM_HBW_IEP2_POS) -#define USB_TX_NUM_HBW_IEP2_UMSK (~(((1U << USB_TX_NUM_HBW_IEP2_LEN) - 1) << USB_TX_NUM_HBW_IEP2_POS)) -#define USB_TX0BYTE_IEP2 USB_TX0BYTE_IEP2 -#define USB_TX0BYTE_IEP2_POS (15U) -#define USB_TX0BYTE_IEP2_LEN (1U) -#define USB_TX0BYTE_IEP2_MSK (((1U << USB_TX0BYTE_IEP2_LEN) - 1) << USB_TX0BYTE_IEP2_POS) -#define USB_TX0BYTE_IEP2_UMSK (~(((1U << USB_TX0BYTE_IEP2_LEN) - 1) << USB_TX0BYTE_IEP2_POS)) - -/* 0x168 : DEV_INMPS3 */ -#define USB_DEV_INMPS3_OFFSET (0x168) -#define USB_MAXPS_IEP3 USB_MAXPS_IEP3 -#define USB_MAXPS_IEP3_POS (0U) -#define USB_MAXPS_IEP3_LEN (11U) -#define USB_MAXPS_IEP3_MSK (((1U << USB_MAXPS_IEP3_LEN) - 1) << USB_MAXPS_IEP3_POS) -#define USB_MAXPS_IEP3_UMSK (~(((1U << USB_MAXPS_IEP3_LEN) - 1) << USB_MAXPS_IEP3_POS)) -#define USB_STL_IEP3 USB_STL_IEP3 -#define USB_STL_IEP3_POS (11U) -#define USB_STL_IEP3_LEN (1U) -#define USB_STL_IEP3_MSK (((1U << USB_STL_IEP3_LEN) - 1) << USB_STL_IEP3_POS) -#define USB_STL_IEP3_UMSK (~(((1U << USB_STL_IEP3_LEN) - 1) << USB_STL_IEP3_POS)) -#define USB_RSTG_IEP3 USB_RSTG_IEP3 -#define USB_RSTG_IEP3_POS (12U) -#define USB_RSTG_IEP3_LEN (1U) -#define USB_RSTG_IEP3_MSK (((1U << USB_RSTG_IEP3_LEN) - 1) << USB_RSTG_IEP3_POS) -#define USB_RSTG_IEP3_UMSK (~(((1U << USB_RSTG_IEP3_LEN) - 1) << USB_RSTG_IEP3_POS)) -#define USB_TX_NUM_HBW_IEP3 USB_TX_NUM_HBW_IEP3 -#define USB_TX_NUM_HBW_IEP3_POS (13U) -#define USB_TX_NUM_HBW_IEP3_LEN (2U) -#define USB_TX_NUM_HBW_IEP3_MSK (((1U << USB_TX_NUM_HBW_IEP3_LEN) - 1) << USB_TX_NUM_HBW_IEP3_POS) -#define USB_TX_NUM_HBW_IEP3_UMSK (~(((1U << USB_TX_NUM_HBW_IEP3_LEN) - 1) << USB_TX_NUM_HBW_IEP3_POS)) -#define USB_TX0BYTE_IEP3 USB_TX0BYTE_IEP3 -#define USB_TX0BYTE_IEP3_POS (15U) -#define USB_TX0BYTE_IEP3_LEN (1U) -#define USB_TX0BYTE_IEP3_MSK (((1U << USB_TX0BYTE_IEP3_LEN) - 1) << USB_TX0BYTE_IEP3_POS) -#define USB_TX0BYTE_IEP3_UMSK (~(((1U << USB_TX0BYTE_IEP3_LEN) - 1) << USB_TX0BYTE_IEP3_POS)) - -/* 0x16C : DEV_INMPS4 */ -#define USB_DEV_INMPS4_OFFSET (0x16C) -#define USB_MAXPS_IEP4 USB_MAXPS_IEP4 -#define USB_MAXPS_IEP4_POS (0U) -#define USB_MAXPS_IEP4_LEN (11U) -#define USB_MAXPS_IEP4_MSK (((1U << USB_MAXPS_IEP4_LEN) - 1) << USB_MAXPS_IEP4_POS) -#define USB_MAXPS_IEP4_UMSK (~(((1U << USB_MAXPS_IEP4_LEN) - 1) << USB_MAXPS_IEP4_POS)) -#define USB_STL_IEP4 USB_STL_IEP4 -#define USB_STL_IEP4_POS (11U) -#define USB_STL_IEP4_LEN (1U) -#define USB_STL_IEP4_MSK (((1U << USB_STL_IEP4_LEN) - 1) << USB_STL_IEP4_POS) -#define USB_STL_IEP4_UMSK (~(((1U << USB_STL_IEP4_LEN) - 1) << USB_STL_IEP4_POS)) -#define USB_RSTG_IEP4 USB_RSTG_IEP4 -#define USB_RSTG_IEP4_POS (12U) -#define USB_RSTG_IEP4_LEN (1U) -#define USB_RSTG_IEP4_MSK (((1U << USB_RSTG_IEP4_LEN) - 1) << USB_RSTG_IEP4_POS) -#define USB_RSTG_IEP4_UMSK (~(((1U << USB_RSTG_IEP4_LEN) - 1) << USB_RSTG_IEP4_POS)) -#define USB_TX_NUM_HBW_IEP4 USB_TX_NUM_HBW_IEP4 -#define USB_TX_NUM_HBW_IEP4_POS (13U) -#define USB_TX_NUM_HBW_IEP4_LEN (2U) -#define USB_TX_NUM_HBW_IEP4_MSK (((1U << USB_TX_NUM_HBW_IEP4_LEN) - 1) << USB_TX_NUM_HBW_IEP4_POS) -#define USB_TX_NUM_HBW_IEP4_UMSK (~(((1U << USB_TX_NUM_HBW_IEP4_LEN) - 1) << USB_TX_NUM_HBW_IEP4_POS)) -#define USB_TX0BYTE_IEP4 USB_TX0BYTE_IEP4 -#define USB_TX0BYTE_IEP4_POS (15U) -#define USB_TX0BYTE_IEP4_LEN (1U) -#define USB_TX0BYTE_IEP4_MSK (((1U << USB_TX0BYTE_IEP4_LEN) - 1) << USB_TX0BYTE_IEP4_POS) -#define USB_TX0BYTE_IEP4_UMSK (~(((1U << USB_TX0BYTE_IEP4_LEN) - 1) << USB_TX0BYTE_IEP4_POS)) - -/* 0x170 : DEV_INMPS5 */ -#define USB_DEV_INMPS5_OFFSET (0x170) -#define USB_MAXPS_IEP5 USB_MAXPS_IEP5 -#define USB_MAXPS_IEP5_POS (0U) -#define USB_MAXPS_IEP5_LEN (11U) -#define USB_MAXPS_IEP5_MSK (((1U << USB_MAXPS_IEP5_LEN) - 1) << USB_MAXPS_IEP5_POS) -#define USB_MAXPS_IEP5_UMSK (~(((1U << USB_MAXPS_IEP5_LEN) - 1) << USB_MAXPS_IEP5_POS)) -#define USB_STL_IEP5 USB_STL_IEP5 -#define USB_STL_IEP5_POS (11U) -#define USB_STL_IEP5_LEN (1U) -#define USB_STL_IEP5_MSK (((1U << USB_STL_IEP5_LEN) - 1) << USB_STL_IEP5_POS) -#define USB_STL_IEP5_UMSK (~(((1U << USB_STL_IEP5_LEN) - 1) << USB_STL_IEP5_POS)) -#define USB_RSTG_IEP5 USB_RSTG_IEP5 -#define USB_RSTG_IEP5_POS (12U) -#define USB_RSTG_IEP5_LEN (1U) -#define USB_RSTG_IEP5_MSK (((1U << USB_RSTG_IEP5_LEN) - 1) << USB_RSTG_IEP5_POS) -#define USB_RSTG_IEP5_UMSK (~(((1U << USB_RSTG_IEP5_LEN) - 1) << USB_RSTG_IEP5_POS)) -#define USB_TX_NUM_HBW_IEP5 USB_TX_NUM_HBW_IEP5 -#define USB_TX_NUM_HBW_IEP5_POS (13U) -#define USB_TX_NUM_HBW_IEP5_LEN (2U) -#define USB_TX_NUM_HBW_IEP5_MSK (((1U << USB_TX_NUM_HBW_IEP5_LEN) - 1) << USB_TX_NUM_HBW_IEP5_POS) -#define USB_TX_NUM_HBW_IEP5_UMSK (~(((1U << USB_TX_NUM_HBW_IEP5_LEN) - 1) << USB_TX_NUM_HBW_IEP5_POS)) -#define USB_TX0BYTE_IEP5 USB_TX0BYTE_IEP5 -#define USB_TX0BYTE_IEP5_POS (15U) -#define USB_TX0BYTE_IEP5_LEN (1U) -#define USB_TX0BYTE_IEP5_MSK (((1U << USB_TX0BYTE_IEP5_LEN) - 1) << USB_TX0BYTE_IEP5_POS) -#define USB_TX0BYTE_IEP5_UMSK (~(((1U << USB_TX0BYTE_IEP5_LEN) - 1) << USB_TX0BYTE_IEP5_POS)) - -/* 0x174 : DEV_INMPS6 */ -#define USB_DEV_INMPS6_OFFSET (0x174) -#define USB_MAXPS_IEP6 USB_MAXPS_IEP6 -#define USB_MAXPS_IEP6_POS (0U) -#define USB_MAXPS_IEP6_LEN (11U) -#define USB_MAXPS_IEP6_MSK (((1U << USB_MAXPS_IEP6_LEN) - 1) << USB_MAXPS_IEP6_POS) -#define USB_MAXPS_IEP6_UMSK (~(((1U << USB_MAXPS_IEP6_LEN) - 1) << USB_MAXPS_IEP6_POS)) -#define USB_STL_IEP6 USB_STL_IEP6 -#define USB_STL_IEP6_POS (11U) -#define USB_STL_IEP6_LEN (1U) -#define USB_STL_IEP6_MSK (((1U << USB_STL_IEP6_LEN) - 1) << USB_STL_IEP6_POS) -#define USB_STL_IEP6_UMSK (~(((1U << USB_STL_IEP6_LEN) - 1) << USB_STL_IEP6_POS)) -#define USB_RSTG_IEP6 USB_RSTG_IEP6 -#define USB_RSTG_IEP6_POS (12U) -#define USB_RSTG_IEP6_LEN (1U) -#define USB_RSTG_IEP6_MSK (((1U << USB_RSTG_IEP6_LEN) - 1) << USB_RSTG_IEP6_POS) -#define USB_RSTG_IEP6_UMSK (~(((1U << USB_RSTG_IEP6_LEN) - 1) << USB_RSTG_IEP6_POS)) -#define USB_TX_NUM_HBW_IEP6 USB_TX_NUM_HBW_IEP6 -#define USB_TX_NUM_HBW_IEP6_POS (13U) -#define USB_TX_NUM_HBW_IEP6_LEN (2U) -#define USB_TX_NUM_HBW_IEP6_MSK (((1U << USB_TX_NUM_HBW_IEP6_LEN) - 1) << USB_TX_NUM_HBW_IEP6_POS) -#define USB_TX_NUM_HBW_IEP6_UMSK (~(((1U << USB_TX_NUM_HBW_IEP6_LEN) - 1) << USB_TX_NUM_HBW_IEP6_POS)) -#define USB_TX0BYTE_IEP6 USB_TX0BYTE_IEP6 -#define USB_TX0BYTE_IEP6_POS (15U) -#define USB_TX0BYTE_IEP6_LEN (1U) -#define USB_TX0BYTE_IEP6_MSK (((1U << USB_TX0BYTE_IEP6_LEN) - 1) << USB_TX0BYTE_IEP6_POS) -#define USB_TX0BYTE_IEP6_UMSK (~(((1U << USB_TX0BYTE_IEP6_LEN) - 1) << USB_TX0BYTE_IEP6_POS)) - -/* 0x178 : DEV_INMPS7 */ -#define USB_DEV_INMPS7_OFFSET (0x178) -#define USB_MAXPS_IEP7 USB_MAXPS_IEP7 -#define USB_MAXPS_IEP7_POS (0U) -#define USB_MAXPS_IEP7_LEN (11U) -#define USB_MAXPS_IEP7_MSK (((1U << USB_MAXPS_IEP7_LEN) - 1) << USB_MAXPS_IEP7_POS) -#define USB_MAXPS_IEP7_UMSK (~(((1U << USB_MAXPS_IEP7_LEN) - 1) << USB_MAXPS_IEP7_POS)) -#define USB_STL_IEP7 USB_STL_IEP7 -#define USB_STL_IEP7_POS (11U) -#define USB_STL_IEP7_LEN (1U) -#define USB_STL_IEP7_MSK (((1U << USB_STL_IEP7_LEN) - 1) << USB_STL_IEP7_POS) -#define USB_STL_IEP7_UMSK (~(((1U << USB_STL_IEP7_LEN) - 1) << USB_STL_IEP7_POS)) -#define USB_RSTG_IEP7 USB_RSTG_IEP7 -#define USB_RSTG_IEP7_POS (12U) -#define USB_RSTG_IEP7_LEN (1U) -#define USB_RSTG_IEP7_MSK (((1U << USB_RSTG_IEP7_LEN) - 1) << USB_RSTG_IEP7_POS) -#define USB_RSTG_IEP7_UMSK (~(((1U << USB_RSTG_IEP7_LEN) - 1) << USB_RSTG_IEP7_POS)) -#define USB_TX_NUM_HBW_IEP7 USB_TX_NUM_HBW_IEP7 -#define USB_TX_NUM_HBW_IEP7_POS (13U) -#define USB_TX_NUM_HBW_IEP7_LEN (2U) -#define USB_TX_NUM_HBW_IEP7_MSK (((1U << USB_TX_NUM_HBW_IEP7_LEN) - 1) << USB_TX_NUM_HBW_IEP7_POS) -#define USB_TX_NUM_HBW_IEP7_UMSK (~(((1U << USB_TX_NUM_HBW_IEP7_LEN) - 1) << USB_TX_NUM_HBW_IEP7_POS)) -#define USB_TX0BYTE_IEP7 USB_TX0BYTE_IEP7 -#define USB_TX0BYTE_IEP7_POS (15U) -#define USB_TX0BYTE_IEP7_LEN (1U) -#define USB_TX0BYTE_IEP7_MSK (((1U << USB_TX0BYTE_IEP7_LEN) - 1) << USB_TX0BYTE_IEP7_POS) -#define USB_TX0BYTE_IEP7_UMSK (~(((1U << USB_TX0BYTE_IEP7_LEN) - 1) << USB_TX0BYTE_IEP7_POS)) - -/* 0x17C : DEV_INMPS8 */ -#define USB_DEV_INMPS8_OFFSET (0x17C) -#define USB_MAXPS_IEP8 USB_MAXPS_IEP8 -#define USB_MAXPS_IEP8_POS (0U) -#define USB_MAXPS_IEP8_LEN (11U) -#define USB_MAXPS_IEP8_MSK (((1U << USB_MAXPS_IEP8_LEN) - 1) << USB_MAXPS_IEP8_POS) -#define USB_MAXPS_IEP8_UMSK (~(((1U << USB_MAXPS_IEP8_LEN) - 1) << USB_MAXPS_IEP8_POS)) -#define USB_STL_IEP8 USB_STL_IEP8 -#define USB_STL_IEP8_POS (11U) -#define USB_STL_IEP8_LEN (1U) -#define USB_STL_IEP8_MSK (((1U << USB_STL_IEP8_LEN) - 1) << USB_STL_IEP8_POS) -#define USB_STL_IEP8_UMSK (~(((1U << USB_STL_IEP8_LEN) - 1) << USB_STL_IEP8_POS)) -#define USB_RSTG_IEP8 USB_RSTG_IEP8 -#define USB_RSTG_IEP8_POS (12U) -#define USB_RSTG_IEP8_LEN (1U) -#define USB_RSTG_IEP8_MSK (((1U << USB_RSTG_IEP8_LEN) - 1) << USB_RSTG_IEP8_POS) -#define USB_RSTG_IEP8_UMSK (~(((1U << USB_RSTG_IEP8_LEN) - 1) << USB_RSTG_IEP8_POS)) -#define USB_TX_NUM_HBW_IEP8 USB_TX_NUM_HBW_IEP8 -#define USB_TX_NUM_HBW_IEP8_POS (13U) -#define USB_TX_NUM_HBW_IEP8_LEN (2U) -#define USB_TX_NUM_HBW_IEP8_MSK (((1U << USB_TX_NUM_HBW_IEP8_LEN) - 1) << USB_TX_NUM_HBW_IEP8_POS) -#define USB_TX_NUM_HBW_IEP8_UMSK (~(((1U << USB_TX_NUM_HBW_IEP8_LEN) - 1) << USB_TX_NUM_HBW_IEP8_POS)) -#define USB_TX0BYTE_IEP8 USB_TX0BYTE_IEP8 -#define USB_TX0BYTE_IEP8_POS (15U) -#define USB_TX0BYTE_IEP8_LEN (1U) -#define USB_TX0BYTE_IEP8_MSK (((1U << USB_TX0BYTE_IEP8_LEN) - 1) << USB_TX0BYTE_IEP8_POS) -#define USB_TX0BYTE_IEP8_UMSK (~(((1U << USB_TX0BYTE_IEP8_LEN) - 1) << USB_TX0BYTE_IEP8_POS)) - -/* 0x180 : DEV_OUTMPS1 */ -#define USB_DEV_OUTMPS1_OFFSET (0x180) -#define USB_MAXPS_OEP1 USB_MAXPS_OEP1 -#define USB_MAXPS_OEP1_POS (0U) -#define USB_MAXPS_OEP1_LEN (11U) -#define USB_MAXPS_OEP1_MSK (((1U << USB_MAXPS_OEP1_LEN) - 1) << USB_MAXPS_OEP1_POS) -#define USB_MAXPS_OEP1_UMSK (~(((1U << USB_MAXPS_OEP1_LEN) - 1) << USB_MAXPS_OEP1_POS)) -#define USB_STL_OEP1 USB_STL_OEP1 -#define USB_STL_OEP1_POS (11U) -#define USB_STL_OEP1_LEN (1U) -#define USB_STL_OEP1_MSK (((1U << USB_STL_OEP1_LEN) - 1) << USB_STL_OEP1_POS) -#define USB_STL_OEP1_UMSK (~(((1U << USB_STL_OEP1_LEN) - 1) << USB_STL_OEP1_POS)) -#define USB_RSTG_OEP1 USB_RSTG_OEP1 -#define USB_RSTG_OEP1_POS (12U) -#define USB_RSTG_OEP1_LEN (1U) -#define USB_RSTG_OEP1_MSK (((1U << USB_RSTG_OEP1_LEN) - 1) << USB_RSTG_OEP1_POS) -#define USB_RSTG_OEP1_UMSK (~(((1U << USB_RSTG_OEP1_LEN) - 1) << USB_RSTG_OEP1_POS)) - -/* 0x184 : DEV_OUTMPS2 */ -#define USB_DEV_OUTMPS2_OFFSET (0x184) -#define USB_MAXPS_OEP2 USB_MAXPS_OEP2 -#define USB_MAXPS_OEP2_POS (0U) -#define USB_MAXPS_OEP2_LEN (11U) -#define USB_MAXPS_OEP2_MSK (((1U << USB_MAXPS_OEP2_LEN) - 1) << USB_MAXPS_OEP2_POS) -#define USB_MAXPS_OEP2_UMSK (~(((1U << USB_MAXPS_OEP2_LEN) - 1) << USB_MAXPS_OEP2_POS)) -#define USB_STL_OEP2 USB_STL_OEP2 -#define USB_STL_OEP2_POS (11U) -#define USB_STL_OEP2_LEN (1U) -#define USB_STL_OEP2_MSK (((1U << USB_STL_OEP2_LEN) - 1) << USB_STL_OEP2_POS) -#define USB_STL_OEP2_UMSK (~(((1U << USB_STL_OEP2_LEN) - 1) << USB_STL_OEP2_POS)) -#define USB_RSTG_OEP2 USB_RSTG_OEP2 -#define USB_RSTG_OEP2_POS (12U) -#define USB_RSTG_OEP2_LEN (1U) -#define USB_RSTG_OEP2_MSK (((1U << USB_RSTG_OEP2_LEN) - 1) << USB_RSTG_OEP2_POS) -#define USB_RSTG_OEP2_UMSK (~(((1U << USB_RSTG_OEP2_LEN) - 1) << USB_RSTG_OEP2_POS)) - -/* 0x188 : DEV_OUTMPS3 */ -#define USB_DEV_OUTMPS3_OFFSET (0x188) -#define USB_MAXPS_OEP3 USB_MAXPS_OEP3 -#define USB_MAXPS_OEP3_POS (0U) -#define USB_MAXPS_OEP3_LEN (11U) -#define USB_MAXPS_OEP3_MSK (((1U << USB_MAXPS_OEP3_LEN) - 1) << USB_MAXPS_OEP3_POS) -#define USB_MAXPS_OEP3_UMSK (~(((1U << USB_MAXPS_OEP3_LEN) - 1) << USB_MAXPS_OEP3_POS)) -#define USB_STL_OEP3 USB_STL_OEP3 -#define USB_STL_OEP3_POS (11U) -#define USB_STL_OEP3_LEN (1U) -#define USB_STL_OEP3_MSK (((1U << USB_STL_OEP3_LEN) - 1) << USB_STL_OEP3_POS) -#define USB_STL_OEP3_UMSK (~(((1U << USB_STL_OEP3_LEN) - 1) << USB_STL_OEP3_POS)) -#define USB_RSTG_OEP3 USB_RSTG_OEP3 -#define USB_RSTG_OEP3_POS (12U) -#define USB_RSTG_OEP3_LEN (1U) -#define USB_RSTG_OEP3_MSK (((1U << USB_RSTG_OEP3_LEN) - 1) << USB_RSTG_OEP3_POS) -#define USB_RSTG_OEP3_UMSK (~(((1U << USB_RSTG_OEP3_LEN) - 1) << USB_RSTG_OEP3_POS)) - -/* 0x18C : DEV_OUTMPS4 */ -#define USB_DEV_OUTMPS4_OFFSET (0x18C) -#define USB_MAXPS_OEP4 USB_MAXPS_OEP4 -#define USB_MAXPS_OEP4_POS (0U) -#define USB_MAXPS_OEP4_LEN (11U) -#define USB_MAXPS_OEP4_MSK (((1U << USB_MAXPS_OEP4_LEN) - 1) << USB_MAXPS_OEP4_POS) -#define USB_MAXPS_OEP4_UMSK (~(((1U << USB_MAXPS_OEP4_LEN) - 1) << USB_MAXPS_OEP4_POS)) -#define USB_STL_OEP4 USB_STL_OEP4 -#define USB_STL_OEP4_POS (11U) -#define USB_STL_OEP4_LEN (1U) -#define USB_STL_OEP4_MSK (((1U << USB_STL_OEP4_LEN) - 1) << USB_STL_OEP4_POS) -#define USB_STL_OEP4_UMSK (~(((1U << USB_STL_OEP4_LEN) - 1) << USB_STL_OEP4_POS)) -#define USB_RSTG_OEP4 USB_RSTG_OEP4 -#define USB_RSTG_OEP4_POS (12U) -#define USB_RSTG_OEP4_LEN (1U) -#define USB_RSTG_OEP4_MSK (((1U << USB_RSTG_OEP4_LEN) - 1) << USB_RSTG_OEP4_POS) -#define USB_RSTG_OEP4_UMSK (~(((1U << USB_RSTG_OEP4_LEN) - 1) << USB_RSTG_OEP4_POS)) - -/* 0x190 : DEV_OUTMPS5 */ -#define USB_DEV_OUTMPS5_OFFSET (0x190) -#define USB_MAXPS_OEP5 USB_MAXPS_OEP5 -#define USB_MAXPS_OEP5_POS (0U) -#define USB_MAXPS_OEP5_LEN (11U) -#define USB_MAXPS_OEP5_MSK (((1U << USB_MAXPS_OEP5_LEN) - 1) << USB_MAXPS_OEP5_POS) -#define USB_MAXPS_OEP5_UMSK (~(((1U << USB_MAXPS_OEP5_LEN) - 1) << USB_MAXPS_OEP5_POS)) -#define USB_STL_OEP5 USB_STL_OEP5 -#define USB_STL_OEP5_POS (11U) -#define USB_STL_OEP5_LEN (1U) -#define USB_STL_OEP5_MSK (((1U << USB_STL_OEP5_LEN) - 1) << USB_STL_OEP5_POS) -#define USB_STL_OEP5_UMSK (~(((1U << USB_STL_OEP5_LEN) - 1) << USB_STL_OEP5_POS)) -#define USB_RSTG_OEP5 USB_RSTG_OEP5 -#define USB_RSTG_OEP5_POS (12U) -#define USB_RSTG_OEP5_LEN (1U) -#define USB_RSTG_OEP5_MSK (((1U << USB_RSTG_OEP5_LEN) - 1) << USB_RSTG_OEP5_POS) -#define USB_RSTG_OEP5_UMSK (~(((1U << USB_RSTG_OEP5_LEN) - 1) << USB_RSTG_OEP5_POS)) - -/* 0x194 : DEV_OUTMPS6 */ -#define USB_DEV_OUTMPS6_OFFSET (0x194) -#define USB_MAXPS_OEP6 USB_MAXPS_OEP6 -#define USB_MAXPS_OEP6_POS (0U) -#define USB_MAXPS_OEP6_LEN (11U) -#define USB_MAXPS_OEP6_MSK (((1U << USB_MAXPS_OEP6_LEN) - 1) << USB_MAXPS_OEP6_POS) -#define USB_MAXPS_OEP6_UMSK (~(((1U << USB_MAXPS_OEP6_LEN) - 1) << USB_MAXPS_OEP6_POS)) -#define USB_STL_OEP6 USB_STL_OEP6 -#define USB_STL_OEP6_POS (11U) -#define USB_STL_OEP6_LEN (1U) -#define USB_STL_OEP6_MSK (((1U << USB_STL_OEP6_LEN) - 1) << USB_STL_OEP6_POS) -#define USB_STL_OEP6_UMSK (~(((1U << USB_STL_OEP6_LEN) - 1) << USB_STL_OEP6_POS)) -#define USB_RSTG_OEP6 USB_RSTG_OEP6 -#define USB_RSTG_OEP6_POS (12U) -#define USB_RSTG_OEP6_LEN (1U) -#define USB_RSTG_OEP6_MSK (((1U << USB_RSTG_OEP6_LEN) - 1) << USB_RSTG_OEP6_POS) -#define USB_RSTG_OEP6_UMSK (~(((1U << USB_RSTG_OEP6_LEN) - 1) << USB_RSTG_OEP6_POS)) - -/* 0x198 : DEV_OUTMPS7 */ -#define USB_DEV_OUTMPS7_OFFSET (0x198) -#define USB_MAXPS_OEP7 USB_MAXPS_OEP7 -#define USB_MAXPS_OEP7_POS (0U) -#define USB_MAXPS_OEP7_LEN (11U) -#define USB_MAXPS_OEP7_MSK (((1U << USB_MAXPS_OEP7_LEN) - 1) << USB_MAXPS_OEP7_POS) -#define USB_MAXPS_OEP7_UMSK (~(((1U << USB_MAXPS_OEP7_LEN) - 1) << USB_MAXPS_OEP7_POS)) -#define USB_STL_OEP7 USB_STL_OEP7 -#define USB_STL_OEP7_POS (11U) -#define USB_STL_OEP7_LEN (1U) -#define USB_STL_OEP7_MSK (((1U << USB_STL_OEP7_LEN) - 1) << USB_STL_OEP7_POS) -#define USB_STL_OEP7_UMSK (~(((1U << USB_STL_OEP7_LEN) - 1) << USB_STL_OEP7_POS)) -#define USB_RSTG_OEP7 USB_RSTG_OEP7 -#define USB_RSTG_OEP7_POS (12U) -#define USB_RSTG_OEP7_LEN (1U) -#define USB_RSTG_OEP7_MSK (((1U << USB_RSTG_OEP7_LEN) - 1) << USB_RSTG_OEP7_POS) -#define USB_RSTG_OEP7_UMSK (~(((1U << USB_RSTG_OEP7_LEN) - 1) << USB_RSTG_OEP7_POS)) - -/* 0x19C : DEV_OUTMPS8 */ -#define USB_DEV_OUTMPS8_OFFSET (0x19C) -#define USB_MAXPS_OEP8 USB_MAXPS_OEP8 -#define USB_MAXPS_OEP8_POS (0U) -#define USB_MAXPS_OEP8_LEN (11U) -#define USB_MAXPS_OEP8_MSK (((1U << USB_MAXPS_OEP8_LEN) - 1) << USB_MAXPS_OEP8_POS) -#define USB_MAXPS_OEP8_UMSK (~(((1U << USB_MAXPS_OEP8_LEN) - 1) << USB_MAXPS_OEP8_POS)) -#define USB_STL_OEP8 USB_STL_OEP8 -#define USB_STL_OEP8_POS (11U) -#define USB_STL_OEP8_LEN (1U) -#define USB_STL_OEP8_MSK (((1U << USB_STL_OEP8_LEN) - 1) << USB_STL_OEP8_POS) -#define USB_STL_OEP8_UMSK (~(((1U << USB_STL_OEP8_LEN) - 1) << USB_STL_OEP8_POS)) -#define USB_RSTG_OEP8 USB_RSTG_OEP8 -#define USB_RSTG_OEP8_POS (12U) -#define USB_RSTG_OEP8_LEN (1U) -#define USB_RSTG_OEP8_MSK (((1U << USB_RSTG_OEP8_LEN) - 1) << USB_RSTG_OEP8_POS) -#define USB_RSTG_OEP8_UMSK (~(((1U << USB_RSTG_OEP8_LEN) - 1) << USB_RSTG_OEP8_POS)) - -/* 0x1A0 : DEV_EPMAP0 */ -#define USB_DEV_EPMAP0_OFFSET (0x1A0) -#define USB_FNO_IEP1 USB_FNO_IEP1 -#define USB_FNO_IEP1_POS (0U) -#define USB_FNO_IEP1_LEN (4U) -#define USB_FNO_IEP1_MSK (((1U << USB_FNO_IEP1_LEN) - 1) << USB_FNO_IEP1_POS) -#define USB_FNO_IEP1_UMSK (~(((1U << USB_FNO_IEP1_LEN) - 1) << USB_FNO_IEP1_POS)) -#define USB_FNO_OEP1 USB_FNO_OEP1 -#define USB_FNO_OEP1_POS (4U) -#define USB_FNO_OEP1_LEN (4U) -#define USB_FNO_OEP1_MSK (((1U << USB_FNO_OEP1_LEN) - 1) << USB_FNO_OEP1_POS) -#define USB_FNO_OEP1_UMSK (~(((1U << USB_FNO_OEP1_LEN) - 1) << USB_FNO_OEP1_POS)) -#define USB_FNO_IEP2 USB_FNO_IEP2 -#define USB_FNO_IEP2_POS (8U) -#define USB_FNO_IEP2_LEN (4U) -#define USB_FNO_IEP2_MSK (((1U << USB_FNO_IEP2_LEN) - 1) << USB_FNO_IEP2_POS) -#define USB_FNO_IEP2_UMSK (~(((1U << USB_FNO_IEP2_LEN) - 1) << USB_FNO_IEP2_POS)) -#define USB_FNO_OEP2 USB_FNO_OEP2 -#define USB_FNO_OEP2_POS (12U) -#define USB_FNO_OEP2_LEN (4U) -#define USB_FNO_OEP2_MSK (((1U << USB_FNO_OEP2_LEN) - 1) << USB_FNO_OEP2_POS) -#define USB_FNO_OEP2_UMSK (~(((1U << USB_FNO_OEP2_LEN) - 1) << USB_FNO_OEP2_POS)) -#define USB_FNO_IEP3 USB_FNO_IEP3 -#define USB_FNO_IEP3_POS (16U) -#define USB_FNO_IEP3_LEN (4U) -#define USB_FNO_IEP3_MSK (((1U << USB_FNO_IEP3_LEN) - 1) << USB_FNO_IEP3_POS) -#define USB_FNO_IEP3_UMSK (~(((1U << USB_FNO_IEP3_LEN) - 1) << USB_FNO_IEP3_POS)) -#define USB_FNO_OEP3 USB_FNO_OEP3 -#define USB_FNO_OEP3_POS (20U) -#define USB_FNO_OEP3_LEN (4U) -#define USB_FNO_OEP3_MSK (((1U << USB_FNO_OEP3_LEN) - 1) << USB_FNO_OEP3_POS) -#define USB_FNO_OEP3_UMSK (~(((1U << USB_FNO_OEP3_LEN) - 1) << USB_FNO_OEP3_POS)) -#define USB_FNO_IEP4 USB_FNO_IEP4 -#define USB_FNO_IEP4_POS (24U) -#define USB_FNO_IEP4_LEN (4U) -#define USB_FNO_IEP4_MSK (((1U << USB_FNO_IEP4_LEN) - 1) << USB_FNO_IEP4_POS) -#define USB_FNO_IEP4_UMSK (~(((1U << USB_FNO_IEP4_LEN) - 1) << USB_FNO_IEP4_POS)) -#define USB_FNO_OEP4 USB_FNO_OEP4 -#define USB_FNO_OEP4_POS (28U) -#define USB_FNO_OEP4_LEN (4U) -#define USB_FNO_OEP4_MSK (((1U << USB_FNO_OEP4_LEN) - 1) << USB_FNO_OEP4_POS) -#define USB_FNO_OEP4_UMSK (~(((1U << USB_FNO_OEP4_LEN) - 1) << USB_FNO_OEP4_POS)) - -/* 0x1A4 : DEV_EPMAP1 */ -#define USB_DEV_EPMAP1_OFFSET (0x1A4) -#define USB_FNO_IEP5 USB_FNO_IEP5 -#define USB_FNO_IEP5_POS (0U) -#define USB_FNO_IEP5_LEN (4U) -#define USB_FNO_IEP5_MSK (((1U << USB_FNO_IEP5_LEN) - 1) << USB_FNO_IEP5_POS) -#define USB_FNO_IEP5_UMSK (~(((1U << USB_FNO_IEP5_LEN) - 1) << USB_FNO_IEP5_POS)) -#define USB_FNO_OEP5 USB_FNO_OEP5 -#define USB_FNO_OEP5_POS (4U) -#define USB_FNO_OEP5_LEN (4U) -#define USB_FNO_OEP5_MSK (((1U << USB_FNO_OEP5_LEN) - 1) << USB_FNO_OEP5_POS) -#define USB_FNO_OEP5_UMSK (~(((1U << USB_FNO_OEP5_LEN) - 1) << USB_FNO_OEP5_POS)) -#define USB_FNO_IEP6 USB_FNO_IEP6 -#define USB_FNO_IEP6_POS (8U) -#define USB_FNO_IEP6_LEN (4U) -#define USB_FNO_IEP6_MSK (((1U << USB_FNO_IEP6_LEN) - 1) << USB_FNO_IEP6_POS) -#define USB_FNO_IEP6_UMSK (~(((1U << USB_FNO_IEP6_LEN) - 1) << USB_FNO_IEP6_POS)) -#define USB_FNO_OEP6 USB_FNO_OEP6 -#define USB_FNO_OEP6_POS (12U) -#define USB_FNO_OEP6_LEN (4U) -#define USB_FNO_OEP6_MSK (((1U << USB_FNO_OEP6_LEN) - 1) << USB_FNO_OEP6_POS) -#define USB_FNO_OEP6_UMSK (~(((1U << USB_FNO_OEP6_LEN) - 1) << USB_FNO_OEP6_POS)) -#define USB_FNO_IEP7 USB_FNO_IEP7 -#define USB_FNO_IEP7_POS (16U) -#define USB_FNO_IEP7_LEN (4U) -#define USB_FNO_IEP7_MSK (((1U << USB_FNO_IEP7_LEN) - 1) << USB_FNO_IEP7_POS) -#define USB_FNO_IEP7_UMSK (~(((1U << USB_FNO_IEP7_LEN) - 1) << USB_FNO_IEP7_POS)) -#define USB_FNO_OEP7 USB_FNO_OEP7 -#define USB_FNO_OEP7_POS (20U) -#define USB_FNO_OEP7_LEN (4U) -#define USB_FNO_OEP7_MSK (((1U << USB_FNO_OEP7_LEN) - 1) << USB_FNO_OEP7_POS) -#define USB_FNO_OEP7_UMSK (~(((1U << USB_FNO_OEP7_LEN) - 1) << USB_FNO_OEP7_POS)) -#define USB_FNO_IEP8 USB_FNO_IEP8 -#define USB_FNO_IEP8_POS (24U) -#define USB_FNO_IEP8_LEN (4U) -#define USB_FNO_IEP8_MSK (((1U << USB_FNO_IEP8_LEN) - 1) << USB_FNO_IEP8_POS) -#define USB_FNO_IEP8_UMSK (~(((1U << USB_FNO_IEP8_LEN) - 1) << USB_FNO_IEP8_POS)) -#define USB_FNO_OEP8 USB_FNO_OEP8 -#define USB_FNO_OEP8_POS (28U) -#define USB_FNO_OEP8_LEN (4U) -#define USB_FNO_OEP8_MSK (((1U << USB_FNO_OEP8_LEN) - 1) << USB_FNO_OEP8_POS) -#define USB_FNO_OEP8_UMSK (~(((1U << USB_FNO_OEP8_LEN) - 1) << USB_FNO_OEP8_POS)) - -/* 0x1A8 : DEV_FMAP */ -#define USB_DEV_FMAP_OFFSET (0x1A8) -#define USB_EPNO_FIFO0 USB_EPNO_FIFO0 -#define USB_EPNO_FIFO0_POS (0U) -#define USB_EPNO_FIFO0_LEN (4U) -#define USB_EPNO_FIFO0_MSK (((1U << USB_EPNO_FIFO0_LEN) - 1) << USB_EPNO_FIFO0_POS) -#define USB_EPNO_FIFO0_UMSK (~(((1U << USB_EPNO_FIFO0_LEN) - 1) << USB_EPNO_FIFO0_POS)) -#define USB_DIR_FIFO0 USB_DIR_FIFO0 -#define USB_DIR_FIFO0_POS (4U) -#define USB_DIR_FIFO0_LEN (2U) -#define USB_DIR_FIFO0_MSK (((1U << USB_DIR_FIFO0_LEN) - 1) << USB_DIR_FIFO0_POS) -#define USB_DIR_FIFO0_UMSK (~(((1U << USB_DIR_FIFO0_LEN) - 1) << USB_DIR_FIFO0_POS)) -#define USB_EPNO_FIFO1 USB_EPNO_FIFO1 -#define USB_EPNO_FIFO1_POS (8U) -#define USB_EPNO_FIFO1_LEN (4U) -#define USB_EPNO_FIFO1_MSK (((1U << USB_EPNO_FIFO1_LEN) - 1) << USB_EPNO_FIFO1_POS) -#define USB_EPNO_FIFO1_UMSK (~(((1U << USB_EPNO_FIFO1_LEN) - 1) << USB_EPNO_FIFO1_POS)) -#define USB_DIR_FIFO1 USB_DIR_FIFO1 -#define USB_DIR_FIFO1_POS (12U) -#define USB_DIR_FIFO1_LEN (2U) -#define USB_DIR_FIFO1_MSK (((1U << USB_DIR_FIFO1_LEN) - 1) << USB_DIR_FIFO1_POS) -#define USB_DIR_FIFO1_UMSK (~(((1U << USB_DIR_FIFO1_LEN) - 1) << USB_DIR_FIFO1_POS)) -#define USB_EPNO_FIFO2 USB_EPNO_FIFO2 -#define USB_EPNO_FIFO2_POS (16U) -#define USB_EPNO_FIFO2_LEN (4U) -#define USB_EPNO_FIFO2_MSK (((1U << USB_EPNO_FIFO2_LEN) - 1) << USB_EPNO_FIFO2_POS) -#define USB_EPNO_FIFO2_UMSK (~(((1U << USB_EPNO_FIFO2_LEN) - 1) << USB_EPNO_FIFO2_POS)) -#define USB_DIR_FIFO2 USB_DIR_FIFO2 -#define USB_DIR_FIFO2_POS (20U) -#define USB_DIR_FIFO2_LEN (2U) -#define USB_DIR_FIFO2_MSK (((1U << USB_DIR_FIFO2_LEN) - 1) << USB_DIR_FIFO2_POS) -#define USB_DIR_FIFO2_UMSK (~(((1U << USB_DIR_FIFO2_LEN) - 1) << USB_DIR_FIFO2_POS)) -#define USB_EPNO_FIFO3 USB_EPNO_FIFO3 -#define USB_EPNO_FIFO3_POS (24U) -#define USB_EPNO_FIFO3_LEN (4U) -#define USB_EPNO_FIFO3_MSK (((1U << USB_EPNO_FIFO3_LEN) - 1) << USB_EPNO_FIFO3_POS) -#define USB_EPNO_FIFO3_UMSK (~(((1U << USB_EPNO_FIFO3_LEN) - 1) << USB_EPNO_FIFO3_POS)) -#define USB_DIR_FIFO3 USB_DIR_FIFO3 -#define USB_DIR_FIFO3_POS (28U) -#define USB_DIR_FIFO3_LEN (2U) -#define USB_DIR_FIFO3_MSK (((1U << USB_DIR_FIFO3_LEN) - 1) << USB_DIR_FIFO3_POS) -#define USB_DIR_FIFO3_UMSK (~(((1U << USB_DIR_FIFO3_LEN) - 1) << USB_DIR_FIFO3_POS)) - -/* 0x1AC : DEV_FCFG */ -#define USB_DEV_FCFG_OFFSET (0x1AC) -#define USB_BLK_TYP_F0 USB_BLK_TYP_F0 -#define USB_BLK_TYP_F0_POS (0U) -#define USB_BLK_TYP_F0_LEN (2U) -#define USB_BLK_TYP_F0_MSK (((1U << USB_BLK_TYP_F0_LEN) - 1) << USB_BLK_TYP_F0_POS) -#define USB_BLK_TYP_F0_UMSK (~(((1U << USB_BLK_TYP_F0_LEN) - 1) << USB_BLK_TYP_F0_POS)) -#define USB_BLKNO_F0 USB_BLKNO_F0 -#define USB_BLKNO_F0_POS (2U) -#define USB_BLKNO_F0_LEN (2U) -#define USB_BLKNO_F0_MSK (((1U << USB_BLKNO_F0_LEN) - 1) << USB_BLKNO_F0_POS) -#define USB_BLKNO_F0_UMSK (~(((1U << USB_BLKNO_F0_LEN) - 1) << USB_BLKNO_F0_POS)) -#define USB_BLKSZ_F0 USB_BLKSZ_F0 -#define USB_BLKSZ_F0_POS (4U) -#define USB_BLKSZ_F0_LEN (1U) -#define USB_BLKSZ_F0_MSK (((1U << USB_BLKSZ_F0_LEN) - 1) << USB_BLKSZ_F0_POS) -#define USB_BLKSZ_F0_UMSK (~(((1U << USB_BLKSZ_F0_LEN) - 1) << USB_BLKSZ_F0_POS)) -#define USB_EN_F0 USB_EN_F0 -#define USB_EN_F0_POS (5U) -#define USB_EN_F0_LEN (1U) -#define USB_EN_F0_MSK (((1U << USB_EN_F0_LEN) - 1) << USB_EN_F0_POS) -#define USB_EN_F0_UMSK (~(((1U << USB_EN_F0_LEN) - 1) << USB_EN_F0_POS)) -#define USB_BLK_TYP_F1 USB_BLK_TYP_F1 -#define USB_BLK_TYP_F1_POS (8U) -#define USB_BLK_TYP_F1_LEN (2U) -#define USB_BLK_TYP_F1_MSK (((1U << USB_BLK_TYP_F1_LEN) - 1) << USB_BLK_TYP_F1_POS) -#define USB_BLK_TYP_F1_UMSK (~(((1U << USB_BLK_TYP_F1_LEN) - 1) << USB_BLK_TYP_F1_POS)) -#define USB_BLKNO_F1 USB_BLKNO_F1 -#define USB_BLKNO_F1_POS (10U) -#define USB_BLKNO_F1_LEN (2U) -#define USB_BLKNO_F1_MSK (((1U << USB_BLKNO_F1_LEN) - 1) << USB_BLKNO_F1_POS) -#define USB_BLKNO_F1_UMSK (~(((1U << USB_BLKNO_F1_LEN) - 1) << USB_BLKNO_F1_POS)) -#define USB_BLKSZ_F1 USB_BLKSZ_F1 -#define USB_BLKSZ_F1_POS (12U) -#define USB_BLKSZ_F1_LEN (1U) -#define USB_BLKSZ_F1_MSK (((1U << USB_BLKSZ_F1_LEN) - 1) << USB_BLKSZ_F1_POS) -#define USB_BLKSZ_F1_UMSK (~(((1U << USB_BLKSZ_F1_LEN) - 1) << USB_BLKSZ_F1_POS)) -#define USB_EN_F1 USB_EN_F1 -#define USB_EN_F1_POS (13U) -#define USB_EN_F1_LEN (1U) -#define USB_EN_F1_MSK (((1U << USB_EN_F1_LEN) - 1) << USB_EN_F1_POS) -#define USB_EN_F1_UMSK (~(((1U << USB_EN_F1_LEN) - 1) << USB_EN_F1_POS)) -#define USB_BLK_TYP_F2 USB_BLK_TYP_F2 -#define USB_BLK_TYP_F2_POS (16U) -#define USB_BLK_TYP_F2_LEN (2U) -#define USB_BLK_TYP_F2_MSK (((1U << USB_BLK_TYP_F2_LEN) - 1) << USB_BLK_TYP_F2_POS) -#define USB_BLK_TYP_F2_UMSK (~(((1U << USB_BLK_TYP_F2_LEN) - 1) << USB_BLK_TYP_F2_POS)) -#define USB_BLKNO_F2 USB_BLKNO_F2 -#define USB_BLKNO_F2_POS (18U) -#define USB_BLKNO_F2_LEN (2U) -#define USB_BLKNO_F2_MSK (((1U << USB_BLKNO_F2_LEN) - 1) << USB_BLKNO_F2_POS) -#define USB_BLKNO_F2_UMSK (~(((1U << USB_BLKNO_F2_LEN) - 1) << USB_BLKNO_F2_POS)) -#define USB_BLKSZ_F2 USB_BLKSZ_F2 -#define USB_BLKSZ_F2_POS (20U) -#define USB_BLKSZ_F2_LEN (1U) -#define USB_BLKSZ_F2_MSK (((1U << USB_BLKSZ_F2_LEN) - 1) << USB_BLKSZ_F2_POS) -#define USB_BLKSZ_F2_UMSK (~(((1U << USB_BLKSZ_F2_LEN) - 1) << USB_BLKSZ_F2_POS)) -#define USB_EN_F2 USB_EN_F2 -#define USB_EN_F2_POS (21U) -#define USB_EN_F2_LEN (1U) -#define USB_EN_F2_MSK (((1U << USB_EN_F2_LEN) - 1) << USB_EN_F2_POS) -#define USB_EN_F2_UMSK (~(((1U << USB_EN_F2_LEN) - 1) << USB_EN_F2_POS)) -#define USB_BLK_TYP_F3 USB_BLK_TYP_F3 -#define USB_BLK_TYP_F3_POS (24U) -#define USB_BLK_TYP_F3_LEN (2U) -#define USB_BLK_TYP_F3_MSK (((1U << USB_BLK_TYP_F3_LEN) - 1) << USB_BLK_TYP_F3_POS) -#define USB_BLK_TYP_F3_UMSK (~(((1U << USB_BLK_TYP_F3_LEN) - 1) << USB_BLK_TYP_F3_POS)) -#define USB_BLKNO_F3 USB_BLKNO_F3 -#define USB_BLKNO_F3_POS (26U) -#define USB_BLKNO_F3_LEN (2U) -#define USB_BLKNO_F3_MSK (((1U << USB_BLKNO_F3_LEN) - 1) << USB_BLKNO_F3_POS) -#define USB_BLKNO_F3_UMSK (~(((1U << USB_BLKNO_F3_LEN) - 1) << USB_BLKNO_F3_POS)) -#define USB_BLKSZ_F3 USB_BLKSZ_F3 -#define USB_BLKSZ_F3_POS (28U) -#define USB_BLKSZ_F3_LEN (1U) -#define USB_BLKSZ_F3_MSK (((1U << USB_BLKSZ_F3_LEN) - 1) << USB_BLKSZ_F3_POS) -#define USB_BLKSZ_F3_UMSK (~(((1U << USB_BLKSZ_F3_LEN) - 1) << USB_BLKSZ_F3_POS)) -#define USB_EN_F3 USB_EN_F3 -#define USB_EN_F3_POS (29U) -#define USB_EN_F3_LEN (1U) -#define USB_EN_F3_MSK (((1U << USB_EN_F3_LEN) - 1) << USB_EN_F3_POS) -#define USB_EN_F3_UMSK (~(((1U << USB_EN_F3_LEN) - 1) << USB_EN_F3_POS)) - -/* 0x1B0 : DEV_FIBC0 */ -#define USB_DEV_FIBC0_OFFSET (0x1B0) -#define USB_BC_F0 USB_BC_F0 -#define USB_BC_F0_POS (0U) -#define USB_BC_F0_LEN (11U) -#define USB_BC_F0_MSK (((1U << USB_BC_F0_LEN) - 1) << USB_BC_F0_POS) -#define USB_BC_F0_UMSK (~(((1U << USB_BC_F0_LEN) - 1) << USB_BC_F0_POS)) -#define USB_FFRST0_HOV USB_FFRST0_HOV -#define USB_FFRST0_HOV_POS (12U) -#define USB_FFRST0_HOV_LEN (1U) -#define USB_FFRST0_HOV_MSK (((1U << USB_FFRST0_HOV_LEN) - 1) << USB_FFRST0_HOV_POS) -#define USB_FFRST0_HOV_UMSK (~(((1U << USB_FFRST0_HOV_LEN) - 1) << USB_FFRST0_HOV_POS)) - -/* 0x1B4 : DEV_FIBC1 */ -#define USB_DEV_FIBC1_OFFSET (0x1B4) -#define USB_BC_F1 USB_BC_F1 -#define USB_BC_F1_POS (0U) -#define USB_BC_F1_LEN (11U) -#define USB_BC_F1_MSK (((1U << USB_BC_F1_LEN) - 1) << USB_BC_F1_POS) -#define USB_BC_F1_UMSK (~(((1U << USB_BC_F1_LEN) - 1) << USB_BC_F1_POS)) -#define USB_FFRST1_HOV USB_FFRST1_HOV -#define USB_FFRST1_HOV_POS (12U) -#define USB_FFRST1_HOV_LEN (1U) -#define USB_FFRST1_HOV_MSK (((1U << USB_FFRST1_HOV_LEN) - 1) << USB_FFRST1_HOV_POS) -#define USB_FFRST1_HOV_UMSK (~(((1U << USB_FFRST1_HOV_LEN) - 1) << USB_FFRST1_HOV_POS)) - -/* 0x1B8 : DEV_FIBC2 */ -#define USB_DEV_FIBC2_OFFSET (0x1B8) -#define USB_BC_F2 USB_BC_F2 -#define USB_BC_F2_POS (0U) -#define USB_BC_F2_LEN (11U) -#define USB_BC_F2_MSK (((1U << USB_BC_F2_LEN) - 1) << USB_BC_F2_POS) -#define USB_BC_F2_UMSK (~(((1U << USB_BC_F2_LEN) - 1) << USB_BC_F2_POS)) -#define USB_FFRST2_HOV USB_FFRST2_HOV -#define USB_FFRST2_HOV_POS (12U) -#define USB_FFRST2_HOV_LEN (1U) -#define USB_FFRST2_HOV_MSK (((1U << USB_FFRST2_HOV_LEN) - 1) << USB_FFRST2_HOV_POS) -#define USB_FFRST2_HOV_UMSK (~(((1U << USB_FFRST2_HOV_LEN) - 1) << USB_FFRST2_HOV_POS)) - -/* 0x1BC : DEV_FIBC3 */ -#define USB_DEV_FIBC3_OFFSET (0x1BC) -#define USB_BC_F3 USB_BC_F3 -#define USB_BC_F3_POS (0U) -#define USB_BC_F3_LEN (11U) -#define USB_BC_F3_MSK (((1U << USB_BC_F3_LEN) - 1) << USB_BC_F3_POS) -#define USB_BC_F3_UMSK (~(((1U << USB_BC_F3_LEN) - 1) << USB_BC_F3_POS)) -#define USB_FFRST3_HOV USB_FFRST3_HOV -#define USB_FFRST3_HOV_POS (12U) -#define USB_FFRST3_HOV_LEN (1U) -#define USB_FFRST3_HOV_MSK (((1U << USB_FFRST3_HOV_LEN) - 1) << USB_FFRST3_HOV_POS) -#define USB_FFRST3_HOV_UMSK (~(((1U << USB_FFRST3_HOV_LEN) - 1) << USB_FFRST3_HOV_POS)) - -/* 0x1C0 : DMA_TFN */ -#define USB_DMA_TFN_OFFSET (0x1C0) -#define USB_ACC_F0_HOV USB_ACC_F0_HOV -#define USB_ACC_F0_HOV_POS (0U) -#define USB_ACC_F0_HOV_LEN (1U) -#define USB_ACC_F0_HOV_MSK (((1U << USB_ACC_F0_HOV_LEN) - 1) << USB_ACC_F0_HOV_POS) -#define USB_ACC_F0_HOV_UMSK (~(((1U << USB_ACC_F0_HOV_LEN) - 1) << USB_ACC_F0_HOV_POS)) -#define USB_ACC_F1_HOV USB_ACC_F1_HOV -#define USB_ACC_F1_HOV_POS (1U) -#define USB_ACC_F1_HOV_LEN (1U) -#define USB_ACC_F1_HOV_MSK (((1U << USB_ACC_F1_HOV_LEN) - 1) << USB_ACC_F1_HOV_POS) -#define USB_ACC_F1_HOV_UMSK (~(((1U << USB_ACC_F1_HOV_LEN) - 1) << USB_ACC_F1_HOV_POS)) -#define USB_ACC_F2_HOV USB_ACC_F2_HOV -#define USB_ACC_F2_HOV_POS (2U) -#define USB_ACC_F2_HOV_LEN (1U) -#define USB_ACC_F2_HOV_MSK (((1U << USB_ACC_F2_HOV_LEN) - 1) << USB_ACC_F2_HOV_POS) -#define USB_ACC_F2_HOV_UMSK (~(((1U << USB_ACC_F2_HOV_LEN) - 1) << USB_ACC_F2_HOV_POS)) -#define USB_ACC_F3_HOV USB_ACC_F3_HOV -#define USB_ACC_F3_HOV_POS (3U) -#define USB_ACC_F3_HOV_LEN (1U) -#define USB_ACC_F3_HOV_MSK (((1U << USB_ACC_F3_HOV_LEN) - 1) << USB_ACC_F3_HOV_POS) -#define USB_ACC_F3_HOV_UMSK (~(((1U << USB_ACC_F3_HOV_LEN) - 1) << USB_ACC_F3_HOV_POS)) -#define USB_ACC_CXF_HOV USB_ACC_CXF_HOV -#define USB_ACC_CXF_HOV_POS (4U) -#define USB_ACC_CXF_HOV_LEN (1U) -#define USB_ACC_CXF_HOV_MSK (((1U << USB_ACC_CXF_HOV_LEN) - 1) << USB_ACC_CXF_HOV_POS) -#define USB_ACC_CXF_HOV_UMSK (~(((1U << USB_ACC_CXF_HOV_LEN) - 1) << USB_ACC_CXF_HOV_POS)) -#define USB_ACC_F4_HOV USB_ACC_F4_HOV -#define USB_ACC_F4_HOV_POS (5U) -#define USB_ACC_F4_HOV_LEN (1U) -#define USB_ACC_F4_HOV_MSK (((1U << USB_ACC_F4_HOV_LEN) - 1) << USB_ACC_F4_HOV_POS) -#define USB_ACC_F4_HOV_UMSK (~(((1U << USB_ACC_F4_HOV_LEN) - 1) << USB_ACC_F4_HOV_POS)) -#define USB_ACC_F5_HOV USB_ACC_F5_HOV -#define USB_ACC_F5_HOV_POS (6U) -#define USB_ACC_F5_HOV_LEN (1U) -#define USB_ACC_F5_HOV_MSK (((1U << USB_ACC_F5_HOV_LEN) - 1) << USB_ACC_F5_HOV_POS) -#define USB_ACC_F5_HOV_UMSK (~(((1U << USB_ACC_F5_HOV_LEN) - 1) << USB_ACC_F5_HOV_POS)) -#define USB_ACC_F6_HOV USB_ACC_F6_HOV -#define USB_ACC_F6_HOV_POS (7U) -#define USB_ACC_F6_HOV_LEN (1U) -#define USB_ACC_F6_HOV_MSK (((1U << USB_ACC_F6_HOV_LEN) - 1) << USB_ACC_F6_HOV_POS) -#define USB_ACC_F6_HOV_UMSK (~(((1U << USB_ACC_F6_HOV_LEN) - 1) << USB_ACC_F6_HOV_POS)) -#define USB_ACC_F7_HOV USB_ACC_F7_HOV -#define USB_ACC_F7_HOV_POS (8U) -#define USB_ACC_F7_HOV_LEN (1U) -#define USB_ACC_F7_HOV_MSK (((1U << USB_ACC_F7_HOV_LEN) - 1) << USB_ACC_F7_HOV_POS) -#define USB_ACC_F7_HOV_UMSK (~(((1U << USB_ACC_F7_HOV_LEN) - 1) << USB_ACC_F7_HOV_POS)) -#define USB_ACC_F8_HOV USB_ACC_F8_HOV -#define USB_ACC_F8_HOV_POS (9U) -#define USB_ACC_F8_HOV_LEN (1U) -#define USB_ACC_F8_HOV_MSK (((1U << USB_ACC_F8_HOV_LEN) - 1) << USB_ACC_F8_HOV_POS) -#define USB_ACC_F8_HOV_UMSK (~(((1U << USB_ACC_F8_HOV_LEN) - 1) << USB_ACC_F8_HOV_POS)) -#define USB_ACC_F9_HOV USB_ACC_F9_HOV -#define USB_ACC_F9_HOV_POS (10U) -#define USB_ACC_F9_HOV_LEN (1U) -#define USB_ACC_F9_HOV_MSK (((1U << USB_ACC_F9_HOV_LEN) - 1) << USB_ACC_F9_HOV_POS) -#define USB_ACC_F9_HOV_UMSK (~(((1U << USB_ACC_F9_HOV_LEN) - 1) << USB_ACC_F9_HOV_POS)) -#define USB_ACC_F10_HOV USB_ACC_F10_HOV -#define USB_ACC_F10_HOV_POS (11U) -#define USB_ACC_F10_HOV_LEN (1U) -#define USB_ACC_F10_HOV_MSK (((1U << USB_ACC_F10_HOV_LEN) - 1) << USB_ACC_F10_HOV_POS) -#define USB_ACC_F10_HOV_UMSK (~(((1U << USB_ACC_F10_HOV_LEN) - 1) << USB_ACC_F10_HOV_POS)) -#define USB_ACC_F11_HOV USB_ACC_F11_HOV -#define USB_ACC_F11_HOV_POS (12U) -#define USB_ACC_F11_HOV_LEN (1U) -#define USB_ACC_F11_HOV_MSK (((1U << USB_ACC_F11_HOV_LEN) - 1) << USB_ACC_F11_HOV_POS) -#define USB_ACC_F11_HOV_UMSK (~(((1U << USB_ACC_F11_HOV_LEN) - 1) << USB_ACC_F11_HOV_POS)) -#define USB_ACC_F12_HOV USB_ACC_F12_HOV -#define USB_ACC_F12_HOV_POS (13U) -#define USB_ACC_F12_HOV_LEN (1U) -#define USB_ACC_F12_HOV_MSK (((1U << USB_ACC_F12_HOV_LEN) - 1) << USB_ACC_F12_HOV_POS) -#define USB_ACC_F12_HOV_UMSK (~(((1U << USB_ACC_F12_HOV_LEN) - 1) << USB_ACC_F12_HOV_POS)) -#define USB_ACC_F13_HOV USB_ACC_F13_HOV -#define USB_ACC_F13_HOV_POS (14U) -#define USB_ACC_F13_HOV_LEN (1U) -#define USB_ACC_F13_HOV_MSK (((1U << USB_ACC_F13_HOV_LEN) - 1) << USB_ACC_F13_HOV_POS) -#define USB_ACC_F13_HOV_UMSK (~(((1U << USB_ACC_F13_HOV_LEN) - 1) << USB_ACC_F13_HOV_POS)) -#define USB_ACC_F14_HOV USB_ACC_F14_HOV -#define USB_ACC_F14_HOV_POS (15U) -#define USB_ACC_F14_HOV_LEN (1U) -#define USB_ACC_F14_HOV_MSK (((1U << USB_ACC_F14_HOV_LEN) - 1) << USB_ACC_F14_HOV_POS) -#define USB_ACC_F14_HOV_UMSK (~(((1U << USB_ACC_F14_HOV_LEN) - 1) << USB_ACC_F14_HOV_POS)) -#define USB_ACC_F15_HOV USB_ACC_F15_HOV -#define USB_ACC_F15_HOV_POS (16U) -#define USB_ACC_F15_HOV_LEN (1U) -#define USB_ACC_F15_HOV_MSK (((1U << USB_ACC_F15_HOV_LEN) - 1) << USB_ACC_F15_HOV_POS) -#define USB_ACC_F15_HOV_UMSK (~(((1U << USB_ACC_F15_HOV_LEN) - 1) << USB_ACC_F15_HOV_POS)) - -/* 0x1C4 : DMA_CPS0 */ -#define USB_DMA_CPS0_OFFSET (0x1C4) -#define USB_AWCHACHE_HOV USB_AWCHACHE_HOV -#define USB_AWCHACHE_HOV_POS (0U) -#define USB_AWCHACHE_HOV_LEN (4U) -#define USB_AWCHACHE_HOV_MSK (((1U << USB_AWCHACHE_HOV_LEN) - 1) << USB_AWCHACHE_HOV_POS) -#define USB_AWCHACHE_HOV_UMSK (~(((1U << USB_AWCHACHE_HOV_LEN) - 1) << USB_AWCHACHE_HOV_POS)) -#define USB_AWPORT_HOV USB_AWPORT_HOV -#define USB_AWPORT_HOV_POS (4U) -#define USB_AWPORT_HOV_LEN (3U) -#define USB_AWPORT_HOV_MSK (((1U << USB_AWPORT_HOV_LEN) - 1) << USB_AWPORT_HOV_POS) -#define USB_AWPORT_HOV_UMSK (~(((1U << USB_AWPORT_HOV_LEN) - 1) << USB_AWPORT_HOV_POS)) -#define USB_AWLOCK_HOV USB_AWLOCK_HOV -#define USB_AWLOCK_HOV_POS (7U) -#define USB_AWLOCK_HOV_LEN (2U) -#define USB_AWLOCK_HOV_MSK (((1U << USB_AWLOCK_HOV_LEN) - 1) << USB_AWLOCK_HOV_POS) -#define USB_AWLOCK_HOV_UMSK (~(((1U << USB_AWLOCK_HOV_LEN) - 1) << USB_AWLOCK_HOV_POS)) -#define USB_ARCACHE_HOV USB_ARCACHE_HOV -#define USB_ARCACHE_HOV_POS (9U) -#define USB_ARCACHE_HOV_LEN (4U) -#define USB_ARCACHE_HOV_MSK (((1U << USB_ARCACHE_HOV_LEN) - 1) << USB_ARCACHE_HOV_POS) -#define USB_ARCACHE_HOV_UMSK (~(((1U << USB_ARCACHE_HOV_LEN) - 1) << USB_ARCACHE_HOV_POS)) -#define USB_ARPORT_HOV USB_ARPORT_HOV -#define USB_ARPORT_HOV_POS (13U) -#define USB_ARPORT_HOV_LEN (3U) -#define USB_ARPORT_HOV_MSK (((1U << USB_ARPORT_HOV_LEN) - 1) << USB_ARPORT_HOV_POS) -#define USB_ARPORT_HOV_UMSK (~(((1U << USB_ARPORT_HOV_LEN) - 1) << USB_ARPORT_HOV_POS)) -#define USB_ARLOCK_HOV USB_ARLOCK_HOV -#define USB_ARLOCK_HOV_POS (16U) -#define USB_ARLOCK_HOV_LEN (2U) -#define USB_ARLOCK_HOV_MSK (((1U << USB_ARLOCK_HOV_LEN) - 1) << USB_ARLOCK_HOV_POS) -#define USB_ARLOCK_HOV_UMSK (~(((1U << USB_ARLOCK_HOV_LEN) - 1) << USB_ARLOCK_HOV_POS)) -#define USB_BUF_LD_EN_HOV USB_BUF_LD_EN_HOV -#define USB_BUF_LD_EN_HOV_POS (18U) -#define USB_BUF_LD_EN_HOV_LEN (1U) -#define USB_BUF_LD_EN_HOV_MSK (((1U << USB_BUF_LD_EN_HOV_LEN) - 1) << USB_BUF_LD_EN_HOV_POS) -#define USB_BUF_LD_EN_HOV_UMSK (~(((1U << USB_BUF_LD_EN_HOV_LEN) - 1) << USB_BUF_LD_EN_HOV_POS)) -#define USB_DST_WD_HOV USB_DST_WD_HOV -#define USB_DST_WD_HOV_POS (19U) -#define USB_DST_WD_HOV_LEN (1U) -#define USB_DST_WD_HOV_MSK (((1U << USB_DST_WD_HOV_LEN) - 1) << USB_DST_WD_HOV_POS) -#define USB_DST_WD_HOV_UMSK (~(((1U << USB_DST_WD_HOV_LEN) - 1) << USB_DST_WD_HOV_POS)) - -/* 0x1C8 : DMA_CPS1 */ -#define USB_DMA_CPS1_OFFSET (0x1C8) -#define USB_DMA_START_HOV USB_DMA_START_HOV -#define USB_DMA_START_HOV_POS (0U) -#define USB_DMA_START_HOV_LEN (1U) -#define USB_DMA_START_HOV_MSK (((1U << USB_DMA_START_HOV_LEN) - 1) << USB_DMA_START_HOV_POS) -#define USB_DMA_START_HOV_UMSK (~(((1U << USB_DMA_START_HOV_LEN) - 1) << USB_DMA_START_HOV_POS)) -#define USB_DMA_TYPE_HOV USB_DMA_TYPE_HOV -#define USB_DMA_TYPE_HOV_POS (1U) -#define USB_DMA_TYPE_HOV_LEN (1U) -#define USB_DMA_TYPE_HOV_MSK (((1U << USB_DMA_TYPE_HOV_LEN) - 1) << USB_DMA_TYPE_HOV_POS) -#define USB_DMA_TYPE_HOV_UMSK (~(((1U << USB_DMA_TYPE_HOV_LEN) - 1) << USB_DMA_TYPE_HOV_POS)) -#define USB_DMA_IO_HOV USB_DMA_IO_HOV -#define USB_DMA_IO_HOV_POS (2U) -#define USB_DMA_IO_HOV_LEN (1U) -#define USB_DMA_IO_HOV_MSK (((1U << USB_DMA_IO_HOV_LEN) - 1) << USB_DMA_IO_HOV_POS) -#define USB_DMA_IO_HOV_UMSK (~(((1U << USB_DMA_IO_HOV_LEN) - 1) << USB_DMA_IO_HOV_POS)) -#define USB_DMA_ABORT_HOV USB_DMA_ABORT_HOV -#define USB_DMA_ABORT_HOV_POS (3U) -#define USB_DMA_ABORT_HOV_LEN (1U) -#define USB_DMA_ABORT_HOV_MSK (((1U << USB_DMA_ABORT_HOV_LEN) - 1) << USB_DMA_ABORT_HOV_POS) -#define USB_DMA_ABORT_HOV_UMSK (~(((1U << USB_DMA_ABORT_HOV_LEN) - 1) << USB_DMA_ABORT_HOV_POS)) -#define USB_CLRFIFO_DMAABORT_HOV USB_CLRFIFO_DMAABORT_HOV -#define USB_CLRFIFO_DMAABORT_HOV_POS (4U) -#define USB_CLRFIFO_DMAABORT_HOV_LEN (1U) -#define USB_CLRFIFO_DMAABORT_HOV_MSK (((1U << USB_CLRFIFO_DMAABORT_HOV_LEN) - 1) << USB_CLRFIFO_DMAABORT_HOV_POS) -#define USB_CLRFIFO_DMAABORT_HOV_UMSK (~(((1U << USB_CLRFIFO_DMAABORT_HOV_LEN) - 1) << USB_CLRFIFO_DMAABORT_HOV_POS)) -#define USB_DMA_LEN_HOV USB_DMA_LEN_HOV -#define USB_DMA_LEN_HOV_POS (8U) -#define USB_DMA_LEN_HOV_LEN (17U) -#define USB_DMA_LEN_HOV_MSK (((1U << USB_DMA_LEN_HOV_LEN) - 1) << USB_DMA_LEN_HOV_POS) -#define USB_DMA_LEN_HOV_UMSK (~(((1U << USB_DMA_LEN_HOV_LEN) - 1) << USB_DMA_LEN_HOV_POS)) -#define USB_R_HPORT_HOV USB_R_HPORT_HOV -#define USB_R_HPORT_HOV_POS (25U) -#define USB_R_HPORT_HOV_LEN (4U) -#define USB_R_HPORT_HOV_MSK (((1U << USB_R_HPORT_HOV_LEN) - 1) << USB_R_HPORT_HOV_POS) -#define USB_R_HPORT_HOV_UMSK (~(((1U << USB_R_HPORT_HOV_LEN) - 1) << USB_R_HPORT_HOV_POS)) -#define USB_UNDEF_LEN_BURST_HOV USB_UNDEF_LEN_BURST_HOV -#define USB_UNDEF_LEN_BURST_HOV_POS (29U) -#define USB_UNDEF_LEN_BURST_HOV_LEN (1U) -#define USB_UNDEF_LEN_BURST_HOV_MSK (((1U << USB_UNDEF_LEN_BURST_HOV_LEN) - 1) << USB_UNDEF_LEN_BURST_HOV_POS) -#define USB_UNDEF_LEN_BURST_HOV_UMSK (~(((1U << USB_UNDEF_LEN_BURST_HOV_LEN) - 1) << USB_UNDEF_LEN_BURST_HOV_POS)) -#define USB_L1_WAKEUP USB_L1_WAKEUP -#define USB_L1_WAKEUP_POS (30U) -#define USB_L1_WAKEUP_LEN (1U) -#define USB_L1_WAKEUP_MSK (((1U << USB_L1_WAKEUP_LEN) - 1) << USB_L1_WAKEUP_POS) -#define USB_L1_WAKEUP_UMSK (~(((1U << USB_L1_WAKEUP_LEN) - 1) << USB_L1_WAKEUP_POS)) -#define USB_DEVPHY_SUSPEND_HOV USB_DEVPHY_SUSPEND_HOV -#define USB_DEVPHY_SUSPEND_HOV_POS (31U) -#define USB_DEVPHY_SUSPEND_HOV_LEN (1U) -#define USB_DEVPHY_SUSPEND_HOV_MSK (((1U << USB_DEVPHY_SUSPEND_HOV_LEN) - 1) << USB_DEVPHY_SUSPEND_HOV_POS) -#define USB_DEVPHY_SUSPEND_HOV_UMSK (~(((1U << USB_DEVPHY_SUSPEND_HOV_LEN) - 1) << USB_DEVPHY_SUSPEND_HOV_POS)) - -/* 0x1CC : DMA_CPS2 */ -#define USB_DMA_CPS2_OFFSET (0x1CC) -#define USB_DMA_MADDR_HOV USB_DMA_MADDR_HOV -#define USB_DMA_MADDR_HOV_POS (0U) -#define USB_DMA_MADDR_HOV_LEN (32U) -#define USB_DMA_MADDR_HOV_MSK (((1U << USB_DMA_MADDR_HOV_LEN) - 1) << USB_DMA_MADDR_HOV_POS) -#define USB_DMA_MADDR_HOV_UMSK (~(((1U << USB_DMA_MADDR_HOV_LEN) - 1) << USB_DMA_MADDR_HOV_POS)) - -/* 0x1D0 : DMA_CPS3 */ -#define USB_DMA_CPS3_OFFSET (0x1D0) -#define USB_SETUP_CMD_RPORT USB_SETUP_CMD_RPORT -#define USB_SETUP_CMD_RPORT_POS (0U) -#define USB_SETUP_CMD_RPORT_LEN (32U) -#define USB_SETUP_CMD_RPORT_MSK (((1U << USB_SETUP_CMD_RPORT_LEN) - 1) << USB_SETUP_CMD_RPORT_POS) -#define USB_SETUP_CMD_RPORT_UMSK (~(((1U << USB_SETUP_CMD_RPORT_LEN) - 1) << USB_SETUP_CMD_RPORT_POS)) - -/* 0x1D4 : DMA_CPS4 */ -#define USB_DMA_CPS4_OFFSET (0x1D4) - -/* 0x1D8 : DEV_FMAP2 */ -#define USB_DEV_FMAP2_OFFSET (0x1D8) -#define USB_EPNO_FIFO4 USB_EPNO_FIFO4 -#define USB_EPNO_FIFO4_POS (0U) -#define USB_EPNO_FIFO4_LEN (4U) -#define USB_EPNO_FIFO4_MSK (((1U << USB_EPNO_FIFO4_LEN) - 1) << USB_EPNO_FIFO4_POS) -#define USB_EPNO_FIFO4_UMSK (~(((1U << USB_EPNO_FIFO4_LEN) - 1) << USB_EPNO_FIFO4_POS)) -#define USB_DIR_FIFO4 USB_DIR_FIFO4 -#define USB_DIR_FIFO4_POS (4U) -#define USB_DIR_FIFO4_LEN (2U) -#define USB_DIR_FIFO4_MSK (((1U << USB_DIR_FIFO4_LEN) - 1) << USB_DIR_FIFO4_POS) -#define USB_DIR_FIFO4_UMSK (~(((1U << USB_DIR_FIFO4_LEN) - 1) << USB_DIR_FIFO4_POS)) -#define USB_EPNO_FIFO5 USB_EPNO_FIFO5 -#define USB_EPNO_FIFO5_POS (8U) -#define USB_EPNO_FIFO5_LEN (4U) -#define USB_EPNO_FIFO5_MSK (((1U << USB_EPNO_FIFO5_LEN) - 1) << USB_EPNO_FIFO5_POS) -#define USB_EPNO_FIFO5_UMSK (~(((1U << USB_EPNO_FIFO5_LEN) - 1) << USB_EPNO_FIFO5_POS)) -#define USB_DIR_FIFO5 USB_DIR_FIFO5 -#define USB_DIR_FIFO5_POS (12U) -#define USB_DIR_FIFO5_LEN (2U) -#define USB_DIR_FIFO5_MSK (((1U << USB_DIR_FIFO5_LEN) - 1) << USB_DIR_FIFO5_POS) -#define USB_DIR_FIFO5_UMSK (~(((1U << USB_DIR_FIFO5_LEN) - 1) << USB_DIR_FIFO5_POS)) -#define USB_EPNO_FIFO6 USB_EPNO_FIFO6 -#define USB_EPNO_FIFO6_POS (16U) -#define USB_EPNO_FIFO6_LEN (4U) -#define USB_EPNO_FIFO6_MSK (((1U << USB_EPNO_FIFO6_LEN) - 1) << USB_EPNO_FIFO6_POS) -#define USB_EPNO_FIFO6_UMSK (~(((1U << USB_EPNO_FIFO6_LEN) - 1) << USB_EPNO_FIFO6_POS)) -#define USB_DIR_FIFO6 USB_DIR_FIFO6 -#define USB_DIR_FIFO6_POS (20U) -#define USB_DIR_FIFO6_LEN (2U) -#define USB_DIR_FIFO6_MSK (((1U << USB_DIR_FIFO6_LEN) - 1) << USB_DIR_FIFO6_POS) -#define USB_DIR_FIFO6_UMSK (~(((1U << USB_DIR_FIFO6_LEN) - 1) << USB_DIR_FIFO6_POS)) -#define USB_EPNO_FIFO7 USB_EPNO_FIFO7 -#define USB_EPNO_FIFO7_POS (24U) -#define USB_EPNO_FIFO7_LEN (4U) -#define USB_EPNO_FIFO7_MSK (((1U << USB_EPNO_FIFO7_LEN) - 1) << USB_EPNO_FIFO7_POS) -#define USB_EPNO_FIFO7_UMSK (~(((1U << USB_EPNO_FIFO7_LEN) - 1) << USB_EPNO_FIFO7_POS)) -#define USB_DIR_FIFO7 USB_DIR_FIFO7 -#define USB_DIR_FIFO7_POS (28U) -#define USB_DIR_FIFO7_LEN (2U) -#define USB_DIR_FIFO7_MSK (((1U << USB_DIR_FIFO7_LEN) - 1) << USB_DIR_FIFO7_POS) -#define USB_DIR_FIFO7_UMSK (~(((1U << USB_DIR_FIFO7_LEN) - 1) << USB_DIR_FIFO7_POS)) - -/* 0x1DC : DEV_FCFG2 */ -#define USB_DEV_FCFG2_OFFSET (0x1DC) -#define USB_BLK_TYP_F4 USB_BLK_TYP_F4 -#define USB_BLK_TYP_F4_POS (0U) -#define USB_BLK_TYP_F4_LEN (2U) -#define USB_BLK_TYP_F4_MSK (((1U << USB_BLK_TYP_F4_LEN) - 1) << USB_BLK_TYP_F4_POS) -#define USB_BLK_TYP_F4_UMSK (~(((1U << USB_BLK_TYP_F4_LEN) - 1) << USB_BLK_TYP_F4_POS)) -#define USB_BLKNO_F4 USB_BLKNO_F4 -#define USB_BLKNO_F4_POS (2U) -#define USB_BLKNO_F4_LEN (2U) -#define USB_BLKNO_F4_MSK (((1U << USB_BLKNO_F4_LEN) - 1) << USB_BLKNO_F4_POS) -#define USB_BLKNO_F4_UMSK (~(((1U << USB_BLKNO_F4_LEN) - 1) << USB_BLKNO_F4_POS)) -#define USB_BLKSZ_F4 USB_BLKSZ_F4 -#define USB_BLKSZ_F4_POS (4U) -#define USB_BLKSZ_F4_LEN (1U) -#define USB_BLKSZ_F4_MSK (((1U << USB_BLKSZ_F4_LEN) - 1) << USB_BLKSZ_F4_POS) -#define USB_BLKSZ_F4_UMSK (~(((1U << USB_BLKSZ_F4_LEN) - 1) << USB_BLKSZ_F4_POS)) -#define USB_EN_F4 USB_EN_F4 -#define USB_EN_F4_POS (5U) -#define USB_EN_F4_LEN (1U) -#define USB_EN_F4_MSK (((1U << USB_EN_F4_LEN) - 1) << USB_EN_F4_POS) -#define USB_EN_F4_UMSK (~(((1U << USB_EN_F4_LEN) - 1) << USB_EN_F4_POS)) -#define USB_BLK_TYP_F5 USB_BLK_TYP_F5 -#define USB_BLK_TYP_F5_POS (8U) -#define USB_BLK_TYP_F5_LEN (2U) -#define USB_BLK_TYP_F5_MSK (((1U << USB_BLK_TYP_F5_LEN) - 1) << USB_BLK_TYP_F5_POS) -#define USB_BLK_TYP_F5_UMSK (~(((1U << USB_BLK_TYP_F5_LEN) - 1) << USB_BLK_TYP_F5_POS)) -#define USB_BLKNO_F5 USB_BLKNO_F5 -#define USB_BLKNO_F5_POS (10U) -#define USB_BLKNO_F5_LEN (2U) -#define USB_BLKNO_F5_MSK (((1U << USB_BLKNO_F5_LEN) - 1) << USB_BLKNO_F5_POS) -#define USB_BLKNO_F5_UMSK (~(((1U << USB_BLKNO_F5_LEN) - 1) << USB_BLKNO_F5_POS)) -#define USB_BLKSZ_F5 USB_BLKSZ_F5 -#define USB_BLKSZ_F5_POS (12U) -#define USB_BLKSZ_F5_LEN (1U) -#define USB_BLKSZ_F5_MSK (((1U << USB_BLKSZ_F5_LEN) - 1) << USB_BLKSZ_F5_POS) -#define USB_BLKSZ_F5_UMSK (~(((1U << USB_BLKSZ_F5_LEN) - 1) << USB_BLKSZ_F5_POS)) -#define USB_EN_F5 USB_EN_F5 -#define USB_EN_F5_POS (13U) -#define USB_EN_F5_LEN (1U) -#define USB_EN_F5_MSK (((1U << USB_EN_F5_LEN) - 1) << USB_EN_F5_POS) -#define USB_EN_F5_UMSK (~(((1U << USB_EN_F5_LEN) - 1) << USB_EN_F5_POS)) -#define USB_BLK_TYP_F6 USB_BLK_TYP_F6 -#define USB_BLK_TYP_F6_POS (16U) -#define USB_BLK_TYP_F6_LEN (2U) -#define USB_BLK_TYP_F6_MSK (((1U << USB_BLK_TYP_F6_LEN) - 1) << USB_BLK_TYP_F6_POS) -#define USB_BLK_TYP_F6_UMSK (~(((1U << USB_BLK_TYP_F6_LEN) - 1) << USB_BLK_TYP_F6_POS)) -#define USB_BLKNO_F6 USB_BLKNO_F6 -#define USB_BLKNO_F6_POS (18U) -#define USB_BLKNO_F6_LEN (2U) -#define USB_BLKNO_F6_MSK (((1U << USB_BLKNO_F6_LEN) - 1) << USB_BLKNO_F6_POS) -#define USB_BLKNO_F6_UMSK (~(((1U << USB_BLKNO_F6_LEN) - 1) << USB_BLKNO_F6_POS)) -#define USB_BLKSZ_F6 USB_BLKSZ_F6 -#define USB_BLKSZ_F6_POS (20U) -#define USB_BLKSZ_F6_LEN (1U) -#define USB_BLKSZ_F6_MSK (((1U << USB_BLKSZ_F6_LEN) - 1) << USB_BLKSZ_F6_POS) -#define USB_BLKSZ_F6_UMSK (~(((1U << USB_BLKSZ_F6_LEN) - 1) << USB_BLKSZ_F6_POS)) -#define USB_EN_F6 USB_EN_F6 -#define USB_EN_F6_POS (21U) -#define USB_EN_F6_LEN (1U) -#define USB_EN_F6_MSK (((1U << USB_EN_F6_LEN) - 1) << USB_EN_F6_POS) -#define USB_EN_F6_UMSK (~(((1U << USB_EN_F6_LEN) - 1) << USB_EN_F6_POS)) -#define USB_BLK_TYP_F7 USB_BLK_TYP_F7 -#define USB_BLK_TYP_F7_POS (24U) -#define USB_BLK_TYP_F7_LEN (2U) -#define USB_BLK_TYP_F7_MSK (((1U << USB_BLK_TYP_F7_LEN) - 1) << USB_BLK_TYP_F7_POS) -#define USB_BLK_TYP_F7_UMSK (~(((1U << USB_BLK_TYP_F7_LEN) - 1) << USB_BLK_TYP_F7_POS)) -#define USB_BLKNO_F7 USB_BLKNO_F7 -#define USB_BLKNO_F7_POS (26U) -#define USB_BLKNO_F7_LEN (2U) -#define USB_BLKNO_F7_MSK (((1U << USB_BLKNO_F7_LEN) - 1) << USB_BLKNO_F7_POS) -#define USB_BLKNO_F7_UMSK (~(((1U << USB_BLKNO_F7_LEN) - 1) << USB_BLKNO_F7_POS)) -#define USB_BLKSZ_F7 USB_BLKSZ_F7 -#define USB_BLKSZ_F7_POS (28U) -#define USB_BLKSZ_F7_LEN (1U) -#define USB_BLKSZ_F7_MSK (((1U << USB_BLKSZ_F7_LEN) - 1) << USB_BLKSZ_F7_POS) -#define USB_BLKSZ_F7_UMSK (~(((1U << USB_BLKSZ_F7_LEN) - 1) << USB_BLKSZ_F7_POS)) -#define USB_EN_F7 USB_EN_F7 -#define USB_EN_F7_POS (29U) -#define USB_EN_F7_LEN (1U) -#define USB_EN_F7_MSK (((1U << USB_EN_F7_LEN) - 1) << USB_EN_F7_POS) -#define USB_EN_F7_UMSK (~(((1U << USB_EN_F7_LEN) - 1) << USB_EN_F7_POS)) - -/* 0x1E0 : DEV_FMAP3 */ -#define USB_DEV_FMAP3_OFFSET (0x1E0) -#define USB_EPNO_FIFO8 USB_EPNO_FIFO8 -#define USB_EPNO_FIFO8_POS (0U) -#define USB_EPNO_FIFO8_LEN (4U) -#define USB_EPNO_FIFO8_MSK (((1U << USB_EPNO_FIFO8_LEN) - 1) << USB_EPNO_FIFO8_POS) -#define USB_EPNO_FIFO8_UMSK (~(((1U << USB_EPNO_FIFO8_LEN) - 1) << USB_EPNO_FIFO8_POS)) -#define USB_DIR_FIFO8 USB_DIR_FIFO8 -#define USB_DIR_FIFO8_POS (4U) -#define USB_DIR_FIFO8_LEN (2U) -#define USB_DIR_FIFO8_MSK (((1U << USB_DIR_FIFO8_LEN) - 1) << USB_DIR_FIFO8_POS) -#define USB_DIR_FIFO8_UMSK (~(((1U << USB_DIR_FIFO8_LEN) - 1) << USB_DIR_FIFO8_POS)) -#define USB_EPNO_FIFO9 USB_EPNO_FIFO9 -#define USB_EPNO_FIFO9_POS (8U) -#define USB_EPNO_FIFO9_LEN (4U) -#define USB_EPNO_FIFO9_MSK (((1U << USB_EPNO_FIFO9_LEN) - 1) << USB_EPNO_FIFO9_POS) -#define USB_EPNO_FIFO9_UMSK (~(((1U << USB_EPNO_FIFO9_LEN) - 1) << USB_EPNO_FIFO9_POS)) -#define USB_DIR_FIFO9 USB_DIR_FIFO9 -#define USB_DIR_FIFO9_POS (12U) -#define USB_DIR_FIFO9_LEN (2U) -#define USB_DIR_FIFO9_MSK (((1U << USB_DIR_FIFO9_LEN) - 1) << USB_DIR_FIFO9_POS) -#define USB_DIR_FIFO9_UMSK (~(((1U << USB_DIR_FIFO9_LEN) - 1) << USB_DIR_FIFO9_POS)) -#define USB_EPNO_FIFO10 USB_EPNO_FIFO10 -#define USB_EPNO_FIFO10_POS (16U) -#define USB_EPNO_FIFO10_LEN (4U) -#define USB_EPNO_FIFO10_MSK (((1U << USB_EPNO_FIFO10_LEN) - 1) << USB_EPNO_FIFO10_POS) -#define USB_EPNO_FIFO10_UMSK (~(((1U << USB_EPNO_FIFO10_LEN) - 1) << USB_EPNO_FIFO10_POS)) -#define USB_DIR_FIFO10 USB_DIR_FIFO10 -#define USB_DIR_FIFO10_POS (20U) -#define USB_DIR_FIFO10_LEN (2U) -#define USB_DIR_FIFO10_MSK (((1U << USB_DIR_FIFO10_LEN) - 1) << USB_DIR_FIFO10_POS) -#define USB_DIR_FIFO10_UMSK (~(((1U << USB_DIR_FIFO10_LEN) - 1) << USB_DIR_FIFO10_POS)) -#define USB_EPNO_FIFO11 USB_EPNO_FIFO11 -#define USB_EPNO_FIFO11_POS (24U) -#define USB_EPNO_FIFO11_LEN (4U) -#define USB_EPNO_FIFO11_MSK (((1U << USB_EPNO_FIFO11_LEN) - 1) << USB_EPNO_FIFO11_POS) -#define USB_EPNO_FIFO11_UMSK (~(((1U << USB_EPNO_FIFO11_LEN) - 1) << USB_EPNO_FIFO11_POS)) -#define USB_DIR_FIFO11 USB_DIR_FIFO11 -#define USB_DIR_FIFO11_POS (28U) -#define USB_DIR_FIFO11_LEN (2U) -#define USB_DIR_FIFO11_MSK (((1U << USB_DIR_FIFO11_LEN) - 1) << USB_DIR_FIFO11_POS) -#define USB_DIR_FIFO11_UMSK (~(((1U << USB_DIR_FIFO11_LEN) - 1) << USB_DIR_FIFO11_POS)) - -/* 0x1E4 : DEV_FCFG3 */ -#define USB_DEV_FCFG3_OFFSET (0x1E4) -#define USB_BLK_TYP_F8 USB_BLK_TYP_F8 -#define USB_BLK_TYP_F8_POS (0U) -#define USB_BLK_TYP_F8_LEN (2U) -#define USB_BLK_TYP_F8_MSK (((1U << USB_BLK_TYP_F8_LEN) - 1) << USB_BLK_TYP_F8_POS) -#define USB_BLK_TYP_F8_UMSK (~(((1U << USB_BLK_TYP_F8_LEN) - 1) << USB_BLK_TYP_F8_POS)) -#define USB_BLKNO_F8 USB_BLKNO_F8 -#define USB_BLKNO_F8_POS (2U) -#define USB_BLKNO_F8_LEN (2U) -#define USB_BLKNO_F8_MSK (((1U << USB_BLKNO_F8_LEN) - 1) << USB_BLKNO_F8_POS) -#define USB_BLKNO_F8_UMSK (~(((1U << USB_BLKNO_F8_LEN) - 1) << USB_BLKNO_F8_POS)) -#define USB_BLKSZ_F8 USB_BLKSZ_F8 -#define USB_BLKSZ_F8_POS (4U) -#define USB_BLKSZ_F8_LEN (1U) -#define USB_BLKSZ_F8_MSK (((1U << USB_BLKSZ_F8_LEN) - 1) << USB_BLKSZ_F8_POS) -#define USB_BLKSZ_F8_UMSK (~(((1U << USB_BLKSZ_F8_LEN) - 1) << USB_BLKSZ_F8_POS)) -#define USB_EN_F8 USB_EN_F8 -#define USB_EN_F8_POS (5U) -#define USB_EN_F8_LEN (1U) -#define USB_EN_F8_MSK (((1U << USB_EN_F8_LEN) - 1) << USB_EN_F8_POS) -#define USB_EN_F8_UMSK (~(((1U << USB_EN_F8_LEN) - 1) << USB_EN_F8_POS)) -#define USB_BLK_TYP_F9 USB_BLK_TYP_F9 -#define USB_BLK_TYP_F9_POS (8U) -#define USB_BLK_TYP_F9_LEN (2U) -#define USB_BLK_TYP_F9_MSK (((1U << USB_BLK_TYP_F9_LEN) - 1) << USB_BLK_TYP_F9_POS) -#define USB_BLK_TYP_F9_UMSK (~(((1U << USB_BLK_TYP_F9_LEN) - 1) << USB_BLK_TYP_F9_POS)) -#define USB_BLKNO_F9 USB_BLKNO_F9 -#define USB_BLKNO_F9_POS (10U) -#define USB_BLKNO_F9_LEN (2U) -#define USB_BLKNO_F9_MSK (((1U << USB_BLKNO_F9_LEN) - 1) << USB_BLKNO_F9_POS) -#define USB_BLKNO_F9_UMSK (~(((1U << USB_BLKNO_F9_LEN) - 1) << USB_BLKNO_F9_POS)) -#define USB_BLKSZ_F9 USB_BLKSZ_F9 -#define USB_BLKSZ_F9_POS (12U) -#define USB_BLKSZ_F9_LEN (1U) -#define USB_BLKSZ_F9_MSK (((1U << USB_BLKSZ_F9_LEN) - 1) << USB_BLKSZ_F9_POS) -#define USB_BLKSZ_F9_UMSK (~(((1U << USB_BLKSZ_F9_LEN) - 1) << USB_BLKSZ_F9_POS)) -#define USB_EN_F9 USB_EN_F9 -#define USB_EN_F9_POS (13U) -#define USB_EN_F9_LEN (1U) -#define USB_EN_F9_MSK (((1U << USB_EN_F9_LEN) - 1) << USB_EN_F9_POS) -#define USB_EN_F9_UMSK (~(((1U << USB_EN_F9_LEN) - 1) << USB_EN_F9_POS)) -#define USB_BLK_TYP_F10 USB_BLK_TYP_F10 -#define USB_BLK_TYP_F10_POS (16U) -#define USB_BLK_TYP_F10_LEN (2U) -#define USB_BLK_TYP_F10_MSK (((1U << USB_BLK_TYP_F10_LEN) - 1) << USB_BLK_TYP_F10_POS) -#define USB_BLK_TYP_F10_UMSK (~(((1U << USB_BLK_TYP_F10_LEN) - 1) << USB_BLK_TYP_F10_POS)) -#define USB_BLKNO_F10 USB_BLKNO_F10 -#define USB_BLKNO_F10_POS (18U) -#define USB_BLKNO_F10_LEN (2U) -#define USB_BLKNO_F10_MSK (((1U << USB_BLKNO_F10_LEN) - 1) << USB_BLKNO_F10_POS) -#define USB_BLKNO_F10_UMSK (~(((1U << USB_BLKNO_F10_LEN) - 1) << USB_BLKNO_F10_POS)) -#define USB_BLKSZ_F10 USB_BLKSZ_F10 -#define USB_BLKSZ_F10_POS (20U) -#define USB_BLKSZ_F10_LEN (1U) -#define USB_BLKSZ_F10_MSK (((1U << USB_BLKSZ_F10_LEN) - 1) << USB_BLKSZ_F10_POS) -#define USB_BLKSZ_F10_UMSK (~(((1U << USB_BLKSZ_F10_LEN) - 1) << USB_BLKSZ_F10_POS)) -#define USB_EN_F10 USB_EN_F10 -#define USB_EN_F10_POS (21U) -#define USB_EN_F10_LEN (1U) -#define USB_EN_F10_MSK (((1U << USB_EN_F10_LEN) - 1) << USB_EN_F10_POS) -#define USB_EN_F10_UMSK (~(((1U << USB_EN_F10_LEN) - 1) << USB_EN_F10_POS)) -#define USB_BLK_TYP_F11 USB_BLK_TYP_F11 -#define USB_BLK_TYP_F11_POS (24U) -#define USB_BLK_TYP_F11_LEN (2U) -#define USB_BLK_TYP_F11_MSK (((1U << USB_BLK_TYP_F11_LEN) - 1) << USB_BLK_TYP_F11_POS) -#define USB_BLK_TYP_F11_UMSK (~(((1U << USB_BLK_TYP_F11_LEN) - 1) << USB_BLK_TYP_F11_POS)) -#define USB_BLKNO_F11 USB_BLKNO_F11 -#define USB_BLKNO_F11_POS (26U) -#define USB_BLKNO_F11_LEN (2U) -#define USB_BLKNO_F11_MSK (((1U << USB_BLKNO_F11_LEN) - 1) << USB_BLKNO_F11_POS) -#define USB_BLKNO_F11_UMSK (~(((1U << USB_BLKNO_F11_LEN) - 1) << USB_BLKNO_F11_POS)) -#define USB_BLKSZ_F11 USB_BLKSZ_F11 -#define USB_BLKSZ_F11_POS (28U) -#define USB_BLKSZ_F11_LEN (1U) -#define USB_BLKSZ_F11_MSK (((1U << USB_BLKSZ_F11_LEN) - 1) << USB_BLKSZ_F11_POS) -#define USB_BLKSZ_F11_UMSK (~(((1U << USB_BLKSZ_F11_LEN) - 1) << USB_BLKSZ_F11_POS)) -#define USB_EN_F11 USB_EN_F11 -#define USB_EN_F11_POS (29U) -#define USB_EN_F11_LEN (1U) -#define USB_EN_F11_MSK (((1U << USB_EN_F11_LEN) - 1) << USB_EN_F11_POS) -#define USB_EN_F11_UMSK (~(((1U << USB_EN_F11_LEN) - 1) << USB_EN_F11_POS)) - -/* 0x1E8 : DEV_FMAP4 */ -#define USB_DEV_FMAP4_OFFSET (0x1E8) -#define USB_EPNO_FIFO12 USB_EPNO_FIFO12 -#define USB_EPNO_FIFO12_POS (0U) -#define USB_EPNO_FIFO12_LEN (4U) -#define USB_EPNO_FIFO12_MSK (((1U << USB_EPNO_FIFO12_LEN) - 1) << USB_EPNO_FIFO12_POS) -#define USB_EPNO_FIFO12_UMSK (~(((1U << USB_EPNO_FIFO12_LEN) - 1) << USB_EPNO_FIFO12_POS)) -#define USB_DIR_FIFO12 USB_DIR_FIFO12 -#define USB_DIR_FIFO12_POS (4U) -#define USB_DIR_FIFO12_LEN (2U) -#define USB_DIR_FIFO12_MSK (((1U << USB_DIR_FIFO12_LEN) - 1) << USB_DIR_FIFO12_POS) -#define USB_DIR_FIFO12_UMSK (~(((1U << USB_DIR_FIFO12_LEN) - 1) << USB_DIR_FIFO12_POS)) -#define USB_EPNO_FIFO13 USB_EPNO_FIFO13 -#define USB_EPNO_FIFO13_POS (8U) -#define USB_EPNO_FIFO13_LEN (4U) -#define USB_EPNO_FIFO13_MSK (((1U << USB_EPNO_FIFO13_LEN) - 1) << USB_EPNO_FIFO13_POS) -#define USB_EPNO_FIFO13_UMSK (~(((1U << USB_EPNO_FIFO13_LEN) - 1) << USB_EPNO_FIFO13_POS)) -#define USB_DIR_FIFO13 USB_DIR_FIFO13 -#define USB_DIR_FIFO13_POS (12U) -#define USB_DIR_FIFO13_LEN (2U) -#define USB_DIR_FIFO13_MSK (((1U << USB_DIR_FIFO13_LEN) - 1) << USB_DIR_FIFO13_POS) -#define USB_DIR_FIFO13_UMSK (~(((1U << USB_DIR_FIFO13_LEN) - 1) << USB_DIR_FIFO13_POS)) -#define USB_EPNO_FIFO14 USB_EPNO_FIFO14 -#define USB_EPNO_FIFO14_POS (16U) -#define USB_EPNO_FIFO14_LEN (4U) -#define USB_EPNO_FIFO14_MSK (((1U << USB_EPNO_FIFO14_LEN) - 1) << USB_EPNO_FIFO14_POS) -#define USB_EPNO_FIFO14_UMSK (~(((1U << USB_EPNO_FIFO14_LEN) - 1) << USB_EPNO_FIFO14_POS)) -#define USB_DIR_FIFO14 USB_DIR_FIFO14 -#define USB_DIR_FIFO14_POS (20U) -#define USB_DIR_FIFO14_LEN (2U) -#define USB_DIR_FIFO14_MSK (((1U << USB_DIR_FIFO14_LEN) - 1) << USB_DIR_FIFO14_POS) -#define USB_DIR_FIFO14_UMSK (~(((1U << USB_DIR_FIFO14_LEN) - 1) << USB_DIR_FIFO14_POS)) -#define USB_EPNO_FIFO15 USB_EPNO_FIFO15 -#define USB_EPNO_FIFO15_POS (24U) -#define USB_EPNO_FIFO15_LEN (4U) -#define USB_EPNO_FIFO15_MSK (((1U << USB_EPNO_FIFO15_LEN) - 1) << USB_EPNO_FIFO15_POS) -#define USB_EPNO_FIFO15_UMSK (~(((1U << USB_EPNO_FIFO15_LEN) - 1) << USB_EPNO_FIFO15_POS)) -#define USB_DIR_FIFO15 USB_DIR_FIFO15 -#define USB_DIR_FIFO15_POS (28U) -#define USB_DIR_FIFO15_LEN (2U) -#define USB_DIR_FIFO15_MSK (((1U << USB_DIR_FIFO15_LEN) - 1) << USB_DIR_FIFO15_POS) -#define USB_DIR_FIFO15_UMSK (~(((1U << USB_DIR_FIFO15_LEN) - 1) << USB_DIR_FIFO15_POS)) - -/* 0x1EC : DEV_FCFG4 */ -#define USB_DEV_FCFG4_OFFSET (0x1EC) -#define USB_BLK_TYP_F12 USB_BLK_TYP_F12 -#define USB_BLK_TYP_F12_POS (0U) -#define USB_BLK_TYP_F12_LEN (2U) -#define USB_BLK_TYP_F12_MSK (((1U << USB_BLK_TYP_F12_LEN) - 1) << USB_BLK_TYP_F12_POS) -#define USB_BLK_TYP_F12_UMSK (~(((1U << USB_BLK_TYP_F12_LEN) - 1) << USB_BLK_TYP_F12_POS)) -#define USB_BLKNO_F12 USB_BLKNO_F12 -#define USB_BLKNO_F12_POS (2U) -#define USB_BLKNO_F12_LEN (2U) -#define USB_BLKNO_F12_MSK (((1U << USB_BLKNO_F12_LEN) - 1) << USB_BLKNO_F12_POS) -#define USB_BLKNO_F12_UMSK (~(((1U << USB_BLKNO_F12_LEN) - 1) << USB_BLKNO_F12_POS)) -#define USB_BLKSZ_F12 USB_BLKSZ_F12 -#define USB_BLKSZ_F12_POS (4U) -#define USB_BLKSZ_F12_LEN (1U) -#define USB_BLKSZ_F12_MSK (((1U << USB_BLKSZ_F12_LEN) - 1) << USB_BLKSZ_F12_POS) -#define USB_BLKSZ_F12_UMSK (~(((1U << USB_BLKSZ_F12_LEN) - 1) << USB_BLKSZ_F12_POS)) -#define USB_EN_F12 USB_EN_F12 -#define USB_EN_F12_POS (5U) -#define USB_EN_F12_LEN (1U) -#define USB_EN_F12_MSK (((1U << USB_EN_F12_LEN) - 1) << USB_EN_F12_POS) -#define USB_EN_F12_UMSK (~(((1U << USB_EN_F12_LEN) - 1) << USB_EN_F12_POS)) -#define USB_BLK_TYP_F13 USB_BLK_TYP_F13 -#define USB_BLK_TYP_F13_POS (8U) -#define USB_BLK_TYP_F13_LEN (2U) -#define USB_BLK_TYP_F13_MSK (((1U << USB_BLK_TYP_F13_LEN) - 1) << USB_BLK_TYP_F13_POS) -#define USB_BLK_TYP_F13_UMSK (~(((1U << USB_BLK_TYP_F13_LEN) - 1) << USB_BLK_TYP_F13_POS)) -#define USB_BLKNO_F13 USB_BLKNO_F13 -#define USB_BLKNO_F13_POS (10U) -#define USB_BLKNO_F13_LEN (2U) -#define USB_BLKNO_F13_MSK (((1U << USB_BLKNO_F13_LEN) - 1) << USB_BLKNO_F13_POS) -#define USB_BLKNO_F13_UMSK (~(((1U << USB_BLKNO_F13_LEN) - 1) << USB_BLKNO_F13_POS)) -#define USB_BLKSZ_F13 USB_BLKSZ_F13 -#define USB_BLKSZ_F13_POS (12U) -#define USB_BLKSZ_F13_LEN (1U) -#define USB_BLKSZ_F13_MSK (((1U << USB_BLKSZ_F13_LEN) - 1) << USB_BLKSZ_F13_POS) -#define USB_BLKSZ_F13_UMSK (~(((1U << USB_BLKSZ_F13_LEN) - 1) << USB_BLKSZ_F13_POS)) -#define USB_EN_F13 USB_EN_F13 -#define USB_EN_F13_POS (13U) -#define USB_EN_F13_LEN (1U) -#define USB_EN_F13_MSK (((1U << USB_EN_F13_LEN) - 1) << USB_EN_F13_POS) -#define USB_EN_F13_UMSK (~(((1U << USB_EN_F13_LEN) - 1) << USB_EN_F13_POS)) -#define USB_BLK_TYP_F14 USB_BLK_TYP_F14 -#define USB_BLK_TYP_F14_POS (16U) -#define USB_BLK_TYP_F14_LEN (2U) -#define USB_BLK_TYP_F14_MSK (((1U << USB_BLK_TYP_F14_LEN) - 1) << USB_BLK_TYP_F14_POS) -#define USB_BLK_TYP_F14_UMSK (~(((1U << USB_BLK_TYP_F14_LEN) - 1) << USB_BLK_TYP_F14_POS)) -#define USB_BLKNO_F14 USB_BLKNO_F14 -#define USB_BLKNO_F14_POS (18U) -#define USB_BLKNO_F14_LEN (2U) -#define USB_BLKNO_F14_MSK (((1U << USB_BLKNO_F14_LEN) - 1) << USB_BLKNO_F14_POS) -#define USB_BLKNO_F14_UMSK (~(((1U << USB_BLKNO_F14_LEN) - 1) << USB_BLKNO_F14_POS)) -#define USB_BLKSZ_F14 USB_BLKSZ_F14 -#define USB_BLKSZ_F14_POS (20U) -#define USB_BLKSZ_F14_LEN (1U) -#define USB_BLKSZ_F14_MSK (((1U << USB_BLKSZ_F14_LEN) - 1) << USB_BLKSZ_F14_POS) -#define USB_BLKSZ_F14_UMSK (~(((1U << USB_BLKSZ_F14_LEN) - 1) << USB_BLKSZ_F14_POS)) -#define USB_EN_F14 USB_EN_F14 -#define USB_EN_F14_POS (21U) -#define USB_EN_F14_LEN (1U) -#define USB_EN_F14_MSK (((1U << USB_EN_F14_LEN) - 1) << USB_EN_F14_POS) -#define USB_EN_F14_UMSK (~(((1U << USB_EN_F14_LEN) - 1) << USB_EN_F14_POS)) -#define USB_BLK_TYP_F15 USB_BLK_TYP_F15 -#define USB_BLK_TYP_F15_POS (24U) -#define USB_BLK_TYP_F15_LEN (2U) -#define USB_BLK_TYP_F15_MSK (((1U << USB_BLK_TYP_F15_LEN) - 1) << USB_BLK_TYP_F15_POS) -#define USB_BLK_TYP_F15_UMSK (~(((1U << USB_BLK_TYP_F15_LEN) - 1) << USB_BLK_TYP_F15_POS)) -#define USB_BLKNO_F15 USB_BLKNO_F15 -#define USB_BLKNO_F15_POS (26U) -#define USB_BLKNO_F15_LEN (2U) -#define USB_BLKNO_F15_MSK (((1U << USB_BLKNO_F15_LEN) - 1) << USB_BLKNO_F15_POS) -#define USB_BLKNO_F15_UMSK (~(((1U << USB_BLKNO_F15_LEN) - 1) << USB_BLKNO_F15_POS)) -#define USB_BLKSZ_F15 USB_BLKSZ_F15 -#define USB_BLKSZ_F15_POS (28U) -#define USB_BLKSZ_F15_LEN (1U) -#define USB_BLKSZ_F15_MSK (((1U << USB_BLKSZ_F15_LEN) - 1) << USB_BLKSZ_F15_POS) -#define USB_BLKSZ_F15_UMSK (~(((1U << USB_BLKSZ_F15_LEN) - 1) << USB_BLKSZ_F15_POS)) -#define USB_EN_F15 USB_EN_F15 -#define USB_EN_F15_POS (29U) -#define USB_EN_F15_LEN (1U) -#define USB_EN_F15_MSK (((1U << USB_EN_F15_LEN) - 1) << USB_EN_F15_POS) -#define USB_EN_F15_UMSK (~(((1U << USB_EN_F15_LEN) - 1) << USB_EN_F15_POS)) - -/* 0x1F0 : DEV_FIBC4 */ -#define USB_DEV_FIBC4_OFFSET (0x1F0) -#define USB_BC_F4 USB_BC_F4 -#define USB_BC_F4_POS (0U) -#define USB_BC_F4_LEN (11U) -#define USB_BC_F4_MSK (((1U << USB_BC_F4_LEN) - 1) << USB_BC_F4_POS) -#define USB_BC_F4_UMSK (~(((1U << USB_BC_F4_LEN) - 1) << USB_BC_F4_POS)) -#define USB_FFRST4_HOV USB_FFRST4_HOV -#define USB_FFRST4_HOV_POS (12U) -#define USB_FFRST4_HOV_LEN (1U) -#define USB_FFRST4_HOV_MSK (((1U << USB_FFRST4_HOV_LEN) - 1) << USB_FFRST4_HOV_POS) -#define USB_FFRST4_HOV_UMSK (~(((1U << USB_FFRST4_HOV_LEN) - 1) << USB_FFRST4_HOV_POS)) - -/* 0x1F4 : DEV_FIBC5 */ -#define USB_DEV_FIBC5_OFFSET (0x1F4) -#define USB_BC_F5 USB_BC_F5 -#define USB_BC_F5_POS (0U) -#define USB_BC_F5_LEN (11U) -#define USB_BC_F5_MSK (((1U << USB_BC_F5_LEN) - 1) << USB_BC_F5_POS) -#define USB_BC_F5_UMSK (~(((1U << USB_BC_F5_LEN) - 1) << USB_BC_F5_POS)) -#define USB_FFRST5_HOV USB_FFRST5_HOV -#define USB_FFRST5_HOV_POS (12U) -#define USB_FFRST5_HOV_LEN (1U) -#define USB_FFRST5_HOV_MSK (((1U << USB_FFRST5_HOV_LEN) - 1) << USB_FFRST5_HOV_POS) -#define USB_FFRST5_HOV_UMSK (~(((1U << USB_FFRST5_HOV_LEN) - 1) << USB_FFRST5_HOV_POS)) - -/* 0x1F8 : DEV_FIBC6 */ -#define USB_DEV_FIBC6_OFFSET (0x1F8) -#define USB_BC_F6 USB_BC_F6 -#define USB_BC_F6_POS (0U) -#define USB_BC_F6_LEN (11U) -#define USB_BC_F6_MSK (((1U << USB_BC_F6_LEN) - 1) << USB_BC_F6_POS) -#define USB_BC_F6_UMSK (~(((1U << USB_BC_F6_LEN) - 1) << USB_BC_F6_POS)) -#define USB_FFRST6_HOV USB_FFRST6_HOV -#define USB_FFRST6_HOV_POS (12U) -#define USB_FFRST6_HOV_LEN (1U) -#define USB_FFRST6_HOV_MSK (((1U << USB_FFRST6_HOV_LEN) - 1) << USB_FFRST6_HOV_POS) -#define USB_FFRST6_HOV_UMSK (~(((1U << USB_FFRST6_HOV_LEN) - 1) << USB_FFRST6_HOV_POS)) - -/* 0x1FC : DEV_FIBC7 */ -#define USB_DEV_FIBC7_OFFSET (0x1FC) -#define USB_BC_F7 USB_BC_F7 -#define USB_BC_F7_POS (0U) -#define USB_BC_F7_LEN (11U) -#define USB_BC_F7_MSK (((1U << USB_BC_F7_LEN) - 1) << USB_BC_F7_POS) -#define USB_BC_F7_UMSK (~(((1U << USB_BC_F7_LEN) - 1) << USB_BC_F7_POS)) -#define USB_FFRST7_HOV USB_FFRST7_HOV -#define USB_FFRST7_HOV_POS (12U) -#define USB_FFRST7_HOV_LEN (1U) -#define USB_FFRST7_HOV_MSK (((1U << USB_FFRST7_HOV_LEN) - 1) << USB_FFRST7_HOV_POS) -#define USB_FFRST7_HOV_UMSK (~(((1U << USB_FFRST7_HOV_LEN) - 1) << USB_FFRST7_HOV_POS)) - -/* 0x300 : VDMA_CXFPS1 */ -#define USB_VDMA_CXFPS1_OFFSET (0x300) -#define USB_VDMA_START_CXF USB_VDMA_START_CXF -#define USB_VDMA_START_CXF_POS (0U) -#define USB_VDMA_START_CXF_LEN (1U) -#define USB_VDMA_START_CXF_MSK (((1U << USB_VDMA_START_CXF_LEN) - 1) << USB_VDMA_START_CXF_POS) -#define USB_VDMA_START_CXF_UMSK (~(((1U << USB_VDMA_START_CXF_LEN) - 1) << USB_VDMA_START_CXF_POS)) -#define USB_VDMA_TYPE_CXF USB_VDMA_TYPE_CXF -#define USB_VDMA_TYPE_CXF_POS (1U) -#define USB_VDMA_TYPE_CXF_LEN (1U) -#define USB_VDMA_TYPE_CXF_MSK (((1U << USB_VDMA_TYPE_CXF_LEN) - 1) << USB_VDMA_TYPE_CXF_POS) -#define USB_VDMA_TYPE_CXF_UMSK (~(((1U << USB_VDMA_TYPE_CXF_LEN) - 1) << USB_VDMA_TYPE_CXF_POS)) -#define USB_VDMA_IO_CXF USB_VDMA_IO_CXF -#define USB_VDMA_IO_CXF_POS (2U) -#define USB_VDMA_IO_CXF_LEN (1U) -#define USB_VDMA_IO_CXF_MSK (((1U << USB_VDMA_IO_CXF_LEN) - 1) << USB_VDMA_IO_CXF_POS) -#define USB_VDMA_IO_CXF_UMSK (~(((1U << USB_VDMA_IO_CXF_LEN) - 1) << USB_VDMA_IO_CXF_POS)) -#define USB_VDMA_LEN_CXF USB_VDMA_LEN_CXF -#define USB_VDMA_LEN_CXF_POS (8U) -#define USB_VDMA_LEN_CXF_LEN (17U) -#define USB_VDMA_LEN_CXF_MSK (((1U << USB_VDMA_LEN_CXF_LEN) - 1) << USB_VDMA_LEN_CXF_POS) -#define USB_VDMA_LEN_CXF_UMSK (~(((1U << USB_VDMA_LEN_CXF_LEN) - 1) << USB_VDMA_LEN_CXF_POS)) - -/* 0x304 : None */ -#define USB_VDMA_CXFPS2_OFFSET (0x304) -#define USB_VDMA_MADDR_CXF USB_VDMA_MADDR_CXF -#define USB_VDMA_MADDR_CXF_POS (0U) -#define USB_VDMA_MADDR_CXF_LEN (32U) -#define USB_VDMA_MADDR_CXF_MSK (((1U << USB_VDMA_MADDR_CXF_LEN) - 1) << USB_VDMA_MADDR_CXF_POS) -#define USB_VDMA_MADDR_CXF_UMSK (~(((1U << USB_VDMA_MADDR_CXF_LEN) - 1) << USB_VDMA_MADDR_CXF_POS)) - -/* 0x308 : None */ -#define USB_VDMA_F0PS1_OFFSET (0x308) -#define USB_VDMA_START_F0 USB_VDMA_START_F0 -#define USB_VDMA_START_F0_POS (0U) -#define USB_VDMA_START_F0_LEN (1U) -#define USB_VDMA_START_F0_MSK (((1U << USB_VDMA_START_F0_LEN) - 1) << USB_VDMA_START_F0_POS) -#define USB_VDMA_START_F0_UMSK (~(((1U << USB_VDMA_START_F0_LEN) - 1) << USB_VDMA_START_F0_POS)) -#define USB_VDMA_TYPE_F0 USB_VDMA_TYPE_F0 -#define USB_VDMA_TYPE_F0_POS (1U) -#define USB_VDMA_TYPE_F0_LEN (1U) -#define USB_VDMA_TYPE_F0_MSK (((1U << USB_VDMA_TYPE_F0_LEN) - 1) << USB_VDMA_TYPE_F0_POS) -#define USB_VDMA_TYPE_F0_UMSK (~(((1U << USB_VDMA_TYPE_F0_LEN) - 1) << USB_VDMA_TYPE_F0_POS)) -#define USB_VDMA_IO_F0 USB_VDMA_IO_F0 -#define USB_VDMA_IO_F0_POS (2U) -#define USB_VDMA_IO_F0_LEN (1U) -#define USB_VDMA_IO_F0_MSK (((1U << USB_VDMA_IO_F0_LEN) - 1) << USB_VDMA_IO_F0_POS) -#define USB_VDMA_IO_F0_UMSK (~(((1U << USB_VDMA_IO_F0_LEN) - 1) << USB_VDMA_IO_F0_POS)) -#define USB_VDMA_LEN_F0 USB_VDMA_LEN_F0 -#define USB_VDMA_LEN_F0_POS (8U) -#define USB_VDMA_LEN_F0_LEN (17U) -#define USB_VDMA_LEN_F0_MSK (((1U << USB_VDMA_LEN_F0_LEN) - 1) << USB_VDMA_LEN_F0_POS) -#define USB_VDMA_LEN_F0_UMSK (~(((1U << USB_VDMA_LEN_F0_LEN) - 1) << USB_VDMA_LEN_F0_POS)) - -/* 0x30C : VDMA_F0PS2 */ -#define USB_VDMA_F0PS2_OFFSET (0x30C) -#define USB_VDMA_MADDR_F0 USB_VDMA_MADDR_F0 -#define USB_VDMA_MADDR_F0_POS (0U) -#define USB_VDMA_MADDR_F0_LEN (32U) -#define USB_VDMA_MADDR_F0_MSK (((1U << USB_VDMA_MADDR_F0_LEN) - 1) << USB_VDMA_MADDR_F0_POS) -#define USB_VDMA_MADDR_F0_UMSK (~(((1U << USB_VDMA_MADDR_F0_LEN) - 1) << USB_VDMA_MADDR_F0_POS)) - -/* 0x310 : VDMA_F1PS1 */ -#define USB_VDMA_F1PS1_OFFSET (0x310) -#define USB_VDMA_START_F1 USB_VDMA_START_F1 -#define USB_VDMA_START_F1_POS (0U) -#define USB_VDMA_START_F1_LEN (1U) -#define USB_VDMA_START_F1_MSK (((1U << USB_VDMA_START_F1_LEN) - 1) << USB_VDMA_START_F1_POS) -#define USB_VDMA_START_F1_UMSK (~(((1U << USB_VDMA_START_F1_LEN) - 1) << USB_VDMA_START_F1_POS)) -#define USB_VDMA_TYPE_F1 USB_VDMA_TYPE_F1 -#define USB_VDMA_TYPE_F1_POS (1U) -#define USB_VDMA_TYPE_F1_LEN (1U) -#define USB_VDMA_TYPE_F1_MSK (((1U << USB_VDMA_TYPE_F1_LEN) - 1) << USB_VDMA_TYPE_F1_POS) -#define USB_VDMA_TYPE_F1_UMSK (~(((1U << USB_VDMA_TYPE_F1_LEN) - 1) << USB_VDMA_TYPE_F1_POS)) -#define USB_VDMA_IO_F1 USB_VDMA_IO_F1 -#define USB_VDMA_IO_F1_POS (2U) -#define USB_VDMA_IO_F1_LEN (1U) -#define USB_VDMA_IO_F1_MSK (((1U << USB_VDMA_IO_F1_LEN) - 1) << USB_VDMA_IO_F1_POS) -#define USB_VDMA_IO_F1_UMSK (~(((1U << USB_VDMA_IO_F1_LEN) - 1) << USB_VDMA_IO_F1_POS)) -#define USB_VDMA_LEN_F1 USB_VDMA_LEN_F1 -#define USB_VDMA_LEN_F1_POS (8U) -#define USB_VDMA_LEN_F1_LEN (17U) -#define USB_VDMA_LEN_F1_MSK (((1U << USB_VDMA_LEN_F1_LEN) - 1) << USB_VDMA_LEN_F1_POS) -#define USB_VDMA_LEN_F1_UMSK (~(((1U << USB_VDMA_LEN_F1_LEN) - 1) << USB_VDMA_LEN_F1_POS)) - -/* 0x314 : VDMA_F1PS2 */ -#define USB_VDMA_F1PS2_OFFSET (0x314) -#define USB_VDMA_MADDR_F1 USB_VDMA_MADDR_F1 -#define USB_VDMA_MADDR_F1_POS (0U) -#define USB_VDMA_MADDR_F1_LEN (32U) -#define USB_VDMA_MADDR_F1_MSK (((1U << USB_VDMA_MADDR_F1_LEN) - 1) << USB_VDMA_MADDR_F1_POS) -#define USB_VDMA_MADDR_F1_UMSK (~(((1U << USB_VDMA_MADDR_F1_LEN) - 1) << USB_VDMA_MADDR_F1_POS)) - -/* 0x318 : VDMA_F2PS1 */ -#define USB_VDMA_F2PS1_OFFSET (0x318) -#define USB_VDMA_START_F2 USB_VDMA_START_F2 -#define USB_VDMA_START_F2_POS (0U) -#define USB_VDMA_START_F2_LEN (1U) -#define USB_VDMA_START_F2_MSK (((1U << USB_VDMA_START_F2_LEN) - 1) << USB_VDMA_START_F2_POS) -#define USB_VDMA_START_F2_UMSK (~(((1U << USB_VDMA_START_F2_LEN) - 1) << USB_VDMA_START_F2_POS)) -#define USB_VDMA_TYPE_F2 USB_VDMA_TYPE_F2 -#define USB_VDMA_TYPE_F2_POS (1U) -#define USB_VDMA_TYPE_F2_LEN (1U) -#define USB_VDMA_TYPE_F2_MSK (((1U << USB_VDMA_TYPE_F2_LEN) - 1) << USB_VDMA_TYPE_F2_POS) -#define USB_VDMA_TYPE_F2_UMSK (~(((1U << USB_VDMA_TYPE_F2_LEN) - 1) << USB_VDMA_TYPE_F2_POS)) -#define USB_VDMA_IO_F2 USB_VDMA_IO_F2 -#define USB_VDMA_IO_F2_POS (2U) -#define USB_VDMA_IO_F2_LEN (1U) -#define USB_VDMA_IO_F2_MSK (((1U << USB_VDMA_IO_F2_LEN) - 1) << USB_VDMA_IO_F2_POS) -#define USB_VDMA_IO_F2_UMSK (~(((1U << USB_VDMA_IO_F2_LEN) - 1) << USB_VDMA_IO_F2_POS)) -#define USB_VDMA_LEN_F2 USB_VDMA_LEN_F2 -#define USB_VDMA_LEN_F2_POS (8U) -#define USB_VDMA_LEN_F2_LEN (17U) -#define USB_VDMA_LEN_F2_MSK (((1U << USB_VDMA_LEN_F2_LEN) - 1) << USB_VDMA_LEN_F2_POS) -#define USB_VDMA_LEN_F2_UMSK (~(((1U << USB_VDMA_LEN_F2_LEN) - 1) << USB_VDMA_LEN_F2_POS)) - -/* 0x31C : VDMA_F2PS2 */ -#define USB_VDMA_F2PS2_OFFSET (0x31C) -#define USB_VDMA_MADDR_F2 USB_VDMA_MADDR_F2 -#define USB_VDMA_MADDR_F2_POS (0U) -#define USB_VDMA_MADDR_F2_LEN (32U) -#define USB_VDMA_MADDR_F2_MSK (((1U << USB_VDMA_MADDR_F2_LEN) - 1) << USB_VDMA_MADDR_F2_POS) -#define USB_VDMA_MADDR_F2_UMSK (~(((1U << USB_VDMA_MADDR_F2_LEN) - 1) << USB_VDMA_MADDR_F2_POS)) - -/* 0x320 : VDMA_F3PS1 */ -#define USB_VDMA_F3PS1_OFFSET (0x320) -#define USB_VDMA_START_F3 USB_VDMA_START_F3 -#define USB_VDMA_START_F3_POS (0U) -#define USB_VDMA_START_F3_LEN (1U) -#define USB_VDMA_START_F3_MSK (((1U << USB_VDMA_START_F3_LEN) - 1) << USB_VDMA_START_F3_POS) -#define USB_VDMA_START_F3_UMSK (~(((1U << USB_VDMA_START_F3_LEN) - 1) << USB_VDMA_START_F3_POS)) -#define USB_VDMA_TYPE_F3 USB_VDMA_TYPE_F3 -#define USB_VDMA_TYPE_F3_POS (1U) -#define USB_VDMA_TYPE_F3_LEN (1U) -#define USB_VDMA_TYPE_F3_MSK (((1U << USB_VDMA_TYPE_F3_LEN) - 1) << USB_VDMA_TYPE_F3_POS) -#define USB_VDMA_TYPE_F3_UMSK (~(((1U << USB_VDMA_TYPE_F3_LEN) - 1) << USB_VDMA_TYPE_F3_POS)) -#define USB_VDMA_IO_F3 USB_VDMA_IO_F3 -#define USB_VDMA_IO_F3_POS (2U) -#define USB_VDMA_IO_F3_LEN (1U) -#define USB_VDMA_IO_F3_MSK (((1U << USB_VDMA_IO_F3_LEN) - 1) << USB_VDMA_IO_F3_POS) -#define USB_VDMA_IO_F3_UMSK (~(((1U << USB_VDMA_IO_F3_LEN) - 1) << USB_VDMA_IO_F3_POS)) -#define USB_VDMA_LEN_F3 USB_VDMA_LEN_F3 -#define USB_VDMA_LEN_F3_POS (8U) -#define USB_VDMA_LEN_F3_LEN (17U) -#define USB_VDMA_LEN_F3_MSK (((1U << USB_VDMA_LEN_F3_LEN) - 1) << USB_VDMA_LEN_F3_POS) -#define USB_VDMA_LEN_F3_UMSK (~(((1U << USB_VDMA_LEN_F3_LEN) - 1) << USB_VDMA_LEN_F3_POS)) - -/* 0x324 : VDMA_F3PS2 */ -#define USB_VDMA_F3PS2_OFFSET (0x324) -#define USB_VDMA_MADDR_F3 USB_VDMA_MADDR_F3 -#define USB_VDMA_MADDR_F3_POS (0U) -#define USB_VDMA_MADDR_F3_LEN (32U) -#define USB_VDMA_MADDR_F3_MSK (((1U << USB_VDMA_MADDR_F3_LEN) - 1) << USB_VDMA_MADDR_F3_POS) -#define USB_VDMA_MADDR_F3_UMSK (~(((1U << USB_VDMA_MADDR_F3_LEN) - 1) << USB_VDMA_MADDR_F3_POS)) - -/* 0x328 : DEV_ISG3 */ -#define USB_DEV_ISG3_OFFSET (0x328) -#define USB_VDMA_CMPLT_CXF USB_VDMA_CMPLT_CXF -#define USB_VDMA_CMPLT_CXF_POS (0U) -#define USB_VDMA_CMPLT_CXF_LEN (1U) -#define USB_VDMA_CMPLT_CXF_MSK (((1U << USB_VDMA_CMPLT_CXF_LEN) - 1) << USB_VDMA_CMPLT_CXF_POS) -#define USB_VDMA_CMPLT_CXF_UMSK (~(((1U << USB_VDMA_CMPLT_CXF_LEN) - 1) << USB_VDMA_CMPLT_CXF_POS)) -#define USB_VDMA_CMPLT_F0 USB_VDMA_CMPLT_F0 -#define USB_VDMA_CMPLT_F0_POS (1U) -#define USB_VDMA_CMPLT_F0_LEN (1U) -#define USB_VDMA_CMPLT_F0_MSK (((1U << USB_VDMA_CMPLT_F0_LEN) - 1) << USB_VDMA_CMPLT_F0_POS) -#define USB_VDMA_CMPLT_F0_UMSK (~(((1U << USB_VDMA_CMPLT_F0_LEN) - 1) << USB_VDMA_CMPLT_F0_POS)) -#define USB_VDMA_CMPLT_F1 USB_VDMA_CMPLT_F1 -#define USB_VDMA_CMPLT_F1_POS (2U) -#define USB_VDMA_CMPLT_F1_LEN (1U) -#define USB_VDMA_CMPLT_F1_MSK (((1U << USB_VDMA_CMPLT_F1_LEN) - 1) << USB_VDMA_CMPLT_F1_POS) -#define USB_VDMA_CMPLT_F1_UMSK (~(((1U << USB_VDMA_CMPLT_F1_LEN) - 1) << USB_VDMA_CMPLT_F1_POS)) -#define USB_VDMA_CMPLT_F2 USB_VDMA_CMPLT_F2 -#define USB_VDMA_CMPLT_F2_POS (3U) -#define USB_VDMA_CMPLT_F2_LEN (1U) -#define USB_VDMA_CMPLT_F2_MSK (((1U << USB_VDMA_CMPLT_F2_LEN) - 1) << USB_VDMA_CMPLT_F2_POS) -#define USB_VDMA_CMPLT_F2_UMSK (~(((1U << USB_VDMA_CMPLT_F2_LEN) - 1) << USB_VDMA_CMPLT_F2_POS)) -#define USB_VDMA_CMPLT_F3 USB_VDMA_CMPLT_F3 -#define USB_VDMA_CMPLT_F3_POS (4U) -#define USB_VDMA_CMPLT_F3_LEN (1U) -#define USB_VDMA_CMPLT_F3_MSK (((1U << USB_VDMA_CMPLT_F3_LEN) - 1) << USB_VDMA_CMPLT_F3_POS) -#define USB_VDMA_CMPLT_F3_UMSK (~(((1U << USB_VDMA_CMPLT_F3_LEN) - 1) << USB_VDMA_CMPLT_F3_POS)) -#define USB_VDMA_CMPLT_F4 USB_VDMA_CMPLT_F4 -#define USB_VDMA_CMPLT_F4_POS (5U) -#define USB_VDMA_CMPLT_F4_LEN (1U) -#define USB_VDMA_CMPLT_F4_MSK (((1U << USB_VDMA_CMPLT_F4_LEN) - 1) << USB_VDMA_CMPLT_F4_POS) -#define USB_VDMA_CMPLT_F4_UMSK (~(((1U << USB_VDMA_CMPLT_F4_LEN) - 1) << USB_VDMA_CMPLT_F4_POS)) -#define USB_VDMA_CMPLT_F5 USB_VDMA_CMPLT_F5 -#define USB_VDMA_CMPLT_F5_POS (6U) -#define USB_VDMA_CMPLT_F5_LEN (1U) -#define USB_VDMA_CMPLT_F5_MSK (((1U << USB_VDMA_CMPLT_F5_LEN) - 1) << USB_VDMA_CMPLT_F5_POS) -#define USB_VDMA_CMPLT_F5_UMSK (~(((1U << USB_VDMA_CMPLT_F5_LEN) - 1) << USB_VDMA_CMPLT_F5_POS)) -#define USB_VDMA_CMPLT_F6 USB_VDMA_CMPLT_F6 -#define USB_VDMA_CMPLT_F6_POS (7U) -#define USB_VDMA_CMPLT_F6_LEN (1U) -#define USB_VDMA_CMPLT_F6_MSK (((1U << USB_VDMA_CMPLT_F6_LEN) - 1) << USB_VDMA_CMPLT_F6_POS) -#define USB_VDMA_CMPLT_F6_UMSK (~(((1U << USB_VDMA_CMPLT_F6_LEN) - 1) << USB_VDMA_CMPLT_F6_POS)) -#define USB_VDMA_CMPLT_F7 USB_VDMA_CMPLT_F7 -#define USB_VDMA_CMPLT_F7_POS (8U) -#define USB_VDMA_CMPLT_F7_LEN (1U) -#define USB_VDMA_CMPLT_F7_MSK (((1U << USB_VDMA_CMPLT_F7_LEN) - 1) << USB_VDMA_CMPLT_F7_POS) -#define USB_VDMA_CMPLT_F7_UMSK (~(((1U << USB_VDMA_CMPLT_F7_LEN) - 1) << USB_VDMA_CMPLT_F7_POS)) -#define USB_VDMA_CMPLT_F8 USB_VDMA_CMPLT_F8 -#define USB_VDMA_CMPLT_F8_POS (9U) -#define USB_VDMA_CMPLT_F8_LEN (1U) -#define USB_VDMA_CMPLT_F8_MSK (((1U << USB_VDMA_CMPLT_F8_LEN) - 1) << USB_VDMA_CMPLT_F8_POS) -#define USB_VDMA_CMPLT_F8_UMSK (~(((1U << USB_VDMA_CMPLT_F8_LEN) - 1) << USB_VDMA_CMPLT_F8_POS)) -#define USB_VDMA_CMPLT_F9 USB_VDMA_CMPLT_F9 -#define USB_VDMA_CMPLT_F9_POS (10U) -#define USB_VDMA_CMPLT_F9_LEN (1U) -#define USB_VDMA_CMPLT_F9_MSK (((1U << USB_VDMA_CMPLT_F9_LEN) - 1) << USB_VDMA_CMPLT_F9_POS) -#define USB_VDMA_CMPLT_F9_UMSK (~(((1U << USB_VDMA_CMPLT_F9_LEN) - 1) << USB_VDMA_CMPLT_F9_POS)) -#define USB_VDMA_CMPLT_F10 USB_VDMA_CMPLT_F10 -#define USB_VDMA_CMPLT_F10_POS (11U) -#define USB_VDMA_CMPLT_F10_LEN (1U) -#define USB_VDMA_CMPLT_F10_MSK (((1U << USB_VDMA_CMPLT_F10_LEN) - 1) << USB_VDMA_CMPLT_F10_POS) -#define USB_VDMA_CMPLT_F10_UMSK (~(((1U << USB_VDMA_CMPLT_F10_LEN) - 1) << USB_VDMA_CMPLT_F10_POS)) -#define USB_VDMA_CMPLT_F11 USB_VDMA_CMPLT_F11 -#define USB_VDMA_CMPLT_F11_POS (12U) -#define USB_VDMA_CMPLT_F11_LEN (1U) -#define USB_VDMA_CMPLT_F11_MSK (((1U << USB_VDMA_CMPLT_F11_LEN) - 1) << USB_VDMA_CMPLT_F11_POS) -#define USB_VDMA_CMPLT_F11_UMSK (~(((1U << USB_VDMA_CMPLT_F11_LEN) - 1) << USB_VDMA_CMPLT_F11_POS)) -#define USB_VDMA_CMPLT_F12 USB_VDMA_CMPLT_F12 -#define USB_VDMA_CMPLT_F12_POS (13U) -#define USB_VDMA_CMPLT_F12_LEN (1U) -#define USB_VDMA_CMPLT_F12_MSK (((1U << USB_VDMA_CMPLT_F12_LEN) - 1) << USB_VDMA_CMPLT_F12_POS) -#define USB_VDMA_CMPLT_F12_UMSK (~(((1U << USB_VDMA_CMPLT_F12_LEN) - 1) << USB_VDMA_CMPLT_F12_POS)) -#define USB_VDMA_CMPLT_F13 USB_VDMA_CMPLT_F13 -#define USB_VDMA_CMPLT_F13_POS (14U) -#define USB_VDMA_CMPLT_F13_LEN (1U) -#define USB_VDMA_CMPLT_F13_MSK (((1U << USB_VDMA_CMPLT_F13_LEN) - 1) << USB_VDMA_CMPLT_F13_POS) -#define USB_VDMA_CMPLT_F13_UMSK (~(((1U << USB_VDMA_CMPLT_F13_LEN) - 1) << USB_VDMA_CMPLT_F13_POS)) -#define USB_VDMA_CMPLT_F14 USB_VDMA_CMPLT_F14 -#define USB_VDMA_CMPLT_F14_POS (15U) -#define USB_VDMA_CMPLT_F14_LEN (1U) -#define USB_VDMA_CMPLT_F14_MSK (((1U << USB_VDMA_CMPLT_F14_LEN) - 1) << USB_VDMA_CMPLT_F14_POS) -#define USB_VDMA_CMPLT_F14_UMSK (~(((1U << USB_VDMA_CMPLT_F14_LEN) - 1) << USB_VDMA_CMPLT_F14_POS)) -#define USB_VDMA_ERROR_CXF USB_VDMA_ERROR_CXF -#define USB_VDMA_ERROR_CXF_POS (16U) -#define USB_VDMA_ERROR_CXF_LEN (1U) -#define USB_VDMA_ERROR_CXF_MSK (((1U << USB_VDMA_ERROR_CXF_LEN) - 1) << USB_VDMA_ERROR_CXF_POS) -#define USB_VDMA_ERROR_CXF_UMSK (~(((1U << USB_VDMA_ERROR_CXF_LEN) - 1) << USB_VDMA_ERROR_CXF_POS)) -#define USB_VDMA_ERROR_F0 USB_VDMA_ERROR_F0 -#define USB_VDMA_ERROR_F0_POS (17U) -#define USB_VDMA_ERROR_F0_LEN (1U) -#define USB_VDMA_ERROR_F0_MSK (((1U << USB_VDMA_ERROR_F0_LEN) - 1) << USB_VDMA_ERROR_F0_POS) -#define USB_VDMA_ERROR_F0_UMSK (~(((1U << USB_VDMA_ERROR_F0_LEN) - 1) << USB_VDMA_ERROR_F0_POS)) -#define USB_VDMA_ERROR_F1 USB_VDMA_ERROR_F1 -#define USB_VDMA_ERROR_F1_POS (18U) -#define USB_VDMA_ERROR_F1_LEN (1U) -#define USB_VDMA_ERROR_F1_MSK (((1U << USB_VDMA_ERROR_F1_LEN) - 1) << USB_VDMA_ERROR_F1_POS) -#define USB_VDMA_ERROR_F1_UMSK (~(((1U << USB_VDMA_ERROR_F1_LEN) - 1) << USB_VDMA_ERROR_F1_POS)) -#define USB_VDMA_ERROR_F2 USB_VDMA_ERROR_F2 -#define USB_VDMA_ERROR_F2_POS (19U) -#define USB_VDMA_ERROR_F2_LEN (1U) -#define USB_VDMA_ERROR_F2_MSK (((1U << USB_VDMA_ERROR_F2_LEN) - 1) << USB_VDMA_ERROR_F2_POS) -#define USB_VDMA_ERROR_F2_UMSK (~(((1U << USB_VDMA_ERROR_F2_LEN) - 1) << USB_VDMA_ERROR_F2_POS)) -#define USB_VDMA_ERROR_F3 USB_VDMA_ERROR_F3 -#define USB_VDMA_ERROR_F3_POS (20U) -#define USB_VDMA_ERROR_F3_LEN (1U) -#define USB_VDMA_ERROR_F3_MSK (((1U << USB_VDMA_ERROR_F3_LEN) - 1) << USB_VDMA_ERROR_F3_POS) -#define USB_VDMA_ERROR_F3_UMSK (~(((1U << USB_VDMA_ERROR_F3_LEN) - 1) << USB_VDMA_ERROR_F3_POS)) -#define USB_VDMA_ERROR_F4 USB_VDMA_ERROR_F4 -#define USB_VDMA_ERROR_F4_POS (21U) -#define USB_VDMA_ERROR_F4_LEN (1U) -#define USB_VDMA_ERROR_F4_MSK (((1U << USB_VDMA_ERROR_F4_LEN) - 1) << USB_VDMA_ERROR_F4_POS) -#define USB_VDMA_ERROR_F4_UMSK (~(((1U << USB_VDMA_ERROR_F4_LEN) - 1) << USB_VDMA_ERROR_F4_POS)) -#define USB_VDMA_ERROR_F5 USB_VDMA_ERROR_F5 -#define USB_VDMA_ERROR_F5_POS (22U) -#define USB_VDMA_ERROR_F5_LEN (1U) -#define USB_VDMA_ERROR_F5_MSK (((1U << USB_VDMA_ERROR_F5_LEN) - 1) << USB_VDMA_ERROR_F5_POS) -#define USB_VDMA_ERROR_F5_UMSK (~(((1U << USB_VDMA_ERROR_F5_LEN) - 1) << USB_VDMA_ERROR_F5_POS)) -#define USB_VDMA_ERROR_F6 USB_VDMA_ERROR_F6 -#define USB_VDMA_ERROR_F6_POS (23U) -#define USB_VDMA_ERROR_F6_LEN (1U) -#define USB_VDMA_ERROR_F6_MSK (((1U << USB_VDMA_ERROR_F6_LEN) - 1) << USB_VDMA_ERROR_F6_POS) -#define USB_VDMA_ERROR_F6_UMSK (~(((1U << USB_VDMA_ERROR_F6_LEN) - 1) << USB_VDMA_ERROR_F6_POS)) -#define USB_VDMA_ERROR_F7 USB_VDMA_ERROR_F7 -#define USB_VDMA_ERROR_F7_POS (24U) -#define USB_VDMA_ERROR_F7_LEN (1U) -#define USB_VDMA_ERROR_F7_MSK (((1U << USB_VDMA_ERROR_F7_LEN) - 1) << USB_VDMA_ERROR_F7_POS) -#define USB_VDMA_ERROR_F7_UMSK (~(((1U << USB_VDMA_ERROR_F7_LEN) - 1) << USB_VDMA_ERROR_F7_POS)) -#define USB_VDMA_ERROR_F8 USB_VDMA_ERROR_F8 -#define USB_VDMA_ERROR_F8_POS (25U) -#define USB_VDMA_ERROR_F8_LEN (1U) -#define USB_VDMA_ERROR_F8_MSK (((1U << USB_VDMA_ERROR_F8_LEN) - 1) << USB_VDMA_ERROR_F8_POS) -#define USB_VDMA_ERROR_F8_UMSK (~(((1U << USB_VDMA_ERROR_F8_LEN) - 1) << USB_VDMA_ERROR_F8_POS)) -#define USB_VDMA_ERROR_F9 USB_VDMA_ERROR_F9 -#define USB_VDMA_ERROR_F9_POS (26U) -#define USB_VDMA_ERROR_F9_LEN (1U) -#define USB_VDMA_ERROR_F9_MSK (((1U << USB_VDMA_ERROR_F9_LEN) - 1) << USB_VDMA_ERROR_F9_POS) -#define USB_VDMA_ERROR_F9_UMSK (~(((1U << USB_VDMA_ERROR_F9_LEN) - 1) << USB_VDMA_ERROR_F9_POS)) -#define USB_VDMA_ERROR_F10 USB_VDMA_ERROR_F10 -#define USB_VDMA_ERROR_F10_POS (27U) -#define USB_VDMA_ERROR_F10_LEN (1U) -#define USB_VDMA_ERROR_F10_MSK (((1U << USB_VDMA_ERROR_F10_LEN) - 1) << USB_VDMA_ERROR_F10_POS) -#define USB_VDMA_ERROR_F10_UMSK (~(((1U << USB_VDMA_ERROR_F10_LEN) - 1) << USB_VDMA_ERROR_F10_POS)) -#define USB_VDMA_ERROR_F11 USB_VDMA_ERROR_F11 -#define USB_VDMA_ERROR_F11_POS (28U) -#define USB_VDMA_ERROR_F11_LEN (1U) -#define USB_VDMA_ERROR_F11_MSK (((1U << USB_VDMA_ERROR_F11_LEN) - 1) << USB_VDMA_ERROR_F11_POS) -#define USB_VDMA_ERROR_F11_UMSK (~(((1U << USB_VDMA_ERROR_F11_LEN) - 1) << USB_VDMA_ERROR_F11_POS)) -#define USB_VDMA_ERROR_F12 USB_VDMA_ERROR_F12 -#define USB_VDMA_ERROR_F12_POS (29U) -#define USB_VDMA_ERROR_F12_LEN (1U) -#define USB_VDMA_ERROR_F12_MSK (((1U << USB_VDMA_ERROR_F12_LEN) - 1) << USB_VDMA_ERROR_F12_POS) -#define USB_VDMA_ERROR_F12_UMSK (~(((1U << USB_VDMA_ERROR_F12_LEN) - 1) << USB_VDMA_ERROR_F12_POS)) -#define USB_VDMA_ERROR_F13 USB_VDMA_ERROR_F13 -#define USB_VDMA_ERROR_F13_POS (30U) -#define USB_VDMA_ERROR_F13_LEN (1U) -#define USB_VDMA_ERROR_F13_MSK (((1U << USB_VDMA_ERROR_F13_LEN) - 1) << USB_VDMA_ERROR_F13_POS) -#define USB_VDMA_ERROR_F13_UMSK (~(((1U << USB_VDMA_ERROR_F13_LEN) - 1) << USB_VDMA_ERROR_F13_POS)) -#define USB_VDMA_ERROR_F14 USB_VDMA_ERROR_F14 -#define USB_VDMA_ERROR_F14_POS (31U) -#define USB_VDMA_ERROR_F14_LEN (1U) -#define USB_VDMA_ERROR_F14_MSK (((1U << USB_VDMA_ERROR_F14_LEN) - 1) << USB_VDMA_ERROR_F14_POS) -#define USB_VDMA_ERROR_F14_UMSK (~(((1U << USB_VDMA_ERROR_F14_LEN) - 1) << USB_VDMA_ERROR_F14_POS)) - -/* 0x32C : DEV_MISG3 */ -#define USB_DEV_MISG3_OFFSET (0x32C) -#define USB_MVDMA_CMPLT_CXF USB_MVDMA_CMPLT_CXF -#define USB_MVDMA_CMPLT_CXF_POS (0U) -#define USB_MVDMA_CMPLT_CXF_LEN (1U) -#define USB_MVDMA_CMPLT_CXF_MSK (((1U << USB_MVDMA_CMPLT_CXF_LEN) - 1) << USB_MVDMA_CMPLT_CXF_POS) -#define USB_MVDMA_CMPLT_CXF_UMSK (~(((1U << USB_MVDMA_CMPLT_CXF_LEN) - 1) << USB_MVDMA_CMPLT_CXF_POS)) -#define USB_MVDMA_CMPLT_F0 USB_MVDMA_CMPLT_F0 -#define USB_MVDMA_CMPLT_F0_POS (1U) -#define USB_MVDMA_CMPLT_F0_LEN (1U) -#define USB_MVDMA_CMPLT_F0_MSK (((1U << USB_MVDMA_CMPLT_F0_LEN) - 1) << USB_MVDMA_CMPLT_F0_POS) -#define USB_MVDMA_CMPLT_F0_UMSK (~(((1U << USB_MVDMA_CMPLT_F0_LEN) - 1) << USB_MVDMA_CMPLT_F0_POS)) -#define USB_MVDMA_CMPLT_F1 USB_MVDMA_CMPLT_F1 -#define USB_MVDMA_CMPLT_F1_POS (2U) -#define USB_MVDMA_CMPLT_F1_LEN (1U) -#define USB_MVDMA_CMPLT_F1_MSK (((1U << USB_MVDMA_CMPLT_F1_LEN) - 1) << USB_MVDMA_CMPLT_F1_POS) -#define USB_MVDMA_CMPLT_F1_UMSK (~(((1U << USB_MVDMA_CMPLT_F1_LEN) - 1) << USB_MVDMA_CMPLT_F1_POS)) -#define USB_MVDMA_CMPLT_F2 USB_MVDMA_CMPLT_F2 -#define USB_MVDMA_CMPLT_F2_POS (3U) -#define USB_MVDMA_CMPLT_F2_LEN (1U) -#define USB_MVDMA_CMPLT_F2_MSK (((1U << USB_MVDMA_CMPLT_F2_LEN) - 1) << USB_MVDMA_CMPLT_F2_POS) -#define USB_MVDMA_CMPLT_F2_UMSK (~(((1U << USB_MVDMA_CMPLT_F2_LEN) - 1) << USB_MVDMA_CMPLT_F2_POS)) -#define USB_MVDMA_CMPLT_F3 USB_MVDMA_CMPLT_F3 -#define USB_MVDMA_CMPLT_F3_POS (4U) -#define USB_MVDMA_CMPLT_F3_LEN (1U) -#define USB_MVDMA_CMPLT_F3_MSK (((1U << USB_MVDMA_CMPLT_F3_LEN) - 1) << USB_MVDMA_CMPLT_F3_POS) -#define USB_MVDMA_CMPLT_F3_UMSK (~(((1U << USB_MVDMA_CMPLT_F3_LEN) - 1) << USB_MVDMA_CMPLT_F3_POS)) -#define USB_MVDMA_CMPLT_F4 USB_MVDMA_CMPLT_F4 -#define USB_MVDMA_CMPLT_F4_POS (5U) -#define USB_MVDMA_CMPLT_F4_LEN (1U) -#define USB_MVDMA_CMPLT_F4_MSK (((1U << USB_MVDMA_CMPLT_F4_LEN) - 1) << USB_MVDMA_CMPLT_F4_POS) -#define USB_MVDMA_CMPLT_F4_UMSK (~(((1U << USB_MVDMA_CMPLT_F4_LEN) - 1) << USB_MVDMA_CMPLT_F4_POS)) -#define USB_MVDMA_CMPLT_F5 USB_MVDMA_CMPLT_F5 -#define USB_MVDMA_CMPLT_F5_POS (6U) -#define USB_MVDMA_CMPLT_F5_LEN (1U) -#define USB_MVDMA_CMPLT_F5_MSK (((1U << USB_MVDMA_CMPLT_F5_LEN) - 1) << USB_MVDMA_CMPLT_F5_POS) -#define USB_MVDMA_CMPLT_F5_UMSK (~(((1U << USB_MVDMA_CMPLT_F5_LEN) - 1) << USB_MVDMA_CMPLT_F5_POS)) -#define USB_MVDMA_CMPLT_F6 USB_MVDMA_CMPLT_F6 -#define USB_MVDMA_CMPLT_F6_POS (7U) -#define USB_MVDMA_CMPLT_F6_LEN (1U) -#define USB_MVDMA_CMPLT_F6_MSK (((1U << USB_MVDMA_CMPLT_F6_LEN) - 1) << USB_MVDMA_CMPLT_F6_POS) -#define USB_MVDMA_CMPLT_F6_UMSK (~(((1U << USB_MVDMA_CMPLT_F6_LEN) - 1) << USB_MVDMA_CMPLT_F6_POS)) -#define USB_MVDMA_CMPLT_F7 USB_MVDMA_CMPLT_F7 -#define USB_MVDMA_CMPLT_F7_POS (8U) -#define USB_MVDMA_CMPLT_F7_LEN (1U) -#define USB_MVDMA_CMPLT_F7_MSK (((1U << USB_MVDMA_CMPLT_F7_LEN) - 1) << USB_MVDMA_CMPLT_F7_POS) -#define USB_MVDMA_CMPLT_F7_UMSK (~(((1U << USB_MVDMA_CMPLT_F7_LEN) - 1) << USB_MVDMA_CMPLT_F7_POS)) -#define USB_MVDMA_CMPLT_F8 USB_MVDMA_CMPLT_F8 -#define USB_MVDMA_CMPLT_F8_POS (9U) -#define USB_MVDMA_CMPLT_F8_LEN (1U) -#define USB_MVDMA_CMPLT_F8_MSK (((1U << USB_MVDMA_CMPLT_F8_LEN) - 1) << USB_MVDMA_CMPLT_F8_POS) -#define USB_MVDMA_CMPLT_F8_UMSK (~(((1U << USB_MVDMA_CMPLT_F8_LEN) - 1) << USB_MVDMA_CMPLT_F8_POS)) -#define USB_MVDMA_CMPLT_F9 USB_MVDMA_CMPLT_F9 -#define USB_MVDMA_CMPLT_F9_POS (10U) -#define USB_MVDMA_CMPLT_F9_LEN (1U) -#define USB_MVDMA_CMPLT_F9_MSK (((1U << USB_MVDMA_CMPLT_F9_LEN) - 1) << USB_MVDMA_CMPLT_F9_POS) -#define USB_MVDMA_CMPLT_F9_UMSK (~(((1U << USB_MVDMA_CMPLT_F9_LEN) - 1) << USB_MVDMA_CMPLT_F9_POS)) -#define USB_MVDMA_CMPLT_F10 USB_MVDMA_CMPLT_F10 -#define USB_MVDMA_CMPLT_F10_POS (11U) -#define USB_MVDMA_CMPLT_F10_LEN (1U) -#define USB_MVDMA_CMPLT_F10_MSK (((1U << USB_MVDMA_CMPLT_F10_LEN) - 1) << USB_MVDMA_CMPLT_F10_POS) -#define USB_MVDMA_CMPLT_F10_UMSK (~(((1U << USB_MVDMA_CMPLT_F10_LEN) - 1) << USB_MVDMA_CMPLT_F10_POS)) -#define USB_MVDMA_CMPLT_F11 USB_MVDMA_CMPLT_F11 -#define USB_MVDMA_CMPLT_F11_POS (12U) -#define USB_MVDMA_CMPLT_F11_LEN (1U) -#define USB_MVDMA_CMPLT_F11_MSK (((1U << USB_MVDMA_CMPLT_F11_LEN) - 1) << USB_MVDMA_CMPLT_F11_POS) -#define USB_MVDMA_CMPLT_F11_UMSK (~(((1U << USB_MVDMA_CMPLT_F11_LEN) - 1) << USB_MVDMA_CMPLT_F11_POS)) -#define USB_MVDMA_CMPLT_F12 USB_MVDMA_CMPLT_F12 -#define USB_MVDMA_CMPLT_F12_POS (13U) -#define USB_MVDMA_CMPLT_F12_LEN (1U) -#define USB_MVDMA_CMPLT_F12_MSK (((1U << USB_MVDMA_CMPLT_F12_LEN) - 1) << USB_MVDMA_CMPLT_F12_POS) -#define USB_MVDMA_CMPLT_F12_UMSK (~(((1U << USB_MVDMA_CMPLT_F12_LEN) - 1) << USB_MVDMA_CMPLT_F12_POS)) -#define USB_MVDMA_CMPLT_F13 USB_MVDMA_CMPLT_F13 -#define USB_MVDMA_CMPLT_F13_POS (14U) -#define USB_MVDMA_CMPLT_F13_LEN (1U) -#define USB_MVDMA_CMPLT_F13_MSK (((1U << USB_MVDMA_CMPLT_F13_LEN) - 1) << USB_MVDMA_CMPLT_F13_POS) -#define USB_MVDMA_CMPLT_F13_UMSK (~(((1U << USB_MVDMA_CMPLT_F13_LEN) - 1) << USB_MVDMA_CMPLT_F13_POS)) -#define USB_MVDMA_CMPLT_F14 USB_MVDMA_CMPLT_F14 -#define USB_MVDMA_CMPLT_F14_POS (15U) -#define USB_MVDMA_CMPLT_F14_LEN (1U) -#define USB_MVDMA_CMPLT_F14_MSK (((1U << USB_MVDMA_CMPLT_F14_LEN) - 1) << USB_MVDMA_CMPLT_F14_POS) -#define USB_MVDMA_CMPLT_F14_UMSK (~(((1U << USB_MVDMA_CMPLT_F14_LEN) - 1) << USB_MVDMA_CMPLT_F14_POS)) -#define USB_MVDMA_ERROR_CXF USB_MVDMA_ERROR_CXF -#define USB_MVDMA_ERROR_CXF_POS (16U) -#define USB_MVDMA_ERROR_CXF_LEN (1U) -#define USB_MVDMA_ERROR_CXF_MSK (((1U << USB_MVDMA_ERROR_CXF_LEN) - 1) << USB_MVDMA_ERROR_CXF_POS) -#define USB_MVDMA_ERROR_CXF_UMSK (~(((1U << USB_MVDMA_ERROR_CXF_LEN) - 1) << USB_MVDMA_ERROR_CXF_POS)) -#define USB_MVDMA_ERROR_F0 USB_MVDMA_ERROR_F0 -#define USB_MVDMA_ERROR_F0_POS (17U) -#define USB_MVDMA_ERROR_F0_LEN (1U) -#define USB_MVDMA_ERROR_F0_MSK (((1U << USB_MVDMA_ERROR_F0_LEN) - 1) << USB_MVDMA_ERROR_F0_POS) -#define USB_MVDMA_ERROR_F0_UMSK (~(((1U << USB_MVDMA_ERROR_F0_LEN) - 1) << USB_MVDMA_ERROR_F0_POS)) -#define USB_MVDMA_ERROR_F1 USB_MVDMA_ERROR_F1 -#define USB_MVDMA_ERROR_F1_POS (18U) -#define USB_MVDMA_ERROR_F1_LEN (1U) -#define USB_MVDMA_ERROR_F1_MSK (((1U << USB_MVDMA_ERROR_F1_LEN) - 1) << USB_MVDMA_ERROR_F1_POS) -#define USB_MVDMA_ERROR_F1_UMSK (~(((1U << USB_MVDMA_ERROR_F1_LEN) - 1) << USB_MVDMA_ERROR_F1_POS)) -#define USB_MVDMA_ERROR_F2 USB_MVDMA_ERROR_F2 -#define USB_MVDMA_ERROR_F2_POS (19U) -#define USB_MVDMA_ERROR_F2_LEN (1U) -#define USB_MVDMA_ERROR_F2_MSK (((1U << USB_MVDMA_ERROR_F2_LEN) - 1) << USB_MVDMA_ERROR_F2_POS) -#define USB_MVDMA_ERROR_F2_UMSK (~(((1U << USB_MVDMA_ERROR_F2_LEN) - 1) << USB_MVDMA_ERROR_F2_POS)) -#define USB_MVDMA_ERROR_F3 USB_MVDMA_ERROR_F3 -#define USB_MVDMA_ERROR_F3_POS (20U) -#define USB_MVDMA_ERROR_F3_LEN (1U) -#define USB_MVDMA_ERROR_F3_MSK (((1U << USB_MVDMA_ERROR_F3_LEN) - 1) << USB_MVDMA_ERROR_F3_POS) -#define USB_MVDMA_ERROR_F3_UMSK (~(((1U << USB_MVDMA_ERROR_F3_LEN) - 1) << USB_MVDMA_ERROR_F3_POS)) -#define USB_MVDMA_ERROR_F4 USB_MVDMA_ERROR_F4 -#define USB_MVDMA_ERROR_F4_POS (21U) -#define USB_MVDMA_ERROR_F4_LEN (1U) -#define USB_MVDMA_ERROR_F4_MSK (((1U << USB_MVDMA_ERROR_F4_LEN) - 1) << USB_MVDMA_ERROR_F4_POS) -#define USB_MVDMA_ERROR_F4_UMSK (~(((1U << USB_MVDMA_ERROR_F4_LEN) - 1) << USB_MVDMA_ERROR_F4_POS)) -#define USB_MVDMA_ERROR_F5 USB_MVDMA_ERROR_F5 -#define USB_MVDMA_ERROR_F5_POS (22U) -#define USB_MVDMA_ERROR_F5_LEN (1U) -#define USB_MVDMA_ERROR_F5_MSK (((1U << USB_MVDMA_ERROR_F5_LEN) - 1) << USB_MVDMA_ERROR_F5_POS) -#define USB_MVDMA_ERROR_F5_UMSK (~(((1U << USB_MVDMA_ERROR_F5_LEN) - 1) << USB_MVDMA_ERROR_F5_POS)) -#define USB_MVDMA_ERROR_F6 USB_MVDMA_ERROR_F6 -#define USB_MVDMA_ERROR_F6_POS (23U) -#define USB_MVDMA_ERROR_F6_LEN (1U) -#define USB_MVDMA_ERROR_F6_MSK (((1U << USB_MVDMA_ERROR_F6_LEN) - 1) << USB_MVDMA_ERROR_F6_POS) -#define USB_MVDMA_ERROR_F6_UMSK (~(((1U << USB_MVDMA_ERROR_F6_LEN) - 1) << USB_MVDMA_ERROR_F6_POS)) -#define USB_MVDMA_ERROR_F7 USB_MVDMA_ERROR_F7 -#define USB_MVDMA_ERROR_F7_POS (24U) -#define USB_MVDMA_ERROR_F7_LEN (1U) -#define USB_MVDMA_ERROR_F7_MSK (((1U << USB_MVDMA_ERROR_F7_LEN) - 1) << USB_MVDMA_ERROR_F7_POS) -#define USB_MVDMA_ERROR_F7_UMSK (~(((1U << USB_MVDMA_ERROR_F7_LEN) - 1) << USB_MVDMA_ERROR_F7_POS)) -#define USB_MVDMA_ERROR_F8 USB_MVDMA_ERROR_F8 -#define USB_MVDMA_ERROR_F8_POS (25U) -#define USB_MVDMA_ERROR_F8_LEN (1U) -#define USB_MVDMA_ERROR_F8_MSK (((1U << USB_MVDMA_ERROR_F8_LEN) - 1) << USB_MVDMA_ERROR_F8_POS) -#define USB_MVDMA_ERROR_F8_UMSK (~(((1U << USB_MVDMA_ERROR_F8_LEN) - 1) << USB_MVDMA_ERROR_F8_POS)) -#define USB_MVDMA_ERROR_F9 USB_MVDMA_ERROR_F9 -#define USB_MVDMA_ERROR_F9_POS (26U) -#define USB_MVDMA_ERROR_F9_LEN (1U) -#define USB_MVDMA_ERROR_F9_MSK (((1U << USB_MVDMA_ERROR_F9_LEN) - 1) << USB_MVDMA_ERROR_F9_POS) -#define USB_MVDMA_ERROR_F9_UMSK (~(((1U << USB_MVDMA_ERROR_F9_LEN) - 1) << USB_MVDMA_ERROR_F9_POS)) -#define USB_MVDMA_ERROR_F10 USB_MVDMA_ERROR_F10 -#define USB_MVDMA_ERROR_F10_POS (27U) -#define USB_MVDMA_ERROR_F10_LEN (1U) -#define USB_MVDMA_ERROR_F10_MSK (((1U << USB_MVDMA_ERROR_F10_LEN) - 1) << USB_MVDMA_ERROR_F10_POS) -#define USB_MVDMA_ERROR_F10_UMSK (~(((1U << USB_MVDMA_ERROR_F10_LEN) - 1) << USB_MVDMA_ERROR_F10_POS)) -#define USB_MVDMA_ERROR_F11 USB_MVDMA_ERROR_F11 -#define USB_MVDMA_ERROR_F11_POS (28U) -#define USB_MVDMA_ERROR_F11_LEN (1U) -#define USB_MVDMA_ERROR_F11_MSK (((1U << USB_MVDMA_ERROR_F11_LEN) - 1) << USB_MVDMA_ERROR_F11_POS) -#define USB_MVDMA_ERROR_F11_UMSK (~(((1U << USB_MVDMA_ERROR_F11_LEN) - 1) << USB_MVDMA_ERROR_F11_POS)) -#define USB_MVDMA_ERROR_F12 USB_MVDMA_ERROR_F12 -#define USB_MVDMA_ERROR_F12_POS (29U) -#define USB_MVDMA_ERROR_F12_LEN (1U) -#define USB_MVDMA_ERROR_F12_MSK (((1U << USB_MVDMA_ERROR_F12_LEN) - 1) << USB_MVDMA_ERROR_F12_POS) -#define USB_MVDMA_ERROR_F12_UMSK (~(((1U << USB_MVDMA_ERROR_F12_LEN) - 1) << USB_MVDMA_ERROR_F12_POS)) -#define USB_MVDMA_ERROR_F13 USB_MVDMA_ERROR_F13 -#define USB_MVDMA_ERROR_F13_POS (30U) -#define USB_MVDMA_ERROR_F13_LEN (1U) -#define USB_MVDMA_ERROR_F13_MSK (((1U << USB_MVDMA_ERROR_F13_LEN) - 1) << USB_MVDMA_ERROR_F13_POS) -#define USB_MVDMA_ERROR_F13_UMSK (~(((1U << USB_MVDMA_ERROR_F13_LEN) - 1) << USB_MVDMA_ERROR_F13_POS)) -#define USB_MVDMA_ERROR_F14 USB_MVDMA_ERROR_F14 -#define USB_MVDMA_ERROR_F14_POS (31U) -#define USB_MVDMA_ERROR_F14_LEN (1U) -#define USB_MVDMA_ERROR_F14_MSK (((1U << USB_MVDMA_ERROR_F14_LEN) - 1) << USB_MVDMA_ERROR_F14_POS) -#define USB_MVDMA_ERROR_F14_UMSK (~(((1U << USB_MVDMA_ERROR_F14_LEN) - 1) << USB_MVDMA_ERROR_F14_POS)) - -/* 0x330 : VDMA_CTRL */ -#define USB_VDMA_CTRL_OFFSET (0x330) -#define USB_VDMA_EN USB_VDMA_EN -#define USB_VDMA_EN_POS (0U) -#define USB_VDMA_EN_LEN (1U) -#define USB_VDMA_EN_MSK (((1U << USB_VDMA_EN_LEN) - 1) << USB_VDMA_EN_POS) -#define USB_VDMA_EN_UMSK (~(((1U << USB_VDMA_EN_LEN) - 1) << USB_VDMA_EN_POS)) - -/* 0x334 : LPM_CAP */ -#define USB_LPM_CAP_OFFSET (0x334) -#define USB_LPM_WAKEUP_EN USB_LPM_WAKEUP_EN -#define USB_LPM_WAKEUP_EN_POS (0U) -#define USB_LPM_WAKEUP_EN_LEN (1U) -#define USB_LPM_WAKEUP_EN_MSK (((1U << USB_LPM_WAKEUP_EN_LEN) - 1) << USB_LPM_WAKEUP_EN_POS) -#define USB_LPM_WAKEUP_EN_UMSK (~(((1U << USB_LPM_WAKEUP_EN_LEN) - 1) << USB_LPM_WAKEUP_EN_POS)) - -/* 0x338 : DEV_ISG4 */ -#define USB_DEV_ISG4_OFFSET (0x338) -#define USB_L1_INT USB_L1_INT -#define USB_L1_INT_POS (0U) -#define USB_L1_INT_LEN (1U) -#define USB_L1_INT_MSK (((1U << USB_L1_INT_LEN) - 1) << USB_L1_INT_POS) -#define USB_L1_INT_UMSK (~(((1U << USB_L1_INT_LEN) - 1) << USB_L1_INT_POS)) -#define USB_VDMA_CMPLT_F15 USB_VDMA_CMPLT_F15 -#define USB_VDMA_CMPLT_F15_POS (16U) -#define USB_VDMA_CMPLT_F15_LEN (1U) -#define USB_VDMA_CMPLT_F15_MSK (((1U << USB_VDMA_CMPLT_F15_LEN) - 1) << USB_VDMA_CMPLT_F15_POS) -#define USB_VDMA_CMPLT_F15_UMSK (~(((1U << USB_VDMA_CMPLT_F15_LEN) - 1) << USB_VDMA_CMPLT_F15_POS)) -#define USB_VDMA_ERROR_F15 USB_VDMA_ERROR_F15 -#define USB_VDMA_ERROR_F15_POS (24U) -#define USB_VDMA_ERROR_F15_LEN (1U) -#define USB_VDMA_ERROR_F15_MSK (((1U << USB_VDMA_ERROR_F15_LEN) - 1) << USB_VDMA_ERROR_F15_POS) -#define USB_VDMA_ERROR_F15_UMSK (~(((1U << USB_VDMA_ERROR_F15_LEN) - 1) << USB_VDMA_ERROR_F15_POS)) - -/* 0x33C : DEV_MISG4 */ -#define USB_DEV_MISG4_OFFSET (0x33C) -#define USB_ML1_INT USB_ML1_INT -#define USB_ML1_INT_POS (0U) -#define USB_ML1_INT_LEN (1U) -#define USB_ML1_INT_MSK (((1U << USB_ML1_INT_LEN) - 1) << USB_ML1_INT_POS) -#define USB_ML1_INT_UMSK (~(((1U << USB_ML1_INT_LEN) - 1) << USB_ML1_INT_POS)) -#define USB_MVDMA_CMPLT_F15 USB_MVDMA_CMPLT_F15 -#define USB_MVDMA_CMPLT_F15_POS (16U) -#define USB_MVDMA_CMPLT_F15_LEN (1U) -#define USB_MVDMA_CMPLT_F15_MSK (((1U << USB_MVDMA_CMPLT_F15_LEN) - 1) << USB_MVDMA_CMPLT_F15_POS) -#define USB_MVDMA_CMPLT_F15_UMSK (~(((1U << USB_MVDMA_CMPLT_F15_LEN) - 1) << USB_MVDMA_CMPLT_F15_POS)) -#define USB_MVDMA_ERROR_F15 USB_MVDMA_ERROR_F15 -#define USB_MVDMA_ERROR_F15_POS (24U) -#define USB_MVDMA_ERROR_F15_LEN (1U) -#define USB_MVDMA_ERROR_F15_MSK (((1U << USB_MVDMA_ERROR_F15_LEN) - 1) << USB_MVDMA_ERROR_F15_POS) -#define USB_MVDMA_ERROR_F15_UMSK (~(((1U << USB_MVDMA_ERROR_F15_LEN) - 1) << USB_MVDMA_ERROR_F15_POS)) - -/* 0x350 : VDMA_FnPS1 */ -#define USB_VDMA_FNPS1_OFFSET (0x350) -#define USB_VDMA_START_FN USB_VDMA_START_FN -#define USB_VDMA_START_FN_POS (0U) -#define USB_VDMA_START_FN_LEN (1U) -#define USB_VDMA_START_FN_MSK (((1U << USB_VDMA_START_FN_LEN) - 1) << USB_VDMA_START_FN_POS) -#define USB_VDMA_START_FN_UMSK (~(((1U << USB_VDMA_START_FN_LEN) - 1) << USB_VDMA_START_FN_POS)) -#define USB_VDMA_TYPE_FN USB_VDMA_TYPE_FN -#define USB_VDMA_TYPE_FN_POS (1U) -#define USB_VDMA_TYPE_FN_LEN (1U) -#define USB_VDMA_TYPE_FN_MSK (((1U << USB_VDMA_TYPE_FN_LEN) - 1) << USB_VDMA_TYPE_FN_POS) -#define USB_VDMA_TYPE_FN_UMSK (~(((1U << USB_VDMA_TYPE_FN_LEN) - 1) << USB_VDMA_TYPE_FN_POS)) -#define USB_VDMA_IO_FN USB_VDMA_IO_FN -#define USB_VDMA_IO_FN_POS (2U) -#define USB_VDMA_IO_FN_LEN (1U) -#define USB_VDMA_IO_FN_MSK (((1U << USB_VDMA_IO_FN_LEN) - 1) << USB_VDMA_IO_FN_POS) -#define USB_VDMA_IO_FN_UMSK (~(((1U << USB_VDMA_IO_FN_LEN) - 1) << USB_VDMA_IO_FN_POS)) -#define USB_VDMA_LEN_FN USB_VDMA_LEN_FN -#define USB_VDMA_LEN_FN_POS (8U) -#define USB_VDMA_LEN_FN_LEN (17U) -#define USB_VDMA_LEN_FN_MSK (((1U << USB_VDMA_LEN_FN_LEN) - 1) << USB_VDMA_LEN_FN_POS) -#define USB_VDMA_LEN_FN_UMSK (~(((1U << USB_VDMA_LEN_FN_LEN) - 1) << USB_VDMA_LEN_FN_POS)) - -/* 0x354 : VDMA_FnPS2 */ -#define USB_VDMA_FNPS2_OFFSET (0x354) -#define USB_VDMA_MADDR_FN USB_VDMA_MADDR_FN -#define USB_VDMA_MADDR_FN_POS (0U) -#define USB_VDMA_MADDR_FN_LEN (32U) -#define USB_VDMA_MADDR_FN_MSK (((1U << USB_VDMA_MADDR_FN_LEN) - 1) << USB_VDMA_MADDR_FN_POS) -#define USB_VDMA_MADDR_FN_UMSK (~(((1U << USB_VDMA_MADDR_FN_LEN) - 1) << USB_VDMA_MADDR_FN_POS)) - -struct usb_reg { - /* 0x000 : HCCAP */ - union { - struct - { - uint32_t CAPLENGTH : 8; /* [ 7: 0], None, 0x0 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t HCIVERSION : 16; /* [31:16], None, 0x0 */ - } BF; - uint32_t WORD; - } HCCAP; - - /* 0x004 : HCSPARAMS */ - union { - struct - { - uint32_t N_PORTS : 4; /* [ 3: 0], None, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HCSPARAMS; - - /* 0x008 : HCCPARAMS */ - union { - struct - { - uint32_t reserved_0 : 1; /* [ 0], rsvd, 0x0 */ - uint32_t PROG_FR_LIST_FLAG : 1; /* [ 1], None, 0x0 */ - uint32_t ASYN_SCH_PARK_CAP : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HCCPARAMS; - - /* 0xc reserved */ - uint8_t RESERVED0xc[4]; - - /* 0x010 : USBCMD */ - union { - struct - { - uint32_t RS : 1; /* [ 0], None, 0x0 */ - uint32_t HC_RESET : 1; /* [ 1], None, 0x0 */ - uint32_t FRL_SIZE : 2; /* [ 3: 2], None, 0x0 */ - uint32_t PSCH_EN : 1; /* [ 4], None, 0x0 */ - uint32_t ASCH_EN : 1; /* [ 5], None, 0x0 */ - uint32_t INT_OAAD : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t ASYN_PK_CNT : 2; /* [ 9: 8], None, 0x0 */ - uint32_t reserved_10 : 1; /* [ 10], rsvd, 0x0 */ - uint32_t ASYN_PK_EN : 1; /* [ 11], None, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t INT_THRC : 8; /* [23:16], None, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } USBCMD; - - /* 0x014 : USBSTS */ - union { - struct - { - uint32_t USB_INT : 1; /* [ 0], None, 0x0 */ - uint32_t USBERR_INT : 1; /* [ 1], None, 0x0 */ - uint32_t PO_CHG_DET : 1; /* [ 2], None, 0x0 */ - uint32_t FRL_ROL : 1; /* [ 3], None, 0x0 */ - uint32_t H_SYSERR : 1; /* [ 4], None, 0x0 */ - uint32_t INT_OAA : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_11 : 6; /* [11: 6], rsvd, 0x0 */ - uint32_t HCHalted : 1; /* [ 12], None, 0x0 */ - uint32_t Reclamation : 1; /* [ 13], None, 0x0 */ - uint32_t PSCH_STS : 1; /* [ 14], None, 0x0 */ - uint32_t ASCH_STS : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } USBSTS; - - /* 0x018 : USBINTR */ - union { - struct - { - uint32_t USB_INT_EN : 1; /* [ 0], None, 0x0 */ - uint32_t USBERR_INT_EN : 1; /* [ 1], None, 0x0 */ - uint32_t PO_CHG_INT_EN : 1; /* [ 2], None, 0x0 */ - uint32_t FRL_ROL_EN : 1; /* [ 3], None, 0x0 */ - uint32_t H_SYSERR_EN : 1; /* [ 4], None, 0x0 */ - uint32_t INT_OAA_EN : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } USBINTR; - - /* 0x01C : FRINDEX */ - union { - struct - { - uint32_t FRINDEX : 14; /* [13: 0], None, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } FRINDEX; - - /* 0x20 reserved */ - uint8_t RESERVED0x20[4]; - - /* 0x024 : PERIODICLISTBASE */ - union { - struct - { - uint32_t reserved_0_11 : 12; /* [11: 0], rsvd, 0x0 */ - uint32_t PERI_BASADR : 20; /* [31:12], None, 0x0 */ - } BF; - uint32_t WORD; - } PERIODICLISTBASE; - - /* 0x028 : ASYNCLISTADDR */ - union { - struct - { - uint32_t reserved_0_4 : 5; /* [ 4: 0], rsvd, 0x0 */ - uint32_t Async_ladr : 27; /* [31: 5], None, 0x0 */ - } BF; - uint32_t WORD; - } ASYNCLISTADDR; - - /* 0x2c reserved */ - uint8_t RESERVED0x2c[4]; - - /* 0x030 : PORTSC */ - union { - struct - { - uint32_t CONN_STS : 1; /* [ 0], None, 0x0 */ - uint32_t CONN_CHG : 1; /* [ 1], None, 0x0 */ - uint32_t PO_EN : 1; /* [ 2], None, 0x0 */ - uint32_t PO_EN_CHG : 1; /* [ 3], None, 0x0 */ - uint32_t reserved_4_5 : 2; /* [ 5: 4], rsvd, 0x0 */ - uint32_t F_PO_RESM : 1; /* [ 6], None, 0x0 */ - uint32_t PO_SUSP : 1; /* [ 7], None, 0x0 */ - uint32_t PO_RESET : 1; /* [ 8], None, 0x0 */ - uint32_t reserved_9 : 1; /* [ 9], rsvd, 0x0 */ - uint32_t LINE_STS : 2; /* [11:10], None, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t PORT_TEST : 4; /* [19:16], None, 0x0 */ - uint32_t HC_TST_PKDONE : 1; /* [ 20], None, 0x0 */ - uint32_t reserved_21_31 : 11; /* [31:21], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } PORTSC; - - /* 0x34 reserved */ - uint8_t RESERVED0x34[12]; - - /* 0x040 : HCMISC */ - union { - struct - { - uint32_t ASYN_SCH_SLPT : 2; /* [ 1: 0], None, 0x0 */ - uint32_t EOF1_Time : 2; /* [ 3: 2], None, 0x0 */ - uint32_t EOF2_Time : 2; /* [ 5: 4], None, 0x0 */ - uint32_t HostPhy_Suspend : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t HC_WKP_DET_EN : 1; /* [ 8], None, 0x0 */ - uint32_t HC_CONN_DET_EN : 1; /* [ 9], None, 0x0 */ - uint32_t reserved_10_31 : 22; /* [31:10], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HCMISC; - - /* 0x044 : FS_EOF */ - union { - struct - { - uint32_t FS_EOF1_Time : 12; /* [11: 0], None, 0x0 */ - uint32_t FS_EOF1_Time_125us : 3; /* [14:12], None, 0x0 */ - uint32_t reserved_15 : 1; /* [ 15], rsvd, 0x0 */ - uint32_t iTDdmaSM : 4; /* [19:16], None, 0x0 */ - uint32_t iTDTravSM : 2; /* [21:20], None, 0x0 */ - uint32_t DMAdmSM : 4; /* [25:22], None, 0x0 */ - uint32_t QHTtrSM : 3; /* [28:26], None, 0x0 */ - uint32_t QHTravSM : 3; /* [31:29], None, 0x0 */ - } BF; - uint32_t WORD; - } FS_EOF; - - /* 0x048 : HS_EOF */ - union { - struct - { - uint32_t HS_EOF1_Time : 12; /* [11: 0], None, 0x0 */ - uint32_t reserved_12_15 : 4; /* [15:12], rsvd, 0x0 */ - uint32_t siTDdmaSM : 4; /* [19:16], None, 0x0 */ - uint32_t siTDTravSM : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_31 : 10; /* [31:22], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } HS_EOF; - - /* 0x4c reserved */ - uint8_t RESERVED0x4c[52]; - - /* 0x080 : OTG_CSR */ - union { - struct - { - uint32_t B_BUS_REQ : 1; /* [ 0], None, 0x0 */ - uint32_t B_HNP_EN : 1; /* [ 1], None, 0x0 */ - uint32_t B_DSCHRG_VBUS : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t A_BUS_REQ_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t A_BUS_DROP_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t A_SET_B_HNP_EN : 1; /* [ 6], None, 0x0 */ - uint32_t A_SRP_DET_EN : 1; /* [ 7], None, 0x0 */ - uint32_t A_SRP_RESP_TYP : 1; /* [ 8], None, 0x0 */ - uint32_t ID_FLT_SEL : 1; /* [ 9], None, 0x0 */ - uint32_t VBUS_FLT_SEL_HOV_POV : 1; /* [ 10], None, 0x0 */ - uint32_t HDISCON_FLT_SEL_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t reserved_12 : 1; /* [ 12], rsvd, 0x0 */ - uint32_t IDPULUP_HOV_POV : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t B_SESS_END_POV : 1; /* [ 16], None, 0x0 */ - uint32_t B_SESS_VLD_POV : 1; /* [ 17], None, 0x0 */ - uint32_t A_SESS_VLD : 1; /* [ 18], None, 0x0 */ - uint32_t VBUS_VLD_HOV : 1; /* [ 19], None, 0x0 */ - uint32_t CROLE_HOV_POV : 1; /* [ 20], None, 0x0 */ - uint32_t ID_HOV_POV : 1; /* [ 21], None, 0x0 */ - uint32_t SPD_TYP_HOV_POV : 2; /* [23:22], None, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } OTG_CSR; - - /* 0x084 : OTG_ISR */ - union { - struct - { - uint32_t B_SRP_DN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t A_SRP_DET : 1; /* [ 4], None, 0x0 */ - uint32_t A_VBUS_ERR_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t B_SESS_END_POV : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t RLCHG : 1; /* [ 8], None, 0x0 */ - uint32_t IDCHG : 1; /* [ 9], None, 0x0 */ - uint32_t OVC_HOV : 1; /* [ 10], None, 0x0 */ - uint32_t A_WAIT_CON_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t APLGRMV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } OTG_ISR; - - /* 0x088 : OTG_IER */ - union { - struct - { - uint32_t B_SRP_DN_EN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_3 : 3; /* [ 3: 1], rsvd, 0x0 */ - uint32_t A_SRP_DET_EN : 1; /* [ 4], None, 0x0 */ - uint32_t A_VBUS_ERR_EN_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t B_SESS_END_EN_POV : 1; /* [ 6], None, 0x0 */ - uint32_t reserved_7 : 1; /* [ 7], rsvd, 0x0 */ - uint32_t RLCHG_EN : 1; /* [ 8], None, 0x0 */ - uint32_t IDCHG_EN : 1; /* [ 9], None, 0x0 */ - uint32_t OVC_EN_HOV : 1; /* [ 10], None, 0x0 */ - uint32_t A_WAIT_CON_EN_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t APLGRMV_EN : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } OTG_IER; - - /* 0x8c reserved */ - uint8_t RESERVED0x8c[52]; - - /* 0x0C0 : GLB_ISR */ - union { - struct - { - uint32_t DEV_INT : 1; /* [ 0], None, 0x0 */ - uint32_t OTG_INT : 1; /* [ 1], None, 0x0 */ - uint32_t HC_INT : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } GLB_ISR; - - /* 0x0C4 : GLB_INT */ - union { - struct - { - uint32_t MDEV_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MOTG_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MHC_INT : 1; /* [ 2], None, 0x0 */ - uint32_t INT_POLARITY : 1; /* [ 3], None, 0x0 */ - uint32_t reserved_4_31 : 28; /* [31: 4], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } GLB_INT; - - /* 0xc8 reserved */ - uint8_t RESERVED0xc8[24]; - - /* 0x0E0 : REVISION */ - union { - struct - { - uint32_t REVISION : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } REVISION; - - /* 0x0E4 : FEATURE */ - union { - struct - { - uint32_t DMABUFSIZE : 5; /* [ 4: 0], None, 0x0 */ - uint32_t FIFO_NUM : 5; /* [ 9: 5], None, 0x0 */ - uint32_t EP_NUM : 5; /* [14:10], None, 0x0 */ - uint32_t DEV_ONLY : 1; /* [ 15], None, 0x0 */ - uint32_t HOST_ONLY : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } FEATURE; - - /* 0x0E8 : AXI_CR */ - union { - struct - { - uint32_t AXI_SGLBST : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } AXI_CR; - - /* 0xec reserved */ - uint8_t RESERVED0xec[20]; - - /* 0x100 : DEV_CTL */ - union { - struct - { - uint32_t CAP_RMWAKUP : 1; /* [ 0], None, 0x0 */ - uint32_t HALF_SPEED_HOV : 1; /* [ 1], None, 0x0 */ - uint32_t GLINT_EN_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t GOSUSP : 1; /* [ 3], None, 0x0 */ - uint32_t SFRST_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t CHIP_EN_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t HS_EN_HOV : 1; /* [ 6], None, 0x0 */ - uint32_t SYSBUS_WIDTH_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8 : 1; /* [ 8], rsvd, 0x0 */ - uint32_t FORCE_FS : 1; /* [ 9], None, 0x0 */ - uint32_t IDLE_DEGLITCH_HOV : 2; /* [11:10], None, 0x0 */ - uint32_t LPM_BESL_MAX : 4; /* [15:12], None, 0x0 */ - uint32_t LPM_BESL_MIN : 4; /* [19:16], None, 0x0 */ - uint32_t LPM_BESL : 4; /* [23:20], None, 0x0 */ - uint32_t reserved_24 : 1; /* [ 24], rsvd, 0x0 */ - uint32_t LPM_EN : 1; /* [ 25], None, 0x0 */ - uint32_t LPM_ACCEPT : 1; /* [ 26], None, 0x0 */ - uint32_t reserved_27_31 : 5; /* [31:27], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_CTL; - - /* 0x104 : DEV_ADR */ - union { - struct - { - uint32_t DEVADR : 7; /* [ 6: 0], None, 0x0 */ - uint32_t AFT_CONF : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ADR; - - /* 0x108 : DEV_TST */ - union { - struct - { - uint32_t TST_CLRFF_HOV : 1; /* [ 0], None, 0x0 */ - uint32_t TST_LPCX : 1; /* [ 1], None, 0x0 */ - uint32_t TST_CLREA : 1; /* [ 2], None, 0x0 */ - uint32_t rsvd_3 : 1; /* [ 3], None, 0x0 */ - uint32_t TST_DISTO_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t TST_MOD_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t DISGENSOF : 1; /* [ 6], None, 0x0 */ - uint32_t TST_MOD_TYP_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_TST; - - /* 0x10C : DEV_SFN */ - union { - struct - { - uint32_t SOFN : 11; /* [10: 0], None, 0x0 */ - uint32_t USOFN : 3; /* [13:11], None, 0x0 */ - uint32_t reserved_14_31 : 18; /* [31:14], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_SFN; - - /* 0x110 : DEV_SMT */ - union { - struct - { - uint32_t SOFMT : 16; /* [15: 0], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_SMT; - - /* 0x114 : PHY_TST */ - union { - struct - { - uint32_t UNPLUG : 1; /* [ 0], None, 0x0 */ - uint32_t TST_JSTA : 1; /* [ 1], None, 0x0 */ - uint32_t TST_KSTA : 1; /* [ 2], None, 0x0 */ - uint32_t TST_SE0NAK : 1; /* [ 3], None, 0x0 */ - uint32_t TST_PKT : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } PHY_TST; - - /* 0x118 : DEV_VCTL */ - union { - struct - { - uint32_t VCTL_HOV : 5; /* [ 4: 0], None, 0x0 */ - uint32_t VCTLOAD_N_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_VCTL; - - /* 0x11C : DEV_CXCFG */ - union { - struct - { - uint32_t VSTA_HOV : 8; /* [ 7: 0], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_CXCFG; - - /* 0x120 : DEV_CXCFE */ - union { - struct - { - uint32_t CX_DONE : 1; /* [ 0], None, 0x0 */ - uint32_t TST_PKDONE : 1; /* [ 1], None, 0x0 */ - uint32_t CX_STL : 1; /* [ 2], None, 0x0 */ - uint32_t CX_CLR : 1; /* [ 3], None, 0x0 */ - uint32_t CX_FUL : 1; /* [ 4], None, 0x0 */ - uint32_t CX_EMP : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t F0_EMP : 1; /* [ 8], None, 0x0 */ - uint32_t F1_EMP : 1; /* [ 9], None, 0x0 */ - uint32_t F2_EMP : 1; /* [ 10], None, 0x0 */ - uint32_t F3_EMP : 1; /* [ 11], None, 0x0 */ - uint32_t F4_EMP : 1; /* [ 12], None, 0x0 */ - uint32_t F5_EMP : 1; /* [ 13], None, 0x0 */ - uint32_t F6_EMP : 1; /* [ 14], None, 0x0 */ - uint32_t F7_EMP : 1; /* [ 15], None, 0x0 */ - uint32_t F8_EMP : 1; /* [ 16], None, 0x0 */ - uint32_t F9_EMP : 1; /* [ 17], None, 0x0 */ - uint32_t F10_EMP : 1; /* [ 18], None, 0x0 */ - uint32_t F11_EMP : 1; /* [ 19], None, 0x0 */ - uint32_t F12_EMP : 1; /* [ 20], None, 0x0 */ - uint32_t F13_EMP : 1; /* [ 21], None, 0x0 */ - uint32_t F14_EMP : 1; /* [ 22], None, 0x0 */ - uint32_t F15_EMP : 1; /* [ 23], None, 0x0 */ - uint32_t CX_FNT : 7; /* [30:24], None, 0x0 */ - uint32_t reserved_31 : 1; /* [ 31], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_CXCFE; - - /* 0x124 : DEV_ICR */ - union { - struct - { - uint32_t IDLE_CNT : 3; /* [ 2: 0], None, 0x0 */ - uint32_t reserved_3_31 : 29; /* [31: 3], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ICR; - - /* 0x128 reserved */ - uint8_t RESERVED0x128[8]; - - /* 0x130 : DEV_MIGR */ - union { - struct - { - uint32_t MINT_G0 : 1; /* [ 0], None, 0x0 */ - uint32_t MINT_G1 : 1; /* [ 1], None, 0x0 */ - uint32_t MINT_G2 : 1; /* [ 2], None, 0x0 */ - uint32_t MINT_G3 : 1; /* [ 3], None, 0x0 */ - uint32_t MINT_G4 : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MIGR; - - /* 0x134 : DEV_MISG0 */ - union { - struct - { - uint32_t MCX_SETUP_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MCX_IN_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MCX_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t MCX_COMFAIL_INT : 1; /* [ 4], None, 0x0 */ - uint32_t MCX_COMABORT_INT : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG0; - - /* 0x138 : DEV_MISG1 */ - union { - struct - { - uint32_t MF0_OUT_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MF0_SPK_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MF1_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t MF1_SPK_INT : 1; /* [ 3], None, 0x0 */ - uint32_t MF2_OUT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t MF2_SPK_INT : 1; /* [ 5], None, 0x0 */ - uint32_t MF3_OUT_INT : 1; /* [ 6], None, 0x0 */ - uint32_t MF3_SPK_INT : 1; /* [ 7], None, 0x0 */ - uint32_t MF4_OUT_INT : 1; /* [ 8], None, 0x0 */ - uint32_t MF4_SPK_INT : 1; /* [ 9], None, 0x0 */ - uint32_t MF5_OUT_INT : 1; /* [ 10], None, 0x0 */ - uint32_t MF5_SPK_INT : 1; /* [ 11], None, 0x0 */ - uint32_t MF6_OUT_INT : 1; /* [ 12], None, 0x0 */ - uint32_t MF6_SPK_INT : 1; /* [ 13], None, 0x0 */ - uint32_t MF7_OUT_INT : 1; /* [ 14], None, 0x0 */ - uint32_t MF7_SPK_INT : 1; /* [ 15], None, 0x0 */ - uint32_t MF0_IN_INT : 1; /* [ 16], None, 0x0 */ - uint32_t MF1_IN_INT : 1; /* [ 17], None, 0x0 */ - uint32_t MF2_IN_INT : 1; /* [ 18], None, 0x0 */ - uint32_t MF3_IN_INT : 1; /* [ 19], None, 0x0 */ - uint32_t MF4_IN_INT : 1; /* [ 20], None, 0x0 */ - uint32_t MF5_IN_INT : 1; /* [ 21], None, 0x0 */ - uint32_t MF6_IN_INT : 1; /* [ 22], None, 0x0 */ - uint32_t MF7_IN_INT : 1; /* [ 23], None, 0x0 */ - uint32_t MF8_IN_INT : 1; /* [ 24], None, 0x0 */ - uint32_t MF9_IN_INT : 1; /* [ 25], None, 0x0 */ - uint32_t MF10_IN_INT : 1; /* [ 26], None, 0x0 */ - uint32_t MF11_IN_INT : 1; /* [ 27], None, 0x0 */ - uint32_t MF12_IN_INT : 1; /* [ 28], None, 0x0 */ - uint32_t MF13_IN_INT : 1; /* [ 29], None, 0x0 */ - uint32_t MF14_IN_INT : 1; /* [ 30], None, 0x0 */ - uint32_t MF15_IN_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG1; - - /* 0x13C : DEV_MISG2 */ - union { - struct - { - uint32_t MUSBRST_INT : 1; /* [ 0], None, 0x0 */ - uint32_t MSUSP_INT : 1; /* [ 1], None, 0x0 */ - uint32_t MRESM_INT : 1; /* [ 2], None, 0x0 */ - uint32_t MSEQ_ERR_INT : 1; /* [ 3], None, 0x0 */ - uint32_t MSEQ_ABORT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t MTX0BYTE_INT : 1; /* [ 5], None, 0x0 */ - uint32_t MRX0BYTE_INT : 1; /* [ 6], None, 0x0 */ - uint32_t MDMA_CMPLT_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t MDMA_ERROR_HOV : 1; /* [ 8], None, 0x0 */ - uint32_t MDev_Idle_HOV : 1; /* [ 9], None, 0x0 */ - uint32_t MDev_Wakeup_byVBUS : 1; /* [ 10], None, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t MF8_OUT_INT : 1; /* [ 16], None, 0x0 */ - uint32_t MF8_SPK_INT : 1; /* [ 17], None, 0x0 */ - uint32_t MF9_OUT_INT : 1; /* [ 18], None, 0x0 */ - uint32_t MF9_SPK_INT : 1; /* [ 19], None, 0x0 */ - uint32_t MF10_OUT_INT : 1; /* [ 20], None, 0x0 */ - uint32_t MF10_SPK_INT : 1; /* [ 21], None, 0x0 */ - uint32_t MF11_OUT_INT : 1; /* [ 22], None, 0x0 */ - uint32_t MF11_SPK_INT : 1; /* [ 23], None, 0x0 */ - uint32_t MF12_OUT_INT : 1; /* [ 24], None, 0x0 */ - uint32_t MF12_SPK_INT : 1; /* [ 25], None, 0x0 */ - uint32_t MF13_OUT_INT : 1; /* [ 26], None, 0x0 */ - uint32_t MF13_SPK_INT : 1; /* [ 27], None, 0x0 */ - uint32_t MF14_OUT_INT : 1; /* [ 28], None, 0x0 */ - uint32_t MF14_SPK_INT : 1; /* [ 29], None, 0x0 */ - uint32_t MF15_OUT_INT : 1; /* [ 30], None, 0x0 */ - uint32_t MF15_SPK_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG2; - - /* 0x140 : DEV_IGR */ - union { - struct - { - uint32_t INT_G0 : 1; /* [ 0], None, 0x0 */ - uint32_t INT_G1 : 1; /* [ 1], None, 0x0 */ - uint32_t INT_G2_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t INT_G3 : 1; /* [ 3], None, 0x0 */ - uint32_t INT_G4 : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_31 : 27; /* [31: 5], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_IGR; - - /* 0x144 : DEV_ISG0 */ - union { - struct - { - uint32_t CX_SETUP_INT : 1; /* [ 0], None, 0x0 */ - uint32_t CX_IN_INT : 1; /* [ 1], None, 0x0 */ - uint32_t CX_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3 : 1; /* [ 3], rsvd, 0x0 */ - uint32_t CX_COMFAIL_INT : 1; /* [ 4], None, 0x0 */ - uint32_t CX_COMABT_INT : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_31 : 26; /* [31: 6], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG0; - - /* 0x148 : DEV_ISG1 */ - union { - struct - { - uint32_t F0_OUT_INT : 1; /* [ 0], None, 0x0 */ - uint32_t F0_SPK_INT : 1; /* [ 1], None, 0x0 */ - uint32_t F1_OUT_INT : 1; /* [ 2], None, 0x0 */ - uint32_t F1_SPK_INT : 1; /* [ 3], None, 0x0 */ - uint32_t F2_OUT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t F2_SPK_INT : 1; /* [ 5], None, 0x0 */ - uint32_t F3_OUT_INT : 1; /* [ 6], None, 0x0 */ - uint32_t F3_SPK_INT : 1; /* [ 7], None, 0x0 */ - uint32_t F4_OUT_INT : 1; /* [ 8], None, 0x0 */ - uint32_t F4_SPK_INT : 1; /* [ 9], None, 0x0 */ - uint32_t F5_OUT_INT : 1; /* [ 10], None, 0x0 */ - uint32_t F5_SPK_INT : 1; /* [ 11], None, 0x0 */ - uint32_t F6_OUT_INT : 1; /* [ 12], None, 0x0 */ - uint32_t F6_SPK_INT : 1; /* [ 13], None, 0x0 */ - uint32_t F7_OUT_INT : 1; /* [ 14], None, 0x0 */ - uint32_t F7_SPK_INT : 1; /* [ 15], None, 0x0 */ - uint32_t F0_IN_INT : 1; /* [ 16], None, 0x0 */ - uint32_t F1_IN_INT : 1; /* [ 17], None, 0x0 */ - uint32_t F2_IN_INT : 1; /* [ 18], None, 0x0 */ - uint32_t F3_IN_INT : 1; /* [ 19], None, 0x0 */ - uint32_t F4_IN_INT : 1; /* [ 20], None, 0x0 */ - uint32_t F5_IN_INT : 1; /* [ 21], None, 0x0 */ - uint32_t F6_IN_INT : 1; /* [ 22], None, 0x0 */ - uint32_t F7_IN_INT : 1; /* [ 23], None, 0x0 */ - uint32_t F8_IN_INT : 1; /* [ 24], None, 0x0 */ - uint32_t F9_IN_INT : 1; /* [ 25], None, 0x0 */ - uint32_t F10_IN_INT : 1; /* [ 26], None, 0x0 */ - uint32_t F11_IN_INT : 1; /* [ 27], None, 0x0 */ - uint32_t F12_IN_INT : 1; /* [ 28], None, 0x0 */ - uint32_t F13_IN_INT : 1; /* [ 29], None, 0x0 */ - uint32_t F14_IN_INT : 1; /* [ 30], None, 0x0 */ - uint32_t F15_IN_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG1; - - /* 0x14C : DEV_ISG2 */ - union { - struct - { - uint32_t USBRST_INT : 1; /* [ 0], None, 0x0 */ - uint32_t SUSP_INT : 1; /* [ 1], None, 0x0 */ - uint32_t RESM_INT : 1; /* [ 2], None, 0x0 */ - uint32_t ISO_SEQ_ERR_INT : 1; /* [ 3], None, 0x0 */ - uint32_t ISO_SEQ_ABORT_INT : 1; /* [ 4], None, 0x0 */ - uint32_t TX0BYTE_INT : 1; /* [ 5], None, 0x0 */ - uint32_t RX0BYTE_INT : 1; /* [ 6], None, 0x0 */ - uint32_t DMA_CMPLT_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t DMA_ERROR_HOV : 1; /* [ 8], None, 0x0 */ - uint32_t Dev_Idle_HOV : 1; /* [ 9], None, 0x0 */ - uint32_t Dev_Wakeup_byVBUS : 1; /* [ 10], None, 0x0 */ - uint32_t reserved_11_15 : 5; /* [15:11], rsvd, 0x0 */ - uint32_t F8_OUT_INT : 1; /* [ 16], None, 0x0 */ - uint32_t F8_SPK_INT : 1; /* [ 17], None, 0x0 */ - uint32_t F9_OUT_INT : 1; /* [ 18], None, 0x0 */ - uint32_t F9_SPK_INT : 1; /* [ 19], None, 0x0 */ - uint32_t F10_OUT_INT : 1; /* [ 20], None, 0x0 */ - uint32_t F10_SPK_INT : 1; /* [ 21], None, 0x0 */ - uint32_t F11_OUT_INT : 1; /* [ 22], None, 0x0 */ - uint32_t F11_SPK_INT : 1; /* [ 23], None, 0x0 */ - uint32_t F12_OUT_INT : 1; /* [ 24], None, 0x0 */ - uint32_t F12_SPK_INT : 1; /* [ 25], None, 0x0 */ - uint32_t F13_OUT_INT : 1; /* [ 26], None, 0x0 */ - uint32_t F13_SPK_INT : 1; /* [ 27], None, 0x0 */ - uint32_t F14_OUT_INT : 1; /* [ 28], None, 0x0 */ - uint32_t F14_SPK_INT : 1; /* [ 29], None, 0x0 */ - uint32_t F15_OUT_INT : 1; /* [ 30], None, 0x0 */ - uint32_t F15_SPK_INT : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG2; - - /* 0x150 : DEV_RXZ */ - union { - struct - { - uint32_t RX0BYTE_EP1 : 1; /* [ 0], None, 0x0 */ - uint32_t RX0BYTE_EP2 : 1; /* [ 1], None, 0x0 */ - uint32_t RX0BYTE_EP3 : 1; /* [ 2], None, 0x0 */ - uint32_t RX0BYTE_EP4 : 1; /* [ 3], None, 0x0 */ - uint32_t RX0BYTE_EP5 : 1; /* [ 4], None, 0x0 */ - uint32_t RX0BYTE_EP6 : 1; /* [ 5], None, 0x0 */ - uint32_t RX0BYTE_EP7 : 1; /* [ 6], None, 0x0 */ - uint32_t RX0BYTE_EP8 : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_RXZ; - - /* 0x154 : DEV_TXZ */ - union { - struct - { - uint32_t TX0BYTE_EP1 : 1; /* [ 0], None, 0x0 */ - uint32_t TX0BYTE_EP2 : 1; /* [ 1], None, 0x0 */ - uint32_t TX0BYTE_EP3 : 1; /* [ 2], None, 0x0 */ - uint32_t TX0BYTE_EP4 : 1; /* [ 3], None, 0x0 */ - uint32_t TX0BYTE_EP5 : 1; /* [ 4], None, 0x0 */ - uint32_t TX0BYTE_EP6 : 1; /* [ 5], None, 0x0 */ - uint32_t TX0BYTE_EP7 : 1; /* [ 6], None, 0x0 */ - uint32_t TX0BYTE_EP8 : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_31 : 24; /* [31: 8], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_TXZ; - - /* 0x158 : DEV_ISE */ - union { - struct - { - uint32_t ISO_ABT_ERR_EP1 : 1; /* [ 0], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP2 : 1; /* [ 1], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP3 : 1; /* [ 2], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP4 : 1; /* [ 3], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP5 : 1; /* [ 4], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP6 : 1; /* [ 5], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP7 : 1; /* [ 6], None, 0x0 */ - uint32_t ISO_ABT_ERR_EP8 : 1; /* [ 7], None, 0x0 */ - uint32_t reserved_8_15 : 8; /* [15: 8], rsvd, 0x0 */ - uint32_t ISO_SEQ_ERR_EP1 : 1; /* [ 16], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP2 : 1; /* [ 17], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP3 : 1; /* [ 18], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP4 : 1; /* [ 19], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP5 : 1; /* [ 20], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP6 : 1; /* [ 21], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP7 : 1; /* [ 22], None, 0x0 */ - uint32_t ISO_SEQ_ERR_EP8 : 1; /* [ 23], None, 0x0 */ - uint32_t reserved_24_31 : 8; /* [31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISE; - - /* 0x15c reserved */ - uint8_t RESERVED0x15c[4]; - - /* 0x160 : DEV_INMPS1 */ - union { - struct - { - uint32_t MAXPS_IEP1 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP1 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP1 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP1 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP1 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS1; - - /* 0x164 : DEV_INMPS2 */ - union { - struct - { - uint32_t MAXPS_IEP2 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP2 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP2 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP2 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP2 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS2; - - /* 0x168 : DEV_INMPS3 */ - union { - struct - { - uint32_t MAXPS_IEP3 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP3 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP3 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP3 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP3 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS3; - - /* 0x16C : DEV_INMPS4 */ - union { - struct - { - uint32_t MAXPS_IEP4 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP4 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP4 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP4 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP4 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS4; - - /* 0x170 : DEV_INMPS5 */ - union { - struct - { - uint32_t MAXPS_IEP5 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP5 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP5 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP5 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP5 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS5; - - /* 0x174 : DEV_INMPS6 */ - union { - struct - { - uint32_t MAXPS_IEP6 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP6 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP6 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP6 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP6 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS6; - - /* 0x178 : DEV_INMPS7 */ - union { - struct - { - uint32_t MAXPS_IEP7 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP7 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP7 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP7 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP7 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS7; - - /* 0x17C : DEV_INMPS8 */ - union { - struct - { - uint32_t MAXPS_IEP8 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_IEP8 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_IEP8 : 1; /* [ 12], None, 0x0 */ - uint32_t TX_NUM_HBW_IEP8 : 2; /* [14:13], None, 0x0 */ - uint32_t TX0BYTE_IEP8 : 1; /* [ 15], None, 0x0 */ - uint32_t reserved_16_31 : 16; /* [31:16], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_INMPS8; - - /* 0x180 : DEV_OUTMPS1 */ - union { - struct - { - uint32_t MAXPS_OEP1 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP1 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP1 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS1; - - /* 0x184 : DEV_OUTMPS2 */ - union { - struct - { - uint32_t MAXPS_OEP2 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP2 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP2 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS2; - - /* 0x188 : DEV_OUTMPS3 */ - union { - struct - { - uint32_t MAXPS_OEP3 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP3 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP3 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS3; - - /* 0x18C : DEV_OUTMPS4 */ - union { - struct - { - uint32_t MAXPS_OEP4 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP4 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP4 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS4; - - /* 0x190 : DEV_OUTMPS5 */ - union { - struct - { - uint32_t MAXPS_OEP5 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP5 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP5 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS5; - - /* 0x194 : DEV_OUTMPS6 */ - union { - struct - { - uint32_t MAXPS_OEP6 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP6 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP6 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS6; - - /* 0x198 : DEV_OUTMPS7 */ - union { - struct - { - uint32_t MAXPS_OEP7 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP7 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP7 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS7; - - /* 0x19C : DEV_OUTMPS8 */ - union { - struct - { - uint32_t MAXPS_OEP8 : 11; /* [10: 0], None, 0x0 */ - uint32_t STL_OEP8 : 1; /* [ 11], None, 0x0 */ - uint32_t RSTG_OEP8 : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_OUTMPS8; - - /* 0x1A0 : DEV_EPMAP08 */ - union { - struct - { - uint32_t FNO_IEP1 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t FNO_OEP1 : 4; /* [ 7: 4], None, 0x0 */ - uint32_t FNO_IEP2 : 4; /* [11: 8], None, 0x0 */ - uint32_t FNO_OEP2 : 4; /* [15:12], None, 0x0 */ - uint32_t FNO_IEP3 : 4; /* [19:16], None, 0x0 */ - uint32_t FNO_OEP3 : 4; /* [23:20], None, 0x0 */ - uint32_t FNO_IEP4 : 4; /* [27:24], None, 0x0 */ - uint32_t FNO_OEP4 : 4; /* [31:28], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_EPMAP08; - - /* 0x1A4 : DEV_EPMAP1 */ - union { - struct - { - uint32_t FNO_IEP5 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t FNO_OEP5 : 4; /* [ 7: 4], None, 0x0 */ - uint32_t FNO_IEP6 : 4; /* [11: 8], None, 0x0 */ - uint32_t FNO_OEP6 : 4; /* [15:12], None, 0x0 */ - uint32_t FNO_IEP7 : 4; /* [19:16], None, 0x0 */ - uint32_t FNO_OEP7 : 4; /* [23:20], None, 0x0 */ - uint32_t FNO_IEP8 : 4; /* [27:24], None, 0x0 */ - uint32_t FNO_OEP8 : 4; /* [31:28], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_EPMAP1; - - /* 0x1A8 : DEV_FMAP */ - union { - struct - { - uint32_t EPNO_FIFO0 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO0 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO1 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO1 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO2 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO2 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO3 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO3 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP; - - /* 0x1AC : DEV_FCFG */ - union { - struct - { - uint32_t BLK_TYP_F0 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F0 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F0 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F0 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F1 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F1 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F1 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F1 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F2 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F2 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F2 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F2 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F3 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F3 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F3 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F3 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG; - - /* 0x1B0 : DEV_FIBC0 */ - union { - struct - { - uint32_t BC_F0 : 11; /* [10: 0], None, 0x0 */ - uint32_t rsvdp : 1; /* [ 11], None, 0x0 */ - uint32_t FFRST0_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC0; - - /* 0x1B4 : DEV_FIBC1 */ - union { - struct - { - uint32_t BC_F1 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST1_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC1; - - /* 0x1B8 : DEV_FIBC2 */ - union { - struct - { - uint32_t BC_F2 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST2_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC2; - - /* 0x1BC : DEV_FIBC3 */ - union { - struct - { - uint32_t BC_F3 : 11; /* [10: 0], None, 0x0 */ - uint32_t rsvdp : 1; /* [ 11], None, 0x0 */ - uint32_t FFRST3_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t rsvd_31_13 : 19; /* [31:13], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC3; - - /* 0x1C0 : DMA_TFN */ - union { - struct - { - uint32_t ACC_F0_HOV : 1; /* [ 0], None, 0x0 */ - uint32_t ACC_F1_HOV : 1; /* [ 1], None, 0x0 */ - uint32_t ACC_F2_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t ACC_F3_HOV : 1; /* [ 3], None, 0x0 */ - uint32_t ACC_CXF_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t ACC_F4_HOV : 1; /* [ 5], None, 0x0 */ - uint32_t ACC_F5_HOV : 1; /* [ 6], None, 0x0 */ - uint32_t ACC_F6_HOV : 1; /* [ 7], None, 0x0 */ - uint32_t ACC_F7_HOV : 1; /* [ 8], None, 0x0 */ - uint32_t ACC_F8_HOV : 1; /* [ 9], None, 0x0 */ - uint32_t ACC_F9_HOV : 1; /* [ 10], None, 0x0 */ - uint32_t ACC_F10_HOV : 1; /* [ 11], None, 0x0 */ - uint32_t ACC_F11_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t ACC_F12_HOV : 1; /* [ 13], None, 0x0 */ - uint32_t ACC_F13_HOV : 1; /* [ 14], None, 0x0 */ - uint32_t ACC_F14_HOV : 1; /* [ 15], None, 0x0 */ - uint32_t ACC_F15_HOV : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_31 : 15; /* [31:17], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_TFN; - - /* 0x1C4 : DMA_CPS0 */ - union { - struct - { - uint32_t AWCHACHE_HOV : 4; /* [ 3: 0], None, 0x0 */ - uint32_t AWPORT_HOV : 3; /* [ 6: 4], None, 0x0 */ - uint32_t AWLOCK_HOV : 2; /* [ 8: 7], None, 0x0 */ - uint32_t ARCACHE_HOV : 4; /* [12: 9], None, 0x0 */ - uint32_t ARPORT_HOV : 3; /* [15:13], None, 0x0 */ - uint32_t ARLOCK_HOV : 2; /* [17:16], None, 0x0 */ - uint32_t BUF_LD_EN_HOV : 1; /* [ 18], None, 0x0 */ - uint32_t DST_WD_HOV : 1; /* [ 19], None, 0x0 */ - uint32_t reserved_20_31 : 12; /* [31:20], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS0; - - /* 0x1C8 : DMA_CPS1 */ - union { - struct - { - uint32_t DMA_START_HOV : 1; /* [ 0], None, 0x0 */ - uint32_t DMA_TYPE_HOV : 1; /* [ 1], None, 0x0 */ - uint32_t DMA_IO_HOV : 1; /* [ 2], None, 0x0 */ - uint32_t DMA_ABORT_HOV : 1; /* [ 3], None, 0x0 */ - uint32_t CLRFIFO_DMAABORT_HOV : 1; /* [ 4], None, 0x0 */ - uint32_t reserved_5_7 : 3; /* [ 7: 5], rsvd, 0x0 */ - uint32_t DMA_LEN_HOV : 17; /* [24: 8], None, 0x0 */ - uint32_t R_HPORT_HOV : 4; /* [28:25], None, 0x0 */ - uint32_t UNDEF_LEN_BURST_HOV : 1; /* [ 29], None, 0x0 */ - uint32_t L1_WAKEUP : 1; /* [ 30], None, 0x0 */ - uint32_t DevPhy_Suspend_HOV : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS1; - - /* 0x1CC : DMA_CPS2 */ - union { - struct - { - uint32_t DMA_MADDR_HOV : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS2; - - /* 0x1D0 : DMA_CPS3 */ - union { - struct - { - uint32_t SETUP_CMD_RPORT : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS3; - - /* 0x1D4 : DMA_CPS4 */ - union { - struct - { - uint32_t reserved_0_31 : 32; /* [31: 0], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DMA_CPS4; - - /* 0x1D8 : DEV_FMAP2 */ - union { - struct - { - uint32_t EPNO_FIFO4 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO4 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO5 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO5 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO6 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO6 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO7 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO7 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP2; - - /* 0x1DC : DEV_FCFG2 */ - union { - struct - { - uint32_t BLK_TYP_F4 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F4 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F4 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F4 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F5 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F5 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F5 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F5 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F6 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F6 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F6 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F6 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F7 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F7 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F7 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F7 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG2; - - /* 0x1E0 : DEV_FMAP3 */ - union { - struct - { - uint32_t EPNO_FIFO8 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO8 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO9 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO9 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO10 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO10 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO11 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO11 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP3; - - /* 0x1E4 : DEV_FCFG3 */ - union { - struct - { - uint32_t BLK_TYP_F8 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F8 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F8 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F8 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F9 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F9 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F9 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F9 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F10 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F10 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F10 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F10 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F11 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F11 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F11 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F11 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG3; - - /* 0x1E8 : DEV_FMAP4 */ - union { - struct - { - uint32_t EPNO_FIFO12 : 4; /* [ 3: 0], None, 0x0 */ - uint32_t Dir_FIFO12 : 2; /* [ 5: 4], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t EPNO_FIFO13 : 4; /* [11: 8], None, 0x0 */ - uint32_t Dir_FIFO13 : 2; /* [13:12], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t EPNO_FIFO14 : 4; /* [19:16], None, 0x0 */ - uint32_t Dir_FIFO14 : 2; /* [21:20], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t EPNO_FIFO15 : 4; /* [27:24], None, 0x0 */ - uint32_t Dir_FIFO15 : 2; /* [29:28], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FMAP4; - - /* 0x1EC : DEV_FCFG4 */ - union { - struct - { - uint32_t BLK_TYP_F12 : 2; /* [ 1: 0], None, 0x0 */ - uint32_t BLKNO_F12 : 2; /* [ 3: 2], None, 0x0 */ - uint32_t BLKSZ_F12 : 1; /* [ 4], None, 0x0 */ - uint32_t EN_F12 : 1; /* [ 5], None, 0x0 */ - uint32_t reserved_6_7 : 2; /* [ 7: 6], rsvd, 0x0 */ - uint32_t BLK_TYP_F13 : 2; /* [ 9: 8], None, 0x0 */ - uint32_t BLKNO_F13 : 2; /* [11:10], None, 0x0 */ - uint32_t BLKSZ_F13 : 1; /* [ 12], None, 0x0 */ - uint32_t EN_F13 : 1; /* [ 13], None, 0x0 */ - uint32_t reserved_14_15 : 2; /* [15:14], rsvd, 0x0 */ - uint32_t BLK_TYP_F14 : 2; /* [17:16], None, 0x0 */ - uint32_t BLKNO_F14 : 2; /* [19:18], None, 0x0 */ - uint32_t BLKSZ_F14 : 1; /* [ 20], None, 0x0 */ - uint32_t EN_F14 : 1; /* [ 21], None, 0x0 */ - uint32_t reserved_22_23 : 2; /* [23:22], rsvd, 0x0 */ - uint32_t BLK_TYP_F15 : 2; /* [25:24], None, 0x0 */ - uint32_t BLKNO_F15 : 2; /* [27:26], None, 0x0 */ - uint32_t BLKSZ_F15 : 1; /* [ 28], None, 0x0 */ - uint32_t EN_F15 : 1; /* [ 29], None, 0x0 */ - uint32_t reserved_30_31 : 2; /* [31:30], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FCFG4; - - /* 0x1F0 : DEV_FIBC4 */ - union { - struct - { - uint32_t BC_F4 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST4_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC4; - - /* 0x1F4 : DEV_FIBC5 */ - union { - struct - { - uint32_t BC_F5 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST5_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC5; - - /* 0x1F8 : DEV_FIBC6 */ - union { - struct - { - uint32_t BC_F6 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST6_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC6; - - /* 0x1FC : DEV_FIBC7 */ - union { - struct - { - uint32_t BC_F7 : 11; /* [10: 0], None, 0x0 */ - uint32_t reserved_11 : 1; /* [ 11], rsvd, 0x0 */ - uint32_t FFRST7_HOV : 1; /* [ 12], None, 0x0 */ - uint32_t reserved_13_31 : 19; /* [31:13], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_FIBC7; - - /* 0x200 reserved */ - uint8_t RESERVED0x200[256]; - - /* 0x300 : VDMA_CXFPS1 */ - union { - struct - { - uint32_t VDMA_START_CXF : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_CXF : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_CXF : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_CXF : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_CXFPS1; - - /* 0x304 : None */ - union { - struct - { - uint32_t VDMA_MADDR_CXF : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_CXFPS2; - - /* 0x308 : None */ - union { - struct - { - uint32_t VDMA_START_F0 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F0 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F0 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F0 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F0PS1; - - /* 0x30C : VDMA_F0PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F0 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F0PS2; - - /* 0x310 : VDMA_F1PS1 */ - union { - struct - { - uint32_t VDMA_START_F1 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F1 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F1 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F1 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F1PS1; - - /* 0x314 : VDMA_F1PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F1 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F1PS2; - - /* 0x318 : VDMA_F2PS1 */ - union { - struct - { - uint32_t VDMA_START_F2 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F2 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F2 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F2 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F2PS1; - - /* 0x31C : VDMA_F2PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F2 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F2PS2; - - /* 0x320 : VDMA_F3PS1 */ - union { - struct - { - uint32_t VDMA_START_F3 : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_F3 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_F3 : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_F3 : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F3PS1; - - /* 0x324 : VDMA_F3PS2 */ - union { - struct - { - uint32_t VDMA_MADDR_F3 : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_F3PS2; - - /* 0x328 : DEV_ISG3 */ - union { - struct - { - uint32_t VDMA_CMPLT_CXF : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_CMPLT_F0 : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_CMPLT_F1 : 1; /* [ 2], None, 0x0 */ - uint32_t VDMA_CMPLT_F2 : 1; /* [ 3], None, 0x0 */ - uint32_t VDMA_CMPLT_F3 : 1; /* [ 4], None, 0x0 */ - uint32_t VDMA_CMPLT_F4 : 1; /* [ 5], None, 0x0 */ - uint32_t VDMA_CMPLT_F5 : 1; /* [ 6], None, 0x0 */ - uint32_t VDMA_CMPLT_F6 : 1; /* [ 7], None, 0x0 */ - uint32_t VDMA_CMPLT_F7 : 1; /* [ 8], None, 0x0 */ - uint32_t VDMA_CMPLT_F8 : 1; /* [ 9], None, 0x0 */ - uint32_t VDMA_CMPLT_F9 : 1; /* [ 10], None, 0x0 */ - uint32_t VDMA_CMPLT_F10 : 1; /* [ 11], None, 0x0 */ - uint32_t VDMA_CMPLT_F11 : 1; /* [ 12], None, 0x0 */ - uint32_t VDMA_CMPLT_F12 : 1; /* [ 13], None, 0x0 */ - uint32_t VDMA_CMPLT_F13 : 1; /* [ 14], None, 0x0 */ - uint32_t VDMA_CMPLT_F14 : 1; /* [ 15], None, 0x0 */ - uint32_t VDMA_ERROR_CXF : 1; /* [ 16], None, 0x0 */ - uint32_t VDMA_ERROR_F0 : 1; /* [ 17], None, 0x0 */ - uint32_t VDMA_ERROR_F1 : 1; /* [ 18], None, 0x0 */ - uint32_t VDMA_ERROR_F2 : 1; /* [ 19], None, 0x0 */ - uint32_t VDMA_ERROR_F3 : 1; /* [ 20], None, 0x0 */ - uint32_t VDMA_ERROR_F4 : 1; /* [ 21], None, 0x0 */ - uint32_t VDMA_ERROR_F5 : 1; /* [ 22], None, 0x0 */ - uint32_t VDMA_ERROR_F6 : 1; /* [ 23], None, 0x0 */ - uint32_t VDMA_ERROR_F7 : 1; /* [ 24], None, 0x0 */ - uint32_t VDMA_ERROR_F8 : 1; /* [ 25], None, 0x0 */ - uint32_t VDMA_ERROR_F9 : 1; /* [ 26], None, 0x0 */ - uint32_t VDMA_ERROR_F10 : 1; /* [ 27], None, 0x0 */ - uint32_t VDMA_ERROR_F11 : 1; /* [ 28], None, 0x0 */ - uint32_t VDMA_ERROR_F12 : 1; /* [ 29], None, 0x0 */ - uint32_t VDMA_ERROR_F13 : 1; /* [ 30], None, 0x0 */ - uint32_t VDMA_ERROR_F14 : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG3; - - /* 0x32C : DEV_MISG3 */ - union { - struct - { - uint32_t MVDMA_CMPLT_CXF : 1; /* [ 0], None, 0x0 */ - uint32_t MVDMA_CMPLT_F0 : 1; /* [ 1], None, 0x0 */ - uint32_t MVDMA_CMPLT_F1 : 1; /* [ 2], None, 0x0 */ - uint32_t MVDMA_CMPLT_F2 : 1; /* [ 3], None, 0x0 */ - uint32_t MVDMA_CMPLT_F3 : 1; /* [ 4], None, 0x0 */ - uint32_t MVDMA_CMPLT_F4 : 1; /* [ 5], None, 0x0 */ - uint32_t MVDMA_CMPLT_F5 : 1; /* [ 6], None, 0x0 */ - uint32_t MVDMA_CMPLT_F6 : 1; /* [ 7], None, 0x0 */ - uint32_t MVDMA_CMPLT_F7 : 1; /* [ 8], None, 0x0 */ - uint32_t MVDMA_CMPLT_F8 : 1; /* [ 9], None, 0x0 */ - uint32_t MVDMA_CMPLT_F9 : 1; /* [ 10], None, 0x0 */ - uint32_t MVDMA_CMPLT_F10 : 1; /* [ 11], None, 0x0 */ - uint32_t MVDMA_CMPLT_F11 : 1; /* [ 12], None, 0x0 */ - uint32_t MVDMA_CMPLT_F12 : 1; /* [ 13], None, 0x0 */ - uint32_t MVDMA_CMPLT_F13 : 1; /* [ 14], None, 0x0 */ - uint32_t MVDMA_CMPLT_F14 : 1; /* [ 15], None, 0x0 */ - uint32_t MVDMA_ERROR_CXF : 1; /* [ 16], None, 0x0 */ - uint32_t MVDMA_ERROR_F0 : 1; /* [ 17], None, 0x0 */ - uint32_t MVDMA_ERROR_F1 : 1; /* [ 18], None, 0x0 */ - uint32_t MVDMA_ERROR_F2 : 1; /* [ 19], None, 0x0 */ - uint32_t MVDMA_ERROR_F3 : 1; /* [ 20], None, 0x0 */ - uint32_t MVDMA_ERROR_F4 : 1; /* [ 21], None, 0x0 */ - uint32_t MVDMA_ERROR_F5 : 1; /* [ 22], None, 0x0 */ - uint32_t MVDMA_ERROR_F6 : 1; /* [ 23], None, 0x0 */ - uint32_t MVDMA_ERROR_F7 : 1; /* [ 24], None, 0x0 */ - uint32_t MVDMA_ERROR_F8 : 1; /* [ 25], None, 0x0 */ - uint32_t MVDMA_ERROR_F9 : 1; /* [ 26], None, 0x0 */ - uint32_t MVDMA_ERROR_F10 : 1; /* [ 27], None, 0x0 */ - uint32_t MVDMA_ERROR_F11 : 1; /* [ 28], None, 0x0 */ - uint32_t MVDMA_ERROR_F12 : 1; /* [ 29], None, 0x0 */ - uint32_t MVDMA_ERROR_F13 : 1; /* [ 30], None, 0x0 */ - uint32_t MVDMA_ERROR_F14 : 1; /* [ 31], None, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG3; - - /* 0x330 : VDMA_CTRL */ - union { - struct - { - uint32_t VDMA_EN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_CTRL; - - /* 0x334 : LPM_CAP */ - union { - struct - { - uint32_t LPM_WAKEUP_EN : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_31 : 31; /* [31: 1], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } LPM_CAP; - - /* 0x338 : DEV_ISG4 */ - union { - struct - { - uint32_t L1_INT : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ - uint32_t VDMA_CMPLT_F15 : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t VDMA_ERROR_F15 : 1; /* [ 24], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_ISG4; - - /* 0x33C : DEV_MISG4 */ - union { - struct - { - uint32_t ML1_INT : 1; /* [ 0], None, 0x0 */ - uint32_t reserved_1_15 : 15; /* [15: 1], rsvd, 0x0 */ - uint32_t MVDMA_CMPLT_F15 : 1; /* [ 16], None, 0x0 */ - uint32_t reserved_17_23 : 7; /* [23:17], rsvd, 0x0 */ - uint32_t MVDMA_ERROR_F15 : 1; /* [ 24], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } DEV_MISG4; - - /* 0x340 reserved */ - uint8_t RESERVED0x340[16]; - - /* 0x350 : VDMA_FnPS1 */ - union { - struct - { - uint32_t VDMA_START_Fn : 1; /* [ 0], None, 0x0 */ - uint32_t VDMA_TYPE_Fn : 1; /* [ 1], None, 0x0 */ - uint32_t VDMA_IO_Fn : 1; /* [ 2], None, 0x0 */ - uint32_t reserved_3_7 : 5; /* [ 7: 3], rsvd, 0x0 */ - uint32_t VDMA_LEN_Fn : 17; /* [24: 8], None, 0x0 */ - uint32_t reserved_25_31 : 7; /* [31:25], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_FnPS1; - - /* 0x354 : VDMA_FnPS2 */ - union { - struct - { - uint32_t VDMA_MADDR_Fn : 32; /* [31: 0], None, 0x0 */ - } BF; - uint32_t WORD; - } VDMA_FnPS2; -}; - -typedef volatile struct usb_reg usb_reg_t; - -#endif /* __USB_REG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/clic.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/clic.h deleted file mode 100644 index 3ea51390b8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/clic.h +++ /dev/null @@ -1,21 +0,0 @@ -// See LICENSE for license details. - -#ifndef _SIFIVE_CLIC_H -#define _SIFIVE_CLIC_H - -#define CLIC_CTRL_ADDR 0x02000000UL -#define CLIC_HART0_ADDR 0x02800000UL - -#define CLIC_MSIP 0x0000 -#define CLIC_MSIP_size 0x4 -#define CLIC_MTIMECMP 0x4000 -#define CLIC_MTIMECMP_size 0x8 -#define CLIC_MTIME 0xBFF8 -#define CLIC_MTIME_size 0x8 - -#define CLIC_INTIP 0x000 -#define CLIC_INTIE 0x400 -#define CLIC_INTCFG 0x800 -#define CLIC_CFG 0xc00 - -#endif /* _SIFIVE_CLIC_H */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_bits.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_bits.h deleted file mode 100644 index 16b15bcddd..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_bits.h +++ /dev/null @@ -1,36 +0,0 @@ -// See LICENSE for license details. -#ifndef _RISCV_BITS_H -#define _RISCV_BITS_H - -#define likely(x) __builtin_expect((x), 1) -#define unlikely(x) __builtin_expect((x), 0) - -#define ROUNDUP(a, b) ((((a)-1) / (b) + 1) * (b)) -#define ROUNDDOWN(a, b) ((a) / (b) * (b)) - -#define MAX(a, b) ((a) > (b) ? (a) : (b)) -#define MIN(a, b) ((a) < (b) ? (a) : (b)) -#define CLAMP(a, lo, hi) MIN(MAX(a, lo), hi) - -#define EXTRACT_FIELD(val, which) (((val) & (which)) / ((which) & ~((which)-1))) -#define INSERT_FIELD(val, which, fieldval) (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1)))) - -#define STR(x) XSTR(x) -#define XSTR(x) #x - -#if __riscv_xlen == 64 -#define SLL32 sllw -#define STORE sd -#define LOAD ld -#define LWU lwu -#define LOG_REGBYTES 3 -#else -#define SLL32 sll -#define STORE sw -#define LOAD lw -#define LWU lw -#define LOG_REGBYTES 2 -#endif -#define REGBYTES (1 << LOG_REGBYTES) - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_const.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_const.h deleted file mode 100644 index 109d1dff76..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_const.h +++ /dev/null @@ -1,18 +0,0 @@ -// See LICENSE for license details. -/* Derived from */ - -#ifndef _RISCV_CONST_H -#define _RISCV_CONST_H - -#ifdef __ASSEMBLER__ -#define _AC(X, Y) X -#define _AT(T, X) X -#else -#define _AC(X, Y) (X##Y) -#define _AT(T, X) ((T)(X)) -#endif /* !__ASSEMBLER__*/ - -#define _BITUL(x) (_AC(1, UL) << (x)) -#define _BITULL(x) (_AC(1, ULL) << (x)) - -#endif /* _NUCLEI_CONST_H */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_encoding.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_encoding.h deleted file mode 100644 index f1dbf3a185..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/riscv_encoding.h +++ /dev/null @@ -1,1363 +0,0 @@ -// See LICENSE for license details. - -#ifndef RISCV_CSR_ENCODING_H -#define RISCV_CSR_ENCODING_H - -#define MSTATUS_UIE 0x00000001 -#define MSTATUS_SIE 0x00000002 -#define MSTATUS_HIE 0x00000004 -#define MSTATUS_MIE 0x00000008 -#define MSTATUS_UPIE 0x00000010 -#define MSTATUS_SPIE 0x00000020 -#define MSTATUS_HPIE 0x00000040 -#define MSTATUS_MPIE 0x00000080 -#define MSTATUS_SPP 0x00000100 -#define MSTATUS_MPP 0x00001800 -#define MSTATUS_FS 0x00006000 -#define MSTATUS_XS 0x00018000 -#define MSTATUS_MPRV 0x00020000 -#define MSTATUS_SUM 0x00040000 -#define MSTATUS_MXR 0x00080000 -#define MSTATUS_VM 0x1F000000 -#define MSTATUS32_SD 0x80000000 -#define MSTATUS64_SD 0x8000000000000000 - -#define SSTATUS_UIE 0x00000001 -#define SSTATUS_SIE 0x00000002 -#define SSTATUS_UPIE 0x00000010 -#define SSTATUS_SPIE 0x00000020 -#define SSTATUS_SPP 0x00000100 -#define SSTATUS_FS 0x00006000 -#define SSTATUS_XS 0x00018000 -#define SSTATUS_PUM 0x00040000 -#define SSTATUS32_SD 0x80000000 -#define SSTATUS64_SD 0x8000000000000000 - -#define DCSR_XDEBUGVER (3U << 30) -#define DCSR_NDRESET (1 << 29) -#define DCSR_FULLRESET (1 << 28) -#define DCSR_EBREAKM (1 << 15) -#define DCSR_EBREAKH (1 << 14) -#define DCSR_EBREAKS (1 << 13) -#define DCSR_EBREAKU (1 << 12) -#define DCSR_STOPCYCLE (1 << 10) -#define DCSR_STOPTIME (1 << 9) -#define DCSR_CAUSE (7 << 6) -#define DCSR_DEBUGINT (1 << 5) -#define DCSR_HALT (1 << 3) -#define DCSR_STEP (1 << 2) -#define DCSR_PRV (3 << 0) - -#define DCSR_CAUSE_NONE 0 -#define DCSR_CAUSE_SWBP 1 -#define DCSR_CAUSE_HWBP 2 -#define DCSR_CAUSE_DEBUGINT 3 -#define DCSR_CAUSE_STEP 4 -#define DCSR_CAUSE_HALT 5 - -#define MCONTROL_TYPE(xlen) (0xfULL << ((xlen)-4)) -#define MCONTROL_DMODE(xlen) (1ULL << ((xlen)-5)) -#define MCONTROL_MASKMAX(xlen) (0x3fULL << ((xlen)-11)) - -#define MCONTROL_SELECT (1 << 19) -#define MCONTROL_TIMING (1 << 18) -#define MCONTROL_ACTION (0x3f << 12) -#define MCONTROL_CHAIN (1 << 11) -#define MCONTROL_MATCH (0xf << 7) -#define MCONTROL_M (1 << 6) -#define MCONTROL_H (1 << 5) -#define MCONTROL_S (1 << 4) -#define MCONTROL_U (1 << 3) -#define MCONTROL_EXECUTE (1 << 2) -#define MCONTROL_STORE (1 << 1) -#define MCONTROL_LOAD (1 << 0) - -#define MCONTROL_TYPE_NONE 0 -#define MCONTROL_TYPE_MATCH 2 - -#define MCONTROL_ACTION_DEBUG_EXCEPTION 0 -#define MCONTROL_ACTION_DEBUG_MODE 1 -#define MCONTROL_ACTION_TRACE_START 2 -#define MCONTROL_ACTION_TRACE_STOP 3 -#define MCONTROL_ACTION_TRACE_EMIT 4 - -#define MCONTROL_MATCH_EQUAL 0 -#define MCONTROL_MATCH_NAPOT 1 -#define MCONTROL_MATCH_GE 2 -#define MCONTROL_MATCH_LT 3 -#define MCONTROL_MATCH_MASK_LOW 4 -#define MCONTROL_MATCH_MASK_HIGH 5 - -#define MIP_SSIP (1 << IRQ_S_SOFT) -#define MIP_HSIP (1 << IRQ_H_SOFT) -#define MIP_MSIP (1 << IRQ_M_SOFT) -#define MIP_STIP (1 << IRQ_S_TIMER) -#define MIP_HTIP (1 << IRQ_H_TIMER) -#define MIP_MTIP (1 << IRQ_M_TIMER) -#define MIP_SEIP (1 << IRQ_S_EXT) -#define MIP_HEIP (1 << IRQ_H_EXT) -#define MIP_MEIP (1 << IRQ_M_EXT) - -#define MIE_SSIE MIP_SSIP -#define MIE_HSIE MIP_HSIP -#define MIE_MSIE MIP_MSIP -#define MIE_STIE MIP_STIP -#define MIE_HTIE MIP_HTIP -#define MIE_MTIE MIP_MTIP -#define MIE_SEIE MIP_SEIP -#define MIE_HEIE MIP_HEIP -#define MIE_MEIE MIP_MEIP - -#define SIP_SSIP MIP_SSIP -#define SIP_STIP MIP_STIP - -#define PRV_U 0 -#define PRV_S 1 -#define PRV_H 2 -#define PRV_M 3 - -#define VM_MBARE 0 -#define VM_MBB 1 -#define VM_MBBID 2 -#define VM_SV32 8 -#define VM_SV39 9 -#define VM_SV48 10 - -#define IRQ_S_SOFT 1 -#define IRQ_H_SOFT 2 -#define IRQ_M_SOFT 3 -#define IRQ_S_TIMER 5 -#define IRQ_H_TIMER 6 -#define IRQ_M_TIMER 7 -#define IRQ_S_EXT 9 -#define IRQ_H_EXT 10 -#define IRQ_M_EXT 11 -#define IRQ_COP 12 -#define IRQ_HOST 13 - -#define DEFAULT_RSTVEC 0x00001000 -#define DEFAULT_NMIVEC 0x00001004 -#define DEFAULT_MTVEC 0x00001010 -#define CONFIG_STRING_ADDR 0x0000100C -#define EXT_IO_BASE 0x40000000 -#define DRAM_BASE 0x80000000 - -// page table entry (PTE) fields -#define PTE_V 0x001 // Valid -#define PTE_R 0x002 // Read -#define PTE_W 0x004 // Write -#define PTE_X 0x008 // Execute -#define PTE_U 0x010 // User -#define PTE_G 0x020 // Global -#define PTE_A 0x040 // Accessed -#define PTE_D 0x080 // Dirty -#define PTE_SOFT 0x300 // Reserved for Software - -#define PTE_PPN_SHIFT 10 - -#define PTE_TABLE(PTE) (((PTE) & (PTE_V | PTE_R | PTE_W | PTE_X)) == PTE_V) - -#ifdef __riscv - -#ifdef __riscv64 -#define MSTATUS_SD MSTATUS64_SD -#define SSTATUS_SD SSTATUS64_SD -#define RISCV_PGLEVEL_BITS 9 -#else -#define MSTATUS_SD MSTATUS32_SD -#define SSTATUS_SD SSTATUS32_SD -#define RISCV_PGLEVEL_BITS 10 -#endif -#define RISCV_PGSHIFT 12 -#define RISCV_PGSIZE (1 << RISCV_PGSHIFT) - -#ifndef __ASSEMBLER__ - -#ifdef __GNUC__ - -#define asm __asm - -#define read_fpu(reg) ({ unsigned long __tmp; \ - asm volatile ("fmv.x.w %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_fpu(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("fmv.w.x " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("fmv.w.x " #reg ", %0" :: "r"(val)); }) - -#define read_csr(reg) ({ unsigned long __tmp; \ - asm volatile ("csrr %0, " #reg : "=r"(__tmp)); \ - __tmp; }) - -#define write_csr(reg, val) ({ \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrw " #reg ", %0" :: "i"(val)); \ - else \ - asm volatile ("csrw " #reg ", %0" :: "r"(val)); }) - -#define swap_csr(reg, val) ({ unsigned long __tmp; \ - if (__builtin_constant_p(val) && (unsigned long)(val) < 32) \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "i"(val)); \ - else \ - asm volatile ("csrrw %0, " #reg ", %1" : "=r"(__tmp) : "r"(val)); \ - __tmp; }) - -#define set_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrs %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define clear_csr(reg, bit) ({ unsigned long __tmp; \ - if (__builtin_constant_p(bit) && (unsigned long)(bit) < 32) \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "i"(bit)); \ - else \ - asm volatile ("csrrc %0, " #reg ", %1" : "=r"(__tmp) : "r"(bit)); \ - __tmp; }) - -#define rdtime() read_csr(time) -#define rdcycle() read_csr(cycle) -#define rdinstret() read_csr(instret) - -#endif - -#endif - -#endif - -#endif -/* Automatically generated by parse-opcodes */ -#ifndef RISCV_ENCODING_H -#define RISCV_ENCODING_H -#define MATCH_BEQ 0x63 -#define MASK_BEQ 0x707f -#define MATCH_BNE 0x1063 -#define MASK_BNE 0x707f -#define MATCH_BLT 0x4063 -#define MASK_BLT 0x707f -#define MATCH_BGE 0x5063 -#define MASK_BGE 0x707f -#define MATCH_BLTU 0x6063 -#define MASK_BLTU 0x707f -#define MATCH_BGEU 0x7063 -#define MASK_BGEU 0x707f -#define MATCH_JALR 0x67 -#define MASK_JALR 0x707f -#define MATCH_JAL 0x6f -#define MASK_JAL 0x7f -#define MATCH_LUI 0x37 -#define MASK_LUI 0x7f -#define MATCH_AUIPC 0x17 -#define MASK_AUIPC 0x7f -#define MATCH_ADDI 0x13 -#define MASK_ADDI 0x707f -#define MATCH_SLLI 0x1013 -#define MASK_SLLI 0xfc00707f -#define MATCH_SLTI 0x2013 -#define MASK_SLTI 0x707f -#define MATCH_SLTIU 0x3013 -#define MASK_SLTIU 0x707f -#define MATCH_XORI 0x4013 -#define MASK_XORI 0x707f -#define MATCH_SRLI 0x5013 -#define MASK_SRLI 0xfc00707f -#define MATCH_SRAI 0x40005013 -#define MASK_SRAI 0xfc00707f -#define MATCH_ORI 0x6013 -#define MASK_ORI 0x707f -#define MATCH_ANDI 0x7013 -#define MASK_ANDI 0x707f -#define MATCH_ADD 0x33 -#define MASK_ADD 0xfe00707f -#define MATCH_SUB 0x40000033 -#define MASK_SUB 0xfe00707f -#define MATCH_SLL 0x1033 -#define MASK_SLL 0xfe00707f -#define MATCH_SLT 0x2033 -#define MASK_SLT 0xfe00707f -#define MATCH_SLTU 0x3033 -#define MASK_SLTU 0xfe00707f -#define MATCH_XOR 0x4033 -#define MASK_XOR 0xfe00707f -#define MATCH_SRL 0x5033 -#define MASK_SRL 0xfe00707f -#define MATCH_SRA 0x40005033 -#define MASK_SRA 0xfe00707f -#define MATCH_OR 0x6033 -#define MASK_OR 0xfe00707f -#define MATCH_AND 0x7033 -#define MASK_AND 0xfe00707f -#define MATCH_ADDIW 0x1b -#define MASK_ADDIW 0x707f -#define MATCH_SLLIW 0x101b -#define MASK_SLLIW 0xfe00707f -#define MATCH_SRLIW 0x501b -#define MASK_SRLIW 0xfe00707f -#define MATCH_SRAIW 0x4000501b -#define MASK_SRAIW 0xfe00707f -#define MATCH_ADDW 0x3b -#define MASK_ADDW 0xfe00707f -#define MATCH_SUBW 0x4000003b -#define MASK_SUBW 0xfe00707f -#define MATCH_SLLW 0x103b -#define MASK_SLLW 0xfe00707f -#define MATCH_SRLW 0x503b -#define MASK_SRLW 0xfe00707f -#define MATCH_SRAW 0x4000503b -#define MASK_SRAW 0xfe00707f -#define MATCH_LB 0x3 -#define MASK_LB 0x707f -#define MATCH_LH 0x1003 -#define MASK_LH 0x707f -#define MATCH_LW 0x2003 -#define MASK_LW 0x707f -#define MATCH_LD 0x3003 -#define MASK_LD 0x707f -#define MATCH_LBU 0x4003 -#define MASK_LBU 0x707f -#define MATCH_LHU 0x5003 -#define MASK_LHU 0x707f -#define MATCH_LWU 0x6003 -#define MASK_LWU 0x707f -#define MATCH_SB 0x23 -#define MASK_SB 0x707f -#define MATCH_SH 0x1023 -#define MASK_SH 0x707f -#define MATCH_SW 0x2023 -#define MASK_SW 0x707f -#define MATCH_SD 0x3023 -#define MASK_SD 0x707f -#define MATCH_FENCE 0xf -#define MASK_FENCE 0x707f -#define MATCH_FENCE_I 0x100f -#define MASK_FENCE_I 0x707f -#define MATCH_MUL 0x2000033 -#define MASK_MUL 0xfe00707f -#define MATCH_MULH 0x2001033 -#define MASK_MULH 0xfe00707f -#define MATCH_MULHSU 0x2002033 -#define MASK_MULHSU 0xfe00707f -#define MATCH_MULHU 0x2003033 -#define MASK_MULHU 0xfe00707f -#define MATCH_DIV 0x2004033 -#define MASK_DIV 0xfe00707f -#define MATCH_DIVU 0x2005033 -#define MASK_DIVU 0xfe00707f -#define MATCH_REM 0x2006033 -#define MASK_REM 0xfe00707f -#define MATCH_REMU 0x2007033 -#define MASK_REMU 0xfe00707f -#define MATCH_MULW 0x200003b -#define MASK_MULW 0xfe00707f -#define MATCH_DIVW 0x200403b -#define MASK_DIVW 0xfe00707f -#define MATCH_DIVUW 0x200503b -#define MASK_DIVUW 0xfe00707f -#define MATCH_REMW 0x200603b -#define MASK_REMW 0xfe00707f -#define MATCH_REMUW 0x200703b -#define MASK_REMUW 0xfe00707f -#define MATCH_AMOADD_W 0x202f -#define MASK_AMOADD_W 0xf800707f -#define MATCH_AMOXOR_W 0x2000202f -#define MASK_AMOXOR_W 0xf800707f -#define MATCH_AMOOR_W 0x4000202f -#define MASK_AMOOR_W 0xf800707f -#define MATCH_AMOAND_W 0x6000202f -#define MASK_AMOAND_W 0xf800707f -#define MATCH_AMOMIN_W 0x8000202f -#define MASK_AMOMIN_W 0xf800707f -#define MATCH_AMOMAX_W 0xa000202f -#define MASK_AMOMAX_W 0xf800707f -#define MATCH_AMOMINU_W 0xc000202f -#define MASK_AMOMINU_W 0xf800707f -#define MATCH_AMOMAXU_W 0xe000202f -#define MASK_AMOMAXU_W 0xf800707f -#define MATCH_AMOSWAP_W 0x800202f -#define MASK_AMOSWAP_W 0xf800707f -#define MATCH_LR_W 0x1000202f -#define MASK_LR_W 0xf9f0707f -#define MATCH_SC_W 0x1800202f -#define MASK_SC_W 0xf800707f -#define MATCH_AMOADD_D 0x302f -#define MASK_AMOADD_D 0xf800707f -#define MATCH_AMOXOR_D 0x2000302f -#define MASK_AMOXOR_D 0xf800707f -#define MATCH_AMOOR_D 0x4000302f -#define MASK_AMOOR_D 0xf800707f -#define MATCH_AMOAND_D 0x6000302f -#define MASK_AMOAND_D 0xf800707f -#define MATCH_AMOMIN_D 0x8000302f -#define MASK_AMOMIN_D 0xf800707f -#define MATCH_AMOMAX_D 0xa000302f -#define MASK_AMOMAX_D 0xf800707f -#define MATCH_AMOMINU_D 0xc000302f -#define MASK_AMOMINU_D 0xf800707f -#define MATCH_AMOMAXU_D 0xe000302f -#define MASK_AMOMAXU_D 0xf800707f -#define MATCH_AMOSWAP_D 0x800302f -#define MASK_AMOSWAP_D 0xf800707f -#define MATCH_LR_D 0x1000302f -#define MASK_LR_D 0xf9f0707f -#define MATCH_SC_D 0x1800302f -#define MASK_SC_D 0xf800707f -#define MATCH_ECALL 0x73 -#define MASK_ECALL 0xffffffff -#define MATCH_EBREAK 0x100073 -#define MASK_EBREAK 0xffffffff -#define MATCH_URET 0x200073 -#define MASK_URET 0xffffffff -#define MATCH_SRET 0x10200073 -#define MASK_SRET 0xffffffff -#define MATCH_HRET 0x20200073 -#define MASK_HRET 0xffffffff -#define MATCH_MRET 0x30200073 -#define MASK_MRET 0xffffffff -#define MATCH_DRET 0x7b200073 -#define MASK_DRET 0xffffffff -#define MATCH_SFENCE_VM 0x10400073 -#define MASK_SFENCE_VM 0xfff07fff -#define MATCH_WFI 0x10500073 -#define MASK_WFI 0xffffffff -#define MATCH_CSRRW 0x1073 -#define MASK_CSRRW 0x707f -#define MATCH_CSRRS 0x2073 -#define MASK_CSRRS 0x707f -#define MATCH_CSRRC 0x3073 -#define MASK_CSRRC 0x707f -#define MATCH_CSRRWI 0x5073 -#define MASK_CSRRWI 0x707f -#define MATCH_CSRRSI 0x6073 -#define MASK_CSRRSI 0x707f -#define MATCH_CSRRCI 0x7073 -#define MASK_CSRRCI 0x707f -#define MATCH_FADD_S 0x53 -#define MASK_FADD_S 0xfe00007f -#define MATCH_FSUB_S 0x8000053 -#define MASK_FSUB_S 0xfe00007f -#define MATCH_FMUL_S 0x10000053 -#define MASK_FMUL_S 0xfe00007f -#define MATCH_FDIV_S 0x18000053 -#define MASK_FDIV_S 0xfe00007f -#define MATCH_FSGNJ_S 0x20000053 -#define MASK_FSGNJ_S 0xfe00707f -#define MATCH_FSGNJN_S 0x20001053 -#define MASK_FSGNJN_S 0xfe00707f -#define MATCH_FSGNJX_S 0x20002053 -#define MASK_FSGNJX_S 0xfe00707f -#define MATCH_FMIN_S 0x28000053 -#define MASK_FMIN_S 0xfe00707f -#define MATCH_FMAX_S 0x28001053 -#define MASK_FMAX_S 0xfe00707f -#define MATCH_FSQRT_S 0x58000053 -#define MASK_FSQRT_S 0xfff0007f -#define MATCH_FADD_D 0x2000053 -#define MASK_FADD_D 0xfe00007f -#define MATCH_FSUB_D 0xa000053 -#define MASK_FSUB_D 0xfe00007f -#define MATCH_FMUL_D 0x12000053 -#define MASK_FMUL_D 0xfe00007f -#define MATCH_FDIV_D 0x1a000053 -#define MASK_FDIV_D 0xfe00007f -#define MATCH_FSGNJ_D 0x22000053 -#define MASK_FSGNJ_D 0xfe00707f -#define MATCH_FSGNJN_D 0x22001053 -#define MASK_FSGNJN_D 0xfe00707f -#define MATCH_FSGNJX_D 0x22002053 -#define MASK_FSGNJX_D 0xfe00707f -#define MATCH_FMIN_D 0x2a000053 -#define MASK_FMIN_D 0xfe00707f -#define MATCH_FMAX_D 0x2a001053 -#define MASK_FMAX_D 0xfe00707f -#define MATCH_FCVT_S_D 0x40100053 -#define MASK_FCVT_S_D 0xfff0007f -#define MATCH_FCVT_D_S 0x42000053 -#define MASK_FCVT_D_S 0xfff0007f -#define MATCH_FSQRT_D 0x5a000053 -#define MASK_FSQRT_D 0xfff0007f -#define MATCH_FLE_S 0xa0000053 -#define MASK_FLE_S 0xfe00707f -#define MATCH_FLT_S 0xa0001053 -#define MASK_FLT_S 0xfe00707f -#define MATCH_FEQ_S 0xa0002053 -#define MASK_FEQ_S 0xfe00707f -#define MATCH_FLE_D 0xa2000053 -#define MASK_FLE_D 0xfe00707f -#define MATCH_FLT_D 0xa2001053 -#define MASK_FLT_D 0xfe00707f -#define MATCH_FEQ_D 0xa2002053 -#define MASK_FEQ_D 0xfe00707f -#define MATCH_FCVT_W_S 0xc0000053 -#define MASK_FCVT_W_S 0xfff0007f -#define MATCH_FCVT_WU_S 0xc0100053 -#define MASK_FCVT_WU_S 0xfff0007f -#define MATCH_FCVT_L_S 0xc0200053 -#define MASK_FCVT_L_S 0xfff0007f -#define MATCH_FCVT_LU_S 0xc0300053 -#define MASK_FCVT_LU_S 0xfff0007f -#define MATCH_FMV_X_S 0xe0000053 -#define MASK_FMV_X_S 0xfff0707f -#define MATCH_FCLASS_S 0xe0001053 -#define MASK_FCLASS_S 0xfff0707f -#define MATCH_FCVT_W_D 0xc2000053 -#define MASK_FCVT_W_D 0xfff0007f -#define MATCH_FCVT_WU_D 0xc2100053 -#define MASK_FCVT_WU_D 0xfff0007f -#define MATCH_FCVT_L_D 0xc2200053 -#define MASK_FCVT_L_D 0xfff0007f -#define MATCH_FCVT_LU_D 0xc2300053 -#define MASK_FCVT_LU_D 0xfff0007f -#define MATCH_FMV_X_D 0xe2000053 -#define MASK_FMV_X_D 0xfff0707f -#define MATCH_FCLASS_D 0xe2001053 -#define MASK_FCLASS_D 0xfff0707f -#define MATCH_FCVT_S_W 0xd0000053 -#define MASK_FCVT_S_W 0xfff0007f -#define MATCH_FCVT_S_WU 0xd0100053 -#define MASK_FCVT_S_WU 0xfff0007f -#define MATCH_FCVT_S_L 0xd0200053 -#define MASK_FCVT_S_L 0xfff0007f -#define MATCH_FCVT_S_LU 0xd0300053 -#define MASK_FCVT_S_LU 0xfff0007f -#define MATCH_FMV_S_X 0xf0000053 -#define MASK_FMV_S_X 0xfff0707f -#define MATCH_FCVT_D_W 0xd2000053 -#define MASK_FCVT_D_W 0xfff0007f -#define MATCH_FCVT_D_WU 0xd2100053 -#define MASK_FCVT_D_WU 0xfff0007f -#define MATCH_FCVT_D_L 0xd2200053 -#define MASK_FCVT_D_L 0xfff0007f -#define MATCH_FCVT_D_LU 0xd2300053 -#define MASK_FCVT_D_LU 0xfff0007f -#define MATCH_FMV_D_X 0xf2000053 -#define MASK_FMV_D_X 0xfff0707f -#define MATCH_FLW 0x2007 -#define MASK_FLW 0x707f -#define MATCH_FLD 0x3007 -#define MASK_FLD 0x707f -#define MATCH_FSW 0x2027 -#define MASK_FSW 0x707f -#define MATCH_FSD 0x3027 -#define MASK_FSD 0x707f -#define MATCH_FMADD_S 0x43 -#define MASK_FMADD_S 0x600007f -#define MATCH_FMSUB_S 0x47 -#define MASK_FMSUB_S 0x600007f -#define MATCH_FNMSUB_S 0x4b -#define MASK_FNMSUB_S 0x600007f -#define MATCH_FNMADD_S 0x4f -#define MASK_FNMADD_S 0x600007f -#define MATCH_FMADD_D 0x2000043 -#define MASK_FMADD_D 0x600007f -#define MATCH_FMSUB_D 0x2000047 -#define MASK_FMSUB_D 0x600007f -#define MATCH_FNMSUB_D 0x200004b -#define MASK_FNMSUB_D 0x600007f -#define MATCH_FNMADD_D 0x200004f -#define MASK_FNMADD_D 0x600007f -#define MATCH_C_NOP 0x1 -#define MASK_C_NOP 0xffff -#define MATCH_C_ADDI16SP 0x6101 -#define MASK_C_ADDI16SP 0xef83 -#define MATCH_C_JR 0x8002 -#define MASK_C_JR 0xf07f -#define MATCH_C_JALR 0x9002 -#define MASK_C_JALR 0xf07f -#define MATCH_C_EBREAK 0x9002 -#define MASK_C_EBREAK 0xffff -#define MATCH_C_LD 0x6000 -#define MASK_C_LD 0xe003 -#define MATCH_C_SD 0xe000 -#define MASK_C_SD 0xe003 -#define MATCH_C_ADDIW 0x2001 -#define MASK_C_ADDIW 0xe003 -#define MATCH_C_LDSP 0x6002 -#define MASK_C_LDSP 0xe003 -#define MATCH_C_SDSP 0xe002 -#define MASK_C_SDSP 0xe003 -#define MATCH_C_ADDI4SPN 0x0 -#define MASK_C_ADDI4SPN 0xe003 -#define MATCH_C_FLD 0x2000 -#define MASK_C_FLD 0xe003 -#define MATCH_C_LW 0x4000 -#define MASK_C_LW 0xe003 -#define MATCH_C_FLW 0x6000 -#define MASK_C_FLW 0xe003 -#define MATCH_C_FSD 0xa000 -#define MASK_C_FSD 0xe003 -#define MATCH_C_SW 0xc000 -#define MASK_C_SW 0xe003 -#define MATCH_C_FSW 0xe000 -#define MASK_C_FSW 0xe003 -#define MATCH_C_ADDI 0x1 -#define MASK_C_ADDI 0xe003 -#define MATCH_C_JAL 0x2001 -#define MASK_C_JAL 0xe003 -#define MATCH_C_LI 0x4001 -#define MASK_C_LI 0xe003 -#define MATCH_C_LUI 0x6001 -#define MASK_C_LUI 0xe003 -#define MATCH_C_SRLI 0x8001 -#define MASK_C_SRLI 0xec03 -#define MATCH_C_SRAI 0x8401 -#define MASK_C_SRAI 0xec03 -#define MATCH_C_ANDI 0x8801 -#define MASK_C_ANDI 0xec03 -#define MATCH_C_SUB 0x8c01 -#define MASK_C_SUB 0xfc63 -#define MATCH_C_XOR 0x8c21 -#define MASK_C_XOR 0xfc63 -#define MATCH_C_OR 0x8c41 -#define MASK_C_OR 0xfc63 -#define MATCH_C_AND 0x8c61 -#define MASK_C_AND 0xfc63 -#define MATCH_C_SUBW 0x9c01 -#define MASK_C_SUBW 0xfc63 -#define MATCH_C_ADDW 0x9c21 -#define MASK_C_ADDW 0xfc63 -#define MATCH_C_J 0xa001 -#define MASK_C_J 0xe003 -#define MATCH_C_BEQZ 0xc001 -#define MASK_C_BEQZ 0xe003 -#define MATCH_C_BNEZ 0xe001 -#define MASK_C_BNEZ 0xe003 -#define MATCH_C_SLLI 0x2 -#define MASK_C_SLLI 0xe003 -#define MATCH_C_FLDSP 0x2002 -#define MASK_C_FLDSP 0xe003 -#define MATCH_C_LWSP 0x4002 -#define MASK_C_LWSP 0xe003 -#define MATCH_C_FLWSP 0x6002 -#define MASK_C_FLWSP 0xe003 -#define MATCH_C_MV 0x8002 -#define MASK_C_MV 0xf003 -#define MATCH_C_ADD 0x9002 -#define MASK_C_ADD 0xf003 -#define MATCH_C_FSDSP 0xa002 -#define MASK_C_FSDSP 0xe003 -#define MATCH_C_SWSP 0xc002 -#define MASK_C_SWSP 0xe003 -#define MATCH_C_FSWSP 0xe002 -#define MASK_C_FSWSP 0xe003 -#define MATCH_CUSTOM0 0xb -#define MASK_CUSTOM0 0x707f -#define MATCH_CUSTOM0_RS1 0x200b -#define MASK_CUSTOM0_RS1 0x707f -#define MATCH_CUSTOM0_RS1_RS2 0x300b -#define MASK_CUSTOM0_RS1_RS2 0x707f -#define MATCH_CUSTOM0_RD 0x400b -#define MASK_CUSTOM0_RD 0x707f -#define MATCH_CUSTOM0_RD_RS1 0x600b -#define MASK_CUSTOM0_RD_RS1 0x707f -#define MATCH_CUSTOM0_RD_RS1_RS2 0x700b -#define MASK_CUSTOM0_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM1 0x2b -#define MASK_CUSTOM1 0x707f -#define MATCH_CUSTOM1_RS1 0x202b -#define MASK_CUSTOM1_RS1 0x707f -#define MATCH_CUSTOM1_RS1_RS2 0x302b -#define MASK_CUSTOM1_RS1_RS2 0x707f -#define MATCH_CUSTOM1_RD 0x402b -#define MASK_CUSTOM1_RD 0x707f -#define MATCH_CUSTOM1_RD_RS1 0x602b -#define MASK_CUSTOM1_RD_RS1 0x707f -#define MATCH_CUSTOM1_RD_RS1_RS2 0x702b -#define MASK_CUSTOM1_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM2 0x5b -#define MASK_CUSTOM2 0x707f -#define MATCH_CUSTOM2_RS1 0x205b -#define MASK_CUSTOM2_RS1 0x707f -#define MATCH_CUSTOM2_RS1_RS2 0x305b -#define MASK_CUSTOM2_RS1_RS2 0x707f -#define MATCH_CUSTOM2_RD 0x405b -#define MASK_CUSTOM2_RD 0x707f -#define MATCH_CUSTOM2_RD_RS1 0x605b -#define MASK_CUSTOM2_RD_RS1 0x707f -#define MATCH_CUSTOM2_RD_RS1_RS2 0x705b -#define MASK_CUSTOM2_RD_RS1_RS2 0x707f -#define MATCH_CUSTOM3 0x7b -#define MASK_CUSTOM3 0x707f -#define MATCH_CUSTOM3_RS1 0x207b -#define MASK_CUSTOM3_RS1 0x707f -#define MATCH_CUSTOM3_RS1_RS2 0x307b -#define MASK_CUSTOM3_RS1_RS2 0x707f -#define MATCH_CUSTOM3_RD 0x407b -#define MASK_CUSTOM3_RD 0x707f -#define MATCH_CUSTOM3_RD_RS1 0x607b -#define MASK_CUSTOM3_RD_RS1 0x707f -#define MATCH_CUSTOM3_RD_RS1_RS2 0x707b -#define MASK_CUSTOM3_RD_RS1_RS2 0x707f -#define CSR_FFLAGS 0x1 -#define CSR_FRM 0x2 -#define CSR_FCSR 0x3 -#define CSR_CYCLE 0xc00 -#define CSR_TIME 0xc01 -#define CSR_INSTRET 0xc02 -#define CSR_HPMCOUNTER3 0xc03 -#define CSR_HPMCOUNTER4 0xc04 -#define CSR_HPMCOUNTER5 0xc05 -#define CSR_HPMCOUNTER6 0xc06 -#define CSR_HPMCOUNTER7 0xc07 -#define CSR_HPMCOUNTER8 0xc08 -#define CSR_HPMCOUNTER9 0xc09 -#define CSR_HPMCOUNTER10 0xc0a -#define CSR_HPMCOUNTER11 0xc0b -#define CSR_HPMCOUNTER12 0xc0c -#define CSR_HPMCOUNTER13 0xc0d -#define CSR_HPMCOUNTER14 0xc0e -#define CSR_HPMCOUNTER15 0xc0f -#define CSR_HPMCOUNTER16 0xc10 -#define CSR_HPMCOUNTER17 0xc11 -#define CSR_HPMCOUNTER18 0xc12 -#define CSR_HPMCOUNTER19 0xc13 -#define CSR_HPMCOUNTER20 0xc14 -#define CSR_HPMCOUNTER21 0xc15 -#define CSR_HPMCOUNTER22 0xc16 -#define CSR_HPMCOUNTER23 0xc17 -#define CSR_HPMCOUNTER24 0xc18 -#define CSR_HPMCOUNTER25 0xc19 -#define CSR_HPMCOUNTER26 0xc1a -#define CSR_HPMCOUNTER27 0xc1b -#define CSR_HPMCOUNTER28 0xc1c -#define CSR_HPMCOUNTER29 0xc1d -#define CSR_HPMCOUNTER30 0xc1e -#define CSR_HPMCOUNTER31 0xc1f -#define CSR_SSTATUS 0x100 -#define CSR_SIE 0x104 -#define CSR_STVEC 0x105 -#define CSR_SSCRATCH 0x140 -#define CSR_SEPC 0x141 -#define CSR_SCAUSE 0x142 -#define CSR_SBADADDR 0x143 -#define CSR_SIP 0x144 -#define CSR_SPTBR 0x180 -#define CSR_MSTATUS 0x300 -#define CSR_MISA 0x301 -#define CSR_MEDELEG 0x302 -#define CSR_MIDELEG 0x303 -#define CSR_MIE 0x304 -#define CSR_MTVEC 0x305 -#define CSR_MCOUNTEREN 0x306 -#define CSR_MSCRATCH 0x340 -#define CSR_MEPC 0x341 -#define CSR_MCAUSE 0x342 -#define CSR_MBADADDR 0x343 -#define CSR_MIP 0x344 -#define CSR_TSELECT 0x7a0 -#define CSR_TDATA1 0x7a1 -#define CSR_TDATA2 0x7a2 -#define CSR_TDATA3 0x7a3 -#define CSR_DCSR 0x7b0 -#define CSR_DPC 0x7b1 -#define CSR_DSCRATCH 0x7b2 -#define CSR_MCYCLE 0xb00 -#define CSR_MINSTRET 0xb02 -#define CSR_MHPMCOUNTER3 0xb03 -#define CSR_MHPMCOUNTER4 0xb04 -#define CSR_MHPMCOUNTER5 0xb05 -#define CSR_MHPMCOUNTER6 0xb06 -#define CSR_MHPMCOUNTER7 0xb07 -#define CSR_MHPMCOUNTER8 0xb08 -#define CSR_MHPMCOUNTER9 0xb09 -#define CSR_MHPMCOUNTER10 0xb0a -#define CSR_MHPMCOUNTER11 0xb0b -#define CSR_MHPMCOUNTER12 0xb0c -#define CSR_MHPMCOUNTER13 0xb0d -#define CSR_MHPMCOUNTER14 0xb0e -#define CSR_MHPMCOUNTER15 0xb0f -#define CSR_MHPMCOUNTER16 0xb10 -#define CSR_MHPMCOUNTER17 0xb11 -#define CSR_MHPMCOUNTER18 0xb12 -#define CSR_MHPMCOUNTER19 0xb13 -#define CSR_MHPMCOUNTER20 0xb14 -#define CSR_MHPMCOUNTER21 0xb15 -#define CSR_MHPMCOUNTER22 0xb16 -#define CSR_MHPMCOUNTER23 0xb17 -#define CSR_MHPMCOUNTER24 0xb18 -#define CSR_MHPMCOUNTER25 0xb19 -#define CSR_MHPMCOUNTER26 0xb1a -#define CSR_MHPMCOUNTER27 0xb1b -#define CSR_MHPMCOUNTER28 0xb1c -#define CSR_MHPMCOUNTER29 0xb1d -#define CSR_MHPMCOUNTER30 0xb1e -#define CSR_MHPMCOUNTER31 0xb1f -#define CSR_MUCOUNTEREN 0x320 -#define CSR_MSCOUNTEREN 0x321 -#define CSR_MHPMEVENT3 0x323 -#define CSR_MHPMEVENT4 0x324 -#define CSR_MHPMEVENT5 0x325 -#define CSR_MHPMEVENT6 0x326 -#define CSR_MHPMEVENT7 0x327 -#define CSR_MHPMEVENT8 0x328 -#define CSR_MHPMEVENT9 0x329 -#define CSR_MHPMEVENT10 0x32a -#define CSR_MHPMEVENT11 0x32b -#define CSR_MHPMEVENT12 0x32c -#define CSR_MHPMEVENT13 0x32d -#define CSR_MHPMEVENT14 0x32e -#define CSR_MHPMEVENT15 0x32f -#define CSR_MHPMEVENT16 0x330 -#define CSR_MHPMEVENT17 0x331 -#define CSR_MHPMEVENT18 0x332 -#define CSR_MHPMEVENT19 0x333 -#define CSR_MHPMEVENT20 0x334 -#define CSR_MHPMEVENT21 0x335 -#define CSR_MHPMEVENT22 0x336 -#define CSR_MHPMEVENT23 0x337 -#define CSR_MHPMEVENT24 0x338 -#define CSR_MHPMEVENT25 0x339 -#define CSR_MHPMEVENT26 0x33a -#define CSR_MHPMEVENT27 0x33b -#define CSR_MHPMEVENT28 0x33c -#define CSR_MHPMEVENT29 0x33d -#define CSR_MHPMEVENT30 0x33e -#define CSR_MHPMEVENT31 0x33f -#define CSR_MVENDORID 0xf11 -#define CSR_MARCHID 0xf12 -#define CSR_MIMPID 0xf13 -#define CSR_MHARTID 0xf14 -#define CSR_CYCLEH 0xc80 -#define CSR_TIMEH 0xc81 -#define CSR_INSTRETH 0xc82 -#define CSR_HPMCOUNTER3H 0xc83 -#define CSR_HPMCOUNTER4H 0xc84 -#define CSR_HPMCOUNTER5H 0xc85 -#define CSR_HPMCOUNTER6H 0xc86 -#define CSR_HPMCOUNTER7H 0xc87 -#define CSR_HPMCOUNTER8H 0xc88 -#define CSR_HPMCOUNTER9H 0xc89 -#define CSR_HPMCOUNTER10H 0xc8a -#define CSR_HPMCOUNTER11H 0xc8b -#define CSR_HPMCOUNTER12H 0xc8c -#define CSR_HPMCOUNTER13H 0xc8d -#define CSR_HPMCOUNTER14H 0xc8e -#define CSR_HPMCOUNTER15H 0xc8f -#define CSR_HPMCOUNTER16H 0xc90 -#define CSR_HPMCOUNTER17H 0xc91 -#define CSR_HPMCOUNTER18H 0xc92 -#define CSR_HPMCOUNTER19H 0xc93 -#define CSR_HPMCOUNTER20H 0xc94 -#define CSR_HPMCOUNTER21H 0xc95 -#define CSR_HPMCOUNTER22H 0xc96 -#define CSR_HPMCOUNTER23H 0xc97 -#define CSR_HPMCOUNTER24H 0xc98 -#define CSR_HPMCOUNTER25H 0xc99 -#define CSR_HPMCOUNTER26H 0xc9a -#define CSR_HPMCOUNTER27H 0xc9b -#define CSR_HPMCOUNTER28H 0xc9c -#define CSR_HPMCOUNTER29H 0xc9d -#define CSR_HPMCOUNTER30H 0xc9e -#define CSR_HPMCOUNTER31H 0xc9f -#define CSR_MCYCLEH 0xb80 -#define CSR_MINSTRETH 0xb82 -#define CSR_MHPMCOUNTER3H 0xb83 -#define CSR_MHPMCOUNTER4H 0xb84 -#define CSR_MHPMCOUNTER5H 0xb85 -#define CSR_MHPMCOUNTER6H 0xb86 -#define CSR_MHPMCOUNTER7H 0xb87 -#define CSR_MHPMCOUNTER8H 0xb88 -#define CSR_MHPMCOUNTER9H 0xb89 -#define CSR_MHPMCOUNTER10H 0xb8a -#define CSR_MHPMCOUNTER11H 0xb8b -#define CSR_MHPMCOUNTER12H 0xb8c -#define CSR_MHPMCOUNTER13H 0xb8d -#define CSR_MHPMCOUNTER14H 0xb8e -#define CSR_MHPMCOUNTER15H 0xb8f -#define CSR_MHPMCOUNTER16H 0xb90 -#define CSR_MHPMCOUNTER17H 0xb91 -#define CSR_MHPMCOUNTER18H 0xb92 -#define CSR_MHPMCOUNTER19H 0xb93 -#define CSR_MHPMCOUNTER20H 0xb94 -#define CSR_MHPMCOUNTER21H 0xb95 -#define CSR_MHPMCOUNTER22H 0xb96 -#define CSR_MHPMCOUNTER23H 0xb97 -#define CSR_MHPMCOUNTER24H 0xb98 -#define CSR_MHPMCOUNTER25H 0xb99 -#define CSR_MHPMCOUNTER26H 0xb9a -#define CSR_MHPMCOUNTER27H 0xb9b -#define CSR_MHPMCOUNTER28H 0xb9c -#define CSR_MHPMCOUNTER29H 0xb9d -#define CSR_MHPMCOUNTER30H 0xb9e -#define CSR_MHPMCOUNTER31H 0xb9f - -#define CSR_MTVT 0x307 -#define CSR_MNXTI 0x345 - -#define CSR_MCOUNTINHIBIT 0x320 - -#define CSR_MNVEC 0x7C3 - -#define CSR_MTVT2 0x7EC -#define CSR_JALMNXTI 0x7ED -#define CSR_PUSHMCAUSE 0x7EE -#define CSR_PUSHMEPC 0x7EF -#define CSR_PUSHMSUBM 0x7EB - -#define CSR_WFE 0x810 -#define CSR_SLEEPVALUE 0x811 -#define CSR_TXEVT 0x812 - -#define CSR_MMISC_CTL 0x7d0 -#define CSR_MSUBM 0x7c4 - -#define CAUSE_MISALIGNED_FETCH 0x0 -#define CAUSE_FAULT_FETCH 0x1 -#define CAUSE_ILLEGAL_INSTRUCTION 0x2 -#define CAUSE_BREAKPOINT 0x3 -#define CAUSE_MISALIGNED_LOAD 0x4 -#define CAUSE_FAULT_LOAD 0x5 -#define CAUSE_MISALIGNED_STORE 0x6 -#define CAUSE_FAULT_STORE 0x7 -#define CAUSE_USER_ECALL 0x8 -#define CAUSE_SUPERVISOR_ECALL 0x9 -#define CAUSE_HYPERVISOR_ECALL 0xa -#define CAUSE_MACHINE_ECALL 0xb -#define CAUSE_INSTRUCTION_PAGE_FAULT 0xc -#define CAUSE_LOAD_PAGE_FAULT 0xd -#define CAUSE_STORE_AMO_PAGE_FAULT 0xf -#endif -#ifdef DECLARE_INSN -DECLARE_INSN(beq, MATCH_BEQ, MASK_BEQ) -DECLARE_INSN(bne, MATCH_BNE, MASK_BNE) -DECLARE_INSN(blt, MATCH_BLT, MASK_BLT) -DECLARE_INSN(bge, MATCH_BGE, MASK_BGE) -DECLARE_INSN(bltu, MATCH_BLTU, MASK_BLTU) -DECLARE_INSN(bgeu, MATCH_BGEU, MASK_BGEU) -DECLARE_INSN(jalr, MATCH_JALR, MASK_JALR) -DECLARE_INSN(jal, MATCH_JAL, MASK_JAL) -DECLARE_INSN(lui, MATCH_LUI, MASK_LUI) -DECLARE_INSN(auipc, MATCH_AUIPC, MASK_AUIPC) -DECLARE_INSN(addi, MATCH_ADDI, MASK_ADDI) -DECLARE_INSN(slli, MATCH_SLLI, MASK_SLLI) -DECLARE_INSN(slti, MATCH_SLTI, MASK_SLTI) -DECLARE_INSN(sltiu, MATCH_SLTIU, MASK_SLTIU) -DECLARE_INSN(xori, MATCH_XORI, MASK_XORI) -DECLARE_INSN(srli, MATCH_SRLI, MASK_SRLI) -DECLARE_INSN(srai, MATCH_SRAI, MASK_SRAI) -DECLARE_INSN(ori, MATCH_ORI, MASK_ORI) -DECLARE_INSN(andi, MATCH_ANDI, MASK_ANDI) -DECLARE_INSN(add, MATCH_ADD, MASK_ADD) -DECLARE_INSN(sub, MATCH_SUB, MASK_SUB) -DECLARE_INSN(sll, MATCH_SLL, MASK_SLL) -DECLARE_INSN(slt, MATCH_SLT, MASK_SLT) -DECLARE_INSN(sltu, MATCH_SLTU, MASK_SLTU) -DECLARE_INSN(xor, MATCH_XOR, MASK_XOR) -DECLARE_INSN(srl, MATCH_SRL, MASK_SRL) -DECLARE_INSN(sra, MATCH_SRA, MASK_SRA) -DECLARE_INSN(or, MATCH_OR, MASK_OR) -DECLARE_INSN(and, MATCH_AND, MASK_AND) -DECLARE_INSN(addiw, MATCH_ADDIW, MASK_ADDIW) -DECLARE_INSN(slliw, MATCH_SLLIW, MASK_SLLIW) -DECLARE_INSN(srliw, MATCH_SRLIW, MASK_SRLIW) -DECLARE_INSN(sraiw, MATCH_SRAIW, MASK_SRAIW) -DECLARE_INSN(addw, MATCH_ADDW, MASK_ADDW) -DECLARE_INSN(subw, MATCH_SUBW, MASK_SUBW) -DECLARE_INSN(sllw, MATCH_SLLW, MASK_SLLW) -DECLARE_INSN(srlw, MATCH_SRLW, MASK_SRLW) -DECLARE_INSN(sraw, MATCH_SRAW, MASK_SRAW) -DECLARE_INSN(lb, MATCH_LB, MASK_LB) -DECLARE_INSN(lh, MATCH_LH, MASK_LH) -DECLARE_INSN(lw, MATCH_LW, MASK_LW) -DECLARE_INSN(ld, MATCH_LD, MASK_LD) -DECLARE_INSN(lbu, MATCH_LBU, MASK_LBU) -DECLARE_INSN(lhu, MATCH_LHU, MASK_LHU) -DECLARE_INSN(lwu, MATCH_LWU, MASK_LWU) -DECLARE_INSN(sb, MATCH_SB, MASK_SB) -DECLARE_INSN(sh, MATCH_SH, MASK_SH) -DECLARE_INSN(sw, MATCH_SW, MASK_SW) -DECLARE_INSN(sd, MATCH_SD, MASK_SD) -DECLARE_INSN(fence, MATCH_FENCE, MASK_FENCE) -DECLARE_INSN(fence_i, MATCH_FENCE_I, MASK_FENCE_I) -DECLARE_INSN(mul, MATCH_MUL, MASK_MUL) -DECLARE_INSN(mulh, MATCH_MULH, MASK_MULH) -DECLARE_INSN(mulhsu, MATCH_MULHSU, MASK_MULHSU) -DECLARE_INSN(mulhu, MATCH_MULHU, MASK_MULHU) -DECLARE_INSN(div, MATCH_DIV, MASK_DIV) -DECLARE_INSN(divu, MATCH_DIVU, MASK_DIVU) -DECLARE_INSN(rem, MATCH_REM, MASK_REM) -DECLARE_INSN(remu, MATCH_REMU, MASK_REMU) -DECLARE_INSN(mulw, MATCH_MULW, MASK_MULW) -DECLARE_INSN(divw, MATCH_DIVW, MASK_DIVW) -DECLARE_INSN(divuw, MATCH_DIVUW, MASK_DIVUW) -DECLARE_INSN(remw, MATCH_REMW, MASK_REMW) -DECLARE_INSN(remuw, MATCH_REMUW, MASK_REMUW) -DECLARE_INSN(amoadd_w, MATCH_AMOADD_W, MASK_AMOADD_W) -DECLARE_INSN(amoxor_w, MATCH_AMOXOR_W, MASK_AMOXOR_W) -DECLARE_INSN(amoor_w, MATCH_AMOOR_W, MASK_AMOOR_W) -DECLARE_INSN(amoand_w, MATCH_AMOAND_W, MASK_AMOAND_W) -DECLARE_INSN(amomin_w, MATCH_AMOMIN_W, MASK_AMOMIN_W) -DECLARE_INSN(amomax_w, MATCH_AMOMAX_W, MASK_AMOMAX_W) -DECLARE_INSN(amominu_w, MATCH_AMOMINU_W, MASK_AMOMINU_W) -DECLARE_INSN(amomaxu_w, MATCH_AMOMAXU_W, MASK_AMOMAXU_W) -DECLARE_INSN(amoswap_w, MATCH_AMOSWAP_W, MASK_AMOSWAP_W) -DECLARE_INSN(lr_w, MATCH_LR_W, MASK_LR_W) -DECLARE_INSN(sc_w, MATCH_SC_W, MASK_SC_W) -DECLARE_INSN(amoadd_d, MATCH_AMOADD_D, MASK_AMOADD_D) -DECLARE_INSN(amoxor_d, MATCH_AMOXOR_D, MASK_AMOXOR_D) -DECLARE_INSN(amoor_d, MATCH_AMOOR_D, MASK_AMOOR_D) -DECLARE_INSN(amoand_d, MATCH_AMOAND_D, MASK_AMOAND_D) -DECLARE_INSN(amomin_d, MATCH_AMOMIN_D, MASK_AMOMIN_D) -DECLARE_INSN(amomax_d, MATCH_AMOMAX_D, MASK_AMOMAX_D) -DECLARE_INSN(amominu_d, MATCH_AMOMINU_D, MASK_AMOMINU_D) -DECLARE_INSN(amomaxu_d, MATCH_AMOMAXU_D, MASK_AMOMAXU_D) -DECLARE_INSN(amoswap_d, MATCH_AMOSWAP_D, MASK_AMOSWAP_D) -DECLARE_INSN(lr_d, MATCH_LR_D, MASK_LR_D) -DECLARE_INSN(sc_d, MATCH_SC_D, MASK_SC_D) -DECLARE_INSN(ecall, MATCH_ECALL, MASK_ECALL) -DECLARE_INSN(ebreak, MATCH_EBREAK, MASK_EBREAK) -DECLARE_INSN(uret, MATCH_URET, MASK_URET) -DECLARE_INSN(sret, MATCH_SRET, MASK_SRET) -DECLARE_INSN(hret, MATCH_HRET, MASK_HRET) -DECLARE_INSN(mret, MATCH_MRET, MASK_MRET) -DECLARE_INSN(dret, MATCH_DRET, MASK_DRET) -DECLARE_INSN(sfence_vm, MATCH_SFENCE_VM, MASK_SFENCE_VM) -DECLARE_INSN(wfi, MATCH_WFI, MASK_WFI) -DECLARE_INSN(csrrw, MATCH_CSRRW, MASK_CSRRW) -DECLARE_INSN(csrrs, MATCH_CSRRS, MASK_CSRRS) -DECLARE_INSN(csrrc, MATCH_CSRRC, MASK_CSRRC) -DECLARE_INSN(csrrwi, MATCH_CSRRWI, MASK_CSRRWI) -DECLARE_INSN(csrrsi, MATCH_CSRRSI, MASK_CSRRSI) -DECLARE_INSN(csrrci, MATCH_CSRRCI, MASK_CSRRCI) -DECLARE_INSN(fadd_s, MATCH_FADD_S, MASK_FADD_S) -DECLARE_INSN(fsub_s, MATCH_FSUB_S, MASK_FSUB_S) -DECLARE_INSN(fmul_s, MATCH_FMUL_S, MASK_FMUL_S) -DECLARE_INSN(fdiv_s, MATCH_FDIV_S, MASK_FDIV_S) -DECLARE_INSN(fsgnj_s, MATCH_FSGNJ_S, MASK_FSGNJ_S) -DECLARE_INSN(fsgnjn_s, MATCH_FSGNJN_S, MASK_FSGNJN_S) -DECLARE_INSN(fsgnjx_s, MATCH_FSGNJX_S, MASK_FSGNJX_S) -DECLARE_INSN(fmin_s, MATCH_FMIN_S, MASK_FMIN_S) -DECLARE_INSN(fmax_s, MATCH_FMAX_S, MASK_FMAX_S) -DECLARE_INSN(fsqrt_s, MATCH_FSQRT_S, MASK_FSQRT_S) -DECLARE_INSN(fadd_d, MATCH_FADD_D, MASK_FADD_D) -DECLARE_INSN(fsub_d, MATCH_FSUB_D, MASK_FSUB_D) -DECLARE_INSN(fmul_d, MATCH_FMUL_D, MASK_FMUL_D) -DECLARE_INSN(fdiv_d, MATCH_FDIV_D, MASK_FDIV_D) -DECLARE_INSN(fsgnj_d, MATCH_FSGNJ_D, MASK_FSGNJ_D) -DECLARE_INSN(fsgnjn_d, MATCH_FSGNJN_D, MASK_FSGNJN_D) -DECLARE_INSN(fsgnjx_d, MATCH_FSGNJX_D, MASK_FSGNJX_D) -DECLARE_INSN(fmin_d, MATCH_FMIN_D, MASK_FMIN_D) -DECLARE_INSN(fmax_d, MATCH_FMAX_D, MASK_FMAX_D) -DECLARE_INSN(fcvt_s_d, MATCH_FCVT_S_D, MASK_FCVT_S_D) -DECLARE_INSN(fcvt_d_s, MATCH_FCVT_D_S, MASK_FCVT_D_S) -DECLARE_INSN(fsqrt_d, MATCH_FSQRT_D, MASK_FSQRT_D) -DECLARE_INSN(fle_s, MATCH_FLE_S, MASK_FLE_S) -DECLARE_INSN(flt_s, MATCH_FLT_S, MASK_FLT_S) -DECLARE_INSN(feq_s, MATCH_FEQ_S, MASK_FEQ_S) -DECLARE_INSN(fle_d, MATCH_FLE_D, MASK_FLE_D) -DECLARE_INSN(flt_d, MATCH_FLT_D, MASK_FLT_D) -DECLARE_INSN(feq_d, MATCH_FEQ_D, MASK_FEQ_D) -DECLARE_INSN(fcvt_w_s, MATCH_FCVT_W_S, MASK_FCVT_W_S) -DECLARE_INSN(fcvt_wu_s, MATCH_FCVT_WU_S, MASK_FCVT_WU_S) -DECLARE_INSN(fcvt_l_s, MATCH_FCVT_L_S, MASK_FCVT_L_S) -DECLARE_INSN(fcvt_lu_s, MATCH_FCVT_LU_S, MASK_FCVT_LU_S) -DECLARE_INSN(fmv_x_s, MATCH_FMV_X_S, MASK_FMV_X_S) -DECLARE_INSN(fclass_s, MATCH_FCLASS_S, MASK_FCLASS_S) -DECLARE_INSN(fcvt_w_d, MATCH_FCVT_W_D, MASK_FCVT_W_D) -DECLARE_INSN(fcvt_wu_d, MATCH_FCVT_WU_D, MASK_FCVT_WU_D) -DECLARE_INSN(fcvt_l_d, MATCH_FCVT_L_D, MASK_FCVT_L_D) -DECLARE_INSN(fcvt_lu_d, MATCH_FCVT_LU_D, MASK_FCVT_LU_D) -DECLARE_INSN(fmv_x_d, MATCH_FMV_X_D, MASK_FMV_X_D) -DECLARE_INSN(fclass_d, MATCH_FCLASS_D, MASK_FCLASS_D) -DECLARE_INSN(fcvt_s_w, MATCH_FCVT_S_W, MASK_FCVT_S_W) -DECLARE_INSN(fcvt_s_wu, MATCH_FCVT_S_WU, MASK_FCVT_S_WU) -DECLARE_INSN(fcvt_s_l, MATCH_FCVT_S_L, MASK_FCVT_S_L) -DECLARE_INSN(fcvt_s_lu, MATCH_FCVT_S_LU, MASK_FCVT_S_LU) -DECLARE_INSN(fmv_s_x, MATCH_FMV_S_X, MASK_FMV_S_X) -DECLARE_INSN(fcvt_d_w, MATCH_FCVT_D_W, MASK_FCVT_D_W) -DECLARE_INSN(fcvt_d_wu, MATCH_FCVT_D_WU, MASK_FCVT_D_WU) -DECLARE_INSN(fcvt_d_l, MATCH_FCVT_D_L, MASK_FCVT_D_L) -DECLARE_INSN(fcvt_d_lu, MATCH_FCVT_D_LU, MASK_FCVT_D_LU) -DECLARE_INSN(fmv_d_x, MATCH_FMV_D_X, MASK_FMV_D_X) -DECLARE_INSN(flw, MATCH_FLW, MASK_FLW) -DECLARE_INSN(fld, MATCH_FLD, MASK_FLD) -DECLARE_INSN(fsw, MATCH_FSW, MASK_FSW) -DECLARE_INSN(fsd, MATCH_FSD, MASK_FSD) -DECLARE_INSN(fmadd_s, MATCH_FMADD_S, MASK_FMADD_S) -DECLARE_INSN(fmsub_s, MATCH_FMSUB_S, MASK_FMSUB_S) -DECLARE_INSN(fnmsub_s, MATCH_FNMSUB_S, MASK_FNMSUB_S) -DECLARE_INSN(fnmadd_s, MATCH_FNMADD_S, MASK_FNMADD_S) -DECLARE_INSN(fmadd_d, MATCH_FMADD_D, MASK_FMADD_D) -DECLARE_INSN(fmsub_d, MATCH_FMSUB_D, MASK_FMSUB_D) -DECLARE_INSN(fnmsub_d, MATCH_FNMSUB_D, MASK_FNMSUB_D) -DECLARE_INSN(fnmadd_d, MATCH_FNMADD_D, MASK_FNMADD_D) -DECLARE_INSN(c_nop, MATCH_C_NOP, MASK_C_NOP) -DECLARE_INSN(c_addi16sp, MATCH_C_ADDI16SP, MASK_C_ADDI16SP) -DECLARE_INSN(c_jr, MATCH_C_JR, MASK_C_JR) -DECLARE_INSN(c_jalr, MATCH_C_JALR, MASK_C_JALR) -DECLARE_INSN(c_ebreak, MATCH_C_EBREAK, MASK_C_EBREAK) -DECLARE_INSN(c_ld, MATCH_C_LD, MASK_C_LD) -DECLARE_INSN(c_sd, MATCH_C_SD, MASK_C_SD) -DECLARE_INSN(c_addiw, MATCH_C_ADDIW, MASK_C_ADDIW) -DECLARE_INSN(c_ldsp, MATCH_C_LDSP, MASK_C_LDSP) -DECLARE_INSN(c_sdsp, MATCH_C_SDSP, MASK_C_SDSP) -DECLARE_INSN(c_addi4spn, MATCH_C_ADDI4SPN, MASK_C_ADDI4SPN) -DECLARE_INSN(c_fld, MATCH_C_FLD, MASK_C_FLD) -DECLARE_INSN(c_lw, MATCH_C_LW, MASK_C_LW) -DECLARE_INSN(c_flw, MATCH_C_FLW, MASK_C_FLW) -DECLARE_INSN(c_fsd, MATCH_C_FSD, MASK_C_FSD) -DECLARE_INSN(c_sw, MATCH_C_SW, MASK_C_SW) -DECLARE_INSN(c_fsw, MATCH_C_FSW, MASK_C_FSW) -DECLARE_INSN(c_addi, MATCH_C_ADDI, MASK_C_ADDI) -DECLARE_INSN(c_jal, MATCH_C_JAL, MASK_C_JAL) -DECLARE_INSN(c_li, MATCH_C_LI, MASK_C_LI) -DECLARE_INSN(c_lui, MATCH_C_LUI, MASK_C_LUI) -DECLARE_INSN(c_srli, MATCH_C_SRLI, MASK_C_SRLI) -DECLARE_INSN(c_srai, MATCH_C_SRAI, MASK_C_SRAI) -DECLARE_INSN(c_andi, MATCH_C_ANDI, MASK_C_ANDI) -DECLARE_INSN(c_sub, MATCH_C_SUB, MASK_C_SUB) -DECLARE_INSN(c_xor, MATCH_C_XOR, MASK_C_XOR) -DECLARE_INSN(c_or, MATCH_C_OR, MASK_C_OR) -DECLARE_INSN(c_and, MATCH_C_AND, MASK_C_AND) -DECLARE_INSN(c_subw, MATCH_C_SUBW, MASK_C_SUBW) -DECLARE_INSN(c_addw, MATCH_C_ADDW, MASK_C_ADDW) -DECLARE_INSN(c_j, MATCH_C_J, MASK_C_J) -DECLARE_INSN(c_beqz, MATCH_C_BEQZ, MASK_C_BEQZ) -DECLARE_INSN(c_bnez, MATCH_C_BNEZ, MASK_C_BNEZ) -DECLARE_INSN(c_slli, MATCH_C_SLLI, MASK_C_SLLI) -DECLARE_INSN(c_fldsp, MATCH_C_FLDSP, MASK_C_FLDSP) -DECLARE_INSN(c_lwsp, MATCH_C_LWSP, MASK_C_LWSP) -DECLARE_INSN(c_flwsp, MATCH_C_FLWSP, MASK_C_FLWSP) -DECLARE_INSN(c_mv, MATCH_C_MV, MASK_C_MV) -DECLARE_INSN(c_add, MATCH_C_ADD, MASK_C_ADD) -DECLARE_INSN(c_fsdsp, MATCH_C_FSDSP, MASK_C_FSDSP) -DECLARE_INSN(c_swsp, MATCH_C_SWSP, MASK_C_SWSP) -DECLARE_INSN(c_fswsp, MATCH_C_FSWSP, MASK_C_FSWSP) -DECLARE_INSN(custom0, MATCH_CUSTOM0, MASK_CUSTOM0) -DECLARE_INSN(custom0_rs1, MATCH_CUSTOM0_RS1, MASK_CUSTOM0_RS1) -DECLARE_INSN(custom0_rs1_rs2, MATCH_CUSTOM0_RS1_RS2, MASK_CUSTOM0_RS1_RS2) -DECLARE_INSN(custom0_rd, MATCH_CUSTOM0_RD, MASK_CUSTOM0_RD) -DECLARE_INSN(custom0_rd_rs1, MATCH_CUSTOM0_RD_RS1, MASK_CUSTOM0_RD_RS1) -DECLARE_INSN(custom0_rd_rs1_rs2, MATCH_CUSTOM0_RD_RS1_RS2, - MASK_CUSTOM0_RD_RS1_RS2) -DECLARE_INSN(custom1, MATCH_CUSTOM1, MASK_CUSTOM1) -DECLARE_INSN(custom1_rs1, MATCH_CUSTOM1_RS1, MASK_CUSTOM1_RS1) -DECLARE_INSN(custom1_rs1_rs2, MATCH_CUSTOM1_RS1_RS2, MASK_CUSTOM1_RS1_RS2) -DECLARE_INSN(custom1_rd, MATCH_CUSTOM1_RD, MASK_CUSTOM1_RD) -DECLARE_INSN(custom1_rd_rs1, MATCH_CUSTOM1_RD_RS1, MASK_CUSTOM1_RD_RS1) -DECLARE_INSN(custom1_rd_rs1_rs2, MATCH_CUSTOM1_RD_RS1_RS2, - MASK_CUSTOM1_RD_RS1_RS2) -DECLARE_INSN(custom2, MATCH_CUSTOM2, MASK_CUSTOM2) -DECLARE_INSN(custom2_rs1, MATCH_CUSTOM2_RS1, MASK_CUSTOM2_RS1) -DECLARE_INSN(custom2_rs1_rs2, MATCH_CUSTOM2_RS1_RS2, MASK_CUSTOM2_RS1_RS2) -DECLARE_INSN(custom2_rd, MATCH_CUSTOM2_RD, MASK_CUSTOM2_RD) -DECLARE_INSN(custom2_rd_rs1, MATCH_CUSTOM2_RD_RS1, MASK_CUSTOM2_RD_RS1) -DECLARE_INSN(custom2_rd_rs1_rs2, MATCH_CUSTOM2_RD_RS1_RS2, - MASK_CUSTOM2_RD_RS1_RS2) -DECLARE_INSN(custom3, MATCH_CUSTOM3, MASK_CUSTOM3) -DECLARE_INSN(custom3_rs1, MATCH_CUSTOM3_RS1, MASK_CUSTOM3_RS1) -DECLARE_INSN(custom3_rs1_rs2, MATCH_CUSTOM3_RS1_RS2, MASK_CUSTOM3_RS1_RS2) -DECLARE_INSN(custom3_rd, MATCH_CUSTOM3_RD, MASK_CUSTOM3_RD) -DECLARE_INSN(custom3_rd_rs1, MATCH_CUSTOM3_RD_RS1, MASK_CUSTOM3_RD_RS1) -DECLARE_INSN(custom3_rd_rs1_rs2, MATCH_CUSTOM3_RD_RS1_RS2, - MASK_CUSTOM3_RD_RS1_RS2) -#endif -#ifdef DECLARE_CSR -DECLARE_CSR(fflags, CSR_FFLAGS) -DECLARE_CSR(frm, CSR_FRM) -DECLARE_CSR(fcsr, CSR_FCSR) -DECLARE_CSR(cycle, CSR_CYCLE) -DECLARE_CSR(time, CSR_TIME) -DECLARE_CSR(instret, CSR_INSTRET) -DECLARE_CSR(hpmcounter3, CSR_HPMCOUNTER3) -DECLARE_CSR(hpmcounter4, CSR_HPMCOUNTER4) -DECLARE_CSR(hpmcounter5, CSR_HPMCOUNTER5) -DECLARE_CSR(hpmcounter6, CSR_HPMCOUNTER6) -DECLARE_CSR(hpmcounter7, CSR_HPMCOUNTER7) -DECLARE_CSR(hpmcounter8, CSR_HPMCOUNTER8) -DECLARE_CSR(hpmcounter9, CSR_HPMCOUNTER9) -DECLARE_CSR(hpmcounter10, CSR_HPMCOUNTER10) -DECLARE_CSR(hpmcounter11, CSR_HPMCOUNTER11) -DECLARE_CSR(hpmcounter12, CSR_HPMCOUNTER12) -DECLARE_CSR(hpmcounter13, CSR_HPMCOUNTER13) -DECLARE_CSR(hpmcounter14, CSR_HPMCOUNTER14) -DECLARE_CSR(hpmcounter15, CSR_HPMCOUNTER15) -DECLARE_CSR(hpmcounter16, CSR_HPMCOUNTER16) -DECLARE_CSR(hpmcounter17, CSR_HPMCOUNTER17) -DECLARE_CSR(hpmcounter18, CSR_HPMCOUNTER18) -DECLARE_CSR(hpmcounter19, CSR_HPMCOUNTER19) -DECLARE_CSR(hpmcounter20, CSR_HPMCOUNTER20) -DECLARE_CSR(hpmcounter21, CSR_HPMCOUNTER21) -DECLARE_CSR(hpmcounter22, CSR_HPMCOUNTER22) -DECLARE_CSR(hpmcounter23, CSR_HPMCOUNTER23) -DECLARE_CSR(hpmcounter24, CSR_HPMCOUNTER24) -DECLARE_CSR(hpmcounter25, CSR_HPMCOUNTER25) -DECLARE_CSR(hpmcounter26, CSR_HPMCOUNTER26) -DECLARE_CSR(hpmcounter27, CSR_HPMCOUNTER27) -DECLARE_CSR(hpmcounter28, CSR_HPMCOUNTER28) -DECLARE_CSR(hpmcounter29, CSR_HPMCOUNTER29) -DECLARE_CSR(hpmcounter30, CSR_HPMCOUNTER30) -DECLARE_CSR(hpmcounter31, CSR_HPMCOUNTER31) -DECLARE_CSR(sstatus, CSR_SSTATUS) -DECLARE_CSR(sie, CSR_SIE) -DECLARE_CSR(stvec, CSR_STVEC) -DECLARE_CSR(sscratch, CSR_SSCRATCH) -DECLARE_CSR(sepc, CSR_SEPC) -DECLARE_CSR(scause, CSR_SCAUSE) -DECLARE_CSR(sbadaddr, CSR_SBADADDR) -DECLARE_CSR(sip, CSR_SIP) -DECLARE_CSR(sptbr, CSR_SPTBR) -DECLARE_CSR(mstatus, CSR_MSTATUS) -DECLARE_CSR(misa, CSR_MISA) -DECLARE_CSR(medeleg, CSR_MEDELEG) -DECLARE_CSR(mideleg, CSR_MIDELEG) -DECLARE_CSR(mie, CSR_MIE) -DECLARE_CSR(mtvec, CSR_MTVEC) -DECLARE_CSR(mscratch, CSR_MSCRATCH) -DECLARE_CSR(mepc, CSR_MEPC) -DECLARE_CSR(mcause, CSR_MCAUSE) -DECLARE_CSR(mbadaddr, CSR_MBADADDR) -DECLARE_CSR(mip, CSR_MIP) -DECLARE_CSR(tselect, CSR_TSELECT) -DECLARE_CSR(tdata1, CSR_TDATA1) -DECLARE_CSR(tdata2, CSR_TDATA2) -DECLARE_CSR(tdata3, CSR_TDATA3) -DECLARE_CSR(dcsr, CSR_DCSR) -DECLARE_CSR(dpc, CSR_DPC) -DECLARE_CSR(dscratch, CSR_DSCRATCH) -DECLARE_CSR(mcycle, CSR_MCYCLE) -DECLARE_CSR(minstret, CSR_MINSTRET) -DECLARE_CSR(mhpmcounter3, CSR_MHPMCOUNTER3) -DECLARE_CSR(mhpmcounter4, CSR_MHPMCOUNTER4) -DECLARE_CSR(mhpmcounter5, CSR_MHPMCOUNTER5) -DECLARE_CSR(mhpmcounter6, CSR_MHPMCOUNTER6) -DECLARE_CSR(mhpmcounter7, CSR_MHPMCOUNTER7) -DECLARE_CSR(mhpmcounter8, CSR_MHPMCOUNTER8) -DECLARE_CSR(mhpmcounter9, CSR_MHPMCOUNTER9) -DECLARE_CSR(mhpmcounter10, CSR_MHPMCOUNTER10) -DECLARE_CSR(mhpmcounter11, CSR_MHPMCOUNTER11) -DECLARE_CSR(mhpmcounter12, CSR_MHPMCOUNTER12) -DECLARE_CSR(mhpmcounter13, CSR_MHPMCOUNTER13) -DECLARE_CSR(mhpmcounter14, CSR_MHPMCOUNTER14) -DECLARE_CSR(mhpmcounter15, CSR_MHPMCOUNTER15) -DECLARE_CSR(mhpmcounter16, CSR_MHPMCOUNTER16) -DECLARE_CSR(mhpmcounter17, CSR_MHPMCOUNTER17) -DECLARE_CSR(mhpmcounter18, CSR_MHPMCOUNTER18) -DECLARE_CSR(mhpmcounter19, CSR_MHPMCOUNTER19) -DECLARE_CSR(mhpmcounter20, CSR_MHPMCOUNTER20) -DECLARE_CSR(mhpmcounter21, CSR_MHPMCOUNTER21) -DECLARE_CSR(mhpmcounter22, CSR_MHPMCOUNTER22) -DECLARE_CSR(mhpmcounter23, CSR_MHPMCOUNTER23) -DECLARE_CSR(mhpmcounter24, CSR_MHPMCOUNTER24) -DECLARE_CSR(mhpmcounter25, CSR_MHPMCOUNTER25) -DECLARE_CSR(mhpmcounter26, CSR_MHPMCOUNTER26) -DECLARE_CSR(mhpmcounter27, CSR_MHPMCOUNTER27) -DECLARE_CSR(mhpmcounter28, CSR_MHPMCOUNTER28) -DECLARE_CSR(mhpmcounter29, CSR_MHPMCOUNTER29) -DECLARE_CSR(mhpmcounter30, CSR_MHPMCOUNTER30) -DECLARE_CSR(mhpmcounter31, CSR_MHPMCOUNTER31) -DECLARE_CSR(mucounteren, CSR_MUCOUNTEREN) -DECLARE_CSR(mscounteren, CSR_MSCOUNTEREN) -DECLARE_CSR(mhpmevent3, CSR_MHPMEVENT3) -DECLARE_CSR(mhpmevent4, CSR_MHPMEVENT4) -DECLARE_CSR(mhpmevent5, CSR_MHPMEVENT5) -DECLARE_CSR(mhpmevent6, CSR_MHPMEVENT6) -DECLARE_CSR(mhpmevent7, CSR_MHPMEVENT7) -DECLARE_CSR(mhpmevent8, CSR_MHPMEVENT8) -DECLARE_CSR(mhpmevent9, CSR_MHPMEVENT9) -DECLARE_CSR(mhpmevent10, CSR_MHPMEVENT10) -DECLARE_CSR(mhpmevent11, CSR_MHPMEVENT11) -DECLARE_CSR(mhpmevent12, CSR_MHPMEVENT12) -DECLARE_CSR(mhpmevent13, CSR_MHPMEVENT13) -DECLARE_CSR(mhpmevent14, CSR_MHPMEVENT14) -DECLARE_CSR(mhpmevent15, CSR_MHPMEVENT15) -DECLARE_CSR(mhpmevent16, CSR_MHPMEVENT16) -DECLARE_CSR(mhpmevent17, CSR_MHPMEVENT17) -DECLARE_CSR(mhpmevent18, CSR_MHPMEVENT18) -DECLARE_CSR(mhpmevent19, CSR_MHPMEVENT19) -DECLARE_CSR(mhpmevent20, CSR_MHPMEVENT20) -DECLARE_CSR(mhpmevent21, CSR_MHPMEVENT21) -DECLARE_CSR(mhpmevent22, CSR_MHPMEVENT22) -DECLARE_CSR(mhpmevent23, CSR_MHPMEVENT23) -DECLARE_CSR(mhpmevent24, CSR_MHPMEVENT24) -DECLARE_CSR(mhpmevent25, CSR_MHPMEVENT25) -DECLARE_CSR(mhpmevent26, CSR_MHPMEVENT26) -DECLARE_CSR(mhpmevent27, CSR_MHPMEVENT27) -DECLARE_CSR(mhpmevent28, CSR_MHPMEVENT28) -DECLARE_CSR(mhpmevent29, CSR_MHPMEVENT29) -DECLARE_CSR(mhpmevent30, CSR_MHPMEVENT30) -DECLARE_CSR(mhpmevent31, CSR_MHPMEVENT31) -DECLARE_CSR(mvendorid, CSR_MVENDORID) -DECLARE_CSR(marchid, CSR_MARCHID) -DECLARE_CSR(mimpid, CSR_MIMPID) -DECLARE_CSR(mhartid, CSR_MHARTID) -DECLARE_CSR(cycleh, CSR_CYCLEH) -DECLARE_CSR(timeh, CSR_TIMEH) -DECLARE_CSR(instreth, CSR_INSTRETH) -DECLARE_CSR(hpmcounter3h, CSR_HPMCOUNTER3H) -DECLARE_CSR(hpmcounter4h, CSR_HPMCOUNTER4H) -DECLARE_CSR(hpmcounter5h, CSR_HPMCOUNTER5H) -DECLARE_CSR(hpmcounter6h, CSR_HPMCOUNTER6H) -DECLARE_CSR(hpmcounter7h, CSR_HPMCOUNTER7H) -DECLARE_CSR(hpmcounter8h, CSR_HPMCOUNTER8H) -DECLARE_CSR(hpmcounter9h, CSR_HPMCOUNTER9H) -DECLARE_CSR(hpmcounter10h, CSR_HPMCOUNTER10H) -DECLARE_CSR(hpmcounter11h, CSR_HPMCOUNTER11H) -DECLARE_CSR(hpmcounter12h, CSR_HPMCOUNTER12H) -DECLARE_CSR(hpmcounter13h, CSR_HPMCOUNTER13H) -DECLARE_CSR(hpmcounter14h, CSR_HPMCOUNTER14H) -DECLARE_CSR(hpmcounter15h, CSR_HPMCOUNTER15H) -DECLARE_CSR(hpmcounter16h, CSR_HPMCOUNTER16H) -DECLARE_CSR(hpmcounter17h, CSR_HPMCOUNTER17H) -DECLARE_CSR(hpmcounter18h, CSR_HPMCOUNTER18H) -DECLARE_CSR(hpmcounter19h, CSR_HPMCOUNTER19H) -DECLARE_CSR(hpmcounter20h, CSR_HPMCOUNTER20H) -DECLARE_CSR(hpmcounter21h, CSR_HPMCOUNTER21H) -DECLARE_CSR(hpmcounter22h, CSR_HPMCOUNTER22H) -DECLARE_CSR(hpmcounter23h, CSR_HPMCOUNTER23H) -DECLARE_CSR(hpmcounter24h, CSR_HPMCOUNTER24H) -DECLARE_CSR(hpmcounter25h, CSR_HPMCOUNTER25H) -DECLARE_CSR(hpmcounter26h, CSR_HPMCOUNTER26H) -DECLARE_CSR(hpmcounter27h, CSR_HPMCOUNTER27H) -DECLARE_CSR(hpmcounter28h, CSR_HPMCOUNTER28H) -DECLARE_CSR(hpmcounter29h, CSR_HPMCOUNTER29H) -DECLARE_CSR(hpmcounter30h, CSR_HPMCOUNTER30H) -DECLARE_CSR(hpmcounter31h, CSR_HPMCOUNTER31H) -DECLARE_CSR(mcycleh, CSR_MCYCLEH) -DECLARE_CSR(minstreth, CSR_MINSTRETH) -DECLARE_CSR(mhpmcounter3h, CSR_MHPMCOUNTER3H) -DECLARE_CSR(mhpmcounter4h, CSR_MHPMCOUNTER4H) -DECLARE_CSR(mhpmcounter5h, CSR_MHPMCOUNTER5H) -DECLARE_CSR(mhpmcounter6h, CSR_MHPMCOUNTER6H) -DECLARE_CSR(mhpmcounter7h, CSR_MHPMCOUNTER7H) -DECLARE_CSR(mhpmcounter8h, CSR_MHPMCOUNTER8H) -DECLARE_CSR(mhpmcounter9h, CSR_MHPMCOUNTER9H) -DECLARE_CSR(mhpmcounter10h, CSR_MHPMCOUNTER10H) -DECLARE_CSR(mhpmcounter11h, CSR_MHPMCOUNTER11H) -DECLARE_CSR(mhpmcounter12h, CSR_MHPMCOUNTER12H) -DECLARE_CSR(mhpmcounter13h, CSR_MHPMCOUNTER13H) -DECLARE_CSR(mhpmcounter14h, CSR_MHPMCOUNTER14H) -DECLARE_CSR(mhpmcounter15h, CSR_MHPMCOUNTER15H) -DECLARE_CSR(mhpmcounter16h, CSR_MHPMCOUNTER16H) -DECLARE_CSR(mhpmcounter17h, CSR_MHPMCOUNTER17H) -DECLARE_CSR(mhpmcounter18h, CSR_MHPMCOUNTER18H) -DECLARE_CSR(mhpmcounter19h, CSR_MHPMCOUNTER19H) -DECLARE_CSR(mhpmcounter20h, CSR_MHPMCOUNTER20H) -DECLARE_CSR(mhpmcounter21h, CSR_MHPMCOUNTER21H) -DECLARE_CSR(mhpmcounter22h, CSR_MHPMCOUNTER22H) -DECLARE_CSR(mhpmcounter23h, CSR_MHPMCOUNTER23H) -DECLARE_CSR(mhpmcounter24h, CSR_MHPMCOUNTER24H) -DECLARE_CSR(mhpmcounter25h, CSR_MHPMCOUNTER25H) -DECLARE_CSR(mhpmcounter26h, CSR_MHPMCOUNTER26H) -DECLARE_CSR(mhpmcounter27h, CSR_MHPMCOUNTER27H) -DECLARE_CSR(mhpmcounter28h, CSR_MHPMCOUNTER28H) -DECLARE_CSR(mhpmcounter29h, CSR_MHPMCOUNTER29H) -DECLARE_CSR(mhpmcounter30h, CSR_MHPMCOUNTER30H) -DECLARE_CSR(mhpmcounter31h, CSR_MHPMCOUNTER31H) -#endif -#ifdef DECLARE_CAUSE -DECLARE_CAUSE("misaligned fetch", CAUSE_MISALIGNED_FETCH) -DECLARE_CAUSE("fault fetch", CAUSE_FAULT_FETCH) -DECLARE_CAUSE("illegal instruction", CAUSE_ILLEGAL_INSTRUCTION) -DECLARE_CAUSE("breakpoint", CAUSE_BREAKPOINT) -DECLARE_CAUSE("misaligned load", CAUSE_MISALIGNED_LOAD) -DECLARE_CAUSE("fault load", CAUSE_FAULT_LOAD) -DECLARE_CAUSE("misaligned store", CAUSE_MISALIGNED_STORE) -DECLARE_CAUSE("fault store", CAUSE_FAULT_STORE) -DECLARE_CAUSE("user_ecall", CAUSE_USER_ECALL) -DECLARE_CAUSE("supervisor_ecall", CAUSE_SUPERVISOR_ECALL) -DECLARE_CAUSE("hypervisor_ecall", CAUSE_HYPERVISOR_ECALL) -DECLARE_CAUSE("machine_ecall", CAUSE_MACHINE_ECALL) -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.h deleted file mode 100644 index 238eacc3d2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.h +++ /dev/null @@ -1,73 +0,0 @@ -#ifndef _RV_PMP_H_ -#define _RV_PMP_H_ - -#define RV_PMP_ENTRY (8) - -#define ENTRY_FLAG_PERM_R (1 << 0) -#define ENTRY_FLAG_PERM_W (1 << 1) -#define ENTRY_FLAG_PERM_X (1 << 2) -#define ENTRY_FLAG_ADDR_OFF (0 << 3) -#define ENTRY_FLAG_ADDR_TOR (1 << 3) -#define ENTRY_FLAG_ADDR_NAPOT (3 << 3) -#define ENTRY_FLAG_ADDR_MASK (3 << 3) -#define ENTRY_FLAG_M_MODE_L (1 << 7) - -#define ENTRY_FLAG_SIZE (8) -#define ENTRY_FLAG_MASK (0xFF) - -#define ENTRY_IN_CFG_REG (__riscv_xlen / ENTRY_FLAG_SIZE) - -/* E907: the smallest granularity is 128B */ -/* C906: the smallest granularity is 4K */ -#define PMP_REG_SZ_128B (1 << 8) -#define PMP_REG_SZ_256B (1 << 9) -#define PMP_REG_SZ_512B (1 << 10) -#define PMP_REG_SZ_1K (1 << 11) -#define PMP_REG_SZ_2K (1 << 12) -#define PMP_REG_SZ_4K (1 << 12) -#define PMP_REG_SZ_8K (1 << 13) -#define PMP_REG_SZ_16K (1 << 14) -#define PMP_REG_SZ_32K (1 << 15) -#define PMP_REG_SZ_64K (1 << 16) -#define PMP_REG_SZ_128K (1 << 17) -#define PMP_REG_SZ_256K (1 << 18) -#define PMP_REG_SZ_512K (1 << 19) -#define PMP_REG_SZ_1M (1 << 20) -#define PMP_REG_SZ_2M (1 << 21) -#define PMP_REG_SZ_4M (1 << 22) -#define PMP_REG_SZ_8M (1 << 23) -#define PMP_REG_SZ_16M (1 << 24) -#define PMP_REG_SZ_32M (1 << 25) -#define PMP_REG_SZ_64M (1 << 26) -#define PMP_REG_SZ_128M (1 << 27) -#define PMP_REG_SZ_256M (1 << 28) -#define PMP_REG_SZ_512M (1 << 29) -#define PMP_REG_SZ_1G (1 << 30) -#define PMP_REG_SZ_1024M (PMP_REG_SZ_1G) - -typedef enum _pmp_status_type_ { - PMP_STATUS_OK = 0, - PMP_STATUS_BUSY, - PMP_STATUS_DENIED, - PMP_STATUS_INVALID, - PMP_STATUS_UNSUPPORTED, - PMP_STATUS_MAX = 0x7FFFFFFF -} pmp_status_type_e; - -typedef enum _addr_match_type_ { - PMP_ADDR_MATCH_OFF = 0, - PMP_ADDR_MATCH_TOR, - PMP_ADDR_MATCH_NA4, - PMP_ADDR_MATCH_NAPOT -} pmp_addr_match_type_e; - -typedef struct _pmp_config_entry { - uintptr_t entry_pa_base; - uintptr_t entry_pa_length; - uintptr_t entry_flag; -} pmp_config_entry_t; - -pmp_status_type_e rvpmp_fill_entry(const pmp_config_entry_t *entry, uintptr_t i, uintptr_t force); -pmp_status_type_e rvpmp_init(const pmp_config_entry_t *entry, uintptr_t n); - -#endif /* _RV_PMP_H_ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram_dv.ld deleted file mode 100644 index 6726215465..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram_dv.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 64K - itcm_memory (rx) : ORIGIN = 0x3eff0000, LENGTH = 64K - dtcm_memory (rx) : ORIGIN = 0x3f000000, LENGTH = 32K - ram_memory (!rx) : ORIGIN = 0x3f008000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/cpu_flags.cmake deleted file mode 100644 index 4c67fb5250..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/cpu_flags.cmake +++ /dev/null @@ -1,18 +0,0 @@ -# CPU_ARCH := RISCV -# MCPU := c906 -# MARCH := rv64gcvxtheadc -# MABI := lp64d - -SET(CPU_ARCH "RISCV") -SET(MCPU "c906") - -SET(MARCH "rv64imafdcv0p7_zfh_xtheadc") -SET(MABI "lp64d") - -list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU} -mcmodel=medany) -list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU} -mcmodel=medany) - -SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_fpga.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_ram.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/d0/bl808_ram_dv.ld) diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/interrupt.c deleted file mode 100644 index 3a60bfbe88..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/interrupt.c +++ /dev/null @@ -1,218 +0,0 @@ -#include -#include -#include -#include -#include "bl808_glb.h" -#include "irq_ctx.h" - -#define DUMP_ALL_REGS -#define DUMP_MCAUSE_INFO - -pFunc g_irqvector[IRQn_LAST] __attribute__((aligned(16))) = { NULL }; - -void Interrupt_Default_Handler(void) __attribute__((weak)); -void Interrupt_Default_Handler(void) -{ - /* un-handled external IRQ */ - MSG("Enter interrupt default handler\r\n"); -} - -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) -{ - if (irq < IRQn_LAST) { - g_irqvector[irq] = interruptFun; - } -} - -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) __attribute__((noreturn)); -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - MSG("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type()); - // clang-format off - MSG("mstatus = 0x%16llx, FS=%d, MPP=%d, MPIE=%d\n\r", regs[REG_INT_CTX_NDX], - (regs[REG_INT_CTX_NDX] >> 13) & 0x3, - (regs[REG_INT_CTX_NDX] >> 11) & 0x3, - (regs[REG_INT_CTX_NDX] >> 7) & 1); - MSG("mcause: %d, mtval = 0x%16llx, mepc = 0x%16llx\n\r\n\r", (cause & 0xf), val, regs[REG_EPC_NDX]); -#ifdef DUMP_MCAUSE_INFO -const char *mcause_str[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store/AMO address misaligned", - "Store/AMO access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "RSVD", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "RSVD", - "Store/AMO page fault" -}; - if ((cause & 0xf)) - MSG("%s\r\n\r\n", mcause_str[cause & 0xf]); -#endif - -#ifdef DUMP_ALL_REGS - MSG("ra = 0x%16llx ", regs[REG_RA]); MSG("sp = 0x%16llx ", regs[REG_SP]); MSG("gp = 0x%16llx ", regs[REG_GP]); - MSG("tp = 0x%16llx ", regs[REG_TP]); MSG("\n\r"); - - MSG("t0 = 0x%16llx ", regs[REG_T0]); MSG("t1 = 0x%16llx ", regs[REG_T1]); MSG("t2 = 0x%16llx ", regs[REG_T2]); - MSG("t3 = 0x%16llx ", regs[REG_T3]); MSG("\n\r"); - MSG("t4 = 0x%16llx ", regs[REG_T4]); MSG("t5 = 0x%16llx ", regs[REG_T5]); MSG("t6 = 0x%16llx ", regs[REG_T6]); - MSG("\n\r"); - - MSG("a0 = 0x%16llx ", regs[REG_A0]); MSG("a1 = 0x%16llx ", regs[REG_A1]); MSG("a2 = 0x%16llx ", regs[REG_A2]); - MSG("a3 = 0x%16llx ", regs[REG_A3]); MSG("\n\r"); - MSG("a4 = 0x%16llx ", regs[REG_A4]); MSG("a5 = 0x%16llx ", regs[REG_A5]); MSG("a6 = 0x%16llx ", regs[REG_A6]); - MSG("a7 = 0x%16llx ", regs[REG_A7]); MSG("\n\r"); - - MSG("s0 = 0x%16llx ", regs[REG_S0]); MSG("s1 = 0x%16llx ", regs[REG_S1]); MSG("s2 = 0x%16llx ", regs[REG_S2]); - MSG("s3 = 0x%16llx ", regs[REG_S3]); MSG("\n\r"); - MSG("s4 = 0x%16llx ", regs[REG_S4]); MSG("s5 = 0x%16llx ", regs[REG_S5]); MSG("s6 = 0x%16llx ", regs[REG_S6]); - MSG("s7 = 0x%16llx ", regs[REG_S7]); MSG("\n\r"); - MSG("s8 = 0x%16llx ", regs[REG_S8]); MSG("s9 = 0x%16llx ", regs[REG_S9]); MSG("s10 = 0x%16llx ", regs[REG_S10]); - MSG("s11 = 0x%16llx ", regs[REG_S11]); MSG("\n\r"); -#endif - // clang-format on - MSG("\n\r"); - - while (1) - ; -} - -static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - regs[REG_EPC_NDX] += 4; - __asm volatile("nop" :: - : "memory"); - - return 0; -} - -static exception_handler exception_handlers[RV_EXCEPTION_NUM] = { - exception_handler_default, /* 0: Instruction Address Misaligned */ - exception_handler_default, /* 1: Instruction Access Fault */ - exception_handler_default, /* 2: Illegal Instruction */ - exception_handler_default, /* 3: Breakpoint */ - exception_handler_default, /* 4: Load Address Misaligned */ - exception_handler_default, /* 5: Load Access Fault */ - exception_handler_default, /* 6: Store/AMO Address Misaligned */ - exception_handler_default, /* 7: Store/AMO Access Fault */ - exception_handler_default, /* 8: Environment Call from U-mode */ - exception_handler_default, /* 9: Environment Call from S-mode */ - exception_handler_default, /* 10: Environment Call from H-mode */ - exception_handler_ECALL_M, /* 11: Environment Call from M-mode */ - exception_handler_default, /* 12: Instruction Page Fault */ - exception_handler_default, /* 13: Load Page Fault */ - exception_handler_default, /* 14: Reserved */ - exception_handler_default, /* 15: Store/AMO Page Fault */ -}; - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler) -{ - exception_handler previous = NULL; - - if (RV_EXCEPTION_NUM > vec) { - previous = exception_handlers[vec]; - exception_handlers[vec] = handler; - } - - return previous; -} - -uintptr_t *trap_c(uintptr_t cause, uintptr_t *regs) -{ - uint32_t vec = 0; - uintptr_t tval = __get_MTVAL(); - - riscv_savefpu(regs); - - vec = cause & 0x3FF; - - if (RV_EXCEPTION_NUM > vec) { - exception_handlers[vec](cause, tval, regs); - } else { - while (1) - ; - } - - riscv_restorefpu(regs); - - return regs; -} - -/** - \brief enable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Enable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { - if (csi_vic_get_prio(irq_num) == 0) { - csi_vic_set_prio(irq_num, 1); - } - -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_enable_sirq(irq_num); -#else - csi_vic_enable_irq(irq_num); -#endif - } -} - -/** - \brief disable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Disable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_disable_sirq(irq_num); -#else - csi_vic_disable_irq(irq_num); -#endif - } -} - -/** - \brief Clear Pending Interrupt - \details Clear the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -void ATTR_TCM_SECTION CPU_Interrupt_Pending_Clear(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - return; - } else { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_clear_pending_irq(irq_num); -#else - csi_vic_clear_pending_irq(irq_num); -#endif - } -} - -void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - csi_vic_set_prio(IRQn, PreemptPriority); -} - -void System_Interrupt_Init(void) -{ - for (uintptr_t irq = 0; irq < IRQn_LAST; irq++) { - g_irqvector[irq] = Interrupt_Default_Handler; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.c deleted file mode 100644 index 048683937d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.c +++ /dev/null @@ -1,105 +0,0 @@ -#include "csi_core.h" -#include "bl808.h" -#include "bl808_clock.h" -#include "bl808_glb.h" -#include "bl808_ef_cfg.h" -#ifdef BOOTROM -#include "bflb_bootrom.h" -#endif - -#define BL808_B0 (0x0) -#define BL808_B1 (0x1) -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define SYSTEM_CLOCK (32000000UL) -uintptr_t g_system_clock = SYSTEM_CLOCK; - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ - -void System_BOR_Init(void) -{ - //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */}; - //HBN_Set_BOR_Cfg(&borCfg); -} - -void System_Core_Clock_Set(BL_System_Clock_Type type, uint32_t clock) -{ - Clock_Cfg_Type *pClk = (Clock_Cfg_Type *)SYS_CLOCK_CFG_ADDR; - - CHECK_PARAM(IS_BL_SYSTEM_CLOCK_TYPE(type)); - - if (type < BL_SYSTEM_CLOCK_MAX) { - pClk->systemClock[type] = clock; - pClk->magic = SYS_CLOCK_CFG_MAGIC; - } -} - -void System_Init(void) -{ - uintptr_t tmpVal = 0; -#ifdef DUALCORE - while ((BL_RD_WORD(IPC_SYNC_ADDR1) != IPC_SYNC_FLAG) || - (BL_RD_WORD(IPC_SYNC_ADDR2) != IPC_SYNC_FLAG)) { - // clang-format off - __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); - __NOP(); __NOP(); __NOP(); __NOP(); - // clang-format on - /* if cache is off, comment this and this api need to start load itcm*/ - // L1C_DCache_Invalid_By_Addr(IPC_SYNC_ADDR1, 8); - }; - /* clear this flags for system reboot */ - BL_WR_WORD(IPC_SYNC_ADDR1, 0x0); - BL_WR_WORD(IPC_SYNC_ADDR2, 0x0); -#endif - /* turn on cache to speed up boot sequence */ - csi_icache_enable(); - csi_dcache_enable(); - /* enable I/D Cache preload. */ - tmpVal = __get_MHINT(); - tmpVal |= (1 << 8) | (1 << 2); - /* clear AMR */ - tmpVal &= (~0x18); - __set_MHINT(tmpVal); - __DSB(); - - /* init bor for all platform */ - System_BOR_Init(); -} - -void System_Post_Init(void) -{ - /* fix amr setting */ - uintptr_t tmpVal = 0; - Efuse_Chip_Info_Type chip_info; - EF_Ctrl_Get_Chip_Info(&chip_info); - /* if not B0 enable AMR */ - if (chip_info.chipInfo != BL808_B0) { - tmpVal = __get_MHINT(); - tmpVal |= (1 << 3); - __set_MHINT(tmpVal); - } - - System_Interrupt_Init(); - - /* global IRQ enable */ - __enable_irq(); -} - -int32_t drv_get_cpu_id(void) -{ - return __get_MHARTID(); -} - -int32_t drv_get_cpu_freq(int32_t idx) -{ - return g_system_clock; -} - -#if defined(DUAL_CORE) -extern void Reset_Handler(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.h deleted file mode 100644 index 07e4e07efc..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/system_bl808.h +++ /dev/null @@ -1,23 +0,0 @@ -#ifndef __SYSTEM_BL808_H__ -#define __SYSTEM_BL808_H__ - -#define RV_EXCEPTION_NUM (16) -typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs); -typedef void (*pFunc)(void); - -extern void System_Interrupt_Init(void); -extern void CPU_Interrupt_Enable(uint32_t irq_num); -extern void CPU_Interrupt_Disable(uint32_t irq_num); -extern void CPU_Interrupt_Pending_Clear(uint32_t irq_num); -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); -extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler); - -void riscv_savefpu(uintptr_t *regs); -void riscv_restorefpu(const uintptr_t *regs); - -int32_t drv_get_cpu_id(void); -int32_t drv_get_cpu_freq(int32_t idx); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_flash.ld deleted file mode 100644 index eb99463384..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_flash.ld +++ /dev/null @@ -1,264 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - xip_memory (rx) : ORIGIN = 0xD8000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K - dtcm_memory (rx) : ORIGIN = 0x62024000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22050000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x62050000, LENGTH = 12K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - KEEP(*startup*.*o(*.text*)) - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for usb desc */ - . = ALIGN(4); - _usb_desc_start = .; - KEEP(*(usb_desc)) - . = ALIGN(4); - _usb_desc_end = .; - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl808_glb*.o* \ - *bl808_glb_gpio*.o* \ - *bl808_pds*.o* \ - *bl808_aon*.o* \ - *bl808_hbn*.o* \ - *bl808_l1c*.o* \ - *bl808_common*.o* \ - *bl808_clock*.o* \ - *bl808_ef_ctrl*.o* \ - *bl808_sf_cfg*.o* \ - *bl808_sf_ctrl*.o* \ - *bl808_sflash*.o* \ - *bl808_xip_sflash*.o* \ - *bl808_romapi_patch*.o* ) .rodata*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl808_glb*.o*(.rodata*) - *bl808_glb_gpio*.o*(.rodata*) - *bl808_pds*.o*(.rodata*) - *bl808_aon*.o*(.rodata*) - *bl808_hbn*.o*(.rodata*) - *bl808_l1c*.o*(.rodata*) - *bl808_common*.o*(.rodata*) - *bl808_clock*.o*(.rodata*) - *bl808_ef_ctrl*.o*(.rodata*) - *bl808_sf_cfg*.o*(.rodata*) - *bl808_sf_ctrl*.o*(.rodata*) - *bl808_sflash*.o*(.rodata*) - *bl808_xip_sflash*.o*(.rodata*) - *bl808_romapi_patch*.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr) - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(xip_memory) + LENGTH(xip_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .nocache_noinit_ram_region (NOLOAD) : - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_noinit_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram.ld deleted file mode 100644 index 5fe6bd2ec6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram.ld +++ /dev/null @@ -1,191 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K - itcm_memory (rx) : ORIGIN = 0x62020000, LENGTH = 16K - dtcm_memory (rx) : ORIGIN = 0x62024000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22025000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x62025000, LENGTH = 12K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram_dv.ld deleted file mode 100644 index 3a992e09a4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/bl808_ram_dv.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x22020000, LENGTH = 32K - itcm_memory (rx) : ORIGIN = 0x22020000, LENGTH = 32K - dtcm_memory (rx) : ORIGIN = 0x22028000, LENGTH = 32K - ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/cpu_flags.cmake deleted file mode 100644 index 982896cb2f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/cpu_flags.cmake +++ /dev/null @@ -1,22 +0,0 @@ -#CPU_ARCH := RISCV -#MCPU := e902 -#E902 rv32ecxthead ilp32e e902 -#E902M rv32emcxthead ilp32e e902 -#E902T rv32ecxthead ilp32e e902 -#E902MT rv32emcxthead ilp32e e902 -#MARCH := rv32emcxthead -#MARCH := rv32emc -#MABI := ilp32e - -SET(CPU_ARCH "RISCV") -SET(MCPU "e902") - -SET(MARCH "rv32emcxtheadse") -SET(MABI "ilp32e") - -list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) -list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) - -SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/lp/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/lp/bl808_ram.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/lp/bl808_ram_dv.ld) \ No newline at end of file diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/interrupt.c deleted file mode 100644 index a167bb8416..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/interrupt.c +++ /dev/null @@ -1,361 +0,0 @@ -#include -#include -#include -#include -#include -#include "irq_ctx.h" -#include "bl808_common.h" - -#define DUMP_ALL_REGS -#define DUMP_MCAUSE_INFO - -typedef void (*pFunc)(void); -void NMI_Handler(void); - -pFunc g_irqvector[IRQn_LAST] = { 0 }; -pFunc g_nmivector = NMI_Handler; - -extern void Default_IRQHandler(void); -extern void Default_Handler(void); -extern void Mtspend_Handler(void); - -void Interrupt_Default_Handler(void) __attribute__((weak)); -void Interrupt_Default_Handler(void) -{ - /* un-handled external IRQ */ -#if !defined(__OS_FREERTOS__) - MSG("Enter interrupt Default_Handler\r\n"); -#endif -} - -#if 0 - extern void Trap_Handler(void); - extern void Interrupt_Handler(void); - void Interrupt_Handler_Stub(void); - - void clic_msip_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void clic_mtimer_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void clic_mext_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void clic_csoft_handler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void L1C_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void L1C_BMX_TO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void RF_TOP_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void RF_TOP_INT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SDIO_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void DMA_BMX_ERR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_GMAC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_CDET_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_PKA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_TRNG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_AES_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SEC_SHA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void DMA_ALL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void IRTX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void IRRX_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SF_CTRL_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void GPADC_DMA_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void EFUSE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void SPI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void UART0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void UART1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void I2C_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void PWM_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void TIMER_CH0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void TIMER_CH1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void TIMER_WDT_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void GPIO_INT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void PDS_WAKEUP_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void HBN_OUT0_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void HBN_OUT1_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BOR_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void WIFI_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BZ_PHY_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void BLE_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_TXRX_TIMER_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_TXRX_MISC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_RX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_TX_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_GEN_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void MAC_PORT_TRG_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); - void WIFI_IPC_PUBLIC_IRQHandler_Wrapper(void) __attribute__((weak, alias("Default_IRQHandler"))); -#endif - -const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = { - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ -#if defined(__OS_FREERTOS__) - Mtspend_Handler, /* 3: M-mode Soft IRQ */ -#else - Default_IRQHandler, /* 3: M-mode Soft IRQ */ -#endif - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_IRQHandler, /* 7: M-mode Timer IRQ */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - - Default_IRQHandler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */ - Default_IRQHandler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */ - Default_IRQHandler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */ - Default_IRQHandler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */ - Default_IRQHandler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */ - Default_IRQHandler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */ - Default_IRQHandler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */ - Default_IRQHandler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */ - Default_IRQHandler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */ - Default_IRQHandler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */ - Default_IRQHandler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */ - Default_IRQHandler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */ - Default_IRQHandler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */ - Default_IRQHandler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */ - Default_IRQHandler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */ - Default_IRQHandler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */ - Default_IRQHandler, //0, /* 16 + 16 */ - Default_IRQHandler, //0, /* 16 + 17 */ - Default_IRQHandler, //0, /* 16 + 18 */ - Default_IRQHandler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */ - Default_IRQHandler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */ - Default_IRQHandler, //0, /* 16 + 21 */ - Default_IRQHandler, //0, /* 16 + 22 */ - Default_IRQHandler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */ - Default_IRQHandler, //0, /* 16 + 24 */ - Default_IRQHandler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */ - Default_IRQHandler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */ - Default_IRQHandler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */ - Default_IRQHandler, //0, /* 16 + 28 */ - Default_IRQHandler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */ - Default_IRQHandler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */ - Default_IRQHandler, //0, /* 16 + 31 */ - Default_IRQHandler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */ - Default_IRQHandler, //0, /* 16 + 33 */ - Default_IRQHandler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */ - Default_IRQHandler, //0, /* 16 + 35 */ - Default_IRQHandler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */ - Default_IRQHandler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */ - Default_IRQHandler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */ - Default_IRQHandler, //0, /* 16 + 39 */ - Default_IRQHandler, //0, /* 16 + 40 */ - Default_IRQHandler, //0, /* 16 + 41 */ - Default_IRQHandler, //0, /* 16 + 42 */ - Default_IRQHandler, //0, /* 16 + 43 */ - Default_IRQHandler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */ - Default_IRQHandler, //0, /* 16 + 45 */ - Default_IRQHandler, //0, /* 16 + 46 */ - Default_IRQHandler, //0, /* 16 + 47 */ - Default_IRQHandler, //0, /* 16 + 48 */ - Default_IRQHandler, //0, /* 16 + 49 */ - Default_IRQHandler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */ - Default_IRQHandler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */ - Default_IRQHandler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */ - Default_IRQHandler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */ - Default_IRQHandler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */ - Default_IRQHandler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */ - Default_IRQHandler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */ - Default_IRQHandler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */ - Default_IRQHandler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */ - Default_IRQHandler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */ - Default_IRQHandler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */ - Default_IRQHandler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */ - Default_IRQHandler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */ - Default_IRQHandler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */ -}; - -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) __attribute__((noreturn)); -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - MSG("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type()); - MSG("cause: 0x%8x, tval = 0x%8x, epc = 0x%8x\n\r", cause, val, regs[REG_EPC_NDX]); -#ifdef DUMP_MCAUSE_INFO - const char *mcause_str[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store/AMO address misaligned", - "Store/AMO access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "RSVD", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "RSVD", - "Store/AMO page fault" - }; - if ((cause & 0xf)) - MSG("%s\r\n\r\n", mcause_str[cause & 0xf]); -#endif - -// clang-format off -#ifdef DUMP_ALL_REGS - MSG("ra = 0x%08x ", regs[REG_RA]); MSG("sp = 0x%08x ", regs[REG_SP]); MSG("gp = 0x%08x ", regs[REG_GP]); - MSG("tp = 0x%08x ", regs[REG_TP]); MSG("\n\r"); - - MSG("t0 = 0x%08x ", regs[REG_T0]); MSG("t1 = 0x%08x ", regs[REG_T1]); MSG("t2 = 0x%08x ", regs[REG_T2]); - MSG("\n\r"); - - MSG("a0 = 0x%08x ", regs[REG_A0]); MSG("a1 = 0x%08x ", regs[REG_A1]); MSG("a2 = 0x%08x ", regs[REG_A2]); - MSG("a3 = 0x%08x ", regs[REG_A3]); MSG("\n\r"); - MSG("a4 = 0x%08x ", regs[REG_A4]); MSG("a5 = 0x%08x ", regs[REG_A5]); MSG("\n\r"); - - MSG("s0 = 0x%08x ", regs[REG_S0]); MSG("s1 = 0x%08x ", regs[REG_S1]); MSG("\n\r"); -#endif - // clang-format on - - while (1) - ; -} - -static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - regs[REG_EPC_NDX] += 4; - __asm volatile("nop" :: - : "memory"); - - return 0; -} - -static exception_handler exception_handlers[RV_EXCEPTION_NUM] = { - exception_handler_default, /* 0: Instruction Address Misaligned */ - exception_handler_default, /* 1: Instruction Access Fault */ - exception_handler_default, /* 2: Illegal Instruction */ - exception_handler_default, /* 3: Breakpoint */ - exception_handler_default, /* 4: Load Address Misaligned */ - exception_handler_default, /* 5: Load Access Fault */ - exception_handler_default, /* 6: Store/AMO Address Misaligned */ - exception_handler_default, /* 7: Store/AMO Access Fault */ - exception_handler_default, /* 8: Environment Call from U-mode */ - exception_handler_default, /* 9: Environment Call from S-mode */ - exception_handler_default, /* 10: Environment Call from H-mode */ - exception_handler_ECALL_M, /* 11: Environment Call from M-mode */ - exception_handler_default, /* 12: Instruction Page Fault */ - exception_handler_default, /* 13: Load Page Fault */ - exception_handler_default, /* 14: Reserved */ - exception_handler_default, /* 15: Store/AMO Page Fault */ -}; - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler) -{ - exception_handler previous = NULL; - - if (RV_EXCEPTION_NUM > vec) { - previous = exception_handlers[vec]; - exception_handlers[vec] = handler; - } - - return previous; -} - -void trap_c(uint32_t *regs) -{ - uint32_t vec = 0; - uintptr_t cause = __get_MCAUSE(); - uintptr_t tval = __get_MTVAL(); - - vec = cause & 0x3FF; - - if (RV_EXCEPTION_NUM > vec) { - exception_handlers[vec](cause, tval, regs); - } else { - while (1) - ; - } -} - -void NMI_Handler(void) -{ - MSG("NMI_Handler\r\n"); - - while (1) - ; -} - -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) -{ - if (irq < IRQn_LAST) { - g_irqvector[irq] = interruptFun; - } -} - -/** - \brief enable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Enable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { - if (irq_num >= CPU_LP_MAX_IRQ_NUM) { - irq_num -= 32; - } - -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_enable_sirq(irq_num); -#else - csi_vic_enable_irq(irq_num); -#endif - } -} - -/** - \brief disable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void ATTR_TCM_SECTION CPU_Interrupt_Disable(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - } else { - if (irq_num >= CPU_LP_MAX_IRQ_NUM) { - irq_num -= 32; - } - -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_disable_sirq(irq_num); -#else - csi_vic_disable_irq(irq_num); -#endif - } -} - -/** - \brief Clear Pending Interrupt - \details Clear the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -void ATTR_TCM_SECTION CPU_Interrupt_Pending_Clear(uint32_t irq_num) -{ - if (irq_num >= IRQn_LAST) { - //MSG("Error! This interrupt don't support!\n"); - return; - } else { -#ifdef CONFIG_SYSTEM_SECURE - csi_vic_clear_pending_irq(irq_num); -#else - csi_vic_clear_pending_irq(irq_num); -#endif - } -} - -void System_Interrupt_Init(void) -{ - for (uintptr_t irq = 0; irq < IRQn_LAST; irq++) { - g_irqvector[irq] = Interrupt_Default_Handler; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/irq_ctx.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/irq_ctx.h deleted file mode 100644 index 909a05658e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/irq_ctx.h +++ /dev/null @@ -1,172 +0,0 @@ -#ifndef __IRQ_CTX_H__ -#define __IRQ_CTX_H__ - -/**************************************************************************** - * Included Files - ****************************************************************************/ - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/* Configuration ************************************************************/ - -/* Processor PC */ - -#define REG_EPC_NDX 0 - -/* General pupose registers - * $0: Zero register does not need to be saved - * $1: ra (return address) - */ - -#define REG_X1_NDX 1 - -/* $2: Stack POinter - * $3: Global Pointer - * $4: Thread Pointer - */ - -#define REG_X2_NDX 2 -#define REG_X3_NDX 3 -#define REG_X4_NDX 4 - -/* $5-$7 = t0-t3: Temporary registers */ - -#define REG_X5_NDX 5 -#define REG_X6_NDX 6 -#define REG_X7_NDX 7 - -/* $8: s0 / fp Frame pointer */ - -#define REG_X8_NDX 8 - -/* $89 s1 Saved register */ - -#define REG_X9_NDX 9 - -/* $10-$17 = a0-a7: Argument registers */ - -#define REG_X10_NDX 10 -#define REG_X11_NDX 11 -#define REG_X12_NDX 12 -#define REG_X13_NDX 13 -#define REG_X14_NDX 14 -#define REG_X15_NDX 15 - -/* Interrupt Context register */ - -#define REG_INT_CTX_NDX 16 - -#define INT_XCPT_REGS 17 - -#define INT_XCPT_SIZE (4 * INT_XCPT_REGS) - -#define XCPTCONTEXT_REGS (INT_XCPT_REGS) - -#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) - -/* In assembly language, values have to be referenced as byte address - * offsets. But in C, it is more convenient to reference registers as - * register save table offsets. - */ - -#ifdef __ASSEMBLY__ -#define REG_EPC (4 * REG_EPC_NDX) -#define REG_X1 (4 * REG_X1_NDX) -#define REG_X2 (4 * REG_X2_NDX) -#define REG_X3 (4 * REG_X3_NDX) -#define REG_X4 (4 * REG_X4_NDX) -#define REG_X5 (4 * REG_X5_NDX) -#define REG_X6 (4 * REG_X6_NDX) -#define REG_X7 (4 * REG_X7_NDX) -#define REG_X8 (4 * REG_X8_NDX) -#define REG_X9 (4 * REG_X9_NDX) -#define REG_X10 (4 * REG_X10_NDX) -#define REG_X11 (4 * REG_X11_NDX) -#define REG_X12 (4 * REG_X12_NDX) -#define REG_X13 (4 * REG_X13_NDX) -#define REG_X14 (4 * REG_X14_NDX) -#define REG_X15 (4 * REG_X15_NDX) -#define REG_INT_CTX (4 * REG_INT_CTX_NDX) - -#else -#define REG_EPC REG_EPC_NDX -#define REG_X1 REG_X1_NDX -#define REG_X2 REG_X2_NDX -#define REG_X3 REG_X3_NDX -#define REG_X4 REG_X4_NDX -#define REG_X5 REG_X5_NDX -#define REG_X6 REG_X6_NDX -#define REG_X7 REG_X7_NDX -#define REG_X8 REG_X8_NDX -#define REG_X9 REG_X9_NDX -#define REG_X10 REG_X10_NDX -#define REG_X11 REG_X11_NDX -#define REG_X12 REG_X12_NDX -#define REG_X13 REG_X13_NDX -#define REG_X14 REG_X14_NDX -#define REG_X15 REG_X15_NDX -#define REG_INT_CTX REG_INT_CTX_NDX - -#endif - -/* Now define more user friendly alternative name that can be used either - * in assembly or C contexts. - */ - -/* $1 = ra: Return address */ - -#define REG_RA REG_X1 - -/* $2 = sp: The value of the stack pointer on return from the exception */ - -#define REG_SP REG_X2 - -/* $3 = gp: Only needs to be saved under conditions where there are - * multiple, per-thread values for the GP. - */ - -#define REG_GP REG_X3 - -/* $4 = tp: Thread Pointer */ - -#define REG_TP REG_X4 - -/* $5-$7 = t0-t2: Caller saved temporary registers */ - -#define REG_T0 REG_X5 -#define REG_T1 REG_X6 -#define REG_T2 REG_X7 - -/* $8 = either s0 or fp: Depends if a frame pointer is used or not */ - -#define REG_S0 REG_X8 -#define REG_FP REG_X8 - -/* $9 = s1: Caller saved register */ - -#define REG_S1 REG_X9 - -/* $10-$17 = a0-a7: Argument registers */ - -#define REG_A0 REG_X10 -#define REG_A1 REG_X11 -#define REG_A2 REG_X12 -#define REG_A3 REG_X13 -#define REG_A4 REG_X14 -#define REG_A5 REG_X15 - -/**************************************************************************** - * Public Types - ****************************************************************************/ - -/**************************************************************************** - * Public Variables - ****************************************************************************/ - -/**************************************************************************** - * Public Function Prototypes - ****************************************************************************/ - -#endif /* __IRQ_CTX_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.c deleted file mode 100644 index 2db677c54c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.c +++ /dev/null @@ -1,84 +0,0 @@ -#include "bl808.h" -#include "bl808_clock.h" -#ifdef BOOTROM -#include "bflb_bootrom.h" -#endif - -/*---------------------------------------------------------------------------- - Define clocks - *----------------------------------------------------------------------------*/ -#define SYSTEM_CLOCK (16000000UL) - -/*---------------------------------------------------------------------------- - System initialization function - *----------------------------------------------------------------------------*/ - -void System_BOR_Init(void) -{ - //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */}; - //HBN_Set_BOR_Cfg(&borCfg); -} - -void System_Core_Clock_Set(BL_System_Clock_Type type, uint32_t clock) -{ - Clock_Cfg_Type *pClk = (Clock_Cfg_Type *)SYS_CLOCK_CFG_ADDR; - - CHECK_PARAM(IS_BL_SYSTEM_CLOCK_TYPE(type)); - - if (type < BL_SYSTEM_CLOCK_MAX) { - pClk->systemClock[type] = clock; - pClk->magic = SYS_CLOCK_CFG_MAGIC; - } -} - -void System_Init(void) -{ - uint32_t i = 0; - - /* get interrupt level from info */ - CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos); - - /* Every interrupt should be clear by software*/ - for (i = 0; i < IRQn_LAST; i++) { - CLIC->CLICINT[i].IP = 0; - CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */ - } - - /* tspend interrupt will be clear auto*/ - /* tspend use positive interrupt */ - CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3; - - //csi_dcache_enable(); - //csi_icache_enable(); - //CPU_Interrupt_Enable(MSOFT_IRQn); - - /* init bor for all platform */ - System_BOR_Init(); -} - -void System_Post_Init(void) -{ - System_Interrupt_Init(); - - /* global IRQ enable */ - __enable_irq(); -} - -void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority) -{ - if (IRQn >= CPU_LP_MAX_IRQ_NUM) { - IRQn -= 32; - } - - csi_vic_set_prio(IRQn, PreemptPriority); -} - -int32_t drv_get_cpu_id(void) -{ - return __get_MHARTID(); -} - -int32_t drv_get_cpu_freq(int32_t idx) -{ - return 16 * 1000 * 1000UL; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.h deleted file mode 100644 index 2ed33137a7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/system_bl808.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __SYSTEM_BL808_H__ -#define __SYSTEM_BL808_H__ - -#define RV_EXCEPTION_NUM (16) -typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs); -typedef void (*pFunc)(void); - -extern void System_Interrupt_Init(void); -extern void CPU_Interrupt_Enable(uint32_t irq_num); -extern void CPU_Interrupt_Disable(uint32_t irq_num); -extern void CPU_Interrupt_Pending_Clear(uint32_t irq_num); -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); -extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler); - -int32_t drv_get_cpu_id(void); -int32_t drv_get_cpu_freq(int32_t idx); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash_dv.ld deleted file mode 100644 index aebfaa8fc7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash_dv.ld +++ /dev/null @@ -1,213 +0,0 @@ -/**************************************************************************************** -* @file flash.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - xip_memory (rx) : ORIGIN = 0x90000000, LENGTH = 32M - itcm_memory (rx) : ORIGIN = 0x62028000, LENGTH = 48K - dtcm_memory (rx) : ORIGIN = 0x62034000, LENGTH = 16K - ram_memory (!rx) : ORIGIN = 0x62038000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /*put .rodata**/ - *(EXCLUDE_FILE( *bl602_glb.o \ - *bl602_pds.o \ - *bl602_common.o \ - *bl602_sf_cfg.o \ - *bl602_sf_ctrl.o \ - *bl602_sflash.o \ - *bl602_xip_sflash.o \ - *bl602_ef_ctrl.o) .rodata*) - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > xip_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - *bl602_glb.o*(.rodata*) - *bl602_pds.o*(.rodata*) - *bl602_common.o*(.rodata*) - *bl602_sf_cfg.o*(.rodata*) - *bl602_sf_ctrl.o*(.rodata*) - *bl602_sflash.o*(.rodata*) - *bl602_xip_sflash.o*(.rodata*) - *bl602_ef_ctrl.o*(.rodata*) - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram.ld deleted file mode 100644 index 60b6da837f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram.ld +++ /dev/null @@ -1,221 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x62028000, LENGTH = 60K - itcm_memory (rx) : ORIGIN = 0x62028000, LENGTH = 60K - dtcm_memory (rx) : ORIGIN = 0x62037000, LENGTH = 4K - nocache_ram_memory (!rx) : ORIGIN = 0x22038000, LENGTH = 0K - ram_memory (!rx) : ORIGIN = 0x62038000, LENGTH = 160K-32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - KEEP(*startup*.*o(*.text*)) - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - /* section information for shell */ - . = ALIGN(4); - __fsymtab_start = .; - KEEP(*(FSymTab)) - __fsymtab_end = .; - - . = ALIGN(4); - __vsymtab_start = .; - KEEP(*(VSymTab)) - __vsymtab_end = .; - - /* section information for usb desc */ - . = ALIGN(4); - _usb_desc_start = .; - KEEP(*(usb_desc)) - . = ALIGN(4); - _usb_desc_end = .; - - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr) - { - . = ALIGN(4); - __nocache_ram_data_start__ = .; - - *(.nocache_ram) - - . = ALIGN(4); - __nocache_ram_data_end__ = .; - } > nocache_ram_memory - - __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram_dv.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram_dv.ld deleted file mode 100644 index d27ef9b8d9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_ram_dv.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x90000000, LENGTH = 48K - itcm_memory (rx) : ORIGIN = 0x22020000, LENGTH = 48K - dtcm_memory (rx) : ORIGIN = 0x2202C000, LENGTH = 16K - ram_memory (!rx) : ORIGIN = 0x62038000, LENGTH = 32K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_rom.ld deleted file mode 100644 index 64ca7f6f7c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_rom.ld +++ /dev/null @@ -1,195 +0,0 @@ -/**************************************************************************************** -* @file ram.ld -* -* @brief This file is the link script file (gnuarm or armgcc). -* -* Copyright (C) BouffaloLab 2021 -* -**************************************************************************************** -*/ - -/* configure the CPU type */ -OUTPUT_ARCH( "riscv" ) -/* link with the standard c library */ -INPUT(-lc) -/* link with the standard GCC library */ -INPUT(-lgcc) -/* configure the entry point */ -ENTRY(Reset_Handler) - -StackSize = 0x0400; /* 1KB */ -HeapMinSize = 0x1000; /* 4KB */ - -MEMORY -{ - code_memory (rx) : ORIGIN = 0x90000000, LENGTH = 128K - itcm_memory (rx) : ORIGIN = 0x62028000, LENGTH = 1K - dtcm_memory (rx) : ORIGIN = 0x62030000, LENGTH = 4K - ram_memory (!rx) : ORIGIN = 0x62031000, LENGTH = 124K - xram_memory (!rx) : ORIGIN = 0x40000000, LENGTH = 16K -} - -SECTIONS -{ - PROVIDE(__metal_chicken_bit = 0); - - .text : - { - . = ALIGN(4); - __text_code_start__ = .; - - KEEP (*(SORT_NONE(_start))) - KEEP (*(SORT_NONE(Reset_Handler))) - - *(.text) - *(.text.*) - - *(.rodata) - *(.rodata.*) - - *(.srodata) - *(.srodata.*) - - *(.tcm_code.*) - *(.tcm_const.*) - *(.sclock_rlt_code.*) - *(.sclock_rlt_const.*) - - . = ALIGN(4); - __text_code_end__ = .; - } > code_memory - - . = ALIGN(4); - __itcm_load_addr = .; - - .itcm_region : AT (__itcm_load_addr) - { - . = ALIGN(4); - __tcm_code_start__ = .; - - . = ALIGN(4); - __tcm_code_end__ = .; - } > itcm_memory - - __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region); - - .dtcm_region : AT (__dtcm_load_addr) - { - . = ALIGN(4); - __tcm_data_start__ = .; - - *(.tcm_data) - /* *finger_print.o(.data*) */ - - . = ALIGN(4); - __tcm_data_end__ = .; - } > dtcm_memory - - /*************************************************************************/ - /* .stack_dummy section doesn't contains any symbols. It is only - * used for linker to calculate size of stack sections, and assign - * values to stack symbols later */ - .stack_dummy (NOLOAD): - { - . = ALIGN(0x4); - . = . + StackSize; - . = ALIGN(0x4); - } > dtcm_memory - - /* Set stack top to end of RAM, and stack limit move down by - * size of stack_dummy section */ - __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory); - PROVIDE( __freertos_irq_stack_top = __StackTop); - __StackLimit = __StackTop - SIZEOF(.stack_dummy); - - /* Check if data + heap + stack exceeds RAM limit */ - ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack") - /*************************************************************************/ - - __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region); - - .system_ram_data_region : AT (__system_ram_load_addr) - { - . = ALIGN(4); - __system_ram_data_start__ = .; - - *(.system_ram) - - . = ALIGN(4); - __system_ram_data_end__ = .; - } > ram_memory - - .system_ram_noinit_data_region (NOLOAD) : - { - . = ALIGN(4); - *(.system_ram_noinit) - - . = ALIGN(4); - } > ram_memory - - __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region); - - /* Data section */ - RAM_DATA : AT (__ram_load_addr) - { - . = ALIGN(4); - __ram_data_start__ = .; - - PROVIDE( __global_pointer$ = . + 0x800 ); - - *(.data) - *(.data.*) - *(.sdata) - *(.sdata.*) - *(.sdata2) - *(.sdata2.*) - - . = ALIGN(4); - __ram_data_end__ = .; - } > ram_memory - - __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA)); - ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow") - - .bss (NOLOAD) : - { - . = ALIGN(4); - __bss_start__ = .; - - *(.bss*) - *(.sbss*) - *(COMMON) - - . = ALIGN(4); - __bss_end__ = .; - } > ram_memory - - .noinit_data (NOLOAD) : - { - . = ALIGN(4); - __noinit_data_start__ = .; - - *(.noinit_data*) - - . = ALIGN(4); - __noinit_data_end__ = .; - } > ram_memory - - .heap (NOLOAD): - { - . = ALIGN(4); - __HeapBase = .; - - /*__end__ = .;*/ - /*end = __end__;*/ - KEEP(*(.heap*)) - - . = ALIGN(4); - __HeapLimit = .; - } > ram_memory - - __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory); - ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow") - -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/cpu_flags.cmake b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/cpu_flags.cmake deleted file mode 100644 index 45614d164c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/cpu_flags.cmake +++ /dev/null @@ -1,20 +0,0 @@ -#CPU_ARCH := RISCV -#MCPU := e907 -#E906 rv32imacxthead ilp32 e907 -#E906F rv32imacfxthead ilp32f e907 -#E906FD rv32imacfdxthead ilp32d e907 - -SET(CPU_ARCH "RISCV") -SET(MCPU "e907") - -SET(MARCH "rv32imafcpzpsfoperand_xtheade") -SET(MABI "ilp32f") - -list(APPEND GLOBAL_C_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) -list(APPEND GLOBAL_LD_FLAGS -march=${MARCH} -mabi=${MABI} -mtune=${MCPU}) - -SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_rom.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_flash.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_ram_dv.ld) -#SET(LINKER_SCRIPT ${CMAKE_SOURCE_DIR}/drivers/bl808_driver/startup/m0/bl808_flash_dv.ld) \ No newline at end of file diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/startup.S b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/startup.S deleted file mode 100644 index 7275d29aa7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/startup.S +++ /dev/null @@ -1,168 +0,0 @@ -/* - * Copyright (C) 2016-2020 Bouffalo Lab - */ - /* stack for IRQs */ - .extern g_irq_sp - -_start: - .text - .align 2 - .globl Reset_Handler - .type Reset_Handler, %function -Reset_Handler: -.option push -.option norelax - la gp, __global_pointer$ -.option pop - csrci mstatus, 8 - /* TODO: debug */ - csrw mcycle, zero - csrw mcycleh, zero - csrw minstret, zero - csrw minstreth, zero -#ifndef __NO_HBN_RECV_IN_STARTUP - /* clear hbn ram ret/slp */ - /* 0x2000F034[7:6] = 0 */ - li a0, 0x2000F034 - li a2, 0xFFFFFF3F - lw a1, 0(a0) - and a1, a1, a2 - sw a1, 0(a0) - - /* clear pds ram ret/slp */ - /* 0x2000E020[31:30][7:0] = 0 */ - li a0, 0x2000E020 - li a2, 0x3FFFFF00 - lw a1, 0(a0) - and a1, a1, a2 - sw a1, 0(a0) - /* 0x2000E028[19:0] = 0 */ - li a0, 0x2000E028 - li a2, 0xFFF00000 - lw a1, 0(a0) - and a1, a1, a2 - sw a1, 0(a0) - - /* load efuse value:if bit[31] is 1,can not jump */ - li a0, 0x2005605C - lw a0, 0(a0) - srli a0, a0, 0x1b - andi a0, a0, 0x10 - li t0, 0x10 - beq t0, a0, .HBN_NOT_JUMP - - /* check hbn mode */ - li a0, 0x2000f100 - lw a0, 0(a0) - li t0, 0x4e424845 - bne t0, a0, .HBN_NOT_JUMP - li a1, 0x4e424857 - li a2, 0x2000f100 - sw a1, 0(a2) - - /* we can jump unless it's not 0 or 0xffffffff */ - li a0, 0x2000f104 - lw a0, 0(a0) - addi t0, a0, -1 - li t1, -3 - bltu t1, t0, .HBN_NOT_JUMP - jalr a0 - -.HBN_NOT_JUMP: - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - /* - li a0, 0x40000060 - li t0, 0x00206F00 - sw t0, 0(a0) - */ - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop - nop -#endif - - /* mtvec: for all exceptions and non-vector mode IRQs */ - la a0, Default_Handler - ori a0, a0, 3 - csrw mtvec, a0 - - /* mtvt: for all vector mode IRQs */ - la a0, __Vectors - csrw mtvt, a0 - -#if defined(__riscv_flen) - /* FP: initial state */ - csrr t0, mstatus - li t1, ~0x6000 - and t0, t0, t1 - li t1, 0x2000 - or t0, t0, t1 - csrw mstatus, t0 - /* csrwi fcsr, 0 */ -#endif - - .weak __StackTop - la sp, __StackTop - /* stack: 16-byte aligned */ - andi sp, sp, -16 - la t0, g_irq_sp - /* utilizes the stack point auto-exchange feature */ - csrw mscratch, t0 - - /* Load data section removed */ - - /* Clear bss section removed */ - -#ifndef __NO_SYSTEM_INIT - jal System_Init -#endif - - /* start load code to itcm like. */ - jal start_load - -#ifndef __NO_BOARD_INIT - jal System_Post_Init -#endif - - jal main - - .size Reset_Handler, . - Reset_Handler - -__exit: - j __exit - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/interrupt.c deleted file mode 100644 index cb93179e59..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/interrupt.c +++ /dev/null @@ -1,343 +0,0 @@ -#include -#include -#include -#include -#include -#include "bl808_glb.h" -#include "irq_ctx.h" - -typedef void (*pFunc)(void); -void NMI_Handler(void); - -/* - * g_irqvector is the real ISRs written in simple C style: no __attribute__ ((interrupt)) needed! - * An when IRQ is in vector mode, the __Vectors is the pesudo handler entry, which redirects the CPU - * to a single handler: Default_IRQHandler, and who will call the corresponding ISR in g_irqvector, - * as well as context save/restore work. - * BTW, some of the special IRQs have different solutions, such as mtime for the RTOS "tick". - */ -pFunc g_irqvector[IRQn_LAST] __attribute__((section(".noinit_data"))); -pFunc g_nmivector = NMI_Handler; - -extern void Default_IRQHandler(void); -extern void Default_Handler(void); -extern void Mtspend_Handler(); - - -const pFunc __Vectors[] __attribute__((section(".init"), aligned(64))) = { - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ -#if defined(__OS_FREERTOS__) - Mtspend_Handler, /* 3: M-mode Soft IRQ */ -#else - Default_IRQHandler, /* 3: M-mode Soft IRQ */ -#endif - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_IRQHandler, /* 7: M-mode Timer IRQ */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - Default_Handler, /* */ - - Default_IRQHandler, //BMX_ERR_IRQHandler_Wrapper, /* 16 + 0 */ - Default_IRQHandler, //BMX_TO_IRQHandler_Wrapper, /* 16 + 1 */ - Default_IRQHandler, //L1C_BMX_ERR_IRQHandler_Wrapper, /* 16 + 2 */ - Default_IRQHandler, //L1C_BMX_TO_IRQHandler_Wrapper, /* 16 + 3 */ - Default_IRQHandler, //SEC_BMX_ERR_IRQHandler_Wrapper, /* 16 + 4 */ - Default_IRQHandler, //RF_TOP_INT0_IRQHandler_Wrapper, /* 16 + 5 */ - Default_IRQHandler, //RF_TOP_INT1_IRQHandler_Wrapper, /* 16 + 6 */ - Default_IRQHandler, //SDIO_IRQHandler_Wrapper, /* 16 + 7 */ - Default_IRQHandler, //DMA_BMX_ERR_IRQHandler_Wrapper, /* 16 + 8 */ - Default_IRQHandler, //SEC_GMAC_IRQHandler_Wrapper, /* 16 + 9 */ - Default_IRQHandler, //SEC_CDET_IRQHandler_Wrapper, /* 16 + 10 */ - Default_IRQHandler, //SEC_PKA_IRQHandler_Wrapper, /* 16 + 11 */ - Default_IRQHandler, //SEC_TRNG_IRQHandler_Wrapper, /* 16 + 12 */ - Default_IRQHandler, //SEC_AES_IRQHandler_Wrapper, /* 16 + 13 */ - Default_IRQHandler, //SEC_SHA_IRQHandler_Wrapper, /* 16 + 14 */ - Default_IRQHandler, //DMA_ALL_IRQHandler_Wrapper, /* 16 + 15 */ - Default_IRQHandler, //0, /* 16 + 16 */ - Default_IRQHandler, //0, /* 16 + 17 */ - Default_IRQHandler, //0, /* 16 + 18 */ - Default_IRQHandler, //IRTX_IRQHandler_Wrapper, /* 16 + 19 */ - Default_IRQHandler, //IRRX_IRQHandler_Wrapper, /* 16 + 20 */ - Default_IRQHandler, //0, /* 16 + 21 */ - Default_IRQHandler, //0, /* 16 + 22 */ - Default_IRQHandler, //SF_CTRL_IRQHandler_Wrapper, /* 16 + 23 */ - Default_IRQHandler, //0, /* 16 + 24 */ - Default_IRQHandler, //GPADC_DMA_IRQHandler_Wrapper, /* 16 + 25 */ - Default_IRQHandler, //EFUSE_IRQHandler_Wrapper, /* 16 + 26 */ - Default_IRQHandler, //SPI_IRQHandler_Wrapper, /* 16 + 27 */ - Default_IRQHandler, //0, /* 16 + 28 */ - Default_IRQHandler, //UART0_IRQHandler_Wrapper, /* 16 + 29 */ - Default_IRQHandler, //UART1_IRQHandler_Wrapper, /* 16 + 30 */ - Default_IRQHandler, //0, /* 16 + 31 */ - Default_IRQHandler, //I2C_IRQHandler_Wrapper, /* 16 + 32 */ - Default_IRQHandler, //0, /* 16 + 33 */ - Default_IRQHandler, //PWM_IRQHandler_Wrapper, /* 16 + 34 */ - Default_IRQHandler, //0, /* 16 + 35 */ - Default_IRQHandler, //TIMER_CH0_IRQHandler_Wrapper, /* 16 + 36 */ - Default_IRQHandler, //TIMER_CH1_IRQHandler_Wrapper, /* 16 + 37 */ - Default_IRQHandler, //TIMER_WDT_IRQHandler_Wrapper, /* 16 + 38 */ - Default_IRQHandler, //0, /* 16 + 39 */ - Default_IRQHandler, //0, /* 16 + 40 */ - Default_IRQHandler, //0, /* 16 + 41 */ - Default_IRQHandler, //0, /* 16 + 42 */ - Default_IRQHandler, //0, /* 16 + 43 */ - Default_IRQHandler, //GPIO_INT0_IRQHandler_Wrapper, /* 16 + 44 */ - Default_IRQHandler, //0, /* 16 + 45 */ - Default_IRQHandler, //0, /* 16 + 46 */ - Default_IRQHandler, //0, /* 16 + 47 */ - Default_IRQHandler, //0, /* 16 + 48 */ - Default_IRQHandler, //0, /* 16 + 49 */ - Default_IRQHandler, //PDS_WAKEUP_IRQHandler_Wrapper, /* 16 + 50 */ - Default_IRQHandler, //HBN_OUT0_IRQHandler_Wrapper, /* 16 + 51 */ - Default_IRQHandler, //HBN_OUT1_IRQHandler_Wrapper, /* 16 + 52 */ - Default_IRQHandler, //BOR_IRQHandler_Wrapper, /* 16 + 53 */ - Default_IRQHandler, //WIFI_IRQHandler_Wrapper, /* 16 + 54 */ - Default_IRQHandler, //BZ_PHY_IRQHandler_Wrapper, /* 16 + 55 */ - Default_IRQHandler, //BLE_IRQHandler_Wrapper, /* 16 + 56 */ - Default_IRQHandler, //MAC_TXRX_TIMER_IRQHandler_Wrapper, /* 16 + 57 */ - Default_IRQHandler, //MAC_TXRX_MISC_IRQHandler_Wrapper, /* 16 + 58 */ - Default_IRQHandler, //MAC_RX_TRG_IRQHandler_Wrapper, /* 16 + 59 */ - Default_IRQHandler, //MAC_TX_TRG_IRQHandler_Wrapper, /* 16 + 60 */ - Default_IRQHandler, //MAC_GEN_IRQHandler_Wrapper, /* 16 + 61 */ - Default_IRQHandler, //MAC_PORT_TRG_IRQHandler_Wrapper, /* 16 + 62 */ - Default_IRQHandler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper, /* 16 + 63 */ -}; - -/** - \brief the default IRQ handler. - \param[in] cause Number of IRQ. - \return no return. -*/ -void Interrupt_Default_Handler(uintptr_t cause) __attribute__((weak)); -void Interrupt_Default_Handler(uintptr_t cause) -{ - /* un-handled external IRQ */ - MSG("Enter interrupt default handler %x\r\n", cause); -} - -/** - \brief the default Trap handler. - \param[in] cause Number of Trap. - \param[in] val from mtval reg. - \param[in] regs CPU context of the Trap. - \return no return. -*/ -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs); -static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - uint32_t mepc_val; - - /* 0x80000000-0x90000000 is protected by PMP for CPU Prefetching */ - if(val>=0x80000000&&val<0x90000000){ - uint32_t tmp_cause=cause&0xf; - if(tmp_cause==0x01||tmp_cause==0x05){ - /*Instruction access fault or Load access fault*/ - mepc_val=BL_RD_WORD(regs[REG_EPC_NDX]); - if((mepc_val&0x03)==0x03){ - regs[REG_EPC_NDX] += 4; - }else{ - regs[REG_EPC_NDX] += 2; - } - return 0; - } - } - - MSG("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type()); - - MSG("cause: 0x%8x, tval = 0x%8x, epc = 0x%8x\n\r", cause, val, regs[REG_EPC_NDX]); -#ifndef CONFIG_ERR_NOT_DUMP_MCAUSE_INFO - const char *mcause_str[] = { - "Instruction address misaligned", - "Instruction access fault", - "Illegal instruction", - "Breakpoint", - "Load address misaligned", - "Load access fault", - "Store/AMO address misaligned", - "Store/AMO access fault", - "Environment call from U-mode", - "Environment call from S-mode", - "RSVD", - "Environment call from M-mode", - "Instruction page fault", - "Load page fault", - "RSVD", - "Store/AMO page fault" - }; - if ((cause & 0xf)) - MSG("%s\r\n\r\n", mcause_str[cause & 0xf]); -#endif - -// clang-format off -#ifndef CONFIG_ERR_NOT_DUMP_ALL_REGS - MSG("ra = 0x%08x ", regs[REG_RA]); MSG("sp = 0x%08x ", regs[REG_SP]); MSG("gp = 0x%08x ", regs[REG_GP]); - MSG("tp = 0x%08x ", regs[REG_TP]); MSG("\n\r"); - - MSG("t0 = 0x%08x ", regs[REG_T0]); MSG("t1 = 0x%08x ", regs[REG_T1]); MSG("t2 = 0x%08x ", regs[REG_T2]); - MSG("t3 = 0x%08x ", regs[REG_T3]); MSG("\n\r"); - MSG("t4 = 0x%08x ", regs[REG_T4]); MSG("t5 = 0x%08x ", regs[REG_T5]); MSG("t6 = 0x%08x ", regs[REG_T6]); - MSG("\n\r"); - - MSG("a0 = 0x%08x ", regs[REG_A0]); MSG("a1 = 0x%08x ", regs[REG_A1]); MSG("a2 = 0x%08x ", regs[REG_A2]); - MSG("a3 = 0x%08x ", regs[REG_A3]); MSG("\n\r"); - MSG("a4 = 0x%08x ", regs[REG_A4]); MSG("a5 = 0x%08x ", regs[REG_A5]); MSG("a6 = 0x%08x ", regs[REG_A6]); - MSG("a7 = 0x%08x ", regs[REG_A7]); MSG("\n\r"); - - MSG("s0 = 0x%08x ", regs[REG_S0]); MSG("s1 = 0x%08x ", regs[REG_S1]); MSG("s2 = 0x%08x ", regs[REG_S2]); - MSG("s3 = 0x%08x ", regs[REG_S3]); MSG("\n\r"); - MSG("s4 = 0x%08x ", regs[REG_S4]); MSG("s5 = 0x%08x ", regs[REG_S5]); MSG("s6 = 0x%08x ", regs[REG_S6]); - MSG("s7 = 0x%08x ", regs[REG_S7]); MSG("\n\r"); - MSG("s8 = 0x%08x ", regs[REG_S8]); MSG("s9 = 0x%08x ", regs[REG_S9]); MSG("s10 = 0x%08x ", regs[REG_S10]); - MSG("s11 = 0x%08x ", regs[REG_S11]); MSG("\n\r"); -#endif - // clang-format on - - while (1) - ; -} - -/** - \brief the trap handler for ecall from M-mode. - \param[in] cause Number of Trap. - \param[in] val from mtval reg. - \param[in] regs CPU context of the Trap. - \return no return. -*/ -static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs) -{ - regs[REG_EPC_NDX] += 4; - __asm volatile("nop" :: - : "memory"); - - /* indicated ecall from Machine-Mode */ - regs[REG_A0] = 1; - return 0; -} - -static exception_handler exception_handlers[RV_EXCEPTION_NUM] = { - exception_handler_default, /* 0: Instruction Address Misaligned */ - exception_handler_default, /* 1: Instruction Access Fault */ - exception_handler_default, /* 2: Illegal Instruction */ - exception_handler_default, /* 3: Breakpoint */ - exception_handler_default, /* 4: Load Address Misaligned */ - exception_handler_default, /* 5: Load Access Fault */ - exception_handler_default, /* 6: Store/AMO Address Misaligned */ - exception_handler_default, /* 7: Store/AMO Access Fault */ - exception_handler_default, /* 8: Environment Call from U-mode */ - exception_handler_default, /* 9: Environment Call from S-mode */ - exception_handler_default, /* 10: Environment Call from H-mode */ - exception_handler_ECALL_M, /* 11: Environment Call from M-mode */ - exception_handler_default, /* 12: Instruction Page Fault */ - exception_handler_default, /* 13: Load Page Fault */ - exception_handler_default, /* 14: Reserved */ - exception_handler_default, /* 15: Store/AMO Page Fault */ -}; - -/** - \brief install handler to Trap handler. - \param[in] vec Number of Trap. - \param[in] handler the handler for Trap. - \return the previous handler. -*/ -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler) -{ - exception_handler previous = NULL; - - if (RV_EXCEPTION_NUM > vec) { - previous = exception_handlers[vec]; - exception_handlers[vec] = handler; - } - - return previous; -} - -/** - \brief C handler for CPU Traps. - \param[in] regs is the CPU context. - \return None. -*/ -void trap_c(uintptr_t *regs) -{ - uint32_t vec = 0; - uintptr_t cause = __get_MCAUSE(); - uintptr_t tval = __get_MTVAL(); - - //riscv_savefpu(regs); - - vec = cause & 0x3FF; - - if (RV_EXCEPTION_NUM > vec) { - exception_handlers[vec](cause, tval, (uintptr_t *)regs); - } else { - while (1) - ; - } - - //riscv_restorefpu(regs); -} - -/** - \brief set all ISRs in g_irqvector to the default one. - \return None. -*/ -void System_Interrupt_Init(void) -{ - for (uintptr_t irq = 0; irq < IRQn_LAST; irq++) { - g_irqvector[irq] = (pFunc)Interrupt_Default_Handler; - } -} - -/** - \brief install ISR to g_irqvector. - \param[in] irq Number of IRQ. - \param[in] interruptFun the ISR for irq. - \return None. -*/ -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun) -{ - if (irq < IRQn_LAST) { - g_irqvector[irq] = interruptFun; - } -} - -/** - \brief enable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void CPU_Interrupt_Enable(uint32_t irq_num) -{ - if (irq_num < IRQn_LAST) - csi_vic_enable_irq(irq_num); -} - -/** - \brief disable irq. - \param[in] irq_num Number of IRQ. - \return None. -*/ -void CPU_Interrupt_Disable(uint32_t irq_num) -{ - if (irq_num < IRQn_LAST) - csi_vic_disable_irq(irq_num); -} - -/** - \brief Clear Pending Interrupt - \details Clear the pending bit of an external interrupt. - \param [in] IRQn External interrupt number. Value cannot be negative. - */ -void CPU_Interrupt_Pending_Clear(uint32_t irq_num) -{ - if (irq_num < IRQn_LAST) - csi_vic_clear_pending_irq(irq_num); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.h deleted file mode 100644 index 2ed33137a7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.h +++ /dev/null @@ -1,20 +0,0 @@ -#ifndef __SYSTEM_BL808_H__ -#define __SYSTEM_BL808_H__ - -#define RV_EXCEPTION_NUM (16) -typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs); -typedef void (*pFunc)(void); - -extern void System_Interrupt_Init(void); -extern void CPU_Interrupt_Enable(uint32_t irq_num); -extern void CPU_Interrupt_Disable(uint32_t irq_num); -extern void CPU_Interrupt_Pending_Clear(uint32_t irq_num); -void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun); -extern void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority); - -exception_handler exception_handler_install(uintptr_t vec, exception_handler handler); - -int32_t drv_get_cpu_id(void); -int32_t drv_get_cpu_freq(int32_t idx); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_adc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_adc.h deleted file mode 100644 index db4f23c74b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_adc.h +++ /dev/null @@ -1,550 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_adc.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_ADC_H__ -#define __BL808_ADC_H__ - -#include "aon_reg.h" -#include "gpip_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Public_Types - * @{ - */ - -/** - * @brief ADC channel type definition - */ -typedef enum { - ADC_CHAN0, /*!< ADC channel 0 */ - ADC_CHAN1, /*!< ADC channel 1 */ - ADC_CHAN2, /*!< ADC channel 2 */ - ADC_CHAN3, /*!< ADC channel 3 */ - ADC_CHAN4, /*!< ADC channel 4 */ - ADC_CHAN5, /*!< ADC channel 5 */ - ADC_CHAN6, /*!< ADC channel 6 */ - ADC_CHAN7, /*!< ADC channel 7 */ - ADC_CHAN8, /*!< ADC channel 8 */ - ADC_CHAN9, /*!< ADC channel 9 */ - ADC_CHAN10, /*!< ADC channel 10 */ - ADC_CHAN11, /*!< ADC channel 11 */ - ADC_CHAN_DAC_OUTA, /*!< DACA, ADC channel 12 */ - ADC_CHAN_DAC_OUTB, /*!< DACB, ADC channel 13 */ - ADC_CHAN_TSEN_P, /*!< TSenp, ADC channel 14 */ - ADC_CHAN_TSEN_N, /*!< TSenn, ADC channel 15 */ - ADC_CHAN_VREF, /*!< Vref, ADC channel 16 */ - ADC_CHAN_DCTEST, /*!< DCTest, ADC channel 17 */ - ADC_CHAN_VABT_HALF, /*!< VBAT/2, ADC channel 18 */ - ADC_CHAN_SENP3, /*!< SenVP3, ADC channel 19 */ - ADC_CHAN_SENP2, /*!< SenVP2, ADC channel 20 */ - ADC_CHAN_SENP1, /*!< SenVP1, ADC channel 21 */ - ADC_CHAN_SENP0, /*!< SenVP0, ADC channel 22 */ - ADC_CHAN_GND, /*!< GND, ADC channel 23 */ -} ADC_Chan_Type; - -/** - * @brief ADC V18 selection type definition - */ -typedef enum { - ADC_V18_SEL_1P62V, /*!< V18 select 1.62V */ - ADC_V18_SEL_1P72V, /*!< V18 select 1.72V */ - ADC_V18_SEL_1P82V, /*!< V18 select 1.82V */ - ADC_V18_SEL_1P92V, /*!< V18 select 1.92V */ -} ADC_V18_SEL_Type; - -/** - * @brief ADC V11 selection type definition - */ -typedef enum { - ADC_V11_SEL_1P0V, /*!< V11 select 1.0V */ - ADC_V11_SEL_1P1V, /*!< V11 select 1.1V */ - ADC_V11_SEL_1P18V, /*!< V11 select 1.18V */ - ADC_V11_SEL_1P26V, /*!< V11 select 1.26V */ -} ADC_V11_SEL_Type; - -/** - * @brief ADC clock type definition - */ -typedef enum { - ADC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ - ADC_CLK_DIV_4, /*!< ADC clock:on 32M clock is 8M */ - ADC_CLK_DIV_8, /*!< ADC clock:on 32M clock is 4M */ - ADC_CLK_DIV_12, /*!< ADC clock:on 32M clock is 2.666M */ - ADC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ - ADC_CLK_DIV_20, /*!< ADC clock:on 32M clock is 1.6M */ - ADC_CLK_DIV_24, /*!< ADC clock:on 32M clock is 1.333M */ - ADC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ -} ADC_CLK_Type; - -/** - * @brief ADC conversion speed type definition - */ -typedef enum { - ADC_DELAY_SEL_0, /*!< Select delay 0 */ - ADC_DELAY_SEL_1, /*!< Select delay 1 */ - ADC_DELAY_SEL_2, /*!< Select delay 2 */ - ADC_DELAY_SEL_3, /*!< Select delay 3 */ - ADC_DELAY_SEL_4, /*!< Select delay 4, not recommend */ - ADC_DELAY_SEL_5, /*!< Select delay 5, not recommend */ - ADC_DELAY_SEL_6, /*!< Select delay 6, not recommend */ - ADC_DELAY_SEL_7, /*!< Select delay 7, not recommend */ -} ADC_DELAY_SEL_Type; - -/** - * @brief ADC PGA gain type definition - */ -typedef enum { - ADC_PGA_GAIN_NONE, /*!< No PGA gain */ - ADC_PGA_GAIN_1, /*!< PGA gain 1 */ - ADC_PGA_GAIN_2, /*!< PGA gain 2 */ - ADC_PGA_GAIN_4, /*!< PGA gain 4 */ - ADC_PGA_GAIN_8, /*!< PGA gain 8 */ - ADC_PGA_GAIN_16, /*!< PGA gain 16 */ - ADC_PGA_GAIN_32, /*!< PGA gain 32 */ -} ADC_PGA_GAIN_Type; - -/** - * @brief ADC analog portion low power mode selection type definition - */ -typedef enum { - ADC_BIAS_SEL_MAIN_BANDGAP, /*!< ADC current from main bandgap */ - ADC_BIAS_SEL_AON_BANDGAP, /*!< ADC current from aon bandgap for HBN mode */ -} ADC_BIAS_SEL_Type; - -/** - * @brief ADC chop mode type definition - */ -typedef enum { - ADC_CHOP_MOD_ALL_OFF, /*!< all off */ - ADC_CHOP_MOD_AZ_ON, /*!< Vref AZ on */ - ADC_CHOP_MOD_AZ_PGA_ON, /*!< Vref AZ and PGA chop on */ - ADC_CHOP_MOD_AZ_PGA_RPC_ON, /*!< Vref AZ and PGA chop+RPC on */ -} ADC_CHOP_MOD_Type; - -/** - * @brief ADC audio PGA output common mode control type definition - */ -typedef enum { - ADC_PGA_VCM_1V, /*!< ADC VCM=1V */ - ADC_PGA_VCM_1P2V, /*!< ADC VCM=1.2V */ - ADC_PGA_VCM_1P4V, /*!< ADC VCM=1.4V */ - ADC_PGA_VCM_1P6V, /*!< ADC VCM=1.6V */ -} ADC_PGA_VCM_Type; - -/** - * @brief ADC tsen diode mode type definition - */ -typedef enum { - ADC_TSEN_MOD_INTERNAL_DIODE, /*!< Internal diode mode */ - ADC_TSEN_MOD_EXTERNAL_DIODE, /*!< External diode mode */ -} ADC_TSEN_MOD_Type; - -/** - * @brief ADC voltage reference type definition - */ -typedef enum { - ADC_VREF_3P2V, /*!< ADC select 3.2V as reference voltage */ - ADC_VREF_2P0V, /*!< ADC select 2V as reference voltage */ -} ADC_VREF_Type; - -/** - * @brief ADC signal input type definition - */ -typedef enum { - ADC_INPUT_SINGLE_END, /*!< ADC signal is single end */ - ADC_INPUT_DIFF, /*!< ADC signal is differential */ -} ADC_SIG_INPUT_Type; - -/** - * @brief ADC data width type definition - */ -typedef enum { - ADC_DATA_WIDTH_12, /*!< ADC 12 bits */ - ADC_DATA_WIDTH_14_WITH_16_AVERAGE, /*!< ADC 14 bits,and the value is average of 16 converts */ - ADC_DATA_WIDTH_14_WITH_64_AVERAGE, /*!< ADC 14 bits,and the value is average of 64 converts */ - ADC_DATA_WIDTH_16_WITH_128_AVERAGE, /*!< ADC 16 bits,and the value is average of 128 converts */ - ADC_DATA_WIDTH_16_WITH_256_AVERAGE, /*!< ADC 16 bits,and the value is average of 256 converts */ -} ADC_Data_Width_Type; - -/** - * @brief ADC micboost 32db type definition - */ -typedef enum { - ADC_MICBOOST_DB_16DB, /*!< MIC boost 16db */ - ADC_MICBOOST_DB_32DB, /*!< MIC boost 32db */ -} ADC_MICBOOST_DB_Type; - -/** - * @brief ADC pga2 gain type definition - */ -typedef enum { - ADC_PGA2_GAIN_0DB, /*!< MIC pga2 gain 0db */ - ADC_PGA2_GAIN_6DB, /*!< MIC pga2 gain 6db */ - ADC_PGA2_GAIN_N6DB, /*!< MIC pga2 gain -6db */ - ADC_PGA2_GAIN_12DB, /*!< MIC pga2 gain 12db */ -} ADC_PGA2_GAIN_Type; - -/** - * @brief ADC mic mode type definition - */ -typedef enum { - ADC_MIC_MODE_SINGLE, /*!< MIC single mode */ - ADC_MIC_MODE_DIFF, /*!< MIC diff mode */ -} ADC_MIC_MODE_Type; - -/** - * @brief ADC mic type definition - */ -typedef struct -{ - ADC_MICBOOST_DB_Type micboostDb; /*!< MIC boost db */ - ADC_PGA2_GAIN_Type micPga2Gain; /*!< MIC pga2 gain */ - ADC_MIC_MODE_Type mic1Mode; /*!< MIC1 single or diff */ - ADC_MIC_MODE_Type mic2Mode; /*!< MIC2 single or diff */ - BL_Fun_Type dwaEn; /*!< Improve dynamic performance */ - BL_Fun_Type micboostBypassEn; /*!< MIC boost amp bypass enable or disable */ - BL_Fun_Type micPgaEn; /*!< MIC pga enable or disable */ - BL_Fun_Type micBiasEn; /*!< MIC bias enable or disable */ -} ADC_MIC_Type; - -/** - * @brief ADC configuration type definition - */ -typedef struct -{ - ADC_V18_SEL_Type v18Sel; /*!< ADC 1.8V select */ - ADC_V11_SEL_Type v11Sel; /*!< ADC 1.1V select */ - ADC_CLK_Type clkDiv; /*!< Clock divider */ - ADC_PGA_GAIN_Type gain1; /*!< PGA gain 1 */ - ADC_PGA_GAIN_Type gain2; /*!< PGA gain 2 */ - ADC_CHOP_MOD_Type chopMode; /*!< ADC chop mode select */ - ADC_BIAS_SEL_Type biasSel; /*!< ADC current form main bandgap or aon bandgap */ - ADC_PGA_VCM_Type vcm; /*!< ADC VCM value */ - ADC_VREF_Type vref; /*!< ADC voltage reference */ - ADC_SIG_INPUT_Type inputMode; /*!< ADC input signal type */ - ADC_Data_Width_Type resWidth; /*!< ADC resolution and oversample rate */ - BL_Fun_Type offsetCalibEn; /*!< Offset calibration enable */ - int16_t offsetCalibVal; /*!< Offset calibration value */ -} ADC_CFG_Type; - -/** - * @brief ADC configuration type definition - */ -typedef struct -{ - int8_t posChan; /*!< Positive channel */ - int8_t negChan; /*!< Negative channel */ - uint16_t value; /*!< ADC value */ - float volt; /*!< ADC voltage result */ -} ADC_Result_Type; - -/** - * @brief ADC FIFO threshold type definition - */ -typedef enum { - ADC_FIFO_THRESHOLD_1, /*!< ADC FIFO threshold is 1 */ - ADC_FIFO_THRESHOLD_4, /*!< ADC FIFO threshold is 4 */ - ADC_FIFO_THRESHOLD_8, /*!< ADC FIFO threshold is 8 */ - ADC_FIFO_THRESHOLD_16, /*!< ADC FIFO threshold is 16 */ -} ADC_FIFO_Threshold_Type; - -/** - * @brief ADC interrupt type definition - */ -typedef enum { - ADC_INT_POS_SATURATION, /*!< ADC positive channel saturation */ - ADC_INT_NEG_SATURATION, /*!< ADC negative channel saturation */ - ADC_INT_FIFO_UNDERRUN, /*!< ADC FIFO underrun interrupt */ - ADC_INT_FIFO_OVERRUN, /*!< ADC FIFO overrun interrupt */ - ADC_INT_ADC_READY, /*!< ADC data ready interrupt */ - ADC_INT_ALL, /*!< ADC all the interrupt */ -} ADC_INT_Type; - -/** - * @brief ADC FIFO configuration structure type definition - */ -typedef struct -{ - ADC_FIFO_Threshold_Type fifoThreshold; /*!< ADC FIFO threshold */ - BL_Fun_Type dmaEn; /*!< ADC DMA enable */ -} ADC_FIFO_Cfg_Type; - -/** - * @brief ADC REG GAIN CAL - */ -typedef struct -{ - BL_Fun_Type adcGainCoeffEnable; /*!< ADC_Gain_Coeff enable */ - uint16_t adcgainCoeffVal; /*!< ADC_Gain_Coeff value */ - float coe; /*!< ADC_Gain_Coeff result */ -} ADC_Gain_Coeff_Type; - -/*@} end of group ADC_Public_Types */ - -/** @defgroup ADC_Public_Constants - * @{ - */ - -/** @defgroup ADC_CHAN_TYPE - * @{ - */ -#define IS_ADC_CHAN_TYPE(type) (((type) == ADC_CHAN0) || \ - ((type) == ADC_CHAN1) || \ - ((type) == ADC_CHAN2) || \ - ((type) == ADC_CHAN3) || \ - ((type) == ADC_CHAN4) || \ - ((type) == ADC_CHAN5) || \ - ((type) == ADC_CHAN6) || \ - ((type) == ADC_CHAN7) || \ - ((type) == ADC_CHAN8) || \ - ((type) == ADC_CHAN9) || \ - ((type) == ADC_CHAN10) || \ - ((type) == ADC_CHAN11) || \ - ((type) == ADC_CHAN_DAC_OUTA) || \ - ((type) == ADC_CHAN_DAC_OUTB) || \ - ((type) == ADC_CHAN_TSEN_P) || \ - ((type) == ADC_CHAN_TSEN_N) || \ - ((type) == ADC_CHAN_VREF) || \ - ((type) == ADC_CHAN_DCTEST) || \ - ((type) == ADC_CHAN_VABT_HALF) || \ - ((type) == ADC_CHAN_SENP3) || \ - ((type) == ADC_CHAN_SENP2) || \ - ((type) == ADC_CHAN_SENP1) || \ - ((type) == ADC_CHAN_SENP0) || \ - ((type) == ADC_CHAN_GND)) - -/** @defgroup ADC_V18_SEL_TYPE - * @{ - */ -#define IS_ADC_V18_SEL_TYPE(type) (((type) == ADC_V18_SEL_1P62V) || \ - ((type) == ADC_V18_SEL_1P72V) || \ - ((type) == ADC_V18_SEL_1P82V) || \ - ((type) == ADC_V18_SEL_1P92V)) - -/** @defgroup ADC_V11_SEL_TYPE - * @{ - */ -#define IS_ADC_V11_SEL_TYPE(type) (((type) == ADC_V11_SEL_1P0V) || \ - ((type) == ADC_V11_SEL_1P1V) || \ - ((type) == ADC_V11_SEL_1P18V) || \ - ((type) == ADC_V11_SEL_1P26V)) - -/** @defgroup ADC_CLK_TYPE - * @{ - */ -#define IS_ADC_CLK_TYPE(type) (((type) == ADC_CLK_DIV_1) || \ - ((type) == ADC_CLK_DIV_4) || \ - ((type) == ADC_CLK_DIV_8) || \ - ((type) == ADC_CLK_DIV_12) || \ - ((type) == ADC_CLK_DIV_16) || \ - ((type) == ADC_CLK_DIV_20) || \ - ((type) == ADC_CLK_DIV_24) || \ - ((type) == ADC_CLK_DIV_32)) - -/** @defgroup ADC_DELAY_SEL_TYPE - * @{ - */ -#define IS_ADC_DELAY_SEL_TYPE(type) (((type) == ADC_DELAY_SEL_0) || \ - ((type) == ADC_DELAY_SEL_1) || \ - ((type) == ADC_DELAY_SEL_2) || \ - ((type) == ADC_DELAY_SEL_3) || \ - ((type) == ADC_DELAY_SEL_4) || \ - ((type) == ADC_DELAY_SEL_5) || \ - ((type) == ADC_DELAY_SEL_6) || \ - ((type) == ADC_DELAY_SEL_7)) - -/** @defgroup ADC_PGA_GAIN_TYPE - * @{ - */ -#define IS_ADC_PGA_GAIN_TYPE(type) (((type) == ADC_PGA_GAIN_NONE) || \ - ((type) == ADC_PGA_GAIN_1) || \ - ((type) == ADC_PGA_GAIN_2) || \ - ((type) == ADC_PGA_GAIN_4) || \ - ((type) == ADC_PGA_GAIN_8) || \ - ((type) == ADC_PGA_GAIN_16) || \ - ((type) == ADC_PGA_GAIN_32)) - -/** @defgroup ADC_BIAS_SEL_TYPE - * @{ - */ -#define IS_ADC_BIAS_SEL_TYPE(type) (((type) == ADC_BIAS_SEL_MAIN_BANDGAP) || \ - ((type) == ADC_BIAS_SEL_AON_BANDGAP)) - -/** @defgroup ADC_CHOP_MOD_TYPE - * @{ - */ -#define IS_ADC_CHOP_MOD_TYPE(type) (((type) == ADC_CHOP_MOD_ALL_OFF) || \ - ((type) == ADC_CHOP_MOD_AZ_ON) || \ - ((type) == ADC_CHOP_MOD_AZ_PGA_ON) || \ - ((type) == ADC_CHOP_MOD_AZ_PGA_RPC_ON)) - -/** @defgroup ADC_PGA_VCM_TYPE - * @{ - */ -#define IS_ADC_PGA_VCM_TYPE(type) (((type) == ADC_PGA_VCM_1V) || \ - ((type) == ADC_PGA_VCM_1P2V) || \ - ((type) == ADC_PGA_VCM_1P4V) || \ - ((type) == ADC_PGA_VCM_1P6V)) - -/** @defgroup ADC_TSEN_MOD_TYPE - * @{ - */ -#define IS_ADC_TSEN_MOD_TYPE(type) (((type) == ADC_TSEN_MOD_INTERNAL_DIODE) || \ - ((type) == ADC_TSEN_MOD_EXTERNAL_DIODE)) - -/** @defgroup ADC_VREF_TYPE - * @{ - */ -#define IS_ADC_VREF_TYPE(type) (((type) == ADC_VREF_3P3V) || \ - ((type) == ADC_VREF_2V)) - -/** @defgroup ADC_SIG_INPUT_TYPE - * @{ - */ -#define IS_ADC_SIG_INPUT_TYPE(type) (((type) == ADC_INPUT_SINGLE_END) || \ - ((type) == ADC_INPUT_DIFF)) - -/** @defgroup ADC_DATA_WIDTH_TYPE - * @{ - */ -#define IS_ADC_DATA_WIDTH_TYPE(type) (((type) == ADC_DATA_WIDTH_12) || \ - ((type) == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_14_WITH_64_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || \ - ((type) == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) - -/** @defgroup ADC_MICBOOST_DB_TYPE - * @{ - */ -#define IS_ADC_MICBOOST_DB_TYPE(type) (((type) == ADC_MICBOOST_DB_16DB) || \ - ((type) == ADC_MICBOOST_DB_32DB)) - -/** @defgroup ADC_PGA2_GAIN_TYPE - * @{ - */ -#define IS_ADC_PGA2_GAIN_TYPE(type) (((type) == ADC_PGA2_GAIN_0DB) || \ - ((type) == ADC_PGA2_GAIN_6DB) || \ - ((type) == ADC_PGA2_GAIN_N6DB) || \ - ((type) == ADC_PGA2_GAIN_12DB)) - -/** @defgroup ADC_MIC_MODE_TYPE - * @{ - */ -#define IS_ADC_MIC_MODE_TYPE(type) (((type) == ADC_MIC_MODE_SINGLE) || \ - ((type) == ADC_MIC_MODE_DIFF)) - -/** @defgroup ADC_FIFO_THRESHOLD_TYPE - * @{ - */ -#define IS_ADC_FIFO_THRESHOLD_TYPE(type) (((type) == ADC_FIFO_THRESHOLD_1) || \ - ((type) == ADC_FIFO_THRESHOLD_4) || \ - ((type) == ADC_FIFO_THRESHOLD_8) || \ - ((type) == ADC_FIFO_THRESHOLD_16)) - -/** @defgroup ADC_INT_TYPE - * @{ - */ -#define IS_ADC_INT_TYPE(type) (((type) == ADC_INT_POS_SATURATION) || \ - ((type) == ADC_INT_NEG_SATURATION) || \ - ((type) == ADC_INT_FIFO_UNDERRUN) || \ - ((type) == ADC_INT_FIFO_OVERRUN) || \ - ((type) == ADC_INT_ADC_READY) || \ - ((type) == ADC_INT_ALL)) - -/*@} end of group ADC_Public_Constants */ - -/** @defgroup ADC_Public_Macros - * @{ - */ - -/*@} end of group ADC_Public_Macros */ - -/** @defgroup ADC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void GPADC_DMA_IRQHandler(void); -#endif -void ADC_Vbat_Enable(void); -void ADC_Vbat_Disable(void); -void ADC_Reset(void); -void ADC_Enable(void); -void ADC_Disable(void); -void ADC_Init(ADC_CFG_Type *cfg); -void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn); -void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn); -void ADC_Start(void); -void ADC_Stop(void); -void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg); -uint8_t ADC_Get_FIFO_Count(void); -BL_Sts_Type ADC_FIFO_Is_Empty(void); -BL_Sts_Type ADC_FIFO_Is_Full(void); -void ADC_FIFO_Clear(void); -uint32_t ADC_Read_FIFO(void); -void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result); -void ADC_IntClr(ADC_INT_Type intType); -BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType); -BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType); -void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun); -void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask); -void ADC_SET_TSVBE_LOW(void); -void ADC_SET_TSVBE_HIGH(void); -void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod); -void ADC_Tsen_Enable(void); -void ADC_Tsen_Disable(void); -void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal); -BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config); -void ADC_MIC_Bias_Disable(void); -void ADC_MIC_Bias_Enable(void); -BL_Err_Type ADC_Trim_TSEN(uint16_t *tsen_offset); -BL_Err_Type ADC_Gain_Trim(void); -uint32_t ADC_Cal_Reg_Coeff_Value(uint32_t raw_reg); -float TSEN_Get_Temp(uint32_t tsen_offset); - -/*@} end of group ADC_Public_Functions */ - -/*@} end of group ADC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_ADC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_audio.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_audio.h deleted file mode 100644 index 63b81cd65e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_audio.h +++ /dev/null @@ -1,971 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_audio.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_AUDIO_H__ -#define __BL808_AUDIO_H__ - -#include "audio_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIO - * @{ - */ - -/** @defgroup AUDIO_Public_Types - * @{ - */ - -/** - * @brief Audio ADC ID - */ -typedef enum { - AUDIO_ADC_0, /*!< Audio ADC 0 */ - AUDIO_ADC_1, /*!< Audio ADC 1 */ - AUDIO_ADC_2, /*!< Audio ADC 2 */ -} Audio_ADC_ID_Type; - -/** - * @brief Audio DAC ID - */ -typedef enum { - AUDIO_DAC_0, /*!< Audio DAC 0 */ - AUDIO_DAC_1, /*!< Audio DAC 1 */ -} Audio_DAC_ID_Type; - -/** - * @brief Audio AEC ID - */ -typedef enum { - AUDIO_AEC_0, /*!< Audio AEC 0 */ - AUDIO_AEC_1, /*!< Audio AEC 1 */ -} Audio_AEC_ID_Type; - -/** - * @brief Audio PDM ID - */ -typedef enum { - AUDIO_PDM_0, /*!< select PDM Channel 0 */ - AUDIO_PDM_1, /*!< select PDM Channel 1 */ - AUDIO_PDM_2, /*!< select PDM Channel 2 */ -} Audio_PDM_ID_Type; - -/** - * @brief Audio MUTE - */ -typedef enum { - AUDIO_UNMUTE, /*!< unmute */ - AUDIO_MUTE, /*!< mute */ -} Audio_Mute_Type; - -/** - * @brief Audio ADC Clock - */ -typedef enum { - AUDIO_ADC_8_KHZ, /*!< Audio ADC Clock set as 8KHZ */ - AUDIO_ADC_16_KHZ, /*!< Audio ADC Clock set as 16KHZ */ - AUDIO_ADC_24_KHZ, /*!< Audio ADC Clock set as 24KHZ */ - AUDIO_ADC_32_KHZ, /*!< Audio ADC Clock set as 32KHZ */ - AUDIO_ADC_48_KHZ, /*!< Audio ADC Clock set as 48KHZ */ - AUDIO_ADC_96_KHZ, /*!< Audio ADC Clock set as 96KHZ */ -} Audio_ADC_Clock_Type; - -/** - * @brief Audio DAC Clock - */ -typedef enum { - AUDIO_DAC_8_KHZ, /*!< Audio DAC Clock set as 8KHZ */ - AUDIO_DAC_16_KHZ, /*!< Audio DAC Clock set as 16KHZ */ - AUDIO_DAC_24_KHZ, /*!< Audio DAC Clock set as 24KHZ */ - AUDIO_DAC_32_KHZ, /*!< Audio DAC Clock set as 32KHZ */ - AUDIO_DAC_48_KHZ, /*!< Audio DAC Clock set as 48KHZ */ - AUDIO_DAC_96_KHZ, /*!< Audio DAC Clock set as 96KHZ */ - AUDIO_DAC_192_KHZ, /*!< Audio DAC Clock set as 192KHZ */ -} Audio_DAC_Clock_Type; - -/** - * @brief Audio ADC Source Interface - */ -typedef enum { - AUDIO_ADC_ANALOG, /*!< set AUDIO ADC as ANALOG mode connect AMIC */ - AUDIO_ADC_PDM, /*!< set AUDIO ADC as PDM mode connect to DMIC */ -} Audio_ADC_Source_Type; - -/** - * @brief Audio LSFR Type - */ -typedef enum { - AUDIO_LFSR32, /*!< Audio LFSR32 */ - AUDIO_LFSR24, /*!< Audio LFSR24 */ - AUDIO_LFSR16, /*!< Audio LFSR16 */ - AUDIO_LFSR12, /*!< Audio LFSR12 */ -} Audio_LFSR_Type; - -/** - * @brief Audio Mixer Mode - */ -typedef enum { - AUDIO_SECOND_DEBUG_MODE = 0x1, /*!< Audio second mode debug mode */ - AUDIO_SIDETONE_LOOPBACK = 0x2, /*!< Audio sidetone mode mix will mixer dac with adc data */ -} Audio_Mixer_Mode; - -/** - * @brief Audio Mixer Volume Type - */ -typedef enum { - AUDIO_MIXER_VOLUME_0_DB, /*!< Audio Mix Volume 0DB */ - AUDIO_MIXER_VOLUME_6_DB, /*!< Audio Mix Volume 6DB */ - AUDIO_MIXER_VOLUME_12_DB, /*!< Audio Mix Volume 12DB */ - AUDIO_MIXER_VOLUME_18_DB, /*!< Audio Mix Volume 18DB */ - AUDIO_MIXER_VOLUME_36_DB, /*!< Audio Mix Volume 36DB */ - AUDIO_MIXER_VOLUME_54_DB, /*!< Audio Mix Volume 54DB */ - AUDIO_MIXER_VOLUME_72_DB, /*!< Audio Mix Volume 72DB */ - AUDIO_MIXER_VOLUME_MUTE, /*!< Audio Mix Volume Mute */ -} Audio_Mixer_Volume_Type; - -/** - * @brief Audio Mixer ID - */ -typedef enum { - AUDIO_MIXER_ID_0, /*!< Audio Mix ID 0 */ - AUDIO_MIXER_ID_1, /*!< Audio Mix ID 1 */ -} Audio_Mixer_ID_Type; - -/** - * @brief Audio dac order - */ -typedef enum { - AUDIO_DAC_2_ORDER, /*!< Audio ORDER 2 */ - AUDIO_DAC_3_ORDER, /*!< Audio ORDER 3 */ -} Audio_DAC_Order_Type; - -/** - * @brief Audio aec attenuation mode - */ -typedef enum { - AUDIO_AEC_NO_DROP, /*!< DROP 0 LSB */ - AUDIO_AEC_DROP_1LSB, /*!< DROP 1 LSB */ - AUDIO_AEC_DROP_2LSB, /*!< DROP 2 LSB */ - AUDIO_AEC_DROP_3LSB, /*!< DROP 3 LSB */ - AUDIO_AEC_DROP_6LSB, /*!< DROP 6 LSB */ - AUDIO_AEC_DROP_9LSB, /*!< DROP 9 LSB */ - AUDIO_AEC_DROP_12LSB, /*!< DROP 12 LSB */ -} Audio_AEC_Atten_Mode; - -/** - * @brief Audio PDM Source Select - */ -typedef enum { - AUDIO_PDM_0_L, /*!< select PDM0 Left Channel */ - AUDIO_PDM_0_R, /*!< select PDM0 Right Channel */ - AUDIO_PDM_1_L, /*!< select PDM1 Left Channel */ - AUDIO_PDM_1_R, /*!< select PDM1 Right Channel */ - AUDIO_PDM_2_L, /*!< select PDM2 Left Channel */ - AUDIO_PDM_2_R, /*!< select PDM2 Right Channel */ -} Audio_PDM_Source_Type; - -/** - * @brief Audio Resolution - */ -typedef enum { - AUDIO_RES_16_BITS, /*!< select ADC Resolution as 16 bit */ - AUDIO_RES_20_BITS, /*!< select ADC Resolution as 20 bit */ -} Audio_Resolution_Type; - -/** - * @brief Audio Resolution - */ -typedef enum { - AUDIO_FIFO_AILGN_MSB_AT_BIT31, /*!< Mode 0: Valid data's MSB is at [31] of FIFO register */ - AUDIO_FIFO_AILGN_MSB_AT_BIT23, /*!< Mode 1: Valid data's MSB is at [23] of FIFO register */ - AUDIO_FIFO_AILGN_MSB_AT_BIT19, /*!< Mode 2: Valid data's MSB is at [19] of FIFO register */ - AUDIO_FIFO_AILGN_MSB_AT_BIT15, /*!< Mode 3: Valid data's MSB is at [15] of FIFO register */ -} Audio_FIFO_Ailgn_Mode; - -/** - * @brief Audio Resolution - */ -typedef enum { - AUDIO_DRQ_EQUEL_TO_IRQ, /*!< DMA request threhold is equeal to Interrupt threhold */ - AUDIO_DRQ_THR_AS_4_TX_8_RX, /*!< DMA request threhold is 4 when config TX FIFO DRQ , 8 when config RX FIFO */ - AUDIO_DRQ_THR_AS_8_TX_16_RX, /*!< DMA request threhold is 8 when config TX FIFO DRQ , 16 when config RX FIFO */ - AUDIO_DRQ_THR_AS_16_TX_32_RX, /*!< DMA request threhold is 16 when config TX FIFO DRQ , 32 when config RX FIFO */ -} Audio_FIFO_DQR_Threshold_Mode; - -/** - * @brief Audio initerrupt type - */ -typedef enum { - AUDIO_INT_RX_FIFO_THR, /*!< Audio RX FIFO counter upper than threhold interrupt */ - AUDIO_INT_RX_FIFO_OVERRUN, /*!< Audio RX FIFO overrun */ - AUDIO_INT_RX_FIFO_UNDERRUN, /*!< Audio RX FIFO underrun */ - AUDIO_INT_TX_FIFO_THR, /*!< Audio TX FIFO THL */ - AUDIO_INT_TX_FIFO_OVERRUN, /*!< Audio TX FIFO overrun */ - AUDIO_INT_TX_FIFO_UNDERRUN, /*!< Audio TX FIFO underrun */ - AUDIO_INT_ADC0_SET_VOLUME_DONE, /*!< Audio set ADC0 volume done */ - AUDIO_INT_ADC1_SET_VOLUME_DONE, /*!< Audio set ADC1 volume done */ - AUDIO_INT_ADC2_SET_VOLUME_DONE, /*!< Audio set ADC2 volume done */ - AUDIO_INT_DAC0_SET_VOLUME_DONE, /*!< Audio set DAC0 volume done */ - AUDIO_INT_DAC1_SET_VOLUME_DONE, /*!< Audio set DAC1 volume done */ - AUDIO_INT_VAD, /*!< Audio VAD */ - AUDIO_INT_NUM_ALL, /*!< Audio int all */ -} Audio_INT_Type; - -/** - * @brief Audio peq qtfm - */ -typedef enum { - AUDIO_PEQ_QFMT_20_17, /*!< Audio QFMT 20.17 */ - AUDIO_PEQ_QFMT_20_16, /*!< Audio QFMT 20.16 */ -} Audio_PEQ_QTFM_Type; - -/** - * @brief Audio mute mode - */ -typedef enum { - AUIDO_MUTE_DIRECTLY, /*!< mute directly */ - AUDIO_MUTE_WITH_RAMP_DOWN, /*!< mute with rampdown */ -} Audio_Mute_Mode; - -/** - * @brief Audio ramp rate - */ -typedef enum { - AUIDO_RAMP_RATE_2_FS, /*!< ramp rate 2 fs */ - AUIDO_RAMP_RATE_4_FS, /*!< ramp rate 4 fs */ - AUIDO_RAMP_RATE_8_FS, /*!< ramp rate 8 fs */ - AUIDO_RAMP_RATE_16_FS, /*!< ramp rate 16 fs */ - AUIDO_RAMP_RATE_32_FS, /*!< ramp rate 32 fs */ - AUIDO_RAMP_RATE_64_FS, /*!< ramp rate 64 fs */ - AUIDO_RAMP_RATE_128_FS, /*!< ramp rate 128 fs */ - AUIDO_RAMP_RATE_256_FS, /*!< ramp rate 256 fs */ - AUIDO_RAMP_RATE_512_FS, /*!< ramp rate 512 fs */ - AUIDO_RAMP_RATE_1024_FS, /*!< ramp rate 1024 fs */ - AUIDO_RAMP_RATE_2048_FS, /*!< ramp rate 2048 fs */ -} Audio_Ramp_Rate_Type; - -/** - * @brief Audio zero cross rate - */ -typedef enum { - AUIDO_ZERO_CROSS_RATE_2_FS, /*!< ramp rate 2 fs */ - AUIDO_ZERO_CROSS_RATE_4_FS, /*!< ramp rate 4 fs */ - AUIDO_ZERO_CROSS_RATE_8_FS, /*!< ramp rate 8 fs */ - AUIDO_ZERO_CROSS_RATE_16_FS, /*!< ramp rate 16 fs */ - AUIDO_ZERO_CROSS_RATE_32_FS, /*!< ramp rate 32 fs */ - AUIDO_ZERO_CROSS_RATE_64_FS, /*!< ramp rate 64 fs */ - AUIDO_ZERO_CROSS_RATE_128_FS, /*!< ramp rate 128 fs */ - AUIDO_ZERO_CROSS_RATE_256_FS, /*!< ramp rate 256 fs */ - AUIDO_ZERO_CROSS_RATE_512_FS, /*!< ramp rate 512 fs */ - AUIDO_ZERO_CROSS_RATE_1024_FS, /*!< ramp rate 1024 fs */ - AUIDO_ZERO_CROSS_RATE_2048_FS, /*!< ramp rate 2048 fs */ -} Audio_Zero_Cross_Rate_Type; - -/** - * @brief Audio volume ctr mode - */ -typedef enum { - AUIDO_VOLUME_UPDATE_FORCE, /*!< volume update force */ - AUIDO_VOLUME_UPDATE_AT_ZERO_CROSSING, /*!< volume update at zero crossing */ - AUIDO_VOLUME_UPDATE_AT_RAMP, /*!< volume update at zero crossing */ -} Audio_Volume_Ctr_Mode; - -/** - * @brief Audio_AGC_Detect_Mode - */ -typedef enum { - AUIDO_AGC_DETECT_BY_PEAK, /*!< detect by peak */ - AUIDO_AGC_DETECT_BY_AVERAGE, /*!< detect by average */ -} Audio_AGC_Detect_Mode; - -/** - * @brief Audio_AGC_Src_Type - */ -typedef enum { - AUIDO_AGC_CH0_ABSOLUTE_VALUE, /*!< Audio AGC CH0 */ - AUIDO_AGC_CH1_ABSOLUTE_VALUE, /*!< Audio AGC CH1 */ - AUIDO_AGC_CH2_ABSOLUTE_VALUE, /*!< Audio AGC CH2 */ - AUIDO_AGC_MAXIMUM_VALUE_OF_CH012, /*!< Audio AGC Max value of ch012 */ -} Audio_AGC_Src_Type; - -/** - * @brief Auido_DRC_Data_Type - */ -typedef enum { - AUIDO_DRC_DATA_SOURCE_CH0, /*!< Audio DRC SOURCE CH0 */ - AUIDO_DRC_DATA_SOURCE_CH1, /*!< Audio DRC SOURCE CH1 */ - AUIDO_DRC_DATA_SOURCE_AVERAGE_OF_CH0_CH1, /*!< Audio DRC SOURCE (CH0+CH1)/2 */ - AUIDO_DRC_DATA_SOURCE_MAX_OF_CH0_CH1, /*!< Audio DRC MAX(CH0,CH1) */ -} Auido_DRC_Data_Type; - -/** - * @brief Auido_VAD_Source_Type - */ -typedef enum { - AUIDO_VAD_DATA_SOURCE_ADC_CH0, /*!< Audio ADC CH0 */ - AUIDO_VAD_DATA_SOURCE_ADC_CH1, /*!< Audio ADC CH1 */ - AUIDO_VAD_DATA_SOURCE_ADC_CH2, /*!< Audio ADC CH2 */ - AUIDO_VAD_DATA_SOURCE_AEC_CH0, /*!< Audio AEC CH0 */ - AUIDO_VAD_DATA_SOURCE_AEC_CH1, /*!< Audio AEC CH1 */ - AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH0_ADD_CH1, /*!< Audio (ADC0+ADC1)/2 */ - AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH1_ADD_CH2, /*!< Audio (ADC1+ADC2)/2 */ - AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH2_ADD_CH0, /*!< Audio (ADC2+ADC0)/2 */ -} Auido_VAD_Source_Type; - -/** - * @brief Auido_VAD_FramingShift_Type - */ -typedef enum { - AUIDO_VAD_FRAMING_SHIFT_2P5_MS, /*!< Audio VAD FramingShift = 2.5 */ - AUIDO_VAD_FRAMING_SHIFT_5_MS, /*!< Audio VAD FramingShift = 5 */ - AUIDO_VAD_FRAMING_SHIFT_7P5_MS, /*!< Audio VAD FramingShift = 7.5 */ - AUIDO_VAD_FRAMING_SHIFT_10_MS, /*!< Audio VAD FramingShift = 10 */ - AUIDO_VAD_FRAMING_SHIFT_12P5_MS, /*!< Audio VAD FramingShift = 12.5 */ - AUIDO_VAD_FRAMING_SHIFT_15_MS, /*!< Audio VAD FramingShift = 15 */ - AUIDO_VAD_FRAMING_SHIFT_17P5_MS, /*!< Audio VAD FramingShift = 17.5 */ - AUIDO_VAD_FRAMING_SHIFT_20_MS, /*!< Audio VAD FramingShift = 20 */ -} Auido_VAD_FramingShift_Type; - -/** - * @brief Auido_VAD_FramingTime_Type - */ -typedef enum { - AUIDO_VAD_FRAMING_TIME_2, /*!< Audio VAD FramingTime K= 2 */ - AUIDO_VAD_FRAMING_TIME_3, /*!< Audio VAD FramingTime K= 3 */ - AUIDO_VAD_FRAMING_TIME_4, /*!< Audio VAD FramingTime K= 4 */ - AUIDO_VAD_FRAMING_TIME_5, /*!< Audio VAD FramingTime K= 5 */ -} Auido_VAD_FramingTime_Type; - -/** - * @brief Auido_VAD_FramingTime_Type - */ -typedef enum { - AUIDO_VAD_ORIGINAL_OUTPUT, /*!< Original VAD output(VAD00) */ - AUIDO_VAD_OUT0, /*!< Debounced VAD output(VADout0), with small NDV but large DL */ - AUIDO_VAD_OUT1, /*!< Debounced VAD output(VADout1) */ - AUIDO_VAD_OUT2, /*!< Debounced VAD output(VADout2), with small DL but large NDV */ -} Auido_VAD_IRQ_Source_Type; - -/** - * @brief Auido_VAD_NoisyBufferLen_Type - */ -typedef enum { - AUIDO_VAD_NOISY_BUF_LEN_4, /*!< noise buffer length control 4 */ - AUIDO_VAD_NOISY_BUF_LEN_8, /*!< noise buffer length control 8 */ - AUIDO_VAD_NOISY_BUF_LEN_12, /*!< noise buffer length control 12 */ - AUIDO_VAD_NOISY_BUF_LEN_16, /*!< noise buffer length control 16 */ - AUIDO_VAD_NOISY_BUF_LEN_20, /*!< noise buffer length control 20 */ - AUIDO_VAD_NOISY_BUF_LEN_24, /*!< noise buffer length control 24 */ - AUIDO_VAD_NOISY_BUF_LEN_28, /*!< noise buffer length control 28 */ - AUIDO_VAD_NOISY_BUF_LEN_32, /*!< noise buffer length control 32 */ -} Auido_VAD_NoisyBufferLen_Type; - -/** - * @brief noise buffer monitor control, forcing noise buffer to refresh when both:VAD goes into high and VAD high last for2'h0: 1s2'h1: 2s2'h2: 4s 2'h3: 8s this monit function is designed in case that VAD is locked into active state and noise buffer no longer refreshes itself. this will happen when audio-background-noise suddenly changes from a relative low level to a much higher one - */ -typedef enum { - AUIDO_VAD_NOISY_MONITOR_1_S, /*!< noise monitor 1 s */ - AUIDO_VAD_NOISY_MONITOR_2_S, /*!< noise monitor 2 s */ - AUIDO_VAD_NOISY_MONITOR_4_S, /*!< noise monitor 4 s */ - AUIDO_VAD_NOISY_MONITOR_8_S, /*!< noise monitor 8 s */ -} Auido_VAD_NoisyBufferMonitor_Type; - -/** - * @brief Audio Clock Configuration - */ -typedef struct { - Audio_ADC_Clock_Type adc_clock; /*!< ADC Rate Configuration */ - Audio_DAC_Clock_Type dac_clock; /*!< DAC Rate Configuration */ - BL_Fun_Type pdm_clk_inv; /*!< enable or not pdm clock inv */ - BL_Fun_Type adc_clk_inv; /*!< enable or not adc clock inv */ - BL_Fun_Type dac_clk_inv; /*!< enable or not dac clock inv */ -} Audio_Clock_CFG_Type; - -/** - * @brief Audio FIFO Configuration - */ -typedef struct { - Audio_Resolution_Type resolution; /*!< Receiving Audio Sample Resolution */ - Audio_FIFO_Ailgn_Mode ailgnMode; /*!< FIFO alignMode */ - uint8_t FifoIntThreshold; /*!< FIFO IRQ Threshold */ - Audio_FIFO_DQR_Threshold_Mode dmaThresholdMode; /*!< FIFO DRQ Threshold mode */ - BL_Fun_Type dmaEn; /*!< enable DMA FIFO interface */ -} Audio_FifoCfg_Type; - -/** - * @brief Audio Volume Configuration - */ -typedef struct { - Audio_Mute_Mode muteMode; /*!< Audio mute mode directly mute or use ramp down */ - Audio_Ramp_Rate_Type muteRmpdnRate; /*!< mute ramp down rate when voice is in up process this parameter define slope */ - Audio_Ramp_Rate_Type muteRmpupRate; /*!< mute ramp up rate when voice is in down process this parameter define slop */ - Audio_Volume_Ctr_Mode volumeCtrMode; /*!< volume will update at direct or zero crossing or ramp */ - Audio_Zero_Cross_Rate_Type volumeZeroCrossRate; /*!< when volume ctrl is zero crossing , select crossing rate */ - Audio_Ramp_Rate_Type volumeRmpRate; /*!< when volume ctrl is ramp ,select ramp rate */ - Audio_Zero_Cross_Rate_Type volumeZeroCrossTimeout; /*!< if select zero cross mode , set volume directly when time out */ -} Audio_Volume_Cfg_Type; - -/** - * @brief Audio VAD Configuration - */ -typedef struct { - Auido_VAD_Source_Type vadSource; /*!< VAD source select */ - Auido_VAD_FramingShift_Type vadFramingShift; /*!< framing-shift control */ - Auido_VAD_FramingTime_Type vadFramingTime; /*!< framing-time control, K times of framing-shift */ - Auido_VAD_IRQ_Source_Type vadIRQSource; /*!< select witch VAD output as final IRQ */ - BL_Fun_Type vadNoisyBufferMonitorEnable; /*!< enable or not noisy buffer monitor */ - Auido_VAD_NoisyBufferLen_Type vadNoisyBufferLen; /*!< noise buffer length control */ - Auido_VAD_NoisyBufferMonitor_Type vadNoisyBufferMonitor; /*!< this monit function is designed in case that VAD is locked into active state and noise buffer - no longer refreshes itself. this will happen when audio-background-noise suddenly changes from a - relative low level to a much higher one */ - uint32_t noisyBufferThr; /*!< vad_noise_th */ - uint8_t noisyBufferDiscardNumber; /*!< noise buffer discard number: */ - uint16_t noisyBufferThrBais; /*!< bias for noise threshold(s8.8, 2's) */ - uint8_t noisyBufferThrScale; /*!< noise threshold scale factor, real scale factor in circuit=dec(nth_scale)/256 */ - uint16_t vadNoisyMaxLimit; /*!< noise threshold max limitation */ - BL_Fun_Type vadNoisyMaxLimitEnable; /*!< noise threshold max limitation enable signal */ - uint16_t vadNoisyMinLimit; /*!< noise threshold min limitation */ - BL_Fun_Type vadNoisyMinLimitEnable; /*!< noise threshold min limitation enable signal */ - uint16_t vadSmoothRise; /*!< VAD output debouce, remove the positive pulse whose width is smaller than Register Value, the - real debouce time = Resister Vale * framing-shift */ - uint16_t vadSmoothFall; /*!< VAD output debouce, remove the negative pulse whose width is smaller than Register Value, the - real debouce time = Resister Vale * framing-shift */ -} Audio_VAD_Cfg_Type; - -/** - * @brief Audio agc Config - */ -typedef struct { - BL_Fun_Type agc_force_gain_en; /*!< 1 force agc gain */ - uint16_t agc_force_gain_ind; /*!< force agc gain index //default 0 -6-24 */ - uint16_t agc_max_gain_qdb; /*!< agc maximun gain //default 24 -6-24 */ - uint16_t agc_min_gain_qdb; /*!< agc minimum gain */ - uint8_t agc_level_target; /*!< agc level target //default-12 -6--20 */ - uint8_t agc_level_hyst_attack; /*!< agc level hysteresis attack */ - uint8_t agc_level_hyst_decay; /*!< agc level hysteresis decay */ - uint8_t agc_hold_time_ms; /*!< agc hold time(ms)//0-32,1-64,2-96,3-128,4-256,5-512 default 96 */ - uint8_t agc_decay_time_ms; /*!< agc decay time(ms) //0-32,1-64,2-96,3-128,4-256,5-512 default 64 */ - uint8_t agc_attack_time_ms; /*!< agc attack time(ms) //0-8,1-16,2-24,3-32,4-64,5-128 default 16 */ - BL_Fun_Type adc3_pga_hw_ctrl; /*!< 1 enable hw control */ - BL_Fun_Type adc2_pga_hw_ctrl; /*!< 1 enable hw control */ - BL_Fun_Type adc1_pga_hw_ctrl; /*!< 1 enable hw control */ - uint8_t agc_noise_gate_th; /*!< agc noise gate threshold //default -48 -32--72 */ - uint8_t agc_noise_gate_hyst; /*!< agc noise gate hysteresis //default 2 0/1/2/4 */ - uint8_t agc_silence_gain_qdb; /*!< agc silence gain qdb //s9.2, default 0 */ - uint8_t agc_silence_gain_wait_ms; /*!< agc silence gain wait time(ms) */ - uint8_t agc_noise_enter_time_ms; /*!< agc noise enter time //default 0 NORMAL_SILENCE_DEBOUNCE_TIME_MS 0/1/2/4/8/16/32/64/96/128 */ - uint8_t agc_noise_exit_time_ms; /*!< agc noise exit time(ms) //default 0 SILENCE_NORMAL_DEBOUNCE_TIME_MS 0/1/2/4/8/16/32/64/96/128 */ - uint8_t agc_dbv_settle_time; /*!< agc dbv settle time */ - Audio_AGC_Src_Type agc_src_select; /*!< agc source select 0 ch0 absolute value, 1 ch1 absolute value, 2 ch2 absolute value, 3 maximum - value of ch0/1/2 */ - Audio_AGC_Detect_Mode agc_detect_mode; /*!< 0 detect by peak, 1 detect by average */ - uint8_t agc_attack_time; /*!< agc peak filter attack time */ - uint8_t agc_release_time; /*!< agc peak filter release time */ - uint8_t agc_average_time; /*!< agc rms filter average time */ - BL_Fun_Type agc_pga_ctrl_en; /*!< 1 enable pga controlled by hw agc */ -} Audio_AGC_Config_Type; - -/** - * @brief Audio agc Config - */ -typedef struct { - Auido_DRC_Data_Type drc_raw_sel; /*!< drc raw data select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - Auido_DRC_Data_Type drc_peak_sel; /*!< drc peak data select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - Auido_DRC_Data_Type drc_avg_sel; /*!< drc average data select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - BL_Fun_Type drc_avg_en; /*!< 1 enable average filter */ - uint8_t drc_avg_time; /*!< drc average filter period */ - uint8_t drc_att_time; /*!< drc peak filter attack time */ - uint8_t drc_rls_time; /*!< drc peak filter release time */ - uint8_t drc_ngt_downsample_en; /*!< 1 drc and noise gate down sample by dac_rate */ - uint8_t drc_threshold_l; /*!< drc threshold of limiter */ - uint8_t drc_threshold_c; /*!< drc threshold of compressor */ - uint8_t drc_threshold_e; /*!< drc threshold of expander */ - uint8_t drc_slope_mode_c; /*!< drc compressor slope mode 0 1-8/8, 1 1-5/8, 2 1-4/8, 3 1-2/8 */ - uint8_t drc_slope_mode_e; /*!< drc expander slope mode 0 0, 1 -1, 2 -2, 3 -3 */ - uint8_t drc_makeup_gain; /*!< drc make up gain */ - uint8_t drc_attack_time; /*!< drc attack time */ - uint8_t drc_release_time; /*!< drc release time */ - BL_Fun_Type ngt_en; /*!< 1 enable noise gate */ - Auido_DRC_Data_Type ngt_src_sel; /*!< noise gate source select 0 ch0, 1 ch1, 2 (ch0+ch1)/2, 3 max(ch0,ch1) */ - uint8_t ngt_avg_time; /*!< noise gate average time */ - uint8_t ngt_threshold; /*!< noise gate threshold */ - uint8_t ngt_hysteresis; /*!< noise gate hysteresis */ - BL_Fun_Type ngt_noise_hold_en; /*!< noise hold enable */ - uint8_t ngt_noise_hold_time_k; /*!< noise hold time k */ - BL_Fun_Type ngt_signal_hold_en; /*!< signal hold enable */ - uint8_t ngt_signal_hold_time_k; /*!< signal hold time k */ - BL_Fun_Type ngt_dmute_on; /*!< 1 enanle noise gate mute hw */ - BL_Fun_Type zd_en; /*!< two channels, 0 zd disabled, 1 zd on channel0, 2 zd on channel1, 3 zd on both channels */ - uint16_t zd_time; /*!< number of zeros */ -} Audio_DRC_Config_Type; - -/*@} end of group AUDIO_Public_Types */ - -/** @defgroup AUDIO_Public_Constants - * @{ - */ - -/** @defgroup AUDIO_ADC_ID_TYPE - * @{ - */ -#define IS_AUDIO_ADC_ID_TYPE(type) (((type) == AUDIO_ADC_0) || \ - ((type) == AUDIO_ADC_1) || \ - ((type) == AUDIO_ADC_2)) - -/** @defgroup AUDIO_DAC_ID_TYPE - * @{ - */ -#define IS_AUDIO_DAC_ID_TYPE(type) (((type) == AUDIO_DAC_0) || \ - ((type) == AUDIO_DAC_1)) - -/** @defgroup AUDIO_AEC_ID_TYPE - * @{ - */ -#define IS_AUDIO_AEC_ID_TYPE(type) (((type) == AUDIO_AEC_0) || \ - ((type) == AUDIO_AEC_1)) - -/** @defgroup AUDIO_PDM_ID_TYPE - * @{ - */ -#define IS_AUDIO_PDM_ID_TYPE(type) (((type) == AUDIO_PDM_0) || \ - ((type) == AUDIO_PDM_1) || \ - ((type) == AUDIO_PDM_2)) - -/** @defgroup AUDIO_MUTE_TYPE - * @{ - */ -#define IS_AUDIO_MUTE_TYPE(type) (((type) == AUDIO_UNMUTE) || \ - ((type) == AUDIO_MUTE)) - -/** @defgroup AUDIO_ADC_CLOCK_TYPE - * @{ - */ -#define IS_AUDIO_ADC_CLOCK_TYPE(type) (((type) == AUDIO_ADC_8_KHZ) || \ - ((type) == AUDIO_ADC_16_KHZ) || \ - ((type) == AUDIO_ADC_24_KHZ) || \ - ((type) == AUDIO_ADC_32_KHZ) || \ - ((type) == AUDIO_ADC_48_KHZ) || \ - ((type) == AUDIO_ADC_96_KHZ)) - -/** @defgroup AUDIO_DAC_CLOCK_TYPE - * @{ - */ -#define IS_AUDIO_DAC_CLOCK_TYPE(type) (((type) == AUDIO_DAC_8_KHZ) || \ - ((type) == AUDIO_DAC_16_KHZ) || \ - ((type) == AUDIO_DAC_24_KHZ) || \ - ((type) == AUDIO_DAC_32_KHZ) || \ - ((type) == AUDIO_DAC_48_KHZ) || \ - ((type) == AUDIO_DAC_96_KHZ) || \ - ((type) == AUDIO_DAC_192_KHZ)) - -/** @defgroup AUDIO_ADC_SOURCE_TYPE - * @{ - */ -#define IS_AUDIO_ADC_SOURCE_TYPE(type) (((type) == AUDIO_ADC_ANALOG) || \ - ((type) == AUDIO_ADC_PDM)) - -/** @defgroup AUDIO_LFSR_TYPE - * @{ - */ -#define IS_AUDIO_LFSR_TYPE(type) (((type) == AUDIO_LFSR32) || \ - ((type) == AUDIO_LFSR24) || \ - ((type) == AUDIO_LFSR16) || \ - ((type) == AUDIO_LFSR12)) - -/** @defgroup AUDIO_MIXER_MODE - * @{ - */ -#define IS_AUDIO_MIXER_MODE(type) (((type) == AUDIO_SECOND_DEBUG_MODE) || \ - ((type) == AUDIO_SIDETONE_LOOPBACK)) - -/** @defgroup AUDIO_MIXER_VOLUME_TYPE - * @{ - */ -#define IS_AUDIO_MIXER_VOLUME_TYPE(type) (((type) == AUDIO_MIXER_VOLUME_0_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_6_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_12_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_18_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_36_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_54_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_72_DB) || \ - ((type) == AUDIO_MIXER_VOLUME_MUTE)) - -/** @defgroup AUDIO_MIXER_ID_TYPE - * @{ - */ -#define IS_AUDIO_MIXER_ID_TYPE(type) (((type) == AUDIO_MIXER_ID_0) || \ - ((type) == AUDIO_MIXER_ID_1)) - -/** @defgroup AUDIO_DAC_ORDER_TYPE - * @{ - */ -#define IS_AUDIO_DAC_ORDER_TYPE(type) (((type) == AUDIO_DAC_2_ORDER) || \ - ((type) == AUDIO_DAC_3_ORDER)) - -/** @defgroup AUDIO_AEC_ATTEN_MODE - * @{ - */ -#define IS_AUDIO_AEC_ATTEN_MODE(type) (((type) == AUDIO_AEC_NO_DROP) || \ - ((type) == AUDIO_AEC_DROP_1LSB) || \ - ((type) == AUDIO_AEC_DROP_2LSB) || \ - ((type) == AUDIO_AEC_DROP_3LSB) || \ - ((type) == AUDIO_AEC_DROP_6LSB) || \ - ((type) == AUDIO_AEC_DROP_9LSB) || \ - ((type) == AUDIO_AEC_DROP_12LSB)) - -/** @defgroup AUDIO_PDM_SOURCE_TYPE - * @{ - */ -#define IS_AUDIO_PDM_SOURCE_TYPE(type) (((type) == AUDIO_PDM_0_L) || \ - ((type) == AUDIO_PDM_0_R) || \ - ((type) == AUDIO_PDM_1_L) || \ - ((type) == AUDIO_PDM_1_R) || \ - ((type) == AUDIO_PDM_2_L) || \ - ((type) == AUDIO_PDM_2_R)) - -/** @defgroup AUDIO_RESOLUTION_TYPE - * @{ - */ -#define IS_AUDIO_RESOLUTION_TYPE(type) (((type) == AUDIO_RES_16_BITS) || \ - ((type) == AUDIO_RES_20_BITS)) - -/** @defgroup AUDIO_FIFO_AILGN_MODE - * @{ - */ -#define IS_AUDIO_FIFO_AILGN_MODE(type) (((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT31) || \ - ((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT23) || \ - ((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT19) || \ - ((type) == AUDIO_FIFO_AILGN_MSB_AT_BIT15)) - -/** @defgroup AUDIO_FIFO_DQR_THRESHOLD_MODE - * @{ - */ -#define IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(type) (((type) == AUDIO_DRQ_EQUEL_TO_IRQ) || \ - ((type) == AUDIO_DRQ_THR_AS_4_TX_8_RX) || \ - ((type) == AUDIO_DRQ_THR_AS_8_TX_16_RX) || \ - ((type) == AUDIO_DRQ_THR_AS_16_TX_32_RX)) - -/** @defgroup AUDIO_INT_TYPE - * @{ - */ -#define IS_AUDIO_INT_TYPE(type) (((type) == AUDIO_INT_RX_FIFO_THR) || \ - ((type) == AUDIO_INT_RX_FIFO_OVERRUN) || \ - ((type) == AUDIO_INT_RX_FIFO_UNDERRUN) || \ - ((type) == AUDIO_INT_TX_FIFO_THR) || \ - ((type) == AUDIO_INT_TX_FIFO_OVERRUN) || \ - ((type) == AUDIO_INT_TX_FIFO_UNDERRUN) || \ - ((type) == AUDIO_INT_ADC0_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_ADC1_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_ADC2_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_DAC0_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_DAC1_SET_VOLUME_DONE) || \ - ((type) == AUDIO_INT_VAD) || \ - ((type) == AUDIO_INT_NUM_ALL)) - -/** @defgroup AUDIO_PEQ_QTFM_TYPE - * @{ - */ -#define IS_AUDIO_PEQ_QTFM_TYPE(type) (((type) == AUDIO_PEQ_QFMT_20_17) || \ - ((type) == AUDIO_PEQ_QFMT_20_16)) - -/** @defgroup AUDIO_MUTE_MODE - * @{ - */ -#define IS_AUDIO_MUTE_MODE(type) (((type) == AUIDO_MUTE_DIRECTLY) || \ - ((type) == AUDIO_MUTE_WITH_RAMP_DOWN)) - -/** @defgroup AUDIO_RAMP_RATE_TYPE - * @{ - */ -#define IS_AUDIO_RAMP_RATE_TYPE(type) (((type) == AUIDO_RAMP_RATE_2_FS) || \ - ((type) == AUIDO_RAMP_RATE_4_FS) || \ - ((type) == AUIDO_RAMP_RATE_8_FS) || \ - ((type) == AUIDO_RAMP_RATE_16_FS) || \ - ((type) == AUIDO_RAMP_RATE_32_FS) || \ - ((type) == AUIDO_RAMP_RATE_64_FS) || \ - ((type) == AUIDO_RAMP_RATE_128_FS) || \ - ((type) == AUIDO_RAMP_RATE_256_FS) || \ - ((type) == AUIDO_RAMP_RATE_512_FS) || \ - ((type) == AUIDO_RAMP_RATE_1024_FS) || \ - ((type) == AUIDO_RAMP_RATE_2048_FS)) - -/** @defgroup AUDIO_ZERO_CROSS_RATE_TYPE - * @{ - */ -#define IS_AUDIO_ZERO_CROSS_RATE_TYPE(type) (((type) == AUIDO_ZERO_CROSS_RATE_2_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_4_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_8_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_16_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_32_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_64_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_128_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_256_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_512_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_1024_FS) || \ - ((type) == AUIDO_ZERO_CROSS_RATE_2048_FS)) - -/** @defgroup AUDIO_VOLUME_CTR_MODE - * @{ - */ -#define IS_AUDIO_VOLUME_CTR_MODE(type) (((type) == AUIDO_VOLUME_UPDATE_FORCE) || \ - ((type) == AUIDO_VOLUME_UPDATE_AT_ZERO_CROSSING) || \ - ((type) == AUIDO_VOLUME_UPDATE_AT_RAMP)) - -/** @defgroup AUDIO_AGC_DETECT_MODE - * @{ - */ -#define IS_AUDIO_AGC_DETECT_MODE(type) (((type) == AUIDO_AGC_DETECT_BY_PEAK) || \ - ((type) == AUIDO_AGC_DETECT_BY_AVERAGE)) - -/** @defgroup AUDIO_AGC_SRC_TYPE - * @{ - */ -#define IS_AUDIO_AGC_SRC_TYPE(type) (((type) == AUIDO_AGC_CH0_ABSOLUTE_VALUE) || \ - ((type) == AUIDO_AGC_CH1_ABSOLUTE_VALUE) || \ - ((type) == AUIDO_AGC_CH2_ABSOLUTE_VALUE) || \ - ((type) == AUIDO_AGC_MAXIMUM_VALUE_OF_CH012)) - -/** @defgroup AUIDO_DRC_DATA_TYPE - * @{ - */ -#define IS_AUIDO_DRC_DATA_TYPE(type) (((type) == AUIDO_DRC_DATA_SOURCE_CH0) || \ - ((type) == AUIDO_DRC_DATA_SOURCE_CH1) || \ - ((type) == AUIDO_DRC_DATA_SOURCE_AVERAGE_OF_CH0_CH1) || \ - ((type) == AUIDO_DRC_DATA_SOURCE_MAX_OF_CH0_CH1)) - -/** @defgroup AUIDO_VAD_SOURCE_TYPE - * @{ - */ -#define IS_AUIDO_VAD_SOURCE_TYPE(type) (((type) == AUIDO_VAD_DATA_SOURCE_ADC_CH0) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_ADC_CH1) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_ADC_CH2) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_AEC_CH0) || \ - ((type) == AUIDO_VAD_DATA_SOURCE_AEC_CH1) || \ - ((type) == AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH0_ADD_CH1) || \ - ((type) == AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH1_ADD_CH2) || \ - ((type) == AUDIO_VAD_DATA_SOURCE_AVERAGE_ADC_CH2_ADD_CH0)) - -/** @defgroup AUIDO_VAD_FRAMINGSHIFT_TYPE - * @{ - */ -#define IS_AUIDO_VAD_FRAMINGSHIFT_TYPE(type) (((type) == AUIDO_VAD_FRAMING_SHIFT_2P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_7P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_10_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_12P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_15_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_17P5_MS) || \ - ((type) == AUIDO_VAD_FRAMING_SHIFT_20_MS)) - -/** @defgroup AUIDO_VAD_FRAMINGTIME_TYPE - * @{ - */ -#define IS_AUIDO_VAD_FRAMINGTIME_TYPE(type) (((type) == AUIDO_VAD_FRAMING_TIME_2) || \ - ((type) == AUIDO_VAD_FRAMING_TIME_3) || \ - ((type) == AUIDO_VAD_FRAMING_TIME_4) || \ - ((type) == AUIDO_VAD_FRAMING_TIME_5)) - -/** @defgroup AUIDO_VAD_IRQ_SOURCE_TYPE - * @{ - */ -#define IS_AUIDO_VAD_IRQ_SOURCE_TYPE(type) (((type) == AUIDO_VAD_ORIGINAL_OUTPUT) || \ - ((type) == AUIDO_VAD_OUT0) || \ - ((type) == AUIDO_VAD_OUT1) || \ - ((type) == AUIDO_VAD_OUT2)) - -/** @defgroup AUIDO_VAD_NOISYBUFFERLEN_TYPE - * @{ - */ -#define IS_AUIDO_VAD_NOISYBUFFERLEN_TYPE(type) (((type) == AUIDO_VAD_NOISY_BUF_LEN_4) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_8) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_12) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_16) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_20) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_24) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_28) || \ - ((type) == AUIDO_VAD_NOISY_BUF_LEN_32)) - -/** @defgroup AUIDO_VAD_NOISYBUFFERMONITOR_TYPE - * @{ - */ -#define IS_AUIDO_VAD_NOISYBUFFERMONITOR_TYPE(type) (((type) == AUIDO_VAD_NOISY_MONITOR_1_S) || \ - ((type) == AUIDO_VAD_NOISY_MONITOR_2_S) || \ - ((type) == AUIDO_VAD_NOISY_MONITOR_4_S) || \ - ((type) == AUIDO_VAD_NOISY_MONITOR_8_S)) - -/*@} end of group AUDIO_Public_Constants */ - -/** @defgroup AUDIO_Public_Macros - * @{ - */ -#define AUDIO_PRIVATE_BIT_POS(n) (0x01 << n) -#define ADC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(0) -#define ADC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(1) -#define ADC3_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(2) -#define AEC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(3) -#define AEC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(4) -#define DAC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(0) -#define DAC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(1) - -/*@} end of group AUDIO_Public_Macros */ - -/** @defgroup AUDIO_Public_Functions - * @{ - */ -void Audio_Clock_Init(Audio_Clock_CFG_Type *cfg); -//debug api -void Debug0_Write(uint32_t wCmd); -uint32_t Debug1_Read(void); -void Debug2_Write(uint32_t wCmd); -void Debug3_Write(uint32_t wCmd); -// -BL_Err_Type Audio_Tx_Source_DAC_Sel(uint8_t tx_channel, Audio_DAC_ID_Type dac_id); -BL_Err_Type Audio_Rx_Source_ADC_Sel(uint8_t rx_channel, Audio_ADC_ID_Type adc_id); -BL_Err_Type Audio_Rx_Source_AEC_Sel(uint8_t rx_channel, Audio_AEC_ID_Type aec_id); -// -void Audio_Set_ADC_Source(Audio_ADC_ID_Type id, Audio_ADC_Source_Type adc_source); -// -void Audio_AEC_Enable(Audio_AEC_ID_Type id); -void Audio_AEC_Disable(Audio_AEC_ID_Type id); -void Audio_ADC_Enable(Audio_ADC_ID_Type id); -void Audio_ADC_Disable(Audio_ADC_ID_Type id); -void Audio_DAC_Enable(Audio_DAC_ID_Type id); -void Audio_DAC_Disable(Audio_DAC_ID_Type id); -//performance -void Audio_Set_HPF_Parameter(Audio_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, - uint8_t k2_enable, uint8_t k2); -//0x08 -void Audio_Set_ADC_LFSR(Audio_LFSR_Type lfsrType); -BL_Sts_Type Audio_Get_ADC_LFSR(void); -void Audio_Set_ADC_Scaling_Value(Audio_ADC_ID_Type id, uint8_t scalingVal); -void Audio_Set_Fir_Mode(Audio_ADC_ID_Type id, uint8_t enable); -//0x10 -void Audio_ADC_Mash_Bit_Swap(Audio_ADC_ID_Type id, uint8_t swap); -void Audio_ADC_PDM_Inv_Swap(Audio_ADC_ID_Type id, uint8_t swap); -void Audio_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h); -//0x14 -void Audio_Set_DAC_LFSR(Audio_LFSR_Type lfsrType); -void Audio_Set_DAC_Dither(uint8_t enable, uint8_t amp); -void Audio_Set_DAC_Scaling(uint8_t enable, uint8_t scaling); -void Audio_Set_DAC_Order(Audio_DAC_Order_Type order); -void Audio_Set_DAC_Dwa_Swap(uint8_t swap); -void Audio_Set_DAC_Dwa_Bypass(uint8_t bypass); -//0x18 -void Audio_Set_AEC_Record_Vid(uint8_t enable, uint8_t div); -void Audio_Set_AEC_Atten_mode(Audio_AEC_ID_Type aec_id, Audio_AEC_Atten_Mode mode); -//0x1c PDM Source sel -void Audio_ADC_PDM_Channel_Sel(Audio_PDM_ID_Type id, - Audio_PDM_Source_Type pdmSel); -void Audio_ADC_PDM_Enable(Audio_PDM_ID_Type id); -void Audio_ADC_PDM_Disable(Audio_PDM_ID_Type id); -//mix about -void Audio_Set_Mixer_Mode(uint8_t enable, Audio_Mixer_ID_Type mixerId, Audio_Mixer_Mode mode, - Audio_ADC_ID_Type sidetoneChannel, Audio_Mixer_Volume_Type Volume); -//int about -void Auido_IntMask(Audio_INT_Type intType, BL_Mask_Type intMask); -void Auido_IntClear(Audio_INT_Type intType); -BL_Err_Type Audio_Int_Callback_Install(Audio_INT_Type intType, intCallback_Type *cbFun); -BL_Sts_Type Audio_GetIntStatus(Audio_INT_Type intType); -void Audio_RxFifoClear(void); -uint32_t Audio_GetRxFifoCount(void); -uint32_t Audio_ReadRxFifo(void); -void Audio_TxFifoClear(void); -uint32_t Audio_GetTxFifoCount(void); -void Audio_WriteTxFifo(uint32_t da); -//fifo about -void Audio_RxFifoConfig(Audio_FifoCfg_Type *cfg); -void Audio_TxFifoConfig(Audio_FifoCfg_Type *Cfg); -void Audio_RxFifoEnable(uint8_t ch); -void Audio_RxFifoDisable(uint8_t ch); -void Audio_TxFifoEnable(uint8_t ch); -void Audio_TxFifoDisable(uint8_t ch); -//PEQ about -BL_Err_Type Audio_PEQ_Config(uint8_t peq_index, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, - uint32_t *b_pra, uint32_t *a_pra); -//volume control -BL_Err_Type Audio_DAC_Set_Mute(BL_Fun_Type muteSyncAllDac, Audio_DAC_ID_Type dac_id, - Audio_Mute_Type mute); -BL_Err_Type Audio_ADC_Set_Mute(BL_Fun_Type muteSyncAllAdc, Audio_ADC_ID_Type adc_id, Audio_Mute_Type mute); -BL_Err_Type Audio_ADC_Software_Volume_Config(Audio_ADC_ID_Type adc_id, Audio_Volume_Cfg_Type *cfg); -BL_Err_Type Audio_DAC_Software_Volume_Config(Audio_DAC_ID_Type dac_id, Audio_Volume_Cfg_Type *cfg); -BL_Err_Type Audio_ADC_Set_Volume(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume); -BL_Err_Type Audio_DAC_Set_Volume(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume); -BL_Err_Type Audio_ADC_Set_Volume_Block(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume, - uint32_t blockTimeout); -BL_Err_Type Audio_DAC_Set_Volume_Block(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume, - uint32_t blockTimeout); -BL_Err_Type Audio_ADC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume); -BL_Err_Type Audio_DAC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume); -void Audio_ADC_Reset_Volume_Update(Audio_ADC_ID_Type adc_id); -void Audio_ADC_Reset_Volume_Update(Audio_ADC_ID_Type dac_id); -void Audio_Reset_Volume_All_Update(uint8_t isAdcOrDac); -BL_Err_Type Audio_ADC_Hardware_Volume_Config(Audio_Volume_Cfg_Type *cfg); -uint16_t Audio_ADC_Get_Hardware_Volume(void); -uint16_t Audio_ADC_Get_Volume(Audio_ADC_ID_Type adc_id); -uint16_t Audio_DAC_Get_Volume(Audio_DAC_ID_Type dac_id); -BL_Sts_Type Audio_IS_ADC_Mute_Done(Audio_ADC_ID_Type adc_id); -BL_Sts_Type Audio_IS_ADC_Volume_Set_Busy(Audio_ADC_ID_Type adc_id); -BL_Sts_Type Audio_IS_DAC_Mute_Set_Done(Audio_DAC_ID_Type dac_id); -BL_Sts_Type Audio_IS_DAC_Volume_Set_Busy(Audio_DAC_ID_Type dac_id); -//agc about -void Audio_AGC_Init(uint8_t enable, Audio_AGC_Config_Type *cfg); -//drc about -void Audio_DRC_Init(uint8_t enable, Audio_DRC_Config_Type *cfg); -//vad about -void Audio_VAD_Init(Audio_VAD_Cfg_Type *cfg); -void Audio_VAD_Enable(void); -void Audio_VAD_Disable(void); -uint32_t Audio_VAD_Get_EK(void); -void Audio_DAC_Reset_Volume_Update(Audio_DAC_ID_Type dac_id); - -/*power */ -void Audio_Poweron(void); - -/*analog gain */ -void Audio_SetADCAnalogGain(Audio_ADC_ID_Type adc, uint8_t analogGain); -void Audio_SetDACAnalogGain(Audio_DAC_ID_Type dac, uint8_t analogGain); - -void AUDIO_IRQHandler(void); - -/*@} end of group AUDIO_Public_Functions */ - -/*@} end of group AUDIO */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_AUDIO_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aupdm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aupdm.h deleted file mode 100644 index 3387cb9dfa..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aupdm.h +++ /dev/null @@ -1,267 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_audiopdm.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_AUDIOPDM_H__ -#define __BL808_AUDIOPDM_H__ - -#include "pdm_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIOPDM - * @{ - */ - -/** @defgroup AUDIOPDM_Public_Types - * @{ - */ - -/** - * @brief Aupdm ADC ID - */ -typedef enum { - AUPDM_ADC_0, /*!< Aupdm ADC 0 */ - AUPDM_ADC_1, /*!< Aupdm ADC 1 */ - AUPDM_ADC_2, /*!< Aupdm ADC 2 */ -} Aupdm_ADC_ID_Type; - -/** - * @brief Aupdm PDM ADC Clock - */ -typedef enum { - AUPDM_PDM_ADC_8_KHZ, /*!< Aupdm PDM ADC Clock set as 8KHZ */ - AUPDM_PDM_ADC_16_KHZ, /*!< Aupdm PDM ADC Clock set as 16KHZ */ - AUPDM_PDM_ADC_24_KHZ, /*!< Aupdm PDM ADC Clock set as 24KHZ */ - AUPDM_PDM_ADC_32_KHZ, /*!< Aupdm PDM ADC Clock set as 32KHZ */ - AUPDM_PDM_ADC_48_KHZ, /*!< Aupdm PDM ADC Clock set as 48KHZ */ - AUPDM_PDM_ADC_96_KHZ, /*!< Aupdm PDM ADC Clock set as 96KHZ */ -} Aupdm_ADC_Clock_Type; - -/** - * @brief Aupdm PDM ID - */ -typedef enum { - AUPDM_PDM_0, /*!< select PDM Channel 0 */ - AUPDM_PDM_1, /*!< select PDM Channel 1 */ - AUPDM_PDM_2, /*!< select PDM Channel 2 */ -} Aupdm_PDM_ID_Type; - -/** - * @brief Aupdm PDM Source Select - */ -typedef enum { - AUPDM_PDM_0_L, /*!< select PDM0 Left Channel */ - AUPDM_PDM_0_R, /*!< select PDM0 Right Channel */ - AUPDM_PDM_1_L, /*!< select PDM1 Left Channel */ - AUPDM_PDM_1_R, /*!< select PDM1 Right Channel */ - AUPDM_PDM_2_L, /*!< select PDM2 Left Channel */ - AUPDM_PDM_2_R, /*!< select PDM2 Right Channel */ -} Aupdm_PDM_Source_Type; - -/** - * @brief Aupdm Resolution - */ -typedef enum { - AUPDM_RES_16_BITS, /*!< select ADC Resolution as 16 bit */ - AUPDM_RES_20_BITS, /*!< select ADC Resolution as 20 bit */ -} Aupdm_Resolution_Type; - -/** - * @brief Aupdm Resolution - */ -typedef enum { - AUPDM_FIFO_AILGN_MSB_AT_BIT31, /*!< Mode 0: Valid data's MSB is at [31] of FIFO register */ - AUPDM_FIFO_AILGN_MSB_AT_BIT23, /*!< Mode 1: Valid data's MSB is at [23] of FIFO register */ - AUPDM_FIFO_AILGN_MSB_AT_BIT19, /*!< Mode 2: Valid data's MSB is at [19] of FIFO register */ - AUPDM_FIFO_AILGN_MSB_AT_BIT15, /*!< Mode 3: Valid data's MSB is at [15] of FIFO register */ -} Aupdm_FIFO_Ailgn_Mode; - -/** - * @brief Aupdm Resolution - */ -typedef enum { - AUPDM_DRQ_EQUEL_TO_IRQ, /*!< DMA request threhold is equeal to Interrupt threhold */ - AUPDM_DRQ_THR_AS_4_TX_8_RX, /*!< DMA request threhold is 4 when config TX FIFO DRQ , 8 when config RX FIFO */ - AUPDM_DRQ_THR_AS_8_TX_16_RX, /*!< DMA request threhold is 8 when config TX FIFO DRQ , 16 when config RX FIFO */ - AUPDM_DRQ_THR_AS_16_TX_32_RX, /*!< DMA request threhold is 16 when config TX FIFO DRQ , 32 when config RX FIFO */ -} Aupdm_FIFO_DQR_Threshold_Mode; - -/** - * @brief Aupdm initerrupt type - */ -typedef enum { - AUPDM_INT_RX_FIFO_THR, /*!< Aupdm RX FIFO counter upper than threhold interrupt */ - AUPDM_INT_RX_FIFO_OVERRUN, /*!< Aupdm RX FIFO overrun */ - AUPDM_INT_RX_FIFO_UNDERRUN, /*!< Aupdm RX FIFO underrun */ - AUPDM_INT_NUM_ALL, /*!< Aupdm int all */ -} Aupdm_INT_Type; - -/** - * @brief Aupdm PDM Clock Configuration - */ -typedef struct { - Aupdm_ADC_Clock_Type adc_clock; /*!< ADC Rate Configuration */ - BL_Fun_Type pdm_clk_inv; /*!< enable or not pdm clock inv */ - BL_Fun_Type adc_clk_inv; /*!< enable or not adc clock inv */ -} Aupdm_Clock_CFG_Type; - -/** - * @brief Aupdm FIFO Configuration - */ -typedef struct { - Aupdm_Resolution_Type resolution; /*!< Receiving Aupdm Sample Resolution */ - Aupdm_FIFO_Ailgn_Mode ailgnMode; /*!< FIFO alignMode */ - uint8_t FifoIntThreshold; /*!< FIFO IRQ Threshold */ - Aupdm_FIFO_DQR_Threshold_Mode dmaThresholdMode; /*!< FIFO DRQ Threshold mode */ - BL_Fun_Type dmaEn; /*!< enable DMA FIFO interface */ -} Aupdm_FifoCfg_Type; - -/*@} end of group AUDIOPDM_Public_Types */ - -/** @defgroup AUDIOPDM_Public_Constants - * @{ - */ - -/** @defgroup AUPDM_ADC_ID_TYPE - * @{ - */ -#define IS_AUPDM_ADC_ID_TYPE(type) (((type) == AUPDM_ADC_0) || \ - ((type) == AUPDM_ADC_1) || \ - ((type) == AUPDM_ADC_2)) - -/** @defgroup AUPDM_ADC_CLOCK_TYPE - * @{ - */ -#define IS_AUPDM_ADC_CLOCK_TYPE(type) (((type) == AUPDM_PDM_ADC_8_KHZ) || \ - ((type) == AUPDM_PDM_ADC_16_KHZ) || \ - ((type) == AUPDM_PDM_ADC_24_KHZ) || \ - ((type) == AUPDM_PDM_ADC_32_KHZ) || \ - ((type) == AUPDM_PDM_ADC_48_KHZ) || \ - ((type) == AUPDM_PDM_ADC_96_KHZ)) - -/** @defgroup AUPDM_PDM_ID_TYPE - * @{ - */ -#define IS_AUPDM_PDM_ID_TYPE(type) (((type) == AUPDM_PDM_0) || \ - ((type) == AUPDM_PDM_1) || \ - ((type) == AUPDM_PDM_2)) - -/** @defgroup AUPDM_PDM_SOURCE_TYPE - * @{ - */ -#define IS_AUPDM_PDM_SOURCE_TYPE(type) (((type) == AUPDM_PDM_0_L) || \ - ((type) == AUPDM_PDM_0_R) || \ - ((type) == AUPDM_PDM_1_L) || \ - ((type) == AUPDM_PDM_1_R) || \ - ((type) == AUPDM_PDM_2_L) || \ - ((type) == AUPDM_PDM_2_R)) - -/** @defgroup AUPDM_RESOLUTION_TYPE - * @{ - */ -#define IS_AUPDM_RESOLUTION_TYPE(type) (((type) == AUDIO_RES_16_BITS) || \ - ((type) == AUDIO_RES_20_BITS)) - -/** @defgroup AUPDM_FIFO_AILGN_MODE - * @{ - */ -#define IS_AUPDM_FIFO_AILGN_MODE(type) (((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT31) || \ - ((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT23) || \ - ((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT19) || \ - ((type) == AUPDM_FIFO_AILGN_MSB_AT_BIT15)) - -/** @defgroup AUPDM_FIFO_DQR_THRESHOLD_MODE - * @{ - */ -#define IS_AUPDM_FIFO_DQR_THRESHOLD_MODE(type) (((type) == AUPDM_DRQ_EQUEL_TO_IRQ) || \ - ((type) == AUPDM_DRQ_THR_AS_4_TX_8_RX) || \ - ((type) == AUPDM_DRQ_THR_AS_8_TX_16_RX) || \ - ((type) == AUPDM_DRQ_THR_AS_16_TX_32_RX)) - -/** @defgroup AUPDM_INT_TYPE - * @{ - */ -#define IS_AUPDM_INT_TYPE(type) (((type) == AUPDM_INT_RX_FIFO_THR) || \ - ((type) == AUPDM_INT_RX_FIFO_OVERRUN) || \ - ((type) == AUPDM_INT_RX_FIFO_UNDERRUN) || \ - ((type) == AUPDM_INT_NUM_ALL)) - -/*@} end of group AUDIOPDM_Public_Constants */ - -/** @defgroup AUDIOPDM_Public_Macros - * @{ - */ -#define AUDIO_PRIVATE_BIT_POS(n) (0x01 << n) -#define ADC1_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(0) -#define ADC2_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(1) -#define ADC3_DATA_CHANNEL_FIFO_EN AUDIO_PRIVATE_BIT_POS(2) - -/*@} end of group AUDIOPDM_Public_Macros */ - -/** @defgroup AUDIOPDM_Public_Functions - * @{ - */ -void Aupdm_IntMask(Aupdm_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type Aupdm_GetIntStatus(Aupdm_INT_Type intType); -void Aupdm_IntClear(Aupdm_INT_Type intType); -void Aupdm_Clock_Init(Aupdm_Clock_CFG_Type *cfg); -void Aupdm_PDM_Channel_Sel(Aupdm_PDM_ID_Type id, Aupdm_PDM_Source_Type pdmSel); -void Aupdm_PDM_Enable(Aupdm_PDM_ID_Type id); -BL_Err_Type Aupdm_Int_Callback_Install(Aupdm_INT_Type intType, intCallback_Type *cbFun); -void Aupdm_RxFifoClear(void); -uint32_t Aupdm_GetRxFifoCount(void); -uint32_t Aupdm_ReadRxFifo(void); -void Aupdm_RxFifoConfig(Aupdm_FifoCfg_Type *cfg); -void Aupdm_RxFifoEnable(uint8_t ch); -void Aupdm_RxFifoDisable(uint8_t ch); -BL_Err_Type Aupdm_Rx_Source_ADC_Sel(uint8_t rx_channel, Aupdm_ADC_ID_Type adc_id); -void Aupdm_ADC_Enable(Aupdm_ADC_ID_Type id); -void Aupdm_ADC_Disable(Aupdm_ADC_ID_Type id); -void Aupdm_Set_ADC_Scaling_Value(Aupdm_ADC_ID_Type id, uint8_t scalingVal); -void Aupdm_Set_Fir_Mode(Aupdm_ADC_ID_Type id, uint8_t enable); -void Aupdm_Set_HPF_Parameter(Aupdm_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2); -void Aupdm_ADC_PDM_Inv_Swap(Aupdm_ADC_ID_Type id, uint8_t swap); -void Audio_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h); -BL_Err_Type Aupdm_ADC_Volume_Config(Aupdm_ADC_ID_Type adc_id, uint8_t volume); -/*@} end of group AUDIOPDM_Public_Functions */ - -/*@} end of group AUDIOPDM */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_AUDIOPDM_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_cam.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_cam.h deleted file mode 100644 index 211c393750..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_cam.h +++ /dev/null @@ -1,349 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_cam.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_CAM_H__ -#define __BL808_CAM_H__ - -#include "cam_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup CAM - * @{ - */ - -/** @defgroup CAM_Public_Types - * @{ - */ - -/** - * @brief CAM port type definition - */ -typedef enum { - CAM0_ID, /*!< Camera0 port define */ - CAM1_ID, /*!< Camera1 port define */ - CAM2_ID, /*!< Camera2 port define */ - CAM3_ID, /*!< Camera3 port define */ - CAM4_ID, /*!< Camera4 port define */ - CAM5_ID, /*!< Camera5 port define */ - CAM6_ID, /*!< Camera6 port define */ - CAM7_ID, /*!< Camera7 port define */ - CAM_ID_MAX, /*!< Camera max ID define */ -} CAM_ID_Type; - -/** - * @brief CAM AHB burst type definition - */ -typedef enum { - CAM_BURST_TYPE_SINGLE, /*!< Camera AHB burst type:single */ - CAM_BURST_TYPE_INCR4, /*!< Camera AHB burst type:incrementing 4 */ - CAM_BURST_TYPE_INCR8, /*!< Camera AHB burst type:incrementing 8 */ - CAM_BURST_TYPE_INCR16, /*!< Camera AHB burst type:incrementing 16 */ - CAM_BURST_TYPE_INCR32 = 5, /*!< Camera AHB burst type:incrementing 32 */ - CAM_BURST_TYPE_INCR64, /*!< Camera AHB burst type:incrementing 64 */ -} CAM_Burst_Type; - -/** - * @brief CAM software mode type definition - */ -typedef enum { - CAM_SW_MODE_AUTO, /*!< CAM auto mode with mjpeg */ - CAM_SW_MODE_MANUAL, /*!< CAM manual mode(software mode) */ -} CAM_SW_Mode_Type; - -/** - * @brief CAM output drop mode type definition - */ -typedef enum { - CAM_DROP_NONE, /*!< Not drop */ - CAM_DROP_ODD_ROW_ODD_PIXEL, /*!< Dropp odd pix data in odd rows, for example:(raw data:YUYV YUYV..., processed data:YUYV YY...) */ - CAM_DROP_ODD_ROW_EVEN_PIXEL, /*!< Dropp even pix data in odd rows, for example:(raw data:UYVY UYVY..., processed data:UYVY YY...) */ - CAM_DROP_ALL_ODD_PIXEL, /*!< Dropp odd pix data, for example:(raw data:YUYV YUYV..., processed data:YY YY...) */ - CAM_DROP_ALL_EVEN_PIXEL, /*!< Dropp even pix data, for example:(raw data:UYVY UYVY..., processed data:YY YY...) */ -} CAM_Output_Drop_Mode_Type; - -/** - * @brief CAM input pix data width type definition - */ -typedef enum { - CAM_PIX_DATA_BIT_16, /*!< CAM pix data is 16-bit */ - CAM_PIX_DATA_BIT_24, /*!< CAM pix data is 24-bit */ - CAM_PIX_DATA_BIT_24TO16, /*!< CAM pix data is 24-comp-16-bit */ - CAM_PIX_DATA_BIT_24TO32, /*!< CAM pix data is 24-exp-32-bit */ - CAM_PIX_DATA_BIT_8, /*!< CAM pix data is 8-bit */ -} CAM_Input_Pix_Width_Type; - -/** - * @brief CAM 8-bit mode byte select type definition - */ -typedef enum { - CAM_8_BIT_SELECT_LOWER, /*!< CAM select the lower byte of pix data */ - CAM_8_BIT_SELECT_UPPER, /*!< CAM select the upper byte of pix data */ -} CAM_8_Bit_Byte_Type; - -/** - * @brief CAM pix data 24-comp-16-bit mode RGB order type definition - */ -typedef enum { - CAM_16_BIT_RGB, /*!< CAM 16-bit pix data is RGB */ - CAM_16_BIT_GRB, /*!< CAM 16-bit pix data is GRB */ - CAM_16_BIT_RBG, /*!< CAM 16-bit pix data is RBG */ - CAM_16_BIT_GBR, /*!< CAM 16-bit pix data is GBR */ - CAM_16_BIT_BRG, /*!< CAM 16-bit pix data is BRG */ - CAM_16_BIT_BGR, /*!< CAM 16-bit pix data is BGR */ -} CAM_16_Bit_RGB_Type; - -/** - * @brief CAM line active polarity type definition - */ -typedef enum { - CAM_LINE_ACTIVE_POLARITY_LOW, /*!< CAM line active polarity low */ - CAM_LINE_ACTIVE_POLARITY_HIGH, /*!< CAM line active polarity high */ -} CAM_Line_Active_Pol; - -/** - * @brief CAM frame active polarity type definition - */ -typedef enum { - CAM_FRAME_ACTIVE_POLARITY_LOW, /*!< CAM frame active polarity low */ - CAM_FRAME_ACTIVE_POLARITY_HIGH, /*!< CAM frame active polarity high */ -} CAM_Frame_Active_Pol; - -/** - * @brief CAM sensor mode type definition - */ -typedef enum { - CAM_SENSOR_MODE_V_AND_H, /*!< CAM sensor type v and h */ - CAM_SENSOR_MODE_V_OR_H, /*!< CAM sensor type v or h */ - CAM_SENSOR_MODE_V, /*!< CAM sensor type v */ - CAM_SENSOR_MODE_H, /*!< CAM sensor type h */ -} CAM_Sensor_Mode_Type; - -/** - * @brief CAM interrupt type definition - */ -typedef enum { - CAM_INT_NORMAL, /*!< Normal write interrupt */ - CAM_INT_MEMORY_OVERWRITE, /*!< Memory overwrite interrupt */ - CAM_INT_FRAME_OVERWRITE, /*!< Frame overwrite interrupt */ - CAM_INT_FIFO_OVERWRITE, /*!< Fifo overwrite interrupt */ - CAM_INT_VSYNC_CNT_ERROR, /*!< Vsync valid line count non-match interrupt */ - CAM_INT_HSYNC_CNT_ERROR, /*!< Hsync valid pixel count non-match interrupt */ - CAM_INT_ALL, /*!< All of interrupt */ -} CAM_INT_Type; - -/** - * @brief CAM configuration strcut definition - */ -typedef struct -{ - CAM_SW_Mode_Type swMode; /*!< Software mode */ - uint8_t swIntCnt; /*!< Set frame count to issue interrupt at software mode */ - CAM_Input_Pix_Width_Type pixWidth; /*!< Input pix data width */ - CAM_Output_Drop_Mode_Type dropMode; /*!< Drop mode */ - CAM_Frame_Active_Pol framePol; /*!< Frame polarity */ - CAM_Line_Active_Pol linePol; /*!< Line polarity */ - CAM_Burst_Type burstType; /*!< AHB burst type */ - CAM_Sensor_Mode_Type camSensorMode; /*!< CAM sensor mode */ - uint8_t waitCount; /*!< Cycles in FSM wait mode, default value:0x40 */ - uint32_t memStart; /*!< Data start address */ - uint32_t memSize; /*!< Memory size in burst */ - uint32_t frameSize; /*!< Frame byte size */ -} CAM_CFG_Type; - -/** - * @brief CAM frame information strcut definition - */ -typedef struct -{ - uint8_t validFrames; /*!< Valid frames */ - uint16_t curFrameId; /*!< Current frame id */ - uint32_t curFrameAddr; /*!< Current frame address */ - uint32_t curFrameBytes; /*!< Current frame bytes */ - uint32_t status; /*!< CAM module status */ -} CAM_Frame_Info; - -/*@} end of group CAM_Public_Types */ - -/** @defgroup CAM_Public_Constants - * @{ - */ - -/** @defgroup CAM_ID_TYPE - * @{ - */ -#define IS_CAM_ID_TYPE(type) (((type) == CAM0_ID) || \ - ((type) == CAM1_ID) || \ - ((type) == CAM2_ID) || \ - ((type) == CAM3_ID) || \ - ((type) == CAM4_ID) || \ - ((type) == CAM5_ID) || \ - ((type) == CAM6_ID) || \ - ((type) == CAM7_ID) || \ - ((type) == CAM_ID_MAX)) - -/** @defgroup CAM_BURST_TYPE - * @{ - */ -#define IS_CAM_BURST_TYPE(type) (((type) == CAM_BURST_TYPE_SINGLE) || \ - ((type) == CAM_BURST_TYPE_INCR4) || \ - ((type) == CAM_BURST_TYPE_INCR8) || \ - ((type) == CAM_BURST_TYPE_INCR16) || \ - ((type) == CAM_BURST_TYPE_INCR32) || \ - ((type) == CAM_BURST_TYPE_INCR64)) - -/** @defgroup CAM_SW_MODE_TYPE - * @{ - */ -#define IS_CAM_SW_MODE_TYPE(type) (((type) == CAM_SW_MODE_AUTO) || \ - ((type) == CAM_SW_MODE_MANUAL)) - -/** @defgroup CAM_OUTPUT_DROP_MODE_TYPE - * @{ - */ -#define IS_CAM_OUTPUT_DROP_MODE_TYPE(type) (((type) == CAM_DROP_NONE) || \ - ((type) == CAM_DROP_ODD_ROW_ODD_PIXEL) || \ - ((type) == CAM_DROP_ODD_ROW_EVEN_PIXEL) || \ - ((type) == CAM_DROP_ALL_ODD_PIXEL) || \ - ((type) == CAM_DROP_ALL_EVEN_PIXEL)) - -/** @defgroup CAM_INPUT_PIX_WIDTH_TYPE - * @{ - */ -#define IS_CAM_INPUT_PIX_WIDTH_TYPE(type) (((type) == CAM_PIX_DATA_BIT_16) || \ - ((type) == CAM_PIX_DATA_BIT_24) || \ - ((type) == CAM_PIX_DATA_BIT_24TO16) || \ - ((type) == CAM_PIX_DATA_BIT_24TO32) || \ - ((type) == CAM_PIX_DATA_BIT_8)) - -/** @defgroup CAM_8_BIT_BYTE_TYPE - * @{ - */ -#define IS_CAM_8_BIT_BYTE_TYPE(type) (((type) == CAM_8_BIT_SELECT_LOWER) || \ - ((type) == CAM_8_BIT_SELECT_UPPER)) - -/** @defgroup CAM_16_BIT_RGB_TYPE - * @{ - */ -#define IS_CAM_16_BIT_RGB_TYPE(type) (((type) == CAM_16_BIT_RGB) || \ - ((type) == CAM_16_BIT_GRB) || \ - ((type) == CAM_16_BIT_RBG) || \ - ((type) == CAM_16_BIT_GBR) || \ - ((type) == CAM_16_BIT_BRG) || \ - ((type) == CAM_16_BIT_BGR)) - -/** @defgroup CAM_LINE_ACTIVE_POL - * @{ - */ -#define IS_CAM_LINE_ACTIVE_POL(type) (((type) == CAM_LINE_ACTIVE_POLARITY_LOW) || \ - ((type) == CAM_LINE_ACTIVE_POLARITY_HIGH)) - -/** @defgroup CAM_FRAME_ACTIVE_POL - * @{ - */ -#define IS_CAM_FRAME_ACTIVE_POL(type) (((type) == CAM_FRAME_ACTIVE_POLARITY_LOW) || \ - ((type) == CAM_FRAME_ACTIVE_POLARITY_HIGH)) - -/** @defgroup CAM_SENSOR_MODE_TYPE - * @{ - */ -#define IS_CAM_SENSOR_MODE_TYPE(type) (((type) == CAM_SENSOR_MODE_V_AND_H) || \ - ((type) == CAM_SENSOR_MODE_V_OR_H) || \ - ((type) == CAM_SENSOR_MODE_V) || \ - ((type) == CAM_SENSOR_MODE_H)) - -/** @defgroup CAM_INT_TYPE - * @{ - */ -#define IS_CAM_INT_TYPE(type) (((type) == CAM_INT_NORMAL) || \ - ((type) == CAM_INT_MEMORY_OVERWRITE) || \ - ((type) == CAM_INT_FRAME_OVERWRITE) || \ - ((type) == CAM_INT_FIFO_OVERWRITE) || \ - ((type) == CAM_INT_VSYNC_CNT_ERROR) || \ - ((type) == CAM_INT_HSYNC_CNT_ERROR) || \ - ((type) == CAM_INT_ALL)) - -/*@} end of group CAM_Public_Constants */ - -/** @defgroup CAM_Public_Macros - * @{ - */ - -/*@} end of group CAM_Public_Macros */ - -/** @defgroup CAM_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void CAM0_IRQHandler(void); -void CAM1_IRQHandler(void); -void CAM2_IRQHandler(void); -void CAM3_IRQHandler(void); -void CAM4_IRQHandler(void); -void CAM5_IRQHandler(void); -void CAM6_IRQHandler(void); -void CAM7_IRQHandler(void); -#endif -void CAM_Init(CAM_ID_Type camId, CAM_CFG_Type *cfg); -void CAM_Deinit(CAM_ID_Type camId); -void CAM_Enable(CAM_ID_Type camId); -void CAM_Disable(CAM_ID_Type camId); -void CAM_Clock_Gate(CAM_ID_Type camId, BL_Fun_Type enable); -void CAM_Hsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end); -void CAM_Vsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end); -void CAM_Set_Hsync_Total_Count(CAM_ID_Type camId, uint16_t count); -void CAM_Set_Vsync_Total_Count(CAM_ID_Type camId, uint16_t count); -void CAM_Get_Frame_Info(CAM_ID_Type camId, CAM_Frame_Info *info); -uint8_t CAM_Get_Frame_Count(CAM_ID_Type camId); -void CAM_Pop_Frame(CAM_ID_Type camId); -void CAM_IntMask(CAM_ID_Type camId, CAM_INT_Type intType, BL_Mask_Type intMask); -void CAM_IntClr(CAM_ID_Type camId, CAM_INT_Type intType); -void CAM_Int_Callback_Install(CAM_ID_Type camId, CAM_INT_Type intType, intCallback_Type *cbFun); -void CAM_8_Bit_Byte_Select(CAM_ID_Type camId, CAM_8_Bit_Byte_Type byteType); -void CAM_16_Bit_RGB_order(CAM_ID_Type camId, CAM_16_Bit_RGB_Type rgbType); -void CAM_32_Bit_Alpha_Set(CAM_ID_Type camId, uint8_t alpha); -void CAM_Set_Frame_Valid_Period(CAM_ID_Type camId, uint8_t period, uint32_t validBit); -void CAM_HW_Cover_First_Frame_Everytime(CAM_ID_Type camId, BL_Fun_Type enable); - -/*@} end of group CAM_Public_Functions */ - -/*@} end of group CAM */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_CAM_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_can.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_can.h deleted file mode 100644 index 4a5bf5b3f0..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_can.h +++ /dev/null @@ -1,244 +0,0 @@ -#ifndef __BL808_CAN_H__ -#define __BL808_CAN_H__ - -#include "can_reg.h" -#include "bl808_common.h" - -#define CAN_BASE CAN_FD_BASE -#define CAN_TIMEOUT_MAX (32 * 1000) - -typedef enum { - CAN_FRAME_FORMAT_STANDARD = 0, - CAN_FRAME_FORMAT_EXTENDED, -}CAN_FRAME_FORMAT_Type; - -typedef enum { - CAN_FRAME_TYPE_DATA = 0, - CAN_FRAME_TYPE_REMOTE, -}CAN_FRAME_Type; - -typedef enum { - CAN_MODE_TYPE_RESET = 0, - CAN_MODE_TYPE_LISTEN_ONLY, - CAN_MODE_TYPE_SELF_TSET, - CAN_MODE_TYPE_ACCEPTANCE_FILTER, -}CAN_MODE_Type; - -typedef enum -{ - CAN_MODE_VALUE_NORMAL = 0, - CAN_MODE_VALUE_RESET = 1, - CAN_MODE_VALUE_LISTEN_ONLY = 1, - CAN_MODE_VALUE_SELF_TSET = 1, - CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL = 0, - CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE = 1, -} CAN_MODE_VALUE_Type; - -typedef enum { - CAN_INT_RECEIVE = 0, - CAN_INT_TRANSMIT, - CAN_INT_ERROR_WARNING, - CAN_INT_OVERRUN, - CAN_INT_RESERVED, - CAN_INT_PASSIVE = 5, - CAN_INT_ARBITRATION_LOST, - CAN_INT_BUS_ERROR, - CAN_INT_ALL, -}CAN_INT_Type; - -typedef enum { - CAN_STATUS_RECEIVE_BUFFER = 0, - CAN_STATUS_DATA_OVERRUN, - CAN_STATUS_TRANSMIT_BUFFER, - CAN_STATUS_TRANSMISSION_COMPLETE, - CAN_STATUS_RECEIVE, - CAN_STATUS_TRANSMIT, - CAN_STATUS_ERROR, - CAN_STATUS_BUS, -}CAN_STATUS_Type; - -typedef enum { - CAN_STATUS_RECEIVE_BUFFER_EMPTY = 0, - CAN_STATUS_RECEIVE_BUFFER_NONEMPTY = 1, - CAN_STATUS_DATA_OVERRUN_NULL = 0, - CAN_STATUS_DATA_OVERRUN_EXIST = 1, - CAN_STATUS_TRANSMIT_BUFFER_LOCKED = 0, - CAN_STATUS_TRANSMIT_BUFFER_ACCESSIBLE = 1, - CAN_STATUS_TRANSMISSION_COMPLETE_NOT = 0, - CAN_STATUS_TRANSMISSION_COMPLETE_YES = 1, - CAN_STATUS_RECEIVE_IDLE = 0, - CAN_STATUS_RECEIVE_ONGOING = 1, - CAN_STATUS_TRANSMIT_IDLE = 0, - CAN_STATUS_TRANSMIT_ONGOING = 1, - CAN_STATUS_ERROR_NULL = 0, - CAN_STATUS_ERROR_EXIST = 1, - CAN_STATUS_BUS_ON = 0, - CAN_STATUS_BUS_OFF = 1, -}CAN_STATUS_VALUE_Type; - -typedef enum { - CAN_ERROR_TYPE_BIT = 0, - CAN_ERROR_TYPE_FORM, - CAN_ERROR_TYPE_STUFF, - CAN_ERROR_TYPE_OTHERS, -}CAN_ERROR_CODE_Type; - -typedef enum { - CAN_ERROR_DIRECTION_TX = 0, - CAN_ERROR_DIRECTION_RX, -}CAN_ERROR_DIRECTION_Type; - -typedef enum { - CAN_ERROR_LOCATION_ID28_TO_ID21 = 2, - CAN_ERROR_LOCATION_START_OF_FRAME = 3, - CAN_ERROR_LOCATION_BIT_SRTR = 4, - CAN_ERROR_LOCATION_BIT_IDE = 5, - CAN_ERROR_LOCATION_ID20_TO_ID18 = 6, - CAN_ERROR_LOCATION_ID17_TO_ID13 = 7, - CAN_ERROR_LOCATION_CRC_SEQUENCE = 8, - CAN_ERROR_LOCATION_BIT_RESERVED_0 = 9, - CAN_ERROR_LOCATION_DATA_FIELD = 10, - CAN_ERROR_LOCATION_DATA_LENGTH_CODE = 11, - CAN_ERROR_LOCATION_BIT_RTR = 12, - CAN_ERROR_LOCATION_BIT_RESERVED_1 = 13, - CAN_ERROR_LOCATION_ID4_TO_ID0 = 14, - CAN_ERROR_LOCATION_ID12_TO_ID15 = 15, - CAN_ERROR_LOCATION_ACTIVE_ERROR_FLAG = 17, - CAN_ERROR_LOCATION_INTERMISSION = 18, - CAN_ERROR_LOCATION_BIT_TOLERATE_DOMINANT = 19, - CAN_ERROR_LOCATION_PASSIVE_ERROR_FLAG = 22, - CAN_ERROR_LOCATION_ERROR_DELIMITER = 23, - CAN_ERROR_LOCATION_CRC_DELIMITER = 24, - CAN_ERROR_LOCATION_ACK_SLOT = 25, - CAN_ERROR_LOCATION_END_OF_FRAME = 26, - CAN_ERROR_LOCATION_ACK_DELIMITER = 27, - CAN_ERROR_LOCATION_OVERLOAD_FLAG = 28, -} CAN_ERROR_LOCATION_Type; - -typedef enum { - CAN_FILTER_REGISTER_ACR0 = 0, - CAN_FILTER_REGISTER_ACR1, - CAN_FILTER_REGISTER_ACR2, - CAN_FILTER_REGISTER_ACR3, - CAN_FILTER_REGISTER_AMR0, - CAN_FILTER_REGISTER_AMR1, - CAN_FILTER_REGISTER_AMR2, - CAN_FILTER_REGISTER_AMR3, -} CAN_FILTER_REGISTER_Type; - -typedef struct { - CAN_ERROR_CODE_Type code; - CAN_ERROR_DIRECTION_Type dir; - CAN_ERROR_LOCATION_Type location; -} CAN_ERROR_Type; - -typedef struct { - CAN_FRAME_FORMAT_Type formatType; - CAN_MODE_VALUE_Type filterMode; - CAN_FRAME_Type matchRtr1; - CAN_FRAME_Type matchRtr2; - uint8_t matchData1; - uint8_t matchData2; - uint32_t matchId1; - uint32_t matchId2; - BL_Mask_Type maskRtr1; - BL_Mask_Type maskRtr2; - uint8_t maskData1; - uint8_t maskData2; - uint32_t maskId1; - uint32_t maskId2; -}CAN_FILTER_CFG_Type; - -typedef struct { - CAN_FRAME_Type frameType; - CAN_FRAME_FORMAT_Type frameFormat; - uint8_t dataLen; - uint8_t *dataAddr; - uint32_t id; - uint32_t timeout; -}CAN_CFG_Type; - -#define IS_CAN_FRAME_FORMAT_TYPE(type) (((type) == CAN_FRAME_FORMAT_STANDARD) || \ - ((type) == CAN_FRAME_FORMAT_EXTENDED)) - -#define IS_CAN_FRAME_TYPE(type) (((type) == CAN_FRAME_TYPE_DATA) || \ - ((type) == CAN_FRAME_TYPE_REMOTE)) - -#define IS_CAN_MODE_TYPE(type) (((type) == CAN_MODE_TYPE_RESET) || \ - ((type) == CAN_MODE_TYPE_LISTEN_ONLY) || \ - ((type) == CAN_MODE_TYPE_SELF_TSET) || \ - ((type) == CAN_MODE_TYPE_ACCEPTANCE_FILTER) || \ - -#define IS_CAN_MODE_VALUE_TYPE(type) (((type) == CAN_MODE_VALUE_NORMAL) || \ - ((type) == CAN_MODE_VALUE_RESET) || \ - ((type) == CAN_MODE_VALUE_LISTEN_ONLY) || \ - ((type) == CAN_MODE_VALUE_SELF_TSET) || \ - ((type) == CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL) || \ - ((type) == CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE) || \ - -#define IS_CAN_INT_TYPE(type) (((type) == CAN_INT_RECEIVE) || \ - ((type) == CAN_INT_TRANSMIT) || \ - ((type) == CAN_INT_ERROR_WARNING) || \ - ((type) == CAN_INT_OVERRUN) || \ - ((type) == CAN_INT_PASSIVE) || \ - ((type) == CAN_INT_ARBITRATION_LOST) || \ - ((type) == CAN_INT_BUSERROR) || \ - ((type) == CAN_INT_ALL)) - -#define IS_CAN_STATUS_TYPE(type) (((type) == CAN_STATUS_RECEIVE_BUFFER) || \ - ((type) == CAN_STATUS_DATA_OVERRUN) || \ - ((type) == CAN_STATUS_TRANSMIT_BUFFER) || \ - ((type) == CAN_STATUS_TRANSMISSION_COMPLETE) || \ - ((type) == CAN_STATUS_RECEIVE) || \ - ((type) == CAN_STATUS_TRANSMIT) || \ - ((type) == CAN_STATUS_ERROR) || \ - ((type) == CAN_STATUS_BUS)) - -#define IS_CAN_STATUS_VALUE_TYPE(type) (((type) == CAN_STATUS_VALUE_RECEIVE_BUFFER_EMPTY || \ - ((type) == CAN_STATUS_VALUE_RECEIVE_BUFFER_NONEMPTY || \ - ((type) == CAN_STATUS_VALUE_DATA_OVERRUN_NULL || \ - ((type) == CAN_STATUS_VALUE_DATA_OVERRUN_EXIST || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_BUFFER_LOCKED || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_BUFFER_ACCESSIBLE || \ - ((type) == CAN_STATUS_VALUE_TRANSMISSION_COMPLETE_NOT || \ - ((type) == CAN_STATUS_VALUE_TRANSMISSION_COMPLETE_YES || \ - ((type) == CAN_STATUS_VALUE_RECEIVE_IDLE || \ - ((type) == CAN_STATUS_VALUE_RECEIVE_ONGOING || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_IDLE || \ - ((type) == CAN_STATUS_VALUE_TRANSMIT_ONGOING || \ - ((type) == CAN_STATUS_VALUE_ERROR_NULL || \ - ((type) == CAN_STATUS_VALUE_ERROR_EXIST || \ - ((type) == CAN_STATUS_VALUE_BUS_ON || \ - ((type) == CAN_STATUS_VALUE_BUS_OFF)) - -void CAN_Init(void); -void CAN_Mode_Set(CAN_MODE_Type type, CAN_MODE_VALUE_Type value); -CAN_MODE_VALUE_Type CAN_Mode_Get(CAN_MODE_Type type); -void CAN_Int_Enable(CAN_INT_Type intType, BL_Fun_Type enable); -void CAN_Cmd_Request_Transmit(void); -void CAN_Cmd_Abort_Transmit(void); -void CAN_Cmd_Release_Recv_Buff(void); -void CAN_Cmd_Clear_Data_Overrun(void); -void CAN_Cmd_Request_Self_Reception(void); -CAN_STATUS_VALUE_Type CAN_Status_Get(CAN_STATUS_Type type); -uint8_t CAN_Arbitration_Lost_Position_Get(void); -void CAN_Error_Get(CAN_ERROR_Type *const code); -BL_Err_Type CAN_Error_Warning_Limit_Set(uint8_t limit); -uint8_t CAN_Error_Warning_Limit_Get(void); -uint8_t CAN_Error_Rx_Counter_Get(void); -uint8_t CAN_Error_Tx_Counter_Get(void); -BL_Err_Type CAN_Transmit(const CAN_CFG_Type *cfg); -BL_Err_Type CAN_Receive(CAN_CFG_Type *cfg); -uint8_t CAN_Receive_Buff_Frame_Count_Get(void); -BL_Err_Type CAN_Clock_Div_Set(uint8_t div); -uint8_t CAN_Clock_Div_Get(void); -BL_Err_Type CAN_Synchronization_Jump_Width_Set(uint8_t width); -uint8_t CAN_Synchronization_Jump_Width_Get(void); -BL_Err_Type CAN_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail); -void CAN_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail); -void CAN_Filter_Set(const CAN_FILTER_CFG_Type *cfg); -void CAN_Filter_Register_Set(CAN_FILTER_REGISTER_Type reg, uint8_t value); -void CAN_Filter_Registers_Set(uint8_t *valueArr); - -BL_Err_Type CAN_Int_Callback_Install(CAN_INT_Type intType, intCallback_Type *cbFun); -#endif /* __BL606p_CAN_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_common.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_common.h deleted file mode 100644 index dc0d456910..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_common.h +++ /dev/null @@ -1,56 +0,0 @@ -#ifndef __BL808_COMMON_H__ -#define __BL808_COMMON_H__ - -#include "bl808.h" -#include "misc.h" - -#ifndef __set_MSP -#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp)) -#endif - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup COMMON - * @{ - */ - -/** @defgroup COMMON_Public_Types - * @{ - */ - -/*@} end of group COMMON_Public_Types */ - -/** @defgroup COMMON_Public_Constants - * @{ - */ - -/** @defgroup DRIVER_INT_PERIPH - * @{ - */ -#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST) - -/*@} end of group DRIVER_INT_PERIPH */ - -/** @defgroup DRIVER_INT_MASK - * @{ - */ -#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK)) - -/*@} end of group COMMON_Public_Constants */ - -/** @defgroup DRIVER_Public_FunctionDeclaration - * @brief DRIVER functions declaration - * @{ - */ - -void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT); -void arch_delay_us(uint32_t cnt); -void arch_delay_ms(uint32_t cnt); - -void C906_All_Int_Enable(void); -void C906_All_Int_Disable(void); -/*@} end of group DRIVER_COMMON */ - -#endif /* __BL808_COMMON_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dac.h deleted file mode 100644 index 980930debe..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dac.h +++ /dev/null @@ -1,290 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dac.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DAC_H__ -#define __BL808_DAC_H__ - -#include "aon_reg.h" -#include "glb_reg.h" -#include "gpip_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Public_Types - * @{ - */ - -/** - * @brief DAC reference voltage definition - */ -typedef enum { - GLB_DAC_REF_SEL_INTERNAL, /*!< DAC reference select internal */ - GLB_DAC_REF_SEL_EXTERNAL, /*!< DAC reference select external */ -} GLB_DAC_Ref_Sel_Type; - -/** - * @brief DAC reference voltage definition - */ -typedef enum { - GLB_DAC_Output_Volt_0P2_1, /*!< DAC output voltage is 0.2-1V */ - GLB_DAC_Output_Volt_0P225_1P425, /*!< DAC output voltage is 0.225-1.425V */ - GLB_DAC_Output_Volt_RESEVED, /*!< DAC output voltage is 0.225-1.425V */ - GLB_DAC_Output_Volt_0P2_1P8, /*!< DAC output voltage is 0.2-1.8V */ -} GLB_DAC_Output_Volt_Range_Type; - -/** - * @brief DAC channel type definition - */ -typedef enum { - GLB_DAC_CHAN0, /*!< DAC channel 0 */ - GLB_DAC_CHAN1, /*!< DAC channel 1 */ - GLB_DAC_CHAN2, /*!< DAC channel 2 */ - GLB_DAC_CHAN3, /*!< DAC channel 3 */ - GLB_DAC_CHAN4, /*!< DAC channel 4 */ - GLB_DAC_CHAN5, /*!< DAC channel 5 */ - GLB_DAC_CHAN6, /*!< DAC channel 6 */ - GLB_DAC_CHAN7, /*!< DAC channel 7 */ - GLB_DAC_CHAN_ALL, /*!< DAC channel all */ -} GLB_DAC_Chan_Type; - -/** - * @brief DAC channel configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type chanEn; /*!< Enable this channel or not */ - BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ - GLB_DAC_Chan_Type outMux; /*!< DAC output mux,NOT implement yet,DAC use fixed GPIO9 and GPIO10 */ - GLB_DAC_Output_Volt_Range_Type outRange; /*!< DAC output voltage range */ -} GLB_DAC_Chan_Cfg_Type; - -/** - * @brief DAC configuration structure type definition - */ -typedef struct -{ - GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ - BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ - BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ -} GLB_DAC_Cfg_Type; - -/** - * @brief DAC channel B source selection type definition - */ -typedef enum { - GPIP_DAC_ChanB_SRC_REG, /*!< select Reg as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_DMA, /*!< select DMA as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_A, /*!< select channel A as source of DAC channel B */ - GPIP_DAC_ChanB_SRC_INVERSE_A, /*!< select inverse of channel A as source of DAC channel B */ -} GPIP_DAC_ChanB_SRC_Type; - -/** - * @brief DAC channel A source selection type definition - */ -typedef enum { - GPIP_DAC_ChanA_SRC_REG, /*!< select Reg as source of DAC channel A */ - GPIP_DAC_ChanA_SRC_DMA, /*!< select DMA as source of DAC channel A */ - GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER, /*!< select DMA with Filter as source of DAC channel A */ - GPIP_DAC_ChanA_SRC_SIN_GEN, /*!< select Sin Gen as source of DAC channel A */ -} GPIP_DAC_ChanA_SRC_Type; - -/** - * @brief DAC clock divider type definition - */ -typedef enum { - DAC_CLK_DIV_16, /*!< ADC clock:on 32M clock is 2M */ - DAC_CLK_DIV_32, /*!< ADC clock:on 32M clock is 1M */ - DAC_CLK_DIV_RESERVE, /*!< reserved */ - DAC_CLK_DIV_64, /*!< ADC clock:on 32M clock is 0.5M */ - DAC_CLK_DIV_1, /*!< ADC clock:on 32M clock is 32M */ -} DAC_CLK_Type; - -/** - * @brief DAC DMA TX format selection type definition - */ -typedef enum { - GPIP_DAC_DMA_FORMAT_0, /*!< {A0},{A1},{A2},... */ - GPIP_DAC_DMA_FORMAT_1, /*!< {B0,A0},{B1,A1},{B2,A2},... */ - GPIP_DAC_DMA_FORMAT_2, /*!< {A1,A0},{A3,A2},{A5,A4},... */ -} GPIP_DAC_DMA_TX_FORMAT_Type; - -/** - * @brief AON and GPIP DAC configuration structure type definition - */ -typedef struct -{ - GLB_DAC_Ref_Sel_Type refSel; /*!< DAC reference voltage select */ - BL_Fun_Type resetChanA; /*!< Reset DAC channel A */ - BL_Fun_Type resetChanB; /*!< Reset DAC channel B */ - DAC_CLK_Type div; /*!< DAC clock div */ - BL_Fun_Type dmaEn; /*!< DAC DMA transfer enable */ - GPIP_DAC_DMA_TX_FORMAT_Type dmaFmt; /*!< DAC DMA TX format selection */ -} GLB_GPIP_DAC_Cfg_Type; - -/** - * @brief AON and GPIP DAC channel A configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ - BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ - BL_Fun_Type chanEn; /*!< Enable this channel or not */ - GPIP_DAC_ChanA_SRC_Type src; /*!< DAC channel A source */ -} GLB_GPIP_DAC_ChanA_Cfg_Type; - -/** - * @brief AON and GPIP DAC channel B configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type chanCovtEn; /*!< Enable this channel conversion or not */ - BL_Fun_Type outputEn; /*!< Output this channel result to PAD */ - BL_Fun_Type chanEn; /*!< Enable this channel or not */ - GPIP_DAC_ChanB_SRC_Type src; /*!< DAC channel B source */ -} GLB_GPIP_DAC_ChanB_Cfg_Type; - -/*@} end of group DAC_Public_Types */ - -/** @defgroup DAC_Public_Constants - * @{ - */ - -/** @defgroup GLB_DAC_REF_SEL_TYPE - * @{ - */ -#define IS_GLB_DAC_REF_SEL_TYPE(type) (((type) == GLB_DAC_REF_SEL_INTERNAL) || \ - ((type) == GLB_DAC_REF_SEL_EXTERNAL)) - -/** @defgroup GLB_DAC_OUTPUT_VOLT_RANGE_TYPE - * @{ - */ -#define IS_GLB_DAC_OUTPUT_VOLT_RANGE_TYPE(type) (((type) == GLB_DAC_Output_Volt_0P2_1) || \ - ((type) == GLB_DAC_Output_Volt_0P225_1P425) || \ - ((type) == GLB_DAC_Output_Volt_RESEVED) || \ - ((type) == GLB_DAC_Output_Volt_0P2_1P8)) - -/** @defgroup GLB_DAC_CHAN_TYPE - * @{ - */ -#define IS_GLB_DAC_CHAN_TYPE(type) (((type) == GLB_DAC_CHAN0) || \ - ((type) == GLB_DAC_CHAN1) || \ - ((type) == GLB_DAC_CHAN2) || \ - ((type) == GLB_DAC_CHAN3) || \ - ((type) == GLB_DAC_CHAN4) || \ - ((type) == GLB_DAC_CHAN5) || \ - ((type) == GLB_DAC_CHAN6) || \ - ((type) == GLB_DAC_CHAN7) || \ - ((type) == GLB_DAC_CHAN_ALL)) - -/** @defgroup GPIP_DAC_CHANB_SRC_TYPE - * @{ - */ -#define IS_GPIP_DAC_CHANB_SRC_TYPE(type) (((type) == GPIP_DAC_ChanB_SRC_REG) || \ - ((type) == GPIP_DAC_ChanB_SRC_DMA) || \ - ((type) == GPIP_DAC_ChanB_SRC_DMA_WITH_FILTER) || \ - ((type) == GPIP_DAC_ChanB_SRC_SIN_GEN) || \ - ((type) == GPIP_DAC_ChanB_SRC_A) || \ - ((type) == GPIP_DAC_ChanB_SRC_INVERSE_A)) - -/** @defgroup GPIP_DAC_CHANA_SRC_TYPE - * @{ - */ -#define IS_GPIP_DAC_CHANA_SRC_TYPE(type) (((type) == GPIP_DAC_ChanA_SRC_REG) || \ - ((type) == GPIP_DAC_ChanA_SRC_DMA) || \ - ((type) == GPIP_DAC_ChanA_SRC_DMA_WITH_FILTER) || \ - ((type) == GPIP_DAC_ChanA_SRC_SIN_GEN)) - -/** @defgroup DAC_CLK_TYPE - * @{ - */ -#define IS_DAC_CLK_TYPE(type) (((type) == DAC_CLK_DIV_16) || \ - ((type) == DAC_CLK_DIV_32) || \ - ((type) == DAC_CLK_DIV_RESERVE) || \ - ((type) == DAC_CLK_DIV_64) || \ - ((type) == DAC_CLK_DIV_1)) - -/** @defgroup GPIP_DAC_DMA_TX_FORMAT_TYPE - * @{ - */ -#define IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(type) (((type) == GPIP_DAC_DMA_FORMAT_0) || \ - ((type) == GPIP_DAC_DMA_FORMAT_1) || \ - ((type) == GPIP_DAC_DMA_FORMAT_2)) - -/*@} end of group DAC_Public_Constants */ - -/** @defgroup DAC_Public_Macros - * @{ - */ - -/*@} end of group DAC_Public_Macros */ - -/** @defgroup DAC_Public_Functions - * @{ - */ -void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg); -void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg); -void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg); -void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src); -void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src); -void GPIP_DAC_ChanB_Enable(void); -void GPIP_DAC_ChanB_Disable(void); -void GPIP_DAC_ChanA_Enable(void); -void GPIP_DAC_ChanA_Disable(void); -void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt); -void GPIP_Set_DAC_DMA_TX_Enable(void); -void GPIP_Set_DAC_DMA_TX_Disable(void); -void GPIP_DAC_DMA_WriteData(uint32_t data); -BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg); -void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg); -void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg); -void GLB_DAC_Set_ChanA_Value(uint16_t val); -void GLB_DAC_Set_ChanB_Value(uint16_t val); - -/*@} end of group DAC_Public_Functions */ - -/*@} end of group DAC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DAC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dbi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dbi.h deleted file mode 100644 index 4bbdeb4aa4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dbi.h +++ /dev/null @@ -1,294 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dbi.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DBI_H__ -#define __BL808_DBI_H__ - -#include "dbi_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DBI - * @{ - */ - -/** @defgroup DBI_Public_Types - * @{ - */ - -/** - * @brief DBI mode type definition - */ -typedef enum { - DBI_TYPE_B = 0, /*!< DBI type B */ - DBI_TYPE_C_3_WIRE, /*!< DBI type C 3 wire mode */ - DBI_TYPE_C_4_WIRE, /*!< DBI type C 4 wire mode */ -} DBI_Mode_Type; - -/** - * @brief DBI pixel format type definition - */ -typedef enum { - DBI_PIXEL_RGB565 = 0, /*!< DBI pixel format is RGB565 */ - DBI_PIXEL_RGB666 = 1, /*!< DBI pixel format is RGB666 */ - DBI_PIXEL_RGB888 = 1, /*!< DBI pixel format is RGB888 */ -} DBI_Pixel_Format_Type; - -/** - * @brief DBI SCL clock phase definition - */ -typedef enum { - DBI_SCL_CLK_PHASE_0 = 0, /*!< DBI SCL clock phase 0 */ - DBI_SCL_CLK_PHASE_1, /*!< DBI SCL clock phase 1 */ -} DBI_SCL_CLK_Phase_Type; - -/** - * @brief DBI SCL clock polarity definition - */ -typedef enum { - DBI_SCL_CLK_POLARITY_LOW = 0, /*!< DBI SCL clock output low at idle state */ - DBI_SCL_CLK_POLARITY_HIGH, /*!< DBI SCL clock output high at idle state */ -} DBI_SCL_CLK_Polarity_Type; - -/** - * @brief DBI read/write data direction type definition - */ -typedef enum { - DBI_DATA_READ = 0, /*!< DBI read data */ - DBI_DATA_WRITE, /*!< DBI write data */ -} DBI_Data_Direction_Type; - -/** - * @brief DBI data type definition - */ -typedef enum { - DBI_DATA_NORMAL = 0, /*!< Normal data */ - DBI_DATA_PIXEL, /*!< Pixel data */ -} DBI_Data_Type; - -/** - * @brief DBI interrupt type definition - */ -typedef enum { - DBI_INT_END = 0, /*!< DBI transfer end interrupt,shared by both type B and C mode */ - DBI_INT_TX_FIFO_REQ, /*!< DBI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */ - DBI_INT_FIFO_ERR, /*!< DBI tx/rx fifo overflow/underflow error interrupt */ - DBI_INT_ALL, /*!< DBI all interrupt */ -} DBI_INT_Type; - -/** - * @brief DBI tx fifo overflow or underflow type definition - */ -typedef enum { - DBI_TX_OVERFLOW, /*!< DBI tx fifo overflow */ - DBI_TX_UNDERFLOW, /*!< DBI tx fifo underflow */ -} DBI_Overflow_Type; - -/** - * @brief DBI fifo format type definition - */ -typedef enum { - DBI_FIFO_888_NBGR = 0, /*!< DBI fifo format is None[31:24] B[23:16] G[15:8] R[7:0] */ - DBI_FIFO_888_NRGB, /*!< DBI fifo format is None[31:24] R[23:16] G[15:8] B[7:0] */ - DBI_FIFO_888_BGRN, /*!< DBI fifo format is B[31:24] G[23:16] R[15:8] None[7:0] */ - DBI_FIFO_888_RGBN, /*!< DBI fifo format is R[31:24] G[23:16] B[15:8] None[7:0] */ - DBI_FIFO_888_RGBR, /*!< DBI fifo format is R[31:24] G[23:16] B[15:8] R[7:0] */ - DBI_FIFO_888_BGRB, /*!< DBI fifo format is B[31:24] G[23:16] R[15:8] B[7:0] */ - DBI_FIFO_565_BGRBGR, /*!< DBI fifo format is B[31:27] G[26:21] R[20:16] B[15:11] G[10:5] R[4:0] */ - DBI_FIFO_565_RGBRGB, /*!< DBI fifo format is R[31:27] G[26:21] B[20:16] R[15:11] G[10:5] B[4:0] */ -} DBI_FIFO_Format_Type; - -typedef struct -{ - uint8_t startLen; /*!< Length of start/stop condition */ - uint8_t dataPhase0Len; /*!< Length of data phase 0 */ - uint8_t dataPhase1Len; /*!< Length of data phase 1 */ - uint8_t intervalLen; /*!< Length of interval between pixel data */ -}DBI_Period_CFG_Type; - -/** - * @brief DBI configuration structure type definition - */ -typedef struct -{ - DBI_Mode_Type mode; /*!< DBI type B or C select */ - DBI_Pixel_Format_Type pixelFormat; /*!< DBI pixel format */ - DBI_FIFO_Format_Type fifoFormat; /*!< DBI fifo format */ - BL_Fun_Type continueEn; /*!< Enable:CS will stay asserted between each consecutive pixel, disable:CS will de-assert between each pixel */ - BL_Fun_Type dummyEn; /*!< Enable:dummy cycle will be inserted between command phase adn data phase, disable:no dummy cycle */ - uint8_t dummyCnt; /*!< Dummy cycle count,effective only in type C(fixed to 1 in type B) */ - DBI_SCL_CLK_Phase_Type clkPhase; /*!< DBI clock phase */ - DBI_SCL_CLK_Polarity_Type clkPolarity; /*!< DBI clock polarity */ - DBI_Period_CFG_Type period; /*!< Period configuration */ -} DBI_CFG_Type; - -/** - * @brief DBI command and data configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type commandEn; /*!< Enable or disable command */ - uint8_t command; /*!< Command to send */ - BL_Fun_Type dataEn; /*!< Enable or disable data */ - DBI_Data_Type dataType; /*!< Select normal data or pixel data */ - DBI_Data_Direction_Type dataDir; /*!< Select read or write data */ - uint8_t dataCnt; /*!< Set byte count of normal data */ - uint32_t data; /*!< Data to send */ -} DBI_CD_CFG_Type; - -/*@} end of group DBI_Public_Types */ - -/** @defgroup DBI_Public_Constants - * @{ - */ - -/** @defgroup DBI_MODE_TYPE - * @{ - */ -#define IS_DBI_MODE_TYPE(type) (((type) == DBI_TYPE_B) || \ - ((type) == DBI_TYPE_C_3_WIRE) || \ - ((type) == DBI_TYPE_C_4_WIRE)) - -/** @defgroup DBI_PIXEL_FORMAT_TYPE - * @{ - */ -#define IS_DBI_PIXEL_FORMAT_TYPE(type) (((type) == DBI_PIXEL_RGB565) || \ - ((type) == DBI_PIXEL_RGB666) || \ - ((type) == DBI_PIXEL_RGB888)) - -/** @defgroup DBI_SCL_CLK_PHASE_TYPE - * @{ - */ -#define IS_DBI_SCL_CLK_PHASE_TYPE(type) (((type) == DBI_SCL_CLK_PHASE_0) || \ - ((type) == DBI_SCL_CLK_PHASE_1)) - -/** @defgroup DBI_SCL_CLK_POLARITY_TYPE - * @{ - */ -#define IS_DBI_SCL_CLK_POLARITY_TYPE(type) (((type) == DBI_SCL_CLK_POLARITY_LOW) || \ - ((type) == DBI_SCL_CLK_POLARITY_HIGH)) - -/** @defgroup DBI_DATA_DIRECTION_TYPE - * @{ - */ -#define IS_DBI_DATA_DIRECTION_TYPE(type) (((type) == DBI_DATA_READ) || \ - ((type) == DBI_DATA_WRITE)) - -/** @defgroup DBI_DATA_TYPE - * @{ - */ -#define IS_DBI_DATA_TYPE(type) (((type) == DBI_DATA_NORMAL) || \ - ((type) == DBI_DATA_PIXEL)) - -/** @defgroup DBI_INT_TYPE - * @{ - */ -#define IS_DBI_INT_TYPE(type) (((type) == DBI_INT_END) || \ - ((type) == DBI_INT_TX_FIFO_REQ) || \ - ((type) == DBI_INT_FIFO_ERR) || \ - ((type) == DBI_INT_ALL)) - -/** @defgroup DBI_OVERFLOW_TYPE - * @{ - */ -#define IS_DBI_OVERFLOW_TYPE(type) (((type) == DBI_TX_OVERFLOW) || \ - ((type) == DBI_TX_UNDERFLOW)) - -/** @defgroup DBI_FIFO_FORMAT_TYPE - * @{ - */ -#define IS_DBI_FIFO_FORMAT_TYPE(type) (((type) == DBI_FIFO_888_NBGR) || \ - ((type) == DBI_FIFO_888_NRGB) || \ - ((type) == DBI_FIFO_888_BGRN) || \ - ((type) == DBI_FIFO_888_RGBN) || \ - ((type) == DBI_FIFO_888_RGBR) || \ - ((type) == DBI_FIFO_888_BGRB) || \ - ((type) == DBI_FIFO_565_BGRBGR) || \ - ((type) == DBI_FIFO_565_RGBRGB)) - -/*@} end of group DBI_Public_Constants */ - -/** @defgroup DBI_Public_Macros - * @{ - */ -#define DBI_TX_FIFO_SIZE 8 - -/*@} end of group DBI_Public_Macros */ - -/** @defgroup DBI_Public_Functions - * @{ - */ -#ifndef BL808_USE_HAL_DRIVER -void DBI_IRQHandler(void); -#endif -BL_Err_Type DBI_Init(DBI_CFG_Type *dbiCfg); -void DBI_Enable(void); -void DBI_Disable(void); - -void DBI_SetPeriod(DBI_Period_CFG_Type *period); -void DBI_SetCommand(uint8_t Command); -void DBI_SetPhaseState(BL_Fun_Type commandEn, BL_Fun_Type dataEn); -void DBI_SetDataTypeAndCount(DBI_Data_Type dataType, uint32_t dataCount); -void DBI_SetNormalDataDir(DBI_Data_Direction_Type dataDir); -void DBI_ReadNormlData(uint8_t dataSize, uint8_t *dataBuff); -void DBI_WriteNormlData(uint8_t dataSize, uint8_t *dataBuff); -void DBI_WirteData2FIFO(uint32_t wordCount, uint32_t *dataBuff); - -uint32_t DBI_GetWordCountOfPixelData(int32_t PixelCount); -void DBI_SendCmdWithNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff); -void DBI_SendCmdAndReadNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff); -void DBI_SendCmdWithPixelData(uint8_t command, int32_t PixelCount, uint32_t *pixelBuff); - -void DBI_TxFifoClear(void); -void DBI_SetDMA(BL_Fun_Type dmaEn); -void DBI_SetTxFifoThreshold(uint8_t threshold); -uint8_t DBI_GetTxFifoCount(void); -BL_Sts_Type DBI_GetIntStatus(DBI_INT_Type intType); -BL_Sts_Type DBI_GetOverflowStatus(DBI_Overflow_Type overflow); -BL_Sts_Type DBI_GetBusBusyStatus(void); -void DBI_IntMask(DBI_INT_Type intType, BL_Mask_Type intMask); -void DBI_IntClear(void); -void DBI_Int_Callback_Install(DBI_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group DBI_Public_Functions */ - -/*@} end of group DBI */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DBI_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma.h deleted file mode 100644 index 49787ac2e4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma.h +++ /dev/null @@ -1,439 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DMA_H__ -#define __BL808_DMA_H__ - -#include "dma_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Public_Types - * @{ - */ - -/** - * @brief DMA port type definition - */ -typedef enum { - DMA0_ID, /*!< DMA0 port define,WLSYS,8 channels */ - DMA1_ID, /*!< DMA1 port define,WLSYS,4 channels */ - DMA2_ID, /*!< DMA2 port define,MMSYS,8 channels */ - DMA_ID_MAX, /*!< DMA MAX ID define */ -} DMA_ID_Type; - -/** - * @brief DMA endian type definition - */ -typedef enum { - DMA_LITTLE_ENDIAN = 0, /*!< DMA use little endian */ - DMA_BIG_ENDIAN, /*!< DMA use big endian */ -} DMA_Endian_Type; - -/** - * @brief DMA synchronization logic type definition - */ -typedef enum { - DMA_SYNC_LOGIC_ENABLE = 0, /*!< DMA synchronization logic enable */ - DMA_SYNC_LOGIC_DISABLE, /*!< DMA synchronization logic disable */ -} DMA_Sync_Logic_Type; - -/** - * @brief DMA transfer width type definition - */ -typedef enum { - DMA_TRNS_WIDTH_8BITS = 0, /*!< DMA transfer width:8 bits */ - DMA_TRNS_WIDTH_16BITS, /*!< DMA transfer width:16 bits */ - DMA_TRNS_WIDTH_32BITS, /*!< DMA transfer width:32 bits */ - DMA_TRNS_WIDTH_64BITS, /*!< DMA transfer width:64 bits, only for DMA2 channel 0 and channel 1, others should not use this */ -} DMA_Trans_Width_Type; - -/** - * @brief DMA transfer direction type definition - */ -typedef enum { - DMA_TRNS_M2M = 0, /*!< DMA transfer tyep:memory to memory */ - DMA_TRNS_M2P, /*!< DMA transfer tyep:memory to peripheral */ - DMA_TRNS_P2M, /*!< DMA transfer tyep:peripheral to memory */ - DMA_TRNS_P2P, /*!< DMA transfer tyep:peripheral to peripheral */ -} DMA_Trans_Dir_Type; - -/** - * @brief DMA burst size type definition - */ -typedef enum { - DMA_BURST_SIZE_1 = 0, /*!< DMA burst size:1 * transfer width */ - DMA_BURST_SIZE_4, /*!< DMA burst size:4 * transfer width */ - DMA_BURST_SIZE_8, /*!< DMA burst size:8 * transfer width */ - DMA_BURST_SIZE_16, /*!< DMA burst size:16 * transfer width */ -} DMA_Burst_Size_Type; - -/** - * @brief DMA destination peripheral type definition - */ -typedef enum { - DMA_REQ_UART0_RX = 0, /*!< DMA request peripheral:UART0 RX, DMA0 and DMA1 support */ - DMA_REQ_UART0_TX = 1, /*!< DMA request peripheral:UART0 TX, DMA0 and DMA1 support */ - DMA_REQ_UART1_RX = 2, /*!< DMA request peripheral:UART1 RX, DMA0 and DMA1 support */ - DMA_REQ_UART1_TX = 3, /*!< DMA request peripheral:UART1 TX, DMA0 and DMA1 support */ - DMA_REQ_UART2_RX = 4, /*!< DMA request peripheral:UART2 RX, DMA0 and DMA1 support */ - DMA_REQ_UART2_TX = 5, /*!< DMA request peripheral:UART2 TX, DMA0 and DMA1 support */ - DMA_REQ_I2C0_RX = 6, /*!< DMA request peripheral:I2C0 RX, DMA0 and DMA1 support */ - DMA_REQ_I2C0_TX = 7, /*!< DMA request peripheral:I2C0 TX, DMA0 and DMA1 support */ - DMA_REQ_IR_TX = 8, /*!< DMA request peripheral:IR TX, DMA0 and DMA1 support */ - DMA_REQ_GPIO_TX = 9, /*!< DMA request peripheral:GPIO TX, DMA0 and DMA1 support */ - DMA_REQ_SPI0_RX = 10, /*!< DMA request peripheral:SPI0 RX, DMA0 and DMA1 support */ - DMA_REQ_SPI0_TX = 11, /*!< DMA request peripheral:SPI0 TX, DMA0 and DMA1 support */ - DMA_REQ_AUDIO_RX = 12, /*!< DMA request peripheral:AUDIO RX, DMA0 and DMA1 support */ - DMA_REQ_AUDIO_TX = 13, /*!< DMA request peripheral:AUDIO TX, DMA0 and DMA1 support */ - DMA_REQ_I2C1_RX = 14, /*!< DMA request peripheral:I2C1 RX, DMA0 and DMA1 support */ - DMA_REQ_I2C1_TX = 15, /*!< DMA request peripheral:I2C1 TX, DMA0 and DMA1 support */ - DMA_REQ_I2S_RX = 16, /*!< DMA request peripheral:I2S RX, DMA0 and DMA1 support */ - DMA_REQ_I2S_TX = 17, /*!< DMA request peripheral:I2S TX, DMA0 and DMA1 support */ - DMA_REQ_PDM_RX = 18, /*!< DMA request peripheral:PDM RX, DMA0 and DMA1 support */ - DMA_REQ_GPADC_RX = 22, /*!< DMA request peripheral:GPADC RX, DMA0 and DMA1 support */ - DMA_REQ_GPADC_TX = 23, /*!< DMA request peripheral:GPADC TX, DMA0 and DMA1 support */ - DMA_REQ_UART3_RX = 0, /*!< DMA request peripheral:UART3 RX, only DMA2 support */ - DMA_REQ_UART3_TX = 1, /*!< DMA request peripheral:UART3 TX, only DMA2 support */ - DMA_REQ_SPI1_RX = 2, /*!< DMA request peripheral:SPI1 RX, only DMA2 support */ - DMA_REQ_SPI1_TX = 3, /*!< DMA request peripheral:SPI1 TX, only DMA2 support */ - DMA_REQ_I2C2_RX = 6, /*!< DMA request peripheral:I2C2 RX, only DMA2 support */ - DMA_REQ_I2C2_TX = 7, /*!< DMA request peripheral:I2C2 TX, only DMA2 support */ - DMA_REQ_I2C3_RX = 8, /*!< DMA request peripheral:I2C3 RX, only DMA2 support */ - DMA_REQ_I2C3_TX = 9, /*!< DMA request peripheral:I2C3 TX, only DMA2 support */ - DMA_REQ_DSI_RX = 10, /*!< DMA request peripheral:DSI RX, only DMA2 support */ - DMA_REQ_DSI_TX = 11, /*!< DMA request peripheral:DSI TX, only DMA2 support */ - DMA_REQ_DBI_TX = 22, /*!< DMA request peripheral:DBI TX, only DMA2 support */ - DMA_REQ_NONE = 0, /*!< DMA request peripheral:None */ -} DMA_Periph_Req_Type; - -/** - * @brief DMA channel type definition - */ -typedef enum { - DMA_CH0 = 0, /*!< DMA channel 0 */ - DMA_CH1, /*!< DMA channel 1 */ - DMA_CH2, /*!< DMA channel 2 */ - DMA_CH3, /*!< DMA channel 3 */ - DMA_CH4, /*!< DMA channel 4 */ - DMA_CH5, /*!< DMA channel 5 */ - DMA_CH6, /*!< DMA channel 6 */ - DMA_CH7, /*!< DMA channel 7 */ - DMA_CH_MAX, /*!< */ -} DMA_Chan_Type; - -/** - * @brief DMA LLI Structure PING-PONG - */ -typedef enum { - PING_INDEX = 0, /*!< PING INDEX */ - PONG_INDEX, /*!< PONG INDEX */ -} DMA_LLI_PP_Index_Type; - -/** - * @brief DMA interrupt type definition - */ -typedef enum { - DMA_INT_TCOMPLETED = 0, /*!< DMA completed interrupt */ - DMA_INT_ERR, /*!< DMA error interrupt */ - DMA_INT_ALL, /*!< All the interrupt */ -} DMA_INT_Type; - -/** - * @brief DMA Configuration Structure type definition - */ -typedef struct -{ - DMA_Endian_Type endian; /*!< DMA endian type */ - DMA_Sync_Logic_Type syncLogic; /*!< DMA synchronization logic */ -} DMA_Cfg_Type; - -/** - * @brief DMA channel Configuration Structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ - uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */ - DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA_Chan_Type ch; /*!< Channel select 0-7 */ - DMA_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2 channel 0 and - channel 1) */ - DMA_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2 channel 0 and - channel 1) */ - DMA_Burst_Size_Type srcBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - DMA_Burst_Size_Type dstBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - BL_Fun_Type dstAddMode; /*!< */ - BL_Fun_Type dstMinMode; /*!< */ - uint8_t fixCnt; /*!< */ - uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */ - uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */ - DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA_Channel_Cfg_Type; - -/** - * @brief DMA LLI control structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA transfer */ - uint32_t nextLLI; /*!< Next LLI address */ - struct DMA_Control_Reg dmaCtrl; /*!< DMA transaction control */ -} DMA_LLI_Ctrl_Type; - -/** - * @brief DMA LLI configuration structure type definition - */ -typedef struct -{ - DMA_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA_LLI_Cfg_Type; - -/** - * @brief DMA LLI Ping-Pong Buf definition - */ -typedef struct -{ - uint8_t idleIndex; /*!< Index Idle lliListHeader */ - uint8_t dmaId; /*!< DMA ID used */ - uint8_t dmaChan; /*!< DMA LLI Channel used */ - DMA_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */ - void (*onTransCompleted)(DMA_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */ -} DMA_LLI_PP_Buf; - -/** - * @brief DMA LLI Ping-Pong Structure definition - */ -typedef struct -{ - uint8_t pingpongIndex; /*!< Ping or Pong Trigger TC */ - uint8_t dmaId; /*!< DMA ID used */ - uint8_t dmaChan; /*!< DMA LLI Channel used */ - struct DMA_Control_Reg dmaCtrlRegVal; /*!< DMA Basic Pararmeter */ - DMA_LLI_Cfg_Type *lliCfg; /*!< LLI Config parameter */ - uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */ - uint32_t pingpongBufAddr[2]; /*!< Ping-Pong addr */ -} DMA_LLI_PP_Struct; - -/*@} end of group DMA_Public_Types */ - -/** @defgroup DMA_Public_Constants - * @{ - */ - -/** @defgroup DMA_ID_TYPE - * @{ - */ -#define IS_DMA_ID_TYPE(type) (((type) == DMA0_ID) || \ - ((type) == DMA1_ID) || \ - ((type) == DMA2_ID) || \ - ((type) == DMA_ID_MAX)) - -/** @defgroup DMA_ENDIAN_TYPE - * @{ - */ -#define IS_DMA_ENDIAN_TYPE(type) (((type) == DMA_LITTLE_ENDIAN) || \ - ((type) == DMA_BIG_ENDIAN)) - -/** @defgroup DMA_SYNC_LOGIC_TYPE - * @{ - */ -#define IS_DMA_SYNC_LOGIC_TYPE(type) (((type) == DMA_SYNC_LOGIC_ENABLE) || \ - ((type) == DMA_SYNC_LOGIC_DISABLE)) - -/** @defgroup DMA_TRANS_WIDTH_TYPE - * @{ - */ -#define IS_DMA_TRANS_WIDTH_TYPE(type) (((type) == DMA_TRNS_WIDTH_8BITS) || \ - ((type) == DMA_TRNS_WIDTH_16BITS) || \ - ((type) == DMA_TRNS_WIDTH_32BITS) || \ - ((type) == DMA_TRNS_WIDTH_64BITS)) - -/** @defgroup DMA_TRANS_DIR_TYPE - * @{ - */ -#define IS_DMA_TRANS_DIR_TYPE(type) (((type) == DMA_TRNS_M2M) || \ - ((type) == DMA_TRNS_M2P) || \ - ((type) == DMA_TRNS_P2M) || \ - ((type) == DMA_TRNS_P2P)) - -/** @defgroup DMA_BURST_SIZE_TYPE - * @{ - */ -#define IS_DMA_BURST_SIZE_TYPE(type) (((type) == DMA_BURST_SIZE_1) || \ - ((type) == DMA_BURST_SIZE_4) || \ - ((type) == DMA_BURST_SIZE_8) || \ - ((type) == DMA_BURST_SIZE_16)) - -/** @defgroup DMA_PERIPH_REQ_TYPE - * @{ - */ -#define IS_DMA_PERIPH_REQ_TYPE(type) (((type) == DMA_REQ_UART0_RX) || \ - ((type) == DMA_REQ_UART0_TX) || \ - ((type) == DMA_REQ_UART1_RX) || \ - ((type) == DMA_REQ_UART1_TX) || \ - ((type) == DMA_REQ_UART2_RX) || \ - ((type) == DMA_REQ_UART2_TX) || \ - ((type) == DMA_REQ_I2C0_RX) || \ - ((type) == DMA_REQ_I2C0_TX) || \ - ((type) == DMA_REQ_IR_TX) || \ - ((type) == DMA_REQ_GPIO_TX) || \ - ((type) == DMA_REQ_SPI0_RX) || \ - ((type) == DMA_REQ_SPI0_TX) || \ - ((type) == DMA_REQ_AUDIO_RX) || \ - ((type) == DMA_REQ_AUDIO_TX) || \ - ((type) == DMA_REQ_I2C1_RX) || \ - ((type) == DMA_REQ_I2C1_TX) || \ - ((type) == DMA_REQ_I2S_RX) || \ - ((type) == DMA_REQ_I2S_TX) || \ - ((type) == DMA_REQ_PDM_RX) || \ - ((type) == DMA_REQ_GPADC_RX) || \ - ((type) == DMA_REQ_GPADC_TX) || \ - ((type) == DMA_REQ_UART3_RX) || \ - ((type) == DMA_REQ_UART3_TX) || \ - ((type) == DMA_REQ_SPI1_RX) || \ - ((type) == DMA_REQ_SPI1_TX) || \ - ((type) == DMA_REQ_I2C2_RX) || \ - ((type) == DMA_REQ_I2C2_TX) || \ - ((type) == DMA_REQ_I2C3_RX) || \ - ((type) == DMA_REQ_I2C3_TX) || \ - ((type) == DMA_REQ_DSI_RX) || \ - ((type) == DMA_REQ_DBI_TX) || \ - ((type) == DMA_REQ_DBI_TX) || \ - ((type) == DMA_REQ_NONE)) - -/** @defgroup DMA_CHAN_TYPE - * @{ - */ -#define IS_DMA_CHAN_TYPE(type) (((type) == DMA_CH0) || \ - ((type) == DMA_CH1) || \ - ((type) == DMA_CH2) || \ - ((type) == DMA_CH3) || \ - ((type) == DMA_CH4) || \ - ((type) == DMA_CH5) || \ - ((type) == DMA_CH6) || \ - ((type) == DMA_CH7) || \ - ((type) == DMA_CH_MAX)) - -/** @defgroup DMA_LLI_PP_INDEX_TYPE - * @{ - */ -#define IS_DMA_LLI_PP_INDEX_TYPE(type) (((type) == PING_INDEX) || \ - ((type) == PONG_INDEX)) - -/** @defgroup DMA_INT_TYPE - * @{ - */ -#define IS_DMA_INT_TYPE(type) (((type) == DMA_INT_TCOMPLETED) || \ - ((type) == DMA_INT_ERR) || \ - ((type) == DMA_INT_ALL)) - -/*@} end of group DMA_Public_Constants */ - -/** @defgroup DMA_Public_Macros - * @{ - */ -#define DMA_PINC_ENABLE 1 -#define DMA_PINC_DISABLE 0 -#define DMA_MINC_ENABLE 1 -#define DMA_MINC_DISABLE 0 - -/*@} end of group DMA_Public_Macros */ - -/** @defgroup DMA_Public_Functions - * @{ - */ - -/** - * @brief DMA Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void DMA0_ALL_IRQHandler(void); -void DMA1_ALL_IRQHandler(void); -void DMA2_INT0_IRQHandler(void); -void DMA2_INT1_IRQHandler(void); -void DMA2_INT2_IRQHandler(void); -void DMA2_INT3_IRQHandler(void); -void DMA2_INT4_IRQHandler(void); -void DMA2_INT5_IRQHandler(void); -void DMA2_INT6_IRQHandler(void); -void DMA2_INT7_IRQHandler(void); -#endif -void DMA_Enable(DMA_ID_Type dmaId); -void DMA_Disable(DMA_ID_Type dmaId); -void DMA_Channel_Init(DMA_ID_Type dmaId, DMA_Channel_Cfg_Type *chCfg); -void DMA_DeInit(DMA_ID_Type dmaId); -void DMA_Channel_Update_SrcMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -void DMA_Channel_Update_DstMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -uint32_t DMA_Channel_TranferSize(DMA_ID_Type dmaId, uint8_t ch); -BL_Sts_Type DMA_Channel_Is_Busy(DMA_ID_Type dmaId, uint8_t ch); -void DMA_Channel_Enable(DMA_ID_Type dmaId, uint8_t ch); -void DMA_Channel_Disable(DMA_ID_Type dmaId, uint8_t ch); -void DMA_LLI_Init(DMA_ID_Type dmaId, uint8_t ch, DMA_LLI_Cfg_Type *lliCfg); -void DMA_LLI_Update(DMA_ID_Type dmaId, uint8_t ch, uint32_t LLI); -uint32_t DMA_LLI_Get_Counter(DMA_ID_Type dmaId, uint8_t ch); -void DMA_IntMask(DMA_ID_Type dmaId, uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask); -void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf); -DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf); -void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList); -void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf); -void DMA_Int_Callback_Install(DMA_ID_Type dmaId, DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun); -void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct); -void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, - uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len); - -/*@} end of group DMA_Public_Functions */ - -/*@} end of group DMA */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DMA_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma2d.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma2d.h deleted file mode 100644 index dd51a48aa5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dma2d.h +++ /dev/null @@ -1,492 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma2d.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DMA2D_H__ -#define __BL808_DMA2D_H__ - -#include "dma2d_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA2D - * @{ - */ - -/** @defgroup DMA2D_Public_Types - * @{ - */ - -/** - * @brief DMA2D port type definition - */ -typedef enum { - DMA2D0_ID, /*!< DMA2D0 port define */ - DMA2D_ID_MAX, /*!< DMA2D MAX ID define */ -} DMA2D_ID_Type; - -/** - * @brief DMA2D endian type definition - */ -typedef enum { - DMA2D_LITTLE_ENDIAN = 0, /*!< DMA2D use little endian */ - DMA2D_BIG_ENDIAN, /*!< DMA2D use big endian */ -} DMA2D_Endian_Type; - -/** - * @brief DMA2D synchronization logic type definition - */ -typedef enum { - DMA2D_SYNC_LOGIC_ENABLE = 0, /*!< DMA2D synchronization logic enable */ - DMA2D_SYNC_LOGIC_DISABLE, /*!< DMA2D synchronization logic disable */ -} DMA2D_Sync_Logic_Type; - -/** - * @brief DMA2D transfer width type definition - */ -typedef enum { - DMA2D_TRNS_WIDTH_8BITS = 0, /*!< DMA2D transfer width:8 bits */ - DMA2D_TRNS_WIDTH_16BITS, /*!< DMA2D transfer width:16 bits */ - DMA2D_TRNS_WIDTH_32BITS, /*!< DMA2D transfer width:32 bits */ -} DMA2D_Trans_Width_Type; - -/** - * @brief DMA2D transfer direction type definition - */ -typedef enum { - DMA2D_TRNS_M2M = 0, /*!< DMA2D transfer type:memory to memory */ - DMA2D_TRNS_M2P, /*!< DMA2D transfer type:memory to peripheral */ - DMA2D_TRNS_P2M, /*!< DMA2D transfer type:peripheral to memory */ - DMA2D_TRNS_P2P, /*!< DMA2D transfer type:peripheral to peripheral */ -} DMA2D_Trans_Dir_Type; - -/** - * @brief DMA2D burst size type definition - */ -typedef enum { - DMA2D_BURST_SIZE_1 = 0, /*!< DMA2D burst size:1 * transfer width */ - DMA2D_BURST_SIZE_4, /*!< DMA2D burst size:4 * transfer width */ - DMA2D_BURST_SIZE_8, /*!< DMA2D burst size:8 * transfer width */ - DMA2D_BURST_SIZE_16, /*!< DMA2D burst size:16 * transfer width */ -} DMA2D_Burst_Size_Type; - -/** - * @brief DMA2D destination peripheral type definition - */ -typedef enum { - DMA2D_REQ_UART0_RX = 0, /*!< DMA2D request peripheral:UART0 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART0_TX = 1, /*!< DMA2D request peripheral:UART0 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART1_RX = 2, /*!< DMA2D request peripheral:UART1 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART1_TX = 3, /*!< DMA2D request peripheral:UART1 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART2_RX = 4, /*!< DMA2D request peripheral:UART2 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART2_TX = 5, /*!< DMA2D request peripheral:UART2 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_I2C0_RX = 6, /*!< DMA2D request peripheral:I2C0 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_I2C0_TX = 7, /*!< DMA2D request peripheral:I2C0 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_IR_TX = 8, /*!< DMA2D request peripheral:IR TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_GPIO = 9, /*!< DMA2D request peripheral:GPIO, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_SPI0_RX = 10, /*!< DMA2D request peripheral:SPI0 RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_SPI0_TX = 11, /*!< DMA2D request peripheral:SPI0 TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_AUDIO_RX = 12, /*!< DMA2D request peripheral:AUDIO RX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_AUDIO_TX = 13, /*!< DMA2D request peripheral:AUDIO TX, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_GPADC0 = 22, /*!< DMA2D request peripheral:GPADC0, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_GPADC1 = 23, /*!< DMA2D request peripheral:GPADC1, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP0 = 24, /*!< DMA2D request peripheral:USB EP 0, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP1 = 25, /*!< DMA2D request peripheral:USB EP 1, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP2 = 26, /*!< DMA2D request peripheral:USB EP 2, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP3 = 27, /*!< DMA2D request peripheral:USB EP 3, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP4 = 28, /*!< DMA2D request peripheral:USB EP 4, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP5 = 29, /*!< DMA2D request peripheral:USB EP 5, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP6 = 30, /*!< DMA2D request peripheral:USB EP 6, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_USB_EP7 = 31, /*!< DMA2D request peripheral:USB EP 7, DMA2D0 and DMA2D1 support */ - DMA2D_REQ_UART3_RX = 0, /*!< DMA2D request peripheral:UART3 RX, only DMA2D2 support */ - DMA2D_REQ_UART3_TX = 1, /*!< DMA2D request peripheral:UART3 TX, only DMA2D2 support */ - DMA2D_REQ_SPI1_RX = 2, /*!< DMA2D request peripheral:SPI1 RX, only DMA2D2 support */ - DMA2D_REQ_SPI1_TX = 3, /*!< DMA2D request peripheral:SPI1 TX, only DMA2D2 support */ - DMA2D_REQ_I2C1_RX = 6, /*!< DMA2D request peripheral:I2C1 RX, only DMA2D2 support */ - DMA2D_REQ_I2C1_TX = 7, /*!< DMA2D request peripheral:I2C1 TX, only DMA2D2 support */ - DMA2D_REQ_I2S_TX = 12, /*!< DMA2D request peripheral:I2S TX, only DMA2D2 support */ - DMA2D_REQ_I2S_RX = 13, /*!< DMA2D request peripheral:I2S RX, only DMA2D2 support */ - DMA2D_REQ_DBI_TX = 22, /*!< DMA2D request peripheral:DBI TX, only DMA2D2 support */ - DMA2D_REQ_NONE = 0, /*!< DMA2D request peripheral:None */ -} DMA2D_Periph_Req_Type; - -/** - * @brief DMA2D channel type definition - */ -typedef enum { - DMA2D_CH0 = 0, /*!< DMA2D channel 0 */ - DMA2D_CH1, /*!< DMA2D channel 1 */ - DMA2D_CH_MAX, /*!< */ -} DMA2D_Chan_Type; - -/** - * @brief DMA2D LLI Structure PING-PONG - */ -typedef enum { - DMA2D_PING_INDEX = 0, /*!< PING INDEX */ - DMA2D_PONG_INDEX, /*!< PONG INDEX */ -} DMA2D_LLI_PP_Index_Type; - -/** - * @brief DMA2D interrupt type definition - */ -typedef enum { - DMA2D_INT_TCOMPLETED = 0, /*!< DMA2D completed interrupt */ - DMA2D_INT_ALL, /*!< All the interrupt */ -} DMA2D_INT_Type; - -/** - * @brief DMA2D rotate type definition - */ -typedef enum { - DMA2D_ROTATE_DEGREE_90 = 0, /*!< DMA2D rotate 90 degrees */ - DMA2D_ROTATE_DEGREE_180, /*!< DMA2D rotate 180 degrees */ - DMA2D_ROTATE_DEGREE_270, /*!< DMA2D rotate 270 degrees */ -} DMA2D_Rotate_Type; - -/** - * @brief DMA2D fold type definition - */ -typedef enum { - DMA2D_FOLD_LEFT_RIGHT = 0, /*!< DMA2D fold left and right */ - DMA2D_FOLD_UP_DOWN, /*!< DMA2D fold up and down */ -} DMA2D_Fold_Type; - -/** - * @brief DMA2D color key type definition - */ -typedef enum { - DMA2D_COLOR_KEY_8BIT = 0, /*!< DMA2D color key is 8-bit */ - DMA2D_COLOR_KEY_16BIT, /*!< DMA2D color key is 16-bit */ - DMA2D_COLOR_KEY_24BIT, /*!< DMA2D color key is 24-bit */ - DMA2D_COLOR_KEY_32BIT, /*!< DMA2D color key is 32-bit */ -} DMA2D_Color_Key_Type; - -/** - * @brief DMA2D channel Configuration Structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA2D transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA2D transfer */ - uint32_t transfLength; /*!< Transfer length, 0~4095, this is burst count */ - DMA2D_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA2D_Chan_Type ch; /*!< Channel select 0-7 */ - DMA2D_Trans_Width_Type srcTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2D2 channel 0 and - channel 1) */ - DMA2D_Trans_Width_Type dstTransfWidth; /*!< Transfer width. 0: 8 bits, 1: 16 bits, 2: 32 bits, 3: 64 bits(only for DMA2D2 channel 0 and - channel 1) */ - DMA2D_Burst_Size_Type srcBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - DMA2D_Burst_Size_Type dstBurstSize; /*!< Number of data items for burst transaction length. Each item width is as same as tansfer width. - 0: 1 item, 1: 4 items, 2: 8 items, 3: 16 items */ - uint8_t srcAddrInc; /*!< Source address increment. 0: No change, 1: Increment */ - uint8_t destAddrInc; /*!< Destination address increment. 0: No change, 1: Increment */ - DMA2D_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA2D_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA2D_Channel_Cfg_Type; - -/** - * @brief DMA2D configuration Structure definition - */ -typedef struct -{ - uint16_t srcCntX; /*!< Source x count */ - uint16_t srcCntY; /*!< Source y count */ - int32_t srcIncrX; /*!< Source x increment */ - int32_t srcIncrY; /*!< Source y increment */ - uint16_t dstCntX; /*!< Destination x count */ - uint16_t reserve; /*!< Reserved */ - int32_t dstIncrX; /*!< Destination x increment */ - int32_t dstIncrY; /*!< Destination y increment */ -} DMA2D_Cfg_Type; - -/** - * @brief DMA2D LLI control structure type definition - */ -typedef struct -{ - uint32_t srcDmaAddr; /*!< Source address of DMA2D transfer */ - uint32_t destDmaAddr; /*!< Destination address of DMA2D transfer */ - uint32_t nextLLI; /*!< Next LLI address */ - struct DMA2D_Control_Reg dmaCtrl; /*!< DMA2D transaction control */ - DMA2D_Cfg_Type dma2dCfg; /*!< DMA2D configuration */ -} DMA2D_LLI_Ctrl_Type; - -/** - * @brief DMA2D LLI configuration structure type definition - */ -typedef struct -{ - DMA2D_Trans_Dir_Type dir; /*!< Transfer dir control. 0: Memory to Memory, 1: Memory to peripheral, 2: Peripheral to memory */ - DMA2D_Periph_Req_Type srcPeriph; /*!< Source peripheral select */ - DMA2D_Periph_Req_Type dstPeriph; /*!< Destination peripheral select */ -} DMA2D_LLI_Cfg_Type; - -/** - * @brief DMA2D LLI Ping-Pong Buf definition - */ -typedef struct -{ - uint8_t idleIndex; /*!< Index Idle lliListHeader */ - uint8_t dmaId; /*!< DMA2D ID used */ - uint8_t dmaChan; /*!< DMA2D LLI Channel used */ - DMA2D_LLI_Ctrl_Type *lliListHeader[2]; /*!< Ping-Pong BUf List Header */ - void (*onTransCompleted)(DMA2D_LLI_Ctrl_Type *); /*!< Completed Transmit One List Callback Function */ -} DMA2D_LLI_PP_Buf; - -/** - * @brief DMA2D LLI Ping-Pong Structure definition - */ -typedef struct -{ - uint8_t pingpongIndex; /*!< Ping or Pong Trigger TC */ - uint8_t dmaId; /*!< DMA2D ID used */ - uint8_t dmaChan; /*!< DMA2D LLI Channel used */ - struct DMA2D_Control_Reg dmaCtrlRegVal; /*!< DMA2D Basic Pararmeter */ - DMA2D_LLI_Cfg_Type *lliCfg; /*!< LLI Config parameter */ - uint32_t operatePeriphAddr; /*!< Operate Peripheral register address */ - uint32_t pingpongBufAddr[2]; /*!< Ping-Pong addr */ -} DMA2D_LLI_PP_Struct; - -/** - * @brief DMA2D picture configure definition - */ -typedef struct -{ - DMA2D_Trans_Width_Type transWidth; /*!< Transfer width */ - uint32_t pixWidth; /*!< Pixel width, unit: byte */ - uint32_t srcAddr; /*!< Source address */ - uint32_t srcWidth; /*!< Source picture width */ - uint32_t srcX0; /*!< Source start x */ - uint32_t srcY0; /*!< Source start y */ - uint32_t srcX1; /*!< Source stop x */ - uint32_t srcY1; /*!< Source stop y */ - uint32_t dstAddr; /*!< Destination address */ - uint32_t dstWidth; /*!< Destination width */ - uint32_t dstX0; /*!< Destination start x */ - uint32_t dstY0; /*!< Destination start y */ -} DMA2D_Picture_Cfg_Type; - -/*@} end of group DMA2D_Public_Types */ - -/** @defgroup DMA2D_Public_Constants - * @{ - */ - -/** @defgroup DMA2D_ID_TYPE - * @{ - */ -#define IS_DMA2D_ID_TYPE(type) (((type) == DMA2D0_ID) || \ - ((type) == DMA2D_ID_MAX)) - -/** @defgroup DMA2D_ENDIAN_TYPE - * @{ - */ -#define IS_DMA2D_ENDIAN_TYPE(type) (((type) == DMA2D_LITTLE_ENDIAN) || \ - ((type) == DMA2D_BIG_ENDIAN)) - -/** @defgroup DMA2D_SYNC_LOGIC_TYPE - * @{ - */ -#define IS_DMA2D_SYNC_LOGIC_TYPE(type) (((type) == DMA2D_SYNC_LOGIC_ENABLE) || \ - ((type) == DMA2D_SYNC_LOGIC_DISABLE)) - -/** @defgroup DMA2D_TRANS_WIDTH_TYPE - * @{ - */ -#define IS_DMA2D_TRANS_WIDTH_TYPE(type) (((type) == DMA2D_TRNS_WIDTH_8BITS) || \ - ((type) == DMA2D_TRNS_WIDTH_16BITS) || \ - ((type) == DMA2D_TRNS_WIDTH_32BITS)) - -/** @defgroup DMA2D_TRANS_DIR_TYPE - * @{ - */ -#define IS_DMA2D_TRANS_DIR_TYPE(type) (((type) == DMA2D_TRNS_M2M) || \ - ((type) == DMA2D_TRNS_M2P) || \ - ((type) == DMA2D_TRNS_P2M) || \ - ((type) == DMA2D_TRNS_P2P)) - -/** @defgroup DMA2D_BURST_SIZE_TYPE - * @{ - */ -#define IS_DMA2D_BURST_SIZE_TYPE(type) (((type) == DMA2D_BURST_SIZE_1) || \ - ((type) == DMA2D_BURST_SIZE_4) || \ - ((type) == DMA2D_BURST_SIZE_8) || \ - ((type) == DMA2D_BURST_SIZE_16)) - -/** @defgroup DMA2D_PERIPH_REQ_TYPE - * @{ - */ -#define IS_DMA2D_PERIPH_REQ_TYPE(type) (((type) == DMA2D_REQ_UART0_RX) || \ - ((type) == DMA2D_REQ_UART0_TX) || \ - ((type) == DMA2D_REQ_UART1_RX) || \ - ((type) == DMA2D_REQ_UART1_TX) || \ - ((type) == DMA2D_REQ_UART2_RX) || \ - ((type) == DMA2D_REQ_UART2_TX) || \ - ((type) == DMA2D_REQ_I2C0_RX) || \ - ((type) == DMA2D_REQ_I2C0_TX) || \ - ((type) == DMA2D_REQ_IR_TX) || \ - ((type) == DMA2D_REQ_GPIO) || \ - ((type) == DMA2D_REQ_SPI0_RX) || \ - ((type) == DMA2D_REQ_SPI0_TX) || \ - ((type) == DMA2D_REQ_AUDIO_RX) || \ - ((type) == DMA2D_REQ_AUDIO_TX) || \ - ((type) == DMA2D_REQ_GPADC0) || \ - ((type) == DMA2D_REQ_GPADC1) || \ - ((type) == DMA2D_REQ_USB_EP0) || \ - ((type) == DMA2D_REQ_USB_EP1) || \ - ((type) == DMA2D_REQ_USB_EP2) || \ - ((type) == DMA2D_REQ_USB_EP3) || \ - ((type) == DMA2D_REQ_USB_EP4) || \ - ((type) == DMA2D_REQ_USB_EP5) || \ - ((type) == DMA2D_REQ_USB_EP6) || \ - ((type) == DMA2D_REQ_USB_EP7) || \ - ((type) == DMA2D_REQ_UART3_RX) || \ - ((type) == DMA2D_REQ_UART3_TX) || \ - ((type) == DMA2D_REQ_SPI1_RX) || \ - ((type) == DMA2D_REQ_SPI1_TX) || \ - ((type) == DMA2D_REQ_I2C1_RX) || \ - ((type) == DMA2D_REQ_I2C1_TX) || \ - ((type) == DMA2D_REQ_I2S_TX) || \ - ((type) == DMA2D_REQ_I2S_RX) || \ - ((type) == DMA2D_REQ_DBI_TX) || \ - ((type) == DMA2D_REQ_NONE)) - -/** @defgroup DMA2D_CHAN_TYPE - * @{ - */ -#define IS_DMA2D_CHAN_TYPE(type) (((type) == DMA2D_CH0) || \ - ((type) == DMA2D_CH1) || \ - ((type) == DMA2D_CH_MAX)) - -/** @defgroup DMA2D_LLI_PP_INDEX_TYPE - * @{ - */ -#define IS_DMA2D_LLI_PP_INDEX_TYPE(type) (((type) == DMA2D_PING_INDEX) || \ - ((type) == DMA2D_PONG_INDEX)) - -/** @defgroup DMA2D_INT_TYPE - * @{ - */ -#define IS_DMA2D_INT_TYPE(type) (((type) == DMA2D_INT_TCOMPLETED) || \ - ((type) == DMA2D_INT_ALL)) - -/** @defgroup DMA2D_ROTATE_TYPE - * @{ - */ -#define IS_DMA2D_ROTATE_TYPE(type) (((type) == DMA2D_ROTATE_DEGREE_90) || \ - ((type) == DMA2D_ROTATE_DEGREE_180) || \ - ((type) == DMA2D_ROTATE_DEGREE_270)) - -/** @defgroup DMA2D_FOLD_TYPE - * @{ - */ -#define IS_DMA2D_FOLD_TYPE(type) (((type) == DMA2D_FOLD_LEFT_RIGHT) || \ - ((type) == DMA2D_FOLD_UP_DOWN)) - -/** @defgroup DMA2D_COLOR_KEY_TYPE - * @{ - */ -#define IS_DMA2D_COLOR_KEY_TYPE(type) (((type) == DMA2D_COLOR_KEY_8BIT) || \ - ((type) == DMA2D_COLOR_KEY_16BIT) || \ - ((type) == DMA2D_COLOR_KEY_24BIT) || \ - ((type) == DMA2D_COLOR_KEY_32BIT)) - -/*@} end of group DMA2D_Public_Constants */ - -/** @defgroup DMA2D_Public_Macros - * @{ - */ -#define DMA2D_PINC_ENABLE 1 -#define DMA2D_PINC_DISABLE 0 -#define DMA2D_MINC_ENABLE 1 -#define DMA2D_MINC_DISABLE 0 - -/*@} end of group DMA2D_Public_Macros */ - -/** @defgroup DMA2D_Public_Functions - * @{ - */ - -/** - * @brief DMA2D Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_INT0_IRQHandler(void); -void DMA2D_INT1_IRQHandler(void); -#endif -void DMA2D_Enable(DMA2D_ID_Type dmaId); -void DMA2D_Disable(DMA2D_ID_Type dmaId); -void DMA2D_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Cfg_Type *cfg); -void DMA2D_Channel_Init(DMA2D_ID_Type dmaId, DMA2D_Channel_Cfg_Type *chCfg); -void DMA2D_DeInit(DMA2D_ID_Type dmaId); -void DMA2D_Channel_Update_SrcMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -void DMA2D_Channel_Update_DstMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len); -uint32_t DMA2D_Channel_TranferSize(DMA2D_ID_Type dmaId, uint8_t ch); -BL_Sts_Type DMA2D_Channel_Is_Busy(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_Channel_Enable(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_Channel_Disable(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_LLI_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Cfg_Type *lliCfg); -void DMA2D_LLI_Update(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t LLI); -uint32_t DMA2D_LLI_Get_Counter(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_IntMask(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_INT_Type intType, BL_Mask_Type intMask); -void DMA2D_LLI_PpBuf_Start_New_Transmit(DMA2D_LLI_PP_Buf *dmaPpBuf); -DMA2D_LLI_Ctrl_Type *DMA2D_LLI_PpBuf_Remove_Completed_List(DMA2D_LLI_PP_Buf *dmaPpBuf); -void DMA2D_LLI_PpBuf_Append(DMA2D_LLI_PP_Buf *dmaPpBuf, DMA2D_LLI_Ctrl_Type *dmaLliList); -void DMA2D_LLI_PpBuf_Destroy(DMA2D_LLI_PP_Buf *dmaPpBuf); -void DMA2D_Int_Callback_Install(DMA2D_ID_Type dmaId, DMA2D_Chan_Type dmaChan, DMA2D_INT_Type intType, intCallback_Type *cbFun); -void DMA2D_LLI_PpStruct_Start(DMA2D_LLI_PP_Struct *dmaPpStruct); -void DMA2D_LLI_PpStruct_Stop(DMA2D_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA2D_LLI_PpStruct_Init(DMA2D_LLI_PP_Struct *dmaPpStruct); -BL_Err_Type DMA2D_LLI_PpStruct_Set_Transfer_Len(DMA2D_LLI_PP_Struct *dmaPpStruct, - uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len); -void DMA2D_Picture_Translate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg); -void DMA2D_Picture_Rotate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Rotate_Type rotate); -void DMA2D_Picture_Fold_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Fold_Type fold); -void DMA2D_Picture_Fill_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg); -void DMA2D_Picture_Transfer_Start(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Ctrl_Type *lliCfg); -void DMA2D_Color_Key_Set(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Color_Key_Type keyType, uint32_t keyValue); -void DMA2D_Color_Key_Enable(DMA2D_ID_Type dmaId, uint8_t ch); -void DMA2D_Color_Key_Disable(DMA2D_ID_Type dmaId, uint8_t ch); -/*@} end of group DMA2D_Public_Functions */ - -/*@} end of group DMA2D */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DMA2D_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsi.h deleted file mode 100644 index 7e8ecf2a6c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsi.h +++ /dev/null @@ -1,382 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsi.h - * @version V1.0 - * @date 2021-04-22 - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSI_H__ -#define __BL808_DSI_H__ - -#include "dsi_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSI - * @{ - */ - -/** @defgroup DSI_Public_Types - * @{ - */ - -/** - * @brief DSI port type definition - */ -typedef enum { - DSI0_ID, /*!< DSI0 port define */ - DSI_ID_MAX, /*!< DSI max ID define */ -} DSI_ID_Type; - -/** - * @brief DSI interrupt type definition - */ -typedef enum { - DSI_INT_ESCAPE_TX_END = 0x01, /*!< DSI escape tx end interrupt */ - DSI_INT_LPDT_RX_END = 0x02, /*!< DSI lpdt rx end interrupt */ - DSI_INT_ULPS_RX_END = 0x04, /*!< DSI ulps rx end interrupt */ - DSI_INT_TRIGGER0_RX_END = 0x08, /*!< DSI trigger0 rx end interrupt */ - DSI_INT_TRIGGER1_RX_END = 0x10, /*!< DSI trigger1 rx end interrupt */ - DSI_INT_TRIGGER2_RX_END = 0x20, /*!< DSI trigger2 rx end interrupt */ - DSI_INT_TRIGGER3_RX_END = 0x40, /*!< DSI trigger3 rx end interrupt */ - DSI_INT_TX_FIFO_READY = 0x80, /*!< DSI tx fifo ready interrupt */ - DSI_INT_RX_FIFO_READY = 0x100, /*!< DSI rx fifo ready interrupt */ - DSI_INT_DATA_OVERRUN_ERR = 0x200, /*!< DSI data overrun error interrupt */ - DSI_INT_DATA_UNDERRUN_ERR = 0x400, /*!< DSI data underrun error interrupt */ - DSI_INT_PIXEL_COUNT_SMALL_ERR = 0x800, /*!< DSI pixel count too small error interrupt */ - DSI_INT_PIXEL_COUNT_LARGE_ERR = 0x1000, /*!< DSI pixel count too large error interrupt */ - DSI_INT_FIFO_ERROR = 0x2000, /*!< DSI fifo error interrupt */ - DSI_INT_ALL = 0x3FFF, /*!< All interrupt */ - DSI_INT_COUNT = 0x0E, /*!< Interrupt count */ -} DSI_INT_Type; - -/** - * @brief DSI fifo error type definition - */ -typedef enum { - DSI_FIFO_ERR_TX_OVERFLOW = 0x01, /*!< DSI tx fifo overflow */ - DSI_FIFO_ERR_TX_UNDERFLOW = 0x02, /*!< DSI tx fifo underflow */ - DSI_FIFO_ERR_RX_OVERFLOW = 0x04, /*!< DSI rx fifo overflow */ - DSI_FIFO_ERR_RX_UNDERFLOW = 0x08, /*!< DSI rx fifo underflow */ -} DSI_FIFO_Error_Type; - -/** - * @brief DSI lane type definition - */ -typedef enum { - DSI_LANE_DATA0 = 0x01, /*!< Data0 */ - DSI_LANE_DATA1 = 0x02, /*!< Data1 */ - DSI_LANE_DATA2 = 0x04, /*!< Data2 */ - DSI_LANE_DATA3 = 0x08, /*!< Data3 */ - DSI_LANE_CLOCK = 0x010, /*!< Clcok */ -} DSI_Lane_Type; - -/** - * @brief DSI data type definition - */ -typedef enum { - DSI_DATA_YUV422 = 0x2c, /*!< YUV422, 8-bit */ - DSI_DATA_RGB565 = 0x0e, /*!< RGB565 */ - DSI_DATA_RGB666 = 0x2e, /*!< RGB666, lossely packed */ - DSI_DATA_RGB888 = 0x3e, /*!< RGB888 */ -} DSI_Data_Type; - -/** - * @brief DSI lane number type definition - */ -typedef enum { - DSI_LANE_NUMBER_1, /*!< 1-lane TX */ - DSI_LANE_NUMBER_2, /*!< 2-lane TX */ - DSI_LANE_NUMBER_4, /*!< 4-lane TX */ -} DSI_Lane_Number_Type; - -/** - * @brief DSI lane order type definition - */ -typedef enum { - DSI_LANE_ORDER_3210, /*!< Lane 3, 2, 1, 0 */ - DSI_LANE_ORDER_2130, /*!< Lane 2, 1, 3, 0 */ - DSI_LANE_ORDER_1320, /*!< Lane 1, 3, 2, 0 */ - DSI_LANE_ORDER_3120, /*!< Lane 3, 1, 2, 0 */ -} DSI_Lane_Order_Type; - -/** - * @brief DSI lane state type definition - */ -typedef enum { - DSI_LANE_STAT_NORMAL = 0x00, /*!< Status normal */ - DSI_LANE_STAT_STOP = 0x01, /*!< Status stop */ - DSI_LANE_STAT_BRIDGE = 0x02, /*!< Status bridge changing */ - DSI_LANE_STAT_ULP = 0x04, /*!< Status ultra low power */ - DSI_LANE_STAT_HS=0x08, /*!< Status high speed */ -} DSI_Lane_State_Type; - -/** - * @brief DSI clock lane option type definition - */ -typedef enum { - DSI_CLOCK_LANE_OPT_ULP_ENTER = 0x01, /*!< Clock lane low power enter */ - DSI_CLOCK_LANE_OPT_ULP_EXIT = 0x02, /*!< Clock lane low power exit */ - DSI_CLOCK_LANE_OPT_HS_REQ = 0x04, /*!< Clock lane hs request */ - DSI_CLOCK_LANE_OPT_HS_EXIT = 0x08, /*!< Clock lane hs exit */ -} DSI_Clock_Lane_Opt_Type; - -/** - * @brief Escape mode type definition - */ -typedef enum { - DSI_ESCAPSE_TYPE_LPDT, /*!< Escape type:LPDT */ - DSI_ESCAPSE_TYPE_TRIGGER, /*!< Escape type:TRIGGER */ - DSI_ESCAPSE_TYPE_ULPS, /*!< Escape type:UPLS */ -} DSI_Escape_Type; - -/** - * @brief HS sync mode type definition - */ -typedef enum { - DSI_HS_SYNC_EVENT_MODE, /*!< HS sync event mode */ - DSI_HS_SYNC_PULSE_MODE, /*!< HS sync pulse mode */ -} DSI_HS_Sync_Type; - -/** - * @brief DSI configuration strcut definition - */ -typedef struct -{ - uint8_t virtualChan; /*!< DSI virtual channels */ - DSI_Lane_Number_Type laneNum; /*!< DSI lane numbers */ - DSI_Lane_Order_Type laneOrder; /*!< DSI lane order */ - DSI_Data_Type dataType; /*!< DSI data type */ - DSI_HS_Sync_Type syncType; /*!< DSI HS sync mode select */ - uint8_t vsa; /*!< HS vertical sync active width */ - uint8_t vfp; /*!< HS vertical front porch width */ -} DSI_CFG_Type; - -/** - * @brief DSI configuration strcut definition - */ -typedef struct -{ - uint8_t virtualChan; /*!< DSI LPDT msg virtual channels */ - uint8_t dataType; /*!< DSI LPDT msg data type */ - uint8_t flag; /*!< DSI LPDT msg flag */ - uint16_t tx_len; /*!< DSI LPDT msg len */ - const uint8_t *tx_buf; /*!< DSI LPDT msg buffer */ - uint16_t rx_len; /*!< DSI LPDT rx len */ - uint8_t *rx_buf; /*!< DSI LPDT rx buffer */ -} DSI_LPDT_MSG_Type; - -/** - * @brief DSI DPHY configuration strcut definition - */ -typedef struct -{ - uint8_t time_clk_zero; /*!< Clock lane zero time */ - uint8_t time_clk_trail; /*!< Clock lane trail time */ - uint8_t time_clk_exit; /*!< Clock lane exit time */ - uint8_t time_data_prepare; /*!< Data lane prepare time*/ - uint8_t time_data_zero; /*!< Data lane zero time*/ - uint8_t time_data_trail; /*!< Data lane trail time */ - uint8_t time_data_exit; /*!< Data lane exit time */ - uint8_t time_lpx; /*!< Low power time */ - uint8_t time_req_ready; /*!< HS request time */ - uint8_t time_ta_get; /*!< Bus turn around get time */ - uint8_t time_ta_go; /*!< Bus turn around go time */ - uint32_t time_wakeup; /*!< Low power wake up time */ -} DSI_DPhy_CFG_Type; - -/** - * @brief DSI FIFO configuration structure type definition - */ -typedef struct -{ - uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */ - uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ - BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ -} DSI_FifoCfg_Type; - -/*@} end of group DSI_Public_Types */ - -/** @defgroup DSI_Public_Constants - * @{ - */ - -/** @defgroup DSI_ID_TYPE - * @{ - */ -#define IS_DSI_ID_TYPE(type) (((type) == DSI0_ID) || \ - ((type) == DSI_ID_MAX)) - -/** @defgroup DSI_INT_TYPE - * @{ - */ -#define IS_DSI_INT_TYPE(type) (((type) == DSI_INT_ESCAPE_TX_END) || \ - ((type) == DSI_INT_LPDT_RX_END) || \ - ((type) == DSI_INT_ULPS_RX_END) || \ - ((type) == DSI_INT_TRIGGER0_RX_END) || \ - ((type) == DSI_INT_TRIGGER1_RX_END) || \ - ((type) == DSI_INT_TRIGGER2_RX_END) || \ - ((type) == DSI_INT_TRIGGER3_RX_END) || \ - ((type) == DSI_INT_TX_FIFO_READY) || \ - ((type) == DSI_INT_RX_FIFO_READY) || \ - ((type) == DSI_INT_DATA_OVERRUN_ERR) || \ - ((type) == DSI_INT_DATA_UNDERRUN_ERR) || \ - ((type) == DSI_INT_PIXEL_COUNT_SMALL_ERR) || \ - ((type) == DSI_INT_PIXEL_COUNT_LARGE_ERR) || \ - ((type) == DSI_INT_FIFO_ERROR) || \ - ((type) == DSI_INT_ALL)) - -/** @defgroup DSI_FIFO_ERROR_TYPE - * @{ - */ -#define IS_DSI_FIFO_ERROR_TYPE(type) (((type) == DSI_FIFO_ERR_TX_OVERFLOW) || \ - ((type) == DSI_FIFO_ERR_TX_UNDERFLOW) || \ - ((type) == DSI_FIFO_ERR_RX_OVERFLOW) || \ - ((type) == DSI_FIFO_ERR_RX_UNDERFLOW)) - -/** @defgroup DSI_LANE_TYPE - * @{ - */ -#define IS_DSI_LANE_TYPE(type) (((type) == DSI_LANE_DATA0) || \ - ((type) == DSI_LANE_DATA1) || \ - ((type) == DSI_LANE_DATA2) || \ - ((type) == DSI_LANE_DATA3) || \ - ((type) == DSI_LANE_CLOCK)) - -/** @defgroup DSI_DATA_TYPE - * @{ - */ -#define IS_DSI_DATA_TYPE(type) (((type) == DSI_DATA_YUV422) || \ - ((type) == DSI_DATA_RGB565) || \ - ((type) == DSI_DATA_RGB666) || \ - ((type) == DSI_DATA_RGB888)) - -/** @defgroup DSI_LANE_NUMBER_TYPE - * @{ - */ -#define IS_DSI_LANE_NUMBER_TYPE(type) (((type) == DSI_LANE_NUMBER_1) || \ - ((type) == DSI_LANE_NUMBER_2) || \ - ((type) == DSI_LANE_NUMBER_4)) - -/** @defgroup DSI_LANE_ORDER_TYPE - * @{ - */ -#define IS_DSI_LANE_ORDER_TYPE(type) (((type) == DSI_LANE_ORDER_3210) || \ - ((type) == DSI_LANE_ORDER_2130) || \ - ((type) == DSI_LANE_ORDER_1320) || \ - ((type) == DSI_LANE_ORDER_3120)) - -/** @defgroup DSI_LANE_STATE_TYPE - * @{ - */ -#define IS_DSI_LANE_STATE_TYPE(type) (((type) == DSI_LANE_STAT_NORMAL) || \ - ((type) == DSI_LANE_STAT_STOP) || \ - ((type) == DSI_LANE_STAT_BRIDGE) || \ - ((type) == DSI_LANE_STAT_ULP) || \ - ((type) == DSI_LANE_STAT_HS)) - -/** @defgroup DSI_CLOCK_LANE_OPT_TYPE - * @{ - */ -#define IS_DSI_CLOCK_LANE_OPT_TYPE(type) (((type) == DSI_CLOCK_LANE_OPT_ULP_ENTER) || \ - ((type) == DSI_CLOCK_LANE_OPT_ULP_EXIT) || \ - ((type) == DSI_CLOCK_LANE_OPT_HS_REQ) || \ - ((type) == DSI_CLOCK_LANE_OPT_HS_EXIT)) - -/** @defgroup DSI_ESCAPE_TYPE - * @{ - */ -#define IS_DSI_ESCAPE_TYPE(type) (((type) == DSI_ESCAPSE_TYPE_LPDT) || \ - ((type) == DSI_ESCAPSE_TYPE_TRIGGER) || \ - ((type) == DSI_ESCAPSE_TYPE_ULPS)) - -/** @defgroup DSI_HS_SYNC_TYPE - * @{ - */ -#define IS_DSI_HS_SYNC_TYPE(type) (((type) == DSI_HS_SYNC_EVENT_MODE) || \ - ((type) == DSI_HS_SYNC_PULSE_MODE)) - -/*@} end of group DSI_Public_Constants */ - -/** @defgroup DSI_Public_Macros - * @{ - */ -#define DSI_TX_FIFO_SIZE 4 -#define DSI_RX_FIFO_SIZE 4 -/*@} end of group DSI_Public_Macros */ - -/** @defgroup DSI_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void DSI_IRQHandler(void); -#endif -void DSI_Init(DSI_ID_Type disId, DSI_CFG_Type *cfg); -void DSI_Deinit(DSI_ID_Type disId); -void DSI_Enable(DSI_ID_Type disId); -void DSI_Disable(DSI_ID_Type disId); -void DSI_IntMask(DSI_ID_Type dsiId, DSI_INT_Type intType, BL_Mask_Type intMask); -void DSI_IntClear(DSI_ID_Type dsiId, DSI_INT_Type intType); -void DSI_IntEnable(DSI_ID_Type dsiId, DSI_INT_Type intType); -DSI_INT_Type DSI_IntGet(DSI_ID_Type dsiId); -void DSI_Set_Line_Buffer_Threshold(DSI_ID_Type dsiId, uint32_t frameWidth, uint32_t dvpTsrcClock, uint32_t dsiClock, \ - DSI_Data_Type dataType, DSI_Lane_Number_Type laneNumber); -void DSI_Set_VSA_VFP(DSI_ID_Type dsiId, uint8_t vsa, uint8_t vfp); -void DSI_PHY_Reset(DSI_ID_Type dsiId); -void DSI_PHY_Config(DSI_ID_Type dsiId, DSI_DPhy_CFG_Type *phyCfg); -void DSI_PHY_Reinit_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Enable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Disable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Data_Lane0_TurnAround(DSI_ID_Type dsiId); -void DSI_PHY_Stop_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes); -void DSI_PHY_Get_Lanes_State(DSI_ID_Type dsiId, DSI_Lane_Type lane, DSI_Lane_State_Type *state); -void DSI_PHY_Set_Clock_Lane(DSI_ID_Type dsiId, DSI_Clock_Lane_Opt_Type opt); -void DSI_PHY_HS_Mode_Start(DSI_ID_Type dsiId); -void DSI_PHY_HS_Mode_Stop(DSI_ID_Type dsiId); -BL_Err_Type DSI_FifoConfig(DSI_ID_Type dsiId, DSI_FifoCfg_Type *fifoCfg); -BL_Err_Type DSI_LPDT_Send_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg); -BL_Err_Type DSI_LPDT_Send_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg); -BL_Err_Type DSI_LPDT_Recv_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg); -BL_Err_Type DSI_Send_Trigger_Command(DSI_ID_Type dsiId, uint8_t cmd); -BL_Err_Type DSI_Send_ULPS_Command(DSI_ID_Type dsiId); -BL_Err_Type DSI_Exit_ULPS(DSI_ID_Type dsiId); - -/*@} end of group DSI_Public_Functions */ - -/*@} end of group DSI */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSI_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2.h deleted file mode 100644 index 3c3a3b43c8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2.h +++ /dev/null @@ -1,689 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_H__ -#define __BL808_DSP2_H__ - -#include -#include "bl808_common.h" -#include "dsp2_tg_reg.h" -#include "dsp2_front_reg.h" -#include "dsp2_back_reg.h" -#include "dsp2_blback_reg.h" -#include "dsp2_middle_reg.h" -#include "dsp2_middle3_reg.h" -#include "dsp2_middle4_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2 - * @{ - */ - -/** @defgroup DSP2_Public_Types - * @{ - */ - -#define DSP2_EE_LUMA_WEIGHT_NUM (32) -#define DSP2_AWB2_STA_Y_NUM (5) -#define DSP2_AWB2_STA_C_NUM (8) -#define CCM_COEF_NUM (9) -#define GAMMA_COEF_NUM (256) - -/** - * @brief Bayer pattern - */ -typedef enum { - BAYER_PATTERN_RG = 0, - BAYER_PATTERN_GR, - BAYER_PATTERN_BG, - BAYER_PATTERN_GB, -} BAYER_PATTERN_E; - -/** - * @brief LSC coefficient - */ -typedef enum { - LSC_COEF_A = 0, - LSC_COEF_B = 1, - LSC_COEF_C = 2, - LSC_COEF_D = 3, - LSC_COEF_E = 4, - LSC_COEF_G = 5, - LSC_COEF_NUM = 6, -} DSP2_LSC_COEF_E; - -/** - * @brief DSP2 sync mode type definition - */ -typedef enum { - DSP2_SYNC_MODE_INPUT = 0, - DSP2_SYNC_MODE_OUTPUT, - DSP2_SYNC_MODE_OUTPUT_INPUT, - DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE, -} DSP2_SYNC_MODE_TYPE; - -/** - * @brief Color correction matrix coefficient - */ -typedef enum { - DSP2_CCM_11 = 0, - DSP2_CCM_12 = 1, - DSP2_CCM_13 = 2, - DSP2_CCM_21 = 3, - DSP2_CCM_22 = 4, - DSP2_CCM_23 = 5, - DSP2_CCM_31 = 6, - DSP2_CCM_32 = 7, - DSP2_CCM_33 = 8, -} DSP2_CCM_COEF_TYPE_E; - -/** - * @brief YUV conversion mode - */ -typedef enum { - DSP2_YUV_CONV_FULL_SCALE = 0, - DSP2_YUV_CONV_BT601, -} DSP2_YUV_CONV_TYPE; - -/** - * @brief Defect correction enhance state - */ -typedef enum { - DSP2_DPC_Enhance1 = 0, - DSP2_DPC_Enhance2, - DSP2_DPC_Enhance3, - DSP2_DPC_Enhance_Num, -} DSP2_DPC_ENHANCE_TYPE; - -/** - * @brief Defect correction threadhold - */ -typedef enum { - DSP2_DPC_th1 = 0, - DSP2_DPC_th2, - DSP2_DPC_th3, - DSP2_DPC_th4, - DSP2_DPC_th5, - DSP2_DPC_th_Num, -} DSP2_DPC_THRESHOLD_TYPE; - -/** - * @brief AE grid data type - */ -typedef enum { - AE_GRID_DATA_RGB = 0, - AE_GRID_DATA_Y = 1, -} AE_GRID_DATA_TYPE_E; - -/** - * @brief AWB grid data type - */ -typedef enum { - AWB_GRID_DATA_RG = 0, - AWB_GRID_DATA_B = 1, -} AWB_GRID_DATA_TYPE_E; - -/** - * @brief Image size - */ -typedef struct -{ - uint32_t width; - uint32_t height; -} BL_Img_Size_T; - -/** - * @brief RGB sum - */ -typedef struct blRGB_SUM_S { - uint32_t r_sum; - uint32_t g_sum; - uint32_t b_sum; -} RGB_SUM_S; - -/** - * @brief R,Gr,Gb,B black level - */ -typedef struct blDSP2_CLAMP_S { - int clamp_r; - int clamp_gr; - int clamp_gb; - int clamp_b; -} DSP2_CLAMP_S; - -/** - * @brief Color correction matrix coefficient group - */ -typedef struct blDSP2_CCM_COEF_GROUP_S { - int ccm_coef[CCM_COEF_NUM]; -} DSP2_CCM_COEF_S; - -/** - * @brief Gamma curve type - */ -typedef struct blDSP2_GAMMA_COEF_GROUP_S { - uint16_t curve_coef[GAMMA_COEF_NUM]; -} DSP2_Gamma_Curve_Type; - -/** - * @brief Saturation - */ -typedef struct blDSP2_SATURATION_S { - uint32_t saturation_cb; - uint32_t saturation_cr; -} DSP2_SATURATION_S; - -/** - * @brief Defect correction enhance state group - */ -typedef struct -{ - BL_Fun_Type data[DSP2_DPC_Enhance_Num]; -} DSP2_DPC_ENHANCE_GROUP_TYPE; - -/** - * @brief Defect correction threadhold group - */ -typedef struct -{ - int data[DSP2_DPC_th_Num]; -} DSP2_DPC_THRESHOLD_GROUP_TYPE; - -/* - Lens Shading Coef - Acoef range: -4194304-4194303 - Bcoef range: -4096-4095 - Ccoef range: 0-255 - Dcoef range: -4194304-4194303 - Ecoef range: -4096-4095 - Gcoef range: -4194304-4194303 -*/ - -/** - * @brief BNR threshold type - */ -typedef struct -{ - uint16_t th_base_r; /*!< r/w, shadow, 10'b, range: 0 ~ (2 ^ TH_BW - 1) */ - uint16_t th_base_g; /*!< r/w, shadow, 10'b, range: 0 ~ (2 ^ TH_BW - 1) */ - uint16_t th_base_b; /*!< r/w, shadow, 10'b, range: 0 ~ (2 ^ TH_BW - 1) */ - uint16_t th_slope_r; /*!< r/w, shadow, 8'b, = TH_SLOPE_PRECISION, range: 0 ~ (2 ^ TH_SLOPE_PRECISION - 1) */ - uint16_t th_slope_g; /*!< r/w, shadow, 8'b, = TH_SLOPE_PRECISION, range: 0 ~ (2 ^ TH_SLOPE_PRECISION - 1) */ - uint16_t th_slope_b; /*!< r/w, shadow, 8'b, = TH_SLOPE_PRECISION, range: 0 ~ (2 ^ TH_SLOPE_PRECISION - 1) */ - uint16_t slope_gain; /*!< r/w, shadow, 6'b, = 2 + SLOPE_GAIN_PRECISION, 2.4 fixed-point, range: 0 ~ (2 ^ 6 - 1) */ -} DSP2_BNR_THRESHOLD_TYPE; - -/** - * @brief BNR fallback type - */ -typedef struct -{ - uint16_t fb_lpf_weight; /*!< r/w, shadow, 5'b, = 1 + LPF_WEIGHT_PRECISION, range: 0 ~ (2 ^ LPF_WEIGHT_PRECISION) */ - uint16_t fb_level; /*!< r/w, shadow, 3'b, = FB_LEVEL_BW, range: 0 ~ (2 ^ FB_LEVEL_BW - 1) */ -} DSP2_BNR_FALLBACK_TYPE; - -/** - * @brief LSC coefficient type - */ -typedef struct -{ - int coef[LSC_COEF_NUM]; -} DSP2_LSC_COEF_TYPE; - -/** - * @brief LSC coefficient group - */ -typedef struct blDSP2_LSC_COEF_S { - DSP2_LSC_COEF_TYPE lsc_coef_r; - DSP2_LSC_COEF_TYPE lsc_coef_g; - DSP2_LSC_COEF_TYPE lsc_coef_b; -} DSP2_LSC_COEF_S; - -/** - * @brief LSC max - */ -typedef struct blDSP2_LSC_MAX_S { - int max_r; - int max_g; - int max_b; -} DSP2_LSC_MAX_S; - -/** - * @brief TG configuration - */ -typedef struct -{ - DSP2_SYNC_MODE_TYPE sync_mode_value; - uint32_t DSP2_clk; - uint32_t pix_clk; - uint16_t fps; - uint16_t total_width; - uint16_t total_height; - uint16_t active_width; - uint16_t active_height; - uint16_t out_width; - uint16_t out_height; -} DSP2_TG_Cfg_Type; - -/** - * @brief AE status configuration - */ -typedef struct _dsp2_ae_stats_conf { - uint16_t roi_start_x; - uint16_t roi_start_y; - uint16_t roi_width; - uint16_t roi_height; - uint16_t img_width; - uint16_t img_height; - uint8_t grid_width; - uint8_t grid_height; - uint8_t grid_num_x; - uint8_t grid_num_y; -} dsp2_ae_stats_conf_t; - -/** - * @brief AE sum - */ -typedef struct _dsp2_ae_sum { - uint32_t r_sum : 8; - uint32_t g_sum : 8; - uint32_t b_sum : 8; - uint32_t reserved_24_31 : 8; - uint32_t y_sum : 8; - uint32_t reserved_8_31 : 24; -} dsp2_ae_sum_t; - -/** - * @brief AWB status configuration - */ -typedef struct _dsp2_awb_stats_conf { - uint16_t roi_start_x; - uint16_t roi_start_y; - uint16_t roi_width; - uint16_t roi_height; - uint16_t img_width; - uint16_t img_height; - uint8_t grid_width; - uint8_t grid_height; - uint8_t grid_num_x; - uint8_t grid_num_y; - uint16_t r_max_thr; - uint16_t r_min_thr; - uint16_t g_max_thr; - uint16_t g_min_thr; - uint16_t b_max_thr; - uint16_t b_min_thr; -} dsp2_awb_stats_conf_t; - -/** - * @brief AWB2 status configuration - */ -typedef struct _dsp2_awb2_stats_conf { - uint16_t stat_x_min; /*!< r/w, shadow, 11'b, range: 0 ~ (width - 1) */ - uint16_t stat_x_max; /*!< r/w, shadow, 11'b, range: 0 ~ (width - 1) */ - uint16_t stat_y_min; /*!< r/w, shadow, 11'b, range: 0 ~ (height - 1) */ - uint16_t stat_y_max; /*!< r/w, shadow, 11'b, range: 0 ~ (height - 1) */ - uint32_t stat_pixel_num; /*!< r/w, shadow, 21'b, = (stat_x_max - stat_x_min + 1) * (stat_y_max - stat_y_min + 1) */ - uint16_t stat_r_gain; /*!< r/w, shadow, 16'b, = 4 + GAIN_PRECISION, 4.12 fixed-point, range: 0 ~ (2 ^ 16 - 1) */ - uint16_t stat_g_gain; /*!< r/w, shadow, 16'b, = 4 + GAIN_PRECISION, 4.12 fixed-point, range: 0 ~ (2 ^ 16 - 1) */ - uint16_t stat_b_gain; /*!< r/w, shadow, 16'b, = 4 + GAIN_PRECISION, 4.12 fixed-point, range: 0 ~ (2 ^ 16 - 1) */ - uint16_t stat_u_gain; /*!< r/w, shadow, 10'b, = 2 + C_GAIN_PRECISION, 2.8 fixed-point, range: 0 ~ (2 ^ 10 - 1) */ - uint16_t stat_v_gain; /*!< r/w, shadow, 10'b, = 2 + C_GAIN_PRECISION, 2.8 fixed-point, range: 0 ~ (2 ^ 10 - 1) */ - uint16_t reserved0; /*!< reserved */ - uint8_t y_th[DSP2_AWB2_STA_Y_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, range: 0 ~ (2 ^ 8 - 1) */ - uint8_t y_weight[DSP2_AWB2_STA_Y_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, range: 0 ~ (2 ^ 8 - 1) */ - uint16_t reserved1; /*!< reserved */ - int16_t y_slope[DSP2_AWB2_STA_Y_NUM]; /*!< r/w, shadow, 9'b, = 7 + SLOPE_PRECISION, signed 2's complement, range: -256 ~ +255 */ - uint16_t reserved2; /*!< reserved */ - int8_t u[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, signed 2's complement, range: -128 ~ +127 */ - int8_t v[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 8'b, = STAT_PIXEL_BW, signed 2's complement, range: -128 ~ +127 */ - uint8_t c_th[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 6'b, = STAT_PIXEL_BW - 2, range: 0 ~ (2 ^ 6 - 1) */ - uint8_t c_slope[DSP2_AWB2_STA_C_NUM]; /*!< r/w, shadow, 8'b, = 6 + SLOPE_PRECISION, range: 0 ~ (2 ^ 8 - 1) */ -} dsp2_awb2_stats_conf_t; - -/** - * @brief AWB2 sum - */ -typedef struct _dsp2_awb2_sum { - uint32_t r_avg; /*!< r, ping-pong, 12'b, = PIXEL_BW */ - uint32_t g_avg; /*!< r, ping-pong, 12'b, = PIXEL_BW */ - uint32_t b_avg; /*!< r, ping-pong, 12'b, = PIXEL_BW */ - uint64_t white_r_sum; /*!< r, ping-pong, 41'b, = max. width * height in bit + WEIGHT_PRECISION + PIXEL_BW */ - uint64_t white_g_sum; /*!< r, ping-pong, 41'b, = max. width * height in bit + WEIGHT_PRECISION + PIXEL_BW */ - uint64_t white_b_sum; /*!< r, ping-pong, 41'b, = max. width * height in bit + WEIGHT_PRECISION + PIXEL_BW */ - uint32_t white_ratio; /*!< r, ping-pong, 15'b, = 1 + RATIO_PRECISION, 1.14 fixed-point */ -} dsp2_awb2_sum_t; - -/** - * @brief AWB sum - */ -typedef struct _dsp2_awb_sum { - uint32_t r_sum : 12; - uint32_t reserved_12_15 : 4; - uint32_t g_sum : 12; - uint32_t reserved_28_31 : 4; - uint32_t b_sum : 12; - uint32_t reserved_12_31 : 20; -} dsp2_awb_sum_t; - -/** - * @brief EE threshold type - */ -typedef struct -{ - uint8_t dirShpnessThresh; - uint8_t noDirShpnessThresh; - uint8_t flatThresh; - uint16_t textureThresh; - uint16_t edgeThresh; -} DSP2_EE_Thresh_Type; - -/** - * @brief EE str type - */ -typedef struct -{ - uint8_t posEdgeOvrshtStr; - uint8_t negEdgeOvrshtStr; - uint8_t posEdgeStr; - uint8_t negEdgeStr; - uint8_t nrStr; -} DSP2_EE_Str_Type; - -/** - * @brief EE luma weight type - */ -typedef struct -{ - uint16_t lumaWgtTbl[DSP2_EE_LUMA_WEIGHT_NUM]; -} DSP2_EE_Luma_Weight_Type; - -/** - * @brief Chroma suppress type - */ -typedef struct -{ - uint16_t gain; - uint8_t weight; - uint8_t gain_thresh; -} DSP2_Chroma_Suppress_Type; - -/** - * @brief RGB gain type - */ -typedef struct -{ - uint16_t r_gain; - uint16_t g_gain; - uint16_t b_gain; -} DSP2_RGB_Gain_Type; - -/** - * @brief RB gain type - */ -typedef struct -{ - uint16_t r_gain; - uint16_t b_gain; -} DSP2_RB_Gain_Type; - -/*@} end of group DSP2_Public_Types */ - -/** @defgroup DSP2_Public_Constants - * @{ - */ - -/** @defgroup DSP2_SYNC_MODE_TYPE - * @{ - */ -#define IS_DSP2_SYNC_MODE_TYPE(type) (((type) == DSP2_SYNC_MODE_INPUT) || \ - ((type) == DSP2_SYNC_MODE_OUTPUT) || \ - ((type) == DSP2_SYNC_MODE_OUTPUT_INPUT) || \ - ((type) == DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE)) - -/** @defgroup DSP2_CCM_COEF_TYPE_E - * @{ - */ -#define IS_DSP2_CCM_COEF_TYPE_E(type) (((type) == DSP2_CCM_11) || \ - ((type) == DSP2_CCM_12) || \ - ((type) == DSP2_CCM_13) || \ - ((type) == DSP2_CCM_21) || \ - ((type) == DSP2_CCM_22) || \ - ((type) == DSP2_CCM_23) || \ - ((type) == DSP2_CCM_31) || \ - ((type) == DSP2_CCM_32) || \ - ((type) == DSP2_CCM_33)) - -/** @defgroup DSP2_YUV_CONV_TYPE - * @{ - */ -#define IS_DSP2_YUV_CONV_TYPE(type) (((type) == DSP2_YUV_CONV_FULL_SCALE) || \ - ((type) == DSP2_YUV_CONV_BT601)) - -/** @defgroup DSP2_DPC_ENHANCE_TYPE - * @{ - */ -#define IS_DSP2_DPC_ENHANCE_TYPE(type) (((type) == DSP2_DPC_Enhance1) || \ - ((type) == DSP2_DPC_Enhance2) || \ - ((type) == DSP2_DPC_Enhance3) || \ - ((type) == DSP2_DPC_Enhance_Num)) - -/** @defgroup DSP2_DPC_THRESHOLD_TYPE - * @{ - */ -#define IS_DSP2_DPC_THRESHOLD_TYPE(type) (((type) == DSP2_DPC_th1) || \ - ((type) == DSP2_DPC_th2) || \ - ((type) == DSP2_DPC_th3) || \ - ((type) == DSP2_DPC_th4) || \ - ((type) == DSP2_DPC_th5) || \ - ((type) == DSP2_DPC_th_Num)) - -/** @defgroup AE_GRID_DATA_TYPE_E - * @{ - */ -#define IS_AE_GRID_DATA_TYPE_E(type) (((type) == AE_GRID_DATA_RGB) || \ - ((type) == AE_GRID_DATA_Y)) - -/** @defgroup AWB_GRID_DATA_TYPE_E - * @{ - */ -#define IS_AWB_GRID_DATA_TYPE_E(type) (((type) == AWB_GRID_DATA_RG) || \ - ((type) == AWB_GRID_DATA_B)) - -/*@} end of group DSP2_Public_Constants */ - -/** @defgroup DSP2_Public_Macros - * @{ - */ -#define CHECK_PARAM_RANGE(value, min, max) \ - CHECK_PARAM((value) >= min && (value) <= max) -#define CHECK_PARAM_MAX(value, max) \ - CHECK_PARAM((value) <= max) -#define CHECK_PARAM_MIN(value, min) \ - CHECK_PARAM((value) >= min) - -/*@} end of group DSP2_Public_Macros */ - -/** @defgroup DSP2_Public_Functions - * @{ - */ -void DSP2_Init(void); - -void DSP2_Set_TG_Cfg(const DSP2_TG_Cfg_Type *cfg); -void DSP2_Set_Bayer_Pattern(const BAYER_PATTERN_E *pattern); - -void DSP2_Set_AE_State(BL_Fun_Type state); -void DSP2_Set_AE_Stats_Conf(const dsp2_ae_stats_conf_t *ae_stats_conf); -void DSP2_Get_AE_Stats_Conf(dsp2_ae_stats_conf_t *ae_stats_conf); -void DSP2_Get_AE_Sum(int grid_idx, AE_GRID_DATA_TYPE_E data_type, uint32_t *data); -int DSP2_Get_AE_Stats(int grid_num, uint32_t *data); - -void DSP2_Set_AWB_State(BL_Fun_Type state); -int DSP2_Get_AWB_Stats(int grid_num, uint32_t *data); -void DSP2_Set_AWB_Stats_Conf(const dsp2_awb_stats_conf_t *awb_stats_conf); -void DSP2_Get_AWB_Stats_Conf(dsp2_awb_stats_conf_t *awb_stats_conf); -void DSP2_Get_AWB_Sum(int grid_idx, RGB_SUM_S *rgb_sum); -void DSP2_Get_AWB_ValidGridNum(int *valid_grid_num); - -void DSP2_Set_AWB_Gain(const DSP2_RGB_Gain_Type *rgb_gain); -void DSP2_Get_AWB_Gain(DSP2_RGB_Gain_Type *rgb_gain); -void DSP2_Set_RB_Gain(const DSP2_RB_Gain_Type *rb_gain); - -void DSP2_Set_AWB2_State(BL_Fun_Type state); -void DSP2_Set_AWB2_Stats_Conf(const dsp2_awb2_stats_conf_t *awb_stats_conf); -int DSP2_Get_AWB2_Sum(dsp2_awb2_sum_t *sum); -void DSP2_Set_AWB2_Gain_State(BL_Fun_Type state); -void DSP2_Set_AWB2_Gain(const DSP2_RGB_Gain_Type *gain); -void DSP2_Get_AWB2_Gain(DSP2_RGB_Gain_Type *rgb_gain); - -int DSP2_Get_Output_Window(BL_Img_Size_T *out_win); - -/* Set R/G/B BLC, value range : 0-1023 */ -int DSP2_Set_BLC(const DSP2_CLAMP_S *clamp); -int DSP2_Get_BLC(DSP2_CLAMP_S *clamp); - -void DSP2_Set_DPC_State(BL_Fun_Type state); -void DSP2_Enable_DPC(void); -void DSP2_Disable_DPC(void); -int DSP2_Set_Defect_Correction_Enhance_Group(const DSP2_DPC_ENHANCE_GROUP_TYPE *value); -int DSP2_Get_Defect_Correction_Enhance_Group(DSP2_DPC_ENHANCE_GROUP_TYPE *value); -int DSP2_Set_Defect_Correction_Threshold_Group(const DSP2_DPC_THRESHOLD_GROUP_TYPE *value); -int DSP2_Get_Defect_Correction_Threshold_Group(DSP2_DPC_THRESHOLD_GROUP_TYPE *value); - -void DSP2_Set_BNR_State(BL_Fun_Type state); -void DSP2_Get_BNR_State(BL_Fun_Type *state); -void DSP2_Set_BNR_Weight(int value); -void DSP2_Get_BNR_Weight(int *value); -void DSP2_Set_BNR_LPF_Weight(int value); -void DSP2_Get_BNR_LPF_Weight(int *value); -void DSP2_Set_BNR_Threshold(const DSP2_BNR_THRESHOLD_TYPE *value); -void DSP2_Get_BNR_Threshold(DSP2_BNR_THRESHOLD_TYPE *value); -void DSP2_Set_BNR_Fallback(const DSP2_BNR_FALLBACK_TYPE *value); -void DSP2_Get_BNR_Fallback(DSP2_BNR_FALLBACK_TYPE *value); - -void DSP2_Set_Brightness(int value); -void DSP2_Get_Brightness(int *value); - -void DSP2_Set_LSC_State(BL_Fun_Type state); -void DSP2_Enable_LSC(void); -void DSP2_Disable_LSC(void); -void DSP2_Get_LSC_State(BL_Fun_Type *state); - -/* Set Lens Shading Correction offset */ -int DSP2_Set_LSC_Offset(int xoffset, int yoffset); - -/* Set/Get Lens Shading Correction setting, value range: please see DSP2_LSC_COEF_S */ -int DSP2_Set_LSC_Coeff(const DSP2_LSC_COEF_S *lsc); -int DSP2_Get_LSC_Coeff(DSP2_LSC_COEF_S *lsc); - -/* Set/Get Lens Shading Correction R,G,B MAX, value range: 0-255 (refs to demo app) */ -int DSP2_Set_LSC_Max(const DSP2_LSC_MAX_S *lsc_max); -int DSP2_Get_LSC_Max(DSP2_LSC_MAX_S *lsc_max); - -void DSP2_Set_Digital_Gain(uint16_t dgain); - -void DSP2_Set_CCM_State(BL_Fun_Type state); -void DSP2_Get_CCM_State(BL_Fun_Type *state); - -/* Set/Get Color Correction Matrix Coefficient Value, value range: 0-4095, 512 normalize to 1 */ -void DSP2_Set_CCM_Coef(const DSP2_CCM_COEF_S *ccm); -void DSP2_Get_CCM_Coef(DSP2_CCM_COEF_S *ccm); - -void DSP2_Set_Gamma_State(BL_Fun_Type state); -void DSP2_Get_Gamma_State(BL_Fun_Type *state); - -/* Set/Get Gamma, value range: 0-4095 */ -void DSP2_Set_Gamma_Coef(const DSP2_Gamma_Curve_Type *gamma_curve); -void DSP2_Get_Gamma_Coef(DSP2_Gamma_Curve_Type *gamma_curve); - -void DSP2_Init_Color_Enhancement(); - -/* Set/Get YUV Conversion mode, if you want to change the yuv range, please set yuv adjust */ -void DSP2_Set_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE type); -void DSP2_Get_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE *type); - -/* Set/Get Brightness, value range: TODO -128-127 */ -void DSP2_Set_Brightness(int value); -void DSP2_Get_Brightness(int *value); - -/* Set/Get Contrast, value range: TODO 0-255 */ -void DSP2_Set_Contrast(int value); -void DSP2_Get_Contrast(int *value); - -/* Set/Get Saturation, value range: TODO 0-255 */ -void DSP2_Set_Saturation(const DSP2_SATURATION_S *saturation); -void DSP2_Get_Saturation(DSP2_SATURATION_S *saturation); - -/* Set/Get Noise Level, value range: 0-63 */ -void DSP2_Set_Noise_Level(int value); -void DSP2_Get_Noise_Level(int *value); - -/* Set/Get 2D Noise Reduction, value range: 0-31 */ -void DSP2_Set_2D_NR(int value); -void DSP2_Get_2D_NR(int *value); - -/* Set/Get 3D Noise Reduction, value range: 0-31 */ -void DSP2_Set_3D_NR(int value); -void DSP2_Get_3D_NR(int *value); - -void DSP2_Set_EE_State(BL_Fun_Type state); -void DSP2_Enable_EE(void); -void DSP2_Disable_EE(void); -void DSP2_EnableEEOverShoot(void); -void DSP2_DisableEEOverShoot(void); -void DSP2_Set_EE_Thresh(const DSP2_EE_Thresh_Type *threshCfg); -void DSP2_Get_EE_Thresh(DSP2_EE_Thresh_Type *threshCfg); -void DSP2_Set_EE_Strength(const DSP2_EE_Str_Type *strCfg); -void DSP2_Get_EE_Strength(DSP2_EE_Str_Type *strCfg); -void DSP2_Set_EE_LumaWeight(const DSP2_EE_Luma_Weight_Type *lumaWgtCfg); -void DSP2_Get_EE_LumaWeight(DSP2_EE_Luma_Weight_Type *lumaWgtCfg); - -void DSP2_Set_ChromaSuppress_State(BL_Fun_Type state); -void DSP2_Enable_ChromaSuppress(void); -void DSP2_Disable_ChromaSuppress(void); - -void DSP2_Set_ChromaSuppress(const DSP2_Chroma_Suppress_Type *chromaSupprCfg); -void DSP2_Get_ChromaSuppress(DSP2_Chroma_Suppress_Type *chromaSupprCfg); - -/*@} end of group DSP2_Public_Functions */ - -/*@} end of group DSP2 */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_axi_ctrl.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_axi_ctrl.h deleted file mode 100644 index 25f9933a71..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_axi_ctrl.h +++ /dev/null @@ -1,174 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_axi_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_AXI_CTRL_H__ -#define __BL808_DSP2_AXI_CTRL_H__ - -#include "dsp2_axi_ctrl_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_AXI_CTRL - * @{ - */ - -/** @defgroup DSP2_AXI_CTRL_Public_Types - * @{ - */ - -/** - * @brief 3DNR burst type definition - */ -typedef enum { - DSP2_3DNR_BURST_TYPE_SINGLE, /*!< DSP2 3DNR burst type:single */ - DSP2_3DNR_BURST_TYPE_INCR4, /*!< DSP2 3DNR burst type:incrementing 4 */ - DSP2_3DNR_BURST_TYPE_INCR8, /*!< DSP2 3DNR burst type:incrementing 8 */ - DSP2_3DNR_BURST_TYPE_INCR16, /*!< DSP2 3DNR burst type:incrementing 16 */ - DSP2_3DNR_BURST_TYPE_INCR32 = 5, /*!< DSP2 3DNR burst type:incrementing 32 */ - DSP2_3DNR_BURST_TYPE_INCR64, /*!< DSP2 3DNR burst type:incrementing 64 */ -} DSP2_3DNR_Burst_Type; - -/** - * @brief 3DNR status type definition - */ -typedef enum { - DSP2_3DNR_STATUS_R_DRAIN = 4, /*!< Read fifo drain error status */ - DSP2_3DNR_STATUS_W_OVERFLOW, /*!< Write overflow status */ - DSP2_3DNR_STATUS_W_DVP_IDLE = 8, /*!< Write dvp idle status */ - DSP2_3DNR_STATUS_W_DVP_WTST, /*!< Write dvp wait start status */ - DSP2_3DNR_STATUS_W_DVP_FUNC, /*!< Write dvp function status */ - DSP2_3DNR_STATUS_W_DVP_FEND, /*!< Write dvp function end status */ - DSP2_3DNR_STATUS_W_DVP_FLSH, /*!< Write dvp flush status */ - DSP2_3DNR_STATUS_W_BUS_IDLE, /*!< Write bus idle status */ - DSP2_3DNR_STATUS_W_BUS_FUNC, /*!< Write bus function status */ - DSP2_3DNR_STATUS_W_BUS_FEND, /*!< Write bus function end status */ - DSP2_3DNR_STATUS_W_BUS_FLSH, /*!< Write bus flush status */ - DSP2_3DNR_STATUS_R_DVP_IDLE, /*!< Read dvp idle status */ - DSP2_3DNR_STATUS_R_DVP_WTST, /*!< Read dvp wait start status */ - DSP2_3DNR_STATUS_R_DVP_FUNC, /*!< Read dvp function status */ - DSP2_3DNR_STATUS_R_DVP_FEND, /*!< Read dvp function end status */ - DSP2_3DNR_STATUS_R_DVP_FLSH, /*!< Read dvp flush status */ - DSP2_3DNR_STATUS_R_BUS_IDLE, /*!< Read bus idle status */ - DSP2_3DNR_STATUS_R_BUS_FUNC, /*!< Read bus function status */ - DSP2_3DNR_STATUS_R_BUS_FEND, /*!< Read bus function end status */ - DSP2_3DNR_STATUS_R_BUS_FLSH, /*!< Read bus flush status */ - DSP2_3DNR_STATUS_R_IDLE, /*!< AXI read channel idle status */ - DSP2_3DNR_STATUS_W_IDLE, /*!< AXI write channel idle status */ -} DSP2_3DNR_Status_Type; - -/** - * @brief 3DNR configure strcut definition - */ -typedef struct -{ - DSP2_3DNR_Burst_Type burst; /*!< 3DNR burst length */ - uint32_t memStart; /*!< Data start address */ - uint32_t memSize; /*!< Memory size */ - uint16_t hsyncStart; /*!< Hsync active start count */ - uint16_t hsyncEnd; /*!< Hsync active end count */ - uint16_t vsyncStart; /*!< Vsync active start count */ - uint16_t vsyncEnd; /*!< Vsync active end count */ -} DSP2_3DNR_Cfg_Type; - -/*@} end of group DSP2_AXI_CTRL_Public_Types */ - -/** @defgroup DSP2_AXI_CTRL_Public_Constants - * @{ - */ - -/** @defgroup DSP2_3DNR_BURST_TYPE - * @{ - */ -#define IS_DSP2_3DNR_BURST_TYPE(type) (((type) == DSP2_3DNR_BURST_TYPE_SINGLE) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR4) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR8) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR16) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR32) || \ - ((type) == DSP2_3DNR_BURST_TYPE_INCR64)) - -/** @defgroup DSP2_3DNR_STATUS_TYPE - * @{ - */ -#define IS_DSP2_3DNR_STATUS_TYPE(type) (((type) == DSP2_3DNR_STATUS_R_DRAIN) || \ - ((type) == DSP2_3DNR_STATUS_W_OVERFLOW) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_WTST) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_FEND) || \ - ((type) == DSP2_3DNR_STATUS_W_DVP_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_FEND) || \ - ((type) == DSP2_3DNR_STATUS_W_BUS_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_WTST) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_FEND) || \ - ((type) == DSP2_3DNR_STATUS_R_DVP_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_FUNC) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_FEND) || \ - ((type) == DSP2_3DNR_STATUS_R_BUS_FLSH) || \ - ((type) == DSP2_3DNR_STATUS_R_IDLE) || \ - ((type) == DSP2_3DNR_STATUS_W_IDLE)) - -/*@} end of group DSP2_AXI_CTRL_Public_Constants */ - -/** @defgroup DSP2_AXI_CTRL_Public_Macros - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Public_Macros */ - -/** @defgroup DSP2_AXI_CTRL_Public_Functions - * @{ - */ -void DSP2_3DNR_Init(DSP2_3DNR_Cfg_Type *dsp23DNRCfg); -void DSP2_3DNR_Enable(void); -void DSP2_3DNR_Disable(void); -void DSP2_3DNR_Clear_Write_Overflow(void); -void DSP2_3DNR_Clear_Read_Drain(void); -BL_Sts_Type DSP2_3DNR_Get_status(DSP2_3DNR_Status_Type dsp23DNRStatus); - -/*@} end of group DSP2_AXI_CTRL_Public_Functions */ - -/*@} end of group DSP2_AXI_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_AXI_CTRL_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_misc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_misc.h deleted file mode 100644 index 2c65e57ecf..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_misc.h +++ /dev/null @@ -1,722 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_misc.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_MISC_H__ -#define __BL808_DSP2_MISC_H__ - -#include "dsp2_misc_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_MISC - * @{ - */ - -/** @defgroup DSP2_MISC_Public_Types - * @{ - */ - -/** - * @brief DVP 2X input data order type definition - */ -typedef enum { - DSP2_MISC_2X_DATA_BYTE_LOWER, /*!< The first data is lower-byte */ - DSP2_MISC_2X_DATA_BYTE_HIGHER, /*!< The first data is higher-byte */ -}DSP2_MISC_2X_Data_Order_Type; - -/** - * @brief Input V/H sync active level type definition - */ -typedef enum { - DSP2_MISC_ACTIVE_HIGH, /*!< Input is active-high */ - DSP2_MISC_ACTIVE_LOW, /*!< Input is active-low */ -}DSP2_MISC_Active_Level_Type; - -/** - * @brief DVP TSRC data source type definition - */ -typedef enum { - DSP2_MISC_TSRC_SOURCE_DVP, /*!< DVP TSRC data source is DVP */ - DSP2_MISC_TSRC_SOURCE_CSI, /*!< DVP TSRC data source is MIPI CSI */ -}DSP2_MISC_TSRC_Source_Type; - -/** - * @brief CAM id type definition - */ -typedef enum { - DSP2_MISC_CAM_0_ID, /*!< CAM 0 port define */ - DSP2_MISC_CAM_1_ID, /*!< CAM 1 port define */ - DSP2_MISC_CAM_2_ID, /*!< CAM 2 port define */ - DSP2_MISC_CAM_3_ID, /*!< CAM 3 port define */ - DSP2_MISC_CAM_4_ID, /*!< CAM 4 port define */ - DSP2_MISC_CAM_5_ID, /*!< CAM 5 port define */ - DSP2_MISC_CAM_6_ID, /*!< CAM 6 port define */ - DSP2_MISC_CAM_7_ID, /*!< CAM 7 port define */ - DSP2_MISC_CAM_ID_MAX, /*!< CAM max ID define */ -} DSP2_MISC_CAM_ID_Type; - -/** - * @brief Crop id type definition - */ -typedef enum { - DSP2_MISC_CROP_0_ID, /*!< Crop 0 port define */ - DSP2_MISC_CROP_1_ID, /*!< Crop 1 port define */ - DSP2_MISC_CROP_2_ID, /*!< Crop 2 port define */ - DSP2_MISC_CROP_3_ID, /*!< Crop 3 port define */ - DSP2_MISC_CROP_ID_MAX, /*!< Crop max ID define */ -} DSP2_MISC_Crop_ID_Type; - -/** - * @brief Scaler id type definition - */ -typedef enum { - DSP2_MISC_SCALER_0_ID, /*!< Scaler 0 port define */ - DSP2_MISC_SCALER_1_ID, /*!< Scaler 1 port define */ - DSP2_MISC_SCALER_2_ID, /*!< Scaler 2 port define */ - DSP2_MISC_SCALER_3_ID, /*!< Scaler 3 port define */ - DSP2_MISC_SCALER_ID_MAX, /*!< Scaler max ID define */ -} DSP2_MISC_Scaler_ID_Type; - -/** - * @brief OSD id type definition - */ -typedef enum { - DSP2_MISC_OSD_0_ID, /*!< OSD 0 port define */ - DSP2_MISC_OSD_1_ID, /*!< OSD 1 port define */ - DSP2_MISC_OSD_2_ID, /*!< OSD 2 port define */ - DSP2_MISC_OSD_3_ID, /*!< OSD 3 port define */ - DSP2_MISC_OSD_ID_MAX, /*!< OSD max ID define */ -} DSP2_MISC_OSD_ID_Type; - -/** - * @brief Adjust id type definition - */ -typedef enum { - DSP2_MISC_ADJUST_0_ID, /*!< Adjust 0 port define */ - DSP2_MISC_ADJUST_1_ID, /*!< Adjust 1 port define */ - DSP2_MISC_ADJUST_2_ID, /*!< Adjust 2 port define */ - DSP2_MISC_ADJUST_3_ID, /*!< Adjust 3 port define */ - DSP2_MISC_ADJUST_ID_MAX, /*!< Adjust max ID define */ -} DSP2_MISC_Adjust_ID_Type; - -/** - * @brief YUV2RGB id type definition - */ -typedef enum { - DSP2_MISC_YUV2RGB_DISPLAY_ID, /*!< Display YUV2RGB port define */ - DSP2_MISC_YUV2RGB_NORMAL_ID, /*!< Normal YUV2RGB port define */ - DSP2_MISC_YUV2RGB_ID_MAX, /*!< YUV2RGB max ID define */ -} DSP2_MISC_YUV2RGB_ID_Type; - -/** - * @brief Frame id type definition - */ -typedef enum { - DSP2_MISC_FRAME_BAYER_ID, /*!< Bayer ID */ - DSP2_MISC_FRAME_YUV_ID, /*!< YUV ID */ -} DSP2_MISC_Frame_ID_Type; - -/** - * @brief Frame id vsync edge type definition - */ -typedef enum { - DSP2_MISC_FRAME_ID_VSYNC_NEGEDGE, /*!< Frame ID base on vsync negedge */ - DSP2_MISC_FRAME_ID_VSYNC_POSEDGE, /*!< Frame ID base on vsync posedge */ -} DSP2_MISC_Frame_ID_Edge_Type; - -/** - * @brief CAM input type definition - */ -typedef enum { - DSP2_MISC_CAM_DSP2_INPUT, /*!< Use DSP2 input as CAM input */ - DSP2_MISC_CAM_ACTIVE_DVP_OUTPUT, /*!< Use active DVP(TG) as CAM input */ - DSP2_MISC_CAM_DEFECT_CORRECT_OUTPUT, /*!< Use defect correct as CAM input */ - DSP2_MISC_CAM_CCM_R_OUTPUT, /*!< Use CCM R as CAM input */ - DSP2_MISC_CAM_CCM_G_OUTPUT, /*!< Use CCM G as CAM input */ - DSP2_MISC_CAM_CCM_B_OUTPUT, /*!< Use CCM B as CAM input */ - DSP2_MISC_CAM_GAMMA_R_OUTPUT, /*!< Use gamma R as CAM input */ - DSP2_MISC_CAM_GAMMA_G_OUTPUT, /*!< Use gamma G as CAM input */ - DSP2_MISC_CAM_NONE_OUTPUT, /*!< Don't use */ - DSP2_MISC_CAM_BNR_OUTPUT, /*!< Use BNR as CAM input */ - DSP2_MISC_CAM_NR_OUTPUT, /*!< Use NR as CAM input */ - DSP2_MISC_CAM_EE_OUTPUT, /*!< Use EE as CAM input */ - DSP2_MISC_CAM_DSP2_OUTPUT, /*!< Use DSP2 output as CAM input */ - DSP2_MISC_CAM_OSD_0_OUTPUT, /*!< Use OSD 0 as CAM input */ - DSP2_MISC_CAM_OSD_1_OUTPUT, /*!< Use OSD 1 as CAM input */ - DSP2_MISC_CAM_OSD_2_OUTPUT, /*!< Use OSD 2 as CAM input */ - DSP2_MISC_CAM_OSD_3_OUTPUT, /*!< Use OSD 3 as CAM input */ - DSP2_MISC_CAM_SCALER_0_OUTPUT, /*!< Use scaler 0 as CAM input */ - DSP2_MISC_CAM_SCALER_1_OUTPUT, /*!< Use scaler 1 as CAM input */ - DSP2_MISC_CAM_SCALER_2_OUTPUT, /*!< Use scaler 2 as CAM input */ - DSP2_MISC_CAM_SCALER_3_OUTPUT, /*!< Use scaler 3 as CAM input */ - DSP2_MISC_CAM_ADJUST_0_OUTPUT, /*!< Use adjust 0 as CAM input */ - DSP2_MISC_CAM_ADJUST_1_OUTPUT, /*!< Use adjust 1 as CAM input */ - DSP2_MISC_CAM_ADJUST_2_OUTPUT, /*!< Use adjust 2 as CAM input */ - DSP2_MISC_CAM_ADJUST_3_OUTPUT, /*!< Use adjust 3 as CAM input */ - DSP2_MISC_CAM_YUV420_0_OUTPUT, /*!< Use YUV420 0 as CAM input */ - DSP2_MISC_CAM_YUV420_1_OUTPUT, /*!< Use YUV420 1 as CAM input */ - DSP2_MISC_CAM_YUV420_2_OUTPUT, /*!< Use YUV420 2 as CAM input */ - DSP2_MISC_CAM_YUV420_3_OUTPUT, /*!< Use YUV420 3 as CAM input */ - DSP2_MISC_CAM_GAMMA_B_OUTPUT, /*!< Use gamma B as CAM input */ - DSP2_MISC_CAM_WDR_Y_OUTPUT, /*!< Use WDR Y as CAM input */ - DSP2_MISC_CAM_WDR_U_OUTPUT, /*!< Use WDR U as CAM input */ - DSP2_MISC_CAM_WDR_V_OUTPUT, /*!< Use WDR V as CAM input */ - DSP2_MISC_CAM_LSC_OUTPUT, /*!< Use LSC as CAM input */ - DSP2_MISC_CAM_AWB2_OUTPUT, /*!< Use AWB2 as CAM input */ - DSP2_MISC_CAM_YUV2RGB_OUTPUT, /*!< Use YUV2RGB as CAM input */ - DSP2_MISC_CAM_DVP_AS_2X_OUTPUT, /*!< Use DVP AS 2X as CAM input */ -} DSP2_MISC_CAM_Input_Type; - -/** - * @brief Scaler input type definition - */ -typedef enum { - DSP2_MISC_SCALER_DSP2_OUTPUT, /*!< Use DSP2 output as scaler input */ - DSP2_MISC_SCALER_DSP2_INPUT, /*!< Use DSP2 input as scaler input */ - DSP2_MISC_SCALER_OSD_0_OUTPUT, /*!< Use OSD 0 as scaler input */ - DSP2_MISC_SCALER_OSD_1_OUTPUT, /*!< Use OSD 1 as scaler input */ - DSP2_MISC_SCALER_OSD_2_OUTPUT, /*!< Use OSD 2 as scaler input */ - DSP2_MISC_SCALER_OSD_3_OUTPUT, /*!< Use OSD 3 as scaler input */ -} DSP2_MISC_Scaler_Input_Type; - -/** - * @brief OSD input type definition - */ -typedef enum { - DSP2_MISC_OSD_DSP2_OUTPUT, /*!< Use DSP2 output as OSD input */ - DSP2_MISC_OSD_DSP2_INPUT, /*!< Use DSP2 input as OSD input */ - DSP2_MISC_OSD_SCALER_0_OUTPUT, /*!< Use scaler 0 as OSD input */ - DSP2_MISC_OSD_SCALER_1_OUTPUT, /*!< Use scaler 1 as OSD input */ - DSP2_MISC_OSD_SCALER_2_OUTPUT, /*!< Use scaler 2 as OSD input */ - DSP2_MISC_OSD_SCALER_3_OUTPUT, /*!< Use scaler 3 as OSD input */ - DSP2_MISC_OSD_OSD_0_OUTPUT, /*!< Use osd 0 as OSD input */ - DSP2_MISC_OSD_DVP_AS_2X_OUTPUT, /*!< Use dvp_as_2x as OSD input */ -} DSP2_MISC_OSD_Input_Type; - -/** - * @brief Adjust input type definition - */ -typedef enum { - DSP2_MISC_ADJUST_DSP2_OUTPUT, /*!< Use DSP2 output as adjust input */ - DSP2_MISC_ADJUST_DSP2_INPUT, /*!< Use DSP2 input as adjust input */ - DSP2_MISC_ADJUST_OSD_0_OUTPUT, /*!< Use OSD 0 as adjust input */ - DSP2_MISC_ADJUST_OSD_1_OUTPUT, /*!< Use OSD 1 as adjust input */ - DSP2_MISC_ADJUST_OSD_2_OUTPUT, /*!< Use OSD 2 as adjust input */ - DSP2_MISC_ADJUST_OSD_3_OUTPUT, /*!< Use OSD 3 as adjust input */ - DSP2_MISC_ADJUST_SCALER_0_OUTPUT, /*!< Use scaler 0 as adjust input */ - DSP2_MISC_ADJUST_SCALER_1_OUTPUT, /*!< Use scaler 1 as adjust input */ - DSP2_MISC_ADJUST_SCALER_2_OUTPUT, /*!< Use scaler 2 as adjust input */ - DSP2_MISC_ADJUST_SCALER_3_OUTPUT, /*!< Use scaler 3 as adjust input */ -} DSP2_MISC_Adjust_Input_Type; - -/** - * @brief YUV2RGB input type definition - */ -typedef enum { - DSP2_MISC_YUV2RGB_DSP2_OUTPUT, /*!< Use DSP2 output as yuv2rgb input */ - DSP2_MISC_YUV2RGB_DSP2_INPUT, /*!< Use DSP2 input as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_0_OUTPUT, /*!< Use OSD 0 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_1_OUTPUT, /*!< Use OSD 1 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_2_OUTPUT, /*!< Use OSD 2 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_OSD_3_OUTPUT, /*!< Use OSD 3 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_0_OUTPUT, /*!< Use scaler 0 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_1_OUTPUT, /*!< Use scaler 1 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_2_OUTPUT, /*!< Use scaler 2 as yuv2rgb input */ - DSP2_MISC_YUV2RGB_SCALER_3_OUTPUT, /*!< Use scaler 3 as yuv2rgb input */ -} DSP2_MISC_YUV2RGB_Input_Type; - -/** - * @brief Bayer data shift direction type definition - */ -typedef enum { - DSP2_MISC_BAYER_SHIFT_LEFT, /*!< Bayer data shift left */ - DSP2_MISC_BAYER_SHIFT_RIGHT, /*!< Bayer data shift right */ -} DSP2_MISC_Bayer_Shift_Type; - -/** - * @brief DSP2 MISC interrupt type definition - */ -typedef enum { - DSP2_MISC_INT_AWB0, /*!< AWB 0 interrupt */ - DSP2_MISC_INT_AE, /*!< AE interrupt */ - DSP2_MISC_INT_WDR, /*!< WDR interrupt */ - DSP2_MISC_INT_AWB1, /*!< AWB 1 interrupt */ - DSP2_MISC_INT_OSD_PB, /*!< OSD probe interrupt */ - DSP2_MISC_INT_SEOF0, /*!< S/E-oF 0 interrupt */ - DSP2_MISC_INT_SEOF1, /*!< S/E-oF 1 interrupt */ - DSP2_MISC_INT_SEOF2, /*!< S/E-oF 2 interrupt */ - DSP2_MISC_INT_AE_HIST, /*!< AE hist interrupt */ - DSP2_MISC_INT_AWB2, /*!< AWB 2 interrupt */ - DSP2_MISC_INT_DISPLAY, /*!< Display S/E-oF 0 interrupt */ - DSP2_MISC_INT_SEOF3, /*!< S/E-oF 3 interrupt */ - DSP2_MISC_INT_ALL, /*!< All the interrupt */ -} DSP2_MISC_INT_Type; - -/** - * @brief SEOF interrupt vsync source type definition - */ -typedef enum { - DSP2_MISC_SEOF_VSYNC_SENSOR = 0, /*!< Use sensor vsync as SEOF vsync source */ - DSP2_MISC_SEOF_VSYNC_DSP2_ACT = 1, /*!< Use dsp2 active vsync as SEOF vsync source */ - DSP2_MISC_SEOF_VSYNC_DSP2_OUT = 2, /*!< Use dsp2 out vsync as SEOF vsync source */ - DSP2_MISC_SEOF_VSYNC_DVP_TSRC = 3, /*!< Use dvp tsrc vsync as SEOF vsync source */ - DSP2_MISC_SEOF_DISPLAY_TEST_SRC = 0, /*!< Use display test source as display SEOF vsync source */ - DSP2_MISC_SEOF_DISPLAY_OUTPUT = 1, /*!< Use display output as display SEOF vsync source */ -} DSP2_MISC_SEOF_Source_Type; - -/** - * @brief SEOF interrupt trigger vsync edge type definition - */ -typedef enum { - DSP2_MISC_SEOF_VSYNC_NEGEDGE, /*!< Vsync negedge will trigger interrupt */ - DSP2_MISC_SEOF_VSYNC_POSEDGE, /*!< Vsync posedge will trigger interrupt */ -} DSP2_MISC_SEOF_Edge_Type; - -/** - * @brief Display input type definition - */ -typedef enum { - DSP2_MISC_DISPLAY_YUV2RGB_OUTPUT, /*!< Use yuv2rgb output as display input */ - DSP2_MISC_DISPLAY_OSD_DP_OUTPUT, /*!< Use OSD_DP output as display input */ - DSP2_MISC_DISPLAY_TSRC_RGB_OUTPUT, /*!< Use dvp tsrc rgb output as display input */ - DSP2_MISC_DISPLAY_TSRC_YUV422_OUTPUT, /*!< Use dvp tsrc yuv422 output as display input */ -} DSP2_MISC_Display_Input_Type; - -/** - * @brief Display OSD input type definition - */ -typedef enum { - DSP2_MISC_DISPLAY_OSD_YUV420TO422_OUTPUT, /*!< Use yuv420to422 output as display OSD input */ - DSP2_MISC_DISPLAY_OSD_RGB2YUV422_OUTPUT, /*!< Use rgb2yuv422 output as display OSD input */ - DSP2_MISC_DISPLAY_OSD_TSRCYUV422_OUTPUT, /*!< Use dvp tsrc yuv422 output as display OSD input */ -} DSP2_MISC_Display_OSD_Input_Type; - -/** - * @brief DVP AS 2X configuration struct definition - */ -typedef struct { - DSP2_MISC_Active_Level_Type hSyncLevel; /*!< Input H-Sync active level */ - DSP2_MISC_Active_Level_Type vSyncLevel; /*!< Input V-Sync active level */ - DSP2_MISC_2X_Data_Order_Type dataOrder; /*!< Input data order */ - uint16_t fifoThreshold; /*!< Fifo threshold for each DVP line to start to - output,((Width-Fifo_th)*T_in*2)<(Width*T_out)<((Width-Fifo_th)*T_in*2+Blank*T_in) */ -}DSP2_MISC_2X_Cfg_Type; - -/** - * @brief DVP reshape configuration struct definition - */ -typedef struct { - DSP2_MISC_Active_Level_Type hSyncLevel; /*!< Input H-Sync active level */ - DSP2_MISC_Active_Level_Type vSyncLevel; /*!< Input V-Sync active level */ - BL_Fun_Type enable; /*!< Enable or disable sensor vsync toggle remove */ - uint8_t vsyncNumber; /*!< Number of sensor vsync toggle before sensor stable */ -}DSP2_MISC_Reshape_Cfg_Type; - -/** - * @brief Display configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type dpiEnable; /*!< Enable or disable dpi function, only one of the four functions can be enabled at the same time */ - BL_Fun_Type bt1120Enable; /*!< Enable or disable BT1120 function, only one of the four functions can be enabled at the same time */ - BL_Fun_Type hdmiEnable; /*!< Enable or disable HDMI function, only one of the four functions can be enabled at the same time */ - DSP2_MISC_Display_Input_Type inputType; /*!< Select display input */ - DSP2_MISC_Display_OSD_Input_Type osdType; /*!< Select display OSD input */ - uint8_t hsyncWidth; /*!< Horizontal synchronization width */ - uint8_t hfpWidth; /*!< Horizontal front porch width */ - uint8_t vsyncWidth; /*!< Vertical synchronization width */ - uint8_t vfpWidth; /*!< Vertical front porch width */ -} DSP2_MISC_Display_Cfg_Type; - -/** - * @brief Display gamma configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type ch0Enable; /*!< Enable or disable display gamma channel 0 */ - BL_Fun_Type ch1Enable; /*!< Enable or disable display gamma channel 1 */ - BL_Fun_Type ch2Enable; /*!< Enable or disable display gamma channel 2 */ - uint8_t *gammaCurve; /*!< Gamma curve */ -} DSP2_MISC_Display_Gamma_Cfg_Type; - -/** - * @brief YUV2RGB configuration struct definition - */ -typedef struct -{ - BL_Fun_Type enable; /*!< Enable or disable yuv2rgb function */ - uint16_t preOffset0; /*!< YUV2RGB pre offset 0 */ - uint16_t preOffset1; /*!< YUV2RGB pre offset 1 */ - uint16_t preOffset2; /*!< YUV2RGB pre offset 2 */ - uint16_t postOffset0; /*!< YUV2RGB post offset 0 */ - uint16_t postOffset1; /*!< YUV2RGB post offset 1 */ - uint16_t postOffset2; /*!< YUV2RGB post offset 2 */ - uint16_t matrix00; /*!< YUV2RGB matrix 00 */ - uint16_t matrix01; /*!< YUV2RGB matrix 01 */ - uint16_t matrix02; /*!< YUV2RGB matrix 02 */ - uint16_t matrix10; /*!< YUV2RGB matrix 10 */ - uint16_t matrix11; /*!< YUV2RGB matrix 11 */ - uint16_t matrix12; /*!< YUV2RGB matrix 12 */ - uint16_t matrix20; /*!< YUV2RGB matrix 20 */ - uint16_t matrix21; /*!< YUV2RGB matrix 21 */ - uint16_t matrix22; /*!< YUV2RGB matrix 22 */ -} DSP2_MISC_YUV2RGB_Cfg_Type; - -/** - * @brief Crop configuration struct definition - */ -typedef struct -{ - uint16_t hsyncStart; /*!< Hsync valid start */ - uint16_t hsyncEnd; /*!< Hsync valid end */ - uint16_t vsyncStart; /*!< Vsync valid start */ - uint16_t vsyncEnd; /*!< Vsync valid end */ -} DSP2_MISC_Crop_Cfg_Type; - -/** - * @brief Scaler configuration struct definition - */ -typedef struct -{ - uint16_t inputWidth; /*!< Width of input frame */ - uint16_t inputHeight; /*!< Height of input frame */ - uint16_t outputWidth; /*!< Width of output frame */ - uint16_t outputHeight; /*!< Height of output frame */ -} DSP2_MISC_Scaler_Cfg_Type; - -/** - * @brief Adjust configuration struct definition - */ -typedef struct -{ - uint16_t yLuma; /*!< Y luma,higher luma */ - uint16_t yMul0; /*!< Contrast adjust mul0 */ - uint16_t yMul1; /*!< Contrast adjust mul1 */ - uint8_t yMin; /*!< Y min clip value */ - uint8_t yMax; /*!< Y max clip value */ - uint16_t uvMul0; /*!< Saturation adjust, software can multipiler gain to this value */ - uint16_t uvMul1; /*!< Saturation adjust, software can multipiler gain to this value */ - uint8_t uvMin; /*!< UV min clip value */ - uint8_t uvMax; /*!< UV max clip value */ -} DSP2_MISC_Adjust_Cfg_Type; - -/*@} end of group DSP2_MISC_Public_Types */ - -/** @defgroup DSP2_MISC_Public_Constants - * @{ - */ - -/** @defgroup DSP2_MISC_2X_DATA_ORDER_TYPE - * @{ - */ -#define IS_DSP2_MISC_2X_DATA_ORDER_TYPE(type) (((type) == DSP2_MISC_2X_DATA_BYTE_LOWER) || \ - ((type) == DSP2_MISC_2X_DATA_BYTE_HIGHER)) - -/** @defgroup DSP2_MISC_ACTIVE_LEVEL_TYPE - * @{ - */ -#define IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(type) (((type) == DSP2_MISC_ACTIVE_HIGH) || \ - ((type) == DSP2_MISC_ACTIVE_LOW)) - -/** @defgroup DSP2_MISC_TSRC_SOURCE_TYPE - * @{ - */ -#define IS_DSP2_MISC_TSRC_SOURCE_TYPE(type) (((type) == DSP2_MISC_TSRC_SOURCE_DVP) || \ - ((type) == DSP2_MISC_TSRC_SOURCE_CSI)) - -/** @defgroup DSP2_MISC_CAM_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_CAM_ID_TYPE(type) (((type) == DSP2_MISC_CAM_0_ID) || \ - ((type) == DSP2_MISC_CAM_1_ID) || \ - ((type) == DSP2_MISC_CAM_2_ID) || \ - ((type) == DSP2_MISC_CAM_3_ID) || \ - ((type) == DSP2_MISC_CAM_4_ID) || \ - ((type) == DSP2_MISC_CAM_5_ID) || \ - ((type) == DSP2_MISC_CAM_6_ID) || \ - ((type) == DSP2_MISC_CAM_7_ID) || \ - ((type) == DSP2_MISC_CAM_ID_MAX)) - -/** @defgroup DSP2_MISC_CROP_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_CROP_ID_TYPE(type) (((type) == DSP2_MISC_CROP_0_ID) || \ - ((type) == DSP2_MISC_CROP_1_ID) || \ - ((type) == DSP2_MISC_CROP_2_ID) || \ - ((type) == DSP2_MISC_CROP_3_ID) || \ - ((type) == DSP2_MISC_CROP_ID_MAX)) - -/** @defgroup DSP2_MISC_SCALER_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_SCALER_ID_TYPE(type) (((type) == DSP2_MISC_SCALER_0_ID) || \ - ((type) == DSP2_MISC_SCALER_1_ID) || \ - ((type) == DSP2_MISC_SCALER_2_ID) || \ - ((type) == DSP2_MISC_SCALER_3_ID) || \ - ((type) == DSP2_MISC_SCALER_ID_MAX)) - -/** @defgroup DSP2_MISC_OSD_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_OSD_ID_TYPE(type) (((type) == DSP2_MISC_OSD_0_ID) || \ - ((type) == DSP2_MISC_OSD_1_ID) || \ - ((type) == DSP2_MISC_OSD_2_ID) || \ - ((type) == DSP2_MISC_OSD_3_ID) || \ - ((type) == DSP2_MISC_OSD_ID_MAX)) - -/** @defgroup DSP2_MISC_ADJUST_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_ADJUST_ID_TYPE(type) (((type) == DSP2_MISC_ADJUST_0_ID) || \ - ((type) == DSP2_MISC_ADJUST_1_ID) || \ - ((type) == DSP2_MISC_ADJUST_2_ID) || \ - ((type) == DSP2_MISC_ADJUST_3_ID) || \ - ((type) == DSP2_MISC_ADJUST_ID_MAX)) - -/** @defgroup DSP2_MISC_YUV2RGB_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_YUV2RGB_ID_TYPE(type) (((type) == DSP2_MISC_YUV2RGB_DISPLAY_ID) || \ - ((type) == DSP2_MISC_YUV2RGB_NORMAL_ID) || \ - ((type) == DSP2_MISC_YUV2RGB_ID_MAX)) - -/** @defgroup DSP2_MISC_FRAME_ID_TYPE - * @{ - */ -#define IS_DSP2_MISC_FRAME_ID_TYPE(type) (((type) == DSP2_MISC_FRAME_BAYER_ID) || \ - ((type) == DSP2_MISC_FRAME_YUV_ID)) - -/** @defgroup DSP2_MISC_FRAME_ID_EDGE_TYPE - * @{ - */ -#define IS_DSP2_MISC_FRAME_ID_EDGE_TYPE(type) (((type) == DSP2_MISC_FRAME_ID_VSYNC_NEGEDGE) || \ - ((type) == DSP2_MISC_FRAME_ID_VSYNC_POSEDGE)) - -/** @defgroup DSP2_MISC_CAM_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_CAM_INPUT_TYPE(type) (((type) == DSP2_MISC_CAM_DSP2_INPUT) || \ - ((type) == DSP2_MISC_CAM_ACTIVE_DVP_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_DEFECT_CORRECT_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_CCM_R_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_CCM_G_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_CCM_B_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_GAMMA_R_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_GAMMA_G_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_NONE_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_BNR_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_NR_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_EE_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_OSD_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_SCALER_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_ADJUST_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_0_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_1_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV420_3_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_GAMMA_B_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_WDR_Y_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_WDR_U_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_WDR_V_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_LSC_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_AWB2_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_YUV2RGB_OUTPUT) || \ - ((type) == DSP2_MISC_CAM_DVP_AS_2X_OUTPUT)) - -/** @defgroup DSP2_MISC_SCALER_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_SCALER_INPUT_TYPE(type) (((type) == DSP2_MISC_SCALER_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_DSP2_INPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_1_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_2_OUTPUT) || \ - ((type) == DSP2_MISC_SCALER_OSD_3_OUTPUT)) - -/** @defgroup DSP2_MISC_OSD_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_OSD_INPUT_TYPE(type) (((type) == DSP2_MISC_OSD_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_DSP2_INPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_0_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_1_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_2_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_SCALER_3_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_OSD_DVP_AS_2X_OUTPUT)) - -/** @defgroup DSP2_MISC_YUV2RGB_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_YUV2RGB_INPUT_TYPE(type) (((type) == DSP2_MISC_YUV2RGB_DSP2_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_DSP2_INPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_0_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_1_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_2_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_OSD_3_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_0_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_1_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_2_OUTPUT) || \ - ((type) == DSP2_MISC_YUV2RGB_SCALER_3_OUTPUT)) - -/** @defgroup DSP2_MISC_BAYER_SHIFT_TYPE - * @{ - */ -#define IS_DSP2_MISC_BAYER_SHIFT_TYPE(type) (((type) == DSP2_MISC_BAYER_SHIFT_LEFT) || \ - ((type) == DSP2_MISC_BAYER_SHIFT_RIGHT)) - -/** @defgroup DSP2_MISC_INT_TYPE - * @{ - */ -#define IS_DSP2_MISC_INT_TYPE(type) (((type) == DSP2_MISC_INT_AWB0) || \ - ((type) == DSP2_MISC_INT_AE) || \ - ((type) == DSP2_MISC_INT_WDR) || \ - ((type) == DSP2_MISC_INT_AWB1) || \ - ((type) == DSP2_MISC_INT_OSD_PB) || \ - ((type) == DSP2_MISC_INT_SEOF0) || \ - ((type) == DSP2_MISC_INT_SEOF1) || \ - ((type) == DSP2_MISC_INT_SEOF2) || \ - ((type) == DSP2_MISC_INT_AE_HIST) || \ - ((type) == DSP2_MISC_INT_AWB2) || \ - ((type) == DSP2_MISC_INT_DISPLAY) || \ - ((type) == DSP2_MISC_INT_SEOF3) || \ - ((type) == DSP2_MISC_INT_ALL)) - -/** @defgroup DSP2_MISC_SEOF_SOURCE_TYPE - * @{ - */ -#define IS_DSP2_MISC_SEOF_SOURCE_TYPE(type) (((type) == DSP2_MISC_SEOF_VSYNC_SENSOR) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_DSP2_ACT) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_DSP2_OUT) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_DVP_TSRC) || \ - ((type) == DSP2_MISC_SEOF_DISPLAY_TEST_SRC) || \ - ((type) == DSP2_MISC_SEOF_DISPLAY_OUTPUT)) - -/** @defgroup DSP2_MISC_SEOF_EDGE_TYPE - * @{ - */ -#define IS_DSP2_MISC_SEOF_EDGE_TYPE(type) (((type) == DSP2_MISC_SEOF_VSYNC_NEGEDGE) || \ - ((type) == DSP2_MISC_SEOF_VSYNC_POSEDGE)) - -/** @defgroup DSP2_MISC_DISPLAY_INPUT_TYPE - * @{ - */ -#define IS_DSP2_MISC_DISPLAY_INPUT_TYPE(type) (((type) == DSP2_MISC_DISPLAY_YUV2RGB_OUTPUT) || \ - ((type) == DSP2_MISC_DISPLAY_YUV422_OUTPUT)) - -/*@} end of group DSP2_MISC_Public_Constants */ - -/** @defgroup DSP2_MISC_Public_Macros - * @{ - */ - -/*@} end of group DSP2_MISC_Public_Macros */ - -/** @defgroup DSP2_MISC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF0_IRQHandler(void); -void SEOF1_IRQHandler(void); -void SEOF2_IRQHandler(void); -void SEOF3_IRQHandler(void); -void AWB0_IRQHandler(void); -void AWB1_IRQHandler(void); -void AWB2_IRQHandler(void); -void AE_IRQHandler(void); -void AE_HIST_IRQHandler(void); -void WDR_IRQHandler(void); -void OSD_PB_IRQHandler(void); -void Display_IRQHandler(void); -#endif -void DSP2_MISC_2X_Init(DSP2_MISC_2X_Cfg_Type *dvp2xCfg); -void DSP2_MISC_2X_Enable(void); -void DSP2_MISC_2X_Disable(void); -void DSP2_MISC_CAM_Input_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_CAM_Input_Type inputType); -void DSP2_MISC_CAM_Frame_ID_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_Frame_ID_Type idType); -void DSP2_MISC_Frame_ID_Init(DSP2_MISC_Frame_ID_Type idType, DSP2_MISC_Frame_ID_Edge_Type edgeType, uint16_t vsyncCnt); -void DSP2_MISC_Frame_ID_Reset(DSP2_MISC_Frame_ID_Type idType); -void DSP2_MISC_OSD_Input_Select(DSP2_MISC_OSD_ID_Type osdId, DSP2_MISC_OSD_Input_Type inputType); -void DSP2_MISC_OSD_Probe_Input_Select(DSP2_MISC_OSD_Input_Type inputType); -void DSP2_MISC_Crop_Init(DSP2_MISC_Crop_ID_Type cropId, DSP2_MISC_Crop_Cfg_Type *cropCfg); -void DSP2_MISC_Crop_Enable(DSP2_MISC_Crop_ID_Type cropId); -void DSP2_MISC_Crop_Disable(DSP2_MISC_Crop_ID_Type cropId); -void DSP2_MISC_Scaler_Input_Select(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Input_Type inputType); -void DSP2_MISC_Scaler_Init(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Cfg_Type *scalerCfg); -void DSP2_MISC_Scaler_Enable(DSP2_MISC_Scaler_ID_Type scalerId); -void DSP2_MISC_Scaler_Disable(DSP2_MISC_Scaler_ID_Type scalerId); -void DSP2_MISC_Scaler_Shadow(DSP2_MISC_Scaler_ID_Type scalerId); -void DSP2_MISC_Adjust_Input_Select(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Input_Type inputType); -void DSP2_MISC_Adjust_Init(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Cfg_Type *adjustCfg); -void DSP2_MISC_Adjust_Enable(DSP2_MISC_Adjust_ID_Type adjustId); -void DSP2_MISC_Adjust_Disable(DSP2_MISC_Adjust_ID_Type adjustId); -void DSP2_MISC_Display_Init(DSP2_MISC_Display_Cfg_Type *displayCfg); -void DSP2_MISC_Display_Gamma_Init(DSP2_MISC_Display_Gamma_Cfg_Type *gammaCfg); -void DSP2_MISC_YUV2RGB_Input_Select(DSP2_MISC_YUV2RGB_Input_Type inputType); -void DSP2_MISC_YUV2RGB_Init(DSP2_MISC_YUV2RGB_ID_Type yuv2rgbId, DSP2_MISC_YUV2RGB_Cfg_Type *yuv2rgbCfg); -void DSP2_MISC_RGB2YUV_Init(DSP2_MISC_YUV2RGB_Cfg_Type *rgb2yuvCfg); -void DSP2_MISC_Int_Clear(DSP2_MISC_INT_Type intType); -void DSP2_MISC_Int_Mask(DSP2_MISC_INT_Type intType, BL_Mask_Type intMask); -void DSP2_MISC_Int_Callback_Install(DSP2_MISC_INT_Type intType, intCallback_Type *cbFun); -void DSP2_MISC_SEOF_Set_Source(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Source_Type source); -void DSP2_MISC_SEOF_Set_Edge(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Edge_Type edge); -void DSP2_MISC_Reshape_Init(DSP2_MISC_Reshape_Cfg_Type *reshapeCfg); -void DSP2_MISC_Reshape_Counter_Clear(void); -void DSP2_MISC_DE_As_Hsync(BL_Fun_Type enable); -void DSP2_MISC_TSRC_Source_Select(DSP2_MISC_TSRC_Source_Type sourceType); -void DSP2_MISC_Bayer_Shift(uint16_t bitEnable, DSP2_MISC_Bayer_Shift_Type shiftType, uint8_t bitShift); -void DSP2_MISC_M2N_Enable(uint8_t m, uint8_t n, uint8_t step); -void DSP2_MISC_M2N_Disable(void); - -/*@} end of group DSP2_MISC_Public_Functions */ - -/*@} end of group DSP2_MISC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_MISC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_wdr.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_wdr.h deleted file mode 100644 index 09e9fd92fb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dsp2_wdr.h +++ /dev/null @@ -1,121 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_wdr.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DSP2_WDR_H__ -#define __BL808_DSP2_WDR_H__ - -#include "bl808_common.h" -#include "bl808_dsp2.h" - -#define DSP2_WDR_HIST_BIN_NUM (65) -#define DSP2_WDR_CURVE_COEF_NUM (64) - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_WDR - * @{ - */ - -/** @defgroup DSP2_WDR_Public_Types - * @{ - */ - -/** - * @brief WDR hist data struct definition - */ -typedef struct -{ - uint32_t hist_bin[DSP2_WDR_HIST_BIN_NUM]; -} DSP2_WDR_Hist_Data_Type; - -/** - * @brief WDR curve strcut definition - */ -typedef struct -{ - uint16_t curve_coef[DSP2_WDR_CURVE_COEF_NUM]; -} DSP2_WDR_Curve_Type; - -/*@} end of group DSP2_WDR_Public_Types */ - -/** @defgroup DSP2_WDR_Public_Constants - * @{ - */ - -/*@} end of group DSP2_WDR_Public_Constants */ - -/** @defgroup DSP2_WDR_Public_Macros - * @{ - */ - -/*@} end of group DSP2_WDR_Public_Macros */ - -/** @defgroup DSP2_WDR_Public_Functions - * @{ - */ -void DSP2_WDR_Get_WDR_State(BL_Fun_Type *state); -void DSP2_WDR_Set_WDR_State(BL_Fun_Type state); -void DSP2_WDR_Set_CS_State(BL_Fun_Type state); -void DSP2_WDR_Set_CS_Config(const DSP2_Chroma_Suppress_Type *chromaSupprCfg); -void DSP2_WDR_Get_CS_Config(DSP2_Chroma_Suppress_Type *chromaSupprCfg); -void DSP2_WDR_Set_ROI_State(int roi_id, BL_Fun_Type state); -void DSP2_WDR_Set_ROI_Position(int roi_id, uint32_t left_x, uint32_t right_x, - uint32_t top_y, uint32_t bottom_y); -void DSP2_WDR_Set_ROI_Weight(int roi_id, uint32_t weight); -int DSP2_WDR_Get_Hist_Data(DSP2_WDR_Hist_Data_Type *hist); -void DSP2_WDR_Set_WDR_Curve_State(BL_Fun_Type state); -void DSP2_WDR_Set_WDR_Curve(const DSP2_WDR_Curve_Type *wdr_curve); -void DSP2_WDR_Get_WDR_Curve(DSP2_WDR_Curve_Type *wdr_curve); -void DSP2_WDR_Set_WDR_Curve_Weight(uint32_t weight); -void DSP2_WDR_Get_WDR_Curve_Weight(uint32_t *weight); -void DSP2_WDR_Set_Post_Enhance_State(BL_Fun_Type state); -void DSP2_WDR_Set_Post_Enhance_Weight(uint32_t weight); -void DSP2_WDR_Get_Post_Enhance_Weight(uint32_t *weight); -void DSP2_WDR_Set_Post_Enhance_Y_Offset(uint32_t y_offset); -void DSP2_WDR_Get_Post_Enhance_Y_Offset(uint32_t *y_offset); -void DSP2_WDR_Set_Post_Enhance_Luma_Gain(uint32_t gain); -void DSP2_WDR_Get_Post_Enhance_Luma_Gain(uint32_t *gain); -void DSP2_WDR_Set_Post_Enhance_Chroma_Gain(uint32_t gain); -void DSP2_WDR_Get_Post_Enhance_Chroma_Gain(uint32_t *gain); - -/*@} end of group DSP2_WDR_Public_Functions */ - -/*@} end of group DSP2_WDR */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DSP2_WDR_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dvp_tsrc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dvp_tsrc.h deleted file mode 100644 index 8fbf07e27c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_dvp_tsrc.h +++ /dev/null @@ -1,255 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dvp_tsrc.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_DVP_TSRC_H__ -#define __BL808_DVP_TSRC_H__ - -#include "dtsrc_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DVP_TSRC - * @{ - */ - -/** @defgroup DVP_TSRC_Public_Types - * @{ - */ - -/** - * @brief DVP_TSRC port type definition - */ -typedef enum { - DVP_TSRC0_ID, /*!< DVP TSRC0 port define */ - DVP_TSRC1_ID, /*!< DVP TSRC1 port define */ - DVP_TSRC_ID_MAX, /*!< DVP TSRC MAX ID define */ -} DVP_TSRC_ID_Type; - -/** - * @brief YUV420 valid line select type definition - */ -typedef enum { - DVP_TSRC_YUV420_LINE_EVEN, /*!< The even lines are valid, UV will send in Y even lines */ - DVP_TSRC_YUV420_LINE_ODD, /*!< The odd lines are valid, UV will send in Y odd lines */ -} DVP_TSRC_YUV420_Line_Type; - -/** - * @brief DVP_TSRC swap mode DVP2AXI type definition - */ -typedef enum { - DVP_TSRC_DVP2AXI_0, /*!< Choose DVP2AXI 0 */ - DVP_TSRC_DVP2AXI_1, /*!< Choose DVP2AXI 1 */ - DVP_TSRC_DVP2AXI_2, /*!< Choose DVP2AXI 2 */ - DVP_TSRC_DVP2AXI_3, /*!< Choose DVP2AXI 3 */ - DVP_TSRC_DVP2AXI_4, /*!< Choose DVP2AXI 4 */ - DVP_TSRC_DVP2AXI_5, /*!< Choose DVP2AXI 5 */ - DVP_TSRC_DVP2AXI_6, /*!< Choose DVP2AXI 6 */ - DVP_TSRC_DVP2AXI_7, /*!< Choose DVP2AXI 7 */ - DVP_TSRC_MJDEC_YY, /*!< Choose MJDEC YY */ - DVP_TSRC_MJDEC_UV, /*!< Choose MJDEC UV */ -} DVP_TSRC_DVP2AXI_Type; - -/** - * @brief DVP_TSRC swap index control mode type definition - */ -typedef enum { - DVP_TSRC_SWAP_HARDWARE, /*!< Swap index is controlled by hardware */ - DVP_TSRC_SWAP_SOFTWARE, /*!< Swap index is controlled by software */ -} DVP_TSRC_Swap_Control_Type; - -/** - * @brief DVP_TSRC pixel format type definition - */ -typedef enum { - DVP_TSRC_PIXEL_YUV422_16BIT, /*!< YUV422 16-bit mode */ - DVP_TSRC_PIXEL_RGB888_24BIT, /*!< RGB888 24-bit mode */ - DVP_TSRC_PIXEL_RGB565_16TO24BIT, /*!< RGB565 16-bit extend 24-bit mode */ - DVP_TSRC_PIXEL_RGBA8888_32TO24BIT, /*!< RGBA8888 32-bit compress 24-bit mode */ - DVP_TSRC_PIXEL_YUV400_8BIT, /*!< YUV400 8-bit mode */ -} DVP_TSRC_Pixel_Format_Type; - -/** - * @brief DVP_TSRC AXI burst type definition - */ -typedef enum { - DVP_TSRC_BURST_TYPE_SINGLE, /*!< DVP_TSRC AXI burst type:single */ - DVP_TSRC_BURST_TYPE_INCR4, /*!< DVP_TSRC AXI burst type:incrementing 4 */ - DVP_TSRC_BURST_TYPE_INCR8, /*!< DVP_TSRC AXI burst type:incrementing 8 */ - DVP_TSRC_BURST_TYPE_INCR16, /*!< DVP_TSRC AXI burst type:incrementing 16 */ - DVP_TSRC_BURST_TYPE_INCR32 = 5, /*!< DVP_TSRC AXI burst type:incrementing 32 */ - DVP_TSRC_BURST_TYPE_INCR64, /*!< DVP_TSRC AXI burst type:incrementing 64 */ -} DVP_TSRC_Burst_Type; - -/** - * @brief DVP_TSRC configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type dataFromSensor; /*!< Enable: pixel data is from sensor, disable: pixel data is from AXI */ - BL_Fun_Type sensorHsyncInverse; /*!< Enable or disable inverse signal of sensor hsync */ - BL_Fun_Type sensorVsyncInverse; /*!< Enable or disable inverse signal of sensor vsync */ - BL_Fun_Type yuv420Enable; /*!< Enable or disable YUV420 mode, YUV420 data is from 2 different planar buffers when enable */ - DVP_TSRC_YUV420_Line_Type lineType; /*!< Select UV send in Y even lines or odd lines */ - BL_Fun_Type swapMode; /*!< Enable or disable swap mode */ - DVP_TSRC_Swap_Control_Type swapControl; /*!< Set swap index controlled by hardware or software */ - DVP_TSRC_DVP2AXI_Type dvp2axi; /*!< Choose dvp2axi used */ - DVP_TSRC_Pixel_Format_Type format; /*!< Set pixel data format */ - DVP_TSRC_Burst_Type burst; /*!< AXI burst length */ - uint8_t byte0; /*!< Byte 0 selection */ - uint8_t byte1; /*!< Byte 1 Selection */ - uint8_t byte2; /*!< Byte 2 Selection */ - uint16_t hTotalCnt; /*!< Horizontal total pixel count */ - uint16_t hBlankCnt; /*!< Horizontal blank stage pixel count */ - uint16_t vTotalCnt; /*!< Vertical total pixel count */ - uint16_t vBlankCnt; /*!< Vertical blank stage pixel count */ - uint16_t prefetch; /*!< Vertical prefetch start position, relativeto blank start position */ - uint16_t fifoThreshold; /*!< FIFO threshold for each DVP line to start to output */ - uint32_t memStartY0; /*!< AXI2DVP start address, Y-planar in YUV420 mode, frame 0 in swap mode */ - uint32_t memSizeY0; /*!< AXI2DVP memory size of memStartY0 */ - uint32_t memStartY1; /*!< AXI2DVP start address, Y-planar in YUV420 mode, frame 1 in swap mode, don't care if not swap mode */ - uint32_t memStartUV0; /*!< AXI2DVP start address, UV-planar in YUV420 mode, frame 0 in swap mode, don't care if not YUV420 mode */ - uint32_t memStartUV1; /*!< AXI2DVP start address, UV-planar in YUV420 mode, frame 1 in swap mode, don't care if not YUV420 swap mode */ -} DVP_TSRC_Cfg_Type; - -/** - * @brief DVP_TSRC fake gradient data configuration structure type definition - */ -typedef struct -{ - uint16_t minData; /*!< Minimum data value of fake gradient data */ - uint16_t maxData; /*!< Maximum data value of fake gradient data */ - uint8_t step; /*!< Data step value for eack line of fake gradient data */ -} DVP_TSRC_Fake_Data_Cfg_Type; - -/** - * @brief DVP_TSRC CEA-861 configuration structure type definition - */ -typedef struct -{ - uint8_t hsyncStart; /*!< Hsync start position, relative to blank start position */ - uint8_t hsyncEnd; /*!< Hsync end position, relative to blank start position */ - uint8_t vsyncStart; /*!< Vsync start position, relative to blank start position */ - uint8_t vsyncEnd; /*!< Vsync end position, relative to blank start position */ -} DVP_TSRC_CEA861_Cfg_Type; - -/*@} end of group DVP_TSRC_Public_Types */ - -/** @defgroup DVP_TSRC_Public_Constants - * @{ - */ - -/** @defgroup DVP_TSRC_ID_TYPE - * @{ - */ -#define IS_DVP_TSRC_ID_TYPE(type) (((type) == DVP_TSRC0_ID) || \ - ((type) == DVP_TSRC1_ID) || \ - ((type) == DVP_TSRC_ID_MAX)) - -/** @defgroup DVP_TSRC_YUV420_LINE_TYPE - * @{ - */ -#define IS_DVP_TSRC_YUV420_LINE_TYPE(type) (((type) == DVP_TSRC_YUV420_LINE_EVEN) || \ - ((type) == DVP_TSRC_YUV420_LINE_ODD)) - -/** @defgroup DVP_TSRC_DVP2AXI_TYPE - * @{ - */ -#define IS_DVP_TSRC_DVP2AXI_TYPE(type) (((type) == DVP_TSRC_DVP2AXI_0) || \ - ((type) == DVP_TSRC_DVP2AXI_1) || \ - ((type) == DVP_TSRC_DVP2AXI_2) || \ - ((type) == DVP_TSRC_DVP2AXI_3) || \ - ((type) == DVP_TSRC_DVP2AXI_4) || \ - ((type) == DVP_TSRC_DVP2AXI_5) || \ - ((type) == DVP_TSRC_DVP2AXI_6) || \ - ((type) == DVP_TSRC_DVP2AXI_7) || \ - ((type) == DVP_TSRC_MJDEC_YY) || \ - ((type) == DVP_TSRC_MJDEC_UV)) - -/** @defgroup DVP_TSRC_SWAP_CONTROL_TYPE - * @{ - */ -#define IS_DVP_TSRC_SWAP_CONTROL_TYPE(type) (((type) == DVP_TSRC_SWAP_HARDWARE) || \ - ((type) == DVP_TSRC_SWAP_SOFTWARE)) - -/** @defgroup DVP_TSRC_PIXEL_FORMAT_TYPE - * @{ - */ -#define IS_DVP_TSRC_PIXEL_FORMAT_TYPE(type) (((type) == DVP_TSRC_PIXEL_YUV422_16BIT) || \ - ((type) == DVP_TSRC_PIXEL_RGB888_24BIT) || \ - ((type) == DVP_TSRC_PIXEL_RGB565_16TO24BIT) || \ - ((type) == DVP_TSRC_PIXEL_RGBA8888_32TO24BIT) || \ - ((type) == DVP_TSRC_PIXEL_YUV400_8BIT)) - -/** @defgroup DVP_TSRC_BURST_TYPE - * @{ - */ -#define IS_DVP_TSRC_BURST_TYPE(type) (((type) == DVP_TSRC_BURST_TYPE_SINGLE) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR4) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR8) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR16) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR32) || \ - ((type) == DVP_TSRC_BURST_TYPE_INCR64)) - -/*@} end of group DVP_TSRC_Public_Constants */ - -/** @defgroup DVP_TSRC_Public_Macros - * @{ - */ - -/*@} end of group DVP_TSRC_Public_Macros */ - -/** @defgroup DVP_TSRC_Public_Functions - * @{ - */ -BL_Err_Type DVP_TSRC_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Cfg_Type *dvpTsrcCfg); -void DVP_TSRC_Fake_Data_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Fake_Data_Cfg_Type *dataCfg); -void DVP_TSRC_CEA861_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_CEA861_Cfg_Type *ceaCfg); -void DVP_TSRC_Sensor_Input_Set(DVP_TSRC_ID_Type tsrcId, uint16_t threshold, BL_Fun_Type hsyncInv, BL_Fun_Type vsyncInv); -void DVP_TSRC_Enable(DVP_TSRC_ID_Type tsrcId); -void DVP_TSRC_Disable(DVP_TSRC_ID_Type tsrcId); -void DVP_TSRC_Set_Swap_Index(DVP_TSRC_ID_Type tsrcId, uint8_t index); -void DVP_TSRC_Clear_Drain_Error(DVP_TSRC_ID_Type tsrcId); -uint32_t DVP_TSRC_Get_Status(DVP_TSRC_ID_Type tsrcId); - -/*@} end of group DVP_TSRC_Public_Functions */ - -/*@} end of group DVP_TSRC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_DVP_TSRC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_cfg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_cfg.h deleted file mode 100644 index 8fc0e24916..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_cfg.h +++ /dev/null @@ -1,238 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ef_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_EF_CFG_H__ -#define __BL808_EF_CFG_H__ - -#include "ef_ctrl_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup EF_CTRL - * @{ - */ - -/** @defgroup EF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Efuse analog device info type definition - */ -typedef struct -{ - uint8_t chipInfo; /*!< Efuse chip revision */ - uint8_t memoryInfo; /*!< Efuse memory info 0:no memory, 8:1MB flash */ - uint8_t psramInfo; /*!< Efuse psram info 0:no psram, 1:BW 4MB, 2:UHS 64MB */ - uint8_t deviceInfo; /*!< Efuse device information */ -} Efuse_Chip_Info_Type; - -/** - * @brief Efuse analog ldo15rf vout sel aon type definition - */ -typedef struct -{ - uint32_t trimLDO15RFVoutAon : 3; /*!< Efuse analog trim:ldo15rf_vout_sel_aon */ - uint32_t trimLDO15RFVoutAonParity : 1; /*!< Efuse analog trim:ldo15rf_vout_sel_aon_parity */ - uint32_t trimLDO15RFVoutAonEn : 1; /*!< Efuse analog trim:ldo15rf_vout_sel_aon_en */ - uint32_t reserved : 27; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO15RF_Vout_Sel_Type; - -/** - * @brief Efuse analog rcal iptat code type definition - */ -typedef struct -{ - uint32_t trimRcalIptatCode : 5; /*!< Efuse analog trim:rcal_iptat_code */ - uint32_t trimRcalIptatCodeParity : 1; /*!< Efuse analog trim:rcal_iptat_code_parity */ - uint32_t trimRcalIptatCodeEn : 1; /*!< Efuse analog trim:rcal_iptat_code_en */ - uint32_t reserved : 25; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Rcal_Iptat_Code_Type; - -/** - * @brief Efuse analog rcal icx code type definition - */ -typedef struct -{ - uint32_t trimRcalIcxCode : 6; /*!< Efuse analog trim:rcal_icx_code */ - uint32_t trimRcalIcxCodeParity : 1; /*!< Efuse analog trim:rcal_icx_code_parity */ - uint32_t trimRcalIcxCodeEn : 1; /*!< Efuse analog trim:rcal_icx_code_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Rcal_Icx_Code_Type; - -/** - * @brief Efuse analog LDO28CIS vout trim type definition - */ -typedef struct -{ - uint32_t trimLDO28CISVout : 4; /*!< Efuse analog trim:ldo28cis_vout_trim */ - uint32_t trimLDO28CISVoutParity : 1; /*!< Efuse analog trim:ldo28cis_vout_trim_parity */ - uint32_t trimLDO28CISVoutEn : 1; /*!< Efuse analog trim:ldo28cis_vout_trim_en */ - uint32_t reserved : 26; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO28CIS_Vout_Trim_Type; - -/** - * @brief Efuse analog LDO15CIS vout trim type definition - */ -typedef struct -{ - uint32_t trimLDO15CISVout : 4; /*!< Efuse analog trim:ldo15cis_vout_trim */ - uint32_t trimLDO15CISVoutParity : 1; /*!< Efuse analog trim:ldo15cis_vout_trim_parity */ - uint32_t trimLDO15CISVoutEn : 1; /*!< Efuse analog trim:ldo15cis_vout_trim_en */ - uint32_t reserved : 26; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO15CIS_Vout_Trim_Type; - -/** - * @brief Efuse analog LDO12UHS vout trim type definition - */ -typedef struct -{ - uint32_t trimLDO12UHSVout : 4; /*!< Efuse analog trim:ldo12uhs_vout_trim */ - uint32_t trimLDO12UHSVoutParity : 1; /*!< Efuse analog trim:ldo12uhs_vout_trim_parity */ - uint32_t trimLDO12UHSVoutEn : 1; /*!< Efuse analog trim:ldo12uhs_vout_trim_en */ - uint32_t reserved : 26; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_LDO12UHS_Vout_Trim_Type; - -/** - * @brief Efuse analog xtal capcode 1 inout type definition - */ -typedef struct -{ - uint32_t trimXtalCapcode1 : 6; /*!< Efuse analog trim:ctal_capcode_1_inout */ - uint32_t trimXtalCapcode1Parity : 1; /*!< Efuse analog trim:ctal_capcode_1_inout_parity */ - uint32_t trimXtalCapcode1En : 1; /*!< Efuse analog trim:ctal_capcode_1_inout_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Xtal_Capcode_1_Type; - -/** - * @brief Efuse analog xtal capcode 2 inout type definition - */ -typedef struct -{ - uint32_t trimXtalCapcode2 : 6; /*!< Efuse analog trim:ctal_capcode_2_inout */ - uint32_t trimXtalCapcode2Parity : 1; /*!< Efuse analog trim:ctal_capcode_2_inout_parity */ - uint32_t trimXtalCapcode2En : 1; /*!< Efuse analog trim:ctal_capcode_2_inout_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Xtal_Capcode_2_Type; - -/** - * @brief Efuse analog xtal capcode 3 inout type definition - */ -typedef struct -{ - uint32_t trimXtalCapcode3 : 6; /*!< Efuse analog trim:ctal_capcode_3_inout */ - uint32_t trimXtalCapcode3Parity : 1; /*!< Efuse analog trim:ctal_capcode_3_inout_parity */ - uint32_t trimXtalCapcode3En : 1; /*!< Efuse analog trim:ctal_capcode_3_inout_en */ - uint32_t reserved : 24; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Xtal_Capcode_3_Type; - -/** - * @brief Efuse analog gauge vpack offset type definition - */ -typedef struct -{ - uint32_t trimGaugeVpackOffset : 16; /*!< Efuse analog trim:gauge_vpack_offset */ - uint32_t trimGaugeVpackOffsetParity : 1; /*!< Efuse analog trim:gauge_vpack_offset_parity */ - uint32_t trimGaugeVpackOffsetEn : 1; /*!< Efuse analog trim:gauge_vpack_offset_en */ - uint32_t reserved : 14; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Gauge_Vpack_Offset_Type; - -/** - * @brief Efuse analog gauge vtemp offset type definition - */ -typedef struct -{ - uint32_t trimGaugeVtempOffset : 16; /*!< Efuse analog trim:gauge_vtemp_offset */ - uint32_t trimGaugeVtempOffsetParity : 1; /*!< Efuse analog trim:gauge_vtemp_offset_parity */ - uint32_t trimGaugeVtempOffsetEn : 1; /*!< Efuse analog trim:gauge_vtemp_offset_en */ - uint32_t reserved : 14; /*!< Efuse analog trim:reserved */ -} Efuse_Ana_Gauge_Vtemp_Offset_Type; - -/** - * @brief Efuse psram trim type definition - */ -typedef struct -{ - uint32_t psramTrim : 11; /*!< Efuse analog trim:psram trim date */ - uint32_t psramTrimParity : 1; /*!< Efuse analog trim:psram trim_parity */ - uint32_t psramTrimEn : 1; /*!< Efuse analog trim:psram trim_en */ - uint32_t reserved : 19; /*!< Efuse analog trim:reserved */ -} Efuse_Psram_Trim_Type; - -/*@} end of group EF_CTRL_Public_Types */ - -/** @defgroup EF_CTRL_Public_Constants - * @{ - */ - -/*@} end of group EF_CTRL_Public_Constants */ - -/** @defgroup EF_CTRL_Public_Macros - * @{ - */ - -/*@} end of group EF_CTRL_Public_Macros */ - -/** @defgroup EF_CTRL_Public_Functions - * @{ - */ -void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo); -void EF_Ctrl_Read_LDO15RF_Vout_Sel(Efuse_Ana_LDO15RF_Vout_Sel_Type *trim); -void EF_Ctrl_Read_Rcal_Iptat_Code(Efuse_Ana_Rcal_Iptat_Code_Type *trim); -void EF_Ctrl_Read_Rcal_Icx_Code(Efuse_Ana_Rcal_Icx_Code_Type *trim); -void EF_Ctrl_Read_LDO28CIS_Vout_Trim(Efuse_Ana_LDO28CIS_Vout_Trim_Type *trim); -void EF_Ctrl_Read_LDO15CIS_Vout_Trim(Efuse_Ana_LDO15CIS_Vout_Trim_Type *trim); -void EF_Ctrl_Read_LDO12UHS_Vout_Trim(Efuse_Ana_LDO12UHS_Vout_Trim_Type *trim); -void EF_Ctrl_Read_Xtal_Capcode1_Inout(Efuse_Ana_Xtal_Capcode_1_Type *trim); -void EF_Ctrl_Read_Xtal_Capcode2_Inout(Efuse_Ana_Xtal_Capcode_2_Type *trim); -void EF_Ctrl_Read_Xtal_Capcode3_Inout(Efuse_Ana_Xtal_Capcode_3_Type *trim); -void EF_Ctrl_Read_Gauge_Vpack_Offset(Efuse_Ana_Gauge_Vpack_Offset_Type *trim); -void EF_Ctrl_Read_Gauge_Vtemp_Offset(Efuse_Ana_Gauge_Vtemp_Offset_Type *trim); -void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim); -void EF_Ctrl_Write_Psram_Trim(Efuse_Psram_Trim_Type *trim, uint8_t program); -uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload); -BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program); -BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload); - -/*@} end of group EF_CTRL_Public_Functions */ - -/*@} end of group EF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_EF_CFG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_emac.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_emac.h deleted file mode 100644 index 38fdb8aac3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_emac.h +++ /dev/null @@ -1,360 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_emac.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_EMAC_H__ -#define __BL808_EMAC_H__ - -#include "emac_reg.h" -#include "bl808_common.h" - - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup EMAC - * @{ - */ - -/** @defgroup EMAC_Public_Types - * @{ - */ - -typedef enum { - EMAC0_ID, /*!< EMAC0 port define */ - EMAC_ID_MAX, /*!< I2S MAX ID define */ -} EMAC_ID_Type; - -/** - * @brief EMAC half/full-duplex type definition - */ -typedef enum { - EMAC_MODE_HALFDUPLEX, /*!< ETH half-duplex */ - EMAC_MODE_FULLDUPLEX, /*!< ETH full-duplex */ -} EMAC_Duplex_Type; - -/** - * @brief EMAC speed type definition - */ -typedef enum { - EMAC_SPEED_10M, /*!< ETH speed 10M */ - EMAC_SPEED_100M, /*!< ETH speed 100M */ -} EMAC_Speed_Type; - -/** - * @brief EMAC interrupt type definition - */ -typedef enum { - EMAC_INT_TX_DONE = 0x01, /*!< Transmit one frame done */ - EMAC_INT_TX_ERROR = 0x02, /*!< Transmit error occur */ - EMAC_INT_RX_DONE = 0x04, /*!< Receive one frame done */ - EMAC_INT_RX_ERROR = 0x08, /*!< Receive error occur */ - EMAC_INT_RX_BUSY = 0x10, /*!< Receive busy due to no free RX buffer Descripter */ - EMAC_INT_TX_CTRL = 0x20, /*!< Transmit control frame */ - EMAC_INT_RX_CTRL = 0x40, /*!< Receive control frame */ - EMAC_INT_ALL = 0x7F, /*!< */ -} EMAC_INT_Type; - -/** - * @brief EMAC interrupt Index - */ -typedef enum { - EMAC_INT_TX_DONE_IDX = 0x0, /*!< Transmit one frame done */ - EMAC_INT_TX_ERROR_IDX = 0x1, /*!< Transmit error occur */ - EMAC_INT_RX_DONE_IDX = 0x2, /*!< Receive one frame done */ - EMAC_INT_RX_ERROR_IDX = 0x3, /*!< Receive error occur */ - EMAC_INT_RX_BUSY_IDX = 0x4, /*!< Receive busy due to no free RX buffer Descripter */ - EMAC_INT_TX_CTRL_IDX = 0x5, /*!< Transmit control frame */ - EMAC_INT_RX_CTRL_IDX = 0x6, /*!< Receive control frame */ - EMAC_INT_CNT, /*!< EMAC INT source count */ -} EMAC_INT_Index; - -/** - * @brief EMAC configuration type definition - */ -typedef struct -{ - BL_Fun_Type recvSmallFrame; /*!< Receive small frmae or not */ - BL_Fun_Type recvHugeFrame; /*!< Receive huge frmae(>64K bytes) or not */ - BL_Fun_Type padEnable; /*!< Enable padding for frame which is less than MINFL or not */ - BL_Fun_Type crcEnable; /*!< Enable hardware CRC or not */ - BL_Fun_Type noPreamble; /*!< Enable preamble or not */ - BL_Fun_Type recvBroadCast; /*!< Receive broadcast frame or not */ - BL_Fun_Type interFrameGapCheck; /*!< Check inter frame gap or not */ - BL_Fun_Type miiNoPreamble; /*!< Enable MII interface preamble or not */ - uint8_t miiClkDiv; /*!< MII interface clock divider from bus clock */ - uint8_t maxTxRetry; /*!< Maximum tx retry count */ - uint16_t interFrameGapValue; /*!< Inter frame gap vaule in clock cycles(default 24),which equals 9.6 us for 10 Mbps and 0.96 us - for 100 Mbps mode */ - uint16_t minFrameLen; /*!< Minimum frame length */ - uint16_t maxFrameLen; /*!< Maximum frame length */ - uint16_t collisionValid; /*!< Collision valid value */ - uint8_t macAddr[6]; /*!< MAC Address */ -} EMAC_CFG_Type; - - -/** - * @brief EMAC TX DMA description type definition - */ -typedef struct -{ - uint32_t CS : 1; /*!< Carrier Sense Lost */ - uint32_t DF : 1; /*!< Defer Indication */ - uint32_t LC : 1; /*!< Late Collision */ - uint32_t RL : 1; /*!< Retransmission Limit */ - uint32_t RC : 4; /*!< Retry Count */ - uint32_t UR : 1; /*!< Underrun */ - uint32_t RSVD : 1; /*!< Reserved */ - uint32_t EoF : 1; /*!< EOF or not */ - uint32_t CRC : 1; /*!< CRC Enable */ - uint32_t PAD : 1; /*!< PAD enable */ - uint32_t WR : 1; /*!< Wrap */ - uint32_t IRQ : 1; /*!< Interrupt Request Enable */ - uint32_t Busy : 1; /*!< The data buffer is ready for transmission or is currently being transmitted. You are not - allowed to change it */ - uint32_t TxLen : 16; /*!< TX Data buffer length */ - uint32_t TXBuffer; /*!< TX buffer address */ -} EMAC_Tx_DMA_Desc_Type; - -/** - * @brief EMAC RX DMA description type definition - */ -typedef struct -{ - uint32_t LC : 1; /*!< Late Collision */ - uint32_t CRC : 1; /*!< RX CRC Error */ - uint32_t SF : 1; /*!< Short Frame */ - uint32_t TL : 1; /*!< Too Long */ - uint32_t DN : 4; /*!< Dribble Nibble */ - uint32_t RE : 1; /*!< Receive Error */ - uint32_t OR : 1; /*!< Overrun */ - uint32_t M : 1; /*!< Miss */ - uint32_t CF : 1; /*!< Control Frame */ - uint32_t RSVD : 4; /*!< PAD enable */ - uint32_t WR : 1; /*!< Wrap */ - uint32_t IRQ : 1; /*!< Interrupt Request Enable */ - uint32_t Empty : 1; /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */ - uint32_t RxLen : 16; /*!< RX Data buffer length */ - uint32_t RXBuffer; /*!< RX buffer address */ -} EMAC_Rx_DMA_Desc_Type; - -/** - * @brief Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern. - */ -typedef struct -{ - uint32_t C_S_L; /*!< Buffer Descriptors(BD) control,status,length */ - uint32_t Buffer; /*!< BD buffer address */ -} EMAC_BD_Desc_Type; - -/** - * @brief EMAC Handle type definition - */ -typedef struct -{ - EMAC_BD_Desc_Type *bd; /*!< Tx descriptor header pointer */ - uint8_t txIndexEMAC; /*!< TX index: EMAC */ - uint8_t txIndexCPU; /*!< TX index: CPU/SW */ - uint8_t txBuffLimit; /*!< TX index max */ - uint8_t rsv0; /*!< RSV0 */ - uint8_t rxIndexEMAC; /*!< RX index: EMAC */ - uint8_t rxIndexCPU; /*!< RX index: CPU/SW */ - uint8_t rxBuffLimit; /*!< RX index max */ - uint8_t rsv1; /*!< rsv1 */ -} EMAC_Handle_Type; - -/*@} end of group EMAC_Public_Types */ - -/** @defgroup EMAC_Public_Constants - * @{ - */ - -/** @defgroup EMAC_ID_TYPE - * @{ - */ -#define IS_EMAC_ID_TYPE(type) (((type) == EMAC0_ID) || \ - ((type) == EMAC_ID_MAX)) - -/** @defgroup EMAC_DUPLEX_TYPE - * @{ - */ -#define IS_EMAC_DUPLEX_TYPE(type) (((type) == EMAC_MODE_HALFDUPLEX) || \ - ((type) == EMAC_MODE_FULLDUPLEX)) - -/** @defgroup EMAC_SPEED_TYPE - * @{ - */ -#define IS_EMAC_SPEED_TYPE(type) (((type) == EMAC_SPEED_10M) || \ - ((type) == EMAC_SPEED_100M)) - -/** @defgroup EMAC_INT_TYPE - * @{ - */ -#define IS_EMAC_INT_TYPE(type) (((type) == EMAC_INT_TX_DONE) || \ - ((type) == EMAC_INT_TX_ERROR) || \ - ((type) == EMAC_INT_RX_DONE) || \ - ((type) == EMAC_INT_RX_ERROR) || \ - ((type) == EMAC_INT_RX_BUSY) || \ - ((type) == EMAC_INT_TX_CTRL) || \ - ((type) == EMAC_INT_RX_CTRL) || \ - ((type) == EMAC_INT_ALL)) - -/** @defgroup EMAC_INT_INDEX - * @{ - */ -#define IS_EMAC_INT_INDEX(type) (((type) == EMAC_INT_TX_DONE_IDX) || \ - ((type) == EMAC_INT_TX_ERROR_IDX) || \ - ((type) == EMAC_INT_RX_DONE_IDX) || \ - ((type) == EMAC_INT_RX_ERROR_IDX) || \ - ((type) == EMAC_INT_RX_BUSY_IDX) || \ - ((type) == EMAC_INT_TX_CTRL_IDX) || \ - ((type) == EMAC_INT_RX_CTRL_IDX) || \ - ((type) == EMAC_INT_CNT)) - -/*@} end of group EMAC_Public_Constants */ - -/** @defgroup EMAC_Public_Macros - * @{ - */ -#define BD_TX_CS_POS (0) /*!< Carrier Sense Lost */ -#define BD_TX_CS_LEN (1) -#define BD_TX_DF_POS (1) /*!< Defer Indication */ -#define BD_TX_DF_LEN (1) -#define BD_TX_LC_POS (2) /*!< Late Collision */ -#define BD_TX_LC_LEN (1) -#define BD_TX_RL_POS (3) /*!< Retransmission Limit */ -#define BD_TX_RL_LEN (1) -#define BD_TX_RTRY_POS (4) /*!< Retry Count */ -#define BD_TX_RTRY_LEN (4) -#define BD_TX_UR_POS (8) /*!< Underrun */ -#define BD_TX_UR_LEN (1) -#define BD_TX_EOF_POS (10) /*!< EOF */ -#define BD_TX_EOF_LEN (1) -#define BD_TX_CRC_POS (11) /*!< CRC Enable */ -#define BD_TX_CRC_LEN (1) -#define BD_TX_PAD_POS (12) /*!< PAD enable */ -#define BD_TX_PAD_LEN (1) -#define BD_TX_WR_POS (13) /*!< Wrap */ -#define BD_TX_WR_LEN (1) -#define BD_TX_IRQ_POS (14) /*!< Interrupt Request Enable */ -#define BD_TX_IRQ_LEN (1) -#define BD_TX_RD_POS (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */ -#define BD_TX_RD_LEN (1) -#define BD_TX_LEN_POS (16) /*!< TX Data buffer length */ -#define BD_TX_LEN_LEN (16) -#define BD_RX_LC_POS (0) /*!< Late Collision */ -#define BD_RX_LC_LEN (1) -#define BD_RX_CRC_POS (1) /*!< RX CRC Error */ -#define BD_RX_CRC_LEN (1) -#define BD_RX_SF_POS (2) /*!< Short Frame */ -#define BD_RX_SF_LEN (1) -#define BD_RX_TL_POS (3) /*!< Too Long */ -#define BD_RX_TL_LEN (1) -#define BD_RX_DN_POS (4) /*!< Dribble Nibble */ -#define BD_RX_DN_LEN (1) -#define BD_RX_RE_POS (5) /*!< Receive Error */ -#define BD_RX_RE_LEN (1) -#define BD_RX_OR_POS (6) /*!< Overrun */ -#define BD_RX_OR_LEN (1) -#define BD_RX_M_POS (7) /*!< Miss */ -#define BD_RX_M_LEN (1) -#define BD_RX_CF_POS (8) /*!< Control Frame Received */ -#define BD_RX_CF_LEN (1) -#define BD_RX_WR_POS (13) /*!< Wrap */ -#define BD_RX_WR_LEN (1) -#define BD_RX_IRQ_POS (14) /*!< Interrupt Request Enable */ -#define BD_RX_IRQ_LEN (1) -#define BD_RX_E_POS (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */ -#define BD_RX_E_LEN (1) -#define BD_RX_LEN_POS (16) /*!< RX Data buffer length */ -#define BD_RX_LEN_LEN (16) -#define EMAC_BD_FIELD_MSK(field) (((1U << BD_##field##_LEN) - 1) << BD_##field##_POS) -#define EMAC_BD_FIELD_UMSK(field) (~(((1U << BD_##field##_LEN) - 1) << BD_##field##_POS)) -/* DMA Descriptor offset */ -#define EMAC_DMA_DESC_OFFSET 0x400 - -/* ETH packet size */ -// ETH | Header | Extra | VLAN tag | Payload | CRC | -// Size | 14 | 2 | 4 | 46 ~ 1500 | 4 | -#define ETH_MAX_PACKET_SIZE ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */ -#define ETH_HEADER_SZIE ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */ -#define ETH_CRC_SIZE ((uint32_t)4U) /*!< Ethernet CRC */ -#define ETH_EXTRA_SIZE ((uint32_t)2U) /*!< Extra bytes in some cases */ -#define ETH_VLAN_TAG_SIZE ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */ -#define ETH_MIN_ETH_PAYLOAD_SIZE ((uint32_t)46U) /*!< Minimum Ethernet payload size */ -#define ETH_MAX_ETH_PAYLOAD_SIZE ((uint32_t)1500U) /*!< Maximum Ethernet payload size */ -#define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) /*!< Jumbo frame payload size */ - -/*@} end of group EMAC_Public_Macros */ - -/** @defgroup EMAC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void EMAC_IRQHandler(EMAC_ID_Type emacId); -void EMAC0_IRQHandler(); -#endif -BL_Err_Type EMAC_Init(EMAC_ID_Type emacId, EMAC_CFG_Type *cfg); -BL_Err_Type EMAC_DeInit(EMAC_ID_Type emacId); -BL_Err_Type EMAC_DMADescListInit(EMAC_ID_Type emacId, EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, - uint8_t *rxBuff, uint32_t rxBuffCount); -BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc); -BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len); -BL_Err_Type EMAC_Enable(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Disable(EMAC_ID_Type emacId); -BL_Err_Type EMAC_IntMask(EMAC_ID_Type emacId, EMAC_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type EMAC_GetIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType); -BL_Err_Type EMAC_ClrIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType); -BL_Err_Type EMAC_Int_Callback_Install(EMAC_ID_Type emacId, EMAC_INT_Index intIdx, intCallback_Type *cbFun); -BL_Err_Type EMAC_TxPauseReq(EMAC_ID_Type emacId, uint16_t timeCount); -BL_Err_Type EMAC_SetHash(EMAC_ID_Type emacId, uint32_t hash0, uint32_t hash1); -BL_Err_Type EMAC_Phy_Read(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t *regValue); -BL_Err_Type EMAC_Phy_Write(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t regValue); -BL_Err_Type EMAC_Enable_TX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Disable_TX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Enable_RX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_Disable_RX(EMAC_ID_Type emacId); -BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min); -BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd); -void EMAC_Phy_SetAddress(EMAC_ID_Type emacId,uint16_t phyAddress); -void EMAC_Phy_Set_Full_Duplex(EMAC_ID_Type emacId,uint8_t fullDuplex); - -/*@} end of group EMAC_Public_Functions */ - -/*@} end of group EMAC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_EMAC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2c.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2c.h deleted file mode 100644 index ca897bd2ac..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2c.h +++ /dev/null @@ -1,210 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2c.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_I2C_H__ -#define __BL808_I2C_H__ - -#include "i2c_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Public_Types - * @{ - */ - -/** - * @brief I2C No. type definition - */ -typedef enum { - I2C0_ID = 0, /*!< I2C0 define */ - I2C1_ID = 1, /*!< I2C1 define */ - I2C0_MM_ID = 2, /*!< MM system I2C0 define */ - I2C1_MM_ID = 3, /*!< MM system I2C1 define */ - I2C_ID_MAX, /*!< I2C max define */ -} I2C_ID_Type; - -/** - * @brief I2C read/write type definition - */ -typedef enum { - I2C_WRITE = 0, /*!< I2C write direction */ - I2C_READ, /*!< I2C read direction */ -} I2C_Direction_Type; - -/** - * @brief I2C interrupt type definition - */ -typedef enum { - I2C_TRANS_END_INT, /*!< I2C transfer end interrupt */ - I2C_TX_FIFO_READY_INT, /*!< I2C TX fifo ready interrupt */ - I2C_RX_FIFO_READY_INT, /*!< I2C RX fifo ready interrupt */ - I2C_NACK_RECV_INT, /*!< I2C nack received interrupt */ - I2C_ARB_LOST_INT, /*!< I2C arbitration lost interrupt */ - I2C_FIFO_ERR_INT, /*!< I2C TX/RX FIFO error interrupt */ - I2C_INT_ALL, /*!< I2C interrupt all type */ -} I2C_INT_Type; - -/** - * @brief I2S start condition phase structure type definition - */ -typedef struct -{ - uint8_t len0; /*!< Length of START condition phase 0 */ - uint8_t len1; /*!< Length of START condition phase 1 */ - uint8_t len2; /*!< Length of START condition phase 2 */ - uint8_t len3; /*!< Length of START condition phase 3 */ -} I2C_Start_Condition_Phase_Type; - -/** - * @brief I2S stop condition phase structure type definition - */ -typedef struct -{ - uint8_t len0; /*!< Length of STOP condition phase 0 */ - uint8_t len1; /*!< Length of STOP condition phase 1 */ - uint8_t len2; /*!< Length of STOP condition phase 2 */ - uint8_t len3; /*!< Length of STOP condition phase 3 */ -} I2C_Stop_Condition_Phase_Type; - -/** - * @brief I2S data phase structure type definition - */ -typedef struct -{ - uint8_t len0; /*!< Length of DATA phase 0 */ - uint8_t len1; /*!< Length of DATA phase 1 */ - uint8_t len2; /*!< Length of DATA phase 2 */ - uint8_t len3; /*!< Length of DATA phase 3 */ -} I2C_Data_Phase_Type; - -/** - * @brief I2S transfer structure type definition - */ -typedef struct -{ - uint16_t slaveAddr; /*!< I2C slave address */ - BL_Fun_Type slaveAddr10Bit; /*!< Enable or disable slave address 10-bit mode */ - BL_Fun_Type stopEveryByte; /*!< I2C all data byte with stop bit */ - uint8_t subAddrSize; /*!< Specifies the size of I2C sub address section */ - uint32_t subAddr; /*!< I2C sub address */ - uint16_t dataSize; /*!< Specifies the size of I2C data section */ - uint8_t *data; /*!< Specifies the pointer of I2C R/W data */ - uint32_t clk; /*!< I2C clk:default is 400k */ -} I2C_Transfer_Cfg; - -/*@} end of group I2C_Public_Types */ - -/** @defgroup I2C_Public_Constants - * @{ - */ - -/** @defgroup I2C_ID_TYPE - * @{ - */ -#define IS_I2C_ID_TYPE(type) (((type) == I2C0_ID) || \ - ((type) == I2C1_ID) || \ - ((type) == I2C0_MM_ID) || \ - ((type) == I2C1_MM_ID) || \ - ((type) == I2C_ID_MAX)) - -/** @defgroup I2C_DIRECTION_TYPE - * @{ - */ -#define IS_I2C_DIRECTION_TYPE(type) (((type) == I2C_WRITE) || \ - ((type) == I2C_READ)) - -/** @defgroup I2C_INT_TYPE - * @{ - */ -#define IS_I2C_INT_TYPE(type) (((type) == I2C_TRANS_END_INT) || \ - ((type) == I2C_TX_FIFO_READY_INT) || \ - ((type) == I2C_RX_FIFO_READY_INT) || \ - ((type) == I2C_NACK_RECV_INT) || \ - ((type) == I2C_ARB_LOST_INT) || \ - ((type) == I2C_FIFO_ERR_INT) || \ - ((type) == I2C_INT_ALL)) - -/*@} end of group I2C_Public_Constants */ - -/** @defgroup I2C_Public_Macros - * @{ - */ - -/*@} end of group I2C_Public_Macros */ - -/** @defgroup I2C_Public_Functions - * @{ - */ - -/** - * @brief I2C Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void I2C0_IRQHandler(void); -void I2C1_IRQHandler(void); -void I2C2_IRQHandler(void); -void I2C3_IRQHandler(void); -#endif -BL_Err_Type I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data); -BL_Err_Type I2C_RecieveWord(I2C_ID_Type i2cNo, uint32_t *recvBuff); -void I2C_Enable(I2C_ID_Type i2cNo); -void I2C_Disable(I2C_ID_Type i2cNo); -BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt); -BL_Err_Type I2C_DeInit(I2C_ID_Type i2cNo); -void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase); -void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk); -void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable); -void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg); -BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo); -BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo); -BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); -BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg); -void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask); -void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group I2C_Public_Functions */ - -/*@} end of group I2C */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_I2C_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2s.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2s.h deleted file mode 100644 index 30d6e85d2d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_i2s.h +++ /dev/null @@ -1,309 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2s.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_I2S_H__ -#define __BL808_I2S_H__ - -#include "i2s_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2S - * @{ - */ - -/** @defgroup I2S_Public_Types - * @{ - */ - -/** - * @brief I2S mode type definition - */ -typedef enum { - I2S_MODE_I2S_LEFT, /*!< Left-Justified Mode */ - I2S_MODE_I2S_RIGHT, /*!< Right-Justified Mode */ - I2S_MODE_I2S_DSP, /*!< DSP Mode */ -} I2S_Mode_Type; - -typedef enum { - I2S0_ID, /*!< I2S0 port define */ - I2S_ID_MAX, /*!< I2S MAX ID define */ -} I2S_ID_Type; - -/** - * @brief I2S role type definition - */ -typedef enum { - I2S_ROLE_MASTER = 0, /*!< I2S as master */ - I2S_ROLE_SLAVE = 1, /*!< I2S as slave */ -} I2S_Role_Type; - -/** - * @brief I2S data size type definition - */ -typedef enum { - I2S_SIZE_DATA_8 = 0, /*!< I2S data size 8 bits */ - I2S_SIZE_DATA_16, /*!< I2S data size 16 bits */ - I2S_SIZE_DATA_24, /*!< I2S data size 24 bits */ - I2S_SIZE_DATA_32, /*!< I2S data size 32 bits */ -} I2S_Data_Size_Type; - -/** - * @brief I2S frame size type definition - */ -typedef enum { - I2S_SIZE_FRAME_8 = 0, /*!< I2S frame size 8 bits */ - I2S_SIZE_FRAME_16, /*!< I2S frame size 16 bits */ - I2S_SIZE_FRAME_24, /*!< I2S frame size 24 bits */ - I2S_SIZE_FRAME_32, /*!< I2S frame size 32 bits */ -} I2S_Frame_Size_Type; - -/** - * @brief I2S endian data type definition - */ -typedef enum { - I2S_DATA_ENDIAN_MSB = 0, /*!< I2S use MSB first */ - I2S_DATA_ENDIAN_LSB, /*!< I2S use LSB first */ -} I2S_Endian_Type; - -/** - * @brief I2S frame select mode type definition - */ -typedef enum { - I2S_FS_MODE_EVEN = 0, /*!< I2S frame is even */ - I2S_FS_MODE_1T, /*!< I2S frame is only 1T high */ -} I2S_Fs_Mode_Type; - -/** - * @brief I2S rx mono mode channel select type definition - */ -typedef enum { - I2S_RX_MONO_MODE_LEFT_CHANNEL, /*!< I2S rx mono mode left channel */ - I2S_RX_MONO_MODE_RIGHT_CHANNEL, /*!< I2S rx mono mode right channel */ -} I2S_Mono_Mode_Channel; - -/** - * @brief I2S frame channel mode type definition - */ -typedef enum { - I2S_FS_CHANNELS_2 = 0, /*!< I2S frame is for 2 channels */ - I2S_FS_CHANNELS_3, /*!< I2S frame is for 3 channels */ - I2S_FS_CHANNELS_4, /*!< I2S frame is for 4 channels */ - I2S_FS_CHANNELS_6, /*!< I2S frame is for 6 channels */ -} I2S_Fs_Channel_Type; - -/** - * @brief I2S mono control definition - */ -typedef enum { - I2S_MONO_CONTROL_STEREO = 0, /*!< I2S output stereo */ - I2S_MONO_CONTROL_MONO, /*!< I2S output mono */ -} I2S_MonoControl_Type; - -/** - * @brief I2S fifo 24-bit data align type definition - */ -typedef enum { - I2S_FIFO_24_RIGHT_JUSTIFIED = 0, /*!< I2S fifo:[31:24]0x00,[23:0]24bit_data */ - I2S_FIFO_24_LEFT_JUSTIFIED, /*!< I2S fifo:[31:8]24bit_data,[7:0]0x00 */ -} I2S_FIFO_24_Justified_Type; - -/** - * @brief I2S configuration structure type definition - */ -typedef struct -{ - I2S_Endian_Type endianType; /*!< I2S endian configuration */ - I2S_Mode_Type modeType; /*!< I2S mode configuration */ - uint32_t audioFreqHz; /*!< I2S audio pll output frequency in Hz */ - uint32_t sampleFreqHz; /*!< I2S sample data frequency in Hz */ - BL_Fun_Type bclkInvert; /*!< I2S bclk invert configuration */ - I2S_Frame_Size_Type frameSize; /*!< I2S frame size configuration */ - BL_Fun_Type fsInvert; /*!< I2S frame select invert configuration */ - I2S_Fs_Mode_Type fsMode; /*!< I2S frame mode configuration */ - I2S_Fs_Channel_Type fsChannel; /*!< I2S frame channels configuration */ - uint32_t dataOffset; /*!< I2S data output offset configuration */ - I2S_Data_Size_Type dataSize; /*!< I2S data size configuration */ - BL_Fun_Type monoMode; /*!< I2S enable mono mode,when this mode enable,lRMerge must be disabled */ - I2S_Mono_Mode_Channel monoModeChannel; /*!< I2S mono mode channel configuration */ -} I2S_CFG_Type; - -/** - * @brief I2S FIFO configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type lRMerge; /*!< I2S FIFO contains both left and right channel data in one entry */ - BL_Fun_Type frameDataExchange; /*!< I2S exchange left and right channel data in one entry */ - BL_Fun_Type txfifoDmaEnable; /*!< Enable or disable I2S tx fifo dma function. */ - BL_Fun_Type rxfifoDmaEnable; /*!< Enable or disable I2S rx fifo dma function. */ - uint8_t rxFifoLevel; /*!< I2S receive fifo interrupt trigger level. only valid when fifo mode enabled. */ - uint8_t txFifoLevel; /*!< I2S transmit fifo interrupt trigger level. only valid when fifo mode enabled. */ -} I2S_FifoCfg_Type; - -/** - * @brief I2S IO configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type deglitchEn; /*!< Enable or disable deglitch(for all the input pins) */ - uint8_t deglitchCnt; /*!< Deglitch cycle count(unit:cycle of I2S kernel clock) */ - BL_Fun_Type inverseBCLK; /*!< Enable or disable inverse BCLK signal */ - BL_Fun_Type inverseFS; /*!< Enable or disable inverse FS signal */ - BL_Fun_Type inverseRX; /*!< Enable or disable inverse RX signal */ - BL_Fun_Type inverseTX; /*!< Enable or disable inverse TX signal */ -} I2S_IOCfg_Type; - -/*@} end of group I2S_Public_Types */ - -/** @defgroup I2S_Public_Constants - * @{ - */ - -/** @defgroup I2S_MODE_TYPE - * @{ - */ -#define IS_I2S_MODE_TYPE(type) (((type) == I2S_MODE_I2S_LEFT) || \ - ((type) == I2S_MODE_I2S_RIGHT) || \ - ((type) == I2S_MODE_I2S_DSP)) - -/** @defgroup I2S_ID_TYPE - * @{ - */ -#define IS_I2S_ID_TYPE(type) (((type) == I2S0_ID) || \ - ((type) == I2S1_ID) || \ - ((type) == I2S_ID_MAX)) - -/** @defgroup I2S_ROLE_TYPE - * @{ - */ -#define IS_I2S_ROLE_TYPE(type) (((type) == I2S_ROLE_MASTER) || \ - ((type) == I2S_ROLE_SLAVE)) - -/** @defgroup I2S_DATA_SIZE_TYPE - * @{ - */ -#define IS_I2S_DATA_SIZE_TYPE(type) (((type) == I2S_SIZE_DATA_8) || \ - ((type) == I2S_SIZE_DATA_16) || \ - ((type) == I2S_SIZE_DATA_24) || \ - ((type) == I2S_SIZE_DATA_32)) - -/** @defgroup I2S_FRAME_SIZE_TYPE - * @{ - */ -#define IS_I2S_FRAME_SIZE_TYPE(type) (((type) == I2S_SIZE_FRAME_8) || \ - ((type) == I2S_SIZE_FRAME_16) || \ - ((type) == I2S_SIZE_FRAME_24) || \ - ((type) == I2S_SIZE_FRAME_32)) - -/** @defgroup I2S_ENDIAN_TYPE - * @{ - */ -#define IS_I2S_ENDIAN_TYPE(type) (((type) == I2S_DATA_ENDIAN_MSB) || \ - ((type) == I2S_DATA_ENDIAN_LSB)) - -/** @defgroup I2S_FS_MODE_TYPE - * @{ - */ -#define IS_I2S_FS_MODE_TYPE(type) (((type) == I2S_FS_MODE_EVEN) || \ - ((type) == I2S_FS_MODE_1T)) - -/** @defgroup I2S_MONO_MODE_CHANNEL - * @{ - */ -#define IS_I2S_MONO_MODE_CHANNEL(type) (((type) == I2S_RX_MONO_MODE_LEFT_CHANNEL) || \ - ((type) == I2S_RX_MONO_MODE_RIGHT_CHANNEL)) - -/** @defgroup I2S_FS_CHANNEL_TYPE - * @{ - */ -#define IS_I2S_FS_CHANNEL_TYPE(type) (((type) == I2S_FS_CHANNELS_2) || \ - ((type) == I2S_FS_CHANNELS_3) || \ - ((type) == I2S_FS_CHANNELS_4)) - -/** @defgroup I2S_MONOCONTROL_TYPE - * @{ - */ -#define IS_I2S_MONOCONTROL_TYPE(type) (((type) == I2S_MONO_CONTROL_STEREO) || \ - ((type) == I2S_MONO_CONTROL_MONO)) - -/** @defgroup I2S_FIFO_24_JUSTIFIED_TYPE - * @{ - */ -#define IS_I2S_FIFO_24_JUSTIFIED_TYPE(type) (((type) == I2S_FIFO_24_RIGHT_JUSTIFIED) || \ - ((type) == I2S_FIFO_24_LEFT_JUSTIFIED)) - -/*@} end of group I2S_Public_Constants */ - -/** @defgroup I2S_Public_Macros - * @{ - */ -#define I2S_TX_FIFO_SIZE 16 -#define I2S_RX_FIFO_SIZE 16 - -/*@} end of group I2S_Public_Macros */ - -/** @defgroup I2S_Public_Functions - * @{ - */ - -/** - * @brief I2S Functions - */ -void I2S_SetBclkPeriod(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg); -void I2S_Init(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg); -void I2S_FifoConfig(I2S_ID_Type i2sId, I2S_FifoCfg_Type *fifoCfg); -void I2S_IOConfig(I2S_ID_Type i2sId, I2S_IOCfg_Type *ioCfg); -void I2S_Enable(I2S_ID_Type i2sId, I2S_Role_Type roleType); -void I2S_Disable(I2S_ID_Type i2sId); -uint32_t I2S_Read(I2S_ID_Type i2sId); -void I2S_Write(I2S_ID_Type i2sId, uint32_t data); -void I2S_Mute(I2S_ID_Type i2sId, BL_Fun_Type enabled); -void I2S_SetFifoJustified(I2S_ID_Type i2sId, I2S_FIFO_24_Justified_Type justType); -uint32_t I2S_GetTxFIFO_AvlCnt(I2S_ID_Type i2sId); -uint32_t I2S_GetRxFIFO_AvlCnt(I2S_ID_Type i2sId); -void I2S_Rx_FIFO_Flush(I2S_ID_Type i2sId); -void I2S_Tx_FIFO_Flush(I2S_ID_Type i2sId); - -/*@} end of group I2S_Public_Functions */ - -/*@} end of group I2S */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_I2S_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ir.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ir.h deleted file mode 100644 index 43f709d7a8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ir.h +++ /dev/null @@ -1,289 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ir.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_IR_H__ -#define __BL808_IR_H__ - -#include "ir_reg.h" -#include "bl808_common.h" -#include "bl808_hbn.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup IR - * @{ - */ - -/** @defgroup IR_Public_Types - * @{ - */ - -/** - * @brief IR direction type definition - */ -typedef enum { - IR_TX, /*!< IR TX direction */ - IR_RX, /*!< IR RX direction */ - IR_TXRX, /*!< IR TX and RX direction */ -} IR_Direction_Type; - -/** - * @brief IR word type definition - */ -typedef enum { - IR_WORD_0, /*!< IR data word 0 */ - IR_WORD_1, /*!< IR data word 1 */ -} IR_Word_Type; - -/** - * @brief IR frame size(also the valid width for each fifo entry) type definition - */ -typedef enum { - IR_FRAME_SIZE_8, /*!< IR frame size 8 bit */ - IR_FRAME_SIZE_16, /*!< IR frame size 16 bit */ - IR_FRAME_SIZE_24, /*!< IR frame size 24 bit */ - IR_FRAME_SIZE_32, /*!< IR frame size 32 bit */ -} IR_FrameSize_Type; - -/** - * @brief IR RX mode type definition - */ -typedef enum { - IR_RX_NEC, /*!< IR RX NEC mode */ - IR_RX_RC5, /*!< IR RX RC5 mode */ - IR_RX_SWM, /*!< IR RX software pulse-width detection mode */ -} IR_RxMode_Type; - -/** - * @brief IR interrupt type definition - */ -typedef enum { - IR_INT_TX_END, /*!< IR TX transfer end interrupt */ - IR_INT_TX_FIFO_REQ, /*!< IR TX fifo ready interrupt (tx fifo count > tx fifo threshold) */ - IR_INT_TX_FIFO_ERROR, /*!< IR TX fifo error interrupt (overflow/underflow) */ - IR_INT_RX_END, /*!< IR RX transfer end interrupt */ - IR_INT_RX_FIFO_REQ, /*!< IR RX fifo ready interrupt (rx fifo count > rx fifo threshold) */ - IR_INT_RX_FIFO_ERROR, /*!< IR RX fifo error interrupt (overflow/underflow) */ - IR_INT_ALL, /*!< IR all interrupt */ -} IR_INT_Type; - -/** - * @brief IR fifo underflow or overflow type definition - */ -typedef enum { - IR_FIFO_TX_OVERFLOW, /*!< IR tx fifo overflow flag */ - IR_FIFO_TX_UNDERFLOW, /*!< IR tx fifo underflow flag */ - IR_FIFO_RX_OVERFLOW, /*!< IR rx fifo overflow flag */ - IR_FIFO_RX_UNDERFLOW, /*!< IR rx fifo underflow flag */ -} IR_FifoStatus_Type; - -/** - * @brief IR TX configuration structure type definition - */ -typedef struct -{ - uint8_t dataBits; /*!< Bit count of data phase (don't care if tx freerun mode is enabled) */ - BL_Fun_Type tailPulseInverse; /*!< Enable or disable signal of tail pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type tailPulse; /*!< Enable or disable signal of tail pulse (don't care if SWM is enabled) */ - BL_Fun_Type headPulseInverse; /*!< Enable or disable signal of head pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type headPulse; /*!< Enable or disable signal of head pulse (don't care if SWM is enabled) */ - BL_Fun_Type logic1PulseInverse; /*!< Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type logic0PulseInverse; /*!< Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled) */ - BL_Fun_Type dataPulse; /*!< Enable or disable signal of data pulse (don't care if SWM is enabled) */ - BL_Fun_Type outputModulation; /*!< Enable or disable signal of output modulation */ - BL_Fun_Type outputInverse; /*!< Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high */ - BL_Fun_Type freerunEnable; /*!< Enable or disable tx freerun mode (don't care if SWM is enabled) */ - BL_Fun_Type continueEnable; /*!< Disable:idle time between frames = (tailPulseWidth_0+tailPulseWidth_1)*pulseWidthUnit,Enable:no - idle time between frames */ - IR_FrameSize_Type frameSize; /*!< IR frame size(also the valid width for each fifo entry) */ -} IR_TxCfg_Type; - -/** - * @brief IR TX pulse width configuration structure type definition - */ -typedef struct -{ - uint8_t logic0PulseWidth_1; /*!< Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled) */ - uint8_t logic0PulseWidth_0; /*!< Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled) */ - uint8_t logic1PulseWidth_1; /*!< Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled) */ - uint8_t logic1PulseWidth_0; /*!< Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled) */ - uint8_t headPulseWidth_1; /*!< Pulse width of head pulse phase 1 (don't care if SWM is enabled) */ - uint8_t headPulseWidth_0; /*!< Pulse width of head pulse phase 0 (don't care if SWM is enabled) */ - uint8_t tailPulseWidth_1; /*!< Pulse width of tail pulse phase 1 (don't care if SWM is enabled) */ - uint8_t tailPulseWidth_0; /*!< Pulse width of tail pulse phase 0 (don't care if SWM is enabled) */ - uint8_t moduWidth_1; /*!< Modulation phase 1 width */ - uint8_t moduWidth_0; /*!< Modulation phase 0 width */ - uint16_t pulseWidthUnit; /*!< Pulse width unit */ -} IR_TxPulseWidthCfg_Type; - -/** - * @brief IR RX configuration structure type definition - */ -typedef struct -{ - IR_RxMode_Type rxMode; /*!< Set ir rx mode */ - BL_Fun_Type inputInverse; /*!< Enable or disable signal of input inverse */ - uint16_t endThreshold; /*!< Pulse width threshold to trigger end condition */ - uint16_t dataThreshold; /*!< Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled) */ - BL_Fun_Type rxDeglitch; /*!< Enable or disable signal of rx input de-glitch function */ - uint8_t DeglitchCnt; /*!< De-glitch function cycle count */ -} IR_RxCfg_Type; - -/** - * @brief IR DMA configuration structure type definition - */ -typedef struct -{ - uint8_t txFifoThreshold; /*!< IR tx FIFO threshold */ - uint8_t rxFifoThreshold; /*!< IR rx FIFO threshold */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ -} IR_FifoCfg_Type; - -/*@} end of group IR_Public_Types */ - -/** @defgroup IR_Public_Constants - * @{ - */ - -/** @defgroup IR_DIRECTION_TYPE - * @{ - */ -#define IS_IR_DIRECTION_TYPE(type) (((type) == IR_TX) || \ - ((type) == IR_RX) || \ - ((type) == IR_TXRX)) - -/** @defgroup IR_WORD_TYPE - * @{ - */ -#define IS_IR_WORD_TYPE(type) (((type) == IR_WORD_0) || \ - ((type) == IR_WORD_1)) - -/** @defgroup IR_FRAMESIZE_TYPE - * @{ - */ -#define IS_IR_FRAMESIZE_TYPE(type) (((type) == IR_FRAME_SIZE_8) || \ - ((type) == IR_FRAME_SIZE_16) || \ - ((type) == IR_FRAME_SIZE_24) || \ - ((type) == IR_FRAME_SIZE_32)) - -/** @defgroup IR_RXMODE_TYPE - * @{ - */ -#define IS_IR_RXMODE_TYPE(type) (((type) == IR_RX_NEC) || \ - ((type) == IR_RX_RC5) || \ - ((type) == IR_RX_SWM)) - -/** @defgroup IR_INT_TYPE - * @{ - */ -#define IS_IR_INT_TYPE(type) (((type) == IR_INT_TX_END) || \ - ((type) == IR_INT_TX_FIFO_REQ) || \ - ((type) == IR_INT_TX_FIFO_ERROR) || \ - ((type) == IR_INT_RX_END) || \ - ((type) == IR_INT_RX_FIFO_REQ) || \ - ((type) == IR_INT_RX_FIFO_ERROR) || \ - ((type) == IR_INT_ALL)) - -/** @defgroup IR_FIFOSTATUS_TYPE - * @{ - */ -#define IS_IR_FIFOSTATUS_TYPE(type) (((type) == IR_FIFO_TX_OVERFLOW) || \ - ((type) == IR_FIFO_TX_UNDERFLOW) || \ - ((type) == IR_FIFO_RX_OVERFLOW) || \ - ((type) == IR_FIFO_RX_UNDERFLOW)) - -/*@} end of group IR_Public_Constants */ - -/** @defgroup IR_Public_Macros - * @{ - */ -#define IR_RX_FIFO_SIZE 64 -#define IR_TX_FIFO_SIZE 4 - -/*@} end of group IR_Public_Macros */ - -/** @defgroup IR_Public_Functions - * @{ - */ - -/** - * @brief IR Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void IRRX_IRQHandler(void); -void IRTX_IRQHandler(void); -#endif -BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg); -BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg); -BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg); -BL_Err_Type IR_FifoConfig(IR_FifoCfg_Type *fifoCfg); -BL_Err_Type IR_DeInit(void); -BL_Err_Type IR_Enable(IR_Direction_Type direct); -BL_Err_Type IR_Disable(IR_Direction_Type direct); -BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM); -BL_Err_Type IR_RxFifoClear(void); -BL_Err_Type IR_TxFifoClear(void); -BL_Err_Type IR_SendData(uint32_t *data, uint8_t length); -BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length); -BL_Err_Type IR_SendCommand(uint32_t *data, uint8_t length); -BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length); -BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command); -BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask); -BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType); -BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun); -BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType); -BL_Sts_Type IR_GetFifoStatus(IR_FifoStatus_Type fifoSts); -uint32_t IR_ReceiveData(IR_Word_Type irWord); -uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length); -BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command); -uint8_t IR_GetRxDataBitCount(void); -uint8_t IR_GetRxFifoCount(void); -uint8_t IR_GetTxFifoCount(void); -IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length); -BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length); -uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data); -BL_Err_Type IR_LEDInit(HBN_MCU_XCLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, - uint8_t code1L); -BL_Err_Type IR_LEDSend(uint32_t data); - -/*@} end of group IR_Public_Functions */ - -/*@} end of group IR */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_IR_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_iso11898.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_iso11898.h deleted file mode 100644 index d98cd01ed4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_iso11898.h +++ /dev/null @@ -1,242 +0,0 @@ -#ifndef __BL808_ISO11898_H__ -#define __BL808_ISO11898_H__ - -#include "iso11898_reg.h" -#include "bl808_common.h" - -#define ISO11898_TIMEOUT_MAX (32 * 1000) - -typedef enum { - ISO11898_FRAME_FORMAT_STANDARD = 0, - ISO11898_FRAME_FORMAT_EXTENDED, -} ISO11898_FRAME_FORMAT_Type; - -typedef enum { - ISO11898_FRAME_TYPE_DATA = 0, - ISO11898_FRAME_TYPE_REMOTE, -} ISO11898_FRAME_Type; - -typedef enum { - ISO11898_MODE_TYPE_RESET = 0, - ISO11898_MODE_TYPE_LISTEN_ONLY, - ISO11898_MODE_TYPE_SELF_TSET, - ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, -} ISO11898_MODE_Type; - -typedef enum { - ISO11898_MODE_VALUE_NORMAL = 0, - ISO11898_MODE_VALUE_RESET = 1, - ISO11898_MODE_VALUE_LISTEN_ONLY = 1, - ISO11898_MODE_VALUE_SELF_TSET = 1, - ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL = 0, - ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE = 1, -} ISO11898_MODE_VALUE_Type; - -typedef enum { - ISO11898_INT_RECEIVE = 0, - ISO11898_INT_TRANSMIT, - ISO11898_INT_ERROR_WARNING, - ISO11898_INT_OVERRUN, - ISO11898_INT_RESERVED, - ISO11898_INT_PASSIVE = 5, - ISO11898_INT_ARBITRATION_LOST, - ISO11898_INT_BUS_ERROR, - ISO11898_INT_ALL, -} ISO11898_INT_Type; - -typedef enum { - ISO11898_STATUS_RECEIVE_BUFFER = 0, - ISO11898_STATUS_DATA_OVERRUN, - ISO11898_STATUS_TRANSMIT_BUFFER, - ISO11898_STATUS_TRANSMISSION_COMPLETE, - ISO11898_STATUS_RECEIVE, - ISO11898_STATUS_TRANSMIT, - ISO11898_STATUS_ERROR, - ISO11898_STATUS_BUS, -} ISO11898_STATUS_Type; - -typedef enum { - ISO11898_STATUS_RECEIVE_BUFFER_EMPTY = 0, - ISO11898_STATUS_RECEIVE_BUFFER_NONEMPTY = 1, - ISO11898_STATUS_DATA_OVERRUN_NULL = 0, - ISO11898_STATUS_DATA_OVERRUN_EXIST = 1, - ISO11898_STATUS_TRANSMIT_BUFFER_LOCKED = 0, - ISO11898_STATUS_TRANSMIT_BUFFER_ACCESSIBLE = 1, - ISO11898_STATUS_TRANSMISSION_COMPLETE_NOT = 0, - ISO11898_STATUS_TRANSMISSION_COMPLETE_YES = 1, - ISO11898_STATUS_RECEIVE_IDLE = 0, - ISO11898_STATUS_RECEIVE_ONGOING = 1, - ISO11898_STATUS_TRANSMIT_IDLE = 0, - ISO11898_STATUS_TRANSMIT_ONGOING = 1, - ISO11898_STATUS_ERROR_NULL = 0, - ISO11898_STATUS_ERROR_EXIST = 1, - ISO11898_STATUS_BUS_ON = 0, - ISO11898_STATUS_BUS_OFF = 1, -} ISO11898_STATUS_VALUE_Type; - -typedef enum { - ISO11898_ERROR_TYPE_BIT = 0, - ISO11898_ERROR_TYPE_FORM, - ISO11898_ERROR_TYPE_STUFF, - ISO11898_ERROR_TYPE_OTHERS, -} ISO11898_ERROR_CODE_Type; - -typedef enum { - ISO11898_ERROR_DIRECTION_TX = 0, - ISO11898_ERROR_DIRECTION_RX, -} ISO11898_ERROR_DIRECTION_Type; - -typedef enum { - ISO11898_ERROR_LOCATION_ID28_TO_ID21 = 2, - ISO11898_ERROR_LOCATION_START_OF_FRAME = 3, - ISO11898_ERROR_LOCATION_BIT_SRTR = 4, - ISO11898_ERROR_LOCATION_BIT_IDE = 5, - ISO11898_ERROR_LOCATION_ID20_TO_ID18 = 6, - ISO11898_ERROR_LOCATION_ID17_TO_ID13 = 7, - ISO11898_ERROR_LOCATION_CRC_SEQUENCE = 8, - ISO11898_ERROR_LOCATION_BIT_RESERVED_0 = 9, - ISO11898_ERROR_LOCATION_DATA_FIELD = 10, - ISO11898_ERROR_LOCATION_DATA_LENGTH_CODE = 11, - ISO11898_ERROR_LOCATION_BIT_RTR = 12, - ISO11898_ERROR_LOCATION_BIT_RESERVED_1 = 13, - ISO11898_ERROR_LOCATION_ID4_TO_ID0 = 14, - ISO11898_ERROR_LOCATION_ID12_TO_ID15 = 15, - ISO11898_ERROR_LOCATION_ACTIVE_ERROR_FLAG = 17, - ISO11898_ERROR_LOCATION_INTERMISSION = 18, - ISO11898_ERROR_LOCATION_BIT_TOLERATE_DOMINANT = 19, - ISO11898_ERROR_LOCATION_PASSIVE_ERROR_FLAG = 22, - ISO11898_ERROR_LOCATION_ERROR_DELIMITER = 23, - ISO11898_ERROR_LOCATION_CRC_DELIMITER = 24, - ISO11898_ERROR_LOCATION_ACK_SLOT = 25, - ISO11898_ERROR_LOCATION_END_OF_FRAME = 26, - ISO11898_ERROR_LOCATION_ACK_DELIMITER = 27, - ISO11898_ERROR_LOCATION_OVERLOAD_FLAG = 28, -} ISO11898_ERROR_LOCATION_Type; - -typedef enum { - ISO11898_FILTER_REGISTER_ACR0 = 0, - ISO11898_FILTER_REGISTER_ACR1, - ISO11898_FILTER_REGISTER_ACR2, - ISO11898_FILTER_REGISTER_ACR3, - ISO11898_FILTER_REGISTER_AMR0, - ISO11898_FILTER_REGISTER_AMR1, - ISO11898_FILTER_REGISTER_AMR2, - ISO11898_FILTER_REGISTER_AMR3, -} ISO11898_FILTER_REGISTER_Type; - -typedef struct { - ISO11898_ERROR_CODE_Type code; - ISO11898_ERROR_DIRECTION_Type dir; - ISO11898_ERROR_LOCATION_Type location; -} ISO11898_ERROR_Type; - -typedef struct { - ISO11898_FRAME_FORMAT_Type formatType; - ISO11898_MODE_VALUE_Type filterMode; - ISO11898_FRAME_Type matchRtr1; - ISO11898_FRAME_Type matchRtr2; - uint8_t matchData1; - uint8_t matchData2; - uint32_t matchId1; - uint32_t matchId2; - BL_Mask_Type maskRtr1; - BL_Mask_Type maskRtr2; - uint8_t maskData1; - uint8_t maskData2; - uint32_t maskId1; - uint32_t maskId2; -} ISO11898_FILTER_CFG_Type; - -typedef struct { - ISO11898_FRAME_Type frameType; - ISO11898_FRAME_FORMAT_Type frameFormat; - uint8_t dataLen; - uint8_t *dataAddr; - uint32_t id; - uint32_t timeout; -} ISO11898_CFG_Type; - -#define IS_ISO11898_FRAME_FORMAT_TYPE(type) (((type) == ISO11898_FRAME_FORMAT_STANDARD) || \ - ((type) == ISO11898_FRAME_FORMAT_EXTENDED)) - -#define IS_ISO11898_FRAME_TYPE(type) (((type) == ISO11898_FRAME_TYPE_DATA) || \ - ((type) == ISO11898_FRAME_TYPE_REMOTE)) - -#define IS_ISO11898_MODE_TYPE(type) (((type) == ISO11898_MODE_TYPE_RESET) || \ - ((type) == ISO11898_MODE_TYPE_LISTEN_ONLY) || \ - ((type) == ISO11898_MODE_TYPE_SELF_TSET) || \ - ((type) == ISO11898_MODE_TYPE_ACCEPTANCE_FILTER) || \ - -#define IS_ISO11898_MODE_VALUE_TYPE(type) (((type) == ISO11898_MODE_VALUE_NORMAL) || \ - ((type) == ISO11898_MODE_VALUE_RESET) || \ - ((type) == ISO11898_MODE_VALUE_LISTEN_ONLY) || \ - ((type) == ISO11898_MODE_VALUE_SELF_TSET) || \ - ((type) == ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL) || \ - ((type) == ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE) || \ - -#define IS_ISO11898_INT_TYPE(type) (((type) == ISO11898_INT_RECEIVE) || \ - ((type) == ISO11898_INT_TRANSMIT) || \ - ((type) == ISO11898_INT_ERROR_WARNING) || \ - ((type) == ISO11898_INT_OVERRUN) || \ - ((type) == ISO11898_INT_PASSIVE) || \ - ((type) == ISO11898_INT_ARBITRATION_LOST) || \ - ((type) == ISO11898_INT_BUSERROR) || \ - ((type) == ISO11898_INT_ALL)) - -#define IS_ISO11898_STATUS_TYPE(type) (((type) == ISO11898_STATUS_RECEIVE_BUFFER) || \ - ((type) == ISO11898_STATUS_DATA_OVERRUN) || \ - ((type) == ISO11898_STATUS_TRANSMIT_BUFFER) || \ - ((type) == ISO11898_STATUS_TRANSMISSION_COMPLETE) || \ - ((type) == ISO11898_STATUS_RECEIVE) || \ - ((type) == ISO11898_STATUS_TRANSMIT) || \ - ((type) == ISO11898_STATUS_ERROR) || \ - ((type) == ISO11898_STATUS_BUS)) - -#define IS_ISO11898_STATUS_VALUE_TYPE(type) (((type) == ISO11898_STATUS_VALUE_RECEIVE_BUFFER_EMPTY || \ - ((type) == ISO11898_STATUS_VALUE_RECEIVE_BUFFER_NONEMPTY || \ - ((type) == ISO11898_STATUS_VALUE_DATA_OVERRUN_NULL || \ - ((type) == ISO11898_STATUS_VALUE_DATA_OVERRUN_EXIST || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_BUFFER_LOCKED || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_BUFFER_ACCESSIBLE || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMISSION_COMPLETE_NOT || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMISSION_COMPLETE_YES || \ - ((type) == ISO11898_STATUS_VALUE_RECEIVE_IDLE || \ - ((type) == ISO11898_STATUS_VALUE_RECEIVE_ONGOING || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_IDLE || \ - ((type) == ISO11898_STATUS_VALUE_TRANSMIT_ONGOING || \ - ((type) == ISO11898_STATUS_VALUE_ERROR_NULL || \ - ((type) == ISO11898_STATUS_VALUE_ERROR_EXIST || \ - ((type) == ISO11898_STATUS_VALUE_BUS_ON || \ - ((type) == ISO11898_STATUS_VALUE_BUS_OFF)) - -void ISO11898_Init(void); -void ISO11898_Mode_Set(ISO11898_MODE_Type type, ISO11898_MODE_VALUE_Type value); -ISO11898_MODE_VALUE_Type ISO11898_Mode_Get(ISO11898_MODE_Type type); -void ISO11898_Int_Enable(ISO11898_INT_Type intType, BL_Fun_Type enable); -void ISO11898_Cmd_Request_Transmit(void); -void ISO11898_Cmd_Abort_Transmit(void); -void ISO11898_Cmd_Release_Recv_Buff(void); -void ISO11898_Cmd_Clear_Data_Overrun(void); -void ISO11898_Cmd_Request_Self_Reception(void); -ISO11898_STATUS_VALUE_Type ISO11898_Status_Get(ISO11898_STATUS_Type type); -uint8_t ISO11898_Arbitration_Lost_Position_Get(void); -void ISO11898_Error_Get(ISO11898_ERROR_Type *const code); -BL_Err_Type ISO11898_Error_Warning_Limit_Set(uint8_t limit); -uint8_t ISO11898_Error_Warning_Limit_Get(void); -uint8_t ISO11898_Error_Rx_Counter_Get(void); -uint8_t ISO11898_Error_Tx_Counter_Get(void); -BL_Err_Type ISO11898_Transmit(const ISO11898_CFG_Type *cfg); -BL_Err_Type ISO11898_Receive(ISO11898_CFG_Type *cfg); -uint8_t ISO11898_Receive_Buff_Frame_Count_Get(void); -BL_Err_Type ISO11898_Clock_Div_Set(uint8_t div); -uint8_t ISO11898_Clock_Div_Get(void); -BL_Err_Type ISO11898_Synchronization_Jump_Width_Set(uint8_t width); -uint8_t ISO11898_Synchronization_Jump_Width_Get(void); -BL_Err_Type ISO11898_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail); -void ISO11898_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail); -void ISO11898_Filter_Set(const ISO11898_FILTER_CFG_Type *cfg); -void ISO11898_Filter_Register_Set(ISO11898_FILTER_REGISTER_Type reg, uint8_t value); -void ISO11898_Filter_Registers_Set(uint8_t *valueArr); - -BL_Err_Type ISO11898_Int_Callback_Install(ISO11898_INT_Type intType, intCallback_Type *cbFun); -#endif /* __BL606p_ISO11898_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_efuse.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_efuse.h deleted file mode 100644 index cbd7e585e8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_efuse.h +++ /dev/null @@ -1,25 +0,0 @@ -#ifndef __BL602_MFG_EFUSE_H__ -#define __BL602_MFG_EFUSE_H__ - -#include "stdint.h" - -uint8_t mfg_efuse_get_rf_cal_slots(void); -void mfg_efuse_set_rf_cal_slots(uint8_t slots); -uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload); -int8_t mfg_efuse_write_xtal_capcode_pre(uint8_t capcode,uint8_t program); -void mfg_efuse_write_xtal_capcode(void); -int8_t mfg_efuse_read_xtal_capcode(uint8_t *capcode,uint8_t reload); -uint8_t mfg_efuse_is_poweroffset_slot_empty(uint8_t reload); -int8_t mfg_efuse_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program); -void mfg_efuse_write_poweroffset(void); -int8_t mfg_efuse_read_poweroffset(int8_t pwrOffset[14],uint8_t reload); -uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload); -int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program); -void mfg_efuse_write_macaddr(void); -int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload); -int8_t mfg_efuse_read(uint32_t addr,uint32_t *data,uint32_t countInword,uint8_t reload); -int8_t mfg_efuse_program(void); -int8_t mfg_efuse_write_pre(uint32_t addr,uint32_t *data,uint32_t countInword); -int8_t mfg_efuse_read_poweroffset_ate(int8_t *pwrOffset); - -#endif/*__BL602_MFG_EFUSE_H__*/ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_flash.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_flash.h deleted file mode 100644 index 2089cc683c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_flash.h +++ /dev/null @@ -1,30 +0,0 @@ -#ifndef __BL602_MFG_FLASH_H__ -#define __BL602_MFG_FLASH_H__ - -#include "stdint.h" -#include "bl808_xip_sflash.h" - -typedef struct rf_para_flash_tag{ - uint32_t magic; //"RFPA" - uint8_t capcode_valid; //0x5A - uint8_t capcode; - uint8_t poweroffset_valid; //0x5A - int8_t poweroffset[3]; - uint8_t mac_valid; //0x5A - uint8_t mac[6]; - uint8_t rsvd[3]; - uint32_t crc32; -}rf_para_flash_t; - -int8_t mfg_flash_init( SPI_Flash_Cfg_Type *flashCfg); -int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode,uint8_t program); -void mfg_flash_write_xtal_capcode(void); -int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode,uint8_t reload); -int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program); -void mfg_flash_write_poweroffset(void); -int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14],uint8_t reload); -int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6],uint8_t program); -void mfg_flash_write_macaddr(void); -int8_t mfg_flash_read_macaddr(uint8_t mac[6],uint8_t reload); - -#endif/*__BL602_MFG_FLASH_H__*/ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_media.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_media.h deleted file mode 100644 index 47b103607a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mfg_media.h +++ /dev/null @@ -1,35 +0,0 @@ -#ifndef __BL602_MFG_MEDIA_H__ -#define __BL602_MFG_MEDIA_H__ - -#include "stdint.h" -#include "bl808_mfg_efuse.h" -#include "bl808_mfg_flash.h" - -int8_t mfg_media_init_need_lock( SPI_Flash_Cfg_Type *flashCfg); -int8_t mfg_media_init_with_lock( SPI_Flash_Cfg_Type *flashCfg); -uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload); -int8_t mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode,uint8_t program); -void mfg_media_write_xtal_capcode_need_lock(void); -int8_t mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode,uint8_t reload); -int8_t mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode,uint8_t program); -void mfg_media_write_xtal_capcode_with_lock(void); -int8_t mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode,uint8_t reload); -int8_t mfg_media_read_xtal_capcode(uint8_t *capcode,uint8_t reload); -uint8_t mfg_media_is_poweroffset_slot_empty(uint8_t reload); -int8_t mfg_media_write_poweroffset_pre_need_lock(int8_t pwrOffset[14],uint8_t program); -void mfg_media_write_poweroffset_need_lock(void); -int8_t mfg_media_read_poweroffset_need_lock(int8_t pwrOffset[14],uint8_t reload); -int8_t mfg_media_read_poweroffset(int8_t pwrOffset[14],uint8_t reload); -int8_t mfg_media_write_poweroffset_pre_with_lock(int8_t pwrOffset[14],uint8_t program); -void mfg_media_write_poweroffset_with_lock(void); -int8_t mfg_media_read_poweroffset_with_lock(int8_t pwrOffset[14],uint8_t reload); -uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload); -int8_t mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6],uint8_t program); -void mfg_media_write_macaddr_need_lock(void); -int8_t mfg_media_read_macaddr_need_lock(uint8_t mac[6],uint8_t reload); -int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6],uint8_t program); -void mfg_media_write_macaddr_with_lock(void); -int8_t mfg_media_read_macaddr_with_lock(uint8_t mac[6],uint8_t reload); -int8_t mfg_media_read_macaddr(uint8_t mac[6],uint8_t reload); - -#endif/*__BL602_MFG_MEDIA_H__*/ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjdec.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjdec.h deleted file mode 100644 index 2456c85ae7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjdec.h +++ /dev/null @@ -1,175 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjdec.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_MJDEC_H__ -#define __BL808_MJDEC_H__ - -#include "mjdec_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJDEC - * @{ - */ - -/** @defgroup MJDEC_Public_Types - * @{ - */ - -/** - * @brief MJDEC YUV format definition - */ -typedef enum { - MJDEC_YUV420, /*!< MJDEC YUV420 planar mode */ - MJDEC_YUV400, /*!< MJDEC YUV400 grey scale mode */ - MJDEC_YUV422_PLANAR, /*!< MJDEC YUV422 planar mode */ -} MJDEC_YUV_Mode_Type; - -/** - * @brief MJDEC burst type definition - */ -typedef enum { - MJDEC_BURST_SINGLE, /*!< MJDEC burst single */ - MJDEC_BURST_INCR4, /*!< MJDEC burst incr4 */ - MJDEC_BURST_INCR8, /*!< MJDEC burst incr8 */ - MJDEC_BURST_INCR16, /*!< MJDEC burst incr16 */ -} MJDEC_Burst_Type; - -/** - * @brief MJDEC interrupt type definition - */ -typedef enum { - MJDEC_INT_NORMAL, /*!< MJDEC normal write interrupt */ - MJDEC_INT_BACK_IDLE, /*!< MJDEC back idle interrupt */ - MJDEC_INT_ALL, /*!< MJDEC all interrupt type */ -} MJDEC_INT_Type; - -/** - * @brief MJDEC configuration strcut definition - */ -typedef struct { - MJDEC_Burst_Type burstRead; /*!< MJDEC burst read type */ - MJDEC_Burst_Type burstWrite; /*!< MJDEC burst write type */ - MJDEC_YUV_Mode_Type yuv; /*!< MJDEC control YUV mode */ - uint8_t intCnt; /*!< Set frame threshold to issue interrupt */ - uint32_t bufferFrameYY; /*!< YUV frame buffer address of YY frame */ - uint32_t bufferFrameUV; /*!< YUV frame buffer address of UV frame */ - uint16_t resolutionX; /*!< YUV frame RESOLUTION X */ - uint16_t resolutionY; /*!< YUV frame RESOLUTION Y */ - uint16_t headByte; /*!< Skip JPEG stream header byte */ - BL_Fun_Type headSkip; /*!< Skip JPEG stream header */ - BL_Fun_Type evenOrderEnable; /*!< Enable:U is even byte of UV frame and V is odd byte of UV frame */ - BL_Fun_Type dmyBlock; /*!< MJPEG last half block with dummy data 8'h80 */ - BL_Fun_Type dmyVertical; /*!< MJPEG last half vertical block drop */ - BL_Fun_Type dmyHorizational; /*!< MJPEG last half horizational block drop */ - BL_Fun_Type swapMode; /*!< MJDEC YUV Memory swap mode */ - uint8_t picQuality; /*!< Quality must be in 1-75 or 100 */ -} MJDEC_CFG_Type; - -/** - * @brief MJDEC frame information strcut definition - */ -typedef struct -{ - uint8_t validFrames; /*!< Valid frames */ - uint32_t curFrameAddr; /*!< Current frame address */ -} MJDEC_Frame_Info; - -/*@} end of group MJDEC_Public_Types */ - -/** @defgroup MJDEC_Public_Constants - * @{ - */ - -/** @defgroup MJDEC_YUV_MODE_TYPE - * @{ - */ -#define IS_MJDEC_YUV_MODE_TYPE(type) (((type) == MJDEC_YUV420) || \ - ((type) == MJDEC_YUV400) || \ - ((type) == MJDEC_YUV422_PLANAR)) - -/** @defgroup MJDEC_BURST_TYPE - * @{ - */ -#define IS_MJDEC_BURST_TYPE(type) (((type) == MJDEC_BURST_SINGLE) || \ - ((type) == MJDEC_BURST_INCR4) || \ - ((type) == MJDEC_BURST_INCR8) || \ - ((type) == MJDEC_BURST_INCR16)) - -/** @defgroup MJDEC_INT_TYPE - * @{ - */ -#define IS_MJDEC_INT_TYPE(type) (((type) == MJDEC_INT_NORMAL) || \ - ((type) == MJDEC_INT_BACK_IDLE) || \ - ((type) == MJDEC_INT_ALL)) - -/*@} end of group MJDEC_Public_Constants */ - -/** @defgroup MJDEC_Public_Macros - * @{ - */ -#define MJDEC_BASE MJPEG_DEC_BASE -/*@} end of group MJDEC_Public_Macros */ - -/** @defgroup MJDEC_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void MJDEC_IRQHandler(void); -#endif -void MJDEC_Init(MJDEC_CFG_Type *cfg); -void MJDEC_Deinit(void); -void MJDEC_Enable(void); -void MJDEC_Disable(void); -void MJDEC_Get_Frame_Info(MJDEC_Frame_Info *info); -uint8_t MJDEC_Get_Frame_Count(void); -BL_Err_Type MJDEC_Push_Frame(uint32_t bufferMjpeg); -void MJDEC_Pop_Frame(void); -void MJDEC_Set_Frame_Threshold(uint8_t count); -void MJDEC_Set_Q_Value(uint8_t q); -void MJDEC_IntMask(MJDEC_INT_Type intType, BL_Mask_Type intMask); -void MJDEC_IntClr(MJDEC_INT_Type intType); -void MJDEC_Int_Callback_Install(MJDEC_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group MJDEC_Public_Functions */ - -/*@} end of group MJDEC */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_MJDEC_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjpeg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjpeg.h deleted file mode 100644 index fa5ffc74f9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_mjpeg.h +++ /dev/null @@ -1,259 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjpeg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_MJPEG_H__ -#define __BL808_MJPEG_H__ - -#include "mjpeg_reg.h" -#include "bl808_common.h" -#include "mjpeg_q_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJPEG - * @{ - */ - -/** @defgroup MJPEG_Public_Types - * @{ - */ - -/** - * @brief MJPEG YUV format definition - */ -typedef enum { - MJPEG_YUV420, /*!< MJPEG YUV420 planar mode */ - MJPEG_YUV400, /*!< MJPEG YUV400 grey scale mode */ - MJPEG_YUV422_PLANAR, /*!< MJPEG YUV422 planar mode */ - MJPEG_YUV422_INTERLEAVE, /*!< MJPEG YUV422 interleave mode */ -} MJPEG_YUV_Mode_Type; - -/** - * @brief MJPEG burst type definition - */ -typedef enum { - MJPEG_BURST_SINGLE, /*!< MJPEG burst single */ - MJPEG_BURST_INCR4, /*!< MJPEG burst incr4 */ - MJPEG_BURST_INCR8, /*!< MJPEG burst incr8 */ - MJPEG_BURST_INCR16, /*!< MJPEG burst incr16 */ -} MJPEG_Burst_Type; - -/** - * @brief MJPEG swap mode block definition - */ -typedef enum { - MJPEG_BLOCK_0, /*!< Memory block 0 */ - MJPEG_BLOCK_1, /*!< Memory block 1 */ -} MJPEG_Swap_Block_Type; - -/** - * @brief MJPEG SW mode type definition - */ -typedef enum { - MJPEG_SW_FRAME_MODE, /*!< SW frame mode */ - MJPEG_SW_KICK_MODE, /*!< SW kick mode */ -} MJPEG_SW_Mode_Type; - -/** - * @brief MJPEG frame id type definition - */ -typedef enum { - MJPEG_FRAME_0, /*!< MJPEG frame 0 */ - MJPEG_FRAME_1, /*!< MJPEG frame 1 */ - MJPEG_FRAME_2, /*!< MJPEG frame 2 */ - MJPEG_FRAME_3, /*!< MJPEG frame 3 */ -} MJPEG_Frame_ID_Type; - -/** - * @brief MJPEG interrupt type definition - */ -typedef enum { - MJPEG_INT_NORMAL, /*!< MJPEG normal write interrupt */ - MJPEG_INT_CAM_OVERWRITE, /*!< MJPEG camera overwrite interrupt */ - MJPEG_INT_MEM_OVERWRITE, /*!< MJPEG memory overwrite interrupt */ - MJPEG_INT_FRAME_OVERWRITE, /*!< MJPEG frame overwrite interrupt */ - MJPEG_INT_BACK_IDLE, /*!< MJPEG back idle interrupt */ - MJPEG_INT_SWAP, /*!< MJPEG swap memory block interrupt */ - MJPEG_INT_ALL, /*!< MJPEG all interrupt type */ -} MJPEG_INT_Type; - -/** - * @brief MJPEG configuration strcut definition - */ -typedef struct -{ - MJPEG_Burst_Type burst; /*!< MJPEG burst type */ - MJPEG_YUV_Mode_Type yuv; /*!< MJPEG control YUV mode */ - uint8_t frameCount; /*!< 0:MJPEG will not stop, !0:MJPEG will stop when count arrived */ - uint16_t waitCount; /*!< Cycle count in wait state, default value:0x400 */ - uint32_t bufferMjpeg; /*!< MJPEG buffer addr */ - uint32_t sizeMjpeg; /*!< MJPEG buffer size */ - uint32_t bufferCamYY; /*!< CAM buffer address of Y frame */ - uint32_t sizeCamYY; /*!< CAM buffer size of Y frame */ - uint32_t bufferCamUV; /*!< CAM buffer address of UV frame */ - uint32_t sizeCamUV; /*!< CAM buffer size of UV frame */ - uint16_t resolutionX; /*!< CAM RESOLUTION X */ - uint16_t resolutionY; /*!< CAM RESOLUTION Y */ - BL_Fun_Type bitOrderEnable; /*!< MJPEG bitstream order adjustment */ - BL_Fun_Type evenOrderEnable; /*!< Enable:U is even byte of UV frame and V is odd byte of UV frame */ - BL_Fun_Type swapModeEnable; /*!< Enable or disable write swap mode */ - BL_Fun_Type readStartEnable; /*!< Enable or disable frame read start at start address */ - BL_Fun_Type reflectDmy; /*!< UV dummy with relect */ - BL_Fun_Type verticalDmy; /*!< MJPEG last half vertical block with dummy data 0x80 */ - BL_Fun_Type horizationalDmy; /*!< MJPEG last half horizational block with dummy data 0x80 */ -} MJPEG_CFG_Type; - -/** - * @brief MJPEG frame information strcut definition - */ -typedef struct -{ - uint8_t validFrames; /*!< Valid frames */ - uint16_t curFrameId; /*!< Current frame id */ - uint32_t curFrameAddr; /*!< Current frame address */ - uint32_t curFrameBytes; /*!< Current frame bytes */ - uint32_t status; /*!< MJPEG module status */ -} MJPEG_Frame_Info; - -/*@} end of group MJPEG_Public_Types */ - -/** @defgroup MJPEG_Public_Constants - * @{ - */ - -/** @defgroup MJPEG_YUV_MODE_TYPE - * @{ - */ -#define IS_MJPEG_YUV_MODE_TYPE(type) (((type) == MJPEG_YUV420) || \ - ((type) == MJPEG_YUV400) || \ - ((type) == MJPEG_YUV422_PLANAR) || \ - ((type) == MJPEG_YUV422_INTERLEAVE)) - -/** @defgroup MJPEG_BURST_TYPE - * @{ - */ -#define IS_MJPEG_BURST_TYPE(type) (((type) == MJPEG_BURST_SINGLE) || \ - ((type) == MJPEG_BURST_INCR4) || \ - ((type) == MJPEG_BURST_INCR8) || \ - ((type) == MJPEG_BURST_INCR16)) - -/** @defgroup MJPEG_SWAP_BLOCK_TYPE - * @{ - */ -#define IS_MJPEG_SWAP_BLOCK_TYPE(type) (((type) == MJPEG_BLOCK_0) || \ - ((type) == MJPEG_BLOCK_1)) - -/** @defgroup MJPEG_SW_MODE_TYPE - * @{ - */ -#define IS_MJPEG_SW_MODE_TYPE(type) (((type) == MJPEG_SW_FRAME_MODE) || \ - ((type) == MJPEG_SW_KICK_MODE)) - -/** @defgroup MJPEG_FRAME_ID_TYPE - * @{ - */ -#define IS_MJPEG_FRAME_ID_TYPE(type) (((type) == MJPEG_FRAME_0) || \ - ((type) == MJPEG_FRAME_1) || \ - ((type) == MJPEG_FRAME_2) || \ - ((type) == MJPEG_FRAME_3)) - -/** @defgroup MJPEG_INT_TYPE - * @{ - */ -#define IS_MJPEG_INT_TYPE(type) (((type) == MJPEG_INT_NORMAL) || \ - ((type) == MJPEG_INT_CAM_OVERWRITE) || \ - ((type) == MJPEG_INT_MEM_OVERWRITE) || \ - ((type) == MJPEG_INT_FRAME_OVERWRITE) || \ - ((type) == MJPEG_INT_BACK_IDLE) || \ - ((type) == MJPEG_INT_SWAP) || \ - ((type) == MJPEG_INT_ALL)) - -/*@} end of group MJPEG_Public_Constants */ - -/** @defgroup MJPEG_Public_Macros - * @{ - */ - -/*@} end of group MJPEG_Public_Macros */ - -/** @defgroup MJPEG_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void MJPEG_IRQHandler(void); -#endif -void MJPEG_Init(MJPEG_CFG_Type *cfg); -void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0); -void MJPEG_Set_Planar_Y_UV_Input(uint8_t yCamId, uint8_t uvCamId); -void MJPEG_Deinit(void); -void MJPEG_Enable(void); -void MJPEG_Disable(void); -void MJPEG_SW_Enable(MJPEG_SW_Mode_Type swType, uint8_t count); -void MJPEG_SW_Run(void); -void MJPEG_SW_Set_Kick_Block(uint16_t count); -void MJPEG_SW_Kick(void); -void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info); -uint8_t MJPEG_Get_Frame_Count(void); -void MJPEG_Pop_Frame(void); -void MJPEG_Current_Block_Clear(void); -MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void); -BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block); -BL_Sts_Type MJPEG_Current_Block_Is_Start(void); -BL_Sts_Type MJPEG_Current_Block_Is_End(void); -uint32_t MJPEG_Get_Remain_Bit(void); -void MJPEG_Set_Frame_Threshold(uint8_t count); -void MJPEG_Frame_Head_Set_Size(uint16_t size); -void MJPEG_Frame_Tail_Auto_Fill(BL_Fun_Type enable); -void MJPEG_Set_Quantize_Parameter_Y(uint8_t index, uint16_t qParameter); -void MJPEG_Set_Quantize_Parameter_UV(uint8_t index, uint16_t qParameter); -void MJPEG_Set_Quantize_Table_Y(uint16_t *qTable); -void MJPEG_Set_Quantize_Table_UV(uint16_t *qTable); -void MJPEG_Calculate_Quantize_Table(uint16_t *inputTable, uint16_t *outputTable, uint8_t quality); -void MJPEG_Quantize_SRAM_Switch(void); -uint8_t MJPEG_Get_Current_Quantize_SRAM(void); -uint8_t MJPEG_Get_Frame_Quantize_SRAM(MJPEG_Frame_ID_Type frameId); -void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask); -void MJPEG_IntClr(MJPEG_INT_Type intType); -void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun); - -/*@} end of group MJPEG_Public_Functions */ - -/*@} end of group MJPEG */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_MJPEG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_blend.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_blend.h deleted file mode 100644 index a45dd88fbb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_blend.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_blend.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef __BL808_OSD_BLEND_H__ -#define __BL808_OSD_BLEND_H__ - -#include -#include "bl808_common.h" -#include "osd_blend_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_BLEND - * @{ - */ - -/** @defgroup OSD_BLEND_Public_Macros - * @{ - */ - -/** @defgroup OSD_BLEND layer definitions - * @{ - */ - -#define OSD_A_BLEND_LAYER0 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND0_OFFSET)) -#define OSD_A_BLEND_LAYER1 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND1_OFFSET)) -#define OSD_A_BLEND_LAYER2 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND2_OFFSET)) -#define OSD_A_BLEND_LAYER3 ((osd_blend_reg_t *)(OSD_A_BASE + OSD_BLEND3_OFFSET)) - -#define OSD_B_BLEND_LAYER0 ((osd_blend_reg_t *)(OSD_B_BASE + OSD_BLEND0_OFFSET)) -#define OSD_B_BLEND_LAYER1 ((osd_blend_reg_t *)(OSD_B_BASE + OSD_BLEND1_OFFSET)) - -#define OSD_DP_BLEND_LAYER0 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND0_OFFSET)) -#define OSD_DP_BLEND_LAYER1 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND1_OFFSET)) -#define OSD_DP_BLEND_LAYER2 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND2_OFFSET)) -#define OSD_DP_BLEND_LAYER3 ((osd_blend_reg_t *)(OSD_DP_BASE + OSD_BLEND3_OFFSET)) - -/*@} end of group OSD_BLEND_Public_Macros */ - -/** @defgroup OSD_BLEND_Public_Constants - * @{ - */ - -/*@} end of group OSD_BLEND_Public_Constants */ - -/** @defgroup OSD_BLEND_Public_Types - * @{ - */ - -/** - * @brief OSD_BLEND state control definition - */ -typedef enum { - OSD_BLEND_ST_ENABLE = 0, - OSD_BLEND_ST_DISABLE, - OSD_BLEND_ST_MAX = 0x7FFFFFFF -} OSD_BLEND_ST_e; - -/* order --- from LSB to MSB. - * eg1: order_a = 3, order_rv=2, order_gy=1, order_bu=0 - * Byte Address: 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 - * ARGB8888: A1 R1 G1 B1 A0 R0 G0 B0 - * - * eg2: order_a = 3, order_rv=0, order_gy=2, order_bu=1 - * Byte Address: 0x7 0x6 0x5 0x4 0x3 0x2 0x1 0x0 - * AYUV8888: A1 Y1 U1 V1 A0 Y0 U0 V0 - */ - -typedef enum { - OSD_BLEND_COLOR_ORDER0 = 0, - OSD_BLEND_COLOR_ORDER1, - OSD_BLEND_COLOR_ORDER2, - OSD_BLEND_COLOR_ORDER3, - OSD_BLEND_COLOR_ORDER_MAX = 0x7F -} OSD_BLEND_COLOR_ORDER_e; - -typedef enum { - OSD_BLEND_COLOR_FMT_ARGB8888 = 0, - OSD_BLEND_COLOR_FMT_AYUV8888, - OSD_BLEND_COLOR_FMT_ARGB4444, - OSD_BLEND_COLOR_FMT_AYUV4444, - OSD_BLEND_COLOR_FMT_ARGB1555, - OSD_BLEND_COLOR_FMT_AYUV1555, - OSD_BLEND_COLOR_FMT_RGB565, - OSD_BLEND_COLOR_FMT_YUV655, - OSD_BLEND_COLOR_FMT_A8RGB, - OSD_BLEND_COLOR_FMT_A8YUV, - OSD_BLEND_COLOR_FMT_BPP8ARGB = 0x10, - OSD_BLEND_COLOR_FMT_BPP8AYUV, - OSD_BLEND_COLOR_FMT_BPP4ARGB, - OSD_BLEND_COLOR_FMT_BPP4AYUV, - OSD_BLEND_COLOR_FMT_BPP2ARGB, - OSD_BLEND_COLOR_FMT_BPP2AYUV, - OSD_BLEND_COLOR_FMT_BPP1ARGB, - OSD_BLEND_COLOR_FMT_BPP1AYUV, - OSD_BLEND_COLOR_FMT_CNT, - OSD_BLEND_COLOR_FMT_MAX = 0x7F -} OSD_BLEND_COLOR_FMT_e; - -/* OSD blending keying mode: nomarl or invert */ -typedef enum { - OSB_BLEND_KEYING_NORMAL = 0, - OSB_BLEND_KEYING_INVERT, - OSB_BLEND_KEYING_MAX = 0x7F -} OSB_BLEND_KEYING_MODE_e; - -typedef struct _osd_blend_color_keying_set_ { - /* obnd_layer_config3 */ - uint8_t min_key_alpha; - uint8_t max_key_alpha; - uint8_t min_key_rv; - uint8_t max_key_rv; - /* obnd_layer_config4 */ - uint8_t min_key_gy; - uint8_t max_key_gy; - uint8_t min_key_bu; - uint8_t max_key_bu; - /* obnd_layer_config5 */ - uint8_t replace_alpha; - uint8_t replace_rv; - uint8_t replace_gy; - uint8_t replace_bu; - /* obnd_layer_config6 */ - OSB_BLEND_KEYING_MODE_e mode_alpha; - OSB_BLEND_KEYING_MODE_e mode_rv; - OSB_BLEND_KEYING_MODE_e mode_gy; - OSB_BLEND_KEYING_MODE_e mode_bu; -} osd_blend_color_keying_set_t; - -/*@} end of group OSD_BLEND_Public_Types */ - -/** @defgroup OSD_BLEND_Public_Functions - * @{ - */ - -BL_Err_Type osd_blend_config_layer(osd_blend_reg_t *pblend, - uint32_t xstart, uint32_t ystart, - uint32_t xend, uint32_t yend, - uintptr_t *data, uint32_t dat_len); - -BL_Err_Type osd_blend_mem_access_line(osd_blend_reg_t *pblend, uint32_t req_hlen); -BL_Err_Type osd_blend_layer_early_commit(osd_blend_reg_t *pblend); -BL_Err_Type osd_blend_ctrl_layer(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable); - -BL_Err_Type osd_blend_set_color_format(osd_blend_reg_t *pblend, OSD_BLEND_COLOR_FMT_e fmt, - OSD_BLEND_COLOR_ORDER_e order_alpha, - OSD_BLEND_COLOR_ORDER_e order_r_v, - OSD_BLEND_COLOR_ORDER_e order_g_y, - OSD_BLEND_COLOR_ORDER_e order_b_u); - -BL_Err_Type osd_blend_set_global_alpha(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t alpha); -BL_Err_Type osd_blend_set_global_color(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t r_v, uint8_t g_y, uint8_t b_u); - -BL_Err_Type osd_blend_update_palette(osd_blend_reg_t *pblend, uint32_t color, uint8_t index); - -BL_Err_Type osd_blend_palette_keying_ctrl(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable); - -BL_Err_Type osd_blend_palette_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - OSB_BLEND_KEYING_MODE_e mode, - uint8_t replace_index, - uint8_t min_key_index, uint8_t max_key_index); - -BL_Err_Type osd_blend_palette_keying_update_range(osd_blend_reg_t *pblend, - uint8_t min_key_index, uint8_t max_key_index); - -BL_Err_Type osd_blend_color_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - osd_blend_color_keying_set_t *pset); - -/*@} end of group OSD_BLEND_Public_Functions */ - -/*@} end of group OSD_BLEND */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_OSD_BLEND_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_draw.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_draw.h deleted file mode 100644 index b424af9917..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_draw.h +++ /dev/null @@ -1,212 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_draw.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#ifndef __BL808_OSD_H__ -#define __BL808_OSD_H__ - -#include -#include "bl808_common.h" -#include "osd_draw_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_DRAW - * @{ - */ - -/** @defgroup OSD_DRAW_Public_Macros - * @{ - */ - -/** @defgroup OSD_DRAW layer definitions - * @{ - */ - -#define OSD_A_DRAW_LAYER_L ((osd_draw_reg_t *)(OSD_A_BASE + OSD_DRAW_LOW_OFFSET)) -#define OSD_A_DRAW_LAYER_H ((osd_draw_reg_t *)(OSD_A_BASE + OSD_DRAW_HIGH_OFFSET)) - -#define OSD_B_DRAW_LAYER_L ((osd_draw_reg_t *)(OSD_B_BASE + OSD_DRAW_LOW_OFFSET)) - -#define OSD_DP_DRAW_LAYER_L ((osd_draw_reg_t *)(OSD_DP_BASE + OSD_DRAW_LOW_OFFSET)) -#define OSD_DP_DRAW_LAYER_H ((osd_draw_reg_t *)(OSD_DP_BASE + OSD_DRAW_HIGH_OFFSET)) - -/*@} end of group OSD_DRAW_Public_Macros */ -/** @defgroup OSD_DRAW_Public_Constants - * @{ - */ - -/*@} end of group OSD_DRAW_Public_Constants */ - -/** @defgroup OSD_DRAW_Public_Types - * @{ - */ - -/** - * @brief OSD_DRAW rectangle style definition - */ - -typedef enum { - OSD_RECT_STYLE_HOLLOW = 0, - OSD_RECT_STYLE_SOLID = 1, - OSD_RECT_STYLE_NUM, - OSD_RECT_STYLE_MAX = 0x7fffffff -} OSD_RECT_STYLE_Type; - -/** - * @brief OSD_DRAW rectangle state definition - */ - -typedef enum { - OSD_RECT_STATE_DISABLE = 0, - OSD_RECT_STATE_ENABLE = 1, - OSD_RECT_STATE_NUM, - OSD_RECT_STATE_MAX = 0x7fffffff -} OSD_RECT_STATE_Type; - -/** - * @brief OSD_DRAW rectangle attribute definition - */ - -typedef union _osd_attribute { - struct - { - uint32_t thinkness : 8; - uint32_t v : 8; - uint32_t u : 8; - uint32_t y : 8; -#define YUV2ATTR(y, u, v) ((y << 24) | (u << 16) | (v << 8)) -#define OSD_COLOR_BLACK YUV2ATTR(0, 128, 128) -#define OSD_COLOR_WHITE YUV2ATTR(255, 128, 128) -#define OSD_COLOR_SILVER YUV2ATTR(192, 128, 128) -#define OSD_COLOR_GRAY YUV2ATTR(127, 128, 128) -#define OSD_COLOR_DIMGRAY YUV2ATTR(105, 128, 128) -#define OSD_COLOR_RED YUV2ATTR(76, 84, 255) -#define OSD_COLOR_GREEN YUV2ATTR(149, 43, 21) -#define OSD_COLOR_BLUE YUV2ATTR(29, 255, 107) -#define OSD_COLOR_SKYBLUE YUV2ATTR(188, 154, 90) -#define OSD_COLOR_INDIGO YUV2ATTR(37, 180, 154) -#define OSD_COLOR_NAVY YUV2ATTR(14, 192, 117) -#define OSD_COLOR_MAGENTA YUV2ATTR(105, 212, 234) -#define OSD_COLOR_PURPLE YUV2ATTR(52, 170, 181) -#define OSD_COLOR_CYAN YUV2ATTR(178, 171, 0) -#define OSD_COLOR_TEAL YUV2ATTR(89, 149, 64) -#define OSD_COLOR_PINK YUV2ATTR(212, 122, 158) -#define OSD_COLOR_DEEPPINK YUV2ATTR(104, 151, 235) -#define OSD_COLOR_YELLOW YUV2ATTR(255, 0, 148) -#define OSD_COLOR_GREENYELLOW YUV2ATTR(206, 37, 103) -#define OSD_COLOR_GOLD YUV2ATTR(202, 13, 165) -#define OSD_COLOR_CHOCOLATE YUV2ATTR(127, 72, 186) -#define OSD_COLOR_ORANGE YUV2ATTR(173, 30, 186) - } yuvt; - uint32_t all; -} osd_attribute_t; - -/** - * @brief OSD_DRAW rectangle axis settings - */ - -typedef struct _osd_pos_axis { - uint32_t start : 11; /* must be EVEN */ - uint32_t rsvd0 : 5; - uint32_t end : 11; /* must be ODD */ - uint32_t rsvd1 : 5; -} osd_pos_axis_t; - -/** - * @brief OSD_DRAW rectangle position definition - */ - -typedef struct _osd_rectangle_position { - osd_pos_axis_t x; - osd_pos_axis_t y; -} osd_rectangle_pos_t; - -/** - * @brief OSD_DRAW rectangle descriptor definition - */ - -typedef struct _osd_rectangle_descriptor { - osd_attribute_t attr; - osd_rectangle_pos_t pos; -} osd_rectangle_desc_t; - -/** - * @brief OSD_DRAW rectangle definition - */ - -#define OSD_RECT_DESC_OFFSET(osd_draw) ((uintptr_t)(osd_draw) + 0x4) -#define OSD_RECT_DESC_SIZE (4 * 3) -#define OSD_RECT_DESC_ADDR(osd_draw, i) (OSD_RECT_DESC_OFFSET(osd_draw) + (i)*OSD_RECT_DESC_SIZE) -#define OSD_RECT_DESC(osd_draw, i) (osd_rectangle_desc_t *)((uintptr_t)(OSD_RECT_DESC_ADDR(osd_draw, i))) - -typedef struct _osd_rectangle { - osd_rectangle_desc_t desc; - -#define OSD_MAX_LAYER (16) -#define OSD_ALL_LAYER (-1) -#define OSD_VALID_LAYER(l) ((l)&0x0F) - uint32_t layer; - OSD_RECT_STYLE_Type style; -} osd_rectangle_t; - -/*@} end of group OSD_DRAW_Public_Types */ - -/** @defgroup OSD_DRAW_Public_Functions - * @{ - */ - -BL_Err_Type osd_draw_init(osd_draw_reg_t *odraw); -BL_Err_Type osd_draw_deinit(osd_draw_reg_t *odraw); - -BL_Err_Type osd_draw_set_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state); -BL_Err_Type osd_draw_get_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type *state); -BL_Err_Type osd_draw_set_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type style); -BL_Err_Type osd_draw_get_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type *style); -BL_Err_Type osd_draw_config_rect_layer(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state, OSD_RECT_STYLE_Type style); - -BL_Err_Type osd_draw_rectangle(osd_draw_reg_t *odraw, osd_rectangle_t *rect); - -BL_Err_Type osd_draw_rectangle_onTop(osd_draw_reg_t *odraw, osd_rectangle_t *rect, uint32_t *layer); - -/*@} end of group OSD_DRAW_Public_Functions */ - -/*@} end of group OSD_DRAW */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h deleted file mode 100644 index efdd41cfa8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pwm.h +++ /dev/null @@ -1,356 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_pwm.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_PWM_H__ -#define __BL808_PWM_H__ - -#include "pwm_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup PWM - * @{ - */ - -/** @defgroup PWM_Public_Types - * @{ - */ - -/** - * @brief PWM No. type definition - */ -typedef enum { - PWM0_ID = 0, /*!< PWM Channel 0 define */ - PWM1_ID, /*!< PWM Channel 1 define */ - PWMx_ID_MAX, /*!< */ -} PWMx_ID_Type; - -/** - * @brief PWM Clock definition - */ -typedef enum { - PWM_CLK_XCLK = 0, /*!< PWM Clock source :XTAL CLK */ - PWM_CLK_BCLK, /*!< PWM Clock source :Bus CLK */ - PWM_CLK_32K, /*!< PWM Clock source :32K CLK */ -} PWM_Clk_Type; - -/** - * @brief PWM Stop Mode definition - */ -typedef enum { - PWM_STOP_ABRUPT = 0, /*!< PWM stop abrupt select define */ - PWM_STOP_GRACEFUL, /*!< PWM stop graceful select define */ -} PWM_Stop_Mode_Type; - -/** - * @brief PWM mode type def - */ -typedef enum { - PWM_POL_ACTIVE_LOW = 0, /*!< PWM active low polarity mode define */ - PWM_POL_ACTIVE_HIGH, /*!< PWM active high polarity mode define */ -} PWM_Polarity_Type; - -/** - * @brief PWM interrupt type def - */ -typedef enum { - PWM_INT_CH0L = 0, /*!< PWM Channel 0L interrupt define */ - PWM_INT_CH0H, /*!< PWM Channel 0H interrupt define */ - PWM_INT_CH1L, /*!< PWM Channel 1H interrupt define */ - PWM_INT_CH1H, /*!< PWM Channel 1H interrupt define */ - PWM_INT_CH2L, /*!< PWM Channel 2L interrupt define */ - PWM_INT_CH2H, /*!< PWM Channel 2H interrupt define */ - PWM_INT_CH3L, /*!< PWM Channel 3L interrupt define */ - PWM_INT_CH3H, /*!< PWM Channel 3H interrupt define */ - PWM_INT_PRDE, /*!< PWM Period end interrupt define */ - PWM_INT_BRK, /*!< PWM break interrupt define */ - PWM_INT_REPT, /*!< PWM repeat interrupt define */ - PWM_INT_ALL, /*!< */ -} PWM_INT_Type; - -/** - * @brief PWM Channel No. type definition - */ -typedef enum { - PWM_CH0 = 0, /*!< PWM Channel 0 define */ - PWM_CH1, /*!< PWM Channel 1 define */ - PWM_CH2, /*!< PWM Channel 2 define */ - PWM_CH3, /*!< PWM Channel 3 define */ - PWM_CHx_MAX, /*!< */ -} PWM_CHx_Type; - -/** - * @brief PWM Mode type definition - */ -typedef enum { - PWM_MODE_DISABLE = 0, /*!< PWM Mode Disable define */ - PWM_MODE_ENABLE, /*!< PWM Mode Enable define */ -} PWM_Mode_Type; - -/** - * @brief PWM Idel State type definition - */ -typedef enum { - PWM_IDLE_STATE_INACTIVE = 0, /*!< PWM Idle State Inactive define */ - PWM_IDLE_STATE_ACTIVE, /*!< PWM Idle State Active define */ -} PWM_Idle_State_Type; - -/** - * @brief PWM break State type definition - */ -typedef enum { - PWM_BREAK_STATE_INACTIVE = 0, /*!< PWM Break State Inactive define */ - PWM_BREAK_STATE_ACTIVE, /*!< PWM Break State Active define */ -} PWM_Break_State_Type; - -/** - * @brief PWM EXT break Polarity Level type definition - */ -typedef enum { - PWM_BREAK_Polarity_LOW = 0, /*!< PWM EXT Break Polarity Low Level define */ - PWM_BREAK_Polarity_HIGH, /*!< PWM EXT Break Polarity High Level define */ -} PWM_EXT_Break_Polarity_Type; - -/** - * @brief PWM Trig ADC Source type definition - */ -typedef enum { - PWM_TRIGADC_SOURCE_0L = 0, /*!< PWM Channel 0 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_0H, /*!< PWM Channel 0 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_1L, /*!< PWM Channel 1 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_1H, /*!< PWM Channel 1 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_2L, /*!< PWM Channel 2 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_2H, /*!< PWM Channel 2 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_3L, /*!< PWM Channel 3 Threshold L Trig ADC Source define */ - PWM_TRIGADC_SOURCE_3H, /*!< PWM Channel 3 Threshold H Trig ADC Source define */ - PWM_TRIGADC_SOURCE_PRDE, /*!< PWM Period End Reached Trig ADC Source define */ - PWM_TRIGADC_SOURCE_NONE = 0xF, /*!< PWM None Trig ADC Source define */ -} PWM_TrigADC_Source_Type; - -/** - * @brief PWM configuration structure type definition - */ -typedef struct { - PWM_Clk_Type clk; /*!< PWM Clock */ - PWM_Stop_Mode_Type stopMode; /*!< PWM Stop Mode */ - PWM_EXT_Break_Polarity_Type extPol; /*!< PWM EXT_Break Polarity */ - PWM_TrigADC_Source_Type adcSrc; /*!< PWM TrigADC Source */ - BL_Fun_Type stpRept; /*!< PWM Stop On Rept */ - uint16_t clkDiv; /*!< PWM clkDiv num */ - uint16_t period; /*!< PWM period set */ - uint16_t intPulseCnt; /*!< PWM interrupt pulse count */ -} PWMx_CFG_Type; - -/** - * @brief PWM CC configuration structure type definition - */ -typedef struct { - PWM_Mode_Type modP; /*!< PWM Channelx Positive PWM mode type */ - PWM_Mode_Type modN; /*!< PWM Channelx Negative PWM mode type */ - PWM_Polarity_Type polP; /*!< PWM Channelx Positive polarity type */ - PWM_Polarity_Type polN; /*!< PWM Channelx Negative polarity type */ - PWM_Idle_State_Type idlP; /*!< PWM Channelx Positive idle state type */ - PWM_Idle_State_Type idlN; /*!< PWM Channelx Negative idle state type */ - PWM_Break_State_Type brkP; /*!< PWM Channelx Positive break state type */ - PWM_Break_State_Type brkN; /*!< PWM Channelx Negative break state type */ - uint16_t thresholdL; /*!< PWM thresholdL number */ - uint16_t thresholdH; /*!< PWM thresholdH number */ - uint8_t dtg; /*!< PWM Channelx deadtime generator */ -} PWM_CHx_CFG_Type; - -/*@} end of group PWM_Public_Types */ - -/** @defgroup PWM_Public_Constants - * @{ - */ - -/** @defgroup PWMx_ID_TYPE - * @{ - */ -#define IS_PWMx_ID_TYPE(type) (((type) == PWM0_ID) || \ - ((type) == PWM1_ID) || \ - ((type) == PWM_CH_MAX)) - -/** @defgroup PWM_CLK_TYPE - * @{ - */ -#define IS_PWM_CLK_TYPE(type) (((type) == PWM_CLK_XCLK) || \ - ((type) == PWM_CLK_BCLK) || \ - ((type) == PWM_CLK_32K)) - -/** @defgroup PWM_STOP_MODE_TYPE - * @{ - */ -#define IS_PWM_STOP_MODE_TYPE(type) (((type) == PWM_STOP_ABRUPT) || \ - ((type) == PWM_STOP_GRACEFUL)) - -/** @defgroup PWM_POLARITY_TYPE - * @{ - */ -#define IS_PWM_POLARITY_TYPE(type) (((type) == PWM_POL_ACTIVE_LOW) || \ - ((type) == PWM_POL_ACTIVE_HIGH)) - -/** @defgroup PWM_INT_TYPE - * @{ - */ -#define IS_PWM_INT_TYPE(type) (((type) == PWM_INT_CH0L) || \ - ((type) == PWM_INT_CH0H) || \ - ((type) == PWM_INT_CH1L) || \ - ((type) == PWM_INT_CH1H) || \ - ((type) == PWM_INT_CH2L) || \ - ((type) == PWM_INT_CH2H) || \ - ((type) == PWM_INT_CH3L) || \ - ((type) == PWM_INT_CH3H) || \ - ((type) == PWM_INT_PRDE) || \ - ((type) == PWM_INT_BRK) || \ - ((type) == PWM_INT_REPT) || \ - ((type) == PWM_INT_ALL)) - -/** @defgroup PWM_CHx_TYPE - * @{ - */ -#define IS_PWM_CHx_TYPE(type) (((type) == PWM_CH0) || \ - ((type) == PWM_CH1) || \ - ((type) == PWM_CH2) || \ - ((type) == PWM_CH3) || \ - ((type) == PWM_CH_MAX)) - -/** @defgroup PWM_MODE_TYPE - * @{ - */ -#define IS_PWM_MODE_TYPE(type) (((type) == PWM_MODE_DISABLE) || \ - ((type) == PWM_Mode_ENABLE)) - -/** @defgroup PWM_IDLE_STATE_TYPE - * @{ - */ -#define IS_PWM_IDLE_STATE_TYPE(type) (((type) == PWM_IDLE_STATE_INACTIVE) || \ - ((type) == PWM_IDLE_STATE_ACTIVE)) - -/** @defgroup PWM_BREAK_STATE_TYPE - * @{ - */ -#define IS_PWM_BREAK_STATE_TYPE(type) (((type) == PWM_BREAK_STATE_INACTIVE) || \ - ((type) == PWM_BREAK_STATE_ACTIVE)) - -/** @defgroup PWM_EXT_BREAK_POLARITY_TYPE - * @{ - */ -#define IS_PWM_EXT_BREAK_POLARITY_TYPE(type) (((type) == PWM_BREAK_Polarity_LOW) || \ - ((type) == PWM_BREAK_Polarity_HIGH)) - -/** @defgroup PWM_TRIGADC_SOURCE_TYPE - * @{ - */ -#define IS_PWM_TRIGADC_SOURCE_TYPE(type) (((type) == PWM_TRIGADC_SOURCE_0L) || \ - ((type) == PWM_TRIGADC_SOURCE_0H) || \ - ((type) == PWM_TRIGADC_SOURCE_1L) || \ - ((type) == PWM_TRIGADC_SOURCE_1H) || \ - ((type) == PWM_TRIGADC_SOURCE_2L) || \ - ((type) == PWM_TRIGADC_SOURCE_2H) || \ - ((type) == PWM_TRIGADC_SOURCE_3L) || \ - ((type) == PWM_TRIGADC_SOURCE_3H) || \ - ((type) == PWM_TRIGADC_SOURCE_PRDE) || \ - ((type) == PWM_TRIGADC_SOURCE_NONE)) - -/*@} end of group PWM_Public_Constants */ - -/** @defgroup PWM_Public_Macros - * @{ - */ -#define IS_PWMx_ID(CH) ((CH) < PWMx_ID_MAX) -#define IS_PWM_CHx(CH) ((CH) < PWM_CHx_MAX) - -/*@} end of group PWM_Public_Macros */ - -/** @defgroup PWM_Public_Functions - * @{ - */ - -/** - * @brief PWM Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void PWM_IRQHandler(void); -#endif -BL_Err_Type PWMx_Init(PWMx_ID_Type pwmx, PWMx_CFG_Type *cfg); -void PWMx_Div_Set(PWMx_ID_Type id, uint16_t div); -void PWMx_Period_Set(PWMx_ID_Type id, uint16_t period); -void PWMx_Period_Get(PWMx_ID_Type id, uint16_t *period); -void PWMx_Enable(PWMx_ID_Type id); -void PWMx_Disable(PWMx_ID_Type id); -void PWM_Channelx_Init(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_CHx_CFG_Type *cfg); -void PWM_Channelx_Threshold_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL, uint16_t thresholdH); -void PWM_Channelx_ThresholdL_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL); -void PWM_Channelx_ThresholdH_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdH); -void PWM_Channelx_Threshold_Get(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t *thresholdL, uint16_t *thresholdH); -void PWM_Channelx_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type modP, PWM_Mode_Type modN); -void PWM_Channelx_Positive_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod); -void PWM_Channelx_Negative_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod); -void PWM_Channelx_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type polP, PWM_Polarity_Type polN); -void PWM_Channelx_Positive_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol); -void PWM_Channelx_Negative_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol); -void PWM_Channelx_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idlP, PWM_Idle_State_Type idlN); -void PWM_Channelx_Positive_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl); -void PWM_Channelx_Negative_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl); -void PWM_Channelx_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brkP, PWM_Break_State_Type brkN); -void PWM_Channelx_Positive_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk); -void PWM_Channelx_Negative_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk); -void PWM_Config1_Set(PWMx_ID_Type id, uint32_t cfg); -void PWM_Config1_Get(PWMx_ID_Type id, uint32_t *cfg); -void PWM_Channelx_Dtg_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint8_t dtg); -void PWM_SW_Break_Enable(PWMx_ID_Type id); -void PWM_SW_Break_Disable(PWMx_ID_Type id); -void PWM_EXT_Break_Enable(PWMx_ID_Type id); -void PWM_EXT_Break_Disable(PWMx_ID_Type id); -void PWM_EXT_Break_Polarity_Set(PWMx_ID_Type id, PWM_EXT_Break_Polarity_Type pol); -void PWM_TrigADC_Source_Set(PWMx_ID_Type id, PWM_TrigADC_Source_Type src); -void PWM_Int_Mask(PWMx_ID_Type id, PWM_INT_Type intType, BL_Mask_Type intMask); -void PWM_Int_Clear(PWMx_ID_Type id, PWM_INT_Type intType); -BL_Sts_Type PWM_Int_Status_Get(PWMx_ID_Type id, PWM_INT_Type intType); -#ifndef BFLB_USE_HAL_DRIVER -void PWM_Int_Callback_Install(PWMx_ID_Type id, uint32_t intType, intCallback_Type *cbFun); -void PWM_IRQHandler(void); -#endif -/*@} end of group PWM_Public_Functions */ - -/*@} end of group PWM */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_PWM_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h deleted file mode 100644 index 101c889048..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_eng.h +++ /dev/null @@ -1,778 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sec_eng.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SEC_ENG_H__ -#define __BL808_SEC_ENG_H__ - -#include "sec_eng_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_ENG - * @{ - */ - -/** @defgroup SEC_ENG_Public_Types - * @{ - */ - -/** - * @brief AES port type definition - */ -typedef enum { - SEC_ENG_AES_ID0, /*!< AES0 port define */ -} SEC_ENG_AES_ID_Type; - -/** - * @brief SHA port type definition - */ -typedef enum { - SEC_ENG_SHA_ID0, /*!< SHA0 port define */ -} SEC_ENG_SHA_ID_Type; - -/** - * @brief SHA type definition - */ -typedef enum { - SEC_ENG_SHA256, /*!< SHA type:SHA256 */ - SEC_ENG_SHA224, /*!< SHA type:SHA224 */ - SEC_ENG_SHA1, /*!< SHA type:SHA1 */ - SEC_ENG_SHA1_RSVD, /*!< SHA type:SHA1 */ - SEC_ENG_SHA512, /*!< SHA type:SHA512 */ - SEC_ENG_SHA384, /*!< SHA type:SHA384 */ - SEC_ENG_SHA512T224, /*!< SHA type:SHA512T224 */ - SEC_ENG_SHA512T256, /*!< SHA type:SHA512T156 */ - SEC_ENG_MD5, /*!< MD5 */ - SEC_ENG_CRC16, /*!< CRC-16 */ - SEC_ENG_CRC32, /*!< CRC-32 */ -} SEC_ENG_SHA_Type; - -/** - * @brief AES type definition - */ -typedef enum { - SEC_ENG_AES_ECB, /*!< AES mode type:ECB */ - SEC_ENG_AES_CTR, /*!< AES mode type:CTR */ - SEC_ENG_AES_CBC, /*!< AES mode type:CBC */ - SEC_ENG_AES_XTS, /*!< AES mode type:XTS */ -} SEC_ENG_AES_Type; - -/** - * @brief AES XTS mode type definition - */ -typedef enum { - SEC_ENG_AES_XTS_MODE1, /*!< AES xts mode type:mode1 */ - SEC_ENG_AES_XTS_MODE2, /*!< AES xts mode type:mode2 */ -} SEC_ENG_AES_XTS_MODE_Type; - -/** - * @brief AES KEY type definition - */ -typedef enum { - SEC_ENG_AES_KEY_128BITS, /*!< AES KEY type:128 bits */ - SEC_ENG_AES_KEY_256BITS, /*!< AES KEY type:256 bits */ - SEC_ENG_AES_KEY_192BITS, /*!< AES KEY type:192 bits */ - SEC_ENG_AES_DOUBLE_KEY_128BITS, /*!< AES double KEY type:128 bits */ -} SEC_ENG_AES_Key_Type; - -/** - * @brief AES CTR mode counter type definition - */ -typedef enum { - SEC_ENG_AES_COUNTER_BYTE_4, /*!< AES CTR mode counter type:4 bytes */ - SEC_ENG_AES_COUNTER_BYTE_1, /*!< AES CTR mode counter type:1 byte */ - SEC_ENG_AES_COUNTER_BYTE_2, /*!< AES CTR mode counter type:2 bytes */ - SEC_ENG_AES_COUNTER_BYTE_3, /*!< AES CTR mode counter type:3 bytes */ -} SEC_ENG_AES_Counter_Type; - -/** - * @brief AES use new or old value type definition - */ -typedef enum { - SEC_ENG_AES_USE_NEW, /*!< Use new value */ - SEC_ENG_AES_USE_OLD, /*!< Use old value same as last one */ -} SEC_ENG_AES_ValueUsed_Type; - -/** - * @brief AES KEY source type definition - */ -typedef enum { - SEC_ENG_AES_KEY_SW, /*!< AES KEY from software */ - SEC_ENG_AES_KEY_HW, /*!< AES KEY from hardware */ -} SEC_ENG_AES_Key_Src_Type; - -/** - * @brief AES KEY source type definition - */ -typedef enum { - SEC_ENG_AES_ENCRYPTION, /*!< AES encryption */ - SEC_ENG_AES_DECRYPTION, /*!< AES decryption */ -} SEC_ENG_AES_EnDec_Type; - -/** - * @brief AES PKA register size type definition - */ -typedef enum { - SEC_ENG_PKA_REG_SIZE_8 = 1, /*!< Register size is 8 Bytes */ - SEC_ENG_PKA_REG_SIZE_16, /*!< Register size is 16 Bytes */ - SEC_ENG_PKA_REG_SIZE_32, /*!< Register size is 32 Bytes */ - SEC_ENG_PKA_REG_SIZE_64, /*!< Register size is 64 Bytes */ - SEC_ENG_PKA_REG_SIZE_96, /*!< Register size is 96 Bytes */ - SEC_ENG_PKA_REG_SIZE_128, /*!< Register size is 128 Bytes */ - SEC_ENG_PKA_REG_SIZE_192, /*!< Register size is 192 Bytes */ - SEC_ENG_PKA_REG_SIZE_256, /*!< Register size is 256 Bytes */ - SEC_ENG_PKA_REG_SIZE_384, /*!< Register size is 384 Bytes */ - SEC_ENG_PKA_REG_SIZE_512, /*!< Register size is 512 Bytes */ -} SEC_ENG_PKA_REG_SIZE_Type; - -/** - * @brief AES PKA register size type definition - */ -typedef enum { - SEC_ENG_PKA_OP_PPSEL, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MOD2N = 0x11, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LDIV2N = 0x12, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LMUL2N = 0x13, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LDIV = 0x14, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LSQR = 0x15, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LMUL = 0x16, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LSUB = 0x17, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LADD = 0x18, /*!< PKA operation type */ - SEC_ENG_PKA_OP_LCMP = 0x19, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MDIV2 = 0x21, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MINV = 0x22, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MEXP = 0x23, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MSQR = 0x24, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MMUL = 0x25, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MREM = 0x26, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MSUB = 0x27, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MADD = 0x28, /*!< PKA operation type */ - SEC_ENG_PKA_OP_RESIZE = 0x31, /*!< PKA operation type */ - SEC_ENG_PKA_OP_MOVDAT = 0x32, /*!< PKA operation type */ - SEC_ENG_PKA_OP_NLIR = 0x33, /*!< PKA operation type */ - SEC_ENG_PKA_OP_SLIR = 0x34, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CLIR = 0x35, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CFLIRI_BUFFER = 0x36, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CTLIRI_PLD = 0x37, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CFLIR_BUFFER = 0x38, /*!< PKA operation type */ - SEC_ENG_PKA_OP_CTLIR_PLD = 0x39, /*!< PKA operation type */ -} SEC_ENG_PKA_OP_Type; - -/** - * @brief Sec Eng Interrupt Type Def - */ -typedef enum { - SEC_ENG_INT_TRNG, /*!< Sec Eng Trng Interrupt Type */ - SEC_ENG_INT_AES, /*!< Sec Eng Aes Interrupt Type */ - SEC_ENG_INT_SHA, /*!< Sec Eng Sha Interrupt Type */ - SEC_ENG_INT_PKA, /*!< Sec Eng Pka Interrupt Type */ - SEC_ENG_INT_CDET, /*!< Sec Eng Cdet Interrupt Type */ - SEC_ENG_INT_GMAC, /*!< Sec Eng Gmac Interrupt Type */ - SEC_ENG_INT_ALL, /*!< Sec Eng All Interrupt Types */ -} SEC_ENG_INT_Type; - -/** - * @brief SEC_ENG SHA256 context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint32_t *shaPadding; /*!< Padding data */ - uint8_t shaFeed; /*!< Sha has feed data */ -} SEC_Eng_SHA256_Ctx; - -/** - * @brief SEC_ENG SHA512 context - */ -typedef struct -{ - uint64_t total[2]; /*!< Number of bytes processed */ - uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint64_t *shaPadding; /*!< Padding data */ - uint8_t shaFeed; /*!< Sha has feed data */ -} SEC_Eng_SHA512_Ctx; - -/** - * @brief SEC_ENG MD5 context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *md5Buf; /*!< Data not processed but in this temp buffer */ - uint32_t *md5Padding; /*!< Padding data */ - uint8_t md5Feed; /*!< md5 has feed data */ -} SEC_Eng_MD5_Ctx; - -/** - * @brief SEC_ENG SHA256 link mode context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint32_t *shaPadding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} SEC_Eng_SHA256_Link_Ctx; - -/** - * @brief SEC_ENG MD5 link mode context - */ -typedef struct -{ - uint64_t total[2]; /*!< Number of bytes processed */ - uint64_t *shaBuf; /*!< Data not processed but in this temp buffer */ - uint64_t *shaPadding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} SEC_Eng_SHA512_Link_Ctx; - -/** - * @brief SEC_ENG SHA256 link mode context - */ -typedef struct -{ - uint32_t total[2]; /*!< Number of bytes processed */ - uint32_t *md5Buf; /*!< Data not processed but in this temp buffer */ - uint32_t *md5Padding; /*!< Padding data */ - uint32_t linkAddr; /*!< Link configure address */ -} SEC_Eng_MD5_Link_Ctx; - -/** - * @brief SEC_ENG AES context - */ -typedef struct -{ - uint8_t aesFeed; /*!< AES has feed data */ - SEC_ENG_AES_Type mode; /*!< AES mode */ -} SEC_Eng_AES_Ctx; - -/** - * @brief SEC_ENG SHA link config structure type definition - */ -typedef struct -{ - uint32_t : 2; /*!< [1:0]Reserved */ - uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */ - uint32_t : 1; /*!< [5]Reserved */ - uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */ - uint32_t : 2; /*!< [8:7]Reserved */ - uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t shaIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t shaModeExt : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */ - uint32_t : 2; /*!< [15:14]Reserved */ - uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */ - uint32_t shaSrcAddr; /*!< Message source address */ - uint32_t result[16]; /*!< Result of SHA */ -} __attribute__((aligned(4))) SEC_Eng_SHA_Link_Config_Type; - -/** - * @brief SEC_ENG SHA link config structure type definition - */ -typedef struct -{ - uint32_t : 2; /*!< [1:0]Reserved */ - uint32_t shaMode : 3; /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */ - uint32_t : 1; /*!< [5]Reserved */ - uint32_t shaHashSel : 1; /*!< [6]New hash or accumulate last hash */ - uint32_t : 2; /*!< [8:7]Reserved */ - uint32_t shaIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t shaIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t shaModeExt : 2; /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */ - uint32_t : 2; /*!< [15:14]Reserved */ - uint32_t shaMsgLen : 16; /*!< [31:16]Number of 512-bit block */ - uint32_t shaSrcAddr; /*!< Message source address */ - uint32_t poly; /*!< poly of CRC */ - uint32_t dout_inv : 1; /*!< [0]dout inv of CRC */ - uint32_t dout_ref : 1; /*!< [1]dout ref of CRC */ - uint32_t din_ref : 1; /*!< [2]din ref of CRC */ - uint32_t : 29; /*!< [31:3]Reserved */ - uint32_t ivAndHash; /*!< CRC hash and also used as iv in 1st block */ -} __attribute__((aligned(4))) SEC_Eng_CRC_Link_Config_Type; - -/** - * @brief SEC_ENG AES link config structure type definition - */ -typedef struct -{ - uint32_t : 3; /*!< [2:0]Reserved */ - uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ - uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ - uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ - uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ - uint32_t : 1; /*!< [8]Reserved */ - uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ - uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ - uint32_t aesXTS : 1; /*!< [15]XTS mode select */ - uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t aesSrcAddr; /*!< Message source address */ - uint32_t aesDstAddr; /*!< Message destination address */ - uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ - uint32_t aesIV1; /*!< Big endian initial vector */ - uint32_t aesIV2; /*!< Big endian initial vector */ - uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ - uint32_t aesKey0; /*!< Big endian aes key(aes-128/256 key MSB) */ - uint32_t aesKey1; /*!< Big endian aes key */ - uint32_t aesKey2; /*!< Big endian aes key */ - uint32_t aesKey3; /*!< Big endian aes key(aes-128 key LSB) */ - uint32_t aesKey4; /*!< Big endian aes key */ - uint32_t aesKey5; /*!< Big endian aes key */ - uint32_t aesKey6; /*!< Big endian aes key */ - uint32_t aesKey7; /*!< Big endian aes key(aes-256 key LSB) */ -} __attribute__((aligned(4))) SEC_Eng_AES_Link_Config_Type; - -/** - * @brief SEC_ENG AES XTS mode1 link config structure type definition - */ -typedef struct -{ - uint32_t : 3; /*!< [2:0]Reserved */ - uint32_t aesMode : 2; /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */ - uint32_t aesDecEn : 1; /*!< [5]Encode or decode */ - uint32_t aesDecKeySel : 1; /*!< [6]Use new key or use same key as last one */ - uint32_t aesHwKeyEn : 1; /*!< [7]Enable or disable using hardware hey */ - uint32_t : 1; /*!< [8]Reserved */ - uint32_t aesIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t aesIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 1; /*!< [11]Reserved */ - uint32_t aesBlockMode : 2; /*!< [13:12]ECB/CTR/CBC mode select */ - uint32_t aesIVSel : 1; /*!< [14]Use new iv or use same iv as last one */ - uint32_t aesXTS : 1; /*!< [15]XTS mode select */ - uint32_t aesMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t aesSrcAddr; /*!< Message source address */ - uint32_t aesDstAddr; /*!< Message destination address */ - uint32_t aesIV0; /*!< Big endian initial vector(MSB) */ - uint32_t aesIV1; /*!< Big endian initial vector */ - uint32_t aesIV2; /*!< Big endian initial vector */ - uint32_t aesIV3; /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */ - uint32_t aesKey10; /*!< Big endian aes key1(aes-128/256 key MSB) */ - uint32_t aesKey11; /*!< Big endian aes key1 */ - uint32_t aesKey12; /*!< Big endian aes key1 */ - uint32_t aesKey13; /*!< Big endian aes key1(aes-128 key LSB) */ - uint32_t aesKey14; /*!< Big endian aes key1 */ - uint32_t aesKey15; /*!< Big endian aes key1 */ - uint32_t aesKey16; /*!< Big endian aes key1 */ - uint32_t aesKey17; /*!< Big endian aes key1(aes-256 key LSB) */ - uint32_t : 16; /*!< [15:0]Reserved */ - uint32_t aesUnitLen : 16; /*!< [31:16]Big endian aes unit len */ - uint32_t aesKey20; /*!< Big endian aes key2(aes-128/256 key MSB) */ - uint32_t aesKey21; /*!< Big endian aes key2 */ - uint32_t aesKey22; /*!< Big endian aes key2 */ - uint32_t aesKey23; /*!< Big endian aes key2(aes-128 key LSB) */ - uint32_t aesKey24; /*!< Big endian aes key2 */ - uint32_t aesKey25; /*!< Big endian aes key2 */ - uint32_t aesKey26; /*!< Big endian aes key2 */ - uint32_t aesKey27; /*!< Big endian aes key2(aes-256 key LSB) */ -} __attribute__((aligned(4))) SEC_Eng_AES_XTS_Mode1_Link_Config_Type; - -/** - * @brief SEC_ENG GMAC link config structure type definition - */ -typedef struct -{ - uint32_t : 9; /*!< [8:0]reserved */ - uint32_t gmacIntClr : 1; /*!< [9]Clear interrupt */ - uint32_t gmacIntSet : 1; /*!< [10]Set interrupt */ - uint32_t : 5; /*!< [15:11]reserved */ - uint32_t gmacMsgLen : 16; /*!< [31:16]Number of 128-bit block */ - uint32_t gmacSrcAddr; /*!< Message source address */ - uint32_t gmacKey0; /*!< GMAC key */ - uint32_t gmacKey1; /*!< GMAC key */ - uint32_t gmacKey2; /*!< GMAC key */ - uint32_t gmacKey3; /*!< GMAC key */ - uint32_t result[4]; /*!< Result of GMAC */ -} __attribute__((aligned(4))) SEC_Eng_GMAC_Link_Config_Type; - -/** - * @brief SEC_ENG PKA status type definition - */ -typedef struct -{ - uint16_t primeFail : 1; /*!< [0]Prime fail */ - uint16_t errUnknown : 1; /*!< [1]Err unknown opc */ - uint16_t errOverflow : 1; /*!< [2]Err opq overflow */ - uint16_t errSrc2 : 1; /*!< [3]Err invalid src2 */ - uint16_t errSrc1 : 1; /*!< [4]Err invalid src1 */ - uint16_t errSrc0 : 1; /*!< [5]Err invalid src0 */ - uint16_t errDiv0 : 1; /*!< [6]Err div by 0 */ - uint16_t errFull : 1; /*!< [7]Err cam full */ - uint16_t lastOpc : 1; /*!< [8]Last opc */ - uint16_t opqFull : 1; /*!< [9]Opq full */ - uint16_t cmdIndex : 5; /*!< [14:10]Cmd err index */ - uint16_t errCmd : 1; /*!< [15]Err cmd */ -} SEC_Eng_PKA_Status_Type; - -/*@} end of group SEC_ENG_Public_Types */ - -/** @defgroup SEC_ENG_Public_Constants - * @{ - */ - -/** @defgroup SEC_ENG_AES_ID_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_ID_TYPE(type) (((type) == SEC_ENG_AES_ID0)) - -/** @defgroup SEC_ENG_SHA_ID_TYPE - * @{ - */ -#define IS_SEC_ENG_SHA_ID_TYPE(type) (((type) == SEC_ENG_SHA_ID0)) - -/** @defgroup SEC_ENG_SHA_TYPE - * @{ - */ -#define IS_SEC_ENG_SHA_TYPE(type) (((type) == SEC_ENG_SHA256) || \ - ((type) == SEC_ENG_SHA224) || \ - ((type) == SEC_ENG_SHA1) || \ - ((type) == SEC_ENG_SHA1_RSVD) || \ - ((type) == SEC_ENG_SHA512) || \ - ((type) == SEC_ENG_SHA384) || \ - ((type) == SEC_ENG_SHA512T224) || \ - ((type) == SEC_ENG_SHA512T256) || \ - ((type) == SEC_ENG_MD5) || \ - ((type) == SEC_ENG_CRC16) || \ - ((type) == SEC_ENG_CRC32)) - -/** @defgroup SEC_ENG_AES_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_TYPE(type) (((type) == SEC_ENG_AES_ECB) || \ - ((type) == SEC_ENG_AES_CTR) || \ - ((type) == SEC_ENG_AES_CBC) || \ - ((type) == SEC_ENG_AES_XTS)) - -/** @defgroup SEC_ENG_AES_XTS_MODE_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_XTS_MODE_TYPE(type) (((type) == SEC_ENG_AES_XTS_MODE1) || \ - ((type) == SEC_ENG_AES_XTS_MODE2)) - -/** @defgroup SEC_ENG_AES_KEY_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_KEY_TYPE(type) (((type) == SEC_ENG_AES_KEY_128BITS) || \ - ((type) == SEC_ENG_AES_KEY_256BITS) || \ - ((type) == SEC_ENG_AES_KEY_192BITS) || \ - ((type) == SEC_ENG_AES_DOUBLE_KEY_128BITS)) - -/** @defgroup SEC_ENG_AES_COUNTER_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_COUNTER_TYPE(type) (((type) == SEC_ENG_AES_COUNTER_BYTE_4) || \ - ((type) == SEC_ENG_AES_COUNTER_BYTE_1) || \ - ((type) == SEC_ENG_AES_COUNTER_BYTE_2) || \ - ((type) == SEC_ENG_AES_COUNTER_BYTE_3)) - -/** @defgroup SEC_ENG_AES_VALUEUSED_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_VALUEUSED_TYPE(type) (((type) == SEC_ENG_AES_USE_NEW) || \ - ((type) == SEC_ENG_AES_USE_OLD)) - -/** @defgroup SEC_ENG_AES_KEY_SRC_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_KEY_SRC_TYPE(type) (((type) == SEC_ENG_AES_KEY_SW) || \ - ((type) == SEC_ENG_AES_KEY_HW)) - -/** @defgroup SEC_ENG_AES_ENDEC_TYPE - * @{ - */ -#define IS_SEC_ENG_AES_ENDEC_TYPE(type) (((type) == SEC_ENG_AES_ENCRYPTION) || \ - ((type) == SEC_ENG_AES_DECRYPTION)) - -/** @defgroup SEC_ENG_PKA_REG_SIZE_TYPE - * @{ - */ -#define IS_SEC_ENG_PKA_REG_SIZE_TYPE(type) (((type) == SEC_ENG_PKA_REG_SIZE_8) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_16) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_32) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_64) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_96) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_128) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_192) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_256) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_384) || \ - ((type) == SEC_ENG_PKA_REG_SIZE_512)) - -/** @defgroup SEC_ENG_PKA_OP_TYPE - * @{ - */ -#define IS_SEC_ENG_PKA_OP_TYPE(type) (((type) == SEC_ENG_PKA_OP_PPSEL) || \ - ((type) == SEC_ENG_PKA_OP_MOD2N) || \ - ((type) == SEC_ENG_PKA_OP_LDIV2N) || \ - ((type) == SEC_ENG_PKA_OP_LMUL2N) || \ - ((type) == SEC_ENG_PKA_OP_LDIV) || \ - ((type) == SEC_ENG_PKA_OP_LSQR) || \ - ((type) == SEC_ENG_PKA_OP_LMUL) || \ - ((type) == SEC_ENG_PKA_OP_LSUB) || \ - ((type) == SEC_ENG_PKA_OP_LADD) || \ - ((type) == SEC_ENG_PKA_OP_LCMP) || \ - ((type) == SEC_ENG_PKA_OP_MDIV2) || \ - ((type) == SEC_ENG_PKA_OP_MINV) || \ - ((type) == SEC_ENG_PKA_OP_MEXP) || \ - ((type) == SEC_ENG_PKA_OP_MSQR) || \ - ((type) == SEC_ENG_PKA_OP_MMUL) || \ - ((type) == SEC_ENG_PKA_OP_MREM) || \ - ((type) == SEC_ENG_PKA_OP_MSUB) || \ - ((type) == SEC_ENG_PKA_OP_MADD) || \ - ((type) == SEC_ENG_PKA_OP_RESIZE) || \ - ((type) == SEC_ENG_PKA_OP_MOVDAT) || \ - ((type) == SEC_ENG_PKA_OP_NLIR) || \ - ((type) == SEC_ENG_PKA_OP_SLIR) || \ - ((type) == SEC_ENG_PKA_OP_CLIR) || \ - ((type) == SEC_ENG_PKA_OP_CFLIRI_BUFFER) || \ - ((type) == SEC_ENG_PKA_OP_CTLIRI_PLD) || \ - ((type) == SEC_ENG_PKA_OP_CFLIR_BUFFER) || \ - ((type) == SEC_ENG_PKA_OP_CTLIR_PLD)) - -/** @defgroup SEC_ENG_INT_TYPE - * @{ - */ -#define IS_SEC_ENG_INT_TYPE(type) (((type) == SEC_ENG_INT_TRNG) || \ - ((type) == SEC_ENG_INT_AES) || \ - ((type) == SEC_ENG_INT_SHA) || \ - ((type) == SEC_ENG_INT_PKA) || \ - ((type) == SEC_ENG_INT_CDET) || \ - ((type) == SEC_ENG_INT_GMAC) || \ - ((type) == SEC_ENG_INT_ALL)) - -/*@} end of group SEC_ENG_Public_Constants */ - -/** @defgroup SEC_ENG_Public_Macros - * @{ - */ -#define SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET 24 -#define SEC_ENG_PKA_STATUS_LAST_OPC_MASK 0x01000000 - -/*@} end of group SEC_ENG_Public_Macros */ - -/** @defgroup SEC_ENG_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SEC_GMAC_IRQHandler(void); -void SEC_CDET_IRQHandler(void); -void SEC_TRNG_IRQHandler(void); -void SEC_PKA_IRQHandler(void); -void SEC_AES_IRQHandler(void); -void SEC_SHA_IRQHandler(void); -#endif -void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, - uint32_t shaTmpBuf[16], uint32_t padding[16]); -void Sec_Eng_SHA512_Init(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, - uint64_t shaTmpBuf[16], uint64_t padding[16]); -void Sec_Eng_MD5_Init(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, - uint32_t md5TmpBuf[16], uint32_t padding[16]); -void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo); -BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, - uint32_t len); -BL_Err_Type Sec_Eng_SHA512_Update(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, - uint64_t len); -BL_Err_Type Sec_Eng_MD5_Update(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, - uint32_t len); -BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); -BL_Err_Type Sec_Eng_SHA512_Finish(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); -BL_Err_Type Sec_Eng_MD5_Finish(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash); -void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo); -void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo); -void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, - uint32_t shaTmpBuf[16], uint32_t padding[16]); -void Sec_Eng_SHA512_Link_Init(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, - uint64_t shaTmpBuf[16], uint64_t padding[16]); -void Sec_Eng_MD5_Link_Init(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, - uint32_t md5TmpBuf[16], uint32_t padding[16]); -void Sec_Eng_Set_MD5_Din(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_Set_MD5_Din_Be(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_Set_MD5_Dout(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_Set_MD5_Dout_BE(SEC_ENG_AES_ID_Type aesNo); -BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - const uint8_t *input, uint32_t len); -BL_Err_Type Sec_Eng_SHA512_Link_Update(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - const uint8_t *input, uint64_t len); -BL_Err_Type Sec_Eng_MD5_Link_Update(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, - const uint8_t *input, uint32_t len); -BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - uint8_t *hash); -BL_Err_Type Sec_Eng_SHA512_Link_Finish(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, - uint8_t *hash); -BL_Err_Type Sec_Eng_MD5_Link_Finish(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, - uint8_t *hash); -BL_Err_Type Sec_Eng_Group0_Request_SHA_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_SHA_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_SHA_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_SHA_Access(void); -BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, - SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType); -void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo); -void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo); -BL_Err_Type Sec_Eng_CRC16_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, - uint8_t *out); -BL_Err_Type Sec_Eng_CRC32_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, - uint8_t *out); -BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, - uint8_t *out); -void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src); -void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, - const uint8_t *iv); -void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, - const uint8_t *iv); -void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType); -BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, - uint8_t *out); -BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo); -BL_Err_Type Sec_Eng_Group0_Request_AES_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_AES_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_AES_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_AES_Access(void); -BL_Err_Type Sec_Eng_Trng_Enable(void); -void Sec_Eng_Trng_Int_Enable(void); -void Sec_Eng_Trng_Int_Disable(void); -BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]); -BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len); -void Sec_Eng_Trng_Int_Read_Trigger(void); -void Sec_Eng_Trng_Int_Read(uint8_t data[32]); -void Sec_Eng_Trng_Disable(void); -BL_Err_Type Sec_Eng_Group0_Request_Trng_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_Trng_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_Trng_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_Trng_Access(void); -void Sec_Eng_PKA_Reset(void); -void Sec_Eng_PKA_BigEndian_Enable(void); -void Sec_Eng_PKA_LittleEndian_Enable(void); -void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status); -void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, - uint8_t lastOp); -void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize); -void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp); -void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp); -void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx); -void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, - uint8_t s1RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, - uint8_t s2RegIdx, uint8_t lastOp); -void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, - uint8_t lastOp); -void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, - uint8_t lastOp); -void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, - uint8_t lastOp); -void Sec_Eng_PKA_GF2Mont(uint8_t dRegType, uint8_t dRegIdx, uint8_t sRegType, uint8_t sRegIdx, uint32_t size, - uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); -void Sec_Eng_PKA_Mont2GF(uint8_t dRegType, uint8_t dRegIdx, uint8_t aRegType, uint8_t aRegIdx, uint8_t invrRegType, - uint8_t invrRegIdx, - uint8_t tRegType, uint8_t tRegIdx, uint8_t pRegType, uint8_t pRegIdx); -BL_Err_Type Sec_Eng_Group0_Request_PKA_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_PKA_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_PKA_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_PKA_Access(void); -void Sec_Eng_GMAC_Enable_LE(void); -void Sec_Eng_GMAC_Enable_BE(void); -void Sec_Eng_GMAC_Enable_Link(void); -void Sec_Eng_GMAC_Disable_Link(void); -BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out); -BL_Err_Type Sec_Eng_Group0_Request_GMAC_Access(void); -BL_Err_Type Sec_Eng_Group0_Release_GMAC_Access(void); -BL_Err_Type Sec_Eng_Group1_Request_GMAC_Access(void); -BL_Err_Type Sec_Eng_Group1_Release_GMAC_Access(void); -void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask); -void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType); -void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun); -BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType); -/*----------*/ -void SEC_Eng_Turn_On_Sec_Ring(void); -void SEC_Eng_Turn_Off_Sec_Ring(void); -void Sec_Eng_PKA_Clear_Int(void); -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len); -/*----------*/; - -/*@} end of group SEC_ENG_Public_Functions */ - -/*@} end of group SEC_ENG */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SEC_ENG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h deleted file mode 100644 index ee315f7f98..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg.h +++ /dev/null @@ -1,106 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SF_CFG_H__ -#define __BL808_SF_CFG_H__ - -#include "string.h" -#include "bl808_glb.h" -#include "bl808_glb_gpio.h" -#include "bl808_sflash.h" -#include "bl808_sf_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Public_Types - * @{ - */ - -/*@} end of group SF_CFG_Public_Types */ - -/** @defgroup SF_CFG_Public_Constants - * @{ - */ - -/*@} end of group SF_CFG_Public_Constants */ - -/** @defgroup SF_CFG_Public_Macros - * @{ - */ -/* Flash option sf2 */ -/* Flash CLK */ -#define BFLB_EXTFLASH_CLK0_GPIO GLB_GPIO_PIN_34 -/* FLASH CS */ -#define BFLB_EXTFLASH_CS0_GPIO GLB_GPIO_PIN_35 -/* FLASH DATA */ -#define BFLB_EXTFLASH_DATA00_GPIO GLB_GPIO_PIN_36 -#define BFLB_EXTFLASH_DATA10_GPIO GLB_GPIO_PIN_37 -#define BFLB_EXTFLASH_DATA20_GPIO GLB_GPIO_PIN_38 -#define BFLB_EXTFLASH_DATA30_GPIO GLB_GPIO_PIN_39 -#define BFLB_FLASH_ID_VALID_FLAG 0x80000000 -#define BFLB_FLASH_ID_VALID_MASK 0x7FFFFFFF - -/*@} end of group SF_CFG_Public_Macros */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault); -BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin); -BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin); -uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, - SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank); -BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); -BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg); - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SF_CFG_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h deleted file mode 100644 index eea942a1e6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_ctrl.h +++ /dev/null @@ -1,470 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_ctrl.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SF_CTRL_H__ -#define __BL808_SF_CTRL_H__ - -#include "sf_ctrl_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Public_Types - * @{ - */ - -/** - * @brief Serial flash pad type definition - */ -typedef enum { - SF_CTRL_PAD1, /*!< SF Ctrl pad 1 */ - SF_CTRL_PAD2, /*!< SF Ctrl pad 2 */ - SF_CTRL_PAD3, /*!< SF Ctrl pad 3 */ -} SF_Ctrl_Pad_Type; - -/** - * @brief Serial flash config pin select type definition - */ -typedef enum { - SF_IO_EMB_SWAP_IO0_IO3 = 0x0, /*!< SF select embedded flash swap io0 with io3 */ - SF_IO_EMB_SWAP_DUAL_IO0_IO3 = 0x1, /*!< SF select embedded flash swap dual io0 with io3 */ - SF_IO_EMB_SWAP_NONE = 0x2, /*!< SF select embedded flash no swap */ - SF_IO_EMB_SWAP_NONE_DUAL_IO0 = 0x3, /*!< SF select embedded flash no swap and use dual io0 */ - SF_IO_EXT_SF2 = 0x4, /*!< SF select external flash SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 = 0x14, /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2 = 0x15, /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_NONE_AND_EXT_SF2 = 0x16, /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */ - SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2 = 0x17, /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */ -} SF_Ctrl_Pin_Select; - -/** - * @brief Serial flash select bank control type definition - */ -typedef enum { - SF_CTRL_FLASH_BANK0, /*!< SF Ctrl select flash bank0 */ - SF_CTRL_FLASH_BANK1, /*!< SF Ctrl select flash bank1 */ -} SF_Ctrl_Bank_Select; - -/** - * @brief Serial flash controller wrap mode type definition - */ -typedef enum { - SF_CTRL_WRAP_MODE_0, /*!< Cmds bypass wrap commands to macro, original mode */ - SF_CTRL_WRAP_MODE_1, /*!< Cmds handle wrap commands, original mode */ - SF_CTRL_WRAP_MODE_2, /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */ - SF_CTRL_WRAP_MODE_3, /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */ -} SF_Ctrl_Wrap_Mode; - -/** - * @brief Serail flash controller wrap mode len type definition - */ -typedef enum { - SF_CTRL_WRAP_LEN_8, /*!< SF Ctrl wrap length: 8 */ - SF_CTRL_WRAP_LEN_16, /*!< SF Ctrl wrap length: 16 */ - SF_CTRL_WRAP_LEN_32, /*!< SF Ctrl wrap length: 32 */ - SF_CTRL_WRAP_LEN_64, /*!< SF Ctrl wrap length: 64 */ - SF_CTRL_WRAP_LEN_128, /*!< SF Ctrl wrap length: 128 */ - SF_CTRL_WRAP_LEN_256, /*!< SF Ctrl wrap length: 256 */ - SF_CTRL_WRAP_LEN_512, /*!< SF Ctrl wrap length: 512 */ - SF_CTRL_WRAP_LEN_1024, /*!< SF Ctrl wrap length: 1024 */ - SF_CTRL_WRAP_LEN_2048, /*!< SF Ctrl wrap length: 2048 */ - SF_CTRL_WRAP_LEN_4096, /*!< SF Ctrl wrap length: 4096 */ -} SF_Ctrl_Wrap_Len_Type; - -/** - * @brief Serail flash controller memory remap type define - */ -typedef enum { - SF_CTRL_ORIGINAL_MEMORY_MAP, /*!< Remap none, use two addr map when use dual flash */ - SF_CTRL_REMAP_16MB, /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */ - SF_CTRL_REMAP_8MB, /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */ - SF_CTRL_REMAP_4MB, /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */ -} SF_Ctrl_Remap_Type; - -/** - * @brief Serial flash controller owner type definition - */ -typedef enum { - SF_CTRL_OWNER_SAHB, /*!< System AHB bus control serial flash controller */ - SF_CTRL_OWNER_IAHB, /*!< I-Code AHB bus control serial flash controller */ -} SF_Ctrl_Owner_Type; - -/** - * @brief Read and write type definition - */ -typedef enum { - SF_CTRL_READ, /*!< Serail flash read command flag */ - SF_CTRL_WRITE, /*!< Serail flash write command flag */ -} SF_Ctrl_RW_Type; - -/** - * @brief Serail flash interface IO type definition - */ -typedef enum { - SF_CTRL_NIO_MODE, /*!< Normal IO mode define */ - SF_CTRL_DO_MODE, /*!< Dual Output mode define */ - SF_CTRL_QO_MODE, /*!< Quad Output mode define */ - SF_CTRL_DIO_MODE, /*!< Dual IO mode define */ - SF_CTRL_QIO_MODE, /*!< Quad IO mode define */ -} SF_Ctrl_IO_Type; - -/** - * @brief Serail flash controller interface mode type definition - */ -typedef enum { - SF_CTRL_SPI_MODE, /*!< SPI mode define */ - SF_CTRL_QPI_MODE, /*!< QPI mode define */ -} SF_Ctrl_Mode_Type; - -/** - * @brief Serail flash controller command mode type definition - */ -typedef enum { - SF_CTRL_CMD_1_LINE, /*!< Command in one line mode */ - SF_CTRL_CMD_4_LINES, /*!< Command in four lines mode */ -} SF_Ctrl_Cmd_Mode_Type; - -/** - * @brief Serail flash controller address mode type definition - */ -typedef enum { - SF_CTRL_ADDR_1_LINE, /*!< Address in one line mode */ - SF_CTRL_ADDR_2_LINES, /*!< Address in two lines mode */ - SF_CTRL_ADDR_4_LINES, /*!< Address in four lines mode */ -} SF_Ctrl_Addr_Mode_Type; - -/** - * @brief Serail flash controller dummy mode type definition - */ -typedef enum { - SF_CTRL_DUMMY_1_LINE, /*!< Dummy in one line mode */ - SF_CTRL_DUMMY_2_LINES, /*!< Dummy in two lines mode */ - SF_CTRL_DUMMY_4_LINES, /*!< Dummy in four lines mode */ -} SF_Ctrl_Dmy_Mode_Type; - -/** - * @brief Serail flash controller data mode type definition - */ -typedef enum { - SF_CTRL_DATA_1_LINE, /*!< Data in one line mode */ - SF_CTRL_DATA_2_LINES, /*!< Data in two lines mode */ - SF_CTRL_DATA_4_LINES, /*!< Data in four lines mode */ -} SF_Ctrl_Data_Mode_Type; - -/** - * @brief Serail flash controller AES mode type definition - */ -typedef enum { - SF_CTRL_AES_CTR_MODE, /*!< Serail flash AES CTR mode */ - SF_CTRL_AES_XTS_MODE, /*!< Serail flash AES XTS mode */ -} SF_Ctrl_AES_Mode_Type; - -/** - * @brief Serail flash controller AES key len type definition - */ -typedef enum { - SF_CTRL_AES_128BITS, /*!< Serail flash AES key 128 bits length */ - SF_CTRL_AES_256BITS, /*!< Serail flash AES key 256 bits length */ - SF_CTRL_AES_192BITS, /*!< Serail flash AES key 192 bits length */ - SF_CTRL_AES_128BITS_DOUBLE_KEY, /*!< Serail flash AES key 128 bits length double key */ -} SF_Ctrl_AES_Key_Type; - -/** - * @brief Serail flash controller configuration structure type definition - */ -typedef struct -{ - SF_Ctrl_Owner_Type owner; /*!< Sflash interface bus owner */ - BL_Fun_Type en32bAddr; /*!< Sflash enable 32-bits address */ - uint8_t clkDelay; /*!< Clock count for read due to pad delay */ - uint8_t clkInvert; /*!< Clock invert */ - uint8_t rxClkInvert; /*!< RX clock invert */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ -} SF_Ctrl_Cfg_Type; - -/** - * @brief SF Ctrl bank2 controller configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type sbus2Select; /*!< Select sbus2 as 2nd flash controller */ - BL_Fun_Type bank2RxClkInvertSrc; /*!< Select bank2 rx clock invert source */ - BL_Fun_Type bank2RxClkInvertSel; /*!< Select inveted bank2 rx clock */ - BL_Fun_Type bank2DelaySrc; /*!< Select bank2 read delay source */ - uint8_t bank2ClkDelay; /*!< Bank2 read delay cycle = n + 1 */ - uint8_t doDelay; /*!< Data out delay */ - uint8_t diDelay; /*!< Data in delay */ - uint8_t oeDelay; /*!< Output enable delay */ - SF_Ctrl_Remap_Type remap; /*!< Select dual flash memory remap set */ - uint8_t remapLock; /*!< Select memory remap lock */ -} SF_Ctrl_Bank2_Cfg; - -/** - * @brief SF Ctrl cmds configuration structure type definition - */ -typedef struct -{ - uint8_t ackLatency; /*!< SF Ctrl ack latency cycles */ - BL_Fun_Type cmdsCoreEn; /*!< SF Ctrl cmds core enable */ - BL_Fun_Type cmdsEn; /*!< SF Ctrl cmds enable */ - SF_Ctrl_Wrap_Mode cmdsWrapMode; /*!< SF Ctrl cmds wrap mode */ - SF_Ctrl_Wrap_Len_Type cmdsWrapLen; /*!< SF Ctrl cmds wrap length */ -} SF_Ctrl_Cmds_Cfg; - -/** - * @brief Serail flash command configuration structure type definition - */ -typedef struct -{ - uint8_t rwFlag; /*!< Read write flag */ - SF_Ctrl_Cmd_Mode_Type cmdMode; /*!< Command mode */ - SF_Ctrl_Addr_Mode_Type addrMode; /*!< Address mode */ - uint8_t addrSize; /*!< Address size */ - uint8_t dummyClks; /*!< Dummy clocks */ - SF_Ctrl_Dmy_Mode_Type dummyMode; /*!< Dummy mode */ - SF_Ctrl_Data_Mode_Type dataMode; /*!< Data mode */ - uint8_t rsv[1]; /*!< */ - uint32_t nbData; /*!< Transfer number of bytes */ - uint32_t cmdBuf[2]; /*!< Command buffer */ -} SF_Ctrl_Cmd_Cfg_Type; - -/*@} end of group SF_CTRL_Public_Types */ - -/** @defgroup SF_CTRL_Public_Constants - * @{ - */ - -/** @defgroup SF_CTRL_PAD_TYPE - * @{ - */ -#define IS_SF_CTRL_PAD_TYPE(type) (((type) == SF_CTRL_PAD1) || \ - ((type) == SF_CTRL_PAD2) || \ - ((type) == SF_CTRL_PAD3)) - -/** @defgroup SF_CTRL_PIN_SELECT - * @{ - */ -#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) || \ - ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) || \ - ((type) == SF_IO_EMB_SWAP_NONE) || \ - ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) || \ - ((type) == SF_IO_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) || \ - ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2)) - -/** @defgroup SF_CTRL_BANK_SELECT - * @{ - */ -#define IS_SF_CTRL_BANK_SELECT(type) (((type) == SF_CTRL_FLASH_BANK0) || \ - ((type) == SF_CTRL_FLASH_BANK1)) - -/** @defgroup SF_CTRL_WRAP_MODE - * @{ - */ -#define IS_SF_CTRL_WRAP_MODE(type) (((type) == SF_CTRL_WRAP_MODE_0) || \ - ((type) == SF_CTRL_WRAP_MODE_1) || \ - ((type) == SF_CTRL_WRAP_MODE_2) || \ - ((type) == SF_CTRL_WRAP_MODE_3)) - -/** @defgroup SF_CTRL_WRAP_LEN_TYPE - * @{ - */ -#define IS_SF_CTRL_WRAP_LEN_TYPE(type) (((type) == SF_CTRL_WRAP_LEN_8) || \ - ((type) == SF_CTRL_WRAP_LEN_16) || \ - ((type) == SF_CTRL_WRAP_LEN_32) || \ - ((type) == SF_CTRL_WRAP_LEN_64) || \ - ((type) == SF_CTRL_WRAP_LEN_128) || \ - ((type) == SF_CTRL_WRAP_LEN_256) || \ - ((type) == SF_CTRL_WRAP_LEN_512) || \ - ((type) == SF_CTRL_WRAP_LEN_1024) || \ - ((type) == SF_CTRL_WRAP_LEN_2048) || \ - ((type) == SF_CTRL_WRAP_LEN_4096)) - -/** @defgroup SF_CTRL_REMAP_TYPE - * @{ - */ -#define IS_SF_CTRL_REMAP_TYPE(type) (((type) == SF_CTRL_ORIGINAL_MEMORY_MAP) || \ - ((type) == SF_CTRL_REMAP_16MB) || \ - ((type) == SF_CTRL_REMAP_8MB) || \ - ((type) == SF_CTRL_REMAP_4MB)) - -/** @defgroup SF_CTRL_OWNER_TYPE - * @{ - */ -#define IS_SF_CTRL_OWNER_TYPE(type) (((type) == SF_CTRL_OWNER_SAHB) || \ - ((type) == SF_CTRL_OWNER_IAHB)) - -/** @defgroup SF_CTRL_RW_TYPE - * @{ - */ -#define IS_SF_CTRL_RW_TYPE(type) (((type) == SF_CTRL_READ) || \ - ((type) == SF_CTRL_WRITE)) - -/** @defgroup SF_CTRL_IO_TYPE - * @{ - */ -#define IS_SF_CTRL_IO_TYPE(type) (((type) == SF_CTRL_NIO_MODE) || \ - ((type) == SF_CTRL_DO_MODE) || \ - ((type) == SF_CTRL_QO_MODE) || \ - ((type) == SF_CTRL_DIO_MODE) || \ - ((type) == SF_CTRL_QIO_MODE)) - -/** @defgroup SF_CTRL_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_MODE_TYPE(type) (((type) == SF_CTRL_SPI_MODE) || \ - ((type) == SF_CTRL_QPI_MODE)) - -/** @defgroup SF_CTRL_CMD_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_CMD_MODE_TYPE(type) (((type) == SF_CTRL_CMD_1_LINE) || \ - ((type) == SF_CTRL_CMD_4_LINES)) - -/** @defgroup SF_CTRL_ADDR_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_ADDR_MODE_TYPE(type) (((type) == SF_CTRL_ADDR_1_LINE) || \ - ((type) == SF_CTRL_ADDR_2_LINES) || \ - ((type) == SF_CTRL_ADDR_4_LINES)) - -/** @defgroup SF_CTRL_DMY_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DMY_MODE_TYPE(type) (((type) == SF_CTRL_DUMMY_1_LINE) || \ - ((type) == SF_CTRL_DUMMY_2_LINES) || \ - ((type) == SF_CTRL_DUMMY_4_LINES)) - -/** @defgroup SF_CTRL_DATA_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_DATA_MODE_TYPE(type) (((type) == SF_CTRL_DATA_1_LINE) || \ - ((type) == SF_CTRL_DATA_2_LINES) || \ - ((type) == SF_CTRL_DATA_4_LINES)) - -/** @defgroup SF_CTRL_AES_MODE_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_MODE_TYPE(type) (((type) == SF_CTRL_AES_CTR_MODE) || \ - ((type) == SF_CTRL_AES_XTS_MODE)) - -/** @defgroup SF_CTRL_AES_KEY_TYPE - * @{ - */ -#define IS_SF_CTRL_AES_KEY_TYPE(type) (((type) == SF_CTRL_AES_128BITS) || \ - ((type) == SF_CTRL_AES_256BITS) || \ - ((type) == SF_CTRL_AES_192BITS) || \ - ((type) == SF_CTRL_AES_128BITS_DOUBLE_KEY)) - -/*@} end of group SF_CTRL_Public_Constants */ - -/** @defgroup SF_CTRL_Public_Macros - * @{ - */ -#define SF_CTRL_NO_ADDRESS 0xFFFFFFFF -#define NOR_FLASH_CTRL_BUF_SIZE 256 -#define NAND_FLASH_CTRL_BUF_SIZE 512 - -/*@} end of group SF_CTRL_Public_Macros */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void); -#endif -void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg); -void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg); -void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay); -void SF_Ctrl_Sbus2_Hold_Sram(void); -void SF_Ctrl_Sbus2_Release_Sram(void); -BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void); -void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad); -void SF_Ctrl_Sbus2_Revoke_replace(void); -void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert); -void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr); -uint8_t SF_Ctrl_Get_Clock_Delay(void); -void SF_Ctrl_Set_Clock_Delay(uint8_t delay); -uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void); -void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock); -void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel); -void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner); -void SF_Ctrl_Disable(void); -void SF_Ctrl_AES_Enable_BE(void); -void SF_Ctrl_AES_Enable_LE(void); -void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, - uint8_t locked); -void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType); -void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset); -void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode); -void SF_Ctrl_AES_Enable(void); -void SF_Ctrl_AES_Disable(void); -BL_Sts_Type SF_Ctrl_Is_AES_Enable(void); -void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank); -uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank); -void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock); -void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg); -void SF_Ctrl_Disable_Wrap_Access(uint8_t disable); -void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid); -BL_Sts_Type SF_Ctrl_GetBusyState(void); - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SF_CTRL_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h deleted file mode 100644 index bddd2ee875..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_spi.h +++ /dev/null @@ -1,321 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_spi.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_SPI_H__ -#define __BL808_SPI_H__ - -#include "spi_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Public_Types - * @{ - */ - -/** - * @brief SPI No. type definition - */ -typedef enum { - SPI0_ID, /*!< SPI0 port define */ - SPI0_MM_ID, /*!< MM system SPI0 port define */ - SPI_ID_MAX, /*!< SPI MAX ID define */ -} SPI_ID_Type; - -/** - * @brief SPI slave pin mode type definition - */ -typedef enum { - SPI_SLAVE_PIN_4, /*!< SPI 4-pin mode(CS is enabled) */ - SPI_SLAVE_PIN_3, /*!< SPI 3-pin mode(CS don't case) */ -} SPI_Slave_Pin_Type; - -/** - * @brief SPI byte inverse type definition - */ -typedef enum { - SPI_BYTE_INVERSE_BYTE0_FIRST, /*!< SPI byte 0 is sent out first */ - SPI_BYTE_INVERSE_BYTE3_FIRST, /*!< SPI byte 3 is sent out first */ -} SPI_BYTE_INVERSE_Type; - -/** - * @brief SPI bit inverse type definition - */ -typedef enum { - SPI_BIT_INVERSE_MSB_FIRST, /*!< SPI each byte is sent out MSB first */ - SPI_BIT_INVERSE_LSB_FIRST, /*!< SPI each byte is sent out LSB first */ -} SPI_BIT_INVERSE_Type; - -/** - * @brief SPI clock phase inverse type definition - */ -typedef enum { - SPI_CLK_PHASE_INVERSE_0, /*!< SPI clock phase inverse 0 */ - SPI_CLK_PHASE_INVERSE_1, /*!< SPI clock phase inverse 1 */ -} SPI_CLK_PHASE_INVERSE_Type; - -/** - * @brief SPI clock polarity type definition - */ -typedef enum { - SPI_CLK_POLARITY_LOW, /*!< SPI clock output low at IDLE state */ - SPI_CLK_POLARITY_HIGH, /*!< SPI clock output high at IDLE state */ -} SPI_CLK_POLARITY_Type; - -/** - * @brief SPI frame size(also the valid width for each fifo entry) type definition - */ -typedef enum { - SPI_FRAME_SIZE_8, /*!< SPI frame size 8 bit */ - SPI_FRAME_SIZE_16, /*!< SPI frame size 16 bit */ - SPI_FRAME_SIZE_24, /*!< SPI frame size 24 bit */ - SPI_FRAME_SIZE_32, /*!< SPI frame size 32 bit */ -} SPI_FrameSize_Type; - -/** - * @brief SPI work mode select type definition - */ -typedef enum { - SPI_WORK_MODE_SLAVE, /*!< SPI work at slave mode */ - SPI_WORK_MODE_MASTER, /*!< SPI work at master mode */ -} SPI_WORK_MODE_Type; - -/** - * @brief SPI enable or disable timeout judgment definition - */ -typedef enum { - SPI_TIMEOUT_DISABLE, /*!< SPI disable timeout judgment */ - SPI_TIMEOUT_ENABLE, /*!< SPI enable timeout judgment */ -} SPI_Timeout_Type; - -/** - * @brief SPI fifo overflow/underflow flag type definition - */ -typedef enum { - SPI_FIFO_TX_OVERFLOW, /*!< SPI tx fifo overflow flag */ - SPI_FIFO_TX_UNDERFLOW, /*!< SPI tx fifo underflow flag */ - SPI_FIFO_RX_OVERFLOW, /*!< SPI rx fifo overflow flag */ - SPI_FIFO_RX_UNDERFLOW, /*!< SPI rx fifo underflow flag */ -} SPI_FifoStatus_Type; - -/** - * @brief SPI interrupt type definition - */ -typedef enum { - SPI_INT_END, /*!< SPI transfer end interrupt,shared by both master and slave mode */ - SPI_INT_TX_FIFO_REQ, /*!< SPI tx fifo ready interrupt(tx fifo count > tx fifo threshold) */ - SPI_INT_RX_FIFO_REQ, /*!< SPI rx fifo ready interrupt(rx fifo count > rx fifo threshold) */ - SPI_INT_SLAVE_TIMEOUT, /*!< SPI slave mode transfer time-out interrupt,triggered when spi bus is idle for the given value */ - SPI_INT_SLAVE_UNDERRUN, /*!< SPI slave mode tx underrun error interrupt,triggered when tx is not ready during transfer */ - SPI_INT_FIFO_ERROR, /*!< SPI tx/rx fifo error interrupt(overflow/underflow) */ - SPI_INT_ALL, /*!< All the interrupt */ -} SPI_INT_Type; - -/** - * @brief SPI configuration type definition - */ -typedef struct -{ - BL_Fun_Type deglitchEnable; /*!< Enable or disable de-glitch function */ - SPI_Slave_Pin_Type slavePin; /*!< Slave 4/3 pin mode */ - BL_Fun_Type continuousEnable; /*!< Enable or disable master continuous transfer mode,enable:SS will stay asserted if next data is valid */ - SPI_BYTE_INVERSE_Type byteSequence; /*!< The byte is sent first in SPI transfer */ - SPI_BIT_INVERSE_Type bitSequence; /*!< The bit is sent first in SPI transfer */ - SPI_CLK_PHASE_INVERSE_Type clkPhaseInv; /*!< Inverse SPI clock phase */ - SPI_CLK_POLARITY_Type clkPolarity; /*!< SPI clock plarity */ - SPI_FrameSize_Type frameSize; /*!< SPI frame size(also the valid width for each fifo entry) */ -} SPI_CFG_Type; - -/** - * @brief SPI configuration type definition - */ -typedef struct -{ - uint8_t startLen; /*!< Length of start condition */ - uint8_t stopLen; /*!< Length of stop condition */ - uint8_t dataPhase0Len; /*!< Length of data phase 0,affecting clock */ - uint8_t dataPhase1Len; /*!< Length of data phase 1,affecting clock */ - uint8_t intervalLen; /*!< Length of interval between frame */ -} SPI_ClockCfg_Type; - -/** - * @brief SPI DMA configuration type definition - */ -typedef struct -{ - uint8_t txFifoThreshold; /*!< SPI tx FIFO threshold */ - uint8_t rxFifoThreshold; /*!< SPI rx FIFO threshold */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ - BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ -} SPI_FifoCfg_Type; - -/*@} end of group SPI_Public_Types */ - -/** @defgroup SPI_Public_Constants - * @{ - */ - -/** @defgroup SPI_ID_TYPE - * @{ - */ -#define IS_SPI_ID_TYPE(type) (((type) == SPI0_ID) || \ - ((type) == SPI0_MM_ID) || \ - ((type) == SPI_ID_MAX)) - -/** @defgroup SPI_SLAVE_PIN_TYPE - * @{ - */ -#define IS_SPI_SLAVE_PIN_TYPE(type) (((type) == SPI_SLAVE_PIN_4) || \ - ((type) == SPI_SLAVE_PIN_3)) - -/** @defgroup SPI_BYTE_INVERSE_TYPE - * @{ - */ -#define IS_SPI_BYTE_INVERSE_TYPE(type) (((type) == SPI_BYTE_INVERSE_BYTE0_FIRST) || \ - ((type) == SPI_BYTE_INVERSE_BYTE3_FIRST)) - -/** @defgroup SPI_BIT_INVERSE_TYPE - * @{ - */ -#define IS_SPI_BIT_INVERSE_TYPE(type) (((type) == SPI_BIT_INVERSE_MSB_FIRST) || \ - ((type) == SPI_BIT_INVERSE_LSB_FIRST)) - -/** @defgroup SPI_CLK_PHASE_INVERSE_TYPE - * @{ - */ -#define IS_SPI_CLK_PHASE_INVERSE_TYPE(type) (((type) == SPI_CLK_PHASE_INVERSE_0) || \ - ((type) == SPI_CLK_PHASE_INVERSE_1)) - -/** @defgroup SPI_CLK_POLARITY_TYPE - * @{ - */ -#define IS_SPI_CLK_POLARITY_TYPE(type) (((type) == SPI_CLK_POLARITY_LOW) || \ - ((type) == SPI_CLK_POLARITY_HIGH)) - -/** @defgroup SPI_FRAMESIZE_TYPE - * @{ - */ -#define IS_SPI_FRAMESIZE_TYPE(type) (((type) == SPI_FRAME_SIZE_8) || \ - ((type) == SPI_FRAME_SIZE_16) || \ - ((type) == SPI_FRAME_SIZE_24) || \ - ((type) == SPI_FRAME_SIZE_32)) - -/** @defgroup SPI_WORK_MODE_TYPE - * @{ - */ -#define IS_SPI_WORK_MODE_TYPE(type) (((type) == SPI_WORK_MODE_SLAVE) || \ - ((type) == SPI_WORK_MODE_MASTER)) - -/** @defgroup SPI_TIMEOUT_TYPE - * @{ - */ -#define IS_SPI_TIMEOUT_TYPE(type) (((type) == SPI_TIMEOUT_DISABLE) || \ - ((type) == SPI_TIMEOUT_ENABLE)) - -/** @defgroup SPI_FIFOSTATUS_TYPE - * @{ - */ -#define IS_SPI_FIFOSTATUS_TYPE(type) (((type) == SPI_FIFO_TX_OVERFLOW) || \ - ((type) == SPI_FIFO_TX_UNDERFLOW) || \ - ((type) == SPI_FIFO_RX_OVERFLOW) || \ - ((type) == SPI_FIFO_RX_UNDERFLOW)) - -/** @defgroup SPI_INT_TYPE - * @{ - */ -#define IS_SPI_INT_TYPE(type) (((type) == SPI_INT_END) || \ - ((type) == SPI_INT_TX_FIFO_REQ) || \ - ((type) == SPI_INT_RX_FIFO_REQ) || \ - ((type) == SPI_INT_SLAVE_TIMEOUT) || \ - ((type) == SPI_INT_SLAVE_UNDERRUN) || \ - ((type) == SPI_INT_FIFO_ERROR) || \ - ((type) == SPI_INT_ALL)) - -/*@} end of group SPI_Public_Constants */ - -/** @defgroup SPI_Public_Macros - * @{ - */ -#define SPI_RX_FIFO_SIZE 32 -#define SPI_TX_FIFO_SIZE 32 - -/*@} end of group SPI_Public_Macros */ - -/** @defgroup SPI_Public_Functions - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -void SPI0_IRQHandler(void); -void SPI1_IRQHandler(void); -#endif -BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg); -BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg); -BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg); -BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); -BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType); -BL_Err_Type SPI_SetFrameSize(SPI_ID_Type spiNo, SPI_FrameSize_Type frameSize); -BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value); -BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt); -BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint); -BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo); -BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); -BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask); -BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun); -BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType); -BL_Err_Type SPI_ReceiveData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType); -BL_Err_Type SPI_SendRecvData(SPI_ID_Type spiNo, void *sendBuff, void *recvBuff, uint32_t length, - SPI_Timeout_Type timeoutType); -uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo); -uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo); -BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType); -BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts); -BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo); -BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk); -/*@} end of group SPI_Public_Functions */ - -/*@} end of group SPI */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_SPI_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h deleted file mode 100644 index ac1c58efad..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_timer.h +++ /dev/null @@ -1,312 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_timer.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_TIMER_H__ -#define __BL808_TIMER_H__ - -#include "timer_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TIMER - * @{ - */ - -/** @defgroup TIMER_Public_Types - * @{ - */ - -/** - * @brief TIMER port type definition - */ -typedef enum { - TIMER0_ID, /*!< TIMER0 port define */ - TIMER1_ID, /*!< TIMER1 port define */ - TIMER_ID_MAX, /*!< TIMER MAX ID define */ -} TIMER_ID_Type; - -/** - * @brief Watchdog timer port type definition - */ -typedef enum { - WDT0_ID, /*!< Watchdog0 port define */ - WDT1_ID, /*!< Watchdog1 port define */ - WDT_ID_MAX, /*!< Watchdog MAX ID define */ -} WDT_ID_Type; - -/** - * @brief TIMER channel type definition - */ -typedef enum { - TIMER_CH0, /*!< TIMER channel 0 port define */ - TIMER_CH1, /*!< TIMER channel 1 port define */ - TIMER_CH_MAX, /*!< */ -} TIMER_Chan_Type; - -/** - * @brief TIMER clock source type definition - */ -typedef enum { - TIMER_CLKSRC_FCLK, /*!< TIMER clock source :System CLK */ - TIMER_CLKSRC_32K, /*!< TIMER clock source :32K CLK */ - TIMER_CLKSRC_1K, /*!< TIMER clock source :1K CLK,Only for Timer not for Watchdog */ - TIMER_CLKSRC_XTAL, /*!< TIMER clock source :XTAL CLK */ - TIMER_CLKSRC_GPIO, /*!< TIMER clock source :GPIO */ - TIMER_CLKSRC_NO, /*!< TIMER clock source :No CLK */ -} TIMER_ClkSrc_Type; - -/** - * @brief TIMER match compare ID type definition - */ -typedef enum { - TIMER_COMP_ID_0, /*!< TIMER match compare ID 0 define */ - TIMER_COMP_ID_1, /*!< TIMER match compare ID 1 define */ - TIMER_COMP_ID_2, /*!< TIMER match compare ID 2 define */ -} TIMER_Comp_ID_Type; - -/** - * @brief TIMER preload source type definition - */ -typedef enum { - TIMER_PRELOAD_TRIG_NONE, /*!< TIMER no preload source, just free run */ - TIMER_PRELOAD_TRIG_COMP0, /*!< TIMER count register preload triggered by comparator 0 */ - TIMER_PRELOAD_TRIG_COMP1, /*!< TIMER count register preload triggered by comparator 1 */ - TIMER_PRELOAD_TRIG_COMP2, /*!< TIMER count register preload triggered by comparator 2 */ -} TIMER_PreLoad_Trig_Type; - -/** - * @brief TIMER count register run mode type definition - */ -typedef enum { - TIMER_COUNT_PRELOAD, /*!< TIMER count register preload from comparator register */ - TIMER_COUNT_FREERUN, /*!< TIMER count register free run */ -} TIMER_CountMode_Type; - -/** - * @brief TIMER gpio polarity type definition - */ -typedef enum { - TIMER_GPIO_POS, /*!< TIMER gpio plarity posedge */ - TIMER_GPIO_NEG, /*!< TIMER gpio plarity negedge */ -} TIMER_GPIO_Polarity_Type; - -/** - * @brief TIMER interrupt type definition - */ -typedef enum { - TIMER_INT_COMP_0, /*!< Comparator 0 match cause interrupt */ - TIMER_INT_COMP_1, /*!< Comparator 1 match cause interrupt */ - TIMER_INT_COMP_2, /*!< Comparator 2 match cause interrupt */ - TIMER_INT_ALL, /*!< */ -} TIMER_INT_Type; - -/** - * @brief Watchdog timer interrupt type definition - */ -typedef enum { - WDT_INT, /*!< Comparator 0 match cause interrupt */ - WDT_INT_ALL, /*!< */ -} WDT_INT_Type; - -/** - * @brief TIMER configuration structure type definition - */ -typedef struct -{ - TIMER_Chan_Type timerCh; /*!< Timer channel */ - TIMER_ClkSrc_Type clkSrc; /*!< Timer clock source */ - TIMER_PreLoad_Trig_Type plTrigSrc; /*!< Timer count register preload trigger source slelect */ - TIMER_CountMode_Type countMode; /*!< Timer count mode */ - uint8_t clockDivision; /*!< Timer clock divison value */ - uint32_t matchVal0; /*!< Timer match 0 value 0 */ - uint32_t matchVal1; /*!< Timer match 1 value 0 */ - uint32_t matchVal2; /*!< Timer match 2 value 0 */ - uint32_t preLoadVal; /*!< Timer preload value */ -} TIMER_CFG_Type; - -/*@} end of group TIMER_Public_Types */ - -/** @defgroup TIMER_Public_Constants - * @{ - */ - -/** @defgroup TIMER_ID_TYPE - * @{ - */ -#define IS_TIMER_ID_TYPE(type) (((type) == TIMER0_ID) || \ - ((type) == TIMER1_ID) || \ - ((type) == TIMER_ID_MAX)) - -/** @defgroup WDT_ID_TYPE - * @{ - */ -#define IS_WDT_ID_TYPE(type) (((type) == WDT0_ID) || \ - ((type) == WDT1_ID) || \ - ((type) == WDT_ID_MAX)) - -/** @defgroup TIMER_CHAN_TYPE - * @{ - */ -#define IS_TIMER_CHAN_TYPE(type) (((type) == TIMER_CH0) || \ - ((type) == TIMER_CH1) || \ - ((type) == TIMER_CH_MAX)) - -/** @defgroup TIMER_CLKSRC_TYPE - * @{ - */ -#define IS_TIMER_CLKSRC_TYPE(type) (((type) == TIMER_CLKSRC_FCLK) || \ - ((type) == TIMER_CLKSRC_32K) || \ - ((type) == TIMER_CLKSRC_1K) || \ - ((type) == TIMER_CLKSRC_XTAL) || \ - ((type) == TIMER_CLKSRC_GPIO) || \ - ((type) == TIMER_CLKSRC_NO)) - -/** @defgroup TIMER_COMP_ID_TYPE - * @{ - */ -#define IS_TIMER_COMP_ID_TYPE(type) (((type) == TIMER_COMP_ID_0) || \ - ((type) == TIMER_COMP_ID_1) || \ - ((type) == TIMER_COMP_ID_2)) - -/** @defgroup TIMER_PRELOAD_TRIG_TYPE - * @{ - */ -#define IS_TIMER_PRELOAD_TRIG_TYPE(type) (((type) == TIMER_PRELOAD_TRIG_NONE) || \ - ((type) == TIMER_PRELOAD_TRIG_COMP0) || \ - ((type) == TIMER_PRELOAD_TRIG_COMP1) || \ - ((type) == TIMER_PRELOAD_TRIG_COMP2)) - -/** @defgroup TIMER_COUNTMODE_TYPE - * @{ - */ -#define IS_TIMER_COUNTMODE_TYPE(type) (((type) == TIMER_COUNT_PRELOAD) || \ - ((type) == TIMER_COUNT_FREERUN)) - -/** @defgroup TIMER_GPIO_POLARITY_TYPE - * @{ - */ -#define IS_TIMER_GPIO_POLARITY_TYPE(type) (((type) == TIMER_GPIO_POS) || \ - ((type) == TIMER_GPIO_NEG)) - -/** @defgroup TIMER_INT_TYPE - * @{ - */ -#define IS_TIMER_INT_TYPE(type) (((type) == TIMER_INT_COMP_0) || \ - ((type) == TIMER_INT_COMP_1) || \ - ((type) == TIMER_INT_COMP_2) || \ - ((type) == TIMER_INT_ALL)) - -/** @defgroup WDT_INT_TYPE - * @{ - */ -#define IS_WDT_INT_TYPE(type) (((type) == WDT_INT) || \ - ((type) == WDT_INT_ALL)) - -/*@} end of group TIMER_Public_Constants */ - -/** @defgroup TIMER_Public_Macros - * @{ - */ -#define WDT_ENABLE_ACCESS(baseAddr) \ - { \ - BL_WR_REG(baseAddr, TIMER_WFAR, BL_SET_REG_BITS_VAL(BL_RD_REG(baseAddr, TIMER_WFAR), TIMER_WFAR, 0xBABA)); \ - BL_WR_REG(baseAddr, TIMER_WSAR, BL_SET_REG_BITS_VAL(BL_RD_REG(baseAddr, TIMER_WSAR), TIMER_WSAR, 0xEB10)); \ - } - -/*@} end of group TIMER_Public_Macros */ - -/** @defgroup TIMER_Public_Functions - * @{ - */ - -/** - * @brief UART Functions - */ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_CH0_IRQHandler(void); -void TIMER0_CH1_IRQHandler(void); -void TIMER0_WDT_IRQHandler(void); -void TIMER1_CH0_IRQHandler(void); -void TIMER1_CH1_IRQHandler(void); -void TIMER1_WDT_IRQHandler(void); -#endif -BL_Err_Type TIMER_Init(TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg); -BL_Err_Type TIMER_DeInit(TIMER_ID_Type timerId); -uint32_t TIMER_GetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); -void TIMER_SetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val); -void TIMER_CompValueEffectImmediately(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable); -uint32_t TIMER_GetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_ResetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -BL_Sts_Type TIMER_GetMatchStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); -uint32_t TIMER_GetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_SetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val); -void TIMER_SetPreloadSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc); -void TIMER_SetCountMode(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode); -void TIMER_ClearIntStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo); -void TIMER_Enable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_Disable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_IntMask(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask); -void TIMER_GPIOSetPolarity(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity); -void TIMER_CH0_SetMeasurePulseWidth(TIMER_ID_Type timerId, BL_Fun_Type enable); -uint32_t TIMER_CH0_GetMeasurePulseWidth(TIMER_ID_Type timerId); -void TIMER_ForceClockDivision(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -void TIMER_SetPreloadTrigSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc); -void TIMER_Int_Callback_Install(TIMER_ID_Type timerId, TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun); - -void WDT_Set_Clock(WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div); -uint16_t WDT_GetMatchValue(WDT_ID_Type wdtId); -void WDT_SetCompValue(WDT_ID_Type wdtId, uint16_t val); -void WDT_CompValueEffectImmediately(WDT_ID_Type wdtId, BL_Fun_Type enable); -uint16_t WDT_GetCounterValue(WDT_ID_Type wdtId); -void WDT_ResetCounterValue(WDT_ID_Type wdtId); -BL_Sts_Type WDT_GetResetStatus(WDT_ID_Type wdtId); -void WDT_ClearResetStatus(WDT_ID_Type wdtId); -void WDT_Enable(WDT_ID_Type wdtId); -void WDT_Disable(WDT_ID_Type wdtId); -void WDT_IntMask(WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask); -void WDT_ForceClockDivision(WDT_ID_Type wdtId); -void WDT_Int_Callback_Install(WDT_ID_Type wdtId, WDT_INT_Type wdtInt, intCallback_Type *cbFun); -void WDT_GPIOSetPolarity(WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity); - -/*@} end of group TIMER_Public_Functions */ - -/*@} end of group TIMER */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_TIMER_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h deleted file mode 100644 index 3768b9298e..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_touch.h +++ /dev/null @@ -1,480 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_touch.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_TOUCH_H__ -#define __BL808_TOUCH_H__ - -#include "pds_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TOUCH - * @{ - */ - -/** @defgroup TOUCH_Public_Types - * @{ - */ - -/** - * @brief TOUCH ID type definition - */ -typedef enum { - TOUCH_ID_0, /*!< TOUCH ID 0 */ -} TOUCH_ID_Type; - -/** - * @brief TOUCH run mode select type definition - */ -typedef enum { - TOUCH_RUN_MODE_SINGLE_SHOT, /*!< TOUCH run in single shot mode */ - TOUCH_RUN_MODE_CONTINUE, /*!< TOUCH run in continue mode */ -} TOUCH_RUN_MODE_Type; - -/** - * @brief TOUCH pcharge low type definition - */ -typedef enum { - TOUCH_PCHARGE_LOW_127, /*!< for one channel, the max external cap leakage cycle is 127 */ - TOUCH_PCHARGE_LOW_255, /*!< for one channel, the max external cap leakage cycle is 255 */ - TOUCH_PCHARGE_LOW_511, /*!< for one channel, the max external cap leakage cycle is 511 */ - TOUCH_PCHARGE_LOW_1023, /*!< for one channel, the max external cap leakage cycle is 1023 */ - TOUCH_PCHARGE_LOW_2047, /*!< for one channel, the max external cap leakage cycle is 2047 */ - TOUCH_PCHARGE_LOW_4095, /*!< for one channel, the max external cap leakage cycle is 4095 */ -} TOUCH_PCHARGE_LOW_Type; - -/** - * @brief TOUCH pcharge high type definition - */ -typedef enum { - TOUCH_PCHARGE_HIGH_511, /*!< for one channel, the max external cap charge-transfer cycle is 511 */ - TOUCH_PCHARGE_HIGH_1023, /*!< for one channel, the max external cap charge-transfer cycle is 1023 */ - TOUCH_PCHARGE_HIGH_2047, /*!< for one channel, the max external cap charge-transfer cycle is 2047 */ - TOUCH_PCHARGE_HIGH_4095, /*!< for one channel, the max external cap charge-transfer cycle is 4095 */ - TOUCH_PCHARGE_HIGH_8191, /*!< for one channel, the max external cap charge-transfer cycle is 8191 */ - TOUCH_PCHARGE_HIGH_16383, /*!< for one channel, the max external cap charge-transfer cycle is 16383 */ - TOUCH_PCHARGE_HIGH_32767, /*!< for one channel, the max external cap charge-transfer cycle is 32767 */ - TOUCH_PCHARGE_HIGH_65535, /*!< for one channel, the max external cap charge-transfer cycle is 65535 */ -} TOUCH_PCHARGE_HIGH_Type; - -/** - * @brief TOUCH clock divider type definition - */ -typedef enum { - TOUCH_CLK_DIV_1, /*!< TOUCH clock div 1 */ - TOUCH_CLK_DIV_2, /*!< TOUCH clock div 2 */ - TOUCH_CLK_DIV_4, /*!< TOUCH clock div 4 */ - TOUCH_CLK_DIV_8, /*!< TOUCH clock div 8 */ - TOUCH_CLK_DIV_16, /*!< TOUCH clock div 16 */ - TOUCH_CLK_DIV_32, /*!< TOUCH clock div 32 */ - TOUCH_CLK_DIV_64, /*!< TOUCH clock div 64 */ - TOUCH_CLK_DIV_128, /*!< TOUCH clock div 128 */ -} TOUCH_CLK_DIV_Type; - -/** - * @brief TOUCH clock source select type definition - */ -typedef enum { - TOUCH_CLK_SEL_32K, /*!< select 32K as TOUCH clock */ - TOUCH_CLK_SEL_32M, /*!< select 32M as TOUCH clock */ -} TOUCH_CLK_SEL_Type; - -/** - * @brief TOUCH current source select type definition - */ -typedef enum { - TOUCH_POWER_SEL_AON, /*!< select touch current from AON bandgap,power up touch current in rf707_aon */ - TOUCH_POWER_SEL_INTERNAL_BG, /*!< select touch current from internal bandgap,power off touch current in rf707_aon */ -} TOUCH_POWER_SEL_Type; - -/** - * @brief TOUCH comparator hystersis voltage type definition - */ -typedef enum { - TOUCH_HYSTERSIS_VOLTAGE_30mV, /*!< set 30mV comparator hystersis voltage */ - TOUCH_HYSTERSIS_VOLTAGE_80mV, /*!< set 80mV comparator hystersis voltage */ -} TOUCH_HYSTERSIS_VOLTAGE_Type; - -/** - * @brief TOUCH LDO voltage control type definition - */ -typedef enum { - TOUCH_LDO_VOLTAGE_0P6V, /*!< LDO output 0.6V */ - TOUCH_LDO_VOLTAGE_0P8V, /*!< LDO output 0.8V */ - TOUCH_LDO_VOLTAGE_1P0V, /*!< LDO output 1.0V */ - TOUCH_LDO_VOLTAGE_1P2V, /*!< LDO output 1.2V */ - TOUCH_LDO_VOLTAGE_1P4V, /*!< LDO output 1.4V */ - TOUCH_LDO_VOLTAGE_1P6V, /*!< LDO output 1.6V */ - TOUCH_LDO_VOLTAGE_1P8V, /*!< LDO output 1.8V */ - TOUCH_LDO_VOLTAGE_2P0V, /*!< LDO output 2.0V */ -} TOUCH_LDO_VOLTAGE_Type; - -/** - * @brief TOUCH reference voltage control type definition - */ -typedef enum { - TOUCH_VREF_VOLTAGE_0P4V, /*!< LDO output 0.4V */ - TOUCH_VREF_VOLTAGE_0P6V, /*!< LDO output 0.6V */ - TOUCH_VREF_VOLTAGE_0P8V, /*!< LDO output 0.8V */ - TOUCH_VREF_VOLTAGE_1P0V, /*!< LDO output 1.0V */ - TOUCH_VREF_VOLTAGE_1P2V, /*!< LDO output 1.2V */ - TOUCH_VREF_VOLTAGE_1P4V, /*!< LDO output 1.4V */ - TOUCH_VREF_VOLTAGE_1P6V, /*!< LDO output 1.6V */ - TOUCH_VREF_VOLTAGE_1P8V, /*!< LDO output 1.8V */ -} TOUCH_VREF_VOLTAGE_Type; - -/** - * @brief TOUCH compensation cap control type definition - */ -typedef enum { - TOUCH_COMPENSATION_CAP_12pF, /*!< compensation cap is 12pF */ - TOUCH_COMPENSATION_CAP_13pF, /*!< compensation cap is 13pF */ - TOUCH_COMPENSATION_CAP_14pF, /*!< compensation cap is 14pF */ - TOUCH_COMPENSATION_CAP_15pF, /*!< compensation cap is 15pF */ -} TOUCH_COMPENSATION_CAP_Type; - -/** - * @brief TOUCH mode select type definition - */ -typedef enum { - TOUCH_WORK_MODE_SELF_CAP, /*!< self cap mode,each channel detection result can judge if this channel is touched */ - TOUCH_WORK_MODE_MUTUAL, /*!< mutual mode,channel 6~0 works,higher 3 channel-->column,lower 4 channel-->row */ -} TOUCH_WORK_MODE_Type; - -/** - * @brief TOUCH filter long time average order control,FLT(new)=(data_raw+FLT(former)*(2^N-1))/2^N - */ -typedef enum { - TOUCH_FILTER_ORDER_CTRL_0, /*!< N=0 (acted like disable actually) */ - TOUCH_FILTER_ORDER_CTRL_1, /*!< N=1 */ - TOUCH_FILTER_ORDER_CTRL_2, /*!< N=2 */ - TOUCH_FILTER_ORDER_CTRL_3, /*!< N=3 */ - TOUCH_FILTER_ORDER_CTRL_4, /*!< N=4 */ - TOUCH_FILTER_ORDER_CTRL_5, /*!< N=5 */ - TOUCH_FILTER_ORDER_CTRL_6, /*!< N=6 */ - TOUCH_FILTER_ORDER_CTRL_7, /*!< N=7 */ -} TOUCH_FILTER_ORDER_CTRL_Type; - -/** - * @brief TOUCH LTA long time average order control,LTA(new)=(data_raw+LTA(former)*(2^N-1))/2^N - */ -typedef enum { - TOUCH_LTA_ORDER_CTRL_0, /*!< N=0 (acted like disable actually) */ - TOUCH_LTA_ORDER_CTRL_1, /*!< N=1 */ - TOUCH_LTA_ORDER_CTRL_2, /*!< N=2 */ - TOUCH_LTA_ORDER_CTRL_3, /*!< N=3 */ - TOUCH_LTA_ORDER_CTRL_4, /*!< N=4 */ - TOUCH_LTA_ORDER_CTRL_5, /*!< N=5 */ - TOUCH_LTA_ORDER_CTRL_6, /*!< N=6 */ - TOUCH_LTA_ORDER_CTRL_7, /*!< N=7 */ -} TOUCH_LTA_ORDER_CTRL_Type; - -/** - * @brief TOUCH configuration type definition - */ -typedef struct -{ - TOUCH_CLK_SEL_Type clkSel; /*!< TOUCH clock source select */ - TOUCH_CLK_DIV_Type clkDiv; /*!< TOUCH clock divider */ - TOUCH_POWER_SEL_Type powerSel; /*!< TOUCH power source select */ - BL_Fun_Type calibrationEn; /*!< touch_channel calibration option, when enable,the counting number will be set as LTA data */ - TOUCH_WORK_MODE_Type workMode; /*!< touch_channel work mode select */ - TOUCH_RUN_MODE_Type runMode; /*!< 0-->single shot mode, 1-->continous mode */ - BL_Fun_Type ulpEn; /*!< ultra low power mode enable */ - BL_Fun_Type cycleEn; /*!< configure for low power mode with single shot, sleep for a time and then turn on */ - uint32_t sleepTime; /*!< Sleep clock_ana cycle, can save power by reduce turn on time */ - TOUCH_PCHARGE_LOW_Type pchargeLow; /*!< the max external cap leakage cycle */ - TOUCH_PCHARGE_HIGH_Type pchargeHigh; /*!< the max external cap charge-transfer cycle */ - TOUCH_LDO_VOLTAGE_Type ldoVol; /*!< TOUCH LDO voltage */ - TOUCH_VREF_VOLTAGE_Type vrefVol; /*!< TOUCH reference voltage control */ - TOUCH_HYSTERSIS_VOLTAGE_Type hystersisVol; /*!< TOUCH comparator hystersis voltage */ - TOUCH_COMPENSATION_CAP_Type compensationCap; /*!< TOUCH compensation cap control */ - BL_Fun_Type filterEn; /*!< touch_channel output data filter control, will do average(low pass filter) when enable */ - TOUCH_FILTER_ORDER_CTRL_Type filterCtrl; /*!< TOUCH filter long time average order control */ - BL_Fun_Type ltaEn; /*!< touch_channel long time average control, will do average(low pass filter) when enable */ - TOUCH_LTA_ORDER_CTRL_Type ltaCtrl; /*!< TOUCH LTA long time average order control */ - BL_Fun_Type dataHystersisEn; /*!< touch_channel hystersis data for touch action judgement, can reduce the false trigger */ - uint16_t dataHysCtrl; /*!< Hystersis data for data and dectection judgement */ -} TOUCH_CFG_Type; - -/** - * @brief TOUCH channel type definition - */ -typedef enum { - TOUCH_CHANNEL_0, /*!< TOUCH channel 0 */ - TOUCH_CHANNEL_1, /*!< TOUCH channel 1 */ - TOUCH_CHANNEL_2, /*!< TOUCH channel 2 */ - TOUCH_CHANNEL_3, /*!< TOUCH channel 3 */ - TOUCH_CHANNEL_4, /*!< TOUCH channel 4 */ - TOUCH_CHANNEL_5, /*!< TOUCH channel 5 */ - TOUCH_CHANNEL_6, /*!< TOUCH channel 6 */ - TOUCH_CHANNEL_7, /*!< TOUCH channel 7 */ - TOUCH_CHANNEL_8, /*!< TOUCH channel 8 */ - TOUCH_CHANNEL_9, /*!< TOUCH channel 9 */ - TOUCH_CHANNEL_10, /*!< TOUCH channel 10 */ - TOUCH_CHANNEL_11, /*!< TOUCH channel 11 */ -} TOUCH_CHANNEL_Type; - -/** - * @brief TOUCH channel config type definition - */ -typedef enum { - TOUCH_CHANNEL_HIGHZ_CFG_GND, /*!< channel tie to ground */ - TOUCH_CHANNEL_HIGHZ_CFG_HIGHZ, /*!< channel HighZ output */ -} TOUCH_CHANNEL_HIGHZ_CFG_Type; - -/** - * @brief TOUCH channel configuration type definition - */ -typedef struct -{ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch0; /*!< TOUCH channel 0 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch1; /*!< TOUCH channel 1 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch2; /*!< TOUCH channel 2 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch3; /*!< TOUCH channel 3 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch4; /*!< TOUCH channel 4 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch5; /*!< TOUCH channel 5 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch6; /*!< TOUCH channel 6 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch7; /*!< TOUCH channel 7 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch8; /*!< TOUCH channel 8 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch9; /*!< TOUCH channel 9 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch10; /*!< TOUCH channel 10 HighZ config */ - TOUCH_CHANNEL_HIGHZ_CFG_Type ch11; /*!< TOUCH channel 11 HighZ config */ -} TOUCH_CHANNEL_CFG_Type; - -/** - * @brief TOUCH interrupt type definition - */ -typedef enum { - TOUCH_INT_INTERRUPT, /*!< TOUCH has only one interrupt */ -} TOUCH_INT_Type; - -/*@} end of group TOUCH_Public_Types */ - -/** @defgroup TOUCH_Public_Constants - * @{ - */ - -/** @defgroup TOUCH_ID_TYPE - * @{ - */ -#define IS_TOUCH_ID_TYPE(type) (((type) == TOUCH_ID_0)) - -/** @defgroup TOUCH_RUN_MODE_TYPE - * @{ - */ -#define IS_TOUCH_RUN_MODE_TYPE(type) (((type) == TOUCH_RUN_MODE_SINGLE_SHOT) || \ - ((type) == TOUCH_RUN_MODE_CONTINUE)) - -/** @defgroup TOUCH_PCHARGE_LOW_TYPE - * @{ - */ -#define IS_TOUCH_PCHARGE_LOW_TYPE(type) (((type) == TOUCH_PCHARGE_LOW_127) || \ - ((type) == TOUCH_PCHARGE_LOW_255) || \ - ((type) == TOUCH_PCHARGE_LOW_511) || \ - ((type) == TOUCH_PCHARGE_LOW_1023) || \ - ((type) == TOUCH_PCHARGE_LOW_2047) || \ - ((type) == TOUCH_PCHARGE_LOW_4095)) - -/** @defgroup TOUCH_PCHARGE_HIGH_TYPE - * @{ - */ -#define IS_TOUCH_PCHARGE_HIGH_TYPE(type) (((type) == TOUCH_PCHARGE_HIGH_511) || \ - ((type) == TOUCH_PCHARGE_HIGH_1023) || \ - ((type) == TOUCH_PCHARGE_HIGH_2047) || \ - ((type) == TOUCH_PCHARGE_HIGH_4095) || \ - ((type) == TOUCH_PCHARGE_HIGH_8191) || \ - ((type) == TOUCH_PCHARGE_HIGH_16383) || \ - ((type) == TOUCH_PCHARGE_HIGH_32767) || \ - ((type) == TOUCH_PCHARGE_HIGH_65535)) - -/** @defgroup TOUCH_CLK_DIV_TYPE - * @{ - */ -#define IS_TOUCH_CLK_DIV_TYPE(type) (((type) == TOUCH_CLK_DIV_1) || \ - ((type) == TOUCH_CLK_DIV_2) || \ - ((type) == TOUCH_CLK_DIV_4) || \ - ((type) == TOUCH_CLK_DIV_8) || \ - ((type) == TOUCH_CLK_DIV_16) || \ - ((type) == TOUCH_CLK_DIV_32) || \ - ((type) == TOUCH_CLK_DIV_64) || \ - ((type) == TOUCH_CLK_DIV_128)) - -/** @defgroup TOUCH_CLK_SEL_TYPE - * @{ - */ -#define IS_TOUCH_CLK_SEL_TYPE(type) (((type) == TOUCH_CLK_SEL_32K) || \ - ((type) == TOUCH_CLK_SEL_32M)) - -/** @defgroup TOUCH_POWER_SEL_TYPE - * @{ - */ -#define IS_TOUCH_POWER_SEL_TYPE(type) (((type) == TOUCH_POWER_SEL_AON) || \ - ((type) == TOUCH_POWER_SEL_INTERNAL_BG)) - -/** @defgroup TOUCH_HYSTERSIS_VOLTAGE_TYPE - * @{ - */ -#define IS_TOUCH_HYSTERSIS_VOLTAGE_TYPE(type) (((type) == TOUCH_HYSTERSIS_VOLTAGE_30mV) || \ - ((type) == TOUCH_HYSTERSIS_VOLTAGE_80mV)) - -/** @defgroup TOUCH_LDO_VOLTAGE_TYPE - * @{ - */ -#define IS_TOUCH_LDO_VOLTAGE_TYPE(type) (((type) == TOUCH_LDO_VOLTAGE_0P6V) || \ - ((type) == TOUCH_LDO_VOLTAGE_0P8V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P0V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P2V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P4V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P6V) || \ - ((type) == TOUCH_LDO_VOLTAGE_1P8V) || \ - ((type) == TOUCH_LDO_VOLTAGE_2P0V)) - -/** @defgroup TOUCH_VREF_VOLTAGE_TYPE - * @{ - */ -#define IS_TOUCH_VREF_VOLTAGE_TYPE(type) (((type) == TOUCH_VREF_VOLTAGE_0P4V) || \ - ((type) == TOUCH_VREF_VOLTAGE_0P6V) || \ - ((type) == TOUCH_VREF_VOLTAGE_0P8V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P0V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P2V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P4V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P6V) || \ - ((type) == TOUCH_VREF_VOLTAGE_1P8V)) - -/** @defgroup TOUCH_COMPENSATION_CAP_TYPE - * @{ - */ -#define IS_TOUCH_COMPENSATION_CAP_TYPE(type) (((type) == TOUCH_COMPENSATION_CAP_12pF) || \ - ((type) == TOUCH_COMPENSATION_CAP_13pF) || \ - ((type) == TOUCH_COMPENSATION_CAP_14pF) || \ - ((type) == TOUCH_COMPENSATION_CAP_15pF)) - -/** @defgroup TOUCH_WORK_MODE_TYPE - * @{ - */ -#define IS_TOUCH_WORK_MODE_TYPE(type) (((type) == TOUCH_WORK_MODE_SELF_CAP) || \ - ((type) == TOUCH_WORK_MODE_MUTUAL)) - -/** @defgroup TOUCH_FILTER_ORDER_CTRL_TYPE - * @{ - */ -#define IS_TOUCH_FILTER_ORDER_CTRL_TYPE(type) (((type) == TOUCH_FILTER_ORDER_CTRL_0) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_1) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_2) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_3) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_4) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_5) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_6) || \ - ((type) == TOUCH_FILTER_ORDER_CTRL_7)) - -/** @defgroup TOUCH_LTA_ORDER_CTRL_TYPE - * @{ - */ -#define IS_TOUCH_LTA_ORDER_CTRL_TYPE(type) (((type) == TOUCH_LTA_ORDER_CTRL_0) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_1) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_2) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_3) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_4) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_5) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_6) || \ - ((type) == TOUCH_LTA_ORDER_CTRL_7)) - -/** @defgroup TOUCH_CHANNEL_TYPE - * @{ - */ -#define IS_TOUCH_CHANNEL_TYPE(type) (((type) == TOUCH_CHANNEL_0) || \ - ((type) == TOUCH_CHANNEL_1) || \ - ((type) == TOUCH_CHANNEL_2) || \ - ((type) == TOUCH_CHANNEL_3) || \ - ((type) == TOUCH_CHANNEL_4) || \ - ((type) == TOUCH_CHANNEL_5) || \ - ((type) == TOUCH_CHANNEL_6) || \ - ((type) == TOUCH_CHANNEL_7) || \ - ((type) == TOUCH_CHANNEL_8) || \ - ((type) == TOUCH_CHANNEL_9) || \ - ((type) == TOUCH_CHANNEL_10) || \ - ((type) == TOUCH_CHANNEL_11)) - -/** @defgroup TOUCH_CHANNEL_HIGHZ_CFG_TYPE - * @{ - */ -#define IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(type) (((type) == TOUCH_CHANNEL_HIGHZ_CFG_GND) || \ - ((type) == TOUCH_CHANNEL_HIGHZ_CFG_HIGHZ)) - -/** @defgroup TOUCH_INT_TYPE - * @{ - */ -#define IS_TOUCH_INT_TYPE(type) (((type) == TOUCH_INT_INTERRUPT)) - -/*@} end of group TOUCH_Public_Constants */ - -/** @defgroup TOUCH_Public_Macros - * @{ - */ - -/*@} end of group TOUCH_Public_Macros */ - -/** @defgroup TOUCH_Public_Functions - * @{ - */ -BL_Err_Type TOUCH_Init(TOUCH_ID_Type touchId, TOUCH_CFG_Type *tCfg); -BL_Err_Type TOUCH_CHANNEL_Init(TOUCH_ID_Type touchId, TOUCH_CHANNEL_CFG_Type *tChCfg, TOUCH_CHANNEL_Type tChSel); -BL_Err_Type TOUCH_Enable(TOUCH_ID_Type touchId); -BL_Err_Type TOUCH_Disable(TOUCH_ID_Type touchId); -BL_Err_Type TOUCH_SetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh, uint8_t value); -uint32_t TOUCH_GetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -uint32_t TOUCH_GetRawData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -uint32_t TOUCH_GetLtaData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -uint32_t TOUCH_GetFltData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh); -BL_Sts_Type TOUCH_GetEndStatus(TOUCH_ID_Type touchId); -BL_Err_Type TOUCH_IntEnable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType); -BL_Err_Type TOUCH_IntDisable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType); -BL_Err_Type TOUCH_IntMask(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, BL_Mask_Type intMask); -BL_Sts_Type TOUCH_GetIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh); -BL_Err_Type TOUCH_ClrIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh); -BL_Err_Type TOUCH_INT_Callback_Install(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, - intCallback_Type *cbFun); - -/*@} end of group TOUCH_Public_Functions */ - -/*@} end of group TOUCH */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_TOUCH_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h deleted file mode 100644 index 1dd38360d3..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uart.h +++ /dev/null @@ -1,359 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_uart.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_UART_H__ -#define __BL808_UART_H__ - -#include "uart_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** @defgroup UART_Public_Types - * @{ - */ - -/** - * @brief UART port type definition - */ -typedef enum { - UART0_ID, /*!< UART0 port define */ - UART1_ID, /*!< UART1 port define */ - UART2_ID, /*!< UART2 port define */ - UART0_MM_ID, /*!< MM system UART0 port define */ - UART_ID_MAX, /*!< UART MAX ID define */ -} UART_ID_Type; - -/** - * @brief UART direction type definition - */ -typedef enum { - UART_TX, /*!< UART TX Direction */ - UART_RX, /*!< UART RX Direction */ - UART_TXRX, /*!< UART TX and RX Direction */ -} UART_Direction_Type; - -/** - * @brief UART parity type definition - */ -typedef enum { - UART_PARITY_NONE, /*!< UART parity none define */ - UART_PARITY_ODD, /*!< UART parity odd define */ - UART_PARITY_EVEN, /*!< UART parity even define */ -} UART_Parity_Type; - -/** - * @brief UART data bits type definiton - */ -typedef enum { - UART_DATABITS_5, /*!< UART data bits length:5 bits */ - UART_DATABITS_6, /*!< UART data bits length:6 bits */ - UART_DATABITS_7, /*!< UART data bits length:7 bits */ - UART_DATABITS_8, /*!< UART data bits length:8 bits */ -} UART_DataBits_Type; - -/** - * @brief UART stop bits type definiton - */ -typedef enum { - UART_STOPBITS_0_5, /*!< UART data stop bits length:0.5 bits */ - UART_STOPBITS_1, /*!< UART data stop bits length:1 bits */ - UART_STOPBITS_1_5, /*!< UART data stop bits length:1.5 bits */ - UART_STOPBITS_2, /*!< UART data stop bits length:2 bits */ -} UART_StopBits_Type; - -/** - * @brief UART each data byte is send out LSB-first or MSB-first type definiton - */ -typedef enum { - UART_LSB_FIRST, /*!< UART each byte is send out LSB-first */ - UART_MSB_FIRST, /*!< UART each byte is send out MSB-first */ -} UART_ByteBitInverse_Type; - -/** - * @brief UART auto baudrate detection using codeword 0x55 or start bit definiton - */ -typedef enum { - UART_AUTOBAUD_0X55, /*!< UART auto baudrate detection using codeword 0x55 */ - UART_AUTOBAUD_STARTBIT, /*!< UART auto baudrate detection using start bit */ -} UART_AutoBaudDetection_Type; - -/** - * @brief UART RS-485 mode DE pin polarity definiton - */ -typedef enum { - UART_RS485_DE_ACTIVE_LOW, /*!< UART DE is active-low */ - UART_RS485_DE_ACTIVE_HIGH, /*!< UART DE is active-high */ -} UART_RS485Polarity_Type; - -/** - * @brief UART interrupt type definition - */ -typedef enum { - UART_INT_TX_END, /*!< UART tx transfer end interrupt */ - UART_INT_RX_END, /*!< UART rx transfer end interrupt */ - UART_INT_TX_FIFO_REQ, /*!< UART tx fifo interrupt when tx fifo count reaches,auto clear */ - UART_INT_RX_FIFO_REQ, /*!< UART rx fifo interrupt when rx fifo count reaches,auto clear */ - UART_INT_RTO, /*!< UART rx time-out interrupt */ - UART_INT_PCE, /*!< UART rx parity check error interrupt */ - UART_INT_TX_FER, /*!< UART tx fifo overflow/underflow error interrupt */ - UART_INT_RX_FER, /*!< UART rx fifo overflow/underflow error interrupt */ - UART_INT_LSE, /*!< UART rx lin mode sync field error interrupt */ - UART_INT_BCR, /*!< UART rx byte count reached interrupt */ - UART_INT_STARTBIT, /*!< UART rx auto baudrate detection finish interrupt using start bit */ - UART_INT_0X55, /*!< UART rx auto baudrate detection finish interrupt using codeword 0x55 */ - UART_INT_ALL, /*!< All the interrupt */ -} UART_INT_Type; - -/** - * @brief UART overflow or underflow type definition - */ -typedef enum { - UART_TX_OVERFLOW, /*!< UART tx fifo overflow */ - UART_TX_UNDERFLOW, /*!< UART tx fifo underflow */ - UART_RX_OVERFLOW, /*!< UART rx fifo overflow */ - UART_RX_UNDERFLOW, /*!< UART rx fifo underflow */ -} UART_Overflow_Type; - -/** - * @brief UART configuration structure type definition - */ -typedef struct -{ - uint32_t uartClk; /*!< Uart module clock */ - uint32_t baudRate; /*!< Uart baudrate */ - UART_DataBits_Type dataBits; /*!< Uart frame length of data bit */ - UART_StopBits_Type stopBits; /*!< Uart frame length of stop bit */ - UART_Parity_Type parity; /*!< Uart parity check type */ - BL_Fun_Type ctsFlowControl; /*!< Enable or disable tx CTS flow control */ - BL_Fun_Type rxDeglitch; /*!< Enable or disable rx input de-glitch function */ - BL_Fun_Type rtsSoftwareControl; /*!< Enable or disable rx RTS output SW control mode */ - BL_Fun_Type txSoftwareControl; /*!< Enable or disable tx output SW control mode */ - BL_Fun_Type txLinMode; /*!< Enable or disable tx LIN mode,LIN header will be sent before sending data */ - BL_Fun_Type rxLinMode; /*!< Enable or disable rx LIN mode,LIN header will be required and checked before receiving data */ - uint8_t txBreakBitCnt; /*!< Uart tx break bit count,additional 8 bit times will be added since LIN break field requires at - least 13 bit times */ - UART_ByteBitInverse_Type byteBitInverse; /*!< Uart each data byte is send out LSB-first or MSB-first */ -} UART_CFG_Type; - -/** - * @brief UART FIFO configuration structure type definition - */ -typedef struct -{ - uint8_t txFifoDmaThreshold; /*!< TX FIFO threshold, dma tx request will not be asserted if tx fifo count is less than this value */ - uint8_t rxFifoDmaThreshold; /*!< RX FIFO threshold, dma rx request will not be asserted if rx fifo count is less than this value */ - BL_Fun_Type txFifoDmaEnable; /*!< Enable or disable tx dma req/ack interface */ - BL_Fun_Type rxFifoDmaEnable; /*!< Enable or disable rx dma req/ack interface */ -} UART_FifoCfg_Type; - -/** - * @brief UART infrared configuration structure type definition - */ -typedef struct -{ - BL_Fun_Type txIrEnable; /*!< Enable or disable uart tx ir mode */ - BL_Fun_Type rxIrEnable; /*!< Enable or disable uart rx ir mode */ - BL_Fun_Type txIrInverse; /*!< Enable or disable inverse signal of uart tx output in ir mode */ - BL_Fun_Type rxIrInverse; /*!< Enable or disable inverse signal of uart rx input in ir mode */ - uint16_t txIrPulseStart; /*!< Set start position of uart tx ir pulse */ - uint16_t txIrPulseStop; /*!< Set stop position of uart tx ir pulse */ - uint16_t rxIrPulseStart; /*!< Set start position of uart rx pulse recovered from ir signal */ -} UART_IrCfg_Type; - -/*@} end of group UART_Public_Types */ - -/** @defgroup UART_Public_Constants - * @{ - */ - -/** @defgroup UART_ID_TYPE - * @{ - */ -#define IS_UART_ID_TYPE(type) (((type) == UART0_ID) || \ - ((type) == UART1_ID) || \ - ((type) == UART2_ID) || \ - ((type) == UART0_MM_ID) || \ - ((type) == UART_ID_MAX)) - -/** @defgroup UART_DIRECTION_TYPE - * @{ - */ -#define IS_UART_DIRECTION_TYPE(type) (((type) == UART_TX) || \ - ((type) == UART_RX) || \ - ((type) == UART_TXRX)) - -/** @defgroup UART_PARITY_TYPE - * @{ - */ -#define IS_UART_PARITY_TYPE(type) (((type) == UART_PARITY_NONE) || \ - ((type) == UART_PARITY_ODD) || \ - ((type) == UART_PARITY_EVEN)) - -/** @defgroup UART_DATABITS_TYPE - * @{ - */ -#define IS_UART_DATABITS_TYPE(type) (((type) == UART_DATABITS_5) || \ - ((type) == UART_DATABITS_6) || \ - ((type) == UART_DATABITS_7) || \ - ((type) == UART_DATABITS_8)) - -/** @defgroup UART_STOPBITS_TYPE - * @{ - */ -#define IS_UART_STOPBITS_TYPE(type) (((type) == UART_STOPBITS_1) || \ - ((type) == UART_STOPBITS_1_5) || \ - ((type) == UART_STOPBITS_2)) - -/** @defgroup UART_BYTEBITINVERSE_TYPE - * @{ - */ -#define IS_UART_BYTEBITINVERSE_TYPE(type) (((type) == UART_LSB_FIRST) || \ - ((type) == UART_MSB_FIRST)) - -/** @defgroup UART_AUTOBAUDDETECTION_TYPE - * @{ - */ -#define IS_UART_AUTOBAUDDETECTION_TYPE(type) (((type) == UART_AUTOBAUD_0X55) || \ - ((type) == UART_AUTOBAUD_STARTBIT)) - -/** @defgroup UART_RS485POLARITY_TYPE - * @{ - */ -#define IS_UART_RS485POLARITY_TYPE(type) (((type) == UART_RS485_DE_ACTIVE_LOW) || \ - ((type) == UART_RS485_DE_ACTIVE_HIGH)) - -/** @defgroup UART_INT_TYPE - * @{ - */ -#define IS_UART_INT_TYPE(type) (((type) == UART_INT_TX_END) || \ - ((type) == UART_INT_RX_END) || \ - ((type) == UART_INT_TX_FIFO_REQ) || \ - ((type) == UART_INT_RX_FIFO_REQ) || \ - ((type) == UART_INT_RTO) || \ - ((type) == UART_INT_PCE) || \ - ((type) == UART_INT_TX_FER) || \ - ((type) == UART_INT_RX_FER) || \ - ((type) == UART_INT_LSE) || \ - ((type) == UART_INT_BCR) || \ - ((type) == UART_INT_STARTBIT) || \ - ((type) == UART_INT_0X55) || \ - ((type) == UART_INT_ALL)) - -/** @defgroup UART_OVERFLOW_TYPE - * @{ - */ -#define IS_UART_OVERFLOW_TYPE(type) (((type) == UART_TX_OVERFLOW) || \ - ((type) == UART_TX_UNDERFLOW) || \ - ((type) == UART_RX_OVERFLOW) || \ - ((type) == UART_RX_UNDERFLOW)) - -/*@} end of group UART_Public_Constants */ - -/** @defgroup UART_Public_Macros - * @{ - */ -#define UART_RX_FIFO_SIZE 128 -#define UART_TX_FIFO_SIZE 128 -#define UART_DEFAULT_RECV_TIMEOUT 80 - -/*@} end of group UART_Public_Macros */ - -/** @defgroup UART_Public_Functions - * @{ - */ - -/** - * @brief UART Functions - */ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) || (defined BFLB_EFLASH_LOADER) -void UART0_IRQHandler(void); -void UART1_IRQHandler(void); -void UART2_IRQHandler(void); -void UART3_IRQHandler(void); -void UART4_IRQHandler(void); -#endif -BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate); -BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg); -BL_Err_Type UART_DeInit(UART_ID_Type uartId); -BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg); -BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg); -BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct); -BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct); -BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length); -BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length); -BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time); -BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count); -BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt); -BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); -BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId); -BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId); -BL_Err_Type UART_SetTxValue(UART_ID_Type uartId); -BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId); -BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun); -BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud); -BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError); -BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width); -BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity); -BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId); -BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId); -BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask); -BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType); -BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun); -BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len); -BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len); -uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen); -uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet); -uint16_t UART_GetRxByteCount(UART_ID_Type uartId); -uint8_t UART_GetTxFifoCount(UART_ID_Type uartId); -uint8_t UART_GetRxFifoCount(UART_ID_Type uartId); -BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType); -BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId); -BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId); -BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow); - -/*@} end of group UART_Public_Functions */ - -/*@} end of group UART */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_UART_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h deleted file mode 100644 index 71bb906797..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_uhs_phy.h +++ /dev/null @@ -1,46 +0,0 @@ -#ifndef __UHS_PHY_H__ -#define __UHS_PHY_H__ - -#include "bl808_common.h" -// /** @addtogroup Configuration_section_for_RISCV -// * @{ -// */ -// #define BL_RD_WORD(addr) (*((volatile uint32_t*)(addr))) -// #define BL_WR_WORD(addr,val) ((*(volatile uint32_t*)(addr))=(val)) -// #define BL_RD_SHORT(addr) (*((volatile uint16_t*)(addr))) -// #define BL_WR_SHORT(addr,val) ((*(volatile uint16_t*)(addr))=(val)) -// #define BL_RD_BYTE(addr) (*((volatile uint8_t*)(addr))) -// #define BL_WR_BYTE(addr,val) ((*(volatile uint8_t*)(addr))=(val)) -// #define BL_RDWD_FRM_BYTEP(p) ((p[3]<<24)|(p[2]<<16)|(p[1]<<8)|(p[0])) -// #define BL_WRWD_TO_BYTEP(p,val) {p[0]=val&0xff;p[1]=(val>>8)&0xff;p[2]=(val>>16)&0xff;p[3]=(val>>24)&0xff;} -// /** -// * @brief Register access macro -// */ -// #define BL_RD_REG16(addr,regname) BL_RD_SHORT(addr+regname##_OFFSET) -// #define BL_WR_REG16(addr,regname,val) BL_WR_SHORT(addr+regname##_OFFSET,val) -// #define BL_RD_REG(addr,regname) BL_RD_WORD(addr+regname##_OFFSET) -// #define BL_WR_REG(addr,regname,val) BL_WR_WORD(addr+regname##_OFFSET,val) -// #define BL_SET_REG_BIT(val,bitname) ( (val) |(1U<> bitname##_POS ) -// #define BL_SET_REG_BITS_VAL(val,bitname,bitval) ( ((val)&bitname##_UMSK) | ((uint32_t)(bitval)<
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __BL808_USB_H__ -#define __BL808_USB_H__ - -#include "usb_reg.h" -#include "bl808_common.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup USB - * @{ - */ - -/** @defgroup USB_Public_Types - * @{ - */ - -/** - * @brief USB LPM response type definition - */ -typedef enum { - USB_LPM_RESP_NYET = 0, /*!< response LPM with NYET */ - USB_LPM_RESP_ACK = 1, /*!< response LPM with ACK */ -} USB_LPM_RESP_Type; - -/** - * @brief USB LPM configuration structure type definition - */ -typedef struct -{ - uint8_t lpmEn; /*!< response LPM or not */ - USB_LPM_RESP_Type resp; /*!< response LPM with ACK or NAK */ - uint8_t minBesl; /*!< BESL min value */ - uint8_t maxBesl; /*!< BESL max value */ - uint8_t lpmWakeUpEn; /*!< LPM wakeup enable */ -} USB_LPM_Cfg_Type; - -/** - * @brief USB global interrupt type definition - */ -typedef enum { - USB_GLOBAL_INT_DEV = 0, /*!< USB device interrupt type */ - USB_GLOBAL_INT_OTG = 1, /*!< USB OTG interrupt type */ - USB_GLOBAL_INT_HC = 2, /*!< USB host interrupt type */ -} USB_GLOBAL_INT_Type; - -/** - * @brief USB global interrupt type definition - */ -typedef enum { - USB_DEVICE_SPEED_FULL_SPEED = 0, /*!< USB device interrupt type */ - USB_DEVICE_SPEED_HIGH_SPEED = 1, /*!< USB OTG interrupt type */ -} USB_DEVICE_SPEED_Type; - -/** - * @brief USB normal configuration structure type definition - */ -typedef struct -{ - uint8_t forceFullSpeed; /*!< force device to full speed */ - uint8_t chipEn; /*!< chip enable */ - uint8_t swRst; /*!< software reset */ - uint8_t remoteWakeupEn; /*!< remote wakeup capability enable */ - uint32_t rstTimeOut; /*!< software reset timeout count */ -} USB_NORMAL_Cfg_Type; - -/** - * @brief USB FIFO empty type definition - */ -typedef enum { - USB_FIFO_EMPTY_FIFO_0 = 8, /*!< USB FIFO 0 empty type */ - USB_FIFO_EMPTY_FIFO_1 = 9, /*!< USB FIFO 1 empty type */ - USB_FIFO_EMPTY_FIFO_2 = 10, /*!< USB FIFO 2 empty type */ - USB_FIFO_EMPTY_FIFO_3 = 11, /*!< USB FIFO 3 empty type */ -} USB_FIFO_EMPTY_Type; - -/** - * @brief USB endpoint ID type definition - */ -typedef enum { - USB_Endpoint_0 = 0, /*!< USB endpoint ID 0 */ - USB_Endpoint_1 = 1, /*!< USB endpoint ID 1 */ - USB_Endpoint_2 = 2, /*!< USB endpoint ID 2 */ - USB_Endpoint_3 = 3, /*!< USB endpoint ID 3 */ - USB_Endpoint_4 = 4, /*!< USB endpoint ID 4 */ - USB_Endpoint_5 = 5, /*!< USB endpoint ID 5 */ - USB_Endpoint_6 = 6, /*!< USB endpoint ID 6 */ - USB_Endpoint_7 = 7, /*!< USB endpoint ID 7 */ - USB_Endpoint_8 = 8, /*!< USB endpoint ID 8 */ -} USB_Endpoint_Type; - -/** - * @brief USB FIFO ID type definition - */ -typedef enum { - USB_FIFO_0 = 0, /*!< USB endpoint ID 0 */ - USB_FIFO_1 = 1, /*!< USB endpoint ID 1 */ - USB_FIFO_2 = 2, /*!< USB endpoint ID 2 */ - USB_FIFO_3 = 3, /*!< USB endpoint ID 3 */ -} USB_FIFO_Type; - -/** - * @brief USB FIFO direction type definition - */ -typedef enum { - USB_FIFO_DIR_OUT = 0, /*!< USB FIFO direction out */ - USB_FIFO_DIR_IN = 1, /*!< USB FIFO direction in */ - USB_FIFO_DIR_BID = 2, /*!< USB FIFO direction bidirectional */ -} USB_FIFO_DIR_Type; - -/** - * @brief USB FIFO block max size type definition - */ -typedef enum { - USB_FIFO_BLOCK_MAX_SIZE_512 = 0, /*!< USB FIFO block max packet size 512 */ - USB_FIFO_BLOCK_MAX_SIZE_1024 = 1, /*!< USB FIFO block max packet size 1024 */ -} USB_FIFO_BLOCK_MAX_SIZE_Type; - -/** - * @brief USB FIFO block count type definition - */ -typedef enum { - USB_FIFO_BLOCK_CNT_SINGLE_BLOCK = 0, /*!< USB FIFO single block */ - USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS = 1, /*!< USB FIFO double block */ - USB_FIFO_BLOCK_CNT_TRIPLE_BLOCKS = 2, /*!< USB FIFO triple block */ -} USB_FIFO_BLOCK_CNT_Type; - -/** - * @brief USB FIFO transfer type definition - */ -typedef enum { - USB_FIFO_TRANSFER_RSV = 0, /*!< USB FIFO transfer type is reserved */ - USB_FIFO_TRANSFER_ISO = 1, /*!< USB FIFO transfer type is isochronous */ - USB_FIFO_TRANSFER_BULK = 2, /*!< USB FIFO transfer type is bulk */ - USB_FIFO_TRANSFER_INT = 3, /*!< USB FIFO transfer type is interrupt */ -} USB_FIFO_TRANSFER_Type; - -/** - * @brief USB FIFO configuration structure type definition - */ -typedef struct -{ - uint8_t enable; /*!< FIFO enable or disable */ - USB_FIFO_DIR_Type dir; /*!< FIFO direction */ - USB_Endpoint_Type epID; /*!< Endpoint number of FIFO */ - USB_FIFO_BLOCK_MAX_SIZE_Type blockSize; /*!< FIFO block max size */ - USB_FIFO_BLOCK_CNT_Type blockType; /*!< FIFO block type */ - USB_FIFO_TRANSFER_Type fifoType; /*!< FIFO transfer type */ -} USB_FIFO_Cfg_Type; - -/** - * @brief USB DMA target FIFO type definition - */ -typedef enum { - USB_DMA_TARGET_FIFO_CTRL = 0, /*!< USB DMA target FIFO is control FIFO */ - USB_DMA_TARGET_FIFO_0 = 1, /*!< USB DMA target FIFO is FIFO 0 */ - USB_DMA_TARGET_FIFO_1 = 2, /*!< USB DMA target FIFO is FIFO 1 */ - USB_DMA_TARGET_FIFO_2 = 3, /*!< USB DMA target FIFO is FIFO 2 */ - USB_DMA_TARGET_FIFO_3 = 4, /*!< USB DMA target FIFO is FIFO 3 */ -} USB_DMA_TARGET_FIFO_Type; - -/** - * @brief USB DMA transfer type definition - */ -typedef enum { - USB_DMA_TRANS_DIR_FIFO_2_MEM = 0, /*!< USB DMA transfer type is FIFO to memory */ - USB_DMA_TRANS_DIR_MEM_2_FIFO = 1, /*!< USB DMA transfer type is memory to FIFO */ - USB_DMA_TRANS_DIR_FIFO_2_FIFO = 2, /*!< USB DMA transfer type is FIFO to FIFO */ -} USB_DMA_TRANS_DIR_Type; - -/** - * @brief USB DMA configuration structure type definition - */ -typedef struct -{ - USB_DMA_TRANS_DIR_Type dir; /*!< USB DMA transfer direction */ - uint32_t memAddr; /*!< USB DMA target memory address */ - uint32_t length; /*!< USB DMA transfer length */ -} USB_DMA_Cfg_Type; - -/** - * @brief USB Virtual DMA target FIFO type definition - */ -typedef enum { - USB_VDMA_TARGET_FIFO_CTRL = 0, /*!< USB VDMA target FIFO is control FIFO */ - USB_VDMA_TARGET_FIFO_0 = 1, /*!< USB VDMA target FIFO is FIFO 0 */ - USB_VDMA_TARGET_FIFO_1 = 2, /*!< USB VDMA target FIFO is FIFO 1 */ - USB_VDMA_TARGET_FIFO_2 = 3, /*!< USB VDMA target FIFO is FIFO 2 */ - USB_VDMA_TARGET_FIFO_3 = 4, /*!< USB VDMA target FIFO is FIFO 3 */ -} USB_VDMA_TARGET_FIFO_Type; - -/** - * @brief USB Virtual DMA transfer type definition - */ -typedef enum { - USB_VDMA_TRANS_DIR_FIFO_2_MEM = 0, /*!< USB VDMA transfer type is FIFO to memory */ - USB_VDMA_TRANS_DIR_MEM_2_FIFO = 1, /*!< USB VDMA transfer type is memory to FIFO */ - USB_VDMA_TRANS_DIR_FIFO_2_FIFO = 2, /*!< USB VDMA transfer type is FIFO to FIFO */ -} USB_VDMA_TRANS_DIR_Type; - -/** - * @brief USB Virtual DMA configuration structure type definition - */ -typedef struct -{ - USB_VDMA_TRANS_DIR_Type dir; /*!< USB VDMA transfer direction */ - uint32_t memAddr; /*!< USB VDMA target memory address */ - uint32_t length; /*!< USB VDMA transfer length */ -} USB_VDMA_Cfg_Type; - -/** - * @brief USB interrupt group type definition - */ -typedef enum { - USB_GRP_INT_G0 = 0, /*!< USB group 0 interrupt type */ - USB_GRP_INT_G1 = 1, /*!< USB group 1 interrupt type */ - USB_GRP_INT_G2 = 2, /*!< USB group 2 interrupt type */ - USB_GRP_INT_G3 = 3, /*!< USB group 3 interrupt type */ - USB_GRP_INT_G4 = 4, /*!< USB group 4 interrupt type */ -} USB_GRP_INT_Type; - -/** - * @brief USB interrupt group0 type definition - */ -typedef enum { - USB_SUB_GRP0_INT_CX_SETUP = 0, /*!< group0 endpoint 0 setup data received */ - USB_SUB_GRP0_INT_CX_IN = 1, /*!< group0 endpoint 0 IN */ - USB_SUB_GRP0_INT_CX_OUT = 2, /*!< group0 endpoint 0 OUT */ - USB_SUB_GRP0_INT_CX_COMFAIL = 3, /*!< group0 endpoint 0 COMFAIL */ - USB_SUB_GRP0_INT_CX_COMABORT = 4, /*!< group0 endpoint 0 COMABORT */ - USB_SUB_GRP1_INT_F0_OUT = 5, /*!< group1 OUT interrupt of FIFO 0 */ - USB_SUB_GRP1_INT_F0_SPK = 6, /*!< group1 short packet interrupt of FIFO 0 */ - USB_SUB_GRP1_INT_F1_OUT = 7, /*!< group1 OUT interrupt of FIFO 1 */ - USB_SUB_GRP1_INT_F1_SPK = 8, /*!< group1 short packet interrupt of FIFO 1 */ - USB_SUB_GRP1_INT_F2_OUT = 9, /*!< group1 OUT interrupt of FIFO 2 */ - USB_SUB_GRP1_INT_F2_SPK = 10, /*!< group1 short packet interrupt of FIFO 2 */ - USB_SUB_GRP1_INT_F3_OUT = 11, /*!< group1 OUT interrupt of FIFO 3 */ - USB_SUB_GRP1_INT_F3_SPK = 12, /*!< group1 short packet interrupt of FIFO 3 */ - USB_SUB_GRP1_INT_F0_IN = 13, /*!< group1 IN interrupt of FIFO 0 */ - USB_SUB_GRP1_INT_F1_IN = 14, /*!< group1 IN interrupt of FIFO 1 */ - USB_SUB_GRP1_INT_F2_IN = 15, /*!< group1 IN interrupt of FIFO 2 */ - USB_SUB_GRP1_INT_F3_IN = 16, /*!< group1 IN interrupt of FIFO 3 */ - USB_SUB_GRP2_INT_RESET = 17, /*!< group2 USB reset interrupt */ - USB_SUB_GRP2_INT_SUSPEND = 18, /*!< group2 suspend interrupt */ - USB_SUB_GRP2_INT_RESUME = 19, /*!< group2 resume interrupt */ - USB_SUB_GRP2_INT_TX0BYTE = 20, /*!< group2 transferred zero-length data packet interrupt */ - USB_SUB_GRP2_INT_RX0BYTE = 21, /*!< group2 received zero-length data packet interrupt */ - USB_SUB_GRP2_INT_DMA_CMPLT = 22, /*!< group2 DMA completion interrupt */ - USB_SUB_GRP2_INT_DMA_ERROR = 23, /*!< group2 DMA error interrupt */ - USB_SUB_GRP2_INT_IDLE = 24, /*!< group2 dev_idle interrupt */ - USB_SUB_GRP2_INT_WAKEUP_BY_VBUS = 25, /*!< group2 dev_wakeup_byVBUS interrupt */ - USB_SUB_GRP3_INT_VDMA_CMPLT_CXF = 26, /*!< group3 Virtual DMA completion interrupt for FIFO CXF */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F0 = 27, /*!< group3 Virtual DMA completion interrupt for FIFO 0 */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F1 = 28, /*!< group3 Virtual DMA completion interrupt for FIFO 1 */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F2 = 29, /*!< group3 Virtual DMA completion interrupt for FIFO 2 */ - USB_SUB_GRP3_INT_VDMA_CMPLT_F3 = 30, /*!< group3 Virtual DMA completion interrupt for FIFO 3 */ - USB_SUB_GRP3_INT_VDMA_ERROR_CXF = 31, /*!< group3 Virtual DMA error interrupt for FIFO CXF */ - USB_SUB_GRP3_INT_VDMA_ERROR_F0 = 32, /*!< group3 Virtual DMA error interrupt for FIFO 0 */ - USB_SUB_GRP3_INT_VDMA_ERROR_F1 = 33, /*!< group3 Virtual DMA error interrupt for FIFO 1 */ - USB_SUB_GRP3_INT_VDMA_ERROR_F2 = 34, /*!< group3 Virtual DMA error interrupt for FIFO 2 */ - USB_SUB_GRP3_INT_VDMA_ERROR_F3 = 35, /*!< group3 Virtual DMA error interrupt for FIFO 3 */ - USB_SUB_GRP4_INT_L1 = 36, /*!< group4 L1-state-change interrupt */ -} USB_SUB_GRP_INT_Type; - -/*@} end of group USB_Public_Types */ - -/** @defgroup USB_Public_Constants - * @{ - */ - -/** @defgroup USB_LPM_RESP_TYPE - * @{ - */ -#define IS_USB_LPM_RESP_TYPE(type) (((type) == USB_LPM_RESP_NYET) || \ - ((type) == USB_LPM_RESP_ACK)) - -/** @defgroup USB_GLOBAL_INT_TYPE - * @{ - */ -#define IS_USB_GLOBAL_INT_TYPE(type) (((type) == USB_GLOBAL_INT_DEV) || \ - ((type) == USB_GLOBAL_INT_OTG) || \ - ((type) == USB_GLOBAL_INT_HC)) - -/** @defgroup USB_DEVICE_SPEED_TYPE - * @{ - */ -#define IS_USB_DEVICE_SPEED_TYPE(type) (((type) == USB_DEVICE_SPEED_FULL_SPEED) || \ - ((type) == USB_DEVICE_SPEED_HIGH_SPEED)) - -/** @defgroup USB_FIFO_EMPTY_TYPE - * @{ - */ -#define IS_USB_FIFO_EMPTY_TYPE(type) (((type) == USB_FIFO_EMPTY_FIFO_0) || \ - ((type) == USB_FIFO_EMPTY_FIFO_1) || \ - ((type) == USB_FIFO_EMPTY_FIFO_2) || \ - ((type) == USB_FIFO_EMPTY_FIFO_3)) - -/** @defgroup USB_ENDPOINT_TYPE - * @{ - */ -#define IS_USB_ENDPOINT_TYPE(type) (((type) == USB_Endpoint_1) || \ - ((type) == USB_Endpoint_2) || \ - ((type) == USB_Endpoint_3) || \ - ((type) == USB_Endpoint_4) || \ - ((type) == USB_Endpoint_5) || \ - ((type) == USB_Endpoint_6) || \ - ((type) == USB_Endpoint_7) || \ - ((type) == USB_Endpoint_8)) - -/** @defgroup USB_FIFO_TYPE - * @{ - */ -#define IS_USB_FIFO_TYPE(type) (((type) == USB_FIFO_0) || \ - ((type) == USB_FIFO_1) || \ - ((type) == USB_FIFO_2) || \ - ((type) == USB_FIFO_3)) - -/** @defgroup USB_FIFO_DIR_TYPE - * @{ - */ -#define IS_USB_FIFO_DIR_TYPE(type) (((type) == USB_FIFO_DIR_OUT) || \ - ((type) == USB_FIFO_DIR_IN) || \ - ((type) == USB_FIFO_DIR_BID)) - -/** @defgroup USB_FIFO_BLOCK_MAX_SIZE_TYPE - * @{ - */ -#define IS_USB_FIFO_BLOCK_MAX_SIZE_TYPE(type) (((type) == USB_FIFO_BLOCK_MAX_SIZE_512) || \ - ((type) == USB_FIFO_BLOCK_MAX_SIZE_1024)) - -/** @defgroup USB_FIFO_BLOCK_CNT_TYPE - * @{ - */ -#define IS_USB_FIFO_BLOCK_CNT_TYPE(type) (((type) == USB_FIFO_BLOCK_CNT_SINGLE_BLOCK) || \ - ((type) == USB_FIFO_BLOCK_CNT_DOUBLE_BLOCKS) || \ - ((type) == USB_FIFO_BLOCK_CNT_TRIPLE_BLOCKS)) - -/** @defgroup USB_FIFO_TRANSFER_TYPE - * @{ - */ -#define IS_USB_FIFO_TRANSFER_TYPE(type) (((type) == USB_FIFO_TRANSFER_RSV) || \ - ((type) == USB_FIFO_TRANSFER_ISO) || \ - ((type) == USB_FIFO_TRANSFER_BULK) || \ - ((type) == USB_FIFO_TRANSFER_INT)) - -/** @defgroup USB_DMA_TARGET_FIFO_TYPE - * @{ - */ -#define IS_USB_DMA_TARGET_FIFO_TYPE(type) (((type) == USB_DMA_TARGET_FIFO_0) || \ - ((type) == USB_DMA_TARGET_FIFO_1) || \ - ((type) == USB_DMA_TARGET_FIFO_2) || \ - ((type) == USB_DMA_TARGET_FIFO_3) || \ - ((type) == USB_DMA_TARGET_FIFO_CTRL)) - -/** @defgroup USB_DMA_TRANS_DIR_TYPE - * @{ - */ -#define IS_USB_DMA_TRANS_DIR_TYPE(type) (((type) == USB_DMA_TRANS_DIR_FIFO_2_MEM) || \ - ((type) == USB_DMA_TRANS_DIR_MEM_2_FIFO) || \ - ((type) == USB_DMA_TRANS_DIR_FIFO_2_FIFO)) - -/** @defgroup USB_VDMA_TARGET_FIFO_TYPE - * @{ - */ -#define IS_USB_VDMA_TARGET_FIFO_TYPE(type) (((type) == USB_VDMA_TARGET_FIFO_0) || \ - ((type) == USB_VDMA_TARGET_FIFO_1) || \ - ((type) == USB_VDMA_TARGET_FIFO_2) || \ - ((type) == USB_VDMA_TARGET_FIFO_3) || \ - ((type) == USB_VDMA_TARGET_FIFO_CTRL)) - -/** @defgroup USB_VDMA_TRANS_DIR_TYPE - * @{ - */ -#define IS_USB_VDMA_TRANS_DIR_TYPE(type) (((type) == USB_VDMA_TRANS_DIR_FIFO_2_MEM) || \ - ((type) == USB_VDMA_TRANS_DIR_MEM_2_FIFO) || \ - ((type) == USB_VDMA_TRANS_DIR_FIFO_2_FIFO)) - -/** @defgroup USB_GRP_INT_TYPE - * @{ - */ -#define IS_USB_GRP_INT_TYPE(type) (((type) == USB_GRP_INT_G0) || \ - ((type) == USB_GRP_INT_G1) || \ - ((type) == USB_GRP_INT_G2) || \ - ((type) == USB_GRP_INT_G3) || \ - ((type) == USB_GRP_INT_G4)) - -/** @defgroup USB_SUB_GRP_INT_TYPE - * @{ - */ -#define IS_USB_SUB_GRP_INT_TYPE(type) (((type) == USB_SUB_GRP0_INT_CX_SETUP) || \ - ((type) == USB_SUB_GRP0_INT_CX_IN) || \ - ((type) == USB_SUB_GRP0_INT_CX_OUT) || \ - ((type) == USB_SUB_GRP0_INT_CX_COMFAIL) || \ - ((type) == USB_SUB_GRP0_INT_CX_COMABORT) || \ - ((type) == USB_SUB_GRP1_INT_F0_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F0_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F1_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F1_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F2_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F2_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F3_OUT) || \ - ((type) == USB_SUB_GRP1_INT_F3_SPK) || \ - ((type) == USB_SUB_GRP1_INT_F0_IN) || \ - ((type) == USB_SUB_GRP1_INT_F1_IN) || \ - ((type) == USB_SUB_GRP1_INT_F2_IN) || \ - ((type) == USB_SUB_GRP1_INT_F3_IN) || \ - ((type) == USB_SUB_GRP2_INT_RESET) || \ - ((type) == USB_SUB_GRP2_INT_SUSPEND) || \ - ((type) == USB_SUB_GRP2_INT_RESUME) || \ - ((type) == USB_SUB_GRP2_INT_TX0BYTE) || \ - ((type) == USB_SUB_GRP2_INT_RX0BYTE) || \ - ((type) == USB_SUB_GRP2_INT_DMA_CMPLT) || \ - ((type) == USB_SUB_GRP2_INT_DMA_ERROR) || \ - ((type) == USB_SUB_GRP2_INT_IDLE) || \ - ((type) == USB_SUB_GRP2_INT_WAKEUP_BY_VBUS) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_CXF) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F0) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F1) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F2) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_CMPLT_F3) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_CXF) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F0) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F1) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F2) || \ - ((type) == USB_SUB_GRP3_INT_VDMA_ERROR_F3) || \ - ((type) == USB_SUB_GRP4_INT_L1)) - -/*@} end of group USB_Public_Constants */ - -/** @defgroup USB_Public_Macros - * @{ - */ -#define USB_SUB_GRP0_INT_OFS (0) -#define USB_SUB_GRP1_INT_OFS (32) -#define USB_SUB_GRP2_INT_OFS (64) -#define USB_SUB_GRP3_INT_OFS (96) -#define USB_SUB_GRP4_INT_OFS (128) -#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C) -#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710) - -#define USB_INT_CX_SETUP (1ULL << USB_SUB_GRP0_INT_CX_SETUP) -#define USB_INT_CX_IN (1ULL << USB_SUB_GRP0_INT_CX_IN) -#define USB_INT_CX_OUT (1ULL << USB_SUB_GRP0_INT_CX_OUT) -#define USB_INT_CX_COMFAIL (1ULL << USB_SUB_GRP0_INT_CX_COMFAIL) -#define USB_INT_CX_COMABORT (1ULL << USB_SUB_GRP0_INT_CX_COMABORT) -#define USB_INT_F0_OUT (1ULL << USB_SUB_GRP1_INT_F0_OUT) -#define USB_INT_F0_SPK (1ULL << USB_SUB_GRP1_INT_F0_SPK) -#define USB_INT_F1_OUT (1ULL << USB_SUB_GRP1_INT_F1_OUT) -#define USB_INT_F1_SPK (1ULL << USB_SUB_GRP1_INT_F1_SPK) -#define USB_INT_F2_OUT (1ULL << USB_SUB_GRP1_INT_F2_OUT) -#define USB_INT_F2_SPK (1ULL << USB_SUB_GRP1_INT_F2_SPK) -#define USB_INT_F3_OUT (1ULL << USB_SUB_GRP1_INT_F3_OUT) -#define USB_INT_F3_SPK (1ULL << USB_SUB_GRP1_INT_F3_SPK) -#define USB_INT_F0_IN (1ULL << USB_SUB_GRP1_INT_F0_IN) -#define USB_INT_F1_IN (1ULL << USB_SUB_GRP1_INT_F1_IN) -#define USB_INT_F2_IN (1ULL << USB_SUB_GRP1_INT_F2_IN) -#define USB_INT_F3_IN (1ULL << USB_SUB_GRP1_INT_F3_IN) -#define USB_INT_RESET (1ULL << USB_SUB_GRP2_INT_RESET) -#define USB_INT_SUSPEND (1ULL << USB_SUB_GRP2_INT_SUSPEND) -#define USB_INT_RESUME (1ULL << USB_SUB_GRP2_INT_RESUME) -#define USB_INT_TX0BYTE (1ULL << USB_SUB_GRP2_INT_TX0BYTE) -#define USB_INT_RX0BYTE (1ULL << USB_SUB_GRP2_INT_RX0BYTE) -#define USB_INT_DMA_CMPLT (1ULL << USB_SUB_GRP2_INT_DMA_CMPLT) -#define USB_INT_DMA_ERROR (1ULL << USB_SUB_GRP2_INT_DMA_ERROR) -#define USB_INT_IDLE (1ULL << USB_SUB_GRP2_INT_IDLE) -#define USB_INT_WAKEUP_BY_VBUS (1ULL << USB_SUB_GRP2_INT_WAKEUP_BY_VBUS) -#define USB_INT_VDMA_CMPLT_CXF (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_CXF) -#define USB_INT_VDMA_CMPLT_F0 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F0) -#define USB_INT_VDMA_CMPLT_F1 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F1) -#define USB_INT_VDMA_CMPLT_F2 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F2) -#define USB_INT_VDMA_CMPLT_F3 (1ULL << USB_SUB_GRP3_INT_VDMA_CMPLT_F3) -#define USB_INT_VDMA_ERROR_CXF (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_CXF) -#define USB_INT_VDMA_ERROR_F0 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F0) -#define USB_INT_VDMA_ERROR_F1 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F1) -#define USB_INT_VDMA_ERROR_F2 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F2) -#define USB_INT_VDMA_ERROR_F3 (1ULL << USB_SUB_GRP3_INT_VDMA_ERROR_F3) -#define USB_INT_L1 (1ULL << USB_SUB_GRP4_INT_L1) - -#define USB_SUB_GROUP_0_CX_SETUP_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_0_CX_IN_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_0_CX_OUT_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_0_CX_COMFAIL_BIT_MUSK (0x00000010) -#define USB_SUB_GROUP_0_CX_COMABORT_BIT_MUSK (0x00000020) -#define USB_SUB_GROUP_1_F0_OUT_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_1_F0_SPK_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_1_F1_OUT_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_1_F1_SPK_BIT_MUSK (0x00000008) -#define USB_SUB_GROUP_1_F2_OUT_BIT_MUSK (0x00000010) -#define USB_SUB_GROUP_1_F2_SPK_BIT_MUSK (0x00000020) -#define USB_SUB_GROUP_1_F3_OUT_BIT_MUSK (0x00000040) -#define USB_SUB_GROUP_1_F3_SPK_BIT_MUSK (0x00000080) -#define USB_SUB_GROUP_1_F0_IN_BIT_MUSK (0x00010000) -#define USB_SUB_GROUP_1_F1_IN_BIT_MUSK (0x00020000) -#define USB_SUB_GROUP_1_F2_IN_BIT_MUSK (0x00040000) -#define USB_SUB_GROUP_1_F3_IN_BIT_MUSK (0x00080000) -#define USB_SUB_GROUP_2_RESET_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_2_SUSPEND_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_2_RESUME_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_2_TX0BYTE_BIT_MUSK (0x00000020) -#define USB_SUB_GROUP_2_RX0BYTE_BIT_MUSK (0x00000040) -#define USB_SUB_GROUP_2_CMPLT_BIT_MUSK (0x00000080) -#define USB_SUB_GROUP_2_ERROR_BIT_MUSK (0x00000100) -#define USB_SUB_GROUP_2_IDLE_BIT_MUSK (0x00000200) -#define USB_SUB_GROUP_2_WAKEUP_BY_VBUS_BIT_MUSK (0x00000400) -#define USB_SUB_GROUP_3_VDMA_CMPLT_CXF_BIT_MUSK (0x00000001) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F0_BIT_MUSK (0x00000002) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F1_BIT_MUSK (0x00000004) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F2_BIT_MUSK (0x00000008) -#define USB_SUB_GROUP_3_VDMA_CMPLT_F3_BIT_MUSK (0x00000010) -#define USB_SUB_GROUP_3_VDMA_ERROR_CXF_BIT_MUSK (0x00010000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F0_BIT_MUSK (0x00020000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F1_BIT_MUSK (0x00040000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F2_BIT_MUSK (0x00080000) -#define USB_SUB_GROUP_3_VDMA_ERROR_F3_BIT_MUSK (0x00100000) -#define USB_SUB_GROUP_4_L1_BIT_MUSK (0x00000001) - -/*@} end of group USB_Public_Macros */ - -/** @defgroup USB_Public_Functions - * @{ - */ - -/** - * @brief USB Functions - */ -BL_Err_Type USB_Set_Normal_Config(USB_NORMAL_Cfg_Type *cfg); -BL_Err_Type USB_SOF_Mask_Time_HighSpeed(void); -BL_Err_Type USB_SOF_Mask_Time_FullSpeed(void); -BL_Err_Type USB_SoftDetach_Enable(void); -BL_Err_Type USB_SoftDetach_Disable(void); -USB_DEVICE_SPEED_Type USB_Get_Device_Speed_Status(void); -BL_Err_Type USB_Go_Suspend(uint8_t enable); -BL_Err_Type USB_Set_Device_Address(uint8_t addr); -uint8_t USB_Get_Device_Address(void); -BL_Err_Type USB_Non_Ctrl_Transfer_Enable(void); -BL_Err_Type USB_Non_Ctrl_Transfer_Disable(void); -BL_Err_Type USB_Clear_CTRL_FIFO(void); -BL_Sts_Type USB_Is_CTRL_FIFO_Empty(void); -BL_Sts_Type USB_Is_CTRL_FIFO_Full(void); -BL_Err_Type USB_Clear_FIFO(void); -BL_Err_Type USB_Reset_FIFO(USB_FIFO_Type fifoID); -BL_Sts_Type USB_Is_FIFO_Empty(USB_FIFO_EMPTY_Type fifoNum); -BL_Err_Type USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_Type epID, USB_FIFO_Type fifoID); -BL_Err_Type USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_Type epID, USB_FIFO_Type fifoID); -BL_Err_Type USB_Set_FIFO_Config(USB_FIFO_Type fifoID, USB_FIFO_Cfg_Type *cfg); -uint16_t USB_Get_OUT_FIFO_Count(USB_FIFO_Type fifoID); -BL_Err_Type USB_Set_Endpoint_IN_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max); -BL_Err_Type USB_Set_Endpoint_OUT_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max); -BL_Err_Type USB_Set_CTRL_Endpoint_Stall_Once(void); -BL_Err_Type USB_Set_Endpoint_IN_Stall(USB_Endpoint_Type epID, uint8_t enable); -BL_Err_Type USB_Set_Endpoint_OUT_Stall(USB_Endpoint_Type epID, uint8_t enable); -BL_Err_Type USB_CTRL_Endpoint_Data_Transfer_Done(void); -BL_Sts_Type USB_Is_Endpoint_Receive_Zero_Length_Packet(USB_Endpoint_Type epID); -BL_Err_Type USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(USB_Endpoint_Type epID); -BL_Err_Type USB_Reset_Endpoint_IN_Data_Toggle_Sequence(USB_Endpoint_Type epID); -BL_Err_Type USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(USB_Endpoint_Type epID); -BL_Err_Type USB_Endpoint_Transmit_Zero_Length_Packet(USB_Endpoint_Type epID); -BL_Sts_Type USB_Is_Endpoint_Transfer_Zero_Length_Packet(USB_Endpoint_Type epID); -BL_Err_Type USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(USB_Endpoint_Type epID); -BL_Err_Type USB_Get_Setup_Command(uint32_t setup[2]); -void USB_Reset_DMA_Accessing_Fifo(void); -BL_Err_Type USB_Update_DMA_Trans(uint32_t memAddr, uint32_t length); -BL_Err_Type USB_Set_DMA_Config(USB_DMA_TARGET_FIFO_Type fifoN, USB_DMA_Cfg_Type *cfg); -BL_Err_Type USB_Set_DMA_Start(void); -BL_Err_Type USB_Set_VDMA_Config(USB_VDMA_TARGET_FIFO_Type fifoN, USB_VDMA_Cfg_Type *cfg); -BL_Err_Type USB_Set_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN); -BL_Sts_Type USB_Get_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN); -BL_Err_Type USB_Set_VDMA_Enable(void); -BL_Err_Type USB_Set_LPM_Config(USB_LPM_Cfg_Type *cfg); -uint8_t USB_Get_LPM_BESL(void); -/*----------*/ -BL_Err_Type USB_Set_Suspend_Delay(uint8_t ms); -/*----------*/ -BL_Err_Type USB_Global_IntEnable(uint8_t enable); -BL_Err_Type USB_Global_IntMask(USB_GLOBAL_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type USB_Global_IntStatus(USB_GLOBAL_INT_Type intType); -/*----------*/ -BL_Err_Type USB_Group_IntMask(USB_GRP_INT_Type intType, BL_Mask_Type intMask); -BL_Sts_Type USB_Group_IntStatus(USB_GRP_INT_Type intType); -/*----------*/ -BL_Err_Type USB_Sub_Group_IntMask(uint64_t intType); -BL_Err_Type USB_Sub_Group_IntUnmask(uint64_t intType); -/*----------*/ -uint32_t USB_Get_Sub_Group_0_IntStatus(void); -uint32_t USB_Get_Sub_Group_1_IntStatus(void); -uint32_t USB_Get_Sub_Group_2_IntStatus(void); -uint32_t USB_Get_Sub_Group_3_IntStatus(void); -uint32_t USB_Get_Sub_Group_4_IntStatus(void); -uint32_t USB_Get_Sub_Group_0_IntMask(void); -uint32_t USB_Get_Sub_Group_1_IntMask(void); -uint32_t USB_Get_Sub_Group_2_IntMask(void); -uint32_t USB_Get_Sub_Group_3_IntMask(void); -uint32_t USB_Get_Sub_Group_4_IntMask(void); -BL_Err_Type USB_Get_Sub_Group_0_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_1_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_2_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_3_IntClear(uint32_t clrVal); -BL_Err_Type USB_Get_Sub_Group_4_IntClear(uint32_t clrVal); -/*----------*/; - -/*@} end of group USB_Public_Functions */ - -/*@} end of group USB */ - -/*@} end of group BL808_Peripheral_Driver */ - -#endif /* __BL808_USB_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c deleted file mode 100644 index bb4dfe39eb..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_acomp.c +++ /dev/null @@ -1,209 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_acomp.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_acomp.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup ACOMP - * @{ - */ - -/** @defgroup ACOMP_Private_Macros - * @{ - */ - -/*@} end of group ACOMP_Private_Macros */ - -/** @defgroup ACOMP_Private_Types - * @{ - */ - -/*@} end of group ACOMP_Private_Types */ - -/** @defgroup ACOMP_Private_Variables - * @{ - */ - -/*@} end of group ACOMP_Private_Variables */ - -/** @defgroup ACOMP_Global_Variables - * @{ - */ - -/*@} end of group ACOMP_Global_Variables */ - -/** @defgroup ACOMP_Private_Fun_Declaration - * @{ - */ - -/*@} end of group ACOMP_Private_Fun_Declaration */ - -/** @defgroup ACOMP_Private_Functions - * @{ - */ - -/*@} end of group ACOMP_Private_Functions */ - -/** @defgroup ACOMP_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Analog compare init - * - * @param acompNo: Compare ID - * @param cfg: Compare consideration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type AON_ACOMP_Init(AON_ACOMP_ID_Type acompNo, AON_ACOMP_CFG_Type *cfg) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); - - if (acompNo == AON_ACOMP0_ID) { - /* Disable ACOMP first */ - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP0_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); - - /* Set ACOMP config */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_MUXEN, cfg->muxEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_POS_SEL, cfg->posChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_NEG_SEL, cfg->negChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_LEVEL_SEL, cfg->scalingFactor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_BIAS_PROG, cfg->biasProg); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELP, cfg->hysteresisPosVolt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP0_HYST_SELN, cfg->hysteresisNegVolt); - - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); - } else { - /* Disable ACOMP first */ - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_ACOMP1_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); - - /* Set ACOMP config */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_MUXEN, cfg->muxEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_POS_SEL, cfg->posChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_NEG_SEL, cfg->negChanSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_LEVEL_SEL, cfg->scalingFactor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_BIAS_PROG, cfg->biasProg); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELP, cfg->hysteresisPosVolt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP1_HYST_SELN, cfg->hysteresisNegVolt); - - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); - } - - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_ACOMP_VREF_SEL, cfg->vioSel); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Analog compare enable - * - * @param acompNo: Compare ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type AON_ACOMP_Enable(AON_ACOMP_ID_Type acompNo) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); - - if (acompNo == AON_ACOMP0_ID) { - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP0_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP0_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP0_CTRL, tmpVal); - } else { - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP1_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_ACOMP1_EN); - tmpVal = BL_WR_REG(AON_BASE, AON_ACOMP1_CTRL, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Analog compare enable - * - * @param acompNo: Compare ID - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompNo)); - - tmpVal = BL_RD_REG(AON_BASE, AON_ACOMP_CTRL); - - /* Disable ACOMP first */ - if (acompNo == AON_ACOMP0_ID) { - if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP0_OUT_RAW)) { - return SET; - } else { - return RESET; - } - } else { - if (BL_IS_REG_BIT_SET(tmpVal, AON_ACOMP1_OUT_RAW)) { - return SET; - } else { - return RESET; - } - } -} - -/*@} end of group ACOMP_Public_Functions */ - -/*@} end of group ACOMP */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c deleted file mode 100644 index 0226b9d705..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_adc.c +++ /dev/null @@ -1,1487 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_adc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_adc.h" -#include "bl808_ef_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup ADC - * @{ - */ - -/** @defgroup ADC_Private_Macros - * @{ - */ -#undef MSG -#define MSG(...) -#define AON_CLK_SET_DUMMY_WAIT \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - } -#define ADC_RESTART_DUMMY_WAIT arch_delay_us(100) - -/*@} end of group ADC_Private_Macros */ - -/** @defgroup ADC_Private_Types - * @{ - */ - -/*@} end of group ADC_Private_Types */ - -/** @defgroup ADC_Private_Variables - * @{ - */ -static intCallback_Type *adcIntCbfArra[ADC_INT_ALL] = { NULL }; -static ADC_Gain_Coeff_Type adcGainCoeffCal = { - .adcGainCoeffEnable = DISABLE, - .adcgainCoeffVal = 0, - .coe = 1, -}; - -/*@} end of group ADC_Private_Variables */ - -/** @defgroup ADC_Global_Variables - * @{ - */ - -/*@} end of group ADC_Global_Variables */ - -/** @defgroup ADC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group ADC_Private_Fun_Declaration */ - -/** @defgroup ADC_Private_Functions - * @{ - */ - -/*@} end of group ADC_Private_Functions */ - -/** @defgroup ADC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Software reset the whole ADC - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Reset(void) -{ - uint32_t regCmd; - - /* reset ADC */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_SET_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); - AON_CLK_SET_DUMMY_WAIT; - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, BL_CLR_REG_BIT(regCmd, AON_GPADC_SOFT_RST)); -} - -/****************************************************************************/ /** - * @brief ADC glable enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC glable disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_GLOBAL_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC normal mode init - * - * @param cfg: ADC normal mode configuration - * - * @return None - * -*******************************************************************************/ -void ADC_Init(ADC_CFG_Type *cfg) -{ - uint32_t regCfg1; - uint32_t regCfg2; - uint32_t regCalib; - uint32_t regCmd; - - CHECK_PARAM(IS_ADC_V18_SEL_TYPE(cfg->v18Sel)); - CHECK_PARAM(IS_ADC_V11_SEL_TYPE(cfg->v11Sel)); - CHECK_PARAM(IS_ADC_CLK_TYPE(cfg->clkDiv)); - CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain1)); - CHECK_PARAM(IS_ADC_PGA_GAIN_TYPE(cfg->gain2)); - CHECK_PARAM(IS_ADC_CHOP_MOD_TYPE(cfg->chopMode)); - CHECK_PARAM(IS_ADC_BIAS_SEL_TYPE(cfg->biasSel)); - CHECK_PARAM(IS_ADC_PGA_VCM_TYPE(cfg->vcm)); - CHECK_PARAM(IS_ADC_VREF_TYPE(cfg->vref)); - CHECK_PARAM(IS_ADC_SIG_INPUT_TYPE(cfg->inputMode)); - CHECK_PARAM(IS_ADC_DATA_WIDTH_TYPE(cfg->resWidth)); - - /* config 1 */ - regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V18_SEL, cfg->v18Sel); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_V11_SEL, cfg->v11Sel); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_DITHER_EN); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_SCAN_LENGTH, 0); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CLK_DIV_RATIO, cfg->clkDiv); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_CLK_ANA_INV); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CAL_OS_EN, cfg->offsetCalibEn); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_RES_SEL, cfg->resWidth); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); - AON_CLK_SET_DUMMY_WAIT; - - /* config 2 */ - regCfg2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DLY_SEL, 0x02); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA1_GAIN, cfg->gain1); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA2_GAIN, cfg->gain2); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_BIAS_SEL, cfg->biasSel); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_CHOP_MODE, cfg->chopMode); - /* pga_vcmi_en is for mic */ - regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_VCMI_EN); - - if ((cfg->gain1 != ADC_PGA_GAIN_NONE) || (cfg->gain2 != ADC_PGA_GAIN_NONE)) { - regCfg2 = BL_SET_REG_BIT(regCfg2, AON_GPADC_PGA_EN); - } else { - regCfg2 = BL_CLR_REG_BIT(regCfg2, AON_GPADC_PGA_EN); - } - - /* pga_os_cal is for mic */ - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_OS_CAL, 8); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_PGA_VCM, cfg->vcm); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_VREF_SEL, cfg->vref); - regCfg2 = BL_SET_REG_BITS_VAL(regCfg2, AON_GPADC_DIFF_MODE, cfg->inputMode); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, regCfg2); - - /* mic2 diff enable */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_MIC2_DIFF); - if (cfg->inputMode == ADC_INPUT_SINGLE_END) { - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_NEG_GND); - } else { - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_NEG_GND); - } - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - /* calibration offset */ - regCalib = BL_RD_REG(AON_BASE, AON_GPADC_REG_DEFINE); - regCalib = BL_SET_REG_BITS_VAL(regCalib, AON_GPADC_OS_CAL_DATA, cfg->offsetCalibVal); - BL_WR_REG(AON_BASE, AON_GPADC_REG_DEFINE, regCalib); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(GPADC_DMA_IRQn, GPADC_DMA_IRQHandler); -#endif - - ADC_Gain_Trim(); -} - -/****************************************************************************/ /** - * @brief ADC normal mode channel config - * - * @param posCh: ADC pos channel type - * @param negCh: ADC neg channel type - * @param contEn: ENABLE or DISABLE continuous mode - * - * @return None - * -*******************************************************************************/ -void ADC_Channel_Config(ADC_Chan_Type posCh, ADC_Chan_Type negCh, BL_Fun_Type contEn) -{ - uint32_t regCmd; - uint32_t regCfg1; - - CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(posCh)); - CHECK_PARAM(IS_AON_ADC_CHAN_TYPE(negCh)); - - /* set channel */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_POS_SEL, posCh); - regCmd = BL_SET_REG_BITS_VAL(regCmd, AON_GPADC_NEG_SEL, negCh); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - /* set continuous mode */ - regCfg1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - regCfg1 = BL_SET_REG_BITS_VAL(regCfg1, AON_GPADC_CONT_CONV_EN, contEn); - regCfg1 = BL_CLR_REG_BIT(regCfg1, AON_GPADC_SCAN_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, regCfg1); -} - -/****************************************************************************/ /** - * @brief ADC scan mode channel config - * - * @param posChList[]: ADC pos channel list type - * @param negChList[]: ADC neg channel list type - * @param scanLength: ADC scan length - * @param contEn: ENABLE or DISABLE continuous mode - * - * @return None - * -*******************************************************************************/ -void ADC_Scan_Channel_Config(ADC_Chan_Type posChList[], ADC_Chan_Type negChList[], uint8_t scanLength, BL_Fun_Type contEn) -{ - uint32_t tmpVal, i; - uint32_t dealLen; - - CHECK_PARAM((scanLength < 13)); - - /* Deal with the first 6 */ - dealLen = 6; - - if (scanLength < dealLen) { - dealLen = scanLength; - } - - /* Set first 6 scan channels */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS1); - - for (i = 0; i < dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (posChList[i] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS1, tmpVal); - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1); - - for (i = 0; i < dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (negChList[i] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG1, tmpVal); - - /* Set the left channels */ - if (scanLength > dealLen) { - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_POS2); - - for (i = 0; i < scanLength - dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (posChList[i + dealLen] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_POS2, tmpVal); - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2); - - for (i = 0; i < scanLength - dealLen; i++) { - tmpVal = tmpVal & (~(0x1F << (i * 5))); - tmpVal |= (negChList[i + dealLen] << (i * 5)); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_SCN_NEG2, tmpVal); - } - - /* Scan mode */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SCAN_LENGTH, scanLength - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_CONT_CONV_EN, contEn); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_CLK_ANA_INV); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_SCAN_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC normal mode convert start - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Start(void) -{ - uint32_t regCmd; - - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); - - ADC_RESTART_DUMMY_WAIT; - - /* enable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_SET_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); -} - -/****************************************************************************/ /** - * @brief ADC normal mode convert stop - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Stop(void) -{ - uint32_t regCmd; - - /* disable convert start */ - regCmd = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - regCmd = BL_CLR_REG_BIT(regCmd, AON_GPADC_CONV_START); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, regCmd); -} - -/****************************************************************************/ /** - * @brief ADC FIFO configuration - * - * @param fifoCfg: ADC FIFO confifuration pointer - * - * @return None - * -*******************************************************************************/ -void ADC_FIFO_Cfg(ADC_FIFO_Cfg_Type *fifoCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_FIFO_THRESHOLD_TYPE(fifoCfg->fifoThreshold)); - - /* - * DMA enable : ,When the fifo data is exceeded to fifoThreshold DMA request will occur - * DMA disable : fifoThreshold determine how many data will raise FIFO ready interrupt - */ - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_THL, fifoCfg->fifoThreshold); - - /* Enable DMA */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPADC_DMA_EN, fifoCfg->dmaEn); - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC get DMA FIFO data count - * - * @param None - * - * @return data count in FIFO - * -*******************************************************************************/ -uint8_t ADC_Get_FIFO_Count(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - return BL_GET_REG_BITS_VAL(tmpVal, GPIP_GPADC_FIFO_DATA_COUNT); -} - -/****************************************************************************/ /** - * @brief ADC get DMA FIFO full status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_FIFO_Is_Full(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_FULL)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief ADC get DMA FIFO empty status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_FIFO_Is_Empty(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_NE)) { - return RESET; - } else { - return SET; - } -} - -/****************************************************************************/ /** - * @brief ADC read DMA FIFO data - * - * @param None - * - * @return ADC result if return 0 that means this is error data,user should ignore this data. - * -*******************************************************************************/ -uint32_t ADC_Read_FIFO(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_DMA_RDATA); - - return (tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC parse result - * - * @param orgVal: Original A to D value - * @param len: Original AD vaule count - * @param result: Final Result array pointer - * - * @return None - * -*******************************************************************************/ -void ADC_Parse_Result(uint32_t *orgVal, uint32_t len, ADC_Result_Type *result) -{ - uint8_t neg = 0; - uint32_t tmpVal1 = 0, tmpVal2 = 0; - ADC_Data_Width_Type dataType; - ADC_SIG_INPUT_Type sigType; - float ref = 2.0; - uint32_t i = 0; - - float coe = 1.0; - - if (adcGainCoeffCal.adcGainCoeffEnable) { - coe = adcGainCoeffCal.coe; - } - - tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - dataType = BL_GET_REG_BITS_VAL(tmpVal1, AON_GPADC_RES_SEL); - sigType = BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_DIFF_MODE); - - if (BL_GET_REG_BITS_VAL(tmpVal2, AON_GPADC_VREF_SEL) == ADC_VREF_3P2V) { - ref = 3.2; - } - - if (sigType == ADC_INPUT_SINGLE_END) { - for (i = 0; i < len; i++) { - result[i].posChan = orgVal[i] >> 21; - result[i].negChan = -1; - - if (dataType == ADC_DATA_WIDTH_12) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); - result[i].volt = result[i].value / 4096.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || - (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); - result[i].volt = result[i].value / 16384.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || - (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { - result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); - result[i].volt = result[i].value / 65536.0 * ref; - } - } - } else { - for (i = 0; i < len; i++) { - neg = 0; - result[i].posChan = orgVal[i] >> 21; - result[i].negChan = (orgVal[i] >> 16) & 0x1F; - - if (orgVal[i] & 0x8000) { - orgVal[i] = ~orgVal[i]; - orgVal[i] += 1; - neg = 1; - } - - if (dataType == ADC_DATA_WIDTH_12) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 4) / coe); - result[i].volt = result[i].value / 2048.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_14_WITH_16_AVERAGE) || - (dataType == ADC_DATA_WIDTH_14_WITH_64_AVERAGE)) { - result[i].value = (unsigned int)(((orgVal[i] & 0xffff) >> 2) / coe); - result[i].volt = result[i].value / 8192.0 * ref; - } else if ((dataType == ADC_DATA_WIDTH_16_WITH_128_AVERAGE) || - (dataType == ADC_DATA_WIDTH_16_WITH_256_AVERAGE)) { - result[i].value = (unsigned int)((orgVal[i] & 0xffff) / coe); - result[i].volt = result[i].value / 32768.0 * ref; - } - - if (neg) { - result[i].volt = -result[i].volt; - } - } - } -} - -/****************************************************************************/ /** - * @brief ADC mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -BL_Mask_Type ADC_IntGetMask(ADC_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR_MASK); - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - return BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR_MASK); - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - return BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY_MASK); - break; - - default: - break; - } - return 0; -} - -/****************************************************************************/ /** - * @brief ADC mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -void ADC_IntMask(ADC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - } - - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - } else { - /* Disable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - } - - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - break; - - case ADC_INT_ALL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - } else { - /* Disable this interrupt */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_MASK); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_MASK); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief ADC clear certain or all interrupt - * - * @param intType: interrupt type - * - * @return None - * -*******************************************************************************/ -void ADC_IntClr(ADC_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - case ADC_INT_ALL: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_POS_SATUR_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_NEG_SATUR_CLR); - BL_WR_REG(AON_BASE, AON_GPADC_REG_ISR, tmpVal); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - /*Manual reset*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_UNDERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_FIFO_OVERRUN_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPADC_RDY_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief ADC get interrupt status - * - * @param intType: interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type ADC_GetIntStatus(ADC_INT_Type intType) -{ - uint32_t tmpVal; - BL_Sts_Type bitStatus = RESET; - - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - switch (intType) { - case ADC_INT_POS_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_POS_SATUR)) ? SET : RESET; - break; - - case ADC_INT_NEG_SATURATION: - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_ISR); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, AON_GPADC_NEG_SATUR)) ? SET : RESET; - break; - - case ADC_INT_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_UNDERRUN)) ? SET : RESET; - break; - - case ADC_INT_FIFO_OVERRUN: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_FIFO_OVERRUN)) ? SET : RESET; - break; - - case ADC_INT_ADC_READY: - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - bitStatus = (BL_IS_REG_BIT_SET(tmpVal, GPIP_GPADC_RDY)) ? SET : RESET; - break; - - case ADC_INT_ALL: - break; - - default: - break; - } - - return bitStatus; -} - -/****************************************************************************/ /** - * @brief ADC install interrupt callback - * - * @param intType: ADC interrupt type - * @param cbFun: ADC interrupt callback - * - * @return None - * -*******************************************************************************/ -void ADC_Int_Callback_Install(ADC_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_GPIP_ADC_INT_TYPE(intType)); - - adcIntCbfArra[intType] = cbFun; -} - -/****************************************************************************/ /** - * @brief ADC DMA interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void GPADC_DMA_IRQHandler(void) -{ - if (ADC_IntGetMask(ADC_INT_POS_SATURATION) == UNMASK && ADC_GetIntStatus(ADC_INT_POS_SATURATION) == SET) { - ADC_IntClr(ADC_INT_POS_SATURATION); - - if (adcIntCbfArra[ADC_INT_POS_SATURATION] != NULL) { - adcIntCbfArra[ADC_INT_POS_SATURATION](); - } - } - - if (ADC_IntGetMask(ADC_INT_NEG_SATURATION) == UNMASK && ADC_GetIntStatus(ADC_INT_NEG_SATURATION) == SET) { - ADC_IntClr(ADC_INT_NEG_SATURATION); - - if (adcIntCbfArra[ADC_INT_NEG_SATURATION] != NULL) { - adcIntCbfArra[ADC_INT_NEG_SATURATION](); - } - } - - if (ADC_IntGetMask(ADC_INT_FIFO_UNDERRUN) == UNMASK && ADC_GetIntStatus(ADC_INT_FIFO_UNDERRUN) == SET) { - ADC_IntClr(ADC_INT_FIFO_UNDERRUN); - - if (adcIntCbfArra[ADC_INT_FIFO_UNDERRUN] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_UNDERRUN](); - } - } - - if (ADC_IntGetMask(ADC_INT_FIFO_OVERRUN) == UNMASK && ADC_GetIntStatus(ADC_INT_FIFO_OVERRUN) == SET) { - ADC_IntClr(ADC_INT_FIFO_OVERRUN); - - if (adcIntCbfArra[ADC_INT_FIFO_OVERRUN] != NULL) { - adcIntCbfArra[ADC_INT_FIFO_OVERRUN](); - } - } - - if (ADC_IntGetMask(ADC_INT_ADC_READY) == UNMASK && ADC_GetIntStatus(ADC_INT_ADC_READY) == SET) { - ADC_IntClr(ADC_INT_ADC_READY); - - if (adcIntCbfArra[ADC_INT_ADC_READY] != NULL) { - adcIntCbfArra[ADC_INT_ADC_READY](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief ADC VBAT enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Vbat_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC VBAT disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_Vbat_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_VBAT_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC TSEN Config - * - * @param tsenMod: None - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Init(ADC_TSEN_MOD_Type tsenMod) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_AON_ADC_TSEN_MOD_TYPE(type)); - - /* config gpadc_reg_cmd */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - /* enable sensor dc test mux*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_SEN_TEST_EN); - /*selected sen output current channel*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_SEN_SEL, 0); - /* enable chip sensor*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_CHIP_SEN_PU); - /*dwa_en */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DWA_EN, 1); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); - - /* config 2 */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - /*tsvbe low=0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - /*dly_sel=2*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_DLY_SEL, 2); - /*test_sel=0*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TEST_SEL, 0); - /*test_en=0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TEST_EN); - /*ts_en*/ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); - /*select tsen ext or inner*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_TSEXT_SEL, tsenMod); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_VCM, 2); - /*pga vcmi enable*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - /*0:512uS;1:16mS;2:32mS;3:64mS*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, 0); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); - - /* config 3 */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG1); - /* set gpadc_dither_en */ - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_DITHER_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG1, tmpVal); - - /* set 4000F90C[19](gpadc_mic2_diff) = 1 - * debug advise form Ran - * 2020.08.26 - */ - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_MIC2_DIFF, 1); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC TSEN Enable - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC TSEN Disable - * - * @return None - * -*******************************************************************************/ -void ADC_Tsen_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC Clear fifo - * - * @return None - * -*******************************************************************************/ -void ADC_FIFO_Clear(void) -{ - uint32_t tmpVal; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief config pga - * - * @param pga_vcmi_enable: enable or not vcmi - * @param pga_os_cal: pga os cal value - * @return None - * -*******************************************************************************/ -void ADC_PGA_Config(uint8_t pga_vcmi_enable, uint8_t pga_os_cal) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - - if (pga_vcmi_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_PGA_VCMI_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_GPADC_PGA_OS_CAL, pga_os_cal); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} -/****************************************************************************/ /** - * @brief TSEN_Get_V_Error - * - * @param None - * - * @return None - * -*******************************************************************************/ -uint32_t TSEN_Get_V_Error(void) -{ - uint32_t v0 = 0, v1 = 0; - uint32_t v_error = 0; - uint32_t regVal = 0; - ADC_Result_Type result; - uint32_t tmpVal; - uint8_t gainCalEnabled = 0; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_LOW(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v0 = result.value; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_HIGH(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v1 = result.value; - - v_error = v0 - v1; - - return v_error; -} - -/****************************************************************************/ /** - * @brief Trim TSEN - * - * @param tsen_offset: None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION ADC_Trim_TSEN(uint16_t *tsen_offset) -{ - Efuse_TSEN_Refcode_Corner_Type trim; - - EF_Ctrl_Read_TSEN_Trim(&trim); - if (trim.tsenRefcodeCornerEn) { - if (trim.tsenRefcodeCornerParity == EF_Ctrl_Get_Trim_Parity(trim.tsenRefcodeCorner, 12)) { - *tsen_offset = trim.tsenRefcodeCorner; - - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_SET_TSVBE_LOW(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_SET_TSVBE_HIGH(void) -{ - uint32_t tmpVal; - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_TSVBE_LOW); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CONFIG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief SET ADC TSEN TSVBE LOW/HIGH - * - * @param tsen_offset: tsen_offset form efuse trim data - * - * @return tempture - * -*******************************************************************************/ -float TSEN_Get_Temp(uint32_t tsen_offset) -{ - uint32_t v0 = 0, v1 = 0; - float temp = 0; - uint32_t regVal = 0; - ADC_Result_Type result; - uint32_t tmpVal; - uint8_t gainCalEnabled = 0; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_LOW(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v0 = result.value; - - /* clear fifo by SET GPIP_GPADC_FIFO_CLR bit*/ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPADC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPADC_FIFO_CLR); - BL_WR_REG(GPIP_BASE, GPIP_GPADC_CONFIG, tmpVal); - - ADC_SET_TSVBE_HIGH(); - - ADC_Start(); - - while (ADC_Get_FIFO_Count() == 0) - ; - - regVal = ADC_Read_FIFO(); - gainCalEnabled = adcGainCoeffCal.adcGainCoeffEnable; - adcGainCoeffCal.adcGainCoeffEnable = 0; - ADC_Parse_Result(®Val, 1, &result); - adcGainCoeffCal.adcGainCoeffEnable = gainCalEnabled; - v1 = result.value; - - if (v0 > v1) { - temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753; - } else { - temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753; - } - - return temp; -} - -/****************************************************************************/ /** - * @brief ADC MIC Config - * - * @param adc_mic_config: adc_mic_config - * - * @return success or not - * -*******************************************************************************/ -BL_Err_Type ADC_Mic_Init(ADC_MIC_Type *adc_mic_config) -{ - uint32_t tmpVal1 = 0, tmpVal2 = 0; - - CHECK_PARAM(IS_ADC_MICBOOST_DB_Type(adc_mic_config->micboostDb)); - CHECK_PARAM(IS_PGA2_GAIN_Type(adc_mic_config->micPga2Gain)); - CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic1Mode)); - CHECK_PARAM(IS_ADC_MIC_MODE_Type(adc_mic_config->mic2Mode)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->dwaEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micboostBypassEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micPgaEn)); - CHECK_PARAM(IS_BL_Fun_Type(adc_mic_config->micBiasEn)); - - tmpVal2 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CONFIG2); - - tmpVal1 = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBOOST_32DB_EN, adc_mic_config->micboostDb); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC_PGA2_GAIN, adc_mic_config->micPga2Gain); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC1_DIFF, adc_mic_config->mic1Mode); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MIC2_DIFF, adc_mic_config->mic2Mode); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_DWA_EN, adc_mic_config->dwaEn); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_BYP_MICBOOST, adc_mic_config->micboostBypassEn); - - if (BL_IS_REG_BIT_SET(tmpVal2, AON_GPADC_PGA_EN) && adc_mic_config->micPgaEn == ENABLE) { - /* 0x4000F914[13] and 0x4000F90c[15] Cannot be both Enable*/ - return ERROR; - } else { - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICPGA_EN, adc_mic_config->micPgaEn); - } - - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, AON_GPADC_MICBIAS_EN, adc_mic_config->micBiasEn); - - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief ADC MIC bias control - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_MIC_Bias_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief ADC MIC bias control - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ADC_MIC_Bias_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD); - tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN); - BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal); -} - -/****************************************************************************/ /** - * @brief Trim ADC Gain - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION ADC_Gain_Trim(void) -{ - Efuse_ADC_Gain_Coeff_Type trim; - uint32_t tmp; - - EF_Ctrl_Read_ADC_Gain_Trim(&trim); - - if (trim.adcGainCoeffEn) { - if (trim.adcGainCoeffParity == EF_Ctrl_Get_Trim_Parity(trim.adcGainCoeff, 12)) { - adcGainCoeffCal.adcGainCoeffEnable = ENABLE; - adcGainCoeffCal.adcgainCoeffVal = trim.adcGainCoeff; - tmp = adcGainCoeffCal.adcgainCoeffVal; - - if (tmp & 0x800) { - tmp = ~tmp; - tmp += 1; - tmp = tmp & 0xfff; - //printf("val==%08x\r\n",(unsigned int)tmp); - adcGainCoeffCal.coe = (1.0 + ((float)tmp / 2048.0)); - //printf("coe==%0f\r\n",adcGainCoeffCal.coe); - } else { - adcGainCoeffCal.coe = (1.0 - ((float)tmp / 2048.0)); - //printf("coe==%0f\r\n",adcGainCoeffCal.coe); - } - - return SUCCESS; - } - } - - return ERROR; -} - -/*@} end of group ADC_Public_Functions */ - -/*@} end of group ADC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c deleted file mode 100644 index ed3e902940..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_audio.c +++ /dev/null @@ -1,2814 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_audio.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_audio.h" -#include "audio_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIO - * @{ - */ - -/** @defgroup AUDIO_Private_Macros - * @{ - */ - -/*@} end of group AUDIO_Private_Macros */ - -/** @defgroup AUDIO_Private_Types - * @{ - */ - -/*@} end of group AUDIO_Private_Types */ - -/** @defgroup AUDIO_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *audioIntCbfArra[AUDIO_INT_NUM_ALL] = { NULL }; -#endif -/*@} end of group AUDIO_Private_Variables */ - -/** @defgroup AUDIO_Global_Variables - * @{ - */ - -/*@} end of group AUDIO_Global_Variables */ - -/** @defgroup AUDIO_Private_Fun_Declaration - * @{ - */ - -/*@} end of group AUDIO_Private_Fun_Declaration */ - -/** @defgroup AUDIO_Private_Functions - * @{ - */ - -/*@} end of group AUDIO_Private_Functions */ - -/** @defgroup AUDIO_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Select Tx channel source Defaule is tx0-dac_0,tx1-dac_1 - * - * @param tx_channel: tx_channel index . Note tx_channel <=2 - * @param dac_id: tx[rx_channel] conect to dac_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Audio_Tx_Source_DAC_Sel(uint8_t tx_channel, Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (tx_channel > 2) { - return ERROR; - /*tx channel sel can not larger than 2*/ - } - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - - if (tx_channel == 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_TX0_SEL, dac_id); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_TX1_SEL, dac_id); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select Rx channel form ADC Channel . source Default selction is - * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1 - * - * @param rx_channel: rx_channel index . Note tx_channel <=4 - * @param adc_id: rx[rx_channel] conect to adc_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Audio_Rx_Source_ADC_Sel(uint8_t rx_channel, Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (rx_channel > 4) { - return ERROR; - /*rx channel sel can not larger than 4*/ - } - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - - switch (rx_channel) { - case 0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX0_SEL, adc_id); - break; - case 1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX1_SEL, adc_id); - break; - case 2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX2_SEL, adc_id); - break; - case 3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX3_SEL, adc_id); - break; - case 4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX4_SEL, adc_id); - break; - default: - break; - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select Rx channel form AEC Channel . source Default selction is - * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1 - * - * @param rx_channel: tx_channel index . Note tx_channel <=4 - * @param aec_id: rx[rx_channel] conect to aec_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Audio_Rx_Source_AEC_Sel(uint8_t rx_channel, Audio_AEC_ID_Type aec_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(aec_id)); - - if (rx_channel > 4) { - return ERROR; - /*rx channel sel can not larger than 4*/ - } - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - - switch (rx_channel) { - case 0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX0_SEL, aec_id + 3); - break; - case 1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX1_SEL, aec_id + 3); - break; - case 2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX2_SEL, aec_id + 3); - break; - case 3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX3_SEL, aec_id + 3); - break; - case 4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AUD_RX4_SEL, aec_id + 3); - break; - default: - break; - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio Set HPF Parameter - * - * @param id: ADC ID - * @param k1_enable: k1 parameter enable - * @param k1: k1 parameter in range 4 bit - * @param k2_enable: k2 parameter enable - * @param k2: k1 parameter in range 4 bit - * - * @return None - * -*******************************************************************************/ -void Audio_Set_HPF_Parameter(Audio_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_1); - - switch (id) { - case AUDIO_ADC_0: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_K2_EN); - } - break; - case AUDIO_ADC_1: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_K2_EN); - } - break; - case AUDIO_ADC_2: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_K1_EN); - } - - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_K2_EN); - } - break; - default: - break; - } - - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio Set ADC Source PDM or Analog - * - * @param id: k1 parameter in range 4 bit ,when k0=0 k0 parameter will disabled - * @param adc_source: k2 parameter in range 4 bit ,when k1=0 k1 parameter will disabled - * - * @return None - * -*******************************************************************************/ -void Audio_Set_ADC_Source(Audio_ADC_ID_Type id, Audio_ADC_Source_Type adc_source) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_SRC, adc_source); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_SRC, adc_source); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_SRC, adc_source); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio AEC enable - * - * @param id: Auido AEC ID - * - * @return None - * -*******************************************************************************/ -void Audio_AEC_Enable(Audio_AEC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_AEC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_AEC_0_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_AEC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio AEC disable - * - * @param id: Auido AEC ID - * - * @return None - * -*******************************************************************************/ -void Audio_AEC_Disable(Audio_AEC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_AEC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_AEC_0_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_AEC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio ADC enable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Enable(Audio_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_0_EN); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_ADC_2_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio ADC disable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Disable(Audio_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_ADC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_0_EN); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_ADC_2_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio DAC disable - * - * @param id: Auido DAC ID - * - * @return None - * -*******************************************************************************/ -void Audio_DAC_Enable(Audio_DAC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_DAC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_DAC_0_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_DAC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio DAC disable - * - * @param id: Auido DAC ID - * - * @return None - * -*******************************************************************************/ -void Audio_DAC_Disable(Audio_DAC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - if (id == AUDIO_DAC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_DAC_0_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_DAC_1_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief set dac amp - * - * @param enable: enable or noy - * @param amp: amp - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Dither(uint8_t enable, uint8_t amp) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_AMP, amp); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_DITHER_EN, 0); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief set dac scaling - * - * @param enable: enable or noy - * @param scaling: scaling - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Scaling(uint8_t enable, uint8_t scaling) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_FACTOR, scaling); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_SCALING_EN, 0); - } - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief set order - * - * @param order: order - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Order(Audio_DAC_Order_Type order) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ORDER_TYPE(order)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DSM_ORDER, order); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_DAC_Dwa_Swap - * - * @param swap: None - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Dwa_Swap(uint8_t swap) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DEM_OUT_SWAP, swap); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_DAC_Dsm_Bypass - * - * @param bypass: None - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_Dwa_Bypass(uint8_t bypass) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_DEM_BYPASS, bypass); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio set adc lfsr - * - * @param lfsrType: Auido ADC LFSR TYPE - * - * @return None - * -*******************************************************************************/ -void Audio_Set_DAC_LFSR(Audio_LFSR_Type lfsrType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_LFSR_TYPE(lfsrType)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_LFSR_MODE, lfsrType); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief read LSFR - * - * @param None - * - * @return read LSFR out - * -*******************************************************************************/ -BL_Sts_Type Audio_Get_ADC_LFSR(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_DITHER_DATA); -} - -/****************************************************************************/ /** - * @brief set adc scaling value - * - * @param id: Auido ADC ID - * @param scalingVal: scaling value - * - * @return None - * -*******************************************************************************/ -void Audio_Set_ADC_Scaling_Value(Audio_ADC_ID_Type id, uint8_t scalingVal) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_SCAL, scalingVal); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_SCAL, scalingVal); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_SCAL, scalingVal); - } - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set fir mode - * - * @param id: Auido ADC ID - * @param enable: enable or disable - * - * @return None - * -*******************************************************************************/ -void Audio_Set_Fir_Mode(Audio_ADC_ID_Type id, uint8_t enable) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_0); - - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_FIR_MODE, enable); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_FIR_MODE, enable); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_FIR_MODE, enable); - } - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief mixer setting function - * - * @param enable: enbale mixer or not,if disable mixer then other parameter is invalid - * @param mixerId: mixer Id,audio have two mixer to selected - * @param mode: mixer mode selection , debug mode or sidetone mode(other source is come form - * adc0-adc2) - * @param sidetoneChannel: mixer adc channel selection , if debug mode is selected this paramter is - * used , or user must select which adc source will be mixed with dac output. - * @param Volume: mixer Volume select - * - * @return None - * -*******************************************************************************/ -void Audio_Set_Mixer_Mode(uint8_t enable, Audio_Mixer_ID_Type mixerId, Audio_Mixer_Mode mode, Audio_ADC_ID_Type sidetoneChannel, Audio_Mixer_Volume_Type Volume) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_MIXER_ID_TYPE(sidetoneChannel)); - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(sidetoneChannel)); - CHECK_PARAM(IS_AUDIO_MIXER_VOLUME_TYPE(Volume)); - CHECK_PARAM(IS_AUDIO_MIXER_MODE(mode)); - - if (mixerId == AUDIO_MIXER_ID_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_1); - } - - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_MODE, mode); - if (mode == AUDIO_SECOND_DEBUG_MODE) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_ATT_MODE1, Volume); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_SEL, sidetoneChannel + 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_ATT_MODE2, Volume); - } - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MIX_0_MODE, 0); - } - - if (mixerId == AUDIO_MIXER_ID_0) { - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); - } else { - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_1, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief set adc swap - * - * @param id: Auido ADC ID - * @param swap: swap - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Mash_Bit_Swap(Audio_ADC_ID_Type id, uint8_t swap) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_MASH_BIT_SWAP, swap); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_MASH_BIT_SWAP, swap); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_MASH_BIT_SWAP, swap); - } - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm inv - * - * @param id: Auido ADC ID - * @param swap: inv - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_PDM_Inv_Swap(Audio_ADC_ID_Type id, uint8_t swap) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_0); - if (id == AUDIO_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap); - } else if (id == AUDIO_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_LVL_SWAP, swap); - } - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm value - * - * @param pdm_l: pdm l - * @param pdm_h: pdm h - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PDM_L, pdm_l); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PDM_H, pdm_l); - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_AEC_Record_Vid - * - * @param enable: enable or not - * @param div: div - * - * @return None - * -*******************************************************************************/ -void Audio_Set_AEC_Record_Vid(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AEC_0); - - if (enable) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_DIV, div); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_RECORD_VLD_4S_EN, 0); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AEC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_Set_AEC_Atten_mode - * - * @param aec_id: AEC ID - * @param mode: Atten Mode - * - * @return None - * -*******************************************************************************/ -void Audio_Set_AEC_Atten_mode(Audio_AEC_ID_Type aec_id, Audio_AEC_Atten_Mode mode) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AEC_ID_TYPE(aec_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AEC_0); - - if (aec_id == AUDIO_AEC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_0_ATTEN_MODE, mode); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AEC_1_ATTEN_MODE, mode); - } - - BL_WR_REG(AUDIO_BASE, AUDIO_AEC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio support three channel for pdm .Meanwhile Audio support two DMIC Interface which - * supporting four pdm data source input.This function is used to select channel with pdm - * source. - * - * @param id: pdm channel,cannot be larger than 3 - * @param pdmSel: pdm source select - * - * @return Success or not - * -*******************************************************************************/ -void Audio_ADC_PDM_Channel_Sel(Audio_PDM_ID_Type id, Audio_PDM_Source_Type pdmSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_PDM_SOURCE_TYPE(pdmSel)); - CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - - if (id == AUDIO_PDM_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_0_PDM_SEL, pdmSel); - } else if (id == AUDIO_PDM_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_1_PDM_SEL, pdmSel); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_2_PDM_SEL, pdmSel); - } - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio Enable PDM - * - * @param id: PDM ID - * - * @return Success or not - * -*******************************************************************************/ -void Audio_ADC_PDM_Enable(Audio_PDM_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - - if (id == AUDIO_PDM_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } else if (id == AUDIO_PDM_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_PDM_2_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio Disable PDM - * - * @param id: None - * - * @return Success or not - * -*******************************************************************************/ -void Audio_ADC_PDM_Disable(Audio_PDM_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_PDM_0); - - if (id == AUDIO_PDM_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } else if (id == AUDIO_PDM_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_PDM_0_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief debug 0x24 reigister - * - * @param wCmd: None - * - * @return None - * -*******************************************************************************/ -void Debug0_Write(uint32_t wCmd) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_DBG_0, wCmd); -} - -/****************************************************************************/ /** - * @brief debug 0x28 reigister - * - * @param None - * - * @return None - * -*******************************************************************************/ -uint32_t Debug1_Read(void) -{ - return BL_RD_REG(AUDIO_BASE, AUDIO_DBG_1); -} - -/****************************************************************************/ /** - * @brief debug 0x2c reigister - * - * @param wCmd: None - * - * @return None - * -*******************************************************************************/ -void Debug2_Write(uint32_t wCmd) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_DBG_2, wCmd); -} - -/****************************************************************************/ /** - * @brief debug 0x30 reigister - * - * @param wCmd: None - * - * @return None - * -*******************************************************************************/ -void Debug3_Write(uint32_t wCmd) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_DBG_3, wCmd); -} - -/****************************************************************************/ /** - * @brief AUDIO Interrupt mask - * - * @param intType: intType - * @param intMask: intMask - * - * @return None - * -*******************************************************************************/ -void Auido_IntMask(Audio_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case AUDIO_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - break; - - case AUDIO_INT_TX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_TX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - break; - case AUDIO_INT_TX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - } - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - break; - - case AUDIO_INT_ADC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_ADC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(AUDIO_BASE, AUDIO_ADC_S1_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - - case AUDIO_INT_ADC2_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_DAC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_DAC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_VAD: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_INT_CLR, intMask); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - break; - case AUDIO_INT_NUM_ALL: - if (intMask) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, 0x40A0A80); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT_EN); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, 0); - } - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief clear audio Interrupt flag - * - * @param intType: intType - * - * @return None - * -*******************************************************************************/ -void Auido_IntClear(Audio_INT_Type intType) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - - switch (intType) { - case AUDIO_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(AUDIO_BASE, AUDIO_RXU_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - break; - - case AUDIO_INT_TX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_TX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - break; - case AUDIO_INT_TX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - break; - - case AUDIO_INT_ADC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_ADC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(AUDIO_BASE, AUDIO_ADC_S1_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - - case AUDIO_INT_ADC2_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_DAC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_DAC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_VAD: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - tmpVal2 = tmpVal; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_INT_CLR, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal2); - break; - case AUDIO_INT_NUM_ALL: - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXA_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXU_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RXO_INT); - - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXA_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXU_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TXO_INT); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal | 0x40A0A80); - BL_WR_REG(AUDIO_BASE, AUDIO_STATUS, tmpVal); - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief register interrupt callback function pointer - * - * @param intType: intType - * @param cbFun: cbFun - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type Audio_Int_Callback_Install(Audio_INT_Type intType, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - - audioIntCbfArra[intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief read int flag - * - * @param intType: intType - * - * @return flag status - * -*******************************************************************************/ -BL_Sts_Type Audio_GetIntStatus(Audio_INT_Type intType) -{ - uint32_t tmpVal = 0; - BL_Sts_Type rlt = RESET; - - CHECK_PARAM(IS_AUDIO_INT_TYPE(intType)); - - switch (intType) { - case AUDIO_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXA_INT); - break; - case AUDIO_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXO_INT); - break; - case AUDIO_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_RXU_INT); - break; - - case AUDIO_INT_TX_FIFO_THR: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXA_INT); - break; - case AUDIO_INT_TX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXO_INT); - break; - case AUDIO_INT_TX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_TXU_INT); - break; - - case AUDIO_INT_ADC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S0_INT); - break; - case AUDIO_INT_ADC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S1_INT); - break; - - case AUDIO_INT_ADC2_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_S2_INT); - break; - case AUDIO_INT_DAC0_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_S0_INT); - break; - case AUDIO_INT_DAC1_SET_VOLUME_DONE: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_S1_INT); - break; - case AUDIO_INT_VAD: - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, AUDIO_VAD_INT); - break; - default: - break; - } - - return rlt; -} - -/****************************************************************************/ /** - * @brief rx fifo flush - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoClear(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_RX_FIFO_FLUSH); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Rx FIFO Count - * - * @param None - * - * @return fifi count - * -*******************************************************************************/ -uint32_t Audio_GetRxFifoCount(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_RXA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Read RX FIFO - * - * @param None - * - * @return fifo data - * -*******************************************************************************/ -uint32_t Audio_ReadRxFifo(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_DATA); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief tx fifo flush - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoClear(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_TX_FIFO_FLUSH); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Tx FIFO Count - * - * @param None - * - * @return fifi count - * -*******************************************************************************/ -uint32_t Audio_GetTxFifoCount(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_TXA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Wirte TX FIFO - * - * @param da: None - * - * @return fifo data - * -*******************************************************************************/ -void Audio_WriteTxFifo(uint32_t da) -{ - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_DATA, da); -} - -/****************************************************************************/ /** - * @brief Configure rx fifo - * - * @param cfg: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoConfig(Audio_FifoCfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_RESOLUTION_TYPE(cfg->resolution)); - CHECK_PARAM(IS_AUDIO_FIFO_AILGN_MODE(cfg->ailgnMode)); - CHECK_PARAM(IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DATA_RES, cfg->resolution); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DATA_MODE, cfg->ailgnMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DRQ_CNT, cfg->dmaThresholdMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_TRG_LEVEL, cfg->FifoIntThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_DRQ_EN, cfg->dmaEn); - - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_ITF_EN, cfg->dmaEn); - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable rx fifo - * - * @param ch: ch - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoEnable(uint8_t ch) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN, ch); - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable rx fifo - * - * @param ch: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Audio_RxFifoDisable(uint8_t ch) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN); - - tmpVal2 &= ~ch; - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_RX_CH_EN, tmpVal2); - - BL_WR_REG(AUDIO_BASE, AUDIO_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable rx fifo - * - * @param ch: ch - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoEnable(uint8_t ch) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN, ch); - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable rx fifo - * - * @param ch: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoDisable(uint8_t ch) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN); - - tmpVal2 &= ~ch; - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_CH_EN, tmpVal2); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Tx FIFO Count - * - * @param cfg: None - * - * @return None - * -*******************************************************************************/ -void Audio_TxFifoConfig(Audio_FifoCfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_RESOLUTION_TYPE(cfg->resolution)); - CHECK_PARAM(IS_AUDIO_FIFO_AILGN_MODE(cfg->ailgnMode)); - CHECK_PARAM(IS_AUDIO_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DATA_RES, cfg->resolution); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DATA_MODE, cfg->ailgnMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DRQ_CNT, cfg->dmaThresholdMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_TRG_LEVEL, cfg->FifoIntThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_TX_DRQ_EN, cfg->dmaEn); - - BL_WR_REG(AUDIO_BASE, AUDIO_TX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_ITF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_ITF_EN, cfg->dmaEn); - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief Audio_PEQ_Config - * - * @param peq_index: PEQ index should be in range[0,19] - * @param peqBypass: PEQ is bypass,if bypass b_pra and a_pra is vaild - * @param qtfm: PEQ qtfm - * @param b_pra: PEQ b_pra ,should be set as [19:0] arrary pointer which length is 3 - * @param a_pra: PEQ a_bra ,should be set as [19:0] arrary pointer which length is 2 - * - * @return PEQ Setting is success or not - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_PEQ_Config(uint8_t peq_index, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, uint32_t *b_pra, uint32_t *a_pra) -{ - uint32_t tmpVal = 0; - uint32_t peqAddr = 0; - if (peq_index > 19) { - return ERROR; - /* PEQ only support [0,19] index */ - } - peqAddr = AUDIO_BASE + 0x200 + (peq_index * 0x14); - - if (peqBypass == 0) { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_B0, b_pra[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_QFMT, qtfm); - - BL_WR_WORD(peqAddr, tmpVal); - - BL_WR_WORD(peqAddr + 0x04, b_pra[1]); - BL_WR_WORD(peqAddr + 0x08, b_pra[2]); - BL_WR_WORD(peqAddr + 0x0c, a_pra[0]); - BL_WR_WORD(peqAddr + 0x10, a_pra[1]); - - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - - } else { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_00_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio_ADC_PEQ_Config - * - * @param peq_index: PEQ index should be in range[0,19] - * @param peqBypass: PEQ is bypass,if bypass b_pra and a_pra is vaild - * @param qtfm: PEQ qtfm - * @param b_pra: PEQ b_pra ,should be set as [19:0] arrary pointer which length is 3 - * @param a_pra: PEQ a_bra ,should be set as [19:0] arrary pointer which length is 2 - * - * @return PEQ Setting is success or not - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_PEQ_Config(uint8_t peq_index, Audio_ADC_ID_Type adcChannel, uint8_t peqBypass, Audio_PEQ_QTFM_Type qtfm, uint32_t *b_pra, uint32_t *a_pra) -{ - uint32_t tmpVal = 0; - uint32_t peqAddr = 0; - if (peq_index > 19) { - return ERROR; - /* PEQ only support [0,19] index */ - } - peqAddr = AUDIO_BASE + 0x390 + (peq_index * 0x14); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x390); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_PEQ_IN_SEL, adcChannel); - BL_WR_WORD(peqAddr, tmpVal); - - if (peqBypass == 0) { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_B0, b_pra[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_QFMT, qtfm); - - BL_WR_WORD(peqAddr, tmpVal); - - BL_WR_WORD(peqAddr + 0x04, b_pra[1]); - BL_WR_WORD(peqAddr + 0x08, b_pra[2]); - BL_WR_WORD(peqAddr + 0x0c, a_pra[0]); - BL_WR_WORD(peqAddr + 0x10, a_pra[1]); - - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - - } else { - tmpVal = BL_RD_WORD(peqAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PEQ_20_BYP, peqBypass); - BL_WR_WORD(peqAddr, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio adc Mute - * - * @param muteSyncAllAdc: mute Sync All ADC Channle - * @param adc_id: adc id - * @param mute: Mute Or Not - * - * @return success or not - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Mute(BL_Fun_Type muteSyncAllAdc, Audio_ADC_ID_Type adc_id, Audio_Mute_Type mute) -{ - uint32_t tmpVal = 0; - uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - CHECK_PARAM(IS_AUDIO_MUTE_TYPE(mute)); - - if (muteSyncAllAdc) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_MUTE, mute); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC, tmpVal); - } else { - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE, mute); - BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio adc Mute - * - * @param muteSyncAllDac: mute Sync All DAC Channle - * @param dac_id: dac id - * @param mute: Mute Or Not - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Mute(BL_Fun_Type muteSyncAllDac, Audio_DAC_ID_Type dac_id, Audio_Mute_Type mute) -{ - uint32_t tmpVal = 0; - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id)); - CHECK_PARAM(IS_AUDIO_MUTE_TYPE(Mute)); - - if (muteSyncAllDac) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_MUTE, mute); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC, tmpVal); - } else { - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE, mute); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio adc Volume Config - * - * @param adc_id: adc id - * @param cfg: volume config cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Software_Volume_Config(Audio_ADC_ID_Type adc_id, Audio_Volume_Cfg_Type *cfg) -{ - uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate)); - CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode)); - CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_SOFTMODE, cfg->muteMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_RMPDN_RATE, cfg->muteRmpdnRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_MUTE_RMPUP_RATE, cfg->muteRmpupRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_MODE, cfg->volumeCtrMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_RMP_RATE, cfg->volumeRmpRate); - BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal); - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout); - BL_WR_WORD(adcVolumeConfigAddrOffset + 0x04, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio DAC Volume Config - * - * @param dac_id: dac id - * @param cfg: volume config cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Software_Volume_Config(Audio_DAC_ID_Type dac_id, Audio_Volume_Cfg_Type *cfg) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate)); - CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode)); - CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_SOFTMODE, cfg->muteMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_RMPDN_RATE, cfg->muteRmpdnRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_MUTE_RMPUP_RATE, cfg->muteRmpupRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_MODE, cfg->volumeCtrMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_RMP_RATE, cfg->volumeRmpRate); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout); - BL_WR_WORD(dacVolumeConfigAddrOffset + 0x04, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set adc volume - * - * @param volumeSyncAllAdc: sync volume configuration for three adc channel - * @param adc_id: adc id - * @param volume: volume - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Volume(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (volumeSyncAllAdc) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x408 + 0x04, tmpVal); - - //TODO AUDIO_ADC_SX_VOLUME_UPDATE/AUDIO_ADC_S012_VOLUME_UPDATE should be reset in isr - - } else { - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - - //TODO AUDIO_ADC_SX_VOLUME_UPDATE/AUDIO_ADC_S012_VOLUME_UPDATE should be reset in isr - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set dac volume - * - * @param volumeSyncAllDac: sync volume configuration for two dac channel - * @param dac_id: dac id - * @param volume: volume - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Volume(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - if (volumeSyncAllDac) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x434 + 0x04, tmpVal); - - //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr - - } else { - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear adc update bit - * - * @param adc_id: adc id - * - * @return None - * -*******************************************************************************/ -void Audio_ADC_Reset_Volume_Update(Audio_ADC_ID_Type adc_id) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return; - /*only support 3 adc*/ - } - - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, 0); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); -} - -/****************************************************************************/ /** - * @brief clear dac update bit - * - * @param dac_id: dac id - * - * @return None - * -*******************************************************************************/ -void Audio_DAC_Reset_Volume_Update(Audio_DAC_ID_Type dac_id) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return; - /*only support 2 dac*/ - } - - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, 0); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); -} - -/****************************************************************************/ /** - * @brief clear adc or dac all update bit, when enable sync bit to set all channel dac/adc volume - * ,user should use this function to clear all update flag. - * - * @param isAdcOrDac: IS ADC or DAC,ADC=1 DAC=0 - * - * @return None - * -*******************************************************************************/ -void Audio_Reset_Volume_All_Update(uint8_t isAdcOrDac) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - if (isAdcOrDac) { - BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_S0_MISC, tmpVal); - } else { - BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_S0_MISC, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Audio set all adc volume Reg Without seting update bit - * - * @param volumeSyncAllAdc: is set all adc - * @param adc_id: adc id - * @param volume: volume - * - * @return Success or Not - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (volumeSyncAllAdc) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal); - - } else { - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set all DAC volume Reg Without seting update bit - * - * @param volumeSyncAllDac: is set all dac - * @param dac_id: dac id - * @param volume: volume - * - * @return Success or Not - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Volume_Reg(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - if (volumeSyncAllDac) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal); - - } else { - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set adc volume - * - * @param volumeSyncAllAdc: sync volume configuration for three adc channel,This function will - * blocking CPU until volume adjust task done - * @param adc_id: adc id - * @param volume: volume - * @param blockTimeout: volume block timeout - * - * @return Configuration is success - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Set_Volume_Block(BL_Fun_Type volumeSyncAllAdc, Audio_ADC_ID_Type adc_id, uint16_t volume, uint32_t blockTimeout) -{ - uint32_t adcVolumeAddrOffset = AUDIO_BASE + 0x408 + adc_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (volumeSyncAllAdc) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x408, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x410); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x410, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x418); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S2_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x418, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x408 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x408 + 0x04, tmpVal); - - while (Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_0) && Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_1) && Audio_IS_ADC_Volume_Set_Busy(AUDIO_ADC_2)) { - blockTimeout--; - if (blockTimeout) { - return TIMEOUT; - } - } - //clear update - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S012_VOLUME_UPDATE, 0); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - - } else { - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - - while (Audio_IS_ADC_Volume_Set_Busy(adc_id)) { - blockTimeout--; - if (blockTimeout) { - return TIMEOUT; - } - } - //clear update - tmpVal = BL_RD_WORD(adcVolumeAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME_UPDATE, 0); - BL_WR_WORD(adcVolumeAddrOffset, tmpVal); - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set dac volume - * - * @param volumeSyncAllDac: sync volume configuration for two dac channel ,This function will - * blocking CPU until volume adjust task done - * @param dac_id: adc id - * @param volume: volume - * @param blockTimeout: volume block timeout - * - * @return is success or not - * -*******************************************************************************/ -BL_Err_Type Audio_DAC_Set_Volume_Block(BL_Fun_Type volumeSyncAllDac, Audio_DAC_ID_Type dac_id, uint16_t volume, uint32_t blockTimeout) -{ - uint32_t dacVolumeConfigAddrOffset = AUDIO_BASE + 0x434 + dac_id * 0x08; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DAC_ID_TYPE(dac_id)); - - if (dac_id > 1) { - return ERROR; - /*only support 2 dac*/ - } - - if (volumeSyncAllDac) { - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x434, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x43c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S1_VOLUME, volume); - BL_WR_WORD(AUDIO_BASE + 0x43c, tmpVal); - - tmpVal = BL_RD_WORD(AUDIO_BASE + 0x434 + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 1); - BL_WR_WORD(AUDIO_BASE + 0x434 + 0x04, tmpVal); - - while (Audio_IS_DAC_Volume_Set_Busy(AUDIO_DAC_0) && Audio_IS_DAC_Volume_Set_Busy(AUDIO_DAC_1)) { - blockTimeout--; - if (blockTimeout) { - return TIMEOUT; - } - } - //clear update - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S01_VOLUME_UPDATE, 0); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - } else { - tmpVal = BL_RD_WORD(dacVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME, volume); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME_UPDATE, 1); - BL_WR_WORD(dacVolumeConfigAddrOffset, tmpVal); - - //TODO AUDIO_DAC_SX_VOLUME_UPDATE/AUDIO_DAC_S01_VOLUME_UPDATE should be reset in isr - } - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Audio set adc agc hardware volume config - * - * @param cfg: cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Audio_ADC_Hardware_Volume_Config(Audio_Volume_Cfg_Type *cfg) -{ - uint32_t adcVolumeConfigAddrOffset = AUDIO_BASE + AUDIO_ADC_H_OFFSET; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_MUTE_MODE(cfg->muteMode)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpdnRate)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->muteRmpupRate)); - CHECK_PARAM(IS_AUDIO_VOLUME_CTR_MODE(cfg->volumeCtrMode)); - CHECK_PARAM(IS_AUDIO_ZERO_CROSS_RATE_TYPE(cfg->resovolumeZeroCrossRatelution)); - CHECK_PARAM(IS_AUDIO_RAMP_RATE_TYPE(cfg->volumeRmpRate)); - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE, cfg->muteMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE_RMPDN_RATE, cfg->muteRmpdnRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_MUTE_RMPUP_RATE, cfg->muteRmpupRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_MODE, cfg->volumeCtrMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_ZCD_RATE, cfg->volumeZeroCrossRate); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_RMP_RATE, cfg->volumeRmpRate); - BL_WR_WORD(adcVolumeConfigAddrOffset, tmpVal); - - tmpVal = BL_RD_WORD(adcVolumeConfigAddrOffset + 0x04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_CTRL_ZCD_TIMEOUT, cfg->volumeZeroCrossTimeout); - BL_WR_WORD(adcVolumeConfigAddrOffset + 0x04, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this - * function - * - * @param None - * - * @return AGC ctr result - * -*******************************************************************************/ -uint16_t Audio_ADC_Get_Hardware_Volume(void) -{ - uint32_t tmpVal = 0; - uint16_t volume = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_H); - volume = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_ADC_H_VOLUME); - - return volume; -} - -/****************************************************************************/ /** - * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this - * function - * - * @param adc_id: adc id - * - * @return adc volume - * -*******************************************************************************/ -uint16_t Audio_ADC_Get_Volume(Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - uint16_t volume = 0; - - if (adc_id == AUDIO_ADC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S0); - } else if (adc_id == AUDIO_ADC_1) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S1); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_S2); - } - - volume = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_ADC_S0_VOLUME); - - return volume; -} - -/****************************************************************************/ /** - * @brief when AGC is enable , software cannot change volume,but can read AGC ctrl result by this - * function - * - * @param dac_id: dac id - * - * @return dac volume - * -*******************************************************************************/ -uint16_t Audio_DAC_Get_Volume(Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - if (dac_id == AUDIO_DAC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S0); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_S1); - } - - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, AUDIO_DAC_S0_VOLUME); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief is audio mute done or not . - * - * @param adc_id: adc id - * - * @return is adc mute done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_ADC_Mute_Done(Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (adc_id == AUDIO_ADC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H0_MUTE_DONE); - } else if (adc_id == AUDIO_ADC_1) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H1_MUTE_DONE); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H2_MUTE_DONE); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param adc_id: adc id - * - * @return is adc volume set done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_ADC_Volume_Set_Busy(Audio_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(adc_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (adc_id == AUDIO_ADC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H0_BUSY); - } else if (adc_id == AUDIO_ADC_1) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H1_BUSY); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_ADC_H2_BUSY); - } -} - -/****************************************************************************/ /** - * @brief is audio mute done or not . - * - * @param dac_id: dac id - * - * @return is dac mute done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_DAC_Mute_Set_Done(Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (dac_id == AUDIO_DAC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H0_MUTE_DONE); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H1_MUTE_DONE); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param dac_id: dac id - * - * @return is dac_id done - * -*******************************************************************************/ -BL_Sts_Type Audio_IS_DAC_Volume_Set_Busy(Audio_DAC_ID_Type dac_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_ID_TYPE(dac_id)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_STATUS); - - if (dac_id == AUDIO_DAC_0) { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H0_BUSY); - } else { - return BL_IS_REG_BIT_SET(tmpVal, AUDIO_DAC_H1_BUSY); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param enable: enable agc - * @param cfg: agc cfg - * - * @return None - * -*******************************************************************************/ -void Audio_AGC_Init(uint8_t enable, Audio_AGC_Config_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_AGC_SRC_TYPE(cfg->agc_src_select)); - CHECK_PARAM(IS_AUDIO_AGC_DETECT_MODE(cfg->agc_detect_mode)); - - if (enable) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_FORCE_GAIN_EN, cfg->agc_force_gain_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_FORCE_GAIN_IND, cfg->agc_force_gain_ind); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_MAX_GAIN_QDB, cfg->agc_max_gain_qdb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_MIN_GAIN_QDB, cfg->agc_min_gain_qdb); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_TARGET, cfg->agc_level_target); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_HYST_ATTACK, cfg->agc_level_hyst_attack); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_LEVEL_HYST_DECAY, cfg->agc_level_hyst_decay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_HOLD_TIME_MS, cfg->agc_hold_time_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DECAY_TIME_MS, cfg->agc_decay_time_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_ATTACK_TIME_MS, cfg->agc_attack_time_ms); - //tmpVal = BL_SET_REG_BITS_VAL(tmpVal,AUDIO_ADC3_PGA_HW_CTRL,cfg->adc3_pga_hw_ctrl); //TODO - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_HW_CTRL, cfg->adc2_pga_hw_ctrl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_HW_CTRL, cfg->adc1_pga_hw_ctrl); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_GATE_TH, cfg->agc_noise_gate_th); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_GATE_HYST, cfg->agc_noise_gate_hyst); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SILENCE_GAIN_QDB, cfg->agc_silence_gain_qdb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SILENCE_GAIN_WAIT_MS, cfg->agc_silence_gain_wait_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_ENTER_TIME_MS, cfg->agc_noise_enter_time_ms); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_2, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_NOISE_EXIT_TIME_MS, cfg->agc_noise_exit_time_ms); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DBV_SETTLE_TIME, cfg->agc_dbv_settle_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_SRC_SELECT, cfg->agc_src_select); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_DETECT_MODE, cfg->agc_detect_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_ATTACK_TIME, cfg->agc_attack_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_RELEASE_TIME, cfg->agc_release_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_AVERAGE_TIME, cfg->agc_average_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_AGC_PGA_CTRL_EN, cfg->agc_pga_ctrl_en); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_3, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal); - - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_ADC_AGC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_AGC_EN, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_ADC_AGC_0, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief is audio mute & volume set are busy or not . - * - * @param enable: enable drc - * @param cfg: drc cfg - * - * @return None - * -*******************************************************************************/ -void Audio_DRC_Init(uint8_t enable, Audio_DRC_Config_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_raw_sel)); - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_peak_sel)); - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->drc_avg_sel)); - CHECK_PARAM(IS_AUDIO_DRC_DATA_TYPE(cfg->ngt_src_sel)); - - if (enable) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RAW_SEL, cfg->drc_raw_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_PEAK_SEL, cfg->drc_peak_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_SEL, cfg->drc_avg_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_EN, cfg->drc_avg_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_AVG_TIME, cfg->drc_avg_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_ATT_TIME, cfg->drc_att_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RLS_TIME, cfg->drc_rls_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_NGT_DOWNSAMPLE_EN, cfg->drc_ngt_downsample_en); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_L, cfg->drc_threshold_l); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_C, cfg->drc_threshold_c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_THRESHOLD_E, cfg->drc_threshold_e); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_SLOPE_MODE_C, cfg->drc_slope_mode_c); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_SLOPE_MODE_E, cfg->drc_slope_mode_e); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_MAKEUP_GAIN, cfg->drc_makeup_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_ATTACK_TIME, cfg->drc_attack_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_RELEASE_TIME, cfg->drc_release_time); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_NGT_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_EN, cfg->ngt_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SRC_SEL, cfg->ngt_src_sel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_AVG_TIME, cfg->ngt_avg_time); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_THRESHOLD, cfg->ngt_threshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_HYSTERESIS, cfg->ngt_hysteresis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_NOISE_HOLD_EN, cfg->ngt_noise_hold_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_NOISE_HOLD_TIME_K, cfg->ngt_noise_hold_time_k); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SIGNAL_HOLD_EN, cfg->ngt_signal_hold_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_SIGNAL_HOLD_TIME_K, cfg->ngt_signal_hold_time_k); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_NGT_DMUTE_ON, cfg->ngt_dmute_on); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_NGT_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_ZD_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ZD_EN, cfg->zd_en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ZD_TIME, cfg->zd_time); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_ZD_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal); - - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_DAC_DRC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DRC_EN, 0); - BL_WR_REG(AUDIO_BASE, AUDIO_DAC_DRC_0, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Audio interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AUDIO_IRQHandler(void) -{ - uint8_t intIndex = 0; - - for (intIndex = 0; intIndex < AUDIO_INT_NUM_ALL; intIndex++) { - if (Audio_GetIntStatus(intIndex) == SET) { - if (audioIntCbfArra[intIndex] != NULL) { - audioIntCbfArra[intIndex](); - } - Auido_IntClear(intIndex); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Audio Clock Initialization Function - * - * @param cfg: clock configuration pra - * - * @return None - * -*******************************************************************************/ -void Audio_Clock_Init(Audio_Clock_CFG_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_ADC_CLOCK_TYPE(cfg->adc_clock)); - CHECK_PARAM(IS_AUDIO_DAC_CLOCK_TYPE(cfg->dac_clock)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_AUD_TOP); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_RATE, cfg->adc_clock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RATE, cfg->dac_clock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_PDM_ITF_INV_SEL, cfg->pdm_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC_ITF_INV_SEL, cfg->adc_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_ITF_INV_SEL, cfg->dac_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CKG_EN, 1); - - BL_WR_REG(AUDIO_BASE, AUDIO_AUD_TOP, tmpVal); - - //TODO to select postion of register interrupt -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(AUDIO_IRQn, AUDIO_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief VAD Configuration function - * - * @param cfg: VAD configuration pra - * - * @return None - * -*******************************************************************************/ -void Audio_VAD_Init(Audio_VAD_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUDIO_VAD_SOURCE_TYPE(cfg->vadSource)); - CHECK_PARAM(IS_AUDIO_VAD_FRAMINGSHIFT_TYPE(cfg->vadFramingShift)); - CHECK_PARAM(IS_AUDIO_VAD_FRAMINGTIME_TYPE(cfg->vadFramingTime)); - CHECK_PARAM(IS_AUDIO_VAD_IRQ_SOURCE_TYPE(cfg->vadIRQSource)); - CHECK_PARAM(IS_AUDIO_VAD_NOISYBUFFERLEN_TYPE(cfg->vadNoisyBufferLen)); - CHECK_PARAM(IS_AUDIO_VAD_NOISYBUFFERMONITOR_TYPE(cfg->vadNoisyBufferMonitor)); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_MONIT_EN, cfg->vadNoisyBufferMonitorEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_MONIT_CTRL, cfg->vadNoisyBufferMonitor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_LEN_CTRL, cfg->vadNoisyBufferLen); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_OUT_SEL, cfg->vadIRQSource); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_FRAMETIME_CTRL, cfg->vadFramingTime); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_FRAMESHIFT_CTRL, cfg->vadFramingShift); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_IN_SEL, cfg->vadSource); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MAXLMT_EN, cfg->vadNoisyMaxLimitEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MINLMT_EN, cfg->vadNoisyMinLimitEnable); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_2); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MINLMT, cfg->vadNoisyMinLimit); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_MAXLMT, cfg->vadNoisyMaxLimit); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_2, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_3); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_SMOOTH_FALL, cfg->vadSmoothFall); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_SMOOTH_RISE, cfg->vadSmoothRise); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_3, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_1); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_SCALE, cfg->noisyBufferThrScale); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NTH_BIAS, cfg->noisyBufferThrBais); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NBUF_DISCARD, cfg->noisyBufferDiscardNumber); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_5); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_VAD_NOISE_TH, cfg->noisyBufferThr); - - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_5, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable VAD - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_VAD_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, AUDIO_VAD_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable VAD - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_VAD_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, AUDIO_VAD_EN); - BL_WR_REG(AUDIO_BASE, AUDIO_VAD_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief VAD set EK function - * - * @param None - * - * @return None - * -*******************************************************************************/ -uint32_t Audio_VAD_Get_EK(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_VAD_CTRL_4); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief audio power on - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Audio_Poweron(void) -{ - uint32_t tmpVal = 0; - - /* common */ - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_POWER1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_MICBIAS_PU, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CODEC_VRDA_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_CODEC_IBIAS_CTRL, 5); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_POWER1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_POWER2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_LDO25_PU, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_HPBG_PU, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_POWER2, tmpVal); - - /*DAC power on*/ - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_SDAC_LINEOUT, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_LINEOUT_MODE, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_EN_DAC, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_EN_LINEOUT, 1); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_SDAC_LINEOUT, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_LINEOUT_MODE, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_EN_DAC, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_EN_LINEOUT, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC_RAMP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RG_LO_VREF_RAMP_DCL_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DAC_RG_PU_VREF_RAMP, 1); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC_RAMP, tmpVal); - - /*ADC Power on */ - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_EN_SDM, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_EN_PGA, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_PGA_GAIN, 8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_ICTRL_ADC2, 3); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC0, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_EN_SDM, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_EN_PGA, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_GAIN, 8); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC1, tmpVal); - - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_EN_SDM, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_EN_PGA, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_GAIN, 8); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC2, tmpVal); - - /* best digital filter configuration*/ - Audio_Set_DAC_Scaling(1, 14); -} - -void Audio_SetADCAnalogGain(Audio_ADC_ID_Type adc, uint8_t analogGain) -{ - uint32_t tmpVal = 0; - - if (adc == AUDIO_ADC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC0_PGA_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC0, tmpVal); - } else if (adc == AUDIO_ADC_1) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC1_PGA_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC1, tmpVal); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_ADC2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_ADC2_PGA_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_ADC2, tmpVal); - } -} - -void Audio_SetDACAnalogGain(Audio_DAC_ID_Type dac, uint8_t analogGain) -{ - uint32_t tmpVal = 0; - - if (dac == AUDIO_DAC_0) { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACL_LINEOUT_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal); - } else { - tmpVal = BL_RD_REG(AUDIO_BASE, AUDIO_CODEC_DAC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AUDIO_DACR_LINEOUT_GAIN, analogGain); - BL_WR_REG(AUDIO_BASE, AUDIO_CODEC_DAC, tmpVal); - } -} - -/*@} end of group AUDIO_Public_Functions */ - -/*@} end of group AUDIO */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c deleted file mode 100644 index 374422e229..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aupdm.c +++ /dev/null @@ -1,777 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_pdm.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_aupdm.h" -#include "pdm_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup AUDIOPDM - * @{ - */ - -/** @defgroup AUDIOPDM_Private_Macros - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Macros */ - -/** @defgroup AUDIOPDM_Private_Types - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Types */ - -/** @defgroup AUDIOPDM_Private_Variables - * @{ - */ -static intCallback_Type *aupdmIntCbfArra[AUPDM_INT_NUM_ALL] = { NULL }; - -/*@} end of group AUDIOPDM_Private_Variables */ - -/** @defgroup AUDIOPDM_Global_Variables - * @{ - */ - -/*@} end of group AUDIOPDM_Global_Variables */ - -/** @defgroup AUDIOPDM_Private_Fun_Declaration - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Fun_Declaration */ - -/** @defgroup AUDIOPDM_Private_Functions - * @{ - */ - -/*@} end of group AUDIOPDM_Private_Functions */ - -/** @defgroup AUDIOPDM_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief AUDIO Interrupt mask - * - * @param intType: intType - * @param intMask: intMask - * - * @return None - * -*******************************************************************************/ -void Aupdm_IntMask(Aupdm_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case AUPDM_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXA_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT_EN); - } - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - break; - case AUPDM_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXO_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT_EN); - } - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - break; - case AUPDM_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - if (intMask) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXU_INT_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT_EN); - } - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - break; - - case AUPDM_INT_NUM_ALL: - if (intMask) { - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXA_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXU_INT_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_RXO_INT_EN); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - - } else { - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT_EN); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - } - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief read int flag - * - * @param intType: intType - * - * @return flag status - * -*******************************************************************************/ -BL_Sts_Type Aupdm_GetIntStatus(Aupdm_INT_Type intType) -{ - uint32_t tmpVal = 0; - BL_Sts_Type rlt = RESET; - - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - - switch (intType) { - case AUPDM_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXA_INT); - break; - case AUPDM_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXO_INT); - break; - case AUPDM_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - rlt = BL_IS_REG_BIT_SET(tmpVal, PDM_RXU_INT); - break; - default: - break; - } - - return rlt; -} - -/****************************************************************************/ /** - * @brief clear audio Interrupt flag - * - * @param intType: intType - * - * @return None - * -*******************************************************************************/ -void Aupdm_IntClear(Aupdm_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - - switch (intType) { - case AUPDM_INT_RX_FIFO_THR: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - break; - case AUPDM_INT_RX_FIFO_OVERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - break; - case AUPDM_INT_RX_FIFO_UNDERRUN: - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_SET_REG_BIT(PDM0_BASE, PDM_RXU_INT); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - break; - - case AUPDM_INT_NUM_ALL: - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXA_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXU_INT); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RXO_INT); - - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_STATUS, tmpVal); - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief AUPDM PDM interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void AUPDM_PDM_IRQHandler(void) -{ - uint8_t intIndex = 0; - - for (intIndex = 0; intIndex < AUPDM_INT_NUM_ALL; intIndex++) { - if (Aupdm_GetIntStatus(intIndex) == SET) { - aupdmIntCbfArra[intIndex](); - Aupdm_IntClear(intIndex); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief AUPDM PDM Clock Initialization Function - * - * @param cfg: clock configuration pra - * - * @return None - * -*******************************************************************************/ -void Aupdm_Clock_Init(Aupdm_Clock_CFG_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_CLOCK_TYPE(cfg->adc_clock)); - CHECK_PARAM(IS_AUPDM_DAC_CLOCK_TYPE(cfg->dac_clock)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_TOP); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_RATE, cfg->adc_clock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ITF_INV_SEL, cfg->pdm_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_ITF_INV_SEL, cfg->adc_clk_inv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUDIO_CKG_EN, 1); - - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_TOP, tmpVal); - -//TODO to select postion of register interrupt -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(AUPDM_TOUCH_IRQn, AUPDM_PDM_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief AUPDM support three channel for pdm .Meanwhile AUPDM support two DMIC Interface which - * supporting four pdm data source input.This function is used to select channel with pdm - * source. - * - * @param id: pdm channel,cannot be larger than 3 - * @param pdmSel: pdm source select - * - * @return Success or not - * -*******************************************************************************/ -void Aupdm_PDM_Channel_Sel(Aupdm_PDM_ID_Type id, Aupdm_PDM_Source_Type pdmSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_PDM_SOURCE_TYPE(pdmSel)); - CHECK_PARAM(IS_AUPDM_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_PDM_0); - - if (id == AUPDM_PDM_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_PDM_SEL, pdmSel); - } else if (id == AUPDM_PDM_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_PDM_SEL, pdmSel); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_PDM_SEL, pdmSel); - } - BL_WR_REG(PDM0_BASE, PDM_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM Enable PDM - * - * @param id: PDM ID - * - * @return Success or not - * -*******************************************************************************/ -void Aupdm_PDM_Enable(Aupdm_PDM_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_PDM_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_PDM_0); - - if (id == AUPDM_PDM_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_0_EN); - } else if (id == AUPDM_PDM_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_2_EN); - } - BL_WR_REG(PDM0_BASE, PDM_PDM_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief register interrupt callback function pointer - * - * @param intType: intType - * @param cbFun: cbFun - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Aupdm_Int_Callback_Install(Aupdm_INT_Type intType, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_AUPDM_INT_TYPE(intType)); - - aupdmIntCbfArra[intType] = cbFun; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief rx fifo flush - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoClear(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_RX_FIFO_FLUSH); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get Rx FIFO Count - * - * @param None - * - * @return fifi count - * -*******************************************************************************/ -uint32_t Aupdm_GetRxFifoCount(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDM_RXA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Read RX FIFO - * - * @param None - * - * @return fifo data - * -*******************************************************************************/ -uint32_t Aupdm_ReadRxFifo(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_DATA); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief Configure rx fifo - * - * @param cfg: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoConfig(Aupdm_FifoCfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_RESOLUTION_TYPE(cfg->resolution)); - CHECK_PARAM(IS_AUPDM_FIFO_AILGN_MODE(cfg->ailgnMode)); - CHECK_PARAM(IS_AUPDM_FIFO_DQR_THRESHOLD_MODE(cfg->dmaThresholdMode)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DATA_RES, cfg->resolution); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DATA_MODE, cfg->ailgnMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DRQ_CNT, cfg->dmaThresholdMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_TRG_LEVEL, cfg->FifoIntThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_DRQ_EN, cfg->dmaEn); - - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_ITF_EN, cfg->dmaEn); - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief enable rx fifo - * - * @param ch: ch - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoEnable(uint8_t ch) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN, ch); - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief disable rx fifo - * - * @param ch: fifo cfg - * - * @return None - * -*******************************************************************************/ -void Aupdm_RxFifoDisable(uint8_t ch) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_RX_FIFO_CTRL); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN); - - tmpVal2 &= ~ch; - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_RX_CH_EN, tmpVal2); - - BL_WR_REG(PDM0_BASE, PDM_RX_FIFO_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select Rx channel form ADC Channel . source Default selction is - * rx0-adc_0,rx1-adc_1,rx2-adc_2,rx3-aec_0,rx4-aec_1 - * - * @param rx_channel: rx_channel index . Note tx_channel <=4 - * @param adc_id: rx[rx_channel] conect to adc_id - * - * @return Success or not - * -*******************************************************************************/ -BL_Err_Type Aupdm_Rx_Source_ADC_Sel(uint8_t rx_channel, Aupdm_ADC_ID_Type adc_id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(adc_id)); - - if (rx_channel > 4) { - return ERROR; - /*rx channel sel can not larger than 4*/ - } - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - - switch (rx_channel) { - case 0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX0_SEL, adc_id); - break; - case 1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX1_SEL, adc_id); - break; - case 2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_AUD_RX2_SEL, adc_id); - break; - default: - break; - } - - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AUPDM ADC enable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_Enable(Aupdm_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_EN); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_EN); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_EN); - } - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM ADC disable - * - * @param id: Auido ADC ID - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_Disable(Aupdm_ADC_ID_Type id) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_AUDPDM_ITF); - if (id == AUPDM_ADC_0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_EN); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_EN); - } - BL_WR_REG(PDM0_BASE, PDM_AUDPDM_ITF, tmpVal); -} - -/****************************************************************************/ /** - * @brief set adc scaling value - * - * @param id: Auido ADC ID - * @param scalingVal: scaling value - * - * @return None - * -*******************************************************************************/ -void Aupdm_Set_ADC_Scaling_Value(Aupdm_ADC_ID_Type id, uint8_t scalingVal) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_0); - - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_SCAL, scalingVal); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_SCAL, scalingVal); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_SCAL, scalingVal); - } - BL_WR_REG(PDM0_BASE, PDM_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set fir mode - * - * @param id: Auido ADC ID - * @param enable: enable or disable - * - * @return None - * -*******************************************************************************/ -void Aupdm_Set_Fir_Mode(Aupdm_ADC_ID_Type id, uint8_t enable) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_0); - - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_FIR_MODE, enable); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_FIR_MODE, enable); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_FIR_MODE, enable); - } - BL_WR_REG(PDM0_BASE, PDM_ADC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM Set HPF Parameter - * - * @param id: ADC ID - * @param k1_enable: k1 parameter enable - * @param k1: k1 parameter in range 4 bit - * @param k2_enable: k2 parameter enable - * @param k2: k1 parameter in range 4 bit - * - * @return None - * -*******************************************************************************/ -void Aupdm_Set_HPF_Parameter(Aupdm_ADC_ID_Type id, uint8_t k1_enable, uint8_t k1, uint8_t k2_enable, uint8_t k2) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_ADC_1); - - switch (id) { - case AUPDM_ADC_0: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_0_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_0_K2_EN); - } - break; - case AUPDM_ADC_1: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_K1_EN); - } - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_1_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_1_K2_EN); - } - break; - case AUPDM_ADC_2: - if (k1_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_K1_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_K1, k1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_K1_EN); - } - - if (k2_enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, PDM_ADC_2_K2_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_K2, k2); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, PDM_ADC_2_K2_EN); - } - break; - default: - break; - } - - BL_WR_REG(PDM0_BASE, PDM_ADC_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm inv - * - * @param id: Auido ADC ID - * @param swap: inv - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_PDM_Inv_Swap(Aupdm_ADC_ID_Type id, uint8_t swap) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_AUPDM_ADC_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_DAC_0); - if (id == AUPDM_ADC_0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_0_PDM_LVL_SWAP, swap); - } else if (id == AUPDM_ADC_1) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_1_PDM_LVL_SWAP, swap); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_2_PDM_LVL_SWAP, swap); - } - BL_WR_REG(PDM0_BASE, PDM_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief set pdm value - * - * @param pdm_l: pdm l - * @param pdm_h: pdm h - * - * @return None - * -*******************************************************************************/ -void Aupdm_ADC_Set_PDM_Value(uint8_t pdm_l, uint8_t pdm_h) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(PDM0_BASE, PDM_DAC_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_PDM_L, pdm_l); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDM_ADC_PDM_H, pdm_l); - BL_WR_REG(PDM0_BASE, PDM_DAC_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief AUPDM adc Volume Config - * - * @param adc_id: adc id - * @param volume: volume config cfg pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type Aupdm_ADC_Volume_Config(Aupdm_ADC_ID_Type adc_id, uint8_t volume) -{ - if (adc_id > 2) { - return ERROR; - /*only support 3 adc*/ - } - - if (adc_id == AUPDM_ADC_0) { - BL_WR_REG(PDM0_BASE, PDM_ADC_S0, volume); - } else if (adc_id == AUPDM_ADC_1) { - BL_WR_REG(PDM0_BASE, PDM_ADC_S1, volume); - } else { - BL_WR_REG(PDM0_BASE, PDM_ADC_S2, volume); - } - - return SUCCESS; -} - -/*@} end of group AUPDMPDM_Public_Functions */ - -/*@} end of group AUPDMPDM */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c deleted file mode 100644 index 45f6c65da2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_cam.c +++ /dev/null @@ -1,979 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_cam.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_cam.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup CAM - * @{ - */ - -/** @defgroup CAM_Private_Macros - * @{ - */ - -/*@} end of group CAM_Private_Macros */ - -/** @defgroup CAM_Private_Types - * @{ - */ - -/*@} end of group CAM_Private_Types */ - -/** @defgroup CAM_Private_Variables - * @{ - */ -static const uint32_t camAddr[CAM_ID_MAX] = { DVP0_BASE, DVP1_BASE, DVP2_BASE, DVP3_BASE, - DVP4_BASE, DVP5_BASE, DVP6_BASE, DVP7_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *camIntCbfArra[CAM_ID_MAX][CAM_INT_ALL] = { { NULL } }; -#endif - -/*@} end of group CAM_Private_Variables */ - -/** @defgroup CAM_Global_Variables - * @{ - */ - -/*@} end of group CAM_Global_Variables */ - -/** @defgroup CAM_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void CAM_IntHandler(CAM_ID_Type camId); -#endif - -/*@} end of group CAM_Private_Fun_Declaration */ - -/** @defgroup CAM_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Camera interrupt common handler function - * - * @param camId: Camera ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void CAM_IntHandler(CAM_ID_Type camId) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_NORMAL_INT)) { - CAM_IntClr(camId, CAM_INT_NORMAL); - - if (camIntCbfArra[camId][CAM_INT_NORMAL] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_NORMAL](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_MEM_INT)) { - CAM_IntClr(camId, CAM_INT_MEMORY_OVERWRITE); - - if (camIntCbfArra[camId][CAM_INT_MEMORY_OVERWRITE] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_MEMORY_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FRAME_INT)) { - CAM_IntClr(camId, CAM_INT_FRAME_OVERWRITE); - - if (camIntCbfArra[camId][CAM_INT_FRAME_OVERWRITE] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_FRAME_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_FIFO_INT)) { - CAM_IntClr(camId, CAM_INT_FIFO_OVERWRITE); - - if (camIntCbfArra[camId][CAM_INT_FIFO_OVERWRITE] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_FIFO_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_HCNT_INT)) { - CAM_IntClr(camId, CAM_INT_HSYNC_CNT_ERROR); - - if (camIntCbfArra[camId][CAM_INT_HSYNC_CNT_ERROR] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_HSYNC_CNT_ERROR](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, CAM_STS_VCNT_INT)) { - CAM_IntClr(camId, CAM_INT_VSYNC_CNT_ERROR); - - if (camIntCbfArra[camId][CAM_INT_VSYNC_CNT_ERROR] != NULL) { - /* call the callback function */ - camIntCbfArra[camId][CAM_INT_VSYNC_CNT_ERROR](); - } - } -} -#endif - -/*@} end of group CAM_Private_Functions */ - -/** @defgroup CAM_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Camera module init - * - * @param camId: CAM ID type - * @param cfg: Camera configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void CAM_Init(CAM_ID_Type camId, CAM_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_SW_MODE_TYPE(cfg->swMode)); - CHECK_PARAM(IS_CAM_INPUT_PIX_WIDTH_TYPE(cfg->pixWidth)); - CHECK_PARAM(IS_CAM_OUTPUT_DROP_MODE_TYPE(cfg->dropMode)); - CHECK_PARAM(IS_CAM_FRAME_ACTIVE_POL(cfg->framePol)); - CHECK_PARAM(IS_CAM_LINE_ACTIVE_POL(cfg->linePol)); - CHECK_PARAM(IS_CAM_BURST_TYPE(cfg->burstType)); - CHECK_PARAM(IS_CAM_SENSOR_MODE_TYPE(cfg->camSensorMode)); - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_CAM); - - /* Set camera configuration */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_SW_MODE, cfg->swMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_DATA_MODE, cfg->pixWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAM_VLD_POL, cfg->framePol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_LINE_VLD_POL, cfg->linePol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_XLEN, cfg->burstType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_MODE, cfg->camSensorMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_WAIT_CYCLE, cfg->waitCount); - - switch (cfg->dropMode) { - case CAM_DROP_NONE: - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - break; - - case CAM_DROP_ODD_ROW_ODD_PIXEL: - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_POL); - break; - - case CAM_DROP_ODD_ROW_EVEN_PIXEL: - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_POL); - break; - - case CAM_DROP_ALL_ODD_PIXEL: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DROP_EVEN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - break; - - case CAM_DROP_ALL_EVEN_PIXEL: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DROP_EVEN); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_V_SUBSAMPLE_EN); - break; - - default: - break; - } - - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); - - /* Set frame count to issue interrupt at sw mode */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_CNT_TRGR_INT, cfg->swIntCnt); - BL_WR_REG(CAMx, CAM_DVP_STATUS_AND_ERROR, tmpVal); - - /* Set camera memory start address, memory brust size and frame byte size */ - BL_WR_REG(CAMx, CAM_DVP2AXI_ADDR_START, cfg->memStart & 0xFFFFFFF0); - - switch (cfg->burstType) { - case CAM_BURST_TYPE_SINGLE: - tmpVal = cfg->memSize / 8; - break; - - case CAM_BURST_TYPE_INCR4: - tmpVal = cfg->memSize / 32; - break; - - case CAM_BURST_TYPE_INCR8: - tmpVal = cfg->memSize / 64; - break; - - case CAM_BURST_TYPE_INCR16: - tmpVal = cfg->memSize / 128; - break; - - case CAM_BURST_TYPE_INCR32: - tmpVal = cfg->memSize / 256; - break; - - case CAM_BURST_TYPE_INCR64: - tmpVal = cfg->memSize / 512; - break; - - default: - tmpVal = 0; - break; - } - - BL_WR_REG(CAMx, CAM_DVP2AXI_MEM_BCNT, tmpVal); - - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_BCNT, cfg->frameSize); - - /* Clear interrupt */ - BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, 0xFFFF0); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DVP2BUS_INT0_IRQn, CAM0_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT1_IRQn, CAM1_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT2_IRQn, CAM2_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT3_IRQn, CAM3_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT4_IRQn, CAM4_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT5_IRQn, CAM5_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT6_IRQn, CAM6_IRQHandler); - Interrupt_Handler_Register(DVP2BUS_INT7_IRQn, CAM7_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Deinit camera module - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Deinit(CAM_ID_Type camId) -{ - switch(camId){ - case CAM0_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSA); - break; - case CAM1_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSB); - break; - case CAM2_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSC); - break; - case CAM3_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSD); - break; - case CAM4_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSE); - break; - case CAM5_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSF); - break; - case CAM6_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSG); - break; - case CAM7_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DVP2BUSH); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Enable camera module - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Enable(CAM_ID_Type camId) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - /* Enable camera module */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable camera module - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Disable(CAM_ID_Type camId) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - /* Disable camera module */ - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_DVP_ENABLE); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera clock gate function - * - * @param camId: CAM ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void CAM_Clock_Gate(CAM_ID_Type camId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_PIX_CLK_CG, enable); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera hsync crop function - * - * @param camId: CAM ID type - * @param start: Valid hsync start count - * @param end: Valid hsync end count - * - * @return None - * -*******************************************************************************/ -void CAM_Hsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - BL_WR_REG(CAMx, CAM_DVP2AXI_HSYNC_CROP, (start << 16) + end); -} - -/****************************************************************************/ /** - * @brief Camera vsync crop function - * - * @param camId: CAM ID type - * @param start: Valid vsync start count - * @param end: Valid vsync end count - * - * @return None - * -*******************************************************************************/ -void CAM_Vsync_Crop(CAM_ID_Type camId, uint16_t start, uint16_t end) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - BL_WR_REG(CAMx, CAM_DVP2AXI_VSYNC_CROP, (start << 16) + end); -} - -/****************************************************************************/ /** - * @brief Camera set total valid pix count in a line function - * - * @param camId: CAM ID type - * @param count: Count value - * - * @return None - * -*******************************************************************************/ -void CAM_Set_Hsync_Total_Count(CAM_ID_Type camId, uint16_t count) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAM_EXM); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_HCNT, count); - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAM_EXM, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera set total valid line count in a frame function - * - * @param camId: CAM ID type - * @param count: Count value - * - * @return None - * -*******************************************************************************/ -void CAM_Set_Vsync_Total_Count(CAM_ID_Type camId, uint16_t count) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAM_EXM); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_TOTAL_VCNT, count); - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAM_EXM, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get one camera frame - * - * @param camId: CAM ID type - * @param info: Camera frame infomation pointer - * - * @return None - * -*******************************************************************************/ -void CAM_Get_Frame_Info(CAM_ID_Type camId, CAM_Frame_Info *info) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - - info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, CAM_FRAME_VALID_CNT); - info->curFrameId = BL_GET_REG_BITS_VAL(BL_RD_REG(CAMx, CAM_FRAME_ID_STS01), CAM_FRAME_ID_0); - info->curFrameAddr = BL_RD_REG(CAMx, CAM_FRAME_START_ADDR0); - info->curFrameBytes = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAME_BCNT); - info->status = tmpVal; -} - -/****************************************************************************/ /** - * @brief Get available count of frames - * - * @param camId: CAM ID type - * - * @return Frames count - * -*******************************************************************************/ -uint8_t CAM_Get_Frame_Count(CAM_ID_Type camId) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR), CAM_FRAME_VALID_CNT); -} - -/****************************************************************************/ /** - * @brief Pop one camera frame - * - * @param camId: CAM ID type - * - * @return None - * -*******************************************************************************/ -void CAM_Pop_Frame(CAM_ID_Type camId) -{ - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - /* Pop one frame */ - BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, 1); -} - -/****************************************************************************/ /** - * @brief CAMERA Enable Disable Interrupt - * - * @param camId: CAM ID type - * @param intType: CAMERA Interrupt Type - * @param intMask: Enable or Disable - * - * @return None - * -*******************************************************************************/ -void CAM_IntMask(CAM_ID_Type camId, CAM_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_STATUS_AND_ERROR); - - switch (intType) { - case CAM_INT_NORMAL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_EN); - } - - break; - - case CAM_INT_MEMORY_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_MEM_EN); - } - - break; - - case CAM_INT_FRAME_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FRAME_EN); - } - - break; - - case CAM_INT_FIFO_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_FIFO_EN); - } - - break; - - case CAM_INT_VSYNC_CNT_ERROR: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_VCNT_EN); - } - - break; - - case CAM_INT_HSYNC_CNT_ERROR: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, CAM_REG_INT_HCNT_EN); - } - - break; - - case CAM_INT_ALL: - if (intMask == UNMASK) { - /* Enable all interrupt */ - tmpVal |= 0xFC0; - } else { - /* Disable all interrupt */ - tmpVal &= 0xFFFFF03F; - } - - break; - - default: - break; - } - - BL_WR_REG(CAMx, CAM_DVP_STATUS_AND_ERROR, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA Interrupt Clear - * - * @param camId: CAM ID type - * @param intType: CAMERA Interrupt Type - * - * @return None - * -*******************************************************************************/ -void CAM_IntClr(CAM_ID_Type camId, CAM_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP_FRAME_FIFO_POP); - - switch (intType) { - case CAM_INT_NORMAL: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_NORMAL_CLR); - break; - - case CAM_INT_MEMORY_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_MEM_CLR); - break; - - case CAM_INT_FRAME_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FRAME_CLR); - break; - - case CAM_INT_FIFO_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_FIFO_CLR); - break; - - case CAM_INT_VSYNC_CNT_ERROR: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_VCNT_CLR); - break; - - case CAM_INT_HSYNC_CNT_ERROR: - tmpVal = BL_SET_REG_BIT(tmpVal, CAM_REG_INT_HCNT_CLR); - break; - - case CAM_INT_ALL: - tmpVal = 0xFFFF0; - - default: - break; - } - - BL_WR_REG(CAMx, CAM_DVP_FRAME_FIFO_POP, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install camera interrupt callback function - * - * @param camId: CAM ID type - * @param intType: CAMERA interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM_Int_Callback_Install(CAM_ID_Type camId, CAM_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_INT_TYPE(intType)); - - camIntCbfArra[camId][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief CAMERA input 8-bit mode lower/upper byte select function - * - * @param camId: CAM ID type - * @param byteType: Byte type - * - * @return None - * -*******************************************************************************/ -void CAM_8_Bit_Byte_Select(CAM_ID_Type camId, CAM_8_Bit_Byte_Type byteType) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_8_BIT_BYTE_TYPE(byteType)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_DVP_DATA_BSEL, byteType); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA input 16-bit mode RGB order select function - * - * @param camId: CAM ID type - * @param rgbType: RGB order type - * - * @return None - * -*******************************************************************************/ -void CAM_16_Bit_RGB_order(CAM_ID_Type camId, CAM_16_Bit_RGB_Type rgbType) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_CAM_16_BIT_RGB_TYPE(rgbType)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FORMAT_565, rgbType); - BL_WR_REG(CAMx, CAM_DVP2AXI_MISC, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA input 32-bit mode alpha value set function - * - * @param camId: CAM ID type - * @param alpha: Alpha value - * - * @return None - * -*******************************************************************************/ -void CAM_32_Bit_Alpha_Set(CAM_ID_Type camId, uint8_t alpha) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_MISC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_ALPHA, alpha); - BL_WR_REG(CAMx, CAM_DVP2AXI_MISC, tmpVal); -} - -/****************************************************************************/ /** - * @brief CAMERA set frame period and bitwise frame valid in period function - * - * @param camId: CAM ID type - * @param period: Frame period count - * @param validBit: Bitwise frame valid in period - * - * @return None - * -*******************************************************************************/ -void CAM_Set_Frame_Valid_Period(CAM_ID_Type camId, uint8_t period, uint32_t validBit) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_FRAME_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_FRAME_PERIOD, period); - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_PERIOD, tmpVal); - - BL_WR_REG(CAMx, CAM_DVP2AXI_FRAME_VLD, validBit); -} - -/****************************************************************************/ /** - * @brief Enable or disable function that covers first frame memory everytime in hardware mode - * - * @param camId: CAM ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void CAM_HW_Cover_First_Frame_Everytime(CAM_ID_Type camId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t CAMx = camAddr[camId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(camId)); - - tmpVal = BL_RD_REG(CAMx, CAM_DVP2AXI_CONFIGUE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAM_REG_HW_MODE_FWRAP, enable); - BL_WR_REG(CAMx, CAM_DVP2AXI_CONFIGUE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Camera 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM0_IRQHandler(void) -{ - CAM_IntHandler(CAM0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM1_IRQHandler(void) -{ - CAM_IntHandler(CAM1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM2_IRQHandler(void) -{ - CAM_IntHandler(CAM2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM3_IRQHandler(void) -{ - CAM_IntHandler(CAM3_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 4 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM4_IRQHandler(void) -{ - CAM_IntHandler(CAM4_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 5 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM5_IRQHandler(void) -{ - CAM_IntHandler(CAM5_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 6 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM6_IRQHandler(void) -{ - CAM_IntHandler(CAM6_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Camera 7 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void CAM7_IRQHandler(void) -{ - CAM_IntHandler(CAM7_ID); -} -#endif - -/*@} end of group CAM_Public_Functions */ - -/*@} end of group CAM */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c deleted file mode 100644 index 9690d01f11..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_can.c +++ /dev/null @@ -1,671 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_can.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_glb.h" -#include "bl808_can.h" -#include "bflb_platform.h" - -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type * canIntCbfArra[CAN_INT_ALL] = { NULL }; -static void CAN_IntHandler(void); -static void CAN_IRQHandler(void); -#endif - -void CAN_Init(void) -{ - uint32_t tmpVal; - - /* Enable CAN clock witch share with UART2 */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2); - - /* Enable UART clock*/ - tmpVal=BL_RD_REG(GLB_BASE,GLB_UART_CFG0); - tmpVal=BL_SET_REG_BIT(tmpVal,GLB_UART_CLK_EN); - BL_WR_REG(GLB_BASE,GLB_UART_CFG0,tmpVal); - - /* UART2 and CAN can not work together */ - GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_CAN_FD); - - /* Need to enter reset mode before operating */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - /* Force using PeliCAN not BasicCAN */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_CLOCK_DIVIDER); - tmpVal = BL_SET_REG_BIT(tmpVal, CAN_MODE); - BL_WR_REG(CAN_BASE, CAN_CLOCK_DIVIDER, tmpVal); - - /* Disable all interrupts */ - BL_WR_REG(CAN_BASE, CAN_INTERRUPT_ENABLE, 0); - - /* Set clock and sample point */ - CAN_Clock_Div_Set(0); - CAN_Synchronization_Jump_Width_Set(3); - CAN_Sample_Parameter_Set(1, 8, 5); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(UART2_IRQn, CAN_IRQHandler); -#endif -} - -void CAN_Mode_Set(CAN_MODE_Type type, CAN_MODE_VALUE_Type value) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_MODE_TYPE(type)); - CHECK_PARAM(IS_CAN_MODE_VALUE_TYPE(value)); - - /* Set mode value */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_MODE); - tmpVal &= ~(1 << type); - tmpVal |= (value << type); - - /* Write back */ - BL_WR_REG(CAN_BASE, CAN_MODE, tmpVal); -} - -CAN_MODE_VALUE_Type CAN_Mode_Get(CAN_MODE_Type type) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_MODE_TYPE(type)); - - tmpVal = BL_RD_REG(CAN_BASE, CAN_MODE); - tmpVal &= (1 << type); - tmpVal >>= type; - return (CAN_MODE_VALUE_Type)tmpVal; -} - -void CAN_Int_Enable(CAN_INT_Type intType, BL_Fun_Type enable) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(CAN_BASE, CAN_INTERRUPT_ENABLE); - /* Enable or Disable certain or all interrupt */ - if(CAN_INT_ALL == intType){ - if(ENABLE == enable){ - tmpVal |= 0xFF; - }else{ - tmpVal &= 0; - } - }else{ - if(ENABLE == enable){ - tmpVal |= 1<>= type; - return (CAN_STATUS_VALUE_Type)tmpVal; -} - -uint8_t CAN_Arbitration_Lost_Position_Get(void) -{ - uint8_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_ARB_LOST_CAPTURE); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, CAN_ALC4_0); - return tmpVal; -} - -void CAN_Error_Get(CAN_ERROR_Type *const type) -{ - uint8_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(type)); - - tmpVal = BL_RD_REG(CAN_BASE, CAN_ERROR_CODE_CAPTURE); - type->code = BL_GET_REG_BITS_VAL(tmpVal, CAN_ERR_CODE); - type->dir = BL_GET_REG_BITS_VAL(tmpVal, CAN_DIR); - type->location = BL_GET_REG_BITS_VAL(tmpVal, CAN_SEGMENT4_0); -} - -BL_Err_Type CAN_Error_Warning_Limit_Set(uint8_t limit) -{ - if(CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - BL_WR_REG(CAN_BASE, CAN_ERROR_WARNING_LIMIT, limit); - return SUCCESS; -} - -uint8_t CAN_Error_Warning_Limit_Get(void) -{ - return BL_RD_REG(CAN_BASE, CAN_ERROR_WARNING_LIMIT); -} - -uint8_t CAN_Error_Rx_Counter_Get(void) -{ - return BL_RD_REG(CAN_BASE, CAN_RX_ERR_COUNT); -} - -uint8_t CAN_Error_Tx_Counter_Get(void) -{ - return BL_RD_REG(CAN_BASE, CAN_TX_ERR_COUNT); -} - -BL_Err_Type CAN_Transmit(const CAN_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->dataAddr)); - CHECK_PARAM(IS_CAN_FRAME_TYPE(cfg->frameType)); - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->frameFormat)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(CAN_STATUS_TRANSMIT_BUFFER_LOCKED == CAN_Status_Get(CAN_STATUS_TRANSMIT_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= CAN_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Config information register */ - tmpVal = cfg->dataLen; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_INF_FF, cfg->frameFormat); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_INF_RTR, cfg->frameType); - BL_WR_REG(CAN_BASE, CAN_INFORMATION, tmpVal); - - tmpVal = cfg->id; - /* Transmit format with 11 bits ID, SFF */ - if(CAN_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Config identifier registers */ - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_1, (tmpVal >> 3) & 0xFF); - tmpVal <<= 5; - tmpVal |= (cfg->frameType << 4); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_2, tmpVal & 0xFF); - /* Config SFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_SFF_DATA_1_OFFSET); - } - /* Transmit format with 29 bits ID, EFF */ - else - { - /* Config identifier registers */ - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_1, (tmpVal >> 21) & 0xFF); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_2, (tmpVal >> 13) & 0xFF); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_3, (tmpVal >> 5) & 0xFF); - tmpVal <<= 3; - tmpVal |= (cfg->frameType << 2); - BL_WR_REG(CAN_BASE, CAN_IDENTIFIER_4, tmpVal & 0xFF); - /* Config EFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_EFF_DATA_1_OFFSET); - } - /* Move data from user buff to registers */ - for (i = 0; i < cfg->dataLen; i++) - { - *(pData + i) = (uint32_t)(*(cfg->dataAddr + i)); - } - - /* Trig a request for transmit */ - if(CAN_MODE_VALUE_RESET == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - else if(CAN_MODE_VALUE_LISTEN_ONLY == CAN_Mode_Get(CAN_MODE_TYPE_LISTEN_ONLY)) - { - return ERROR; - } - else if(CAN_MODE_VALUE_SELF_TSET == CAN_Mode_Get(CAN_MODE_TYPE_SELF_TSET)) - { - CAN_Cmd_Request_Self_Reception(); - } - else - { - CAN_Cmd_Request_Transmit(); - } - - return SUCCESS; -} - -BL_Err_Type CAN_Receive(CAN_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - uint32_t id; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cfg->dataAddr)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(CAN_STATUS_RECEIVE_BUFFER_EMPTY == CAN_Status_Get(CAN_STATUS_RECEIVE_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= CAN_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Read information register */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_INFORMATION); - cfg->frameFormat = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_FF); - cfg->frameType = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_RTR); - cfg->dataLen = BL_GET_REG_BITS_VAL(tmpVal, CAN_INF_DLC); - - /* Receive with 11 bits ID */ - if(CAN_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 3); - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_2); - id |= (tmpVal & 0xFF) >> 5; - /* Config SFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_SFF_DATA_1_OFFSET); - } - /* Receive with 29 bits ID */ - else - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 21); - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_2); - id |= (tmpVal & 0xFF) << 13; - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_3); - id |= (tmpVal & 0xFF) << 5; - tmpVal = BL_RD_REG(CAN_BASE, CAN_IDENTIFIER_4); - id |= (tmpVal & 0xFF) >> 3; - /* Config EFF data registers start address */ - pData = (uint32_t *)(CAN_BASE + CAN_EFF_DATA_1_OFFSET); - } - cfg->id = id; - - /* Move data from registers to user buff */ - for (i = 0; i < cfg->dataLen; i++) - { - *(cfg->dataAddr + i) = (uint8_t)(*(pData + i) & 0xFF); - } - - CAN_Cmd_Release_Recv_Buff(); - - return SUCCESS; -} - -uint8_t CAN_Receive_Buff_Frame_Count_Get(void) -{ - volatile uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_RX_MESSAGE_COUNT); - return (uint8_t)(tmpVal & 0xFF); -} - -BL_Err_Type CAN_Clock_Div_Set(uint8_t div) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_BAUD_RATE_PRESCALER, div); - BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t CAN_Clock_Div_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_BAUD_RATE_PRESCALER); -} - -BL_Err_Type CAN_Synchronization_Jump_Width_Set(uint8_t width) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_SYNC_JUMP_WIDTH, width); - BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t CAN_Synchronization_Jump_Width_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_SYNC_JUMP_WIDTH); -} - -BL_Err_Type CAN_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail) -{ - uint32_t tmpVal = 0; - - /* Must be operated in reset mode */ - if (CAN_MODE_VALUE_NORMAL == CAN_Mode_Get(CAN_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_1, head); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_2, tail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CAN_SAMPLING, num); - BL_WR_REG(CAN_BASE, CAN_BUS_TIMING_1, tmpVal & 0xFF); - - return SUCCESS; -} - -void CAN_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_BUS_TIMING_1); - *head = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_1); - *tail = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_TIME_SEGMENT_2); - *num = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, CAN_SAMPLING); -} - -void CAN_Filter_Set(const CAN_FILTER_CFG_Type *cfg) -{ - uint8_t tmpVal[8] = {0}; //tmpVal[0~3] for match, tmpVal[4~7] for mask - - /* Config filter must be in reset mode */ - CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET); - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - - /* Single filter mode */ - if (CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE == cfg->filterMode) - { - CAN_Mode_Set(CAN_MODE_TYPE_ACCEPTANCE_FILTER, CAN_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE); - /* Filter: ID10~0 + RTR + Data1 + Data2 */ - if (CAN_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[2] = cfg->matchData1; - tmpVal[3] = cfg->matchData2; - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (uint8_t)0x0F;//0b1111 for unused bit 3:0 - tmpVal[6] = cfg->maskData1; - tmpVal[7] = cfg->maskData2; - } - /* Filter: ID28~0 + RTR */ - else if(CAN_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId1 >> 5); - tmpVal[3] = (uint8_t)(cfg->matchId1 << 3); - tmpVal[3] |= (uint8_t)(cfg->matchRtr1 << 2); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId1 >> 5); - tmpVal[7] = (uint8_t)(cfg->maskId1 << 3); - tmpVal[7] |= (uint8_t)(cfg->maskRtr1 << 2); - tmpVal[7] |= (uint8_t)0x03;//0b11 for unused bit 1:0 - } - } - /* Dual filter mode */ - else if (CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL == cfg->filterMode) - { - CAN_Mode_Set(CAN_MODE_TYPE_ACCEPTANCE_FILTER, CAN_MODE_VALUE_ACCEPTANCE_FILTER_DUAL); - /* Filter1: ID10~0 + RTR + Data1 */ - /* Filter2: ID10~0 + RTR */ - if (CAN_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[1] |= (cfg->matchData1 >> 4); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 3); - tmpVal[3] = (uint8_t)(cfg->matchId2 << 5); - tmpVal[3] |= (uint8_t)(cfg->matchRtr2 << 4); - tmpVal[3] |= (cfg->matchData1 & 0xF); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (cfg->maskData1 >> 4); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 3); - tmpVal[7] = (uint8_t)(cfg->maskId2 << 5); - tmpVal[7] |= (uint8_t)(cfg->maskRtr2 << 4); - tmpVal[7] |= (cfg->maskData1 & 0xF); - } - /* Filter1: ID28~13 */ - /* Filter2: ID28~13 */ - else if (CAN_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 21); - tmpVal[3] = (uint8_t)(cfg->matchId2 >> 13); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 21); - tmpVal[7] = (uint8_t)(cfg->maskId2 >> 13); - } - } - /* Write configuration to Registers*/ - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_0, (uint32_t)tmpVal[0]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_1, (uint32_t)tmpVal[1]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_2, (uint32_t)tmpVal[2]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_3, (uint32_t)tmpVal[3]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_0, (uint32_t)tmpVal[4]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_1, (uint32_t)tmpVal[5]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_2, (uint32_t)tmpVal[6]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_3, (uint32_t)tmpVal[7]); - - /* Recovery reset mode value */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset); -} - -void CAN_Filter_Register_Set(CAN_FILTER_REGISTER_Type reg, uint8_t value) -{ - /* Config filter must be in reset mode */ - CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET); - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - /* Write configuration to Register*/ - BL_WR_WORD(CAN_BASE + CAN_FILTER_ACCEPTANCE_0_OFFSET + 4 * reg, value); - - /* Recovery reset mode value */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset); -} - -void CAN_Filter_Registers_Set(uint8_t *valueArr) -{ - /* Config filter must be in reset mode */ - CAN_MODE_VALUE_Type modeReset = CAN_Mode_Get(CAN_MODE_TYPE_RESET); - CAN_Mode_Set(CAN_MODE_TYPE_RESET, CAN_MODE_VALUE_RESET); - - /* Write configuration to Registers*/ - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_0, (uint32_t)valueArr[0]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_1, (uint32_t)valueArr[1]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_2, (uint32_t)valueArr[2]); - BL_WR_REG(CAN_BASE, CAN_FILTER_ACCEPTANCE_3, (uint32_t)valueArr[3]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_0, (uint32_t)valueArr[4]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_1, (uint32_t)valueArr[5]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_2, (uint32_t)valueArr[6]); - BL_WR_REG(CAN_BASE, CAN_FILTER_Mask_3, (uint32_t)valueArr[7]); - - /* Recovery reset mode value */ - CAN_Mode_Set(CAN_MODE_TYPE_RESET, modeReset); -} - -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type CAN_Int_Callback_Install(CAN_INT_Type intType,intCallback_Type* cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_CAN_FRAME_FORMAT_TYPE(cbFun)); - CHECK_PARAM(IS_CAN_INT_TYPE(intType)); - - canIntCbfArra[intType] = cbFun; - - return SUCCESS; -} - -static void CAN_IntHandler(void) -{ - uint32_t tmpVal = 0; - uint32_t i = 0; - - tmpVal = BL_RD_REG(CAN_BASE, CAN_INTERRUPT); - - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dac.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DAC - * @{ - */ - -/** @defgroup DAC_Private_Macros - * @{ - */ -#define GPIP_CLK_SET_DUMMY_WAIT \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - } - -/*@} end of group DAC_Private_Macros */ - -/** @defgroup DAC_Private_Types - * @{ - */ - -/*@} end of group DAC_Private_Types */ - -/** @defgroup DAC_Private_Variables - * @{ - */ - -/*@} end of group DAC_Private_Variables */ - -/** @defgroup DAC_Global_Variables - * @{ - */ - -/*@} end of group DAC_Global_Variables */ - -/** @defgroup DAC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DAC_Private_Fun_Declaration */ - -/** @defgroup DAC_Private_Functions - * @{ - */ - -/*@} end of group DAC_Private_Functions */ - -/** @defgroup DAC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DAC initialization - * - * @param cfg: DAC configuration pointer - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Init(GLB_DAC_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); - - /* Set DAC config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); - - if (ENABLE == cfg->resetChanA) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - if (ENABLE == cfg->resetChanB) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - /* Clear reset */ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel A initialization - * - * @param cfg: DAC channel configuration pointer - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanA_Config(GLB_DAC_Chan_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); - - /* Set channel A config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_OUTMUX, cfg->outMux); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanEn); - - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel B initialization - * - * @param cfg: DAC channel configuration pointer - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanB_Config(GLB_DAC_Chan_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_GLB_DAC_CHAN_TYPE(cfg->outMux)); - - /* Set channel A config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_OUTMUX, cfg->outMux); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanEn); - - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DAC channel B source - * - * @param src: DAC channel B source selection type - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_ChanB_SRC_SEL(GPIP_DAC_ChanB_SRC_Type src) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(src)); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DAC channel A source - * - * @param src: DAC channel A source selection type - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_ChanA_SRC_SEL(GPIP_DAC_ChanA_SRC_Type src) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(src)); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable DAC channel B - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanB_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC channel B - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanB_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable DAC channel A - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanA_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC channel A - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_ChanA_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DAC DMA TX format - * - * @param fmt: DAC DMA TX format selection type - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_DMA_TX_FORMAT_SEL(GPIP_DAC_DMA_TX_FORMAT_Type fmt) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(fmt)); - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, fmt); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable DAC DMA TX - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_DMA_TX_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC DMA TX - * - * @param None - * - * @return None - * -*******************************************************************************/ -void GPIP_Set_DAC_DMA_TX_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, GPIP_GPDAC_DMA_TX_EN); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable DAC DMA TX - * - * @param data: The data to be send - * - * @return None - * -*******************************************************************************/ -void GPIP_DAC_DMA_WriteData(uint32_t data) -{ - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_WDATA, data); -} - -/****************************************************************************/ /** - * @brief AON and GPIP DAC config - * - * @param cfg: AON and GPIP DAC configuration - * - * @return config success or not - * -*******************************************************************************/ -BL_Err_Type GLB_GPIP_DAC_Init(GLB_GPIP_DAC_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DAC_REF_SEL_TYPE(cfg->refSel)); - CHECK_PARAM(IS_GPIP_DAC_MOD_TYPE(cfg->div)); - CHECK_PARAM(IS_GPIP_DAC_DMA_TX_FORMAT_TYPE(cfg->dmaFmt)); - - /* AON Set DAC config */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_REF_SEL, cfg->refSel); - - if (ENABLE == cfg->resetChanA) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - if (ENABLE == cfg->resetChanB) { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - __NOP(); - __NOP(); - __NOP(); - __NOP(); - } - - /* AON Clear reset */ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACA_RSTN_ANA); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPDACB_RSTN_ANA); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG0, tmpVal); - - /* GPIP Set DAC config */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_MODE, cfg->div); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP Set DMA config */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_TX_EN, cfg->dmaEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_DMA_FORMAT, cfg->dmaFmt); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_DMA_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AON and GPIP DAC channel A config - * - * @param cfg: AON and GPIP DAC channel A configuration - * - * @return None - * -*******************************************************************************/ -void GLB_GPIP_DAC_Set_ChanA_Config(GLB_GPIP_DAC_ChanA_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANA_SRC_TYPE(cfg->src)); - - /* GPIP select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_A_SEL, cfg->src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable or disable channel */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* AON enable or disable channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOA_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_EN, cfg->chanCovtEn); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG1, tmpVal); -} - -/****************************************************************************/ /** - * @brief AON and GPIP DAC channel B config - * - * @param cfg: AON and GPIP DAC channel B configuration - * - * @return None - * -*******************************************************************************/ -void GLB_GPIP_DAC_Set_ChanB_Config(GLB_GPIP_DAC_ChanB_Cfg_Type *cfg) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GPIP_DAC_CHANB_SRC_TYPE(cfg->src)); - - /* GPIP select source */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_CH_B_SEL, cfg->src); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* GPIP enable or disable channel */ - tmpVal = BL_RD_REG(GPIP_BASE, GPIP_GPDAC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GPIP_GPDAC_EN, cfg->chanEn); - BL_WR_REG(GPIP_BASE, GPIP_GPDAC_CONFIG, tmpVal); - - /* AON enable or disable channel */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_IOB_EN, cfg->outputEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_EN, cfg->chanCovtEn); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG2, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel A set value - * - * @param val: DAC value - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanA_Value(uint16_t val) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_A_DATA, val); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG3, tmpVal); -} - -/****************************************************************************/ /** - * @brief DAC channel B set value - * - * @param val: DAC value - * - * @return None - * -*******************************************************************************/ -void GLB_DAC_Set_ChanB_Value(uint16_t val) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DAC_CFG3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPDAC_B_DATA, val); - tmpVal = BL_WR_REG(GLB_BASE, GLB_DAC_CFG3, tmpVal); -} - -/*@} end of group DAC_Public_Functions */ - -/*@} end of group DAC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c deleted file mode 100644 index bde60e85a7..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dbi.c +++ /dev/null @@ -1,802 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dbi.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dbi.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DBI - * @{ - */ - -/** @defgroup DBI_Private_Macros - * @{ - */ - -/*@} end of group DBI_Private_Macros */ - -/** @defgroup DBI_Private_Types - * @{ - */ - -/*@} end of group DBI_Private_Types */ - -/** @defgroup DBI_Private_Variables - * @{ - */ - -/** - * @brief DBI interrupt callback function address array - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *DBIIntCbfArra[DBI_INT_ALL] = { - NULL -}; -#endif - -/*@} end of group DBI_Private_Variables */ - -/** @defgroup DBI_Global_Variables - * @{ - */ - -/*@} end of group DBI_Global_Variables */ - -/** @defgroup DBI_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DBI_Private_Fun_Declaration */ - -/** @defgroup DBI_Private_Functions - * @{ - */ - -/*@} end of group DBI_Private_Functions */ - -/** @defgroup DBI_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DBI interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DBI_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - - /* DBI transfer end interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, DBI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_END_MASK)) { - BL_WR_REG(DBI_BASE, DBI_INT_STS, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_END_CLR)); - - if (DBIIntCbfArra[DBI_INT_END] != NULL) { - DBIIntCbfArra[DBI_INT_END](); - } - } - - /* DBI tx fifo ready interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, DBI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_TXF_MASK)) { - if (DBIIntCbfArra[DBI_INT_TX_FIFO_REQ] != NULL) { - DBIIntCbfArra[DBI_INT_TX_FIFO_REQ](); - } - } - - /* DBI tx fifo ready interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, DBI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, DBI_CR_DBI_FER_MASK)) { - if (DBIIntCbfArra[DBI_INT_FIFO_ERR] != NULL) { - DBIIntCbfArra[DBI_INT_FIFO_ERR](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief DBI init - * - * @param dbiCfg: DBI configuration - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DBI_Init(DBI_CFG_Type *dbiCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_MODE_TYPE(dbiCfg->mode)); - CHECK_PARAM(IS_DBI_PIXEL_FORMAT_TYPE(dbiCfg->pixelFormat)); - CHECK_PARAM(IS_DBI_FIFO_FORMAT_TYPE(dbiCfg->fifoFormat)); - CHECK_PARAM(IS_DBI_SCL_CLK_PHASE_TYPE(dbiCfg->clkPhase)); - CHECK_PARAM(IS_DBI_SCL_CLK_POLARITY_TYPE(dbiCfg->clkPolarity)); - - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - - /* Select DBI type B or C */ - if (dbiCfg->mode == DBI_TYPE_B) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_SEL); - } else if (dbiCfg->mode == DBI_TYPE_C_3_WIRE) { - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_SEL); - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_TC_3W_MODE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_TC_3W_MODE); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CONT_EN, dbiCfg->continueEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DMY_EN, dbiCfg->dummyEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DMY_CNT, dbiCfg->dummyCnt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_SCL_PH, dbiCfg->clkPhase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_SCL_POL, dbiCfg->clkPolarity); - - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); - - /* Set data period */ - DBI_SetPeriod(&(dbiCfg->period)); - - /* Set pixel format */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_PIX_CNT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PIX_FORMAT, dbiCfg->pixelFormat); - BL_WR_REG(DBI_BASE, DBI_PIX_CNT, tmpVal); - - /* Set fifo format */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_FIFO_FORMAT, dbiCfg->fifoFormat); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DBI_IRQn, DBI_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DBI command and data configuration - * - * @param cdCfg: Pointer of DBI CD configure type - * - * @return None - * -*******************************************************************************/ -void DBI_CDConfig(DBI_CD_CFG_Type *cdCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_DATA_TYPE(cdCfg->dataType)); - CHECK_PARAM(IS_DBI_DATA_DIRECTION_TYPE(cdCfg->dataDir)); - - /* Set command and data comfiguration */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD_EN, cdCfg->commandEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD, cdCfg->command); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_EN, cdCfg->dataEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_TP, cdCfg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_WR, cdCfg->dataDir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_BC, cdCfg->dataCnt); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); - BL_WR_REG(DBI_BASE, DBI_WDATA, cdCfg->data); -} - -/****************************************************************************/ /** - * @brief DBI enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - BL_WR_REG(DBI_BASE, DBI_CONFIG, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_EN)); -} - -/****************************************************************************/ /** - * @brief DBI disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - BL_WR_REG(DBI_BASE, DBI_CONFIG, BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_EN)); -} - -/****************************************************************************/ /** - * @brief DBI enable - * - * @param period: DBI period configuration - * - * @return None - * -*******************************************************************************/ -void DBI_SetPeriod(DBI_Period_CFG_Type *period) -{ - uint32_t tmpVal; - - /* Set data period */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_PRD); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_S, period->startLen); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_D_PH_0, period->dataPhase0Len); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_D_PH_1, period->dataPhase1Len); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_PRD_I, period->intervalLen); - - BL_WR_REG(DBI_BASE, DBI_PRD, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set Command - * - * @param Command: start Command (frist byte) - * @return None - * -*******************************************************************************/ -void DBI_SetCommand(uint8_t Command ) -{ - uint32_t tmpVal; - - /* Set command */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD, Command); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set Command and Data enable signal - * - * @param CommandEn: DISABLE:No command phase, ENABLE:Command will be sent - * @param dataEn: DISABLE:No data phase, ENABLE:data will be sent - * @return None - * -*******************************************************************************/ -void DBI_SetPhaseState(BL_Fun_Type commandEn, BL_Fun_Type dataEn) -{ - uint32_t tmpVal; - - /* Set command */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_CMD_EN, commandEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_EN, dataEn); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set Data type and count, Automatically change data phase settings - * - * @param datatype: Data type select - * @param dataCount: count of data (Not the size of the data) - * normal data: max 4 - * @return None - * -*******************************************************************************/ -void DBI_SetDataTypeAndCount(DBI_Data_Type dataType, uint32_t dataCount) -{ - uint32_t tmpVal, tmpVal2; - - /* Set dbi config */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - /* Set data type */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_TP, dataType); - - if(!dataCount){ - /* No data phase */ - tmpVal = BL_CLR_REG_BIT(tmpVal, DBI_CR_DBI_DAT_EN); - }else{ - /* data will be sent */ - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_DAT_EN); - - if(dataType == DBI_DATA_NORMAL){ - if(dataCount > 4){ - dataCount = 4; - } - /* data byte count of normal-data */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_BC, dataCount-1); - }else{ - /* pixel count of pixel-data */ - tmpVal2 = BL_RD_REG(DBI_BASE, DBI_PIX_CNT); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, DBI_CR_DBI_PIX_CNT, dataCount-1); - BL_WR_REG(DBI_BASE, DBI_PIX_CNT, tmpVal2); - } - } - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI set normal data direction (It only works in normal data) - * - * @param dataDir: write or read - * @return None - * -*******************************************************************************/ -void DBI_SetNormalDataDir(DBI_Data_Direction_Type dataDir) -{ - uint32_t tmpVal; - /* Set dbi config */ - tmpVal = BL_RD_REG(DBI_BASE, DBI_CONFIG); - /* set normal data direction */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_DAT_WR, dataDir); - BL_WR_REG(DBI_BASE, DBI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DBI Read Norml-Data from rdata-register - * - * @param dataSize: size of data (max 4-byte) - * @param dataBuff: buff of data - * @return None - * -*******************************************************************************/ -void DBI_ReadNormlData(uint8_t dataSize, uint8_t *dataBuff) -{ - if(dataSize > 4){ - dataSize = 4; - } - - /* get receive data from registers*/ - uint32_t para_data = 0; - para_data = BL_RD_REG(DBI_BASE, DBI_RDATA); - - /* copy to buff */ - memcpy(dataBuff, ¶_data, dataSize); -} - -/****************************************************************************/ /** - * @brief DBI Write Norml-Data to rdata-register - * - * @param dataSize: size of data (max 4-byte) - * @param dataBuff: buff of data - * @return None - * -*******************************************************************************/ -void DBI_WriteNormlData(uint8_t dataSize, uint8_t *dataBuff) -{ - uint32_t para_data = 0; - - if(dataSize > 4){ - dataSize = 4; - } - - for(uint8_t i=0; i 0) { - BL_WR_REG(DBI_BASE, DBI_FIFO_WDATA, dataBuff[i++]); - } - } -} - -/****************************************************************************/ /** - * @brief DBI Calculate the WordCount of data in different pixel formats - * You should have configured the FIFO-format before - * @param PixelCount: pixel count - * @return Words Count - * -*******************************************************************************/ -uint32_t DBI_GetWordCountOfPixelData(int32_t PixelCount) -{ - uint32_t wordCount; - /* get pixel-formats of fifo*/ - DBI_FIFO_Format_Type fifoFormat = BL_GET_REG_BITS_VAL(BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0), DBI_FIFO_FORMAT); - - if(fifoFormat == DBI_FIFO_888_NBGR || fifoFormat == DBI_FIFO_888_NRGB){ - wordCount = PixelCount; - }else if(fifoFormat == DBI_FIFO_565_BGRBGR || fifoFormat == DBI_FIFO_565_RGBRGB){ - wordCount = (PixelCount + 1) >> 1; - }else{ - wordCount = (PixelCount * 3 + 3) >> 2; - } - return wordCount; -} - -/****************************************************************************/ /** - * @brief DBI send Command and write normal-data function - * - * @param command: Command to send (if command phase enable) - * @param dataSize: write size of NormalData (write max 4) - * @param dataBuff: buff of NormalData - * @return None - * -*******************************************************************************/ -void DBI_SendCmdWithNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff) -{ - /* disable transfer */ - DBI_Disable(); - - /* clear fifo and interrupt */ - DBI_IntClear(); - - /* set command */ - DBI_SetCommand(command); - - /* set data direction */ - DBI_SetNormalDataDir(DBI_DATA_WRITE); - - /* Data type select, and set data count */ - DBI_SetDataTypeAndCount(DBI_DATA_NORMAL, dataSize); - - /* Fill the data into the register */ - DBI_WriteNormlData(dataSize, dataBuff); - - /* enable transfer */ - DBI_Enable(); - - /* Wait transfer end */ - while (DBI_GetIntStatus(DBI_INT_END) != SET) { - } - - /* clear interrupt */ - DBI_IntClear(); -} - -/****************************************************************************/ /** - * @brief DBI send Command and read normal-data function - * - * @param command: Command to send (if command phase enable) - * @param dataSize: read size of NormalData (read max 4 ) - * @param dataBuff: buff of NormalData - * @return None - * -*******************************************************************************/ -void DBI_SendCmdAndReadNormalData(uint8_t command, uint8_t dataSize, uint8_t *dataBuff) -{ - /* disable transfer */ - DBI_Disable(); - - /* clear interrupt */ - DBI_IntClear(); - - /* set command */ - DBI_SetCommand(command); - - /* set data direction */ - DBI_SetNormalDataDir(DBI_DATA_READ); - - /* Data type select, and set data count */ - DBI_SetDataTypeAndCount(DBI_DATA_NORMAL, dataSize); - - /* enable transfer */ - DBI_Enable(); - - /* Wait transfer end */ - while (DBI_GetIntStatus(DBI_INT_END) != SET) { - } - - /* get data */ - DBI_ReadNormlData(dataSize, dataBuff); - - /* clear interrupt */ - DBI_IntClear(); -} - -/****************************************************************************/ /** - * @brief DBI send Command and write pixel-data function - * - * @param command: Command to send (if command phase enable) - * @param dataSize: write size of Pixel-Data - * @param dataBuff: buff of Pixel-Data - * @return None - * -*******************************************************************************/ -void DBI_SendCmdWithPixelData(uint8_t command, int32_t PixelCount, uint32_t *pixelBuff) -{ - /* disable transfer */ - DBI_Disable(); - - /* clear fifo and interrupt */ - DBI_TxFifoClear(); - DBI_IntClear(); - - /* set command */ - DBI_SetCommand(command); - - /* set data direction */ - DBI_SetNormalDataDir(DBI_DATA_WRITE); - - /* Data type select, and set data count */ - DBI_SetDataTypeAndCount(DBI_DATA_PIXEL, PixelCount); - - /* enable transfer */ - DBI_Enable(); - - /* get words count */ - uint32_t wordsCount = DBI_GetWordCountOfPixelData(PixelCount); - /* send data */ - DBI_WirteData2FIFO(wordsCount, pixelBuff); - - /* Wait transfer end */ - while (DBI_GetIntStatus(DBI_INT_END) != SET) { - } - - /* clear interrupt */ - DBI_IntClear(); -} - -/****************************************************************************/ /** - * @brief Clear tx fifo,overflow/underflow flag and fifo error interrupt will be cleared - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_TxFifoClear(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DBI_TX_FIFO_CLR); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable or disable signal of dma interface - * - * @param dmaEn: Enable or disable - * - * @return None - * -*******************************************************************************/ -void DBI_SetDMA(BL_Fun_Type dmaEn) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_DMA_TX_EN, dmaEn); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set tx fifo threshold - * - * @param threshold: Threshold value - * - * @return None - * -*******************************************************************************/ -void DBI_SetTxFifoThreshold(uint8_t threshold) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_TX_FIFO_TH, threshold); - BL_WR_REG(DBI_BASE, DBI_FIFO_CONFIG_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get tx fifo count value - * - * @param None - * - * @return Count value - * -*******************************************************************************/ -uint8_t DBI_GetTxFifoCount(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_1), DBI_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get interrupt status - * - * @param intType: DBI interrupt type - * - * @return Status of interrupt - * -*******************************************************************************/ -BL_Sts_Type DBI_GetIntStatus(DBI_INT_Type intType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - - if ((tmpVal >> intType & 1) == 1) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get tx fifo overflow/underflow status - * - * @param overflow: Select overflow or underflow - * - * @return Status of tx fifo - * -*******************************************************************************/ -BL_Sts_Type DBI_GetOverflowStatus(DBI_Overflow_Type overflow) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_OVERFLOW_TYPE(overflow)); - - tmpVal = BL_RD_REG(DBI_BASE, DBI_FIFO_CONFIG_0); - - if (overflow == DBI_TX_OVERFLOW) { - if (BL_IS_REG_BIT_SET(tmpVal, DBI_TX_FIFO_OVERFLOW)) { - return SET; - } else { - return RESET; - } - } else { - if (BL_IS_REG_BIT_SET(tmpVal, DBI_TX_FIFO_UNDERFLOW)) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Get DBI bus busy status - * - * @param None - * - * @return Status of DBI bus - * -*******************************************************************************/ -BL_Sts_Type DBI_GetBusBusyStatus(void) -{ - if (BL_IS_REG_BIT_SET(BL_RD_REG(DBI_BASE, DBI_BUS_BUSY), DBI_STS_DBI_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the DBI interrupt - * - * @param intType: DBI interrupt type - * @param intMask: Mask/Unmask - * - * @return None - * -*******************************************************************************/ -void DBI_IntMask(DBI_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DBI_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - - switch (intType) { - case DBI_INT_END: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_END_MASK, intMask); - break; - - case DBI_INT_TX_FIFO_REQ: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_TXF_MASK, intMask); - break; - - case DBI_INT_FIFO_ERR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_FER_MASK, intMask); - break; - - case DBI_INT_ALL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_END_MASK, intMask); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_TXF_MASK, intMask); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DBI_CR_DBI_FER_MASK, intMask); - break; - - default: - break; - } - - BL_WR_REG(DBI_BASE, DBI_INT_STS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Clear DBI interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DBI_IntClear(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DBI_BASE, DBI_INT_STS); - BL_WR_REG(DBI_BASE, DBI_INT_STS, BL_SET_REG_BIT(tmpVal, DBI_CR_DBI_END_CLR)); -} - -/****************************************************************************/ /** - * @brief Install DBI interrupt callback function - * - * @param intType: DBI interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DBI_Int_Callback_Install(DBI_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DBI_INT_TYPE(intType)); - - DBIIntCbfArra[intType] = cbFun; -} -#endif - -/*@} end of group DBI_Public_Functions */ - -/*@} end of group DBI */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c deleted file mode 100644 index aae3f9ae22..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma.c +++ /dev/null @@ -1,1060 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_dma.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA - * @{ - */ - -/** @defgroup DMA_Private_Macros - * @{ - */ -#define DMA_CHANNEL_OFFSET 0x100 -#define DMA_Get_Channel(id_base, ch) ((id_base) + DMA_CHANNEL_OFFSET + (ch)*0x100) - -/*@} end of group DMA_Private_Macros */ - -/** @defgroup DMA_Private_Types - * @{ - */ - -/*@} end of group DMA_Private_Types */ - -/** @defgroup DMA_Private_Variables - * @{ - */ -static const uint32_t dmaAddr[DMA_ID_MAX] = { DMA0_BASE, DMA1_BASE, DMA2_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *dmaIntCbfArra[DMA_ID_MAX][DMA_CH_MAX][DMA_INT_ALL] = { - { { NULL } } -}; -#endif -static DMA_LLI_Ctrl_Type PingPongListArra[DMA_ID_MAX][DMA_CH_MAX][2]; - -/*@} end of group DMA_Private_Variables */ - -/** @defgroup DMA_Global_Variables - * @{ - */ - -/*@} end of group DMA_Global_Variables */ - -/** @defgroup DMA_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA_IntHandler(DMA_ID_Type dmaId); -#endif -static void CPU_Interrupt_Enable_DMA(DMA_ID_Type dmaId); -static void CPU_Interrupt_Disable_DMA(DMA_ID_Type dmaId); - -/*@} end of group DMA_Private_Fun_Declaration */ - -/** @defgroup DMA_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA interrupt handler - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA_IntHandler(DMA_ID_Type dmaId) -{ - uint32_t tmpVal; - uint32_t intClr; - uint8_t ch; - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[dmaId]; - - for (ch = 0; ch < DMA_CH_MAX; ch++) { - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCSTATUS); - - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTTCCLEAR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTTCCLEAR, intClr); - BL_WR_REG(DMAChs, DMA_INTTCCLEAR, tmpVal); - - if (dmaIntCbfArra[dmaId][ch][DMA_INT_TCOMPLETED] != NULL) { - /* Call the callback function */ - dmaIntCbfArra[dmaId][ch][DMA_INT_TCOMPLETED](); - } - } - } - - for (ch = 0; ch < DMA_CH_MAX; ch++) { - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRORSTATUS); - - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRORSTATUS) & (1 << ch)) != 0) { - /*Clear interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_INTERRCLR); - intClr = BL_GET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR); - intClr |= (1 << ch); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_INTERRCLR, intClr); - BL_WR_REG(DMAChs, DMA_INTERRCLR, tmpVal); - - if (dmaIntCbfArra[dmaId][ch][DMA_INT_ERR] != NULL) { - /* Call the callback function */ - dmaIntCbfArra[dmaId][ch][DMA_INT_ERR](); - } - } - } -} -#endif - -/****************************************************************************/ /** - * @brief CPU enable DMA interrupt - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Enable_DMA(DMA_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - if (DMA0_ID == dmaId) { - CPU_Interrupt_Enable(DMA0_ALL_IRQn); - } else if (DMA1_ID == dmaId) { - CPU_Interrupt_Enable(DMA1_ALL_IRQn); - } else { - CPU_Interrupt_Enable(DMA2_INT0_IRQn); - CPU_Interrupt_Enable(DMA2_INT1_IRQn); - CPU_Interrupt_Enable(DMA2_INT2_IRQn); - CPU_Interrupt_Enable(DMA2_INT3_IRQn); - CPU_Interrupt_Enable(DMA2_INT4_IRQn); - CPU_Interrupt_Enable(DMA2_INT5_IRQn); - CPU_Interrupt_Enable(DMA2_INT6_IRQn); - CPU_Interrupt_Enable(DMA2_INT7_IRQn); - } -} - -/****************************************************************************/ /** - * @brief CPU disable DMA interrupt - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Disable_DMA(DMA_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - if (DMA0_ID == dmaId) { - CPU_Interrupt_Disable(DMA0_ALL_IRQn); - } else if (DMA1_ID == dmaId) { - CPU_Interrupt_Disable(DMA1_ALL_IRQn); - } else { - CPU_Interrupt_Disable(DMA2_INT0_IRQn); - CPU_Interrupt_Disable(DMA2_INT1_IRQn); - CPU_Interrupt_Disable(DMA2_INT2_IRQn); - CPU_Interrupt_Disable(DMA2_INT3_IRQn); - CPU_Interrupt_Disable(DMA2_INT4_IRQn); - CPU_Interrupt_Disable(DMA2_INT5_IRQn); - CPU_Interrupt_Disable(DMA2_INT6_IRQn); - CPU_Interrupt_Disable(DMA2_INT7_IRQn); - } -} - -/*@} end of group DMA_Private_Functions */ - -/** @defgroup DMA_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA enable - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -void DMA_Enable(DMA_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DMA0_ALL_IRQn, DMA0_ALL_IRQHandler); - Interrupt_Handler_Register(DMA1_ALL_IRQn, DMA1_ALL_IRQHandler); - Interrupt_Handler_Register(DMA2_INT0_IRQn, DMA2_INT0_IRQHandler); - Interrupt_Handler_Register(DMA2_INT1_IRQn, DMA2_INT1_IRQHandler); - Interrupt_Handler_Register(DMA2_INT2_IRQn, DMA2_INT2_IRQHandler); - Interrupt_Handler_Register(DMA2_INT3_IRQn, DMA2_INT3_IRQHandler); - Interrupt_Handler_Register(DMA2_INT4_IRQn, DMA2_INT4_IRQHandler); - Interrupt_Handler_Register(DMA2_INT5_IRQn, DMA2_INT5_IRQHandler); - Interrupt_Handler_Register(DMA2_INT6_IRQn, DMA2_INT6_IRQHandler); - Interrupt_Handler_Register(DMA2_INT7_IRQn, DMA2_INT7_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief DMA disable - * - * @param dmaId: DMA ID type - * - * @return None - * -*******************************************************************************/ -void DMA_Disable(DMA_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA register */ - uint32_t DMAChs = dmaAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMAChs, DMA_TOP_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_TOP_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA channel init - * - * @param dmaId: DMA ID type - * @param chCfg: DMA configuration - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Init(DMA_ID_Type dmaId, DMA_Channel_Cfg_Type *chCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], chCfg->ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(chCfg->ch)); - CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth)); - CHECK_PARAM(IS_DMA_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth)); - CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->srcBurstSize)); - CHECK_PARAM(IS_DMA_BURST_SIZE_TYPE(chCfg->dstBurstSize)); - CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(chCfg->dir)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->dstPeriph)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(chCfg->srcPeriph)); - - /* Disable clock gate when use DMA0 */ - if (DMA0_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0); - } else if (DMA1_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_1); - } else if (DMA2_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_2); - } - - /* Config channel config */ - BL_WR_REG(DMAChs, DMA_SRCADDR, chCfg->srcDmaAddr); - BL_WR_REG(DMAChs, DMA_DSTADDR, chCfg->destDmaAddr); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, chCfg->transfLength); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SWIDTH, chCfg->srcTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DWIDTH, chCfg->dstTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SBSIZE, chCfg->srcBurstSize); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DBSIZE, chCfg->dstBurstSize); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_ADD_MODE, chCfg->dstAddMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DST_MIN_MODE, chCfg->dstMinMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FIX_CNT, chCfg->fixCnt); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SI, chCfg->srcAddrInc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DI, chCfg->destAddrInc); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, chCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, chCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, chCfg->srcPeriph); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA set default value of all registers function - * - * @param dmaId: DMA ID type - * - * @return SUCCESS - * -*******************************************************************************/ -void DMA_DeInit(DMA_ID_Type dmaId) -{ - switch (dmaId) { - case DMA0_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_DMA); - break; - - case DMA1_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_DMA2); - break; - - case DMA2_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DMA); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief DMA channel update source memory address and len - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * @param memAddr: source memoty address - * @param len: source memory data length - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Update_SrcMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMAChs, DMA_SRCADDR, memAddr); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA channel update destination memory address and len - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * @param memAddr: destination memoty address - * @param len: destination memory data length - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Update_DstMemcfg(DMA_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMAChs, DMA_DSTADDR, memAddr); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_TRANSFERSIZE, len); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get DMA channel tranfersize - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * - * @return tranfersize size - * -*******************************************************************************/ -uint32_t DMA_Channel_TranferSize(DMA_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_TRANSFERSIZE); -} - -/****************************************************************************/ /** - * @brief Get DMA channel busy status - * - * @param dmaId: DMA ID type - * @param ch: DMA channel - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type DMA_Channel_Is_Busy(DMA_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - return BL_IS_REG_BIT_SET(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_E) == 1 ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief DMA enable - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Enable(DMA_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA disable - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * - * @return None - * -*******************************************************************************/ -void DMA_Channel_Disable(DMA_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_E); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA init LLI transfer - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * @param lliCfg: LLI configuration - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_Init(DMA_ID_Type dmaId, uint8_t ch, DMA_LLI_Cfg_Type *lliCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA_TRANS_DIR_TYPE(lliCfg->dir)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->dstPeriph)); - CHECK_PARAM(IS_DMA_PERIPH_REQ_TYPE(lliCfg->srcPeriph)); - - /* Disable clock gate when use DMA0 */ - if (DMA0_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_0); - } else if (DMA1_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_1); - } else if (DMA2_ID == dmaId) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_DMA_2); - } - - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_FLOWCNTRL, lliCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_DSTPERIPHERAL, lliCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA_SRCPERIPHERAL, lliCfg->srcPeriph); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA channel update LLI - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * @param LLI: LLI addr - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_Update(DMA_ID_Type dmaId, uint8_t ch, uint32_t LLI) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - /* Config channel config */ - //BL_WR_REG(DMAChs, DMA_LLI, LLI); - ARCH_MemCpy4((uint32_t *)(uintptr_t)DMAChs, (uint32_t *)(uintptr_t)LLI, 4); -} - -/****************************************************************************/ /** - * @brief DMA channel get LLI counter - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * - * @return LLI counter - * -*******************************************************************************/ -uint32_t DMA_LLI_Get_Counter(DMA_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_LLICOUNTER); -} - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Start - * - * @param dmaPpStruct: dma pp struct pointer - * @param Ping_Transfer_len: ping len - * @param Pong_Transfer_len: pong len - * - * @return Succrss or not - * -*******************************************************************************/ -BL_Err_Type DMA_LLI_PpStruct_Set_Transfer_Len(DMA_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len) -{ - struct DMA_Control_Reg dmaCtrlRegVal_temp; - - if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) { - return ERROR; - } - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - DMA_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - DMA_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA LLI Start New Transmit for Ping-Pong Buf - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpBuf_Start_New_Transmit(DMA_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId); - - if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) { - DMA_LLI_Update(dmaPpBuf->dmaId, dmaPpBuf->dmaChan, (uint32_t)(uintptr_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]); - DMA_Channel_Enable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0; - } - - CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA LLI Remove Completed Ping-Pong Buf List - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * - * @return Next Ping-Pong Buf List Header - * -*******************************************************************************/ -DMA_LLI_Ctrl_Type *DMA_LLI_PpBuf_Remove_Completed_List(DMA_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId); - - dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL; - CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId); - return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex]; -} - -/****************************************************************************/ /** - * @brief DMA LLI Append Buf to List - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * @param dmaLliList: New LLI Buf to Append - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpBuf_Append(DMA_LLI_PP_Buf *dmaPpBuf, DMA_LLI_Ctrl_Type *dmaLliList) -{ - DMA_LLI_Ctrl_Type *pLliList = NULL; - CPU_Interrupt_Disable_DMA(dmaPpBuf->dmaId); - - pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]; - - if (pLliList == NULL) { - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList; - } else { - /*Append to last */ - while (pLliList->nextLLI != 0) { - pLliList = (DMA_LLI_Ctrl_Type *)(uintptr_t)pLliList->nextLLI; - } - - pLliList->nextLLI = (uint32_t)(uintptr_t)dmaLliList; - pLliList->dmaCtrl.I = 0; - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - } - - if (DMA_Channel_Is_Busy(dmaPpBuf->dmaId, dmaPpBuf->dmaChan) == RESET) { - /* DMA stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable) - or has already stopped before this function is called */ - if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) { - /* DMA has already stopped before this function is called */ - DMA_LLI_PpBuf_Start_New_Transmit(dmaPpBuf); - } - } - - CPU_Interrupt_Enable_DMA(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA LLi Destroy Ping-Pong Buf - * - * @param dmaPpBuf: DMA LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpBuf_Destroy(DMA_LLI_PP_Buf *dmaPpBuf) -{ - /* DMA LLI Disable */ - DMA_Channel_Disable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - - if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]); - } - - dmaPpBuf->lliListHeader[0] = NULL; - - if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]); - } - - dmaPpBuf->lliListHeader[1] = NULL; - dmaPpBuf->idleIndex = 0; -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the DMA interrupt - * - * @param dmaId: DMA ID type - * @param ch: DMA channel number - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void DMA_IntMask(DMA_ID_Type dmaId, uint8_t ch, DMA_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMAChs = DMA_Get_Channel(dmaAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA_INT_TYPE(intType)); - - switch (intType) { - case DMA_INT_TCOMPLETED: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_ITC); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONTROL), DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } - - break; - - case DMA_INT_ERR: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMAChs, DMA_CONFIG), DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - } - - break; - - case DMA_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_ITC); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_RD_REG(DMAChs, DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_ITC); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA_IE); - BL_WR_REG(DMAChs, DMA_CONFIG, tmpVal); - tmpVal = BL_RD_REG(DMAChs, DMA_CONTROL); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA_I); - BL_WR_REG(DMAChs, DMA_CONTROL, tmpVal); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Install DMA interrupt callback function - * - * @param dmaId: DMA ID type - * @param dmaChan: DMA Channel type - * @param intType: DMA interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA_Int_Callback_Install(DMA_ID_Type dmaId, DMA_Chan_Type dmaChan, DMA_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA_CHAN_TYPE(dmaChan)); - CHECK_PARAM(IS_DMA_INT_TYPE(intType)); - - dmaIntCbfArra[dmaId][dmaChan][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief WLSYS DMA0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA0_ALL_IRQHandler(void) -{ - DMA_IntHandler(DMA0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief WLSYS DMA1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA1_ALL_IRQHandler(void) -{ - DMA_IntHandler(DMA1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT0_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT1_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT2_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT3_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 4 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT4_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 5 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT5_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 6 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT6_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA channel 7 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2_INT7_IRQHandler(void) -{ - DMA_IntHandler(DMA2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Initial - * - * @param dmaPpStruct: DMA LLI PingPong Config Parameter - * - * @return start success or not - * -*******************************************************************************/ -BL_Err_Type DMA_LLI_PpStruct_Init(DMA_LLI_PP_Struct *dmaPpStruct) -{ - //setup lliList - dmaPpStruct->dmaCtrlRegVal.I = 1; - dmaPpStruct->pingpongIndex = 0; - - if (dmaPpStruct->lliCfg->dir == DMA_TRNS_M2P) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - } else if (dmaPpStruct->lliCfg->dir == DMA_TRNS_P2M) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - } else { - return ERROR; - /*V1.0 version DMA LLI Ping-Pong structure not support P2P & M2M MODE*/ - } - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - DMA_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - - DMA_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Start - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpStruct_Start(DMA_LLI_PP_Struct *dmaPpStruct) -{ - DMA_Channel_Enable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/****************************************************************************/ /** - * @brief DMA LLI PingPong Structure Stop - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA_LLI_PpStruct_Stop(DMA_LLI_PP_Struct *dmaPpStruct) -{ - DMA_Channel_Disable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/*@} end of group DMA_Public_Functions */ - -/*@} end of group DMA */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c deleted file mode 100644 index d406f906f0..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dma2d.c +++ /dev/null @@ -1,1228 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dma2d.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_dma2d.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DMA2D - * @{ - */ - -/** @defgroup DMA2D_Private_Macros - * @{ - */ -#define DMA2D_Get_Channel(id_base, ch) ((id_base) + (ch)*0x100) - -/*@} end of group DMA2D_Private_Macros */ - -/** @defgroup DMA2D_Private_Types - * @{ - */ - -/*@} end of group DMA2D_Private_Types */ - -/** @defgroup DMA2D_Private_Variables - * @{ - */ -static const uint32_t dma2dAddr[DMA2D_ID_MAX] = { DMA2D_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *dma2dIntCbfArra[DMA2D_ID_MAX][DMA2D_CH_MAX][DMA2D_INT_ALL] = { - { { NULL } } -}; -#endif -static DMA2D_LLI_Ctrl_Type PingPongListArra[DMA2D_ID_MAX][DMA2D_CH_MAX][2]; - -/*@} end of group DMA2D_Private_Variables */ - -/** @defgroup DMA2D_Global_Variables - * @{ - */ - -/*@} end of group DMA2D_Global_Variables */ - -/** @defgroup DMA2D_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA2D_IntHandler(DMA2D_ID_Type dmaId); -#endif -static void CPU_Interrupt_Enable_DMA2D(DMA2D_ID_Type dmaId); -static void CPU_Interrupt_Disable_DMA2D(DMA2D_ID_Type dmaId); - -/*@} end of group DMA2D_Private_Fun_Declaration */ - -/** @defgroup DMA2D_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA2D interrupt handler - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void DMA2D_IntHandler(DMA2D_ID_Type dmaId) -{ - uint32_t tmpVal; - uint8_t ch; - /* Get DMA2D register */ - uint32_t DMA2DChs = dma2dAddr[dmaId]; - - for (ch = 0; ch < DMA2D_CH_MAX; ch++) { - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_INTSTATUS); - - if ((BL_GET_REG_BITS_VAL(tmpVal, DMA2D_INTSTATUS) & (1 << ch)) != 0) { - /* Clear interrupt */ - BL_WR_REG(DMA2DChs, DMA2D_DMA_INTTCCLEAR, 1 << ch); - - if (dma2dIntCbfArra[dmaId][ch][DMA2D_INT_TCOMPLETED] != NULL) { - /* Call the callback function */ - dma2dIntCbfArra[dmaId][ch][DMA2D_INT_TCOMPLETED](); - } - } - } -} -#endif - -/****************************************************************************/ /** - * @brief CPU enable DMA2D interrupt - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Enable_DMA2D(DMA2D_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - CPU_Interrupt_Enable(DMA2D_INT0_IRQn); - CPU_Interrupt_Enable(DMA2D_INT1_IRQn); -} - -/****************************************************************************/ /** - * @brief CPU disable DMA2D interrupt - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -static void CPU_Interrupt_Disable_DMA2D(DMA2D_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - CPU_Interrupt_Disable(DMA2D_INT0_IRQn); - CPU_Interrupt_Disable(DMA2D_INT1_IRQn); -} - -/*@} end of group DMA2D_Private_Functions */ - -/** @defgroup DMA2D_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DMA2D enable - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Enable(DMA2D_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = dma2dAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_E); - BL_WR_REG(DMA2DChs, DMA2D_DMA_CONFIG, tmpVal); -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(DMA2D_INT0_IRQn, DMA2D_INT0_IRQHandler); - Interrupt_Handler_Register(DMA2D_INT1_IRQn, DMA2D_INT1_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief DMA2D disable - * - * @param dmaId: DMA2D ID type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Disable(DMA2D_ID_Type dmaId) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = dma2dAddr[dmaId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_DMA_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_E); - BL_WR_REG(DMA2DChs, DMA2D_DMA_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D configure function - * - * @param dmaId: DMA2D ID type - * - * @return SUCCESS - * -*******************************************************************************/ -void DMA2D_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Cfg_Type *cfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, BL_SET_REG_BIT(tmpVal, DMA2D_REG_DMA_2D_EN)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_SRC_CNT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_X_CNT, cfg->srcCntX); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_Y_CNT, cfg->srcCntY); - BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_CNT, tmpVal); - - BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_XIC, cfg->srcIncrX); - BL_WR_REG(DMA2DChs, DMA2D_C0_SRC_YIC, cfg->srcIncrY); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_DST_CNT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_X_CNT, cfg->dstCntX); - BL_WR_REG(DMA2DChs, DMA2D_C0_DST_CNT, tmpVal); - - BL_WR_REG(DMA2DChs, DMA2D_C0_DST_XIC, cfg->dstIncrX); - BL_WR_REG(DMA2DChs, DMA2D_C0_DST_YIC, cfg->dstIncrY); -} - -/****************************************************************************/ /** - * @brief DMA2D channel init - * - * @param dmaId: DMA2D ID type - * @param chCfg: DMA2D configuration - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Init(DMA2D_ID_Type dmaId, DMA2D_Channel_Cfg_Type *chCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], chCfg->ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(chCfg->ch)); - CHECK_PARAM(IS_DMA2D_TRANS_WIDTH_TYPE(chCfg->srcTransfWidth)); - CHECK_PARAM(IS_DMA2D_TRANS_WIDTH_TYPE(chCfg->dstTransfWidth)); - CHECK_PARAM(IS_DMA2D_BURST_SIZE_TYPE(chCfg->srcBurstSize)); - CHECK_PARAM(IS_DMA2D_BURST_SIZE_TYPE(chCfg->dstBurstSize)); - CHECK_PARAM(IS_DMA2D_TRANS_DIR_TYPE(chCfg->dir)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(chCfg->dstPeriph)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(chCfg->srcPeriph)); - - /* Config channel config */ - BL_WR_REG(DMA2DChs, DMA2D_C0SRCADDR, chCfg->srcDmaAddr); - BL_WR_REG(DMA2DChs, DMA2D_C0DSTADDR, chCfg->destDmaAddr); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, chCfg->transfLength); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_SIZE, chCfg->srcTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_SIZE, chCfg->dstTransfWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRC_BURST, chCfg->srcBurstSize); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DST_BURST, chCfg->dstBurstSize); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SI, chCfg->srcAddrInc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DI, chCfg->destAddrInc); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_FLOWCNTRL, chCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DSTPERIPHERAL, chCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRCPERIPHERAL, chCfg->srcPeriph); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D set default value of all registers function - * - * @param dmaId: DMA2D ID type - * - * @return SUCCESS - * -*******************************************************************************/ -void DMA2D_DeInit(DMA2D_ID_Type dmaId) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_DMA2D); -} - -/****************************************************************************/ /** - * @brief DMA2D channel update source memory address and len - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * @param memAddr: source memoty address - * @param len: source memory data length - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Update_SrcMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMA2DChs, DMA2D_C0SRCADDR, memAddr); - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, len); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D channel update destination memory address and len - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * @param memAddr: destination memoty address - * @param len: destination memory data length - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Update_DstMemcfg(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t memAddr, uint32_t len) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - /* config channel config*/ - BL_WR_REG(DMA2DChs, DMA2D_C0DSTADDR, memAddr); - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_TRANSFERSIZE, len); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get DMA2D channel tranfersize - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * - * @return tranfersize size - * -*******************************************************************************/ -uint32_t DMA2D_Channel_TranferSize(DMA2D_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_TRANSFERSIZE); -} - -/****************************************************************************/ /** - * @brief Get DMA2D channel busy status - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type DMA2D_Channel_Is_Busy(DMA2D_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - return BL_IS_REG_BIT_SET(BL_RD_REG(DMA2DChs, DMA2D_C0_CFG), DMA2D_CH_EN) == 1 ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief DMA2D enable - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Enable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_CH_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D disable - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * - * @return None - * -*******************************************************************************/ -void DMA2D_Channel_Disable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_CH_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D init LLI transfer - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * @param lliCfg: LLI configuration - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_Init(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Cfg_Type *lliCfg) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA2D_TRANS_DIR_TYPE(lliCfg->dir)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(lliCfg->dstPeriph)); - CHECK_PARAM(IS_DMA2D_PERIPH_REQ_TYPE(lliCfg->srcPeriph)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_FLOWCNTRL, lliCfg->dir); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_DSTPERIPHERAL, lliCfg->dstPeriph); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_SRCPERIPHERAL, lliCfg->srcPeriph); - BL_WR_REG(DMA2DChs, DMA2D_C0_CFG, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D channel update LLI - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * @param LLI: LLI addr - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_Update(DMA2D_ID_Type dmaId, uint8_t ch, uint32_t LLI) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch) + 0x100; - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - /* Config channel config */ - //BL_WR_REG(DMA2DChs, DMA2D_LLI, LLI); - ARCH_MemCpy4((uint32_t *)(uintptr_t)DMA2DChs, (uint32_t *)(uintptr_t)LLI, 10); -} - -/****************************************************************************/ /** - * @brief DMA2D channel get LLI counter - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * - * @return LLI counter - * -*******************************************************************************/ -uint32_t DMA2D_LLI_Get_Counter(DMA2D_ID_Type dmaId, uint8_t ch) -{ - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DMA2DChs, DMA2D_C0_CFG), DMA2D_LLICOUNTER); -} - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Start - * - * @param dmaPpStruct: dma pp struct pointer - * @param Ping_Transfer_len: ping len - * @param Pong_Transfer_len: pong len - * - * @return Succrss or not - * -*******************************************************************************/ -BL_Err_Type DMA2D_LLI_PpStruct_Set_Transfer_Len(DMA2D_LLI_PP_Struct *dmaPpStruct, uint16_t Ping_Transfer_len, uint16_t Pong_Transfer_len) -{ - struct DMA2D_Control_Reg dmaCtrlRegVal_temp; - - if (Ping_Transfer_len > 4096 || Pong_Transfer_len > 4096) { - return ERROR; - } - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Ping_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - dmaCtrlRegVal_temp = PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl; - dmaCtrlRegVal_temp.TransferSize = Pong_Transfer_len; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl = dmaCtrlRegVal_temp; - - DMA2D_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - DMA2D_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA2D LLI Start New Transmit for Ping-Pong Buf - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpBuf_Start_New_Transmit(DMA2D_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId); - - if (dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] != NULL) { - DMA2D_LLI_Update(dmaPpBuf->dmaId, dmaPpBuf->dmaChan, (uint32_t)(uintptr_t)dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]); - DMA2D_Channel_Enable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - dmaPpBuf->idleIndex = (dmaPpBuf->idleIndex == 0) ? 1 : 0; - } - - CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA2D LLI Remove Completed Ping-Pong Buf List - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * - * @return Next Ping-Pong Buf List Header - * -*******************************************************************************/ -DMA2D_LLI_Ctrl_Type *DMA2D_LLI_PpBuf_Remove_Completed_List(DMA2D_LLI_PP_Buf *dmaPpBuf) -{ - CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId); - - dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] = NULL; - CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId); - return dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex]; -} - -/****************************************************************************/ /** - * @brief DMA2D LLI Append Buf to List - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * @param dmaLliList: New LLI Buf to Append - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpBuf_Append(DMA2D_LLI_PP_Buf *dmaPpBuf, DMA2D_LLI_Ctrl_Type *dmaLliList) -{ - DMA2D_LLI_Ctrl_Type *pLliList = NULL; - CPU_Interrupt_Disable_DMA2D(dmaPpBuf->dmaId); - - pLliList = dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex]; - - if (pLliList == NULL) { - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - dmaPpBuf->lliListHeader[dmaPpBuf->idleIndex] = dmaLliList; - } else { - /*Append to last */ - while (pLliList->nextLLI != 0) { - pLliList = (DMA2D_LLI_Ctrl_Type *)(uintptr_t)pLliList->nextLLI; - } - - pLliList->nextLLI = (uint32_t)(uintptr_t)dmaLliList; - pLliList->dmaCtrl.I = 0; - dmaLliList->nextLLI = 0; - dmaLliList->dmaCtrl.I = 1; - } - - if (DMA2D_Channel_Is_Busy(dmaPpBuf->dmaId, dmaPpBuf->dmaChan) == RESET) { - /* DMA2D stopped: maybe stop just a few minutes ago(not enter INT due to CPU_Interrupt_Disable) - or has already stopped before this function is called */ - if (dmaPpBuf->lliListHeader[!dmaPpBuf->idleIndex] == NULL) { - /* DMA2D has already stopped before this function is called */ - DMA2D_LLI_PpBuf_Start_New_Transmit(dmaPpBuf); - } - } - - CPU_Interrupt_Enable_DMA2D(dmaPpBuf->dmaId); -} - -/****************************************************************************/ /** - * @brief DMA2D LLi Destroy Ping-Pong Buf - * - * @param dmaPpBuf: DMA2D LLI Ping-Pong Buf - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpBuf_Destroy(DMA2D_LLI_PP_Buf *dmaPpBuf) -{ - /* DMA2D LLI Disable */ - DMA2D_Channel_Disable(dmaPpBuf->dmaId, dmaPpBuf->dmaChan); - - if (dmaPpBuf->lliListHeader[0] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[0]); - } - - dmaPpBuf->lliListHeader[0] = NULL; - - if (dmaPpBuf->lliListHeader[1] != NULL && dmaPpBuf->onTransCompleted != NULL) { - dmaPpBuf->onTransCompleted(dmaPpBuf->lliListHeader[1]); - } - - dmaPpBuf->lliListHeader[1] = NULL; - dmaPpBuf->idleIndex = 0; -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the DMA2D interrupt - * - * @param dmaId: DMA2D ID type - * @param ch: DMA2D channel number - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void DMA2D_IntMask(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - /* Get channel register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(ch)); - CHECK_PARAM(IS_DMA2D_INT_TYPE(intType)); - - switch (intType) { - case DMA2D_INT_TCOMPLETED: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(BL_RD_REG(DMA2DChs, DMA2D_C0_BUS), DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } - - break; - - case DMA2D_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_BUS); - tmpVal = BL_CLR_REG_BIT(tmpVal, DMA2D_I); - BL_WR_REG(DMA2DChs, DMA2D_C0_BUS, tmpVal); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Install DMA2D interrupt callback function - * - * @param dmaId: DMA2D ID type - * @param dmaChan: DMA2D Channel type - * @param intType: DMA2D interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_Int_Callback_Install(DMA2D_ID_Type dmaId, DMA2D_Chan_Type dmaChan, DMA2D_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_ID_TYPE(dmaId)); - CHECK_PARAM(IS_DMA2D_CHAN_TYPE(dmaChan)); - CHECK_PARAM(IS_DMA2D_INT_TYPE(intType)); - - dma2dIntCbfArra[dmaId][dmaChan][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA2D channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_INT0_IRQHandler(void) -{ - DMA2D_IntHandler(DMA2D0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief MMSYS DMA2D channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DMA2D_INT1_IRQHandler(void) -{ - DMA2D_IntHandler(DMA2D0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Initial - * - * @param dmaPpStruct: DMA2D LLI PingPong Config Parameter - * - * @return start success or not - * -*******************************************************************************/ -BL_Err_Type DMA2D_LLI_PpStruct_Init(DMA2D_LLI_PP_Struct *dmaPpStruct) -{ - //setup lliList - dmaPpStruct->dmaCtrlRegVal.I = 1; - dmaPpStruct->pingpongIndex = 0; - - if (dmaPpStruct->lliCfg->dir == DMA2D_TRNS_M2P) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].srcDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].destDmaAddr = dmaPpStruct->operatePeriphAddr; - } else if (dmaPpStruct->lliCfg->dir == DMA2D_TRNS_P2M) { - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[0]; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].srcDmaAddr = dmaPpStruct->operatePeriphAddr; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].destDmaAddr = dmaPpStruct->pingpongBufAddr[1]; - } else { - return ERROR; - /*V1.0 version DMA2D LLI Ping-Pong structure not support P2P & M2M MODE*/ - } - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].nextLLI = (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]; - PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PONG_INDEX].dmaCtrl = dmaPpStruct->dmaCtrlRegVal; - - DMA2D_LLI_Init(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, dmaPpStruct->lliCfg); - - DMA2D_LLI_Update(dmaPpStruct->dmaId, dmaPpStruct->dmaChan, (uint32_t)(uintptr_t)&PingPongListArra[dmaPpStruct->dmaId][dmaPpStruct->dmaChan][DMA2D_PING_INDEX]); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Start - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpStruct_Start(DMA2D_LLI_PP_Struct *dmaPpStruct) -{ - DMA2D_Channel_Enable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/****************************************************************************/ /** - * @brief DMA2D LLI PingPong Structure Stop - * - * @param dmaPpStruct: None - * - * @return None - * -*******************************************************************************/ -void DMA2D_LLI_PpStruct_Stop(DMA2D_LLI_PP_Struct *dmaPpStruct) -{ - DMA2D_Channel_Disable(dmaPpStruct->dmaId, dmaPpStruct->dmaChan); -} - -/****************************************************************************/ /** - * @brief DMA2D translate picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Translate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = tmpVal; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = tmpVal; - lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; -} - -/****************************************************************************/ /** - * @brief DMA2D rotate picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * @param rotate: Rotate degree type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Rotate_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Rotate_Type rotate) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = tmpVal; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = pictureCfg.dstWidth * pictureCfg.pixWidth; - lliCfg->dma2dCfg.dstIncrY = -((pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal * pictureCfg.pixWidth * pictureCfg.dstWidth) + pictureCfg.pixWidth * pictureCfg.dstWidth - tmpVal; - - if (rotate == DMA2D_ROTATE_DEGREE_90) { - lliCfg->destDmaAddr += (pictureCfg.srcY1 - pictureCfg.srcY0 - 1) * tmpVal; - } else if (rotate == DMA2D_ROTATE_DEGREE_180) { - lliCfg->destDmaAddr += (pictureCfg.srcY1 - pictureCfg.srcY0) * tmpVal * pictureCfg.dstWidth + (pictureCfg.srcX1 - pictureCfg.srcX0 - 1) * tmpVal; - lliCfg->dma2dCfg.dstIncrX = -tmpVal; - lliCfg->dma2dCfg.dstIncrY = -pictureCfg.dstWidth * pictureCfg.pixWidth + (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal; - } else if (rotate == DMA2D_ROTATE_DEGREE_270) { - lliCfg->destDmaAddr += (pictureCfg.srcX1 - pictureCfg.srcX0 - 1) * tmpVal * pictureCfg.dstWidth; - lliCfg->dma2dCfg.dstIncrX = -pictureCfg.dstWidth * pictureCfg.pixWidth; - lliCfg->dma2dCfg.dstIncrY = -lliCfg->dma2dCfg.dstIncrY; - } -} - -/****************************************************************************/ /** - * @brief DMA2D fold picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * @param fold: Fold direction type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Fold_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg, DMA2D_Fold_Type fold) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr + pictureCfg.srcWidth * pictureCfg.pixWidth * pictureCfg.srcY0 + pictureCfg.pixWidth * pictureCfg.srcX0; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0 + (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = tmpVal; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = (pictureCfg.srcWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = -tmpVal; - lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth + pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth - tmpVal; - - if (fold == DMA2D_FOLD_UP_DOWN) { - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0 + (pictureCfg.srcY1 - pictureCfg.srcY0 - 1) * pictureCfg.pixWidth * pictureCfg.dstWidth; - lliCfg->dma2dCfg.dstIncrX = tmpVal; - lliCfg->dma2dCfg.dstIncrY = -lliCfg->dma2dCfg.dstIncrY; - } -} - -/****************************************************************************/ /** - * @brief DMA2D fill picture - * - * @param cfg: Pointer of DMA2D picture configure type - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Fill_Calculate(DMA2D_Picture_Cfg_Type *cfg, DMA2D_LLI_Ctrl_Type *lliCfg) -{ - uint32_t tmpVal = 1 << cfg->transWidth; - lliCfg->dmaCtrl.SRC_SIZE = cfg->transWidth; - lliCfg->dmaCtrl.DST_SIZE = cfg->transWidth; - - DMA2D_Picture_Cfg_Type pictureCfg = { - .transWidth = cfg->transWidth, - .pixWidth = cfg->pixWidth, - .srcAddr = cfg->srcAddr, - .srcWidth = cfg->srcWidth, - .srcX0 = cfg->srcX0, - .srcY0 = cfg->srcY0, - .srcX1 = cfg->srcX1, - .srcY1 = cfg->srcY1, - .dstAddr = cfg->dstAddr, - .dstWidth = cfg->dstWidth, - .dstX0 = cfg->dstX0, - .dstY0 = cfg->dstY0, - }; - - if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 <= cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } else if (cfg->srcX0 <= cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth; - } else if (cfg->srcX0 > cfg->srcX1 && cfg->srcY0 > cfg->srcY1) { - pictureCfg.srcX0 = cfg->srcX1; - pictureCfg.srcX1 = cfg->srcX0; - pictureCfg.srcY0 = cfg->srcY1; - pictureCfg.srcY1 = cfg->srcY0; - pictureCfg.dstAddr = pictureCfg.dstAddr - (pictureCfg.srcY1 - pictureCfg.srcY0) * pictureCfg.pixWidth * pictureCfg.srcWidth - (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth; - } - - lliCfg->srcDmaAddr = pictureCfg.srcAddr; - lliCfg->destDmaAddr = pictureCfg.dstAddr + pictureCfg.dstWidth * pictureCfg.pixWidth * pictureCfg.dstY0 + pictureCfg.pixWidth * pictureCfg.dstX0; - - lliCfg->dma2dCfg.srcCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.srcIncrX = 0; - lliCfg->dma2dCfg.srcCntY = pictureCfg.srcY1 - pictureCfg.srcY0; - lliCfg->dma2dCfg.srcIncrY = 0; - lliCfg->dma2dCfg.dstCntX = (pictureCfg.srcX1 - pictureCfg.srcX0) * pictureCfg.pixWidth / tmpVal; - lliCfg->dma2dCfg.dstIncrX = tmpVal; - lliCfg->dma2dCfg.dstIncrY = (pictureCfg.dstWidth - pictureCfg.srcX1 + pictureCfg.srcX0) * pictureCfg.pixWidth + tmpVal; -} - -/****************************************************************************/ /** - * @brief DMA2D transfer start - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * @param lliCfg: Pointer of DMA2D LLI ctrl type - * - * @return None - * -*******************************************************************************/ -void DMA2D_Picture_Transfer_Start(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_LLI_Ctrl_Type *lliCfg) -{ - DMA2D_Channel_Cfg_Type chCfg = { - .srcDmaAddr = lliCfg->srcDmaAddr, - .destDmaAddr = lliCfg->destDmaAddr, - .transfLength = 0, - .dir = DMA2D_TRNS_M2M, - .ch = ch, - .srcTransfWidth = lliCfg->dmaCtrl.SRC_SIZE, - .dstTransfWidth = lliCfg->dmaCtrl.DST_SIZE, - .srcBurstSize = DMA2D_BURST_SIZE_16, - .dstBurstSize = DMA2D_BURST_SIZE_16, - .srcAddrInc = DMA2D_MINC_ENABLE, - .destAddrInc = DMA2D_MINC_ENABLE, - .srcPeriph = DMA2D_REQ_NONE, - .dstPeriph = DMA2D_REQ_NONE, - }; - - DMA2D_Channel_Disable(dmaId, ch); - DMA2D_Init(dmaId, ch, &lliCfg->dma2dCfg); - DMA2D_Channel_Init(dmaId, &chCfg); - DMA2D_Enable(dmaId); - DMA2D_Channel_Enable(dmaId, ch); -} - -/****************************************************************************/ /** - * @brief DMA2D color key mode configure - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * @param keyType: Color key type - * @param keyValue: Color key value - * - * @return None - * -*******************************************************************************/ -void DMA2D_Color_Key_Set(DMA2D_ID_Type dmaId, uint8_t ch, DMA2D_Color_Key_Type keyType, uint32_t keyValue) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_COLOR_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_MODE, keyType); - switch(keyType) - { - case DMA2D_COLOR_KEY_8BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x1); - break; - case DMA2D_COLOR_KEY_16BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x3); - break; - case DMA2D_COLOR_KEY_24BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0x7); - break; - case DMA2D_COLOR_KEY_32BIT: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DMA2D_KEY_STRB, 0xf); - break; - default: - break; - } - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, tmpVal); - - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY, keyValue); -} - -/****************************************************************************/ /** - * @brief DMA2D color key mode enable - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * - * @return None - * -*******************************************************************************/ -void DMA2D_Color_Key_Enable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - /* Check the parameters */ - CHECK_PARAM(IS_DMA2D_COLOR_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, DMA2D_KEY_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, tmpVal); -} - -/****************************************************************************/ /** - * @brief DMA2D color key mode disable - * - * @param dmaId: DMA2D id - * @param ch: DMA2D channel - * - * @return None - * -*******************************************************************************/ -void DMA2D_Color_Key_Disable(DMA2D_ID_Type dmaId, uint8_t ch) -{ - uint32_t tmpVal; - /* Get DMA2D register */ - uint32_t DMA2DChs = DMA2D_Get_Channel(dma2dAddr[dmaId], ch); - - tmpVal = BL_RD_REG(DMA2DChs, DMA2D_C0_KEY_EN); - BL_WR_REG(DMA2DChs, DMA2D_C0_KEY_EN, BL_CLR_REG_BIT(tmpVal, DMA2D_KEY_EN)); -} - -/*@} end of group DMA2D_Public_Functions */ - -/*@} end of group DMA2D */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c deleted file mode 100644 index cc52e40294..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsi.c +++ /dev/null @@ -1,1500 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsi.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsi.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSI - * @{ - */ - -/** @defgroup DSI_Private_Macros - * @{ - */ -#define DSI_TX_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group DSI_Private_Macros */ - -/** @defgroup DSI_Private_Types - * @{ - */ - -/*@} end of group DSI_Private_Types */ - -/** @defgroup DSI_Private_Variables - * @{ - */ - -static const uint32_t dsiAddr[DSI_ID_MAX] = { DSI_BASE }; - -/** - * @brief DSI interrupt callback function address array -*/ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *DSIIntCbfArra[DSI_ID_MAX][DSI_INT_COUNT] = { - { NULL, NULL, NULL } -}; -#endif -/*@} end of group DSI_Private_Variables */ - -/** @defgroup DSI_Global_Variables - * @{ - */ - -/*@} end of group DSI_Global_Variables */ - -/** @defgroup DSI_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type DSI_IntHandler(DSI_ID_Type dsiId); -#endif - -/*@} end of group DSI_Private_Fun_Declaration */ - -/** @defgroup DSI_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DSI interrupt handle - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type DSI_IntHandler(DSI_ID_Type dsiId) -{ - uint32_t maskVal; - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_CAM_ID_TYPE(dsiId)); - - maskVal = BL_RD_REG(DSIx, DSI_INT_MASK); - tmpVal = BL_RD_REG(DSIx, DSI_INT_STATUS); - - if (tmpVal & DSI_INT_ESCAPE_TX_END && !(maskVal & DSI_INT_ESCAPE_TX_END)) { - DSI_IntClear(dsiId, DSI_INT_ESCAPE_TX_END); - - if (DSIIntCbfArra[dsiId][0] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][0](); - } - } - - if (tmpVal & DSI_INT_LPDT_RX_END && !(maskVal & DSI_INT_LPDT_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_LPDT_RX_END); - - if (DSIIntCbfArra[dsiId][1] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][1](); - } - } - - if (tmpVal & DSI_INT_ULPS_RX_END && !(maskVal & DSI_INT_ULPS_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_ULPS_RX_END); - - if (DSIIntCbfArra[dsiId][2] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][2](); - } - } - - if (tmpVal & DSI_INT_TRIGGER0_RX_END && !(maskVal & DSI_INT_TRIGGER0_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER0_RX_END); - - if (DSIIntCbfArra[dsiId][3] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][3](); - } - } - - if (tmpVal & DSI_INT_TRIGGER1_RX_END && !(maskVal & DSI_INT_TRIGGER1_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER1_RX_END); - - if (DSIIntCbfArra[dsiId][4] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][4](); - } - } - - if (tmpVal & DSI_INT_TRIGGER2_RX_END && !(maskVal & DSI_INT_TRIGGER2_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER2_RX_END); - - if (DSIIntCbfArra[dsiId][5] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][5](); - } - } - - if (tmpVal & DSI_INT_TRIGGER3_RX_END && !(maskVal & DSI_INT_TRIGGER3_RX_END)) { - DSI_IntClear(dsiId, DSI_INT_TRIGGER3_RX_END); - - if (DSIIntCbfArra[dsiId][6] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][6](); - } - } - - if (tmpVal & DSI_INT_TX_FIFO_READY && !(maskVal & DSI_INT_TX_FIFO_READY)) { - DSI_IntClear(dsiId, DSI_INT_TX_FIFO_READY); - - if (DSIIntCbfArra[dsiId][7] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][7](); - } - } - - if (tmpVal & DSI_INT_RX_FIFO_READY && !(maskVal & DSI_INT_RX_FIFO_READY)) { - DSI_IntClear(dsiId, DSI_INT_RX_FIFO_READY); - - if (DSIIntCbfArra[dsiId][8] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][8](); - } - } - - if (tmpVal & DSI_INT_DATA_OVERRUN_ERR && !(maskVal & DSI_INT_DATA_OVERRUN_ERR)) { - DSI_IntClear(dsiId, DSI_INT_DATA_OVERRUN_ERR); - - if (DSIIntCbfArra[dsiId][9] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][9](); - } - } - - if (tmpVal & DSI_INT_DATA_UNDERRUN_ERR && !(maskVal & DSI_INT_DATA_UNDERRUN_ERR)) { - DSI_IntClear(dsiId, DSI_INT_DATA_UNDERRUN_ERR); - - if (DSIIntCbfArra[dsiId][10] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][10](); - } - } - - if (tmpVal & DSI_INT_PIXEL_COUNT_SMALL_ERR && !(maskVal & DSI_INT_PIXEL_COUNT_SMALL_ERR)) { - DSI_IntClear(dsiId, DSI_INT_PIXEL_COUNT_SMALL_ERR); - - if (DSIIntCbfArra[dsiId][11] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][11](); - } - } - - if (tmpVal & DSI_INT_PIXEL_COUNT_LARGE_ERR && !(maskVal & DSI_INT_PIXEL_COUNT_LARGE_ERR)) { - DSI_IntClear(dsiId, DSI_INT_PIXEL_COUNT_LARGE_ERR); - - if (DSIIntCbfArra[dsiId][12] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][12](); - } - } - - if (tmpVal & DSI_INT_FIFO_ERROR && !(maskVal & DSI_INT_FIFO_ERROR)) { - DSI_IntClear(dsiId, DSI_INT_FIFO_ERROR); - - if (DSIIntCbfArra[dsiId][13] != NULL) { - /* call the callback function */ - DSIIntCbfArra[dsiId][13](); - } - } - - return SUCCESS; -} -#endif - -/*@} end of group DSI_Private_Functions */ - -/** @defgroup DSI_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DSI module init - * - * @param dsiId: DSI ID type - * @param cfg: DSI configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSI_Init(DSI_ID_Type dsiId, DSI_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - DSI_Lane_Type lanes=0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_DATA_TYPE(cfg->dataType)); - CHECK_PARAM(IS_DSI_LANE_NUMBER_TYPE(cfg->laneNum)); - CHECK_PARAM(IS_DSI_LANE_ORDER_TYPE(cfg->laneOrder)); - CHECK_PARAM(IS_DSI_HS_SYNC_TYPE(cfg->syncType)); - - /* Set DSI configuration */ - tmpVal = BL_RD_REG(DSIx, DSI_CONFIG); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LANE_NUM, cfg->laneNum); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_MODE, cfg->syncType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LANE_MUX_SEL, cfg->laneOrder); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_DT, cfg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_VC, cfg->virtualChan); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VFP, cfg->vfp); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_HSTX_VSA, cfg->vsa); - - BL_WR_REG(DSIx, DSI_CONFIG, tmpVal); - - if(cfg->laneNum == DSI_LANE_NUMBER_1){ - lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0; - }else if(cfg->laneNum == DSI_LANE_NUMBER_2){ - lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0|DSI_LANE_DATA1; - }else if(cfg->laneNum == DSI_LANE_NUMBER_4){ - lanes=DSI_LANE_CLOCK|DSI_LANE_DATA0|DSI_LANE_DATA1|DSI_LANE_DATA2|DSI_LANE_DATA3; - } - - DSI_PHY_Enable_Lanes(dsiId,lanes); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(MIPI_DSI_IRQn, DSI_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Deinit DSI module - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_Deinit(DSI_ID_Type dsiId) -{ -} - -/****************************************************************************/ /** - * @brief DSI Enable Disable Interrupt - * - * @param dsiId: DSI ID type - * @param intType: DSI Interrupt Type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -void DSI_IntMask(DSI_ID_Type dsiId, DSI_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_MASK); - - if (intMask == UNMASK) { - /* Unmask this interrupt */ - tmpVal &= (~intType); - - } else { - /* Mask this interrupt */ - tmpVal |= intType; - } - - BL_WR_REG(DSIx, DSI_INT_MASK, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Clear Interrupt - * - * @param dsiId: DSI ID type - * @param intType: DSI Interrupt Type - * - * @return None - * -*******************************************************************************/ -void DSI_IntClear(DSI_ID_Type dsiId, DSI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_CLEAR); - - /* Clear this interrupt */ - tmpVal |= intType; - - BL_WR_REG(DSIx, DSI_INT_CLEAR, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Enable Interrupt - * - * @param dsiId: DSI ID type - * @param intType: DSI Interrupt Type - * - * @return None - * -*******************************************************************************/ -void DSI_IntEnable(DSI_ID_Type dsiId, DSI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_ENABLE); - - /* Enable this interrupt */ - tmpVal |= intType; - - BL_WR_REG(DSIx, DSI_INT_ENABLE, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Get Interrupt status - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -DSI_INT_Type DSI_IntGet(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_INT_STATUS); - - return BL_GET_REG_BITS_VAL(tmpVal, DSI_INT_STATUS); -} - -/****************************************************************************/ /** - * @brief DSI set line buffer threshold for controller to start transmitting each line(unit:pixel) - * - * @param dsiId: DSI ID type - * @param frameWidth: frame width - * @param dvpTsrcClock: display(dp_dvp_tsrc) clock rate - * @param dsiClock: DSI bit clock rate - * @param dataType: DSI data type - * @param laneNumber: DSI lane number - * - * @return None - * -*******************************************************************************/ -void DSI_Set_Line_Buffer_Threshold(DSI_ID_Type dsiId, uint32_t frameWidth, uint32_t dvpTsrcClock, uint32_t dsiClock, \ - DSI_Data_Type dataType, DSI_Lane_Number_Type laneNumber) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - int64_t threshold = dvpTsrcClock; - uint32_t pixelByte; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_DATA_TYPE(dataType)); - CHECK_PARAM(IS_DSI_LANE_NUMBER_TYPE(laneNumber)); - - /* Frame Width should not exceed 1280 and should be a multiple of 4 */ - if(frameWidth > 1280 || frameWidth % 4){ - return; - } - - if(dataType < DSI_DATA_RGB666){ - pixelByte = 2; - }else{ - pixelByte = 3; - } - - threshold = frameWidth - threshold*frameWidth*pixelByte/(dsiClock/8)/(1<time_clk_zero); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_CK_TRAIL, phyCfg->time_clk_trail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_CK_EXIT, phyCfg->time_clk_exit); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_ZERO, phyCfg->time_data_zero); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_TRAIL, phyCfg->time_data_trail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_EXIT, phyCfg->time_data_exit); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_HS_PREP, phyCfg->time_data_prepare); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_TA_GO, phyCfg->time_ta_go); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_TA_GET, phyCfg->time_ta_get); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_REQRDY, phyCfg->time_req_ready); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_LPX, phyCfg->time_lpx); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_REG_TIME_WAKEUP, phyCfg->time_wakeup); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_4, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI Reinit data lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Reinit_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_FORCERXMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_FORCERXMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_FORCERXMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_FORCERXMODE); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_FORCERXMODE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_FORCERXMODE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_FORCERXMODE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_FORCERXMODE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI enable lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Enable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_ENABLE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_ENABLE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_ENABLE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_ENABLE); - } - - if (lanes & DSI_LANE_CLOCK) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_ENABLE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI disable lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Disable_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_ENABLE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_ENABLE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_ENABLE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_ENABLE); - } - - if (lanes & DSI_LANE_CLOCK) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_ENABLE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI stop data lanes - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Stop_Data_Lanes(DSI_ID_Type dsiId, DSI_Lane_Type lanes) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL0_FORCETXSTOPMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL1_FORCETXSTOPMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL2_FORCETXSTOPMODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DL3_FORCETXSTOPMODE); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); - - if (lanes & DSI_LANE_DATA0) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_FORCETXSTOPMODE); - } - - if (lanes & DSI_LANE_DATA1) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL1_FORCETXSTOPMODE); - } - - if (lanes & DSI_LANE_DATA2) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL2_FORCETXSTOPMODE); - } - - if (lanes & DSI_LANE_DATA3) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL3_FORCETXSTOPMODE); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI stop data lanes - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Data_Lane0_TurnAround(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DL0_TURNESC); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief DSI get lanes state - * - * @param dsiId: DSI ID type - * - * @param lanes: lanes - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Get_Lanes_State(DSI_ID_Type dsiId, DSI_Lane_Type lane, DSI_Lane_State_Type *state) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - uint32_t stop_state_pos = 0; - uint32_t ulp_state_pos = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_LANE_TYPE(lanes)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - *state = DSI_LANE_STAT_NORMAL; - - if (lane == DSI_LANE_DATA0) { - stop_state_pos = DSI_DL0_STOPSTATE_POS; - ulp_state_pos = DSI_DL0_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_DATA1) { - stop_state_pos = DSI_DL1_STOPSTATE_POS; - ulp_state_pos = DSI_DL1_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_DATA2) { - stop_state_pos = DSI_DL2_STOPSTATE_POS; - ulp_state_pos = DSI_DL2_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_DATA3) { - stop_state_pos = DSI_DL3_STOPSTATE_POS; - ulp_state_pos = DSI_DL3_ULPSACTIVENOT_POS; - } else if (lane == DSI_LANE_CLOCK) { - stop_state_pos = DSI_CL_STOPSTATE_POS; - ulp_state_pos = DSI_CL_ULPSACTIVENOT_POS; - } else { - return; - } - - if(!(tmpVal & (1 << ulp_state_pos))) { - *state = DSI_LANE_STAT_ULP; - } else if(tmpVal & (1 << stop_state_pos)) { - *state = DSI_LANE_STAT_STOP; - } else { - if(lane == DSI_LANE_CLOCK) { - if(tmpVal & (1 << DSI_CL_TXREQUESTHS_POS)) { - *state = DSI_LANE_STAT_HS; - } else { - *state = DSI_LANE_STAT_BRIDGE; - } - } else { - if(BL_RD_REG(DSIx, DSI_CONFIG) & (1 << DSI_CR_HSTX_EN_POS)) { - *state = DSI_LANE_STAT_HS; - } else { - *state = DSI_LANE_STAT_BRIDGE; - } - } - } -} - -/****************************************************************************/ /** - * @brief Set clock lane operation - * - * @param dsiId: DSI ID type - * - * @param opt: operation type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_Set_Clock_Lane(DSI_ID_Type dsiId, DSI_Clock_Lane_Opt_Type opt) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - CHECK_PARAM(IS_DSI_CLOCK_LANE_OPT_TYPE(opt)); - - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - - if (opt & DSI_CLOCK_LANE_OPT_ULP_ENTER) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXULPSCLK); - } - - if (opt & DSI_CLOCK_LANE_OPT_ULP_EXIT) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXULPSEXIT); - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); - arch_delay_ms(1); - tmpVal = BL_RD_REG(DSIx, DSI_DPHY_CONFIG_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_TXULPSCLK); - } - - if (opt & DSI_CLOCK_LANE_OPT_HS_REQ) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS); - } - - if (opt & DSI_CLOCK_LANE_OPT_HS_EXIT) { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CL_TXREQUESTHS); - } - - BL_WR_REG(DSIx, DSI_DPHY_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Start HS Mode - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_HS_Mode_Start(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - DSI_Lane_State_Type state = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - /* bring clock lane to high speed */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state); - if(state == DSI_LANE_STAT_STOP){ - DSI_PHY_Set_Clock_Lane(dsiId, DSI_CLOCK_LANE_OPT_HS_REQ); - } - - /* bring data lane to high speed */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - if(state == DSI_LANE_STAT_STOP){ - tmpVal = BL_RD_REG(DSIx, DSI_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_HSTX_EN); - BL_WR_REG(DSIx, DSI_CONFIG, tmpVal); - } - -} - -/****************************************************************************/ /** - * @brief Stop HS Mode - * - * @param dsiId: DSI ID type - * - * @return None - * -*******************************************************************************/ -void DSI_PHY_HS_Mode_Stop(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - DSI_Lane_State_Type state = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - /* set data lane to stop mode */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - if(state != DSI_LANE_STAT_STOP){ - tmpVal = BL_RD_REG(DSIx, DSI_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_HSTX_EN); - BL_WR_REG(DSIx, DSI_CONFIG, tmpVal); - do{ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - }while(state != DSI_LANE_STAT_STOP); - } - - /* set clock lane to stop mode */ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state); - if(state != DSI_LANE_STAT_STOP){ - DSI_PHY_Set_Clock_Lane(dsiId, DSI_CLOCK_LANE_OPT_HS_EXIT); - do{ - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_CLOCK, &state); - }while(state != DSI_LANE_STAT_STOP); - } - -} - -/****************************************************************************/ /** - * @brief DSI configure fifo function - * - * @param dsiId: DSI ID type - * - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_FifoConfig(DSI_ID_Type dsiId, DSI_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - /* Deal with DSI fifo configure register */ - tmpVal = BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1); - /* Configure dma tx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold); - /* Configure dma rx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold); - /* Write back */ - BL_WR_REG(DSIx, DSI_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable DSI fifo dma function */ - tmpVal = BL_RD_REG(DSIx, DSI_FIFO_CONFIG_0); - - if (ENABLE == fifoCfg->txFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DMA_TX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DMA_TX_EN); - } - - if (ENABLE == fifoCfg->rxFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_DMA_RX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_DMA_RX_EN); - } - - BL_WR_REG(DSIx, DSI_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI start tx for short and long packet - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Start_Tx(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************//** - * @brief DSI wait for send done - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Wait_For_Esc_Tx_Done(DSI_ID_Type dsiId) -{ - DSI_INT_Type intStatus; - - /* wait for Tx finished */ - do{ - intStatus=DSI_IntGet(dsiId); - }while(!(intStatus&DSI_INT_ESCAPE_TX_END)); - DSI_IntClear(dsiId,DSI_INT_ESCAPE_TX_END); - - return SUCCESS; -} -/****************************************************************************/ /** - * @brief DSI start rx for short and long packet - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Start_Rx(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_RX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI Get Rx length - * - * @param dsiId: DSI ID type - * - * @return RX length - * -*******************************************************************************/ -uint16_t DSI_LPDT_Get_Rx_Length(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - return BL_GET_REG_BITS_VAL(tmpVal, DSI_ST_ESC_RX_LEN); -} - -/****************************************************************************/ /** - * @brief DSI Escape mode send trigger command - * - * @param dsiId: DSI ID type - * - * @param cmd: trigger command - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Send_Trigger_Command(DSI_ID_Type dsiId, uint8_t cmd) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_TRIG, cmd); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI Escape mode send ULPS command - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Send_ULPS_Command(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 2); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI exit ULPS - * - * @param dsiId: DSI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Exit_ULPS(DSI_ID_Type dsiId) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - //DSI_Lane_State_Type state; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_ULPS_EXIT, 1); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - arch_delay_ms(2); -#if 0 - DSI_PHY_HS_Mode_Stop(dsiId); - - do - { - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - } while(state != DSI_LANE_STAT_STOP); - -#endif - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 3); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DSI_CR_ESC_TX_EN); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI config LPDT short packet - * - * @param dsiId: DSI ID type - * - * @param msg: LPDT long message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Config_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 0); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - /*short packet*/ - tmpVal = BL_RD_REG(DSIx, DSI_LPDT_TX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_PDLEN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_VC, msg->virtualChan); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_DI, msg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD0, msg->tx_buf[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD1, msg->tx_buf[1]); - BL_WR_REG(DSIx, DSI_LPDT_TX_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI send LPDT short packet - * - * @param dsiId: DSI ID type - * - * @param msg: DSI message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Send_Short_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - DSI_LPDT_Config_Short_Packet(dsiId, msg); - - DSI_LPDT_Start_Tx(dsiId); - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI config LPDT long packet - * - * @param dsiId: DSI ID type - * - * @param msg: LPDT long message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Config_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - uint32_t tmpVal; - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - DSI_PHY_HS_Mode_Stop(dsiId); - - tmpVal = BL_RD_REG(DSIx, DSI_ESC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_ESC_TX_MODE, 0); - BL_WR_REG(DSIx, DSI_ESC_CONFIG, tmpVal); - - /*long packet*/ - tmpVal = BL_RD_REG(DSIx, DSI_LPDT_TX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_VC, msg->virtualChan); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_DI, msg->dataType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD0, msg->tx_len & 0xff); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_WORD1, (msg->tx_len >> 8) & 0xff); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSI_CR_LPDT_PDLEN, msg->tx_len); - BL_WR_REG(DSIx, DSI_LPDT_TX_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI get tx fifo unoccupied count value - * - * @param dsiId: DSI ID type - * - * @return Tx fifo unoccupied count value - * -*******************************************************************************/ -uint8_t DSI_GetTxFifoCount(DSI_ID_Type dsiId) -{ - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameter */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1), DSI_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief DSI get rx fifo count value - * - * @param dsiId: DSI ID type - * - * @return Rx fifo count value - * -*******************************************************************************/ -uint8_t DSI_GetRxFifoCount(DSI_ID_Type dsiId) -{ - uint32_t DSIx = dsiAddr[dsiId]; - - /* Check the parameter */ - CHECK_PARAM(IS_DSI_ID_TYPE(dsiId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(DSIx, DSI_FIFO_CONFIG_1), DSI_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief DSI full fill FIFO - * - * @param dsiId: DSI ID type - * - * @param data: Data to send buffer - * - * @param len: Data length to send - * - * @return Data length filled - * -*******************************************************************************/ -uint8_t DSI_Full_Fill_FIFO(DSI_ID_Type dsiId, const uint8_t *data, uint16_t len) -{ - uint32_t DSIx = dsiAddr[dsiId]; - const uint8_t *pDataEnd = data + len; - uint8_t filled = 0; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (data < pDataEnd) { - if (DSI_GetTxFifoCount(dsiId) > 0) { - BL_WR_WORD(DSIx + DSI_FIFO_WDATA_OFFSET, BL_RDWD_FRM_BYTEP(data)); - data += 4; - filled += 4; - } else { - return filled; - } - } - - return filled; -} - -/****************************************************************************/ /** - * @brief DSI feed FIFO with data - * - * @param dsiId: DSI ID type - * - * @param data: Data to send buffer - * - * @param len: Data length to send - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Feed_FIFO(DSI_ID_Type dsiId, const uint8_t *data, uint16_t len) -{ - uint32_t timeoutCnt = DSI_TX_TIMEOUT_COUNT; - uint32_t DSIx = dsiAddr[dsiId]; - const uint8_t *pDataEnd = data + len; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (data < pDataEnd) { - if (DSI_GetTxFifoCount(dsiId) > 0) { - BL_WR_WORD(DSIx + DSI_FIFO_WDATA_OFFSET, BL_RDWD_FRM_BYTEP(data)); - timeoutCnt = DSI_TX_TIMEOUT_COUNT; - data += 4; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI Read FIFO - * - * @param dsiId: DSI ID type - * - * @param data: Data to receive buffer - * - * @param len: Data length to receive - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_Read_FIFO(DSI_ID_Type dsiId, uint8_t *data, uint16_t len) -{ - uint32_t DSIx = dsiAddr[dsiId]; - uint8_t *pDataEnd = data + len; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Receive data */ - while (data < pDataEnd && DSI_GetRxFifoCount(dsiId) > 0) { - BL_WRWD_TO_BYTEP(data, BL_RD_WORD(DSIx + DSI_FIFO_RDATA_OFFSET)); - data += 4; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI send LPDT long packet - * - * @param dsiId: DSI ID type - * - * @param msg: DSI message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Send_Long_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - uint8_t filled = 0; - - DSI_LPDT_Config_Long_Packet(dsiId, msg); - - filled = DSI_Full_Fill_FIFO(dsiId, msg->tx_buf, msg->tx_len); - - DSI_LPDT_Start_Tx(dsiId); - - if (filled < msg->tx_len) { - DSI_Feed_FIFO(dsiId, msg->tx_buf + filled, msg->tx_len - filled); - } - - return DSI_Wait_For_Esc_Tx_Done(dsiId); -} - -/****************************************************************************/ /** - * @brief DSI receive packet - * - * @param dsiId: DSI ID type - * - * @param msg: DSI message config - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DSI_LPDT_Recv_Packet(DSI_ID_Type dsiId, DSI_LPDT_MSG_Type *msg) -{ - DSI_Lane_State_Type state; - DSI_INT_Type intStatus; - - /* wait for bus stop */ - do { - DSI_PHY_Get_Lanes_State(dsiId, DSI_LANE_DATA0, &state); - } while (state != DSI_LANE_STAT_STOP); - - /* turn around */ - DSI_PHY_Data_Lane0_TurnAround(dsiId); - - /* start rx */ - DSI_LPDT_Start_Rx(dsiId); - - /* wait for rx finished */ - do { - intStatus = DSI_IntGet(dsiId); - } while (!(intStatus & DSI_INT_LPDT_RX_END)); - DSI_IntClear(dsiId,DSI_INT_LPDT_RX_END); - - msg->rx_len = DSI_LPDT_Get_Rx_Length(dsiId); - - DSI_Read_FIFO(dsiId, msg->rx_buf, msg->rx_len); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSI interrupt function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DSI_IRQHandler(void) -{ - DSI_IntHandler(DSI0_ID); -} -#endif - -/*@} end of group DSI_Public_Functions */ - -/*@} end of group DSI */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c deleted file mode 100644 index f2f25f3783..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2.c +++ /dev/null @@ -1,2029 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2 - * @{ - */ - -/** @defgroup DSP2_Private_Macros - * @{ - */ -#define DSP2_PRINT_LOG 0 -#if DSP2_PRINT_LOG -#include "bflb_platform.h" -#endif - -/* To avoid divide-0 exception in code */ -#define DIV_0_TO_1(a) ((0 == (a)) ? 1 : (a)) - -#define DIV_ROUND(divident, divider) (((divident) + ((divider) >> 1)) / (divider)) - -#define SIGN_EXTEND(x, num_bits) ((((int)(x)) & ((1 << num_bits) - 1)) << (32 - num_bits) >> (32 - num_bits)) - -#define BL_SET_REG_BITS_VAL_2(val, bitname, bitval) \ - (((val)&bitname##_UMSK) | (((uint32_t)(bitval) << bitname##_POS) & bitname##_MSK)) - -#define AE_SRAM_BASE ((uint32_t)0x30019000) /*!< AE status SRAM base address */ -#define AWB_SRAM_BASE ((uint32_t)0x3001c000) /*!< AWB status SRAM base address */ - -#define DSP2_BLC_MAX 1023 -#define DSP2_BLC_MIN 0 - -#define DSP2_BNR_WEIGHT_MAX 64 -#define DSP2_BNR_WEIGHT_MIN 0 -#define DSP2_BNR_LPF_WEIGHT_MAX 16 -#define DSP2_BNR_LPF_WEIGHT_MIN 0 - -#define DSP2_GAIN_MAX 2047 -#define DSP2_GAIN_MIN 0 - -#define DSP2_CCM_MAX 2047 -#define DSP2_CCM_MIN -2048 - -#define DSP2_BRIGHTNESS_MAX 127 -#define DSP2_BRIGHTNESS_MIN -128 - -#define DSP2_CONTRAST_MAX 255 -#define DSP2_CONTRAST_MIN 0 - -#define DSP2_SATURATION_MAX 255 -#define DSP2_SATURATION_MIN 0 - -#define DSP2_NOISE_LEVEL_MAX 63 -#define DSP2_NOISE_LEVEL_MIN 0 - -#define DSP2_NOISE_THRESHOLD_MAX 127 -#define DSP2_NOISE_THRESHOLD_MIN 0 - -#define DSP2_NR_STRENGTH_MAX 15 -#define DSP2_NR_STRENGTH_MIN 0 - -#define DSP2_Edge_Enhance_LEVEL_MAX 127 -#define DSP2_Edge_Enhance_LEVEL_MIN 0 - -#define DSP2_Edge_Enhance_LIMIT_MAX 255 -#define DSP2_Edge_Enhance_LIMIT_MIN 0 - -#define DSP2_Edge_Enhance_HPF_MAX 8 -#define DSP2_Edge_Enhance_HPF_MIN 0 - -#define DSP2_DPC_TH_MAX 255 -#define DSP2_DPC_TH_MIN 0 - -#define DSP2_AE_ROI_START_X_RANGE_MAX 2047 -#define DSP2_AE_ROI_START_Y_RANGE_MAX 2047 -#define DSP2_AE_ROI_WIDTH_RANGE_MAX 2047 -#define DSP2_AE_ROI_WIDTH_RANGE_MIN 32 -#define DSP2_AE_ROI_HEIGHT_RANGE_MAX 2047 -#define DSP2_AE_ROI_HEIGHT_RANGE_MIN 2 - -#define DSP2_AE_GRID_WIDTH_RANGE_MAX 255 -#define DSP2_AE_GRID_WIDTH_RANGE_MIN 32 -#define DSP2_AE_GRID_HEIGHT_RANGE_MAX 255 -#define DSP2_AE_GRID_HEIGHT_RANGE_MIN 2 -#define DSP2_AE_GRID_NUM_X_RANGE_MAX 12 -#define DSP2_AE_GRID_NUM_X_RANGE_MIN 1 -#define DSP2_AE_GRID_NUM_Y_RANGE_MAX 8 -#define DSP2_AE_GRID_NUM_Y_RANGE_MIN 1 - -#define DSP2_AWB_ROI_START_X_RANGE_MAX 2047 -#define DSP2_AWB_ROI_START_Y_RANGE_MAX 2047 -#define DSP2_AWB_ROI_WIDTH_RANGE_MAX 2047 -#define DSP2_AWB_ROI_WIDTH_RANGE_MIN 32 -#define DSP2_AWB_ROI_HEIGHT_RANGE_MAX 2047 -#define DSP2_AWB_ROI_HEIGHT_RANGE_MIN 2 - -#define DSP2_AWB_GRID_WIDTH_RANGE_MAX 255 -#define DSP2_AWB_GRID_WIDTH_RANGE_MIN 32 -#define DSP2_AWB_GRID_HEIGHT_RANGE_MAX 255 -#define DSP2_AWB_GRID_HEIGHT_RANGE_MIN 2 -#define DSP2_AWB_GRID_NUM_X_RANGE_MAX 32 -#define DSP2_AWB_GRID_NUM_X_RANGE_MIN 1 -#define DSP2_AWB_GRID_NUM_Y_RANGE_MAX 32 -#define DSP2_AWB_GRID_NUM_Y_RANGE_MIN 1 - -#define DSP2_AWB_R_MAX_THR_RANGE_MAX 4095 -#define DSP2_AWB_R_MIN_THR_RANGE_MAX 4095 -#define DSP2_AWB_G_MAX_THR_RANGE_MAX 4095 -#define DSP2_AWB_G_MIN_THR_RANGE_MAX 4095 -#define DSP2_AWB_B_MAX_THR_RANGE_MAX 4095 -#define DSP2_AWB_B_MIN_THR_RANGE_MAX 4095 - -#define DSP2_LSC_OFFSET_MAX 127 -#define DSP2_LSC_OFFSET_MIN -128 - -#define DSP2_EE_DIR_SHPNSS_THRESH_MAX 127 -#define DSP2_EE_NO_DIR_SHPNSS_THRESH_MAX 127 -#define DSP2_EE_FLAT_REGION_THRESH_MAX 255 -#define DSP2_EE_TEXTURE_REGION_THRESH_MAX 511 -#define DSP2_EE_EDGE_REGION_THRESH_MAX 65535 - -#define DSP2_EE_STRENGTH_MAX 127 -#define DSP2_EE_NR_STRENGTH_MAX 255 - -#define DSP2_EE_LUMA_WEIGHT_MAX 1023 - -#define DSP2_AE_SRAM_BANK1 (AE_SRAM_BASE) /*!< 0x30019000 */ -#define DSP2_AE_SRAM_BANK2 (AE_SRAM_BASE + (768)) /*!< 0x30019300 */ - -#define DSP2_AWB_SRAM_BANK1 (AWB_SRAM_BASE) /*!< 0x3001c000 */ -#define DSP2_AWB_SRAM_BANK2 (AWB_SRAM_BASE + (1024 * 8)) /*!< 0x3001e000 */ - -#define DSP2_LSC_MAX_MAX 255 -#define DSP2_LSC_MAX_MIN 0 - -#define DSP2_ERROR_ADDR 0xffffffff - -/* For 16bits reg, high 8bits offset 1Byte is low 8bits */ -#define DSP2_REG_H_L_OFFSET 0X1 - -/* Read 16 bits data consits of high 8bits and low 8bits */ -#define BL_RD_16_H_L_REG(addr_h, addr_l) \ - ((BL_RD_BYTE(addr_h)) << 8) + (BL_RD_BYTE(addr_l)) - -#define DSP2_RD_16_H_L_REG(regname_h, regname_l) \ - ((BL_RD_BYTE_REG(DSP2_BASE, regname_h)) << 8) + (BL_RD_BYTE_REG(DSP2_BASE, regname_l)) - -#define IS_BLACK_WHITE_MODE(mode) (mode == BLACK_WHITE_MODE_ON) - -/*@} end of group DSP2_Private_Macros */ - -/** @defgroup DSP2_Private_Types - * @{ - */ -typedef enum { - DSP2_DPC_OFF = 0, - DSP2_DPC_FLY, -} DSP2_DPC_MODE_TYPE; - -typedef enum { - DSP2_HSYNC_INVERT_NORMAL = 0, - DSP2_HSYNC_INVERT_INVERT, -} DSP2_HSYNC_INVERT_TYPE; - -typedef enum { - DSP2_VSYNC_INVERT_NORMAL = 0, - DSP2_VSYNC_INVERT_INVERT, -} DSP2_VSYNC_INVERT_TYPE; - -typedef enum { - DSP2_HCNT_RST_RISING = 0, - DSP2_HCNT_RST_FALLING, -} DSP2_HCNT_RST_TYPE; - -typedef enum { - DSP2_VCNT_RST_RISING = 0, - DSP2_VCNT_RST_FALLING, -} DSP2_VCNT_RST_TYPE; - -typedef enum { - DSP2_VCNT_RST_REVERT_FALLING = 0, - DSP2_VCNT_RST_REVERT_RISING, -} DSP2_VCNT_RST_REVERT_TYPE; - -typedef enum { - DSP2_FHBLK_LINE_OFF = 0, - DSP2_FHBLK_LINE_ON = 1, -} DSP2_FHBLK_LINE_TYPE; - -/*@} end of group DSP2_Private_Types */ - -/** @defgroup DSP2_Private_Variables - * @{ - */ - -/*@} end of group DSP2_Private_Variables */ - -/** @defgroup DSP2_Global_Variables - * @{ - */ - -/*@} end of group DSP2_Global_Variables */ - -/** @defgroup DSP2_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_Private_Fun_Declaration */ - -/** @defgroup DSP2_Private_Functions - * @{ - */ -static uint16_t DSP2_Calc_Total_Width(const DSP2_TG_Cfg_Type *config) -{ - // uint32_t pix_clk = config->pix_clk; - // uint32_t DSP2_clk = config->DSP2_clk; - // uint16_t sns_tot_width = config->total_width; - - return (uint16_t)((uint64_t)config->DSP2_clk / config->total_height / config->fps + 48) & 0xFFFE; - - /* the final total width must be even */ - - // return (uint16_t)((uint64_t)DSP2_clk/1125/25) & 0xFFFE; - // return (uint16_t)((uint64_t)sns_tot_width * DSP2_clk / pix_clk + 48) & 0xFFFE; //TODO: remove magic number -} - -static bool is_LSC_Coeff_Valid(const DSP2_LSC_COEF_S *lsc) -{ - int i; - - const int DSP2_LSC_COEF_LIMIT[LSC_COEF_NUM][2] = { - { -4194304, 4194303 }, /*!< A */ - { -4096, 4095 }, /*!< B */ - { 0, 255 }, /*!< C */ - { -4194304, 4194303 }, /*!< D */ - { -4096, 4095 }, /*!< E */ - { -4194304, 4194303 }, /*!< G */ - }; - - for (i = 0; i < LSC_COEF_NUM; ++i) { - if ((lsc->lsc_coef_r.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_r.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) { - return false; - } - - if ((lsc->lsc_coef_g.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_g.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) { - return false; - } - - if ((lsc->lsc_coef_b.coef[i]) < DSP2_LSC_COEF_LIMIT[i][0] || (lsc->lsc_coef_b.coef[i]) > DSP2_LSC_COEF_LIMIT[i][1]) { - return false; - } - } - - return true; -} - -static int DSP2_Calc_Clamp_Gain(int black_level) -{ - return DIV_ROUND(4095 * 4096, (4095 - black_level)); -} - -/*@} end of group DSP2_Private_Functions */ - -/** @defgroup DSP2_Public_Functions - * @{ - */ - -void DSP2_Init(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_COEFF); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_R_PRE, 77); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_G_PRE, 150); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_YSUM_COEFF_B_PRE, 29); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_COEFF, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_B); - /* yuv output 16bit mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OUT_FORMAT_W, 1); - /* YUYV order */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBCR_SELECT_W, 1); - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_B, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_BL_AWB_GAIN_SEL_W); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_BL_DIGITAL_GAIN_SEL_W); - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING, tmpVal); -} - -void DSP2_Set_TG_Cfg(const DSP2_TG_Cfg_Type *cfg) -{ - dsp2_tg_reg_t *dsp2_tg_reg = (dsp2_tg_reg_t *)DSP2_BASE; - - uint16_t act_start_pixel = 0; - uint16_t act_pixel_width = 0; - uint16_t act_start_line = 0; - uint16_t act_line_height = 0; - - uint16_t out_pixel_width = 0; - uint16_t out_line_height = 0; - - uint16_t out_start_pixel = 0; - uint16_t out_start_line = 0; - - /* TODO: crop the best window */ - if (DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE == cfg->sync_mode_value) { - act_start_pixel = 0; /* hcount reset in rising edge, so H blanking is put after valid line */ - act_pixel_width = cfg->active_width; - act_start_line = 0; - act_line_height = cfg->active_height; - } else { - act_start_pixel = cfg->total_width - cfg->active_width; - act_pixel_width = cfg->active_width; - act_start_line = cfg->total_height - cfg->active_height; - act_line_height = cfg->active_height; - } - - out_pixel_width = cfg->out_width; - out_line_height = cfg->out_height; - - out_start_pixel = (act_pixel_width - out_pixel_width) / 2; - out_start_line = (act_line_height - out_line_height) / 2; - - /* further reduce frame latency by enabling act_vsync reset mode on vsync edge */ - dsp2_tg_reg->dvp_mode.BF.reg_act_vsync_rst_en_w = 1; - - /* set sync mode */ - dsp2_tg_reg->dvp_mode.BF.sync_mode_w = cfg->sync_mode_value; - dsp2_tg_reg->dvp_mode.BF.hsync_in_inv_w = DSP2_HSYNC_INVERT_NORMAL; - /* dvp_tsrc would do vsync invert so vsync pulse is always active low */ - dsp2_tg_reg->dvp_mode.BF.vsync_in_inv_w = DSP2_VSYNC_INVERT_NORMAL; - dsp2_tg_reg->dvp_mode.BF.fhblk_line_on_w = DSP2_FHBLK_LINE_OFF; - - /* note: if vsync invert, vcnt reset mode set 0, means falling - else if vsync not invert, vcont reset mode set 1, also means falling - this value will not open to user now. - */ - if (DSP2_SYNC_MODE_INPUT_VBLANK_NO_TOGGLE == cfg->sync_mode_value) { - /* hcnt reset in rising edge, so H blanking is put after valid line - vcnt reset mode must be 0, to make sure vcnt is reset to 4095 instead of 0. */ - dsp2_tg_reg->dvp_mode.BF.hcnt_rst_mode_w = DSP2_HCNT_RST_RISING; - dsp2_tg_reg->dvp_mode.BF.vcnt_rst_mode_w = DSP2_VCNT_RST_RISING; - } else { - dsp2_tg_reg->dvp_mode.BF.hcnt_rst_mode_w = DSP2_HCNT_RST_FALLING; - dsp2_tg_reg->dvp_mode.BF.vcnt_rst_mode_w = DSP2_HCNT_RST_FALLING; - } - - /* set total pixels and total lines */ - dsp2_tg_reg->total_pixels.BF.total_hpixels_w = - DSP2_Calc_Total_Width(cfg); - - dsp2_tg_reg->total_pixels.BF.total_vlines_w = cfg->total_height; - ; - - /* act start pixel, act pixel width */ - dsp2_tg_reg->act_pixels_1.BF.act_start_pixel_w = act_start_pixel; - dsp2_tg_reg->act_pixels_1.BF.act_pixel_width_w = act_pixel_width; - - /* act start line, act line height */ - dsp2_tg_reg->act_pixels_2.BF.act_start_line_w = act_start_line; - dsp2_tg_reg->act_pixels_2.BF.act_line_height_w = act_line_height; - - /* out start pixel, out pixel width */ - dsp2_tg_reg->fact_pixels_1.BF.fact_start_pixel_w = out_start_pixel; - dsp2_tg_reg->fact_pixels_1.BF.fact_pixel_width_w = out_pixel_width; - - /* out start line, out line height*/ - dsp2_tg_reg->fact_pixels_2.BF.fact_start_line_w = out_start_line; - - dsp2_tg_reg->fact_pixels_2.BF.fact_line_height_w = out_line_height; -} - -int DSP2_Get_Output_Window(BL_Img_Size_T *out_win) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_TG_FACT_PIXELS_1); - out_win->width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_TG_FACT_PIXEL_WIDTH_W); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_TG_FACT_PIXELS_2); - out_win->height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_TG_FACT_LINE_HEIGHT_W); - - return 0; -} - -void DSP2_Set_Bayer_Pattern(const BAYER_PATTERN_E *pattern) -{ - dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE; - - dsp2_front_reg->pattern_mode.BF.pattern_mode_w = 0; - - /* fix issue: bayer pattern highly sensitive to total width setting */ - dsp2_front_reg->pattern_mode.BF.reg_bl_lpid_sel_w = 1; - - if (*pattern == BAYER_PATTERN_BG) { - /* lid invert depends on the total height */ - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 1; - } else if (*pattern == BAYER_PATTERN_RG) { - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 0; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0; - } else if (*pattern == BAYER_PATTERN_GR) { - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0; - } else if (*pattern == BAYER_PATTERN_GB) { - dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 0; - dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 1; - } else { -#if DSP2_PRINT_LOG - MSG("Error bayer pattern!\n"); -#endif - return; - } - - /* hack for CISTA sensor */ - //dsp2_front_reg->pattern_mode.BF.pid_inv_rgb_pre = 1; - //dsp2_front_reg->pattern_mode.BF.lid_inv_rgb_pre = 0; -} - -void DSP2_Set_AE_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE, tmpVal); -} - -void DSP2_Set_AE_Stats_Conf(const dsp2_ae_stats_conf_t *ae_stats_conf) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(ae_stats_conf->roi_start_x, DSP2_AE_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(ae_stats_conf->roi_start_y, DSP2_AE_ROI_START_Y_RANGE_MAX); - CHECK_PARAM_RANGE(ae_stats_conf->roi_width, - DSP2_AE_ROI_WIDTH_RANGE_MIN, DSP2_AE_ROI_WIDTH_RANGE_MAX); - CHECK_PARAM_RANGE(ae_stats_conf->roi_height, - DSP2_AE_ROI_HEIGHT_RANGE_MIN, DSP2_AE_ROI_HEIGHT_RANGE_MAX); - CHECK_PARAM_MIN(ae_stats_conf->grid_width, DSP2_AE_GRID_WIDTH_RANGE_MIN); - CHECK_PARAM_MIN(ae_stats_conf->grid_height, DSP2_AE_GRID_HEIGHT_RANGE_MIN); - CHECK_PARAM_RANGE(ae_stats_conf->grid_num_x, - DSP2_AE_GRID_NUM_X_RANGE_MIN, DSP2_AE_GRID_NUM_X_RANGE_MAX); - CHECK_PARAM_RANGE(ae_stats_conf->grid_num_y, - DSP2_AE_GRID_NUM_Y_RANGE_MIN, DSP2_AE_GRID_NUM_Y_RANGE_MAX); - - /* special check */ - - /* AE ROI must be in the active image region */ - if ((ae_stats_conf->roi_start_x + ae_stats_conf->roi_width > ae_stats_conf->img_width) || - (ae_stats_conf->roi_start_y + ae_stats_conf->roi_height > ae_stats_conf->img_height)) { -#if DSP2_PRINT_LOG - MSG("AE ROI must be in the active image region!\r\n"); -#endif - } - - /* grid width/height must be even number */ - if ((ae_stats_conf->grid_width & 0x1) & (ae_stats_conf->grid_height & 0x1)) { -#if DSP2_PRINT_LOG - MSG("Grid width/height must be even number!\r\n"); -#endif - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_X_PRE, ae_stats_conf->roi_start_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_WIDTH_PRE, ae_stats_conf->roi_width); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_Y_PRE, ae_stats_conf->roi_start_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_HEIGHT_PRE, ae_stats_conf->roi_height); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE, ae_stats_conf->img_width); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE, ae_stats_conf->img_height); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_WIDTH_PRE, ae_stats_conf->grid_width); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_HEIGHT_PRE, ae_stats_conf->grid_height); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_X_MAX_PRE, ae_stats_conf->grid_num_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_Y_MAX_PRE, ae_stats_conf->grid_num_y); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AE_STA_ENABLE_W); - /* AE occupies 2 bank of memory*/ - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_AE_SWITCH_BANK_EN_PRE); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE, tmpVal); -} - -void DSP2_Get_AE_Stats_Conf(dsp2_ae_stats_conf_t *ae_stats_conf) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_X); - ae_stats_conf->roi_start_x = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_X_PRE); - ae_stats_conf->roi_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_WIDTH_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_ROI_Y); - ae_stats_conf->roi_start_y = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_START_Y_PRE); - ae_stats_conf->roi_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_ROI_HEIGHT_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_IMAGE_SIZE); - ae_stats_conf->img_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_WIDTH_PRE); - ae_stats_conf->img_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_IMAGE_HEIGHT_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_GRID_SIZE); - ae_stats_conf->grid_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_WIDTH_PRE); - ae_stats_conf->grid_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_HEIGHT_PRE); - ae_stats_conf->grid_width = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_X_MAX_PRE); - ae_stats_conf->grid_height = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AE_GRID_Y_MAX_PRE); -} - -int DSP2_Get_AE_Stats(int grid_num, uint32_t *data) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_STATUS); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_W_CNT_R); - - buf_addr = (0 == buf_idx) ? DSP2_AE_SRAM_BANK1 : DSP2_AE_SRAM_BANK2; - ARCH_MemCpy4(data, (uint32_t *)(uintptr_t)buf_addr, grid_num * 2); // two word per grid - - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_W_CNT_R); - - if (w_cnt_idx_start != w_cnt_idx_end) { -#if DSP2_PRINT_LOG - MSG("AE statistics overwrite!\n"); -#endif - return -1; - } - - return 0; -} - -void DSP2_Get_AE_Sum(int grid_idx, AE_GRID_DATA_TYPE_E data_type, uint32_t *data) -{ - dsp2_ae_sum_t *grid_array; - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AE_STATUS); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAE_BUF_IDX_R); - - buf_addr = (0 == buf_idx) ? DSP2_AE_SRAM_BANK1 : DSP2_AE_SRAM_BANK2; - grid_array = (dsp2_ae_sum_t *)(uintptr_t)buf_addr; - *data = grid_array[grid_idx].y_sum; -} - -void DSP2_Set_AWB_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_NEW_AWB_STA_ENABLE_W); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_SETTING, tmpVal); -} - -void DSP2_Set_AWB_Stats_Conf(const dsp2_awb_stats_conf_t *awb_stats_conf) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - CHECK_PARAM_MAX(awb_stats_conf->roi_start_x, DSP2_AWB_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->roi_start_y, DSP2_AWB_ROI_START_Y_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->roi_width, DSP2_AWB_ROI_WIDTH_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->roi_height, DSP2_AWB_ROI_HEIGHT_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->grid_num_x, DSP2_AWB_GRID_NUM_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->grid_num_y, DSP2_AWB_GRID_NUM_Y_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->r_max_thr, DSP2_AWB_R_MAX_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->r_min_thr, DSP2_AWB_R_MIN_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->g_max_thr, DSP2_AWB_G_MAX_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->g_min_thr, DSP2_AWB_G_MIN_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->b_max_thr, DSP2_AWB_B_MAX_THR_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->b_min_thr, DSP2_AWB_B_MIN_THR_RANGE_MAX); - - CHECK_PARAM_MIN(awb_stats_conf->grid_width, DSP2_AWB_GRID_WIDTH_RANGE_MIN); - CHECK_PARAM_MIN(awb_stats_conf->grid_height, DSP2_AWB_GRID_HEIGHT_RANGE_MIN); - - /* special check */ - /* AWB ROI must be in the active image region */ - if ((awb_stats_conf->roi_start_x + awb_stats_conf->roi_width > awb_stats_conf->img_width) || - (awb_stats_conf->roi_start_y + awb_stats_conf->roi_height > awb_stats_conf->img_height)) { -#if DSP2_PRINT_LOG - MSG("AWB ROI must be in the active image region!\r\n"); -#endif - } - - /* grid width/height must be even number */ - if ((awb_stats_conf->grid_width & 0x1) & (awb_stats_conf->grid_height & 0x1)) { -#if DSP2_PRINT_LOG - MSG("Grid width/height must be even number!\r\n"); -#endif - } - - dsp2_middle_reg->awb_roi_x.BF.awb_roi_start_x_w = awb_stats_conf->roi_start_x; - dsp2_middle_reg->awb_roi_x.BF.awb_roi_width_w = awb_stats_conf->roi_width; - dsp2_middle_reg->awb_roi_y.BF.awb_roi_start_y_w = awb_stats_conf->roi_start_y; - dsp2_middle_reg->awb_roi_y.BF.awb_roi_height_w = awb_stats_conf->roi_height; - - dsp2_middle_reg->awb_image_size.BF.awb_image_width_w = awb_stats_conf->img_width; - dsp2_middle_reg->awb_image_size.BF.awb_image_height_w = awb_stats_conf->img_height; - - dsp2_middle_reg->awb_grid_size.BF.awb_grid_width_w = awb_stats_conf->grid_width; - dsp2_middle_reg->awb_grid_size.BF.awb_grid_height_w = awb_stats_conf->grid_height; - - dsp2_middle_reg->awb_grid_size.BF.awb_grid_x_max_w = awb_stats_conf->grid_num_x; - dsp2_middle_reg->awb_grid_size.BF.awb_grid_y_max_w = awb_stats_conf->grid_num_y; - - dsp2_middle_reg->awb_r_thre.BF.awb_r_max_thr_w = awb_stats_conf->r_max_thr; - dsp2_middle_reg->awb_r_thre.BF.awb_r_min_thr_w = awb_stats_conf->r_min_thr; - - dsp2_middle_reg->awb_g_thre.BF.awb_g_max_thr_w = awb_stats_conf->g_max_thr; - dsp2_middle_reg->awb_g_thre.BF.awb_g_min_thr_w = awb_stats_conf->g_min_thr; - - dsp2_middle_reg->awb_b_thre.BF.awb_b_max_thr_w = awb_stats_conf->b_max_thr; - dsp2_middle_reg->awb_b_thre.BF.awb_b_min_thr_w = awb_stats_conf->b_min_thr; - - dsp2_middle_reg->awb_setting.BF.new_awb_sta_enable_w = 1; - - /* AWB occupies 2 banks of memory */ - dsp2_middle_reg->awb_setting.BF.awb_switch_bank_en_w = 1; -} - -void DSP2_Get_AWB_Stats_Conf(dsp2_awb_stats_conf_t *awb_stats_conf) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - awb_stats_conf->roi_start_x = dsp2_middle_reg->awb_roi_x.BF.awb_roi_start_x_w; - awb_stats_conf->roi_start_y = dsp2_middle_reg->awb_roi_y.BF.awb_roi_start_y_w; - awb_stats_conf->roi_width = dsp2_middle_reg->awb_roi_x.BF.awb_roi_width_w; - awb_stats_conf->roi_height = dsp2_middle_reg->awb_roi_y.BF.awb_roi_height_w; - awb_stats_conf->img_width = dsp2_middle_reg->awb_image_size.BF.awb_image_width_w; - awb_stats_conf->img_height = dsp2_middle_reg->awb_image_size.BF.awb_image_height_w; - - awb_stats_conf->grid_width = dsp2_middle_reg->awb_grid_size.BF.awb_grid_width_w; - awb_stats_conf->grid_height = dsp2_middle_reg->awb_grid_size.BF.awb_grid_height_w; - - awb_stats_conf->grid_num_x = dsp2_middle_reg->awb_grid_size.BF.awb_grid_x_max_w; - awb_stats_conf->grid_num_y = dsp2_middle_reg->awb_grid_size.BF.awb_grid_y_max_w; -} - -int DSP2_Get_AWB_Stats(int grid_num, uint32_t *data) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_STA_DBG1); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_W_CNT_R); - - buf_addr = (0 == buf_idx) ? DSP2_AWB_SRAM_BANK1 : DSP2_AWB_SRAM_BANK2; - ARCH_MemCpy4(data, (uint32_t *)(uintptr_t)buf_addr, grid_num * 2); // two word per grid - - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_W_CNT_R); - - if (w_cnt_idx_start != w_cnt_idx_end) { -#if DSP2_PRINT_LOG - MSG("AWB statistics overwrite!\n"); -#endif - return -1; - } - - return 0; -} - -void DSP2_Get_AWB_Sum(int grid_idx, RGB_SUM_S *rgb_sum) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_STA_DBG1); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_BLAWB_BUF_IDX_R); - - buf_addr = (0 == buf_idx) ? DSP2_AWB_SRAM_BANK1 : DSP2_AWB_SRAM_BANK2; - - // dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t*)DSP2_BASE; - dsp2_awb_sum_t *grid_array = (dsp2_awb_sum_t *)(uintptr_t)buf_addr; - - rgb_sum->r_sum = grid_array[grid_idx].r_sum; - rgb_sum->g_sum = grid_array[grid_idx].g_sum; - rgb_sum->b_sum = grid_array[grid_idx].b_sum; - - // *buf_idx = dsp2_middle_reg->awb_sta_dbg1.BF.blawb_buf_idx_r; -} - -void DSP2_Get_AWB_ValidGridNum(int *valid_grid_num) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - *valid_grid_num = dsp2_middle_reg->awb_setting.BF.grid_cnt_within_thre_r; -} - -void DSP2_Set_AWB_Gain(const DSP2_RGB_Gain_Type *rgb_gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_R_GAIN_PRE, rgb_gain->r_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GR_GAIN_PRE, rgb_gain->g_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_B_GAIN_PRE, rgb_gain->b_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GB_GAIN_PRE, rgb_gain->g_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN, tmpVal); -} - -void DSP2_Get_AWB_Gain(DSP2_RGB_Gain_Type *rgb_gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_RGR_GAIN); - - rgb_gain->r_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_R_GAIN_PRE); - rgb_gain->g_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_GR_GAIN_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_AWB_BGB_GAIN); - rgb_gain->b_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_AWB_B_GAIN_PRE); -} - -void DSP2_Set_AWB2_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_STAT_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_STAT_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT, tmpVal); -} - -void DSP2_Set_AWB2_Gain_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_GAIN_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE3_AWB2_GAIN_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT, tmpVal); -} - -int DSP2_Get_AWB2_Sum(dsp2_awb2_sum_t *sum) -{ - uint32_t tmpVal; - uint64_t tmpVal64; - uint32_t buf_idx; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_W_CNT_R); - - if (0 == buf_idx) { - sum->r_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R0), DSP2_MIDDLE3_AWB2_R_AVG0_R); - sum->g_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R0), DSP2_MIDDLE3_AWB2_G_AVG0_R); - sum->b_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R1), DSP2_MIDDLE3_AWB2_B_AVG0_R); - sum->white_ratio = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R1), DSP2_MIDDLE3_AWB2_WHITE_RATIO0_R); - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R4); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R5), DSP2_MIDDLE3_AWB2_WHITER_SUML0_R); - sum->white_r_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R7); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R8), DSP2_MIDDLE3_AWB2_WHITEG_SUML0_R); - sum->white_g_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RA); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RB), DSP2_MIDDLE3_AWB2_WHITEB_SUML0_R); - sum->white_b_sum = (tmpVal64 << 9) + tmpVal; - } else { - sum->r_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R2), DSP2_MIDDLE3_AWB2_R_AVG1_R); - sum->g_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R2), DSP2_MIDDLE3_AWB2_G_AVG1_R); - sum->b_avg = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R3), DSP2_MIDDLE3_AWB2_B_AVG1_R); - sum->white_ratio = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R3), DSP2_MIDDLE3_AWB2_WHITE_RATIO1_R); - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R6); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R5), DSP2_MIDDLE3_AWB2_WHITER_SUML1_R); - sum->white_r_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R9); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_R8), DSP2_MIDDLE3_AWB2_WHITEG_SUML1_R); - sum->white_g_sum = (tmpVal64 << 9) + tmpVal; - - tmpVal64 = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RC); - tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_RB), DSP2_MIDDLE3_AWB2_WHITEB_SUML1_R); - sum->white_b_sum = (tmpVal64 << 9) + tmpVal; - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_INT); - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_W_CNT_R); - - // TODO: chang the algo - if (w_cnt_idx_start != w_cnt_idx_end) { -#if DSP2_PRINT_LOG - MSG("w_cnt_idx_start %d, w_cnt_idx_end %d \r\n", w_cnt_idx_start, w_cnt_idx_end); - MSG("AWB2 statistics overwrite!\n"); -#endif - return -1; - } - - return 0; -} - -void DSP2_Set_AWB2_Gain(const DSP2_RGB_Gain_Type *rgb_gain) -{ - DSP2_Set_AWB_Gain(rgb_gain); - // uint32_t tmpVal; - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_RGAIN_PRE, rgb_gain->r_gain); - // BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1, tmpVal); - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_GGAIN_PRE, rgb_gain->g_gain); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BGAIN_PRE, rgb_gain->b_gain); - // BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2, tmpVal); -} - -void DSP2_Get_AWB2_Gain(DSP2_RGB_Gain_Type *rgb_gain) -{ - DSP2_Get_AWB_Gain(rgb_gain); - // uint32_t tmpVal; - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1); - // rgb_gain->r_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_RGAIN_PRE); - - // tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN2); - // rgb_gain->g_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_GGAIN_PRE); - // rgb_gain->b_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_BGAIN_PRE); -} - -void DSP2_Set_AWB2_Stats_Conf(const dsp2_awb2_stats_conf_t *awb_stats_conf) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(awb_stats_conf->stat_x_min, DSP2_AWB_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->stat_x_max, DSP2_AWB_ROI_START_X_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->stat_y_min, DSP2_AWB_ROI_START_Y_RANGE_MAX); - CHECK_PARAM_MAX(awb_stats_conf->stat_y_max, DSP2_AWB_ROI_START_Y_RANGE_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_XAXIS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_X_MIN_PRE, awb_stats_conf->stat_x_min); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_X_MAX_PRE, awb_stats_conf->stat_x_max); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_XAXIS, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_YAXIS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_Y_MIN_PRE, awb_stats_conf->stat_y_min); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_Y_MAX_PRE, awb_stats_conf->stat_y_max); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_YAXIS, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_PIXEL_NUM_PRE, awb_stats_conf->stat_pixel_num); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_PIXEL_NUM, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_GGAIN_PRE, awb_stats_conf->stat_g_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_RGAIN_PRE, awb_stats_conf->stat_r_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_STAT_BGAIN_PRE, awb_stats_conf->stat_b_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_VGAIN_PRE, awb_stats_conf->stat_v_gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_UGAIN_PRE, awb_stats_conf->stat_u_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_GAIN3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH1_PRE, awb_stats_conf->y_th[1]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH2_PRE, awb_stats_conf->y_th[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH3_PRE, awb_stats_conf->y_th[3]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH4_PRE, awb_stats_conf->y_th[4]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YTH0_PRE, awb_stats_conf->y_th[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT2_PRE, awb_stats_conf->y_weight[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT3_PRE, awb_stats_conf->y_weight[3]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT4_PRE, awb_stats_conf->y_weight[4]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT0_PRE, awb_stats_conf->y_weight[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_YWEIGHT1_PRE, awb_stats_conf->y_weight[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE4_PRE, awb_stats_conf->y_slope[4]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE3_PRE, awb_stats_conf->y_slope[3]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE2_PRE, awb_stats_conf->y_slope[2]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L4); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE1_PRE, awb_stats_conf->y_slope[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_YSLOPE0_PRE, awb_stats_conf->y_slope[0]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_L4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C0); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG4_PRE, awb_stats_conf->u[4]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG5_PRE, awb_stats_conf->u[5]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG6_PRE, awb_stats_conf->u[6]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG7_PRE, awb_stats_conf->u[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C1); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG0_PRE, awb_stats_conf->u[0]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG1_PRE, awb_stats_conf->u[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG2_PRE, awb_stats_conf->u[2]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG3_PRE, awb_stats_conf->u[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C2); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG4_PRE, awb_stats_conf->v[4]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG5_PRE, awb_stats_conf->v[5]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG6_PRE, awb_stats_conf->v[6]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_VREG7_PRE, awb_stats_conf->v[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG0_PRE, awb_stats_conf->v[0]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG1_PRE, awb_stats_conf->v[1]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG2_PRE, awb_stats_conf->v[2]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE3_AWB2_UREG3_PRE, awb_stats_conf->v[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH4_PRE, awb_stats_conf->c_th[4]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH5_PRE, awb_stats_conf->c_th[5]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH6_PRE, awb_stats_conf->c_th[6]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH7_PRE, awb_stats_conf->c_th[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH0_PRE, awb_stats_conf->c_th[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH1_PRE, awb_stats_conf->c_th[1]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH2_PRE, awb_stats_conf->c_th[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CTH3_PRE, awb_stats_conf->c_th[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C5, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE4_PRE, awb_stats_conf->c_slope[4]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE5_PRE, awb_stats_conf->c_slope[5]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE6_PRE, awb_stats_conf->c_slope[6]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE7_PRE, awb_stats_conf->c_slope[7]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C6, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE0_PRE, awb_stats_conf->c_slope[0]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE1_PRE, awb_stats_conf->c_slope[1]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE2_PRE, awb_stats_conf->c_slope[2]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE3_AWB2_CSLOPE3_PRE, awb_stats_conf->c_slope[3]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE3_AWB2_STA_C7, tmpVal); -} - -void DSP2_Set_RB_Gain(const DSP2_RB_Gain_Type *rb_gain) -{ - DSP2_RGB_Gain_Type rgb_gain; - - rgb_gain.r_gain = rb_gain->r_gain; - rgb_gain.g_gain = 4096; - rgb_gain.b_gain = rb_gain->b_gain; - - DSP2_Set_AWB_Gain(&rgb_gain); -} - -int DSP2_Set_BLC(const DSP2_CLAMP_S *clamp) -{ - dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE; - - CHECK_PARAM_RANGE(clamp->clamp_r, DSP2_BLC_MIN, DSP2_BLC_MAX); - CHECK_PARAM_RANGE(clamp->clamp_gr, DSP2_BLC_MIN, DSP2_BLC_MAX); - CHECK_PARAM_RANGE(clamp->clamp_gb, DSP2_BLC_MIN, DSP2_BLC_MAX); - CHECK_PARAM_RANGE(clamp->clamp_b, DSP2_BLC_MIN, DSP2_BLC_MAX); - - dsp2_front_reg->clamp_R_Gr.BF.clp_R_pre = clamp->clamp_r; - dsp2_front_reg->clamp_R_Gr.BF.clp_Gr_pre = clamp->clamp_gr; - dsp2_front_reg->clamp_B_Gb.BF.clp_Gb_pre = clamp->clamp_gb; - dsp2_front_reg->clamp_B_Gb.BF.clp_B_pre = clamp->clamp_b; - - dsp2_front_reg->gain_R_G.BF.rgain1_pre = 128; - dsp2_front_reg->gain_R_G.BF.ggain1_pre = 128; - dsp2_front_reg->gain_B.BF.bgain1_pre = 128; - - /* compensate back the lost dynamic range for bayer image */ - dsp2_front_reg->clp_rgr_gain.BF.clp_gain_en_pre = 1; - dsp2_front_reg->clp_rgr_gain.BF.clp_r_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_r); - dsp2_front_reg->clp_rgr_gain.BF.clp_gr_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_gr); - dsp2_front_reg->clp_bgb_gain.BF.clp_gb_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_gb); - dsp2_front_reg->clp_bgb_gain.BF.clp_b_gain_pre = DSP2_Calc_Clamp_Gain(clamp->clamp_b); - - return 0; -} - -int DSP2_Get_BLC(DSP2_CLAMP_S *clamp) -{ - dsp2_front_reg_t *dsp2_front_reg = (dsp2_front_reg_t *)DSP2_BASE; - - clamp->clamp_r = dsp2_front_reg->clamp_R_Gr.BF.clp_R_pre; - clamp->clamp_gr = dsp2_front_reg->clamp_R_Gr.BF.clp_Gr_pre; - clamp->clamp_gb = dsp2_front_reg->clamp_B_Gb.BF.clp_Gb_pre; - clamp->clamp_b = dsp2_front_reg->clamp_B_Gb.BF.clp_B_pre; - - return 0; -} - -void DSP2_Set_DPC_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_FLY); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_OFF); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal); -} - -void DSP2_Enable_DPC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_FLY); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal); -} - -void DSP2_Disable_DPC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DEFECT_CORRECT_MODE_W, DSP2_DPC_OFF); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DEFECT_SETTING, tmpVal); -} - -int DSP2_Set_Defect_Correction_Enhance_Group(const DSP2_DPC_ENHANCE_GROUP_TYPE *value) -{ - int i; - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - for (i = 0; i < DSP2_DPC_Enhance_Num; i++) { - if ((DISABLE != value->data[i]) && (ENABLE != value->data[i])) { - return -1; - } - } - - dsp2_middle_reg->defect_setting.BF.resolution_enhance1_w = value->data[DSP2_DPC_Enhance1]; - dsp2_middle_reg->defect_setting.BF.resolution_enhance2_w = value->data[DSP2_DPC_Enhance2]; - dsp2_middle_reg->defect_setting.BF.resolution_enhance3_w = value->data[DSP2_DPC_Enhance3]; - - return 0; -} - -int DSP2_Get_Defect_Correction_Enhance_Group(DSP2_DPC_ENHANCE_GROUP_TYPE *value) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - value->data[DSP2_DPC_Enhance1] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance1_w; - value->data[DSP2_DPC_Enhance2] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance2_w; - value->data[DSP2_DPC_Enhance3] = (BL_Fun_Type)dsp2_middle_reg->defect_setting.BF.resolution_enhance3_w; - - return 0; -} - -int DSP2_Set_Defect_Correction_Threshold_Group(const DSP2_DPC_THRESHOLD_GROUP_TYPE *value) -{ - int i; - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - for (i = 0; i < DSP2_DPC_th_Num; i++) { - CHECK_PARAM_RANGE(value->data[i], DSP2_DPC_TH_MIN, DSP2_DPC_TH_MAX); - } - - dsp2_middle_reg->defect_th_A.BF.defect_th1_w = value->data[DSP2_DPC_th1]; - dsp2_middle_reg->defect_th_A.BF.defect_th2_w = value->data[DSP2_DPC_th2]; - dsp2_middle_reg->defect_th_A.BF.defect_th3_w = value->data[DSP2_DPC_th3]; - dsp2_middle_reg->defect_th_A.BF.defect_th4_w = value->data[DSP2_DPC_th4]; - dsp2_middle_reg->defect_th_B.BF.defect_th5_w = value->data[DSP2_DPC_th5]; - - return 0; -} - -int DSP2_Get_Defect_Correction_Threshold_Group(DSP2_DPC_THRESHOLD_GROUP_TYPE *value) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - value->data[DSP2_DPC_th1] = dsp2_middle_reg->defect_th_A.BF.defect_th1_w; - value->data[DSP2_DPC_th2] = dsp2_middle_reg->defect_th_A.BF.defect_th2_w; - value->data[DSP2_DPC_th3] = dsp2_middle_reg->defect_th_A.BF.defect_th3_w; - value->data[DSP2_DPC_th4] = dsp2_middle_reg->defect_th_A.BF.defect_th4_w; - value->data[DSP2_DPC_th5] = dsp2_middle_reg->defect_th_B.BF.defect_th5_w; - - return 0; -} - -void DSP2_Set_BNR_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); -} - -void DSP2_Get_BNR_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_MIDDLE4_BNR_EN_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -/* - Set/Get BNR Weight - value range: 0~64 -*/ -void DSP2_Set_BNR_Weight(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_BNR_WEIGHT_MIN, DSP2_BNR_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_BNR_WEIGHT_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); -} - -void DSP2_Get_BNR_Weight(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_BNR_WEIGHT_PRE); -} - -/* - Set/Get BNR LPF Weight - value range: 0~16 -*/ -void DSP2_Set_BNR_LPF_Weight(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_BNR_LPF_WEIGHT_MIN, DSP2_BNR_LPF_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_LPF_WEIGHT_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); -} - -void DSP2_Get_BNR_LPF_Weight(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_LPF_WEIGHT_PRE); -} - -void DSP2_Set_BNR_Threshold(const DSP2_BNR_THRESHOLD_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_B_PRE, value->th_base_b); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_G_PRE, value->th_base_g); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_R_PRE, value->th_base_r); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_B_PRE, value->th_slope_b); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_G_PRE, value->th_slope_g); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_R_PRE, value->th_slope_r); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_SLOPE_GAIN_PRE, value->slope_gain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2, tmpVal); -} - -void DSP2_Get_BNR_Threshold(DSP2_BNR_THRESHOLD_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_0); - value->th_base_b = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_B_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_1); - value->th_base_g = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_G_PRE); - value->th_base_r = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_BASE_R_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_2); - value->th_slope_b = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_B_PRE); - value->th_slope_g = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_G_PRE); - value->th_slope_r = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_TH_SLOPE_R_PRE); - value->slope_gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_SLOPE_GAIN_PRE); -} - -void DSP2_Set_BNR_Fallback(const DSP2_BNR_FALLBACK_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LEVEL_PRE, value->fb_level); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE, value->fb_lpf_weight); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3, tmpVal); -} - -void DSP2_Get_BNR_Fallback(DSP2_BNR_FALLBACK_TYPE *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE4_BNR_CONFIG_3); - value->fb_lpf_weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LPF_WEIGHT_PRE); - value->fb_level = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE4_FB_LEVEL_PRE); -} - -void DSP2_Set_LSC_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - } - - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal); -} - -void DSP2_Enable_LSC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal); -} - -void DSP2_Disable_LSC(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MIDDLE_LSC_ON_W); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING, tmpVal); -} - -void DSP2_Get_LSC_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_SETTING); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_MIDDLE_LSC_ON_W)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -/* - xoffset and yoffset caculated by active and out window - */ -int DSP2_Set_LSC_Offset(int xoffset, int yoffset) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - CHECK_PARAM_RANGE(xoffset, DSP2_LSC_OFFSET_MIN, DSP2_LSC_OFFSET_MAX); - CHECK_PARAM_RANGE(yoffset, DSP2_LSC_OFFSET_MIN, DSP2_LSC_OFFSET_MAX); - - dsp2_middle_reg->LSC_setting.BF.X_offset_w = xoffset; - dsp2_middle_reg->LSC_setting.BF.Y_offset_w = yoffset; - - return 0; -} - -int DSP2_Set_LSC_Coeff(const DSP2_LSC_COEF_S *lsc) -{ - uint32_t tmpVal; - - if (!is_LSC_Coeff_Valid(lsc)) { - return -1; - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_ACOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_A]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_BCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_B]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_ECOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_E]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_CCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_C]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_DCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_D]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_R_GCOEFF_W, lsc->lsc_coef_r.coef[LSC_COEF_G]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_ACOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_A]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_BCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_B]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_ECOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_E]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_CCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_C]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_DCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_D]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_G_GCOEFF_W, lsc->lsc_coef_g.coef[LSC_COEF_G]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_ACOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_A]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_BCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_B]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_ECOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_E]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_CCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_C]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_DCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_D]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_MIDDLE_B_GCOEFF_W, lsc->lsc_coef_b.coef[LSC_COEF_G]); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G, tmpVal); - - return 0; -} - -int DSP2_Get_LSC_Coeff(DSP2_LSC_COEF_S *lsc) -{ - uint32_t tmpVal; - - /* channel R */ - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_A); - lsc->lsc_coef_r.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_ACOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_BE); - lsc->lsc_coef_r.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_BCOEFF_W), 13); - lsc->lsc_coef_r.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_ECOEFF_W), 13); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_CD); - lsc->lsc_coef_r.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_CCOEFF_W); - lsc->lsc_coef_r.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_DCOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_R_G); - lsc->lsc_coef_r.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_R_GCOEFF_W), 23); - - /* channel G */ - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_A); - lsc->lsc_coef_g.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_ACOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_BE); - lsc->lsc_coef_g.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_BCOEFF_W), 13); - lsc->lsc_coef_g.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_ECOEFF_W), 13); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_CD); - lsc->lsc_coef_g.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_CCOEFF_W); - lsc->lsc_coef_g.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_DCOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_G_G); - lsc->lsc_coef_g.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_G_GCOEFF_W), 23); - - /* channel B */ - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_A); - lsc->lsc_coef_b.coef[LSC_COEF_A] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_ACOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_BE); - lsc->lsc_coef_b.coef[LSC_COEF_B] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_BCOEFF_W), 13); - lsc->lsc_coef_b.coef[LSC_COEF_E] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_ECOEFF_W), 13); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_CD); - lsc->lsc_coef_b.coef[LSC_COEF_C] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_CCOEFF_W); - lsc->lsc_coef_b.coef[LSC_COEF_D] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_DCOEFF_W), 23); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_LSC_COEFF_B_G); - lsc->lsc_coef_b.coef[LSC_COEF_G] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_B_GCOEFF_W), 23); - - return 0; -} - -int DSP2_Set_LSC_Max(const DSP2_LSC_MAX_S *lsc_max) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - CHECK_PARAM_RANGE(lsc_max->max_r, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX); - CHECK_PARAM_RANGE(lsc_max->max_g, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX); - CHECK_PARAM_RANGE(lsc_max->max_b, DSP2_LSC_MAX_MIN, DSP2_LSC_MAX_MAX); - - dsp2_middle_reg->MAX_R_G.BF.MAXR_w = lsc_max->max_r; - dsp2_middle_reg->MAX_R_G.BF.MAXG_w = lsc_max->max_g; - dsp2_middle_reg->MAX_B.BF.MAXB_w = lsc_max->max_b; - - return 0; -} - -int DSP2_Get_LSC_Max(DSP2_LSC_MAX_S *lsc_max) -{ - dsp2_middle_reg_t *dsp2_middle_reg = (dsp2_middle_reg_t *)DSP2_BASE; - - lsc_max->max_r = dsp2_middle_reg->MAX_R_G.BF.MAXR_w; - lsc_max->max_g = dsp2_middle_reg->MAX_R_G.BF.MAXG_w; - lsc_max->max_b = dsp2_middle_reg->MAX_B.BF.MAXB_w; - - return 0; -} - -void DSP2_Set_Digital_Gain(uint16_t dgain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_RGR_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_GR_GAIN_PRE, dgain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_R_GAIN_PRE, dgain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_RGR_GAIN, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_BGB_GAIN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_GB_GAIN_PRE, dgain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MIDDLE_DIGITAL_B_GAIN_PRE, dgain); - BL_WR_REG(DSP2_BASE, DSP2_MIDDLE_DIGITAL_BGB_GAIN, tmpVal); -} - -void DSP2_Set_CCM_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0, tmpVal); -} - -void DSP2_Get_CCM_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_OFFSET_0); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_CC_ENABLE_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -void DSP2_Set_CCM_Coef(const DSP2_CCM_COEF_S *ccm) -{ - int i; - uint32_t tmpVal; - - for (i = 0; i < CCM_COEF_NUM; i++) { - CHECK_PARAM_RANGE(ccm->ccm_coef[i], DSP2_CCM_MIN, DSP2_CCM_MAX); - } - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX00_PRE, ccm->ccm_coef[DSP2_CCM_11]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX01_PRE, ccm->ccm_coef[DSP2_CCM_12]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX02_PRE, ccm->ccm_coef[DSP2_CCM_13]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX10_PRE, ccm->ccm_coef[DSP2_CCM_21]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX11_PRE, ccm->ccm_coef[DSP2_CCM_22]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX12_PRE, ccm->ccm_coef[DSP2_CCM_23]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX20_PRE, ccm->ccm_coef[DSP2_CCM_31]); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX21_PRE, ccm->ccm_coef[DSP2_CCM_32]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CC_MATRIX22_PRE, ccm->ccm_coef[DSP2_CCM_33]); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX, tmpVal); -} - -void DSP2_Get_CCM_Coef(DSP2_CCM_COEF_S *ccm) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_0); - ccm->ccm_coef[DSP2_CCM_11] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX00_PRE), DSP2_BLBACK_CC_MATRIX00_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_12] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX01_PRE), DSP2_BLBACK_CC_MATRIX01_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_1); - ccm->ccm_coef[DSP2_CCM_13] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX02_PRE), DSP2_BLBACK_CC_MATRIX02_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_21] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX10_PRE), DSP2_BLBACK_CC_MATRIX10_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_2); - ccm->ccm_coef[DSP2_CCM_22] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX11_PRE), DSP2_BLBACK_CC_MATRIX11_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_23] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX12_PRE), DSP2_BLBACK_CC_MATRIX12_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_MATRIX_3); - ccm->ccm_coef[DSP2_CCM_31] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX20_PRE), DSP2_BLBACK_CC_MATRIX20_PRE_LEN); - ccm->ccm_coef[DSP2_CCM_32] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX21_PRE), DSP2_BLBACK_CC_MATRIX21_PRE_LEN); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX); - ccm->ccm_coef[DSP2_CCM_33] = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CC_MATRIX22_PRE), DSP2_BLBACK_CC_MATRIX22_PRE_LEN); -} - -void DSP2_Set_Gamma_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A, tmpVal); -} - -void DSP2_Get_Gamma_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_GAMMA_A); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_BL_GAMMA_EN_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -void DSP2_Set_Gamma_Coef(const DSP2_Gamma_Curve_Type *gamma_curve) -{ - ARCH_MemCpy4((uint32_t *)(DSP2_BASE + DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET), (uint32_t *)&gamma_curve->curve_coef[0], - GAMMA_COEF_NUM / 2); -} - -void DSP2_Get_Gamma_Coef(DSP2_Gamma_Curve_Type *gamma_curve) -{ - ARCH_MemCpy4((uint32_t *)&gamma_curve->curve_coef[0], (uint32_t *)(DSP2_BASE + DSP2_BLBACK_BL_GAMMA_TABLE_1_OFFSET), - GAMMA_COEF_NUM / 2); -} - -/* - should not change, yuv range should change in yuv adjust module -*/ -void DSP2_Init_Color_Enhancement() -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_0); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX00_PRE, 0x99); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX01_PRE, 0x12D); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX02_PRE, 0x3A); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CC_CE_MATRIX, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_1); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX10_PRE, 0xFA9); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX11_PRE, 0xF57); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_2); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX12_PRE, 0x100); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX20_PRE, 0x100); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_3); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX21_PRE, 0xF29); - tmpVal = BL_SET_REG_BITS_VAL_2(tmpVal, DSP2_BLBACK_CE_MATRIX22_PRE, 0xFD7); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CE_MATRIX_3, tmpVal); -} - -void DSP2_Set_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE type) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_YUV_CONV_TYPE(type)); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CONV_MODE_W, type); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE, tmpVal); -} - -void DSP2_Get_YUV_Conv_Mode(DSP2_YUV_CONV_TYPE *type) -{ - *type = BL_GET_REG_BITS_VAL(BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CONV_MODE), DSP2_BLBACK_CONV_MODE_W); -} - -void DSP2_Set_Brightness(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_BRIGHTNESS_MIN, DSP2_BRIGHTNESS_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YBRIGHTNESS_W, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal); -} - -void DSP2_Get_Brightness(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - *value = SIGN_EXTEND(BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YBRIGHTNESS_W), DSP2_BLBACK_YBRIGHTNESS_W_LEN); -} - -void DSP2_Set_Contrast(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_CONTRAST_MIN, DSP2_CONTRAST_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YCONTRAST_W, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal); -} - -void DSP2_Get_Contrast(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_YCONTRAST_W); -} - -void DSP2_Set_Saturation(const DSP2_SATURATION_S *saturation) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(saturation->saturation_cb, DSP2_SATURATION_MAX); - CHECK_PARAM_MAX(saturation->saturation_cr, DSP2_SATURATION_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBSATURATION_PRE, saturation->saturation_cb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CRSATURATION_PRE, saturation->saturation_cr); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A, tmpVal); -} - -void DSP2_Get_Saturation(DSP2_SATURATION_S *saturation) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_YUVC_A); - saturation->saturation_cb = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CBSATURATION_PRE); - saturation->saturation_cr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CRSATURATION_PRE); -} - -void DSP2_Set_Noise_Level(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_NOISE_LEVEL_MIN, DSP2_NOISE_LEVEL_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NOISE_LEVEL_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal); -} - -void DSP2_Get_Noise_Level(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NOISE_LEVEL_PRE); -} - -void DSP2_Set_2D_NR(int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_NR_STRENGTH_MIN, DSP2_NR_STRENGTH_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_2D_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal); -} - -void DSP2_Get_2D_NR(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_2D_PRE); -} - -void DSP2_Set_3D_NR(const int value) -{ - uint32_t tmpVal; - - CHECK_PARAM_RANGE(value, DSP2_NR_STRENGTH_MIN, DSP2_NR_STRENGTH_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_3D_PRE, value); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_DNR_A, tmpVal); -} - -void DSP2_Get_3D_NR(int *value) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_DNR_A); - *value = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FILT_STRENGTH_3D_PRE); -} - -void DSP2_Set_EE_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_Enable_EE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_Disable_EE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_EE_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_EnableEEOverShoot(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_OVRSHT_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_DisableEEOverShoot(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_OVRSHT_EB_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); -} - -void DSP2_Set_EE_Thresh(const DSP2_EE_Thresh_Type *threshCfg) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(threshCfg->dirShpnessThresh, DSP2_EE_DIR_SHPNSS_THRESH_MAX); - CHECK_PARAM_MAX(threshCfg->noDirShpnessThresh, DSP2_EE_NO_DIR_SHPNSS_THRESH_MAX); - CHECK_PARAM_RANGE(threshCfg->textureThresh, (threshCfg->flatThresh + 1), DSP2_EE_TEXTURE_REGION_THRESH_MAX); - CHECK_PARAM_MIN(threshCfg->edgeThresh, (threshCfg->textureThresh + 1)); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_TXT_THR_PRE, threshCfg->textureThresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH1_PRE, threshCfg->dirShpnessThresh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH2_PRE, threshCfg->noDirShpnessThresh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FLAT_THR_PRE, threshCfg->flatThresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - ; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_EDGE_THR_PRE, threshCfg->edgeThresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3, tmpVal); -} - -void DSP2_Get_EE_Thresh(DSP2_EE_Thresh_Type *threshCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_0); - threshCfg->textureThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_TXT_THR_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_1); - threshCfg->dirShpnessThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH1_PRE); - threshCfg->noDirShpnessThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_THRESH2_PRE); - threshCfg->flatThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_FLAT_THR_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - threshCfg->edgeThresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_EDGE_THR_PRE); -} - -void DSP2_Set_EE_Strength(const DSP2_EE_Str_Type *strCfg) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(strCfg->posEdgeOvrshtStr, DSP2_EE_STRENGTH_MAX); - CHECK_PARAM_MAX(strCfg->negEdgeOvrshtStr, DSP2_EE_STRENGTH_MAX); - CHECK_PARAM_MAX(strCfg->posEdgeStr, DSP2_EE_STRENGTH_MAX); - CHECK_PARAM_MAX(strCfg->negEdgeStr, DSP2_EE_STRENGTH_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_POS_PRE, strCfg->posEdgeOvrshtStr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_NEG_PRE, strCfg->negEdgeOvrshtStr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_POSEE_STR_PRE, strCfg->posEdgeStr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NEGEE_STR_PRE, strCfg->negEdgeStr); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - ; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NR_STR_PRE, strCfg->nrStr); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3, tmpVal); -} - -void DSP2_Get_EE_Strength(DSP2_EE_Str_Type *strCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_2); - strCfg->posEdgeOvrshtStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_POS_PRE); - strCfg->negEdgeOvrshtStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_OVRSHT_NEG_PRE); - strCfg->posEdgeStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_POSEE_STR_PRE); - strCfg->negEdgeStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NEGEE_STR_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_BLEE_3); - ; - strCfg->nrStr = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_NR_STR_PRE); -} - -void DSP2_Set_EE_LumaWeight(const DSP2_EE_Luma_Weight_Type *lumaWgtCfg) -{ - int i; - uint32_t tmpVal; - uint32_t tmpAddr = DSP2_BASE + DSP2_BLBACK_BLEE_4_OFFSET; - - for (i = 0; i < DSP2_EE_LUMA_WEIGHT_NUM; i += 2, tmpAddr += 4) { - CHECK_PARAM_MAX(lumaWgtCfg->lumaWgtTbl[i], DSP2_EE_LUMA_WEIGHT_MAX); - CHECK_PARAM_MAX(lumaWgtCfg->lumaWgtTbl[i + 1], DSP2_EE_LUMA_WEIGHT_MAX); - tmpVal = BL_RD_WORD(tmpAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT0_PRE, lumaWgtCfg->lumaWgtTbl[i]); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT1_PRE, lumaWgtCfg->lumaWgtTbl[i + 1]); - BL_WR_WORD(tmpAddr, tmpVal); - } -} - -void DSP2_Get_EE_LumaWeight(DSP2_EE_Luma_Weight_Type *lumaWgtCfg) -{ - int i; - uint32_t tmpVal; - uint32_t tmpAddr = DSP2_BASE + DSP2_BLBACK_BLEE_4_OFFSET; - - for (i = 0; i < DSP2_EE_LUMA_WEIGHT_NUM; i += 2, tmpAddr += 4) { - tmpVal = BL_RD_WORD(tmpAddr); - lumaWgtCfg->lumaWgtTbl[i] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT0_PRE); - lumaWgtCfg->lumaWgtTbl[i + 1] = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_LUMA_WGT1_PRE); - } -} - -void DSP2_Set_ChromaSuppress_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Enable_ChromaSuppress(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Disable_ChromaSuppress(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CS2_ENABLE_PRE); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Set_ChromaSuppress(const DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GAIN_PRE, chromaSupprCfg->gain); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_WEIGHT_PRE, chromaSupprCfg->weight); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GREY_TH_PRE, chromaSupprCfg->gain_thresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_CS2, tmpVal); -} - -void DSP2_Get_ChromaSuppress(DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_CS2); - chromaSupprCfg->gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GAIN_PRE); - chromaSupprCfg->weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_WEIGHT_PRE); - chromaSupprCfg->gain_thresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CS2_GREY_TH_PRE); -} - -/*@} end of group DSP2_Public_Functions */ - -/*@} end of group DSP2 */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c deleted file mode 100644 index 67b078763f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_axi_ctrl.c +++ /dev/null @@ -1,234 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_axi_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2_axi_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_AXI_CTRL - * @{ - */ - -/** @defgroup DSP2_AXI_CTRL_Private_Macros - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Macros */ - -/** @defgroup DSP2_AXI_CTRL_Private_Types - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Types */ - -/** @defgroup DSP2_AXI_CTRL_Private_Variables - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Variables */ - -/** @defgroup DSP2_AXI_CTRL_Global_Variables - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Global_Variables */ - -/** @defgroup DSP2_AXI_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Fun_Declaration */ - -/** @defgroup DSP2_AXI_CTRL_Private_Functions - * @{ - */ - -/*@} end of group DSP2_AXI_CTRL_Private_Functions */ - -/** @defgroup DSP2_AXI_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief 3DNR init function - * - * @param dsp23DNRCfg: 3DNR configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Init(DSP2_3DNR_Cfg_Type *dsp23DNRCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_3DNR_BURST_TYPE(dsp23DNRCfg->burst)); - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_AXI_CTRL_REG_XLEN, dsp23DNRCfg->burst); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, tmpVal); - - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_HADDR_START_ADDRESS, dsp23DNRCfg->memStart); - - /*Set memory brust size */ - switch (dsp23DNRCfg->burst) { - case DSP2_3DNR_BURST_TYPE_SINGLE: - tmpVal = dsp23DNRCfg->memSize / 8; - break; - - case DSP2_3DNR_BURST_TYPE_INCR4: - tmpVal = dsp23DNRCfg->memSize / 32; - break; - - case DSP2_3DNR_BURST_TYPE_INCR8: - tmpVal = dsp23DNRCfg->memSize / 64; - break; - - case DSP2_3DNR_BURST_TYPE_INCR16: - tmpVal = dsp23DNRCfg->memSize / 128; - break; - - case DSP2_3DNR_BURST_TYPE_INCR32: - tmpVal = dsp23DNRCfg->memSize / 256; - break; - - case DSP2_3DNR_BURST_TYPE_INCR64: - tmpVal = dsp23DNRCfg->memSize / 512; - break; - - default: - tmpVal = 0; - break; - } - - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_MEMORY_BURST_COUNT, tmpVal); - - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_HSYNC_CONTROL, dsp23DNRCfg->hsyncStart << 16 | dsp23DNRCfg->hsyncEnd); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_VSYNC_CONTROL, dsp23DNRCfg->vsyncStart << 16 | dsp23DNRCfg->vsyncEnd); -} - -/****************************************************************************/ /** - * @brief 3DNR enable function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_ENABLE)); -} - -/****************************************************************************/ /** - * @brief 3DNR disable function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_CLR_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_ENABLE)); -} - -/****************************************************************************/ /** - * @brief 3DNR clear write fifo overflow error function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Clear_Write_Overflow(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_OVERFLOW_CLR)); -} - -/****************************************************************************/ /** - * @brief 3DNR clear read fifo drain error function - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_3DNR_Clear_Read_Drain(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL); - BL_WR_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_CONTROL, BL_SET_REG_BIT(tmpVal, DSP2_AXI_CTRL_REG_DRAIN_CLR)); -} - -/****************************************************************************/ /** - * @brief 3DNR get write and read status function - * - * @param dsp23DNRStatus: 3DNR write and read status type - * - * @return Set or reset - * -*******************************************************************************/ -BL_Sts_Type DSP2_3DNR_Get_status(DSP2_3DNR_Status_Type dsp23DNRStatus) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(AXI_CTRL_NR3D_BASE, DSP2_AXI_CTRL_NR_STATUS); - - if (tmpVal & 1 << dsp23DNRStatus) { - return SET; - } else { - return RESET; - } -} - -/*@} end of group DSP2_AXI_CTRL_Public_Functions */ - -/*@} end of group DSP2_AXI_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c deleted file mode 100644 index 33e2690c2a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_misc.c +++ /dev/null @@ -1,1575 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_misc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2_misc.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_MISC - * @{ - */ - -/** @defgroup DSP2_MISC_Private_Macros - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Macros */ - -/** @defgroup DSP2_MISC_Private_Types - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Types */ - -/** @defgroup DSP2_MISC_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *dsp2MiscIntCbfArra[DSP2_MISC_INT_ALL] = { - NULL -}; -#endif - -/*@} end of group DSP2_MISC_Private_Variables */ - -/** @defgroup DSP2_MISC_Global_Variables - * @{ - */ - -/*@} end of group DSP2_MISC_Global_Variables */ - -/** @defgroup DSP2_MISC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Fun_Declaration */ - -/** @defgroup DSP2_MISC_Private_Functions - * @{ - */ - -/*@} end of group DSP2_MISC_Private_Functions */ - -/** @defgroup DSP2_MISC_Public_Functions - * @{ - */ - -/****************************************************************************//** - * @brief DVP AS 2X function init - * - * @param dvp2xCfg: DVP AS 2X configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_2X_Init(DSP2_MISC_2X_Cfg_Type *dvp2xCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->hSyncLevel)); - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(dvp2xCfg->vSyncLevel)); - CHECK_PARAM(IS_DSP2_MISC_2X_DATA_ORDER_TYPE(dvp2xCfg->dataOrder)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_HS_INV, dvp2xCfg->hSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_VS_INV, dvp2xCfg->vSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_DA_ORDER, dvp2xCfg->dataOrder); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DVPAS_FIFO_TH, dvp2xCfg->fifoThreshold & 0x7ff); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, tmpVal); -} - -/****************************************************************************//** - * @brief DVP AS 2X function enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_2X_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE)); -} - -/****************************************************************************//** - * @brief DVP AS 2X function disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_2X_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DVPAS_ENABLE)); -} - -/****************************************************************************/ /** - * @brief CAM input selection - * - * @param camId: CAM id - * @param inputType: CAM input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_CAM_Input_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_CAM_Input_Type inputType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_DSP2_MISC_CAM_INPUT_TYPE(inputType)); - - if (camId < DSP2_MISC_CAM_4_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1); - tmpVal = (tmpVal & ~(0x3f << (camId * 8))) | (inputType & 0x3f) << (camId * 8); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1, tmpVal); - } else { - camId -= 4; - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2); - tmpVal = (tmpVal & ~(0x3f << (camId * 8))) | (inputType & 0x3f) << (camId * 8); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief CAM frame id type selection - * - * @param camId: CAM id - * @param idType: Frame id type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_CAM_Frame_ID_Select(DSP2_MISC_CAM_ID_Type camId, DSP2_MISC_Frame_ID_Type idType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CAM_ID_TYPE(camId)); - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType)); - - if (camId < DSP2_MISC_CAM_4_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1); - tmpVal = (tmpVal & ~(0x1 << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_A_POS))) | idType << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_A_POS); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_1, tmpVal); - } else { - camId -= 4; - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2); - tmpVal = (tmpVal & ~(0x1 << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_E_POS))) | idType << (camId * 8 + DSP2_MISC_RG_D2X_ID_SEL_E_POS); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP2BUS_SRC_SEL_2, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Frame id init - * - * @param idType: Frame id type - * @param edgeType: Frame id edge type - * @param vsyncCnt: Vsync count to trigger id increment - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Frame_ID_Init(DSP2_MISC_Frame_ID_Type idType, DSP2_MISC_Frame_ID_Edge_Type edgeType, uint16_t vsyncCnt) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType)); - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_EDGE_TYPE(edgeType)); - - if (idType == DSP2_MISC_FRAME_BAYER_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_EDGE, edgeType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_CNT_INCR, vsyncCnt); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER, tmpVal); - } else { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_YUV_IDGEN_EDGE, edgeType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_YUV_IDGEN_CNT_INCR, vsyncCnt); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief Reset frame id - * - * @param idType: Frame id type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Frame_ID_Reset(DSP2_MISC_Frame_ID_Type idType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_FRAME_ID_TYPE(idType)); - - if (idType == DSP2_MISC_FRAME_BAYER_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_BAYER, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_BAYER_IDGEN_RST)); - } else { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DSP2_ID_YUV, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_YUV_IDGEN_RST)); - } -} - -/****************************************************************************/ /** - * @brief OSD input selection - * - * @param osdId: OSD id - * @param inputType: OSD input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_OSD_Input_Select(DSP2_MISC_OSD_ID_Type osdId, DSP2_MISC_OSD_Input_Type inputType) -{ - uint32_t tmpVal; - uint32_t osdAddr = DSP2_MISC_BASE + DSP2_MISC_OSDA_I_CTRL_OFFSET + 4 * osdId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_OSD_ID_TYPE(osdId)); - CHECK_PARAM(IS_DSP2_MISC_OSD_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_WORD(osdAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSDA_SEL, inputType); - BL_WR_WORD(osdAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief OSD probe input selection - * - * @param inputType: OSD input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_OSD_Probe_Input_Select(DSP2_MISC_OSD_Input_Type inputType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_OSD_INPUT_TYPE(inputType)); - - if (inputType > DSP2_MISC_OSD_DSP2_INPUT) { - return; - } - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_OSDA_I_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSD_PB_SEL, inputType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_OSDA_I_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Crop init - * - * @param cropId: Crop id - * @param cropCfg: Crop configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Crop_Init(DSP2_MISC_Crop_ID_Type cropId, DSP2_MISC_Crop_Cfg_Type *cropCfg) -{ - uint32_t cropAddr = DSP2_MISC_BASE + DSP2_MISC_CROPA_HSYNC_OFFSET + 8 * cropId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId)); - - BL_WR_WORD(cropAddr, cropCfg->hsyncEnd << 16 | cropCfg->hsyncStart); - cropAddr += 4; - BL_WR_WORD(cropAddr, cropCfg->vsyncEnd << 16 | cropCfg->vsyncStart); -} - -/****************************************************************************/ /** - * @brief Crop enable - * - * @param cropId: Crop id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Crop_Enable(DSP2_MISC_Crop_ID_Type cropId) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE); - - switch (cropId) { - case DSP2_MISC_CROP_0_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPA_ENABLE); - break; - - case DSP2_MISC_CROP_1_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPB_ENABLE); - break; - - case DSP2_MISC_CROP_2_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPC_ENABLE); - break; - - case DSP2_MISC_CROP_3_ID: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_CROPD_ENABLE); - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Crop disable - * - * @param cropId: Crop id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Crop_Disable(DSP2_MISC_Crop_ID_Type cropId) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_CROP_ID_TYPE(cropId)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE); - - switch (cropId) { - case DSP2_MISC_CROP_0_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPA_ENABLE); - break; - - case DSP2_MISC_CROP_1_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPB_ENABLE); - break; - - case DSP2_MISC_CROP_2_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPC_ENABLE); - break; - - case DSP2_MISC_CROP_3_ID: - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_CROPD_ENABLE); - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CROP_ENABLE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler input selection - * - * @param scalerId: Scaler id - * @param inputType: Scaler input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Input_Select(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Input_Type inputType) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - CHECK_PARAM(IS_DSP2_MISC_SCALER_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_SEL, inputType); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler init - * - * @param scalerId: Scaler id - * @param scalerCfg: Scaler configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Init(DSP2_MISC_Scaler_ID_Type scalerId, DSP2_MISC_Scaler_Cfg_Type *scalerCfg) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_I_W, scalerCfg->inputWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_I_H, scalerCfg->inputHeight & 0x7ff); - BL_WR_WORD(scalerAddr, tmpVal); - - scalerAddr += 4; - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_O_W, scalerCfg->outputWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SCALERA_O_H, scalerCfg->outputHeight); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler enable - * - * @param scalerId: Scaler id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Enable(DSP2_MISC_Scaler_ID_Type scalerId) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_SCALERA_BYPASS); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Scaler disable - * - * @param scalerId: Scaler id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Disable(DSP2_MISC_Scaler_ID_Type scalerId) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SCALERA_BYPASS); - BL_WR_WORD(scalerAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust input selection - * - * @param adjustId: Adjust id - * @param inputType: Adjust input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Scaler_Shadow(DSP2_MISC_Scaler_ID_Type scalerId) -{ - uint32_t tmpVal; - uint32_t scalerAddr = DSP2_MISC_BASE + DSP2_MISC_SCALERA_I_SIZE_OFFSET + 8 * scalerId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_SCALER_ID_TYPE(scalerId)); - - tmpVal = BL_RD_WORD(scalerAddr); - BL_WR_WORD(scalerAddr, BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SCLRA_SW_SH)); -} - -/****************************************************************************/ /** - * @brief Adjust input selection - * - * @param adjustId: Adjust id - * @param inputType: Adjust input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Input_Select(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Input_Type inputType) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_2_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - CHECK_PARAM(IS_DSP2_MISC_ADJUST_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_ADJA_SEL, inputType); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust init - * - * @param adjustId: Adjust id - * @param adjustCfg: Adjust configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Init(DSP2_MISC_Adjust_ID_Type adjustId, DSP2_MISC_Adjust_Cfg_Type *adjustCfg) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_LUMA, adjustCfg->yLuma); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MUL0, adjustCfg->yMul0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MUL1, adjustCfg->yMul1); - BL_WR_WORD(adjustAddr, tmpVal); - - adjustAddr += 4; - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MIN, adjustCfg->yMin); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_Y_MAX, adjustCfg->yMax); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MIN, adjustCfg->uvMin); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MAX, adjustCfg->uvMax); - BL_WR_WORD(adjustAddr, tmpVal); - - adjustAddr += 4; - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MUL0, adjustCfg->uvMul0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_ADJA_UV_MUL1, adjustCfg->uvMul1); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust enable - * - * @param adjustId: Adjust id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Enable(DSP2_MISC_Adjust_ID_Type adjustId) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_ADJA_ADJ_EB); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Adjust disable - * - * @param adjustId: Adjust id - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Adjust_Disable(DSP2_MISC_Adjust_ID_Type adjustId) -{ - uint32_t tmpVal; - uint32_t adjustAddr = DSP2_MISC_BASE + DSP2_MISC_ADJA_CTRL_0_OFFSET + 16 * adjustId; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - - tmpVal = BL_RD_WORD(adjustAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_REG_ADJA_ADJ_EB); - BL_WR_WORD(adjustAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief Display init - * - * @param displayCfg: Display configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Display_Init(DSP2_MISC_Display_Cfg_Type *displayCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ADJUST_ID_TYPE(adjustId)); - CHECK_PARAM(IS_DSP2_MISC_DISPLAY_OSD_INPUT_TYPE(displayCfg->osdType)); - CHECK_PARAM(IS_DSP2_MISC_DISPLAY_INPUT_TYPE(displayCfg->inputType)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_HDMI_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_BT1120_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_DPI_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_MUX_SEL, displayCfg->inputType); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSDDP_SEL, displayCfg->osdType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG, tmpVal); - - if (displayCfg->dpiEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_DPI_EN); - } else if (displayCfg->hdmiEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_HDMI_EN); - } else if (displayCfg->bt1120Enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DISP_BT1120_EN); - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_DPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_HS_W, displayCfg->hsyncWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_HFP_W, displayCfg->hfpWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_VS_W, displayCfg->vsyncWidth); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_DPI_VFP_W, displayCfg->vfpWidth); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_DPI_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Display gamma init - * - * @param gammaCfg: Display gamma configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Display_Gamma_Init(DSP2_MISC_Display_Gamma_Cfg_Type *gammaCfg) -{ - uint32_t tmpVal, i, j; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_GMA_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH0_EN, gammaCfg->ch0Enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH1_EN, gammaCfg->ch1Enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DP_GMA_CH2_EN, gammaCfg->ch2Enable); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_GMA_CFG, tmpVal); - - if (gammaCfg->gammaCurve == NULL) { - return; - } - - for (i = 0; i < 64; i++) { - tmpVal = 0; - - for (j = 0; j < 4; j++) { - tmpVal |= gammaCfg->gammaCurve[j + 4 * i] << (8 * j); - } - - BL_WR_WORD(DSP2_MISC_BASE + DSP2_MISC_DISP_GMA_CURVE_00_OFFSET + 4 * i, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief YUV2RGB input selection - * - * @param inputType: YUV2RGB input type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_YUV2RGB_Input_Select(DSP2_MISC_YUV2RGB_Input_Type inputType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_YUV2RGB_INPUT_TYPE(inputType)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_SEL, inputType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief YUV2RGB init - * - * @param yuv2rgbId: YUV2RGB ID type - * @param yuv2rgbCfg: YUV2RGB configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_YUV2RGB_Init(DSP2_MISC_YUV2RGB_ID_Type yuv2rgbId, DSP2_MISC_YUV2RGB_Cfg_Type *yuv2rgbCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_YUV2RGB_ID_TYPE(yuv2rgbId)); - - if (yuv2rgbId == DSP2_MISC_YUV2RGB_DISPLAY_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_0, yuv2rgbCfg->preOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_1, yuv2rgbCfg->preOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_PRE_2, yuv2rgbCfg->preOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_0, yuv2rgbCfg->postOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_1, yuv2rgbCfg->postOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_POS_2, yuv2rgbCfg->postOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_00, yuv2rgbCfg->matrix00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_01, yuv2rgbCfg->matrix01); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_02_L, yuv2rgbCfg->matrix02); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_02_U, yuv2rgbCfg->matrix02 >> 8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_10, yuv2rgbCfg->matrix10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_11, yuv2rgbCfg->matrix11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_12_L, yuv2rgbCfg->matrix12); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_12_U, yuv2rgbCfg->matrix12 >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_20, yuv2rgbCfg->matrix20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_21, yuv2rgbCfg->matrix21); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_MTX_22, yuv2rgbCfg->matrix22); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_5, tmpVal); - - /* Enable or disable function */ - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_YUV_RGB_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_Y2R_EN, yuv2rgbCfg->enable)); - - } else if (yuv2rgbId == DSP2_MISC_YUV2RGB_NORMAL_ID) { - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_0, yuv2rgbCfg->preOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_0, yuv2rgbCfg->postOffset0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_1, yuv2rgbCfg->preOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_1, yuv2rgbCfg->postOffset1); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_PRE_2, yuv2rgbCfg->preOffset2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_POS_2, yuv2rgbCfg->postOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_00, yuv2rgbCfg->matrix00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_01, yuv2rgbCfg->matrix01); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_02, yuv2rgbCfg->matrix02); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_10, yuv2rgbCfg->matrix10); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_11, yuv2rgbCfg->matrix11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_12, yuv2rgbCfg->matrix12); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_5, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_20, yuv2rgbCfg->matrix20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_21, yuv2rgbCfg->matrix21); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_6, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_MTX_22, yuv2rgbCfg->matrix22); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_7, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_Y2RA_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_Y2RA_EN, yuv2rgbCfg->enable)); - } -} - -/****************************************************************************/ /** - * @brief RGB2YUV init - * - * @param rgb2yuvCfg: YUV2RGB configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_RGB2YUV_Init(DSP2_MISC_YUV2RGB_Cfg_Type *rgb2yuvCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_0, rgb2yuvCfg->preOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_1, rgb2yuvCfg->preOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_PRE_2, rgb2yuvCfg->preOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_0, rgb2yuvCfg->postOffset0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_1, rgb2yuvCfg->postOffset1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_POS_2, rgb2yuvCfg->postOffset2); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_1, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_00, rgb2yuvCfg->matrix00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_01, rgb2yuvCfg->matrix01); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_02_L, rgb2yuvCfg->matrix02); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_2, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_02_U, rgb2yuvCfg->matrix02 >> 8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_10, rgb2yuvCfg->matrix10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_11, rgb2yuvCfg->matrix11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_12_L, rgb2yuvCfg->matrix12); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_3, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_12_U, rgb2yuvCfg->matrix12 >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_20, rgb2yuvCfg->matrix20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_21, rgb2yuvCfg->matrix21); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_4, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_MTX_22, rgb2yuvCfg->matrix22); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_5, tmpVal); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DISP_RGB2YUV_CONFIG_0, BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DISP_R2Y_EN, rgb2yuvCfg->enable)); -} - -/****************************************************************************/ /** - * @brief Clear certain or all of the interrupt - * - * @param intType: Interrupt type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Int_Clear(DSP2_MISC_INT_Type intType) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - - switch (intType) { - case DSP2_MISC_INT_AWB0: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB_INT_CLR); - break; - - case DSP2_MISC_INT_AE: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AE_INT_CLR); - break; - - case DSP2_MISC_INT_WDR: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_WDR_INT_CLR); - break; - - case DSP2_MISC_INT_AWB1: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB2_INT_CLR); - break; - - case DSP2_MISC_INT_OSD_PB: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_OSD_PB_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF1_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF2_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF3_INT_CLR); - break; - - case DSP2_MISC_INT_AE_HIST: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AE_HIST_INT_CLR); - break; - - case DSP2_MISC_INT_AWB2: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_AWB3_INT_CLR); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_CLR); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_RG_SEOF4_INT_CLR); - break; - - case DSP2_MISC_INT_ALL: - tmpVal = 0x7f1f; - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CLR, tmpVal); -} - -/****************************************************************************/ /** - * @brief Mask/Unmask certain or all of the interrupt - * - * @param intType: Interrupt type - * @param intMask: Mask or unmask - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Int_Mask(DSP2_MISC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL); - - switch (intType) { - case DSP2_MISC_INT_AWB0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AE: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AE_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_WDR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_WDR_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AWB1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB2_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_OSD_PB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_OSD_PB_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AE_HIST: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AE_HIST_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_AWB2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_AWB3_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_MASK, intMask); - break; - - case DSP2_MISC_INT_ALL: - if (intMask == MASK) { - tmpVal |= 0x1131111f; - } else { - tmpVal &= ~0x1131111f; - } - - break; - - default: - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install dsp2 misc interrupt callback function - * - * @param intType: DSP2 misc interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void DSP2_MISC_Int_Callback_Install(DSP2_MISC_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - - switch (intType) { -#if defined(CPU_D0) - - case DSP2_MISC_INT_AWB0: - Interrupt_Handler_Register(DSP2_AWB0_IRQn, AWB0_IRQHandler); - break; -#endif - - case DSP2_MISC_INT_AE: - Interrupt_Handler_Register(DSP2_AE_IRQn, AE_IRQHandler); - break; - - case DSP2_MISC_INT_WDR: - Interrupt_Handler_Register(DSP2_WDR_IRQn, WDR_IRQHandler); - break; - - case DSP2_MISC_INT_AWB1: - Interrupt_Handler_Register(DSP2_AWB1_IRQn, AWB1_IRQHandler); - break; - - case DSP2_MISC_INT_OSD_PB: - Interrupt_Handler_Register(OSD_PB_IRQn, OSD_PB_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF0: - Interrupt_Handler_Register(SEOF_INT0_IRQn, SEOF0_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF1: - Interrupt_Handler_Register(SEOF_INT1_IRQn, SEOF1_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF2: - Interrupt_Handler_Register(SEOF_INT2_IRQn, SEOF2_IRQHandler); - break; - - case DSP2_MISC_INT_AE_HIST: - Interrupt_Handler_Register(DSP2_AE_HIST_IRQn, AE_HIST_IRQHandler); - break; - - case DSP2_MISC_INT_AWB2: - Interrupt_Handler_Register(DSP2_AWB2_IRQn, AWB2_IRQHandler); - break; - - case DSP2_MISC_INT_DISPLAY: - Interrupt_Handler_Register(DISPLAY_IRQn, Display_IRQHandler); - break; - - case DSP2_MISC_INT_SEOF3: - Interrupt_Handler_Register(SEOF_INT3_IRQn, SEOF3_IRQHandler); - break; - - default: - break; - } - - dsp2MiscIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Select SEOF interrupt vsync source - * - * @param intType: SEOF interrupt type - * @param source: SEOF interrupt vsync source type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_SEOF_Set_Source(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Source_Type source) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - CHECK_PARAM(IS_DSP2_MISC_SEOF_SOURCE_TYPE(source)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL); - - switch (intType) { - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_SRC, source); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_SRC, source); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_SRC, source); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_SRC, source & 0x1); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_SRC, source); - break; - - default: - return; - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select SEOF interrupt vsync source - * - * @param intType: SEOF interrupt type - * @param edge: SEOF interrupt edge type - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_SEOF_Set_Edge(DSP2_MISC_INT_Type intType, DSP2_MISC_SEOF_Edge_Type edge) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_INT_TYPE(intType)); - CHECK_PARAM(IS_DSP2_MISC_SEOF_SOURCE_TYPE(edge)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL); - - switch (intType) { - case DSP2_MISC_INT_SEOF0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF1_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_SEOF1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF2_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_SEOF2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF3_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_DISPLAY: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_DP_SEOF0_INT_EDGE, edge); - break; - - case DSP2_MISC_INT_SEOF3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_RG_SEOF4_INT_EDGE, edge); - break; - - default: - return; - break; - } - - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_INT_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Reshape init - * - * @param reshapeCfg: Reshape configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Reshape_Init(DSP2_MISC_Reshape_Cfg_Type *reshapeCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->hSyncLevel)); - CHECK_PARAM(IS_DSP2_MISC_ACTIVE_LEVEL_TYPE(reshapeCfg->vSyncLevel)); - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_TGL_COUNT, reshapeCfg->vsyncNumber & 0x1f); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_HSYNC_INV, reshapeCfg->hSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_VSYNC_INV, reshapeCfg->vSyncLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_RSHP_EN, reshapeCfg->enable); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Clear vsync toggle counter - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Reshape_Counter_Clear(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_RESHAPE, BL_SET_REG_BIT(tmpVal, DSP2_MISC_REG_RSHP_CLR)); -} - -/****************************************************************************/ /** - * @brief Enable or disable use DE as hsync for DSP2 - * - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_DE_As_Hsync(BL_Fun_Type enable) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_DSP2_DE_AS_HSYNC, enable); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Select DVP TSRC data source - * - * @param sourceType: DVP or CSI - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_TSRC_Source_Select(DSP2_MISC_TSRC_Source_Type sourceType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_DSP2_DTSRC_SRC, sourceType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Configure bayer data shift function - * - * @param bitEnable: Enable bits used - * @param shiftType: Set shift direction - * @param bitShift: Set Shift bits - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_Bayer_Shift(uint16_t bitEnable, DSP2_MISC_Bayer_Shift_Type shiftType, uint8_t bitShift) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_DSP2_MISC_BAYER_SHIFT_TYPE(shiftType)); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_CTRL, bitEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_SHT_BIT, bitShift); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_REG_PIX_DATA_SHT_DIR, shiftType); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_PIX_DATA_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief Reduce m frames to n frames function enable - * - * @param m: Total frame count - * @param n: Enabled frame count - * @param step: Step between enabled frames - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_M2N_Enable(uint8_t m, uint8_t n, uint8_t step) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N); - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_MISC_CR_FRAME_M_TO_N_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_INTERVAL, step); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_CNT_N, n); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_MISC_CR_FRAME_CNT_M, m); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N, tmpVal); -} - -/****************************************************************************/ /** - * @brief Reduce m frames to n frames function disable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void DSP2_MISC_M2N_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N); - BL_WR_REG(DSP2_MISC_BASE, DSP2_MISC_DVP_FRAME_M_TO_N, BL_CLR_REG_BIT(tmpVal, DSP2_MISC_CR_FRAME_M_TO_N_EN)); -} - -/****************************************************************************/ /** - * @brief SEOF0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF0_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF0); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF0] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF0](); - } -} -#endif - -/****************************************************************************/ /** - * @brief SEOF1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF1_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF1); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF1] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF1](); - } -} -#endif - -/****************************************************************************/ /** - * @brief SEOF2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF2_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF2); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF2] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF2](); - } -} -#endif - -/****************************************************************************/ /** - * @brief SEOF3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEOF3_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_SEOF3); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF3] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_SEOF3](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AWB0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AWB0_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB0); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB0] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB0](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AWB1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AWB1_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB1); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB1] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB1](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AWB2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AWB2_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AWB2); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB2] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AWB2](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AE interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AE_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AE); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AE] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AE](); - } -} -#endif - -/****************************************************************************/ /** - * @brief AE HIST interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void AE_HIST_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_AE_HIST); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_AE_HIST] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_AE_HIST](); - } -} -#endif - -/****************************************************************************/ /** - * @brief WDR interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void WDR_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_WDR); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_WDR] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_WDR](); - } -} -#endif - -/****************************************************************************/ /** - * @brief OSD PB interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void OSD_PB_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_OSD_PB); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_OSD_PB] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_OSD_PB](); - } -} -#endif - -/****************************************************************************/ /** - * @brief Display interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void Display_IRQHandler(void) -{ - DSP2_MISC_Int_Clear(DSP2_MISC_INT_DISPLAY); - - if (dsp2MiscIntCbfArra[DSP2_MISC_INT_DISPLAY] != NULL) { - dsp2MiscIntCbfArra[DSP2_MISC_INT_DISPLAY](); - } -} -#endif - -/*@} end of group DSP2_MISC_Public_Functions */ - -/*@} end of group DSP2_MISC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c deleted file mode 100644 index 92324196fe..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dsp2_wdr.c +++ /dev/null @@ -1,557 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dsp2_wdr.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dsp2_wdr.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DSP2_WDR - * @{ - */ - -/** @defgroup DSP2_WDR_Private_Macros - * @{ - */ -#define DSP2_WDR_ROI_WEIGHT_MAX (15) -#define DSP2_WDR_CURVE_WEIGHT_MAX (2 << 8) -#define DSP2_WDR_POST_ENHANCE_Y_OFFSET_MAX ((2 << 12) - 1) -#define DSP2_WDR_POST_ENHANCE_Y_GAIN_MAX ((2 << 15) - 1) -#define DSP2_WDR_POST_ENHANCE_C_GAIN_MAX ((2 << 15) - 1) - -/*@} end of group DSP2_WDR_Private_Macros */ - -/** @defgroup DSP2_WDR_Private_Types - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Types */ - -/** @defgroup DSP2_WDR_Private_Variables - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Variables */ - -/** @defgroup DSP2_WDR_Global_Variables - * @{ - */ - -/*@} end of group DSP2_WDR_Global_Variables */ - -/** @defgroup DSP2_WDR_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Fun_Declaration */ - -/** @defgroup DSP2_WDR_Private_Functions - * @{ - */ - -/*@} end of group DSP2_WDR_Private_Functions */ - -/** @defgroup DSP2_WDR_Public_Functions - * @{ - */ - -void DSP2_WDR_Get_WDR_State(BL_Fun_Type *state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - - if (BL_IS_REG_BIT_SET(tmpVal, DSP2_BLBACK_WDR_EN_PRE)) { - *state = ENABLE; - } else { - *state = DISABLE; - } -} - -void DSP2_WDR_Set_WDR_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_WDR_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_WDR_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_0, tmpVal); -} - -void DSP2_WDR_Set_CS_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_WDR_CS_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_WDR_CS_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0, tmpVal); -} - -void DSP2_WDR_Set_CS_Config(const DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GAIN_PRE, chromaSupprCfg->gain); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_0, tmpVal); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_WEIGHT_PRE, chromaSupprCfg->weight); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GREY_TH_PRE, chromaSupprCfg->gain_thresh); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0, tmpVal); -} - -void DSP2_WDR_Get_CS_Config(DSP2_Chroma_Suppress_Type *chromaSupprCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - chromaSupprCfg->gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GAIN_PRE); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CS_0); - chromaSupprCfg->weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_WEIGHT_PRE); - chromaSupprCfg->gain_thresh = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_WDR_CS_GREY_TH_PRE); -} - -void DSP2_WDR_Set_ROI_State(int roi_id, BL_Fun_Type state) -{ - uint32_t tmpVal; - - switch (roi_id) { - case 0: - case 1: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI1_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI0_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1, tmpVal); - break; - - case 2: - case 3: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI3_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI2_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2, tmpVal); - break; - - case 4: - case 5: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI5_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI4_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3, tmpVal); - break; - - case 6: - case 7: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI7_EN_PRE, state); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI6_EN_PRE, state); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4, tmpVal); - break; - - default: - break; - } -} - -void DSP2_WDR_Set_ROI_Position(int roi_id, uint32_t left_x, uint32_t right_x, - uint32_t top_y, uint32_t bottom_y) -{ - uint32_t tmpVal; - - switch (roi_id) { - case 0: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X0_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X0_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_5, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y0_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y0_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_6, tmpVal); - break; - - case 1: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X1_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X1_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_7, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y1_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y1_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_8, tmpVal); - break; - - case 2: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_9); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X2_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X2_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_9, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y2_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y2_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_10, tmpVal); - break; - - case 3: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X3_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X3_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_11, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_12); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y3_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y3_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_12, tmpVal); - break; - - case 4: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_13); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X4_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X4_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_13, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y4_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y4_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_14, tmpVal); - break; - - case 5: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_15); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X5_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X5_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_15, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_16); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y5_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y5_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_16, tmpVal); - break; - - case 6: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_17); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X6_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X6_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_17, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y6_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y6_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_18, tmpVal); - break; - - case 7: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_19); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X7_MIN_PRE, left_x); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_X7_MAX_PRE, right_x); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_19, tmpVal); - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y7_MIN_PRE, top_y); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_Y7_MAX_PRE, bottom_y); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_20, tmpVal); - break; - - default: - break; - } -} - -void DSP2_WDR_Set_ROI_Weight(int roi_id, uint32_t weight) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(weight, DSP2_WDR_ROI_WEIGHT_MAX); - - switch (roi_id) { - case 0: - case 1: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI1_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI0_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_1, tmpVal); - break; - - case 2: - case 3: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI3_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI2_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_2, tmpVal); - break; - - case 4: - case 5: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI5_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI4_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_3, tmpVal); - break; - - case 6: - case 7: - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4); - - if (roi_id & 0x01) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI7_WEIGHT_PRE, weight); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_HIST_ROI6_WEIGHT_PRE, weight); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_HIST_4, tmpVal); - break; - - default: - break; - } -} - -int DSP2_WDR_Get_Hist_Data(DSP2_WDR_Hist_Data_Type *hist) -{ - uint32_t tmpVal; - uint32_t buf_idx; - uint32_t buf_addr; - uint32_t w_cnt_idx_start; - uint32_t w_cnt_idx_end; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_0); - buf_idx = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_BUF_IDX_R); - w_cnt_idx_start = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_W_CNT_R); - - if (0 == buf_idx) { - buf_addr = DSP2_BASE + DSP2_BLBACK_REG_HIST0_0_OFFSET; - hist->hist_bin[64] = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_REG_HIST0_64); - } else { - buf_addr = DSP2_BASE + DSP2_BLBACK_REG_HIST1_0_OFFSET; - hist->hist_bin[64] = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_REG_HIST1_64); - } - - /* copy all the histogram bin except for the last one */ - ARCH_MemCpy4(&hist->hist_bin[0], (uint32_t *)(uintptr_t)buf_addr, 64); - - w_cnt_idx_end = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_BLWDR_W_CNT_R); - - if (w_cnt_idx_start != w_cnt_idx_end) { - return -1; - } - - return 0; -} - -void DSP2_WDR_Set_WDR_Curve_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_CURVE_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_CURVE_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33, tmpVal); -} - -void DSP2_WDR_Set_WDR_Curve(const DSP2_WDR_Curve_Type *wdr_curve) -{ - ARCH_MemCpy4((uint32_t *)(DSP2_BASE + DSP2_BLBACK_WDR_CURVE_1_OFFSET), (uint32_t *)&wdr_curve->curve_coef[0], DSP2_WDR_CURVE_COEF_NUM / 2); -} - -void DSP2_WDR_Get_WDR_Curve(DSP2_WDR_Curve_Type *wdr_curve) -{ - ARCH_MemCpy4((uint32_t *)&wdr_curve->curve_coef[0], (uint32_t *)(DSP2_BASE + DSP2_BLBACK_WDR_CURVE_1_OFFSET), DSP2_WDR_CURVE_COEF_NUM / 2); -} - -void DSP2_WDR_Set_WDR_Curve_Weight(uint32_t weight) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(weight, DSP2_WDR_CURVE_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CURVE_WEIGHT_PRE, weight); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33, tmpVal); -} - -void DSP2_WDR_Get_WDR_Curve_Weight(uint32_t *weight) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_CURVE_33); - *weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_CURVE_WEIGHT_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_State(BL_Fun_Type state) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - - if (ENABLE == state) { - tmpVal = BL_SET_REG_BIT(tmpVal, DSP2_BLBACK_ENH_EN_PRE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, DSP2_BLBACK_ENH_EN_PRE); - } - - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal); -} - -void DSP2_WDR_Set_Post_Enhance_Weight(uint32_t weight) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(weight, DSP2_WDR_CURVE_WEIGHT_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_WEIGHT_PRE, weight); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Weight(uint32_t *weight) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - *weight = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_WEIGHT_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_Y_Offset(uint32_t y_offset) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(y_offset, DSP2_WDR_POST_ENHANCE_Y_OFFSET_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_OFFSET_PRE, y_offset); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Y_Offset(uint32_t *y_offset) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_1); - *y_offset = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_OFFSET_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_Luma_Gain(uint32_t gain) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(gain, DSP2_WDR_POST_ENHANCE_Y_GAIN_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_GAIN_PRE, gain); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Luma_Gain(uint32_t *gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - *gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_Y_GAIN_PRE); -} - -void DSP2_WDR_Set_Post_Enhance_Chroma_Gain(uint32_t gain) -{ - uint32_t tmpVal; - - CHECK_PARAM_MAX(gain, DSP2_WDR_POST_ENHANCE_C_GAIN_MAX); - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_C_GAIN_PRE, gain); - BL_WR_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2, tmpVal); -} - -void DSP2_WDR_Get_Post_Enhance_Chroma_Gain(uint32_t *gain) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(DSP2_BASE, DSP2_BLBACK_WDR_ENH_2); - *gain = BL_GET_REG_BITS_VAL(tmpVal, DSP2_BLBACK_ENH_C_GAIN_PRE); -} - -/*@} end of group DSP2_WDR_Public_Functions */ - -/*@} end of group DSP2_WDR */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c deleted file mode 100644 index 1be3c39d98..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_dvp_tsrc.c +++ /dev/null @@ -1,394 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_dvp_tsrc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_dvp_tsrc.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup DVP_TSRC - * @{ - */ - -/** @defgroup DVP_TSRC_Private_Macros - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Macros */ - -/** @defgroup DVP_TSRC_Private_Types - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Types */ - -/** @defgroup DVP_TSRC_Private_Variables - * @{ - */ -static const uint32_t dvpTsrcAddr[DVP_TSRC_ID_MAX] = { DVP_TSRC0_BASE, DVP_TSRC1_BASE }; - -/*@} end of group DVP_TSRC_Private_Variables */ - -/** @defgroup DVP_TSRC_Global_Variables - * @{ - */ - -/*@} end of group DVP_TSRC_Global_Variables */ - -/** @defgroup DVP_TSRC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Fun_Declaration */ - -/** @defgroup DVP_TSRC_Private_Functions - * @{ - */ - -/*@} end of group DVP_TSRC_Private_Functions */ - -/** @defgroup DVP_TSRC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief DVP_TSRC init - * - * @param tsrcId: DVP_TSRC ID type - * @param dvpTsrcCfg: DVP_TSRC configuration - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type DVP_TSRC_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Cfg_Type *dvpTsrcCfg) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - CHECK_PARAM(IS_DVP_TSRC_PIXEL_FORMAT_TYPE(dvpTsrcCfg->format)); - CHECK_PARAM(IS_DVP_TSRC_DVP2AXI_TYPE(dvpTsrcCfg->dvp2axi)); - CHECK_PARAM(IS_DVP_TSRC_SWAP_CONTROL_TYPE(dvpTsrcCfg->swapControl)); - CHECK_PARAM(IS_DVP_TSRC_BURST_TYPE(dvpTsrcCfg->burst)); - CHECK_PARAM(IS_DVP_TSRC_YUV420_LINE_TYPE(dvpTsrcCfg->lineType)); - - /* Enable using AXI data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, DTSRC_CR_MODE_CEA_861); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_MODE, dvpTsrcCfg->swapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SWM, dvpTsrcCfg->swapControl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SEL, dvpTsrcCfg->dvp2axi); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_DVP_DATA_MODE, dvpTsrcCfg->format); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_EN, dvpTsrcCfg->dataFromSensor); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_HSYNC_INV, dvpTsrcCfg->sensorHsyncInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_VSYNC_INV, dvpTsrcCfg->sensorVsyncInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B0_SEL, dvpTsrcCfg->byte0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B1_SEL, dvpTsrcCfg->byte1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_B2_SEL, dvpTsrcCfg->byte2); - tmpVal = BL_SET_REG_BIT(tmpVal, DTSRC_CR_AXI_EN); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, tmpVal); - - /* Set burst length */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_420_MODE, dvpTsrcCfg->yuv420Enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_420_UD_SEL, dvpTsrcCfg->lineType); - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_XLEN, dvpTsrcCfg->burst)); - - /* Set horizontal pixel count */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_H); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_TOTAL_H, dvpTsrcCfg->hTotalCnt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_BLANK_H, dvpTsrcCfg->hBlankCnt); - BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_H, tmpVal); - - /* Set vertical pixel count */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_V); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_TOTAL_V, dvpTsrcCfg->vTotalCnt); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_BLANK_V, dvpTsrcCfg->vBlankCnt); - BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_V, tmpVal); - - /* Set vertical prefetch start position */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_PREFETCH); - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_PREFETCH, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_PREFETCH_V, dvpTsrcCfg->prefetch)); - - /* Set fifo threshold for each DVP line to start to output */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS); - BL_WR_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_FIFO_TH, dvpTsrcCfg->fifoThreshold)); - - /* Set axi2dvp start address, Y planar in YUV420 mode, frame 0 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_START_ADDR_BY, dvpTsrcCfg->memStartY0); - - /* Set axi2dvp memory size in burst */ - switch (dvpTsrcCfg->burst) { - case DVP_TSRC_BURST_TYPE_SINGLE: - tmpVal = dvpTsrcCfg->memSizeY0 / 8; - break; - - case DVP_TSRC_BURST_TYPE_INCR4: - tmpVal = dvpTsrcCfg->memSizeY0 / 32; - break; - - case DVP_TSRC_BURST_TYPE_INCR8: - tmpVal = dvpTsrcCfg->memSizeY0 / 64; - break; - - case DVP_TSRC_BURST_TYPE_INCR16: - tmpVal = dvpTsrcCfg->memSizeY0 / 128; - break; - - case DVP_TSRC_BURST_TYPE_INCR32: - tmpVal = dvpTsrcCfg->memSizeY0 / 256; - break; - - case DVP_TSRC_BURST_TYPE_INCR64: - tmpVal = dvpTsrcCfg->memSizeY0 / 512; - break; - - default: - tmpVal = 0; - break; - } - - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_BURST_CNT, tmpVal); - - /* Set axi2dvp start address, Y planar in YUV420 mode, frame 1 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SWAP_ADDR_BY, dvpTsrcCfg->memStartY1); - - /* Set axi2dvp start address, UV planar in YUV420 mode, frame 0 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_START_ADDR_UV, dvpTsrcCfg->memStartUV0); - - /* Set axi2dvp start address, UV planar in YUV420 mode, frame 1 in swap mode */ - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SWAP_ADDR_UV, dvpTsrcCfg->memStartUV1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Use fake gradient data function init - * - * @param tsrcId: DVP_TSRC ID type - * @param dataCfg: Fake gradient data configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Fake_Data_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_Fake_Data_Cfg_Type *dataCfg) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - /* Enable using fake gradient data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_CLR_REG_BIT(tmpVal, DTSRC_CR_AXI_EN)); - - /* Set min and max value of fake gradient data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_PIX_DATA_RANGE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_MIN, dataCfg->minData); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_MAX, dataCfg->maxData); - BL_WR_REG(dvpTsrcX, DTSRC_PIX_DATA_RANGE, tmpVal); - - /* Set step value for eack line of fake gradient data */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_PIX_DATA_STEP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_DATA_STEP, dataCfg->step); - BL_WR_REG(dvpTsrcX, DTSRC_PIX_DATA_STEP, tmpVal); -} - -/****************************************************************************/ /** - * @brief CEA-861 mode init - * - * @param tsrcId: DVP_TSRC ID type - * @param ceaCfg: CEA-861 configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_CEA861_Init(DVP_TSRC_ID_Type tsrcId, DVP_TSRC_CEA861_Cfg_Type *ceaCfg) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BIT(tmpVal, DTSRC_CR_MODE_CEA_861)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_FRAME_SIZE_CEA_861); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_H_PLACEMENT, ceaCfg->hsyncStart); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_H_DURATION, ceaCfg->hsyncEnd); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_V_PLACEMENT, ceaCfg->vsyncStart); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_V_DURATION, ceaCfg->vsyncEnd); - BL_WR_REG(dvpTsrcX, DTSRC_FRAME_SIZE_CEA_861, tmpVal); -} - -/****************************************************************************/ /** - * @brief Sensor input configuration - * - * @param tsrcId: DVP_TSRC ID type - * @param threshold: FIFO threshold for each DVP line to start to output - * @param hsyncInv:Enable or disable inverse signal of sensor hsync - * @param vsyncInv:Enable or disable inverse signal of sensor vsync - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Sensor_Input_Set(DVP_TSRC_ID_Type tsrcId, uint16_t threshold, BL_Fun_Type hsyncInv, BL_Fun_Type vsyncInv) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, DTSRC_CR_SNSR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_HSYNC_INV, hsyncInv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_VSYNC_INV, vsyncInv); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, tmpVal); - - /* Set fifo threshold for each DVP line to start to output */ - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS); - BL_WR_REG(dvpTsrcX, DTSRC_SNSR2DVP_WAIT_POS, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_SNSR_FIFO_TH, threshold)); -} - -/****************************************************************************/ /** - * @brief DVP_TSRC enable - * - * @param tsrcId: DVP_TSRC ID type - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Enable(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BIT(tmpVal, DTSRC_CR_ENABLE)); -} - -/****************************************************************************/ /** - * @brief DVP_TSRC disable - * - * @param tsrcId: DVP_TSRC ID type - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Disable(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_CLR_REG_BIT(tmpVal, DTSRC_CR_ENABLE)); -} - -/****************************************************************************/ /** - * @brief DVP_TSRC set swap index in software mode - * - * @param tsrcId: DVP_TSRC ID type - * @param index: Swap index used - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Set_Swap_Index(DVP_TSRC_ID_Type tsrcId, uint8_t index) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_CONFIG); - BL_WR_REG(dvpTsrcX, DTSRC_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, DTSRC_CR_AXI_SWAP_IDX_SWV, index)); -} - -/****************************************************************************/ /** - * @brief AXI2DVP clear drain error function - * - * @param tsrcId: DVP_TSRC ID type - * - * @return None - * -*******************************************************************************/ -void DVP_TSRC_Clear_Drain_Error(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t tmpVal; - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - tmpVal = BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING); - BL_WR_REG(dvpTsrcX, DTSRC_AXI2DVP_SETTING, BL_SET_REG_BIT(tmpVal, DTSRC_CR_AXI_DRAIN_ERR_CLR)); -} - -/****************************************************************************/ /** - * @brief Get AXI2DVP status function - * - * @param tsrcId: DVP_TSRC ID type - * - * @return Status - * -*******************************************************************************/ -uint32_t DVP_TSRC_Get_Status(DVP_TSRC_ID_Type tsrcId) -{ - uint32_t dvpTsrcX = dvpTsrcAddr[tsrcId]; - - /* Check the parameters */ - CHECK_PARAM(IS_DVP_TSRC_ID_TYPE(tsrcId)); - - return (BL_RD_REG(dvpTsrcX, DTSRC_AXI2DVP_STATUS)); -} - -/*@} end of group DVP_TSRC_Public_Functions */ - -/*@} end of group DVP_TSRC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c deleted file mode 100644 index 05c3efc134..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_cfg.c +++ /dev/null @@ -1,610 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ef_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_ef_ctrl.h" -#include "bl808_ef_cfg.h" -#include "ef_data_0_reg.h" -#include "ef_data_1_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1() - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Efuse get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Cfg_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse get chip info - * - * @param chipInfo: info pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Get_Chip_Info(Efuse_Chip_Info_Type *chipInfo) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - chipInfo->chipInfo = (tmpVal>>29)&0x7; - chipInfo->memoryInfo = (tmpVal>>27)&0x3; - chipInfo->psramInfo = (tmpVal>>25)&0x3; - chipInfo->deviceInfo = (tmpVal>>22)&0x7; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - chipInfo->psramInfo |= ((tmpVal>>20)&0x1) << 2; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal trim rc32m configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO15RF_Vout_Sel(Efuse_Ana_LDO15RF_Vout_Sel_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - trim->trimLDO15RFVoutAon = (tmpVal >> 27) & 0x07; - trim->trimLDO15RFVoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimLDO15RFVoutAonEn = (tmpVal >> 31) & 0x01; -} - - -/****************************************************************************/ /** - * @brief Efuse read rcal iptat code configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Rcal_Iptat_Code(Efuse_Ana_Rcal_Iptat_Code_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - trim->trimRcalIptatCode = (tmpVal >> 22) & 0x1f; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - trim->trimRcalIptatCodeParity = (tmpVal >> 30) & 0x01; - trim->trimRcalIptatCodeEn = (tmpVal >> 31) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read rcal icx code configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Rcal_Icx_Code(Efuse_Ana_Rcal_Icx_Code_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - trim->trimRcalIcxCode = (tmpVal >> 22) & 0x3f; - trim->trimRcalIcxCodeParity = (tmpVal >> 28) & 0x01; - trim->trimRcalIcxCodeEn = (tmpVal >> 29) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read LDO28CIS vout trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO28CIS_Vout_Trim(Efuse_Ana_LDO28CIS_Vout_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimLDO28CISVout = (tmpVal >> 8) & 0xf; - trim->trimLDO28CISVoutParity = (tmpVal >> 12) & 0x01; - trim->trimLDO28CISVoutEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read LDO15CIS vout trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO15CIS_Vout_Trim(Efuse_Ana_LDO15CIS_Vout_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimLDO15CISVout = (tmpVal >> 8) & 0xf; - trim->trimLDO15CISVoutParity = (tmpVal >> 12) & 0x01; - trim->trimLDO15CISVoutEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read LDO12UHS vout trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_LDO12UHS_Vout_Trim(Efuse_Ana_LDO12UHS_Vout_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimLDO12UHSVout = (tmpVal >> 20) & 0xf; - trim->trimLDO12UHSVoutParity = (tmpVal >> 24) & 0x01; - trim->trimLDO12UHSVoutEn = (tmpVal >> 25) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal capcode 1 inout configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Capcode1_Inout(Efuse_Ana_Xtal_Capcode_1_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimXtalCapcode1 = (tmpVal >> 0) & 0x3f; - trim->trimXtalCapcode1Parity = (tmpVal >> 6) & 0x01; - trim->trimXtalCapcode1En = (tmpVal >> 7) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal capcode 2 inout configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Capcode2_Inout(Efuse_Ana_Xtal_Capcode_2_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimXtalCapcode2 = (tmpVal >> 26) & 0x3f; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->trimXtalCapcode2Parity = (tmpVal >> 30) & 0x01; - trim->trimXtalCapcode2En = (tmpVal >> 31) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read xtal capcode 3 inout configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Capcode3_Inout(Efuse_Ana_Xtal_Capcode_3_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimXtalCapcode3 = (tmpVal >> 20) & 0x3f; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->trimXtalCapcode3Parity = (tmpVal >> 28) & 0x01; - trim->trimXtalCapcode3En = (tmpVal >> 29) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read gauge vpack offset configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Gauge_Vpack_Offset(Efuse_Ana_Gauge_Vpack_Offset_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimGaugeVpackOffset = (tmpVal >> 2) & 0xffff; - trim->trimGaugeVpackOffsetParity = (tmpVal >> 18) & 0x01; - trim->trimGaugeVpackOffsetEn = (tmpVal >> 19) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read gauge vtemp offset configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Gauge_Vtemp_Offset(Efuse_Ana_Gauge_Vtemp_Offset_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2); - trim->trimGaugeVtempOffset = (tmpVal >> 16) & 0xffff; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_1); - trim->trimGaugeVtempOffsetParity = (tmpVal >> 0) & 0x01; - trim->trimGaugeVtempOffsetEn = (tmpVal >> 1) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read psram trim configuration - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Psram_Trim(Efuse_Psram_Trim_Type *trim) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2); - trim->psramTrim = (tmpVal >> 0) & 0x7ff; - trim->psramTrimParity = (tmpVal >> 11) & 0x01; - trim->psramTrimEn = (tmpVal >> 12) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write psram trim configuration - * - * @param trim: Trim data pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Psram_Trim(Efuse_Psram_Trim_Type *trim, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2); - tmpVal |= (trim->psramTrim<<0); - tmpVal |= (trim->psramTrimParity<<11); - tmpVal |= (trim->psramTrimEn<<12); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W2, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } -} - -/****************************************************************************/ /** - * @brief Whether MAC address slot is empty - * - * @param slot: MAC address slot - * @param reload: whether reload to check - * - * @return 0 for all slots full,1 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload) -{ - uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff; - uint32_t part1Empty = 0, part2Empty = 0; - - if (slot == 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - } else if (slot == 2) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - tmp1 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1); - tmp2 = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - } - - part1Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp1, 0, 32)); - part2Empty = (EF_Ctrl_Is_All_Bits_Zero(tmp2, 0, 22)); - - return (part1Empty && part2Empty); -} - -/****************************************************************************/ /** - * @brief Efuse write optional MAC address - * - * @param slot: MAC address slot - * @param mac[6]: MAC address buffer - * @param program: Whether program - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0, cnt; - - if (slot >= 3) { - return ERROR; - } - - /* Change to local order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, BL_RDWD_FRM_BYTEP(maclow)); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1, BL_RDWD_FRM_BYTEP(maclow)); - } - - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - cnt = 0; - - for (i = 0; i < 6; i++) { - cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]); - } - - tmpVal |= ((cnt & 0x3f) << 16); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, tmpVal); - } else if (slot == 2) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2, tmpVal); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse read optional MAC address - * - * @param slot: MAC address slot - * @param mac[6]: MAC address buffer - * @param reload: Whether reload - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal = 0; - uint32_t i = 0; - uint32_t cnt = 0; - - if (slot >= 3) { - return ERROR; - } - - /* Trigger read data from efuse */ - if (reload) { - EF_CTRL_LOAD_BEFORE_READ_R0; - } - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W1); - } - - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - if (slot == 0) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - } else if (slot == 1) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - } else if (slot == 2) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W2); - } - - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Cfg_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c deleted file mode 100644 index 1a28966881..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ef_ctrl.c +++ /dev/null @@ -1,1727 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ef_ctrl.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_ef_ctrl.h" -#include "ef_data_0_reg.h" -#include "ef_data_1_reg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_EF_CTRL - * @{ - */ - -/** @defgroup SEC_EF_CTRL_Private_Macros - * @{ - */ -#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24) -#define EF_CTRL_EFUSE_CTRL_PROTECT (0xbf << 8) -#define EF_CTRL_DFT_TIMEOUT_VAL (320 * 1000) -#ifndef BOOTROM -#define EF_CTRL_LOAD_BEFORE_READ_R0 EF_Ctrl_Load_Efuse_R0() -#define EF_CTRL_LOAD_BEFORE_READ_R1 EF_Ctrl_Load_Efuse_R1() -#else -#define EF_CTRL_LOAD_BEFORE_READ_R0 -#define EF_CTRL_LOAD_BEFORE_READ_R1 -#endif -#define EF_CTRL_DATA0_CLEAR EF_Ctrl_Clear(0, 0, EF_CTRL_EFUSE_R0_SIZE / 4) -#define EF_CTRL_DATA1_CLEAR EF_Ctrl_Clear(1, 0, EF_CTRL_EFUSE_R1_SIZE / 4) - -/*@} end of group SEC_EF_CTRL_Private_Macros */ - -/** @defgroup SEC_EF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Types */ - -/** @defgroup SEC_EF_CTRL_Private_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Variables */ - -/** @defgroup SEC_EF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Global_Variables */ - -/** @defgroup SEC_EF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_EF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SEC_EF_CTRL_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief get custom USB PID VID - * - * @param PID - * - * @param VID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]) -{ - uint32_t tmpVal; - - EF_Ctrl_Read_Sw_Usage(4, &tmpVal); - - pid[0] = (uint16_t)(tmpVal & 0xFFFF); - vid[0] = (uint16_t)(tmpVal >> 16); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Switch efuse region 0 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Switch efuse region 1 control to AHB clock - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_1(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - while (EF_Ctrl_Busy() == SET) { - timeout--; - - if (timeout == 0) { - break; - } - } - - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Program */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - arch_delay_us(4); - - /* Trigger */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Program efuse region 1 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_1(void) -{ - uint32_t tmpVal; - - /* Select auto mode and select ef clock */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - /* Program */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (1 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - /* Add delay for POR to be stable */ - arch_delay_us(4); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (1 << EF_CTRL_EF_IF_1_RW_POS) | - (1 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Load efuse region 0 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void) -{ - uint32_t tmpVal; - uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL; - - EF_CTRL_DATA0_CLEAR; - - /* Trigger read */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (1 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - arch_delay_us(10); - - /* Wait for efuse control idle */ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - timeout--; - - if (timeout == 0) { - break; - } - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_BUSY) || - - (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE))); - - /* Switch to AHB clock */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Load efuse region 1 - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void EF_Ctrl_Load_Efuse_R1(void) -{ - uint32_t tmpVal; - - EF_CTRL_DATA1_CLEAR; - - /* Trigger read */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (1 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); - - arch_delay_us(10); - - /* Wait for efuse control idle */ - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1); - } while (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_1_BUSY)); - - do { - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - } while (!BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)); - - /* Switch to AHB clock since often read efuse data after load */ - /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0, - so we select it(them) in ef_if_ctrl_0 */ - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) | - (0 << EF_CTRL_EF_IF_POR_DIG_POS) | - (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_0_RW_POS) | - (0 << EF_CTRL_EF_IF_0_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0, tmpVal); - - tmpVal = (EF_CTRL_EFUSE_CTRL_PROTECT) | - (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) | - (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) | - (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) | - (0 << EF_CTRL_EF_IF_1_RW_POS) | - (0 << EF_CTRL_EF_IF_1_TRIG_POS); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse busy status - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void) -{ - if (BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0), EF_CTRL_EF_IF_0_BUSY) || - BL_IS_REG_BIT_SET(BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_1), EF_CTRL_EF_IF_1_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Check efuse whether finish loading - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_IF_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_IF_0_AUTOLOAD_DONE)) { - return SET; - } else { - return RESET; - } -} -#endif - -/****************************************************************************/ /** - * @brief Efuse write debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits - * @param passWdHigh: password high 32 bits - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (slot == 0) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH, passWdHigh); - } else if (slot == 1) { - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW, passWdLow); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH, passWdHigh); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read debug password - * - * @param slot: password slot0 or slot1 - * @param passWdLow: password low 32 bits pointer to store value - * @param passWdHigh: password high 32 bits pointer to store value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh) -{ - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - if (slot == 0) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD_HIGH); - } else if (slot == 1) { - *passWdLow = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_LOW); - *passWdHigh = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_DBG_PWD2_HIGH); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_RD_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for passwd - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_DBG_PWD); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE, cfg->ef_dbg_mode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS, cfg->ef_dbg_jtag_0_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS, cfg->ef_dbg_jtag_1_dis); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN, cfg->ef_sboot_en); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read security configuration - * - * @param cfg: security configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - cfg->ef_dbg_mode = (EF_Ctrl_Dbg_Mode_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_MODE); - cfg->ef_dbg_jtag_0_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_0_DIS); - cfg->ef_dbg_jtag_1_dis = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_DBG_JTAG_1_DIS); - cfg->ef_sboot_en = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_EN); -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param sign[1]: Sign configuration pointer - * @param aes[1]: AES configuration pointer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - if (aes[0] != EF_CTRL_SF_AES_NONE) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE, aes[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); - } - - if (EF_CTRL_SIGN_NONE != sign[0]) { - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SBOOT_SIGN_MODE, sign[0]); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, tmpVal); - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write security boot configuration - * - * @param aes[2]: AES configuration pointer - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2]) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - aes[1] = aes[0] = (EF_Ctrl_SF_AES_Type)BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_AES_MODE); -} - -/****************************************************************************/ /** - * @brief Efuse read xtal trim rc32m configuration - * - * @param forceNoTrim: force no trim - * @param noXtal: no xtal - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Xtal_Trim_RC32M(uint8_t *forceNoTrim, uint8_t *noXtal) -{ - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - - *forceNoTrim = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_FORCE_NO_TRIM); - *noXtal = BL_GET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_NO_XTAL); -} - -/****************************************************************************/ /** - * @brief Efuse Set sf key re sel - * - * @param ef_sf_key_re_sel: Efuse sf key re sel - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EF_DATA_0_EF_SF_KEY_RE_SEL, ef_sf_key_re_sel); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_CFG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Analog Trim parity calculate - * - * @param val: Value of efuse trim data - * @param len: Length of bit to calculate - * - * @return Parity bit value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len) -{ - uint8_t cnt = 0; - uint8_t i = 0; - - for (i = 0; i < len; i++) { - if (val & (1 << i)) { - cnt++; - } - } - - return cnt & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC11 trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC11_Trim(Efuse_Ana_DCDC11_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimDcdc11VoutAon = (tmpVal >> 26) & 0x0f; - trim->trimDcdc11VoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimDcdc11VoutAonEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read DCDC18 trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_DCDC18_Trim(Efuse_Ana_DCDC18_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimDcdc18VoutAon = (tmpVal >> 20) & 0x0f; - trim->trimDcdc18VoutAonParity = (tmpVal >> 24) & 0x01; - trim->trimDcdc18VoutAonEn = (tmpVal >> 25) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read LDO18FLASH trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18FLASH_Trim(Efuse_Ana_LDO18FLASH_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimLdo18flashVoutAon = (tmpVal >> 26) & 0x0f; - trim->trimLdo18flashVoutAonParity = (tmpVal >> 30) & 0x01; - trim->trimLdo18flashVoutAonEn = (tmpVal >> 31) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read USB20RCAL trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_USB20RCAL_Trim(Efuse_Ana_USB20RCAL_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_2); - trim->trimUsb20rcalAon = (tmpVal >> 8) & 0x3f; - trim->trimUsb20rcalAonParity = (tmpVal >> 14) & 0x01; - trim->trimUsb20rcalAonEn = (tmpVal >> 15) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32M trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - trim->trimRc32mCodeFrExt = (tmpVal >> 4) & 0xff; - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimRc32mCodeFrExtParity = (tmpVal >> 0) & 0x01; - trim->trimRc32mExtCodeEn = (tmpVal >> 1) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read RC32K trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_KEY_SLOT_10_W3); - trim->trimRc32kCodeFrExt = (tmpVal >> 8) & 0x3ff; - trim->trimRc32kCodeFrExtParity = (tmpVal >> 18) & 0x01; - trim->trimRc32kExtCodeEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief - * - * @param - * - * @return - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_CLOCK_SECTION EF_Ctrl_Read_LDO18IO_Vout_Trim(Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W3); - trim->trimLdo18ioVoutVal = (tmpVal >> 14) & 0x0f; - trim->trimLdo18ioVoutParity = (tmpVal >> 18) & 0x01; - trim->trimLdo18ioVoutEn = (tmpVal >> 19) & 0x01; -} -#endif - -/****************************************************************************/ /** - * @brief Efuse read TSEN trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_EF_DAT_1_RSVD_0); - trim->tsenRefcodeCorner = (tmpVal >> 0) & 0xfff; - trim->tsenRefcodeCornerParity = (tmpVal >> 12) & 0x01; - trim->tsenRefcodeCornerEn = (tmpVal >> 13) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse read ADC Gain trim - * - * @param trim: Trim data pointer - * - * @return None - * -*******************************************************************************/ -void ATTR_CLOCK_SECTION EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim) -{ - uint32_t tmpVal = 0; - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - tmpVal = BL_RD_REG(EF_DATA_BASE,EF_DATA_1_EF_DAT_1_RSVD_0); - trim->adcGainCoeff = (tmpVal >> 14) & 0xfff; - trim->adcGainCoeffParity = (tmpVal >> 26) & 0x01; - trim->adcGainCoeffEn = (tmpVal >> 27) & 0x01; -} - -/****************************************************************************/ /** - * @brief Efuse write software usage - * - * @param index: index of software usage - * @param usage: usage value - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program) -{ - /* switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - switch (index) { - case 0: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0, usage); - break; - - case 1: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1, usage); - break; - - case 2: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2, usage); - break; - - case 3: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3, usage); - break; - - case 4: - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0, usage); - break; - - default: - break; - } - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param usage: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage) -{ - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - switch (index) { - case 0: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_0); - break; - - case 1: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_1); - break; - - case 2: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_2); - break; - - case 3: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_SW_USAGE_3); - break; - - case 4: - *usage = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_KEY_SLOT_11_W0); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Efuse read software usage - * - * @param index: index of software usage - * @param program: usage value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - - if (index == 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_0); - } else if (index == 1) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_1); - } else if (index == 2) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_2); - } else if (index == 3) { - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_SW_USAGE_3); - } - - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse write MAC address - * - * @param mac[6]: MAC address buffer - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* The low 32 bits */ - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW, BL_RDWD_FRM_BYTEP(maclow)); - /* The high 16 bits */ - tmpVal = machigh[0] + (machigh[1] << 8); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Efuse Ctrl get zero bit count - * - * @param val: Value to count - * - * @return Zero bit count - * -*******************************************************************************/ -static uint32_t EF_Ctrl_Get_Byte_Zero_Cnt(uint8_t val) -{ - uint32_t cnt = 0; - uint32_t i = 0; - - for (i = 0; i < 8; i++) { - if ((val & (1 << i)) == 0) { - cnt += 1; - } - } - - return cnt; -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[6]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - uint32_t i = 0; - uint32_t cnt = 0; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - - /* Check parity */ - for (i = 0; i < 6; i++) { - cnt += EF_Ctrl_Get_Byte_Zero_Cnt(mac[i]); - } - - if ((cnt & 0x3f) == ((tmpVal >> 16) & 0x3f)) { - /* Change to network order */ - for (i = 0; i < 3; i++) { - tmpVal = mac[i]; - mac[i] = mac[5 - i]; - mac[5 - i] = tmpVal; - } - - return SUCCESS; - } else { - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief Efuse read MAC address - * - * @param mac[7]: MAC address buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]) -{ - uint8_t *maclow = (uint8_t *)mac; - uint8_t *machigh = (uint8_t *)(mac + 4); - uint32_t tmpVal; - - /* Trigger read data from efuse */ - EF_CTRL_LOAD_BEFORE_READ_R0; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_LOW); - BL_WRWD_TO_BYTEP(maclow, tmpVal); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH); - machigh[0] = tmpVal & 0xff; - machigh[1] = (tmpVal >> 8) & 0xff; - machigh[2] = (tmpVal >> 16) & 0xff; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for MAC address - * - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_MAC_Address(uint8_t program) -{ - uint32_t tmpVal; - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_DATA_0_WR_LOCK_WIFI_MAC); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } -} - -/****************************************************************************/ /** - * @brief Whether a value bits is all zero - * - * @param val: value to check - * @param start: start bit - * @param len: total length of bits to check - * - * @return 1 for all bits zero 0 for others - * -*******************************************************************************/ -uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len) -{ - uint32_t mask = 0; - - val = (val >> start); - - if (len >= 32) { - mask = 0xffffffff; - } else { - mask = (1 << len) - 1; - } - - if ((val & mask) == 0) { - return 1; - } else { - return 0; - } -} - -/****************************************************************************/ /** - * @brief Efuse read chip ID - * - * @param chipID[8]: Chip ID buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t chipID[8]) -{ - chipID[6] = 0; - chipID[7] = 0; - return EF_Ctrl_Read_MAC_Address_Raw(chipID); -} - -/****************************************************************************/ /** - * @brief Efuse write AES key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - /* slot_w0~slot_w3,slot_w11 in ef_data0 - slot_w4~slot_w10,in ef_data1 */ - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - - ARCH_MemCpy4(pAESKeyStart0 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - /* Every key is 4 words len*/ - ARCH_MemCpy4(pAESKeyStart1 + index * 4, keyData, len); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Efuse read AES key from specified region and index - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param keyData: key data buffer - * @param len: key data length in words - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len) -{ - uint32_t *pAESKeyStart0 = (uint32_t *)(EF_DATA_BASE + 0x1C); - uint32_t *pAESKeyStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - if ((index <= 3) || (index == 11)) { - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R0; - - index = ((index == 11) ? 5 : index); - - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart0 + index * 4, len); - } else if ((index < 11) && (index > 3)) { - /* Trigger read data from efuse*/ - EF_CTRL_LOAD_BEFORE_READ_R1; - index = index - 4; - /* Every key is 4 words len*/ - ARCH_MemCpy4(keyData, pAESKeyStart1 + index * 4, len); - } -} - -/****************************************************************************/ /** - * @brief Efuse lock writing for aes key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 8 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 17)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 15)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Efuse lock reading for aes key - * - * @param keyRegion: efuse key region - * @param index: index of key slot - * @param program: program to efuse entity or not - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program) -{ - uint32_t tmpVal; - - if ((index <= 3) || (index == 11)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - index = ((index == 11) ? 4 : index); - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_LOCK); - tmpVal |= (1 << (index + 27)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_0_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_0(); - } - } else if ((index < 11) && (index > 3)) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - index = index - 4; - - tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_1_LOCK); - tmpVal |= (1 << (index + 25)); - BL_WR_REG(EF_DATA_BASE, EF_DATA_1_LOCK, tmpVal); - - if (program) { - EF_Ctrl_Program_Efuse_1(); - } - } -} - -/****************************************************************************/ /** - * @brief Program data to efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Add delay for CLK to be stable */ - arch_delay_us(4); - - if (data != NULL) { - ARCH_MemCpy4(pEfuseStart0 + index, data, len); - } - - EF_Ctrl_Program_Efuse_0(); -} - -/****************************************************************************/ /** - * @brief Program data to efuse region 1 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct_R1(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - /* Add delay for CLK to be stable */ - arch_delay_us(4); - - if (data != NULL) { - ARCH_MemCpy4(pEfuseStart1 + index, data, len); - } - - EF_Ctrl_Program_Efuse_1(); -} - -/****************************************************************************/ /** - * @brief Read data from efuse region 0 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - - EF_CTRL_LOAD_BEFORE_READ_R0; - - ARCH_MemCpy4(data, pEfuseStart0 + index, len); -} - -/****************************************************************************/ /** - * @brief Read data from efuse region 1 - * - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct_R1(uint32_t index, uint32_t *data, uint32_t len) -{ - uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - - EF_CTRL_LOAD_BEFORE_READ_R1; - - ARCH_MemCpy4(data, pEfuseStart1 + index, len); -} - -/****************************************************************************/ /** - * @brief Program data to efuse entity - * - * @param region: index of efuse region - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Program_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len) -{ - if (region == 0) { - EF_Ctrl_Program_Direct_R0(index, data, len); - } else if (region == 1) { - EF_Ctrl_Program_Direct_R1(index, data, len); - } -} - -/****************************************************************************/ /** - * @brief Read efuse from register - * - * @param region: index of efuse region - * @param index: index of efuse in word - * @param data: data buffer - * @param len: data length - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Read_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len) -{ - if (region == 0) { - EF_Ctrl_Read_Direct_R0(index, data, len); - } else if (region == 1) { - EF_Ctrl_Read_Direct_R1(index, data, len); - } -} - -/****************************************************************************/ /** - * @brief Clear efuse data register - * - * @param region: index efuse region - * @param index: index of efuse in word - * @param len: data length - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len) -{ - uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + 0x00); - uint32_t *pEfuseStart1 = (uint32_t *)(EF_DATA_BASE + 0x80); - uint32_t i = 0; - - if (region == 0) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_0(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart0[index + i] = 0; - } - } else if (region == 1) { - /* Switch to AHB clock */ - EF_Ctrl_Sw_AHB_Clk_1(); - - /* Clear data */ - for (i = 0; i < len; i++) { - pEfuseStart1[index + i] = 0; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief efuse ctrl crc enable - * - * @param None - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_TRIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_INV_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DOUT_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, EF_CTRL_EF_CRC_INT_SET); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, EF_CTRL_EF_CRC_EN); - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc busy status - * - * @param None - * - * @return DISABLE or ENABLE - * -*******************************************************************************/ -BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Sts_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_BUSY); -} - -/****************************************************************************/ /** - * @brief efuse ctrl set golden value - * - * @param goldenValue: Crc golden value - * - * @return None - * -*******************************************************************************/ -void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue) -{ - BL_WR_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_4, goldenValue); -} - -/****************************************************************************/ /** - * @brief efuse ctrl get crc result - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EF_Ctrl_Crc_Result(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(EF_CTRL_BASE, EF_CTRL_EF_CRC_CTRL_0); - return (BL_Err_Type)BL_IS_REG_BIT_SET(tmpVal, EF_CTRL_EF_CRC_ERROR); -} - -/*@} end of group SEC_EF_CTRL_Public_Functions */ - -/*@} end of group SEC_EF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c deleted file mode 100644 index 8c4a3e62cd..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_emac.c +++ /dev/null @@ -1,785 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_emac.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_emac.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup EMAC - * @{ - */ - -/** @defgroup EMAC_Private_Macros - * @{ - */ -#define PHY_MAX_RETRY (0x3F) - -/*@} end of group EMAC_Private_Macros */ - -/** @defgroup EMAC_Private_Types - * @{ - */ - -/*@} end of group EMAC_Private_Types */ - -/** @defgroup EMAC_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *emacIntCbfArra[EMAC_ID_MAX][EMAC_INT_CNT] = { {NULL} }; -#endif - -static const uint32_t emacAddr[EMAC_ID_MAX] = { EMAC_BASE }; - -/*@} end of group EMAC_Private_Variables */ - -/** @defgroup EMAC_Global_Variables - * @{ - */ - -/*@} end of group EMAC_Global_Variables */ - -/** @defgroup EMAC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group EMAC_Private_Fun_Declaration */ - -/** @defgroup EMAC_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Set MAC Address - * - * @param emacId: EMAC ID type - * @param macAddr[6]: MAC address buffer array - * - * @return None - * -*******************************************************************************/ -static void EMAC_SetMACAddress(EMAC_ID_Type emacId, uint8_t macAddr[6]) -{ - uint32_t EMACx = emacAddr[emacId]; - BL_WR_REG(EMACx, EMAC_MAC_ADDR1, (macAddr[0] << 8) | macAddr[1]); - BL_WR_REG(EMACx, EMAC_MAC_ADDR0, (macAddr[2] << 24) | (macAddr[3] << 16) | (macAddr[4] << 8) | (macAddr[5] << 0)); -} - -/****************************************************************************/ /** - * @brief Set PHY Address - * - * @param emacId: EMAC ID type - * @param phyAddress: Phy address - * - * @return None - * -*******************************************************************************/ -void EMAC_Phy_SetAddress(EMAC_ID_Type emacId, uint16_t phyAddress) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set Phy Address */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FIAD, phyAddress); - BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set PHY Address - * - * @param emacId: EMAC ID type - * @param phyAddress: Phy address - * - * @return None - * -*******************************************************************************/ -void EMAC_Phy_Set_Full_Duplex(EMAC_ID_Type emacId, uint8_t fullDuplex) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set MAC duplex config */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_FULLD, fullDuplex); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Read PHY register - * - * @param emacId: EMAC ID type - * @param phyReg: PHY register - * @param regValue: PHY register value pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Phy_Read(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t *regValue) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set Register Address */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg); - BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal); - - /* Trigger read */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIICOMMAND); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RSTAT); - BL_WR_REG(EMACx, EMAC_MIICOMMAND, tmpVal); - - BL_DRV_DUMMY; - - do { - tmpVal = BL_RD_REG(EMACx, EMAC_MIISTATUS); - arch_delay_us(16); - } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY)); - - *regValue = BL_RD_REG(EMACx, EMAC_MIIRX_DATA); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Write PHY register - * - * @param emacId: EMAC ID type - * @param phyReg: PHY register - * @param regValue: PHY register value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Phy_Write(EMAC_ID_Type emacId, uint16_t phyReg, uint16_t regValue) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Set Register Address */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIADDRESS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RGAD, phyReg); - BL_WR_REG(EMACx, EMAC_MIIADDRESS, tmpVal); - - /* Set Write data */ - BL_WR_REG(EMACx, EMAC_MIITX_DATA, regValue); - - /* Trigger write */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIICOMMAND); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_WCTRLDATA); - BL_WR_REG(EMACx, EMAC_MIICOMMAND, tmpVal); - - BL_DRV_DUMMY; - - do { - tmpVal = BL_RD_REG(EMACx, EMAC_MIISTATUS); - } while (BL_IS_REG_BIT_SET(tmpVal, EMAC_MIIM_BUSY)); - - return SUCCESS; -} - -/*@} end of group EMAC_Private_Functions */ - -/** @defgroup EMAC_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Initialize EMAC module - * - * @param emacId: EMAC ID type - * @param cfg: EMAC configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Init(EMAC_ID_Type emacId, EMAC_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Disable clock gate */ - //GLB_AHB_Slave2_Clock_Gate(DISABLE, BL_AHB_SLAVE2_EXT_EMAC); - - /* Set MAC config */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RMII_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_RECSMALL, cfg->recvSmallFrame); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PAD, cfg->padEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_HUGEN, cfg->recvHugeFrame); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CRCEN, cfg->crcEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_NOPRE, cfg->noPreamble); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_BRO, cfg->recvBroadCast); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_PRO, ENABLE); - //tmpVal |= (1 << 7); /* local loopback in emac */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_IFG, cfg->interFrameGapCheck); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - /* Set inter frame gap value */ - BL_WR_REG(EMACx, EMAC_IPGT, cfg->interFrameGapValue); - - /* Set MII interface */ - tmpVal = BL_RD_REG(EMACx, EMAC_MIIMODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MIINOPRE, cfg->miiNoPreamble); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_CLKDIV, cfg->miiClkDiv); - BL_WR_REG(EMACx, EMAC_MIIMODE, tmpVal); - - /* Set collision */ - tmpVal = BL_RD_REG(EMACx, EMAC_COLLCONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXRET, cfg->maxTxRetry); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_COLLVALID, cfg->collisionValid); - BL_WR_REG(EMACx, EMAC_COLLCONFIG, tmpVal); - - /* Set frame length */ - tmpVal = BL_RD_REG(EMACx, EMAC_PACKETLEN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MINFL, cfg->minFrameLen); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, EMAC_MAXFL, cfg->maxFrameLen); - BL_WR_REG(EMACx, EMAC_PACKETLEN, tmpVal); - - EMAC_SetMACAddress(emacId, cfg->macAddr); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(EMAC_IRQn, EMAC0_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - - * @brief DeInitialize EMAC module - * - * @param emacId: EMAC ID type - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_DeInit(EMAC_ID_Type emacId) -{ - EMAC_Disable(emacId); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Initialize EMAC TX RX MDA buffer - * - * @param emacId: EMAC ID type - * @param handle: EMAC handle pointer - * @param txBuff: TX buffer - * @param txBuffCount: TX buffer count - * @param rxBuff: RX buffer - * @param rxBuffCount: RX buffer count - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_DMADescListInit(EMAC_ID_Type emacId, EMAC_Handle_Type *handle, uint8_t *txBuff, uint32_t txBuffCount, uint8_t *rxBuff, uint32_t rxBuffCount) -{ - uint32_t i = 0; - uint32_t EMACx = emacAddr[emacId]; - - /* Set the Ethernet handler env */ - handle->bd = (EMAC_BD_Desc_Type *)(uintptr_t)(EMACx + EMAC_DMA_DESC_OFFSET); - handle->txIndexEMAC = 0; - handle->txIndexCPU = 0; - handle->txBuffLimit = txBuffCount - 1; - /* The receive descriptors' address starts right after the last transmit BD. */ - handle->rxIndexEMAC = txBuffCount; - handle->rxIndexCPU = txBuffCount; - handle->rxBuffLimit = txBuffCount + rxBuffCount - 1; - - /* Fill each DMARxDesc descriptor with the right values */ - for (i = 0; i < txBuffCount; i++) { - /* Get the pointer on the ith member of the Tx Desc list */ - handle->bd[i].Buffer = (NULL == txBuff) ? 0 : (uint32_t)(uintptr_t)(txBuff + (ETH_MAX_PACKET_SIZE * i)); - handle->bd[i].C_S_L = 0; - } - - /* For the last TX DMA Descriptor, it should be wrap back */ - handle->bd[handle->txBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(TX_WR); - - for (i = txBuffCount; i < (txBuffCount + rxBuffCount); i++) { - /* Get the pointer on the ith member of the Rx Desc list */ - handle->bd[i].Buffer = (NULL == rxBuff) ? 0 : (uint32_t)(uintptr_t)(rxBuff + (ETH_MAX_PACKET_SIZE * (i - txBuffCount))); - handle->bd[i].C_S_L = (ETH_MAX_PACKET_SIZE << 16) | - EMAC_BD_FIELD_MSK(RX_IRQ) | - EMAC_BD_FIELD_MSK(RX_E); - } - - /* For the last RX DMA Descriptor, it should be wrap back */ - handle->bd[handle->rxBuffLimit].C_S_L |= EMAC_BD_FIELD_MSK(RX_WR); - - /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/ - BL_WR_REG(EMACx, EMAC_TX_BD_NUM, txBuffCount); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get TX MDA buffer descripter for data to send - * - * @param handle: EMAC handle pointer - * @param txDMADesc: TX DMA descriptor pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_DMATxDescGet(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type **txDMADesc) -{ - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Start TX - * - * @param handle: EMAC handle pointer - * @param txDMADesc: TX DMA descriptor pointer - * @param len: len - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_StartTx(EMAC_Handle_Type *handle, EMAC_BD_Desc_Type *txDMADesc, uint32_t len) -{ - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable EMAC module - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Enable(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Enable_TX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Enable_TX(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_SET_REG_BIT(tmpVal, EMAC_TXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Disable_TX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Disable_TX(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Enable_RX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Enable_RX(EMAC_ID_Type emacId) -{ - uint32_t tmpval; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC TX*/ - tmpval = BL_RD_REG(EMACx, EMAC_MODE); - tmpval = BL_SET_REG_BIT(tmpval, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpval); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Disable_RX - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Disable_RX(EMAC_ID_Type emacId) -{ - uint32_t tmpval; - uint32_t EMACx = emacAddr[emacId]; - - /* Disable EMAC RX*/ - tmpval = BL_RD_REG(EMACx, EMAC_MODE); - tmpval = BL_CLR_REG_BIT(tmpval, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpval); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable EMAC module - * - * @param emacId: EMAC ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_Disable(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Enable EMAC */ - tmpVal = BL_RD_REG(EMACx, EMAC_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_TXEN); - tmpVal = BL_CLR_REG_BIT(tmpVal, EMAC_RXEN); - BL_WR_REG(EMACx, EMAC_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC mask or unmask certain or all interrupt - * - * @param emacId: EMAC ID type - * @param intType: EMAC interrupt type - * @param intMask: EMAC interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_IntMask(EMAC_ID_Type emacId, EMAC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Check the parameters */ - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_MASK); - - /* Mask or unmask certain or all interrupt */ - if (MASK == intMask) { - tmpVal |= intType; - } else { - tmpVal &= (~intType); - } - - /* Write back */ - BL_WR_REG(EMACx, EMAC_INT_MASK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get EMAC interrupt status - * - * @param emacId: EMAC ID type - * @param intType: EMAC interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Sts_Type EMAC_GetIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Check the parameters */ - CHECK_PARAM(IS_EMAC_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_SOURCE); - - return (tmpVal & intType) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief Clear EMAC interrupt - * - * @param emacId: EMAC ID type - * @param intType: EMAC interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_ClrIntStatus(EMAC_ID_Type emacId, EMAC_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - /* Check the parameters */ - CHECK_PARAM(IS_EMAC_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_SOURCE); - - BL_WR_REG(EMACx, EMAC_INT_SOURCE, tmpVal | intType); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief EMAC_Int_Callback_Install - * - * @param emacId: EMAC ID type - * @param intIdx: EMAC_INT_Index - * @param cbFun: call back - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type EMAC_Int_Callback_Install(EMAC_ID_Type emacId, EMAC_INT_Index intIdx, intCallback_Type *cbFun) -{ - /* Check the parameters */ - - emacIntCbfArra[emacId][intIdx] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief EMAC_IRQHandler - * - * @param emacId: EMAC ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void EMAC_IRQHandler(EMAC_ID_Type emacId) -{ - uint32_t tmpVal; - uint32_t EMACx = emacAddr[emacId]; - - tmpVal = BL_RD_REG(EMACx, EMAC_INT_MASK); - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXB_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_TX_DONE); - - if (emacIntCbfArra[emacId][EMAC_INT_TX_DONE_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_TX_DONE_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXE_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_TX_ERROR); - - if (emacIntCbfArra[emacId][EMAC_INT_TX_ERROR_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_TX_ERROR_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_DONE) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXB_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_DONE); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_DONE_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_DONE_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_ERROR) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXE_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_ERROR); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_ERROR_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_ERROR_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_BUSY) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_BUSY_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_BUSY); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_BUSY_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_BUSY_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_TX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_TXC_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_TX_CTRL); - - if (emacIntCbfArra[emacId][EMAC_INT_TX_CTRL_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_TX_CTRL_IDX](); - } - } - - if (SET == EMAC_GetIntStatus(emacId, EMAC_INT_RX_CTRL) && !BL_IS_REG_BIT_SET(tmpVal, EMAC_RXC_M)) { - EMAC_ClrIntStatus(emacId, EMAC_INT_RX_CTRL); - - if (emacIntCbfArra[emacId][EMAC_INT_RX_CTRL_IDX]) { - emacIntCbfArra[emacId][EMAC_INT_RX_CTRL_IDX](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief EMAC0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void EMAC0_IRQHandler(void) -{ - EMAC_IRQHandler(EMAC0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief Request to pause TX - * - * @param emacId: EMAC ID type - * @param timeCount: Pause time count - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_TxPauseReq(EMAC_ID_Type emacId, uint16_t timeCount) -{ - uint32_t EMACx = emacAddr[emacId]; - - BL_WR_REG(EMACx, EMAC_TXCTRL, (1 << 16) | timeCount); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set hash value - * - * @param emacId: EMAC ID type - * @param hash0: Hash value one - * @param hash1: Hash value two - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_SetHash(EMAC_ID_Type emacId, uint32_t hash0, uint32_t hash1) -{ - uint32_t EMACx = emacAddr[emacId]; - - BL_WR_REG(EMACx, EMAC_HASH0_ADDR, hash0); - - BL_WR_REG(EMACx, EMAC_HASH1_ADDR, hash1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get fram maximum len and minimum - * - * @param emacId: EMAC ID type - * @param max: point to maximum fram len - * @param min: point to minimum fram len - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_GetFramLen(EMAC_ID_Type emacId, uint16_t * max, uint16_t *min) -{ - uint32_t EMACx = emacAddr[emacId]; - uint32_t tmpval; - - tmpval = BL_RD_REG(EMACx, EMAC_PACKETLEN); - *max = BL_GET_REG_BITS_VAL(tmpval, EMAC_MAXFL); - *min = BL_GET_REG_BITS_VAL(tmpval, EMAC_MINFL); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get BD numbers - * - * @param emacId: EMAC ID type - * @param bd: point to BD num - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type EMAC_GetBD(EMAC_ID_Type emacId, uint32_t *bd) -{ - uint32_t EMACx = emacAddr[emacId]; - - *bd = BL_RD_REG(EMACx, EMAC_TX_BD_NUM); - - return SUCCESS; -} -/*@} end of group EMAC_Public_Functions */ - -/*@} end of group EMAC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c deleted file mode 100644 index 55140d8174..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_misc.c +++ /dev/null @@ -1,2959 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_glb_misc.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_clock.h" -#include "bl808_glb.h" -#include "bl808_aon.h" -#include "bl808_hbn.h" -#include "bl808_pds.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup GLB - * @{ - */ - -/** @defgroup GLB_Private_Macros - * @{ - */ - - - -/*@} end of group GLB_Private_Macros */ - -/** @defgroup GLB_Private_Types - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL }; -#endif - -static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit); - -/*@} end of group GLB_Private_Types */ - -/** @defgroup GLB_Private_Variables - * @{ - */ - -/*@} end of group GLB_Private_Variables */ - -/** @defgroup GLB_Global_Variables - * @{ - */ - -/*@} end of group GLB_Global_Variables */ - -/** @defgroup GLB_Private_Fun_Declaration - * @{ - */ - -/*@} end of group GLB_Private_Fun_Declaration */ - -/** @defgroup GLB_Private_Functions - * @{ - */ - -/*@} end of group GLB_Private_Functions */ - -/** @defgroup GLB_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief GLB set display clock - * - * @param enable: ENABLE or DISABLE - * @param srcClk: source clock type - * @param evenDiv: divider in even number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv) -{ - uint32_t tmpVal = 0; - uint32_t evenNum = 0; - - CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk)); - CHECK_PARAM((evenDiv <= 0x7F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - if ((evenDiv >= 8) && (evenDiv <= 126)) { - evenNum = evenDiv & ~(1 << 0); - } else { - evenNum = evenDiv; - } - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - if(enable){ - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - }else{ - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB enable or disable ethernet clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Ethernet_CLK_From_UHSPLL(uint8_t enable) - -{ - uint32_t tmpVal = 0; - - /* uhspll_even_div_en */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG1); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UHSPLL_EVEN_DIV_EN); - } - BL_WR_REG(GLB_BASE, GLB_UHS_PLL_CFG1, tmpVal); - - return SUCCESS; -} - - - -/****************************************************************************/ /** - * @brief DSP get MCU interrupt status - * - * @param intType: MCU interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type GLB_DSP_Get_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType) -{ - CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType)); - - if (intType < 32) { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG16) & (1 << intType)) ? SET : RESET; - } else { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG17) & (1 << (intType - 32))) ? SET : RESET; - } -} - -/****************************************************************************/ /** - * @brief DSP set MCU interrupt mask - * - * @param intType: MCU interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_DSP_Set_MCU_IntMask(GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG18); - if (UNMASK != intMask) { - tmpVal |= (1 << intType); - } else { - tmpVal &= ~(1 << intType); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG18, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG19); - if (UNMASK != intMask) { - tmpVal |= (1 << (intType - 32)); - } else { - tmpVal &= ~(1 << (intType - 32)); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG19, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP clear MCU interrupt status - * - * @param intType: MCU interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_DSP_Clr_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_MCU_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG20); - tmpVal |= (1 << intType); - BL_WR_REG(GLB_BASE, GLB_CORE_CFG20, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG21); - tmpVal |= (1 << (intType - 32)); - BL_WR_REG(GLB_BASE, GLB_CORE_CFG21, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP set LP interrupt enable - * - * @param enable: ENABLE or DISABLE - * @param intType: LP interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_DSP_Set_LP_IntEn(uint8_t enable, GLB_LP_ALL_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG22); - if (enable) { - tmpVal |= (1 << intType); - } else { - tmpVal &= ~(1 << intType); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG22, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_CORE_CFG23); - if (enable) { - tmpVal |= (1 << (intType - 32)); - } else { - tmpVal &= ~(1 << (intType - 32)); - } - BL_WR_REG(GLB_BASE, GLB_CORE_CFG23, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP get LP interrupt status - * - * @param intType: LP interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type GLB_DSP_Get_LP_IntStatus(GLB_LP_ALL_INT_Type intType) -{ - CHECK_PARAM(IS_GLB_LP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG24) & (1 << intType)) ? SET : RESET; - } else { - return (BL_RD_REG(GLB_BASE, GLB_CORE_CFG25) & (1 << (intType - 32))) ? SET : RESET; - } -} - -/****************************************************************************/ /** - * @brief MCU get DSP interrupt status - * - * @param intType: DSP interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type GLB_MCU_Get_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType) -{ - CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA0) & (1 << intType)) ? SET : RESET; - } else { - return (BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_STA1) & (1 << (intType - 32))) ? SET : RESET; - } -} - -/****************************************************************************/ /** - * @brief MCU set DSP interrupt mask - * - * @param intType: DSP interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_MCU_Set_DSP_IntMask(GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0); - if (UNMASK != intMask) { - tmpVal |= (1 << intType); - } else { - tmpVal &= ~(1 << intType); - } - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK0, tmpVal); - } else { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1); - if (UNMASK != intMask) { - tmpVal |= (1 << (intType - 32)); - } else { - tmpVal &= ~(1 << (intType - 32)); - } - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_MASK1, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MCU clear DSP interrupt status - * - * @param intType: DSP interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_MCU_Clr_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_ALL_INT_TYPE(intType)); - - if (intType < 32) { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0); - tmpVal |= (1 << intType); - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_0, tmpVal); - } else { - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1); - tmpVal |= (1 << (intType - 32)); - BL_WR_REG(MM_MISC_BASE, MM_MISC_MM_INT_CLR_1, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set MTimer clock - * - * @param enable: enable or disable MTimer clock - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_MCU_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x3FF)); - - /* disable MTimer clock first */ - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST); - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - - tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN); - } - BL_WR_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set MTimer clock - * - * @param enable: enable or disable MTimer clock - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x3FF)); - - /* disable MTimer clock first */ - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_RST); - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - - tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_CPU_RTC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_C906_RTC_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_MISC_C906_RTC_EN); - } - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU_RTC, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set ADC clock - * - * @param enable: enable frequency divider or not - * @param clkSel: ADC clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3F)); - - /* disable ADC clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); - BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN); - } - BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set DMA clock - * - * @param enable: Enable or disable - * @param clk: DMA clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_GLB_DMA_CLK_ID_TYPE(clk)); - - if (clk >= GLB_DMA1_CLK_CH0) { - /* DMA1 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG1); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN); - if (enable) { - tmpVal2 |= (1 << (clk - GLB_DMA1_CLK_CH0)); - } else { - tmpVal2 &= (~(1 << (clk - GLB_DMA1_CLK_CH0))); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA2_CLK_EN, tmpVal2); - BL_WR_REG(GLB_BASE, GLB_DMA_CFG1, tmpVal); - } else { - /* DMA0 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG0); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN); - if (enable) { - tmpVal2 |= (1 << clk); - } else { - tmpVal2 &= (~(1 << clk)); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2); - BL_WR_REG(GLB_BASE, GLB_DMA_CFG0, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set peripheral DMA cn - * - * @param peri: peripheral - * @param cn: cn - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PERI_DMA_TYPE(peri)); - CHECK_PARAM(IS_GLB_PERI_DMA_CN_SEL_TYPE(cn)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG2); - switch (cn) { - case GLB_PERI_DMA_CN_SEL_DMA0: - tmpVal &= ~(1 << peri); - break; - case GLB_PERI_DMA_CN_SEL_DMA1: - tmpVal |= (1 << peri); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_DMA_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set IR clock divider - * - * @param enable: enable or disable IR clock - * @param clkSel: IR clock type - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select ir rx gpio (gpio11~gpio13) - * - * @param gpio: IR gpio selected - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio) -{ - uint32_t tmpVal = 0; - - /* Select gpio between gpio9 and gpio23 */ - if (gpio > 8 && gpio < 24) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 8); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - } - - /* Close ir rx */ - if (gpio == 0) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable ir led driver - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_IR_LED_Driver_Enable(void) -{ - uint32_t tmpVal = 0; - - /* Enable led driver */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable ir led driver - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_IR_LED_Driver_Disable(void) -{ - uint32_t tmpVal = 0; - - /* Disable led driver */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV); - BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set UART2 IO selection - * - * @param ioType: UART2 IO selection type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_Type ioType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_UART2_IO_SEL_TYPE(ioType)); - - /* Set uart2 io selection */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART2_IO_SEL, ioType); - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set UART clock - * - * @param enable: Enable or disable UART clock - * @param clkSel: UART clock type - * @param div: UART clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x7)); - CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel)); - - /* disable UART clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - /* Set div */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - /* Select clock source for uart */ - HBN_Set_UART_CLK_Sel(clkSel); - - /* Set enable or disable */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select UART signal function - * - * @param sig: UART signal - * @param fun: UART function - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun) -{ - uint32_t sig_pos = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig)); - CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun)); - - if (sig < GLB_UART_SIG_8) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG1); - sig_pos = (sig * 4); - /* Clear original val */ - tmpVal &= (~(0xf << sig_pos)); - /* Set new value */ - tmpVal |= (fun << sig_pos); - BL_WR_REG(GLB_BASE, GLB_UART_CFG1, tmpVal); - } else { - tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG2); - sig_pos = ((sig - 8) * 4); - /* Clear original val */ - tmpVal &= (~(0xf << sig_pos)); - /* Set new value */ - tmpVal |= (fun << sig_pos); - BL_WR_REG(GLB_BASE, GLB_UART_CFG2, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set sflash clock - * - * @param enable: enable or disable sflash clock - * @param clkSel: sflash clock type - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - /* disable SFLASH clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); - - if (clkSel == GLB_SFLASH_CLK_100M_CPUPLL) { - GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_CPUPLL_100M); - } - - /* clock divider */ - /* Select flash clock, all Flash CLKs are divied by PLL_480M */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div); - switch (clkSel) { - case GLB_SFLASH_CLK_120M_WIFIPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0); - break; - case GLB_SFLASH_CLK_XTAL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1); - break; - case GLB_SFLASH_CLK_100M_CPUPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3); - break; - case GLB_SFLASH_CLK_80M_MUXPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1); - break; - case GLB_SFLASH_CLK_BCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2); - break; - case GLB_SFLASH_CLK_96M_WIFIPLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); - - /* enable or disable flash clock */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set I2C clock - * - * @param enable: Enable or disable I2C clock - * @param clkSel: clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_I2C_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set I2S clock - * - * @param refClkEn: ref clock ENABLE or DISABLE - * @param refClkDiv: divider - * @param inRef: di ref clock - * @param outRef: do ref clock - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((refClkDiv <= 0x3F)); - CHECK_PARAM(IS_GLB_I2S_DI_REF_CLK_TYPE(inRef)); - CHECK_PARAM(IS_GLB_I2S_DO_REF_CLK_TYPE(outRef)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DO_REF_CLK_SEL, outRef); - if (refClkEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DI_REF_CLK_SEL, inRef); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV, refClkDiv); - BL_WR_REG(GLB_BASE, GLB_I2S_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set SPI clock - * - * @param enable: Enable or disable SPI clock - * @param clkSel: clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_SPI_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x1F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set PWM1 clock - * - * @param ioSel: io select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PWM1_IO_SEL_TYPE(ioSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM1_IO_SEL, ioSel); - BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set PWM2 clock - * - * @param ioSel: io select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PWM2_IO_Sel(GLB_PWM2_IO_SEL_Type ioSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PWM2_IO_SEL_TYPE(ioSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM2_IO_SEL, ioSel); - BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set PDM clock - * - * @param ioSel: io select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PDM_IO_Sel(GLB_PDM_IO_SEL_Type ioSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PDM_IO_SEL_TYPE(ioSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM_IO_SEL, ioSel); - BL_WR_REG(GLB_BASE, GLB_PDM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DIG clock source - * - * @param clkSel: DIG clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel) -{ - uint32_t tmpVal; - uint32_t dig512kEn; - uint32_t dig32kEn; - - CHECK_PARAM(IS_GLB_DIG_CLK_TYPE(clkSel)); - - /* disable DIG512K and DIG32K clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN); - dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - /* repristinate DIG512K and DIG32K clock */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set DIG 512K clock - * - * @param enable: enable or disable DIG 512K clock - * @param compensationEn: enable or disable DIG 512K clock compensation - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensationEn, uint8_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x7F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (compensationEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN); - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set DIG 32K clock - * - * @param enable: enable or disable DIG 32K clock - * @param compensationEn: enable or disable DIG 32K clock compensation - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM((div <= 0x7FF)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (compensationEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN); - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief platform wakeup becomes one of pds_wakeup source - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP); - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief mcu gpio timer clock select - * - * @param gpioPin: gpio pin number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - switch (gpioPin & 0x3) { - case 0: /* inout_sig_0 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 0); - break; - case 1: /* inout_sig_1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 1); - break; - case 2: /* inout_sig_2 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 2); - break; - case 3: /* inout_sig_3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 3); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief dsp gpio timer clock select - * - * @param gpioPin: gpio pin number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Sel_DSP_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - switch (gpioPin & 0x3) { - case 0: /* inout_sig_0 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 0); - break; - case 1: /* inout_sig_1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 1); - break; - case 2: /* inout_sig_2 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 2); - break; - case 3: /* inout_sig_3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_MM_TMR_CLK_SEL, 3); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out0 select - * - * @param clkOutType: chip clock out0 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out0 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out1 select - * - * @param clkOutType: chip clock out1 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out1 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out2 select - * - * @param clkOutType: chip clock out2 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out2 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out3 select - * - * @param clkOutType: chip clock out3 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out3 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief csi dsi clock select - * - * @param csiClkSel: csi clock select - * @param dsiClkSel: dsi clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_CSI_DSI_CLK_Sel(GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CSI_TXCLKESC_SEL, csiClkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DSI_TXCLKESC_SEL, dsiClkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief BMX init - * - * @param BmxCfg: BMX config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((BmxCfg->timeoutEn) <= 0x1F); - CHECK_PARAM(IS_BMX_ARB_TYPE(BmxCfg->arbMod)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_TIMEOUT_EN, BmxCfg->timeoutEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_ARB_MODE, BmxCfg->arbMod); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(BMX_MCU_TO_IRQn, BMX_TO_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get BMX TO status - * - * @param None - * - * @return BMX TO status - * -*******************************************************************************/ -uint8_t GLB_Get_BMX_TO_Status(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_BMX_CFG0), GLB_STS_BMX_TIMEOUT_STS); -} - -/****************************************************************************/ /** - * @brief clear BMX TO status - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Clr_BMX_TO_Status(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR); - BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief BMX timeout interrupt callback install - * - * @param intType: BMX timeout interrupt type - * @param cbFun: callback - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType)); - - glbBmxToIntCbfArra[intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief BMX Time Out interrupt IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void BMX_TO_IRQHandler(void) -{ - BMX_TO_INT_Type intType; - - for (intType = 0; intType < BMX_TO_INT_ALL; intType++) { - if (glbBmxToIntCbfArra[intType] != NULL) { - glbBmxToIntCbfArra[intType](); - } - } - GLB_Clr_BMX_TO_Status(); -} -#endif - -/****************************************************************************/ /** - * @brief set audio auto clock - * - * @param divEn: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (divEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio ADC clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio DAC clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_DAC_CLK(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_DAC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio PDM clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Audio_PDM_CLK(uint8_t enable, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_PDM_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set audio PDM clock - * - * @param enable: ENABLE or DISABLE - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_PADC_CLK(uint8_t enable, uint16_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((div <= 0x3F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PADC_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PADC_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief invert eth rx clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK); - } - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief invert eth tx clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK); - } - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief invert eth ref clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O); - } - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set eth ref clock select - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_ETH_REF_CLK_OUT_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel); - BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set CAM clock - * - * @param enable: Enable or disable CAM clock - * @param clkSel: CAM clock type - * @param div: clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set SDH clock - * - * @param enable: Enable or disable - * @param clkSel: SDH clock type - * @param div: clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_SDH_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL, clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief swap UART gpio pins sig function - * - * @param group: UART swap set group - * @param swap: swap or no swap - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal2 = 0; - - CHECK_PARAM(IS_GLB_UART_SIG_SWAP_GRP_TYPE(group)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET); - if (swap) { - tmpVal2 |= (1 << group); - } else { - tmpVal2 &= ~(1 << group); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, tmpVal2); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief swap DSP SPI0 MOSI with MISO - * - * @param newState: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_SWAP, newState); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select DSP SPI_0 act mode - * - * @param mod: SPI work mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_SPI_MASTER_MODE, mod); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set L2SRAM - * - * @param h2pfSramRel: make pfh_64k0,pfh_64k1,pfh_64k0 writable - * @param vramSramRel: make l2_vram writable - * @param dspl2SramRel: make dspl2_32k0,dspl2_32k1 writable - * @param blaiSramRel: make blai_64k0,blai_64k1 writable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_H2PF_SRAM_REL, h2pfSramRel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_VRAM_SRAM_REL, vramSramRel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_DSPL2_SRAM_REL, dspl2SramRel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_BLAI_SRAM_REL, blaiSramRel); - BL_WR_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL, tmpVal); - - /* Make the above settings effective */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SYSRAM_SET, 1); - BL_WR_REG(MM_GLB_BASE, MM_MISC_VRAM_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select DSP SPI_0 act mode - * - * @param mod: SPI work mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Select SPI_0 act mode - * - * @param mod: SPI work mode - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod); - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set flash io parameter - * - * @param selEmbedded: Select embedded flash pin - * @param swap: Select embedded flash swap io0 with io3 - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0); - if (selEmbedded) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); - if (swap) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0); - } - BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal); - - if (selEmbedded) { - GLB_Embedded_Flash_Pad_Enable(); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief gate pll clock cgen - * - * @param clk: pll clock cgen - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3); - tmpVal &= (~(1 << clk)); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief gate pll clock cgen - * - * @param clk: pll clock cgen - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3); - tmpVal |= (1 << clk); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select PKA clock source - * - * @param clkSel: PKA clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief mcu system part reset - * - * @param sysPart: mcu reset part - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_MCU_SW_SYSTEM_TYPE(sysPart)); - - /* reset=0 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - BL_DRV_DUMMY; - /* reset=1 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal |= (1 << sysPart); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - BL_DRV_DUMMY; - /* reset=1 */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Software system reset - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void) -{ - uint32_t tmpVal; - - /* Swicth DSP clock to RC32M, no divider */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - - /* reset M0/M1/LP/SYS(bus+...+D0+D1) */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - /* waiting for reset */ - while (1) { - arch_delay_us(10); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Software CPU reset - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void) -{ - uint32_t tmpVal; - - GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID; - - /* Do reset */ - core = GLB_Get_Core_Type(); - - switch (core) { - case GLB_CORE_ID_M0: - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - case GLB_CORE_ID_D0: - /* Swicth DSP clock to RC32M, no divider */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - break; - case GLB_CORE_ID_LP: - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - default: - break; - } - - /* waiting for reset */ - while (1) { - arch_delay_us(10); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Software power on reset - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void) -{ - uint32_t tmpVal; - - /* Swicth DSP clock to RC32M, no divider */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - - /* Swicth MCU clock to RC32M, no divider */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - - /* Do reset */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - - /* waiting for reset */ - while (1) { - arch_delay_us(10); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set auto calc xtal type value - * - * @param calcXtalType: auto calc xtal type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_XTAL_TYPE(calcXtalType)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0); - tmpVal = tmpVal & 0xffff0000; - tmpVal |= GLB_AUTO_CALC_XTAL_FLAG_VALUE; - tmpVal |= calcXtalType; - BL_WR_REG(GLB_BASE, GLB_HW_RSV0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set auto calc xtal type value - * - * @param calcXtalType: auto calc xtal type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0); - if ((tmpVal & GLB_AUTO_CALC_XTAL_FLAG_MASK) == GLB_AUTO_CALC_XTAL_FLAG_VALUE) { - *calcXtalType = (tmpVal & 0xff); - return SUCCESS; - } else { - *calcXtalType = 0; - return ERROR; - } -} - -/****************************************************************************/ /** - * @brief set flash id value - * - * @param idValue: flash id value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue) -{ - BL_WR_REG(GLB_BASE, GLB_HW_RSV1, idValue); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get flash id value - * - * @param None - * - * @return flash id - * -*******************************************************************************/ -uint32_t GLB_Get_Flash_Id_Value(void) -{ - return BL_RD_REG(GLB_BASE, GLB_HW_RSV1); -} - -/****************************************************************************/ /** - * @brief set sram_ret value - * - * @param value: value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SRAM_RET(uint32_t value) -{ - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG0, value); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get sram_ret value - * - * @param None - * - * @return value - * -*******************************************************************************/ -uint32_t GLB_Get_SRAM_RET(void) -{ - return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG0); -} - -/****************************************************************************/ /** - * @brief set sram_slp value - * - * @param value: value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value) -{ - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG1, value); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get sram_slp value - * - * @param None - * - * @return value - * -*******************************************************************************/ -uint32_t GLB_Get_SRAM_SLP(void) -{ - return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG1); -} - -/****************************************************************************/ /** - * @brief set sram_param value - * - * @param value: value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value) -{ - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG2, value); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get sram_parm value - * - * @param None - * - * @return value - * -*******************************************************************************/ -uint32_t GLB_Get_SRAM_PARM(void) -{ - return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG2); -} - -/****************************************************************************/ /** - * @brief select EM type - * - * @param emType: EM type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_EM_TYPE(emType)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_CFG3); - switch (emType) { - case GLB_WRAM160KB_EM0KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); - break; - case GLB_WRAM144KB_EM16KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03); - break; - case GLB_WRAM128KB_EM32KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x0F); - break; - case GLB_WRAM112KB_EM48KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x3F); - break; - case GLB_WRAM96KB_EM64KB: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0xFF); - break; - default: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03); - break; - } - BL_WR_REG(GLB_BASE, GLB_SRAM_CFG3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set psram clock - * - * @param id: psram id - * @param enable: enable or disable psram clock - * @param pll: psram pll clock - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -__WEAK -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div) -{ - uint32_t tmpVal = 0; - uint32_t en = 0; - - CHECK_PARAM(IS_GLB_PSRAM_PLL_TYPE(pll)); - CHECK_PARAM((div <= 0x3)); - - en = enable ? 1 : 0; - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3); - switch (pll) { - case GLB_PSRAM_EMI_CPUPLL_400M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_CPUPLL_400M, en); - break; - case GLB_PSRAM_EMI_WIFIPLL_320M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_WIFIPLL_320M, en); - break; - case GLB_PSRAM_EMI_AUPLL_DIV1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CGEN_EMI_AUPLL_DIV1, en); - break; - default: - break; - } - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0); - if (id == 1) { - /* psram B */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_EN, en); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL, pll); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV, div); - } - BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief trim ldo18io vout - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18IO_Vout(void) -{ - Efuse_Ana_LDO18IO_VOUT_Trim_Type trim; - uint32_t tmpVal = 0; - - EF_Ctrl_Read_LDO18IO_Vout_Trim(&trim); - if (trim.trimLdo18ioVoutEn) { - if (trim.trimLdo18ioVoutParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18ioVoutVal, 4)) { - tmpVal = BL_RD_REG(AON_BASE, AON_LDO18IO); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO18IO_VOUT_TRIM_AON, trim.trimLdo18ioVoutVal); - BL_WR_REG(AON_BASE, AON_LDO18IO, tmpVal); - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief trim ldo18flash vout - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Trim_LDO18FLASH_Vout(void) -{ - Efuse_Ana_LDO18FLASH_Trim_Type trim; - uint32_t tmpVal = 0; - - EF_Ctrl_Read_LDO18FLASH_Trim(&trim); - if (trim.trimLdo18flashVoutAonEn) { - if (trim.trimLdo18flashVoutAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimLdo18flashVoutAon, 4)) { - tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18FLASH); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18FLASH_VOUT_TRIM, trim.trimLdo18flashVoutAon); - BL_WR_REG(GLB_BASE, GLB_LDO18FLASH, tmpVal); - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief set cnn clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: cnn clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_CNN_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CNN_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set display clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: display clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_DP_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0xF)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set dsp2 clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: dsp2 clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_DSP2_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set h264 clock - * - * @param enable: ENABLE or DISABLE - * @param clkSel: h264 clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_H264_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV, div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL, clkSel); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_H264_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_CODEC_CLK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set spi clock - * - * @param enable: ENABLE or DISABLE - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_SPI_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL, clkSel); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_SPI_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set uart0 clock - * - * @param enable: ENABLE or DISABLE - * @param uartClk: mm glb uart clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART0_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set uart1 clock - * - * @param enable: ENABLE or DISABLE - * @param uartClk: mm glb uart clock type - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_UART1_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_UART_CLK_TYPE(uartClk)); - CHECK_PARAM((div <= 0x7)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL, uartClk); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_UART1_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set i2c0 clock - * - * @param enable: ENABLE or DISABLE - * @param divEn: div enable - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_I2C0_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_EN); - } - if (divEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C0_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set i2c1 clock - * - * @param enable: ENABLE or DISABLE - * @param divEn: div enable - * @param div: div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_I2C_CLK_TYPE(clkSel)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL, clkSel); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV, div); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_EN); - } - if (divEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_I2C1_CLK_DIV_EN); - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_PERI3, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief sw sys reset - * - * @param sysPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_SW_SYSTEM_TYPE(sysPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal |= (1 << sysPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal &= ~(1 << sysPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief peripheral reset - * - * @param periPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_PERIPHERAL_TYPE(periPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI); - tmpVal &= ~(1 << periPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI); - tmpVal |= (1 << periPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI); - tmpVal &= ~(1 << periPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_MM_PERI, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief dsp2 sub reset - * - * @param dsp2Part: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_DSP2_SUB_TYPE(dsp2Part)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB); - tmpVal &= ~(1 << dsp2Part); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB); - tmpVal |= (1 << dsp2Part); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB); - tmpVal &= ~(1 << dsp2Part); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief codec sub reset - * - * @param codecPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_CODEC_SUB_TYPE(codecPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB); - tmpVal &= ~(1 << codecPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB); - tmpVal |= (1 << codecPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB); - tmpVal &= ~(1 << codecPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_CODEC_SUB, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief image sensor reset - * - * @param imageSensorPart: reset type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_IMAGE_SENSOR_TYPE(imageSensorPart)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL); - tmpVal &= ~(1 << imageSensorPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL); - tmpVal |= (1 << imageSensorPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL); - tmpVal &= ~(1 << imageSensorPart); - BL_WR_REG(MM_GLB_BASE, MM_GLB_IMAGE_SENSOR_CTRL, tmpVal); - - return SUCCESS; -} - -/*@} end of group GLB_Public_Functions */ - -/*@} end of group GLB */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c deleted file mode 100644 index 39bc803983..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_pll.c +++ /dev/null @@ -1,3050 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_glb_pll.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_clock.h" -#include "bl808_glb.h" -#include "bl808_aon.h" -#include "bl808_hbn.h" -#include "bl808_pds.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup GLB - * @{ - */ - -/** @defgroup GLB_Private_Macros - * @{ - */ -#define GLB_CLK_SET_DUMMY_WAIT \ - { \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - __NOP(); \ - } -#define GLB_CLK_SET_DUMMY_TIMEOUT (0xFF) -#define GLB_FREQ_RC32M (32000000) - -/*@} end of group GLB_Private_Macros */ - -/** @defgroup GLB_Private_Types - * @{ - */ - -/*@} end of group GLB_Private_Types */ - -/** @defgroup GLB_Private_Variables - * @{ - */ - - - -/* WiFi PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */ - { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */ -}; - -/* Audio PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */ -}; - -/* CPU PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */ -}; - -/* MIPI PLL Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &mipiPllBasicCfg_24M, 0x1F400 }, /*!< XTAL is 24M */ - { &mipiPllBasicCfg_32M, 0x2EE00 }, /*!< XTAL is 32M */ - { &mipiPllBasicCfg_38P4M, 0x27100 }, /*!< XTAL is 38.4M */ - { &mipiPllBasicCfg_40M, 0x25800 }, /*!< XTAL is 40M */ - { &mipiPllBasicCfg_26M, 0x1CD89 }, /*!< XTAL is 26M */ - { &mipiPllBasicCfg_32M, 0x2EE00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2100 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */ - { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */ - { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */ - { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1400MCfg_24M, 0x1D2AA }, /*!< XTAL is 24M */ - { &uhsPll1400MCfg_32M, 0x2BC00 }, /*!< XTAL is 32M */ - { &uhsPll1400MCfg_38P4M, 0x24755 }, /*!< XTAL is 38.4M */ - { &uhsPll1400MCfg_40M, 0x23000 }, /*!< XTAL is 40M */ - { &uhsPll1400MCfg_26M, 0x1AEC4 }, /*!< XTAL is 26M */ - { &uhsPll1400MCfg_32M, 0x2BC00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1500 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1500MCfg_24M, 0x1F400 }, /*!< XTAL is 24M */ - { &uhsPll1500MCfg_32M, 0x2EE00 }, /*!< XTAL is 32M */ - { &uhsPll1500MCfg_38P4M, 0x27100 }, /*!< XTAL is 38.4M */ - { &uhsPll1500MCfg_40M, 0x25800 }, /*!< XTAL is 40M */ - { &uhsPll1500MCfg_26M, 0x1CD89 }, /*!< XTAL is 26M */ - { &uhsPll1500MCfg_32M, 0x2EE00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1600 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */ - { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */ - { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */ - { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll400BasicCfg_24M, 0x8555 }, /*!< XTAL is 24M */ - { &uhsPll400BasicCfg_32M, 0xC800 }, /*!< XTAL is 32M */ - { &uhsPll400BasicCfg_38P4M, 0xA6AA }, /*!< XTAL is 38.4M */ - { &uhsPll400BasicCfg_40M, 0xA000 }, /*!< XTAL is 40M */ - { &uhsPll400BasicCfg_26M, 0x7B13 }, /*!< XTAL is 26M */ - { &uhsPll400BasicCfg_32M, 0xC800 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 667 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll667BasicCfg_24M, 0xDE55 }, /*!< XTAL is 24M */ - { &uhsPll667BasicCfg_32M, 0x14D80 }, /*!< XTAL is 32M */ - { &uhsPll667BasicCfg_38P4M, 0x115EA }, /*!< XTAL is 38.4M */ - { &uhsPll667BasicCfg_40M, 0x10ACC }, /*!< XTAL is 40M */ - { &uhsPll667BasicCfg_26M, 0xCD3B }, /*!< XTAL is 26M */ - { &uhsPll667BasicCfg_32M, 0x14D80 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 800 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 0, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll800BasicCfg_24M, 0x10AAA }, /*!< XTAL is 24M */ - { &uhsPll800BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */ - { &uhsPll800BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &uhsPll800BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */ - { &uhsPll800BasicCfg_26M, 0xF627 }, /*!< XTAL is 26M */ - { &uhsPll800BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1066 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1066BasicCfg_24M, 0x16355 }, /*!< XTAL is 24M */ - { &uhsPll1066BasicCfg_32M, 0x21500 }, /*!< XTAL is 32M */ - { &uhsPll1066BasicCfg_38P4M, 0x1BC2A }, /*!< XTAL is 38.4M */ - { &uhsPll1066BasicCfg_40M, 0x1AA66 }, /*!< XTAL is 40M */ - { &uhsPll1066BasicCfg_26M, 0x14800 }, /*!< XTAL is 26M */ - { &uhsPll1066BasicCfg_32M, 0x21500 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2000 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */ - { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */ - { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */ - { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */ -}; - -/*@} end of group GLB_Private_Variables */ - -/** @defgroup GLB_Global_Variables - * @{ - */ - -/*@} end of group GLB_Global_Variables */ - -/** @defgroup GLB_Private_Fun_Declaration - * @{ - */ - -/*@} end of group GLB_Private_Fun_Declaration */ - -/** @defgroup GLB_Private_Functions - * @{ - */ - -/*@} end of group GLB_Private_Functions */ - -/** @defgroup GLB_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief set mcu muxpll 160M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_160M_Sel(GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get mcu muxpll 160M selection - * - * @param None - * - * @return 160M mux select value - * -*******************************************************************************/ -GLB_MCU_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_160M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_MCU_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL)); -} - -/****************************************************************************/ /** - * @brief set top muxpll 80M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_80M_Sel(GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get mcu muxpll 80M selection - * - * @param None - * - * @return 80M mux select value - * -*******************************************************************************/ -GLB_MCU_MUXPLL_80M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_80M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_MCU_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL)); -} - -/****************************************************************************/ /** - * @brief set dsp muxpll 320M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_MUXPLL_320M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get dsp muxpll 320M selection - * - * @param None - * - * @return dsp 320M mux select value - * -*******************************************************************************/ -GLB_DSP_MUXPLL_320M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_320M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_DSP_MUXPLL_320M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL)); -} - -/****************************************************************************/ /** - * @brief set dsp muxpll 240M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_MUXPLL_240M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get dsp muxpll 240M selection - * - * @param None - * - * @return dsp 240M mux select value - * -*******************************************************************************/ -GLB_DSP_MUXPLL_240M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_240M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_DSP_MUXPLL_240M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL)); -} - -/****************************************************************************/ /** - * @brief set dsp muxpll 160M selection - * - * @param clkSel: clock selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_MUXPLL_160M_CLK_SEL_TYPE(clkSel)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL, clkSel); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get dsp muxpll 160M selection - * - * @param None - * - * @return dsp 160M mux select value - * -*******************************************************************************/ -GLB_DSP_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_DSP_Muxpll_160M_Sel(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1); - return (GLB_DSP_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL)); -} - -/****************************************************************************/ /** - * @brief power on all PLL clock - * - * @param xtalType: XTAL frequency type - * @param pllType: only power on xtal - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type pllType) -{ - uint32_t tmpVal; - GLB_CORE_ID_Type coreType; - HBN_MCU_XCLK_Type mcuXclkSel; - HBN_MCU_ROOT_CLK_Type mcuRootClkSel; - GLB_DSP_XCLK_Type dspXclkSel; - GLB_DSP_ROOT_CLK_Type dspRootClkSel; - volatile GLB_PLL_REF_CLK_Type refClk; - - CHECK_PARAM(IS_GLB_XTAL_TYPE(xtalType)); - CHECK_PARAM((pllType < (GLB_PLL_UHSPLL * 2))); - - if (xtalType == GLB_XTAL_NONE) { - return ERROR; - } - - if (xtalType != GLB_XTAL_RC32M) { - /* power on xtal first */ - AON_Power_On_XTAL(); - } - - coreType = GLB_Get_Core_Type(); - if ((GLB_CORE_ID_D0 == coreType)) { - /* D0 */ - /* Before config XTAL and PLL ,make sure root clk is from RC32M */ - dspXclkSel = GLB_Get_DSP_XCLK_Sel(); - dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel(); - if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) { - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - } - GLB_Set_DSP_System_CLK_Div(0, 0); - } else { - /* M0 or LP or invalid(use M0 instead) */ - /* Before config XTAL and PLL ,make sure root clk is from RC32M */ - mcuXclkSel = HBN_Get_MCU_XCLK_Sel(); - mcuRootClkSel = HBN_Get_MCU_Root_CLK_Sel(); - if ((mcuXclkSel != HBN_MCU_XCLK_RC32M) || (mcuRootClkSel != HBN_MCU_ROOT_CLK_XCLK)) { - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - } - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - } - - HBN_Set_Xtal_Type(xtalType); - - if (GLB_PLL_NONE == pllType) { - GLB_CLK_SET_DUMMY_WAIT; - return SUCCESS; - } - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - /* power on wifipll */ - if (pllType & GLB_PLL_WIFIPLL) { - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &wifiPllCfg_960M[xtalType], 0); - } - - /* power on aupll */ - if (pllType & GLB_PLL_AUPLL) { - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &audioPllCfg_442P368M[xtalType], 0); - } - - /* power on cpupll */ - if (pllType & GLB_PLL_CPUPLL) { - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &cpuPllCfg_380M[xtalType], 0); - } - - /* power on mipipll */ - if (pllType & GLB_PLL_MIPIPLL) { - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &mipiPllCfg_1500M[xtalType], 0); - } - - /* power on uhspll */ - if (pllType & GLB_PLL_UHSPLL) { - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &uhsPllCfg_2100M[xtalType], 0); - } - - arch_delay_us(75); - - if (xtalType != GLB_XTAL_RC32M) { - /* if power on xtal, always set xclk from xtal */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL); - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL); - } - - /* enable all PLL clock output */ - /* GLB reg_pll_en = 1, cannot be zero */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); - /* MM_GLB reg_pll_en = 1, cannot be zero */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_PLL_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power off wifi audio cpu PLL - * - * @param pllType: PLL XTAL type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_Type pllType) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* cfg0 : pu_aupll=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* cfg0 : pu_aupll_sfreg=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB wifi audio cpu PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) { - /* wifipll_refclk_sel different from other's pll, 1 means xtal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power on PLL - * - * @param pllType: PLL XTAL type - * @param cfg: GLB PLL configuration - * @param waitStable: wait PLL clock stable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - /* unknown */ - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* Step1:config parameter */ - /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal); - - /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal); - - /* cfg4:Set aupll_sel_sample_clk */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal); - - /* cfg5:Set aupll_vco_speed */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - - /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal); - - /* Step2:config pu */ - /* cfg0 : pu_aupll_sfreg=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* cfg0 : pu_wifipll=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */ - if (GLB_WAC_PLL_AUPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((cfg->clkpllSdmin==0x12D0E)||(cfg->clkpllSdmin==0x1C395)||(cfg->clkpllSdmin==0x17851)||(cfg->clkpllSdmin==0x16944)||(cfg->clkpllSdmin==0x115E5)) { - /* 451.548 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14); - } else { - /* 442.368 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - } - - /* Step4:enable output clock */ - /* wifipll : cfg5, wifipll_vco_div3_en=1 */ - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - } - /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1); - } - /* cfg8 : wifipll/aupll/cpupll clock enable */ - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10); - break; - case GLB_WAC_PLL_AUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6); - break; - case GLB_WAC_PLL_CPUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5); - break; - default: - break; - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal); - - if (waitStable) { - /* Wait 1.5*30us */ - arch_delay_us(45); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB enable or disable USB clock - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable) -{ - uint32_t tmpVal = 0; - - /* pu_usbpll_mmdiv */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV); - } - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - - /* toggle usbpll_rstb */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB); - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB); - BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power off mipi uhs PLL - * - * @param pllType: PLL XTAL type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_Power_Off_MU_TYPE(pllType)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* cfg0 : pu_aupll=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* cfg0 : pu_aupll_sfreg=0 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB mipi uhs PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB power on PLL - * - * @param pllType: PLL XTAL type - * @param cfg: GLB PLL configuration - * @param waitStable: wait PLL stable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - /* unknown */ - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* Step1:config parameter */ - /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - /* cfg4:Set aupll_sel_sample_clk */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal); - - /* cfg5:Set aupll_vco_speed */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - - /* cfg1: uhspll_even_div_en and uhspll_even_div_ratio */ - if (GLB_MU_PLL_UHSPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_EN, cfg->basicCfg->clkpllEvenDivEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_EVEN_DIV_RATIO, cfg->basicCfg->clkpllEvenDivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - } - - /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal); - - /* Step2:config pu */ - /* cfg0 : pu_aupll_sfreg=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* cfg0 : pu_wifipll=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - if (waitStable) { - /* Wait 1.5*30us */ - arch_delay_us(45); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set System clock divider - * - * @param mcuClkDiv: HCLK divider - * @param mcuPBclkDiv: BCLK divider - * @param lpClkDiv: LP clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv) -{ - uint32_t tmpVal; - uint32_t timeout = 1024; - HBN_MCU_XCLK_Type xclkSel; - HBN_MCU_ROOT_CLK_Type rootClkSel; - - /* get root clock */ - xclkSel = HBN_Get_MCU_XCLK_Sel(); - rootClkSel = HBN_Get_MCU_Root_CLK_Sel(); - - if ((xclkSel != HBN_MCU_XCLK_RC32M) || (rootClkSel != HBN_MCU_ROOT_CLK_XCLK)) { - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - } - - /* config hclk_div=mcuClkDiv */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, mcuClkDiv); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); - - /* config bclk_div=mcuPBclkDiv */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, mcuPBclkDiv); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal); - /* bclk act pulse */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV_ACT_PULSE, 1); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal); - - timeout = 1024; - do { - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE); - } while ((--timeout) && (!tmpVal)); - if (!timeout) { - return ERROR; - } - - /* config lp clock div=lpClkDiv */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV, lpClkDiv); - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG7, tmpVal); - /* bclk act pulse */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PICO_CLK_DIV_ACT_PULSE, 1); - BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal); - - timeout = 1024; - do { - tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_PICO_CLK_PROT_DONE); - } while ((--timeout) && (!tmpVal)); - if (!timeout) { - return ERROR; - } - - /* recover root clock */ - HBN_Set_MCU_XCLK_Sel(xclkSel); - HBN_Set_MCU_Root_CLK_Sel(rootClkSel); - - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get System clock divider - * - * @param mcuClkDiv: HCLK divider - * @param mcuPBclkDiv: BCLK divider - * @param lpClkDiv: LP clock divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv) -{ - *mcuClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV); - *mcuPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV); - *lpClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG7), PDS_REG_PICO_DIV); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set mcu System clock - * - * @param clkFreq: mcu system clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq) -{ - uint32_t tmpVal; - HBN_MCU_XCLK_Type mcuXclkSel; - - CHECK_PARAM(IS_GLB_MCU_SYS_CLK_TYPE(clkFreq)); - - /* get xclk&&rootclk clock */ - mcuXclkSel = HBN_Get_MCU_XCLK_Sel(); - - /* change root clock to rc32m */ - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - - /* select pll output clock before select root clock */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1); - switch (clkFreq) { - case GLB_MCU_SYS_CLK_CPUPLL_400M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 0); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_240M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 2); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_320M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 3); - break; - default: - break; - } - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal); - - /* select root clock */ - switch (clkFreq) { - case GLB_MCU_SYS_CLK_RC32M: - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - break; - case GLB_MCU_SYS_CLK_XTAL: - GLB_Set_MCU_System_CLK_Div(0, 0, 0); - HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL); - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK); - break; - case GLB_MCU_SYS_CLK_CPUPLL_400M: - /* For high speed, set DIV first */ - GLB_Set_MCU_System_CLK_Div(1, 2, 1); - /* Set IROM 2T Access 0 since we use RC32M, unuseful now */ - /* MCU_MISC_IROM_2T_Access_Set(0); */ - /* unuseful for mcu, useful for dsp, just for safe */ - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL); - /* recover xclk */ - HBN_Set_MCU_XCLK_Sel(mcuXclkSel); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_240M: - /* For high speed, set DIV first */ - GLB_Set_MCU_System_CLK_Div(0, 2, 1); - /* Set IROM 2T Access 0 since we use RC32M, unuseful now */ - /* MCU_MISC_IROM_2T_Access_Set(0); */ - /* unuseful for mcu, useful for dsp, just for safe */ - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL); - /* recover xclk */ - HBN_Set_MCU_XCLK_Sel(mcuXclkSel); - break; - case GLB_MCU_SYS_CLK_WIFIPLL_320M: - /* overclock, not recommended */ - /* For high speed, set DIV first */ - GLB_Set_MCU_System_CLK_Div(0, 3, 1); - /* Set IROM 2T Access 0 since we use RC32M, unuseful now */ - /* MCU_MISC_IROM_2T_Access_Set(0); */ - HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL); - /* recover xclk */ - HBN_Set_MCU_XCLK_Sel(mcuXclkSel); - break; - default: - break; - } - - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DSP0 DSP1 clock div - * - * @param dspClkDiv: mm glb cpu div - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK_Div(uint8_t dspClkDiv, uint8_t dspBclkDiv) -{ - uint32_t tmpVal = 0; - uint32_t timeout = 1024; - GLB_DSP_XCLK_Type dspXclkSel; - GLB_DSP_ROOT_CLK_Type dspRootClkSel; - - /* get root clock */ - dspXclkSel = GLB_Get_DSP_XCLK_Sel(); - dspRootClkSel = GLB_Get_DSP_ROOT_CLK_Sel(); - - /* change root clock to rc32m */ - if ((dspXclkSel != GLB_DSP_XCLK_RC32M) || (dspRootClkSel != GLB_DSP_ROOT_CLK_XCLK)) { - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - } - - /* set div */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV, dspBclkDiv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV, dspClkDiv); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV_ACT_PULSE, 1); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - do { - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_STS_BCLK2X_PROT_DONE); - } while ((--timeout) && (!tmpVal)); - if (!timeout) { - return ERROR; - } - - /* recover root clock */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - GLB_Set_DSP_ROOT_CLK_Sel(dspRootClkSel); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP0 DSP1 clock div - * - * @param dspClkDiv: mm glb cpu div - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_System_CLK_Div(uint8_t *dspClkDiv, uint8_t *dspBclkDiv) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - *dspBclkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV); - *dspClkDiv = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set dsp System clock - * - * @param clkFreq: dsp system clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_Type clkFreq) -{ - GLB_DSP_XCLK_Type dspXclkSel; - - CHECK_PARAM(IS_GLB_DSP_SYS_CLK_TYPE(clkFreq)); - - /* get root clock */ - dspXclkSel = GLB_Get_DSP_XCLK_Sel(); - - /* Before config XTAL and PLL ,make sure root clk is from RC32M */ - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - GLB_Set_DSP_System_CLK_Div(0, 0); - - /* select pll output clock before select root clock */ - if (GLB_DSP_SYS_CLK_MM_WIFIPLL_240M == clkFreq) { - GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_240M); - } else if (GLB_DSP_SYS_CLK_MM_WIFIPLL_320M == clkFreq) { - GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_MUXPLL_320M); - } else if (GLB_DSP_SYS_CLK_CPUPLL_400M == clkFreq) { - GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_CPUPLL_400M); - } - - /* select root clock */ - switch (clkFreq) { - case GLB_DSP_SYS_CLK_RC32M: - GLB_Set_DSP_System_CLK_Div(0, 0); - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - break; - case GLB_DSP_SYS_CLK_XTAL: - GLB_Set_DSP_System_CLK_Div(0, 0); - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_XCLK); - break; - case GLB_DSP_SYS_CLK_MM_WIFIPLL_240M: - GLB_Set_DSP_System_CLK_Div(0, 1); - GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL); - /* recover xclk */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - break; - case GLB_DSP_SYS_CLK_MM_WIFIPLL_320M: - GLB_Set_DSP_System_CLK_Div(0, 1); - GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_320M); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL); - /* recover xclk */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - break; - case GLB_DSP_SYS_CLK_CPUPLL_400M: - GLB_Set_DSP_System_CLK_Div(0, 1); - GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_PLL); - /* recover xclk */ - GLB_Set_DSP_XCLK_Sel(dspXclkSel); - break; - default: - break; - } - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DSP0 pbus clock div - * - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK_Div(uint8_t dspPBclkDiv) -{ - uint32_t tmpVal = 0; - - /* set div */ - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV, dspPBclkDiv); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP0 pbus clock div - * - * @param dspBclkDiv: mm glb bclk2x div - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBCLK_Div(uint8_t *dspPBclkDiv) -{ - *dspPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CPU), MM_GLB_REG_BCLK1X_DIV); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set dsp pbus clock - * - * @param pbClkSel: dsp pbus clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_Type pbClkSel) -{ - CHECK_PARAM(IS_GLB_DSP_SYS_PBCLK_TYPE(pbClkSel)); - - GLB_Set_DSP_PBCLK_Div(0); - - /* select pbroot clock */ - switch (pbClkSel) { - case GLB_DSP_SYS_PBCLK_RC32M: - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_RC32M); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK); - break; - case GLB_DSP_SYS_PBCLK_XTAL: - GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_XTAL); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_XCLK); - break; - case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_160M: - GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_160M); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M); - break; - case GLB_DSP_SYS_PBCLK_CPUPLL_160M: - GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_SEL_CPUPLL_160M); - GLB_Set_DSP_PBCLK_Div(0); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M); - break; - case GLB_DSP_SYS_PBCLK_MM_WIFIPLL_240M: - GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_SEL_WIFIPLL_240M); - GLB_Set_DSP_PBCLK_Div(1); - GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M); - break; - default: - break; - } - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP0 clock enable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief DSP0 clock disable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_DSP0_Clock_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_MMCPU0_CLK_EN); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get xclk clock source Select - * - * @param None - * - * @return xclk clock type selection - * -*******************************************************************************/ -GLB_DSP_XCLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_XCLK_Sel(void) -{ - return (GLB_DSP_XCLK_Type)(BL_GET_REG_BITS_VAL(BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU), MM_GLB_REG_XCLK_CLK_SEL)); -} - -/****************************************************************************/ /** - * @brief Select xclk clock source - * - * @param xclk: xclk clock type selection - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_Type xclk) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_XCLK_TYPE(xclk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL, xclk); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP root clock - * - * @param None - * - * @return mm glb root clock type - * -*******************************************************************************/ -GLB_DSP_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_ROOT_CLK_Sel(void) -{ - uint32_t tmpVal = 0; - uint32_t rootclk = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - rootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL); - if (0 == rootclk) { - /* xclk */ - return GLB_DSP_ROOT_CLK_XCLK; - } else { - /* pll */ - return GLB_DSP_ROOT_CLK_PLL; - } -} - -/****************************************************************************/ /** - * @brief select DSP root clock - * - * @param rootClk: mm glb root clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_Type rootClk) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_ROOT_CLK_TYPE(rootClk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - switch (rootClk) { - case GLB_DSP_ROOT_CLK_XCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 0); - break; - case GLB_DSP_ROOT_CLK_PLL: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL, 1); - break; - default: - break; - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief select DSP muxpll clock - * - * @param pllClk: mm glb pll clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_Type pllClk) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_DSP_PLL_CLK_TYPE(pllClk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - switch (pllClk) { - case GLB_DSP_PLL_CLK_MUXPLL_240M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 0); - break; - case GLB_DSP_PLL_CLK_MUXPLL_320M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 1); - break; - case GLB_DSP_PLL_CLK_CPUPLL_400M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_SEL, 2); - break; - default: - break; - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get DSP pbroot clock - * - * @param None - * - * @return mm DSP pbroot clock type - * -*******************************************************************************/ -GLB_DSP_PBROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_DSP_PBROOT_CLK_Sel(void) -{ - uint32_t tmpVal = 0; - uint32_t pbrootclk = 0; - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - pbrootclk = BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL); - switch (pbrootclk) { - case 0: - return GLB_DSP_PBROOT_CLK_MM_XCLK; - case 1: - return GLB_DSP_PBROOT_CLK_MM_XCLK; - case 2: - return GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M; - case 3: - return GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M; - default: - return GLB_DSP_PBROOT_CLK_MM_XCLK; - } -} - -/****************************************************************************/ /** - * @brief select DSP pbroot clock - * - * @param pbrootClk: mm DSP pbroot clock type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_Type pbrootClk) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_DSP_PBROOT_CLK_TYPE(pbrootClk)); - - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU); - switch (pbrootClk) { - case GLB_DSP_PBROOT_CLK_MM_XCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 0); - break; - case GLB_DSP_PBROOT_CLK_MM_MUXPLL_160M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 2); - break; - case GLB_DSP_PBROOT_CLK_MM_MUXPLL_240M: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL, 3); - break; - default: - break; - } - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_CLK_CTRL_CPU, tmpVal); - GLB_CLK_SET_DUMMY_WAIT; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set CPU reset address - * - * @param coreID: core type - * @param addr: reset address - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr) -{ - CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID)); - - switch (coreID) { - case GLB_CORE_ID_M0: - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr); - break; - case GLB_CORE_ID_D0: - BL_WR_REG(MM_MISC_BASE, MM_MISC_CPU0_BOOT, addr); - break; - case GLB_CORE_ID_LP: - BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG13, addr); - break; - default: - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief hold cpu - * - * @param coreID: core type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Halt_CPU(GLB_CORE_ID_Type coreID) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID)); - - switch (coreID) { - case GLB_CORE_ID_M0: - PDS_Set_MCU0_Clock_Disable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - case GLB_CORE_ID_D0: - GLB_DSP0_Clock_Disable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - break; - case GLB_CORE_ID_LP: - PDS_Set_LP_Clock_Disable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - default: - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief release cpu - * - * @param coreID: core type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Release_CPU(GLB_CORE_ID_Type coreID) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID)); - - switch (coreID) { - case GLB_CORE_ID_M0: - PDS_Set_MCU0_Clock_Enable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - case GLB_CORE_ID_D0: - GLB_DSP0_Clock_Enable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET); - tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CTRL_MMCPU0_RESET); - BL_WR_REG(MM_GLB_BASE, MM_GLB_MM_SW_SYS_RESET, tmpVal); - break; - case GLB_CORE_ID_LP: - PDS_Set_LP_Clock_Enable(); - arch_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PICO_RESET); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal); - break; - default: - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set MTimer clock - * - * @param enable: enable or disable - * @param clkSel: clock selection - * @param div: divider - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_EMI_CLK(uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_GLB_EMI_CLK_TYPE(clkSel)); - CHECK_PARAM((div <= 0x3)); - - /* disable EMI clock first */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN); - BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); - switch (clkSel) { - case GLB_EMI_CLK_MCU_PBCLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 0); - break; - case GLB_EMI_CLK_CPUPLL_200M_CLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 4); - break; - case GLB_EMI_CLK_WIFIPLL_320M_CLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 2); - break; - case GLB_EMI_CLK_CPUPLL_400M_CLK: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL, 3); - break; - default: - break; - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV, div); - BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_EMI_CFG0); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EMI_CLK_EN); - } - BL_WR_REG(GLB_BASE, GLB_EMI_CFG0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Clr_EMI_Reset_Gate(void) -{ - uint32_t tmpVal; - - /* clear EMI swrst bit */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S1_EXT_EMI_MISC); - BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal); - - /* set EMI cgen bit */ - tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S1_EXT_EMI_MISC); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure WIFIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure AUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure CPUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock div - * - * @param divEn: div enable - * @param divRatio: div ratio - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure UHSPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 0); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get core type - * - * @param None - * - * @return core type - * -*******************************************************************************/ -GLB_CORE_ID_Type ATTR_CLOCK_SECTION GLB_Get_Core_Type(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_WORD(CORE_ID_ADDRESS); - - switch (tmpVal) { - case CORE_ID_M0: - return GLB_CORE_ID_M0; - case CORE_ID_D0: - return GLB_CORE_ID_D0; - case CORE_ID_LP: - return GLB_CORE_ID_LP; - default: - return GLB_CORE_ID_INVALID; - } - - return GLB_CORE_ID_INVALID; -} - -/****************************************************************************/ /** - * @brief get first 1 from u64, then clear it - * - * @param val: target value - * @param bit: first 1 in bit - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit) -{ - if (!*val) { - return ERROR; - } - - for (uint8_t i = 0; i < 64; i++) { - if ((*val) & ((uint64_t)1 << i)) { - *bit = i; - (*val) &= ~((uint64_t)1 << i); - break; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief hold IPs clock - * - * @param ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ...... - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips) -{ - /* api request from cjy */ - - uint32_t tmpValCfg0 = 0; - uint32_t tmpValCfg1 = 0; - uint32_t tmpValCfg2 = 0; - uint32_t bitfield = 0; - - tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); - tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - while (ips) { - if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { - switch (bitfield) { - case GLB_AHB_CLOCK_IP_CPU: - tmpValCfg0 &= ~(1 << 0); - break; - case GLB_AHB_CLOCK_IP_SDU: - tmpValCfg0 &= ~(1 << 1); - break; - case GLB_AHB_CLOCK_IP_SEC: - tmpValCfg0 &= ~(1 << 2); - tmpValCfg1 &= ~(1 << 3); - tmpValCfg1 &= ~(1 << 4); - break; - case GLB_AHB_CLOCK_IP_DMA_0: - tmpValCfg0 &= ~(1 << 3); - tmpValCfg1 &= ~(1 << 12); - break; - case GLB_AHB_CLOCK_IP_DMA_1: - tmpValCfg0 &= ~(1 << 3); - break; - case GLB_AHB_CLOCK_IP_DMA_2: - tmpValCfg0 &= ~(1 << 3); - tmpValCfg2 &= ~(1 << 24); - break; - case GLB_AHB_CLOCK_IP_CCI: - tmpValCfg0 &= ~(1 << 4); - break; - case GLB_AHB_CLOCK_IP_RF_TOP: - tmpValCfg1 &= ~(1 << 1); - break; - case GLB_AHB_CLOCK_IP_GPIP: - tmpValCfg1 &= ~(1 << 2); - break; - case GLB_AHB_CLOCK_IP_TZC: - tmpValCfg1 &= ~(1 << 5); - break; - case GLB_AHB_CLOCK_IP_EF_CTRL: - tmpValCfg1 &= ~(1 << 7); - break; - case GLB_AHB_CLOCK_IP_SF_CTRL: - tmpValCfg1 &= ~(1 << 11); - break; - case GLB_AHB_CLOCK_IP_EMAC: - tmpValCfg2 &= ~(1 << 19); - tmpValCfg2 &= ~(1 << 23); - break; - case GLB_AHB_CLOCK_IP_UART0: - tmpValCfg1 &= ~(1 << 16); - break; - case GLB_AHB_CLOCK_IP_UART1: - tmpValCfg1 &= ~(1 << 17); - break; - case GLB_AHB_CLOCK_IP_UART2: - tmpValCfg1 &= ~(1 << 26); - break; - case GLB_AHB_CLOCK_IP_UART3: - break; - case GLB_AHB_CLOCK_IP_UART4: - break; - case GLB_AHB_CLOCK_IP_SPI: - tmpValCfg1 &= ~(1 << 18); - break; - case GLB_AHB_CLOCK_IP_I2C: - tmpValCfg1 &= ~(1 << 19); - break; - case GLB_AHB_CLOCK_IP_PWM: - tmpValCfg1 &= ~(1 << 20); - break; - case GLB_AHB_CLOCK_IP_TIMER: - tmpValCfg1 &= ~(1 << 21); - break; - case GLB_AHB_CLOCK_IP_IR: - tmpValCfg1 &= ~(1 << 22); - break; - case GLB_AHB_CLOCK_IP_CHECKSUM: - tmpValCfg1 &= ~(1 << 23); - break; - case GLB_AHB_CLOCK_IP_QDEC: - break; - case GLB_AHB_CLOCK_IP_KYS: - break; - case GLB_AHB_CLOCK_IP_I2S: - tmpValCfg1 &= ~(1 << 27); - break; - case GLB_AHB_CLOCK_IP_USB11: - break; - case GLB_AHB_CLOCK_IP_CAM: - break; - case GLB_AHB_CLOCK_IP_MJPEG: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: - tmpValCfg2 &= ~(1 << 8); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_LP: - break; - case GLB_AHB_CLOCK_IP_ZB_NORMAL: - tmpValCfg2 &= ~(1 << 9); - break; - case GLB_AHB_CLOCK_IP_ZB_LP: - break; - case GLB_AHB_CLOCK_IP_WIFI_NORMAL: - tmpValCfg2 &= ~(1 << 4); - break; - case GLB_AHB_CLOCK_IP_WIFI_LP: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL: - tmpValCfg2 &= ~(1 << 10); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_LP: - break; - case GLB_AHB_CLOCK_IP_EMI_MISC: - tmpValCfg2 &= ~(1 << 16); - break; - case GLB_AHB_CLOCK_IP_PSRAM0_CTRL: - tmpValCfg2 &= ~(1 << 17); - break; - case GLB_AHB_CLOCK_IP_PSRAM1_CTRL: - tmpValCfg2 &= ~(1 << 18); - break; - case GLB_AHB_CLOCK_IP_USB20: - tmpValCfg1 &= ~(1 << 13); - break; - case GLB_AHB_CLOCK_IP_MIX2: - tmpValCfg2 &= ~(1 << 20); - break; - case GLB_AHB_CLOCK_IP_AUDIO: - tmpValCfg2 &= ~(1 << 21); - break; - case GLB_AHB_CLOCK_IP_SDH: - tmpValCfg2 &= ~(1 << 22); - break; - case GLB_AHB_CLOCK_IP_ZB2_NORMAL: - tmpValCfg2 &= ~(1 << 11); - break; - case GLB_AHB_CLOCK_IP_ZB2_LP: - break; - case GLB_AHB_CLOCK_IP_I2C1: - tmpValCfg1 &= ~(1 << 25); - break; - case GLB_AHB_CLOCK_IP_WIFI_PHY: - tmpValCfg0 &= ~(1 << 7); - break; - case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY: - tmpValCfg0 &= ~(1 << 6); - break; - case GLB_AHB_CLOCK_IP_WIFI_PLATFORM: - tmpValCfg0 &= ~(1 << 5); - break; - case GLB_AHB_CLOCK_IP_LZ4: - tmpValCfg1 &= ~(1 << 29); - break; - case GLB_AHB_CLOCK_IP_AUPDM: - tmpValCfg1 &= ~(1 << 28); - break; - case GLB_AHB_CLOCK_IP_GAUGE: - tmpValCfg1 &= ~(1 << 0); - break; - default: - break; - } - } - } - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief release IPs clock - * - * @param ips: GLB_AHB_CLOCK_xxx | GLB_AHB_CLOCK_xxx | ...... (not GLB_AHB_CLOCK_IP_xxx) - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips) -{ - /* api request from cjy */ - - uint32_t tmpValCfg0 = 0; - uint32_t tmpValCfg1 = 0; - uint32_t tmpValCfg2 = 0; - uint32_t bitfield = 0; - - tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0); - tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1); - tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2); - while (ips) { - if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) { - switch (bitfield) { - case GLB_AHB_CLOCK_IP_CPU: - tmpValCfg0 |= (1 << 0); - break; - case GLB_AHB_CLOCK_IP_SDU: - tmpValCfg0 |= (1 << 1); - break; - case GLB_AHB_CLOCK_IP_SEC: - tmpValCfg0 |= (1 << 2); - tmpValCfg1 |= (1 << 3); - tmpValCfg1 |= (1 << 4); - break; - case GLB_AHB_CLOCK_IP_DMA_0: - tmpValCfg0 |= (1 << 3); - tmpValCfg1 |= (1 << 12); - break; - case GLB_AHB_CLOCK_IP_DMA_1: - tmpValCfg0 |= (1 << 3); - break; - case GLB_AHB_CLOCK_IP_DMA_2: - tmpValCfg0 |= (1 << 3); - tmpValCfg2 |= (1 << 24); - break; - case GLB_AHB_CLOCK_IP_CCI: - tmpValCfg0 |= (1 << 4); - break; - case GLB_AHB_CLOCK_IP_RF_TOP: - tmpValCfg1 |= (1 << 1); - break; - case GLB_AHB_CLOCK_IP_GPIP: - tmpValCfg1 |= (1 << 2); - break; - case GLB_AHB_CLOCK_IP_TZC: - tmpValCfg1 |= (1 << 5); - break; - case GLB_AHB_CLOCK_IP_EF_CTRL: - tmpValCfg1 |= (1 << 7); - break; - case GLB_AHB_CLOCK_IP_SF_CTRL: - tmpValCfg1 |= (1 << 11); - break; - case GLB_AHB_CLOCK_IP_EMAC: - tmpValCfg2 |= (1 << 19); - tmpValCfg2 |= (1 << 23); - break; - case GLB_AHB_CLOCK_IP_UART0: - tmpValCfg1 |= (1 << 16); - break; - case GLB_AHB_CLOCK_IP_UART1: - tmpValCfg1 |= (1 << 17); - break; - case GLB_AHB_CLOCK_IP_UART2: - tmpValCfg1 |= (1 << 26); - break; - case GLB_AHB_CLOCK_IP_UART3: - break; - case GLB_AHB_CLOCK_IP_UART4: - break; - case GLB_AHB_CLOCK_IP_SPI: - tmpValCfg1 |= (1 << 18); - break; - case GLB_AHB_CLOCK_IP_I2C: - tmpValCfg1 |= (1 << 19); - break; - case GLB_AHB_CLOCK_IP_PWM: - tmpValCfg1 |= (1 << 20); - break; - case GLB_AHB_CLOCK_IP_TIMER: - tmpValCfg1 |= (1 << 21); - break; - case GLB_AHB_CLOCK_IP_IR: - tmpValCfg1 |= (1 << 22); - break; - case GLB_AHB_CLOCK_IP_CHECKSUM: - tmpValCfg1 |= (1 << 23); - break; - case GLB_AHB_CLOCK_IP_QDEC: - break; - case GLB_AHB_CLOCK_IP_KYS: - break; - case GLB_AHB_CLOCK_IP_I2S: - tmpValCfg1 |= (1 << 23); - break; - case GLB_AHB_CLOCK_IP_USB11: - break; - case GLB_AHB_CLOCK_IP_CAM: - break; - case GLB_AHB_CLOCK_IP_MJPEG: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL: - tmpValCfg2 |= (1 << 8); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_LP: - break; - case GLB_AHB_CLOCK_IP_ZB_NORMAL: - tmpValCfg2 |= (1 << 9); - break; - case GLB_AHB_CLOCK_IP_ZB_LP: - break; - case GLB_AHB_CLOCK_IP_WIFI_NORMAL: - tmpValCfg2 |= (1 << 4); - break; - case GLB_AHB_CLOCK_IP_WIFI_LP: - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL: - tmpValCfg2 |= (1 << 10); - break; - case GLB_AHB_CLOCK_IP_BT_BLE_2_LP: - break; - case GLB_AHB_CLOCK_IP_EMI_MISC: - tmpValCfg2 |= (1 << 16); - break; - case GLB_AHB_CLOCK_IP_PSRAM0_CTRL: - tmpValCfg2 |= (1 << 17); - break; - case GLB_AHB_CLOCK_IP_PSRAM1_CTRL: - tmpValCfg2 |= (1 << 18); - break; - case GLB_AHB_CLOCK_IP_USB20: - tmpValCfg1 |= (1 << 13); - break; - case GLB_AHB_CLOCK_IP_MIX2: - tmpValCfg2 |= (1 << 20); - break; - case GLB_AHB_CLOCK_IP_AUDIO: - tmpValCfg2 |= (1 << 21); - break; - case GLB_AHB_CLOCK_IP_SDH: - tmpValCfg2 |= (1 << 22); - break; - case GLB_AHB_CLOCK_IP_ZB2_NORMAL: - tmpValCfg2 |= (1 << 11); - break; - case GLB_AHB_CLOCK_IP_ZB2_LP: - break; - case GLB_AHB_CLOCK_IP_I2C1: - tmpValCfg1 |= (1 << 25); - break; - case GLB_AHB_CLOCK_IP_WIFI_PHY: - tmpValCfg0 |= (1 << 7); - break; - case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY: - tmpValCfg0 |= (1 << 6); - break; - case GLB_AHB_CLOCK_IP_WIFI_PLATFORM: - tmpValCfg0 |= (1 << 5); - break; - case GLB_AHB_CLOCK_IP_LZ4: - tmpValCfg1 |= (1 << 29); - break; - case GLB_AHB_CLOCK_IP_AUPDM: - tmpValCfg1 |= (1 << 28); - break; - case GLB_AHB_CLOCK_IP_GAUGE: - tmpValCfg1 |= (1 << 0); - break; - default: - break; - } - } - } - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1); - BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief software reset - * - * @param swrst: reset num - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst) -{ - uint32_t tmpVal = 0; - uint32_t bit = 0; - uint32_t regAddr = 0; - - CHECK_PARAM(IS_GLB_AHB_MCU_SW_TYPE(swrst)); - - if (swrst < 32) { - bit = swrst; - regAddr = GLB_BASE + GLB_SWRST_CFG0_OFFSET; - } else if (swrst < 64) { - bit = swrst - 32; - regAddr = GLB_BASE + GLB_SWRST_CFG1_OFFSET; - } else if (swrst < 96) { - bit = swrst - 64; - regAddr = GLB_BASE + GLB_SWRST_CFG2_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal |= (1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief software reset - * - * @param swrst: reset num - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst) -{ - uint32_t tmpVal = 0; - uint32_t bit = 0; - uint32_t regAddr = 0; - - CHECK_PARAM(IS_GLB_AHB_DSP_SW_TYPE(swrst)); - - if (swrst < 32) { - bit = swrst; - regAddr = MM_GLB_BASE + MM_GLB_MM_SW_SYS_RESET_OFFSET; - } else if (swrst < 64) { - bit = swrst - 32; - regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_MM_PERI_OFFSET; - } else if (swrst < 96) { - bit = swrst - 64; - regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_DSP2_SUB_OFFSET; - } else if (swrst < 128) { - bit = swrst - 96; - regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_CODEC_SUB_OFFSET; - } else if (swrst < 160) { - bit = swrst - 128; - regAddr = MM_GLB_BASE + MM_GLB_IMAGE_SENSOR_CTRL_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal |= (1 << bit); - BL_WR_WORD(regAddr, tmpVal); - BL_DRV_DUMMY; - tmpVal = BL_RD_WORD(regAddr); - tmpVal &= ~(1 << bit); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/*@} end of group GLB_Public_Functions */ - -/*@} end of group GLB */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c deleted file mode 100644 index 80319fce62..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2c.c +++ /dev/null @@ -1,964 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2c.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_i2c.h" -#include "bl808_glb.h" -#include "bl808_clock.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2C - * @{ - */ - -/** @defgroup I2C_Private_Macros - * @{ - */ -#define I2C_FIFO_STATUS_TIMEOUT (320 * 1000 * 2) -#define PUT_UINT32_LE(n, b, i) \ - { \ - (b)[(i)] = (uint8_t)((n)); \ - (b)[(i) + 1] = (uint8_t)((n) >> 8); \ - (b)[(i) + 2] = (uint8_t)((n) >> 16); \ - (b)[(i) + 3] = (uint8_t)((n) >> 24); \ - } - -/*@} end of group I2C_Private_Macros */ - -/** @defgroup I2C_Private_Types - * @{ - */ - -/*@} end of group I2C_Private_Types */ - -/** @defgroup I2C_Private_Variables - * @{ - */ -static const uint32_t i2cAddr[4] = { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -intCallback_Type *i2cIntCbfArra[I2C_ID_MAX][I2C_INT_ALL] = { { NULL } }; -#endif - -/*@} end of group I2C_Private_Variables */ - -/** @defgroup I2C_Global_Variables - * @{ - */ - -/*@} end of group I2C_Global_Variables */ - -/** @defgroup I2C_Private_Fun_Declaration - * @{ - */ - -/*@} end of group I2C_Private_Fun_Declaration */ - -/** @defgroup I2C_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief I2C interrupt handler - * - * @param i2cNo: I2C ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void I2C_IntHandler(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_TRANS_END_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_TXF_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_TX_FIFO_READY_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_RXF_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_RX_FIFO_READY_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_NAK_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_NACK_RECV_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_ARB_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_ARB_LOST_INT](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, I2C_FER_INT)) { - if (i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT] != NULL) { - /* Call the callback function */ - i2cIntCbfArra[i2cNo][I2C_FIFO_ERR_INT](); - } - } -} -#endif - -/*@} end of group I2C_Private_Functions */ - -/** @defgroup I2C_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief I2C write word data - * - * @param i2cNo: I2C ID type - * @param data: Data word - * - * @return None - * -*******************************************************************************/ -BL_Err_Type I2C_SendWord(I2C_ID_Type i2cNo, uint32_t data) -{ - uint32_t I2Cx = i2cAddr[i2cNo]; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { - timeOut--; - if (timeOut == 0) { - return TIMEOUT; - } - } - - BL_WR_REG(I2Cx, I2C_FIFO_WDATA, data); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C read word data - * - * @param i2cNo: I2C ID type - * - * @return word data - * -*******************************************************************************/ -BL_Err_Type I2C_RecieveWord(I2C_ID_Type i2cNo, uint32_t *recvBuff) -{ - uint32_t I2Cx = i2cAddr[i2cNo]; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - *recvBuff = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C enable - * - * @param i2cNo: I2C ID type - * - * @return None - * -*******************************************************************************/ -void I2C_Enable(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2C disable - * - * @param i2cNo: I2C ID type - * - * @return None - * -*******************************************************************************/ -void I2C_Disable(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_M_EN); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); - - /* Clear I2C fifo */ - tmpVal = BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_TX_FIFO_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_RX_FIFO_CLR); - BL_WR_REG(I2Cx, I2C_FIFO_CONFIG_0, tmpVal); - - /* Clear I2C interrupt status */ - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_CLR); - BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2C set global reset function - * - * @param i2cNo: I2C ID type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type I2C_DeInit(I2C_ID_Type i2cNo) -{ - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - if (i2cNo == I2C0_ID || i2cNo == I2C1_ID) { - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_I2C); - } else if (i2cNo == I2C0_MM_ID) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_I2C0); - } else if (i2cNo == I2C1_MM_ID) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_I2C1); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C init function - * - * @param i2cNo: I2C ID type - * @param direct: I2C read or write direct - * @param cfg: I2C transfer config struct - * - * @return None - * -*******************************************************************************/ -void I2C_Init(I2C_ID_Type i2cNo, I2C_Direction_Type direct, I2C_Transfer_Cfg *cfg) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - /* set i2c clk,default is 400000,max support clk is 400000 */ - if (cfg->clk == 0 || cfg->clk > 400000){ - I2C_ClockSet(i2cNo, 400000); - } else { - I2C_ClockSet(i2cNo, cfg->clk); - } - - /* Disable clock gate when use I2C0 */ - if (I2C0_ID == i2cNo) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C); - } else if (I2C1_ID == i2cNo) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2C1); - } - - /* I2C write config */ - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - - if (direct == I2C_WRITE) { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_PKT_DIR); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SLV_ADDR, cfg->slaveAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_10B_ADDR_EN, cfg->slaveAddr10Bit); - - if (cfg->subAddrSize > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SUB_ADDR_BC, cfg->subAddrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SUB_ADDR_EN); - } - - /* align clock when 1 master*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_SCL_SYNC_EN, DISABLE); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PKT_LEN, cfg->dataSize - 1); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); - - /* Set sub address */ - BL_WR_REG(I2Cx, I2C_SUB_ADDR, cfg->subAddr); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(I2C0_IRQn, I2C0_IRQHandler); - Interrupt_Handler_Register(I2C1_IRQn, I2C1_IRQHandler); - Interrupt_Handler_Register(I2C2_IRQn, I2C2_IRQHandler); - Interrupt_Handler_Register(I2C3_IRQn, I2C2_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Set de-glitch function cycle count value - * - * @param i2cNo: I2C ID type - * @param cnt: De-glitch function cycle count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type I2C_SetDeglitchCount(I2C_ID_Type i2cNo, uint8_t cnt) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - - if (cnt > 0) { - /* enable de-glitch function */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); - } else if (cnt == 0) { - /* disable de-glitch function */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_DEG_EN); - } else { - return ERROR; - } - - /* Set count value */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_DEG_CNT, cnt); - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set i2c prd - * - * @param i2cNo: I2C ID type - * @param phase: I2C phase value - * - * @return None - * -*******************************************************************************/ -void I2C_SetPrd(I2C_ID_Type i2cNo, uint8_t phase) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - //phase_cycles = (32000000 / phase / 4) - 1; - tmpVal = BL_RD_REG(I2Cx, I2C_PRD_START); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_0, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_1, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_2, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_S_PH_3, phase); - BL_WR_REG(I2Cx, I2C_PRD_START, tmpVal); - tmpVal = BL_RD_REG(I2Cx, I2C_PRD_STOP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_0, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_1, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_2, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_P_PH_3, phase); - BL_WR_REG(I2Cx, I2C_PRD_STOP, tmpVal); - tmpVal = BL_RD_REG(I2Cx, I2C_PRD_DATA); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_0, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_1, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_2, phase); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2C_CR_I2C_PRD_D_PH_3, phase); - BL_WR_REG(I2Cx, I2C_PRD_DATA, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2C set scl output clock - * - * @param i2cNo: I2C ID type - * @param clk: Clock set - * - * @return None - * -*******************************************************************************/ -void I2C_ClockSet(I2C_ID_Type i2cNo, uint32_t clk) -{ - uint32_t bclk = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - if (i2cNo == I2C0_ID || i2cNo == I2C1_ID) { - bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK); - - if (clk >= 100000) { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 0); - I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1); - } else if (clk >= 8000) { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 9); - I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1); - } else if (clk >= 800) { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 99); - I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1); - } else { - GLB_Set_I2C_CLK(1, GLB_I2C_CLK_BCLK, 255); - I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1); - } - } else if (i2cNo == I2C0_MM_ID) { - bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK); - - if (clk >= 100000) { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 0); - I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1); - } else if (clk >= 8000) { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 9); - I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1); - } else if (clk >= 800) { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 99); - I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1); - } else { - GLB_Set_DSP_I2C0_CLK(1, 1, 1, 255); - I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1); - } - } else if (i2cNo == I2C1_MM_ID) { - bclk = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_PBCLK); - - if (clk >= 100000) { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 0); - I2C_SetPrd(i2cNo, bclk / (clk * 4) - 1); - } else if (clk >= 8000) { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 9); - I2C_SetPrd(i2cNo, bclk / 10 / (clk * 4) - 1); - } else if (clk >= 800) { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 99); - I2C_SetPrd(i2cNo, bclk / 100 / (clk * 4) - 1); - } else { - GLB_Set_DSP_I2C1_CLK(1, 1, 1, 255); - I2C_SetPrd(i2cNo, bclk / 256 / (clk * 4) - 1); - } - } -} - -/****************************************************************************/ /** - * @brief I2C set scl sync - * - * @param i2cNo: I2C ID type - * @param enable: Enable or disable I2C scl sync - * - * @return None - * -*******************************************************************************/ -void I2C_SetSclSync(I2C_ID_Type i2cNo, uint8_t enable) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_CONFIG); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_SCL_SYNC_EN); - } - - BL_WR_REG(I2Cx, I2C_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get i2c busy state - * - * @param i2cNo: I2C ID type - * - * @return RESET or SET - * -*******************************************************************************/ -BL_Sts_Type I2C_IsBusy(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_BUS_BUSY); - return ((BL_IS_REG_BIT_SET(tmpVal, I2C_STS_I2C_BUS_BUSY)) ? SET : RESET); -} - -/****************************************************************************/ /** - * @brief Get i2c transfer end state - * - * @param i2cNo: I2C ID type - * - * @return RESET or SET - * -*******************************************************************************/ -BL_Sts_Type I2C_TransferEndStatus(I2C_ID_Type i2cNo) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - return ((BL_IS_REG_BIT_SET(tmpVal, I2C_END_INT)) ? SET : RESET); -} - -/****************************************************************************/ /** - * @brief I2C master write block data - * - * @param i2cNo: I2C ID type - * @param cfg: I2C transfer config struct - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type I2C_MasterSendBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) -{ - uint8_t i; - uint32_t timeOut = 0; - uint32_t temp = 0; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - I2C_Disable(i2cNo); - I2C_Init(i2cNo, I2C_WRITE, cfg); - - /* Set I2C write data */ - for (i = 0; i < cfg->dataSize; i++) { - temp += (cfg->data[i] << ((i % 4) * 8)); - - if ((i + 1) % 4 == 0) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); - if(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_CONFIG), I2C_CR_I2C_M_EN) == 0) { - I2C_Enable(i2cNo); - } - temp = 0; - } - } - - if ((cfg->dataSize % 4) != 0) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_TX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - BL_WR_REG(I2Cx, I2C_FIFO_WDATA, temp); - if(BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_CONFIG), I2C_CR_I2C_M_EN) == 0) { - I2C_Enable(i2cNo); - } - } - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - I2C_Disable(i2cNo); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief I2C master read block data - * - * @param i2cNo: I2C ID type - * @param cfg: I2C transfer config struct - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type I2C_MasterReceiveBlocking(I2C_ID_Type i2cNo, I2C_Transfer_Cfg *cfg) -{ - uint8_t i = 0; - uint32_t timeOut = 0; - uint32_t temp = 0; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - - I2C_Disable(i2cNo); - I2C_Init(i2cNo, I2C_READ, cfg); - I2C_Enable(i2cNo); - - /* Read I2C data */ - while (cfg->dataSize - i >= 4) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); - PUT_UINT32_LE(temp, cfg->data, i); - i += 4; - } - - if (i < cfg->dataSize) { - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(I2Cx, I2C_FIFO_CONFIG_1), I2C_RX_FIFO_CNT) == 0) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - temp = BL_RD_REG(I2Cx, I2C_FIFO_RDATA); - - while (i < cfg->dataSize) { - cfg->data[i] = (temp & 0xff); - temp = (temp >> 8); - i++; - } - } - - timeOut = I2C_FIFO_STATUS_TIMEOUT; - - while (I2C_IsBusy(i2cNo) || !I2C_TransferEndStatus(i2cNo)) { - timeOut--; - - if (timeOut == 0) { - I2C_Disable(i2cNo); - return TIMEOUT; - } - } - - I2C_Disable(i2cNo); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the I2C interrupt - * - * @param i2cNo: I2C ID type - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void I2C_IntMask(I2C_ID_Type i2cNo, I2C_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t I2Cx = i2cAddr[i2cNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - CHECK_PARAM(IS_I2C_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(I2Cx, I2C_INT_STS); - - switch (intType) { - case I2C_TRANS_END_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - } - - break; - - case I2C_TX_FIFO_READY_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - } - - break; - - case I2C_RX_FIFO_READY_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - } - - break; - - case I2C_NACK_RECV_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - } - - break; - - case I2C_ARB_LOST_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - } - - break; - - case I2C_FIFO_ERR_INT: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } - - break; - - case I2C_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_END_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_TXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_RXF_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_NAK_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_ARB_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2C_CR_I2C_FER_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_END_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_TXF_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_RXF_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_NAK_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_ARB_MASK); - tmpVal = BL_SET_REG_BIT(tmpVal, I2C_CR_I2C_FER_MASK); - } - - break; - - default: - break; - } - - BL_WR_REG(I2Cx, I2C_INT_STS, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install I2C interrupt callback function - * - * @param i2cNo: I2C ID type - * @param intType: Specifies the interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C_Int_Callback_Install(I2C_ID_Type i2cNo, I2C_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_I2C_ID_TYPE(i2cNo)); - CHECK_PARAM(IS_I2C_INT_TYPE(intType)); - - i2cIntCbfArra[i2cNo][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief I2C0 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C0_IRQHandler(void) -{ - I2C_IntHandler(I2C0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief I2C1 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C1_IRQHandler(void) -{ - I2C_IntHandler(I2C1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief I2C2 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C2_IRQHandler(void) -{ - I2C_IntHandler(I2C0_MM_ID); -} -#endif - -/****************************************************************************/ /** - * @brief I2C3 IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void I2C3_IRQHandler(void) -{ - I2C_IntHandler(I2C1_MM_ID); -} -#endif - -/*@} end of group I2C_Public_Functions */ - -/*@} end of group I2C */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c deleted file mode 100644 index 5e8fb35959..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_i2s.c +++ /dev/null @@ -1,508 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_i2s.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_i2s.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup I2S - * @{ - */ - -/** @defgroup I2S_Private_Macros - * @{ - */ - -static const uint32_t i2sAddr[I2S_ID_MAX] = { I2S_BASE }; -#define I2S_USE_ID I2S0_ID - -/*@} end of group I2S_Private_Macros */ - -/** @defgroup I2S_Private_Types - * @{ - */ - -/*@} end of group I2S_Private_Types */ - -/** @defgroup I2S_Private_Variables - * @{ - */ - -/*@} end of group I2S_Private_Variables */ - -/** @defgroup I2S_Global_Variables - * @{ - */ - -/*@} end of group I2S_Global_Variables */ - -/** @defgroup I2S_Private_Fun_Declaration - * @{ - */ - -/*@} end of group I2S_Private_Fun_Declaration */ - -/** @defgroup I2S_Private_Functions - * @{ - */ - -/*@} end of group I2S_Private_Functions */ - -/** @defgroup I2S_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief I2S BCLK config - * - * @param i2sId: I2S ID type - * @param i2sCfg: I2S configuration pointer - * - * @return NONE - * -*******************************************************************************/ -void I2S_SetBclkPeriod(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg) -{ - uint32_t overSampleRate; - uint32_t bclkDivCnt; - uint32_t tmpVal; - uint8_t enumOffset = 2; - uint32_t I2Sx = i2sAddr[i2sId]; - - CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize)); - - if (i2sCfg->fsChannel == I2S_FS_CHANNELS_6) { - enumOffset = 3; - } - overSampleRate = i2sCfg->audioFreqHz / i2sCfg->sampleFreqHz; - - switch (i2sCfg->frameSize) { - case I2S_SIZE_FRAME_8: - bclkDivCnt = overSampleRate / (8 * (i2sCfg->fsChannel + enumOffset)); - break; - - case I2S_SIZE_FRAME_16: - bclkDivCnt = overSampleRate / (16 * (i2sCfg->fsChannel + enumOffset)); - break; - - case I2S_SIZE_FRAME_24: - bclkDivCnt = overSampleRate / (24 * (i2sCfg->fsChannel + enumOffset)); - break; - - case I2S_SIZE_FRAME_32: - bclkDivCnt = overSampleRate / (32 * (i2sCfg->fsChannel + enumOffset)); - break; - - default: - bclkDivCnt = overSampleRate / (16 * (i2sCfg->fsChannel + enumOffset)); - break; - } - - bclkDivCnt = (bclkDivCnt / 2) - 1; - - tmpVal = (bclkDivCnt << 16) | bclkDivCnt; - BL_WR_REG(I2Sx, I2S_BCLK_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S configuration - * - * @param i2sId: I2S ID type - * @param i2sCfg: I2S configuration pointer - * - * @return NONE - * -*******************************************************************************/ -void I2S_Init(I2S_ID_Type i2sId, I2S_CFG_Type *i2sCfg) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2S_ENDIAN_TYPE(i2sCfg->endianType)); - CHECK_PARAM(IS_I2S_MODE_TYPE(i2sCfg->modeType)); - CHECK_PARAM(IS_I2S_FRAME_SIZE_TYPE(i2sCfg->frameSize)); - CHECK_PARAM(IS_I2S_FS_MODE_TYPE(i2sCfg->fsMode)); - CHECK_PARAM(IS_I2S_FS_CHANNEL_TYPE(i2sCfg->fsChannel)); - CHECK_PARAM(IS_I2S_DATA_SIZE_TYPE(i2sCfg->dataSize)); - CHECK_PARAM(IS_I2S_MONO_MODE_CHANNEL(i2sCfg->monoModeChannel)); - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_I2S); - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - - /* Set data endian*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_ENDIAN, i2sCfg->endianType); - - /* Set I2S mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_MODE, i2sCfg->modeType); - - /* Set BCLK invert */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, i2sCfg->bclkInvert); - - /* Set FS size */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FRAME_SIZE, i2sCfg->frameSize); - - /* Set FS invert */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, i2sCfg->fsInvert); - - /* Set FS mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_1T_MODE, i2sCfg->fsMode); - - /* Set FS channel mode */ - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FS_CH_CNT, i2sCfg->fsChannel); - - /* Set Data size */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DATA_SIZE, i2sCfg->dataSize); - - /* Set Data offset */ - if (i2sCfg->dataOffset != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_OFS_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_OFS_CNT, i2sCfg->dataOffset - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_OFS_EN); - } - - /* Set mono mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_MODE, i2sCfg->monoMode); - - /* Set rx mono mode channel left or right */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_MONO_RX_CH, i2sCfg->monoModeChannel); - - /* Clear mute mode */ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); - - I2S_SetBclkPeriod(I2S_USE_ID, i2sCfg); -} - -/****************************************************************************/ /** - * @brief I2S configure FIFO function - * - * @param i2sId: I2S ID type - * @param fifoCfg: FIFO configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void I2S_FifoConfig(I2S_ID_Type i2sId, I2S_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - /* Set packed mode */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_MERGE, fifoCfg->lRMerge); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_LR_EXCHG, fifoCfg->frameDataExchange); - /* Clear tx and rx FIFO signal */ - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); - - /* Set DMA config */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_TX_EN, fifoCfg->txfifoDmaEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_DMA_RX_EN, fifoCfg->rxfifoDmaEnable); - - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); - - /* Set CLR signal to 0*/ - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1); - /* Set TX and RX FIFO threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_TX_FIFO_TH, fifoCfg->txFifoLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_RX_FIFO_TH, fifoCfg->rxFifoLevel); - - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S configure IO function - * - * @param i2sId: I2S ID type - * @param ioCfg: IO configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void I2S_IOConfig(I2S_ID_Type i2sId, I2S_IOCfg_Type *ioCfg) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_IO_CONFIG); - /* Enable or disable deglitch */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_EN, ioCfg->deglitchEn); - - /* Set deglitch cycle count */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_DEG_CNT, ioCfg->deglitchCnt); - - /* Enable or disable inverse BCLK signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_BCLK_INV, ioCfg->inverseBCLK); - - /* Enable or disable inverse FS signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_FS_INV, ioCfg->inverseFS); - - /* Enable or disable inverse RX signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_RXD_INV, ioCfg->inverseRX); - - /* Enable or disable inverse TX signal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_I2S_TXD_INV, ioCfg->inverseTX); - - BL_WR_REG(I2Sx, I2S_IO_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable I2S - * - * @param i2sId: I2S ID type - * @param roleType: I2S master or slave - * - * @return None - * -*******************************************************************************/ -void I2S_Enable(I2S_ID_Type i2sId, I2S_Role_Type roleType) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2S_ROLE_TYPE(roleType)); - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN); - - /* Set role type */ - if (I2S_ROLE_MASTER == roleType) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); - } else if (I2S_ROLE_SLAVE == roleType) { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); - } - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable I2S - * - * @param i2sId: I2S ID type - * - * @return None - * -*******************************************************************************/ -void I2S_Disable(I2S_ID_Type i2sId) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_TXD_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_RXD_EN); - - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_M_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_I2S_S_EN); - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S read data - * - * @param i2sId: I2S ID type - * - * @return Data read - * -*******************************************************************************/ -uint32_t I2S_Read(I2S_ID_Type i2sId) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT)) { - }; - - return BL_RD_REG(I2Sx, I2S_FIFO_RDATA); -} - -/****************************************************************************/ /** - * @brief I2S write data - * - * @param i2sId: I2S ID type - * @param data: write data - * - * @return None - * -*******************************************************************************/ -void I2S_Write(I2S_ID_Type i2sId, uint32_t data) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - while (0 == BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT)) { - }; - - BL_WR_REG(I2Sx, I2S_FIFO_WDATA, data); -} - -/****************************************************************************/ /** - * @brief I2S set mute - * - * @param i2sId: I2S ID type - * @param enabled: mute enabled or not - * - * @return None - * -*******************************************************************************/ -void I2S_Mute(I2S_ID_Type i2sId, BL_Fun_Type enabled) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_CONFIG); - - if (enabled ? 1 : 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, I2S_CR_MUTE_MODE); - } - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S set 24-bit data align mode in fifo - * - * @param i2sId: I2S ID type - * @param justType: Align mode - * - * @return None - * -*******************************************************************************/ -void I2S_SetFifoJustified(I2S_ID_Type i2sId, I2S_FIFO_24_Justified_Type justType) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - /* Check the parameters */ - CHECK_PARAM(IS_I2S_FIFO_24_JUSTIFIED_TYPE(justType)); - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, I2S_CR_FIFO_24B_LJ, justType); - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S flush - * - * @param i2sId: I2S ID type - * - * @return data count in TX FIFO - * -*******************************************************************************/ -uint32_t I2S_GetTxFIFO_AvlCnt(I2S_ID_Type i2sId) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - return BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief I2S flush - * -* @param i2sId: I2S ID type - * - * @return data count in RX FIFO - * -*******************************************************************************/ -uint32_t I2S_GetRxFIFO_AvlCnt(I2S_ID_Type i2sId) -{ - uint32_t I2Sx = i2sAddr[i2sId]; - - return BL_GET_REG_BITS_VAL(BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_1), I2S_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief I2S flush - * - * @param i2sId: I2S ID type - * - * @return None - * -*******************************************************************************/ -void I2S_Tx_FIFO_Flush(I2S_ID_Type i2sId) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_TX_FIFO_CLR); - - BL_WR_REG(I2Sx, I2S_CONFIG, tmpVal); -} - -/****************************************************************************/ /** - * @brief I2S flush - * - * @param i2sId: I2S ID type - * - * @return None - * -*******************************************************************************/ -void I2S_Rx_FIFO_Flush(I2S_ID_Type i2sId) -{ - uint32_t tmpVal; - uint32_t I2Sx = i2sAddr[i2sId]; - - tmpVal = BL_RD_REG(I2Sx, I2S_FIFO_CONFIG_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, I2S_RX_FIFO_CLR); - - BL_WR_REG(I2Sx, I2S_FIFO_CONFIG_0, tmpVal); -} - -/*@} end of group I2S_Public_Functions */ - -/*@} end of group I2S */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c deleted file mode 100644 index 952504ab10..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ipc.c +++ /dev/null @@ -1,737 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ipc.c - * @version V1.2 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2018 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_ipc.h" - -/** @addtogroup BL606P_Peripheral_Driver - * @{ - */ - -/** @addtogroup IPC - * @{ - */ - -/** @defgroup IPC_Private_Macros - * @{ - */ -#define IPC_LP_OFFSET_IN_M0 0 -#define IPC_D0_OFFSET_IN_M0 16 - -#define IPC_M0_OFFSET_IN_LP 0 -#define IPC_D0_OFFSET_IN_LP 16 - -#define IPC_M0_OFFSET_IN_D0 0 -#define IPC_LP_OFFSET_IN_D0 16 - -/*@} end of group IPC_Private_Macros */ - -/** @defgroup IPC_Private_Types - * @{ - */ - -/*@} end of group IPC_Private_Types */ - -/** @defgroup IPC_Private_Variables - * @{ - */ - -ipcIntCallback *m0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL }; -ipcIntCallback *lpIpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL }; -ipcIntCallback *d0IpcIntCbfArra[GLB_CORE_ID_MAX - 1] = { NULL }; - -/*@} end of group IPC_Private_Variables */ - -/** @defgroup IPC_Global_Variables - * @{ - */ - -/*@} end of group IPC_Global_Variables */ - -/** @defgroup IPC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group IPC_Private_Fun_Declaration */ - -/** @defgroup IPC_Private_Functions - * @{ - */ - -/*@} end of group IPC_Private_Functions */ - -/** @defgroup IPC_Public_Functions - * @{ - */ -#if defined(CPU_M0) || defined(CPU_LP) -/****************************************************************************/ /** - * @brief M0 IPC interrupt init - * - * @param onLPTriggerCallBack: Callback when LP trigger - * - * @param onD0TriggerCallBack: Callback when D0 trigger - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Init(ipcIntCallback *onLPTriggerCallBack, - ipcIntCallback *onD0TriggerCallBack) -{ - m0IpcIntCbfArra[0] = onLPTriggerCallBack; - m0IpcIntCbfArra[1] = onD0TriggerCallBack; - - IPC_M0_Int_Unmask_By_Word(0xffffffff); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_M0_IRQn, IPC_M0_IRQHandler); -#endif - CPU_Interrupt_Enable(IPC_M0_IRQn); -} -#endif - -/****************************************************************************/ /** - * @brief M0 unmask IPC interrupt - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Int_Unmask(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 unmask IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Int_Unmask_By_Word(uint32_t src) -{ - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_IUSR, src); -} - -/****************************************************************************/ /** - * @brief M0 get IPC interrupt raw status - * - * @param None - * - * @return IPC interrupt raw status - * -*******************************************************************************/ -uint32_t IPC_M0_Get_Int_Raw_Status(void) -{ - return BL_RD_REG(IPC0_BASE, IPC_CPU0_IPC_IRSRR); -} - -/****************************************************************************/ /** - * @brief M0 clear IPC interrupt - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Clear_Int(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 clear IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Clear_Int_By_Word(uint32_t src) -{ - BL_WR_REG(IPC0_BASE, IPC_CPU0_IPC_ICR, src); -} - -/****************************************************************************/ /** - * @brief CPUx trigger IPC interrupt to M0 - * - * @param src: IPC interrupt source - * - * @param cpuxOffset: CPU interrupt offset - * - * @return None - * -*******************************************************************************/ -void IPC_CPUx_Trigger_M0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src)); - - tmpVal = (1 << (src + cpuxOffset)); - - BL_WR_REG(IPC0_BASE, IPC_CPU1_IPC_ISWR, tmpVal); -} - -/****************************************************************************/ /** - * @brief LP trigger IPC interrupt to M0 - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Trigger_M0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_M0(src, IPC_LP_OFFSET_IN_M0); -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to M0 - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Trigger_M0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_M0(src, IPC_D0_OFFSET_IN_M0); -} - -#if defined(CPU_M0) || defined(CPU_LP) -/****************************************************************************/ /** - * @brief LP IPC interrupt init - * - * @param onM0TriggerCallBack: Callback when M0 trigger - * - * @param onD0TriggerCallBack: Callback when D0 trigger - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Init(ipcIntCallback *onM0TriggerCallBack, - ipcIntCallback *onD0TriggerCallBack) -{ - lpIpcIntCbfArra[0] = onM0TriggerCallBack; - lpIpcIntCbfArra[1] = onD0TriggerCallBack; - - IPC_LP_Int_Unmask_By_Word(0xffffffff); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_LP_IRQn, IPC_LP_IRQHandler); -#endif - CPU_Interrupt_Enable(IPC_LP_IRQn); -} -#endif - -/****************************************************************************/ /** - * @brief LP unmask IPC interrupt - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Int_Unmask(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, tmpVal); -} - -/****************************************************************************/ /** - * @brief LP unmask IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Int_Unmask_By_Word(uint32_t src) -{ - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_IUSR, src); -} - -/****************************************************************************/ /** - * @brief LP get IPC interrupt raw status - * - * @param None - * - * @return IPC interrupt raw status - * -*******************************************************************************/ -uint32_t IPC_LP_Get_Int_Raw_Status(void) -{ - return BL_RD_REG(IPC1_BASE, IPC_CPU0_IPC_IRSRR); -} - -/****************************************************************************/ /** - * @brief LP clear IPC interrupt - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Clear_Int(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, tmpVal); -} - -/****************************************************************************/ /** - * @brief LP clear IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Clear_Int_By_Word(uint32_t src) -{ - BL_WR_REG(IPC1_BASE, IPC_CPU0_IPC_ICR, src); -} - -/****************************************************************************/ /** - * @brief CPUx trigger IPC interrupt to LP - * - * @param src: IPC interrupt source - * - * @param cpuxOffset: CPU interrupt offset - * - * @return None - * -*******************************************************************************/ -void IPC_CPUx_Trigger_LP(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src)); - - tmpVal = (1 << (src + cpuxOffset)); - - BL_WR_REG(IPC1_BASE, IPC_CPU1_IPC_ISWR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 trigger IPC interrupt to LP - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Trigger_LP(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_LP(src, IPC_M0_OFFSET_IN_LP); -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to LP - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Trigger_LP(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_LP(src, IPC_D0_OFFSET_IN_LP); -} - -#if defined(CPU_D0) || defined(CPU_D1) -/****************************************************************************/ /** - * @brief D0 IPC interrupt init - * - * @param onM0TriggerCallBack: Callback when M0 trigger - * - * @param onLPTriggerCallBack: Callback when LP trigger - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Init(ipcIntCallback *onM0TriggerCallBack, - ipcIntCallback *onLPTriggerCallBack) -{ - d0IpcIntCbfArra[0] = onM0TriggerCallBack; - d0IpcIntCbfArra[1] = onLPTriggerCallBack; - - IPC_D0_Int_Unmask_By_Word(0xffffffff); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IPC_D0_IRQn, IPC_D0_IRQHandler); -#endif - CPU_Interrupt_Enable(IPC_D0_IRQn); -} -#endif - -/****************************************************************************/ /** - * @brief D0 unmask IPC interrupt - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Int_Unmask(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, tmpVal); -} - -/****************************************************************************/ /** - * @brief D0 unmask IPC interrupt by word - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Int_Unmask_By_Word(uint32_t src) -{ - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_IUSR, src); -} - -/****************************************************************************/ /** - * @brief D0 get IPC interrupt raw status - * - * @param None - * - * @return IPC interrupt raw status - * -*******************************************************************************/ -uint32_t IPC_D0_Get_Int_Raw_Status(void) -{ - return BL_RD_REG(IPC2_BASE, IPC_CPU0_IPC_IRSRR); -} - -/****************************************************************************/ /** - * @brief D0 clear IPC interrupt - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Clear_Int(IPC_Int_Src_Type src) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_INT_SRC_TYPE(src)); - - tmpVal = (1 << src); - - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, tmpVal); -} - -/****************************************************************************/ /** - * @brief D0 clear IPC interrupt by word - * - * @param src: IPC interrupt source in word,every bit is interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Clear_Int_By_Word(uint32_t src) -{ - BL_WR_REG(IPC2_BASE, IPC_CPU0_IPC_ICR, src); -} - -/****************************************************************************/ /** - * @brief CPUx trigger IPC interrupt to D0 - * - * @param src: IPC interrupt source - * - * @param cpuxOffset: CPU interrupt offset - * - * @return None - * -*******************************************************************************/ -void IPC_CPUx_Trigger_D0(IPC_Grp_Int_Src_Type src, uint8_t cpuxOffset) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IPC_Grp_Int_Src_Type(src)); - - tmpVal = (1 << (src + cpuxOffset)); - - BL_WR_REG(IPC2_BASE, IPC_CPU1_IPC_ISWR, tmpVal); -} - -/****************************************************************************/ /** - * @brief M0 trigger IPC interrupt to D0 - * - * @param src: M0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Trigger_D0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_D0(src, IPC_M0_OFFSET_IN_D0); -} - -/****************************************************************************/ /** - * @brief LP trigger IPC interrupt to D0 - * - * @param src: LP IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Trigger_D0(IPC_Grp_Int_Src_Type src) -{ - IPC_CPUx_Trigger_D0(src, IPC_LP_OFFSET_IN_D0); -} - -/****************************************************************************/ /** - * @brief M0 trigger IPC interrupt to CPUx - * - * @param tgtCPU: Target CPU - * - * @param src: IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_M0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - switch (tgtCPU) { - case GLB_CORE_ID_LP: - IPC_M0_Trigger_LP(src); - break; - case GLB_CORE_ID_D0: - IPC_M0_Trigger_D0(src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief LP trigger IPC interrupt to CPUx - * - * @param tgtCPU: Target CPU - * - * @param src: IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_LP_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - switch (tgtCPU) { - case GLB_CORE_ID_M0: - IPC_LP_Trigger_M0(src); - break; - case GLB_CORE_ID_D0: - IPC_LP_Trigger_D0(src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to CPUx - * - * @param tgtCPU: Target CPU - * - * @param src: IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_D0_Trigger_CPUx(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - switch (tgtCPU) { - case GLB_CORE_ID_M0: - IPC_D0_Trigger_M0(src); - break; - case GLB_CORE_ID_LP: - IPC_D0_Trigger_LP(src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to D1 - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_Trigger_Target_CPU(GLB_CORE_ID_Type tgtCPU, IPC_Grp_Int_Src_Type src) -{ - GLB_CORE_ID_Type localCPU = GLB_Get_Core_Type(); - - switch (localCPU) { - case GLB_CORE_ID_M0: - IPC_M0_Trigger_CPUx(tgtCPU, src); - break; - case GLB_CORE_ID_LP: - IPC_LP_Trigger_CPUx(tgtCPU, src); - break; - case GLB_CORE_ID_D0: - IPC_D0_Trigger_CPUx(tgtCPU, src); - break; - default: - break; - } -} - -/****************************************************************************/ /** - * @brief D0 trigger IPC interrupt to D1 - * - * @param src: D0 IPC interrupt source - * - * @return None - * -*******************************************************************************/ -void IPC_Common_Interrupt_Handler(uint32_t irqStatus, ipcIntCallback *callBack[GLB_CORE_ID_MAX - 1]) -{ - uint32_t tmp; - uint32_t grp = 0; - - for (grp = 0; grp < GLB_CORE_ID_MAX - 1; grp++) { - tmp = (irqStatus >> (16 * grp)) & 0xffff; - if (tmp != 0) { - if (callBack[grp] != NULL) { - callBack[grp](tmp); - } - } - } -} - -/****************************************************************************/ /** - * @brief M0 IPC IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IPC_M0_IRQHandler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_M0_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, m0IpcIntCbfArra); - IPC_M0_Clear_Int_By_Word(irqStatus); -} -#endif - -/****************************************************************************/ /** - * @brief LP IPC IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IPC_LP_IRQHandler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_LP_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, lpIpcIntCbfArra); - IPC_LP_Clear_Int_By_Word(irqStatus); -} -#endif - -/****************************************************************************/ /** - * @brief D0 IPC IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IPC_D0_IRQHandler(void) -{ - uint32_t irqStatus; - irqStatus = IPC_D0_Get_Int_Raw_Status(); - IPC_Common_Interrupt_Handler(irqStatus, d0IpcIntCbfArra); - IPC_D0_Clear_Int_By_Word(irqStatus); -} -#endif - -/*@} end of group IPC_Public_Functions */ - -/*@} end of group IPC */ - -/*@} end of group BL606P_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c deleted file mode 100644 index 1fb74e6277..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_ir.c +++ /dev/null @@ -1,1269 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_ir.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_ir.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup IR - * @{ - */ - -/** @defgroup IR_Private_Macros - * @{ - */ -#define NEC_HEAD_H_MIN 17000 -#define NEC_HEAD_H_MAX 19000 -#define NEC_HEAD_L_MIN 8400 -#define NEC_HEAD_L_MAX 9600 -#define NEC_BIT0_H_MIN 525 -#define NEC_BIT0_H_MAX 1725 -#define RC5_ONE_PLUSE_MIN 1175 -#define RC5_ONE_PLUSE_MAX 2375 -#define RC5_TWO_PLUSE_MIN 2955 -#define RC5_TWO_PLUSE_MAX 4155 -#define IR_TX_INT_TIMEOUT_COUNT (100 * 320 * 1000) -#define IR_RX_INT_TIMEOUT_COUNT (100 * 320 * 1000) -#define DIVIDE_ROUND(a, b) ((2 * a + b) / (2 * b)) - -/*@} end of group IR_Private_Macros */ - -/** @defgroup IR_Private_Types - * @{ - */ - -/*@} end of group IR_Private_Types */ - -/** @defgroup IR_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *irIntCbfArra[IR_INT_ALL] = { NULL }; -#endif - -/*@} end of group IR_Private_Variables */ - -/** @defgroup IR_Global_Variables - * @{ - */ - -/*@} end of group IR_Global_Variables */ - -/** @defgroup IR_Private_Fun_Declaration - * @{ - */ - -/*@} end of group IR_Private_Fun_Declaration */ - -/** @defgroup IR_Private_Functions - * @{ - */ - -/*@} end of group IR_Private_Functions */ - -/** @defgroup IR_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief IR RX IRQ handler function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IRRX_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - - if (BL_IS_REG_BIT_SET(tmpVal, IRRX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_END_MASK)) { - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - - if (irIntCbfArra[IR_INT_RX_END] != NULL) { - irIntCbfArra[IR_INT_RX_END](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRRX_FRDY_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_FRDY_MASK)) { - if (irIntCbfArra[IR_INT_RX_FIFO_REQ] != NULL) { - irIntCbfArra[IR_INT_RX_FIFO_REQ](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRRX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRRX_FER_MASK)) { - if (irIntCbfArra[IR_INT_RX_FIFO_ERROR] != NULL) { - irIntCbfArra[IR_INT_RX_FIFO_ERROR](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief IR TX IRQ handler function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void IRTX_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - - if (BL_IS_REG_BIT_SET(tmpVal, IRTX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_END_MASK)) { - BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); - - if (irIntCbfArra[IR_INT_TX_END] != NULL) { - irIntCbfArra[IR_INT_TX_END](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRTX_FRDY_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_FRDY_MASK)) { - if (irIntCbfArra[IR_INT_TX_FIFO_REQ] != NULL) { - irIntCbfArra[IR_INT_TX_FIFO_REQ](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, IRTX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, IR_CR_IRTX_FER_MASK)) { - if (irIntCbfArra[IR_INT_TX_FIFO_ERROR] != NULL) { - irIntCbfArra[IR_INT_TX_FIFO_ERROR](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief IR tx initialization function - * - * @param irTxCfg: IR tx configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxInit(IR_TxCfg_Type *irTxCfg) -{ - uint32_t tmpVal; - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR); - - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - /* Set data bit */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, irTxCfg->dataBits - 1); - /* Set tail pulse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_HL_INV, irTxCfg->tailPulseInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_EN, irTxCfg->tailPulse); - /* Set head pulse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_HL_INV, irTxCfg->headPulseInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_EN, irTxCfg->headPulse); - /* Enable or disable logic 1 and 0 pulse inverse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_HL_INV, irTxCfg->logic1PulseInverse); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_HL_INV, irTxCfg->logic0PulseInverse); - /* Enable or disable data pulse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_EN, irTxCfg->dataPulse); - /* Enable or disable output modulation */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_EN, irTxCfg->outputModulation); - /* Enable or disable output inverse */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_OUT_INV, irTxCfg->outputInverse); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_EN, irTxCfg->freerunEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_CONT_EN, irTxCfg->continueEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_FRM_FRAME_SIZE, irTxCfg->frameSize); - - /* Write back */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IRTX_IRQn, IRTX_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR tx pulse width configure function - * - * @param irTxPulseWidthCfg: IR tx pulse width configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxPulseWidthConfig(IR_TxPulseWidthCfg_Type *irTxPulseWidthCfg) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(IR_BASE, IRTX_PW_0); - /* Set logic 0 pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH0_W, irTxPulseWidthCfg->logic0PulseWidth_0 - 1); - /* Set logic 0 pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC0_PH1_W, irTxPulseWidthCfg->logic0PulseWidth_1 - 1); - /* Set logic 1 pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH0_W, irTxPulseWidthCfg->logic1PulseWidth_0 - 1); - /* Set logic 1 pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_LOGIC1_PH1_W, irTxPulseWidthCfg->logic1PulseWidth_1 - 1); - BL_WR_REG(IR_BASE, IRTX_PW_0, tmpVal); - - tmpVal = BL_RD_REG(IR_BASE, IRTX_PW_1); - /* Set head pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH0_W, irTxPulseWidthCfg->headPulseWidth_0 - 1); - /* Set head pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_HEAD_PH1_W, irTxPulseWidthCfg->headPulseWidth_1 - 1); - /* Set tail pulse phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH0_W, irTxPulseWidthCfg->tailPulseWidth_0 - 1); - /* Set tail pulse phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_TAIL_PH1_W, irTxPulseWidthCfg->tailPulseWidth_1 - 1); - BL_WR_REG(IR_BASE, IRTX_PW_1, tmpVal); - - tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); - /* Set modulation phase 0 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH0_W, irTxPulseWidthCfg->moduWidth_0 - 1); - /* Set modulation phase 1 width */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_MOD_PH1_W, irTxPulseWidthCfg->moduWidth_1 - 1); - /* Set pulse width unit */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, irTxPulseWidthCfg->pulseWidthUnit - 1); - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR rx initialization function - * - * @param irRxCfg: IR rx configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_RxInit(IR_RxCfg_Type *irRxCfg) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_RXMODE_TYPE(irRxCfg->rxMode)); - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR); - - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - - /* Set rx mode */ - switch (irRxCfg->rxMode) { - case IR_RX_NEC: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0); - break; - - case IR_RX_RC5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1); - break; - - case IR_RX_SWM: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); - break; - - default: - break; - } - - /* Enable or disable input inverse */ - ENABLE == irRxCfg->inputInverse ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV)); - /* Enable or disable rx input de-glitch function */ - ENABLE == irRxCfg->rxDeglitch ? (tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)) : (tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_DEG_EN)); - /* Set de-glitch function cycle count */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DEG_CNT, irRxCfg->DeglitchCnt); - /* Write back */ - BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); - - tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); - /* Set pulse width threshold to trigger end condition */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, irRxCfg->endThreshold - 1); - /* Set pulse width threshold for logic0/1 detection */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_DATA_TH, irRxCfg->dataThreshold - 1); - /* Write back */ - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(IRRX_IRQn, IRRX_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR configure fifo function - * - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_FifoConfig(IR_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - - /* Set fifo threshold value */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_TX_FIFO_TH, fifoCfg->txFifoThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_TH, fifoCfg->rxFifoThreshold); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable dma function */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IRTX_DMA_EN, fifoCfg->txFifoDmaEnable); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR set default value of all registers function - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_DeInit(void) -{ - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_IR_REMOTE); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR enable function - * - * @param direct: IR direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_Enable(IR_Direction_Type direct) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); - - if (direct == IR_TX || direct == IR_TXRX) { - /* Enable ir tx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_EN)); - } - - if (direct == IR_RX || direct == IR_TXRX) { - /* Enable ir rx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR disable function - * - * @param direct: IR direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_Disable(IR_Direction_Type direct) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_DIRECTION_TYPE(direct)); - - if (direct == IR_TX || direct == IR_TXRX) { - /* Disable ir tx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_EN)); - } - - if (direct == IR_RX || direct == IR_TXRX) { - /* Disable ir rx unit */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR tx software mode enable or disable function - * - * @param txSWM: Enable or disable - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxSWM(BL_Fun_Type txSWM) -{ - uint32_t tmpVal; - - /* Enable or disable tx swm */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - - if (ENABLE == txSWM) { - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); - } else { - BL_WR_REG(IR_BASE, IRTX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRTX_SWM_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR clear rx fifo function - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_RxFifoClear(void) -{ - uint32_t tmpVal; - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_RX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR clear tx fifo function - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_TxFifoClear(void) -{ - uint32_t tmpVal; - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - BL_WR_REG(IR_BASE, IRTX_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, IR_TX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send data function - * - * @param data: data to send - * @param length: Length of send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SendData(uint32_t *data, uint8_t length) -{ - uint32_t txLen = 0; - uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - - while (txLen < length) { - if (IR_GetTxFifoCount() > 0) { - BL_WR_REG(IR_BASE, IR_FIFO_WDATA, data[txLen++]); - timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR software mode send pulse width data function - * - * @param data: data to send - * @param length: Length of send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SWMSendData(uint16_t *data, uint8_t length) -{ - uint8_t i = 0, j = 0; - uint16_t minData = data[0]; - uint32_t tmpVal; - uint32_t count = (length + 3) / 4; - uint32_t pwVal = 0; - - /* Search for min value */ - for (i = 1; i < length; i++) { - if (minData > data[i] && data[i] != 0) { - minData = data[i]; - } - } - - /* Set min value as pulse width unit */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_PULSE_WIDTH); - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_PW_UNIT, minData)); - - /* Calculate tx SWM pulse width data as multiples of pulse width unit */ - for (i = 0; i < count; i++) { - pwVal = 0; - - if (i < count - 1) { - /* Put every four pulse width together as a 32-bit value to tx fifo */ - for (j = 0; j < 4; j++) { - /* Every pulse width divided by pulse width unit */ - tmpVal = (DIVIDE_ROUND(data[j + i * 4], minData) - 1) & 0xff; - /* Tx fifo 32-bit value: pwVal[7:0]:first pulse width, pwVal[15:8]:second pulse width... */ - pwVal |= tmpVal << (8 * j); - } - } else { - /* Deal with pulse width data remained which is less than 4 */ - for (j = 0; j < length % 4; j++) { - tmpVal = (DIVIDE_ROUND(data[j + i * 4], minData) - 1) & 0xff; - pwVal |= tmpVal << (8 * j); - } - } - - /* Write to tx fifo */ - IR_SendData(&pwVal, 1); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send command function - * - * @param data: data to send - * @param length: Length of send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SendCommand(uint32_t *data, uint8_t length) -{ - uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - - /* Write data */ - IR_SendData(data, length); - - /* Mask tx interrupt */ - IR_IntMask(IR_INT_TX_END, MASK); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - /* Enable ir tx */ - IR_Enable(IR_TX); - - /* Wait for tx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_TX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_TX); - - return TIMEOUT; - } - } - - /* Disable ir tx */ - IR_Disable(IR_TX); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send command in software mode function - * - * @param data: IR fifo data to send - * @param length: Length of data - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SWMSendCommand(uint16_t *data, uint8_t length) -{ - uint32_t timeoutCnt = IR_TX_INT_TIMEOUT_COUNT; - - /* Mask tx interrupt */ - IR_IntMask(IR_INT_TX_END, MASK); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - /* Enable ir tx */ - IR_Enable(IR_TX); - - /* Write fifo */ - IR_SWMSendData(data, length); - - /* Wait for tx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_TX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_TX); - - return TIMEOUT; - } - } - - /* Disable ir tx */ - IR_Disable(IR_TX); - - /* Clear tx interrupt */ - IR_ClrIntStatus(IR_INT_TX_END); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send in NEC protocol - * - * @param address: Address - * @param command: Command - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_SendNEC(uint8_t address, uint8_t command) -{ - uint32_t tmpVal = ((~command & 0xff) << 24) + (command << 16) + ((~address & 0xff) << 8) + address; - - IR_SendCommand(&tmpVal, 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR interrupt mask or unmask function - * - * @param intType: IR interrupt type - * @param intMask: Mask or unmask - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_IntMask(IR_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - if (intType < 3) { - /* Mask or unmask tx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - - if (MASK == intMask) { - tmpVal |= 1 << (intType + 8); - } else { - tmpVal &= ~(1 << (intType + 8)); - } - - BL_WR_REG(IR_BASE, IRTX_INT_STS, tmpVal); - } else if (intType < 6) { - /* Mask or unmask rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - - if (MASK == intMask) { - tmpVal |= 1 << (intType + 5); - } else { - tmpVal &= ~(1 << (intType + 5)); - } - - BL_WR_REG(IR_BASE, IRRX_INT_STS, tmpVal); - } else { - if (MASK == intMask) { - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal |= 0x700; - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal |= 0x700; - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - } else { - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal &= ~0x700; - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal &= ~0x700; - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear ir interrupt function - * - * @param intType: IR interrupt type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_ClrIntStatus(IR_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - if (intType == IR_INT_TX_END || intType == IR_INT_ALL) { - /* Clear tx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - BL_WR_REG(IR_BASE, IRTX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRTX_END_CLR)); - } - - if (intType == IR_INT_RX_END || intType == IR_INT_ALL) { - /* Clear rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR install interrupt callback function - * - * @param intType: IR interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type IR_Int_Callback_Install(IR_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - irIntCbfArra[intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief IR get interrupt status function - * - * @param intType: IR int type - * - * @return IR tx or rx interrupt status - * -*******************************************************************************/ -BL_Sts_Type IR_GetIntStatus(IR_INT_Type intType) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_INT_TYPE(intType)); - - /* Read tx or rx interrupt status */ - if (intType < 3) { - tmpVal = BL_RD_REG(IR_BASE, IRTX_INT_STS); - tmpVal &= 1 << intType; - } else if (intType < 6) { - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal &= 1 << (intType - 3); - } else { - } - - if (tmpVal) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief IR get tx/rx fifo underflow or overflow status function - * - * @param fifoSts: IR fifo status type - * - * @return IR fifo status - * -*******************************************************************************/ -BL_Sts_Type IR_GetFifoStatus(IR_FifoStatus_Type fifoSts) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_FIFOSTATUS_TYPE(fifoSts)); - - /* Read rx fifo status */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_0); - - if ((tmpVal & (1U << (fifoSts + IR_TX_FIFO_OVERFLOW_POS))) != 0) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief IR receive data function - * - * @param irWord: IR rx data word 0 or 1 - * - * @return Data received - * -*******************************************************************************/ -uint32_t IR_ReceiveData(IR_Word_Type irWord) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_WORD_TYPE(irWord)); - - /* Read word 0 or word 1 */ - if (IR_WORD_0 == irWord) { - tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD0); - } else { - tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_WORD1); - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR software mode receive pulse width data function - * - * @param data: Data received - * @param length: Max length of receive buffer - * - * @return Length of datas received - * -*******************************************************************************/ -uint8_t IR_SWMReceiveData(uint16_t *data, uint8_t length) -{ - uint8_t rxLen = 0; - - while (rxLen < length && IR_GetRxFifoCount() > 0) { - /* Read data */ - data[rxLen++] = BL_RD_REG(IR_BASE, IR_FIFO_RDATA) & 0xffff; - } - - return rxLen; -} - -/****************************************************************************/ /** - * @brief IR receive in NEC protocol - * - * @param address: Address - * @param command: Command - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type IR_ReceiveNEC(uint8_t *address, uint8_t *command) -{ - uint32_t tmpVal = IR_ReceiveData(IR_WORD_0); - - *address = tmpVal & 0xff; - *command = (tmpVal >> 16) & 0xff; - - if ((~(*address) & 0xff) != ((tmpVal >> 8) & 0xff) || (~(*command) & 0xff) != ((tmpVal >> 24) & 0xff)) { - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR get rx data bit count function - * - * @param None - * - * @return IR rx data bit count - * -*******************************************************************************/ -uint8_t IR_GetRxDataBitCount(void) -{ - uint32_t tmpVal; - - /* Read rx data bit count */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_DATA_COUNT); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_STS_IRRX_DATA_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR get rx fifo count function - * - * @param None - * - * @return IR rx fifo available count - * -*******************************************************************************/ -uint8_t IR_GetRxFifoCount(void) -{ - uint32_t tmpVal; - - /* Read rx fifo count */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_RX_FIFO_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR get tx fifo count function - * - * @param None - * - * @return IR tx fifo available count - * -*******************************************************************************/ -uint8_t IR_GetTxFifoCount(void) -{ - uint32_t tmpVal; - - /* Read tx fifo count */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_FIFO_CONFIG_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_TX_FIFO_CNT); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief IR learning to set rx and tx mode function - * - * @param data: Buffer to save data - * @param length: Length of data - * - * @return Protocol type - * -*******************************************************************************/ -IR_RxMode_Type IR_LearnToInit(uint32_t *data, uint8_t *length) -{ - uint32_t tmpVal; - uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_IR); - - /* Disable rx,set rx in software mode and enable rx input inverse */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x2); - tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_IN_INV); - BL_WR_REG(IR_BASE, IRRX_CONFIG, tmpVal); - /* Set pulse width threshold to trigger end condition */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_PW_CONFIG); - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_END_TH, 19999)); - - /* Clear and mask rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - tmpVal = BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_MASK); - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - - /* Enable rx */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - - /* Wait for rx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_RX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_RX); - - return IR_RX_SWM; - } - } - - /* Disable rx */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_CLR_REG_BIT(tmpVal, IR_CR_IRRX_EN)); - - /* Clear rx interrupt */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_INT_STS); - BL_WR_REG(IR_BASE, IRRX_INT_STS, BL_SET_REG_BIT(tmpVal, IR_CR_IRRX_END_CLR)); - - /*Receive data */ - *length = IR_GetRxFifoCount(); - *length = IR_SWMReceiveData((uint16_t *)data, *length); - - /* Judge protocol type */ - if (NEC_HEAD_H_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < NEC_HEAD_H_MAX && NEC_HEAD_L_MIN < (data[0] >> 16) && (data[0] >> 16) < NEC_HEAD_L_MAX && NEC_BIT0_H_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < NEC_BIT0_H_MAX) { - /* Set rx in NEC mode */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x0)); - /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x23270d47); - /* Set tx in NEC mode */ - /* Tx configure */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, 0x1fc514); - /* Set logic 0,logic 1,head and tail pulse width */ - BL_WR_REG(IR_BASE, IRTX_PW_0, 0x02000000); - BL_WR_REG(IR_BASE, IRTX_PW_1, 0x0000070f); - /* Set modulation phase width and pulse width unit */ - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110464); - - return IR_RX_NEC; - } else if (RC5_ONE_PLUSE_MIN < (data[0] & 0xffff) && (data[0] & 0xffff) < RC5_ONE_PLUSE_MAX && ((RC5_ONE_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[0] >> 16) && (data[0] >> 16) < RC5_TWO_PLUSE_MAX)) && - ((RC5_ONE_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_ONE_PLUSE_MAX) || (RC5_TWO_PLUSE_MIN < (data[1] & 0xffff) && (data[1] & 0xffff) < RC5_TWO_PLUSE_MAX))) { - /* Set rx in RC-5 mode */ - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - BL_WR_REG(IR_BASE, IRRX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE, 0x1)); - /* Set pulse width threshold to trigger end condition and pulse width threshold for logic0/1 detection */ - BL_WR_REG(IR_BASE, IRRX_PW_CONFIG, 0x13870a6a); - /* Set tx in RC-5 mode */ - /* Tx configure */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, 0xcc134); - /* Set logic 0,logic 1,head and tail pulse width */ - BL_WR_REG(IR_BASE, IRTX_PW_0, 0); - BL_WR_REG(IR_BASE, IRTX_PW_1, 0); - /* Set modulation phase width and pulse width unit */ - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x221106f1); - - return IR_RX_RC5; - } else if ((data[0] >> 16) != 0) { - /* Set tx in software mode */ - /* Tx configure */ - BL_WR_REG(IR_BASE, IRTX_CONFIG, *length << 16 | 0xc); - /* Set modulation phase width */ - BL_WR_REG(IR_BASE, IRTX_PULSE_WIDTH, 0x22110000); - - return IR_RX_SWM; - } else { - tmpVal = BL_RD_REG(IR_BASE, IRRX_CONFIG); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, IR_CR_IRRX_MODE); - - if (tmpVal == 0) { - return IR_RX_NEC; - } else if (tmpVal == 1) { - return IR_RX_RC5; - } else { - return IR_RX_SWM; - } - } -} - -/****************************************************************************/ /** - * @brief IR receive data according to mode which is learned function - * - * @param mode: Protocol type - * @param data: Buffer to save data - * - * @return Length of data - * -*******************************************************************************/ -uint8_t IR_LearnToReceive(IR_RxMode_Type mode, uint32_t *data) -{ - uint8_t length = 0; - uint32_t timeoutCnt = IR_RX_INT_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); - - /* Disable ir rx */ - IR_Disable(IR_RX); - - /* Clear and mask rx interrupt */ - IR_ClrIntStatus(IR_INT_RX_END); - IR_IntMask(IR_INT_RX_END, MASK); - - /* Enable ir rx */ - IR_Enable(IR_RX); - - /* Wait for rx interrupt */ - while (SET != IR_GetIntStatus(IR_INT_RX_END)) { - timeoutCnt--; - - if (timeoutCnt == 0) { - IR_Disable(IR_RX); - - return TIMEOUT; - } - } - - /* Disable ir rx */ - IR_Disable(IR_RX); - - /* Clear rx interrupt */ - IR_ClrIntStatus(IR_INT_RX_END); - - /* Receive data according to mode */ - if (mode == IR_RX_NEC || mode == IR_RX_RC5) { - /* Get data bit count */ - length = IR_GetRxDataBitCount(); - data[0] = IR_ReceiveData(IR_WORD_0); - } else { - /* Get fifo count */ - length = IR_GetRxFifoCount(); - length = IR_SWMReceiveData((uint16_t *)data, length); - } - - return length; -} - -/****************************************************************************/ /** - * @brief IR send data according to mode which is learned function - * - * @param mode: Protocol type - * @param data: Buffer of data to send - * @param length: Length of data - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_LearnToSend(IR_RxMode_Type mode, uint32_t *data, uint8_t length) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_IR_RXMODE_TYPE(mode)); - - /* Set send length */ - tmpVal = BL_RD_REG(IR_BASE, IRTX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, IR_CR_IRTX_DATA_NUM, length - 1); - BL_WR_REG(IR_BASE, IRTX_CONFIG, tmpVal); - - if (mode == IR_RX_NEC || mode == IR_RX_RC5) { - IR_SendCommand(data, 1); - } else { - IR_SWMSendCommand((uint16_t *)data, length); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR init to control led function - * - * @param clk: Clock source - * @param div: Clock division(1~64) - * @param unit: Pulse width unit(multiples of clock pulse width, 1~4096) - * @param code0H: code 0 high level time(multiples of pulse width unit, 1~16) - * @param code0L: code 0 low level time(multiples of pulse width unit, 1~16) - * @param code1H: code 1 high level time(multiples of pulse width unit, 1~16) - * @param code1L: code 1 low level time(multiples of pulse width unit, 1~16) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_LEDInit(HBN_MCU_XCLK_Type clk, uint8_t div, uint8_t unit, uint8_t code0H, uint8_t code0L, uint8_t code1H, uint8_t code1L) -{ - IR_TxCfg_Type txCfg = { - 24, /* 24-bit data */ - DISABLE, /* Disable signal of tail pulse inverse */ - DISABLE, /* Disable signal of tail pulse */ - DISABLE, /* Disable signal of head pulse inverse */ - DISABLE, /* Disable signal of head pulse */ - DISABLE, /* Disable signal of logic 1 pulse inverse */ - DISABLE, /* Disable signal of logic 0 pulse inverse */ - ENABLE, /* Enable signal of data pulse */ - DISABLE, /* Disable signal of output modulation */ - ENABLE, /* Enable signal of output inverse */ - DISABLE, /* Disable tx freerun mode */ - DISABLE, /* Disable tx freerun continuous mode */ - IR_FRAME_SIZE_32 /* Frame size */ - }; - - IR_TxPulseWidthCfg_Type txPWCfg = { - code0L, /* Pulse width of logic 0 pulse phase 1 */ - code0H, /* Pulse width of logic 0 pulse phase 0 */ - code1L, /* Pulse width of logic 1 pulse phase 1 */ - code1H, /* Pulse width of logic 1 pulse phase 0 */ - 1, /* Pulse width of head pulse phase 1 */ - 1, /* Pulse width of head pulse phase 0 */ - 1, /* Pulse width of tail pulse phase 1 */ - 1, /* Pulse width of tail pulse phase 0 */ - 1, /* Modulation phase 1 width */ - 1, /* Modulation phase 0 width */ - unit /* Pulse width unit */ - }; - - HBN_Set_MCU_XCLK_Sel(clk); - GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, div - 1); - - /* Disable ir before config */ - IR_Disable(IR_TXRX); - - /* IR tx init */ - IR_TxInit(&txCfg); - IR_TxPulseWidthConfig(&txPWCfg); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief IR send 24-bit data to control led function - * - * @param data: Data to send(24-bit) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type IR_LEDSend(uint32_t data) -{ - /* Change MSB_first to LSB_first */ - data = ((data >> 1) & 0x55555555) | ((data << 1) & 0xaaaaaaaa); - data = ((data >> 2) & 0x33333333) | ((data << 2) & 0xcccccccc); - data = ((data >> 4) & 0x0f0f0f0f) | ((data << 4) & 0xf0f0f0f0); - data = ((data >> 16) & 0xff) | (data & 0xff00) | ((data << 16) & 0xff0000); - IR_SendCommand(&data, 1); - - return SUCCESS; -} - -/*@} end of group IR_Public_Functions */ - -/*@} end of group IR */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c deleted file mode 100644 index 23fcb419b1..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_iso11898.c +++ /dev/null @@ -1,671 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_iso11898.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_glb.h" -#include "bl808_iso11898.h" -#include "bflb_platform.h" - -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type * iso11898IntCbfArra[ISO11898_INT_ALL] = { NULL }; -static void ISO11898_IntHandler(void); -static void ISO11898_IRQHandler(void); -#endif - -void ISO11898_Init(void) -{ - uint32_t tmpVal; - - /* Enable ISO11898 clock witch share with UART2 */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2); - - /* Enable UART clock*/ - tmpVal=BL_RD_REG(GLB_BASE,GLB_UART_CFG0); - tmpVal=BL_SET_REG_BIT(tmpVal,GLB_UART_CLK_EN); - BL_WR_REG(GLB_BASE,GLB_UART_CFG0,tmpVal); - - /* UART2 and ISO11898 can not work together */ - GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_ISO11898); - - /* Need to enter reset mode before operating */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - /* Force using Peli not Basic ISO11898 */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_CLOCK_DIVIDER); - tmpVal = BL_SET_REG_BIT(tmpVal, ISO11898_MODE); - BL_WR_REG(ISO11898_BASE, ISO11898_CLOCK_DIVIDER, tmpVal); - - /* Disable all interrupts */ - BL_WR_REG(ISO11898_BASE, ISO11898_INTERRUPT_ENABLE, 0); - - /* Set clock and sample point */ - ISO11898_Clock_Div_Set(0); - ISO11898_Synchronization_Jump_Width_Set(3); - ISO11898_Sample_Parameter_Set(1, 8, 5); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(UART2_IRQn, ISO11898_IRQHandler); -#endif -} - -void ISO11898_Mode_Set(ISO11898_MODE_Type type, ISO11898_MODE_VALUE_Type value) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_MODE_TYPE(type)); - CHECK_PARAM(IS_ISO11898_MODE_VALUE_TYPE(value)); - - /* Set mode value */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_MODE); - tmpVal &= ~(1 << type); - tmpVal |= (value << type); - - /* Write back */ - BL_WR_REG(ISO11898_BASE, ISO11898_MODE, tmpVal); -} - -ISO11898_MODE_VALUE_Type ISO11898_Mode_Get(ISO11898_MODE_Type type) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_MODE_TYPE(type)); - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_MODE); - tmpVal &= (1 << type); - tmpVal >>= type; - return (ISO11898_MODE_VALUE_Type)tmpVal; -} - -void ISO11898_Int_Enable(ISO11898_INT_Type intType, BL_Fun_Type enable) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INTERRUPT_ENABLE); - /* Enable or Disable certain or all interrupt */ - if(ISO11898_INT_ALL == intType){ - if(ENABLE == enable){ - tmpVal |= 0xFF; - }else{ - tmpVal &= 0; - } - }else{ - if(ENABLE == enable){ - tmpVal |= 1<>= type; - return (ISO11898_STATUS_VALUE_Type)tmpVal; -} - -uint8_t ISO11898_Arbitration_Lost_Position_Get(void) -{ - uint8_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_ARB_LOST_CAPTURE); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_ALC4_0); - return tmpVal; -} - -void ISO11898_Error_Get(ISO11898_ERROR_Type *const type) -{ - uint8_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(type)); - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_ERROR_CODE_CAPTURE); - type->code = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_ERR_CODE); - type->dir = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_DIR); - type->location = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SEGMENT4_0); -} - -BL_Err_Type ISO11898_Error_Warning_Limit_Set(uint8_t limit) -{ - if(ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - BL_WR_REG(ISO11898_BASE, ISO11898_ERROR_WARNING_LIMIT, limit); - return SUCCESS; -} - -uint8_t ISO11898_Error_Warning_Limit_Get(void) -{ - return BL_RD_REG(ISO11898_BASE, ISO11898_ERROR_WARNING_LIMIT); -} - -uint8_t ISO11898_Error_Rx_Counter_Get(void) -{ - return BL_RD_REG(ISO11898_BASE, ISO11898_RX_ERR_COUNT); -} - -uint8_t ISO11898_Error_Tx_Counter_Get(void) -{ - return BL_RD_REG(ISO11898_BASE, ISO11898_TX_ERR_COUNT); -} - -BL_Err_Type ISO11898_Transmit(const ISO11898_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->dataAddr)); - CHECK_PARAM(IS_ISO11898_FRAME_TYPE(cfg->frameType)); - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->frameFormat)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(ISO11898_STATUS_TRANSMIT_BUFFER_LOCKED == ISO11898_Status_Get(ISO11898_STATUS_TRANSMIT_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= ISO11898_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Config information register */ - tmpVal = cfg->dataLen; - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_INF_FF, cfg->frameFormat); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_INF_RTR, cfg->frameType); - BL_WR_REG(ISO11898_BASE, ISO11898_INFORMATION, tmpVal); - - tmpVal = cfg->id; - /* Transmit format with 11 bits ID, SFF */ - if(ISO11898_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Config identifier registers */ - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1, (tmpVal >> 3) & 0xFF); - tmpVal <<= 5; - tmpVal |= (cfg->frameType << 4); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2, tmpVal & 0xFF); - /* Config SFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_SFF_DATA_1_OFFSET); - } - /* Transmit format with 29 bits ID, EFF */ - else - { - /* Config identifier registers */ - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1, (tmpVal >> 21) & 0xFF); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2, (tmpVal >> 13) & 0xFF); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_3, (tmpVal >> 5) & 0xFF); - tmpVal <<= 3; - tmpVal |= (cfg->frameType << 2); - BL_WR_REG(ISO11898_BASE, ISO11898_IDENTIFIER_4, tmpVal & 0xFF); - /* Config EFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_EFF_DATA_1_OFFSET); - } - /* Move data from user buff to registers */ - for (i = 0; i < cfg->dataLen; i++) - { - *(pData + i) = (uint32_t)(*(cfg->dataAddr + i)); - } - - /* Trig a request for transmit */ - if(ISO11898_MODE_VALUE_RESET == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - else if(ISO11898_MODE_VALUE_LISTEN_ONLY == ISO11898_Mode_Get(ISO11898_MODE_TYPE_LISTEN_ONLY)) - { - return ERROR; - } - else if(ISO11898_MODE_VALUE_SELF_TSET == ISO11898_Mode_Get(ISO11898_MODE_TYPE_SELF_TSET)) - { - ISO11898_Cmd_Request_Self_Reception(); - } - else - { - ISO11898_Cmd_Request_Transmit(); - } - - return SUCCESS; -} - -BL_Err_Type ISO11898_Receive(ISO11898_CFG_Type *cfg) -{ - uint32_t timeOut; - uint32_t tmpVal; - uint32_t i; - uint32_t id; - volatile uint32_t *pData; - - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cfg->dataAddr)); - - timeOut = cfg->timeout; - - /* Chcek Timeout type */ - while(ISO11898_STATUS_RECEIVE_BUFFER_EMPTY == ISO11898_Status_Get(ISO11898_STATUS_RECEIVE_BUFFER)) - { - /* Wait no time */ - if (cfg->timeout == 0) - { - return TIMEOUT; - } - /* Wait until transmit buffer accessible */ - if (cfg->timeout >= ISO11898_TIMEOUT_MAX) - { - - } - /* Wait time = cfg->timeOut */ - else - { - if(timeOut == 0) - { - return TIMEOUT; - } - timeOut--; - } - } - - /* Read information register */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INFORMATION); - cfg->frameFormat = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_FF); - cfg->frameType = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_RTR); - cfg->dataLen = BL_GET_REG_BITS_VAL(tmpVal, ISO11898_INF_DLC); - - /* Receive with 11 bits ID */ - if(ISO11898_FRAME_FORMAT_STANDARD == cfg->frameFormat) - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 3); - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2); - id |= (tmpVal & 0xFF) >> 5; - /* Config SFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_SFF_DATA_1_OFFSET); - } - /* Receive with 29 bits ID */ - else - { - /* Read identifier registers */ - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_1); - id = ((tmpVal & 0xFF) << 21); - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_2); - id |= (tmpVal & 0xFF) << 13; - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_3); - id |= (tmpVal & 0xFF) << 5; - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_IDENTIFIER_4); - id |= (tmpVal & 0xFF) >> 3; - /* Config EFF data registers start address */ - pData = (uint32_t *)(ISO11898_BASE + ISO11898_EFF_DATA_1_OFFSET); - } - cfg->id = id; - - /* Move data from registers to user buff */ - for (i = 0; i < cfg->dataLen; i++) - { - *(cfg->dataAddr + i) = (uint8_t)(*(pData + i) & 0xFF); - } - - ISO11898_Cmd_Release_Recv_Buff(); - - return SUCCESS; -} - -uint8_t ISO11898_Receive_Buff_Frame_Count_Get(void) -{ - volatile uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_RX_MESSAGE_COUNT); - return (uint8_t)(tmpVal & 0xFF); -} - -BL_Err_Type ISO11898_Clock_Div_Set(uint8_t div) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_BAUD_RATE_PRESCALER, div); - BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t ISO11898_Clock_Div_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_BAUD_RATE_PRESCALER); -} - -BL_Err_Type ISO11898_Synchronization_Jump_Width_Set(uint8_t width) -{ - uint32_t tmpVal; - - /* Must be operated in reset mode */ - if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_SYNC_JUMP_WIDTH, width); - BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0, tmpVal); - - return SUCCESS; -} - -uint8_t ISO11898_Synchronization_Jump_Width_Get(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_0); - return (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SYNC_JUMP_WIDTH); -} - -BL_Err_Type ISO11898_Sample_Parameter_Set(uint8_t num, uint8_t head, uint8_t tail) -{ - uint32_t tmpVal = 0; - - /* Must be operated in reset mode */ - if (ISO11898_MODE_VALUE_NORMAL == ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET)) - { - return ERROR; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_1, head); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_2, tail); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, ISO11898_SAMPLING, num); - BL_WR_REG(ISO11898_BASE, ISO11898_BUS_TIMING_1, tmpVal & 0xFF); - - return SUCCESS; -} - -void ISO11898_Sample_Parameter_Get(uint8_t *num, uint8_t *head, uint8_t *tail) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_BUS_TIMING_1); - *head = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_1); - *tail = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_TIME_SEGMENT_2); - *num = (uint8_t)BL_GET_REG_BITS_VAL(tmpVal, ISO11898_SAMPLING); -} - -void ISO11898_Filter_Set(const ISO11898_FILTER_CFG_Type *cfg) -{ - uint8_t tmpVal[8] = {0}; //tmpVal[0~3] for match, tmpVal[4~7] for mask - - /* Config filter must be in reset mode */ - ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET); - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - - /* Single filter mode */ - if (ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE == cfg->filterMode) - { - ISO11898_Mode_Set(ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_SINGLE); - /* Filter: ID10~0 + RTR + Data1 + Data2 */ - if (ISO11898_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[2] = cfg->matchData1; - tmpVal[3] = cfg->matchData2; - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (uint8_t)0x0F;//0b1111 for unused bit 3:0 - tmpVal[6] = cfg->maskData1; - tmpVal[7] = cfg->maskData2; - } - /* Filter: ID28~0 + RTR */ - else if(ISO11898_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId1 >> 5); - tmpVal[3] = (uint8_t)(cfg->matchId1 << 3); - tmpVal[3] |= (uint8_t)(cfg->matchRtr1 << 2); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId1 >> 5); - tmpVal[7] = (uint8_t)(cfg->maskId1 << 3); - tmpVal[7] |= (uint8_t)(cfg->maskRtr1 << 2); - tmpVal[7] |= (uint8_t)0x03;//0b11 for unused bit 1:0 - } - } - /* Dual filter mode */ - else if (ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL == cfg->filterMode) - { - ISO11898_Mode_Set(ISO11898_MODE_TYPE_ACCEPTANCE_FILTER, ISO11898_MODE_VALUE_ACCEPTANCE_FILTER_DUAL); - /* Filter1: ID10~0 + RTR + Data1 */ - /* Filter2: ID10~0 + RTR */ - if (ISO11898_FRAME_FORMAT_STANDARD == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 3); - tmpVal[1] = (uint8_t)(cfg->matchId1 << 5); - tmpVal[1] |= (uint8_t)(cfg->matchRtr1 << 4); - tmpVal[1] |= (cfg->matchData1 >> 4); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 3); - tmpVal[3] = (uint8_t)(cfg->matchId2 << 5); - tmpVal[3] |= (uint8_t)(cfg->matchRtr2 << 4); - tmpVal[3] |= (cfg->matchData1 & 0xF); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 3); - tmpVal[5] = (uint8_t)(cfg->maskId1 << 5); - tmpVal[5] |= (uint8_t)(cfg->maskRtr1 << 4); - tmpVal[5] |= (cfg->maskData1 >> 4); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 3); - tmpVal[7] = (uint8_t)(cfg->maskId2 << 5); - tmpVal[7] |= (uint8_t)(cfg->maskRtr2 << 4); - tmpVal[7] |= (cfg->maskData1 & 0xF); - } - /* Filter1: ID28~13 */ - /* Filter2: ID28~13 */ - else if (ISO11898_FRAME_FORMAT_EXTENDED == cfg->formatType) - { - tmpVal[0] = (uint8_t)(cfg->matchId1 >> 21); - tmpVal[1] = (uint8_t)(cfg->matchId1 >> 13); - tmpVal[2] = (uint8_t)(cfg->matchId2 >> 21); - tmpVal[3] = (uint8_t)(cfg->matchId2 >> 13); - tmpVal[4] = (uint8_t)(cfg->maskId1 >> 21); - tmpVal[5] = (uint8_t)(cfg->maskId1 >> 13); - tmpVal[6] = (uint8_t)(cfg->maskId2 >> 21); - tmpVal[7] = (uint8_t)(cfg->maskId2 >> 13); - } - } - /* Write configuration to Registers*/ - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_0, (uint32_t)tmpVal[0]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_1, (uint32_t)tmpVal[1]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_2, (uint32_t)tmpVal[2]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_3, (uint32_t)tmpVal[3]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_0, (uint32_t)tmpVal[4]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_1, (uint32_t)tmpVal[5]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_2, (uint32_t)tmpVal[6]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_3, (uint32_t)tmpVal[7]); - - /* Recovery reset mode value */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset); -} - -void ISO11898_Filter_Register_Set(ISO11898_FILTER_REGISTER_Type reg, uint8_t value) -{ - /* Config filter must be in reset mode */ - ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET); - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - /* Write configuration to Register*/ - BL_WR_WORD(ISO11898_BASE + ISO11898_FILTER_ACCEPTANCE_0_OFFSET + 4 * reg, value); - - /* Recovery reset mode value */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset); -} - -void ISO11898_Filter_Registers_Set(uint8_t *valueArr) -{ - /* Config filter must be in reset mode */ - ISO11898_MODE_VALUE_Type modeReset = ISO11898_Mode_Get(ISO11898_MODE_TYPE_RESET); - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, ISO11898_MODE_VALUE_RESET); - - /* Write configuration to Registers*/ - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_0, (uint32_t)valueArr[0]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_1, (uint32_t)valueArr[1]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_2, (uint32_t)valueArr[2]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_ACCEPTANCE_3, (uint32_t)valueArr[3]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_0, (uint32_t)valueArr[4]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_1, (uint32_t)valueArr[5]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_2, (uint32_t)valueArr[6]); - BL_WR_REG(ISO11898_BASE, ISO11898_FILTER_Mask_3, (uint32_t)valueArr[7]); - - /* Recovery reset mode value */ - ISO11898_Mode_Set(ISO11898_MODE_TYPE_RESET, modeReset); -} - -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type ISO11898_Int_Callback_Install(ISO11898_INT_Type intType,intCallback_Type* cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_ISO11898_FRAME_FORMAT_TYPE(cbFun)); - CHECK_PARAM(IS_ISO11898_INT_TYPE(intType)); - - iso11898IntCbfArra[intType] = cbFun; - - return SUCCESS; -} - -static void ISO11898_IntHandler(void) -{ - uint32_t tmpVal = 0; - uint32_t i = 0; - - tmpVal = BL_RD_REG(ISO11898_BASE, ISO11898_INTERRUPT); - - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_common.h" -#include "bl808_lz4d.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup LZ4D - * @{ - */ - -/** @defgroup LZ4D_Private_Macros - * @{ - */ - -/*@} end of group LZ4D_Private_Macros */ - -/** @defgroup LZ4D_Private_Types - * @{ - */ - -/*@} end of group LZ4D_Private_Types */ - -/** @defgroup LZ4D_Private_Variables - * @{ - */ - -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *lz4dIntCbfArra[LZ4D_INT_ALL] = { NULL }; -#endif - -/*@} end of group LZ4D_Private_Variables */ - -/** @defgroup LZ4D_Global_Variables - * @{ - */ - -/*@} end of group LZ4D_Global_Variables */ - -/** @defgroup LZ4D_Private_Fun_Declaration - * @{ - */ - -/*@} end of group LZ4D_Private_Fun_Declaration */ - -/** @defgroup LZ4D_Private_Functions - * @{ - */ - -/*@} end of group LZ4D_Private_Functions */ - -/** @defgroup LZ4D_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief None - * - * @param None - * - * @return None - * -*******************************************************************************/ -void LZ4D_Stop(void) -{ - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 0; -} - -void LZ4D_Start(void) -{ - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 1; -} - -uint32_t LZ4D_GetAddrReg(LZ4D_ADDR_REG_Type addr) -{ - uint32_t res = -1; - - switch (addr) { - case LZ4D_ADDR_END_SRC: - res = LZ4DECOMPRESSOR->lz4_src_end.WORD & LZ4D_ADDR_END_MAX; - break; - - case LZ4D_ADDR_END_DST: - res = LZ4DECOMPRESSOR->lz4_dst_end.WORD & LZ4D_ADDR_END_MAX; - break; - - case LZ4D_ADDR_BASE_SRC: - res = LZ4DECOMPRESSOR->lz4_src_start.WORD; - break; - - case LZ4D_ADDR_BASE_DST: - res = LZ4DECOMPRESSOR->lz4_dst_start.WORD; - break; - - default: - break; - } - - return res; -} - -uint32_t LZ4D_GetDecompressLen(void) -{ - uint32_t len = 0; - - len = LZ4D_GetAddrReg(LZ4D_ADDR_END_DST) - - (LZ4D_GetAddrReg(LZ4D_ADDR_BASE_DST) & LZ4D_ADDR_END_MAX); - - return len; -} - -uint32_t LZ4D_GetStatus(LZ4D_STATUS_Type sts) -{ - uint32_t res = 0; - - switch (sts) { - case LZ4D_STATUS_DONE ... LZ4D_STATUS_ERROR: - res = LZ4DECOMPRESSOR->lz4_int_sta.WORD & sts; - break; - - default: - break; - } - - return res; -} - -void LZ4D_Decompress(const void *in, void *out) -{ - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 0; - - LZ4DECOMPRESSOR->lz4_src_start.WORD = (uint32_t)(uintptr_t)in; - /* TODO: the out region length must be 4-byte aligned: - * e.g.: the decompressed length is 33, you have to allocate 36 bytes for it. - * or, the HW will overwrite the RAM space from offset 34 to 36. - */ - LZ4DECOMPRESSOR->lz4_dst_start.WORD = (uint32_t)(uintptr_t)out; - - /* flush the CPU D$ in case of data bas been cached, - * e.g., the compressed data is copied by CPU. - */ - //L1C_DCache_Clean_Invalid_All(); - - LZ4DECOMPRESSOR->lz4_config.BF.lz4_en = 1; - - /* after LZ4D doing it's job, CPU has to invalid the cache line for *out */ -} - -/******************************************************************************* - * @brief LZ4D mask or unmask certain or all interrupt - * - * @param intType: interrupt type - * @param intMask: mask or unmask - * - * @return None - * -*******************************************************************************/ -void LZ4D_IntMask(LZ4D_INT_Type intType, BL_Mask_Type intMask) -{ - /* Check the parameters */ - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - switch (intType) { - case LZ4D_INT_DONE: - if (UNMASK == intMask) { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 1; - } else { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 0; - } - break; - - case LZ4D_INT_ERROR: - if (UNMASK == intMask) { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 1; - } else { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 0; - } - break; - - case LZ4D_INT_ALL: - if (UNMASK == intMask) { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 1; - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 1; - } else { - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_done_en = 0; - LZ4DECOMPRESSOR->lz4_int_en.BF.lz4_err_en = 0; - } - break; - - default: - /* invalid param */ - break; - } -} - -/******************************************************************************* - * @brief ADC install interrupt callback - * - * @param intType: ADC interrupt type - * @param cbFun: ADC interrupt callback - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void LZ4D_Int_Callback_Install(LZ4D_INT_Type intType, intCallback_Type *cbFun) -{ - if (intType < LZ4D_INT_ALL) - lz4dIntCbfArra[intType] = cbFun; -} -#endif - -/******************************************************************************* - * @brief LZ4D interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void LZ4D_IRQHandler(void) -{ - if (LZ4D_GetStatus(LZ4D_STATUS_DONE)) { - if (lz4dIntCbfArra[LZ4D_INT_DONE] != NULL) { - lz4dIntCbfArra[LZ4D_INT_DONE](); - } - } - - if (LZ4D_GetStatus(LZ4D_STATUS_ERROR)) { - if (lz4dIntCbfArra[LZ4D_INT_ERROR] != NULL) { - lz4dIntCbfArra[LZ4D_INT_ERROR](); - } - } -} -#endif - -void LZ4D_Init(void) -{ -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(LZ4D_IRQn, LZ4D_IRQHandler); -#endif -} - -/*@} end of group LZ4D_Public_Functions */ - -/*@} end of group LZ4D */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c deleted file mode 100644 index cfce979ae9..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_efuse.c +++ /dev/null @@ -1,105 +0,0 @@ -#include "bl808_glb.h" -#include "bl808_mfg_efuse.h" -#include "bl808_ef_ctrl.h" -#include "bl808_ef_cfg.h" - -static uint8_t rf_cal_slots=3; -extern void main(void); -#define RF_CAL_SLOT_CFG_OFFSET (4*13) -#ifdef BFLB_MCU_SDK -#include "bflb_platform.h" -#define mfg_print MSG -#else -#define mfg_print printf -#endif - -uint8_t mfg_efuse_get_rf_cal_slots(void) -{ - return rf_cal_slots; -} - -void mfg_efuse_set_rf_cal_slots(uint8_t slots) -{ - rf_cal_slots=slots; -} - -uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload) -{ - uint8_t empty=0; - - - if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload)){ - empty=1; - }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload)){ - empty=1; - }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload)){ - empty=1; - }else{ - } - - - return empty; -} - -int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6],uint8_t program) -{ - BL_Err_Type ret=SUCCESS; - uint8_t slot=0xff; - - if(rf_cal_slots>=1&&EF_Ctrl_Is_MAC_Address_Slot_Empty(0,1)){ - slot=0; - }else if(rf_cal_slots>=2&&EF_Ctrl_Is_MAC_Address_Slot_Empty(1,1)){ - slot=1; - }else if(rf_cal_slots>=3&&EF_Ctrl_Is_MAC_Address_Slot_Empty(2,1)){ - slot=2; - }else{ - mfg_print("No empty slot found\r\n"); - } - - if(slot!=0xff){ - ret=EF_Ctrl_Write_MAC_Address_Opt(slot,mac,program); - mfg_print("Write slot:%d\r\n",slot); - } - - - if(ret==SUCCESS){ - return 0; - }else{ - return -1; - } -} - -void mfg_efuse_write_macaddr(void) -{ - EF_Ctrl_Program_Direct_R0(0,NULL,0); - while(SET==EF_Ctrl_Busy()); -} - -int8_t mfg_efuse_read_macaddr(uint8_t mac[6],uint8_t reload) -{ - uint8_t slot=0xff; - BL_Err_Type ret=ERROR; - - - if(rf_cal_slots>=3&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(2,reload))){ - slot=2; - }else if(rf_cal_slots>=2&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(1,reload))){ - slot=1; - }else if(rf_cal_slots>=1&&(!EF_Ctrl_Is_MAC_Address_Slot_Empty(0,reload))){ - slot=0; - } - - if(slot!=0xff){ - mfg_print("Read slot:%d\r\n",slot); - ret=EF_Ctrl_Read_MAC_Address_Opt(slot,mac,reload); - }else{ - mfg_print("No written slot found\r\n"); - } - - - if(ret==SUCCESS){ - return 0; - }else{ - return -1; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c deleted file mode 100644 index 907720aa62..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_flash.c +++ /dev/null @@ -1,241 +0,0 @@ -#include "bl808_mfg_flash.h" -#include "softcrc.h" - -static rf_para_flash_t rf_para; -static uint32_t rf_para_addr=0; -static SPI_Flash_Cfg_Type *pFlashCfg; - -//#define RF_PARA_MAGIC_FLAG 0x41504652 -#define RF_PARA_MAGIC_FLAG 0x41 -#define RF_PARA_VALID_FLAG 0x5A -#define RF_PARA_PART_NAME "rf_para" - - -//PtTable_Stuff_Config ptTableStuff[2]; -//PtTable_Entry_Config ptEntry={0}; - - -static BL_Err_Type PtTable_Flash_Read (uint32_t addr,uint8_t *data, uint32_t len) -{ - //XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg,addr,data,len); - return SUCCESS; -} - -int8_t mfg_flash_init( SPI_Flash_Cfg_Type *flashCfg) -{ -#if 0 - PtTable_ID_Type activeID; - PtTable_Error_Type ret; - - pFlashCfg=flashCfg; - if(pFlashCfg!=NULL){ - PtTable_Set_Flash_Operation(NULL,NULL,PtTable_Flash_Read); - activeID=PtTable_Get_Active_Partition_Need_Lock(ptTableStuff); - if(PT_TABLE_ID_INVALID==activeID){ - //mfg_print("No valid PT\r\n"); - return -1; - } - ret=PtTable_Get_Active_Entries_By_Name(&ptTableStuff[activeID],(uint8_t*)RF_PARA_PART_NAME,&ptEntry); - if(PT_ERROR_SUCCESS==ret){ - rf_para_addr=ptEntry.Address[0]; - //mfg_print("RF para flash address=%08x\r\n",(unsigned int)rf_para_addr); - return 0; - }else{ - //mfg_print("Not found "RF_PARA_PART_NAME"\r\n"); - return -1; - } - } -#endif - return -1; -} - -static int8_t mfg_flash_program(void) -{ -#if 0 - BL_Err_Type ret; - - //mfg_print("mfg_flash_write\r\n"); - - ret=XIP_SFlash_Erase_Need_Lock_Ext(pFlashCfg,rf_para_addr,rf_para_addr+15); - if(ret!=SUCCESS){ - //mfg_print("Flash erase error\r\n"); - return -1; - } - - ret=XIP_SFlash_Write_Need_Lock_Ext(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para)); - if(ret!=SUCCESS){ - //mfg_print("Flash write error\r\n"); - return -1; - } -#endif - return 0; -} - -static int8_t mfg_flash_read(void) -{ -#if 0 - BL_Err_Type ret; - - //mfg_print("mfg_flash_read\r\n"); - - ret=XIP_SFlash_Read_Need_Lock_Ext(pFlashCfg,rf_para_addr,(uint8_t *)&rf_para,sizeof(rf_para)); - if(ret!=SUCCESS){ - //mfg_print("Flash write error\r\n"); - return -1; - } -#endif - return 0; -} - -int8_t mfg_flash_write_xtal_capcode_pre(uint8_t capcode,uint8_t program) -{ -#if 0 - rf_para.magic=RF_PARA_MAGIC_FLAG; - rf_para.capcode_valid=RF_PARA_VALID_FLAG; - rf_para.capcode=capcode; - rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); - - if(program){ - return mfg_flash_program(); - }else{ - return 0; - } -#endif - return 0; -} - -void mfg_flash_write_xtal_capcode(void) -{ - //mfg_flash_program(); -} - -int8_t mfg_flash_read_xtal_capcode(uint8_t *capcode,uint8_t reload) -{ -#if 0 - if((reload!=0)&&(mfg_flash_read()!=0)){ - return -1; - } - if(rf_para.magic==RF_PARA_MAGIC_FLAG){ - if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ - if(rf_para.capcode_valid==RF_PARA_VALID_FLAG){ - *capcode=rf_para.capcode; - return 0; - } - } - } -#endif - return -1; -} - -int8_t mfg_flash_write_poweroffset_pre(int8_t pwrOffset[14],uint8_t program) -{ -#if 0 - rf_para.magic=RF_PARA_MAGIC_FLAG; - rf_para.poweroffset_valid=RF_PARA_VALID_FLAG; - rf_para.poweroffset[0]=pwrOffset[0]; - rf_para.poweroffset[1]=pwrOffset[6]; - rf_para.poweroffset[2]=pwrOffset[12]; - rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); - - if(program){ - return mfg_flash_program(); - }else{ - return 0; - } -#endif - return 0; -} - -void mfg_flash_write_poweroffset(void) -{ - //mfg_flash_program(); -} - -int8_t mfg_flash_read_poweroffset(int8_t pwrOffset[14],uint8_t reload) -{ -#if 0 - int8_t pwrOffsetTmp[3]; - int32_t step=0; - - if((reload!=0)&&(mfg_flash_read()!=0)){ - return -1; - } - if(rf_para.magic==RF_PARA_MAGIC_FLAG){ - if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ - if(rf_para.poweroffset_valid==RF_PARA_VALID_FLAG){ - memset(pwrOffset,0,14); - pwrOffsetTmp[0]=rf_para.poweroffset[0]; - pwrOffsetTmp[1]=rf_para.poweroffset[1]; - pwrOffsetTmp[2]=rf_para.poweroffset[2]; - - pwrOffset[0]=pwrOffsetTmp[0]; - - step=(pwrOffsetTmp[1]-pwrOffsetTmp[0])*100/6; - pwrOffset[1]=(step+50)/100+pwrOffsetTmp[0]; - pwrOffset[2]=(step*2+50)/100+pwrOffsetTmp[0]; - pwrOffset[3]=(step*3+50)/100+pwrOffsetTmp[0]; - pwrOffset[4]=(step*4+50)/100+pwrOffsetTmp[0]; - pwrOffset[5]=(step*5+50)/100+pwrOffsetTmp[0]; - - pwrOffset[6]=pwrOffsetTmp[1]; - - step=(pwrOffsetTmp[2]-pwrOffsetTmp[1])*100/6; - pwrOffset[7]=(step+50)/100+pwrOffsetTmp[1]; - pwrOffset[8]=(step*2+50)/100+pwrOffsetTmp[1]; - pwrOffset[9]=(step*3+50)/100+pwrOffsetTmp[1]; - pwrOffset[10]=(step*4+50)/100+pwrOffsetTmp[1]; - pwrOffset[11]=(step*5+50)/100+pwrOffsetTmp[1]; - - pwrOffset[12]=pwrOffsetTmp[2]; - - pwrOffset[13]=(step*7+50)/100+pwrOffsetTmp[1]; - return 0; - } - } - } -#endif - return -1; - -} - -int8_t mfg_flash_write_macaddr_pre(uint8_t mac[6],uint8_t program) -{ -#if 0 - rf_para.magic=RF_PARA_MAGIC_FLAG; - rf_para.mac_valid=RF_PARA_VALID_FLAG; - memcpy(rf_para.mac,mac,6); - rf_para.crc32=BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8); - - if(program){ - return mfg_flash_program(); - }else{ - return 0; - } -#endif - return 0; -} - -void mfg_flash_write_macaddr(void) -{ - //mfg_flash_program(); -} - -int8_t mfg_flash_read_macaddr(uint8_t mac[6],uint8_t reload) -{ -#if 0 - if((reload!=0)&&(mfg_flash_read()!=0)){ - //mfg_print("mfg_flash_read fail\r\n"); - return -1; - } - if(rf_para.magic==RF_PARA_MAGIC_FLAG){ - if(rf_para.crc32==(BFLB_Soft_CRC32(&rf_para.capcode_valid,sizeof(rf_para)-8))){ - if(rf_para.mac_valid==RF_PARA_VALID_FLAG){ - memcpy(mac,rf_para.mac,6); - return 0; - } - } - } -#endif - return -1; -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c deleted file mode 100644 index 745c2b91d2..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mfg_media.c +++ /dev/null @@ -1,237 +0,0 @@ -#include "bl808_mfg_media.h" - -static uint8_t rf_para_on_flash=0; - -#if 0 -int8_t mfg_media_init_need_lock( SPI_Flash_Cfg_Type *flashCfg) -{ - if(0==mfg_flash_init(flashCfg)){ - rf_para_on_flash=1; - }else{ - rf_para_on_flash=0; - } - return 0; -} - -int8_t mfg_media_init_with_lock( SPI_Flash_Cfg_Type *flashCfg) -{ - int8_t ret; - - __disable_irq(); - ret=mfg_media_init_need_lock(flashCfg); - __enable_irq(); - - return ret; -} - -uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload) -{ - if(rf_para_on_flash){ - return 1; - }else{ - return mfg_efuse_is_xtal_capcode_slot_empty(reload); - } -} - -int8_t mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode,uint8_t program) -{ - if(rf_para_on_flash){ - return mfg_flash_write_xtal_capcode_pre(capcode,program); - }else{ - return mfg_efuse_write_xtal_capcode_pre(capcode,program); - } -} - -int8_t mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode,uint8_t program) -{ - int8_t ret; - - __disable_irq(); - ret=mfg_media_write_xtal_capcode_pre_need_lock(capcode,program); - __enable_irq(); - - return ret; -} - -void mfg_media_write_xtal_capcode_need_lock(void) -{ - if(rf_para_on_flash){ - return mfg_flash_write_xtal_capcode(); - }else{ - return mfg_efuse_write_xtal_capcode(); - } -} - -void mfg_media_write_xtal_capcode_with_lock(void) -{ - __disable_irq(); - mfg_media_write_xtal_capcode_need_lock(); - __enable_irq(); -} - -int8_t mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode,uint8_t reload) -{ - if(rf_para_on_flash){ - return mfg_flash_read_xtal_capcode(capcode,reload); - }else{ - return mfg_efuse_read_xtal_capcode(capcode,reload); - } -} - -int8_t mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode,uint8_t reload) -{ - int8_t ret; - - __disable_irq(); - ret=mfg_media_read_xtal_capcode_need_lock(capcode,reload); - __enable_irq(); - - return ret; -} - -int8_t mfg_media_read_xtal_capcode(uint8_t *capcode,uint8_t reload) -{ - return mfg_media_read_xtal_capcode_need_lock(capcode,reload); -} - -uint8_t mfg_media_is_poweroffset_slot_empty(uint8_t reload) -{ - if(rf_para_on_flash){ - return 1; - }else{ - return mfg_efuse_is_poweroffset_slot_empty(reload); - } -} - -int8_t mfg_media_write_poweroffset_pre_need_lock(int8_t pwrOffset[14],uint8_t program) -{ - if(rf_para_on_flash){ - return mfg_flash_write_poweroffset_pre(pwrOffset,program); - }else{ - return mfg_efuse_write_poweroffset_pre(pwrOffset,program); - } -} - -int8_t mfg_media_write_poweroffset_pre_with_lock(int8_t pwrOffset[14],uint8_t program) -{ - int ret; - - __disable_irq(); - ret=mfg_media_write_poweroffset_pre_need_lock(pwrOffset,program); - __enable_irq(); - - return ret; -} - -void mfg_media_write_poweroffset_need_lock(void) -{ - if(rf_para_on_flash){ - return mfg_flash_write_poweroffset(); - }else{ - return mfg_efuse_write_poweroffset(); - } -} - -void mfg_media_write_poweroffset_with_lock(void) -{ - __disable_irq(); - mfg_media_write_poweroffset_need_lock(); - __enable_irq(); -} - -int8_t mfg_media_read_poweroffset_need_lock(int8_t pwrOffset[14],uint8_t reload) -{ - if(rf_para_on_flash){ - return mfg_flash_read_poweroffset(pwrOffset,reload); - }else{ - return mfg_efuse_read_poweroffset(pwrOffset,reload); - } -} - -int8_t mfg_media_read_poweroffset_with_lock(int8_t pwrOffset[14],uint8_t reload) -{ - int ret; - - __disable_irq(); - ret=mfg_media_read_poweroffset_need_lock(pwrOffset,reload); - __enable_irq(); - - return ret; -} - -int8_t mfg_media_read_poweroffset(int8_t pwrOffset[14],uint8_t reload) -{ - return mfg_media_read_poweroffset_need_lock(pwrOffset,reload); -} -#endif -uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload) -{ - if(rf_para_on_flash){ - return 1; - }else{ - return mfg_efuse_is_macaddr_slot_empty(reload); - } -} - -int8_t mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6],uint8_t program) -{ - if(rf_para_on_flash){ - return mfg_flash_write_macaddr_pre(mac,program); - }else{ - return mfg_efuse_write_macaddr_pre(mac,program); - } -} - -int8_t mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6],uint8_t program) -{ - int ret; - - __disable_irq(); - ret=mfg_media_write_macaddr_pre_need_lock(mac,program); - __enable_irq(); - - return ret; -} - -void mfg_media_write_macaddr_need_lock(void) -{ - if(rf_para_on_flash){ - return mfg_flash_write_macaddr(); - }else{ - return mfg_efuse_write_macaddr(); - } -} - -void mfg_media_write_macaddr_with_lock(void) -{ - __disable_irq(); - mfg_media_write_macaddr_need_lock(); - __enable_irq(); -} - -int8_t mfg_media_read_macaddr_need_lock(uint8_t mac[6],uint8_t reload) -{ - if(rf_para_on_flash){ - return mfg_flash_read_macaddr(mac,reload); - }else{ - return mfg_efuse_read_macaddr(mac,reload); - } -} - -int8_t mfg_media_read_macaddr_with_lock(uint8_t mac[6],uint8_t reload) -{ - int ret; - - __disable_irq(); - ret=mfg_media_read_macaddr_need_lock(mac,reload); - __enable_irq(); - - return ret; -} - -int8_t mfg_media_read_macaddr(uint8_t mac[6],uint8_t reload) -{ - - return mfg_media_read_macaddr_need_lock(mac,reload); -} - diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c deleted file mode 100644 index ca0d7e8dd5..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjdec.c +++ /dev/null @@ -1,467 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjdec.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_mjdec.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJDEC - * @{ - */ - -/** @defgroup MJDEC_Private_Macros - * @{ - */ - -/*@} end of group MJDEC_Private_Macros */ - -/** @defgroup MJDEC_Private_Types - * @{ - */ - -/*@} end of group MJDEC_Private_Types */ - -/** @defgroup MJDEC_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type * mjdecIntCbfArra[MJDEC_INT_ALL] = {NULL}; -#endif - -/*@} end of group MJDEC_Private_Variables */ - -/** @defgroup MJDEC_Global_Variables - * @{ - */ - -/*@} end of group MJDEC_Global_Variables */ - -/** @defgroup MJDEC_Private_Fun_Declaration - * @{ - */ - -/*@} end of group MJDEC_Private_Fun_Declaration */ - -/** @defgroup MJDEC_Private_Functions - * @{ - */ - -/*@} end of group MJDEC_Private_Functions */ - -/** @defgroup MJDEC_Public_Functions - * @{ - */ - -/****************************************************************************//** - * @brief Mjdec module init - * - * @param cfg: Mjdec configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void MJDEC_Init(MJDEC_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t q; - - /* disable mjdec */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); - - if(cfg->picQuality < 1) { - q = 1; - } else if(cfg->picQuality > 75) { - q = 100; - } else { - q = cfg->picQuality; - } - - /* basic configure */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_YUV_MODE, cfg->yuv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_W_XLEN, cfg->burstWrite); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_R_XLEN, cfg->burstRead); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_U_EVEN, cfg->evenOrderEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_BLK_DMY, cfg->dmyBlock); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_HBLK_DMY, cfg->dmyVertical); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_LAST_HF_WBLK_DMY, cfg->dmyHorizational); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_SWAP_MODE, cfg->swapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_Q_MODE, q); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,MJDEC_REG_FRAME_CNT_TRGR_INT,cfg->intCnt); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3,tmpVal); - - /* align buffer to 16 bytes boundary */ - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_YY_FRAME_ADDR, (cfg->bufferFrameYY + 0xF) & (~0xF)); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_UV_FRAME_ADDR, (cfg->bufferFrameUV + 0xF) & (~0xF)); - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_FRAME_SIZE); - switch(cfg->yuv) - { - case MJDEC_YUV422_PLANAR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+15)>>4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+7)>>3); - break; - case MJDEC_YUV420: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+15)>>4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+15)>>4); - break; - case MJDEC_YUV400: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_WBLK, (cfg->resolutionX+7)>>3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_FRAME_HBLK, (cfg->resolutionY+7)>>3); - break; - default: - break; - } - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_FRAME_SIZE, tmpVal); - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_HEADER_SKIP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_HDER_SKIP, cfg->headSkip); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_HDER_SKIP_BYTE, cfg->headByte); - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_HEADER_SKIP, tmpVal); - - /* Clear interrupt */ - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_INT_CLR, 0x1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(MJDEC_IRQn, MJDEC_IRQHandler); -#endif -} - -/****************************************************************************//** - * @brief Deinit mjdec module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Deinit(void) -{ - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_MJPEG_DEC); -} - -/****************************************************************************//** - * @brief Enable mjdec module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Enable(void) -{ - uint32_t tmpVal; - - /* Enable mjdec module */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); -} - -/****************************************************************************//** - * @brief Disable mjdec module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Disable(void) -{ - uint32_t tmpVal; - - /* Disable mjdec module */ - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_MJ_DEC_ENABLE); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get one mjdec frame - * - * @param info: Mjdec frame infomation pointer - * - * @return None - * -*******************************************************************************/ -void MJDEC_Get_Frame_Info(MJDEC_Frame_Info *info) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3); - info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJDEC_FRAME_VALID_CNT); - info->curFrameAddr = BL_RD_REG(MJDEC_BASE, MJDEC_JP_ADDR0); -} - -/****************************************************************************//** - * @brief Get available count of frames - * - * @param None - * - * @return Frames count - * -*******************************************************************************/ -uint8_t MJDEC_Get_Frame_Count(void) -{ - return (uint8_t)BL_GET_REG_BITS_VAL(BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3), MJDEC_FRAME_VALID_CNT); -} - -/****************************************************************************/ /** - * @brief Push one jpeg picture frame - * - * @param bufferMjpeg: jpeg picture frame buffer pointer - * - * @return None - * -*******************************************************************************/ -BL_Err_Type MJDEC_Push_Frame(uint32_t bufferJpeg) -{ - /* because of AXI 64bits, bufferJpeg address bit [0:2] must be 0 */ - if((bufferJpeg & 0x07) != 0) - { - return INVALID; - } - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_FRAM_PUSH, bufferJpeg | 0x1); - return SUCCESS; -} - -/****************************************************************************//** - * @brief Pop one mjdec frame - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJDEC_Pop_Frame(void) -{ - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_INT_CLR, 1 << 1); -} - -/****************************************************************************//** - * @brief Set frame threshold to issue normal interrupt - * - * @param count: Frame threshold - * - * @return None - * -*******************************************************************************/ -void MJDEC_Set_Frame_Threshold(uint8_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,MJDEC_REG_FRAME_CNT_TRGR_INT,count); - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3,tmpVal); -} - -/****************************************************************************//** - * @brief Set Q value - * - * @param q: Q value, must be in 1-75 or 100 - * - * @return None - * -*******************************************************************************/ -void MJDEC_Set_Q_Value(uint8_t q) -{ - uint32_t tmpVal; - - if(q < 1) { - q = 1; - } else if(q > 75) { - q = 100; - } - tmpVal = BL_RD_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJDEC_REG_Q_MODE, q); - BL_WR_REG(MJDEC_BASE, MJDEC_JDEC_CONTROL_1, tmpVal); -} - -/****************************************************************************//** - * @brief MJDEC Enable Disable Interrupt - * - * @param intType: MJDEC Interrupt Type - * @param intMask: Enable or Disable - * - * @return None - * -*******************************************************************************/ -void MJDEC_IntMask(MJDEC_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_MJDEC_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3); - switch(intType) - { - case MJDEC_INT_NORMAL: - if(intMask == UNMASK){ - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_NORMAL_EN); - }else{ - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_NORMAL_EN); - } - break; - - case MJDEC_INT_BACK_IDLE: - if(intMask == UNMASK){ - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - }else{ - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - } - break; - - case MJDEC_INT_ALL: - if(intMask == UNMASK){ - /* Enable all interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJDEC_REG_INT_NORMAL_EN); - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - }else{ - /* Disable all interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJDEC_REG_INT_NORMAL_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal,MJDEC_REG_INT_IDLE_EN); - } - break; - - default: - break; - } - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3,tmpVal); -} - -/****************************************************************************//** - * @brief MJDEC Interrupt Clear - * - * @param intType: MJDEC Interrupt Type - * - * @return None - * -*******************************************************************************/ -void MJDEC_IntClr(MJDEC_INT_Type intType) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_MJDEC_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR); - switch(intType) - { - case MJDEC_INT_NORMAL: - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_CLR); - break; - case MJDEC_INT_BACK_IDLE: - tmpVal = BL_SET_REG_BIT(tmpVal,MJDEC_REG_INT_CLR); - break; - case MJDEC_INT_ALL: - tmpVal = 0x1; - default: - break; - } - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR,tmpVal); -} - -/****************************************************************************//** - * @brief Install mjdec interrupt callback function - * - * @param intType: MJDEC interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJDEC_Int_Callback_Install(MJDEC_INT_Type intType,intCallback_Type* cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_MJDEC_INT_TYPE(intType)); - - mjdecIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************//** - * @brief Mjdec interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJDEC_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJDEC_BASE,MJDEC_JDEC_CONTROL_3); - BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1); - if( BL_IS_REG_BIT_SET(tmpVal, MJDEC_STS_NORMAL_INT) ){ - // BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1); - if(mjdecIntCbfArra[MJDEC_INT_NORMAL] != NULL) { - /* call the callback function */ - mjdecIntCbfArra[MJDEC_INT_NORMAL](); - } - } - if( BL_IS_REG_BIT_SET(tmpVal, MJDEC_STS_IDLE_INT) ){ - // BL_WR_REG(MJDEC_BASE,MJDEC_JDEC_INT_CLR, 0x1); - if(mjdecIntCbfArra[MJDEC_INT_BACK_IDLE] != NULL) { - /* call the callback function */ - mjdecIntCbfArra[MJDEC_INT_BACK_IDLE](); - } - } -} -#endif - - -/*@} end of group MJDEC_Public_Functions */ - -/*@} end of group MJDEC */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c deleted file mode 100644 index b41bc29a78..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_mjpeg.c +++ /dev/null @@ -1,1006 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_mjpeg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808.h" -#include "bl808_mjpeg.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup MJPEG - * @{ - */ - -/** @defgroup MJPEG_Private_Macros - * @{ - */ - -/*@} end of group MJPEG_Private_Macros */ - -/** @defgroup MJPEG_Private_Types - * @{ - */ - -/*@} end of group MJPEG_Private_Types */ - -/** @defgroup MJPEG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *mjpegIntCbfArra[MJPEG_INT_ALL] = { NULL }; -#endif - -/*@} end of group MJPEG_Private_Variables */ - -/** @defgroup MJPEG_Global_Variables - * @{ - */ - -/*@} end of group MJPEG_Global_Variables */ - -/** @defgroup MJPEG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group MJPEG_Private_Fun_Declaration */ - -/** @defgroup MJPEG_Private_Functions - * @{ - */ - -/*@} end of group MJPEG_Private_Functions */ - -/** @defgroup MJPEG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Mjpeg module init - * - * @param cfg: Mjpeg configuration structure pointer - * - * @return None - * -*******************************************************************************/ -void MJPEG_Init(MJPEG_CFG_Type *cfg) -{ - uint32_t tmpVal; - - /* Disable clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_MJPEG); - - /* disable mjpeg */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); - - /* basic configure */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_HW_FRAME, cfg->frameCount); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YUV_MODE, cfg->yuv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_XLEN, cfg->burst); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_BIT_ORDER, cfg->bitOrderEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_ORDER_U_EVEN, cfg->evenOrderEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_READ_FWRAP, cfg->readStartEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_REFLECT_DMY, cfg->reflectDmy); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_HBLK_DMY, cfg->verticalDmy); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_LAST_HF_WBLK_DMY, cfg->horizationalDmy); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_MJPEG_WAIT_CYCLE, cfg->waitCount); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_SIZE); - - switch (cfg->yuv) { - case MJPEG_YUV422_INTERLEAVE: - case MJPEG_YUV422_PLANAR: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3); - break; - - case MJPEG_YUV420: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 15) >> 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 15) >> 4); - break; - - case MJPEG_YUV400: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_WBLK, (cfg->resolutionX + 7) >> 3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_HBLK, (cfg->resolutionY + 7) >> 3); - break; - - default: - break; - } - - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_SIZE, tmpVal); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_W_SWAP_MODE, cfg->swapModeEnable); - BL_WR_REG(MJPEG_BASE, MJPEG_SWAP_MODE, tmpVal); - - /*align buffer to 16 bytes boundary, should be kept the same as CAM module*/ - BL_WR_REG(MJPEG_BASE, MJPEG_YY_FRAME_ADDR, (cfg->bufferCamYY & 0xFFFFFFF0)); - BL_WR_REG(MJPEG_BASE, MJPEG_UV_FRAME_ADDR, (cfg->bufferCamUV & 0xFFFFFFF0)); - BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM, (cfg->sizeCamUV << 16) + cfg->sizeCamYY); - - /*align buffer to 16 bytes boundary*/ - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_FRAME_ADDR, (cfg->bufferMjpeg & 0xFFFFFFF0)); - - /*Set memory brust size */ - if (cfg->burst == MJPEG_BURST_SINGLE) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 8); - } else if (cfg->burst == MJPEG_BURST_INCR4) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 32); - } else if (cfg->burst == MJPEG_BURST_INCR8) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 64); - } else if (cfg->burst == MJPEG_BURST_INCR16) { - BL_WR_REG(MJPEG_BASE, MJPEG_JPEG_STORE_MEMORY, cfg->sizeMjpeg / 128); - } - - /* Clear interrupt */ - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x3F00); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(MJPEG_IRQn, MJPEG_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Mjpeg set YUYV order, only work in interleave mode - * - * @param y0: Y0 order - * @param u0: U0 order - * @param y1: Y1 order - * @param v0: V0 order - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_YUYV_Order_Interleave(uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y0_ORDER, y0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_U0_ORDER, u0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_Y1_ORDER, y1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_V0_ORDER, v0); - BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Mjpeg set Y/UV input cam id, only work in planar mode - * - * @param yCamId: Cam id of Y used - * @param uvCamId: Cam id of UV used - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Planar_Y_UV_Input(uint8_t yCamId, uint8_t uvCamId) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_YY_DVP2AXI_SEL, yCamId); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_UV_DVP2AXI_SEL, uvCamId); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Deinit mjpeg module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Deinit(void) -{ - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_MJPEG); -} - -/****************************************************************************/ /** - * @brief Enable mjpeg module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Enable(void) -{ - uint32_t tmpVal; - - /* Enable mjpeg module */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable mjpeg module - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Disable(void) -{ - uint32_t tmpVal; - - /* Disable mjpeg module */ - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_ENABLE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_1, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable&disable mjpeg software mode and set frame count - * - * @param swType: SW mode type - * @param count: Frame count - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Enable(MJPEG_SW_Mode_Type swType, uint8_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_FRAME, count); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_KICK_MODE, swType); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_MODE); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief MJPEG software mode run, software mode enable first - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Run(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_MJPEG_SW_RUN); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set memory to store block line for frame on SW kick - * - * @param count: Block line count - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Set_Kick_Block(uint16_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_YUV_MEM_SW); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_SW_KICK_HBLK, count); - BL_WR_REG(MJPEG_BASE, MJPEG_YUV_MEM_SW, tmpVal); -} - -/****************************************************************************/ /** - * @brief MJPEG SW mode kick once - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_SW_Kick(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_SW_KICK); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_2, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get one mjpeg frame - * - * @param info: Mjpeg frame infomation pointer - * - * @return None - * -*******************************************************************************/ -void MJPEG_Get_Frame_Info(MJPEG_Frame_Info *info) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - - info->validFrames = BL_GET_REG_BITS_VAL(tmpVal, MJPEG_FRAME_VALID_CNT); - info->curFrameId = BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_ID_10), MJPEG_FRAME_ID_0); - info->curFrameAddr = BL_RD_REG(MJPEG_BASE, MJPEG_START_ADDR0); - info->curFrameBytes = (BL_RD_REG(MJPEG_BASE, MJPEG_BIT_CNT0) + 7) >> 3; - info->status = tmpVal; -} - -/****************************************************************************/ /** - * @brief Get available count of frames - * - * @param None - * - * @return Frames count - * -*******************************************************************************/ -uint8_t MJPEG_Get_Frame_Count(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3), MJPEG_FRAME_VALID_CNT); -} - -/****************************************************************************/ /** - * @brief Pop one mjpeg frame - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Pop_Frame(void) -{ - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 1); -} - -/****************************************************************************/ /** - * @brief Free current read memory block - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Current_Block_Clear(void) -{ - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2); -} - -/****************************************************************************/ /** - * @brief Current read memory block index - * - * @param None - * - * @return Block number - * -*******************************************************************************/ -MJPEG_Swap_Block_Type MJPEG_Get_Current_Block(void) -{ - return (MJPEG_Swap_Block_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_READ_SWAP_IDX); -} - -/****************************************************************************/ /** - * @brief Get block status, full or not full - * - * @param block: Block number - * - * @return Block status - * -*******************************************************************************/ -BL_Sts_Type MJPEG_Block_Is_Full(MJPEG_Swap_Block_Type block) -{ - CHECK_PARAM(IS_MJPEG_SWAP_BLOCK_TYPE(block)); - - if (MJPEG_BLOCK_0 == block) { - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP0_FULL); - } else { - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP1_FULL); - } -} - -/****************************************************************************/ /** - * @brief Current read memory block is frame start - * - * @param None - * - * @return Set or reset - * -*******************************************************************************/ -BL_Sts_Type MJPEG_Current_Block_Is_Start(void) -{ - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FSTART); -} - -/****************************************************************************/ /** - * @brief Current read memory block is frame end - * - * @param None - * - * @return Set or reset - * -*******************************************************************************/ -BL_Sts_Type MJPEG_Current_Block_Is_End(void) -{ - return (BL_Sts_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_MODE), MJPEG_STS_SWAP_FEND); -} - -/****************************************************************************/ /** - * @brief Get frame remain bit count in last block, only valid when current read memory block is - * frame end - * - * @param None - * - * @return Bit count - * -*******************************************************************************/ -uint32_t MJPEG_Get_Remain_Bit(void) -{ - return BL_RD_REG(MJPEG_BASE, MJPEG_SWAP_BIT_CNT); -} - -/****************************************************************************/ /** - * @brief Set frame threshold to issue normal interrupt - * - * @param count: Frame threshold - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Frame_Threshold(uint8_t count) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_FRAME_CNT_TRGR_INT, count); - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set bytes of frame head to preserve - * - * @param size: Bytes of head - * - * @return None - * -*******************************************************************************/ -void MJPEG_Frame_Head_Set_Size(uint16_t size) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_HEAD_BYTE, size); - BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Enable or disable auto fill frame tail with 0xff and 0xd9 - * - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void MJPEG_Frame_Tail_Auto_Fill(BL_Fun_Type enable) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_HEADER_BYTE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MJPEG_REG_TAIL_EXP, enable); - BL_WR_REG(MJPEG_BASE, MJPEG_HEADER_BYTE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Set parameter in Y quantize table according to index - * - * @param index: Q parameter index - * @param qParameter: Q parameter value - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Parameter_Y(uint8_t index, uint16_t qParameter) -{ - uint32_t tmpVal; - - if (index > 63) { - return; - } - - index = index % 8 * 8 + index / 8; - - tmpVal = 2048 / qParameter; - - if (20480 / qParameter % 10 > 4) { - tmpVal++; - } - - qParameter = tmpVal & 0xffff; - - tmpVal = BL_RD_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (index >> 1) * 4); - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (index >> 1) * 4, (tmpVal & 0xffff0000 >> 16 * (index % 2)) | qParameter << 16 * (index % 2)); -} - -/****************************************************************************/ /** - * @brief Set parameter in UV quantize table according to index - * - * @param index: Q parameter index - * @param qParameter: Q parameter value - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Parameter_UV(uint8_t index, uint16_t qParameter) -{ - uint32_t tmpVal; - - if (index > 63) { - return; - } - - index = index % 8 * 8 + index / 8; - - tmpVal = 2048 / qParameter; - - if (20480 / qParameter % 10 > 4) { - tmpVal++; - } - - qParameter = tmpVal & 0xffff; - - tmpVal = BL_RD_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (index >> 1) * 4); - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (index >> 1) * 4, (tmpVal & 0xffff0000 >> 16 * (index % 2)) | qParameter << 16 * (index % 2)); -} - -/****************************************************************************/ /** - * @brief Set Y quantize table - * - * @param qTable: Y table - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Table_Y(uint16_t *qTable) -{ - uint8_t i, j; - uint16_t tmpVal1; - uint16_t tmpVal2; - - for (i = 0; i < 8; i++) { - for (j = 0; j < 4; j++) { - tmpVal1 = 2048 / qTable[16 * j + i]; - tmpVal2 = 2048 / qTable[16 * j + i + 8]; - - if (20480 / qTable[16 * j + i] % 10 > 4) { - tmpVal1++; - } - - if (20480 / qTable[16 * j + i + 8] % 10 > 4) { - tmpVal2++; - } - - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_00_OFFSET + (i * 4 + j) * 4, tmpVal1 | tmpVal2 << 16); - } - } -} - -/****************************************************************************/ /** - * @brief Set UV quantize table - * - * @param qTable: UV table - * - * @return None - * -*******************************************************************************/ -void MJPEG_Set_Quantize_Table_UV(uint16_t *qTable) -{ - uint8_t i, j; - uint16_t tmpVal1; - uint16_t tmpVal2; - - for (i = 0; i < 8; i++) { - for (j = 0; j < 4; j++) { - tmpVal1 = 2048 / qTable[16 * j + i]; - tmpVal2 = 2048 / qTable[16 * j + i + 8]; - - if (20480 / qTable[16 * j + i] % 10 > 4) { - tmpVal1++; - } - - if (20480 / qTable[16 * j + i + 8] % 10 > 4) { - tmpVal2++; - } - - BL_WR_WORD(MJPEG_BASE + MJPEG_Q_PARAM_40_OFFSET + (i * 4 + j) * 4, tmpVal1 | tmpVal2 << 16); - } - } -} - -/****************************************************************************/ /** - * @brief Calculate quantize table according to input table and quality factor - * - * @param inputTable: Pointer of input table - * @param outputTable: Pointer of output table - * @param quality: Quality factor - * - * @return None - * -*******************************************************************************/ -void MJPEG_Calculate_Quantize_Table(uint16_t *inputTable, uint16_t *outputTable, uint8_t quality) -{ - uint32_t scaleFactor, i; - - if (quality == 0) { - quality = 1; - } else if (quality > 100) { - quality = 100; - } - - if (quality < 50) { - scaleFactor = 5000000 / quality; - } else { - scaleFactor = 200000 - quality * 2000; - } - - for (i = 0; i < 64; i++) { - outputTable[i] = (inputTable[i] * scaleFactor + 50000) / 100000; - - if (outputTable[i] == 0) { - outputTable[i] = 1; - } else if (outputTable[i] > 0xff) { - outputTable[i] = 0xff; - } - } -} - -/****************************************************************************/ /** - * @brief Quantize SRAM switch - * - * @param None - * - * @return None - * -*******************************************************************************/ -void MJPEG_Quantize_SRAM_Switch(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_Q_SRAM_SW); - BL_WR_REG(MJPEG_BASE, MJPEG_Q_ENC, tmpVal); -} - -/****************************************************************************/ /** - * @brief Get current quantize SRAM selection for encode - * - * @param None - * - * @return Current quantize SRAM - * -*******************************************************************************/ -uint8_t MJPEG_Get_Current_Quantize_SRAM(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC); - return BL_GET_REG_BITS_VAL(tmpVal, MJPEG_STS_Q_SRAM_ENC); -} - -/****************************************************************************/ /** - * @brief Get frame0~3 quantize SRAM selection - * - * @param frameId: Frame id - * - * @return Quantize SRAM - * -*******************************************************************************/ -uint8_t MJPEG_Get_Frame_Quantize_SRAM(MJPEG_Frame_ID_Type frameId) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_Q_ENC); - return (tmpVal >> frameId & 1); -} - -/****************************************************************************/ /** - * @brief MJPEG Enable Disable Interrupt - * - * @param intType: MJPEG Interrupt Type - * @param intMask: Enable or Disable - * - * @return None - * -*******************************************************************************/ -void MJPEG_IntMask(MJPEG_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - - switch (intType) { - case MJPEG_INT_NORMAL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - } - - break; - - case MJPEG_INT_CAM_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - } - - break; - - case MJPEG_INT_MEM_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - } - - break; - - case MJPEG_INT_FRAME_OVERWRITE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - } - - break; - - case MJPEG_INT_BACK_IDLE: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - } - - break; - - case MJPEG_INT_SWAP: - if (intMask == UNMASK) { - /* Enable this interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } else { - /* Disable this interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } - - break; - - case MJPEG_INT_ALL: - if (intMask == UNMASK) { - /* Enable all interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } else { - /* Disable all interrupt */ - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_EN); - } - - break; - - default: - break; - } - - BL_WR_REG(MJPEG_BASE, MJPEG_CONTROL_3, tmpVal); -} - -/****************************************************************************/ /** - * @brief MJPEG Interrupt Clear - * - * @param intType: MJPEG Interrupt Type - * - * @return None - * -*******************************************************************************/ -void MJPEG_IntClr(MJPEG_INT_Type intType) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP); - - switch (intType) { - case MJPEG_INT_NORMAL: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_NORMAL_CLR); - break; - - case MJPEG_INT_CAM_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_CAM_CLR); - break; - - case MJPEG_INT_MEM_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_MEM_CLR); - break; - - case MJPEG_INT_FRAME_OVERWRITE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_FRAME_CLR); - break; - - case MJPEG_INT_BACK_IDLE: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_IDLE_CLR); - break; - - case MJPEG_INT_SWAP: - tmpVal = BL_SET_REG_BIT(tmpVal, MJPEG_REG_INT_SWAP_CLR); - break; - - case MJPEG_INT_ALL: - tmpVal = 0x3F00; - - default: - break; - } - - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, tmpVal); -} - -/****************************************************************************/ /** - * @brief Install mjpeg interrupt callback function - * - * @param intType: MJPEG interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJPEG_Int_Callback_Install(MJPEG_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_MJPEG_INT_TYPE(intType)); - - mjpegIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Mjpeg interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void MJPEG_IRQHandler(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(MJPEG_BASE, MJPEG_CONTROL_3); - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_NORMAL_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x100); - - if (mjpegIntCbfArra[MJPEG_INT_NORMAL] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_NORMAL](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_CAM_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x200); - - if (mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_CAM_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_MEM_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x400); - - if (mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_MEM_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_FRAME_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x800); - - if (mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_FRAME_OVERWRITE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_IDLE_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x1000); - - if (mjpegIntCbfArra[MJPEG_INT_BACK_IDLE] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_BACK_IDLE](); - } - } - - if (BL_IS_REG_BIT_SET(tmpVal, MJPEG_STS_SWAP_INT)) { - BL_WR_REG(MJPEG_BASE, MJPEG_FRAME_FIFO_POP, 0x2000); - - if (mjpegIntCbfArra[MJPEG_INT_SWAP] != NULL) { - /* call the callback function */ - mjpegIntCbfArra[MJPEG_INT_SWAP](); - } - } -} -#endif - -/*@} end of group MJPEG_Public_Functions */ - -/*@} end of group MJPEG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c deleted file mode 100644 index 998c6dddab..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_blend.c +++ /dev/null @@ -1,480 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_blend.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_osd_blend.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_BLEND - * @{ - */ - -/** @defgroup OSD_BLEND_Private_Macros - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Macros */ - -/** @defgroup OSD_BLEND_Private_Types - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Types */ - -/** @defgroup OSD_BLEND_Private_Variables - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Variables */ - -/** @defgroup OSD_BLEND_Global_Variables - * @{ - */ - -/*@} end of group OSD_BLEND_Global_Variables */ - -/** @defgroup OSD_BLEND_Private_Fun_Declaration - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Fun_Declaration */ - -/** @defgroup OSD_BLEND_Private_Functions - * @{ - */ - -/*@} end of group OSD_BLEND_Private_Functions */ - -/** @defgroup OSD_BLEND_Public_Functions - * @{ - */ - -/****************************************************************************** - * @brief OSD blend layer configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param xstart: OSD layer start point: x-axis, better to be even. - * @param ystart: OSD layer start point: y-axis, better to be even. - * @param xend: OSD layer end point: x-axis, better to be odd. - * @param yend: OSD layer end point: y-axis, better to be odd. - * @param data: OSD layer data buffer pointer. - * @param dat_len: data length in dword size(8bytes). - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_config_layer(osd_blend_reg_t *pblend, - uint32_t xstart, uint32_t ystart, - uint32_t xend, uint32_t yend, - uintptr_t *data, uint32_t dat_len) -{ - pblend->obnd_layer_xconfig.WORD = (xstart & OSD_BLEND_OBND_X_MIN_MSK) | - ((xend << OSD_BLEND_OBND_X_MAX_POS) & OSD_BLEND_OBND_X_MAX_MSK); - pblend->obnd_layer_yconfig.WORD = (ystart & OSD_BLEND_OBND_Y_MIN_MSK) | - ((yend << OSD_BLEND_OBND_Y_MAX_POS) & OSD_BLEND_OBND_Y_MAX_MSK); - - pblend->obnd_mem_config1.WORD = (uint32_t)(uintptr_t)data; - pblend->obnd_mem_config2.WORD = dat_len; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer mem access timing configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param req_hlen: memory access timing setting in H-SYNC cycles after V-SYNC. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_mem_access_line(osd_blend_reg_t *pblend, uint32_t req_hlen) -{ - pblend->obnd_sh.BF.obnd_layer_mem_req_cnt = req_hlen; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer force shadow control: - * call this API before DSP2 streaming on to ensure the OSD layer - * is activated even in frame 0. - * After calling this API, this OSD blending layer has to be enabled. - * - * @param pblend: pointer to a specific OSD blend layer - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_layer_early_commit(osd_blend_reg_t *pblend) -{ - uint32_t val = 0; - - val = pblend->obnd_mem_config0.WORD; - /* disable this layer */ - val &= OSD_BLEND_OBND_LAYER_EN_UMSK; - /* set OSD blend force shadow bit, so that the settings will be loaded - * immediately and mem access will be started after layer is enabled. - */ - val |= OSD_BLEND_OBND_FORCE_SH_MSK; - pblend->obnd_mem_config0.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer enable/disable control - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: requested state of this blend layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_ctrl_layer(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable) -{ - uint32_t val = 0; - - val = pblend->obnd_mem_config0.WORD; - val &= OSD_BLEND_OBND_LAYER_EN_UMSK; - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_LAYER_EN_MSK : 0; - pblend->obnd_mem_config0.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer color format configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param fmt: color format. - * @param order_alpha: order of the alpha. - * @param order_r_v: order of the red(RGB) or v(YUV). - * @param order_g_y: order of the green(RGB) or y(YUV). - * @param order_b_u: order of the blue(RGB) or u(YUV). - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_set_color_format(osd_blend_reg_t *pblend, OSD_BLEND_COLOR_FMT_e fmt, - OSD_BLEND_COLOR_ORDER_e order_alpha, - OSD_BLEND_COLOR_ORDER_e order_r_v, - OSD_BLEND_COLOR_ORDER_e order_g_y, - OSD_BLEND_COLOR_ORDER_e order_b_u) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config0.WORD; - val &= ~(OSD_BLEND_OBND_COLOR_FORMAT_MSK | - OSD_BLEND_OBND_ORDER_A_MSK | - OSD_BLEND_OBND_ORDER_RV_MSK | - OSD_BLEND_OBND_ORDER_GY_MSK | - OSD_BLEND_OBND_ORDER_BU_MSK); - - val |= fmt << OSD_BLEND_OBND_COLOR_FORMAT_POS; - val |= order_alpha << OSD_BLEND_OBND_ORDER_A_POS; - val |= order_r_v << OSD_BLEND_OBND_ORDER_RV_POS; - val |= order_g_y << OSD_BLEND_OBND_ORDER_GY_POS; - val |= order_b_u << OSD_BLEND_OBND_ORDER_BU_POS; - - pblend->obnd_layer_config0.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer global alpha configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the global alpha for this layer. - * @param alpha: value of the alpha. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_set_global_alpha(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t alpha) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config0.WORD; - val &= OSD_BLEND_OBND_GLOBAL_A_UMSK; - val &= OSD_BLEND_OBND_GLOBAL_A_EN_UMSK; - val |= (alpha << OSD_BLEND_OBND_GLOBAL_A_POS) & OSD_BLEND_OBND_GLOBAL_A_MSK; - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_GLOBAL_A_EN_MSK : 0; - pblend->obnd_layer_config0.WORD = val; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer global color configuration - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the global color for this layer. - * @param r_v: value of the red(RGB) or v(YUV). - * @param g_y: value of the green(RGB) or y(YUV). - * @param b_u: value of the blue(RGB) or u(YUV). - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_set_global_color(osd_blend_reg_t *pblend, uint32_t enable, - uint8_t r_v, uint8_t g_y, uint8_t b_u) -{ - uint32_t val = 0; - - val = (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_GLOBAL_COLOR_EN_MSK : 0; - val |= (r_v << OSD_BLEND_OBND_GLOBAL_RV_POS) & OSD_BLEND_OBND_GLOBAL_RV_MSK; - val |= (g_y << OSD_BLEND_OBND_GLOBAL_GY_POS) & OSD_BLEND_OBND_GLOBAL_GY_MSK; - val |= (b_u << OSD_BLEND_OBND_GLOBAL_BU_POS) & OSD_BLEND_OBND_GLOBAL_BU_MSK; - pblend->obnd_layer_config1.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer update palette value according to the index. - * - * @param pblend: pointer to a specific OSD blend layer - * @param color: palette color, can be format ARGB8888 or AYUV8888. - * @param index: the palette index for updating. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_update_palette(osd_blend_reg_t *pblend, uint32_t color, uint8_t index) -{ - uint32_t val = 0; - - /* palette should be updated when blend is disabled. */ - - pblend->obnd_layer_config7.WORD = color; - val = pblend->obnd_layer_config6.WORD; - val &= OSD_BLEND_OBND_UPDATE_INDEX_UMSK; - val |= index << OSD_BLEND_OBND_UPDATE_INDEX_POS; - - /* trigger update */ - val |= OSD_BLEND_OBND_UPDATE_TRIGGER_MSK; - pblend->obnd_layer_config6.WORD = val; - arch_delay_us(1); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer palette keying control. - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the palette keying for this layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_palette_keying_ctrl(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config2.WORD; - val &= OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK; - - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_KEY_PALETTE_EN_MSK : 0; - - pblend->obnd_layer_config2.WORD = val; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer palette keying configuration. - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the palette keying for this layer. - * @param mode: palette keying mode: within or out of the min/max range. - * @param replace_index: the palette index that will be used as the replace color. - * @param min_key_index: min index for the palette keying. - * @param max_key_index: max index for the palette keying. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_palette_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - OSB_BLEND_KEYING_MODE_e mode, - uint8_t replace_index, - uint8_t min_key_index, uint8_t max_key_index) -{ - uint32_t val = 0; - - /* disable palette keying */ - val = pblend->obnd_layer_config2.WORD; - val &= OSD_BLEND_OBND_KEY_PALETTE_EN_UMSK; - pblend->obnd_layer_config2.WORD = val; - - /* it is done if palette keying mode is disabled */ - if (OSD_BLEND_ST_ENABLE != enable) { - return SUCCESS; - } - - val |= (OSD_BLEND_ST_ENABLE == enable) ? OSD_BLEND_OBND_KEY_PALETTE_EN_MSK : 0; - val |= (OSB_BLEND_KEYING_INVERT == mode) ? OSD_BLEND_OBND_KEY_INDEX_INV_MSK : 0; - val |= (min_key_index << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) & OSD_BLEND_OBND_KEY_INDEX_MIN_MSK; - val |= (max_key_index << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) & OSD_BLEND_OBND_KEY_INDEX_MAX_MSK; - val |= (replace_index << OSD_BLEND_OBND_KEY_REPLACE_INDEX_POS) & - OSD_BLEND_OBND_KEY_REPLACE_INDEX_MSK; - - pblend->obnd_layer_config2.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer palette keying min/max updating control. - * - * @param pblend: pointer to a specific OSD blend layer - * @param min_key_index: min index for the palette keying. - * @param max_key_index: max index for the palette keying. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_palette_keying_update_range(osd_blend_reg_t *pblend, - uint8_t min_key_index, uint8_t max_key_index) -{ - uint32_t val = 0; - - val = pblend->obnd_layer_config2.WORD; - - val &= OSD_BLEND_OBND_KEY_INDEX_MIN_UMSK; - val &= OSD_BLEND_OBND_KEY_INDEX_MAX_UMSK; - val |= (min_key_index << OSD_BLEND_OBND_KEY_INDEX_MIN_POS) & OSD_BLEND_OBND_KEY_INDEX_MIN_MSK; - val |= (max_key_index << OSD_BLEND_OBND_KEY_INDEX_MAX_POS) & OSD_BLEND_OBND_KEY_INDEX_MAX_MSK; - - pblend->obnd_layer_config2.WORD = val; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD blend layer color keying configuration. - * - * @param pblend: pointer to a specific OSD blend layer - * @param enable: enable or disable the color keying for this layer. - * @param pset: point to the color keying setting. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_blend_color_keying(osd_blend_reg_t *pblend, OSD_BLEND_ST_e enable, - osd_blend_color_keying_set_t *pset) -{ - uint32_t val = 0; - - CHECK_PARAM(NULL != pset); - - /* disable color keying */ - val = pblend->obnd_layer_config6.WORD; - val &= OSD_BLEND_OBND_KEY_COLOR_EN_UMSK; - pblend->obnd_layer_config6.WORD = val; - - /* it is done if color keying mode is disabled */ - if (OSD_BLEND_ST_ENABLE != enable) { - return SUCCESS; - } - - /* layer_config3: min & max for alpha and rv */ - val = pset->min_key_alpha << OSD_BLEND_OBND_KEY_A_MIN_POS; - val |= pset->max_key_alpha << OSD_BLEND_OBND_KEY_A_MAX_POS; - val |= pset->min_key_rv << OSD_BLEND_OBND_KEY_RV_MIN_POS; - val |= pset->max_key_rv << OSD_BLEND_OBND_KEY_RV_MAX_POS; - pblend->obnd_layer_config3.WORD = val; - - /* layer_config4: min & max for gy and bu */ - val = pset->min_key_gy << OSD_BLEND_OBND_KEY_GY_MIN_POS; - val |= pset->max_key_gy << OSD_BLEND_OBND_KEY_GY_MAX_POS; - val |= pset->min_key_bu << OSD_BLEND_OBND_KEY_BU_MIN_POS; - val |= pset->max_key_bu << OSD_BLEND_OBND_KEY_BU_MAX_POS; - pblend->obnd_layer_config4.WORD = val; - - /* layer_config5: replace color */ - val = pset->replace_alpha << OSD_BLEND_OBND_KEY_REPLACE_A_POS; - val |= pset->replace_rv << OSD_BLEND_OBND_KEY_REPLACE_RV_POS; - val |= pset->replace_gy << OSD_BLEND_OBND_KEY_REPLACE_GY_POS; - val |= pset->replace_bu << OSD_BLEND_OBND_KEY_REPLACE_BU_POS; - pblend->obnd_layer_config5.WORD = val; - - /* color range inverted? */ - val = pblend->obnd_layer_config6.WORD; - val &= ~(OSD_BLEND_OBND_KEY_A_INV_MSK | - OSD_BLEND_OBND_KEY_RV_INV_MSK | - OSD_BLEND_OBND_KEY_GY_INV_MSK | - OSD_BLEND_OBND_KEY_BU_INV_MSK); - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_alpha) ? - OSD_BLEND_OBND_KEY_A_INV_MSK : - 0; - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_rv) ? - OSD_BLEND_OBND_KEY_RV_INV_MSK : - 0; - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_gy) ? - OSD_BLEND_OBND_KEY_GY_INV_MSK : - 0; - val |= (OSB_BLEND_KEYING_INVERT == pset->mode_bu) ? - OSD_BLEND_OBND_KEY_BU_INV_MSK : - 0; - - /* enable color keying */ - val |= OSD_BLEND_OBND_KEY_COLOR_EN_MSK; - pblend->obnd_layer_config6.WORD = val; - - return SUCCESS; -} - -/*@} end of group OSD_BLEND_Public_Functions */ - -/*@} end of group OSD_BLEND */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c deleted file mode 100644 index 9e0e42c969..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_draw.c +++ /dev/null @@ -1,335 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_blend.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_osd_draw.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_DRAW - * @{ - */ - -/** @defgroup OSD_DRAW_Private_Macros - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Macros */ - -/** @defgroup OSD_DRAW_Private_Types - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Types */ - -/** @defgroup OSD_DRAW_Private_Variables - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Variables */ - -/** @defgroup OSD_DRAW_Global_Variables - * @{ - */ - -/*@} end of group OSD_DRAW_Global_Variables */ - -/** @defgroup OSD_DRAW_Private_Fun_Declaration - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Fun_Declaration */ - -/** @defgroup OSD_DRAW_Private_Functions - * @{ - */ - -/*@} end of group OSD_DRAW_Private_Functions */ - -/** @defgroup OSD_DRAW_Public_Functions - * @{ - */ - -/****************************************************************************** - * @brief OSD draw layer state control - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param state: enable or disable the layer in this draw HW IP. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_set_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - tmpval = odraw->osd_draw_config.WORD; - - if (state == OSD_RECT_STATE_ENABLE) { - tmpval |= layer_mask; - } else { - tmpval &= ~layer_mask; - } - - odraw->osd_draw_config.WORD = tmpval; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer state get - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param state: pointer to return the state value. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_get_layer_state(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type *state) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - CHECK_PARAM(NULL != odraw); - CHECK_PARAM(NULL != state); - - tmpval = odraw->osd_draw_config.WORD; - tmpval &= layer_mask; - *state = (!!tmpval) ? OSD_RECT_STATE_ENABLE : OSD_RECT_STATE_DISABLE; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer style set - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param style: solid or hollow style. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_set_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type style) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - if (style == OSD_RECT_STYLE_SOLID) { - tmpval |= layer_mask << OSD_REG_DRAW_TYPE_L_POS; - } else { - tmpval &= ~(layer_mask << OSD_REG_DRAW_TYPE_L_POS); - } - - odraw->osd_draw_config.WORD = tmpval; - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer style get - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param style: pointer to return the solid or hollow style. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_get_layer_style(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STYLE_Type *style) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - CHECK_PARAM(NULL != odraw); - CHECK_PARAM(NULL != style); - - tmpval = odraw->osd_draw_config.WORD; - tmpval &= layer_mask << OSD_REG_DRAW_TYPE_L_POS; - *style = (!!tmpval) ? OSD_RECT_STYLE_SOLID : OSD_RECT_STYLE_HOLLOW; - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD draw layer control - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param layer: draw layer. - * @param state: enable or disable this draw layer. - * @param style: solid or hollow style for this layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_config_rect_layer(osd_draw_reg_t *odraw, uint32_t layer, OSD_RECT_STATE_Type state, OSD_RECT_STYLE_Type style) -{ - uint32_t tmpval = 0; - uint32_t layer_mask = 1 << OSD_VALID_LAYER(layer); - - tmpval = odraw->osd_draw_config.WORD; - - if (state == OSD_RECT_STATE_ENABLE) { - tmpval |= layer_mask; - } else { - tmpval &= ~layer_mask; - } - - if (style == OSD_RECT_STYLE_SOLID) { - tmpval |= layer_mask << OSD_REG_DRAW_TYPE_L_POS; - } else { - tmpval &= ~(layer_mask << OSD_REG_DRAW_TYPE_L_POS); - } - - odraw->osd_draw_config.WORD = tmpval; - return SUCCESS; -} - -/****************************************************************************** - * @brief Draw a specific rectangle with OSD draw HW IP. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param rect: pointer to a rectangle setting structure. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_rectangle(osd_draw_reg_t *odraw, osd_rectangle_t *rect) -{ - osd_rectangle_desc_t *desc = OSD_RECT_DESC((odraw), OSD_VALID_LAYER(rect->layer)); - - CHECK_PARAM(NULL != odraw); - CHECK_PARAM(NULL != rect); - - osd_draw_set_layer_state(odraw, rect->layer, OSD_RECT_STATE_DISABLE); - desc->attr = rect->desc.attr; - - /* EVEN and ODD */ - rect->desc.pos.x.start &= -2; - rect->desc.pos.x.end |= 1; - rect->desc.pos.y.start &= -2; - rect->desc.pos.y.end |= 1; - rect->desc.attr.yuvt.thinkness += (rect->desc.attr.yuvt.thinkness & 1) ? 1 : 0; - - desc->pos.x = rect->desc.pos.x; - desc->pos.y = rect->desc.pos.y; - osd_draw_config_rect_layer(odraw, rect->layer, OSD_RECT_STATE_ENABLE, rect->style); - - return SUCCESS; -} - -/****************************************************************************** - * @brief Draw a specific rectangle with OSD draw HW IP on the top if possible. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * @param rect: pointer to a rectangle setting structure. - * @param layer: pointer to return the current drawing layer. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_rectangle_onTop(osd_draw_reg_t *odraw, osd_rectangle_t *rect, uint32_t *layer) -{ - uint32_t tmpval = 0; - uint32_t draw_layer = 0; - - CHECK_PARAM(NULL != layer); - CHECK_PARAM(NULL != rect); - - tmpval = odraw->osd_draw_config.WORD; - tmpval &= 0x0000FFFF; - - tmpval = __CLZ(tmpval); - - if (OSD_MAX_LAYER == tmpval) { - /* no available TOP layer since all layers used */ - *layer = (uint32_t)-1; - return NORESC; - } - - draw_layer = sizeof(uintptr_t) * 8 - tmpval; - - rect->layer = draw_layer; - *layer = draw_layer; - osd_draw_rectangle(odraw, rect); - - return SUCCESS; -} - -/****************************************************************************** - * @brief Init the OSD draw HW IP. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_init(osd_draw_reg_t *odraw) -{ - odraw->osd_draw_config.WORD = 0; - return SUCCESS; -} - -/****************************************************************************** - * @brief DeInit the OSD draw HW IP. - * - * @param odraw: pointer to a specific OSD draw HW IP. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_draw_deinit(osd_draw_reg_t *odraw) -{ - odraw->osd_draw_config.WORD = 0; - return SUCCESS; -} - -/*@} end of group OSD_DRAW_Public_Functions */ - -/*@} end of group OSD_DRAW */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c deleted file mode 100644 index ecf59a9814..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_osd_probe.c +++ /dev/null @@ -1,245 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_osd_probe.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_osd_probe.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup OSD_PROBE - * @{ - */ - -/** @defgroup OSD_PROBE_Private_Macros - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Macros */ - -/** @defgroup OSD_PROBE_Private_Types - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Types */ - -/** @defgroup OSD_PROBE_Private_Variables - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Variables */ - -/** @defgroup OSD_PROBE_Global_Variables - * @{ - */ - -/*@} end of group OSD_PROBE_Global_Variables */ - -/** @defgroup OSD_PROBE_Private_Fun_Declaration - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Fun_Declaration */ - -/** @defgroup OSD_PROBE_Private_Functions - * @{ - */ - -/*@} end of group OSD_PROBE_Private_Functions */ - -/** @defgroup OSD_PROBE_Public_Functions - * @{ - */ - -/****************************************************************************** - * @brief OSD probe setup one detect point - * - * @param index: point index in probe. - * @param x: point x-axis. - * @param y: point y-axis. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_set_addr(uintptr_t index, uintptr_t x, uintptr_t y) -{ - uint32_t addr = 0; - - addr = ((y << OSD_PB_REG_OSD_PB_Y_00_POS) & OSD_PB_REG_OSD_PB_Y_00_MSK) | (x & OSD_PB_REG_OSD_PB_X_00_MSK); - - if (index < OSD_PROBE_ADDR_MAX_INDEX) { - BL_WR_WORD(OSD_PROBE_BASE + OSD_PB_ADDR_00_OFFSET + index * sizeof(uint32_t), addr); - return SUCCESS; - } else { - return INVALID; - } -} - -/****************************************************************************** - * @brief OSD probe get info of one detect point - * - * @param index: point index in probe. - * @param x: return the value of point x-axis. - * @param y: return the value of point y-axis. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_addr(uintptr_t index, uintptr_t *x, uintptr_t *y) -{ - uint32_t addr = 0; - BL_Err_Type err = INVALID; - - CHECK_PARAM(NULL != x); - CHECK_PARAM(NULL != y); - - if (index < OSD_PROBE_ADDR_MAX_INDEX) { - addr = BL_RD_WORD(OSD_PROBE_BASE + OSD_PB_ADDR_00_OFFSET + index * sizeof(uint32_t)); - *x = addr & OSD_PB_REG_OSD_PB_X_00_MSK; - *y = (addr & OSD_PB_REG_OSD_PB_Y_00_MSK) >> OSD_PB_REG_OSD_PB_Y_00_POS; - err = SUCCESS; - } - - return err; -} - -/****************************************************************************** - * @brief OSD probe get result count info - * - * @param cnt: return the count info of the probe result. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_count(uintptr_t *cnt) -{ - CHECK_PARAM(NULL != cnt); - - *cnt = BL_GET_REG_BITS_VAL(BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG), OSD_PB_STS_OSD_PB_W_CNT_R); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe get result - * - * @param res: return the probe result. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_result(uintptr_t *res) -{ - uint32_t ctrl = 0; - - CHECK_PARAM(NULL != res); - - ctrl = BL_GET_REG_BITS_VAL(BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG), OSD_PB_STS_OSD_PB_IDX_R); - - *res = ctrl ? BL_RD_REG(OSD_PROBE_BASE, OSD_PB_RESULT0) : BL_RD_REG(OSD_PROBE_BASE, OSD_PB_RESULT1); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe get ctrl reg - * - * @param ctrl: return the value of the ctrl reg. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_ctrl(uintptr_t *ctrl) -{ - CHECK_PARAM(NULL != ctrl); - - *ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe set Y channel threshold. - * - * @param luma: value of the Y threshold. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_set_threshold(uintptr_t luma) -{ - uint32_t ctrl = 0; - - ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG); - ctrl &= ~OSD_PB_REG_OSD_PB_LUMA_TH_MSK; - ctrl |= (luma & OSD_PB_REG_OSD_PB_LUMA_TH_MSK); - BL_WR_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG, ctrl); - - return SUCCESS; -} - -/****************************************************************************** - * @brief OSD probe get Y channel threshold. - * - * @param luma: return value of the Y threshold in reg. - * - * @return Result of the operation. - * -*******************************************************************************/ - -BL_Err_Type osd_probe_get_threshold(uintptr_t *luma) -{ - uint32_t ctrl = 0; - - CHECK_PARAM(NULL != luma); - - ctrl = BL_RD_REG(OSD_PROBE_BASE, OSD_PB_CTRL_REG); - *luma = ctrl & OSD_PB_REG_OSD_PB_LUMA_TH_MSK; - - return SUCCESS; -} - -/*@} end of group OSD_PROBE_Public_Functions */ - -/*@} end of group OSD_PROBE */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c deleted file mode 100644 index fd9451c627..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pwm.c +++ /dev/null @@ -1,1247 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_pwm.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_pwm.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup PWM - * @{ - */ - -/** @defgroup PWM_Private_Macros - * @{ - */ -#define PWMx_Get_Reg_Addr(id) (PWM_BASE + PWM_CHANNEL_OFFSET + (id)*0x40) -#define PWM_INT_TIMEOUT_COUNT (320 * 1000) -#define PWM_STOP_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group PWM_Private_Macros */ - -/** @defgroup PWM_Private_Types - * @{ - */ - -/*@} end of group PWM_Private_Types */ - -/** @defgroup PWM_Private_Variables - * @{ - */ - -/** - * @brief PWM interrupt callback function address array -*/ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *PWMIntCbfArra[PWMx_ID_MAX][PWM_INT_ALL] = { { NULL } }; -#endif -/*@} end of group PWM_Private_Variables */ - -/** @defgroup PWM_Global_Variables - * @{ - */ - -/*@} end of group PWM_Global_Variables */ - -/** @defgroup PWM_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph); -#endif - -/*@} end of group PWM_Private_Fun_Declaration */ - -/** @defgroup PWM_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief PWM interrupt handle - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static BL_Err_Type PWM_IntHandler(IRQn_Type intPeriph) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t PWMx; - uint16_t intIndex; - PWMx_ID_Type id; - - for (id = PWM0_ID; id < PWMx_ID_MAX; id++) { - /* Get PWMx start register address */ - PWMx = PWMx_Get_Reg_Addr(id); - tmpVal = BL_RD_REG(PWMx, PWM_INT_STS); - maskVal = BL_RD_REG(PWMx, PWM_INT_MASK); - for (intIndex = 0; intIndex < PWM_INT_ALL; intIndex++) { - if (((1 << intIndex) & tmpVal) && (((1 << intIndex) & maskVal) == 0)) { - if (intIndex == PWM_INT_REPT) { - if (BL_GET_REG_BITS_VAL(BL_RD_REG(PWMx, PWM_CONFIG0), PWM_STOP_ON_REPT) == 1) { - PWMx_Disable(id); - } - } - BL_WR_REG(PWMx, PWM_INT_CLEAR, 1 << intIndex); - if (PWMIntCbfArra[id][intIndex] != NULL) { - PWMIntCbfArra[id][intIndex](); - } - } - } - } - return SUCCESS; -} - -#endif - -/*@} end of group PWM_Private_Functions */ - -/** @defgroup PWM_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief PWMx init - * - * @param id: PWM ID - * @param chCfg: PWMx configuration - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type PWMx_Init(PWMx_ID_Type id, PWMx_CFG_Type *cfg) -{ - uint32_t tmpVal; - uint32_t timeoutCnt = PWM_STOP_TIMEOUT_COUNT; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CLK_TYPE(cfg->clk)); - CHECK_PARAM(IS_PWM_STOP_MODE_TYPE(cfg->stopMode)); - CHECK_PARAM(IS_PWM_EXT_BREAK_POLARITY_TYPE(cfg->extPol)); - CHECK_PARAM(IS_PWM_TRIGADC_SOURCE_TYPE(cfg->adcSrc)); - - /* Ungate pwm clock gate */ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_PWM); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - BL_WR_REG(PWMx, PWM_CONFIG0, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); - while (!BL_IS_REG_BIT_SET(BL_RD_REG(PWMx, PWM_CONFIG0), PWM_STS_STOP)) { - timeoutCnt--; - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL, cfg->clk); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_MODE, cfg->stopMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_EXT_BREAK_PL, cfg->extPol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_ADC_TRG_SRC, cfg->adcSrc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_STOP_ON_REPT, cfg->stpRept); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CLK_DIV, cfg->clkDiv); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); - - /* Config pwm period and rept count */ - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_PERIOD, cfg->period); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_INT_PERIOD_CNT, cfg->intPulseCnt); - BL_WR_REG(PWMx, PWM_PERIOD, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(PWM_IRQn, PWM_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief PWMx update clock divider - * - * @param id: PWM ID - * @param div: Clock divider - * - * @return None - * -*******************************************************************************/ -void PWMx_Div_Set(PWMx_ID_Type id, uint16_t div) -{ - uint32_t tmpVal; - //* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CLK_DIV, div); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -/****************************************************************************/ /** - * @brief PWMx update period - * - * @param id: PWM ID - * @param period: period - * - * @return None - * -*******************************************************************************/ -void PWMx_Period_Set(PWMx_ID_Type id, uint16_t period) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm period and duty */ - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_PERIOD, period); - BL_WR_REG(PWMx, PWM_PERIOD, tmpVal); -} - -/****************************************************************************/ /** - * @brief PWMx get configuration - * - * @param id: PWM ID - * @param period: period pointer - * - * @return None - * -*******************************************************************************/ -void PWMx_Period_Get(PWMx_ID_Type id, uint16_t *period) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* get pwm period */ - tmpVal = BL_RD_REG(PWMx, PWM_PERIOD); - *period = BL_GET_REG_BITS_VAL(tmpVal, PWM_PERIOD); -} - -/****************************************************************************/ /** - * @brief PWMx enable - * - * @param id: PWMx ID - * - * @return None - * -*******************************************************************************/ -void PWMx_Enable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm clock to enable pwm */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - BL_WR_REG(PWMx, PWM_CONFIG0, BL_CLR_REG_BIT(tmpVal, PWM_STOP_EN)); -} - -/****************************************************************************/ /** - * @brief PWMx disable - * - * @param id: PWMx ID - * - * @return None - * -*******************************************************************************/ -void PWMx_Disable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - - /* Config pwm clock to disable pwm */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - BL_WR_REG(PWMx, PWM_CONFIG0, BL_SET_REG_BIT(tmpVal, PWM_STOP_EN)); -} - -void PWM_Channelx_Init(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_CHx_CFG_Type *cfg) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(cfg->modP)); - CHECK_PARAM(IS_PWM_MODE_TYPE(cfg->modN)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(cfg->polP)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(cfg->polN)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(cfg->idlP)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(cfg->idlN)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(cfg->brkP)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(cfg->brkN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, cfg->brkN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, cfg->brkN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, cfg->brkN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, cfg->modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, cfg->modN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, cfg->polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, cfg->polN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, cfg->idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, cfg->idlN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, cfg->brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, cfg->brkN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); - - /* Config pwm thresholdL and thresholdH */ - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, cfg->thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, cfg->thresholdH); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } - - /* Config pwm dead time */ - tmpVal = BL_RD_REG(PWMx, PWM_DEAD_TIME); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_DTG, cfg->dtg); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_DTG, cfg->dtg); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_DTG, cfg->dtg); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_DTG, cfg->dtg); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_DEAD_TIME, tmpVal); -} - -void PWM_Channelx_Threshold_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL, uint16_t thresholdH) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, thresholdL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } -} - -void PWM_Channelx_ThresholdL_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdL) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL, thresholdL); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } -} - -void PWM_Channelx_ThresholdH_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t thresholdH) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH0_THRE, tmpVal); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH1_THRE, tmpVal); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH2_THRE, tmpVal); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH, thresholdH); - BL_WR_REG(PWMx, PWM_CH3_THRE, tmpVal); - break; - default: - break; - } -} - -void PWM_Channelx_Threshold_Get(PWMx_ID_Type id, PWM_CHx_Type ch, uint16_t *thresholdL, uint16_t *thresholdH) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - /* get pwm thresholdL and thresholdH */ - switch (ch) { - case PWM_CH0: - tmpVal = BL_RD_REG(PWMx, PWM_CH0_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH0_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH0_THREH); - break; - case PWM_CH1: - tmpVal = BL_RD_REG(PWMx, PWM_CH1_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH1_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH1_THREH); - break; - case PWM_CH2: - tmpVal = BL_RD_REG(PWMx, PWM_CH2_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH2_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH2_THREH); - break; - case PWM_CH3: - tmpVal = BL_RD_REG(PWMx, PWM_CH3_THRE); - *thresholdL = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH3_THREL); - *thresholdH = BL_GET_REG_BITS_VAL(tmpVal, PWM_CH3_THREH); - break; - default: - break; - } -} - -void PWM_Channelx_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type modP, PWM_Mode_Type modN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(modP)); - CHECK_PARAM(IS_PWM_MODE_TYPE(modN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, modN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, modN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, modN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, modP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, modN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} -void PWM_Channelx_Positive_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(mod)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PEN, mod); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PEN, mod); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PEN, mod); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PEN, mod); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} -void PWM_Channelx_Negative_Pwm_Mode_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Mode_Type mod) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_MODE_TYPE(mod)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NEN, mod); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NEN, mod); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NEN, mod); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NEN, mod); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type polP, PWM_Polarity_Type polN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(polP)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(polN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, polN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, polN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, polN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, polP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, polN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Positive_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(pol)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PPL, pol); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PPL, pol); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PPL, pol); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PPL, pol); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Negative_Polarity_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Polarity_Type pol) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_POLARITY_TYPE(pol)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NPL, pol); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NPL, pol); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NPL, pol); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NPL, pol); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idlP, PWM_Idle_State_Type idlN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idlP)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idlN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, idlN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, idlN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, idlN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, idlP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, idlN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Positive_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idl)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PSI, idl); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PSI, idl); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PSI, idl); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PSI, idl); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Negative_Idle_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Idle_State_Type idl) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_IDLE_STATE_TYPE(idl)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NSI, idl); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NSI, idl); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NSI, idl); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NSI, idl); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brkP, PWM_Break_State_Type brkN) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brkP)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brkN)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, brkN); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, brkN); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, brkN); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, brkP); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, brkN); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Positive_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brk)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_PBS, brk); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_PBS, brk); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_PBS, brk); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_PBS, brk); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Channelx_Negative_Break_State_Set(PWMx_ID_Type id, PWM_CHx_Type ch, PWM_Break_State_Type brk) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - CHECK_PARAM(IS_PWM_BREAK_STATE_TYPE(brk)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG1); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_NBS, brk); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_NBS, brk); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_NBS, brk); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_NBS, brk); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_CONFIG1, tmpVal); -} - -void PWM_Config1_Set(PWMx_ID_Type id, uint32_t cfg) -{ - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm config1 */ - BL_WR_REG(PWMx, PWM_CONFIG1, cfg); -} - -void PWM_Config1_Get(PWMx_ID_Type id, uint32_t *cfg) -{ - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Get pwm config1 value */ - *cfg = BL_RD_REG(PWMx, PWM_CONFIG1); -} - -void PWM_Channelx_Dtg_Set(PWMx_ID_Type id, PWM_CHx_Type ch, uint8_t dtg) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_CHx_TYPE(ch)); - - /* Config pwm config1 */ - tmpVal = BL_RD_REG(PWMx, PWM_DEAD_TIME); - switch (ch) { - case PWM_CH0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH0_DTG, dtg); - break; - case PWM_CH1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH1_DTG, dtg); - break; - case PWM_CH2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH2_DTG, dtg); - break; - case PWM_CH3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_CH3_DTG, dtg); - break; - default: - break; - } - BL_WR_REG(PWMx, PWM_DEAD_TIME, tmpVal); -} - -void PWM_SW_Break_Enable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BIT(tmpVal, PWM_SW_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_SW_Break_Disable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, PWM_SW_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_EXT_Break_Enable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BIT(tmpVal, PWM_EXT_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_EXT_Break_Disable(PWMx_ID_Type id) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_CLR_REG_BIT(tmpVal, PWM_EXT_BREAK_EN); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_EXT_Break_Polarity_Set(PWMx_ID_Type id, PWM_EXT_Break_Polarity_Type pol) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_EXT_BREAK_POLARITY_TYPE(pol)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_EXT_BREAK_PL, pol); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -void PWM_TrigADC_Source_Set(PWMx_ID_Type id, PWM_TrigADC_Source_Type src) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_TRIGADC_SOURCE_TYPE(src)); - - /* Config pwm config0 */ - tmpVal = BL_RD_REG(PWMx, PWM_CONFIG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PWM_ADC_TRG_SRC, src); - BL_WR_REG(PWMx, PWM_CONFIG0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Mask/Unmask the PWM interrupt - * - * @param id: PWM ID - * @param intType: Specifies the interrupt type - * @param intMask: Enable/Disable Specified interrupt type - * - * @return None - * -*******************************************************************************/ -void PWM_Int_Mask(PWMx_ID_Type id, PWM_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PWMx, PWM_INT_MASK); - if (intType == PWM_INT_ALL) { - if (intMask == UNMASK) { - tmpVal &= ~((1U << PWM_INT_ALL) - 1); - } else { - tmpVal |= ((1U << PWM_INT_ALL) - 1); - } - } else { - if (intMask == UNMASK) { - tmpVal &= ~(1U << intType); - } else { - tmpVal |= (1U << intType); - } - } - BL_WR_REG(PWMx, PWM_INT_MASK, tmpVal); -} - -void PWM_Int_Clear(PWMx_ID_Type id, PWM_INT_Type intType) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWMx_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PWMx, PWM_INT_CLEAR); - - if (intType == PWM_INT_ALL) { - tmpVal = ((1U << PWM_INT_ALL) - 1); - } else { - tmpVal = (1U << intType); - } - BL_WR_REG(PWMx, PWM_INT_CLEAR, tmpVal); -} - -BL_Sts_Type PWM_Int_Status_Get(PWMx_ID_Type id, PWM_INT_Type intType) -{ - uint32_t tmpVal; - /* Get PWMx start register address */ - uint32_t PWMx = PWMx_Get_Reg_Addr(id); - - /* Check the parameters */ - CHECK_PARAM(IS_PWM_CH_ID_TYPE(id)); - CHECK_PARAM(IS_PWM_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PWMx, PWM_INT_STS); - - if (intType == PWM_INT_ALL) { - if (tmpVal & ((1 << PWM_CHx_MAX) - 1)) { - return SET; - } else { - return RESET; - } - } else { - if (tmpVal & (1 << intType)) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Install PWM interrupt callback function - * - * @param id: PWM ID - * @param intType: PWM interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void PWM_Int_Callback_Install(PWMx_ID_Type id, uint32_t intType, intCallback_Type *cbFun) -{ - PWMIntCbfArra[id][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief PWM interrupt function - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void PWM_IRQHandler(void) -{ - PWM_IntHandler(PWM_IRQn); -} -#endif - -/*@} end of group PWM_Public_Functions */ - -/*@} end of group PWM */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c deleted file mode 100644 index 84af0f57ec..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_patch.c +++ /dev/null @@ -1,3092 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_romapi_patch.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2021 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_romapi_patch.h" -#include "bl808_romdriver_e907.h" -#error "Not using romndriver now" - -/* WiFi PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 0, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 0, /*!< pll_icp_1u */ - .clkpllIcp5u = 2, /*!< pll_icp_5u */ - .clkpllRz = 3, /*!< pll_rz */ - .clkpllCz = 1, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 1, /*!< pll_r4_short */ - .clkpllC4En = 0, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 1, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 1, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &wifiPllBasicCfg_24M, 0x1400000 }, /*!< XTAL is 24M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is 32M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000 }, /*!< XTAL is 38.4M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000 }, /*!< XTAL is 40M */ - { &wifiPllBasicCfg_26M, 0x1276276 }, /*!< XTAL is 26M */ - { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000 }, /*!< XTAL is RC32M */ -}; - -/* Audio PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_442P368M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x126E9 }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x170A3 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x161E5 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x1103A }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1BA5E }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P584M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &audioPllBasicCfg_24M_26M, 0x12D0E }, /*!< XTAL is 24M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is 32M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x17851 }, /*!< XTAL is 38.4M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x16944 }, /*!< XTAL is 40M */ - { &audioPllBasicCfg_24M_26M, 0x115E5 }, /*!< XTAL is 26M */ - { &audioPllBasicCfg_32M_38P4M_40M, 0x1C395 }, /*!< XTAL is RC32M */ -}; - -/* CPU PLL Config*/ -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_24M_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION cpuPllBasicCfg_32M_38P4M_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllIntFracSw = 1, /*!< pll_int_frac_sw */ - .clkpllIcp1u = 1, /*!< pll_icp_1u */ - .clkpllIcp5u = 0, /*!< pll_icp_5u */ - .clkpllRz = 5, /*!< pll_rz */ - .clkpllCz = 2, /*!< pll_cz */ - .clkpllC3 = 2, /*!< pll_c3 */ - .clkpllR4Short = 0, /*!< pll_r4_short */ - .clkpllC4En = 1, /*!< pll_r4_en */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllSdmCtrlHw = 0, /*!< pll_sdm_ctrl_hw */ - .clkpllSdmBypass = 0, /*!< pll_sdm_bypass */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_380M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0xFD55 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13CAA }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x13000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xE9D8 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x17C00 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x10AAA }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x14000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0xF627 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */ -}; -const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &cpuPllBasicCfg_24M_26M, 0x14000 }, /*!< XTAL is 24M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is 32M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is 38.4M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x18000 }, /*!< XTAL is 40M */ - { &cpuPllBasicCfg_24M_26M, 0x12762 }, /*!< XTAL is 26M */ - { &cpuPllBasicCfg_32M_38P4M_40M, 0x1E000 }, /*!< XTAL is RC32M */ -}; - -/* MIPI PLL Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION mipiPllBasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 0, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 0, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &mipiPllBasicCfg_24M, 0x3E800 }, /*!< XTAL is 24M */ - { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is 32M */ - { &mipiPllBasicCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */ - { &mipiPllBasicCfg_40M, 0x38400 }, /*!< XTAL is 40M */ - { &mipiPllBasicCfg_26M, 0x39B13 }, /*!< XTAL is 26M */ - { &mipiPllBasicCfg_32M, 0x46500 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2100 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2100BasicCfg_24M, 0x2BC00 }, /*!< XTAL is 24M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is 32M */ - { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */ - { &uhsPll2100BasicCfg_40M, 0x34800 }, /*!< XTAL is 40M */ - { &uhsPll2100BasicCfg_26M, 0x28627 }, /*!< XTAL is 26M */ - { &uhsPll2100BasicCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 4, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1400MCfg_24M, 0x3A555 }, /*!< XTAL is 24M */ - { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is 32M */ - { &uhsPll1400MCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */ - { &uhsPll1400MCfg_40M, 0x34800 }, /*!< XTAL is 40M */ - { &uhsPll1400MCfg_26M, 0x35D89 }, /*!< XTAL is 26M */ - { &uhsPll1400MCfg_32M, 0x41A00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1500 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1500MCfg_24M, 0x3E800 }, /*!< XTAL is 24M */ - { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is 32M */ - { &uhsPll1500MCfg_38P4M, 0x3A980 }, /*!< XTAL is 38.4M */ - { &uhsPll1500MCfg_40M, 0x38400 }, /*!< XTAL is 40M */ - { &uhsPll1500MCfg_26M, 0x39B13 }, /*!< XTAL is 26M */ - { &uhsPll1500MCfg_32M, 0x46500 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1600 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 5, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1600BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is 32M */ - { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */ - { &uhsPll1600BasicCfg_40M, 0x28000 }, /*!< XTAL is 40M */ - { &uhsPll1600BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ - { &uhsPll1600BasicCfg_32M, 0x32000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 400 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll400BasicCfg_24M, 0x19000 }, /*!< XTAL is 24M */ - { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is 32M */ - { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */ - { &uhsPll400BasicCfg_40M, 0x14000 }, /*!< XTAL is 40M */ - { &uhsPll400BasicCfg_26M, 0x1713B }, /*!< XTAL is 26M */ - { &uhsPll400BasicCfg_32M, 0x19000 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 667 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = { - .clkpllRefdivRatio = 4, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 1, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll667BasicCfg_24M, 0x29B00 }, /*!< XTAL is 24M */ - { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is 32M */ - { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */ - { &uhsPll667BasicCfg_40M, 0x21599 }, /*!< XTAL is 40M */ - { &uhsPll667BasicCfg_26M, 0x267B1 }, /*!< XTAL is 26M */ - { &uhsPll667BasicCfg_32M, 0x29B00 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 800 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 2, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll800BasicCfg_24M, 0x21555 }, /*!< XTAL is 24M */ - { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is 32M */ - { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */ - { &uhsPll800BasicCfg_40M, 0x1E000 }, /*!< XTAL is 40M */ - { &uhsPll800BasicCfg_26M, 0x1EC4E }, /*!< XTAL is 26M */ - { &uhsPll800BasicCfg_32M, 0x25800 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 1066 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = { - .clkpllRefdivRatio = 3, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 3, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll1066BasicCfg_24M, 0x2C6AA }, /*!< XTAL is 24M */ - { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is 32M */ - { &uhsPll1066BasicCfg_38P4M, 0x29A40 }, /*!< XTAL is 38.4M */ - { &uhsPll1066BasicCfg_40M, 0x27F99 }, /*!< XTAL is 40M */ - { &uhsPll1066BasicCfg_26M, 0x29000 }, /*!< XTAL is 26M */ - { &uhsPll1066BasicCfg_32M, 0x31F80 }, /*!< XTAL is RC32M */ -}; - -/* uhs PLL 2000 Config*/ -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = { - .clkpllRefdivRatio = 2, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */ -}; -const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPll2000BasicCfg_24M, 0x29AAA }, /*!< XTAL is 24M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is 32M */ - { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */ - { &uhsPll2000BasicCfg_40M, 0x32000 }, /*!< XTAL is 40M */ - { &uhsPll2000BasicCfg_26M, 0x26762 }, /*!< XTAL is 26M */ - { &uhsPll2000BasicCfg_32M, 0x3E800 }, /*!< XTAL is RC32M */ -}; - -static intCallback_Type *uartIntCbfArra[UART_ID_MAX][UART_INT_ALL] = { - { NULL } -}; -#ifndef BFLB_USE_HAL_DRIVER -static const uint32_t uartAddr[UART_ID_MAX] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE }; - -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; -#endif - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_LQ64E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JW = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xf0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_XM25QH16={ - .resetCreadCmd=0xff, - .resetCreadCmdSize=3, - .mid=0x20, - - .deBurstWrapCmd=0x77, - .deBurstWrapCmdDmyClk=0x3, - .deBurstWrapDataMode=SF_CTRL_DATA_4_LINES, - .deBurstWrapData=0xF0, - - /*reg*/ - .writeEnableCmd=0x06, - .wrEnableIndex=0x00, - .wrEnableBit=0x01, - .wrEnableReadRegLen=0x01, - - .qeIndex=1, - .qeBit=0x01, - .qeWriteRegLen=0x01, - .qeReadRegLen=0x1, - - .busyIndex=0, - .busyBit=0x00, - .busyReadRegLen=0x1, - .releasePowerDown=0xab, - - .readRegCmd[0]=0x05, - .readRegCmd[1]=0x35, - .writeRegCmd[0]=0x01, - .writeRegCmd[1]=0x31, - - .fastReadQioCmd=0xeb, - .frQioDmyClk=16/8, - .cReadSupport=1, - .cReadMode=0x20, - - .burstWrapCmd=0x77, - .burstWrapCmdDmyClk=0x3, - .burstWrapDataMode=SF_CTRL_DATA_4_LINES, - .burstWrapData=0x40, - /*erase*/ - .chipEraseCmd=0xc7, - .sectorEraseCmd=0x20, - .blk32EraseCmd=0x52, - .blk64EraseCmd=0xd8, - /*write*/ - .pageProgramCmd=0x02, - .qpageProgramCmd=0x32, - .qppAddrMode=SF_CTRL_ADDR_1_LINE, - - .ioMode=SF_CTRL_QIO_MODE, - .clkDelay=1, - .clkInvert=0x01, - - .resetEnCmd=0x66, - .resetCmd=0x99, - .cRExit=0xff, - .wrEnableWriteRegLen=0x00, - - /*id*/ - .jedecIdCmd=0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd=0x0b, - .frDmyClk=8/8, - .qpiFastReadCmd =0x0b, - .qpiFrDmyClk=8/8, - .fastReadDoCmd=0x3b, - .frDoDmyClk=8/8, - .fastReadDioCmd=0xbb, - .frDioDmyClk=0, - .fastReadQoCmd=0x6b, - .frQoDmyClk=8/8, - - .qpiFastReadQioCmd=0xeb, - .qpiFrQioDmyClk=16/8, - .qpiPageProgramCmd=0x02, - .writeVregEnableCmd=0x50, - - /* qpi mode */ - .enterQpi=0x38, - .exitQpi=0xff, - - /*AC*/ - .timeEsector=400, - .timeE32k=1600, - .timeE64k=2000, - .timePagePgm=5, - .timeCe=33000, - .pdDelay=3, - .qeData=0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x24, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x15, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = (SF_CTRL_QIO_MODE | 0x20), - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_GD_LQ64E, - }, - { - .jedecID = 0x1760ef, - //.name="WB_64JW_64_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID=0x144020, - //.name="XM_25QH80_80_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID=0x154020, - //.name="XM_25QH16_16_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID=0x164020, - //.name="XM_25QH32_32_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID=0x174020, - //.name="XM_25QH64_64_33", - .cfg=&flashCfg_XM25QH16, - }, - { - .jedecID = 0x17400B, - //.name="XT_25F64B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1570ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1940ef, - //.name="Winb_256FV_128_33", - .cfg = &flashCfg_Winb_256FV, - }, - { - .jedecID = 0x1860c8, - //.name="GD_LQ128E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x15345e, - //.name="ZB_WQ16A_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15405e, - //.name="ZB_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x16405e, - //.name="ZB_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x17405e, - //.name="ZB_Q64B_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15605E, - //.name="ZB_VQ16", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x3925C2, - //.name="MX_25U256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID = 0x1740c8, - //.name="GD_Q64E_64_18", - .cfg = &flashCfg_XM25QH16, - } -}; - -static void UART_IntHandler(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - maskVal = BL_RD_REG(UARTx, UART_INT_MASK); - - /* Length of uart tx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_UTX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_END](); - } - } - - /* Length of uart rx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_END](); - } - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ](); - } - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ](); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_RTO_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) { - uartIntCbfArra[uartId][UART_INT_RTO](); - } - } - - /* Rx parity check error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_PCE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) { - uartIntCbfArra[uartId][UART_INT_PCE](); - } - } - - /* Tx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FER](); - } - } - - /* Rx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FER](); - } - } - - /* Rx lin mode sync field error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_LSE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) { - uartIntCbfArra[uartId][UART_INT_LSE](); - } - } - - /* Rx byte count reached interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_BCR_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_BCR_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_BCR_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_BCR] != NULL) { - uartIntCbfArra[uartId][UART_INT_BCR](); - } - } - - /* Rx auto baud rate detection finish interrupt using start bit */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_ADS_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_ADS_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_ADS_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_STARTBIT] != NULL) { - uartIntCbfArra[uartId][UART_INT_STARTBIT](); - } - } - - /* Rx auto baud rate detection finish interrupt using codeword 0x55 */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_AD5_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_AD5_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_AD5_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_0X55] != NULL) { - uartIntCbfArra[uartId][UART_INT_0X55](); - } - } -} - -void UART1_IRQHandler(void) -{ - UART_IntHandler(UART1_ID); -} - -void UART0_IRQHandler(void) -{ - UART_IntHandler(UART0_ID); -} - -#endif - -/****************************************************************************/ /** - * @brief Install uart interrupt callback function - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - uartIntCbfArra[uartId][intType] = cbFun; - - return SUCCESS; -} -//CLOCK -//EFUSE -//PDS -/****************************************************************************/ /** - * @brief PDS turn on USB - * - * @param waitReady : wait turn on usb finish - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady) -{ - uint32_t tmpVal = 0; - - /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0 */ - /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */ - /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1 */ - /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0 */ - /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1 */ - /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1 */ - /* #1.2ms; wait UCLK */ - /* wait(soc616_b0.usb_uclk); */ - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0); - BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW); - BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST); - BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal); - - /* greater than 5T */ - arch_delay_us(1); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N); - BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal); - - /* greater than 5T */ - arch_delay_us(1); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N); - BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal); - - /* wait UCLK 1.2ms */ - arch_delay_ms(3); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N); - BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal); - - if (waitReady) { - arch_delay_ms(2); - } - - return SUCCESS; -} - -//HBN - -/****************************************************************************/ /** - * @brief Power on XTAL 32K - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); - BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); - - /* Delay >1s */ - arch_delay_us(1100); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Power off XTAL 32K - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF); - BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal); - - return SUCCESS; -} - -/** - * @brief Power Off RC32K in all state - * - * @return BL_Err_Type - */ -BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_All_State(void) -{ - int32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2); - tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K); - BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal); - HBN_Power_Off_RC32K(); - return SUCCESS; -} - -/** - * @brief Power Off RC32K In power off state - * - * @return BL_Err_Type - */ -BL_Err_Type ATTR_CLOCK_SECTION HBN_PD_RC32K_In_Poff(void) -{ - int32_t tmpVal = 0; - - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL2); - tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_RC32K); - BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL2, tmpVal); - HBN_Power_Off_RC32K(); - return SUCCESS; -} - -/**************************************************************************** - * @brief HBN set ldo11_Rtc voltage out - * - * @param ldoLevel: LDO11_Rtc volatge level - * 0:0.60V 1:0.65V 2:0.70V 3:0.75V - * 4:0.80V 5:0.85V 6:0.9V 7:0.95V - * 8:1.0V 9:1.05V 10:1.1V 11:1.15V, - * 12:1.2V 13:1.25V 14:1.3V 15:1.35V - * - * @return SUCCESS or ERROR - * - *******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel) -{ - HBN_RTC_MISC_Type rtcMiscCfg; - - CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); - - HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg); - rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel; - HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN set ldo11 all voltage out, not include dcdc11 - * - * @param ldoLevel: LDO volatge level - * - * @return SUCCESS or ERROR - * - * @note not support LDO11_Rtc 0.65v & 0.6v -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel) -{ - uint32_t tmpVal; - HBN_RTC_MISC_Type rtcMiscCfg; - - CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel); - BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal); - - HBN_Get_RTC_Misc_Cfg(&rtcMiscCfg); - rtcMiscCfg.ldo11RtcVoutSelRtc = ldoLevel; - HBN_Set_RTC_Misc_Cfg(&rtcMiscCfg); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get RTC misc config - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t *pCfg = (uint32_t *)cfg; - - if (!cfg) { - return ERROR; - } - - /* read [31:19] */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC); - - /* use [30:19] */ - *pCfg = tmpVal; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set RTC misc config - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg) -{ - uint32_t tmpVal = 0; - - if (!cfg) { - return ERROR; - } - - /* read [31:19] */ - tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_RST_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_RST_CTRL_MISC, ((*(uint32_t *)cfg)<<1)); - BL_WR_REG(HBN_BASE, HBN_RTC_RST_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN enable ACOMP0 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); - tmpVal2 = tmpVal2 | (1 << edge); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN disable ACOMP0 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN); - tmpVal2 = tmpVal2 & (~(1 << edge)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN enable ACOMP1 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); - tmpVal2 = tmpVal2 | (1 << edge); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief HBN disable ACOMP1 interrupt - * - * @param edge: HBN acomp interrupt edge type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge) -{ - uint32_t tmpVal; - uint32_t tmpVal2; - - CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge)); - - tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE); - tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN); - tmpVal2 = tmpVal2 & (~(1 << edge)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2); - BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal); - - return SUCCESS; -} - -//AON -/****************************************************************************/ /** - * @brief AON set DCDC11_Top voltage out - * - * @param dcdcLevel: DCDC11_Top volatge level - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel) -{ - uint32_t tmpVal; - - CHECK_PARAM(IS_AON_DCDC_LEVEL_TYPE(dcdcLevel)); - - tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC11_VOUT_SEL_AON, dcdcLevel); - BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal); - - return SUCCESS; -} -/****************************************************************************/ /** - * @brief delay us - * - * @param[in] core: systemcoreclock - * - * @param[in] cnt: delay cnt us - * - * @return none - * - *******************************************************************************/ -void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT) -{ - volatile uint32_t divVal = loopT; - volatile uint32_t speed = 0; - volatile uint32_t cycNum = 0; - - /* 1M=100K*10, so multiple is 10 */ - /* loop function take 4 instructions, so instructionNum is 4 */ - /* divVal = multiple*instructionNum */ - - if (core >= 1 * 1000 * 1000) { - /* CPU clock >= 1MHz */ - speed = core / (100 * 1000); - cycNum = speed * cnt; - cycNum = cycNum / 10; - cycNum = cycNum / divVal; - /* cycNum >= 0 */ - } else { - /* CPU clock < 1MHz */ - speed = core / 1000; - cycNum = speed * cnt; - cycNum = cycNum / 1000; - cycNum = cycNum / divVal; - /* cycNum >= 0 */ - } - - if (!cycNum) { - return; - } - - __asm__ __volatile__( - "mv a4,%0\n\t" - "li a5,0x0\n\t" - "nop\n\t" - "nop\n\t" - "nop\n\t" - ".align 4\n\t" - "1 :\n" - "beq a5,a4,2f\n\t" - "addi a5,a5,0x1\n\t" - "lui a3,0xF0000\n\t" - "lw a3,0(a3)\n\t" - "j 1b\n\t" - "nop\n\t" - "nop\n\t" - "2 :\n\t" - "nop\n" - : /* output */ - : "r"(cycNum) /* input */ - : "a3", "a4", "a5" /* destruct description */ - ); -} - -/****************************************************************************/ /** - * @brief delay us - * - * @param[in] cnt: delay cnt us - * - * @return none - * - *******************************************************************************/ -void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt) -{ - GLB_CORE_ID_Type coreID; - uint32_t coreFreq; - uint32_t loopTick = 5; - uint32_t m0Cyc00[] = { 46, 46, 77, 85 }; - uint32_t m0Cyc10[] = { 10, 10, 77, 85 }; - uint32_t m0Cyc11[] = { 10, 10, 77, 85 }; - uint32_t d0Cyc00[] = { 5, 5, 62, 34 }; - uint32_t d0Cyc11[] = { 5, 5, 13, 13 }; - uint32_t lpCyc00[] = { 6, 6, 55, 85 }; - uint32_t *pCyc = NULL; - uint32_t iCacheEn = 1; - uint32_t dCacheEn = 1; - - /* requirement: icache enable && dcache enable */ - /* otherwise the latency depends on the code address */ - - coreID = GLB_Get_Core_Type(); - - if (GLB_CORE_ID_M0 == coreID) { - coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK); -#ifdef __RV32 - iCacheEn = (__get_MHCR() & CLIC_INTIE_IE_Msk) >> CLIC_INTIE_IE_Pos; - dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos; -#endif - if (iCacheEn && dCacheEn) { - pCyc = m0Cyc11; - } else if (iCacheEn && !dCacheEn) { - pCyc = m0Cyc10; - } else if (!iCacheEn && !dCacheEn) { - pCyc = m0Cyc00; - } else { - pCyc = m0Cyc11; - } - } else if (GLB_CORE_ID_D0 == coreID) { - coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_CLK); -#ifdef __RV64 - iCacheEn = (__get_MHCR() & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos; - dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos; -#endif - if (iCacheEn && dCacheEn) { - pCyc = d0Cyc11; - } else if (!iCacheEn && !dCacheEn) { - pCyc = d0Cyc00; - } else { - pCyc = d0Cyc11; - } - } else if (GLB_CORE_ID_LP == coreID) { - coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_LP_CLK); - pCyc = lpCyc00; - } else { - coreFreq = 32 * 1000 * 1000; - pCyc = lpCyc00; - } - - switch (((uint32_t)&ASM_Delay_Us) >> 24) { - case 0x22: - loopTick = pCyc[0]; - break; - case 0x62: - loopTick = pCyc[0]; - break; - case 0x3F: - loopTick = pCyc[2]; - break; - case 0x3E: - loopTick = pCyc[3]; - break; - default: - break; - } - - coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000); - - ASM_Delay_Us(coreFreq, cnt, loopTick); -} - -/****************************************************************************/ /** - * @brief delay ms - * - * @param[in] cnt: delay cnt ms - * - * @return none - * - *******************************************************************************/ -void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt) -{ - uint32_t i = 0; - uint32_t count = 0; - - if (cnt >= 1024) { - /* delay (n*1024) ms */ - for (i = 0; i < (cnt / 1024); i++) { - arch_delay_us(1024 * 1000); - } - } - - count = cnt & 0x3FF; - - if (count) { - /* delay (1-1023)ms */ - arch_delay_us(count * 1000); - } -} - -/****************************************************************************/ /** - * @brief chip clock out0 select - * - * @param clkOutType: chip clock out0 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out0 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out1 select - * - * @param clkOutType: chip clock out1 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out1 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out2 select - * - * @param clkOutType: chip clock out2 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out2 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief chip clock out3 select - * - * @param clkOutType: chip clock out3 output type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2); - /* set clk out3 output enable */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType); - BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal); - - return SUCCESS; -} - -//FLASH - -/****************************************************************************/ /** - * @brief GLB power on PLL - * - * @param pllType: PLL XTAL type - * @param cfg: GLB PLL configuration - * @param waitStable: wait PLL clock stable - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - /* unknown */ - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* Step1:config parameter */ - /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal); - - /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal); - - /* cfg4:Set aupll_sel_sample_clk */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal); - - /* cfg5:Set aupll_vco_speed */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - - /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal); - - /* Step2:config pu */ - /* cfg0 : pu_aupll_sfreg=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* cfg0 : pu_wifipll=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* delay > 2us */ - arch_delay_us(3); - - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal); - - /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */ - if (GLB_WAC_PLL_AUPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((cfg->clkpllSdmin == 0x12D0E) || (cfg->clkpllSdmin == 0x1C395) || (cfg->clkpllSdmin == 0x17851) || (cfg->clkpllSdmin == 0x16944) || (cfg->clkpllSdmin == 0x115E5)) { - /* 451.548 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14); - } else { - /* 442.368 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x12); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - } - - /* Step4:enable output clock */ - /* wifipll : cfg5, wifipll_vco_div3_en=1 */ - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_VCO_DIV3_EN); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal); - } - /* cfg8 : wifipll->wifipll_en_ctrl_hw=1 */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8); - if (GLB_WAC_PLL_WIFIPLL == pllType) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_EN_CTRL_HW, 1); - } - /* cfg8 : wifipll/aupll/cpupll clock enable */ - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8); - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10); - break; - case GLB_WAC_PLL_AUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6); - break; - case GLB_WAC_PLL_CPUPLL: - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV1); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV2P5); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV4); - tmpVal = BL_SET_REG_BIT(tmpVal, CCI_CPUPLL_EN_DIV5); - break; - default: - break; - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal); - - if (waitStable) { - /* Wait 1.5*30us */ - arch_delay_us(45); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB wifi audio cpu PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_WAC_PLL_WIFIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_AUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - case GLB_WAC_PLL_CPUPLL: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_CPU_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - if ((GLB_WAC_PLL_WIFIPLL == pllType) && (GLB_PLL_REFCLK_XTAL == refClk)) { - /* wifipll_refclk_sel different from other's pll, 1 means xtal */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - } - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB mipi uhs PLL ref clock select - * - * @param pllType: PLL XTAL type - * @param refClk: PLL ref clock select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_GLB_WAC_PLL_TYPE(pllType)); - CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk)); - - switch (pllType) { - case GLB_MU_PLL_MIPIPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - case GLB_MU_PLL_UHSPLL: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_UHS_PLL_CFG0_OFFSET; - break; - default: - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - break; - } - - /* xxxpll_refclk_sel */ - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure WIFIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_WIFIPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_WIFIPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_WIFIPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure AUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_AUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_AUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_AUPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure CPUPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_CPUPLL); - GLB_WAC_PLL_Ref_Clk_Sel(GLB_WAC_PLL_CPUPLL, refClk); - GLB_Power_On_WAC_PLL(GLB_WAC_PLL_CPUPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_MIPIPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_MIPIPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_MIPIPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure MIPIPLL clock div - * - * @param divEn: div enable - * @param divRatio: div ratio - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio) -{ - uint32_t REG_PLL_BASE_ADDRESS = 0; - uint32_t tmpVal = 0; - - REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_MIPI_PLL_CFG0_OFFSET; - - tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN, divEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, divRatio); - BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reconfigure UHSPLL clock - * - * @param xtalType: XTAL frequency type - * @param pllCfg: PLL configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList) -{ - GLB_PLL_REF_CLK_Type refClk; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(pllCfgList[xtalType]), 1); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief GLB set display clock - * - * @param enable: ENABLE or DISABLE - * @param srcClk: source clock type - * @param evenDiv: divider in even number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv) -{ - uint32_t tmpVal = 0; - uint32_t evenNum = 0; - - CHECK_PARAM(IS_GLB_DISP_CLK_TYPE(srcClk)); - CHECK_PARAM((evenDiv <= 0x7F)); - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - if ((evenDiv >= 8) && (evenDiv <= 126)) { - evenNum = evenDiv & ~(1 << 0); - } else { - evenNum = evenDiv; - } - - tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1); - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN); - } - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum); - BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase - * @param len: data length to erase - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - char flashCfgMagic[] = "FCFG"; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8, group, bank); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, group, bank); - - if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - if(RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg, group, bank) == SUCCESS){ - return SUCCESS; - } - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t ret = 0; - - ret = SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); - if(callFromFlash){ - SFlash_Set_IDbus_Cfg(pFlashCfg, pFlashCfg->ioMode&0xf , 1, 0, 32, bank); - } - if((ret&BFLB_FLASH_ID_VALID_FLAG) != 0){ - return ret; - } - - jdecId = (ret&0xffffff); - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_sec_dbg.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_DBG - * @{ - */ - -/** @defgroup SEC_DBG_Private_Macros - * @{ - */ - -/*@} end of group SEC_DBG_Private_Macros */ - -/** @defgroup SEC_DBG_Private_Types - * @{ - */ - -/*@} end of group SEC_DBG_Private_Types */ - -/** @defgroup SEC_DBG_Private_Variables - * @{ - */ - -/*@} end of group SEC_DBG_Private_Variables */ - -/** @defgroup SEC_DBG_Global_Variables - * @{ - */ - -/*@} end of group SEC_DBG_Global_Variables */ - -/** @defgroup SEC_DBG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_DBG_Private_Fun_Declaration */ - -/** @defgroup SEC_DBG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Sec Dbg read chip ID - * - * @param id[8]: chip ID buffer - * - * @return None - * -*******************************************************************************/ -void Sec_Dbg_Read_Chip_ID(uint8_t id[8]) -{ - uint32_t idLow, idHigh; - - idLow = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_LOW); - BL_WRWD_TO_BYTEP(id, idLow); - - idHigh = BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_CHIP_ID_HIGH); - BL_WRWD_TO_BYTEP((id + 4), idHigh); -} - -/***************************************************************************** / - * @brief Sec Dbg set PWD - * - * @param pwd: PWD buffer - * - * @return None - * -*******************************************************************************/ -void Sec_Dbg_Set_Dbg_Pwd(const uint32_t pwd[4]) -{ - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD_LOW, pwd[0]); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD_HIGH, pwd[1]); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD2_LOW, pwd[2]); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_DBG_PWD2_HIGH, pwd[3]); -} - -/****************************************************************************/ /** - * @brief Sec Dbg read debug mode - * - * @param None - * - * @return debug mode status - * -*******************************************************************************/ -uint32_t Sec_Dbg_Read_Dbg_Mode(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_MODE); -} - -/****************************************************************************/ /** - * @brief Sec Dbg read debug enable status - * - * @param None - * - * @return enable status - * -*******************************************************************************/ -uint32_t Sec_Dbg_Read_Dbg_Enable(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS), SEC_DBG_SD_DBG_ENA); -} - -/****************************************************************************/ /** - * @brief Sec Dbg Set debug trigger status - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Dbg_Set_Dbg_Trigger(void) -{ - uint32_t tmpVal=0; - tmpVal=BL_RD_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS); - tmpVal=BL_SET_REG_BIT(tmpVal,SEC_DBG_SD_DBG_PWD_TRIG); - BL_WR_REG(SEC_DBG_BASE, SEC_DBG_SD_STATUS,tmpVal); -} - -/*@} end of group SEC_DBG_Public_Functions */ - -/*@} end of group SEC_DBG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c deleted file mode 100644 index 8e12b99b16..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sec_eng.c +++ /dev/null @@ -1,5135 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sec_eng.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_sec_eng.h" -#include "bl808_tzc_sec.h" -#include "bl808_l1c.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SEC_ENG - * @{ - */ - -/** @defgroup SEC_ENG_Private_Macros - * @{ - */ -#define PUT_UINT32_BE(n, b, i) \ - { \ - (b)[(i)] = (uint8_t)((n) >> 24); \ - (b)[(i) + 1] = (uint8_t)((n) >> 16); \ - (b)[(i) + 2] = (uint8_t)((n) >> 8); \ - (b)[(i) + 3] = (uint8_t)((n)); \ - } -#define PUT_UINT32(n, b, i) \ - { \ - (b)[(i) + 3] = (uint8_t)((n) >> 24); \ - (b)[(i) + 2] = (uint8_t)((n) >> 16); \ - (b)[(i) + 1] = (uint8_t)((n) >> 8); \ - (b)[(i) + 0] = (uint8_t)((n)); \ - } -#define PUT_UINT64_BE(n, b, i) \ - { \ - (b)[(i)] = (uint8_t)((n) >> 56); \ - (b)[(i) + 1] = (uint8_t)((n) >> 48); \ - (b)[(i) + 2] = (uint8_t)((n) >> 40); \ - (b)[(i) + 3] = (uint8_t)((n) >> 32); \ - (b)[(i) + 4] = (uint8_t)((n) >> 24); \ - (b)[(i) + 5] = (uint8_t)((n) >> 16); \ - (b)[(i) + 6] = (uint8_t)((n) >> 8); \ - (b)[(i) + 7] = (uint8_t)((n)); \ - } -#define SEC_ENG_SHA_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_AES_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_PKA_INT_TIMEOUT_COUNT (100 * 320 * 1000) -#define SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT (100 * 320 * 1000) - -/*@} end of group SEC_ENG_Private_Macros */ - -/** @defgroup SEC_ENG_Private_Types - * @{ - */ -struct pka0_pld_cfg { - union { - struct - { - uint32_t size : 12; /*[11: 0], r/w, 0x0 */ - uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ - uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t op : 7; /*[30:24], r/w, 0x0 */ - uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_pldi_cfg { - union { - struct - { - uint32_t rsvd : 12; /*[11: 0], r/w, 0x0 */ - uint32_t d_reg_index : 8; /*[19:12], r/w, 0x0 */ - uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t op : 7; /*[30:24], r/w, 0x0 */ - uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_first_cfg { - union { - struct - { - uint32_t s0_reg_idx : 8; /*[7: 0], r/w, 0x0 */ - uint32_t s0_reg_type : 4; /*[11:8], r/w, 0x0 */ - uint32_t d_reg_idx : 8; /*[19:12], r/w, 0x0 */ - uint32_t d_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t op : 7; /*[30:24], r/w, 0x0 */ - uint32_t last_op : 1; /*[31:31], r/w, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_snd_cfg_S1_only { - union { - struct - { - uint32_t reserved_0_11 : 12; /*[11: 0], rsvd, 0x0 */ - uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ - uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_snd_cfg_S2_only { - union { - struct - { - uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ - uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ - uint32_t reserved_12_31 : 20; /*[31:12], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_common_op_snd_cfg_S1_S2 { - union { - struct - { - uint32_t s2_reg_idx : 8; /*[7 : 0], r/w, 0x0 */ - uint32_t s2_reg_type : 4; /*[11: 8], r/w, 0x0 */ - uint32_t s1_reg_idx : 8; /*[19:12], r/w, 0x0 */ - uint32_t s1_reg_type : 4; /*[23:20], r/w, 0x0 */ - uint32_t reserved_24_31 : 8; /*[31:24], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -struct pka0_bit_shift_op_cfg { - union { - struct - { - uint32_t bit_shift : 15; /*[14: 0], r/w, 0x0 */ - uint32_t reserved_24_31 : 17; /*[31:15], rsvd, 0x0 */ - } BF; - uint32_t WORD; - } value; -}; - -/*@} end of group SEC_ENG_Private_Types */ - -/** @defgroup SEC_ENG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *secEngIntCbfArra[SEC_ENG_INT_ALL] = { NULL }; -#endif - -/*@} end of group SEC_ENG_Private_Variables */ - -/** @defgroup SEC_ENG_Global_Variables - * @{ - */ - -/*@} end of group SEC_ENG_Global_Variables */ - -/** @defgroup SEC_ENG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SEC_ENG_Private_Fun_Declaration */ - -/** @defgroup SEC_ENG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief SHA256 initialization function - * - * @param shaCtx: SHA256 context pointer - * @param shaNo: SHA ID type - * @param shaType: SHA type - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA256_Init(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t shaTmpBuf[16], uint32_t padding[16]) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); - - /* Deal SHA control register to set SHA mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - if (shaType < 8) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7); - } - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA256_Ctx)); - - /* Init temp buffer and padding buffer */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 64); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA512 initialization function - * - * @param shaCtx: SHA512 context pointer - * @param shaNo: SHA ID type - * @param shaType: SHA type - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less that 128 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA512_Init(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint64_t shaTmpBuf[16], uint64_t padding[16]) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); - - /* Deal SHA control register to set SHA mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - if (shaType < 8) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7); - } - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA512_Ctx)); - - /* Init temp buffer and padding buffer */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 128); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief MD5 initialization function - * - * @param md5Ctx: MD5 context pointer - * @param shaNo: SHA ID type - * @param shaType: SHA type - * @param md5TmpBuf[16]: MD5 temp buffer for store data that is less that 64 bytes - * @param padding[16]: MD5 padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_MD5_Init(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, SEC_ENG_SHA_Type shaType, uint32_t md5TmpBuf[16], uint32_t padding[16]) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - CHECK_PARAM(IS_SEC_ENG_SHA_TYPE(shaType)); - - /* Deal SHA control register to set SHA mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - if (shaType < 8) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE, shaType); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE_EXT, shaType - 7); - } - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Clear context */ - ARCH_MemSet(md5Ctx, 0, sizeof(SEC_Eng_MD5_Ctx)); - - /* Init temp buffer and padding buffer */ - md5Ctx->md5Buf = md5TmpBuf; - md5Ctx->md5Padding = padding; - ARCH_MemSet(md5Ctx->md5Padding, 0, 64); - ARCH_MemSet(md5Ctx->md5Padding, 0x80, 1); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA start function - * - * @param shaNo: SHA ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA_Start(SEC_ENG_SHA_ID_Type shaNo) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Set SHA enable */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - /* Hash sel 0 for new start */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief SHA256 update input data function - * - * @param shaCtx: SHA256 context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Update(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last SHA state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - left = shaCtx->total[0] & 0x3F; - fill = 64 - left; - - shaCtx->total[0] += (uint32_t)len; - shaCtx->total[0] &= 0xFFFFFFFF; - - if (shaCtx->total[0] < (uint32_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)shaCtx->shaBuf); - - /* Set data length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - shaCtx->shaFeed = 1; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last sha state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - /* Fill data */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - input += (fill * 64); - shaCtx->shaFeed = 1; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 update input data function - * - * @param shaCtx: SHA512 context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Update(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint64_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - if ((((uintptr_t)input) & 0x07) != 0) { - return ERROR; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last SHA state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - left = shaCtx->total[0] & 0x7F; - fill = 128 - left; - - shaCtx->total[0] += (uint64_t)len; - - if (shaCtx->total[0] < (uint64_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)shaCtx->shaBuf); - - /* Set data length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - shaCtx->shaFeed = 1; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 128; - len = len % 128; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last sha state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, shaCtx->shaFeed); - - /* Fill data */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - input += (fill * 128); - shaCtx->shaFeed = 1; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 update input data function - * - * @param md5Ctx: MD5 context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Update(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last SHA state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, md5Ctx->md5Feed); - - left = md5Ctx->total[0] & 0x3F; - fill = 64 - left; - - md5Ctx->total[0] += (uint32_t)len; - md5Ctx->total[0] &= 0xFFFFFFFF; - - if (md5Ctx->total[0] < (uint32_t)len) { - md5Ctx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, fill); - - /* Set data source address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)md5Ctx->md5Buf); - - /* Set data length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, 1); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - md5Ctx->md5Feed = 1; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* SHA need set se_sha_sel to 1 to keep the last sha state */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL, md5Ctx->md5Feed); - - /* Fill data */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_MSA, (uintptr_t)input); - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MSG_LEN, fill); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - input += (fill * 64); - md5Ctx->md5Feed = 1; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA256 finish to get output function - * - * @param shaCtx: SHA256 context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Finish(SEC_Eng_SHA256_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t shaMode; - uint8_t msgLen[8]; - uint8_t *p = (uint8_t *)hash; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT32_BE(high, msgLen, 0); - PUT_UINT32_BE(low, msgLen, 4); - - last = shaCtx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(shaCtx->shaPadding, msgLen, 8); - Sec_Eng_SHA256_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE); - /* Copy SHA value */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_4); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA224 || shaMode == SEC_ENG_SHA256) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_5); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_6); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA256) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_7); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - } - } - - /* Disable SHA engine*/ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 finish to get output function - * - * @param shaCtx: SHA512 context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Finish(SEC_Eng_SHA512_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint64_t last, padn; - uint64_t high, low; - uint8_t shaMode; - uint8_t msgLen[16]; - uint8_t *p = (uint8_t *)hash; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - high = (shaCtx->total[0] >> 61) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT64_BE(high, msgLen, 0); - PUT_UINT64_BE(low, msgLen, 8); - - last = shaCtx->total[0] & 0x7F; - padn = (last < 112) ? (112 - last) : (240 - last); - - Sec_Eng_SHA512_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(shaCtx->shaPadding, msgLen, 16); - Sec_Eng_SHA512_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, 16); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - shaMode = (SEC_ENG_SHA_Type)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_SHA_0_MODE); - /* Copy SHA value */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA512T256 || shaMode == SEC_ENG_SHA384 || shaMode == SEC_ENG_SHA512) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA384 || shaMode == SEC_ENG_SHA512) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_4); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_4); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_5); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_5); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - if (shaMode == SEC_ENG_SHA512) { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_6); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_6); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_H_7); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_7); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - } - } - } - - /* Disable SHA engine*/ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 finish to get output function - * - * @param md5Ctx: MD5 context pointer - * @param shaNo: SHA ID type - * @param hash: MD5 output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Finish(SEC_Eng_MD5_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t msgLen[8]; - uint8_t *p = (uint8_t *)hash; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - high = (md5Ctx->total[0] >> 29) | (md5Ctx->total[1] << 3); - low = (md5Ctx->total[0] << 3); - - PUT_UINT32(low, msgLen, 0); - PUT_UINT32(high, msgLen, 4); - - last = md5Ctx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_MD5_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(md5Ctx->md5Padding, msgLen, 8); - Sec_Eng_MD5_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - - /* Copy SHA value */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_0); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_1); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_2); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_HASH_L_3); - *p++ = (tmpVal & 0xff); - *p++ = ((tmpVal >> 8) & 0xff); - *p++ = ((tmpVal >> 16) & 0xff); - *p++ = ((tmpVal >> 24) & 0xff); - - /* Disable SHA engine*/ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_HASH_SEL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA enable link mode and set link config address - * - * @param shaNo: SHA ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA_Enable_Link(SEC_ENG_SHA_ID_Type shaNo) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Enable sha and enable link mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief SHA disable link mode - * - * @param shaNo: SHA ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA_Disable_Link(SEC_ENG_SHA_ID_Type shaNo) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Disable sha and disable link mode */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_LINK_MODE); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_EN); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief SHA256 link mode initialization function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param linkAddr: SHA link configure address - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 64 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA256_Link_Init(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t shaTmpBuf[16], uint32_t padding[16]) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA256_Link_Ctx)); - - /* Init temp buffer,padding buffer and link address */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 64); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - shaCtx->linkAddr = linkAddr; - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA512 link mode initialization function - * - * @param shaCtx: SHA512 link mode context pointer - * @param shaNo: SHA ID type - * @param linkAddr: SHA link configure address - * @param shaTmpBuf[16]: SHA temp buffer for store data that is less than 128 bytes - * @param padding[16]: SHA padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_SHA512_Link_Init(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint64_t shaTmpBuf[16], uint64_t padding[16]) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Clear context */ - ARCH_MemSet(shaCtx, 0, sizeof(SEC_Eng_SHA512_Link_Ctx)); - - /* Init temp buffer,padding buffer and link address */ - shaCtx->shaBuf = shaTmpBuf; - shaCtx->shaPadding = padding; - ARCH_MemSet(shaCtx->shaPadding, 0, 128); - ARCH_MemSet(shaCtx->shaPadding, 0x80, 1); - shaCtx->linkAddr = linkAddr; - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief MD5 link mode initialization function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param linkAddr: MD5 link configure address - * @param shaTmpBuf[16]: MD5 temp buffer for store data that is less than 64 bytes - * @param padding[16]: MD5 padding buffer for store padding data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_MD5_Link_Init(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, uint32_t md5TmpBuf[16], uint32_t padding[16]) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Clear context */ - ARCH_MemSet(md5Ctx, 0, sizeof(SEC_Eng_MD5_Link_Ctx)); - - /* Init temp buffer,padding buffer and link address */ - md5Ctx->md5Buf = md5TmpBuf; - md5Ctx->md5Padding = padding; - ARCH_MemSet(md5Ctx->md5Padding, 0, 64); - ARCH_MemSet(md5Ctx->md5Padding, 0x80, 1); - md5Ctx->linkAddr = linkAddr; - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_SHA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief SHA256 link mode update input data function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Link_Update(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - left = shaCtx->total[0] & 0x3F; - fill = 64 - left; - - shaCtx->total[0] += (uint32_t)len; - shaCtx->total[0] &= 0xFFFFFFFF; - - if (shaCtx->total[0] < (uint32_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)shaCtx->shaBuf; - - /* Set data length */ - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = 1; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Fill data */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)input; - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = fill; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - input += (fill * 64); - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 link mode update input data function - * - * @param shaCtx: SHA512 link mode context pointer - * @param shaNo: SHA ID type - * @param input: SHA input data pointer, and the address should be word align - * @param len: SHA input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Link_Update(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint64_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - left = shaCtx->total[0] & 0x7F; - fill = 128 - left; - - shaCtx->total[0] += (uint64_t)len; - - if (shaCtx->total[0] < (uint64_t)len) { - shaCtx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, fill); - /* Set data source address */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)shaCtx->shaBuf; - - /* Set data length */ - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = 1; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 128; - len = len % 128; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Fill data */ - *(uint32_t *)(uintptr_t)(shaCtx->linkAddr + 4) = (uint32_t)(uintptr_t)input; - *((uint16_t *)(uintptr_t)shaCtx->linkAddr + 1) = fill; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - input += (fill * 128); - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) |= 0x40; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)shaCtx->shaBuf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 link mode update input data function - * - * @param md5Ctx: MD5 link mode context pointer - * @param shaNo: SHA ID type - * @param input: MD5 input data pointer, and the address should be word align - * @param len: MD5 input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Link_Update(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, const uint8_t *input, uint32_t len) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t fill; - uint32_t left; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - if (len == 0) { - return SUCCESS; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, md5Ctx->linkAddr); - - left = md5Ctx->total[0] & 0x3F; - fill = 64 - left; - - md5Ctx->total[0] += (uint32_t)len; - md5Ctx->total[0] &= 0xFFFFFFFF; - - if (md5Ctx->total[0] < (uint32_t)len) { - md5Ctx->total[1]++; - } - - if (left && len >= fill) { - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, fill); - - /* Set data source address */ - *(uint32_t *)(uintptr_t)(md5Ctx->linkAddr + 4) = (uint32_t)(uintptr_t)md5Ctx->md5Buf; - - /* Set data length */ - *((uint16_t *)(uintptr_t)md5Ctx->linkAddr + 1) = 1; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) |= 0x40; - input += fill; - len -= fill; - left = 0; - } - - fill = len / 64; - len = len % 64; - - if (fill > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Fill data */ - *(uint32_t *)(uintptr_t)(md5Ctx->linkAddr + 4) = (uint32_t)(uintptr_t)input; - *((uint16_t *)(uintptr_t)md5Ctx->linkAddr + 1) = fill; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - input += (fill * 64); - /* Choose accumulating last hash in the next time */ - *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) |= 0x40; - } - - if (len > 0) { - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Copy left data into temp buffer */ - ARCH_MemCpy_Fast((void *)((uint8_t *)md5Ctx->md5Buf + left), input, len); - } - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief CRC16 link mode work input data function - * - * @param shaNo: SHA ID type - * @param linkAddr: CRC16 link mode address - * @param input: CRC16 input data pointer, and the address should be word align - * @param len: CRC16 input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_CRC16_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(shaNo)); - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0) { - return ERROR; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, linkAddr); - - /* Change source buffer address and destination buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - - /* Set data length, 16 bits per block */ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len * 8 / 16; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* CRC16 code len is 16 bits */ - ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x10), 2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief CRC32 link mode work input data function - * - * @param shaNo: SHA ID type - * @param linkAddr: CRC32 link mode address - * @param input: CRC32 input data pointer, and the address should be word align - * @param len: CRC32 input data length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_CRC32_Link_Work(SEC_ENG_SHA_ID_Type shaNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(shaNo)); - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0) { - return ERROR; - } - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, linkAddr); - - /* Change source buffer address and destination buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - - /* Set data length , 32 bits per block*/ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len * 8 / 32; - - /* Trigger */ - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_TRIG_1T)); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* CRC32 code len is 32 bits */ - ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x10), 4); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA256 link mode finish to get output function - * - * @param shaCtx: SHA256 link mode context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA256_Link_Finish(SEC_Eng_SHA256_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t msgLen[8]; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t shaMode = (*(uint32_t *)(uintptr_t)shaCtx->linkAddr) >> 2 & 0x7; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - high = (shaCtx->total[0] >> 29) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT32_BE(high, msgLen, 0); - PUT_UINT32_BE(low, msgLen, 4); - - last = shaCtx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - Sec_Eng_SHA256_Link_Update(shaCtx, shaNo, msgLen, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Get result according to SHA mode,result is placed in (link address + offset:8) */ - switch (shaMode) { - case 0: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 32); - break; - - case 1: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 28); - break; - - case 2: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 20); - break; - - case 3: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 20); - break; - - default: - break; - } - - /* Choose new hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) &= ~0x40; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SHA512 link mode finish to get output function - * - * @param shaCtx: SHA512 link mode context pointer - * @param shaNo: SHA ID type - * @param hash: SHA output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_SHA512_Link_Finish(SEC_Eng_SHA512_Link_Ctx *shaCtx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint64_t last, padn; - uint64_t high, low; - uint8_t msgLen[16]; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t shaMode = (*(uint32_t *)(uintptr_t)shaCtx->linkAddr) >> 2 & 0x7; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, shaCtx->linkAddr); - - high = (shaCtx->total[0] >> 61) | (shaCtx->total[1] << 3); - low = (shaCtx->total[0] << 3); - - PUT_UINT64_BE(high, msgLen, 0); - PUT_UINT64_BE(low, msgLen, 8); - - last = shaCtx->total[0] & 0x7F; - padn = (last < 112) ? (112 - last) : (240 - last); - - Sec_Eng_SHA512_Link_Update(shaCtx, shaNo, (uint8_t *)shaCtx->shaPadding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - Sec_Eng_SHA512_Link_Update(shaCtx, shaNo, msgLen, 16); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Get result according to SHA mode,result is placed in (link address + offset:8) */ - switch (shaMode) { - case 4: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 64); - break; - - case 5: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 48); - break; - - case 6: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 28); - break; - - case 7: - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(shaCtx->linkAddr + 8), 32); - break; - - default: - break; - } - - /* Choose new hash in the next time */ - *((uint32_t *)(uintptr_t)shaCtx->linkAddr) &= ~0x40; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief MD5 link mode finish to get output function - * - * @param md5Ctx: MD5 link mode context pointer - * @param shaNo: SHA ID type - * @param hash: MD5 output data of SHA result - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_MD5_Link_Finish(SEC_Eng_MD5_Link_Ctx *md5Ctx, SEC_ENG_SHA_ID_Type shaNo, uint8_t *hash) -{ - uint32_t last, padn; - uint32_t high, low; - uint8_t msgLen[8]; - uint32_t SHAx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_SHA_ID_TYPE(shaNo)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - /* Set link address */ - BL_WR_REG(SHAx, SEC_ENG_SE_SHA_0_LINK, md5Ctx->linkAddr); - - high = (md5Ctx->total[0] >> 29) | (md5Ctx->total[1] << 3); - low = (md5Ctx->total[0] << 3); - - PUT_UINT32(low, msgLen, 0); - PUT_UINT32(high, msgLen, 4); - - last = md5Ctx->total[0] & 0x3F; - padn = (last < 56) ? (56 - last) : (120 - last); - - Sec_Eng_MD5_Link_Update(md5Ctx, shaNo, (uint8_t *)md5Ctx->md5Padding, padn); - - /* Wait for shaPadding idle */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - Sec_Eng_MD5_Link_Update(md5Ctx, shaNo, msgLen, 8); - - /* Wait finished */ - timeoutCnt = SEC_ENG_SHA_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(SHAx, SEC_ENG_SE_SHA_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_BUSY)); - - ARCH_MemCpy_Fast(hash, (uint8_t *)(uintptr_t)(md5Ctx->linkAddr + 8), 16); - - /* Choose new hash in the next time */ - *((uint32_t *)(uintptr_t)md5Ctx->linkAddr) &= ~0x40; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group0 request SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_SHA_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_SHA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_SHA_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if ((tmpVal & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release SHA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_SHA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES initialization function - * - * @param aesCtx: AES context pointer - * @param aesNo: AES ID type - * @param aesType: AES type:ECB,CTR,CBC - * @param keyType: AES key type:128,256,192 - * @param enDecType: AES encryption or decryption - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Init(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Type aesType, SEC_ENG_AES_Key_Type keyType, SEC_ENG_AES_EnDec_Type enDecType) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_TYPE(aesType)); - CHECK_PARAM(IS_SEC_ENG_AES_KEY_TYPE(keyType)); - CHECK_PARAM(IS_SEC_ENG_AES_ENDEC_TYPE(enDecType)); - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Set AES mode type*/ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE, aesType); - - /* Set AES key type */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE, keyType); - - /* Set AES encryption or decryption */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_DEC_EN, enDecType); - - /* Clear dec_key_sel to select new key */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - - /* Clear aes iv sel to select new iv */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_IV_SEL); - - /* Clear AES interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T); - - /* Enable AES */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Clear AES context */ - memset(aesCtx, 0, sizeof(SEC_Eng_AES_Ctx)); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES enable function,set AES bigendian - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Enable_BE(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* set 0x0f to 0x1f for xts mode */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, 0x1f); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief AES enable function,set AES littleendian - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Enable_LE(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* set 0x00 to 0x0f for xts mode */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, 0x10); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_AES_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief AES enable link mode - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Enable_Link(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* Enable aes link mode */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); -} - -/****************************************************************************/ /** - * @brief AES disable link mode - * - * @param aesNo: AES ID type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Disable_Link(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* Disable aes link mode */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_LINK_MODE)); -} - -/****************************************************************************/ /** - * @brief AES work in link mode - * - * @param aesNo: AES ID type - * @param linkAddr: Address of config structure in link mode - * @param in: AES input data buffer to deal with - * @param len: AES input data length - * @param out: AES output data buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Link_Work(SEC_ENG_AES_ID_Type aesNo, uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0 || len % 16 != 0) { - return ERROR; - } - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Set link address */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_LINK, linkAddr); - - /* Change source buffer address and destination buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - *(uint32_t *)(uintptr_t)(linkAddr + 8) = (uint32_t)(uintptr_t)out; - - /* Set data length */ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len / 16; - - /* Enable aes */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); - - /* Start aes engine and wait finishing */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T)); - - __NOP(); - __NOP(); - timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Disable aes */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES set hardware key source:efuse region for CPU0 or region efuse for CPU1 - * - * @param aesNo: AES ID type - * @param src: AES key source type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Hw_Key_Src(SEC_ENG_AES_ID_Type aesNo, uint8_t src) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_SBOOT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_SBOOT_KEY_SEL, src); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_SBOOT, tmpVal); -} - -/****************************************************************************/ /** - * @brief AES set KEY and IV - * - * @param aesNo: AES ID type - * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW - * @param key: AES KEY pointer - * @param iv: AES IV pointer - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Key_IV(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t keyType; - uint32_t aesType; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - aesType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE); - - /* Set IV, XTS mode and other mode are different */ - if (aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - } else { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - } - - /* Select hardware key */ - if (keySrc == SEC_ENG_AES_KEY_HW) { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_HW); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_1_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL, tmpVal); - - return; - } - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_7, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_6, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE); - - if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS || aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_1, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_0, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - } - - /* Select software key */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_SW); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief AES set KEY and IV with bigendian - * - * @param aesNo: AES ID type - * @param keySrc: AES KEY type:SEC_ENG_AES_KEY_HW or SEC_ENG_AES_KEY_SW - * @param key: AES KEY pointer - * @param iv: AES IV pointer - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Key_IV_BE(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Key_Src_Type keySrc, const uint8_t *key, const uint8_t *iv) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t keyType; - uint32_t aesType; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_KEY_SRC_TYPE(keySrc)); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - aesType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_BLOCK_MODE); - - /* Set IV, XTS mode and other mode are different */ - if (aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - } else { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_0, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_1, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_2, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_IV_3, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - } - - /* Select hardware key */ - if (keySrc == SEC_ENG_AES_KEY_HW) { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_HW); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_SEL, tmpVal); - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_1_KEY_SEL, *key); - BL_WR_REG(AESx, SEC_ENG_SE_AES_1_KEY_SEL, tmpVal); - - return; - } - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_0, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_1, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_2, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_3, BL_RDWD_FRM_BYTEP(key)); - key += 4; - - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - keyType = BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MODE); - - if (keyType == (uint32_t)SEC_ENG_AES_KEY_192BITS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, BL_RDWD_FRM_BYTEP(key)); - key += 4; - } else if (keyType == (uint32_t)SEC_ENG_AES_KEY_256BITS || keyType == (uint32_t)SEC_ENG_AES_DOUBLE_KEY_128BITS || aesType == (uint32_t)SEC_ENG_AES_XTS) { - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_4, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_5, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_6, BL_RDWD_FRM_BYTEP(key)); - key += 4; - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_KEY_7, BL_RDWD_FRM_BYTEP(key)); - key += 4; - } - - /* Select software key */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_HW_KEY_EN, SEC_ENG_AES_KEY_SW); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); -} - -/****************************************************************************/ /** - * @brief AES set counter byte type in CTR mode - * - * @param aesNo: AES ID type - * @param counterType: AES counter type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_AES_Set_Counter_Byte(SEC_ENG_AES_ID_Type aesNo, SEC_ENG_AES_Counter_Type counterType) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_AES_ID_TYPE(aesNo)); - CHECK_PARAM(IS_SEC_ENG_AES_COUNTER_TYPE(counterType)); - - /* Set counter type */ - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_ENDIAN, BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_CTR_LEN, counterType)); -} - -/****************************************************************************/ /** - * @brief AES encrypt or decrypt input data - * - * @param aesCtx: AES context pointer - * @param aesNo: AES ID type - * @param in: AES input data buffer to deal with - * @param len: AES input data length - * @param out: AES output data buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Crypt(SEC_Eng_AES_Ctx *aesCtx, SEC_ENG_AES_ID_Type aesNo, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - if (len % 16 != 0) { - return ERROR; - } - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - /* Clear trigger */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Set input and output address */ - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_MSA, (uintptr_t)in); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_MDA, (uintptr_t)out); - - /* Set message length */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_MSG_LEN, len / 16); - - if (aesCtx->mode == SEC_ENG_AES_CTR) { - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - } - - /* Set IV sel:0 for new, 1 for last */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_AES_0_IV_SEL, aesCtx->aesFeed); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Trigger AES Engine */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_TRIG_1T); - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - /* Wait finished */ - timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - aesCtx->aesFeed = 1; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief AES finish function, clean register - * - * @param aesNo: AES ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_AES_Finish(SEC_ENG_AES_ID_Type aesNo) -{ - uint32_t AESx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_AES_BUSY_TIMEOUT_COUNT; - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(AESx, SEC_ENG_SE_AES_0_CTRL); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_BUSY)); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_EN); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_DEC_KEY_SEL); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_IV_SEL); - - BL_WR_REG(AESx, SEC_ENG_SE_AES_0_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group0 request access for AES - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_AES_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release AES Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_AES_Access(void) -{ - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request AES Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_AES_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 2) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release AES Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_AES_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TRNG enable TRNG interrupt - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Trng_Enable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - /* FIXME:default reseed number is 0x1ff, to verify, use 0xa to speed up */ - //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,SEC_ENG_SE_TRNG_0_RESEED_N,0x1ff); - - /* No interrupt as default */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_EN); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* busy will be set to 1 after trigger, the gap is 1T */ - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - do { - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_BUSY)); - - /* Clear trng interrupt */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_TRNG_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_TRNG_IRQHandler); -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TRNG enable TRNG interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Enable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief TRNG disable TRNG interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Disable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief TRNG get random data out - * - * @param data[32]: TRNG output data - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Trng_Read(uint8_t data[32]) -{ - uint8_t *p = (uint8_t *)data; - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_TRNG_BUSY_TIMEOUT_COUNT; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* busy will be set to 1 after trigger, the gap is 1T */ - __NOP(); - __NOP(); - __NOP(); - __NOP(); - - do { - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_BUSY)); - - /* copy trng value */ - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7)); - p += 4; - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* Clear data */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TRNG get random data out - * - * @param data: TRNG output data buffer - * - * @param len: total length to get in bytes - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Trng_Get_Random(uint8_t *data, uint32_t len) -{ - uint8_t tmpBuf[32]; - uint32_t readLen = 0; - uint32_t i = 0, cnt = 0; - - while (readLen < len) { - if (Sec_Eng_Trng_Read(tmpBuf) != SUCCESS) { - return -1; - } - - cnt = len - readLen; - - if (cnt > sizeof(tmpBuf)) { - cnt = sizeof(tmpBuf); - } - - for (i = 0; i < cnt; i++) { - data[readLen + i] = tmpBuf[i]; - } - - readLen += cnt; - } - - return 0; -} - -/****************************************************************************/ /** - * @brief TRNG Interrupt Read Trigger - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Read_Trigger(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - Sec_Eng_Trng_Int_Enable(); - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief TRNG get random data out with Interrupt - * - * @param data[32]: TRNG output data - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Int_Read(uint8_t data[32]) -{ - uint8_t *p = (uint8_t *)data; - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - /* copy trng value */ - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_0)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_1)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_2)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_3)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_4)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_5)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_6)); - p += 4; - BL_WRWD_TO_BYTEP(p, BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_DOUT_7)); - p += 4; - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_TRIG_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - /* Clear data */ - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_DOUT_CLR_1T); - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Disable TRNG - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_Trng_Disable(void) -{ - uint32_t TRNGx = SEC_ENG_BASE; - uint32_t tmpVal; - - tmpVal = BL_RD_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_EN); - //tmpVal=BL_CLR_REG_BIT(tmpVal,SEC_ENG_SE_TRNG_0_RESEED_N); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T); - - BL_WR_REG(TRNGx, SEC_ENG_SE_TRNG_0_CTRL_0, tmpVal); -} - -/****************************************************************************/ /** - * @brief Group0 request TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_Trng_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_Trng_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_Trng_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 4) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release TRNG Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_Trng_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief PKA Reset - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Reset(void) -{ - uint8_t val; - - //Disable sec engine - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, 0); - - //Enable sec engine - val = 1 << 3; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, val); -} - -/****************************************************************************/ /** - * @brief PKA Enable big endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_BigEndian_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief PKA Enable little endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LittleEndian_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_PKA_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief PKA get status function - * - * @param status: Structure pointer of PKA status type - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_GetStatus(SEC_Eng_PKA_Status_Type *status) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - *(uint16_t *)status = (uint16_t)BL_GET_REG_BITS_VAL(tmpVal, SEC_ENG_SE_PKA_0_STATUS); -} - -/****************************************************************************/ /** - * @brief PKA clear interrupt - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Clear_Int(void) -{ - uint32_t ctrl; - - ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - ctrl = BL_SET_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); - - ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - ctrl = BL_CLR_REG_BIT(ctrl, SEC_ENG_SE_PKA_0_INT_CLR_1T); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, ctrl); -} - -/****************************************************************************/ /** - * @brief PKA get Register size according to Register type - * - * @param reg_type: PKA Register type - * - * @return Register size - * -*******************************************************************************/ -static uint16_t Sec_Eng_PKA_Get_Reg_Size(SEC_ENG_PKA_REG_SIZE_Type reg_type) -{ - switch (reg_type) { - case SEC_ENG_PKA_REG_SIZE_8: - return 8; - - case SEC_ENG_PKA_REG_SIZE_16: - return 16; - - case SEC_ENG_PKA_REG_SIZE_32: - return 32; - - case SEC_ENG_PKA_REG_SIZE_64: - return 64; - - case SEC_ENG_PKA_REG_SIZE_96: - return 96; - - case SEC_ENG_PKA_REG_SIZE_128: - return 128; - - case SEC_ENG_PKA_REG_SIZE_192: - return 192; - - case SEC_ENG_PKA_REG_SIZE_256: - return 256; - - case SEC_ENG_PKA_REG_SIZE_384: - return 384; - - case SEC_ENG_PKA_REG_SIZE_512: - return 512; - - default: - return 0; - } -} - -/****************************************************************************/ /** - * @brief PKA set pre-load register configuration - * - * @param size: Data size in word to write - * @param regIndex: Register index - * @param regType: Register type - * @param op: PKA operation - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Pld_Cfg(uint16_t size, uint8_t regIndex, SEC_ENG_PKA_REG_SIZE_Type regType, SEC_ENG_PKA_OP_Type op, uint8_t lastOp) -{ - struct pka0_pld_cfg cfg; - - cfg.value.BF.size = size; - cfg.value.BF.d_reg_index = regIndex; - cfg.value.BF.d_reg_type = regType; - cfg.value.BF.op = op; - cfg.value.BF.last_op = lastOp; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation first configuration - * - * @param s0RegIndex: Register index - * @param s0RegType: Register type - * @param dRegIndex: Result Register index - * @param dRegType: Result Register type - * @param op: PKA operation - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_First_Cfg(uint8_t s0RegIndex, uint8_t s0RegType, uint8_t dRegIndex, uint8_t dRegType, - uint8_t op, uint8_t lastOp) -{ - struct pka0_common_op_first_cfg cfg; - - cfg.value.BF.s0_reg_idx = s0RegIndex; - cfg.value.BF.s0_reg_type = s0RegType; - - if (op != SEC_ENG_PKA_OP_LCMP) { - cfg.value.BF.d_reg_idx = dRegIndex; - cfg.value.BF.d_reg_type = dRegType; - } - - cfg.value.BF.op = op; - cfg.value.BF.last_op = lastOp; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation second configuration1 - * - * @param s1RegIndex: Register index - * @param s1RegType: Register type - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(uint8_t s1RegIndex, uint8_t s1RegType) -{ - struct pka0_common_op_snd_cfg_S1_only cfg; - - cfg.value.BF.s1_reg_idx = s1RegIndex; - cfg.value.BF.s1_reg_type = s1RegType; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation second configuration2 - * - * @param s2RegIndex: Register index - * @param s2RegType: Register type - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(uint8_t s2RegIndex, uint8_t s2RegType) -{ - struct pka0_common_op_snd_cfg_S2_only cfg; - - cfg.value.BF.s2_reg_idx = s2RegIndex; - cfg.value.BF.s2_reg_type = s2RegType; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA write common operation second configuration1 and configuration 2 - * - * @param s1RegIndex: Configuration 1 Register index - * @param s1RegType: Configuration 1 Register type - * @param s2RegIndex: Configuration 2 Register index - * @param s2RegType: Configuration 3 Register type - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(uint8_t s1RegIndex, uint8_t s1RegType, uint8_t s2RegIndex, uint8_t s2RegType) -{ - struct pka0_common_op_snd_cfg_S1_S2 cfg; - - cfg.value.BF.s1_reg_idx = s1RegIndex; - cfg.value.BF.s1_reg_type = s1RegType; - cfg.value.BF.s2_reg_idx = s2RegIndex; - cfg.value.BF.s2_reg_type = s2RegType; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); -} - -/****************************************************************************/ /** - * @brief PKA wait for complete interrupt - * - * @param None - * - * @return SUCCESS - * -*******************************************************************************/ -static BL_Err_Type Sec_Eng_PKA_Wait_ISR(void) -{ - uint32_t pka0_ctrl; - uint32_t timeoutCnt = SEC_ENG_PKA_INT_TIMEOUT_COUNT; - - do { - pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (!BL_GET_REG_BITS_VAL(pka0_ctrl, SEC_ENG_SE_PKA_0_INT)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief PKA read block data from register - * - * @param dest: Pointer to buffer address - * @param src: Pointer to register address - * @param len: Data len in word - * - * @return None - * -*******************************************************************************/ -#ifdef ARCH_ARM -#ifndef __GNUC__ -__ASM void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - PUSH{ R3 - R6, LR } Start0 - CMP R2, -# 4 BLT Finish0 - LDR R3, - [R1] LDR R4, [R1] LDR R5, [R1] LDR R6, [R1] STMIA R0 !, { R3 - R6 } SUBS R2, R2, #4 B Start0 Finish0 POP - { - R3 - R6, PC - } -} -#else -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - __asm__ __volatile__("push {r3-r6,lr}\n\t" - "Start0 :" - "cmp r2,#4\n\t" - "blt Finish0\n\t" - "ldr r3,[r1]\n\t" - "ldr r4,[r1]\n\t" - "ldr r5,[r1]\n\t" - "ldr r6,[r1]\n\t" - "stmia r0!,{r3-r6}\n\t" - "sub r2,r2,#4\n\t" - "b Start0\n\t" - "Finish0 :" - "pop {r3-r6,pc}\n\t"); -} -#endif -#endif -#ifdef ARCH_RISCV -void Sec_Eng_PKA_Read_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - uint32_t wrLen = len - len % 4; - uint32_t i; - - for (i = 0; i < wrLen; i++) { - dest[i] = *src; - } -} -#endif - -/****************************************************************************/ /** - * @brief PKA Write block data to register - * - * @param dest: Pointer to register address - * @param src: Pointer to buffer address - * @param len: Data len in word - * - * @return None - * -*******************************************************************************/ -#ifdef ARCH_ARM -#ifndef __GNUC__ -__ASM void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - PUSH{ R3 - R6, LR } Start1 - CMP R2, -# 4 BLT Finish1 - LDMIA R1 !, - { R3 - R6 } STR R3, [R0] STR R4, [R0] STR R5, [R0] STR R6, [R0] SUBS R2, R2, #4 B Start1 Finish1 POP - { - R3 - R6, PC - } -} -#else -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - __asm__ __volatile__("push {r3-r6,lr}\n\t" - "Start1 :" - "cmp r2,#4\n\t" - "blt Finish1\n\t" - "ldmia r1!,{r3-r6}\n\t" - "str r3,[r0]\n\t" - "str r4,[r0]\n\t" - "str r5,[r0]\n\t" - "str r6,[r0]\n\t" - "sub r2,r2,#4\n\t" - "b Start1\n\t" - "Finish1 :" - "pop {r3-r6,pc}\n\t"); -} -#endif -#endif -#ifdef ARCH_RISCV -void Sec_Eng_PKA_Write_Block(uint32_t *dest, const uint32_t *src, uint32_t len) -{ - uint32_t wrLen = len - len % 4; - uint32_t i; - - for (i = 0; i < wrLen; i++) { - *dest = src[i]; - } -} -#endif - -/****************************************************************************/ /** - * @brief PKA get result - * - * @param result: Pointer to store result - * @param retSize: Result length in word - * @param regLen: register length in byte - * - * @return None - * -*******************************************************************************/ -static void Sec_Eng_PKA_Get_Result(uint32_t *result, uint8_t retSize, uint16_t regLen) -{ - uint32_t ret_data = 0x00; - int index = 0x00; - - /* Wait for the result */ - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - Sec_Eng_PKA_Read_Block(result, (uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), retSize); - index = retSize - (retSize % 4); - - while (index < retSize) { - ret_data = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW); - result[index] = ret_data; - index++; - } -} - -/****************************************************************************/ /** - * @brief PKA load data to register - * - * @param regType: Register type - * @param regIndex: Register index - * @param data: Data buffer - * @param size: Data length in word - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Write_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, const uint32_t *data, uint16_t size, uint8_t lastOp) -{ - int index = 0x00; - uint16_t regLen = Sec_Eng_PKA_Get_Reg_Size(regType); - - Sec_Eng_PKA_Write_Pld_Cfg(size, regIndex, regType, SEC_ENG_PKA_OP_CTLIR_PLD, lastOp); - - if (size > regLen / 4) { - size = regLen / 4; - } - - Sec_Eng_PKA_Write_Block((uint32_t *)(SEC_ENG_BASE + SEC_ENG_SE_PKA_0_RW_OFFSET), data, size); - index = size - (size % 4); - - while (index < size) { - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data[index]); - index++; - } -} - -/****************************************************************************/ /** - * @brief PKA read data from register - * - * @param regType: Register type - * @param regIdx: Register index - * @param result: Data buffer - * @param retSize: Data length in word - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Read_Data(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIdx, uint32_t *result, uint8_t retSize) -{ - uint16_t regSize; - uint32_t dummyData = 0; - - regSize = Sec_Eng_PKA_Get_Reg_Size(regType); - - if (retSize > regSize / 4) { - result = NULL; - return; - } - - Sec_Eng_PKA_Write_Pld_Cfg(retSize, regIdx, regType, SEC_ENG_PKA_OP_CFLIR_BUFFER, 1); - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - Sec_Eng_PKA_Get_Result(result, retSize, regSize); -} - -/****************************************************************************/ /** - * @brief PKA clear register - * - * @param dRegType: Register type - * @param dRegIdx: Register index - * @param size: Data length in word - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_CREG(SEC_ENG_PKA_REG_SIZE_Type dRegType, uint8_t dRegIdx, uint8_t size, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Pld_Cfg(size, dRegIdx, dRegType, SEC_ENG_PKA_OP_CLIR, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA load data to register - * - * @param regType: regType: Register type - * @param regIndex: regIndex: Register index - * @param data: data: Data buffer - * @param lastOp: size: Data length in word - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Write_Immediate(SEC_ENG_PKA_REG_SIZE_Type regType, uint8_t regIndex, uint32_t data, uint8_t lastOp) -{ - struct pka0_pldi_cfg cfg; - - cfg.value.BF.rsvd = 0; - cfg.value.BF.d_reg_index = regIndex; - cfg.value.BF.d_reg_type = regType; - cfg.value.BF.op = SEC_ENG_PKA_OP_SLIR; - cfg.value.BF.last_op = lastOp; - - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, data); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA negative source data:D = (1 << SIZE{S0})-S0 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source Register type - * @param s0RegIdx: Source Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_NREG(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_NLIR, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA move data:D = S0 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source Register type - * @param s0RegIdx: Source Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_Move_Data(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOVDAT, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA resize data:D = S0, D.Size = S0.Size - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source Register type - * @param s0RegIdx: Source Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_RESIZE(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_RESIZE, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod add:D = (S0 + S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MADD, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod sub:D = (S0 - S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSUB, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod :D = S0 mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MREM(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MREM, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod mul:D = (S0 * S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MMUL, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod sqr:D = (S0 ^ 2) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MSQR, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod exp:D = (S0 ^ S1) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MEXP(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MEXP, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1_S2(s1RegIdx, s1RegType, s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod exp:D = (S0 ^ (S2-2) ) mod S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_MINV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MINV, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA Report COUT to 1 when S0 < S1 - * - * @param cout: Compare result - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LCMP(uint8_t *cout, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t s1RegType, uint8_t s1RegIdx) -{ - uint32_t pka0_ctrl = 0x00; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, 0, 0, SEC_ENG_PKA_OP_LCMP, 1); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - pka0_ctrl = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - *cout = (pka0_ctrl & SEC_ENG_PKA_STATUS_LAST_OPC_MASK) >> SEC_ENG_PKA_STATUS_LAST_OPC_OFFSET; -} - -/****************************************************************************/ /** - * @brief PKA add:D = S0 + S1 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LADD(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LADD, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA sub:D = S0 - S1 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LSUB(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSUB, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mul:D = S0 * S1 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s1RegType: Source 1 Register type - * @param s1RegIdx: Source 1 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LMUL(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s1RegType, uint8_t s1RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S1(s1RegIdx, s1RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA sqr:D = S0^2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LSQR(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, uint8_t lastOp) -{ - uint32_t dummyData = 0; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LSQR, lastOp); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, dummyData); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA div:D = S0 / S2 - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param s2RegType: Source 2 Register type - * @param s2RegIdx: Source 2 Register index - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LDIV(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint8_t s2RegType, uint8_t s2RegIdx, uint8_t lastOp) -{ - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV, lastOp); - Sec_Eng_PKA_Write_Common_OP_Snd_Cfg_S2(s2RegIdx, s2RegType); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA shift:D = S0 << BIT SHIFT - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param bit_shift: Bits to shift - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LMUL2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, uint8_t lastOp) -{ - struct pka0_bit_shift_op_cfg cfg; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LMUL2N, 0); - - cfg.value.BF.bit_shift = bit_shift; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA shift:D = S0 >> BIT SHIFT - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param bit_shift: Bits to shift - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LDIV2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, uint8_t lastOp) -{ - struct pka0_bit_shift_op_cfg cfg; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_LDIV2N, 0); - - cfg.value.BF.bit_shift = bit_shift; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA mod 2N:D = S0 % ((1 << BIT SHIFT)-1) - * - * @param dRegType: Destination Register type - * @param dRegIdx: Destination Register index - * @param s0RegType: Source 0 Register type - * @param s0RegIdx: Source 0 Register index - * @param bit_shift: Bits to shift - * @param lastOp: Last operation - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_PKA_LMOD2N(uint8_t dRegType, uint8_t dRegIdx, uint8_t s0RegType, uint8_t s0RegIdx, - uint16_t bit_shift, uint8_t lastOp) -{ - struct pka0_bit_shift_op_cfg cfg; - - Sec_Eng_PKA_Write_Common_OP_First_Cfg(s0RegIdx, s0RegType, dRegIdx, dRegType, SEC_ENG_PKA_OP_MOD2N, lastOp); - - cfg.value.BF.bit_shift = bit_shift; - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_RW, cfg.value.WORD); - - if (lastOp) { - Sec_Eng_PKA_Wait_ISR(); - Sec_Eng_PKA_Clear_Int(); - } -} - -/****************************************************************************/ /** - * @brief PKA GF to Mont filed 2N:d = (a<> 6) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 6) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release PKA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_PKA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request PKA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_PKA_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 6) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 6) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release PKA Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_PKA_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set gmac little endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_T_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_H_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_X_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief Set gmac big endian - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_T_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_H_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_X_ENDIAN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); - Interrupt_Handler_Register(SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn, SEC_GMAC_IRQHandler); -#endif -} - -/****************************************************************************/ /** - * @brief GMAC enable link mode - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Enable_Link(void) -{ - uint32_t tmpVal; - - /* Enable gmac link mode */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_EN)); -} - -/****************************************************************************/ /** - * @brief GMAC disable link mode - * - * @param None - * - * @return None - * -*******************************************************************************/ -void Sec_Eng_GMAC_Disable_Link(void) -{ - uint32_t tmpVal; - - /* Disable gmac link mode */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_EN)); -} - -/****************************************************************************/ /** - * @brief GMAC work in link mode - * - * @param linkAddr: Address of config structure in link mode - * @param in: GMAC input data buffer to deal with - * @param len: GMAC input data length - * @param out: GMAC output data buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_GMAC_Link_Work(uint32_t linkAddr, const uint8_t *in, uint32_t len, uint8_t *out) -{ - uint32_t GMACx = SEC_ENG_BASE; - uint32_t tmpVal; - uint32_t timeoutCnt = SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT; - - /* Link address should word align */ - if ((linkAddr & 0x03) != 0 || len % 16 != 0) { - return ERROR; - } - - /* Wait finished */ - do { - tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_BUSY)); - - /* Set link address */ - BL_WR_REG(GMACx, SEC_ENG_SE_GMAC_0_LCA, linkAddr); - - /* Change source buffer address */ - *(uint32_t *)(uintptr_t)(linkAddr + 4) = (uint32_t)(uintptr_t)in; - - /* Set data length */ - *((uint16_t *)(uintptr_t)linkAddr + 1) = len / 16; - - /* Start gmac engine and wait finishing */ - tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_TRIG_1T)); - timeoutCnt = SEC_ENG_GMAC_BUSY_TIMEOUT_COUNT; - - do { - tmpVal = BL_RD_REG(GMACx, SEC_ENG_SE_GMAC_0_CTRL_0); - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } while (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_BUSY)); - - /* Get result */ - ARCH_MemCpy_Fast(out, (uint8_t *)(uintptr_t)(linkAddr + 0x18), 16); - - return SUCCESS; -} - -#ifndef BFLB_USE_HAL_DRIVER -/****************************************************************************/ /** - * @brief Sec Eng Interrupt Handler - * - * @param intType: IRQ Type - * - * @return None - * -*******************************************************************************/ -static void SEC_Eng_IntHandler(SEC_ENG_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_TRNG] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_TRNG](); - } - } - - break; - - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_AES] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_AES](); - } - } - - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_SHA] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_SHA](); - } - } - - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_PKA_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_PKA] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_PKA](); - } - } - - break; - - case SEC_ENG_INT_CDET: - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_CDET] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_CDET](); - } - - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_INT)) { - /* Clear interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_CLR_1T)); - - /* Call the callback function */ - if (secEngIntCbfArra[SEC_ENG_INT_GMAC] != NULL) { - secEngIntCbfArra[SEC_ENG_INT_GMAC](); - } - } - - break; - - default: - break; - } -} -#endif - -/****************************************************************************/ /** - * @brief Group0 request GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Request_GMAC_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x02); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x01) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group0 release GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group0_Release_GMAC_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Group1 request GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Request_GMAC_Access(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x03) { - /* SHA control idle, write to request*/ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x04); - - /* Check request result */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_CTRL_PROT_RD); - - if (((tmpVal >> 10) & 0x03) == 0x02) { - return SUCCESS; - } - } - - return ERROR; -} - -/****************************************************************************/ /** - * @brief Group1 release GMAC Access - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type Sec_Eng_Group1_Release_GMAC_Access(void) -{ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_PROT, 0x06); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Sec Eng Interrupt Mask or Unmask - * - * @param intType: Sec Eng Interrupt Type - * @param intMask: MASK or UNMASK - * - * @return None - * -*******************************************************************************/ -void SEC_Eng_IntMask(SEC_ENG_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_CDET: - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } - - break; - - case SEC_ENG_INT_ALL: - if (intMask == UNMASK) { - /* UNMASK(Enable) this interrupt */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } else { - /* MASK(Disable) this interrupt */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_MASK)); - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_MASK)); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Sec Eng Interrupt clear - * - * @param intType: Sec Eng Interrupt Type - * - * @return None - * -*******************************************************************************/ -void SEC_Eng_ClrIntStatus(SEC_ENG_INT_Type intType) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_AES_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_SHA_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_PKA_0_INT_CLR_1T)); - break; - - case SEC_ENG_INT_CDET: - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0, BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_GMAC_0_INT_CLR_1T)); - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Sec Eng Interrupt callback function install - * - * @param intType: Sec Eng Interrupt Type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SEC_Eng_Int_Callback_Install(SEC_ENG_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - secEngIntCbfArra[intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Sec Eng get interrupt status - * - * @param intType: Sec Eng Interrupt Type - * - * @return status of interrupt - * -*******************************************************************************/ -BL_Sts_Type SEC_Eng_GetIntStatus(SEC_ENG_INT_Type intType) -{ - uint32_t tmpVal; - BL_Sts_Type status = RESET; - - /* Check the parameters */ - CHECK_PARAM(IS_SEC_ENG_INT_TYPE(intType)); - - switch (intType) { - case SEC_ENG_INT_AES: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_AES_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_AES_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_SHA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_SHA_0_CTRL); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_SHA_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_TRNG: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_TRNG_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_PKA: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_PKA_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_PKA_0_INT)) { - status = SET; - } - - break; - - case SEC_ENG_INT_CDET: - break; - - case SEC_ENG_INT_GMAC: - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_GMAC_0_CTRL_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SEC_ENG_SE_GMAC_0_INT)) { - status = SET; - } - - break; - - default: - break; - } - - return status; -} - -#ifndef BFLB_USE_HAL_DRIVER -/****************************************************************************/ /** - * @brief Sec Eng Trng IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_TRNG_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_TRNG); -} - -/****************************************************************************/ /** - * @brief Sec Eng Pka IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_PKA_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_PKA); -} - -/****************************************************************************/ /** - * @brief Sec Eng Aes IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_AES_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_AES); -} - -/****************************************************************************/ /** - * @brief Sec Eng Sha IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_SHA_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_SHA); -} - -/****************************************************************************/ /** - * @brief Sec Eng Cdet IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_CDET_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_CDET); -} - -/****************************************************************************/ /** - * @brief Sec Eng Gmac IRQ Handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void SEC_GMAC_IRQHandler(void) -{ - SEC_Eng_IntHandler(SEC_ENG_INT_GMAC); -} -#endif - -/****************************************************************************/ /** - * @brief turn on sec ring - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION SEC_Eng_Turn_On_Sec_Ring(void) -{ - uint32_t tmpVal = 0; - - /* Turn-on Sec Ring Oscillation */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3); - tmpVal = BL_SET_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_ROSC_EN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3, tmpVal); -} - -/****************************************************************************/ /** - * @brief turn off sec ring - * - * @param None - * - * @return None - * -*******************************************************************************/ -void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void) -{ - uint32_t tmpVal = 0; - - /* Turn-off Sec Ring Oscillation */ - tmpVal = BL_RD_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3); - tmpVal = BL_CLR_REG_BIT(tmpVal, SEC_ENG_SE_TRNG_0_ROSC_EN); - BL_WR_REG(SEC_ENG_BASE, SEC_ENG_SE_TRNG_0_CTRL_3, tmpVal); -} - -/*@} end of group SEC_ENG_Public_Functions */ - -/*@} end of group SEC_ENG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c deleted file mode 100644 index 3d0745eb74..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg.c +++ /dev/null @@ -1,1673 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_sf_cfg.h" -#include "softcrc.h" -#include "bl808_xip_sflash.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG - * @{ - */ - -/** @defgroup SF_CFG_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_Private_Macros */ - -/** @defgroup SF_CFG_Private_Types - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; -#endif - -/*@} end of group SF_CFG_Private_Types */ - -/** @defgroup SF_CFG_Private_Variables - * @{ - */ -#ifndef BFLB_USE_ROM_DRIVER -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_80DV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xFF, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_16JV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_64JW = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 0, - .cReadMode = 0xf0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Winb_256FV = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xef, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0x20, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = 0x24, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1600, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q80E_Q16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_WQ80E_WQ16E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 32 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 8 / 8, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 20 * 1000, - .pdDelay = 20, - .qeData = 0x12, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Gd_Q32E_Q128E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x31, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_128 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xC2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x01, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 300, - .timeE32k = 1200, - .timeE64k = 1200, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 45, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_Mxic_25L256 = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc2, - - .deBurstWrapCmd = 0xC0, - .deBurstWrapCmdDmyClk = 0x00, - .deBurstWrapDataMode = SF_CTRL_DATA_1_LINE, - .deBurstWrapData = 0x10, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 0, - .qeBit = 0x06, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x15, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xA5, - - .burstWrapCmd = 0xC0, - .burstWrapCmdDmyClk = 0x00, - .burstWrapDataMode = SF_CTRL_DATA_1_LINE, - .burstWrapData = 0x02, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x38, - .qppAddrMode = SF_CTRL_ADDR_4_LINES, - - .ioMode = (SF_CTRL_QIO_MODE | 0x20), - .clkDelay = 1, - .clkInvert = 0x3f, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 400, - .timeE32k = 1000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 20, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1440ef, - //.name="Winb_80DV_08_33", - .cfg = &flashCfg_Winb_80DV, - }, - { - .jedecID = 0x1540ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1640ef, - //.name="Winb_32FV_32_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1840ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1940ef, - //.name="Winb_256FV_128_33", - .cfg = &flashCfg_Winb_256FV, - }, - { - .jedecID = 0x1460ef, - //.name="Winb_80EW_08_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1560ef, - //.name="Winb_16FW_16_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1660ef, - //.name="Winb_32FW_32_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1760ef, - //.name="WB_64JW_64_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1860ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1570ef, - //.name="Winb_16JV_16_33", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1870ef, - //.name="Winb_128JV_128_33", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1680ef, - //.name="Winb_32JW_32_18", - .cfg = &flashCfg_Winb_16JV, - }, - { - .jedecID = 0x1880ef, - //.name="Winb_128JW_128_18", - .cfg = &flashCfg_Winb_64JW, - }, - { - .jedecID = 0x1440C8, - //.name="GD_Q08E_08_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1540C8, - //.name="GD_Q16E_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1640C8, - //.name="GD_Q32C_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1740C8, - //.name="GD_Q64E_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1840C8, - //.name="GD_Q128E_128_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1460C8, - //.name="GD_LQ08C_08_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1560C8, - //.name="GD_LE16C_16_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1660C8, - //.name="GD_LQ32D_32_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1860c8, - //.name="GD_LQ128E_64_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x1465C8, - //.name="GD_WQ80E_80_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1565C8, - //.name="GD_WQ16E_16_33", - .cfg = &flashCfg_Gd_WQ80E_WQ16E, - }, - { - .jedecID = 0x1665C8, - //.name="GD_WQ32E_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x15345e, - //.name="ZB_WQ16A_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15405e, - //.name="ZB_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x16405e, - //.name="ZB_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x17405e, - //.name="ZB_Q64B_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x14605E, - //.name="ZB_VQ80", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x15605E, - //.name="ZB_VQ16", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x1820C2, - //.name="MX_25L128_128_33", - .cfg = &flashCfg_Mxic_128, - }, - { - .jedecID = 0x1920C2, - //.name="MX_25L256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID = 0x3925C2, - //.name="MX_25U256_256_33", - .cfg = &flashCfg_Mxic_25L256, - }, - { - .jedecID=0x144020, - //.name="XM_25QH80_80_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x154020, - //.name="XM_25QH16_16_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x164020, - //.name="XM_25QH32_32_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID=0x174020, - //.name="XM_25QH64_64_33", - .cfg=&flashCfg_Winb_16JV, - }, - { - .jedecID = 0x15400B, - //.name="XT_25F16B_16_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x16400B, - //.name="XT_25F32B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x17400B, - //.name="XT_25F64B_32_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x18400B, - //.name="XT_25F128B_128_33", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x14600B, - //.name="XT_25Q80B_08_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x16600B, - //.name="XT_25Q32B_32_18", - .cfg = &flashCfg_Gd_Q80E_Q16E, - }, - { - .jedecID = 0x144068, - //.name="Boya_Q08B_08_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x154068, - //.name="Boya_Q16B_16_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x164068, - //.name="Boya_Q32B_32_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x174068, - //.name="Boya_Q64A_64_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - }, - { - .jedecID = 0x184068, - //.name="Boya_Q128A_128_33", - .cfg = &flashCfg_Gd_Q32E_Q128E, - } -}; -#endif - -/*@} end of group SF_CFG_Private_Variables */ - -/** @defgroup SF_CFG_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_Global_Variables */ - -/** @defgroup SF_CFG_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_AF; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 2; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_FLASH; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - - if (i == 0 || i == 1) { - /* flash clk and cs is output */ - cfg.gpioMode = GPIO_MODE_OUTPUT; - } else { - /* data are bidir */ - cfg.gpioMode = GPIO_MODE_AF; - } - - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Deinit external flash GPIO according to flash GPIO config - * - * @param extFlashPin: Flash GPIO config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin) -{ - GLB_GPIO_Cfg_Type cfg; - uint8_t gpiopins[6]; - uint8_t i = 0; - - cfg.gpioMode = GPIO_MODE_INPUT; - cfg.pullType = GPIO_PULL_UP; - cfg.drive = 1; - cfg.smtCtrl = 1; - cfg.gpioFun = GPIO_FUN_GPIO; - - if (extFlashPin == 0) { - gpiopins[0] = BFLB_EXTFLASH_CLK0_GPIO; - gpiopins[1] = BFLB_EXTFLASH_CS0_GPIO; - gpiopins[2] = BFLB_EXTFLASH_DATA00_GPIO; - gpiopins[3] = BFLB_EXTFLASH_DATA10_GPIO; - gpiopins[4] = BFLB_EXTFLASH_DATA20_GPIO; - gpiopins[5] = BFLB_EXTFLASH_DATA30_GPIO; - } else { - return ERROR; - } - - for (i = 0; i < sizeof(gpiopins); i++) { - cfg.gpioPin = gpiopins[i]; - GLB_GPIO_Init(&cfg); - } - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Private_Functions */ - -/** @defgroup SF_CFG_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8, group, bank); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, group, bank); - - if (ARCH_MemCmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - return SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg, group, bank); -} -#endif - -/****************************************************************************/ /** - * @brief Init flash GPIO according to flash Pin config - * - * @param flashPinCfg: Specify flash Pin config - * @param restoreDefault: Wether to restore default setting - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault) -{ - uint8_t selEmbedded = 0; - uint8_t swap = 0; - - if ((flashPinCfg&(1<<3)) > 0) { - return ERROR; - } - - if (restoreDefault) { - /* Set Default first */ - GLB_Set_Flash_IO_PARM(1, 1); - SF_Ctrl_Select_Pad(SF_IO_EMB_SWAP_IO0_IO3); - - /* Default is set, so return */ - if (flashPinCfg == SF_IO_EMB_SWAP_IO0_IO3) { - return SUCCESS; - } - } - - if (flashPinCfg & (1 << 2)) { - /* Init sf2 gpio */ - SF_Cfg_Init_Ext_Flash_Gpio(0); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* if pin select dual flash, embedded is default */ - if ((flashPinCfg & (1 << 4))) { - selEmbedded = 1; - } - - swap = ((flashPinCfg >> 1) & 1); - swap = (!swap); - GLB_Set_Flash_IO_PARM(selEmbedded, swap); - SF_Ctrl_Select_Pad(flashPinCfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint8_t autoScan = 0; - uint8_t flashPin = 0; - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t offset; - BL_Err_Type stat; - - autoScan = ((flashPinCfg >> 7) & 1); - flashPin = (flashPinCfg & 0x7F); - - ARCH_MemCpy_Fast(pFlashCfg, &flashCfg_Winb_16JV, sizeof(SPI_Flash_Cfg_Type)); - - if (callFromFlash == 1) { - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - return 0; - } - } - - if (autoScan) { - flashPin = 0; - - do { - if (flashPin > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - jdecId = 0; - break; - } - - if (!IS_SF_CTRL_PIN_SELECT(flashPin) || (flashPin&(1<<3)) > 0) { - flashPin++; - continue; - } - - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = 0; - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - flashPin++; - } while ((jdecId & 0x00ffff) == 0 || (jdecId & 0xffff00) == 0 || (jdecId & 0x00ffff) == 0xffff || (jdecId & 0xffff00) == 0xffff00); - } else { - /* select media gpio */ - SF_Cfg_Init_Flash_Gpio(flashPin, restoreDefault); - SFlash_Release_Powerdown(pFlashCfg); - SFlash_Reset_Continue_Read(pFlashCfg); - SFlash_DisableBurstWrap(pFlashCfg); - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - SFlash_DisableBurstWrap(pFlashCfg); - jdecId = jdecId & 0xffffff; - } - - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == jdecId) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - break; - } - } - - if (i == sizeof(flashInfos) / sizeof(flashInfos[0])) { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return jdecId; - } else { - if (callFromFlash == 1) { - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - return (jdecId | BFLB_FLASH_ID_VALID_FLAG); - } -} -#endif - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - return SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg flash init - * - * @param sel: SF pin select - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t selEmbedded = 0; - uint8_t swap = 0; - - if ((sel&(1<<3)) > 0) { - return ERROR; - } - - if (sel & (1 << 2)) { - SF_Cfg_Init_Ext_Flash_Gpio(0); - selEmbedded = 0; - } else { - selEmbedded = 1; - } - /* If pin select dual flash, embedded is default */ - if ((sel & (1 << 4))) { - selEmbedded = 1; - } - - swap = ((sel >> 1) & 1); - swap = (!swap); - GLB_Set_Flash_IO_PARM(selEmbedded, swap); - SF_Ctrl_Select_Pad(sel); - - if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { - /* Embedded pad1 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } else if (sel <= SF_IO_EXT_SF2) { - /* Pad2 or pad3 io delay set */ - SF_Ctrl_Set_IO_Delay((sel >> 2), pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Dual flash mode, embedded pad1 and pad2 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD1, pSfCtrlCfg->doDelay, pSfCtrlCfg->diDelay, pSfCtrlCfg->oeDelay); - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - } - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - } - } - - SFlash_Init(pSfCtrlCfg, pBank2Cfg); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief SF Cfg system bus 2 flash init - * - * @param sel: SF pin select - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - if (sel < SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 || sel > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - return ERROR; - } - - /* Init flash2 gpio */ - if (sel & (1 << 2)) { - SF_Cfg_Init_Ext_Flash_Gpio(0); - } - - /* Set remap for flash2 xip mode */ - SF_Ctrl_Remap_Set(pBank2Cfg->remap, pBank2Cfg->remapLock); - - /* Dual flash mode, pad2 io delay set */ - SF_Ctrl_Set_IO_Delay(SF_CTRL_PAD2, pBank2Cfg->doDelay, pBank2Cfg->diDelay, pBank2Cfg->oeDelay); - - if (pBank2Cfg->sbus2Select) { - /* Default sbus2 replace opt flash2 */ - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - - SFlash_Init(NULL, pBank2Cfg); - - return SUCCESS; -} -#endif - -/*@} end of group SF_CFG_Public_Functions */ - -/*@} end of group SF_CFG */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c deleted file mode 100644 index 9dd2683e6d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sf_cfg_ext.c +++ /dev/null @@ -1,295 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sf_cfg_ext.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "softcrc.h" -#include "bl808_sf_cfg.h" -#include "bl808_sf_cfg_ext.h" -#include "bl808_xip_sflash.h" -#include "bl808_romdriver_e907.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CFG_EXT - * @{ - */ - -/** @defgroup SF_CFG_EXT_Private_Macros - * @{ - */ -#define BFLB_FLASH_CFG_MAGIC "FCFG" - -/*@} end of group SF_CFG_EXT_Private_Macros */ - -/** @defgroup SF_CFG_EXT_Private_Types - * @{ - */ -typedef struct -{ - uint32_t jedecID; - char *name; - const SPI_Flash_Cfg_Type *cfg; -} Flash_Info_t; - -/*@} end of group SF_CFG_EXT_Private_Types */ - -/** @defgroup SF_CFG_EXT_Private_Variables - * @{ - */ -static const ATTR_TCM_CONST_SECTION SPI_Flash_Cfg_Type flashCfg_GD_LQ64E = { - .resetCreadCmd = 0xff, - .resetCreadCmdSize = 3, - .mid = 0xc8, - - .deBurstWrapCmd = 0x77, - .deBurstWrapCmdDmyClk = 0x3, - .deBurstWrapDataMode = SF_CTRL_DATA_4_LINES, - .deBurstWrapData = 0xF0, - - /*reg*/ - .writeEnableCmd = 0x06, - .wrEnableIndex = 0x00, - .wrEnableBit = 0x01, - .wrEnableReadRegLen = 0x01, - - .qeIndex = 1, - .qeBit = 0x01, - .qeWriteRegLen = 0x02, - .qeReadRegLen = 0x1, - - .busyIndex = 0, - .busyBit = 0x00, - .busyReadRegLen = 0x1, - .releasePowerDown = 0xab, - - .readRegCmd[0] = 0x05, - .readRegCmd[1] = 0x35, - .writeRegCmd[0] = 0x01, - .writeRegCmd[1] = 0x01, - - .fastReadQioCmd = 0xeb, - .frQioDmyClk = 16 / 8, - .cReadSupport = 1, - .cReadMode = 0xa0, - - .burstWrapCmd = 0x77, - .burstWrapCmdDmyClk = 0x3, - .burstWrapDataMode = SF_CTRL_DATA_4_LINES, - .burstWrapData = 0x40, - /*erase*/ - .chipEraseCmd = 0xc7, - .sectorEraseCmd = 0x20, - .blk32EraseCmd = 0x52, - .blk64EraseCmd = 0xd8, - /*write*/ - .pageProgramCmd = 0x02, - .qpageProgramCmd = 0x32, - .qppAddrMode = SF_CTRL_ADDR_1_LINE, - - .ioMode = SF_CTRL_QIO_MODE, - .clkDelay = 1, - .clkInvert = 0x3d, - - .resetEnCmd = 0x66, - .resetCmd = 0x99, - .cRExit = 0xff, - .wrEnableWriteRegLen = 0x00, - - /*id*/ - .jedecIdCmd = 0x9f, - .jedecIdCmdDmyClk = 0, - .enter32BitsAddrCmd = 0xb7, - .exit32BitsAddrCmd = 0xe9, - .sectorSize = 4, - .pageSize = 256, - - /*read*/ - .fastReadCmd = 0x0b, - .frDmyClk = 8 / 8, - .qpiFastReadCmd = 0x0b, - .qpiFrDmyClk = 8 / 8, - .fastReadDoCmd = 0x3b, - .frDoDmyClk = 8 / 8, - .fastReadDioCmd = 0xbb, - .frDioDmyClk = 0, - .fastReadQoCmd = 0x6b, - .frQoDmyClk = 8 / 8, - - .qpiFastReadQioCmd = 0xeb, - .qpiFrQioDmyClk = 16 / 8, - .qpiPageProgramCmd = 0x02, - .writeVregEnableCmd = 0x50, - - /* qpi mode */ - .enterQpi = 0x38, - .exitQpi = 0xff, - - /*AC*/ - .timeEsector = 500, - .timeE32k = 2000, - .timeE64k = 2000, - .timePagePgm = 5, - .timeCe = 33 * 1000, - .pdDelay = 3, - .qeData = 0, -}; - -static const ATTR_TCM_CONST_SECTION Flash_Info_t flashInfos[] = { - { - .jedecID = 0x1760c8, - //.name="GD_LQ64E_64_18", - .cfg = &flashCfg_GD_LQ64E, - }, -}; - -/*@} end of group SF_CFG_EXT_Private_Variables */ - -/** @defgroup SF_CFG_EXT_Global_Variables - * @{ - */ - -/*@} end of group SF_CFG_EXT_Global_Variables */ - -/** @defgroup SF_CFG_EXT_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */ - -/** @defgroup SF_CFG_EXT_Private_Functions - * @{ - */ - - - -/*@} end of group SF_CFG_EXT_Private_Functions */ - -/****************************************************************************/ /** - * @brief Get flash config according to flash ID patch - * - * @param flashID: Flash ID - * @param pFlashCfg: Flash config pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg) -{ - uint32_t i; - uint8_t buf[sizeof(SPI_Flash_Cfg_Type) + 8]; - uint32_t crc, *pCrc; - uint32_t xipOffset; - char flashCfgMagic[] = "FCFG"; - - if (flashID == 0) { - xipOffset = SF_Ctrl_Get_Flash_Image_Offset(0, SF_CTRL_FLASH_BANK0); - SF_Ctrl_Set_Flash_Image_Offset(0, 0, SF_CTRL_FLASH_BANK0); - XIP_SFlash_Read_Via_Cache_Need_Lock(8 + BL808_FLASH_XIP_BASE, buf, sizeof(SPI_Flash_Cfg_Type) + 8); - SF_Ctrl_Set_Flash_Image_Offset(xipOffset, 0, SF_CTRL_FLASH_BANK0); - - if (ARCH_MemCmp(buf, flashCfgMagic, 4) == 0) { - crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - pCrc = (uint32_t *)(buf + 4 + sizeof(SPI_Flash_Cfg_Type)); - - if (*pCrc == crc) { - ARCH_MemCpy_Fast(pFlashCfg, (uint8_t *)buf + 4, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } else { - if(SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID, pFlashCfg) == SUCCESS){ - return SUCCESS; - } - for (i = 0; i < sizeof(flashInfos) / sizeof(flashInfos[0]); i++) { - if (flashInfos[i].jedecID == flashID) { - ARCH_MemCpy_Fast(pFlashCfg, flashInfos[i].cfg, sizeof(SPI_Flash_Cfg_Type)); - return SUCCESS; - } - } - } - - return ERROR; -} - - -/****************************************************************************/ /** - * @brief Identify one flash patch - * - * @param callFromFlash: code run at flash or ram - * @param flashPinCfg: Bit 7: autoscan, Bit6-0: flash GPIO config - * @param restoreDefault: Wether restore default flash GPIO config - * @param pFlashCfg: Flash config pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return Flash ID - * -*******************************************************************************/ -uint32_t ATTR_TCM_SECTION SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, - uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t jdecId = 0; - uint32_t i = 0; - uint32_t ret = 0; - - ret = SF_Cfg_Flash_Identify(callFromFlash, flashPinCfg, restoreDefault, pFlashCfg, group, bank); - if(callFromFlash){ - SFlash_Set_IDbus_Cfg(pFlashCfg, pFlashCfg->ioMode&0xf , 1, 0, 32, bank); - } - if((ret&BFLB_FLASH_ID_VALID_FLAG) != 0){ - return ret; - } - - jdecId = (ret&0xffffff); - for(i=0; i
© COPYRIGHT(c) 2020 Bouffalo Lab
- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_sf_ctrl.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SF_CTRL - * @{ - */ - -/** @defgroup SF_CTRL_Private_Macros - * @{ - */ - -/*@} end of group SF_CTRL_Private_Macros */ - -/** @defgroup SF_CTRL_Private_Types - * @{ - */ - -/*@} end of group SF_CTRL_Private_Types */ - -/** @defgroup SF_CTRL_Private_Variables - * @{ - */ -#define SF_CTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) -#define SF_Ctrl_Get_AES_Region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80) - -/*@} end of group SF_CTRL_Private_Variables */ - -/** @defgroup SF_CTRL_Global_Variables - * @{ - */ - -/*@} end of group SF_CTRL_Global_Variables */ - -/** @defgroup SF_CTRL_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SF_CTRL_Private_Fun_Declaration */ - -/** @defgroup SF_CTRL_Private_Functions - * @{ - */ - -/*@} end of group SF_CTRL_Private_Functions */ - -/** @defgroup SF_CTRL_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Enable serail flash controller - * - * @param cfg: serial flash controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - if (cfg == NULL) { - return; - } - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(cfg->owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (cfg->en32bAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - if (cfg->clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, cfg->clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - /* Serail out inverted, so sf ctrl send on negative edge */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_OUT_INV_SEL, cfg->clkInvert); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_RX_INV_SEL, cfg->rxClkInvert); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); - - /* Enable AHB access sram buffer and enable sf interface */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SRAM_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); - - SF_Ctrl_Set_Owner(cfg->owner); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serail bank2 controller - * - * @param bank2Cfg: serial bank2 controller config - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg) -{ - uint32_t tmpVal = 0; - - if (bank2Cfg == NULL) { - return; - } - - /* Select if1 bank2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12); - - if (bank2Cfg->bank2RxClkInvertSrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SEL); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_CLK_SF_RX_INV_SRC); - } - - if (bank2Cfg->bank2DelaySrc) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF2_IF_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_EN); - } - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF2_IF_READ_DLY_SRC); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_12, tmpVal); - - /* Select sbus2 clock delay */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (bank2Cfg->bank2RxClkInvertSel) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL); - } - - if (bank2Cfg->bank2ClkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, bank2Cfg->bank2ClkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set io delay - * - * @param pad: Pad select - * @param doDelay: DO delay select - * @param diDelay: DI delay select - * @param oeDelay: OE delay select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay) -{ - uint32_t tmpVal = 0; - uint32_t offset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - if (pad == SF_CTRL_PAD1) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET; - } else if (pad == SF_CTRL_PAD2) { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET; - } else { - offset = SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET; - } - - /* Set do di and oe delay */ - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_0_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_1, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_1_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_2, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_2_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_3, tmpVal); - - tmpVal = BL_RD_REG(offset, SF_CTRL_IO_DLY_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DO_DLY_SEL, doDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_DI_DLY_SEL, diDelay); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IO_3_OE_DLY_SEL, oeDelay); - BL_WR_REG(offset, SF_CTRL_IO_DLY_4, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 hold sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Hold_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 hold sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Flash controller sbus2 release sram - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Release_Sram(void) -{ - uint32_t tmpVal; - - /* Sbus2 release sram */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_FN_SEL); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller sbus2 status - * - * @param None - * - * @return Wether if2 is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_Sbus2_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_EN)) { - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_IF2_FN_SEL)) { - return SET; - } else { - return RESET; - } - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 repalce - * - * @param pad: SF pad to replace - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PAD_TYPE(pad)); - - /* Sbus2 enable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); - - SF_Ctrl_Sbus2_Hold_Sram(); - - /* Sbus2 repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - - if (pad == SF_CTRL_PAD1) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - } else if (pad == SF_CTRL_PAD2) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_PAD_SEL, pad); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl sbus2 revoke replace - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Revoke_replace(void) -{ - uint32_t tmpVal = 0; - - SF_Ctrl_Sbus2_Release_Sram(); - - /* Sbus2 clear repalce pad */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF2); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_REPLACE_SF3); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); - - /* Sbus2 disable */ - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_EN); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set sbus2 clock delay - * - * @param clkDelay: Sbus2 clock delay - * @param rxClkInvert: Sbus2 rx clock invert - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0); - - if (clkDelay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF2_READ_DLY_N, clkDelay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF2_READ_DLY_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL, rxClkInvert); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF2_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (en32BitsAddr) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_32B_ADR_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash controller clock delay value - * - * @param None - * - * @return Clock delay value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Clock_Delay(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN) == 0) { - return 0; - } else { - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N) + 1; - } -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller clock delay value - * - * @param delay: Clock delay value - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Clock_Delay(uint8_t delay) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - if (delay > 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_READ_DLY_N, delay - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_READ_DLY_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl get wrap queue value - * - * @param None - * - * @return Wrap queue value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint8_t ATTR_TCM_SECTION SF_Ctrl_Get_Wrap_Queue_Value(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - return BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_Q); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl set cmds config - * - * @param cmdsCfg: SF Ctrl cmds config - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_WRAP_MODE(cmdsCfg->cmdsWrapMode)); - CHECK_PARAM(IS_SF_CTRL_WRAP_LEN_TYPE(cmdsCfg->cmdsWrapLen)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_3); - - if (cmdsCfg->ackLatency) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_1_ACK_LAT); - } - - if (cmdsCfg->cmdsCoreEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_CORE_EN); - } - - if (bank == SF_CTRL_FLASH_BANK1) { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_2_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_2_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } else { - if (cmdsCfg->cmdsEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_CMDS_1_EN); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_MODE, cmdsCfg->cmdsWrapMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_CMDS_1_WRAP_LEN, cmdsCfg->cmdsWrapLen); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_3, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl pad select - * - * @param sel: Pin select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_PIN_SELECT(sel)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (sel <= SF_IO_EXT_SF2) { - /* Single flash mode, disable bank2 */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - - if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) { - /* Select embedded pad1 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } else { - /* Select pad2 or pad3 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, ((sel&0xf) >> 2)); - } - } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) { - /* Dual flash mode, enable bank2, select pad1 and pad2 */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_BK2_MODE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_PAD_SEL, 0); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl dual flash memory remap set - * - * @param remap: Memory remap set type - * @param lock: Memory remap lock - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_REMAP_TYPE(remap)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP, remap); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_REMAP_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl select bank on system bus - * - * @param bank: bank select type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank) -{ - /* TODO: sf_if_bk_swap */ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_IF_0_BK_SEL); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash controller owner:I/D AHB or system AHB - * - * @param owner: owner type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_OWNER_TYPE(owner)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - /* Set owner */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL, owner); - - /* Set iahb to flash interface */ - if (owner == SF_CTRL_OWNER_IAHB) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_EN); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash controller - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_IF_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with big indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_BE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash controller AES with little indian - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable_LE(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_0); - - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_KEY_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_IV_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DIN_ENDIAN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_DOUT_ENDIAN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES region - * - * @param region: region number - * @param enable: enable or not - * @param hwKey: hardware key or software key - * @param startAddr: region start address - * @param endAddr: region end address - * @param locked: lock this region or not - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, - uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal; - - if (!hwKey) { - regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - } - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_END); - /* sf_aes_end =1 means 1,11,1111,1111 */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_END, endAddr / 1024); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_END, tmpVal); - - tmpVal = BL_RD_REG(regionRegBase, SF_CTRL_SF_AES_START); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_HW_KEY_EN, hwKey); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_START, startAddr / 1024); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_REGION_LOCK, locked); - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_START, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,__REV(BL_RDWD_FRM_BYTEP(key))); - key+=4; - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco */ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_7_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(key))); - key += 4; - tmpVal -= 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - if (keyType == SF_CTRL_AES_128BITS) { - i = 4; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_256BITS) { - i = 8; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_6,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_7,BL_RDWD_FRM_BYTEP(key)); - key+=4; - */ - } else if (keyType == SF_CTRL_AES_192BITS) { - i = 6; - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_0,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_1,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_2,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_3,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_4,BL_RDWD_FRM_BYTEP(key)); - key+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_KEY_5,BL_RDWD_FRM_BYTEP(key)); - */ - } - - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS mode key with big endian - * - * @param region: region number - * @param key: key data pointer - * @param keyType: flash controller AES key type:128 bits,192 bits or 256 bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_KEY_TYPE(keyType)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_AES_MODE, keyType); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); - - if (NULL != key) { - i = 8; - tmpVal = SF_CTRL_SF_AES_KEY_0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(key)); - key += 4; - tmpVal += 4; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W3_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - iv += 4; - tmpVal -= 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W3,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,__REV(BL_RDWD_FRM_BYTEP(iv))); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W1_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, (BL_RDWD_FRM_BYTEP(iv))); - tmpVal += 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W0, addrOffset); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W0_OFFSET; - - while (i--) { - BL_WR_WORD(regionRegBase + tmpVal, BL_RDWD_FRM_BYTEP(iv)); - iv += 4; - tmpVal += 4; - } - - /* - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W0,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W1,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - BL_WR_REG(regionRegBase,SF_CTRL_SF_AES_IV_W2,BL_RDWD_FRM_BYTEP(iv)); - iv+=4; - */ - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif - -/****************************************************************************/ /** - * @brief Serial flash controller set AES XTS iv with big endian - * - * @param region: region number - * @param iv: iv data pointer - * @param addrOffset: flash address offset - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset) -{ - /* Do flash key eco*/ - uint32_t regionRegBase = SF_Ctrl_Get_AES_Region(SF_CTRL_BASE, region); - uint32_t tmpVal, i = 3; - - if (iv != NULL) { - tmpVal = SF_CTRL_SF_AES_IV_W2_OFFSET; - - while (i--) { - iv += 4; - BL_WR_WORD(regionRegBase + tmpVal, __REV(BL_RDWD_FRM_BYTEP(iv))); - tmpVal -= 4; - } - - BL_WR_REG(regionRegBase, SF_CTRL_SF_AES_IV_W3, __REV(addrOffset)); - iv += 4; - } -} -#endif -#ifndef BFLB_USE_ROM_DRIVER - -/****************************************************************************/ /** - * @brief Set serial flash controller AES mode - * - * @param mode: AES mode select - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode) -{ - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_AES_MODE_TYPE(mode)); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (mode == SF_CTRL_AES_CTR_MODE) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_BLK_MODE); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Enable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Disable serial flash controller AES - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_AES_Disable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AES_EN); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_AES, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Check is serial flash controller AES enable - * - * @param None - * - * @return Wether AES is enable - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_Is_AES_Enable(void) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_AES); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_SF_AES_EN)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash image offset - * - * @param addrOffset: Address offset value - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET, addrOffset); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET, addrOffset); - } else { - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET, addrOffset); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Get flash image offset - * - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return :Address offset value - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -uint32_t ATTR_TCM_SECTION SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmpVal = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_BANK_SELECT(bank)); - - if (group) { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID1_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID1_OFFSET); - } - } else { - if (bank == SF_CTRL_FLASH_BANK0) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_ID0_OFFSET); - } else { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_BK2_ID0_OFFSET); - } - } - - return tmpVal; -} -#endif - -/****************************************************************************/ /** - * @brief Lock/unlock sf_id0/sf_id1/sf_bk2_id0/sf_bk2_id1 offset - * - * @param lock: lock or unlock - * - * @return :None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock) -{ - uint32_t tmpVal; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_2); - if (lock) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_ID_OFFSET_LOCK); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_2, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief SF controller send one command - * - * @param cfg: Serial flash controller command configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - uint32_t cmdOffset = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_SAHB) { - return; - } - - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - /* Clear trigger */ - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Copy command buffer */ - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_SPI_MODE, SF_CTRL_QIO_MODE); - } - - /* Configure cmd */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_CMD_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_CMD_BYTE, 0); - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_ADR_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_ADR_BYTE, 0); - } - - /* Configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DMY_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, cfg->nbData - 1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_IF_0_DAT_EN); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_BYTE, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_IF_0_DAT_RW, cfg->rwFlag); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - /* Trigger */ - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_IF_0_TRIG); - BL_WR_REG(cmdOffset, SF_CTRL_IF_SAHB_0, tmpVal); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief SF Ctrl disable iahb to flash wrap access for XTS mode - * - * @param disable: Disable for 1 and enable for 0 - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Disable_Wrap_Access(uint8_t disable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (disable) { - tmpVal = BL_CLR_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, SF_CTRL_SF_AHB2SIF_DISWRAP); - } - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_1, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config SF controller for flash I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_1, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_2, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_0, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Config bank2 controller for flash2 I/D cache read - * - * @param cfg: Serial flash controller command configuration pointer - * @param cmdValid: command valid or not, for continous read, cache may need no command - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid) -{ - uint32_t tmpVal = 0; - uint32_t timeOut = 0; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_CMD_MODE_TYPE(cfg->cmdMode)); - CHECK_PARAM(IS_SF_CTRL_ADDR_MODE_TYPE(cfg->addrMode)); - CHECK_PARAM(IS_SF_CTRL_DMY_MODE_TYPE(cfg->dummyMode)); - CHECK_PARAM(IS_SF_CTRL_DATA_MODE_TYPE(cfg->dataMode)); - - timeOut = SF_CTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_1); - - if (BL_GET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_FN_SEL) != SF_CTRL_OWNER_IAHB) { - return; - } - - /* Copy command buffer */ - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_10, cfg->cmdBuf[0]); - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_11, cfg->cmdBuf[1]); - - tmpVal = BL_RD_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9); - - /* Configure SPI and IO mode*/ - if (SF_CTRL_CMD_1_LINE == cfg->cmdMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_SPI_MODE); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_QPI_MODE_EN, SF_CTRL_QPI_MODE); - } - - if (SF_CTRL_ADDR_1_LINE == cfg->addrMode) { - if (SF_CTRL_DATA_1_LINE == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_NIO_MODE); - } else if (SF_CTRL_DATA_2_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DO_MODE); - } else if (SF_CTRL_DATA_4_LINES == cfg->dataMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QO_MODE); - } - } else if (SF_CTRL_ADDR_2_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_DIO_MODE); - } else if (SF_CTRL_ADDR_4_LINES == cfg->addrMode) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_SPI_MODE, SF_CTRL_QIO_MODE); - } - - if (cmdValid) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_CMD_BYTE, 0); - } - - /* Configure address */ - if (cfg->addrSize != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, cfg->addrSize - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_ADR_BYTE, 0); - } - - /* configure dummy */ - if (cfg->dummyClks != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, cfg->dummyClks - 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_EN, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DMY_BYTE, 0); - } - - /* Configure data */ - if (cfg->nbData != 0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 1); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_EN, 0); - } - - /* Set read write flag */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SF_CTRL_SF_IF_1_DAT_RW, cfg->rwFlag); - - BL_WR_REG(SF_CTRL_BASE, SF_CTRL_SF_IF_IAHB_9, tmpVal); -} -#endif - -/****************************************************************************/ /** - * @brief Get SF Ctrl busy state - * - * @param None - * - * @return SET for SF ctrl busy or RESET for SF ctrl not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SF_Ctrl_GetBusyState(void) -{ - uint32_t tmpVal = 0; - uint32_t cmdOffset = 0; - - if (SF_Ctrl_Is_Sbus2_Enable() == RESET) { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET; - } else { - cmdOffset = SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET; - } - - tmpVal = BL_RD_REG(cmdOffset, SF_CTRL_IF_SAHB_0); - - if (BL_IS_REG_BIT_SET(tmpVal, SF_CTRL_IF_BUSY)) { - return SET; - } - - return RESET; -} -#endif - -/****************************************************************************/ /** - * @brief SF Controller interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SF_Ctrl_IRQHandler(void) -{ - /* TODO: Not implemented */ -} -#endif - -/*@} end of group SF_CTRL_Public_Functions */ - -/*@} end of group SF_CTRL */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c deleted file mode 100644 index d6dfcb749a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sflash.c +++ /dev/null @@ -1,2164 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_sflash.h" -#include "bl808_sf_ctrl.h" -#include "bl808_l1c.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SFLASH - * @{ - */ - -/** @defgroup SFLASH_Private_Macros - * @{ - */ - -/*@} end of group SFLASH_Private_Macros */ - -/** @defgroup SFLASH_Private_Types - * @{ - */ - -/*@} end of group SFLASH_Private_Types */ - -/** @defgroup SFLASH_Private_Variables - * @{ - */ -#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 320 * 1000) - -/*@} end of group SFLASH_Private_Variables */ - -/** @defgroup SFLASH_Global_Variables - * @{ - */ - -/*@} end of group SFLASH_Global_Variables */ - -/** @defgroup SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group SFLASH_Private_Fun_Declaration */ - -/** @defgroup SFLASH_Private_Functions - * @{ - */ - -/*@} end of group SFLASH_Private_Functions */ - -/** @defgroup SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Init serial flash control interface - * - * @param pSfCtrlCfg: Serial flash controller configuration pointer - * @param pBank2Cfg: Serial flash2 controller configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg) -{ - uint8_t clkDelay = 0; - uint8_t rxClkInvert = 0; - - if (pBank2Cfg != NULL) { - if (pBank2Cfg->sbus2Select) { - if (pBank2Cfg->bank2DelaySrc) { - clkDelay = pBank2Cfg->bank2ClkDelay; - } else { - if (pSfCtrlCfg != NULL) { - clkDelay = pSfCtrlCfg->clkDelay; - } else { - clkDelay = 1; - } - } - - if (pBank2Cfg->bank2RxClkInvertSrc) { - rxClkInvert = pBank2Cfg->bank2RxClkInvertSel; - } else { - if (pSfCtrlCfg != NULL) { - rxClkInvert = pSfCtrlCfg->rxClkInvert; - } else { - rxClkInvert = 0; - } - } - - SF_Ctrl_Sbus2_Set_Delay(clkDelay, rxClkInvert); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - SF_Ctrl_Bank2_Enable(pBank2Cfg); - } else { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - if (pSfCtrlCfg != NULL) { - SF_Ctrl_Enable(pSfCtrlCfg); - } -} -#endif - -/****************************************************************************/ /** - * @brief Set serial flash control interface SPI or QPI mode - * - * @param mode: Serial flash interface mode - * - * @return BFLB_RET:SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode) -{ - BL_Err_Type stat = SUCCESS; - - /* Check the parameters */ - CHECK_PARAM(IS_SF_CTRL_MODE_TYPE(mode)); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->readRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param regIndex: register index - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = (flashCfg->writeRegCmd[regIndex]) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read flash register with read command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param readRegCmd: read command - * @param regValue: register value pointer to store data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = readRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SF_Ctrl_GetBusyState()) { - arch_delay_us(1); - cnt++; - - if (cnt > 1000) { - return ERROR; - } - } - - ARCH_MemCpy(regValue, flashCtrlBuf, regLen); - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Write flash register with write command - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param writeRegCmd: write command - * @param regValue: register value pointer storing data - * @param regLen: register value length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - ARCH_MemCpy(flashCtrlBuf, regValue, regLen); - - flashCmd.cmdBuf[0] = writeRegCmd << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.nbData = regLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* take 40ms for tw(write status register) as default */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 400) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Check flash busy status - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SET for busy or RESET for not busy - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Sts_Type ATTR_TCM_SECTION SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SFlash_Read_Reg(flashCfg, flashCfg->busyIndex, (uint8_t *)&stat, flashCfg->busyReadRegLen); - - if ((stat & (1 << flashCfg->busyBit)) == 0) { - return RESET; - } - - return SET; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash write function - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Write enable*/ - flashCmd.cmdBuf[0] = (flashCfg->writeEnableCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - SFlash_Read_Reg(flashCfg, flashCfg->wrEnableIndex, (uint8_t *)&stat, flashCfg->wrEnableReadRegLen); - - if ((stat & (1 << flashCfg->wrEnableBit)) != 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex)); - } else { - stat = stat & (~(0xff << (8 * flashCfg->qeIndex))); - stat |= (flashCfg->qeData << (8 * flashCfg->qeIndex)); - } - } else { - if (flashCfg->qeData == 0) { - stat |= (1 << (flashCfg->qeBit % 8)); - } else { - stat = flashCfg->qeData; - } - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if (flashCfg->qeData == 0) { - if ((stat & (1 << flashCfg->qeBit)) != 0) { - return SUCCESS; - } - } else { - if (((stat >> (flashCfg->qeBit & 0x08)) & 0xff) == flashCfg->qeData) { - return SUCCESS; - } - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash flash controller QSPI interface - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg) -{ - uint32_t stat = 0, ret; - - if (flashCfg->qeReadRegLen == 0) { - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - return SUCCESS; - } - - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - if (flashCfg->qeWriteRegLen != 1) { - /* This is read r0,read r1 write r0,r1 case*/ - SFlash_Read_Reg(flashCfg, 0, (uint8_t *)&stat, 1); - SFlash_Read_Reg(flashCfg, 1, ((uint8_t *)&stat) + 1, 1); - stat &= (~(1 << (flashCfg->qeBit + 8 * flashCfg->qeIndex))); - } else { - stat &= (~(1 << (flashCfg->qeBit % 8))); - } - - ret = SFlash_Write_Enable(flashCfg); - - if (SUCCESS != ret) { - return ERROR; - } - - SFlash_Write_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeWriteRegLen); - SFlash_Read_Reg(flashCfg, flashCfg->qeIndex, (uint8_t *)&stat, flashCfg->qeReadRegLen); - - if ((stat & (1 << flashCfg->qeBit)) == 0) { - return SUCCESS; - } - - return ERROR; -} -#endif - -/****************************************************************************/ /** - * @brief Enable flash volatile register write enable - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->writeVregEnableCmd) << 24; - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash whole chip - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint32_t timeout = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (flashCfg->chipEraseCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - timeout = flashCfg->timeCe; - - if ((timeout >> 15) > 0) { - timeout = (timeout & 0x7FFF) * 1000; - } - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > timeout * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one sector - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param secNum: flash sector number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | ((flashCfg->sectorSize * 1024 * secNum) >> 8); - flashCmd.cmdBuf[1] = ((flashCfg->sectorSize * 1024 * secNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->sectorEraseCmd << 24) | (flashCfg->sectorSize * 1024 * secNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeEsector * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 32K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 32K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk32EraseCmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE32k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one 64K block - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param blkNum: flash 64K block number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) >> 8); - flashCmd.cmdBuf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blkNum) << 24); - } else { - flashCmd.cmdBuf[0] = (flashCfg->blk64EraseCmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blkNum); - } - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > flashCfg->timeE64k * 3) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param startaddr: start address to erase - * @param endaddr: end address(include this address) to erase - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr) -{ - uint32_t len = 0; - uint32_t eraseLen = 0; - BL_Err_Type ret = SUCCESS; - - if (startaddr > endaddr) { - return ERROR; - } - - while (startaddr <= endaddr) { - len = endaddr - startaddr + 1; - - if (flashCfg->blk64EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK64K_SIZE - flashCfg->sectorSize * 1024)) { - /* 64K margin address,and length > 64K-sector size, erase one first */ - ret = SFlash_Blk64_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK64K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK64K_SIZE; - } else if (flashCfg->blk32EraseCmd != BFLB_SPIFLASH_CMD_INVALID && - (startaddr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 && - len > (BFLB_SPIFLASH_BLK32K_SIZE - flashCfg->sectorSize * 1024)) { - /* 32K margin address,and length > 32K-sector size, erase one first */ - ret = SFlash_Blk32_Erase(flashCfg, startaddr / BFLB_SPIFLASH_BLK32K_SIZE); - eraseLen = BFLB_SPIFLASH_BLK32K_SIZE; - } else { - /* Sector erase */ - startaddr = ((startaddr) & (~(flashCfg->sectorSize * 1024 - 1))); - ret = SFlash_Sector_Erase(flashCfg, startaddr / flashCfg->sectorSize / 1024); - eraseLen = flashCfg->sectorSize * 1024; - } - - startaddr += eraseLen; - - if (ret != SUCCESS) { - return ERROR; - } - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get flash unique ID - * - * @param data: data pointer to store read data - * @param idLen: unique ID len - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetUniqueId(uint8_t *data, uint8_t idLen) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = 4; - cmd = 0x4B; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = idLen; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, idLen); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash jedec ID - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param data: data pointer to store read data - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - dummyClks = flashCfg->jedecIdCmdDmyClk; - cmd = flashCfg->jedecIdCmd; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 3); -} -#endif - -/****************************************************************************/ /** - * @brief Get flash device ID - * - * @param data: data pointer to store read data - * @param is32BitsAddr: Is flash addr mode in 32-bits - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint32_t addr = 0x00000001; - uint8_t readMode = 0xFF; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - dummyClks = 2; - cmd = 0x94; - flashCmd.addrSize = 4; - - if (is32BitsAddr) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24) | (readMode << 16); - flashCmd.addrSize++; - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - flashCmd.cmdBuf[1] = (readMode << 24); - } - - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 2; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } - - ARCH_MemCpy(data, flashCtrlBuf, 2); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash power down - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Powerdown(void) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - uint32_t timeOut = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = 0xB9; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Release flash power down for wake up - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t cmd; - uint32_t timeOut = 0; - - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = flashCfg->releasePowerDown; - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return; - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Sflash restore from power down - * - * @param pFlashCfg: Flash configuration pointer - * @param flashContRead: Whether enable continuous read - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, - SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat = SUCCESS; - uint32_t jdecId = 0; - uint8_t tmp[8]; - uint8_t ioMode = pFlashCfg->ioMode & 0xf; - - /* Wake flash up from power down */ - SFlash_Release_Powerdown(pFlashCfg); - arch_delay_us(120); - - SFlash_GetJedecId(pFlashCfg, (uint8_t *)&jdecId); - - if (SF_CTRL_QO_MODE == ioMode || SF_CTRL_QIO_MODE == ioMode) { - SFlash_Qspi_Enable(pFlashCfg); - } - - if (((pFlashCfg->ioMode >> 4) & 0x01) == 1) { - /* unwrap */ - L1C_Set_Wrap(DISABLE); - } else { - /* burst wrap */ - L1C_Set_Wrap(ENABLE); - /* For command that is setting register instead of send command, we need write enable */ - SFlash_Write_Enable(pFlashCfg); - SFlash_SetBurstWrap(pFlashCfg); - } - - if (flashContRead) { - stat = SFlash_Read(pFlashCfg, ioMode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp)); - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 0, 0, 32, bank); - } - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Set flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((flashCfg->ioMode >> 4) & 0x01) == 1) { - /* Disable burst wrap ,just return */ - return; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->burstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->burstWrapDataMode; - dummyClks = flashCfg->burstWrapCmdDmyClk; - cmd = flashCfg->burstWrapCmd; - wrapData = flashCfg->burstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Disable flash burst wrap config - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint8_t cmd, dummyClks; - uint32_t wrapData; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->deBurstWrapDataMode; - flashCmd.dataMode = (SF_Ctrl_Data_Mode_Type)flashCfg->deBurstWrapDataMode; - dummyClks = flashCfg->deBurstWrapCmdDmyClk; - cmd = flashCfg->deBurstWrapCmd; - wrapData = flashCfg->deBurstWrapData; - ARCH_MemCpy4((uint32_t *)flashCtrlBuf, &wrapData, 4); - flashCmd.cmdBuf[0] = (cmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = 1; - - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set flash 24-bits or 32-bits addr mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param en32BitsAddr: Serial flash enable or disable 32-bits addr - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmd = 0; - - if ((flashCfg->ioMode & 0x20) == 0) { - return ERROR; - } - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_32bits_Addr_En(en32BitsAddr); - - if (en32BitsAddr) { - cmd = flashCfg->enter32BitsAddrCmd; - } else { - cmd = flashCfg->exit32BitsAddrCmd; - } - - flashCmd.cmdBuf[0] = (cmd << 24); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - SF_Ctrl_SendCmd(&flashCmd); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Software reset flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg) -{ - uint16_t cnt = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset enable */ - flashCmd.cmdBuf[0] = (flashCfg->resetEnCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - - /* Wait for write done */ - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > 20) { - return ERROR; - } - } - - SF_Ctrl_SendCmd(&flashCmd); - - /* Reset */ - flashCmd.cmdBuf[0] = (flashCfg->resetCmd) << 24; - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - SF_Ctrl_SendCmd(&flashCmd); - - arch_delay_us(50); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Reset flash continous read mode - * - * @param flashCfg: Serial flash parameter configuration pointer - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg) -{ - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Reset continous read */ - ARCH_MemSet(&flashCmd.cmdBuf[0], flashCfg->resetCreadCmd, 4); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = flashCfg->resetCreadCmdSize; - SF_Ctrl_SendCmd(&flashCmd); -} -#endif - -/****************************************************************************/ /** - * @brief Set I/D bus read flash configuration in flash controller - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: address to read/write - * @param len: data length to read/write - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, - uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank) -{ - uint8_t cmd, dummyClks; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t cmdValid = 1; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_IAHB); - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /*prepare command**/ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | addr; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = addr; - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } else { - flashCmd.cmdBuf[0] = (addr << 8) | flashCfg->cReadMode; - } - - cmdValid = 0; - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - flashCmd.nbData = len; - if (bank == SF_CTRL_FLASH_BANK0) { - SF_Ctrl_Flash_Read_Icache_Set(&flashCmd, cmdValid); - } else { - SF_Ctrl_Flash2_Read_Icache_Set(&flashCmd, cmdValid); - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Enable I/D bus read from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param bank: bank select type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, - uint8_t contRead, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - - stat = SFlash_Set_IDbus_Cfg(flashCfg, ioMode, contRead, 0, 32, bank); - - if (SUCCESS != stat) { - return stat; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Disable read from flash with IDbus - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -void ATTR_TCM_SECTION SFlash_IDbus_Read_Disable(void) -{ - //L1C_Cache_Read_Disable(); -} -#endif - -/****************************************************************************/ /** - * @brief Sflash enable RCV mode to recovery for erase while power drop - * - * @param pFlashCfg: Flash configuration pointer - * @param rCmd: Read RCV register cmd - * @param wCmd: Write RCV register cmd - * @param bitPos: RCV register bit pos - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos) -{ - BL_Err_Type stat; - uint32_t cnt = 0; - uint32_t tempVal = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) > 0) { - return SUCCESS; - } - - tempVal |= (uint32_t)(1 << bitPos); - stat = SFlash_Write_Enable(pFlashCfg); - - if (SUCCESS != stat) { - stat = ERROR; - } - - stat = SFlash_Write_Reg_With_Cmd(pFlashCfg, wCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - return stat; - } - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > 20000 * 3) { - return ERROR; - } - } - - stat = SFlash_Read_Reg_With_Cmd(pFlashCfg, rCmd, (uint8_t *)&tempVal, 1); - - if (SUCCESS != stat) { - stat = ERROR; - } - - if (((tempVal >> bitPos) & 0x01) <= 0) { - return ERROR; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Erase flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint32_t cnt = 0; - uint8_t cmd = 0; - uint8_t secOptMode = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - BL_Err_Type stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - cmd = pSecRegCfg->eraseCmd; - flashCmd.cmdBuf[0] = (cmd << 24) | (pSecRegCfg->blockNum << 12); - /* rwFlag don't care */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - SF_Ctrl_SendCmd(&flashCmd); - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(500); - cnt++; - - if (cnt > pFlashCfg->timeEsector * 3) { - return ERROR; - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Program flash security register one block - * - * @param pFlashCfg: Flash configuration pointer - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - BL_Err_Type stat; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - cmd = pSecRegCfg->programCmd; - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(pFlashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = 256 - addr % 256; - - if (curLen > len - i) { - curLen = len - i; - } - - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - - /* Prepare command */ - arch_memcpy_fast(flashCtrlBuf, data, curLen); - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(pFlashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > pFlashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash security register one block - * - * @param pSecRegCfg: Security register configuration pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type ATTR_TCM_SECTION SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd; - uint8_t secOptMode = 0; - uint8_t *data = pSecRegCfg->data; - uint32_t addr = pSecRegCfg->addr; - uint32_t len = pSecRegCfg->len; - uint32_t currentAddr = 0; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (pSecRegCfg->enterSecOptCmd != 0x00) { - secOptMode = 1; - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->enterSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - flashCmd.dummyClks = 1; - cmd = pSecRegCfg->readCmd; - - /* Read data */ - for (i = 0; i < len;) { - currentAddr = (pSecRegCfg->blockNum << 12) | addr; - /* Prepare command */ - flashCmd.cmdBuf[0] = (cmd << 24) | (currentAddr); - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - arch_memcpy_fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - if (secOptMode > 0) { - if (((uint32_t)(uintptr_t)&flashCmd) % 4 == 0) { - arch_memset4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - arch_memset(&flashCmd, 0, sizeof(flashCmd)); - } - - flashCmd.cmdBuf[0] = (pSecRegCfg->exitSecOptCmd << 24); - flashCmd.rwFlag = SF_CTRL_WRITE; - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: flash controller interface mode - * @param contRead: Wether enable cont read mode - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t curLen, i; - uint8_t cmd, dummyClks; - uint32_t timeOut = 0; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - uint8_t noReadModeCfg = 0; - uint8_t cReadSupport = 0; - uint8_t is32BitsAddr = 0; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode) { - cmd = flashCfg->fastReadCmd; - dummyClks = flashCfg->frDmyClk; - } else if (SF_CTRL_DO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDoCmd; - dummyClks = flashCfg->frDoDmyClk; - } else if (SF_CTRL_DIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_2_LINES; - flashCmd.dataMode = SF_CTRL_DATA_2_LINES; - cmd = flashCfg->fastReadDioCmd; - dummyClks = flashCfg->frDioDmyClk; - } else if (SF_CTRL_QO_MODE == ioMode) { - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQoCmd; - dummyClks = flashCfg->frQoDmyClk; - } else if (SF_CTRL_QIO_MODE == ioMode) { - flashCmd.addrMode = SF_CTRL_ADDR_4_LINES; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->fastReadQioCmd; - dummyClks = flashCfg->frQioDmyClk; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_READ; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - noReadModeCfg = flashCfg->cReadSupport & 0x02; - cReadSupport = flashCfg->cReadSupport & 0x01; - - if (noReadModeCfg == 0) { - /* Read mode must be set*/ - if (cReadSupport == 0) { - /* Not support cont read,but we still need set read mode(winbond 80dv)*/ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - /* Flash support cont read, setting depend on user parameter */ - if (contRead) { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= (flashCfg->cReadMode << 16); - } else { - flashCmd.cmdBuf[1] = (flashCfg->cReadMode << 24); - } - } else { - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[1] |= ((!flashCfg->cReadMode) << 16); - } else { - flashCmd.cmdBuf[1] = ((!flashCfg->cReadMode) << 24); - } - } - } - - flashCmd.addrSize++; - } - } - - flashCmd.dummyClks = dummyClks; - - /* Read data */ - for (i = 0; i < len;) { - /* Prepare command */ - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] |= (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - curLen = len - i; - - if (curLen >= NOR_FLASH_CTRL_BUF_SIZE) { - curLen = NOR_FLASH_CTRL_BUF_SIZE; - flashCmd.nbData = curLen; - } else { - /* Make sf_ctrl word read */ - flashCmd.nbData = ((curLen + 3) >> 2) << 2; - } - - SF_Ctrl_SendCmd(&flashCmd); - - timeOut = SFCTRL_BUSY_STATE_TIMEOUT; - - while (SET == SF_Ctrl_GetBusyState()) { - timeOut--; - - if (timeOut == 0) { - return TIMEOUT; - } - } - - ARCH_MemCpy_Fast(data, flashCtrlBuf, curLen); - - addr += curLen; - i += curLen; - data += curLen; - } - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param flashCfg: Serial flash parameter configuration pointer - * @param ioMode: progran mode:SPI mode or QPI mode - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, - SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len) -{ - uint8_t *const flashCtrlBuf = (uint8_t *)SF_CTRL_BUF_BASE; - uint32_t i = 0, curLen = 0; - uint32_t cnt = 0; - uint8_t is32BitsAddr = 0; - BL_Err_Type stat; - uint8_t cmd; - SF_Ctrl_Cmd_Cfg_Type flashCmd; - - if (((uintptr_t)&flashCmd) % 4 == 0) { - ARCH_MemSet4((uint32_t *)&flashCmd, 0, sizeof(flashCmd) / 4); - } else { - ARCH_MemSet(&flashCmd, 0, sizeof(flashCmd)); - } - - if (SF_CTRL_NIO_MODE == ioMode || SF_CTRL_DO_MODE == ioMode || SF_CTRL_DIO_MODE == ioMode) { - cmd = flashCfg->pageProgramCmd; - } else if (SF_CTRL_QIO_MODE == ioMode || SF_CTRL_QO_MODE == ioMode) { - flashCmd.addrMode = (SF_Ctrl_Addr_Mode_Type)flashCfg->qppAddrMode; - flashCmd.dataMode = SF_CTRL_DATA_4_LINES; - cmd = flashCfg->qpageProgramCmd; - } else { - return ERROR; - } - - is32BitsAddr = (flashCfg->ioMode & 0x20); - /* Prepare command */ - flashCmd.rwFlag = SF_CTRL_WRITE; - flashCmd.addrSize = 3; - - if (is32BitsAddr > 0) { - flashCmd.addrSize++; - } - - for (i = 0; i < len;) { - /* Write enable is needed for every program */ - stat = SFlash_Write_Enable(flashCfg); - - if (stat != SUCCESS) { - return stat; - } - - /* Get current programmed length within page size */ - curLen = flashCfg->pageSize - addr % flashCfg->pageSize; - - if (curLen > len - i) { - curLen = len - i; - } - - /* Prepare command */ - ARCH_MemCpy_Fast(flashCtrlBuf, data, curLen); - - if (is32BitsAddr > 0) { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr >> 8); - flashCmd.cmdBuf[1] = (addr << 24); - } else { - flashCmd.cmdBuf[0] = (cmd << 24) | (addr); - } - - flashCmd.nbData = curLen; - - SF_Ctrl_SendCmd(&flashCmd); - - /* Adjust address and programmed length */ - addr += curLen; - i += curLen; - data += curLen; - - /* Wait for write done */ - cnt = 0; - - while (SET == SFlash_Busy(flashCfg)) { - arch_delay_us(100); - cnt++; - - if (cnt > flashCfg->timePagePgm * 20) { - return ERROR; - } - } - } - - return SUCCESS; -} -#endif - -/*@} end of group SFLASH_Public_Functions */ - -/*@} end of group SFLASH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c deleted file mode 100644 index 4776ac4c74..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_spi.c +++ /dev/null @@ -1,1373 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_spi.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_spi.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup SPI - * @{ - */ - -/** @defgroup SPI_Private_Macros - * @{ - */ -#define SPI_TX_TIMEOUT_COUNT (320 * 1000) -#define SPI_RX_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group SPI_Private_Macros */ - -/** @defgroup SPI_Private_Types - * @{ - */ - -/*@} end of group SPI_Private_Types */ - -/** @defgroup SPI_Private_Variables - * @{ - */ -const uint32_t spiAddr[SPI_ID_MAX] = { SPI0_BASE, SPI1_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -static intCallback_Type *spiIntCbfArra[SPI_ID_MAX][SPI_INT_ALL] = { - { NULL } -}; -#endif - -/*@} end of group SPI_Private_Variables */ - -/** @defgroup SPI_Global_Variables - * @{ - */ - -/*@} end of group SPI_Global_Variables */ - -/** @defgroup SPI_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void SPI_IntHandler(SPI_ID_Type spiNo); -#endif - -/*@} end of group SPI_Private_Fun_Declaration */ - -/** @defgroup SPI_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief SPI interrupt common handler function - * - * @param spiNo: SPI ID type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -static void SPI_IntHandler(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - /* Transfer end interrupt,shared by both master and slave mode */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_END_MASK)) { - BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_END_CLR)); - - if (spiIntCbfArra[spiNo][SPI_INT_END] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_END](); - } - } - - /* TX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXF_MASK)) { - if (spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_TX_FIFO_REQ](); - } - } - - /* RX fifo ready interrupt(fifo count > fifo threshold) */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_RXF_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_RXF_MASK)) { - if (spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_RX_FIFO_REQ](); - } - } - - /* Slave mode transfer time-out interrupt,triggered when bus is idle for the given value */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_STO_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_STO_MASK)) { - BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_STO_CLR)); - - if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_SLAVE_TIMEOUT](); - } - } - - /* Slave mode tx underrun error interrupt,trigged when tx is not ready during transfer */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_TXU_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_TXU_MASK)) { - BL_WR_REG(SPIx, SPI_INT_STS, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_TXU_CLR)); - - if (spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_SLAVE_UNDERRUN](); - } - } - - /* TX/RX fifo overflow/underflow interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, SPI_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, SPI_CR_SPI_FER_MASK)) { - if (spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR] != NULL) { - spiIntCbfArra[spiNo][SPI_INT_FIFO_ERROR](); - } - } -} -#endif - -/*@} end of group SPI_Private_Functions */ - -/** @defgroup SPI_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief SPI initialization function - * - * @param spiNo: SPI ID type - * @param spiCfg: SPI configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_Init(SPI_ID_Type spiNo, SPI_CFG_Type *spiCfg) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_SLAVE_PIN_TYPE(slavePin)); - CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(spiCfg->mod)); - CHECK_PARAM(IS_SPI_BYTE_INVERSE_TYPE(spiCfg->byteSequence)); - CHECK_PARAM(IS_SPI_BIT_INVERSE_TYPE(spiCfg->bitSequence)); - CHECK_PARAM(IS_SPI_CLK_PHASE_INVERSE_TYPE(spiCfg->clkPhaseInv)); - CHECK_PARAM(IS_SPI_CLK_POLARITY_TYPE(spiCfg->clkPolarity)); - - /* Disable clock gate when use SPI0 */ - if (SPI0_ID == spiNo) { - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_SPI); - } - - /* spi config */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_EN, spiCfg->deglitchEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_S_3PIN_MODE, spiCfg->slavePin); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_M_CONT_EN, spiCfg->continuousEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BYTE_INV, spiCfg->byteSequence); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_BIT_INV, spiCfg->bitSequence); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_PH, (spiCfg->clkPhaseInv + 1) & 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_SCLK_POL, spiCfg->clkPolarity); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, spiCfg->frameSize); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(SPI0_IRQn, SPI0_IRQHandler); - Interrupt_Handler_Register(SPI1_IRQn, SPI1_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI set default value of all registers function - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_DeInit(SPI_ID_Type spiNo) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - if (SPI0_ID == spiNo) { - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SPI); - } else if (SPI0_MM_ID == spiNo) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_SPI); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Length of data phase1/0,start/stop condition and interval between frame initialization - * function - * - * @param spiNo: SPI ID type - * @param clockCfg: Clock configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClockConfig(SPI_ID_Type spiNo, SPI_ClockCfg_Type *clockCfg) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Configure length of data phase1/0 and start/stop condition */ - tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, clockCfg->startLen - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, clockCfg->stopLen - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, clockCfg->dataPhase0Len - 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, clockCfg->dataPhase1Len - 1); - BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); - - /* Configure length of interval between frame */ - tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); - BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, clockCfg->intervalLen - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI configure fifo function - * - * @param spiNo: SPI ID type - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_FifoConfig(SPI_ID_Type spiNo, SPI_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Set fifo threshold value */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_TX_FIFO_TH, fifoCfg->txFifoThreshold); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_RX_FIFO_TH, fifoCfg->rxFifoThreshold); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable dma function */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_TX_EN, fifoCfg->txFifoDmaEnable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_DMA_RX_EN, fifoCfg->rxFifoDmaEnable); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set SPI Frame Size - * - * @param spiNo: SPI ID type - * @param frameSize: FrameSize Type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetFrameSize(SPI_ID_Type spiNo, SPI_FrameSize_Type frameSize) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_SLAVE_PIN_TYPE(frameSize)); - - /* The SPI must be clear fifo first */ - SPI_ClrRxFifo(spiNo); - SPI_ClrTxFifo(spiNo); - - /* set framsize*/ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE, frameSize); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set SPI SCK Clcok - * - * @param spiNo: SPI ID type - * @param clk: Clk - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetClock(SPI_ID_Type spiNo, uint32_t clk) -{ - uint32_t glb_div = 0, spi_div = 0; - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - if (clk > 80000000) { - clk = 80000000; - } else if (clk < 9766) { - clk = 9766; - } - - if (clk >= 312500) { - glb_div = 0; - spi_div = 80000000 / clk - 1; - } else { - glb_div = 31; - spi_div = 2500000 / clk - 1; - } - - if (spiNo == SPI0_ID) { - GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, glb_div); - } else { - GLB_Set_DSP_SPI_CLK(ENABLE, GLB_DSP_SPI_CLK_DSP_MUXPLL_160M, glb_div); - } - - /* Configure length of data phase1/0 and start/stop condition */ - tmpVal = BL_RD_REG(SPIx, SPI_PRD_0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_S, spi_div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_P, spi_div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_0, spi_div); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_D_PH_1, spi_div); - BL_WR_REG(SPIx, SPI_PRD_0, tmpVal); - - tmpVal = BL_RD_REG(SPIx, SPI_PRD_1); - BL_WR_REG(SPIx, SPI_PRD_1, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_PRD_I, spi_div)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable spi transfer - * - * @param spiNo: SPI ID type - * @param modeType: Master or slave mode select - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_Enable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); - - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - - if (modeType != SPI_WORK_MODE_SLAVE) { - /* master mode */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); - } else { - /* slave mode */ - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); - tmpVal = BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); - } - - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable spi transfer - * - * @param spiNo: SPI ID type - * @param modeType: Master or slave mode select - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_Disable(SPI_ID_Type spiNo, SPI_WORK_MODE_Type modeType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_WORK_MODE_TYPE(modeType)); - - /* close master and slave */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_M_EN); - tmpVal = BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_S_EN); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set time-out value to trigger interrupt when spi bus is idle for the given value - * - * @param spiNo: SPI ID type - * @param value: Time value - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetTimeOutValue(SPI_ID_Type spiNo, uint16_t value) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Set time-out value */ - tmpVal = BL_RD_REG(SPIx, SPI_STO_VALUE); - BL_WR_REG(SPIx, SPI_STO_VALUE, BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_STO_VALUE, value - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Set de-glitch function cycle count value - * - * @param spiNo: SPI ID type - * @param cnt: De-glitch function cycle count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SetDeglitchCount(SPI_ID_Type spiNo, uint8_t cnt) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Set count value */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_DEG_CNT, cnt); - BL_WR_REG(SPIx, SPI_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable rx data ignore function and set start/stop point - * - * @param spiNo: SPI ID type - * @param startPoint: Start point - * @param stopPoint: Stop point - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_RxIgnoreEnable(SPI_ID_Type spiNo, uint8_t startPoint, uint8_t stopPoint) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Enable rx ignore function */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - BL_WR_REG(SPIx, SPI_CONFIG, BL_SET_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); - - /* Set start and stop point */ - tmpVal = startPoint << SPI_CR_SPI_RXD_IGNR_S_POS | stopPoint; - BL_WR_REG(SPIx, SPI_RXD_IGNR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable rx data ignore function - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_RxIgnoreDisable(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Disable rx ignore function */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - BL_WR_REG(SPIx, SPI_CONFIG, BL_CLR_REG_BIT(tmpVal, SPI_CR_SPI_RXD_IGNR_EN)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear tx fifo and tx fifo overflow/underflow status - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClrTxFifo(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Clear tx fifo */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_TX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear rx fifo and rx fifo overflow/underflow status - * - * @param spiNo: SPI ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClrRxFifo(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - BL_WR_REG(SPIx, SPI_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, SPI_RX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Clear spi interrupt status - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ClrIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Clear certain or all interrupt */ - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - if (SPI_INT_ALL == intType) { - tmpVal |= 0x1f << SPI_CR_SPI_END_CLR_POS; - } else { - tmpVal |= 1 << (intType + SPI_CR_SPI_END_CLR_POS); - } - - BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI mask or unmask certain or all interrupt - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * @param intMask: SPI interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_IntMask(SPI_ID_Type spiNo, SPI_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - /* Mask or unmask certain or all interrupt */ - if (SPI_INT_ALL == intType) { - if (MASK == intMask) { - tmpVal |= 0x3f << SPI_CR_SPI_END_MASK_POS; - } else { - tmpVal &= ~(0x3f << SPI_CR_SPI_END_MASK_POS); - } - } else { - if (MASK == intMask) { - tmpVal |= 1 << (intType + SPI_CR_SPI_END_MASK_POS); - } else { - tmpVal &= ~(1 << (intType + SPI_CR_SPI_END_MASK_POS)); - } - } - - /* Write back */ - BL_WR_REG(SPIx, SPI_INT_STS, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Install spi interrupt callback function - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -BL_Err_Type SPI_Int_Callback_Install(SPI_ID_Type spiNo, SPI_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_INT_TYPE(intType)); - - spiIntCbfArra[spiNo][intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief SPI send datas - * - * @param spiNo: SPI ID type - * @param buff: Buffer of datas - * @param length: Length of buffer - * @param timeoutType: Enable or disable timeout judgment - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SendData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType) -{ - uint32_t tmpVal; - uint32_t txLen = 0; - uint32_t rData; - uint32_t frameSize = 0; - uint32_t SPIx = spiAddr[spiNo]; - uint32_t timeoutCnt = SPI_TX_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); - - /* Get fifo valid width */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE); - - switch (frameSize) { - case 0: - - tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)buff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)buff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 1: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)buff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)buff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 2: - - /* Same as case 3 */ - case 3: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)buff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)buff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - rData |= BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI receive datas - * - * @param spiNo: SPI ID type - * @param buff: Buffer of datas - * @param length: Length of buffer - * @param timeoutType: Enable or disable timeout judgment - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_ReceiveData(SPI_ID_Type spiNo, void *buff, uint32_t length, SPI_Timeout_Type timeoutType) -{ - uint32_t tmpVal; - uint32_t rxLen = 0; - uint32_t frameSize = 0; - uint32_t SPIx = spiAddr[spiNo]; - uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); - - /* Get fifo valid width */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE); - - switch (frameSize) { - case 0: - - tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; - - /* Fill tx fifo with 0 */ - for (rxLen = 0; rxLen < tmpVal; rxLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive data and send the rest of the data 0 */ - for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive the rest of the data */ - for (; rxLen < length; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 1: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2); - - /* Fill tx fifo with 0 */ - for (rxLen = 0; rxLen < tmpVal; rxLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive data and send the rest of the data 0 */ - for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive the rest of the data */ - for (; rxLen < length; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 2: - - /* Same as case 3 */ - case 3: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4); - - /* Fill tx fifo with 0 */ - for (rxLen = 0; rxLen < tmpVal; rxLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive data and send the rest of the data 0 */ - for (rxLen = 0; rxLen < length - tmpVal; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, 0); - } - - /* Wait receive the rest of the data */ - for (; rxLen < length; rxLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)buff)[rxLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief SPI send and receive datas at the same time - * - * @param spiNo: SPI ID type - * @param sendBuff: Buffer of datas to send - * @param recvBuff: Buffer of datas received - * @param length: Length of buffer - * @param timeoutType: Enable or disable timeout judgment - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type SPI_SendRecvData(SPI_ID_Type spiNo, void *sendBuff, void *recvBuff, uint32_t length, SPI_Timeout_Type timeoutType) -{ - uint32_t tmpVal; - uint32_t txLen = 0; - uint32_t frameSize = 0; - uint32_t SPIx = spiAddr[spiNo]; - uint32_t timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_TIMEOUT_TYPE(timeoutType)); - - /* Get fifo valid width */ - tmpVal = BL_RD_REG(SPIx, SPI_CONFIG); - frameSize = BL_GET_REG_BITS_VAL(tmpVal, SPI_CR_SPI_FRAME_SIZE); - - switch (frameSize) { - case 0: - - tmpVal = length <= (SPI_TX_FIFO_SIZE) ? length : SPI_TX_FIFO_SIZE; - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)sendBuff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint8_t *)sendBuff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint8_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 1: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 2) ? length : (SPI_TX_FIFO_SIZE / 2); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)sendBuff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint16_t *)sendBuff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint16_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - case 2: - - /* Same as case 3 */ - case 3: - - tmpVal = length <= (SPI_TX_FIFO_SIZE / 4) ? length : (SPI_TX_FIFO_SIZE / 4); - - /* Fill tx fifo */ - for (; txLen < tmpVal; txLen++) { - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)sendBuff)[txLen]); - } - - /* Wait receive data and send the rest of the data */ - for (; txLen < length; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)recvBuff)[txLen - tmpVal] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - BL_WR_REG(SPIx, SPI_FIFO_WDATA, ((uint32_t *)sendBuff)[txLen]); - } - - /* Wait receive the rest of the data */ - for (txLen = 0; txLen < tmpVal; txLen++) { - timeoutCnt = SPI_RX_TIMEOUT_COUNT; - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT) == 0) { - if (timeoutType) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - ((uint32_t *)recvBuff)[length - tmpVal + txLen] = BL_RD_REG(SPIx, SPI_FIFO_RDATA); - } - - break; - - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Get tx fifo available count value function - * - * @param spiNo: SPI ID type - * - * @return Count value - * -*******************************************************************************/ -uint8_t SPI_GetTxFifoCount(SPI_ID_Type spiNo) -{ - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Get count value */ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get rx fifo available count value function - * - * @param spiNo: SPI ID type - * - * @return Count value - * -*******************************************************************************/ -uint8_t SPI_GetRxFifoCount(SPI_ID_Type spiNo) -{ - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Get count value */ - return BL_GET_REG_BITS_VAL(BL_RD_REG(SPIx, SPI_FIFO_CONFIG_1), SPI_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get spi interrupt status - * - * @param spiNo: SPI ID type - * @param intType: SPI interrupt type - * - * @return Status of interrupt - * -*******************************************************************************/ -BL_Sts_Type SPI_GetIntStatus(SPI_ID_Type spiNo, SPI_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_INT_TYPE(intType)); - - /* Get certain or all interrupt status */ - tmpVal = BL_RD_REG(SPIx, SPI_INT_STS); - - if (SPI_INT_ALL == intType) { - if ((tmpVal & 0x3f) != 0) { - return SET; - } else { - return RESET; - } - } else { - if ((tmpVal & (1U << intType)) != 0) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Get indicator of spi bus busy - * - * @param spiNo: SPI ID type - * - * @return Status of spi bus - * -*******************************************************************************/ -BL_Sts_Type SPI_GetBusyStatus(SPI_ID_Type spiNo) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - - /* Get bus busy status */ - tmpVal = BL_RD_REG(SPIx, SPI_BUS_BUSY); - - if (BL_IS_REG_BIT_SET(tmpVal, SPI_STS_SPI_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get tx/rx fifo overflow or underflow status - * - * @param spiNo: SPI ID type - * @param fifoSts: Select tx/rx overflow or underflow - * - * @return Status of tx/rx fifo - * -*******************************************************************************/ -BL_Sts_Type SPI_GetFifoStatus(SPI_ID_Type spiNo, SPI_FifoStatus_Type fifoSts) -{ - uint32_t tmpVal; - uint32_t SPIx = spiAddr[spiNo]; - - /* Check the parameters */ - CHECK_PARAM(IS_SPI_ID_TYPE(spiNo)); - CHECK_PARAM(IS_SPI_FIFOSTATUS_TYPE(fifoSts)); - - /* Get tx/rx fifo overflow or underflow status */ - tmpVal = BL_RD_REG(SPIx, SPI_FIFO_CONFIG_0); - - if ((tmpVal & (1U << (fifoSts + SPI_TX_FIFO_OVERFLOW_POS))) != 0) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief SPI0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SPI0_IRQHandler(void) -{ - SPI_IntHandler(SPI0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief SPI1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void SPI1_IRQHandler(void) -{ - SPI_IntHandler(SPI0_MM_ID); -} -#endif - -/*@} end of group SPI_Public_Functions */ - -/*@} end of group SPI */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c deleted file mode 100644 index 8d1e6211ea..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_timer.c +++ /dev/null @@ -1,1317 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_timer.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_timer.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TIMER - * @{ - */ - -/** @defgroup TIMER_Private_Macros - * @{ - */ -#define TIMER_MAX_MATCH 3 - -/*@} end of group TIMER_Private_Macros */ - -/** @defgroup TIMER_Private_Types - * @{ - */ - -/*@} end of group TIMER_Private_Types */ - -/** @defgroup TIMER_Private_Variables - * @{ - */ -static const uint32_t timerAddr[TIMER_ID_MAX] = { TIMER0_BASE, TIMER1_BASE }; -#ifndef BFLB_USE_HAL_DRIVER -intCallback_Type *timerIntCbfArra[TIMER_ID_MAX][TIMER_CH_MAX][TIMER_INT_ALL] = { NULL }; -intCallback_Type *wdtIntCbfArra[WDT_ID_MAX][WDT_INT_ALL] = { NULL }; -#endif - -/*@} end of group TIMER_Private_Variables */ - -/** @defgroup TIMER_Global_Variables - * @{ - */ - -/*@} end of group TIMER_Global_Variables */ - -/** @defgroup TIMER_Private_Fun_Declaration - * @{ - */ -#ifndef BFLB_USE_HAL_DRIVER -static void TIMER_IntHandler(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh); -#endif - -/*@} end of group TIMER_Private_Fun_Declaration */ - -/** @defgroup TIMER_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief TIMER interrupt common handler function - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER_IntHandler(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t intId; - uint32_t tmpVal; - uint32_t tmpAddr; - uint32_t TIMERx = timerAddr[timerId]; - - intId = BL_RD_WORD(TIMERx + TIMER_TSR2_OFFSET + 4 * timerCh); - tmpAddr = TIMERx + TIMER_TICR2_OFFSET + 4 * timerCh; - tmpVal = BL_RD_WORD(tmpAddr); - - /* Comparator 0 match interrupt */ - if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_0)) { - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_0)); - - if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_0] != NULL) { - /* Call the callback function */ - timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_0](); - } - } - - /* Comparator 1 match interrupt */ - if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_1)) { - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_1)); - - if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_1] != NULL) { - /* Call the callback function */ - timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_1](); - } - } - - /* Comparator 2 match interrupt */ - if (BL_IS_REG_BIT_SET(intId, TIMER_TSR2_2)) { - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TSR2_2)); - - if (timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_2] != NULL) { - /* Call the callback function */ - timerIntCbfArra[timerId][timerCh][TIMER_INT_COMP_2](); - } - } -} -#endif - -/****************************************************************************/ /** - * @brief Get the specified channel and match comparator value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER comparator ID type - * - * @return Match comapre register value - * -*******************************************************************************/ -uint32_t TIMER_GetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - tmpVal = BL_RD_WORD(TIMERx + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo)); - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER set specified channel and comparator compare value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER comparator ID type - * @param val: TIMER match compare register value - * - * @return None - * -*******************************************************************************/ -void TIMER_SetCompValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo, uint32_t val) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - BL_WR_WORD(TIMERx + TIMER_TMR2_0_OFFSET + 4 * (TIMER_MAX_MATCH * timerCh + cmpNo), val); -} - -/****************************************************************************/ /** - * @brief TIMER enable or disable compare value effect immediately after update - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void TIMER_CompValueEffectImmediately(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCMR); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_ALIGN, 1 - enable); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER3_ALIGN, 1 - enable); - } - - BL_WR_REG(TIMERx, TIMER_TCMR, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER get the specified channel count value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return TIMER count register value - * -*******************************************************************************/ -uint32_t TIMER_GetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t tmpAddr; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpAddr = TIMERx + TIMER_TCR2_OFFSET+ 4 * timerCh; - tmpVal = BL_RD_WORD(tmpAddr); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER reset count value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_ResetCounterValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCER); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCR2_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCR2_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCR3_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCR3_CNT_CLR); - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); - } -} - -/****************************************************************************/ /** - * @brief TIMER get specified channel and comparator match status - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER comparator ID type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type TIMER_GetMatchStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) -{ - uint32_t tmpVal; - BL_Sts_Type bitStatus = RESET; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - tmpVal = BL_RD_WORD(TIMERx + TIMER_TSR2_OFFSET + 4 * timerCh); - - switch (cmpNo) { - case TIMER_COMP_ID_0: - bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_0) ? SET : RESET; - break; - - case TIMER_COMP_ID_1: - bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_1) ? SET : RESET; - break; - - case TIMER_COMP_ID_2: - bitStatus = BL_IS_REG_BIT_SET(tmpVal, TIMER_TSR3_2) ? SET : RESET; - break; - - default: - break; - } - - return bitStatus; -} - -/****************************************************************************/ /** - * @brief TIMER get specified channel preload value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return Preload register value - * -*******************************************************************************/ -uint32_t TIMER_GetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - return BL_RD_WORD(TIMERx + TIMER_TPLVR2_OFFSET + 4 * timerCh); -} - -/****************************************************************************/ /** - * @brief TIMER set preload register low 32bits value - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param val: Preload register low 32bits value - * - * @return None - * -*******************************************************************************/ -void TIMER_SetPreloadValue(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, uint32_t val) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - BL_WR_WORD(TIMERx + TIMER_TPLVR2_OFFSET + 4 * timerCh, val); -} - -/****************************************************************************/ /** - * @brief TIMER set preload trigger source,COMP0,COMP1,COMP2 or None - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param plSrc: TIMER preload source type - * - * @return None - * -*******************************************************************************/ -void TIMER_SetPreloadTrigSrc(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_PreLoad_Trig_Type plSrc) -{ - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(plSrc)); - - BL_WR_WORD(TIMERx + TIMER_TPLCR2_OFFSET + 4 * timerCh, plSrc); -} - -/****************************************************************************/ /** - * @brief TIMER set count mode:preload or free run - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param countMode: TIMER count mode: TIMER_COUNT_PRELOAD or TIMER_COUNT_FREERUN - * - * @return None - * -*******************************************************************************/ -void TIMER_SetCountMode(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_CountMode_Type countMode) -{ - uint32_t tmpval; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(countMode)); - - tmpval = BL_RD_WORD(TIMERx + TIMER_TCMR_OFFSET); - tmpval &= (~(1 << (timerCh + 1))); - tmpval |= (countMode << (timerCh + 1)); - - BL_WR_WORD(TIMERx + TIMER_TCMR_OFFSET, tmpval); -} - -/****************************************************************************/ /** - * @brief TIMER clear interrupt status - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param cmpNo: TIMER macth comparator ID type - * - * @return None - * -*******************************************************************************/ -void TIMER_ClearIntStatus(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_Comp_ID_Type cmpNo) -{ - uint32_t tmpAddr; - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_COMP_ID_TYPE(cmpNo)); - - tmpAddr = TIMERx + TIMER_TICR2_OFFSET + 4 * timerCh; - - tmpVal = BL_RD_WORD(tmpAddr); - tmpVal |= (1 << cmpNo); - - BL_WR_WORD(tmpAddr, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER initialization function - * - * @param timerId: Timer ID type - * @param timerCfg: TIMER configuration structure pointer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TIMER_Init(TIMER_ID_Type timerId, TIMER_CFG_Type *timerCfg) -{ - TIMER_Chan_Type timerCh = timerCfg->timerCh; - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(timerCfg->clkSrc)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCfg->timerCh)); - CHECK_PARAM(IS_TIMER_PRELOAD_TRIG_TYPE(timerCfg->plTrigSrc)); - CHECK_PARAM(IS_TIMER_COUNTMODE_TYPE(timerCfg->countMode)); - - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_TIMER); - - /* Configure timer clock source */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCCR); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_2, timerCfg->clkSrc); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_3, timerCfg->clkSrc); - } - - BL_WR_REG(TIMERx, TIMER_TCCR, tmpVal); - - /* Configure timer clock division */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR2, timerCfg->clockDivision); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_TCDR3, timerCfg->clockDivision); - } - - BL_WR_REG(TIMERx, TIMER_TCDR, tmpVal); - - /* Configure timer count mode: preload or free run */ - TIMER_SetCountMode(timerId, timerCh, timerCfg->countMode); - - /* Configure timer preload trigger src */ - TIMER_SetPreloadTrigSrc(timerId, timerCh, timerCfg->plTrigSrc); - - if (timerCfg->countMode == TIMER_COUNT_PRELOAD) { - /* Configure timer preload value */ - TIMER_SetPreloadValue(timerId, timerCh, timerCfg->preLoadVal); - - /* Configure match compare values */ - if (timerCfg->matchVal0 > 1 + timerCfg->preLoadVal) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); - } - - if (timerCfg->matchVal1 > 1 + timerCfg->preLoadVal) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); - } - - if (timerCfg->matchVal2 > 1 + timerCfg->preLoadVal) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); - } - } else { - /* Configure match compare values */ - if (timerCfg->matchVal0 > 1) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_0, timerCfg->matchVal0); - } - - if (timerCfg->matchVal1 > 1) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_1, timerCfg->matchVal1); - } - - if (timerCfg->matchVal2 > 1) { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2 - 2); - } else { - TIMER_SetCompValue(timerId, timerCh, TIMER_COMP_ID_2, timerCfg->matchVal2); - } - } - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(TIMER0_CH0_IRQn, TIMER0_CH0_IRQHandler); - Interrupt_Handler_Register(TIMER0_CH1_IRQn, TIMER0_CH1_IRQHandler); - Interrupt_Handler_Register(TIMER1_CH0_IRQn, TIMER1_CH0_IRQHandler); - Interrupt_Handler_Register(TIMER1_CH1_IRQn, TIMER1_CH1_IRQHandler); - -#endif - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TIMER set default value of all registers function - * - * @param timerId: TIMER ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type TIMER_DeInit(TIMER_ID_Type timerId) -{ - if (TIMER0_ID == timerId) { - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_TIMER); - } else if (TIMER1_ID == timerId) { - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_TIMER); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief TIMER enable one channel function - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_Enable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCER); - tmpVal |= (1 << (timerCh + 1)); - - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER disable one channel function - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_Disable(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCER); - tmpVal &= (~(1 << (timerCh + 1))); - - BL_WR_REG(TIMERx, TIMER_TCER, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER mask or unmask certain or all interrupt - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param intType: TIMER interrupt type - * @param intMask: TIMER interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt - * - * @return None - * -*******************************************************************************/ -void TIMER_IntMask(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpAddr; - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpAddr = TIMERx + TIMER_TIER2_OFFSET + 4 * timerCh; - tmpVal = BL_RD_WORD(tmpAddr); - - switch (intType) { - case TIMER_INT_COMP_0: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_0)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_0)); - } - - break; - - case TIMER_INT_COMP_1: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_1)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_1)); - } - - break; - - case TIMER_INT_COMP_2: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_2)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_2)); - } - - break; - - case TIMER_INT_ALL: - if (intMask == UNMASK) { - /* Enable this interrupt */ - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_0)); - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_1)); - BL_WR_WORD(tmpAddr, BL_SET_REG_BIT(tmpVal, TIMER_TIER3_2)); - } else { - /* Disable this interrupt */ - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_0)); - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_1)); - BL_WR_WORD(tmpAddr, BL_CLR_REG_BIT(tmpVal, TIMER_TIER3_2)); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief TIMER set gpio polarity - * - * @param timerId: Timer ID type - * @param timerCh: TIMER channel type - * @param polarity: TIMER GPIO polarity - * - * @return None - * -*******************************************************************************/ -void TIMER_GPIOSetPolarity(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh, TIMER_GPIO_Polarity_Type polarity) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_GPIO_INV, polarity); - } else { - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER3_GPIO_INV, polarity); - } - - BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER channel 0 enable or disable measure gpio pulse width function - * - * @param timerId: Timer ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void TIMER_CH0_SetMeasurePulseWidth(TIMER_ID_Type timerId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER2_GPIO_EN, enable); - BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER channel 0 get gpio pulse width value function - * - * @param timerId: Timer ID type - * - * @return Pulse width - * -*******************************************************************************/ -uint32_t TIMER_CH0_GetMeasurePulseWidth(TIMER_ID_Type timerId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - - do { - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - } while (!BL_IS_REG_BIT_SET(tmpVal, TIMER_GPIO_LAT_OK)); - - return (BL_RD_REG(TIMERx, TIMER_GPIO_LAT2) - BL_RD_REG(TIMERx, TIMER_GPIO_LAT1)); -} - -/****************************************************************************/ /** - * @brief TIMER force clock division - * - * @param timerId: Timer ID type - * @param timerChan: TIMER channel type - * - * @return None - * -*******************************************************************************/ -void TIMER_ForceClockDivision(TIMER_ID_Type timerId, TIMER_Chan_Type timerCh) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[timerId]; - - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan)); - - /* write 0 after write 1 to force clock division */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCDR2_FORCE); - } else { - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_TCDR3_FORCE); - } - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - if (timerCh == TIMER_CH0) { - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCDR2_FORCE); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_TCDR3_FORCE); - } - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER install interrupt callback - * - * @param timerId: Timer ID type - * @param timerChan: TIMER channel type - * @param intType: TIMER interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER_Int_Callback_Install(TIMER_ID_Type timerId, TIMER_Chan_Type timerChan, TIMER_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_TIMER_ID_TYPE(timerId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerChan)); - CHECK_PARAM(IS_TIMER_INT_TYPE(intType)); - - timerIntCbfArra[timerId][timerChan][intType] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief TIMER set watchdog clock source and clock division - * - * @param wdtId: Watchdog ID type - * @param clkSrc: Watchdog timer clock source type - * @param div: Watchdog timer clock division value - * - * @return None - * -*******************************************************************************/ -void WDT_Set_Clock(WDT_ID_Type wdtId, TIMER_ClkSrc_Type clkSrc, uint8_t div) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_TIMER_CLKSRC_TYPE(clkSrc)); - - /* Configure watchdog timer clock source */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCCR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT, clkSrc); - BL_WR_REG(TIMERx, TIMER_TCCR, tmpVal); - - /* Configure watchdog timer clock divison */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WCDR, div); - BL_WR_REG(TIMERx, TIMER_TCDR, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER get watchdog match compare value - * - * @param wdtId: Watchdog ID type - * - * @return Watchdog match comapre register value - * -*******************************************************************************/ -uint16_t WDT_GetMatchValue(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Get watchdog timer match register value */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WMR); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, TIMER_WMR); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER set watchdog match compare value - * - * @param wdtId: Watchdog ID type - * @param val: Watchdog match compare value - * - * @return None - * -*******************************************************************************/ -void WDT_SetCompValue(WDT_ID_Type wdtId, uint16_t val) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Set watchdog timer match register value */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WMR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WMR, val); - BL_WR_REG(TIMERx, TIMER_WMR, tmpVal); -} - -/****************************************************************************/ /** - * @brief Watchdog enable or disable compare value effect immediately after update - * - * @param wdtId: Watchdog ID type - * @param enable: Enable or disable - * - * @return None - * -*******************************************************************************/ -void WDT_CompValueEffectImmediately(WDT_ID_Type wdtId, BL_Fun_Type enable) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WMR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WDT_ALIGN, 1 - enable); - BL_WR_REG(TIMERx, TIMER_WMR, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER get watchdog count register value - * - * @param wdtId: Watchdog ID type - * - * @return Watchdog count register value - * -*******************************************************************************/ -uint16_t WDT_GetCounterValue(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Get watchdog timer count register value */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WVR); - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief TIMER reset watchdog count register value - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_ResetCounterValue(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - /* Reset watchdog timer count register value */ - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WCR); - - /* Set watchdog counter reset register bit0 to 1 */ - BL_WR_REG(TIMERx, TIMER_WCR, BL_SET_REG_BIT(tmpVal, TIMER_WCR)); -} - -/****************************************************************************/ /** - * @brief TIMER get watchdog reset status - * - * @param wdtId: Watchdog ID type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type WDT_GetResetStatus(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Get watchdog status register */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WSR); - - return (BL_IS_REG_BIT_SET(tmpVal, TIMER_WTS)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief TIMER clear watchdog reset status - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_ClearResetStatus(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WSR); - - /* Set watchdog status register */ - BL_WR_REG(TIMERx, TIMER_WSR, BL_CLR_REG_BIT(tmpVal, TIMER_WTS)); -} - -/****************************************************************************/ /** - * @brief TIMER enable watchdog function - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_Enable(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(TIMER0_WDT_IRQn, TIMER0_WDT_IRQHandler); - Interrupt_Handler_Register(TIMER1_WDT_IRQn, TIMER1_WDT_IRQHandler); -#endif - - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WMER); - - BL_WR_REG(TIMERx, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WE)); -} - -/****************************************************************************/ /** - * @brief Watchdog timer disable function - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_Disable(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - WDT_ENABLE_ACCESS(TIMERx); - - tmpVal = BL_RD_REG(TIMERx, TIMER_WMER); - - BL_WR_REG(TIMERx, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WE)); -} - -/****************************************************************************/ /** - * @brief Watchdog timer disable function - * - * @param wdtId: Watchdog ID type - * - * @return None - * -*******************************************************************************/ -void WDT_ForceClockDivision(WDT_ID_Type wdtId) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - - /* write 0 after write 1 to force clock division */ - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - tmpVal = BL_SET_REG_BIT(tmpVal, TIMER_WCDR_FORCE); - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); - - tmpVal = BL_RD_REG(TIMERx, TIMER_TCDR_FORCE); - - tmpVal = BL_CLR_REG_BIT(tmpVal, TIMER_WCDR_FORCE); - - BL_WR_REG(TIMERx, TIMER_TCDR_FORCE, tmpVal); -} - -/****************************************************************************/ /** - * @brief Watchdog timer mask or unmask certain or all interrupt - * - * @param wdtId: Watchdog ID type - * @param intType: Watchdog interrupt type - * @param intMask: Watchdog interrupt mask value:MASK:disbale interrupt.UNMASK:enable interrupt - * - * @return None - * -*******************************************************************************/ -void WDT_IntMask(WDT_ID_Type wdtId, WDT_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_WDT_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - WDT_ENABLE_ACCESS(TIMERx); - - /* Deal with watchdog match/interrupt enable register, - WRIE:watchdog reset/interrupt enable */ - tmpVal = BL_RD_REG(TIMERx, TIMER_WMER); - - switch (intType) { - case WDT_INT: - if (intMask == UNMASK) { - /* Enable this interrupt */ - /* 0 means generates a watchdog interrupt, - a watchdog timer reset is not generated*/ - BL_WR_REG(TIMERx, TIMER_WMER, BL_CLR_REG_BIT(tmpVal, TIMER_WRIE)); - } else { - /* Disable this interrupt */ - /* 1 means generates a watchdog timer reset, - a watchdog interrupt is not generated*/ - BL_WR_REG(TIMERx, TIMER_WMER, BL_SET_REG_BIT(tmpVal, TIMER_WRIE)); - } - - break; - - default: - break; - } -} - -/****************************************************************************/ /** - * @brief Watchdog install interrupt callback - * - * @param wdtId: Watchdog ID type - * @param wdtInt: Watchdog interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void WDT_Int_Callback_Install(WDT_ID_Type wdtId, WDT_INT_Type wdtInt, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_WDT_INT_TYPE(wdtInt)); - - wdtIntCbfArra[wdtId][wdtInt] = cbFun; -} -#endif - -/****************************************************************************/ /** - * @brief Watchdog set gpio polarity - * - * @param wdtId: Watchdog ID type - * @param polarity: Watchdog GPIO polarity - * - * @return None - * -*******************************************************************************/ -void WDT_GPIOSetPolarity(WDT_ID_Type wdtId, TIMER_GPIO_Polarity_Type polarity) -{ - uint32_t tmpVal; - uint32_t TIMERx = timerAddr[wdtId]; - - /* Check the parameters */ - CHECK_PARAM(IS_WDT_ID_TYPE(wdtId)); - CHECK_PARAM(IS_TIMER_CHAN_TYPE(timerCh)); - - tmpVal = BL_RD_REG(TIMERx, TIMER_GPIO); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TIMER_WDT_GPIO_INV, polarity); - BL_WR_REG(TIMERx, TIMER_GPIO, tmpVal); -} - -/****************************************************************************/ /** - * @brief TIMER0 channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_CH0_IRQHandler(void) -{ - TIMER_IntHandler(TIMER0_ID, TIMER_CH0); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER0 channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_CH1_IRQHandler(void) -{ - TIMER_IntHandler(TIMER0_ID, TIMER_CH1); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER0 watchdog interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER0_WDT_IRQHandler(void) -{ - uint32_t tmpVal; - - WDT_ENABLE_ACCESS(TIMER0_BASE); - - tmpVal = BL_RD_REG(TIMER0_BASE, TIMER_WICR); - BL_WR_REG(TIMER0_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR)); - - if (wdtIntCbfArra[WDT0_ID][WDT_INT] != NULL) { - /* Call the callback function */ - wdtIntCbfArra[WDT0_ID][WDT_INT](); - } -} -#endif - -/****************************************************************************/ /** - * @brief TIMER1 channel 0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER1_CH0_IRQHandler(void) -{ - TIMER_IntHandler(TIMER1_ID, TIMER_CH0); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER1 channel 1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER1_CH1_IRQHandler(void) -{ - TIMER_IntHandler(TIMER1_ID, TIMER_CH1); -} -#endif - -/****************************************************************************/ /** - * @brief TIMER1 watchdog interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void TIMER1_WDT_IRQHandler(void) -{ - uint32_t tmpVal; - - WDT_ENABLE_ACCESS(TIMER1_BASE); - - tmpVal = BL_RD_REG(TIMER1_BASE, TIMER_WICR); - BL_WR_REG(TIMER1_BASE, TIMER_WICR, BL_SET_REG_BIT(tmpVal, TIMER_WICLR)); - - if (wdtIntCbfArra[WDT1_ID][WDT_INT] != NULL) { - /* Call the callback function */ - wdtIntCbfArra[WDT1_ID][WDT_INT](); - } -} -#endif -/*@} end of group TIMER_Private_Functions */ - -/*@} end of group TIMER */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c deleted file mode 100644 index 2cea9f2e57..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_touch.c +++ /dev/null @@ -1,906 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_touch.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_touch.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup TOUCH - * @{ - */ - -/** @defgroup TOUCH_Private_Macros - * @{ - */ - -/*@} end of group TOUCH_Private_Macros */ - -/** @defgroup TOUCH_Private_Types - * @{ - */ - -/*@} end of group TOUCH_Private_Types */ - -/** @defgroup TOUCH_Private_Variables - * @{ - */ -static intCallback_Type *touchIntCbfArra[TOUCH_INT_INTERRUPT + 1][TOUCH_CHANNEL_11 + 1] = { { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL } }; - -/*@} end of group TOUCH_Private_Variables */ - -/** @defgroup TOUCH_Global_Variables - * @{ - */ - -/*@} end of group TOUCH_Global_Variables */ - -/** @defgroup TOUCH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group TOUCH_Private_Fun_Declaration */ - -/** @defgroup TOUCH_Private_Functions - * @{ - */ - -/*@} end of group TOUCH_Private_Functions */ - -/** @defgroup TOUCH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief touch moudle init - * - * @param touchId: touch moudle ID - * @param tCfg: touch moudle config - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_Init(TOUCH_ID_Type touchId, TOUCH_CFG_Type *tCfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CLK_SEL_TYPE(tCfg->clkSel)); - CHECK_PARAM(IS_TOUCH_CLK_DIV_TYPE(tCfg->clkDiv)); - CHECK_PARAM(IS_TOUCH_POWER_SEL_TYPE(tCfg->powerSel)); - CHECK_PARAM(IS_TOUCH_WORK_MODE_TYPE(tCfg->workMode)); - CHECK_PARAM(IS_TOUCH_RUN_MODE_TYPE(tCfg->runMode)); - CHECK_PARAM((tCfg->sleepTime <= 0x7FFFFF)); - CHECK_PARAM(IS_TOUCH_PCHARGE_LOW_TYPE(tCfg->pchargeLow)); - CHECK_PARAM(IS_TOUCH_PCHARGE_HIGH_TYPE(tCfg->pchargeHigh)); - CHECK_PARAM(IS_TOUCH_LDO_VOLTAGE_TYPE(tCfg->ldoVol)); - CHECK_PARAM(IS_TOUCH_VREF_VOLTAGE_TYPE(tCfg->vrefVol)); - CHECK_PARAM(IS_TOUCH_HYSTERSIS_VOLTAGE_TYPE(tCfg->hystersisVol)); - CHECK_PARAM(IS_TOUCH_COMPENSATION_CAP_TYPE(tCfg->compensationCap)); - CHECK_PARAM(IS_TOUCH_FILTER_ORDER_CTRL_TYPE(tCfg->filterCtrl)); - CHECK_PARAM(IS_TOUCH_LTA_ORDER_CTRL_TYPE(tCfg->ltaCtrl)); - CHECK_PARAM((tCfg->dataHysCtrl <= 0x1FF)); - - /* touch1 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1); - - if (tCfg->powerSel == TOUCH_POWER_SEL_AON) { - /* power from AON bandgap */ - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_TOUCH_CURRENT_SEL); - } else { - /* power from internal bandgap */ - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_TOUCH_CURRENT_SEL); - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_ULP_EN, tCfg->ulpEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CYCLE_EN, tCfg->cycleEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CONT_EN, tCfg->runMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_PCHARGE_LOW, tCfg->pchargeLow); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_PCHARGE_HIGH, tCfg->pchargeHigh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CLK_DIV_RATIO, tCfg->clkDiv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CLK_SEL, tCfg->clkSel); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_COMP_HYS_SEL, tCfg->hystersisVol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VLDO_SEL, tCfg->ldoVol); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VREF_SEL, tCfg->vrefVol); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal); - - /* touch3 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VLDO_CCSEL, tCfg->compensationCap); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_SELF_MUTUAL_SEL, tCfg->workMode); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_ORDER, tCfg->filterCtrl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_EN, tCfg->filterEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_ORDER, tCfg->ltaCtrl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_EN, tCfg->ltaEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_DATA_HYS_EN, tCfg->dataHystersisEn); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL_CAL_EN, tCfg->calibrationEn); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH3, tmpVal); - - /* touch_sleep_time */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_SLEEP_TIME); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_SLEEP_CYCLE, tCfg->sleepTime); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_SLEEP_TIME, tmpVal); - - /* touch_data_hystersis */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_DATA_HYSTERSIS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_DATA_HYS, tCfg->dataHysCtrl); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_DATA_HYSTERSIS, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle channel init - * - * @param touchId: touch moudle ID - * @param tChCfg: touch moudle channel config - * @param tChSel: touch moudle channel select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_CHANNEL_Init(TOUCH_ID_Type touchId, TOUCH_CHANNEL_CFG_Type *tChCfg, TOUCH_CHANNEL_Type tChSel) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch0)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch1)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch2)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch3)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch4)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch5)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch6)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch7)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch8)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch9)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch10)); - CHECK_PARAM(IS_TOUCH_CHANNEL_HIGHZ_CFG_TYPE(tChCfg->ch11)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tChSel)); - - /* touch2 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL11_HIGHZ_EN, tChCfg->ch11); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL10_HIGHZ_EN, tChCfg->ch10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL9_HIGHZ_EN, tChCfg->ch9); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL8_HIGHZ_EN, tChCfg->ch8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL7_HIGHZ_EN, tChCfg->ch7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL6_HIGHZ_EN, tChCfg->ch6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL5_HIGHZ_EN, tChCfg->ch5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL4_HIGHZ_EN, tChCfg->ch4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL3_HIGHZ_EN, tChCfg->ch3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL2_HIGHZ_EN, tChCfg->ch2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL1_HIGHZ_EN, tChCfg->ch1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL0_HIGHZ_EN, tChCfg->ch0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_CHANNEL_SEL, tChSel); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH2, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle start - * - * @param touchId: touch moudle ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_Enable(TOUCH_ID_Type touchId) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - - /* touch1 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_TOUCH); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle stop - * - * @param touchId: touch moudle ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_Disable(TOUCH_ID_Type touchId) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - - /* touch1 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH1); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_TOUCH); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch moudle set V threshold value - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * @param value: vth value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_SetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh, uint8_t value) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - if (tCh <= TOUCH_CHANNEL_3) { - /* channel 0 - channel 3 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH0, value); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH1, value); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH2, value); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH3, value); - break; - - default: - break; - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0, tmpVal); - } else if (tCh <= TOUCH_CHANNEL_7) { - /* channel 4 - channel 7 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1); - - switch (tCh) { - case TOUCH_CHANNEL_4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH4, value); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH5, value); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH6, value); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH7, value); - break; - - default: - break; - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1, tmpVal); - } else { - /* channel 8 - channel 11 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2); - - switch (tCh) { - case TOUCH_CHANNEL_8: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH8, value); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH9, value); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH10, value); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH11, value); - break; - - default: - break; - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2, tmpVal); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get touch moudle vth data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return vth data - * -*******************************************************************************/ -uint32_t TOUCH_GetVthData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - if (tCh <= TOUCH_CHANNEL_3) { - /* channel 0 - channel 3 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_0); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH3); - break; - - default: - break; - } - } else if (tCh <= TOUCH_CHANNEL_7) { - /* channel 4 - channel 7 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_1); - - switch (tCh) { - case TOUCH_CHANNEL_4: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH7); - break; - - default: - break; - } - } else { - /* channel 8 - channel 11 */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_VTH_DATA_2); - - switch (tCh) { - case TOUCH_CHANNEL_8: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_VTH_DATA_CH11); - break; - - default: - break; - } - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch moudle raw data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return raw data - * -*******************************************************************************/ -uint32_t TOUCH_GetRawData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_0); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_2); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_3); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH3); - break; - - case TOUCH_CHANNEL_4: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_4); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_5); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_6); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_7); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH7); - break; - - case TOUCH_CHANNEL_8: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_8); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_9); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_10); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_RAW_DATA_11); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_RAW_DATA_CH11); - break; - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch moudle LTA data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return LTA data - * -*******************************************************************************/ -uint32_t TOUCH_GetLtaData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_0); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_2); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_3); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH3); - break; - - case TOUCH_CHANNEL_4: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_4); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_5); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_6); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_7); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH7); - break; - - case TOUCH_CHANNEL_8: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_8); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_9); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_10); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_LTA_DATA_11); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_LTA_DATA_CH11); - break; - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch moudle FLT data - * - * @param touchId: touch moudle ID - * @param tCh: touch moudle channel - * - * @return FLT data - * -*******************************************************************************/ -uint32_t TOUCH_GetFltData(TOUCH_ID_Type touchId, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - switch (tCh) { - case TOUCH_CHANNEL_0: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_0); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH0); - break; - - case TOUCH_CHANNEL_1: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_1); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH1); - break; - - case TOUCH_CHANNEL_2: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_2); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH2); - break; - - case TOUCH_CHANNEL_3: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_3); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH3); - break; - - case TOUCH_CHANNEL_4: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_4); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH4); - break; - - case TOUCH_CHANNEL_5: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_5); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH5); - break; - - case TOUCH_CHANNEL_6: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_6); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH6); - break; - - case TOUCH_CHANNEL_7: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_7); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH7); - break; - - case TOUCH_CHANNEL_8: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_8); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH8); - break; - - case TOUCH_CHANNEL_9: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_9); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH9); - break; - - case TOUCH_CHANNEL_10: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_10); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH10); - break; - - case TOUCH_CHANNEL_11: - tmpVal = BL_RD_REG(PDS_BASE, PDS_CHANNEL_FLT_DATA_11); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_FLT_DATA_CH11); - break; - } - - return tmpVal; -} - -/****************************************************************************/ /** - * @brief get touch end flag - * - * @param touchId: touch moudle ID - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type TOUCH_GetEndStatus(TOUCH_ID_Type touchId) -{ - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_STATUS), PDS_TOUCH_END_FLAG) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief touch interrupt enable - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_IntEnable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpVal = BL_SET_REG_BIT(tmpVal, PDS_TOUCH_INT_EN); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch interrupt disable - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_IntDisable(TOUCH_ID_Type touchId, TOUCH_INT_Type intType) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_TOUCH_INT_EN); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch interrupt mask or not - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_IntMask(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - uint32_t tmpMask = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - TOUCH_IntEnable(touchId, intType); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - - if (intMask == MASK) { - tmpMask = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK); - tmpMask |= (1 << tCh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK, tmpMask); - } else { - tmpMask = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK); - tmpMask &= (~(1 << tCh)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_MASK, tmpMask); - } - - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get touch interrupt status - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type TOUCH_GetIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_STATUS); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_STATUS); - - if (tmpVal & (1 << tCh)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief clear touch interrupt status - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_ClrIntStatus(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh) -{ - uint32_t tmpVal = 0; - uint32_t tmpClr = 0; - - CHECK_PARAM(IS_TOUCH_ID_TYPE(touchId)); - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - CHECK_PARAM(IS_TOUCH_CHANNEL_TYPE(tCh)); - - /* set */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpClr = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR); - tmpClr |= (1 << tCh); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR, tmpClr); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - /* unset */ - tmpVal = BL_RD_REG(PDS_BASE, PDS_TOUCH_INT_SETTING); - tmpClr = BL_GET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR); - tmpClr &= (~(1 << tCh)); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_TOUCH_INT_CLR, tmpClr); - tmpVal = BL_WR_REG(PDS_BASE, PDS_TOUCH_INT_SETTING, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief install touch interrupt callback - * - * @param touchId: touch moudle ID - * @param intType: touch moudle interrupt type - * @param tCh: touch moudle channel - * @param cbFun: callback function - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type TOUCH_INT_Callback_Install(TOUCH_ID_Type touchId, TOUCH_INT_Type intType, TOUCH_CHANNEL_Type tCh, intCallback_Type *cbFun) -{ - CHECK_PARAM(IS_TOUCH_INT_TYPE(intType)); - - touchIntCbfArra[intType][tCh] = cbFun; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief touch IRQ handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -void TOUCH_IRQHandler(void) -{ - TOUCH_CHANNEL_Type tmpCh; - - for (tmpCh = TOUCH_CHANNEL_0; tmpCh <= TOUCH_CHANNEL_11; tmpCh++) { - if (SET == TOUCH_GetIntStatus(TOUCH_ID_0, TOUCH_INT_INTERRUPT, tmpCh)) { - TOUCH_ClrIntStatus(TOUCH_ID_0, TOUCH_INT_INTERRUPT, tmpCh); - - if (touchIntCbfArra[TOUCH_INT_INTERRUPT][tmpCh] != NULL) { - touchIntCbfArra[TOUCH_INT_INTERRUPT][tmpCh](); - } - } - } -} - -/*@} end of group TOUCH_Public_Functions */ - -/*@} end of group TOUCH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c deleted file mode 100644 index 1b228b6f01..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uart.c +++ /dev/null @@ -1,1471 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_uart.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_uart.h" -#include "bl808_glb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup UART - * @{ - */ - -/** @defgroup UART_Private_Macros - * @{ - */ -#define UART_TX_TIMEOUT_COUNT (320 * 1000) - -/*@} end of group UART_Private_Macros */ - -/** @defgroup UART_Private_Types - * @{ - */ - -/*@} end of group UART_Private_Types */ - -/** @defgroup UART_Private_Variables - * @{ - */ -static const uint32_t uartAddr[UART_ID_MAX] = { UART0_BASE, UART1_BASE, UART2_BASE, UART3_BASE }; -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -static intCallback_Type *uartIntCbfArra[UART_ID_MAX][UART_INT_ALL] = { - { NULL } -}; -#endif - -/*@} end of group UART_Private_Variables */ - -/** @defgroup UART_Global_Variables - * @{ - */ - -/*@} end of group UART_Global_Variables */ - -/** @defgroup UART_Private_Fun_Declaration - * @{ - */ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -static void UART_IntHandler(UART_ID_Type uartId); -#endif - -/*@} end of group UART_Private_Fun_Declaration */ - -/** @defgroup UART_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief UART interrupt common handler function - * - * @param uartId: UART ID type - * - * @return None - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -static void UART_IntHandler(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t maskVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - maskVal = BL_RD_REG(UARTx, UART_INT_MASK); - - /* Length of uart tx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_UTX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_TX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_END](); - } - } - - /* Length of uart rx data transfer arrived interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_END_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_END_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_END_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RX_END] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_END](); - } - } - - /* Tx fifo ready interrupt,auto-cleared when data is pushed */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FIFO_REQ](); - } - } - - /* Rx fifo ready interrupt,auto-cleared when data is popped */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FRDY_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FRDY_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FIFO_REQ](); - } - } - - /* Rx time-out interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_RTO_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_RTO_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_RTO_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_RTO] != NULL) { - uartIntCbfArra[uartId][UART_INT_RTO](); - } - } - - /* Rx parity check error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_PCE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_PCE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_PCE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_PCE] != NULL) { - uartIntCbfArra[uartId][UART_INT_PCE](); - } - } - - /* Tx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_UTX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_UTX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_TX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_TX_FER](); - } - } - - /* Rx fifo overflow/underflow error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_FER_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_FER_MASK)) { - if (uartIntCbfArra[uartId][UART_INT_RX_FER] != NULL) { - uartIntCbfArra[uartId][UART_INT_RX_FER](); - } - } - - /* Rx lin mode sync field error interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_LSE_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_LSE_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_LSE_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_LSE] != NULL) { - uartIntCbfArra[uartId][UART_INT_LSE](); - } - } - - /* Rx byte count reached interrupt */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_BCR_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_BCR_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_BCR_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_BCR] != NULL) { - uartIntCbfArra[uartId][UART_INT_BCR](); - } - } - - /* Rx auto baud rate detection finish interrupt using start bit */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_ADS_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_ADS_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_ADS_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_STARTBIT] != NULL) { - uartIntCbfArra[uartId][UART_INT_STARTBIT](); - } - } - - /* Rx auto baud rate detection finish interrupt using codeword 0x55 */ - if (BL_IS_REG_BIT_SET(tmpVal, UART_URX_AD5_INT) && !BL_IS_REG_BIT_SET(maskVal, UART_CR_URX_AD5_MASK)) { - BL_WR_REG(UARTx, UART_INT_CLEAR, 1 << UART_CR_URX_AD5_CLR_POS); - - if (uartIntCbfArra[uartId][UART_INT_0X55] != NULL) { - uartIntCbfArra[uartId][UART_INT_0X55](); - } - } -} -#endif - -/*@} end of group UART_Private_Functions */ - -/** @defgroup UART_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief UART set baud rate function - * - * @param uartId: UART ID type - * @param baudRate: baudRate need to set - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate) -{ - uint32_t uartClk= 0; - uint32_t fraction = 0; - uint32_t baudRateDivisor = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get uart clk */ - if (uartId == UART0_ID || uartId == UART1_ID || uartId == UART2_ID) { - uartClk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0); - } else if (uartId == UART0_MM_ID) { - uartClk = Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART3); - } else { - return ERROR; - } - - /* Cal the baud rate divisor */ - fraction = uartClk * 10 / baudRate % 10; - baudRateDivisor = uartClk / baudRate; - - if (fraction >= 5) { - ++baudRateDivisor; - } - - /* Set the baud rate register value */ - BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART initialization function - * - * @param uartId: UART ID type - * @param uartCfg: UART configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg) -{ - uint32_t tmpValTxCfg = 0; - uint32_t tmpValRxCfg = 0; - uint32_t fraction = 0; - uint32_t baudRateDivisor = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_PARITY_TYPE(uartCfg->parity)); - CHECK_PARAM(IS_UART_DATABITS_TYPE(uartCfg->dataBits)); - CHECK_PARAM(IS_UART_STOPBITS_TYPE(uartCfg->stopBits)); - CHECK_PARAM(IS_UART_BYTEBITINVERSE_TYPE(uartCfg->byteBitInverse)); - - /* Disable clock gate when use UART2 */ - if(uartId == UART2_ID){ - GLB_PER_Clock_UnGate(GLB_AHB_CLOCK_UART2); - } - - /* Cal the baud rate divisor */ - fraction = uartCfg->uartClk * 10 / uartCfg->baudRate % 10; - baudRateDivisor = uartCfg->uartClk / uartCfg->baudRate; - - if (fraction >= 5) { - ++baudRateDivisor; - } - - /* Set the baud rate register value */ - BL_WR_REG(UARTx, UART_BIT_PRD, ((baudRateDivisor - 1) << 0x10) | ((baudRateDivisor - 1) & 0xFFFF)); - - /* Configure parity type */ - tmpValTxCfg = BL_RD_REG(UARTx, UART_UTX_CONFIG); - tmpValRxCfg = BL_RD_REG(UARTx, UART_URX_CONFIG); - - switch (uartCfg->parity) { - case UART_PARITY_NONE: - tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); - tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); - break; - - case UART_PARITY_ODD: - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); - tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); - tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); - break; - - case UART_PARITY_EVEN: - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_EN); - tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UTX_PRT_SEL); - tmpValRxCfg = BL_SET_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_EN); - tmpValRxCfg = BL_CLR_REG_BIT(tmpValRxCfg, UART_CR_URX_PRT_SEL); - break; - - default: - break; - } - - /* Configure data bits */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_D, (uartCfg->dataBits + 4)); - tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_BIT_CNT_D, (uartCfg->dataBits + 4)); - - /* Configure tx stop bits */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_P, uartCfg->stopBits); - - /* Configure tx cts flow control function */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_CTS_EN, uartCfg->ctsFlowControl); - - /* Configure rx input de-glitch function */ - tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_DEG_EN, uartCfg->rxDeglitch); - - /* Configure tx lin mode function */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_LIN_EN, uartCfg->txLinMode); - - /* Configure rx lin mode function */ - tmpValRxCfg = BL_SET_REG_BITS_VAL(tmpValRxCfg, UART_CR_URX_LIN_EN, uartCfg->rxLinMode); - - /* Set tx break bit count for lin protocol */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_BIT_CNT_B, uartCfg->txBreakBitCnt); - - /* Write back */ - BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpValTxCfg); - BL_WR_REG(UARTx, UART_URX_CONFIG, tmpValRxCfg); - - /* Configure LSB-first or MSB-first */ - tmpValTxCfg = BL_RD_REG(UARTx, UART_DATA_CONFIG); - - if (UART_MSB_FIRST == uartCfg->byteBitInverse) { - tmpValTxCfg = BL_SET_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); - } else { - tmpValTxCfg = BL_CLR_REG_BIT(tmpValTxCfg, UART_CR_UART_BIT_INV); - } - - BL_WR_REG(UARTx, UART_DATA_CONFIG, tmpValTxCfg); - - tmpValTxCfg = BL_RD_REG(UARTx, UART_SW_MODE); - /* Configure rx rts output SW control mode */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_URX_RTS_SW_MODE, uartCfg->rtsSoftwareControl); - /* Configure tx output SW control mode */ - tmpValTxCfg = BL_SET_REG_BITS_VAL(tmpValTxCfg, UART_CR_UTX_TXD_SW_MODE, uartCfg->txSoftwareControl); - BL_WR_REG(UARTx, UART_SW_MODE, tmpValTxCfg); - -#ifndef BFLB_USE_HAL_DRIVER - Interrupt_Handler_Register(UART0_IRQn, UART0_IRQHandler); - Interrupt_Handler_Register(UART1_IRQn, UART1_IRQHandler); - Interrupt_Handler_Register(UART2_IRQn, UART2_IRQHandler); - Interrupt_Handler_Register(UART3_IRQn, UART3_IRQHandler); -#endif - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set default value of all registers function - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_DeInit(UART_ID_Type uartId) -{ - switch(uartId){ - case UART0_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART0); - break; - case UART1_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART1); - break; - case UART2_ID: - GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_UART2); - break; - case UART0_MM_ID: - GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_SWRST_UART0); - break; - default: - break; - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure fifo function - * - * @param uartId: UART ID type - * @param fifoCfg: FIFO configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Deal with uart fifo configure register */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_1); - /* Configure dma tx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_TX_FIFO_TH, fifoCfg->txFifoDmaThreshold); - /* Configure dma rx fifo threshold */ - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_RX_FIFO_TH, fifoCfg->rxFifoDmaThreshold); - /* Write back */ - BL_WR_REG(UARTx, UART_FIFO_CONFIG_1, tmpVal); - - /* Enable or disable uart fifo dma function */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - - if (ENABLE == fifoCfg->txFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_TX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_TX_EN); - } - - if (ENABLE == fifoCfg->rxFifoDmaEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_DMA_RX_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_DMA_RX_EN); - } - - BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure infra function - * - * @param uartId: UART ID type - * @param irCfg: IR configuration structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Configure tx ir mode */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - - if (ENABLE == irCfg->txIrEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_EN); - } - - if (ENABLE == irCfg->txIrInverse) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_IR_INV); - } - - BL_WR_REG(UARTx, UART_UTX_CONFIG, tmpVal); - - /* Configure rx ir mode */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - - if (ENABLE == irCfg->rxIrEnable) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_EN); - } - - if (ENABLE == irCfg->rxIrInverse) { - tmpVal = BL_SET_REG_BIT(tmpVal, UART_CR_URX_IR_INV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, UART_CR_URX_IR_INV); - } - - BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); - - /* Configure tx ir pulse start and stop position */ - BL_WR_REG(UARTx, UART_UTX_IR_POSITION, irCfg->txIrPulseStop << 0x10 | irCfg->txIrPulseStart); - - /* Configure rx ir pulse start position */ - BL_WR_REG(UARTx, UART_URX_IR_POSITION, irCfg->rxIrPulseStart); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Enable UART - * - * @param uartId: UART ID type - * @param direct: UART direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); - - if (direct == UART_TX || direct == UART_TXRX) { - /* Enable UART tx unit */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_EN)); - } - - if (direct == UART_RX || direct == UART_TXRX) { - /* Enable UART rx unit */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Disable UART - * - * @param uartId: UART ID type - * @param direct: UART direction type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_DIRECTION_TYPE(direct)); - - if (direct == UART_TX || direct == UART_TXRX) { - /* Disable UART tx unit */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_EN)); - } - - if (direct == UART_RX || direct == UART_TXRX) { - /* Disable UART rx unit */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set length of tx data transfer,tx end interrupt will assert when this length is - * reached - * - * @param uartId: UART ID type - * @param length: Length of data (unit:character/byte) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set length */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_LEN, length - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set length of rx data transfer,rx end interrupt will assert when this length is - * reached - * - * @param uartId: UART ID type - * @param length: Length of data (unit:character/byte) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set length */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_LEN, length - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set rx time-out value for triggering RTO interrupt - * - * @param uartId: UART ID type - * @param time: Time-out value (unit:bit time) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set time-out value */ - tmpVal = BL_RD_REG(UARTx, UART_URX_RTO_TIMER); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_RTO_VALUE, time - 1); - BL_WR_REG(UARTx, UART_URX_RTO_TIMER, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set byte count value for bcr interrupt - * - * @param uartId: UART ID type - * @param count: Byte count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set count value */ - tmpVal = BL_RD_REG(UARTx, UART_URX_BCR_INT_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_BCR_VALUE, count); - BL_WR_REG(UARTx, UART_URX_BCR_INT_CFG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set de-glitch function cycle count value - * - * @param uartId: UART ID type - * @param deglitchCnt: De-glitch function cycle count - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Set count value */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_DEG_CNT, deglitchCnt); - BL_WR_REG(UARTx, UART_URX_CONFIG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set tx and rx baudrate according to auto baudrate detection value - * - * @param uartId: UART ID type - * @param autoBaudDet: Choose detection value using codeword 0x55 or start bit - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) -{ - uint32_t UARTx = uartAddr[uartId]; - uint16_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get detection value */ - tmpVal = UART_GetAutoBaudCount(uartId, autoBaudDet); - - /* Set tx baudrate */ - BL_WR_REG(UARTx, UART_BIT_PRD, tmpVal << 0x10 | tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set rx rts output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Rts set 1*/ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART clear rx rts output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Rts clear 0 */ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_RTS_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set tx output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetTxValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Tx set 1*/ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART clear tx output software control value - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - uint32_t tmpVal; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Rts clear 0 */ - tmpVal = BL_RD_REG(UARTx, UART_SW_MODE); - BL_WR_REG(UARTx, UART_SW_MODE, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_TXD_SW_VAL)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure tx free run mode function - * - * @param uartId: UART ID type - * @param txFreeRun: Enable or disable tx free run mode - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Enable or disable tx free run mode */ - tmpVal = BL_RD_REG(UARTx, UART_UTX_CONFIG); - - if (ENABLE == txFreeRun) { - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); - } else { - BL_WR_REG(UARTx, UART_UTX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_UTX_FRM_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART configure auto baud rate detection function - * - * @param uartId: UART ID type - * @param autoBaud: Enable or disable auto function - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Enable or disable auto baud rate detection function */ - tmpVal = BL_RD_REG(UARTx, UART_URX_CONFIG); - - if (ENABLE == autoBaud) { - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_SET_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); - } else { - BL_WR_REG(UARTx, UART_URX_CONFIG, BL_CLR_REG_BIT(tmpVal, UART_CR_URX_ABR_EN)); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART auto baud rate detection pulse width allowable error for using codeword 0x55 - * - * @param uartId: UART ID type - * @param allowableError: Pulse width allowable error - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - tmpVal = BL_RD_REG(UARTx, UART_URX_ABR_PW_TOL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_URX_ABR_PW_TOL, allowableError); - BL_WR_REG(UARTx, UART_URX_ABR_PW_TOL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART get bit width of auto baud rate detection for using codeword 0x55 - * - * @param uartId: UART ID type - * @param width: Buffer to save bit width, length:8 - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width) -{ - uint32_t i; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - for (i = 0; i < 4; i++) { - width[2 * i] = (uint16_t)BL_RD_WORD(UARTx + UART_URX_ABR_PRD_B01_OFFSET + 4 * i); - width[2 * i + 1] = (uint16_t)(BL_RD_WORD(UARTx + UART_URX_ABR_PRD_B01_OFFSET + 4 * i) >> 16); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART set RS-485 trans ceiver mode - * - * @param uartId: UART ID type - * @param enable: Enable or disable RS-485 mode - * @param polarity: Set DE polarity, active-low or active-high - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - tmpVal = BL_RD_REG(UARTx, UART_UTX_RS485_CFG); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_RS485_EN, enable); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, UART_CR_UTX_RS485_POL, polarity); - BL_WR_REG(UARTx, UART_UTX_RS485_CFG, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART tx fifo clear - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Clear tx fifo */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_TX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART rx fifo clear - * - * @param uartId: UART ID type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId) -{ - uint32_t tmpVal = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Clear rx fifo */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - BL_WR_REG(UARTx, UART_FIFO_CONFIG_0, BL_SET_REG_BIT(tmpVal, UART_RX_FIFO_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART mask or unmask certain or all interrupt - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * @param intMask: UART interrupt mask value( MASK:disbale interrupt,UNMASK:enable interrupt ) - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - CHECK_PARAM(IS_BL_MASK_TYPE(intMask)); - - tmpVal = BL_RD_REG(UARTx, UART_INT_MASK); - - /* Mask or unmask certain or all interrupt */ - if (UART_INT_ALL == intType) { - if (MASK == intMask) { - tmpVal |= 0xfff; - } else { - tmpVal &= 0; - } - } else { - if (MASK == intMask) { - tmpVal |= 1 << intType; - } else { - tmpVal &= ~(1 << intType); - } - } - - /* Write back */ - BL_WR_REG(UARTx, UART_INT_MASK, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART clear certain or all interrupt - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(UARTx, UART_INT_CLEAR); - - /* Clear certain or all interrupt */ - if (UART_INT_ALL == intType) { - tmpVal |= 0xfff; - } else { - tmpVal |= 1 << intType; - } - - /* Write back */ - BL_WR_REG(UARTx, UART_INT_CLEAR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Install uart interrupt callback function - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * @param cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void) - * - * @return SUCCESS - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -BL_Err_Type UART_Int_Callback_Install(UART_ID_Type uartId, UART_INT_Type intType, intCallback_Type *cbFun) -{ - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - uartIntCbfArra[uartId][intType] = cbFun; - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief UART send data to tx fifo - * - * @param uartId: UART ID type - * @param data: The data to be send - * @param len: The length of the send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len) -{ - uint32_t txLen = 0; - uint32_t UARTx = uartAddr[uartId]; - uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (txLen < len) { - if (UART_GetTxFifoCount(uartId) > 0) { - BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); - timeoutCnt = UART_TX_TIMEOUT_COUNT; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART send data to tx fifo in block mode - * - * @param uartId: UART ID type - * @param data: The data to be send - * @param len: The length of the send buffer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len) -{ - uint32_t txLen = 0; - uint32_t UARTx = uartAddr[uartId]; - uint32_t timeoutCnt = UART_TX_TIMEOUT_COUNT; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Send data */ - while (txLen < len) { - if (UART_GetTxFifoCount(uartId) > 0) { - BL_WR_BYTE(UARTx + UART_FIFO_WDATA_OFFSET, data[txLen++]); - timeoutCnt = UART_TX_TIMEOUT_COUNT; - } else { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - } - - timeoutCnt = UART_TX_TIMEOUT_COUNT; - - while (UART_GetTxBusBusyStatus(uartId) == SET) { - timeoutCnt--; - - if (timeoutCnt == 0) { - return TIMEOUT; - } - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief UART receive data from rx fifo - * - * @param uartId: UART ID type - * @param data: The receive data buffer - * @param maxLen: The max length of the buffer - * - * @return The length of the received buffer - * -*******************************************************************************/ -uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen) -{ - uint32_t rxLen = 0; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Receive data */ - while (rxLen < maxLen && UART_GetRxFifoCount(uartId) > 0) { - data[rxLen++] = BL_RD_BYTE(UARTx + UART_FIFO_RDATA_OFFSET); - } - - return rxLen; -} - -/****************************************************************************/ /** - * @brief UART get auto baud count value - * - * @param uartId: UART ID type - * @param autoBaudDet: Detection using codeword 0x55 or start bit - * - * @return Bit period of auto baudrate detection - * -*******************************************************************************/ -uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_AUTOBAUDDETECTION_TYPE(autoBaudDet)); - - /* Select 0x55 or start bit detection value */ - if (UART_AUTOBAUD_0X55 == autoBaudDet) { - return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) >> 0x10 & 0xffff; - } else { - return BL_RD_REG(UARTx, UART_STS_URX_ABR_PRD) & 0xffff; - } -} - -/****************************************************************************/ /** - * @brief UART get rx current byte count value - * - * @param uartId: UART ID type - * - * @return Rx byte count value - * -*******************************************************************************/ -uint16_t UART_GetRxByteCount(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_URX_BCR_INT_CFG), UART_STS_URX_BCR_COUNT); -} - -/****************************************************************************/ /** - * @brief UART get tx fifo unoccupied count value - * - * @param uartId: UART ID type - * - * @return Tx fifo unoccupied count value - * -*******************************************************************************/ -uint8_t UART_GetTxFifoCount(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_TX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief UART get rx fifo occupied count value - * - * @param uartId: UART ID type - * - * @return Rx fifo occupied count value - * -*******************************************************************************/ -uint8_t UART_GetRxFifoCount(UART_ID_Type uartId) -{ - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameter */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - return BL_GET_REG_BITS_VAL(BL_RD_REG(UARTx, UART_FIFO_CONFIG_1), UART_RX_FIFO_CNT); -} - -/****************************************************************************/ /** - * @brief Get uart interrupt status - * - * @param uartId: UART ID type - * @param intType: UART interrupt type - * - * @return Status of interrupt - * -*******************************************************************************/ -BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_INT_TYPE(intType)); - - /* Get certain or all interrupt status */ - tmpVal = BL_RD_REG(UARTx, UART_INT_STS); - - if (UART_INT_ALL == intType) { - if ((tmpVal & 0xfff) != 0) { - return SET; - } else { - return RESET; - } - } else { - if ((tmpVal & (1U << intType)) != 0) { - return SET; - } else { - return RESET; - } - } -} - -/****************************************************************************/ /** - * @brief Get indicator of uart tx bus busy - * - * @param uartId: UART ID type - * - * @return Status of tx bus - * -*******************************************************************************/ -BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get tx bus busy status */ - tmpVal = BL_RD_REG(UARTx, UART_STATUS); - - if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_UTX_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get indicator of uart rx bus busy - * - * @param uartId: UART ID type - * - * @return Status of rx bus - * -*******************************************************************************/ -BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - - /* Get rx bus busy status */ - tmpVal = BL_RD_REG(UARTx, UART_STATUS); - - if (BL_IS_REG_BIT_SET(tmpVal, UART_STS_URX_BUS_BUSY)) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief Get tx/rx fifo overflow or underflow status - * - * @param uartId: UART ID type - * @param overflow: Select tx/rx overflow or underflow - * - * @return Status of tx/rx fifo - * -*******************************************************************************/ -BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow) -{ - uint32_t tmpVal; - uint32_t UARTx = uartAddr[uartId]; - - /* Check the parameters */ - CHECK_PARAM(IS_UART_ID_TYPE(uartId)); - CHECK_PARAM(IS_UART_OVERFLOW_TYPE(overflow)); - - /* Get tx/rx fifo overflow or underflow status */ - tmpVal = BL_RD_REG(UARTx, UART_FIFO_CONFIG_0); - - if ((tmpVal & (1U << (overflow + 4))) != 0) { - return SET; - } else { - return RESET; - } -} - -/****************************************************************************/ /** - * @brief UART0 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -void UART0_IRQHandler(void) -{ - UART_IntHandler(UART0_ID); -} -#endif - -/****************************************************************************/ /** - * @brief UART1 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER) -void UART1_IRQHandler(void) -{ - UART_IntHandler(UART1_ID); -} -#endif - -/****************************************************************************/ /** - * @brief UART2 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void UART2_IRQHandler(void) -{ - UART_IntHandler(UART2_ID); -} -#endif - -/****************************************************************************/ /** - * @brief UART3 interrupt handler - * - * @param None - * - * @return None - * -*******************************************************************************/ -#ifndef BFLB_USE_HAL_DRIVER -void UART3_IRQHandler(void) -{ - UART_IntHandler(UART0_MM_ID); -} -#endif - -/*@} end of group UART_Public_Functions */ - -/*@} end of group UART */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c deleted file mode 100644 index 6b502dc01d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_uhs_phy.c +++ /dev/null @@ -1,1500 +0,0 @@ -#include "bl808_uhs_phy.h" -#include -#include -#include -#include "psram_uhs_reg.h" -#include "glb_reg.h" -#include "pds_reg.h" -#include "bl808_common.h" -#include "bl808_psram_uhs.h" -#include "bl808_glb.h" - -#define bl808_DBG_RF (0) -#if bl808_DBG_RF -#define uhs_phy_printf_debug printf // debug mode -#define uhs_phy_printf printf -#else -#define uhs_phy_printf_debug(...) -// #define uhs_phy_printf printf // commit it out in release version -#define uhs_phy_printf(...) // useed in release version -#endif - -uint8_t uhs_latency_code = 1; -int32_t dqs_dq_delta = 0; -uint32_t dcache_original = 0; -uint32_t dcache_current = 0; -uint32_t dcache_end = 0; - - -void uhs_phy_delay_us(uint32_t us) -{ - arch_delay_us(us); -} - -void power_up_mm(void) -{ - // power up MM domain - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,0x0); - BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal); -} - -void power_up_uhspll(void) -{ - // power_up_uhspll - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); -} - -void power_up_ldo12uhs(void) -{ - // use internal LDO - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_VOUT_SEL,0x5); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - uhs_phy_delay_us(1); - // use external LDO - // tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN,0x0); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x1); - // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0); - // BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); -} - -void set_cen_ck_ckn(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xfc); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(1); -} - -void set_or_uhs(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,0x8); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,0xB); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,0x7); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,0x6); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,0x6); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_SR,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_SR,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_P_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_N_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_P_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_N_REG,0x3); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0N_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_RX,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1N_DLY_RX,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); - uhs_phy_delay_us(300); -} - -void switch_to_ldo12uhs(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcc); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(150); -} - -void release_cen_ck_ckn(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcf); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x3); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x3); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); - uhs_phy_delay_us(1); -} - -void uhs_phy_pwr_down(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x0); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xff); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal); - uhs_phy_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x0); - BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal); - uhs_phy_delay_us(1); -} - -void psram_init(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_LINEAR_BND_B,0xb); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_GLBR_PULSE,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); - uhs_phy_delay_us(10); // wait for reg_config_gnt - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - - // psram auto refresh at 2000Mbps - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,0x001E0C4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,0x1007); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,0x01d); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,0x40); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - - // psram cmd timing < 2000Mbps - BL_WR_WORD(0x3000F030,0x18090610); -} - -void set_uhspll_freq(uint32_t datarate) -{ - uint32_t tmpVal = 0; - uint32_t uhspll_sdmin = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SEL_SAMPLE_CLK,0x1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG4,tmpVal); - uhspll_sdmin = (datarate/(40/2))<<11; - if(datarate > 1000) - { - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x0); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal); - } - else if(datarate > 500) - { - uhspll_sdmin = uhspll_sdmin<<1; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal); - } - else - { - uhspll_sdmin = uhspll_sdmin<<2; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG5); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_VCO_POSTDIV_SEL,0x2); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG5,tmpVal); - } - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG6); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDMIN,uhspll_sdmin); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG6,tmpVal); - uhs_phy_delay_us(30); - - //reset PLL - /* toggle sdm_reset (pulse 0 > 1us) */ - /* cfg0 : aupll_sdm_reset */ - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 0); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_SDM_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - - /* Step3:reset pll */ - /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */ - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 0); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - arch_delay_us(2); - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UHSPLL_FBDV_RSTB, 1); - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal); - - uhs_phy_delay_us(30); -} - -void set_uhs_phy_init(void) -{ - // set phy & controller - uint32_t tmpVal = 0; - // default latency(800MHz) - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,0x7); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,0x2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,0x2); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x09020303); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x040c0313); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x07d11515); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x060f050c); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_CEN_ANA,0x1); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal); -} - -void set_uhs_phy(void) -{ - // set phy & controller - // latency code=3 (1066MHz) - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a1323); // if fail than use 0x0f391323 - // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a0313); //for 400Mbps - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x0b030404); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x050e0418); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x0a6a1c1c); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x07110710); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,0x01333333); -} - -void uhs_reg_w(uint32_t uhs_latency,uint32_t uhs_drive,uint32_t ma,uint32_t BL_32) -{ - uint32_t tmpVal = 0; - if(ma == 0) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_LATENCY,uhs_latency); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DRIVE_ST,uhs_drive); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal); - } - else if(ma == 2) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,BL_32); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal); - } - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - while (1) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT); - if (tmpVal == 1) - break; - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1); //reg_regw_pulse - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); - while (1) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if (tmpVal == 1) - break; - } - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); -} - -void uhs_reg_r(uint32_t ma) -{ - uint32_t tmpVal = 0; - uint32_t tmpInd = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); - - // uhs_phy_delay_us(10); - while (1) - { - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT); - if (tmpVal == 1) - break; - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGR_PULSE,0x1); //reg_regw_pulse - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal); - // uhs_phy_delay_us(1); - tmpInd = 0; - while (1) - { - tmpInd++; - uhs_phy_delay_us(1); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if (tmpVal == 1 || tmpInd == 2){ - //debug - if (tmpInd == 2){ - uhs_phy_printf_debug("tmpInd = %ld\r\n",tmpInd); - } - break; - } - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0); //reg_config_req - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal); -} - - -void cfg_dq_rx(uint8_t dq){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); -} - -void cfg_dqs_rx(uint8_t dqs){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); -} - -void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,array_ck_dly_drv); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,array_cen_dly_drv); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal); -} - -void uhs_reset(uint32_t datarate) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_WORD(0x30007044); - tmpVal = tmpVal | 0x00008000; - BL_WR_WORD(0x30007044,tmpVal); - uhs_phy_delay_us(10); - tmpVal = tmpVal & 0xFFFF7FFF; - BL_WR_WORD(0x30007044,tmpVal); - - BL_WR_WORD(0x3000F030,0x18090610); - - PSRAM_UHS_Cfg_Type psramCfg = { - datarate, - PSRAM_MEM_SIZE_64MB, - PSRAM_PAGE_SIZE_2KB, - 0, - }; - Psram_UHS_Init(&psramCfg); //controller init - - set_or_uhs(); - set_uhs_phy(); -} - -void reg_read_cal(uint32_t datarate) -{ - uint32_t tmpVal = 0; - uint32_t tmpVal_1 = 0; - uint32_t uhs_latency = 42; - int32_t i = 0; - uint8_t dqs_dq_flag = 0; - uint32_t reg_dqs = 0; - uint32_t reg_dq = 0; - - for(uhs_latency = 41; uhs_latency > 0; uhs_latency --) - { - if(uhs_latency == 34) - { - uhs_phy_printf("reg read cal error\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - uhs_phy_printf_debug("reg read cal by latency=%ld\r\n",uhs_latency); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - - // sweep dqs - cfg_dq_rx(0); - for(i = 15; i >= 0; i --) - { - cfg_dqs_rx(i); - - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dqs=%ld\r\n",i); - reg_dqs = i; - dqs_dq_flag = 1; - break; - } - else - { - uhs_phy_printf_debug("reg read fail by dqs=%ld\r\n",i); - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if(tmpVal == 0) - { - uhs_phy_printf_debug("read done not found!!!"); - uhs_reset(datarate); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - cfg_dq_rx(0); - } - - } - - // sweep dq - cfg_dqs_rx(0); - for(i = 15; i >=0; i --) - { - cfg_dq_rx(i); - - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dq=%ld\r\n",i); - reg_dq = i; - dqs_dq_flag = 1; - break; - } - else - { - uhs_phy_printf_debug("reg read fail by dq=%ld\r\n",i); - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); - tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); - if(tmpVal == 0) - { - uhs_phy_printf_debug("read done not found!!!"); - uhs_reset(datarate); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - cfg_dqs_rx(0); - } - - } - - if (dqs_dq_flag == 1){ - uhs_latency = uhs_latency - 2; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - //sweep dqs - cfg_dq_rx(0); - for(i = 15; i >= 0; i --) - { - cfg_dqs_rx(i); - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dqs=%ld\r\n",i); - reg_dqs = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg read fail by dqs=%ld\r\n",i); - } - } - // sweep dq - cfg_dqs_rx(0); - for(i = 15; i >=0; i --) - { - cfg_dq_rx(i); - - uhs_reg_r(0); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)&& (tmpVal_1 == 1)) - { - uhs_phy_printf_debug("reg read pass by dq=%ld\r\n",i); - reg_dq = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg read fail by dq=%ld\r\n",i); - } - } - - if(reg_dqs > reg_dq) - { - reg_dqs = (reg_dqs-reg_dq)/2; - reg_dq = 0; - } - else - { - reg_dq = (reg_dq-reg_dqs)/2; - reg_dqs = 0; - } - - // set dqs & dq by register read calibration result - cfg_dqs_rx(reg_dqs); - cfg_dq_rx(reg_dq); - uhs_reg_r(0); - uhs_phy_printf("reg read cal pass, latency=%ld, dqs=%ld, dq=%ld\r\n",uhs_latency,reg_dqs,reg_dq); - - break; - } - } -} - -void cfg_dq_drv(uint32_t dq){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,dq); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,dq); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal); -} - -void cfg_dqs_drv(uint32_t dqs){ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,dqs); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal); -} - -void reg_write_cal(void) //only need sweep dqs -{ - uint32_t tmpVal = 0; - uint32_t tmpVal_1 = 0; - int32_t i = 0; - uint32_t reg_dqs; - uint32_t reg_dq = 0; - uint32_t reg_dqs1 = 0; - uint32_t reg_dqs2 = 0; - uint8_t dqs_dq_flag = 0; - - // sweep1 dqs - for(i = 15; i >=0; i --) - { - cfg_dqs_drv(i); - uhs_reg_w(uhs_latency_code,2,2,1); //BL_32 == 1 - uhs_reg_r(2); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if((tmpVal == 16) && (tmpVal_1 == 1)) - { - uhs_phy_printf("reg write pass by -- dqs1=%ld\r\n",i); - reg_dqs1 = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg write fail by -- dqs1=%ld\r\n",i); - } - } - // sweep2 dqs - for(i = 0; i <=15; i ++) - { - cfg_dqs_drv(i); - uhs_reg_w(uhs_latency_code,2,2,1); //BL_32 == 1 - uhs_reg_r(2); - tmpVal_1 = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD); //high temp failure workaround - tmpVal_1 = BL_GET_REG_BITS_VAL(tmpVal_1,PSRAM_UHS_STS_REGR_DONE); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if((tmpVal == 16) && (tmpVal_1 == 1)) - { - uhs_phy_printf("reg write pass by ++ dqs2=%ld\r\n",i); - reg_dqs2 = i; - dqs_dq_flag = 1; - break; - } - else{ - uhs_phy_printf_debug("reg write fail by ++ dqs2=%ld\r\n",i); - } - } - - if(dqs_dq_flag == 0) - { - uhs_phy_printf("reg write cal error 0\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - reg_dqs = (reg_dqs1 + reg_dqs2) / 2 ; - // set dqs by register write cal result - cfg_dqs_drv(reg_dqs); - uhs_reg_w(uhs_latency_code,2,2,0); //BL_32 == 0 - uhs_reg_r(2); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == 0) - { - uhs_phy_printf("reg write cal pass dqs=%ld, dq=%ld\r\n",reg_dqs,reg_dq); - } - else{ - uhs_phy_printf("reg write cal error 1\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08); - reg_dq = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV); - dqs_dq_delta = 16 + reg_dqs - reg_dq; - uhs_phy_printf("reg_write_cal return dqs_dq_delta=%ld\r\n",dqs_dq_delta); - // return dqs_dq_delta; -} - -void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1) -{ - uint32_t addr_tmp = addr; - uint32_t data = data0; - int32_t i = 0; - for(i = 0; i < (len>>2); i ++) - { - addr_tmp = (i << 2) + addr; - if(i % 2 == 0) - data = data0 + i; - else - data = data1 + i; - BL_WR_WORD(addr_tmp,data); - } -} -uint32_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1) -{ - uint32_t array_read_pass = 1; - uint32_t addr_tmp = addr; - uint32_t data = data0; - uint32_t data_read = 0; - int32_t i = 0; - - for(i = 0; i < (len>>2); i ++) - { - addr_tmp = (i << 2) + addr; - data_read = BL_RD_WORD(addr_tmp); - if(i % 2 == 0) - data = data0 + i; - else - data = data1 + i; - if(data_read != data){ - array_read_pass = 0; - break; - } - } - return array_read_pass; -} - -void set_ck_dly_drv(uint32_t array_ck_dly_drv) -{ - uint32_t array_dqx_dly_drv = 0; - uint32_t array_dqsx_dly_drv = 0; - uint32_t array_cen_dly_drv = 0; - - arch_delay_us(1); // ck modify need time - - array_dqx_dly_drv = (array_ck_dly_drv >=4) ? (array_ck_dly_drv-4) : 0; - array_cen_dly_drv = array_dqx_dly_drv + 1; - // array_dqsx_dly_drv = ((int32_t)((int32_t)(dqs_dq_delta)+(int32_t)(array_dqx_dly_drv))<0)?0:(array_dqx_dly_drv + dqs_dq_delta); - array_dqsx_dly_drv = (dqs_dq_delta + array_dqx_dly_drv >= 16) ? (dqs_dq_delta + array_dqx_dly_drv - 16) : 0; - - // array_dqsx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqsx_dly_drv; - array_dqx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqx_dly_drv; - array_cen_dly_drv = (array_cen_dly_drv > 15) ? 15 : array_cen_dly_drv; - array_dqsx_dly_drv = (array_dqsx_dly_drv > 15) ? 15 : array_dqsx_dly_drv; - - cfg_dq_drv(array_dqx_dly_drv); - cfg_dqs_drv(array_dqsx_dly_drv); - cfg_ck_cen_drv(array_ck_dly_drv,array_cen_dly_drv); - - arch_delay_us(10); // ck modify need time -} - -void array_read_latency_cal(void) -{ - uint32_t tmpVal = 0; - uint32_t uhs_latency = 42; - uint32_t array_ck_dly_drv = 0; - uint32_t flag = 0; - - uint32_t dig = 0; - uint32_t ana = 0; - uint32_t latency = 0; - - array_write_fix(0x50000000,128,0x12345678,0x87654321); - - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - dig = (tmpVal >> 16) & 0xF; - ana = (tmpVal >> 20) & 0x7; - latency = (dig<<2) + ana; - - for(uhs_latency = latency; uhs_latency > 0; uhs_latency --) - { - if(uhs_latency == 34) - { - uhs_phy_printf("array read latency cal error\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - - uhs_phy_printf_debug("array read cal by latency=%ld\r\n",uhs_latency); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - - array_ck_dly_drv = 11; - set_ck_dly_drv(array_ck_dly_drv); - - flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - - if(flag == 1) - { - uhs_phy_printf_debug("array read pass by ck == 11\r\n"); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - uhs_phy_printf("array read latency cal pass, latency=%ld, ck=%ld\r\n",uhs_latency,array_ck_dly_drv); - break; - } - else - { - uhs_phy_printf_debug("array read fail by ck == 11\r\n"); - array_ck_dly_drv = 4; - set_ck_dly_drv(array_ck_dly_drv); - flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(flag == 1) - { - uhs_phy_printf_debug("array read pass by ck == 4\r\n"); - // uhs_latency = uhs_latency - 2; - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4); - BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal); - uhs_phy_printf("array read latency cal pass, latency=%ld, ck=%ld\r\n",uhs_latency,array_ck_dly_drv); - break; - } - else{ - uhs_phy_printf_debug("array read fail by ck == 4\r\n"); - } - } - } -} - -void array_write_ck_cal(void) -{ - uint32_t array_ck_dly_drv = 0; - uint32_t array_ck_dly_drv1 = 0; - uint32_t array_ck_dly_drv2 = 0; - uint32_t flag = 0; - - array_write_fix(0x50000000,1024,0x12345678,0x87654321); - - for(array_ck_dly_drv = 15; array_ck_dly_drv >= 4; array_ck_dly_drv --) - { - set_ck_dly_drv(array_ck_dly_drv); - - flag = array_read_fix(0x50000000,1024,0x12345678,0x87654321); - if(flag == 0){ - uhs_phy_printf_debug("array write ck cal fail by ck=%ld\r\n",array_ck_dly_drv); - array_ck_dly_drv1 = array_ck_dly_drv; - break; - } - } - - if(flag == 1){ - array_ck_dly_drv = (15 + 4) / 2; - set_ck_dly_drv(array_ck_dly_drv); - - uhs_phy_printf("array write ck cal pass, ck=%ld\r\n",array_ck_dly_drv); - return; - } - - for(array_ck_dly_drv = 4; array_ck_dly_drv <= 15; array_ck_dly_drv ++) - { - set_ck_dly_drv(array_ck_dly_drv); - - flag = array_read_fix(0x50000000,1024,0x12345678,0x87654321); - if(flag == 0){ - uhs_phy_printf_debug("array write ck cal fail by ck=%ld\r\n",array_ck_dly_drv); - array_ck_dly_drv2 = array_ck_dly_drv; - break; - } - } - - if(array_ck_dly_drv1 == 15 && array_ck_dly_drv2 == 4) - { - uhs_phy_printf_debug("array write ck cal error\r\n"); - while(1){ - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - // break; - } - if ((15 - array_ck_dly_drv1) >= (array_ck_dly_drv2 - 4)) - { - array_ck_dly_drv = 15; - } - else - { - array_ck_dly_drv = 4; - } - - set_ck_dly_drv(array_ck_dly_drv); - - uhs_phy_printf("array write ck cal pass, ck=%ld\r\n",array_ck_dly_drv); - -} - -void array_read_dqs_dq_cal(void) -{ - // uint32_t tmpVal = 0; - int32_t i = 0; - uint32_t array_dqs = 0; - uint32_t array_dq = 0; - uint32_t dqs_flag; - uint32_t dq_flag; - array_write_fix(0x50000000,128,0x12345678,0x87654321); - // sweep dqs - cfg_dq_rx(0); - - for(i = 15; i >= 0; i --) - { - cfg_dqs_rx(i); - dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dqs_flag == 1) - { - uhs_phy_printf_debug("array_read_dqs_dq_cal pass by dqs%ld\r\n",i); - array_dqs = i; - break; - } - } - // sweep dq - cfg_dqs_rx(0); - for(i = 15; i >=0; i --) - { - cfg_dq_rx(i); - dq_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dq_flag == 1) - { - uhs_phy_printf_debug("array_read_dqs_dq_cal pass by dq%ld\r\n",i); - array_dq = i; - break; - } - } - if(dqs_flag == 0 && dq_flag == 0) - { - uhs_phy_printf("array_read_dqs_dq_cal error\r\n"); - while(1) - { - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - } - if(array_dqs > array_dq) - { - array_dqs = (array_dqs-array_dq)/2; - array_dq = 0; - } - else - { - array_dq = (array_dq-array_dqs)/2; - array_dqs = 0; - } - cfg_dq_rx(array_dq); - cfg_dqs_rx(array_dqs); - uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs=%ld, array_dq=%ld\r\n",array_dqs,array_dq); -} - -void array_write_dqs_dq_cal(void) -{ - uint32_t tmpVal = 0; - int32_t i = 0; - uint32_t dqs_flag = 0; - uint32_t array_dqs_dly_drv = 0; - uint32_t array_dqs_dly_drv1 = 0; - uint32_t array_dqs_dly_drv2 = 0; - - for(i = 15; i >= 0; i --) - { - cfg_dqs_drv(i); - array_write_fix(0x50000000,128,0x12345678,0x87654321); - dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dqs_flag == 1) - { - uhs_phy_printf("array_write_dqs_dq_cal pass by -- dqs1=%ld\r\n",i); - array_dqs_dly_drv1 = i; - break; - } - else - { - uhs_phy_printf_debug("array_write_dqs_dq_cal fail by -- dqs1=%ld\r\n",i); - } - } - for(i = 0; i <= 15; i ++) - { - cfg_dqs_drv(i); - array_write_fix(0x50000000,128,0x12345678,0x87654321); - dqs_flag = array_read_fix(0x50000000,128,0x12345678,0x87654321); - if(dqs_flag == 1) - { - uhs_phy_printf("array_write_dqs_dq_cal pass by ++ dqs2=%ld\r\n",i); - array_dqs_dly_drv2 = i; - break; - } - else - { - uhs_phy_printf_debug("array_write_dqs_dq_cal fail by ++ dqs2=%ld\r\n",i); - } - } - if(dqs_flag == 0) - { - uhs_phy_printf("array_write_dqs_dq_cal error\r\n"); - while(1) - { - uhs_phy_printf("."); - uhs_phy_delay_us(100000); - }; - } - array_dqs_dly_drv = (array_dqs_dly_drv1 + array_dqs_dly_drv2) / 2 ; - // if ck_dly_drv = 4, fix dqsx_dly_drv to 0 - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00); - tmpVal = (tmpVal >> 16) & 0xF; - if(tmpVal == 4) - { - array_dqs_dly_drv = 0; - } - uhs_phy_printf("array_write_dqs_dq_cal pass by array_dqs_dly_drv=%ld\r\n",array_dqs_dly_drv); - // set dqs by register write cal result - cfg_dqs_drv(array_dqs_dly_drv); -} - -BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq) -{ - uint32_t xtalFreq = 0; - uint32_t factor = 0; - GLB_MU_PLL_CFG_BASIC_Type uhsPllMCfg = { - .clkpllRefdivRatio = 1, /*!< pll_refdiv_ratio */ - .clkpllSelSampleClk = 2, /*!< pll_sel_sample_clk */ - .clkpllVcoSpeed = 7, /*!< pll_vco_speed */ - .clkpllEvenDivEn = 1, /*!< pll_even_div_en */ - .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */ - }; - GLB_MU_PLL_Cfg_Type uhsPllCfg[GLB_XTAL_MAX] = { - { NULL, 0x0 }, /*!< XTAL is None */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 24M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 32M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 38.4M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 40M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is 26M */ - { &uhsPllMCfg, 0x0 }, /*!< XTAL is RC32M */ - }; - GLB_PLL_REF_CLK_Type refClk; - - /* calc clkpllRefdivRatio */ - switch(xtalType){ - case GLB_XTAL_NONE: - return ERROR; - case GLB_XTAL_24M: - xtalFreq = 240; - uhsPllMCfg.clkpllRefdivRatio = 1; - break; - case GLB_XTAL_32M: - xtalFreq = 320; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - case GLB_XTAL_38P4M: - xtalFreq = 384; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - case GLB_XTAL_40M: - xtalFreq = 400; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - case GLB_XTAL_26M: - xtalFreq = 260; - uhsPllMCfg.clkpllRefdivRatio = 1; - break; - case GLB_XTAL_RC32M: - xtalFreq = 320; - uhsPllMCfg.clkpllRefdivRatio = 2; - break; - default : - break; - } - /* calc clkpllSelSampleClk */ - factor = pllFreq*20480/(xtalFreq/uhsPllMCfg.clkpllRefdivRatio); - if(factor<32*2048){ - uhsPllMCfg.clkpllSelSampleClk = 0; - }else if(factor<64*2048){ - uhsPllMCfg.clkpllSelSampleClk = 1; - }else if(factor<128*2048){ - uhsPllMCfg.clkpllSelSampleClk = 2; - }else{ - uhsPllMCfg.clkpllSelSampleClk = 2; - } - /* calc clkpllVcoSpeed */ - if(pllFreq<800){ - uhsPllMCfg.clkpllVcoSpeed = 1; - }else if(pllFreq<1000){ - uhsPllMCfg.clkpllVcoSpeed = 2; - }else if(pllFreq<1200){ - uhsPllMCfg.clkpllVcoSpeed = 3; - }else if(pllFreq<1500){ - uhsPllMCfg.clkpllVcoSpeed = 4; - }else if(pllFreq<1700){ - uhsPllMCfg.clkpllVcoSpeed = 5; - }else if(pllFreq<1900){ - uhsPllMCfg.clkpllVcoSpeed = 6; - }else if(pllFreq<2200){ - uhsPllMCfg.clkpllVcoSpeed = 7; - }else{ - uhsPllMCfg.clkpllVcoSpeed = 8; - } - /* calc clkpllEvenDivRatio */ - uhsPllMCfg.clkpllEvenDivRatio = pllFreq/50; - /* calc clkpllSdmin */ - uhsPllCfg[GLB_XTAL_24M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_32M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_38P4M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_40M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_26M].clkpllSdmin = factor; - uhsPllCfg[GLB_XTAL_RC32M].clkpllSdmin = factor; - - if (xtalType == GLB_XTAL_RC32M) { - refClk = GLB_PLL_REFCLK_RC32M; - } else { - refClk = GLB_PLL_REFCLK_XTAL; - } - - GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL); - GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk); - GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(uhsPllCfg[xtalType]), 1); - - return SUCCESS; -} - -void self_cal(uint32_t datarate) -{ - // int32_t P1= 0; - uint32_t tmpVal = 0; - // uint32_t uhs_latency = 0; - - if (datarate >= 933*2){ - uhs_latency_code = UHS_LATENCY_CODE_1066; - }else if(datarate >= 800*2){ - uhs_latency_code = UHS_LATENCY_CODE_933; - }else if(datarate >= 533*2){ - uhs_latency_code = UHS_LATENCY_CODE_800; - }else if(datarate >= 400*2){ - uhs_latency_code = UHS_LATENCY_CODE_533; - }else if(datarate >= 333*2){ - uhs_latency_code = UHS_LATENCY_CODE_400; - }else if(datarate >= 200*2){ - uhs_latency_code = UHS_LATENCY_CODE_333; - }else{ - uhs_latency_code = UHS_LATENCY_CODE_200; - } - - PSRAM_UHS_Cfg_Type psramCfg = { - datarate, - PSRAM_MEM_SIZE_64MB, - PSRAM_PAGE_SIZE_2KB, - 0, - }; - - // set to 2000Mbps - uhs_reg_w(uhs_latency_code,2,0,0); // BL_32 == 0 - // set_uhspll_freq(datarate); // use SW function later - GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,datarate); //stuck - Psram_UHS_Init(&psramCfg); //controller init - set_uhs_phy(); - - // check reg read - uhs_reg_r(0); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+uhs_latency_code)){ - uhs_phy_printf("register write pass at 1400Mbps and read pass at %ldMbps\r\n",datarate); - } - else{ - uhs_phy_printf("register write fail at 1400Mbps or read fail at %ldMbps\r\n",datarate); - } - - // register read latency & dqs & dq calibration - reg_read_cal(datarate); - // register write dqs & dq calibration - reg_write_cal(); - uhs_reg_w(uhs_latency_code,2,2,0); // BL_32 == 0 - uhs_reg_r(2); - // array read latency calibration - array_read_latency_cal(); - // array write ck calibration - array_write_ck_cal(); - // array read dqs & dq calibration - array_read_dqs_dq_cal(); - // array write dqs & dq calibration - array_write_dqs_dq_cal(); -} - -void soft_reset(void) -{ - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_SWRST_CFG2); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_CTRL_PWRON_RST,0x1); // soft power on reset - BL_WR_REG(GLB_BASE,GLB_SWRST_CFG2,tmpVal); -} - -void uhs_phy_init(uint32_t datarate) -{ - uhs_phy_printf_debug("uhs phy init\r\n"); - power_up_mm(); - power_up_uhspll(); - - power_up_ldo12uhs(); - set_cen_ck_ckn(); - - set_or_uhs(); - switch_to_ldo12uhs(); - release_cen_ck_ckn(); - - uint32_t tmpVal = 0; - tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG9); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SSC_EN,0x0); // uhspll_ssc_en - BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG9,tmpVal); - - PSRAM_UHS_Cfg_Type psramCfg = { - 1400, - PSRAM_MEM_SIZE_64MB, - PSRAM_PAGE_SIZE_2KB, - 0, - }; - - // set_uhspll_freq(1400); // 700MHz is prefer , use SW function later - GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,1400); //stuck - Psram_UHS_Init(&psramCfg); // controller init - set_uhs_phy_init(); // phy init - psram_init(); // psram init after set freq & set_phy - - uhs_reg_r(0); - tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24; - if(tmpVal == ((2<<3)+1)) // 1400M --> default uhs_latency_code == 1 - { - uhs_phy_printf_debug("register read pass at datarate at 1400Mbps\r\n"); - } - else{ - uhs_phy_printf_debug("register read fail at datarate at 1400Mbps\r\n"); - } - - //get dcache original state - __DSB(); - __ISB(); - dcache_original = __get_MHCR(); - dcache_original &= (0x1<<1); - __DSB(); - __ISB(); - uhs_phy_printf("dcache_original=%lx\r\n",dcache_original); - - csi_dcache_disable(); - - //get dcache current state - __DSB(); - __ISB(); - dcache_current = __get_MHCR(); - dcache_current &= (0x1<<1); - __DSB(); - __ISB(); - uhs_phy_printf("dcache_current=%lx\r\n",dcache_current); - - if(dcache_current == 0x0) - { - self_cal(datarate); - } - else - { - uhs_phy_printf("dcache disable fail\r\n"); - } - - if (dcache_original == (0x1<<1)) - { - csi_dcache_enable(); - } - - //get dcache end state - __DSB(); - __ISB(); - dcache_end = __get_MHCR(); - dcache_end &= (0x1<<1); - __DSB(); - __ISB(); - if(dcache_end == dcache_original) - { - uhs_phy_printf("dcache state right , dcache_state=%lx\r\n",dcache_end); - } - else - { - uhs_phy_printf("dcache state error\r\n"); - } - - uhs_phy_delay_us(1000); - -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c deleted file mode 100644 index aa0d23b852..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_usb.c +++ /dev/null @@ -1,1939 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_usb.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "bl808_usb.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup USB - * @{ - */ - -/** @defgroup USB_Private_Macros - * @{ - */ - -/*@} end of group USB_Private_Macros */ - -/** @defgroup USB_Private_Types - * @{ - */ - -/*@} end of group USB_Private_Types */ - -/** @defgroup USB_Private_Variables - * @{ - */ - -/*@} end of group USB_Private_Variables */ - -/** @defgroup USB_Global_Variables - * @{ - */ - -/*@} end of group USB_Global_Variables */ - -/** @defgroup USB_Private_Fun_Declaration - * @{ - */ - -/*@} end of group USB_Private_Fun_Declaration */ - -/** @defgroup USB_Private_Functions - * @{ - */ - -/*@} end of group USB_Private_Functions */ - -/** @defgroup USB_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief USB global interrupt enable or disable - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Global_IntEnable(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_GLINT_EN_HOV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_GLINT_EN_HOV); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB global interrupt mask or unmask - * - * @param intType: interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Global_IntMask(USB_GLOBAL_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_GLOBAL_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(USB_BASE, USB_GLB_INT); - - if (intMask == MASK) { - tmpVal = tmpVal | (1 << intType); - } else { - tmpVal = tmpVal & ~(1 << intType); - } - - BL_WR_REG(USB_BASE, USB_GLB_INT, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB global interrupt status - * - * @param intType: interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Global_IntStatus(USB_GLOBAL_INT_Type intType) -{ - CHECK_PARAM(IS_USB_GLOBAL_INT_TYPE(intType)); - - return (BL_RD_REG(USB_BASE, USB_GLB_ISR) & (1 << intType)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief set USB normal configuration - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Normal_Config(USB_NORMAL_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t to = 0; - - if (cfg->swRst) { - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_SFRST_HOV); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - while (BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_SFRST_HOV)) { - if (to >= cfg->rstTimeOut) { - return ERROR; - } - - to++; - } - } - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (cfg->forceFullSpeed) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_FORCE_FS); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_FORCE_FS); - } - - if (cfg->remoteWakeupEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CAP_RMWAKUP); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (cfg->chipEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CHIP_EN_HOV); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_CHIP_EN_HOV); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB device speed - * - * @param None - * - * @return high speed or full speed - * -*******************************************************************************/ -USB_DEVICE_SPEED_Type USB_Get_Device_Speed_Status(void) -{ - return (USB_DEVICE_SPEED_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_HS_EN_HOV); -} - -/****************************************************************************/ /** - * @brief USB go suspend - * - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Go_Suspend(uint8_t enable) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_GOSUSP); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_GOSUSP); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB device address - * - * @param addr: address - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Device_Address(uint8_t addr) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM((addr <= 127)); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DEVADR, addr); - BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB device address - * - * @param None - * - * @return address - * -*******************************************************************************/ -uint8_t USB_Get_Device_Address(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_ADR), USB_DEVADR); -} - -/****************************************************************************/ /** - * @brief USB non-control transfer enable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Non_Ctrl_Transfer_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_AFT_CONF); - BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB non-control transfer disable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Non_Ctrl_Transfer_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ADR); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_AFT_CONF); - BL_WR_REG(USB_BASE, USB_DEV_ADR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB FIFO counters and location counters clear - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Clear_FIFO(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_TST_CLRFF_HOV); - BL_WR_REG(USB_BASE, USB_DEV_TST, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in high speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SOF_Mask_Time_HighSpeed(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_SMT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_SOFMT, USB_SOF_TIMER_MASK_AFTER_RESET_HS); - BL_WR_REG(USB_BASE, USB_DEV_SMT, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in full speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SOF_Mask_Time_FullSpeed(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_SMT); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_SOFMT, USB_SOF_TIMER_MASK_AFTER_RESET_FS); - BL_WR_REG(USB_BASE, USB_DEV_SMT, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in full speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SoftDetach_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_UNPLUG); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB SOF mask timer in full speed - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_SoftDetach_Disable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_PHY_TST); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_UNPLUG); - BL_WR_REG(USB_BASE, USB_PHY_TST, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief is USB FIFOn empty - * - * @param fifoNum: FIFO number - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_FIFO_Empty(USB_FIFO_EMPTY_Type fifoNum) -{ - CHECK_PARAM(IS_USB_FIFO_EMPTY_TYPE(fifoNum)); - - return (BL_RD_REG(USB_BASE, USB_DEV_CXCFE) & (1 << fifoNum)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief is USB control FIFO empty - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_CTRL_FIFO_Empty(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_EMP) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief is USB control FIFO full - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_CTRL_FIFO_Full(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CXCFE), USB_CX_FUL) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief is USB control FIFO full - * - * @param None - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Err_Type USB_Clear_CTRL_FIFO(void) -{ - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, BL_SET_REG_BIT(0, USB_CX_CLR)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB control endpoint stall once - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_CTRL_Endpoint_Stall_Once(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CX_STL); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB control endpoint data transfer done - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_CTRL_Endpoint_Data_Transfer_Done(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CXCFE); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_CX_DONE); - BL_WR_REG(USB_BASE, USB_DEV_CXCFE, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief is USB endpoint receive 0 length data packet - * - * @param epID: endpoint number - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_Endpoint_Receive_Zero_Length_Packet(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - return (BL_RD_REG(USB_BASE, USB_DEV_RXZ) & (1 << (epID - 1))) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief clear USB endpoint receive 0 length data packet - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Clear_Endpoint_Receive_Zero_Length_Packet_Status(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - BL_WR_REG(USB_BASE, USB_DEV_RXZ, 1 << (epID - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reset USB in endpoint data_toggle_sequence - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Reset_Endpoint_IN_Data_Toggle_Sequence(USB_Endpoint_Type epID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - /* calc reg address */ - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + (epID - 1) * 4; - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_IEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* set RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_RSTG_IEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_IEP1); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reset USB out endpoint data_toggle_sequence - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Reset_Endpoint_OUT_Data_Toggle_Sequence(USB_Endpoint_Type epID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - /* calc reg address */ - regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + (epID - 1) * 4; - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_OEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* set RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_RSTG_OEP1); - BL_WR_WORD(regAddr, tmpVal); - - /* clear RSTG_IEPn bit */ - BL_RD_WORD(regAddr); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_RSTG_OEP1); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB endpoint transmit 0 length data packet - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Endpoint_Transmit_Zero_Length_Packet(USB_Endpoint_Type epID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - tmpVal |= (1 << USB_TX0BYTE_IEP1_POS); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief is USB endpoint receive 0 length data packet - * - * @param epID: endpoint number - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Is_Endpoint_Transfer_Zero_Length_Packet(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - return (BL_RD_REG(USB_BASE, USB_DEV_TXZ) & (1 << (epID - 1))) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief clear USB endpoint transfer 0 length data packet status - * - * @param epID: endpoint number - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Clear_Endpoint_Transfer_Zero_Length_Packet_Status(USB_Endpoint_Type epID) -{ - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - BL_WR_REG(USB_BASE, USB_DEV_TXZ, 1 << (epID - 1)); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB IN endpoint stall - * - * @param epID: endpoint number - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_IN_Stall(USB_Endpoint_Type epID, uint8_t enable) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_STL_IEP1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_STL_IEP1); - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB IN endpoint max packet size - * - * @param epID: endpoint number - * @param max: max packet size - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_IN_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM((max <= 0x7FF)); - - regAddr = USB_BASE + USB_DEV_INMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_MAXPS_IEP1, max); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB OUT endpoint stall - * - * @param epID: endpoint number - * @param enable: ENABLE or DISABLE - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_OUT_Stall(USB_Endpoint_Type epID, uint8_t enable) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - - regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - - if (enable) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_STL_OEP1); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_STL_OEP1); - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB OUT endpoint max packet size - * - * @param epID: endpoint number - * @param max: max packet size - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Endpoint_OUT_MaxPacketSize(USB_Endpoint_Type epID, uint16_t max) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM((max <= 0x7FF)); - - regAddr = USB_BASE + USB_DEV_OUTMPS1_OFFSET + 0x04 * (epID - 1); - - tmpVal = BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_MAXPS_OEP1, max); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB FIFO ID of IN endpoint - * - * @param epID: endpoint number - * @param fifoID: FIFO ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_FIFO_Of_Endpoint_IN(USB_Endpoint_Type epID, USB_FIFO_Type fifoID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - if (epID <= USB_Endpoint_4) { - regAddr = USB_BASE + USB_DEV_EPMAP0_OFFSET; - } else { - regAddr = USB_BASE + USB_DEV_EPMAP1_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - - switch (epID) { - case USB_Endpoint_1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP1, fifoID); - break; - - case USB_Endpoint_2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP2, fifoID); - break; - - case USB_Endpoint_3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP3, fifoID); - break; - - case USB_Endpoint_4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP4, fifoID); - break; - - case USB_Endpoint_5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP5, fifoID); - break; - - case USB_Endpoint_6: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP6, fifoID); - break; - - case USB_Endpoint_7: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP7, fifoID); - break; - - case USB_Endpoint_8: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_IEP8, fifoID); - break; - - default: - break; - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB FIFO ID of IN endpoint - * - * @param epID: endpoint number - * @param fifoID: FIFO ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_FIFO_Of_Endpoint_OUT(USB_Endpoint_Type epID, USB_FIFO_Type fifoID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - /* cannot be USB_Endpoint_0 */ - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(epID)); - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - if (epID <= USB_Endpoint_4) { - regAddr = USB_BASE + USB_DEV_EPMAP0_OFFSET; - } else { - regAddr = USB_BASE + USB_DEV_EPMAP1_OFFSET; - } - - tmpVal = BL_RD_WORD(regAddr); - - switch (epID) { - case USB_Endpoint_1: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP1, fifoID); - break; - - case USB_Endpoint_2: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP2, fifoID); - break; - - case USB_Endpoint_3: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP3, fifoID); - break; - - case USB_Endpoint_4: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP4, fifoID); - break; - - case USB_Endpoint_5: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP5, fifoID); - break; - - case USB_Endpoint_6: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP6, fifoID); - break; - - case USB_Endpoint_7: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP7, fifoID); - break; - - case USB_Endpoint_8: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_FNO_OEP8, fifoID); - break; - - default: - break; - } - - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB FIFO configuration - * - * @param fifoID: FIFO ID - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_FIFO_Config(USB_FIFO_Type fifoID, USB_FIFO_Cfg_Type *cfg) -{ - uint32_t tmpVal1 = 0; - uint32_t tmpVal2 = 0; - uint32_t en = 0; - - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - CHECK_PARAM(IS_USB_FIFO_DIR_TYPE(cfg->dir)); - CHECK_PARAM(IS_USB_ENDPOINT_TYPE(cfg->epID)); - CHECK_PARAM(IS_USB_FIFO_BLOCK_MAX_SIZE_TYPE(cfg->blockSize)); - CHECK_PARAM(IS_USB_FIFO_BLOCK_CNT_TYPE(cfg->blockType)); - CHECK_PARAM(IS_USB_FIFO_TRANSFER_TYPE(cfg->fifoType)); - - tmpVal1 = BL_RD_REG(USB_BASE, USB_DEV_FMAP); - tmpVal2 = BL_RD_REG(USB_BASE, USB_DEV_FCFG); - - if (cfg->enable) { - en = 1; - } - - switch (fifoID) { - case USB_FIFO_0: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO0, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO0, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F0, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F0, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F0, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F0, cfg->fifoType); - break; - - case USB_FIFO_1: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO1, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO1, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F1, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F1, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F1, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F1, cfg->fifoType); - break; - - case USB_FIFO_2: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO2, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO2, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F2, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F2, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F2, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F2, cfg->fifoType); - break; - - case USB_FIFO_3: - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_DIR_FIFO3, cfg->dir); - tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, USB_EPNO_FIFO3, cfg->epID); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_EN_F3, en); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKSZ_F3, cfg->blockSize); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLKNO_F3, cfg->blockType); - tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, USB_BLK_TYP_F3, cfg->fifoType); - break; - - default: - break; - } - - BL_WR_REG(USB_BASE, USB_DEV_FMAP, tmpVal1); - BL_WR_REG(USB_BASE, USB_DEV_FCFG, tmpVal2); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief reset USB FIFO - * - * @param fifoID: FIFO ID - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Reset_FIFO(USB_FIFO_Type fifoID) -{ - uint32_t tmpVal = 0; - uint32_t regAddr = 0; - - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - regAddr = USB_BASE + USB_DEV_FIBC0_OFFSET + 0x04 * fifoID; - - tmpVal = BL_RD_WORD(regAddr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_FFRST0_HOV); - BL_WR_WORD(regAddr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB out FIFO count - * - * @param fifoID: FIFO ID - * - * @return FIFO count - * -*******************************************************************************/ -uint16_t USB_Get_OUT_FIFO_Count(USB_FIFO_Type fifoID) -{ - uint32_t regAddr = 0; - - CHECK_PARAM(IS_USB_FIFO_TYPE(fifoID)); - - regAddr = USB_BASE + USB_DEV_FIBC0_OFFSET + 0x04 * fifoID; - - return BL_GET_REG_BITS_VAL(BL_RD_WORD(regAddr), USB_BC_F0); -} - -/****************************************************************************/ /** - * @brief set USB dma configuration - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_DMA_Config(USB_DMA_TARGET_FIFO_Type fifoN, USB_DMA_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_DMA_TRANS_DIR_TYPE(cfg->dir)); - CHECK_PARAM(IS_USB_DMA_TARGET_FIFO_TYPE(fifoN)); - CHECK_PARAM(((cfg->length) <= 0x1FFFF)); - - switch (fifoN) { - case USB_DMA_TARGET_FIFO_CTRL: - tmpVal = (1 << 4); - break; - case USB_DMA_TARGET_FIFO_0: - tmpVal = (1 << 0); - break; - case USB_DMA_TARGET_FIFO_1: - tmpVal = (1 << 1); - break; - case USB_DMA_TARGET_FIFO_2: - tmpVal = (1 << 2); - break; - case USB_DMA_TARGET_FIFO_3: - tmpVal = (1 << 3); - break; - default: - break; - } - BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1); - - switch (cfg->dir) { - case USB_DMA_TRANS_DIR_FIFO_2_MEM: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 0); - break; - - case USB_DMA_TRANS_DIR_MEM_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 1); - break; - - case USB_DMA_TRANS_DIR_FIFO_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_IO_HOV, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_TYPE_HOV, 0); - - if ((cfg->length) & 0x3) { - return ERROR; - } - - break; - - default: - break; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_LEN_HOV, cfg->length); - BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal); - - BL_WR_REG(USB_BASE, USB_DMA_CPS2, cfg->memAddr); - - return SUCCESS; -} -/****************************************************************************/ /** - * @brief reset usb dma accessing fifo - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -void USB_Reset_DMA_Accessing_Fifo(void) -{ - BL_WR_REG(USB_BASE, USB_DMA_TFN, 0); -} -/****************************************************************************/ /** - * @brief update USB dma transmit configuration - * - * @param memAddr: memory address - * @param length: transmit length - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Update_DMA_Trans(uint32_t memAddr, uint32_t length) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_DMA_LEN_HOV, length); - BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal); - - BL_WR_REG(USB_BASE, USB_DMA_CPS2, memAddr); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB dma transmit start - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_DMA_Start(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_CPS1); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_DMA_START_HOV); - BL_WR_REG(USB_BASE, USB_DMA_CPS1, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB setup command - * - * @param setup[2]: buffer - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Setup_Command(uint32_t setup[2]) -{ - uint32_t tmpVal = 0; - - if (NULL == setup) { - return ERROR; - } - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_TFN); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_ACC_CXF_HOV); - BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal); - - setup[0] = BL_RD_REG(USB_BASE, USB_DMA_CPS3); - setup[1] = BL_RD_REG(USB_BASE, USB_DMA_CPS3); - - tmpVal = BL_RD_REG(USB_BASE, USB_DMA_TFN); - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_ACC_CXF_HOV); - BL_WR_REG(USB_BASE, USB_DMA_TFN, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB vdma configuration - * - * @param fifoN: target FIFO - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_VDMA_Config(USB_VDMA_TARGET_FIFO_Type fifoN, USB_VDMA_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - uint32_t setting1Addr = 0; - uint32_t setting2Addr = 0; - - CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN)); - CHECK_PARAM(IS_USB_VDMA_TRANS_DIR_TYPE(cfg->dir)); - CHECK_PARAM(((cfg->length) <= 0x1FFFF)); - - setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 0x08 * (fifoN); - setting2Addr = USB_BASE + USB_VDMA_CXFPS2_OFFSET + 0x08 * (fifoN); - tmpVal = BL_RD_WORD(setting1Addr); - - switch (cfg->dir) { - case USB_VDMA_TRANS_DIR_FIFO_2_MEM: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 0); - break; - - case USB_VDMA_TRANS_DIR_MEM_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 0); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 1); - break; - - case USB_VDMA_TRANS_DIR_FIFO_2_FIFO: - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_IO_CXF, 1); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_TYPE_CXF, 0); - - if ((cfg->length) & 0x3) { - return ERROR; - } - - break; - - default: - break; - } - - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_VDMA_LEN_CXF, cfg->length); - BL_WR_WORD(setting1Addr, tmpVal); - - BL_WR_WORD(setting2Addr, cfg->memAddr); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB vdma transmit start - * - * @param fifoN: target FIFO - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN) -{ - uint32_t tmpVal = 0; - uint32_t setting1Addr = 0; - - CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN)); - - setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 0x08 * (fifoN); - - tmpVal = BL_RD_WORD(setting1Addr); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_VDMA_START_CXF); - BL_WR_WORD(setting1Addr, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB vdma transmit start status - * - * @param fifoN: target FIFO - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Get_VDMA_Start(USB_VDMA_TARGET_FIFO_Type fifoN) -{ - uint32_t setting1Addr = 0; - - CHECK_PARAM(IS_USB_VDMA_TARGET_FIFO_TYPE(fifoN)); - - setting1Addr = USB_BASE + USB_VDMA_CXFPS1_OFFSET + 8 * (fifoN); - - return BL_GET_REG_BITS_VAL(BL_RD_WORD(setting1Addr), USB_VDMA_START_CXF) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief USB vdma multi channel function enable - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_VDMA_Enable(void) -{ - uint32_t tmpVal = 0; - - tmpVal = BL_RD_REG(USB_BASE, USB_VDMA_CTRL); - tmpVal = BL_SET_REG_BIT(tmpVal, USB_VDMA_EN); - BL_WR_REG(USB_BASE, USB_VDMA_CTRL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB LPM configuration - * - * @param cfg: configuration - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_LPM_Config(USB_LPM_Cfg_Type *cfg) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_LPM_RESP_TYPE(cfg->resp)); - - tmpVal = BL_RD_REG(USB_BASE, USB_LPM_CAP); - - if (cfg->lpmWakeUpEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_LPM_WAKEUP_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_LPM_WAKEUP_EN); - } - - BL_WR_REG(USB_BASE, USB_LPM_CAP, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_ACCEPT, cfg->resp); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_BESL_MIN, cfg->minBesl); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_LPM_BESL_MAX, cfg->maxBesl); - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_CTL); - - if (cfg->lpmEn) { - tmpVal = BL_SET_REG_BIT(tmpVal, USB_LPM_EN); - } else { - tmpVal = BL_CLR_REG_BIT(tmpVal, USB_LPM_EN); - } - - BL_WR_REG(USB_BASE, USB_DEV_CTL, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief set USB LPM configuration - * - * @param None - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -uint8_t USB_Get_LPM_BESL(void) -{ - return BL_GET_REG_BITS_VAL(BL_RD_REG(USB_BASE, USB_DEV_CTL), USB_LPM_BESL); -} - -/****************************************************************************/ /** - * @brief set suspend delay - * - * @param ms: delay ms count - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Set_Suspend_Delay(uint8_t ms) -{ - uint32_t tmpVal; - - CHECK_PARAM((ms <= 7)); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_ICR); - tmpVal = BL_SET_REG_BITS_VAL(tmpVal, USB_IDLE_CNT, ms); - BL_WR_REG(USB_BASE, USB_DEV_ICR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB group interrupt mask or unmask - * - * @param intType: interrupt type - * @param intMask: MASK or UNMASK - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Group_IntMask(USB_GRP_INT_Type intType, BL_Mask_Type intMask) -{ - uint32_t tmpVal = 0; - - CHECK_PARAM(IS_USB_GRP_INT_TYPE(intType)); - - tmpVal = BL_RD_REG(USB_BASE, USB_DEV_MIGR); - - if (intMask == MASK) { - tmpVal = tmpVal | (1 << intType); - } else { - tmpVal = tmpVal & ~(1 << intType); - } - - BL_WR_REG(USB_BASE, USB_DEV_MIGR, tmpVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB group interrupt status - * - * @param intType: interrupt type - * - * @return SET or RESET - * -*******************************************************************************/ -BL_Sts_Type USB_Group_IntStatus(USB_GRP_INT_Type intType) -{ - CHECK_PARAM(IS_USB_GRP_INT_TYPE(intType)); - - return (BL_RD_REG(USB_BASE, USB_DEV_IGR) & (1 << intType)) ? SET : RESET; -} - -/****************************************************************************/ /** - * @brief USB mask sub group interrupt - * - * @param intType: interrupt type, USB_INT_CX_SETUP | USB_INT_CX_IN | ... - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Sub_Group_IntMask(uint64_t intType) -{ - uint64_t val = intType; - uint32_t bit = 0; - uint32_t tmpValG0 = BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET); - uint32_t tmpValG1 = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); - uint32_t tmpValG2 = BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET); - uint32_t tmpValG3 = BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET); - uint32_t tmpValG4 = BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET); - - while (0 == arch_ctzll(&val, &bit)) { - val &= ~(((uint64_t)1) << bit); - switch (bit) { - case USB_SUB_GRP0_INT_CX_SETUP: - tmpValG0 |= (1 << USB_MCX_SETUP_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_IN: - tmpValG0 |= (1 << USB_MCX_IN_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_OUT: - tmpValG0 |= (1 << USB_MCX_OUT_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMFAIL: - tmpValG0 |= (1 << USB_MCX_COMFAIL_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMABORT: - tmpValG0 |= (1 << USB_MCX_COMABORT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_OUT: - tmpValG1 |= (1 << USB_MF0_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_SPK: - tmpValG1 |= (1 << USB_MF0_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_OUT: - tmpValG1 |= (1 << USB_MF1_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_SPK: - tmpValG1 |= (1 << USB_MF1_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_OUT: - tmpValG1 |= (1 << USB_MF2_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_SPK: - tmpValG1 |= (1 << USB_MF2_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_OUT: - tmpValG1 |= (1 << USB_MF3_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_SPK: - tmpValG1 |= (1 << USB_MF3_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_IN: - tmpValG1 |= (1 << USB_MF0_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_IN: - tmpValG1 |= (1 << USB_MF1_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_IN: - tmpValG1 |= (1 << USB_MF2_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_IN: - tmpValG1 |= (1 << USB_MF3_IN_INT_POS); - break; - case USB_SUB_GRP2_INT_RESET: - tmpValG2 |= (1 << USB_MUSBRST_INT_POS); - break; - case USB_SUB_GRP2_INT_SUSPEND: - tmpValG2 |= (1 << USB_MSUSP_INT_POS); - break; - case USB_SUB_GRP2_INT_RESUME: - tmpValG2 |= (1 << USB_MRESM_INT_POS); - break; - case USB_SUB_GRP2_INT_TX0BYTE: - tmpValG2 |= (1 << USB_MTX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_RX0BYTE: - tmpValG2 |= (1 << USB_MRX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_DMA_CMPLT: - tmpValG2 |= (1 << USB_MDMA_CMPLT_HOV_POS); - break; - case USB_SUB_GRP2_INT_DMA_ERROR: - tmpValG2 |= (1 << USB_MDMA_ERROR_HOV_POS); - break; - case USB_SUB_GRP2_INT_IDLE: - tmpValG2 |= (1 << USB_MDEV_IDLE_HOV_POS); - break; - case USB_SUB_GRP2_INT_WAKEUP_BY_VBUS: - tmpValG2 |= (1 << USB_MDEV_WAKEUP_BYVBUS_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_CXF: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F0: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F1: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F2: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F3: - tmpValG3 |= (1 << USB_MVDMA_CMPLT_F3_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_CXF: - tmpValG3 |= (1 << USB_MVDMA_ERROR_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F0: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F1: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F2: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F3: - tmpValG3 |= (1 << USB_MVDMA_ERROR_F3_POS); - break; - case USB_SUB_GRP4_INT_L1: - tmpValG4 |= (1 << USB_ML1_INT_POS); - break; - default: - break; - } - } - BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, tmpValG0); - BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmpValG1); - BL_WR_WORD(USB_BASE + USB_DEV_MISG2_OFFSET, tmpValG2); - BL_WR_WORD(USB_BASE + USB_DEV_MISG3_OFFSET, tmpValG3); - BL_WR_WORD(USB_BASE + USB_DEV_MISG4_OFFSET, tmpValG4); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief USB unmask sub group interrupt - * - * @param intType: interrupt type, USB_INT_CX_SETUP | USB_INT_CX_IN | ... - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Sub_Group_IntUnmask(uint64_t intType) -{ - uint64_t val = intType; - uint32_t bit = 0; - uint32_t tmpValG0 = BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET); - uint32_t tmpValG1 = BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); - uint32_t tmpValG2 = BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET); - uint32_t tmpValG3 = BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET); - uint32_t tmpValG4 = BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET); - - while (0 == arch_ctzll(&val, &bit)) { - val &= ~(((uint64_t)1) << bit); - switch (bit) { - case USB_SUB_GRP0_INT_CX_SETUP: - tmpValG0 &= ~(1 << USB_MCX_SETUP_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_IN: - tmpValG0 &= ~(1 << USB_MCX_IN_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_OUT: - tmpValG0 &= ~(1 << USB_MCX_OUT_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMFAIL: - tmpValG0 &= ~(1 << USB_MCX_COMFAIL_INT_POS); - break; - case USB_SUB_GRP0_INT_CX_COMABORT: - tmpValG0 &= ~(1 << USB_MCX_COMABORT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_OUT: - tmpValG1 &= ~(1 << USB_MF0_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_SPK: - tmpValG1 &= ~(1 << USB_MF0_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_OUT: - tmpValG1 &= ~(1 << USB_MF1_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_SPK: - tmpValG1 &= ~(1 << USB_MF1_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_OUT: - tmpValG1 &= ~(1 << USB_MF2_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_SPK: - tmpValG1 &= ~(1 << USB_MF2_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_OUT: - tmpValG1 &= ~(1 << USB_MF3_OUT_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_SPK: - tmpValG1 &= ~(1 << USB_MF3_SPK_INT_POS); - break; - case USB_SUB_GRP1_INT_F0_IN: - tmpValG1 &= ~(1 << USB_MF0_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F1_IN: - tmpValG1 &= ~(1 << USB_MF1_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F2_IN: - tmpValG1 &= ~(1 << USB_MF2_IN_INT_POS); - break; - case USB_SUB_GRP1_INT_F3_IN: - tmpValG1 &= ~(1 << USB_MF3_IN_INT_POS); - break; - case USB_SUB_GRP2_INT_RESET: - tmpValG2 &= ~(1 << USB_MUSBRST_INT_POS); - break; - case USB_SUB_GRP2_INT_SUSPEND: - tmpValG2 &= ~(1 << USB_MSUSP_INT_POS); - break; - case USB_SUB_GRP2_INT_RESUME: - tmpValG2 &= ~(1 << USB_MRESM_INT_POS); - break; - case USB_SUB_GRP2_INT_TX0BYTE: - tmpValG2 &= ~(1 << USB_MTX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_RX0BYTE: - tmpValG2 &= ~(1 << USB_MRX0BYTE_INT_POS); - break; - case USB_SUB_GRP2_INT_DMA_CMPLT: - tmpValG2 &= ~(1 << USB_MDMA_CMPLT_HOV_POS); - break; - case USB_SUB_GRP2_INT_DMA_ERROR: - tmpValG2 &= ~(1 << USB_MDMA_ERROR_HOV_POS); - break; - case USB_SUB_GRP2_INT_IDLE: - tmpValG2 &= ~(1 << USB_MDEV_IDLE_HOV_POS); - break; - case USB_SUB_GRP2_INT_WAKEUP_BY_VBUS: - tmpValG2 &= ~(1 << USB_MDEV_WAKEUP_BYVBUS_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_CXF: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F0: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F1: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F2: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_CMPLT_F3: - tmpValG3 &= ~(1 << USB_MVDMA_CMPLT_F3_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_CXF: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_CXF_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F0: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F0_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F1: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F1_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F2: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F2_POS); - break; - case USB_SUB_GRP3_INT_VDMA_ERROR_F3: - tmpValG3 &= ~(1 << USB_MVDMA_ERROR_F3_POS); - break; - case USB_SUB_GRP4_INT_L1: - tmpValG4 &= ~(1 << USB_ML1_INT_POS); - break; - default: - break; - } - } - BL_WR_WORD(USB_BASE + USB_DEV_MISG0_OFFSET, tmpValG0); - BL_WR_WORD(USB_BASE + USB_DEV_MISG1_OFFSET, tmpValG1); - BL_WR_WORD(USB_BASE + USB_DEV_MISG2_OFFSET, tmpValG2); - BL_WR_WORD(USB_BASE + USB_DEV_MISG3_OFFSET, tmpValG3); - BL_WR_WORD(USB_BASE + USB_DEV_MISG4_OFFSET, tmpValG4); - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief get USB sub group 0 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_0_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG0_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 1 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_1_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG1_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 2 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_2_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG2_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 3 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_3_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG3_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 4 interrupt status - * - * @param None - * - * @return interrupt status - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_4_IntStatus(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_ISG4_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 0 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_0_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG0_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 1 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_1_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG1_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 2 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_2_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG2_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 3 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_3_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG3_OFFSET); -} - -/****************************************************************************/ /** - * @brief get USB sub group 4 interrupt mask - * - * @param None - * - * @return interrupt mask - * -*******************************************************************************/ -uint32_t USB_Get_Sub_Group_4_IntMask(void) -{ - return BL_RD_WORD(USB_BASE + USB_DEV_MISG4_OFFSET); -} - -/****************************************************************************/ /** - * @brief clear USB sub group 0 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_0_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG0_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 1 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_1_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG1_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 2 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_2_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG2_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 3 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_3_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG3_OFFSET, clrVal); - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief clear USB sub group 4 interrupt status - * - * @param clrVal: clear value - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -BL_Err_Type USB_Get_Sub_Group_4_IntClear(uint32_t clrVal) -{ - BL_WR_WORD(USB_BASE + USB_DEV_ISG4_OFFSET, clrVal); - - return SUCCESS; -} - -/*@} end of group USB_Public_Functions */ - -/*@} end of group USB */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c deleted file mode 100644 index b6c7b11c98..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_xip_sflash.c +++ /dev/null @@ -1,469 +0,0 @@ -/** - ****************************************************************************** - * @file bl808_xip_sflash.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "string.h" -#include "bl808_xip_sflash.h" - -/** @addtogroup BL808_Peripheral_Driver - * @{ - */ - -/** @addtogroup XIP_SFLASH - * @{ - */ - -/** @defgroup XIP_SFLASH_Private_Macros - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Macros */ - -/** @defgroup XIP_SFLASH_Private_Types - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Types */ - -/** @defgroup XIP_SFLASH_Private_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Variables */ - -/** @defgroup XIP_SFLASH_Global_Variables - * @{ - */ - -/*@} end of group XIP_SFLASH_Global_Variables */ - -/** @defgroup XIP_SFLASH_Private_Fun_Declaration - * @{ - */ - -/*@} end of group XIP_SFLASH_Private_Fun_Declaration */ - -/** @defgroup XIP_SFLASH_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Save flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset pointer - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - /* XIP_SFlash_Delay */ - volatile uint32_t i = 32 * 2; - - while (i--) - ; - - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Replace(SF_CTRL_PAD2); - } - SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB); - /* Exit form continous read for accepting command */ - SFlash_Reset_Continue_Read(pFlashCfg); - /* For disable command that is setting register instaed of send command, we need write enable */ - SFlash_DisableBurstWrap(pFlashCfg); - /* Enable 32Bits addr mode again in case reset command make it reset */ - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - if ((pFlashCfg->ioMode & 0x0f) == SF_CTRL_QO_MODE || (pFlashCfg->ioMode & 0x0f) == SF_CTRL_QIO_MODE) { - /* Enable QE again in case reset command make it reset */ - SFlash_Qspi_Enable(pFlashCfg); - } - /* Deburst again to make sure */ - SFlash_DisableBurstWrap(pFlashCfg); - - /* Clear offset setting*/ - *offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Restore flash controller state - * - * @param pFlashCfg: Flash config pointer - * @param offset: CPU XIP flash offset - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t tmp[1]; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank); - - if(((pFlashCfg->ioMode>>4)&0x01) == 0) { - if((pFlashCfg->ioMode&0x0f)==SF_CTRL_QO_MODE || (pFlashCfg->ioMode&0x0f)==SF_CTRL_QIO_MODE) { - SFlash_SetBurstWrap(pFlashCfg); - } - } - SFlash_Set32BitsAddrMode(pFlashCfg, ENABLE); - SFlash_Read(pFlashCfg, ioMode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp)); - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - if (bank == SF_CTRL_FLASH_BANK1) { - SF_Ctrl_Sbus2_Revoke_replace(); - } - - return SUCCESS; -} -#endif - -/*@} end of group XIP_SFLASH_Private_Functions */ - -/** @defgroup XIP_SFLASH_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Erase flash one region - * - * @param pFlashCfg: Flash config pointer - * @param startaddr: start address to erase - * @param len: data length to erase - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Erase(pFlashCfg, startaddr, startaddr + len - 1); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Program flash one region - * - * @param pFlashCfg: Flash config pointer - * @param addr: start address to be programed - * @param data: data pointer to be programed - * @param len: data length to be programed - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Program(pFlashCfg, ioMode, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash - * - * @param pFlashCfg: Flash config pointer - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - stat = SFlash_Read(pFlashCfg, ioMode, 0, addr, data, len); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return stat; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Jedec ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Jedec ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetJedecId(pFlashCfg, data); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Device ID - * - * @param pFlashCfg: Flash config pointer - * @param is32BitsAddr: Is flash addr mode in 32-bits - * @param data: data pointer to store Device ID Read from flash - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetDeviceId(data, is32BitsAddr); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Get Flash Unique ID - * - * @param pFlashCfg: Flash config pointer - * @param data: data pointer to store Device ID Read from flash - * @param idLen: Unique id len - * @param group: CPU group id 0 or 1 - * @param bank: Flash bank select - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - BL_Err_Type stat; - uint32_t offset; - uint8_t aesEnable = 0; - SF_Ctrl_IO_Type ioMode = (SF_Ctrl_IO_Type)pFlashCfg->ioMode & 0xf; - - XIP_SFlash_Opt_Enter(&aesEnable); - stat = XIP_SFlash_State_Save(pFlashCfg, &offset, group, bank); - - if (stat != SUCCESS) { - SFlash_Set_IDbus_Cfg(pFlashCfg, ioMode, 1, 0, 32, bank); - } else { - SFlash_GetUniqueId(data, idLen); - XIP_SFlash_State_Restore(pFlashCfg, offset, group, bank); - } - - XIP_SFlash_Opt_Exit(aesEnable); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief Read data from flash via XIP - * - * @param addr: flash read start address - * @param data: data pointer to store data read from flash - * @param len: data length to read - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -#ifndef BFLB_USE_ROM_DRIVER -__WEAK -BL_Err_Type ATTR_TCM_SECTION XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len, - uint8_t group, SF_Ctrl_Bank_Select bank) -{ - uint32_t offset; - - addr = addr & (BL808_FLASH_XIP_END-BL808_FLASH_XIP_BASE-1); - addr |= BL808_FLASH_XIP_BASE; - - offset = SF_Ctrl_Get_Flash_Image_Offset(group, bank); - SF_Ctrl_Set_Flash_Image_Offset(0, group, bank); - /* Flash read */ - ARCH_MemCpy_Fast(data, (void *)(uintptr_t)(addr), len); - SF_Ctrl_Set_Flash_Image_Offset(offset, group, bank); - - return SUCCESS; -} -#endif - -/****************************************************************************/ /** - * @brief XIP SFlash option save - * - * @param aesEnable: AES enable status pointer - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Enter(uint8_t *aesEnable) -{ - *aesEnable = SF_Ctrl_Is_AES_Enable(); - - if (*aesEnable) { - SF_Ctrl_AES_Disable(); - } -} - -/****************************************************************************/ /** - * @brief XIP SFlash option restore - * - * @param aesEnable: AES enable status - * - * @return None - * -*******************************************************************************/ -__WEAK -void ATTR_TCM_SECTION XIP_SFlash_Opt_Exit(uint8_t aesEnable) -{ - if (aesEnable) { - SF_Ctrl_AES_Enable(); - } -} - -/*@} end of group XIP_SFLASH_Public_Functions */ - -/*@} end of group XIP_SFLASH */ - -/*@} end of group BL808_Peripheral_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c deleted file mode 100644 index 05c627927f..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.c +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file arm_dsp_wrapper.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "arm_dsp_wrapper.h" - -void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize) -{ - uint32_t blkCnt = blockSize >> 2u; - - float32_t in1 = value; - float32_t in2 = value; - float32_t in3 = value; - float32_t in4 = value; - - while (blkCnt > 0u) { - *pDst++ = in1; - *pDst++ = in2; - *pDst++ = in3; - *pDst++ = in4; - - blkCnt--; - } - - blkCnt = blockSize % 0x4u; - - while (blkCnt > 0u) { - *pDst++ = value; - blkCnt--; - } -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h deleted file mode 100644 index 45c87cd526..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/bl_math/arm_dsp_wrapper.h +++ /dev/null @@ -1,44 +0,0 @@ -/** - * @file arm_dsp_wrapper.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __MY_MATH_F_H__ -#define __MY_MATH_F_H__ - -#include "misc.h" -#include "math.h" - -typedef float float32_t; - -__INLINE__ float32_t arm_sqrt_f32(float32_t x) -{ - return sqrtf(x); -} - -__INLINE__ float32_t arm_cos_f32(float32_t x) -{ - return cosf(x); -} - -void arm_fill_f32(float32_t value, float32_t *pDst, uint32_t blockSize); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c deleted file mode 100644 index e746501e0c..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.c +++ /dev/null @@ -1,294 +0,0 @@ -/** - * @file drv_device.c - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "drv_device.h" - -#define DEVICE_CHECK_PARAM - -#define dev_open (dev->open) -#define dev_close (dev->close) -#define dev_read (dev->read) -#define dev_write (dev->write) -#define dev_control (dev->control) - -dlist_t device_head = DLIST_OBJECT_INIT(device_head); - -/** - * This function get device list header - * - * @param None - * - * @return device header - */ -dlist_t *device_get_list_header(void) -{ - return &device_head; -} - -/** - * This function registers a device driver with specified name. - * - * @param dev the pointer of device driver structure - * @param name the device driver's name - * @param flags the capabilities flag of device - * - * @return the error code, DEVICE_EOK on initialization successfully. - */ -int device_register(struct device *dev, const char *name) -{ - dlist_t *node; - - dlist_for_each(node, &device_head) - { - struct device *dev_obj; - dev_obj = dlist_entry(node, struct device, list); - - if (dev_obj == dev) { - return -DEVICE_EEXIST; - } - } - - strcpy(dev->name, name); - - dlist_insert_after(&device_head, &(dev->list)); - dev->status = DEVICE_REGISTERED; - return DEVICE_EOK; -} - -/** - * This function unregisters a device driver with specified name. - * - * @param dev the pointer of device driver structure - * @param name the device driver's name - * @param flags the capabilities flag of device - * - * @return the error code, DEVICE_EOK on initialization successfully. - */ -int device_unregister(const char *name) -{ - struct device *dev = device_find(name); - - if (!dev) { - return -DEVICE_ENODEV; - } - dev->status = DEVICE_UNREGISTER; - /* remove from old list */ - dlist_remove(&(dev->list)); - return DEVICE_EOK; -} - -/** - * This function finds a device driver by specified name. - * - * @param name the device driver's name - * - * @return the registered device driver on successful, or NULL on failure. - */ -struct device *device_find(const char *name) -{ - struct device *dev; - dlist_t *node; - - dlist_for_each(node, &device_head) - { - dev = dlist_entry(node, struct device, list); - - if (strncmp(dev->name, name, DEVICE_NAME_MAX) == 0) { - return dev; - } - } - return NULL; -} - -/** - * This function will open a device - * - * @param dev the pointer of device driver structure - * @param oflag the flags for device open - * - * @return the result - */ -int device_open(struct device *dev, uint16_t oflag) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if ((dev->status == DEVICE_REGISTERED) || (dev->status == DEVICE_CLOSED)) { - if (dev_open != NULL) { - retval = dev_open(dev, oflag); - dev->status = DEVICE_OPENED; - dev->oflag |= oflag; - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_open(dev, oflag); -#endif -} -/** - * This function will close a device - * - * @param dev the pointer of device driver structure - * - * @return the result - */ -int device_close(struct device *dev) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status == DEVICE_OPENED) { - if (dev_close != NULL) { - retval = dev_close(dev); - dev->status = DEVICE_CLOSED; - dev->oflag = 0; - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_close(dev); -#endif -} -/** - * This function will perform a variety of control functions on devices. - * - * @param dev the pointer of device driver structure - * @param cmd the command sent to device - * @param arg the argument of command - * - * @return the result - */ -int device_control(struct device *dev, int cmd, void *args) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status > DEVICE_UNREGISTER) { - if (dev_control != NULL) { - retval = dev_control(dev, cmd, args); - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_control(dev, cmd, args); -#endif -} -/** - * This function will write some data to a device. - * - * @param dev the pointer of device driver structure - * @param pos the position of written - * @param buffer the data buffer to be written to device - * @param size the size of buffer - * - * @return the actually written size on successful, otherwise negative returned. - */ -int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status == DEVICE_OPENED) { - if (dev_write != NULL) { - retval = dev_write(dev, pos, buffer, size); - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_write(dev, pos, buffer, size); -#endif -} -/** - * This function will read some data from a device. - * - * @param dev the pointer of device driver structure - * @param pos the position of reading - * @param buffer the data buffer to save read data - * @param size the size of buffer - * - * @return the actually read size on successful, otherwise negative returned. - */ -int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size) -{ -#ifdef DEVICE_CHECK_PARAM - int retval = DEVICE_EOK; - - if (dev->status == DEVICE_OPENED) { - if (dev_read != NULL) { - retval = dev_read(dev, pos, buffer, size); - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -#else - return dev_read(dev, pos, buffer, size); -#endif -} -/** - * This function will read some data from a device. - * - * @param dev the pointer of device driver structure - * @param pos the position of reading - * @param buffer the data buffer to save read data - * @param size the size of buffer - * - * @return the actually read size on successful, otherwise negative returned. - */ -int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)) -{ - int retval = DEVICE_EOK; - - if (dev->status > DEVICE_UNREGISTER) { - if (callback != NULL) { - dev->callback = callback; - } else { - retval = -DEVICE_EFAULT; - } - } else { - retval = -DEVICE_EINVAL; - } - - return retval; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h deleted file mode 100644 index 82053757a4..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/device/drv_device.h +++ /dev/null @@ -1,135 +0,0 @@ -/** - * @file drv_device.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __DRV_DEVICE_H__ -#define __DRV_DEVICE_H__ - -#include "drv_list.h" -#include "stdio.h" - -#define DEVICE_NAME_MAX 20 /* max device name*/ - -#define DEVICE_OFLAG_DEFAULT 0x000 /* open with default */ -#define DEVICE_OFLAG_STREAM_TX 0x001 /* open with poll tx */ -#define DEVICE_OFLAG_STREAM_RX 0x002 /* open with poll rx */ -#define DEVICE_OFLAG_INT_TX 0x004 /* open with interrupt tx */ -#define DEVICE_OFLAG_INT_RX 0x008 /* open with interrupt rx */ -#define DEVICE_OFLAG_DMA_TX 0x010 /* open with dma tx */ -#define DEVICE_OFLAG_DMA_RX 0x020 /* open with dma rx */ - -#define DEVICE_CTRL_SET_INT 0x01 /* set interrupt */ -#define DEVICE_CTRL_CLR_INT 0x02 /* clear interrupt */ -#define DEVICE_CTRL_GET_INT 0x03 /* get interrupt status*/ -#define DEVICE_CTRL_RESUME 0x04 /* resume device */ -#define DEVICE_CTRL_SUSPEND 0x05 /* suspend device */ -#define DEVICE_CTRL_CONFIG 0x06 /* config device */ -#define DEVICE_CTRL_GET_CONFIG 0x07 /* get device configuration */ -#define DEVICE_CTRL_ATTACH_TX_DMA 0x08 /* deivce link tx dma */ -#define DEVICE_CTRL_ATTACH_RX_DMA 0x09 /* deivce link rx dma */ -#define DEVICE_CTRL_TX_DMA_SUSPEND 0x0a /* deivce suspend tx dma */ -#define DEVICE_CTRL_RX_DMA_SUSPEND 0x0b /* deivce suspend rx dma */ -#define DEVICE_CTRL_TX_DMA_RESUME 0x0c /* deivce resume tx dma */ -#define DEVICE_CTRL_RX_DMA_RESUME 0x0d /* deivce resume rx dma */ -#define DEVICE_CTRL_RESVD1 0x0E -#define DEVICE_CTRL_RESVD2 0x0F - -/* - * POSIX Error codes - */ - -#define DEVICE_EOK 0 -#define DEVICE_EFAULT 14 /* Bad address */ -#define DEVICE_EEXIST 17 /* device exists */ -#define DEVICE_ENODEV 19 /* No such device */ -#define DEVICE_EINVAL 22 /* Invalid argument */ -#define DEVICE_ENOSPACE 23 /* No more Device for Allocate */ - -#define __ASSERT_PRINT(fmt, ...) printf(fmt, ##__VA_ARGS__) - -#define __ASSERT_LOC(test) \ - __ASSERT_PRINT("ASSERTION FAIL [%s] @ %s:%d\n", \ - #test, \ - __FILE__, __LINE__) - -#define DEVICE_ASSERT(test, fmt, ...) \ - do { \ - if (!(test)) { \ - __ASSERT_LOC(test); \ - __ASSERT_PRINT(fmt, ##__VA_ARGS__); \ - } \ - } while (0) - -enum device_class_type { - DEVICE_CLASS_NONE = 0, - DEVICE_CLASS_GPIO, - DEVICE_CLASS_UART, - DEVICE_CLASS_SPI, - DEVICE_CLASS_I2C, - DEVICE_CLASS_ADC, - DEVICE_CLASS_DAC, - DEVICE_CLASS_DMA, - DEVICE_CLASS_TIMER, - DEVICE_CLASS_PWM, - DEVICE_CLASS_QDEC, - DEVICE_CLASS_SDIO, - DEVICE_CLASS_USB, - DEVICE_CLASS_RMII, - DEVICE_CLASS_I2S, - DEVICE_CLASS_CAMERA, - DEVICE_CLASS_SEC_HASH, - DEVICE_CLASS_KEYSCAN, -}; - -enum device_status_type { - DEVICE_UNREGISTER = 0, - DEVICE_REGISTERED, - DEVICE_OPENED, - DEVICE_CLOSED -}; - -struct device { - char name[DEVICE_NAME_MAX]; /*name of device */ - dlist_t list; /*list node of device */ - enum device_status_type status; /*status of device */ - enum device_class_type type; /*type of device */ - uint16_t oflag; /*oflag of device */ - - int (*open)(struct device *dev, uint16_t oflag); - int (*close)(struct device *dev); - int (*control)(struct device *dev, int cmd, void *args); - int (*write)(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); - int (*read)(struct device *dev, uint32_t pos, void *buffer, uint32_t size); - void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event); - void *handle; -}; - -int device_register(struct device *dev, const char *name); -int device_unregister(const char *name); -struct device *device_find(const char *name); -int device_open(struct device *dev, uint16_t oflag); -int device_close(struct device *dev); -int device_control(struct device *dev, int cmd, void *args); -int device_write(struct device *dev, uint32_t pos, const void *buffer, uint32_t size); -int device_read(struct device *dev, uint32_t pos, void *buffer, uint32_t size); -int device_set_callback(struct device *dev, void (*callback)(struct device *dev, void *args, uint32_t size, uint32_t event)); -dlist_t *device_get_list_header(void); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h deleted file mode 100644 index b0b5181d23..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/list/drv_list.h +++ /dev/null @@ -1,472 +0,0 @@ -/** - * @file drv_list.h - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __DRV_LIST_H__ -#define __DRV_LIST_H__ - -#include "string.h" -#include "stdint.h" - -#ifdef __cplusplus -extern "C" { -#endif - -/** - * container_of - return the member address of ptr, if the type of ptr is the - * struct type. - */ -#define container_of(ptr, type, member) \ - ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member))) - -/** - * Double List structure - */ -struct dlist_node { - struct dlist_node *next; /**< point to next node. */ - struct dlist_node *prev; /**< point to prev node. */ -}; -typedef struct dlist_node dlist_t; /**< Type for lists. */ - -/** - * @brief initialize a list - * - * @param l list to be initialized - */ -static inline void dlist_init(dlist_t *l) -{ - l->next = l->prev = l; -} - -/** - * @brief insert a node after a list - * - * @param l list to insert it - * @param n new node to be inserted - */ -static inline void dlist_insert_after(dlist_t *l, dlist_t *n) -{ - l->next->prev = n; - n->next = l->next; - - l->next = n; - n->prev = l; -} - -/** - * @brief insert a node before a list - * - * @param n new node to be inserted - * @param l list to insert it - */ -static inline void dlist_insert_before(dlist_t *l, dlist_t *n) -{ - l->prev->next = n; - n->prev = l->prev; - - l->prev = n; - n->next = l; -} - -/** - * @brief remove node from list. - * @param n the node to remove from the list. - */ -static inline void dlist_remove(dlist_t *n) -{ - n->next->prev = n->prev; - n->prev->next = n->next; - - n->next = n->prev = n; -} - -/** - * @brief move node from list. - * @param n the node to remove from the list. - */ -static inline void dlist_move_head(dlist_t *l, dlist_t *n) -{ - dlist_remove(n); - dlist_insert_after(l, n); -} - -/** - * @brief move node from list. - * @param n the node to remove from the list. - */ -static inline void dlist_move_tail(dlist_t *l, dlist_t *n) -{ - dlist_remove(n); - dlist_insert_before(l, n); -} - -/** - * @brief tests whether a list is empty - * @param l the list to test. - */ -static inline int dlist_isempty(const dlist_t *l) -{ - return l->next == l; -} - -/** - * @brief get the list length - * @param l the list to get. - */ -static inline unsigned int dlist_len(const dlist_t *l) -{ - unsigned int len = 0; - const dlist_t *p = l; - - while (p->next != l) { - p = p->next; - len++; - } - - return len; -} - -/** - * @brief initialize a dlist object - */ -#define DLIST_OBJECT_INIT(object) \ - { \ - &(object), &(object) \ - } -/** - * @brief initialize a dlist object - */ -#define DLIST_DEFINE(list) \ - dlist_t list = { &(list), &(list) } - -/** - * dlist_first_entry - get the first element from a list - * @ptr: the list head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_struct within the struct. - * - * Note, that list is expected to be not empty. - */ -#define dlist_first_entry(ptr, type, member) \ - dlist_entry((ptr)->next, type, member) -/** - * dlist_first_entry_or_null - get the first element from a list - * @ptr: the list head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the list_struct within the struct. - * - * Note, that list is expected to be not empty. - */ -#define dlist_first_entry_or_null(ptr, type, member) \ - (dlist_isempty(ptr) ? NULL : dlist_first_entry(ptr, type, member)) - -/** - * @brief get the struct for this entry - * @param node the entry point - * @param type the type of structure - * @param member the name of list in structure - */ -#define dlist_entry(node, type, member) \ - container_of(node, type, member) - -/** - * dlist_for_each - iterate over a list - * @pos: the dlist_t * to use as a loop cursor. - * @head: the head for your list. - */ -#define dlist_for_each(pos, head) \ - for (pos = (head)->next; pos != (head); pos = pos->next) - -/** - * dlist_for_each_prev - iterate over a list - * @pos: the dlist_t * to use as a loop cursor. - * @head: the head for your list. - */ -#define dlist_for_each_prev(pos, head) \ - for (pos = (head)->prev; pos != (head); pos = pos->prev) - -/** - * dlist_for_each_safe - iterate over a list safe against removal of list entry - * @pos: the dlist_t * to use as a loop cursor. - * @n: another dlist_t * to use as temporary storage - * @head: the head for your list. - */ -#define dlist_for_each_safe(pos, n, head) \ - for (pos = (head)->next, n = pos->next; pos != (head); \ - pos = n, n = pos->next) - -#define dlist_for_each_prev_safe(pos, n, head) \ - for (pos = (head)->prev, n = pos->prev; pos != (head); \ - pos = n, n = pos->prev) -/** - * dlist_for_each_entry - iterate over list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry(pos, head, member) \ - for (pos = dlist_entry((head)->next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = dlist_entry(pos->member.next, typeof(*pos), member)) - -/** - * dlist_for_each_entry_reverse - iterate over list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry_reverse(pos, head, member) \ - for (pos = dlist_entry((head)->prev, typeof(*pos), member); \ - &pos->member != (head); \ - pos = dlist_entry(pos->member.prev, typeof(*pos), member)) - -/** - * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry_safe(pos, n, head, member) \ - for (pos = dlist_entry((head)->next, typeof(*pos), member), \ - n = dlist_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = dlist_entry(n->member.next, typeof(*n), member)) - -/** - * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry - * @pos: the type * to use as a loop cursor. - * @n: another type * to use as temporary storage - * @head: the head for your list. - * @member: the name of the list_struct within the struct. - */ -#define dlist_for_each_entry_safe_reverse(pos, n, head, member) \ - for (pos = dlist_entry((head)->prev, typeof(*pos), field), \ - n = dlist_entry(pos->member.prev, typeof(*pos), member); \ - &pos->member != (head); \ - pos = n, n = dlist_entry(pos->member.prev, typeof(*pos), member)) - -/** - * Single List structure - */ -struct slist_node { - struct slist_node *next; /**< point to next node. */ -}; -typedef struct slist_node slist_t; /**< Type for single list. */ - -/** - * @brief initialize a single list - * - * @param l the single list to be initialized - */ -static inline void slist_init(slist_t *l) -{ - l->next = NULL; -} - -static inline void slist_add_head(slist_t *l, slist_t *n) -{ - n->next = l->next; - l->next = n; -} - -static inline void slist_add_tail(slist_t *l, slist_t *n) -{ - while (l->next) { - l = l->next; - } - - /* append the node to the tail */ - l->next = n; - n->next = NULL; -} - -static inline void slist_insert(slist_t *l, slist_t *next, slist_t *n) -{ - if (!next) { - slist_add_tail(next, l); - return; - } - - while (l->next) { - if (l->next == next) { - l->next = n; - n->next = next; - } - - l = l->next; - } -} - -static inline slist_t *slist_remove(slist_t *l, slist_t *n) -{ - /* remove slist head */ - while (l->next && l->next != n) { - l = l->next; - } - - /* remove node */ - if (l->next != (slist_t *)0) { - l->next = l->next->next; - } - - return l; -} - -static inline unsigned int slist_len(const slist_t *l) -{ - unsigned int len = 0; - const slist_t *list = l->next; - - while (list != NULL) { - list = list->next; - len++; - } - - return len; -} - -static inline unsigned int slist_contains(slist_t *l, slist_t *n) -{ - while (l->next) { - if (l->next == n) { - return 0; - } - - l = l->next; - } - - return 1; -} - -static inline slist_t *slist_head(slist_t *l) -{ - return l->next; -} - -static inline slist_t *slist_tail(slist_t *l) -{ - while (l->next) { - l = l->next; - } - - return l; -} - -static inline slist_t *slist_next(slist_t *n) -{ - return n->next; -} - -static inline int slist_isempty(slist_t *l) -{ - return l->next == NULL; -} - -/** - * @brief initialize a slist object - */ -#define SLIST_OBJECT_INIT(object) \ - { \ - NULL \ - } - -/** - * @brief initialize a slist object - */ -#define SLIST_DEFINE(slist) \ - slist_t slist = { NULL } - -/** - * @brief get the struct for this single list node - * @param node the entry point - * @param type the type of structure - * @param member the name of list in structure - */ -#define slist_entry(node, type, member) \ - container_of(node, type, member) - -/** - * slist_first_entry - get the first element from a slist - * @ptr: the slist head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the slist_struct within the struct. - * - * Note, that slist is expected to be not empty. - */ -#define slist_first_entry(ptr, type, member) \ - slist_entry((ptr)->next, type, member) - -/** - * slist_tail_entry - get the tail element from a slist - * @ptr: the slist head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the slist_struct within the struct. - * - * Note, that slist is expected to be not empty. - */ -#define slist_tail_entry(ptr, type, member) \ - slist_entry(slist_tail(ptr), type, member) - -/** - * slist_first_entry_or_null - get the first element from a slist - * @ptr: the slist head to take the element from. - * @type: the type of the struct this is embedded in. - * @member: the name of the slist_struct within the struct. - * - * Note, that slist is expected to be not empty. - */ -#define slist_first_entry_or_null(ptr, type, member) \ - (slist_isempty(ptr) ? NULL : slist_first_entry(ptr, type, member)) - -/** - * slist_for_each - iterate over a single list - * @pos: the slist_t * to use as a loop cursor. - * @head: the head for your single list. - */ -#define slist_for_each(pos, head) \ - for (pos = (head)->next; pos != NULL; pos = pos->next) - -#define slist_for_each_safe(pos, next, head) \ - for (pos = (head)->next, next = pos->next; pos; \ - pos = next, next = pos->next) - -/** - * slist_for_each_entry - iterate over single list of given type - * @pos: the type * to use as a loop cursor. - * @head: the head for your single list. - * @member: the name of the list_struct within the struct. - */ -#define slist_for_each_entry(pos, head, member) \ - for (pos = slist_entry((head)->next, typeof(*pos), member); \ - &pos->member != (NULL); \ - pos = slist_entry(pos->member.next, typeof(*pos), member)) - -#define slist_for_each_entry_safe(pos, n, head, member) \ - for (pos = slist_entry((head)->next, typeof(*pos), member), \ - n = slist_entry(pos->member.next, typeof(*pos), member); \ - &pos->member != (NULL); \ - pos = n, n = slist_entry(pos->member.next, typeof(*pos), member)) - -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c deleted file mode 100644 index 5e053f2597..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.c +++ /dev/null @@ -1,421 +0,0 @@ -/** - * @file drv_mmheap.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "drv_mmheap.h" - -#define MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT 8 -#define MEM_MANAGE_BITS_PER_BYTE 8 -#define MEM_MANAGE_MEM_STRUCT_SIZE mmheap_align_up(sizeof(struct heap_node), MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT) -#define MEM_MANAGE_MINUM_MEM_SIZE (MEM_MANAGE_MEM_STRUCT_SIZE << 1) -#define MEM_MANAGE_ALLOCA_LABAL ((size_t)((size_t)1 << (sizeof(size_t) * MEM_MANAGE_BITS_PER_BYTE - 1))) - -static inline size_t mmheap_align_down(size_t data, size_t align_byte) -{ - return data & ~(align_byte - 1); -} - -static inline size_t mmheap_align_up(size_t data, size_t align_byte) -{ - return (data + align_byte - 1) & ~(align_byte - 1); -} - -static inline struct heap_node *mmheap_addr_sub(const void *addr) -{ - return (struct heap_node *)((const uint8_t *)addr - MEM_MANAGE_MEM_STRUCT_SIZE); -} - -static inline void *mmheap_addr_add(const struct heap_node *mem_node) -{ - return (void *)((const uint8_t *)mem_node + MEM_MANAGE_MEM_STRUCT_SIZE); -} - -/** - * @brief mmheap_insert_node_to_freelist - * - * @param pRoot - * @param pNode - */ -static inline void mmheap_insert_node_to_freelist(struct heap_info *pRoot, struct heap_node *pNode) -{ - struct heap_node *pPriv_Node; - struct heap_node *pNext_Node; - /*Find the node with an address similar to pNode*/ - for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pNode; pPriv_Node = pPriv_Node->next_node) { - } - - pNext_Node = pPriv_Node->next_node; - /*Try to merge the pNode with the previous block*/ - if ((uint8_t *)mmheap_addr_add(pPriv_Node) + pPriv_Node->mem_size == (uint8_t *)pNode) { - if (pPriv_Node != pRoot->pStart) { /*can merge if not start block*/ - pPriv_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNode->mem_size; - pNode = pPriv_Node; - } else { - /*The latter is not merged if it is a Start block to avoid wasting memory*/ - pRoot->pStart->next_node = pNode; - } - } else { - /*Insert directly into the free single-chain table when merging is not possible*/ - pPriv_Node->next_node = pNode; - } - /*Try to merge the pNode with the next block*/ - if ((uint8_t *)mmheap_addr_add(pNode) + pNode->mem_size == (uint8_t *)pNext_Node) { - if (pNext_Node != pRoot->pEnd) { - pNode->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size; - pNode->next_node = pNext_Node->next_node; - } else { - pNode->next_node = pRoot->pEnd; - } - } else { - /*Insert directly into the free single-chain table when merging is not possible*/ - pNode->next_node = pNext_Node; - } -} - -/** - * @brief mmheap_get_state - * - * @param pRoot - * @param pState - */ -void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState) -{ - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - pState->max_node_size = pRoot->pStart->next_node->mem_size; - pState->min_node_size = pRoot->pStart->next_node->mem_size; - pState->remain_size = 0; - pState->free_node_num = 0; - MMHEAP_LOCK(); - for (struct heap_node *pNode = pRoot->pStart->next_node; pNode->next_node != NULL; pNode = pNode->next_node) { - pState->remain_size += pNode->mem_size; - pState->free_node_num++; - if (pNode->mem_size > pState->max_node_size) - pState->max_node_size = pNode->mem_size; - if (pNode->mem_size < pState->min_node_size) - pState->min_node_size = pNode->mem_size; - } - MMHEAP_UNLOCK(); -} -/** - * @brief mmheap_align_alloc - * - * @param pRoot - * @param align_size - * @param want_size - * @return void* - */ -void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size) -{ - void *pReturn = NULL; - struct heap_node *pPriv_Node, *pNow_Node; - - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - - if (want_size == 0) { - return NULL; - } - - if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) { - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - if (align_size & (align_size - 1)) { - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - MMHEAP_LOCK(); - if (want_size < MEM_MANAGE_MINUM_MEM_SIZE) - want_size = MEM_MANAGE_MINUM_MEM_SIZE; - if (align_size < MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT) - align_size = MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT; - - want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); - - pPriv_Node = pRoot->pStart; - pNow_Node = pRoot->pStart->next_node; - - while (pNow_Node->next_node != NULL) { - if (pNow_Node->mem_size >= want_size + MEM_MANAGE_MEM_STRUCT_SIZE) { - size_t use_align_size; - size_t new_size; - pReturn = (void *)mmheap_align_up((size_t)mmheap_addr_add(pNow_Node), align_size); /*Calculate the aligned address*/ - use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node); /*Calculate the memory consumed by the alignment*/ - if (use_align_size != 0) { /*if Memory misalignment*/ - if (use_align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) { /*The unaligned value is too small*/ - pReturn = (void *)mmheap_align_up( - (size_t)mmheap_addr_add(pNow_Node) + MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE, align_size); - use_align_size = (uint8_t *)pReturn - (uint8_t *)mmheap_addr_add(pNow_Node); - } - if (use_align_size <= pNow_Node->mem_size) { - new_size = pNow_Node->mem_size - use_align_size; /*Calculate the remaining memory size by removing the memory consumed by alignment*/ - if (new_size >= want_size) { /*Meet the conditions for distribution*/ - struct heap_node *pNew_Node = mmheap_addr_sub(pReturn); - pNow_Node->mem_size -= new_size + MEM_MANAGE_MEM_STRUCT_SIZE; /*Split Node*/ - pNew_Node->mem_size = new_size; /*The new node is also not in the free chain and does not need to be discharged from the free chain*/ - pNew_Node->next_node = NULL; - pNow_Node = pNew_Node; - break; - } - } - } else { /*Memory is directly aligned*/ - pPriv_Node->next_node = pNow_Node->next_node; - pNow_Node->next_node = NULL; - break; - } - } - pPriv_Node = pNow_Node; - pNow_Node = pNow_Node->next_node; - } - - if (pNow_Node == pRoot->pEnd) { - MMHEAP_UNLOCK(); - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - if (pNow_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) { /*Node memory is still available*/ - struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pNow_Node) + want_size); /*Calculate the address of the node that will be moved into the free chain table*/ - pNew_Node->mem_size = pNow_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE; - pNew_Node->next_node = NULL; - pNow_Node->mem_size = want_size; - mmheap_insert_node_to_freelist(pRoot, pNew_Node); - } - pNow_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_UNLOCK(); - return pReturn; -} -/** - * @brief mmheap_alloc - * - * @param pRoot - * @param want_size - * @return void* - */ -void *mmheap_alloc(struct heap_info *pRoot, size_t want_size) -{ - return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size); -} -/** - * @brief mmheap_realloc - * - * @param pRoot - * @param src_addr - * @param want_size - * @return void* - */ -void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size) -{ - void *pReturn = NULL; - struct heap_node *pNext_Node, *pPriv_Node; - struct heap_node *pSrc_Node; - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - if (src_addr == NULL) { - return mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size); - } - if (want_size == 0) { - mmheap_free(pRoot, src_addr); - return NULL; - } - - MMHEAP_LOCK(); - if ((want_size & MEM_MANAGE_ALLOCA_LABAL) != 0) { - MMHEAP_UNLOCK(); - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - pSrc_Node = mmheap_addr_sub(src_addr); - - if ((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) { - MMHEAP_UNLOCK(); - MMHEAP_ASSERT((pSrc_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0); - MMHEAP_MALLOC_FAIL(); - return NULL; - } - - pSrc_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL; - if (pSrc_Node->mem_size >= want_size) { - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - pReturn = src_addr; - MMHEAP_UNLOCK(); - return pReturn; - } - /*Start looking in the free list for blocks similar to this block*/ - for (pPriv_Node = pRoot->pStart; pPriv_Node->next_node < pSrc_Node; pPriv_Node = pPriv_Node->next_node) { - } - pNext_Node = pPriv_Node->next_node; - - if (pNext_Node != pRoot->pEnd && - ((uint8_t *)src_addr + pSrc_Node->mem_size == (uint8_t *)pNext_Node) && - (pSrc_Node->mem_size + pNext_Node->mem_size + MEM_MANAGE_MEM_STRUCT_SIZE >= want_size)) { - /*Meet next node non-end, memory contiguous, enough memory left*/ - pReturn = src_addr; - pPriv_Node->next_node = pNext_Node->next_node; - pSrc_Node->mem_size += MEM_MANAGE_MEM_STRUCT_SIZE + pNext_Node->mem_size; - want_size = mmheap_align_up(want_size, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); - if (pSrc_Node->mem_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE + want_size) { /*Removing the remaining space allocated is enough to open new blocks*/ - struct heap_node *pNew_Node = (struct heap_node *)((uint8_t *)mmheap_addr_add(pSrc_Node) + want_size); - pNew_Node->next_node = NULL; - pNew_Node->mem_size = pSrc_Node->mem_size - want_size - MEM_MANAGE_MEM_STRUCT_SIZE; - pSrc_Node->mem_size = want_size; - mmheap_insert_node_to_freelist(pRoot, pNew_Node); - } - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_UNLOCK(); - } else { - MMHEAP_UNLOCK(); - pReturn = mmheap_align_alloc(pRoot, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT, want_size); - if (pReturn == NULL) { - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_MALLOC_FAIL(); - return NULL; - } - MMHEAP_LOCK(); - memcpy(pReturn, src_addr, pSrc_Node->mem_size); - pSrc_Node->mem_size |= MEM_MANAGE_ALLOCA_LABAL; - MMHEAP_UNLOCK(); - mmheap_free(pRoot, src_addr); - } - return pReturn; -} -/** - * @brief - * - * @param pRoot - * @param num - * @param size - * @return void* - */ -void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size) -{ - void *pReturn = NULL; - - pReturn = (void *)mmheap_alloc(pRoot, size * num); - - if (pReturn) { - memset(pReturn, 0, num * size); - } - - return pReturn; -} -/** - * @brief mmheap_free - * - * @param pRoot - * @param addr - */ -void mmheap_free(struct heap_info *pRoot, void *addr) -{ - struct heap_node *pFree_Node; - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); - MMHEAP_LOCK(); - if (addr == NULL) { - MMHEAP_UNLOCK(); - return; - } - pFree_Node = mmheap_addr_sub(addr); - - if ((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) == 0) { - MMHEAP_UNLOCK(); - MMHEAP_ASSERT((pFree_Node->mem_size & MEM_MANAGE_ALLOCA_LABAL) != 0); - return; - } - - if (pFree_Node->next_node != NULL) { - MMHEAP_UNLOCK(); - MMHEAP_ASSERT(pFree_Node->next_node == NULL); - return; - } - pFree_Node->mem_size &= ~MEM_MANAGE_ALLOCA_LABAL; - mmheap_insert_node_to_freelist(pRoot, pFree_Node); - MMHEAP_UNLOCK(); -} -/** - * @brief mmheap_init - * - * @param pRoot - * @param pRegion - */ -void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRegion) -{ - struct heap_node *align_addr; - size_t align_size; - struct heap_node *pPriv_node = NULL; - - pRoot->total_size = 0; - pRoot->pEnd = NULL; - pRoot->pStart = NULL; - - for (; pRegion->addr != NULL; pRegion++) { - align_addr = (struct heap_node *)mmheap_align_up((size_t)pRegion->addr, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); /*Calculate the aligned address*/ - if ((uint8_t *)align_addr > pRegion->mem_size + (uint8_t *)pRegion->addr) /*Alignment consumes more memory than the memory area*/ - continue; - align_size = pRegion->mem_size - ((uint8_t *)align_addr - (uint8_t *)pRegion->addr); /*Calculate the size of memory left after alignment*/ - if (align_size < MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) /*if Aligning the remaining memory is too small*/ - continue; - align_size -= MEM_MANAGE_MEM_STRUCT_SIZE; /*Find the size of the memory block after removing the table header*/ - align_addr->mem_size = align_size; - align_addr->next_node = NULL; - if (pRoot->pStart == NULL) { - pRoot->pStart = align_addr; /*set current addr for start*/ - if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE + MEM_MANAGE_MEM_STRUCT_SIZE) { /*If the remaining blocks are large enough*/ - align_size -= MEM_MANAGE_MEM_STRUCT_SIZE; /*Remove the next block of table headers remaining memory size*/ - align_addr = (struct heap_node *)((uint8_t *)pRoot->pStart + MEM_MANAGE_MEM_STRUCT_SIZE); //the next block addr - align_addr->mem_size = align_size; - align_addr->next_node = NULL; - pRoot->pStart->mem_size = 0; - pRoot->pStart->next_node = align_addr; - pRoot->total_size = align_addr->mem_size; - } else { /*The memory is too small, and the address of the current memory block is recorded as start*/ - pRoot->total_size = 0; - pRoot->pStart->mem_size = 0; - } - } else { - pPriv_node->next_node = align_addr; - pRoot->total_size += align_size; - } - pPriv_node = align_addr; - } - //At this point, pPriv_node is the last block, then place the end of the table at the end of the block, find the address to place the end block, end block is only convenient for traversal, so as small as possible, assigned to MEM_MANAGE_MEM_STRUCT_SIZE - align_addr = (struct heap_node *)mmheap_align_down( - (size_t)mmheap_addr_add(pPriv_node) + pPriv_node->mem_size - MEM_MANAGE_MEM_STRUCT_SIZE, MEM_MANAGE_ALIGNMENT_BYTE_DEFAULT); - align_size = (uint8_t *)align_addr - (uint8_t *)mmheap_addr_add(pPriv_node); /*Find the remaining size of the previous block after the end block is allocated*/ - if (align_size >= MEM_MANAGE_MINUM_MEM_SIZE) { - pRoot->total_size -= pPriv_node->mem_size - align_size; /*Removing memory consumed by allocating end blocks*/ - pRoot->pEnd = align_addr; /*Update the address at the end of the list*/ - pPriv_node->next_node = align_addr; - pPriv_node->mem_size = align_size; - align_addr->next_node = NULL; - align_addr->mem_size = 0; /*The end block is not involved in memory allocation, so a direct 0 is sufficient*/ - } else { /*The last block is too small, directly as the end block*/ - pRoot->pEnd = pPriv_node; - pRoot->total_size -= pPriv_node->mem_size; - } - MMHEAP_ASSERT(pRoot->pStart != NULL); - MMHEAP_ASSERT(pRoot->pEnd != NULL); -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h deleted file mode 100644 index 42a7187ce6..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/memheap/drv_mmheap.h +++ /dev/null @@ -1,159 +0,0 @@ -/** - * @file drv_mmheap.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __DRV_MMHEAP_H -#define __DRV_MMHEAP_H - -#include -#include -#include - -#ifndef MMHEAP_LOCK -#define MMHEAP_LOCK() -#endif - -#ifndef MMHEAP_UNLOCK -#define MMHEAP_UNLOCK() -#endif - -#ifndef MMHEAP_ASSERT -#define MMHEAP_ASSERT(A) \ - if (!(A)) \ - printf("mmheap malloc error:drv_mmheap,%d\r\n", __LINE__) - -#endif - -#ifndef MMHEAP_MALLOC_FAIL -#define MMHEAP_MALLOC_FAIL() printf("mmheap malloc fail:drv_mmheap,%d\r\n", __LINE__) -#endif - -#ifdef __cplusplus -extern "C" { -#endif - -struct heap_region { - void *addr; - size_t mem_size; -}; - -struct heap_node { - struct heap_node *next_node; - size_t mem_size; -}; - -struct heap_info { - struct heap_node *pStart; - struct heap_node *pEnd; - size_t total_size; -}; - -struct heap_state { - size_t remain_size; - size_t free_node_num; - size_t max_node_size; - size_t min_node_size; -}; - -void mmheap_init(struct heap_info *pRoot, const struct heap_region *pRigon); -/** - * @brief Alloc start address aligned memory from the heap. - * Alloc aligned address and specified size memory from the heap. - * - * @attention - * - * @param[in] pRoot heap info. - * @param[in] align_size address align mask of the memory. - * @param[in] want_size size of the memory. - * - * @return the pointer to the allocated memory. - */ -void *mmheap_align_alloc(struct heap_info *pRoot, size_t align_size, size_t want_size); -/** - * @brief Alloc memory. - * Allocate size bytes and returns a pointer to the allocated memory. - * - * @attention size should no bigger than MMHEAP_BLK_SIZE_MAX. - * - * @param[in] pRoot heap info. - * @param[in] want_size size of the memory. - * - * @return the pointer to the allocated memory. - */ -void *mmheap_alloc(struct heap_info *pRoot, size_t want_size); -/** - * @brief Realloc memory from the heap. - * Change the size of the memory block pointed to by ptr to size bytes. - * - * @attention - *
    - *
  • if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size. - *
  • if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr). - *
- * - * @param[in] pRoot heap info. - * @param[in] src_addr old pointer to the memory space. - * @param[in] want_size new size of the memory space. - * - * @return the new pointer to the allocated memory. - */ -void *mmheap_realloc(struct heap_info *pRoot, void *src_addr, size_t want_size); -/** - * @brief Cealloc memory from the heap. - * Change the size of the memory block pointed to by ptr to size bytes. - * - * @attention - *
    - *
  • if ptr is NULL, then the call is equivalent to mmheap_alloc(size), for all values of size. - *
  • if ptr is if size is equal to zero, and ptr is not NULL, then the call is equivalent to mmheap_free(ptr). - *
- * - * @param[in] pRoot heap info. - * @param[in] num size number. - * @param[in] size new size of the memory space. - * - * @return the new pointer to the allocated memory. - */ -void *mmheap_calloc(struct heap_info *pRoot, size_t num, size_t size); -/** - * @brief Free the memory. - * Free the memory space pointed to by ptr, which must have been returned by a previous call to mmheap_alloc(), mmheap_aligned_alloc(), or mmheap_realloc(). - * - * @attention - * - * @param[in] pRoot heap info. - * @param[in] addr pointer to the memory. - * - * @return None. - */ -void mmheap_free(struct heap_info *pRoot, void *addr); -/** - * @brief get mmheap state - * - * @param pRoot heap info. - * @param pState heap state - */ -void mmheap_get_state(struct heap_info *pRoot, struct heap_state *pState); -#ifdef __cplusplus -} -#endif - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h deleted file mode 100644 index 29489e3c1d..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/common.h +++ /dev/null @@ -1,63 +0,0 @@ -#ifndef __COMMON_H -#define __COMMON_H - -/** - * @brief Memory access macro - */ -#define BL_RD_WORD(addr) (*((volatile uint32_t *)(uintptr_t)(addr))) -#define BL_WR_WORD(addr, val) ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val)) -#define BL_RD_SHORT(addr) (*((volatile uint16_t *)(uintptr_t)(addr))) -#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val)) -#define BL_RD_BYTE(addr) (*((volatile uint8_t *)(uintptr_t)(addr))) -#define BL_WR_BYTE(addr, val) ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val)) -#define BL_RDWD_FRM_BYTEP(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0])) - -#define BL_WRWD_TO_BYTEP(p, val) \ - { \ - p[0] = val & 0xff; \ - p[1] = (val >> 8) & 0xff; \ - p[2] = (val >> 16) & 0xff; \ - p[3] = (val >> 24) & 0xff; \ - } -/** - * @brief Register access macro - */ -#define BL_RD_REG16(addr, regname) BL_RD_SHORT(addr + regname##_OFFSET) -#define BL_WR_REG16(addr, regname, val) BL_WR_SHORT(addr + regname##_OFFSET, val) -#define BL_RD_REG(addr, regname) BL_RD_WORD(addr + regname##_OFFSET) -#define BL_WR_REG(addr, regname, val) BL_WR_WORD(addr + regname##_OFFSET, val) -#define BL_SET_REG_BIT(val, bitname) ((val) | (1U << bitname##_POS)) -#define BL_CLR_REG_BIT(val, bitname) ((val)&bitname##_UMSK) -#define BL_GET_REG_BITS_VAL(val, bitname) (((val)&bitname##_MSK) >> bitname##_POS) -#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS)) -#define BL_IS_REG_BIT_SET(val, bitname) (((val) & (1U << (bitname##_POS))) != 0) -#define BL_DRV_DUMMY \ - { \ - __ASM volatile("nop"); \ - __ASM volatile("nop"); \ - __ASM volatile("nop"); \ - __ASM volatile("nop"); \ - } - -/* Std driver attribute macro*/ -#ifndef BFLB_USE_CUSTOM_LD_SECTIONS -//#define ATTR_UNI_SYMBOL -#define ATTR_STRINGIFY(x) #x -#define ATTR_TOSTRING(x) ATTR_STRINGIFY(x) -#define ATTR_UNI_SYMBOL __FILE__ ATTR_TOSTRING(__LINE__) -#define ATTR_CLOCK_SECTION __attribute__((section(".sclock_rlt_code." ATTR_UNI_SYMBOL))) -#define ATTR_CLOCK_CONST_SECTION __attribute__((section(".sclock_rlt_const." ATTR_UNI_SYMBOL))) -#define ATTR_TCM_SECTION __attribute__((section(".tcm_code." ATTR_UNI_SYMBOL))) -#define ATTR_TCM_CONST_SECTION __attribute__((section(".tcm_const." ATTR_UNI_SYMBOL))) -#define ATTR_DTCM_SECTION __attribute__((section(".tcm_data"))) -#define ATTR_HSRAM_SECTION __attribute__((section(".hsram_code"))) -#define ATTR_DMA_RAM_SECTION __attribute__((section(".system_ram"))) -#define ATTR_HBN_RAM_SECTION __attribute__((section(".hbn_ram_code"))) -#define ATTR_HBN_RAM_CONST_SECTION __attribute__((section(".hbn_ram_data"))) -#define ATTR_EALIGN(x) __attribute__((aligned(x))) -#define ATTR_FALLTHROUGH() __attribute__((fallthrough)) -#define ATTR_USED __attribute__((__used__)) -#else -#include "bl_ld_sections.h" -#endif /* BFLB_USE_CUSTOM_LD_SECTIONS */ -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c deleted file mode 100644 index 3292a68359..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.c +++ /dev/null @@ -1,253 +0,0 @@ -/** - * @file misc.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "misc.h" - -#ifndef BFLB_USE_ROM_DRIVER -/****************************************************************************/ /** - * @brief Char memcpy - * - * @param dst: Destination - * @param src: Source - * @param n: Count of char - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n) -{ - const uint8_t *p = src; - uint8_t *q = dst; - - while (n--) { - *q++ = *p++; - } - - return dst; -} - -/****************************************************************************/ /** - * @brief Word memcpy - * - * @param dst: Destination - * @param src: Source - * @param n: Count of words - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n) -{ - const uint32_t *p = src; - uint32_t *q = dst; - - while (n--) { - *q++ = *p++; - } - - return dst; -} - -/****************************************************************************/ /** - * @brief Fast memcpy - * - * @param dst: Destination - * @param src: Source - * @param n: Count of bytes - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n) -{ - uint32_t left, done, i = 0; - uint8_t *dst = (uint8_t *)pdst; - uint8_t *src = (uint8_t *)psrc; - - if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) { - arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2); - left = n % 4; - done = n - left; - - while (i < left) { - dst[done + i] = src[done + i]; - i++; - } - } else { - arch_memcpy(dst, src, n); - } - - return dst; -} - -/****************************************************************************/ /** - * @brief char memset - * - * @param dst: Destination - * @param val: Value to set - * @param n: Count of char - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n) -{ - uint8_t *p = (uint8_t *)s; - - while (n > 0) { - *p++ = (uint8_t)c; - --n; - } - - return s; -} -/****************************************************************************/ /** - * @brief Word memset - * - * @param dst: Destination - * @param val: Value to set - * @param n: Count of words - * - * @return Destination pointer - * - *******************************************************************************/ -__WEAK__ uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n) -{ - uint32_t *q = dst; - - while (n--) { - *q++ = val; - } - - return dst; -} - -/****************************************************************************/ /** - * @brief string compare - * - * @param s1: string 1 - * @param s2: string 2 - * @param n: Count of chars - * - * @return compare result - * - *******************************************************************************/ -__WEAK__ int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n) -{ - const unsigned char *c1 = s1, *c2 = s2; - int d = 0; - - while (n--) { - d = (int)*c1++ - (int)*c2++; - - if (d) { - break; - } - } - - return d; -} -#endif - -void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length) -{ - uint8_t *p = (uint8_t *)fifo_addr; - uint8_t *q = data; - - while (length--) { - *p = *q++; - } -} - -void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length) -{ - uint8_t *p = (uint8_t *)fifo_addr; - uint8_t *q = data; - - while (length--) { - *q++ = *p; - } -} - -/****************************************************************************/ /** - * @brief get u64 first number 1 from right to left - * - * @param val: target value - * @param bit: first 1 in bit - * - * @return SUCCESS or ERROR - * -*******************************************************************************/ -int arch_ffsll(uint64_t *val, uint32_t *bit) -{ - if (!*val) { - return ERROR; - } - - *bit = __builtin_ffsll(*val) - 1; - *val &= ~((1ULL) << (*bit)); - return 0; -} - -int arch_ctzll(uint64_t *val, uint32_t *bit) -{ - if (!*val) - return -1; - - *bit = __builtin_ctzll(*val); - *val &= ~((1ULL) << (*bit)); - return 0; -} - -int arch_clzll(uint64_t *val, uint32_t *bit) -{ - if (!*val) - return -1; - - *bit = __builtin_clzll(*val); - *val &= ~((1ULL) << (*bit)); - return 0; -} - -#ifdef DEBUG -/******************************************************************************* -* @brief Reports the name of the source file and the source line number -* where the CHECK_PARAM error has occurred. - -* @param file: Pointer to the source file name -* @param line: assert_param error line source number - -* @return None -*******************************************************************************/ -void check_failed(uint8_t *file, uint32_t line) -{ - /* Infinite loop */ - while (1) - ; -} -#endif /* DEBUG */ - -/*@} end of group DRIVER_Public_Functions */ - -/*@} end of group DRIVER_COMMON */ - -/*@} end of group BL602_Periph_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h deleted file mode 100644 index 50ea5cd025..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/misc.h +++ /dev/null @@ -1,131 +0,0 @@ -/** - * @file misc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef _MISC_H -#define _MISC_H - -#include -#include -#include -#include -#include -#include -#include "compiler/gcc.h" -#include "compiler/common.h" - -#ifdef BIT -#undef BIT -#define BIT(n) (1UL << (n)) -#else -#define BIT(n) (1UL << (n)) -#endif - -/** - * @brief Null Type definition - */ -#ifndef NULL -#define NULL 0 -#endif - -/** - * @brief Error type definition - */ -typedef enum { - SUCCESS = 0, - ERROR = 1, - TIMEOUT = 2, - INVALID = 3, /* invalid arguments */ - NORESC = 4 /* no resource or resource temperary unavailable */ -} BL_Err_Type; - -/** - * @brief Functional type definition - */ -typedef enum { - DISABLE = 0, - ENABLE = 1, -} BL_Fun_Type; - -/** - * @brief Status type definition - */ -typedef enum { - RESET = 0, - SET = 1, -} BL_Sts_Type; - -/** - * @brief Mask type definition - */ -typedef enum { - UNMASK = 0, - MASK = 1 -} BL_Mask_Type; - -/** - * @brief Logical status Type definition - */ -typedef enum { - LOGIC_LO = 0, - LOGIC_HI = !LOGIC_LO -} LogicalStatus; - -/** - * @brief Active status Type definition - */ -typedef enum { - DEACTIVE = 0, - ACTIVE = !DEACTIVE -} ActiveStatus; - -/** - * @brief Interrupt callback function type - */ -typedef void(intCallback_Type)(void); -typedef void (*pFunc)(void); - -#define ARCH_MemCpy arch_memcpy -#define ARCH_MemSet arch_memset -#define ARCH_MemCmp arch_memcmp -#define ARCH_MemCpy4 arch_memcpy4 -#define ARCH_MemCpy_Fast arch_memcpy_fast -#define ARCH_MemSet4 arch_memset4 - -#ifdef DEBUG -void check_failed(uint8_t *file, uint32_t line); -#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__)) -#else -#define CHECK_PARAM(expr) ((void)0) -#endif /* DEBUG */ - -void *arch_memcpy(void *dst, const void *src, uint32_t n); -void *arch_memset(void *s, uint8_t c, uint32_t n); -int arch_memcmp(const void *s1, const void *s2, uint32_t n); -uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n); -void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n); -uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n); -void memcopy_to_fifo(void *fifo_addr, uint8_t *data, uint32_t length); -void fifocopy_to_mem(void *fifo_addr, uint8_t *data, uint32_t length); -int arch_ctzll(uint64_t *val, uint32_t *bit); -int arch_clzll(uint64_t *val, uint32_t *bit); -int arch_ffsll(uint64_t *val, uint32_t *bit); -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c deleted file mode 100644 index 673dcbe88b..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.c +++ /dev/null @@ -1,544 +0,0 @@ -/** - ****************************************************************************** - * @file partition.c - * @version V1.0 - * @date - * @brief This file is the standard driver c file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2019 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - -#include "partition.h" -#include "softcrc.h" -#include "bflb_platform.h" - -/** @addtogroup BFLB_Common_Driver - * @{ - */ - -/** @addtogroup PARTITION - * @{ - */ - -/** @defgroup PARTITION_Private_Macros - * @{ - */ - -/*@} end of group PARTITION_Private_Macros */ - -/** @defgroup PARTITION_Private_Types - * @{ - */ - -/*@} end of group PARTITION_Private_Types */ - -/** @defgroup PARTITION_Private_Variables - * @{ - */ -p_pt_table_flash_erase gp_pt_table_flash_erase = NULL; -p_pt_table_flash_write gp_pt_table_flash_write = NULL; -p_pt_table_flash_read gp_pt_table_flash_read = NULL; -pt_table_iap_param_type p_iap_param; - -/*@} end of group PARTITION_Private_Variables */ - -/** @defgroup PARTITION_Global_Variables - * @{ - */ -extern int main(void); - -/*@} end of group PARTITION_Global_Variables */ - -/** @defgroup PARTITION_Private_Fun_Declaration - * @{ - */ - -/*@} end of group PARTITION_Private_Fun_Declaration */ - -/** @defgroup PARTITION_Private_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Judge partition table valid - * - * @param ptStuff: Partition table stuff pointer - * - * @return 0 for invalid and 1 for valid - * -*******************************************************************************/ -static uint8_t pt_table_valid(pt_table_stuff_config *pt_stuff) -{ - pt_table_config *pt_table = &pt_stuff->pt_table; - pt_table_entry_config *pt_entries = pt_stuff->pt_entries; - uint32_t *p_crc32; - uint32_t entriesLen = sizeof(pt_table_entry_config) * pt_table->entryCnt; - - if (pt_table->magicCode == BFLB_PT_MAGIC_CODE) { - if (pt_table->entryCnt > PT_ENTRY_MAX) { - MSG("PT Entry Count Error\r\n"); - return 0; - } - - if (pt_table->crc32 != - BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4)) { - MSG("PT CRC Error\r\n"); - return 0; - } - - /* ToDo it is a trap here, when entryCnt > 8, crc32 will overflow, comment by zhangcheng */ - p_crc32 = (uint32_t *)((uintptr_t)pt_entries + entriesLen); - - if (*p_crc32 != BFLB_Soft_CRC32((uint8_t *)pt_entries, entriesLen)) { - MSG("PT Entry CRC Error\r\n"); - return 0; - } - - return 1; - } - - return 0; -} - -/*@} end of group PARTITION_Private_Functions */ - -/** @defgroup PARTITION_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Register partition flash read write erase fucntion - * - * @param erase: Flash erase function - * @param write: Flash write function - * @param read: Flash read function - * - * @return None - * -*******************************************************************************/ -void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read) -{ - gp_pt_table_flash_erase = erase; - gp_pt_table_flash_write = write; - gp_pt_table_flash_read = read; -} - -/****************************************************************************/ /** - * @brief Get active partition table whole stuff - * - * @param ptStuff[2]: Partition table stuff pointer - * - * @return Active partition table ID - * -*******************************************************************************/ -pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]) -{ - uint32_t pt_valid[2] = { 0, 0 }; - pt_table_id_type activePtID; - - if (ptStuff == NULL) { - return PT_TABLE_ID_INVALID; - } - - activePtID = PT_TABLE_ID_INVALID; - - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&ptStuff[0], sizeof(pt_table_stuff_config)); - pt_valid[0] = pt_table_valid(&ptStuff[0]); - - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&ptStuff[1], sizeof(pt_table_stuff_config)); - pt_valid[1] = pt_table_valid(&ptStuff[1]); - - if (pt_valid[0] == 1 && pt_valid[1] == 1) { - if (ptStuff[0].pt_table.age >= ptStuff[1].pt_table.age) { - activePtID = PT_TABLE_ID_0; - } else { - activePtID = PT_TABLE_ID_1; - } - } else if (pt_valid[0] == 1) { - activePtID = PT_TABLE_ID_0; - } else if (pt_valid[1] == 1) { - activePtID = PT_TABLE_ID_1; - } - - return activePtID; -} - -/****************************************************************************/ /** - * @brief Get partition entry according to entry ID - * - * @param ptStuff: Partition table stuff pointer - * @param type: Type of partition entry - * @param ptEntry: Partition entry pointer to store read data - * - * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER - * -*******************************************************************************/ -pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, - pt_table_entry_type type, - pt_table_entry_config *pt_entry) -{ - uint32_t i = 0; - - if (pt_stuff == NULL || pt_entry == NULL) { - return PT_ERROR_PARAMETER; - } - - for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { - if (pt_stuff->pt_entries[i].type == type) { - ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); - return PT_ERROR_SUCCESS; - } - } - - return PT_ERROR_ENTRY_NOT_FOUND; -} - -/****************************************************************************/ /** - * @brief Get partition entry according to entry name - * - * @param ptStuff: Partition table stuff pointer - * @param name: Name of partition entry - * @param ptEntry: Partition entry pointer to store read data - * - * @return PT_ERROR_SUCCESS or PT_ERROR_ENTRY_NOT_FOUND or PT_ERROR_PARAMETER - * -*******************************************************************************/ -pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, - uint8_t *name, - pt_table_entry_config *pt_entry) -{ - uint32_t i = 0; - uint32_t len = strlen((char *)name); - - if (pt_stuff == NULL || pt_entry == NULL) { - return PT_ERROR_PARAMETER; - } - - for (i = 0; i < pt_stuff->pt_table.entryCnt; i++) { - if (strlen((char *)pt_stuff->pt_entries[i].name) == len && - memcmp((char *)pt_stuff->pt_entries[i].name, (char *)name, len) == 0) { - ARCH_MemCpy_Fast(pt_entry, &pt_stuff->pt_entries[i], sizeof(pt_table_entry_config)); - return PT_ERROR_SUCCESS; - } - } - - return PT_ERROR_ENTRY_NOT_FOUND; -} - -/****************************************************************************/ /** - * @brief Update partition entry - * - * @param targetTableID: Target partition table to update - * @param ptStuff: Partition table stuff pointer - * @param ptEntry: Partition entry pointer to update - * - * @return Partition update result - * -*******************************************************************************/ -pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, - pt_table_stuff_config *pt_stuff, - pt_table_entry_config *pt_entry) -{ - uint32_t i = 0; - BL_Err_Type ret; - uint32_t write_addr; - uint32_t entries_len; - pt_table_config *pt_table; - pt_table_entry_config *pt_entries; - uint32_t *crc32; - - if (pt_entry == NULL || pt_stuff == NULL) { - return PT_ERROR_PARAMETER; - } - - pt_table = &pt_stuff->pt_table; - pt_entries = pt_stuff->pt_entries; - - if (target_table_id == PT_TABLE_ID_INVALID) { - return PT_ERROR_TABLE_NOT_VALID; - } - - if (target_table_id == PT_TABLE_ID_0) { - write_addr = BFLB_PT_TABLE0_ADDRESS; - } else { - write_addr = BFLB_PT_TABLE1_ADDRESS; - } - - for (i = 0; i < pt_table->entryCnt; i++) { - if (pt_entries[i].type == pt_entry->type) { - ARCH_MemCpy_Fast(&pt_entries[i], pt_entry, sizeof(pt_table_entry_config)); - break; - } - } - - if (i == pt_table->entryCnt) { - /* Not found this entry ,add new one */ - if (pt_table->entryCnt < PT_ENTRY_MAX) { - ARCH_MemCpy_Fast(&pt_entries[pt_table->entryCnt], pt_entry, sizeof(pt_table_entry_config)); - pt_table->entryCnt++; - } else { - return PT_ERROR_ENTRY_UPDATE_FAIL; - } - } - - /* Prepare write back to flash */ - /* Update age */ - pt_table->age++; - pt_table->crc32 = BFLB_Soft_CRC32((uint8_t *)pt_table, sizeof(pt_table_config) - 4); - - /* Update entries CRC */ - entries_len = pt_table->entryCnt * sizeof(pt_table_entry_config); - crc32 = (uint32_t *)((uintptr_t)pt_entries + entries_len); - *crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_entries[0], entries_len); - - /* Write back to flash */ - /* Erase flash first */ - //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) + entries_len + 4 - 1); - ret = gp_pt_table_flash_erase(write_addr, sizeof(pt_table_config) + entries_len + 4); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - /* Write flash */ - ret = gp_pt_table_flash_write(write_addr, (uint8_t *)pt_stuff, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - return PT_ERROR_SUCCESS; -} - -/****************************************************************************/ /** - * @brief Create partition entry - * - * @param ptID: Partition table ID - * - * @return Partition create result - * -*******************************************************************************/ -pt_table_error_type pt_table_create(pt_table_id_type pt_id) -{ - uint32_t write_addr; - BL_Err_Type ret; - pt_table_config pt_table; - - if (pt_id == PT_TABLE_ID_INVALID) { - return PT_ERROR_TABLE_NOT_VALID; - } - - if (pt_id == PT_TABLE_ID_0) { - write_addr = BFLB_PT_TABLE0_ADDRESS; - } else { - write_addr = BFLB_PT_TABLE1_ADDRESS; - } - - /* Prepare write back to flash */ - pt_table.magicCode = BFLB_PT_MAGIC_CODE; - pt_table.version = 0; - pt_table.entryCnt = 0; - pt_table.age = 0; - pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_table, sizeof(pt_table_config) - 4); - /* Write back to flash */ - //ret = gp_pt_table_flash_erase(write_addr, write_addr + sizeof(pt_table_config) - 1); - ret = gp_pt_table_flash_erase(write_addr,sizeof(pt_table_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_ERASE; - } - - ret = gp_pt_table_flash_write(write_addr, (uint8_t *)&pt_table, sizeof(pt_table_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - - return PT_ERROR_SUCCESS; -} - -pt_table_error_type pt_table_dump(void) -{ - uint32_t pt_valid[2] = { 0, 0 }; - pt_table_stuff_config pt_stuff[2]; - - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); - pt_valid[0] = pt_table_valid(&pt_stuff[0]); - - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); - pt_valid[1] = pt_table_valid(&pt_stuff[1]); - - if (pt_valid[0]) { - MSG("PT TABLE0 valid\r\n"); - } else { - MSG("PT TABLE0 invalid\r\n"); - } - - if (pt_valid[1]) { - MSG("PT TABLE1 valid\r\n"); - } else { - MSG("PT TABLE1 invalid\r\n"); - } - - for (int i = 0; i < 2; i++) { - if (pt_valid[i] == 1) { - MSG("ptStuff[%d].pt_table.magicCode 0x%08x\r\n", i, pt_stuff[i].pt_table.magicCode); - MSG("ptStuff[%d].pt_table.version 0x%08x\r\n", i, pt_stuff[i].pt_table.version); - MSG("ptStuff[%d].pt_table.entryCnt 0x%08x\r\n", i, pt_stuff[i].pt_table.entryCnt); - MSG("ptStuff[%d].pt_table.age 0x%08x\r\n", i, pt_stuff[i].pt_table.age); - MSG("ptStuff[%d].pt_table.crc32 0x%08x\r\n", i, pt_stuff[i].pt_table.crc32); - - for (int j = 0; j < pt_stuff[i].pt_table.entryCnt; j++) { - MSG("ptStuff[%d].pt_entries[%d].type 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].type); - MSG("ptStuff[%d].pt_entries[%d].device 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].device); - MSG("ptStuff[%d].pt_entries[%d].active_index 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].active_index); - MSG("ptStuff[%d].pt_entries[%d].Address[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[0]); - MSG("ptStuff[%d].pt_entries[%d].Address[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].start_address[1]); - MSG("ptStuff[%d].pt_entries[%d].maxLen[0] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[0]); - MSG("ptStuff[%d].pt_entries[%d].maxLen[1] 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].max_len[1]); - MSG("ptStuff[%d].pt_entries[%d].len 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].len); - MSG("ptStuff[%d].pt_entries[%d].age 0x%08x\r\n", i, j, pt_stuff[i].pt_entries[j].age); - } - } - } - - return PT_ERROR_SUCCESS; -} - -pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para) -{ - uint32_t pt_valid[2] = { 0, 0 }; - pt_table_stuff_config pt_stuff[2]; - uint8_t active_index; - - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff[0], sizeof(pt_table_stuff_config)); - pt_valid[0] = pt_table_valid(&pt_stuff[0]); - - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff[1], sizeof(pt_table_stuff_config)); - pt_valid[1] = pt_table_valid(&pt_stuff[1]); - - if ((pt_valid[0] == 1) && (pt_valid[1] == 1)) { - if (pt_stuff[0].pt_table.age >= pt_stuff[1].pt_table.age) { - active_index = pt_stuff[0].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 1; - - } else { - active_index = pt_stuff[1].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 0; - } - - } else if (pt_valid[1] == 1) { - active_index = pt_stuff[1].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[1].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 0; - } else if (pt_valid[0] == 1) { - active_index = pt_stuff[0].pt_entries[0].active_index; - para->iap_write_addr = para->iap_start_addr = pt_stuff[0].pt_entries[0].start_address[!(active_index & 0x01)]; - para->inactive_index = !(active_index & 0x01); - para->inactive_table_index = 1; - } else { - return PT_ERROR_TABLE_NOT_VALID; - } - - MSG("inactive_table_index %d, inactive index %d , IAP start addr %08x \r\n", para->inactive_table_index, para->inactive_index, para->iap_start_addr); - return PT_ERROR_SUCCESS; -} - -pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para) -{ - pt_table_stuff_config pt_stuff, pt_stuff_write; - int32_t ret; - uint32_t *p_crc32; - uint32_t entries_len; - - if (para->inactive_table_index == 1) { - gp_pt_table_flash_read(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); - } else if (para->inactive_table_index == 0) { - gp_pt_table_flash_read(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff, sizeof(pt_table_stuff_config)); - } - - ARCH_MemCpy_Fast((void *)&pt_stuff_write, (void *)&pt_stuff, sizeof(pt_table_stuff_config)); - pt_stuff_write.pt_table.age += 1; - pt_stuff_write.pt_entries[0].active_index = !(pt_stuff_write.pt_entries[0].active_index & 0x01); - pt_stuff_write.pt_table.crc32 = BFLB_Soft_CRC32((uint8_t *)&pt_stuff_write, sizeof(pt_table_config) - 4); - entries_len = sizeof(pt_table_entry_config) * pt_stuff_write.pt_table.entryCnt; - //pt_stuff_write.crc32 = BFLB_Soft_CRC32((uint8_t*)pt_stuff_write.pt_entries,entries_len); - p_crc32 = (uint32_t *)((uintptr_t)pt_stuff_write.pt_entries + entries_len); - *p_crc32 = BFLB_Soft_CRC32((uint8_t *)pt_stuff_write.pt_entries, entries_len); - - if (para->inactive_table_index == 1) { - //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, BFLB_PT_TABLE1_ADDRESS + sizeof(pt_table_stuff_config) - 1); - ret = gp_pt_table_flash_erase(BFLB_PT_TABLE1_ADDRESS, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_ERASE; - } - - ret = gp_pt_table_flash_write(BFLB_PT_TABLE1_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - } else if (para->inactive_table_index == 0) { - //ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, BFLB_PT_TABLE0_ADDRESS + sizeof(pt_table_stuff_config) - 1); - ret = gp_pt_table_flash_erase(BFLB_PT_TABLE0_ADDRESS, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Erase error\r\n"); - return PT_ERROR_FALSH_ERASE; - } - - ret = gp_pt_table_flash_write(BFLB_PT_TABLE0_ADDRESS, (uint8_t *)&pt_stuff_write, sizeof(pt_table_stuff_config)); - - if (ret != SUCCESS) { - MSG_ERR("Flash Write error\r\n"); - return PT_ERROR_FALSH_WRITE; - } - } - - MSG("Update pt_table suss\r\n"); - return PT_ERROR_SUCCESS; -} - -/*@} end of group PARTITION_Public_Functions */ - -/*@} end of group PARTITION */ - -/*@} end of group BFLB_Common_Driver */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h deleted file mode 100644 index f20332dcd8..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/partition/partition.h +++ /dev/null @@ -1,209 +0,0 @@ -/** - ****************************************************************************** - * @file partition.h - * @version V1.0 - * @date - * @brief This file is the standard driver header file - ****************************************************************************** - * @attention - * - *

© COPYRIGHT(c) 2020 Bouffalo Lab

- * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of Bouffalo Lab nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ -#ifndef __PARTITION_H__ -#define __PARTITION_H__ - -#include "misc.h" - -/** @addtogroup BFLB_Common_Driver - * @{ - */ - -/** @addtogroup PARTITION - * @{ - */ - -/** @defgroup PARTITION_Public_Types - * @{ - */ - -/** - * @brief Partition table error type definition - */ -typedef enum { - PT_ERROR_SUCCESS, /*!< Partition table error type:success */ - PT_ERROR_TABLE_NOT_VALID, /*!< Partition table error type:table not found */ - PT_ERROR_ENTRY_NOT_FOUND, /*!< Partition table error type:entry not found */ - PT_ERROR_ENTRY_UPDATE_FAIL, /*!< Partition table error type:entry update fail */ - PT_ERROR_CRC32, /*!< Partition table error type:crc32 error */ - PT_ERROR_PARAMETER, /*!< Partition table error type:input parameter error */ - PT_ERROR_FALSH_READ, /*!< Partition table error type:flash read error */ - PT_ERROR_FALSH_WRITE, /*!< Partition table error type:flash write error */ - PT_ERROR_FALSH_ERASE, /*!< Partition table error type:flash erase error */ -} pt_table_error_type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_TABLE_ID_0, /*!< Partition table ID 0 */ - PT_TABLE_ID_1, /*!< Partition table ID 1 */ - PT_TABLE_ID_INVALID, /*!< Partition table ID invalid */ -} pt_table_id_type; - -/** - * @brief Partition id type definition - */ -typedef enum { - PT_ENTRY_FW_CPU0, /*!< Partition entry type:CPU0 firmware */ - PT_ENTRY_FW_CPU1, /*!< Partition entry type:CPU1 firmware */ - PT_ENTRY_MAX = 16, /*!< Partition entry type:Max */ -} pt_table_entry_type; - -/** - * @brief Partition table config definition - */ -typedef struct -{ - uint32_t magicCode; /*!< Partition table magic code */ - uint16_t version; /*!< Partition table verdion */ - uint16_t entryCnt; /*!< Partition table entry count */ - uint32_t age; /*!< Partition table age */ - uint32_t crc32; /*!< Partition table CRC32 value */ -} pt_table_config; - -/** - * @brief Partition table entry config definition - */ -typedef struct -{ - uint8_t type; /*!< Partition entry type */ - uint8_t device; /*!< Partition entry device */ - uint8_t active_index; /*!< Partition entry active index */ - uint8_t name[9]; /*!< Partition entry name */ - uint32_t start_address[2]; /*!< Partition entry start address */ - uint32_t max_len[2]; /*!< Partition entry max length */ - uint32_t len; /*!< Partition entry length */ - uint32_t age; /*!< Partition entry age */ -} pt_table_entry_config; - -/** - * @brief Partition table stuff config definition - */ -typedef struct -{ - pt_table_config pt_table; /*!< Partition table */ - pt_table_entry_config pt_entries[PT_ENTRY_MAX]; /*!< Partition entries */ - uint32_t crc32; /*!< Partition entries crc32 */ -} pt_table_stuff_config; - -/** - * @brief Partition table iap param definition - */ -typedef struct -{ - uint32_t iap_start_addr; - uint32_t iap_write_addr; - uint32_t iap_img_len; - uint8_t inactive_index; - uint8_t inactive_table_index; -} pt_table_iap_param_type; - -/*@} end of group PARTITION_Public_Types */ - -/** @defgroup PARTITION_Public_Constants - * @{ - */ - -/** @defgroup pt_table_error_type - * @{ - */ -#define IS_PTTABLE_ERROR_TYPE(type) (((type) == PT_ERROR_SUCCESS) || \ - ((type) == PT_ERROR_TABLE_NOT_VALID) || \ - ((type) == PT_ERROR_ENTRY_NOT_FOUND) || \ - ((type) == PT_ERROR_ENTRY_UPDATE_FAIL) || \ - ((type) == PT_ERROR_CRC32) || \ - ((type) == PT_ERROR_PARAMETER) || \ - ((type) == PT_ERROR_FALSH_READ) || \ - ((type) == PT_ERROR_FALSH_WRITE) || \ - ((type) == PT_ERROR_FALSH_ERASE)) - -/** @defgroup pt_table_id_type - * @{ - */ -#define IS_PTTABLE_ID_TYPE(type) (((type) == PT_TABLE_ID_0) || \ - ((type) == PT_TABLE_ID_1) || \ - ((type) == PT_TABLE_ID_INVALID)) - -/** @defgroup pt_table_entry_type - * @{ - */ -#define IS_PTTABLE_ENTRY_TYPE(type) (((type) == PT_ENTRY_FW_CPU0) || \ - ((type) == PT_ENTRY_FW_CPU1) || \ - ((type) == PT_ENTRY_MAX)) - -/*@} end of group PARTITION_Public_Constants */ - -/** @defgroup PARTITION_Public_Macros - * @{ - */ -#define BFLB_PT_TABLE0_ADDRESS 0xE000 -#define BFLB_PT_TABLE1_ADDRESS 0xF000 -#define BFLB_PT_MAGIC_CODE 0x54504642 -typedef BL_Err_Type (*p_pt_table_flash_erase)(uint32_t startaddr, uint32_t endaddr); -typedef BL_Err_Type (*p_pt_table_flash_write)(uint32_t addr, uint8_t *data, uint32_t len); -typedef BL_Err_Type (*p_pt_table_flash_read)(uint32_t addr, uint8_t *data, uint32_t len); - -/*@} end of group PARTITION_Public_Macros */ - -/** @defgroup PARTITION_Public_Functions - * @{ - */ -void pt_table_set_flash_operation(p_pt_table_flash_erase erase, p_pt_table_flash_write write, p_pt_table_flash_read read); -pt_table_id_type pt_table_get_active_partition_need_lock(pt_table_stuff_config ptStuff[2]); -pt_table_error_type pt_table_get_active_entries_by_id(pt_table_stuff_config *pt_stuff, - pt_table_entry_type type, - pt_table_entry_config *pt_entry); -pt_table_error_type pt_table_get_active_entries_by_name(pt_table_stuff_config *pt_stuff, - uint8_t *name, - pt_table_entry_config *pt_entry); -pt_table_error_type pt_table_update_entry(pt_table_id_type target_table_id, - pt_table_stuff_config *pt_stuff, - pt_table_entry_config *pt_entry); -pt_table_error_type pt_table_create(pt_table_id_type pt_id); -pt_table_error_type pt_table_dump(void); -pt_table_error_type pt_table_get_iap_para(pt_table_iap_param_type *para); -pt_table_error_type pt_table_set_iap_para(pt_table_iap_param_type *para); - -/*@} end of group PARTITION_Public_Functions */ - -/*@} end of group PARTITION */ - -/*@} end of group BFLB_Common_Driver */ - -extern pt_table_iap_param_type p_iap_param; - -#endif /* __PARTITION_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c deleted file mode 100644 index c7d6da8593..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.c +++ /dev/null @@ -1,68 +0,0 @@ -/** - * @file pid.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "pid.h" - -void pid_init(pid_alg_t *pid) -{ - pid->set_val = 0.0f; - pid->out_val = 0.0f; - - pid->last_error = 0.0f; - pid->prev_error = 0.0f; - - pid->kp = 3.0f; - pid->ki = 0.0f; - pid->kd = 0.0f; - - pid->i_error = 0.0f; - pid->sum_error = 0.0f; - - pid->max_val = 32; - pid->min_val = -32; -} - -// standard pid -float standard_pid_cal(pid_alg_t *pid, float next_val) -{ - pid->set_val = next_val; - pid->i_error = pid->set_val - pid->out_val; - pid->sum_error += pid->i_error; - pid->out_val = pid->kp * pid->i_error + pid->ki * pid->sum_error + pid->kd * (pid->i_error - pid->last_error); - pid->last_error = pid->i_error; - - return pid->out_val; -} - -// increment pid -float increment_pid_cal(pid_alg_t *pid, float next_val) -{ - pid->set_val = next_val; - pid->i_error = pid->set_val - pid->out_val; - float increment = pid->kp * (pid->i_error - pid->prev_error) + pid->ki * pid->i_error + pid->kd * (pid->i_error - 2 * pid->prev_error + pid->last_error); - pid->out_val += increment; - pid->last_error = pid->prev_error; - pid->prev_error = pid->i_error; - - return pid->out_val; -} diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h deleted file mode 100644 index 5323790f20..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/pid/pid.h +++ /dev/null @@ -1,50 +0,0 @@ -/** - * @file pid.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#ifndef __PID_H__ -#define __PID_H__ - -#include "stdint.h" - -typedef struct pid_alg { - float set_val; - float out_val; - - float kp; - float ki; - float kd; - - float i_error; - float last_error; - float prev_error; - float sum_error; - - int max_val; - int min_val; -} pid_alg_t; - -void pid_init(pid_alg_t *pid); -float standard_pid_cal(pid_alg_t *pid, float next_val); -float increment_pid_cal(pid_alg_t *pid, float next_val); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c deleted file mode 100644 index ec91c71578..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.c +++ /dev/null @@ -1,679 +0,0 @@ -/** - * @file ring_buffer.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#include "ring_buffer.h" - -/** @addtogroup BL_Common_Component - * @{ - */ - -/** @addtogroup RING_BUFFER - * @{ - */ - -/** @defgroup RING_BUFFER_Private_Macros - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Macros */ - -/** @defgroup RING_BUFFER_Private_Types - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Types */ - -/** @defgroup RING_BUFFER_Private_Fun_Declaration - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Fun_Declaration */ - -/** @defgroup RING_BUFFER_Private_Variables - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Variables */ - -/** @defgroup RING_BUFFER_Global_Variables - * @{ - */ - -/*@} end of group RING_BUFFER_Global_Variables */ - -/** @defgroup RING_BUFFER_Private_Functions - * @{ - */ - -/*@} end of group RING_BUFFER_Private_Functions */ - -/** @defgroup RING_BUFFER_Public_Functions - * @{ - */ - -/****************************************************************************/ /** - * @brief Ring buffer init function - * - * @param rbType: Ring buffer type structure pointer - * @param buffer: Pointer of ring buffer - * @param size: Size of ring buffer - * @param lockCb: Ring buffer lock callback function pointer - * @param unlockCb: Ring buffer unlock callback function pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, ringBuffer_Lock_Callback *unlockCb) -{ - /* Init ring buffer pointer */ - rbType->pointer = buffer; - - /* Init read/write mirror and index */ - rbType->readMirror = 0; - rbType->readIndex = 0; - rbType->writeMirror = 0; - rbType->writeIndex = 0; - - /* Set ring buffer size */ - rbType->size = size; - - /* Set lock and unlock callback function */ - rbType->lock = lockCb; - rbType->unlock = unlockCb; - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Ring buffer reset function - * - * @param rbType: Ring buffer type structure pointer - * - * @return SUCCESS - * -*******************************************************************************/ -BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Clear read/write mirror and index */ - rbType->readMirror = 0; - rbType->readIndex = 0; - rbType->writeMirror = 0; - rbType->writeIndex = 0; - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return SUCCESS; -} - -/****************************************************************************/ /** - * @brief Use callback function to write ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param length: Length of data want to write - * @param writeCb: Callback function pointer - * @param parameter: Parameter that callback function may use - * - * @return Length of data actually write - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, void *parameter) -{ - uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); - - if (writeCb == NULL) { - return 0; - } - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no space for new data */ - if (sizeRemained == 0) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Drop part of data when length out of space remained */ - if (length > sizeRemained) { - length = sizeRemained; - } - - /* Get size of space remained in current mirror */ - sizeRemained = rbType->size - rbType->writeIndex; - - if (sizeRemained > length) { - /* Space remained is enough for data in current mirror */ - writeCb(parameter, &rbType->pointer[rbType->writeIndex], length); - rbType->writeIndex += length; - } else { - /* Data is divided to two parts with different mirror */ - writeCb(parameter, &rbType->pointer[rbType->writeIndex], sizeRemained); - writeCb(parameter, &rbType->pointer[0], length - sizeRemained); - rbType->writeIndex = length - sizeRemained; - rbType->writeMirror = ~rbType->writeMirror; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Copy data from data buffer to ring buffer function - * - * @param parameter: Pointer to source pointer - * @param dest: Ring buffer to write - * @param length: Length of data to write - * - * @return None - * -*******************************************************************************/ -static void Ring_Buffer_Write_Copy(void *parameter, uint8_t *dest, uint32_t length) -{ - uint8_t **src = (uint8_t **)parameter; - - ARCH_MemCpy_Fast(dest, *src, length); - *src += length; -} - -/****************************************************************************/ /** - * @brief Write ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * @param length: Length of data - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) -{ - return Ring_Buffer_Write_Callback(rbType, length, Ring_Buffer_Write_Copy, &data); -} - -/****************************************************************************/ /** - * @brief Write 1 byte to ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no space for new data */ - if (!Ring_Buffer_Get_Empty_Length(rbType)) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - rbType->pointer[rbType->writeIndex] = data; - - /* Judge to change index and mirror */ - if (rbType->writeIndex != (rbType->size - 1)) { - rbType->writeIndex++; - } else { - rbType->writeIndex = 0; - rbType->writeMirror = ~rbType->writeMirror; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Write ring buffer function, old data will be covered by new data when ring buffer is - * full - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * @param length: Length of data - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length) -{ - uint32_t sizeRemained = Ring_Buffer_Get_Empty_Length(rbType); - uint32_t indexRemained = rbType->size - rbType->writeIndex; - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Drop extra data when data length is large than size of ring buffer */ - if (length > rbType->size) { - data = &data[length - rbType->size]; - length = rbType->size; - } - - if (indexRemained > length) { - /* Space remained is enough for data in current mirror */ - ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, length); - rbType->writeIndex += length; - - /* Update read index */ - if (length > sizeRemained) { - rbType->readIndex = rbType->writeIndex; - } - } else { - /* Data is divided to two parts with different mirror */ - ARCH_MemCpy_Fast(&rbType->pointer[rbType->writeIndex], data, indexRemained); - ARCH_MemCpy_Fast(&rbType->pointer[0], &data[indexRemained], length - indexRemained); - rbType->writeIndex = length - indexRemained; - rbType->writeMirror = ~rbType->writeMirror; - - /* Update read index and mirror */ - if (length > sizeRemained) { - rbType->readIndex = rbType->writeIndex; - rbType->readMirror = ~rbType->readMirror; - } - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Write 1 byte to ring buffer function, old data will be covered by new data when ring - * buffer is full - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data to write - * - * @return Length of data writted actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data) -{ - Ring_Buffer_Status_Type status = Ring_Buffer_Get_Status(rbType); - - if (rbType->lock != NULL) { - rbType->lock(); - } - - rbType->pointer[rbType->writeIndex] = data; - - /* Judge to change index and mirror */ - if (rbType->writeIndex == rbType->size - 1) { - rbType->writeIndex = 0; - rbType->writeMirror = ~rbType->writeMirror; - - /* Update read index and mirror */ - if (status == RING_BUFFER_FULL) { - rbType->readIndex = rbType->writeIndex; - rbType->readMirror = ~rbType->readMirror; - } - } else { - rbType->writeIndex++; - - /* Update read index */ - if (status == RING_BUFFER_FULL) { - rbType->readIndex = rbType->writeIndex; - } - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Use callback function to read ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param length: Length of data want to read - * @param readCb: Callback function pointer - * @param parameter: Parameter that callback function may use - * - * @return Length of data actually read - * -*******************************************************************************/ -uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, void *parameter) -{ - uint32_t size = Ring_Buffer_Get_Length(rbType); - - if (readCb == NULL) { - return 0; - } - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!size) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Ring buffer do not have enough data */ - if (size < length) { - length = size; - } - - /* Get size of space remained in current mirror */ - size = rbType->size - rbType->readIndex; - - if (size > length) { - /* Read all data needed */ - readCb(parameter, &rbType->pointer[rbType->readIndex], length); - rbType->readIndex += length; - } else { - /* Read two part of data in different mirror */ - readCb(parameter, &rbType->pointer[rbType->readIndex], size); - readCb(parameter, &rbType->pointer[0], length - size); - rbType->readIndex = length - size; - rbType->readMirror = ~rbType->readMirror; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Copy data from ring buffer to data buffer function - * - * @param parameter: Pointer to destination pointer - * @param data: Data buffer to copy - * @param length: Length of data to copy - * - * @return None - * -*******************************************************************************/ -static void Ring_Buffer_Read_Copy(void *parameter, uint8_t *data, uint32_t length) -{ - uint8_t **dest = (uint8_t **)parameter; - - ARCH_MemCpy_Fast(*dest, data, length); - *dest += length; -} - -/****************************************************************************/ /** - * @brief Read ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Buffer for data read - * @param length: Length of data to read - * - * @return Length of data read actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) -{ - return Ring_Buffer_Read_Callback(rbType, length, Ring_Buffer_Read_Copy, &data); -} - -/****************************************************************************/ /** - * @brief Read 1 byte from ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data read - * - * @return Length of data actually read - * -*******************************************************************************/ -uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!Ring_Buffer_Get_Length(rbType)) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Read data */ - *data = rbType->pointer[rbType->readIndex]; - - /* Update read index and mirror */ - if (rbType->readIndex == rbType->size - 1) { - rbType->readIndex = 0; - rbType->readMirror = ~rbType->readMirror; - } else { - rbType->readIndex++; - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Read ring buffer function, do not remove from buffer actually - * - * @param rbType: Ring buffer type structure pointer - * @param data: Buffer for data read - * @param length: Length of data to read - * - * @return Length of data read actually - * -*******************************************************************************/ -uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length) -{ - uint32_t size = Ring_Buffer_Get_Length(rbType); - - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!size) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Ring buffer do not have enough data */ - if (size < length) { - length = size; - } - - /* Get size of space remained in current mirror */ - size = rbType->size - rbType->readIndex; - - if (size > length) { - /* Read all data needed */ - ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], length); - } else { - /* Read two part of data in different mirror */ - ARCH_MemCpy_Fast(data, &rbType->pointer[rbType->readIndex], size); - ARCH_MemCpy_Fast(&data[size], &rbType->pointer[0], length - size); - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return length; -} - -/****************************************************************************/ /** - * @brief Read 1 byte from ring buffer function, do not remove from buffer actually - * - * @param rbType: Ring buffer type structure pointer - * @param data: Data read - * - * @return Length of data actually read - * -*******************************************************************************/ -uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Ring buffer has no data */ - if (!Ring_Buffer_Get_Length(rbType)) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 0; - } - - /* Read data */ - *data = rbType->pointer[rbType->readIndex]; - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return 1; -} - -/****************************************************************************/ /** - * @brief Get length of data in ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * - * @return Length of data - * -*******************************************************************************/ -uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType) -{ - uint32_t readMirror = 0; - uint32_t writeMirror = 0; - uint32_t readIndex = 0; - uint32_t writeIndex = 0; - uint32_t size = 0; - - if (rbType->lock != NULL) { - rbType->lock(); - } - - readMirror = rbType->readMirror; - writeMirror = rbType->writeMirror; - readIndex = rbType->readIndex; - writeIndex = rbType->writeIndex; - size = rbType->size; - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - if (readMirror == writeMirror) { - return writeIndex - readIndex; - } else { - return size - (readIndex - writeIndex); - } -} - -/****************************************************************************/ /** - * @brief Get space remained in ring buffer function - * - * @param rbType: Ring buffer type structure pointer - * - * @return Length of space remained - * -*******************************************************************************/ -uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType) -{ - return (rbType->size - Ring_Buffer_Get_Length(rbType)); -} - -/****************************************************************************/ /** - * @brief Get ring buffer status function - * - * @param rbType: Ring buffer type structure pointer - * - * @return Status of ring buffer - * -*******************************************************************************/ -Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType) -{ - if (rbType->lock != NULL) { - rbType->lock(); - } - - /* Judge empty or full */ - if (rbType->readIndex == rbType->writeIndex) { - if (rbType->readMirror == rbType->writeMirror) { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return RING_BUFFER_EMPTY; - } else { - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return RING_BUFFER_FULL; - } - } - - if (rbType->unlock != NULL) { - rbType->unlock(); - } - - return RING_BUFFER_PARTIAL; -} - -/*@} end of group RING_BUFFER_Public_Functions */ - -/*@} end of group RING_BUFFER */ - -/*@} end of group BL_Common_Component */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h deleted file mode 100644 index dbc6681994..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/ring_buffer/ring_buffer.h +++ /dev/null @@ -1,116 +0,0 @@ -/** - * @file ring_buffer.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __RING_BUFFER_H__ -#define __RING_BUFFER_H__ - -#include "misc.h" - -/** @addtogroup BL_Common_Component - * @{ - */ - -/** @addtogroup RING_BUFFER - * @{ - */ - -/** @defgroup RING_BUFFER_Public_Types - * @{ - */ - -/** - * @brief Ring buffer status type definition - */ -typedef enum { - RING_BUFFER_EMPTY, /*!< Ring buffer is empty */ - RING_BUFFER_PARTIAL, /*!< Ring buffer has partial data */ - RING_BUFFER_FULL, /*!< Ring buffer is full */ -} Ring_Buffer_Status_Type; - -/** - * @brief Ring buffer structure definition - */ -typedef struct -{ - uint8_t *pointer; /*!< Pointer of ring buffer */ - uint8_t readMirror; /*!< Read mirror,used to judge empty or full */ - uint32_t readIndex; /*!< Index of read address */ - uint8_t writeMirror; /*!< Write mirror,used to judge empty or full */ - uint32_t writeIndex; /*!< Index of write address */ - uint32_t size; /*!< Size of ring buffer */ - void (*lock)(void); /*!< Lock ring buffer */ - void (*unlock)(void); /*!< Unlock ring buffer */ -} Ring_Buffer_Type; - -/*@} end of group RING_BUFFER_Public_Types */ - -/** @defgroup RING_BUFFER_Public_Constants - * @{ - */ - -/** @defgroup RING_BUFFER_STATUS_TYPE - * @{ - */ -#define IS_RING_BUFFER_STATUS_TYPE(type) (((type) == RING_BUFFER_EMPTY) || \ - ((type) == RING_BUFFER_PARTIAL) || \ - ((type) == RING_BUFFER_FULL)) - -/*@} end of group RING_BUFFER_Public_Constants */ - -/** @defgroup RING_BUFFER_Public_Macros - * @{ - */ -typedef void(ringBuffer_Lock_Callback)(void); -typedef void(ringBuffer_Read_Callback)(void *, uint8_t *, uint32_t); -typedef void(ringBuffer_Write_Callback)(void *, uint8_t *, uint32_t); - -/*@} end of group RING_BUFFER_Public_Macros */ - -/** @defgroup RING_BUFFER_Public_Functions - * @{ - */ -BL_Err_Type Ring_Buffer_Init(Ring_Buffer_Type *rbType, uint8_t *buffer, uint32_t size, ringBuffer_Lock_Callback *lockCb, - ringBuffer_Lock_Callback *unlockCb); -BL_Err_Type Ring_Buffer_Reset(Ring_Buffer_Type *rbType); -uint32_t Ring_Buffer_Write_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Write_Callback *writeCb, - void *parameter); -uint32_t Ring_Buffer_Write(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Write_Byte(Ring_Buffer_Type *rbType, const uint8_t data); -uint32_t Ring_Buffer_Write_Force(Ring_Buffer_Type *rbType, const uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Write_Byte_Force(Ring_Buffer_Type *rbType, const uint8_t data); -uint32_t Ring_Buffer_Read_Callback(Ring_Buffer_Type *rbType, uint32_t length, ringBuffer_Read_Callback *readCb, - void *parameter); -uint32_t Ring_Buffer_Read(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Read_Byte(Ring_Buffer_Type *rbType, uint8_t *data); -uint32_t Ring_Buffer_Peek(Ring_Buffer_Type *rbType, uint8_t *data, uint32_t length); -uint32_t Ring_Buffer_Peek_Byte(Ring_Buffer_Type *rbType, uint8_t *data); -uint32_t Ring_Buffer_Get_Length(Ring_Buffer_Type *rbType); -uint32_t Ring_Buffer_Get_Empty_Length(Ring_Buffer_Type *rbType); -Ring_Buffer_Status_Type Ring_Buffer_Get_Status(Ring_Buffer_Type *rbType); - -/*@} end of group RING_BUFFER_Public_Functions */ - -/*@} end of group RING_BUFFER */ - -/*@} end of group BL_Common_Component */ - -#endif /* __RING_BUFFER_H__ */ diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h deleted file mode 100644 index c56ab26d23..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.h +++ /dev/null @@ -1,32 +0,0 @@ -/** - * @file softcrc.h - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ -#ifndef __SOFTCRC_H__ -#define __SOFTCRC_H__ - -#include "stdint.h" - -uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len); -uint32_t BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len); -uint32_t BFLB_Soft_CRC32(void *dataIn, uint32_t len); - -#endif diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c deleted file mode 100644 index 74a5b2cc3a..0000000000 --- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.c +++ /dev/null @@ -1,136 +0,0 @@ -/** - * @file timestamp.c - * @brief - * - * Copyright (c) 2021 Bouffalolab team - * - * Licensed to the Apache Software Foundation (ASF) under one or more - * contributor license agreements. See the NOTICE file distributed with - * this work for additional information regarding copyright ownership. The - * ASF licenses this file to you under the Apache License, Version 2.0 (the - * "License"); you may not use this file except in compliance with the - * License. You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT - * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the - * License for the specific language governing permissions and limitations - * under the License. - * - */ - -#include "timestamp.h" - -#define FOUR_YEAR_DAY ((365 << 2) + 1) //The total number of days in a 4-year cycle -#define TIMEZONE (8) //Beijing time Zone adjustment - -#define SEC_NUM_PER_DAY (24 * 60 * 60) -#define SEC_NUM_PER_HOUR (60 * 60) -#define SEC_NUM_PER_MINUTE (60) - -static uint8_t month_day[12] = { 31, 28, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //平年 -static uint8_t Leap_month_day[12] = { 31, 29, 31, 30, 31, 30, 31, 31, 30, 31, 30, 31 }; //闰年 - -/** -* @bref judge if it is a leap year -* @para year to be judge -* @return 1：leap year 0： nonleap year -*/ -bool check_leap_year(uint16_t year) -{ - if (year % 4) { - return false; - } else { - if ((year % 100 == 0) && (year % 400 != 0)) { - return false; - } else { - return true; - } - } -} - -void cal_weekday(rtc_time *beijing_time) -{ - uint32_t y,m,d,w; - - y=beijing_time->year; - m=beijing_time->month; - d=beijing_time->day; - - if((m==1)||(m==2)) - { - m+=12; - y--; - } - /* - 把一月和二月看成是上一年的十三月和十四月，例：如果是2004-1-10则换算成：2003-13-10来代入公式计算。 - 以公元元年为参考，公元元年1月1日为星期一
程序如下：
-    利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)
-    */
-    w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400+1)%7;
-
-    beijing_time->week=(uint8_t)w;
-}
-
-void unixtime2bejingtime(uint32_t unixtime, rtc_time *beijing_time)
-{
-    uint32_t totle_day_num;
-    uint32_t current_sec_num;
-
-    uint16_t remain_day;
-
-    uint16_t temp_year;
-
-    uint8_t *p = NULL;
-
-    totle_day_num = unixtime / SEC_NUM_PER_DAY;   //The total number of days
-    current_sec_num = unixtime % SEC_NUM_PER_DAY; //The number of seconds this day
-
-    /* use the number of seconds this day, To calculate hour\minute\second */
-    beijing_time->hour = current_sec_num / SEC_NUM_PER_HOUR;
-    beijing_time->minute = (current_sec_num % SEC_NUM_PER_HOUR) / SEC_NUM_PER_MINUTE;
-    beijing_time->second = (current_sec_num % SEC_NUM_PER_HOUR) % SEC_NUM_PER_MINUTE;
-
-    /* Adjust the time zone and check whether the date is +1 */
-    beijing_time->hour += 8;
-    if (beijing_time->hour > 23) {
-        beijing_time->hour -= 24;
-        totle_day_num++;
-    }
-
-
-    /* calculate year */
-    beijing_time->year = 1970 + (totle_day_num / FOUR_YEAR_DAY) * 4; // 4-year as a cycle
-    remain_day = totle_day_num % FOUR_YEAR_DAY;                      //remaining day nym( < 4 year )
-
-    /* calculate year & day */
-    temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
-    while (remain_day >= temp_year) {
-        beijing_time->year++;
-        remain_day -= temp_year;
-        temp_year = check_leap_year(beijing_time->year) ? 366 : 365;
-    }
-
-    /* Calculate specific dates(month\day)*/
-    p = check_leap_year(beijing_time->year) ? Leap_month_day : month_day;
-    remain_day++; //The actual day starts at 1
-    beijing_time->month = 0;
-    while (remain_day > *(p + beijing_time->month)) {
-        remain_day -= *(p + beijing_time->month);
-        beijing_time->month++;
-    }
-
-    beijing_time->month++; //The actual month starts at 1
-    beijing_time->day = remain_day;
-
-
-
-    /*利用基姆拉尔森计算日期公式  w=(d+2*m+3*(m+1)/5+y+y/4-y/100+y/400)*/
-
-    beijing_time->week = beijing_time->day + 2*beijing_time->month + 3*(beijing_time->month+1)/5 + \
-    beijing_time->year + beijing_time->year/4 - beijing_time->year/100 +beijing_time->year/400 ;
-
-    cal_weekday(beijing_time);
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h b/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h
deleted file mode 100644
index 5986baf91c..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/timestamp/timestamp.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/**
- * @file timestamp.h
- * @brief
- *
- * Copyright (c) 2021 Bouffalolab team
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- */
-#ifndef _TIMESTAMP_
-#define _TIMESTAMP_
-
-#include "stdint.h"
-#include "stddef.h"
-#include "stdbool.h"
-
-typedef struct _rtc_time_t
-{
-    uint16_t year;
-    uint8_t month;
-    uint8_t day;
-    uint8_t week;
-    uint8_t hour;
-    uint8_t minute;
-    uint8_t second;
-}rtc_time;
-
-void unixtime2bejingtime(uint32_t unixtime,rtc_time* beijing_time);
-
-#endif
-
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld
deleted file mode 100644
index da0ef735e2..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash.ld
+++ /dev/null
@@ -1,350 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-BOOT2_PT_ADDR = 0x62047e00;
-BOOT2_FLASHCFG_ADDR = 0x62047f14;
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M
-    xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K 
-    ram_memory  (!rx) : ORIGIN = 0x22024000, LENGTH = 48K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 96K 
-    ram_psram  (!rx)  : ORIGIN = 0x54000000, LENGTH = 4M
-    bugkill   (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text.boot :
-    {
-        . = ALIGN(4);
-    
-        *(.text.entry)
-
-        . = ALIGN(4);
-    } > flash
-
-    .bugkiller_command :
-    {
-        PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );
-        PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );
-        KEEP (*(.static_bugkiller_command))
-    } > bugkill
-
-    .bugkiller :
-    {
-        KEEP (*(.bugkiller_code))
-        KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))
-    } > bugkill
-
-    .psram_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __psram_ram_data_start__ = .;
- 
-        *(.psram_data.*)
-        *liblwip.a:*.o(.text*)
-        *libwifi.a:*.o(.text*)
-        *libwifi_manager.a:*.o(.text*)
-        *libfreertos_e907.a:*.o(.text*)
-        *libnetutils.a:*.o(.text*)
-        *libutils.a:*.o(.text*)
-        *libstartup_bl808.a:debug.o(.text*)
-
-        *liblwip.a:*.o(.rodata*)
-        *libwifi.a:*.o(.rodata*)
-        *libwifi_manager.a:*.o(.rodata*)
-        *libfreertos_e907.a:*.o(.rodata*)
-        *libnetutils.a:*.o(.rodata*)
-        *libutils.a:*.o(.rodata*)
-        *libstartup_bl808.a:debug.o(.rodata*)
-        
-        . = ALIGN(4);
-        __psram_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-    
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.tcm_const.*)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_code.*)
-        *(.sclock_rlt_const)
-        *(.sclock_rlt_const.*)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > ram_psram AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-	PROVIDE ( _sp_base = . );
-        . = ALIGN(64);
-        __stack_protect_start = .;
-        . = . + 256;
-        __stack_protect_end = .;
-        . = . + StackSize;
-        . = ALIGN(64);
-	PROVIDE( _sp_main = . );
-    } > ram_psram
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .xrambss  (NOLOAD) :
-    {
-        __xram_load_addr = .;
-        
-        . = ALIGN(4);
-        __xram_data_start__ = .;
-
-        *(.static_xram_region)
-
-        __xram_data_end__ = .;
-        . = ALIGN(4);
-    } > xram_memory
-
-    .ocram_bss_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __ocram_bss_start__ = .;
-
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __ocram_bss_end__ = .;
-    } > ram_memory
-
-    .boot2 (NOLOAD) :
-    {
-        PROVIDE ( __boot2_pt_addr_start = . );
-        *(.bss.boot2_partition_table)
-        PROVIDE ( __boot2_pt_addr_end   = . );
-
-        PROVIDE ( __boot2_flashCfg_start = . );
-        *(.bss.boot2_flashCfg)
-        PROVIDE ( __boot2_flashCfg_end = . );
-
-    } > ram_psram
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_psram 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_psram 
-
-    __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = ADDR(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_psram) + LENGTH(ram_psram);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    /*BOOT2 sections*/
-    PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
-    PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-    PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );
-    PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld
deleted file mode 100644
index d2001b4ffd..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_flash_rom.ld
+++ /dev/null
@@ -1,252 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0xD8000000, LENGTH = 4M
-    itcm_memory (rx)  : ORIGIN = 0xC2024000, LENGTH = 48K
-    dtcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22010000, LENGTH = 64K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 160K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-    
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(4);
-        . = . + StackSize;
-        . = ALIGN(4);
-    } > dtcm_memory
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory AT > flash
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_memory 
-
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld
deleted file mode 100644
index fe07f7ebe9..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram.ld
+++ /dev/null
@@ -1,277 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    itcm_memory (rx)  : ORIGIN = 0x22028000, LENGTH = 16K
-    dtcm_memory (rx)  : ORIGIN = 0x2202c000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22020000, LENGTH = 32K
-    ram_wifi    (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
- 
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld
deleted file mode 100644
index 23ff22baef..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl606p_ram_phyrf.ld
+++ /dev/null
@@ -1,288 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory       (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    ram_wifi          (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-    ram_memory        (!rx) : ORIGIN = 0x22020000, LENGTH = 28K
-    itcm_memory       (rx)  : ORIGIN = 0x22027000, LENGTH = 2K
-    dtcm_memory       (rx)  : ORIGIN = 0x22027800, LENGTH = 2K
-    test_ocram        (!rx) : ORIGIN = 0x22028000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-
-    /* keep my variable even if not referenced */
-    /* .testmem_at_ocram (NOLOAD) : 
-    {
-        PROVIDE( __testmem_at_ocram_start_addr = ADDR(.testmem_at_ocram) );
-        PROVIDE( __testmem_at_wram_start_addr = ADDR(.testmem_at_ocram) + SIZEOF(.testmem_at_ocram) );
-        KEEP(*(.testmem_at_ocram))
-    } > ram_test */
-
-    /* __testmem_at_ocram_start_addr = ORIGIN(ram_test);
-    __testmem_at_wram_start_addr = ORIGIN(wifi_ram); */
-
-    __testmem_at_ocram_start_addr = ORIGIN(test_ocram);
-    __testmem_at_wram_start_addr = ORIGIN(ram_wifi);
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld
deleted file mode 100644
index abb4c12666..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash.ld
+++ /dev/null
@@ -1,374 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-BOOT2_PT_ADDR = 0x22057C00;
-BOOT2_FLASHCFG_ADDR = 0x22057c18;
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M
-    xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K 
-    ram_memory  (!rx) : ORIGIN = 0x22024000, LENGTH = 48K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 96K 
-    ram_psram  (!rx)  : ORIGIN = 0x50000000, LENGTH = 1M
-    bugkill   (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text.boot :
-    {
-        . = ALIGN(4);
-    
-        *(.text.startup)
-
-        . = ALIGN(4);
-    } > flash
-
-    .bugkiller_command :
-    {
-        PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );
-        PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );
-        KEEP (*(.static_bugkiller_command))
-    } > bugkill
-
-    .bugkiller :
-    {
-        KEEP (*(.bugkiller_code))
-        KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))
-    } > bugkill
-
-    .psram_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __psram_ram_data_start__ = .;
- 
-        *(.psram_data.*)
-        *liblwip.a:*.o(.text*)
-        *libwifi.a:*.o(.text*)
-        *libwifi_manager.a:*.o(.text*)
-        *libfreertos_e907.a:*.o(.text*)
-        *libnetutils.a:*.o(.text*)
-        *libutils.a:*.o(.text*)
-        *libstartup_bl808.a:debug.o(.text*)
-
-        *liblwip.a:*.o(.rodata*)
-        *libwifi.a:*.o(.rodata*)
-        *libwifi_manager.a:*.o(.rodata*)
-        *libfreertos_e907.a:*.o(.rodata*)
-        *libnetutils.a:*.o(.rodata*)
-        *libutils.a:*.o(.rodata*)
-        *libstartup_bl808.a:debug.o(.rodata*)
-        
-        . = ALIGN(4);
-        __psram_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-    
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-
-        /* section information for finsh shell */
-        . = ALIGN(4);
-        __fsymtab_start = .;
-        KEEP(*(FSymTab))
-        __fsymtab_end = .;
-        . = ALIGN(4);
-        __vsymtab_start = .;
-        KEEP(*(VSymTab))
-        __vsymtab_end = .;
-        . = ALIGN(4);
-
-        /* section information for modules */
-        . = ALIGN(4);
-        __rtmsymtab_start = .;
-        KEEP(*(RTMSymTab))
-        __rtmsymtab_end = .;
-
-        /* section information for initialization */
-        . = ALIGN(4);
-        __rt_init_start = .;
-        KEEP(*(SORT(.rti_fn*)))
-        __rt_init_end = .;
-
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.tcm_const.*)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_code.*)
-        *(.sclock_rlt_const)
-        *(.sclock_rlt_const.*)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > ram_psram AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-	PROVIDE ( _sp_base = . );
-        . = ALIGN(64);
-        __stack_protect_start = .;
-        . = . + 256;
-        __stack_protect_end = .;
-        . = . + StackSize;
-        . = ALIGN(64);
-	PROVIDE( _sp_main = . );
-    } > ram_psram
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_psram AT > flash
-
-    .xrambss  (NOLOAD) :
-    {
-        __xram_load_addr = .;
-        
-        . = ALIGN(4);
-        __xram_data_start__ = .;
-
-        *(.static_xram_region)
-
-        __xram_data_end__ = .;
-        . = ALIGN(4);
-    } > xram_memory
-
-    .ocram_bss_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __ocram_bss_start__ = .;
-
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __ocram_bss_end__ = .;
-    } > ram_memory
-
-    .boot2 (NOLOAD) :
-    {
-        PROVIDE ( __boot2_pt_addr_start = . );
-        *(.bss.boot2_partition_table)
-        PROVIDE ( __boot2_pt_addr_end   = . );
-
-        PROVIDE ( __boot2_flashCfg_start = . );
-        *(.bss.boot2_flashCfg)
-        PROVIDE ( __boot2_flashCfg_end = . );
-
-    } > ram_psram
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_psram 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_psram 
-
-    __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = ADDR(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_psram) + LENGTH(ram_psram);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    /*BOOT2 sections*/
-    PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
-    PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-    PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );
-    PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld
deleted file mode 100644
index 1a9a7a5105..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_no_wifi.ld
+++ /dev/null
@@ -1,357 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-BOOT2_PT_ADDR = 0x22057C00;
-BOOT2_FLASHCFG_ADDR = 0x22057c18;
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0x58000000, LENGTH = 4M
-    xram_memory (!rx) : ORIGIN = 0x22020000, LENGTH = 16K 
-    ram_memory  (!rx) : ORIGIN = 0x22024000, LENGTH = 208K
-    ram_wifi    (!rx) : ORIGIN = 0x22058000, LENGTH = 0K
-    ram_psram  (!rx)  : ORIGIN = 0x50000000, LENGTH = 1M
-    bugkill   (rxai!w) : ORIGIN = 0xD0000000, LENGTH = 16M
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text.boot :
-    {
-        . = ALIGN(4);
-    
-        *(.text.startup)
-
-        . = ALIGN(4);
-    } > flash
-
-    .bugkiller_command :
-    {
-        PROVIDE( __bugkiller_command_start = ADDR(.bugkiller_command) );
-        PROVIDE( __bugkiller_command_end = ADDR(.bugkiller_command) + SIZEOF(.bugkiller_command) );
-        KEEP (*(.static_bugkiller_command))
-    } > bugkill
-
-    .bugkiller :
-    {
-        KEEP (*(.bugkiller_code))
-        KEEP (*bugkiller*.o(.rodata* .text* .data* .sdata* .sbss*))
-    } > bugkill
-
-    .psram_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __psram_ram_data_start__ = .;
- 
-        *(.psram_data.*)
-        *liblwip.a:*.o(.text*)
-        *libwifi.a:*.o(.text*)
-        *libwifi_manager.a:*.o(.text*)
-        *libfreertos_e907.a:*.o(.text*)
-        *libnetutils.a:*.o(.text*)
-        *libutils.a:*.o(.text*)
-        *libstartup_bl808.a:debug.o(.text*)
-
-        *liblwip.a:*.o(.rodata*)
-        *libwifi.a:*.o(.rodata*)
-        *libwifi_manager.a:*.o(.rodata*)
-        *libfreertos_e907.a:*.o(.rodata*)
-        *libnetutils.a:*.o(.rodata*)
-        *libutils.a:*.o(.rodata*)
-        *libstartup_bl808.a:debug.o(.rodata*)
-        
-        . = ALIGN(4);
-        __psram_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .text :
-    {
-        . = ALIGN(4);
-    
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.tcm_const.*)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_code.*)
-        *(.sclock_rlt_const)
-        *(.sclock_rlt_const.*)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > ram_memory AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .xrambss  (NOLOAD) :
-    {
-        __xram_load_addr = .;
-        
-        . = ALIGN(4);
-        __xram_data_start__ = .;
-
-        *(.static_xram_region)
-
-        __xram_data_end__ = .;
-        . = ALIGN(4);
-    } > xram_memory
-
-    .ocram_bss_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __ocram_bss_start__ = .;
-
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __ocram_bss_end__ = .;
-    } > ram_memory
-
-    .boot2 (NOLOAD) :
-    {
-        PROVIDE ( __boot2_pt_addr_start = . );
-        *(.bss.boot2_partition_table)
-        PROVIDE ( __boot2_pt_addr_end   = . );
-
-        PROVIDE ( __boot2_flashCfg_start = . );
-        *(.bss.boot2_flashCfg)
-        PROVIDE ( __boot2_flashCfg_end = . );
-
-    } > ram_memory
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_memory
-
-    .psram_bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.custom_psram_bss*)
-        . = ALIGN(4);
-    } > ram_psram
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .stack_dummy (NOLOAD):
-    {
-	PROVIDE ( _sp_base = . );
-        . = ALIGN(64);
-        __stack_protect_start = .;
-        . = . + 256;
-        __stack_protect_end = .;
-        . = . + StackSize;
-        . = ALIGN(64);
-	PROVIDE( _sp_main = . );
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_memory
-
-    __StackTop = ADDR(.stack_dummy) + SIZEOF(.stack_dummy);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = ADDR(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __psram_ram_load_addr = LOADADDR(.psram_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    /*BOOT2 sections*/
-    PROVIDE ( __boot2_pt_addr_src = BOOT2_PT_ADDR );
-    PROVIDE ( __boot2_flashCfg_src = BOOT2_FLASHCFG_ADDR );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_psram) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_psram) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-    PROVIDE( _ld_ram_size3 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr3 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size4 = LENGTH(xram_memory) );
-    PROVIDE( _ld_ram_addr4 = ORIGIN(xram_memory) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld
deleted file mode 100644
index d2001b4ffd..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_flash_rom.ld
+++ /dev/null
@@ -1,252 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    flash    (rxai!w) : ORIGIN = 0xD8000000, LENGTH = 4M
-    itcm_memory (rx)  : ORIGIN = 0xC2024000, LENGTH = 48K
-    dtcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22010000, LENGTH = 64K
-    ram_wifi    (!rx) : ORIGIN = 0x22030000, LENGTH = 160K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-    
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-
-        . = ALIGN(4);
-    } > flash
-
-    .rodata :
-    {
-        . = ALIGN(4);
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-    } > flash
-
-    .itcm_region :
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-
-        *(.tcm_code)
-        *(.tcm_code.*)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory AT > flash
-
-    .dtcm_region : 
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory AT > flash
-
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(4);
-        . = . + StackSize;
-        . = ALIGN(4);
-    } > dtcm_memory
-
-    .system_ram_data_region : 
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
- 
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory AT > flash
-
-    .data : 
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory AT > flash
-    
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(.noinit_data*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory 
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-        _heap_end = .;
-    } > ram_memory 
-
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - _heap_start;
-
-    PROVIDE( __itcm_load_addr = LOADADDR(.itcm_region));
-    PROVIDE( __dtcm_load_addr = LOADADDR(.dtcm_region));
-    PROVIDE( __system_ram_load_addr = LOADADDR(.system_ram_data_region));
-    PROVIDE( __ram_load_addr = LOADADDR(.data));
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-    
-    PROVIDE( _ld_ram_size0 = LENGTH(flash) );
-    PROVIDE( _ld_ram_addr0 = ORIGIN(flash) );
-    PROVIDE( _ld_ram_size1 = LENGTH(ram_memory) );
-    PROVIDE( _ld_ram_addr1 = ORIGIN(ram_memory) );
-    PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-    PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
- 
-    /* blog */
-    PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-    PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-    PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-    PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-    PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-    PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-    PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-    PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld
deleted file mode 100644
index fe07f7ebe9..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram.ld
+++ /dev/null
@@ -1,277 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    itcm_memory (rx)  : ORIGIN = 0x22028000, LENGTH = 16K
-    dtcm_memory (rx)  : ORIGIN = 0x2202c000, LENGTH = 16K
-    ram_memory  (!rx) : ORIGIN = 0x22020000, LENGTH = 32K
-    ram_wifi    (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
- 
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld
deleted file mode 100644
index 23ff22baef..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/ld/bl808_ram_phyrf.ld
+++ /dev/null
@@ -1,288 +0,0 @@
-/****************************************************************************************
-* @file map.txt
-*
-* @brief This file is the map file (gnuarm or armgcc).
-*
-* Copyright (C) BouffaloLab 2018
-*
-****************************************************************************************
-*/
-
-/* configure the CPU type */
-OUTPUT_ARCH( "riscv" )
-/* link with the standard c library */
-INPUT(-lc)
-/* link with the standard GCC library */
-INPUT(-lgcc)
-/* configure the entry point */
-ENTRY(risc_e906_start)
-
-StackSize = 0x0400; /*  1KB */
-
-MEMORY
-{
-    code_memory       (rx)  : ORIGIN = 0x22030000, LENGTH = 128K
-    ram_wifi          (!rx) : ORIGIN = 0x22050000, LENGTH = 32K
-    ram_memory        (!rx) : ORIGIN = 0x22020000, LENGTH = 28K
-    itcm_memory       (rx)  : ORIGIN = 0x22027000, LENGTH = 2K
-    dtcm_memory       (rx)  : ORIGIN = 0x22027800, LENGTH = 2K
-    test_ocram        (!rx) : ORIGIN = 0x22028000, LENGTH = 32K
-}
-
-SECTIONS
-{
-    PROVIDE(__metal_chicken_bit = 0);
-    
-    .text :
-    {
-        . = ALIGN(4);
-        __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(risc_e906_start)))
-        
-        *(.text)
-        *(.text.*)
-        
-        *(.rodata)
-        *(.rodata.*)
-    
-        *(.srodata)
-        *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-
-        /* static cli cmds */
-        . = ALIGN(4);
-        _bl_static_cli_cmds_start = .;
-        KEEP(*(.static_cli_cmds))
-        *(.static_cli_cmds)
-        _bl_static_cli_cmds_end = .;    
-        
-        /* static blog code1 */
-        . = ALIGN(4);
-        _bl_static_blogcomponent_code_start = .;
-        KEEP(SORT(*)(.static_blogcomponent_code*))
-        *(.static_blogcomponent_code*)
-        _bl_static_blogcomponent_code_end = .;
-    
-        /* static blog code2 */
-        . = ALIGN(4);
-        _bl_static_blogfile_code_start = .;
-        KEEP(SORT(*)(.static_blogfile_code*))
-        *(.static_blogfile_code*)
-        _bl_static_blogfile_code_end = .;
-    
-        /* static blog code3 */
-        . = ALIGN(4);
-        _bl_static_blogpri_code_start = .;
-        KEEP(SORT(*)(.static_blogpri_code*))
-        *(.static_blogpri_code*)
-        _bl_static_blogpri_code_end = .;
-    
-        /* static fw attribute entry */
-        . = ALIGN(4);
-        _bl_static_fw_cfg_entry_start = .;
-        KEEP(*(.wifi.cfg.entry))
-        _bl_static_fw_cfg_entry_end = .;
-        . = ALIGN(4);
-
-        __text_code_end__ = .;
-    } > code_memory
-
-    .wifibss  (NOLOAD) :
-    {
-        PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
-        PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
-        *ipc_shared.o(COMMON)
-        *sdu_shared.o(COMMON)
-        *hal_desc.o(COMMON)
-        *txl_buffer_shared.o(COMMON)
-        *txl_frame_shared.o(COMMON)
-        *scan_shared.o(COMMON)
-        *scanu_shared.o(COMMON)
-        *mfp_bip.o(COMMON)
-        *me_mic.o(COMMON)
-        *bl_sta_mgmt_others.o(COMMON)
-        *bl_pmk_mgmt.o(COMMON)
-        *bl_pmk_mgmt_internal.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(COMMON)
-        *libwifi_drv.a:bl_utils.o(.bss*)
-        *(.wifi_ram*)
-        . = ALIGN(16);
-    } > ram_wifi
-
-    PROVIDE( _heap_wifi_start = . );
-    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
-
-    /*SYMOBOL used in code*/
-    PROVIDE( _ld_bl_static_cli_cmds_start = _bl_static_cli_cmds_start );
-    PROVIDE( _ld_bl_static_cli_cmds_end   = _bl_static_cli_cmds_end );
-
-    . = ALIGN(4);
-    __itcm_load_addr = .;
-    
-    .itcm_region : AT (__itcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_code_start__ = .;
-        
-        . = ALIGN(4);
-        __tcm_code_end__ = .;
-    } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
-    .dtcm_region : AT (__dtcm_load_addr)
-    {
-        . = ALIGN(4);
-        __tcm_data_start__ = .;
-        
-        *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
-        . = ALIGN(4);
-        __tcm_data_end__ = .;
-    } > dtcm_memory
-    
-    /*************************************************************************/
-    /* .stack_dummy section doesn't contains any symbols. It is only
-     * used for linker to calculate size of stack sections, and assign
-     * values to stack symbols later */
-    .stack_dummy (NOLOAD):
-    {
-        . = ALIGN(0x4);
-        . = . + StackSize;
-        . = ALIGN(0x4);
-    } > dtcm_memory
-    
-    /* Set stack top to end of RAM, and stack limit move down by
-     * size of stack_dummy section */
-    __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
-    PROVIDE( __freertos_irq_stack_top = __StackTop);
-    __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
-    /* Check if data + heap + stack exceeds RAM limit */
-    ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
-    /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
-    /* Data section */
-    RAM_DATA : AT (__ram_load_addr)
-    {
-        . = ALIGN(4);
-        __ram_data_start__ = .;
-        
-        PROVIDE( __global_pointer$ = . + 0x800 );
-        
-        *(.data)
-        *(.data.*)
-        *(.sdata)
-        *(.sdata.*)
-        *(.sdata2)
-        *(.sdata2.*)
-        
-        _bt_gatt_service_static_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_gatt_service_static.static.*")))
-        _bt_gatt_service_static_list_end = .;
-        _bt_l2cap_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_fixed_chan.static.*")))
-        _bt_l2cap_fixed_chan_list_end = .;
-        _bt_l2cap_br_fixed_chan_list_start = .;
-        KEEP(*(SORT_BY_NAME("._bt_l2cap_br_fixed_chan.static.*")))
-        _bt_l2cap_br_fixed_chan_list_end = .;
-
-        . = ALIGN(4);
-        __ram_data_end__ = .;
-    } > ram_memory
-    
-    .noinit_data (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __noinit_data_start__ = .;
-        
-        *(.noinit_data*)
-        
-        . = ALIGN(4);
-        __noinit_data_end__ = .;
-    } > ram_memory
-    
-    .bss (NOLOAD) :
-    {
-        . = ALIGN(4);
-        __bss_start__ = .;
-        
-        *(.bss*)
-        *(.sbss*)
-        *(COMMON)
- 
-        . = ALIGN(4);
-        __bss_end__ = .;
-    } > ram_memory
-
-    .heap (NOLOAD):
-    {
-        . = ALIGN(4);
-        __HeapBase = .;
-        _heap_start = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
-        KEEP(*(.heap*))
-        
-        . = ALIGN(4);
-        __HeapLimit = .;
-    } > ram_memory
-    __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    _heap_size = __HeapLimit - __HeapBase;
-
-    /* keep my variable even if not referenced */
-    /* .testmem_at_ocram (NOLOAD) : 
-    {
-        PROVIDE( __testmem_at_ocram_start_addr = ADDR(.testmem_at_ocram) );
-        PROVIDE( __testmem_at_wram_start_addr = ADDR(.testmem_at_ocram) + SIZEOF(.testmem_at_ocram) );
-        KEEP(*(.testmem_at_ocram))
-    } > ram_test */
-
-    /* __testmem_at_ocram_start_addr = ORIGIN(ram_test);
-    __testmem_at_wram_start_addr = ORIGIN(wifi_ram); */
-
-    __testmem_at_ocram_start_addr = ORIGIN(test_ocram);
-    __testmem_at_wram_start_addr = ORIGIN(ram_wifi);
-}
-
-PROVIDE( _ld_ram_size0 = LENGTH(ram_memory) );
-PROVIDE( _ld_ram_addr0 = ORIGIN(ram_memory) );
-PROVIDE( _ld_ram_size1 = 0);
-PROVIDE( _ld_ram_addr1 = 0);
-PROVIDE( _ld_ram_size2 = LENGTH(ram_wifi) );
-PROVIDE( _ld_ram_addr2 = ORIGIN(ram_wifi) );
-
-/* blog */
-PROVIDE( _ld_bl_static_blogcomponent_code_start = _bl_static_blogcomponent_code_start );
-PROVIDE( _ld_bl_static_blogcomponent_code_end   = _bl_static_blogcomponent_code_end );
-PROVIDE( _ld_bl_static_blogfile_code_start = _bl_static_blogfile_code_start );
-PROVIDE( _ld_bl_static_blogfile_code_end   = _bl_static_blogfile_code_end );
-PROVIDE( _ld_bl_static_blogpri_code_start = _bl_static_blogpri_code_start );
-PROVIDE( _ld_bl_static_blogpri_code_end   = _bl_static_blogpri_code_end );
-
-
-PROVIDE( _ld_bl_static_cfg_entry_start = _bl_static_fw_cfg_entry_start );
-PROVIDE( _ld_bl_static_cfg_entry_end   = _bl_static_fw_cfg_entry_end );
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c
deleted file mode 100644
index 705babcd15..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/start_load.c
+++ /dev/null
@@ -1,109 +0,0 @@
-#include 
-#include 
-#define __STARTUP_CLEAR_BSS             1
-
-/*----------------------------------------------------------------------------
-  Linker generated Symbols
- *----------------------------------------------------------------------------*/
-extern uint32_t __itcm_load_addr;
-extern uint32_t __dtcm_load_addr;
-extern uint32_t __system_ram_load_addr;
-extern uint32_t __psram_ram_load_addr;
-extern uint32_t __ram_load_addr;
-
-extern uint32_t __text_code_start__;
-extern uint32_t __text_code_end__;
-extern uint32_t __tcm_code_start__;
-extern uint32_t __tcm_code_end__;
-extern uint32_t __tcm_data_start__;
-extern uint32_t __tcm_data_end__;
-extern uint32_t __system_ram_data_start__;
-extern uint32_t __system_ram_data_end__;
-extern uint32_t __psram_ram_data_start__;
-extern uint32_t __psram_ram_data_end__;
-extern uint32_t __ram_data_start__;
-extern uint32_t __ram_data_end__;
-extern uint32_t __wifi_bss_start;
-extern uint32_t __wifi_bss_end;
-extern uint32_t __bss_start__;
-extern uint32_t __bss_end__;
-extern uint32_t __ocram_bss_start__;
-extern uint32_t __ocram_bss_end__;
-extern uint32_t __noinit_data_start__;
-extern uint32_t __noinit_data_end__;
-
-extern uint32_t __StackTop;
-extern uint32_t __StackLimit;
-extern uint32_t __HeapBase;
-extern uint32_t __HeapLimit;
-
-//extern uint32_t __copy_table_start__;
-//extern uint32_t __copy_table_end__;
-//extern uint32_t __zero_table_start__;
-//extern uint32_t __zero_table_end__;
-
-
-void start_load(void) {
-    uint32_t *pSrc, *pDest;
-    /*boot2 dcache is enable need disable*/
-    csi_dcache_disable();
-
-    /* Copy ITCM code */
-    pSrc  = &__itcm_load_addr;
-    pDest = &__tcm_code_start__;
-    for ( ; pDest < &__tcm_code_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-
-    /* Copy DTCM code */
-    pSrc  = &__dtcm_load_addr;
-    pDest = &__tcm_data_start__;
-    for( ; pDest < &__tcm_data_end__; ){
-        *pDest++ = *pSrc++;
-    }
-
-    /* BF Add system RAM data copy */
-    pSrc  = &__system_ram_load_addr;
-    pDest = &__system_ram_data_start__;
-    for ( ; pDest < &__system_ram_data_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-
-    /* BF Add OCARAM data copy */
-    pSrc  = &__ram_load_addr;
-    pDest = &__ram_data_start__;
-    for ( ; pDest < &__ram_data_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-
-#ifdef __STARTUP_CLEAR_BSS
-    /*
-     *  The BSS section is specified by following symbols
-     *    __bss_start__: start of the BSS section.
-     *    __bss_end__: end of the BSS section.
-     *
-     *  Both addresses must be aligned to 4 bytes boundary.
-     */
-    pDest = &__bss_start__;
-    for ( ; pDest < &__bss_end__ ; ) {
-        *pDest++ = 0ul;
-    }
-
-    pDest = &__wifi_bss_start;
-    for ( ; pDest < &__wifi_bss_end ; ) {
-        *pDest++ = 0ul;
-    }
-
-    pDest = &__ocram_bss_start__;
-    for ( ; pDest < &__ocram_bss_end__ ; ) {
-        *pDest++ = 0ul;
-    }
-#endif
-
-    /* BF Add PSRAM RAM data copy */
-    pSrc  = &__psram_ram_load_addr;
-    pDest = &__psram_ram_data_start__;
-    for ( ; pDest < &__psram_ram_data_end__ ; ) {
-        *pDest++ = *pSrc++;
-    }
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S
deleted file mode 100644
index cb74576c0e..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/startup.S
+++ /dev/null
@@ -1,84 +0,0 @@
-/*
- * Copyright (C) 2016-2020 Bouffalo Lab
- */
-
-_start:
-    .section      .text.startup
-    .align  2
-    .globl  risc_e906_start
-    .type   risc_e906_start, %function
-risc_e906_start:
-.option push
-.option norelax
-    la      gp, __global_pointer$
-.option pop
-    la      a0, IRQ_Handler
-    ori     a0, a0, 3
-    csrw    mtvec, a0 
-#1:
-#    j       1b
-
-    la      a0, __Vectors
-    csrw    mtvt, a0
-
-    .weak __StackTop
-    la      sp, __StackTop
-    csrw    mscratch, sp
-
-#ifndef RUN_IN_RAM
-	/* Load boot2 partition address */
-	la a0, __boot2_pt_addr_src
-	la a1, __boot2_pt_addr_start
-	la a2, __boot2_pt_addr_end
-	bgeu a1, a2, 2f
-1:
-	lw t0, (a0)
-	sw t0, (a1)
-	addi a0, a0, 4
-	addi a1, a1, 4
-	bltu a1, a2, 1b
-2:
-
-
-	/* Load boot2 flashCfg address */
-	la a0, hal_boot2_get_flash_addr
-	jalr a0
-	la a1, __boot2_flashCfg_start
-	la a2, __boot2_flashCfg_end
-	bgeu a1, a2, 2f
-1:
-	lw t0, (a0)
-	sw t0, (a1)
-	addi a0, a0, 4
-	addi a1, a1, 4
-	bltu a1, a2, 1b
-2:
-#endif
-
-    /* Load data section removed */
-    
-    /* start load code to itcm like. */
-    la a0,  start_load
-    jalr    a0
- 
-    /* Clear bss section removed */
-
-#ifndef __NO_SYSTEM_INIT
-    la a0,  system_init_bl606p
-    jalr    a0
-#endif
-
-#ifndef __NO_BOARD_INIT
-    la a0,  board_init
-    jalr    a0
-#endif
-   
-	//la a0,  bfl_main
-	la a0,  entry
-    jalr    a0
-
-    .size   risc_e906_start, . - risc_e906_start
-
-__exit:
-    j      __exit
-
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S
deleted file mode 100644
index 94f538fdae..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/boot/gcc/vectors.S
+++ /dev/null
@@ -1,327 +0,0 @@
-/*
- * Copyright (C) 2017-2019 Alibaba Group Holding Limited
- */
- /******************************************************************************
- * @file     vectors.S
- * @brief    define default vector handlers. Should use with
- *           GCC for CSKY Embedded Processors
- * @version  V1.0
- * @date     28. Nove 2017
- ******************************************************************************/
-
-/* Enable interrupts when returning from the handler */
-#define MSTATUS_PRV1 0x1880
-
-.section .bss
-    .align  2
-    .globl  g_trapstackalloc
-    .global g_trapstackbase
-    .global g_top_trapstack
-g_trapstackalloc:
-g_trapstackbase:
-    .space 768
-g_top_trapstack:
-
-    .align 2
-    .globl g_trap_sp
-    .type  g_trap_sp, object
-g_trap_sp:
-    .long 0
-    .size g_trap_sp, .-g_trap_sp
-
-irq_nested_level:
-.long 0
-irq_mstatus_fs_flag:
-.long 0
-
-.text
-
-    .align  2
-    .global Default_IRQHandler
-    .weak   Default_IRQHandler
-    .type   Default_IRQHandler, %function
-Default_IRQHandler:
-    ipush
-
-#if 0
-    csrr    t1, mstatus
-    srli    t1, t1, 13
-    andi    t1, t1, 0x3
-    la      t3, irq_mstatus_fs_flag
-    sw      t1, (t3)
-    li      t0, 0x3
-    bne     t1, t0,  .F_RegNotSave1
-
-
-    addi    sp,  sp, -80
-    fsw     ft0, 0(sp)
-    fsw     ft1, 4(sp)
-    fsw     ft2, 8(sp)
-    fsw     ft3, 12(sp)
-    fsw     ft4, 16(sp)
-    fsw     ft5, 20(sp)
-    fsw     ft6, 24(sp)
-    fsw     ft7, 28(sp)
-    fsw     fa0, 32(sp)
-    fsw     fa1, 36(sp)
-    fsw     fa2, 40(sp)
-    fsw     fa3, 44(sp)
-    fsw     fa4, 48(sp)
-    fsw     fa5, 52(sp)
-    fsw     fa6, 56(sp)
-    fsw     fa7, 60(sp)
-    fsw     ft8, 64(sp)
-    fsw     ft9, 68(sp)
-    fsw     ft10,72(sp)
-    fsw     ft11,76(sp)
-.F_RegNotSave1:
-#endif
-    
-    /* disable irq */
-    csrc    mstatus, 8 
-
-    /* Set IRQ stack pointer */
-    la      t0, __freertos_irq_stack_top
-    addi    t1, sp, 0
-    addi    sp, t0, -8
-    /* save t1 to stack */
-    sw      t1, 4(sp)
-
-    csrr    t1, mcause
-    andi    t1, t1, 0x3FF
-    slli    t1, t1, 2
-    la      t0, g_irqvector
-    add     t0, t0, t1
-    lw      t2, (t0)
-    jalr    t2
- 
-    la      t0, __freertos_irq_stack_top
-    lw      sp, t0, -4
-
-    /* enable irq */
-    csrs    mstatus, 8 
-
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
-
-#if 0
-    la      t0, irq_mstatus_fs_flag
-    lw      t1, (t0)
-    li      t0, 0x3
-    bne     t1, t0,  .F_RegNotLoad
-
-    flw     ft0, 0(sp)
-    flw     ft1, 4(sp)
-    flw     ft2, 8(sp)
-    flw     ft3, 12(sp)
-    flw     ft4, 16(sp)
-    flw     ft5, 20(sp)
-    flw     ft6, 24(sp)
-    flw     ft7, 28(sp)
-    flw     fa0, 32(sp)
-    flw     fa1, 36(sp)
-    flw     fa2, 40(sp)
-    flw     fa3, 44(sp)
-    flw     fa4, 48(sp)
-    flw     fa5, 52(sp)
-    flw     fa6, 56(sp)
-    flw     fa7, 60(sp)
-    flw     ft8, 64(sp)
-    flw     ft9, 68(sp)
-    flw     ft10,72(sp)
-    flw     ft11,76(sp)
-    addi    sp, sp, 80
-
-.F_RegNotLoad:
-#endif
-
-    ipop
-
-
-/******************************************************************************
- * Functions:
- *     void trap(void);
- * default exception handler
- ******************************************************************************/
-    .align  2
-    .global trap
-    .type   trap, %function
-trap:
-    /* Check for interrupt */
-    addi    sp, sp, -4
-    sw      t0, 0x0(sp)
-    csrr    t0, mcause
-
-    blt     t0, x0, .Lirq
-
-    addi    sp, sp, 4
-
-    la      t0, g_trap_sp
-    addi    t0, t0, -132
-    sw      x1, 0(t0)
-    sw      x2, 4(t0)
-    sw      x3, 8(t0)
-    sw      x4, 12(t0)
-    sw      x6, 20(t0)
-    sw      x7, 24(t0)
-    sw      x8, 28(t0)
-    sw      x9, 32(t0)
-    sw      x10, 36(t0)
-    sw      x11, 40(t0)
-    sw      x12, 44(t0)
-    sw      x13, 48(t0)
-    sw      x14, 52(t0)
-    sw      x15, 56(t0)
-    sw      x16, 60(t0)
-    sw      x17, 64(t0)
-    sw      x18, 68(t0)
-    sw      x19, 72(t0)
-    sw      x20, 76(t0)
-    sw      x21, 80(t0)
-    sw      x22, 84(t0)
-    sw      x23, 88(t0)
-    sw      x24, 92(t0)
-    sw      x25, 96(t0)
-    sw      x26, 100(t0)
-    sw      x27, 104(t0)
-    sw      x28, 108(t0)
-    sw      x29, 112(t0)
-    sw      x30, 116(t0)
-    sw      x31, 120(t0)
-    csrr    a0, mepc
-    sw      a0, 124(t0)
-    csrr    a0, mstatus
-    sw      a0, 128(t0)
-
-    mv      a0, t0
-    lw      t0, -4(sp)
-    mv      sp, a0
-    sw      t0, 16(sp)
-
-    jal     trap_c
-
-
-.Lirq:
-    lw      t0, 0x0(sp)
-    addi    sp, sp, 4
-    j       Default_IRQHandler
-
-    .align  6
-    .weak   Default_Handler
-    .global Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    /* Check for nmi */
-    addi    sp, sp, -8
-    sw      t0, 0x0(sp)
-    sw      t1, 0x4(sp)
-    csrr    t0, mcause
-    andi    t0, t0, 0x3FF
-    li      t1, 24
-    beq     t0, t1, .NMI_Handler
-    lw      t0, 0x0(sp)
-    lw      t1, 0x4(sp)
-    addi    sp, sp, 8
-    j      trap
-
-.NMI_Handler:
-    lw      t0, 0x0(sp)
-    lw      t1, 0x4(sp)
-    addi    sp, sp, 8
-
-    addi    sp, sp, -64
-    sw      ra, 0(sp)
-    sw      t0, 4(sp)
-    sw      t1, 8(sp)
-    sw      t2, 12(sp)
-    sw      a0, 16(sp)
-    sw      a1, 20(sp)
-    sw      a2, 24(sp)
-    sw      a3, 28(sp)
-    sw      a4, 32(sp)
-    sw      a5, 36(sp)
-    sw      a6, 40(sp)
-    sw      a7, 44(sp)
-    sw      t3, 48(sp)
-    sw      t4, 52(sp)
-    sw      t5, 56(sp)
-    sw      t6, 60(sp)
-
-    addi    sp,  sp, -80
-    fsw     ft0, 0(sp)
-    fsw     ft1, 4(sp)
-    fsw     ft2, 8(sp)
-    fsw     ft3, 12(sp)
-    fsw     ft4, 16(sp)
-    fsw     ft5, 20(sp)
-    fsw     ft6, 24(sp)
-    fsw     ft7, 28(sp)
-    fsw     fa0, 32(sp)
-    fsw     fa1, 36(sp)
-    fsw     fa2, 40(sp)
-    fsw     fa3, 44(sp)
-    fsw     fa4, 48(sp)
-    fsw     fa5, 52(sp)
-    fsw     fa6, 56(sp)
-    fsw     fa7, 60(sp)
-    fsw     ft8, 64(sp)
-    fsw     ft9, 68(sp)
-    fsw     ft10,72(sp)
-    fsw     ft11,76(sp)
-
-    la      t0, g_nmivector
-    lw      t0, (t0)
-    jalr    t0
-
-    flw     ft0, 0(sp)
-    flw     ft1, 4(sp)
-    flw     ft2, 8(sp)
-    flw     ft3, 12(sp)
-    flw     ft4, 16(sp)
-    flw     ft5, 20(sp)
-    flw     ft6, 24(sp)
-    flw     ft7, 28(sp)
-    flw     fa0, 32(sp)
-    flw     fa1, 36(sp)
-    flw     fa2, 40(sp)
-    flw     fa3, 44(sp)
-    flw     fa4, 48(sp)
-    flw     fa5, 52(sp)
-    flw     fa6, 56(sp)
-    flw     fa7, 60(sp)
-    flw     ft8, 64(sp)
-    flw     ft9, 68(sp)
-    flw     ft10,72(sp)
-    flw     ft11,76(sp)
-
-    addi    sp, sp, 80
-
-    lw      ra, 0(sp)
-    lw      t0, 4(sp)
-    lw      t1, 8(sp)
-    lw      t2, 12(sp)
-    lw      a0, 16(sp)
-    lw      a1, 20(sp)
-    lw      a2, 24(sp)
-    lw      a3, 28(sp)
-    lw      a4, 32(sp)
-    lw      a5, 36(sp)
-    lw      a6, 40(sp)
-    lw      a7, 44(sp)
-    lw      t3, 48(sp)
-    lw      t4, 52(sp)
-    lw      t5, 56(sp)
-    lw      t6, 60(sp)
-    addi    sp, sp, 64
-    mret
-
-    .size   Default_Handler, . - Default_Handler
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro  def_irq_handler handler_name
-    .weak   \handler_name
-    .globl  \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c
deleted file mode 100644
index b8e720f65e..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/debug.c
+++ /dev/null
@@ -1,914 +0,0 @@
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#define DEFAULT_UART_ID 0
-
-uint32_t debug_uart_id = DEFAULT_UART_ID;
-
-//#define CHAR_BIT  8
-//FIXME no ugly declare
-extern int bl_uart_data_send(uint8_t id, uint8_t data);
-
-volatile bool sys_log_all_enable = true;
-
-enum flag {
-    FL_ZERO     = 0x01, /* Zero modifier */
-    FL_MINUS    = 0x02, /* Minus modifier */
-    FL_PLUS     = 0x04, /* Plus modifier */
-    FL_TICK     = 0x08, /* ' modifier */
-    FL_SPACE    = 0x10, /* Space modifier */
-    FL_HASH     = 0x20, /* # modifier */
-    FL_SIGNED   = 0x40, /* Number is signed */
-    FL_UPPER    = 0x80  /* Upper case digits */
-};
-
-/* These may have to be adjusted on certain implementations */
-enum ranks {
-    rank_char   = -2,
-    rank_short  = -1,
-    rank_int    =  0,
-    rank_long   =  1,
-    rank_longlong   =  2
-};
-
-#define MIN_RANK    rank_char
-#define MAX_RANK    rank_longlong
-
-#define INTMAX_RANK rank_longlong
-#define SIZE_T_RANK rank_long
-#define PTRDIFF_T_RANK  rank_long
-
-#define EMIT(x) { if (o < n) { *q++ = (x); } o++; }
-
-void debug_uart_id_set(uint8_t id)
-{
-    debug_uart_id = id;
-}
-
-static size_t
-format_int(char *q, size_t n, uintmax_t val, unsigned int flags,
-       int base, int width, int prec)
-{
-    char *qq;
-    size_t o = 0, oo;
-    static const char lcdigits[] = "0123456789abcdef";
-    static const char ucdigits[] = "0123456789ABCDEF";
-    const char *digits;
-    uintmax_t tmpval;
-    int minus = 0;
-    int ndigits = 0, nchars;
-    int tickskip, b4tick;
-
-    /* Select type of digits */
-    digits = (flags & FL_UPPER) ? ucdigits : lcdigits;
-
-    /* If signed, separate out the minus */
-    if (flags & FL_SIGNED && (intmax_t) val < 0) {
-        minus = 1;
-        val = (uintmax_t) (-(intmax_t) val);
-    }
-
-    /* Count the number of digits needed.  This returns zero for 0. */
-    tmpval = val;
-    while (tmpval) {
-        tmpval /= base;
-        ndigits++;
-    }
-
-    /* Adjust ndigits for size of output */
-
-    if (flags & FL_HASH && base == 8) {
-        if (prec < ndigits + 1)
-            prec = ndigits + 1;
-    }
-
-    if (ndigits < prec) {
-        ndigits = prec; /* Mandatory number padding */
-    } else if (val == 0) {
-        ndigits = 1;    /* Zero still requires space */
-    }
-
-    /* For ', figure out what the skip should be */
-    if (flags & FL_TICK) {
-        tickskip = (base == 16) ? 4 : 3;
-    } else {
-        tickskip = ndigits; /* No tick marks */
-    }
-
-    /* Tick marks aren't digits, but generated by the number converter */
-    ndigits += (ndigits - 1) / tickskip;
-
-    /* Now compute the number of nondigits */
-    nchars = ndigits;
-
-    if (minus || (flags & (FL_PLUS | FL_SPACE)))
-        nchars++;   /* Need space for sign */
-    if ((flags & FL_HASH) && base == 16) {
-        nchars += 2;    /* Add 0x for hex */
-    }
-
-    /* Emit early space padding */
-    if (!(flags & (FL_MINUS | FL_ZERO)) && width > nchars) {
-        while (width > nchars) {
-            EMIT(' ');
-            width--;
-        }
-    }
-
-    /* Emit nondigits */
-    if (minus) {
-        EMIT('-');
-    } else if (flags & FL_PLUS) {
-        EMIT('+');
-    } else if (flags & FL_SPACE) {
-        EMIT(' ');
-    }
-
-    if ((flags & FL_HASH) && base == 16) {
-        EMIT('0');
-        EMIT((flags & FL_UPPER) ? 'X' : 'x');
-    }
-
-    /* Emit zero padding */
-    if ((flags & (FL_MINUS | FL_ZERO)) == FL_ZERO && width > ndigits) {
-        while (width > nchars) {
-            EMIT('0');
-            width--;
-        }
-    }
-
-    /* Generate the number.  This is done from right to left. */
-    q += ndigits;       /* Advance the pointer to end of number */
-    o += ndigits;
-    qq = q;
-    oo = o;         /* Temporary values */
-
-    b4tick = tickskip;
-    while (ndigits > 0) {
-        if (!b4tick--) {
-            qq--;
-            oo--;
-            ndigits--;
-            if (oo < n)
-                *qq = '_';
-            b4tick = tickskip - 1;
-        }
-        qq--;
-        oo--;
-        ndigits--;
-        if (oo < n)
-            *qq = digits[val % base];
-        val /= base;
-    }
-
-    /* Emit late space padding */
-    while ((flags & FL_MINUS) && width > nchars) {
-        EMIT(' ');
-        width--;
-    }
-
-    return o;
-}
-
-#define ZEROPAD     (1<<0)  /* Pad with zero */
-#define SIGN        (1<<1)  /* Unsigned/signed long */
-#define PLUS        (1<<2)  /* Show plus */
-#define SPACE       (1<<3)  /* Spacer */
-#define LEFT        (1<<4)  /* Left justified */
-#define HEX_PREP    (1<<5)  /* 0x */
-#define UPPERCASE   (1<<6)  /* 'ABCDEF' */
-
-#include 
-#define CVTBUFSIZE 80
-
-static char *cvt(double arg, int ndigits, int *decpt, int *sign, char *buf, int eflag)
-{
-  int r2;
-  double fi, fj;
-  char *p, *p1;
-
-  if (ndigits < 0) ndigits = 0;
-  if (ndigits >= CVTBUFSIZE - 1) ndigits = CVTBUFSIZE - 2;
-  r2 = 0;
-  *sign = 0;
-  p = &buf[0];
-  if (arg < 0)
-  {
-    *sign = 1;
-    arg = -arg;
-  }
-  arg = modf(arg, &fi);
-  p1 = &buf[CVTBUFSIZE];
-
-  if (fi != 0)
-  {
-    p1 = &buf[CVTBUFSIZE];
-    while (fi != 0)
-    {
-      fj = modf(fi / 10, &fi);
-      *--p1 = (int)((fj + 0.03) * 10) + '0';
-      r2++;
-    }
-    while (p1 < &buf[CVTBUFSIZE]) *p++ = *p1++;
-  }
-  else if (arg > 0)
-  {
-    while ((fj = arg * 10) < 1)
-    {
-      arg = fj;
-      r2--;
-    }
-  }
-  p1 = &buf[ndigits];
-  if (eflag == 0) p1 += r2;
-  *decpt = r2;
-  if (p1 < &buf[0])
-  {
-    buf[0] = '\0';
-    return buf;
-  }
-  while (p <= p1 && p < &buf[CVTBUFSIZE])
-  {
-    arg *= 10;
-    arg = modf(arg, &fj);
-    *p++ = (int) fj + '0';
-  }
-  if (p1 >= &buf[CVTBUFSIZE])
-  {
-    buf[CVTBUFSIZE - 1] = '\0';
-    return buf;
-  }
-  p = p1;
-  *p1 += 5;
-  while (*p1 > '9')
-  {
-    *p1 = '0';
-    if (p1 > buf)
-      ++*--p1;
-    else
-    {
-      *p1 = '1';
-      (*decpt)++;
-      if (eflag == 0)
-      {
-        if (p > buf) *p = '0';
-        p++;
-      }
-    }
-  }
-  *p = '\0';
-  return buf;
-}
-
-char *ecvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)
-{
-  return cvt(arg, ndigits, decpt, sign, buf, 1);
-}
-
-char *fcvtbuf(double arg, int ndigits, int *decpt, int *sign, char *buf)
-{
-  return cvt(arg, ndigits, decpt, sign, buf, 0);
-}
-
-static void ee_bufcpy(char *d, char *s, int count);
-
-void ee_bufcpy(char *pd, char *ps, int count) {
-    char *pe=ps+count;
-    while (ps!=pe)
-        *pd++=*ps++;
-}
-
-static void parse_float(double value, char *buffer, char fmt, int precision)
-{
-  int decpt, sign, exp, pos;
-  char *digits = NULL;
-  char cvtbuf[80];
-  int capexp = 0;
-  int magnitude;
-
-  if (fmt == 'G' || fmt == 'E')
-  {
-    capexp = 1;
-    fmt += 'a' - 'A';
-  }
-
-  if (fmt == 'g')
-  {
-    digits = ecvtbuf(value, precision, &decpt, &sign, cvtbuf);
-    magnitude = decpt - 1;
-    if (magnitude < -4  ||  magnitude > precision - 1)
-    {
-      fmt = 'e';
-      precision -= 1;
-    }
-    else
-    {
-      fmt = 'f';
-      precision -= decpt;
-    }
-  }
-
-  if (fmt == 'e')
-  {
-    digits = ecvtbuf(value, precision + 1, &decpt, &sign, cvtbuf);
-
-    if (sign) *buffer++ = '-';
-    *buffer++ = *digits;
-    if (precision > 0) *buffer++ = '.';
-    ee_bufcpy(buffer, digits + 1, precision);
-    buffer += precision;
-    *buffer++ = capexp ? 'E' : 'e';
-
-    if (decpt == 0)
-    {
-      if (value == 0.0)
-        exp = 0;
-      else
-        exp = -1;
-    }
-    else
-      exp = decpt - 1;
-
-    if (exp < 0)
-    {
-      *buffer++ = '-';
-      exp = -exp;
-    }
-    else
-      *buffer++ = '+';
-
-    buffer[2] = (exp % 10) + '0';
-    exp = exp / 10;
-    buffer[1] = (exp % 10) + '0';
-    exp = exp / 10;
-    buffer[0] = (exp % 10) + '0';
-    buffer += 3;
-  }
-  else if (fmt == 'f')
-  {
-    digits = fcvtbuf(value, precision, &decpt, &sign, cvtbuf);
-    if (sign) *buffer++ = '-';
-    if (*digits)
-    {
-      if (decpt <= 0)
-      {
-        *buffer++ = '0';
-        *buffer++ = '.';
-        for (pos = 0; pos < -decpt; pos++) *buffer++ = '0';
-        while (*digits) *buffer++ = *digits++;
-      }
-      else
-      {
-        pos = 0;
-        while (*digits)
-        {
-          if (pos++ == decpt) *buffer++ = '.';
-          *buffer++ = *digits++;
-        }
-      }
-    }
-    else
-    {
-      *buffer++ = '0';
-      if (precision > 0)
-      {
-        *buffer++ = '.';
-        for (pos = 0; pos < precision; pos++) *buffer++ = '0';
-      }
-    }
-  }
-
-  *buffer = '\0';
-}
-
-static void decimal_point(char *buffer)
-{
-  while (*buffer)
-  {
-    if (*buffer == '.') return;
-    if (*buffer == 'e' || *buffer == 'E') break;
-    buffer++;
-  }
-
-  if (*buffer)
-  {
-    int n = strnlen(buffer,256);
-    while (n > 0)
-    {
-      buffer[n + 1] = buffer[n];
-      n--;
-    }
-
-    *buffer = '.';
-  }
-  else
-  {
-    *buffer++ = '.';
-    *buffer = '\0';
-  }
-}
-
-static void cropzeros(char *buffer)
-{
-  char *stop;
-
-  while (*buffer && *buffer != '.') buffer++;
-  if (*buffer++)
-  {
-    while (*buffer && *buffer != 'e' && *buffer != 'E') buffer++;
-    stop = buffer--;
-    while (*buffer == '0') buffer--;
-    if (*buffer == '.') buffer--;
-    while (buffer!=stop)
-        *++buffer=0;
-  }
-}
-
-static char *flt(char *str, double num, int size, int precision, char fmt, int flags)
-{
-  char tmp[80];
-  char c, sign;
-  int n, i;
-
-  // Left align means no zero padding
-  if (flags & LEFT) flags &= ~ZEROPAD;
-
-  // Determine padding and sign char
-  c = (flags & ZEROPAD) ? '0' : ' ';
-  sign = 0;
-  if (flags & SIGN)
-  {
-    if (num < 0.0)
-    {
-      sign = '-';
-      num = -num;
-      size--;
-    }
-    else if (flags & PLUS)
-    {
-      sign = '+';
-      size--;
-    }
-    else if (flags & SPACE)
-    {
-      sign = ' ';
-      size--;
-    }
-  }
-
-  // Compute the precision value
-  if (precision < 0)
-    precision = 6; // Default precision: 6
-
-  // Convert floating point number to text
-  parse_float(num, tmp, fmt, precision);
-
-  if ((flags & HEX_PREP) && precision == 0) decimal_point(tmp);
-  if (fmt == 'g' && !(flags & HEX_PREP)) cropzeros(tmp);
-
-  n = strnlen(tmp,256);
-
-  // Output number with alignment and padding
-  size -= n;
-  if (!(flags & (ZEROPAD | LEFT))) while (size-- > 0) *str++ = ' ';
-  if (sign) *str++ = sign;
-  if (!(flags & LEFT)) while (size-- > 0) *str++ = c;
-  for (i = 0; i < n; i++) *str++ = tmp[i];
-  while (size-- > 0) *str++ = ' ';
-
-  return str;
-}
-
-
-/*use O0 preventing consuming more stack*/
-int __attribute__((optimize("O1"))) vsnprintf(char *buffer, size_t n, const char *format, va_list ap)
-{
-    const char *p = format;
-    char ch;
-    char *q = buffer;
-    char *tmp;
-    size_t o = 0;       /* Number of characters output */
-    uintmax_t val = 0;
-    int rank = rank_int;    /* Default rank */
-    int width = 0;
-    int prec = -1;
-    int base;
-    size_t sz;
-    unsigned int flags = 0;
-    enum {
-        st_normal,  /* Ground state */
-        st_flags,   /* Special flags */
-        st_width,   /* Field width */
-        st_prec,    /* Field precision */
-        st_modifiers    /* Length or conversion modifiers */
-    } state = st_normal;
-    const char *sarg;   /* %s string argument */
-    char carg;      /* %c char argument */
-    int slen;       /* String length */
-
-    while ((ch = *p++)) {
-        switch (state) {
-        case st_normal:
-            if (ch == '%') {
-                state = st_flags;
-                flags = 0;
-                rank = rank_int;
-                width = 0;
-                prec = -1;
-            } else {
-                EMIT(ch);
-            }
-            break;
-
-        case st_flags:
-            switch (ch) {
-            case '-':
-                flags |= FL_MINUS;
-                break;
-            case '+':
-                flags |= FL_PLUS;
-                break;
-            case '\'':
-                flags |= FL_TICK;
-                break;
-            case ' ':
-                flags |= FL_SPACE;
-                break;
-            case '#':
-                flags |= FL_HASH;
-                break;
-            case '0':
-                flags |= FL_ZERO;
-                break;
-            default:
-                state = st_width;
-                p--;    /* Process this character again */
-                break;
-            }
-            break;
-
-        case st_width:
-            if (ch >= '0' && ch <= '9') {
-                width = width * 10 + (ch - '0');
-            } else if (ch == '*') {
-                width = va_arg(ap, int);
-                if (width < 0) {
-                    width = -width;
-                    flags |= FL_MINUS;
-                }
-            } else if (ch == '.') {
-                prec = 0;   /* Precision given */
-                state = st_prec;
-            } else {
-                state = st_modifiers;
-                p--;    /* Process this character again */
-            }
-            break;
-
-        case st_prec:
-            if (ch >= '0' && ch <= '9') {
-                prec = prec * 10 + (ch - '0');
-            } else if (ch == '*') {
-                prec = va_arg(ap, int);
-                if (prec < 0)
-                    prec = -1;
-            } else {
-                state = st_modifiers;
-                p--;    /* Process this character again */
-            }
-            break;
-
-        case st_modifiers:
-            switch (ch) {
-                /* Length modifiers - nonterminal sequences */
-            case 'h':
-                rank--; /* Shorter rank */
-                break;
-            case 'l':
-                rank++; /* Longer rank */
-                break;
-            case 'j':
-                rank = INTMAX_RANK;
-                break;
-            case 'z':
-                rank = SIZE_T_RANK;
-                break;
-            case 't':
-                rank = PTRDIFF_T_RANK;
-                break;
-            case 'L':
-            case 'q':
-                rank += 2;
-                break;
-            default:
-                /* Output modifiers - terminal sequences */
-
-                /* Next state will be normal */
-                state = st_normal;
-
-                /* Canonicalize rank */
-                if (rank < MIN_RANK)
-                    rank = MIN_RANK;
-                else if (rank > MAX_RANK)
-                    rank = MAX_RANK;
-
-                switch (ch) {
-                case 'P':   /* Upper case pointer */
-                    flags |= FL_UPPER;
-                    __attribute__ ((fallthrough));
-                    /* fall through */
-                case 'p':   /* Pointer */
-                    base = 16;
-                    prec = (CHAR_BIT*sizeof(void *)+3)/4;
-                    flags |= FL_HASH;
-                    val = (uintmax_t)(uintptr_t)
-                        va_arg(ap, void *);
-                    goto is_integer;
-
-                case 'd':   /* Signed decimal output */
-                case 'i':
-                    base = 10;
-                    flags |= FL_SIGNED;
-                    switch (rank) {
-                    case rank_char:
-                        /* Yes, all these casts are
-                           needed... */
-                        val = (uintmax_t)(intmax_t)
-                            (signed char)
-                            va_arg(ap, signed int);
-                        break;
-                    case rank_short:
-                        val = (uintmax_t)(intmax_t)
-                            (signed short)
-                            va_arg(ap, signed int);
-                        break;
-                    case rank_int:
-                        val = (uintmax_t)(intmax_t)
-                            va_arg(ap, signed int);
-                        break;
-                    case rank_long:
-                        val = (uintmax_t)(intmax_t)
-                            va_arg(ap, signed long);
-                        break;
-                    case rank_longlong:
-                        val = (uintmax_t)(intmax_t)
-                            va_arg(ap,
-                               signed long long);
-                        break;
-                    }
-                    goto is_integer;
-                case 'o':   /* Octal */
-                    base = 8;
-                    goto is_unsigned;
-                case 'u':   /* Unsigned decimal */
-                    base = 10;
-                    goto is_unsigned;
-                case 'X':   /* Upper case hexadecimal */
-                    flags |= FL_UPPER;
-                    __attribute__ ((fallthrough));
-                    /* fall through */
-                case 'x':   /* Hexadecimal */
-                    base = 16;
-                    goto is_unsigned;
-
-                is_unsigned:
-                    switch (rank) {
-                    case rank_char:
-                        val = (uintmax_t)
-                            (unsigned char)
-                            va_arg(ap, unsigned
-                                   int);
-                        break;
-                    case rank_short:
-                        val = (uintmax_t)
-                            (unsigned short)
-                            va_arg(ap, unsigned
-                                   int);
-                        break;
-                    case rank_int:
-                        val = (uintmax_t)
-                            va_arg(ap, unsigned
-                                   int);
-                        break;
-                    case rank_long:
-                        val = (uintmax_t)
-                            va_arg(ap, unsigned
-                                   long);
-                        break;
-                    case rank_longlong:
-                        val = (uintmax_t)
-                            va_arg(ap, unsigned
-                                   long long);
-                        break;
-                    }
-                    /* fall through */
-
-                is_integer:
-                    sz = format_int(q, (o < n) ? n - o : 0,
-                            val, flags, base,
-                            width, prec);
-                    q += sz;
-                    o += sz;
-                    break;
-
-                case 'c':   /* Character */
-                    carg = (char)va_arg(ap, int);
-                    sarg = &carg;
-                    slen = 1;
-                    goto is_string;
-                case 's':   /* String */
-                    sarg = va_arg(ap, const char *);
-                    sarg = sarg ? sarg : "(null)";
-                    slen = strlen(sarg);
-                    goto is_string;
-
-                is_string:
-                    {
-                        char sch;
-                        int i;
-
-                        if (prec != -1 && slen > prec)
-                            slen = prec;
-
-                        if (width > slen
-                            && !(flags & FL_MINUS)) {
-                            char pad =
-                                (flags & FL_ZERO) ?
-                                '0' : ' ';
-                            while (width > slen) {
-                                EMIT(pad);
-                                width--;
-                            }
-                        }
-                        for (i = slen; i; i--) {
-                            sch = *sarg++;
-                            EMIT(sch);
-                        }
-                        if (width > slen
-                            && (flags & FL_MINUS)) {
-                            while (width > slen) {
-                                EMIT(' ');
-                                width--;
-                            }
-                        }
-                    }
-                    break;
-
-                case 'n':
-                    {
-                        /* Output the number of
-                           characters written */
-
-                        switch (rank) {
-                        case rank_char:
-                            *va_arg(ap,
-                                signed char *)
-                                = o;
-                            break;
-                        case rank_short:
-                            *va_arg(ap,
-                                signed short *)
-                                = o;
-                            break;
-                        case rank_int:
-                            *va_arg(ap,
-                                signed int *)
-                                = o;
-                            break;
-                        case rank_long:
-                            *va_arg(ap,
-                                signed long *)
-                                = o;
-                            break;
-                        case rank_longlong:
-                            *va_arg(ap,
-                                signed long long *)
-                                = o;
-                            break;
-                        }
-                    }
-                    break;
-#ifndef DISABLE_PRINT_FLOAT
-                case 'f':
-                    {
-                            tmp = q;
-                        q = flt(q, va_arg(ap, double), width, prec, ch, SIGN);
-                            o += q - tmp;
-                        continue;
-                    }
-#endif
-                default:    /* Anything else, including % */
-                    EMIT(ch);
-                    break;
-                }
-            }
-        }
-    }
-
-    /* Null-terminate the string */
-    if (o < n)
-        *q = '\0';  /* No overflow */
-    else if (n > 0)
-        buffer[n - 1] = '\0';   /* Overflow - terminate at end of buffer */
-
-    return o;
-}
-
-#ifdef SYS_BIG_DEBUG_BUFFER
-static char string[2048];
-#else
-static char string[512];
-#endif
-
-int vsprintf(char *buffer, const char *format, va_list ap)
-{
-    return vsnprintf(buffer, sizeof(string) - 32, format, ap);
-}
-
-extern volatile bool sys_log_all_enable;
-
-void vprint(const char *fmt, va_list argp)
-{
-    char *str;
-    int ch;
-
-    if (sys_log_all_enable) {
-        str = string;
-        if (0 < vsprintf(string, fmt, argp)) {
-            while ('\0' != (ch = *(str++))) {
-#if !defined(DISABLE_PRINT)
-                bl_uart_data_send(debug_uart_id, ch);
-#endif
-            }
-        }
-    }
-}
-
-int bl_putchar(int c)
-{
-#if !defined(DISABLE_PRINT)
-    bl_uart_data_send(debug_uart_id, c);
-#endif
-    return 0;
-}
-
-int puts(const char *s)
-{
-    int counter = 0;
-    char c;
-
-    if (sys_log_all_enable) {
-        while ('\0' != (c = *(s++))) {
-#if !defined(DISABLE_PRINT)
-            bl_uart_data_send(debug_uart_id, c);
-#endif
-            counter++;
-        }
-    }
-    return counter;
-}
-
-int printf(const char *fmt, ...)
-{
-    va_list argp;
-
-    if (sys_log_all_enable) {
-        va_start(argp, fmt);
-        vprint(fmt, argp);
-        va_end(argp);
-    }
-
-    return 0;
-}
-
-int sprintf(char *buffer, const char *format, ...)
-{
-    va_list ap;
-    int rv;
-
-    va_start(ap, format);
-    rv = vsnprintf(buffer, ~(size_t) 0, format, ap);
-    va_end(ap);
-
-    return rv;
-}
-
-int snprintf(char *buffer, size_t n, const char *format, ...)
-{
-    va_list ap;
-    int rv;
-
-    va_start(ap, format);
-    rv = vsnprintf(buffer, n, format, ap);
-    va_end(ap);
-    return rv;
-}
-
-void vMainUARTPrintString(char *pcString)
-{
-    puts(pcString);
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c
deleted file mode 100644
index 524439edc5..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_bl606p.c
+++ /dev/null
@@ -1,399 +0,0 @@
-#ifdef BL808
-#include "bl808.h"
-#include "bl808_clock.h"
-#include "bl808_pds.h"
-#include "bl808_glb.h"
-#elif defined(BL606P)
-#include "bl606p.h"
-#include "bl606p_clock.h"
-#include "bl606p_pds.h"
-#include "bl606p_glb.h"
-#else
-#error "Use CHIP BL808/BL606P for this module"
-#endif
-
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define SYSTEM_CLOCK (32000000UL)
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-
-void System_BOR_Init(void)
-{
-    //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */};
-    //HBN_Set_BOR_Cfg(&borCfg);
-}
-
-void System_Core_Clock_Set(BL_System_Clock_Type type, uint32_t clock)
-{
-    Clock_Cfg_Type *pClk = (Clock_Cfg_Type *)SYS_CLOCK_CFG_ADDR;
-
-    CHECK_PARAM(IS_BL_SYSTEM_CLOCK_TYPE(type));
-
-    if (type < BL_SYSTEM_CLOCK_MAX) {
-        pClk->systemClock[type] = clock;
-        pClk->magic = SYS_CLOCK_CFG_MAGIC;
-    }
-}
-
-void board_init(void)
-{
-
-}
-
-void system_init_bl606p(void)
-#if 0
-{
-    uint32_t i = 0;
-
-    /* enable mstatus FS */
-    uint32_t mstatus = __get_MSTATUS();
-    mstatus |= (1 << 13);
-    __set_MSTATUS(mstatus);
-
-    /* enable mxstatus THEADISAEE */
-    uint32_t mxstatus = __get_MXSTATUS();
-    mxstatus |= (1 << 22);
-    /* enable mxstatus MM */
-    mxstatus |= (1 << 15);
-    __set_MXSTATUS(mxstatus);
-
-    /* get interrupt level from info */
-    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
-
-    /* Every interrupt should be clear by software*/
-    for (i = 0; i < IRQn_LAST; i++) {
-        CLIC->CLICINT[i].IP = 0;
-        CLIC->CLICINT[i].IE = 0;
-        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
-    }
-
-    /* tspend interrupt will be clear auto*/
-    /* tspend use positive interrupt */
-    CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
-
-#ifdef BOOTROM
-    /* i cache enable d cache disable*/
-    uint32_t cache;
-    __DSB();
-    __ISB();
-    __ICACHE_IALL();
-    cache = __get_MHCR();
-    cache |= CACHE_MHCR_IE_Msk;
-    //cache &= ~(uint32_t)CACHE_MHCR_DE_Msk; /* disable all Cache */
-    cache |= (CACHE_MHCR_DE_Msk | CACHE_MHCR_WB_Msk | CACHE_MHCR_WA_Msk | CACHE_MHCR_RS_Msk | CACHE_MHCR_BPE_Msk | CACHE_MHCR_L0BTB_Msk); /* enable all Cache */
-    __set_MHCR(cache);
-    __DCACHE_IALL(); /* invalidate all Cache */
-    __DSB();
-    __ISB();
-    //csi_dcache_disable();
-#else
-    csi_icache_enable();
-    csi_dcache_enable();
-    /* enable preload $ AMR for D$ */
-    __set_MHINT(0x000c);
-#endif
-
-#ifndef CONFIG_OS_SUPPORT
-    /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack */
-    uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus |= (0x03 << 16);
-    __set_MEXSTATUS(mexstatus);
-#else
-    /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack*/
-    uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus |= (0x3 << 16);
-    __set_MEXSTATUS(mexstatus);
-#endif
-
-#ifdef BOOTROM
-    extern void GLB_Power_On_LDO18_IO(void);
-    extern void WDT_Disable(void);
-    extern BL_Err_Type HBN_Clear_RTC_INT(void);
-    uint32_t *p;
-    BMX_TO_Cfg_Type bmxCfg = {
-        .arbMod = BMX_ARB_FIX,
-        .timeoutEn = 0x1F,
-        //.errEn=DISABLE,
-    };
-
-    /* M0 boot log Flag */
-    extern uint32_t __bootrom_data_section_end;
-    p = (uint32_t *)(&__bootrom_data_section_end);
-    *p = 0x5A5AA5A5;
-    /*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,
-    if not disable this bit, CPU will also get hardfault at the same time*/
-    GLB_BMX_TO_Init(&bmxCfg);
-    //GLB_BMX_Addr_Monitor_Disable();
-
-    /* Do the same for L1C BMX*/
-    //L1C_BMX_Init(&l1cBmxCfg);
-    //L1C_BMX_Addr_Monitor_Disable();
-
-    /* make ram max*/
-    //L1C_Set_Way_Disable(0x0f);
-    //GLB_Set_EM_Sel(GLB_EM_0KB);
-
-    /* Disable Watchdog */
-    WDT_Disable();
-    /* Clear RTC */
-    HBN_Clear_RTC_INT();
-
-    /*TODO*/
-    /* Make OCRAM Idle from retention or sleep */
-    //GLB_Set_OCRAM_Idle();
-    //GLB_Set_SRAM_RET(0x0);
-    //GLB_Set_SRAM_SLP(0x0);
-    /* Disable embedded flash power up*/
-    //HBN_Set_Embedded_Flash_Pullup(DISABLE);
-#if 0
-    /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
-    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
-    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
-    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
-
-    /* Restore default setting*/
-    GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
-    GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE);
-
-    /*Power up soc 11 power domain,TODO: This should be optional */
-    //AON_Power_On_SOC_11();
-    /* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/
-    //BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);
-    /* Power up flash power*/
-    //GLB_Power_On_LDO18_IO();
-
-#endif
-#endif
-
-    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 1);
-    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 1);
-
-    /* init bor for all platform */
-    System_BOR_Init();
-}
-#else
-{
-    uint32_t i=0;
-
-    /* enable mstatus FS */
-    uint32_t mstatus = __get_MSTATUS();
-    mstatus |= (1 << 13);
-    __set_MSTATUS(mstatus);
-
-    /* enable mxstatus THEADISAEE */
-    uint32_t mxstatus = __get_MXSTATUS();
-    mxstatus |= (1 << 22);
-    /* enable mxstatus MM */
-    mxstatus |= (1 << 15);
-    __set_MXSTATUS(mxstatus);
-
-    /* get interrupt level from info */
-    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
-
-    /* Every interrupt should be clear by software*/
-    for (i = 0; i < IRQn_LAST; i++) {
-        CLIC->CLICINT[i].IP = 0;
-        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
-    }
-
-    /* tspend interrupt will be clear auto*/
-    /* tspend use positive interrupt */
-    CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
-
-    csi_dcache_enable();
-    csi_icache_enable();
-    /* enable preload $ AMR for D$*/
-    __set_MHINT(0x0004);
-    CPU_Interrupt_Enable(MSOFT_IRQn);
-
-    /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/
-    uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus &= ~(0x3 << 16);
-    __set_MEXSTATUS(mexstatus);
-
-#ifdef BOOTROM
-    extern void GLB_Power_On_LDO18_IO(void);
-    extern void WDT_Disable(void);
-    extern void HBN_Clear_RTC_INT(void);
-
-    BMX_Cfg_Type bmxCfg={
-            .timeoutEn=0,
-            .errEn=DISABLE,
-            .arbMod=BMX_ARB_FIX
-    };
-    L1C_BMX_Cfg_Type  l1cBmxCfg={
-            .timeoutEn=0,
-            .errEn=DISABLE,
-            .arbMod=L1C_BMX_ARB_FIX,
-    };
-
-    /* NP boot log Flag */
-    p= (uint32_t *)(BFLB_BOOTROM_NP_BOOT_LOG_ADDR);
-    *p=0x5A5AA5A5;
-    /*diable BMX error incase Sbooten=0xf,while user send vector(core) reset and CPU read deadbeef,
-    if not disable this bit, CPU will also get hardfault at the same time*/
-    //GLB->bmx_cfg1.BF.bmx_err_en=0;
-    //GLB->bmx_cfg1.BF.bmx_timeout_en=0;
-    //GLB->bmx_cfg2.BF.bmx_err_addr_dis=1;
-    GLB_BMX_Init(&bmxCfg);
-    GLB_BMX_Addr_Monitor_Disable();
-    //L1C->l1c_config.BF.l1c_bmx_err_en=0;
-    //L1C->l1c_config.BF.l1c_bmx_timeout_en=0;
-    //L1C->l1c_bmx_err_addr_en.BF.l1c_bmx_err_addr_dis=1;
-    L1C_BMX_Init(&l1cBmxCfg);
-    L1C_BMX_Addr_Monitor_Disable();
-    //L1C->l1c_config.BF.l1c_way_dis=0xf;
-    L1C_Set_Way_Disable(0x0f);
-    /* Disable Watchdog */
-    WDT_Disable();
-    /* Clear RTC */
-    HBN_Clear_RTC_INT();
-    /* Make OCRAM Idle from retention or sleep */
-    GLB_Set_OCRAM_Idle();
-    /* Disable embedded flash power up*/
-    HBN_Set_Embedded_Flash_Pullup(DISABLE);
-#endif
-
-#if 0
-    /* disable hardware_pullup_pull_down (reg_en_hw_pu_pd = 0) */
-    tmpVal=BL_RD_REG(HBN_BASE,HBN_IRQ_MODE);
-    tmpVal=BL_CLR_REG_BIT(tmpVal,HBN_REG_EN_HW_PU_PD);
-    BL_WR_REG(HBN_BASE,HBN_IRQ_MODE,tmpVal);
-
-    GLB_Set_EM_Sel(GLB_EM_0KB);
-
-    /* Fix 26M xtal clkpll_sdmin */
-    tmpVal=BL_RD_REG(PDS_BASE,PDS_CLKPLL_SDM);
-    if(0x49D39D==BL_GET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN)){
-        tmpVal=BL_SET_REG_BITS_VAL(tmpVal,PDS_CLKPLL_SDMIN,0x49D89E);
-        BL_WR_REG(PDS_BASE,PDS_CLKPLL_SDM,tmpVal);
-    }
-
-    /* Restore default setting*/
-    GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE);
-    GLB_JTAG_Sig_Swap_Set(JTAG_SIG_SWAP_NONE);
-
-    /* CLear all interrupt */
-    p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIE);
-    for(i=0;i<(IRQn_LAST+3)/4;i++){
-        p[i]=0;
-    }
-    p=(uint32_t *)(CLIC_HART0_ADDR+CLIC_INTIP);
-    for(i=0;i<(IRQn_LAST+3)/4;i++){
-        p[i]=0;
-    }
-#endif
-    /* global IRQ disable */
-    __disable_irq();
-
-    //__asm volatile("csrw mnxti, %0" : : "i"(0x1 << 3));
-    /* init bor for all platform */
-    //system_bor_init();
-
-#ifdef BOOTROM
-    /*Power up soc 11 power domain,TODO: This should be optional */
-    //AON_Power_On_SOC_11();
-    /* Record LDO18 pu flag before power up. This maybe not neccessary but copy from 606*/
-    //BL_WR_WORD(BFLB_BOOTROM_AP_BOOT_LOG_ADDR,GLB->ldo18io.BF.pu_ldo18io);
-    /* Power up flash power*/
-    //GLB_Power_On_LDO18_IO();
-#endif
-
-}
-#endif
-
-void System_Post_Init(void)
-{
-#ifndef BOOTROM
-    //PDS_Power_On_MM_System();
-    //FIXME
-    GLB_Set_EM_Sel(1);
-#endif
-
-    System_Interrupt_Init();
-
-    CPU_Interrupt_Enable(MSOFT_IRQn);
-
-#ifndef BOOTROM
-    /* global IRQ enable */
-    __enable_irq();
-#endif
-}
-
-void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    csi_vic_set_prio(IRQn, PreemptPriority);
-}
-
-int32_t drv_get_cpu_id(void)
-{
-    return __get_MHARTID();
-}
-
-int32_t drv_get_cpu_freq(int32_t idx)
-{
-    return 32 * 1000 * 1000UL;
-}
-
-#if defined(DUAL_CORE)
-extern void Reset_Handler(void);
-#endif
-
-/**
-  \brief       enable irq.
-  \param[in]   irq_num Number of IRQ.
-  \return      None.
-*/
-__attribute__((weak)) void CPU_Interrupt_Enable(uint32_t irq_num)
-{
-    if (irq_num >= IRQn_LAST) {
-        // MSG("Error! This interrupt don't support!\n");
-    } else {
-#ifdef CONFIG_SYSTEM_SECURE
-        csi_vic_enable_sirq(irq_num);
-#else
-        csi_vic_enable_irq(irq_num);
-#endif
-    }
-}
-
-/**
-  \brief       disable irq.
-  \param[in]   irq_num Number of IRQ.
-  \return      None.
-*/
-__attribute__((weak)) void CPU_Interrupt_Disable(uint32_t irq_num)
-{
-    if (irq_num >= IRQn_LAST) {
-        //MSG("Error! This interrupt don't support!\n");
-    } else {
-#ifdef CONFIG_SYSTEM_SECURE
-        csi_vic_disable_sirq(irq_num);
-#else
-        csi_vic_disable_irq(irq_num);
-#endif
-    }
-}
-
-/**
-  \brief   Clear Pending Interrupt
-  \details Clear the pending bit of an external interrupt.
-  \param [in]      IRQn  External interrupt number. Value cannot be negative.
- */
-__attribute__((weak)) void CPU_Interrupt_Pending_Clear(uint32_t irq_num)
-{
-    if (irq_num >= IRQn_LAST) {
-        //MSG("Error! This interrupt don't support!\n");
-        return;
-    } else {
-#ifdef CONFIG_SYSTEM_SECURE
-        csi_vic_clear_pending_irq(irq_num);
-#else
-        csi_vic_clear_pending_irq(irq_num);
-#endif
-    }
-}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c b/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c
deleted file mode 100644
index dff511ad05..0000000000
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/startup_bl808/evb/src/startup_interrupt.c
+++ /dev/null
@@ -1,180 +0,0 @@
-
-#include 
-#include 
-#include 
-#ifdef BL808
-#include "bl808.h"
-#elif defined(BL606P)
-#include "bl606p.h"
-#else
-#error "Use CHIP BL808/BL606P for this module"
-#endif
-
-
-#define MSG(...)
-
-typedef void( *pFunc )( void );
-void NMI_Handler(void);
-
-pFunc g_irqvector[IRQn_LAST]={0};
-pFunc g_nmivector=NMI_Handler;
-
-extern void Default_IRQHandler(void);
-extern void Default_Handler(void);
-extern void IRQ_Handler(void);
-
-const pFunc __Vectors[] __attribute__ ((section(".init"),aligned(64))) = {
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,            /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-    IRQ_Handler,                         /*         */
-
-    IRQ_Handler,//BMX_ERR_IRQHandler_Wrapper,              /* 16 +  0 */
-    IRQ_Handler,//BMX_TO_IRQHandler_Wrapper,               /* 16 +  1 */
-    IRQ_Handler,//L1C_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  2 */
-    IRQ_Handler,//L1C_BMX_TO_IRQHandler_Wrapper,           /* 16 +  3 */
-    IRQ_Handler,//SEC_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  4 */
-    IRQ_Handler,//RF_TOP_INT0_IRQHandler_Wrapper,          /* 16 +  5 */
-    IRQ_Handler,//RF_TOP_INT1_IRQHandler_Wrapper,          /* 16 +  6 */
-    IRQ_Handler,//SDIO_IRQHandler_Wrapper,                 /* 16 +  7 */
-    IRQ_Handler,//DMA_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  8 */
-    IRQ_Handler,//SEC_GMAC_IRQHandler_Wrapper,             /* 16 +  9 */
-    IRQ_Handler,//SEC_CDET_IRQHandler_Wrapper,             /* 16 + 10 */
-    IRQ_Handler,//SEC_PKA_IRQHandler_Wrapper,              /* 16 + 11 */
-    IRQ_Handler,//SEC_TRNG_IRQHandler_Wrapper,             /* 16 + 12 */
-    IRQ_Handler,//SEC_AES_IRQHandler_Wrapper,              /* 16 + 13 */
-    IRQ_Handler,//SEC_SHA_IRQHandler_Wrapper,              /* 16 + 14 */
-    IRQ_Handler,//DMA_ALL_IRQHandler_Wrapper,              /* 16 + 15 */
-    IRQ_Handler,//0,                                       /* 16 + 16 */
-    IRQ_Handler,//0,                                       /* 16 + 17 */
-    IRQ_Handler,//0,                                       /* 16 + 18 */
-    IRQ_Handler,//IRTX_IRQHandler_Wrapper,                 /* 16 + 19 */
-    IRQ_Handler,//IRRX_IRQHandler_Wrapper,                 /* 16 + 20 */
-    IRQ_Handler,//0,                                       /* 16 + 21 */
-    IRQ_Handler,//0,                                       /* 16 + 22 */
-    IRQ_Handler,//SF_CTRL_IRQHandler_Wrapper,              /* 16 + 23 */
-    IRQ_Handler,//0,                                       /* 16 + 24 */
-    IRQ_Handler,//GPADC_DMA_IRQHandler_Wrapper,            /* 16 + 25 */
-    IRQ_Handler,//EFUSE_IRQHandler_Wrapper,                /* 16 + 26 */
-    IRQ_Handler,//SPI_IRQHandler_Wrapper,                  /* 16 + 27 */
-    IRQ_Handler,//0,                                       /* 16 + 28 */
-    IRQ_Handler,//UART0_IRQHandler_Wrapper,                /* 16 + 29 */
-    IRQ_Handler,//UART1_IRQHandler_Wrapper,                /* 16 + 30 */
-    IRQ_Handler,//0,                                       /* 16 + 31 */
-    IRQ_Handler,//I2C_IRQHandler_Wrapper,                  /* 16 + 32 */
-    IRQ_Handler,//0,                                       /* 16 + 33 */
-    IRQ_Handler,//PWM_IRQHandler_Wrapper,                  /* 16 + 34 */
-    IRQ_Handler,//0,                                       /* 16 + 35 */
-    IRQ_Handler,//TIMER_CH0_IRQHandler_Wrapper,            /* 16 + 36 */
-    IRQ_Handler,//TIMER_CH1_IRQHandler_Wrapper,            /* 16 + 37 */
-    IRQ_Handler,//TIMER_WDT_IRQHandler_Wrapper,            /* 16 + 38 */
-    IRQ_Handler,//0,                                       /* 16 + 39 */
-    IRQ_Handler,//0,                                       /* 16 + 40 */
-    IRQ_Handler,//0,                                       /* 16 + 41 */
-    IRQ_Handler,//0,                                       /* 16 + 42 */
-    IRQ_Handler,//0,                                       /* 16 + 43 */
-    IRQ_Handler,//GPIO_INT0_IRQHandler_Wrapper,            /* 16 + 44 */
-    IRQ_Handler,//0,                                       /* 16 + 45 */
-    IRQ_Handler,//0,                                       /* 16 + 46 */
-    IRQ_Handler,//0,                                       /* 16 + 47 */
-    IRQ_Handler,//0,                                       /* 16 + 48 */
-    IRQ_Handler,//0,                                       /* 16 + 49 */
-    IRQ_Handler,//PDS_WAKEUP_IRQHandler_Wrapper,           /* 16 + 50 */
-    IRQ_Handler,//HBN_OUT0_IRQHandler_Wrapper,             /* 16 + 51 */
-    IRQ_Handler,//HBN_OUT1_IRQHandler_Wrapper,             /* 16 + 52 */
-    IRQ_Handler,//BOR_IRQHandler_Wrapper,                  /* 16 + 53 */
-    IRQ_Handler,//WIFI_IRQHandler_Wrapper,                 /* 16 + 54 */
-    IRQ_Handler,//BZ_PHY_IRQHandler_Wrapper,               /* 16 + 55 */
-    IRQ_Handler,//BLE_IRQHandler_Wrapper,                  /* 16 + 56 */
-    IRQ_Handler,//MAC_TXRX_TIMER_IRQHandler_Wrapper,       /* 16 + 57 */
-    IRQ_Handler,//MAC_TXRX_MISC_IRQHandler_Wrapper,        /* 16 + 58 */
-    IRQ_Handler,//MAC_RX_TRG_IRQHandler_Wrapper,           /* 16 + 59 */
-    IRQ_Handler,//MAC_TX_TRG_IRQHandler_Wrapper,           /* 16 + 60 */
-    IRQ_Handler,//MAC_GEN_IRQHandler_Wrapper,              /* 16 + 61 */
-    IRQ_Handler,//MAC_PORT_TRG_IRQHandler_Wrapper,         /* 16 + 62 */
-    IRQ_Handler,//WIFI_IPC_PUBLIC_IRQHandler_Wrapper,      /* 16 + 63 */
-};
-
-void trap_c(uint32_t *regs)
-{
-    int i;
-    uint32_t vec = 0;
-
-    vec = __get_MCAUSE() & 0x3FF;
-
-    MSG("CPU Exception: NO.%d", vec);
-    MSG("\n");
-
-    for (i = 0; i < 31; i++) {
-        MSG("x%d: %08x\t", i + 1, regs[i]);
-
-        if ((i % 4) == 3) {
-            MSG("\n");
-        }
-    }
-
-    MSG("\n");
-    MSG("mepc   : %08x\n", regs[31]);
-    MSG("mstatus: %08x\n", regs[32]);
-
-    //if (trap_c_callback) {
-    //    trap_c_callback();
-    //}
-
-    while (1);
-}
-
-void NMI_Handler(void)
-{
-
-    MSG("NMI_Handler\r\n");
-
-    while (1);
-}
-
-void Interrupt_Handler_Register(IRQn_Type irq,pFunc interruptFun)
-{
-    if(irq
-#include 
-
-#define FDT_FIRST_SUPPORTED_VERSION 0x02
-#define FDT_LAST_SUPPORTED_VERSION  0x11
-
-/* Error codes: informative error codes */
-#define FDT_ERR_NOTFOUND    1
-    /* FDT_ERR_NOTFOUND: The requested node or property does not exist */
-#define FDT_ERR_EXISTS      2
-    /* FDT_ERR_EXISTS: Attempted to create a node or property which
-     * already exists */
-#define FDT_ERR_NOSPACE     3
-    /* FDT_ERR_NOSPACE: Operation needed to expand the device
-     * tree, but its buffer did not have sufficient space to
-     * contain the expanded tree. Use fdt_open_into() to move the
-     * device tree to a buffer with more space. */
-
-/* Error codes: codes for bad parameters */
-#define FDT_ERR_BADOFFSET   4
-    /* FDT_ERR_BADOFFSET: Function was passed a structure block
-     * offset which is out-of-bounds, or which points to an
-     * unsuitable part of the structure for the operation. */
-#define FDT_ERR_BADPATH     5
-    /* FDT_ERR_BADPATH: Function was passed a badly formatted path
-     * (e.g. missing a leading / for a function which requires an
-     * absolute path) */
-#define FDT_ERR_BADPHANDLE  6
-    /* FDT_ERR_BADPHANDLE: Function was passed an invalid phandle.
-     * This can be caused either by an invalid phandle property
-     * length, or the phandle value was either 0 or -1, which are
-     * not permitted. */
-#define FDT_ERR_BADSTATE    7
-    /* FDT_ERR_BADSTATE: Function was passed an incomplete device
-     * tree created by the sequential-write functions, which is
-     * not sufficiently complete for the requested operation. */
-
-/* Error codes: codes for bad device tree blobs */
-#define FDT_ERR_TRUNCATED   8
-    /* FDT_ERR_TRUNCATED: FDT or a sub-block is improperly
-     * terminated (overflows, goes outside allowed bounds, or
-     * isn't properly terminated).  */
-#define FDT_ERR_BADMAGIC    9
-    /* FDT_ERR_BADMAGIC: Given "device tree" appears not to be a
-     * device tree at all - it is missing the flattened device
-     * tree magic number. */
-#define FDT_ERR_BADVERSION  10
-    /* FDT_ERR_BADVERSION: Given device tree has a version which
-     * can't be handled by the requested operation.  For
-     * read-write functions, this may mean that fdt_open_into() is
-     * required to convert the tree to the expected version. */
-#define FDT_ERR_BADSTRUCTURE    11
-    /* FDT_ERR_BADSTRUCTURE: Given device tree has a corrupt
-     * structure block or other serious error (e.g. misnested
-     * nodes, or subnodes preceding properties). */
-#define FDT_ERR_BADLAYOUT   12
-    /* FDT_ERR_BADLAYOUT: For read-write functions, the given
-     * device tree has it's sub-blocks in an order that the
-     * function can't handle (memory reserve map, then structure,
-     * then strings).  Use fdt_open_into() to reorganize the tree
-     * into a form suitable for the read-write operations. */
-
-/* "Can't happen" error indicating a bug in libfdt */
-#define FDT_ERR_INTERNAL    13
-    /* FDT_ERR_INTERNAL: libfdt has failed an internal assertion.
-     * Should never be returned, if it is, it indicates a bug in
-     * libfdt itself. */
-
-/* Errors in device tree content */
-#define FDT_ERR_BADNCELLS   14
-    /* FDT_ERR_BADNCELLS: Device tree has a #address-cells, #size-cells
-     * or similar property with a bad format or value */
-
-#define FDT_ERR_BADVALUE    15
-    /* FDT_ERR_BADVALUE: Device tree has a property with an unexpected
-     * value. For example: a property expected to contain a string list
-     * is not NUL-terminated within the length of its value. */
-
-#define FDT_ERR_BADOVERLAY  16
-    /* FDT_ERR_BADOVERLAY: The device tree overlay, while
-     * correctly structured, cannot be applied due to some
-     * unexpected or missing value, property or node. */
-
-#define FDT_ERR_NOPHANDLES  17
-    /* FDT_ERR_NOPHANDLES: The device tree doesn't have any
-     * phandle available anymore without causing an overflow */
-
-#define FDT_ERR_MAX     17
-
-/**********************************************************************/
-/* Low-level functions (you probably don't need these)                */
-/**********************************************************************/
-
-#ifndef SWIG /* This function is not useful in Python */
-const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int checklen);
-#endif
-static inline void *fdt_offset_ptr_w(void *fdt, int offset, int checklen)
-{
-    return (void *)(uintptr_t)fdt_offset_ptr(fdt, offset, checklen);
-}
-
-uint32_t fdt_next_tag(const void *fdt, int offset, int *nextoffset);
-
-/*
- * Alignment helpers:
- *     These helpers access words from a device tree blob.  They're
- *     built to work even with unaligned pointers on platforms (ike
- *     ARM) that don't like unaligned loads and stores
- */
-
-static inline uint32_t fdt32_ld(const fdt32_t *p)
-{
-    const uint8_t *bp = (const uint8_t *)p;
-
-    return ((uint32_t)bp[0] << 24)
-        | ((uint32_t)bp[1] << 16)
-        | ((uint32_t)bp[2] << 8)
-        | bp[3];
-}
-
-static inline uint64_t fdt64_ld(const fdt64_t *p)
-{
-    const uint8_t *bp = (const uint8_t *)p;
-
-    return ((uint64_t)bp[0] << 56)
-        | ((uint64_t)bp[1] << 48)
-        | ((uint64_t)bp[2] << 40)
-        | ((uint64_t)bp[3] << 32)
-        | ((uint64_t)bp[4] << 24)
-        | ((uint64_t)bp[5] << 16)
-        | ((uint64_t)bp[6] << 8)
-        | bp[7];
-}
-
-/**********************************************************************/
-/* Traversal functions                                                */
-/**********************************************************************/
-
-int fdt_next_node(const void *fdt, int offset, int *depth);
-
-/**
- * fdt_first_subnode() - get offset of first direct subnode
- *
- * @fdt:    FDT blob
- * @offset: Offset of node to check
- * @return offset of first subnode, or -FDT_ERR_NOTFOUND if there is none
- */
-int fdt_first_subnode(const void *fdt, int offset);
-
-/**
- * fdt_next_subnode() - get offset of next direct subnode
- *
- * After first calling fdt_first_subnode(), call this function repeatedly to
- * get direct subnodes of a parent node.
- *
- * @fdt:    FDT blob
- * @offset: Offset of previous subnode
- * @return offset of next subnode, or -FDT_ERR_NOTFOUND if there are no more
- * subnodes
- */
-int fdt_next_subnode(const void *fdt, int offset);
-
-/**
- * fdt_for_each_subnode - iterate over all subnodes of a parent
- *
- * @node:   child node (int, lvalue)
- * @fdt:    FDT blob (const void *)
- * @parent: parent node (int)
- *
- * This is actually a wrapper around a for loop and would be used like so:
- *
- *  fdt_for_each_subnode(node, fdt, parent) {
- *      Use node
- *      ...
- *  }
- *
- *  if ((node < 0) && (node != -FDT_ERR_NOTFOUND)) {
- *      Error handling
- *  }
- *
- * Note that this is implemented as a macro and @node is used as
- * iterator in the loop. The parent variable be constant or even a
- * literal.
- *
- */
-#define fdt_for_each_subnode(node, fdt, parent)     \
-    for (node = fdt_first_subnode(fdt, parent); \
-         node >= 0;                 \
-         node = fdt_next_subnode(fdt, node))
-
-/**********************************************************************/
-/* General functions                                                  */
-/**********************************************************************/
-#define fdt_get_header(fdt, field) \
-    (fdt32_ld(&((const struct fdt_header *)(fdt))->field))
-#define fdt_magic(fdt)          (fdt_get_header(fdt, magic))
-#define fdt_totalsize(fdt)      (fdt_get_header(fdt, totalsize))
-#define fdt_off_dt_struct(fdt)      (fdt_get_header(fdt, off_dt_struct))
-#define fdt_off_dt_strings(fdt)     (fdt_get_header(fdt, off_dt_strings))
-#define fdt_off_mem_rsvmap(fdt)     (fdt_get_header(fdt, off_mem_rsvmap))
-#define fdt_version(fdt)        (fdt_get_header(fdt, version))
-#define fdt_last_comp_version(fdt)  (fdt_get_header(fdt, last_comp_version))
-#define fdt_boot_cpuid_phys(fdt)    (fdt_get_header(fdt, boot_cpuid_phys))
-#define fdt_size_dt_strings(fdt)    (fdt_get_header(fdt, size_dt_strings))
-#define fdt_size_dt_struct(fdt)     (fdt_get_header(fdt, size_dt_struct))
-
-#define fdt_set_hdr_(name) \
-    static inline void fdt_set_##name(void *fdt, uint32_t val) \
-    { \
-        struct fdt_header *fdth = (struct fdt_header *)fdt; \
-        fdth->name = cpu_to_fdt32(val); \
-    }
-fdt_set_hdr_(magic);
-fdt_set_hdr_(totalsize);
-fdt_set_hdr_(off_dt_struct);
-fdt_set_hdr_(off_dt_strings);
-fdt_set_hdr_(off_mem_rsvmap);
-fdt_set_hdr_(version);
-fdt_set_hdr_(last_comp_version);
-fdt_set_hdr_(boot_cpuid_phys);
-fdt_set_hdr_(size_dt_strings);
-fdt_set_hdr_(size_dt_struct);
-#undef fdt_set_hdr_
-
-/**
- * fdt_header_size - return the size of the tree's header
- * @fdt: pointer to a flattened device tree
- */
-size_t fdt_header_size_(uint32_t version);
-static inline size_t fdt_header_size(const void *fdt)
-{
-    return fdt_header_size_(fdt_version(fdt));
-}
-
-/**
- * fdt_check_header - sanity check a device tree header
-
- * @fdt: pointer to data which might be a flattened device tree
- *
- * fdt_check_header() checks that the given buffer contains what
- * appears to be a flattened device tree, and that the header contains
- * valid information (to the extent that can be determined from the
- * header alone).
- *
- * returns:
- *     0, if the buffer appears to contain a valid device tree
- *     -FDT_ERR_BADMAGIC,
- *     -FDT_ERR_BADVERSION,
- *     -FDT_ERR_BADSTATE,
- *     -FDT_ERR_TRUNCATED, standard meanings, as above
- */
-int fdt_check_header(const void *fdt);
-
-/**
- * fdt_move - move a device tree around in memory
- * @fdt: pointer to the device tree to move
- * @buf: pointer to memory where the device is to be moved
- * @bufsize: size of the memory space at buf
- *
- * fdt_move() relocates, if possible, the device tree blob located at
- * fdt to the buffer at buf of size bufsize.  The buffer may overlap
- * with the existing device tree blob at fdt.  Therefore,
- *     fdt_move(fdt, fdt, fdt_totalsize(fdt))
- * should always succeed.
- *
- * returns:
- *     0, on success
- *     -FDT_ERR_NOSPACE, bufsize is insufficient to contain the device tree
- *     -FDT_ERR_BADMAGIC,
- *     -FDT_ERR_BADVERSION,
- *     -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_move(const void *fdt, void *buf, int bufsize);
-
-/**********************************************************************/
-/* Read-only functions                                                */
-/**********************************************************************/
-
-int fdt_check_full(const void *fdt, size_t bufsize);
-
-/**
- * fdt_get_string - retrieve a string from the strings block of a device tree
- * @fdt: pointer to the device tree blob
- * @stroffset: offset of the string within the strings block (native endian)
- * @lenp: optional pointer to return the string's length
- *
- * fdt_get_string() retrieves a pointer to a single string from the
- * strings block of the device tree blob at fdt, and optionally also
- * returns the string's length in *lenp.
- *
- * returns:
- *     a pointer to the string, on success
- *     NULL, if stroffset is out of bounds, or doesn't point to a valid string
- */
-const char *fdt_get_string(const void *fdt, int stroffset, int *lenp);
-
-/**
- * fdt_string - retrieve a string from the strings block of a device tree
- * @fdt: pointer to the device tree blob
- * @stroffset: offset of the string within the strings block (native endian)
- *
- * fdt_string() retrieves a pointer to a single string from the
- * strings block of the device tree blob at fdt.
- *
- * returns:
- *     a pointer to the string, on success
- *     NULL, if stroffset is out of bounds, or doesn't point to a valid string
- */
-const char *fdt_string(const void *fdt, int stroffset);
-
-/**
- * fdt_get_max_phandle - retrieves the highest phandle in a tree
- * @fdt: pointer to the device tree blob
- *
- * fdt_get_max_phandle retrieves the highest phandle in the given
- * device tree. This will ignore badly formatted phandles, or phandles
- * with a value of 0 or -1.
- *
- * returns:
- *      the highest phandle on success
- *      0, if no phandle was found in the device tree
- *      -1, if an error occurred
- */
-uint32_t fdt_get_max_phandle(const void *fdt);
-
-/**
- * fdt_num_mem_rsv - retrieve the number of memory reserve map entries
- * @fdt: pointer to the device tree blob
- *
- * Returns the number of entries in the device tree blob's memory
- * reservation map.  This does not include the terminating 0,0 entry
- * or any other (0,0) entries reserved for expansion.
- *
- * returns:
- *     the number of entries
- */
-int fdt_num_mem_rsv(const void *fdt);
-
-/**
- * fdt_get_mem_rsv - retrieve one memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @address, @size: pointers to 64-bit variables
- *
- * On success, *address and *size will contain the address and size of
- * the n-th reserve map entry from the device tree blob, in
- * native-endian format.
- *
- * returns:
- *     0, on success
- *     -FDT_ERR_BADMAGIC,
- *     -FDT_ERR_BADVERSION,
- *     -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size);
-
-/**
- * fdt_subnode_offset_namelen - find a subnode based on substring
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_subnode_offset(), but only examine the first
- * namelen characters of name for matching the subnode name.  This is
- * useful for finding subnodes based on a portion of a larger string,
- * such as a full path.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_subnode_offset_namelen(const void *fdt, int parentoffset,
-                   const char *name, int namelen);
-#endif
-/**
- * fdt_subnode_offset - find a subnode of a given node
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- *
- * fdt_subnode_offset() finds a subnode of the node at structure block
- * offset parentoffset with the given name.  name may include a unit
- * address, in which case fdt_subnode_offset() will find the subnode
- * with that unit address, or the unit address may be omitted, in
- * which case fdt_subnode_offset() will find an arbitrary subnode
- * whose name excluding unit address matches the given name.
- *
- * returns:
- *  structure block offset of the requested subnode (>=0), on success
- *  -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- *  -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
- *      tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_subnode_offset(const void *fdt, int parentoffset, const char *name);
-
-/**
- * fdt_path_offset_namelen - find a tree node by its full path
- * @fdt: pointer to the device tree blob
- * @path: full path of the node to locate
- * @namelen: number of characters of path to consider
- *
- * Identical to fdt_path_offset(), but only consider the first namelen
- * characters of path as the path name.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen);
-#endif
-
-/**
- * fdt_path_offset - find a tree node by its full path
- * @fdt: pointer to the device tree blob
- * @path: full path of the node to locate
- *
- * fdt_path_offset() finds a node of a given path in the device tree.
- * Each path component may omit the unit address portion, but the
- * results of this are undefined if any such path component is
- * ambiguous (that is if there are multiple nodes at the relevant
- * level matching the given component, differentiated only by unit
- * address).
- *
- * returns:
- *  structure block offset of the node with the requested path (>=0), on
- *      success
- *  -FDT_ERR_BADPATH, given path does not begin with '/' or is invalid
- *  -FDT_ERR_NOTFOUND, if the requested node does not exist
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_path_offset(const void *fdt, const char *path);
-
-/**
- * fdt_get_name - retrieve the name of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of the starting node
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_name() retrieves the name (including unit address) of the
- * device tree node at structure block offset nodeoffset.  If lenp is
- * non-NULL, the length of this name is also returned, in the integer
- * pointed to by lenp.
- *
- * returns:
- *  pointer to the node's name, on success
- *      If lenp is non-NULL, *lenp contains the length of that name
- *          (>=0)
- *  NULL, on error
- *      if lenp is non-NULL *lenp contains an error code (<0):
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- *          tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE, standard meanings
- */
-const char *fdt_get_name(const void *fdt, int nodeoffset, int *lenp);
-
-/**
- * fdt_first_property_offset - find the offset of a node's first property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of a node
- *
- * fdt_first_property_offset() finds the first property of the node at
- * the given structure block offset.
- *
- * returns:
- *  structure block offset of the property (>=0), on success
- *  -FDT_ERR_NOTFOUND, if the requested node has no properties
- *  -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_BEGIN_NODE tag
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_first_property_offset(const void *fdt, int nodeoffset);
-
-/**
- * fdt_next_property_offset - step through a node's properties
- * @fdt: pointer to the device tree blob
- * @offset: structure block offset of a property
- *
- * fdt_next_property_offset() finds the property immediately after the
- * one at the given structure block offset.  This will be a property
- * of the same node as the given property.
- *
- * returns:
- *  structure block offset of the next property (>=0), on success
- *  -FDT_ERR_NOTFOUND, if the given property is the last in its node
- *  -FDT_ERR_BADOFFSET, if nodeoffset did not point to an FDT_PROP tag
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_next_property_offset(const void *fdt, int offset);
-
-/**
- * fdt_for_each_property_offset - iterate over all properties of a node
- *
- * @property_offset:    property offset (int, lvalue)
- * @fdt:        FDT blob (const void *)
- * @node:       node offset (int)
- *
- * This is actually a wrapper around a for loop and would be used like so:
- *
- *  fdt_for_each_property_offset(property, fdt, node) {
- *      Use property
- *      ...
- *  }
- *
- *  if ((property < 0) && (property != -FDT_ERR_NOTFOUND)) {
- *      Error handling
- *  }
- *
- * Note that this is implemented as a macro and property is used as
- * iterator in the loop. The node variable can be constant or even a
- * literal.
- */
-#define fdt_for_each_property_offset(property, fdt, node)   \
-    for (property = fdt_first_property_offset(fdt, node);   \
-         property >= 0;                 \
-         property = fdt_next_property_offset(fdt, property))
-
-/**
- * fdt_get_property_by_offset - retrieve the property at a given offset
- * @fdt: pointer to the device tree blob
- * @offset: offset of the property to retrieve
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_property_by_offset() retrieves a pointer to the
- * fdt_property structure within the device tree blob at the given
- * offset.  If lenp is non-NULL, the length of the property value is
- * also returned, in the integer pointed to by lenp.
- *
- * Note that this code only works on device tree versions >= 16. fdt_getprop()
- * works on all versions.
- *
- * returns:
- *  pointer to the structure representing the property
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
-                              int offset,
-                              int *lenp);
-
-/**
- * fdt_get_property_namelen - find a property based on substring
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @namelen: number of characters of name to consider
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * Identical to fdt_get_property(), but only examine the first namelen
- * characters of name for matching the property name.
- */
-#ifndef SWIG /* Not available in Python */
-const struct fdt_property *fdt_get_property_namelen(const void *fdt,
-                            int nodeoffset,
-                            const char *name,
-                            int namelen, int *lenp);
-#endif
-
-/**
- * fdt_get_property - find a given property in a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_get_property() retrieves a pointer to the fdt_property
- * structure within the device tree blob corresponding to the property
- * named 'name' of the node at offset nodeoffset.  If lenp is
- * non-NULL, the length of the property value is also returned, in the
- * integer pointed to by lenp.
- *
- * returns:
- *  pointer to the structure representing the property
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_NOTFOUND, node does not have named property
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- *          tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-const struct fdt_property *fdt_get_property(const void *fdt, int nodeoffset,
-                        const char *name, int *lenp);
-static inline struct fdt_property *fdt_get_property_w(void *fdt, int nodeoffset,
-                              const char *name,
-                              int *lenp)
-{
-    return (struct fdt_property *)(uintptr_t)
-        fdt_get_property(fdt, nodeoffset, name, lenp);
-}
-
-/**
- * fdt_getprop_by_offset - retrieve the value of a property at a given offset
- * @fdt: pointer to the device tree blob
- * @offset: offset of the property to read
- * @namep: pointer to a string variable (will be overwritten) or NULL
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_getprop_by_offset() retrieves a pointer to the value of the
- * property at structure block offset 'offset' (this will be a pointer
- * to within the device blob itself, not a copy of the value).  If
- * lenp is non-NULL, the length of the property value is also
- * returned, in the integer pointed to by lenp.  If namep is non-NULL,
- * the property's namne will also be returned in the char * pointed to
- * by namep (this will be a pointer to within the device tree's string
- * block, not a new copy of the name).
- *
- * returns:
- *  pointer to the property's value
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *      if namep is non-NULL *namep contiains a pointer to the property
- *      name.
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_PROP tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-#ifndef SWIG /* This function is not useful in Python */
-const void *fdt_getprop_by_offset(const void *fdt, int offset,
-                  const char **namep, int *lenp);
-#endif
-
-/**
- * fdt_getprop_namelen - get property value based on substring
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @namelen: number of characters of name to consider
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * Identical to fdt_getprop(), but only examine the first namelen
- * characters of name for matching the property name.
- */
-#ifndef SWIG /* Not available in Python */
-const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
-                const char *name, int namelen, int *lenp);
-static inline void *fdt_getprop_namelen_w(void *fdt, int nodeoffset,
-                      const char *name, int namelen,
-                      int *lenp)
-{
-    return (void *)(uintptr_t)fdt_getprop_namelen(fdt, nodeoffset, name,
-                              namelen, lenp);
-}
-#endif
-
-/**
- * fdt_getprop - retrieve the value of a given property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to find
- * @name: name of the property to find
- * @lenp: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_getprop() retrieves a pointer to the value of the property
- * named 'name' of the node at offset nodeoffset (this will be a
- * pointer to within the device blob itself, not a copy of the value).
- * If lenp is non-NULL, the length of the property value is also
- * returned, in the integer pointed to by lenp.
- *
- * returns:
- *  pointer to the property's value
- *      if lenp is non-NULL, *lenp contains the length of the property
- *      value (>=0)
- *  NULL, on error
- *      if lenp is non-NULL, *lenp contains an error code (<0):
- *      -FDT_ERR_NOTFOUND, node does not have named property
- *      -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE
- *          tag
- *      -FDT_ERR_BADMAGIC,
- *      -FDT_ERR_BADVERSION,
- *      -FDT_ERR_BADSTATE,
- *      -FDT_ERR_BADSTRUCTURE,
- *      -FDT_ERR_TRUNCATED, standard meanings
- */
-const void *fdt_getprop(const void *fdt, int nodeoffset,
-            const char *name, int *lenp);
-static inline void *fdt_getprop_w(void *fdt, int nodeoffset,
-                  const char *name, int *lenp)
-{
-    return (void *)(uintptr_t)fdt_getprop(fdt, nodeoffset, name, lenp);
-}
-
-/**
- * fdt_get_phandle - retrieve the phandle of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of the node
- *
- * fdt_get_phandle() retrieves the phandle of the device tree node at
- * structure block offset nodeoffset.
- *
- * returns:
- *  the phandle of the node at nodeoffset, on success (!= 0, != -1)
- *  0, if the node has no phandle, or another error occurs
- */
-uint32_t fdt_get_phandle(const void *fdt, int nodeoffset);
-
-/**
- * fdt_get_alias_namelen - get alias based on substring
- * @fdt: pointer to the device tree blob
- * @name: name of the alias th look up
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_get_alias(), but only examine the first namelen
- * characters of name for matching the alias name.
- */
-#ifndef SWIG /* Not available in Python */
-const char *fdt_get_alias_namelen(const void *fdt,
-                  const char *name, int namelen);
-#endif
-
-/**
- * fdt_get_alias - retrieve the path referenced by a given alias
- * @fdt: pointer to the device tree blob
- * @name: name of the alias th look up
- *
- * fdt_get_alias() retrieves the value of a given alias.  That is, the
- * value of the property named 'name' in the node /aliases.
- *
- * returns:
- *  a pointer to the expansion of the alias named 'name', if it exists
- *  NULL, if the given alias or the /aliases node does not exist
- */
-const char *fdt_get_alias(const void *fdt, const char *name);
-
-/**
- * fdt_get_path - determine the full path of a node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose path to find
- * @buf: character buffer to contain the returned path (will be overwritten)
- * @buflen: size of the character buffer at buf
- *
- * fdt_get_path() computes the full path of the node at offset
- * nodeoffset, and records that path in the buffer at buf.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- *  0, on success
- *      buf contains the absolute path of the node at
- *      nodeoffset, as a NUL-terminated string.
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_NOSPACE, the path of the given node is longer than (bufsize-1)
- *      characters and will not fit in the given buffer.
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen);
-
-/**
- * fdt_supernode_atdepth_offset - find a specific ancestor of a node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- * @supernodedepth: depth of the ancestor to find
- * @nodedepth: pointer to an integer variable (will be overwritten) or NULL
- *
- * fdt_supernode_atdepth_offset() finds an ancestor of the given node
- * at a specific depth from the root (where the root itself has depth
- * 0, its immediate subnodes depth 1 and so forth).  So
- *  fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, NULL);
- * will always return 0, the offset of the root node.  If the node at
- * nodeoffset has depth D, then:
- *  fdt_supernode_atdepth_offset(fdt, nodeoffset, D, NULL);
- * will return nodeoffset itself.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- *  structure block offset of the node at node offset's ancestor
- *      of depth supernodedepth (>=0), on success
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_NOTFOUND, supernodedepth was greater than the depth of
- *      nodeoffset
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
-                 int supernodedepth, int *nodedepth);
-
-/**
- * fdt_node_depth - find the depth of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- *
- * fdt_node_depth() finds the depth of a given node.  The root node
- * has depth 0, its immediate subnodes depth 1 and so forth.
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset.
- *
- * returns:
- *  depth of the node at nodeoffset (>=0), on success
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_depth(const void *fdt, int nodeoffset);
-
-/**
- * fdt_parent_offset - find the parent of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose parent to find
- *
- * fdt_parent_offset() locates the parent node of a given node (that
- * is, it finds the offset of the node which contains the node at
- * nodeoffset as a subnode).
- *
- * NOTE: This function is expensive, as it must scan the device tree
- * structure from the start to nodeoffset, *twice*.
- *
- * returns:
- *  structure block offset of the parent of the node at nodeoffset
- *      (>=0), on success
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_parent_offset(const void *fdt, int nodeoffset);
-
-/**
- * fdt_node_offset_by_prop_value - find nodes with a given property value
- * @fdt: pointer to the device tree blob
- * @startoffset: only find nodes after this offset
- * @propname: property name to check
- * @propval: property value to search for
- * @proplen: length of the value in propval
- *
- * fdt_node_offset_by_prop_value() returns the offset of the first
- * node after startoffset, which has a property named propname whose
- * value is of length proplen and has value equal to propval; or if
- * startoffset is -1, the very first such node in the tree.
- *
- * To iterate through all nodes matching the criterion, the following
- * idiom can be used:
- *  offset = fdt_node_offset_by_prop_value(fdt, -1, propname,
- *                         propval, proplen);
- *  while (offset != -FDT_ERR_NOTFOUND) {
- *      // other code here
- *      offset = fdt_node_offset_by_prop_value(fdt, offset, propname,
- *                             propval, proplen);
- *  }
- *
- * Note the -1 in the first call to the function, if 0 is used here
- * instead, the function will never locate the root node, even if it
- * matches the criterion.
- *
- * returns:
- *  structure block offset of the located node (>= 0, >startoffset),
- *       on success
- *  -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
- *      tree after startoffset
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
-                  const char *propname,
-                  const void *propval, int proplen);
-
-/**
- * fdt_node_offset_by_phandle - find the node with a given phandle
- * @fdt: pointer to the device tree blob
- * @phandle: phandle value
- *
- * fdt_node_offset_by_phandle() returns the offset of the node
- * which has the given phandle value.  If there is more than one node
- * in the tree with the given phandle (an invalid tree), results are
- * undefined.
- *
- * returns:
- *  structure block offset of the located node (>= 0), on success
- *  -FDT_ERR_NOTFOUND, no node with that phandle exists
- *  -FDT_ERR_BADPHANDLE, given phandle value was invalid (0 or -1)
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle);
-
-/**
- * fdt_node_check_compatible: check a node's compatible property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @compatible: string to match against
- *
- *
- * fdt_node_check_compatible() returns 0 if the given node contains a
- * 'compatible' property with the given string as one of its elements,
- * it returns non-zero otherwise, or on error.
- *
- * returns:
- *  0, if the node has a 'compatible' property listing the given string
- *  1, if the node has a 'compatible' property, but it does not list
- *      the given string
- *  -FDT_ERR_NOTFOUND, if the given node has no 'compatible' property
- *  -FDT_ERR_BADOFFSET, if nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_check_compatible(const void *fdt, int nodeoffset,
-                  const char *compatible);
-
-/**
- * fdt_node_offset_by_compatible - find nodes with a given 'compatible' value
- * @fdt: pointer to the device tree blob
- * @startoffset: only find nodes after this offset
- * @compatible: 'compatible' string to match against
- *
- * fdt_node_offset_by_compatible() returns the offset of the first
- * node after startoffset, which has a 'compatible' property which
- * lists the given compatible string; or if startoffset is -1, the
- * very first such node in the tree.
- *
- * To iterate through all nodes matching the criterion, the following
- * idiom can be used:
- *  offset = fdt_node_offset_by_compatible(fdt, -1, compatible);
- *  while (offset != -FDT_ERR_NOTFOUND) {
- *      // other code here
- *      offset = fdt_node_offset_by_compatible(fdt, offset, compatible);
- *  }
- *
- * Note the -1 in the first call to the function, if 0 is used here
- * instead, the function will never locate the root node, even if it
- * matches the criterion.
- *
- * returns:
- *  structure block offset of the located node (>= 0, >startoffset),
- *       on success
- *  -FDT_ERR_NOTFOUND, no node matching the criterion exists in the
- *      tree after startoffset
- *  -FDT_ERR_BADOFFSET, nodeoffset does not refer to a BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE, standard meanings
- */
-int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
-                  const char *compatible);
-
-/**
- * fdt_stringlist_contains - check a string list property for a string
- * @strlist: Property containing a list of strings to check
- * @listlen: Length of property
- * @str: String to search for
- *
- * This is a utility function provided for convenience. The list contains
- * one or more strings, each terminated by \0, as is found in a device tree
- * "compatible" property.
- *
- * @return: 1 if the string is found in the list, 0 not found, or invalid list
- */
-int fdt_stringlist_contains(const char *strlist, int listlen, const char *str);
-
-/**
- * fdt_stringlist_count - count the number of strings in a string list
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @return:
- *   the number of strings in the given property
- *   -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- *   -FDT_ERR_NOTFOUND if the property does not exist
- */
-int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property);
-
-/**
- * fdt_stringlist_search - find a string in a string list and return its index
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @string: string to look up in the string list
- *
- * Note that it is possible for this function to succeed on property values
- * that are not NUL-terminated. That's because the function will stop after
- * finding the first occurrence of @string. This can for example happen with
- * small-valued cell properties, such as #address-cells, when searching for
- * the empty string.
- *
- * @return:
- *   the index of the string in the list of strings
- *   -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- *   -FDT_ERR_NOTFOUND if the property does not exist or does not contain
- *                     the given string
- */
-int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
-              const char *string);
-
-/**
- * fdt_stringlist_get() - obtain the string at a given index in a string list
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of a tree node
- * @property: name of the property containing the string list
- * @index: index of the string to return
- * @lenp: return location for the string length or an error code on failure
- *
- * Note that this will successfully extract strings from properties with
- * non-NUL-terminated values. For example on small-valued cell properties
- * this function will return the empty string.
- *
- * If non-NULL, the length of the string (on success) or a negative error-code
- * (on failure) will be stored in the integer pointer to by lenp.
- *
- * @return:
- *   A pointer to the string at the given index in the string list or NULL on
- *   failure. On success the length of the string will be stored in the memory
- *   location pointed to by the lenp parameter, if non-NULL. On failure one of
- *   the following negative error codes will be returned in the lenp parameter
- *   (if non-NULL):
- *     -FDT_ERR_BADVALUE if the property value is not NUL-terminated
- *     -FDT_ERR_NOTFOUND if the property does not exist
- */
-const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
-                   const char *property, int index,
-                   int *lenp);
-
-/**********************************************************************/
-/* Read-only functions (addressing related)                           */
-/**********************************************************************/
-
-/**
- * FDT_MAX_NCELLS - maximum value for #address-cells and #size-cells
- *
- * This is the maximum value for #address-cells, #size-cells and
- * similar properties that will be processed by libfdt.  IEE1275
- * requires that OF implementations handle values up to 4.
- * Implementations may support larger values, but in practice higher
- * values aren't used.
- */
-#define FDT_MAX_NCELLS      4
-
-/**
- * fdt_address_cells - retrieve address size for a bus represented in the tree
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to find the address size for
- *
- * When the node has a valid #address-cells property, returns its value.
- *
- * returns:
- *  0 <= n < FDT_MAX_NCELLS, on success
- *      2, if the node has no #address-cells property
- *      -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
- *      #address-cells property
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_address_cells(const void *fdt, int nodeoffset);
-
-/**
- * fdt_size_cells - retrieve address range size for a bus represented in the
- *                  tree
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to find the address range size for
- *
- * When the node has a valid #size-cells property, returns its value.
- *
- * returns:
- *  0 <= n < FDT_MAX_NCELLS, on success
- *      1, if the node has no #size-cells property
- *      -FDT_ERR_BADNCELLS, if the node has a badly formatted or invalid
- *      #size-cells property
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_size_cells(const void *fdt, int nodeoffset);
-
-
-/**********************************************************************/
-/* Write-in-place functions                                           */
-/**********************************************************************/
-
-/**
- * fdt_setprop_inplace_namelen_partial - change a property's value,
- *                                       but not its size
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @namelen: number of characters of name to consider
- * @idx: index of the property to change in the array
- * @val: pointer to data to replace the property value with
- * @len: length of the property value
- *
- * Identical to fdt_setprop_inplace(), but modifies the given property
- * starting from the given index, and using only the first characters
- * of the name. It is useful when you want to manipulate only one value of
- * an array and you have a string that doesn't end with \0.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
-                    const char *name, int namelen,
-                    uint32_t idx, const void *val,
-                    int len);
-#endif
-
-/**
- * fdt_setprop_inplace - change a property's value, but not its size
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: pointer to data to replace the property value with
- * @len: length of the property value
- *
- * fdt_setprop_inplace() replaces the value of a given property with
- * the data in val, of length len.  This function cannot change the
- * size of a property, and so will only work if len is equal to the
- * current length of the property.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, if len is not equal to the property's current length
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
-            const void *val, int len);
-#endif
-
-/**
- * fdt_setprop_inplace_u32 - change the value of a 32-bit integer property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value to replace the property with
- *
- * fdt_setprop_inplace_u32() replaces the value of a given property
- * with the 32-bit integer value in val, converting val to big-endian
- * if necessary.  This function cannot change the size of a property,
- * and so will only work if the property already exists and has length
- * 4.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, if the property's length is not equal to 4
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_inplace_u32(void *fdt, int nodeoffset,
-                      const char *name, uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_inplace_u64 - change the value of a 64-bit integer property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value to replace the property with
- *
- * fdt_setprop_inplace_u64() replaces the value of a given property
- * with the 64-bit integer value in val, converting val to big-endian
- * if necessary.  This function cannot change the size of a property,
- * and so will only work if the property already exists and has length
- * 8.
- *
- * This function will alter only the bytes in the blob which contain
- * the given property value, and will not alter or move any other part
- * of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, if the property's length is not equal to 8
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_inplace_u64(void *fdt, int nodeoffset,
-                      const char *name, uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_setprop_inplace(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_inplace_cell - change the value of a single-cell property
- *
- * This is an alternative name for fdt_setprop_inplace_u32()
- */
-static inline int fdt_setprop_inplace_cell(void *fdt, int nodeoffset,
-                       const char *name, uint32_t val)
-{
-    return fdt_setprop_inplace_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_nop_property - replace a property with nop tags
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to nop
- * @name: name of the property to nop
- *
- * fdt_nop_property() will replace a given property's representation
- * in the blob with FDT_NOP tags, effectively removing it from the
- * tree.
- *
- * This function will alter only the bytes in the blob which contain
- * the property, and will not alter or move any other part of the
- * tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_nop_property(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_nop_node - replace a node (subtree) with nop tags
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to nop
- *
- * fdt_nop_node() will replace a given node's representation in the
- * blob, including all its subnodes, if any, with FDT_NOP tags,
- * effectively removing it from the tree.
- *
- * This function will alter only the bytes in the blob which contain
- * the node and its properties and subnodes, and will not alter or
- * move any other part of the tree.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_nop_node(void *fdt, int nodeoffset);
-
-/**********************************************************************/
-/* Sequential write functions                                         */
-/**********************************************************************/
-
-int fdt_create(void *buf, int bufsize);
-int fdt_resize(void *fdt, void *buf, int bufsize);
-int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size);
-int fdt_finish_reservemap(void *fdt);
-int fdt_begin_node(void *fdt, const char *name);
-int fdt_property(void *fdt, const char *name, const void *val, int len);
-static inline int fdt_property_u32(void *fdt, const char *name, uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_property(fdt, name, &tmp, sizeof(tmp));
-}
-static inline int fdt_property_u64(void *fdt, const char *name, uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_property(fdt, name, &tmp, sizeof(tmp));
-}
-
-#ifndef SWIG /* Not available in Python */
-static inline int fdt_property_cell(void *fdt, const char *name, uint32_t val)
-{
-    return fdt_property_u32(fdt, name, val);
-}
-#endif
-
-/**
- * fdt_property_placeholder - add a new property and return a ptr to its value
- *
- * @fdt: pointer to the device tree blob
- * @name: name of property to add
- * @len: length of property value in bytes
- * @valp: returns a pointer to where where the value should be placed
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_NOSPACE, standard meanings
- */
-int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp);
-
-#define fdt_property_string(fdt, name, str) \
-    fdt_property(fdt, name, str, strlen(str)+1)
-int fdt_end_node(void *fdt);
-int fdt_finish(void *fdt);
-
-/**********************************************************************/
-/* Read-write functions                                               */
-/**********************************************************************/
-
-int fdt_create_empty_tree(void *buf, int bufsize);
-int fdt_open_into(const void *fdt, void *buf, int bufsize);
-int fdt_pack(void *fdt);
-
-/**
- * fdt_add_mem_rsv - add one memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @address, @size: 64-bit values (native endian)
- *
- * Adds a reserve map entry to the given blob reserving a region at
- * address address of length size.
- *
- * This function will insert data into the reserve map and will
- * therefore change the indexes of some entries in the table.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new reservation entry
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size);
-
-/**
- * fdt_del_mem_rsv - remove a memory reserve map entry
- * @fdt: pointer to the device tree blob
- * @n: entry to remove
- *
- * fdt_del_mem_rsv() removes the n-th memory reserve map entry from
- * the blob.
- *
- * This function will delete data from the reservation table and will
- * therefore change the indexes of some entries in the table.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOTFOUND, there is no entry of the given index (i.e. there
- *      are less than n+1 reserve map entries)
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_del_mem_rsv(void *fdt, int n);
-
-/**
- * fdt_set_name - change the name of a given node
- * @fdt: pointer to the device tree blob
- * @nodeoffset: structure block offset of a node
- * @name: name to give the node
- *
- * fdt_set_name() replaces the name (including unit address, if any)
- * of the given node with the given string.  NOTE: this function can't
- * efficiently check if the new name is unique amongst the given
- * node's siblings; results are undefined if this function is invoked
- * with a name equal to one of the given node's siblings.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob
- *      to contain the new name
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE, standard meanings
- */
-int fdt_set_name(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_setprop - create or change a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: pointer to data to set the property value to
- * @len: length of the property value
- *
- * fdt_setprop() sets the value of the named property in the given
- * node to the given value and length, creating the property if it
- * does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
-        const void *val, int len);
-
-/**
- * fdt_setprop_placeholder - allocate space for a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @len: length of the property value
- * @prop_data: return pointer to property data
- *
- * fdt_setprop_placeholer() allocates the named property in the given node.
- * If the property exists it is resized. In either case a pointer to the
- * property data is returned.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
-                int len, void **prop_data);
-
-/**
- * fdt_setprop_u32 - set a property to a 32-bit integer
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value for the property (native endian)
- *
- * fdt_setprop_u32() sets the value of the named property in the given
- * node to the given 32-bit integer value (converting to big-endian if
- * necessary), or creates a new property with that value if it does
- * not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_u32(void *fdt, int nodeoffset, const char *name,
-                  uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_u64 - set a property to a 64-bit integer
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value for the property (native endian)
- *
- * fdt_setprop_u64() sets the value of the named property in the given
- * node to the given 64-bit integer value (converting to big-endian if
- * necessary), or creates a new property with that value if it does
- * not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_setprop_u64(void *fdt, int nodeoffset, const char *name,
-                  uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_setprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_setprop_cell - set a property to a single cell value
- *
- * This is an alternative name for fdt_setprop_u32()
- */
-static inline int fdt_setprop_cell(void *fdt, int nodeoffset, const char *name,
-                   uint32_t val)
-{
-    return fdt_setprop_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_setprop_string - set a property to a string value
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @str: string value for the property
- *
- * fdt_setprop_string() sets the value of the named property in the
- * given node to the given string value (using the length of the
- * string to determine the new length of the property), or creates a
- * new property with that value if it does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_setprop_string(fdt, nodeoffset, name, str) \
-    fdt_setprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
-
-
-/**
- * fdt_setprop_empty - set a property to an empty value
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- *
- * fdt_setprop_empty() sets the value of the named property in the
- * given node to an empty (zero length) value, or creates a new empty
- * property if it does not already exist.
- *
- * This function may insert or delete data from the blob, and will
- * therefore change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_setprop_empty(fdt, nodeoffset, name) \
-    fdt_setprop((fdt), (nodeoffset), (name), NULL, 0)
-
-/**
- * fdt_appendprop - append to or create a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to append to
- * @val: pointer to data to append to the property value
- * @len: length of the data to append to the property value
- *
- * fdt_appendprop() appends the value to the named property in the
- * given node, creating the property if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
-           const void *val, int len);
-
-/**
- * fdt_appendprop_u32 - append a 32-bit integer value to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 32-bit integer value to append to the property (native endian)
- *
- * fdt_appendprop_u32() appends the given 32-bit integer value
- * (converting to big-endian if necessary) to the value of the named
- * property in the given node, or creates a new property with that
- * value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_appendprop_u32(void *fdt, int nodeoffset,
-                     const char *name, uint32_t val)
-{
-    fdt32_t tmp = cpu_to_fdt32(val);
-    return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_appendprop_u64 - append a 64-bit integer value to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @val: 64-bit integer value to append to the property (native endian)
- *
- * fdt_appendprop_u64() appends the given 64-bit integer value
- * (converting to big-endian if necessary) to the value of the named
- * property in the given node, or creates a new property with that
- * value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-static inline int fdt_appendprop_u64(void *fdt, int nodeoffset,
-                     const char *name, uint64_t val)
-{
-    fdt64_t tmp = cpu_to_fdt64(val);
-    return fdt_appendprop(fdt, nodeoffset, name, &tmp, sizeof(tmp));
-}
-
-/**
- * fdt_appendprop_cell - append a single cell value to a property
- *
- * This is an alternative name for fdt_appendprop_u32()
- */
-static inline int fdt_appendprop_cell(void *fdt, int nodeoffset,
-                      const char *name, uint32_t val)
-{
-    return fdt_appendprop_u32(fdt, nodeoffset, name, val);
-}
-
-/**
- * fdt_appendprop_string - append a string to a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to change
- * @name: name of the property to change
- * @str: string value to append to the property
- *
- * fdt_appendprop_string() appends the given string to the value of
- * the named property in the given node, or creates a new property
- * with that value if it does not already exist.
- *
- * This function may insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there is insufficient free space in the blob to
- *      contain the new property value
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-#define fdt_appendprop_string(fdt, nodeoffset, name, str) \
-    fdt_appendprop((fdt), (nodeoffset), (name), (str), strlen(str)+1)
-
-/**
- * fdt_delprop - delete a property
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node whose property to nop
- * @name: name of the property to nop
- *
- * fdt_del_property() will delete the given property.
- *
- * This function will delete data from the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOTFOUND, node does not have the named property
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_delprop(void *fdt, int nodeoffset, const char *name);
-
-/**
- * fdt_add_subnode_namelen - creates a new node based on substring
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- * @namelen: number of characters of name to consider
- *
- * Identical to fdt_add_subnode(), but use only the first namelen
- * characters of name as the name of the new node.  This is useful for
- * creating subnodes based on a portion of a larger string, such as a
- * full path.
- */
-#ifndef SWIG /* Not available in Python */
-int fdt_add_subnode_namelen(void *fdt, int parentoffset,
-                const char *name, int namelen);
-#endif
-
-/**
- * fdt_add_subnode - creates a new node
- * @fdt: pointer to the device tree blob
- * @parentoffset: structure block offset of a node
- * @name: name of the subnode to locate
- *
- * fdt_add_subnode() creates a new node as a subnode of the node at
- * structure block offset parentoffset, with the given name (which
- * should include the unit address, if any).
- *
- * This function will insert data into the blob, and will therefore
- * change the offsets of some existing nodes.
-
- * returns:
- *  structure block offset of the created nodeequested subnode (>=0), on
- *      success
- *  -FDT_ERR_NOTFOUND, if the requested subnode does not exist
- *  -FDT_ERR_BADOFFSET, if parentoffset did not point to an FDT_BEGIN_NODE
- *      tag
- *  -FDT_ERR_EXISTS, if the node at parentoffset already has a subnode of
- *      the given name
- *  -FDT_ERR_NOSPACE, if there is insufficient free space in the
- *      blob to contain the new node
- *  -FDT_ERR_NOSPACE
- *  -FDT_ERR_BADLAYOUT
- *      -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings.
- */
-int fdt_add_subnode(void *fdt, int parentoffset, const char *name);
-
-/**
- * fdt_del_node - delete a node (subtree)
- * @fdt: pointer to the device tree blob
- * @nodeoffset: offset of the node to nop
- *
- * fdt_del_node() will remove the given node, including all its
- * subnodes if any, from the blob.
- *
- * This function will delete data from the blob, and will therefore
- * change the offsets of some existing nodes.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_BADOFFSET, nodeoffset did not point to FDT_BEGIN_NODE tag
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_del_node(void *fdt, int nodeoffset);
-
-/**
- * fdt_overlay_apply - Applies a DT overlay on a base DT
- * @fdt: pointer to the base device tree blob
- * @fdto: pointer to the device tree overlay blob
- *
- * fdt_overlay_apply() will apply the given device tree overlay on the
- * given base device tree.
- *
- * Expect the base device tree to be modified, even if the function
- * returns an error.
- *
- * returns:
- *  0, on success
- *  -FDT_ERR_NOSPACE, there's not enough space in the base device tree
- *  -FDT_ERR_NOTFOUND, the overlay points to some inexistant nodes or
- *      properties in the base DT
- *  -FDT_ERR_BADPHANDLE,
- *  -FDT_ERR_BADOVERLAY,
- *  -FDT_ERR_NOPHANDLES,
- *  -FDT_ERR_INTERNAL,
- *  -FDT_ERR_BADLAYOUT,
- *  -FDT_ERR_BADMAGIC,
- *  -FDT_ERR_BADOFFSET,
- *  -FDT_ERR_BADPATH,
- *  -FDT_ERR_BADVERSION,
- *  -FDT_ERR_BADSTRUCTURE,
- *  -FDT_ERR_BADSTATE,
- *  -FDT_ERR_TRUNCATED, standard meanings
- */
-int fdt_overlay_apply(void *fdt, void *fdto);
-
-/**********************************************************************/
-/* Debugging / informational functions                                */
-/**********************************************************************/
-
-const char *fdt_strerror(int errval);
-
-#endif /* LIBFDT_H */
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h
deleted file mode 100644
index e7a0e02f55..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_env.h
+++ /dev/null
@@ -1,169 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef LIBFDT_ENV_H
-#define LIBFDT_ENV_H
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- * Copyright 2012 Kim Phillips, Freescale Semiconductor.
- *
- * libfdt is dual licensed: you can use it either under the terms of
- * the GPL, or the BSD license, at your option.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
- *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *     MA 02110-1301 USA
- *
- * Alternatively,
- *
- *  b) Redistribution and use in source and binary forms, with or
- *     without modification, are permitted provided that the following
- *     conditions are met:
- *
- *     1. Redistributions of source code must retain the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer.
- *     2. Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials
- *        provided with the distribution.
- *
- *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
- *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#ifdef __CHECKER__
-#define FDT_FORCE __attribute__((force))
-#define FDT_BITWISE __attribute__((bitwise))
-#else
-#define FDT_FORCE
-#define FDT_BITWISE
-#endif
-
-typedef uint16_t FDT_BITWISE fdt16_t;
-typedef uint32_t FDT_BITWISE fdt32_t;
-typedef uint64_t FDT_BITWISE fdt64_t;
-
-#define EXTRACT_BYTE(x, n)  ((unsigned long long)((uint8_t *)&x)[n])
-#define CPU_TO_FDT16(x) ((EXTRACT_BYTE(x, 0) << 8) | EXTRACT_BYTE(x, 1))
-#define CPU_TO_FDT32(x) ((EXTRACT_BYTE(x, 0) << 24) | (EXTRACT_BYTE(x, 1) << 16) | \
-             (EXTRACT_BYTE(x, 2) << 8) | EXTRACT_BYTE(x, 3))
-#define CPU_TO_FDT64(x) ((EXTRACT_BYTE(x, 0) << 56) | (EXTRACT_BYTE(x, 1) << 48) | \
-             (EXTRACT_BYTE(x, 2) << 40) | (EXTRACT_BYTE(x, 3) << 32) | \
-             (EXTRACT_BYTE(x, 4) << 24) | (EXTRACT_BYTE(x, 5) << 16) | \
-             (EXTRACT_BYTE(x, 6) << 8) | EXTRACT_BYTE(x, 7))
-
-static inline uint16_t fdt16_to_cpu(fdt16_t x)
-{
-    return (FDT_FORCE uint16_t)CPU_TO_FDT16(x);
-}
-static inline fdt16_t cpu_to_fdt16(uint16_t x)
-{
-    return (FDT_FORCE fdt16_t)CPU_TO_FDT16(x);
-}
-
-static inline uint32_t fdt32_to_cpu(fdt32_t x)
-{
-    return (FDT_FORCE uint32_t)CPU_TO_FDT32(x);
-}
-static inline fdt32_t cpu_to_fdt32(uint32_t x)
-{
-    return (FDT_FORCE fdt32_t)CPU_TO_FDT32(x);
-}
-
-static inline uint64_t fdt64_to_cpu(fdt64_t x)
-{
-    return (FDT_FORCE uint64_t)CPU_TO_FDT64(x);
-}
-static inline fdt64_t cpu_to_fdt64(uint64_t x)
-{
-    return (FDT_FORCE fdt64_t)CPU_TO_FDT64(x);
-}
-#undef CPU_TO_FDT64
-#undef CPU_TO_FDT32
-#undef CPU_TO_FDT16
-#undef EXTRACT_BYTE
-
-#ifdef __APPLE__
-#include 
-
-/* strnlen() is not available on Mac OS < 10.7 */
-# if !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED < \
-                                         MAC_OS_X_VERSION_10_7)
-
-#define strnlen fdt_strnlen
-
-/*
- * fdt_strnlen: returns the length of a string or max_count - which ever is
- * smallest.
- * Input 1 string: the string whose size is to be determined
- * Input 2 max_count: the maximum value returned by this function
- * Output: length of the string or max_count (the smallest of the two)
- */
-static inline size_t fdt_strnlen(const char *string, size_t max_count)
-{
-    const char *p = memchr(string, 0, max_count);
-    return p ? p - string : max_count;
-}
-
-#endif /* !defined(MAC_OS_X_VERSION_10_7) || (MAC_OS_X_VERSION_MAX_ALLOWED <
-          MAC_OS_X_VERSION_10_7) */
-
-#endif /* __APPLE__ */
-
-#endif /* LIBFDT_ENV_H */
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h b/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h
deleted file mode 100644
index dec0382a0c..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/inc/libfdt_internal.h
+++ /dev/null
@@ -1,125 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef LIBFDT_INTERNAL_H
-#define LIBFDT_INTERNAL_H
-/*
- * libfdt - Flat Device Tree manipulation
- * Copyright (C) 2006 David Gibson, IBM Corporation.
- *
- * libfdt is dual licensed: you can use it either under the terms of
- * the GPL, or the BSD license, at your option.
- *
- *  a) This library is free software; you can redistribute it and/or
- *     modify it under the terms of the GNU General Public License as
- *     published by the Free Software Foundation; either version 2 of the
- *     License, or (at your option) any later version.
- *
- *     This library is distributed in the hope that it will be useful,
- *     but WITHOUT ANY WARRANTY; without even the implied warranty of
- *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- *     GNU General Public License for more details.
- *
- *     You should have received a copy of the GNU General Public
- *     License along with this library; if not, write to the Free
- *     Software Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
- *     MA 02110-1301 USA
- *
- * Alternatively,
- *
- *  b) Redistribution and use in source and binary forms, with or
- *     without modification, are permitted provided that the following
- *     conditions are met:
- *
- *     1. Redistributions of source code must retain the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer.
- *     2. Redistributions in binary form must reproduce the above
- *        copyright notice, this list of conditions and the following
- *        disclaimer in the documentation and/or other materials
- *        provided with the distribution.
- *
- *     THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND
- *     CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES,
- *     INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
- *     MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- *     DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
- *     CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
- *     SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
- *     NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- *     LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
- *     HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
- *     CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR
- *     OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
- *     EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-#define FDT_ALIGN(x, a)     (((x) + (a) - 1) & ~((a) - 1))
-#define FDT_TAGALIGN(x)     (FDT_ALIGN((x), FDT_TAGSIZE))
-
-int fdt_ro_probe_(const void *fdt);
-#define FDT_RO_PROBE(fdt)           \
-    { \
-        int err_; \
-        if ((err_ = fdt_ro_probe_(fdt)) != 0)   \
-            return err_; \
-    }
-
-int fdt_check_node_offset_(const void *fdt, int offset);
-int fdt_check_prop_offset_(const void *fdt, int offset);
-const char *fdt_find_string_(const char *strtab, int tabsize, const char *s);
-int fdt_node_end_offset_(void *fdt, int nodeoffset);
-
-static inline const void *fdt_offset_ptr_(const void *fdt, int offset)
-{
-    return (const char *)fdt + fdt_off_dt_struct(fdt) + offset;
-}
-
-static inline void *fdt_offset_ptr_w_(void *fdt, int offset)
-{
-    return (void *)(uintptr_t)fdt_offset_ptr_(fdt, offset);
-}
-
-static inline const struct fdt_reserve_entry *fdt_mem_rsv_(const void *fdt, int n)
-{
-    const struct fdt_reserve_entry *rsv_table =
-        (const struct fdt_reserve_entry *)
-        ((const char *)fdt + fdt_off_mem_rsvmap(fdt));
-
-    return rsv_table + n;
-}
-static inline struct fdt_reserve_entry *fdt_mem_rsv_w_(void *fdt, int n)
-{
-    return (void *)(uintptr_t)fdt_mem_rsv_(fdt, n);
-}
-
-#define FDT_SW_MAGIC        (~FDT_MAGIC)
-
-#endif /* LIBFDT_INTERNAL_H */
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c
deleted file mode 100644
index f77dc17a6c..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt.c
+++ /dev/null
@@ -1,310 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-/*
- * Minimal sanity check for a read-only tree. fdt_ro_probe_() checks
- * that the given buffer contains what appears to be a flattened
- * device tree with sane information in its header.
- */
-int fdt_ro_probe_(const void *fdt)
-{
-    if (fdt_magic(fdt) == FDT_MAGIC) {
-        /* Complete tree */
-        if (fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
-            return -FDT_ERR_BADVERSION;
-        if (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION)
-            return -FDT_ERR_BADVERSION;
-    } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
-        /* Unfinished sequential-write blob */
-        if (fdt_size_dt_struct(fdt) == 0)
-            return -FDT_ERR_BADSTATE;
-    } else {
-        return -FDT_ERR_BADMAGIC;
-    }
-
-    return 0;
-}
-
-static int check_off_(uint32_t hdrsize, uint32_t totalsize, uint32_t off)
-{
-    return (off >= hdrsize) && (off <= totalsize);
-}
-
-static int check_block_(uint32_t hdrsize, uint32_t totalsize,
-            uint32_t base, uint32_t size)
-{
-    if (!check_off_(hdrsize, totalsize, base))
-        return 0; /* block start out of bounds */
-    if ((base + size) < base)
-        return 0; /* overflow */
-    if (!check_off_(hdrsize, totalsize, base + size))
-        return 0; /* block end out of bounds */
-    return 1;
-}
-
-size_t fdt_header_size_(uint32_t version)
-{
-    if (version <= 1)
-        return FDT_V1_SIZE;
-    else if (version <= 2)
-        return FDT_V2_SIZE;
-    else if (version <= 3)
-        return FDT_V3_SIZE;
-    else if (version <= 16)
-        return FDT_V16_SIZE;
-    else
-        return FDT_V17_SIZE;
-}
-
-int fdt_check_header(const void *fdt)
-{
-    size_t hdrsize;
-
-    if (fdt_magic(fdt) != FDT_MAGIC)
-        return -FDT_ERR_BADMAGIC;
-    hdrsize = fdt_header_size(fdt);
-    if ((fdt_version(fdt) < FDT_FIRST_SUPPORTED_VERSION)
-        || (fdt_last_comp_version(fdt) > FDT_LAST_SUPPORTED_VERSION))
-        return -FDT_ERR_BADVERSION;
-    if (fdt_version(fdt) < fdt_last_comp_version(fdt))
-        return -FDT_ERR_BADVERSION;
-
-    if ((fdt_totalsize(fdt) < hdrsize)
-        || (fdt_totalsize(fdt) > INT_MAX))
-        return -FDT_ERR_TRUNCATED;
-
-    /* Bounds check memrsv block */
-    if (!check_off_(hdrsize, fdt_totalsize(fdt), fdt_off_mem_rsvmap(fdt)))
-        return -FDT_ERR_TRUNCATED;
-
-    /* Bounds check structure block */
-    if (fdt_version(fdt) < 17) {
-        if (!check_off_(hdrsize, fdt_totalsize(fdt),
-                fdt_off_dt_struct(fdt)))
-            return -FDT_ERR_TRUNCATED;
-    } else {
-        if (!check_block_(hdrsize, fdt_totalsize(fdt),
-                  fdt_off_dt_struct(fdt),
-                  fdt_size_dt_struct(fdt)))
-            return -FDT_ERR_TRUNCATED;
-    }
-
-    /* Bounds check strings block */
-    if (!check_block_(hdrsize, fdt_totalsize(fdt),
-              fdt_off_dt_strings(fdt), fdt_size_dt_strings(fdt)))
-        return -FDT_ERR_TRUNCATED;
-
-    return 0;
-}
-
-const void *fdt_offset_ptr(const void *fdt, int offset, unsigned int len)
-{
-    unsigned absoffset = offset + fdt_off_dt_struct(fdt);
-
-    if ((absoffset < offset)
-        || ((absoffset + len) < absoffset)
-        || (absoffset + len) > fdt_totalsize(fdt))
-        return NULL;
-
-    if (fdt_version(fdt) >= 0x11)
-        if (((offset + len) < offset)
-            || ((offset + len) > fdt_size_dt_struct(fdt)))
-            return NULL;
-
-    return fdt_offset_ptr_(fdt, offset);
-}
-
-uint32_t fdt_next_tag(const void *fdt, int startoffset, int *nextoffset)
-{
-    const fdt32_t *tagp, *lenp;
-    uint32_t tag;
-    int offset = startoffset;
-    const char *p;
-
-    *nextoffset = -FDT_ERR_TRUNCATED;
-    tagp = fdt_offset_ptr(fdt, offset, FDT_TAGSIZE);
-    if (!tagp)
-        return FDT_END; /* premature end */
-    tag = fdt32_to_cpu(*tagp);
-    offset += FDT_TAGSIZE;
-
-    *nextoffset = -FDT_ERR_BADSTRUCTURE;
-    switch (tag) {
-    case FDT_BEGIN_NODE:
-        /* skip name */
-        do {
-            p = fdt_offset_ptr(fdt, offset++, 1);
-        } while (p && (*p != '\0'));
-        if (!p)
-            return FDT_END; /* premature end */
-        break;
-
-    case FDT_PROP:
-        lenp = fdt_offset_ptr(fdt, offset, sizeof(*lenp));
-        if (!lenp)
-            return FDT_END; /* premature end */
-        /* skip-name offset, length and value */
-        offset += sizeof(struct fdt_property) - FDT_TAGSIZE
-            + fdt32_to_cpu(*lenp);
-        if (fdt_version(fdt) < 0x10 && fdt32_to_cpu(*lenp) >= 8 &&
-            ((offset - fdt32_to_cpu(*lenp)) % 8) != 0)
-            offset += 4;
-        break;
-
-    case FDT_END:
-    case FDT_END_NODE:
-    case FDT_NOP:
-        break;
-
-    default:
-        return FDT_END;
-    }
-
-    if (!fdt_offset_ptr(fdt, startoffset, offset - startoffset))
-        return FDT_END; /* premature end */
-
-    *nextoffset = FDT_TAGALIGN(offset);
-    return tag;
-}
-
-int fdt_check_node_offset_(const void *fdt, int offset)
-{
-    if ((offset < 0) || (offset % FDT_TAGSIZE)
-        || (fdt_next_tag(fdt, offset, &offset) != FDT_BEGIN_NODE))
-        return -FDT_ERR_BADOFFSET;
-
-    return offset;
-}
-
-int fdt_check_prop_offset_(const void *fdt, int offset)
-{
-    if ((offset < 0) || (offset % FDT_TAGSIZE)
-        || (fdt_next_tag(fdt, offset, &offset) != FDT_PROP))
-        return -FDT_ERR_BADOFFSET;
-
-    return offset;
-}
-
-int fdt_next_node(const void *fdt, int offset, int *depth)
-{
-    int nextoffset = 0;
-    uint32_t tag;
-
-    if (offset >= 0)
-        if ((nextoffset = fdt_check_node_offset_(fdt, offset)) < 0)
-            return nextoffset;
-
-    do {
-        offset = nextoffset;
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-        switch (tag) {
-        case FDT_PROP:
-        case FDT_NOP:
-            break;
-
-        case FDT_BEGIN_NODE:
-            if (depth)
-                (*depth)++;
-            break;
-
-        case FDT_END_NODE:
-            if (depth && ((--(*depth)) < 0))
-                return nextoffset;
-            break;
-
-        case FDT_END:
-            if ((nextoffset >= 0)
-                || ((nextoffset == -FDT_ERR_TRUNCATED) && !depth))
-                return -FDT_ERR_NOTFOUND;
-            else
-                return nextoffset;
-        }
-    } while (tag != FDT_BEGIN_NODE);
-
-    return offset;
-}
-
-int fdt_first_subnode(const void *fdt, int offset)
-{
-    int depth = 0;
-
-    offset = fdt_next_node(fdt, offset, &depth);
-    if (offset < 0 || depth != 1)
-        return -FDT_ERR_NOTFOUND;
-
-    return offset;
-}
-
-int fdt_next_subnode(const void *fdt, int offset)
-{
-    int depth = 1;
-
-    /*
-     * With respect to the parent, the depth of the next subnode will be
-     * the same as the last.
-     */
-    do {
-        offset = fdt_next_node(fdt, offset, &depth);
-        if (offset < 0 || depth < 1)
-            return -FDT_ERR_NOTFOUND;
-    } while (depth > 1);
-
-    return offset;
-}
-
-const char *fdt_find_string_(const char *strtab, int tabsize, const char *s)
-{
-    int len = strlen(s) + 1;
-    const char *last = strtab + tabsize - len;
-    const char *p;
-
-    for (p = strtab; p <= last; p++)
-        if (memcmp(p, s, len) == 0)
-            return p;
-    return NULL;
-}
-
-int fdt_move(const void *fdt, void *buf, int bufsize)
-{
-    FDT_RO_PROBE(fdt);
-
-    if (fdt_totalsize(fdt) > bufsize)
-        return -FDT_ERR_NOSPACE;
-
-    memmove(buf, fdt, fdt_totalsize(fdt));
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c
deleted file mode 100644
index c854c90e12..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_addresses.c
+++ /dev/null
@@ -1,75 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_cells(const void *fdt, int nodeoffset, const char *name)
-{
-    const fdt32_t *c;
-    int val;
-    int len;
-
-    c = fdt_getprop(fdt, nodeoffset, name, &len);
-    if (!c)
-        return len;
-
-    if (len != sizeof(*c))
-        return -FDT_ERR_BADNCELLS;
-
-    val = fdt32_to_cpu(*c);
-    if ((val <= 0) || (val > FDT_MAX_NCELLS))
-        return -FDT_ERR_BADNCELLS;
-
-    return val;
-}
-
-int fdt_address_cells(const void *fdt, int nodeoffset)
-{
-    int val;
-
-    val = fdt_cells(fdt, nodeoffset, "#address-cells");
-    if (val == -FDT_ERR_NOTFOUND)
-        return 2;
-    return val;
-}
-
-int fdt_size_cells(const void *fdt, int nodeoffset)
-{
-    int val;
-
-    val = fdt_cells(fdt, nodeoffset, "#size-cells");
-    if (val == -FDT_ERR_NOTFOUND)
-        return 1;
-    return val;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c
deleted file mode 100644
index 8c9a9f5e57..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_empty_tree.c
+++ /dev/null
@@ -1,62 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-int fdt_create_empty_tree(void *buf, int bufsize)
-{
-    int err;
-
-    err = fdt_create(buf, bufsize);
-    if (err)
-        return err;
-
-    err = fdt_finish_reservemap(buf);
-    if (err)
-        return err;
-
-    err = fdt_begin_node(buf, "");
-    if (err)
-        return err;
-
-    err =  fdt_end_node(buf);
-    if (err)
-        return err;
-
-    err = fdt_finish(buf);
-    if (err)
-        return err;
-
-    return fdt_open_into(buf, buf, bufsize);
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c
deleted file mode 100644
index e7d14b1e4c..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_overlay.c
+++ /dev/null
@@ -1,890 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-/**
- * overlay_get_target_phandle - retrieves the target phandle of a fragment
- * @fdto: pointer to the device tree overlay blob
- * @fragment: node offset of the fragment in the overlay
- *
- * overlay_get_target_phandle() retrieves the target phandle of an
- * overlay fragment when that fragment uses a phandle (target
- * property) instead of a path (target-path property).
- *
- * returns:
- *      the phandle pointed by the target property
- *      0, if the phandle was not found
- *  -1, if the phandle was malformed
- */
-static uint32_t overlay_get_target_phandle(const void *fdto, int fragment)
-{
-    const fdt32_t *val;
-    int len;
-
-    val = fdt_getprop(fdto, fragment, "target", &len);
-    if (!val)
-        return 0;
-
-    if ((len != sizeof(*val)) || (fdt32_to_cpu(*val) == (uint32_t)-1))
-        return (uint32_t)-1;
-
-    return fdt32_to_cpu(*val);
-}
-
-/**
- * overlay_get_target - retrieves the offset of a fragment's target
- * @fdt: Base device tree blob
- * @fdto: Device tree overlay blob
- * @fragment: node offset of the fragment in the overlay
- * @pathp: pointer which receives the path of the target (or NULL)
- *
- * overlay_get_target() retrieves the target offset in the base
- * device tree of a fragment, no matter how the actual targetting is
- * done (through a phandle or a path)
- *
- * returns:
- *      the targetted node offset in the base device tree
- *      Negative error code on error
- */
-static int overlay_get_target(const void *fdt, const void *fdto,
-                  int fragment, char const **pathp)
-{
-    uint32_t phandle;
-    const char *path = NULL;
-    int path_len = 0, ret;
-
-    /* Try first to do a phandle based lookup */
-    phandle = overlay_get_target_phandle(fdto, fragment);
-    if (phandle == (uint32_t)-1)
-        return -FDT_ERR_BADPHANDLE;
-
-    /* no phandle, try path */
-    if (!phandle) {
-        /* And then a path based lookup */
-        path = fdt_getprop(fdto, fragment, "target-path", &path_len);
-        if (path)
-            ret = fdt_path_offset(fdt, path);
-        else
-            ret = path_len;
-    } else
-        ret = fdt_node_offset_by_phandle(fdt, phandle);
-
-    /*
-    * If we haven't found either a target or a
-    * target-path property in a node that contains a
-    * __overlay__ subnode (we wouldn't be called
-    * otherwise), consider it a improperly written
-    * overlay
-    */
-    if (ret < 0 && path_len == -FDT_ERR_NOTFOUND)
-        ret = -FDT_ERR_BADOVERLAY;
-
-    /* return on error */
-    if (ret < 0)
-        return ret;
-
-    /* return pointer to path (if available) */
-    if (pathp)
-        *pathp = path ? path : NULL;
-
-    return ret;
-}
-
-/**
- * overlay_phandle_add_offset - Increases a phandle by an offset
- * @fdt: Base device tree blob
- * @node: Device tree overlay blob
- * @name: Name of the property to modify (phandle or linux,phandle)
- * @delta: offset to apply
- *
- * overlay_phandle_add_offset() increments a node phandle by a given
- * offset.
- *
- * returns:
- *      0 on success.
- *      Negative error code on error
- */
-static int overlay_phandle_add_offset(void *fdt, int node,
-                      const char *name, uint32_t delta)
-{
-    const fdt32_t *val;
-    uint32_t adj_val;
-    int len;
-
-    val = fdt_getprop(fdt, node, name, &len);
-    if (!val)
-        return len;
-
-    if (len != sizeof(*val))
-        return -FDT_ERR_BADPHANDLE;
-
-    adj_val = fdt32_to_cpu(*val);
-    if ((adj_val + delta) < adj_val)
-        return -FDT_ERR_NOPHANDLES;
-
-    adj_val += delta;
-    if (adj_val == (uint32_t)-1)
-        return -FDT_ERR_NOPHANDLES;
-
-    return fdt_setprop_inplace_u32(fdt, node, name, adj_val);
-}
-
-/**
- * overlay_adjust_node_phandles - Offsets the phandles of a node
- * @fdto: Device tree overlay blob
- * @node: Offset of the node we want to adjust
- * @delta: Offset to shift the phandles of
- *
- * overlay_adjust_node_phandles() adds a constant to all the phandles
- * of a given node. This is mainly use as part of the overlay
- * application process, when we want to update all the overlay
- * phandles to not conflict with the overlays of the base device tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_adjust_node_phandles(void *fdto, int node,
-                    uint32_t delta)
-{
-    int child;
-    int ret;
-
-    ret = overlay_phandle_add_offset(fdto, node, "phandle", delta);
-    if (ret && ret != -FDT_ERR_NOTFOUND)
-        return ret;
-
-    ret = overlay_phandle_add_offset(fdto, node, "linux,phandle", delta);
-    if (ret && ret != -FDT_ERR_NOTFOUND)
-        return ret;
-
-    fdt_for_each_subnode(child, fdto, node) {
-        ret = overlay_adjust_node_phandles(fdto, child, delta);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_adjust_local_phandles - Adjust the phandles of a whole overlay
- * @fdto: Device tree overlay blob
- * @delta: Offset to shift the phandles of
- *
- * overlay_adjust_local_phandles() adds a constant to all the
- * phandles of an overlay. This is mainly use as part of the overlay
- * application process, when we want to update all the overlay
- * phandles to not conflict with the overlays of the base device tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_adjust_local_phandles(void *fdto, uint32_t delta)
-{
-    /*
-     * Start adjusting the phandles from the overlay root
-     */
-    return overlay_adjust_node_phandles(fdto, 0, delta);
-}
-
-/**
- * overlay_update_local_node_references - Adjust the overlay references
- * @fdto: Device tree overlay blob
- * @tree_node: Node offset of the node to operate on
- * @fixup_node: Node offset of the matching local fixups node
- * @delta: Offset to shift the phandles of
- *
- * overlay_update_local_nodes_references() update the phandles
- * pointing to a node within the device tree overlay by adding a
- * constant delta.
- *
- * This is mainly used as part of a device tree application process,
- * where you want the device tree overlays phandles to not conflict
- * with the ones from the base device tree before merging them.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_update_local_node_references(void *fdto,
-                        int tree_node,
-                        int fixup_node,
-                        uint32_t delta)
-{
-    int fixup_prop;
-    int fixup_child;
-    int ret;
-
-    fdt_for_each_property_offset(fixup_prop, fdto, fixup_node) {
-        const fdt32_t *fixup_val;
-        const char *tree_val;
-        const char *name;
-        int fixup_len;
-        int tree_len;
-        int i;
-
-        fixup_val = fdt_getprop_by_offset(fdto, fixup_prop,
-                          &name, &fixup_len);
-        if (!fixup_val)
-            return fixup_len;
-
-        if (fixup_len % sizeof(uint32_t))
-            return -FDT_ERR_BADOVERLAY;
-
-        tree_val = fdt_getprop(fdto, tree_node, name, &tree_len);
-        if (!tree_val) {
-            if (tree_len == -FDT_ERR_NOTFOUND)
-                return -FDT_ERR_BADOVERLAY;
-
-            return tree_len;
-        }
-
-        for (i = 0; i < (fixup_len / sizeof(uint32_t)); i++) {
-            fdt32_t adj_val;
-            uint32_t poffset;
-
-            poffset = fdt32_to_cpu(fixup_val[i]);
-
-            /*
-             * phandles to fixup can be unaligned.
-             *
-             * Use a memcpy for the architectures that do
-             * not support unaligned accesses.
-             */
-            memcpy(&adj_val, tree_val + poffset, sizeof(adj_val));
-
-            adj_val = cpu_to_fdt32(fdt32_to_cpu(adj_val) + delta);
-
-            ret = fdt_setprop_inplace_namelen_partial(fdto,
-                                  tree_node,
-                                  name,
-                                  strlen(name),
-                                  poffset,
-                                  &adj_val,
-                                  sizeof(adj_val));
-            if (ret == -FDT_ERR_NOSPACE)
-                return -FDT_ERR_BADOVERLAY;
-
-            if (ret)
-                return ret;
-        }
-    }
-
-    fdt_for_each_subnode(fixup_child, fdto, fixup_node) {
-        const char *fixup_child_name = fdt_get_name(fdto, fixup_child,
-                                NULL);
-        int tree_child;
-
-        tree_child = fdt_subnode_offset(fdto, tree_node,
-                        fixup_child_name);
-        if (tree_child == -FDT_ERR_NOTFOUND)
-            return -FDT_ERR_BADOVERLAY;
-        if (tree_child < 0)
-            return tree_child;
-
-        ret = overlay_update_local_node_references(fdto,
-                               tree_child,
-                               fixup_child,
-                               delta);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_update_local_references - Adjust the overlay references
- * @fdto: Device tree overlay blob
- * @delta: Offset to shift the phandles of
- *
- * overlay_update_local_references() update all the phandles pointing
- * to a node within the device tree overlay by adding a constant
- * delta to not conflict with the base overlay.
- *
- * This is mainly used as part of a device tree application process,
- * where you want the device tree overlays phandles to not conflict
- * with the ones from the base device tree before merging them.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_update_local_references(void *fdto, uint32_t delta)
-{
-    int fixups;
-
-    fixups = fdt_path_offset(fdto, "/__local_fixups__");
-    if (fixups < 0) {
-        /* There's no local phandles to adjust, bail out */
-        if (fixups == -FDT_ERR_NOTFOUND)
-            return 0;
-
-        return fixups;
-    }
-
-    /*
-     * Update our local references from the root of the tree
-     */
-    return overlay_update_local_node_references(fdto, 0, fixups,
-                            delta);
-}
-
-/**
- * overlay_fixup_one_phandle - Set an overlay phandle to the base one
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- * @symbols_off: Node offset of the symbols node in the base device tree
- * @path: Path to a node holding a phandle in the overlay
- * @path_len: number of path characters to consider
- * @name: Name of the property holding the phandle reference in the overlay
- * @name_len: number of name characters to consider
- * @poffset: Offset within the overlay property where the phandle is stored
- * @label: Label of the node referenced by the phandle
- *
- * overlay_fixup_one_phandle() resolves an overlay phandle pointing to
- * a node in the base device tree.
- *
- * This is part of the device tree overlay application process, when
- * you want all the phandles in the overlay to point to the actual
- * base dt nodes.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_fixup_one_phandle(void *fdt, void *fdto,
-                     int symbols_off,
-                     const char *path, uint32_t path_len,
-                     const char *name, uint32_t name_len,
-                     int poffset, const char *label)
-{
-    const char *symbol_path;
-    uint32_t phandle;
-    fdt32_t phandle_prop;
-    int symbol_off, fixup_off;
-    int prop_len;
-
-    if (symbols_off < 0)
-        return symbols_off;
-
-    symbol_path = fdt_getprop(fdt, symbols_off, label,
-                  &prop_len);
-    if (!symbol_path)
-        return prop_len;
-
-    symbol_off = fdt_path_offset(fdt, symbol_path);
-    if (symbol_off < 0)
-        return symbol_off;
-
-    phandle = fdt_get_phandle(fdt, symbol_off);
-    if (!phandle)
-        return -FDT_ERR_NOTFOUND;
-
-    fixup_off = fdt_path_offset_namelen(fdto, path, path_len);
-    if (fixup_off == -FDT_ERR_NOTFOUND)
-        return -FDT_ERR_BADOVERLAY;
-    if (fixup_off < 0)
-        return fixup_off;
-
-    phandle_prop = cpu_to_fdt32(phandle);
-    return fdt_setprop_inplace_namelen_partial(fdto, fixup_off,
-                           name, name_len, poffset,
-                           &phandle_prop,
-                           sizeof(phandle_prop));
-};
-
-/**
- * overlay_fixup_phandle - Set an overlay phandle to the base one
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- * @symbols_off: Node offset of the symbols node in the base device tree
- * @property: Property offset in the overlay holding the list of fixups
- *
- * overlay_fixup_phandle() resolves all the overlay phandles pointed
- * to in a __fixups__ property, and updates them to match the phandles
- * in use in the base device tree.
- *
- * This is part of the device tree overlay application process, when
- * you want all the phandles in the overlay to point to the actual
- * base dt nodes.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_fixup_phandle(void *fdt, void *fdto, int symbols_off,
-                 int property)
-{
-    const char *value;
-    const char *label;
-    int len;
-
-    value = fdt_getprop_by_offset(fdto, property,
-                      &label, &len);
-    if (!value) {
-        if (len == -FDT_ERR_NOTFOUND)
-            return -FDT_ERR_INTERNAL;
-
-        return len;
-    }
-
-    do {
-        const char *path, *name, *fixup_end;
-        const char *fixup_str = value;
-        uint32_t path_len, name_len;
-        uint32_t fixup_len;
-        char *sep, *endptr;
-        int poffset, ret;
-
-        fixup_end = memchr(value, '\0', len);
-        if (!fixup_end)
-            return -FDT_ERR_BADOVERLAY;
-        fixup_len = fixup_end - fixup_str;
-
-        len -= fixup_len + 1;
-        value += fixup_len + 1;
-
-        path = fixup_str;
-        sep = memchr(fixup_str, ':', fixup_len);
-        if (!sep || *sep != ':')
-            return -FDT_ERR_BADOVERLAY;
-
-        path_len = sep - path;
-        if (path_len == (fixup_len - 1))
-            return -FDT_ERR_BADOVERLAY;
-
-        fixup_len -= path_len + 1;
-        name = sep + 1;
-        sep = memchr(name, ':', fixup_len);
-        if (!sep || *sep != ':')
-            return -FDT_ERR_BADOVERLAY;
-
-        name_len = sep - name;
-        if (!name_len)
-            return -FDT_ERR_BADOVERLAY;
-
-        poffset = strtoul(sep + 1, &endptr, 10);
-        if ((*endptr != '\0') || (endptr <= (sep + 1)))
-            return -FDT_ERR_BADOVERLAY;
-
-        ret = overlay_fixup_one_phandle(fdt, fdto, symbols_off,
-                        path, path_len, name, name_len,
-                        poffset, label);
-        if (ret)
-            return ret;
-    } while (len > 0);
-
-    return 0;
-}
-
-/**
- * overlay_fixup_phandles - Resolve the overlay phandles to the base
- *                          device tree
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- *
- * overlay_fixup_phandles() resolves all the overlay phandles pointing
- * to nodes in the base device tree.
- *
- * This is one of the steps of the device tree overlay application
- * process, when you want all the phandles in the overlay to point to
- * the actual base dt nodes.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_fixup_phandles(void *fdt, void *fdto)
-{
-    int fixups_off, symbols_off;
-    int property;
-
-    /* We can have overlays without any fixups */
-    fixups_off = fdt_path_offset(fdto, "/__fixups__");
-    if (fixups_off == -FDT_ERR_NOTFOUND)
-        return 0; /* nothing to do */
-    if (fixups_off < 0)
-        return fixups_off;
-
-    /* And base DTs without symbols */
-    symbols_off = fdt_path_offset(fdt, "/__symbols__");
-    if ((symbols_off < 0 && (symbols_off != -FDT_ERR_NOTFOUND)))
-        return symbols_off;
-
-    fdt_for_each_property_offset(property, fdto, fixups_off) {
-        int ret;
-
-        ret = overlay_fixup_phandle(fdt, fdto, symbols_off, property);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_apply_node - Merges a node into the base device tree
- * @fdt: Base Device Tree blob
- * @target: Node offset in the base device tree to apply the fragment to
- * @fdto: Device tree overlay blob
- * @node: Node offset in the overlay holding the changes to merge
- *
- * overlay_apply_node() merges a node into a target base device tree
- * node pointed.
- *
- * This is part of the final step in the device tree overlay
- * application process, when all the phandles have been adjusted and
- * resolved and you just have to merge overlay into the base device
- * tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_apply_node(void *fdt, int target,
-                  void *fdto, int node)
-{
-    int property;
-    int subnode;
-
-    fdt_for_each_property_offset(property, fdto, node) {
-        const char *name;
-        const void *prop;
-        int prop_len;
-        int ret;
-
-        prop = fdt_getprop_by_offset(fdto, property, &name,
-                         &prop_len);
-        if (prop_len == -FDT_ERR_NOTFOUND)
-            return -FDT_ERR_INTERNAL;
-        if (prop_len < 0)
-            return prop_len;
-
-        ret = fdt_setprop(fdt, target, name, prop, prop_len);
-        if (ret)
-            return ret;
-    }
-
-    fdt_for_each_subnode(subnode, fdto, node) {
-        const char *name = fdt_get_name(fdto, subnode, NULL);
-        int nnode;
-        int ret;
-
-        nnode = fdt_add_subnode(fdt, target, name);
-        if (nnode == -FDT_ERR_EXISTS) {
-            nnode = fdt_subnode_offset(fdt, target, name);
-            if (nnode == -FDT_ERR_NOTFOUND)
-                return -FDT_ERR_INTERNAL;
-        }
-
-        if (nnode < 0)
-            return nnode;
-
-        ret = overlay_apply_node(fdt, nnode, fdto, subnode);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-/**
- * overlay_merge - Merge an overlay into its base device tree
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- *
- * overlay_merge() merges an overlay into its base device tree.
- *
- * This is the next to last step in the device tree overlay application
- * process, when all the phandles have been adjusted and resolved and
- * you just have to merge overlay into the base device tree.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_merge(void *fdt, void *fdto)
-{
-    int fragment;
-
-    fdt_for_each_subnode(fragment, fdto, 0) {
-        int overlay;
-        int target;
-        int ret;
-
-        /*
-         * Each fragments will have an __overlay__ node. If
-         * they don't, it's not supposed to be merged
-         */
-        overlay = fdt_subnode_offset(fdto, fragment, "__overlay__");
-        if (overlay == -FDT_ERR_NOTFOUND)
-            continue;
-
-        if (overlay < 0)
-            return overlay;
-
-        target = overlay_get_target(fdt, fdto, fragment, NULL);
-        if (target < 0)
-            return target;
-
-        ret = overlay_apply_node(fdt, target, fdto, overlay);
-        if (ret)
-            return ret;
-    }
-
-    return 0;
-}
-
-static int get_path_len(const void *fdt, int nodeoffset)
-{
-    int len = 0, namelen;
-    const char *name;
-
-    FDT_RO_PROBE(fdt);
-
-    for (;;) {
-        name = fdt_get_name(fdt, nodeoffset, &namelen);
-        if (!name)
-            return namelen;
-
-        /* root? we're done */
-        if (namelen == 0)
-            break;
-
-        nodeoffset = fdt_parent_offset(fdt, nodeoffset);
-        if (nodeoffset < 0)
-            return nodeoffset;
-        len += namelen + 1;
-    }
-
-    /* in case of root pretend it's "/" */
-    if (len == 0)
-        len++;
-    return len;
-}
-
-/**
- * overlay_symbol_update - Update the symbols of base tree after a merge
- * @fdt: Base Device Tree blob
- * @fdto: Device tree overlay blob
- *
- * overlay_symbol_update() updates the symbols of the base tree with the
- * symbols of the applied overlay
- *
- * This is the last step in the device tree overlay application
- * process, allowing the reference of overlay symbols by subsequent
- * overlay operations.
- *
- * returns:
- *      0 on success
- *      Negative error code on failure
- */
-static int overlay_symbol_update(void *fdt, void *fdto)
-{
-    int root_sym, ov_sym, prop, path_len, fragment, target;
-    int len, frag_name_len, ret, rel_path_len;
-    const char *s, *e;
-    const char *path;
-    const char *name;
-    const char *frag_name;
-    const char *rel_path;
-    const char *target_path;
-    char *buf;
-    void *p;
-
-    ov_sym = fdt_subnode_offset(fdto, 0, "__symbols__");
-
-    /* if no overlay symbols exist no problem */
-    if (ov_sym < 0)
-        return 0;
-
-    root_sym = fdt_subnode_offset(fdt, 0, "__symbols__");
-
-    /* it no root symbols exist we should create them */
-    if (root_sym == -FDT_ERR_NOTFOUND)
-        root_sym = fdt_add_subnode(fdt, 0, "__symbols__");
-
-    /* any error is fatal now */
-    if (root_sym < 0)
-        return root_sym;
-
-    /* iterate over each overlay symbol */
-    fdt_for_each_property_offset(prop, fdto, ov_sym) {
-        path = fdt_getprop_by_offset(fdto, prop, &name, &path_len);
-        if (!path)
-            return path_len;
-
-        /* verify it's a string property (terminated by a single \0) */
-        if (path_len < 1 || memchr(path, '\0', path_len) != &path[path_len - 1])
-            return -FDT_ERR_BADVALUE;
-
-        /* keep end marker to avoid strlen() */
-        e = path + path_len;
-
-        /* format: //__overlay__/ */
-
-        if (*path != '/')
-            return -FDT_ERR_BADVALUE;
-
-        /* get fragment name first */
-        s = strchr(path + 1, '/');
-        if (!s)
-            return -FDT_ERR_BADOVERLAY;
-
-        frag_name = path + 1;
-        frag_name_len = s - path - 1;
-
-        /* verify format; safe since "s" lies in \0 terminated prop */
-        len = sizeof("/__overlay__/") - 1;
-        if ((e - s) < len || memcmp(s, "/__overlay__/", len))
-            return -FDT_ERR_BADOVERLAY;
-
-        rel_path = s + len;
-        rel_path_len = e - rel_path;
-
-        /* find the fragment index in which the symbol lies */
-        ret = fdt_subnode_offset_namelen(fdto, 0, frag_name,
-                           frag_name_len);
-        /* not found? */
-        if (ret < 0)
-            return -FDT_ERR_BADOVERLAY;
-        fragment = ret;
-
-        /* an __overlay__ subnode must exist */
-        ret = fdt_subnode_offset(fdto, fragment, "__overlay__");
-        if (ret < 0)
-            return -FDT_ERR_BADOVERLAY;
-
-        /* get the target of the fragment */
-        ret = overlay_get_target(fdt, fdto, fragment, &target_path);
-        if (ret < 0)
-            return ret;
-        target = ret;
-
-        /* if we have a target path use */
-        if (!target_path) {
-            ret = get_path_len(fdt, target);
-            if (ret < 0)
-                return ret;
-            len = ret;
-        } else {
-            len = strlen(target_path);
-        }
-
-        ret = fdt_setprop_placeholder(fdt, root_sym, name,
-                len + (len > 1) + rel_path_len + 1, &p);
-        if (ret < 0)
-            return ret;
-
-        if (!target_path) {
-            /* again in case setprop_placeholder changed it */
-            ret = overlay_get_target(fdt, fdto, fragment, &target_path);
-            if (ret < 0)
-                return ret;
-            target = ret;
-        }
-
-        buf = p;
-        if (len > 1) { /* target is not root */
-            if (!target_path) {
-                ret = fdt_get_path(fdt, target, buf, len + 1);
-                if (ret < 0)
-                    return ret;
-            } else
-                memcpy(buf, target_path, len + 1);
-
-        } else
-            len--;
-
-        buf[len] = '/';
-        memcpy(buf + len + 1, rel_path, rel_path_len);
-        buf[len + 1 + rel_path_len] = '\0';
-    }
-
-    return 0;
-}
-
-int fdt_overlay_apply(void *fdt, void *fdto)
-{
-    uint32_t delta = fdt_get_max_phandle(fdt);
-    int ret;
-
-    FDT_RO_PROBE(fdt);
-    FDT_RO_PROBE(fdto);
-
-    ret = overlay_adjust_local_phandles(fdto, delta);
-    if (ret)
-        goto err;
-
-    ret = overlay_update_local_references(fdto, delta);
-    if (ret)
-        goto err;
-
-    ret = overlay_fixup_phandles(fdt, fdto);
-    if (ret)
-        goto err;
-
-    ret = overlay_merge(fdt, fdto);
-    if (ret)
-        goto err;
-
-    ret = overlay_symbol_update(fdt, fdto);
-    if (ret)
-        goto err;
-
-    /*
-     * The overlay has been damaged, erase its magic.
-     */
-    fdt_set_magic(fdto, ~0);
-
-    return 0;
-
-err:
-    /*
-     * The overlay might have been damaged, erase its magic.
-     */
-    fdt_set_magic(fdto, ~0);
-
-    /*
-     * The base device tree might have been damaged, erase its
-     * magic.
-     */
-    fdt_set_magic(fdt, ~0);
-
-    return ret;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c
deleted file mode 100644
index 64aff00b79..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_ro.c
+++ /dev/null
@@ -1,901 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_nodename_eq_(const void *fdt, int offset,
-                const char *s, int len)
-{
-    int olen;
-    const char *p = fdt_get_name(fdt, offset, &olen);
-
-    if (!p || olen < len)
-        /* short match */
-        return 0;
-
-    if (memcmp(p, s, len) != 0)
-        return 0;
-
-    if (p[len] == '\0')
-        return 1;
-    else if (!memchr(s, '@', len) && (p[len] == '@'))
-        return 1;
-    else
-        return 0;
-}
-
-const char *fdt_get_string(const void *fdt, int stroffset, int *lenp)
-{
-    uint32_t absoffset = stroffset + fdt_off_dt_strings(fdt);
-    size_t len;
-    int err;
-    const char *s, *n;
-
-    err = fdt_ro_probe_(fdt);
-    if (err != 0)
-        goto fail;
-
-    err = -FDT_ERR_BADOFFSET;
-    if (absoffset >= fdt_totalsize(fdt))
-        goto fail;
-    len = fdt_totalsize(fdt) - absoffset;
-
-    if (fdt_magic(fdt) == FDT_MAGIC) {
-        if (stroffset < 0)
-            goto fail;
-        if (fdt_version(fdt) >= 17) {
-            if (stroffset >= fdt_size_dt_strings(fdt))
-                goto fail;
-            if ((fdt_size_dt_strings(fdt) - stroffset) < len)
-                len = fdt_size_dt_strings(fdt) - stroffset;
-        }
-    } else if (fdt_magic(fdt) == FDT_SW_MAGIC) {
-        if ((stroffset >= 0)
-            || (stroffset < -fdt_size_dt_strings(fdt)))
-            goto fail;
-        if ((-stroffset) < len)
-            len = -stroffset;
-    } else {
-        err = -FDT_ERR_INTERNAL;
-        goto fail;
-    }
-
-    s = (const char *)fdt + absoffset;
-    n = memchr(s, '\0', len);
-    if (!n) {
-        /* missing terminating NULL */
-        err = -FDT_ERR_TRUNCATED;
-        goto fail;
-    }
-
-    if (lenp)
-        *lenp = n - s;
-    return s;
-
-fail:
-    if (lenp)
-        *lenp = err;
-    return NULL;
-}
-
-const char *fdt_string(const void *fdt, int stroffset)
-{
-    return fdt_get_string(fdt, stroffset, NULL);
-}
-
-static int fdt_string_eq_(const void *fdt, int stroffset,
-              const char *s, int len)
-{
-    int slen;
-    const char *p = fdt_get_string(fdt, stroffset, &slen);
-
-    return p && (slen == len) && (memcmp(p, s, len) == 0);
-}
-
-uint32_t fdt_get_max_phandle(const void *fdt)
-{
-    uint32_t max_phandle = 0;
-    int offset;
-
-    for (offset = fdt_next_node(fdt, -1, NULL);;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        uint32_t phandle;
-
-        if (offset == -FDT_ERR_NOTFOUND)
-            return max_phandle;
-
-        if (offset < 0)
-            return (uint32_t)-1;
-
-        phandle = fdt_get_phandle(fdt, offset);
-        if (phandle == (uint32_t)-1)
-            continue;
-
-        if (phandle > max_phandle)
-            max_phandle = phandle;
-    }
-
-    return 0;
-}
-
-static const struct fdt_reserve_entry *fdt_mem_rsv(const void *fdt, int n)
-{
-    int offset = n * sizeof(struct fdt_reserve_entry);
-    int absoffset = fdt_off_mem_rsvmap(fdt) + offset;
-
-    if (absoffset < fdt_off_mem_rsvmap(fdt))
-        return NULL;
-    if (absoffset > fdt_totalsize(fdt) - sizeof(struct fdt_reserve_entry))
-        return NULL;
-    return fdt_mem_rsv_(fdt, n);
-}
-
-int fdt_get_mem_rsv(const void *fdt, int n, uint64_t *address, uint64_t *size)
-{
-    const struct fdt_reserve_entry *re;
-
-    FDT_RO_PROBE(fdt);
-    re = fdt_mem_rsv(fdt, n);
-    if (!re)
-        return -FDT_ERR_BADOFFSET;
-
-    *address = fdt64_ld(&re->address);
-    *size = fdt64_ld(&re->size);
-    return 0;
-}
-
-int fdt_num_mem_rsv(const void *fdt)
-{
-    int i;
-    const struct fdt_reserve_entry *re;
-
-    for (i = 0; (re = fdt_mem_rsv(fdt, i)) != NULL; i++) {
-        if (fdt64_ld(&re->size) == 0)
-            return i;
-    }
-    return -FDT_ERR_TRUNCATED;
-}
-
-static int nextprop_(const void *fdt, int offset)
-{
-    uint32_t tag;
-    int nextoffset;
-
-    do {
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-        switch (tag) {
-        case FDT_END:
-            if (nextoffset >= 0)
-                return -FDT_ERR_BADSTRUCTURE;
-            else
-                return nextoffset;
-
-        case FDT_PROP:
-            return offset;
-        }
-        offset = nextoffset;
-    } while (tag == FDT_NOP);
-
-    return -FDT_ERR_NOTFOUND;
-}
-
-int fdt_subnode_offset_namelen(const void *fdt, int offset,
-                   const char *name, int namelen)
-{
-    int depth;
-
-    FDT_RO_PROBE(fdt);
-
-    for (depth = 0;
-         (offset >= 0) && (depth >= 0);
-         offset = fdt_next_node(fdt, offset, &depth))
-        if ((depth == 1)
-            && fdt_nodename_eq_(fdt, offset, name, namelen))
-            return offset;
-
-    if (depth < 0)
-        return -FDT_ERR_NOTFOUND;
-    return offset; /* error */
-}
-
-int fdt_subnode_offset(const void *fdt, int parentoffset,
-               const char *name)
-{
-    return fdt_subnode_offset_namelen(fdt, parentoffset, name, strlen(name));
-}
-
-int fdt_path_offset_namelen(const void *fdt, const char *path, int namelen)
-{
-    const char *end = path + namelen;
-    const char *p = path;
-    int offset = 0;
-
-    FDT_RO_PROBE(fdt);
-
-    /* see if we have an alias */
-    if (*path != '/') {
-        const char *q = memchr(path, '/', end - p);
-
-        if (!q)
-            q = end;
-
-        p = fdt_get_alias_namelen(fdt, p, q - p);
-        if (!p)
-            return -FDT_ERR_BADPATH;
-        offset = fdt_path_offset(fdt, p);
-
-        p = q;
-    }
-
-    while (p < end) {
-        const char *q;
-
-        while (*p == '/') {
-            p++;
-            if (p == end)
-                return offset;
-        }
-        q = memchr(p, '/', end - p);
-        if (! q)
-            q = end;
-
-        offset = fdt_subnode_offset_namelen(fdt, offset, p, q-p);
-        if (offset < 0)
-            return offset;
-
-        p = q;
-    }
-
-    return offset;
-}
-
-int fdt_path_offset(const void *fdt, const char *path)
-{
-    return fdt_path_offset_namelen(fdt, path, strlen(path));
-}
-
-const char *fdt_get_name(const void *fdt, int nodeoffset, int *len)
-{
-    const struct fdt_node_header *nh = fdt_offset_ptr_(fdt, nodeoffset);
-    const char *nameptr;
-    int err;
-
-    if (((err = fdt_ro_probe_(fdt)) != 0)
-        || ((err = fdt_check_node_offset_(fdt, nodeoffset)) < 0))
-            goto fail;
-
-    nameptr = nh->name;
-
-    if (fdt_version(fdt) < 0x10) {
-        /*
-         * For old FDT versions, match the naming conventions of V16:
-         * give only the leaf name (after all /). The actual tree
-         * contents are loosely checked.
-         */
-        const char *leaf;
-        leaf = strrchr(nameptr, '/');
-        if (leaf == NULL) {
-            err = -FDT_ERR_BADSTRUCTURE;
-            goto fail;
-        }
-        nameptr = leaf+1;
-    }
-
-    if (len)
-        *len = strlen(nameptr);
-
-    return nameptr;
-
- fail:
-    if (len)
-        *len = err;
-    return NULL;
-}
-
-int fdt_first_property_offset(const void *fdt, int nodeoffset)
-{
-    int offset;
-
-    if ((offset = fdt_check_node_offset_(fdt, nodeoffset)) < 0)
-        return offset;
-
-    return nextprop_(fdt, offset);
-}
-
-int fdt_next_property_offset(const void *fdt, int offset)
-{
-    if ((offset = fdt_check_prop_offset_(fdt, offset)) < 0)
-        return offset;
-
-    return nextprop_(fdt, offset);
-}
-
-static const struct fdt_property *fdt_get_property_by_offset_(const void *fdt,
-                                      int offset,
-                                      int *lenp)
-{
-    int err;
-    const struct fdt_property *prop;
-
-    if ((err = fdt_check_prop_offset_(fdt, offset)) < 0) {
-        if (lenp)
-            *lenp = err;
-        return NULL;
-    }
-
-    prop = fdt_offset_ptr_(fdt, offset);
-
-    if (lenp)
-        *lenp = fdt32_ld(&prop->len);
-
-    return prop;
-}
-
-const struct fdt_property *fdt_get_property_by_offset(const void *fdt,
-                              int offset,
-                              int *lenp)
-{
-    /* Prior to version 16, properties may need realignment
-     * and this API does not work. fdt_getprop_*() will, however. */
-
-    if (fdt_version(fdt) < 0x10) {
-        if (lenp)
-            *lenp = -FDT_ERR_BADVERSION;
-        return NULL;
-    }
-
-    return fdt_get_property_by_offset_(fdt, offset, lenp);
-}
-
-static const struct fdt_property *fdt_get_property_namelen_(const void *fdt,
-                                    int offset,
-                                    const char *name,
-                                    int namelen,
-                                int *lenp,
-                                int *poffset)
-{
-    for (offset = fdt_first_property_offset(fdt, offset);
-         (offset >= 0);
-         (offset = fdt_next_property_offset(fdt, offset))) {
-        const struct fdt_property *prop;
-
-        if (!(prop = fdt_get_property_by_offset_(fdt, offset, lenp))) {
-            offset = -FDT_ERR_INTERNAL;
-            break;
-        }
-        if (fdt_string_eq_(fdt, fdt32_ld(&prop->nameoff),
-                   name, namelen)) {
-            if (poffset)
-                *poffset = offset;
-            return prop;
-        }
-    }
-
-    if (lenp)
-        *lenp = offset;
-    return NULL;
-}
-
-
-const struct fdt_property *fdt_get_property_namelen(const void *fdt,
-                            int offset,
-                            const char *name,
-                            int namelen, int *lenp)
-{
-    /* Prior to version 16, properties may need realignment
-     * and this API does not work. fdt_getprop_*() will, however. */
-    if (fdt_version(fdt) < 0x10) {
-        if (lenp)
-            *lenp = -FDT_ERR_BADVERSION;
-        return NULL;
-    }
-
-    return fdt_get_property_namelen_(fdt, offset, name, namelen, lenp,
-                     NULL);
-}
-
-
-const struct fdt_property *fdt_get_property(const void *fdt,
-                        int nodeoffset,
-                        const char *name, int *lenp)
-{
-    return fdt_get_property_namelen(fdt, nodeoffset, name,
-                    strlen(name), lenp);
-}
-
-const void *fdt_getprop_namelen(const void *fdt, int nodeoffset,
-                const char *name, int namelen, int *lenp)
-{
-    int poffset;
-    const struct fdt_property *prop;
-
-    prop = fdt_get_property_namelen_(fdt, nodeoffset, name, namelen, lenp,
-                     &poffset);
-    if (!prop)
-        return NULL;
-
-    /* Handle realignment */
-    if (fdt_version(fdt) < 0x10 && (poffset + sizeof(*prop)) % 8 &&
-        fdt32_ld(&prop->len) >= 8)
-        return prop->data + 4;
-    return prop->data;
-}
-
-const void *fdt_getprop_by_offset(const void *fdt, int offset,
-                  const char **namep, int *lenp)
-{
-    const struct fdt_property *prop;
-
-    prop = fdt_get_property_by_offset_(fdt, offset, lenp);
-    if (!prop)
-        return NULL;
-    if (namep) {
-        const char *name;
-        int namelen;
-        name = fdt_get_string(fdt, fdt32_ld(&prop->nameoff),
-                      &namelen);
-        if (!name) {
-            if (lenp)
-                *lenp = namelen;
-            return NULL;
-        }
-        *namep = name;
-    }
-
-    /* Handle realignment */
-    if (fdt_version(fdt) < 0x10 && (offset + sizeof(*prop)) % 8 &&
-        fdt32_ld(&prop->len) >= 8)
-        return prop->data + 4;
-    return prop->data;
-}
-
-const void *fdt_getprop(const void *fdt, int nodeoffset,
-            const char *name, int *lenp)
-{
-    return fdt_getprop_namelen(fdt, nodeoffset, name, strlen(name), lenp);
-}
-
-uint32_t fdt_get_phandle(const void *fdt, int nodeoffset)
-{
-    const fdt32_t *php;
-    int len;
-
-    /* FIXME: This is a bit sub-optimal, since we potentially scan
-     * over all the properties twice. */
-    php = fdt_getprop(fdt, nodeoffset, "phandle", &len);
-    if (!php || (len != sizeof(*php))) {
-        php = fdt_getprop(fdt, nodeoffset, "linux,phandle", &len);
-        if (!php || (len != sizeof(*php)))
-            return 0;
-    }
-
-    return fdt32_ld(php);
-}
-
-const char *fdt_get_alias_namelen(const void *fdt,
-                  const char *name, int namelen)
-{
-    int aliasoffset;
-
-    aliasoffset = fdt_path_offset(fdt, "/aliases");
-    if (aliasoffset < 0)
-        return NULL;
-
-    return fdt_getprop_namelen(fdt, aliasoffset, name, namelen, NULL);
-}
-
-const char *fdt_get_alias(const void *fdt, const char *name)
-{
-    return fdt_get_alias_namelen(fdt, name, strlen(name));
-}
-
-int fdt_get_path(const void *fdt, int nodeoffset, char *buf, int buflen)
-{
-    int pdepth = 0, p = 0;
-    int offset, depth, namelen;
-    const char *name;
-
-    FDT_RO_PROBE(fdt);
-
-    if (buflen < 2)
-        return -FDT_ERR_NOSPACE;
-
-    for (offset = 0, depth = 0;
-         (offset >= 0) && (offset <= nodeoffset);
-         offset = fdt_next_node(fdt, offset, &depth)) {
-        while (pdepth > depth) {
-            do {
-                p--;
-            } while (buf[p-1] != '/');
-            pdepth--;
-        }
-
-        if (pdepth >= depth) {
-            name = fdt_get_name(fdt, offset, &namelen);
-            if (!name)
-                return namelen;
-            if ((p + namelen + 1) <= buflen) {
-                memcpy(buf + p, name, namelen);
-                p += namelen;
-                buf[p++] = '/';
-                pdepth++;
-            }
-        }
-
-        if (offset == nodeoffset) {
-            if (pdepth < (depth + 1))
-                return -FDT_ERR_NOSPACE;
-
-            if (p > 1) /* special case so that root path is "/", not "" */
-                p--;
-            buf[p] = '\0';
-            return 0;
-        }
-    }
-
-    if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
-        return -FDT_ERR_BADOFFSET;
-    else if (offset == -FDT_ERR_BADOFFSET)
-        return -FDT_ERR_BADSTRUCTURE;
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_supernode_atdepth_offset(const void *fdt, int nodeoffset,
-                 int supernodedepth, int *nodedepth)
-{
-    int offset, depth;
-    int supernodeoffset = -FDT_ERR_INTERNAL;
-
-    FDT_RO_PROBE(fdt);
-
-    if (supernodedepth < 0)
-        return -FDT_ERR_NOTFOUND;
-
-    for (offset = 0, depth = 0;
-         (offset >= 0) && (offset <= nodeoffset);
-         offset = fdt_next_node(fdt, offset, &depth)) {
-        if (depth == supernodedepth)
-            supernodeoffset = offset;
-
-        if (offset == nodeoffset) {
-            if (nodedepth)
-                *nodedepth = depth;
-
-            if (supernodedepth > depth)
-                return -FDT_ERR_NOTFOUND;
-            else
-                return supernodeoffset;
-        }
-    }
-
-    if ((offset == -FDT_ERR_NOTFOUND) || (offset >= 0))
-        return -FDT_ERR_BADOFFSET;
-    else if (offset == -FDT_ERR_BADOFFSET)
-        return -FDT_ERR_BADSTRUCTURE;
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_node_depth(const void *fdt, int nodeoffset)
-{
-    int nodedepth;
-    int err;
-
-    err = fdt_supernode_atdepth_offset(fdt, nodeoffset, 0, &nodedepth);
-    if (err)
-        return (err < 0) ? err : -FDT_ERR_INTERNAL;
-    return nodedepth;
-}
-
-int fdt_parent_offset(const void *fdt, int nodeoffset)
-{
-    int nodedepth = fdt_node_depth(fdt, nodeoffset);
-
-    if (nodedepth < 0)
-        return nodedepth;
-    return fdt_supernode_atdepth_offset(fdt, nodeoffset,
-                        nodedepth - 1, NULL);
-}
-
-int fdt_node_offset_by_prop_value(const void *fdt, int startoffset,
-                  const char *propname,
-                  const void *propval, int proplen)
-{
-    int offset;
-    const void *val;
-    int len;
-
-    FDT_RO_PROBE(fdt);
-
-    /* FIXME: The algorithm here is pretty horrible: we scan each
-     * property of a node in fdt_getprop(), then if that didn't
-     * find what we want, we scan over them again making our way
-     * to the next node.  Still it's the easiest to implement
-     * approach; performance can come later. */
-    for (offset = fdt_next_node(fdt, startoffset, NULL);
-         offset >= 0;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        val = fdt_getprop(fdt, offset, propname, &len);
-        if (val && (len == proplen)
-            && (memcmp(val, propval, len) == 0))
-            return offset;
-    }
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_node_offset_by_phandle(const void *fdt, uint32_t phandle)
-{
-    int offset;
-
-    if ((phandle == 0) || (phandle == -1))
-        return -FDT_ERR_BADPHANDLE;
-
-    FDT_RO_PROBE(fdt);
-
-    /* FIXME: The algorithm here is pretty horrible: we
-     * potentially scan each property of a node in
-     * fdt_get_phandle(), then if that didn't find what
-     * we want, we scan over them again making our way to the next
-     * node.  Still it's the easiest to implement approach;
-     * performance can come later. */
-    for (offset = fdt_next_node(fdt, -1, NULL);
-         offset >= 0;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        if (fdt_get_phandle(fdt, offset) == phandle)
-            return offset;
-    }
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_stringlist_contains(const char *strlist, int listlen, const char *str)
-{
-    int len = strlen(str);
-    const char *p;
-
-    while (listlen >= len) {
-        if (memcmp(str, strlist, len+1) == 0)
-            return 1;
-        p = memchr(strlist, '\0', listlen);
-        if (!p)
-            return 0; /* malformed strlist.. */
-        listlen -= (p-strlist) + 1;
-        strlist = p + 1;
-    }
-    return 0;
-}
-
-int fdt_stringlist_count(const void *fdt, int nodeoffset, const char *property)
-{
-    const char *list, *end;
-    int length, count = 0;
-
-    list = fdt_getprop(fdt, nodeoffset, property, &length);
-    if (!list)
-        return length;
-
-    end = list + length;
-
-    while (list < end) {
-        length = strnlen(list, end - list) + 1;
-
-        /* Abort if the last string isn't properly NUL-terminated. */
-        if (list + length > end)
-            return -FDT_ERR_BADVALUE;
-
-        list += length;
-        count++;
-    }
-
-    return count;
-}
-
-int fdt_stringlist_search(const void *fdt, int nodeoffset, const char *property,
-              const char *string)
-{
-    int length, len, idx = 0;
-    const char *list, *end;
-
-    list = fdt_getprop(fdt, nodeoffset, property, &length);
-    if (!list)
-        return length;
-
-    len = strlen(string) + 1;
-    end = list + length;
-
-    while (list < end) {
-        length = strnlen(list, end - list) + 1;
-
-        /* Abort if the last string isn't properly NUL-terminated. */
-        if (list + length > end)
-            return -FDT_ERR_BADVALUE;
-
-        if (length == len && memcmp(list, string, length) == 0)
-            return idx;
-
-        list += length;
-        idx++;
-    }
-
-    return -FDT_ERR_NOTFOUND;
-}
-
-const char *fdt_stringlist_get(const void *fdt, int nodeoffset,
-                   const char *property, int idx,
-                   int *lenp)
-{
-    const char *list, *end;
-    int length;
-
-    list = fdt_getprop(fdt, nodeoffset, property, &length);
-    if (!list) {
-        if (lenp)
-            *lenp = length;
-
-        return NULL;
-    }
-
-    end = list + length;
-
-    while (list < end) {
-        length = strnlen(list, end - list) + 1;
-
-        /* Abort if the last string isn't properly NUL-terminated. */
-        if (list + length > end) {
-            if (lenp)
-                *lenp = -FDT_ERR_BADVALUE;
-
-            return NULL;
-        }
-
-        if (idx == 0) {
-            if (lenp)
-                *lenp = length - 1;
-
-            return list;
-        }
-
-        list += length;
-        idx--;
-    }
-
-    if (lenp)
-        *lenp = -FDT_ERR_NOTFOUND;
-
-    return NULL;
-}
-
-int fdt_node_check_compatible(const void *fdt, int nodeoffset,
-                  const char *compatible)
-{
-    const void *prop;
-    int len;
-
-    prop = fdt_getprop(fdt, nodeoffset, "compatible", &len);
-    if (!prop)
-        return len;
-
-    return !fdt_stringlist_contains(prop, len, compatible);
-}
-
-int fdt_node_offset_by_compatible(const void *fdt, int startoffset,
-                  const char *compatible)
-{
-    int offset, err;
-
-    FDT_RO_PROBE(fdt);
-
-    /* FIXME: The algorithm here is pretty horrible: we scan each
-     * property of a node in fdt_node_check_compatible(), then if
-     * that didn't find what we want, we scan over them again
-     * making our way to the next node.  Still it's the easiest to
-     * implement approach; performance can come later. */
-    for (offset = fdt_next_node(fdt, startoffset, NULL);
-         offset >= 0;
-         offset = fdt_next_node(fdt, offset, NULL)) {
-        err = fdt_node_check_compatible(fdt, offset, compatible);
-        if ((err < 0) && (err != -FDT_ERR_NOTFOUND))
-            return err;
-        else if (err == 0)
-            return offset;
-    }
-
-    return offset; /* error from fdt_next_node() */
-}
-
-int fdt_check_full(const void *fdt, size_t bufsize)
-{
-    int err;
-    int num_memrsv;
-    int offset, nextoffset = 0;
-    uint32_t tag;
-    unsigned depth = 0;
-    const void *prop;
-    const char *propname;
-
-    if (bufsize < FDT_V1_SIZE)
-        return -FDT_ERR_TRUNCATED;
-    err = fdt_check_header(fdt);
-    if (err != 0)
-        return err;
-    if (bufsize < fdt_totalsize(fdt))
-        return -FDT_ERR_TRUNCATED;
-
-    num_memrsv = fdt_num_mem_rsv(fdt);
-    if (num_memrsv < 0)
-        return num_memrsv;
-
-    while (1) {
-        offset = nextoffset;
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-
-        if (nextoffset < 0)
-            return nextoffset;
-
-        switch (tag) {
-        case FDT_NOP:
-            break;
-
-        case FDT_END:
-            if (depth != 0)
-                return -FDT_ERR_BADSTRUCTURE;
-            return 0;
-
-        case FDT_BEGIN_NODE:
-            depth++;
-            if (depth > INT_MAX)
-                return -FDT_ERR_BADSTRUCTURE;
-            break;
-
-        case FDT_END_NODE:
-            if (depth == 0)
-                return -FDT_ERR_BADSTRUCTURE;
-            depth--;
-            break;
-
-        case FDT_PROP:
-            prop = fdt_getprop_by_offset(fdt, offset, &propname,
-                             &err);
-            if (!prop)
-                return err;
-            break;
-
-        default:
-            return -FDT_ERR_INTERNAL;
-        }
-    }
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c
deleted file mode 100644
index e9b446b99f..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_rw.c
+++ /dev/null
@@ -1,484 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_blocks_misordered_(const void *fdt,
-                  int mem_rsv_size, int struct_size)
-{
-    return (fdt_off_mem_rsvmap(fdt) < FDT_ALIGN(sizeof(struct fdt_header), 8))
-        || (fdt_off_dt_struct(fdt) <
-            (fdt_off_mem_rsvmap(fdt) + mem_rsv_size))
-        || (fdt_off_dt_strings(fdt) <
-            (fdt_off_dt_struct(fdt) + struct_size))
-        || (fdt_totalsize(fdt) <
-            (fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt)));
-}
-
-static int fdt_rw_probe_(void *fdt)
-{
-    FDT_RO_PROBE(fdt);
-
-    if (fdt_version(fdt) < 17)
-        return -FDT_ERR_BADVERSION;
-    if (fdt_blocks_misordered_(fdt, sizeof(struct fdt_reserve_entry),
-                   fdt_size_dt_struct(fdt)))
-        return -FDT_ERR_BADLAYOUT;
-    if (fdt_version(fdt) > 17)
-        fdt_set_version(fdt, 17);
-
-    return 0;
-}
-
-#define FDT_RW_PROBE(fdt) \
-    { \
-        int err_; \
-        if ((err_ = fdt_rw_probe_(fdt)) != 0) \
-            return err_; \
-    }
-
-static inline int fdt_data_size_(void *fdt)
-{
-    return fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
-}
-
-static int fdt_splice_(void *fdt, void *splicepoint, int oldlen, int newlen)
-{
-    char *p = splicepoint;
-    char *end = (char *)fdt + fdt_data_size_(fdt);
-
-    if (((p + oldlen) < p) || ((p + oldlen) > end))
-        return -FDT_ERR_BADOFFSET;
-    if ((p < (char *)fdt) || ((end - oldlen + newlen) < (char *)fdt))
-        return -FDT_ERR_BADOFFSET;
-    if ((end - oldlen + newlen) > ((char *)fdt + fdt_totalsize(fdt)))
-        return -FDT_ERR_NOSPACE;
-    memmove(p + newlen, p + oldlen, end - p - oldlen);
-    return 0;
-}
-
-static int fdt_splice_mem_rsv_(void *fdt, struct fdt_reserve_entry *p,
-                   int oldn, int newn)
-{
-    int delta = (newn - oldn) * sizeof(*p);
-    int err;
-    err = fdt_splice_(fdt, p, oldn * sizeof(*p), newn * sizeof(*p));
-    if (err)
-        return err;
-    fdt_set_off_dt_struct(fdt, fdt_off_dt_struct(fdt) + delta);
-    fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
-    return 0;
-}
-
-static int fdt_splice_struct_(void *fdt, void *p,
-                  int oldlen, int newlen)
-{
-    int delta = newlen - oldlen;
-    int err;
-
-    if ((err = fdt_splice_(fdt, p, oldlen, newlen)))
-        return err;
-
-    fdt_set_size_dt_struct(fdt, fdt_size_dt_struct(fdt) + delta);
-    fdt_set_off_dt_strings(fdt, fdt_off_dt_strings(fdt) + delta);
-    return 0;
-}
-
-static int fdt_splice_string_(void *fdt, int newlen)
-{
-    void *p = (char *)fdt
-        + fdt_off_dt_strings(fdt) + fdt_size_dt_strings(fdt);
-    int err;
-
-    if ((err = fdt_splice_(fdt, p, 0, newlen)))
-        return err;
-
-    fdt_set_size_dt_strings(fdt, fdt_size_dt_strings(fdt) + newlen);
-    return 0;
-}
-
-static int fdt_find_add_string_(void *fdt, const char *s)
-{
-    char *strtab = (char *)fdt + fdt_off_dt_strings(fdt);
-    const char *p;
-    char *new;
-    int len = strlen(s) + 1;
-    int err;
-
-    p = fdt_find_string_(strtab, fdt_size_dt_strings(fdt), s);
-    if (p)
-        /* found it */
-        return (p - strtab);
-
-    new = strtab + fdt_size_dt_strings(fdt);
-    err = fdt_splice_string_(fdt, len);
-    if (err)
-        return err;
-
-    memcpy(new, s, len);
-    return (new - strtab);
-}
-
-int fdt_add_mem_rsv(void *fdt, uint64_t address, uint64_t size)
-{
-    struct fdt_reserve_entry *re;
-    int err;
-
-    FDT_RW_PROBE(fdt);
-
-    re = fdt_mem_rsv_w_(fdt, fdt_num_mem_rsv(fdt));
-    err = fdt_splice_mem_rsv_(fdt, re, 0, 1);
-    if (err)
-        return err;
-
-    re->address = cpu_to_fdt64(address);
-    re->size = cpu_to_fdt64(size);
-    return 0;
-}
-
-int fdt_del_mem_rsv(void *fdt, int n)
-{
-    struct fdt_reserve_entry *re = fdt_mem_rsv_w_(fdt, n);
-
-    FDT_RW_PROBE(fdt);
-
-    if (n >= fdt_num_mem_rsv(fdt))
-        return -FDT_ERR_NOTFOUND;
-
-    return fdt_splice_mem_rsv_(fdt, re, 1, 0);
-}
-
-static int fdt_resize_property_(void *fdt, int nodeoffset, const char *name,
-                int len, struct fdt_property **prop)
-{
-    int oldlen;
-    int err;
-
-    *prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
-    if (!*prop)
-        return oldlen;
-
-    if ((err = fdt_splice_struct_(fdt, (*prop)->data, FDT_TAGALIGN(oldlen),
-                      FDT_TAGALIGN(len))))
-        return err;
-
-    (*prop)->len = cpu_to_fdt32(len);
-    return 0;
-}
-
-static int fdt_add_property_(void *fdt, int nodeoffset, const char *name,
-                 int len, struct fdt_property **prop)
-{
-    int proplen;
-    int nextoffset;
-    int namestroff;
-    int err;
-
-    if ((nextoffset = fdt_check_node_offset_(fdt, nodeoffset)) < 0)
-        return nextoffset;
-
-    namestroff = fdt_find_add_string_(fdt, name);
-    if (namestroff < 0)
-        return namestroff;
-
-    *prop = fdt_offset_ptr_w_(fdt, nextoffset);
-    proplen = sizeof(**prop) + FDT_TAGALIGN(len);
-
-    err = fdt_splice_struct_(fdt, *prop, 0, proplen);
-    if (err)
-        return err;
-
-    (*prop)->tag = cpu_to_fdt32(FDT_PROP);
-    (*prop)->nameoff = cpu_to_fdt32(namestroff);
-    (*prop)->len = cpu_to_fdt32(len);
-    return 0;
-}
-
-int fdt_set_name(void *fdt, int nodeoffset, const char *name)
-{
-    char *namep;
-    int oldlen, newlen;
-    int err;
-
-    FDT_RW_PROBE(fdt);
-
-    namep = (char *)(uintptr_t)fdt_get_name(fdt, nodeoffset, &oldlen);
-    if (!namep)
-        return oldlen;
-
-    newlen = strlen(name);
-
-    err = fdt_splice_struct_(fdt, namep, FDT_TAGALIGN(oldlen+1),
-                 FDT_TAGALIGN(newlen+1));
-    if (err)
-        return err;
-
-    memcpy(namep, name, newlen+1);
-    return 0;
-}
-
-int fdt_setprop_placeholder(void *fdt, int nodeoffset, const char *name,
-                int len, void **prop_data)
-{
-    struct fdt_property *prop;
-    int err;
-
-    FDT_RW_PROBE(fdt);
-
-    err = fdt_resize_property_(fdt, nodeoffset, name, len, &prop);
-    if (err == -FDT_ERR_NOTFOUND)
-        err = fdt_add_property_(fdt, nodeoffset, name, len, &prop);
-    if (err)
-        return err;
-
-    *prop_data = prop->data;
-    return 0;
-}
-
-int fdt_setprop(void *fdt, int nodeoffset, const char *name,
-        const void *val, int len)
-{
-    void *prop_data;
-    int err;
-
-    err = fdt_setprop_placeholder(fdt, nodeoffset, name, len, &prop_data);
-    if (err)
-        return err;
-
-    if (len)
-        memcpy(prop_data, val, len);
-    return 0;
-}
-
-int fdt_appendprop(void *fdt, int nodeoffset, const char *name,
-           const void *val, int len)
-{
-    struct fdt_property *prop;
-    int err, oldlen, newlen;
-
-    FDT_RW_PROBE(fdt);
-
-    prop = fdt_get_property_w(fdt, nodeoffset, name, &oldlen);
-    if (prop) {
-        newlen = len + oldlen;
-        err = fdt_splice_struct_(fdt, prop->data,
-                     FDT_TAGALIGN(oldlen),
-                     FDT_TAGALIGN(newlen));
-        if (err)
-            return err;
-        prop->len = cpu_to_fdt32(newlen);
-        memcpy(prop->data + oldlen, val, len);
-    } else {
-        err = fdt_add_property_(fdt, nodeoffset, name, len, &prop);
-        if (err)
-            return err;
-        memcpy(prop->data, val, len);
-    }
-    return 0;
-}
-
-int fdt_delprop(void *fdt, int nodeoffset, const char *name)
-{
-    struct fdt_property *prop;
-    int len, proplen;
-
-    FDT_RW_PROBE(fdt);
-
-    prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
-    if (!prop)
-        return len;
-
-    proplen = sizeof(*prop) + FDT_TAGALIGN(len);
-    return fdt_splice_struct_(fdt, prop, proplen, 0);
-}
-
-int fdt_add_subnode_namelen(void *fdt, int parentoffset,
-                const char *name, int namelen)
-{
-    struct fdt_node_header *nh;
-    int offset, nextoffset;
-    int nodelen;
-    int err;
-    uint32_t tag;
-    fdt32_t *endtag;
-
-    FDT_RW_PROBE(fdt);
-
-    offset = fdt_subnode_offset_namelen(fdt, parentoffset, name, namelen);
-    if (offset >= 0)
-        return -FDT_ERR_EXISTS;
-    else if (offset != -FDT_ERR_NOTFOUND)
-        return offset;
-
-    /* Try to place the new node after the parent's properties */
-    fdt_next_tag(fdt, parentoffset, &nextoffset); /* skip the BEGIN_NODE */
-    do {
-        offset = nextoffset;
-        tag = fdt_next_tag(fdt, offset, &nextoffset);
-    } while ((tag == FDT_PROP) || (tag == FDT_NOP));
-
-    nh = fdt_offset_ptr_w_(fdt, offset);
-    nodelen = sizeof(*nh) + FDT_TAGALIGN(namelen+1) + FDT_TAGSIZE;
-
-    err = fdt_splice_struct_(fdt, nh, 0, nodelen);
-    if (err)
-        return err;
-
-    nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
-    memset(nh->name, 0, FDT_TAGALIGN(namelen+1));
-    memcpy(nh->name, name, namelen);
-    endtag = (fdt32_t *)((char *)nh + nodelen - FDT_TAGSIZE);
-    *endtag = cpu_to_fdt32(FDT_END_NODE);
-
-    return offset;
-}
-
-int fdt_add_subnode(void *fdt, int parentoffset, const char *name)
-{
-    return fdt_add_subnode_namelen(fdt, parentoffset, name, strlen(name));
-}
-
-int fdt_del_node(void *fdt, int nodeoffset)
-{
-    int endoffset;
-
-    FDT_RW_PROBE(fdt);
-
-    endoffset = fdt_node_end_offset_(fdt, nodeoffset);
-    if (endoffset < 0)
-        return endoffset;
-
-    return fdt_splice_struct_(fdt, fdt_offset_ptr_w_(fdt, nodeoffset),
-                  endoffset - nodeoffset, 0);
-}
-
-static void fdt_packblocks_(const char *old, char *new,
-                int mem_rsv_size, int struct_size)
-{
-    int mem_rsv_off, struct_off, strings_off;
-
-    mem_rsv_off = FDT_ALIGN(sizeof(struct fdt_header), 8);
-    struct_off = mem_rsv_off + mem_rsv_size;
-    strings_off = struct_off + struct_size;
-
-    memmove(new + mem_rsv_off, old + fdt_off_mem_rsvmap(old), mem_rsv_size);
-    fdt_set_off_mem_rsvmap(new, mem_rsv_off);
-
-    memmove(new + struct_off, old + fdt_off_dt_struct(old), struct_size);
-    fdt_set_off_dt_struct(new, struct_off);
-    fdt_set_size_dt_struct(new, struct_size);
-
-    memmove(new + strings_off, old + fdt_off_dt_strings(old),
-        fdt_size_dt_strings(old));
-    fdt_set_off_dt_strings(new, strings_off);
-    fdt_set_size_dt_strings(new, fdt_size_dt_strings(old));
-}
-
-int fdt_open_into(const void *fdt, void *buf, int bufsize)
-{
-    int err;
-    int mem_rsv_size, struct_size;
-    int newsize;
-    const char *fdtstart = fdt;
-    const char *fdtend = fdtstart + fdt_totalsize(fdt);
-    char *tmp;
-
-    FDT_RO_PROBE(fdt);
-
-    mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
-        * sizeof(struct fdt_reserve_entry);
-
-    if (fdt_version(fdt) >= 17) {
-        struct_size = fdt_size_dt_struct(fdt);
-    } else {
-        struct_size = 0;
-        while (fdt_next_tag(fdt, struct_size, &struct_size) != FDT_END)
-            ;
-        if (struct_size < 0)
-            return struct_size;
-    }
-
-    if (!fdt_blocks_misordered_(fdt, mem_rsv_size, struct_size)) {
-        /* no further work necessary */
-        err = fdt_move(fdt, buf, bufsize);
-        if (err)
-            return err;
-        fdt_set_version(buf, 17);
-        fdt_set_size_dt_struct(buf, struct_size);
-        fdt_set_totalsize(buf, bufsize);
-        return 0;
-    }
-
-    /* Need to reorder */
-    newsize = FDT_ALIGN(sizeof(struct fdt_header), 8) + mem_rsv_size
-        + struct_size + fdt_size_dt_strings(fdt);
-
-    if (bufsize < newsize)
-        return -FDT_ERR_NOSPACE;
-
-    /* First attempt to build converted tree at beginning of buffer */
-    tmp = buf;
-    /* But if that overlaps with the old tree... */
-    if (((tmp + newsize) > fdtstart) && (tmp < fdtend)) {
-        /* Try right after the old tree instead */
-        tmp = (char *)(uintptr_t)fdtend;
-        if ((tmp + newsize) > ((char *)buf + bufsize))
-            return -FDT_ERR_NOSPACE;
-    }
-
-    fdt_packblocks_(fdt, tmp, mem_rsv_size, struct_size);
-    memmove(buf, tmp, newsize);
-
-    fdt_set_magic(buf, FDT_MAGIC);
-    fdt_set_totalsize(buf, bufsize);
-    fdt_set_version(buf, 17);
-    fdt_set_last_comp_version(buf, 16);
-    fdt_set_boot_cpuid_phys(buf, fdt_boot_cpuid_phys(fdt));
-
-    return 0;
-}
-
-int fdt_pack(void *fdt)
-{
-    int mem_rsv_size;
-
-    FDT_RW_PROBE(fdt);
-
-    mem_rsv_size = (fdt_num_mem_rsv(fdt)+1)
-        * sizeof(struct fdt_reserve_entry);
-    fdt_packblocks_(fdt, fdt, mem_rsv_size, fdt_size_dt_struct(fdt));
-    fdt_set_totalsize(fdt, fdt_data_size_(fdt));
-
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c
deleted file mode 100644
index 92853fe6a2..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_strerror.c
+++ /dev/null
@@ -1,81 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-struct fdt_errtabent {
-    const char *str;
-};
-
-#define FDT_ERRTABENT(val) \
-    [(val)] = { .str = #val, }
-
-static struct fdt_errtabent fdt_errtable[] = {
-    FDT_ERRTABENT(FDT_ERR_NOTFOUND),
-    FDT_ERRTABENT(FDT_ERR_EXISTS),
-    FDT_ERRTABENT(FDT_ERR_NOSPACE),
-
-    FDT_ERRTABENT(FDT_ERR_BADOFFSET),
-    FDT_ERRTABENT(FDT_ERR_BADPATH),
-    FDT_ERRTABENT(FDT_ERR_BADPHANDLE),
-    FDT_ERRTABENT(FDT_ERR_BADSTATE),
-
-    FDT_ERRTABENT(FDT_ERR_TRUNCATED),
-    FDT_ERRTABENT(FDT_ERR_BADMAGIC),
-    FDT_ERRTABENT(FDT_ERR_BADVERSION),
-    FDT_ERRTABENT(FDT_ERR_BADSTRUCTURE),
-    FDT_ERRTABENT(FDT_ERR_BADLAYOUT),
-    FDT_ERRTABENT(FDT_ERR_INTERNAL),
-    FDT_ERRTABENT(FDT_ERR_BADNCELLS),
-    FDT_ERRTABENT(FDT_ERR_BADVALUE),
-    FDT_ERRTABENT(FDT_ERR_BADOVERLAY),
-    FDT_ERRTABENT(FDT_ERR_NOPHANDLES),
-};
-#define FDT_ERRTABSIZE  (sizeof(fdt_errtable) / sizeof(fdt_errtable[0]))
-
-const char *fdt_strerror(int errval)
-{
-    if (errval > 0)
-        return "";
-    else if (errval == 0)
-        return "";
-    else if (errval > -FDT_ERRTABSIZE) {
-        const char *s = fdt_errtable[-errval].str;
-
-        if (s)
-            return s;
-    }
-
-    return "";
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c
deleted file mode 100644
index a16d4c3f38..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_sw.c
+++ /dev/null
@@ -1,344 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-static int fdt_sw_probe_(void *fdt)
-{
-    if (fdt_magic(fdt) == FDT_MAGIC)
-        return -FDT_ERR_BADSTATE;
-    else if (fdt_magic(fdt) != FDT_SW_MAGIC)
-        return -FDT_ERR_BADMAGIC;
-    return 0;
-}
-
-#define FDT_SW_PROBE(fdt) \
-    { \
-        int err; \
-        if ((err = fdt_sw_probe_(fdt)) != 0) \
-            return err; \
-    }
-
-/* 'memrsv' state:  Initial state after fdt_create()
- *
- * Allowed functions:
- *  fdt_add_reservmap_entry()
- *  fdt_finish_reservemap()     [moves to 'struct' state]
- */
-static int fdt_sw_probe_memrsv_(void *fdt)
-{
-    int err = fdt_sw_probe_(fdt);
-    if (err)
-        return err;
-
-    if (fdt_off_dt_strings(fdt) != 0)
-        return -FDT_ERR_BADSTATE;
-    return 0;
-}
-
-#define FDT_SW_PROBE_MEMRSV(fdt) \
-    { \
-        int err; \
-        if ((err = fdt_sw_probe_memrsv_(fdt)) != 0) \
-            return err; \
-    }
-
-/* 'struct' state:  Enter this state after fdt_finish_reservemap()
- *
- * Allowed functions:
- *  fdt_begin_node()
- *  fdt_end_node()
- *  fdt_property*()
- *  fdt_finish()            [moves to 'complete' state]
- */
-static int fdt_sw_probe_struct_(void *fdt)
-{
-    int err = fdt_sw_probe_(fdt);
-    if (err)
-        return err;
-
-    if (fdt_off_dt_strings(fdt) != fdt_totalsize(fdt))
-        return -FDT_ERR_BADSTATE;
-    return 0;
-}
-
-#define FDT_SW_PROBE_STRUCT(fdt) \
-    { \
-        int err; \
-        if ((err = fdt_sw_probe_struct_(fdt)) != 0) \
-            return err; \
-    }
-
-/* 'complete' state:    Enter this state after fdt_finish()
- *
- * Allowed functions: none
- */
-
-static void *fdt_grab_space_(void *fdt, size_t len)
-{
-    int offset = fdt_size_dt_struct(fdt);
-    int spaceleft;
-
-    spaceleft = fdt_totalsize(fdt) - fdt_off_dt_struct(fdt)
-        - fdt_size_dt_strings(fdt);
-
-    if ((offset + len < offset) || (offset + len > spaceleft))
-        return NULL;
-
-    fdt_set_size_dt_struct(fdt, offset + len);
-    return fdt_offset_ptr_w_(fdt, offset);
-}
-
-int fdt_create(void *buf, int bufsize)
-{
-    const size_t hdrsize = FDT_ALIGN(sizeof(struct fdt_header),
-                     sizeof(struct fdt_reserve_entry));
-    void *fdt = buf;
-
-    if (bufsize < hdrsize)
-        return -FDT_ERR_NOSPACE;
-
-    memset(buf, 0, bufsize);
-
-    fdt_set_magic(fdt, FDT_SW_MAGIC);
-    fdt_set_version(fdt, FDT_LAST_SUPPORTED_VERSION);
-    fdt_set_last_comp_version(fdt, FDT_FIRST_SUPPORTED_VERSION);
-    fdt_set_totalsize(fdt,  bufsize);
-
-    fdt_set_off_mem_rsvmap(fdt, hdrsize);
-    fdt_set_off_dt_struct(fdt, fdt_off_mem_rsvmap(fdt));
-    fdt_set_off_dt_strings(fdt, 0);
-
-    return 0;
-}
-
-int fdt_resize(void *fdt, void *buf, int bufsize)
-{
-    size_t headsize, tailsize;
-    char *oldtail, *newtail;
-
-    FDT_SW_PROBE(fdt);
-
-    headsize = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
-    tailsize = fdt_size_dt_strings(fdt);
-
-    if ((headsize + tailsize) > fdt_totalsize(fdt))
-        return -FDT_ERR_INTERNAL;
-
-    if ((headsize + tailsize) > bufsize)
-        return -FDT_ERR_NOSPACE;
-
-    oldtail = (char *)fdt + fdt_totalsize(fdt) - tailsize;
-    newtail = (char *)buf + bufsize - tailsize;
-
-    /* Two cases to avoid clobbering data if the old and new
-     * buffers partially overlap */
-    if (buf <= fdt) {
-        memmove(buf, fdt, headsize);
-        memmove(newtail, oldtail, tailsize);
-    } else {
-        memmove(newtail, oldtail, tailsize);
-        memmove(buf, fdt, headsize);
-    }
-
-    fdt_set_totalsize(buf, bufsize);
-    if (fdt_off_dt_strings(buf))
-        fdt_set_off_dt_strings(buf, bufsize);
-
-    return 0;
-}
-
-int fdt_add_reservemap_entry(void *fdt, uint64_t addr, uint64_t size)
-{
-    struct fdt_reserve_entry *re;
-    int offset;
-
-    FDT_SW_PROBE_MEMRSV(fdt);
-
-    offset = fdt_off_dt_struct(fdt);
-    if ((offset + sizeof(*re)) > fdt_totalsize(fdt))
-        return -FDT_ERR_NOSPACE;
-
-    re = (struct fdt_reserve_entry *)((char *)fdt + offset);
-    re->address = cpu_to_fdt64(addr);
-    re->size = cpu_to_fdt64(size);
-
-    fdt_set_off_dt_struct(fdt, offset + sizeof(*re));
-
-    return 0;
-}
-
-int fdt_finish_reservemap(void *fdt)
-{
-    int err = fdt_add_reservemap_entry(fdt, 0, 0);
-
-    if (err)
-        return err;
-
-    fdt_set_off_dt_strings(fdt, fdt_totalsize(fdt));
-    return 0;
-}
-
-int fdt_begin_node(void *fdt, const char *name)
-{
-    struct fdt_node_header *nh;
-    int namelen;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    namelen = strlen(name) + 1;
-    nh = fdt_grab_space_(fdt, sizeof(*nh) + FDT_TAGALIGN(namelen));
-    if (! nh)
-        return -FDT_ERR_NOSPACE;
-
-    nh->tag = cpu_to_fdt32(FDT_BEGIN_NODE);
-    memcpy(nh->name, name, namelen);
-    return 0;
-}
-
-int fdt_end_node(void *fdt)
-{
-    fdt32_t *en;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    en = fdt_grab_space_(fdt, FDT_TAGSIZE);
-    if (! en)
-        return -FDT_ERR_NOSPACE;
-
-    *en = cpu_to_fdt32(FDT_END_NODE);
-    return 0;
-}
-
-static int fdt_find_add_string_(void *fdt, const char *s)
-{
-    char *strtab = (char *)fdt + fdt_totalsize(fdt);
-    const char *p;
-    int strtabsize = fdt_size_dt_strings(fdt);
-    int len = strlen(s) + 1;
-    int struct_top, offset;
-
-    p = fdt_find_string_(strtab - strtabsize, strtabsize, s);
-    if (p)
-        return p - strtab;
-
-    /* Add it */
-    offset = -strtabsize - len;
-    struct_top = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
-    if (fdt_totalsize(fdt) + offset < struct_top)
-        return 0; /* no more room :( */
-
-    memcpy(strtab + offset, s, len);
-    fdt_set_size_dt_strings(fdt, strtabsize + len);
-    return offset;
-}
-
-int fdt_property_placeholder(void *fdt, const char *name, int len, void **valp)
-{
-    struct fdt_property *prop;
-    int nameoff;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    nameoff = fdt_find_add_string_(fdt, name);
-    if (nameoff == 0)
-        return -FDT_ERR_NOSPACE;
-
-    prop = fdt_grab_space_(fdt, sizeof(*prop) + FDT_TAGALIGN(len));
-    if (! prop)
-        return -FDT_ERR_NOSPACE;
-
-    prop->tag = cpu_to_fdt32(FDT_PROP);
-    prop->nameoff = cpu_to_fdt32(nameoff);
-    prop->len = cpu_to_fdt32(len);
-    *valp = prop->data;
-    return 0;
-}
-
-int fdt_property(void *fdt, const char *name, const void *val, int len)
-{
-    void *ptr;
-    int ret;
-
-    ret = fdt_property_placeholder(fdt, name, len, &ptr);
-    if (ret)
-        return ret;
-    memcpy(ptr, val, len);
-    return 0;
-}
-
-int fdt_finish(void *fdt)
-{
-    char *p = (char *)fdt;
-    fdt32_t *end;
-    int oldstroffset, newstroffset;
-    uint32_t tag;
-    int offset, nextoffset;
-
-    FDT_SW_PROBE_STRUCT(fdt);
-
-    /* Add terminator */
-    end = fdt_grab_space_(fdt, sizeof(*end));
-    if (! end)
-        return -FDT_ERR_NOSPACE;
-    *end = cpu_to_fdt32(FDT_END);
-
-    /* Relocate the string table */
-    oldstroffset = fdt_totalsize(fdt) - fdt_size_dt_strings(fdt);
-    newstroffset = fdt_off_dt_struct(fdt) + fdt_size_dt_struct(fdt);
-    memmove(p + newstroffset, p + oldstroffset, fdt_size_dt_strings(fdt));
-    fdt_set_off_dt_strings(fdt, newstroffset);
-
-    /* Walk the structure, correcting string offsets */
-    offset = 0;
-    while ((tag = fdt_next_tag(fdt, offset, &nextoffset)) != FDT_END) {
-        if (tag == FDT_PROP) {
-            struct fdt_property *prop =
-                fdt_offset_ptr_w_(fdt, offset);
-            int nameoff;
-
-            nameoff = fdt32_to_cpu(prop->nameoff);
-            nameoff += fdt_size_dt_strings(fdt);
-            prop->nameoff = cpu_to_fdt32(nameoff);
-        }
-        offset = nextoffset;
-    }
-    if (nextoffset < 0)
-        return nextoffset;
-
-    /* Finally, adjust the header */
-    fdt_set_totalsize(fdt, newstroffset + fdt_size_dt_strings(fdt));
-    fdt_set_magic(fdt, FDT_MAGIC);
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c b/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c
deleted file mode 100644
index e97f282851..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/src/fdt_wip.c
+++ /dev/null
@@ -1,118 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "libfdt_env.h"
-
-#include 
-#include 
-
-#include "libfdt_internal.h"
-
-int fdt_setprop_inplace_namelen_partial(void *fdt, int nodeoffset,
-                    const char *name, int namelen,
-                    uint32_t idx, const void *val,
-                    int len)
-{
-    void *propval;
-    int proplen;
-
-    propval = fdt_getprop_namelen_w(fdt, nodeoffset, name, namelen,
-                    &proplen);
-    if (!propval)
-        return proplen;
-
-    if (proplen < (len + idx))
-        return -FDT_ERR_NOSPACE;
-
-    memcpy((char *)propval + idx, val, len);
-    return 0;
-}
-
-int fdt_setprop_inplace(void *fdt, int nodeoffset, const char *name,
-            const void *val, int len)
-{
-    const void *propval;
-    int proplen;
-
-    propval = fdt_getprop(fdt, nodeoffset, name, &proplen);
-    if (!propval)
-        return proplen;
-
-    if (proplen != len)
-        return -FDT_ERR_NOSPACE;
-
-    return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name,
-                           strlen(name), 0,
-                           val, len);
-}
-
-static void fdt_nop_region_(void *start, int len)
-{
-    fdt32_t *p;
-
-    for (p = start; (char *)p < ((char *)start + len); p++)
-        *p = cpu_to_fdt32(FDT_NOP);
-}
-
-int fdt_nop_property(void *fdt, int nodeoffset, const char *name)
-{
-    struct fdt_property *prop;
-    int len;
-
-    prop = fdt_get_property_w(fdt, nodeoffset, name, &len);
-    if (!prop)
-        return len;
-
-    fdt_nop_region_(prop, len + sizeof(*prop));
-
-    return 0;
-}
-
-int fdt_node_end_offset_(void *fdt, int offset)
-{
-    int depth = 0;
-
-    while ((offset >= 0) && (depth >= 0))
-        offset = fdt_next_node(fdt, offset, &depth);
-
-    return offset;
-}
-
-int fdt_nop_node(void *fdt, int nodeoffset)
-{
-    int endoffset;
-
-    endoffset = fdt_node_end_offset_(fdt, nodeoffset);
-    if (endoffset < 0)
-        return endoffset;
-
-    fdt_nop_region_(fdt_offset_ptr_w(fdt, nodeoffset, 0),
-            endoffset - nodeoffset);
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c b/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c
deleted file mode 100644
index e0e7ddd421..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/blfdt_cli_test.c
+++ /dev/null
@@ -1,67 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-
-#include 
-#include 
-
-static void blfdt(char *buf, int len, int argc, char **argv)
-{
-    int tc_fdt_wifi(void);
-    int tc_blfdtdump(void);
-
-    tc_fdt_wifi();
-    tc_blfdtdump();
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-// STATIC_CLI_CMD_ATTRIBUTE makes this(these) command(s) static
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-    { "blfdt", "blfdt", blfdt}
-};
-#endif
-
-int blfdt_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user)/sizeof(cmds_user[0]));
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c
deleted file mode 100644
index a352974456..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_dump.c
+++ /dev/null
@@ -1,766 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-/*
- * fdtdump.c - Contributed by Pantelis Antoniou 
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-
-#include 
-// #include "log/log.h"
-
-#define FDT_MAGIC_SIZE    4
-#define MAX_VERSION 17
-
-#define ALIGN(x, a)    (((x) + ((a) - 1)) & ~((a) - 1))
-#define PALIGN(p, a)    ((void *)(ALIGN((unsigned long)(p), (a))))
-#define GET_CELL(p)    (p += 4, *((const fdt32_t *)(p-4)))
-
-#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
-
-static const char *tagname(uint32_t tag)
-{
-    static const char * const names[] = {
-#define TN(t) [t] = #t
-        TN(FDT_BEGIN_NODE),
-        TN(FDT_END_NODE),
-        TN(FDT_PROP),
-        TN(FDT_NOP),
-        TN(FDT_END),
-#undef TN
-    };
-    if (tag < ARRAY_SIZE(names)) {
-        if (names[tag]) {
-            return names[tag];
-        }
-    }
-
-    return "FDT_???";
-}
-
-#define dumpf(fmt, args...) \
-    do { if (debug) printf("// " fmt, ## args); } while (0)
-
-bool util_is_printable_string(const void *data, int len)
-{
-    const char *s = data;
-    const char *ss, *se;
-
-    /* zero length is not */
-    if (len == 0) {
-        return 0;
-    }
-
-    /* must terminate with zero */
-    if (s[len - 1] != '\0') {
-        return 0;
-    }
-
-    se = s + len;
-
-    while (s < se) {
-        ss = s;
-        while (s < se && *s && isprint((unsigned char)*s)) {
-            s++;
-        }
-
-        /* not zero, or not done yet */
-        if (*s != '\0' || s == ss) {
-            return 0;
-        }
-
-        s++;
-    }
-
-    return 1;
-}
-
-void utilfdt_print_data(const char *data, int len)
-{
-    int i;
-    const char *s;
-
-    /* no data, don't print */
-    if (len == 0) {
-        return;
-    }
-
-    if (util_is_printable_string(data, len)) {
-        printf(" = ");
-
-        s = data;
-        do {
-            printf("\"%s\"", s);
-            s += strlen(s) + 1;
-            if (s < data + len)
-                printf(", ");
-        } while (s < data + len);
-
-    } else if ((len % 4) == 0) {
-        const fdt32_t *cell = (const fdt32_t *)data;
-
-        printf(" = <");
-        for (i = 0, len /= 4; i < len; i++) {
-            printf("0x%08x%s", (unsigned int)fdt32_to_cpu(cell[i]),
-                   i < (len - 1) ? " " : "");
-        }
-        printf(">");
-    } else {
-        const unsigned char *p = (const unsigned char *)data;
-        printf(" = [");
-        for (i = 0; i < len; i++) {
-            printf("%02x%s", *p++, i < len - 1 ? " " : "");
-        }
-        printf("]");
-    }
-}
-
-static void dump_blob(void *blob, bool debug)
-{
-    uintptr_t blob_off = (uintptr_t)blob;
-    struct fdt_header *bph = blob;
-    uint32_t off_mem_rsvmap = fdt32_to_cpu(bph->off_mem_rsvmap);
-    uint32_t off_dt = fdt32_to_cpu(bph->off_dt_struct);
-    uint32_t off_str = fdt32_to_cpu(bph->off_dt_strings);
-    struct fdt_reserve_entry *p_rsvmap =
-        (struct fdt_reserve_entry *)((char *)blob + off_mem_rsvmap);
-    const char *p_struct = (const char *)blob + off_dt;
-    const char *p_strings = (const char *)blob + off_str;
-    uint32_t version = fdt32_to_cpu(bph->version);
-    uint32_t totalsize = fdt32_to_cpu(bph->totalsize);
-    uint32_t tag;
-    const char *p, *s, *t;
-    int depth, sz, shift;
-    int i;
-    uint64_t addr, size;
-
-    depth = 0;
-    shift = 4;
-
-    printf("/dts-v1/;\r\n");
-    printf("// magic:\t\t0x%"PRIx32"\r\n", fdt32_to_cpu(bph->magic));
-    printf("// totalsize:\t\t0x%"PRIx32" (%"PRIu32")\r\n",
-           totalsize, totalsize);
-    printf("// off_dt_struct:\t0x%"PRIx32"\r\n", off_dt);
-    printf("// off_dt_strings:\t0x%"PRIx32"\r\n", off_str);
-    printf("// off_mem_rsvmap:\t0x%"PRIx32"\r\n", off_mem_rsvmap);
-    printf("// version:\t\t%"PRIu32"\r\n", version);
-    printf("// last_comp_version:\t%"PRIu32"\r\n",
-           fdt32_to_cpu(bph->last_comp_version));
-    if (version >= 2) {
-        printf("// boot_cpuid_phys:\t0x%"PRIx32"\r\n",
-               fdt32_to_cpu(bph->boot_cpuid_phys));
-    }
-
-    if (version >= 3) {
-        printf("// size_dt_strings:\t0x%"PRIx32"\r\n",
-               fdt32_to_cpu(bph->size_dt_strings));
-    }
-
-    if (version >= 17) {
-        printf("// size_dt_struct:\t0x%"PRIx32"\r\n",
-               fdt32_to_cpu(bph->size_dt_struct));
-    }
-
-    printf("\r\n");
-
-    for (i = 0; ; i++) {
-        addr = fdt64_to_cpu(p_rsvmap[i].address);
-        size = fdt64_to_cpu(p_rsvmap[i].size);
-        if (addr == 0 && size == 0)
-            break;
-
-        printf("/memreserve/ %#"PRIx64" %#"PRIx64";\r\n",
-               addr, size);
-    }
-
-    p = p_struct;
-
-    // uint32_t index = 0;
-    while ((tag = fdt32_to_cpu(GET_CELL(p))) != FDT_END) {
-
-        // printf("index = %d\r\n", index++);
-        dumpf("%04"PRIxPTR": tag: 0x%08"PRIx32" (%s)\r\n",
-                (uintptr_t)p - blob_off - 4, tag, tagname(tag));
-
-        if (tag == FDT_BEGIN_NODE) {
-            s = p;
-            p = PALIGN(p + strlen(s) + 1, 4);
-
-            if (*s == '\0')
-                s = "/";
-
-            printf("%*s%s {\r\n", depth * shift, "", s);
-
-            depth++;
-            continue;
-        }
-
-        if (tag == FDT_END_NODE) {
-            depth--;
-
-            printf("%*s};\r\n", depth * shift, "");
-            continue;
-        }
-
-        if (tag == FDT_NOP) {
-            printf("%*s// [NOP]\r\n", depth * shift, "");
-            continue;
-        }
-
-        if (tag != FDT_PROP) {
-            log_error("%*s ** Unknown tag 0x%08"PRIx32"\r\n", depth * shift, "", tag);
-            break;
-        }
-        sz = fdt32_to_cpu(GET_CELL(p));
-        s = p_strings + fdt32_to_cpu(GET_CELL(p));
-        if (version < 16 && sz >= 8)
-            p = PALIGN(p, 8);
-        t = p;
-
-        p = PALIGN(p + sz, 4);
-
-        dumpf("%04"PRIxPTR": string: %s\r\n", (uintptr_t)s - blob_off, s);
-        dumpf("%04"PRIxPTR": value\r\n", (uintptr_t)t - blob_off);
-        printf("%*s%s", depth * shift, "", s);
-        utilfdt_print_data(t, sz);
-        printf(";\r\n");
-    }
-}
-
-
-static bool valid_header(char *p, uint32_t len)
-{
-    if (len < sizeof(struct fdt_header) ||
-        fdt_magic(p) != FDT_MAGIC ||
-        fdt_version(p) > MAX_VERSION ||
-        fdt_last_comp_version(p) > MAX_VERSION ||
-        fdt_totalsize(p) >= len ||
-        fdt_off_dt_struct(p) >= len ||
-        fdt_off_dt_strings(p) >= len) {
-            return 0;
-        }
-        return 1;
-}
-/*
-  input_buf
-  input_len
-  debug   Dump debug information while decoding the file
-  scan    Scan for an embedded fdt in file
-*/
-
-static int blfdtdump(const unsigned char *input_buf, const uint32_t input_len, uint8_t arg_debug, uint8_t arg_scan)
-{
-    const char *file = "fdtbuff";
-    char *buf = (char *)input_buf;
-    uint8_t debug = arg_debug;
-    uint8_t scan = arg_scan;
-    uint32_t len = (uint32_t)input_len;
-    uint32_t this_len = 0;
-
-    // log_info("**** fdtdump is a low-level debugging tool, not meant for general use.\r\n"
-    //         "**** If you want to decompile a dtb, you probably want\r\n"
-    //         "****     dtc -I dtb -O dts \r\n\r\n"
-    //     );
-
-    /* try and locate an embedded fdt in a bigger blob */
-    if (scan) {
-        unsigned char smagic[FDT_MAGIC_SIZE];
-        char *p = buf;
-        char *endp = buf + len;
-
-        fdt_set_magic(smagic, FDT_MAGIC);
-
-        /* poor man's memmem */
-        while ((endp - p) >= FDT_MAGIC_SIZE) {
-            p = memchr(p, smagic[0], endp - p - FDT_MAGIC_SIZE);
-            if (!p) {
-                break;
-            }
-            if (fdt_magic(p) == FDT_MAGIC) {
-                /* try and validate the main struct */
-                this_len = endp - p;
-                if (valid_header(p, this_len)) {
-                    break;
-                }
-                if (debug) {
-                    printf("%s: skipping fdt magic at offset %#tx\r\n",
-                        file, p - buf);
-                }
-            }
-            ++p;
-        }
-        if (!p || endp - p < sizeof(struct fdt_header)) {
-            log_error("%s: could not locate fdt magic\r\n", file);
-            return -1;
-        }
-        printf("%s: found fdt at offset %#tx\r\n", file, p - buf);
-        buf = p;
-    } else if (!valid_header(buf, len)) {
-        log_error("%s: header is not valid\r\n", file);
-        return -1;
-    }
-
-    log_info("dump_blob.");
-
-    dump_blob(buf, debug);
-
-    return 0;
-}
-
-#define TC_WIFI_DTB_LEN    (4779 + 4)
-const uint8_t tc_wifi_dtb[TC_WIFI_DTB_LEN] = {
-  0xd0, 0x0d, 0xfe, 0xed, 0x00, 0x00, 0x12, 0xab, 0x00, 0x00, 0x00, 0x38,
-  0x00, 0x00, 0x10, 0xc0, 0x00, 0x00, 0x00, 0x28, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xeb,
-  0x00, 0x00, 0x10, 0x88, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x13,
-  0x00, 0x00, 0x00, 0x00, 0x62, 0x6c, 0x20, 0x62, 0x6c, 0x36, 0x30, 0x78,
-  0x20, 0x41, 0x56, 0x42, 0x20, 0x62, 0x6f, 0x61, 0x72, 0x64, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x2c, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x2d, 0x73, 0x61, 0x6d,
-  0x70, 0x6c, 0x65, 0x00, 0x62, 0x6c, 0x2c, 0x62, 0x6c, 0x36, 0x30, 0x78,
-  0x2d, 0x63, 0x6f, 0x6d, 0x6d, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x69, 0x70, 0x63, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
-  0x69, 0x70, 0x63, 0x40, 0x34, 0x30, 0x30, 0x31, 0x43, 0x30, 0x30, 0x30,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0xc0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x69, 0x32, 0x73, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
-  0x69, 0x32, 0x73, 0x40, 0x34, 0x30, 0x30, 0x31, 0x37, 0x30, 0x30, 0x30,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
-  0x00, 0x00, 0x00, 0x2c, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32, 0x73, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0x70, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x37, 0x6f, 0x6b, 0x61, 0x79,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x41,
-  0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x69, 0x32, 0x73, 0x40, 0x34, 0x30, 0x30, 0x31,
-  0x37, 0x31, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c, 0x6f, 0x6b, 0x61, 0x79,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a,
-  0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32,
-  0x73, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x71, 0x00, 0x00, 0x00, 0x01, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x37,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x01,
-  0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x46, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x4b, 0x00, 0x00, 0x00, 0x1d,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x4e,
-  0x00, 0x00, 0x00, 0x1e, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x51, 0x00, 0x00, 0x00, 0x1f, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x69, 0x32, 0x63, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x01, 0x69, 0x32, 0x63, 0x40, 0x34, 0x30, 0x30, 0x31,
-  0x31, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c, 0x6f, 0x6b, 0x61, 0x79,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a,
-  0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32,
-  0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x10, 0x00, 0x00, 0x00, 0x01, 0x00,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x54, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x58,
-  0x00, 0x00, 0x00, 0x0d, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x64, 0x65, 0x76, 0x69, 0x63, 0x65, 0x73, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x5c, 0x00, 0x00, 0x00, 0x18,
-  0x00, 0x00, 0x00, 0x21, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x17,
-  0x00, 0x00, 0x00, 0x66, 0x69, 0x32, 0x63, 0x5f, 0x65, 0x73, 0x38, 0x33,
-  0x31, 0x31, 0x00, 0x69, 0x32, 0x63, 0x5f, 0x67, 0x63, 0x30, 0x33, 0x30,
-  0x38, 0x3e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x69, 0x32, 0x63, 0x40, 0x34, 0x30, 0x30, 0x31,
-  0x31, 0x31, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61,
-  0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a,
-  0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x69, 0x32,
-  0x63, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x11, 0x00, 0x00, 0x00, 0x01, 0x00,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x6d, 0x6a, 0x70, 0x65, 0x67, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x6d, 0x6a, 0x70, 0x65,
-  0x67, 0x40, 0x34, 0x30, 0x30, 0x31, 0x36, 0x30, 0x30, 0x30, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c,
-  0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30,
-  0x78, 0x5f, 0x6d, 0x6a, 0x70, 0x65, 0x67, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x60, 0x00,
-  0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x74, 0x69, 0x6d, 0x65, 0x72, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
-  0x74, 0x69, 0x6d, 0x65, 0x72, 0x40, 0x34, 0x30, 0x30, 0x31, 0x34, 0x30,
-  0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x74, 0x69, 0x6d, 0x65, 0x72, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0x40, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x74, 0x69, 0x6d, 0x65, 0x72, 0x40, 0x34, 0x30,
-  0x30, 0x31, 0x34, 0x31, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61,
-  0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0c,
-  0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x74, 0x69,
-  0x6d, 0x65, 0x72, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x41, 0x00, 0x00, 0x00, 0x01, 0x00,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x70, 0x77, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x77, 0x6d, 0x40, 0x34, 0x30, 0x30, 0x31,
-  0x32, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61,
-  0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a,
-  0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x70, 0x77,
-  0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x33, 0x40, 0x01, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x75, 0x61, 0x72, 0x74, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x75, 0x61, 0x72, 0x74,
-  0x40, 0x34, 0x30, 0x30, 0x31, 0x30, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x2c,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x75, 0x61, 0x72, 0x74, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x75,
-  0x2f, 0x64, 0x65, 0x76, 0x2f, 0x74, 0x74, 0x79, 0x53, 0x30, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x7a, 0x00, 0x01, 0xc2, 0x00,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x66, 0x65, 0x61, 0x74, 0x75, 0x72, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x7e,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, 0x64, 0x69, 0x73, 0x61,
-  0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x86, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x89,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x75, 0x61, 0x72, 0x74,
-  0x40, 0x34, 0x30, 0x30, 0x31, 0x30, 0x31, 0x30, 0x30, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x2c,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x75, 0x61, 0x72, 0x74, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x75,
-  0x2f, 0x64, 0x65, 0x76, 0x2f, 0x74, 0x74, 0x79, 0x53, 0x31, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8c, 0x00, 0x01, 0xc2, 0x00,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x66, 0x65, 0x61, 0x74, 0x75, 0x72, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x7e,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82, 0x64, 0x69, 0x73, 0x61,
-  0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x86, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x89,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x75, 0x61, 0x72, 0x74,
-  0x40, 0x34, 0x30, 0x30, 0x31, 0x30, 0x32, 0x30, 0x30, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c,
-  0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x72, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x06,
-  0x62, 0x6c, 0x36, 0x30, 0x78, 0x5f, 0x75, 0x61, 0x72, 0x74, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0b, 0x00, 0x00, 0x00, 0x75,
-  0x2f, 0x64, 0x65, 0x76, 0x2f, 0x74, 0x74, 0x79, 0x53, 0x32, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x01, 0x02, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x8c, 0x00, 0x4c, 0x4b, 0x40,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x89, 0x00, 0x00, 0x00, 0x0e,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x86,
-  0x00, 0x00, 0x00, 0x07, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x66, 0x65, 0x61, 0x74, 0x75, 0x72, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x89, 0x6f, 0x6b, 0x61, 0x79,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05,
-  0x00, 0x00, 0x00, 0x86, 0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x82,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x7e, 0x64, 0x69, 0x73, 0x61,
-  0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x73, 0x70, 0x69, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
-  0x73, 0x70, 0x69, 0x40, 0x34, 0x30, 0x30, 0x30, 0x46, 0x30, 0x30, 0x30,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08,
-  0x00, 0x00, 0x00, 0x2c, 0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33,
-  0x40, 0x00, 0xf0, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x67, 0x70, 0x69, 0x70,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x01, 0x61, 0x64, 0x63, 0x5f, 0x6b, 0x65, 0x79, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c,
-  0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x09,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x99,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x14,
-  0x00, 0x00, 0x00, 0xa3, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x64,
-  0x00, 0x00, 0x01, 0x90, 0x00, 0x00, 0x01, 0x2c, 0x00, 0x00, 0x01, 0xf4,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0xab,
-  0x53, 0x57, 0x31, 0x00, 0x53, 0x57, 0x32, 0x00, 0x53, 0x57, 0x33, 0x00,
-  0x53, 0x57, 0x34, 0x00, 0x53, 0x57, 0x35, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0xb3, 0x55, 0x73, 0x72, 0x31,
-  0x00, 0x55, 0x73, 0x72, 0x32, 0x00, 0x53, 0x74, 0x61, 0x72, 0x74, 0x00,
-  0x55, 0x70, 0x00, 0x44, 0x6f, 0x77, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0xbd, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x70, 0x64, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x70, 0x64, 0x6d, 0x40,
-  0x34, 0x30, 0x30, 0x30, 0x43, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x2c,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33, 0x40, 0x00, 0xc0, 0x00,
-  0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x63, 0x61, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x63, 0x61, 0x6d, 0x40,
-  0x34, 0x30, 0x30, 0x30, 0x42, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c,
-  0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30,
-  0x78, 0x5f, 0x63, 0x61, 0x6d, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33, 0x40, 0x00, 0xb0, 0x00,
-  0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xc5,
-  0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0xcd, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xd7, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xe0,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0xe9, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xf2, 0x00, 0x00, 0x00, 0x05,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0xfb,
-  0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x01, 0x04, 0x00, 0x00, 0x00, 0x19, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x0d, 0x00, 0x00, 0x00, 0x1a,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x16,
-  0x00, 0x00, 0x00, 0x1b, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x01, 0x1f, 0x00, 0x00, 0x00, 0x1c, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x28, 0x00, 0x00, 0x00, 0x0f,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x31,
-  0x00, 0x00, 0x00, 0x18, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x66, 0x65, 0x61, 0x74, 0x75, 0x72, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x09, 0x00, 0x00, 0x01, 0x3d, 0x48, 0x41, 0x52, 0x44,
-  0x57, 0x41, 0x52, 0x45, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x63, 0x6f, 0x6e, 0x66, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x01, 0x42,
-  0x61, 0x75, 0x74, 0x6f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x71, 0x73, 0x70, 0x69, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x71, 0x73, 0x70, 0x69,
-  0x40, 0x34, 0x30, 0x30, 0x30, 0x41, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x2c,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33, 0x40, 0x00, 0xa0, 0x00,
-  0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x73, 0x64, 0x68, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x20,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0x73, 0x64, 0x68, 0x40,
-  0x34, 0x30, 0x30, 0x30, 0x33, 0x30, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x2c,
-  0x6f, 0x6b, 0x61, 0x79, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x0a, 0x00, 0x00, 0x00, 0x06, 0x62, 0x6c, 0x36, 0x30,
-  0x78, 0x5f, 0x73, 0x64, 0x68, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x00, 0x33, 0x40, 0x00, 0x30, 0x00,
-  0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x00, 0x01, 0x70, 0x69, 0x6e, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x42,
-  0x00, 0x00, 0x00, 0x10, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x01, 0x49, 0x00, 0x00, 0x00, 0x11, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x4d, 0x00, 0x00, 0x00, 0x12,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x52,
-  0x00, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x01, 0x57, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x5c, 0x00, 0x00, 0x00, 0x15,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x77, 0x69, 0x66, 0x69, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x11,
-  0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x20, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01,
-  0x72, 0x65, 0x67, 0x69, 0x6f, 0x6e, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x61, 0x00, 0x00, 0x00, 0x56,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01, 0x6d, 0x61, 0x63, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x6e,
-  0xc8, 0x43, 0x57, 0x82, 0x73, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x06, 0x00, 0x00, 0x01, 0x7b, 0xc8, 0x43, 0x57, 0x82,
-  0x73, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x01,
-  0x61, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0f,
-  0x00, 0x00, 0x01, 0x87, 0x42, 0x4c, 0x36, 0x30, 0x78, 0x5f, 0x43, 0x61,
-  0x6d, 0x65, 0x72, 0x61, 0x30, 0x33, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x0c, 0x00, 0x00, 0x01, 0x8c, 0x31, 0x32, 0x33, 0x34,
-  0x35, 0x36, 0x37, 0x38, 0x39, 0x30, 0x61, 0x00, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0x90, 0x00, 0x00, 0x00, 0x0b,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x08, 0x00, 0x00, 0x01, 0x9b,
-  0x64, 0x69, 0x73, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x01, 0x62, 0x72, 0x64, 0x5f, 0x72, 0x66, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x14, 0x00, 0x00, 0x01, 0xac,
-  0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x29, 0x00, 0x00, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x3f, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x01, 0xb1, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0xba,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0xb0, 0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0xa7, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x9f,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x95, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x8c, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x81,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x77, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x6e, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x65,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x5b, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x52, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x48,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x04,
-  0x00, 0x00, 0x00, 0x3e, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x05, 0x00, 0x00, 0x00, 0x34, 0x00, 0x00, 0x00, 0x01,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x0a,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x3c, 0x00, 0x00, 0x01, 0xbb,
-  0x14, 0xf0, 0x00, 0x00, 0x14, 0xfb, 0x1c, 0x71, 0x15, 0x06, 0x38, 0xe3,
-  0x15, 0x11, 0x55, 0x55, 0x15, 0x1c, 0x71, 0xc7, 0x15, 0x27, 0x8e, 0x38,
-  0x15, 0x32, 0xaa, 0xaa, 0x15, 0x3d, 0xc7, 0x1c, 0x15, 0x48, 0xe3, 0x8e,
-  0x15, 0x54, 0x00, 0x00, 0x15, 0x5f, 0x1c, 0x71, 0x15, 0x6a, 0x38, 0xe3,
-  0x15, 0x75, 0x55, 0x55, 0x15, 0x90, 0x00, 0x00, 0x15, 0xc0, 0x00, 0x00,
-  0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x38, 0x00, 0x00, 0x01, 0xcd,
-  0x00, 0x00, 0xa7, 0x80, 0x00, 0x00, 0xa7, 0xd8, 0x00, 0x00, 0xa8, 0x31,
-  0x00, 0x00, 0xa8, 0x8a, 0x00, 0x00, 0xa8, 0xe3, 0x00, 0x00, 0xa9, 0x3c,
-  0x00, 0x00, 0xa9, 0x95, 0x00, 0x00, 0xa9, 0xee, 0x00, 0x00, 0xaa, 0x47,
-  0x00, 0x00, 0xaa, 0xa0, 0x00, 0x00, 0xaa, 0xf8, 0x00, 0x00, 0xab, 0x51,
-  0x00, 0x00, 0xab, 0xaa, 0x00, 0x00, 0xac, 0x80, 0x00, 0x00, 0x00, 0x03,
-  0x00, 0x00, 0x00, 0x04, 0x00, 0x00, 0x01, 0xdf, 0x00, 0x00, 0x08, 0x00,
-  0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02, 0x00, 0x00, 0x00, 0x02,
-  0x00, 0x00, 0x00, 0x09, 0x6d, 0x6f, 0x64, 0x65, 0x6c, 0x00, 0x63, 0x6f,
-  0x6d, 0x70, 0x61, 0x74, 0x69, 0x62, 0x6c, 0x65, 0x00, 0x23, 0x61, 0x64,
-  0x64, 0x72, 0x65, 0x73, 0x73, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00,
-  0x23, 0x73, 0x69, 0x7a, 0x65, 0x2d, 0x63, 0x65, 0x6c, 0x6c, 0x73, 0x00,
-  0x73, 0x74, 0x61, 0x74, 0x75, 0x73, 0x00, 0x72, 0x65, 0x67, 0x00, 0x6d,
-  0x63, 0x6c, 0x6b, 0x5f, 0x6f, 0x6e, 0x6c, 0x79, 0x00, 0x6d, 0x63, 0x6c,
-  0x6b, 0x00, 0x62, 0x63, 0x6c, 0x6b, 0x00, 0x66, 0x73, 0x00, 0x64, 0x6f,
-  0x00, 0x64, 0x69, 0x00, 0x73, 0x63, 0x6c, 0x00, 0x73, 0x64, 0x61, 0x00,
-  0x6c, 0x69, 0x73, 0x74, 0x5f, 0x61, 0x64, 0x64, 0x72, 0x00, 0x6c, 0x69,
-  0x73, 0x74, 0x5f, 0x64, 0x72, 0x69, 0x76, 0x65, 0x72, 0x00, 0x69, 0x64,
-  0x00, 0x70, 0x61, 0x74, 0x68, 0x00, 0x63, 0x66, 0x67, 0x00, 0x72, 0x74,
-  0x73, 0x00, 0x63, 0x74, 0x73, 0x00, 0x72, 0x78, 0x00, 0x74, 0x78, 0x00,
-  0x62, 0x61, 0x75, 0x64, 0x72, 0x61, 0x74, 0x65, 0x00, 0x70, 0x69, 0x6e,
-  0x00, 0x69, 0x6e, 0x74, 0x65, 0x72, 0x72, 0x75, 0x70, 0x74, 0x00, 0x6b,
-  0x65, 0x79, 0x5f, 0x76, 0x6f, 0x6c, 0x00, 0x6b, 0x65, 0x79, 0x5f, 0x70,
-  0x63, 0x62, 0x00, 0x6b, 0x65, 0x79, 0x5f, 0x65, 0x76, 0x65, 0x6e, 0x74,
-  0x00, 0x6b, 0x65, 0x79, 0x5f, 0x72, 0x61, 0x77, 0x00, 0x50, 0x49, 0x58,
-  0x5f, 0x43, 0x4c, 0x4b, 0x00, 0x46, 0x52, 0x41, 0x4d, 0x45, 0x5f, 0x56,
-  0x4c, 0x44, 0x00, 0x4c, 0x49, 0x4e, 0x45, 0x5f, 0x56, 0x4c, 0x44, 0x00,
-  0x50, 0x49, 0x58, 0x5f, 0x44, 0x41, 0x54, 0x30, 0x00, 0x50, 0x49, 0x58,
-  0x5f, 0x44, 0x41, 0x54, 0x31, 0x00, 0x50, 0x49, 0x58, 0x5f, 0x44, 0x41,
-  0x54, 0x32, 0x00, 0x50, 0x49, 0x58, 0x5f, 0x44, 0x41, 0x54, 0x33, 0x00,
-  0x50, 0x49, 0x58, 0x5f, 0x44, 0x41, 0x54, 0x34, 0x00, 0x50, 0x49, 0x58,
-  0x5f, 0x44, 0x41, 0x54, 0x35, 0x00, 0x50, 0x49, 0x58, 0x5f, 0x44, 0x41,
-  0x54, 0x36, 0x00, 0x50, 0x49, 0x58, 0x5f, 0x44, 0x41, 0x54, 0x37, 0x00,
-  0x43, 0x41, 0x4d, 0x5f, 0x50, 0x57, 0x44, 0x4e, 0x00, 0x43, 0x41, 0x4d,
-  0x5f, 0x52, 0x45, 0x46, 0x5f, 0x43, 0x4c, 0x4b, 0x00, 0x6d, 0x6f, 0x64,
-  0x65, 0x00, 0x73, 0x65, 0x6e, 0x73, 0x6f, 0x72, 0x00, 0x63, 0x6d, 0x64,
-  0x00, 0x64, 0x61, 0x74, 0x30, 0x00, 0x64, 0x61, 0x74, 0x31, 0x00, 0x64,
-  0x61, 0x74, 0x32, 0x00, 0x64, 0x61, 0x74, 0x33, 0x00, 0x63, 0x6f, 0x75,
-  0x6e, 0x74, 0x72, 0x79, 0x5f, 0x63, 0x6f, 0x64, 0x65, 0x00, 0x73, 0x74,
-  0x61, 0x5f, 0x6d, 0x61, 0x63, 0x5f, 0x61, 0x64, 0x64, 0x72, 0x00, 0x61,
-  0x70, 0x5f, 0x6d, 0x61, 0x63, 0x5f, 0x61, 0x64, 0x64, 0x72, 0x00, 0x73,
-  0x73, 0x69, 0x64, 0x00, 0x70, 0x77, 0x64, 0x00, 0x61, 0x70, 0x5f, 0x63,
-  0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x00, 0x61, 0x75, 0x74, 0x6f, 0x5f,
-  0x63, 0x68, 0x61, 0x6e, 0x5f, 0x64, 0x65, 0x74, 0x65, 0x63, 0x74, 0x00,
-  0x78, 0x74, 0x61, 0x6c, 0x00, 0x70, 0x77, 0x72, 0x5f, 0x74, 0x61, 0x62,
-  0x6c, 0x65, 0x00, 0x63, 0x68, 0x61, 0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x64,
-  0x69, 0x76, 0x5f, 0x74, 0x61, 0x62, 0x6c, 0x65, 0x00, 0x63, 0x68, 0x61,
-  0x6e, 0x6e, 0x65, 0x6c, 0x5f, 0x63, 0x6e, 0x74, 0x5f, 0x74, 0x61, 0x62,
-  0x6c, 0x65, 0x00, 0x6c, 0x6f, 0x5f, 0x66, 0x63, 0x61, 0x6c, 0x5f, 0x64,
-  0x69, 0x76, 0x00
-};
-
-int tc_blfdtdump(void)
-{
-    int result;
-
-    result = blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, true, true);
-
-    if (result) {
-        printf("dump failed\r\n");
-    } else {
-        printf("dump successed\r\n");
-    }
-
-    return result;
-
-    // blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, false, true);
-    // blfdtdump(tc_wifi_dtb, TC_WIFI_DTB_LEN, false, false);
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c
deleted file mode 100644
index 2fd04af164..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_blfdt_wifi.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-#include 
-// #include "log/log.h"
-
-#define TC_WIFI_DTB_LEN    (4779 + 4)
-extern const uint8_t tc_wifi_dtb[];
-
-static int tc_fdt_wifi_module(void)
-{
-    const void *fdt = (const void *)tc_wifi_dtb;/* const tc_wifi_dtb */
-
-    int wifi_offset = 0;
-    int offset1 = 0;
-
-    const uint32_t *addr_prop = 0;
-    const char *result = 0;
-    int lentmp = 0;
-    int countindex = 0;
-    int i;
-
-    /* get wifi offset */
-    wifi_offset = fdt_subnode_offset(fdt, 0, "wifi");
-    // wifi
-    if (!(wifi_offset > 0)) {
-        log_error("wifi NULL.\r\n");
-        return -1;
-    }
-
-    // wifi->region->country_code = u32
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "region");
-    if (offset1 > 0) {
-        addr_prop = fdt_getprop(fdt, offset1, "country_code", &lentmp);
-        if (addr_prop) {
-            log_info("value = %ld, lentmp = %d\r\n", fdt32_to_cpu(*addr_prop), lentmp);
-        } else {
-            log_error("country_code NULL.\r\n");
-            return -1;
-        }
-    }
-    // wifi->mac
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "mac");
-    if (offset1 > 0) {
-        // wifi->mac->sta_mac_addr = hex dump
-        addr_prop = fdt_getprop(fdt, offset1, "sta_mac_addr", &lentmp);
-        if (lentmp == 6) {
-            uint8_t sta_mac[6];
-
-            memcpy(sta_mac, addr_prop, 6);
-            log_info("sta_mac :\r\n");
-            log_buf(sta_mac, 6);
-        } else {
-            log_error("sta_mac_addr NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->mac->ap_mac_addr = hex dump
-        addr_prop = fdt_getprop(fdt, offset1, "ap_mac_addr", &lentmp);
-        if (lentmp == 6) {
-            uint8_t ap_mac[6];
-
-            memcpy(ap_mac, addr_prop, 6);
-            log_info("ap_mac :\r\n");
-            log_buf(ap_mac, 6);
-        }
-    }
-
-    // wifi -> ap
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "ap");
-    if (offset1 > 0) {
-        // wifi->ap->ssid = string
-        countindex = fdt_stringlist_count(fdt, offset1, "ssid");
-        if (countindex > 0) {
-            for (i = 0; i < countindex; i++) {
-                result = fdt_stringlist_get(fdt, offset1, "ssid", i, &lentmp);
-                if (lentmp > 0) {/* !NULL */
-                    log_info("ap string[%d] = %s, lentmp = %d\r\n", i, result, lentmp);
-                }
-            }
-        } else {
-            log_error("ap NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->ap->pwd = string
-        countindex = fdt_stringlist_count(fdt, offset1, "pwd");
-        if (countindex > 0) {
-            for (i = 0; i < countindex; i++) {
-                result = fdt_stringlist_get(fdt, offset1, "pwd", i, &lentmp);
-                if (lentmp > 0) {/* !NULL */
-
-                    log_info("pwd string[%d] = %s, lentmp = %d\r\n", i, result, lentmp);
-                }
-            }
-        } else {
-            log_error("pwd NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->ap->ap_channel = u32
-        addr_prop = fdt_getprop(fdt, offset1, "ap_channel", &lentmp);
-        if (addr_prop) {
-            log_info("ap_channel = %ld\r\n", fdt32_to_cpu(*addr_prop));
-        } else {
-            log_error("ap_channel NULL.\r\n");
-            return -1;
-        }
-
-        // wifi->ap->auto_chan_detect = dis ? en
-        countindex = fdt_stringlist_count(fdt, offset1, "auto_chan_detect");
-        if (countindex > 0) {
-            for (i = 0; i < countindex; i++) {
-                result = fdt_stringlist_get(fdt, offset1, "auto_chan_detect", i, &lentmp);
-                if (lentmp > 0) {/* !NULL */
-                    log_info("auto_chan_detect string[%d] = %s, lentmp = %d\r\n", i, result, lentmp);
-                }
-            }
-        } else {
-            log_error("auto_chan_detect NULL.\r\n");
-            return -1;
-        }
-    } else {
-        log_error("ap NULL.\r\n");
-        return -1;
-    }
-
-    // wifi -> brd_rf
-    offset1 = fdt_subnode_offset(fdt, wifi_offset, "brd_rf");
-    if (offset1 > 0) {
-        // wifi->brd_rf->xtal = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "xtal", &lentmp);
-        if (lentmp == 5*4) {
-            uint8_t xtal[5*4];
-
-            memcpy(xtal, addr_prop, 5*4);
-            log_info("xtal :\r\n");
-            log_buf(xtal, 5*4);
-        } else {
-            log_error("xtal NULL.");
-            return -1;
-        }
-        // wifi->brd_rf->pwr_table = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "pwr_table", &lentmp);
-        if (lentmp == 16*4*4) {
-            uint8_t pwr_table[16*4*4];
-
-            memcpy(pwr_table, addr_prop, 16*4*4);
-            log_info("pwr_table :\r\n");
-            log_buf(pwr_table, 16*4*4);
-        } else {
-            log_error("pwr_table NULL. lentmp = %d.\r\n", lentmp);
-            return -1;
-        }
-        // wifi->brd_rf->channel_div_table = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "channel_div_table", &lentmp);
-        if (lentmp == 15*4) {
-            uint8_t channel_div_table[15*4];
-
-            memcpy(channel_div_table, addr_prop, 15*4);
-            log_info("channel_div_table :\r\n");
-            log_buf(channel_div_table, 15*4);
-        }  else {
-            log_error("channel_div_table NULL.\r\n");
-            return -1;
-        }
-        // wifi->brd_rf->channel_cnt_table = u32 []
-        addr_prop = fdt_getprop(fdt, offset1, "channel_cnt_table", &lentmp);
-        if (lentmp == 14*4) {
-            uint8_t channel_cnt_table[14*4];
-
-            memcpy(channel_cnt_table, addr_prop, 14*4);
-            log_info("channel_cnt_table :\r\n");
-            log_buf(channel_cnt_table, 14*4);
-        }  else {
-            log_error("channel_cnt_table NULL.\r\n");
-            return -1;
-        }
-        // wifi->brd_rf->lo_fcal_div = u32
-        addr_prop = fdt_getprop(fdt, offset1, "lo_fcal_div", &lentmp);
-        if (lentmp == 1*4) {
-            uint8_t lo_fcal_div[1*4];
-
-            memcpy(lo_fcal_div, addr_prop, 1*4);
-            log_info("lo_fcal_div :\r\n");
-            log_buf(lo_fcal_div, 1*4);
-        }  else {
-            log_error("lo_fcal_div NULL.\r\n");
-            return -1;
-        }
-    } else {
-        log_error("brd_rf NULL.\r\n");
-        return -1;
-    }
-
-    return 0;
-}
-
-int tc_fdt_wifi(void)
-{
-    int result;
-    result = tc_fdt_wifi_module();
-
-    if (result) {
-        printf("fdt wifi module failed\r\n");
-    } else {
-        printf("fdt wifi module successed\r\n");
-    }
-
-    return result;
-}
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh
deleted file mode 100644
index 9052b8496e..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_dts2dtb.sh
+++ /dev/null
@@ -1,40 +0,0 @@
-#!/bin/sh
-##
-## Copyright (c) 2016-2022 Bouffalolab.
-##
-## This file is part of
-##     *** Bouffalolab Software Dev Kit ***
-##      (see www.bouffalolab.com).
-##
-## Redistribution and use in source and binary forms, with or without modification,
-## are permitted provided that the following conditions are met:
-##   1. Redistributions of source code must retain the above copyright notice,
-##      this list of conditions and the following disclaimer.
-##   2. Redistributions in binary form must reproduce the above copyright notice,
-##      this list of conditions and the following disclaimer in the documentation
-##      and/or other materials provided with the distribution.
-##   3. Neither the name of Bouffalo Lab nor the names of its contributors
-##      may be used to endorse or promote products derived from this software
-##      without specific prior written permission.
-##
-## THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-## AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-## IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-## DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
-## FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
-## DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
-## SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
-## CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
-## OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
-## OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-##
-
-curent_dir=$(pwd)
-cd $curent_dir
-echo $curent_dir
-
-echo "tc_wifi.  dts -> dtb"
-dtc -I dts -O dtb -o tc_wifi.dtb tc_wifi.dts
-
-echo "tc_wifi.  dtb -> c"
-xxd -i tc_wifi.dtb tc_wifi.c
diff --git a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts b/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts
deleted file mode 100644
index e6a4e0dda6..0000000000
--- a/bsp/bl808/m0/libraries/stage/blfdt/test/tc_wifi.dts
+++ /dev/null
@@ -1,310 +0,0 @@
-
-/*
-    echo "tc_wifi.  dts -> dtb"
-    dtc -I dts -O dtb -o tc_wifi.dtb tc_wifi.dts
-
-    echo "tc_wifi.  dtb -> c"
-    xxd -i tc_wifi.dtb tc_wifi.c
-*/
-
-/dts-v1/;
-
-/ {
-    model = "bl bl60x AVB board";
-    compatible = "bl,bl60x-sample", "bl,bl60x-common";
-    #address-cells = <1>;
-    #size-cells = <1>;
-
-    ipc {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        ipc@4001C000 {
-            status = "disable";
-            reg = <0x4001C000 0x100>;
-        };
-    };
-    i2s {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        i2s@40017000 {
-            status = "okay";
-            compatible = "bl60x_i2s";
-            reg = <0x40017000 0x100>;
-            mclk_only = "okay";
-            pin {
-                mclk = <11>;
-            };
-        };
-        i2s@40017100 {
-            status = "okay";
-            compatible = "bl60x_i2s";
-            reg = <0x40017100 0x100>;
-            mclk_only = "disable";
-            pin {
-                bclk = <12>;
-                fs = <29>;
-                do = <30>;
-                di = <31>;
-            };
-        };
-    };
-    i2c {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        i2c@40011000 {
-            status = "okay";
-            compatible = "bl60x_i2c";
-            reg = <0x40011000 0x100>;
-            pin {
-                scl = <32>;
-                sda = <13>;
-            };
-            devices {
-                list_addr = <0x18 0x21>;
-                list_driver = "i2c_es8311", "i2c_gc0308>";
-            };
-        };
-        i2c@40011100 {
-            status = "disable";
-            compatible = "bl60x_i2c";
-            reg = <0x40011100 0x100>;
-            pin {
-                /*empty here*/
-            };
-        };
-    };
-    mjpeg {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        mjpeg@40016000 {
-            status = "okay";
-            compatible = "bl60x_mjpeg";
-            reg = <0x40016000 0x100>;
-        };
-    };
-    timer {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        timer@40014000 {
-            status = "disable";
-            compatible = "bl60x_timer";
-            reg = <0x40014000 0x100>;
-        };
-        timer@40014100 {
-            status = "disable";
-            compatible = "bl60x_timer";
-            reg = <0x40014100 0x100>;
-        };
-    };
-    pwm {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        pwm@40012000 {
-            status = "disable";
-            compatible = "bl60x_pwm";
-            reg = <0x40012000 0x100>;
-            pin {
-                /*empty here*/
-            };
-        };
-    };
-    uart {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        uart@40010000 {
-            status = "disable";
-            id = <0>;
-            compatible = "bl60x_uart";
-            path = "/dev/ttyS0";
-            reg = <0x40010000 0x100>;
-            baudrate = <115200>;
-            pin {
-                /*empty here*/
-            };
-            feature {
-                rts = "disable";
-                cts = "disable";
-                rx = "disable";
-                tx = "disable";
-            };
-        };
-        uart@40010100 {
-            status = "disable";
-            id = <1>;
-            compatible = "bl60x_uart";
-            path = "/dev/ttyS1";
-            reg = <0x40010100 0x100>;
-            baudrate = <115200>;
-            pin {
-                /*empty here*/
-            };
-            feature {
-                rts = "disable";
-                cts = "disable";
-                rx = "disable";
-                tx = "disable";
-            };
-        };
-        uart@40010200 {
-            status = "okay";
-            id = <2>;
-            compatible = "bl60x_uart";
-            path = "/dev/ttyS2";
-            reg = <0x40010200 0x100>;
-            baudrate = <5000000>;
-            pin {
-                tx = <14>;
-                rx = <7>;
-            };
-            feature {
-                tx = "okay";
-                rx = "okay";
-                cts = "disable";
-                rts = "disable";
-            };
-        };
-    };
-    spi {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        spi@4000F000 {
-            status = "disable";
-            reg = <0x4000F000 0x100>;/* 4KB */
-        };
-    };
-    gpip {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        adc_key {
-            status = "okay";
-            pin = <9>;
-            interrupt  = <3>;
-            key_vol = <0 100 400 300 500>;
-            key_pcb = "SW1", "SW2", "SW3", "SW4","SW5";
-            key_event = "Usr1", "Usr2", "Start", "Up", "Down";
-            key_raw = <1 2 3 4 5>;
-        };
-    };
-    pdm {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        pdm@4000C000 {
-            status = "disable";
-            reg = <0x4000C000 0x100>;/* 256B */
-        };
-    };
-    cam {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        cam@4000B000 {
-            status = "okay";
-            compatible = "bl60x_cam";
-            reg = <0x4000B000 0x1000>;/* 4KB */
-            pin {
-                PIX_CLK = <0>;
-                FRAME_VLD = <1>;
-                LINE_VLD = <2>;
-                PIX_DAT0 = <3>;
-                PIX_DAT1 = <4>;
-                PIX_DAT2 = <5>;
-                PIX_DAT3 = <6>;
-                PIX_DAT4 = <25>;
-                PIX_DAT5 = <26>;
-                PIX_DAT6 = <27>;
-                PIX_DAT7 = <28>;
-                CAM_PWDN = <15>;
-                CAM_REF_CLK = <24>;
-            };
-            feature {
-                mode = "HARDWARE";
-            };
-            conf {
-                sensor = "auto";
-            };
-        };
-    };
-    qspi {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        qspi@4000A000 {
-            status = "disable";
-            reg = <0x4000A000 0x1000>;/* 4KB */
-        };
-    };
-    sdh {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        sdh@40003000 {
-            status = "okay";
-            compatible = "bl60x_sdh";
-            reg = <0x40003000 0x1000>;/* 4KB */
-            pin {
-                clk = <16>;
-                cmd = <17>;
-                dat0 = <18>;
-                dat1 = <19>;
-                dat2 = <20>;
-                dat3 = <21>;
-            };
-        };
-    };
-    wifi {
-        #address-cells = <1>;
-        #size-cells = <1>;
-        region {
-            country_code = <86>;
-        };
-        mac {
-            sta_mac_addr = [C8 43 57 82 73 40];
-            ap_mac_addr = [C8 43 57 82 73 02];
-        };
-        ap {
-            ssid = "BL60x_Camera03";
-            pwd = "1234567890a";
-            ap_channel = <11>;
-            auto_chan_detect = "disable";
-        };
-        brd_rf {
-            xtal = <41 41 0 63 63>;
-            pwr_table = <4 3 3 186>,
-                        <4 3 4 176>,
-                        <4 3 5 167>,
-                        <3 3 0 159>,
-                        <3 3 1 149>,
-                        <3 3 2 140>,
-                        <3 3 3 129>,
-                        <3 3 4 119>,
-                        <3 3 5 110>,
-                        <2 3 0 101>,
-                        <2 3 1 91>,
-                        <2 3 2 82>,
-                        <2 3 3 72>,
-                        <2 3 4 62>,
-                        <2 3 5 52>,
-                        <1 3 3 10>;
-            channel_div_table = <0x14F00000
-                                 0x14FB1C71
-                                 0x150638E3
-                                 0x15115555
-                                 0x151C71C7
-                                 0x15278E38
-                                 0x1532AAAA
-                                 0x153DC71C
-                                 0x1548E38E
-                                 0x15540000
-                                 0x155F1C71
-                                 0x156A38E3
-                                 0x15755555
-                                 0x15900000
-                                 0x15C00000>;
-            channel_cnt_table = <0xa780 0xa7d8
-                                 0xa831 0xa88a
-                                 0xa8e3 0xa93c
-                                 0xa995 0xa9ee
-                                 0xaa47 0xaaa0
-                                 0xaaf8 0xab51
-                                 0xabaa 0xac80>;
-            lo_fcal_div = <0x800>;
-        };
-    };
-};
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog.c b/bsp/bl808/m0/libraries/stage/blog/blog.c
deleted file mode 100644
index fdbcf2b404..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog.c
+++ /dev/null
@@ -1,369 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-
-#include "blog_type.h"
-#include "blog_cfg.h"
-
-#include 
-
-#if BLOG_TEST
-#include 
-#endif
-
-/* every line log's buffer */
-static char log_buf[BLOG_LINE_BUF_SIZE] = { 0 };
-
-static int findch_sum(const char *str, char ch)
-{
-    int i = 0;
-    int len = strlen(str);
-    int ret = 0;
-
-    for (i = 0; i < len; i++) {
-        if (str[i] == ch) {
-            ret++;
-        }
-    }
-
-    return ret;
-}
-static int set_level(int argc, char **argv)
-{
-    extern char _ld_bl_static_blogcomponent_code_start;
-    extern char _ld_bl_static_blogcomponent_code_end;
-    extern char _ld_bl_static_blogfile_code_start;
-    extern char _ld_bl_static_blogfile_code_end;
-    extern char _ld_bl_static_blogpri_code_start;
-    extern char _ld_bl_static_blogpri_code_end;
-
-    blog_info_t *start;
-    blog_info_t *end;
-    blog_info_t *info;
-
-    int          left;
-    int          right;
-    uint32_t     mid;
-    int          cmp_val;
-    blog_level_t level;
-
-    int ch_sum;
-
-    if (argc != 3) {
-        __blog_printf("arg error.\r\n");
-        return -1;
-    }
-
-    /* get component level */
-    if (0 == strcmp(argv[1], "all")) {
-        level = BLOG_LEVEL_ALL;
-    } else if (0 == strcmp(argv[1], "debug")) {
-        level = BLOG_LEVEL_DEBUG;
-    } else if (0 == strcmp(argv[1], "info")) {
-        level = BLOG_LEVEL_INFO;
-    } else if (0 == strcmp(argv[1], "warn")) {
-        level = BLOG_LEVEL_WARN;
-    } else if (0 == strcmp(argv[1], "error")) {
-        level = BLOG_LEVEL_ERROR;
-    } else if (0 == strcmp(argv[1], "assert")) {
-        level = BLOG_LEVEL_ASSERT;
-    } else if (0 == strcmp(argv[1], "never")) {
-        level = BLOG_LEVEL_NEVER;
-    } else {
-        __blog_printf("input level = %s not support.\r\n", argv[1]);
-        return -1;
-    }
-
-    /* component_name.file_name.pri_name */
-    ch_sum = findch_sum(argv[2], '.');
-
-    if (0 == ch_sum) {
-        start = (blog_info_t *)(&_ld_bl_static_blogcomponent_code_start);
-        end = (blog_info_t *)(&_ld_bl_static_blogcomponent_code_end);
-    } else if (1 == ch_sum) {
-        start = (blog_info_t *)(&_ld_bl_static_blogfile_code_start);
-        end = (blog_info_t *)(&_ld_bl_static_blogfile_code_end);
-    } else if (2 == ch_sum) {
-        start = (blog_info_t *)(&_ld_bl_static_blogpri_code_start);
-        end = (blog_info_t *)(&_ld_bl_static_blogpri_code_end);
-    } else {
-        __blog_printf("input name = %s not support.\r\n", argv[2]);
-        return -1;
-    }
-
-    left  = 0;
-    right = end - start - 1;
-    while (left <= right) {
-        mid = (left + right) >> 1;
-        cmp_val = strcmp(start[mid].name, argv[2]);
-        if (cmp_val < 0) {
-            left = mid + 1;
-        } else if (cmp_val > 0) {
-            right = mid - 1;
-        } else {
-            info = &start[mid];
-            break;
-        }
-    }
-
-    if (left > right) {
-        __blog_printf("input name = %s not find.\r\n", argv[2]);
-        return -1;
-    }
-
-    /* set level */
-    *(info->level) = level;
-    __blog_printf("set %s = %d\r\n", info->name, *(info->level));
-    return 0;
-}
-
-void cmd_blog_set_level(char *buf, int len, int argc, char **argv)
-{
-    if (0 != set_level(argc, argv)) {
-        __blog_printf("set blog error.\r\n");
-    }
-}
-
-void cmd_blog_info_dump(char *buf, int len, int argc, char **argv)
-{
-    blog_info_t *info_c, *info_f, *info_p;
-    char         name_buf[BLOG_NAMELEN_MAX] = {0};
-
-    extern char _ld_bl_static_blogcomponent_code_start;
-    extern char _ld_bl_static_blogcomponent_code_end;
-    extern char _ld_bl_static_blogfile_code_start;
-    extern char _ld_bl_static_blogfile_code_end;
-    extern char _ld_bl_static_blogpri_code_start;
-    extern char _ld_bl_static_blogpri_code_end;
-
-    __blog_printf("blog code1 = %p - %p\r\n", &_ld_bl_static_blogcomponent_code_start, &_ld_bl_static_blogcomponent_code_end);
-    __blog_printf("blog code2 = %p - %p\r\n", &_ld_bl_static_blogfile_code_start, &_ld_bl_static_blogfile_code_end);
-    __blog_printf("blog code3 = %p - %p\r\n", &_ld_bl_static_blogpri_code_start, &_ld_bl_static_blogpri_code_end);
-
-    for (info_c = (blog_info_t *)&_ld_bl_static_blogcomponent_code_start;
-         (uint32_t)info_c < (uint32_t)&_ld_bl_static_blogcomponent_code_end; info_c++) {
-        if (strlen(info_c->name) > BLOG_NAMELEN_MAX) {
-            __blog_printf("name too long.\r\n");
-            return;
-        }
-        if (name_buf[0] != 0) {
-            if (0 == strcmp(name_buf, info_c->name)) {
-#if BLOG_DUMP_DEDUPLICATE
-              continue;
-#endif
-            } else {
-                memset(name_buf, 0, strlen(name_buf));
-            }
-        }
-
-        __blog_printf("[%-48s] = [%d]\r\n", info_c->name, *(info_c->level));
-
-        if ((name_buf[0] != 0) && (strcmp(info_c->name, name_buf) == 0)) {
-            continue;
-        }
-        strcpy(name_buf, info_c->name);
-
-        for (info_f = (blog_info_t *)&_ld_bl_static_blogfile_code_start;
-            (uint32_t)info_f < (uint32_t)&_ld_bl_static_blogfile_code_end; info_f++) {
-
-            if (strstr(info_f->name, info_c->name) == info_f->name) {
-
-                __blog_printf("[%-48s] = [%d]\r\n", info_f->name, *(info_f->level));
-
-                for (info_p = (blog_info_t *)&_ld_bl_static_blogpri_code_start;
-                    (uint32_t)info_p < (uint32_t)&_ld_bl_static_blogpri_code_end; info_p++) {
-
-                    if (strstr(info_p->name, info_f->name) == info_p->name) {
-                        __blog_printf("[%-48s] = [%d]\r\n", info_p->name, *(info_p->level));
-                    }
-                }
-            }
-        }
-    }
-}
-
-#if BLOG_TEST
-void cmd_blog_test(char *buf, int len, int argc, char **argv)
-{
-    blog_testc_init();
-}
-#endif
-
-static void blog_set_poweron_softlevel(void)
-{
-    blog_info_t *info;
-
-    extern char _ld_bl_static_blogcomponent_code_start;
-    extern char _ld_bl_static_blogcomponent_code_end;
-    extern char _ld_bl_static_blogfile_code_start;
-    extern char _ld_bl_static_blogfile_code_end;
-    extern char _ld_bl_static_blogpri_code_start;
-    extern char _ld_bl_static_blogpri_code_end;
-
-    __blog_printf("\r\nblog init set power on level %d, %d, %d.\r\n", BLOG_POWERON_SOFTLEVEL_COMPONENT,
-            BLOG_POWERON_SOFTLEVEL_FILE, BLOG_POWERON_SOFTLEVEL_PRI);
-    for ( info = (blog_info_t *)&_ld_bl_static_blogcomponent_code_start;
-          (uint32_t)info < (uint32_t)&_ld_bl_static_blogcomponent_code_end; info++ ) {
-        *(info->level) = BLOG_POWERON_SOFTLEVEL_COMPONENT;
-    }
-
-    for ( info = (blog_info_t *)&_ld_bl_static_blogfile_code_start;
-          (uint32_t)info < (uint32_t)&_ld_bl_static_blogfile_code_end; info++ ) {
-        *(info->level) = BLOG_POWERON_SOFTLEVEL_FILE;
-    }
-
-    for ( info = (blog_info_t *)&_ld_bl_static_blogpri_code_start;
-          (uint32_t)info < (uint32_t)&_ld_bl_static_blogpri_code_end; info++ ) {
-        *(info->level) = BLOG_POWERON_SOFTLEVEL_PRI;
-    }
-}
-
-/**
- * output log port interface
- *
- * @param log output of log
- * @param size log size
- */
-void blog_port_output(const char *log, size_t size) {
-    /* output to terminal */
-    __blog_printf("%.*s", size, log);
-    //TODO output to flash
-}
-
-/**
- * another copy string function
- *
- * @param cur_len current copied log length, max size is BLOG_LINE_BUF_SIZE
- * @param dst destination
- * @param src source
- *
- * @return copied length
- */
-size_t blog_strcpy(size_t cur_len, char *dst, const char *src) {
-    const char *src_old = src;
-
-    if ((!dst) || (!src)) {
-        __blog_printf("assert.\r\n");
-        return 0;
-    }
-
-    while (*src != 0) {
-        /* make sure destination has enough space */
-        if (cur_len++ < BLOG_LINE_BUF_SIZE) {
-            *dst++ = *src++;
-        } else {
-            break;
-        }
-    }
-    return src - src_old;
-}
-/**
- * dump the hex format data to log
- *
- * @param name name for hex object, it will show on log header
- * @param width hex number for every line, such as: 16, 32
- * @param buf hex buffer
- * @param size buffer size
- */
-void blog_hexdump_out(const char *name, uint8_t width, const uint8_t *buf, uint16_t size)
-{
-#define __is_print(ch)       ((unsigned int)((ch) - ' ') < 127u - ' ')
-
-    uint16_t i, j;
-    uint16_t log_len = 0;
-    char dump_string[8] = {0};
-    int fmt_result;
-
-    /* lock output */
-
-    for (i = 0; i < size; i += width) {
-        /* package header */
-        fmt_result = snprintf(log_buf, BLOG_LINE_BUF_SIZE, "[%s]: %04X-%04X: ", name, i, i + width - 1);
-        /* calculate log length */
-        if ((fmt_result > -1) && (fmt_result <= BLOG_LINE_BUF_SIZE)) {
-            log_len = fmt_result;
-        } else {
-            log_len = BLOG_LINE_BUF_SIZE;
-        }
-        /* dump hex */
-        for (j = 0; j < width; j++) {
-            if (i + j < size) {
-                snprintf(dump_string, sizeof(dump_string), "%02X ", buf[i + j]);
-            } else {
-                strncpy(dump_string, "   ", sizeof(dump_string));
-            }
-            log_len += blog_strcpy(log_len, log_buf + log_len, dump_string);
-            if ((j + 1) % 8 == 0) {
-                log_len += blog_strcpy(log_len, log_buf + log_len, " ");
-            }
-        }
-        log_len += blog_strcpy(log_len, log_buf + log_len, "  ");
-        /* dump char for hex */
-        for (j = 0; j < width; j++) {
-            if (i + j < size) {
-                snprintf(dump_string, sizeof(dump_string), "%c", __is_print(buf[i + j]) ? buf[i + j] : '.');
-                log_len += blog_strcpy(log_len, log_buf + log_len, dump_string);
-            }
-        }
-        /* overflow check and reserve some space for newline sign */
-        if (log_len + strlen("\r\n") > BLOG_LINE_BUF_SIZE) {
-            log_len = BLOG_LINE_BUF_SIZE - strlen("\r\n");
-        }
-        /* package newline sign */
-        log_len += blog_strcpy(log_len, log_buf + log_len, "\r\n");
-
-        /* do log output */
-        blog_port_output(log_buf, log_len);
-    }
-
-    /* unlock output */
-}
-
-void blog_init(void)
-{
-    blog_set_poweron_softlevel();
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-    { "blogset", "blog pri set level", cmd_blog_set_level},
-    { "blogdump", "blog info dump", cmd_blog_info_dump},
-#if BLOG_TEST
-    { "blogtest", "blog test", cmd_blog_test},
-#endif
-};
-#endif
-
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog.h b/bsp/bl808/m0/libraries/stage/blog/blog.h
deleted file mode 100644
index 242578bdac..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog.h
+++ /dev/null
@@ -1,268 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __BLOG_H__
-#define __BLOG_H__
-
-#include 
-#include 
-#include 
-
-// #include 
-// #include 
-
-#include 
-
-#include "blog_type.h"
-#include "blog_cfg.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-#if (CFG_COMPONENT_BLOG_ENABLE == 1)
-#define ATTR_BLOG_CODE1(name)        __attribute__((used, section(".static_blogcomponent_code." #name)))
-#define ATTR_BLOG_CODE2(name)        __attribute__((used, section(".static_blogfile_code." #name)))
-#define ATTR_BLOG_CODE3(name)        __attribute__((used, section(".static_blogpri_code." #name)))
-
-/* for hard debug level */
-const static uint32_t BLOG_HARD_DECLARE_DISABLE __attribute__((used)) = 0;
-
-/* component level */
-#define _REFC_LEVEL(name)            _fsymc_level_##name
-#define REFC_LEVEL(name)             _REFC_LEVEL(name)
-#define _DEFC_LEVEL(name)            blog_level_t REFC_LEVEL(name) __attribute__((weak))
-#define DECLARE_C_LEVEL(name)        _DEFC_LEVEL(name)
-/* component info */
-#define _REFC_INFO(name)             _fsymc_info_##name
-#define REFC_INFO(name)              _REFC_INFO(name)
-#define _DEFC_INFO(name)             static const blog_info_t REFC_INFO(name) ATTR_BLOG_CODE1(name) = {\
-                                         (blog_level_t *)(&REFC_LEVEL(name)), (char *)(#name)}
-#define DECLARE_C_INFO(name)         _DEFC_INFO(name)
-DECLARE_C_LEVEL(__COMPONENT_NAME_DEQUOTED__);
-DECLARE_C_INFO(__COMPONENT_NAME_DEQUOTED__);
-
-/* file level */
-#define _REFF_LEVEL(name)            _fsymf_level_##name
-#define REFF_LEVEL(name)             _REFF_LEVEL(name)
-#define _DEFF_LEVEL(name)            blog_level_t REFF_LEVEL(name)
-#define DECLARE_F_LEVEL(name)        _DEFF_LEVEL(name)
-/* file info */
-#define _REFF_INFO(name)             _fsymf_info_##name
-#define REFF_INFO(name)              _REFF_INFO(name)
-#define _DEFF_INFO(name, named)      const blog_info_t REFF_INFO(name) ATTR_BLOG_CODE2(name) = {\
-                                        (blog_level_t *)(&REFF_LEVEL(name)), (char *)(#named)}
-#define DECLARE_F_INFO(name, named) _DEFF_INFO(name, named)
-DECLARE_F_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__);
-DECLARE_F_INFO(__COMPONENT_FILE_NAME_DEQUOTED__, __COMPONENT_FILE_NAMED__);
-
-/* pri level */
-#define _REFP_LEVEL(name)            _fsymp_level_##name
-#define REFP_LEVEL(name)             _REFP_LEVEL(name)
-#define _DEFP_LEVEL(name)            blog_level_t REFP_LEVEL(name)
-#define DECLARE_P_LEVEL(name)        _DEFP_LEVEL(name)
-/* pri info */
-#define _REFP_INFO(name)             _fsymp_info_##name
-#define REFP_INFO(name)              _REFP_INFO(name)
-#define _DEFP_INFO(name, prefix)     const blog_info_t REFP_INFO(name) ATTR_BLOG_CODE3(name) = {\
-                                        (blog_level_t *)(&REFP_LEVEL(name)), (char *)(#prefix"."#name)}
-#define DECLARE_P_INFO(name, prefix) _DEFP_INFO(name, prefix)
-
-#define BLOG_DECLARE(name)           DECLARE_P_LEVEL(name);\
-                                     DECLARE_P_INFO(name, __COMPONENT_FILE_NAMED__);
-
-#define custom_cflog(lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\
-       ) {\
-            __blog_printf("[%10u][%s: %s:%4d] " M,\
-            (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-            N, __FILENAME__, __LINE__,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_cflog_raw(lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\
-       ) {\
-            __blog_printf(M,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_plog(priname, lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFP_LEVEL(priname)) \
-       ) {\
-            __blog_printf("[%10u][%s: %s:%4d] " M,\
-            (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-            N, __FILENAME__, __LINE__,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_plog_raw(priname, lowlevel, N, M, ...) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFP_LEVEL(priname)) \
-       ) {\
-            __blog_printf(M,\
-            ##__VA_ARGS__);\
-    }\
-} while(0==1)
-
-#define custom_hexdumplog(name, lowlevel, logo, buf, size) do {\
-    if ( (lowlevel >= REFC_LEVEL(__COMPONENT_NAME_DEQUOTED__)) && \
-         (lowlevel >= REFF_LEVEL(__COMPONENT_FILE_NAME_DEQUOTED__))\
-       ) {\
-            __blog_printf("[%10u][%s: %s:%4d] %s:\r\n",\
-            (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-            logo, __FILENAME__, __LINE__,\
-            name);\
-            blog_hexdump_out(name, 16, buf, size);\
-    }\
-} while(0==1)
-
-#define BLOG_USE_COLOR (0)
-
-#if LOG_USE_COLOR
-#define BLOG_PREFIX_INFO  "\x1b[32mINFO  \x1b[0m"
-#define BLOG_PREFIX_WARN  "\x1b[33mWARN  \x1b[0m"
-#define BLOG_PREFIX_ERROR "\x1b[31mERROR \x1b[0m"
-#define BLOG_PREFIX_USER  "\x1b[35mASSERT\x1b[0m"
-#define BLOG_PREFIX_DUMP  "\x1b[35mDUMP\x1b[0m"
-#else
-#define BLOG_PREFIX_INFO  "INFO"
-#define BLOG_PREFIX_WARN  "WARN"
-#define BLOG_PREFIX_ERROR "ERROR"
-#define BLOG_PREFIX_USER  "ASSERT"
-#define BLOG_PREFIX_DUMP  "DUMP"
-#endif
-
-#define blog_debug(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_DEBUG,"DEBUG ", M, ##__VA_ARGS__);}                 // NULL
-#define blog_info(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_INFO,BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}    // F_GREEN
-#define blog_warn(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_WARN,BLOG_PREFIX_WARN, M, ##__VA_ARGS__);}    // F_YELLOW
-#define blog_error(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog(BLOG_LEVEL_ERROR,BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}  // F_RED
-#define blog_assert(assertion)          if (0 == (assertion)) {\
-                                                __blog_printf("assert, %s:%d\r\n", __FILENAME__, __LINE__);\
-                                                while(1);\
-                                            }
-#define blog_debug_raw(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_DEBUG,"DEBUG ", M, ##__VA_ARGS__);}                 // NULL
-#define blog_info_raw(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_INFO,BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}    // F_GREEN
-#define blog_warn_raw(M, ...)               if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_WARN,BLOG_PREFIX_WARN, M, ##__VA_ARGS__);}    // F_YELLOW
-#define blog_error_raw(M, ...)              if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_cflog_raw(BLOG_LEVEL_ERROR,BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}  // F_RED
-
-#define blog_debug_user(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_DEBUG, "DEBUG ", M, ##__VA_ARGS__);}
-#define blog_info_user(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}
-#define blog_warn_user(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN, M, ##__VA_ARGS__);}
-#define blog_error_user(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}
-#define blog_debug_user_raw(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_DEBUG, "DEBUG ", M, ##__VA_ARGS__);}
-#define blog_info_user_raw(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, M, ##__VA_ARGS__);}
-#define blog_warn_user_raw(name, M, ...)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN,M, ##__VA_ARGS__);}
-#define blog_error_user_raw(name, M, ...)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog_raw(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, M, ##__VA_ARGS__);}
-#define blog_assert_user(name, M, ...)  if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                            custom_plog(name,BLOG_LEVEL_ASSERT, BLOG_PREFIX_USER, M, ##__VA_ARGS__);}
-
-#define blog_debug_hexdump(name, buf, size)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_DEBUG, "DEBUG ", buf, size);}
-#define blog_info_hexdump(name, buf, size)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_INFO, BLOG_PREFIX_INFO, buf, size);}
-#define blog_warn_hexdump(name, buf, size)    if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_WARN, BLOG_PREFIX_WARN, buf, size);}
-#define blog_error_hexdump(name, buf, size)   if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_ERROR, BLOG_PREFIX_ERROR, buf, size);}
-#define blog_assert_hexdump(name, buf, size)  if (0 == BLOG_HARD_DECLARE_DISABLE) {\
-                                              custom_hexdumplog(name,BLOG_LEVEL_ASSERT, BLOG_PREFIX_DUMP, buf, size);}
-#define blog_print          __blog_printf
-#define blog_buf            log_buf//unsupport
-
-#else
-
-//#define BLOG_HARD_DECLARE_DISABLE 1
-#define BLOG_DECLARE(name)
-
-#define blog_debug(M, ...)
-#define blog_info(M, ...)
-#define blog_warn(M, ...)
-#define blog_error(M, ...)
-#define blog_debug_raw(M, ...)
-#define blog_info_raw(M, ...)
-#define blog_warn_raw(M, ...)
-#define blog_error_raw(M, ...)
-#define blog_assert(M, ...)
-
-#define blog_debug_user(name, M, ...)
-#define blog_info_user(name, M, ...)
-#define blog_warn_user(name, M, ...)
-#define blog_error_user(name, M, ...)
-#define blog_debug_user_raw(name, M, ...)
-#define blog_info_user_raw(name, M, ...)
-#define blog_warn_user_raw(name, M, ...)
-#define blog_error_user_raw(name, M, ...)
-#define blog_assert_user(name, M, ...)
-
-#define blog_debug_hexdump(name, buf, size)
-#define blog_info_hexdump(name, buf, size)
-#define blog_warn_hexdump(name, buf, size)
-#define blog_error_hexdump(name, buf, size)
-#define blog_assert_hexdump(name, buf, size)
-
-#define blog_print(...)
-#define blog_buf(...)
-
-#endif
-
-void blog_init(void);
-
-void blog_hexdump_out(const char *name, uint8_t width, uint8_t *buf, uint16_t size);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h b/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h
deleted file mode 100644
index 41ad4f0dc5..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog_cfg.h
+++ /dev/null
@@ -1,44 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __BLOG_CFG_H__
-#define __BLOG_CFG_H__
-
-#define BLOG_POWERON_SOFTLEVEL_COMPONENT    (BLOG_LEVEL_INFO)
-#define BLOG_POWERON_SOFTLEVEL_FILE         (BLOG_LEVEL_INFO)
-#define BLOG_POWERON_SOFTLEVEL_PRI          (BLOG_LEVEL_INFO)
-#define BLOG_NAMELEN_MAX                    (128)
-#define BLOG_DUMP_DEDUPLICATE               (1)
-#define BLOG_TEST                           (0)
-
-#define BLOG_LINE_BUF_SIZE                  (256)
-
-#define __blog_printf                       bl_printk
-
-#endif
diff --git a/bsp/bl808/m0/libraries/stage/blog/blog_type.h b/bsp/bl808/m0/libraries/stage/blog/blog_type.h
deleted file mode 100644
index 538ad60ff6..0000000000
--- a/bsp/bl808/m0/libraries/stage/blog/blog_type.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __BLOG_TYPE_H__
-#define __BLOG_TYPE_H__
-
-typedef enum _blog_leve {
-    BLOG_LEVEL_ALL = 0,
-    BLOG_LEVEL_DEBUG,
-    BLOG_LEVEL_INFO,
-    BLOG_LEVEL_WARN,
-    BLOG_LEVEL_ERROR,
-    BLOG_LEVEL_ASSERT,
-    BLOG_LEVEL_NEVER,
-} blog_level_t;
-
-typedef struct _blog_info {
-    blog_level_t *level; //default 0
-    char *name;
-} blog_info_t;
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_base64.h b/bsp/bl808/m0/libraries/utils/include/utils_base64.h
deleted file mode 100644
index 7c7db40874..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_base64.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_BASE64_H_
-#define _IOTX_COMMON_BASE64_H_
-
-#include 
-
-#define UTILS_BASE64_TEST
-
-typedef enum iotx_err
-{
-    FAIL_RETURN = 0,
-    SUCCESS_RETURN
-}iotx_err_t;
-
-iotx_err_t utils_base64encode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *encodedData, uint32_t *outputLength);
-iotx_err_t utils_base64decode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *decodedData, uint32_t *outputLength);
-
-void utils_base64_encode_stream(int (*read_data)(uint8_t *data, void *opaque), void (*write_data)(const uint8_t data[4], void *opaque), void *opaque);
-int base64_cli_init(void);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h b/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h
deleted file mode 100644
index 20a24439fd..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_bitmap_window.h
+++ /dev/null
@@ -1,45 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-struct utils_bitmap_ctx {
-    int ssn;
-    int ssn_duration;
-    union {
-        uint8_t bytes[8];
-        uint64_t map64;
-    } bitmap;
-};
-
-int utils_bitmap_window_init(struct utils_bitmap_ctx *ctx, int ssn, int ssn_max);
-int utils_bitmap_window_bit_set(struct utils_bitmap_ctx *ctx, int bit_pos);
-uint64_t utils_bitmap_window_map_get(struct utils_bitmap_ctx *ctx);
-int utils_bitmap_window_ssn_get(struct utils_bitmap_ctx *ctx);
-int utils_bitmap_window_cli_init(void);
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_crc.h b/bsp/bl808/m0/libraries/utils/include/utils_crc.h
deleted file mode 100644
index 10f62d4c17..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_crc.h
+++ /dev/null
@@ -1,47 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_CRC_H__
-#define __UTILS_CRC_H__
-#include 
-
-uint16_t utils_crc16(void *dataIn, uint32_t len);
-uint32_t utils_crc32(void *dataIn, uint32_t len);
-uint16_t utils_crc16_ccitt(void *dataIn, uint32_t len);
-
-struct crc32_stream_ctx {
-  uint32_t crc;
-};
-
-void utils_crc32_stream_init(struct crc32_stream_ctx *ctx);
-void utils_crc32_stream_feed(struct crc32_stream_ctx *ctx, uint8_t data);
-void utils_crc32_stream_feed_block(struct crc32_stream_ctx *ctx, uint8_t *data, uint32_t len);
-uint32_t utils_crc32_stream_results(struct crc32_stream_ctx *ctx);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_debug.h b/bsp/bl808/m0/libraries/utils/include/utils_debug.h
deleted file mode 100644
index 8f5dcecc75..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_debug.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_DEBUG_H__
-#define __UTILS_DEBUG_H__
-#include 
-#define BL_ASSERT_ERROR(cond) do {\
-    if (!(cond)) { \
-        printf("[ASSERT] [ERR] %s:%d\r\n", __FILENAME__, __LINE__); \
-        while (1) { \
-        } \
-    } \
-} while (0)
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_dns.h b/bsp/bl808/m0/libraries/utils/include/utils_dns.h
deleted file mode 100644
index 19eeb2bc02..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_dns.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_DNS_H__
-#define __UTILS_DNS_H__
-#include 
-int utils_dns_domain_get(uint8_t *records, uint8_t *buf, int *len);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_fec.h b/bsp/bl808/m0/libraries/utils/include/utils_fec.h
deleted file mode 100644
index 114b332368..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_fec.h
+++ /dev/null
@@ -1,61 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTILS_FEC_H__
-#define __UTILS_FEC_H__
-
-#include 
-#include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define FEC_MSG_LENGTH  128
-#define FEC_ECC_LENGTH  126
-
-#define bl_assert(expr)
-
-typedef struct
-{
-    int dummy[1120];
-} fec_t;
-
-int  reedsolomon_getmemsize(void);
-void reedsolomon_init(void *context);
-void reedsolomon_encode(void *context, void* src, void* dst);
-char reedsolomon_decode(void *context, void* src, void* dst);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_getopt.h b/bsp/bl808/m0/libraries/utils/include/utils_getopt.h
deleted file mode 100644
index 026640e0a3..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_getopt.h
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __GETOPT_H__
-#define __GETOPT_H__
-/**
- * @brief Parameters needed to parse the command line
- *
- */
-typedef struct getopt_env {
-    char *optarg;    /*!< if the option accepts parameters, then optarg point to the option parameter*/
-    int optind;      /*!< current index of argv*/
-    int opterr;      /*!< non-zero enable error message output, while 0,no error message output*/
-    int optopt;      /*!< contain unrecognized option character*/
-    int __optpos;
-} getopt_env_t;
-
-/**
- * @brief Initialize struct getopt_env
- *
- * @param env pointer to struct getopt_env
- * @param opterr set error message output method
- *
- * @return
- *     -  0: success
- *     - -1: fail
- */
-int utils_getopt_init(getopt_env_t *env, int opterr);
-
-/**
- * @brief Parses the command-line arguments
- *
- * @param env pointer to struct getopt_env
- * @param argc the argument count
- * @param argv the argument array
- *
- * @return
- *     -  option character : an option was successfully found
- *     - -1 : all command-line options have been parsed
- *     - '?' : option character was not in optstring
- *     - ':' or '?' : If utils_getopt() encounters an option with a missing argument, then the return value depends on the first character in optstring: if it is ':', then ':' is returned; otherwise '?' is returned
- *
- * @note Example
- * @code
- *
- * #include 
- * #include 
- *
- * void cmd(char *buf, int len, int argc, char **argv)
- * {
- *     int opt;
-       getopt_env_t getopt_env;
-       utils_getopt_init(&getopt_env, 0);
- *     //put ':' in the starting of the string so that program can distinguish between '?' and ':'
- *     while ((opt = utils_getopt(&getopt_env, argc, argv, ":if:lr")) != -1) {
- *         switch(opt)
- *         {
- *             case 'i':
- *             case 'l':
- *             case 'r':
- *                 printf("option: %c\r\n", opt);
- *                 break;
- *             case 'f':
- *                 printf("filename: %s\r\n", getopt_env.optarg);
- *                 break;
- *             case ':':
-                   printf("%s: %c requires an argument\r\n", *argv, getopt_env.optopt);
- *                 break;
- *             case '?':
- *                 printf("unknow option: %c\r\n", getopt_env.optopt);
- *                 break;
- *          }
- *      }
- *      //optind is for the extra arguments which are not parsed
- *      for(; getopt_env.optind < argc; getopt_env.optind++){
- *          printf("extra arguments: %s\r\n", argv[getopt_env.optind]);
- *      }
- *
- *  }
- *  @endcode
- */
-int utils_getopt(getopt_env_t *env, int argc, char * const argv[], const char *optstring);
-
-#endif /* __GETOPT_H__ */
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hex.h b/bsp/bl808/m0/libraries/utils/include/utils_hex.h
deleted file mode 100644
index 6361fdad07..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hex.h
+++ /dev/null
@@ -1,34 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_HEX_H__
-#define __UTILS_HEX_H__
-char *utils_bin2hex(char *dst, const void *src, size_t count);
-size_t utils_hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h b/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h
deleted file mode 100644
index 4cbde0c711..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hexdump.h
+++ /dev/null
@@ -1,33 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_HEXDUMP_H__
-#define __UTILS_HEXDUMP_H__
-void utils_hexdump(void *mem, unsigned int len);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hmac.h b/bsp/bl808/m0/libraries/utils/include/utils_hmac.h
deleted file mode 100644
index 7949a190c6..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hmac.h
+++ /dev/null
@@ -1,59 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_HMAC_H_
-#define _IOTX_COMMON_HMAC_H_
-
-#include 
-
-#define KEY_IOPAD_SIZE        (64)
-#define MD5_DIGEST_SIZE       (16)
-#define SHA1_DIGEST_SIZE      (20)
-#define SHA256_DIGEST_SIZE    (32)
-
-#ifdef UTILS_MD5
-void utils_hmac_md5(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-#endif
-
-#ifdef UTILS_SHA1
-void utils_hmac_sha1(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-
-void utils_hmac_sha1_hex(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-#endif
-
-#ifdef UTILS_SHA256
-void utils_hmac_sha256(const char *msg, int msg_len, char *digest, const char *key, int key_len);
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h b/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h
deleted file mode 100644
index e6f9de7a77..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_hmac_sha1_fast.h
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_HMAC_SHA1_FASH_H__
-#define __UTILS_HMAC_SHA1_FASH_H__
-
-void utils_hmac_sha1_fast(unsigned char ** ppText,
-                    int * pTextLen,
-                    int textNum,
-                    unsigned char *key,
-                    int key_len,
-                    unsigned char *output,
-                    int outputLen);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_list.h b/bsp/bl808/m0/libraries/utils/include/utils_list.h
deleted file mode 100644
index 6248b1b1c2..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_list.h
+++ /dev/null
@@ -1,621 +0,0 @@
-
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#ifndef _UTILS_LIST_H_
-#define _UTILS_LIST_H_
-
-#include 
-
-struct utils_list_hdr
-{
-    struct utils_list_hdr *next;
-};
-
-struct utils_list
-{
-    /// pointer to first element of the list
-    struct utils_list_hdr *first;
-    /// pointer to the last element
-    struct utils_list_hdr *last;
-};
-
-
-/*
- * FUNCTION DECLARATIONS
- ****************************************************************************************
- */
-/**
- ****************************************************************************************
- * @brief Initialize a list to defaults values.
- * @param[in] list           Pointer to the list structure.
- ****************************************************************************************
- */
-void utils_list_init(struct utils_list *list);
-
-/**
- ****************************************************************************************
- * @brief Initialize a pool to default values, and initialize the relative free list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] pool           Pointer to the pool to be initialized
- * @param[in] elmt_size      Size of one element of the pool
- * @param[in] elmt_cnt       Nb of elements available in the pool
- * @param[in] default_value  Pointer to the default value of each element (may be NULL)
- ****************************************************************************************
- */
-void utils_list_pool_init(struct utils_list *list, void *pool, size_t elmt_size, unsigned int elmt_cnt, void *default_value);
-
-/**
- ****************************************************************************************
- * @brief Add an element as last on the list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the header to add at the end of the list
- ****************************************************************************************
- */
-void utils_list_push_back(struct utils_list *list,
-                       struct utils_list_hdr *list_hdr);
-
-/**
- ****************************************************************************************
- * @brief Add an element as first on the list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the header to add at the beginning of the list
- ****************************************************************************************
- */
-void utils_list_push_front(struct utils_list *list, struct utils_list_hdr *list_hdr);
-/**
- ****************************************************************************************
- * @brief Extract the first element of the list.
- *
- * @param[in] list           Pointer to the list structure
- *
- * @return The pointer to the element extracted, and NULL if the list is empty.
- ****************************************************************************************
- */
-struct utils_list_hdr *utils_list_pop_front(struct utils_list *list);
-
-/**
- ****************************************************************************************
- * @brief Search for a given element in the list, and extract it if found.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the searched element
- *
- * @return CO_EMPTY if the list is empty, CO_FAIL if the element not found in the list,
- * CO_OK else.
- ****************************************************************************************
- */
-void utils_list_extract(struct utils_list *list, struct utils_list_hdr *list_hdr);
-
-/**
- ****************************************************************************************
- * @brief Searched a given element in the list.
- *
- * @param[in] list           Pointer to the list structure
- * @param[in] list_hdr       Pointer to the searched element
- *
- * @return true if the element is found in the list, false otherwise
- ****************************************************************************************
- */
-int utils_list_find(struct utils_list *list, struct utils_list_hdr *list_hdr);
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list     Pointer to the list.
- * @param[in]  element  Pointer to the element to insert.
- * @param[in]  cmp      Comparison function (return true if first element has to be inserted
- *                      before the second one).
- *
- * @return              Pointer to the element found and removed (NULL otherwise).
- ****************************************************************************************
- */
-void utils_list_insert(struct utils_list * const list, struct utils_list_hdr * const element,
-        int (*cmp)(struct utils_list_hdr const *elementA,
-        struct utils_list_hdr const *elementB));
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list after the provided element.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list           Pointer to the list.
- * @param[in]  prev_element   Pointer to the element to find in the list
- * @param[in]  element        Pointer to the element to insert.
- *
- * If prev_element is not found, the provided element is not inserted
- ****************************************************************************************
- */
-void utils_list_insert_after(struct utils_list * const list, struct utils_list_hdr * const prev_element, struct utils_list_hdr * const element);
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list before the provided element.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list           Pointer to the list.
- * @param[in]  next_element   Pointer to the element to find in the list
- * @param[in]  element        Pointer to the element to insert.
- *
- * If next_element is not found, the provided element is not inserted
- ****************************************************************************************
- */
-void utils_list_insert_before(struct utils_list * const list, struct utils_list_hdr * const next_element, struct utils_list_hdr * const element);
-
-/**
- ****************************************************************************************
- * @brief Concatenate two lists.
- * The resulting list is the list passed as the first parameter. The second list is
- * emptied.
- *
- * @param[in]  list1          First list (will get the result of the concatenation)
- * @param[in]  list2          Second list (will be emptied after the concatenation)
- ****************************************************************************************
- */
-void utils_list_concat(struct utils_list *list1, struct utils_list *list2);
-
-/**
- ****************************************************************************************
- * @brief Remove the element in the list after the provided element.
- *
- * This primitive removes an element in the list. It is assume that element is part of
- * the list.
- *
- * @param[in] list          Pointer to the list.
- * @param[in] prev_element  Pointer to the previous element.
- *                          NULL if @p element is the first element in the list
- * @param[in] element       Pointer to the element to remove.
- *
- ****************************************************************************************
- */
-void utils_list_remove(struct utils_list *list, struct utils_list_hdr *prev_element, struct utils_list_hdr *element);
-/**
- ****************************************************************************************
- * @brief Test if the list is empty.
- *
- * @param[in] list           Pointer to the list structure.
- *
- * @return true if the list is empty, false else otherwise.
- ****************************************************************************************
- */
-static inline int utils_list_is_empty(const struct utils_list *const list)
-{
-    return (NULL == list->first);
-}
-
-/**
- ****************************************************************************************
- * @brief Return the number of element of the list.
- *
- * @param[in] list           Pointer to the list structure.
- *
- * @return The number of elements in the list.
- ****************************************************************************************
- */
-unsigned int utils_list_cnt(const struct utils_list *const list);
-
-/**
- ****************************************************************************************
- * @brief Pick the first element from the list without removing it.
- *
- * @param[in] list           Pointer to the list structure.
- *
- * @return First element address. Returns NULL pointer if the list is empty.
- ****************************************************************************************
- */
-static inline struct utils_list_hdr *utils_list_pick(const struct utils_list *const list)
-{
-    return list->first;
-}
-
-static inline struct utils_list_hdr *utils_list_pick_last(const struct utils_list *const list)
-{
-    return list->last;
-}
-
-static inline struct utils_list_hdr *utils_list_next(const struct utils_list_hdr *const list_hdr)
-{
-    return list_hdr->next;
-}
-
-
-/*
- * Get offset of a member variable.
- *
- * @param[in]   type     the type of the struct this is embedded in.
- * @param[in]   member   the name of the variable within the struct.
- */
-#define utils_offsetof(type, member)   ((size_t)&(((type *)0)->member))
-
-/*
- * Get the struct for this entry.
- *
- * @param[in]   ptr     the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the variable within the struct.
- */
-#define utils_container_of(ptr, type, member) \
-    ((type *) ((char *) (ptr) - utils_offsetof(type, member)))
-
-/* for double link list */
-typedef struct utils_dlist_s {
-    struct utils_dlist_s *prev;
-    struct utils_dlist_s *next;
-} utils_dlist_t;
-
-static inline void __utils_dlist_add(utils_dlist_t *node, utils_dlist_t *prev, utils_dlist_t *next)
-{
-    node->next = next;
-    node->prev = prev;
-
-    prev->next = node;
-    next->prev = node;
-}
-
-/*
- * Get the struct for this entry.
- *
- * @param[in]   addr    the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_entry(addr, type, member) \
-    ((type *)((long)addr - utils_offsetof(type, member)))
-
-
-static inline void utils_dlist_add(utils_dlist_t *node, utils_dlist_t *queue)
-{
-    __utils_dlist_add(node, queue, queue->next);
-}
-
-static inline void utils_dlist_add_tail(utils_dlist_t *node, utils_dlist_t *queue)
-{
-    __utils_dlist_add(node, queue->prev, queue);
-}
-
-static inline void utils_dlist_del(utils_dlist_t *node)
-{
-    utils_dlist_t *prev = node->prev;
-    utils_dlist_t *next = node->next;
-
-    prev->next = next;
-    next->prev = prev;
-}
-
-static inline void utils_dlist_init(utils_dlist_t *node)
-{
-    node->next = node->prev = node;
-}
-
-static inline void INIT_UTILS_DLIST_HEAD(utils_dlist_t *list)
-{
-    list->next = list;
-    list->prev = list;
-}
-
-static inline int utils_dlist_empty(const utils_dlist_t *head)
-{
-    return head->next == head;
-}
-
-/*
- * Initialise the list.
- *
- * @param[in]   list    the list to be inited.
- */
-#define UTILS_DLIST_INIT(list)  {&(list), &(list)}
-
-/*
- * Get the first element from a list
- *
- * @param[in]   ptr     the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_first_entry(ptr, type, member) \
-    utils_dlist_entry((ptr)->next, type, member)
-
-/*
- * Iterate over a list.
- *
- * @param[in]   pos     the &struct utils_dlist_t to use as a loop cursor.
- * @param[in]   head    he head for your list.
- */
-#define utils_dlist_for_each(pos, head) \
-    for (pos = (head)->next; pos != (head); pos = pos->next)
-
-/*
- * Iterate over a list safe against removal of list entry.
- *
- * @param[in]   pos     the &struct utils_dlist_t to use as a loop cursor.
- * @param[in]   n       another &struct utils_dlist_t to use as temporary storage.
- * @param[in]   head    he head for your list.
- */
-#define utils_dlist_for_each_safe(pos, n, head) \
-    for (pos = (head)->next, n = pos->next; pos != (head); \
-    pos = n, n = pos->next)
-
-/*
- * Iterate over list of given type.
- *
- * @param[in]   queue   he head for your list.
- * @param[in]   node    the &struct utils_dlist_t to use as a loop cursor.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_for_each_entry(queue, node, type, member) \
-    for (node = utils_container_of((queue)->next, type, member); \
-         &node->member != (queue); \
-         node = utils_container_of(node->member.next, type, member))
-
-/*
- * Iterate over list of given type safe against removal of list entry.
- *
- * @param[in]   queue   the head for your list.
- * @param[in]   n       the type * to use as a temp.
- * @param[in]   node    the type * to use as a loop cursor.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- */
-#define utils_dlist_for_each_entry_safe(queue, n, node, type, member) \
-    for (node = utils_container_of((queue)->next, type, member),  \
-         n = (queue)->next ? (queue)->next->next : NULL;        \
-         &node->member != (queue);                              \
-         node = utils_container_of(n, type, member), n = n ? n->next : NULL)
-
-/*
- * Get the struct for this entry.
- * @param[in]   ptr     the list head to take the element from.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the variable within the struct.
- */
-#define utils_list_entry(ptr, type, member) \
-        utils_container_of(ptr, type, member)
-
-
-/*
- * Iterate backwards over list of given type.
- *
- * @param[in]   pos     the type * to use as a loop cursor.
- * @param[in]   head    he head for your list.
- * @param[in]   member  the name of the utils_dlist_t within the struct.
- * @param[in]   type    the type of the struct this is embedded in.
- */
-#define utils_dlist_for_each_entry_reverse(pos, head, member, type) \
-    for (pos = utils_list_entry((head)->prev, type, member);        \
-         &pos->member != (head);                              \
-         pos = utils_list_entry(pos->member.prev, type, member))
-
-
-/*
- * Get the list length.
- *
- * @param[in]  queue  the head for your list.
- */
-static inline int utils_dlist_entry_number(utils_dlist_t *queue)
-{
-    int num;
-    utils_dlist_t *cur = queue;
-    for (num=0;cur->next != queue;cur=cur->next, num++)
-        ;
-
-    return num;
-}
-
-
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_DLIST_HEAD_INIT(name) { &(name), &(name) }
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_DLIST_HEAD(name) \
-        utils_dlist_t name = UTILS_DLIST_HEAD_INIT(name)
-
-/* for single link list */
-typedef struct utils_slist_s {
-    struct utils_slist_s *next;
-} utils_slist_t;
-
-static inline void utils_slist_add(utils_slist_t *node, utils_slist_t *head)
-{
-    node->next = head->next;
-    head->next = node;
-}
-
-static inline void utils_slist_add_tail(utils_slist_t *node, utils_slist_t *head)
-{
-    while (head->next) {
-        head = head->next;
-    }
-
-    utils_slist_add(node, head);
-}
-
-static inline void utils_slist_append(utils_slist_t *l, utils_slist_t *n)
-{
-    utils_slist_t *node;
-
-    node = l;
-    while (node->next) node = node->next;
-
-    /* append the node to the tail */
-    node->next = n;
-    n->next = NULL;
-}
-
-static inline void utils_slist_del(utils_slist_t *node, utils_slist_t *head)
-{
-    while (head->next) {
-        if (head->next == node) {
-            head->next = node->next;
-            break;
-        }
-
-        head = head->next;
-    }
-}
-
-static inline int utils_slist_empty(const utils_slist_t *head)
-{
-    return !head->next;
-}
-
-static inline void utils_slist_init(utils_slist_t *head)
-{
-    head->next = 0;
-}
-
-static inline utils_slist_t* utils_slist_first(utils_slist_t *l)
-{
-    return l->next;
-}
-
-static inline utils_slist_t* utils_slist_tail(utils_slist_t *l)
-{
-    while (l->next) l = l->next;
-
-    return l;
-}
-
-static inline utils_slist_t* utils_slist_next(utils_slist_t *l)
-{
-    return l->next;
-}
-
-/*
-* Iterate over list of given type.
-*
-* @param[in]   queue   he head for your list.
-* @param[in]   node    the type * to use as a loop cursor.
-* @param[in]   type    the type of the struct this is embedded in.
-* @param[in]   member  the name of the utils_slist_t within the struct.
-*/
-#define utils_slist_for_each_entry(queue, node, type, member)        \
-    for (node = utils_container_of((queue)->next, type, member); \
-         &node->member;                                        \
-         node = utils_container_of(node->member.next, type, member))
-
-/*
- * Iterate over list of given type safe against removal of list entry.
- *
- * @param[in]   queue   the head for your list.
- * @param[in]   tmp     the type * to use as a temp.
- * @param[in]   node    the type * to use as a loop cursor.
- * @param[in]   type    the type of the struct this is embedded in.
- * @param[in]   member  the name of the utils_slist_t within the struct.
- */
-#define utils_slist_for_each_entry_safe(queue, tmp, node, type, member) \
-    for (node = utils_container_of((queue)->next, type, member),    \
-         tmp = (queue)->next ? (queue)->next->next : NULL;        \
-         &node->member;                                           \
-         node = utils_container_of(tmp, type, member), tmp = tmp ? tmp->next : tmp)
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_SLIST_HEAD_INIT(name) {0}
-
-/*
- * Initialise the list.
- *
- * @param[in]   name    the list to be initialized.
- */
-#define UTILS_SLIST_HEAD(name) \
-        utils_slist_t name = UTILS_SLIST_HEAD_INIT(name)
-
-/*
- * Get the struct for this entry.
- * @param[in]   addr     the list head to take the element from.
- * @param[in]   type     the type of the struct this is embedded in.
- * @param[in]   member   the name of the utils_slist_t within the struct.
- */
-#define utils_slist_entry(addr, type, member) (                                   \
-    addr ? (type *)((long)addr - utils_offsetof(type, member)) : (type *)addr \
-)
-
-/*
-* Get the first element from a list.
-*
-* @param[in]   ptr     the list head to take the element from.
-* @param[in]   type    the type of the struct this is embedded in.
-* @param[in]   member  the name of the utils_slist_t within the struct.
-*/
-#define utils_slist_first_entry(ptr, type, member) \
-    utils_slist_entry(utils_slist_next(ptr), type, member)
-
-
-/*
-* Get the last element from a list.
-*
-* @param[in]   ptr     the list head to take the element from.
-* @param[in]   type    the type of the struct this is embedded in.
-* @param[in]   member  the name of the utils_slist_t within the struct.
-*/
-#define utils_slist_tail_entry(ptr, type, member) \
-    utils_slist_entry(utils_slist_tail(ptr), type, member)
-
-
-/*
- * Get the list length.
- *
- * @param[in]   queue    the head for your list.
- */
-static inline int utils_slist_entry_number(utils_slist_t *queue)
-{
-    int num;
-    utils_slist_t *cur = queue;
-    for (num=0;cur->next;cur=cur->next, num++)
-        ;
-
-    return num;
-}
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_log.h b/bsp/bl808/m0/libraries/utils/include/utils_log.h
deleted file mode 100644
index bbf73a7c49..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_log.h
+++ /dev/null
@@ -1,168 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTILS_LOG_H__
-#define __UTILS_LOG_H__
-
-#include 
-#include 
-#include 
-#include 
-
-// #include 
-// #include 
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define __utils_printf              bl_printk
-
-/* cc */
-/* define compiler specific symbols */
-#if defined (__ICCARM__)
-#define BL_PACK_STRUCT_BEGIN
-#define BL_PACK_STRUCT_STRUCT
-#define BL_PACK_STRUCT_END
-#define BL_PACK_STRUCT_FIELD(x) x
-#define BL_PACK_STRUCT_USE_INCLUDES
-#elif defined (__CC_ARM)
-#define BL_PACK_STRUCT_BEGIN __packed
-#define BL_PACK_STRUCT_STRUCT
-#define BL_PACK_STRUCT_END
-#define BL_PACK_STRUCT_FIELD(x) x
-#elif defined (__GNUC__)
-#define BL_PACK_STRUCT_BEGIN    //#pragma pack(push, 1)
-#define BL_PACK_STRUCT_STRUCT //__attribute__ ((__packed__))
-#define BL_PACK_STRUCT_END      //#pragma pack(pop)
-#define BL_PACK_STRUCT_FIELD(x)
-#elif defined (__TASKING__)
-#define BL_PACK_STRUCT_BEGIN
-#define BL_PACK_STRUCT_STRUCT
-#define BL_PACK_STRUCT_END
-#define BL_PACK_STRUCT_FIELD(x) x
-#endif
-
-#if 0
-#define BL_ASSERT(condition)    \
-    do { \
-        if (!(condition)) { \
-            log_assert("ASSERT: %s:%d\r\n", __FILENAME__, __LINE__); \
-            while (1) { \
-                /*deap loop now*/ \
-            } \
-        } \
-    } while (0)
-#endif
-#define BL_ASSERT(condition)
-
-#define LOG_USE_COLOR  (0)
-typedef enum LOG_BUF_OUT_DATA_TYPE {
-    LOG_BUF_OUT_DATA_TYPE_HEX,
-    LOG_BUF_OUT_DATA_TYPE_INT8,
-    LOG_BUF_OUT_DATA_TYPE_UNT8,
-} LOG_BUF_OUT_DATA_TYPE_T;
-//#define LOG_USE_LINE_FEED
-#define LOG_LOCK_LOCK    /* reserved, must diffrent with buf lock */
-#define LOG_LOCK_UNLOCK  /* reserved, must diffrent with buf lock */
-//#define SHORT_FILE __FILENAME__
-#define SHORT_FILE __FILE__
-
-#ifdef LOG_USE_LINE_FEED
-#define custom_log(N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M "\r\n",\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, SHORT_FILE, __LINE__,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#define custom_buf_pri(file, line, N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M, "\r\n",\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, file, line,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#else
-#define custom_log(N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M,\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, SHORT_FILE, __LINE__,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#define custom_buf_pri(file, line, N, M, ...) do {  LOG_LOCK_LOCK;\
-                                    __utils_printf("[%10u][%s: %s:%4d] " M,\
-                                    (xPortIsInsideInterrupt())?(xTaskGetTickCountFromISR()):(xTaskGetTickCount()),\
-                                    N, file, line,\
-                                    ##__VA_ARGS__);\
-                                    LOG_LOCK_UNLOCK;\
-                                    } while(0==1)
-#endif
-
-#if LOG_USE_COLOR
-#define log_buf_pri(file, line, M, ...)   custom_buf_pri(file, line, "\x1b[36mBUF\x1b[0m", M, ##__VA_ARGS__)
-#else
-#define log_buf_pri(file, line, M, ...)   custom_buf_pri(file, line, "BUF", M, ##__VA_ARGS__)
-#endif
-
-#if LOG_USE_COLOR
-#define log_trace(M, ...)   custom_log("\x1b[94mTRACE \x1b[0m", M, ##__VA_ARGS__)
-#define log_debug(M, ...)   custom_log("\x1b[36mDEBUG \x1b[0m", M, ##__VA_ARGS__)
-#define log_info(M, ...)    custom_log("\x1b[32mINFO  \x1b[0m", M, ##__VA_ARGS__)
-#define log_warn(M, ...)    custom_log("\x1b[33mWARN  \x1b[0m", M, ##__VA_ARGS__)
-#define log_error(M, ...)   custom_log("\x1b[31mERROR \x1b[0m", M, ##__VA_ARGS__)
-#define log_assert(M, ...)  custom_log("\x1b[35mASSERT\x1b[0m", M, ##__VA_ARGS__)
-#else
-#define log_trace(M, ...)   custom_log("TRACE ", M, ##__VA_ARGS__)
-#define log_debug(M, ...)   custom_log("DEBUG ", M, ##__VA_ARGS__)
-#define log_info(M, ...)    custom_log("INFO  ", M, ##__VA_ARGS__)
-#define log_warn(M, ...)    custom_log("WARN  ", M, ##__VA_ARGS__)
-#define log_error(M, ...)   custom_log("ERROR ", M, ##__VA_ARGS__)
-#define log_assert(M, ...)  custom_log("ASSERT", M, ##__VA_ARGS__)
-#endif
-#define log_buf(pbuf, len)  log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_HEX)
-#define log_buf_int8(pbuf, len)  log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_INT8)
-#define log_buf_unt8(pbuf, len)  log_buf_out(SHORT_FILE, __LINE__, pbuf, len, LOG_BUF_OUT_DATA_TYPE_UNT8)
-#define log_compile_time()  do {\
-                            log_info("compile date = %s\r\n", __DATE__);\
-                            log_info("compile time = %s\r\n", __TIME__);\
-                            } while (0 == 1);
-
-int log_buf_out(const char *file, int line, const void *inbuf, int len, LOG_BUF_OUT_DATA_TYPE_T type);
-
-void bl_printk(const char *format, ...);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_md5.h b/bsp/bl808/m0/libraries/utils/include/utils_md5.h
deleted file mode 100644
index 2ac9461e9f..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_md5.h
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_MD5_H_
-#define _IOTX_COMMON_MD5_H_
-
-#include "iot_import.h"
-
-typedef struct {
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[4];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-} iot_md5_context;
-
-/**
- * \brief          Initialize MD5 context
- *
- * \param ctx      MD5 context to be initialized
- */
-void utils_md5_init(iot_md5_context *ctx);
-
-/**
- * \brief          Clear MD5 context
- *
- * \param ctx      MD5 context to be cleared
- */
-void utils_md5_free(iot_md5_context *ctx);
-
-/**
- * \brief          Clone (the state of) an MD5 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void utils_md5_clone(iot_md5_context *dst,
-                     const iot_md5_context *src);
-
-/**
- * \brief          MD5 context setup
- *
- * \param ctx      context to be initialized
- */
-void utils_md5_starts(iot_md5_context *ctx);
-
-/**
- * \brief          MD5 process buffer
- *
- * \param ctx      MD5 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void utils_md5_update(iot_md5_context *ctx, const unsigned char *input, size_t ilen);
-
-/**
- * \brief          MD5 final digest
- *
- * \param ctx      MD5 context
- * \param output   MD5 checksum result
- */
-void utils_md5_finish(iot_md5_context *ctx, unsigned char output[16]);
-
-/* Internal use */
-void utils_md5_process(iot_md5_context *ctx, const unsigned char data[64]);
-
-/**
- * \brief          Output = MD5( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   MD5 checksum result
- */
-void utils_md5(const unsigned char *input, size_t ilen, unsigned char output[16]);
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_memp.h b/bsp/bl808/m0/libraries/utils/include/utils_memp.h
deleted file mode 100644
index e89951d7e4..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_memp.h
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_MEMP_H__
-#define __UTILS_MEMP_H__
-
-
-struct utils_memp_node {
-    struct utils_memp_node *next;
-};
-
-typedef struct pool {
-    uint32_t node_size;
-    uint32_t pool_cap;
-    uint32_t pool_size;
-    uint8_t align_req;
-    uint32_t padded_node_size;
-    void *first_node;
-    void *last_node;
-    struct utils_memp_node *mem;
-}utils_memp_pool_t;
-
-int utils_memp_init(utils_memp_pool_t **pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req);
-int utils_memp_init_alloced(utils_memp_pool_t *pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req);
-int utils_memp_deinit(utils_memp_pool_t *pool);
-void *utils_memp_malloc(utils_memp_pool_t *pool);
-int utils_memp_free(utils_memp_pool_t *pool, void *node);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_notifier.h b/bsp/bl808/m0/libraries/utils/include/utils_notifier.h
deleted file mode 100644
index 3120cb004c..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_notifier.h
+++ /dev/null
@@ -1,51 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __NOTIFIER_H__
-#define __NOTIFIER_H__
-
-#include 
-
-typedef struct utils_list ntf_list_t;
-typedef int (*utils_notifier_fn_t)(void *cb_arg, void *env);
-
-typedef struct utils_notifier {
-    struct utils_list_hdr node;
-    utils_notifier_fn_t cb;
-    void *cb_arg;
-    int priority;
-} utils_notifier_t;
-
-int utils_notifier_chain_init(ntf_list_t *nl);
-int utils_notifier_chain_register(ntf_list_t *nl, utils_notifier_t *node);
-int utils_notifier_chain_call(ntf_list_t *nl, void *env);
-
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h b/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h
deleted file mode 100644
index d178344b0b..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_psk_fast.h
+++ /dev/null
@@ -1,36 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_PSK_FAST_H__
-#define __UTILS_PSK_FAST_H__
-
-int utils_wifi_psk_cal_fast(char *password, char *ssid, int ssid_len, char *output);
-int utils_wifi_psk_cal_fast_bin(char *password, unsigned char *ssid, int ssidlength, unsigned char *output);
-
-#endif /* __UTILS_PSK_FAST_H__ */
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h b/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h
deleted file mode 100644
index 068b3daa4a..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_rbtree.h
+++ /dev/null
@@ -1,100 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef __UTILS_RBTREE_H__
-#define __UTILS_RBTREE_H__
-
-#include 
-#include 
-#include 
-
-#ifndef RB_ITER_MAX_HEIGHT
-#define RB_ITER_MAX_HEIGHT 64 // Tallest allowable tree to iterate
-#endif
-
-struct rb_node;
-struct rb_tree;
-
-typedef int  (*rb_tree_node_cmp_f) (struct rb_tree *self, struct rb_node *a, struct rb_node *b);
-typedef void (*rb_tree_node_f)     (struct rb_tree *self, struct rb_node *node);
-
-struct rb_node {
-    int             red;     // Color red (1), black (0)
-    struct rb_node *link[2]; // Link left [0] and right [1]
-    void           *value;   // User provided, used indirectly via rb_tree_node_cmp_f.
-};
-
-struct rb_tree {
-    struct rb_node    *root;
-    rb_tree_node_cmp_f cmp;
-    size_t             size;
-    void              *info; // User provided, not used by rb_tree.
-};
-
-struct rb_iter {
-    struct rb_tree *tree;
-    struct rb_node *node;                     // Current node
-    struct rb_node *path[RB_ITER_MAX_HEIGHT]; // Traversal path
-    size_t          top;                      // Top of stack
-    void           *info;                     // User provided, not used by rb_iter.
-};
-
-int             rb_tree_node_cmp_ptr_cb (struct rb_tree *self, struct rb_node *a, struct rb_node *b);
-void            rb_tree_node_dealloc_cb (struct rb_tree *self, struct rb_node *node);
-
-struct rb_node *rb_node_alloc           ();
-struct rb_node *rb_node_create          (void *value);
-struct rb_node *rb_node_init            (struct rb_node *self, void *value);
-void            rb_node_dealloc         (struct rb_node *self);
-
-struct rb_tree *rb_tree_alloc           ();
-struct rb_tree *rb_tree_create          (rb_tree_node_cmp_f cmp);
-struct rb_tree *rb_tree_init            (struct rb_tree *self, rb_tree_node_cmp_f cmp);
-void            rb_tree_dealloc         (struct rb_tree *self, rb_tree_node_f node_cb);
-void           *rb_tree_find            (struct rb_tree *self, void *value);
-int             rb_tree_insert          (struct rb_tree *self, void *value);
-int             rb_tree_remove          (struct rb_tree *self, void *value);
-size_t          rb_tree_size            (struct rb_tree *self);
-
-int             rb_tree_insert_node     (struct rb_tree *self, struct rb_node *node);
-int             rb_tree_remove_with_cb  (struct rb_tree *self, void *value, rb_tree_node_f node_cb);
-
-int             rb_tree_test            (struct rb_tree *self, struct rb_node *root);
-
-struct rb_iter *rb_iter_alloc           ();
-struct rb_iter *rb_iter_init            ();
-struct rb_iter *rb_iter_create          ();
-void            rb_iter_dealloc         (struct rb_iter *self);
-void           *rb_iter_first           (struct rb_iter *self, struct rb_tree *tree);
-void           *rb_iter_last            (struct rb_iter *self, struct rb_tree *tree);
-void           *rb_iter_next            (struct rb_iter *self);
-void           *rb_iter_prev            (struct rb_iter *self);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h b/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h
deleted file mode 100644
index 91526bccf1..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_ringblk.h
+++ /dev/null
@@ -1,136 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifndef _UTILS_RINGBLK_H_
-#define _UTILS_RINGBLK_H_
-
-
-#include "stddef.h"
-#include 
-#include "utils_list.h"
-
-
-#define UTILS_RINGBLK_TEST
-
-/*
- * Introduction:
- * The rbb is the ring buffer which is composed with many blocks. It is different from the ring buffer.
- * The ring buffer is only composed with chars. The rbb put and get supported zero copies. So the rbb
- * is very suitable for put block and get block by a certain order. Such as DMA block transmit,
- * communicate frame send/recv, and so on.
- */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-enum utils_rbb_status
-{
-    /* unused status when first initialize or after blk_free() */
-    RBB_BLK_UNUSED,
-    /* initialized status after blk_alloc() */
-    RBB_BLK_INITED,
-    /* put status after blk_put() */
-    RBB_BLK_PUT,
-    /* get status after blk_get() */
-    RBB_BLK_GET,
-};
-typedef enum utils_rbb_status utils_rbb_status_t;
-
-/**
- * the block of rbb
- */
-struct utils_rbb_blk
-{
-    utils_rbb_status_t status :8;
-    /* less then 2^24 */
-    uint32_t size :24;
-    uint8_t *buf;
-    utils_slist_t list;
-};
-typedef struct utils_rbb_blk *utils_rbb_blk_t;
-
-/**
- * Rbb block queue: the blocks (from block1->buf to blockn->buf) memory which on this queue is continuous.
- */
-struct utils_rbb_blk_queue
-{
-    utils_rbb_blk_t blocks;
-    uint32_t blk_num;
-};
-typedef struct utils_rbb_blk_queue *utils_rbb_blk_queue_t;
-
-/**
- * ring block buffer
- */
-struct utils_rbb
-{
-    uint8_t *buf;
-    uint32_t buf_size;
-    /* all of blocks */
-    utils_rbb_blk_t blk_set;
-    uint32_t blk_max_num;
-    /* saved the initialized and put status blocks */
-    utils_slist_t blk_list;
-};
-typedef struct utils_rbb *utils_rbb_t;
-
-/* rbb (ring block buffer) API */
-void utils_rbb_init(utils_rbb_t rbb, uint8_t *buf, uint32_t buf_size, utils_rbb_blk_t block_set, uint32_t blk_max_num);
-uint32_t utils_rbb_get_buf_size(utils_rbb_t rbb);
-
-utils_rbb_t utils_rbb_create(uint32_t buf_size, uint32_t blk_max_num);
-void utils_rbb_destroy(utils_rbb_t rbb);
-
-/* rbb block API */
-utils_rbb_blk_t utils_rbb_blk_alloc(utils_rbb_t rbb, uint32_t blk_size);
-void utils_rbb_blk_put(utils_rbb_blk_t block);
-utils_rbb_blk_t utils_rbb_blk_get(utils_rbb_t rbb);
-uint32_t utils_rbb_blk_size(utils_rbb_blk_t block);
-uint8_t *utils_rbb_blk_buf(utils_rbb_blk_t block);
-void utils_rbb_blk_free(utils_rbb_t rbb, utils_rbb_blk_t block);
-utils_rbb_blk_t utils_rbb_find_empty_blk(utils_rbb_t rbb);
-utils_rbb_blk_t utils_rbb_find_used_blk(utils_rbb_t rbb);
-
-/* rbb block queue API */
-uint32_t utils_rbb_blk_queue_get(utils_rbb_t rbb, uint32_t queue_data_len, utils_rbb_blk_queue_t blk_queue);
-uint32_t utils_rbb_blk_queue_len(utils_rbb_blk_queue_t blk_queue);
-uint8_t *utils_rbb_blk_queue_buf(utils_rbb_blk_queue_t blk_queue);
-void utils_rbb_blk_queue_free(utils_rbb_t rbb, utils_rbb_blk_queue_t blk_queue);
-uint32_t utils_rbb_next_blk_queue_len(utils_rbb_t rbb);
-
-
-int utils_rbb_cli_init(void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _UTILS_RINGBLK_H_ */
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_sha1.h b/bsp/bl808/m0/libraries/utils/include/utils_sha1.h
deleted file mode 100644
index 422ee3d59e..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_sha1.h
+++ /dev/null
@@ -1,108 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_SHA1_H_
-#define _IOTX_COMMON_SHA1_H_
-
-#include "iot_import.h"
-
-
-/**
- * \brief          SHA-1 context structure
- */
-typedef struct {
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[5];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-} iot_sha1_context;
-
-/**
- * \brief          Initialize SHA-1 context
- *
- * \param ctx      SHA-1 context to be initialized
- */
-void utils_sha1_init(iot_sha1_context *ctx);
-
-/**
- * \brief          Clear SHA-1 context
- *
- * \param ctx      SHA-1 context to be cleared
- */
-void utils_sha1_free(iot_sha1_context *ctx);
-
-/**
- * \brief          Clone (the state of) a SHA-1 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void utils_sha1_clone(iot_sha1_context *dst,
-                      const iot_sha1_context *src);
-
-/**
- * \brief          SHA-1 context setup
- *
- * \param ctx      context to be initialized
- */
-void utils_sha1_starts(iot_sha1_context *ctx);
-
-/**
- * \brief          SHA-1 process buffer
- *
- * \param ctx      SHA-1 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void utils_sha1_update(iot_sha1_context *ctx, const unsigned char *input, size_t ilen);
-
-/**
- * \brief          SHA-1 final digest
- *
- * \param ctx      SHA-1 context
- * \param output   SHA-1 checksum result
- */
-void utils_sha1_finish(iot_sha1_context *ctx, unsigned char output[20]);
-
-/* Internal use */
-void utils_sha1_process(iot_sha1_context *ctx, const unsigned char data[64]);
-
-/**
- * \brief          Output = SHA-1( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   SHA-1 checksum result
- */
-void utils_sha1(const unsigned char *input, size_t ilen, unsigned char output[20]);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_sha256.h b/bsp/bl808/m0/libraries/utils/include/utils_sha256.h
deleted file mode 100644
index 42379eba45..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_sha256.h
+++ /dev/null
@@ -1,119 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-
-
-#ifndef _IOTX_COMMON_SHA256_H_
-#define _IOTX_COMMON_SHA256_H_
-
-#include 
-
-#define SHA256_DIGEST_LENGTH            (32)
-#define SHA256_BLOCK_LENGTH             (64)
-#define SHA256_SHORT_BLOCK_LENGTH       (SHA256_BLOCK_LENGTH - 8)
-#define SHA256_DIGEST_STRING_LENGTH     (SHA256_DIGEST_LENGTH * 2 + 1)
-
-/**
- * \brief          SHA-256 context structure
- */
-typedef struct {
-    uint32_t total[2];          /*!< number of bytes processed  */
-    uint32_t state[8];          /*!< intermediate digest state  */
-    unsigned char buffer[64];   /*!< data block being processed */
-    int is224;                  /*!< 0 => SHA-256, else SHA-224 */
-} iot_sha256_context;
-
-typedef union {
-    char sptr[8];
-    uint64_t lint;
-} u_retLen;
-
-/**
- * \brief          Initialize SHA-256 context
- *
- * \param ctx      SHA-256 context to be initialized
- */
-void utils_sha256_init(iot_sha256_context *ctx);
-
-/**
- * \brief          Clear SHA-256 context
- *
- * \param ctx      SHA-256 context to be cleared
- */
-void utils_sha256_free(iot_sha256_context *ctx);
-
-/**
- * \brief          Clone (the state of) a SHA-256 context
- *
- * \param dst      The destination context
- * \param src      The context to be cloned
- */
-void utils_sha256_clone(iot_sha256_context *dst,
-                        const iot_sha256_context *src);
-
-/**
- * \brief          SHA-256 context setup
- *
- * \param ctx      context to be initialized
- */
-void utils_sha256_starts(iot_sha256_context *ctx);
-
-/**
- * \brief          SHA-256 process buffer
- *
- * \param ctx      SHA-256 context
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- */
-void utils_sha256_update(iot_sha256_context *ctx, const unsigned char *input, uint32_t ilen);
-
-/**
- * \brief          SHA-256 final digest
- *
- * \param ctx      SHA-256 context
- * \param output   SHA-256 checksum result
- */
-void utils_sha256_finish(iot_sha256_context *ctx, uint8_t output[32]);
-
-/* Internal use */
-void utils_sha256_process(iot_sha256_context *ctx, const unsigned char data[64]);
-
-/**
- * \brief          Output = SHA-256( input buffer )
- *
- * \param input    buffer holding the  data
- * \param ilen     length of the input data
- * \param output   SHA-256 checksum result
- */
-void utils_sha256(const uint8_t *input, uint32_t ilen, uint8_t output[32]);
-
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_string.h b/bsp/bl808/m0/libraries/utils/include/utils_string.h
deleted file mode 100644
index 6a7626ade6..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_string.h
+++ /dev/null
@@ -1,60 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_STRING_H__
-#define __UTILS_STRING_H__
-void get_bytearray_from_string(char** params, uint8_t *result,int array_size);
-void get_uint8_from_string(char** params, uint8_t *result);
-void get_uint16_from_string(char** params, uint16_t *result);
-void get_uint32_from_string(char** params, uint32_t *result);
-void utils_parse_number(const char *str, char sep, uint8_t *buf, int buflen, int base);
-void utils_parse_number_adv(const char *str, char sep, uint8_t *buf, int buflen, int base, int *count);
-unsigned long long convert_arrayToU64(uint8_t* inputArray);
-void convert_u64ToArray(unsigned long long inputU64, uint8_t result[8]);
-void utils_memcpy8(void *dst, void *src, size_t len);
-void utils_memcpy16(void *dst, void *src, size_t len);
-void utils_memcpy32(void *dst, void *src, size_t len);
-void utils_memcpy64(void *dst, void *src, size_t len);
-void utils_memset8(void *src, uint8_t n, size_t len);
-void utils_memset16(void *src, uint16_t n, size_t len);
-void utils_memset32(void *src, uint32_t n, size_t len);
-void utils_memset64(void *src, uint64_t n, size_t len);
-void utils_memset8_with_seq(void *src, uint8_t seq, size_t len);
-void utils_memset16_with_seq(void *src, uint16_t seq, size_t len);
-void utils_memset32_with_seq(void *src, uint32_t seq, size_t len);
-void utils_memset64_with_seq(void *src, uint64_t seq, size_t len);
-void utils_memdrain8(void *src, size_t len);
-void utils_memdrain16(void *src, size_t len);
-void utils_memdrain32(void *src, size_t len);
-void utils_memdrain64(void *src, size_t len);
-void * utils_memdrain8_with_check(void *src, size_t len, uint8_t seq);
-void * utils_memdrain16_with_check(void *src, size_t len, uint16_t seq);
-void * utils_memdrain32_with_check(void *src, size_t len, uint32_t seq);
-void * utils_memdrain64_with_check(void *src, size_t len, uint64_t seq);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_time.h b/bsp/bl808/m0/libraries/utils/include/utils_time.h
deleted file mode 100644
index 3c3466c535..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_time.h
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_TIME_H__
-#define __UTILS_TIME_H__
-typedef struct {
-    unsigned char ntp_hour;
-    unsigned char ntp_minute;
-    unsigned char ntp_second;
-    unsigned char ntp_week_day;
-    unsigned char ntp_date;
-    unsigned char ntp_month;
-    unsigned char leap_days;
-    unsigned char leap_year_ind;
-    unsigned int ntp_year;
-    unsigned int days_since_epoch;
-    unsigned int day_of_year;
-} utils_time_date_t;
-
-int utils_time_date_from_epoch(unsigned int epoch, utils_time_date_t *date);
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h b/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h
deleted file mode 100644
index 8ee870f6c6..0000000000
--- a/bsp/bl808/m0/libraries/utils/include/utils_tlv_bl.h
+++ /dev/null
@@ -1,80 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#ifndef __UTILS_TLV_BL_H__
-#define __UTILS_TLV_BL_H__
-#include 
-#include 
-
-#define CFG_ELEMENT_TYPE_SIZE_BOOLEAN                 (4)
-#define CFG_ELEMENT_TYPE_SIZE_UINT32                  (4)
-#define UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL         (-1)
-#define UTILS_TLV_BL_ERROR_CODE_UNKOWN                (-2)
-// Wi-Fi CFG API
-enum CFG_ELEMENT_TYPE {
-    CFG_ELEMENT_TYPE_UNKNOWN,
-    CFG_ELEMENT_TYPE_BOOLEAN,
-    CFG_ELEMENT_TYPE_SINT8,
-    CFG_ELEMENT_TYPE_UINT8,
-    CFG_ELEMENT_TYPE_SINT16,
-    CFG_ELEMENT_TYPE_UINT16,
-    CFG_ELEMENT_TYPE_SINT32,
-    CFG_ELEMENT_TYPE_UINT32,
-    CFG_ELEMENT_TYPE_STRING,
-};
-
-enum CFG_ELEMENT_TYPE_OPS
-{
-    CFG_ELEMENT_TYPE_OPS_SET,
-    CFG_ELEMENT_TYPE_OPS_GET,
-    CFG_ELEMENT_TYPE_OPS_RESET,
-    CFG_ELEMENT_TYPE_OPS_DUMP_DEBUG,
-    CFG_ELEMENT_TYPE_OPS_UNKNOWN,
-};
-
-int utils_tlv_bl_pack_bool(uint32_t *buf, int buf_sz, bool val);
-int utils_tlv_bl_pack_uint8(uint32_t *buf, int buf_sz, uint8_t val);
-int utils_tlv_bl_pack_int8(uint32_t *buf, int buf_sz, int8_t val);
-int utils_tlv_bl_pack_uint16(uint32_t *buf, int buf_sz, uint16_t val);
-int utils_tlv_bl_pack_int16(uint32_t *buf, int buf_sz, int16_t val);
-int utils_tlv_bl_pack_uint32(uint32_t *buf, int buf_sz, uint32_t val);
-int utils_tlv_bl_pack_int32(uint32_t *buf, int buf_sz, int32_t val);
-int utils_tlv_bl_pack_string(uint32_t *buf, int buf_sz, const char *str);
-int utils_tlv_bl_pack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1);
-
-int utils_tlv_bl_unpack_bool(uint32_t *buf, int buf_sz, bool *val);
-int utils_tlv_bl_unpack_uint8(uint32_t *buf, int buf_sz, uint8_t *val);
-int utils_tlv_bl_unpack_int8(uint32_t *buf, int buf_sz, int8_t *val);
-int utils_tlv_bl_unpack_uint16(uint32_t *buf, int buf_sz, uint16_t *val);
-int utils_tlv_bl_unpack_int16(uint32_t *buf, int buf_sz, int16_t *val);
-int utils_tlv_bl_unpack_uint32(uint32_t *buf, int buf_sz, uint32_t *val);
-int utils_tlv_bl_unpack_int32(uint32_t *buf, int buf_sz, int32_t *val);
-int utils_tlv_bl_unpack_string(uint32_t *buf, int buf_sz, char *str, int size);
-int utils_tlv_bl_unpack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1);
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c
deleted file mode 100644
index 0dee7bc1fc..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_base64.c
+++ /dev/null
@@ -1,109 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-#include "utils_base64.h"
-#include 
-
-#ifdef UTILS_BASE64_TEST
-
-static void cmd_encode(char *buf, int len, int argc, char **argv)
-{
-    uint32_t input_len, output_len = 0;
-    char *inbuf, *outbuf = NULL;
-
-    if (argc != 3)
-    {
-        log_error("Usage:\r\n");
-        log_error("encode_base64 0x420c0000 512\r\n");
-        return;
-    }
-
-    inbuf = (char *)strtol(argv[1], NULL, 0);
-    input_len = strtol(argv[2], NULL, 0);
-    if (inbuf != NULL && input_len != 0)
-    {
-        output_len = 4 * ((input_len + 2) / 3);
-        outbuf = calloc(1, output_len);
-
-        if (outbuf)
-        {
-            if (SUCCESS_RETURN == utils_base64encode((uint8_t *)inbuf, input_len, output_len, (uint8_t *)outbuf, &output_len))
-            {
-                uint32_t i = 0;
-                char *addr = outbuf;
-                for (i = 0; i < output_len; i++)
-                {
-                #ifdef CONFIG_CLI_CMD_ENABLE
-                    aos_cli_printf("%c", *(char *)addr);
-                #endif
-                    addr += 1;
-                }
-            }
-            else
-            {
-                log_error("base64 encode error\r\n");
-            }
-
-            free(outbuf);
-        }
-        else
-        {
-            log_error("base64 encode mem not enough %d\r\n", output_len);
-        }
-    }
-    else
-    {
-        log_error("base64 encode argc error\r\n");
-    }
-
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-        { "encode_base64", "base64 encode", cmd_encode},
-};
-#endif
-
-int base64_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));
-    return 0;
-}
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c
deleted file mode 100644
index f2cc9e9146..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_bitmap_window.c
+++ /dev/null
@@ -1,105 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-#include 
-
-static void cmd_bitmap_window_test(char *buf, int len, int argc, char **argv)
-{
-    int ret;
-    struct utils_bitmap_ctx ctx;
-
-    utils_bitmap_window_init(&ctx, 0, 4095);
-
-    printf("Set Seq 1 2 3 4 5 6 7...\r\n");
-    utils_bitmap_window_bit_set(&ctx, 1);
-    utils_bitmap_window_bit_set(&ctx, 2);
-    utils_bitmap_window_bit_set(&ctx, 3);
-    utils_bitmap_window_bit_set(&ctx, 4);
-    utils_bitmap_window_bit_set(&ctx, 5);
-    utils_bitmap_window_bit_set(&ctx, 6);
-    ret = utils_bitmap_window_bit_set(&ctx, 7);
-    printf("  Got ssn %d(0) Bitmap %llx(0), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 0 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 0);
-    printf("  Got ssn %d(8) Bitmap %llx(0), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 0 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 0);
-    printf("  Got ssn %d(8) Bitmap %llx(0), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 9 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 9);
-    printf("  Got ssn %d(8) Bitmap %llx(2), ret %x\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-    printf("Set Seq 9 ...\r\n");
-    ret = utils_bitmap_window_bit_set(&ctx, 9);
-    printf("  Got ssn %d(8) Bitmap %llx(2), ret %d\r\n",
-        utils_bitmap_window_ssn_get(&ctx),
-        utils_bitmap_window_map_get(&ctx),
-        ret
-    );
-
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-  {"utils_bitmap_widow_test", "bitmap window test", cmd_bitmap_window_test},
-};
-#endif
-
-int utils_bitmap_window_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c
deleted file mode 100644
index 25c68fe710..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_rbtree.c
+++ /dev/null
@@ -1,94 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "../../include/utils_rbtree.h"
-#include 
-#include 
-
-struct iovec {
-    void  *iov_base; // [XSI] Base address of I/O memory region
-    size_t iov_len;  // [XSI] Size of region iov_base points to
-};
-
-static int my_cmp_cb(struct rb_tree *self, struct rb_node *node_a, struct rb_node *node_b)
-{
-    struct iovec *a = (struct iovec *) node_a->value;
-    struct iovec *b = (struct iovec *) node_b->value;
-
-    return (a->iov_len > b->iov_len) - (a->iov_len < b->iov_len);
-}
-
-int main(int argc, char *argv[])
-{
-    struct rb_tree *tree = rb_tree_create(my_cmp_cb);
-    if (tree) {
-        // Use the tree here...
-        for (int i = 0; i < 10; i++) {
-            struct iovec *v = malloc(sizeof *v);
-            v->iov_base = (void *) i;
-            v->iov_len = i * i;
-            // Default insert, which allocates internal rb_nodes for you.
-            printf("[rb_tree_insert] insert %p with base %p len %d\r\n",
-                    v,
-                    v->iov_base,
-                    v->iov_len
-            );
-            rb_tree_insert(tree, v);
-        }
-
-        // To f
-        struct iovec *f = rb_tree_find(tree,
-                & (struct iovec) { .iov_base = (void *) 7, .iov_len = 0 }
-        );
-        if (f) {
-            printf("[rb_tree_find] found iovec %p(.iov_base = %p, .iov_len = %zu)\n", f, f->iov_base, f->iov_len);
-        } else {
-            printf("[rb_tree_find] iov_len 9 not found\n");
-        }
-
-        printf("[rb_tree_test] testing...\r\n");
-        rb_tree_test(tree, f);
-
-        f = rb_tree_find(tree,
-                & (struct iovec) { .iov_base = (void *) 7, .iov_len = 10 }
-        );
-        if (f) {
-            printf("[rb_tree_find] found iovec %p(.iov_base = %p, .iov_len = %zu)\n", f, f->iov_base, f->iov_len);
-        } else {
-            printf("[rb_tree_find] iov_len 10 not found\n");
-        }
-
-        printf("[rb_tree_size] is %d\r\n", rb_tree_size(tree));
-
-        // Dealloc call can take optional parameter to notify on each node
-        // being deleted so you can free the node and/or your object:
-        rb_tree_dealloc(tree, NULL);
-    }
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c b/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c
deleted file mode 100644
index b79f7cd5ac..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/test/test_utils_ringblk.c
+++ /dev/null
@@ -1,388 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-#include 
-#include 
-#include 
-#include 
-
-#include 
-#include 
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-#include 
-#endif
-#include "utils_ringblk.h"
-
-#ifdef UTILS_RINGBLK_TEST
-
-
-static void cmd_ringblk_test(char *buf, int len, int argc, char **argv)
-{
-    utils_rbb_t rbb;
-    utils_rbb_blk_t blk1, blk2, blk3, blk4, blk5, blk6, _blk1, _blk2;
-    uint32_t i, j, k, req_size, size;
-    struct utils_rbb_blk_queue blk_queue1;
-
-    /* create ring block buffer */
-    printf("\n====================== rbb create test =====================\r\n");
-    rbb = utils_rbb_create(52, 6);
-    if (rbb)
-    {
-        printf("6 blocks in 52 bytes ring block buffer object create success.\r\n");
-    }
-    else
-    {
-        printf("Test error: 6 blocks in 52 bytes ring block buffer object create failed.\r\n");
-    }
-    /* allocate block */
-    printf("\n====================== rbb alloc test =====================\r\n");
-    blk1 = utils_rbb_blk_alloc(rbb, 2);
-    if (blk1 && blk1->size == 2)
-    {
-        memset(blk1->buf, 1, blk1->size);
-        printf("Block1 (2 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block1 (2 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk2 = utils_rbb_blk_alloc(rbb, 4);
-    if (blk2 && blk2->size == 4)
-    {
-        memset(blk2->buf, 2, blk2->size);
-        printf("Block2 (4 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block2 (4 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk3 = utils_rbb_blk_alloc(rbb, 8);
-    if (blk3 && blk3->size == 8)
-    {
-        memset(blk3->buf, 3, blk3->size);
-        printf("Block3 (8 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block3 (8 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk4 = utils_rbb_blk_alloc(rbb, 16);
-    if (blk4 && blk4->size == 16)
-    {
-        memset(blk4->buf, 4, blk4->size);
-        printf("Block4 (16 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block4 (16 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    blk5 = utils_rbb_blk_alloc(rbb, 32);
-    if (blk5 && blk5->size == 32)
-    {
-        memset(blk5->buf, 5, blk5->size);
-        printf("Block5 (32 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Block5 (32 bytes) allocate failed.\r\n");
-    }
-    blk5 = utils_rbb_blk_alloc(rbb, 18);
-    if (blk5 && blk5->size == 18)
-    {
-        memset(blk5->buf, 5, blk5->size);
-        printf("Block5 (18 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block5 (18 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| blcok1 | block2  |    block3    |       block4        |       block5     |    empty    |\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| inited | inited  |    inited    |       inited        |       inited     |             |\r\n");
-    //
-    /* put block */
-    printf("\n====================== rbb put test =====================\r\n");
-    utils_rbb_blk_put(blk1);
-    utils_rbb_blk_put(blk2);
-    utils_rbb_blk_put(blk3);
-    utils_rbb_blk_put(blk4);
-    utils_rbb_blk_put(blk5);
-    printf("Block1 to block5 put success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| blcok1 | block2  |    block3    |       block4        |       block5     |    empty    |\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|  put   |  put    |     put      |        put          |        put       |             |\r\n");
-    //
-    /* get block */
-    printf("\n====================== rbb get test =====================\r\n");
-    _blk1 = utils_rbb_blk_get(rbb);
-    _blk2 = utils_rbb_blk_get(rbb);
-    for (i = 0; i < _blk1->size; i++)
-    {
-        if (_blk1->buf[i] != 1) break;
-    }
-    for (j = 0; j < _blk2->size; j++)
-    {
-        if (_blk2->buf[j] != 2) break;
-    }
-    if (blk1 == _blk1 && blk2 == _blk2 && i == _blk1->size && j == _blk2->size)
-    {
-        printf("Block1 and block2 get success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block1 and block2 get failed.\r\n");
-        goto __exit;
-    }
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<- 2 -->|<-- 4 -->|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("| blcok1 | block2  |    block3    |       block4        |       block5     |    empty    |\r\n");
-    printf("+--------+---------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|  get   |   get   |     put      |        put          |        put       |             |\r\n");
-    //
-    /* free block */
-    printf("\n====================== rbb free test =====================\r\n");
-    utils_rbb_blk_free(rbb, blk2);
-    printf("Block2 free success.\r\n");
-    utils_rbb_blk_free(rbb, blk1);
-    printf("Block1 free success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<------- 6 ------>|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+------------------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|      empty2      |    block3    |       block4        |       block5     |    empty1   |\r\n");
-    printf("+------------------+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|                  |     put      |        put          |        put       |             |\r\n");
-
-    blk6 = utils_rbb_blk_alloc(rbb, 5);
-    if (blk6)
-    {
-        printf("Block6 (5 bytes) allocate success.\r\n");
-    }
-    else
-    {
-        printf("Test error: block6 (5 bytes) allocate failed.\r\n");
-        goto __exit;
-    }
-
-    utils_rbb_blk_put(blk6);
-    printf("Block6 put success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<--- 5 ---->|< 1 >|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|   block6   |empty|    block3    |       block4        |       block5     |   fragment  |\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|     put    |     |     put      |        put          |        put       |             |\r\n");
-
-    /* get block queue */
-    printf("\n====================== rbb block queue get test =====================\r\n");
-    req_size = utils_rbb_next_blk_queue_len(rbb) + 5;
-    size = utils_rbb_blk_queue_get(rbb, req_size, &blk_queue1);
-    i = j = k = 0;
-    for (; i < blk3->size; i++)
-    {
-        if (utils_rbb_blk_queue_buf(&blk_queue1)[i] != 3) break;
-    }
-    for (; j < blk4->size; j++)
-    {
-        if (utils_rbb_blk_queue_buf(&blk_queue1)[i + j] != 4) break;
-    }
-    for (; k < blk5->size; k++)
-    {
-        if (utils_rbb_blk_queue_buf(&blk_queue1)[i + j + k] != 5) break;
-    }
-    if (size && size == 42 && utils_rbb_blk_queue_len(&blk_queue1) == 42 && k == blk5->size)
-    {
-        printf("Block queue (request %"PRIu32" bytes, actual %"PRIu32") get success.\r\n", req_size, size);
-    }
-    else
-    {
-        printf("Test error: Block queue (request %"PRIu32" bytes, actual %"PRIu32") get failed.\r\n", req_size, size);
-        goto __exit;
-    }
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|            |     |<----- block queue1 (42 bytes continuous buffer) ----->|             |\r\n");
-    printf("|<--- 5 ---->|< 1 >|<---- 8 ----->|<------- 16 -------->|<------ 18 ------>|<---- 4 ---->|\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|   block6   |empty|    block3    |       block4        |       block5     |   fragment  |\r\n");
-    printf("+------------+-----+--------------+---------------------+------------------+-------------+\r\n");
-    printf("|     put    |     |     get      |        get          |        get       |             |\r\n");
-
-    /* free block queue */
-    printf("\n====================== rbb block queue free test =====================\r\n");
-    utils_rbb_blk_queue_free(rbb, &blk_queue1);
-    printf("Block queue1 free success.\r\n");
-    printf("Ring block buffer current status:\r\n");
-    printf("next block queue length: %"PRIu32"\r\n", utils_rbb_next_blk_queue_len(rbb));
-    printf("block list length: %d\r\n", utils_slist_entry_number(&rbb->blk_list));
-    printf("|<--- 5 ---->|<--------------------------------- 47 ------------------------------------>|\r\n");
-    printf("+------------+---------------------------------------------------------------------------+\r\n");
-    printf("|   block6   |                                 empty                                     |\r\n");
-    printf("+------------+---------------------------------------------------------------------------+\r\n");
-    printf("|     put    |                                                                           |\r\n");
-    utils_rbb_blk_free(rbb, blk6);
-
-    printf("\n====================== rbb static test SUCCESS =====================\r\n");
-
-    printf("\n====================== rbb dynamic test =====================\r\n");
-
-__exit :
-
-    utils_rbb_destroy(rbb);
-}
-
-
-static uint8_t put_finish = 0;
-
-static void put_thread(void *param)
-{
-  utils_rbb_t rbb = (utils_rbb_t)param;
-  utils_rbb_blk_t block;
-  uint32_t put_count = 0;
-
-  put_finish = 0;
-
-  while (put_count < 10000)
-  {
-    block = utils_rbb_blk_alloc(rbb, rand() % 10 + 4);
-    if (block)
-    {
-      memcpy(&block->buf[0], (void *)&put_count, 4);
-      utils_rbb_blk_put(block);
-      printf("put block size %d count %" PRId32 "\r\n", block->size, put_count++);
-    }
-    else
-    {
-      printf("block alloc failed\r\n");
-    }
-    vTaskDelay(rand() % 10);
-  }
-  printf("Put block data finish.\r\n");
-
-  put_finish = 1;
-
-  vTaskDelete(NULL);
-}
-
-static void get_thread(void *param)
-{
-  utils_rbb_t rbb = (utils_rbb_t)param;
-  utils_rbb_blk_t block;
-  uint32_t get_count = 0;
-
-  while (get_count < 10000)
-  {
-    block = utils_rbb_blk_get(rbb);
-
-    if (block)
-    {
-      if (memcmp(&block->buf[0], (void *)&get_count, 4) != 0)
-      {
-        printf("Error: get data (times %" PRId32 ") has an error!\r\n", get_count);
-        goto exit_;
-      }
-      utils_rbb_blk_free(rbb, block);
-      printf("free block size %d count %" PRId32 "\r\n", block->size, get_count++);
-    }
-    else if (put_finish)
-    {
-      break;
-    }
-    vTaskDelay(rand() % 10);
-  }
-  printf("Get block data finish.\r\n");
-
-  utils_rbb_blk_t new_rbb = utils_rbb_find_used_blk(rbb);
-  if (new_rbb != NULL)
-  {
-    printf("\n====================== rbb blk not free =====================\r\n");
-  }
-
-exit_:
-  printf("\n====================== rbb dynamic test finish =====================\r\n");
-
-  utils_rbb_destroy(rbb);
-
-  vTaskDelete(NULL);
-}
-
-static void cmd_ringblk_through_test(char *buf, int len, int argc, char **argv)
-{
-  utils_rbb_t rbb;
-
-  rbb = utils_rbb_create(100, 10);
-
-  xTaskCreate(put_thread, "rbb_put", 1024, rbb, 10, NULL);
-
-  xTaskCreate(get_thread, "rbb_get", 1024, rbb, 10, NULL);
-}
-
-#ifdef CONFIG_CLI_CMD_ENABLE
-const static struct cli_command cmds_user[] STATIC_CLI_CMD_ATTRIBUTE = {
-  {"rbb_static_test", "ringblk static test", cmd_ringblk_test},
-  {"rbb_through_test", "ringblk dynamic test", cmd_ringblk_through_test},
-};
-#endif
-
-int utils_rbb_cli_init(void)
-{
-    // static command(s) do NOT need to call aos_cli_register_command(s) to register.
-    // However, calling aos_cli_register_command(s) here is OK but is of no effect as cmds_user are included in cmds list.
-    // XXX NOTE: Calling this *empty* function is necessary to make cmds_user in this file to be kept in the final link.
-    //return aos_cli_register_commands(cmds_user, sizeof(cmds_user) / sizeof(cmds_user[0]));
-    return 0;
-}
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_base64.c b/bsp/bl808/m0/libraries/utils/src/utils_base64.c
deleted file mode 100644
index c17b77e988..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_base64.c
+++ /dev/null
@@ -1,206 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include 
-#include "utils_base64.h"
-#include 
-
-static int8_t g_encodingTable[] = {'A', 'B', 'C', 'D', 'E', 'F', 'G', 'H',
-                                   'I', 'J', 'K', 'L', 'M', 'N', 'O', 'P',
-                                   'Q', 'R', 'S', 'T', 'U', 'V', 'W', 'X',
-                                   'Y', 'Z', 'a', 'b', 'c', 'd', 'e', 'f',
-                                   'g', 'h', 'i', 'j', 'k', 'l', 'm', 'n',
-                                   'o', 'p', 'q', 'r', 's', 't', 'u', 'v',
-                                   'w', 'x', 'y', 'z', '0', '1', '2', '3',
-                                   '4', '5', '6', '7', '8', '9', '+', '/'
-                                  };
-
-static int8_t g_decodingTable[256];
-static int32_t g_modTable[] = { 0, 2, 1 };
-
-static void build_decoding_table()
-{
-    static int32_t signal = 0;
-    int32_t i = 0;
-
-    if (signal != 0) {
-        return;
-    }
-
-    for (i = 0; i < 64; i++) {
-        g_decodingTable[(uint8_t) g_encodingTable[i]] = i;
-    }
-
-    signal = 1;
-    return;
-}
-
-iotx_err_t utils_base64encode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *encodedData, uint32_t *outputLength)
-{
-    uint32_t i = 0;
-    uint32_t j = 0;
-
-    if (NULL == encodedData) {
-        log_error("pointer of encodedData is NULL!\r\n");
-        return FAIL_RETURN;
-    }
-
-    *outputLength = 4 * ((inputLength + 2) / 3);
-
-    if (outputLenMax < *outputLength) {
-        log_error("the length of output memory is not enough!\r\n");
-        return FAIL_RETURN;
-    }
-
-    for (i = 0, j = 0; i < inputLength;) {
-        uint32_t octet_a = i < inputLength ? (uint8_t) data[i++] : 0;
-        uint32_t octet_b = i < inputLength ? (uint8_t) data[i++] : 0;
-        uint32_t octet_c = i < inputLength ? (uint8_t) data[i++] : 0;
-
-        uint32_t triple = (octet_a << 0x10) + (octet_b << 0x08) + octet_c;
-
-        encodedData[j++] = g_encodingTable[(triple >> 3 * 6) & 0x3F];
-        encodedData[j++] = g_encodingTable[(triple >> 2 * 6) & 0x3F];
-        encodedData[j++] = g_encodingTable[(triple >> 1 * 6) & 0x3F];
-        encodedData[j++] = g_encodingTable[(triple >> 0 * 6) & 0x3F];
-    }
-
-    for (i = 0; i < g_modTable[inputLength % 3]; i++) {
-        encodedData[*outputLength - 1 - i] = '=';
-    }
-
-    return SUCCESS_RETURN;
-}
-
-/*
- * Streaming Base64 encoder
- * param:
- *  read_data: The callback function when the encoder absorbs data.
- *             A non-zero return indicates the end of the data.
- *  write_data: The callback function when the encoder releases data.
- *  opaque: Callback function context.
- */
-void utils_base64_encode_stream(int (*read_data)(uint8_t *data, void *opaque), void (*write_data)(const uint8_t data[4], void *opaque), void *opaque)
-{
-  uint8_t encodedData[4], c;
-  int end = 0, remainder = -1, i;
-
-  while (!end) {
-    uint32_t octet_a = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 0), 0) : c;
-    uint32_t octet_b = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 1), 0) : c;
-    uint32_t octet_c = (end = read_data(&c, opaque)) ? (remainder = (remainder >= 0 ? remainder : 2), 0) : c;
-
-    uint32_t triple = (octet_a << 0x10) + (octet_b << 0x08) + octet_c;
-
-    if (end && remainder == 0) {
-      return;
-    }
-
-    encodedData[0] = g_encodingTable[(triple >> 3 * 6) & 0x3F];
-    encodedData[1] = g_encodingTable[(triple >> 2 * 6) & 0x3F];
-    encodedData[2] = g_encodingTable[(triple >> 1 * 6) & 0x3F];
-    encodedData[3] = g_encodingTable[(triple >> 0 * 6) & 0x3F];
-
-    if (!end) {
-      write_data(encodedData, opaque);
-    }
-  }
-
-  for (i = 0; i < g_modTable[remainder]; i++) {
-    encodedData[3 - i] = '=';
-  }
-
-  write_data(encodedData, opaque);
-
-  return;
-}
-
-iotx_err_t utils_base64decode(const uint8_t *data, uint32_t inputLength, uint32_t outputLenMax,
-                              uint8_t *decodedData, uint32_t *outputLength)
-{
-    uint32_t i = 0;
-    uint32_t j = 0;
-
-    build_decoding_table();
-
-    if (inputLength % 4 != 0) {
-        log_error("the input length is error!\r\n");
-        return FAIL_RETURN;
-    }
-
-    *outputLength = inputLength / 4 * 3;
-
-
-    if (data[inputLength - 1] == '=') {
-        (*outputLength)--;
-    }
-
-    if (data[inputLength - 2] == '=') {
-        (*outputLength)--;
-    }
-
-    if (outputLenMax < *outputLength) {
-        log_error("the length of output memory is not enough!\r\n");
-        return FAIL_RETURN;
-    }
-
-    uint32_t sextet_a = 0;
-    uint32_t sextet_b = 0;
-    uint32_t sextet_c = 0;
-    uint32_t sextet_d = 0;
-    uint32_t triple = 0;
-
-    for (i = 0, j = 0; i < inputLength;) {
-        sextet_a = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-        sextet_b = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-        sextet_c = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-        sextet_d = data[i] == '=' ? 0 & i++ : g_decodingTable[data[i++]];
-
-        triple = (sextet_a << 3 * 6) + (sextet_b << 2 * 6) + (sextet_c << 1 * 6) + (sextet_d << 0 * 6);
-
-        if (j < *outputLength) {
-            decodedData[j++] = (triple >> 2 * 8) & 0xFF;
-        }
-
-        if (j < *outputLength) {
-            decodedData[j++] = (triple >> 1 * 8) & 0xFF;
-        }
-
-        if (j < *outputLength) {
-            decodedData[j++] = (triple >> 0 * 8) & 0xFF;
-        }
-    }
-
-    return SUCCESS_RETURN;
-}
-
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c b/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c
deleted file mode 100644
index 3feb69c765..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_bitmap_window.c
+++ /dev/null
@@ -1,87 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-
-int utils_bitmap_window_init(struct utils_bitmap_ctx *ctx, int ssn, int ssn_max)
-{
-    memset(ctx, 0, sizeof(struct utils_bitmap_ctx));
-    ctx->ssn = ssn;
-    ctx->ssn_duration = ssn_max + 1;//ssn start from 0
-
-    return 0;
-}
-
-int utils_bitmap_window_bit_set(struct utils_bitmap_ctx *ctx, int bit_pos)
-{
-    int i;
-    int pos_offset;
-
-    if (bit_pos < ctx->ssn) {
-        /*failed case*/
-        if (ctx->ssn_duration - ctx->ssn + bit_pos + 1 > sizeof(ctx->bitmap) * 8) {
-            printf("small ssn %d\r\n", bit_pos);
-            return -INT_MAX;
-        }
-    }
-    pos_offset = bit_pos + ctx->ssn_duration - ctx->ssn;
-    if (pos_offset >= ctx->ssn_duration) {
-        pos_offset -= ctx->ssn_duration;
-    }
-
-    if (ctx->bitmap.map64 & (1 << pos_offset)) {
-        printf("Dup bit_pos %d with pos_offset %d\r\n", bit_pos, pos_offset);
-        return -bit_pos;
-    }
-    ctx->bitmap.map64 |= (1 << pos_offset);//TODO use bytearray
-
-    for (i = 0; i < sizeof(ctx->bitmap.bytes) * 8; i++) {
-        if (ctx->bitmap.map64 & 0x1) {
-            ctx->bitmap.map64 >>= 1;
-            ctx->ssn += 1;
-            if (ctx->ssn == ctx->ssn_duration) {
-                ctx->ssn = 0;
-            }
-        }
-    }
-    return pos_offset;
-}
-
-uint64_t utils_bitmap_window_map_get(struct utils_bitmap_ctx *ctx)
-{
-    return ctx->bitmap.map64;
-}
-
-int utils_bitmap_window_ssn_get(struct utils_bitmap_ctx *ctx)
-{
-    return ctx->ssn;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_crc.c b/bsp/bl808/m0/libraries/utils/src/utils_crc.c
deleted file mode 100644
index 237bb581b1..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_crc.c
+++ /dev/null
@@ -1,223 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-#include 
-
-// ---------------- POPULAR POLYNOMIALS ----------------
-// CCITT:      x^16 + x^12 + x^5 + x^0                 (0x1021,init 0x0000)
-// CRC-16:     x^16 + x^15 + x^2 + x^0                 (0x8005,init 0xFFFF)
-// we use 0x8005 here and
-
-static const uint8_t chCRCHTalbe[] =
-{
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41,
-0x00, 0xC1, 0x81, 0x40
-};
-
-static const uint8_t chCRCLTalbe[] =
-{
-0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7,
-0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E,
-0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9,
-0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC,
-0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3,
-0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32,
-0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D,
-0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38,
-0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF,
-0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26,
-0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1,
-0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4,
-0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB,
-0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA,
-0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5,
-0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0,
-0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97,
-0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E,
-0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89,
-0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C,
-0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83,
-0x41, 0x81, 0x80, 0x40
-};
-
-uint16_t utils_crc16(void * dataIn, uint32_t len)
-{
-    uint8_t chCRCHi = 0xFF;
-    uint8_t chCRCLo = 0xFF;
-    uint16_t wIndex;
-  uint8_t* data=(uint8_t *) dataIn;
-
-    while (len--)
-    {
-        wIndex = chCRCLo ^ *data++ ;
-        chCRCLo = chCRCHi ^ chCRCHTalbe[wIndex];
-        chCRCHi = chCRCLTalbe[wIndex] ;
-    }
-
-    return ((chCRCHi << 8) | chCRCLo) ;
-}
-
-/*
-x^32+x^26+x^23+x^22+x^16+x^12+x^11+x^10+x^8+x^7+x^5+x^4+x^2+x+1
-*/
-static const uint32_t crc32Tab[256] = {
-    0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f,
-    0xe963a535, 0x9e6495a3, 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988,
-    0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, 0x1db71064, 0x6ab020f2,
-    0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7,
-    0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9,
-    0xfa0f3d63, 0x8d080df5, 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172,
-    0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, 0x35b5a8fa, 0x42b2986c,
-    0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59,
-    0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423,
-    0xcfba9599, 0xb8bda50f, 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924,
-    0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, 0x76dc4190, 0x01db7106,
-    0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433,
-    0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d,
-    0x91646c97, 0xe6635c01, 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e,
-    0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, 0x65b0d9c6, 0x12b7e950,
-    0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65,
-    0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7,
-    0xa4d1c46d, 0xd3d6f4fb, 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0,
-    0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, 0x5005713c, 0x270241aa,
-    0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f,
-    0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81,
-    0xb7bd5c3b, 0xc0ba6cad, 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a,
-    0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, 0xe3630b12, 0x94643b84,
-    0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1,
-    0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb,
-    0x196c3671, 0x6e6b06e7, 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc,
-    0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, 0xd6d6a3e8, 0xa1d1937e,
-    0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b,
-    0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55,
-    0x316e8eef, 0x4669be79, 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236,
-    0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, 0xc5ba3bbe, 0xb2bd0b28,
-    0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d,
-    0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f,
-    0x72076785, 0x05005713, 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38,
-    0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, 0x86d3d2d4, 0xf1d4e242,
-    0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777,
-    0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69,
-    0x616bffd3, 0x166ccf45, 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2,
-    0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, 0xaed16a4a, 0xd9d65adc,
-    0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9,
-    0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693,
-    0x54de5729, 0x23d967bf, 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94,
-    0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
-};
-
-uint32_t utils_crc32(void *dataIn, uint32_t len)
-{
-    uint32_t crc=0;
-  uint8_t *data=(uint8_t *)dataIn;
-
-    crc = crc ^ 0xffffffff;
-
-    while (len--)
-        crc = crc32Tab[(crc ^ *data++) & 0xFF] ^ (crc >> 8);
-
-    return crc ^ 0xffffffff;
-}
-
-void utils_crc32_stream_init(struct crc32_stream_ctx *ctx)
-{
-  ctx->crc = 0xffffffff;
-}
-
-void utils_crc32_stream_feed(struct crc32_stream_ctx *ctx, uint8_t data)
-{
-    ctx->crc = crc32Tab[(ctx->crc ^ data) & 0xFF] ^ (ctx->crc >> 8);
-}
-
-void utils_crc32_stream_feed_block(struct crc32_stream_ctx *ctx, uint8_t *data, uint32_t len)
-{
-  while (len--)
-      ctx->crc = crc32Tab[(ctx->crc ^ *data++) & 0xFF] ^ (ctx->crc >> 8);
-}
-
-uint32_t utils_crc32_stream_results(struct crc32_stream_ctx *ctx)
-{
-  return ctx->crc ^ 0xffffffff;
-}
-
-#define POLY 0x8408
-uint16_t utils_crc16_ccitt(void *dataIn, uint32_t len)
-{
-    uint8_t *data_p=(uint8_t *)dataIn;
-    uint8_t i;
-    uint8_t data;
-    uint16_t crc;
-
-    crc = 0xFFFF;
-
-    if (len == 0)
-        return (~crc);
-
-    do {
-        for (i = 0, data = (unsigned int)0xff & *data_p++;
-            i < 8;
-            i++, data >>= 1) {
-        if ((crc & 0x0001) ^ (data & 0x0001))
-            crc = (crc >> 1) ^ POLY;
-        else
-            crc >>= 1;
-        }
-    } while (--len);
-
-    crc = ~crc;
-
-    data = crc;
-
-    return (crc);
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_dns.c b/bsp/bl808/m0/libraries/utils/src/utils_dns.c
deleted file mode 100644
index 0228adb662..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_dns.c
+++ /dev/null
@@ -1,55 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-
-int utils_dns_domain_get(uint8_t *records, uint8_t *buf, int *len)
-{
-    int i, pos_in, pos_out, size_buf;
-
-    size_buf = *len;
-
-    pos_in = 0;
-    pos_out = 0;
-    i = records[pos_in++];
-    while (i > 0 && size_buf > 0) {
-        buf[pos_out++] = records[pos_in++];
-        i--;
-        size_buf--;
-
-        if (0 == i && size_buf > 0) {
-            /*current record is empty*/
-            buf[pos_out++] = '.';
-            i = records[pos_in++];
-        }
-    }
-    *len = pos_out;
-
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_fec.c b/bsp/bl808/m0/libraries/utils/src/utils_fec.c
deleted file mode 100644
index cc2efa4999..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_fec.c
+++ /dev/null
@@ -1,880 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-#include "utils_log.h"
-#include "stdio.h"
-
-#include "utils_fec.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define MSG_CNT     3      /* message-length polynomials count */
-#define POLY_CNT    14     /* (FEC_ECC_LENGTH*2)-length polynomialc count */
-
-typedef struct {
-    uint8_t   _id;
-    uint8_t   _size;    /* Size of reserved memory for this polynomial */
-    uint16_t  _offset;  /* Offset in memory */
-    uint8_t*  _memory;  /* Pointer to pointer to memory */
-    uint8_t   length;
-} blpoly_t;
-
-typedef struct {
-    blpoly_t g_polynoms[MSG_CNT + POLY_CNT];
-    uint8_t g_stack_memory[MSG_CNT * FEC_MSG_LENGTH + POLY_CNT * FEC_ECC_LENGTH * 2];
-    uint8_t g_generator_cache[FEC_ECC_LENGTH + 1];
-    uint8_t g_generator_cached_flag;/* false */
-} fec_context_t;
-
-enum POLY_ID {
-    ID_MSG_IN = 0,
-    ID_MSG_OUT,
-    ID_GENERATOR,
-    ID_TPOLY1,
-    ID_TPOLY2,
-
-    ID_MSG_E,
-
-    ID_TPOLY3,
-    ID_TPOLY4,
-
-    ID_SYNDROMES,
-    ID_FORNEY,
-
-    ID_ERASURES_LOC,
-    ID_ERRORS_LOC,
-
-    ID_ERASURES,
-    ID_ERRORS,
-
-    ID_COEF_POS,
-    ID_ERR_EVAL
-};
-
-/* GF tables pre-calculated for 0x11d primitive polynomial */
-const uint8_t code_exp[512] = {
-    0x1, 0x2, 0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c,
-    0x98, 0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x3, 0x6, 0xc, 0x18, 0x30, 0x60, 0xc0, 0x9d,
-    0x27, 0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46,
-    0x8c, 0x5, 0xa, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f,
-    0xbe, 0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0xf, 0x1e, 0x3c, 0x78, 0xf0, 0xfd,
-    0xe7, 0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9,
-    0xaf, 0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0xd, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81,
-    0x1f, 0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85,
-    0x17, 0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8,
-    0x4d, 0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6,
-    0xd1, 0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3,
-    0xdb, 0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82,
-    0x19, 0x32, 0x64, 0xc8, 0x8d, 0x7, 0xe, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51,
-    0xa2, 0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x9, 0x12,
-    0x24, 0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0xb, 0x16, 0x2c,
-    0x58, 0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x1, 0x2,
-    0x4, 0x8, 0x10, 0x20, 0x40, 0x80, 0x1d, 0x3a, 0x74, 0xe8, 0xcd, 0x87, 0x13, 0x26, 0x4c, 0x98,
-    0x2d, 0x5a, 0xb4, 0x75, 0xea, 0xc9, 0x8f, 0x3, 0x6, 0xc, 0x18, 0x30, 0x60, 0xc0, 0x9d, 0x27,
-    0x4e, 0x9c, 0x25, 0x4a, 0x94, 0x35, 0x6a, 0xd4, 0xb5, 0x77, 0xee, 0xc1, 0x9f, 0x23, 0x46, 0x8c,
-    0x5, 0xa, 0x14, 0x28, 0x50, 0xa0, 0x5d, 0xba, 0x69, 0xd2, 0xb9, 0x6f, 0xde, 0xa1, 0x5f, 0xbe,
-    0x61, 0xc2, 0x99, 0x2f, 0x5e, 0xbc, 0x65, 0xca, 0x89, 0xf, 0x1e, 0x3c, 0x78, 0xf0, 0xfd, 0xe7,
-    0xd3, 0xbb, 0x6b, 0xd6, 0xb1, 0x7f, 0xfe, 0xe1, 0xdf, 0xa3, 0x5b, 0xb6, 0x71, 0xe2, 0xd9, 0xaf,
-    0x43, 0x86, 0x11, 0x22, 0x44, 0x88, 0xd, 0x1a, 0x34, 0x68, 0xd0, 0xbd, 0x67, 0xce, 0x81, 0x1f,
-    0x3e, 0x7c, 0xf8, 0xed, 0xc7, 0x93, 0x3b, 0x76, 0xec, 0xc5, 0x97, 0x33, 0x66, 0xcc, 0x85, 0x17,
-    0x2e, 0x5c, 0xb8, 0x6d, 0xda, 0xa9, 0x4f, 0x9e, 0x21, 0x42, 0x84, 0x15, 0x2a, 0x54, 0xa8, 0x4d,
-    0x9a, 0x29, 0x52, 0xa4, 0x55, 0xaa, 0x49, 0x92, 0x39, 0x72, 0xe4, 0xd5, 0xb7, 0x73, 0xe6, 0xd1,
-    0xbf, 0x63, 0xc6, 0x91, 0x3f, 0x7e, 0xfc, 0xe5, 0xd7, 0xb3, 0x7b, 0xf6, 0xf1, 0xff, 0xe3, 0xdb,
-    0xab, 0x4b, 0x96, 0x31, 0x62, 0xc4, 0x95, 0x37, 0x6e, 0xdc, 0xa5, 0x57, 0xae, 0x41, 0x82, 0x19,
-    0x32, 0x64, 0xc8, 0x8d, 0x7, 0xe, 0x1c, 0x38, 0x70, 0xe0, 0xdd, 0xa7, 0x53, 0xa6, 0x51, 0xa2,
-    0x59, 0xb2, 0x79, 0xf2, 0xf9, 0xef, 0xc3, 0x9b, 0x2b, 0x56, 0xac, 0x45, 0x8a, 0x9, 0x12, 0x24,
-    0x48, 0x90, 0x3d, 0x7a, 0xf4, 0xf5, 0xf7, 0xf3, 0xfb, 0xeb, 0xcb, 0x8b, 0xb, 0x16, 0x2c, 0x58,
-    0xb0, 0x7d, 0xfa, 0xe9, 0xcf, 0x83, 0x1b, 0x36, 0x6c, 0xd8, 0xad, 0x47, 0x8e, 0x1, 0x2
-};
-
-const uint8_t code_log[256] = {
-    0x0, 0x0, 0x1, 0x19, 0x2, 0x32, 0x1a, 0xc6, 0x3, 0xdf, 0x33, 0xee, 0x1b, 0x68, 0xc7, 0x4b, 0x4,
-    0x64, 0xe0, 0xe, 0x34, 0x8d, 0xef, 0x81, 0x1c, 0xc1, 0x69, 0xf8, 0xc8, 0x8, 0x4c, 0x71, 0x5,
-    0x8a, 0x65, 0x2f, 0xe1, 0x24, 0xf, 0x21, 0x35, 0x93, 0x8e, 0xda, 0xf0, 0x12, 0x82, 0x45, 0x1d,
-    0xb5, 0xc2, 0x7d, 0x6a, 0x27, 0xf9, 0xb9, 0xc9, 0x9a, 0x9, 0x78, 0x4d, 0xe4, 0x72, 0xa6, 0x6,
-    0xbf, 0x8b, 0x62, 0x66, 0xdd, 0x30, 0xfd, 0xe2, 0x98, 0x25, 0xb3, 0x10, 0x91, 0x22, 0x88, 0x36,
-    0xd0, 0x94, 0xce, 0x8f, 0x96, 0xdb, 0xbd, 0xf1, 0xd2, 0x13, 0x5c, 0x83, 0x38, 0x46, 0x40, 0x1e,
-    0x42, 0xb6, 0xa3, 0xc3, 0x48, 0x7e, 0x6e, 0x6b, 0x3a, 0x28, 0x54, 0xfa, 0x85, 0xba, 0x3d, 0xca,
-    0x5e, 0x9b, 0x9f, 0xa, 0x15, 0x79, 0x2b, 0x4e, 0xd4, 0xe5, 0xac, 0x73, 0xf3, 0xa7, 0x57, 0x7,
-    0x70, 0xc0, 0xf7, 0x8c, 0x80, 0x63, 0xd, 0x67, 0x4a, 0xde, 0xed, 0x31, 0xc5, 0xfe, 0x18, 0xe3,
-    0xa5, 0x99, 0x77, 0x26, 0xb8, 0xb4, 0x7c, 0x11, 0x44, 0x92, 0xd9, 0x23, 0x20, 0x89, 0x2e, 0x37,
-    0x3f, 0xd1, 0x5b, 0x95, 0xbc, 0xcf, 0xcd, 0x90, 0x87, 0x97, 0xb2, 0xdc, 0xfc, 0xbe, 0x61, 0xf2,
-    0x56, 0xd3, 0xab, 0x14, 0x2a, 0x5d, 0x9e, 0x84, 0x3c, 0x39, 0x53, 0x47, 0x6d, 0x41, 0xa2, 0x1f,
-    0x2d, 0x43, 0xd8, 0xb7, 0x7b, 0xa4, 0x76, 0xc4, 0x17, 0x49, 0xec, 0x7f, 0xc, 0x6f, 0xf6, 0x6c,
-    0xa1, 0x3b, 0x52, 0x29, 0x9d, 0x55, 0xaa, 0xfb, 0x60, 0x86, 0xb1, 0xbb, 0xcc, 0x3e, 0x5a, 0xcb,
-    0x59, 0x5f, 0xb0, 0x9c, 0xa9, 0xa0, 0x51, 0xb, 0xf5, 0x16, 0xeb, 0x7a, 0x75, 0x2c, 0xd7, 0x4f,
-    0xae, 0xd5, 0xe9, 0xe6, 0xe7, 0xad, 0xe8, 0x74, 0xd6, 0xf4, 0xea, 0xa8, 0x50, 0x58, 0xaf
-};
-
-void poly_init(blpoly_t *dev, uint8_t id, uint16_t offset, uint8_t size, uint8_t *memory_ptr)
-{
-    bl_assert(memory_ptr && dev);
-
-    dev->_id = id;
-    dev->_size = size;
-    dev->_offset = offset;
-    dev->_memory = memory_ptr;
-    dev->length = 0;
-}
-
-uint8_t *poly_ptr(blpoly_t *dev)
-{
-    bl_assert(dev);
-
-    return (dev->_memory + dev->_offset);
-}
-
-void poly_reset(blpoly_t *dev)
-{
-    bl_assert(dev->_memory && dev);
-
-    memset(poly_ptr(dev), 0, dev->_size);
-}
-
-void poly_set(blpoly_t *dev, uint8_t* src, uint8_t len, uint8_t offset)/* offset=0 */
-{
-    bl_assert(src && len <= dev->_size - offset);
-
-    memcpy(poly_ptr(dev)+offset, src, len * sizeof(uint8_t));
-
-    dev->length = len + offset;
-}
-
-uint8_t *poly_at(blpoly_t *dev, uint8_t i)
-{
-    uint8_t *pt;
-
-    bl_assert(dev);
-
-    pt = poly_ptr(dev);
-
-    return (pt + i);
-}
-
-uint8_t poly_get_size(blpoly_t *dev)
-{
-    bl_assert(dev);
-
-    return dev->_size;
-}
-
-uint8_t poly_get_id(blpoly_t *dev)
-{
-    bl_assert(dev);
-
-    return dev->_id;
-}
-
-void poly_copy(blpoly_t *dev, blpoly_t *src)
-{
-    bl_assert(dev && src);
-
-    dev->length = ((dev->length) > (src->length) ? (dev->length) : (src->length));
-    poly_set(dev, poly_ptr(src), dev->length, 0);
-}
-
-uint8_t poly_append(blpoly_t *dev, uint8_t num)
-{
-    uint8_t *pt;
-    bl_assert(dev->length + 1 < dev->_size);
-
-    pt = poly_ptr(dev);
-    pt[dev->length++] = num;
-
-    return 1;/* true */
-}
-
-/*****************************************************/
-uint8_t gf_add(uint8_t x, uint8_t y)
-{
-    return x + y;
-}
-
-uint8_t gf_sub(uint8_t x, uint8_t y)
-{
-    return x^y;
-}
-
-uint8_t gf_mul(uint16_t x, uint16_t y)
-{
-    if (x == 0 || y == 0) {
-        return 0;
-    }
-
-    return code_exp[code_log[x] + code_log[y]];
-}
-
-uint8_t gf_div(uint8_t x, uint8_t y)
-{
-    bl_assert(y != 0);
-
-    if (x == 0) {
-        return 0;
-    }
-    return code_exp[(code_log[x] + 255 - code_log[y]) % 255];
-}
-
-uint8_t gf_pow(uint8_t x, intmax_t power)
-{
-    intmax_t i = code_log[x];
-
-    i *= power;
-    i %= 255;
-
-    if (i < 0) {
-        i = i + 255;
-    }
-
-    return code_exp[i];
-}
-
-uint8_t gf_inverse(uint8_t x)
-{
-    return code_exp[255 - code_log[x]]; /* == div(1, x); */
-}
-
-/* POLYNOMIALS OPERATIONS */
-void poly_scale(blpoly_t *p, blpoly_t *newp, uint16_t x)
-{
-    uint16_t i;
-
-    newp->length = p->length;
-    for (i = 0; i < p->length; i++)
-    {
-        *poly_at(newp, i) = gf_mul(*poly_at(p, i), x);
-    }
-}
-
-void poly_add(blpoly_t *p, blpoly_t *q, blpoly_t *newp)
-{
-    uint8_t i;
-
-    newp->length = ((p->length) > (q->length) ? (p->length) : (q->length));
-    memset(poly_ptr(newp), 0, newp->length * sizeof(uint8_t));
-
-    for (i = 0; i < p->length; i++)
-    {
-        *poly_at(newp, i + newp->length - p->length) = *poly_at(p, i);
-    }
-
-    for (i = 0; i < q->length; i++)
-    {
-        *poly_at(newp, i + newp->length - q->length) ^= *poly_at(q, i);
-    }
-}
-
-void poly_mul(blpoly_t *p, blpoly_t *q, blpoly_t *newp)
-{
-    uint8_t i,j;
-
-    newp->length = p->length + q->length - 1;
-    memset(poly_ptr(newp), 0, newp->length * sizeof(uint8_t));
-    /* Compute the polynomial multiplication (just like the outer product of two vectors,
-     * we multiply each coefficients of p with all coefficients of q) */
-    for (j = 0; j < q->length; j++) {
-        for (i = 0; i < p->length; i++) {
-            *poly_at(newp, i+j) ^= gf_mul(*poly_at(p, i), *poly_at(q, j)); /* == r[i + j] = gf_add(r[i+j], gf_mul(p[i], q[j])) */
-        }
-    }
-}
-
-void poly_div(blpoly_t *p, blpoly_t *q, blpoly_t *newp)
-{
-    uint8_t coef;
-    unsigned long sep;
-    long i;
-
-    if (poly_ptr(p) != poly_ptr(newp)) {
-        memcpy(poly_ptr(newp), poly_ptr(p), p->length*sizeof(uint8_t));
-    }
-
-    newp->length = p->length;
-
-    for (i = 0; i < (p->length-(q->length-1)); i++) {
-        coef = *poly_at(newp, i);
-        if (coef != 0) {
-            for (uint8_t j = 1; j < q->length; j++) {
-                if (*poly_at(q, j) != 0) {
-                    *poly_at(newp, i+j) ^= gf_mul(*poly_at(q, j), coef);
-                }
-            }
-        }
-    }
-
-    sep = p->length-(q->length-1);
-    memmove(poly_ptr(newp), poly_ptr(newp)+sep, (newp->length-sep) * sizeof(uint8_t));
-    newp->length = newp->length-sep;
-}
-
-int8_t poly_eval(blpoly_t *p, uint16_t x)
-{
-    uint8_t y = *poly_at(p, 0);
-
-    for (uint8_t i = 1; i < p->length; i++)
-    {
-        y = gf_mul(y, x) ^ (*poly_at(p, i));
-    }
-    return y;
-}
-
-/*****************************************************/
-void generator_poly(fec_context_t *context)
-{
-    uint8_t i;
-    blpoly_t *gen = context->g_polynoms + ID_GENERATOR;
-    blpoly_t *mulp = context->g_polynoms + ID_TPOLY1;
-    blpoly_t *temp = context->g_polynoms + ID_TPOLY2;
-
-    *poly_at(gen, 0) = 1;
-    gen->length = 1;
-
-    mulp->length = 2;
-
-    for (i = 0; i < FEC_ECC_LENGTH; i++)
-    {
-        *poly_at(mulp, 0) = 1;
-        *poly_at(mulp, 1) = gf_pow(2, i);
-
-        poly_mul(gen, mulp, temp);
-        poly_copy(gen, temp);
-    }
-}
-
-void calc_syndromes(fec_context_t *context, blpoly_t *msg)
-{
-    uint8_t i;
-    blpoly_t *synd = &context->g_polynoms[ID_SYNDROMES];
-
-    synd->length = FEC_ECC_LENGTH + 1;
-    *poly_at(synd, 0) = 0;
-
-    for (i = 1; i < FEC_ECC_LENGTH + 1; i++)
-    {
-        *poly_at(synd, i) = poly_eval(msg, gf_pow(2, i - 1));
-    }
-}
-
-void find_errata_locator(fec_context_t *context, blpoly_t *epos)
-{
-    blpoly_t *errata_loc = &context->g_polynoms[ID_ERASURES_LOC];
-    blpoly_t *mulp = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *addp = &context->g_polynoms[ID_TPOLY2];
-    blpoly_t *apol = &context->g_polynoms[ID_TPOLY3];
-    blpoly_t *temp = &context->g_polynoms[ID_TPOLY4];
-
-    errata_loc->length = 1;
-    *poly_at(errata_loc, 0) = 1;
-
-    mulp->length = 1;
-    addp->length = 2;
-
-    for (uint8_t i = 0; i < epos->length; i++)
-    {
-        *poly_at(mulp, 0) = 1;
-        *poly_at(addp, 0) = gf_pow(2, *poly_at(epos           , i));
-        *poly_at(addp, 1) = 0;
-
-        poly_add(mulp, addp, apol);
-        poly_mul(errata_loc, apol, temp);
-
-        poly_copy(errata_loc, temp);
-    }
-}
-
-void find_error_evaluator(fec_context_t *context, blpoly_t *synd, blpoly_t *errata_loc, blpoly_t *dst, uint8_t ecclen)
-{
-    blpoly_t *mulp = &context->g_polynoms[ID_TPOLY1];
-    poly_mul(synd, errata_loc, mulp);
-
-    blpoly_t *divisor = &context->g_polynoms[ID_TPOLY2];
-    divisor->length = ecclen + 2;
-
-    poly_reset(divisor);
-    *poly_at(divisor, 0) = 1;
-
-    poly_div(mulp, divisor, dst);
-}
-
-void correct_errata(fec_context_t *context, blpoly_t *synd, blpoly_t *err_pos, blpoly_t *msg_in)
-{
-    uint8_t i;
-    int8_t s_i;
-    int16_t l;
-    uint8_t Xi_inv;
-    uint8_t err_loc_prime;
-    uint8_t y;
-    uint8_t j;
-
-    blpoly_t *c_pos     = &context->g_polynoms[ID_COEF_POS];
-    blpoly_t *corrected = &context->g_polynoms[ID_MSG_OUT];
-    blpoly_t *errata_loc = &context->g_polynoms[ID_ERASURES_LOC];
-    blpoly_t *rsynd = &context->g_polynoms[ID_TPOLY3];
-    blpoly_t *re_eval = &context->g_polynoms[ID_TPOLY4];
-    blpoly_t *e_eval = &context->g_polynoms[ID_ERR_EVAL];
-    blpoly_t *X = &context->g_polynoms[ID_TPOLY1]; /* this will store errors positions */
-    blpoly_t *E = &context->g_polynoms[ID_MSG_E];
-    blpoly_t *err_loc_prime_temp = &context->g_polynoms[ID_TPOLY2];
-
-    c_pos->length = err_pos->length;
-
-    for (i = 0; i < err_pos->length; i++)
-        *poly_at(c_pos, i) = msg_in->length - 1 - *poly_at(err_pos, i);
-
-    /* uses t_poly 1, 2, 3, 4 */
-    find_errata_locator(context, c_pos);
-
-
-    /* reversing syndromes */
-    rsynd->length = synd->length;
-
-    for (s_i = synd->length-1, j = 0; s_i >= 0; s_i--, j++)
-    {
-        *poly_at(rsynd, j) = *poly_at(synd, s_i);
-    }
-
-    /* getting reversed error evaluator polynomial */
-
-    /* uses T_POLY 1, 2 */
-    find_error_evaluator(context, rsynd, errata_loc, re_eval, errata_loc->length-1);
-
-    /* reversing it back */
-    e_eval->length = re_eval->length;
-    for (s_i = re_eval->length-1, j = 0; s_i >= 0; s_i--, j++)
-    {
-        *poly_at(e_eval, j) = *poly_at(re_eval, s_i);
-    }
-
-
-    X->length = 0;
-
-    for (i = 0; i < c_pos->length; i++)
-    {
-        l = 255 - *poly_at(c_pos, i);
-        poly_append(X, gf_pow(2, -l));
-    }
-
-    /* Magnitude polynomial
-        Shit just got real */
-    poly_reset(E);
-    E->length = msg_in->length;
-
-
-    for (i = 0; i < X->length; i++) {
-        Xi_inv = gf_inverse(*poly_at(X, i));
-
-        err_loc_prime_temp->length = 0;
-        for (j = 0; j < X->length; j++) {
-            if (j != i) {
-                poly_append(err_loc_prime_temp, gf_sub(1, gf_mul(Xi_inv, *poly_at(X, j))));
-            }
-        }
-
-        err_loc_prime = 1;
-        for (j = 0; j < err_loc_prime_temp->length; j++) {
-            err_loc_prime = gf_mul(err_loc_prime, *poly_at(err_loc_prime_temp, j));
-        }
-
-        y = poly_eval(re_eval, Xi_inv);
-        y = gf_mul(gf_pow(*poly_at(X, i), 1), y);
-
-        *poly_at(E, *poly_at(err_pos, i)) = gf_div(y, err_loc_prime);
-    }
-
-    poly_add(msg_in, E, corrected);
-}
-
-uint8_t find_error_locator(fec_context_t *context, blpoly_t *synd, blpoly_t *erase_loc, unsigned long erase_count)
-{
-    uint8_t i;
-    uint8_t synd_shift = 0;
-    uint8_t K = 0;
-    uint8_t delta = 0;
-    uint8_t index;
-    uint8_t j;
-    uint32_t shift = 0;
-    uint32_t errs;
-
-    blpoly_t *error_loc = &context->g_polynoms[ID_ERRORS_LOC];
-    blpoly_t *err_loc   = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *old_loc   = &context->g_polynoms[ID_TPOLY2];
-    blpoly_t *temp      = &context->g_polynoms[ID_TPOLY3];
-    blpoly_t *temp2     = &context->g_polynoms[ID_TPOLY4];
-
-    if (erase_loc != NULL) {
-        poly_copy(err_loc, erase_loc);
-        poly_copy(old_loc, erase_loc);
-    } else {
-        err_loc->length = 1;
-        old_loc->length = 1;
-        *poly_at(err_loc, 0)  = 1;
-        *poly_at(old_loc, 0)  = 1;
-    }
-
-
-    if (synd->length > FEC_ECC_LENGTH) {
-        synd_shift = synd->length - FEC_ECC_LENGTH;
-    }
-
-    for (i = 0; i < FEC_ECC_LENGTH - erase_count; i++)
-    {
-        if (erase_loc != NULL) {
-            K = erase_count + i + synd_shift;
-        } else {
-            K = i + synd_shift;
-        }
-
-        delta = *poly_at(synd, K);
-        for (j = 1; j < err_loc->length; j++) {
-            index = err_loc->length - j - 1;
-            delta ^= gf_mul(*poly_at(err_loc, index), *poly_at(synd, K-j));
-        }
-
-        poly_append(old_loc, 0);
-
-        if (delta != 0) {
-            if (old_loc->length > err_loc->length) {
-                poly_scale(old_loc, temp, delta);
-                poly_scale(err_loc, old_loc, gf_inverse(delta));
-                poly_copy(err_loc, temp);
-            }
-            poly_scale(old_loc, temp, delta);
-            poly_add(err_loc, temp, temp2);
-            poly_copy(err_loc, temp2);
-        }
-    }
-
-    while(err_loc->length && *poly_at(err_loc, shift) == 0) shift++;
-
-    errs = err_loc->length - shift - 1;
-    if (((errs - erase_count) * 2 + erase_count) > FEC_ECC_LENGTH) {
-        return 0;/* false */ /* Error count is greater then we can fix! */
-    }
-
-    memcpy(poly_ptr(error_loc), poly_ptr(err_loc) + shift, (err_loc->length - shift) * sizeof(uint8_t));
-    error_loc->length = (err_loc->length - shift);
-    return 1;/* true */
-}
-
-uint8_t find_errors(fec_context_t *context, blpoly_t *error_loc, unsigned long msg_in_size)
-{
-    uint8_t i;
-
-    blpoly_t *err = &context->g_polynoms[ID_ERRORS];
-    uint8_t errs = error_loc->length - 1;
-
-    err->length = 0;
-
-    for (i = 0; i < msg_in_size; i++)
-    {
-        if (poly_eval(error_loc, gf_pow(2, i)) == 0)
-        {
-            poly_append(err, msg_in_size - 1 - i);
-        }
-    }
-
-    /* Sanity check:
-        * the number of err/errata positions found
-        * should be exactly the same as the length of the errata locator polynomial */
-    if (err->length != errs) {
-        /* couldn't find error locations */
-        return 0;/* false */
-    }
-
-    return 1;/* true */
-}
-
-void calc_forney_syndromes(fec_context_t *context, blpoly_t *synd, blpoly_t *erasures_pos, unsigned long msg_in_size)
-{
-    uint8_t i;
-    uint8_t x;
-    uint8_t j;
-
-    blpoly_t *erase_pos_reversed = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *forney_synd = &context->g_polynoms[ID_FORNEY];
-
-    erase_pos_reversed->length = 0;
-
-    for (i = 0; i < erasures_pos->length; i++)
-    {
-        poly_append(erase_pos_reversed, msg_in_size - 1 - *poly_at(erasures_pos, i));
-    }
-
-    poly_reset(forney_synd);
-    poly_set(forney_synd, poly_ptr(synd)+1, synd->length-1, 0);
-
-    for (i = 0; i < erasures_pos->length; i++)
-    {
-        x = gf_pow(2, *poly_at(erase_pos_reversed, i));
-        for (j = 0; j < forney_synd->length - 1; j++)
-        {
-            *poly_at(forney_synd, j) = gf_mul(*poly_at(forney_synd, j), x) ^ *poly_at(forney_synd, j+1);
-        }
-    }
-}
-
-void reedsolomon_init(void *context)
-{
-    fec_context_t *p = (fec_context_t *)context;
-    uint16_t offset = 0;
-    uint8_t i;
-    uint8_t enc_len = FEC_MSG_LENGTH + FEC_ECC_LENGTH;
-    uint8_t poly_len = FEC_ECC_LENGTH * 2;
-
-    bl_assert(p);
-
-    log_info("reedsolomon_init.\r\n");
-
-    poly_init(&p->g_polynoms[0], ID_MSG_IN, offset, enc_len, p->g_stack_memory);
-    offset += enc_len;
-
-    poly_init(&p->g_polynoms[1], ID_MSG_OUT, offset, enc_len, p->g_stack_memory);
-    offset += enc_len;
-
-    for (i = ID_GENERATOR; i < ID_MSG_E; i++)
-    {
-        poly_init(&p->g_polynoms[i], i, offset, poly_len, p->g_stack_memory);
-        offset += poly_len;
-    }
-
-    poly_init(&p->g_polynoms[5], ID_MSG_E, offset, enc_len, p->g_stack_memory);
-    offset += enc_len;
-
-    for (i = ID_TPOLY3; i < ID_ERR_EVAL+2; i++)
-    {
-        poly_init(&p->g_polynoms[i], i, offset, poly_len, p->g_stack_memory);
-        offset += poly_len;
-    }
-}
-
-void encode_block(fec_context_t *context, void *src, void *dst)
-{
-    /* Generator cache, it dosn't change for one template parameters */
-
-    uint8_t coef = 0; /* cache */
-    uint8_t i;
-    uint32_t j;
-
-    uint8_t* src_ptr = (uint8_t*) src;
-    uint8_t* dst_ptr = (uint8_t*) dst;
-
-    blpoly_t *msg_in  = &context->g_polynoms[ID_MSG_IN];
-    blpoly_t *msg_out = &context->g_polynoms[ID_MSG_OUT];
-    blpoly_t *gen     = &context->g_polynoms[ID_GENERATOR];
-
-    bl_assert(FEC_MSG_LENGTH + FEC_ECC_LENGTH < 256);
-
-    poly_reset(msg_in);
-    poly_reset(msg_out);
-
-    if (context->g_generator_cached_flag) {
-        poly_set(gen, context->g_generator_cache, (FEC_ECC_LENGTH + 1), 0);
-    } else {
-        generator_poly(context);
-        memcpy(context->g_generator_cache, poly_ptr(gen), gen->length);
-        context->g_generator_cached_flag = 1;/* true */
-    }
-
-    /* Copying input message to internal polynomial */
-    poly_set(msg_in, src_ptr, FEC_MSG_LENGTH, 0);
-    poly_set(msg_out, src_ptr, FEC_MSG_LENGTH, 0);
-    msg_out->length = msg_in->length + FEC_ECC_LENGTH;
-
-    /* Here all the magic happens */
-
-    for (i = 0; i < FEC_MSG_LENGTH; i++) {
-        coef = *poly_at(msg_out, i);
-        if (coef != 0) {
-            for (j = 1; j < gen->length; j++) {
-                *poly_at(msg_out, i+j) ^= gf_mul(*poly_at(gen, j), coef);
-            }
-        }
-    }
-
-    /* Copying ECC to the output buffer */
-    memcpy(dst_ptr, poly_ptr(msg_out)+FEC_MSG_LENGTH, FEC_ECC_LENGTH * sizeof(uint8_t));
-
-}
-
-void reedsolomon_encode(void *context, void* src, void* dst)
-{
-    fec_context_t *p = (fec_context_t *)context;
-    uint8_t* dst_ptr = (uint8_t*) dst;
-
-    /* Copying message to the output buffer */
-    memcpy(dst_ptr, src, FEC_MSG_LENGTH * sizeof(uint8_t));
-
-    /* Calling EncodeBlock to write ecc to out[ut buffer */
-    encode_block(p, src, dst_ptr+FEC_MSG_LENGTH);
-}
-
-char decode_block(fec_context_t *context, void* src, const void* ecc, void* dst, uint8_t* erase_pos, unsigned long erase_count)
-{
-    uint8_t i, j;
-    int8_t s_i;
-    bl_assert(FEC_MSG_LENGTH + FEC_ECC_LENGTH < 256);
-
-    uint8_t *src_ptr = (uint8_t*) src;
-    uint8_t *ecc_ptr = (uint8_t*) ecc;
-    uint8_t *dst_ptr = (uint8_t*) dst;
-
-    uint8_t src_len = FEC_MSG_LENGTH + FEC_ECC_LENGTH;
-    uint8_t dst_len = FEC_MSG_LENGTH;
-
-    uint8_t ok;
-
-    blpoly_t *msg_in  = &context->g_polynoms[ID_MSG_IN];
-    blpoly_t *msg_out = &context->g_polynoms[ID_MSG_OUT];
-    blpoly_t *epos    = &context->g_polynoms[ID_ERASURES];
-    blpoly_t *synd   = &context->g_polynoms[ID_SYNDROMES];
-    blpoly_t *eloc   = &context->g_polynoms[ID_ERRORS_LOC];
-    blpoly_t *reloc  = &context->g_polynoms[ID_TPOLY1];
-    blpoly_t *err    = &context->g_polynoms[ID_ERRORS];
-    blpoly_t *forney = &context->g_polynoms[ID_FORNEY];
-
-    uint8_t has_errors;
-
-    /* Copying message to polynomials memory */
-    poly_set(msg_in, src_ptr, FEC_MSG_LENGTH, 0);
-    poly_set(msg_in, ecc_ptr, FEC_ECC_LENGTH, FEC_MSG_LENGTH);
-    poly_copy(msg_out, msg_in);
-
-    /* Copying known errors to polynomial */
-    if (erase_pos == NULL) {
-        epos->length = 0;
-    } else {
-        poly_set(epos, erase_pos, (uint8_t)erase_count, 0);
-        for (i = 0; i < epos->length; i++){
-            *poly_at(msg_in, *poly_at(epos, i)) = 0;
-        }
-    }
-
-    /* Too many errors */
-    if (epos->length > FEC_ECC_LENGTH) return 1;
-
-
-    /* Calculating syndrome */
-    calc_syndromes(context, msg_in);
-
-    /* Checking for errors */
-    has_errors = 0;/* false */
-    for (i = 0; i < synd->length; i++) {
-        if (*poly_at(synd, i) != 0) {
-            has_errors = 1;/* true */
-            break;
-        }
-    }
-
-    /* Going to exit if no errors */
-    if (!has_errors) {
-        goto return_corrected_msg;
-    }
-
-    calc_forney_syndromes(context, synd, epos, src_len);
-    find_error_locator(context, forney, NULL, epos->length);
-
-    /*
-        Reversing syndrome
-        TODO optimize through special Poly flag
-    */
-    reloc->length = eloc->length;
-
-    for (s_i = eloc->length-1, j = 0; s_i >= 0; s_i--, j++) {
-        *poly_at(reloc, j) = *poly_at(eloc, s_i);
-    }
-
-    /* Fing errors */
-    ok = find_errors(context, reloc, src_len);
-    if (!ok) {
-        return 1;
-    }
-
-    /* Error happened while finding errors (so helpfull :D) */
-    if (err->length == 0) {
-        return 1;
-    }
-
-    /* Adding found errors with known */
-    for (uint8_t i = 0; i < err->length; i++) {
-        poly_append(epos, *poly_at(err, i));
-    }
-
-    /* Correcting errors */
-    correct_errata(context, synd, epos, msg_in);
-
-return_corrected_msg:
-    /* Wrighting corrected message to output buffer */
-    msg_out->length = dst_len;
-    memcpy(dst_ptr, poly_ptr(msg_out), msg_out->length * sizeof(uint8_t));
-    return 0;
-}
-
-/*
-    old:
-        reedsolomon_decode(void *context, void* src, void* dst, uint8_t* erase_pos, uint32_t erase_count)
-        return decode_block(p, src, ecc_ptr, dst, erase_pos, erase_count);
-*/
-char reedsolomon_decode(void *context, void* src, void* dst)
-{
-    fec_context_t *p = (fec_context_t *)context;
-    uint8_t *src_ptr = (uint8_t*) src;
-    uint8_t *ecc_ptr = src_ptr + FEC_MSG_LENGTH;
-
-    return decode_block(p, src, ecc_ptr, dst, 0, 0);
-}
-
-/* which compiles with no warnings, and produces no code. */
-#define BUILD_BUG_ON(condition) ((void)sizeof(char [1 - 2 * !!(condition)]))
-int reedsolomon_getmemsize(void)
-{
-    /*
-        which compiles with no warnings, and produces no code.
-        err ? too waste mem ? pleas set fec_t.dummy size to (sizeof(fec_context_t)/sizeof(int) + 1)!
-    */
-    BUILD_BUG_ON((sizeof(fec_t) - sizeof(fec_context_t) > 512) ||
-                (sizeof(fec_t) - sizeof(fec_context_t) < 0));
-
-    log_info("sizeof(fec_t) = %d   sizeof(fec_context_t) = %d\r\n", sizeof(fec_t), sizeof(fec_context_t));
-    return (int)sizeof(fec_context_t);
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-
-
-
-
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_getopt.c b/bsp/bl808/m0/libraries/utils/src/utils_getopt.c
deleted file mode 100644
index 7e91ebc703..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_getopt.c
+++ /dev/null
@@ -1,142 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-/*
- * This file is derived from musl v1.2.0.
- * Modifications are applied.
- * Copyright (C) Bouffalo Lab 2016-2020
- */
-
-/*
- * Copyright © 2005-2020 Rich Felker, et al.
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * "Software"), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY
- * CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
- * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
- * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
- */
-
-int utils_getopt_init(getopt_env_t *env, int opterr)
-{
-    if (!env) {
-        return -1;
-    }
-    env->optarg = NULL;
-    env->optind = 1;
-    env->opterr = opterr;
-    env->optopt = 0;
-    env->__optpos = 0;
-    return 0;
-}
-
-#define NEWLINE "\r\n"
-
-int utils_getopt(getopt_env_t *env, int argc, char * const argv[], const char *optstring)
-{
-    int i;
-    char c, d;
-    char *optchar;
-
-    if (!env) {
-        return -1;
-    }
-
-    if (env->optind >= argc || !argv[env->optind])
-        return -1;
-
-    if (argv[env->optind][0] != '-') {
-        if (optstring[0] == '-') {
-            env->optarg = argv[env->optind++];
-            return 1;
-        }
-        return -1;
-    }
-
-    if (!argv[env->optind][1])
-        return -1;
-
-    if (argv[env->optind][1] == '-' && !argv[env->optind][2])
-        return env->optind++, -1;
-
-    if (!env->__optpos) env->__optpos++;
-    c = argv[env->optind][env->__optpos];
-    optchar = argv[env->optind] + env->__optpos;
-    env->__optpos += !!c;
-
-    if (!argv[env->optind][env->__optpos]) {
-        env->optind++;
-        env->__optpos = 0;
-    }
-
-    if (optstring[0] == '-' || optstring[0] == '+')
-        optstring++;
-
-    i = 0;
-    do d = optstring[i++]; while (d && d != c);
-
-    if (d != c || c == ':') {
-        env->optopt = c;
-        if (optstring[0] != ':' && env->opterr)
-            printf("%s: unrecognized option: %c"NEWLINE, argv[0], *optchar);
-        return '?';
-    }
-    if (optstring[i] == ':') {
-        env->optarg = 0;
-        if (optstring[i+1] != ':' || env->__optpos) {
-            env->optarg = argv[env->optind++] + env->__optpos;
-            env->__optpos = 0;
-        }
-        if (env->optind > argc) {
-            env->optopt = c;
-            if (optstring[0] == ':') return ':';
-            if (env->opterr) {
-                printf("%s: option requires an argument: %c"NEWLINE, argv[0], *optchar);
-            }
-            return '?';
-        }
-    }
-    return c;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hex.c b/bsp/bl808/m0/libraries/utils/src/utils_hex.c
deleted file mode 100644
index e403f9e9a2..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hex.c
+++ /dev/null
@@ -1,104 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-const char hex_asc[] = "0123456789abcdef";
-const char hex_asc_upper[] = "0123456789ABCDEF";
-#define hex_asc_lo(x)   hex_asc_upper[((x) & 0x0f)]
-#define hex_asc_hi(x)   hex_asc_upper[((x) & 0xf0) >> 4]
-
-static inline char *hex_byte_pack(char *buf, uint8_t byte)
-{
-    *buf++ = hex_asc_hi(byte);
-    *buf++ = hex_asc_lo(byte);
-    return buf;
-}
-
-static int char2hex(char c, uint8_t *x)
-{
-    if (c >= '0' && c <= '9') {
-        *x = c - '0';
-    } else if (c >= 'a' && c <= 'f') {
-        *x = c - 'a' + 10;
-    } else if (c >= 'A' && c <= 'F') {
-        *x = c - 'A' + 10;
-    } else {
-        return -1;
-    }
-
-    return 0;
-}
-
-char *utils_bin2hex(char *dst, const void *src, size_t count)
-{
-    const unsigned char *_src = src;
-
-    while (count--) {
-        dst = hex_byte_pack(dst, *_src++);
-    }
-
-    return dst;
-}
-
-size_t utils_hex2bin(const char *hex, size_t hexlen, uint8_t *buf, size_t buflen)
-{
-    uint8_t dec;
-
-    if (buflen < hexlen / 2 + hexlen % 2) {
-        return 0;
-    }
-
-    /* if hexlen is uneven, insert leading zero nibble */
-    if (hexlen % 2) {
-        if (char2hex(hex[0], &dec) < 0) {
-            return 0;
-        }
-        buf[0] = dec;
-        hex++;
-        buf++;
-    }
-
-    /* regular hex conversion */
-    for (size_t i = 0; i < hexlen / 2; i++) {
-        if (char2hex(hex[2 * i], &dec) < 0) {
-            return 0;
-        }
-        buf[i] = dec << 4;
-
-        if (char2hex(hex[2 * i + 1], &dec) < 0) {
-            return 0;
-        }
-        buf[i] += dec;
-    }
-
-    return hexlen / 2 + hexlen % 2;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c b/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c
deleted file mode 100644
index 0320fbe04b..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hexdump.c
+++ /dev/null
@@ -1,77 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-#include 
-
-#ifndef HEXDUMP_COLS
-#define HEXDUMP_COLS 16
-#endif
-//FIXME fix putchar
-extern int bl_putchar(int c);
-
-void utils_hexdump(void *mem, unsigned int len)
-{
-    unsigned int i, j;
-
-    for (i = 0; i < len + ((len % HEXDUMP_COLS) ? (HEXDUMP_COLS - len % HEXDUMP_COLS) : 0); i++) {
-        /* print offset */
-        if (i % HEXDUMP_COLS == 0) {
-            printf("0x%06x: ", i);
-        }
-
-        /* print hex data */
-        if (i < len) {
-            printf("%02x ", 0xFF & ((char*)mem)[i]);
-        } else {
-            /* end of block, just aligning for ASCII dump */
-            printf("   ");
-        }
-
-        /* print ASCII dump */
-        if (i % HEXDUMP_COLS == (HEXDUMP_COLS - 1)) {
-            for (j = i - (HEXDUMP_COLS - 1); j <= i; j++) {
-                if (j >= len) {
-                    /* end of block, not really printing */
-                    bl_putchar(' ');
-                } else if(isprint((int)((char*)mem)[j])) {
-                    /* printable char */
-                    bl_putchar(0xFF & ((char*)mem)[j]);
-                } else {
-                    /* other char */
-                    bl_putchar('.');
-                }
-            }
-            puts("\r\n");
-        }
-    }
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hmac.c b/bsp/bl808/m0/libraries/utils/src/utils_hmac.c
deleted file mode 100644
index ce763397aa..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hmac.c
+++ /dev/null
@@ -1,239 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include "iotx_utils_internal.h"
-#include "utils_md5.h"
-#include "utils_sha1.h"
-#include "utils_sha256.h"
-#include "utils_hmac.h"
-#include "utils_base64.h"
-
-#ifdef UTILS_MD5
-void utils_hmac_md5(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_md5_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[MD5_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner MD5 */
-    utils_md5_init(&context);                                      /* init context for 1st pass */
-    utils_md5_starts(&context);                                    /* setup context for 1st pass */
-    utils_md5_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_md5_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_md5_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer MD5 */
-    utils_md5_init(&context);                              /* init context for 2nd pass */
-    utils_md5_starts(&context);                            /* setup context for 2nd pass */
-    utils_md5_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_md5_update(&context, out, MD5_DIGEST_SIZE);      /* then results of 1st hash */
-    utils_md5_finish(&context, out);                       /* finish up 2nd pass */
-
-    for (i = 0; i < MD5_DIGEST_SIZE; ++i) {
-        digest[i * 2] = utils_hb2hex(out[i] >> 4);
-        digest[i * 2 + 1] = utils_hb2hex(out[i]);
-    }
-}
-#endif  /* #ifdef UTILS_MD5 */
-
-#ifdef UTILS_SHA256
-void utils_hmac_sha256(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_sha256_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[SHA256_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner SHA */
-    utils_sha256_init(&context);                                      /* init context for 1st pass */
-    utils_sha256_starts(&context);                                    /* setup context for 1st pass */
-    utils_sha256_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_sha256_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_sha256_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer SHA */
-    utils_sha256_init(&context);                              /* init context for 2nd pass */
-    utils_sha256_starts(&context);                            /* setup context for 2nd pass */
-    utils_sha256_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_sha256_update(&context, out, SHA256_DIGEST_SIZE);     /* then results of 1st hash */
-    utils_sha256_finish(&context, out);                       /* finish up 2nd pass */
-
-    for (i = 0; i < SHA256_DIGEST_SIZE; ++i) {
-        digest[i * 2] = utils_hb2hex(out[i] >> 4);
-        digest[i * 2 + 1] = utils_hb2hex(out[i]);
-    }
-}
-#endif /* #ifdef UTILS_SHA256 */
-
-#ifdef UTILS_SHA1
-void utils_hmac_sha1(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_sha1_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[SHA1_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner SHA */
-    utils_sha1_init(&context);                                      /* init context for 1st pass */
-    utils_sha1_starts(&context);                                    /* setup context for 1st pass */
-    utils_sha1_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_sha1_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_sha1_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer SHA */
-    utils_sha1_init(&context);                              /* init context for 2nd pass */
-    utils_sha1_starts(&context);                            /* setup context for 2nd pass */
-    utils_sha1_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_sha1_update(&context, out, SHA1_DIGEST_SIZE);     /* then results of 1st hash */
-    utils_sha1_finish(&context, out);                       /* finish up 2nd pass */
-
-    for (i = 0; i < SHA1_DIGEST_SIZE; ++i) {
-        digest[i * 2] = utils_hb2hex(out[i] >> 4);
-        digest[i * 2 + 1] = utils_hb2hex(out[i]);
-    }
-}
-
-void utils_hmac_sha1_hex(const char *msg, int msg_len, char *digest, const char *key, int key_len)
-{
-    if ((NULL == msg) || (NULL == digest) || (NULL == key)) {
-        utils_err("parameter is Null,failed!");
-        return;
-    }
-
-    if (key_len > KEY_IOPAD_SIZE) {
-        utils_err("key_len > size(%d) of array", KEY_IOPAD_SIZE);
-        return;
-    }
-
-    iot_sha1_context context;
-    unsigned char k_ipad[KEY_IOPAD_SIZE];    /* inner padding - key XORd with ipad  */
-    unsigned char k_opad[KEY_IOPAD_SIZE];    /* outer padding - key XORd with opad */
-    unsigned char out[SHA1_DIGEST_SIZE];
-    int i;
-
-    /* start out by storing key in pads */
-    memset(k_ipad, 0, sizeof(k_ipad));
-    memset(k_opad, 0, sizeof(k_opad));
-    memcpy(k_ipad, key, key_len);
-    memcpy(k_opad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < KEY_IOPAD_SIZE; i++) {
-        k_ipad[i] ^= 0x36;
-        k_opad[i] ^= 0x5c;
-    }
-
-    /* perform inner SHA */
-    utils_sha1_init(&context);                                      /* init context for 1st pass */
-    utils_sha1_starts(&context);                                    /* setup context for 1st pass */
-    utils_sha1_update(&context, k_ipad, KEY_IOPAD_SIZE);            /* start with inner pad */
-    utils_sha1_update(&context, (unsigned char *) msg, msg_len);    /* then text of datagram */
-    utils_sha1_finish(&context, out);                               /* finish up 1st pass */
-
-    /* perform outer SHA */
-    utils_sha1_init(&context);                              /* init context for 2nd pass */
-    utils_sha1_starts(&context);                            /* setup context for 2nd pass */
-    utils_sha1_update(&context, k_opad, KEY_IOPAD_SIZE);    /* start with outer pad */
-    utils_sha1_update(&context, out, SHA1_DIGEST_SIZE);     /* then results of 1st hash */
-    utils_sha1_finish(&context, out);                       /* finish up 2nd pass */
-    memcpy(digest, out, SHA1_DIGEST_SIZE);
-}
-#endif  /* #ifdef UTILS_SHA1 */
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c b/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c
deleted file mode 100644
index 4e24d6485a..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_hmac_sha1_fast.c
+++ /dev/null
@@ -1,113 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-#include 
-#include 
-
-
-void utils_hmac_sha1_fast(unsigned char ** ppText,
-                    int * pTextLen,
-                    int textNum,
-                    unsigned char *key,
-                    int key_len,
-                    unsigned char *output,
-                    int outputLen)
-{
-    uint64_t pBuf[(64 + 20) / 8 + 1]; /*BIG stack*/
-    bl_sha_ctx_t sha_ctx;
-    unsigned char *k_pad; /* padding - key XORd with i/opad */
-    unsigned char *digest;
-    int i;
-
-    /* k_pad start at a UINT32 boundary */
-    k_pad = (unsigned char *)pBuf;
-    digest = k_pad + 64;
-
-    /* if key is longer than 64 bytes reset it to key=SHA1(key) */
-    if (key_len > 64)
-    {
-        bl_sha_init(&sha_ctx, BL_SHA1);
-        bl_sha_update(&sha_ctx, key, key_len);
-        bl_sha_finish(&sha_ctx, key);
-
-        key_len = 20;
-    }
-
-    /*
-     * the HMAC_SHA1 transform looks like:
-     *
-     * SHA1(K XOR opad, SHA1(K XOR ipad, text))
-     *
-     * where K is an n byte key
-     * ipad is the byte 0x36 repeated 64 times
-     * opad is the byte 0x5c repeated 64 times
-     * and text is the data being protected
-     */
-
-    /* perform inner SHA1*/
-    /* start out by storing key in pads */
-    memset(k_pad, 0, 64);
-    memcpy(k_pad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < 8; i++)
-    {
-        ((uint64_t *)k_pad)[i] ^= 0x3636363636363636;
-    }
-
-    bl_sha_init(&sha_ctx, BL_SHA1); /* init context for 1st pass */
-    bl_sha_update(&sha_ctx, k_pad, 64); /* start with inner pad */
-    for (i = 0; i < textNum; i++)
-    {
-        /* then text of datagram */
-        bl_sha_update(&sha_ctx, ppText[i], pTextLen[i]);
-    }
-
-    bl_sha_finish(&sha_ctx, digest); /* finish up 1st pass */
-
-    /* perform outer SHA1 */
-    /* start out by storing key in pads */
-    memset(k_pad, 0, 64);
-    memcpy(k_pad, key, key_len);
-
-    /* XOR key with ipad and opad values */
-    for (i = 0; i < 8; i++)
-    {
-        ((uint64_t *)k_pad)[i] ^= 0x5c5c5c5c5c5c5c5c;
-    }
-
-    bl_sha_init(&sha_ctx, BL_SHA1); /* init context for 2nd pass */
-    bl_sha_update(&sha_ctx, k_pad, 64); /* start with outer pad */
-    bl_sha_update(&sha_ctx, digest, 20); /* then results of 1st hash */
-    bl_sha_finish(&sha_ctx, digest); /* finish up 2nd pass */
-    memcpy(output, digest, outputLen);
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_list.c b/bsp/bl808/m0/libraries/utils/src/utils_list.c
deleted file mode 100644
index 59c6d3a0a2..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_list.c
+++ /dev/null
@@ -1,365 +0,0 @@
-
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-#include 
-
-void utils_list_init(struct utils_list *list)
-{
-    list->first = NULL;
-    list->last = NULL;
-}
-
-void utils_list_pool_init(struct utils_list *list, void *pool, size_t elmt_size, unsigned int elmt_cnt, void *default_value)
-{
-    unsigned int i;
-
-    // initialize the free list relative to the pool
-    utils_list_init(list);
-
-    // Add each element of the pool to this list, and init them one by one
-    for (i = 0; i < elmt_cnt; i++) {
-        if (default_value)
-        {
-            memcpy(pool, default_value, elmt_size);
-        }
-        utils_list_push_back(list, (struct utils_list_hdr *) pool);
-
-        // move to the next pool element
-        pool = (void *)((uint8_t *)pool + (unsigned int)elmt_size);
-    }
-}
-
-void utils_list_push_back(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    // Sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list_hdr != NULL);
-
-    // check if list is empty
-    if (utils_list_is_empty(list))
-    {
-        // list empty => pushed element is also head
-        list->first = list_hdr;
-    }
-    else
-    {
-        // list not empty => update next of last
-        list->last->next = list_hdr;
-    }
-
-    // add element at the end of the list
-    list->last = list_hdr;
-    list_hdr->next = NULL;
-}
-
-void utils_list_push_front(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    // Sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list_hdr != NULL);
-
-    // check if list is empty
-    if (utils_list_is_empty(list))
-    {
-        // list empty => pushed element is also head
-        list->last = list_hdr;
-    }
-
-    // add element at the beginning of the list
-    list_hdr->next = list->first;
-    list->first = list_hdr;
-}
-
-struct utils_list_hdr *utils_list_pop_front(struct utils_list *list)
-{
-    struct utils_list_hdr *element;
-
-    // check if list is empty
-    element = list->first;
-    if (element != NULL)
-    {
-        // The list isn't empty : extract the first element
-        list->first = list->first->next;
-    }
-
-    return element;
-}
-
-void utils_list_extract(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    struct utils_list_hdr *scan_list;
-
-    // sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list != NULL);
-
-    scan_list = list->first;
-
-    // Check if list is empty or not
-    if (scan_list == NULL)
-        return;
-
-    // check if searched element is first
-    if (scan_list == list_hdr)
-    {
-        // Extract first element
-        list->first = scan_list->next;
-    }
-    else
-    {
-        // Look for the element in the list
-        while ((scan_list->next != NULL) && (scan_list->next != list_hdr))
-        {
-            scan_list = scan_list->next;
-        }
-
-        // Check if element was found in the list
-        if (scan_list->next != NULL)
-        {
-            // check if the removed element is the last in the list
-            if (list->last == list_hdr)
-            {
-                // Last element will be extracted
-                list->last = scan_list;
-            }
-            // Extract the element from the list
-            scan_list->next = list_hdr->next;
-        }
-    }
-}
-
-int utils_list_find(struct utils_list *list, struct utils_list_hdr *list_hdr)
-{
-    struct utils_list_hdr *tmp_list_hdr;
-
-    // Go through the list to find the element
-    tmp_list_hdr = list->first;
-    while((tmp_list_hdr != list_hdr) && (tmp_list_hdr != NULL))
-    {
-        tmp_list_hdr = tmp_list_hdr->next;
-    }
-
-    return (tmp_list_hdr == list_hdr);
-}
-
-unsigned int utils_list_cnt(const struct utils_list *const list)
-{
-    unsigned int cnt = 0;
-    struct utils_list_hdr *elt = utils_list_pick(list);
-
-    // Go through the list to count the number of elements
-    while (elt != NULL)
-    {
-        cnt++;
-        elt = utils_list_next(elt);
-    }
-
-    return(cnt);
-}
-
-/**
- ****************************************************************************************
- * @brief Insert an element in a sorted list.
- *
- * This primitive use a comparison function from the parameter list to select where the
- * element must be inserted.
- *
- * @param[in]  list     Pointer to the list.
- * @param[in]  element  Pointer to the element to insert.
- * @param[in]  cmp      Comparison function (return true if first element has to be inserted
- *                      before the second one).
- *
- * @return              Pointer to the element found and removed (NULL otherwise).
- ****************************************************************************************
- */
-void utils_list_insert(struct utils_list * const list, struct utils_list_hdr * const element,
-                    int (*cmp)(struct utils_list_hdr const *elementA, struct utils_list_hdr const *elementB))
-{
-    struct utils_list_hdr *prev = NULL;
-    struct utils_list_hdr *scan = list->first;
-
-    for(;;)
-    {
-        // scan the list until the end or cmp() returns true
-        if (scan)
-        {
-            if (cmp(element, scan))
-            {
-                // insert now
-                break;
-            }
-            prev = scan;
-            scan = scan->next;
-        }
-        else
-        {
-            // end of list
-            list->last = element;
-            break;
-        }
-    }
-
-    element->next = scan;
-
-    if (prev)
-    {
-        // second or more
-        prev->next = element;
-    }
-    else
-    {
-        // first message
-        list->first = element;
-    }
-}
-
-void utils_list_insert_after(struct utils_list * const list, struct utils_list_hdr * const prev_element, struct utils_list_hdr * const element)
-{
-    struct utils_list_hdr *scan = list->first;
-
-    if (prev_element == NULL)
-    {
-        // Insert the element in front on the list
-        utils_list_push_front(list, element);
-    }
-    else
-    {
-        // Look for prev_element in the list
-        while (scan)
-        {
-            if (scan == prev_element)
-            {
-                break;
-            }
-
-            // Get next element
-            scan = scan->next;
-        }
-
-        // If prev_element has been found, insert element
-        if (scan)
-        {
-            element->next = prev_element->next;
-            prev_element->next = element;
-
-            if (element->next == NULL)
-            {
-                list->last = element;
-            }
-        }
-    }
-}
-
-void utils_list_insert_before(struct utils_list * const list, struct utils_list_hdr * const next_element, struct utils_list_hdr * const element)
-{
-    if (next_element == NULL)
-    {
-        // Insert the element at the end of the list
-        utils_list_push_back(list, element);
-    }
-    else if (next_element == list->first)
-    {
-        // Insert the element in front of the list
-        utils_list_push_front(list, element);
-    }
-    else
-    {
-        struct utils_list_hdr *scan = list->first;
-
-        // Look for next_element in the list
-        while (scan)
-        {
-            if (scan->next == next_element)
-            {
-                break;
-            }
-
-            // Get next element
-            scan = scan->next;
-        }
-
-        // Insert element after scan
-        if (scan)
-        {
-            element->next = next_element;
-            scan->next = element;
-        }
-    }
-}
-
-void utils_list_concat(struct utils_list *list1, struct utils_list *list2)
-{
-    // If list2 is empty, don't do anything
-    if (list2->first != NULL)
-    {
-        // Check if list1 is empty
-        if (list1->first == NULL)
-        {
-            // If list1 is empty, list1 becomes list2
-            *list1 = *list2;
-        }
-        else
-        {
-            // Otherwise, append list2 to list1
-            list1->last->next = list2->first;
-            list1->last = list2->last;
-        }
-        // Clear list2
-        list2->first = NULL;
-    }
-}
-
-
-void utils_list_remove(struct utils_list *list, struct utils_list_hdr *prev_element, struct utils_list_hdr *element)
-{
-    // sanity check
-    // FIXME assert error here
-    //ASSERT_ERR(list != NULL);
-    //ASSERT_ERR((prev_element == NULL) || (prev_element->next == element));
-    //ASSERT_ERR(element != NULL);
-
-
-    if (prev_element == NULL)
-    {
-        list->first = element->next;
-    }
-    else
-    {
-        prev_element->next = element->next;
-        if (list->last == element)
-            list->last = prev_element;
-    }
-
-    element->next = NULL;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_log.c b/bsp/bl808/m0/libraries/utils/src/utils_log.c
deleted file mode 100644
index 73fbeec762..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_log.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-#include "utils_log.h"
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#define ONE_LINE_MAX_NUM        (50)/* for print_buf log length */
-#define MODULE_LOG_LOCK_LOCK    /* reserved */
-#define MODULE_LOG_LOCK_UNLOCK  /* reserved */
-static char log_buf[512];
-int log_buf_out(const char *file, int line, const void *inbuf, int len, LOG_BUF_OUT_DATA_TYPE_T type)
-{
-    char *buf = (char *)inbuf;
-    char *pbuffer = NULL;
-
-#if defined(BL702) || defined(BL702L)
-    pbuffer = (char *)pvPortMalloc(sizeof(log_buf));
-    if(pbuffer == NULL){
-        return -1;
-    }
-#else
-    pbuffer = (char *)log_buf;
-#endif
-    int m = 0, n = 0;
-    int j = 0, k = 0, tmp = 0;
-
-    MODULE_LOG_LOCK_LOCK;
-
-    tmp = (sizeof(log_buf))/3;/* 数组最大长度 */
-    if ((ONE_LINE_MAX_NUM > tmp) || (len < 1))
-    {
-        MODULE_LOG_LOCK_UNLOCK;
-        return -1;
-    }
-
-    m = len / ONE_LINE_MAX_NUM;
-    n = len % ONE_LINE_MAX_NUM;
-    if (n > 0) {
-        m++;
-    }
-
-
-    if (n > 0) {
-        /* 非整数倍 */
-        for (k = 0; k < m; k++) {
-            if ((k+1) == m) {
-                /* 最后一帧数据 */
-                tmp = 0;
-                for (j = 0; j < n; j++) {
-                    switch (type) {
-                        case LOG_BUF_OUT_DATA_TYPE_INT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3d ", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_UNT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3u ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_HEX:
-                        default:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%02x ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                    }
-                }
-                log_buf_pri(file, line, "%.*s\r\n", tmp, pbuffer);
-            } else {
-                tmp = 0;
-                for (j = 0; j < ONE_LINE_MAX_NUM; j++) {
-                    switch (type) {
-                        case LOG_BUF_OUT_DATA_TYPE_INT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3d ", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_UNT8:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%3u ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                        break;
-                        case LOG_BUF_OUT_DATA_TYPE_HEX:
-                        default:
-                        {
-                            tmp += sprintf(pbuffer + tmp, "%02x ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                        }
-                    }
-                }
-                log_buf_pri(file, line, "%.*s\r\n", tmp, pbuffer);
-            }
-        }
-    } else {
-        /* 整数倍 */
-        for (k = 0; k < m; k++) {
-            tmp = 0;
-            for (j = 0; j < ONE_LINE_MAX_NUM; j++) {
-                switch (type) {
-                    case LOG_BUF_OUT_DATA_TYPE_INT8:
-                    {
-                        tmp += sprintf(pbuffer + tmp, "%3d ", (int8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                    }
-                    break;
-                    case LOG_BUF_OUT_DATA_TYPE_UNT8:
-                    {
-                        tmp += sprintf(pbuffer + tmp, "%3u ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                    }
-                    break;
-                    case LOG_BUF_OUT_DATA_TYPE_HEX:
-                    default:
-                    {
-                        tmp += sprintf(pbuffer + tmp, "%02x ", (uint8_t)buf[k*ONE_LINE_MAX_NUM+j]);
-                    }
-                }
-            }
-            log_buf_pri(file, line, "%.*s\r\n", tmp, pbuffer);
-        }
-    }
-
-    MODULE_LOG_LOCK_UNLOCK;
-
-#if defined(BL702) || defined(BL702L)
-    vPortFree(pbuffer);
-#endif
-
-    return 0;
-}
-
-extern void vprint(const char *fmt, va_list argp);
-
-extern volatile bool sys_log_all_enable;
-
-void bl_printk(const char *format, ...)
-{
-    va_list args;
-
-    if (sys_log_all_enable) {
-        /* args point to the first variable parameter */
-        va_start(args, format);
-
-        /* You can add your code under here. */
-        vprint(format, args);
-
-        va_end(args);
-    }
-}
-
-#ifdef __cplusplus
-}
-#endif
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_md5.c b/bsp/bl808/m0/libraries/utils/src/utils_md5.c
deleted file mode 100644
index a5dd329265..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_md5.c
+++ /dev/null
@@ -1,324 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef UTILS_MD5
-
-
-#include 
-#include 
-#include "iot_import.h"
-#include "iot_export.h"
-#include "iotx_log.h"
-#include "utils_md5.h"
-
-#define MD5_DIGEST_SIZE 16
-
-
-/* Implementation that should never be optimized out by the compiler */
-static void utils_md5_zeroize(void *v, size_t n)
-{
-    volatile unsigned char *p = v;
-    while (n--) {
-        *p++ = 0;
-    }
-}
-
-/*
- * 32-bit integer manipulation macros (little endian)
- */
-#ifndef IOT_MD5_GET_UINT32_LE
-#define IOT_MD5_GET_UINT32_LE(n,b,i)                            \
-    {                                                       \
-        (n) = ( (uint32_t) (b)[(i)    ]       )             \
-              | ( (uint32_t) (b)[(i) + 1] <<  8 )             \
-              | ( (uint32_t) (b)[(i) + 2] << 16 )             \
-              | ( (uint32_t) (b)[(i) + 3] << 24 );            \
-    }
-#endif
-
-#ifndef IOT_MD5_PUT_UINT32_LE
-#define IOT_MD5_PUT_UINT32_LE(n,b,i)                                    \
-    {                                                               \
-        (b)[(i)    ] = (unsigned char) ( ( (n)       ) & 0xFF );    \
-        (b)[(i) + 1] = (unsigned char) ( ( (n) >>  8 ) & 0xFF );    \
-        (b)[(i) + 2] = (unsigned char) ( ( (n) >> 16 ) & 0xFF );    \
-        (b)[(i) + 3] = (unsigned char) ( ( (n) >> 24 ) & 0xFF );    \
-    }
-#endif
-
-void utils_md5_init(iot_md5_context *ctx)
-{
-    memset(ctx, 0, sizeof(iot_md5_context));
-}
-
-void utils_md5_free(iot_md5_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    utils_md5_zeroize(ctx, sizeof(iot_md5_context));
-}
-
-void utils_md5_clone(iot_md5_context *dst,
-                     const iot_md5_context *src)
-{
-    *dst = *src;
-}
-
-/*
- * MD5 context setup
- */
-void utils_md5_starts(iot_md5_context *ctx)
-{
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    ctx->state[0] = 0x67452301;
-    ctx->state[1] = 0xEFCDAB89;
-    ctx->state[2] = 0x98BADCFE;
-    ctx->state[3] = 0x10325476;
-}
-
-void utils_md5_process(iot_md5_context *ctx, const unsigned char data[64])
-{
-    uint32_t X[16], A, B, C, D;
-
-    IOT_MD5_GET_UINT32_LE(X[ 0], data,  0);
-    IOT_MD5_GET_UINT32_LE(X[ 1], data,  4);
-    IOT_MD5_GET_UINT32_LE(X[ 2], data,  8);
-    IOT_MD5_GET_UINT32_LE(X[ 3], data, 12);
-    IOT_MD5_GET_UINT32_LE(X[ 4], data, 16);
-    IOT_MD5_GET_UINT32_LE(X[ 5], data, 20);
-    IOT_MD5_GET_UINT32_LE(X[ 6], data, 24);
-    IOT_MD5_GET_UINT32_LE(X[ 7], data, 28);
-    IOT_MD5_GET_UINT32_LE(X[ 8], data, 32);
-    IOT_MD5_GET_UINT32_LE(X[ 9], data, 36);
-    IOT_MD5_GET_UINT32_LE(X[10], data, 40);
-    IOT_MD5_GET_UINT32_LE(X[11], data, 44);
-    IOT_MD5_GET_UINT32_LE(X[12], data, 48);
-    IOT_MD5_GET_UINT32_LE(X[13], data, 52);
-    IOT_MD5_GET_UINT32_LE(X[14], data, 56);
-    IOT_MD5_GET_UINT32_LE(X[15], data, 60);
-
-#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
-
-#define P(a,b,c,d,k,s,t)                                \
-    {                                                       \
-        a += F(b,c,d) + X[k] + t; a = S(a,s) + b;           \
-    }
-
-    A = ctx->state[0];
-    B = ctx->state[1];
-    C = ctx->state[2];
-    D = ctx->state[3];
-
-#define F(x,y,z) (z ^ (x & (y ^ z)))
-
-    P(A, B, C, D,  0,  7, 0xD76AA478);
-    P(D, A, B, C,  1, 12, 0xE8C7B756);
-    P(C, D, A, B,  2, 17, 0x242070DB);
-    P(B, C, D, A,  3, 22, 0xC1BDCEEE);
-    P(A, B, C, D,  4,  7, 0xF57C0FAF);
-    P(D, A, B, C,  5, 12, 0x4787C62A);
-    P(C, D, A, B,  6, 17, 0xA8304613);
-    P(B, C, D, A,  7, 22, 0xFD469501);
-    P(A, B, C, D,  8,  7, 0x698098D8);
-    P(D, A, B, C,  9, 12, 0x8B44F7AF);
-    P(C, D, A, B, 10, 17, 0xFFFF5BB1);
-    P(B, C, D, A, 11, 22, 0x895CD7BE);
-    P(A, B, C, D, 12,  7, 0x6B901122);
-    P(D, A, B, C, 13, 12, 0xFD987193);
-    P(C, D, A, B, 14, 17, 0xA679438E);
-    P(B, C, D, A, 15, 22, 0x49B40821);
-
-#undef F
-
-#define F(x,y,z) (y ^ (z & (x ^ y)))
-
-    P(A, B, C, D,  1,  5, 0xF61E2562);
-    P(D, A, B, C,  6,  9, 0xC040B340);
-    P(C, D, A, B, 11, 14, 0x265E5A51);
-    P(B, C, D, A,  0, 20, 0xE9B6C7AA);
-    P(A, B, C, D,  5,  5, 0xD62F105D);
-    P(D, A, B, C, 10,  9, 0x02441453);
-    P(C, D, A, B, 15, 14, 0xD8A1E681);
-    P(B, C, D, A,  4, 20, 0xE7D3FBC8);
-    P(A, B, C, D,  9,  5, 0x21E1CDE6);
-    P(D, A, B, C, 14,  9, 0xC33707D6);
-    P(C, D, A, B,  3, 14, 0xF4D50D87);
-    P(B, C, D, A,  8, 20, 0x455A14ED);
-    P(A, B, C, D, 13,  5, 0xA9E3E905);
-    P(D, A, B, C,  2,  9, 0xFCEFA3F8);
-    P(C, D, A, B,  7, 14, 0x676F02D9);
-    P(B, C, D, A, 12, 20, 0x8D2A4C8A);
-
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-
-    P(A, B, C, D,  5,  4, 0xFFFA3942);
-    P(D, A, B, C,  8, 11, 0x8771F681);
-    P(C, D, A, B, 11, 16, 0x6D9D6122);
-    P(B, C, D, A, 14, 23, 0xFDE5380C);
-    P(A, B, C, D,  1,  4, 0xA4BEEA44);
-    P(D, A, B, C,  4, 11, 0x4BDECFA9);
-    P(C, D, A, B,  7, 16, 0xF6BB4B60);
-    P(B, C, D, A, 10, 23, 0xBEBFBC70);
-    P(A, B, C, D, 13,  4, 0x289B7EC6);
-    P(D, A, B, C,  0, 11, 0xEAA127FA);
-    P(C, D, A, B,  3, 16, 0xD4EF3085);
-    P(B, C, D, A,  6, 23, 0x04881D05);
-    P(A, B, C, D,  9,  4, 0xD9D4D039);
-    P(D, A, B, C, 12, 11, 0xE6DB99E5);
-    P(C, D, A, B, 15, 16, 0x1FA27CF8);
-    P(B, C, D, A,  2, 23, 0xC4AC5665);
-
-#undef F
-
-#define F(x,y,z) (y ^ (x | ~z))
-
-    P(A, B, C, D,  0,  6, 0xF4292244);
-    P(D, A, B, C,  7, 10, 0x432AFF97);
-    P(C, D, A, B, 14, 15, 0xAB9423A7);
-    P(B, C, D, A,  5, 21, 0xFC93A039);
-    P(A, B, C, D, 12,  6, 0x655B59C3);
-    P(D, A, B, C,  3, 10, 0x8F0CCC92);
-    P(C, D, A, B, 10, 15, 0xFFEFF47D);
-    P(B, C, D, A,  1, 21, 0x85845DD1);
-    P(A, B, C, D,  8,  6, 0x6FA87E4F);
-    P(D, A, B, C, 15, 10, 0xFE2CE6E0);
-    P(C, D, A, B,  6, 15, 0xA3014314);
-    P(B, C, D, A, 13, 21, 0x4E0811A1);
-    P(A, B, C, D,  4,  6, 0xF7537E82);
-    P(D, A, B, C, 11, 10, 0xBD3AF235);
-    P(C, D, A, B,  2, 15, 0x2AD7D2BB);
-    P(B, C, D, A,  9, 21, 0xEB86D391);
-
-#undef F
-
-    ctx->state[0] += A;
-    ctx->state[1] += B;
-    ctx->state[2] += C;
-    ctx->state[3] += D;
-}
-
-/*
- * MD5 process buffer
- */
-void utils_md5_update(iot_md5_context *ctx, const unsigned char *input, size_t ilen)
-{
-    size_t fill;
-    uint32_t left;
-
-    if (ilen == 0) {
-        return;
-    }
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if (ctx->total[0] < (uint32_t) ilen) {
-        ctx->total[1]++;
-    }
-
-    if (left && ilen >= fill) {
-        memcpy((void *)(ctx->buffer + left), input, fill);
-        utils_md5_process(ctx, ctx->buffer);
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while (ilen >= 64) {
-        utils_md5_process(ctx, input);
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if (ilen > 0) {
-        memcpy((void *)(ctx->buffer + left), input, ilen);
-    }
-}
-
-static const unsigned char iot_md5_padding[64] = {
-    0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * MD5 final digest
- */
-void utils_md5_finish(iot_md5_context *ctx, unsigned char output[16])
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = (ctx->total[0] >> 29)
-           | (ctx->total[1] <<  3);
-    low  = (ctx->total[0] <<  3);
-
-    IOT_MD5_PUT_UINT32_LE(low,  msglen, 0);
-    IOT_MD5_PUT_UINT32_LE(high, msglen, 4);
-
-    last = ctx->total[0] & 0x3F;
-    padn = (last < 56) ? (56 - last) : (120 - last);
-
-    utils_md5_update(ctx, iot_md5_padding, padn);
-    utils_md5_update(ctx, msglen, 8);
-
-    IOT_MD5_PUT_UINT32_LE(ctx->state[0], output,  0);
-    IOT_MD5_PUT_UINT32_LE(ctx->state[1], output,  4);
-    IOT_MD5_PUT_UINT32_LE(ctx->state[2], output,  8);
-    IOT_MD5_PUT_UINT32_LE(ctx->state[3], output, 12);
-}
-
-
-/*
- * output = MD5( input buffer )
- */
-void utils_md5(const unsigned char *input, size_t ilen, unsigned char output[16])
-{
-    iot_md5_context ctx;
-
-    utils_md5_init(&ctx);
-    utils_md5_starts(&ctx);
-    utils_md5_update(&ctx, input, ilen);
-    utils_md5_finish(&ctx, output);
-    utils_md5_free(&ctx);
-}
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_memp.c b/bsp/bl808/m0/libraries/utils/src/utils_memp.c
deleted file mode 100644
index 43d56f9ca1..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_memp.c
+++ /dev/null
@@ -1,180 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-
-#define UTILS_MEMP_ALLOCED_NODE_PATTERN 0XA5
-#define MEM_ALIGN(addr, align) (((addr) + (align) -1) & ~((align)-1))
-
-int utils_memp_init(utils_memp_pool_t **pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req)
-{
-    utils_memp_pool_t *npool;
-    struct utils_memp_node *node;
-    struct utils_memp_node *pool_mem;
-    size_t size;
-    uint16_t padded_node_size;
-    uint16_t i;
-
-    align_req = MEM_ALIGN(align_req, sizeof(void *));
-    padded_node_size = MEM_ALIGN(node_size + sizeof(struct utils_memp_node), align_req);
-
-    size = sizeof(utils_memp_pool_t);
-    size = MEM_ALIGN(size, align_req);
-    size += padded_node_size * pool_cap;
-
-    npool = pvPortMalloc(size);
-
-    if (!npool) {
-        return -1;
-    }
-
-    node = (struct utils_memp_node *)((uint8_t *)npool + (size - padded_node_size * pool_cap));
-    npool->first_node = node;
-    npool->node_size = node_size;
-    npool->pool_cap = pool_cap;
-    npool->pool_size = 0;
-    npool->align_req = align_req;
-    npool->padded_node_size = padded_node_size;
-    npool->mem = NULL;
-    pool_mem = npool->mem;
-
-    for(i = 0; i < pool_cap; ++i) {
-        node->next = pool_mem;
-        pool_mem = node;
-        node = (struct utils_memp_node *)((uint8_t *)node + padded_node_size);
-    }
-    npool->mem = pool_mem;
-    npool->last_node = npool->mem;
-    *pool = npool;
-
-    return 0;
-}
-
-int utils_memp_init_alloced(utils_memp_pool_t *pool, uint16_t node_size, uint16_t pool_cap, uint8_t align_req)
-{
-    utils_memp_pool_t *npool = pool;
-    struct utils_memp_node *node;
-    struct utils_memp_node *pool_mem;
-    size_t size;
-    uint16_t padded_node_size;
-    uint16_t i;
-
-    align_req = MEM_ALIGN(align_req, sizeof(void *));
-    padded_node_size = MEM_ALIGN(node_size + sizeof(struct utils_memp_node), align_req);
-
-    size = sizeof(utils_memp_pool_t);
-    size = MEM_ALIGN(size, align_req);
-    size += padded_node_size * pool_cap;
-
-    node = (struct utils_memp_node *)((uint8_t *)npool + (size - padded_node_size * pool_cap));
-    npool->first_node = node;
-    npool->node_size = node_size;
-    npool->pool_cap = pool_cap;
-    npool->pool_size = 0;
-    npool->align_req = align_req;
-    npool->padded_node_size = padded_node_size;
-    npool->mem = NULL;
-    pool_mem = npool->mem;
-
-    for(i = 0; i < pool_cap; ++i) {
-        node->next = pool_mem;
-        pool_mem = node;
-        node = (struct utils_memp_node *)((uint8_t *)node + padded_node_size);
-    }
-    npool->mem = pool_mem;
-    npool->last_node = npool->mem;
-
-    return 0;
-}
-
-int utils_memp_deinit(utils_memp_pool_t *pool)
-{
-    if (!pool) {
-        return -1;
-    }
-    vPortFree(pool);
-
-    return 0;
-}
-
-void *utils_memp_malloc(utils_memp_pool_t *pool)
-{
-    struct utils_memp_node *node;
-    uint32_t *pat;
-    if (!pool) {
-        return NULL;
-    }
-    if (pool->pool_size == pool->pool_cap) {
-        return NULL;
-    }
-    node = pool->mem;
-    if (node != NULL) {
-        pool->mem = node->next;
-        pool->pool_size++;
-        pat = (uint32_t *)&node->next;
-        *pat = UTILS_MEMP_ALLOCED_NODE_PATTERN;
-        return (void *)node + sizeof(struct utils_memp_node);
-    } else {
-        return NULL;
-    }
-}
-
-int utils_memp_free(utils_memp_pool_t *pool, void *node)
-{
-    struct utils_memp_node *utils_memp_node;
-    node = node - sizeof(struct utils_memp_node);
-    uint32_t *pat;
-    int diff;
-
-    if (!pool || !node) {
-        return -1;
-    }
-    if (pool->pool_size == 0) {
-        return -1;
-    }
-    if (!(node >= pool->first_node && node <= pool->last_node)) {
-        return -1;
-    }
-    diff = node - pool->first_node;
-    if (diff % pool->padded_node_size) {
-        return -1;
-    }
-
-    pat = (uint32_t *)(&((struct utils_memp_node *)node)->next);
-    if (*pat != UTILS_MEMP_ALLOCED_NODE_PATTERN) {
-        return -1;
-    }
-    utils_memp_node = (struct utils_memp_node*)node;
-    utils_memp_node->next = pool->mem;
-    pool->mem = utils_memp_node;
-    pool->pool_size--;
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_notifier.c b/bsp/bl808/m0/libraries/utils/src/utils_notifier.c
deleted file mode 100644
index c6ab60240f..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_notifier.c
+++ /dev/null
@@ -1,69 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include "utils_notifier.h"
-
-int utils_notifier_chain_init(ntf_list_t *nl)
-{
-    utils_list_init((struct utils_list *)nl);
-
-    return 0;
-}
-
-int utils_notifier_chain_register(ntf_list_t *nl, utils_notifier_t *node)
-{
-    if (!nl || !node) {
-        return -1;
-    }
-    utils_list_push_back((struct utils_list *)nl, (struct utils_list_hdr *)node);
-
-    return 0;
-}
-
-int utils_notifier_chain_call(ntf_list_t *nl, void *env)
-{
-    utils_notifier_t *raw;
-
-    if (!nl) {
-        return 0;
-    }
-
-    raw = (utils_notifier_t *)nl->first;
-
-    while (raw) {
-        if (raw->cb) {
-            raw->cb(raw->cb_arg, env);
-        }
-        raw = (utils_notifier_t *)raw->node.next;
-    }
-
-    return 0;
-}
-
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c b/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c
deleted file mode 100644
index 87485e76a3..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_psk_fast.c
+++ /dev/null
@@ -1,115 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-
-#include 
-#include 
-#include 
-#include 
-
-#define A_SHA_DIGEST_LEN 20
-static void Bl_F_fast(unsigned char digest[36], unsigned char digest1[A_SHA_DIGEST_LEN], char *password, unsigned char *ssid, int ssidlength, int iterations, int count, unsigned char *output)
-{
-    int i, j;
-    int len = strlen(password);
-    int tmpLen = ssidlength + 4;
-    unsigned char * pTemp = digest;
-
-    /* U1 = PRF(P, S || int(i)) */
-    memcpy(digest, ssid, ssidlength);
-    digest[ssidlength] = (unsigned char)((count>>24) & 0xff);
-    digest[ssidlength+1] = (unsigned char)((count>>16) & 0xff);
-    digest[ssidlength+2] = (unsigned char)((count>>8) & 0xff);
-    digest[ssidlength+3] = (unsigned char)(count & 0xff);
-
-    bl_sha_mutex_take();
-    utils_hmac_sha1_fast(&pTemp,
-                   &tmpLen,
-                   1,
-                   (unsigned char*) password,
-                   len,
-                   digest1,
-                   A_SHA_DIGEST_LEN);
-
-    /* output = U1 */
-    memcpy(output, digest1, A_SHA_DIGEST_LEN);
-    pTemp = digest1;
-    for (i = 1; i < iterations; i++)
-    {
-        tmpLen = A_SHA_DIGEST_LEN;
-
-        /* Un = PRF(P, Un-1) */
-        utils_hmac_sha1_fast(&pTemp,
-                       &tmpLen,
-                       1,
-                       (unsigned char*) password,
-                       len,
-                       digest,
-                       A_SHA_DIGEST_LEN);
-
-        memcpy(digest1, digest, A_SHA_DIGEST_LEN);
-
-        /* output = output xor Un */
-        for (j = 0; j < A_SHA_DIGEST_LEN; j++)
-        {
-            output[j] ^= digest[j];
-        }
-    }
-    bl_sha_mutex_give();
-}
-
-int utils_wifi_psk_cal_fast_bin(char *password, unsigned char *ssid, int ssidlength, unsigned char *output)
-{
-    unsigned char digest[36], digest1[A_SHA_DIGEST_LEN];
-
-    if ((strlen(password) > 63) || (ssidlength > 32)) {
-        return -1;
-    }
-
-    Bl_F_fast(digest, digest1, password, ssid, ssidlength, 4096, 2, output);
-    memcpy(output + A_SHA_DIGEST_LEN, output, 12);
-    Bl_F_fast(digest, digest1, password, ssid, ssidlength, 4096, 1, output);
-
-    return 0;
-}
-
-int utils_wifi_psk_cal_fast(char *password, char *ssid, int ssid_len, char *output)
-{
-    int ret;
-    char psk[32];
-
-    ret = utils_wifi_psk_cal_fast_bin(password, (unsigned char *)ssid, ssid_len, (unsigned char *)psk);
-    if (0 == ret) {
-        utils_bin2hex(output, psk, 32);
-    }
-
-    return ret;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c b/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c
deleted file mode 100644
index 4a39ee0091..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_rbtree.c
+++ /dev/null
@@ -1,526 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#include 
-#include "utils_rbtree.h"
-
-// rb_node
-
-struct rb_node * rb_node_alloc ()
-{
-    return pvPortMalloc(sizeof(struct rb_node));
-}
-
-struct rb_node * rb_node_init (struct rb_node *self, void *value)
-{
-    if (self) {
-        self->red = 1;
-        self->link[0] = self->link[1] = NULL;
-        self->value = value;
-    }
-    return self;
-}
-
-struct rb_node * rb_node_create (void *value)
-{
-    return rb_node_init(rb_node_alloc(), value);
-}
-
-void rb_node_dealloc (struct rb_node *self)
-{
-    if (self) {
-        vPortFree(self);
-    }
-}
-
-static int rb_node_is_red (const struct rb_node *self)
-{
-    return self ? self->red : 0;
-}
-
-static struct rb_node * rb_node_rotate (struct rb_node *self, int dir)
-{
-    struct rb_node *result = NULL;
-
-    if (self) {
-        result = self->link[!dir];
-        self->link[!dir] = result->link[dir];
-        result->link[dir] = self;
-        self->red = 1;
-        result->red = 0;
-    }
-    return result;
-}
-
-static struct rb_node * rb_node_rotate2 (struct rb_node *self, int dir)
-{
-    struct rb_node *result = NULL;
-
-    if (self) {
-        self->link[!dir] = rb_node_rotate(self->link[!dir], !dir);
-        result = rb_node_rotate(self, dir);
-    }
-    return result;
-}
-
-// rb_tree - default callbacks
-int rb_tree_node_cmp_ptr_cb (struct rb_tree *self, struct rb_node *a, struct rb_node *b)
-{
-    return (a->value > b->value) - (a->value < b->value);
-}
-
-void rb_tree_node_dealloc_cb (struct rb_tree *self, struct rb_node *node)
-{
-    if (self) {
-        if (node) {
-            rb_node_dealloc(node);
-        }
-    }
-}
-
-// rb_tree
-struct rb_tree * rb_tree_alloc ()
-{
-    return pvPortMalloc(sizeof(struct rb_tree));
-}
-
-struct rb_tree * rb_tree_init (struct rb_tree *self, rb_tree_node_cmp_f node_cmp_cb)
-{
-    if (self) {
-        self->root = NULL;
-        self->size = 0;
-        self->cmp = node_cmp_cb ? node_cmp_cb : rb_tree_node_cmp_ptr_cb;
-    }
-
-    return self;
-}
-
-struct rb_tree * rb_tree_create (rb_tree_node_cmp_f node_cb)
-{
-    return rb_tree_init(rb_tree_alloc(), node_cb);
-}
-
-void rb_tree_dealloc(struct rb_tree *self, rb_tree_node_f node_cb)
-{
-    if (self) {
-        if (node_cb) {
-            struct rb_node *node = self->root;
-            struct rb_node *save = NULL;
-
-            // Rotate away the left links so that
-            // we can treat this like the destruction
-            // of a linked list
-            while (node) {
-                if (node->link[0] == NULL) {
-
-                    // No left links, just kill the node and move on
-                    save = node->link[1];
-                    node_cb(self, node);
-                    node = NULL;
-                } else {
-
-                    // Rotate away the left link and check again
-                    save = node->link[0];
-                    node->link[0] = save->link[1];
-                    save->link[1] = node;
-                }
-                node = save;
-            }
-        }
-        vPortFree(self);
-    }
-}
-
-int rb_tree_test(struct rb_tree *self, struct rb_node *root)
-{
-    int lh, rh;
-
-    if (NULL == root) {
-        return 1;
-    } else {
-        struct rb_node *ln = root->link[0];
-        struct rb_node *rn = root->link[1];
-
-        /* Consecutive red links */
-        if (rb_node_is_red(root)) {
-            if (rb_node_is_red(ln) || rb_node_is_red(rn)) {
-                printf("Red violation");
-                return 0;
-            }
-        }
-
-        lh = rb_tree_test(self, ln);
-        rh = rb_tree_test(self, rn);
-
-        /* Invalid binary search tree */
-        if ( ( ln != NULL && self->cmp(self, ln, root) >= 0 )
-            || ( rn != NULL && self->cmp(self, rn, root) <= 0))
-        {
-            puts ( "Binary tree violation" );
-            return 0;
-        }
-
-        /* Black height mismatch */
-        if ( lh != 0 && rh != 0 && lh != rh ) {
-            puts ( "Black violation" );
-            return 0;
-        }
-
-        /* Only count black links */
-        if ( lh != 0 && rh != 0 )
-            return rb_node_is_red ( root ) ? lh : lh + 1;
-        else
-            return 0;
-    }
-}
-
-void * rb_tree_find(struct rb_tree *self, void *value)
-{
-    void *result = NULL;
-
-    if (self) {
-        struct rb_node node = { .value = value };
-        struct rb_node *it = self->root;
-        int cmp = 0;
-        while (it) {
-            if ((cmp = self->cmp(self, it, &node))) {
-
-                // If the tree supports duplicates, they should be
-                // chained to the right subtree for this to work
-                it = it->link[cmp < 0];
-            } else {
-                break;
-            }
-        }
-        result = it ? it->value : NULL;
-    }
-    return result;
-}
-
-// Creates (malloc'ates)
-int rb_tree_insert(struct rb_tree *self, void *value)
-{
-    struct rb_node *node;
-
-    if (NULL == self) {
-        return 0;
-    }
-
-    node = rb_node_create(value);
-
-    if (NULL == node) {
-        return 0;
-    }
-
-    return rb_tree_insert_node(self, node);
-}
-
-// Returns 1 on success, 0 otherwise.
-int rb_tree_insert_node (struct rb_tree *self, struct rb_node *node)
-{
-    if (self && node) {
-        if (self->root == NULL) {
-            self->root = node;
-        } else {
-            struct rb_node head = { 0 }; // False tree root
-            struct rb_node *g, *t;       // Grandparent & parent
-            struct rb_node *p, *q;       // Iterator & parent
-            int dir = 0, last = 0;
-
-            // Set up our helpers
-            t = &head;
-            g = p = NULL;
-            q = t->link[1] = self->root;
-
-            // Search down the tree for a place to insert
-            while (1) {
-                if (q == NULL) {
-
-                    // Insert node at the first null link.
-                    p->link[dir] = q = node;
-                } else if (rb_node_is_red(q->link[0]) && rb_node_is_red(q->link[1])) {
-
-                    // Simple red violation: color flip
-                    q->red = 1;
-                    q->link[0]->red = 0;
-                    q->link[1]->red = 0;
-                }
-
-                if (rb_node_is_red(q) && rb_node_is_red(p)) {
-
-                    // Hard red violation: rotations necessary
-                    int dir2 = t->link[1] == g;
-                    if (q == p->link[last]) {
-                        t->link[dir2] = rb_node_rotate(g, !last);
-                    } else {
-                        t->link[dir2] = rb_node_rotate2(g, !last);
-                    }
-                }
-
-                // Stop working if we inserted a node. This
-                // check also disallows duplicates in the tree
-                if (self->cmp(self, q, node) == 0) {
-                    break;
-                }
-
-                last = dir;
-                dir = self->cmp(self, q, node) < 0;
-
-                // Move the helpers down
-                if (g != NULL) {
-                    t = g;
-                }
-
-                g = p, p = q;
-                q = q->link[dir];
-            }
-
-            // Update the root (it may be different)
-            self->root = head.link[1];
-        }
-
-        // Make the root black for simplified logic
-        self->root->red = 0;
-        ++self->size;
-    } else {
-        return 0;
-    }
-
-    return 1;
-}
-
-// Returns 1 if the value was removed, 0 otherwise. Optional node callback
-// can be provided to dealloc node and/or user data. Use rb_tree_node_dealloc
-// default callback to deallocate node created by rb_tree_insert(...).
-int rb_tree_remove_with_cb (struct rb_tree *self, void *value, rb_tree_node_f node_cb)
-{
-    if (self->root != NULL) {
-        struct rb_node head = {0}; // False tree root
-        struct rb_node node = { .value = value }; // Value wrapper node
-        struct rb_node *q, *p, *g; // Helpers
-        struct rb_node *f = NULL;  // Found item
-        int dir = 1;
-
-        // Set up our helpers
-        q = &head;
-        g = p = NULL;
-        q->link[1] = self->root;
-
-        // Search and push a red node down
-        // to fix red violations as we go
-        while (q->link[dir] != NULL) {
-            int last = dir;
-
-            // Move the helpers down
-            g = p, p = q;
-            q = q->link[dir];
-            dir = self->cmp(self, q, &node) < 0;
-
-            // Save the node with matching value and keep
-            // going; we'll do removal tasks at the end
-            if (self->cmp(self, q, &node) == 0) {
-                f = q;
-            }
-
-            // Push the red node down with rotations and color flips
-            if (!rb_node_is_red(q) && !rb_node_is_red(q->link[dir])) {
-                if (rb_node_is_red(q->link[!dir])) {
-                    p = p->link[last] = rb_node_rotate(q, dir);
-                } else if (!rb_node_is_red(q->link[!dir])) {
-                    struct rb_node *s = p->link[!last];
-                    if (s) {
-                        if (!rb_node_is_red(s->link[!last]) && !rb_node_is_red(s->link[last])) {
-
-                            // Color flip
-                            p->red = 0;
-                            s->red = 1;
-                            q->red = 1;
-                        } else {
-                            int dir2 = g->link[1] == p;
-                            if (rb_node_is_red(s->link[last])) {
-                                g->link[dir2] = rb_node_rotate2(p, last);
-                            } else if (rb_node_is_red(s->link[!last])) {
-                                g->link[dir2] = rb_node_rotate(p, last);
-                            }
-
-                            // Ensure correct coloring
-                            q->red = g->link[dir2]->red = 1;
-                            g->link[dir2]->link[0]->red = 0;
-                            g->link[dir2]->link[1]->red = 0;
-                        }
-                    }
-                }
-            }
-        }
-
-        // Replace and remove the saved node
-        if (f) {
-            void *tmp = f->value;
-            f->value = q->value;
-            q->value = tmp;
-
-            p->link[p->link[1] == q] = q->link[q->link[0] == NULL];
-
-            if (node_cb) {
-                node_cb(self, q);
-            }
-            q = NULL;
-        }
-
-        // Update the root (it may be different)
-        self->root = head.link[1];
-
-        // Make the root black for simplified logic
-        if (self->root != NULL) {
-            self->root->red = 0;
-        }
-
-        --self->size;
-    }
-    return 1;
-}
-
-int rb_tree_remove (struct rb_tree *self, void *value)
-{
-    int result = 0;
-
-    if (self) {
-        result = rb_tree_remove_with_cb(self, value, rb_tree_node_dealloc_cb);
-    }
-    return result;
-}
-
-size_t rb_tree_size (struct rb_tree *self)
-{
-    size_t result = 0;
-
-    if (self) {
-        result = self->size;
-    }
-    return result;
-}
-
-// rb_iter
-struct rb_iter * rb_iter_alloc ()
-{
-    return pvPortMalloc(sizeof(struct rb_iter));
-}
-
-struct rb_iter * rb_iter_init (struct rb_iter *self)
-{
-    if (self) {
-        self->tree = NULL;
-        self->node = NULL;
-        self->top = 0;
-    }
-    return self;
-}
-
-struct rb_iter * rb_iter_create ()
-{
-    return rb_iter_init(rb_iter_alloc());
-}
-
-void rb_iter_dealloc (struct rb_iter *self)
-{
-    if (self) {
-        vPortFree(self);
-    }
-}
-
-// Internal function, init traversal object, dir determines whether
-// to begin traversal at the smallest or largest valued node.
-static void * rb_iter_start (struct rb_iter *self, struct rb_tree *tree, int dir)
-{
-    void *result = NULL;
-
-    if (self) {
-        self->tree = tree;
-        self->node = tree->root;
-        self->top = 0;
-
-        // Save the path for later selfersal
-        if (self->node != NULL) {
-            while (self->node->link[dir] != NULL) {
-                self->path[self->top++] = self->node;
-                self->node = self->node->link[dir];
-            }
-        }
-        result = self->node == NULL ? NULL : self->node->value;
-    }
-
-    return result;
-}
-
-// Traverse a red black tree in the user-specified direction (0 asc, 1 desc)
-static void * rb_iter_move(struct rb_iter *self, int dir)
-{
-    if (self->node->link[dir] != NULL) {
-        // Continue down this branch
-        self->path[self->top++] = self->node;
-        self->node = self->node->link[dir];
-        while ( self->node->link[!dir] != NULL ) {
-            self->path[self->top++] = self->node;
-            self->node = self->node->link[!dir];
-        }
-    } else {
-        // Move to the next branch
-        struct rb_node *last = NULL;
-        do {
-            if (self->top == 0) {
-                self->node = NULL;
-                break;
-            }
-            last = self->node;
-            self->node = self->path[--self->top];
-        } while (last == self->node->link[dir]);
-    }
-    return self->node == NULL ? NULL : self->node->value;
-}
-
-void *rb_iter_first(struct rb_iter *self, struct rb_tree *tree)
-{
-    return rb_iter_start(self, tree, 0);
-}
-
-void * rb_iter_last(struct rb_iter *self, struct rb_tree *tree)
-{
-    return rb_iter_start(self, tree, 1);
-}
-
-void * rb_iter_next(struct rb_iter *self)
-{
-    return rb_iter_move(self, 1);
-}
-
-void * rb_iter_prev(struct rb_iter *self)
-{
-    return rb_iter_move(self, 0);
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c b/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c
deleted file mode 100644
index 7a9b3da047..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_ringblk.c
+++ /dev/null
@@ -1,578 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-
-#include 
-#include 
-
-#include "FreeRTOS.h"
-#include "utils_list.h"
-#include "utils_ringblk.h"
-
-/**
- * ring block buffer object initialization
- *
- * @param rbb ring block buffer object
- * @param buf buffer
- * @param buf_size buffer size
- * @param block_set block set
- * @param blk_max_num max block number
- *
- * @note When your application need align access, please make the buffer address is aligned.
- */
-void utils_rbb_init(utils_rbb_t rbb, uint8_t *buf, uint32_t buf_size, utils_rbb_blk_t block_set, uint32_t blk_max_num)
-{
-    uint32_t i;
-
-    assert(rbb);
-    assert(buf);
-    assert(block_set);
-
-    rbb->buf = buf;
-    rbb->buf_size = buf_size;
-    rbb->blk_set = block_set;
-    rbb->blk_max_num = blk_max_num;
-    utils_slist_init(&rbb->blk_list);
-    /* initialize block status */
-    for (i = 0; i < blk_max_num; i++)
-    {
-        block_set[i].status = RBB_BLK_UNUSED;
-    }
-}
-
-
-/**
- * ring block buffer object create
- *
- * @param buf_size buffer size
- * @param blk_max_num max block number
- *
- * @return != NULL: ring block buffer object
- *            NULL: create failed
- */
-utils_rbb_t utils_rbb_create(uint32_t buf_size, uint32_t blk_max_num)
-{
-    utils_rbb_t rbb = NULL;
-    uint8_t *buf;
-    utils_rbb_blk_t blk_set;
-
-    rbb = (utils_rbb_t)pvPortMalloc(sizeof(struct utils_rbb));
-    if (!rbb)
-    {
-        return NULL;
-    }
-
-    buf = (uint8_t *)pvPortMalloc(buf_size);
-    if (!buf)
-    {
-        vPortFree(rbb);
-        return NULL;
-    }
-
-    blk_set = (utils_rbb_blk_t)pvPortMalloc(sizeof(struct utils_rbb_blk) * blk_max_num);
-    if (!blk_set)
-    {
-        vPortFree(buf);
-        vPortFree(rbb);
-        return NULL;
-    }
-
-    utils_rbb_init(rbb, buf, buf_size, blk_set, blk_max_num);
-
-    return rbb;
-}
-
-/**
- * ring block buffer object destroy
- *
- * @param rbb ring block buffer object
- */
-void utils_rbb_destroy(utils_rbb_t rbb)
-{
-    assert(rbb);
-
-    vPortFree(rbb->buf);
-    vPortFree(rbb->blk_set);
-    vPortFree(rbb);
-
-}
-
-utils_rbb_blk_t utils_rbb_find_used_blk(utils_rbb_t rbb)
-{
-    uint32_t i;
-
-    assert(rbb);
-
-    for (i = 0; i < rbb->blk_max_num; i ++)
-    {
-        if (rbb->blk_set[i].status != RBB_BLK_UNUSED)
-        {
-            return &rbb->blk_set[i];
-        }
-    }
-
-    return NULL;
-}
-
-utils_rbb_blk_t utils_rbb_find_empty_blk(utils_rbb_t rbb)
-{
-    uint32_t i;
-
-    assert(rbb);
-
-    for (i = 0; i < rbb->blk_max_num; i ++)
-    {
-        if (rbb->blk_set[i].status == RBB_BLK_UNUSED)
-        {
-            return &rbb->blk_set[i];
-        }
-    }
-
-    return NULL;
-}
-
-/**
- * Allocate a block by given size. The block will add to blk_list when allocate success.
- *
- * @param rbb ring block buffer object
- * @param blk_size block size
- *
- * @note When your application need align access, please make the blk_szie is aligned.
- *
- * @return != NULL: allocated block
- *            NULL: allocate failed
- */
-utils_rbb_blk_t utils_rbb_blk_alloc(utils_rbb_t rbb, uint32_t blk_size)
-{
-    uint32_t empty1 = 0, empty2 = 0;
-    utils_rbb_blk_t head, tail, new_rbb = NULL;
-    int list_num = 0;
-
-    assert(rbb);
-    assert(blk_size < (1L << 24));
-
-    portENTER_CRITICAL();
-
-    new_rbb = utils_rbb_find_empty_blk(rbb);
-
-    list_num = utils_slist_entry_number(&rbb->blk_list);
-
-    if (list_num < rbb->blk_max_num && new_rbb)
-    {
-        if (list_num > 0)
-        {
-            head = utils_slist_first_entry(&rbb->blk_list, struct utils_rbb_blk, list);
-            tail = utils_slist_tail_entry(&rbb->blk_list, struct utils_rbb_blk, list);
-            if (head->buf <= tail->buf)
-            {
-                /**
-                 *                      head                     tail
-                 * +--------------------------------------+-----------------+------------------+
-                 * |      empty2     | block1 |   block2  |      block3     |       empty1     |
-                 * +--------------------------------------+-----------------+------------------+
-                 *                            rbb->buf
-                 */
-                empty1 = (rbb->buf + rbb->buf_size) - (tail->buf + tail->size);
-                empty2 = head->buf - rbb->buf;
-
-                if (empty1 >= blk_size)
-                {
-                    utils_slist_append(&rbb->blk_list, &new_rbb->list);
-                    new_rbb->status = RBB_BLK_INITED;
-                    new_rbb->buf = tail->buf + tail->size;
-                    new_rbb->size = blk_size;
-                }
-                else if (empty2 >= blk_size)
-                {
-                    utils_slist_append(&rbb->blk_list, &new_rbb->list);
-                    new_rbb->status = RBB_BLK_INITED;
-                    new_rbb->buf = rbb->buf;
-                    new_rbb->size = blk_size;
-                }
-                else
-                {
-                    /* no space */
-                    new_rbb = NULL;
-                }
-            }
-            else
-            {
-                /**
-                 *        tail                                              head
-                 * +----------------+-------------------------------------+--------+-----------+
-                 * |     block3     |                empty1               | block1 |  block2   |
-                 * +----------------+-------------------------------------+--------+-----------+
-                 *                            rbb->buf
-                 */
-                empty1 = head->buf - (tail->buf + tail->size);
-
-                if (empty1 >= blk_size)
-                {
-                    utils_slist_append(&rbb->blk_list, &new_rbb->list);
-                    new_rbb->status = RBB_BLK_INITED;
-                    new_rbb->buf = tail->buf + tail->size;
-                    new_rbb->size = blk_size;
-                }
-                else
-                {
-                    /* no space */
-                    new_rbb = NULL;
-                }
-            }
-        }
-        else
-        {
-            /* the list is empty */
-            utils_slist_append(&rbb->blk_list, &new_rbb->list);
-            new_rbb->status = RBB_BLK_INITED;
-            new_rbb->buf = rbb->buf;
-            new_rbb->size = blk_size;
-        }
-    }
-    else
-    {
-        new_rbb = NULL;
-    }
-
-    portEXIT_CRITICAL();
-
-    return new_rbb;
-}
-
-/**
- * put a block to ring block buffer object
- *
- * @param block the block
- */
-void utils_rbb_blk_put(utils_rbb_blk_t block)
-{
-    assert(block);
-    assert(block->status == RBB_BLK_INITED);
-
-    block->status = RBB_BLK_PUT;
-}
-
-/**
- * get a block from the ring block buffer object
- *
- * @param rbb ring block buffer object
- *
- * @return != NULL: block
- *            NULL: get failed
- */
-utils_rbb_blk_t utils_rbb_blk_get(utils_rbb_t rbb)
-{
-    utils_rbb_blk_t block = NULL;
-    utils_slist_t *node;
-
-    assert(rbb);
-
-    if (utils_slist_empty(&rbb->blk_list))
-        return 0;
-
-    portENTER_CRITICAL();
-
-    for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))
-    {
-        block = utils_slist_entry(node, struct utils_rbb_blk, list);
-        if (block->status == RBB_BLK_PUT)
-        {
-            block->status = RBB_BLK_GET;
-            goto __exit;
-        }
-    }
-    /* not found */
-    block = NULL;
-
-__exit:
-
-    portEXIT_CRITICAL();
-
-    return block;
-}
-
-/**
- * return the block size
- *
- * @param block the block
- *
- * @return block size
- */
-uint32_t utils_rbb_blk_size(utils_rbb_blk_t block)
-{
-    assert(block);
-
-    return block->size;
-}
-
-/**
- * return the block buffer
- *
- * @param block the block
- *
- * @return block buffer
- */
-uint8_t *utils_rbb_blk_buf(utils_rbb_blk_t block)
-{
-    assert(block);
-
-    return block->buf;
-}
-
-/**
- * free the block
- *
- * @param rbb ring block buffer object
- * @param block the block
- */
-void utils_rbb_blk_free(utils_rbb_t rbb, utils_rbb_blk_t block)
-{
-    assert(rbb);
-    assert(block);
-    assert(block->status != RBB_BLK_UNUSED);
-
-    portENTER_CRITICAL();
-
-    /* remove it on rbb block list */
-    utils_slist_del(&block->list, &rbb->blk_list);
-
-    block->status = RBB_BLK_UNUSED;
-
-    portEXIT_CRITICAL();
-}
-
-/**
- * get a continuous block to queue by given size
- *
- *          tail                         head
- * +------------------+---------------+--------+----------+--------+
- * |      block3      |  empty1       | block1 |  block2  |fragment|
- * +------------------+------------------------+----------+--------+
- *                                    |<-- return_size -->|    |
- *                                    |<--- queue_data_len --->|
- *
- *         tail                          head
- * +------------------+---------------+--------+----------+--------+
- * |      block3      |  empty1       | block1 |  block2  |fragment|
- * +------------------+------------------------+----------+--------+
- *                                    |<-- return_size -->|              out of len(b1+b2+b3)    |
- *                                    |<-------------------- queue_data_len -------------------->|
- *
- * @param rbb ring block buffer object
- * @param queue_data_len The max queue data size, and the return size must less then it.
- * @param queue continuous block queue
- *
- * @return the block queue data total size
- */
-uint32_t utils_rbb_blk_queue_get(utils_rbb_t rbb, uint32_t queue_data_len, utils_rbb_blk_queue_t blk_queue)
-{
-    uint32_t data_total_size = 0;
-    utils_slist_t *node;
-    utils_rbb_blk_t last_block = NULL, block;
-
-    assert(rbb);
-    assert(blk_queue);
-
-    if (utils_slist_empty(&rbb->blk_list))
-        return 0;
-
-    portENTER_CRITICAL();
-
-    for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))
-    {
-        if (!last_block)
-        {
-            last_block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            if (last_block->status == RBB_BLK_PUT)
-            {
-                /* save the first put status block to queue */
-                blk_queue->blocks = last_block;
-                blk_queue->blk_num = 0;
-            }
-            else
-            {
-                /* the first block must be put status */
-                last_block = NULL;
-                continue;
-            }
-        }
-        else
-        {
-            block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            /*
-             * these following conditions will break the loop:
-             * 1. the current block is not put status
-             * 2. the last block and current block is not continuous
-             * 3. the data_total_size will out of range
-             */
-            if (block->status != RBB_BLK_PUT ||
-                last_block->buf > block->buf ||
-                data_total_size + block->size > queue_data_len)
-            {
-                break;
-            }
-            /* backup last block */
-            last_block = block;
-        }
-        /* remove current block */
-        utils_slist_del(&last_block->list, &rbb->blk_list);
-        data_total_size += last_block->size;
-        last_block->status = RBB_BLK_GET;
-        blk_queue->blk_num++;
-    }
-
-    portEXIT_CRITICAL();
-
-    return data_total_size;
-}
-
-/**
- * get all block length on block queue
- *
- * @param blk_queue the block queue
- *
- * @return total length
- */
-uint32_t utils_rbb_blk_queue_len(utils_rbb_blk_queue_t blk_queue)
-{
-    uint32_t i, data_total_size = 0;
-
-    assert(blk_queue);
-
-    for (i = 0; i < blk_queue->blk_num; i++)
-    {
-        data_total_size += blk_queue->blocks[i].size;
-    }
-
-    return data_total_size;
-}
-
-/**
- * return the block queue buffer
- *
- * @param blk_queue the block queue
- *
- * @return block queue buffer
- */
-uint8_t *utils_rbb_blk_queue_buf(utils_rbb_blk_queue_t blk_queue)
-{
-    assert(blk_queue);
-
-    return blk_queue->blocks[0].buf;
-}
-
-/**
- * free the block queue
- *
- * @param rbb ring block buffer object
- * @param blk_queue the block queue
- */
-void utils_rbb_blk_queue_free(utils_rbb_t rbb, utils_rbb_blk_queue_t blk_queue)
-{
-    uint32_t i;
-
-    assert(rbb);
-    assert(blk_queue);
-
-    for (i = 0; i < blk_queue->blk_num; i++)
-    {
-        utils_rbb_blk_free(rbb, &blk_queue->blocks[i]);
-    }
-}
-
-/**
- * The put status and buffer continuous blocks can be make a block queue.
- * This function will return the length which from next can be make block queue.
- *
- * @param rbb ring block buffer object
- *
- * @return the next can be make block queue's length
- */
-uint32_t utils_rbb_next_blk_queue_len(utils_rbb_t rbb)
-{
-    uint32_t data_len = 0;
-    utils_slist_t *node;
-    utils_rbb_blk_t last_block = NULL, block;
-
-    assert(rbb);
-
-    if (utils_slist_empty(&rbb->blk_list))
-        return 0;
-
-    portENTER_CRITICAL();
-
-    for (node = utils_slist_first(&rbb->blk_list); node; node = utils_slist_next(node))
-    {
-        if (!last_block)
-        {
-            last_block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            if (last_block->status != RBB_BLK_PUT)
-            {
-                /* the first block must be put status */
-                last_block = NULL;
-                continue;
-            }
-        }
-        else
-        {
-            block = utils_slist_entry(node, struct utils_rbb_blk, list);
-            /*
-             * these following conditions will break the loop:
-             * 1. the current block is not put status
-             * 2. the last block and current block is not continuous
-             */
-            if (block->status != RBB_BLK_PUT || last_block->buf > block->buf)
-            {
-                break;
-            }
-            /* backup last block */
-            last_block = block;
-        }
-        data_len += last_block->size;
-    }
-
-    portEXIT_CRITICAL();
-
-    return data_len;
-}
-
-/**
- * get the ring block buffer object buffer size
- *
- * @param rbb ring block buffer object
- *
- * @return buffer size
- */
-uint32_t utils_rbb_get_buf_size(utils_rbb_t rbb)
-{
-    assert(rbb);
-
-    return rbb->buf_size;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_sha1.c b/bsp/bl808/m0/libraries/utils/src/utils_sha1.c
deleted file mode 100644
index 74b50940fe..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_sha1.c
+++ /dev/null
@@ -1,355 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-
-#ifdef UTILS_SHA1
-
-
-#include 
-#include 
-#include "iot_import.h"
-#include "iotx_log.h"
-#include "utils_sha1.h"
-
-/* Implementation that should never be optimized out by the compiler */
-static void utils_sha1_zeroize(void *v, size_t n)
-{
-    volatile unsigned char *p = v;
-    while (n--) {
-        *p++ = 0;
-    }
-}
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef IOT_SHA1_GET_UINT32_BE
-#define IOT_SHA1_GET_UINT32_BE(n,b,i)                            \
-    {                                                       \
-        (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
-              | ( (uint32_t) (b)[(i) + 1] << 16 )             \
-              | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
-              | ( (uint32_t) (b)[(i) + 3]       );            \
-    }
-#endif
-
-#ifndef IOT_SHA1_PUT_UINT32_BE
-#define IOT_SHA1_PUT_UINT32_BE(n,b,i)                            \
-    {                                                       \
-        (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
-        (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
-        (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
-        (b)[(i) + 3] = (unsigned char) ( (n)       );       \
-    }
-#endif
-
-void utils_sha1_init(iot_sha1_context *ctx)
-{
-    memset(ctx, 0, sizeof(iot_sha1_context));
-}
-
-void utils_sha1_free(iot_sha1_context *ctx)
-{
-    if (ctx == NULL) {
-        return;
-    }
-
-    utils_sha1_zeroize(ctx, sizeof(iot_sha1_context));
-}
-
-void utils_sha1_clone(iot_sha1_context *dst,
-                      const iot_sha1_context *src)
-{
-    *dst = *src;
-}
-
-/*
- * SHA-1 context setup
- */
-void utils_sha1_starts(iot_sha1_context *ctx)
-{
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    ctx->state[0] = 0x67452301;
-    ctx->state[1] = 0xEFCDAB89;
-    ctx->state[2] = 0x98BADCFE;
-    ctx->state[3] = 0x10325476;
-    ctx->state[4] = 0xC3D2E1F0;
-}
-
-void utils_sha1_process(iot_sha1_context *ctx, const unsigned char data[64])
-{
-    uint32_t temp, W[16], A, B, C, D, E;
-
-    IOT_SHA1_GET_UINT32_BE(W[ 0], data,  0);
-    IOT_SHA1_GET_UINT32_BE(W[ 1], data,  4);
-    IOT_SHA1_GET_UINT32_BE(W[ 2], data,  8);
-    IOT_SHA1_GET_UINT32_BE(W[ 3], data, 12);
-    IOT_SHA1_GET_UINT32_BE(W[ 4], data, 16);
-    IOT_SHA1_GET_UINT32_BE(W[ 5], data, 20);
-    IOT_SHA1_GET_UINT32_BE(W[ 6], data, 24);
-    IOT_SHA1_GET_UINT32_BE(W[ 7], data, 28);
-    IOT_SHA1_GET_UINT32_BE(W[ 8], data, 32);
-    IOT_SHA1_GET_UINT32_BE(W[ 9], data, 36);
-    IOT_SHA1_GET_UINT32_BE(W[10], data, 40);
-    IOT_SHA1_GET_UINT32_BE(W[11], data, 44);
-    IOT_SHA1_GET_UINT32_BE(W[12], data, 48);
-    IOT_SHA1_GET_UINT32_BE(W[13], data, 52);
-    IOT_SHA1_GET_UINT32_BE(W[14], data, 56);
-    IOT_SHA1_GET_UINT32_BE(W[15], data, 60);
-
-#define S(x,n) ((x << n) | ((x & 0xFFFFFFFF) >> (32 - n)))
-
-#define R(t)                                            \
-    (                                                       \
-            temp = W[( t -  3 ) & 0x0F] ^ W[( t - 8 ) & 0x0F] ^ \
-                   W[( t - 14 ) & 0x0F] ^ W[  t       & 0x0F],  \
-            ( W[t & 0x0F] = S(temp,1) )                         \
-    )
-
-#define P(a,b,c,d,e,x)                                  \
-    {                                                       \
-        e += S(a,5) + F(b,c,d) + K + x; b = S(b,30);        \
-    }
-
-    A = ctx->state[0];
-    B = ctx->state[1];
-    C = ctx->state[2];
-    D = ctx->state[3];
-    E = ctx->state[4];
-
-#define F(x,y,z) (z ^ (x & (y ^ z)))
-#define K 0x5A827999
-
-    P(A, B, C, D, E, W[0]);
-    P(E, A, B, C, D, W[1]);
-    P(D, E, A, B, C, W[2]);
-    P(C, D, E, A, B, W[3]);
-    P(B, C, D, E, A, W[4]);
-    P(A, B, C, D, E, W[5]);
-    P(E, A, B, C, D, W[6]);
-    P(D, E, A, B, C, W[7]);
-    P(C, D, E, A, B, W[8]);
-    P(B, C, D, E, A, W[9]);
-    P(A, B, C, D, E, W[10]);
-    P(E, A, B, C, D, W[11]);
-    P(D, E, A, B, C, W[12]);
-    P(C, D, E, A, B, W[13]);
-    P(B, C, D, E, A, W[14]);
-    P(A, B, C, D, E, W[15]);
-    P(E, A, B, C, D, R(16));
-    P(D, E, A, B, C, R(17));
-    P(C, D, E, A, B, R(18));
-    P(B, C, D, E, A, R(19));
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0x6ED9EBA1
-
-    P(A, B, C, D, E, R(20));
-    P(E, A, B, C, D, R(21));
-    P(D, E, A, B, C, R(22));
-    P(C, D, E, A, B, R(23));
-    P(B, C, D, E, A, R(24));
-    P(A, B, C, D, E, R(25));
-    P(E, A, B, C, D, R(26));
-    P(D, E, A, B, C, R(27));
-    P(C, D, E, A, B, R(28));
-    P(B, C, D, E, A, R(29));
-    P(A, B, C, D, E, R(30));
-    P(E, A, B, C, D, R(31));
-    P(D, E, A, B, C, R(32));
-    P(C, D, E, A, B, R(33));
-    P(B, C, D, E, A, R(34));
-    P(A, B, C, D, E, R(35));
-    P(E, A, B, C, D, R(36));
-    P(D, E, A, B, C, R(37));
-    P(C, D, E, A, B, R(38));
-    P(B, C, D, E, A, R(39));
-
-#undef K
-#undef F
-
-#define F(x,y,z) ((x & y) | (z & (x | y)))
-#define K 0x8F1BBCDC
-
-    P(A, B, C, D, E, R(40));
-    P(E, A, B, C, D, R(41));
-    P(D, E, A, B, C, R(42));
-    P(C, D, E, A, B, R(43));
-    P(B, C, D, E, A, R(44));
-    P(A, B, C, D, E, R(45));
-    P(E, A, B, C, D, R(46));
-    P(D, E, A, B, C, R(47));
-    P(C, D, E, A, B, R(48));
-    P(B, C, D, E, A, R(49));
-    P(A, B, C, D, E, R(50));
-    P(E, A, B, C, D, R(51));
-    P(D, E, A, B, C, R(52));
-    P(C, D, E, A, B, R(53));
-    P(B, C, D, E, A, R(54));
-    P(A, B, C, D, E, R(55));
-    P(E, A, B, C, D, R(56));
-    P(D, E, A, B, C, R(57));
-    P(C, D, E, A, B, R(58));
-    P(B, C, D, E, A, R(59));
-
-#undef K
-#undef F
-
-#define F(x,y,z) (x ^ y ^ z)
-#define K 0xCA62C1D6
-
-    P(A, B, C, D, E, R(60));
-    P(E, A, B, C, D, R(61));
-    P(D, E, A, B, C, R(62));
-    P(C, D, E, A, B, R(63));
-    P(B, C, D, E, A, R(64));
-    P(A, B, C, D, E, R(65));
-    P(E, A, B, C, D, R(66));
-    P(D, E, A, B, C, R(67));
-    P(C, D, E, A, B, R(68));
-    P(B, C, D, E, A, R(69));
-    P(A, B, C, D, E, R(70));
-    P(E, A, B, C, D, R(71));
-    P(D, E, A, B, C, R(72));
-    P(C, D, E, A, B, R(73));
-    P(B, C, D, E, A, R(74));
-    P(A, B, C, D, E, R(75));
-    P(E, A, B, C, D, R(76));
-    P(D, E, A, B, C, R(77));
-    P(C, D, E, A, B, R(78));
-    P(B, C, D, E, A, R(79));
-
-#undef K
-#undef F
-
-    ctx->state[0] += A;
-    ctx->state[1] += B;
-    ctx->state[2] += C;
-    ctx->state[3] += D;
-    ctx->state[4] += E;
-}
-
-/*
- * SHA-1 process buffer
- */
-void utils_sha1_update(iot_sha1_context *ctx, const unsigned char *input, size_t ilen)
-{
-    size_t fill;
-    uint32_t left;
-
-    if (ilen == 0) {
-        return;
-    }
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if (ctx->total[0] < (uint32_t) ilen) {
-        ctx->total[1]++;
-    }
-
-    if (left && ilen >= fill) {
-        memcpy((void *)(ctx->buffer + left), input, fill);
-        utils_sha1_process(ctx, ctx->buffer);
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while (ilen >= 64) {
-        utils_sha1_process(ctx, input);
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if (ilen > 0) {
-        memcpy((void *)(ctx->buffer + left), input, ilen);
-    }
-}
-
-static const unsigned char iot_sha1_padding[64] = {
-    0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-/*
- * SHA-1 final digest
- */
-void utils_sha1_finish(iot_sha1_context *ctx, unsigned char output[20])
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = (ctx->total[0] >> 29)
-           | (ctx->total[1] <<  3);
-    low  = (ctx->total[0] <<  3);
-
-    IOT_SHA1_PUT_UINT32_BE(high, msglen, 0);
-    IOT_SHA1_PUT_UINT32_BE(low,  msglen, 4);
-
-    last = ctx->total[0] & 0x3F;
-    padn = (last < 56) ? (56 - last) : (120 - last);
-
-    utils_sha1_update(ctx, iot_sha1_padding, padn);
-    utils_sha1_update(ctx, msglen, 8);
-
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[0], output,  0);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[1], output,  4);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[2], output,  8);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[3], output, 12);
-    IOT_SHA1_PUT_UINT32_BE(ctx->state[4], output, 16);
-}
-
-
-/*
- * output = SHA-1( input buffer )
- */
-void utils_sha1(const unsigned char *input, size_t ilen, unsigned char output[20])
-{
-    iot_sha1_context ctx;
-
-    utils_sha1_init(&ctx);
-    utils_sha1_starts(&ctx);
-    utils_sha1_update(&ctx, input, ilen);
-    utils_sha1_finish(&ctx, output);
-    utils_sha1_free(&ctx);
-}
-
-#endif
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_sha256.c b/bsp/bl808/m0/libraries/utils/src/utils_sha256.c
deleted file mode 100644
index 98b4e2d28d..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_sha256.c
+++ /dev/null
@@ -1,299 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include "utils_sha256.h"
-
-#define SHA256_KEY_IOPAD_SIZE (64)
-#define SHA256_DIGEST_SIZE    (32)
-
-/*
- * 32-bit integer manipulation macros (big endian)
- */
-#ifndef GET_UINT32_BE
-#define GET_UINT32_BE(n,b,i)                            \
-    do {                                                    \
-        (n) = ( (uint32_t) (b)[(i)    ] << 24 )             \
-              | ( (uint32_t) (b)[(i) + 1] << 16 )             \
-              | ( (uint32_t) (b)[(i) + 2] <<  8 )             \
-              | ( (uint32_t) (b)[(i) + 3]       );            \
-    } while( 0 )
-#endif
-
-#ifndef PUT_UINT32_BE
-#define PUT_UINT32_BE(n,b,i)                            \
-    do {                                                    \
-        (b)[(i)    ] = (unsigned char) ( (n) >> 24 );       \
-        (b)[(i) + 1] = (unsigned char) ( (n) >> 16 );       \
-        (b)[(i) + 2] = (unsigned char) ( (n) >>  8 );       \
-        (b)[(i) + 3] = (unsigned char) ( (n)       );       \
-    } while( 0 )
-#endif
-
-
-static void utils_sha256_zeroize(void *v, uint32_t n)
-{
-    volatile unsigned char *p = v;
-    while (n--) {
-        *p++ = 0;
-    }
-}
-void utils_sha256_init(iot_sha256_context *ctx)
-{
-    memset(ctx, 0, sizeof(iot_sha256_context));
-}
-void utils_sha256_free(iot_sha256_context *ctx)
-{
-    if (NULL == ctx) {
-        return;
-    }
-
-    utils_sha256_zeroize(ctx, sizeof(iot_sha256_context));
-}
-void utils_sha256_clone(iot_sha256_context *dst,
-                        const iot_sha256_context *src)
-{
-    *dst = *src;
-}
-void utils_sha256_starts(iot_sha256_context *ctx)
-{
-    int is224 = 0;
-    ctx->total[0] = 0;
-    ctx->total[1] = 0;
-
-    if (is224 == 0) {
-        /* SHA-256 */
-        ctx->state[0] = 0x6A09E667;
-        ctx->state[1] = 0xBB67AE85;
-        ctx->state[2] = 0x3C6EF372;
-        ctx->state[3] = 0xA54FF53A;
-        ctx->state[4] = 0x510E527F;
-        ctx->state[5] = 0x9B05688C;
-        ctx->state[6] = 0x1F83D9AB;
-        ctx->state[7] = 0x5BE0CD19;
-    }
-
-    ctx->is224 = is224;
-}
-
-static const uint32_t K[] = {
-    0x428A2F98, 0x71374491, 0xB5C0FBCF, 0xE9B5DBA5,
-    0x3956C25B, 0x59F111F1, 0x923F82A4, 0xAB1C5ED5,
-    0xD807AA98, 0x12835B01, 0x243185BE, 0x550C7DC3,
-    0x72BE5D74, 0x80DEB1FE, 0x9BDC06A7, 0xC19BF174,
-    0xE49B69C1, 0xEFBE4786, 0x0FC19DC6, 0x240CA1CC,
-    0x2DE92C6F, 0x4A7484AA, 0x5CB0A9DC, 0x76F988DA,
-    0x983E5152, 0xA831C66D, 0xB00327C8, 0xBF597FC7,
-    0xC6E00BF3, 0xD5A79147, 0x06CA6351, 0x14292967,
-    0x27B70A85, 0x2E1B2138, 0x4D2C6DFC, 0x53380D13,
-    0x650A7354, 0x766A0ABB, 0x81C2C92E, 0x92722C85,
-    0xA2BFE8A1, 0xA81A664B, 0xC24B8B70, 0xC76C51A3,
-    0xD192E819, 0xD6990624, 0xF40E3585, 0x106AA070,
-    0x19A4C116, 0x1E376C08, 0x2748774C, 0x34B0BCB5,
-    0x391C0CB3, 0x4ED8AA4A, 0x5B9CCA4F, 0x682E6FF3,
-    0x748F82EE, 0x78A5636F, 0x84C87814, 0x8CC70208,
-    0x90BEFFFA, 0xA4506CEB, 0xBEF9A3F7, 0xC67178F2,
-};
-
-#define  SHR(x,n) ((x & 0xFFFFFFFF) >> n)
-#define ROTR(x,n) (SHR(x,n) | (x << (32 - n)))
-
-#define S0(x) (ROTR(x, 7) ^ ROTR(x,18) ^  SHR(x, 3))
-#define S1(x) (ROTR(x,17) ^ ROTR(x,19) ^  SHR(x,10))
-
-#define S2(x) (ROTR(x, 2) ^ ROTR(x,13) ^ ROTR(x,22))
-#define S3(x) (ROTR(x, 6) ^ ROTR(x,11) ^ ROTR(x,25))
-
-#define F0(x,y,z) ((x & y) | (z & (x | y)))
-#define F1(x,y,z) (z ^ (x & (y ^ z)))
-
-#define R(t)                                    \
-    (                                               \
-            W[t] = S1(W[t -  2]) + W[t -  7] +          \
-                   S0(W[t - 15]) + W[t - 16]            \
-    )
-
-#define P(a,b,c,d,e,f,g,h,x,K)                  \
-    {                                               \
-        temp1 = h + S3(e) + F1(e,f,g) + K + x;      \
-        temp2 = S2(a) + F0(a,b,c);                  \
-        d += temp1; h = temp1 + temp2;              \
-    }
-
-void utils_sha256_process(iot_sha256_context *ctx, const unsigned char data[64])
-{
-    uint32_t temp1, temp2, W[64];
-    uint32_t A[8];
-    unsigned int i;
-
-    for (i = 0; i < 8; i++) {
-        A[i] = ctx->state[i];
-    }
-
-#if defined(INFRA_SHA256_SMALLER)
-    for (i = 0; i < 64; i++) {
-        if (i < 16) {
-            GET_UINT32_BE(W[i], data, 4 * i);
-        } else {
-            R(i);
-        }
-
-        P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i], K[i]);
-
-        temp1 = A[7];
-        A[7] = A[6];
-        A[6] = A[5];
-        A[5] = A[4];
-        A[4] = A[3];
-        A[3] = A[2];
-        A[2] = A[1];
-        A[1] = A[0];
-        A[0] = temp1;
-    }
-#else /* INFRA_SHA256_SMALLER */
-    for (i = 0; i < 16; i++) {
-        GET_UINT32_BE(W[i], data, 4 * i);
-    }
-
-    for (i = 0; i < 16; i += 8) {
-        P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], W[i + 0], K[i + 0]);
-        P(A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], W[i + 1], K[i + 1]);
-        P(A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], W[i + 2], K[i + 2]);
-        P(A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], W[i + 3], K[i + 3]);
-        P(A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], W[i + 4], K[i + 4]);
-        P(A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], W[i + 5], K[i + 5]);
-        P(A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], W[i + 6], K[i + 6]);
-        P(A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], W[i + 7], K[i + 7]);
-    }
-
-    for (i = 16; i < 64; i += 8) {
-        P(A[0], A[1], A[2], A[3], A[4], A[5], A[6], A[7], R(i + 0), K[i + 0]);
-        P(A[7], A[0], A[1], A[2], A[3], A[4], A[5], A[6], R(i + 1), K[i + 1]);
-        P(A[6], A[7], A[0], A[1], A[2], A[3], A[4], A[5], R(i + 2), K[i + 2]);
-        P(A[5], A[6], A[7], A[0], A[1], A[2], A[3], A[4], R(i + 3), K[i + 3]);
-        P(A[4], A[5], A[6], A[7], A[0], A[1], A[2], A[3], R(i + 4), K[i + 4]);
-        P(A[3], A[4], A[5], A[6], A[7], A[0], A[1], A[2], R(i + 5), K[i + 5]);
-        P(A[2], A[3], A[4], A[5], A[6], A[7], A[0], A[1], R(i + 6), K[i + 6]);
-        P(A[1], A[2], A[3], A[4], A[5], A[6], A[7], A[0], R(i + 7), K[i + 7]);
-    }
-#endif /* INFRA_SHA256_SMALLER */
-
-    for (i = 0; i < 8; i++) {
-        ctx->state[i] += A[i];
-    }
-}
-void utils_sha256_update(iot_sha256_context *ctx, const unsigned char *input, uint32_t ilen)
-{
-    size_t fill;
-    uint32_t left;
-
-    if (ilen == 0) {
-        return;
-    }
-
-    left = ctx->total[0] & 0x3F;
-    fill = 64 - left;
-
-    ctx->total[0] += (uint32_t) ilen;
-    ctx->total[0] &= 0xFFFFFFFF;
-
-    if (ctx->total[0] < (uint32_t) ilen) {
-        ctx->total[1]++;
-    }
-
-    if (left && ilen >= fill) {
-        memcpy((void *)(ctx->buffer + left), input, fill);
-        utils_sha256_process(ctx, ctx->buffer);
-        input += fill;
-        ilen  -= fill;
-        left = 0;
-    }
-
-    while (ilen >= 64) {
-        utils_sha256_process(ctx, input);
-        input += 64;
-        ilen  -= 64;
-    }
-
-    if (ilen > 0) {
-        memcpy((void *)(ctx->buffer + left), input, ilen);
-    }
-}
-
-static const unsigned char sha256_padding[64] = {
-    0x80, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
-    0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0
-};
-
-void utils_sha256_finish(iot_sha256_context *ctx, uint8_t output[32])
-{
-    uint32_t last, padn;
-    uint32_t high, low;
-    unsigned char msglen[8];
-
-    high = (ctx->total[0] >> 29)
-           | (ctx->total[1] <<  3);
-    low  = (ctx->total[0] <<  3);
-
-    PUT_UINT32_BE(high, msglen, 0);
-    PUT_UINT32_BE(low,  msglen, 4);
-
-    last = ctx->total[0] & 0x3F;
-    padn = (last < 56) ? (56 - last) : (120 - last);
-
-    utils_sha256_update(ctx, sha256_padding, padn);
-    utils_sha256_update(ctx, msglen, 8);
-
-    PUT_UINT32_BE(ctx->state[0], output,  0);
-    PUT_UINT32_BE(ctx->state[1], output,  4);
-    PUT_UINT32_BE(ctx->state[2], output,  8);
-    PUT_UINT32_BE(ctx->state[3], output, 12);
-    PUT_UINT32_BE(ctx->state[4], output, 16);
-    PUT_UINT32_BE(ctx->state[5], output, 20);
-    PUT_UINT32_BE(ctx->state[6], output, 24);
-
-    if (ctx->is224 == 0) {
-        PUT_UINT32_BE(ctx->state[7], output, 28);
-    }
-}
-
-void utils_sha256(const uint8_t *input, uint32_t ilen, uint8_t output[32])
-{
-    iot_sha256_context ctx;
-
-    utils_sha256_init(&ctx);
-    utils_sha256_starts(&ctx);
-    utils_sha256_update(&ctx, input, ilen);
-    utils_sha256_finish(&ctx, output);
-    utils_sha256_free(&ctx);
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_string.c b/bsp/bl808/m0/libraries/utils/src/utils_string.c
deleted file mode 100644
index e6af56d1bd..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_string.c
+++ /dev/null
@@ -1,427 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-#include 
-#include 
-#include 
-
-static int params_filter(char** params,uint32_t *r)
-{
-    char *p ;
-    uint32_t result=0;
-    uint8_t base=0;
-
-    p = *params;
-
-    if((*p == '0') && ((*(p+1) == 'x') || (*(p+1) == 'X')) ){
-        p = p + 2;
-        base = 16;
-
-    }else{
-        base = 10;
-    }
-
-    while(*p){
-        result *= base;
-        if(*p >= '0' && *p<='9')
-            result += *p-'0';
-        else if(base==10)
-            return -1;
-
-        if(base==16){
-            if(*p >= 'a' && *p<='f')
-                result += *p-'a' + 10;
-            else if(*p >= 'A' && *p<='F')
-                result += *p-'A' + 10;
-
-        }
-        p++;
-    }
-
-    *r = result;
-    return 0;
-
-}
-
-
-void get_bytearray_from_string(char** params, uint8_t *result,int array_size)
-{
-
-    int i = 0;
-    char rand[3];
-
-    for(i=0; i < array_size; i++){
-        strncpy(rand, (const char*)*params, 2);
-        rand[2]='\0';
-        result[i] = strtol(rand, NULL, 16);
-        *params = *params + 2;
-    }
-}
-
-void get_uint8_from_string(char** params, uint8_t *result)
-{
-    uint32_t p = 0;
-    int state=0;
-
-    state = params_filter(params,&p);
-    if(!state){
-        *result = p & 0xff;
-    }else
-        *result = 0;
-}
-
-void get_uint16_from_string(char** params, uint16_t *result)
-{
-    uint32_t p = 0;
-    int state=0;
-
-    state = params_filter(params,&p);
-    if(!state){
-        *result = p & 0xffff;
-    }else
-        *result = 0;
-}
-
-void get_uint32_from_string(char** params, uint32_t *result)
-{
-    uint32_t p = 0;
-    int state=0;
-
-    state = params_filter(params,&p);
-    if(!state){
-        *result = p;
-    }else
-        *result = 0;
-}
-
-void utils_parse_number(const char *str, char sep, uint8_t *buf, int buflen, int base)
-{
-  int i;
-  for (i = 0; i < buflen; i++) {
-    buf[i] = (uint8_t)strtol(str, NULL, base);
-    str = strchr(str, sep);
-    if (str == NULL || *str == '\0') {
-      break;
-    }
-    str++;
-  }
-}
-
-void utils_parse_number_adv(const char *str, char sep, uint8_t *buf, int buflen, int base, int *count)
-{
-  int i;
-
-  for (i = 0; i < buflen; i++) {
-    buf[i] = (uint8_t)strtol(str, NULL, base);
-    str = strchr(str, sep);
-    if (str == NULL || *str == '\0') {
-      break;
-    }
-    str++;
-  }
-  *count = (i + 1);
-}
-
-
-unsigned long long convert_arrayToU64(uint8_t* inputArray)
-{
-    unsigned long long result = 0;
-    for(uint8_t i = 0; i < 8; i++)
-    {
-        result <<= 8;
-        result |= (unsigned long long)inputArray[7-i];
-    }
-
-    return result;
-}
-
-void convert_u64ToArray(unsigned long long inputU64, uint8_t result[8])
-{
-    for(int i = 0; i < 8; i++)
-    {
-        result[i] = inputU64>>(i*8);
-    }
-}
-
-void utils_memcpy8(void *dst, void *src, size_t len)
-{
-    uint8_t *d = (uint8_t *)dst;
-    uint8_t *s = (uint8_t *)src;
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memcpy16(void *dst, void *src, size_t len)
-{
-    uint16_t *d = (uint16_t *)dst;
-    uint16_t *s = (uint16_t *)src;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memcpy32(void *dst, void *src, size_t len)
-{
-    uint32_t *d = (uint32_t *)dst;
-    uint32_t *s = (uint32_t *)src;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memcpy64(void *dst, void *src, size_t len)
-{
-    uint64_t *d = (uint64_t *)dst;
-    uint64_t *s = (uint64_t *)src;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        *d++ = *s++;
-    }
-}
-
-void utils_memset8(void *src, uint8_t n, size_t len)
-{
-    uint8_t *s = (uint8_t *)src;
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset16(void *src, uint16_t n, size_t len)
-{
-    uint16_t *s = (uint16_t *)src;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset32(void *src, uint32_t n, size_t len)
-{
-    uint32_t *s = (uint32_t *)src;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset64(void *src, uint64_t n, size_t len)
-{
-    uint64_t *s = (uint64_t *)src;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        *s++ = n;
-    }
-}
-
-void utils_memset8_with_seq(void *src, uint8_t seq, size_t len)
-{
-    uint8_t *s = (uint8_t *)src;
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memset16_with_seq(void *src, uint16_t seq, size_t len)
-{
-    uint16_t *s = (uint16_t *)src;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memset32_with_seq(void *src, uint32_t seq, size_t len)
-{
-    uint32_t *s = (uint32_t *)src;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memset64_with_seq(void *src, uint64_t seq, size_t len)
-{
-    uint64_t *s = (uint64_t *)src;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        *s++ = (seq++);
-    }
-}
-
-void utils_memdrain8(void *src, size_t len)
-{
-    volatile uint8_t *s = (uint8_t *)src;
-    uint8_t tmp;
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void utils_memdrain16(void *src, size_t len)
-{
-    volatile uint16_t *s = (uint16_t *)src;
-    uint16_t tmp;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void utils_memdrain32(void *src, size_t len)
-{
-    volatile uint32_t *s = (uint32_t *)src;
-    uint32_t tmp;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void utils_memdrain64(void *src, size_t len)
-{
-    volatile uint64_t *s = (uint64_t *)src;
-    uint64_t tmp;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        tmp = *s++;
-    }
-
-    (void)tmp;
-}
-
-void * utils_memdrain8_with_check(void *src, size_t len, uint8_t seq)
-{
-    volatile uint8_t *s = (uint8_t *)src;
-    uint8_t tmp;
-
-    (void)tmp;
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint8_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
-
-void * utils_memdrain16_with_check(void *src, size_t len, uint16_t seq)
-{
-    volatile uint16_t *s = (uint16_t *)src;
-    uint16_t tmp;
-    (void)tmp;
-
-    len >>= 1;//convert to half words
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint16_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
-
-void * utils_memdrain32_with_check(void *src, size_t len, uint32_t seq)
-{
-    volatile uint32_t *s = (uint32_t *)src;
-    uint32_t tmp;
-    (void)tmp;
-
-    len >>= 2;//convert to words
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint32_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
-
-void * utils_memdrain64_with_check(void *src, size_t len, uint64_t seq)
-{
-    volatile uint64_t *s = (uint64_t *)src;
-    uint64_t tmp;
-    (void)tmp;
-
-    len >>= 3;//convert to two words
-
-    while (len--) {
-        tmp = *s++;
-        if((seq++) != tmp){
-            return (uint64_t *)s-1;
-        }
-    }
-
-    return NULL;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_time.c b/bsp/bl808/m0/libraries/utils/src/utils_time.c
deleted file mode 100644
index 0e8dd1dd73..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_time.c
+++ /dev/null
@@ -1,96 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include 
-#include 
-//Thu=4, Fri=5, Sat=6, Sun=0, Mon=1, Tue=2, Wed=3
-
-int utils_time_date_from_epoch(unsigned int epoch, utils_time_date_t *date)
-{
-    int i;
-    unsigned short temp_days;
-    unsigned char month_days[12]={31,28,31,30,31,30,31,31,30,31,30,31};
-    unsigned char week_days[7] = {4,5,6,0,1,2,3};
-
-    date->leap_days = 0;
-    date->leap_year_ind = 0;
-
-    // Add or substract time zone here.
-    //epoch += 19800; //GMT +5:30 = +19800 seconds
-
-    date->ntp_second = epoch%60;
-    epoch /= 60;
-    date->ntp_minute = epoch%60;
-    epoch /= 60;
-    date->ntp_hour  = epoch%24;
-    epoch /= 24;
-
-    date->days_since_epoch = epoch;      //number of days since epoch
-    date->ntp_week_day = week_days[date->days_since_epoch%7];  //Calculating WeekDay
-
-    date->ntp_year = 1970 + (date->days_since_epoch/365); // ball parking year, may not be accurate!
-    for (i = 1972, date->leap_days = 0; i < date->ntp_year; i+=4) {
-        // Calculating number of leap days since epoch/1970
-        if(((i%4==0) && (i%100!=0)) || (i%400==0)) {
-            date->leap_days++;
-        }
-    }
-
-    date->ntp_year = 1970 + ((date->days_since_epoch - date->leap_days)/365); // Calculating accurate current year by (days_since_epoch - extra leap days)
-    if (((date->ntp_year%4==0) && (date->ntp_year%100!=0)) || (date->ntp_year%400==0))  {
-        month_days[1]=29;     //February = 29 days for leap years
-        date->leap_year_ind = 1;    //if current year is leap, set indicator to 1
-    } else {
-        month_days[1]=28; //February = 28 days for non-leap years
-        date->leap_year_ind = 0;    //if current year is leap, set indicator to 1
-    }
-    for (i = 1972, date->leap_days = 0; i < date->ntp_year; i+=4) {
-        // Calculating number of leap days since epoch/1970
-        if(((i%4==0) && (i%100!=0)) || (i%400==0)) {
-            date->leap_days++;
-        }
-    }
-    date->day_of_year = date->days_since_epoch - date->leap_days - (date->ntp_year - 1970) * 365 + 1;
-
-
-    temp_days = 0;
-
-    for (date->ntp_month = 0; date->ntp_month <= 11; date->ntp_month++) {
-        //calculating current Month
-        if (date->day_of_year <= temp_days) {
-            break;
-        }
-        temp_days = temp_days + month_days[date->ntp_month];
-    }
-
-    temp_days = temp_days - month_days[date->ntp_month-1]; //calculating current Date
-    date->ntp_date = date->day_of_year - temp_days;
-
-    return 0;
-}
diff --git a/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c b/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c
deleted file mode 100644
index 0ec23c4daa..0000000000
--- a/bsp/bl808/m0/libraries/utils/src/utils_tlv_bl.c
+++ /dev/null
@@ -1,184 +0,0 @@
-/*
- * Copyright (c) 2016-2022 Bouffalolab.
- *
- * This file is part of
- *     *** Bouffalolab Software Dev Kit ***
- *      (see www.bouffalolab.com).
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *   1. Redistributions of source code must retain the above copyright notice,
- *      this list of conditions and the following disclaimer.
- *   2. Redistributions in binary form must reproduce the above copyright notice,
- *      this list of conditions and the following disclaimer in the documentation
- *      and/or other materials provided with the distribution.
- *   3. Neither the name of Bouffalo Lab nor the names of its contributors
- *      may be used to endorse or promote products derived from this software
- *      without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
- * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
- * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
- * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
- * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
- * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
- * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
- * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
- * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
-#include "utils_tlv_bl.h"
-
-int utils_tlv_bl_pack_bool(uint32_t *buf, int buf_sz, bool val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_BOOLEAN) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *buf = val;//XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;
-}
-
-int utils_tlv_bl_pack_uint32(uint32_t *buf, int buf_sz, uint32_t val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_UINT32) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *buf = val;//XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_UINT32;
-}
-
-int utils_tlv_bl_unpack_bool(uint32_t *buf, int buf_sz, bool *val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_BOOLEAN) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *val = (*buf) ? true : false;// XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;
-}
-
-int utils_tlv_bl_unpack_uint32(uint32_t *buf, int buf_sz, uint32_t *val)
-{
-    if (buf_sz < CFG_ELEMENT_TYPE_SIZE_UINT32) {
-        return UTILS_TLV_BL_ERROR_CODE_BUF_TOO_SMALL;
-    }
-    *val = (*buf);//XXX caution for unaligned access
-
-    return CFG_ELEMENT_TYPE_SIZE_BOOLEAN;
-}
-
-int utils_tlv_bl_pack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1)
-{
-    int ret = UTILS_TLV_BL_ERROR_CODE_UNKOWN;
-
-    switch (type) {
-        case CFG_ELEMENT_TYPE_BOOLEAN:
-        {
-            ret = utils_tlv_bl_pack_bool(buf, buf_sz, *(bool*)arg1 ? true : false);
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT32:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT32:
-        {
-            ret = utils_tlv_bl_pack_uint32(buf, buf_sz, *(uint32_t*)arg1);
-        }
-        break;
-        case CFG_ELEMENT_TYPE_STRING:
-        {
-            //TODO
-        }
-        break;
-        default:
-        {
-            /*empty*/
-        }
-    }
-
-    return ret;
-}
-
-int utils_tlv_bl_unpack_auto(uint32_t *buf, int buf_sz, uint16_t type, void *arg1)
-{
-    int ret = UTILS_TLV_BL_ERROR_CODE_UNKOWN;
-
-    switch (type) {
-        case CFG_ELEMENT_TYPE_BOOLEAN:
-        {
-            bool val = true;
-
-            ret = utils_tlv_bl_unpack_bool(buf, buf_sz, &val);
-            *(bool*)arg1 = val;
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT8:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT16:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_SINT32:
-        {
-            //TODO
-        }
-        break;
-        case CFG_ELEMENT_TYPE_UINT32:
-        {
-            uint32_t val = 0;
-
-            ret = utils_tlv_bl_unpack_uint32(buf, buf_sz, &val);
-            *(uint32_t*)arg1 = val;
-        }
-        break;
-        case CFG_ELEMENT_TYPE_STRING:
-        {
-            //TODO
-        }
-        break;
-        default:
-        {
-            /*empty*/
-        }
-    }
-
-    return ret;
-}
diff --git a/bsp/bl808/m0/link_stacksize.lds b/bsp/bl808/m0/link_stacksize.lds
deleted file mode 100644
index 28438c7da1..0000000000
--- a/bsp/bl808/m0/link_stacksize.lds
+++ /dev/null
@@ -1 +0,0 @@
-__STACKSIZE__ = 4096;
diff --git a/bsp/bouffalo_lab/.gitignore b/bsp/bouffalo_lab/.gitignore
new file mode 100755
index 0000000000..9b96be28e1
--- /dev/null
+++ b/bsp/bouffalo_lab/.gitignore
@@ -0,0 +1,8 @@
+*.ota
+*.xz
+*.xz.ota
+*.bin
+*.asm
+*.exe
+*-ubuntu
+*-macos
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/README.md b/bsp/bouffalo_lab/README.md
new file mode 100755
index 0000000000..e0d8600961
--- /dev/null
+++ b/bsp/bouffalo_lab/README.md
@@ -0,0 +1,193 @@
+# bouffalo_lab bsp
+
+## 1. 简介
+
+bouffalo_lab bsp针对bouffalo_lab的系列AIoT芯片，采用bouffalo_lab最新**LHAL** 驱动库，驱动库与[bl_mcu_sdk](https://github.com/bouffalolab/bl_mcu_sdk) 代码同步，当前commitid:`47c662afae69309fd49d2721b5c9b93219a91af7`
+
+目前支持以下芯片：
+
+|      | 芯片型号                 | 内核                                     |
+| ---- | :----------------------- | ---------------------------------------- |
+| 1    | bl60x(bl602/bl604)       | RISC-V SiFive E24                        |
+| 2    | bl70x(bl702/bl704/bl706) | RISC-V SiFive E24                        |
+| 3    | bl61x(bl616/bl618)       | RISC-V T-Head E907                       |
+| 4    | bl808                    | RISC-V T-Head E902(lp)+E907(m0)+C906(d0) |
+
+**LHAL** 是博流为统一通用外设接口而设计的驱动库，代码精炼并且支持博流所有系列芯片。
+
+|   外设   | BL602/BL604 | BL702/BL704/BL706 | BL616/BL618 | BL808 |
+| :------: | :---------: | :---------------: | :---------: | :---: |
+|   ADC    |      ○      |         √         |      √      |   ○   |
+|   CAM    |      -      |         ×         |      ×      |   ×   |
+|   CKS    |      ○      |         √         |      √      |   ○   |
+|   DAC    |      ○      |         √         |      √      |   ○   |
+|   DMA    |      ○      |         √         |      √      |   √   |
+|  EFUSE   |      ×      |         √         |      √      |   √   |
+|   EMAC   |      -      |         √         |      √      |   √   |
+|  FLASH   |      √      |         √         |      √      |   √   |
+|   GPIO   |      ○      |         √         |      √      |   √   |
+|   I2C    |      ○      |         √         |      √      |   ○   |
+|   I2S    |      ○      |         ○         |      √      |   ○   |
+|    IR    |      ○      |         √         |      √      |   ○   |
+|  MJPEG   |      ×      |         ×         |      √      |   √   |
+|  PWM_v1  |      ○      |         √         |      -      |   -   |
+|  PWM_v2  |      -      |         -         |      √      |   √   |
+|   RTC    |      ○      |         √         |      √      |   √   |
+| SEC_AES  |      ○      |         √         |      √      |   √   |
+| SEC_SHA  |      ○      |         √         |      √      |   √   |
+| SEC_TRNG |      ○      |         √         |      √      |   √   |
+| SEC_PKA  |      ○      |         √         |      √      |   √   |
+|   SPI    |      ○      |         √         |      √      |   √   |
+|  TIMER   |      ○      |         √         |      √      |   √   |
+|   UART   |      √      |         √         |      √      |   √   |
+|  USB_v1  |      -      |         √         |      -      |   -   |
+|  USB_v2  |      -      |         -         |      √      |   √   |
+|   WDG    |      ○      |         √         |      √      |   ○   |
+
+备注：**√** 表示已支持；**×** 表示未支持；**○** 表示已支持但未测试；**-** 表示没有该外设。
+
+
+
+## 2.  环境搭建及编译
+
+bl60x/bl70x/bl61x可在对应芯片直接编译；bl808是多核异构架构，分为m0、lp、d0（适配中，敬请期待），每个核需要单独编译并烧录到对应的位置。
+
+以下操作以bl61x为例，其他芯片操作类同。
+
+### 2.1. 下载
+
+请至对应下载链接下载芯片的工具链
+
+| 芯片型号    | 下载地址                                                     |
+| ----------- | ------------------------------------------------------------ |
+| bl60x/bl70x | [Linux](https://gitee.com/bouffalolab/toolchain_gcc_sifive_linux)/[windows](https://gitee.com/bouffalolab/toolchain_gcc_sifive_windows) |
+| bl61x/bl808 | [T-Head官网](https://occ.t-head.cn/community/download?id=4073475960903634944)或[Linux](https://gitee.com/bouffalolab/linuxtoolchain_gcc_t-head)/[windows](https://gitee.com/bouffalolab/toolchain_gcc_t-head_windows) |
+
+### 2.2. 设置
+
+Windows下请使用使用[env工具][1]，使用命令 `tar -xvf Xuantie-900-gcc-elf-newlib-mingw-V2.6.1-20220906.tar.gz` 解压交叉编译器，使用Windows下解压工具直接解压可能出现Windows下编译错误。
+
+在`rtconfig.py`中将risc-v工具链的本地路径加入 `EXEC_PATH` 或通过 `RTT_EXEC_PATH` 环境变量指定路径
+
+Windows：
+
+```
+set RTT_EXEC_PATH=C:\Users\xxxx\Downloads\Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1\bin
+```
+
+Linux:
+
+```
+export RTT_EXEC_PATH=/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin
+```
+
+### 2.3. 编译
+
+Windows下推荐使用[env工具][1]，在console下进入bsp/bouffalo_lab/bl61x目录中，运行：
+
+    cd bsp/bouffalo_lab/bl61x
+    menuconfig
+    pkgs --update
+
+如果在Linux平台下，可以先执行：
+
+    scons --menuconfig
+
+它会自动下载env相关脚本到~/.env目录，然后执行
+
+    source ~/.env/env.sh
+    
+    cd bsp/bouffalo_lab/bl61x
+    pkgs --update
+
+更新完软件包后，执行 `scons -j10` 或 `scons -j10 --verbose` 来编译这个板级支持包。或者通过 `scons --exec-path="GCC工具链路径"` 命令，在指定工具链位置的同时直接编译。
+
+如果编译正确无误，会产生rtthread.elf、rtthread.bin文件；编译完成后自动调用`libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc`对rtthread.bin进行打包处理以用于后续`bouffalo_flash_cube`工具烧录。
+
+脚本会自动采用curl命令行方式下载`bflb_fw_post_proc`，如自动下载失败，可采用手工方式下载对应操作系统文件后保存至`libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc`
+
+[windows](https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe)
+
+[Linux](https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu)
+
+[macos](https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos)
+
+## 3. 下载烧录
+
+### 3.1. GUI方式下载
+
+当前bsp必须使用`bouffalo_flash_cube-1.0.4](https://pan.baidu.com/s/1eG9pkxf3riAqQAu9aXiOjw?pwd=miv1)工具进行烧录，否则无法正常运行。
+
+1. 连接好串口并在工具上选择对应的串口号
+
+2. 打开对应芯片文件夹下的flash_prog_cfg.ini文件
+
+3. 按住开发板上的boot按钮后重新上电，进入下载状态
+
+4. 点击"Download"开始下载
+
+![Flash Download](figures/bouffalo_flash_cube.jpg)
+
+### 3.2. 命令行下载
+
+或者可使用`bsp/bouffalo_lab`目录下的`bouffalo_flash_cube.sh`脚本通过命令行下载，输入`./`bouffalo_flash_cube.sh bl616 /dev/ttyUSB1`，使用前先确定脚本中bouffalo_flash_cube工具路径，需手工修改为工具所在目录。
+
+其中：
+
+- bl616：芯片名称
+- /dev/ttyUSB1：下载串口号，linux下为/dev/ttyUSBx或/dev/ttyACMx，windows下为COMx
+
+
+
+### 4.  运行
+
+如果编译 & 烧写无误，当复位设备后，会在串口上看到RT-Thread的启动logo信息：
+
+![terminal](figures/rt-thread.jpg)
+
+
+
+## 5. 支持开发板列表
+
+|       | 开发板型号             |
+| ----- | ---------------------- |
+| bl602 | BL602-IoT-3S/BL-HWC-G1 |
+| bl702 | Maix Zero Sense        |
+| bl616 | M0S Dock               |
+| bl808 | M1s Dock               |
+
+
+
+## 6. 驱动支持列表
+
+| 驱动 | 支持情况 | 备注              |
+| :--- | :------- | :---------------- |
+| UART | 支持     | 默认波特率2000000 |
+| GPIO | 支持     |                   |
+| I2C  | 开发中   |                   |
+| SPI  | 开发中   |                   |
+
+
+
+## 7. 联系人信息
+
+维护人：[flyingcys](https://github.com/flyingcys)
+
+
+
+## 8. 参考
+
+* 芯片[datasheet][2]
+
+  [1]: https://www.rt-thread.org/page/download.html
+  [2]: https://github.com/bouffalolab/bl_docs
+
+
+
+## 9. FAQ
+
+|      | M1s Dock                                                     |
+| ---- | :----------------------------------------------------------- |
+| 1    | 在 windows 环境下，通过 UART 接口将开发板连接至电脑时，仅能识别到两个 USB converter 设备，但是识别不到对应的串口设备。  
进入到设备管理器中，右击对应的 USB converter 设备，进入到属性中的高级设置，钩选 vcp 选项，刷新后即可看到对应的串口设备。
 也可通过安装以下驱动解决问题： https://dl.sipeed.com/shareURL/MAIX/tools/ftdi_vcp_driver |
+| 2    | 使用 TypeC 数据线将电脑与板子的 UART 口连接起来，此时电脑上会出现两个串口 （如果出现鼠标不能动的现象请拔掉 USB 并且查看 [更新板载 bl702 固件](https://wiki.sipeed.com/hardware/zh/maix/m1s/other/start.html#给板载-bl702-进行烧录) 相关内容来修复问题)。 |
+
diff --git a/bsp/bouffalo_lab/bl60x/.config b/bsp/bouffalo_lab/bl60x/.config
new file mode 100755
index 0000000000..a62ef1cdef
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/.config
@@ -0,0 +1,1000 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_BSP_USING_BL60X=y
+CONFIG_BSP_USING_ROMAPI=y
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# General Purpose UARTs
+#
+CONFIG_BSP_USING_UART0=y
+# CONFIG_UART0_TX_USING_GPIO14 is not set
+CONFIG_UART0_TX_USING_GPIO16=y
+# CONFIG_UART0_TX_USING_GPIO21 is not set
+CONFIG_UART0_RX_USING_GPIO7=y
+# CONFIG_UART0_RX_USING_GPIO15 is not set
+# CONFIG_UART0_RX_USING_GPIO22 is not set
+# CONFIG_UART0_RX_USING_GPIO23 is not set
+CONFIG_BSP_USING_UART1=y
+CONFIG_UART1_TX_USING_GPIO4=y
+# CONFIG_UART1_TX_USING_GPIO16 is not set
+# CONFIG_UART1_TX_USING_GPIO18 is not set
+# CONFIG_UART1_TX_USING_GPIO26 is not set
+CONFIG_UART1_RX_USING_GPIO3=y
+# CONFIG_UART1_RX_USING_GPIO5 is not set
+# CONFIG_UART1_RX_USING_GPIO17 is not set
+# CONFIG_UART1_RX_USING_GPIO19 is not set
+# CONFIG_UART1_RX_USING_GPIO27 is not set
diff --git a/bsp/bl808/m0/Kconfig b/bsp/bouffalo_lab/bl60x/Kconfig
old mode 100644
new mode 100755
similarity index 68%
rename from bsp/bl808/m0/Kconfig
rename to bsp/bouffalo_lab/bl60x/Kconfig
index eaacad85ce..c6ee6e58f8
--- a/bsp/bl808/m0/Kconfig
+++ b/bsp/bouffalo_lab/bl60x/Kconfig
@@ -15,6 +15,12 @@ config PKGS_DIR
     option env="PKGS_ROOT"
     default "packages"
 
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../libraries"
+
 source "$RTT_DIR/Kconfig"
 source "$PKGS_DIR/Kconfig"
-source "drivers/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"
diff --git a/bsp/bl808/m0/SConscript b/bsp/bouffalo_lab/bl60x/SConscript
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/SConscript
rename to bsp/bouffalo_lab/bl60x/SConscript
diff --git a/bsp/bouffalo_lab/bl60x/SConstruct b/bsp/bouffalo_lab/bl60x/SConstruct
new file mode 100755
index 0000000000..da9ba9a91a
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/SConstruct
@@ -0,0 +1,46 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
+
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
+
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/bl808/m0/applications/SConscript b/bsp/bouffalo_lab/bl60x/applications/SConscript
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/applications/SConscript
rename to bsp/bouffalo_lab/bl60x/applications/SConscript
diff --git a/bsp/bouffalo_lab/bl60x/applications/main.c b/bsp/bouffalo_lab/bl60x/applications/main.c
new file mode 100644
index 0000000000..55495688b0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/applications/main.c
@@ -0,0 +1,19 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/25     flyingcys    first version
+ */
+
+#include 
+#include 
+
+int main(void)
+{
+    rt_kprintf("Hello, RISC-V!\n");
+
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/bl60x/board/Kconfig b/bsp/bouffalo_lab/bl60x/board/Kconfig
new file mode 100755
index 0000000000..b25faf2847
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/Kconfig
@@ -0,0 +1,12 @@
+config BSP_USING_BL60X
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BSP_USING_ROMAPI
+    default y
+
+config BSP_USING_ROMAPI
+    bool 
+    default y
diff --git a/bsp/bouffalo_lab/bl60x/board/SConscript b/bsp/bouffalo_lab/bl60x/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl60x/board/board.c b/bsp/bouffalo_lab/bl60x/board/board.c
new file mode 100644
index 0000000000..413a39bc32
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/board.c
@@ -0,0 +1,84 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+static void system_clock_init(void)
+{
+    GLB_Set_System_CLK(GLB_PLL_XTAL_40M, GLB_SYS_CLK_PLL192M);
+    GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 95);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_160M, 0);
+    GLB_Set_SPI_CLK(ENABLE, 0);
+    GLB_Set_I2C_CLK(ENABLE, 0);
+
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E);
+}
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl60x/board/board.h b/bsp/bouffalo_lab/bl60x/board/board.h
new file mode 100644
index 0000000000..d58d575f33
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/board.h
@@ -0,0 +1,33 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl602_glb.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_debug_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..28ee214554bd61021c5c43dfd93e51d43ccec6e3
GIT binary patch
literal 42096
zcmeFadt4Mp_BdMIGu=IdC}4v?7URGODw`N&RFbSAJva|QMPl%k;6`kSaTDYFwO`$U
zGd(yeB54sxbbZAa-^3^roy4qRKwcVy=qg~=B$^S3$(ljKLygGq)bxyCcE9_*_kQl@
z{&U3-boZ&MQ>RXyI(6#QsWQQkl1dd1!Z7jsShQsGlo*jjh&PjHNvi+q
z-~e(6OXPGH0Zd#=QcE^3j`=0RKSsPwl6)?SisvlZMaC@gk3lXjn{>q-S>@t(DV9WX
zw{rA^!G&gz!!;1Qe#_+TTBLsb`~RE=+JK14s0z9|+HB86YC`Yg&
zOROWUv1VSN{f`UD!q{q8>O!VeKe#F`3#nO3_|=8#6Ro=AT$GMZx;=BwD;Hi#c(wG^
zi1c^U$yrgtR$WHM+H5JWzT1WT4JPAI6l!=%v7XseRBM#z%5I8YKHY{FWGr7Rw(kUkgB;!iC!6
zF9?4Wq?RIvNY-DY-eP@yIi7#7AI2A9IU|TQT|L4EHPMd3QrTmnNMOS1U8(g%iFw`)
zss5?}sQ-CE7haa5PZnIMyB6i>13WZWJ?J>;$%URP8?JD1F^dJG^U03e9@^!=@3FX^
z6v4$U%n)==CG}4!O;164N2>`rQb);AjxNiK$rtL=%s*x`Pt@{DwxjRO;(BeeX`c^@
zvb-WlTvJ^mPJ6HnaG`}Ur|nX@x3#*j@%wd5IB>g-iO!;7p?Ugt`MFe5C-$sp0GvVA!z
zz?_SIEF^n<@IPVbn4)Nv_
z1tA&CGboC3Opnr~~szyUeZH~@94`}-n&Qp1gGzS=<$Gz14zCYwY4f#F19U;??LLy+7P0Ar`)G^t(&@T#k
zqW^%=ikOg9@zLg4HwB}5|E*+dk}H*ayDu))FsqRdX!rH->*+&fK#Slr+>3j5)XeiH
zV-9h-M?-x8cw<6v&GCh<)a>}@Zf@1bwUdYyHVofW=t7Qn2I;kiiT)9V5?#CMO-3zA
z8O2*jhgzcDGW7^+F=d->EaB%{V{I8x$3zk2DzxwEGl>;BitF
zyDHM%I*N-N7YckKV?qSo7lpINI(?{y@PmX0OIw;?j5a$_cY|}i+^x|uK4Emu(|9c6
zu|3-t|IHo?&E6XwRft{cW)@Ey%4rDSgNR!)vWJU(@tu3In
zor@YDP>{N2>e_6+V;?CRI(u@A-NAf8CkbUBue%JC6&N*YM9!j`2Wzu)jLl^lrW0w_
zH6vM~0!0_8VWPNUkKS66%ZoK=ZMMMd&9^_eR2H3!%bRK_Bv7{8PL3_iB{GE2YZTMm
ziSh7kC*=OudYbLxN`+h-z`v)E$MK+jWT&1J7b^&`mgMZpA9}AeZwZ5D;rnN@bYtr-^QThxf-Dbu?j>|yZAfD
zk%qcP$n+FaXYWS>eXWddx5GO_2#kjA;G9X02kzDwaVb2jty(nY?6fnl)Y1(R7o#pD
z*QeC|v3gFW#^)F+S$}-p$PN6m62wmE=vniMHWS-d(*#y|gcSQBa!sIUmOuO4L6%7+
zc~h&LU#ch6r~`>i5Gu8@mQWNgn2a=P{)MOeA^yMgW7LR3rKu5V@1~J6Zzs)3PMAtk!z+qiyQCD
z4k&<@C{&dV&pd90ItEmdtlufgp
z$Nc!v23k-`b+^&Hq9KC+xtfNS)BJ#j0sKF!Du6pyHS72@yDrIV=PE
zF_(EC=1IQYNbE(;@EwU39bIachq8C3}uOsZ69fnx`9pip{h$
zq~RX>#&C4V@ENo%m2vtuJm8ygy@=tNhCx6J;~dm*N48&qSW_Yj_&&-4GML+fY*Yg>
zRZ-~fHGXOv;{V==zJQSgqk52HKuN9!
zZq-0>*>HsM@_(fUW^B43+=ws9{eInDn;Xj$3i5=dBo}%gTBgok0g~H2$eCRKKxDdl
zfC3n$Us%Q#^5d@}%Bab0{oP63<#8O>7B}Jv{
zcG&oK17KcG2=v`DfgWS;t;t5+;hd+BKd@1a9O$+2jp%T0d?BlVnvJ}!5!sj{oFIZOkRmA{wC;cv8jj)yGMw336$mbV<>B>pDKOQ5}fCqbD?qPPdL#XH(Fg^Dw@F
z0<@f<=*#x*X?zft;1CpU#GEQOVBXw3CXJ^mcTZ3H3}j4RZkTkkJ9O63-G=$c5@@aE
z^0B>sJ`dI$1*`OL>gZbu>fzTCWCyepz%u2)^5oPJM-$XT%M;X5=M&UV5#s?qp87J{
zBGTFf7-5`3!J4%b##VR4iwxqTEqwa{#L@ugd=*7U@EVC5VN#WAWkYkcgdS?qt<6@K
z>`q>rZ5KYh$>wS==D_Ss#j+IgKb{+IV4H%Gu))T(aX0hV46+&Tpf#Ogrvy5HaTe@{
z8Ha^=siY8>d~5-1A5T#)Y^t({Y2!fY^0!*az@$A)
zSb4ghT{j5L(5i=1#PK3i4TB;ecY1k<*3<|XrrBX0>m<{(d>5^x=E5k?9-JSPJCHt6
zq*hTx0IlBKfl3Rl#?|M;Q-n7JqkRA(#C3}7K&^$*n4p(#HONAe_RxXlX?j)>j8fe-
zo!DxEksLvnZcQtf4F{z(T?Q%Qv`>-E(n9j98+-!GZI&OnLd)19wZ9WNZ`Ay{@+A#Z
zqdify`aGVm8LiDiYuTph$d=1!L(0?2F(r1~wuN0}1QSvol9aCBL*qJe+rS2bwteBL
z&(s)+(zNXKPmzY{BKcb_WJvj=tz&6}zq$ao?T|6Zu2K8|^4Y@8C}$g|qvCwrcAR?J
z2v(G8^?8`r{FRWaiL=oSTw1v}Z92kvg7Pu-0+VB(p@-RjVGA8H31oRqi+r7N%Yn46lBRXLT%HLMb8asQUi}=j_sD46h(MIFu@vIPp*41dJ7KCS>ky|OSGH@!-)*!;z
zJ?PehZN`g6O3!z+pr#tUl3JS`@>1ATA|T={T^DsGxi+PGO69bQXfwa63$1>spe80s
zr1W$KmG`2M$yzHvvMW(G>!YJ1ipBNvZ1MEn9^cfEv@nkEY(^o8X^DJS3yI|g>bTW9
z8sx>1&IKm2MY$+l$65v<|5{0AKw=!!{+Jnd8qQ+q<@Eeb{H;dPonME0AdQPJQV*9C
zCa|s8A`8O#*7RDMYp
zN{3a0obGSr-|X^LBRQRM(zdRa)6i91s)KEq2GSBp6l}s61ZG*;=)}T&{`zs0mUg_z
z-NGW-DF)FpQGxt{auUXvUz?xiFDzlR+(G`_?X4D?mYvwjFP=u4M#_l@+TW3?WAmQ`
zTGhj^6U(>C3^3lP=&h*^*)wt^YXE+Y)FF0i8EDli(!%g$0vPdKUdKc;lR-<-$&F43Q
zo6B%7XcQq@@zQjZmmla*N66j1=pLbMoh0USU}Cy1LLmx+kgrFM;^VsH@h<@OYr
z8jM5Oreh!#O_EgnSI96;F7P_{#8$Udyw~_-sBwppUvdB)GUB?&O%y5f{0L$7+0}{T
z&W=l5T}#BTP7Q(_U8vCbSD4X^Pshm+As9tPn=Ax+-X_$bJ%#+DxuhZyw1#5_$ZHVD
zE0)&iBD@yZLys+*;gCV!%RnP0au2oCqD%5Xht2Y%q@^}DBj=qv_rOZI551hxB_CHC
zlXwBvC1xUElrxArbDNu^yP!)*Dou(=em9u{yG+s-m$)>Cq%Y)HUjQC~nN`Mi1*0(r
zu^|{K89uYqM-)1HG{JVzc6YgFYuN$1Stp8!L`skKEj2lW(^w85nqCYN&?o~rB|L30
zg}B?2i41+)qK39i$0J4u8s6sCxirOhH=#c5@oxbu*_rw2y{F4GvcGdSOA}{$Movkz
z0-Y)_S|N`n*pK*25k);)d%En|S~2%{PaK7a5RPAXfb{opRHOz06~48xeP{^eQn_an
zg|$JO#HpQH&;kyMxw)xy>&T)s$FsHF!Qb=@WT2fg^P7Sp4%#TB6eL1_(Hh0y5x=lT
z=IiY((2=Q}qIRSkcLW^^eWl=J(-mkU$4)y2qZHw>5nieA=mGk3kw8CNd%4Ue1WA(IGz~a4Nb4)fGRPj*cKoeN
zy~D$HDpaSDiL&sO`v6I9Dnb)+_ug~D>lvGd>w{u
z>a9$;dt9`1D6pJ?HjJF;k+V*czjsN2`^BRTpXeGIYTW0R`H$Q(FBn(X&-`4I`ze
DoIvOb3-G{O>LWJOI^Sj&p
z*~8xQ;F5Z44}D^5nxoK;XL6fBY1tXmVLoQGfsTm|ObwoS__h|0u9%_QLt$G*4bnZ<
z-P`tZcUM6164cq(PYL0;K7ns09L<$dfiJTo_zM~sT6YMyakAJzk!E2L}e
zmBcNHD>=~jprcOY&PWSP)zFO`-(G_>xs6B`>GN~Q#c{gOYkV;i&oaA6Wxh54A}8h6
zC@*vTFT;p<>qaiwl2UlQ&~>%!J}xs(mt4q)cEqxDn@qVWN1p;IL++S{`TTsQD7{u4
zHJSiEB6t6E^ECCOEXwC+-^AEre)eZij??AkkE`VGRgLYxNv%5bb6p{Lny(INyYwNi
ztWoe;Ek4eG;ErvaXbDCa9g=0mGH3ulr|Sv83VtvLIeG^Fr_Lx?Ndz~->i^j$@JG|T
z4J*_5*3PJL7Yht0iuj*82MI=7Q7h^WUVRbIiBMLqj)vc-;CG~4E;2d>@N(+St;ota
zciel>Jw41(Xbh_?Ho`msYm#>PI9-5|U*0t^L!l-TrkE`5)$AvuWm{WG(M`svw
zW1Mb_?kvY|WQOx?msFb*n-cleEl(;^Wg{v{jq;F(gW$1PGK_fMnzxDnC5jkpwdD@e
zZsW#PhD|(Cm}~*x;MF0mcs4&%6jqP9pI$FBR?0%p%}C?7v|>pjH*!r}t!{f_vgJgf
zJOA~t)bz946VDWFuf4*ZDZ1j=QT8a;cncHFGHw0&tS(q}@jF}P&|ZJ_pzCssoA_yS
z;zeCkV(Hd^{J^s_E&@;7^{9u+NoYR_B^j{n6l@Vg*y$l?S^i1~1#Q0$SlasWE4#=-
z<6c@W-wWJ0`Z-{fuWB5u@9QbJ;PDk;FM-T>Q9l2dP~%>yywbU>>%#w?Uco&QR(a_&
zrP29z*B!NgCe?iO(blTbCvt2%uI9jsciiZcx{|}zIRz_^)s8%O?=6E=7UZkmBVTHC
zQND*6SNYOsy*QuMc}tC}G#LZs*X&|$TsNBwJ`M28KHGHc^KXJF2EVVoIMc=lUWOH`
z(!P;n!Qx2e4sWe>NUM-F!LSZ-gj6p3{JfF>=K=Z(r&g8x9AB*7Gn9}$B_}~nz;dmW
z+4?=DEjX8+#s}Va_k-_5+}nS&oN@Q|i&bH%n-kN|uI5VLS07wT#20InR;@Z>D8&y_
z`i#>#MdpXqsm{&J59yq92h-w}W#F-V%@jE~NIO;IzuoI#HNL@R?vOGmR*{7LVa`4yT;@J|yu9H(IBmyEx~~>Z`^1
z$BV{QHaVKO?Yi@Z;(X^%owsEp%y^(Jm~X%Cako&P^+B;xf*lu2LE3
z3!r>qSLx+rl>V|!8xU1dVji3YI|{cWDw7>_^++r1SNKJn`d-)$#h
zR|~}qP@GjZ1AS<-AE7JdB7_LtyE-xn`^T(C=eG6->Zib?_7p{4vWv_@lK;U@YXiit
zASC2ORMOQ}<|E1mz9*BhO6Gex+Pve-88ZX)e5Re8cu{GDQAdWQ^SA7zVj}F1C>1kc
zKaf$JC2oNJAp7f~J{_)Ua2D(mM1XbyKC9_=dGr<-t3MO^Dtjobm+&qpU5#sqHs{nR
zCc*xh9Mg&SrWPQ7xycv=nw>&>m|6KIVlp_BYC3H|A^z@#hMk-6Fco6yLOn;8M~)f+Q47O)@VIuTu6QluCk)8s#Kb<2H&pQW~aQ
zoOa=r`ajmqIs5vVKh>Iymk2yV7dU6WXgZ{WU0gY_J6Sz^G_h|&=mgeRPT65s3sz((
z$T-+wg`GEked{3p?XD;IwT&ZTjw1PW%uwf6`vW`@c)DxocFx-Sh5fK$Y5dQvPl5)A
zl?&Jm=!(vNBA#J(UR9h0NWk4E!&1Aa!Af&WBjOcZC@`Jh+8LIf4wQw3r9nzs4EF}-
zPNiX`yRGI4e$as@-bzeQADtMI{zYNfjIlrscp{1pZ`Igakx5?(HrBY>m9>I_FTR9C
zixJuEosd4dc6IHzi7O{w(?gqzaGPSz#-xJYK060&gq@A!bW3%^>)G63khCszyl8c0
zf$>@BY1j)-PfcgL;trk=Xi4efGu1)7c!AmfStETPL#Us
zXwCF4#IES_}Jv(&R;w3gCu~|$YEa}V;X#tUpGCDzj2S`-<>NHH|UU%temh#
zw~_m!B|1ZqL^ZIm;H+P@xupAIRhhu7XTqBBn6Vn&qX)Q!X$gPsh0CVMN+qk5
zLkn*OsYiaI0G)mHozG2CmCEQm4RslftyYe84*cj2F4?Yt8PXN3D8@47j3}}m|E-GYt#)oD6NoPp&Z8mopz^*IyU|H~S?mXV+RJ8n@$6%Vka|Ai@
z$aA#~*&c0mhEe~N4XadQ+DItk#$lVntvTc}kQoX~OwMO(rgu-bmf^ob8Lk`G
z3qFS$#^=W0vrb;*w&|SfTdsq(0oKAcw=fsoHY_^yIkW`I04Eixo)V>7Wl?hF@gnFsg?i|9g*vKTaScb2
zTrJy)%d3Zf06SsRwRpU0nCaj#9SyXcECW3Twl?m2SKDiU-S_!+PNagNW${JWE9d+x
z(*)j2riMFSl(*s5uTsA6-p_zNc{xN7$SK#=XFhWNj%wKL9&yr$bt?B?_)jC&$u?f}
zj@Y9{EQR}UPq;@e?uD0*1|l5a65HQ+J&^znGvtN`wIE$?Fn-xUYM9LDOpIE
z84hzD@2@1UaQu!qVtXS0o)PS^>qNn+@FW=je(mVIUF|1FYs!d#s52#ImdZ}X9?+51
zpAC;TE59n$?;TKxqM+T+w5wGgBnRAx5DHa>?(rKRgQFdNG%nxMjR-f6fF=?ta9ts6n!Q&+e}k>-4&tBmlWRi2o6yP-w$29P>6E~7aXGDE
z1wATgfj9r+YF3zv1cPnsesn3HT~4b)t62-!RRF05h-isKwn4Bvk}H4*=VvrE|1x-V
zeu3R)@Gz2m&=A7b(n)05;Y-dBf-k6LM9RD}_@&gYJL~(Azm|sezULtJunr
z+a2$^t+vbd;_tCPd)1=kdf5m)!fWr8x@l+VhAC%Xsl_XBZ0*QuD4&t$QtNTEc(3c%
z&{N`%j695E?{&%c7lk?ajv|x}wpO}>SNh1=en_tAH$lrgGbyp3oU9Wx!UWeP;8!o$K@H83ZKH`e5UyCcmxeTm+7(#5!L|Rh?qmFovz+AtJ
z#8%L7_}MPMFBtb1<2v|UA5y~0-3H5RgV@iDcV8=vMsk{^PMA_C<=EBbdAhL8BPzW)
zkGhEeakVFv$o{8>$OQ^(O!txyCS8LkVZaClR=uS9c`cJE+>aH`NK2{(kLh=rO}W^
zKTKmF4d%1$sqS(LNK-saQ$m^&(m1OL=2XAp4M$y9QpEHMWv7xIo9M_h&e|gR!jRKE9kER%xnUio&=V
z;Df35Q5yJ7)js?d8l8Oqh4)R>X?V4s5B6Pt0lkO5ls`4UV|n+Wj(k&fCMtz*Q}q_a
zb~g4{*B4i?EyGava?#THj=y7B{tQPtC&FwRM_;?z@qW4^UAJaX95V#neLuZ2jI&c{
zNGT__8c~?zO2V2=rkW2x=I-XpYCb{l>gF)>LFb*%zf!S1;nw?NYYp07(LFuAJ_PJf
zc5W~Vafq$KDBU5gG(a=S*tv|%S_ZUs1FhWvApk<;fcD!mzG?j3_g1~X8n%Tvp-4jcjTM|LKgg#285AWd3yKw=(-XsYt;%lI@oy@7A4DI
zg;poH>W7>lZnA|s6j9iB{fOr~L9SIgcj&qaSU-Nx{6%4d_Dq3w?N|Aj=MgYo)vAus
zu(u3xT47pfttzY>o?Ttvg#oR-b<=gxW@(H$4&W7{qRn8XdRJ?V>;MxpH6Op>x>Bl5cm{B{HrgC-tuTKDE9(@2t}BjH
z?;0_txHgeH8JEb-ff-%eVWBd1+aJX*Sq6z(yjqVpCs;2V4eL^>>AGsGGVTf&E1#m&
zWDX_NyK+bK8~LmU-QY|;_FLQiJ1a=#+skE<`@WLvyrY_Hs%U9MHwsi
zVy)$Fjj81(y&&7CjKP>Pay*n;aqD}jOQ}vUe_=JO6B!kmTuav(ta*Sb0`P#PkE!#;
z)M>{&O5LG
cKXEoTBJ{Ygl@IU>tyAZ=E>X16Y-vpKjMAYA-8rf
z$~l)?ag4a!H1Ga{TYCtO;I}#GS}-Sm6gb^*+B2EFPg7||9C;2Rd@bN#hCi2Ebd0#%
zG;e~x```$^`uPk^3+BW>?;qXTQs7(y9xXWj^rr}4|6B(44)FdGczhjY`Q0(xFOLzI
zo9<=czNqkThD@w@3ue8Oe+cdX+&+a*uzOYbMhDD5m~=X0tDESS&eq5N>n2ZiO>Nyp
z>o?S292kK`46cjA_TGjyYc1YZSU+6pA_T!Z4>;*Vy{?{u!Ck@JfY+`1{2X}??FZpEVJqj2(f>C^>!(D~&bDxp!
z9ry>8^IkJEW4%+D;Pn2u!(DMbtWWSU1l(0Gz`bJI_P$oRr0X@^eDT(iKaV7cWCwC@3si
zwD{Ywk)k7hx_flXZ(Z75_^!+%gx}fEW>^WnYFGe72hXQ`qCgYxP0Y;+enp|i_Od4S
zRXEFc;4cIhB(NZX1qm!jU_k;45?GMHf&>;Mupog22`orpK>`aBSdhT~4-)vl%I(i;

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl60x/board/config/.gitkeep b/bsp/bouffalo_lab/bl60x/board/config/.gitkeep
new file mode 100755
index 0000000000..e69de29bb2
diff --git a/bsp/bouffalo_lab/bl60x/board/fw_header.c b/bsp/bouffalo_lab/bl60x/board/fw_header.c
new file mode 100644
index 0000000000..fdfbd8687b
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/fw_header.c
@@ -0,0 +1,122 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0xff,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0xa0,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xff,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x04, /*!<  0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.pll_clk = 0x04,   /*!< mcu_clk 0:RC32M,1:XTAL,2:PLL 48M,3:PLL 120M,4:PLL 160M,5:PLL 192M */
+    .clk_cfg.cfg.hclk_div = 0x00,
+    .clk_cfg.cfg.bclk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x03, /*!< 0:120M,1:XCLK(RC32M or XTAL),2:48M,3:80M,4:BCLK,5:96M */
+    .clk_cfg.cfg.flash_clk_div = 0x01,
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* boot cfg */
+    .boot_cfg.bval.sign = 0x0,               /* [1: 0]      for sign*/
+    .boot_cfg.bval.encrypt_type = 0x0,       /* [3: 2]      for encrypt */
+    .boot_cfg.bval.key_sel = 0x0,            /* [5: 4]      for key sel in boot interface*/
+    .boot_cfg.bval.rsvd6_7 = 0x0,            /* [7: 6]      for encrypt*/
+    .boot_cfg.bval.no_segment = 0x1,         /* [8]         no segment info */
+    .boot_cfg.bval.cache_select = 0x1,       /* [9]         for cache */
+    .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10]        not load this img in bootrom */
+    .boot_cfg.bval.aes_region_lock = 0x0,    /* [11]        aes region lock */
+    .boot_cfg.bval.cache_way_disable = 0x3,  /* [15: 12]    cache way disable info*/
+    .boot_cfg.bval.crc_ignore = 0x1,         /* [16]        ignore crc */
+    .boot_cfg.bval.hash_ignore = 0x1,        /* [17]        hash crc */
+    .boot_cfg.bval.halt_ap = 0x0,            /* [18]        halt ap */
+    .boot_cfg.bval.rsvd19_31 = 0x0,          /* [31:19]     rsvd */
+
+    .img_segment_info.img_len = 0x00010000, /* image length or segment count */
+    .rsvd0 = 0x00000000,
+#ifdef BFLB_BOOT2
+    .img_start.flashoffset = 0x00002000, /* flash controller offset */
+#else
+    .img_start.flashoffset = 0x00001000, /* flash controller offset */
+#endif
+    .hash = { 0xdeadbeef },              /* hash of the image */
+
+    .crc32 = 0xdeadbeef /* 4 */
+};
diff --git a/bsp/bouffalo_lab/bl60x/board/fw_header.h b/bsp/bouffalo_lab/bl60x/board/fw_header.h
new file mode 100644
index 0000000000..b6746ad076
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/fw_header.h
@@ -0,0 +1,168 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t pll_clk;
+    uint8_t hclk_div;
+    uint8_t bclk_div;
+
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t rsvd[2];
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode;                /* 4 */
+    uint32_t rivison;                  /* 4 */
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 8 + 4 */
+    union __attribute__((packed, aligned(1))) {
+        struct __attribute__((packed, aligned(1))) {
+            uint32_t sign               : 2;  /* [1: 0]      for sign*/
+            uint32_t encrypt_type       : 2;  /* [3: 2]      for encrypt */
+            uint32_t key_sel            : 2;  /* [5: 4]      for key sel in boot interface*/
+            uint32_t rsvd6_7            : 2;  /* [7: 6]      for encrypt*/
+            uint32_t no_segment         : 1;  /* [8]         no segment info */
+            uint32_t cache_select       : 1;  /* [9]         for cache */
+            uint32_t notload_in_bootrom : 1;  /* [10]        not load this img in bootrom */
+            uint32_t aes_region_lock    : 1;  /* [11]        aes region lock */
+            uint32_t cache_way_disable  : 4;  /* [15: 12]    cache way disable info*/
+            uint32_t crc_ignore         : 1;  /* [16]        ignore crc */
+            uint32_t hash_ignore        : 1;  /* [17]        hash crc */
+            uint32_t halt_ap            : 1;  /* [18]        halt ap */
+            uint32_t rsvd19_31          : 13; /* [31:19]     rsvd */
+        } bval;
+        uint32_t wval;
+    } boot_cfg; /* 4 */
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t segment_cnt;
+        uint32_t img_len;
+    } img_segment_info; /* 4 */
+
+    uint32_t rsvd0; /* rsvd */
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t ramaddr;
+        uint32_t flashoffset;
+    } img_start; /* 4 */
+
+    uint32_t hash[32 / 4]; /*hash of the image*/
+
+    uint32_t rsv1;
+    uint32_t rsv2;
+    uint32_t crc32;
+};
+
+#define BFLB_FW_LENGTH_OFFSET 120
+#define BFLB_FW_HASH_OFFSET   132
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_fpga.ld b/bsp/bouffalo_lab/bl60x/board/linker_scripts/bl602_flash.ld
old mode 100644
new mode 100755
similarity index 61%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_fpga.ld
rename to bsp/bouffalo_lab/bl60x/board/linker_scripts/bl602_flash.ld
index c61185f7fe..d8e8cb5b9d
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_fpga.ld
+++ b/bsp/bouffalo_lab/bl60x/board/linker_scripts/bl602_flash.ld
@@ -11,104 +11,133 @@
 /* configure the CPU type */
 OUTPUT_ARCH( "riscv" )
 /* link with the standard c library */
-INPUT(-lc)
+/*INPUT(-lc)*/
 /* link with the standard GCC library */
-INPUT(-lgcc)
+/*INPUT(-lgcc)*/
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
 StackSize = 0x0400; /*  1KB */
-HeapSize  = 0x0400; /*  1KB */
+HeapSize  = 0x1000; /*  4KB */
 
 MEMORY
 {
-    code_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    itcm_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    dtcm_memory (rx)  : ORIGIN = 0x3f000000, LENGTH = 32K
-    ram_memory  (!rx) : ORIGIN = 0x3f008000, LENGTH = 32K
-    xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
+    fw_header_memory  (rx)  : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0x23000000, LENGTH = 1024K
+    itcm_memory (rx)  : ORIGIN = 0x22010000, LENGTH = 16K
+    dtcm_memory (rx)  : ORIGIN = 0x42014000, LENGTH = 48K
+    ram_memory  (!rx) : ORIGIN = 0x42020000, LENGTH = 176K
 }
 
 SECTIONS
 {
     PROVIDE(__metal_chicken_bit = 0);
-    
+
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
+
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
-        
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
+
         *(.text)
         *(.text.*)
-        
+
+        /* section information for finsh shell */
+        . = ALIGN(4);
+        __fsymtab_start = .;
+        KEEP(*(FSymTab))
+        __fsymtab_end = .;
+        . = ALIGN(4);
+        __vsymtab_start = .;
+        KEEP(*(VSymTab))
+        __vsymtab_end = .;
+        . = ALIGN(4);
+
+        /* section information for modules */
+        . = ALIGN(4);
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
+        . = ALIGN(4);
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
         /*put .rodata**/
-        *(EXCLUDE_FILE( *bl808_glb*.o* \
-                        *bl808_pds*.o* \
-                        *bl808_common*.o* \
-                        *bl808_sf_cfg*.o* \
-                        *bl808_sf_ctrl*.o* \
-                        *bl808_sflash*.o* \
-                        *bl808_xip_sflash*.o* \
-                        *bl808_ef_ctrl*.o* \
-                        *bl808_sf_cfg_ext*.o* \
-                        *bl808_sflash_ext*.o* \
-                        *bl808_xip_sflash_ext*.o*) .rodata*)
-        
+        *(EXCLUDE_FILE( *bl602_glb*.o* \
+                        *bl602_pds*.o* \
+                        *bl602_common*.o* \
+                        *bl602_sf_cfg*.o* \
+                        *bl602_sf_cfg_ext*.o* \
+                        *bl602_sf_ctrl*.o* \
+                        *bl602_sflash*.o* \
+                        *bl602_sflash_ext*.o* \
+                        *bl602_xip_sflash*.o* \
+                        *bl602_xip_sflash_ext*.o* \
+                        *bl602_ef_ctrl*.o*) .rodata*)
+        *(.rodata)
+        *(.rodata.*)
+
         *(.srodata)
         *(.srodata.*)
-        
-        *(.tcm_code)
-        *(.tcm_const)
-        *(.sclock_rlt_code)
-        *(.sclock_rlt_const)
-        
+
         . = ALIGN(4);
         __text_code_end__ = .;
-    } > code_memory
-    
+
+    } > xip_memory
+
     . = ALIGN(4);
     __itcm_load_addr = .;
-    
+
     .itcm_region : AT (__itcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_code_start__ = .;
 
         *(.tcm_code.*)
-        *(.tcm_cons.t*)
+        *(.tcm_const.*)
         *(.sclock_rlt_code.*)
         *(.sclock_rlt_const.*)
 
-        *bl808_glb*.o*(.rodata*)
-        *bl808_pds*.o*(.rodata*)
-        *bl808_common*.o*(.rodata*)
-        *bl808_sf_cfg*.o*(.rodata*)
-        *bl808_sf_ctrl*.o*(.rodata*)
-        *bl808_sflash*.o*(.rodata*)
-        *bl808_xip_sflash*.o*(.rodata*)
-        *bl808_ef_ctrl*.o*(.rodata*)
+        *bl602_glb*.o*(.rodata*)
+        *bl602_pds*.o*(.rodata*)
+        *bl602_common*.o*(.rodata*)
+        *bl602_sf_cfg*.o*(.rodata*)
+        *bl602_sf_cfg_ext*.o*(.rodata*)
+        *bl602_sf_ctrl*.o*(.rodata*)
+        *bl602_sflash*.o*(.rodata*)
+        *bl602_sflash_ext*.o*(.rodata*)
+        *bl602_xip_sflash*.o*(.rodata*)
+        *bl602_xip_sflash_ext*.o*(.rodata*)
+        *bl602_ef_ctrl*.o*(.rodata*)
 
         . = ALIGN(4);
         __tcm_code_end__ = .;
     } > itcm_memory
-    
+
     __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
+
     .dtcm_region : AT (__dtcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_data_start__ = .;
-        
+
         *(.tcm_data)
-        /* *finger_print.o(.data*) */
-        
+
         . = ALIGN(4);
         __tcm_data_end__ = .;
     } > dtcm_memory
 
+
     /* .heap_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of heap sections, and assign
      * values to heap symbols later */
@@ -119,9 +148,9 @@ SECTIONS
         . = ALIGN(0x4);
     } > dtcm_memory
 
-    _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;  
+    _HeapBase = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory) - StackSize - HeapSize;
     _HeapSize = HeapSize;
-    
+
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(_HeapBase >= __tcm_data_end__, "region RAM overflowed with stack")
 
@@ -135,91 +164,83 @@ SECTIONS
         . = . + StackSize;
         . = ALIGN(0x4);
     } > dtcm_memory
-    
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
+
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
     /*************************************************************************/
-    
-    __system_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
-    
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
+
+    __ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
+
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
     {
         . = ALIGN(4);
         __ram_data_start__ = .;
-        
+
         PROVIDE( __global_pointer$ = . + 0x800 );
-        
+
         *(.data)
         *(.data.*)
         *(.sdata)
         *(.sdata.*)
         *(.sdata2)
         *(.sdata2.*)
-        
+
+        *(.nocache_ram)
+
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
-    
-    __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
-    ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow")
 
     .bss (NOLOAD) :
     {
         . = ALIGN(4);
         __bss_start__ = .;
-        
+
         *(.bss*)
         *(.sbss*)
         *(COMMON)
-        
+
         . = ALIGN(4);
         __bss_end__ = .;
     } > ram_memory
-    
+
     .noinit_data (NOLOAD) :
     {
         . = ALIGN(4);
         __noinit_data_start__ = .;
-        
+
         *(.noinit_data*)
-        
+        *(.nocache_noinit_ram)
+
         . = ALIGN(4);
         __noinit_data_end__ = .;
     } > ram_memory
-    
+
     .heap (NOLOAD):
     {
         . = ALIGN(4);
         __HeapBase = .;
-        
+
         /*__end__ = .;*/
         /*end = __end__;*/
         KEEP(*(.heap*))
-        
+
         . = ALIGN(4);
         __HeapLimit = .;
     } > ram_memory
     __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    
+
 }
 
diff --git a/bsp/bouffalo_lab/bl60x/board/trap_gcc.S b/bsp/bouffalo_lab/bl60x/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl60x/combine.sh b/bsp/bouffalo_lab/bl60x/combine.sh
new file mode 100755
index 0000000000..198f6dccf2
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/combine.sh
@@ -0,0 +1,35 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=./board/config
+TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    chmod +x $TOOL_DIR/$TOOL_NAME
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl60x/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl60x/flash_prog_cfg.ini
new file mode 100755
index 0000000000..9dacfa8a0c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread.bin
+address = 0x000000
+
diff --git a/bsp/bouffalo_lab/bl60x/rtconfig.h b/bsp/bouffalo_lab/bl60x/rtconfig.h
new file mode 100644
index 0000000000..f405d74fdd
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/rtconfig.h
@@ -0,0 +1,244 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL60X
+#define BSP_USING_ROMAPI
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART0
+#define UART0_TX_USING_GPIO16
+#define UART0_RX_USING_GPIO7
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO4
+#define UART1_RX_USING_GPIO3
+
+#endif
diff --git a/bsp/bouffalo_lab/bl60x/rtconfig.py b/bsp/bouffalo_lab/bl60x/rtconfig.py
new file mode 100755
index 0000000000..b714aa719b
--- /dev/null
+++ b/bsp/bouffalo_lab/bl60x/rtconfig.py
@@ -0,0 +1,62 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='e24'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/toolchain_riscv_sifive_linux/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32imafc -mabi=ilp32f'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl602_flash.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl602 ./rtthread.bin\n'
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/.config b/bsp/bouffalo_lab/bl61x/.config
new file mode 100755
index 0000000000..1904fc04c8
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/.config
@@ -0,0 +1,1001 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=512
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_BSP_USING_BL61X=y
+CONFIG_BSP_USING_ROMAPI=y
+# CONFIG_BSP_USING_PSRAM is not set
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# General Purpose UARTs
+#
+CONFIG_BSP_USING_UART0=y
+# CONFIG_UART0_TX_USING_GPIO14 is not set
+# CONFIG_UART0_TX_USING_GPIO16 is not set
+CONFIG_UART0_TX_USING_GPIO21=y
+# CONFIG_UART0_RX_USING_GPIO7 is not set
+# CONFIG_UART0_RX_USING_GPIO15 is not set
+CONFIG_UART0_RX_USING_GPIO22=y
+# CONFIG_UART0_RX_USING_GPIO23 is not set
+CONFIG_BSP_USING_UART1=y
+# CONFIG_UART1_TX_USING_GPIO4 is not set
+CONFIG_UART1_TX_USING_GPIO16=y
+# CONFIG_UART1_TX_USING_GPIO18 is not set
+# CONFIG_UART1_TX_USING_GPIO26 is not set
+# CONFIG_UART1_RX_USING_GPIO3 is not set
+# CONFIG_UART1_RX_USING_GPIO5 is not set
+CONFIG_UART1_RX_USING_GPIO17=y
+# CONFIG_UART1_RX_USING_GPIO19 is not set
+# CONFIG_UART1_RX_USING_GPIO27 is not set
diff --git a/bsp/bouffalo_lab/bl61x/Kconfig b/bsp/bouffalo_lab/bl61x/Kconfig
new file mode 100755
index 0000000000..c6ee6e58f8
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/Kconfig
@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../libraries"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"
diff --git a/bsp/bouffalo_lab/bl61x/SConscript b/bsp/bouffalo_lab/bl61x/SConscript
new file mode 100755
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bl808/m0/SConstruct b/bsp/bouffalo_lab/bl61x/SConstruct
old mode 100644
new mode 100755
similarity index 60%
rename from bsp/bl808/m0/SConstruct
rename to bsp/bouffalo_lab/bl61x/SConstruct
index 7966251fa1..4b958f7cbe
--- a/bsp/bl808/m0/SConstruct
+++ b/bsp/bouffalo_lab/bl61x/SConstruct
@@ -22,15 +22,21 @@ env['ASCOM'] = env['ASPPCOM']
 Export('RTT_ROOT')
 Export('rtconfig')
 
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
 # prepare building environment
 objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
 
-stack_size = 4096
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
 
-stack_lds = open('link_stacksize.lds', 'w')
-if GetDepend('__STACKSIZE__'): stack_size = GetDepend('__STACKSIZE__')
-stack_lds.write('__STACKSIZE__ = %d;' % stack_size)
-stack_lds.close()
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
 
 # make a building
 DoBuilding(TARGET, objs)
diff --git a/bsp/bouffalo_lab/bl61x/applications/SConscript b/bsp/bouffalo_lab/bl61x/applications/SConscript
new file mode 100755
index 0000000000..c583d3016e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl61x/applications/main.c b/bsp/bouffalo_lab/bl61x/applications/main.c
new file mode 100644
index 0000000000..4d11a45f4c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/applications/main.c
@@ -0,0 +1,21 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ */
+
+#include 
+#include 
+#include 
+#include "drv_gpio.h"
+
+int main(void)
+{
+    rt_kprintf("Hello, RISC-V!\n");
+
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/bl61x/board/Kconfig b/bsp/bouffalo_lab/bl61x/board/Kconfig
new file mode 100755
index 0000000000..03b674a334
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/Kconfig
@@ -0,0 +1,16 @@
+config BSP_USING_BL61X
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BSP_USING_ROMAPI
+    default y
+
+config BSP_USING_ROMAPI
+    bool 
+    default y
+
+config BSP_USING_PSRAM
+    bool "Enable PSRAM"
+    default n
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/board/SConscript b/bsp/bouffalo_lab/bl61x/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl61x/board/board.c b/bsp/bouffalo_lab/bl61x/board/board.c
new file mode 100644
index 0000000000..1216b77be0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/board.c
@@ -0,0 +1,171 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+static void system_clock_init(void)
+{
+#if 1
+    /* wifipll/audiopll */
+    GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL | GLB_PLL_AUPLL);
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M);
+#else
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
+    GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL);
+    GLB_Config_AUDIO_PLL_To_384M();
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1);
+    GLB_Set_MCU_System_CLK_Div(0, 3);
+#endif
+    CPU_Set_MTimer_CLK(ENABLE, BL_MTIMER_SOURCE_CLOCK_MCU_XCLK, Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK) / 1000000 - 1);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+    PERIPHERAL_CLOCK_IR_ENABLE();
+    PERIPHERAL_CLOCK_I2S_ENABLE();
+    PERIPHERAL_CLOCK_USB_ENABLE();
+    PERIPHERAL_CLOCK_CAN_ENABLE();
+
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
+    GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
+    GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
+    GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
+    GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
+    GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
+    GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
+
+    GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
+#ifdef CONFIG_BSP_SDH_SDCARD
+    PERIPHERAL_CLOCK_SDH_ENABLE();
+    GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_EXT_SDH);
+#endif
+
+    GLB_Set_USB_CLK_From_WIFIPLL(1);
+    GLB_Swap_MCU_SPI_0_MOSI_With_MISO(0);
+}
+
+#ifdef BSP_USING_PSRAM
+static void bflb_init_psram_gpio(void)
+{
+    struct bflb_device_s *gpio;
+
+    gpio = bflb_device_get_by_name("gpio");
+    for (uint8_t i = 0; i < 12; i++) {
+        bflb_gpio_init(gpio, (41 + i), GPIO_INPUT | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_0);
+    }
+}
+
+static void psram_winbond_default_init(void)
+{
+    PSRAM_Ctrl_Cfg_Type default_psram_ctrl_cfg = {
+        .vendor = PSRAM_CTRL_VENDOR_WINBOND,
+        .ioMode = PSRAM_CTRL_X8_MODE,
+        .size = PSRAM_SIZE_4MB,
+        .dqs_delay = 0xfff0,
+    };
+
+    PSRAM_Winbond_Cfg_Type default_winbond_cfg = {
+        .rst = DISABLE,
+        .clockType = PSRAM_CLOCK_DIFF,
+        .inputPowerDownMode = DISABLE,
+        .hybridSleepMode = DISABLE,
+        .linear_dis = ENABLE,
+        .PASR = PSRAM_PARTIAL_REFRESH_FULL,
+        .disDeepPowerDownMode = ENABLE,
+        .fixedLatency = DISABLE,
+        .brustLen = PSRAM_WINBOND_BURST_LENGTH_64_BYTES,
+        .brustType = PSRAM_WRAPPED_BURST,
+        .latency = PSRAM_WINBOND_6_CLOCKS_LATENCY,
+        .driveStrength = PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M,
+    };
+
+    PSram_Ctrl_Init(PSRAM0_ID, &default_psram_ctrl_cfg);
+    // PSram_Ctrl_Winbond_Reset(PSRAM0_ID);
+    PSram_Ctrl_Winbond_Write_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_CR0, &default_winbond_cfg);
+}
+
+static uint32_t board_psram_x8_init(void)
+{
+    uint16_t reg_read = 0;
+
+    GLB_Set_PSRAMB_CLK_Sel(ENABLE, GLB_PSRAMB_EMI_WIFIPLL_320M, 0);
+
+    bflb_init_psram_gpio();
+
+    /* psram init*/
+    psram_winbond_default_init();
+    /* check psram work or not */
+    PSram_Ctrl_Winbond_Read_Reg(PSRAM0_ID, PSRAM_WINBOND_REG_ID0, ®_read);
+    return reg_read;
+}
+#endif
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x size: %d\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END, RT_HW_HEAP_END - RT_HW_HEAP_BEGIN);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef BSP_USING_PSRAM
+    board_psram_x8_init();
+    Tzc_Sec_PSRAMB_Access_Release();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl61x/board/board.h b/bsp/bouffalo_lab/bl61x/board/board.h
new file mode 100644
index 0000000000..e2a0acbb6e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/board.h
@@ -0,0 +1,35 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl616_tzc_sec.h"
+#include "bl616_psram.h"
+#include "bl616_glb.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_debug_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..b9cf792b19073483ff41f15dc01171e8d75c381c
GIT binary patch
literal 43392
zcmeFadsq|K);PQ;$;>2N1RN0P!8RrW%CQ!RN^32hV3Gl6d@e7brD4*OOX-^hJTrP2-&~+?6Uav=f9Xo$G=kN%m3|Dy8OFk|F<+A
z=YK4L#}arffyWYfEP=-ocr1a(5_l|u#}arffyWYfEP=-ocr1a(5_l|u#}arffyWYf
zEP=-ocr1a(5_l|u#}arffyWYfEP?+&NT4{mug083WM(Xuh5G6dVo3d8nY8gJ!*fQc
zFRa|NXz00q;&BGmRu$3i+50&=%E4aGG;_&{5O6OigPY(#)ts6-8ZW
zYC*5%QCzctTj6sUO~kmq7!Tujp%Z|s^-|Ra)ll_i*%7Izl+fE*>wnkZ!*qg!4+r)DjqG%6A0{<_2GcDM`y3ko2z&$XLb^Kjlo%`5x+7*AC@9ciuGJ
zRE%)#(S)p6{Z-Rj=6qL{w{396)KobqP3DH4ep9}h=tKc=%wd0Iq61p&ai!zSvX|Tx
zODFHxk>_}mZgf?aKGtN9vj%4Ay&N2qmwS&nu&$7nQF4&C+QiwO>bmRT+-65{VYr-W
zCOg|P)TFbykhjD%(=|KV{EV8AA$5=pW$6|=Dcyqd#x6fxAxqMlHxh>`EFU1_9ygS~
z?T@ISoYzdE)R2@o;h=LH@c&wE!8k!V&iY;nb@FJk*I9x-2zr0-`y(t4Uhl51GIBvk
z>&1-sK~4#Dqk!pDJ=FgU)IX5;PQM0L=i#66=K
zDwE98ulJPHs9}SVq)E~YPszIGBcmmal9Tqh%m|R=QpQw$8F-n4?fA+x@KrM`>3u2E
zJ={>xttx`-Rh>>_NYc%&EFD4OH`cDaGD5w7*Fne;SE?;DIqJ|2_Twkofs*w44!017
z)cp?f_Z3=#U?JAHEq0r|b`aaU4>yrf=YR~~c&&aMH6FWcFcH`Lki9>=D68A58upiy#>yUg7f
ze~g?VO%kZ1dj$0$#X>$viGV+b%K1BRkin3F^X+WtG9o78P2dmyBHn`MeE5TB!~%H2
z-za}OyE)@yVi(He%1pd(7ZN$ClU|HuWNe_BCKB>}O-hD5DUBq`EA^?9K*`@z3`;
zJc1u0a~mfQ^;;cTmOb^hiBs>rbB)y5lLXC*+lOyvZK;>hUvA2DW0k#hpyd>oK`||=3Khh
z+|%P>o7>YJ?Fp8V%1~YXyExm8hE6m2io{ui(hXBQ8B>$Oj?fC9D#rA!iyh5f{Um1PL^yEv{adyB>PzU)Sp9$TsB)Gc5UVF-Aef^(T^Hc&%$
zNzC+B*ZjJDrSL7OFm*{L`9~I=CILUz$nBC|K>1vcZr7eSGAnYs
z+5CNUK#7f{ySgKxe|6&G@~Ol;^n
z*nYmd61mom%2a3WMJDPFlxKmmX~INns4gha+J|caaTDagebVYBL1z+9zFtqASDlS*
znbthL>9xj`+6viWRJP&se7@@wWPYiuzc*exAA89J6XSAF!nh*IT7Pq1jPG;%89GkF
z8{1|4vLcX07qnU*6rRmc-YC*!qIZ#K?vrTXB0I^M;&&=&mRo
z($=GM@Mb{(liaN0i+lm*hpMX>@L7BGd|R80-~tT?qQgq_eSJreG7L9zGGsQM^77HY9>o1YZGlHmItm4hM9~k
z2-#kxA86<+EaqlmRen*!2$C}AlD$Sfg%~5*YwLNVkN*c)3m2YkjK-y8Qs%BNJ^1(P
zC{iXh01spb#Z#3^{&pP&b*6atN;m$OI+>XSdAe5yn8{3%N0m?VD~dp-aS|+BDdrvI
z%ggBizOxv8jKD(aKooNfbI2E4P(J358i`)9glA`Qvn*NBV1*=$OM((NQ#Sv~`^+1o
z&;k8{{ZJBZbF1v*ZMalK^U_Lh;DomMR{ow}XP8MC@{5kJJarxAH`ZnH+vP5NLI!hqXcWKMVyKlutGIZbXmOVUgZ&{$rCc0@Vt>YJR2
zMHS>ZmXAFMK8}yS0?|TGe_3&Pj`l0Qb34$T2d(8^6-ga{*5fQkv;KFmd#Ya}Z(u7%
zHK3Z@d|%JWkws>CPd|7nT?4A1kyexIOTgEb21$5PS*`}^R6+jE@{=niPMij|tT?bj
zBkw}|iuaIfBlxzN*caXzRMs8K+63OG0W8uFjo>D1bTv$wS#8*BQcNhz{VC`6A+eRz
z30k~!1gu9^t*<_|*1P)1F8$TR*h*~0jkk>ZVVtvK6ms1wpH%Xbrh63edCu~xj|*je
z)rTN{{8}AyCrUl)YLs-JwhdxP7GgwJtvVE?9$6iw4musB9z#q9_+;|ikQ_6mjRNhm
zaygT&ZJSU}JZGj68P+6$F)H3URk$MzK
zZ7it@W#puf}{>aJ}B`K>;x;+OK-1{$Z`Sp3L3UH;&Sbt$`?B%Ork@G<1)I
zzjIyUSN&+s7|P(O-h%6OfD5!}rMCVy%>dSKZzh9U6O@&tUAJ=8;x%Xb$rd1SbzPyfHi>b*a
zo3>S(L4#%6`P99r<)!lNo4JjX8FCm}-{4wzF4IK0o~r{mZ>|^m!-c=S$DQR!J>PX5
zU1-4LoOPLguLR5>yi`q8bI{4y#%cA_YZGchvia3LXw55I8bV{tFxQey?tIad%H-94
zW>KI_#zjY|O3WK%ndTGs`rYFE;saQ|yAAn8$4B$s*Cp6Wpp4%3P_Pqg5*x2$igQsw
zG?U|tJR7m4fSp)xe;PW|LLovLEu$80;`>{XfURRlUlh;E0k1uiDb7I{*E}p5m2dZB
z^M{?47+VcAGsA)^FTe{ExDQ$-|HI}C!a!a
z{xz;#SEf{*O|6OF6`bzV}F%l9@)
zJgu6X?^&Om^6mKv^a$JPzWYqB5AtitPdp5x@tJXaMh{AAf!>aC=lC~!+|)=$EkCT0
z9%nT?be
zXiFX)9^P!l--i$ykKYkBWW`7PodgNAC#!d~aa1jeV;SQxXuGK>zy5;QrX00s|9EgM
za%jF|a4pQuef{|f?P|@c3xuts|GsVAb_<233%U6v$sncKG^lhus
z(7sv?>7zBDOGE{Qe%5F!)|$`;{|;?18rqaJa-tQ_N)cLX~Mv)0*f>O_QS6G(H`<
zCe8;idQcJfA)FYYH7#e*BMhV#j`JBz4Y`V*)
z=+5Y(V#;Gwv0GzFh^UGR1P@@v9>C4&Q;2Dp=!I2Gk1rZ;FrW8D3YvejTh5re`!&A%
zz<1qapKWBMy4gpIv!cmp>^sSq{aDQ=8vIx*@$Y#*{_z0sl$>9C9u4OHxY{JQ{j&f5
zA&c=D8Cg`|vk7zMQ|M-mv$`f8S8IHqBK}@X%Aak#TJ>zBIk&RkLL$PC<=?dok{NEr
z@1>iuUVe`7HNop+L)$!P4;6M
zzhR(@hJRBZIqTXW-!+9bCy2U;%Hey@4X#hC93*M`ApQQ~V?G5HIpI&(a;y(0FF+=&GXB$sfRhWE4>ztVge%@E>CfH~DlS1FukGueQi4)|av73o}_atD#7}eVH?;h#T?GY^bGr^Kg+?tlOuPSoBWZetRGiD(70&nX~t3VOt
z&)=@3yjf@+Drmc;`CKK^nA#*$SiWx$C0eH33Vq_%cGaY4;F?_1NbV1C)P#YShW%|9
z^x%=2RL4$fgo8Ym@NA;=x
zuwA7d<4wN5KCnvEr>ILgv>KeYW{P@jsw~oYr)u?*=}p7moYtIh^0mf-H_5lmir8OO
zXM@h*5manTO6@%8EQp>D?!j
z(?;*-QR@W$*XwS))Dq5nq=)maw37E|c*b@uxF0;ulRXpOi@p?HQn-q(n9u_=wyjY!
z2az@mND4v*OSFbjq0Fr
zgc__6>!xZQuOOe);4*{gU)`d^OZem?PfpSm6i%w;yXz*nZ&E88er+y-Iom5A-Rt^<
zryJxvf8E9A=lk1xtQq?1vsUbV85#}YQ+u8Ox)h8UB;#iCZ*&Ji?C;wOAX0IL5BM2&a(WIwDPv^q}rXh9mwV%v$^fNVe_GH
zPSS1DHL?5#dKBM(?n&tZ8F3++f9K|t^0>HojUrg9*rfRqkAdjPnurs~b=b`)Ow&Qn|53XPYVD~W
zc1?yU6TfVZKC8PBUB2C`(7S2oS&)lRih86>0#cAbP8uX2XNqaULOq3+7p}6BAc1Q@
zrNb3cBt_iEluY(9$YfUqP?W819j+fdZa?D~xo@3#9coCBsqP8WtjLYuY1et6+?Xp#_5emOvVg1X~2_
zQlqo7-Sni|S%(HwdltqgM~f%b!bo3s$70Tn=w)(;Aw0YJ>;-Mb556Rg-&dWTU%`7{
zgc0Uw%SIM^pE$PBiv5p@TI-AZ7r)x-iqjl_YaexqRVzRJHL^s#dn92TBa=u+*Ahn1
zf@b3w?UqwXpyLOE^xdXl4X5Os6g2!|b3okY=%l7KZ1@iK{%j($M58Fts#PON-e2J|
zNoRYHzOg3GRz%-OVr^UL8%{e0xyojI^R!QN}}Mg!FJIy!z`DgZ5wlM
zZ(kN%9TD6$|US0{D57?Qp7+nKYx^n9vCGUcp-gZ3r~NaF8UB=RXh
z-$yY9=^8rs!!l+|*p^*!OX~^-YhQ3&sLe4H&mzktpy+m~u
z&$3bHgU-aZB%BP%9=oADFRz{8vN*rGq&l-phxEvP*O>d6I@Uz1OYfne9A^1FI!g~L
zh*wUP`{|N&<%XET?+TM@{c7`r6#;xLE#aS3Abz6^{c}sjEflvgQr~9TDbrbPneqL`
zeF|i|(t4lJpRT&3^@|CewQN>Nq1G#MeO5HC+sa{7bx3yT#bp=QYdxoYW10wk!868k
zR^BAaN9$z_HYqM>H|tfk(vfuv|4p&h;Ty;1ZPZpw$U&~&=c9sZ%CceR+eHQb?`RPP
zd_VP(F*pWE_hu^y{qAD5>K-!gt5t+=Q-7K*=Y2Yn`cs*l6g03^CyBvY(0Wnzs#-i}
z7?Q2_0IjP8&Eq)>DV|q1N$pqqw?p&`y$6Os8QTwWK1}N2t7dhDu~@bXdh;T9MJE^UN@;nJ%GG!L{_XiM6&T8%+XQVF+}gLO(Gq(B-tg;>cnSf#;kGGp)*Szf`|4aQMZ
zBrBi%*{UA1K%ySIMxs_Wk!sZ?l5blT#BX1Pj6rS^-ac=nG^k0!zjZ#4A9kKF25*$`
zZ4H4^t_eme{9k&2lO_bE61X4gx2eZ`3aiPyPp=9h0ZDIyG^JQNU=DK)qzfz$r2Tlj=eIwtY|XLoH7NwY0DtTQ*;TCli;xb|
zXp*UwpF(Gi;3Hor<+`C6++_Mp_H5m6!L40B5
z5Gkw&1Ftw2!K{bz>~1%hu{xKjN$f$)${r8?iB`{Dv|9B5*;aNxP>*o~`*Z_Yg&pJ9
zt$cyE{UPJuYmhJ-rXW+SLT8q_$=A;6on_p+QCN+ho|9twAu^AUPT&M}wq@Eqeo_p&z)2(^rQ*U5D4T6tJ#U_XISDiAcvX9okxg+S3?+K-
zmsg%Tf!my$i*^FP;}c3{+7oFE0!l${w7E41t)zo4^PX)K{~;|iavNO^{UYUdxEMk2
zl(stWd{na5&
z47t(exd}gUe9k_}@To@b62Wh#$MJu04;8E!+QjgwytD_6n5y2rfKc!M8dkrJ+ya-9
z-57}%s>+})tQcYM@i
zzm~rVb^h@P*pVWnSwsGSCN#|&cbBt$xUU=MeIPe-0WM5Wk5t=l?xAHr8SZ?`P#YCL
zLoE+ag0;3Mx;jC(pyMXc+yjY`4scN`Z%O#?X%|e>iJOISy}Rx@aiR4nz^)|5;Ef9P
z$XgPVUPE`Yw%^)1aAd2Yp{2c1!-#c4Ix|Vk@fbu(@5o
zRX}4NQ;Lm%30jY}cf4p0DX@8xx1_;M3QV29(GD}u1P9W9xb1-qq8u!dF}I*)ix$27
zo3)9(iFp?MyT^jd$7TOiY;2%ie)v&;7~8TGEY6l&|C4mD8?1U@JN_Exlg?+_-lwh!
zZ3NSU623bGRzdN3iBf)DF2xtoGG~pUokM(mivldl_R;k#z@NL4Dd#&ypmfXcQW$$=*b26-yyTN_|Hxk;@ry%{ay95pge1R>m
zvibky3vAx4Ed##b5Z0J{57w686L5{kAMu%b?hshglfBK|>^$9hogt<&CMb4$EcMde
zzojIdNh+WHrYUN6AoSM!P6;ZMaoBGDI5pBxS`kL^&O68Lb9cS
zWGwX39gFTdBN_Mo5I20jYoxlA2vUD~Xym#~b1o6IZL)N4R-h(#FXC4=AnBg!!1s<%
zC=%y;*JZ|Qm#=j9-4V5cyjS=`!NwZghX>Vso~^2d9@>r7W`UNe`r<2ijeYJWGmU;%
zXLeEnY&pAC2XXfw=5|^VU={oAiE7Z1E8kU&k|2gkvhwQ{GFY>eX=Zyj7ej9o_H-sU^$?M5K7dA5%2ToD`4P8B!)m$T?%0
zR#e;~>{D3b;N4f4aZorhceN9LI$p!EpqNAHz0xP`c*#}UJD+wkr1kd`RU*7}D2DfT
z*?KToi?1a13I@C;ON*Nag%pJ9|(}kT~BVHI`7=vKvl~5<^8@mi5
zoEX0&nrY3&qjp&5yoQ)onz(9I6W7qku;1*Gm?nWV$-^`$q)9u`jwwPu8KlV`rjd|F
zLOwB#f;8%38VzYQsj=%>oxRVypZMwX>JeG+#${V8Y;10iWkZl0%Z(&ScV7Sdf+nfC>vVBy&YD`
ztgZ2QjU4L?WJcdPoP2nu)|3vjza9C89@gDZuz@eGM|lSI*w!I1pTdeG6TFM@^K7HO
z2(elpz1_3r&Cy&1-6mPjdb6bA-uo4;`y@qlMQc0EB6?d_e=yV9>)TV@GbEtaSicO`
zBVcZ^px#Ac;0x%sJifb`=`yQ_<%D
zG1hNGOm}O4-iDGI=6W#d71BMe%L`{(lcty{nLL8Jdgb;9Nli(*wZkIlr_j9*l4=83
znB#q_oHe&|D8PCtYV9Ut!zVCWx>qP|_%F0omqITryjXa;@KVi=s5>8++Z)i1n%=~u
z7C$zLWzv0-pVi#%i;^5Z1N?`SNvEY*Rlsd8aN7$I0wBZ-RY}@ylP^rZ_x|b+wjIB4
zd|jr+f|T1PXK}8U$}vPkz9nariH-o+%)c=?)h6?d24wCcrQa2*iEd1Y^zXalp7re*+dA459!jn$@rYBSA}JF3@Ze#V8YhmolaX78?Ar~;1v!y?NF
z_MB+$8IR1{BakMs6*0?cInR(!Bl@idasZP$nQHl5hQbrp1{5on~rn`YJz)ybxZ@BR5W8ib^
zcRYrj
zFn1GyO5^`@+d(1c;}Qm{NWxqwvlR9
zHBGAz$@@Ip19f;1x6mOH->is}FeN(VsvoI6W3sorTjqaLLyjZ{sHueY9Fxqpb6hX%BDMTP
z|6N`I);%43@OOpf&;nJ|X;=yF8V76dBpDi@1>0A`YPuHM!jA!9m14{((LQ&72vE@CSpU>AfbP|I)YLbm>!4+i+bwM){D;7s$>rF5ve
zv>oDoI&?-Me#2!=t2g3a8|n(R%#O^f$^MQbqNkat=8_0?>FDt#jnV9}h-fwi=6J+4
zD>8YPwx-6{wMY?!^>c
zBRfE^?btul8_ZQ%HVOPp$ex&&1?{ShqnekGzr;>ggv*>%8`(SK8`-HZNcSj0F{R`z
z2d8}W047RW9S@Bc|yk8Q@VK_&AVZ!V4@F0h(Z9Wi^O+4lsh2F>@3<2SiLIU`;e
zT#mRB*jq6m3Fq42pYcD}!T(gv|Kz_~Gng)!JpZc!nxZ`Z9si35@xMj$@A%*K{NQp#
zZeREl{q*VR6Ftt)KZVOmgm?j$L^l*HM=akwG;Tb;X
z{L*wPNjqaxIXQI`>=rmYW0ShHVI0`h5Qj
zcXZ7MqxW_6dzblNO&~wlxOMf57B#eU5mwa4#
zE}zkWj^^UIcde0G-hlTX`M{o(pWC4qVYUaO3EMrRO!VgJ+m^v!br!4JTiQw^g^_}%`K=Sp7M
z8aq9=IY$*+9ut%kYr-wd6ip_72D8P}Yo)OSv;#vnw*Q2h*Q~f*NMFj5OvpQ$w>xKg
zZdP>ANvgRl`(EUu6sP5$%qfqFikY4hWKzYR(P4@szQX#9NbO5uWVK9Lj+_muiM5u4
z-^=1gaPF`to2nl^Ue2D(5x-6P5iiIEtC7U)&Dp9Gp?P{OK^(?&w@yk4Co4B#YT}N`
z*XzR}TA#S#o4gS)k1J3W=66$Sqw?yrqmoW*5oC0lg~qX6MXG;q~w#0-~Ka@J|5D;>MYpjQO#jD@!XI(mzxo3wSe{G
z7Jwnx{w$DpaDMap=tM>yJqNI7Gc@-%bB}7ftXubk8r|Mt0%VOUFBjbRsJ_p_B
z|5tQh0J?ghI~nL|f$oby_c@>&0dzHK&|XwcPECQvPZsEctdg3nX!qzXoI7{e;1089
zR5Q#R?1xlG%1%f*0x1Q0d&iu818|(<7{H4F{^OnjIL5CAcpk?8WB`7|QNm%2|M>vC
z+Ck?S#{X;pj_Kq9oh=yuqXGCafENHN-IIb7Q$MC`Y7XbVO!1rMM?F0Cje+)l?@rwrFCme8r{viG_KIUJL=hgvyEFUaq
zp}w03;FwQbFASekH~`1=v3#%`ek^zt{*eBA18~egh70oFAZJZnWKED2>mHZv%<*E8
z=;^Ti4PSDy5w8n~>jZd};PuOR-2kr=lx-NBPsH?c8v3tGmO8-iQhIrAH$uJ@VGWWAD8=?6aS|HeC#idIQh9cKz}fwPX2Ly
zv38wu@VG4Ek3g%=;ie<&XZ{}><3!O3Ugc{#h2o9@u1
zn05#>=5fyC3g>{#f3)x>1?u&;-5Y)C&u2HIW|s?dn>N|KCQ>o`$jt|~T<*VZ@6!*!
zy7o-1u$g187U-PTg7tu{0^8=P<`Y8yEuOG}RliZ<3El7D4e)s;IthB
zr|rD#)~eGOAI{hL+pYaAugu^xU8o(pS7z)wbxC*VTVA1%@wp1wK;J^X1iX9!5`}2u
zWRA#n;SX{a_k|b+ebcM%hF#dgK~G{E7uvIh_f3D&XK^r7+d7z5VY$sM?GI_44Au{yTK6a~r_N%`
zEQdVpUxaM14NJTCD7C^fgK@t2%;ux-!Bm=aMnEisxn0yEXGy`Q;WoUe$@z5zz6!zL
z6~w^&s%KWTm*5A)R`FWRH1H4DYE9rDu!q4`C{X)U&U(e}1St0T7`sG2tyWSq9q^yI
zG7t@6Z*;0rwALcdOR!1|D}>(ANpq*cOYnEkRNy*oQ{eUsRK6RK0?x6h_J2}&=KcRk
z1z8Rndq(nMeH@r@G_n=X2L``5Vt5q+u9
z8~oQJmXYkRm!pqBdC|i^b41LG+am5cJPzUVH!5K69(vyqoVQ#obrF;bUw$H1;W42G
zkcNAbFQ9zU3Y|Qj0y&8gCy!s0Kgwfa**2YsBXak}L8rE{?!N%tiI#wMf9gL0^G~$?
z#W!ak(h%hTFqdFI5OodED1=zcNkjBgqU9_CsbJYXtpBdT+IZ#@K^p!LD`X2bhWcX(
z7k(y41MC3H408*z0exa=2;4d>4&&M(N^;sI#RQ6#G-u!L%wsQu_H6(@{cx=peE|F9z{hR#)6nz{z>zz|3K#7G^iko-~OsZa)tWI
z<=T+zLvIZG`H5Rk{ut|k1nR9mz
zLsZK$kTUdNN$3B2xO(g>eZQ%c9&5c4`B-Mns{UA=oKQh%aC>b>Dey*~{yZ@EOhzeb`iJ0nql`jbTc`CW;+R6;^t67rIemxR2ex@
zVDuV)cXG<)Gf`1d<=U;RN{c0qDKF}nbK(C^!WJ6Ng0BScJ?udWtfL^9ExBpVsb9<6
zS}98pq~$_dw==C_o;intnVD9ZC9zLP6Z2p=aR~CrEOf6*$YbbJ4WvCQjB$@?E)PPR}I*b|j0gY}M%FORQH{Jr7J$)nJW!Y_~8
ztzR^h=tm*@m8xyO1*1?!I-cdGL*ac*L@tYjuQd^L=9Q$$Mgxr^yV|H&SQqMI>$WvGhgwW?m^Us9|>@p8fXlM93BX
zqZ3%|SYys@m*Nt9*Emz0PgnR)RDQ!4uy!*z9bkWtpnLn*`rgC&;2kM@;qHST?{2m_
zz1LSgrpG%FA|Xr%f(^06hovIINgw+g@#YM;qk*hji1(2N)!3~cZOj;{9Opc#O)j!q
z-_8GRq^AJEw|kI_?bbOPehUm0AdnM(=P}DVU);s3YLT0)YGqf=Zju#35%Nmv8#
z_3Z^cdcPVWM;&YZD!M7+E_tp1<|NtPVO<69P^Syr{^9rPy+Wc6u;mvEac-FHO~I?<
z7O-ZR16dzX&5%m4v5*{+Ga0VJX?ow|f7GO-$pT^bn>wbs}FcvoTDj{;^8sm$ljv10!G#B(g31yVIJ-gPh+
zI#)3k=Hnf!(T5^{s+r=v^0~8Yxn8^CPGO6dAsf)?!u-UuY`)c+K?#rXNw68r^VoXKb$D$E%tv;;Aj+T<
zIL(`fS2lN(7Yp)dbix^&PF7_Ys>f34WHqoF414J#cg-`x+T2=ScaTi)f8)Gc=zPGe
zHmW_l(bX3Sy|W~R{s+e@4=ydXacsR<;{5R{gJmR0C`U%Pf`p7*B`S#4esHmn>FN31
z$n8Z#_2v4lu%093w&V5I9*trfdJ=Y#nt?khmxEOB-n+8bcP;EIU4hC0b2VsnZJ{~0
z7P&@u0>ycVnYo^*gp>&Ss?d(4Tms^s@>4_!Fyw$4&~7qCgj~UPA?1S53h~>DDdO|i
z_r>o%@p}TgE`Dd?^*o$|LVpK{pjmDkOQvs`2Ry^RkNg?iK!4jEed_FrHI4#Y&b3VV~-NJ$)F3l>+7mu9Tnb2=zp;65#GY|
zcdF`yw;272Dp+-u;B+7TMGI~dycbDDq=EOPNe>3^i{IRiA~^P`5%h)Q5s7$?Jh$w<
z2Jx-^(+dp|zHmDTO^3brt@yU@`3v8Qslk=+of6;DE$S>9T{s0k!UJpxw>vF}n26)4>qjpc_aO`1Vq#9tq@^Up!Rqx(6)ROxo_yamRvZjFhSat`&P97ilO|Pb>
zz)l1LseSK&pZ3TW=R+|C?7K_>c<-$JYbO=^l`qWmUo2+{n2pAJW0t_|bu_{!_a#>Q
z!KbccJSp7pf}^_)redqO)25f>JN8j{FBwC{k=1%Lq`K;_X7WCD$VBruy09w9Yj@c_QBWCp#oApWozgW5z4(UilCZPDs&c^Z6Qy|H!rB>n&?ers>ww#x
zd}4XcUb465q!r(flvBUEcG_ipOOm>jf;$G_jwIN><6mD6cO;29m0#Gc_AdwBP}A~}
zWmg)M+49t(vOM0M^d!^lEiYO^YRNQ7y`&M=ODj$3AtxnGky9=KeR`}
zkl*eGYM<`blk*ZBdrXwZCAUrKk&Tl2Z{8n+;G9a!sbeV|P{`(eAcx8I6T9`)0bb#P
z&Ok0FSEXO<04twZa?e)gG7w>bxD-J=Xt?}3n%Joby4B5DoeyWGhuZs
zxAk4vheVf>RI_^69prTaZpuRTgD-x8Z)p-+6|9?AJ-0-4Dd_vL*`H`*FF<4?3&~TN
zrk|xQPdgvJq4*$fFYFk8`zLbg9-_^n=v6^mk*RXv#vBAzb`V2d9A7Us;4j#B-cq$0
zzlk_i+e{pssrI=qF>?N>;1{taGNxTW+7G_FH>_IZoh*mg%m_QLly~D&;?KlK%_^Uz
zdTj*A&9<5Af0*a$9gCx`6@Z_~kO!4;w*|D`-Ow)cNRi)C9}F>*aI%NYqea+UZ$dxY
zvIF*M1)Xu;>w$ftS=OS2Ggq>)*&%sm69?zH%Jak=R|4GFka{n}7IJsd8z8r;58%W`
z+isJIbFJ6U1j_Dw_B{m8;SMPcaq8WvaYxM#gCFWP%dRNvgj>~Otz)yL2S_5QrdnT?
zt-|~N1Swzf;h#DHZA~Y81$IY3o}Cw13oU`0yzUj2{31vn-%w@1vL`|IRqx@5OA-U6
z31>7Ma;XFj+s(4g%I{#sC+H;JDL^%wv#T#l>qjDEUDh?2Hxz76|E2xlN4KO6S=XRN
z4ujq64I`nfL#LA1EL}nVp>G}Be+Be@7QN7wU0M2&JQvty{Nk5pI-88FW$0`Vc%#i!
zw)+T!nbZ+3rbzJ5A02_c1P;yWzs7zTI2wWDfhgctJiX%Zi90IDK&@C--7&BT+s&$(
zpe0;$)miF1M0q-s9rj~_Jz1ds*w%3E-z~+ZVLbys2m7-^vf&;spZ1D)t
zhe;*0Jx5)tf&LG-EzUjxduEX17jW`rJp4U_$G{?2nSXV9YJ8WSQ(~r?ocfbie3#wl
z`QaP))=axB-fo9)wtKrdVpd-Y&~Js2$J6*UMogIfphq8K)tRm+>>B0(L&;i@=Q%hb
z^CC~1lpuNU2TBLuO`wl|Knoc0KfRiG1K!=K*t@~)V3R5op9r3#8LYmp4(i)t+yf&k
z3VBX5IqW@IfM71r;^49k{4mlJ%g~gbrH|ZZZz()4NYoA5v&jwQ`SSN>IwmZ$;nHNL
zK;g-_#Do>(Uv$`jsR1N>LM(xmz3C`{{Tqgm2BD@MKYlf}O{|Bh5%_8FGAuxhDaKpk
zutz
zW6`1fykGE>f&Dq7+ttVg9op|G{RGIj3g>*q;N-M44u6Y$KGm3f?x8NufxfKiVg>Da5XU+?Hd9%(=zy
zL>A%xMx=qyQsH$1yx)M4We?qQ6Kn$ZIf`RP@s!i&*=}sx#So$Yg>zn{{sP$3Zdm0v
z1?7kwlv>=_y+v-;n-)K_7@^~y1xKH%(+FF_Pd;=9%U3;GZko#+m;j@o|(k;#xx?u)f1
zFE6xYark~OL00=As>RXmrxx*9)-ZHkrs8&x|A%Az@|Z{yj`Oj9wtzIu**azi
z3%fT=a0_A}_Shk?Z{)eOb;WpBdjFjrtXZK8#A(f@kh~WF4)IUNyB**?{&Ejx!D)=Z
zKLT{pz}mnH%RV%}%J!G8-%VUh)pK=axjy=^dg-}z1d%Q*GQurRaQ1N@!aMjXC|c@z
z`~vK*uaKBc6ruGBH+@qCrAVATl5&^R3zGCrix1=x@5X{1awdG%+u4s!Z+gA{^9|wo
zS;2>ELpJ#6d6}z>$r}gv<(OSri4pdA^QoOsCb>V>RH0ZV9q|nRq+U8b=RCx>_Jhyt
z9gZUf@a3#zZxP%_DcIlKl0VzAjpHa%#wcPW3xS_H%i3mK!>;e}?mD~&5$~;=UaR2D
zc_h9UC8yo(xi_~Qf8kAOYZ?mA8=Kvno2BFLUXw(cqy`f9qAOqo!b#v{l?yKYq@(Q8
zEyhIPxwu#Y>!NzzRxHOOs%a+IqE6*tJY^xqgA<7i-1ezE1ZR#QI;$1=MT+fxTW|NMXZdzB2cTg#Aiz&IVKF0>`hPy^ZxL5UXVJt1$
zj&t85oXQt8^6c#D^m~O{zBLBbc|EWwZuK|9gm1;(lB(x
zBs_X8o59fgUW3tVtEP#eBaUBaz%y#D!A8&;RE
zx(1Sy%yb9I!@XU2|9tullMc@p^3snRi6cP=bU%)
zY#Y+mDe`>8QV~&tTuVBmW(#8i%&Xo8^{>Js2yy(d^)<=gAl{6};|M(8CGJ%Y$u`S8
zNr%NfAY;V0%s+TpAkphxa?9CUvk&m?a&VVuKo1g5)FZF`PCI5ZZdwWqHmbF6gNbn3
z_Pr@^s@S2!d+UVuWHPu~RtDhH8m^Ys<@l_ItEGL)$MiMXP%ad9K-OJzjcA{whHrqc
zh7%R?kL8^*Jh!{1Q7ykF1KOo{43?P+HCj5AKcHNgryV4m_sRVD;
zAojz!4Pkr6x0BYj!3nL>Id!kpIU#xh@?!1N-!WvU@}32cUSNm*<~o_NJ_wn9#qrw3
z!X&G4U-h*u4N0u?J0O}N7b`FRs0FIoE^sriRFt7|9HCFP;8|UmG5yxKH(PE2e`(I`
z`IX<+jco4p{UnwUW`&nqKsL%lRfK-TB^C6_Na`A=e-^0G4sAS>1hcW#m(4lVmt8Hv
zZajS*$D%TZj8hK(hqM81hw6?%Hu?2V_xw9BpP6K3$hpce3*I%4=YB|zr`iylzlU2b
zVSZ2Wbo}>axzYw2{L8|AjcFgd)@NNNLVwfG{@ZM2V1~O3yc_U)+S|*Pt_Fzm?M2I!
z^A;_CJM~Y}{uCagQwF9!n(YyqV*10ZjL7B@&r4UPEnPZDJ|cYn+w+$>s*J)k6US*LhChpSVMt3+
zhD9jDL&G%=`cYF}jZ;P~TC^-&nXwEQo*0-hX0ZKmOBXF){6b*rn8|T7l#{`JmcfTm
z-m_yv$3{HV?~1ggkQFCnypimny*wjr=^U^H5k75^az*lj`Kijd_(A+?`DOE0fUM#t
zLK)ihG?DAjh4a!ezxWa6co+4*6x$a-u=>&kZBNA72Z~}k28)b{-%}0TKiTj@K7^(r
zu!0Pe4IC~{%!9=tN&}}3f-Oy3wtVT^50x?bjWqr(<@7}h7NjKeZw=r&AcZsEIs6-g-*GnNfQJuy*9>|eH|Tx*p!W%b-mwXx
z`Qf}kdwzI^@LV>3VcJr76P{4g(q%kKPRl^cmcA|6#p1V;QQE>}A=Ap_W&9hdiv&3T
zRt8%5=HfK`F@NdORhTxPyilMCPl4y;K
zL{?a3%_NZI;*C7_)NOWi-n*gI!KeOn_VZtzO?Y>Y+oVjG49P6E4(osPU*FNsFJ1p4
zy7c*~Gp}!KnV{7^n*7LDUw{9DXa0%)>v4OYXdHLs*2tIK`{&JAf9S;%$NWj3SB)h*
z3^g@HcP+_Zm#h0OjVzsY;aSD-GlAoUIsyCt>L2m15&#Zq(w6^2`k8-|E2idgTtByEo+gH@zDfUHDSLA6%D|(SfBR{2!lEyl|I*mA!+*_c
zkZ2#!kixSUp1>0#oG?rqOWgUy?_XcP|Jgp@53_$eavnhfsO>({V^#0fin@Fpd&;>TF;>L-v_13{Wi~8
zu_t0i{pvq5{<<Y_00_~tKOmb?r<`Bf;D2ef5N=Pz`mKRYKQZNbBLF#+;vG!7(8BW%vH`AZ?gQeG2|
z^S!Zn&f-P$=4GUT7aw>J8}uHI77W4}cn=!{4@W8Q4A2>P4;uszN6Qv2p0jXqsN)&t
zc!q=j9H_7OE^-9yp~V?XlNUPp$2`9UuvHL>VMmOg*lFRX;CHb+Qs)bPLXgdhMa!|Q
zaJ`?Mld^hoa)yw$JR>C>=MPOsrE{dOOaCU7qG#c~O8Sj7K?)Z%!}~Gm*V0NUg>>-#
zqx7=$d#Mb?!TUw&1?gFMPlESfRTssE?8tAUE*%F?g8yQ)xhgaH1Wi8Ccgs|>OcM1qOfM7m2c
zF%D6a?8ZcG5#7;XB!oC8&U8x`od)qI7#Z@jgZLN8&qj#!Y%(4|n{ITBQ71&r8b?F$
zC$kyR)lm|W{ccrPH;KtPn>o9j1Kj)Gt5>&Py?XE7_r7eHK(7&|
z3ip8i1L)rf4+|F1KG44vo)Tt*J_`C3VYRS87{N}1epRS}r|J>xBIwtI{}5_HUjuzm
zXov6b2zCqfpM~SXA{0KpkEhX6W;@UH_0QuBCZz)v9X{l#dSC@
zKZwminMSce+#_;q0qA$de;4aTo-GHxTYN*@j`SBme9c1_P=ZM@FVs}?aJn5<%N^;D%#fvT
zXK3|jTOW~T%==DOP_~stPpv3iOzLuS{t}E)($YmwLqmf?`c%=ff{?wVwu`2xB6))P
z4%9YdKRrqW9#ll9sH3*`p74YuD>l9%j6RcnWt7%~R6Hr8ZW1sz@rD)CzS)4H{y>F{AQH`xAa^1mc5
zo-b*mo+_%8jINu1N2=aG=~09BxMs2h`$ecdRxVschN)&cYtO8jTxbr=HO2HgbUTMe
zMG55>t_b(*e$S@1$Lu+hRW<+BN+fH){;20q%bWJS>A~yz=dP0SmrN!*^xoyFA&QRt
zEnbsX9r?8m0*j8`M*no`SV)#AT`h@k`2kz@Z2ZIjS?Yg~nA17Nb6DaeHT*2=W;fvk
z=r-$f^tJSz?d$Hl33Y}P0-U;4W2*FzlhQ9O2e>?}&bBpYM>iJiRd;%5FR8L3$@TJu
z2G@YKDV~E^0R4YfSJ$sGn|*lzR|)ykI=suKc3|J;+tFM4@wh`rGx*H`
z?3+Zt5jh%u~2DT$ui
z=B1qhV3`r;g!TsDDdQRQr?gT&$xmzMvp%5}bNGF98ID}Wbk|@@@@(2aE~B;JwU(t3
z)fUr~3y#{E_2pd7gqijMa|SmKSZus1=P4C!8QCfR>IIa)U~hvp2@%U`(u>bsm5<=e
zw@j<&UmJ{r&^)>t9e+fASjLP1b
zyA8RC|8Jmt8e
zrC9#9u(I@oiM6-PuN-+vkrSNP81})~*~R^lFSK$^tJaZ$^N=p>2}09{nr)2xl~KHLZFQP_v6SxNP$_*Q3h+W6ab
z)>K<$hk_lEOZdLyeWig`pkt!t-U|C`7qGGp6nzn5xP?56t~6r*iAfaKEtEE!(N+5@
zdho@a7~;7=d4rmF=D)FAEgr8kuUXkOf+{2=>{5#}?h%2mgSGE~@KzC#B
zXi@Ka+S@cAH~7#F_)4=KHD4mn6ng+G;K7JJ)QdBaW`EfaRIY@$JK!QT4oLE5aD(id
z{1INk!eS3R7?B}LKnq!nzdLXl8Yw+Z%W@#2FnTy09I!JMJWZ9$i8pf3kj|(0n{9H!
z#%nB@^*$P-I2{Qat|5XOE2@(-5c7c$s)}_f%km)tnwjb=#W^U&#@Y6HsC2J+LN8jY
zpr+X?IM{A4Ju4x?hD8ZSvV3@60naP*Ol@0ukH!uak3Bx5j>S%1VxqQ+51&>_wpnWl
zEe?`lzxE}vSVWV{PTC*iYE@!9PV>kQow#=u+8WYF*Ly~Gy(E(#FT`44`zjLPuc}&7
zzXto;Q}l6QQLZ*Vz>5S*ZNt=H@M&cY{=}4|ay9N5j4-O1uq0~T!;@8NWa408*`~9D
zljE&kv)d}RF`M4J-j4GE2{-}(*vKG@yOs%Iz#RxrpK$YOF@#B+Rt)tF0
zk5Arcf$Z!1*Af*4On{O&`k`CAb;daOVD?|{%iVGb7_V7=FOWy@$%Y;b|8J1be2Dy_
z5RPEp{6Q%`yBQR-8iZ
z8RKbHmYE6hSm%i;Z&j3!u&es&HAAU&0NW%#&zv@1{Z?C*=#&v38nLUl+Pr42{%w$-
zGc5v`Gl%wpAx(0rbs(-Xm(dsAs!WjRn%ya!^@_L29fSGEY3tfP%374pc1Y(Y9e(bJ!S<4k&V6;B?YL#%
z+{8MUw|yNCkCBV4SFN2x+rIAH-0?M?38ONc+~6*W+tord%AD+|>=ZY8!!+kK`Kw;{tA2vM2M{O3-4{!
zztVyeedNbQ^_sinJS!P`et$`fv9%;(_?fDc!&zhgaIQogc19_^)SDpX!;@e!ONC~}
z0d*dok>pG9!^aHo$l8~I83!i`NIIHVa&ZcmFcIgb(oA`9YH#g6_+p4E*Qr2=5-asIalKBtH|do4l1|B6bSm(Ah}y1G@*5%Q
z9i4KAD7jTn6MZ`6_J^o;ostjglz42dJ7X!g(KvScF~f`6v&qNxT=$=KDiEUFAM0si
zhkosg9s0H62|d?+N~Z#0>Qg;U{!g6>gedv6p632cr{pvGJ=)KN?r}Dh3rdr|{j8oV
zpVM>2&vi-;QGpO8f1&5P!_;Nctk+g+(P)FM(H$xWO2bFzo+Lzc-pAO}_AJY&cZ~zi
zInD-LFwPSbN&sgVMBq9~L_-43E|kinxvIDxHu6uOi(8%1@`oF?iRV}r;?gcoVORsOAe)_yi~|SL(W|f!K>4h}cSztOfB25v8zqL}_3m
zSK8*os8(*Vua)`6l8M~Qm#ai(s@za7+Iub-s^*$Fv$AJOYeCj#uB-F;b+@8xzdJfT
zpvEdBEeObA&hC(njU}Tw=jBHC2Nu+F^8%}ydktP!Thq4|tY~g@=Nrw+nstqH-!trX
zj!!QQ_*lL8ke8xwYWg8OnvowiPm`-Mt%0z6k(kk-)o5cIjh1F*M7sSUlOZ_cuk+%Z
z3iKzpxMGj>AzP#1HAJ@k-C~bX3{BPRaI(X~lh4-;ucN$U{yJUj)Xv!OINuStbzSp{
zV`8Q?v3b5_>r%=mDeuE08{tIA&r%b7p*56W$;>UoyaTIkOOh+`QWbCE
z5hJ>L$g53{+BfYI=!ugf2pjnD`uCw@C*{17GjPV=AD@AD6dc2jCVAFYC%IM}`+>Im
zX(Fe$9o6%Zhs&AYjJApj++H)M*t_}}>Lt2QQvtDA-|?j4jb-^85Nx0k>||Z2^`>#tc2R#@aumFt=yUw
zo(DPjXd>NRkHkr*H_XRzdSfPe!KeAQ$pfpge6ok;VCRHGWwXkbvv{Ru>R@>PJ`|i8
zd0SQSH%L7-iDu2X2~_``Cp2P&ulwe0Ij+Pj^CvU_n@@GcE9bJVcxeovub*txCyxkc
z$Z{>s(Ip`4W0UIXiexCxI#QOW%CPUn)+vJzCV7s8q}YkNJ*o`WNt(4sryR)EyE-#h
zdEjxf_&zP0hraZro3Nk1eFqk;hw4K+Wu5y`asV~e7?z|aedHaI01NgewFgS>`5|dO
zfh=d-|Lo>$Bv13suslEwzlBu{`nD?ZSHhXDC)9Ibpi6hjpzS9_hQ92eb&)lQ^gwGu
zK$-40_`Eg*k@e&3VuHPAr|BG>Ui{azxgCaaa+0r3ZghJM)T78JEB(JKL@5UvY?Da0
zz-ki5Vo)D2o>*DwS}7S)yHiRiik#m0>#ItJvca}XeG6@;R6AAh
z(;5^IbyG2FeS;X1kMF<=Nyd&LOffw^we#+p+jL@f1Q1$~jNfhu``_Eq{4F~f$RI+1
z(h3osSu5-=^iaO
ziz;W9j)}a>{`EH|jQ7ll)t)-?gNL*VuXuk|nau33oi|XuyvSE1qyp(PM)Btu6G6Gvx^yQB`u7-&61
zICeUPf>Rq4IBRq#Z|xZy_f=`Y#GHSkv^`Q4qOX
zV$%WOVR?)2O!`;BcBA)AcY=455A-|Je8jW214px~O8o5Y1FBaGRrMW?oDF}&eE*gH
z&NvkVN_{>g#YHvdN%zASPd~od8rdYzuh=VQ7j|F%qlx3DEUD=;{+@X+nc5i_kn&Cn
zhEx{GMRNCXAFy9>e>MEoV3LsU)8EmKz837u<2Py}chRWH8H-rx!_*mnRF9?^}pO~qZc>yv=mROah`%1xjG+L`iqqTZe`hhSV8I+Ucf!!}-hJ6mc)Vi8j
z%=KXmrwfLjXP4GH{fZhtiWfih(yc7`m4L`$#{cVn8~y)K=erA8Ep{p-K(*AL_lU;>
z033p^lCeJ!zknxx4Dl_&{QEVG1#2h1mPyHs@sxj*_^nJDkF5~mPZD3xq!h*m6aNMA
zbxisNW9VLt{TK1unS{@E5b-yOZ)MWY8DLHLF)aeWpLkB?qliC1yg}vfCf-LpHX-mc
zmiRW}O)5W;ct7#H%3FvJ5RZ*%{5(i}JMp5*KSumE)!mCo`3s1DlS%h7Hh}o0#P47d
zKw@xcf&HK$pU!Fg^TeY)r!l5>ycdYKsO@<-l^?wz#E&H25zfaWGxlPbmxy0SJQJm{
zOjQNgX5w*wfYH?Z*Al-A9geY4_+{IP-^fdNS@FcbMf^@Cjb=DNhM)I{UkQLRV?QDO
zkHkB8358YOM?Bsqgf~$BVd7_F-vfP*_>YM{$|QUxYL_`p{2NTV3y((mbL;2UA5J@*
MhJSPM?=YqP4|sgn1ONa4

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_release_v8.0.7.bin b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/boot2_bl616_release_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..93b15b209278aeecfbd70f4108711a187d4af925
GIT binary patch
literal 43328
zcmeFadsq|KwgA2-$;>1?1RN0P!8RrW%CQ!RN^32hV3GlLAiuPKoMnq3*gUX{?f#2FQiQu`t=icvkzu))$
z{?P9uvuEwK*Is+Q_Ir#mOi3URLWYS3&Ib|1+>$=&$H;n9h7i%9oO+&;L?U;>op_%3
z8ofpQEcsa?Nk9Z3A_*ZO{zi~v0TBp1+ox<_A(gQ3*FK8aFWWDRMB&SP(ZSxjfCQjT
zlL$#AfC;$qWXC2%oLGXCP%->t^AK`;`}rmD?T>#kkIsLkuEhWKSsc5y^8ZTXarws*
zcr1a(5_l|u#}arffyWYfEP=-ocr1a(5_l|u#}arffyWYfEP=-ocr1a(5_l|u#}arf
zfyWYfEP=-ocr1a(5_l|u#}fGeg9M6GduuG&L{{b^S-8I*A%@idnMoguGQFpT`@^0+
zyi=Lp%fj!fQ24yeHB7~wG^F4wuBM^PO_FebqNj!-hCRsiCdN2eWPrct9W0ydK$l~P
z(*I5SSS>1j{P+J}2D~SQEHsjAF686dL0eQW!D-I!LWfOjvotMrNHeVtRTOoi$pt;u
zM{z9zZiU}LG#=ynV?2!CiH-rT)<;zvQbX03^3o^?z{t?6!y=nt;nnN7WJ-X3BR53YG?cgeghO8j$qQ4aiu=5m(Jq%|Adp$?H(xbLUJ`O~nYe
z9*xV6*IzNcWyyDEdHZ^IOig7zZn89V_nGq5L*Gz11Y2;n-p9$Y{$kG&C)Op>IzkTeR+~8cQ=NC5oL_OE_HbO!6qAE(
zA8gXu-N;|Wyt=Cn6#k5wkRf%53}x#UxG4P->U(xI(cnhRb}Ktkk*G8
z>xWzt=t4nLsd{MtX=r~i@x6#k-UWLZu1#O#SI%mQwONF|wTdB#-3-M_vh^bZ)T4c-
zt4C!|SBGt$t{yRLhB_o-hI+VmhFbN?47DCc(;P7P!8$M5+1L=gzypJKQb`%;R7rDE<6XTDPGh`itHhM-;
z57MmUgS064V<_`qfqEuG2G4V_o0bxBQEvi&@E7$KJmV2TU7R
zmNWU5iBs>seT~$CZl(>Sq%p?AyWFZ!~mR$X6t;7NGn|-i*mZ?m%d{Uln6=S2)n@WlvjiyG8|O8*q!l0|?!P
z31vBBtFjH@0k_AL}HaB^LUMdw$)XQh1kC
zm^vjB0;7vgK?@ee8@V0Q^C+L|*6lbkNiLT=lv$h=Yyj(`&i#f{*0Zyx8fw5(obAdw
zt&h<=Ev6u>eyaX~d_M9aeGJh>#qGaCoSXeu3uz;7KqN}giBi>j%nR#8g(T{*#1UNUCojXujDB(baG1`U}EH3T3`
z$G$;+AD&V@Kw=Ri-7n#b71#cp-^Keu?E@M$*G({#6=f8`k)bEAlJk<$$^LAX1}rz$Qta
z^pZgtX&qvq?n9--#8;{;?{*=dwFj(xMZS=3t)V)hK3gwt1&o-W1n!MiEe<)Ibo}*t>YVCK{K+ZJQ=49EOslPs
z9Ykg8zsTo1KSh?8I{SJOwexV4OfoTU`z4G!lB@}|3o*1Npf9q~(w#;6gA$`e$HTM{KR?!=|V$GlYjl4_EMoTfb;uZK|%
z5zEjgB^EMVVv!?hL@ECfM=)>1!WhHI4MB`-2(lNq^)heB2^iNEWkB9KbQV%p1Te|X
zD!#}cU;(JQih-E5OV78q$_OslurD^EG~eHU7%9VWBPT-^6WwE9QQ2$M%Me3dmh>d^
zAJxf>oG;p?$DCW%(LH>dpL;g9D|Y0Rv85KWRI(=7USfUV-e8!{$U>0)Rr-O3zRY57
z7F6XIH4GyuOD@@C)KiEtl0EkBH+uPhfVFUuImTFAOBQA6{K|`euZ|*RQUmZnwo^P+
zspN0fQP5_J_pJ2bf3A~RNRX#zWsrr;B6(E#B)_}}WSStsvXx@qLB7144&pnC(I*Hj
zlnzF5M=*zcu@&WG{;1*T6>DTpHaEkX9Sc@SvbZLwaT8?^th~>>F#_$=@7oJC(RPo@
zUfzytMKmw1^aW06yMN_x`E`crgdxA^5X)27QGR1x7QapI#wWF-ioFfUeVhM8W+ixU
zfZU@jw?f{E7Vl-GS#-7D9yqsyp==bh!GQRZ#=)CnN_GmEPskzp+
zW{5rB)@z}=`v?Q}xoC4_5kK)VA~{WN8%xrR8E7mkLfd0pcJ-}!d{G5?mgVF3LyY4S
zFC&KR?kg)UH*3G8zhlMWw{z?Qw8}O%TKJ7xNsWSvf|(hjl2`_%ilxpjS$jX!!QC)vdbMGj`{
z<6C`bhyKbzY$f*M#$SwkVTQAO1ajXkpHOmD(=~$l!n~~NlR{Z<^#K?;exnY%9itv`
zB}TeO+X|yc7Dk7xT6G{sJ-j+b9das0J&KqJ@QLJiVP*@ZjREblaygTuZ5>xnJZGU1
z8)oJ^_JCCaob`~4{T_-lDyy~9;n`Y354GslW~s||T!Yz%`Kwz5$52$H#gyI3kjVRR
z?hXTU9%c@EXmq={cFTVvN44PwbJHm0e!L
z)>hP0M82U#XQIb$tg{AbqaYyh?QN2sbWn9rT%vxumRaYI)FVhDzo9EjMISCssSeN@
zTS#O{vLem8E=i)6@1hiB21C1^q12l?p=ZnER-YO+#q@@WvkpRp
zWt}|BS8Jv|j
zV?M07UGH|Ipg0vBP(5A$uvJ`l)=uhMXKluoV3eq3lD|S4x?95EzAg!}YxIy=3ZX-P&Ug}B`~_ZSCbY~|`x(EoS`0@iu9f;z`0R$G#i5ytT=
z#Jrp6JnM9QSuX$A>#~5!;6?v&UAB&U@1?C;MWN=a>&U&Bnpm=NYqbS5ShkIyvm2d!
zseIceZo@=|9D>$0xYwP{GEwel>j2JM>V^Jr!QJ<`GaRYsJFlbj4S0sLHY?zjplO7U
zs)=e2IUe6QrG9E{QcYM6zp5Lper0n*c$@`RSyIUlUo_2O@@hY~Do_^VrlV9Pmi4kM
z%dvZX9ti=7K`h_ZiUML2WBIP@5^N<G5aI$Mr*t0s0ADOz7`~4>lo4>C9-nBYs+Ga%?RUKhQy-sZ2@flkTVivi-BgQSy6?&
zQxePa@A&;mlY5`_%f)u(OQ_%PqAcdlzRKK^D=CRR{s{^4Ndy;Ickzf
z73w32DN)J@A)HWUwexb^A{AG
zpi5*eg4O#H`CJ#+M|jbzlagBs~kR%32t6Ku@6B(RD(
zX!Ax~-a-eUWmVDBmsZ2`NkSY)WQk{V;lm$I|t?0pBH_~*^0JL2DZXX^X&s$VQKE|%TH=k
zYgV2o?CpK`J*)nh*EY3@UcT;LRWQfT?M9vcYSclU`ue7SYn6uf*J?;Vt>tVoDku!F
z#oDme1Rwk>_+Tvfpl!O&V)92GjWB1(QjyU`u{IAj-(Mz`ws21|XAgq*TSe^$SD61P
z`n#b0wkHF*4>>-QCiZc-#tD-wWX=MWX?4@;*a=M&Vplgl9lbii4=}n>5%&?zn7F5-
zq=+za7J0igfQ8tzZV%$$%|Muo08!guksgii+;!0PxZ>%+i909Tk-%Ec0UtQ-EIudm
zwYm6kPnHd{KltswC6|5x8eP~ena~&>dm3g5IRyEfJ&tf={<5clm;z<}$
z6%_~(z=k7$ht01L(=gEss+ewnG}d4_=Z_RL|7Mq*F?IE6{P#fYy2n1-$VhcF4;N?0
zlCd~;k}n6anvFEXu@>Ur^M3S`e%>iLzvdho$o)~ZNpAmn@BIT-<1;d{sK9R{=E|?o
z!UBsCAp0fkn(;^2++CRv+fAEN3L52A&D}`1i3X=9Kl-t}PUsK$R-YI6N0Q79*
zsj3Q-pJ<)alOfLgYdr+}YtQn#skiM>3U+Sql*?I&WWkeI2I7FwpLDg#18fgt
z+526?1G!y-C4VkhvWZ)LGX3ic^H;2Ap=H`M*g8cbgm6R_F-k}2DB`s$w
zk;c?2nZ)wFyC~5zROx3sAy!~)mk>PB*Jkh3KWcp8qkozR0vgMEK!4J^>)wzAW0
zxZjf7pyv{}*)f2d<0h5K(eBkZv_gz1lXNQZr6HJ3{n;$+B?VP^8}ka7X~{@Y=xdu~
z!*vTX?7fa<2yqDd1<^_xz_ZB1MU!lDXhDOzUz-rI$w&36{-{l*9_35Ezb?2+)TgLR
zId~1uTRllVdX6mGc)M!V;;BtT-<;B%bo{l(f;Y*xEQQb-_d|Hxh*hy
z)e+KN^sfPDCg=jM@E_38XIO?Vl_(1H3N=ERh8T_F0=t3LSVIZ-lD3$5b7j$#B1ij|
zCXEM_4fgnTf-b%Y*0~}Xs$Htsn61aTUfIS_k6(`$r!=ZV#t>?-LadvrwY-9SQiJOZ
zp?~#=jV$3)4?Q_SS5P>imhY+?=ebd>Z1}ag2v%z^e|)d=Q=V>+^Za!;dw~Dl_gD+`
z)n{xt`Z6>c#Lww|0_ajOV~~uQ&cD$W0%L#w7MM>zdmdJFsU3!uiF|8U$b>VS4Tp>Q
zTU|p;Tt#sk>hWKF2KQ%BR;CVvzftfvS|)=LCyZ^~TYgu8Z+@8E*OMG%E8>D`OE|Sk
z2D8%+*#w;r2V;=I0lG6R|0J!vzQS`LdZH%k7;+zSGe(nF$qMPf>ug1CsP;W}LT%8b
z!$tAt=px7ESq|JEA1@9%DfY=yu2vd&VtOLKwGDb;nPdZdo^8}^kBv7UE)wv62}($5
z+8%qnczfeT_IU9{+Y#$P$?;}7jG@~-`Sfm>EAbz<$)MHV>LJ%;m@@J6rr0yO^ReaI
zd#7vK*8DH?*2{f
zJ%>DXXkc5_=fr~JXYhXujJ84rZ>0h_&&a+K5iYC!Boc8pF#b+h)X^;b&@D?uvfZRgqTx>JUdLi^8M
zccde8WE+*`P$eQ5W7Ar|eSA)eTm
zckf?wgw$WCAbdiOm*osihqcf~6qe&zU9MLTDw3GENf-Fd9g@)|SVs?(
zHz`_yPZa(qLU)H%nednfk7e>Wdr3#HdK8J^Px7PHLNAi=H>{M_$I|VGOxdbhsy>hY
zoUACaA|qEP^|%n0^Wk^XXZYy(IabM}GYSs;O%jyC-?mERlYqXTd^*%OSl&e3g!m!x
z)R(g=9bOR|nr_1Jg2K{PQysFft>C4<68bu8Ak1sI`0Gqt1n#jz5`nJS=DQ
z`trQIHiFCM0_sxgEN<=6Lwnuh?q}&(6Rj@2heFKEvU_y49`+6|KT{E)OVO1Z;tIbn
zOsNg1%@0)s@wK#se^PbRf6X6nuQdv
ztDB^b%YEBm^b5TQhCm(L4shkL79x|YM|a4bx?G%gaqbW1=ABKuj~{Pru0LISuI2~Z
z>zCd<|Moc}ca{j-@WqDB_E%n%{%sPh$#{^)&pn78FR4e&C&;+$xai|X&I9>zfrbzD
zc?Ot!=CuX!v%6Ki8T#yBx+D;ZN7=XS>6Px81nt>?cuDst;~v;&ggGW(LPuI?7|ZR1
z2r%Lo1bq;Cfb>-`cK@Jlh!ILazZ-wuq#p4A%6bsl@#?S#2qb-9pcd*uNNS`Z8>AI<
zHydp;hBQef+!hXYD2cEFY49Xs1=C=YhI+`1p_62J1*6v+M@*8ec=De%^{Dw0_2|_S
zwX%s+t1gm!>&g&*+e%~%@sRM2xx=L)O%ndCbHV(ObA&N;gM@Ew2$ph9FjL|G)D4_8
zA*hwW{ZOA>J?b;qN9O%{R4@{d^dw0`CrS9NEr@pmOyG?#?ot{HZp3fh^CUmm`Xq2m0=Fb?6>g7oxQ8@bx56LVVQ3;&_~+U{PSBq}keLkp
z6Xy`@av5;03n~rW0OgyYya%t7`5=uZnOgZ7lA
z9UKe&zy+MYD&pxnysxEzeJwJOAwP3-TrRw#y~)TXxeDGKY4}=Rt!EdbTTjPM#Cnncg`o&d%uBwZzDI~t>kFnPa2xPdZ
zr>U;WM6aj88^C%W$n!XmsT}J~X#cpU&l-c96pW__wD-23dh|E)H=)fx9RfR2gf(l(
zAJMp`8Ds8n_K)^-;j$0pMlQ&W>F$b@lR;w!3nU}_C#j~=oWO`
z1e$vwG15V9YUM8y{s-C(({$lxV_e_PJ1$)C9tGHy#2C6kp&tH=#H82IU9A0XYdap<
zYH0BFQ5WS>J?+NO-V*zht?f*1D8PP^U)^S`r`+sCmF;$q>%SDxn8&nYBVdBo;~niU
zTEYtK-sCUR&?W_@&fjQ*m1lwjX~4Mcfec1DSR$i-0nZjKdfB&Yl6#W#toV1A71xjJ
zzFKT-pxu7_Nq-RAvJ@=No?Cxay4wSGJ+K{r1M5lWvh43u*90HI^q_|C4}eurd|tAY
zUz
zK9f7S75I3?YJ_${^bxGX(f*TVUxg7`h{u2GolOvbyRz&h^f@C$SxJ2bjEct9sto0Z
z6+?F0Jl8M2gKf&u{_dt!*eUmb^8y|u_|s<~{WCiR4*O$)J+HF)e~JZm-pNd8?;Q-7hlGE?6!>-8vUlu>Y#$ya(0Uj#@)YL
z+Gt6TP3*TXSWB+rRpeER<4;OQ>Jgq{Pi;y%PMw?5{95Dd^=Y-nPz91UkZz-MBG*^u
zSnhZK9(dI9Pg)klTJCjAcNYiQ_|9UK0%NEY8^2B=gFQ=`#{GFMe{~LNahFL>n>429
ziPy{`Kc(5#8Tp6ZCa6`b2u<64lt-(TH&Mku?;}f|;(=N@1Nz72tuRk?d+q(~I1Ak_
zwcPKJ^7o2mV)@xmh2?*d&v>vD=F5~{?U2ILXpp&CR&@VfQe(-WWlYN)u!uOK+rN8|
zT6qsy+8{FEXNT;8i3@ojQ|EKtBqBxj2~5!$9`wu{Zmz+AKa?F2xC~L-*{!Fs;99_1O-qgw{SdI~GfOz`=|FLI3fBE)L_^bYUvw?=Xm
zbgN_?>&udcd+%4Y?2#1F6)kPBis)-w^}%#okAHV@_n@F!WBpRtkAStsf_gWFfiJ9g
zdSgmCLt2NNGyZtr-$UKZWjnkWw4O!W!>W<*cQRLqWES
zF>5v&8$N~E(!D}y!{5;sT^hZh@Iv9K!izQAV{U(7X=^~+YkHDXP6n_kER*4n0&JEx
zf0W{k84y3DOa?8@t^#g*fZHB`5C9=ws7ldpop^rYz4upru=VKqqieIQR;1iIF`IL@
zR*oVX@~!3(COQgW)BnPlt4)?^4am|-O202u6J5yCG6d!2=T{oM&lXyeGSCqEz>x0)fSp1w^y&t`kV_}2QyO{tlnL*QUx6UyH%DM>OJ1lJr-HEMIlXc
z3u2bha-JcdNX-vC$`jNR#?WuL&L{UtI7;TME1`E}IVEKdVpfS-W^-caG!&%o!_$=7B@7gEAKiGdD#EWm<$XZ94LO|Xr=}A2b4)V(hhuu+{HXOR{a1MfSoc(j!QU5_
zg9oapQ?L`-E=MZ!cRe9m150!Czfgs%W=m0znA5V&a((Thb$b%
z$=)RnF=uwUhAv_&qTm#SDOk&I?L_vzn-BW=!L3Wt4&zL7)unW}y0i_(`*irULY%^N
zO{q8HUK`p9t;~tetI7GEBVwnRsOFL=b?L~lC5^G{k*HWU4c2(XJu5PGhxJkV;`k<3
zt7?jGjLwP4yTBRNVeaem6j2x1NZC|{X3lU}i^?6tZ&08{_PH0+bd793z1AcDN^c-n
zWjQ49GcIR*UN-nuD@Qdi8+(zRs)&@is5Y{<$2PK)Uy$xngkwsn*-lRLaO?ZIn^GT>
z^KG7CorP9Puyq*n3V@Od=)kHu=FS6iryct!cl-VecS$wIc&!A>OsXR!WjV20tSyjT
z9zOq*v<};hVZBP`GuBcZN1SIhb9BVa4Ho}ns2ViiJ%-=t2K5YkVPHMtPGC<(za(6H
zgMY;TY$yMdHUE|WYRy2pWa_-H`)P{u_;>s-8o>W%&A;P+$MXa05xITg5BS&m#M^|C
zA)MKdUKf`0ZBD!iG$5tw&qk<~iZPqP!Xh-Wu%?H{mv~L7^#ESsbFD8;rBbxhHkOl<
zH^OOwgVQ#uOB=?3Esr5ih-2bdEmeOzLM*Q(mK|7|WgMZ0^G02L%(70e;E6;m|K=ws
z>J3!N$YV!QWK5BCI*EGesTA(9%E|8wqbT$o_+;sCW0<57F#D2^DbM9I8_?lgy!Ng&
zGRqq9`6E9#lk(3t=tY=qp=jJT?-&!ksrr_6;9H%Q@UhTceWE{6&ExW>)PrAp?J|td
zDa#=^{-0ea3TEsK&5bg{3b(X{MhYYUR<2|!RZeO*LK|uH)y$2sTJ3CQBWuZ{$8?Ts
zWRFE#me*oFKIlUHm0ZcAT9xirAf`AJ#TR=Yg_BNI#)t2|@Lny%v*;XSvQ`puye0?7
zwbyKwdD52%$@uj<%^|r&YB|1yk^6GA$=)ZGA{3M-cIw>-0awp<5Y85&b{bI
zDNe~fZZ40DiJNK;F{$ED>oCP(Ut@hn&FM{JWVKA0S&Op{?X
zHSXpSSm}ETPP#vOZvSb>*FgR=byghnsOE^9cx}j%oBL|C%?j3!Jpe!vaCbu$6`FASYK!(uik!%6&Cfac3U^CkTYcUT-dU}hZD+3TeH-2aO1^FVhZ(A5In
z7lG~zKsO5Ljs?0A>EJJ_CYPo_Gv`Cd
zIRrTcdPn=LJ^gT8;t0Tt0RGdiemKUj26!IE|Fj=|$XUZdjQ>SHyxK|U2*&@sACBqd
z0iDel|Koo65r7u}T)_Y6QTS$nV?KY{-VZ+r_;mos_0IaBAD-ug*J1pUemHIy#>eo1
z{1*WH7{GU7{B8aCn12jEhVhH~;m4eCf&KvgF+S#Bkmr_ud@LU?-kMkr?T){S94wybY?{~wRaej%D&dYbidT_lT;{4lpI7>%|S4DRZs#wv3
zZWiJmgSY5L!W!^!ToTI^Q~o$#&O*!*B!ek`EXYjM1*Y_Io}A@Bb{k%x!!j%aOzb~J
zdI?AsR+&1WG{9Zn^Pv;|%w0K)Fpo_Qy3p^
z)&)9jeJ5X;#%H-v+jXx@+i~Ke?!b4vLLuXG6|(-mg?tHk`4S`wqlx2Yk?X=A<;GuI59xn_*Og>)pr7)MqQmWE{yHil^jOaDv^
zHvYNVCjw%WoE^qB3-q%&SgCCpNUN~i?vehxv`z;5hfl42l$R4{FlM$>o{lfW*4u}q
z-+Po=;pu@mUw&@)(|2Pk&E{b+mciUEJSk^MA*Nv;UfAS%I|Ofq5bp}&V13m)JJv^t
z1EN>FRx<_S1GZWd#0MNw4dG~XqEWQg
zBF;y!N(?K6-q1z!LxYbH@1Ci^ZQ829{tHyT@0S8Dv9R{PQhDb6|4QWq^w&ToP^5zE
z#;q1>@H&DejPD8JdxH>R9bz38b3QM|darL?koDl0ItldNJJB;&{i?uFtB9*<{=G1{trtD
z_5-7?ej0@^)^gDhI4whEl
zL(eIMww7=>&(*iP$~elvzYV}=0B-fd58#{}#JH^i8u}jkcH7pNfQk0)*DE*E_Tq+K
zLVx6c_#XloLi_uWnkQ=Ss=UW!s+D8jw{5F|ZzYV`R!iBQtPg7(eLS*hT=V#o(Whh1
z7|ty@zx;=HF8=jW=4@FwLuB92RHN|sk6T{-2eRDNpn@2F+p7}EW$LQiwL#Yh-x%`G
zCw_VI*Rb}{cOpB+b&dZm`hLs%E>CtQ^B+cD`6FMaW{D7`N7vH1S_3
z&E7Iwm0F$}lXf~SjlaW7mTg(4T3)_9X2t0hX)Eunq~6~4cF4lYg}@1kzyGi;CUeu^
zF=qHxjoA&qk}+%9EitNz{xGAwJ?I@CJ{BlV{$q~0Bg)O%y#JWU!>f3XCqOV>)&
zJGV&GpYD{Xcb7}ldut@>veOdvXICZaFYZXxr4ka#l2Dd}vLuux)n!vjC{IFp63Ww1
zo`&)?l&7IQ4drPlPeXY+GuRteO?INpU<9jxJLN-6MpboRSoV-?sdcKl`}(TZcCw3x?Y<5(z$p;JnVzUZHuL1?djsak2c5xxRq_>c!_u$zKl&7{?0u3y93TPSNc8A%k3P+;Hm0NhgY<=fgM
zaL3lbO?N-XO^>T`rKVY3smTvvr>yQLx#{<;)?}n)a_MJ%Umd#G+^n5@`+eVkSg5W(
z-xl9j@p%xK?`E9Z==+baCR!;8oQ%qn!LCR9S4Y<*|JLx;#1Uv(;a5i;wwD`9^dk_Q
zL*05e6oo4?@LD$=4(ZiVxhxXiR!7lUms2Jh4K#|9XI(yJyqDi?rax1o7G%mG;AW47
zM5OzW8?p+j3w@GBA@_tXq|V-rNZRga?Tzx!x?EsT!x=-o2JYpJkURWGC$Q(S+LGHQ
z#Wnb^cICL9?(mIm8+t)`|!heH?GZFK56v8c1?JK1~)<CDNldu!sce6Zyl_N&Q^?uRe5p$
z79EHJsuqg#$>+|n<$CS%+l42!4B3EA73L?OVe<{wSYrc;qNq)MsY7mWJX>g`9`r#Q
zVF%F<9fy4kE9H&O0`4_7pZk=R)(0beo2zF?&qj;CnK)Z`1@A0+br$B$162hHnCH>;nCr;eFj$rBd_j~!2XLA<7w>QG
zBrg=?PwRl2I329YFj$YJ(!pwAPZ&IJ&B*OWgZ1V5
zEwHO2<+kBn*KUnsD|!;nl3IW}DQ8A1NcXJh@m~X{OP8Z^z+44dT~lbutwrv!9YAp|
zVy3SnDj_F|z9RUMluJVVQvr$?0fw9~1KLTZiIB_KE~H!tS}wlZFhzXp`o8$yE546I
z*TwfNysL*xQ0T7!5j4wfWyy@qbAe|#{gFRyE9h@4i}SX!Sa$ea#2SB}6IgPN_P!rP
zS>bhGteJTFL#smHV=dzF*EU?1`-xWxe9xd0dFtz`U^f*~!}LE|cL}Ko{q3qcAr+@T
zRt0;n5}fa+zhK2a!TXR@R60aon)G7u>G(};D2ijB8b+T#8kLM!%5%%!YYEdhzE3RbWH*GiR?Cl^E`g=n^8?qg7XLjQv2VA
zIQ^wjTouI>aO|pk0-vBQ{KiGaartG-ycf$^0@kGQ37N&Ph8>IW{e6kevA?Pn<4JdM
zgYg(|y{XtHoE6#F!}0BVD14%fp%Tbyy#;dJ^;fcZzdB^1`5T=$mIt)-zQFOTyCqRe
zG54}khc`RC45Ff}RHRe7TA>$H=ne_z3(znp{60~NPcN*QrUz}}v%5~X!^J0-*UZJc
zYmVFS_mRx?J8P$0!e2>Jms0Sh0r*A|oZ<bCX;rO^l0gnKGgqCH3FFKMKKZm6HpPq;WtYhxdaLrk8d)Yzz1C3O95bO1Zcy
z{c<~4`S_B<#c)QWNq;iUplIgh7{`T?_4#%-jl=n1%VY<|J90tKJkcRr<_o=u7vGgD
ziCQMu#_ou{VBc^SBwfgXRq$)Mz0SN(fZrXMtG-?M%RwVcar(twgdTq>YTF~FYvovHB5g6ZYtsPICy^opPPz5`C6kiE(DEUADNT?L#-(4`hRoSzTA2;wjA!>z)qFe`p-bVmIYQn}TF!~}q%;L3i1i5HlS2EwwLRr<@)Xl@6l$xSRK9T7yb6z0S)<;W4tr#|E$_l<
zB)XKOn$<&YBcEgNr7Yyw|I-)vD@~$T!R~q0bBk3MLw*>Y^QkueJdA8)VRJUehhVUzWr2>-{AE5$yu9lO2nD9
z)x^QgYQOsuBNvDYeil8EG41%tvHz*v5!E8^`u#9AGs5{R<(-7I#M6l}Gs@-0vatXc0Esm(b6&Zimxa
zA*Wqm_rS5xB0H&sn^&^YIbnGg69>1t%Jak$mxDamuzDZEW^!lI8z8q?AHcnh)}1C3
z=U%U$4wOCloO=kKL!D9@ry_`CqsY{{vqHGz^aiVt`-q4vRA;Zm%GNwPIc5H((L=n^n_6OSt8#
zGt@a4<>^cgIF$+ZWQF!)Tf?n?sub6T^$h&%|2R7=2foH7w2S-}>bu0q77YV^m{fxA
zIonbN^nbi%b@d52GJ_ny1mD%b-_v*wEOM3gXIG@g-?DQ_tj=bxKW@X{vil-Ga>MSL
zDVM~r+u<+Uz1T5urXW*{Q3p{O7
zg5-T4D4l$N2m1I2c)+m#8r8%v;N6*wqZ`~88egIKREQkSVD)4zwD*K@7tE|E;|Cjtdq#E+VVp;zXuE;mx?k
zMHJ*;aN0m!9Z2|?SOY72(^&)i7Yrc{LQC6!`g(G!*p9k-;0OF>K4MI9z7nT(&z>G>
zuz$b$9$)JXbg=<2lDfN
z#!m)L>5ObsBR6zlue0_Bkngv+6j
zTPyNrYAZrtAaJeufju!(%qpkMP^@$}aX<=sXa+kLmm*uO-af78D=`AFz4xmd3x-Jt*?|wdZ1c6u6e!{!=;p$xq;ZHMK$*s|e9Z$(OUj
z7;E>Q!LA!fqGqyEG2FPTVQ@KHK^|nq8pyM7<7@wmdjy|CS?@q;>yZPN+~Rkli*SD<
z(!e*W@NNM7S25-IzHUXy{#kr$+*XfHK54QC}n9%>iZ7z15-EjLYq{f(-j&LpUwrUPWFYU#y@x^(N$A{T)CrUi^
z5^cg9Nk`V91A39_h2^~fa2WrzzuOMc<4^ZcHr&Yw{yj)1
z4XzEYu?HSpiXjcys1L5RNDD8|D;|z)qD=dw~qZMb`8ZN
z1&HOWWOosKk5aI|*(HB;ZX1uINExGulPmy!>a1&;aSJ=Y$7k&DNkn|YZfdQ9v*eNZ
z>nP?nkLTXpeDsAkr7h_wGH-NFb8fbdzjI9zZIT*DIFYV^83-qV`&DkZ_T$dFOE(*n
zf#>343G9yQd3&)O�!D+>1Jt1M!rF7!U3xGVrxe-2u3H1f#QBk$+TTOq_$T4aL@0
zAUSn!`cG~<4@gteG-#8lJTVtkHDaZAj}goRD}Cf4;ALpqV2d&
zKf>L7K_k!3tj@SsxcNI{NS#+y!{?V6y8BnK4D)pf+y*6WUf3JpjH4jc(n4cstrzxz
zyh4lBAHGV4y#U+qs>Sd{6NqoBGkB~Rmea#U7+^*1YOI_(r>1WswI2avpoNzCFdtPl
z!VRn23GzHxRe?4BwG6cb312O|+;<<3fuz%RAgrnWXi};oU0$Y+GI+u295q~%R0lVP
zNd1~2?&GKlB7Zg|SRAb4lQ5g}ufXdy>QJpulyzE}q#oiPd|xej*Lz2!qM9@e-7o>q
zUdyI2^q$vX_S&LpV(6%&=Ns^fTU2uIVVJ>&Tg)`EX<~j|8yi_4Y2ZuhWU#LPUP~{g
z)sqxOvwQPl{n7qWTW>Z8D=T}WXm6C?(xt;U<_E&u>$`LUg@7*5x4ondb_THINc}As
zKTkOaXPz$^8?0o=57Z^q#rX46&m^6G?PNhdSlb5LH;?;-xD9JEFxt$kzN8*}8@}JR
zNn(*Dz_<6Z5h-&s;kl3+{&Qqe3d%sc@77)dX0kBDyZmmmb`HcK*d6X`g>}m_SWCkA
z)}*(?*r)VGxFZ=yuJPpu<;wD-xS$vED-_*uL)?_>uD`t#_LQ%>2a^*lbUVqz*Shej
z`HUMT9bO;EA45*S(gJJQ0^iJpSuP$=$S%RSY*}Pj;@=YR6tAq2o?(HPw
z_U4W1cz69~p#9TDOq-Xb6MUeafS3fm3g4Y03&{z|gY&r`CH7eSb*Q2(l)&dL)MfW%
z6^cBT$vxD!kArX5UTym=ek+;duFnQqPn~!1X_s|&iG1#>s)#BDlZ81B=FbH4
zhA(Y+mLSd%w!9|!3ydif@mv9~X^E$j!*VP#Z&H+JRxcSRrq~`{7EJW`mi+RtNAAVn
zk%O;>26ZFh?mY6@>#|j}?54HAV5eGo*P95Z{g(bd3GNSz)Gps&EBK7b;BH+Jgzsgz
zTU(alTN&=wwn?AR*JOjaa5(EoUU83Vo1lhwfUknP6Y@{w9WuOrySh;=za|6PrNTUG
zE_|C5Z9ZYtA3%|Mqi!=2H88uH-})&k=T^!Vm|i!*Em(
zTV49AICm89Sip^Klj{`1$JUv3U#0BGU`VABB2t6c*J3}xHjBSQN?wJ#Sfy38I+?LP1et!tW3mf{DK_Jt>T8=DQdrk}P%J|(QeOB;
z3siI5;5*b(QHGbt68cmtUb%%;(eI4AbL3WtiI&{%U-_+F$nHtsPhkmR<#(ACWTQM#
zMd*iJR6);+r0xm&XMq~+)J8-KthiQRvY4wcxm!a$c=|dXZ^{@lK{@mv(gyerR96(T
z%ddBM=HG@j%M=?!&Q?ZP@%ebXzC&_6)r#PzJ$%0s*6_q=cCjp1+CW1LS!lyg((&Bryl_?Z5ha^8Z}jC3bV;4^MPhH_3izi`2#CFz-&t|B7e
zx`iUXl3%!Jl~728znrKQK+4P|yfSsp9HC@z__HfV0jbQT{{mXNaB1p%<^1%wp(#SU
zg?jZ%QZv()bLXdKz9CfVlAFN0Az6SaSG)nGT$PJ*OA#c{WUO2G_9N|@wrEZ&
zASR?PSvqg&yoGNom!_u8Pj{-~p
zwl9ES^<@a!9*?yT6vccD78w!WCmXnbvEhe&2(BTpf(#Q49Ij6+gT*0A1LqEaElFRx
zY{}aXl`-*+bp9>n)P?isr={|5_2arA$_y+#mmWlYPfnjRFIAa_Yj9F?iqq*of7MvkWwi4FW$S;5jdIVMN5U&pnItG8fGgY-Q1k1+$h%&Jxmd
z7NmyH;@=pU#>J2m9yuVb8IT?`AU$?Kdfb3CHX$@Gk{4*ti_8?BOXn>}UjixN2{kQQ
z%A?fuOtf^#+k#yzdMg#BFGv*%tw>$UzcFW_0O#MzL<`)8(X9CPTG;V*gi&7HRHz>CL@1d@KQ8cVhtYHEt^SW~|#SNC2VUOMCavx=do
zgU1SO0`~vAf5d;60dUBZp8Oy3Pyd^I2}1PFf0GaAN!&C4O}-2vFWtY%mm~D#y4fe^
zYU0T1oAhs$vL|P+2tIu2?$wD&3%_jsQ)Bn`z}2fjqP;*v3eO&R0#Ar=!7yzsan}>4
zzqx+@^F96_<=j1VyygKP{E9RG5jkO)>mROv-?z
zWxt|tUdDJpAJ^;pH;~rAv@3t$Q^*GrU<>{K1|s0}zsYyCx2M0fAP*M_oG*dA2Ltl4
zoLv7vM}q8rACUjRl?hMK5uzcldqDng1M=kon`SNF6*aAX)$f^qUXd2;z3gz&gITvK
ziB)akX9D*5PB1O*3kY5}({%cVdEJl0?gr<_e|7C};I)(=@4TAaT$Ch?5eCrv!z9%G
z-^s@%U*&sZNfsWi^dd-mJK6tG{Ddz^6hd_JXsAf&M6c
z5%2167A%GC%=H39G8RExnU#?`?`?=%nd$J0(EK?IBXHoGw`ghVQvBpsqB%UEEnPBi
zfiwTvS()kcAEw0&D5udlkuZ&jSxe_FfdWf-O(ZV&#-dq^7S5fUnGR9BKOHe39f{@-
z!0As%41h0r(r=`dQVNZL^iR@D(jTNUGzQWar01n)Ak9MhAJWs(
zW=Kzh^!L&xX(ObkL%Km)FRg*}97tD7ZPIH}IhqgYcPK9kQC?^zr2m6@it>hZ4y0F8
z&rnK8|39@|4OA3YmVVXURfVDx2;k3|I8%VM${;5~kdQ=dBHbmJ7>6jC?8XFb5#5Qw
zNCLxKcXESHF&w;-8z1Od9y?XWDeeZqu-i@Hw2s4GdL2m*5Tj3GG0(v*--w96%^FY4?
z`c+}IP#}zF?Vw*1>fw`mJUaw>i}0VqR?sIv9}s%r2K{H@m~asEdC;E;p9&v=
z9soTkTo+Em`{fPLuF+
zH}O5tcY}Ui+#bhWq+mhq$5y(rTnHj8^jj%9;>Tl{yiN#xl)
z(0jz);tr%2fc{WCEcT!tO^M8bI!Su;>VVz^z28;{o#&aNkbZeJRHg-fs!DMH1?($kAp6&1$f=fUe|
ztIHQ%RSTrgn(7(Wa@swq_nC**8lFE3YrkbAFRc?*tsTq6
z;9^i~V@;M-(BY+k60fB{qpwyp9X_d3Bj0Ib-kwTGuu$3e10>1s*5s}I_;=HUz9bJcH<
zn6o*?bJ(UNHTyIhVAtW!=N21s47CrP9vT?B4t0eleAv&b(NTs+JQTPn=3o(p$+A*i3Ro@&-dzd$`@#2}bRH}4*cd4{bmXfMW-Y6E2QHJ9-DEJ;J7)~=^tO!_tWFIaK`qX>(E|XEzpqmKChr5
zUWAWZUF3zPYI83z4))W>O(~wyhwZgjan^qyd{0_dH+gD$QsmM5tJA%OykxFucsW<`
z%+Rf8=PH+Ttc!}7r7Uu0x0iPJfk#Hf658K~&x>cxpU`gibRX?|&;6Koz2U*pWjK5h
z(^<1E(NohoCB36)OZ&30I*Vz>ImgyHO_f~sv^n+>^GCOgSYo^^=P6a)=~>CXx&k%7
zrP-Q@sAKhMrDrb7hhe=f)6O~W=p4(Lu}Y@an_FkhZ)Dq@U93DGxxM+Us@t0lZ@8O}
zv#-|Icfykra*7z0y*+n3a*dC
zq8??b(fxAUaWaHcu@+Z1vqzKFSjN^WYxFC*%Dd@(zv9uqLT{cXCE1yC+4gZ=zz>DI
zk(!khUvk&#^gbJZtHGLL3-48Ms&N7DcU)JwzXJ%DNcm=!eakuQoC678f;enJAE7Ia
zI74C*#byhp&13YdeN}^aYuBY=!^D#pg+5vBAmZSblj6)Y@z|3hKvq6EZ`#rVqpi_B3(chmkf&`lUUoDL577YpvD
z*5$+#x%-a3r}*pLa{R_CEQ#HGEJ|@Y;x}9|AR<^vgPe}&4TLgPtjkzt7h;*2slIYp
zG$}UDw$DSQZn+^@_twQb=C8mCM=&gqak
z8K-dx3ED0_yi+MzX00W(h(?A^?M-CSK!#)`c1F26lqiqWJmCW;u3d|^hV+q5o(cUg
z$>fm>Q4`p{s(5&ws*~t#XkYy141F9}oU4rw@CSiX+c7m5y0o$eUqW(Xr5eEux+>L7
zco4PjaY-sQAz?J|XtUXY`{Jx#v+~c_Cnc6z8WCsm$LCpVv~nF9&mDQ1znrk
zb|A6|S2!7`A+2b9cqv!MTiKr>S*J`f!!HDoi&m0$TWphS#FPVV&&H82i>6Ad&AEP9
zeWRLO`O52w-Pd_*x0(E3vYGX%RoMXql_pbrMtM4vNCb74(L8DAOeR&7Ne=ddb`Bj>3H8
zwDs?ZwU(suu+}Jvp#NN?*UwHHce#hkcfmu-BhFdVyMF5n^0QOgf7Th~=BD)64(i_LLF1krG{@WLO_1}ue^<4K!o$`mMPxLhTzjVqUq~uTaH1}sZC7;r-
z(Q_(zjnlzgP@42Tr}bRv;vfnYgM8pb*I
z1fiPqKEj!`XL)*)YYMQ+F*aa(VHr#)0N5djz-E+*hIrT?l*<#j+L%E$;ZL87+nkZ|
z2OGAFXILg;%PwR6X^BaI885p*QN=i&z&G7p_>gSPPV`d^gG@0g78
z4ii730Tv=HZrRxP-;-|MoPWk^U)(y1{Cdtk9J{<@x$fCh^Xe&l45XDSWnJw^oHdU`
zl%#Ohj!1)uH+XY=x&I!nyt@mdTBXIlR_0sE?%`g(SSvD9^@b+VK6uVhyTHVmmAx}M
ziZVBG{e3U2yAiqdyQ9;CYScl}f`I<-!3QZ|uuUTkr{Z$T~B&#~GCSKvRjBW+vJ
zinbPaq0y|YS=X}Q9m5{y)U8O+SQhGV-YAX?0bnHWU6X95WiU8f|Q&
z(bBApPqRO4G6ZJ)bzaz-K!0+JEB0C+wzUXeLwNV!E%qqI&|0?+))^L_yti(69pxPh
z*XdfPW+%hLM#F#Os^;Iu#7t|V^SYL=ORk)*ya(TEgaaXuNv-f|)?9fhBew$c4pwaw
z?gx@kxrBpy>=;((S9q%PaD`%E>T)Y~DY5tK_z7+H3(VMaP?Z-CFID50HyC@hxWJF@}!#ayK@
zgD|eM!*IpTiLQhTwY&wnnr={I4O+qeUGev4?1>Y_N&<=bN>E#4xUk9
z3_FtOSzDLrT5eD#Cwj&HPgD>Sw8!=-x>ML|J{ylY%Ff
z>1&pw+}DQg^Yss5p4)Tw`SLCTO?0d0e#^?iyp2I;YcA;*M
zDuZ>pw%Q|01zPJ}o|CIQ_&BZjKB>q@UwYC__|4zFg%z!b>O(tap7~L7zz(D(BuRbR
zgxe$mzUvKY50u>dL(+T}rr(++G9q
zDDtjK-**NnWq-46I_VbJP2yM->H|&_J33#rX({R+hTzDgx)QtM;A_ZhxKFL=xM5)%
zU0?f@oRZMUs)qlED+vGR))aLIic@ZNA#yJI1h|A@1RwY)4One
zZP^$$+IC@Rk?o|qP8EE#2L+VeOpIFJAR6T3JF!EOzVi;Im>!?mcUS!_vU(j41QsOY
zcNjvR^mev=Yn=?_51}||hluRXiU*24)bk1TY@E~;NqNAWMryu+$r_2q`l_yT*?1E@
zRT;tq7#RiTK4UqnO}#Y^FLMvC^LYw(SJQeEeU-je2^H4;XgFUw-Av}aJ9HV7YqxZ9&>3B(Oa
z*HOR3k)3eA)GHbN9j6G3PL?FFyqLyWBl~#k;N+OE%Kawh{1c_^m1+@TowwFVPKhw<
zG*SSU3XFQaicxo-d*X?j{lK*H7U9{nuLA8x&zr6U9}w^BSEl)hXK(tCWYw1W*qi%R
z|Aw%c(d4lkMwr5?}T7TVc}djcR%+&`!)Ah!(R=CdDO9Kv(&)7!SOgqB<9|stwUu-
zg9U#BSGXhM5uC}KcNiJ!ocUww`RU$l%@>B;bzaIs)m`bt!Sj{{|T0_Bs44wN|&P4qam
z4AD>Cqm`#JPg;i4W7INQx>mnR7lg`mCS<5(eghdKOSDSUb)`T(8m-l%(ONw!{a}a=
z56DUKVBIfchJ7Ah(fV6i)YY*J76N0=vJ2~-K1GcL#fu+!=~5Q_NkH5%KQu%Sj`-taNej@RH;&Jed&)vlL5HG6y1H^AvUABmn
zpH2K5OuCn`5yU@4{7xnT1O}%RjLi@5X`IGCK|I=X7LN2Ozkqm)+Mah2A65|LClJ3R
zl#g2mJ|M(P#IGctiPB`Issii<;&FX|&D86=h;KxPV=NYb>_y@?@)90a9Pt~8-^HYf
z3`Su1yh8j+0FW8`3GrKrckmJltNd=_@jM~Cf%4xbejd&}(D#V{58{t732%woW!j0~
a&7?aS!zCD7(6pfGQ0k#nd@aD&q5lCrXTt&j

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_autoboot_v2.26.bin b/bsp/bouffalo_lab/bl61x/board/builtin_imgs/mfg_bl616_gu_af8b0946f_autoboot_v2.26.bin
new file mode 100755
index 0000000000000000000000000000000000000000..c8b8957ec3d9d482a6e91e963f4241ab0d2885ba
GIT binary patch
literal 411008
zcmeEv3s@9Kws7@K_cS9Q;D7_!F+oN^Sz{DL^6)Xh%rxL5#PykAV(b`AcC*G!jB)?4
z0cRQ<5z!0;h6AdCUt_v6tQIP+f?ioPh-p%fRzyG`6
z{TyYwy1M$*sq?C;Q&neTjI$CcLWnWe$oUY8dO5#WzKz(f(!GRo1kOIIkcAU>%AIKwIFYTN+Q~9Rnyy%O)
zr*hKk>cd|{9G#y+S3)x?{|
ze1GRPfcysU7yC-j7dy)@c9vi4EWg-U{&nZ`*PZt%&T=Wz{WCfhIRx+yLH(nEK8K)w
z={lUGi1%ve)nB?oz2bAISGo>&Ue(U4zjR&dOU~o_OZ}Wzsoe7u{X{s=Lp=!pd7V_x
z^E#=X=b@cq{$iEbzUQGn>0T;d5j>GRt{|i$IMR8YBwYigc2orVitVWg^mAVQozDYE
zw)ox?;x!Q3i*ybIJfy2cmq5TnypNHt?(iJj=?-{GSE-%ufTwuxq=!4uAMcj~JzJrk
zx%
z&V1mrnE$$zKbC$tAN7d_+3eG&mVZ^B3VZL>CkFJ%jqHA+YvI2Gn{w&u1k~00!`@>z
ze=EWU4f5BqHX-(oueE69oYYzCcfnMykGhL4A>Od
zbov_ok8FBB-jYp68T1{-R6G>&6WIS1y@AAvpY#_yd&>xs!Jl_O>_$64w`4gIK{V!lUX)>6XWpbhbnvj0j
z3~4t0u&(#P=K%#CP~ZUt9#G%`1s+h~0R{e>D3F`lU13e7-c>IpM8yb?sg_2PH@xSL
zSHt`X?uWkNy=uIAdryUmD*yToZ)#!`LjqMy_2PpDk8*V|mN9haG5|xUzN0pFSEv;4
z-{o&t6H^dFw1snt53`wR{Gs};dMSft|6moUBkFkoPm!j&Z@IbfjA4f5=JWteW)A<>
zewj9q0XU7X?Z2yLs7e(R+>r}ctFW`3U%j97KW$kYIHYBh_hVEc44{7QhbM*P!Qa16
zgP%+12j%`pQXpo=Y-3{d?CAfI$UQ*n0R{b48cUz*?f!7Vkm~=w=~gRTL4emWQZhtu0qKkz?Cv_24c+#CDzsIUO6|H
z)MY8yb6IN;JFny{6X!>Y;2tp7C9Au#$M78*J_pxhQZYP2bHArx
z4@$}n9rI$UZP7;S>fyxGc(wOM<2gHU*fEL(RfSY2YHV*ZD6OqgRl!7C*q&l#&8>J<
z(dITE!^$Xap*f{Q7o>krk9gWvGlBA*Y>Iniu-n>{XrG{}s5fN<;izcZThLcW@xD1E
z*>`C-)({1y5w_KjVuCHF9q$82CnDr^n>yYznftZOf^w
z$zOvW!h6={bP{iO*%fBlOk475)Si`ndB<%N>I9CbIuwYpHQm9Sjg4Y@dXxPsm{+o9
zW(6r!s~yLl$(oyWwla^y9M^rGJ;PUJeO7r3(&QqhZ&jA)M2W?g6tfPrDJ-6_)B*ZB6f-mb}rbE+)sb%0Uv4
z+V6lgAS8r8*B-^TiZv~=^TbUSrI10%C`Eg3^6&(octSzyBe
z#(zFHlH>nS43maPPMpsgOYS=4S%u5nrMU8qIO#adAYRjaB!pWzw;HT%73e`^5yTU0z`ZHjgmep6Sph2q_Z_>HBNwR{dkK&IeczS9BUsZC&W#JhC(
zM()27fhDP0YkIoJy4VsOV?kbTXHS7_fK8g{0X8Y2Oi>eN0lSna=-Z-rCP#+voR0;p
zL4K37tm;~jHr^*6!({X&n%GlU;CYI*=4Nk4mdQAZbX_qSUn1xJ
z4!N6phGX7Da=ju-v9`BoI7(iP;=)E7OFT}&6FuoV%)BM#mq_`tQ(3#1nV
zS})~Nr?Nn20RqCK3Gxg1^o`5q8_n-n*HKjx39f@(DRC^8IMSAw_+dlkekdG9yY1ye!xqd4E=<^{TAs
zV+-_o$Nb~YLVp6M8mB*V4P+`s#dY@L$ZQl@bWP5^L>4we?k1G9uIeaulc@iY;$eiI2xv}Ak}~&*@RpPxF6D!U`s)p7mqcrtB0`dLGyqA2wQP*ia*MGch;^xD16ZvJuFKQ+4{
zRl&w97Y?GUp#|w0-R#2W64AL8?be;KM&=uwgZX#vde@a>5zLY&^1B&_m
zOv?KFBgzK%QFePDW%K(en{QvU(hAZNbTZ^bLc^?j#py8f$Chx*0W*$QRq36*Pu4W`
z!uTSm9mc*bt?!yC!)ud+gcj2J3;b^I77TbDKimW|bTFd}Mnh-3@*9H$YNYsl=q@2a
z$e*Y!+(Sar4hxhaU~)-f(46*d7MxpOiBwmoN&mbr-`C|lBFXY
z*`L@rFM_vV1{tU>s(f9GeX`ZlWN{HbTjuhNi{OYT>|F6{>#JZD(H#&b2j+`
z{=QwLrFF$!7wstn$~D#;MH4#NH{sAL8^&2EL#jbhA98qBO^GG`$-QREi1W6baQu!B
zw=tx!Jabl>B{Ko)X?-C?z~}klE|?|I9)ya$4D>E$&u}gIkSMFsGDlM*OVCDPpW##9
z^Xb}@H7kQoBE@GPop)GqI^@K&hvd^45@uF0`^W*yxb-FLpS0{?C^B=};j~$4zac?F
z{uIC3z2^SbSy$bGT%d$PZrDd&i$c00RhJ~3NQjvpBD^;TsjE`l?w$Ak382lvUzQl)
zeSj7utc+~4J+U(A{H)WnPtH5>Y{T>Qif=-`N;qrMyKwk;eR#%!j3?LsMZ_X9sy=PD
zh{eHmT@ik@VV3$qR1W+DV&NBcBXP-`6LU%y20i=Uv$E%IOivJE7LEiwPN(e>zDa*J
zoiZZM-aaJ;fB`T;QXhO6i0)uYI9d)s+awVs@_1HZpL4&PqzE%gsbeQb5e
zSF=ukYz{N08cHn7iJwvNO~TpPCns4#vVoeMiPOuM6Rm`UX%Mpzseo-qIaAb|
zjFEDaVW;eM;Igb{=QI;{QpOl==py_&NC~$@pPU&HSx8WV5XXeGvrdOuN-X2dejsJb
z3G(NF8StAD1$Bp{)eA6#TMTkIF(KQ;nE~UF!-%iIX%%h6N_z*iwDzV5@d-kF6yQup
zQk4FQLKUM^AfAtHZE7EgCt`^b>1RZ$Ky9aGRiNFIfEH9gEm~TS-7y*4WhR4JHXdYe
z?i3UEXJ|u7BDSH33!0NGj`30Mq&AECZ1j`MKp%uFYo_frD{BQkYD`Rgh;Tw2w?i)v
zbjb#~1PK9Ar)(xe4y3nFG3h5V;avG;ld(!BaHY9t2=snGVreFxPYH1sjIWbaus%~F
z1*1xFoS;4MjD#@=Bj>VZ;l};nnYb#Mdv3F$RDBi3$Wv>AgbCB)+XmLRa0-lU`f5KF
z0lg_x!i|K!0qWG3W?v>f8?1l!C7;_6*7l6j`JDtk3yoWIZ>H*l?L%2B+v-)C+f1yE
z&fd1Hh}#Jm#vzcd%#=1I8qi+ra`~Zz^OcnE)N;5Wdvb`qK1J`4V=s
zaR+;x$m;j9+fC=PrXF1mn&NediWlNN6M}^32woN`N6nOE5-2|hIWE1s7kd7wN4snw
z8;`VH+;+#rWz%xbOfyRK5|yTN^2XlKJA%Gkv>0e5`Y~;b*lV89lxpxZLXD(Bg%(@F
zRJEFQVmgYl`gIZJ*mvyqR3EM`YX^IYOg$>AM;woxcH!9e1n(6|{S?RV*gC-OxLv}|
z-Ubo}*nKz((0vhhgn5{)t$(C0!)sH
zl&QLkM5M3R@oPDzboE3kr^O0=c4pRImhWnoS?AJJh@gxrUp6(HYHECYL$^;M>ZGfe
zmHLB{=|MA4FHMe76raM$OIMGgQd>&XztjPgTOhx4+ewJ<#FXvJUbB~`FO`P~$s0=N
z{#mvsRfsS-s>oh;rVYJcXeB~Ugn?E1*bII@gW_~TLkkIf6KoJjWHwnYT1_0aXM!c7
zh}I3beHcgZV7qNhJbdruhXjij)YFI-G(>nY7-v?=tuCAq&wH&=$ce5;P24E3atOKK
z&Pi}rln8pT_JxvvDfyNJM{F(3!!vB0_s+(_@DdtU1_MMIMjJF*R4r(iR@nxcHIbIb
z`_f~Hj}a~G)T*9e3fy-z*w>?4w~-WD*QtlWg8p$Jwm-!;p&=6BzXb60gW$gj@aGJG
zzvlk%cMgPaf_8v^RJNzmMgNao{le+v+7O}T;ux;+f@RR#&OB9)Q
zK2u3}mVuT{IvIXC)sSN=QsC1IcGaZe;JtETjis-{Xe6tYiicTge7^mFa|E?$|A>`E
zM|U0mstm^@;Te)OJ$$IX=0sIm{ppJ5zgcqr<*!~n``go#U`+TI%kgpNz6bkEnT*+#
zDS;NbmC0Fe50UYvA!IYx;VbqONKcNxk}H$L+}*l5gb0nydJ}h9KJy1YbI6e287o-m
z6YGJN;BUq^Y+r&FxE&`}-*k$auJUO0vQ73N%uH*B`(pm(r<9c8rtW3^X}vN2KzvBT
z`w5EaH=bLPbRsEcQOTmewEelhzz9gZ@{B
zWk=Y3IL6Sp?eZ--Hwtor+RoAw?2Z2J?N*zbY`1;Kes1HBiDUb2BL^;XfuyUo@!qVWUIZlz(Q-HWt(c|r6hcZg!)O5>UV{^8mVj_?_MZUZx=
zIYrmZGXji)q`Spe_@M$(I`2}Ncvc{u&bz|P(p*5f%ch{vUz!TD&jy_9{ti5k+P%9(
z_-j@wPD}H#9k_Cl-qCAi6J>l`^DvMP%NwuL<5djk=EbM~KE}{;@z@WxPVfxQKYL93
zF-vUC;921E%T&u?bqmuD^niBXv8ElcqYw1OQ4*FHPg~ipUL46h!SOG3dZ?S>q$|5D
z%(X_M_JwH#Y85u7
zwKq!P4QFT-W!JNkhu3Buhcc6nzLxc-+jzGbZfG&%+o`j9`mAoN|)^?CQl3#xo))`svv*7Pnt?q0&
z>+p|Wvn8+6KN?pb^D4!aHjrz7@h!@bcO)=FN%vwubV=~vFDGBVyvLHJAsk;>%#
zH7`2vjDO5$j=Y##j#O?cV1%>YkP7S_R0@W&G6I}vR@AJD3Q4mvRWP#uJW85_IoARK
zzq1@=knkCdpELtf`-1e-FU=lfEE3|p72n7X=WcRCeS0=ZKiUl~7foqNn=H2swQw=N
zgtM_k)0L%4FAq+=25DLYZPOM~AvuNMtE2gxGsMOQlI!Rjbd&CMq|FX@9&kt7SRMEl
zXLw^77;Vb6g>4}%r0h+Q=8G-u>NgP^{d)pOaYbpA(F!F%Gf3g@_yk-R#E~nGsco=k
z@uIDo(|Wg)8E!rEg9NQtyA1lKzn$Pf+bPs`!LZzI>S6V27#%&<`F_hquO1Whl!B2m
z9<<=>cH4i1)hz00xwzuTaKlpYCgSW7XHv2XsjU~SVHFZS=8c}!MS^n7UbE+=_c#&a
zsLuC*GU6I(JIVD%iluyGm=e5u>DWgn<*uTLRS3?Y3|-?UOkFbyOMOF
zXI*i=75Mc>Q&I=b)plT9yee7E{!uDs0@$E;+fo7R-w-vxRWUnZ95U_evCg|{b4%;f
z7d(w)NgP=;A;>Hc@V7J-aXS?4Fa{goOKMgx
zMc7U6!g%Hbe1hY-eZbk4))$IP3|PNZqB!>^z?(%|569^8DPba9ZnBPM~M;)
z(p$`LVD8o%Rs;P1>m{2q$P_XJ*4HU6bz?tdW(83Ca#&4UV7OsX8^Squ7|TVZr|C-5
z&*?&P4R*$`5@aXgkjjEBP>L-GIjpD;I$BEaN988an_A5b*pFUJ>PaQ1}QG)FP&TMp*U|s@v
z$HQtSj1D&#xZhkP5WCOjiRj47_;caA0lZ|B=SpCsWEyLBkWt+6a+6bkG
zF_%7r8?J?AvZflj`
zohdZf7p^QinRa^DiE(D8I+atavG+_j?K7wppVFmiHktdOD>^=4w_;MR2d7f#n9aLW
zfk$2^T|PxfABRX2g(^iEGlPs|Kyq#9O~jG>ieo;;++ftxokejl27hE~ck57S;4cktl
z{gtdQKEu8%%)Irg^-Vqbyh>%DW$ux4eXmBP>aDA3YBQ{{Si#?>ddrt&?DwMquZC?$
z0M5k~U;6AuSp^<8yn7h5@Z!^7%yq86NYJgT%_P;q81_wBWEb=^?N5k)#(5{6uiv|V
zoVg^!dTtf;RXQe@A<)LAxswF+DLmUS)uQ-j_Q@qjUq1Zmp#$b8Gr$AYy3GP(*e$nZ
zhtr--`wh%bLF#ixl%xEt01F`b8YQ2Gdkhqh)#~0`)z4w6m{Y2#v$CD#&uD5EQJ6?)#d$+UNv_PQ5pP5bR=Ngdd!O7
zkL|&4um2beEx=Z_WQg}$VP{BZF*UVnkxf=rWB@sW7>uy1=!FSRIVzUq=%LU0*sdzk%^pT|}D=Bx$qbC-rO-f($FA8pudH=*Ez)Rx7M0H(p9_=il4_{i9BX
z5DXDMwnk0YT@{@ut3KH1*LC;${_9^_+3LGUO%*#{#=qRDkVXuO8tZBU_d5Y`a|q
zD-10cU)VBmtbtw&TiR#WRfdjUii4dw;k+M=mf&t}N`|8;WlH9DPW84QVN!Xy8;Q)6
z_73%QGVCS$xU{_hvDQY&zH196I``X95IPfry+Ypq>C02f$Nwa6jC?#~iscr%-hBn~
zCPn8+iD^W0C*K0W$Jah^e*Fm^1cpcE(der<=i!~t2GfnelULG^U4(>A-QA_7~G{VjAKs<3~(G%wGJ6
zWgu>Ee|o^X5Z@O+V)>K-`6>PR&qFL^{2&~RhwMsYOkn&Rf_#h%+@F@{Ai$!7zY|Z{^Kz%m6y^|`7$wI!c9y&ad;iyb>bkUrSf7LVnO5QH~22Z
zgYHlFm%+Hs`1w;v_Y#clEPg^UJxNT8`GHcs1oHy}#QZss#u&}`*)66em{M9QFQ%P%
zO6mSG7=IZ*-S95PVD3*#WfFnc7>gM{Qd)wEX^i!ZpAW^f1ZTz=%$MLuX$g*$mf%Qf
z2@a-RJS~KDMW6(;T}(?brL+VS(=8A~8b6}U=p;JCg+aa(Pe~4?@+hl^oaH5cN$*NL
zl5oH@#^uHjmciKE{b>n*DPMY5N=xsGX(!zoNlrO;)
z(-3ppRmR2=^Nu#*Gr&%X?_x34dA!TdgDknR1aad(|IEfQ>+
zGahysAqx2Gi@O^*ivfE#z)n8%ulA4qHm$!e8`O{g(>T&Ur{4jXg!+Hz%lhfrkLMtI
z{>ym&TWyzOQTP46z~Hvu7v`{g~q1D4m*X}l)ULZZ^54RcUNVB&u_Zu
zjkD+Bu3va=D(1jD4f}|}U!}Yny>w9~=4$sAi$3ZYrW*ES!R{Gf5~!$$Rk)OKHA!*e
zZbLX>poum)Sn-TO(jnhy%?!C?IIfyE;x1{EBZPba>&kM+B+To^J&l^9zR?S2*uW#*
z1GUK=MiK)hkFN%A5tN@tzJM~Tz?Y17FOw4S?YH3V=9VBaore4Sy3b`L9n~bNIvu@O
ze=e-UYZ{W^K3%*ohWn%j?`Z!y;D<^<|23Y3I6&?K1XcP?@veqMDQ@-t067byVSitm
z3}Kw~Px3UZg#FY0=O^o6H*MDBGEE%#ymgvGEe)Tn)5N(>f@ltT!mK1KT@$A?h`U|!
zc^clqZdXXR2>nkG0!J`6%Z$0##S+I%kX{z8mY!)AK<#Hs43=sY(;$QQQ_(vi?J=^Y
ziyVCYGbh(RJM!6dn9F|q8FDWTxo2GE;$Dojw(zF7et|qQJ9+l{xSDtF!?SmQXOsUa
z&n5%U-u{2$*}1HDj!wRZUy~c&xrblxG)$fYvr~{kNv0gI@(Vj(VRvg6aOhmt_Y~wDwEZlGdwFBGuXScgs!m(f@cU=@q7OnaQ)xq$tn?daH6hCK4eBeraYeugMCH3
zyn`?y(PQ_TYsc1Z!1Y&46=is36!?Zm;f^RIevJT
zn{$84YG1OovZeKrFXV
zML5e8xys}}rD8s%fj=hzJ`MXv4Ao&E3vgn9Ribv`e#*gkQTna69V|sY!u^ebrVz&h
z+&5HA;FLm0=K^W%4tJTM=j+8V@WmNchEayiPI^JbRhum!->;96#i;
z47@+^jq6w1uuktBj=!8vs~za62~Eu4(#11Heq5vX<+~tl@=JJPth-kHhITY_oNU@9tZ6$}XjZW!If~mSxqp%w=tTr&$)k`71aR@SJ!i08$0d
zsXC*`h;rCZOrMgqZ2|3vT+P>mX@|U3b%v5IJ8H`%ClvQcKN{@ezYIq$!U+X9s5j_W
zo`vUCSXi?SW!F*qC?yq$yoM7->%hn8ZKYFKSc@(Dw%8PES;x@m8_d7fsLsBt9HfU<
zHicCh8WrtuChh|GXyJ^Nv=Y27iq(lHXPyOXZDY%!Crr+)U}k1&i*~J3!LGfQvfk~k
z(}^~~1kOOLbB|p58u-GwRE{xP-|F<@n+^~a?3sX_UBj=Cs~b~m1Qu-%!`6v=($PNc
zHKT@L|ADK>@(Q>O<7hB{IOaunyLnQSZ=l$vahCOcTUjAmjxGfagz
z4mb%JItx}k*s|+D5B^HAn}lKWxD2jXkCKaLDJ5+!(V?bAQ!m=2d%W8}4ROYu_ZhbI
z$*_72)Rj(MF$TkcXY3+4pCsx$LW%T_rj(-g7Ca|pYAR7G_p$U=Bk`qgG88&v2ggNrM4(wv_ScwW;U_TXts(=n)YvsiXKNxY$pHEpb+@n@&
z;B16LtZ8$zOuo|?>>jyuEcA>QoOJQqnjyhnRb+_lfRhkFtx)zC8MfR}mKJ$1=PLh|
zv-~f5GRp0KhMXzYQtuYZYOrkTfU+-~ahBB_hmw0D>s%!t8C=qS(pmD6*KB?U21+{b
z{XGp(cIoCyKf@R&C0Ku?!)Cj*cV*#z>1sF_C1I=vnorEU2Dn42dGhB#U4Bb5tXsWs
z+zAu%(?|QDoMkr4V82G|yS58>LS)++A`gXjMx~GPbTrbPcP$)cXdK?z9bjm~(wmxP
zFrsdK;p|d-lwT+dJi3@{b8%~~Evo4=2J%u~fn8PGs-1NOfZdQU-H)|=>uRGf;6L}7
zgA(2o4n|=Q@+-h8&~n7>In0&h4rHMgp@2mBfJFI#hRHK*t2LXi0et(t(j>yK@31**
z4F(#l%B+Nz7c@i93S6%1f5I*tc@WzCWlx_BgTy24irE-^Z}T;LqgSjO^SVq;r2q-e
z0b{=X!=}ELcDc9|3-683KO#Oaa>9bV+_A}}E~;F2N>utBXz7dj&Dc&)INQFW^@U25
zE~(u+$70U6rPzPs2nV>Rqj1!`82UEQ2+=1hlY_UNPz?Ir(Xl`nnGCMzF}?Sro7TOA
z5FHjHqji{up<`cq(|~k}m`;T9Z!HNOkS~?TpV5=*5La5z?|jca!o&}Hfc^|HKISMf
zT?J|3T7Nn}zds#ik0C1^)}aV1GKze_u>;JK;AB(j7xGP8Gu$
zf7qpR(LJY_7M4xT!FT}J+v2Et2b`4^yKdNGU>r1zO+8C+8e%*4Gi<~PBc
zXqSHsCF7OL&Skx^i5(B=ccRjDFpq}2ci=ql#iZCMx0H(}BTJ5(x?smiC-j&UCoEGb
z2$M1Vd%9G(N!%N55^d^E!my2M$K5D(%Ee5hmOVpUJMr8}AbA7Mx?9tmBW-y3e6xOwvS>APot3?k#-
z|H@QE9g**l5e9ZdEg`u#x+_dYF}JmaLFA3#z=<|lN{V&ujoye=bIFgv-V;^xI;iNH
zab;GSH@PcQnSMw3Uo54iw~8X=JED*DJa5v%66m;CqAff@X^Sc-ZQ<`oZaBhSd#!Zi
z??{CG52V!V@02$1uaq|EM@l`RyFxya`T_PIdXB7X@ecH|?3VJ%zkfp;I8pV+kJE<8
zu@39nqVpfTX98^3TBj6lX2z9$6vGG1B~s~2O)cJw-2-<27!)}14XyXYAGKusDLdYE
z*j=qmR$(jEKSGV##%uDCa~n(6aqT$%CK%(O+rpWpTTq!(&l04}g^kihZifB*ma
zN0D4GY}U21i`MVLK@(<=SGOT8qrZ_wuhsoKEjc}Vy9_B&6oYMoS=ayP7X7RBp$uDZ
z{H|9ePw^inFa2%_S?Q+@oD2R4;kI}ANJzuZdY}=XE)$&4P4fg>MVS^^i34Y*#QQ$xQ2v#BQE
z*oOJ&O>u}PojTwwcF%m?qn$3$C1jUX@~@1Nt2+Q*aMNcSbeox$z`|gu#|gch7t6nK
znWR+S>ycWbm&ykp*r2djt47UHMoN{709h=P3{O&&p?4
z&8v8}3}T;HQ#mSYw^7S+Fu-YQAcXviJBQ3Ql$C
z<%pho%6NJR
z(FU#u&za;mD~S(EcrQUV9p`!4A+&5E>@}25;JQu);Z8$|SLUPY+tB_Y>yPIG$E+4h
zQ7+tD*AF>?98@Xe4>Qv((+hMx-{L;S%}205lNT$A3I5)J{c`VAnu-sTG7j4WZSlgr
zfIVt$U>AXR)CFbuR{k+8-5r~MM0|4>zS*OGr?NXna8R%x^CV+A!mnK>Z_HfXh45vY
zs6w{|E#BS>VNaO%rwih3xL5Cz9q$_E=RjndH7l3Exh841q;$#^&pN$aAxTBL!yK#b
z2JAh?RtU7Y^7G45KAV#l>mRFhxayFkui3gO)+09eCbT;3W&4Io@5;OwhRv(Mvb-NV
zOoFuGV9$JQU^fALLp=z8xqXO4ui7kZTR|+pp7q8Q6@Q*9z=5l3_OW9l*u?
zkD0k}wPySp&U#Y2v8=P?#dZ&?hn~C)t@HjrnmH&9`IRl+iNBAVBQG98t_Y>-y~N#b
zC!D%>_xmHQExb*jEfljuL)A!
ze>9tl-3h~$B%Ys-C%7_lJL&ao26sp2)R#Zsh%bdHjC(+5jJtY|Zb^b{A)fce^Ih-F
zcv3KcL`e{jq~u=1)?~bkRC&!-;H0?6AJ20Iv6y%1Ak+?JRPOG7kjfr;XQvH@PCm10
zB-+LAMJk{N41GtaZDE$&%K+6p>i4Olq@neYq)g(~vhC6y%>rFD$Q|rD4X%}`e}FoM
z9A3TOp#~nR6j!$S$4J~v+qNM_;20LYv`D|YEbXYPw3Ug6yS;Qlg?|N{BzOVgq&f<8
z-LXOorY%SEbf(Z+*@F4}o1NqhFw*zx6>3$1?)?15S2}KK3rA6}*z$DQfTbkS7kW`v
zm)h}(f2_dq%FY2;zWUleyA$8v%r-maBb$QVme0^F-s9&s7OcPP)W7U`C=YYgU{PV8
zdN#`b_+Lr3O2}#PetotxoeLWBOn-iBVs3MHg|=w^GNg@|{y6=m3;R)L<{g$`AAZjS
zay3wYq?3X#S8P6px{-Socwo8uq8zA!6p=U}*^4TRq}K(yre@SCQ*r3Ju4B2NZPpDQ
z8%)I>M3S_Ota670=aog0CE1fENy9G}NhN-r$t0MHkBYVf?4NfcoC?yDCD6`K6F~Aq
zmE^m@k`Gn|TCPW&7R)(6AI_G*C~rE2wO+V`ZG}0=Jk;BT*Lvoo#K1grtyH^mt$dV{
z_*DtFE%^Y#dB#dvFn70>x{glGpI2rLyX}ydqFJfh8p=Zs`G8sg(p_dJE8an
z&y3@V?Aa&rth}^G^?bB-y+F>#o-gOu&R3cK=zuirxJ@`;?$oI`&l$OYL#qGjb>&Pe
zoj8Qgysa?pagbRSK1JzfW#hqvJc>#J3tTJH9D+8=la7K1nbuT6n$eD>NfP9`6MjP|
zqg7N9o=sDlLX>ioLqYfta_Ll<_X@1L<7P^uXYSn$Tc{pR9mtp=a85zSuYHO+AC1^G
z=H9+#Do!Bh%cZ&-vz52xW86u!O{;+2|4w*~>vM0X;;9Aa`;G5C)ziPf_C4_|zqGq{
zwjiBqN1g&l3cJDHT4ec^TE&MVpDoQU>m3fUydopQjYWn%w)2Mb
z&~TQ&b;WInNHFPs=Vwt)lIJ$rVBai2OP<>Ws{=5K0!>sYYv-ec;#z^Ceioc{mu%$a
z(7`s6ccX_|m3jg-dA~lKy1rme?iG-bG(|{;x*6@f(X5Jw!|<9$&URjgx%
zCN^7#d*AtWX>QUxH3V7Xh3yp}I;|o2BwAP6Im_+$qZuNqD&Mr8I1Z{bv
zK!+Bw@wc5fu}wJ;d1X0Cbn|dSD=({&9fC3Q+c5^e@^C$M)XEaY)cW6XvyJ>v=;53r
zuEEzEac*aohRJS0>+rNiZZJrau(V~z&<|;KM{h6i_nd46K9!y{{Y`q}1Md!e0>1(J5I*rS
zUJoDqq)81=9G=GVC--Jcqx~Ub&)iQFSd&~t)CoK12ti7
z*+&x#dj-VPF3#s3`3`}@rx0Cm82Z|Rs_==n7)HRL87lhnMSmTvC>HPB>Hi!==X};T
zme09Kl4AMHGqjt|LuVBXa+m?kmUvUmwva!Q9?p`5V@#>m^b6}*cVnlnRMAP4S6uvV
zh}q75k-H$~Yz6PtNs_n{ou*7$|MKM;vv1x`;u<%fx&4}LLG0OzI&u66^Gs1!^$MI@
z;^+~rqQp7NY3CdTv=KE@8oTfc+S_Fr%k=%0@#T~Kma%JqWlV{2Ssnw7ICKz+q>5oU
z^keeb%|ttthMB3wf$+Oy54IHOwu9c^uU@1eoE54=>o>-6Pyc_bK$lr5L9iT?Berm^
z$u*)#ZAQz5a}7BEoiW%dI&~|kvwf9)@SFSZ;F||+l8tz|Ww3RgV8?OLse_0wVrMEY
z{+rN0BZ3@xDBC7IN&kU=s8iGt?QXVgza1^hR(t=vwQVg}n0nmpItFB?`qOLV)WxH}ggx#N-%
zX+N2mMRp@g;ZbhDc@Lp3bM8<^)O<$3C5>y#t4cxE7VZGN?|;08m%DNv8I|UOlJM2
zSiz|EQqV9PKIW=_lXE=#PK?xJO%nPsaJ5&yn<2@+N;Njp%ey5BGai+HtRSXw43TRg
z;^ew|ioXIe9ts&aaXQl$v2nSs@%KY}v5a?2slq?{gZHz`wSm=CVtJ}D-sa>=aOY8&
zSBf@W_@K|GA7TutN2J`P6&T%9!K_UQuIulst8zhJVCNC`)eGjHoCoI(SDvALXYz-j
zrMiZBRt1r5-soF5C(daba@=7YBmcb1|_@s54=|~oV&ucb3D23
zKQrkR&#|zR3A|ctr%qD`nUeRvI>ky}OcZk>3R9kfw8$*vMdKNtb+^;em?
zxH*!1sMzKr9R2vl;^^nFa0>i`XeVUx?l~XQVvH{0&AX`N(&XZ8-p)~zwFaUmZS<`y
zca8)dMXAy}7x0D?oNwgC7J%%dFUuu+#f6}s;?wk%F8vrh-@`Emo<5XfoAt*!ljd)~
zt&#MRd*2Mu!S_iZR!nZELIshtK?*_)wUlv}5Vir%%5{XTS9#7Lsqv52ZJwU10h~7c
zE$NBrDkYH})aO0~_v>F>fPS(}k~)*We1~Mzb*GquJ;7_xGXCTo{GOP^FaIO>rrZ~P
zNEoJZM9y9J#1EnOm`UXG>nKx59SO_+ZQ5x#J=c;rAsFBAT_`BSvQ?flWsSa1-dQr|
zMxraG*n8q^3{N_i%v>TYnKAOk73B56{@I!<_L?+bD-q8_O0;r3p9kKx?ATigVD}EM
zi(Q+dtafpwUu!R~$6gz?Rt?eszK!Rkd5oJ*qkAVBxKOUqDGie>CWnI&d)&-o;-<4!
zcl1u4c|B`#od$Xp?M55D@EY{N$28)2+aJas&b~8RvR(x`393Ir6?w}mltiQZ&!=&g
z4>iDUfW8_m%`%NnyOE^_LiBY(blO9goj_~guTvRs_A-XaPq$@F1{|b!yS_bcdr}C8
zlgjUAVP9FG3peik_H(xFObgNV%|pni
zVVXHY-z;nLOo5$Tx6eL#=5gTLW;@mf{nu-I&baEJ4EZ)Gmwif{zualQfs~tKd$gS2
z%E+hzyIun-$IkQ+siOqyG|@g1byl3AbNv7hVd-dh$0_|d*hA)m4!b-om+A3!499Q0
z3?7)DwjX;}|G7*b#*fcr*vIS2?T^oVChPIKOEzq^JT!gDqHkR=Aws2ns>O-(!Z7o`
z7Nir#=}UaXMJ0B@PpMS%Xg`$_{iXLEzZBct-h7j1lrTa;$pniBb!x|UKAUQXI2V-q
z6wsYnIbC&C)}%k(V*R%L)@$%_xnjMp28>95PL;OGZLR
zxn$&iy}lN_6)^iUc6?oHmue|~8u5?^?+nz$)}4um*(G{IBoE@OdbKFedlJ=O0Y*b!
zP4X;6&$ej~3y}iF@fF$Rse!nKYjaJUS++SNQ=IYV#lF%jLFZ=r#%d~YHmD6eN2KVT
zOA^o{qM5NvsL$oQy1<7Dp6)Vo20-#@8
zr$hR9cmsX3kM^yy$N};R4tKR`>B}-LA$Bu9iB0^qHuQ<2{1Ir*PpMCCC9Rz+Tc*lZi1K92ZZ!}_|x)8Zjp
z0=2!ipMSH7G~Q@#MgAkkslf{mVmkQIHT%Jj7xLnMdFTd8J9-0EntqLFgSrWy+zzsY
zt13Q^F12Ip@V$}2pC62%-;Cy8x-7#!K-Td5i6tk2gJ=5b*6J1A;gTzS?}||S%dLIZ
z64y0cyWpjM?eZ_7ZCx7O=SScq{B5{azD_V&i41d{P`j)w-+}Bl;s<7)X+Pbwq+N=9iMxzVt9e*wa#+WR(?bKrI>(=JD^d{=re{B}Wa<3nfeTG_Oz5&MBt3Po~3d8u0yi8xRLQP%w^d=GZe
zXu@-|E6-NqcoJ>74EFCNj>qV~o?Ir3eVhBnzPX`2I2N-U%&_#$Mh`}ffHN;Id!5Jh*zy&H@P@e^>G&)XQx_TWs)yPxy5UYZwteuM9DeKDFjQ7)H&ef>D
z0XhtwYzmv2nO^6#PbETu{x4s#%u
zzzWmFX&4&=X2VDWh#v4)@QO~OVD#$Bi%2^|;wny7szrP5aQ`CBKeq9=j=S<5MiLiO
zy76VgGpFSd@?C^?TLut$Qw`Y!Smi);xbMk=*e7%1D)M6dWBn^G*dEF`R52;-IQ*K(
zaO#q?zYS$JSGMhU$qn+wRNO4jbRZog=>0M=Hm>kmBt%cG4oZXb6M-jR!ZEoN{kDIU
z?^$gMF^Cph9vVtYJFk$`Bc@QMSMqycPwJ`zy+;^hd{q{5N*mU67rAAx$b~)x;*NA@
zN6SO>5MhdT+W++K5||ZA?e4sLG$ukgKzLIz?ACG+US^Z!Rr02rq@Y5g(6TP*o4|90
zGXV51O#2JMHSOGav(dxW4fJ>)VpIV=@+z;|#=YNAaUgvutQh0?^JBAXwkWPO0#5IK
zzVE0+5yy=&N1grG4bvEXuY3%|yXhQ5c{=2wbni$9pT^2Ugl8i5u7`*iHkVGKuWg?2
zUII$y^&egBcU^;ow#d|ka{HxDSI*XBAwnv^n0rAL-_;wj<_Rh~AVj2j_Dp_hzDy2L
zc3?FHV&CBSGI?Y4a99NlJUKo{h>v`+&+Cu?F@P|C&SOnBsb5~&3^SK+fx1~wUoq|U
zBK_lpr0AryI
z1+f{9dgB3sne}Ae=SSSRYNHjrcGkB$N%;p6@=n4FZe&t=Df?GlDQI!|@bV8z*Im&a
zNH?73(;1q-)1*%T`)kmUJE<^I)4)tXw|iv#;1M&ox<
z^!f5UF0Xn<Pi(cHiJ8
zrNQXdbdw%ac!QHtn<@@{^QVd@YbL???O0loF?qqCV$MImDMtGzg{(BaL#AD;U>YiR
zz_&_JP^E%RSCTvK{eqf?nnxpxj4Ht>^NfVif>2}(=Ozi-v@3K;B90hc81&e`(?aayTbJbtllwQ6Ze`UYqchtHkXy1hc$c#=+gaX-T93XiauMm1HM%PO_ipd(S4CSDYu~NY}J|wm7tfs7y;Jqjy7!~gLVQv
z@-AOI>?mho*Y&Qw=74HzI?Z5B1!W8Ese1S|h(2obZ|(1sVU(CKTv-H9DgMsK$7XoH
zD9rLiomS4!ZsocQAlEeXg*U)|Ov75QTn^(%C$3|aGOetZ)&^ZAJK(BflzrH0M|BZx
z$W_wzgo=rmoqGZxw8E@Y(M4;==F23hN)RNk3?YkFrqvWdgx14lv%Z;qe%@Elo_+pw
zcnwc8zI+BV4CLyAn`FTvn2mysaMAO?`i~)YA@q2ad*L)7Gb~lFoSyuwN(ue5QV(0c
z;YqW9Qc@DXv{S>IUL8>avo!W$em(sV#5HSfx%kPq(04XLjBq-mnAPyv9Ho`fw27P3
zcfSMf!5TOHhKzQDvY+t77!C02k_eUR^ne-~;r^od&W8XaVH25Bi06M);K|Q`9HufU
zaq}^lyA7Gmt-I&Jy%|$8KwS;TT>d%GV=}d_Mq4rv!{*wb+F}VJu
z#C)+8_Dr$yj4aCt5SgRkx%)!;7
z_LT`-l1u--n5aui@^@K@v0x=+RrG?g9q_GU`mKbfY5`chZSRZiZ+!&fGd}Wps!^-R
zrqTLp1K}?OA`-w}zaZh23805Ca+KC8JZnMMh>}ZM#AjY1{)-^Wl?=VZlcPKO{3+n+
zSl>UUcFC1y5!yiXGNIQ^9zU1XEGjWiN(1d|eIz$yj8X%;EzMnE*;`rZ8bDCzke-9R
zCLn3e44e&h!It>=*p*eM8U^~Uz!j7+hA!KL^2yNx^laN5nnep1K?F1z{8Atdz3hda
zc^PoFh~IcdW>r9KcxBbj+B%@NehcoZ0o$lCRQGvclAb{f`pdyslQGDUH{-zCWL;2J
z^EAY}0sRk+Xb{sXx$z=ig2F3Iv9>qpEp4rU}Ij`
z2(4dF4;`SyR-%#bsqioe`JJajXvaJ;E^>+z+}YvTBAtUt6MlQGop21}O3{@~&j
zSg?)#cR)|ez*gSR_F^lau0ZToe0wi;QX8kGgFQ9>oHn)`L?~Wg-wVZMd+lo>#^4>G
zSBfSn{|Im}73%G!lNvvuTLEh;`yFryR(bCAb7QPOh|hXgvcoI(0sQWPEgDR37vCP+
zFVg$OU|gg&wRC};cK)0;eex;7IaW6qj>NYW9WXooyJUww`#ce7Z2-@Y8oijyXj}6S
z;yT5>@;|P|P&YZcf2NH(aO}`t^UUhhgjD@NiTAn=Qfp;LgGQ`pL-=$Ww4~)a#I$Sz
z`d$0yTJYF4NeiCdKjAva;r9S-BMUG-xeD*YFB&*?VEQI<{T>U?E7+k)iM)v&iW2fz
z;i}_M{$N*MD*>N$_92(t0X^aOIQsSJA4%FLTSR((b}v08u4G+=dcGORmBCOnane}f
z>0E@e;?MU&k$Cdh`Id%9;Az%5Xz6>bH%cU*J;ZyUT)~V{{N)zWz7!b_I_p0R^`9PC
zzvn$;6`v#6U!gWXoh8=)r#hQdXUj?8N1dRz90Uj_HM;6!PI*m(+K&&U%V3DEUi7i`
z2=VFSI-7*cv18D_x}SqfRvNzf$qpATj~#{fS4Vb9V}tTiz~G3WU;1Tg!fTLz?9hzF
z&DEL(R))w5Vz*|x=~EMcR-XfeLtTh{4bDVbw&N^2%kika(LAJY?|?t-C)b=0aA@Kz
z*Pwj0kg#e$lsfAMXR}3_Z}_%n=_#zY&K6K7jhmsrzSvSmlAwHr)R&?c#w9g`ctU(t
zX|J%+ZMy;1&m1?6s`vjdaqj~cWtIJpKM&75GXtm$4*xW&f#Hv`=AxsHx>jJ!j9`Dz
z{F7#-j%d1-q9SUsf)4{4De8#$uNF~2+1Ap@X4}t}kPN8XmX&Gkwi|{>?QT0*{1F5B
zz0Y%>5wz{o=llEY_x0U<8S~sf=bU@)x%ZxP?z#7xIeSnuq7R$)xNk_d4Au6AzB
Nr~zHbla(YSGKstX74D~3f3`Pu-bm9PFwDa
ztN9$zM9DISi^ls?zTM&-{UUddKZN(T=580UUz}K$#;4*o5B2!3
zZe>pUJ!UsKmZ(1XLu=sd4!k9RvE|pa@8S(Qn}jj5%{5!8w*vefLf(13cG#~=8^Eu^
zs#or1{7WhYJ=m{Z!S*|v>u^uiAy%(>Iq-#se?|2USCM}YcXr25VD$`2z2)J!c@A^O
z1n;?^1FT-gbHF!P!FLy{SM~C(^_E-J@d@n2Yo&~-^iYNITUSyh*Hzg0)Vjn*8
zaG>pz+&i1bl?b->-U=&P+C%r2*juh}fuGX53bdeCJb2hokMA
zkA#O`hr9+X%dp?Qlk1DTi%w&`UJ)u{v~3ri*=<~23v`3T4^>5$&AHPZ@ChXbtGaKQRc9UfwV}U&1;uRbf;&RdjJKY{(!wW7NPOwLI!WJ_K2Vc7S9{GQmXHc)v3HD#N
zAo>LF=1{3UEqHMyhO>vl8>~rEpE-H(CH}oy>>iPo%&>SKmo4Q){sn!0-k)%H6Oa3q
z8&n+2t(c2((nH)kD1hn@M4Lj}T-py}znkZJ6QkBj4IwwbeRZ${i94Wtbt>lCx3s_}
zX0^n}`yhB`c@z27l4lGjG{kU6Y_*|9p`8X+&NIi^-X3K1dxP^P)@EYGV=Z&G_#ZO`??yJ6s$UH;<4&)m3sT4>tQ(hY6~WZc4$*cpr?
zmzEJnaJ#(Bkukt)5U6GFI)Fpq>b4fOLIbGUY*E@Zjmi+WK<{G7lA>_Mk&f?-K5E5>
z@V!W~tXA?ZkKo&WEA>f2le6VIQNI)vD)1jBsfb$Oy8&oU=Gk+4|75QG{GC>uHo&@w
z*xr$8j>?Y;E_ij9<4Iy9D{Sl~c+H3Vlnbx=5wV+bdVBhv*RC?2s`B+dFPG#VM1a)YE2(Jy{oWWH(o|f+;G=|gnB88UK
zGA%?Cz5L}(KcM>L1ZJ~_e%RBKgKFP4sy^fnsxILTftOPPF?MO>@+nPs?7T7aZ5may
zIth3=(+SDJU5GunIV9-LuSlxlZ;j}b;~wPMx3O##R%^DtnT&b)kd{ji^zVHK?h$Ld
zL2`Df7wgzCXhHG{=9uTz<;RA1V5U*m-%|>m1}~?*&hk7MiTq^Y!ey>hp0yn#Si0qL
zZ(?4OP@q!MJwH>*Bb~ori4A>iAX^t&6NkJk-$%tF0|gseqnWR=59#!Chu6fI@kWxd
zyd|H0OBFU{7Kt4J`jvNG{P6lIY3>P#$?$R^%V|b)&S+0&t@Xru6O+eEHoW*iGt@pr
zILcfQ;~@Vg=j?pWS(4BHb&Ea}=ghdayGx-Jq9=N{J#hX3Z>tdyV{)+Tm{_7YO^SM
z)pPdUEr`dAtietIw|e1#q=W*B6f_>FdWONxxXYWkU|9bdm=g%AT&hg7?2^n$MAtuQ
z+;QOjqOsy6rQV&OC&o91$^N0aMqQ7y$A~dG|2XMxM!!SK+~5gBKSlS=CGvMvAJ$r6
z>6_6rB1j4W|1N^*u*ErO1_S-GZiSkm#(Wvs2UY&QqrVIiUH#Uh5Sn@NhCs9C-k3(^
zjN1>q&-$9_^Nf4w)&1yI`5Z#qR$9H_>D++7ra^u0|Y=iaXNeJ@>(1
zf^X4CEQ6WGp;^l`j0_RCp6y2@mn?;`!9*A63G|+O~W=t@TphMLrf{{f@ZaO
zvrdsU8;g4e7i29WKv#;t&KFd2GMbQ*XDe{GMh&(PL$+5)#T?-dk
zGazZS1@S{26o2LKDV;Ctlqad4n8E5bI;q}t_y>b?Zm(DTZU1_W|3&rum3s5HQ9bf2
zZeMqMy&&8>)eqnAsNO&yzL%)pT*9~J_Ikzt=wGk#4XPLH!-tcrj#G@Q8Gc^FsFkUu{np__g@<+CiW9uRXtlYDX!x8`t&KZtn0JjxD^s_Rl}CcH)QRkX6|)io;I*ErC=qu!5ZwU`&G9meVd?=#8w{0;CXf2%}O
z>D4-weSbY>r(=)x%oIGyA25mIZgib=s>=lXkc)m2UQO{Ap%L_q#EFBHY`m>qz+j1g
zfjr!+!2L7&=iUrA@MYnxro>~9jmcIqPiBxAXb*F*w*=X3Ksa#4LaQ1
z#Lg!4)BX3hsGO?iK%yBZhq#czdjF6Bq7)u6ZcMOV)h2(@iZ(;%&HXMzw4QZ%bL|Fi
zt_i=(@mrYS&0V#Kv{U>}A1GT9O}kpY?GJb7fc|jb2<#8{d;sdhZYQ`+L%q4Kr+68z
zWCFe?d20sl`}nQ=f)y+gop0r!bwhn&?&)g8KpfAfx2@?23$Odp+gOq%4?ZYpxrX4O!#D=9aU5y2bKFMU^XPFGHBgOdynP9)
z;VYFphU(6h>rM+3@Y`Xbdg#NSy>*i6es+>HXjcH@N(~XoUs5pT#gK}oxe%7BNPZ-?c
z?yO98L$oLER9fx(fBWe33xEFer+>RZ=0{(pmbl=9iJ0#lz{_RtFDZia6rcxjIPh~x~
z?6*Y?dvft+t?J;QOu-lwCD<2VR~rXi^?N$P$RjmqfpCzE5*f#9?iMVyg2UoKtEYua
z_&v)(rw!0P*f0zDroXpcXP$v1vFVP^Hh+~L=Len(iC`Ra?DiV+mi6%m9BusK
zQ@ww!5a-aVGkJ{Z#xE`kpi;7BDqaZ3uBMk;zGC&o(xyUAu8X24g}2CXjtGIo>~
z@OFEfV*SLHdJUKCzFgHVIrrH%KLyS%uYq4ESQh{zbiUTR-xklXoQjgMCyFp4;^c8w
z`xK3cC*0&!Vkrlnq?CtFQeC=%2zMsDm5`r#mDTp_K>Oz1>0;VDSrFb_eJGt*^K$em
z8of8$7zFS06}&Bu8@xw4m=>9vg%g~zzFbl4H7t0nzs-Q?gphVW%%8yy_$uqL!kyiV=A7LlFuN7CS{^G`G>>jvUR
z;R}Ao%N-ia){QHh*t!v0L;5+^q-9=1)O01UkmY5(!}4N(2|Cl++EH2KTRU=}VcL9u
z435QU`_G93iv;+{n4K*#XpXlSG|M9JZK@uzNu{0W&BDUCz%wl=rDJIo^PFX6#6@X{
z?~6)R)~mOCIBVw8ib!5LV|Wa2jMzz@fuT5S#%z4KC6*_#cE^WbAsfHo=M1;!7=sJ@
z-%$I2Fbg(*GjPM#qu_hOYe=3fsA1#F>5hAp@<^{uVpOP)DK>s%>(ECckDLPDn5fK$qsh48mz{O`RY5
zHBz^!?Ju|7!du4_^lvbuRK0{zD(+{LdaM{{BlThoPC7X4CUsd7jx?HZdd5}1?n05WWh0zrCTOJKBM|%!81T9k96L^Xti$h$%0`$@t0{$
zwD#eRX%#%i0YtHUBd9u8w7+r@G$xNz+B6$*hWNY}PBkam_d@ry#bPDQRZ%~n$A7`f
zinGY`TBCy94qIx$WR{vSD+fBOPSv#a;&rF`9O@AK1*t68GRxv-P!^=Kl!{sFXq8Yw
z^SVZ_)gN@PKab7A)ZyY%)*f=6N*qAUa*e4^}n<(!Y~G
z3rDN<0oC{JNwE)z;Ul$0otqk2Ya{LwDcl61=Btn_(PE@9FxmoiQ_PXUF{zTktHx7JR~oO&-nrTK+b2bE2|h
zWsLI|=|yR8>#8Y&tq${0jnbEn2~9&f8&~+sjnRwHDO&YbI++x0!CAhnPHwXVpFgM4
zo-L>Ze}jjX!(UDkFOKF@(7z8KSH3-?!@*&_zyEL0o(Gk7j`r$;AACDCJb+{+;c>*6
zz0meINJ%a?LNNq$V>}RKem#FF@D+sFckM2|BGP`knT+x+cAA*?eYO
zGJ{-^i1OA6F81X~JOW+ILD3Mn<=Zze(7raMd~w>BGBdN>Q+euaE#8yfT*_?V?W6Oj
zXp^l44ddz`{sJ5d(Bq~6me;&(iq6~msDEFIXZvaJ$D}3if>M9SX_V1xXcy4mV%K!3
zj$7aQY8>>z2kv4zjOInz!`^r*0(+X9=V=3X6{@s27kTP|go2|5X^!_1L-OcAR<@x~
zE_?12usoo8CuwBLD=C9gug_VE(Tf#qdz&9YJ{ZADFUe<+jd~ff?g=+y(3LXwFjgjh
zBP-LSqcWd!sqQVfr7}s~w4?1h!D`Z%V&=xa^afVWK1eR7JEE+slH#|=?&s68$ANaR
zY{ok-bM{irAaI8EPh{Q7fj)97>wkSjX_mZ}M=I+hZbJzkDOgh!NpplN>uH0CyTUR@
z2(zHS%Ke=Y#&RkeFfJ4NR@#hEmL7W+<%dfsPteHkE?7dqtzUnM9RwMIL(fV&&Oi?1
zL@P_J7~HRZ>@+167Mx7G2T+4!O6x&$fi)zGt%6(>ZsGB*-}cg$0sUKB@fIY~PtnT;
zvDU^aT0*lMdd4mWNgp{te_}wbC}8
zwJoEUVT!E=|AY1FTtCLwSdOJvApL4kzjR-D%m$f*a%Qp8mKzGaNDUsS@Vkd@dWFZS
zF=<_YDjWyBt{wGVXK>DR$u@=U8@AOI3
zupHMk8|>KD{w;0Z34TAJ@cZuyzrRx8JH5IE>wP_I`C6e5srAvzvug&!JWW^Q)89ix53L&_D;WJcsHg45m0m7
zC*)tE^~A}y9ae6HrsHHx}#5i#0%jbvVc9m0>2mblb`okx@80K
z&F?2aA1mdN&Oaq#e|#X`4f-&g^kn-gc)NV_&PV;~&-@wh+ru291Jxs1!U(fmM57>)Dgp3bYMV(T99m+o}TBqT)5k!St
z_xH`m?<)D($bZn^T5_^h<`POR?mWzJFFwU^SGZZ(jD=p^fmDY3%3D6%t!t0`0ahyQ
z4j<~XU27(X%UViojj@z}AN3vx{ex2@$`LoQHk`KNjJfm?j8o+Jsi4wD0KHw=xBlHY(-Z1FzVbFQQpu2}bcMpZ`
z9tzz(RQMSmD*dcBghBDVk+opC?to%3HlO&P)TA1DCU8kaoDSytT=)++VbzqveEL0u
z?Kn;+XUM9=t_0^xgIxUl^N9Q2-yd<`d)>PG&i(;f>gT%q>i6sJtLxU@_wFCG_tiMH
z$)aA%i{0GsxbxgLWj+;O*NbC-r^%3yJE8AQtDWoguk|ba3p9?RsZUJ6joS8^@XnT{
z@I{`Kh$kIIGbiw(KkyA}(&JtXQ676(O>5(QbYj07=VKt-Rv%X#uOdG-&qA7fp6#Z6
z^y(3X>yD$yH|CW!eKEVsST=*7!)zPG9}t|pG#?z#Z!r%=F*s3Es~vZqQTUDY+PkT5
zWKRD#{gVYPjnxrkTl&CXrj?{cCfWZAZ>(VqUt~#%nCmF|B!-9QT6Zb5$vH#eR`VfzhfvE7
zJnU;(>|uQA<-HkQ-XlH^Sq?ke89lMpU2ivCw0&wiV};Vd8hVAvaB@sbNF2_M({YlW?IRfldqec%^?V@1wKcWn7L|FuHLuve6`G3d-bK2xE$d@Sx(UBFYlQ)Z_)
zw%3st{s~z*85v&g>ISSzI@X7)?0G3v%04zHH10+Fk|Qbxq2kwGE;9$#=4WIBo%yrR
z=J|UOVir|Ql4Fa!+^FXR$Hl}9+%$S7Uni>dYdV7RtS=!}EBO9({}pJ7$#aSa{LrVZ
z8%_jzhU4p)pS&N@y5SAUb^uX|$Nc>Lci@H2-CWUZ8~^gj{T$hyu%@`}S+`hI-1gO?
zYMRd{QQH2N&$~dk8Imst-foxAE@JVQbPH2LzF>*P4IS`j|5ku@?G(3@cKxbgNx|;}
z`2EFi1j`KkK8D|Si|7xAX!gz#s@XNm>OF+_Jx7U@?lH(LJtAr~$Gy~K$N2IJknjk)VG
zqtD-ih`c<@Fx=klZG1G1R)Q%wrRGX?iXq%^>oCl(-`zvKB;27_TYAY`F6WQHe_Kyp
zO~^-y*88vW-za^z$;%yEK)YGIh4!#?$y{wn^38El?Bzau>QC+`GRx~2-YMFG`pR2Q
z0Rvw$?S(!K%#S7yw-OzM(HTor97Oy)qe9M)Auk(#wMrHz;;Wo0F3EnX3Lbf)?u(X$
z&5$D5x3KI*=2={RwHEbymKoAtwUrM!hsmO9ssK_t6BZfS*O
z&3*W2ktOvp_+z+HkJ?L?@=ubyOczxT$zDFW_bCFm|G%5}xRkmPmsPB>%9fzoKr5TG
z!KY=)+EMdYX#XfhU&t-ZAj>aflCr+HU|c*bSz)JHW4Ka`DeOo8N?Fg5ckDsQIzzVQ
zSYGoBEUyB2SJT2TU^J=YUSQFe8F4JH8F`~pOW!1GZSe#}=QJ#^`0k@%cceJgNm%VJ
zCg?ZQuE213fQ>_NgOa6!v+FwtG3gBI6)bNk()q{@DdiG&{qSO=1@ji9cZcd7XyzYu
zvvF{hD>|f##P|1-?GmK;Dl8wGAsj1r;O17+6_^jywkt5Dv%DM}&YXnZ99AY1{QiZa
z+sZtvz?l)(U95dqDjCmWhb!&-814H-bOGatr-G$A&Z8eEU880e_
zDW2zZxr0A>8-5f&`{4En!G;!6{BmSxn0LPG8A;_Kj|SNYG9}`lj6?T8Za)rX)TlpZ
z)L0Bk{vRP{qkVWY6wS2)saF#j-nb~mJAckFv_IqwoX%OLV^Av>GN{c%8Pp07>W{cp
zE@GcxdCkZh^|M>$BI9wE7mMf%*#EHD1nVN7Jk4Qw8OS>pFCk`Du;wdy&9fDJ$h#UV
zSPy|0=lmq=8=QSe2O_<}my!;@B6rG&SR4FZixJOVs1fuXok9A}Hm<_vRA-C!%ZPMV
zYXqe~rZb3+Q|J$auZJ^cg04Fie&`fi8{WthE+%QqKkbvW*Dm@bjUMs)4Tlysf|~%!BI{-af3zkH{!%ehvH!SH_1%IhA0zG|+R*
zDH>Gv9c}|@srFwt`1WsPIe;G3C}lB-1!)YT$T5hXYA+W&ShA*ovtty_S|+nR@i&kU
zorK;HFp?RM97!zCg1qg67$x;L6zMcvx_i%C_Wc(JEA70iQ!Q9NQPvBuN3dL0M&!>u
zK0dJ#=o^u*onosIM&ui+Nw{C@UCF{mZn!+!GVb3YzEgs@?85k6q)EI}Qgi~|S1wcV
z^_F-)=<=(5r$0v>`_cXk*8Y04(*9PZ{d>`VNX;$nAFZ^1AKH&d@LSrSsI(t>dB2h%
zjk1L%k6h14mghiT?F$kllA^pB-^6CcHzQ?*3HAZud4C
z=Q66Vm>AU+ml>1{tXv1yFeq29C~}}1wc^qr7@wL)dAX>SU%$c2cTyes6P=%`E;MOQ
zU%`Vm+INTp_#b9h?ih`~Bd<
z?>O?TD>!dWvE#T6FSwKypZ!*evs#x)?dXfdQC|=jl_pXwP2<{xokvobCU|yu&m5*j
zeVyRQh<30@4K5(q`V4pTt7kM~PbuDqR<}zTI0sv7=F=QKA>doa*KPeHQ)oq3H7&j{W&YDVF~RasDzrW!K^PyLsn8uu{6hh#iJT!I+TGH$y-A4ligb
zIgV(`u}7K4lyN3iZqgaV9xQNv=#98*?-$O1
zMnxk|i(#67V07t!p-jzZ^V4z->$4k8F!%HXPh}H
z)TubT{~<)?E3`zS{f~mu*1KD0ewJqoZ0IVm-(83sS-aGqKd`wW&+;VhlUsVS+<~}K
zE-yX#B+hKUGP{Sk?2+RL67okn1|$*Ba9efb!SKi=+*4gjHh1KV9c9h-+sjpr=U5c
z&Bl0{xrigrtjSS@cSXfX6caC(pIwK%LtJ$!y&Lgx{qfCo=M9}EiaU!}b@E4U9`_K-~jipylRuAcH_pmb#YYVNorT#fTwYU@AM??blQ*!#r1d}9TjiAvb4e*Y*U)eMOS6}95~SwkmuSv>r^KGU
zlZ!5Z&3x|B=d(`6$-i9dsf0-AIE>3!za7{
z|8e-xPjVQtTxtycDGuYTNvOhMoRhkp!&g4;&taUS)mR2b*EuzosBnx$y-JlqGp4cp
z$|7}rIO)Door|K54T$lFvj6uSUcw}<5p@h
zD%eeTWUDZ!hn|W|iu*`?L1>r_*~4p(RfPlejzVlTMJ83}3snsRhBOEsx}RXWopyS=Xb+Iv2>O
z-KN=mQu18nnl8QhEwySmW)8x6>p?Byo4PM&0*1EFQgaKQ}Md7eItI&{)*Cbu|tP+Gr_^e=1KD>)F
z%{B|>Fr4&>ug|}<#*HTt+lxKL#<-4rXGlKZ6Y8*;uD`(rnl+P*aaXq5`L?^bQX4=G}Eb{n9f{hwyM{@
zT@xvvORCi5*6yv{YAm~$YabF2!7!=&VKSC=Y!oWh#b`I6X6-c|uHPzDS~urxHCESe
zdg3eSE)m98>o=OiI6u(eYCKw>i~L-($nkn@doMUK#I#1uKeW|YUY{#fSS9nDH8HMs
zkw3G=SpDWkDb{L!wiu;^hl-5}SH=ld>cTGg4vdF83Z$y~e6;xnwb@wNfmhz@HzjB5
zHJw3S#r{js|GLj8eUs6k9)r6I#u#JNW2jYk+M*E~-m=weXdT8*m(q=fX^zRM;)3P6
z6=_&ogW3j|H7Y;q1HC3Y-B{K#2D_l;En|#_G-EK9&3K(WuO}?47=N`hi;b_gfHE7U
z_E0LIkDGIHAbRXg4ePO3?6y#k#o`u+6>Cb~cD*&6cb*x-=?jN&tfyPh)8lY+taW4U
z(w;4zEyn0KHy%4dFw~U{M)ThojAq=-mALX*mn;$gQsDnpfsgw}R;)Piwn)DU4D_bv}&=&@ulQg(HcyrZYXF=Wvfr!&Ga(Lmmp(aKsP;*j+
zMw|Sr1nBBwD|y7w_hk)Q$q~j0YB=_hs~>bDXymTi487Fe8?AO_d3e*B#hkBP94Ck<
zSEFyJl5)}XD-Z8#&){6m9*ixwmS~kI-?4^UziYDE
zbuAQBUf@lO!;s%_Ge2RM>6*wdRGSv7S$bt5Xe;0ZaL5UaBTMOoHDu^ei4BjZ;2#?0KzrJKNlqzN2g+Z{l
z>L#)B$5qY6O}jOB`DTEOY?2g|FWa@zE!M>BPsS{;(cf0&c0XILL9cp0ET*|(e{zv~
z$(+1@(BHxgm${YGmxgmbDDC?oXD9{v*@zd?4fLB)`u37OTFVLdK1~RIe*{uvNxLV$_F@JI&l?q39YqX4`HXlc$Z*o+V
z8&vd0N+jdxN7Skv8kMiKTfMEfC#;=#iW+9LDsr+EXG5znr-TyszS;Vv=96M$bmvCo
z#M(A)widaomX>Q^^Lp{hqnysT9XZ*@ZRf6V&WE9WAFItcjQ7StjZYqk8vDzdwQe<5
zi7NFdvu0bb(!+;$CH`CKX|hhMYpm8hB?FAghCDMf|Tb?@%GK9JP$YP{bx8x#ivs=y5+-e<_
ztZvzaR0*rVwVtqh_u+eEL>kTRzI7tvEJksF8S~(b4}e2=Ns;6df?3w0qcrygtU1}5
zYx*S`k)_q=$}8YuaH{eO@Mbk!!My?iR%R9zVs#%0&
zgi`7xj-?6})^S&}v7!a#Y}rnldf5}0$t%ZEI^-1ki9Sp0)@Pg$SZcvItQ^7$A!mzQ
z6VIXSAu3xi&W&|YzqPX$rEByVVmwQ)N4kL%mm;+lsl2h0O4pBb`uQih>%ilz_F|-`
z`_k8K0YsFMs_H>2*G06tTFj_N^sCKgF;AiYF{1yloJt&saCJ8DNGX$BPbn&A5cPzs
zWeKgn#FI(r@z1H8yiOxUJ<+^1h+CJjvuFe*@v{0cQ@4i?Qvu+Do
zpJXhn94}N@$D6X+c~b_hlEqGG#U2th;Ut
zt;kfqK!J<;huAmz4{N>x)0ZaU7Hc0&Uz)%zGHn3NLsupcoON4F88aD_*Xqaf7So1a
z-n4uJXRJg%QryCP!L;G-+tLPcrVT;2q?tB&In(l|lzJM8;JAahZqxE!9%EAyUeidf
zwRiL8ARXuW>MNv$OVVMKyQbycn+9^Grz4Q2kpxQ1{)#g#nGG$9X30Vc;|jCdMc%Xo
z{qibHGiBqR^(7h=`))v)*1j@FsZ0alC}retO}<%M(^sYpvu2ehpOslcvtGVv`}AD_
zBYweJz4lsA=05plgu_?Hn{m4jwCE|uqgN&hRn}zS)fua=B#naRSE#`}SwOXD#zziX
zab-NseoB4JeW;U2ctW4nYqhVNs7(14yrXT)qcYGI*({o;&o+1KmlXEay6s!en(KP!7R@c$?`lY-bOBQIbL3sZG=dcOM5Z04RXJ?(J*p3-e4k}i=Sq>
z;t-aLyO|o3Ml5fA5KFM
zsX~)0#1$%S@Yvqo92lpLSl&86;7^x)cYBl`B0p%|L&9v4lP;$CNi$;+RcGPoZV#d1
zJkCIraQ47Xbwa*m4VC@V@cS1C7Tm$oFaxDkC>_H|v(R7g!`Yoxeu#;ay@bXcZ}=IV
zb$-U3=lzT&m;H>p+WeTel1k96M?Y3#IhQ^I=MXP0@@pz_Uz0B8`!#KExF%dY1lSoI
zVw5|m_KpE~
zg>{SHHEApHDu^mlh(FCamgcN;zS!04>Wt@2*|Yg4ib=+#szSUHaye3pOF^kkoH>9q
zm;<>+r}lcUt79=rhVxkYqc2AmSu2yIVfm4ecGv-(y=DQkLHpC()vaf?8e`6*_7uFZ
zSQn|+c5TQkMqScU;x0#?e*{*Y!(U|_d4BNDM|18l8qSBDdlawZMc0LFn{AA#3pqF2
z7>D1F8;9ZdVmEE|yPqs^|zlYU26&5>N%3_z=N+uiBG%@(w%cZ&R_se9-bdQ9RAq%O3mrzbxbNZQm3%Z_dErs_
znxf5Vkvgm!dzf6n=kG~Xf9!9gA4Xm!S`eQf?P{OL^VxEnV%nnT&BzINtNl2%Mn!xU
zE%;@SIo=Y^%{wn8q{O+dC-AQ3nY=Oj4Y|K^hIAEwf|ugk*cX0XzS(c^l})9#iIz*?
zW;pI@Zi~ZPKWQvY#ww>6QYnSBPxi)2#c!xQ=6U4OO2O`ku{~#67tgzvPQZ#WZi0aJ
zx+`m9UfybYehF_{HWlyIJjnBSFUM5a!3AFENILgGttR~xy}zPs5bzR9dPCC=_YF7n
z*ZqBZ?;Ef{&tg>hbl72S9F?yd2dRc0g(+ivRYg+&2v_6eE|eCb_1
z;W^~T6Md;Fvs;q~t(j6Eqq4(LHcmAOWg^Tr%rqGHPi)0ZFiD6@L24tH6aMU0q(s*d
zZzh=wg5Z7B@Q^E+TdIlrP1j&M5C@^58qg!Ls!3hhPUza?3vxD#fkwj{lO*7P7Jt91
zV;t|gvKaS+pQp6(qFp~o$nDztA#k1_kGkXaf{^5Dk0oEB;f?X2ZM<9La)~b43uCAo
zPxV|K7kH{6=c~EPIa~FM)k#L=g6{EDdM43~vMJ;B_3fBr@c?xYkR>Xe4_s=h8-uT5`QzQ{6};=(Fy8gmr<^e+WP%WzFKeFALt_rfC3uVL
z8myIhSi}yx5x!eQLZ0{d^s(*4<@C>)s64kYK$ZNb>kIk=&MpC
z5jF6Ab-S*>_jLIDMoKelp^2h}{nKEd77V1d;qYZ>Z7NBzH4eAoD_?SJuJy`x`m2mDEe|M3*`LQn*{Iig4`1k7a@w81o<&n}~`
zJif+Q*^&-_LMwbVF-F71L1xX)7~?PvXH39;5cCKk-sYC9Ho7%Rx`G&I=>17WiLwiP4W&^bejw_#PXCQ}K
z_`a4bQ<7xbH~0n+^&CoONiyVHlkG`5Tz
zED~(^e}+|!hkOC24+rHEp6Q5fH6E_qh+ODP$en~SfxQRPPou@IV&s-pPGY0!&RWrS
z(9yyXJu-f>!*8QyW9~tRrmw`mp>|^~_F*O^2b;t)aLxPrqxw=eEYZTkHS$TovX2L{
zZ;kRT2;SFSatkR=gZ6N!)^|ayRQzgIYgGUsO(s6jEzcZRx(oJ8W&LvArr#7NI1BSG
zY_|kjzk(*$!ik!uJKQ&Tn{(4*A!-VbNM`suaQmsKF^X?;O+z%jye;Z${iZ8Il%>dW
zGcSPhs&4RBePO+NIPNPivNUk6f(A}h8;dEg@~v|5{bLvYsMQ#;4TPo
zQ^!^`Wu62{Fq
z5A7z7Gy%-w(M<0rtKq+~12|nER
z>&e#RwBQ9&@uo^Hmx_Cq#^S7LZsSOA(zzkNC=ff}zLt%FmJ|W6y-G)H9M+k9^&aXC
z@9PgNg3cM)lao;3>Ufj)kgggjB&0+hEl8*t`L2BaciW>6mA*ysU#ZDLr9UTCrgGu<
z#yNr{^8mmo6J`o=NRLb9%mcYb)B0-OyG^>!`?~#Mr@Fg03%*MWG|oejezqMpvj0op
z1hj(1_imc}-ehxNYp?6t)BMDOcM2xf-B)j|@osz6>cit$RQm$pKjMR5`%C?c-9g@M
z2gl=<_bD5vkan08!MvxTq@_ki+l~WAor0s%OgJVM5QcXO2(~lH2iy7L_r37-^MIe~
zgWog6>|fgp_@e=T^2RA{@>Ib7xQQX|P$cfi-{qa3J{j_%j}}c?GkI61jmHc)^3Y%<
z?*RdM&g^zU@5tYUHMARZ^vJfs-ubQfQLTldIq-hi8s?j|@&U2+e#*-kGFg=UD_I#g
zbL$A-FQCVT+=9<=C`9j&^Ck(%WB63qpOx_$+Cl)+Ea!wfc)WsEYRZ-^L^(${f#6LB
z{TZM?o^Z+VQcAt^w~c{bdMmDI!X@X86_BU2&4(+Ra3zkCb7WlkK3sB6I{XAFx8joF
z)dAPJdoZqU#T6sBi}FSa$Wz+2TWMDe;aZU(=dgC|R@x=!Z2K9(yQN(+yp-ME`MP*;
z_*PtTa=R#R82ZfDE+4Kq!u7gQ&SCBH;gWOC!Jk-nD=ryc9pI%Kz~9hY`fHfnF3O8S
zuY@Y?+M~2(PUI|nBYv0ZBh4Tunyqv?@wa>NA%)7pZr^YZQ9C>~O5iNT@
zgC`5hwDf1li3!Iz+UK30^egZf_+0B}@}}!H-t_l0%#kTdu3-b^V%-p&TY5IYdh5pc
zj6M|hSdzX#rMk4nmE%U~H-Nn^&RN{i8@2oitW%fcz{|MIY^Syp9-~qoduGg^iTH!y
z=X_pGy`-vfZtdf4^rSy9ND&z(p=a*bG5YazHiWQjeY~89Uhe$
zniXNkk37H7=O;~{AxE?ilCX16UYV`<%gO$iB&;||u8t1a^jFB!
zkpvzlk(XHBIWk;M0^i7*gPsB?2H31}3V!S4-!TJbASUDk*X2d?4eB8$rME)-`^`rM#K6E2aPIdC~KB%=3HV
z+lT0^lcKl2=UD7pf1UYPN|(3ZzbVfGO+43u|Gw7Cac+uutJDlm4#ry#e$~6oh;0~I
z&vVCZ`ohlMiS^CBQoMR_NpVxX<_77n9RBC4RFmiaySfxJsGrlG
zY_c5T`gAjT+hEqaCNVY{5@2{VOFW15F<0Nv)k`aOVU^XdtN78Zb{#Y#gAiM1aH?AG
zcL(s@F83Q;&(NZs?Mb6wBzg9heYb(Nx~lj51KS?(ZZoEO%S_2`O|LLn%%QzZ_!bUf
zhOC3XfGZ;lLxvfzih@?7lVj3`T{fVXqCCvTm%mb?F!pjS@Oxf1NU`}*@WSQ(=_TWc
zod&xmK!yH@B42|HEuqZ-?^Kj4djfA(b2Z0H5r0FzQ3GjP*ab2GPcF2lxK2agt{25x
zQ*^QbNNzwPUn1cW;`5_GA!?s-D?4^XcP_o3jP%M51NFwbOkXU$`a<;iS!d^-W;-a=
zc=KiA=65#x)2W$(?GcPK8n5sww6Rxhod02#vg8|I3Tb8-$qPVZqw_`b{?6useLkg;
zzT^!29%m3cTAM7|kHsz9y?@a=>+!ciYDkSz2L*YzgH$
zW4vYhVd#Mc$=R-PWzeHBzLGG)=L>Ol3qDf2MX1k+AvY~M%Na+eEC3G{AS%*e%FgED
zuNZNjQ3L%bCw$!&7j{4}Lyb73q;g5r3y2LGv2#B9VF6|ggR5f}|5v#t4_&cf!8cpK
z`I{7{UMR#_7Zz2j=VRAxzFp;yG5r~5&&S`gGn}jNg5Q1lu3Z=WOyTu@fg$yV-|upn
z+qidj9r=>kmxVHyWQlpTWj^+y@y()Ku;)Ast89Qe9&G|NUVcM;GFX1O>cTwC0
zduQs*lciN;T~M1Y@OLzIH$URBEl*=;%<&Z
zW%PZh{_*kWgUBq9&Nv#&Z`+cC?OeN>pnp0U>p%96G%NJkosink-~A!<9~;|L|MST?
zM7P*uG
zr4GscNOljRQ=i?3?`ZU^R?hd6^R?HW0&l$6zF0m#*Z)WGFzk(l9W)x`I4dpS%%5h#
zx^?Ix$;!XSA>585N!V_)e_iFrdaf|~(weu`?ZtH7*BDb3t=MEY6r0TN6WJz%q<}+&
zgGy&ntI!JBnnOu^gHJxon8rKix@e3NowI=6WXJA>;W8kn;GZfQ{4#`BkhC^G(@ygk
zRyfMLuikr(GaR>t!!x4Sv{Wl)mKV7j))iSgQ@rO4clmNPzhSu!*K#MlAeb4hw%N(EA4wV-FPFGXBcbRtv*dV+l^
z8LJ$d@vUPm5Lcsq(1SCS_Mo&}e~>T5vRbJ>(3jGTl;-hhPoOWwk;Q1O3Gk)Fu2I_K
z?@RF@g=o#y`cg8oiH=;2!rxzlA8IL96~MkN+2GnFu>t7yBt*Dx
zQOd7HeLpESCC;&=FSQw|^LapsW~G|f6`eSd2>!_L4Y9O}^@sK4!v%(2P)ijJD|A*`IWfC0MT~M~!-|jxq@$Wlw}tC1+Eu9*KCV|w
zrwi0Qp=M7nH&GDY-=%ilc!x8sI>wAuc0^iq1d&JGWdE2i*P2$H;#}80Ma0n4
zoL)bY)2})eU8uzOR<1Y*o8@PZBK;zoPchVX}YsQ@CFRZW(Vw
zX3_4iZsNR&?
zTDVeQ{K2j51gCFr=TG831l+8hE2Sq7bAi7`TZa|P{3Sl#Y;UE4w_LL-@U9zu?d?7O
z1Drp}+rvJbwpIP{-NaSRa0#y!0@weNx33a!Pb<7_SoK5Re%05;qdwkhR{uwMTNa+B
z$nI+CNiE;Mt+(*DJUmP8)AGXA|7+eJ^5JY)-5=jg-c~YPklU>PHE$0C*Ysh$(#EVG
z@^%V;6K}QB#-oK<{}JB4db6Eb(vwgBIB$>oc&l0SzvgXOc(&5kHUE~k<>A@XkC0p7
z`d`ZJA;5Za6XNn{?rT`%)M8GHh|mbb*xVO5Uc1!vH0HfZjY5+qo90I0)6;69VH0LL
z7v~K9ihFj8aC)~I8c&cbBZG@ZR6j)(=);C_&W>?7lTsgq7=yzX*I@r(Yx3vP%t2hZ
zg!x~P{wc%@oU@>rrxhSD{Gu9rj%y=q?kQX^cDizLE@LTloywNALY%-sJ6YEg5g7KS
zT9{cMBv}iB%%?H`i_*ipf=nA=og+pycnNk@gRUYL5j(_)t~M=c=F8R37SkS@z7#Wm
zc0&-+1PkHt#kJD(ksMJVRod3+9bfW+;Z^Dg8)257e3(v;5%y|ek42f+3fJk2|HTJ}
z&QuGtJ;3h>a`oQLPt*vOk|46x3A1TQXCJ=s*#7ul1wOeI(0z7Y(d@L6tyuJ?dMRi*
zdT}k$f$_2)T+j$J8vwsB$n`707X@2s5VcK)pYaL7-$D^-0h)fTDZ98{c=9=4Yu4*U
zPBJ_gN5q@Lp>U4mM2KCp%rWO{O@sxKuM4b@eOh>UJ2u)HQ#KdonB`c
zwZh!$?5Jm_YSwSeeInCYko;|VeP!L*ci*p>_4(XCKl$mx3yaS$`)K;#o;xR%7VuKZ
zVqRa!|1EG=r#djK!A~l+@yZ`VooTra^@hei^@`oA`F>8eU+c}y`k^t
z-0fCz8uuWaS-8ur;reLxruB3A
z9cgplb)8KR_6~IQJPS|VL%e={K)18!xTVY!NB7YW8e#;X)s%=`oo_9U;GvT=+=gVg~SI^79OXx^vr|2Uz+Rr7x?1?O`y!x
z{WAaVL*zL#eLs~SoMt+6k1%wgYyCsK>+j2W=kt|;Qdkc8@xw1cc
zk*FaWOwWJK3qz_oVdz<|XzyIjLVwe`J)CLjQvNyc`bEyP?lbsC6ZnDv@VU*`V0Gh$(h!li+Z9F!XfzExHE2o*Y9uGM=u*X7H+{?~8urq#uq>&AKB_1t-QsxD?qub}3Uh86l>-^aOB
zU+_gCrGC<`%bc(?pOZ=#aYxmrU!CDi-$6d@r+8^s3P;+#UVoVPz0oSS^%7%ERi_fx8;~giu%pp)KkosYNAjKa*vwK-Pg!ini{K
z6pvD_olsM*6qw+G&*F&N+pS-oV`&!L07)gh(yow4rkc
zYI8}ib_QJQbq8Wcx#;^1<^X8e{?M?8xK+@w{kTNv*KIv_L!TdjQj*OU>;=Y%cYYHk-e==2)1fL&ibG<%nYsj`E{+r83fBp{t(=cSQ&v6iqmugbRw~t6qSLimLpPd?0Ielo146?(VdqkA
zq$ri7f)i_C`DfskidiaQ*Ko8H@d~R`_|%t(Z<;96>KO2iEVkMo;hk(>mQ?x4JRAue
zAr-)(SugFO{_$`NRi-udfO(#u_R_yZ8nXrdG6z>LLVTo|f9NIZO{1Z3y%1wtPrW))
zOa1D4eznr8YtgH6kD_P$_o_LH^{TLQF?VK*GpwG+9wcY#$l}O*a+o)5xWZGfP%J`G
zX`!EM@fU~+zqnr7RfXHAfNxg==Y+Lwy5T{L)J4QYH1N)_H}QK3{M}*rzJ~b4&h?{b
zl+PGEXXBieX-#
zursBJhQ}T8Y>0fEZ^Z5p_KxP~Wa-8Bpl9VhG2_wykF#%&i>g}t-@~4n4KpCv2&0BI
zG6G8Gp)m3Ik`6Y*C|)A-9u_zUIa;QkBD3TO4#S88LXA3BTBHeOW*kY!I;R8!M#+@S
z!22acj+PCUFk&FT@3Z$FKu>kv_xA@M)?Tx&&wAE+p7q=oH=ixxpgoglQr}c9NPq{Y
z%hz0DO^ua9-wOSkc4tEhWGzX&uf*1dBsRjh#u?Fd6uqu<<}w=c8*!~cZuUa*DT&rb
zxw4>-Ta%iR8N3h?ZSWgu^l&TA41V-YZLuq??3sn@%Fd(B>{xkS2lc_Xy`v$^u>h8{
zH3?m&b@KbnXfgXu`{kLit!T)?+!XEbfOaaJZH#8~TxhSZlQtOt;c-N|uFa=HXIuWF
zvW|r9a_9*s=7TzG)Eh{{W${70xnfnik-P}jn713(*!Ie1DEFo<<~2HH2$L8oRXQ`&
zjD3ya9!OJu;k`SCUQ$4pjVL%81~KR4(2+&l@Mk0Sid6XS!bdrbe%C8_%_!pSAeK?s
z4dmn~V_hBOalQ)LZ_=kzp32@F%ODL)C#ez^9z!WtuWT=Th++#w-B2XMJJ;h$K0I6J
zguloX^k8IWSFn*)L6AAYVn1E3jkpx_VsdQr0L0KXDj-?92`>QlMZ5r<;~NX#5xd-|
zpqL~p3i_tcffn&S*epqv&~;)SL#M~O7=LJQd{-b^#NRKfIOC8x1w)Us;rf7BPfORM
z9P-sI@TpM8p>EWB{?ORJnz@emAsSKj3T$px(w7`oD^)82gO!Xpne)=8o1ZM>_DyuK&ED`%vcAx}Eg6(nDS
z-gUJaZL>z}@khQCQnAM$q6lZJQD-H;BT8gb
znKc`^7l3I#+MUh7a91|8(F;hnDkr`6uI8-Ii&>XM5$+P(%@KO;)oMDY^0vAH7}HFC
z^Z%=s`8MQ;f(5N{CB@Ld*aQm^X|`Yb6!jIt&@A9;wy=Y?e=B+?@p-(bi}1VoYqC}t
z3a_JZshQWomTBTBE!O*n*M62=AU`)TuL*h3=av=!xhF6D7_ap$OCg^&v0NJRpc^jJ
z#P;NEM;B`1IKK$m@w`+w>IdP8jubkh}Z)XUr(vbefIu
zr`S;nyT1jTSc#80p&A1j@^K80t;Nj>_?SXs?o!6e
zgTR+LSaz0+x30iZ6*rA6EOs?3a3cHjxE#rCRvJt7!1;>nXpiUs-_BOTEzVzvyb`|x
zGSikFHc%CR!kqYL!JR2!XVouO5hQWELAKp_RRf9v?|bP?9A-fD0{%2ayui_vqmpS@
zvJ$2f(p_8uUri}r3X(6Jj_%^(M<|C%H4%m(CyQ)|l~XNb8(r;zpD+_PeRq;=Gv-r&
znCWei6E^wv$>%J)CkZQO_?L22Zk!=?NmTBe@hr7@`Ow6=w_Jqp8zsoGF6c4*XV9V%1r^5A$wWtY;NN
zwaG5=Ec{pYqLhXFzL?cnc;`_!WxuyS!Rz?|`WwgBp#B(U(6aewRO(PAxj|d_CR}9ycQ2FWYpnS>sn|pQT3R&#?#Xvm%+XwRy&|N1R*^
z>>}eAjXmuAwadNYRm-ASzn1fM?p9ac#LjzF%3oL6*GBnf4j5ZQ${@7?Gh@Iboev-u9A2yX!3SrVOTdp2G~J
zd4V=$2jvwErY~UA&TBZIzt%eCQigEr8u*TYFr0SH+F~IcvmBnz=~!v;`%#=;u*BrQ
zzSh7(u7qzv6O-iDemYO(#8CDc$>GBZ*}f0ts!RKN4l%IVYww@E8&~n#bwV*5?~qS
zE8^f5cX81o75Ej?%u-2q{(vf3*1SEYrvs#0*Js`|#Ro`*ax#<)`fIknO}9XwFmdn1
zh{TPF@<~5GH9z@S^7whX=S5iR_2J+I^9ofBY9`8&XC8BKY;E5?KN~F*Rmq`DV?pe%
z7GQ#G&%BOI=bx9&JT|v({^13+eV@C&(y3@UAOCFFnTS(~C#KdvePq!=`MGJwpGTzC
z?1|ZWl@wN^L>AN8HJJ5L{)n0h*JlYy)e$cxPhTNa94rQ}#
z9|ffRBtlST1-xdNBMMS~vW8j7&QCl1Y|7N!W4X0riS6s$#Y<XJC`qJ~=|AU#S0ELB{&q*s9do&Xx$yRpz2-vpkyX9sBG^mPT!a)q
z7k@ur*!Ip>TXsc7BoU|hJi{x%*FcDYP}9nUtZZ`~-#RUuBQckWF&fR{nQm?r8^|5`Dk*|Fdi$uC56!#8+8
z`=DMNlk625Q`z`EPHOuDqea@dzWr87EtR(){V;=j@&nHuv?pK2QBT
zY5wG6lgCflJq59Xrw<0snID`Yw%GI{tys~cpYE|Qzt!Dqr|;MQWSBoMlb;Ja^YoEX
zISXo^ui2fy!?vqHz_@A01#Db|ck}j_4l}rmmd+wNC)_t$x>V}*h}%KuM>F;=Z*_T|
z=cVv1lnLT(ZK0XQt%UZyIntV{l3P<-3p-E4W^O+Fpb^&O*3`GT`vO$+0^(x=K4L4a
zprYqhwl+inN|*FMAe-oyX!mPj2{)8mJeqRLmiY3VEfUkKEBczulT?UDd%vnwcA>m<
zBV$)E7i@1f>1^xU#@Ac$hD6J_%{1;7M1z3ssys+zKNG4WT=!xG?E~1z_reeG!Sg}4
zV3V4YdLQ>TS7|M`dVJ!oxFw@jRf-M7quk=s*|t>a8aMg3&`KZsjkSK>vU>`x
z^w@&>g2wg!KV95!ceQqPT4PEf-@4Vx*w$Ye-}E^kw91>mQOv(QzIqSQFQQh9PV}Z<
zPoJBAX2GfF>+_6Jwq0uqr3tBaPwP0~ZN*8!T6jkr>^9v+b&n8c
zh**FasX-dD)eIzh@_X2U@?Q&>0Xt&}L%3lFZd~)?MwEaXPEf@A6soz3_!vbZ`!?4(
zpwdd-Be9`bU7HR_^m&u){>%mCn;wmw>*yj1IQB@nbw_-R-#m$G-XNXH@73U#QitS=
z9NYRI$46LAUvmRN4^!>SJ>#%P?^k)`m`izhgoLc0l>_#U*Y4=#=TtP*OcV*LO1R6%
z-`I&W5qVfuq%dZrTd}U@(t!Eq_ovJ!I`lU8wy*t!Z+!Wh{=j952tky{w#lPO$TwY^
z5NHZ`wQsG}G~Ev|Qv7smDMsSKNP0n3=)Fwy$G!LNn|;sQ_kGg%oET}2PfyRv^&XAs
zFM75yB;Y5aQuQL8>P@9)S~eyUl?to)eofe#T5E*0Hg{3(DT{bUjt4zo5w^B=ZDYTH
zs~P)$PT)sf<>~6o>CDe4v^%O8XWJ@bhvt;e!zvQ^c1wD-
zYZ!$X$uG`dTe7yXf54>;PO)9}AqKc3wigS|4A91kv?5BYRQJXn@iv+23=!f2*d4Xq
zy?aZyrr=cz@NfSphkx%Zx>Z^)N9FEu5!Zk5Xy*C&{Z;Co>#0_rol49nm-eYMG!ALG(BtE@HBHnw2
zu^jqbn3u6`0}tU1U(xJbZ}FS&f=#4JAb;pN&BkMpVG%SSdn#izDiK8%x1$)`&%*V3)3C*LTf
zKfYWW>tQtgg&HN752A)IUy4t2etde@bQVHW=K3&S!6w=%Hnp!^pe9GnLi|>GXfV?o3QKQ%!F^)eIBMe~g}nh~+=V
zIK_12PK>6Hn7`xZw?fMG(LQn3r8`hhY$I~#P49emq6G!r8wH*#;uP^T#M=v;*3(Cb
z^IvrE`I_VjvD^*ZQJqpLymG1wlfi*K^IftomTP|ylFGu?w~{Ng5mKMf*}}=Q9VbO3
z6M7wS1>ujm3ihpV(JUY4ap>N$cu2c%($oVdy^i}c0rZWg==
z;C%q;0qpv+$O{gVKHkRwxxVm&>i;<+-tgXcs9mM)X$SS&y(Mve`t+m`aYtx@_fhBh
zbzdhh#cCz5MB?A^O&%UN+Yl=nrwN}cCAm2K-Er;@z2TcYS@31~rZD+1dQORj*OtoA
zMqXDDJing;9**Kz;VVv`Mt(0x+Y19I?g^r)$5o*Y&xKMSEQ3Daxd#4jFnR<{S3_<|
z-|!Pd8d|4{@@C}0&kOYiJ8wc>kLaez86nhyOd-qOj7W-Nt?qB3h8F%#Bi8fq?G4vE
z;duunHJJrk(GL!ukr7oi7I3N*p$PC!@p6yIIS)CJ$W2!9H)*0u;9cRbCDdUw0w)W;
z1iX|=D)QMwIPn%xy#ucZ6h&v+wo6k)y!jB{EAdJJht?ra39aa-qf-$u4$3I(UxA1s
z;F)J2C1L1%vgcY;mlbB7hK^u9TWXwd-fm4rJkRr_{VQ*UN8e6o%1&b%X)KQ3$6YCi
zw+(XRTwg)gi(7E8W
zpl{lznFCP^-)6u8@am#CZHRh8cvgI}a5G{d__g5v9fTMazA?5f5@6*xyV?eQQ-Xvd
zRMoj2jOLv@{wB@dllkA6t&E=g}$Y0RQb0Fu0mo3%wzo!KE9P!CQkytGDzV4e
z&X9K4JzEjq^17(k*os#p2|A(UosjN!h6v?_G0WaYyz}8ygF_AR{?C`q9FT7;GSVoN
zqiXcFy$gmbV%&E;@vIx=K&Y|{EU1guAxKx@aB-^l20t>5B@m$;P2fKh5MmE
zO-TRd%a=a1f5kHLP>ndoQ=mF;%um5vHF?4ld|d66e#@Xt=oAxxV
zaZIPksF!438WgL9wDex|w!8&3xC=ZbDk_6~xC&;{j7DYvd`5`6H$?Y?JhPI=dxbkI
z=?NCpg(Q(O!wi(V6o&hFSZC<6mHb}jJ>sNcD|&f1M$*|YQYzu}zvFz>s{A_w@h&Ar
z{t_wQf1_B??ZM|f`EZ4|IAi%O*xOLtgds*54}}i2d?gRxh`&&@v=4CiyW|O^
zwM{8hzWAL!ng4#k(`M(Gq@K3DuR}Q>d7j!&F*qGOESi~5#W~DkP97E7
zY+lH>@u25taSl)L-`ehPBmX_j(?ahZa#_?%9zTPH`-K`-VU)u?KZ)Ooe2p;gw+qp_
zL?}dfegqU2^|Zl5Aq}rxS!Bi6K6lReH;p%|`g2;PPk(Umqb_Z=oEBOx6~-Fr`M2=x
zn#A|?py#siZG4pf)_N|}SZ94i{b=8ooT>iYi5HpBa?+g7#hTBEW4t7MTZL5`>iJ%5
zX*B=)2+sw+B}>nUXY6tCqvC#i*NYE7Y!FAEtmEl;dJ@(xDNMV(bg6=97kU**!DL?|LETqJ@r0Cv3v8H;*nWFfsb5A^7KfgQH
zR3iA6AYMBb%O!zUXrpc+8eL(5IWm#K>33APeQ3jQc0?$A%#jLKz&*=Qr&7xBaWRJ8
z;`3L$O8P6hk8~Xo?ju_K;x5w6z>OrU;&0~2TCHUf>9+*E!!2;lim-4)Y)2Q#K5!=y
za!A{?eWGxJ;v^JvRep@GUCIP`&w46btL6E$(BAC{XT8vpa69p)>2`7}%zYtn8)`}d
z(&^4YbmI2Q7%fB!fweiN-ma9wE3bSu7J8%1ft~k)XU81|dWKcQ3^B{CxWil`ZfG#L
zjx2bWi%~7;i^j&^c(k#clv)=lrI+3b>ml45dsagD_O1YZRcYGA`&E^uyxBo?OM|#%
zh|0oiYA^@7bAb->JZ=@wAM$iLMJ%Dgm&pH;u7=ms2xr@Q=tPQA9=b2UJ|j~n;9T{2
zoOjVw6LQ}8tI*U4Ehmy*PdIze0pCWbF+IrF7U>244%o&U7Oz9oaPpUTu>JoneryO>4H{Zz(Y
zKPY}CU=qng`+E^07GL~6sIe;fPvsGFCH9&SW@fH3?
zmRm=~H(HyAmRnEi8qLi^ee}Z2n>ckMD5c`+g01LF*Po40FyMu++n3*9W+!xpe9uvw
zmE;;fgS+mTYXWSXQi4tJL_1>1Ku436&BLa%A7JC}h0PDRV+t^Fh%kX2frux61Q7uq
z);r*#I?cnQ4BUxk)qR;lU9+VBrL4^iQN$pSJSw2(2{`JkAL4
z=nV@2PY4z`=|ntvpv(&kFMj-AVBz>rSY*{@dSQ{a)1B3_@@`mk)fV9ob0%bfs1d!ZMoK6_YSx_
z1v7eftUM?1j4}SL%n*`DgVV--pqN0A67Z+pL^_X1W)lIK4bEMPgjDW#&uGF8Zc$WnJ84=m3voLf(Xaz~9p^%b9O@DUs9<
zvVitXl6LbEEJ^l6b*oWtWfDe7b~-4pYvEf;ipP5aLJy&{uS3=rH@OwIS&*ocluESp
zY^9S_V-}=MS*n^giY1EvCybY*-(r9nIkkGZp!&V#OQY0#^*`d*ojcaLHAyqt`rO1yNBKY6gTyY-_zG9`8x
zWJ>(bvRFtzSBupyo24A)m*VC4Wr#&oG!yT4g3m=Z=55&y*Kv$bPxO?2;wZPXW?ABkq##Y$5U%UG1-_?`d!`K57
zW_1D^IYnNs+^n-0ZEr1)CtcJ75+^KUc$>noPDEeDe4itWhKMSG`o!Wq6l@+|Pq1Y1
zl1C}gAi>%J^W|w!kL?5d0PG&ph`+9W$*%Yy@D%3SGC}!(G6g$|&o?Z0XVpO_P>||a
zPFy|rGTESzq(nRXT8cX;W}KM6oVP*I+55Xw8bf2A`cQYunrJt=XIGq^G!d8xkit%eW*-1C(hOKSDX)j
zCK;i*1o&Wu&Vrw_>#u^{%_vE~FR{MSLT+=qFyj~e+$moMls9~+OSGQqHQ(^^u~leq
zB+c0T>{jEBwJJ*~=KSTNtwxi6#w-neLj1@1FqQN05#v^r^}Ph*WydcZH#+;~p2z3tD$6xV5;Wc1|ZZ
zU5or5J9nnbU^M;JGluX{1$={4tZvK!ry}UK3V7%EGo&1O6Nkn6wRerFQdw_xX^ZnD
zJZ;a%s^|Y$X3vqFQ{fCRFlG)IQ$w0)wlqLqV52>>jDI(DB~u>123d
zFwuYG*o}W-5MgyWC)u4avG4$Qt&r@ipo>)}NFX(5O+`0cxM1JjxZ`H*tT7nBJ3T@WBBf8E?o<&B=86n<96q*
z6uZ1g8lM23%?FZ+y8G+RC5asTNGdz;p}3f2!C&riO1>+M%Gd6=CGRPXn?>EYZ~4-F
zD!Wv++we&l$Jo^})L9@QX(Z}Ye2=$Og<6B@C8fIi>&&HzoQhgTOhwGCa`oeOA5fW}
zXEEj1<}tTX{xgnx8JrN6PknSjADGDT?V`={zo$c*(Ez_AYE|P0e$y9Y*X<}E9%x*x
zxkQl?3vD&odD_+0Oe}QU*C7!mJvmOE;#(;@Y+^lWwjqGpui3G72W$jnun~~yV($ee
zMJQ813&!!~UXoXQBUoQ(eoaAd(sLH->76glDCO-*CH6$Npwv@T#SF;FegJIw5&G0y
zsHbNtRvUNZ@;%AX6WMq~%2OZ%9cRygUDWK^1&abG?NBS7$&*$@x{z9CGieoTB_A|f2Y!O*VHox#xCr-!qdQ5n*TTd?c1#i}g6NC0Gecl|;LF?Yj{BZtDa~UC
z$&OnK!#F1_gNdhJd4kHDBc%KqQ=Lr2Z#AOkYi2J_fuE=Vk2MZEQF9|@uP#FW`%x*M
z&Yzn%<6m?0$L3{z^8YOxxNy`az$AQ;J1b=tZnM89C*WzNEW)X{Q%*qVDgSEBopOS#
z;%V4vOLa@>UN6Xdc}eI9;rESNrZ+9h59$Kn5#$Ge
zcrV!jzWzgUz(&-9uZ4b#!@E~Jf4c(jcTQyHK<`(JeU~^GcmWPH6L<5g_+C4hf8C}6
zC;#xP;35@rugm~t<**$N6kfWCE<%a0tB@p+(T}>Drn#H=(x7SfwYR~Scxl>9(6n@(rk%5RYY8;%==bKx
z|3cHEyfkfxjcD4(=Ya(xO#?mqJIVe*)A+I6P1D?GaI@>CG`~U9G`CWs?xJZQpN#57
z(};UuK^K36rhy(3O*_TYw8ugFdwTj!npS+Zo2DJ(XZ(GF_p!_&0;8v5K#)6V4zC!S%DOuCGxX&1QdMiX-bJMb`Let>A2ncD54F!{}W
zw&9PbFk71YXy4}eR)3$uSk&IOH9p%RleuxrT~_!#QJFuaFm?NR+mROR^W=kneEKuY
z-ET5bB5-->@xD_2y}pT&wMmnC(OJ0P^@1TlkwJU-Ug-rY{y7m|7UQv
zuY%`dB-0;uC}^dKw1qfztX+lOTEL}A8Q}(Z#rdyT=mMR*E)Zwe2=dI!Q3@v(JV%yZ
zfcCjc3$J9NC3OGvYVItObGX-gEmk5B>lv1Mo>iUeNXj1Ri`cT7<6)qXVV}bn5wGIV
z7h3Ao!hf|^$sv6r>`+!Fl{ZI9R@QCO#m$~>tbEJ1H+S*bbt6xpbw7;U2Ru>-`hfS#
zah#uI$wG37nB}A?*ABVl3n|1v@O%RW8Ntg*J?C|(W?tdTkVUYL_+QBDx)pDN#vQh~
zn!-lvaRS%D>)O%ebA8>EO(1obzLQGIz+EU}ea
zRw(>}^-l#9lW3qlUoJo$(R)`Hw%?kw=`o
z=`k6z!%DlDuSt+cnI7oZ;}pM6z+(CB!3M
zsb5?>)?O|7S4~GkdjWhC#+7@>POPH_@+x(#TyoPc=OtXQp@Mz3yo-xzKghHS_%ifH
zNRjvaI2M;Ev=mpnGErz_Wi3{XUKB*#cB+%!P7*%UiJK~xJ+gADSoR3Ue0SO5eA#K_
z=c<;BKDKfil|5VV+%YzyO0B|;DdsZlis2J`2(hfILN@Dm8p|eq^7y_d<5yR%jyG3k
z10D}-*3tVcKN?#m-FW=wlgIS*QVT@{7h!gUqG2PRTpVGnZI3KYmbzqV^iYO*Xqo(c
z*x88Fi6@>f4dIUM8Vyx6BA88+F-
zoWbe3q~VM%*3kl=Ur%7`TW2b?B~qWwv(+Bk?S|?FmZG(
z{*b0(E$i;bD{Tt8djN(lkTCk<%{qm-G)Gzak{!MjSlgY#_b@}|+|S>lFT9MWFgL`X
zrL#o)-VFuzBVGrlo0-&K28}sd;L~((7SiGwjkJ7)LTqIr;hrI-%o2#tDuq&Vw59=7xyX&iVB(|+SB6o
zLEhFJQfP*sVF_8mxDg>H=1{ZRcN%V+=3G#y
zxYjOZBo}A#ZL}Z!6(`+4WqS3P4rr8WE5)1GKLrfWD?X{0Fm&flW^hmUVe6Z_?A(ix
z5_o*f@Q9Vk?Jq&UBFBCTgs%birZ&Wbcf0b!wptP`GO2rM%JYqV*LRQ%FnJOn!X|%p
zD{0a6Q_~aYd^RU)?wfNJPu-fdX!5DaiBmqCGAwm<7LE43?$I_*x^P2ce0TqE+3U`&
zBRk!h#{`?*nc&5NNVK>#itGjJ>`CXm%i26a)2zc-U?QOE%
zC5fTa5B{a%zJ~qoQr-OI$+Cr+b7?)3564PjS=Eo$G(dry9%Emd!(61@TigjeQUW&u
z6f%R&F^e@fxER8Y*Cs)$5=T-dDiOdyKIvm~IrNY+`nyw7UJ=@|hai?4JXJ0hg2on~
zMH}vv;+Nqiqp%pu9m^##vJOz-2+8*j<%R}b=e<$+jTWHQX9
zQ+S+vqq!Y28>@t5J7YIPI>o47?g%Wg*xsCp5h7lb$VrFi(5Y2UlzQVW#t{pC(i-`;
z@{A)4Z)Q!iNWU{SI&QSM>yB>fUQ7Svum0HPjo$4RI8*)R^>{xntcuP~oFO6R_j9HD
z5l_kTrn?Q#!Iz!hcBeJ6dPq8*#?6ef=c@KOX!~v
zbK4~$OU2NH@8$HGt1>oycsXK=j^~0BW)vd&yMA#Y*&zb19m?2A=k6=ZtT8`F{_F72c{Q9A%y{}J$lCMtN?;F1wmN%=j$or;w;n)p++20srN=q5#
zhUW2uWe)HH=F;ZBDG?Eeoq?F_k67aVxNPK7Z&`XrZgrN-KoOt>3(my5tTzR?fbOq^
z*27_B;%%Qp_s|)tYA|Azh>`-HpkRQN68DQ1+%}wQX*rypX5rJR~bP?AJm%TI(eqL>>>}n?>7W9QhwLFXJb#|RB%nVUETzo4menTsWmBND3
zI~9;-4z$m*LiUMWgqPz<*MT)?p}mK4p#7k|{^*@>+@E3?AYH+0M8b&nO8ti!hE1d~
zcFzJdIeB`)M52tqmS5>*cGmkHr5F7EQ4D@>MrW|yftb1&J@Ek;
zHE6qgDJ)6kBRNxml(da0nsD~LDn;f1p$*Gup$)`G#ruCLGLyfbe45219VsyllFIQC
zu)@4u3QkOl^DgzrmZb5%k?mA|zJ>SCzQ`CkO4PFwXE17sBKpsVH
z=pC(L_autfAhalZ*pRv;rDZwomlLx@xIIkqcuq8&cua_kbK=Vrk0VEZ;^>l;qzp-4
zdIyr;fSgt(KO)oHrLA4+fkgk;E_2L*ls3=rp+_f57-dZkV^gn%jD9L;x%M5`ZM^xm
ztTA{rhBDtZm#Q*Hp{W9XAgz~g1
zpLdNh2~|F(Gfss}{!OrQG;R|^aI3&=LKUKCV&qjixtw?zyS4JN$};#Db3JYe4IHz3
zqxQ81W`sl8;26^w(t6u&jsMx6EBS?OXlC-b7>&uk_|6FaCxJpahClT4MNTELEzu#_~}nN7tZ2GTPlld
zJllk5Q2&tip24Hwl_Y&<9++F3<}UY)AGm$;%IlFbbYhSrFku4JZF^{jc~G-bk@
zVT1Cg);zpkekAc=rIBE|BhU1eHKcM@Se|LpjecsZ0Bi`R5cJKi<|JE!BkZH2X0?)G
z9SSCK%@K<*O2hq_-{Y+7-II1MT5eK!XqJ@_IjevB*L~ttG7SPVDvY^+h5~A&&@j_`)wet
z{=x)t{rlKw-H5l>H%nr;<4l1qz&3V$aG}Mh963a9BcA#M-j$VJ52l*~VS_RxM=F=c
z$SZULHe5VM*Z_X*5Aoq5@B!DjLS;kb=*G9&Zqt3X=N?NlSW>*?v&tFbx9Y-q=
zKPP^A>gTW(;d#^TQmpqFK7V4oJ|3Rp!~-XuU=O`}_W2rnKzkR(42U>&x96J5(;2wO
zX!@~P?ihx(`e5NL^9Dbbt?`ox_@Ede?DQQYwMCyXTBerSkrRHI)>XTK8>8-rb(ZEl
zKo-m!elQypj4&FR2JZ?!G=KWfNyn!DXS9Pv%lJ8iQtKk>)>pxBnbD!=k1+8a*s
zXx=@lDi|iQ=O2#w+SB
z7Q4u{VZAh02DzbB&S6&s(_PB8T^48hrb&)?Sqf9m&3RC&I$^W}P*$Dv`At}qP
zJY{pWg_Y+v>2l@eHEljT%-?DVvz5r>KG2s}ZSWDs`JRfPUt+Pi1$Y^7>IMzeZhq~|
zM|-jp8lQ4@pbuZunwx$2J|>v_f&&|aWF(Etm7H3(U#Jz1T4f^d+a$p|h{2ESALd$$W
za-P6PjHWb?KkWv@S2|>V&yT@vmp>Cfq$qa^2Y3{mla-Gq3iQqfdN;F&-uW~J>$`f_
zvUS4KMy#bkEiawCv)+ZjQ$5z;2ixuacGAnqjE)fCW5MMctffH-Z_+R4>-qDvA(FlG
zgb?r+*87CN7Vc+uL-tvm8ZF~0e(N;6lk!Hbg*J5n&Gk@=8nhh#WX&7&%7nEH-N@-?
zj$1kIhmGp>w|lon=jxngwRLL1i5=$W+VsFWsU%?K_U!m4^8i+_z2f#!BNnr;wZ8RXJk;a&`0LXPvXg@5ebR
zo`y~J?vx8D=3wu4_z8SJ6WgC;%Dyj~XJt#+;CChF;7SRkY8`mznS9h%sn*Fm?1f#h
zLl}rSnHRyodL&MYzKZ**%8a{h7t72m*ex@wB|eDt3B8LH9-U1RdPmgRrvsjviHM3y
zF-_|wf+bF@j2SltH1rDYr!)CiJrBNYj-2o+J2T$L9Fpq8s
z`joF~gPZ{|I4`$J9_HAPN*~ze;5N`KnE@LpdjFGd!DP9Vi_|P;A%BCo`HEehDp|>7
z8zc#=g9Eo?n#B1Kbt7EG`EY2%A#IS08C0`3DPsD@>GC;k6Bi`bCnikVJ1JuF#>w(2
zKhH}8hBeM|b&Sci7#iPhyLHlOR#zfE>_x;Ml^_=EV2L>-Ub4fn%dy+B*Rdg?+|}Tt
z4e~IV&UwpfE2f^Cc4p=&!FQs!zl4ad`DQh!T!NR%?bt6+xx^Zhu<=wbFWX=Wl8+V7
z)cyS4+QEIn|9@ZnzmfX_>-`u{J9w!Y;)Ste&~!`ZlDQ)0f}3AqUrbCc~k
zl_!@>$wnNmD6`R?!mraJ%0yl_hAU%
z&HXtB7>Ag*VGJ7*$(T2e$BG)6@-=_e5#|M~BiT;oixv}WpO1A;XH?P~tli9Zl>hrC
zGf-ZBa}5(*fatc2^Zt%5_U+Y-S#4zyrx<&IB56J>qqx82mNaOwq}VCg4I~9(JD4X5
zYVm4zu%z7Tibw1oid$TXw@CUh;|>*k&+%HP*6*Nw(1z`M*}UEdePg5!j52)9tNchq
zj12q6c*aryX-dbSbtHv3RA7dt&%AyN>PkEERH3A=N(2NgG-
z-g|SeMP_Kcr|sqnr|EdUlzm%y7fukCG=^~JYzb?%^ViI`mal2h5r){hF+^7APO0e2
zV?|I${k3va;(CdM;rGs)+{SF9WNOBKJ4S%uKzFr01G}69P5?K67i>s6;_tCoW7_4P
zIf9Mlu4W%?Q5)muWZzaWKU+8KCyAB{oQ%>~AEunz2A=QiR^UjVpL8*Oc0qF5xphNf
z%+%XHW8S`Vt`F}2!lE{S;>nuQXm8>?mv7d6`jtIkm_!vo{H4l|=P&cKPpk4Jr}$kr
ziTKP9|3WmpbL&?4ZYb;X!)ytiVYZq1VM=3rn6kkJ{*v+8r0eD`p9Oab&UoGzG*YGO
zbQtY48s!K3$%|25LvVq9cRbN~wUjt&>2i1sGB>~rtSZ+sQikq^Dp|A-qGPr^vs<|5
zMjVLBakq3?1-yuuxOqI;0*;=0#weayIo)!>Q=7*Nkz(9QOJCk#G*w%r;I_`N4mo4;
z@j#a-XPode4(7ISDnumTbl}W^{s)o|Y|y)lkAC7V`cwT@3ymNm_jSDhG0Q59B&qC$
zZ;aFq+Vi2dEJl;k;}gsIFfz^wd;WquTC?b<>}MSdm^X|jUk|92P)g2R*?+g3Fyern
ze0^lC%&r{MYprtJafEfs#Q2{h8&lzX`zm}tOHr;mrp9s?DI#zMN#YTWnd3Bwvv`DB
zZl9&*z!&xP{DuENz?0&j?@iqEuj|Pdafc-;M`$lC1MMwv(A_
zcR#Zte_sCUQu__*INTp94EYz1T$x2Z@$C=tB=i4+J#()MJ*zx_6?&r87I=2)kWk3C
z&DH7tZ1pUEaC|NOb!MZ{|FuSok(Igpv<25sAopUZ4qTudqb
z2Y$R3s#5`4X4i6mQ%*B%8YnJv!s^d$BFvV=lO6Ncw$-6JbMr-H_S~AM
z5my?wX{^7Dk#q(x26q6<3;u>JXIR{@g;r!suaia=GAd6Xe#bqVVyXi^PZC~SpCQ6;
z31LOjv{=N3Hb)v)3%QnsDacLd
zf05!2yX3y`ai_cJ@k8$7Kyi++V@zsEq?#vYy|%!f8{&g#&J3hkvt|^YXkbfSrgxDm
z_nkpeSm)D9(Ym`YoZpy+9Y}fx+DXq`c2^wz46RlG>)rot9D^~AKef7xj-qto>fh>H
zgn#O9jX{+4Bo&Q=7x%iw`z6)df_G0)BvV@X)mhqX$r&Dtq?~|N0o=%KD6zxZ_iLHa
zBx#c7C79Une0GSqYA`KHsvBc5W{W$;@{~6F`k5t3MSsro?wzN3oXKmBUXm0&+9Ku}
zp5l9vc*dgsD857i7f1iM4>zQHW*6IAh^wY~@lY)~nM6pJprfzR9oE
z$2klByzm+3^WpnyQX(%M-o93@*d#&O3DY!0#yHKA@Am=7i0UR^#z^TC=h&9PrOydp{!k
za%yOAJ?q#SRA!sj5`XImeS;ya@j
z?+j`+oR2mPe?#yWfxrIv>*Mj=ts~5$h{KsL+PO;$cRA$s{~3FDQH71yZ);@GZ~OeV
zkGszl1Nh%q;B@k=sNAT$Yi}ht2(vUy*p&l(zZdpXxz;yvTW#LRV6+=0M$`9>(X>98
zMSoj$a~P$~4x>ighY7nJ_U}CL1$kd=$g_-i!<|&7CcND@%UOfhEOK*w$qs1wMMMxE
zGNW)`!#<-^?stTI4xDm|e6i1kl5*xgA%`O1@8kCtEY-WkcwMBm8dFk++JFHtM3*?pjMeEhH`PT;aa3+aGfAJG4#7I+gXx!q3+C
zM8t>{J*2%F-6)&-5#kB9&jcmuwr>tSvC9T{Ny$pCg>i%e#`*roC`yL8#GlE_VI!mp
z+s2JPtgBvPcGXDiI4hxT3!DMikxh68d_2gmiY%!}Z^GLe7UV!vUZu1-N^wJQF^JoP
zlF$PJlE7AHDzF+;h3pEcKRH1yd1o%P4UNy)ehEQB4PS;|1c(f|xV|qQt*P
zbM@~W5dR8UHfc2@1Dt+LOZ;=01D&v+?i>)SM9k#684uK6JZ!w`OQjunXB1mUVtb<~3wyP%aM-@o2g
z=|XOg{~p#(vrM#JtI|L&4gbC1Pwkw3VX(2pL42x(RUIPSjQ
zoIi^>uI`+N%7rqef!;FLJ{5Af?wqE7;8k~UK!}pvgXzU>VN1&X^sc~Ha$D#;L@d6N
z)mg+Hm`fAZ#Bw^`dTg#Nma7O{Q7{kjw1KCWw)Kv?0FWy;KO?8FdjMH1+!bv`z&ROAf6u8~(@a*J#
zk{gyJ=@ReC_jo!fzhVNx>CDV!ythYRSWBI$7wR?zFG;$P(EC^KFV*-(XYlgdyqmXPgjm=gMHcM(a^~IQiOe>#cGv1sUqH6&Wy6SFLKxeqhX6SM<`
zW8PjVYCoF>;CoDO-J1M}1NR9?Ei*UkgqFAWcleQ<|ASZajS{^e@mn|$=fNm%30eQ|
z^yX?8xVz#ZmB<32IWUB>|p+K1wRt$l#;Yuowfvrw2sUXP&S1gM-HnY|#
ztr=oj6n31V6wN*Obd9_|u@0lqKxV&oZHVImoI|!rqXnt`SN#O3phA6RV&C_vk9PDi
zjoN<@T3VL}
z`6Y$cnJvu?BE7uRRWZbF$v*n%l|hJ)Ze_IZT@GSPtiG%(gE8mMV2J019Ry+;vfGWm
zv2qDK!eV{9m;>@<1!TK%2=A{n@V}XB9uf2heYn+-5VVNDSc75V!}*Sfq>PhftV3JH
z&EOIQ4ir7Yzt7vF1wE$ypL#SfbS7$L)|I_`3};q2X#P_8ZvKA&uT_xIWX;3tC8c8o
zPKPhkGHxGUaNs3FmQJdzxrfic5csB(s~I9Qo^Wk?O!(c<0j;uR)0b3xNm6kjZjACa
zzAr~GaKa+nPxs+bIqv9fQIA$n&^gem-Lkz4-@_jL+WXza;CpENA@6s%556O(RC>SD
zSbRs!=>8qLvFL5#CRXO}Em19VN1KPhSJL0R7Vf3bd?}1k=5Z%6a&O5dk2|_?@SN+g
zl3F^hQYaCQ5*Ju+3E53|^q2QP(heKorT2^46vQV;s*rd~grmf^K@VPs-S5(_e+g}*
zdEC0PRo)T?lrY~rxVl~?B6Gp*p3oQU-g!-pu}V9
z#{ROOA4Qo}d+FTpmIJhPbuSBFvZf`vpqBx8|F)p`z5~(;;=+4Jnd%b_xJ&jqaWt0e
zz#ZB#4ly&~69w%}EExJNOl;ZlyIc1qJu4$qjr54(ncnaQf~O-u<2S3%&y;
zRujC1+c1st{+-^@H?`n*<-+SuZY;xFhghk{8%YGS{U4l}EcW{oPI=9l!xMCXm+y@0
zFvP@jysD{u&(^age^ubPop-a2~a9alk}Az
z@u~8u0knMDq$*goo4#`~bdJ0bx{?{qe2@^83mG@s`uNv}6Sj)F*t9EdT}!IaPWTVt
zk5Yfu(b*{E$Qs?cpcElTun6)w>~jP?NZRBN=RoRwf_fN*y%!U*J7I?<&j^ci9klB{
zD}6`%en9@OOOM|8Tf+B-9l1h_+tEkMTyfmj(BE7-3+eP*lQ079l=t0jh{`=AT9jC*
z|JmLWOO`%Uj{6h8d$<2Ucj1TwMCaVPx*3yoNjlK32yi+PpgsLXvf1_oOMCiS
z`XrT_u0tH+p~_Kvha>9V3gK7Tb>Qz4pn(yfl@UTaIcR5QKSavw51t^NUb7L(R>Rt&
zZmKz48U{`}Oswz03p0zAqe>QHyi@ekRWdyb>-X(Zx%Sq6jJJ$imoy2#NZ=Fv9&W?@
zJesgCS|+MwRmk1H)tf83iSbOBJe_Fj%lbiU;TPZj>XIH^v25xQilOaj$7z`7Hv#yd#96s?swM1rV%@aEy!SKUN<57K*F
zdgb28dA7X~^T@ssHia2lrd_g)xgya@PD-{(PBL1bLy~Pi3mGjtK(dX!!f2&_l5Nrt
z7_ID6W}EB~qm{Qa&?oYGx%@UkD>vEWfOg()`^qEI`*z_TvUc1<(1mWbKxd{4`jgF&
z2M>1J`aC)Ccf?`+)6l3YOZOnE;`YVLz2Q&bm7_GkXL!+s!+Ju5a$$ol=syB>*H
zk2~Ws((T`^F)cDj=J^V%hli{6sx}X6+nYXI37b!wGjg6b>kzXo3((EJ!feZKX9V~i
z{!xTqqX@r70e+Ky6yf(k-$Vg=(f8V_^BB8SDuGr~mo(7U?+v*KLFe5NT-slRAfQIj
zLwPkpt|g>#ARs66LhjOK+%uQ+P-0&A8z5)kAr}<$l8_g(jE7wK{|<77vjn*^&>NCC
z&>17IIq_6{hF#v;wdu6Bg!92mOz>Ii49>tCO!O)f-gkrMCi^A2J5$aRdZG%%MQu7=
z^i<|@(sC|dS9E&)Q?do5Q~74y`qTMOL9Vk3_kcxC5vUAK!qnB@}4gA-L|8?}A
zY+R|e6}S3v33`f>)c
z5&XAG_PNT8^g6VqR+_D4uoYE97sCNW`#*m+*HhN`Zsu
zQYk6!Pr5|-zA472qj;v2)0tr}Xzj8rq__~|eI%5kwG-M>Sz4h3_oKVKJM={V+3m|!
z1<>>?_nhyKFTX|CGmzd-X?uQaSKsFr!jH%$p>M1a@7Gs~7m$p6j>_y=MRE{&RVN1P
z#MfGbcp-?BP4X=U@-49@zq-ir5ppv7J3}hE1Ru%K`p%GV^t9fit48Z%2f&6EZNZxl
zF|5gp$8!|iNf3RL7a#fgnFUWRtT`{ufG(f>wOB-jr56s3h(veE7ZMgf;6;`y0X8u3
z@TMq6$P0tF3?vbgC*#%GrfSLL!=M^|ki@j^k(4(*0?ErKe5vY;&S26f5(K@H3-~YI
zC#DCN-&CV)zrkp6@HMg*#f`m6<3vQ~&fsf>P8rJ}YB1Ux#i8#G`qCp>NT9Pjj8`$(@2&9H6n@
zIWH@K^*!Qg`_j5yuv-yHI%5ysczs0Td%|~iOvZMk4M_XXE^pm{xmzUuh^nCX%Ov@Z
zFB_pJ=s}vX0-j=cJ1eS+;EO$leWbY*CZ-_=_NK9qkcQu4O6NK!h+
zI|MiIJ6h6TQ5@3Z^Ad;@Fkhke%hzusqmZ2Lw#
zRqX){vGh2&s!&w>fEL}m#L0Vcb$Y;%;Cq(2}UMN4jNI2Tkz5;>*~I&dklLPyK?b5
zOWH0uMeU>-$G_Ybz(F3wYqxF?)xGqoaG#LZu*Me|ME*9J6LOgQIGl}r^gv(E%8_P{VMV;!&2
zY2m#T&=&o|a-YCbJsUT4vtBO|-sf8di*`ZlWA{jJe$eRLTY*zg9%MF7m&Ddr41uih
zCVa<=aR-mAfpiQyFr4k*lk_#BEsIV<2i8Eln%gDZSyb}6>B3DlZMdl4dC?tRJTA=%
z{=H8d_;&v08)TomTj!v=d12{ll2kclkhxTco5eaAOLQ0RM-9I=A8(Bp1YIFhy4t?H
zHPFv!+R)4hckJD|m`7R|x-UO-!O{9F+NoY8w6pzhOLQss-r3GC(+F#}aiuGNznxWQ
zg?9Fc+P&>dFrJV*XYj&Q%z#?5mcGQ#fbaQ{mxP{W&o9wcsJdk<^QtfpM9rEMfO}Gt
zFGddym8p+KDlzbFBtTsliDdy_UPd?*pAPwIT&6lqwxS@OB3V-$`2uZmNu0Ozb`zD(
z@^M01f*l#h&&m>R652APC?j&?@H=!>bjQLNq_p#+*iSpUQM|IQ9zc4a%2SGxmBl
zc2cVc-etbnNh7e6B3!1|tQRxB;6Me|QS2JL5i&n{mO|DSnx=UL6B-2Eqf?0XBkkei
zvq-)v$U7r^g>hBSaYrY;AkHz_9bNRdo^;(ZA#K6fgO+u}X+DiSXsI}I-!}Qd@!5v>
z1h=Mf4)u0?mTFcj<7aDqlk}!#MrCaEX#30=OzN9YKm%1~ytr1SHZX(U{AS%Ju1}2E
zztIoNa6%mA^;5baSxdfS*ijP)IZ
zH~&VgHJx%P_U2ji>M1xE13pSs^Y$Y@q}mk*ST@zM4tyiV=zPdotKZNsvSd#IJf9w1
zYzZ*2pK-RypBj~i-_YZRq}is5%Drp>f3GnOSbY5_l7dE;Jw>&Yhd(o#T{7l+gUM=T
zY_8xnSH5lBV!ds41vAy>?fJnB>Ic2hH!4@F*~whS8)%jQ%x_j>-_L$khhto_rUm$(
zxs_h6+u~^3?bQv>RSulUVLUU`dOFqhbIp+x;ai$FI}9-Zfsao%_K)iNV=E-GK@U44
zKgUbX;T^A@g_gKd-B5bNWZc*q@DZs62Ec#z*n^a|IhW5HTkD7gRIJ9Xv4@j=#~u;&
zBu|d53-uj)Ow@loIrjKUW^6rdB$~ksq#lE=Qg~bH9Q15if}SnvM#?cG{YpOhJ2>JN
z!Hwu}w&NGdKVYQOemCd!)2DnIh04QK>^9N}g|bAc>CHCM>&okexk&M{4b7$bAzxqI
zlt+#Q{g?XY8BmKITO-UM-Dm8CGNRN|
zOBh23KL+9%k>{1y^oA$i1mVY!KA{Jm(v%)}N>lED=hZvlIra{Cj_ro$F^mmx`we&^
zegwf&3JLmM@Wd~a{~z!~KIW2g2RxD28=iu8T!8A!v+X$&r2})aThpO6vSw_mczHIv
zi(}YrM#lWUm0{m^F{-?HB`kVpz_Nj#y>*nrqSdrByYv25G4Mb_)%Y6Na?q)0YnQ$}
z+Z#WFs5Jr!)n6dn+B@yEp6bv4_RF!>Ol-bM``h
zTc$3-i>ksnO4WG=UtjE}-K>FnzrW%CarQRgO;p+c_?=89(>6d`LJ3un(zNAe6|og6
zES40K3@w7FU`1gC#!_`x5fxo_m!&01LkQ(9KtW|G6exCA1S&+`#g>;gfbt>&MSP(c
zOBG*ISlUvx^#3_C2`#L<|L^mAc*Iixv)n#JZQwPyca>O587%I?ZI3z~2){7r3D6pO3_VlqAl?f4S?*%GXp
z{mn^f;00dfxB(HnzbkjaHd&)TVeAE~;_Fyrx;dP_wwVR1Dp#ah=~M{OZrVb)2aFSi
zJ?0s}yhgNjY8Hfo!8Oi~qgPC@t2)N2hb2NynhsAJVaN;c=Ft
zL8~xNL*s19I5CoiX}=U5>T^B%91*5lqg=tN;Nh-6q)K+NfZgRcMOAXtIdea)jN>%8ZbedKwJeylnB|a_;TV6@&(uSyD)q+i-KHL@@lJG=l>QD{n
z7)}6a#op3xw{W|zxX$hNkL%p7|3kIi=qssG2p{W|Hcvcwn&1eYxO=hMwldz2bZ*;<
zw#^T#Dbwa`I%v@5?<=fH+@E+bu_p0QBCX|a%`xhzinrgiAKjL50wW&U-=*6!PGQ8)
zs5$%JmT?v^h1Yq!iXZ=}jL%nFdq-dnV4dIHa8kNUl7HV4)g3a3OJlr<-C1Wlt?${a
z>yfSKif|hQ?nn`T!2P$qjwE8;=kJqQZ7Ao~lWIt{-2%FRCJa1ebj_J(Bg)uWL1X
z4}-6V6;Q^(&^n3eJgTk`hvM4jwq|@35%CvB{(l+Au--t8?>ZcKuFSx1Pwi--=y9JH<#ph=p7`;MQM?PGNE;CH%u9bSUm<~BnRmp
zn#e?nzVDlxT^x!f5YkRQr08*<>!g2#7Dd%oPORMi>)OgAg%b)pG?piwDxR!AL*sgj
z?h@;HP-ndgt!&IWO|yoBzp?IE3hrNBaN@DwM@&>=oj#?j<2IgwMRF)Z4`^!G)Kd@j6i
zoWcBLA-vTF6Lu^JmoO~KZKs@>KEg?0ZNt^cmFWVPkQqz2#E>0E`?*q$fO9tiR*-$`
zg62_m)Dwe{3yJaW1HpunXlOw-1Qoc?Cj@b=KVAG%z)iTnJNsdzWO}0kXZR%vrsWNa
zeLl%xYjM_JVupP$Gi}2kxNPin8q+5H;XKB)wn0-`AZk@TKxV8nmoyDtXZ0Exwu&@k
zAGy;rR2WH65{$uw^WOv$%wh)={)Y()Wxnaehm~iN2;1&lGcYegpO%5?Ucbc}^C
z(pXF5FTQ}Coiph2HM~n=`xnXX8ZBSbA9l1g*NvxW25g>9Gk|)ij#qu9I`Ta@Q+JF$
zYAIbN{vnv~f}E)MMnH#w*}dQ_=?n=Tj6d^6Y-65xBSud1c_W@~r(bhmZ?4w21(q(^
zRb+XQ>KNt@CN%yIJ>ag!$Y)*M_~a}G{PuK9fu3|gj%3$2sfw}FrGAw1#tknu_`Cvx4Oa`ij0e#V7M{;-?MpWaQD<|KcK
zB^d{CFHAJa>m*@j)W8CaFAQ-WdAl=Ixx7EE7Jr0M!ibB~1eFU?xSzUFUxhJkx9nqy
zS(x9ORD2iL5~lsXS1_&o?*BYt+Qd6?J6kem(ya!*R};Rs0N-0e`0fsTF9NU2=NXjf3kSTE%;7Qa;hr?Rv-$#3&cAp8b~J@Zc{Mf
zM0!|qrF2Dmuh2e=k+*Kv=xWk%dsWaJ-D;OMYj|r9jnZB}v6mN&1AQwMu4;njx3BTm
zcbHuYeZNcWF+YxS7>33%6Gu57{K+o8!+7f|rqqxqc8BLVa+q{iF>5g!ig0fmo~FNx
zF+ua)2Y6vKld}b^Z*{hqHj3Sp?{ABk*~kwYedT>s=($3Sp_vpkAHRGVz9sOnQE7OT
zUALL>IC-#B+lqwgTtl>U$bcSWdD}sxzY|Iqih+-mNe}S0Rh-@G;MCm7Yq7qQCr#pQ
z?`Z76iJEF%7fgsrnlzEOB_S34R%*_D4f8QEy%x4|$)cUK!0F(x_^smbL<_X76R{T#
zx8sj&?+O#3+eq;Eij!bf(;HSWAzkB^wV)vh6YrSac>dp{ABAts#SRNPLQp&`sOm_@2eck!Di4tNp+=e}7X#?vn30BAo
zm^W{4g`JZ5?$h-D>@&d~vm1lv;8p64)A|wY0e!k1N$DYef?x-)i5}6fd9SZMfE@_7
zD>}0hQAk5plNZ5F=*-l6`b{;cm_WR!AHud&Dy%MdXg&Ypgfx|SD&vq~8Od~KGL8@>
z*ad2{yzCM|Sw%1kfDtETYD<7I4iF>u=dExG
z=4U8cR!Kcz6hbi8o2dr1q`cUn1vYii3rfoVTyUf?r4Vw1>O0gs!7
zD5f{9jU$CB{K8B8o36x9qL3q@>Uq*eeHro`*zyv1n&%!7^o`VFurc+ON1RcOgBf99dc_k3z^{D)VK!QJsn
zj}Kp0d%XBM@2=%dC9u6oxWtkb&$M7n$zS1D`5m4Mp!Xk2Tvj!Cwk4E2l_pl1*GXwo
zOGwit?&i0N8vAyUAN`T;%an7k9DK3nwnMffabpL$
zx4VZqyvF{lLToV?ifM&@vz&A2jyT&$=Be>pyjn!gJ@vJ@!f{Fi{Em7*jE|?+JJQOE
znP*kQ=&gmpgt{j{LK76*+)|tlZ^D`B+c>AepM5)?^k))d6nZqkpKphhM>7C+oOS6~
zd7eFcV9j3(8!<5vK{48$R?nWT&y#k%k5BqGylo
zzEY&|+az{qj6FqX_I$APK7B^FDTt9Lde1K6^!L4cC*q?GXp1p*^)XWyA1lQZHag&5
zUuC6y4y?vnU^UjjnS@%dRPb}As61901v>?e$dzi!$gcqQ7^VcQ`TjbySIE~Y>z>}r
z=*(E56)kjztegmoS{`dM`m%CHd@5%SzF%H?suuqAz2#s%ENpNR_VQKe|HW%lmYBA?
zW~v(egYt~fNgh0HX2SkKP8V@{3`-4qhkfY8yB9)xors8A4dGkV6&ryTvJrq>R7GDy
zej^Qt-ilO8nNYaZNtUOI-aauL11A*o#@v3uD>b*bx#lnB_NsHsIUehK)NbE!XmZi>
zeBGBLsxcBcYRoyoWMAf_CJX`b~T&<3zDhS+8=4mV5v$(y0}s
zQ$7=QGFUhJw8py2)*be#pdzQ#R+A@SeWj~9tk4{nf(iM<)D+r%!j_=fRggA5Qu>Mj
zqpb^+`{_b`z2904ZrSTN_&%gZ1uv8jzk@1{`u=G5Z|0nS9;tT!Q!H&>e=ag_JEGu-
z`4l6#zhbkZP~rmdUAy1Gtvdjn^UrqwJ6yqss?#T#wjR$V(AS)yiyL#t(FAXlHaGzQZ@nK2~6shxmgw#&54?_5<*C
zJh^cuG))9}{}=ACO~-MT%N?Y-WMtr6@43c0RsvH^On8$Y0i
zGu)BP3@@c!Gc={QSJa1U~yO_uJ8G>{p~S!w14%?rK`4ta1z2lt~&
zWtLUpz4+E$IB0I)NID8|IcDf76rVfno}d__*=~D>Q}qz*_G5M(u}kVa>wDTRt>WCr
z$y)+6t{*Qw#TB0cFR)mLJL?+~!1;3P{psW{(qETom!4u2Te5k<+-2@r+eK*l@>PGn
z=0s%%=Zj0i(%myn)VYRr||ryFHW95^U1l7
zzdZic(Tg8mIvi}gGIIvb@YNh!9>Y7uBZqcDO{so7*m!a}o$`m?AHw^SDqge?e=PN`
zQlR*UIMD|x(i`%RSvU2dlD18ps64lZo|{9@P2xnan4i)6g!1)maf0%EOPt`8rk+xM
z|2>rUX6RWaPS_~PQLVr8zWQl&oHT&R_J*-49g?0HDU!vL9|>tCBajc
zd*DEff0BQnm?;KU8QXVSjp?)#xt=-(E+|;H%mW=}1aaMRTq{Go#-^rdUZ>@X0Eujj5#B%x~41Y3DTh2?l94tTe$<)|hE0?7S?7Z{`s|nR|LKowMrICGWO+I48O@Tg1ys*&o!3THhGnNj}r@hqM
z^X|2ghCf~tv1i_Ait=M8#H!F>XVmz)Qa%s6C02@7#BNyznajs~HK=V%VLu)a6VxWX
z58jn~hCo}@LiS)v8jpGaG17uJ($FJyw}MQ7`>wD$5@qi2y*(a~dqmz5@(q33(DDk?
z`!9iGa3#)o<$m4erFV$fi#My*siXlU-6Wo{kE9yl#bIt=)DN?gMn|2Q$#;Wa8y0zE
zrq&O``_Q->@3}+qes9NnJ-w%OyeHp__f&%}0kQbi8lATX8@t~V^MKu^Wi&4lA7?{1&L`9)5w$TYT#{&l4k5u%C?K|najoZ!^jP2x|8+r<=SY1G;(Mgm
zk1n#wUtQFy`TYZVE26}|f;C}Vbbz-SArVWEthOZb*8cD+!&6FUrmgjfrfp4$^1_-S
zSVdeb;)qPL5HD^TfYQY_wtCrOanjh4ep4c}R(4%?gKkKd;-;T)T98|#$tSWbsFDZcsF*8U#=1FJv-j(={>IF
zJ-H{|d)zd>Z5UsJ+@95MH7uiA2d$T6O>4$RDG=9s(Flrc&|Qow2IcfRlSOq#)N3I1
z6uh|`m>BZKUX=p%*MkBLL$1QY?siZh;!&4KCqRQR)`=q5#XnJ{LMv+#!Aqq={d+4^
z=)|Z4M1f}PQO8r#+ifCSb%3lc)sZ|6D@q#4(>INzdpE6C9z?i_#^-?Z-Xz8T~)reQ?*F;_d|
zc-6ShSnl!R$Kpd`V0qs4`VgMW1QpMf{~$aI@2D`jn(Q?gCqLFoIWSyfWTt=66PVtP
zrypykq$$a?sXpn#d(@Xnk9C=3w+=ePb(CsG+(@A;;O-=RYOh@xP2d}aPF|A)xY&PO~1Vyo01
z8V7ld35!Gc|H7!!mInK#LU5VbA#MEMvBCet#&Azq;c@VfY0Q2kofV%&`9+5U`~;EN
z$AK5*y}$HUD4StcPiD{R&+L|TW*;K~;#tgod@MLUEoWFil?iU|8#ZQG&=*nL?_=Gg
z)1KRkJzy>~^vq>Z5r+DyO7GL2j^@&49c2~IpXLmI?RMS!v;LYl?k~*n=bu44^_80O
z-k%nOO4fou&BOTTa23CQMd33|cJW-=(}y^3YveE9udjmZ<-vpIa)#3j%@r3fa)##U
zYbGYbXXsV<45f3WTru`CNPYS50;Aw@3%0>hy#^fgH8w9a2gD=GrH{sh@ketigueq=
zzg%YwmK|0x*l;q8!9%xTu*gmLGk!wz^T6>i{+0^=4S(a8+8-RlysLpTV9)T!Ud(&ZAR|12*;lIKPxEi~-Y%c6CP|%Jk`D?x6FAZoz2CT2Uu(sFb^7|`T@0rKIPGM+
zobX+Y7*+@^+!>reBm+N!^Cf5)W2WaohEm>zmmx#NOn($5L@L2qmHeNC^9!#k`6q?*
zJ6~1uKN8L#spdZs&TsvblK-J_{^~y|`6q_+$Eo>`-pKz~B|q$rL-0_HshH{G!}Oe&t^wirKKjcq{trSHI@2oE=j#w&Pnre7n0Qw5Q@*
zosF}?PFv+I*6>)J@rav$ok6qFMb_4Lm!B`wz`FUVGMymFe=gIgGts}wKGw*{zMjYK
zK=fpjE?N3`sXWgp8g$ct@ph~FdHuFNIMu9&BqlMUywi&qzM7@HWJ4Q|LS{`tJHv3(!QRCWE!$7@izVAWT^jg(
z&(=^KN5XZe@VQ>IThn>oB=P*B{@BU-^A*mx%ryQJvmwpE+{?VX?i84E(c_oWuwyGe}tx7wGEnG2apZ%?u5i@}LQ*SLUBF4TMH
zwnXzOHG0D%F6Mm(qyAojqz1OD`TLLr4)?y7M^y!7s#;Q?)e838?-eb1$ktdjqO67vhuKbry~w
z<0ScDE$cN_5Xl##*P+1gTYhok^guZk0@SAM;`2B`I}@T+j|XF_y0{k|J)z=4`&_tI
zUOLD&+G9Th9~}L$c#jX~{~EbS>@G-w*BhEq!}|N1cO{M3mBJIeUp)0h;D_3)
zf|W)DJKD3#vqXFrlH-S=_8z@qu@GYxP}ho!m+ZQyI2Ega{ZttCmkIWnE#GizZ3W^}
zN^Nh8GlL10N7UMq9}LFSF*jg)M|0GV+SWCEj}v`wAWryRfo+oA)`KU01+bk8T&lgK
z!dB`Qrz^E>6{iOi7F4OVRgVj@n7_>14QQ7I`U)3$X%$}}#UGgZfKvpIq?!6rphwF^
z!ewa}oUp05d>oi4!dXm0-+$5nPwrJt*~SSGq5fKf?8Ga=UgTOFdzf&zkLq{F9VM9G
z^I@dbHYQRV4h=B)eM6m7;;eMW7sB78DB)A<6GrdbeWT1I1uh;v`=Q};DnloSN||!;
zVc=m`s9*O7+4AS7{S(mbehW%zvdLMIw02B<;PWvB$LaUGV~YDLJm_CN{szm60}EYr
zZmFyBxppMY&w2N=Yv(DK0TxjPVY+thhr#I@*iTH?77L8Q-stS--_EhYH5}U|Q8b(pHTCWG{<`j~mj!CX>$Fn(%$ap=*OH9FVuiyNlQ(^I
ztma(R@4lS*`Lk!AKT~*Y>yaaeP98k7-#br?$fz0Q7`$Yd=Y7xUqM9PPI5NzaCuG!k
zTl88ktKhi&gq~HTFXz(q(=*fbKbtGMEYB3OW;xF}3oM4mn=>o&b~AaM7~^f$YYL8R
zl;obxO#bj4&RYa}1I=qi!ymY-q7M7$~L&#+S8;Q-g|W%
zSMhZcS8?xh_Wt@GSGj94CE0)#uk|+lmT_a87v%Gsxio&g8Fy2`w@iN7#px&a=p~4O
z+w-oc6v-?S)}SXevTWB2{CX-KcTpq1V&^b^ygsK#FN0`c@}FFI&lluXkql3f(j$36
zl2_F;`OsVX3fFV&`BfQ*9(89d-sJW^+MFqm*`Xh8HMIPOd7-07i+GDg`YXh3X1V5S
zw`TJ!%NdI;Yfn~6_L^+nxGPW0oO*KV=xMvACC^xxf3h(3P;keKNuzB}ZR=h`%Q(h;
zXb^X30(0yw)b5*=h88_H{IkG3dlO*PH2Kn;7tQj^PR@gV%{K-Pe|pGV3c_`I5n&_{#aW$*(Nta7rYUE^EEs
z7T?y#;Qp!oIiCX4qrkNg>+3UT(?>Laj@8WkeAc-S9EHbdCeiGox#bn>wB_!>?qN&z
zFEMEAv@*{7QXTRmaD=mPwgTG(=Mm?KgTWJD=@KP*tbj8PTtN~+slnwhCQ`h$(bkhz
z%IS4$g<#dm=VgP?o!%*8S+J`69}C9IkC$lGnO%03q$4||@*D4e$NS$UHoCAziE$P@
zu}M$y&IT0?b_c6gE>QFJzZ@WIaDGfgaQVZ%_>`{9o-&>d`e^X6;Er7{gmVQ?BnrV3FTMm#EU%yZbL430q{P{%
zY=LdW!Hk+T_cNKnsw*=RrCrjIqRE#Fq%`qoCeKb6(*F4jr;ndLCS_g9D%slwv(J?9
zFV6T|?9lqZUzF#s(wXwLjAq)e&9fBe84Jy|37%q<@OnG}somBa;}8Qv!6
z-piG`wA#IucF4;H-Eto5fL|?AG+D0@!*6o&e(08RFG8}_vW=CH@|fIu6*71W;(rMu
z@i(nV^)cm!1ksf6Jqr|f`9;3!K#5aK(C+gIV`n#3p5yTUljlgseXO=ai~XaYG}}i$
zCEd2+&k2lP+xC1Kw9Zk2Z)CwepIF9tN=soxw*7Szhr4o!q_Uwl{kHG2-5c
zS%pe1jZZeuw9LuziirPyumNniLn~H
z1PeRX0-IVRlOM|m1*yXsY=7AN)iOb-fDKiKOJ2UU$EIQhmL5ctChBHpWjORXNxkG=
zk;=@c`e7SU)jeYubbLbh`BTy&6Eca`fj?w#N@;nmnzXD|v?%i6t#ChC$9pNm`!lVY
zO)kXY=k=ea_o5h;pz9h#B&U%J#3cFkEEbAd#ua&@hCSaE?(Z#$h|A=a|tC-slw
zCJbFQyd5U$LP!*_lqa*m6tSN-nDdUFKxyuEMxQI0^>?>
zH=_CtR67O{&+4wEdVjv1t0>%TmY3*tvNnq8&tdIF>LUsy`A}Je{0PG6S|_YlFrrCw
zHJjxzbrJF>I#yu&Z<^T;#t&Of+F3!|yRFTbxlMnj6@8(yxXtkT9+y%Yo@yVgTfcOk
zPp$c=&vWj-=UQD^AbsIOG-~vOa;*nOVJ9d$F%mE60=NBgCEG=q@<_(D>)|U{d!6Qz
zT|%^RKVc{EdTld&J=$qhNk12G)-=<2%ibE+W(-8N{0I+_i26#x3M^miR`&CXJ=ngz
zedZJ%3-31JU50iY+Gz$=ZC{+~@JKz@${um_u*K!>0vk7O{?vj83dWKD2bWcx1d8ZL
zdZ`!`(OdL`U8RgaEEP(y$~3aOVWj->6wXr{-%E&0EDY7<5;I~Y`I*`gdjBa)O0mXO
zVDvV%M1z}n+Bd=oZjsJ-Jd)4ye(^$=;rG8`iG`o~48I?T=ln{;?>%@GLWLF0qX$%@(VCsUEhWV%tE;Q~Z6x2TKwQGkvhf)5wd+t`?ZFH{83zw%g}<
zAp0@-U>B5j`iSdNTU_z$H5tE8$UsefDwUcX4Qz$&E}x!iuuu)dE9X!B0VSoMNh((G
zKWmT1n1Vj(Y_s&z9!o0viJx+#$un;?*aMMDbW?qL787I
znziV07i3&0oUboshL>kHE!cVX(|elg3FSL6Ku
zH*CFM76o0Jn9Ln^JTl_
z$5%&F%kG8|Zo+yw`c<7T8woL|ObfZ%}})@40RFBc;g3J5+KNA0ou
z3-m?DGh-F0Z8uhuu;p(Q{|=UxZN_)-uHC#|&MH9+0M&{cQU50H@8YrcSliaxda51yO|7UAcH(LjiQ#iH
z&gqT~KAC!I*qIS$M}Kbnl1jS$55&N?q_Mr}3hE`#mEm(J$Kb+yW7;O`j*U2*agOpL
zGF;<^H?Nr09K+7M9CP!x^JVI{^%73M6XdVTG`K@8E=t&odtu8kms{F#Kk4c%xH|@M
z9D9(~b4Hv!#r5ks?kwxkTG=MaKbC30mnDD(PFgiakkaDHm_cf4Z(X|T0EcL=^l#Oe
z$wiAgy>V7VNjk7FpR5GsZ^{^z=i=bkJ!wAnp+-UeR!sv3`-|7*nv{#ZjkAvT5&uW=
zXjy`3Q`uC4kA6e1h2L_m$Y7C~Z?HDC&o9CkoaCd%CHm?zi+*VJ95p5^X#Nt9RAwnS
zjB{%4^fFIQnMJ8bu?uNhR$W=_gP)(j;cqJf$)$8NXXt(Xx&zQSYm)y?T7{Qh&<+8n
zufH^1J4CgKRdcysr(9;XyYzqM>c0-TSj=DF`=53B*Q^L+c7njano2ePDf54p%JWjL
z6MsDVKOqoTP_E^#RR7OhWlL8ChHmM=L0J)%df}y^Z~d>{Ngm2Ian8Ig|0`F+BFYsr
zd-wm$hne-a*#_O|~RkA;+f$TPE9$=nWT7W~J!iTRZ8
z#4O4aWC<_bTJ!nNHJ2&#<1gz1vsv9A71)#%|DTmQX3l0+^ZrX)N$Z
z>HkM1Os7
z6Ki21pC;vzgu>I^N4ts*x?(QP){`es6}w-{GS-lnQ&(Gs;MdSQPS5#@>eHGJR+n<`
zFfZ;{NrMbRsq~e;z&?~ulWLK}q=8jG)lpmu4=HNd#DC4~t|Yc@S%s@sQ{m6kz;;z*
zaP~(HXxEC;x)jtO$B$TD%5R25*@LCo&S>6WZPLR2A8#Yplxhz$!3vsbX<=|Amn$cL}#s&Z%m->9N?oZ0eEKWV*U%q?vtyi9Ga`_LI`OSlBB`+8Ht
z6z(C&^94-akOTjOn`^H7XXlzDvjcN~0{5P9Q_c0sYQ2b=pq~AGjUBJpl#s;@tyE#g
zU6@zYnt4kYX7ipv-_4B#b9^NiTVD7AyOV{=U(mrb`TRGD@Msi-G4x*ytw?@-X`*9ZZ5Eq+rWP4$`qXV+~TJrNm4d+uWXzz}zA&7J7
zK9xmRunW($oU{ErAK{sbI-`0JLTN1J==0h2hZaLXO*4_@U2#Q
zCY++4EpU*%pxt_q^~-~#U$sUo7g~$FEn>#eWp=BUr4&X)w7I`18h%%}-`1nxudj19
zbylT1X+FUo5>`{3LJ&g)?whSXpyD1zcODkFyLfQO8244mLgrexw6yH)G3M
zL)d!q(EkNn&I5$44b?YetA0OWYuV-h8@8$khOw3Vez5WF?{3BxIJ_VJ6C1+6RBW{G
z{eQv6`K=w;NPY)A?bkPBBjt$Ku|l8t5r0q%pO~(PaGOvKXN~_2BJMik_X!rEga;J`
zO=xL=WHGp=Y2e(ZT~r=s`bkq!F9=
z0z3}+BIxoBShnKkuz>@I;{*vY+k&)D6;6G>PmNn|kd~#K)Wj<)t*CAT9r3k*vdppmJ0x1q_*RQVKS3+yIr{@f5
zivz3t*E!2!;ASvZBi-1Xda&Fv%n_oOe5_UdRnof4>OP!kOV1S&QdSq6iJG#d+()5&
zzX+DluXds?9iH*(TpaB1p#}tRO!-Ni
zJ?E+aNH3-IM;**t`zZ4NWT86Ja%vfsYlCOWTJz^sX|GDKMRo>E1xegJ+CX>DwXpA2
z*q@1ZJX3*|9Yx#_+EKGlgrf@U&JYdQwV3)48m)SzFHfN_*=GgP#~AqS~)5cI#$VJdtKWRXTSx+?!kS3zD)SBu}g=?CAj%xbmk&>Kgm7s?=a#WoR=P;k8
z9NV6#d*Y$W`IF{Pp65fpAIrL_GkuW5;F`<|q#_$XR>ZxUP5Jt>O-w(zB_3<7xb}L-
z{4Y7W$(m~855<8~hW%kpGPvBKEHUE#Z_=K=#`f#T>tQCWr>V8GAKLws@!bkd@Fp>%
zxZebv*^luYJDtys<*XHFx0}7!dNJ7>!Gs7w2=uCMck1>R2bRye-f?r#z`AtQ)cbgB
zXg(+G1C;@FPjwPyugIe|zgX%ux;Q~Py-e=;HKY80`DBWZo+CfoTPfhIS4|yR`&^~+
z^|SGnf-Tj#FdsPhp{$Ea=XEuM9pyLHjk)^cZ+xiX^Kph+7fwh>SN=8Tg~(m7(+Nf?
zca`n?nsTgt&RO`o=J5t?I&OSDx+QF(_uobWT@gB=P`|LHL7A^Ak
zXc6*bq>WA`$kIoan{g{m5?Ymi^rJ=U13_Zap+y~s7MH&|$RT%)gw$HV3M_rH^wt&m
zPHnKR@4>+9N$r5fnK&uz6F+=T%DL>bp}4Nr8}NLY`1yo0prPHswbtKb8F-ZMfT+Q*
zwWIy@S@Kt(YI*;?tO#1;5NzKzX$Y&AK^1xcwo>gr#K*s^V5JmT3B#yjCg!?sR-N5C38!wjBOS3%!RsKJMPG>subUT^S$5D@bv!RA%FFNMAR`=gu3whF>j>
z&%&26J|FJ1OzYh53!=y;y)5dOI|1sqg)p!bJ-5lF>_!>=8+Vfgcj-Erhi^js7d2KqqxVl)vaH&@6D%ENHm+
z|BRc3k6}IvVcf)w{B_)HSoCYSp_>>Ck(n&8e7MW}
zfzueLoEr$(3F*HLprn2`+ds4I^ueVGiy)
zK}xNmlWh0`PfN9}0N>J#JBTvD{{*WZe%jP+Ba5)8Z!hMR;%#i`ZRIRe^hWHoob72y
zG8@Xvow0|BD^sDgw!;g)?(SCgtzO~RC?)!unj&c0eDQNOeO~xw2%fus1)fQ%HrU6;
zH%Gu5Nhq+QovP7~g<)IyyUwufn${V%lT!({h_Nc%SDq-v+t|=s_a{u^Mx9$yAvZBj
zW8yB8PtV8HgISZBLp{iCjU;$~2*LX^eW8@#ccDHtwJBV(?u^<4f4~3iL7kLpL%gqE
z&Dt>3sgHDq`r(HOY88^K#G5gg+^pcMUTv+qg>XwL!9b|}A8u(s{#V)`m127Ewe<4(){)x1@08~f{pGM#;Lk}@jt
zcRuWt7TR+z9@g4zlh|oVzEG>Ri`Y>jhD5^llVT8qetrWk4D|Dn7L6d4YBwq{Utp%V
zo!|}jVYdX2AcAYkzdYvGY2k5S#~#^1uWqG<)t}!?3pE;r78bdF3@+an{oiO|^sZl{
zg(MlJ93hziqv))GrYp5(80-QsXrTdsUf0xpH8U9y|ENbb`f-|(JWg7tdjy&>bl#D8
z@TDX+u@R?9A8#8`0eMYeX+$WA=-w
z&+hA{JF2hGZrt$m>=PUHs+^{*B}RS1*+W
zEcR<)yODRrh@2)Ides~vQE$niM%KP0dpJT==ItPON%{x=A
z%6U#%gJ;nJpZ~xCuPc3|+@*>6%C>Crx^f1-6N#byrH}IyC!(%YV1Ky9BZ2qCKlI)f$}su*M)D&N%hGKs-TD#9KNR95QoM
zaWYv&Z<$TsgF`lDsLz@A8-#o}7fTPmM7&*jW5NL(87_vpA1d(;KQ*jWM)bY)5)SPee@$r{`6kdgN?Q
ze7*OgjXn4JsZY+<;#3EBC#DM*+ULhTvvj|ZE-YZ*7JZESQGF3VyhgXUd|Rp3S@zFx
z*+Mq$rn2k;mHi53*@AG{FHqKnvatLDMO7mo;7sMJ+NXv+IK__eLKmX=`0|0GT4?-f
zt_-Y}9fDTY=(N--X6if3KQyiZ9#XbeoceId@k7U_j`o6k*W>n8Z!vBOS~hh*PPH_0
zgAca=;Qmf{K89CLWHc-MG)1UP*d(GUWYo}S#RUa0eiw=hiTKNSnZ~g
z!!*CXS7Gb_R_`&MJ*XWvmitBWK1O_?2*bQqUY6aOP0%Vs61j+73R;}=mq>pX(m!MW
zK-=G>ko|CDdmv4llzC*8X|tP|wytCQtb%nPU`ltfnBHR$e-dMIGv)B%%h@rUmF`--
ztKsYzilTK_pcsAk7N%_F{XMxz|L0>ozMLLA8#?k9C-n(Z-t;bgK0J&21dQ4~4HTJ)
zVr5Z!{|HX`?n>akS~x4wC)%9|_ktDlM4ihUPWhMnsg*^?*FMtv
z3Vi!_+tZ?a3(?FOo>tHaxp+Ch-`2Fyq7AF=WMVh>gc
zv|@j58K6e$89gQO@s*Ejp13k@<^v}m7(IT1lO*riF;#llg7T|jK?ZMx*{~6IiNAy)
zaIy8C3P6Cm*bfKn(!qAv#4T!wk*Bw4A|=_`0MEg|hK6Ru!V&geBzjQ{$*YS^FCI
z?Bacu@hCsjiSl!wYt7uvk6Xp~?9J_J51#4cghz>cob!SCQ+Yr={x~lI>f2t$N!PdS
z?|nB=+UoKYUrMn1i!}y!L%Wym1eRpEHYyPN9ekA+Ga+|9_LAjhZ$11Ig~>5EF=;Xk
zk7x0=O->V^%msI7Uc&j;HLtkbY{2AgdgKWre;nmleVK)NX7_N!Qe=F8>wRwd}tdD^49mh+P@GXhv
zlLk@sFzZO$h82f5(!lV_%ro(=>^WaN$|bQ_l-nfDskB?-*y)39J-p3VqYEqnx%Mib
z=1cD9U
ztFVdZRM^TsC)jSqB;Z*Qh!!rX@R&FO@Hp9Wr5`G(9B640$>*_t
zzBZ4++r>+(fO2BQP4=8ToX*H|o8TEu{Ef*_d*f?fKgB-&xIL#o-~1=944Yh{E?BY1(?0_D&%v>sJHp
zWsyv$-CC@~UF;vpQeczw?G2lN@R@!5oRg;tzuffs)^kVB9y@d9XPIE~doF*fdGV;Lf7fp@XilU;sCY6epKHfMe76_ajBt-Lz)2d{YVEvZlb
z`~C}F(Q->_`{jP9VbU$B8ydT!hNo^x9Tkkbz-4)(UdEhxipdjNVXc-V+ze6s_nV|N
zhs$h=SXZ_8j1>
zIHQKJw#z0+DTRN)JpvPsP56lT(m@WPewWSbibrqMFBwQ*@YNs(_pQObjw{Hv`{S8>
z^e4>~sluI}X^I)a*%S5|5}kZffx!+4_<@|kK5$=meo#So`=HG3_n;@eyTd~hUOaPr
zs9RijJ+f2Xm7mME2{DxZ9-<6&v^nZC`3|8Qr60Z?-zmNFQ@OjEKCu0!{AcG7xvq}ux1lJj|vx#xF}x5E?Y;B`+j7I{5CrNf-`E)-a!uQZc~g7y4vx(
z`^-7Bzq5DAxvE`@<%L2_xjVVqJ_)0_D$PwRU~6G^VV8)f*@QzAAOnx`(^#q_8U8|d
z(NtC|W4ZWE#*I_PQuLo~O{STsz07+fGr1YCUS5nI-&9}KP^^j9
zZb^NzayZsRIq=XqZ~NYU^&O=j1~ljY)#uxj3MM+|TkuZ-t1k*VqRy#(-#0|Pris5G
z=r{TXId=L~{Je*|V@Ii2f6HfSnUI}m+hvo*EFSx+&>FEYM_G@{-E5CJ#iGl)GG*rDDb6*@9Ti^P
z#~O3YWZ-}(3)Pnqu5ZV{dfHc%x)vkOqZD|f;U}Us87JbUJ|*<4t5Sm6&p3g-{w>N|
z?#OHZ3k`>8oi=}?NiDUqy*jN$}JMnlmbiJ-a(7Je~f4x?A+xXR``CQL1c~cqHow}
z7wma=%y?w>j*qq8SFc4QHpuT=5JBczbVyIJ+T$0k3th3;p}dc7fxOVHoLnLn2&4z2
zk#?NCmGH;N2lpQ>zuv$&X#{pE@RU4<*agkk*Ga`X>{x|0AL((Q$YWzXHO*V+op0-z
z`83XmM|rmDMiy8j$IS0_&xF8%J-<}APBXH})nnhHI2{!(KVK2i!q7qq_QO$fa~TtK
zo@Cv~!(3z^ZsAT^VVeSwXxM>Gr8&lX*O(2
z33IX45mv6+N$(BH`(gU7ykATkTF0UU
zvVwL*Sh|MlO{Tm_R2#w6wO+_o>*`w`s>=~9d2w{2(=#cqSG?_*Ggz`RCDA$G7tXh#
zjPebF9yVBVWt54nf|XE54~3ZFmHcFZ>4$E)cVYfUNv=nv8j(47qWDNWeV^f)x0R4-w-L#Y)n#L}6Ny6R}R_
z7Xb&?Jn6#7z;i9lkW>^-O&mrt3Ga7tZYdDk(%exG={r=;&`G+~lFO6gzl9ZF{gk62
ze$f>y+4)H3VXDVeURG$&u`-hWp_>RaYYZZE6S*zATQmTFYSC~wS1GXefn1&!6L_uR
zdY3Gp$PI|JUXJ@ZUD?)!}BCk;6-Pn-f0Ob6KP=7IrC0Yfdr0SO>jm
z;YAL*Yqmqr+jb+*7IwK()!wNZE#UQ4;Lhdxi({M-zfAqbzX*~Eo?rGeIGKk2A}>aM
z{i24iJ;)4>miEiA9h<0Q!-*SaR!nj8=5pTFqg|6vrF^m6wMj=5TwW5Xc^F>GDxD;a@`Ar%{=_!HmOTp^6iPW?(m`b@
z5#I~
zwvUASv9GC=Ebm)SahQ@J`aa@Jg-0yaf%yIA$iqZuGFEp`UZUvFVEhb1GWzh~A*Y3Q
zE$ld36nn@WGsY7}P0Nb!y9~bN#HheE|4&5MspgdZblR3(rQqD}Pv7HMaeNpwPW>KJ
z$~eVgYCCEqZM83hVMzoJYppZ4E$%`QLGJN^8vmi?mrVj`*hsrABPFNqu)Fk&Rp3>~~E}K;QeWq4<~v!J-M4
zjGkzhUe+W+(}x>I8rxfW>pL21J8ku5rqDeWlg!(!ntP;jm&bT9!K-t&n-F{C^Ko1J
zbV4==r~lOBSbgA%I`0*)BPu
zQxHjy=@x)81oE+9cjS`6X3mi|tGIHpBiNVc`&mg{AFLkw|Dn82jIK(yl@coJwz~rc
z5^d`5{kg6g!0Nt#zu)Woht4qPI@iPJ`dpvq&*#F7Z4Ojl?ikZ|Z9%fQ2=iTN)i>AS
zyN!RRQO4Cg{BU41&XcN|CE<2B*I%wvhJkm5lb2f`YI}xmJ}r-y$0Ebv9pCOHPNWq@
zYu7BQz6VfQuBTl>yez)Is3(kGhWw;eT|19y%T3yh2CR24&C`wV6LEi3+(EY_hzFz+
zeM&?4I?&p{H~Z>bh%6@Wp%JFpYWD9
z-W#p?{`#x8y#1bNW^v`27NB?MD>v`CS!jPbjN%)JR{8kK*QmAz-&5}`LrcIh)!3w8
zaE#85O&*OT#y3}Jd!^!_7L8>#v$J>j<)k_V9fLJY9z`y57}Yc@B+
zbI05DusZT}1_?Ej-#@w`d(G>EzprE8Ve|Zsy}h>YYyLKGaf7`{_Yu+F#2x(F7yZB?
zncMEIX`jg~{pA(m{8N|AJ})kPg+7%f
z`UIW?`=4mV-lErj&z>}lU(Y^krjF!)=LGP-Lx06T6CM2biYExGaoP2q!)MopRyNm*o4-X&$AY1-
zhq*oeq+fAmIaj~I{P;?EQM
zelrueIcDxyD|GO_F(+4*hbHPm!>q_#D(`-%PS#CG#JQG3gHTUv5Ny5bp|2(EN(;TGuF{Bdle((4P(bK!_BW_5mECSDIww^v@w!D*}2zlbSpx9$>zGz
z!UXbdihFI_Unr6jN`C`6KhO5uwsY#%>-wTkBO2-MIAimM?62c^Tn^0`*|*P*dFU`a
z`Y#k263Cv-Gm28^W=2DA(7G^+Pj`G(HG!S?YGnmh%4E*nD^$Hsc=FhokDqK{Yo);=>o8+H;U;QVHFLcgT>TBWj9@Bx&LJxrs6zCaq7^|h;-)3)ZTVZgJg
z6Z{mPo)cvq*R4(nl%5AyO%%G@aHD`>9_uL?Jw-NFq9><)9%L0n+hG<5W_FQmKY{RF
ztx%9B!RPpMv<_^Byce&AbtChR|C+$wxew1mn@K0i|EW4^@Ttj=&Ys^h^tlNh*v09B
zxTpeFh8&^J9wNB4KJ`JvM}`L#(5{%trIWYr+d6&Gb^U>J*Y#>xqX2KSULAExs5TI+
zRrGKUaTupIKY784o}B1udL3*y_Hdz~^ooUg9r`!5SEG9-z*9Y8rXmZ)9if@(=)idGtUhe%RwTMLvUGphBw4w>{+E18gcRbsNDy`6ZCTzFJ
z$(6eCI^N@=XQ+J!+GEcQF%ySMAM5On<$Xe#{VM$RQ6haWv7_FPQX|p#V*6wGZZXjJ
zLObgHC~1N8-DO{i-^)YjyM{YF8IBh!Y3X&hpOMa)Zq&XAcZz~VydQ=HF%Qp^a3WWDjI`d^(m1rE7aPp8@~3-RteC7`VE
zjZaC|{>P`VGfIdInG5bDZ99pm7_=HQ7gXfmWAK-6yeZVz$A{D{|3hErSYPMRm)_Tx
z{-UVxAoh(cuf!h+OLi&eH;eWdVK)1m
zAuLm#+U!;g0iXQUX`w}tO&py5LGnvel&u9!(7u^NgsKV!|CP4L@U*OS0VuYwS70Xo%Gh|mb=$V
zQsE(LP4n3H7hkIiU#owkReA9$_u5fH`ytI<2f7EJo}SBRS4R>3(+V6;Wz55*%kOel
zxpc23-B{HBy81_WgX5D02cmkg$Hte#59Ie)`Zwcyz`AhC(@~?(3)CKae}h^>@_YjQ
z>256gU*4H;UO*267z5s(;fz15Lzd~Qox+Y+unr@%Rr(C*4|iND#jI{^AuhS|6jmCL
za}-Z#r2*Ui0-SKW*X9bv>^BbEr(S1J$*5RiT
z)_=af{g}7B!j`x(u!&Zb2wWPpGLVJATT^^j_lHE~;4|)XF7oKdJfRxT38NMtPFK=F?>Qq%jsH`#UK-(Ik2`@Pw&8j8P9urIec3qwV}J@s26HAePOSDdm_EH
zvC+!nL8FiPV{a3LN3qlEd#2hR^;zdG|HE6f%reqWYb6Tw{ud&+1hqfnCl(#N*H!D9yvc7@OuGDGZHCw>1JhQ4UG(uC@UJxOwQX&-Xz^6f#vP5Iew#iDn7nXh+@2$H7f=i;sWVFPbTeZva2
z_!YDWAZu*+OX}z|0q(rEU#cVN
zv-An|&NH~JV(}yD9rPLgGd#yxtvNjNBJ?GBB;@O@P4_Vq|P9owW0#Eb$qQg@-pu^Hpp8ve$G&g=KJY?
zpSQB2-l}dcwHlm3v@iSk_V)dlk@g>xOK^+R1M}okh5;F3LCGEi?`e;S@$5rmNp+!S
zRz0KsuhXo+qMj<@26EX+_J`kK4pFzn6^$#P0pt{Wx;J0GpqksVj{_^|#BrH>`6qK)
zoXJf>%EvPUbrZa6#Rzd@}~}V>sS28MZb*hn0=jndH=f4W;NWoXL8ds#@r?GEZTjh@NU0
zW1)8Zt@oOqV>$+tI5$lsZ+UKy0rM^DiT2qUvgu}9Asf8ROLy6lyg^UIDkZyPj&f7o
zt7N~tSgr1aJg1wWMkx2HcjDhD<)`W$_-9n^S4S)Nqjlj87DKGQ(fJDOmbuW25bZgJ
z=|z-ZX@p)Bd7EBD_yT=1mqweZ7~z3ZvQ5g`v~33yGuJ7fw9Hht;?`=V$fT6sz3s0v
z72-gi;UrZx4F3lIUmSt@>3^LmLGrV|?=eZaKhq_bCCh;a*4`(=+oazLO(g$kF5C^!
zgIKazE$SV+Z+3*#sMYs`JaIf+J?j1Aq
zg-q{j5!B+&kZ8YJR-gmBzVCR)!HR&Uu`%53K^LZX31
zP#q4tiO;48j#Zxi{D$oD$0^3#;LES^L_XN^WTH7&y+bG9ZqsCat7_2cA3OnTw(c2J
z4?sSkzFY5t2CZ~KUxl`dUt}F@|NArGt5bUPlqX9$(L_o7_q>xwidHPfT>8KfA{nc5
zHL4#`zB(EdkRn;f^aXj#Z+0S%M~JoYo7I{(!UL2&4f@S)*ux#$I-yhRCO8+`!^2mC
zRs@!97wv(}19IQVN_oFfk)s;+BQhj5CAhhaa>~mue9`fG(k&71gN~2x6U2qNWQX_z
zY{h@0IO0=Z4fQDz%;49_wx+Kt-+6(LRTVz3Ubcr{rYG`C4%qSeckLx_`O?py!VShG
zCB?re9-b+F@UbYeA^3mb0BU|E1m<1NxgFJL(ol%GH23Ai?q5U~h3fvbX=`Pwa
zv?H+mE{JSb6-hrR(=KCvGqE{dJWq8nhT|@PP7k8#LSdUH&%q9R$FS>^PXj6nJMHeW
zuOI`XdKlT|)|bDG%9i98ByM=4?(Wryw+lu5oe}YOM#SG45qlS^#(arcj;h2$Ua1zb8xv3ut{cyoBED(^E@XHdf{*pSALD%4eS)
zL{GdZKT9xC3oqehq-;;NuJ-(YV|{i7HjEw-CV
zR^S$>D57|<8Q#%15;3i#*sY}@oX5N9c^4|c;BD2^hn|)rgIm{0I=W_ahi3|#3?pGn
zLKH2i8TG2(**CI|K6fZ1b$|@NMxzHIl}*
zn|!kbZCos~`2gxu?GD`ENR=oYh_rV*#Dp4-#@yNR0Xa#h0^?QK+
z14kctgd~98&Dsk3i*op#wiwtY7YNa?q_{`tGrQz?=fcffVS}NSvAr7GXA{u|(&{0?
zrT@Y+hVQ2Shng)}_70>4C=`VWo!IDk*ZT6F7Z+2E03SVB!ZqRxOlwK}63
zLlGAn>I4-)Tx=-fVvUH4HHLw9(;OTBLUvNztTeiR)b02#1K)Qoast=YFg%kN=pd&k
zM2C>a@Nb83nf$eiW7uW=_PH+D0V&3at!78nNJQs&Jg}`1-gYwl#k-;EYn`K3+ts4Z
zk*))xrwzWn{_xcY+)A2$CH_y<&pR+4*&c*HwCYWO9^Kp@rZB|S;_I_uOrojv)$RBI@5(@Dnl*Km5l%x&$Z3qVVE@18p~`Fw+T
z_>$hCz&>PmjOY*2C6~P6EkAL?$DzOxkfV7gaVWh_^e_$+)@Pt~iD&HLIaZ8ao->0#
zp@<;Hf3QE^t|{-8F2*RH(u6k;RmwTS_-xgXBkW1iB?ULLx(DTRzwY?S7D#h%-*~|o
zl)yOxNhv9sehFDR_$XE3E9-gxi0)w=>T;-qqI=l)jFH~*DPOOtCp?C(k_`$dF>eLz
z{bxpa>^|rVpXe0GXXd_VV6x3`oa+`fATYrXe
zIOL;MMHQ>KG!rwt6g=LYyL-&TNxJ5FVcv$5A3;WxIwH5+G;u!}(;oK(0e>Fj?_3Im
z{`*tt=B&r&Ag+})2dJSv5y0PsFq<3v)2FN9m*^B|LZSTE8wKi!9wUEtPq;UG*~8!+
zBg0paCJ`6rhGc%Dpi<}=S!Vam?`$RVx1ntSCw0dW5yx(DmFMstS1>S~w
zRHPsoP={=4;>yUp83xUX!6RcN_eG-p13Lz63))EjR5NH}6rA+U=?1R3DL;G!xWyb;9SrXLEw92W5KxSs&YYO)v!d+r^|eP)BQ6=p
zD&fu6rMmN*MnDq@0Dn=$%Hb@Y~?S_?)9f;D59UlQi4+oNBVoj#vw>1EX=
z=~l8D@F%j4>;{E$LD;*7RoU&2@?T>Gw4cj$e9At0VIn`dYhE--FaFxR1+t4}`hwm1
z{Z=0?erI~ICuF+xj{X2FSFrud-iEGukynA2@&PSZ;Jr3~3rN^rFb1-WQh#MbzqKO+
zetfL%VQy>C2CN<3kQwaV)ulA%fwn6BR6FnO@=c;r!6lth8?t$u2O$k&Ua$a`vYlxD
zZa;1@>y7fQ>+4n76%Qt|d)6VNe&KCsH4dMQ%rZcZaAsAi4wa2rh4ZeZpJ5GV
z7oMgLgZ(x&eJ!k$bjmGUzv;7Z*^hqp*(wqTY!w!=Rk+tuB$4t!qLm_t9d<>?Q(g|E
zUo!e>Ua+TOo}yK|&gDyWb5##vZAydLC8OR|nQdAw#XwE8QB>2uT&9<3N{_c@TpxK`
z)lk$O&}+gFA8o_tztEjW9E+R0;JEs{6CZdY5j!*i7`|&*K!mquziuP!=<{@mwqX&d
z0GTyEE7A4}aks46Rl62WTNDt$xlH`O678Gv;6r@D2fcs6Z~rovg4Auw-`RXNDu4H;
z&YKg~tl0u>6x(D>$Nc_DBU5EAZ_TVOXe`i(P@@a6jA~?$!1XZoRpp8|b$`lO_NH4l
z8u`0RuMWPu{vUW(fHX4jE`7^6x+3Yig=%@mf-a69FWP44=@&MiGUZ~9bt*mS+WFNG
z9q>ZjLDC$khNs!}RulNDPF%QL_u-+zz9B{F1Cis@qkrUpm}M
z35#QowL4bA2N}Fu;*ilkhu{9W9S#1SaA9s_t4t54%qY}$Pg+>VX17B*N3-Saj%fO1
zhIL)HF5a^`(Rb#X&ut7aoQysmcNF`v$p33b+eRb)UYHgU4R3u`$D|RHLpGxae%YdQF=w
zA_jq-k%lST=v~gWw1-`#!@GWkkzj*q1w}#7CoOgpL34=6f$L(9%o~|qHH_MMv6OfFKph?$M(U3G;gWPj;y25
z-T*$DR8nTI*g*YXhZVX?SA3Lc57pd56!9>RKy;ISf&Ll*pMg*ToplDcxJWcl&?->0
z9FJ(-qLbTc#`Mc2_Dhd0@-noMKOy1(adtW@Q6T5SCYpKK&{>1R9b_|hDz6fbx5Ixn
z4K-Eog>TE7J#~R*-({<{IwE@wK6tw#G3N*Kg126Y6773+V?ClL3^DxiI(66;?0&3p
z1G*o+p+2Zu)+SWqS2=t-Zu(S*m=)$0~8
zf9_wXVp!s^s
zUmtupKZztC7HKZDLxcN3jMm=59izq!qVYWE+AU`pK*h3)@8z>lUMlcZC8;@elPYsO
zlhh4ulc;}l9`Sq)H7;o;IaZ<+n{l5w=kIvG=EB*;(D9%P;S1>`@1Yy1vtA4F$@IHH
ztFu?%%}2=m4c(kpiGN&1(GB=14JX2(ec?Xc7jlwHmyoyM%@^e4F_ywZ;vRbp{0-T~
z@)(P_C!c*kCBY(^y;@SEBq6wUhAvccl*Q-=2`?NXQ(o+a
z-NRxyZ9knS+aBB!JZiT-c*dybWNFjf%PGOcpRLTHmcNYlwxB6L$?S4^X56J6h5Q;IXY6y8
z+18+UqTk+{xffL79>`uADBmR=(Qr`oKUcaWGuPT`lT)m)C1++p9_R9;G
z+_D7`tw}P*o+%%8dX|fF@+8>rJ8w}1&qmbe>K0)2!Cjro$I-agPnE|b*QRxnniCW2
z#{$9u9qQ-MuG1>#w9Icx`4~5125_jxKPG1c0|zE=+K-H`;fxDoz@p+t$u7Kd!zfAZhbAn8tNrl+atad~*&^rjUN`haF@
zG-^s)my1I&0`rb4ddv?sUXPykXJG#K^N9BOO@1ug=NfJ=vB4rxc-7$8eBRKpz5ixm
z20X1(#j}@mI-9p9>UlFN3a2LnTSc`fMs#eLDVl-^X9;s~J{ZPMc}Fz@&J1&Q7GqU4
z!b_E|-FortZv7EWMnC1xRBMB=+yrUNR!ILvF^$%kT>oyyWl&mPi6Xkm2k$Agm%v*AJU}nQE-(g_crS^S`d;Bl%ahGxlExf<
zGU>^~-kMwaTq=hB1*eDTWsZZSFw)wQ&%x+-<^=zkqJ6g+TuzcvJEcd&UW%sPo)E`R
z`h8Z%A!b)0_1PKwy(1}Uh70u%O#w_B9ZQjmLwX#V?^J#l_5R){yM}Y=$*b^*7@R}QySt9
z`sP2zzqiCSKxLYHz%LHmQ-fIM#s{2dCAKHDBiVClN4&y#3otgXN5c26gsI<$Q2IQo
zd&g_O$DN*kY|#-uPG{KooZzOaBv=?lx7=hf8DbPuVD4CVVD6ZA4;{&$&UUwg$)9AW8M~rd
zGZ_s3fpe6GUH`?p)#S;-&Agky1*Rjy166+)9eMm?s%tu}>E4$63qIO3`=HImIa!S2
z%}yK^yl{rq5h5GmKfxQ`Ed8CqNi(dyut?`Ms^iWG8Z7^L|3?jt0fmG7q*q6Pe(GZ6
z%D@;=9fyCTBt7JhAaB-cJ>ql2kwswanT9ygX(qtWTa!9_BD0YJ7T`G15l-7E)xE`q
ziaV$Zt5gP@iJkjS{?R(|+d|VU{6H3f~4f?g%o#@8MBeVdsH=Fk4U2CUKe?
zEWs19Tvr*i0J_dCuaC~8S4uIk_t)Rze9H~ljhIy0K98W3}rw|wVy{=7B)t$Moa
zl4F|P%kNj-b|5N$>r7h0!=H0Kb(duJJ#emhs$zgkOv@;@6^6
z%ZG6-Htn>-|IRdrF@nFN`?de+wRGGCpg0%CDB_~!%0XpR#OHx^`&9~{IPP4Eb_4QN`W@FT{@Mt!12P1iY2W$&f@nDLSAM?f)Mmfn^t@w!^N=Y|
zik+rS!`-;!AD@QWX3KH%Aty2}GpnO_!HX=n>N)QqSwe;+(KyooMwieJ
zZG!WP=wn0=`PfzGh!&#{NLZ*zFA-Jtc9s8<&Hsqg{*Jliq{-l)L;F0;0a$`IQ4PNp
zK_~vV(c6RkZH0Ao4~d`m4oWkg6P)w9<#L=O;(^)IVviF?rSUBenoE5n=6vSgjA_qR40I)?Xs2Mxi1EHZnKSv5%J%3#S{
zcBoR3z$wm{cN_vG#jmO;MW{hNOj<*);O?iBOmcZTpj^K6WB5Pr0_`_z*28W6^`^ys
z=z1CoJe^6-mOiuVU(Obfx%lt0y>fG>Sbx&_^`Fyc&Yj-%
znGfHq{IWo`3-Q{4xsl*vcQC${Hcg#C6$(Bl{+DQ*WYh}WomD!MTr8@?y7hEIK#!s(
zMF1;}UF%IjO;P7SZ2<4I*Tzlq)2lmA`)JktJH3mSA
zqN(GtM;FJP8)*NNBR<+ydq;wgcI8YQIu{S-a!OJS-4f_q#6JX@N7h=R*SEg0^24cAep?_mmQ~B}yx!h6wsLL+*=3EK>aR(a2DbZ;E;O)#>*(2z1uK
zTLUVUM&W})n60H^u`@O|hVDS_7Ut*Smxkgf!nY$DQQ)YtbW+FV$7yc4LGotJd*r>;
zxCL7m7?xa5UXhXknkU95#pIy69iUZHY&g$!KhpZR{ztVE2We7fA(syc;&k@a5NR}I
zkVt~~o}<{Wv5+##D?q=`5idxqRT3e!1`+)SmG)6<`-})b%unQRq8S&328lMJSm!i&
zp7<`lbk&Mo$eL&275Zv@l?-uOsDfdax8G~Y`I(ktE^yqjQ1*|k3#F0Sc;H;@Uc9tr
z>wkRYQN$05R>SwZMWk_;N3va8^G|Df9sO28eAZawKu(jKJBIo^_@DkhqyO`{1tQjw
z@QV}qyr1@$`>mD2g2?>?IdUltjM~`APSLrpps5qIT=c|5kX$-Mp6!}-6;*vQ%4|!R
zg%BEP`IPH!Ee84%H0rbsF8~VVv;IQo>g~Vt6H1;Iw;ZLXQ#x<*lGR6A36J)kCX8Yf
zoQ+xaYog#pv5|>s)($zbrnm*~rEXn7JD;K%mN0*yn32B9*t!IC*R0tI=MI#13L@~W
zI(I%QEKYB<*v|I!Kka|0_m?zK-L+?z85_Zoi-*qKjgn6)u$4dLG03xs=J
zz`bJi$8b-ybqhJrBnkg=o<0m-NH$C2!Bpj;l*11iXMR$3E^^!d?zF8Gt2J>^vfi|&
zCuGOpQDafkzH%#3GDR{?5=hgftRk;5bry6*rC(yR*zecWNWb+)T^vEbZa&L(QQ}1v
zq~T}Hi{xHhK5pjIB<+%Q=Q*JgH*u&N6|>WmDH8pO7jWJ&O4m7s(O>^t0$xhS;)2thJ&SV;1%WeZfObr-5lOc!sv)=xLFIp3Xfo
zC`o|E>S@;9!v|}|@Nqr!2@^OEhkrMs>?>e#BuTX1@`RsK)fqZz^hCBp2SWbzJ7(8W
z9^2=O>g&4oHN*W#I?4J+2G7Cl6q42;{f%=gQdFGp4C@lH^Wt8%^IgAyJZ|<&s3e*8
z{@Z1jGib~*+fxIWzS-l(j5wx$nM9brbNAR4Og~>n8iY4%|ER$^!9u9FVzs*Uv`17G
zdh-VqV~n#P6BKe@zGrpZ(Uik;JoB3u9s1%6^13|U=z~Y1pHEkBx)i{%82VE%U=o;n
zr=v_60lhC=v(M33RNX~y-!ls){Q_2i@|tmpwl6gJ+0qW)Kh?HZ3ov@qqVG=x#u8jM
z+}9%*1BMy#yhvwHwEY7&s^R%hVV{UdVYIFBQPY}lLyl-V8_igNr3RI(yRsi7`sr|C
z+@$3wLhJ21`A2yp^=euk1BvUDtd7V5H`y?q$qmM$k&AGOvi07q@vFH1CMEe#$>x;*
zN(p-8`V-{K0pChwGo|qp;K7DIM{`{^h0T@bKN)k4z+3~0AyW-%k~yAQ$P^!GreG;5
zCI8dBr{Rl8%oMSLMBC5pfv?idDYf~IC;IfLtt{kN<4S-J)pL
z=e6uTc%)&MZ!~4Re>6~(uDK;R8C;er3cb4)>msP>$IyA<8q4gTkoJLJi>8`s2E!t-
zZev$ioYrf_ek`K8Vp~yJEFHVBZnY2J?%>hj?A)K`Hb~&>t3DeNZ9p7&Ugawi`1_s4^lV4MD
zdYa51e5ECuU25KpyDD=evNv4pil4%AiVumu
z8_S;u=MgJ)lB5PfN~g-5dhF}PTmN?2mq(EPRCdTM7ctun-(})@?KnNlAt&T~HI$RC
z|J%^NZk;DvEm7aNBR=?`QVy42ou1w19Y@`o6l>09QY`%71fiWhB+G80SsJqpgL11|
zPGuA(eWo8C1dR*K9>T3?e1yz@6VE4JZ_dRn4(5tO#Mw=TRK$QX+g;K6Zw7dK>ghEY
zr+n2}8u`{ghVpi!OsmXEFliEU7h(TM(~lT@j%Qu#+1-IYseAwfGQTDa03Qd3F}rZz
zpQLV*%+!BE0PX#A@G}zc>eLbM!Y>h(jE9v!O8ZiOX((q&Wt=5(0@EabU&yfdC)XrI
zTc)TAZIc|vbNT`O;o^mhe*K|_ox+M3Ra7EYb=CKBy=e~fm2o(A{>_gW)w%niH!T-)
zE+f(};^&7{L7G(3soCQ4T!2_qmbYl>WwOtEi|YTTS!sTRi$2{kEB#Jzut})uA4t~q
zGTTJRu^i5~+AGl$x9rEl{@fFe$|ZugeDg=o*XMX47l=I({=MY5J?ks%{~6MESK@qe
zyn)?&0Jc@1lhvCfUvq9{@COV_8-DGyuLM-%I8>QL;Iyw3IaDn($;XhI=7rmuaN4+}
z%sw4Cvfi}uOD5W;8=Cb4&*RP$|IbPfb=p6GtVX{V;k`!lE}S=h)}Yg-0qe4IZp#fG
z3R{Ay55A{4=g+aa1CwOv0p;cQhF&fNL?y(WH-u?c`Yr9A(90#h-?B$Rs)Hp|(ubn%
z;R5O1L(SH(aPVIj&d12!$u1hwF2`zatl?{7bWU$i1kM!Zbo-
z_QSODarHxY?ky%GRWOT)e>b7&6TWrr{2Ngb?wR9jiEp7Z6^t|Gv~R(@$cyhbbcKxd
zOA$r04#8H%J
z0^j`>ARqqh8$6#PPN&l@MLgCaqFIc&s{-?$4A_0r_AmP!xChHp`Nd(w58w7KvMPxKTF9Dpap~)ES|KRl{-r}Dc%RM4
zn7x4YU*@ttR=49T;wz8_$(m#oAmvFBu;K%QX=iZeg`PDi)gOWn*Cm+@^H85~U#v7vsfBNX(NPI`9kBJ+{5G2CXHm3v
z3NsB|ICQ3*mhe6^%L+Vo;0=>C(juM{C~A!Q$>h)y5?+kfn$bgdD)m5`3O@}#d_xsZ
z-`mZZBE5_I5tC@-aV}1K8Lp;fdIy!YMXxbx61}%mPD4Hm1^
z(>ko7Xni}=7?{5yYMD2!cpm8q3x6PER>6Y;=-~!k^7p95-Fk0P>hjpe%Nz@fik43W
z7M_uy1wo>G4cds$PgISS7{EydWSxTg)4VMvr&Xex1PMcpaqE+uv6lFNouScpHn)MECQb2(vBpq`3`j#P;cz!gC#tdkoYOQW2{a7Z%DQ%XsSvw
zNw`NfV>0~KpW3s52t)(`?uF3zL&HqEYsXP$XX?7pP10U$IXjt0F@m87)?NJ5!Ly5Y
zC5On4OIBQOQOH01bc_3oIpsP9&i~?FH~zxg)ugxAlSKp)A!IVYk1-rjg#B|_HFWsk
zq^cyMWPx5MXoMd+B)xt}xG&Ts)3|^zG|~h_q||qEd9-o_Y|mm$B)u^pe|Bv?1^u4w
zk^M<-xu4TQk^*W^;6`KEX2JEzQUj>(uPO_tuReflW9JZl>x8uvAgM%1jf6R|D&XiG;9JxW*uc1_y
z^FJEKGOXD|Z6)OS(;9fpkQJy$aAO^Z4-P1VM{I%G4h~&>6&u
z*ZffgT_-O!-{P1_lAs?m=QjFBzKz!w-P*CTZUDEzA4tP2!T%WbPr9outy%@3|{7t^?ExdyrOiO%`bT!Uh5gEX6M!Ao4wgP6+0$ug2ylclH
z6N^kKw#5#f?|1#@8yw%Q76h`Lx?L`)zntj9L(g_{T6A1ko4$Qnc!A=E+C&i?`^)E6@n;!d=}`*~!X$$(%zPTGy-|bt`N+7K%V8
ziiijy`aP{;#pQt;y~$I}q|f_7+cpK=WjHqn{v$I{mQDNH5ziLB1F_4aCTU(d<8xa&
zk0dC1y9#nyIJ+Z3QG+ZkZyAvX
zqb3!0xS8}nlp2NXQYjJzvX!@J)h)75R04mRkJ6k-!e??vQI`C3zelSz;a=Lu&07cy
z_8%p#1P`CzyM}6`10F4*Yc^r`?cOy%=UO(H6Ps4Cz$c>!t+V^tX{2}H*9zi(t?oMJ
z)50l)NBoC5wO#d}oz^bbm9?+B_;%+HamX`@;9YPy-b(k_`EbYwhu8rvXmc^en^9#;
zZ;|(3ghO=7DCWvR5!{|7lItse{{0&M=9=689`_~55*%;yhg0rAbW?CsRTAA;GudS_
zP$oO)04F!00z0fuF-q_flES|v$**X0rx=?Q6M5L1rW>n9OEE+7NQ}*m$vE##OaF-)
zBgK3U3Cu5r`cF!x!7qoBU5Mlf+L^{f^rkmz^^?GusP4s)?G7yvIXNn1J@H}e4YI~y
zr4E2Sih0rCLBp(27d_H3>Jx(_NRhZNZE}8Xe(8J2Ny^)M!Ino<8{V{$`xr
z=KTY-z^8LwJb8jv^PdoR+^YpT^-M
zAL!TdDOOAvuWpV(}`}7G@6z^)vr%;h-Y3O&#cd3_R4}z+#2l}&*bmy&WI8#
zPQVo|y_GNxWj*43{Sk0P1AP4H8n-=>MSv_DWV>;g&Pk%@MRSRLtT!4~ML}}iMYa&`
z&r5tBr@Qr52e*WPatIA;I8JcOP=ZV|ZH();BZ4fC-rj%L;B!2K-I(M^UQhS&kDqQ?
z*2HaLd`9tCO;3_OmyfJi+D&&5Je}}6xFspx9gMh^;3h-kN!sDP8z0~JMZQUyVcwfJ
zpVh#Xu|KGv5GYMd1dap0Ec2gq+P0WYFMSvCRQtV{jZs>r%^OeslK1p2)=zETk&RDp
z{1iP&=0$lFMMeGSa6d44$(CV-Mib~vYyBB+anmoMb3FTz+DD=vougfYucb(`V$C_>
zqAkhnw9PP+w>8?Z@KvX60X(js<{vbidiCl2IP^{auf&-j)cgIhN3ep&^C^lCp3-~P
z)h*M=>td8*$N%_P7^mwNbWO7FG5-sHe!RB7IaFDEG~
zC#99!un>v=F6HdS?h68}PvfQ#$&CBK&7%SeO0P?QDn)efEl@RAjDlQMiQBp;-`$9aWM;{kZ9CdiCnw-7#v+o6t2u-z%usTkj9;)k;wOYS8{SKu;P;2SB8v3o(R<
zB6!DKDMAX8i3XQ=Oo&JJrWPluF}q`&IHg*rGd?$_u!Cbam&^dQu3OEBW18em?M_sq
zcgLKs*H-Sq%%f=L+C*gK%=!~#7_&(t&xR^NJGYNgt8-P6zQw4!v`T#QTCUy0=wk`l
z2aN;ou77Wr4`$b7*j|N%j_944ZeD)}8~qGhg$(d;DwO(Lrn0I&PPDFTBTBdF5pFA}7=w$5_
zcB5T~w^MVXYpr4J;=&}%cvO86s9D^>{4!IMdM;X;$
z^YwEI_vun!>%09eP@51w&q`Eta9`nlO`;Jcv_v*1A9?4$cx#@)%g=g#(d3T{nyZpD
zRJcO_ii#*d#D_*B%37WW3-Kvn>1)AcGsb-WPV1yqQhf@&(sXFJw@q0K+4
z>f7J9?EX2?u0#7f`@fAm`$a(Jo57JUoE{wc$6*=0+O+)Akh#{M9DIYzjtTzPb#_zdFqKh<`=$CN-Sltiit`toP%=ryS=E`oX8S
zTKrF$Umx}~oK9v>V>5|LACA?^kJ3!^G?QD0zCV-8%(G8D!uoK~-&@>~eYqs>xaHNz
zSDKa^rzKE}sPq89;#Q&kQE&%UEJl=a4l1w^)R%treY;#~JlSHDG_u7^0*xp&n=&a@
zzFk;}Gu4h?;-MqcC;9!uLGkE@19m%%0LkkU9;Zuw|LX8xzy3!0Z=Ax9egwM9{-z(zy1E3u%X@dCizfsZ{->Ps8v&gJ^ApV$aMZ-qgRK+yPn$kLa5yl
zd|9Z@cPy*Y>mUWm$lP>Lb${flMI+-z+qB<`GhT-KWZv-4b^5zifcNG4qu3KrJm$;BzTYwDcM
zTgZdZwbVmx=ek$2C*F<8EITa)aSL$=X?1+9@ndL}1Xt)!x&BopKFwAYfK^>&t5SM{
z9RKjI%C80U`hP>#^dhb4IA4?8YjD}m^EFAmuoGfU!M&1iP2&dFl>Q9ObJc0SCfIO9
z$mmiDi`{Yr_X+;Bw`Wkhao5+?53YMIygvi$g$#}L=6*=)ZN1gMgRPfV%U7B|oUn=X
zNxoYDT65+`9`|F0fhe-$q!@u^{%147=kQ
z!Yus$QXkp`zTsA4zonW4)VAZLzVH0IMi}q31qvBB8^^7*#*>#D0V_j`(7=mO)r8ZCG?$n^t#TNh
z6y1GpB~3zYkpRb~DhXKAQKf%5%)PcZWS%`I$&ucNOclNw(lDXXcFq0lU92KOawT<`
zdT-KMB0G;i?+Ub1DVOm~>b(hUm2rxIWm!_k*xqkNSdL*mHoN=#LlB2EOhjxm@*nQ#
zlW>nWMu~lcJnispr{-AvZSfQuPOiDQ6Q}3mty?)s>+1Zi#y^O+%we`Uus0Yb#4?_y
zHcPv^>zy{}>af$eWo`p7A==rEsOL9*5zmtm@m#I#-N@|#%tlk5I4n-1SWIui{3ok(
zf8HyiZ-395Kc=47|244w$F+6R)e+ZK)c(Ml`gOK2o3CD`$Vk&pkg?ll?J?)AOCh((HTfHX3Ija8pg
zya3^$nbF(IVg34juy9t40mTv>A-$+f+A2E6_DW7$8DL#zW*JXqZSa(QU>3m>W!rvF
z393MO45BSY2t>WNEATnZ5KO4q>==DTLRNuzZ=Na!no%F;1MGLhPDn!+MSM$b95zTf
zdA2Qj8skAmRE*$=xPnjCkC;*4Zzn5GD4|?A
z=d9JRq(3kutm(!p^TgRxjn+5O14|C*R5jy^0_^zPNJ_?nrayx~N
zQU$kXp^}<(ip`2FofDr%X^!w@oRtJQgDh8mIUuvzWO&yD3kNFw6dZ=c
zlePX0b1u%OW!`g<&9O}K!OSmJ>GzX&p4A?R)=A(I_C(gqrV=vlHZaR0@stfe=(PK4-UE{~PdjESR@
zWW;UiUdz;Fz&Oz%k~C2yqKcE`!#oSJG+N5cV#{*jGLs!bHkxG1LveYOpL*dspnLH`
z<@e_vm$x5#VtELp~~t7(a6aagq6vWbu{cmbUZ0j5O*jPZ8Do+c03N`ngfD;J&QA0+hBI*oi*5UI2@<<#53;;BRoqEN
zc+N2e_?>m(uN=Q8YthFhW9GQu%yP=&vg(f4TKT=GnJ-nqK3|7e5_OBB7tgUe9$gpu
zhr&A%9(~A*w5u(kap5c<;J3sRf^i~h(P#0`T-MOzs0JY%wwn5s5Zza%zAB;Fs_Rrk
z`}H|iaghY=81kr3k{YaGKs^(k*q7^vCO>OfPq!1WKt?up0`FSp-4psx)G)&tBk0XK
zar^17$o8#gRe`4zx3keX%V+28Fp~lQr%^V4b^9pYlZTFS!SmyzC@Tj>K@<$_&SBWg
z2EC*{Y62XiST8;^55-Ypw>T9Exx}eRcYNfKRb6QKQJkO?LDee!M7hv
zNpi%=0QKIbRlo+AEprOG>T|jq4w~vTx?SGsNt#y4J{L@*GXV^nR>?k>Pb2z@NQ`Nf
zWZlgg_dZ{{U+U#C34AnVi5nwRd;mO5cU2svJZm|lo$SDR;tNE%y=TeWP3Mhsk4$Bk}ELB|c%pO84Si
zLCwxZH3?*|E|zrZ*_AoDs4EeT3Kl&AzY%FLLu=P(l%qA-#pD`>yYY`zLwhYvD)5AD
zgI*Vi^a^mn9zD)$!mfvjwil0ZD;C+&Sp{jbOC;*9ONneA&=8;x4dz5`eSE$a$L>bQ
z?tVw{NvG_n#4m)GvU-j2{(D|YQVmRjr25^Uj4M!P$Hj5`#+Q@CH@8)nk^z~*C$}O}
z$MJ_YJ)%U+RPhCV8|w^`GvjwD$2U8z3(N;`W1H8g8%eSwWvB=e==N^()Uf`Qr|QFO
z{@=#ELA}4-@)&%$L;8;FLwwnCvuuOR{=FP6mY)^Uh#i9$`6S}Th1D;UKZ|Z^?AFc6
z8-@tLL>tNYka;I~6Z8q@O<}f)?U)Io*Z8VtZRdYUv9!ke4{2U+SL3OSZd#|?7qk&vB&IK)~5%YW4+n?C(x{y76~fH_VAWpdC7eeW(o4Ay#ky^6&3O&fSB1F*}^r*zptGTRH?UmO7~)cqn5{
zN>j{RfY$vjfLGcyyAu#Qkr$Uo*#S8r+=rDgAb)KxbH+EpS4>`zG0p7!jmCavO}S2M
zdArapM@g~|Iy&E8CXOhqcg7{f=m2%J%}#VYUpL$q_HJOx)%`>z=OswF~lIV8-2X8bx>^r*SfH>aHA{&UQd^3DdP?o%ZnXhXUs~JqxEeQmzlFfFF$*
zFKB^_<17XC-fUC&Xd$xTKwGD!u)wh)JkYVh6X?iOr1$b=!$*0C>r8ENmSFqUY}2;U
zxEuT#Vftbv(XGJO;uLw^r1m>#a^fy(Z|SH4?Q|6YEM
z?Rb6g`|&XaC!`!xDGHI`jSgXYW*b^cs3s?VY@ISazs-W`@;6r3y_ery@5I~hl_oMB
zi&M{dnPdoa3*!=g{lJoF2fdW0*&L|3Pa3a7>6J+0YM70zi_gPwlOq3q@-x2_r&~yo
z^%P<6O^8OO3;Q1LO;{EV4%slpXAkExlmBh+CzVdg+>Y50?0GyLDy5Juh|$K(f0HK9
zB=k*OJLu6*h6gkK=g|2`bC>82Yep5N-XPF433|J!S8%~w`$OHlL2`(&_sALF5?zFz
zeslMCIZ5ZCF>^ZP*wF?{fm^zr=yB{!EPT9ONCDS2@>%^msdb?gA`C$H-o0!Eln@flj}(O&_PNvt6|!y7Cl8Yh4O2mjCvK
z=oG&^JK%jK&Y8CKOVOSp@H1DbzXZM2jL0HH7UJ9etj;hb4l`~C1$~}@*glefli<4q
z*N&=v5^%_x`)4}sPU{v?J4Cv+%O-;xU=9}D5K%q5*7m4{vVbw0hKnO$YvJn=`eXcX;V>clo*TM1%{t`I
zRIQ9l-9Gu_6xT1fEg8N}OS-Ahj!Iy6GKmIuOtKE6N@H7$fEpL0QJ-}W@1OThy>VHd
zTd#PpRfw+QxKCOXmk9{>D~3bE8{R7%w>u2IdjC9YQ7MsV5BUI6GKWXoMUPV$KQH*HfvBbmIEcIzP5vJp*Bv&NZXZ;qlB
z;Z4YB-mH^FhdReA3_KALW(E%NGiNHZ`#SD
z^A__CV`KyK;#~9=@^#-nJHp@}u03;~Z|w>5Ru3Pv@qSaKr+A`Lh1Jkcji#H2P@9e0
zg98u4()w|nYWzw
zlIUuo-Epl-Py0x7cB4EN^0h-~?j(U%lBce<{#)L&AOC+0R#mV2`!0U^?!mshstg=Y
zdL)7w$CGzYim=OQsCC#U;dG4XlTao1D<3?6Myn(q5!!wh8RJ{nyqI4So=8v}%&8sT
zW}4S5!~k%5$Y;iT$e+o3DA&JS&wr`H4Y|~3x!zj8(sqNaVy*Sxof@d;E!s1LV!Jty
ztewbU&VVeAyQ;@ApZ{wMbXF@)>fnh`3e7G4wVs+wTx^;2WIvS@ey$kk!U{*Xs$uz^am2Eg~)-Rs{ImCTe7bX?_hZwfGO>8
zC33oPFY9M+xkv^~5?0^$Se-wX>IQtQwENJS8LZcTiWW7it|4MYrkW|FuQH1-tpFzh
zHJg7oxPo~P{@<+N1K$b`V+E?=$5x;K?*~^<-|An%yu0}d_|qG9T7jz2D%YQ2^S?s#
zKmX(NUo~X@)BbPf|NnOf>YE1UKmLb10Q)1`fu#p&1#>?gx&s{Yoeuv_46a~moJMyq
zK?CF&dj5TdAI*2Fmww3lI}07cfNu%Kk++|w`%neZUjuRe8LEWw^oeE1RvdYjTlv|Z
z+n;0-4g5YNu|V65CXRka?|4-)I_+VCm=Y^ElNSnN@*2T(e6bvB-?zz>^0@3iyhJu7
zFOeP3Rt!$BD*#f`A0&d-s<2zF6p~a`w?(bg<*KTFhFYnAQAOT^ii%d_A$J{sj#l&b!8fg>2Zky`
zYcIa`xc-T2k1Tui^rN#M(^;t!qe&?b(%Cw+&YpF);yRrzrw(&wBY|QaIE9*O7JYL)
zk7VK1&gLK6=OW(cw=4S2ldYK9e1eaF52l@LBFiG;=&14>tXh!N61o++9p@9446HQm
zLOG9m;kOfUsuibI685K!+ey*aI1BQ(l5B(gR&HG7wBmF(Bj*vEcvg`UpK^xFX2qB!
zN1nvp8j_$IdxfW%-EfGvk?nld1Ab4a*~K{@s=I|%=aV#0h-{n}qf0tONC?1IQQic<
zD`rsX?1{eJCg%4)QY*l@;y4?NtTnI|vT@??CCW?nFG#QO%U1n*WL^Ds{2-sXRizh!
z>A(?qVw`7Vz{|**h1!6rl&NDfWQ(Nv(8{LNFq;<1No1!@TUvPgoDyNNwp_8Aq=Sx?HuiX4hlr1iw1h7gw(v7TRQ
zB!!OZB`HtZ(;+4=hkxu%iTn{1yF_zewVTJ7S4y!uivHd(emHPT5?Q`L)UGICMcUHr
zN~*cmmGC&Cvk}cknYLtCOG`rr->N-U;7UT{EvIqRS%i&ntC+yEeoYDJ^
zf9JzH&b?lZR?M|^X>QmXxXV;sH_B0hXZDFPB^}XJS1GD{G@p5`)g)(O=DOvegOgp+
zs;)og`*Y_l+A~#MV9Z%WHb}Vd*`n7rtp=TkPU0e66({UdI$?ppa^hUk$9(vO8hgzi
z-$_F@81UoO{fM?F+asN^ig{xj2Rt=5vD>gK<3^YO$2Pl;JX%`kVRi!PchHhz*xJ*k
z{LN2E$=l3j6Ezz;589hhm5=Ue^hTY61?|NMs?FE^7t**szaTDZ($l>s6H@|Too=v+
zB;6wqIw5fZJ)ytK)980^!ubD4^jW6qq?iVHuw5h$kWY5?1f6aCAfEPBNpv3Mj9nUh
zhK4Me;Zy4RTXYt@X(6ABiw>i1E|q`lf$jGm|GW9K|dPgph@#?HgJOMm2c9KUb%
z{4+EFydE(ANkhsMan0OPCtFZeLfNrWtUQrRDeuOM^S%(
zGvy8;ybRPn@M_+EdvMveQIyHIa0Jc)kLGiT{P~*$7tOCsGO7~z#3Ep
z!TgARx!;3@2N-ltb7=iRCxEAKw><^BLl9Qbpm(1cEja!k&fY#Qsygi-KQm{}JTNMQ
zBO<0bFg{`mie`4ZI@Am&s1)6ld}zhShqb#_Y*W|0*A*NF8Ye^=5vg?@MJ4SnQ8d=d
zfCMHj1znYFGa*ElS{rPE5mWiSug{qQ?BRRw>-UE;Gv}Poxjs+V=X!i!U+2qDiPp}1
zwIHIx#k~@Ec2PNjM>SWzGv}R}^n{^qYR$R>T1vuT?xJXIoT9ReQ>GX=s@#YwLF&$&
z1D`rYrz>mV9)YBXh3kt?@u4y0Y$r6IjJcOCR{iT^YN{HTc73GnWi2qPibTIKC>
zM1*x_abpIMyx!LmI~krEf2@;~{{$+_+Br6B_@E#o0r^xl?P$TKPV
z7sBv1-a!QSd4CRPsPkf8m94
z@A7+Ur8p~KS+G8MF3=7pTLbBdK;y;AkO9BODr=Wp!ILE})mMZ?>~}?ei=TfV@_Wf{
z-g>qDMk!*L703z}%9nVPc3o@%w;)7AMCZlC^%v+_R3(B8zCO@iwpdbH#3XJ>*4EF>
zq$t9h>Ehk)TrkT0V!8sOQ#?(1ZapWLF}ss2Vli=jc8XLloMNJ4C%b8c5d$gZ1dz57
z;Ib5HcCnO)4i7y872#kNYDO#pxa|Q%X*7eI7Vsopa6B+oYG=JO(ZW~LHT}AdVC%n|
z;SID^`JV-f4U6c&uPt+_N($tp6sG+fZmuVrz-i)kdPD~?>6kP}|9bg|`V%lujE&
zLm4Lgacb|ghQ;FvsDHwANZ5?XuA%R!3$_Z^QRCFQtr-@ddileIy;D1D2lW~_L&c_k
z0ZuH}uhv=kdaTkVjtB3aVu>*bV*7I$aaA>f4-$hVB73r<{
z?VNG*Q8{|*KID(p3V14|_`s2;XI3Ltpu4YGZv~_p+G+37PDG3h*{#zN4MpulAH)e{
z$X%I>7)97l;Q>w;HNdWdT@>+tfu03o0|RSDTBB!>=emASK@COIq}R}yI2ExbE+ER#
zTpZe*E>^IUk|G>$u*?AocQ>*2pych6=Hsu@{=$4LncFiTcZ-0h0_)GSz|629KpuLtZ%hi@@-P@q`obF^*`%dS7Ts)rIm|}Yc?aJScM14{w~?xov=HO&xnZEJIv5%
zLSb7*Z*^a9#5^0$S>R86pgVTMaCojw4C3~|f(sjGHg<86ZdnL2W!x0;nUu7Ycu`^2
zUU1`#FtVXzhEO@s_!_LBNvY3=pAlejM7zbqz6ns*BjK=UBg2Hrl*t&dk0L&XX*T(+
zGWd%1G|tdw46~<=>5)xt6)DaFp&@jKOJNow;-%FD9!lKzjnKW{7$cUGsiP(%YN<7H?&u4tue+E*7q2cC4_$lO!
zFT)3mI)OofJ%#AxAX-Z#6}$xdi%!`X-hR(-OEt_k(KUDic|>5CTE8$xO7hWGM&)_}qq%yl4brflu<3$i3gBx#Xx*WLwZARwVq;wV7lc5klh5%Z
zys5pq$7cIcFLis8`l!!m29Y~G>F%O!ViO;4bR=sbqF~@E>0L~3rRFH7a
z1L$<{U>jy;UCLYl56zMdJbH2;I^8^)cBb$6~0U6Ixv{fhOcJ#)-i1x!2TZIgs)
zH@}pvF;p0-I-RnppD7x3t
zJ)F4yU6&4dy8b8Y$iL5Ik@`&bKs=)%?q!!MMQ-g!-qfx1SMg)6Lg%0KPVyGP9${$MXcIfbZ1D$}M`Yi(
zyeFI+5${svGwYT$r9)|yw+wnXv%=ynpRt9goYC}BDV<>9Os)}NIfD*{r>yIJ@;K3&
z;*(ccjPlMwxZeqX7S0r}A!0E-=`FCAQESvz+28J#9?2xhhQ1AhSDm9fi@T~0`_H>T
zUspshsTr0giryrD74O!?l$P{Yp*DO|F+uqOm9a)+~D|p~RIK+?|l6I)g#qUpb
z2WF@7Yl_zI85c<=_H$4~_W~b6Mp3?QIYm^H7eMm&U4Rr7?yt&e{coSr$X_GO+v4cg
zo`#MEsRFBC-`)vdfwAuec|o(Dp_Cx@p(~+`&?o5W6Bdg6MYYHBoK7|#uhJeR=|;lK
z!*7Q4r?L?b1HTNjNYYd3%|`Io*<~}~RXu^RnsvLA_I~l=k`e69Jorw}-Qg##S*X0k
zYNPSs;sxJY`>G)G5heHQw^FMACY(1G0L)*CZ>0nrC4xH*etH=fc>fZVJw
zc)24f5-*OvsVVDu^W9R!>2de>Fk-Te&e)*JVLQK-XrT8VStQZG=vf$`VUaFC!5j(g
zIcD~p5ZC|)aLDTCCO*^npa86hqfrIG4Z#|@Zv*B5?jM!D&gO!q&&Hdnh_TCqPl}Q3iU8vcYt6^+aJ#J)}R
zX2-WZZ#q8{2>PT6Y#mnZ0*}NeLtIc(Ngj~8q*($6lf0^wszK~OefpEL)q6fWUwP@{
zcO^}MofhJm-cpes^+%*NgSNQyPvFgl-H86<od?9m
zZ;I}Pts_szibFjyelg0%2ixzUm91rmc#I{UV^v(FRR>O0KI`vvb=dnZ!KB0|-RwV4
za2xyWjlyTQ*PAZ()N>e_xIJ;YeFRA)Xi0y&EjagE8#_y5mshE&h9#1nQhjQ;}w)%>r-$6~7?iGCg5kjTFz1+k{
zs0HwXVT%S~%>Z#1&qvdI6wu5Ml4kz=WNPueo%&T%WwX3O5j(|Qo5z*W8XUrea^(6wmxCZk6Zsfx~Fw7^;5#QHC0Tf-;Xd!cvT_2$$pZ?bk~lbAMxl9>1x*=
z7jUuGAG6`v@OV~J=h)EI(kjV3yN6{l`T6bJfjE#rhC~}>Na!ZK)Gi|HMNWANm{$eP
z*lycT&#cjW1C8EC6w}A-XLpC403~*w$kXWub(NaDqsjTbb=F#
z5%mQ#zjfnVH*rdnW)&mfM?QgaZ`w<+K#`sd|%y5Px#jZW9D
zWbtVxZ+X{uG!{U?(@j``H;)bMYkJ>Kpe1ZWH6++8fx}C9NXU&So^hK={kn4r0Xas}
z85z1t@r*BSl(Hx~v^}Gx6DPXztC3$&b%4k(5j_ujBnq3I#1%$a0x`h>u7KWfFOxi~
zoBebPokj}(>?2>ZXZCw6)MS~yfA(+C2^~bUPva(0b+uMzk;aUzfcy?+UOgl5Wp=pRc;)4!#8+D)=_@y6@>7*#ZjSO0aaG(g4bS@d>#YodLL-=8Pd
zC0((eycLo>M6x#I5bTWH|AMS2kIY0Qpn_(y7NfoRJRiRlmYr81W1lh<%1&X`fBZ7+
zZCL5>01euYF}+FHs#|9?-LLV|d{GNC&XT0xJ5CWeZZu=fgn8jfb^0|CRIKycz{y`d
z-d^Y=iEH-61`#|Q(q2h^5jRCJ$poP#=Uk)fkDbBLfVY}n#HpXt78R92UK!ebAtsyW
znXx-P5*9C^anX4OpPebX#U>7huW^Kod`e!^;_AZ9Sb^yZ1zJkm`e%y03Af~)gsokH
z%7Bv<(-2#`Lh^nETAwhfiS~wW_OQS@CA-V(e%}&BW84?L#QK=^yx(J~TRq}_Pbpb3
z$>z9+;?y8vJ^}QzwBNrjZia0~TRO_ru&yA-7(xiihykQ{Dr7#vnp-^M{lMF$T_X9g
zr4cP!sJuj8PV)UsL>3YALFvv71+PO!vLsfLhixq#o?4mpT=
z>t6agFnOG%VbhGS!((R}_73qJzx7|Y`aiP%PXrZ%
zXdYc|-=Th67orya2#wY=T;Y!wPj6GedkPC8`KF7PV6B{iZC{ZqS_k^L;})_3uVPt5
zubX8oBVHDw?|w&?nfN07ee|ActUwj{ERf?XYa$=cAAQI;FS;jrYo&~JnmvIe0-Uvl
zvb_rQz`d$LW@)-_m#SvaE~Ut%?r0L-Y}r1M#YZAD5}X}Yr#NuW#rrE5jnP-`--FV+
zAbWCREwi~v>v1YYgCfVyVO485$(uQ>vY#9hFz_z_)Yt<9-6CqeeNECfxdsy+Zu@ee+B5@y$1TLjMW55
zi<#;YlH^2hbjA7;6zxMN8%6w(UL~z#@j;Sipkq10Ke34;*sPJ1oKD;*ZH61?fG&M8
zvypsXgoy4W!FrwkatiCWMTigBI~F>0KfnJD&0Gxh=J2y^-1!}*KK6!0Zv
zlivV71Q)F7dh#DI3p?{3nA}UOVZwB8+MxnlJZ!D=a2M>|xK3oXvLos
z8^12P6}EyTY}K8Bge`p+xxja<0+P7f{F;ZZ!fLA;4tq1~M_&(piwC8Mea5;XPb|D>
zSz&i5AKv;MDiR?^8&VFl0G+1Qn?fhztZhAKxul7+-uf-t(kM(}Z8WxZ+@Vogg9!h?
zc+BnfIWS^aDYpaEHO%iBF;si>`(FN^<26&$1iH3%y|J%UiWzQzCxX@j&ZU^LE^3cZ
zB8`+W3C{bAo)%N^KbWUb7dK@psp
zJY&6E!|=ZaQa^sL{}qkzp}m(+P&-v*J^9y9TZwp*EI_CfflAG_|ASpI_GOF1;}Q(O
zZ};A%zpRzKIM&K3v2lR!pFeG-BA)X1rL~&6&IVbZ?CafjbzOy-Xop>07Xe>@c`PjI
zn19+4K%T{?)jyh%3b9e=`?`BROo7$1I49y5_2vX!um33>antEeW{G%}#oLcf_t0Br
z-K5<}n7_d4heUd=4!@?kH~QP%y6cYR18PkgTWQ>5_{Il)p9g5z{m5=MAK+5@o?qjp
z^gPx5W*5Z*F6A3{setm&v?2Jp8;}99l>eS~b8*gjM@eo&9?5p@;2T3fp!e+-t)V_<
z0VWxzVggPlsUN^PAQ_sZQrw@`RU2L+y_0OZ(vyv$zS99ZBgS_>2@Xt8(o?(6%s)&r
zdSDz6HSIhectSRIeMw-=>X8{3Shb5U{CL&=pP7NC=tIJJOWO=iPgvy9pu$Dgs><8`7cEQQ0%c}^|YCn^4ay!K?hl1FG7ApC6BXy^K}lG
zoe$9|8~g_Rtz~!3x$#uj0Vwt{S3O294}9cD2=*~EPG2r7FgLLHKqgOt7e{5}w?Jxj
ztgISur@E-hOWM<8$abr%P$3GXf4iE_0!jX+wQ?I0tSpST4B)iYV=Okya4rhDM|yQ?
zuuDCO)AJpwsWV+ZL~PNs{XAq+lER#x&(rKmXL2Jas2bm>?mRB8EF-yX
z#`ov^v5zDj_RXHgB!qCW=sFyedb|C>b_
z6nk?5v`BPF)#j)|82Pv^o&MqzytC(gE0#1$FE`=$R+-R0pnajhS4gJpPyFDO>k28p6>B5cF`W{Z0^JKtzFAWxRFRV7CArx!%W
zZnp5&F0rrO+2BRR8?OD$hHv>#Ux>C{P8^>|k#5D&&Cc+*4M!}tFJ8be&Qi@ZS3wq6
z;^;Jai)$L3gWon72b;%fOM|Al!m_x6oRU)se2GWooyRrPoTaL1w6ox)LI&=nSR;3B
zqO{{%gRNWJ<=f2ZqD-WSg2`^d=`t6IF=M;kKEn+Swdb
z3dP>sYSIvAAPFJSu77wS=DH^17d&3Lk77`gFjF;=M>RCq!sPQL8r{46nFJnkK9^$U2WZ|kE*i`U)_>@mee
zJ=TOZr&)e3J~B(2UuUq1E27C-BF$Rw%8y82L#5jBdQLvecHSnCL>ylg3S7+)IBFStA^FT9z~a8-wjrG5VYs>7eLA
zK5=Dqqb%r-&5{6HdRE!nA607TI6wa6^n`b>Yp{5g3urHXhz;IsR
zHwWx3Mr7=HxpQNpvLIc;|DH8g)H$~
z;-u{b?qBlc1|qUy<#d4F2VE+lhV+AVvxV6?`?e4KWi+z@x21@sGo^ZHa}2GF
z<+u~I#CffM=>ShzAKzs0x;Ivk)a1RAEWX;#($O;bc1
z(R9^K)Xe&u3%Lf!p#~lFezGJGJ;)2L(>8N#1gdM!;Jhvj+8NKqFO54QOU&
zU`EnP#K}ULqr}^AHW=|6WaHa$WCuqZsr>w7WP6h0`24w_Y!7%ICH_vlXZMDoJ#k}*
zpT_7SDp4waLHaG!U-Uyo>^t?pYP1vbJ
z+tqY})#Fs(m_ha)NYvc!KVfVYh=r{tzXDlIv8uL`B{A<)oX%Tkyc1gW6N_R@@Lt%`
znWYTK_A!go1NKBbr%111aai2$MfZfu~}G^iW7)Q95D7cVp6n-M?W4{arZtzzGR6?6W8AAYoO3BE5s$~v8)DqQTaT-0YFt%%W6EDzf~>0;ibIa!
zUZNPbfX9Qz-!GrCH6_97*Xcno&aY7RRX-mh(_%S6$7;O?-J=8A;*
zO1(7lu$j7ZzLI9hWjAx(b5wtLgEW4u<}D)VF0(oEmg^>mw@5v^e+_xdQztGX%Kg1G
zEm?V`cP~vTD{(c@%ap})uLOGO{tfkV1B<bph7x&5wbK1yy7h@WUiXqtB^#kc`NlfaEelyVHK!!HO2ut}$WD)h#
z`!C5d%Jz5k)4d}`g9yi{!o$xsBdcO#gE3U#c>I#P{O&+wXcI$+T9b3oe%$uH3Zoqg
zYe2k4K+eLnooCmq+Yr{telw~y;BN;MK>n`V2dU9n>X~HS)T}Tfn-gm$wN*B><$jB+
z4Y^v`%iD9>*WMktCP!)+mC*1jJ)7PPnM{o=P*CFV)7Ev_PUsKFkXltd7kog%AEI-f
z<;sAEN!e(c<-j14_}dlAquQTFI7BQb&9Lhqy)tDu*|5H+x-(_kisU@r?ow&g)(3F{
zS=c_kUJA))5@&61M)m~dtr3O(teKdaqdj9E$eOV`um;k~VM&xuphER+1!d9@21UT<
z;pbO%fz_n?J6YbNV6((}Rm)CAW|B{cdmQrK|K`0#Yih{=mr5rz4rsrp->eu(Uel#A
zc*N@uKNXotoPh3)KFAlL&c$ZMsBjOhN#^;EIrnFmgAifx1lft|a})gNF!hHYXH|u5
zZBcPj>|Omik!Zi_>D{Y<$A&EAiM7(Wsy?Bb0|EbL;M|CS6;&tT+(7g$(G)}UyW>a;
zBFv8Zn~SK5C-P)GRIl?zR8GatN49Z0%Q^PCSM4HxKjYJYL@3FFwBBdkX=h$dYO&_c
zD*s4Iw1{OtcZMyI;S3{m5e?bgfi5yg^10SR<~)=S8y4$zfU?=YPPfFxgUV4DpE0B;ZqP((ePKA?an*Giqg)D{vyFYk|i~)*<&Q$~fLStgMq!OLuvr48GcS6
z{x9L5Q8l~VZ^769`);xk=wVNk8wUWRuavS<(q1?M`}q@UZ))nV=2%KqobGPe$h-~N
zm*Gv8Ebh|C7Zs7^ea;1Fa7=#iN9VN`uf#f#CuV{J2GM90fG7)i
z^j*SAipHtWHDESiyTZAQv$k@q12H+!G~n^Jd%!u;4pl>@8SC({NYJg(xjpvkNJK@E
z|Cyq-5U){x^8r{1hcKUT{e%Zt#06rJTq>%O%&OMwZievi^ODpEkH-NP0kAdafQ8K#
zsB{nOc)B~oo-`yIvg|eDnJ~%+JY~VWq}J>#c&kUJ$jT>OLc$+}KdV)@U?2Qh$gF>$
z{mw*tx&`;YL8}CLjIA*%Df5M|UWyYihGN&Z?z(HMT1t5)X^R=2xRgsHt$JAq@d#<0
zN9EEPOVI@qf(}{z#&14?^IrFBND>@;mA8sGiH~U#tSJYShsin$)0r&60g12@`az8R
zu8(Ye1!h?Ll>2phNgl9cgia&hiBa4t_QDlI#G8Xry6ROK
z@N}rsNuZJ)*+Hmn8+3Bblh#*$!1x1M8S(vkd!pbq)GlqYtUt$BZVsb6VxMU<39pX%
zWF{N)9NW)$stn#AY?d*wOGd;y^WImw>=pqMTm9}o(CVi)BJG9prSL1X!N0H#$TGv~
zj+LUvt+msTW#$A@D7YtPG^Olr;j1r<<>SY|dPyU)>smpn#_V7`DS!nD`PxHzb=DeM
zALFYjZUBDOR^1~LIRxRa0hv0l>Iue-j3tQNMjM#@Ab3>S%-n(K@jWRVgjw&V;ILvcyot1=Rb
zi&&{*C@zMLAHRf{Q&`!fMrINhh*{z_)U?cJ(Wb;tlwZxf#C)!dR`Gd>Rwr~ZNGq+i
z!->{_-c3=y4o20CrXEfp@d1h2GN970L`43*zOR#^7u69p*vhpPQfkWXBWF
zmVf@lpifA~E#$5#m_|4yjI;8{=J99pNM1&TtjEhJFZUW^9yn+x>_wan>5$_7E=#c2
zdsAkeCoS
zImVbfNoL$cd*%XcI)$6sxJ9PFz|(q-H`?&|i7zXMnEp~ZLZwQ>stOtW
z7LvS7R8bUxG`r0}{2!m;$NOwe`;)^GunEBC`{yFqmRny8N1Z~=pgneEkg<2>e8^6e
zlwBX(FX{H2;ypcYj-BYxRx_Coc?A)~zjJEn!bONViTYdoR!f>10?0zq1lK
zY|Hr}ACrvf60Y-lb-dgd+#w%g)~hmM{f*}qeZ0s#q#7ub)$($esv2vVTOXBiko3%y
zU5B4*lXhY&#vuBzrF1IdzDIsRt32`ZgHr6M#J|Q!Hj#-`ou}3CVh@F|OaS5KFymyq
z{x@B8xJ$zZgu1elW2S#bx=uE-=ZkWU58mWr)ahbDytc}dW>q!G?W)E%>+YShG{AG>
zZRJ*w1;b%!?Avs^XE#r`(`vNUAx{qZXpMi#haGZ!W}&u4Zq#%F5t4fz^SdwIGTSc)
zB3FP>Tl64Ff|4xar1731TIm(#nfTW!6@uueNttbOsZ@2g(dG1HW-3>lXQf>~ilLDx?
zbV?r}JoAEPWqu{j*9>#vmrw9j7vy%!rhKD(FDHF-;9Ft$w`{t`??tqLf@Cd2&gJ`e
z=k7EXPnlXDO)WUcPL^tjrsuQS=aliMN}>6Y?W#Xw4tN2U4~b(C#lX<^qu%;)e03Y!
zrSqAciQwaO29i~SDi~OIHOu{LHUIM``KmflE@zYns5?}1KXuS}=Q@Cd#*J(#lc;Fv
z&Q?z>|LNOz-9W4&d%`r&mAuCEtL&lKdP_SjEPI*U5DDxU@NmNGHh4d||6PGB_@8Tc
z*gpg9mM2kL)C%nCp6d4%}q$RRNkv_oncUVHJpkshW6f4sUG
zo+#i{k3e)N;lX%QYM&2KeW>t$s%agNoYalS-CC|XZ0UMtTwAJv@R0U}10
zBE8w0Vwgo%E>wJQ2k(^TL(;ryCM1*_irDl&Uq(@jS!P&HS`G3EJ#ymBB6yxme{zUc
zLgZ8^)Qs!9YhELNUiPQLGQtg_GXZk7ZpQlzQ^Zh{Z>!6|8D-qoCcnQQ#%&7uUB8S^
z7AMq==%!&*X~4FIIjFB)fB%X`Y!T|>?kYU@7U=ms=m9RhH>v9_*lUw^9gK2>pRwT%
ze%^4z?8-(T%rl0b;%4UQ*LKYC)}9;B;-^!%nNMHAJSAN{fP6F2p}1HlEZcA24I2-z
zMv4A+X{Q)B5NMAu;DXZhv#mFB(W>FMHP^OUbP|bJ`Z~L
z@u;1i9#oaHy-`)_W7g3X+B<||0#ucH-P)erBFzxV5fqU}*jp5L&R-Nb{er+;740q6
z$VNMXSmX2@NE=^05m60cCf65XG(KApONkr@>#$C;3Zx{x+#?S}E_mIq=`#!J5ZKl0
z1n#2(%2uortpgC9ldc#J-d?YJUa#6JSo<~wS(g+k4kTEWlZDG7wDH?J5y9Abn_8}Y
zAX|*Z8AklVTkn1#RympBEWx)?-}>7tB+=CCo=HGOpHzyp>%jMvnjf;u5Ca+3*+DCY
z?o4`-_biRHdCZaeHMfHcgHds;?pnk{YC_F34xw*~NbI?x^l5mc@j*nMq!hnQ`>y^W
zwi4@WpXNP^Nc1SU@c~~eP--Kmmb$VA-y^@OAT}=Xwc0It&^{7BKNpWWGlDMVh&}R4
z8e1A!*L>i3=*qV6W(lJvYO|1L9Sk3nne5C-a_f!!pb27Z)-`#4JWk5Y>kpJn6)dTXhy}ni}rzX6vdt4pkIu&WTh*k@6en*s1oSw?1XYgfr{o`@Th1G;33q5^brv
z+q#x+4zxD+2fgy>J^kAEf+^x+nNlw#c2Q(+S+*@+qHJQklo@FSg3x}_a9bnXm{9m3>=PI)Ama%T?)_$or;fm^~M0J)N$ln&w9`fOS0r`@%3`
z1GrFq%wveY6_Bxl5hxdsgQDym{UMWbolzl}tO!)y8rftT#i+a*wYrcH$BGTp2^%^w
z3z*;B%uJR6q=LN&_@khA>meI)x||z`e;|u?eeDF`i;pr7Crc}{C>bhVIz{n9X~Xs}
z0jKcW{OW5T`44S=snJv&3wCXi6T^-Z+K*#3&GSTXPx37~%~LI~BGebhLXzNFgx4Pe
zI4{sjUMT97@#~NA@+{>YUae)Sg)BhK%cYB%Evuq6owMCr>>k!jmeu97cFVH58f0dH
z*T6eRp7>1FbG>?0JoZ27kqbyO6Cq1o{W@K2_se*JC~c|gW|6f!TDv}VWOtu_f?X5f
z#8T}o@V_v<4@lI_`*BL3{jzkiv&`YV(Z#Gou!nect&gp_C?HOmuJ1Zc_F@(_S4uV+
zaS>Um@Mc)iuu|)5AGE_}M<_h9URkAm&9RgAa!QOSS*0XP)KXq%Zu)^)8IoqST*2z3
z6-jYg5+=bHpL|vQb>;PszbXISSB&dP@0&}##A?Oapc`aW_QD)!1?GS_b$CM~PKI$&
zPOm9=chqZMLt6iXo5#RvK3ZMchtu_a$y*x-`T6b;ec!vo^xF^(2d%*Vr2T1^{fDmD
z{0*{_{1e>e9Ig0f+J+pf(ifC1KBCr&`DrEjrJP1_Ip-0zGdZ7gX!nWqWMkeBckBw}
z^S#-2Tdx>n925T#MOD>SJSLo>&w62r+*=zV5>nbzIw0Ol{yBLS`RC+V-TNR%0nse*
zT)LSbamwhe)rmd%AF1GwF#~$I)bjaIuTD>ZIW_CHl-?5FB~@x=PoiM4v{qnT%2h|ZAKUh{vE
z423$68It#ICd-EMCe8SW_IBC^_zaYYeCZQ5h2pV269e(r&<81V7WPu&28aALQwhIN
z($1N;gRs48Wit^=9+h_zwlh?GMy)FvM{pK+I~dN;uC2r?W_`GUct*;M@18@AUPSCr
zyJ@rjv8Pm
z4I>im8(@QFRHV-OCZtq)YXc&*yWh93_xp^9(*C6gZD4UTnn|+sTjg|zcHj3j^ewM0
z=N{9~>dP0*J|R6p7Rc`R{q?>lU>qLh`r3h1Ry=gUzsZKFO+7LC}xJC7y
ze|%GC?7fRz1oPPRPXoUUE2PL~TIFpDlDcXqxP&Ac`P7=@vJ-*+&-ftZ*lv;Lh34;&
zbkLd;E@WNkF?P^-FC9BUR|*kF+-qJ_yWCHIKy7uMeW`?G-R}Gx
z#z#E5?);qkv|rzkh0O0W4-YxxHLRXu%-9RcDepz%=16XK8
zCON*P^FFdeH9APSKej
zVgBuu`q47W1h-z5#G{Vi*5+OjlEjI#m)hwq6IS}On3z?KjZxM;t*6;6Mc1&(j;Qqo
z8P9|qi`y6#WXF;8wg)3%0tU7>ZB+)1j5IEiPOoHD3jF6&=g+lPj@-Xxz%s4_zJG2F
zBo3+wFc|uqzhyTtuW>5fqn1b7rRpqkA<%#@pRi}wmrsFwri71_3&@gbq9hTzAL^l|
zM}8=uM5isr9>{LLlp{r>Lg#H5MgjPB-#Oz;&4ruyM`=a;l@(FeRBFx@Lb{{aKhnnn
z$XRnfn|B&faP=wUUGUwawq1~`&f#yTs6}h`VKk3MT|VjByj1S8BP$#3e1?rs9$`mQk~qvfWUBJqh0FsD
zu16WZbnWnB?6{P&t3CSY^NHvE@!6mO)vlMyj+F)EuJdHiH0;(rT`E=UB3f#WQ#Au%
zWwI5q;)>rp+-+;4IY@(7kT9^3zX_?R^)Xn>w$6GFJ04zPS{Jiyz4cD=#kW2N-TCN^
zK-L*+yQuDGazpFO!>MiLh7O>%>si}5#Y3*Peyo55?N&hlZsmZ*#o~F@}V1LEpF1cNu*`-cY@pEH<^NtB@@mLRlEw6a^k&
zktx#g|M0Qzd~1VFqyGUpNX@oU8N(gGxFYQQmz$UGr8%LPFX61gbeo`nST%8^&Y$6r&qgf`Vs0sIJPS=Us0Wm+)!nSC8MbPM9+%R?rni^y%j?ve0|z2!GU
z6YaZ8seOtp-J&`J4S=No)3u}rd{w>wJmqS9T?tGwcnQNWWBQ;M@(wcW8LjzIM3^8m
zS*sX9`9{CNj=V{zT(!0H^lL5#ll6me0eDD@7-^p3#ApU>=A}{AT$O;U~&^FImeY&VlM-)$`yu-{U<=UFkn3
zkNdS^&!g~DMj@tu4`RG{&tPtkDkPph1>w_X`{kVJ<+(w4pV0WgqPv(OM;p)_t*E(~
zomkPT7o3BPqqPH!BeesK!?lC#7DRemiAKHfWGKd0ez+_``i9CRxw43O#A%Gs3)(R7
zdoDZiSHOv&d!1pZ9)vyz+3lYK>&rqXNl1JUMoPAxV)1O~)6fR0FXQi53;LBhwr;lK|Hv5N;Chy}vgL=q&VBW^~zQ88&O
z%|y&}m#Ut(B^-^ih9mO~)nu&c8o3@hj}EDxOzPDiXe4LdI8I)Z+TsZtj^Qe+Cxfgr
zmj;-c#^APrE@2Y9REj9b7jI*f2tng|k=!~+;DDftyK?<^6${i#(m070-Sb{<)vd!P
zU}qZAehpVrR<$2L1`I8s1)2emv1n||ukRe7_W>6rv9YPS{&fYce)5YS%wK)FHp-#a
zp&l;NMbDnac#LCJah<4CgxNw(>s&!jco>QHkhda$oPqYs8-5!R{}7N(;9n?@`0eQo
znYkjtwWcySB>r^XZ`HWI{ChEkMJ4L%U`a>pTVdKYPG6^zHQ0>l*I;#PqK5IP^?_Q=R)*kKjJ{bGRa>Z;6OQ7Y(TOEem3UG
zw3xCqj3Eg!M7|*B54dE^Yh8%Hi%iDR^bKBX9^an8*$hp^I2`{!VT?kwE;o#!LllDt
zZ5>A$c>CVc3&-wK)=!n#*izIHHj2qwF9bA0>3h*jf$#U_^|nb@Jue5Yk`-F7(kcAW
z>#&ts|8gBxIppXf+mLa?YFfX+r+Y?rIpiQ3-Jd?&_}A;m9Y+NJVBZ~jHu|JXNF^&(
zZK?{Gsq9@`uXin^
z_RmKwk!*jxo0*6#8Q`3a|4~&qF8Xh_Q9V`Rq7bDSF&R6EySj}inDxJ~t|<~uPz^X%
zsX#Y@MDrA(Z`!mWsLS=Essq7OVm@K
z)J3IR{HqybtybsOAX==7TIi$3ZcOdkOD*ISoUrUG@wRpyz2a{J{T}A44fNXM
zO`oLozM=6ihxv~Dv>%3Nf1w|Ub&`5vLN8`zF}qDt8l)l63X2Z1
zd_Z?E*|s+A*Ag|zsGUR6jt*pNOak{qltI#r_bZNiO*2pfs9vZF#OLf~PR-(I?hCmEJiV}qQ8
zIC6}tX$JU@g!PD#-R}~%%JYuWFA|L#Pfz#|e6}u}wFJu}-#F0c?)^TNvr@}hV11NR
zjr5^M>7Ba?DdewoAFVUGhx*NW{aMQquj%U7otF0ZNr#{)E2{EMk%7>EYty19^v+gR
zM5Kisz-gv&e8X3Tb566voM1HO0oljmFq3`9BD9RLiy;+x;&l6!v9^nQk&SRUin0@g
z_|8b^ZSsStJ5WS^>m)BfFbe>HNbl_vQWi+!_x
zZU&+tR-Gno?kDX<{^#wH>{yOE8~*mHezv`#|9N{v-?47`az2*Y>$djP)!z>I9@AibO~w5RHuI88%_jTi-Cu7AYka^1-%;!oSfRu)PMg34&$Vr5P^YYh>DK2%6;6!0F+
ziuKu=rd+($zPaFQjsMM|qAgiKUR4wDtMsboo1Hm*afPf9o6_J@vp2z8-h8vFY{NQS
zozR(s_G8YJy4LQKX+-Sr?bkV%XhFuxC^Z{{+LbvjxgPYNMp9RX5Gph`*Qk)
zC})bUtGy!{;TMFj46qf3?6$EZWj$tVrCA=#SV
z3~fX=3iV!Drb_3V)?3Y7sA#qNIAqu1KH7N{fkil5fha7j<-BH`)oJqQ$}}tj$u>sG
zwI}PdI=i4n+{3ANxl{}WR*Y(RiHdAix>2EGiQ|C0q;3k|`6kU{(-KQ|6sz
zA35ye!<(%;;cK3&=BxvG$RVBP#($UIaS7J|EzOE>?DXxx5{vpu8cI(Ix>)>mxYe(fHQ(V&_I
zE(Ir_fE*z;q|vlK4i(X6)ZOA5U-8|!2-{p#<@oA!aWrBgmve|Y^c1COlRG$VT{~x2
zH5Sy}qlz39nYbcm1LC4cr=&dlWf&dqjx*F}u#4K#$wRc3rnH@olDtyxCI3BAd}L2#
z19TUMUco8nC+5FFcA22*E=8KsRuse)@^LaL$BpXu4Q&dKr^=7s;+uW?Hc-w(1I61E
z&khlORON*t9tEarH4fc&TV}x;TNlb@dyawHtP1@)RQrp!_OFwNte}i5J@#K{qr@Mi
z9h6J=nHtI*@s0iK?$H(BjD|8q(XA1b)&X@)i?t4H;^>NKxQWbVPHsg-Rn3a3GWJ`{
zvNDqJtpn(uHSBuhfTr7YO%<~m(GSR^!Az6xJb4*7LdB-EkY!C}ed+TATF;T6h3&-|
zqEKYbthOa=lO=vKWsGbzS>0UQ5;#<@c~c+3C6F-i@p?n$`9kXWcb}P248?-gMqtY-KuWm
z)|BP%zx}bT`n@!2?RBLK?P;q!+}ejbrpeCgRYhq1y4zV=IxW^-WYSL##mvhro6_=k
zVE$hH7tT8E-sw^$Nd%9S(;GQGg*jQjt_tJpzyR+3l6T|s6{_zmefS5Mlxf}^$l6qxx=?>#yx>otT@d3JaU^^0Kt}Mk;Jo}I_
zboe-AnqHu5h{;?g6Y=yz#s{`NbtgP>~Ed+rgX
z_T?^>%7n8fZ(H5A$I*i)!nV;`GC%L?P~LG}zr<}jS+V@G@`C5?ybGTWcrr5cMb6dH
zp)&Tpzzup*uxO`bJyO^gwh5J}F!sB~?RZ?jLZ#brl18}Dsrn7LBOwN0%r@m~PKC$k
zkHARUoBo6|w>bUTe2lltp0`LEcVQt=5`s~w!Hig)A>I_-25)K%axarcd6QD+A+zu0
z9^ZroD-rooqm6H=%=6)AzHk2KQQlVMg^}lHo+U4fx47X&x)*%bwBzwoC6_iu!;OYF
z+q>iBj>qTb>^KQ7Z)!ZNx@TX?<}7Qtf6juz@i1pAU7N4vA=>g;SC(T5#vgx|Zb#PE
zv&by|kj+^*{dVekj6VMErKfQ%`U7cRF4W`M1+Fa3QaroBIN+Iun9t+vnj>KutF#x6
z-v>`xSh2!5eE#E?Rj`Sez?Y*sO-4h33DhM>vvTc;$V}K8G5YLe0@8=Gl*YdeX9$gd
z8&0D_)PI!LxA?E#W4>=0jd@(0H0E>tYrX1mZ<^^3-lXDj-W0dmo07U5*{w0&7+r`r
zseXnx&9JCv%*h`_<1Pz%fO79GwsU)w=eD$Lab8kIIIEl8tJiKA=zLE(?dFz{<>&Bg
zvjNtm_$F{RPDyl@WOm4jE_NT|m#S$u!HKUMj50wj#llLJNo+;-eq_P3d3=hA8TOO5
zs%08Iq6Z*7Soa97rcg)#Ti&)6W%Mh|QYrX-8U6StsuWg1t!#a!PaO7v&Xwuwirl_t
zi#|UTs3q4;rD{&yo@4dh!Z(kpJ*NcKrR`ZI9u*IXO6kl~Mf9oQ(O#?um6Sw}V$kDC
zRrnU|!vkN8UE3kwqk3*jDa~7!7^9unX`naS#45rm5StW^W^cJ6#<*9}FW`HVYI8{%
z5qyPg_C^hZe4*4<7MV*FdGh>G9IfYJi)#I!W-t0o`n2NVA+`Bo;N2coBkch@&R#Kl
z5j*c3BHIVbmhn!{1-AyLHF3R8jNt{tLAxEXVu%XVD*DKfGqiEX5z810Y@Q?GY3YYC
z^mr7G8fanToH!}zIqWhYBu+J*k^!xXPCwgzdq11!x}x*bJ9Br$AIYBrnRCNHrRpX|
z&1brq1D>jeZys{3Du{fFLlzG!sm>N+TLL$;y|Pnjr;eD2A8R<;z=C
znJRsj=Z;{DRefX9j#5ptKBgMNkIK+W_s1$n#gz)2dd(KAuZoLRwwTtS3Q4(%)@n)S
zWwz_JlYxsR6pfqqnSQ=TroH%{!6kUcX)nKLz%H5DxrTPy-B7EweUK!ZsHWY>aV$H-
z_S>|lN=L{>YgX7*b{k}kXzTUnfh3v7))mQ1d`0rylY**Y-E%o4PigDWGI5)%PWE23
z8*Pi<+h>o`S=H<&i_aOh*NFqzEE#=>1K?b3m43C&Gxu>Uvu}Dh%X;lS$b%cgN=ITJ
zWh!H|b#(?_d_^;+kxy2r_3E@f;V1Qj!ni*qJ!O*a$sAXZjkTtOOqw0BLNEBbw4ORQ
z(X=wh`pVz9-OHZNp;q#z&|Xq~KD~O8$!`8FH+?&CfV*KEwjgVeoA`-QF@ZM@z6m@0
z%-TY^Og{ZA=15kk$dwyI@egrl=wGT)kNC4%cVC;R2r~BBrq=CEzdZ%ii@9&M#PkwT4=UqXZ4jX6*XQ+^>$=Mp?A{7`yhsv7Q-7IA(`l5oU5?
zR9`x_Debw{3qB8XLK@MIy|SlLYku2IRUPJi@taGoaL7BV3`OZ!+31LswC3h~`TPZ1
zv&+xFQ2V>HQJcqq>}m<;rdR4;dwb!A@VkR;@vj6yYxLIjf$a+toi)D$x}5@hxtVK#
z&vL28W?mW;X>lU{+*_OyOo;LaUrRW3SS-nCL-dE!li}ZC>uw>tLFTN>h=46D2p-(3
z7digoQ?S~mJwkU)7hIX2E~Ncb;u|G9#k6sDx93H8E?v#*AbDRf*e*SVdC@L%UTQPA
zGMx*FX9b>N*Ttnl6#ogYVh}v1L3R}))PjI^KhoUq6vll&cMJ$|Be}luHy9q2br~`a
zaG%wsGTcAkH94%G}R(DGM}zyYMi41LmMp|F9)rQ}1hZ^-%~Lo-6Iksh7iF
zT>C!_WKFPaWxOfJZ21a>d)Jq8Jo05T#1zr?N`DVw{+wS5X#a($r8bv>S=
ztF))}G~<^l4Y1FuU76o5)Lyz^(9^6|SGwtXNykVTUAN6cU$z*-E~ss|^Syl3c2$R;
zFh;hi^WHj`nOnx66?^yX+3=tC?dE&(`};O3xmVxjhL#@81hN(OY2!}SSFl=gZ9!EZ
z*e(@u@ad|x?^REN^giQqyK#7%n$b}Q|01Zci;dcje>$E>I5Bngyz}{+F>0Gn?^}M_
z`Po6UlqoDlz)N+#U-;yA)i%$cf=CX*N%xSg?jg0+u8PuDMpYo@ycrzn}cv91I1M!sL(K&FIRsj`074B6qCAXsuW{6*|>>;Ui=
zIr-Noh-9%~GM%z{p|%>_4lC8Va=+SkX&>n%GY)RI&bg%4t2`L@X7~EFLzR-mMbZ}i
z!oI!Xx{f)=FT9wck$K=1(oAh;Jk_4LQ0pmmM=akkkof58oQUPK!9z>2KlkH`#9j64
z*4>gge;st>SAy<_(Y^%#=-#caPzQ%qjnz%En6$dTa?(t+V|726gPo-IukQ?FByvZ>
z6l#8ChWc*uvyUO$cwo;s(J4oAS^H1NsiwI|IaTaMqTMV|j`?>Xh
z*!^35&h>@*%<6^uEtv~x3~?gONKZICbEsN){O+KJjnuP}tU4a2tC~;F;+!8h?{*%M
zPqQ|Ctsb9mJ^!^@>+!HtC3c-krmgcB0^e7^sb3KW`;MpAI8OMMhec1nPGz!YtmLeE
zl>&D&yF=`{Fj?#hpG+D#PsD#dnt|2OdnH)&R}T5PQT|=Kk((^@)}OsaYfu{FS>Mrk
z7c|l+vo((qfBu>8lPLT8^l2FRcF`in!FjID~U)vlqHFeHXd{nI@K7!7kH!qu
z*~4P2qD}4;U%~m|o7U)5edZJ=v9siqhoZ1rgTJ=x1rvDS?^@^zi^Hnl@-J=DqzJw0
zorO;E8ao+WzIC^VLphVL83MnR_(YlX{U~d(#J2+9k4DhDiE5zvVb%+6cY+uq8>qLT
zKl(`nxWY}Z1!)Jg$%%T@piMfmsL|qzZU1X(n!V}B
z)7sD3E@iS@ruXu#GktPtwNo#MllQwq(MIS^y{+gq|15YfqD{4NPam~$?;SO13;I{F
zhm#Z$Q_JiLCq5vZkYaB0*AcfCf8&HEV2_W=uoap6@tz{i8dOKo6r3-qNB6UVa~(K|
z-7?x%6#ukL!b3XP@f1Bn`yf_vP0rVh;$VqWbxC-v*RKcV55yZXuM5b>F+ZFy&q6My
zM>qp}iu%^CjRT6fTfer=%i@U37(?owZTmI#)EM6VDWq<}onO
zqRq38%e7fI`W}{0A5rV=5xOEh>lx2iPvLg2Abl>dBET;ODcKsK`|>lXx0yh@hAqD%
zjI-OUT9oFiz9fgu5}Mn&?stLLjOO=So~An?_u{I4t@746^rQVLen0w&XKZ3T$H&jZ
zbz!qrrJN+S(L*oz`e=SsJlaV1x6!cHmDv%zCTEWdBN8Re4PS+;(A!3BpPt7u!OEZh
zuHsl=gj}%I-8|9rElKF?zIMWLihZUr)GIkfekgipU-m5<&sfO+iYZDNRs+^dor(hj
zt5OzE+Ed_{#^me&BpK$&b~*{Pp8aWp(lvJ-=L%cLoyl>9Cd2P7DCpA^`Xr}MVO)g+
zf9HmocC)`zOu3HGtTQ~rM2Mi-=E-IYyXbCHx+kxpkDp=E*jt6qVuCIqxBuPI993rkwIMS
znkt!fKo@4=xoqv+qXwFLXgW`Pm>^rTA+#mu!&4t7#Q8q~Cr4ANLL@|182?e8E9_aW
zzq+JZCEKDbX|9u9%&AzuUAUO@mx^?Y^+BGZtoV*TuJ%{Ci%qat2X_P&pqf=j5RX<|
z14Wr@kWxmn6LgT#=eG1$&CMAo=wB6|*Cq>bJm$?-y;P&OXDy+#XuEQJz9vgQP$i>N
zc)uxd{m0i_cFz*%VJ2h+YFwG(k}1kWZlFp#ua5nayWF81sM2SumN@5m(1!SQIzv4x
zRm!=!7}4gZ<{#fJrdt|^b+nB^d<-WKjR#Jvc)WCsc%XE)Sit71XP;s{Zc4^-6
z`*(5ARoGQCm1)=;SQnSeXvghQ(Kz?)xSriM|M(u&FYTfY$9MZV!s?H_
z#H}Z#e%$)>){_;iN4Gw8F|OApX`)KccxKTTA%QZ^BDGU#&?|}ORQBRI&SXfY7`?;s
znJkhK5`o+W8OsS7i*`!-*`JrG=$Q#(rb>z^>Mfo9pHI>rB^h70xD6Q;{Tc;f4|3xA
z8uuvrP5qEO8cOJ)Bh&&_nRhe;3Ce0~R+IgL>=wMG2^uG-EX7WW1+oQZJ=!IhWzP6I
zx3T{@&Xu_$ntj&O=Pc>-0Qy|SKD)9!(Z(`?lId&VTPg?X=}h}p9F|Z2
zgmm=rwMIcEmvnSVJ14E2GQu$5CZ?H}a|1{#m$Ev^p9Pd<;D!C>ETM!2d}j-4pZ{$6
zX_DNfQ?|KTi&OSs#=A~$eekt46=API)9&*b;-vl}qmjjECHGfp6YJcrOi!{if&Mlp
zW9>bw#b;-t&;6&QDa-;@l#?MR11DKK6}aQ?Z+^u3XW;sY
zZ5q8QRfUQ^9Le3XW@xp+ZEDxL!Cb*fAXmSozq_6@M!ur5%KOTRN?TFZpO?d%2Y;nz
zdLE*rHO4`E)sVw9^i&jg(`Ow1ipsSvNKtUo8s3+49-lhe(OV8W35fqDYp$&X#PLe-aam>I_)1nXU>^9
zGmIcQ;%H$F90hd~Q7p=3b+CC5d)DvkNOHVnVQqfWR^JVo{=Fvy&5O@adk#IXsqw)pZ0%K4lpxE2
zT0|S-2tGI(Gami1q)8*>t`1MJoeS>ty>euKJ>kAO?p_HUigRZ
zcHLZ{RM_3A}GEl{=%GaE8&xCwwV#Og->joN*R|lEs1aVEMKs!{8v~{Deu3zb
z=06{u4+{>~?OVbnk8oXzN>W%^Py1V@0GGz;S2wV?teqjHpjE0QoaZ5gfK4D5|M
zY8wci{-beOQT&lS&vQN?&%pL$autX1h(Vdywa+=e5#Er_uTN5p=>g&{z=D|nzM|Ml
z+yvfMHE48#i~O;^5cPHu7ia~YhP@h=YM~I8>X2U0(?b-VytV^v?CDMN{7&18*ag#G
z6M2N;A;!4v%in(DKXDSeCrF>SaAQmnfy&M#=&BK@rAcvlrMZtkdW4&A2K_!<1mrlh
zt-Mpg`@Q(B8hJw{>i+7cfg@$dNPV>fdGKLltNR)C6#Bx9b^6vg^B&-$&rjgS@DU@A
z;Cc4}cP;H@+^02Hm|$7@8PR`jMuq7>8pR$+)_CZ^#DPf5p>->BVt(y-
zW1lZR`(%r3fuvb8z6f7NmDxstG%>UuhrY0gpOtPL=`cJSsc{2rp}``Zvt!hLiouZjAkU{Z&;st
zZmk_oZ6y_U8CRFsUhWtKS{tr81$#j_&A@f~B-AG$Yr)kLF#)!VtfvNXkAh}J^9+2N
zgKQd2m`VeCUgV9JJ-m_2OJnEU7*(rf)XG_~3EA{N^ny!WUA1jXca{nFeX`{;To+?O{U>!hYAKi$Cdhf7-EX5ge#VLlWV~df*66!2GgQmRU2Y?uG(W&$
zq#ys5gO%KjK8Qm$lzI)(%8=JC+eovJ=KAwM)@0Z1w#qHFYs#MSxWer32qY!c^dz(H
z4}_F5E0;c;L0y9|vfJOcF#qA=*Y^*@jETGv_1)`%(j6~**4)p0<^?U_maZW#f|VT!
zttq;T;hTtVmiaP_J7MJsoIiDpdasf*U!Wf9?-zSR@{H*rdvICtFDz_wTG}?Zb_3fQ
zw!4Q$nr81IZy7RG80M0kTyqErFR~)*TaDRGWwnm^=<$Y>Oz#VjUh3Ne#r&1ce=g6S
zNk}ZnP7;Fb&*kp&_Z1bjfzqWb``($}7nojdK
zqW)==QDzs5VXuc8lF
zF=`r3M2NFlf0YdccN!#<7c|7h`i~fKwDCnU<%>7kh6@H*XIMv8y^v?3v2-KvjTXGf
z)*`?!rjMtwb@K4U;(YJxPGxT~Vhz;XSfvWI3V!G@{JP;+HY5q9MltqtCft3cf>zvz
z8!xO$5FRg?T_;AjGb!_8onJm2-4v*N?`cF34Od1x(x1|3R_wRxymv9WmtoaZx)!;k
zP}2jvBU#Iion%Q>lK%Y#k8Qh95<1}>>_)r
zwz0NSyvL`~Hda>>2C?T=vNx~YAfXNIkHY^A8^YOY17~>wI%~lMT{2cZ?$ro%h24TX
za8*~hXM*++k30Q_BX(V3;{1@rhAcbs3+8#uApNPEH!Pc4qFCbcX
zT5P(rj4MsnC18s-w^nY@5LeT!UVSZT+5If-Yv+gVPBYuMvkYraCd;s@agp2Nt6cli
zC^g9&@OyNt*y9_Z4I4N!wGEH%@H31fj*sBZHZt-vRN2s<4KC=g1&bc=Y8+$*r&Xu4
ziiLg&>)1c~PvXRw2Tv{3VNyAeg|tG-fb`ctc~ne%TWj}ukI?fu&4nAoLUZ9p)R{jK
zN9%7XF9knKsPG{6T(Xrn&)r7PtilTA&iEKe1(By5G{%8S=4W0>A`?bo*2;U2KpvB&
zv?()_7%uZRr`c?No&&jBccQl;8WgC^ous@>
zXOh>cnY42}B~W@KCfxN6xZIsj&=p#lWhD#ih}#jxxG25b
z#gA-*fi#x%{vdo=)?9b)luDAg_l-?if{jP<^
zTG&V&d#n+jEIll9`@GxTF5v^WTi>IQzb@7Z9zp17k|*$ui6Z+QjbTjX5Nq4({$M6L
z$au(0jm?D-m(Rq7GM3Wt8V@`KrUj{M}eu7;jTRtT~{kpEC#
zH`V90^|dCOh9BxMwZpE+MCuBAZn<91HWt6Oue|s58py1&)QfSanrWFmkusn1Uzpa2
zdB}*ci^MgNH3Si(kIVLugk~M#4qy@4A%su}WFH|pL&zWt$wu;@nt86=6cCpDIhAqki%Ln^nVCDEj)#wkcUDeIaoe
zaJZD&+OzG_Hxh?)3UuUjXyBPpO|*UE57Vg#KLhEw$9D&QhL8pQB(vtjWi%eAfyn66
zoP*TJhaJKH_rs3+W!=s{u}|+6Iz4{)hoSe$we+x8ECx5Lt|q1g-!+AkegzuPwy
z7ilbdB?C&j>@@UR=xVSQhUEcm%ntcwJ9n;hgP@4D+7
zD|M>s$=b%o%6E_{$Uj+o{7@xvnWMafT_QO_sGeZn;I7AcAOy$GKFX5~@xyY+mUA8H
z?V6N@x|e#V+n%dtYLpM8x(|-|P2O?$#t-;f=tnn3*7V-bl0AS+OWWfa4r`Bwi3g(3
zn55C9mc5>gwfJc{xbp+B*^SdcTC*)gT$XEiypxxYYgDDi;v${O$Z1jWZ1m^iJ);G2
zaEm(e6LDBOV|!%}d_(WE?8iD4GcqZ;gV6|t3(n27l>_%NXcLd9ZVlo(ycc=f>kA~V
z_o0`b>MW5enLyjIX*MZHCXl_NviH36$w1vr*#As}B-w(vYmZ+c`AF*)Zz1{ksTT3x
z(E_C8=pGfx9>_zeOLE1hda`;`la9x;Nt#}xJ6@AwTL{gJ;vsO2j`1$PLZrW>OVE34
zd-&6h>-5CCdpD3KZF}mhqPMuliQ{6AU{u+@tYzr!`tiR}q9&w?R#+Iz1`&=|{Nyw)E&ta#_Fwn5j2dp5dmKM}H$
z5;9WV%>t1@o`<@{MY@WSgea$)lg|7_`>oojUV{S?Qf(MX!AF!N7cSTsuwP+qL&ENo
z)^UD?G!H%SKWRVis-%^pomw>3b4U;CLW|l~CJZM!`-KyAlKljZ#BzN61l6PjW8s
z(dt^*|A1{)@?o!hqAT1BzjH?=S%los8!l|E$+^zBvpV46zAX7ILT7+!z({eeKEYEs
zZlboe3zGHapQHtWN&~FB`4PpZkTnGFE&JNR@&5&m&%0Zv#PmBCw46=~<@Nd2W&c5c??IUr
zNFS~{0~%PHPX%6w{~qK+&}WfE5^vL{^&nmmx^<;-7OJOfupWnEby-~+jft>yw(>%L
z-GX!GI42^IKgIv^(+}Z)-K$>?IZ6DEkQcJ0JZ9<2x?7(iYbe{@FEcrzHHiBKnjhKh
z7_W(tzt#pBn#dKQx93_a*IXZ0>1jyx1I
zs5(n)>Z$z98RsN~ZTM@j34dq1n>WryUM2jh^Xqzgr_dWAo+}e?b^b6o%vz12ku$B(
z*xnHCliF`a)ZSR{a`1!3O&Qew8!8>O-`G((s>pVaDh_yth1!PhN_OTeOrAwocpZ7!
z2dO2SWQKitpl*6SwW{Ot*kNkd3B3*d$=TAWMR*g_9ce2xr~#l(oJSS_k1!qdzRo(@$PX{qi7Kt&4HB)6rja-ELO)O0Url(w3V&=csnSGI)SCv*l#vr~7T`|hXi
zIvl!-v#f=5IAxyg9(cmfG%_O_0?b4&qB4|S(pJ`2Poda4KW
zr*%r3S2(-uF!%s!zgACnr=efc+bcI)q>92HhNUEhA#3EzAHvh|JNN+2Y?5F_yt-j-
zC8b7q;!PwG)0iHx9@TIQ_6kKp&E-c~*(O|5
zn4EgGB+oLk@dl72jW!@R_NY>T3@_|3t`O)RLKK5i#@`rjo715neH`-n1F%5N5oB+G
z3cTwe#(zFM-^9z#0>`$X-B1JDaWbe+
z_ed5E*`6WCo~}Iq$oW9s;RX(r1(gGeY&!Hmd6|^&%cEV0(e_=%`1Yg(>pOL>JmUb}
z7Gobme67vy=TTQ#0W>k9`9Y&Dl9oE~317cS5u*OCA77bB*+J@VAzu*a>WPM0I=c5l
z=su#lvFV?|lfUx(txMAPp*KDG?Kiaz`BHBt=Fpz37t7D2d++szT8Irs*seT3_$c{e
zKCUBeXzo`OtI*#EQ)WeV#9s8YraRH*mwFre2YQU@HulN;Pd+x#Q$g}S`aTkUe;p&8
zjgcO7-&L(?w)y!M(uN$Cd{`%f$U5kcwu%nk<`sA;lVEA?qM*$d+A;Av%%9G{*Z6;a
zq7VP;R(|*B={_IHkDtA=ZekmHYaeRLP&K>r?>asui*@s<#-NUQR}XMlEn&88Lae-g
zzv&xMX~p)W*j&O;LNf+BC;qWYwF?^V=&%MKS&&AaO34hZtX?2*v9Bg%BapXW`BfyL
zV}^Q>feEtKgA3`-Z4b}&!Z%akN0bHGw`|We@T*HI;GLOA+BrBpydRRDRso&u{jfaz
ze?ha|hhBDGg;!kCi_sUPKiP9_-}*tLOp<0+&CtCqK+uyM0{J9KwleTQ|DsLD5XUsH
z%;l}SU@20OUK`TxNw%V|0>=4oG$w5o!ry}Z|FGP?)MwYl*eR^s+jsUf_3A$#Ri!P(
z%zE`3H%3?Tc#ZlY!?6Xvqfgp3i0LpUA@Mx-dtPw-9=@dW&mHlAzSR^~gT6(^CnItj
z9){6*7MwxEw!eSm3Nq>hj|-T5D9
z^!XC6G*(`r3G@GleJ**Vn#WRGZDm3S%@~Yid$zG{OIJJ1sJ2Z4w(t|aLEHDk+TO%C
zlLat$UbZ|Z^o}1(x@4!6t(XJsd!>eD>_xKgP1;X0t?aP;w*P$e&N-3pl;%V8;U8iw
zhy|XHm9KOjT$zhBR#Hv4ytSz>Q$&|ssa~1peGGJ~=$RVWcgNlsx$Z7PzmKb<`B!`l
zn8P{bxf1tv5h4})R%xFb18=%Layn@huxQ(Jr;+ACd(FRqly1-cg>9%t(VzCck>2+<
zyZ;-MFn5TNO`9iG;gqB3WUt&~buw3aYM%VgUqB%(e=kxp3`fxOvnv_DQef3(@A
zQ6@-wAnZATx{@}nX|$O*@xCH(m5tubt-sPAYUQ&_g{!p=C!Sm3Jd%b>8ft(UCfTB<*P!cjBbZ@
z3Nz+{Wio2rpTV8+6W6{J5rz!8b8n0orCz#9`3U(&sEumr322u?yIs_Zd>+zhLrbL|
zJ;hnAS)Mg|=7wvZfJn3Z_52>CHaT8>vLqJh*ro6=3CI{O$*O2kdT(d-BF_fjB9Ftr
z$g^I^_LM-j2Zlj6D~i$TFDme~!AXLTb6aX9S=H11;X6)%6A{3bci5`JltInO7qM@*@CRiuz83FxUC{)qK;65@
z7rzhHu)D(WzI9KyS4C7HjD_W+l--mt(|HRR<
z8`ab)1KY$(_xtrzC?77Y0gf)dcbKH%f8$j&9U0p!ue`_+4#bFU_ve{bMTRAk{dz_}
zB%G{KueaaG`tnFhb8l@*#+OGf)Jl?0-Pd;N@e5tV9V&c~G2ikdQ(k%aU;pAhG2Sf4
zmpZCvG2nl|>LsVv^klJZ&;IM$JZsxyJ=gNg$nROoJWRh{dv`@Z-1&2s#^l!b+a=tH
z3cgADg@k;8H8BY-B&|UUzy055A=lL%(OlX3AAYpX}$YGeg#N{I`a&Z9-0#
z>NLidSIEr;UJ>7ro2cc^xR@_cT_*xIC7z+^lP+eiyTdiV7F#)u!&bMpS|#XFRYWt^FOX91d4wmVqx0b}X!x;v00FHA$=c!T>AuBF|t@
z7+4NG*RD-xXHI$qd9EVXMP2wUG(N-!`8oG7U#0ta&koP`NsOo9`&%SSkp5>oeaRuzhn*-MGotdQR8Z<@f2k~4);pB6D5nU8x?>9h(_=#97>H`PpnH)U?R5QNc
zHu8@{sjno2TIbyV?(17{?mHrd$_`Qs)SJqg{Ueb2$D;Wb=>$0*jbeVoi*!P_6m3EX
z1l!U}VUC4P#`ay5hRfQG*r=ZA7O(B>MZ{ILR`#ym4h|rsJPU2V)quzhmd?_dP;?di
zM)0>y3M7+;t}Fy1TaHhoKDe?WW*PkWXKSI?R!b3YboQru=*oZUA$+sk6Yp&8>j_}}
z)D$t*wk_<7Wi`r~SN}B0JmF72wJt)`LO%=AlJ@tp6s5c0WaIeZkp06@J
zg5l<;F#%&D>-J^tKn%1BQ82ZnwNF!qqHb}wWrb{EDfBHuoNLF6i2Z}VXaVx#z`6n+
zgt*OiM76=XP5q9M07vQ<%}4VJ_IR!fS`-iM2EH9g$3&qj>heqTmP7*4O=+wHApjm1cs7^dP-rd%5{RdF0U-kSTQ7U`xOVmQ|T|}vV%>r%M
z{KVd6wH*8%GNp>|N2zi^sp8qTe|~e5?mN{(l$Gd;0yQu~R0VnOGl{BDj@^7dkZYg5
z_fCGICVs-2D~@qz;?*)Y8OU+0D!QZMm{?Z()7SaF7JQnYY9St3XQUS147DIx9g&HO
zW-``Gg4=pgvQA#v3Rx)YBC=uJdB;v==pL-vQ~&O+ef{q`jJq%ceyY8k#5}9c5yhm=
z9Pf2ozPG!ZuG)91C>Di$ur6TzgK9g(suD*W5rI-yF@rkOuTKI=xZS0!?6Ud_1{pvfn$M0%M-{`H1R6)jZ<|O%$ML9>;t&H?^D-B7<
zt}>pctG9IYhniOu&!kQEC2EuYcZ%oQSVs5KOeRA02I770;#N)U{~qz@w4Z`cDu#g_o!u$g-OiLFZqLmKMX|Hy($mO^NAXNaPmf?vmLx4#v7Xgt#DvATPH#9~G9S6;
z^bBbPV%SY}RoFl9t%LD?tH$EmSsLB);gNYKd$&{^6^mNc
zYqyR(R#oK3uhsaqxW%XbYp|l^s?q&hvVJPHbRyJa(wr>xC1}l8E2&={)z!bDY{=`q
z^nX<(FG+QBKAe*SWZGZW50q-Fn@C;6Z3TSs>-Q}rw8jm6@#{BUH?<(XLE&vBJ+QjLHXNuZAMNLOqQ8`|
z-FC(@4sy7T+F3GbD&$&a7fG%`sW{{%rCF(iRWiw09ij^pBujjdHe8h`!ygV$GN0?W
z5(Y|Og@2+inotkxK-j_a9%QtU-`c#exa7Wt^q$2fwK7JuB)dg^=bR5U9r7DnUz6YX
z0pzo-n~Iz;@UYT5Ur7L+$2*hcCd=_5DSp3+Dr%{u+LGT77&ZR^dJ|2P1AVKs!Ux5`
z!@R-ItSXhq=MBj4G)8i7d?#Ui_G0Yg^>iM?kU>`0J;6XPmWpERu82vno&=Wc
zzn`uY`;=DE>1W995ktD!l1U>+zAf4EHivA18tD!PBpqr8x{5tgAe-?istDEm$R7vJ
zn;+9M>(<*}>P!yuBdXpv_w0htxb*7Ip=No7
z#BN+y?8!ppzjrJ9i;|=@Ioz}g`3mNt8rUGCZn&PQQSC9_*kJ2E!we~2S3Km%V_td&
zZ1j9pL5`C4KR?D=-M-6qZV%3%)f)>0Pxk_)r>FY*)JT!<6T)S
z?E#<3hcvD}pQ>WfKW9BTTk@a2_egzlE!|m#u{&KG?2kfiL$&GqAUz}A$AHIQv~y#f
zcRqVFJ^PyU?3|liyfY&D;RD`i;P{;~I+R~kO4N;JsklW*7rlaIh*f;cZxY`UEMloJ
zQ{0NbZTQ=czc=ys7XC_cXBqz9z@GvKLtMA(fqm{%ZbNBCO8a#
zzEQlZC*6@%xcJ6!Sgmj#F%83d76?>;QjFXg
zD|}Z8U%_X8`)=S!xU2t?aVV74IU_evxgn6f(9v2b*GZ||@XzdplH7bg;gUF>R}h7Y
z``C+j^yJt7Hue*{QLa^rS*`FM??v{&%gIxW$Q7*Y;>&W#qT%qtYYjX0WoUQHC5=qZ
z4kHflS?p-FFoaYRM_?b{9{OV1hQ7G(Yhgv_)@6xE)=uSF3nl`uZ|R*SL4UyV0|WzZ3ddYXAT5
zH^}XLrERG4@AM8Iee{|!kb8cyH~IQeu~NvG|54gWiXl~f<(2TuzWWKuC(qQ;bH%$@
zW?EC3by{Q@%%RN0ZQck?L
z$8u#2MF=^v{AP!F7cb8tTX_RhhWIjEH({1whLXL8sKt8wydWYp?kEt2EXCt~;IM7?
zW2|@B{vFa*3#6?~@zw$9+lMfjevH)sY{w|(y
z82x_zF`=nKdE<~-J3mnQR?m1BQR_NrI(0vndbGNFs*O{^s!@kZNU(w}iJ24Z*Y9D)
zmR4fgE%}W95+WV23Tf_Q-b;}V9>Fj-yD6}w?rG%FEp+&fGa|oB;aZN!6iGMWTK$$A
z!^1T+OCH}U%@wcTLT7brkKdx>)g@x^%!L=}7<0BKbRThe&YJbvd?|aFxXEu>VHG#~
zEue)a&_Wa1F?$=)Cyg(5xevxk88`5I`EJlqP|~gbbVMMis=eCU;rvczoZu{)Q?gGr
zzl3rv#PRb>#0sB9dfqm_Nv=R!FotVYF=8pbXB;Dz(bmFRe%oQY$T
ze7wzXaWuZbaK5LQovL#i#Oq6+2y#h|URqb2P6KpGX2+2G$)bcfmgE_s9T
zUtVXs^ilPa9X2=jRfn~mQ(A1Rx)q400`=%O1HJGItGj>b!$~^VR`)ss+FBjOp
zOdT^uHS#$19OxBDB9HVt8!{);mvOBf(kg#`YZ~ZHhsA;8FeTCR@3tPt
znQq)mPp|E`+3FE;W_k(^)$ZG*Q{|+MD%SeC?QZi`JFR+cYy5+4n|(Le6Rtdxq-Om?
z7#q#;j@U1`(Wr0mh3cz?nMBPY@h=6!)|}75;;cWQ{BYxq;t?&gTcXU6ww}Ztl$Ro-
zd=WfZu*4*NV{8IvKf0jmOl@@n)ZmktVZ4&Is&GN
zX)!*{WM?@|8%xTT_aZBf{x?a75OZ%qjGed9NcjP!kuB{`k*T=#UhvC@Wj+br3MhZ@
z%2~uKiBDF`xeO_T0=T8T0(_Mskna0Y^Od-z5mH#WqCdi(Bu_&55@#`FkggXf{oUE%
zoIRs9A~UfK*od*<8L--`ezjE2J@j_>FKG=&LCafdH_j)CGwvwWDGbt>(+e|E%}8-0
z%Uch5Fu#41P3Tc`$EUD?j4RKDyK00n?9w%mYdQGBf^m!4nbFWE-{+2;;6OQm4JJ%2
zckTrBx#1Cdhk?)Ud+R{y;uC?4=U2dz$RUE26C-%!C#YF-Rq>&BMCJiO#$J;zExYbU
zR(4Bti=&?2WZv>{*S>P(H1F!-FrJZreO-($hYTrGCq){*E!U6>nKHL-<^8=OZxZRX
z{qE?T{`ZHD6TNU$TaR+SY7S_SVLi;s&col_fn3d)_XI^i>Kou6HD4{*SH8!4C(fgf
zF5dfX|A>-4j}_&$09_y49c^p#!RAc=y_m%w*NP7Vm5*F??9w1=@ko=#9H?A*&=#&7
zrk{;DK4{SUj&$TBK$dQuc30LLVcO%*>frZ=91rFy@a60nqIQ?x(-`B;xi%gQbO
zZjUx)kes0bEpKEWEBM>SUnm0^L&QMksW)F?SgS|%0;5wug^IM2wb@WQy%scqYxPZY
zoUNXAz&bmO!cSzFAZla2t_d)XHIdKFu72jwE
zIZYIf)_fqDX=|c9@Yp`ZAP+pQ?_y{LS5c*z!uOe~2s&5KAXfzLX=i}c2VIG7$!-Z4
za(~V#TR3_3<&1Zl*L&r+h<`*|tLNQ^;?+ApBmssjs>nQCO%_ttto$e>1BUE&
zdgP*qjPueY6DqBmc5_4OK|5Gvdo@j}gas?NaxqZyZw2jlpn!5kVd?3mg(<=JGbRh?
zZ^`dxpd4M5-9~Vs@T-bvVcQ*Lmbgc5=X3heB=NLAPu#=s>H#D14mmP!9?<;Y5#xyK
zUS0_VFC$wQIbRQ96(K|Rr>wWG2QmK{`?d18)+YU*kx;qzVVaBd1lY0^{b_f9JOL;v
z(|y-?c$=Ce&r+E
zlQFNLaU$0c;Y~k)gq(xC^{rDjo^oW3=Av5y85e%%5jv+Qtp@VY3SJe)D?m|D-`icj
zOOXugEwYlmPLcGcx=|RHjD@bs=*%SN=v3|fQNOX>tPTU}2fs9NN~`U4f0)Z+D{du(
zB&2U@tz9w7d_-yw7RpTdnRJET%liQML_yr@19C-^Q9aY>N|^)F*0d3sK?*gB)-P#>
z@P#Y5vlb>P84?N5dTxD(ar2DqCRkIr9z~|nqt`RZz*KG|WF>N1TrIKXbR!Fozzh*q
zlP(PVXT~dSk;;Em3B2OMN3eVw)h$t1%WCPHk)2%Oz}n-`E2GSap@uiKRP1
zowF^*I&;#hH{NT)INg>ymSimL)AuC#SX!xRux?|eO3|%-l89}S5I4Svc!eEagv!a|
z^C4}F4wT;eola%v@_?7|{tWZY{j*82PVU6rOduom;b70#h4@BcyUaI$vFqY|R@U(`
z&?=I3qMh!a4f$+K1x2<-dahsRYQDLSi0n+{U_i|HlqD>3`C=uEXG8(ptaL`=E?LhY
zUnTgnbqf>S0)!q`gcwHGp8>uqox#jV>w(UKXnaXdqq#`D2^KwreSyQ0$!VS;eu7Ar
z7(KS|Q5f=OvNPifywDO+zr&zYhCLrJ)V)BoQ714D!Ah}MCm1x~CW}Ftu^;xl_$KzZ
z2#akhEzh-DpSbcOBJEenwgl&LU4d$IP>bK8
zDj}i3N;lBPPwVZcxtuvn=5kjRcW}8Sux)p~wehF8oWz}teSFRyrP(@?HSjGIbVYbn%oR7XV}csp
zButL$BC4W|XhkJ8r=YvuGnh4fR;ab+?X)fLQSC=$aFb-LzkHaigss0r`L$3ZBe_dpf*(%1$ifkdXy^T$i`;KI9
zEUBK-o3okpGRU-Vt8hi>EqvjXna-_^%0@pWQ?<5c8W~
z93Ns%J*@wLau1~yIM4={UV(PzEe>~mRxx*=FF?vn0)F~*%n^rm1zVNR^IY0mVEv(0
zNp0tx1BEn}Jr?d7UqKoTDip5mR;fC(Z6k5{XdXg!8NQw>+kM^CnJvN17~gB
zN4!;zU8TspVmE9OkSrdl46mehO%a{Y5|w!pK0uD&L!=(0Y-H9nBkM4tu06u#$!=>`
zrT+Kmb?vv$ku+|z3(>l;6^QmT0cqDd#rB$TmnRHy)7H!#Bds^wwo?CHwUP{~QzBba
zvBT#EHGGM_KRp9-NwDt`nab55pW~O=;x@$JIJbd&ou6&HTRDtc
z)d`veo$7c3QMNo#ws^#QXU5PtdJ6qp9LSQrban4)_kwoR$cSfj!nlMRQSy-$M`;PP
z&-vn6N24Bo3Se_oD-yI>EjR~RsWCZt&Ly35__A1?us6Y@x;&xSO`Jx~mflkNJZyIK
z2ED+Tv>3FA7q?MoxrBa4XI(jT?%5Lg4E2f3V}htf^oBedcsr>Eq&v$L
zgGz8x>?bU<*p7~YpDw?Pf4s(F{WZ&({)?s2kk>->+tPT9!&)d0u7wx6xW`}LhSA7p
zfsPTqD)e%1K&_np@#B
z`?9rArj~M}!?#DtHN41|wXriDzD>O2Z40yem_*x#dL<8R;h(29emO(rcPPd;Piy)z
zUDAgTskMidG$E>uL$+k}6>@;2knXeBO8ODmli{C*mEMebaMkCgc9R
zA;zQTP)#T*M#r@w%4Jz)t(v`dV+74V$~~;hv7&~zsE5SDMG_Iff==OWS8=+HmO#FN?eGMX73~pZoC=X#Ygig%y
z)&|3}gFrv(C4cvmu*pS{-DTO*piM5r@EmM%bajWYM7GI=bU4^WFavb_uEo(t=<_3F
zJ6s)XoaeLEb)b$TKmomsaXci?I%OVVhm0}L$)gxw7SgD!e}P6N&Ft!XX=aDCDUuDj
ztm@SZo5*6s9bW_fllmg@5US}pkca3r`HGPiDXP-QBE$VK)}!3Tr#pcR=C_%mKX>s
zaG-+eveYW1v%z|atJ6^l`nQ3|_wEUF4o0q`_mu|s;*KR~TyWuG6)0M+RgAuKxEPUjjfke@XXwNkQnylT0IFXLItB2BIK4+e2h$TVfdds5#KN
zGH|C3;;^h9u%6))?rGgg-dJUY)oqyOAX6f0eq0kHH%zPC5cxx||6L9xX+ggLuh^
z7NRyJmFf^#PSPX2g{;%bb)WYvCKn9x`a88oJeNF=^bBNH02kI308NXtOJb=J&NBl!Dar0{oxW`Y
z1O??r*N5Ftb}(*sDrafo{y_ZB?jIym%AC|tZnYzd$x^=u92Bv1@sOkR)^{Z0)U#r?4BA#|tky9cLupytH}?
zR1@7X1XzZLO~K6m(3aYa|(&AC3aY|(%amcgb*x!pN@E4ds;-ufumnId4@@ODW
zMgj63+}sz;NDuf1G-!a*s+`baKOZ
z(DQoCP?9%BCy4MOPNbyq(gczAZHMTjRf9zjBwSc6<#U-ynMNfmMB~}@CpXZ_li$E+
z@X%VzfEJCoT6v2#B^_5o#-;P1s?rwpVLlxTq5Fc{oZz-FxUCLueZj3?-WEdp≫G
zP3S}krzy#m`R9-geJ_&RNm?;wHs*Yn$yW_rX#ZY+BOTr&tf}c=I()sD5iZh%^ZcqG
zuVyZ7H;ei4TUj>rZuzk;yxB-vFc7OOILI+M2j!hllh*G>{a(_IUFBT*Zq||Bi+0O?
z6Yg5D<(C6=W4XOp=bbGEGU`^3Iqk3>XRAsy60(gmokJV*p5AOE`CXwAFqdT%a^}{UN2lsOO;KO%`vHKXu$6cIQ!YgdAg+W(u
z+jRX0&inXCCMXfo3iu)
z`{4gpnm5*N&SZ2c#QO
zj&Btnp?)%?TxjQ@3)aHQ$)-@AwJ?6v>$Q^pz3%mZedP|DVo;d8>c3S;Jd`rISbCtn
zeoPr2rn@(FqctXeV~Onxf$<9Dw6^vc177R}zag
ztX%+Vdq0nQhI=N^nn%u^3AzP5GUl`z#Bv}4q&G?8?Z)ueND2^N1J3yE(HwLzW27$c
zAZuc0?>$V_zV%*;c+Yu8;%S}lUWz&xu$OF0i+Ke?L>-dhg%Oroe@u&ahQ&1Xds;L!mbQyL+cYErs4uEo}B)MFflU
z;oD~<2*vc&521~n98(O>bn$@M@bD02j@6kFOa=SK2y+}BuT8~VF<>lQyU{P#bG?-
zuIR;FmA$Iu1ChAI**)80;r}SQ)BllCH+JNABn?wcj^zF5XH_FfYLfY{Kh`{yq-iSu
zOV&It${zkc%_GCUgoWnu?#&--9%neLBGn2D*%D}-k=&;}+dq=Wp}
zTOtm=s(7>(TB}N?unwz|D?8@0>S1+&USpWrxG+^zUQxJmrZz21^Arl5DSTFbc#@4sLsZHMltnzycO2WQX9)-E=%~7r_@T!p_aK
zy(#=4A2*1Bj5qV2Jsey=cXP+}%zosBfZaPWbyc|QGRZ2A4@d}
zhU7pyN8AV2r!n#s*_YRs6@aj@T!X+|Ko$sFI4}c#9|JGnQKcC*82&EVk%7^qk#SU8
z=T-m-7s!394zoA+iKcbH;n6se=kG?Xj%7a*6DFm4H6-b}W)U?O0G!{9hAQ*9lf_$g)!X
zzf>zgV7PR|MoQEqSlwY;b`z~|^v_aImMvvDx|gqWNzah4+Qd?vIdEjKR}Vw%KO!qz
z^~{Hb6-PZnp`r@sYxRtp#u+QXE{^S)?Xa{cJl+C^s?7mEJ054y0=)}o6%>@Yl=7c!zKGe|v_`Dg<9fN7`uOqE|?OuXnQKF-?G{_da-f?+bc?6CA!w
zP{z@WEzmvG3rXEmu-xx%=(fxIahH%CGPvJyN!u9O-*egB*u9fRuj)0QBI!_vgn`up
z0}E`tLVT@SA-ZZ6oR#PBE&84avVI)N0siPo#J4Co%P`KPx3Zon73_JZONPRtE$-}o
zl6uZoCPdQuhtzKzF+*PcN1&&U06!LH{&5ysx<;5>Y}NBi{wPHv!b?6`^azueu7U3z
znE-PXh+B}po3pkkVg
z;V;-KwMjO(epV)9b6S6Y_h0wPb(QkWHx9Zi$fd&BqFWJTm&Lq+FH6md!GG!jwpN+*
z4)#gPlg9hrp8F=%Dwk=at}1lO`^!l3`a`YcY3YVdPQpn9-g~FerdEy+hwYMRJz|UZWc-wY?r&R{K@60K)*1qU;lNIm~R!z!@lv!lgkgJiV
zoZy^Kfj^xWhq0o{*=uW|i^%{O_ar!TJca1-kv$2if8rWY{{Ruh
zkKd8iB^2@L1uudhw0Bb4@jC8!m%=6h!)mp0y9
z>zJ9q991V>e4BC1oW}f3U32Mepnpuzgs6sTm0kD0uQ8%MimkFQgG8?TUp4Fb{54k0
zTgFu7MX}=g-ORj?J-DB0tr9m*;trxE9pg41wC_Y~e`FkHkvXcYxrAq#lbF9LYc58y
z9(6uL-U{v9s63ClT-s0KqFDFLs65WByZvtXW$@jSm@2lB4Zh!*G4O`(K@8k*R(EDM
zgEwN1=T*@e_7Ko&!`bbh>QwJDWPPC;c1g|##@*0h=PXgojK*p8v8vO>oMjC2fOG26
z8PI$tfBGABxFuki_sHa#JFP>l>?x0`UCKX0HD%qFv-a&pBGbxjJfRcXnOdA9t6x$<
z2ZLPfb_b#pD5i##zTO6uIV(7ou(T0`?iL18)pTk@`|@qVhCTrM$u@8d+9Oka$4
zzK>A~gu8Lf%wrvvGM2OKU^(-CmYaEmwE2{CExiM@(gznMbF*W~4V5`)pSyhDRs~4E0=e}Ycb5mJS
zbA;8sIgFuS(Qm47%*~yL-?&~2{YnfwjeD2km$&Zx0*>>jy-Ky^g6Bf*K>(=1??d$H-T6^r;1|cs=)oFAJr49PR^lva?obvct%u$=KM
zC}gUbv)BskQisT%#d_{wk_CZDdg&6Z;Cja4i^tepLL8J%Xkcn`u1S2*ot4AXsB)N8
zrLMJ*IpPrWy749*cs`Z~XjF}`jL~L*8rk*idi!ojcD1~;LVbJe#a3k@+4GcACUrN?
zcnY&_P&M>v&h>WSYy_vZ?QY-AzUxjstsGBnJkxtP&w5$L=tz1L?^Q#O8Ut&V{Xy`E
zL05UDIgl7B3^FdYki|f!-0cM(>#l&|N?6~yi#TVF4jA@pWa&LVNsk)j@R*jvgUZbV
z_k`A!*a?jtTGt+-G^BMs`#hxe$O#rNbP}{Wdtd%clH(&G$43SXr-6VvA3=72D-51@
zk9^ne9B2fI%_(_i+Gb4mqACTR-bL?eTobg56m0+GX%ld@iSG@UtRFjtBDIlim=_gT
za?>?4xVPA)mvrZbLRjw-BZtwGmShAHb2FhCj6!xy>3c8cfq(0rIj{pT$F0DcLV~Wm
zH@m4;KNR+U!5;mI(<(-EF~#7>kVAB+wFh)g?ImRTQ;f6R$f9cBa!bk*AW}zw{tg`n
z+j{7%vjpuAaagAeBR=iPAAN5I)twir*sft0vZ~lC%r^MLCovlI;*bX9VKAItQpN5-
zU7blxo_UB;x4PlpK%(L0r|U-^=PZ+$*|;O-d53ip^Aaja_AnQ$avORTjfmxCYHJSK
z8hMhw9*CE<$O7@wm&V}rmoAv;D)ew}!0%q7-_b}$os=vy_XQHq|5o1xy1>`3QrD4X
zMjoGKGlA`k3K%XtE!n1W-+LAFXxLTgNrornCpuq2_R1XAN|_A3cn6Pj*(>sui!b9{
zMnWQrghUhxi70X&IENQ+4t-(;*H{2+=nivIR<}{<)?MuxJjCY|+A3;qvWOT|T5FJl
z_jHMv-_2vz3&@`XdWPEE=lu#j<{fmpWln32w;DZH$a{P}w=S26d=KuWSqU_e4Hi0X
zh}D+c%5%O}&S|mT)2hg`I2y9}Ar{-qhZwFghmcdsZiQ3A*?HDPF&dZK+dYGA_>lD9
z!L;5W!&|S^IxXKJpE&eBoV{>3uL1EAcI5f7+PYi{Uw(`w
z)(Iq>Vd;E4V`CRDf3@l{hp&+|AjV16*sFzTLOyc74uwjf`t0&iw<1g!a{K74B0`7>
z9`)JV|)0
z+;M#WBUC>mbk#X0xHsQCo8A;&EJ?T5q^CEHcX7Lq^KzD`g!}{fpfic0eHZhPCC?12
zi6Qmzoz6V?u5$-JWU-w;ggnB~|GvD)aMj0ot+m$fRBE$&8O)S7d^h|28GUcsfH+c#
zZuyeoA!9gsPL4@)`Q%YD4_j$q5s3*Y+NU=y4bIu!=Fs(qNL-&9ygmah@Nx^v^w1q+
zbSn)Pl2eDo9o?5ty#b`dY!zZIk?e_v2B|$5HNCVB3e5>ld9`;u
z9I#hT3q3{oFg<1Igji?j%*7cvzOUQ3+;rA71|#b}=uAl+l4{92E`Q<0>C*GZ=Me_e
zaKuDUs|Br4^{@>oTnu*ZYU9OkA?^|55htaZO!W|L{IJISCk$U__*YRf(eI*V0yMecDfJ
zgXRKWv5&Vp_F_-1)oHa(r_=Fyh89c?7$YK$8fm?Pf~7Ow(wdphSVVz%#Y;uhsfvw=
zwkl`^yaDfbof8B*&&=~ae<(ZW?7h$0Yp=cb+H0@N!i<5zUbIH)1*b0ly&&}_g0>W$
zkRP(@Ho;|SDH2yz!!M>q^Zm#?|4wOPHfU>wU*SSClOxwy6SKer^_do$RNh&6Wr^3tEuFt2y9FCaI_@uWOQHZf%eeMb+rGd8hMxW4UK(U
zy4Fa@CYel`l|f;Nk`Wn3d0RC0vchb5{WrdJt7~mK6<{RU`z>O9Gn2oX+uSYF^1K9V
z*Bf1H@>-l9H0y;eS#IqtHF0CKfoBqZ$(UQO$+SF+Hm_gr+NMkIo*Je1oMyGsdnv5U
zJIB?fW)P0TjAoTmv+tE()^t7uabZ?-n^NFpMMa?&Z@SX0cS(0V1(Xix5MC{0_Z%dRkm2@73
zy?UGYLxtJ^-RFKwpG*9yc=lqnL36u}-iq`5h!?8mh|XYF^pg=gx4kAFGyp#>+|jmw
z*U|fa%VF?@ge*WaMZ<(yi4tzq+hn~GeW9)zJ28D>`w#roc;*g)uLZtA@5L*pRARlB
zSN74YI^*hQ#!rrimIoTwHI<0X2^ho{l}sOtwHGsSOY+H~j_<-N13D7p(q>i%ZFOBK
z;E-=#>{tQS%IvlT>2Xzat%8$v`#M^amfAj9V1Fi=aFiii(@ZDn#4MuXdW9m_)_jkc
z<(TQ0DjsU}&-A{u`Ao3?JrC6cB(yHv&D!?7OY+KC+k8r?*CEy=h9qR#4rC%{ex7mP_9dT&)xj5>#p7R
zaNRAN9R1=w8s#l6D^9t;8&)tr|SEA??vU
zU)YS0L8+YqcU}gydfT6EM!m$0hC1{@W4gYkb44gv%j@#>wq5ic8FMw-z0^;`8&#im
zeDi;(|4nE8`qE&1&%^b*&Pto_L4Chx7tIX%U;c3YuCvniRY!g7d_H7OP!+N|oGn{a
z$_#bSd$?`aZw=qx(H3V>pYpBlOaE1U>|kk+ZlPS7?(9J?Cpb=xCViu1QF#j4MqnR4
zzSx1fFa9O=x_w{#Xws=
zxQVdrc&-`bpuVXs;QvQQ{fA|(C|TlbNK3reMb=9D_!My@Wj7UUi4N=mb6Ql&j$8*J
z^3I+@q2*&(v;N*ApM^KMl=DDPf^{~$v23uiXXpOVxyI-$LDC_~1%hphqrxIe^(r}|
z@REA$hk3~3rpA6s{TqdrKRmrY9Q#{t-ge8(YDoEwN96tgQ*(!e10OB4xC%+A48h*H%Yz+(J*4LFfrR#MV!#hu1cC_MmwFCOS$aT}9L?&WC2iOpamI+fi~3%>_LuECxdq{2?zgn&;Ukza
z7u-u}^V;W~ZGO29vATcLg8DfD-lArt;b_Q6gtt7cx!fXZ*RkdrGR7eXZmlZ)*lAh+
z8owvep{Yc~KmF1FIBY{dH;SP@ERv#|KIbc4Pu2|7>sc|u2-w&iaMPZ+u^6)^zDfqT5i(lQx_>+U!5D&?yie@WM
zd&RfkQeBFZNZRoGSAsT2i4OZD3+zjX2M%vi@IF4jD=vu7@fLyQD17cxF%z8Fdwy2x
z=C15omna5$inLFz$}tHVw?f)^m`*zRu)JP3fwJfXo%YFPnz^=xo%I*Y@62XT95LLs
z#feB>-6dCoQ{iilft&o;wSh~wG;|QOsQL?!+NWG(&^PzI0b5lyXN<3@_rS+^%I&p>LNZO>Poh+aVEh{ZR3-fyGlDKep!&>X&yi$pVD~ko1{mG
zJ7h!%g7a{L{zg~_FQ~$v-+^)PFMZkIv+$zm@EO%qZE+?zJ=hi8j*XEG`WXwZnvpMk
zKlKEyo4)L0Xdn(>HaGNpqaW;RBi!1I2=P`nGpI8V>%t8D%+GJ=w_bm_e2pb^{{bm3
zt3kg(d*2K_$kA*D$ZOX%b!y|t`k1V8N1al*ZpYkH%uw>YfBD4Zg~dkSaY`7B<7#`;=}^>GH6+5GU_E&rL;1-?MHN$t>_VxLI$?Z*l8x%uNxmdHC!2M40K
z0u-0c?-J$=QF
zTH~Y`t8Rs@|Kr35+5Fj$U5Ize&$CWjbSrKB?Zu;jDM7Q)6Mk5Mj@DY@p@(s!`n7@`
zUH*XN;Fwmubte!TdUp+U-z0flX`x;v%0AC>e6P+wuv?ft?p$J4iBpkEL-hsaS(Qb5
zI`SDdn9kL2uo-(`bdUh-ewy90fmT@(RxlnMFRbQhj(<727wc$_K~?PO=}%k`W}dZ9
zl6Sv>`UcbRA4(kbmPVZSI<%J-g9NVzb_@|4DBlctb6WRr5p_;J&440$C=^lk_kYfy
z$XRA|QpK79Ef*B3(9kZS&|>sGP=@Z{Lf9SarO`4)A`4jILlhZ)O@R+IX?pEciL(Q`
z?UNMf767^%^TtWWj0K2SH|{HfO@S+jZIAihUrYDP*vZH4(ZNd-@5!9Dmd^hjE1N?+
zS(3Xxt{Y;(DzAO%+nd-0Xtj}Cn&@zn<|l2-b*1I&fA4Imyw6eIUk$$hrt>{Xd&)Za
z;s~tpdEy+Js&SPGjx7!ec@JMv=N~Kpy(v4`q+_7B5t1dmEDm}Q+7F++y=#5RgZC9x
zcyF5Blxf*yJK%KXH}w;2h)v6j+4ZVx@_i*ok~2d**euGM4!Sgbe5g~-+aX6WvkyvT
z72hG7XV!L`7}dn$vobBGOCgCZy`$nR$7BgLxOTyv|2LSUDnU=f6qubd%net&!Yu8@
z`=S3gn1`4BGt8kf%nf({XPAjIkf$(l0pbX}Z6;((>~I(Adj|P4Gyvs1^utc^hkD$9
zOjN^@p{-sWgJ|>$_CNe9Xg{HUonVRF+=+9^2lyYGamO7cF~TWXwv5Xnsyw$dQ{G)7
zb^zLkVz3ZbaKoM#*>>~?+dp++3AAxK+`BB&vQ2W!d0RN-G!V?l3R*tUR)pK8
zi~Wqb#j5v?5mbX|{l&v#5O&sPt}rZn~_ai^p;scVg
z`(609CP@x_cS7HjlCfX_CqTx@2j7kRUXc;Zh1lnL!gU9xak6s4maIo4VfMdUSSRM{
z3W3k4#}E;5q8gZR)a!9`IJ*U!Y$x6FU9a!X+xA0)2s!RbJtJvgg)9xM*sEYCcQt1z
zTi<1V)}cTB>>GcEo)J5KZNs*X{hn|(zq$iwc?LwzLR2HdSzZulUmyzNFLCB|C^#c{
zy5OtZav5K4hk`E;FbaLZW|zOd!1yb|UpYs(gAB8i@TOqxfRrRGr}@&2lYqH?131W%
z%l;?2*lvjeP6fz|B!SQwjknc*>V!17-9k~`8n!*TvPAOGnbf6Sh80{pzNwR+bZwQL
zD|Kmg0!fy}Gol$sFC-S28b6rDQk{Z!DZYuthbI`elh;thWUbz)9`$KGLowj<*D
zBP1&hkZI4@o62fLog%zBm{Etn{jKTgpZ4zt4-NsY(Pn0<|BUMOGYL*a
zMD8*wVUaSb?YuIo(rdpQ6-flqS4f7s@*BH#KTp|>i}w6;e&Z+`e3VvSf;4=Z=YHa>
zFq9WE-e@pw`AM?bt*@w~5HsnLp0~|bi!oX~XLSpDy;5W870ya|4VJy%V5+*@kQPyx
zuo$_9|6bzsbz}O5_Y=33{U-d~1XrdxXH4rOZkKMoA?$u%LwJS3aN-%0&hN}{w<5A=
z^R0-aDZXUEH6t);Id9u&AR7W7NA?4Ea^dyf13R*|Q5{%$>wa_{#v@3-ZD8A`AGV2C
ziq#X$&<=E~RZF8nmo%`lk6~@46@OO(%fqO9hRH)&l6F6{TZ;{SoZgxuWKM84AftVT
zx2727e1Fo45;iHv7+#ET1j-!ug||CzE*tdv0skzW#7+Nny6V-NV-+bSuuR)XnPiQ*
z+INnXBDd}Pi3LNfk%x7*&&^3%WHd)kKymg}wadDOrB4ZzUApPjIAL4xc8{3FNmKl$
za92R($;h$r%ZMzSqe6i-H(|EkaInkHfokX=@n8%To3$
z%{fJO=PLy^Ff|%<4119=Nt$>*6k02%l;&tF~*ctH{J9_7iiWeH`Km
z@ccbtu?rfKF(&9p*oEg_#=f~WKSlof(!KK63$(*ieIe%L(*)7DJ@T^>?F(4Pa=cpI
z%0d0%;|mSa+dRfwzsV=q0{K^(`2$hR_$XFi1jj_yO@-ZDceh)JN#uo|)YFz-a!(ty
z|B>g5lFx&@AJMqwF&4s(gRj6Z$rUxQKWuB@`OtQtr)fhaEJBpbR`3{qfZ7Y1S;^WZ(P;(2Z|FxlpySsIwyb>_~)
zd$nUO$zG-P>*=N|=YKgbiG?Lj-L$Cx;Ts$Jj+0*XrI-R*p_cHN_(hOL;+p@HPjxl6NYrl2lektp$cv0SjnE1GzF3%{!kxAngX=H
zUyl``@SqisBtn|b)ZMgL4tK?3lr0W8C;dSu9tB$=e#>9OTo?q<3+o?F^w5=p&J`6Q
ze~y0@XB)nouN=Va6?Ecszz%ZkQhUWSjNkV=STw@^xn9e`>UiIBSWB5BHx)ap>*-cBICPWKiiUf42AI&r*6Idbz
zmT0e&ER`qAQh^oP>!e#5tcPuqYWRtuZITKZxbFs{g{xhylhSu_561?RchmuDj9aKU
zlIT$OB4?}zdy?C^zi;$^fm3x$=wCoN=9wvd!jqp0VS*4t7KAC_COBLAEga-r@{H!&(yEzB&lhIY`^
zQ^Rl5`4rd&FG2ec$@3mNkF*gt;mdx9Sgowkehae3Muup66eEvLtfuS7JGCcqqm&aJ
z^=r`dlXbE<`98JwrqVO%aT^+s&gzCtx
zG|&~Av^P4TS@wDdG|xdw4cfpQZGUj@pBx!oO}n_Io+Q|^1UdhA@vKV;j?DTpN1XvATaluavL@lA{0<2gZ++QlE@C2F6Xu-Zf|5kH+BeL3=>mU5(JxvgB1
zJ=^Gxp~F8Y2*>&DaS9B@=cuRt=;^6(a#R}JigozXc7;gkmvjQ)P~Do?f+)h6*j}ts
zJm@^Kz3iqYf+@|c{1R@+V;iabs%W9FEE}OfFt8@4pHh;lHw@lk3c^*L%zd%m*iT?%
z$`)qCCa-89Jwx0f1=jlSN~FB{gi7k?=u0~+9|W_=DQ$)0dHpC}HPJ8WAr@v(KgKx9
z2^m(Fn4M{B?Ir$L!zhlSH@lkYj#itd<10xaerD{a#i|;SUEzyO&Z`eA8&hUnPwl2B
zFWFmNsys_8GxpPTeHIu~wz@1#hBME{nxKfey@G?p6^Ep7IC?co!UciIvl+pQ_=*Ld?2lCRdVk=%Ls~8A1u<{mCfx)<@$F(&sN7Dd7i%k2!~EgQ
zn_XctXj}d&zC#g*GlqMiyFm^;*2glBrS%nCE7-86jYE-VSSu_GglJp$jTpXS-Wyc`
zU(3d!xZ_(^0S~5>5Y0*4FPx)%@~{osdeb_6By`T`tJ#!P?N@nQ{3;$+_B#;69}&JZ
z?++KnW)(7`vFWzqE5whWJ+u*x7(-fEihttX9cf{sEi)Eozz@HSY6$|}Q)*zx2{SNnjVVli`lYr={`=?PUsv$2TU&%1r0;gvlyy_b^|27t
z#(^yxv3|P0S4#bm=L=$_2mOLyJ`{JNf$3p4x9&z_CB@+NsaeLb&Tz3LJ!7!S%D;>Jh_xO
z$ypzKbxy<|Pjn2a)SSePRO9(eiB$>N35UD_?Ga_%5Ubc!$0V(6^StsN2){eI(1=Vgn<#`84__o5X$(E5eNkR8o>m)ZS@|B$V1B}(X-%=|t#+XQd{;slYIkr${u5T{Si
zhqOY44e3)|*1C-JXhU-|%Uh_ctU%l9j2$a?%9h`O9@=)|Cw=Ch+5P7Cb5D{bZqb1Q
z`>HCBm!I78+PSyS%sDk=&+}CYE^kgXOL}2F%e%mh0i|NU+s%t>Ackn4uaZ)eXHRno
zR&H$On9R|N3^FI*16jnq_{XJ&(9p)4(1~i)vix=-@hO6T2*U~
zxI9etsVzzURx)QXF3V7d%V!g6=LK4ei
zANgZ}B_Zpk&7gfsfPX7XsN(l(nK)yX3i&wH;)gTwH*k-36w5eq?iQx2C^1i7p^^+j
ztww}rGupvtGVn;aMX?&TrtVCQAGLCnX7tTpzd8N*^bxP_cy%D?L9z{5>UC5wF(QnK
z7uGzAdo?EJgsS4CM=E~{IBI_zH*UyC=rAYB6=1kiKUwSXPx75MY
zO;;V=`@OqYN(-{Dl}f^$e8Z!?7<%QzZs_&Wn%=ls948*GlAob3wcJ;qpS$rVFSd_`
z)~mYEa6X%fPI!;QG6fb?T&N&*zvC;=dh6>sqAGg6!A^D}XMH)sjeNJmf)iO7EDP84
zSdwh07C6yGt-pe2ej)xhavNE=I)Ag{nyMnfkOx8^C~nb*_ywyJ=<2J(+|xVV|sF
z@(Nkv?S>Wd{5BSOfgAN;h2;A+M8U%7ve|E9g=CJ+G-rr7ziVQT$*RlgzX_9Lez#t&V?Bp|o;@(SdybZTc=ZdInZb
z*xi4*x87;zN-}L_
z|6-L0YC}{nwqR9~a}yI)=zZ=JF<$LPCSJYUJ9C_2-J{H#TgSz%qg6w7Xw@W8-;cI+
z<0oHip9F1xU*_6VZKpLd1^M4}%)KrfYs6dMF2@}*>f4#r{nb)~@C=)uZ*UG}q6XiY
z^Mt{z#oD=iw};(7Q1<+@S46Qr+5&jWR=|HBG4ok$nL%w~nVSvgw4AqT7)NjRXoq#D
zb>v5#3ST(jk7x6{!XF-lKa3k^=$qI9Kh_PwPp}`5s=f9qK<%%P3c7o*x8daaB);su
zUc=e_FR>pmk{V9zsYCWH?LuR}b|wJ+2P?xNa_3Z@w?S!HMJB_?IDya#DX+}bRTO2E
zEGG&xII)_#A;RFSCj?loU}cr4|NV*)d-+t-*z}%rv0^}_O9rt8OWv-^FLh$YMA|E^%I1IlZ&*?`}3ZnKsW8A1^kYyNh
zZzAgu{%yv;5-mI}lDR)`2qgIOTt9GwP5h}?&hv-w_HucO)ra=d4jPVsKL_)q_qS0_GQ968
zz5|O8TT*l}TQu^OoJD&nBRt}{tMc~3PXl%A#r|6hvpd?M@9V`Z8qeWpuUCAxLPjc{
zTd{ImU`v=RkPsN&Ae^yRSO6C?s
zutlttZ81s07be=%bWt1C)03}!x6qSbYRDeSg0gR4qTKnP!_!N>$}eX`{{!+}uegz)
zpJR;lu_dpP#_x#~w%f!H
zn%L8pj6FJz1<-dOc?3ShIHj}Mc-Dh9?zMj1~FV6VxK$!vO)#hnJwO^)QFr`
z^Q`pT)nQFHZ^DP~$%d!4*nb(}hpc+UH;Po^?|N~|ZTSbpFg3XB0Ooxb{;8G7E5E$P
z^!>=OzTu8*rHHXfyB%yHhA)45v!$gZ>sd)ROn4!%ytu8WdAjNQJ^6cknwR@8d}NHo
zSv@;D2@#wB16B-d)@{L-S=##1F0ETr(QbUSsg0jf*Dhn}BlT0!I6W9N@w(V?_DLF*
zIJ1d;yF$FbiA~4v_>SK{Z&GL4QrF)&&spu&gP3RV_rQ=(zGyf
zHT0LzTn_QjlT#y3?L9Rja&N3(!SLCd{k|>PWj^t4vufg=w6fWV30O4A_-I92lBNc2
z{p{#SeOct5o|X2RL2S6k*tf3jv@f=7x&LhGp^?M0ZrnJrcX}E5Zek`Ot0n88n)$-;9K?>6P!8-Ji`wflb^JzvV9kx%F;CV0;c8#%R
z&sGj8w@IQ3H2pyMh5XbiBz1bn07rH|oW{%_x*V-nH%imNaHhY+$b)n{!QnC3KOOK{j
zcYOBZaV)>Vha6L_(Ip<82em7jipplSMvLp3RMSUFN8H$F$YQ1s{1wH}CRN9|o%jmY
z=Jm{avif|fvg7oATt2^pgY;W_;uytlkaZ^&S26aiV>qd1THrM-a|=ricvkJUHxXk@
z);|c>!pUc>@uk0ato9W)@j|gm!Nsf-I%}~x&&FMHO)55L+K5k(be&^6TWa{IDFSt`
z)oUn=EO_!UL?zGYw|7zFWp?Rc{_w`;WwNJ@ls%2euZ*;~3
zZ&cvAh#V&}T=Dxl;4;A1SBC9Q4VyYrhgcyCGn8J4e-TfxPuj%6s&taXL8lhc(C^%?
z4qQs78fx2{;^atEgs;;5%3Nq`@&kksvc?vB6+^FI%mqSxZL3Gt1vLZ;KX;tK?9`Sv
zauqn|Ra8IVnorz9(RW`1>3qQ3hu-n2&U;5e@JCrl_83?!%vXnX7)P(z%
z#@xaV*kG|ydmdS_&FoF{O%ug9FOrBN<~2T9po|OWiKZynT~fPw1s&}y2LTam_=4VO
zji1OiC$zs9muwiYFas1ic$g-Q84#%lH(o>2{5?lg&W@&tYfIgiH1GF3*mLw9iw_Zv
zkahF6`;wLQJczm`=p^5G<{voIq@DV;?^)JwSO`Zxz`2H5TGJ^!*K9Uu*Ty$s-w(8)agLRfAM^@GJx1FkijxqEvdxvRX!WnYVQ@8gbB+lSJ9YH+iMa%Xc-Mb98
zL2T$z|1fxW8Z^(ozwDqv(=YAlLHrJJ3(vm4FK
zMc-S7SrJ_g(a0yfeJuC;3ZHgQ2*td)qFr6-)AUds)&R0q%lDqxyWD@mPxME-E?<#3
z5Lzl*l2mNc4HROPrwcP^EQq3Fch`T!5N&GV!i;X@Hy)w9_b55JTVvrFgtd`9t95!u
z>E87H9nWG9E2Tk~VuR0$?@zB#o)zDY4VL_OVyl&B+KaJe!MDxRgC&3S^us>esdCIw
z#`J2pcKtnLNRtXs$oUCr2S*OJl>_&s;FjglZ|##Z*{8M?lYO#-xh0Ec81B)@LIpE1
zC_P%7vr`4^>(hHBX`4**b7>|JTl(!wDsg48YD>2Gb2au#*Voz?h&n-)rnV-~&?!kv
zecZ_{^9`5I`gTf(eVLZ@NjFLtL_s5T8S;kAuPSop)t=u;x*Lk-HY}9seW5HQ{`kv>
zG$-RuWSXN75cinlN{_h{L(mTQ@`x}UerT%cQyX%SwhZFLpYGsJ607$wu_=}8A)NXY8oz%+IrM(B~Hq9ms1=AeEyNAtUx_n!=%ej}t&HDnV@Xm-@`9YePeu2|RUsTdHH-1sT>>8nt=~e+
z_hIP{Df(-SMvy+nE$5%HX6q@hpCYSt@WJS>P(%IJ9}%OzM-$E;4Yi+q8EbO>#94w;
z2ke?@1w#iEX!0qxVxN?}cO%qN;iLF);*}Sj^c+ZtLPcp>@`>b@|xRe@bHFe+SfF%}LXhrAgYOru-koi(27ms#kN{6lK}5QvCH%
zRckMtJ_mU#cdEWwDel#%>_sVDq-CckFV~A0$>OL++_X2I^7@OB5!SFt%ff|)8Dq~=
zEe^G)PGD+d8)b_J-#z86tVBP7@kj5UNJX^N+`zO(#CgIFE4Pk@=1`&36sBN9{Vv(N
zsZFrqb5mqBqRUU=hi>aD`yc-INpO;3w_VR7N*Bg0X(@vJrrrBYw8!zbS@-qkm>hbO
z9&N97umw4xmArK)7n!plCrH=X#Shc<@?s|5tcC=hJ_#0Dhe37cCEHCCqDp`RD|<1$
zBYKzluxafbR|(xVpS
z@TYS)!}Ke%zQ{H7ug~DVb8!=+Z?;AYLV6DLg{P70qG)XJSrU3m&&B(YJJI6hddPo8
zYI{u%6K`t;F(ynU{4e?`L&)t@h?jyfr02X?N-d2Ae`ewxEl1xJ1fpSj0?gje=J}#<
z&R&df%aQJrw9O`;K(X${<~o*_+mxGx5#c=t&xb+Yni^Fgx#hOKSjYH{F1gL{a^3Q5
zLmG>H>id@MAVtVO&+tqE_rq$$Jrz>&Hi<=%vBwXVyQ*~KQQ+wZW0EDu{Rgx*NLliA=4HwSii%S>PuX*zmy+1
zhOY=>1X(&Hp1@Tt#gTE-_%)ZM`O4R2|+v2QA9}eVF_5^M(xyujM
z0FRr2*@2w+hg~d55R&PwS6FXK8I?3?C?BZabUW}X-R%IR)A+38L5$Q5#JnGeUBtSl
zcNy3JhD*|}G$jqIWqX3}2O3?=e}dIa!>QM@_WJ^T!Y+L%-~0tWF1Z-`x0nkgACzPV
z*L=U;7Q|Cz@|s_-?N{x)c7x6_-%7E`;%D%^s?9wN3fj)Wi;ARM*bn2$4$I6tO8bF*
z@cWR$-51P{KaP76><_s2d?fA!?UxxQ+~Jt6mn|}Xn##YD$rc%EuZlD8sDk(kM<0Jra4a%&6$(_-$7GZ{{j{e?u7B?S_qa>JE|Ar^uhXvn
z$(r=&4|Cnw(Sx?jGP$yAYz%>Q4X3G$-;?i`N1CM#!D{$P!JtDs-JDn7d9#aKmD(d;
zO`mYBW}yf7GV+Xq=Uj!(h4}SSty+PwLOrkc$d`zVfv3<#sCx)rO)>j^M4o?%Rc9$S
zg<2P8cf9qhe)%?BeoJ~GWTTOHdIvMaSQtT>q#eN7ZGQHJ-xr;sD)D@(wby7_z7?^>
zdy1de;M`c^$n%HUbd~|hkygx?O|2I_9%hhwvKO83v(m$>Mjw}N)Pw@N(0I$g1)I3G
z9(PG)yp*9>&Uqa>nJtOJ*Ml`^!4P(5)a+0lg3AZBOG421PNyq;rAG6
zgQgO3ZKG^`tgy+&j@%d##Ou$77&A-C9>7f>=_F_?1|$Pk{{X$cvZp>iU$Fos7>${?
z^y1>O>$u?}pEB^@!6bq0{!jNuh#~ll
zAB}DdkTtxIZ#8r{6HC92U8+UkqKu?IZZ&C6dK(Pk619j_fvx^X#Pa
z@}(cfBZ%)KQ6OFdnJo8%g5|fE!ZhADrpdNP4)G&LoXt|)7qOdEV&oim}^pWfBRI4AqvfuFyX|Xk
z!N>C1p?g~dG}ld}aYoEF^j^(vg0Dgahx?3BFV0_XX%XEi_Hf#%2f~|uoS@>z)gjI-
zVn(*(dyBg3TgQn%Uk5byaZxIQXp6R}ySJ_yz1l5JTwHf=y`Nhv;J&ARkeW1Wt|`ET
zrJ9p$(6xlvEp=SxctdVoyZfW_5%~f8_$EaEtKgh--62flUb^%N*Q1a2AJ!e14Oz;_
zjyNIYGia%`TzZQ8Tq1M57Tw>KGHbn(32R@w_wsGdHFZ`$-Xd}CKfv1KgWg=ag*2Lp
z!v0)?RNYRxs@AA@!Tog<+n-w?7+&hj4(C1^LHAs8ZXp>)e}B+j#;Z$-`iz_Xdb__D
ztZA8AUZWY!_#Kb+ir94ec~7nVQ4(BVN13+o>c9ozA+Gxtt)kDTtamX!;!@D4{f#fS
z>BAe04xipwP%KC0T{3={mMw!!oby}6sl+K9XJd9Fz1RHQA2i6ug!~h$zFRfkFe{p^
zIs)x5`my_q{o?0A&bLWhiS~nI$KUxp7VqfEN_NKCd&X70e8~P7tY4=&)pYmWI>m$2DDtwECBHTKz_fj@RlZrS
zIk|dwde7ET2AzJ8bF?rc3~KgBsWyCpRaXV+|4q8Qz{a~rf@)jC;ZHLBGn
zaY;>3!pw(Ei9IajPA~E2X0~cKKPZ&{-)nU}V;&zhV)TyDabxJL39qU3Z#S2VG5Uw-y~=_~2KO4x;6U3NNIix-^RV(?WpdA`!gtKsOjJ{|L9E)JbF
zeK#x$Qe#g|Ke2i@qQq+90|E?2gXhE!M8qCBv={x=9ICliy5t`e{R;OO@(ymxrzlBE|I~Mr{B203VNEK;
zw1ZR+4K2LnTc=Fl3(ehk@+oXk{YqqMe-wTe%RYg181{gS++Ci5()`BWH8Q+(r*S%GiNF8)FOU(X31j}`umYDK^2|&*_SG`K
zab=ARp^uIE_1T;;|F}|$o-fHgH+S^xUqU?_;}twmzm&oCz1&q@`Y!b=eQOuHqEYux
zT6nj@#vZ-W$gky2|HqA>J_0bSn^ZYA<*uiEk*I5W5Iqb!iK8zSK=NyeH8tG}>O`^{
zj(+kP=}e4vZ5H`i%MsXQ4Nskeq#aFVqO;*>=~}`c5U
zHRm)a+DeLl0Ib%Izp-TWKEy9Hs%yYw+D>06B|GE;63K(J82zmG=-FK}CowaltZY08kax>I$KmHjN!CTIiEHHfxvw+U=h
zG{q*Qh*56;l(s^-Jdik1t1*+F4<$Zzzfdk)@O;=k<3f5q3C};eTPT-j;`x+2Mms(K
z5YLC*E|kmI`~99aql2EWU@M{v<9+(Ysu(!*leW
zP0yPMg4=~CFU-I_w^e6r%Fyj=${69%O=%`Oo>eq1MZc}78sgxs8dl<D;Z}q
zXu!ez7c+D8plm`<`SnKp}6=f9QV?llb2T&Kh$Dsm071ZV>*{c_)=kHNkPyAQ?Uu`Aq3
zuvQB~?jgtxS^+s;1&kC?-h@2iYpnccSW;KF11If~nw_4)?#*rX$~ye6Yv1WHM&OsN
zsoh@L)c$pDA$|oS>+X{;HS(1^vhz#ST4xhFmi*c^I9+$Nkw2IQ50*4_~%@t%v
zEA%wQGnr(>_(eQ8SDqHxy)ukT{cU_@O}nnLGNVu~*UM#NE8e|P)L`z!^M%>aC=rO20(}t{c8DSy8
zS^dn9OzS#-F+K4k7W5Q(K34hLT6waZhl^p$(7Ek76e>+t0P?Va9A
zans1(k-S+H3=VM=B7ah*E!pNG>#@mlubr8B-u*#WUiAQ%>B^Z0AMg`E~xsa
z8j!Q22pCU?eR%1mKul;GJ$V;*ZQ$M2aar$@H*4d%+K%tiH*tH`@s*QJBYa1y>1hpsN`M+sHtE
zjSR6NG?VLqc@UllVOC#2yq5l>oTChy`OwwGNysyTyjkK(Gfz)sU;4(r2ja3Gm*MVP
z{jep?KtLaGPi&3L!krq%)%UxZr378k0ft;CiHDw*hExF?SzdZ{#oqV
zJ%thQ*K2(JPoG)~q!9hHSp*}^jzSHvi#(TD&ZX!>zLCTkmsOnYMQgs*5W*qidnOa#
z+Q}$$11y=XFIxL-c3DmV%6&`-*9h`1UpnWS{N4fVy;TmIC+_ghQA<-
zmZ05}75Ly1#?w>(A~-jooQi!}OEH{zKsg+D^MB1L)NWTHw?JblsD_|YVt`gv4w1Gv
z^&v$PSy>&}mr(hv6R@8cV$p}}ApHJ?D3$4-#-8A+xRZg~kV)AO?Flpw$Yap>Nl935
z`NX+)R8|-)=`fFHI_H`288g4=OxC%A?+=`+I(huW$>V2^o~!!d(4_-E?z>+3VoHfa
zob{LACpw2X(ARfv;ZD0d-@+6=GpPSKkIVxrJsG;-8mhs11)bvNHl(+1vdo!317{u?
z$=gjFZy(X0w~v3C=f@}W_Hh$Vv;2A;QW=k3-qp0^$2?Y0ZN
z-F$=RMscaG5*90jis!qHfW?#A7!s)}44JPohE7lwhTh
zMe>DV9Q=tls0zc&RL1VdRE6CysEiReRD}_FD(cm4LhmDw0je@UwH;7x091ftTxJle
z8Gvd6ph^Z*PXns{fGCpZM{#`SC>A#jnr^kqf*{L3IUYs|P?bVl|V8_;PoM(7d
znHBuY3XZ1Noor%+m$2T*xedyeapMNZ96N)zkG{e4V>s2E-Tc@IfG1LAAKza!XAeIX
zUmpLo3K8j5bISR#PXo3IDt_b)l|5y?iciT@@fM85vH@9Cwj*+68N6JNsem<=easCN
zKl%c1A9W1ymhtw~?L42l0ocsLxHB>C`TU$per$h!&OUx@BtPc>KbGU?95S^23Yz8c
zFn%oJ-i-Yd2h9)1kL}5l4i|8Ra(MvCTVbb2&!0h^t*}L;GW0Tsw{S)kl_%o)7Oqe(
zzlCxkG7Z!7-=WTCu23#J@O(38RMYe2C~x8lD@nZSt`TXPnh?I0>sQWyoyr8R!$RP
zIE%Rc^R`l?{#Pjnz!r+)|0?3`&qawhoJ9fcP!_+R}H5#Lb~3};cA
zxrxgX46h=7f88by@%zvIo+Z6qL^1te{fK!l6>%D^;Vh!|&no7!Q2HbD))#Z`fBcFW
z`usQZ{`4hh_%+IF{);93=1b0f<`F#qFXsKRgfmP-dCdZrG^d1fpN_%v1edl4gIwNg0MU?=$bkjhy?a9#21D-rDt?YOMP^1N(IBqv75_A%3k5&k8fV+J_~*
zw~I5Rw?-61GBDy&2mXNW3nL=|U#2dY3x-7yZD0U6uCtc*p%SrAtpc%pm{58()S
z5JnyTN;hU=X3`(8V)cfF@nh61Y0P4*UI)jI>B*7~Wn=YHc>u~;SiMw!26eKqdZ}zi
zS;Fe2@yr1FP4;8CJi~qzvyxheF@0iM}&9qHe=#nl(G;
zKHdXmnzx0pqVCHKu{3kJ$S8sGYMQ%T&VBAtJg3=PiYyaUrujqpKdB#@LG*K~H=ffR
zF5(PRsZ6uDh!Zjmu{4VkCoD9qrdiD5B$Q|tQL-Civ09<^?Mj9Jm)Rrgrj;)C`iPS#
zPiDx>Zv^|KZ)o>)Rd^t2$fuysYua9f)hN!FjpP5Socl??uh>c^I5~5fxncLVDBUC{
zG~JY)r>h=2pQKx}&fjDfq5Xvi)T|noK51b_Yjj-;-6JK~xfDcWF`U8~%;gs>t`v=>
z#PjW{BwsP}`ffuP%v+KqNMIp2xzA01v?SNtR>^TA%NBB$vNv7B_!q>0Uv4|ooYd~;
z%IrzmZK`h;xmI23pS0*YEZdq@;?I}aN{^u?gxeE>+eB?|PW&JmGHQZH{Gb>zo33V_
zdAKC-W92U-wO4YP)ez3C23z*B`rd)ANejmEEEKK}|pCw1aPz5;e3w#Q4L~k+lYt`!H*fRH&$tLnzNnfn<
z)Ts^KEiC4GzLmV1#L#Buvii-g$yH`SbGUTDUGhC~t!Ps7n=OcG%v39^`Ia?H*W`E?
z?K5T4DfP8|OkClE9{8O3Sg9_h#hhg5%_WK7ak~F(GQ;BHWE3R-)+jMh11u+HH<@%P
zI0NCtqMJ(6gKjcT)S#n^pr;Sr*=cZEgio1yMyk81JR;Iswc;Jb0m&G%!8pQi@14Jya_JC;{X<;m63>lFrc+lzerj|QTsLSYvT9Jw<3xpa1vJzo5$T5Z_+tv
zzO`X@tyQ5o1xqwyg+4WM{2(#pYslYyuTX8skN02;XuDz2Ro*hWd-Y;+7IIUb)-a`+
z3#|0DiE1r0QPYEWF-nh4TOXN|%n^~kr@kArb4$|HW!09XVvrZPAC^~-NXjRqmLnjZMtNfw7#BpX{iA#6XJoO!x
zxCGjW>NkP0mu|W|8#Tr)+BSFS7}zerN*~svhy(XX6f-zotZK11u~DVliTvE5OPKCg
zchsCErqUiihEnZpq*P9xLl^VOY_evzHsPecfM7b-J(xBW(VWlnsVq)@LXF}
zNqH$soC=3{hh
zQ%OG+WfwSxJIde#GQ9F#ifD$pyipnloKu_j?-x|7g3tRNIOgM0>FK(iIDKZBanEL^
z9CVE@6(yV)RT+p3y??qi-{zH?5VKIc=mRHTn4ybqQcoQjT91<-?tHHKXf@Evi!moT
zBo*PY#8H5+mfnB*8vL-^^VF?VbQNEjxw_V9o*|
zE>Zva7MY7y6+^2)`cKbLc|QJIzRUE`{zL7R)&0u+f)j6qRKa#NPRcrY;3%zz#L6Mg
zqT_&k(+*3VWa!4i(5KJcjUie!&FT3YUUi8{{9esq{q+#75{-HX<>Ty+`GT+QsmZ@S*)_X0*+=@21jjqDuYzqw19{%(kvDgY1Qec#Zjn`lEGL&@RNSLYWXR?dOlTO322&>~}3LQgEK67Yl(HI%LZ
zHE2>{GpSI+>r%oAr$v5qLB{Yw+@Z<1ojH@9zMd(L5ulBt{?~asqRPy`7lY3Vn|y@t
zsw%`??V$0Htdqot8g{=Sz+%|iO#;2EofhMIihv7TpNc9ImqWHd1Yc!UfRcBwS5aBU
z(6+|6t9^3K^O1Fu95L+t;{Cu8R)|9Nt2^h2=7;do{@I7sk_F#t?7L{{nAkLfGZmHy
zY0%q@LXNxP<_n<_0DO(!L+f;?p)ukXs8X%;^}2oP
z#Mr41>IC~y>gC>`deP5-qo~VYer|nS7WD(1t!?eubX&oqFo9NS!_~kjp)vYd(jCXA
zDYe=^=YBEM4fm9pURM}e@otEW@gFijay^;+L(&t(ljd7k#|BT);hT`;ZMf(vJ%W7qN_B%v@F3%ts8FM
zI2zzW?~5%1pankQnCuwm{C2UuXcTjYni&Ix@zCNSzHUG_X}Q_$>d82BdQ4#IfIEh;
zp757iESwl=5C*_LtqPGaO4P3{N503#hy!4rIHE-5q1~N)^zmxhlUhyK8zeWImdLQg&Ut!PCrv51r7q
zUGP0N-u*0Ey9$8E^EX??LW)EZh(*~l{B#kvW)AI5PV`5|v!t*>P4b;q;c?uNMro=$cAl=Q?WK~yJ}LorE0hKeJ#o7Vx#R>hF7LBWA09^_s`gY`w%XQVnoANY)wOOr;vzNVoVkBP(Z=vX3k*?m)Mtb+bYGFluq|Wnu{a`yv4
zJJgd0Tvdx+wx5(f&Rx5(IVU~~x%hhR)a#<(*1K$F$wPBp*0srz-FJFiy;epJ&2?Lw
zVGZSNzQlPyn#{h={l?>3IZ&_jRO|n`G|6V*u6w-cK6sZKxFr8I=2|l|(tG$Uo9ppr
zeZ<|(`NmV}5@WW6p7b1FG0uHpRnf{vSFT)lcdZZ-yL-%TaHG97@12TRY?3hdBKs6u-Y7gW1%
z2q!FtXjO^0pCakKVO!dB@V7KgM_dHbqfeS&P%-X&qJ!R*IQOwEf6?9pWiOwd{114F
zJxfm)=^M7`pOs{e+J0BE3`UNd2yiYuZ#;68yT+NnHN{DZ=C$VTsdrzQGwsZ@*??7{
z8cX+m;JEXu=AX@)vT#p+{UJuJp8P@_FR;tdZ8!XNiJtzBKXkP>y(!(C;23*4D%H>}
zS>x`OseY_rk4;j$zEZy+xxVnfE4O*FG5Pe>-l5h+tf$xaPdIk9H*xj8o1Qr9u9?UJ
z@7%fXvfVX%Yj7*!y7Ha4NX?e$8}rglTeK(znsxDbJx4mVjd_1b0{{Q>E)G^9iH`UKlBL8ECqZkE
zyM}o;rkjRX^Q^mE&!v>5^dEVnXVf@Dc4a$k>3=Lz3)s!Xx9V8$Jrb-%NcK*Yh%*^l
zqFJAV?k2L!$geQ8e8j|CMa+<`g|`RFzxfMue~A3t)%m%Z2gU4YPLyVmOk2v?bTuas
zS99_UQnu?`%?q4OeCJ!{iuy`@DmiIN4JWv81ErBPyX0MczLlbS48~r5V0Y0T&|3u2
zTME%zgdxA6cRFa=uD3)1I$Ejlv1y~?m3=Tm)
z#-7N>*b|u=dm`t$0eRI8#sqNE!7~ite}W8QZ}3m}#jx&J9U<7C)CRQ^`_m%WrEOj3
z7WRi+4#gTlDYW}$+=0zo>lRWCDcwMUYtp*?DJCTnl)DW1sk=9ZF5w2F)hD?kGKHo^
zKF(dnnAR;7y9r@e<=KC!az=$Y(wRDc^oCLHni#eu#I<5p|M;xIAtXt)yT(@RuoxDb
z+g{E}!8&SRoO<~25ZdXU^d#>eBj0G`u6(7;8R~X8_`tGPTA?!vb@o;y#CeCKt`$kt
z?!4oPGPmHkpVpfwZe7;X)K;d<^HTo`$k}bmn|4R|VWsWs-x$kf7Dirf^jM<|nEP2k|+tJW-;zcD44yQMb2^7gcN
z=`(XGzEpx6VBkOZ>52mqNkt9K^Up4pNTS+WGyC-WA&cdwThA;w7L;H1C~tF5PdY8H
zCzqkye(t%taj-_F_PI@8tgn*WkH49U_DZi?Prh=D%7Cy{_ZKGi$;jhio4zZ*jB
zjvO6|8jGbN(j=eUQ|C(IxwrF
z@O$gVP{dj{3G&-*>>0s4biErqK$-I+1)&x6wgCQ1n4#L&Zw%ZI%GHx+UHApg4El?V
zlR$xypuk8_U?eC|4+_*rfgapaIS1%!+v^sb#)1{!zmGVFhmrMn%Zhjv1;YC){<&Yd#Zr)()zCA
zwqc!Tx&h{r&I#fBZ=H-ZQgi&6=4tGi%lZJ@GTf;H4i}aW$WR
zusK}*?GLO*egJ9xzr+gsZOcC*4hcN}LjMCuy^yUM0(lW=()QRFPx!{-d_rxS|BsVC
zIeeZACENTBv>vv5=@e%(3;Q2APK-EH_;=(D7NrpzeUWu8a4^`=M=qeAyG2r+H;?w+
z56`pmW_J<1`;f5xa4`zGGJs{o}@VZV|3P?c-CIOtK{<{
z%%_KKR&5cT#x6aI+v0}eg0T9V1w)~4Bi!Rd_ov1zmTY+hbKzs0fg`z%p$~}PHYZ|@
zD0s7`lI)TN`0~g6p6tK6@$BO3hESjM|M+46LLDG%{F|7@3u)6o3a0T$JHJg6g2>29
z5mHO6UTIRGzjqP#E_tpx?9OC9zGLAMzLU|LDrj
z5evl#1>12_{cX>+Xhg4Ay54ss~0yAO&zSQ~LM(1X|S>p_v?Exo8W
zo?aWIcuP;`jr_iO@UOrdyeJ>Q{fBo!rkQ&mcSSsEkda4
z<@c05*Vh6I8*wbq`?Pgt@hy((bN00y4y5uuP~Wq`)Xm|j53&$OQ4&aRp>wbM{=VNV
z^?Mfl2|kOUrAB=(wDVryyM<9Vi=}o}6$jfn3-jgaB5@>ay(^9cr{&^*KMo!i$H6^(
zeg!_u#c_c0|NSUHd2tjxb33SqR5>MP>Z+-dX9r*${8zIyuKm7Q>PdP&I7^Fu{;y{#
zf0cZILo0set==NtXI=LfOfQ~c5vjxfEPmy$qd(KcZ{}-6u@%>Y6f*-xud8C3Tu3`|
zEtn=J`2Ozmbk=vmJO%H)zpq;Uh5nuV-_2A0GT?m|@SEQ9znP~k7r|?;|Ig;>W8ePY
z^OQJUaIVH(0H5<5O(H&5gIOB%KfAps!SQ5~i?>9+_-%l$XNV&{)7HfiTh91BNso%u
z+nv532GZN<-
zQjf+5Q{zsemJ{Jh^oTr=eiXCd+sa8P)?N%G%(3K0^;$N0X^yTIwXlM1oplKK#)zfj
z4*LsMG_Qort!XdWswO%soRz;>QDzl0_m9Pj^Tmhc~gH`e^mX33F{NwV5x>h6Os4xDW9LbBnHKQ699&u^_2kBh#Qx)mW;`Z{wn}09CjgHX*%ZWF{dr#WU
zd~MC2M0%n8ceqW&og-`g+NvFd-HLMQrOpX-|LUw)*tqZO8E#e+tl^s7KH>gQZiP=u
z_%@+?7~w9&qmCwzCVJ+5A(EVHlAN7kBX4n=;9m~-JSe0}kSe*(1X86)l~QVUl#nVz
zs_b5>9I5c$i2m;*q=q0ht3Y&AW-c4ce
zBT9e}F$aDOMjWF%8j_<$EG$Q)ymaR9Df{^?|2%MJyF*g#FF5iyLFNu#pxUo8-^qR@
z=bN0dQ}#@W0QFqhdGcoLI>8HGyQ)#u_7P4(7kZsoe3L6uLB3G?h;UZykA2y7f!Jp~5F>1*Hzo&YUkXyCnH1Z42FGNT%a}BQx`B}+H9({rH2k_s*>@%#aT$%!(W$&5Rp@
z$aXUGgRTF@-xX$%=jVov`8Srcg-f_TJtUodxgv+E+5P0*P0Z>?^{nYpJ(Ke&
zZ++1t+}&O{-|=Fn!@BbW*Q9(yaz-bUth#B?OzUJxTZ#)A!*WZ)C7LIpT{fk!fxLn*
z9>6URhjpbvj^6SZGHqFltLU`QtLnwhSyhSlczz4sK3-;Qf7!?N3>EZupV_UtvaqVz
z5q^ixaJBvXN6&vxeO-0bW*v8|OLt&qX3#ciRhDGTD4yn(=JXTLXW$-!_2J3kc!G|`
zL+$WuaguaMVAF7qqOFg9$jUzYgaKOpprKlQyiu!<
z9jDdn7E)Ry(jxT3wpzY~
z&2SaFk7*RXw_W!7rSK{+(6#h~KWe1<6iv_P{^eT!*V(QxMkddSsaKh}hgUGRXSnqx
zgJaC4Hrq2^NgVrxN7akZoKl7F>J@{Vi$d=xm0{WKEZ?hn{hN2?A2|12vniF%KMG&o
zZojLMF~1;3&Q6BMNe+=d7JeEFiDsV_EVnw88D=W4&+qS&u&gbu@Q8$2DbcK6!4@7l
zes^!L@{Q8kYj^4Iw|8S?%ZPu@$W?smRR=gU9!vZdEuy1o5{IhrrNo_Qtdssfpu_qyyl
zxt!6nyBOEWp3r;4?*zO{=@;)3`YmMia{84*ZwARiT
z6xIX|NzWnd#U=XCCdLI%RhxQTX7oMiS;5YLJ?>>_)!-}J1UcUu?Ryx?IEgZ~hr3p2C3KML7q>mW;6h6ZCkq)VeEF5Bsls;;V
zEPRxW?2EZa<83E1<{vR;uQZNz?){m@+jw!jy?NKg%P-`6V@eJe{?^WCXkM$m
zJJM`}Ww_
z*l(VaMDGi(PqaE|SoWWgg~#e+ZLv7TDy!uhB_tK#6$Q|DyUs9d82$n`*kinB_0|bG
z7qz~Sw^-DyQ$n72-dn+k+Lw}adsl@$N*ZdXl%41kdog&Dv0D)XD7E--f?Q0|*+58Z&id#~Ey3>&hmQcy*uqFZ?1q^)=ZHox2
z4OK%I#{V;MdC2*guc;5_sV@ndWxwqKfx74cn>9~4GQ?<3R<=QREW{ReTIj)bTVc7v
zNdBdMvVM52zih``dJ|T)vbGn?Ep2MFNLdI!%rU$xq(G++xe6Ko#vg`3mujTE2G$vX
zW`W<{iNvGH3guSz+?=yHgF)Y+3&);HTtWE7|1Hmum#Lqnh+L3SmMxgt7pEGH{5?GHnBodyqRME@3->Q~&kX~uN6L*|
z&?o*Pw7fOY^2{lpPodUFE-?mhZ_pQz5y-9HWt8F@;7Vg3q}jni13#k&BUoh3E6B}QYKMD
zBOe-u^bC<6EAhM|9iyPXnr47Vk1s2KOOK`?J?JIhn2MqX0S@uXeG5rfxv^$;>+ciM$FKhd^0qExslt}+K^m6zP
zNW)1#0^@tne?Gpuw9234RYI$tf2p6)DmsOZg7p*m2p?WV7~eNe1RFBqB@_V*EygXC
zja_F6tAifrNwnB}8NSHFPKq2;z@EXrv8-$;;hv7Cwj>ev_ax|_Bw(ym3$v5WRe
zJ1T>m>jrMFgJ&i>D~Wbn2O5XtlspocV7{?3HDo%Cz~l5laGA^W3;sjC(ZfXUyy_I@
zP6@A!0zQLCA^;v&);170sMRz#l!U|6fBWxoAPmUAjHsU)bAmA@IJP@%roPZ7q5Iq=
z>!NX&8(GJ#kiphI+OYBn>Fi-I$;ae~{?%yrsMptH)ex^??~?nQz>%abQ2
zB@}Dyc7}VsPQv}iNro$uGrVPW%~ItaqT~a`LXuMSm
z2>Qo5jzSU+zd6yy(q`xp)@UP%E7!$Crm|!A5%H~Mpnpf_;YxF1gPfIH7Fx;M7-`{i
ze{Nz*Etq?9uJ9DYTFcD5+1-cuzFo%^`6Q0O+iV?I>SIa+Zy^tJ@Vg=AtMC6gFV+!<
zI(9b(<9d=_De06tthMJr0lv~I;9%H$h
zc?GgK4SYtKuhOo4$FzMXeKSo54P?O@fTNesn7`xe8tvv^&{p|4|Bik&RI++@K$8a)
z|9uSP4+GvF0Rx>O85m5HGxx)u)sJBJ`(gmjV1sD>^-p4i`ve`6UTKN395jeHK*qge
z_h-=ZGy8P~521D)^KV_X^Rrot=&{nwiuqd}nxDjEvgY|oh6(V^A~(d+Ia~WGdQ0~F
zPJfbNp|biDYd_qN8?al(e2I!OxS`2~xEImx6#Nz|^46^A-Qe3*QQ;_d*>_cVi%&_&
z&u{Lj=zpT;_t~I95(9m7I{A{;LD08mf&+YVRz(qOaxVrPM~0WnT+N8MlE+L|(0h_@
zRx!!;B7;}%U=TBTc(Xx%Ct)?&t83&8ytTzZZ{MHy#g-{GZj3M&zquD=7G-6V(L-fz
z)02zd5B70Sygyf7oE*X%hFUSxBwl+1!~OA;>BDz+L%trnrwg@JNqNjU);
zh2r_ym^J?F+#57M&;Q)bmrUNdP5J`t(~fGD`95kXd6-#J01Yg<8IAb_T39s?(7h4^
zuQy7iKH=&E!rf^6F=$?0d_X^hh1OMs1~^NExz|u!&YD*q5o0UVZBT-%?ielZXo^=KDtIYi%`llq}
zZp2GkJi)&#>wXAdoL}AM7eu`Z8kI=DN@fK4*IAS=6k*As
ziO{c5Y*pqp4We0U!rCM&=ZUR)}c3hBclu~%sCvRCy{CP*K__X;v@wruj)y;gKw9Tt38&kzp^PS<~
zw4V8q7e&}|V19mw2(4ip`PT2^hUo^eOx-u&EAwWxizVW|0ewCS)IYX%Uk$iA`5hsi
zUTPig;KFXm;5P;9G{Q~}5R+_H(u#!8j6V%e{619=3>1`bRf#%igy`&a7B+EQgh~J=1
z;QdhIekLf>%gHa1bRu%AksH4hcZGbL?iZrf2j_`+2mIV&NqwnxmxJqZBLwXUxgm2{
zBQlI8n~CcS=>s?oi#rVLo(ESHRazYl(yib<>snnaJo
z(qpvyZ+LS4t*-f5$1kqMBN)!Dg05|>oJP}hm$NR`Oxn>^tGG2UvfwRk{a49V$EsY5
zZwfiRd@M^jtICkmMmhVJ1#`Z+Lau7ga@>BRDp+sHMUihFXdD@+_mMp}0c&xvRw=={
z>jbP#1Z%o82&<|@gjKgY2uHRg|f
zrCChn_XYIV8{E)i$A0fC@UNnBM|_F4FSxhLQR{x2=yPCrxM5vgwjq-bTYJC&e3lHA
zHEUPj5$E=-O3XJ~U`+1?{DK-2Ytp_*5C#trvHPw{`wl1`_Q)`Jq+)U>y{F(_yUs*E
z%l&Y@+ny&Tb5*8fv>ZJvth#N_G;q&9!E!H|*>Iz6f3|TV{7r=Q`4SjBc1tdshE}?@
zz`Iy+Y;3)A|5j6GquAQQ_f-<<`x%l1hpVGEv#!Cls5fJ4(|CVYCtGCaP-GNsK9
zs}{2#vBVw{QnVS27tsXZY2UDJUt{VL#BVY&>yD5wJ)2*HRGO=<;?}6o-EUd@?rXG4
zkfVqx-AA7IR{BL)3a#sR;K<{Ik*DymI{HL!Pb@j%wuFwlsYTWP5Ax=dng
z)VwN_s4ig?ODJd8o{%Vmy=q%kn;d_qw=G_{!AgELH_5It2@aJB9>mmxnE2zO&0b}Z
zURJ~CBW;Yn&sD~Kp<{1rLEdKQrpbn~^i}*~c%PH2B>ghhnTMK^+Z~8{(PLS1dl4jO
z{v9tnyQJ@QUh0wIfM#OK3o|9t7HX7APim7!nWRoVtBr!+;z2L`y}UN@@UVl!4?Nj8
z>NHNUu-%cIL$q4R5Lij-3Ag$eU~pk#r8S`mE0$%Z<(hfrzEP*KwzqBk8T(mjL@j1%
zpX*qW)l%&1mdY)kkj_xj4kc`X@VkJWN78~M-JBu9FSAHE10ox|)Rq@~G
zG!TX|s9UbuFE!UH$#))ccG~6UPoSH*i{^k0W0K(w)>0~9T9D5oA~j)j;V&^fYgq}L
z41b|=tYG_TjF2N|u$<=&c_26QMhq_(a_24Xo|__8V+BrP{#W2zA(x2=jMKVz=AheE~K8_FSl}v7D@gD(f*hA^sE`&>!wCtEfG&hEoZLk=YNSt8(Pn*rAah4djSB{W5YKmD~gkeh=o|s{+jSE|{B77zLOg=|q_4{Q^w%eGq2L
z@y`Z{FiV9PFXAj|xcGoPxp*u5PHr`1?<2c3I%^}xk6Rg+7QRDfVHV40ogcLZk>u)v
z>GP95ygffD>kfYJQm^6pR&XagYx#W7$P)xb{1-hA^KTq^LX94Sr!n*--UeqLjXz#!
zk~4{paTd3*L)g5Etg8G43!>wBaZGy#7Y=kV3H3d!qZ$jX`{5M|z99c}iad6OLXv1b
z1K(*JyhW+3J>jk7)216FGvfpCslR|#^$1GvChQsL2u~NIvF#pK9P2-HO(gZopSRqOV~*s7Vl)2B(9j?
z5{|?oAr@WVu9NvNLF?aX?){e3tO5+QDHFen)*K=gbv>7m!7F0PY^@U4bLVb@4NwkI}uA
zX0td`d_!yv&f&#__z>45E#f$brC8P4*`QlU{ofEbp2aN{dxJ?q{>jg}CNwavcDeM>
za{BI?IEU$@_@qR$NCB^)XI4-?QNlvpJ+VG8Gyh&`))#C>-;>6K=wnT*`DO1MrqD|_
z=&%OkwQ}Mf{N(uK!x7bzB#MZ6;+eLl(t`Gu+>mjNrzG66kPzO=X1G<@0XS5XxPlwX
zE}zcgd8cK7dB%Lt*DFh{&8{1F%2#WVSEI_vX%1g~8{;JkXKPRAibGYwlx^did#%1j
zBZ*R`Ek9J{G{`m0#NY;JQ1Dv11f#yz)#PrRv4h4Ngim!uE2@@w1K4J9oaS
zRAD`7IzU$7q769N176S7^BZMnymCWYjJlw+r+0QI$HTl>Jv)m{c<_`GR
zgU38rkV#Fymin+;_q_bep{m~M5tjF87tgdk!{vHpHtT1WD0P^%qX6e$ZI_Qg5#Lt`
zU(6sGLv3nyv|guro7cA9qH@1q<6_@jeq7c6rdP5p+%(SvzwL+7qr`p)hfRL4AC`>>
z^n*d{htg5^`eEKpna~e!r^v;A*zHcJfAmUMKWsc2=!bqO(qKOnJjVXU_F1&k{~ysk
z40Nv|y8n1VqydOH&_eZHkhP|Iyauz(M?q@2IGUk&?>qk|u@K=3gl`q=wA!F4ZN;fB=LA
zGfOQ4?m>`;fm*g8gbjdDFuw~zT)5x!=-Mke?Ymv7=cPdi+0S){&_ecSw}TKi147b32Kh(0*Jf?g35R|ullrszEO(8>r_-B?{hIZi(J(iFE6)gXm
zxwLzExxcKlb6d`4l$R;)mABkiUV`$Mg5`Icdvq@^L;0JVbK+3GwyS*VedVEJ^YMjX
z`5N<~!QI*~Mfvvka#}uvHJ$Qa{iE(HkKOyn=cqjSYR0M+S6m63cj80$RlQdu@oPNJ86id>yPinviOwPfXBF4Ys{Ng@8S
zem|Va+4h-OLJqBye&2tcv+a{ED0S>60m_CeB9y^^qLYjm(ACDxpz-e3lQ|J+Bg-DP
zvsM>$eP(WZiS5?kchSFx*5!Qk
zsaO(scV+z!Zphiz9fx1_;e^A616_1s1-MA(v^3yKNH~*^Fd*qCeHP~vJ0a5hF*ZU;nM()
zJw%8j9bFL39h-v?qdR23g;;QmTlv1M3t~(ArX_@9{>T2ZXqPB+l;cbzwt)X0^!Ui(
z6W?0==${X#1m5J=(f=P_@kJSZlg3-1{Zz~K?T}11`mE!P*eyhI4|GVP%_%9Sm(tCM
zcJTaXD^lhReMzGzjvG-rEf|p&XLvDg;rN3S4~Vu7QyUX-8;RYT1AOcj=+YCh0}zEU
zCP$1yNIKVu8zb0c!fMuTBOBxeI~2{!LvJ^St8Qy#q3{H@<4v!^WNd!^*V`(KU^Tj+
zU@pzlSVkki$oLm{UM!qc!_=LUPQ1u){3NKx3|oEE$NdYkGH_6WSTJXy4?gB_%Nl<+
z^YqxJ5Ztu}?~i64oPA(!<16*hwPwf`6rL&e)tELcJFpts6QMYTmLy!#;>4;6d+Cz<
zS-Qu0Y0=0m@w}S*fVLFlt4EJP+{z+Y3eC(RTcM!++O^R$vyNw_j;S0&_erk&>kPNH
z2dtd2Gb|gqhI=Dc>a24V;3QKvZM7y8@w+#cvaTMz@77tlKYfmvEymuXR&(!^;>H>I
zSBx)OSOtGOWgAu=LzHty!rgq74XgXi=CrP{A*PSYf$^U24Kh7
z*B#G-C#%?*IFTK|oZ78(J*dEsPY21d(3|F9#jJJzX4Pc$U
zKc4?+@PsNy1KrRsad$#nNQ?y=lNm2WgMID2!8zlqG_veli+%YyFZ$wgrUX2(kT1%N
z!HaVu4@DVCdKaB`E^XbuC2rgT3%g)P8Sy)6%ZI1X7Q~&5=SK{nZ^3pvbv7tp6XSX3
z=hQ*27XqJJ!)oION9>O>##k^b)7D#UUkZ`TiWg51ej!z`q5uk4Ti)ySQB(pZjrA)x{v6(p&Ojj
z_mCT0)KwI_B*C%NkXSj{-}KHZp?_eVIk=)kb!DmHUi%L`k#nXhVn_ub
z1i#>%6NvQ{9#}ghJA+krmwH9zvA0t)a~NXI3^)&y7VtA(okeY7E~C{fEBozl`N4
z4C#XLMXm9^@rLMerjZ`ENx*jz;Y($+_MmL<_B)w;+~9y5so8
zp5~>hTR0^HLr&5m3Bdad@S+KqxY#aOxBoHD7i~EA$E%31A!7a_d{V3%qO4xnjjDrl
zM(nRZoYTbm#W^E~R1^)Ui#GPKLhG&``tn2r^wIjXbCUw&D}zp1j=A^7*C)a8l^=88
z`1-V~9n=aMUp@BIND%8fmJo4>>Y-Y=byUOpNsflfdvS)udnS^po-J~@>10TvV_%CHWSHVbwN
z>IL~rtCfamttrF4(E$0#AO5*I(B$HdchbrTybu%G8Otj&>ke+
z2k1K(mhDVOPjLout|!zJJqx$aNne^)!u!>2b41QTy&1G1Bq?&W*#u4?V+$K(tQ3B@
zG{sGK+qIe$tq`|snThMw5rR>^@rEq1o>ssM&sUlg?DXWBo8Wl#iqeE94z$Owj^k|G
zLd1DNu!>AvpAHG-Etny!HCoF^eT;w>e~=En&>
zk6vKlL1KXiUI@v1r!>wyH0FR`y(62jHDl(n5y3d_v<7O0`Kx-YLXb9K9n|TVzE^%b
zs%ge16k$X&6-BQdE5y3NX83g%7}bxU6iU=oRlxJgl68ISB0fNT0A(y2ZSL$4(j>EP
z;#b|4pYNmF7GAMQN%3ar+1Ajh72mp#g7F6>^$}MFPYB*nT@xZZ!(;ME(jS&0mJ1@2
zN}AOjceI$5n$S!=Y4U_J+a2r`kxDJO{<4>sy0h{EUee!PS9p*
zUVZsab(%(QlH-=)(HBf~6AlUFUtg#m1iK7+R{!-chC#JopKtCdzg2G6hJb5@TplR;
z2kCVt_@$l|Zv8L#PxY{TM0e>I{QDO|!V5h@S-7(NpdI%-(B8c8aSddfOoIId!>bJ9
zUZ@KORay~sQ}@NGr?PBE{+v}fX%0h??DU!r=Bcb9*)L=*ag&A_YmUP>hyI;;D^$r`B^mO>l8JohgkcUqeYmjJ5yF}}d%HgE&3I*H2Ixb{l0zKO
z_$^_!*!^n5@PyTzES7CvExSYV%CdgfeuqO-D+W&}JtE>BzqdL~UQIq*IwxSXGCQ=a
zWw$`VBRlCmyKi?tx73Oy1tV(+!p?o-?dSN~ki#^uChnC2^Td)$xZXfAx;iwE
zpo1o}S>o+YfO~Xag@gKnwball;evnr*wx;m$Bo|566WIV7=FJ`tc$e3#aTOXFRee(
z#_ibURHu=CE@2(dKUo4S!#Q`T#GmxTHvJG8)&g0GKPl^P0{%U^bYch(aWzHiR{fAz
zxjyl6xn2j4D@pS{K+mal2J9Z>?YIA&bsYPI?xR7nZj9ioCZs8$Xps3;B}rXAVPW~J
z)(yP|O|*o1zb@B1%#1xizjk=Sqf{D)z22qSEZ#MDe(~)!Ud0ne?nW`=b!;GoWEy6nyK2!dasQtakl)Yf
zUhf)p)ax{!&=VJqlnwRp@YDm{s-o){$H%H1uvTAVKIz+x`0g9bSF1|R7pn&6ycY1~
zljx{$kd-f^*s|ANUyg`7!)xKaC-1_d5r>9Z$}N(kos$xZ<|%PY*{epdztS^TCF3lm
z)(E*?b`>#KhO(P_4q%5Lmo$NY$M3#8TKi?p3EK0HKS(=m(wxdXTIm2^G2C8>e(&8bOK^zZZqJwFRC5I!
z(_>}zxbMVMc?#RLAN^sKxJR$FF17Zp@h3f1Im|4qYWP1rB={(P7nKF4qRD<7vV}1R3x|!+F-CDmc
z+@x9iBs`4@TAF#)dDvSeJ@uA8*2H=hBUoq72&2Ay5vzZH4qG_M#Iok*6YgL153Xj6
z;8;6_)5O?%(w`JhYNSOu{Zc~FCmHh0m6?UsBG&f3$so;mp5@f5CEUY^6&x;u&H-tg
z1ozRRUSs}5E_^j}Y`{5FnTe}!XSh{98MmNLrdn>ZDoxy>fl|1n9F*YXCdy@4$@(Me
zwr!G}PR`vSiS*jsDxWdG;Oi3Ba?F=poFdJE4)kS1*raw#lqpQx5u$&jeQ)hsntm>Qi5s&yDY_V|_msS!n~P(Ajy5^n
z?vTP$bKo0v-Iw0t$EA}^q#apiIhYz|?l4H!^0JFniTrEZ$%{^UP*XST?p^ikhl0^W#=$pT`y4p$d4In81X=cWLsP3T8@a
z*o0dqUX@=3Yml}hb&rDMRaz!1*QZUj^X7A-m$*;*;AP3;nlK45f8j}9dzpE8Mc;<7
zh8tTbifq^^n6)UHj|}W&Gi@0-*C387@T-lLrYj-OmEx?E5tJK=UXRA|l~YJwls}cQ
zT5aKuRp4IYu{|oR!iWxFS)WE)*;KRB`cC}HeY}d7nX9%<;;`Gp4#~=;ZDnpw8pYG>
zrFkE}S7tUC{Yl~ecwVxa_7|&!eeitU4@GRm_}YXL=+LRUPHGeP?s8O?Os!6IVs*Tn
zP=wQ9(!9%pPrIZa;ENHS+#LSAyfK=PYL%c#o9D@@ne^1rd{}Dg6Jizcs;KbiwLR+7
zYITquO5k}{Sx~Jne;zX+hmBc!pm?x#i(S(+n1Kf@;Y``m?pNpfd$fSxCVhB`=4jR>
z8ZkdK=Ry?+kJAY!}7IHWnF2h^W{%C32B6=&xzYmU9=4{ms!P<
z!gyYlg0?~XN>WjrKY`Bpm1d{ASjL)v_=@nQHB8jr4DeK4Rwv4Gzb%U$;hM|vW?d}%
z*B^r%m&JNVt-`5R(8+wNSy@eK!P5}osx;0w%sbz&hWfX2lG4a6MRZC$?>*Tr
z!CCdgpw=dx8&!uWr_vaZ)g(Q&y?d%y8&*vv>41JwF4iZWl-N3|>%-Hq$gKO%Ya6n;
z(vTlXUcl+RMi`RrBMW&2PA7-l3gJ9!Q5x5M2~GT@T&!}mgI=~tJlO`ZI`@8E)%>J`
z_&=|fjhM#_g7iRAi?vdBa2eJwRJ;BcCzc
z{rMWIRkT7h7`GR7P9ST|;k8dfZ+!ZX4_M1B@WA_nK1K#!4V_15By9Xi9ADxdFFHND
zx_9m5+Rm>EPt9gN=ZEvc&fax{k*wVhKHW7(3`Xf-8O!xl$q?&O+-w6#i;(k2SOiJPyCT-3-qfb)=UfUC
zo7)(D(1jYJkLDh&7DkXb>uGfrcO#^?IToiJ_$O|PKfVhR`u_hMX35PO=HMo`g_yFz
z$9vxh3G(sWtWGUqc%0Xub-W_Fv8)#D`F9QK;!0Gq=qzfB>>%1=upNmqb>9i+8nR4E
z(-Jpf_vR__tV$p1R>Bjlk8Ss`CP)M}EF&KsV4q?yFDziBC8VNl8
zNYb;p2i8E38=4GfXkG=W5@pOaQlCK+;PigPhzPz-KXp@(8;iCKvZQDOLFd6ixfO1l
zMcgeU9pPWs;uo@r*WeH6Lc~Q`fZ_sYi6Ek_xv|m2aVvWgs
z0t*Yb(fRkuhsW1~FThI)*GGP@ge`+xuu~E&FGPmEm&Ru_Kfm)1_Kflg63iW4^vwhZ
z93+RDC35IQy{<^
zVD(_tGT!3r2IuP5RE*s=Q!l^nDSK`@=TJVp;s
z{{%IwXv|6OZHh@9WympP9>~{5uJ9JMBI?$4L@wztIDW91XcrT_`@$WJ5VJJ%K%upk
z<(=;}dwsEDoci83Q{xZ3cThUm#6+2rLkD7PnZ&X6_H~0-k->7Wb;yEkjW##`%X+h)
zulb_sSCb*y6p`UAaT}6Trmz!B!XCVmnp_O-bEj1q%pd&4>ayKdrOX;{M_eHqj{~^{
zZv*>ey9sC9hI_rM%<}RX7+Ga;Q6{fq9g}VH?n0~hR)ed)4_4-rskzm;hTewH-D_4*
z3Vls3ZZ$Zyr&62$)zIcwKjn!|U-_jnopxq|wVZCqLH!`;b*a~H?A%EhWGUl;!Giwa
z`xhrkfkQ~fZ*a&}dZGS{@!c;9(I!mHaRH0&b>&t!za{&jhcDQ^n*E$quDo9oND_f4
zbF{H=keQLD*Rh|wJGI_ot3+#U@P0R#
z*91evTfbdwxDlQH$$4e^VR)+z_F8x?_1Ze0a?C_KECWz?wv2jgj?iOMe^Wc6W8$6}
z^-IJas}y=H*&Y}-pdos!O!mW2-$ylc=S=s_bni@e&J{%?YNQ!;>~?q^)-3MJgsMLK
zcD<<@=cQ4r`z}jP3CvZ+bwe2DD)*v81_?9H_ucQ7>3k5RXYd#26Loawe*x*Qu)jhM
zE>a~cx6{m^J;mLP2}R~(e)WexpTjtA>^6=++^DahaUA}0h7XpX;0QzZt%pB^H4VWU
z%k7!=dCGXckn)ior8QX=YvdN)lIT4-ESvcvotf0@4=ruP-}Xvjehe>$q~GG#&2#8K
zkTC;%qe|9P5siY8u0xwWD28ja$J|{H!x8qU#ImH#5+2Z$z6jst
z>~>f_ELTi>XWELwhIVHE>z#d;Lw~D%MPYp;y9+R*_fFnB*&?lrV|j~fQR`i<_esWu
z6K`&P?pSHVNl5gsyc4Q8vqIX?f=D{Khq13|RY)~+6w*>3aO(sno%q7y3u~(qsnF2u
z1Qk*g7w_h43%6PzGtEcsa%L~!K$rAlzV;^IMKUw-t}nl#lx_`C0s}^@zfP#XumB*0<8=jQ-ZX&Pa;pDz|d8eava$
z+v$B>CFYzBmS9n0@jKn}&!YT`-|3#a_!Q#5n>r&|bM!N=4n^D7rQt_{bvK-(G~N=O
z#<@YQRx1-N)bryzEddH_{fcsYV#)m@xBevb0BvS2vWekmbw++&n)Mao#9O>;b}`MW
zraP{>_Pd>>Kl;RWDUMQ`q?@f|MJNr{xb<-GYuFR~ESwtU(KWP#
z{{Q=F9nPF|icRFPGu6%ew(rGH5b=)op2D6ObqCWcg&g5m@6S<+)9v=+m|BY8G)jbV
z{{9?_9EBL
zNG7J1B${D;cgpBiECchr|80HDHk=G;wn{R#@FW|>$pe;sbd#R^1a8rN;w^f%QR9w-
zMek+iTnk58qTHW*5nwIi+3@(X^z%(V?+(z^-^w)o$}QQ
z`BpdNrsdXLtb)(b*mmK|dTWj`x8`&AxwPiBr*2dJ_Mi2*tIn@7n$co`wxYE5>ANhn
zH_$%ZVp9%7U696oYv$_?V&p~CaXc&x`T2+&isi<*MX^h4*B(kN7DDr-Fpz(Mud6S-bZtiLO
z;VlOa*FX2o?6a>lAvzm8+M*}wC5@5;5_t3&RVyFE5;cnCqh0+TWxU~^vW45S815}q
z2p1MAnQST?cmSuB@0i@$Tti{(GC@PYsl5)G*p|`FptJXS*|}^FneLu5)@Fu`zV__Q+~c{a(<-OMp>GNYX29bH#qnI?rss+x*R$>H
zy)Ro;OxWAo3>#XV?!|J_xLTi9+U%;mez&v0xq6-K9K2|)hc?qUxJAQyyDyv2B*cJ(=oJF&z$!?`qS?>WPI+`%ZA
zDZZD#icY(EUM#Wk^P4`3V%fJ&yibn*az3n1@m{0ESL!*)&mtgEb@i$9
zEmW(Bv*Gap7rQXdOMc=Iz4_G_;z(QZUQ4W8sytl8m~L+-^2hmAnW82nJtKe2(Eaoz
zLcNf<@FvyaSLY3Q@uUc`S~ueu=18H~dT_!_GyEV2Yp8x?%vHCW=+v5ASOGd!SQ%rL
z2t(Iz+A$GELG-wu$*{P?WYnpjt_VKw#UpbtjR5QY8KPHcKt&L>(CHt3ig&~RD
z0r_yTmVvL8A$qDmDetN6_LPveH))(|DOPP<)KmYUos2VY5k;Sa23Vaa^7sHAuMi%Y{1)6}c#_>#Vcb4U{+yPk9Rz;a;fQ-(k_n$m
zVxGLAls29}O!<>4AOT9Sa|+p@81#+g9Da&&4
z#^kQbl}x)fhUWGR@Ot+op*?>kd{R1Z-qrMY`R~wi>P7Vk?a}Rc5Gy7R9Vvrh&_w%j
zdxbO6DU9!=>KMwky%f8RBqm0Su>~I~&#KdM(khlAl5|qFPW+}2zKz`g|7D@G?cbsu
zy8dEH>lDh3`jp~#PrtzT$>R4sMWyv8`zVxPq66?J3Gj=zm(J$DxCzIvH3WJh)uhuG5%
zce{GOS|j!X{B5Cp!m{m-x%_3!5OqG$1?`QXaX;Y)N}Vb6Tftm<7RN>Pi_{~#ce;f+
z*kGa2BaAj(nb4CfcSD9@ZC1!G(MTzX5c65hR6p@Fzz-9@6`O=_;KbtGHiS|w;%v=+
zm1-HVv#VaiOcA>aii(o$jz@uACV$v2jOIMbd-Wfb7tp7dR*CQxqX_<49{TJ_1v0JB
zuhx+w-4lzR0^8fa0+K)N#e4KWn6uVVmRVzb1QBtx#~pcr%GeBUOn4}_R@PJaQuu3c{65Xu
ze(i($49$}3I-lag)9^48&Y8l)<8yXpi&4p&GASatXz4r^eBCm7cIK=Z^O+q3zdqqp
zsH+dVy{&WD4d07Ad+TZ9k_XeeTd8-qm7d5qp)__L7n@Hk?&zweE9$OTlepT+-=mt2
zj`ArCY22A#9}qC!_p8KpYP69!+c<0U^p4&dg+c07bQqFPU1vyFl`D1kY+fR}M%Y3p
zY(zx~_f9y&txzdl+62Z?m_qGd+NyL-y2W;Cljp!ol}ynyMRCE%O<2?mscHCqQ>g3s
z%@A&yEU<#K#!!z9<9DGK7tE|E8CuoV{$`t^O(;=+^UvkHEwedW)@IAJnOk|g?ZwKpth9;tJ%HtTrlO?ACwHncl2um>&4sdWRX$aQYPU!Ocn>RS
zE(mX%iqT0cX1))td^7nCm|~f^h){_;o>q>_eacc#q)y~VRik}5ORO|=H1Zv{eR8Zj
zO&LZ_ar<507Ae-AE6_>oQ=Jmp_B2W@O;&7SlD~uG`{?kOe7nNn34HCG=F`Jj_j*8G
zw#+B}Ae<@uAd8VJl0!c?u%m6Grxt!w$Y!P5>uCk&A3X7J)04+X9Zjva?8WL4FG*jO
zp17P+D@u>U+T@xewb25-);56((#?RjIg4S(fR7o7F7OLj{|Y$ISm523?wa_ZAti*-
z9b2B#Q^{Ogo4nl4Cakz-XDxI2?T$B={d+CeYRh)}5_5w670gsm|Cq6<>BrL(SESmn
z@l+>kexn-PT3GEwo}brmuKh5mtWJ|WLp8p_-$F?y`rEOUskSk%+t(s3+gPzQap_Ft
zBd%bnPDMRxgGkwWmMBYn67zqQ_$@^E=2w>q>kG<{418xOFZk;~fz#-Y{#)StUGaNa
zocKNa$-wtJf&8(7{C^01?+oORA-pJ!+EQPV3LMIYi@XN&LwEEE!i(A`a5HsTe+hKW
zfY0LsJayT_iAyVl^toskmEJK-SmYzD+V!sA1oTu1sC;e{da3*;|h=!l3X=-(EvEBBcsNJj?y9}Lr5NcdD*ZvbUFj;eIDfm5f
zVT1b=h7n6#{$8MzE-6lYpDnx-bk>YLiEfAfUK#a{9x;Ec{Nsc6ckLLD;SWrzDBWK2
zB(QFaqx??tz$fe*`&8sA3x%v2zv@snJ(Z{DRPu1COZu~ruG_KbJNrzu
zH)+wmF{xYd`jSZrrQ4nPeZ9n;+=>9jt!Je;Igq|An>7>rQ(^VfmHlbFy@??7#op3M
z`_^yxx%?j75UQgH^Qp9pQ>&rvL1hx11y&Oe_!M^SAr5xnPU{nL3C!$NeFYf_dG
zveGwGz(F7*uJ%r9H+<{XoU$4rJ$=&^g2)>RZMF9#NyAANcx-h0iv25+i@!IpmhE=$
zKU)o4PB`NYTVRB=hDOu#_hVfBs%FDzHnAvx-!a0^Hl`dS4C6-$YAlP#*r9iU8Z)T0
zfWIy~Puv3z6xsxSC)Wxq{?E9GFv^ElkbeaV33ho0M=o@-tl5pbCRsTiITU;-ER~O6{
zzZ?D|@VzdOKPQlXao~GxAU_w#|7WqaM7IUwsLrnUg4f*>iQ`)i)5sTk67BmOUcNEf
z$5Ot)zG^O&n`u8Q@DBKk{u4bz?|Rz3Jh~mD1wNrm8VyctC(cY98tuvSDt0rjCaV#r
z`*BBOY3~isrWmK5S1L;8xAnT?az`@0rZNLx2nl`_clO4EzLfb-L+8q{-MxRsy6>s)
zfRA}1)u}7UY0i+J)y87&lbI^jbdM`=nCchl8T5RSpnm*|bQ{(O$d7J*hBbJpPtFwB
zGT$pjeI4#)!g@3|xE?_U;>J4ov@4|bZu8f}ZOx-oip4xxS<)?lvL%ZNtcD}C;(l-w
zjSiaWsBfnDt+-s+BjQvea3)=Ko_3M2KIhQ)L}$XX!?2e?{^^1IZxQWi<;HkU5qN{H
zV460C%2?C8(vpTJEKMw?bb^~&@;T}hcbH;5hN&Vv#XD3F;7_5lGlf0of?@QGla}K-
zI#vB2=H3N7iYi+h-qqbz)d>WGMJ^yH5Jk-yQ7KJk{Eo4kB;A0b;s}wM0mTxco>5c;
zbY>z6o$gM6q{Sj>K+uSC5k~}Sl2#lD2_y|T0t!ih5e&9T0Ede}5^hQUcU5(hsBb$!Vo6AYnk+TJJ%7X)UIKL
zK24}$Bj5Ij)qX+b=bie2!~G3rf{l?oV69Tv(3{G7#GE+ed)zJ=8Eira+B!9UC#xt>
zMp>h=`<^0lB|cdc?UB+W)mo2HW9p?tzAw*66C|A6yun5|m0rJrZT2gCAC^jMfugVA
z;orI#zE*hl4X-}DU*I0MYnSg-1Lru@BsEm9+v7KT>xG=Zs}r2up%ZzTF0K7-yFPH~wR1^7NO
zfs_J*A!ov*fQNVI!RuHOhc;nf=8h=I!Eb*8IMkc{D%r>wA?EV6mvm2|o_TKUzDM^=
z{F~&7-!@M78IEvCM_V~1b7!nFMzE5O!7088H8$cX*azOV!2Yrr7msuU*N^0QYVh8{u;K?
zCAX|WJo!f3A)mjNWUyx_^_b!}CquI*J6S-mq7*mhdF)jl@@<7otta^r%Y;bZhPEH_
z%6f0kLT%PkR#impe^iNhqh{raolF&&joyU%*SG0&5o1tIFji)h9PpjujaGlqrajZZYPP^z+mLCeGg_p}N9I?BBDD9#
zUSr0BV-BRh0U5;leTm&z;qwt*W$b}IREuh;-ZfWO`ctxDKzBlQ!QSMsE&fH$K&#=yGWC~E>7aQRX`5P|lqhl|=
z((|j)(k-JSErpKomlHr&h$ZxE^Q~z8RwtXRN8^vQNA!msRByKVdEZyqnKep#$CF$o
zuTq)0XZ!SQ)Og;fmN>a}-a|zOT>f}{K1UnYq>c5gWwaT5AOb;LK#73|26rzP`IIqd
zaWhpw-b1-=70zwW%at2y7$})(h$1+ysN*MPRlTehSFY~}$_UG^l~8%?a-(cjwlcfb
zgnM&+wZIxyEK2BOu#dhPRPDWzRzmRyWqyqfu`EQ!RXIa1G+jOBJcNCPGFwg&TA10h
z1*)3>j)0%5{a(FpM?xCTs)p-MZR$Mc{GoDPF*jN{%rh;ujA{G^+lnHs4_bR%`MZF3
z+pyQT&qm((6~(f!&9tXx%|n$?Gs=S(xDc#!eV
zGz#;oTwTLz{gS7xOKC~ql-4y&@-%nV`U`z>d$ws*A8AS-PHVuED8CToG*7E3&8z(J
zD093mdE2{`={Mk%&r#e|ZRwKY1a49hmp+-|MG^jcl7
z^hTZ8z_C21&MZw3xHK1GYm_*~r~Ih_uu857tPM0bu4tY)T_PG?7o
zJkCD;;fw7z;kl^bnsUbpg!c&d}~d~#md!ouEH<%
zX$8y;OlfWBq&`hu6@JazZkO9z%+-8Vp4QNU8smIg!9~+nxALb1F2%392{WiMD*^ud
zmaY`P6xWBd&lp#v3Wy*x0ey)$^Y&^T`=QuAPcA-)TqJcSqGhdMr>SB|tzUE3n3VGk
z>~e`(FLD(n%98<8==wmtJ)2IKfCgSa&9t{)VCVc?dgw}LV@}+=pK8gpgE6S|t(USQrBKU4+?>gmQx3Oh9cWx~;
zaNhv#YyfvoW7@=Tz@5NbO9hkTW-tlVqfH2!4N9jhsM_qHS>r1}<#j&gVgS6UG=aX)
z(^C<6GH4#f+kr*=6(<#GVw*{MwUs$alxd)nne;TcNS-i_;f%>OdM3GJ&~vI;pYIvd
z!I|%dIrE~)o~@iaZY3&GW+reLLBqwceCaWQB@F^`rdkia^n)*5(nLVp4tlMt1DAd2
z)A)etrx0uIfQ`!NFze+e7wP3-jYMFkrnJKf~E-e
zz9=@hOgbuXgh4qgh~Bjp@VK`L{kL4h7(LOsPO4okRLwI=QYozow05xx{G~JjYv<`{
zX%SAOw$%Lt9Ce}1LbIu*?kA4g-^Tnqp~DJBFI~38yxq#uRGL+-Als&tW}B4nDwy)@
zUTBWJwvr+_^<#z}Y@6L<%3(K<6l{#|IOcr5Qp=hS-iqhITSq|$S%5t5Mo#Cg8{#>6
z_GzBV}2R(t{t2r37uh10dEPX!6~u`-g+IpC04oQ
zEbvwz`2}bIcN59GKW$|xhP=x@3hvsf%e$1fM+sFkCKqe`R-07Z)g{lZ<)jAi+dR2*
z52uNH&2pbwv)uQLiKOPs?+`41@GCQe-0P*%6p?$m)c!)w4f32I2YJ;V#JWLgu3^es
z`1e{X(~28#y0iguU~qApR}))p@;$9=QBh%$tU{jDC2;bz_n20PoABDYg7w~!1u1Ta
zODPqG7(CTHPv@y@Wma=EQKXz2WPL<=LNi;Z^AxQzQXn~-Y)UW4sFDUy38ZpjJv)RR
z4l?y|&`W)sS&Ap!p=OymxjoLD;@0^3u)YhhYQN+rxr#^|tpO&vo4cxY-byf!GE2WU
zL)+jL&I@RZ06&6Km&f~U;Tb`rE*GDgsBQ{tMfnpd>DGYM(~VhIpyZ3$+Afi#`m2M|C`
z0^5L^_1R=LG6n7-3NJ8#pDH{g;tX%#2ND2v&OUza5b<|ewByB*Wqfw
z>aq!N8JaCVtl98al-&&`E!)s+YiI^^%|K`h7(
z;6z4)Sv
z514%&{J!K9_Od@OGj!qjw>fbiX>_*tt}V%~kp&fAXsi-wtO~Njg>gz-O?1^W%Aew+
zR4e5D`JK>M+T(4kwue2b6-4aGI8Mtt5AK45Y5}g|B#yGtYI6dnFn>V@$XNkMV8}JG
z8S=N8RhKGF0;DQEEiKmCD-7vh51l4L`U~~YSaoa^G!_qyMNe_iScry!^D|+Y`AmHK
zG3Q5t9=tTOo0p)UvPeIfVgIJ-8dfU^+LWb1=qKK;PK0%$Q!D8wIjo;XiIAgi=%-f$
zpjTxY=x!!GK^MUS>()&CJFXt8rv&6SkyZ!*;4~gXEF3!IiLDlvjyk3<&7S;1rb5Z9pnXrN{t_F>`G~Z+0ani
zp`o_x8tT1>hT4)E)=)xNL&bAiDQN#R@qZjAJpudb2K=7g0^I~U&5}qz!7`(|$dtCompMVqFv3Rt>L
z>|BYe%Yz!!YJyk1x$9gBFaj+_7N9({o-HlHN&s3)YdZ>00dYyaNj8Uc9hIVzjv5FZ
z)xiExN?fw3)IL2Y{v~k74?faQ$jA5={y{&<9@0-iSb{5xH(k?DCD2dW63ky6#?-VH
z`ibX?KI?fq@X;OTZyUk_@E&y}%I%*poF3uS1Ff7|=K#H>GVS6)CS}!e$ci)<=Z@!2
z_DTEO@Z}z+PORsOt;jxRlM+*y)*R2_6iCU_cPqasi&Yl$78%^quZh<0%Aoq>U#*q+
zwl3~O+LFzsTIxltka)+WGR*c|rC&U+K}spP!ixdH#x4~j!p57zkgCj%brRLSVF%N{
zyMz~v?}}Tvj=s3xPZe_6m&LeMXjaCqw&pk#+iHRIP*kz@I7VAi3m)IeG+0COFBvBv
z2j|qSW@$_AEg={*p%vLA0%9&}^_73l3s{NHRm^R}Q^j1I=~lB6*(@L3LXnS)7;!sy
zYNg8ao#fThAh$V(Vg)rJ28+zEw#lWdA%{U#;eNQxXDj97#_zhyoL#cVZ5w)A#(JaQ
z3B4a^;1qAQSK$TQ)OD&AdV8rAl2!ghj~9WZ2jb17XJkIkF2}Ed
z?nvM?KmJaKEth(hed&Y7<*NO#M=A)Kw1N?y6I&#YwNo;q*2Eyr%PR%Xz>h&=M;mc#
z*e;(@lXD&mVBLgPj#NrQeb!8=T7ZAvQW<+WldC7xX;
zD60FhO>SzxUoE|#Row5}s!U}7|0v;^%byK=DQ)lZWER&fGE!`2OtN!nMeTu=o-SEwglT897-USrWWmC7Fc|wFz)~
z4~;HzD7lA5D{9nez(Lq|vFElFXMrK)XvW
zrG=JSI;RDctg_z9o4l2{2+@Id6ZiBxAs2{tlB`-l#2pjf@qx}kAub*{1;GQObsl(l
zwI$30pnu|npYniK4_f_EOT#>=QMouLHk=E2#QK~8@}=S2sQDxF%ipIFhqxU(4NiNu
z@+TZ18XOQ+ESG}UdeDEK<5QjLms=tCF52W@US!a!
z9>KmWKdoRe;zD9>;={CGERMKF+i!^@s=dqdzo^hlM5y1@qr@UAL2xh2=d>SDzf-6F
zhkru-M{R
zaVQISCAu?}Ci^;2gU)W**YqqFpWzFd6Vi6%!_2
zDjKjWGBUzA?NKbtpA^tqu*z93Ue^sz5x5sK0NJY)T8ICL&r00GH@SzFDT``w+q7Rz
z4_;epy-5-Ic;dHZ`LAuv%j^iq^8rJJlar$wY;x2toYu%?^6Xvg_F6gmqHSrh{L9gt
zTu8I7uqXj{R~x%FNrJnp!>Q~ET2#pLMa6Q$E_fIYvqQyl;%=rq;1RfDNsMPGQ{AG|
z`ha515Bi&c6;u39$Rasq8%ePS#J4EdvXi;G^MjH9@=W9XA0d*jDKnr7?hY;fFyls#
ztK{QVl7;oP$Va4z0rJyYmijb5{Epd}dz~U`wivQW7IxS=ir@VUjWBNu{eM^aNbFQC
zDqrmmy=ghFR(QfQ;m$1C;?4{eSem=vt#-T1IVa&YFEgjC+I!FDi1gqxsw#*Ermm&`
zBWoT0p@+=YzjDrH`MdB8ipN{3TZ3N)b-OF_oOv0k&O>PYmG*l@3
z*=RXW?=yf|yHvbrH*_R=!hN30c+=Gp5B*q|%IKY%(7^5T#kiCKSh4yz#EeQ6t-xqr
zMgU(Q6-J7)itlob_jOvd>3;N7;ayravn=jMv0-S}nC_H^-0s6zfqu5h9pd@-S5<}z
z-0$aQ-u_pLg*S2c^lAYy04N^7qkp5gJ5TMvuGGSc`7>e1NPma*f)%^;$18Kyzkkl8
z!>ybm^db-WT&33)fh?KgUfO@m;YjOf-(O+sfO`;i<@#;hgLxTS%Cwdb*@>XCpqB|J
z0~?>1FNqVnesC%~TTHDEHOk!u3H8?hg5UW7>dxl00e5pMzi*qoV3n;ZfbuxK%bR`(
zsJ%d4*T2H$A={$--G^+JOE98cq8}ndQ#;z+;$!;b+23YIHa_X$sxy@en
z@MZ3!Dv4k%Y>HMJzUHL3yV>NTR0}ltLe>B8SkuRCL!|QfUw{`h{zF?w{I4=)2kyB(
zR~Ma74qKU@ws5|%u5|IJb*1w>c@N}`;U3^092}r0>N)Dc+bXr}#oR|hrMJa|U9QHy
zSJ$~!k3Py>4W?O6)$8tx^T}}+U@QNF$xpAry7?+{Ghmc_z&1WG9d-6zgcdNJ2uN;s
zhrIaDnB|&)Jbf`YU=PjtRNUY@J9ogD7-v<+Qsi99b8?wHb{6T0zC=0m0x`~eDwXN4
zaLVEZ!gEu1P6HmZdq#j2k?0MdR~w8b-U6^}`f_dWbo!MG4V-;i^4rpW_|sI~pVkTt^YYxi+#gDm>Df%VF8dc1-od-j
z53P)*ie~+7e0H+Zu~uIpsim;LK8fcXOGf#zquw8N^6{kwy0D=2e&uo2PXab?-W%mq
zze5~q@q_@m#!d)|6eURQ?F=_i`!rZ2FYK+f3Ze*ZJ|`a+awXYoeq(g8XyZ34seHj(uBL&DDR^p$-a^NEZ<#ulZsv!+2Wz&vAZlf>tyT@3X
zdt6{zTTLa8$ZS>%*~-JbD|W*MC7cL{Oc-O|L%?>FDQtrlt!7dn*hR4whWR1+o27ua
z>kEu%s*B$73;0Z#=j|%lk=3hvcQ};Yt1YU#$u1vU!?gInKn?`3%EP)J8nF(0jPE16
z-yHT)b-2&ohb-umKV(r7qW}-)AyaWxSgzT{;Ij86=5~TcSc$X9MP;~5&iUz5H)V`UuqT
zYq)Exl-6{?
zg_i&Shx)&_O;oZ?mew%!3T%@@yI`xpHt~dQlLc1|Pg^<$-mD9Z+K>lkaB8o8+q4BAl5Mi@osO_=5(V1?
zb_+L_Y?BX|J#3p?V#)K>ZrcPliL@B@iEfwNl}nb%?S^F{8kR{P%jAV*Lrq>N@p0S8
zHi_6J>)wJ@;?OdG3t#^AO!<%cJ_)N~nFtuBy?)t)W&ZSRu*a1t#v
zbJBq*Zd5eR?{l&*)ts{It9LZdFL8I`f=QcKfPKC;c<}miwWZ2=oVs|^o~`2ifIPPg
z@=V}5iZ$;p`2H`KmM)R|>@aJEX=d41Y&y48Iv{c@mn!FXareHX>-Y9u`q)N^ub09;
zxz_=IrEGC>DWzIUJ^cRtIjs-;|EbwbzB_}%yj2`!>LJ)}zr2A%Ox)&!ShfCPvD)xD
zHyjkDCY0*F7t%44=aH`c(zm+LRG-$;z}@`0)R2G}jL@zL7ocPLT*(T1;1L$1+XLIf
z_CT)_7T5!p6BcMrOV}PT{n#FeTYK33Q2tl21PaL#7zDi))iB8I2qiXLCd!z$vfh0J
z*%C7Yg-xXQj|EP3{7mm#c|-4y6=AtX^nOh4DDMy2f2O~ij`Yyq`4hCJ*8j2ob|^))
zKhocTOxNG1IwJbp?I7K%`+-K)_lB2mY(38LHNnI8K9dh(pI-Oy8TuP*+i*+zxj!>VCZjo;ttZ^o_P2_NPoY7O@DvsLk3o0&d}edI!J#Xi|B7)m-P3v
zjfVa{K>9m36eI4`^>>uG)6m~jH~tUwcLwKlZ(QX(b;!`)r&^J(0__v;zPqs}AK(7z
zf9LTgFLzI`H~F|}t!VhT$-hk+Qi2AC|C>DF@PCuXTPdkwp8Gx7Pi{g>)f7Kt@?U#>u#6OC7
z#7%7@QvVZ=_=@+j671;_{~!7Tr|lts;BEihA3l1(pZ}RZyvgu~hkb$^GDwTK%@+2E
zFBYd)d*jN;_EI7~L67)UkMB{_wv-`vPmY%+eZN%OR#vS**Nnyg2p46o*!R`P&j*E5$cwnk%
zQIkDmXc?Cg@~rAq1`0TjMP4SIuAvEWCJ>M`9sbWfKZ;oY*#D;I$6etbux;j${y*~k
zkk?12Ztg$##$)d{gA4rE{&@J+!v6TUj6#R>G}c1%b$`4I{`k^s{`kDrqpz(?;Eykg
zc=^d6uUc%xZ*ds|0+8d&uleI2-`4Gq7kPME{tJIRA77*M-3Kf8mjjGd%K<-6&rVfBSO7BR_egPK9q=+mGt@
z*{czcJgudA>_+_`^~cXTO}i1qd+^6!#|uh-;phH%m!SLO)wl#!Q4;aTa~ZlnexdG<
z_w7pLGyb_hzM|w<9!1)57jllJ8#538i~jg`e(aCe_e%TsH!IQn4L{;>f1DXRYV0Q*
z?v3k$lwnG=5cbCp{glf%RvC&Cw(%SPWv~1`->3gydgUjCz4APH<@fE?$a4SJz4E8Z
z4e4lj<#%l&Y4$-m{eRXL^2*=0Wq5w*oo)|&MG2p=rJTlV6ta-VpK1zq>WBhgaU7k)zk;9QS=<
zc;%n1fLFeRe}6J^>Hc?KdFg3*dc2eV8gjY6<1*s5go@qoa~U7}CD|MCKHyF>PE&rF
z*Xkn+<;!`*gLI2RDOm-N!*RwRBf7zUt%_at<3Y$bE4&JdT4$28k27vB`3vM%;d|_B
zWnoXk+s*JK@R|K~8@>cSv#^D{0kmRAwwP|eM|~zoXUC{Fc%|-tzPKY#apDBxTY`0b
zk^RIxtWfvamB$-Qu$^-yCsr5kCbs1Z6?d=gPUX!ui<(fuq=}Ei#$WNhl<*0=FN8Y$
zo#}B!InFPAN(Owk6zc^$I+{O--5vN)Quo0hzO+ilDdqv&XAVigSS0Kb!5YB59m!k2
zP4>4iv|%R?3eMl8HsbsjVvHjOHxECa-T6acg!forormy8cV=*J0T%4VF1ovbecbz>
zN2F$~%bkeS>KBCxMK?E54`=NIij{*wlX9bI(Qv+ppd1V+2}af1u$9j4)5!wbH5yk`
z^tszP6t+lvSCw;SSpthG>j`56V1#!YFb*!lIk>u2?Aa?6m*)q-2nfS*&~N)f&1$vF
zJJztl3)RP3Ir!@LJ)8$T+dptd`IMb&OdmN5eG_ww(F%dU|a7Rr#1nlDGfJ`?BqBhvH
z!V@;xQfAweuM|ZI@N8`BI=61V)T=RF?)6(cvS+3%Uu26Pp$}z$mRS|cOv>IYUbSp6
zsh;0-Y59-YwZ|3%?}yltg>rwaY5Y6bqrCuY_7(Pel-7I;Fb9ic`^?7Jf9i21e=Bgi
z?Vaz{Xx=n6pn8APp~1_5HB6-{KAEl@%r*~o$ihVXFuFmv?VS*!V&v1arKQCU9QKk9q_RWEE)I+80d5TD
zuiV~mzsNTlvAV}@Bfp_~U=F8VxX@Sf;uObXKcX?V^u0M(I@Hd^d@i{yzf`mCW_cO2
zEucGoBkrcX9woOBwy$|daCat>CByv>rI*D*c)qdj1E;cg4I}D>2TS)?$-ssrzVS=C
zr7{j!kI+_YU@*K>Hg?RnC}ek1e{^4Jwx!OuIiKX*B%-}cJN}=SQByhdR_yH#Iv*R1jYANCI>A_Z)<;e+6Tbv>E-+D`=Wh0
zXFr_r2o1d0sjT3yrRqL8srptIkeJd+)L21;Y0O^*U`O2
zb@m*VH`)!qI(mvmPu#(1_h`MZ+31T_<*c9heAsKxIc{J3T9zyXZTi_9>|&EFoQBcg
zx?A=)V=va&!5$YF$jgX&Uo5n`b``_N?##pKlsT-VP3bGbPm;(A12~yqilcLmjX}3_
zMdg>Dt5``ZZ(KA5tTvnji|5o&64{&9Vj+NY;)v5Job8)anK!zoa(%%^mxhY&(d7a6
z=v8$?#q|Y6m=pS5G8(eqlH==#wIsAlU!_m81#hm>?FIT>Feab@G1FLHnS{|{n{;_otK+8np&L|KvbF0lLMh8{PB0iXUjwR{P8A=
z;K!`A$DIgmwtzSGxclmR+}9t+9yivh#~)|U21u^nS47zbZ*$~j&R{Q&{J_CEX0SJY
zF~YOXozT=?ZNAxkXhzvL->P%&!Th%NE!nP$ZCx?7ITN|HJTKvGzt1}ol%k-XwJem-
z03Y`zFM58m-J~pr(+Zk$oquQ<&xaPQ>7>kNq3fv(G<08ei5ut9K4Iz-p3{zh0v*)V
z8F1&qmv!+BvM^g?(i81+@Hl)4@GC)QzT|t}H{r?;3H|uc)8{)wCF13A0nqDN+#G;h
zEm~0ISaBxNzTB=1YB#+U-;ZC!hfdTYHWuKmc4H?Pdkryl%moKNqyn=##x4d@r@_>{3OcQ^{@@a9ZB9-m}?DH+L6_
zi-e^0Vpr&7u#@n!)c3<%i^MelR_ya7aIh4-q1WRmIxFKvH~(JW_Ri3A35e?Gs--vT
zoK$2rLSAdWX8%v$T7DP}EB5nd%9Hb?P8Ufw6>wsHQd>iw2uCIyORD)e}i2~>l->lH(tCd&8el^
zPp`JIn7t#sTMJ?yGAD`PW=%M5ODcPYtuI|<4P_tgl*FA~FTK@IjG4a~nIg6XX!obB
zYn}HaJdN^viut-P9XIV~Z8xcN+S#s<;wOKA&~@MZ&85A!Ke)Yj@WG&64E;w#rvlRh
za0}aQ^98?&vC`7)+|?`z=UmS64JCpqAdkjMhE#T5>&?OLMCd2K&-VL$7SVSQ0?&jh1%giM-|g
zr1#fEC#@Ev5!>}R`0Q5ed#>RH(E)eKgQ~mkoaU`SG|ZjR6mL{ZZNu#Dj81JE|F|U7
zkCHvL*mVw=w2BJTNSsW>P41EemNfigG@myw_nw#1AgydeJV#f4J+fv*eoFA(U8BBm
z>`fZ@154hK{I^phaR0M5ZI54MO!WqP-OZ&P80Pr}WJH+XmzlnvSDSSG4=km6=`C%K
zOn)q9Dz&=u>$K04^Qq+#ZqL!xhf{)^^1E9ev17#FGKcqU`4-_7v^*RwBRfV`cbi|_
zPHooft&-(6BHvZg#1L(^?443Xtz-W_dXsIPA9=g$pM^Iq!3N
z-}H?EP3x6Jd#cdYDG6=pH^>4W$YAt&$)|b*YpZY3_tX=8G2XWNkk=9QYtTBic?yzj
zUM^!Yq;SWtV-~#D67bH&?dSIPSo>nT_HrAOl{U8ZP3_yK5Z(0U-b!M<@QD4uProdE
zIa;~C-V&R+IP)iU-o%$1>P?Si9{A~(w_dg?{pwAzV-}D3Nu9+nTgUTX@}a)5s_oV_4(NY43|QP+xk7T!s$FUXs($7fSzn
z7D^O4WxgI?bPdz5zLPLIlz*2GU0;8dp6}u}@}W56+0Iw-p&RQj(|d;h3{AE1%o2OR
z0~~qU+O;_itipfDSLZ_>u(yJiWKYiHiPZ<~i}-#*_qUK&)b$5N(RS6|4C&K`d3}#H
zGcK6K)w4z4&dYs|Bl)(@+f!E0!g?y%a|m(=+^%b}6=xzncOX_CUY^&+gXlD!)Vu8Tp-&*1_L-sw!**>(*EcT4~6uq8y;5>M@chE~M{
z)^Cri77=`KPW?S!LucOZH18;n@nu@uyxetv|ezJmiZ?0y(MnZyc1FylQv=Oj!4PFq=Td-wy#vy~l>Bd@)9@siSf8f`DR92(tl8Eu*ri-nPIf~!^D
zvYL8VkJROPXvepgUqbmI$TbjRue+bGr<=jAyK4f}i#`tY!e`uExz2Yap!YQJxQ;K0
z&xO6&9-~;+F#E$XD4&48g<_RsKqX;H6^!p8OGD?-hu?K@SOF^DX24`KDM|wyhjkrk
z8Q+JH`tXm8_v0+%*i0z%walZJ16Sh8@BnxW-7<{(|?j3rl@#;y6QgY|M-%UMa
z4qASMdAB7rSp3KBm9F9AAg7XsoWe@9t&3{@tYmMLO%PB1DqysBHY*g(pEky}(!V@?
zY0#DR1ykEa3+^Q7?`h8P9+`@^S$~Y19={G{GxDmQ&gaG~w=J^pQF_MqB-ff9T{PdJ
z_+NG9%#lRz#*VCE{z2QHFYm64s3<21)04JH?H$(8^@NZ1BW^*2^qg3i8beL=V
zBL)#)ju_$AxFZlJu3Oi^L_>^h?;dvQ#=B
zV_jaY^f#l<8>2#kctJuIJVarMTUQh^8F(Z7bj)6!PW4yfq>bxvHZwOkSwXe(-AUAY
za!x^d_h==5GIK{KsaYJo^MW^)r{7zWGiOkhUgl#^m+0J(R2CqJvEm;DS^#xG7e=T<
z=`Y52U|g1~64GsK_Um~4n6OIRlQ%Z)ZEDGhmXgYX9P)`O{%K)2x5_PhUP(sIEE#a
zA#YCXoiF{g)P~IZ|!zWenO`UvyJ%H9sWgj27fPQ1mY
zeAh;EIbNruj7B`i-uF`s4+w>B>~*rcr_fSyXLmnIWijmC?cKd-?w)-}4L93(QF+n8
z6hY=%C$dGnc@?so4|&o&pem_soh}PW<}FXxXK$lhr1|?9uUbOai5p5Pz!xlZqxcu%
z1NGGH;Dvr$^>-F=&(aF@RLl@+Mcm+b(mHERF}1ZmzsgB(og4L*Ay10Nh8&H5i;Rl6
zfAMxiRZNJyS)3jk%%j~HODJC4Z6=un`5vJaor1^ZluWDe+G~1R`)O
z#*9jC@l)cVw30Ki`<}h_1o#U9QCw#9
zT#KHEJa0hy>1IG>4Gk2R=xyusPc&}mlhj@WEG-gA
zw>IYJP+(q@a!a{E+v_$1x?vrk$^Y>g7aG*-O=_!Z-1_{QPYfAIvaI%Fl7WzC?St9!
zYRIt+;vP1oy9ZtVecV(2)vo`s{A0gIz4vwb7aN$Ib
z%RiCm&%faLDrwJG>S;aY=)avU*oOY8wi(4C&-T?OTyNYga%lDx7?EZ
zsN3X^)O0({@4=S|-*}xaC5-tu2faF_8o$!WPWY5)A@}z&&idscc4Br|GV1s&`Ce~L
ze_j-`LWhblyF6W+AC^`6FR3Bfraava8JIhaxRzonH@*TIGGw1#=F^t$wrI5OApH)v
z7Lk16)^y4D3bkjOt=IaQgrm2?^@ulpxBdj2=~5^*RvKhCC~#%z@@o3#M4N`C$WJ#U
zz9e4hQu*4H#pz0C6L2GWQ*o>Ad-!aKVu%-|UiGljNGnn=k@^O-*Q`$T8F>zd`=A*C
z553Agtj!PNgm$APVK$wet^JehW=O#r9+v$C-L_O(P9w|6NPlAbNZ6D581=E!sz6Cx
z^C$4`5JbBElRg6UWXSg*pi?_K8U}4o%3a5Du6IZGl#$AB8;863q#;{aXh5%v&#sZh
zZ*YS^d=)iXs%W2S(3#m$4n&n;EEjMf1yU0lUS0#|M-}!pq%|VW;)wpVazA&W)(|bPHOr{f;ci0glj%&Hs*4
zu|ts`IR?AGGh(+*bJbk#QiVqZX~E?#$$Pa+@zh~W^oS)?TIZnlgBba9h^dKOsdtv$
z5_z*E{qX$F3(*Rv^b-#xzFc0@uz!O{%S{VH_
zR;bSIHWwn7OB{Dlx4OJPqtj~=c1VExxmH#Z#0tdj{3}i>z1{Y^BFF9J7|A2B)@(`)
z{64^wViJExeHpV8a*HSNcF5qCjyXB{TUe!_n_-|MSk^whH=Tm1jzPJGedydEo$v6j
z^sCRC6Nzf8v=z7o-8S)E$K=nJI+b_Y9$Vp5@FPDFmtVdh<_s)C)Nc9$iqM!e^_32rE!KNw%lXub$csYH_<$6~)|~InX=0
z4J_c!49R}2sFst2eHK5sQuPeaN|+1o?0d&^gSP*SKc_ZZqQw;8H6_fSPJM1~b1ILu
zo3zV^xuo2Wm^+5}@0uMGZ*X7E_29qDQhRi43~(Yr-w-vW`9m`TSv`L%^G_{DDfsxr
zUt;WTqukaK!UOfTINiX=O8-Jb^6GMca{#-!F>IbL=?%KpB_7rcXw9^6l(fLfaMIyU
zseL|!jqppUeJmpxZ;PV#j2cVQlVaDf);~x3f<(udX#esLepdoKJ=ZM0p_OR$Nzmkw
zP(u4T8oq)a)=Vwe*PBDmg0H*ha{9eA>*4tv7wXG5
z+shBnC%eTxmaqe==wY`&`rR5@A?h-w8-tD?t=b&0L5x*fh%-N}#E44_i>2{b>xz^p
z{!PMM5VMpsXL&kN8S$X`@7c^%?_}2Pp+EdR{zuk|cs*0&|BWT7ExI-~_&Md;dd&;I
zB3}Mi>=ohz?g6q_a+4Lyw8EbDidnZ;%vhP_#B1(stjTnHrC=58l`mkg@V$Dh#zdTC
z)mLF>8b7X&(A*p8Q@n@uRTnbs{30hSxlrkkeS))n=Y?WMfnha}%)&Z%;=kFHD{ZeY(z%Fx0Q&1sp=HtMbeh!L=~*|j
zIx_0g>L~PNyDr-eIHW*=j#;nHr{UGCzGl(e`G^_~vWtm*wf8$eSYl8~R?{X#P-y>{=ueCBo;>+x)1~zZaX)Sa}HX_hX0j
zOLm2N^H1u~>0?P6@*yK1h`GU_#M5r&nFb*OL4h%9z+#`iWc#G}(6jYVzbjPZd(}K+
zd@s1wlHm;Nxmep^y;YR$mP1R@BQ23_+1)E_cr*WG!SN3MwG9Y#x(F>6b%>3*(q{+SE5^DAYg^Yx
z!LC8uL%q#+DvM))hx>PdE0Jq9mmzD0$Uo8zQ&QPvt{^>v2gC&XV?&Rx1Y1f;7`7qh
z9G$+P)jMPbWHqA2G4k5CQS_-#mwpR;S5NfZUZ&xk#^(9T+3B%4*DID@R+9e8~F#rGdv^oRq_sGNx6qvXhqEB&GU0Aby$I4(3*}l8ZXJVH?|`_e-eGA
zH*e@TC)x|+yjZ-t^6g1=3hsB&_~iw=ZN~H5PskQhiek_=Zf;$g#>}f?kX5&gk+0w*
zy$|m{q4>kgBc2b!wP>vKf94k?+P?A6__rwnH)(vqOi+$=ukY>ixfg(O)E8m{BB~lLbzl{7*5gs*Q`N_On%obzbD?iZZoyAVYy!Ybo
z)LYTVX3V>*9=8<%X`dLT2~+H#1qW!MPcIA2xiWblqt<%1HT2ta?g{!_
zdwa|^&8J}}k!S5rO9TrMzZaDye2qJ#MNhG-?tzdu=jQA4tJ8gDqw?J}n*T<9j@gS(
z4LCNV@riE;tB^lOsXeF8O@v41#~le|Ga(MVj&Eum^7r!PVBY5je;METUJ*FL>y5DG
z2mbs4-q1fbjEHe6#m&_@bAE_7{Gn}qsa?u{Brmwk$ew@B(=m`ZyzKX(0l)3)Zci$>
z+NJfrXq$0%FJU8W?Qo8*CA1=b<56TjK}5Ld-Bg3%Gh`LvY2kJ~cJ#izy3dIy2`h2<
z!Xj-OQil&zs5nX_OT+Fm+E(LkL6+e&>=8SSvJzH74tfo4
zB+jOl!t(UQbb_aa+R^ni;W(@hrq)}!^#PR+YXkP;zeivXj}3JUycI_>*hBZ)<3h8n79-SVshOurZ_&>g?
z(=RNYjyZ|x5e;G8PH%%Bd!P}tm}&4`fvT?9r%#GkUa7~p9==RH7?9C;s2|dBJxBD&
z9eVriKgUmh9Y0t{p1tF{Zk+dR?QXLt&Yi$S1n05I)aDFWFganI)7Ky4{KkB0hag#=
z4lA6kK|eD9MfW=^P5{LQ9}8k-xQyQG6cv`W!3`68$lBN>S*Km#x93)Rb^^FgIs`snoUlv+zl6dzO+G|jwZ@S{2hBcD==HJ53IJLO5f9>@0*SEhy7uVAOC#k40lcc-ngkqnbf_{_JUqs
z>4k72x4@$2K~099+u7CBL)XF-u!Hx{###N8(7h4yL-Kkd5CzFh&v+B
zG#+}+8wZNm+A&9R1p|=o;kSg#V2{#72UJ?OV~VoD4Iejh58SqPb16YZu-yBWHvc5D
zuxuNI=xW0Wa>7K&meqyWB=-8!iEkwhgKrb14`Vj_QjcEh(STWBO~Ir4Q|}tS_k<$+
zY(SyQnzioCyiMlXo8X-O*#^}^r%;NHr
zBEJmzL*+i*y;`E@`ERvU3-}R`M(RiA6cV9K|JI{U@gto`E_fh$BwZQCvGxmxyPQd!#!4s`uhguH{FyU+09V~i|hXh?O$)u
ze&6*v?Z@6Zd#XpQIf3?o4C$1!mF3nrRW>!{i`3Z#>(_PeNVQri|{=^>`hrFd!J*jOq>>_
zwm0TThDR}pY}MEopNh0X@-lS2`6_g8N#58QjeD!W1J`ts^EpY1}c@TUxB
zzxrM}e>+pGW{cEt)qW5*S9m7NjG6T5dW5Kgq&n>i@>ZqQ_7s!t_KZm%oxhKSDM;Q=5(WJK;
zK1(oT-#g6-I7cJ#nXgP8q1%p)->m$3TV2O`wsj{WKGNvlY1BvBlTL>boxb~-c})yc
zEU+gam4Kb&RE~I1KMMh@Mb1fJ2X9~3*TCaxoMSK7&-0v`@!~gUe)ZDG11a@shc|it
zJyt*Kqkqf%Uf6T*!BJm3jv~kGi{Jd?oQ<;9hff3PC2l@3u{kVtB>mog@>PIc^{VvkOs!96qkkLZ~Z#e(|;x|Vlzg8Wb@!}KT
z(K*@S)k1A@{^optfX*{#f6;F@yr@|U*J`5v-qgqBb|lmTE4bI4mq}kkQfp^Y8J&_T
zvu?5t+7>AnX)h(;{};6Oe#Tb`pJ2{zweDQ{#U{@%FX4T-+q8r-GWBdf#T#z_A-BW$
z9=Z-a46*1rXsDOv+YCqyD8=pbyoF!j9;iuKD41N>Nnc)N&J-Bk2BGtJzsK1=CGV$S
zXm;p)9+!EflHvfpHlZWXO$qMcj2FB1xNt^M6&v~F0%hSvi{y!8dGG?_9;9fEP0DS+
zdBD($mQH1X)g<8rr_^VkNiy%_H8GJ(%5A~UnNvZihQ_TELZw(hH}Vl-+UWD52Kt#<}^6SWP#x(C2|p)su*rFG|fP
zjAEON3+P!Lkj0dKjjvR#`%KB6@d3h#xXRlwFL%~U^@sh>U95JkJ2`4tO>+K3_wemw
ztM(lI>g%KRC-;q{WJNe(=LGH
zv@6()DaTux-%BdXB9(isG&o9dl-C!Q3dT(H9M_oH^U|$64k>!}`o~aw=fM4Zq
zZnOadmucFG`5LP%jT$6R`w)AsN*sTyvYbxRy&;4OksJ81ANyF1f>M0pR>cwxi*6l<
zJhx*u+mbVuWkipe{u{?{D}Fotccs4*Cbx~7h&yrhziFE^22#Y`Ys%46+pZ#{CpfPx$-%1D&e(
z!quTpMQOk3+!R%eW6&oZX*=5%aHHL0)P!HKZ~e%9wh*`WG6w`)L3qmPT;u}$ZEueW
z6*ct!%~6-L7dyOw?-g1Aiu8z&^ACJf{!oE|1GW7^ha^5?!LIYNmeX3x2aK{DFKu{v
zvWl~&k~o;%3rr7Yq2db`6{k=U`FY6&#yeE;cEWN7_5{6_j+>phA@eBqIn2uP3+!AL
zjVUq)aKggx!lOVh+3m+)o+6bZf_r^F${!)`iJsxR%=cHLChp2qr^bxLIV|zHO^(o``%IIZp~($>HaUPt
zlU($HT^3XADJzuBhG@zsd;hixu%_CJMey7ef5|KOpzEBK*
z;N>j3bxG&cLR@=%SRY?G^Tr)ZspZK5ZZznAjN5Tr`6eepnzlmuUDra!7&e+c0A=pZdc@9h4#2}-wW8$5qMx?l!JRv4Z=qA
zw))ckrsAfN)X-+vq9@wZ4p6K(x&0*TNVs<=_dr^`Yt=YLwa-4bZh^vK9km+gVkX?h
zM+wownQiy4`Gg%{!#%sH2OFEQZreKV?)j?=6$^iZJCoj(vE&5`&ku`tDw*Q&YUj5O
z8GF7fovSk?VaT?@z7aUJ_oO)|p~$C92@V-h+>wdwV>LB5@lH7*$nM=^+9!M4*hd081fh{{MshR9I=gZD4B?8^U&G;n{ea#>_FwgH?BvN
zcMe`L4?)s+GazC7Ku_irI3LZweAxXI>TG+F
z?gSz4UOvtHx`iY5oY~+jQ^u9We}!A|;vgfloA0hVkJ$P?X+EK$*rJbGT1GP&%|RB?l_
z8Cjb|J5lqfJ!$)pg&yCCzNaJh?3oRF-_z-`tZ(tlqmgT}aJ_e!vtJAKn&VTVj@vwh
z`8)5l8S}p3{=@qG-+BMH`ri#{_mtBc8m~?K%9*@iOpV}JXS})d#ovGBy!{JLX7X2h
zi97fGuQw-t<*e8int1l4Co@gQoUI?tGfux9H%22q>Pi-w>ozCWGDA#>+qN40{W9Et
zYPkQ@(?Bjs-<6SJhdlsiUO#ANLbL2CB
zkY+>dqS-i?iFj%o`l??!M|_oBRMJA+_mOYi!ZGFFI!BGu;1hZFGtk&pWX7=Z4jDH%
z@7>2c@7yKu#a`2Ytj^>RWzlroo)Tfx4
ztD6^h&&rTHdd|v>`TDH9QF(#lY0B*txGh@tr5*u8~Y^H)0EL8&1FH<58S8C1B`r~K|LLyXP+ZBMC!&CHEa4zxWLu)Jvg
zf0%psxTwnQe|+zm*|QlK6dV*VDr6Lt(q
zQJC2?3>Q&H9Pv_UiODHTCZ#O7$wg2RNx{quxn)qxKobxZ_`RRmklN>a&iDK0?{!|D
zn7yCc
zvT!qwjK?Lk=db>mpT+!1T1)N{dAdv>&lh!tTgfVhXGb)CmUA#`$=Ah-+48*`3#^Qj
za7z0ZkGH=w&G$zpnsChOKC<$d-)w$68#=i9wfpR>Uc*=Hew54<*0-T}y5ld{HL}Ln
zlKF7~bsT8JGsx@+74iZPm8gUyZ?VtE(f6m
zB6&d#$T>QtvRKiv8vVcK?EVs5pZ^c6`K#T2&$8?O5i*VcpYDmhekt>1mD%44Tx5mD
z`Uu&nvHv4V=GMVXSi9O}71xW2+)OEQ#1nhuk~w6jXjuUHbn|B7z_S-#4?vc~3&>4A
zpN4Kic5Mfw3HV_oIn|o>aMYoq+@*-_`te|f_(NNI2{PtBZrd<_nGjiz*?W7P3NzS2
zaw69w8#iRm*Nt3JLSY7ph`-70wUO+exuR4j_eZiW?fIoA#re!Z3rBi4W*;JuJD#{J
zl?V%$N_==iG%$VAv!&z6GooYR%L*|m|G@Xf8@QS2o3TsyCx9}Q)pPz50O=I`#b502
zzYC;k(d1bN&zx;{)V$L3vNm{`TX)0F#N~m0s0YU;(bw{hi|JE1jU|v0xNyg$BSivF
zbt-1&)(fL%rVKaCDzfp*k!cIsmd>U)(PC6L~&YodId))oZunc*E+&B4QL(tLo3K0y}aZ3HAIr6ep}A*
zHN`{h4(O54@SNViQY241W~xzX^sTcqv*n*q*joZ5xtyPz%kgcAa{olKi*tHAJlqfB
zlzh;UX5GXch=LsNw_Bf`n&KZC)05T6p3k!P*r>V;F;#V;7&%;>SM!K1{dTbekwula
zAVaE(3H@Cy4UIVvb+VMSoYQLB
z)xi3CIjTWjme5Z&PbK+7&rO|>J+bj%mUodfx>=QtMhUgm*?pP1TEVBbjl>RSVu!Wn
zd|iY6(Z&uVv)KOR7fCxgVj~c0>_obBNzw)TJfsUo`+Os0U5SN6d_I4Gl$+?*;|^Nd
z*Y$r$`WC`jI8n)N@ptc?VG6Qy5*mvn{OZ&p+8OnuoahJd755Hw=%6GyWR+Oe_Ae-j
zgQCY1u39q|^B>T8R4S6>jZ`==0|jb3wHdv6E}aX50THUIbGUGLJx~pNd=&$M`7#@dyyAqzOi=)@K$-~sNz=@~ZZe0=>qkAuY?5q%;
zg_(#D7v$euQF@bec8AeI^VLK2bVm}API0Rj9*}0MAx4_5p8xA?E&6D1whme_&-u^a
zBQlxH1R{3VjO!tDVc`PYG8ueh*~z6O=ADpwT&#pXaKuJx|jmc|=$2_3vFkW^mu3lthw`Th|jt
zA1}i0p&;4+dJ_qPL~mC4L9(V&FE8G>-^(Yuo;q*gVAJfyz8KhZoBZ8=$5BA&uD}T?
zux`N8vy0e?ggWq4PK0IP{XSSe+|QX>SOT-(TM^sfzX#ftN_7O0mSa@zm@()gr$QT*
zO(aiqh^xKhiATkdDbNYBLpE89Z_XXyE^I?LZ{UT!y
z-Y{1-pJZg7@ESpL@vkB_sWE@%6BQJCmHMLJuHf%WL*^FEey|+wL;LTK%XUy2*We6T
zcKmL1EsJ{Zk8akL!O``9b$@i$#(y`uuoM61(VY+<9Np&~|L>!Vj&P5zWznzyZgizL
zXy1tRkYhzcxOt*wK<;exv_i8Gl=ZfVH14K8LaXO#0=$y(6cj}
zUant!EV*vkk+-V%W`x@&WJZ`B*xl@wl@=4HK(;0Z)Q?zFobE$$6Z&-SQ(R
zb>4i-^I0{uCS{=}?p}Xt4DaFTi5*0F$FDKdzVMFWWy>#?Wx^$)ecjM)?6>-MaA}f09%2-e-W&{}oU^hSU6i
z@0IbYy`H+9&t%Lro%LP0{dBkCeTQ?%yK>$0_$M?2E4`C?9|#U5xs1XTb*q0#amu{&
zrKFFhCehI#|1n#JrvsDm*|_b7td{+J7s>+{E!737RX+@Iel?lW89P(MKg$f
zSIqnBR?0lF_FmVHVzTdRgL^14CnDo@&+d7vpZxu1Dd`KJ~_U@HbAjdE7mPtE#SX~D8F=-!P4=t=s9=S>DS4EvOY&K|`Smf?w
zX{}EyrS;uUX@_-ES`AQ4GV-cTi30WNs_%2Oex0y%YW*0z!M|bn=Zk+n3`(^&T`hG$
zU%(whb=K5|shhcToVt8=c|cWC)sBp-P4AYH@8*~OxJm;b6|G+@>Oc$l)?Ekc+L3X(
zaX#>`h%5{_B}_Yr{6&1)2*%+c8szT3lA9sZCmgkz+ctgTv60orBa`YP>;Fb2QJz-p
zTfEE|ZZ5RM0iA2qvyf;)$lMKci5zoma?9%FKceoCQ?U(mjwRGBI5N?uMD~-J^#olj
zxgsJXJhLbRJYpm~GI8#I;E^>FkI-?j=6UiSDj7IK-80Od)MJRXxGX90z47g9KKwG)
zQV5i;-+o_>wS=$r&UdeS_N`$Om+ww9{Y%n{htC9tPTaVdLEdRKKEye{0OO5tPGcC$
zBbJ+YeNFLs&(M7Lzo?XX5=WGm^0IeT&b6Pqd8kT8cxa^qI5aY6WR*-O_`7*%rJIL(
ziV0m3s!T0*^M-4HH!8yJ^3fg&-c$X*Im6;fI0KQ_u{7B)$R2PrW^rs|?3C$6(+4vy
zi0hu|0atK+UE6^_MY!TFMP@{_dfwB3D{9>>GjXKtll$GXk#`H|5)W{}hix+GkUoS5
zCeKtUdSB`dG+=HFF{k%GSWaBqb`Rx(ADu}`j6#V~F}3?q(kQLK>TL!iS%KevpCq+}
zuYC_10_8K={S|rg-u~;(0lvv4JNS~BR|ok>`aR>SGdu@z^;4k>%k2|LT*!Zjt7oLR
z`qZh2uvg-qfHH7=s!QEFM|Yu7b|A-jvr#tc6Aj^h^%eEAd-DQwr)Y+JkhcfX@TriS
zB;Nj^So@!Uk-1~-XCv0W(nB^7YpJt#z6hZwF5%=it$SVpm
z_TM7ugLccF9YXn#NcuxlY;4M7<+I9-&paGWPc`?UOz`$8DUakE9GU~%NJzj
zvkpz6OUd_#@UDE8Z}Eyl53T|;amAo?bFTvP%zk%tJh?fFEra~Fb}CGX)s)|Yc~c-e
zd$l9Fs0n6G4{%d%0cWZ%X#qc{TNb3(SiAcJ%09{o>rc`PY*HDyU6KLCMY`81B6rwc
zZ=CO)+gj`w8#E=annx}$f@s8BH_3v|Wpi43G?R2jqf{vD%FzmeE7H$9=X1udED5(y
z_v`8PXV@Uze9tH*cTo}Mtoh37?d9;eQ1IqXs{NIr`;(HiV->QbvectNNpy6OyC39c
zh~U5kOw)$oR;!JLU5X&Yq{JUDes4uWoin3aMkL|GIhv9y_zX{F)YQFM6Ef6OCuSDf
zCYcj#b}v@J-MH!c3uHn@*Ldf9fc&SVgzL(*Cc(
z9_=}-PAW00%S17(Hx|}A*k4Y~(+BC#X6V>3LuB5(GHvkahd6$a-xGw!SR!AgF*I!?
zBXF9{2Itu*IYxrk$!NYWeszU*bm~ZL_zQvBv9AVdgLedKLw!eTL)MSf29J6~8}U@2
zcDw=4Rs^D4Af5+mBlh`Ij}Y_%U=?H%)Pe*55wSp{hIeSlP9;15;6u72Tb`>L}^&`Q)s0~o3n(6+GN-%gKgFx(yZ$85QEsCHI8xA!90tqev{p%
z>@^vKsN}2{_Tw$}?hoPzUe~^N|1F{o@=lW+iubwuHOb0ghdXX}_qW>cTds0W8*$6!
z9VaI%lGqZUS*27UYAZ;^@!mgAfWNHg&&wE&r+=P}jFJ@YyH)}9XcZ`D{4E!v13VBv
zOZluc?M4)vHI~w>RC;JbZ@IJ)moEoiLd=dQP;@Rq?eT!O-Uj$OE0{l-!YWrX${ymgDOmP))`yNuHh=x&I1;0Br
ztm5h=i$-a_+9Y7sTiR{Ch!YV#JI9M77`-XX+(x29JgG|?djs9S+DR|-j+(-vT)M0~
zq=d_!FkUbAcj?!=V;SiUM3a@O{eCtnL
z+Mb+s(y2)vfnLIAJ6VZwiZfbVZn{WkLfmv=BXpr1U+HR}{h=riHNzJ108KJ1{8c5I
zByNS(zc+G{QpEmtGipbF(dhG
z23(*GRkTU1m;N9hi}m|`4-{;GDU|f!JhiZxj71ff;vSPkYi+rN)^-fg+6&*15{??+
z+gQ2n5-geD8ZQN
zd@Csn6^NQVWrh-f=(fb6%~b#Eq&iNm+w2Ig36(IHh+!
z;S$Y1fPuxZi^Tx-pWHkG{#ftn<{g=G0qz#RaPtPdZ^F~zX{{u5A#c9V8_l5-ZOT>3-+jf`B;U^6dL6s+(dY(0=z`tkuvQK
zrKfrm$y->?hjgwaWx-pK+F%bzkW&xzt`xo}QK$#+{g}57faAnR)vuBH@bwVWS@M@F
z)u=D~tAXtd+b^VP{t@u()^6%#$P{fLK@QUlzTT
ze-bm;4btkCR^UdGWnL%Jz;yP%5#8jLd_C9H(&}RFU@L}J>N&W&FVWfvb1RW{?v;!M
z#au@JzT(yKJQ*w5SBTs*LGF=w{$8?r>I0B_=Lh5-iRdSC&wS-Uxo5tDTbj#F77c5@
zLe}aMk$VlR54z*|(}C5Q#6QNouMNho&i%I5;|ZNz##l&Ew$tmI_LtwOZIkVzKA
zrCzl&iYp6*w9SawA8T%-arbr_`yBF-qKEDn{SHya8sXi#kyrKn%`Hn^d61=1E?+f~
zrj@Nu&wE%`g^NVui~s1xUQMF#`9&@7h`Fi`vU0g1DNlNq3aN@On87dHE4i%uAA+|j
zJgPN0Yu8sAYY*bGUy;$X_%0Wv$;s=rtKOCgOYQ0G8I9U})%p4eV09{7i__r|q>xUp
z)t4PJp{J~^@3s&1RzUha9Pj>$_&_`@+HV`j@d@3aE=8O3HoSnSPbkJ6Pc;xto76Hy
zilzk}Z&4wd*270t!!J?4$PZ1wfnT&X)USz-Wta2=!E5?R!DLyN)8S=lwZ?%Nc7
zk(65Bwu7@@@dze$pawl8TqNq)ef^Mo*ASTTd`_nvqY1tRDRCM5w;w17(qQ(9ZqpMA
zm;4Fv0mepl5^2`oYLQkU`50M|hxWE1Z0O+L7JrD0*yFI^U7tbtTIZ2&(5Y`@e@@Oy
z{hB;MM!47PgL()w6#1t(e|swb#4FTiXM)ln&nQgiWz3UA#~hTi+Tc$SKgGY=tS}^N
zLq2wCM_+a!ws2`v1c|*UPfKve6ly~u?Hc;waa`$=gC0$gR?uf;%y@17zbNg79}piK
zMm4$P1);U%Tj*+G8N4(YBRH%h=K$gbX=Wmy^2}56F=`-(eu>&1x0}XPx_CMBBe3i+IEp})ErZM*;#CnHoLk_vMdyPB@)O?Oo)#%iR
z_55n}8@+*isw#v?96r9`9a5jEN=Y^5nt%tf!^Yd0;E`GJpdPb}-^9XpIiLkX5)RD%
zGM-VxCQe2$^k%pP^B>^u{eUFY1|K7FZogg&9h8DvJLF%mK-)c~s7AM>gRWgdH1`gE
zt@2wU6(^*V-EVTfQ^^`8S@>HCD)cl*<<`R>IUqyOQ+!3fmcFd2aLdjA9odL%&RPmM
zlaHwHOtQfKh!en$D
z>GNw%&|%2>>XfIcuS?}X6~i3T+7NF_vy_Fc2ND}Na{N#w<5VdP`0wXhN=flbHDwn9
zDgJW&6Od~z&^)Ld@fctKyBcuY^3}h4$ERa12Jp;q5B5p#Lf-6ENVvfC{eM#gv8?Gq
z#IlCvXMRI0+cd5prMGw%;4W=9xV(l}45d;Y7gSjBHi0F&%%}r8ApF|lOTo7?toBs(u|D*t7Q
zzKv)X%six|U3I&^y`}V5A`#(F_NC!oG}9;J@&D^J#fe-Vdv#q~Ccf@xPmcH4tKX8o`H9-^>`BC}
zVt^bw5Bt4**7ExOkC3BB9e#j2%^3a&#WCysOgCYeK}2{%|w^$ESXu-`v+%tR;8$7&ftr-!I{N6cer;j#E?z?
zl1N2(iI$6=OatMTr<|s7QLaJFYUe3Mp;6)X@eXz)$a(yO7NGHnx`LTJstunDjSJ5r
z6qmIjc&;YTpSVKilSn;2>Dd>_>eF!=rME(gM_Qa-pFU|D$s)nqm`QwUm5fM>N>C?u
zJm^jBvp-LlW5o#VLUKHGYU3&PPvp#$8ck$?IPKZHx-4X1gy-UcJZ%VxV46%{+W2UZ
zHUj-3eMO&0zY*WjF)N4kh)6baj+1mO*l}8(|C#hwI^jv0h+q^`zh6sw{9ydcLz-EZ
z^bIqBXy)#X)s`s^(oib%XWmvdc>dIXco!r3{YWMap8jSO3(>tLld@ow=UylR?+op%
zl#ltnwtvDTAJFze5v}~AOhh(!U?V@Gr)*$NW!+`Hf#8TzlW{!G#1=}W#+~U|=~t-x
zSLydkj|oBr=9_32m&sbvAw&89)2t5oz58Wp=v^V}WSG)f4HWN-mggVg<_LNGOTubEE;JN-h
z{MVG@2j_Lg7euzpAKE!!;~+bSpBimG-}BVBhzV`i~Dp
z^TVEFx;kE?CNu%N*zd}x{vwrUSjj3zz7w}yg@+tubIZk(?y=dJVBRJW%K(w@`bBQp
z`B2}}m5<5Y7J=jNhX1$wlF73ow}|9_fPQ;P(>0dtgDocL!~Wg<{Tg=Z2BJ4Y-n2>j
zF`v~o5_X!ya_|%Jk&qX7Qd0C(`vpGR6MBL9s?N&NBw{Khz`cVIs%W{GL)KFC_2|Qz
zf0Js2?AiA3`XqX)vo37}?VbI1B_I_JyJukyGXh#d>wuPk^RD|$tY2MA&bcO>dLNRu
zDt6eQv_&s+-ISlB+(`NiuSR!tRf@m6&+eKquPuwr5`8FKh^*>(!fqM|Dj{dpvPJEI
zB+BUrw@hq#{s&@hQ2nIJ2&~pL-!hoX&y*t;tk{hIFFo+@#z97zbIb%uy%!#3IsNi6
zIB#I5l57TOzpVd?cJ#+C#AV$h{lHk=Cv=@hD>+%VSy-Zhc_4cEbE_%gK6Tn%O6WC&
zI?q#AoinqZIndtn#QDKB+qa*T#r)B3t-)RP5bS*3?(&0L1nRs?`VH!QKvx=|_&nuJ
z%wQVB?RUZ_hvFY;#ztc`0te#T|`KRF5
zbSmWIqU83#Kx(F?U4L;;p?OTL&T|ZO=~xm~zwTla4cQz;E6!-cpO)X$FOF)Ani5kK
z6B0{273>V92jzcUX!SlW=SC~+K=AT7Gxy9#Lt7(FMn8pyJ^ehs&uPXlh2o>N&5<|t
z0c8)@krMxAG3~3Y4>>0F40klPPM{yc_rM%j9<;E$h9Ko5vV-QQv((>b+mcV`^sMY1
z@or89TWqE9{IbF$Hi5HxEpx?Awq~m90iq=%-s1}g$AF1xrU>dMU#+h`WW^)L>{WBxVYA9f{`}PBuIpb
zysFd3eNQttE^d8hUd>#6(7fTt5~0_W#N&oZaZ^v)AEZ4}_nC#FzNO>6;<3{nEq0e1=%?Q_LRp$-%fPIAPKMlc$}{Ap*%8!Mr-=(5Ujkul(O7bP)YI;fM7n$SkjKyZ`mh
zfiD90hgYu{Pu@<5zW&|yVh00cQ=#g%znh9$*DwWyJ{-@upFXbIOMX4bd2=cgDi)OK
z4gR%tWl`!fi>F#4d)F#C{6OCHHlNg2&=tIR1f>
zHB2SbzV7k8rqMRa|6ka}y#7$@D1@y$W7#o({8!@{e$ufAziqXr%9m<`Uz6jGL#`bi
zCD(>NE!Q90#h#Pe*oig}xu@NUe;?!DC-_&0f1jcafwXaPw|sOhywPQpHXpU@L@ghq
zmV&3{mB(t?q{{zWFUd&S*RB2t)bYQ1u{cWLwBvhZgA#8;tZX`2ErV|;ynWXw?PkQb
znJZ*dzY$
zVP(gSTWSik$qC02DLALH(01}LeElMN=laH)!eS^n<`I62%|MmS*C@=02XiRoSm$2<
zH}96O!U^N|4H;YrdcYnWRmYE(v#Mv0eXKra}Z>2%}|Nb;}Cjv0_$=>qqyS3O$j_!1LaH
z8AH}|jv(!3#2ayDz2xQdaFR$Rw>){?^`IslA;-g1g1E`z@{;
z-7o)x7bOn&x_966Me=)@BP@2`f&0X0F2w8k7wVN7c{HsF2!(%l1l4OBxp|A@>)Or0
zS)^p^S?Agky)&Vh;_tBXE$N%5t_PBq&cB(C&(ZF^(kI_t(@)-tm)U-uvfALOTrpzg
zCcld8I$!1F{JFIwEvzZ$v8$tLS<)}UI^
zEBRj9n)xg0>mAP_K6B62Pa2Q8D#A1NX3Z4p8k*`ZRnDoNSU2fN6;-&oLR+=j=aj_{Cv@zX+erhL~^zf&6$;(vwSOWRR)x!yTRUyYp^>r5+Kw
z?dukmA%g2MW(ZF!^rjkQfRJz0+aJ-oqYu#%6Kdwy77x+pZv$3=m!Fe08+!e>gY)^O
zE=sT>BUgP_--PJ(VelDHMAQ6=EIl);Af29p+m@k=3>vI~iM!QrABulj(-7OhX?WRj
z|7(J;H+lX~^DhqK^`iOvZAuq_=vQR46<^N+CdoFv%A(Cb1KD_#nkd+V5`d5Mq>pJF
z{0A+c>iMI!LGT8Porrr}8^zC9^{gDc&VTn)fYWQ0fv^3q$4z0i6td8zHBUkox~%3u
z3r0S(dD4XFvw}uJG1vcC0bXONn0zwk)aj}-?s3B-kc^p(Kh!L4D(*0GzzS!+knyJC
z@g!=Nw-x)@J^YY89`jhmQm;nuG}{rU3r%XM_*Uo7rkVi6cLq@9!!a(rZ=E*(I7LG~b&56mH#P?<4!~Bl#@w1f?dcFvoyh|Du?zOF@@#W%99
z)b6)i(;?N*AS<0K-FHSwR;n@Pkh}_G5!ik~;k15+`w5nseA4b1L+y1~*g}VR@{_*2
zQqsm^P(}X-@BXM$B+<}4DW~;3MX2h>6NK_YviNNW2Iw;g9t((2?UQIq^Nl~n%$WZT
z6U7fzQ)K>C9G}_d2`_-GHcy-y1w<3Srl85pFQpst|Ep+KF)U2nXv*#}no8NPQ%p4M
zBzHpWX48JZw5m
z#-veZ()I+zqWrZhs6YsqLNW;blO>X=wND;a-A~?$OS%v*yVS7VpJb@RJRtXia-`1c
z(5tN4u|FY4xFY~NASHP5b*os?dh~w#s_~SV$zIu}cP_n037NV5WZqxhPfvT{(1d86
zxmJ(ZI}7+}M0ln%GgD7Ecgfc}VJ=OwL=~EWHi`2jgP38aM3NeVPprnZaoZ2M$ZApzZ-r-lw%^WN?kB%G-t>+W
zHO%GI{i)NL>F<4gi9=?<>PAkZ2v%-B4839OU20pIL?y@fiH`TG#I&A1yU^qQ+GiOo
za}|W!dy4U8I$QC5u{-85uc(&QzJRg)*vT>W9iPHH!O{ZjOo<_D%g`e!}Z;GN!W2VEaRbW0FO;)Wi%g!97
zY^-Ke81)p>zUJ|svyh(g<4wEOwA~y>Cuhzt-dI*(UGLJ4gZrVu!mmdhzed
zZqhrNTM-~c#}qr6FZJ>W4=RJvWjOT}R?}V%7}h$+Oj@_JhSpsup|pG3fKpLIi(*^<
zbES4O2P}pghe%7Jm+Ce=DP=lUm?0%mmly_Vpxt|`?+`p?*U5OMTXw&7Uw7;85Y06o
zw}KD#$)@xxA64wMdKd^7GNq%Uoy>l{DHM69bH`8`%(hPc5&Cuvx`EEIgo@8`Htllv
zYvW=yyv~YtI<|5$y?|^vzQ@muEq%qXaj<5AckRkWR{1*f^=$=5vZ=6BQXT7}eaZSYm>ZecX3caH7Bnim#3LNT`%<1pF?
zuR<^XG4McSb`3+$kY~w>aL|Htz_yFqp;Xo`8K`Eyl1jkL;g=rCy!PxJ%jkr149(pbfDR0-1qviZQW27Nwg>C~U|97=PN5Yz5n=^vh<=u(`crZO#Zk;o7Jqk;zkQhvK1U5yOE
zLvvB8o65%D&klT%=Mqc|liD^=8|t;0NKGoH^UnF=_4xZ)%9rW6bG>*6{)X2abK~aq
z;&Sr$P($=_Jh!1G73AH0nkN*WcjCy@r^*8iXATn@7r3ZeE$BU{R`MJkr1hblgx25d
zkyg6kS29nOpEOU*Eg-uEtN`Ll2qFxZ-&}EC;F8L1Tu@aC>LG&I@k
z*0bVue`J-5r8SR@qwH&=XnXEBYRU&)x%^*`47FS5(!R6!j!qv#a>@wRC-#d&X@1L4
zrLTvt9PhnNPe3cYb%JU=wZ+txM#so^%aAcvPOX^fR|e5-6bp*-up?kws^M`IrIc
zyQVPQFA|v()}J7>PFi?e&nNwJzuYm3~c*luD}{dXUV=
zxCXf$2^x;AtS
zUGPE0hJWUSno_x5+}+D@-+(=EsB@)1U9!p9J)GXYwmg;aXLb(w(ID}nvugzSk<81*
zK3{pcReWvUJ*SYS|7>`?!j?*N{N*&*;>S?`bofr=Thl0k(QF<=Rcx&IkncFfl)wJZ
z^a7zbV6(y3V?CooOOc!G2}%QL1sFt-$hwsy=#y);5oh{P_x01g8f#xale1#$KOO6F
zw^Gxe^4JRh){8`PYR6X5gBn7Cm5JGDjx>)d7N@KF=olJ%Onb-j9;Q~3u|c)OwlP>*
zTD#;A+_XGeTDz(bfKWVDdQ-iPyb0DyZ^mqI_vtXWBZISx*|K}co*n-MmC8j5IJe@&
zdr~;gAqJi*W+CfN7weH9(puHm1M7jniS@2~#VobP+1y5v@qpqx;L%@eaqbcEF#HuORpkl{cdE_sHEftQLy+lQKxgB%TMK=`f>36gL`r$5R}QD
z{F%|V7NdJ!m-s!kFejDcS4PpKB`4a5XLQ5&P_;Qf7L)&yT4GS*O~kt;)a}g>q9uEn
zWC@#Ko0xIX*4{Dn(!yF29c`Z*Lu)ME{kTzC9d6dG45inXEnGXHn$Pi6jHMDPg(oL)
zh1M6!LyWKk$!u$#Bbup`YjugcskuicRqLK>p%_)bG40sV^o}yS`P8>18#O=^&<1Y-
zPj|ZKXD}9TFkUPgqj{Yg^&~WzBSjn&lXS$+GO`;T8vk)X*!P%@xWsP>Vo`fXd(Q}!
zPPGTMjHBNy-D#YA#8B!OL3Ao*3R(O7C;f*LooY!6vde`KyI+KDJSB~DW__V;%w!Tp
z9V`5Wn*5ABOojPU(M86*oDgmkJ3Qy0Bizcr&>?GNBRB4~km%@1miAYc@4av1BRy?o
zw`U(mTo2)Lq7k2m<($8;TShWH;mou>XlmS4>2Gc;H8pB#Bu=vhsHfDK5(osEKvmzM
zjvOfvYq2Kq8A`$&;ogtT!zqv^@1b+LxkM`C7u!2L7aFJ?G9*Kp!IW$&%;j%1%fgW_
zp6vC$u=tUD@y$4mR}ad~Tz=JlXgb;mrcZoxKQhM##Aur0^>!ts_re<3Bg2rXm%rU5
zlf%w{AL~LYo>^Gq=u{n?DoV)GALt$qWF`YI1@zUOdv4oBSm^3
z7LzjEncvF9>B-p})VS9NNI7<4Ff2OA1K|VSs
zQ(%a&M;sej&(HZnX=i84d3mo)K!({{p|I$9-BQ~vo&9{CGMGf3s;HzG!6an*eu`gK
z6|y-V1KJ3(Ifl3q8ai?c59mXqHbp68Zq8r4pmD*Jmx^B6kR)5USO`ga6;zG5j4ai?
z)am?2-23m2L%htd3Y~eWKC+%SW)u1?`jam*&clH8$03zgUa8TnmQdQ
zD8SUZ23vW1$D-4)N>EIkvuzc89q&?yN=>`7DDmRbdm8phPuyw*|3tw?7<|zkCr!R5
zb*4^#x3s;Z|MaEk@T^c_#eWsxj@Em!=5M`pp_va
zqMh4vX(BD0_wG@rpR#de%=nJs&1xkX#eQ9(xjnf56KS^aM)`Gqp`cS9*T)iCX(Ow>
zV!z8xIsH}PS)#A{4%Wl0y8Q3k+5eo>j<`;Jr#<-jj|Nv_*C9=Fg5H<)WWyavQ^{T+
zWQGdBA?;XHb}8EVU%)oQ>`s2Jh}+U8g?-kI8q
zm4(&7Y}LQ9|J0Ga*4#^Eg?jg6eZC3Ldi6XhSw6ir@|~$CzmewXhI2hzyFVc21*SKF
zwEa{*kvymS_?4|xkfHO3UjLwS17wH6_nZNIspz7~&01_(F7%|m7XG+Hsd@JnZN~-m
zaPxCjj6&l-np#sA;ov)3WqYkD2}HxJ=@YNF^=T{#L`VEbjjSX$u-3G@3cfVxD}&wj
z^lqFFcKs$_Cra{lpeFHpE6#sTws}B4mgK&AzP32r1`nFsWR;M`??$2Jv(n)!b{_Zl
zyImn4t?(~6`trp>^MT9|p{};+aPkj(GnRcnq26+$zNWG2Z298zZ#5sRFR7ejYhN?#
zbJM3@RAIWTN_ITqXhOC|2^35B&XoLwoP&qm>#hNbyKU+LN18PadmKRuTH1--TI|bvZ_BEe>x^v!JW_X_gN>X;p$&R2SkIL&gsmx&4v+5BzZG>MYGzDHOhoJl
zu|uZcd1+bF*`(No2N(Vkl7sPHcJ#SYG488wJ97F)ZdH0MaA>^P-tEPMeQE!QmodZM
zG6NIxRI1Uw>W&)|63ASRHl?%eGhjkm>8itLV+qm($;2`VJq7x--yP(O>sUc>C}<-e
zaEIVRTEj^{>%w8F^dz{D$=yk09{Hd<)L9O6KyV@5;}lp?eXY;V-T}HL9V5Qi?a6QU
z_R%f*l;TG+^B^^4u(2sc`JG{W4L1~jD@5-*kZ&yt{*gPB16qV#U<#(GKpmgKaN)Pi
zNaiKs=sR5C;j>)O;cCuSQ^?udtW;!`I8^y_XtWEwTq;}xXTYQPyYT3%`{mrDm~UV?
z0OykA8i&3l7nL=yqld73L}sIpUd?^9F}|6J>-^>{w{u>#L+U+mMg|?~?SGIF@rrBY
z@4x>J!P7lT(ev!U7%>yZ1v3bOr^eH>H}cf7bUI3yai3b8s5rMS?*3%}cj}c{@F7|t?9GVGMESi0>16?Y
z$lGVVuQA5x#GiMld
zY_VbDR-j)hof*Xj|3{$hc^z%DJ0?+Q-MEtPSnfdAYTxGK2oly>_AE}yzyy2c#8%6+
zKhvbm$TE6b0k@Kiuw1YZ9N>4F-f!6RC)uJ2FN0eq($jtOlc(!4W*Fvdl!))d2mGoXc<<|(G#)2WgQ@m$w5o#$OWAFE%=
z5Aj6w+oYOh(c<)$Bp?n=?Vbxnwwj>Yq}majD{)dSZW)Z#i3iUxaj4^P+nf-~OzSV$
zi3uHEJm@lpBp6;BM9wU!hUW)Wa>{NEqDmSqoK6*LAUK-3Radc36gEscL&ua{Nb$4G
z4;4(iVkl5@zPvz17sMB44Cpv-Kk@4|E>t)+74q_fYtiAEPciFa_DQzTx0m0jGalpw
z@BnTBPqnu^ek?6vXJVmEmk~j?WTYjV6jF3drZf_c%xbuh}^b660TKYe^
z7QM_pibc1>kMq8W2}Bvc7=m&j#xxJBPQ=V^Z+rhB7m@@VzM285u>InmqeaLYr+RV{
zSH~T6ypzahw~d8v^Zvm6S)1Ht9=E!0;#)qnG)liMr=4^Zs$1SpA$qRtorXIZ
z{y~rt>a2gI8a1m%QuGN^XdFB|q077beDOO{r(o197^xqn79aP#CvH}LD|*N3Q=;7S
z%ljkvc?a2}N0L~?hel9Z^ZOA@E^Pvu7~!GS-xOxNyKkaVqM7GEL-g1peeLn$0s8;f
zX7C1~^+^pAn+Uy^b0tjz2aY&9@m%C7@x@IiuSM&!kLe{^{_sE@WM^`X&a&Gup|*8j
z6DOM4CP!j7b{5u`@EPG1M2nX=R*`4i9yjl0@6DbQe<>c)f0NsGQ&UVYvy@oEPen9f
zWxwF(F)z
zCKPf3u|IAFIt085!w~z($^#D*|H8ts2mX+J!hwBpy6l;inZ0Po7KU0
zgP>RwWb^qmefhFzxh61-nv_RStd*+BqjU1)u|TnARlVYrY5h*CzXA8Dr#goWe?z0{
z`H`oU9XeI8VR^^r?E+T^QoGmj7YQon{O#Ug-HSqZvoG!Ugv4GY?5(VbZ@*p
zAwh3vVZl?DY~uTxSCVs~s4niSf@a4jZhu2msc&D4J{KcoiW%$$K0x(%oS;2>-`W;)
z5~rFBR%h*`U_)TEdvUJmYNfWh&o$f1$@e(3owJo9E|2CL+Ma&PbPczyp~9B4WEWii
z>CVK27m3x}w3DU7b6${Z$Hqf89PZZ$9CQ*A-&K(d+c+l=8$y}1xM%TjuC!9l4ijbB
zRI-U!SvAda8kSt#uSoXXAJ>xGl{0<5LtxD{iI=~+XICzweSy+>n$lTY4S)1svDKH=
zSt|6N%1N7xawp~T?|voogZ-ujarO4~sc!TK?5NejOXyJB;ik
z?;q!n-9+4iT83R6IPeZbWR336Yv?5h*UK_wBR-UmnMI8tBP`oFr_dUC>X!}jT~nYn
zEHB-eD4yNDSsbpucP)Bb48N!&;!I2is}Z7UWV52|RzyG&-;(~C@&EpGeqi8qUPw;o
z4rQdyx|^KNYkAMk@an|0I)N=YQ%7j7c1)49Yqj4D2R3bK>O`($q0W;7wV&v5EOpC`
zr9?)A#1q~hdN=%R#5vGL5RpT&Q<7w9tC_QK@qAKhnNUY|nd^KK6HrHR>|R;!Dy#!)
z&%M3Y@P>${a7Y!Y%%TP*ym8#M!O{Y&%+PLXpuJZ}P0(}C^9vb@j#=KZI(27aYd>vF
zHMY-w;+&Y6-`51`L&sngb&&$J0y*@bruJ7p?<8%2`una$Ge#nHa#|q|t=EKJe`q|l
zla50^WmhMXJ-pYyPmq^XrIPV?iKXk^ANcNO>UGtm
z6X3GK@H{#W$eO8LiMk{3z0U}n%KNK^5gH!BRVNbP=U(nwG=JLhh{hUCyRuV^PvxgR
z%BXx>jU)t85@D{7Rw#vCN@lHI_Q@0i%+H1O*}i{
zTnQP=O(#>PhgSA2VljR-h2>Cu>P;WJbqbJGhQZRN9otUbaS$8Z8_s2>U#usAlSxM2
zemWeIX?cf}>CwYGr{%-1u%cok)}D@uY`BydiMrc=A{rIhPa;n}dPqB#c(G7S%9kPW
zY4OXTL1HDV___HvrJk}=2?nzCeD#-PKfwFLc;9jQAknKLbEg?f&SIYIO^M;wgJ&f@
zYx#zRL_W6l8sboYmg=!al06MKZnDTKw?>DZZHi6W(FjeU*OyM!7FzkO%3<11;GfeEi4BXcg)AzxKE=qxhQhbt1QmHo#cFVCbmwgQE6;zM
zuqc%15Dkld*_lWrNMz3U`{}q>iwLsu&>UAb!|{uXY1}XkA4f&xP60o*XWFg3{UP(j
z>7AFaMOP;#TO`^^u7OT|CH%NJQoSzz%WAI67@Phl)ytMR6=u8P^9$isc^p5o({+N^B$x4wVjl}zGX#*_jgN^N
z6FFuAz6}_^Eg5*rlQQ{P-P?9165Y;e4U-U;S#t7a`v*?G`u;-D=H|D|poNx;SHLY)
z?+|G`FC26Vxdxm(GM~Y0A_p}7?nji;6CX)ET+}wO3w_9L;)kodu75@1B2S1KM=0fR
zx3YUUH1-oFAiMI93{jI?8|Tt~a5&McBTpcf|ECEr%NE5?*LnR*@8Za5)r|@5{W1A0)@E7NwPDt_bcpU%bb>v#VIo#Pz7N7QM5
z8W3pcF+YKhxPV%h1NsBGxt7hVom3N9bxA;pHLt7QZ+fQz=p7ejFHcxRM)Ai|A`cd&
z1;k8>3P0`*`=*m^rH)M1!BaIQ9lUV{7Ga9)QjtKGCtL}S%S+&odt~m~4V?k_-up(FmDRBImaVQznj3CgUlSJ>iij27$N-xTktE%$$G$f8
zy!-Jn7?aPeQ^a@wFZ%UWk(bLRHf^zx>{pRzN&c&m)mO(#*{{gkR2j*Z6=B(e6Ry9z
zrCon|uxv`ORQC1@@2#*cU2x<N$=(CUT(t!@|)?0kW4=L>W@JYV69=e~IE`^&|N)!`Wtwh7sERnS5{hn*w$haY&d
z-5;8mN!Qg(F_+|_F-qssW~zdHZ&kT9#eW5&t9tND8*)`yZqjsHDa7E9CwG_7+s9wc
z9EY49Z4p1Nx=h(?SW`h+T4h>ALALCOtU-24)+nn)HWXrg&Spn0GrN)P);2#){KgqY
z?_H7TwdDF6#BswZJ&aTRrG2R+wK4Z5k`}pNuGJnV&4ZFLE
z_^n7-vvd^R0oM(2-or;z5gV0?$c|A7!8TZr43z&+^eKPkNBrg&1bK
z-Lu?-jX#*eo_PeI&eR8`co60TMDEGlC
ztj#|T`>}TCajK-UtKw0PpV9p0O3Q(4VaN_8pDmNU9bj{pQ9W2@Ve@h^m8GQd|FdqF
zZp`%&#saQ!)+rDBkP%ctHvC#VcysAoo%$~ZK5EUPv&gHrkk;;elOAa0rDmGXVjq)g
z7^7pZ7jOj@O&{*pltU;T=_~ijTnL%dTy`;8F|vxtMsc}-6SuOVro>tz
zJrv>wHXMk7!{nf}kZ2$V4g+G~Fdzo{%EMEAff(ou#6Vvl2KoRo(8o01-~+@!pT33h
zplw*I)}7drWQY_Z8{1zYv7K{-k_?*l
zxh;r{cN}*$Q{33rX!5^GiDhgf8FP`5jGl~}jQRgG-oAy)EOi1IHJOlA`34)
zR2<@U6Fa1PTx3ko6cc_DM}B;i@W<(WX%+5u_8v0Vz0UJri7&7ixDiG%eyO)(2y}(D
zGru*&ZI7itu`{964&@|^;Sqk(U*zSihG4ejH-U~UpreBoV#BpQaPWAEidNQDJ&n9G
z7e*KjkAN0u7FY=Ni_w4SCDcd0O2$`vLF3}w;;KB`=l%-K?nPt%O)5_-(x>BMlrkkf(o%N)sK-`(`>px+gJV%Wl#Js
z3SJv>-G2jV_(CN0QO?;uGTTi;@5mK>_HLlV%`+L1t@3-X0OcSWH_@|8dw4nXH=S3!;pJ*N?hWSz
zcX=TuXsRzesamVN;UUSCcY%gSFel2CywLRup_Iub(vvmh$;)`6c;Aaqetd{hOHnaWecuM=&kFv-kHscG@
zYRLTDJ>oxLr;)Yc^VoUrS>M7g*7T`^d3wmaot$<}7v+sQN&RbJyNIk7lN6s24aoj;
z9JK-{eHg>fK~&6_gs;diaT{BJImEi$knJCMA4g?>Np9N6d-8n!x9;y4Sc2A0TtZ~<
z7%n0k_s_3(f9!rU9C=C71zPDr@Th*1(tqvlW4>gJyrudTmCs!IuSKg(1
zN0w}oSK}m>I2|W|dRq4rS>>6CY_4-lh^y|kOf=MIoiBk&z*u1Mb?SybZ4i@M{#72$
zf7iOu;RO!K{6l8>%N^x4cxE9hLXH_TJCT1A?b>e!tKEegB{LJi1wHuf6u#Yv1pCzC>An4K?KOH9DUl
zO8T^YXV0DeC*I=QG;(d!lsug4*BmvN^oy`$Ev%;>$(Q=g_VrPv
z2VXeV#<&JGczALI*A2Z1bW2@$H57f;*HX9n@XPzEl+Qw|nlClYVK2|0il=*#Ui0tT
zuF4wzGv3ZwefdqEj`J_SgEx@EgxdrATO%cg|AhU^)zoi&J^XNr8k5+UEl>JJ7*I|u
z9en#+=IC2a58t+XE>;FV@v9p4+Wg6LsE4B-H1^GJ=k|OfIn6SvJbA@6%=Q-?a3I!$
zT2zNpyA>2YXU9#JF%KFkeRrS_{Svt%QuWlKE!XgiDl*oS4@iB!KGoK^gyOyf?bn52
zq}96lp_Ds=P7QnTpC=G|k}(6Zui5!j`lG|hRr7W8|Gt@eQ_O9CI~5VQ{J=cj5FL6UUGU%E
zq;}39QCknS$F8!x}5=K0b)xG*+
z6<%z|i)fSgomIAfdU%-S;pSa>Jodr@4LzpUqoGEl;kku1*A5T6+O8__)SPBlX5Kk#
zw=X-jc==VF0SG=d|H_}1$D6a~GfveNez@k&C8H2JZb=P6shpb(gm&9Qd1SfP7|%J
z{DxNjR{VxJe)Y8N%g_ex0#ftzEUeLD?D93*z9h_}PIbyydgrC&l{=5`#C+-)`RKD-
z^aS|Drb;29&+ZwotL12EP_ogOUh>w8OSD3i5kFurS~UHJ51Q(GLoY@!-2v(Y{P%@o
zr@V9X9s1{*f23b}CW=wNJU9LM&EL*VenrT8I7Z0(@Smcu3Po@B)E=RQdH3k;lv=^d
zdpt(%K4#XJjTy%tKC=7R-ec%bKk-8hzN7Z_9cc5=Ff;Gizhzk!T1jKuq@8Zu~Yx1!`Jlrp>r1_i%te(vBU{JO|L5yE31^uPKV%EOO^U;OZj
zw=|wT+V&3I;`V*Xux&T3=#vYiA4Wg1=pw>-u~y34DCJ#{afN-vJ6<=0bdKu{x|*NC
zr_{P+Uyn79qj@qNUpyUMCE9=mG0(n1HD1_W=moAnzQylLE&RvTI|twwj1GRQ2b0nf2Lw%yv5FII=6C+)E~y>nzoyy@5?y~o@OM>^k>%hC_0
z92u}{!2bSw>DL&~VlNeE$nG-YCV4V?a9^KQd-!}@zU+W8Wd=r<85l8QXB(r-41|?A
zvoea|RM6%QUl)IRHT!e^k~`ghTG98?&ROeyhtf&XRqw9M>3EQC?9&`>Dc0%sV-KaZ_wFD$+2t9yRu;>RBUDJ(Oz@L?V<`Peb*bG(4*8;Kc-
za!UW&A9N0}q&xWz%M|m=ceVzOedt5}G6(iCuyVj&+)wVb`T$u|wqC``1K#i`+4_9O
z>RPWRFCpe_)9@?MENPlC4Zhx|U(FbHfad4)5~gCU2y8?3#@asr}h2IIF)rW
z*iv)}yIhxpJDdK&jDwBtrKVlRVRLMZZdxAdNH0=bOuw6OI>=x8wDhk@Wh^+yd-^
z;CBNm4)@zG)>GQVqfB;5jix>MwzU!CtMFz`)4tSImiJ!mv8z*+dH31P&-`LeUxVM*
zj!4H0suPuJN;^t1k#>}d;`c@-*3#VG{Adk+bENmXD+hOdH}q0BHmgej>-qt`e$uxY
zt9)p%ZgA)w&1#3CFR%po>-WvEl-;U3HU}$ABis?Qx;@HjR?+F`xGJ1O?^1)+5d2ao
z{1X4EcK%mpZSY}+4XNx|pBdZfRfDtV>JD4l8Y8JLP)HQwh<}D&YQwDG&5D}M{E{ft
zrFZ;PhaM9l;})~tKQQ!?FUF(3?Fz8IyQ%|hnLR(idv>}&>{w!Ew7f0DtL>j()Wrq8
zn)KSLrJuJ=nz&*Z-mv_Ey*ao49F+4U%Ph<$DSX!J>6&@aQVGnQh;{mfABt77OIwjk
zew0gbRhx8M9^R1LIdYlKuNE&A>GsWw*me8-iF5Ez+)fYC3o6p~DLHpSmTf0Jhf=BJxv;tJ$w?p0LQPc5
z=8Vzj`MTUJsR2n471&T#QFD2{^3>3
z-^*6%_RSr})Aq%k5vk!x^b5knRz&OyuRUKUbRD?3-(})2erMmj+vh+3&b^%b;C9N1
zd*{aaPDwtoB79dw?KiJd{tlm6Gw)P;&kBP}z*0-S*(phkN_1-mx0DoQ}VL
zF{>c^NOt;NuibUa-Tt(C_xLxsEoIqjG{xYqz=;c%WTWZjjKpF*S)LR(^)kCWWx%Sc
z!q9$gS?Hs_m3(LaT>Fa@a>ozb;KlY(-){4c9#_krU#;I>Dsh$;{y3$Wp}UwxC9*+?
zcOuu&a_a^^{sBVq5i(DlBbmC}NB>TBrF-4^C;4u_Z#-{#s_^S};d{sLox7Fv(%t_2
z_F1h?Q+s^w-tTqakk7%}sjQN(Hdy)F@$lfScTHOJN%U-r-@3#54$V38^6WlyE&Gjn
zis!wjEg43=Ipdwe*Rn1zoI2&r6}M#5i9P!LDa`$nR@WM>^nwFMo|RTgC4@llxscwg
zK6ot)+`i0bb*<^H<=MJ4;*d1>^wMT^d#~rJcWK=duLNS%i%#$Mn0@wK`>*jHWt2bq
z6{8>BIBQ`%b@T7IGfq7n^>Z^ue~GsAmVI=a@oENg=j>Lzul8Qg=-I8_4e;r|%r7aV
zR@`neB4olo&xqJ@ICaKovQtQCN6&5hqVo%Dqk25t_I-1D&BIGg2us{?eCo4nCEI6=
zp0Pa{Z}-rB3?9ZeTTP^I^z6s?(48i_O&s)YRl3FSna|ZR7QfH*(N*MMze4CKZgBD(
zIM``Ur_`5|X!nt*_H)|~QcOsvC8@?VijnBUbsQ)9jM3%WuVz^Ou@!G*zt=Na-ja@<
zT{GKwFchnsJyt{vn*T1so%fj!beQ#-Pp7KRiZ7d4FLWVQgg~)Ad+ve#BF?RLTo>c5
zf;))o;Gae*a1V@l!APXS3iMpF)~?-YIlbP5yXHN6%$~m|w2ep$Bc+9&r-kol`2D8F
zQexY-hAGj0yGRL?r!Kwfxss;8^L#d33e82h9H7jCF;dR<2
zdg;?!@P=Pc)9%H4yrqwqRLI!2m6uZNGigidKOo_AP00~ymj5Dd!J7;`%^Kw3e4c}|
z|5^@Gc^a^}sXVkc$U}0o-{qFhQ;YrzkhxTm1yC=VysJ=CP7w_!3g&!sU!+=)8zkti;;hkR)kx8L^bj_7DV&T-uGg_Zt
z(7E+#7M|ofBtpgcRg5}m#C-OJoBt7>6oxy}q{G$LA+@Rwr&?T+JTGn<@zK@n~s{tk`3sKw|p`?c9(wB2pq;`e9Lt93!YGjD65OCN$-gfp>ie#Z+7
zK4|USeixD=YU!3QwH~S*^K6l`yA}&+84tJkFnZ1!gh{(|kQ%I&`tqD1Ooww9TyiT&
z##?9Ov=9d~m7n$$>vFuzawGSt3kp!S&h+AOTg&nlzn{S!r*dClKKl1k3kl>GN9=0CRW%R_zI%d$~1!#vp
z_)HJCZECqN;Dw79Zu#tY?*E~*kG4{Lj2Yyk_txZ$&$lvme9YCn?_o|p
zbu~}PGq9$<7G|xB&0nXn1_N&%+D^Hpr@7z2O2+yvFt9z7e2AmdB7equXBt>aJ0I3<
za$X0rZ>-U?(W5D>%C=-bouFqCd-Sj;wIX|`PI}G*d)Nc8w_B@Y9fR~N>~AjxlY7=<
zSMyroqW~BS<6p~`5({n7g0YtLh0wG9|udxh07H=D;QfbV77V0W{bz-|8b
z<1X|n|7yfc$MnpASI$*f1*|g+#o2(rzN`ZbRgoe&R2I9zhrc%j`>%vNSe3~iP#7x0#FYxKLI}7)XSs*KM8z>
zX`m?v_!;02n1-8@fd2vfK~s(?3%JkKD|t_trkW<0+OiPfPnuTY{l~T}0{Cjv8zwjK
zNZ{|A_L^!wfIs8=wC|h1D}g`dyV~~^;Ew=*()S791-^l7
z8SweO^L#6TuLi!w_hsLge08iE_-5Z1eQSJ;>=ob}e5-xeg1!s*LEi(udm-mamM&7%
zjU=91*^geyBLfSo!$*+5?D<#n-iGP2K)4C&|F`~9`J=CS+=mc|0KwLHIb;0ePA%k$Is47_V;r)6CRA0D`ryMHtAncWqK{GWJt;ENRtZhmjl
z{((M!u2{8d)#uQFB^h4-dZ6jh!9hP=9Wp?K^9RxKo!h>;oIP^e>AnxZG9jbYrGcqm
z-SbDY7qSOjn|Z61?3|4y4LUn4?e@qA_6@Xt@&3}==X^L&mwfYv39gR@4!vdJh|!}z
z9ay)~{>5u0Uko(F(RWJv^GkyNlm2^t8FqTL_8PEF$X{{WUBCXZvqS0g
zJedX|-u-OVfw|+AZHLxwa~Ah47;yf+!|x@(^VWc<6J1}NIHtwGrSEKOZQD^WZ~%|@
zdor9q9+dI8CgnXO^j<{6VtgmJGggai{wn$L-tJ|91ABk-B3|7-IZ)USN;z5mL|Hid
zAQF$hwyno}_w`ujLbqU^~=^4rxtFx@wUfN$le9h73
zJ{0ei@?u-QlA7zXaxzP|<|(o9iaEv{C*87(OQc(DZ2!2}{xN;YpEl@!7blGhY`JAc
zN-?D%bX2KZvML3+#gzWzhL5^O8Rg1#x{6B+dHifhy&Q+rZc$vh
zW%or#NApPX9LOOz*1!)*_HvdK6gF_rbLH8r8V<%_C*>OO4Iib9vJ_eK%WYPt2sKu5
zS<76Eb&WAsC`gz5a@W-UUCX+5g+{TlxfP15g6n3n=acfTsSc}>GHB3sv>~ZkoM~Gt-7-r{5YAolst;WDM5QVx#-0w0M;-F50ZpN-Sj}VWF3+LdlyV
zZLzVXs#-)ZvFBU0d>(Ib)2hw$2x%vDpORBXIReqFz-gV7Q&Kc7v1>kaOmXJq=amr3
zz*|ptajB!+g+dB$dqF{&)s>SuO$`{e!-7&bG;IPfH5K
z0|iSbm0K;8k6f9u@-m0D6cvh>Sssq7h%02jj~Eb7)eVtSq+70ySf(n{cSjK~4KL{{
zc}wjswaibox`#_*N1g)eT<-QQYsq`a7L_Rr9n@-CmEm^~6Q>n9>Sefe
z5^lB|xD8Dnq))1Uw;q8Y-upw2x=XVC|V%$Y3veA$$t-Q#_DKh8(Je%CU^
zMLoP^;1TLCA|%sA+9W8%3iOdQ
zvMRCW7w5_j8Z>0bb-c(rE{Dbiyi5a9c^KKi_efVMI<11-a+_!~M8C!uK{I+J5wU{u
zGAl0$Xo9`{9(87F&D8Ma=elxv8;t=VDxXztB=W4X0gpkeJp_GejAARk&&rE34=5z??gGFc>aIEzbiom06-@>eST+43D0B9@issA>?dszP{ym2)swWX;L9h@lAK
zHdjFojlZ}|*b9rjR<2tv>VCNlhr)#2>h#!^GMAhjc&d0oxsArBYH^x^VZN1$MZHqU
z8o0|&8F8j^H%09Q6tplXC{*qm(s*Bk?&e?q7czMj7F~-XHRNGw=~`921Mutp3qGl`
z+Eg`^-GJVt>_+*d?35vC*G0U3jCnoN#=#S}hRvZ?0dH&I^)LHfrC#I^ceS}yQ%$u~
z^DA;kjPv{RO5MmG$Pi<9s+qhT@X96XY$6lkx$KJ7Tc6e1+`#QG)#1bn&8Ml$CCY8o
zYYb3sF?=OpbJLm#RXG?0z^mOUn#XtQ3M_-+a+paV!8(fa3Sz4
zpuIpT#{?-#iS1?X6|ZQSXs>77`kjRmX|bMHUx$Hcd7o#9c`5AM6yXRYBtRjA=Bjz
zD-ZM00!xm?URqFGsE!PzPq@(#!BtUKESnK^Ei2yANW+KeYlqXi{k_!rECdb9S3pagAT-+c|kBeIZw>7}u1w5Ma
z;r?G!3JQFYUX@8&KUzG`Ki|K=zsP^0zsnGAD3
zOeIVe%%d<1VV1$Hf_WO|IhbmgS70(3W82)!jcjE{-ePVPc@9SdraaBuKN)rJ$DSgU3MoQC8_j$d#ROs25%4eRc9JeN`))eMx$e;s}1W97EF;`PRuVf
z6OkT@ixvW{rRdzyWS3%Mm}7V56xeN;exaR-;xb(h3-De||0g!~)WcoN`YSYw!jOiq
ztEe!R5NdGcct*$s`)#+OxmRvc
z9?-CenSbB(^z`oCmBd5^EpdGrt_qCYO0eDq-{$y6ywgemKGnN6e0Y;nXKOwdsURV?
zPa_gyVz>-dLjCZm!4`g-&>dknrMvUr)x9LYB&Q^IBJxd6uW0&P5ZPV1RWWy0dML3m
zz&KNJ>Ge!VzF}i?hNce98Iwjuy$BW-z5uz=BJl^K%>FhyE^m8980A
ze??w-K_hZp_31$YBJULi!`s4K3`8w1r!A*w3Q4qy3_}{;zzr>RuFd0%hp6$_w42SY
z@g!pG@rO*Q=cv^MaaL8N1gx)T0k&&$CR^+|)br$6rqqiFFALJW7>U-Dds%)7(g8^z
zK2PA>zoiJBeSXfA;)3Gq-Se=dVJ~-DWFc(e|AwU)j+%0xHZ1iX_`abJo^d17bFygv
z5^xla!vKfScm;4IjiUgwRcIbLnA6P|7=k{O#zP|q#Ck!)fS8v}_GNaxBP#
zmX%B#qleuwZ1|m$CP?sANow%#P|KyfojBC;ISwmlmvV^On5?{bB`*>t9wrGU6DC`l
z@qi~^xRUoh%sH4pU>InAFd;DEFnnE#hDDxnlC{F+%*8HVY5%UBZ50?L$?;QhLjpCg
z#DYa{Y7}VoR+N3pONY&dikFjLJULEDlqJ7DJ-!Kg?j!A9k#{
zX*VppHR&&|QMWRyjYpLJc(wF~Dc$>!yEbHvPHGMGgd7c>hYZISnB_hzW`5X15UmH+
z2ud8-YRGk3io^gG14ma8Hq)rt;zQX)wViR4vniPD*xo|ZExd*qOugzhSX
z$6XR2nXsrbmsKEWQ*%nJxurQ+VwY`+hlGxuGkXceSZ(B78VzZOxMRnTw1ide#O?}o
z$KVvj#1nQs-THZSE1txq^MIqAJaU}Sh;E#dN?ucbJSqwXUPznZB>=Jci&qv^xWq5g}Vm(yyOwIA|@UXe<
z|4?AAl8PL@RE$b4#yu!Y&_XP(D2{TzqsG-@P7JDSIJZ#1Va?%Q8u|Qkv%}!C2a*A^bEpe)b8k)Hg
zT5KbMBzo(IwsL7J4)}Oo)VeqDsHs>Qf!+#7aT9gy20}blGD;gdEFK3ELuV;agS>5%
zR-)D;F;7*ujxl`4riHDzq*!ej-CYFI(0^3(Ha96XNA;X6nk#vykw`e4+f&iiJYi*JCXYgg+gM=roa%>GWJ^_;xnS+I8}
zhH0fJPrwl2(WTZ3ht=Z3zyV9~A`$QxXW-Q7ZT&&Lnojk3Xw)x9^^&20x`5(R3nm0K
zrzuB;r)>egaaw;GpmCu7v)&YEvomc(&7SFG0JF(azs6N1+8@G4MfI
zrNOk4EmMOyqC6Jiqn;hJW7<21!r5gg0Cp#NP}34Pj>}yib63Zin
zu?#GT)aRh>EKiA~cvaV8#!u|xrMZ)wBX0m#8xL9Q06N5
zj;bq{_Etq#U7SyQ3?!x4fptB^5r?3t$%JqEM$iSX*F2?r7TrTGQE*t~l
ziWS%M-!x~w1#`;DSUSiduQ^y|@aoWr8xO9yk?;_2nm$8kl)eTfrJh@USy@>_20o7A
z8|%f^{3JR{of8w=Gd2M+2?{`~?kwOZpDAKEPF{@Vr{dBAJI+igJqIY03QFT+BJ*s0
zunEGW-V{$s?uHUo1dG+Y()zzn~Z{6VB
z@WuvKlTovv=F^&pjrkilZoIIu-=@kyp<$vi{KeHr4l5KVN;OI&Q{U`*VnH1s~%pxy!y-PE*tLK@bZSs84XIx_e@&d5qmQo7o2*%qcdVpN8AvTGy
zd8a*-B06oX>CtJysf13>h>T9y)9C~`ogk+Zp*V}TwZSP@WIyU9iBcqw}a#I@(wBO)^@-f
z0v)~`x2?nL(?96&=u<~KY^(`rJ9>1hwu~ul5jODNz>|RA4tzB53BV@;F9%);{88YK
z19t?p1Z+g0gnwl<=}Y$JP(6sQLDL+_=UA-(IO1(PFSZ-
zox-4N7%o_az5UkT!ctRH!#>5U)RrhPgJ34Ytbo}ILlu1>Ocl&0Fi~iD7Q)oQz{<332gy*|
zhNj$zzoA=*^w(Hh<&bXFCN=c8S-LgWRxN^?+IGNeeLW#a)w`igH4gu&o{hz!@&Q@>|Pi=U4Q!wtBT$oEb;k+)xdMtLR%kAYjV1qds
z&hlbTor9T{l_1VC7V;yybcR-*ndN6|)$_FcoUPq~`7#P9cuFv=dnh6e%Q3y>y|oAc!+2Na|G+DMy~ybn<(fx#c(=D^9$SR|lGfYu<3Nmct^LSIq
zA{xoH6csyA>k8;BATM#n4nFC@A6yDV8NmEhJIkbLNgfUmV*6fQCIZgy>Btke+9e3i
zr&%;2yWmyNoTFTOS1h0dUxV<9_VDwmO+98+6O?sKz%^dDy)k9vOkT^{6t73PJXLcQ;WR2Ij(aZK82%|lZ}JmBZo
zpm@6iL6~D>jY-CWx3ZikzZ_9@mRQjO(|sbWVUmTHG;zh!QSNlu%dE^QIG@2}sMd>2q
z+XNqX6nrAS-nQN4iM7RUEuitC;1lt!$0uXWlSnd)3@+e(n8@D(3sqn0^QD{2_X3qH
z=&p*%)OT|~{6-`600n1cRd=31_1s00F`R16;j+me^c6gGFh|rnzM4ewQ2EdRa2~8c
zX*tNf+<_|+)*LQL;C#KN9-n%`45w>x#0O(&0t$9(MYD;Dg7bHvgO9fG#bE@LmgH2N
zW*dZCUb$uHkUj3y4iSyJXYn<24+|?pXNDGC-tm}%n}7(dglZtUpqvVK1e8zBGQ(kf
zC+-G=O2raKzY4ILPmVbAPwwceT@_{sQ4Y8C^2P
zC(1G(vDD*lNLTr3x2L~CBhnbO5@e%IC7h82CAJ<#lyEJNsD~ORsE}WP2Mh8GV{)*d
zEF~4jYAt5fBJ_1w`YU(<0J~8YSgwqsl}$9NlLQm#p^B30*Up0eN}(mkm4_pQq^Q6>
zXbGh7jlugnQHFNv-_=$=gF-^96Rn;Q&r!GE;h@shlTfs1O8jUYqHXqZUCsITL`Ku*
zSR&A<=v;~MMZHLz;K{X(!S+;RCw+0|S##(aRhJ9Hil}E_4P}6qXd^X8&AD9Jaq|T7
zj3?wp)B5#Fq4Q|d`C+u_{1_VjrBh~r9ME~R>FL8q4ob@zo}Lbgq8>VBdqZ`EMDU=P
zdZ_Js9`3@K)WdGq^Kci=!w%&9KE5Z_e
z7WFX-5@9-y08Jk`2q{FaATSVcjs$C|IQ)mYt!a;NnahGvT?MVh%X%`=9|wr
z)XP&$(nOC@pMsO#g>?A$daA7d@aw56;Po(SiCO_3y0|z8xw7n_FTi90+f$fT=fvYK
zKIJ8(6BP%L8=(r4Ryf5B8|6;CNTCYO%cJrLfgU~&#lxdHy~{&&lv|wCCezI|ei#5{
z9v9|l9D~6FULHZ?rMd_@B_~ozOXp)KRNizbxL5R+VC!$~UvzuvnyYjW!qX
zUJ^ELK|<1yO{-y};XtPL9tH+HG5J`x!Gr=gqhjbjMx$3b=r%}SO}~b*Of<$gIlOh1
zo6JO0$3AG#-eK@sXC5#zxVk3}Vj<-6)!)+Lh56ut|J~1|O=yGYN-(jLk5%
zqG>|ceDtwmA5PGyDTg#E8?{-TvX+;uK9
znI^?zHH{#~d{ouS@QM_}=6X4uPZCe1U^mt!4p-3|N^sA0*$X1Omhq#@#9Ky-2Dtgh
z^AC3p=o&9tSCOF<4%L5Nl>zCjtEkMJ1&ttT_9QPqU#p?zH&N=aU_%W#?EFFoJ?dnR
zk1;EJOiYhF(AjF$iHC!+GA$VM@gn?@Ql7OQk5F~-2jv#aKv>93j8){WGhY-+92e6I
z_sH+zQ4;?7YA5E1e1BZ59C_t>p24AY98@Ir@S~U|%BVEv#2I)bD2-?i2iO=R&6U*y
zV45{3Z;U*vJ8E5|=|keU*au?caTA0OJ3TCkF=ClZOhkEPDXOv(lSeTI^?0ClUo4Bs
ziK|-KMeMW-S$v^NRTJ`ZG;3fQRkc)2pbfOua5bSY(n>^3!wQNhayL1nqC`W_Cwng;2V=Rv#E0=6y25-B
z)(zwlAC32J6t2@^&aqB*#oHYi13)QfaXH>IBcYhnaDtc|qAM4xojEZHoKBHeM~&)O
z4sV80n%EpPz*P5dcqveys-!YeO#6~*IY!qBH(Hr2&KJG2C={44SJ>|p(|4eFhET;3
z2+;f}90tJvhohY^YZ6F)q3Y(qO(;qv*rQ_$qB@bC5<|6@+KVxC#;spFO}g`GNkHgC
z`%R*5m6jD1%j-m?xh`?70P`=A-=2{N&MD9xVj7?El{0y^4BLTt^`&Qg!UMOOB6pO=Fkr>PU5{c56NCX8l&D}^Vp3dGdU{~LC
z)y_5e&>s_wrY^eUsR7SLciQ)pTg;l4MT~d7F7zDLxY+6D>2cFB0>G3vkse1>3W{xX
zbt{%eP&9yw?XA!oS#aY!C1T%Qj7TUP`94-7;ixV=oR|mtiZJ41`t|vD!;p{HG!lmD
z@}GyH@CUla#Y~SCgE_fps=lk$NSK;ew-gy}Z0x@uIZeO{Kd69V)^udYJ!Hdi0K?d^54N#Wc@;vP;_slTd*0W%
z50!5h5A7-VQ%4Cx)^I_{8ZPar(w-_kP{n132A#^ki0MdzMI
zz|c9U{P%J9cply-2h0L=0A>Ta0LKGX0*(cI1keV!2+#qz8gMpXHQ*zFuK+FstOZ;N
zxF2vH;3t5K0FMK{4tN^yZNM{twSd0??gG35xEIg|`tAn|0Xzg40r&}EJm68lRKVka
zV*yVBIsi`t{?&LirGG9?SnI|-)3XVQ?UX{i3yRs6*BzItnsgU)
zP`tq@`8{^@rqs?0JK-d+;rQ7bnsBc-h}JktznYnc*OA=n&!?_)Q)ePx2d_R2=cL#1
zc;>Pg0n$v*lR#32IuF-6kWQLTQtKqr0mtI`Ngs_1`BBdn5H82#oL{q#s+kISJ&W*Y
zZMW&X6gzT_=OxqW4U|VFA3gIm8g$RC+pzJ)mtWob=G%B@>e=VkJ@@>&>WweFw53^a
zKy&{fzd+*sE8m%2I=A1q%>7q*wLJR0I`{v?Xl309Zz_z2ej4)e7Xxvbt4xW+sDW08
z#1l~%XNrYG3^{O~-NzonVjye6UBF={eB5~8XJa^St`f%wIqyQ&HZnzrgXooPCHQnP
zyNUzae^MOKZQ0a-R;#B5uu5G*M?V%4&J+fo1Va)Fya~7wa{C*7!f+PVhx3?NNJo_?
zfdzJvJUz8MJ}jh%$`i!`drF?pS{^+MiBowL7T8DfM0j~3|Hhb~k?9k3j3wcR7l5-E
zox)O+p$p;oxuwKZiQ`b|fDDPpc5dI{cHn1~pvWQcSNFHJw&1WZpM|@2m1L!c_|=(p
z3AhlDOm0XEN;e(eAoC%7br|c^p5yw2Sm;;)eyEm|gP&W&cKLA}t{tljV?ma^C1L2B
zC_NM4kMaO~kgH<@FzEO5RiL+yCE9?W1s>A2Z3mor@;l4)k(em?oeg9P2CqJVm9yC9
zn1@(W{UkJTxUdWS
zAdE-IPZyuaM=6XbrofBO*#*9t3sc=C3qeCUnXokV%}LAI=1HqkLqxeTu+}lY%}kN6amZqzL-HHowKszd#yX;jAiQ!1bl#O3;()R3f!_9D
zga^I%kvrkg+k-=I!p}A{NA8E*vn0#FIvy0VPJWhpZ0a${`!Y4ebrSLbD*zp*C_M};
zMvq@U?v9^z<2b_j0saJC=cOY&FP(M&mUu*2G6VW7lx67*;kxA&pe3KjvvuI}>zo#{
z2*2J%KLb}w_(hblE2$yN7V1#`B3Y-)GCZVn_uwp_Wm0bUVCZK=dDH21iAL0AssrFD
zHKtKMM$HWXjpPKSh3sxII(%2K9*5*1AI2xRQa_gRu$7KgwgaEE2XlLxBJ<3U7*6qK
zA(5S>eA4@7(2UHGU@#aG74pkM5{OPbq#Nmci%c(%&PYcpCs9NX1+HV}UL61BZt~kl
z$EL@Tf5``$PjHK9;d?(@!dv#S|SXTm4T`(nJxLqB9>!;q
z-j({u+W{Bqg}VOZn{a)V6LDVu1aLZ`7(r-h+WsLrhWc&Q6`70L(D{`>tm
z1^!=60mFR1+Q?EI{_W1#_eXsa!#?*(oB&e;a~dWd=Jn&k+@`^a7S+JsMcN}Y^i<&6
zV0Qfmqa7fqWV|Ao8OZ~tRHi4!HiLnBkAX?X+T
zegV7*8u=CQPdrC7v>4#0k#84Z81UvWl>P%?GGRu-jE5pwzTB$h1aG@(I#@<(>Qubg%m`
zJAY=|g@YPI#KxHT*@z;Xq!!0gaX-X^lLUVL*yBb!O@dFjK_0d|qzWEscms{z<@W|l
z`%E4gUR=u0x5xHIIQ*V6K}!YWcZ2E5Foh5I1Z*o(!~`xJfXBu0d&Pnti&r3>@Zhw>
znaQ6w9x)m`R)d@A{I%38MuW#{aI;4D7!4k)!OeJ^$B|Rwh>LNm)Pr=w$HZ${v1
zDr3KsPyR$)NN0MFm-3A|Y=W^8(m8`dhgS}5JAow9D8HDmy?X9agD%o2Z>j^oy+M5C
zWqD?jnc2RsZsN^#bv*#vYfQWb*V0vd0Nig!xjX~259T<`X=%R*s7LvvG8+Qp14Cu^
zmc+WcJ}~oO?uN0!Ooy2R({g~BTNq9epCSwOc`sg|h
zj`s7FYW^?@CV-d=_NUj;Y2t@>$8YEk|2RX;S?K*9{GbO;9rI26dSWOXm5)1@DP`i3
zae4z8Pr#EdcRJ}uk#O}Y59g6_&VbGvkOS%X7sF8bnhb;9SpO@sG<-LbrG|IIxKkR+
zFq@QxJkuEhQO@mHzW1m&nW}}PsUif8-|L}-LFP#wugW0MTkz@|^pNRQ0dCwcQKVlg
zFODms+)U!oWOM@3hr@hWDWh9i{E8iW;t!pBAIzVZbZ!%1JHP^%A1~_MXJE)r9evL*
zr2|>$o8ZI#@J-UEU@YfLQlGbUaH^aE7wdf@o5Pms57M{qDRDs3DAk5yqxf{fpxjv8;KLo$KW9C-y3P0w!6h*Yzk)oZz8{X_{9@Ylf=D@3Y}HLn?<+gH$ig0ALaPRqsu
zngEvp(g3H6-_<-!+1Tk;SZ{BAHIEh(>9=Jh+ny3h`z6!~@eJ_pT|;^{K1-mE>#gkN&&qY1aK
zCfo##%zhI81b+I5TxGMRoPi+$EK15r(eMw_=#Z+Rr)lWv8hVC?PL+Vl3FYr#js7Df
z|2%{}GUPm)EyEop^@le$S|f9eM&_N8z6^fHYIyF_@Z7DTkJHd|!bCcg{0aD(bSj5r
zESj=iBzdYqw@EpauO%o~6c0-0sT%pyH1hAq`Z_QF;G6E_&G#9Se+c9}AaN=W4{FM4
zrH1~HhCUNZek7B^oyF={He?WvwLYGRdN$U=?fektzF
zB%R_IsKJ9I57C>Wyb&*j9Sj}D1Cm|m=WP@8enKXdVS~g;2cw^f?I&HJvk9wJo8gae
zU&%vh>gT7hwZKR$jK@XSmDZXt3BiLyvr(Ix6b_O`*
z^-a<*;Sn1Cn>BH4?`L3{2$RC?AbE&ik-8DyF;J9Y!aD_;m|M#4tn$O&#n0QOb@S`S
zeglnUMrz{QUGfvXhr}r_Zk0TgMo}8Pr$*0cq`z7wdr7~4fImjY@e1%*#D&TZ$u|f3
zGC$yyZgCoVJoKctlX!Y-bh|^<4St45ocfEQns^Pb78^sJ5#*v=75K%TLE_$`TfNnrPSS@w%(a?<{
zL2NVV#BY-AJmG#JqFzus`^&b7=m8qMS$J#qI{Xq(V7Qk*D7+0D3mVazYv{qU%_li6
zG;L|9rrm3$p|_EJ5b?J~`~SAovz73p8aX%1wvPOE(C{b{uZ65z!~Gf630{^o
zdiK=d(cuAXo{UQ`4Lv6O7PeQ$Jx)W9*R8BsgGzQVYsBX10?@90a99G_{1n5ZD`>HIbzrSo1uO6Nm>l+Jp{Z4P)8cI?-%lYo@&6i-TbO23wX-@{JnPw}Pnr+lMy
z{|$CZcOU3W>Fx(ebJZ|FIyc~BH2KCD_3jWKy}OTI?+(=I-TVKEHPS0SiK}5gfmsAQ
znIafw@Zp=327@oQs|
zFW%}@74h>AxTRTOQ1jrB7A-@=TD5Ky-nQLM5jVH*pmglixl6awyc`GaX45qU^$A4g
zr8zw`xm3W{c^p<8GR2aMPjl}&(7756a)L)Qbj4k<)4L6TMS!&V
zrvMrOcY@C!(3}7}WT(S!0(8KBpUstr;5{GqAvwOyZcKEScui#kyVgyM*OnR++rbcR
zrNfx`ij=Vp@V4p3#49ia$3I@*Y+G(jB;y4A&t<}Nf&CEdJKe^_+Go7xw8s7ba5AcU
zV|J|@;ly(6;lJ%SCa(KXnDz&~c+3HTUyyDp&oJ1vMx`_O&69pMf#(A7KVV2c!6>+s
zNzjBb0eoas83a}PxA3zFW*H3OWZr}!p6LzzX#K1Bw~{9YP^)iKxb0u?CEdW?r-2*k
za2oNh095tSLee2slMbpI#l7e&V`3+mnI{n6FTn?V|IvTX^nt$zJ~t-LhQFqa0v^>Z
z6L`&Wln@T~ptk`1%t5_76fg_04|R;->kGK#2>LAW1ss5X*uxg;-8q04zSXb-
zjRDjHz7Dzpa5em!0QImd@V{@G-W>rL^#Sw&JredJgk$?y?;Zu1by)9i1^3E*kPEo(
zBlIzVf4;AGHv?=97zk*tLHK}IHtOBY0gu%pJs@w+UcI|5?2{3{c7P#}e=FeexApFL
zz(rH_?kK>NS%@Ft(|h#pXuxpr_X6DZjouvtn7v!?jst87_X*Hz<)eCc8tg|;>)rRm
zezZdGo(?!|3G~B&Va)l-eTOZZCZvi|B{%(NFP|hL&=RmJp0hi1}`T`z)4CxCP0vH4Mr(N%k1zdn~
zL;d+~*r`8%dzapg*m}N@*Y)n-u)ewzl=!VkBaGV?15f=~&}RZ)`;y*G>jSfZPe3}*
z*lq{#*QOw^FpeX7#U?NRUX+zC;Q0vjBh_B~beR`_VVxIGS&KM;zY6@0=LDT}xVXlP
zPkYv@=K{AEU;dO=&I7Bxx{X9w3S_wg_vr6Epz!~sV@Mi#Bjkr_(4g$V%r8lfFiKl?Rd4)G^PopfW$>4bn^)ws&lrQTZ_R6e8+*SUQRlvb>
z2s|gs_3lF`&%1!%@}swG976k}mdVYi>nd(?dGV9T3zZJ>wk`z(Z;H2<%DkEBdjclJ%jureRw`L5zN}fdiNjT*#r0E
z+fnC{KL1nQ_D=Ga+uxq?;%~nr(uC^Tx!GR)wu^#?+K>yUy!bi|Zm#f_r30uVYJ3&6
zEovE?Eb9)H!(pd|9I6Xr-V*KA2;jfHfqoZpBz!vBvUy
zNj6H?g7sme1QY*j*F}Di!Xmzu`YGd{v_R)7AKDv1Kr@M9~bqpUidd_dhA8ob%%#yE`j*1E2
z7r%YYp1TScz8O?`W>G3W0$z9pP#t-AEcAeN?;A+L-R>>-&mbb3Qo-0
z)QKDOV!{nWA(}Ge>O@ROwhTWj{tb)D5Zo~WNMY;$|
zLu1vX#0|4%&tLx5{_HC$c06&GYqO_ht0DgX2iAo@|J&Ka_vYOi7I^T;`FmKmV9L7JUi$oW&8Ati()o6ubxj!
zFsw!9)b`I#xm@{QfsY%bs||eIxO<(!P5US-pES5>4<%{2
z!L7r1Zyo3sz&U_)Hp2#J1RMtF4_E~L0KnGZ4+1>5*5Gad7zWr9F#I`#I~4GVH3oMW
zU>0C2zy$bf4S4c#gS!o&AMD|Pufg6H@aPlJ3oz?hgZn1H)v!kZM#KGPzzMLo2i(8R
z;O+nz1G@sa2KLT?3jB2e)B{EX2Ee@+-~zbE0v>T2+;M=L0eb_E1xx@uxys<~2lzB#
zf50g44+IQ>dkSDF=z{?Dpr-;3fISWH=u(3_9k4m<8GtXqo(Z`88H0N;;6A_+fcFB9
z1ndtu8t}wQgL@3%Z1CR+xbta)do18;(C-4w0{w148|>o%Z-Lzg7z29=;2%p2?x}!S
z1b0sZT(sKYowUx3WNJWz$4(R1a!mx5a27Y)0*^n*l9nbKlo`a`r1<{FMw+R
zY45NT+-XnW0Xyv(UZi{m+y_YehED*}Jme_C)u9wmgk2Aq0=oflIl}P)`~~?-=WG5v
zuXEG+8rKD#o7ze9uR8Zk=ra?1vjFG3igF0K?O+cEJhs^2-i{^I{dH&S2G(8aa3T2n
zYXdJWtczeiEca4f-Gd4AYZKnj7Y7$Q?EdiD(GK@NtkxGShx1QoM7Ud^AKgogZ^76mgpZ^9yaKjgX-eF^!j$-ggoJ+!lc2E^?Siy7q?230
zDpTT>CrpX2!&E*gAmMMrwAR>(c0}46(#b7pwJA~8IjwN+Mm3gzI-Opp*JI&TZ_pbI
zJ~u0v?_#a8J>X10Iu~~wkj}-~e$=_?TwLp)bnYy`z%x2Gor??jS?8v6aku=UbL)D3
zy>wezs~0K^53hYa;ov~OLjPqy-BNwuJK^y+y|vwWDXDkn>Jh#EHu_ZUGejxa4Gv%{&E&lo2n@bkw&pID>_E^-bFW>seN2@-VH~Z$WhgMA5m-F0XciuL0*U0e^
z-@AQYsk;4QX!dJg1-4so;$*)o%9CA&ZCLsA#tRb;*?#_-%U1!hjw7->_~zyn9po#!k)ki(Wf#y=fak
zeB7#ET+hnb<62kXwEclkZTU_9^{h-!+bAAaV6;7we{yiiV^40kZC=Q9r!FQ=zH7^a;XB73ymi(|Z7Uyx2;IcjR~4UVlm6hxWfMOq`8tcqy!cqwnbDI*W{@2%?9!1n
zw%Y9US*UIN+j6Py%GXnWb(cvydv@bPh}k*qL!bm&RaB>+Sx6ipQ>kPgQnECGny`GKV2o;>_6e`8&^YGK6ASG&A8!Wk
z8QK1)7xo|N?YH;QSHAvm`{#$U?ix5WFFqjikypnIiN5dY!-=;ULjSp9MEUKDCw1O7
zxkt|BPewO8-Z!?j>$55AzxDlMZLjoSbJGe>1+Mv9L{+%Y&E4G#U%vb3x(9xlKkANW
zpV-lS+TiD-9@@31&#ey*dOYret*GRjKJvhqPyTrCs_9{K4t|sJdQwHt{y*e*Sh8qF
zKl{nKF@DVggY`O-F~Glh5cBmhW>-+L;5Fe0p!h#+5a`M|I<7wcJ(}+vVLEfumjbY;#_F=|tsv
z)A1)==bzlMqxi|wb27G_-Tl;#;Qh}AcCknO(6eT?>-OUtHjh8{$mPi+M+{h5vOBhV
zZ#To{JrCZs{nutEcV{eK|LF+JK2u@$?qO8{Te~H6yeaxhNz~BLpoCG`WdYW=0wzw5
zet+jfRZ-3*&wjss%^d~psvVErvGchRwmogXU-D5G)2bs?y_^5$a8C?ry<=@#KU?4S
zL#AYQd-d(j@mm5T`rTf0blC8HtH=Fnk1qOU=0ca<@_a>D#opO|`aSdhtlPHeCtKFq
zOV3^2cA;X@?!s^VCsw^s_?Gk6(%bs~KK%IyM>ZcZugLi1#?NPUX#3&Gap`m!cGOhd
zA1`5pigKMwDt{D=rO>Zes}`j1=+gU2?Ndsb|0w)sl|OyTF#N;-AW3jdb%>NPIaPy(_RGW;ISx#+DgWkZJ
z5!F{_nabdgH`Yr8m=wFxS@qK=%?)`8w#Z~Nj&Mj1Np+1)@iw!8%c}LJXuWK@rq@d_
z)tK3(noBQAJyg@i3T!1t8k^&`OrXtX9^1Ao33)aGCOp0b`fV()U00{lta
zpux;zVplaZ6Y?s7ph6W8y-M^tLB52EelDvQSY)yxR>SNtol9H`5>#%NkDgGUL!iPZM8R}aK9JCPu_6CmR=>Esh*vP9mTW{r+rF51@BR|RsTL|0oROr*Ox$@8N1MifVHf?kkq{+lcwWoHr<&yMC=`_0p-sg<|+_}M|
zpQW(R$xNwJl;7742p&gAcEj@w_Fb3yy1
zAXjtT{&R~mv|s!&I1O^@A7yr?``I(b(aTQSbL?H32|Q?quuir&#hx6`)ck}N=R;vl
zW1Q%^+`Vp;Xp3e+qxd-ms%o5VyIuX2YH-d!MNKTFlsTAgbaL@oD5q=JBQcn0?TC5B
z!IeMteC%DxhdW=#?wqHSUnU?oh$^QQt5m7@V7|b|%AKlja$1$5-xOUJ3@3}tWV0LN
z*lPKL#GO2`!`$0TC)<%?w{yGNDGQyg$fy_0pO9=GE$gGrHRdVTyQIz9ogr<`B<<=$
zT;^`0x?;NOW}$hqmFBKTvemsM4Xt)(upM((xd@I96L4>JG&dY8YrN|xCTD)OnB
zCn^atDP9wo-5D8m?qQVo#t2_)mC5`zsct_qmC3y?&&OQi3v_|?7P{e`U^jRMJYn%(
zi=Tpx3a=6WzSlSaHdT6!ibY=I6kH72WM?JyLhW+v*+yHUd}-vol-deoYTtM(T@CL=
zb2~oG&#kmS+``u(O*_1Va+i9ItKt3dK`?lO*PtlpzOwKl6W%Cz8Bna_V6Zkk@PJ=c_~R<N{?nd{(z{aAwtd{~zQ9;u`)A@Alp*?$IvBq@eE~_^NcW$LkFEPE
zzP2npDJ?C!VwZnQ2D|v!^^e0|1njzn7n9xv?0Wl=2SFD7F%>Rx^~+?^bEt1UY`4p<
zU-bQ3e1R3fW|2?c;|uh{qd|O!!+|tgh%#3QEd9j0ld`QlmX^oX54iH#x+58MwoUl6
zsQ(}L`U3CJ4x2@u-02H+qaO}$VH1e&a5#W16NdBuB>KKl>Xx!H)h)VDQqOR{QvXDL
zWgwm%|5A_FCh%-V7EeA+)V`oi(k|96Aqe7R-tY3^Q+@rCYnH?2f@?(>1&X~26
z_t0Y_qX?gLjFxAtb}4tPz6W=kzCG})JbVPb;?wtsu_3*@Oz8*y$YM`C>(YEz
zr=`X31DF3J8SHjh!Vgh@N1Bh$c^3n_-Yn#2@Hqn3gEKDwAo6kQd&i}->lc0RAzxq$
zuvz3|pmhZFVH1e&a5(im?aP4S{6C4lYlM33ax&E|I@|tfSn40kbt2rilk`Hze3|C#t>p-5wW*q>k#1_PUix6x5iKdXK>e+U_R=$d-DVljL6JVQ}IKSOYb*%%L^v2
zKd-pGW6peyw(tmEx-wAKM@^IfV
zxNz3Hw@fP2+E0AD?S=VenlW(aO@%FGTL0p8_0RvhObh&M?cnk^%St=b2z$ynfw;SI)MVzqjbkKaI=VSN`;lzqOUMzEwW9>v2DEjLrJK)-ZnGzWqP1
zc=!G9{p+IZi?1uVBLDr$jd!e=_gvz(zh8e@^TB`f88HgZVo%3tdB$p&a>wfX?0-$)
zoiP2)r#TPR0-l87vz%w9fULol2UorVN*%BNqQ@p{XE*Y1Qub6?O
z<4kd>8s2d`E*_$4IPGR<*0nk$hGA#wXh+>9Z5e^lI06
zbWKY28L3REe`#9%RhF*8(wA6eKMm{DzZJG^QhzCaCtP(7TC(VqUtmqi+QG-6%^wa0
zd%M^x;9<=;L+t+ZV9_p*vHX#t;N%zC!=T4wY(UnL^N~;QVE+K*C&;^zCm$IKP6OJb9-|np1m}<=a4R_d
zOWFzV0Y?nVga<&yW0V7HuM7o?c2f>K4UBuzW8}m0z^>ap##%T6?nB=JcY%37ra$5R
z;KVkM@tQE0d56asg0qg|gFF+?2mKFwj4F6J=z4^6hugv0pLh%d?g6tX=P-N}EG6$5
z_&kUsU;1bI5KQ@n$Cw9KfAyh#E`ecJzziW?1TG3C*`~Wp8=EZ^%&k)
z8Ede;lXk*|;1GRM1+N09WQ^braMu=((FN}kJ@S6|AjtX^;{u-sv#BfVFMJMzj{7}E
zjwK)aDgB8opV23~JVvP{&wh|+OD(w<{c=l=qhD*uyO1N6T-m{#x8xPf?ah`vw1@d=
z$?dc`YbW(<9|n)}jA|uvH}d+oJw^z55Aq%8n~?jEbI&qw;Q_D*`5^k!$b0cQm(PA8
zpmL_y=zWuOoy$7B8T@uQ#5f>-G~H|D!1*AATn<-(gO_`a=`y2sq$C?wBAWpsX()7+`GyC{@?HW
zefM*e>FVn0Q>V_Ws!mm%i80PdqzEC#SR>~{DC(8`9{Dz6yGHjA$`Ls8oI(~(+$neJ
z8R|>&8|u33x=fZxC@4r|l#Kcl#Y7UkAy4-7w5*oPbnw?Qn);Oflny7~r}&a*_uYFv
z5n!_nA#xd%g#Yg2n=OQzwuE>?#qddqRFL29$ZPp{`Q$^ty8egIMaoTI{pCvN(04CS
z`-FZu`N;_rlQf8<^HbJTfATBD?MN6EWglMexbAcLTCBcozGu)-lsUrrAYVB=~Uzpz&ix>j{y1{
zg8HTFP?93vtDRSW=?e9V&!JxFI@EbpJFouIb%`&zfbTEyb6%x#FOK&U;k*d-Ap93~
zQavx~qr(z``q6yUCmLk4SD%`HsXi6<+^sgbf<>OYpuQcFP0smXk-mJ|N;f;uq57e%KGfTTZ6G_;s;lzxv@_@iXZSZAIJi
zWDj`&-oE7EyVDDQLhnOA6Lzm{?87@y{+WBB*C5e0e(=uG4gU`8e@zo#a%ax3eSZdQ
z3T!%ko&IMwy$^56rlSn{4q+-D3Hb@^|B2o}V#QDTi=91Xgvj8}yASr`Ze;88MgRR1nr!_aU^{6tke6k0q5ztZ
zKG+OtGXAix=i%oe1s+o1Aq5^%;2{MbQs5y4{(quCZfaMBHI;f-y@U`IBRrv65=q|h
zo;_9#^C!3;{D$|cvFh#J6)LLy>o>fq@lgy3R58^H4;nnm)xlWC(3Q&o459k2+Spa0
zQoMhUzf(<2K@8Cr&L%$0W~SkX>U-)X43_<)RiKWj=KwrKn(Be&X2Uav8IqgR4KSHm
z{9F5F+CT>2G`zO|o|>U5RZMVuE?lj`&NhDae$w}}d12t7=1tyDP=zpn`neyT6q1L3
z|2_?VE}b8i`+t%GG1F!m6QgHF|38V`L!=&3;2{MbQs5y49#Y^T1s+o1Aq5^%;2{Mb
zQs5y49#Y^T1s+o1Aq5^%;2{MbQs5y49#Y^T1s+o1Aq5^%;2{Nm5d~~42{aY6&oOm;
z8Y8ndv13&o9rl0a0}SqFoUPI0
zoyibPR2@yX`7DNFIDShb-MIzuq)moMvgaC<>;_yZ6K5dSoKRw2t?rR?vq@c+f<2$L
z2C?%>&N6X+qzLW-b6v8!GfU1bA(Y_{kb|{|ZNF=6Qj=9SCQjAS(bbU8+&#Dj;L4Uj
zyKJGMBLm89p(93G)8{UZQj@^RHOojUr((Gcn+@(Y#VG=tVRY!NSBH{}ISze8uI-*g
zQ`;>PSnxd5+KROL4WAY}ytf+}
z&iw$V;fJ0f2Q##!olxA1^(uWZqgxHM@bcsMS38KBrHG1MnwP9x913uY(&5rLe
zfYtrt2a;1EtFjrrh^)q%c1z25?xHWhVog)L8ZrB{Y!nw(Rm7F1+hmh#O1RRqP2zP(
zZ%U{vF-}NN<>1%|{8IsFKCOue>3br6zoAsxv66o
zrP>y3w5}dXJdM|S78%dmfy0gwB&aH+LQ!LTlR;^1iK+@F+QPOJD{F4StBN+a`WRM5
zX$#FMCAuK}dwRsvwwei)?_^WlBZJ-6rbPP$RYkoiBM3)D)82x%3Uzr(uJLF8N{2|g|dEt^!CjFOfW#4gCPEQMOo
zBEXy4F&%F5P}aj_42HLDJ^2;Zr5wCxAj2JfZwUS02<-5f_<~JA7Pf9Voi*`m&_j67
z+LTV>?Jm2*ES+vkUX9wbvN!L9ZCste@l?A4F}9{Vm~*jFOm|PRUj?%~YkF3YLbcj)
z{JE^zS?4PAILvX~=Q+;ZcYn^2H+4;BZKk!o`uK^=x{cXKfTto%R=&z6rPAr?Hf*0M
zl=A>wy-#OpgE~B*+yT^5qX%er3*x6Ox`nw=Qoa*PvSe&>=CDjvq#s$ELiq$84XaTc
zi~0+~(c?RT=K)Te$ATzRDD4q$h+dVp{U86;>6qSvsjxVrK@}Bs;ti{Z$p|~!u0LR5}hcq*pgz_!>>HqPvj!l
zB#9@rSvR(Tac80B%nq6C?Y2EuQvmZ@%a+~a9CqPogb-K(wX9aEAwTGhqmL{>RS0#f@OkOqW=
z@Mqhj*cP#-1$Lge$)Xf8C>f<_>q#D(z_wSVm1NYApB01vd)qc)4$?a4JPExre}h`CrR%AjghwdZqOLqOxb)-CXC;rXnK
zBDBv?QrnQ0uQKy9cYpogFQfuJh)kjfz6p2tBzhn$&0OqJG-n}SyzAV8X~b*YT*e}$
zEVaC!f@q712dz!f?!s^Css%B4&TWAa}^>+3&$OhP?@g88463P@cVHU7UiGsd0if3|U_|An`z#8N?Im@c9
z1!?1b@=@+|Qmc|G0}7LUm*18wo-7`r!qYObl{TMiYg4*?b1wCN8toHOVT1aDs>J%t
zRx_Q*#P6HZ;1LX64Cn^uOA2B~9g!qS&W#|$kNng+$hq<4qb)%1!XeN{%Q-z6guOSs
zuc=ImJ)M)|y*A?O7({2-11gWPF*N{|Dr5>K=-D
z^Dy(4lwTs{%T8zc>aW!#L$0TyHEX?;OP$UF
zodpO8k0!`3`P>o&}08+xxB
z?}piJw|eenD%!IwHp(aDu*mnL35OKN!kl~`QRr^h7{&T9TC6M})Ve{BS8BG}K>jK)WPb(-aYsoTJH$PMJzNf)w3%8?EX|eN4R5
zvZkER%Crkc{*kl9g$Z1}&u0mCi?Lzo*<1Z`ftFA*;J%VTODH$wY+Ju_Kuce#^Q
zklCAeF}24QrM}mVsqK(QMEthf{~1N8r+}i0`zdOuoTu0BZF2LE)Bd^14XFw?UO9gN
zT@B4h*XSk}K9|9M4W#Rue@fQ{52Wk#|ADSBM{pA<+xAn+3J;|0K^sua?`Klh=buqF
zxRzJR}PCuwe3
zanD72%7Ai>HAm5ePWDYWw0y%D3uQ<(D2|03o>5a`iGO;pnKI(MEhikm^DM%r&lkdQyguXeAw
zuXWZ{cOe%jp^zK)k=LS-u1M9z2`3X`riKXb%|hy`6nA>&ynhmCbMRLs26!K!1qmx7
zTWwFR47xDm%*<1BPCj4%;xWZHAzvk&GwEG8e7rt9<3PsK>;EcZ5gBzXZKjCD!F8Px
zezjqiV*{uh_(#OTFY0FE;#ntWmCO%%{=MgAFWj7(AjHfc4tShN+a-LH{(L%RM4Y{S
zN(=x4V1lGXo`-oQ&J%*F_L{fXnj8!nW8PC~azv6$hrHTAOa@<)S#2_m03J49f%jXy
zYPMD(U7?jg(-kc*tz!(=F377#kQ4US3#Mv4Id2Dke|rMHz2IBwACUUk>X5HyocY)s
zW==JfSe6k#qvD%{b2Cp(u!Lj-H8~TfmoFn)1x3DNCm&5XY^66%Zf=>ffk|j?dE!o(
znfEYIw*4e9Ar1ELFPs6b`E(+s9|cykx#g4M)~=h0K?2esW682d<9OcXeCzKJD|CxCq;-)5aOc%XF8Ii^iLJ4
z7@Y#~d}3>3TYo$eOO!}IBT@xwJ0q(C?VbR%p!#Uh+;aS`$=D_{8O*Y=AbYbXnYh0|
z8%h$f4MkkgtYmSFk8&rqS=48vpIip|AY5HDWv^LTE9g;UV&X%Dlj67?dU>ErHqa$V
z2#7juGZ}Iqy?v5NKb{Ha%CDG=RWgAq%{@z?_xlk`Gx2;%h`V5Xouq>GnG`7)Rf-b?
z?SW?`j6oPVmn{o7?*GojRmt3Qn-rz$YcNKhToWXWn-bsJzrOjCU}V!<`{@YiO_>sI
zIP?urr@l1%3hCZp{fjU8+=j5WXOzzEAm~|W*qVDQRUd30%v#wNuhQHmVs&)%v}Q%*
zUWGCKe7og)EWb6Q^!;08cGlB1^KBtD@ivnlV5}=Wl}oH`ZC?2sO2=;^rw>XJnQ%_=
z4QgYUd5mT2q`l@**Cf7!MSB!5CYjt07WjHgAw$Uo=rD)yrM4a`O%IhXW;YvmuqTM@
z*j{$K>3r7Yqsu^3ye?DmLcC`}kPscg%Od5dnUYKb!_{T&U@w!&M`gzl$Kz*QIJQ2;dqq+|#qm3~4zN36m$0+9g2VxK
zANI%YW@xvdKmP#iCf$c!i}FF(jR)+M)Pu2WKI+15($B)~+a}Oyz^>{6*zt=Gc&u58
z7JvBi^5xjyqUC@7(2F&Ts}yJUn#Y*KH&_P^C8|L!UMhE(RRmbwiL5)oH%Bb?Cle4MDhPO9#`4pl~x_ViuKPZ_R
zG!6CA+0NWP4JD
z2$Q3V>}99h(EEi}BIINkSf!86;P*2q&Lq?~lfXB@27yFolVzgS#8G=DSR#sO-GJMN
zaRd*x+s4Gh_fCFLuxLR&jc7qbghjzPvr2Ap;f#3RZ;e7uc0O+6Mu3$=$bEKBg1e$b
z(1W!vl>AG{wzN5ju9@V-Hr_j1iJ`5K0PyMm|DZUBykpTZ?fUh3_|4o2Ds~`L|4~D<9
zKYSCk1N@`1J(Vu{f9&cP&YaMO2+fziy(N^HxDTE5N6G`G3nduRI14m~)b;YP&(c4q
zH5p!p){b=hNNeKW1PJ&xS{u;M0)&8+T(GjJYFEXKZ(w|AF0qIj?>3?4>8iAv!)22#
zsahNzKCwQCD>0t9A~%{Td0aMy^HPw4!Qk0k#mIJewUWh(HRYQ*Oj*yS5%4_brcvRi
zCZB2dMT;mH`0sOMCK$1+ZiN!R@2u@=A~#-F(F%iMTheX|!WaaZKif8a9*4f?&Yf`vZu7|;^@
z&G?4xOV9$h6U6G9PEk`;9xYzBi5`TRZq0CC$iMQ8k}}-Vy`n#(H^v``4@r1GK{55_
z3yYIZCdDi$SrFVuYpx0~16nILlT4c@tWjJ6yKn{afYweO+hcRmnxkdV|H`oJFuM=O
z7#g-+xh>~LKrT?*S$dqk!QZ{jYEzT#w(r=_ZM=C9{d>+jcRi_wp24bK4>Q@x$0E$j
zqxs)#kXhOBq;<8#c2v1)qI76
zH;vNhR*IfTO_|a_O^Jf{ynhXIsFd(Snz_?APCh)In{f1PF8t6WBR{NGVPjf)q7>e6
zhE`E_BP)4mZPp1WGvVlKS#P?Hb(`kq=Jxcl%rKne%@2EnB*MJY2k{!>2jBHUZ!Dz8
z_P3W3{x9!JwMi+uc$i&EeOMgn%+v4ow1G`6n|#=Y9@VTx_EhjR-vSS{yQ4kDeQrDG
zMRor?J>=;zFWRSc>3)JTfS$z6j4*RfQ;Au*c8sNVinXJvhtJO?Fyjz#Wkm85x^tZX
zu?--ewk@A>+UBY$V>Z@uy0;d%hZ@BDYzM4x`RsO&Yfs6jX-^T@2=<(=fjM^%SG`p1
zElDccnrJJ#P{wySh)S`m8@W(lnHP;$@G3=H-%^wOW9MLu>&8n!7G%HgDBm2*zq&b*#EfDZK$593e
zpMm&EGa$7uNI(7Z%u&W7Az*4VXuaBG&^P`4BnR3~p|%T#Wp0xXt5?J5=!uT^n=g5Fo1mu@jFj=91!uS0
z{wu6zL3{J16+ea>mVh@AXOB3Ol2u4;y<`omknk~Y^sFutl%w{VJuknX&g=B
z$bxY}2H*(QtxnEVuYt14QR^gJmaGk{(gyA!pND|IrLl?tlLsqF?x!d%g@5eck0X{T
zJNnmEcUOWGyaxK|3$tx&R?a-CT3;S)3LQk`#Z(CT$0W;Ks;nlHbNLlf%5V$z+WfUB
z`Svha$K?*Eg`^b;5}ciHLf>;OtY%nH_l)wBkN8y2)8oa2YFTts@Bt~C9;E+p4r
zXACPrb`lP$EZ732*n*J5ieo`XOX>ZH{VTa{fO%7{Y)s9{k>N(D0W{5t!}8`!kDUpt
z*$?nt{w)TvUMykVT&YTH>v5HCTnJ;o62$n~L*@3=k@65F*e>AAMpp^uWq@}gtY+NE
zaD$;!#Mf>DZm4S7dqUoS4RBp<&s_?#nI5_{FE&}7S6L97-+)$qZ3^~yYIp|y(-KXr
zz~X8fq#e>qC_Rk1^cmcU
zl#xUWZlrZ@+I)W#3EXTy32!U~3sp;2PA8_iSp9!PazJiv;g%p}{_X
zWzng$GrLZXF*DVvoLY^&XS!*hL8bVVE={w^+z(yV@d3LP6LLK`l|sjC-kl0O@;c@6
zDMI=LM4Bj6Dax2>WH4Z31}If~vyIxH^7f5|pgpb_(sUWPR}&
z_FZA-t=Ft?>dEI-Dg!NZkDTp$Eh<%ST}@M)VU5KK{x;QHz9eJ69}RfbZ#x2TF0J^|
zXE(|!@UZ^f!=Qzip8aCBbNxkvZe49AsSd`lZ_)z0pr3AkO7t_%Ir-wTz3a!AOERqI
zS3zH;V{#b+ZET!9K|r6v^YxQ0if?9~T72}C!>=AXV17CSJWws$EHH-Maz}PJ?fJCd
z!u%AZK4(}t%Fhb00Ftj!@@Yuk#>LZ4PK%k2c9`Fw9BczIjDA&>+1W$sH%}WrE%_0v
zMcKmN-9Yn$%_N!H+~o0=6y3t@!=K9{l$D
zuhGx~Y*llHc)t~PhIABDldBfkWK~55kRyn}2)l}28t0UwVo8o3`K(ut@V#emLtS}y
zNQnWd0y&o++fc-TG^H%a?A{O09_^I5_<7?Qd}D=J-|<3Bf0Bb(z}1A`$Ft#0XRkE5
zYQOy(7+=*zwAw(DHamV&&o&{*uu`gl47Y=B4C-vL!g_MU<@7fG%?;2$>SPGP5aDBM
z&~)BY(TTF^gAIP2_ipUJ@uiimzK7IQv14WYD;)}H#Gt6Lt~P+bcdyyv@JmI?Y@RC(|HeY%o{{+YY^a{o|Vb=CCc!Os_f7@JdZ$aCg?|`S$>O}pvJ4LX<(0u8o
zE&azD=(Vt=eRe}-Xz!so*qIZ~`@v`l?$)McI2uzXWp3wGZ~GA@m6yAb$V_SPPD&cCwZgfV$d5dB5p>
z*Nx!25aX4ms42a1`+8#nJ}LW2d|ENK9vKjy_NOrc17|$`i(&T0>w}Grx=&C56}KEp-Fvw|CjL^2e$pEF)RaTi1h4h`@f9MIuPcA@RZ-*
z_Md_0ziRtW`2I8S{8uoMM-b<^kDk4H^v~ivgFIpESWrPJPU?f&4snV5%lt3KvyVrc
zD4jx*c{#*ghG{l@s-EatjIo*Vb9*GFhl=UIF_`uj({ExL;w{F<-(>OgnLS9p820Af=`9Vj5yWjO{FbLNPr-Op5t|QoRK80|UhTS&+sU&G^|ZrX`qCS}HH5op?&=zA_kp
z89!a{F2-Q)OG{-Ef!7#|89!25f{AI2^^Bhn#k2%x+9=GI;7Dl+j+B<*NNEWUrd>QO
zgmguq1hY*{OE9Ih1QXNE5JMV2qRi+dI>d!Rz7tPL4yE!atB0KBC4NcoN<5Nqz%<6?
z#t)Xk*xY?-34bYHdRIzI?}}+B-7sAd{FL}E@&#jT;|FoTINN<`38s`U!4%UFbK6zM
z-H9{ec3;2qi}kwCR=D&!a0b}P{`Th=!|dtp%Um$OPZ?l)|7F}=r%j6lo92v%T}Frk
z{(9r?2F_r>-u1JS&;8Q=vCpRU^<@M4@qZad`segJ0FzMv2Yp!|J^Sz+K+j){=fBl<
zDHe6_?+XlU`vYMPxlcZS2A=<_f5bi)T+Wi*nS$}s`7Wn+8irzST9`5>u
z=cZx~ywk9c82nYrYtc&Ck!;v
zCI>5?F-SV(8?BipcMQc<^9I}{ZE}Q=4`5wc?wEjiUAU)FbJRC_-ZUF{q`RRuxx+|e
zpyY|w;4OmkbI2D^W)=97@$MB;BEJ0=yxr6sB&O4Fe_z-6tfZrwL{*2Q2kXy;b$CsE
z65OYY_r-9ZRPP<_KMVX&Dd@k(lMn~UJ%FG}za`$)kSN9No*y7*UNr3QOOqjtQ~pVw
zhLx~?+W*2t9qgvfnpmcZ1E04}bEvuglXaRn*GUk~Ay1fCPD?U%dJJ{_C
z>1Ltt2}0lq=4P2O_l8*FxCzorqt((g%{-|6T#3O_tzznB@O~t6bcRk=7R86xT11XJ#kQULRBQ&I5S%4)AQ^zvS6O;Mv>%
zM?5>9_0G|W_wj3D{X6&Z>z(?EvtV`#GAPNE16F=v=PT@P?F0^;&zgAZ9XO%F-ZpW#
z#scsTO+?NFPCV3H_E_`8I8WdMtHZk~|Cs3H3f{eR1MfPwV0zo%`<~$291+W3$J`rY
ziFbc+*=yN3rnG4f%DGpV#p0k0ks*{p
z7y}ZB`sbE6wH)=&YgJYeeSU-a$cCv=EQK1E8ADIskaFbQRFLaH^wOU@qJn+Mz*S|k
zdUJ+nWkUvgZ-&r0IzjLZ0V{t0KLf7+yF6JX;to#KRmq3U=tq_3b78Qrh?ln$CM0_F
zUUTi}+6}n=YN?_O%SV83cm(cvW2V49x3ZUNm`elT!#NDt;ncf3G@s*#cDgzDr>yoR
zTPvGe9{WOWXoXeZb}#VKeyN7;8Dgq#-N(86bq0bbtmWPRR<2{p9)HGFYF~u2Op&Wh
z{xd4(QyTbl65!LYf5cE72C@Jr23RF(7w)GVh!>^bYTLn5EJU~wc-dwF?_2yc(S~+NQHDhk
zk%l^3CZrBN^OWJTXqVB?i?U-XR;XQjz_q(?4YhE4&EaPL{dVF9XM(OxDnYM&pnMmr
zwywUFr5b96HF;>^4I7bKm>!$K*~AuBqcz6e+;C#fF%)*xs`pj7EFV%E_%T$HImtpv
z1n%^5|-X@=2@0j+cKB7_MT>00OzmZOu!4`nE*%?yrAlcBE!mI
zKQVn;*183>A96Kc52PLPR@D(oI_;<}mz_}DBmHQwhrbw(T7(k{a8Pg1uRH_KtFW+U
z8_KSu^ifJG5P1zJjMjmV(c4O=u&@?e_HD5#)UuAD(KncXy+NIQPdPvjt!xUbG&CsM
z;7r^_@X^8wwzztvo3x9|asx157L0IVB$38M)Dyrkl?;y7g&%uF*Z3L_?+`Q@*HTTg*$jyekdsh`vj;Qb9?usq#
zQCNL|QgQrk$Zh)7HOL+D1$eUgtG5(UOB#k+)7yFwZ#cjAT8C5DnhdVB>0qpXp;UjN
z*GHyk+bGPb>b8lP&EIMpj`#JQ_9$lBFgP!h^TQ*slSlEIElN16hLp}=W5m8x+JC5E
zayXyDOfF(}yX=NdnR?Nd&z*+Tp3+&Opem%5{6lUPWmq){{J(6(Y(a*)in~cY%fa93
z+YY^tVL$9?fD~i6X!it;@cxak3jo#{S6h@g*1|PX$_Ht#IEEZ(E_?Q7zzy7e5y0`w
z;FO|hQ5;j;4IQxNhN}-zOBTxj+rm0nZ$`aC%O(Gi4Tc)KiV0xyu3-v8_s3@V5-49^
zXAfwUWM0U~JhBq@;^S)bX_?Eu!TOo+=7#Do`Rrms85-?ipHND#iJ!EaDjbP2&w`)fUT7mEBs)@F?TLy$#9Qat%0)<4zZ@q
zO)~jTW3YSV&e6~_UUbsMZ)=7GdsUGkvK>xB0JTEd|H!cAj<7V#gE?3Eubk!oqdTMA
z?q|rER4w&xp{xeWruHlQ(phI&%?T*EC$i2}^09#>?Wde2AA8N_XJDYD^WNXn0A-hK
zuJkjEa#DizM>=e_OM6%5@0YHIgHaO3YM}Y}%g
zu}ArZvcRKD$u<|aX4|3~KVu*-WjXAs+E(qXD*)_!E1@0TVK{;_tOv({js!K%zk
zXn8>s^sK<;y1pmu{NV?o&0lu+$}mVg(yo||!S^;_$2WS!x-qZQ)L06T;2bdK+dpjV
zZE2^AOR@0Y*!&~n^CBlK$jcp_Tg`
zzAeT66Gu3}MID8s=7rF=fkucvQJEaP?Sx{`?~aZI!pLNBMUUzIAKjF$#f0dv7#XR<
zGz=Yk)0_IGQ^a&4lz(e+Xuo`^JpPQHREN0If_~@w?hz(_&;#@rfblU$iRmgx3)lP7
z`T2e6D2tTF@@vNQ<-5wm^2>eg6f5{&@CEzRY5x0SlG_2lVUX?^lySNk&iKPFl}qk9
z#k8<=at_7=z}^-|)jQx^{ezx1c}Y)1Xg7*soFKi=EY08=Q(z|Ul`*#w-bB0nV<;J`
zTzWq1jZN%WNWT-6u7i0r+`R+mc`qf!M!BV2G8tKN!qf>nPCB5+q&Q)zNUUgETvyz;ho|AO
zP5qyH8Umsq|BtS@F+BSt?k|vfrvC-({z(&5RO)R-#n7rpY92ilbU5T_*s(G7;U_1Y
zdiu=db1`2TFC=_(tn6gPnX0d9zB%;W;j2e~IQEbFnh%vw8~8U$8}uWk9@kYNA5Q%M`wu;b*EM?wdRcZ$dF9`~p$#0bdgI3_gXCC;b#2jw
z58g8Ywrj1E3O6%j%07zW17;Jc^yS88?}hFGyMGJ{9RG&ad;E`DGWN6`@7nFIRwk>k
zmFgd%Ms34&`EWT|8}r7dA>+@?d}EVr?0dSRnDE$&*qQq8^uIT(ojqhu(VXzP6?13K
z`)=Ov=cmOFP1uz%VQS6PIn%CAduw{yf}t<&dU3)_H7@}d*f&VvSoFXD-~6LUE*LiJ
zTG=J*cj2H3Gsmi1k(SZl$fDQk{+*VbnYmqtlqib9Ho>gx|8k3dX?-Ze)|6g`)#*6zJ5@Z@_G-(Koh!E_zcO
z;z_4=IE&pqm-lF+3v>zDWtIH$5ps1qzzc5tY=dqy(;QeBEcG~{SMp-{H?EMB%KJT1
zi}h0Z-~$_UH+6W@xFmiv!z@}6NP-&Dly^3OuhW%}CBc7mS$dxGXy2@SX4RaE=gT1W
ziA5glCRYW7kc704%~mFHP>gx<`UC5q&VV)6nVNYk119II)+l>U9HQVYxnKpBiyU8%ER3fdpoaW~wgu&YG|V2%OtUU~Dg(JHrV7%h66U07y=eLvoPIs{j9VE`4j-|U|^N)yc?!q^_)$dex#Rv`x_G6x6EJygYOXUrjt2+_CY!g-JHm}*+
zdp_(5^Zs;Rybbs2UAE(0{oEXgOtWU?VmQ|%?Us~Ix#C%;S1Kf_NOzcH)m?zS$LI=y
zHdlUrMapM$@?!mCl@3=OlJqrMH^q9y=H7x5T{<=3;`n4;n@aAjPQj=$07AyG2SroIcfxc@0L7p~Tf
z-@sW4so0$`
zTuI`Exp;yrBe#QI&t`CUbxwWx%gy*wn8LURbi}x;_vjWU$mZjDUp(LS-n6F$14xtv
z@kmPUb!<(>yGWJSYz0n=d;IAFR}hPNmk&biP)6nM{zs|ok#~05VCdvCqeh}#{9dF2
zdce?kgxVHn$-M$l%_IJhDoPq!4@t@-UM<}&?a?gIRfF8YuG8RJnfeE)W6>Ccl#gr*c3VD2H+zqr-B7Upo>Tv_=b${yQiDZ>ed^gL`(uAC
z*(xEY+57dG&U7wl$a8)9Es42JT@~7*xl55YV*2CsmoM%|otbl3f_?Zs6UbG6{gF-z
zzEZLIIO<03HQ<5e+9Ekn11TbLK(ZHA7D=xQbd61@Ri@(5b)Cm^LEEewJT{n$J%}V}
z8Cm5H3C{8bk|o)bCP~Au7Dy$2lgT8QijRu61MHu7BAg1+lf}@^PZL1$LzU#afszka
z1zN60oaW8CFc;32z$kAjg|%M1i*1ED$Q;z$`PaMWqQt;FbFEana;V_KmGos^d)P<*3&N-?02G5M+iR_uD
z@T|PFNA*Iqb-h3?#9k=p*UnX${^Wo(?6^(1Q0~;JIL~Rhe@CkS`E})VE1fuq&%C2B
z?QxJ97CuGkW@Y2SgFJ#t0t;L#(;R{}%9D_$gJZ-dbe&m0HDzBA+cyF6$i*vAiN9!i`0SJ+=#m3+1f`Gab@OR1BP=hloe;TfmRh
zgwNmy|Bkrc8F>BcI_*e*xg~DLV1K40ZX)`XQs6YnWYqW|G2X(Ol{29KSNTETU*Es?
z3^^GNaTIV2@Yf8OIV>Mnz89h^5Jj_h*)oXEP#3li;}M)mOGrB@(C2pyW@tFe-?HKk
zL?oE-p!2gRC&{xLZLn_^pe4`lgw+8UMS&)&l(lnFLUFA?acl;hb(d`9mC%7Ul6RvA
zTa|hOHF>{2l)5o*R_;}hkTgX|hPnyuyyKQ`k3%!d;t)q1-eY}H7FDccnkF_|hkM`o
zb!l$WJ2eRfF>>gcp%1TMj({CwJ3PP#t?ZDwXegC4#%}@}+jmC2pu%9ozFW5dE!L$Z
zNo$r4L#-T#T8Yvh+!2Q@lC19MO|CS*A)W5CwPQnuXAjunQLs1*NS6TvF9-lDbQhW
zgsU=qS}`qgV9yj0#{qrPym+Z~>}1}fLxv?R$FU#T3_VC+k04ox``hKBp=P$TO;0wY
zHgz>@WA9j%28iH*9Mt_mdKMZHH_I1#5^1dw`!R{~yWEZm?m4^Q91^tUjRGB7#D?E>
z+`=~HK;)HWB+<>o4XwPaMs^6s%x}jS{K~`i)KM!-6qAqro||dp2SX3%9B~c2-i&iQ
zr!-7-3tES#EpmfFl7uDAI|hG9tJ`~efG012Jl6pwTOKog$K@Pp_9osSCy%s?65`}^
zU`JTctP-hD+FKlk^wR#B9c@^&!aMLW*XiHxxefo(e$Q3E)M`#Ead~YDz5^?#L4BG(
z>pb-O}Vq2wg7hUi@rr1XNWzS>T5_{%8n!uXGT9h%I=}4o0R|E_vT?XejtZ4bS1$SMU`4Tb=T83@AUfyszOj7HEs_+=
zXP%|qbRIgZV35NMV5Y>IYPOmDg>-Y4EF5D>wWeQO&$=5sbft<8qP*(jcYVxu_KVzk
zG3P3HuMU#LmFP5O()yP#*N}bdP7>F!`Rtw7Z1ZBzRn&>&N0?`dx~f;;+!9BRXcZ;S
zSm~ka&cU{VZcjjLY&EV8o$=NF-GZ!=WFO&u${x
z!8FWFEe?d=6??F`K(`(A{z3I31>vkv9a_Ipj{Exm+XcGJN(qAHxE!&Cb4{)hMQRgT
zE}Uz?`R|N@R?(?jK^<+Y>;vE2e;408Xp?NjE6oF~^Ef+>gH9hrd=WcSaq-`Uz8MkZ
z$V1sy=}Gzz{39Krj%atYW&7=DS+?5yX3or_6Qvm4HmGWhS(5FYf4vOnGMl{%e}(5$
zOLPLR30&INtJ_R%|I*c8US=>dPl*|9M`-eFcfV{{`7F`xlH%@MdhD)CMx+(FkcuQj
z8TVY7l{Q063b1-3op@dnj_-2z6x9vDuOKPku^(+Bto%X*3a4xbc3g$t7iy8Bidtzs
zo>%cs(ZIChqxgnsM`9KQ|o
z$lDdj3Dd5c^Y}y_>bO`C>svmrymvhLr++q{l+LDMZza81d>ZQlex3I(Pby!V5?Kvr
zXBAR?#ixB^@hQmKuGGVb-6j~Hz8NDZ-mFkV{VIj=jA^8TWXGCnt}>a&HpL1?t(Ss^
z+3;~!{hOTQ*>_^39&3Wohk>iT^4$zc{&lLcfnL@nNtp4d{9^?%jbVsf3lS&R9i#ZG
z5aXecffJ|GZ4n!n=^FkpxChI4$CN7kqd#~*yIdPsO(mA68slwFt^{`+g?XiD(}fRu
zZTca`ka|SQT~dM3Jr&H_l;FC)zPc(Gahd_P||J^N-A${bW4MBx`x|RiGvuo`QN^)Wep|xi
z>ZcFFVPwRN*7I2n_^^!ik)Mrt$oBqgq6~nnJTsy~;>;BV|PV*cK
zJDI?%#dhd4bueB!1u|-;lii2b&>6W^H1F1dXW2m;rIYL`arA=`&|ZI)sf(K>$%l$<
zD#Fo^Z!C^}4hyHjKZtfh7Vn<(AuYz}BHp}8=y6gm61Am>$c&mpoOnkOAYa-wvz1#Wi3ER^`IGj{|Hw*j9
z0$sRq=eM8RExlBjT`tb*&O^JE%m0AAJB~^*Cg4Zcd732?r)w%r`fA1kac$b^%^dEV
z^XA3B9wd
ziPHskV%y%;|^onfD>E4M#6{kg0s>n_`{)$-8v#S6Z5!Gs8v_Q@6}&hx{}`9UG1tk+K9@MEF-SK>?9pYS2>eE1XX33mp
z(&Br~)+b59)mRQ>VvZ)Zzcot_$wpqr052;{Ts5OKrW!>pN^{6Gu`U@29pRFZ2le_|
z@K(U=%h>*PtzD|6_*uk59=tP96I*vS9%h&54Us&EGmfc6dES$#{t7S}^lFl4A$qn=
zdsv7RD2}hlCQl8-EnJ&x;>@zm8JXgYKQDH9j|82Y?i;JA#Mz)W@H~;CcP>sqkBDa4
zF5y@%-`NR1RPc0{kwZWSrq(8|MI4uv&8P^16VFd{%Yz|`0mN!pk3C1^^i~(QhOOLn
zSc-LYrsAuzv|~j_rFcgYrt1w7=E`a6uK{!SBYLTS(kJEyfJ9l8%+3THgTq|wPb{qA
zxevL(VG7Pz=fGbsY8{L@e%n3-V@yy+e&s5^b-Gd^LkDBf#SrBIBBr4z#3cuaGaPja}cRZCxyX^!$1cF5jbq_Y(;9>sx>PFzQ#5)V};EMA*|(oMe?1kEy{rs}wcra)XaS
zg!W;mTD%tJ4jmTkR`&R5XT9fPzBYaz>;wHVRM!fTc@1zDM}xac|C+Ork?^oRYIERr
zE7LAVk9=2p5BzpPPs1Z;?^)Tj$r1a3Qwl|LL3ycLBZ)Xr15wufD0~lg&}hPQvn$V4
z;&>8mxeWI2B#y=Czn)wsjD4GW$G*9t-8dGr9L%uv&PESL4TCc;FMSE8@jGwA&N1wH
z3Beg8M!*FsT~wa~t28oBUAlT5Io-fh^dPH(rmP)`o=NM<*^KwoW6sy8zX3W7p5bQ-
z9!&U4r`;sF82vOcqYCq4eH@e1zDPe8+whyS_i_Q6Y4^w>e5RVoizPAOL6-SfoQsX7
zBbc)~{`I9}06ImcR3NeTl
zTOJxpN;|HS)FY-)rbqI7U{C6*1HDHWV|-N>a!MQ4cn`T{ugHZy1mcc#Wk<_H^blc+
zcG~~+t`e9PO6~5rcQhtKI6!z)G3?fI5ME}JgTcn^uqR`S#=$pWEg);#3E=>6=
z!Zq#Od8@(0)&=x)r12cO2uLWJic_O6GB7&ezqqOWa^@LmE+=8Yd+
z?RQ;+gx1K^gmU}k4p+|B;~_#Sz?gke72nwtvF0f%Iv_-(dG>UENxn=DQFdT81!CXe
z_%eB8^iWs@3_LY9NQjSI)a!LffEYlSKkJD`o768aX@Z%{w?N&jXRn%edXc_yLQ?d#
zBh(DaNX1zP8;BapsJyZoncdiG?H=}uHn15a7JeC_5dMPHlyBvM^nKSD#k|-I$1&pp
zftm4i-seZ$xoV>oymr>NJ4pEl5%Lbg3vOgWdMW!iT`6dB`OxwYO4nW09Y{Bv;nNwK
zzuTy|A8KAX!u+d%P!ZivtRS>ZZg<$nxaPR#&n!po5CvwOQm+Q
z=Uh}2OYdOMiPw+VGp>A|9t`cU_u3RIE0E;5N#*|4N!6NK+=~PIAx7eNQuKxLJT9+#
zTIB}Ex>^m4d^P20TQ)@}&&9WRa#i-%v;FcaVRBk?V4LTY
zx+J}?E<$lhm!FkX#kZd&8huG_QWeY^*0#wIUSCa=IM;X6LsY9<+7UF_4^ee8d`E$I
zIMc3dbWv8Qz_@{)HGB#KF%Ss@s|Rts`|aMfAXhop^`jfkQpSeIZgt({CZxgW)^v*=
zRd|z=QkyCcee>svr)ws_`0aRFkuiDRpJOh(xG6^aXN9aZyRi>D2$i6hEs6kZcUPM>oBh_EbIm8bmL(`M37>$}mby7_KaWrxbtZ<6|?tUle9}s!l6s
zXt#3RMUZP6`of#wKc-==S1yNfq!ZWCN|{zxOKXF!ksWYVG0I+SwIe!-Hsl&v{(XxhZh>b>6q_h5}1
ze@jNXLD^6EA&dt2bysrD!WcB4j?{v1rfKYoZQ2(j^tr%E;QewW?3VWtl
z|K5T1OYL~~B($^s=d@#r1>wB3Yakq{9X)jr5w3>m#<`844?c+0@5$M-e-1=Ig(&Eg
zlM*u)&n+IEOCKt%mZ
zJ=MJ}ox4evlqfhrT@j2xx43eQ^5HKOE_7Vw!@iT?tKawS9W@Wkl$UVjRBI@b4%saM
zU9crSK5=!`=>~zmCvXL2jG@yuu6$y&06p7whi1XN1rPyE2EP!N;+7#fp!7y5?Z$>jv}0AuMLFb)aOl52iTaGHbU#y(}TzA
zsAJRgFlNY^R>fawCmy=)^Mav&~J
zo0>a8PCI^1n?Csz;T*3U2uI@EiguVC|3k9Fp1qz3v^Id}M-5)g6|}AS2XUR^e)%6$
zW2l=L-8a)l9XNhyuX%cPYC@{Mzr=gp0I9XIBS9n9vmtys4O-HC17cb>0{yQ4Yb|)<
zx}*iq?jLspP{6rLjSIDPV9!&@cHiHQ_Z#KXGVU;^u12JS#(F
z1+iN*-SnvmK&#II!l6#Yz6NI^&D(L7o#lAk-e4ZoyLZ4J_LFNa1UNKtmg`WyT1Z&6
zA4;8bgR|M9%-4V0z2r33TW1TXlg7=^Utel2BS}!cLh4J=3*(X+LOdb9st~KzM%DXKg!gLv|A>1R@TjV*Z~UB`IddinkO@OBVAM$_7f6u?1{k2I31((U@Dh-V
zASy5fgsKoA1kjX(lS#k`0frE6+7L(rsYPMLseP*?k_%9)s0iBH8Vn)Y)=tn|2om!D
zt+UUNfc5qL{%^nMYah&2zwH)_bwE8+Xro(~kav-CD5h>?7Z>
zoo8?9NvrpD^8~sF;1g>Yc0sU5vX$-wm~F$op06Jm=zYB@F4xN7rf>0C&
z%YWj-DqcMom=?_w?rHf-xsnp$U(ThVFvr&P%wD`A)%(`ft+;4qejnDxXD6DT*?slm
zi7^?t^;h={r~SZNDo=FGDaFmriMlGM;}q^8uszM49&;_RKk9_Fe~%t3&+;aW9Mz3G
zGIFi`AxVgJEB*f6mK^Ryyx3->ow&BgJYfO{FZf2h9s5{~-4xyS7{x&%nnFjhPVi%%
zq}UYr>;LFYn76=Fa2J)HY`|UT&}@Td+diRNjB_3x$}n12LY~#%PW+x47ZyXco#P=d
zv8;@91>_}${jS6B;22iMYC-vEmM$WFn@NR9<)c^`aSX~wscT@}RUi
zW|cSLN|eEw3+-q9+uj^kDn_cdZ64h=&*>tq&`bYG5&gJ@>-U43)jGg%^lo)d`#oki
zC6=f@_(NOZtPZ>-fU)J*wD-adI-7(sv(-IIt+yQf9ZcSNgKp@rOB%qhg34F!W&BGl
z0X^8SUC#D9nrm@S)j?LTc^UA9gndQz4powW4|jIQjc4_YYQ1G)xOon9$9V7Ap#7{~
z`g6cHP{nr_t5^B*t@UD_Q}*WmtV
zt*fIWXvT@AmvlFJ>*Y>v_6*tRoQ#`OV97A+jC@qn@H%xo?tJHyONOECn+}JCU4y&^
zEKPUZy@TtGyo*X@yqByE#;9
zcMD!ziRK(3@CHkX+S4Zvyu`m(gWV&tk{On|#}!LCfq%h}m-{E&-NfU5JmT-@ZE7fy5n9zB=V|9GhEU6SG?4%))Y7PLLb5ATM7Uk>Gq6F>9d?rEWEd&_ljGa&sIj>Jr79J#oZID*^d
z6^@JsUZX%QgVzBZ0#~=TXjK|O)h4UjuBlXpxCMF_$<}0*E6y~0r}t7TK7{XuvUQc3
zZ+!&cj$5fu6q;Nu*NFNhpiqVXFiAz^eBTW~vop?|HTWlSW#{g+;j{tPMa1@wNOe|x
zlz-l6mRdEjHv^1jmkANZe>n
zM8p%la0R`Rdzw3-{F=_uOFZ7hss7+!zDIIwtJP9j!M1~Qi3joi5G#)tA@J%?%`LTL
z`$FXJQ#2+ar0xci#^7ZWUfv(s&a;9OLwKOO9P_3N4ti5;JUX
zd1^qV)Zp0qV^n(6lK2=<7e-~^fdqAEfe5b+;hfG@IGemxH%-~&aX(S;cpG^RN@|#*|)KDBvxy-zL`zAd61Ti5A^MQC+-nzyFqexu?Oqe
zP-sEQ3g(>a)#t^8bzr8^*56YCodz$bz0UILFcSGm!ud;Fi85MRm79Q3R2y7=MsQ_|ey5tHHN1}&o*%{9F}iM6&a#+#5dMz-U{2b!VwBEnJOf*1?=
zH@jx#ajxP#{;!)2AvkBowcT9;tq?uYv-N><4|rQmfEb;PT_-3U2MX!0zv8x5~
zm=V?33E);O=$9CuPmzMA{gux!xaoI!6Xp-?I|Fk9VO2_%N=q*)oJ4f}lcw$a-!B{^
zPE_mN33{S^W0>q8nrpQ6ID3p3lXH)g?q>2ksLl;_f#|2G-nm5ij_k!+11!BWdU`lX
zA>iLdFrD^TC(U4>f99=F)3ul{BYL4K-*@ztL87bAdNhb;p4`FEthqO)QaRJM{qM8B
zX8Jti9(r{jdQ~}x(6)tEFL*k)xA>9F2{Fzb+>VC(edvW5wQuy8&jt-U(Vt7{}4oAZsZt|Y};4i_qXe8Ew
zOyiK&FbyMJ#I0xh5Xq%TVN5X51$qL#XCL|VY!9N+aQ6_~w{2d9I}m>dee)*ePW^6=
zXm8ru(!pvwgYQJNRrX5XS!eBeb_#9CHgWMFU3b>l5=8jatLGsmmvlk1+O$cp%9@?U
zJ%bC177?H?!C%*lFY3d-$5;;x#5=j-BHpTMiX{~JLOMh)7oO-`?D(#Qi>U6GILeCn
zp$>|_@~NUEk-Zc0JgR^h1SM+V)dX4`@_59U(^R`kw@+)pzdwabg
z+&k3=-|whie;>Y=sNNjHxBB*aMgQnqukj747wp4_ldH~?jH~H>UgO9Wx7U8HrEhKS
zDAf*8Yv(w7Ydd?q#;MQUUi*WlzO{|NrP_nl+NHU@wac%2jTuXCukHP!Z|%gxRQt~K
zlI6tj>g?XybzR`sqT6c+ecreBymG1?sn%{>+grQ2!)rXc;P%=-|Fm!Ioc&ZgMy<`Q
z?yW7hd5s@Fd3)_g&h@Qb`ZCoXrq(vD=&c=d1(x%i+iNd7+qZW0ZmNBcT08N%-rClG
zp}%L{Uc2bMzO@^RsrE><_PnLNwbTEB{(kiK+OM7JTbtWXwa2Kna~Ad1c7BEae&qJr
zAJq1(ZQMe&$E&qV7xdOHZ$^JlxxKcxx^L~o7peBWYVGPLdu!KyiT<|VUONa;ZvI>o
zFV?aVnV3KREsC$AmDQlF*5JOz{*LYSel)8^zfk2gRqcPDNq*hm0B_Q_YBZHWtJgU8
z)nj%#`dIf2p)TnICUM-2t`jb8so)rV!B57kDgGifg6l?rNsFnJmhyQtwHjvX#VgAeYKbvyc9cnFw5wV6+U#M9yd3!vk854
z|2-`lm!>(8XvWDQZqPu3|DXV(6do~dbg)6wrhL(gHeK({`7T|wopE||97b=B8NbW$
zTNv-nS-Ft3Q~XZruUHXHJ6pc(3wKAqzHr|N>RygBZtcm=L(2EHeG
zTRQIh_^tAS6)X|GZ{?tMLwkPCsVc-k9LuA(t>`@~lY|rQ$%X)rd)V==4YE0r^v
z>dsN>P7M|C+i9hG=)<4Ab%N@Cc7il$cL3r_jUNtm1X}UBaez-J_#Nh-fqbc`ytA~)
zL$GMoIvN~Uw<#yrN)#Q9C3qnWia$Zgh!*SQI)4>L`EisPkUit}v;Gu$!r%_`WM*g^
zqUvH#rq;aww~szQ|K~q{`nU5mE=_@W_ZI(@Th4IOkx%|Tc6Z~G_aq0Tbj)5f=lmSo
z<8MBm0!Vac8f;0CjS!cAE^pAz=ihfi_ienpL$=T7-#(d}{M#vF3iXly6xMS~e_PnF
zI|pypY7Pv@5KKXlf@9G&t!cm&zo)}ZJW_+^3kSGJk#W5GZoyh3IIT{!dTN-A-!q+b
z+5qi?4Ktr_`g_|o<{3y7o9^gr^Vhh<*ZoMUNB47tiv!tsOt119_h)BMzw?A?K$0*Y
zlANG%xLS0#()`8W3F4pr@^5H9@B^CXU(@^;%{haJ=3Is5;C_8+o}cNX`KX5|ISqZ?
zC_;;BGpO71y~aSo?$i*+
zMmRAq8n5s)FOod%e@3C@>$Yn($4vu93N@apyuh=A!WqY$yS&ESrM>(CM;pKR)Zkwu
z#5xVy3?5^;@rw%rsFdv)su#k!v+3oQuULJtq^Usi{RXU>boh$epw;DF!jAHM-r;Cd
zt)G|@ukoV8m#f*SjxxBg|BW>d
z2s2^hHv>0(Ju1E@yvC$Sf)+NulJ2}mEsyk?L`H@7sA}Ukwhp;GhPfo{j4(Uj}Kpmi(HzI3d9_0DWp5W)M!gHFaLd*GS!}
zb-dhi3vZp1(Z9irQte_!sko0(T4%#J8(|Qmanix%Fl$Q_887S7`{WNVK_5ZGvW0=q
z*b`U|z7JLTyVuvc<-tciYW@P`$KDJ1R;=
z1-)8EZ~Xw3-fb#9zd$`xuPiwGvvli3$Y*4)EY$T=%OjmPGFok0eX?L&NBm`46RmxC
zV_E}`aR5=Q+z6`85go5w0F6mw)i%unoWVZtg-gqcjy=#l?J-yhb2QWs=<#2$vf@ng
zyjE*qx5Jj2KZ&KL&&-C-s@F7axp2*;J&QU7e|`$fwa&D97?k;GETw$rT3RJE(7dkF
z>$pnK8%NGOuG|65sD=#bI|uowHb{V4*rIn8T<9YI^$fe?nNFO*MxRLybA306Gw9A~
zXiq=6ZkyUCB7Fz$FI91;VH^jPD5I+UBVStA3HGb*Vem!A`p1^WO4WVH@h6;ezpxF*P-%zvMijCuICY7S)9$ot8kTvT(M4>?uoYKFwl=j2Z!
z)tvMPcdI#8t5^Twuh?wM-9`J1B&{)1?)2q9fczKay8UXKov9<){s#6qmSmWsa|fDY
zg9n|WUy&?Qm`q0YOqg6pz++*IpU^-;N4`M&V-j3z^zapzVa!%n`JA{
ztNeJ#tKXI>8*2s%fG*I$|66c*j{7AS&bZ)@qN)A^k;4IzH>gGXLe>ATOX&w$1slEUB|zAp@|
zHUw1NyF1y@FPe|g71kB79Vh*jx%4i<=C@_*RQ_RSw<;InMBsZ|r47Hg&0)XA@!;2N
zPgs;0`y2ZEP8H)lUHf#?5PDD7hwZe5VLLPShuDH=61L#uK5WWp-rMrG5t|a!6)SzL
zzeq1ids|md7VNc{hpN@SbdGNt+}XI?S8lXHgig_Fu+hn+C@aqLWp;9#Wcd6!jqXf-
z1^630qzwLYl6Y|xpN#%}_?Y@#H!2JqHu(Gh2JLxJZRaSjKKQ}6Q^EpBR^lH=jM)oq
ze}k0dKx5Kpr1Ga|&(2Y7;Yn&TQbY|bZuA0l?T<>>yb!O~iK5>rZ>xLayVgyowG-k#|9@zx@=-7$n*S^tU>sF3mC9
zTVIWZKKQ_0Oox$PR6OjBC&RI)xoNI0aA$!=hjWo9ABfLClAr2)A2B44_Ge`q3Y4;E
zPXfyWns*XMB)^h8Am!TZB^bR}!M3&e5#$5mtn}hM2H9j#AnTv-AO>A6;|OJC;x@1{
zO?oQxIhW$uj9V%bwN2aGt`V#zLkVVX>`Sj_w11-LR!;PhOI`o#!%H%iwLC&yA8{K>@Cd<{tV)_QOkGbKMBEjYFc>n~Q(?g=wATS@aCAvMXwJ6{ie#%G7l~VVeCxNPq@`cq)|S5oiS$$TvH`5M
zF{+l(?7_IWySKIFI))|vcV7L`JA2z&F0u4xq>qf~ZELw!E&mqE5BXtRzxdeK);f(!
zKOh8$`&w15rlwQ66Myze_&BIH?lJoE}bv@Nu6+nRp^xmcyPjc093
z?_ro?s=)tXgEq&H@im5H>E%ej64WQ%S01xL#(?aZthDupN-t7_`>Xu!rkh^jacWFl
z+m{OG0dK4P45K3ddsUt~)%yEU-@li`&Tm<|wG8vB)XQP#6}3FlgSEXJcDAbJ51_n8
zu&q+1udZD!kMv;Shn&Cv4?fPve8Wn{pkxLo%*^9i3!DGR(#w&4@mH*cvEDm<5;Zj2
zJ=G37wzY3dn|FZUPpJIzt(T6o(~buj
z^%b8o>YLBATIIRm@6$fM)Lmey)(u{L?&7Jo-5!@@Q{K11%TkU`zoU3JrUMaBvpvU^
zU!v{!iMNzr{cW311l!*BB!wEXI)XOYagMs9SAN9vVRd8y*Zm6oUeHH=-ec+3^}si;
zkNkYBmPb1Ol#KoH{&+X&!!Xj59V_AO^36LR^{GGihjMnJ*e7S@^{iw$D7ZMgSI*Ma
z^cY~8|5z^t<)_v1NWVCf_T9@{d~;y>A6Z^A@*-#4q~(u{ci2DF*E~uz-)na)g+{Mf
z$+%@qnaR^nu(~lzfp4nX-!=Czxo&+u`?Eh_FA@`nr
zHy^*N=4T=QL4RBEi5i7VD7C2b5W~IbB*R_qVP(@7c=h{J81Bn&`Ea+cIs6A$skA$M
zu-A62o)o5NDKXWi68?SEdm!WwE=g1(Zer{>ZN-^#=p6=^)UH@Dcn4{5C*rA!ubFbn
zS^D?XYfZoGyn)o~-*{3;cMpZ`9tzz(6uNsDboUVG?jg|KLrg>GhnQkBLYUVwhrE`%
zTXcwh(??E692uhpvvefhT!R(dXkH0#KfT?C{3>V2Y3RJ6(BDI$^M*oq4~6a?0^L0X
zx_gN5Gd@KASnu>$>~i{e$klYL_la
zH0XHoI`=#79Jf`SPsP^_;%MM$GUnk<=zCLZ=D7T8{7U`;jiYeN6XS8Cwqpjov!%&=
zVO?_glg`2!<9X2^_=Ywaa4&|aj6JNTHE}*VvEPmJF_3MWkE_mCksp(5B~3ope$zgB
z^{~oy=Mm(aa!Z@OnAK$}ozBl@whiJB2u^OQ4^G{0F%LyDIFVDToOhm9`Hl3NyQyy!
zPX9OklL;-2)e(Q20joMqQz9&)xbdSa@&-fp^J|K4Ow=AQuF@E&Z!3MIiBdWFewQev>m
z&Gf@b|CPth$GDGm`kgn0^Ekg|UctV-jjjx}{lJ*pk6L)ET*T&=C_0+8(hF{2$A#MW
zXT^?c*-ds?@-)amG*6LfWS=GJnnFjbEwkc|=Ol@>;^KJc+XnJl6t`S<`QvRB@vQJL
z=z(rL&>@L>_>)^7_(k9tk@L|VQ})e&E!Q*b|FxIP$cDA~8QDOm|Ln7Q
z{$7ZfMGceWm_jc%^7+8A(b4@kj+(*Oidw_!j-XuIONiA9zJKk11zMwXUE+Q}^l9t*
zeyy((tgDdvA%34YELijK`yzh#91^S)!-m+e*8301_FVWS
zw?Sv$&wVQ`Ks)F~ylFTg{8`cIBEfnT(Vde-`c=b?QvQC(MJazTa^n1fc(-pu&f1Kq
zbN3)3FV{L0w|9FRA5Eo|U@}grxl>%?Aa0m#DCXDi?x9{1?l5SrJ>)G{@`vNUttYO;
z=b=RF{a5&J)V|y3<&Ms$-7MZpdszA;u4Yiu&2duXR$TLdlONFB^Wf%2pTRt6Ul`(Q&d89(khfipZ@TX6m`NMOiyp>Lty4H?HB)dOuX@zCY
zefVghHRUn*W4MuzI*OO@Pm;V$6EzPhUOuJwDFV0eznk~Clz0%ARV3LIOHga1mCe=Q
z(=rw9sQD|jf267}H2Wrop&D$y&}i44ng*bO!YZ);Cn?eB_3ld=a~Tc(Kunc?;6JUGok!^AE1G
zad3qzJgAAl_xG~>BBb~VEFYR7oGZ5D=2p@bm=DyxGcdWctPC8^n26mRRwe`d{)MXB
zDm*L4nGyG0tbLa&7|&vcsqOn1?fXSkKI2GTIZJh(LqCqk465)jMoo?R1bD_VUQ`TK
zJzT2vZjta8e}6Vl!$*a4cQI3{WyeCqy3ms
zV>PPze}tTk^5IQaHP>>aUP)khV5sF#7(`#d{)fdT*cSTaX*SDCN8Zsm88NehElnGdZ;2eWH5a|uR6nFR)dXk67*x~P5gm~@(NicMD1{pfrxN^Hon)eOQ$rkx|zC8u%Bcjt@yam0-NszwW3@
zG-@2%Jx0<}9lvhy?cXSJ06nTv&SVhtQyD~&V-V}Ayj<`=*_I5>j#fEqoy79Q-#|X}
zGI~S6NM<~8CbB#$^0p0Nl+@o)rPFxv?%i)W_FWjLw)3t|tzi8`T`##hAE>h{r>IZJH?30E{NMnn#4QBg~#E2jzoq>NYWtCw`zsmJ
zs90#q$gLZ}@|?)4c|nFmQj|C2n|P0k4|)9ajBmDo(8>b;h;ja)@$ZnQyD!x-+q{jY
zIgIMdW=3`SB?cuOE7$(j49expsvPJ?F2DE(#;4|yUM_OQ*KhF3om7YaMCYff3e3`R
z%z$)rt%Li-Z_MOjR@v6sh=`4d0CX(uc~Ox?!8m&xvW2j{}>en0ro
zJI-9&a?V>_Kg9`|@J;UAn>K=vIQ;PSY)$L+B&cPO0_*7^2An+~y>$bj;DYT-iauJL6
zIzB-xR)|gIcPxu6$Nqey9K(NuIDdtn(rfVi-Mn)kSS?*{!VW{DV2aP;EzZ@_%v->$Am>35*tr=LC{
z)M_|~|3O6NtF%O*{f~mu*1KD0e3okuZ0O2&++BbhS-Z5KKd`AG*ZL&xlUs74%!#;C
zE;lXd1kP-}GOL@oT&Khl#OIB0_Ddw5;kN3=17Q(~xTm^=ZYpQDGx%Z+;`4M#R6-89
zy+pqn6Jp&=2K>|DUkLt%)^USQKX#h552~-Nk4TBn+jbK7B+__;2V?GJ$F|FUI0eli
zZ5GDMjD;L|X3fq@yeleBq?mZ6{H$8!9ptJ?=-r5i>yK@sJ8$STQS2GKs*^Wj)7TfG
zk#;#=_J@7tyOoCSiTB-16EV3;!My3x+{s;EY$&;MqN2dDayNITK$yLdljqdp7J$Mx
zq>1MI_@uzG+KFe19o@BDEFxYu?3QOOug3=N7tGHv%FfGn=X>I@1z7N@IWA795%8eCtCMtfD_WdJ>SOfjv
z;5I>?amfFla$E{eZT}YX>U;M}gv6H>IKIo{DhlN3r@25-EYDiP$&i|tU!pnlonlAU
z4lXJmHuKp>pU*rItNe1WqY`HAjzqI_H^<)2#;J?xbq*O>92`z-EMDLTEul1`ZWGcZKiqEB&lHP)q3xWvlv|<0
zs9-nUk*&g@9(*byG4>h!Csa1{8{8n&(H(-Vf}^LR
zpHM0F4{m_n#E)=N8M$FGR|iiWX`JOj7~i20i5u;R&Kww?$S8|ANt!y|h?spKPx9%e
zxapD~gxc0CxITf)dV!L19I67c`;w6eAdp7f8kvUpOvqE;C2fVARWK`={0sxhDSrkE
zTcu4Wh1@vNi3SKvMY{0KsUr~AvcIfa9wkF{@^m+&0)tZMBG#Yn9oDk^goJcc=LoY=e!n!!~
zEQ??X#YvyI`n-#)J$Mqay{N9p6x)&K8kEO(hdAx#Yj1FY7HOg>_VN}7-*%VBgHt%A
zlFl?#o974$;QSXEv=u=micUfMDvB-Q=WWdi_7L1k+Xjoob!Ufl0j_JXhBuXUZ170e
zac5x{=h!QSTBO&bbm}L%Gsl&s>2Yk6
zB9wDU6;e*ko|-MD(hE6`!2#h6leP~gQ)$Nrp+Z}Pb^~hW9@C-vEkcEDQ}z~9RsF^%
zzJl%&ZhEzTgC&&n1O2V0BlS7R&#{OcZ_u^(fD?nwtF`P)c~H$P|BhtWc>f=z{OSbf_a=uB^{Pn{QB?O%)w@<*j~WQkFsL
z4C*TKUyT0Oe@5vWO-Ai#+*L5z6s;Xit-8}5h1l?xEnZ{mP`jUFSPXVssK;V(i^KBO#c#Xc8pgX$59SO7gE`jIE$Hd7xH;Cgp=L?<
z=DN+Ms5dtpJx(yR6%0o6-x!Q$+{~4*;#s#M5&u%*|5b&L`$m>8-~YBq((+4|m;M))
z2OGQb_2*)a!wZ2vfpo-i0($6TrTO7
zeiaX0U2G+f82Y}nK_@#yIYA4@K5`8MZUl|kS(9#%+k2w4?#w#gym}GmD;LWNBFa@r
zI**R;8ByFF?itX-O%lzkLwR%NC;ZgSrqW8l8+)^yMTeG!k0>TdTOj)KZEC(%*~bix`kbg)IoPDRtaqUZpa
z0b2)Kr0VFoPd)aO3vmh;Kinh*9ilXv^>eeT=a-*_e5Bz;xiFIU
z5Idw7GeLE9-UEei|WN8dqoA)us~63n+s($~VBHarLh+nT#cBSx-R_?5)~~
zto$)eb5YYS=`P<4ke)@7g7T$1H+aPA=zU3;1vdEG3q77^%Ov!w_roHZ8}=m?dKS;l
z{RjOmNOxOWIYUVp=Y!I|7jlMDke>~BA>By78KrM8?xnSiaPO4{QEP-sDW`k2E59Qs
zv*Kf;51R#va%!mRU2N-7-^}3dk)Rd^xQ*bEe(Qc}b}?Tkgtzwx}kv
zJ47secFUyOa%U*Hn15Qu!tRh2(z9C_TyV9lWkcSiUMf|N?viwjqjn!hqi%9k$_Xlb
zBRPU`^doB3c1hza?a^-S=?-lto}z{Yt%{f=$J)^<%qbzny>GUBDSc98it5~eoEZCt
zO}0W$<&rW9Hm?`2JSypo+Yys|+;;5@<9ry}_p;iI!+38T)cE9qsBye3t?_8FN>pk`
zTBNN#Y7ZaUnecC=r`1s+t@8B=^@2zA;~>ketY3)p_6R$=gTgS!tA8SSjhwb^MGNq
zMdGjHmew9~)_KmNeThm{wY-Emdb35l3HGZYOR6?3_GmFjE2)`9D53n8wpg?~qFH_%
zUgB=qVv%sBx~ydjXxu_`dp?J8iFBdTp6dyP3}J3Rya;JkEjdWr6*L0-xW9M>e%UZjCE(?2
zbLgHQPh#K&`(sV}@B%zq-diu?4ElV0wlbzMhmWJLnoL7MdrwzU65gHnrMaB#LEty-
zw4Y#Uwh7r`7Ts06b}zMJZJ2;{WWumT22tDi4Xq&bJ>CQ3)gm->KcMTo2#CoAy{G(=*WymhKTm&YUUUmc~sqXExugyLL0J$W%UG
zg^T(J**E$RYrYE8mnP#DYadKsn!qhIuLsP7m&X&FwVTc9GZ>WD>c{a`^ZFj%ylg#Z
zsz5$cJi?R@L5reUvOvbT!mM_IH!nuNyvowd
zS-59?v7}+&4JgyvTjmIrX#gCxjPfnzS#;ICWlAw?R!VuS%wn4L@}JARCPIVBs9MQ3G-w=)uI_6IcUY@aWwm>
z^)dIMP6FWxdD@`Uy>6y5WtZ`ewmp~1KwD(9Xs#j4a^0}FpwD;bNkG(5{vQ%8l3vm9
zN&5d#jqie1Wo7z9_4P!O;_LWJ(tW)eFBg333FVA(WqmAaRnv^9j=0!;528#pbPRFd
zdtNRf9WR$;8nmZ(9)tH1zSdT6sqk|RUi5+oYD69AYCiA)nAAC@sW|4Zh
zl1ljB3JMmuv|(vvWq@~R(FMp9`lkY8^H3OOH;Lc)!FwNU{rKF+yDs>4sMy;xq_1nQ
zmDJImSWHwH{^G371aITKG0R#%Xd#VVyOib9UJT`0)4Yv2=8WHw6%eXrdCt4kJlr8y
zJu>%q1l1PI^6Da3UR|=ckxN*Hmsb@VA%f-7UW{Uc-0y8Pj#!2_mhr&+EznC0Sb
zrpCnK%UU1#n(D^3v)q_4mRpWnp6A7*?iUFiYg*3(0=+j2J}KSvk7fLufdMGZ4j`
zBd}8&pC{Ww6#q2*{`rCxcd#@}M`;a8M|1K_^cVba4p*fgV&W7pp=tXYekNC~pJ~TA
zKU47~Khw@OKjy8Z5_Id)kCj-)rA@~<#0v}knuO&jjzA3jC*|^-c`*o&Tmm{+X=LVg96tCk&)ehP^%M@KZ=%2Df`UAKnEHo{Vtg5tXA+|R5i9M(lE63%aDDy#y)U(s56bfw@`X&vr4<=k*^MiE6}ze(Y)iyCta_-=;9*!zMhy3J@RUw
zx#xqea$N1rc?avWh_yMk?Y5bx75h>N_mQ?NSK6SBjI5{qPLd{y&rY`h1bknG|36x^dLVFcEFyf$zv9$3P=_+@4(Kkil
zXFS!*8*eDkHU=-FGDsV)z#@(7Vm4wH$qxeEG^%YP;EgrN+63tPpDSJy>aD1@v6SB1
zvlFRj)zl2tJ7ti9N_$gbpFs)$8B*yHSlPU>7JvP9>Jmm)_MKmQ8*<
z(U+>Rc%)ot&6N5Wl^u$*v6_h}6K=6%rop&>Vhd)1i9&2LQX9GKuxGa*C90NqGtrVC
z1n;B7L#`BVX(kvpUWM&I9E65yM32O1CU#}Hplg#a$ki+cnv8Eulz{_U{Qd5ZvAp~8
zBHRytj?%`74#NN;r)$fHzW(uALZZ7phJ1y_H^zasaUPM&A-WVVjInkc)pK{8
z=c$I0ujMXfZ!s*=CYq27y2nxJ8ALP6CXX}Jw_}dQ14Kvx4y0H_DDO0%-u&h!DiGCg
z@}$;7mZ)?daA~P-G`@!Bjq_-i^X{uddG}YJa;E4(GnyO8r>mD``2sFexpzc3jsMQ!L@H9j8)5UlkgesDbb6
zy8AMGPlwKJpfrmPnkZV>Hx2e_et%jU4qbxQrjb=!<4_yE@??*6wMVhjU!~kUIlBnj
z88pyK8|2Db*&?;}Tq%P8;YgeE-9_@|$G$Z1&qB80->c2T(>8gOM>=O)9`2B@rtvyo
z84)x~V_w0i_1!3G8ljBWB*4;RR3;vUJx4lcTRzo-R6~X!HPUtEM
zA>ZWd$_PuCeNRaRbdCJ_`hAn`QPNG=FCi$F`s!%Rjh&rd1rEU_ACxk8XeKZ@EeKHL
zG)^;7oehj_kZs7PBE=rco%q5ecbA2CeeFNb6g5_qZyR;&n`9pA8I4Nt*W49{{)m?M
zO=7g1iT&$dQ|vYDSGTT`<6exySM;^0VZXWkg&j+&4HMXRY(G=Qg$eZCwZ+mI$e|X#uO=x}
z=42GjD7sn$%V?}2OJcT4MGN{N={)V6L1(y?sur#O$EYI9M@sBV6~kYl&~r73`G_)T
zd?fb8h@J;VP%wc}Pyl*cU{f_rz{s1~k47H88AX*pr08}&Eryh;d{QKOYhQ}`@@eM(
zkWUK5^L|M2k5Y6ykNQwFW^rF?7=Jo`$RFbmvGww&p)Y@S{*XTuH(FrJ@%_63uo#f5HEQZxq
z(Zuw$+8*lI5S~b*?|>+Apeqfs=|vxW8!a1h4mhRW690zU4LR6{nV1x87E8f3@9U2mN<6Sc3kp^%Cjm=8?$5p@^;;0U
zue+5NQk(|u;ZUvbf>^1zRjk&^06>~Ve4tyNIj&?U?3arAWxU<6F;;LDsVJGmH@T+4QV(yB{MxYbvJh!4wBF1MpuEZ(
zyv4pkXX);Sr>$!^XZ^{wDo;wd{HeH&5r0gyJ(HT-SE}pOv7;(1h^?GcVbst
z_-{Ozt#{cWSJ!tnD1X1(g&Wr~PYQHSh34`IJERCYp~OctD8IkMZ%qVBQ3MygZ9*0%
z?G%v>pxBaR)xZLHY`UwUtLJNFoqp`xW7DhhL@VYb<74NhPv_y~bzKhSrk{g$6HA%^
zX7MPd_mkD|-`D}1J`k(ft#$x+)}N)_v;(-;b(CVjsncHlAO04Jm7|po_5+uuC8}ec
zwAQsndFLf8a7igkDoP4H(nPxb058}tLv-e*l)dAvju%Js266Y2*y4~Bvo%Jbk>Xu$
z%%CCP&(av2HO*-p;Y~a{*cS!j;M>=*G0>7M;I&uzu${v?lc(KHz2SZRfrZdH
zBf7KW^W7b9@^z%EMhNlA5l8alt4F-6od4bW=tCuMQT$g*l2GB#$rUMF7`}0iAkoqf
zFiM3PLM+l_Q#eb1uF<@%iuZ1n@AJOyc-W=A-jfO6r4<_I!3aP5c01YsC2s;+{-S#~
zPI_;WC9t)}ef4R6LjF7X6Ke0Pw^e($K5FyfaW1TR0q`I3!LRwH;l=Ag-mM45;gm>tf%ry-=JMnu_<0Y|NhqryTsCgc-_ck&6gE71qr_2TzE@b&Y6pW=hxJ=o%3
z(*yXU0Dsbk$sY1l!2Y<2A@*Pd?#SQiotHKV@?nS)&6zWJcc-1l3^?N8KsE0H0eP;h
zcERAx+le*wI_BsRZ3DgYTJNJ;3q(uc{jfDGH*4hqV(a~smpyorsQ6bh({JY1624zR
zj~jFgKI6eb2B(rYQ9vHUr@{WLg3s7C2rw;5PMDL&D`+L=EX6`pa`fW~-XzeU4*KH=
zmjW-j#5-^6Xy~Q4;))_%O5PX&d1~8yxS|MG!bl}Y!IkI3rR1c+Pmp{oE(KmKaGkve
zuc)~4e7NG3{t8uc
zSi5|xYA!iN)Bt+9<^Oc&Q?9a
zy9Jj5FL@98q#yWuE3OeryC|zuh7aXIjmiK-D@qp`)hb=jHAPl=SL9HvggxzvY^aM
zeukXrFpQ(U-g$|?0*`^uy>13?zGmmme^136nXKj-*HbRm4Z*d!dp)eT>lmL=2SXoA
zG~{bE7gxKpJt+MKu-C@AiaL5Cmpy@X>QXFt8Jm&i(sjaPRKjD=jQKMWe-Qkf&#P&W
zHPx;y*L%nYf_E*h)`2~{M3>l&6!;TIv@M`CH+Ik5EiJt78#G*{-@xdAN2Qu(McDBp
z&MolyNz+24KrbKd=r7kE?rDt}m}`Y5p5w%SU+dvG4@JCHNCT6C@z#T1)lLgy8%EUg+%dbM
zptEN}eRGc-ryW>a)Ko9sApMoY|9o{^QqFxz!G)piMyg9SdG5cfOEH6n+3iVY>tU`}
zH>0-=X1;3{W0D{N#z!;7vsfQ<3=Lg9v|<-j+WfkT9?fjmLnAT@F||gQruBYL0Ds->
zd4ua7Qn;f%any?>&)(AS*0WYu_MCfQ>jU1crW9|fImsjS2$RHY+RKD*;UH$nTKEgN
zQnD}-Jm#nNlfN1dB_X3ia*r*A9*yyph!H+dh^?Lfk=7$ZeMStqdFdI>G$MIEcrYJPkw$Y?77u^L@NG1A-Z9_(3(5OQc>vY|!u>^Ux3TF=H6r9W(jADm8iNiuv=u+49Zb~WRB!zKPPe6vduQk2
zFPVK=pm0f%m{(ioVILabEXoCY&hxPI;*6TUeY)T5Z&Mbe-n#b^cARz>#htKsrp!1|
zQc2cjWw@^oj=%jj?&oVqG?F4OipQ%n7FHB^AYjMVm6eHes`Du#tfC|K<~USG--p^C
zAAdfG%mV3*rLp|BJt^41wQC9br<1V$WA8{>Zpi9{)PDZ%5263q*rxiQPs%1Q<$5*d
zF^3=!4#GS40pI)pTdipBNgrf|-ddh3V{=Vy-?`>im<$$X9^y-d6ot{%W46Fc5PD_H
z0%-=KG+LrWc+Z-(*g5xy1h-P(;IAHeRV_NiK>1_rH2Pwol(fo%dBdzqDI-c9RQi$Z
z9z>@;yBFV4=vSSR@2BMJu093cc&~o3Y+jE4kKke08wopTG%9gcI>4DX)rxiN;02PE
ze~&}B9Y>7lK2Lne3mhdcg%HB7$tgFKE26~-3#L-Ku*R#O%(WL3@ayTZGNVm<}s{rly_gf
z_bg{TW)FjB#2~d)sb!WGdK%UiT04`yXN`CHa;4v}Tqkl%o@Kd-5x5;ofm^<;@Ob%9
zl)uB5A}%jHUK|bhLwqUeNO2myXB)$PDRoH6jKKH_^QFXO6dq3x_ns{c^`$tGGGmbU
zY)*(Tr5Pz!z4z?ALB160io)Y#`gzYL8hk0`NQu#bo`Jp;ab@B05Dn-F_NAn+bZ)}8
zp0z++h5A7cPFLH5(n|dSz7*>!wSIqJN;6WL$Duuez7%IBqqRD~mlCsDZI8b%r4A`X
zYmUyBlAc9$`?h9*YZH+#_NIwzkd_I0HCV;^q1O`;;l5cdzXtXF
zUy{dg7E%Mt^3A1oO$H|&UFeHK0`GcKD?IwXR-U{?>+U&0v^@NZ)<=ig@!e11eigVCybT$JyS}=K
z^CrF{44?3tv?B1XzezW7{pyFfezKjVVJqcnPy5=r;s@<~YGZFZ%fePF?L1Pj!cg?V
zt?dM-Z*S*M;ywu6teq?5Cl7IfzeZb!7AgECKHh9^g^IUKS{ZoPjo$Y59Qy&zpXBW!
zA5QzqzW8q9s$#f=*9w5^f63cdiMOXz-ZrfKA#cCxZQ~IiZ>3fL5#E-DWva5fN`6wu
z_igJfye$jMRQj~6VAcPcw+DSV8&>tjcaygj3>V}!^MB3TL%=m{D6h6L^M|~h%-_UY
zrMB@%LFRvix3Au8XQuq*(?8DJBR<|rtN+)$Ee*?3+q(MS^0q82i~13A3taz8xjhJ2
zPi{n99?g9Xt6e(GY2o3LFqF-Gf#Y;b%ui$9tB_Qhq%4{ng-=gug@%oo>D-(v^ZIpw|gdYJ=p2W!MThj&~++W)(Eiz2km5ScX(jvn_6K;eUNO+
z53-!X{4dH6?+h}phjoq^)!@b0RSmj=SVZg)Bf8qWxS220K3hb4XoeEZ{85
zE$gTy!hwQyfgyF0JhLuHu%i`g4E*nLhd^IU
zQ#I>0XtiGc5%)9Sb&-{GOpP&46!TCk!mVPwtZ_k~TOY(WScoAxJTc&RrKH;1m&^aay#9Gq29)J$GF1>AoW{TqhL{k_69n
zfpab;D2Bp->w)2wcpX0W)TA@Qu0@+~k1D#O`p5&UhV>`9h;$
z5icQ<-QyR*!Nxt?9fJ7h1Xu`dIN{;X^&1snUbhF4U32&isqR1BBbe9C;kT#GdDnd=
zUf9#$-Tf>)br11|bph91-PZ*AZ8~VrIF=ffD!&}Szndxy3E-crrQc<#&lS2KiWjCS
zY18V3D*JNtx)=E~fbv_O;8AV!x^=w!p`QuQ6}nzN!@0X(23|@(_7GuqpSeeH-T6yy
z;FN!hxy+vNWvZ|zmLq)MrUnj4m7Xh<_XP0r%UUjQh+UXj?@s-hQ26rOQsJE*TpUQ$
z9RsEP`DumEopS#vUJ$CJ)zE7JV@Z%}IvXI{FLUjZ14!0F!uR~K-l@P7|*Uz-3(r#bW2@qFMNzm!ZBaan;w
z77GfczbRNv)XIAn@u2qkf1u>;6jMtW)kLxBU|bfX+WsG<+V)dam-SLDS4j%h3;f;J
z{;pCy`!*h%N@tcB7Vb2+Efj`mnQ@l348kgBCA@hw6e=jOxqa_fPWrU|*{3|52*ze~Rj|TX?NdO%j57KQS61;eC0%
z@;}GxALldVd8M$Yf@FDR@4TnXB$!2r;(s^i_0AxW>Xm(@`aejsus8pwI9(ODvX4}+
zWb%>!KadY)-aCYrv)OvZe~#0bt$&K@ie9Sas)7|n^?y6>9R!_#iZytJyvN4TjQ{^&
z-Ybh+**ot^D}3{w?SCTGeI%qI<3Gpi|5mE8nnSm!D#-Ayi|8-D#3Z(dczxo@1~-Ortar|Lq6{0eFwZdh*k^?jUM^95fxsKig+
zd5IHtnC_v7AM#=?M&L
z(FT^Z_z8m~-U15bp#^KQLrMR3Up<8q+*y~<(G$2!5-i&5oDiWyoHlgsKwS>$)vkc6
zJ)S`9C>MUe-Vy)}+aDVCV2=hGwjY-O{kpCDZs_yC-eXP=
z;j=@RY_YTp9CUigB4F3o0F7ODOf)|@QTTfEhnurkU)e0CW2ff2**01j(hoW+ZZ$we
z%jymR{>$iwHNp-pCl6~_6F4YOtJRqE3pgSCGAD#A;^Yt;H$vy`TFaZ)Jk6V*9>>oV
z&1)WmtrUwhmsXtP6!|k^;Hd(mIWvZD-h6uV3az_66ZXnX^uo{gJ&_)TE)%+FNK}uoLpQ7Saoz~0`5~t+43(~AUNTjaC{t5?IEkt~zg@5QJ>P?feV4V57^w@0hiKqkp>N{%V)(m5@qHEXi=FF6O)r~1aQ24T
zD^kBqoi^p&DWe{wvt4wHEo@q5RaZ7ddOCW%%FfS`7VHbr-WZ<%3$#)3fnaA!ih{=-
z@ob2EoM*!B5cZDdWoH`1_Mm5#Ju%Y}X@O87{ePT&dt6l2+W#K*%xste!A2N0tdS8=
zG7p7`$Cq@l8AkCEnfI{3Impp6^%R*UM{pQM91v>MvC<+bLKJ{@*8ojL2mX!@+pbdM!B+}k6V+P
zkr})Y5pD1rY4mU_&J2F^O>MC&tn8VE>&nif&FoltT?h5Sx4okw%dr5Kvo#4_rgifB
z%xE$DP5b4Uu&rpw!rT#Z?!reojDFWEc+Du{?I4y>*bU_5C}Uk6
zSFda@e28KTMBPv%!#mgGNj^MV=Y+q=6!c(Z
zW>>J0RY8zB!D2sMu8p`9^kQ;s^8m!qHYy-lx(P1;_C>q^oZ}k{-x0gqsGyi6D+>Ci
z&w&>4J=iQsmC$u!9z&WUF#3&zfgJr7Omeuq;3%5NMEieddnVEJr%<$>lti?G{qaClOI^2vIYxl=B%@
zETkeO>`b|6H*Q^R4@qENTX$Lhtw&ymo;%vted}rNA1i01nITU))D+wgv6jHIrAEF3nt5IhqzavqGEp@GShTQCG4*^d72$?8yxPbV#wC^_~+L<*Qxfg(G
zKH8nlz;IVKw9yMlwkjvR_O9lv&x=`?L=o;1+szSr?$v5Kr}DPC0vOXwe)IpUmiad1
zh=K*JaV5pjz}N%}5oxwx`V{pQ!q6<>YPPV0wtp*nC-Hf_r;G5r`D?OP7z(eWaH*Ns
z!Io*_C@t3ehSz?UT_8UB$TKme(_v6_4!6+m5_F!`)>mF+F+V$8CG6qtV{OJ$c)a2c2%&h3KBVwC{Lr
zY+3Q2D32`Gg}F3+*O?7phce9w0h`o&wloSU>nB?p%~+{|X5qWE-14P}TW4mJ3n}C2
zh5r;%%_rl<6nAn?ImOHK+W7R?_sHvsXWR4?>`oZ+8mIvGQ>YkFCYc3iy~pV(wDL%7eg{Iaqd<
zi?^=8Q583hEG%|4D{vzF^SB(zZB`mf^}zXx>u8VY0N>75!Y$5Uh`bWN0y5K<9X3!E
zf5M#jXThB*U}x1YRuLp|yg|0zc~t|70q=Y1OdMuF^aB1gM7+S!l%tYqSh5nP6VhE=
z0bfliUkZ{hoR03|;zuZlN;MINAt#G$h?P?(K~E}4|)TqC&@L>Qt7A{A!~;G?P2YMd#8-46U#QexFvybtqkS*&LjL$%2+@htpT
z_M()9{JxmgS$OABH)X%KKf&wy0Qwup*P#9wX3(-?c%H)yql*lufH0hP&Dvri9kU#s&gocb@%vGnUa-XEzrNPMLau~w
zK@*eifZy0P_ybh*o1c5cBCMyS*j-$g!Il;fmmR^olRO
z1lj5EzZIlr6fQo`eiSfYXs7z^tFUy7UZ#97AmysJ?RVV8K}#{0RNAe0m#%otV}~Cj
z9}(@&vnlTA7t+Q2cX*q(ly7zJEUh7C-bcEtxna2_Vk_aB-Nj|kN)lihTi0jaG{pxo{K3;JuezD>74pD=On#E8U=iSkK5
zKQ%x3Sn~LJyXQq%>hQ6IIEfOk+XpuNGi}Y|p%o
zOy{4M%{(@@ZvNo~wSAwvzS5~^IUoOQ*qMk^i6^GkKYe7;LHW69$Dc=})$EDcdX*Gb
zo>*^ten%kAo0iUjnfE%CjFgQG@QqQdM=T0Ija|JKJ_c4v%yI|$g=;!}&5;GESOKzK
z3=(V#J7KT)bt+l!A#x6Eed)U(^*hjcA=O@Z?L68VXnxSU4u;&HunuLjZ65`s{3Jq9
zW(B-vnIj5Pf3k*I$<9wZ{A|k9++(@5Vu|hR+{H_0m>w&W9Lurzyt$QX0)To<~>t}kRn6voV+uNB9#?F4G
ztaiCffgR5_s&CyW$yFgvs(0>9Ie?czz?dfLPybpmqS>+F70E9|bHg`yKl`9w9Fy!7
z8dKT$Jx*%-1EWRSxW4^XNiIJEeuQ`*sklt{bJG0jtp68|TEtCo3
zZEc~M#;t_*y*bjFs*+n%TMIi+!)9(i`=AllsTRfU_%a-`^oGlX5t1J4N%#&1zM|;1jRCb}fbR%O|Fc)lZ
zHtB5Z+s4;h@PX>y%GlOl8Q=6dAhgPxzfsJ;JidAl(J!J_i%#^WUr(Q#e`dj{
z=j-!~QMO%cA1*NYwhlGb%A$w@v84&Ac2Da#;BCc8!CH7n8|*gSMRku5W{6mT7^y)T
zvegVEdh&bNf%0Dqm;pOu2}8JH2X0*R;zpE!8%|Kf`xL6Viuf2sBKtPiIiS)?-XpQ0
zSzVhBNc4G=?EcIJ<(nRjo$Kf#3OM#ixphZ;jNd$oYTh87$?w(Rm{N!2iyYhfAIC>n
zOt_qMP7gl~NLn*P9LiU>iJ$hOI&Nys-{n-FLUc(re>
z)im7?F;e_=Y$-RROr1-^T)mS?wftj+xLCa_?#GNj!#d|%Jm+N=`VV=F(lw8
zqEhuDo$5`cW?D8T5|s+8_
zUFGTO%<0U}D6~7O7-!omhVF5I=qh;ZGcl3mrKucnnTO_-&%-Jb_;yQrwQCrK7|Acr
zUt6-av46m&4NkFL^&tkhBeoX{&J57TinJn1t5o;K9`QDr>I@O$0@xk3-MxEDx2E7#
z3-E9MD2IRVEV@-%FGuC>aS_*l@o49AyVbQ|H}ALkgweFpqlg7A;yelvZcQG4DiMhi
z#9!m?y^lORPbT<37K@v#>0+Dz$T^!QR=#O-8biM;j5`_nm;k5hQTdZ_rwUzCd|`pv
zHTcY)uc*I6zX~I8{rGi*kXrs@^|zLEmDTu$$^Wu1{F&c0`L-bjCyl|1sEvp?lH2A6
zR2jY{U(2@seWZsorC055Y(-U?e`hMk3yOg|Qs^T$q=!
zZUYbD4PVjhTyL0snxu$n_?D?pt7tb(5QbC-;{|oXc(Zv3UHMh`y4EGM6M3rXG>!i2
zt|q5yhxCm?v@
zF~>|qP%pWB$-iJ;kTCT|SJHP06QAFW1toswdwlq(8n~8|z^-
z{e>DOmk*+bFJFpJbAEh!*X1hIPT|u#DD4u`C6uS*A&v*_?lWi|KrOC(9;mHJkmxXUCQSN^7$WK{^I77e5&~J7yE=+e|Wh9
z^}_hvck#P0pIw)~Fhi!N#$E#UeIZ!3(-#{V`Ogzy3MrTKM1zn@|Lnw3F>l|d(_)?z
zlz?x6jcneh#XVHa->1b*mHIQ6EZ9RZ>?hVR?$IK`uu#gl8?q8H?fM65r-=FgfGk8z
zyUK{xi1}r>Ba3P4C;MDNZZnnE2;H&ab-KGh5p%YTfXhKS`q#yG`vhEe
zvd9Y#l0M$Y0J*;KgX;e|BHr-ccc@*Z?P&+~+r1@me){yJ5phRof%j48`E_3>FU4vl
zuSDYC@l75cINJ~_8m9@LDKn>|cS1BH)>4ASGew
ze6r_SQZ{BWAMLf^*r2Q*zg-72`XUa}v8fh$!-p5@jh_?TM#ST1C5Nf#HqPY&Tcmjj?Yzs`;C?B@U{|o|Cjc_7r>=q
zORR$tO|bI%ipA@oDXD;tYA5Bow8}xvQm0G`9o;kuvT!qEA^5f6{vCuE6}~aHEfQemIJ?>geN%#jB2?HzYz*;`
zB%1&hh6(pq;x4^6Oj1P+CMTwZQ%FpX9wYBmGY5W7<(1sK@_#jvxUB;YgGBS39#(DkYBX`;Z~J7
z5V0D^(R^qQf+m;lYI4ucHo9>@i(y@KAnRa*9Wu-vo-8;7bPX-
z=_T(|i4TmOp^bezZWrj)pd~8#<!
z>(-Ii);$b~>L%oEGTLSBEabB6o3Lm0<^ji0(zdroUn}NrHd327KPs`u+0Kx5*gabj
z-}1Vs*Vu|zBMCa8s%_vZl@{QQi3B(9-D{P5x;I4kgFLg6$9si4E9nUq)P*FG
zGQ$j%x)g@{cvxrXvX%T^<~`!1VJmuhH%8LgFH$Pu^uObL)vEkE0`V>-Mg9^g-+!Z6
z(CxwJJo#{(UZ5kMz5*SQ`eO86k6*}a+!w}GZ_?RUAO_MvnI!JXsJtDB(8RS+1mC!C
zF#QX{wEi7HNL-cCg$M5SYYsiX2Tpn>;E-K5nd-WDH*V9op
zC=~I8FRa?PNmu!beeJElxF=Pwv<8ML=v<;vd*{N8Q{8JJ`%KKofnU-kG-G~F86-=S
zy^8&)#+(M^F=THM_c%t&|FZp+?zZ@OkxY`0a}0Q(|9<>f`I3eeag(~s^7AV1a7bdF
zeGBvY3&xt%x2J6N@;GDpE!f*o+=L-U84raHw0tEG--y3Zw6qU!_q*f?q_s^x`1>(f
zDLR*0k5fbX-aTfcl#$n%@bIF;NH<4E-$QO8#q~86L3V)KgUP}57xJ0|QSv^A0VS)0
z1Ir&NW1M)?r(9O1gEyZr_vf*HWz_1PW}(h<|F6GtSa}`-PsKURVon|v+H79PxACCo
zXK@Zs@ZZ|*ZzKOb%+o^e9dcRJOCCRih5LmXR$-LGJwJ)xiF}PP@3#xlx^XU0Gzs*FJa7_&1F=tNL?VrB8ow@S`qmwVW1OE)~Wa>G`+t?V7~*^q}Xm
z@NImQ|JHgg(^zMHMEz*rmYk{n+=&;N&~nn8&&8V0h-17Yd|QQ88tVC8Y-u$A`v}hk
zz9mb~h-d6^@T1~>eAkN)KWq?3+I;ohW*WK0i*Z*!XjB8YSi_7f6o-v)i=v@r;+5f8
ztUdPJ`$%Dxkb>?i7LY)y7%4yksVt<#x1{LaL9wQK$C;w|t8-60T|d7&)>I<+mLOg`
z7Rx1pR%oMcAsSs_fjKgf!RdEYxP55DaCSr}e9VywR=_>WP^VJL@NqGQ-s1CDyh{2j
zx{q`n5$+>e{NgUs%)pH#tKx6w$Xcys5$U%Cy~8bV&5E#aLu^ME$v$u=5pqb|wSA&+
zg5o3;b5(wfuU*OndCz((TdU>yw9ww|31_{~l5jimrs;NaE6jZ%a2sk$0@CTuL3HUB
zIG45jNzdOvhTOtEB~dO)mcnkyF-k6$k1AjLI-g^7mhCd&B|Nhra$zZP1?c76@`nGC-rMJv)+&hH5E=&_uY
z)@2Bvi?*2igk0tVpDV9?HWqrL%z>Tvf@jAa26~27!wfOYt+>NnB5r6fxQ;A%my1y?
z=!?e2-*~jKoRnG@DW#X*3F{%;8+%ql`1Y;ND9;%ZZz}L(RC5L}m3Wi5
zMP{lgWjhDdu5Wbs-M*SDN$|E-eG>f*6Z^i$U6eI+Kyf4EcYA|zY(-@{X>L2!8z!n0
zxKRLSC6jq<95D6(BBBL3Ud4HD`|y|=|5eHdj!T%h*_CgVH(MofCujzuW*u;-O1;O(
z7ixUOy;)CSVfD
zL;HIXA{Jl#KB%!O`A_8$b0zkg5N2ksGUU{F+ki8O+#>U@G&c6@Xj`2iGnQLN#Wz};
zhn8DU>Ke_>Lw)qZ%$qoMA}FQe>VmE4OV^)`P%z+yuiKa3U}h(DhJ4RaoR#DnKZCpO
znQH=UoKk{K@I*Ue$v{VwmCeJZvmapN?}g0|xMK=1afmR19f61^e*_T$9@abHp*qdO
zqYot5{F;Y@CdCn5IoKZ@aPQ-0Z#}P
zIO#+@d7#V-3om~BUtr<*PgrEtWqM(ew$q)}vhr?NbmPZmcUI7=jkSvc?t%sIV|U)2
z_`$Sx^!iH
zLZv}G3y-<8md=B&ZfVe~wEA9|k9Ut@_Pm^oq)NPWk3V^^v%B@9Ju)SB7-UNP&azlY
zKUa&@E}Nws=9l8-_+^MiR5TOscY@DFT#{Vh$0k39vljA?&P>a
zihtIvQ$@N{Ob^7&`9N2jJGgt?;kCfmC+yZ=yT(@7xnH~b>fhCq-NV=e5@vM*8#zT@
zuH3A%7;SGYk0)K!0}>}JV|bgwuueo@#eAP5i-w3Qf%?SaJQQpmUQe)O@sdX=(ICOv
z0rTZ)P><~c`vB}7(ulvVe#x%*An+9C+A=};fHDO;iqAJJcW2c>CQy*-SWa9$_cGa_
zkfcOA{91}TC}y0Pznr&0(b@aEQyN2Kp88OC%9?0Bmpi|kUNwF0&We6)rp2AI?Ufw`
zD%ppD?iBVF)8svADo%IJG~tK8gc;44G3dGSM<&x)J}Mpldky1#U_)b9Kfp_6I_2)A
zEy<#thoH3-=iB=f73SxqE4(ffiS>ex-jDx{M;#D29!5^s7th->NVf+^08HDZzRpw{Onfa
zjgK
zDtXo~cA4&)i0_{O-$#&+DDQb!m(9Bs^`;$ExT5
zSZ2?WoKxWpFEC~f7*j)VX+_+~Ut+#TqwC~q!>jT!I>0<8%CPgSyKnuq4
zgk;?%_!yVNhS6~wxHBgRK*O)$$kKA`4RfmTd1dJDpnhJ
zr+_JYgJokplvS~r&L=Jv)U=&CUwcR
z!3}cTC|R5~q(RPZluCvfqt?VET=v;&dEWYcu1F_V%cR%+4@uownv6qu3I2w^x%4o@
z?(~;j{M5%-9(#qcyVQ(Q-L4x`fmfh@{f)dU$a9M296~vF{RajCk7O&{Sy@YlO@8ek
zJ`?Nn7F3*CyQHP?(&~u|*3Pe}&qw+g<i5ZTLfuPP?I5
zuHDG-^Z39hnGloE=0hdz_{|O-mC)Pv4DW1oe?4Suy!Xb>#M`*bKK^&|0U3$dwEId2;u$?ZW5=oz#R!WbP}sqf=>HShF*r=`V}~(TVa4&nBzs9(K&x%?Mfy{
z)b(htg3qeeO7z0X{=rwh+jmUHX`jDy6MBGl(si^IEDJb$|a?{`jQ=0NXPi+z_k7bQ$mibj
zrS=MpWK+yYq2)qbMDfNPfNl6~qI95luu1+ynno7ue@xRN{}(hZ^8ZNFBL8r`x^S(P1DZh3MZankW9Lar)d|s?M4%G13U0AV}5{Wnwi?|p)mQ)eYW9`r!ZTZ
z`)J?h_*Q?P!dTSawlzN6A(Odr%UxFZJyDrIq%d{+dE1c|?DOPTPMuB`cSN27L)PTY~BW?|7^!dUjJuswy%QcVkFZa
zb|`42h_r<`b*x>5-CDqqyET>5JI1n&V-hkYS(07ZI=G&=*?j)xv+Z
zR>>iKBJ5CBCY3iwN>xjNpmjft+y^{T2l{~b%W<5aWXVEu
zh?wQ1Dc26ULvsAgW_%aBE|j`&~5>$(+hg2o-TxthX8>Tv?s
z!Ry-5#ABe?!?4+5Dn+_;>rNG6=IWE}2a7TLU
zFA)d+)y=Ty02du%E_K1j2z&(e)3gJ5K2PK*Z=`I72N7--I#@dJrR=hsU9aJdR^S5e
z@355xT!_2atc#UF9@D3_i%Pyc8`d*fB>h7l=ZW`6th(Wwn{znTB_g0B`Gdfs(rf;zI}0PG$$<~bbW<-FLZA{jQ>$eh9Hx}@QZ
zF4oZkpI=X4>sx0kv?WrX&9l`rc)8QxDi@JvZS#rEvk7<93z6$L>@ab3E&h|jRxim*v`H~&J6jgrkk16Uj~giTHw=kZx+(x8I8Jl6NBD`^Cy45@~gA(`}6?njV~+wKJv_Dl`PAj
zVqBj&jPfxO<_*0nfbn(u2QijJoIeWt^3FgNUfltXLMn_i1?@&Zgk7fKWuy@|6r}H{
zf+YgUwBeBfI#H##YO&9gOE3rg{(Nqt1@f*y(+`hwrdR$cDR;cdjNPJqG$5|CU*kLa
zb~`tyi#R$J7u3hJ)FZ#@m1BL1_4daY{44)LbD)^!TFoWoZ&J^eg0{
z8o+{R6v1LRKmUk;{nT4bK&OuSi{DRcPphDk4q}ueg%|fK35p7uBihsA^+Dd&98ze8
zpJ54E!MGH5xl3`K_j{ld7vGA(Y^C|pw>BNn_P_3Ha=27c-VUsbJ0B(3IN#()2
zuy|VzxBB8sd=Iuyxj4XY5cT419q_{!-3OpAqV+DRQdF8he^Xm>T%j$x#hB7Mm^?*e
z$lPDmT41P_^;jn0B`jYFyF%p`FlVX+Z&#_d*%JP})y}CIf~4{hF3!}smr<5t426~)-rQQSZcBmbrd)&%2LH(@u`y{o%zcKKbM_K5mH)ChR+0_|KT0u(ZX%`uBL
zH@FzWj@KqZs}e_2CMprYKtAbXb2;>oGWxqyQeF|-vWFm+8$4Am7J|kWpG6z)l;W4+
zC8Mwy%N@%lF|rO&;0Ve04&{ahUFW?~`HdSUby9DF3@lc1ah=cy)nqcvrBisEd!xA>
zG8?OeWIJOwLpsH%UhW7ivDn_6i4h`RlgLSj=g_HDPLz7%EyfWGe$pEGw(^W43~y#l
zvq--)Hac#!xa*E?>RwC#l?uuGm0WbAh^ym&GjS5M`uE
zf@n6CnfDRDGp9hMmV+y!C@_39hmcJ=yg?NroZ#E$~aUEED$nNgJ?t8j9XnM6=bzX+!yvAg}uuzC(aDA4{nD|XMK7G_K#pi
ztXhuNk@i|h;r#lcr@gOFgOaaK+wU8{8kRS!v&j3VdEwX%e%ap`V@gXI<%Z_*gJllz
z0_M`@zbO$Bhn<0#?2lOD{&K1Pji@yR0__xPb1jgx14hWa4d~
zL-)`bs%kJ|m57o8o}gfWl@j-h7Th+RYH2&lkcTp9IH9c|n2Rw_o_NV_Y3ouoSP_9>
z40I9K3zxk#4}M;4tL$ngA{O+8MYTMO>UDOVEX)j1Ib3`zEPg{Ph?T;E(mNH9W)8H^
zvO@NWU4)n8N!NijXraA_a-jX7z5eK(aNM6_7$9B2Yed3`_DcPS8HP=yF?P=aG&y;C
z!9=2rz?NU>Wp>%KB=P?m{t?NO)pNloDWb-!lSwN0++#RH<>W(kK^6b)Vyqbr$sBS0QSZRj1XVfQ48
z*C4bgd)Sb=B&B6J?Uxg?M7TXn@pw)&oOn!#i*w@36OSWDe&Xnol%xzvUwQ|U-hiA|
zB|jq5+oi2t>VZW6*DiC+fs{7S@1aL0N*HBL4r5cVg^YeGXu0+s*KNG{wyZIDNLTOI
zdSsy5B+2;QHWvwPP8{)jZAL%$+ieP`OlGh{P1J~6psXt0DyGwwuF|a+jRW$PL!@!0
zBUXPqSJ7#je8X2I*Y&eoDqB^MQ@C~C{%K)?-6FZ6vc&)F*8MW#p@j0ZDxY_aF$q;Z
zrZY~3O#V%xd!zQX24;jq
z+29z{7}9#%ZjJxho-6r)n%fE?RC?jKX4=VRp!vSYRlk6)nZ7BB^zdF7A5{JWH5oDgA1W
zaJ^FNxGucb%=43Y7wVPXnD%<2&m_XOM60(y%V6|3!P{TsK+nxPA^UA0t^UFUasB()
zXWfXm*EdUIxZ_NLEx~d;<`dFA00<45I-k=dg|w}
z72$c)?NY4w7(RbuygnYD;=}_do?s8Xd-nMndq8^^#SDlzb+_l5%F`LR$7uSoS?(By
zwfbP;E%OFHmaXxV2>75FA?)-WBeg}JFFo|7Wy=M9cU&gHxBZ>_73x{GiyDzbe1-B-$HJ@o3&Xswx;J
zvF9I>Nc8r+g+AFvyDj^)`YF&07EwJ7UtVYZr%u(=l7Olz3Z)gFfZ
zc}m$}#XGR{ZlpifPW9rAz^&HC1(!O^MvR?iHIN%F%xcJe1r47XO?}$?Skje_&t>pH
z-Z<7la)dFt=Ar(0?aDWZ`ZhNx8PoHgKH0`$#kQJXx0=%NIxt5!oW?8aE*87Uwqd{DK1;gJdL)%axp3wqK|fj#_0R@7pB7JBY!L>>rd;dW~db!$2Czmi=^22s5-fJW`cI4Jmrh92>uE>cA*wJ8uYWNP4%iz9EF#2-vT(
zc;G>e86PYOQ-1m3R$EP5n6moUtuej}bmi8N_;M@9#>moiA~am3J~fVRn7r0-54F;|
zr?Wq;u+62`Ug6UcKAriw(7NQ*6epc^i3jbt&#Lm?JuAGSC%m6Gw?fN&KyseIM~tR4
zk3a1O#8*0Ge$S7=ZI?e2Kcpyk3I});oRgK0CJOY<26{KMhu--#2J5?e*RplO(?+bN
zKrJtwytCegzf(Qd;0N37{dUsJ$&8K=;A6q%8?2>432)Lb=j-|Nv>}qc^Mnxa7S{WO
zzZULic0=}AoEk0TDt_xUyp!@qt%Wvq0L}GKiyE{X{$$M?^vZ;_4Bg1-W{z7q?uU))
z^|yPsM(66BWwmu`z=<8^=iGX{=tiRy==BqF4D{Q95u=
z*mK^yD)4t#FKn2oOvpnI)6hc>-@}FH8`UGb%#IwUNOxREHZwAP<+Bghj5??tc%7-#
z`%Mu?*{sHBVHvfzRG(=e(@7=ZO#lxvE
z!$50|r!U>2JncJ<+m(j-7TmW@@y1HyJg1PG-c>nc0djTo<7b_-#_z{DDxQW-_3o4l
zDdu4BclZf>KNH)ZWXirTn`dQ9*x+|1=HN;Rq-q^_=b3!eR;kv>JM4vButOM#IGGp0
zzj`E2ioS~bs>+PJZ5PYTE7&bFt0g{&^$ER;6ds*T5_(6}*{1`Znu&;tN-<6AC4wbR
ztc)2q1vK;u?x!>PS3M8DY>u4pDmydY#~hOC!>Y4=z~6UJjMjPU-jtiw@A{OlYJ;2s
zF*q-`Ngn3dkV+re<={5ZESUitD0=^sZoy=^l#A3XW+8urxcQ1*o+??%WE&(2tb+r$
zW17VI5OpJ5#rbe(!y#>uiy2h2Hz{KJ#_94oZ4(zH)+Z)R+B+#?^2W*XDL>Ck1BNxu
za&?T!wHO-TZo75TX;xPvKI}!rAC({$>|lvGBwn(^vCFaBvDdL7q1@HrqYd&fna+93
zYAdFmn|5aADZzK5x4(plulZ&*s9b`V%I(-MP`Sh!lCbeqE-%|)3X+c%&(!_=-rB)^
z!T*0>{J)X=0_*)4Pdj+5%=@RQkn5wg|5+wyZNu5PVN+th-U+!06myg9Ih7}s>pfDZ
zdbJY#Hv`#i8nNe0-x3LWYOt#Uqyoq`DJzGsDDA9M_l*oD8)R2FlX)PCKvN;)*
zHT5iOZYxiLY-_89w1{jB!
zw_yw$63Li1j>n1`nesJ%)e+_etRvY@=8F~+YoCvGPG?lo8?4>Tc9j47CNof8esc{I
zT!84djPw4EF81x!j9G1E5T_V>fg))>ETg!;<(4#Pv8323*bO8FVmp{83Tp9ccCe(}
z>WW9~9*SFBiML4lFyjste9!S(r`GSFeb9#Od)d6+2Yq9t4vaE<&8z%KLyQdj#(2h3
z0BK6cpmijLIaFYVrq8^7K1Q}UpGH-l8xd~~w&E?6)lB@l-H0tryXUgRQuxg}?3Uc^
zkjaH$pQOWz%pO8JrU7wkvAfc5BX;S{SJXK1Rr1_7KC?;;*#`4Qe&@L4^2U4HZWA>?
zIu7ZwFeb9p5A+NuSI5P
zyr=Ev3a9CKzLb4ic^6I)mNbTN=WGdUwe#1^x0bJI&=H2%x-mpn=uWBV%VR}QNBy;O
zQ{sAwgyHwjo7~21qhxBvemh2h;6Qh^Jp;R(15N-pfER2?I^yrKSYz7dpE-h!<*sHQ
zZBZNJ=VaejFh5&2>?etq3Y?76SRbaG+6JEQ>{j4NpPzIweRe@|+PQT@Va(LqK4ad#
zbFL5W|H7g+fa1xT(r9nuJeP0QefpI>V3Vf3kLNG*vrnt?C8zjZH;MSn5C1|m
zymRYT_--ic^TTWjonf|_`C&?9dziAp2L6)q*`({{E}sQ=3C?)l7c^3(>vS0HG#cdx
z`^k$@UPEw!es?_4d9{={YUy%#3^F&s3#=;FGE#=_hALUK529nXJhNN4=SCce%5k@J
zSp~d^n7Da7*#eH9d&Vf9SvlQu!Bd;Z3z1^nNlRbeU^G=*rQo*Cunsw6^6@~IC}*7T
zGY;mqa4JM3-*n*2f&K@Q4{Xr8i;sTdF8WjbRtt?FBKLK@05Qudj3lY-g>Q`14%+jf
zwk$@I(&H1$`7koh348v6J6f~or|f4P3z#>ICSMPzl~78~T-krOoG{{moqT;{t<0_*
z(`&7A+;N0;%Eb7eBO6oUd;2PUKTA=rI;O^Q7bzle1xex&jhW*#h_iTvT5g}E=D-*A
z_56kZKfsgXpzlrG^RMg47jcIrDo1E9Ed%W>fbS6BTQ$Cl(t27aZR>bxEO$S%B7a`~
z>r(p-={VdUDh&A-j$D~VJ@M@i@+9;BgFSPv3q7kme-(P7)fRYm>5x#!x6Re*{%rLu
ze{g&){dH!e(f_qZi;=@RRP?{Z78wB+V^Xj(Ijb-<|UZe
z?|gQMxN0yhNva!TF=mT9#qyLk`}&zBNkxCo^X{Fed7Q~>j$V=!J=!AX8lK{Nk$A?U
z{wTgg0T)OAx8(`{wYlQ=YA#NjB~gfF#yDf)XKdwCDAudf1)pXs_rA%m)yFvt{=D!R
z=JVnEYEmLE9p1iHuGl0&+2!!cwQ@=y-t;!#p0w6SNNcmM
zE4;sJ{X7qoEHS>Xh<`KWHNfvE;y$30z2=0?k5=RHcUrTuEFAF9Uwc0y`*Lb%Z#~dc
zYqK~;YXuj?5ohY;o&zt&1%-a)RIf$K=}1QEeWV<3gu>?_+GkrIkK#L{7VivdHJpz&
z41YuL7lFV2`0L~G-K`_cqKLzpFWR|F3wJr>_5T@rcu|Fo*KccN&~N+vwvW5d6a)C*
zSm1Q>tf<_mylZbIHwd#dOxTqJe7_g=Q@PeRaa(QP$Y8V^B}UWtj?uI}m_>hEb#oY{
z%?_hR+=mIf9QN-#@dbHbY{;{Wc*C7krY5}IH_KUr*DP{#eaQ}J`9(w!A2OqGU&B75
zQ|@cSA
zTz?DiEe#&=Vc}O!ZE|?iu_2~+xDk@X>_oh-Zp7Wr%8kd1Ab88f$f!09VceQ0pP!an
zpX&}XKO_8Z)seS~kT&X~*6vzMJ}o3I?_A-&u-hMU@jJ9l$vTzw%EHgq_e8{q6+NWA
z8r>+H`Vry@w$B75>9%hUJ+aFMcuC1hu7z=g0>=6N$0$mMxx}Bz%V8s=3fsnwKCG)=
zVs_O?>^Li-Z3~X18W!Y0Q(mRCIZAOua50G6gObn#0+Pp|
z2ZRO<8Xvv?+}v}y(=7FtSOrrNbIT}k2fZ-Itx-(}cH;%&%z~IS1ER#gM|1V>91#Bs
zSvF}kBLkd%OiTQ8nFF1$pY9wGt3=G`F(kQ29E_OJNf(xjdX#3XU>%{W>qj{%vJQa_
zA#X9ED^ihWfg(#U7h*>1mh$oSg;MB;^bfk|z8I%+riJt&XMdr&l~@EQRu5EeDP`H2
zUo#XR+MSdI+wdMw!9Vg5lo^PU3qII_?Ux$Z%&JR&8S{o$f8bSja6pKX-Gk}HZDC8w{`9WES8`kEJVY$MlGRzn9hgfK
z*2Ho;-g<1VES9SXTv0F&@w9=bz@`H-CnBJ97EHlg5G89+gJ?P4c~Cmj7i*a&1~ZzW
z&7x@A3|V@D&U4e_`$A9m5Kh|Zc6esdy;Z`PXH`sTb-t1usdukkI>A?=RK(MQ8Bx+q|B3NYyLm@G2AZ
z-lpl(XHQp-YJ+{*<Wyu#~xMApwxj!H;HeX)$CKXF?r|6|@>DQZ8P
z2H<;4Z{3>why(WtNG&rr>x7oK_jmY_od1JY^NkX{An{u`5a+=tZwXod@AT$s7r49P
zM_^0j$n#-q8YJc#mt?C2lA%DE6jls@u;EH7j)ARCFR38O1XnDJI5xA^DXke|Srm4h
zq7=?WUND5#m(Rn1P&BE
z!oSbkqXj*t{hxX?FmxtrW!9Cwdkkk*IB8zA3(VoxpfEkn2yYMgVz>F4OF8rpESg93
z2|IKittsAP2omt4sf)0R2{|~PupaQ566>rO0&f0)0IyY$(PYiT>m{XQ1Wt!9(=u)!
zUU1+gLzYget+|KKzYzGQldBmbGoEm5dQAA;&;hNoWYd>adr4ApAa0EEHoh-MFmS>m
z+fVo5Q917DZBdU_PtZBgs@<}^3*W;Y{o4E8#Nc~q{2}jmxDUP~r&M~s(^z~*%;^3d
zy0PeO;U-q*?=4X+b4Qzpz*o}WyB6-H&wMG2QRZ-IoCXYM1aqyh$u##Fju2Luw
zjuIDGZwc8=cl4L{Khh2x;HCGA+7!emNUD%{ON67uwm}bGhu!beu73$_qc;-EpC3h;
zReR~&@RkF#b#*TbU$Ukpx}cW%bk_F%B^^
z;S&doaV`?}t<6aX$2<5Hscxk;G6eoCdskJ9H$
z&WQ0R1?o+)QmBT|Leo{Or}V*2g5$XNgtJwEi{TtWY3Tyts|iplOOy1KAMvU3sR6Wn
z+N3I2wVS?kF?5c+5W12X&3up$l?xd++WPp{hZDAny4bWUZe2^N&`$Ud;Ez&&*3sE0
zdxs&LW6QF?+pp_9qJ2_})WkpnFo?f#N%2vbLqHd}=Tp9*W
zI!vtZ!3#5sm7_`)V!TuI(^WD(3+wmoQMvZkevG$_TbDEmzewN{{2p$@{5+blFIpz5
zWL3!Bztx*7yNU5km^__m>dX2;YvCO-1h2DDU2V0lob>C9G+s$YTA
zGEHdN(vJT0-f@!G3g(@Pc}Ls!ZX7CTsHO7z;4ynw8>`&EV7Tpz8olc89#$EXKHN6irB~fVdJocjTzci+$a%KC
z5%b8t5H^JwTBcpHjkzMxN={0)Nlr3apF@&uJ_{KwJ3z9Hy~1dvev)m{4;ZcNQ)Zj&
z5Tlj1GtejUdb#{IK`S@eDoghus^a#=%Dv%F;FY5^z-M^Tgu{ABU1K9cZKHBWf~#7k9CbMv>m7xN
z1iGTA#{T+WS<6X<`Y)KZH0PFE!zzP-pY9-59<`RWTv6;=>(+efC**x8-IW_Q-Msyf
z!fP)zev)7-HO*RYou7CtF)EiLY>Rl+0?R2~(vTI)66`n=^8rHtP_xEep`izQSzFZf6Ae9sW^-U!w@W
zMge}4eiY&NK;J|GdeQgVs`D7TR4Rd1QkOK)*6$6u2tnuF5M0_{gdm_s&_j7OL9QjF
zaUdWk^Fr>@W!y8D^H5@5_!}T+;2{?j^OBGkvy6va`2P-ahO-2@GSC~6IM5j*uQ~Bl
ze1=`#+O_GlwuJM+OHA-t>I}}n8%*>n6W(`&<|g|kx;ss15wri2rr;pKM&IwH3G#
ztXMY%tra~*w}Tby@V*=Wg|-mYi+p|=3FXkp82EGvW6F4I)9HOiRr+!UvJw2ZO7^+R
zjPybrc&ekS1@fRWe6Ls+fY!=f#D$@qPO&`}KE&_2z>{%ds`S|Vz!!!IX?Q93qY71Q(h+#U-3-(p^CBPgDA%`YugLol`
zlTGq12J$VjCcnDK@ey(|`#VD_x&$A|(fZDiZ}ha@qpL>iV+X*76>Y(r4>7FCi^p>m
z+({69lNTTP`I!YzEvz{&&44bS{Iys_g{2n`jfg~d$rln9Kj1}{Dgiby@bIQ6M#u|;
zw+ti^lPBZV*`{jA-gtdP;(Nk(c1*^0qzy>>&n|D>fVo>F{)noe_sb;tjxQUbC+I<%
zu>ziAcsnbqir|Yqg?*&C6egx22ll41kC2AnVoK*aC*%>ZEFN+^#f&B6&;QENuQ%z}pXgWLo?oq~8_QhG_*}Ml-RpAH
zdCyxXlIq;1I+v-APj{V!S19%1qR8Qk
z3%`)Rn|5s-f1V*iIh9|}u-to$y;XJ-(gqH%&g^QKkF(DNEB3%JE@K_9(P`nm6wns^
z!g8O$Qau|tbhBPB5#Hxp1&ek;>tpvwZ+_6|+*^TDPab48PM5^iR}6uy@Fsl6ig5>z
ztbue4Ixw8=-;?w;qAiO~LI>7ByPDf2+*wrey6M7AHEp=4-+9p;T|6$$3I4rL8~Aqq
z<{M<6yIbd=yLn;hYLZkrWRSU3hnvMZ8B25*?ne#3HXm<|7X)1)Q@Yx|yfx6zXxh-s
z2zTt=x|l~=7`iV%bHUO2E83}ECA72sZ%cG3_ukpgFVhHXwsEB^f4`koXN7k5h}ymF
zOE8|0J7@61RLp={vX;KY&w%gwk(Y#?WzR3sRj9gUEAy%_4@AwH6o7kDlP^XO4V9^n
zMJh4yZRBu&b0@vCoxhRtx>d{b#Mu@HQjRc|jHTk77Sbe9dB)g(Y&7>Q*8UtUHy6Q2(GYFwr|OtzvRo+4RO9QgumaY>xF^mY@K&hl|WT7n%J
z$Ir?VZW7uuq$neD%4%_L91qMR-5s
zj;>qTGZ(`%_%*uhRcZ}w1++~2i|4A
z*hwR>lOkNE*Q^&azTiLw)=}&lyb&@#d6q)f7n-Jd1rr(s+@n*7_9N}#CZ1p1vLFLA<$c#~cnpifXU6X9E$H#-b50D+HBHujI|`eQ33vOy0!BR|JW&fy)e
zo`sgUQr%E`!(`mp8t@UR1qQ%>_Sl1zwmFy28(Zs$1yroYuCa%cea9XV^(0S@tqb)X
zdrZ`SJURCGN@i?5Y$Te&3#1-{u2Ohg>KycJS%RJ|>PE^jBmGJ~`8zn`7Qv0^aJJ(Y
z%0FPF(|$MS_0y+(8imTkRqQs>2!*mlsp-u&((B6Wg}F%avJK6p`5|9l+>}R-1^t)$
z<{40n9a|&JAl+x|!8p7dDtx&lV-I7@M_{vYhDF(}M(^tbuPx~HsxqR~Q%e{_2R{bl
z8Ik9e*Yt)b-UQ*tkUpUYp3;;acuG_5falda;5qgVc#iFc=P`^8aQh8-B7OwHQwjZ;_L_X${atAz-*BhRKc3gn!%d_n{5~TxkvRl)kHL_-Gs(5)eyNhGkZAQlY
zzLjC$cQLBGcqJ@)XTY+7pS^XI!lKo*GrRNtRx$8ELe=;h*mBURXls|gJlh*TgQz;_
zyBOsHyc&b(7yqG~MZB&EKPF$K0O1efJPz;CE09F3_wQ*B;CJnvzgyB*EVEl9H;%26
z*Yk2iu1zZ7to1<=8+grj`h&vgBg1@s#~#iz2$*sHGd8%AG0(_m+;!)F6;2=ndI=h|
zJBfN1a<+$Kzuqh4tXO6-3SNa{A*VD2dV4D!-n%#J@Ue%*y2GibhjaEqep{w4!HcTG
zI7-!d247$7r`@c9dcVJcHB{pNJO7Wfw*haW%KpdiWHOny0ooEusDhNHEibExtx#dH
zq>yB25kv(m3M(*{s=JD)=(4*kElC#iXma3)y&zVVRVcq?IpWnk%CUfV$oO|xQ=bm%!Ip@}@{p)C5Fae$(9jP4YNcRKZ
z-Qc63_U$*JzQs7L16anvsVoCy()TT1$V81#u2La!4#a*D9ny>{bT>H(`0S>pP~3A(
zjpmT%2x=Caqtu%Hcd7GKeJi^w<1A>xx$rl&RZ%Rm4v5M49JJ$0^k+-3YW6oLrGXcC
zk>dtL?EbFY1>0ne{)Dj?tctH=jp^oa`r2j|tg2j*YNb;lM7wDV;T|wf6!w^B0QYts
z#}Q}2_wRpbV}Ptk46q_m>+xStwGJvavD&D8z7U@K0Kc4CQf(17gSBd#Q!16xBH5sL
z&QMwd%1?pa@~`#Tbw}quHw@_9XV)E}J~wyn^MWEpRmcU50(<4w
zJ~zBeeQrUYYxOtvS?uU@eXrn<=`a5GKBKf)3m=`%eI^})W`9V>&V|QWiUzI1JPnPr
zDdWUQ7N-4Dbg0ku=yODvZjEvUtAdBS{*Wr!#R7Jh-xP6~mEzA7i6{O{QI{F!ch!@P
z80V{MPjmYM-n=UliMH>u@hC@ppuMbrdC`w6ZKe$(;w^|>Oa)>W_z5g)i25`SVQCcS&=|gmJ_!kW-+x`bD$*r)R<
zE$dBd5Gz%oYtm_2sqk!WO_lh#Fl>1xrAr&4f>jGPh5B$?a7e-vovA}Lpkp`zpcQ*d
zyWPU=y5c&w+dr;zyZ#T=cB8MPN+Eo#Q`$W7;Aw&*c;fEGYTL?qKhn8vE7~?ctfowx
zv+1Bgo4>EHCUJk_!Ni)xLy5GOyEVtCqblBh(|&YY#tDpgXn&V(%Q%G*KcnXCe_O^`
zz!YBR@hX1&r!qcYZS5U_Ie>M3cf(2PE=m4^%&=9#%jZ
z2Se*5qVuS_LL7=~pWB-8QAEUF82SHY9K(78HNN{4@xoXw&>o~i+nRztH*WwxJst9L
zNY6-~;R7K_D-tyHjDC}P7u;Nu-=TMqAQz=Y4$6eqwcRjfAY%0xjFB9qduSpPCHlT^
zZgz1fmOw~5`H-T=eXf)K5n2>gTRE|E`>$&&j}%TQ?9f=AbgFo={tS)lExJpr=RuwI
zDzvgO=QPb44*tfvV=1`9eVBvp?!^7{LbFEoXcCai2Rj!)yhyFP`kH6xESx>*CeI#X
zPKKPuUYb_!h_HB@u14cTjd`cS76AILuqDm>W#_a$Sklxh_FnMa?`bd!Toc~ZIH0D)
z=0!6tyR785Wq742T5TowiZBE9_f_i8p&EJA=tI16;!C~8T*Sq$il$oj!B79!>!cdJ
z*t0ONLRQhj4^(SiJW1y`%hSRV!-A9is=GH@4kEgD10>xpVhMC~i0e%$>MuN@zwBMr
z+uZaz{ojiJq2Fae^M+Q-LEI`Q?nnavbe+!c>6W>+o}oT`gE@YjQs%whODVyZiDt}@
zk_I#Vx}QcGdK9u@AsK9XjLN|p9GOve(ZcN3B*shkf=eD;GvW}&O5fZ?oz4CRm0u3g
zfQHWes_SCLDU}N3t(Y32>;sSmf?HEP?jS4WuHr=NYi1DgHG>z)t}^XTqw#B!bq+48NN;3h=R(#Ip*eBh)cqY+
z3aflmtd=VV9!r;sOF-}V0&Ai(IHdAgn6G_Ug6Bj|oyM?e3)9~hG4i?azHtWglZEhB
z8%)@-AY8(*D7T$*X8H&xfwc`+Cs(EmTta3n-4a7~813guH3H7v1Xw}#tqYn*)lp9j
zLM|l6yAK2tN}{0!)euzRKA#Z8wf=PRO940G{_gCDk&@|+2AtuSB$$>rDE9dzgRR9`
ze~B6Pz09-?f8esQ(`ihb@Q3pl)7l12X@RI!^#GZ%&Ro(oc%9X2WY{XwjD6%z&ro3`
zK}j$M6V87VOfZWbQ1~AvD3tl86CYNdNg`~+Z-z=qA1qD`L#Mn)iW8M*iU{ii4In3I
zm6U!;PBTFV%@K`(U7SezDa@P$enksO`V|GfM6W9|imw%!tSi&mYtk_m!boE+jlcK;
zc6QF7%h&KOiS1t`yKA(3O@G+Y)?7E9q8YGxHq8L)p*mjmmFmd%;7r{y`lzLJnfQlb
z!V7Yu;u`@S24?qyv!pX5crgCV8?lXf-i;VJ&F77Hx}AQ_fxWp}-xgT9WLJ^pMXF<%
zJDAY;JM@6N8Y7=|b>ow>81UQEEtNZD?bYslvYX!H3@_p(&-Qi~8H|Fb!zxqOCURoU9ao!GsO}3YshbrOumraJFx62*wQgL&u1frQaB_
zuHrBS-@g%u{pyG%i^FajF&4^ymw4|jBQ`+1SD9zZh(Vu9W9Am`U1`x|5uSWc!8Y8X
zEiq`BCN8v2a^D6%#)t5P-$TYLxtz##gUZ$K#QGT*F8RZ5Dt~%6S(=mlC6;6y#Jw=l
zB(IZ%nNb4^FupLvdF1WRQ04Oev|9WTMhPP>N)uErNa23!Mtv2=wB53gC1zoMZ&LAH
zTuYet|6akg^1J`@glQA+#O-X!oJqGD_+Cx;-U57Y3E{gt@VyB5p4Eu!9k<{+LCLAE5LkgI_%0CdplBeSWVlVigcIpu$(7O-
z?Y%<#EJohCS);2-!|hc;b9Ad++N|NNJv2&t{ls2gFb?#sRJf`Mn%}<0Ti;=JDfIm=
zvB&&4%3&B9$4ngMcC$Gi&PM$Q0x4omW11D;#
zbzLwaCTY?{-j;+^^joPp_chGN#PnL&$|Z|-(gLT0zv8!w!xJsgwob%eINXjuvb`%z
zfNmqf<10>rRZVYL!Gv^;Th@YxBuuy(hjTjX=8^&)b3cOw;PM*p3HuOz7VUAKM
zJ{Rj1C;ptVKeQJkBnL_I>PjgSr!w6!$ng3n57M@yChg4D`4Kdy%ly!
z=DSbR|Fh2ocg$`KnuAxVH%{wEum|+%b|j^T_z8j?ye4`?zvjKZ_5gMu*skczN<<+I
zSxsI9H=#3A@98(ypke~?qJ9Y5QmL@I+@baSixbjR;;D>7f@LJroyj;tlwcRAt>z%^
zf!s`xn_RA#O_GsjRdmax;Ew2vLG!Xp1Z5S$C;&#Bkf|*J#yCKX*q^t;DVU$3Xjvuo
zfKdp+SZ}5p)ROXIhZfk>K`$sN`*XpO!jwYDEgw0d_fetEy9`;c?)+=1lFwL`q*~7>
zF97efWEZshY(DfS=R2=gHHY=j*mM63eb*PAzx`UADcbko@vCv;)TyOgI(lgDFGdu9
z3V7V#b~T;@1&k{1YAR`Ed%6;`HH5wWnL$xNi88wm$;kX
zCTi^4MULMtaeS$Zvv2crpFcu8ZpJaXCw%lrx-V1Cy>jryn%fT9j>L@}ydwrFa@;R^?
zYk}2R17{Lyxl+N;nWFMoX%y@fG$L23DI>oE*khOyu;%;g%w8d1tE_u^FQYSKg;uoC
z8M1OBENXeI$>__<8S$x{Irx5g>8V=y)AyEx^{}wPN!ZI*q5l`JO<7{v?wYA;@DIu}
zLMM6fw3!L}2RU8D=`k!d=pFW<6YpLK?R6p|ZZ(8&QCDmPTF6EKa#0n14f%~UAbKlO
zDP=<8Rwr4WDti0Ga15MK%o}t20k72D-sYOWl-sM$E$4Ww?@_yb!=cGV&+~O(j;PY?
zSG2j>W?ks);Gv8|(2j&o67n9(_z2pOW9m2Yp^Ov7MrFOqAzJbQv`D8`kWTqb)X8Ao
z?9&?SE?allr-F){Qd>=)fc2HG>aap{TnZ-S4^vZU_X%5qW>-Pl_(S$KKu@(e?~S)YTj``4r#
z%-(PO26H`PTOlt+FjXtFbs0aENF#A}6SsvmK+8DpRn%NJ)+x0+C#ve~%
z_G81C{lWW~C*6JLO6|^G_C$fpT$@&3%qs4S;k>Wj!AuJaAvX@dT;0Z2Mi}O{Tw5u6
z|9#-P;iUuZ{B|o_n+1OGBdoC
zcFoX~-d<6ET9HK{^SxS8pNlrDxjr6K{#LZGhw&zzhU6YYQ!l0y?T7la?t*u2FJ{Oy
zGJb%L%UZTZFf>K{GJe^G*SvFIVp+?ME^V7^T8LG+P(%$_xdpY53L99j(ePDflWg~U
z$RY!_X7&cw#bzG>>7C0FB`I-}z8JsUJ
z2}^&o8#nx$vDi6VKRfd2v0Bi4$1cPZG3csz<7wJYgq*_jo4z=C`phTiKK}CfS4S^?
zc2%5;dVdJ-PpWv)KK!xNyGnuLAL2wG
zs7P2+ooezgay%Z>68RdS?+-YG5$&Z
zePX5SAX*H(PPUL#(7`UKd-7*h!m=VNv%W=-K-E8x(^Za@YAEh`Y3x>CB*~A*(}%
z7&WGnW;4H4XQrLg=qDJY*|5?CM_FU0ov`z+SlTt6>%1qLy3l*4{V=o-l68oEy96qN
zzf$bJ+pzP}AFL)+%L!eK50*yutu^_G5jO?;B=N#R&j%mesn1wCK%e$fZ_m5eMjHNj
zO~jsgpDD_Zoe--+gPl?1=SulJ?3P$5S`oWt8DuUW^VOiXErtDfKul1Z^gei3?im7Y
zRSVgJDQP_F0mMiP-bh1_)ZGd)0q(oP>PVEi!}s=hK<*KFN60tyX+z5^Oz*!0j=_~U
zPs{^$o0ieMM0}h9eHQn6%u{_N
zpRX1{g|wQTJ$cZ&ieV?%N}YXxmP<>oW0RM`GwPamjTM@lMR%Sq%39`qrLY}mGoWhV
zHxx>zQaPVclSI_UsBlT52|9!XL!p4!9>%qvGty&$H~iNHNuDG1HHhz#UO&3XCVzEN
ztLFC)f$I~WpY-LV2~$3pGWhYoJ>Kn!>*Jn(;L8UljE{wk&tpst#(BWX
zg;(}sWc$s^?AaanJN*BRZ}8GB;~R_d>D6g`d*R*KF@Cv5y!Y&Quc!C8j`!rAc<*u3
z__kqu4RU){ztymeY8|v*k~OUv8>K*8>qR3dvO#w-su+~h>r58a8Bwo+)Kl>0ZeU`_
z7kgC-)L#z@Gz_^43%lDvfrv+4BAoyY!dNGYTo?aDl?tt_MFcOE3ia=;P@xl}4iE*J
zu}2+GNpH7_Y}Em>x>QHz)8+9IRX|x|h4PyjmAK>67K5&nbKa|e+-)S|p{+)}R?m~gT
zTg!D97we8LCH;r@dbewam-uUU=n!j4^v+$>o|ab&4h2!o5JAfD*iyuWXdteKD=qMW
zS3IpyoYH*pl8LJZmsSlqMd0>*pu*Ar%jFVJ)+rBanf)IkM>`+!5Qwc(duSZwF(xby
z;r|PxN?RK2n+m~YVu!Txf5!&@4;#ZhVTH%RKc+GJk#tsk7UdTm3h)y|W*-M$koW%5
zTcK=*Sv{FOt3R__(wTjX1c+xb`|+{h^t7B|{ZuBny>Hl
z;WL!Zm2$<{%OLgTzYC0l$1T_fOZ6IX(AU_!&>RqtESEkS6UHCSsSy4SVEuBPF<5q3
z#bCq9Fa{6Zg25s;;m`O9&CdhJ!}wb&{5SlKUuu7F4D+rA&VW6`AA2$ToxmjU=e>3x
zQ?U06Vee^XsGkdbE{>qt6UJS|(|vypfA4n2UomFUP57%ptor|gKV1la#{a}0tALE~
z2xecYia*W2*?YTux|$?)Zb?2U=uF^9Q}ll0T79h*`_<{|lXo$k4&bzt?Q+6*F=ALD
zv~Xu|0+9^-2+o(FVT_rc0~tzr7hZ-86*K)&ln|)|XI1il63#EYs^p&(&hLCx$^S?=
zf25lKL^!|oPfGrW!uhNJq~xC%&L5}dKYAnoUzPl@I}X7^F{Wasj}PbXqvk(?{EAM-
zx=6`C4*8XL!L8)ac1pXP@G54*3gfNluV4L|yK;6+$=Hr>{qXJXn$Vt#Z*?}#3Oj9;
zw^+ktb;cuZ{&fb;Mi*II-(7ybOatrYr^%Zgqs~PCD*IR?Bl~(Dy93daO}b?1
zgV;_`ruTv9+H^Ei1v1s_AJ`Fc$3ca?%3YQ`Fmqmbtm#4_e?Ny
zhQjS^MM<0#h_C-e-T7*k@{$d0JPMgL1?>#OO$U1yKeTK=(Jz*4`*dmG_dQ!fbsP!T
zp~B~S&2CNSd6UHRi~3_H>(5s><1*9uPt1li19LC)?v7)IaZ0{y9>fdT#I%Y0pD!o0$rY{C34qf8{KDkiuo!b)4r_|^T
zkGPokF`UqyEo3w7r3IkJB#q|hh4?n?O5okRE%i+A(@k5^K;s6>o8=4hBgcZfzRx+*
z@KRH>>=yaG?$wgvNhj!fA*avKP4i?F;yx5X@p_jFn>64w>`fZPBr9stV*C|Y@?NDK
zpftZ0tr7h*a^aaFLbks7i(10&?p~P
zgSNEWRSnS(Xw|#)HfP#ReZSW5WwtI(5x--;){46#)0O7J8$4@LR{AJK{_G8?%3O#~Zr52jf{c^ogSD*J
zSV1ITj9!NVzi;`)iPHn+R0vR;wu{f>1no?SRy`h!sp{fhbo7LZ3+;2^T6yUp+h~vd
z4193($KpLcod0X&BC)$51zvAxMh)xlZ{nqQ_^A`^wp9vG@P6^s6M-LUuL@Qg5$tHs
zD$f$}SxAl_hT41dhQ&gRSwLMYE?%b_($YTC7Z#SS_7U(NnH|&@Jd$SWM}ZzK7YUc8U2wvt
z;_`7|q6lX(34Q-X|3A4`Ib|CsM1=Zl4YCuj2z!xhaqMBj;XbP09e0#qe$R)IR@<0J
zZ8$W*;P(x6PKmS98D9v0kD`Q6txp)eZ}*KdlN7jk^z4U*TZ94ckX#fO21U7>#6
zA7sm)pY~5cxBD$9rO75|Mbg?a@qy3B6db4D?~W<%ukfIM_4pesD-JAl(Yd9r#^>6R
zG(YFv&#s-PTn1P~8HDNDwI2qjYhXVyU0W|l_je=fis@SH
zBGVUk>quYNwIf~AwNv>Plt;XX8|9-iV|Nt}E`;}ny8k#)6MJDMS3-IyNa2Wr;kK5q
zA$>c?2G?+GmqgKUM%2`|+xzRfuU;0Y5wFuq=`&~6xm`;#3X2sETTI^c(XpCyRloak
z=I76zef~`0v8_jr96EXM%zp1YF(RX8kYn(YVV?Irql;>atwtSH;yYHLrEa(M66aa_gMNnFLf
z%h~(ue_Z9R$&_RRR=n2R^jpS_abA$mZ|2hY^=8~n1>Z9HWf!NP+@qHu25!&0o>C;U
zNLYiO(8#h~FYxQBblgRa{ED5!`0@Ij9=!~rfysYz;XPlFS4A>BMM{t41xa32&*VdI
z=__2%vFBH19D3B9v3Qf)`)G5fJZ6V}wAIk^8|Hpr)F>~t4siUXunwC6cVgAX&)I-4?FD8w)Ikl~O4K3ps_n|@Dp$W{f
zw@|xpRvKFL-0;r=^XyH4QPbp0b6zydFFQF8`ZeDeIQ;eXG;zJTz$RPP<5sFVb4Buc
z+R-znDnz)<#=TS}CX3trdb*
zC!d!MLU($nh-Ja5?td&8FF#(QRcChDRg#YEkjiho{~hmtm)PjS8YRYA@WduP#XB2R
zG}s-iTDd^Y*Z*?3oNN)gJ^NAiu@rY!iBsx*fHa+Hhx>E8ef(BE&Z)++5zY_L?!x&o
z5y9mT_u^B!GJDE+Ht3_l$AUX{y%5e7Jdr2_PrUdNG_kyX^3Rc@rIQk8qp}6I5eGAB
z(%jEv2CJ^jNR)O-M~Wt2E|Aj1pP4*6T}b=qGn_tt`k0h;DXU~}7tB6W!oN7@<>e6cW
zR@xyi8+6NgtOI_vNYP}yLJYsj#rvUK%Do85R?9Y4Lds)u>s83$Er|amh{WHtBGt!~
z8xllQ!uKpt+~pVfssklXF+sb}CybrlSb2`a|4*JH9rv-?4lVYNe$s3o`IL0qhCfGe
z|>U((q{7t(zifO!9qfqi5pxN@g^AbjF<#hRBp@%Z2N6Waj
z9)>8;hflh&bq{!7{XE(rPSnaP8hRMSE_4PTEo6Dc7j$y>mfPOw^~Z>NBW4vUwKP82
zJkv5K$15WK`@sg#wc=QV=G>OSPN`w
zjZA(l9~7hxXR!TY^H<9Rp#nBk87_JG)*hRR6w15CIXN2!ba
z;odKvyjNb*fO*%_Rkqjm5VW*H+FC#ZF$1n*l(nqiHodeNtFVmCj|+?|!QF`JH&E>u
zL_DjzlIs2WcCMmuvsqrE*U8!_rayw8>EX?UuAux|a*c|Nt~qdw2M
z|DJ1gWr6gC57DU66Uwz77=@jn=)_38pbOmg%av>wVag*J*RF@JVC{99OLhs-#{Gny
z!0WZm@bze?Q6>Fcz**Bw<1Kq@Ser2r)$$`eKqBfZ2`jLCty|g8EB0Xf_V$@mcr3iz
zgm)R*b!ev37oSSx$P(Zd#(y9;dGxcO5H9w-<`{vTXcaS|w^Bk84LP(*Lh
z4|bI@{;*Ui!79_p?uL=_%TqW{ZG0~wGO;jJmrKlumE>n?N9g^hEGfkrSAo&n)DjJD
z;%VOqBe+F6NEU)9G>$l4Zru`ISo%ehj*mwHF(GKcBId%
zG`PezqBL8q@}+v%hKg+iB~S792_Gy;EX?%59#11LBD-2(#@=x63fpd<=Yj0UJyP~#85oOwQoje}SEoc*I0t2ZwP@C&$6c@;
z051Svl+)$w2CYjhEU;znMhUIg^&1BK&u)oQaqWN6Bef{FMqRx!_P4n*4!$W(uEg7Y
z;kRi%wH@`_4Elyv)wgGSUhz-t!s{7}_0r>`isqa=?BZR
zfSjP-C)N8lN~bZ`v)7IQKk?ygp(vBG*4QZ2x0p
zMjY&ix??K~to;-?N~13`!Ri$+a~U;lIda4=tfK!v7~O@bkNd?ePhO4l|KG6nepwWB
zX<{;W#I?(o=1$2h*yceS#TXl$J=oy?Va}+@z{(i?*mITMS8r$Q8i-@8aNWtdmkq~!
zX8h?&AyO7wSz!K@c0K0w(aQ2A8SY%4QQ6StIe0~k{@3kO)a|{
zMz{(4krip~f0#$C>sKO(a^$zDB?tGc;+{~{)aEP4tSYdzz84yu=`CH<(aC$F)95^A
z%I}X^UtpW|9>H!}uD<2&RNhL|w`bIEp|?3VzL_?On4tx>x85`8fYH|sQH3mWtXG__
zo9Vh(*k$y@(KK6TUoTgnUGZM$m0Mt2u@hzS=e$7yy1wVO-H((a8}~pTJl*4jooY|}
zy+`dtzPB)o%R()n_K_^x`M){&Kz`Kqh0+JFl`f0A{&6MAXrNTEsvNb)?k~_69nXwa
zq_*8yNy3)DQT#htTDBSA!Mk?zdO52EF#uF6Zbbc?xW9|X+GA~7Ym;vwq)qa*5MZMa
zoH$y)%gn**n^M&ndQ>}SS@&VNgR=}Qp|YAtLF=h@z~Z0biB?8aQdy7(q&lD`N(!sl9dSsskLNz0$u`Vh#80
z5hdxs!hEt4l)ousRGy22U-zW>*oPVg`CBy&9PBS%mupfk_BPHs-bef&#iL~jrcGs2
z2|oG_y%v7UwIYK>X1>AN)IPrmUvQF-8kgv+%Pjh#)pOLCu%P)%JW`pZ;4sdqxzo!$
zIb{~59>p%CX<2n;u@8QJ{)WG;2qc%%&77h4_3I8mLR3
zTtT^(zf%1_bCoS!5g59q0|#YARO*G7hQ9T`dM9}(*TgyVw*0SL4T~sO%VPTJlfm-V>}j8{vprIW+ihwpjq%A<0j@)z7w-3Pmm?N
zbZgD$JJ(#M%#XjU3(RJ9e^g*oQv82b>XiyvcR(EPf3z^5dEj~g4iEKRJ1g?yTn
zM-mE8cOUI4Ht34EG+R%eJXP#|Ez4L#UQS(Y6@p(w?>If@E2>XxK3HAKy~Dh?V&Kf3-;q`+vNRSW~J!$P8=xLoQ9>>6@CG=7J<7pno+z
zz)h(Tq!yP7)NT^|1iof{qzYGql6$4a>r(ssesL*02vj;9j#QR?c9&zYn>;4>xCbqM
z^d$L@Q*_PXiCs^&L5?@71{I!k!Wa0&S1&-y;S7scz@yoP(~&6b?AS&5Uhw60
zu?dBDLYoj|b$_x;8`=5;1=f(BvJu+w&8CD%*4fi=<>N$;d8vRoC6aaQ)}1WXYR_K5
zil_gyzabyKrmM=K0eqv1+Hq#fKmDZjiZQpemGCmPweCY_s4d|VwC?Lo2~)U-AkP;t
zc|#8T6K<}#?w_4&j?50s{R!NA!c8^TC#&@$W`cV5_ceCBVpBpEH?&fP8Fyh`QETQc
zVVKQ(0)00(63p?HTx@ya3+zr7Dt|!-&*bypB*LRn5YpfcBB1vaA0y@D3&8Pqhtn3$
zTm7XDzIlBwCfdMJ=@26T5O|&SUr@AxzAIA-H_=$I{5go8s=!wLIntMMHr1j%)v0=?
z;Fg>O!sGNuY26x4Kkdg^&_i5o%8~7b<&F->>TAi*6E&PqwV=H_u7)7arTbJCUBNCq
z({j>6(36vhfdbYqp
z_JVfnLDnx1l77`1v0P{^^0tT>N0-^HT9#565z*%UqGg1^4b+0ZJJu
zdq`MKaSBBcEFbq%abUIvx;U?gd6fUeLGp(x4$dD_aG<}cDX_&^9{?ptb8Xe6<$P`S
zzS_cNdSVY080jp=Q@aOpdSGSE^%QVzl|IfgyhI%fp*q<3Ao!6Etlf+)YYk!R$wU7a
zY&j1Qwl-AXjIH|pgso+l|8Ll;9vH?}?)$;Ux4*j?Tj211_)lyI|5CBhzW4tH8|Sxn
zU?ce*@U&mwjE$5dUdIZ3;z#^JEqr3S9>Q%xHJmm6H;B0Fh~Fnzgc2T96f~iw0g}bw
znx=tsn|4_#4d-RwG_cOKMOs@2rrle@nlL8`X7$cx1L`MDMUfwNq;AgYwB`=H{{oK`
z)Y{y@oL0d)tzW+%C2s-KRIq&q_u7EoYqLoJtbRVU2t^pAjiD6O`*2y
zH)A}Hr2wWx=lb6eMIjhyj)y%3G5>F&LR&V`>|0Rsf0=#t8))`bu2*Is54(D0ty(wG
z?0XyV_P|Xxg|E)7~
z!-4;tnOoMVGxNz+sh0VmRbPi_)s`aoGVkp?GYX_QtX;plc3%mt-JYH^q%97t@?YmH
zhk={HSdDaJbLzoz$1q2TUh=V4^;b#jF01=+qAfjFNJv>-Y$j^TmU173^8F%MLciLH
zx^#HPt8;O%!-sO^tKCOZYX%=wb5`-G@F^hLKpt4eF+`ICi`t~L$v9uSTjR$a
z^mB^H8*pL%{71jI0c9%gTvBT>BkH;OD?iu)VPXivI(w*gh2ry9I7FKn6xs`_e)i=F
z38~gM9_+m@>;sl^a>6l+hZByA4E?hsGMxX~zPvZ8432$zgC{fD_pFd0WEmE>w0AL2
za6@Nl$%f=w)&1G~FW7T7<9r^RRE~uiYIDdc)>2_?Wv$EB9Wdo5arT_2{v*AV
z(jRp&Z|$SV|C5F4NXw~ZRIUx4C2P%}SEaow!4}yWFclmLuj<>mA*WMzGQbXXDj{qY9jRm`pT-6)9(3};Gf{6
z9(ZcLMh|{skceu(w%DzkS@A@g1y$+X(Qt2W$&=$y`lzH9w}wgr>f1fn
ztuxe}*etjmv)!T1VLZVy%8w?wEqz4;seC_HzZ&
zx~htFRWe^`$#9a~4f+?;q)}_CI~A^J`Z=oUn@37=rd5I--pEmPGMvMFmU3)+qV9=@
zD(6p{KY5-H`Fwc^_A9rM5B=q78b
zjXx9zP8s%xHOb&|hqABd>>C?y4|VUUmRFI>w3q{K?Cd3QB&{Zv7z~#un$xQ
z)IHTnl)WO4+Wcav*XZH|>GU$W=huw#|K*b@K6;M)Y;UE2vtBiIWbJd6%Gb}vR|>XN
z=fZs8;D@p?SU2YCkH7JuhR??tYF#)XAzk^`m=_{U_rQB7v?`z7j
z_CYT=XNsv%s=3MvtOd4>W8=r_$DGQCY;Q}Oe84QYV=p+NJqz5{6FvN3bzr5g-J2tF
zZ!Lr7nHQ|ifI*zZifnc(aBsVs@0om+;XELOd(Nuv2%*tmbCpr6zdW+VN6&vf;q+ln
zgi_zlSzSq~*PhtzBMHvefcxPP*Q^mYO*fC4yX>t0tORcoP3Wl&JtNNgiSIH93EJYJ
zWO-fR8}i}{87?~cPaw;I7ru0nHeq2t{r`XcrM3==xVntZE28~P)jB|XfjVL(dyPw5
za7hp-{uHz<+CZ=R>xQ9-5(xV%f+up8kehgLg>A57z7C!wf)GPe?2Z)LX-%vNR0@((
zY!eH{r-5h_Zxw1|VOfXc9hVrNRYP
z+6^@i+40w#YbKhe#!;;wU+zeCM>+f0h-wF`cEMJ>^2d8D_w2LRgj%%7-=jsykC8Sy
zl^{zWS#HLyG)ZVx{?U&XsSgB+Nrx7799mrd>L7>QH4;*50V}Zd$Sutg4vk+99`jJa9O5q6B8
z(>m;1I;f{2~K9PT{(ek#Zpm$iV_3AFRQ%n^3
z>$6(erD2usw8-6RH9Kw97Wq<*#w2cJrQ%Lz5Mnv6@G^SNAsPaW2xdkEuz*p*+5Ef#
zG(L!@qmIuCNMSTS1^KvpyRL6};C5wv5U(J`xl);p!y$d$7@s?D^csG(G(HPo#`t`=
z(=x4dzb}Y-9{e1}=leG!c=WQUW9|f~-xk8aQuN#=f7h(^*gaOh_^yunYT!Hd^$(wD
zWv9r{(}r)fN>2kdTBpqvn)ju`MrOLT&o@R{?RT(h^s}@kFc*~7Z~}Aw*ZThCYt(m=
z|7g5ZoF|p2lbw4n^trY7o1VgY`R7i{oX)+k6T60b|J|EWxAgw2=BQBbi)tg#`%AzE
z#v9gw^?M@zW2C=3tFuQW2?l;hq_+^(@-+Idd;*=+2~qx{r$Dp7O|zik;{P*l7Cwgg
zD1>nnGxFDQvtiM%;f8KvFhpju#8c|(b?Q?c+0JCp65<1cRr?<&1JnO=;H|T6*Wh+HfUh&~B^9N32oN{g;
zU?-^CU=M2%RXJT(^VUGhxehrwTR3k$?HYCG^VPg6T_w2S#WakpF@`y~?*u8ehEB5K
z3p_2=wgP-hGwvYD1pgDPdiZHmw~Z{qqQ1SDSBkf>p|_Q@Owk*$({i?_A<1kgFL%Zs
zCaz3{(%KF$_`17W)wg
zigv0-KNf~<6UB{UHSJ&-8^-g5QPu)YPVM$+|OY5B&Z9vj=rjstxhJdNpgqP^Ui9
z8R~~0Ca6_NvJ!8`U~;p9uX?q$>K4K+r33?^_J6pg{rF#Le^jb%HMD}wx_%hX0fawG
z7?PFQrY;?0yDN*}3Xko{u>{u*{7HmO*sF{pNC!li`dnu3-2$!9sEqeH6}Byx!_Y>5
zs-_45(s!jCNn(9$#hAyqTkCR)lcdJ%L&2)A`UVpchAPw;XI4aw@BUa>bs-IcU?o12
zI3Chz!xt!#_xpKpFAaQkj+SIR@GnE*ogCs>GH>uK(D(YoT+8G^|G~2`^B+5S7J@JP
zkP4kMcw;vPj9AZc;AF1dW9d^(8Whk}ZI(s8&;adr4|dunf8TtA7f^SdVE)bre|>*l
zc0k!*Lz=D8if*Ly?wb3}4N4oLB^vMnm5nw@qTFCHX?F)-Ga4i5LPqM_M$3RI1&mzVW~)#%4*M)Ejmo$e86#?X03;=z}a*pPp}
zsvY7LtnJ1vL__Ou4^~|m`cjN`2w7Wqr3hM8v9mK{3v5Jl+piJ5gpJuRrarr`o9?K-
zKD%+l&$CZ#)T?ruvX&V231@?Wg~i6rbbgz(GQvFn(K}gi`QOe2V_uklw6fT*f$c`#
z6(e$*Of7Yx_b$r&T`ga#@BP11-uvNQgtf5CB`WWCw|tHnujm{I_BZcLwJPU1WeuK1
z2Ymhm2fVKIk#d(N<}2H>#p}v>T-G%~r&l1M-!4@r5x0-dn+t5P6GpH3WP$uvmVbcV
zV168}8IolbNg~#*aE*wjTT`4zy=v&=^cUDBlGa@*nd{K(4=(@R?(P!!-X1M1_`)4O
zscp1P22a(vq4g;AD>zv`IEePF##C!?`okK7fH>pS_X6<*JrQr|Sa8V9QN_t*6}@FP
zeGd-Vl%YOn-fs}{wfKI2@lg6+U#q@v8W~FetwE?m{+YimwkqZ8)b~vzLg~Xf+eYg{
z*5LB(UnELOyJcm6q$kd8{#amxbZ-u=?Fu98vf+mm2)^*w4Oh&@)r6g7zc6EV%#c5+
z5iO*O$ispJ+p3=ROik&(GsC$sA9i&bd6~eBs2A~g55k)q7FZrzQ@&H|aUk$U({<1&
ze6yG3?LRff&|qWn`wT66+Rx%VT1{`LS~bSda!&_BTZ>a2+?|*%Txg#k_sr7$Lb|YkeOvS~?nm`S{O}sx;__{!T4&im!(|KEw42JZ
z3sm+ilw}LTWxqgK7s|r&3lvq2e1J2Rt7@Mb_TUsd!V6u9;^WH)ifWT5;;bCC3jPpE}wL?p=@DSG~o!C1}~y{W#Uq$PGT+0)YEF
z;rTSGX`i(oEoU8;7YPxvP8UH`cS23Mqj(+abZ5PdGY9MmgB_+#pJKI}N)FTf`d)>t
z|69Gsc=n)n*jVlt$@>`bfg%j^T6tM^Yc@fv3`yi7b}49a&R-(^T}c0o{R3@(lS1~x
zjqQOnZBpiuRi@2uX4<-r?XwEjeSj(5#bSDoLHtRK$<36*hc9Qxa8|l&^{$4qV}=@BTb$GHQ-(
z<-03^`;M>f$;BR3>nQMJuW8||M4xDPBHRmB&=YkoZ#d;&?x$839bfxM>nrf>$Gy#;
z7A^T??IRbITL?DJLd@4s)Om%u|Hi2U%MVcgL&)#badqTJzh4-SJoL^GOIFFP^u}f@
zkcPS9Z1(C|nswDq@l9Reb!d4pPu{fA>8rt+rx~&O{bE5f*&8&3r*daM8?7L$r_rD<
zJ5o&rl8TwaOm*+C&hKZ_`)l*bs(k!1eJyM=#lTvBXjYMwLGl#!4%R&uA!bmT7m+9B-YvI5PAqW2~Lu{XUA0OVGGKyh6NeC5oW_i*d_iFhQP(vdny0{
z>S8|}uuBKqVH3BgAx56wqKTAbX9GM30~;Ee5erAy`nCcSHz$_P6cwZO@9lG#q84aQb%yafwWj#d#?UDYt>|XkA9KIWJAY
z`yjk2e8-N&KLsL$?i@p?L}CU)Q|ia&o0HY0{lOa
z?XA6mkEgkMr%!gjN}dCkHCOWHqfyE7H19yD)eFu~!ouFLy9YGk}
zk@(F0l8LVeRekVBS`9m41)3g%NbqNfy9}}+zlq<*Pd?ZlWD|RDJF&Wgx624WvTL^4j}IlxkWcD!N8p4Wy-lCJm%eM-%z=t#4u-^hIdHm`=kT@{Q-;4O_r<
zeBJW%Q6&Z=pn3H)?)L@v9p3`WkbGz@L-gqy%D-$B6k3JIAPe4EVO8If@%H4keo160
zr|^Dk`HR$7ijtaLWw!`Sp!ybmtp!X=uXd4FYn46FR3u&vtt$1oEcBi)HY@1`Vl!bv
zL$bX>$L&%aEBFv`C`p%i?W*RmrP`Ki;x3cGa@hF$XVo`3BG^f&TiDRb^w)OBfUyUxX1mxPQe3p|Pwiv`#
zCGtq%Qo|J$T7N)=Ht(Vv(B^4kk0>x3&%l<(rHTJ41i822I(F~Z${qKdc1xwCEe6b`
zTrzz0n*axCZ^2JSbU;6PR43>c!aJk`dc1Xl-hP!e?dC0z`M?X1bQ1_Re6PYLo>O5f
z`PdHodo_~Z7R{)|UH*doqrVQJ0=GrWmMVh7Hh
zA4ie`aZPk`KcQx@yGy2Esc^wl?dfJsxtmXpWFrdSccf|SS=u{=psZgFu$M(Lopx)n
z5_hqGBujx!&bK#g0>WqZ@pDd|D*STO=UdMmIeYBPnUjO}r!JPA0`_0y_wy|<)3`S1HLcty)C
zsqL5hp@vDfq;6>JiW;7}C3RFV?gE$Pjd~e#<|!smXoa;}l5jIb?cZ;b(i|?cDP}Qi
zo;YjLnMt-Od#0p3zUJ}B8L%FWyev#-U40de?J)13v~O@mf+Hx1}#Fs0mMFeN@@0M^{XZRPI!58HEqv*L^z!rCsI
zAf*)k0rv<@I5y!U;!6iPg!)}JuPYwCQNLs$eZg0Q9Nf1C_d2d1+wPBN^3k6(SELGe
zdZsC61ZPj!XGnDNNd*QwAm9gb2K&H$-T6TU-R*-iyWfMJ^zIH1O?dIl@u6;U-Sx;$
zbyt2a-zLOR`g@2n)Y0as&*VFVZj^rbdVHt!%1`C)YWl$ToARHXLy(KZZ%RFXX4?VX{1^5fw@Pz~#D%G-XtpHjn{?VTas
zaI7n82*a99_&h3HIO3vs6}xO5J?{IFA@bYk_zTXcIeP~=th-GyI_PT0@9s0_%>K^a
zCFiPkEtVGwG3D;$YWpON=BhL|t$?kC*@ayqo@NscO@ItM%1>jdj%4@?-9=Mbt&HX3
zHyJlh8B6JB&3<((myh6@p%uE>Q#6@oqV_WHjm+d`z6k2vV1rry~+i468|{^|QO&
z5&tcprDZ~PqHUK=7PENlt3qqU!W?BiE_bs%<`j!A>&ldwkEb}-D0ftNbsuZYF_VD<
zqAXNjM!3Em1M6vDQR-TZIFC}`jfS6y)?}QBm->{@udYf7YCq!y_WHLdZ@DA0mFP*v
z3H2-R@%M7a?q6x)$@1K$8!dPwPImPd0hT^8PWRajaqh
zBOly#$=L)_kPLeIk#I@zgYLop-*iXXev5BOc}1
zsvB8gjT|$-*F6&g2lo6@;X2L8CRdMri{f-txcq!YL<>U;CD;!~$<1X<(0P(|BM(=~
zuQuTXr@5W#_}FK2&G313RT@qz22Tb*`B~(>XE({{B?vUW}_>5-xPurMN)R&1P
z10P?6l_FUT1pX?(XVin+4x4;mz)MgqFU{rhpjE8I#$?T6_
zV2RpkON88PSgg|dJEApj=aE`q9pny{q)ORN6I+Kfc*N>&e9%LuNp!w^CCduh5n<^X
zsyCVPCQ)q!Q`dSSSFNjWd8jT&u;j(jiB8X?xL)zLW6og7%9KRsd|x=`T0e`o6@xp&e7QdnP+sXd
z=dxgp-4;&W{aZ?188@djQ847j0U`nSAP7?6FFr(!M-(eb#}b8UMNY&znO_7PT=S$0
zBLmO1G(%ERI5lw?$t1kr#kr+GY)f-TJ*4kYIYTGuQcEsRivJc?eDza~hWJHSuw>^W
znTM$!Q+ZjTJ;%yO`iE{J(5x|t&`spF=x)&f{HaC5;asJ_+6QuZUQFP%hU;Cjd?Gg>
z(t0`WgVlV^P|Sm5mZ+PyG**Y3VMY!w;cZU%RL^CRx>(qyD6Kig{9+ySqJzKOYP5jYSAjd1>o1ORM*K4M7ylwiCU}0?&){Sl`is06`Spt$zV;w9
zI9l2-!**=m5_bcCTFV7v%r6+U+H3lIwIji|Uv$Bl45l>1f?
z9i4d6lq0%h*@p-ZoqHV*X{z{T8ei?p^7AdBnc~V0dx`bRvgcGY+)FcHj?t4tzP^6M
zS}8^RT08E#G8Ht_8~*2EVdl((jy(p}oO6j|cg~h|pmNG@>+`{q73sX+!U5X2mL4-h
z`al7?z{&uh<7E3#)`+{9S~RGoFuh9F*MeT=9FWBp;CvG26iXLF27xUdjW3^^dmBH+
z!A!;rZ1_G|BWex0gP>;@*e+-l`|iD~^*yPSC%e51tVlFz@e6f;a`l!U5nqOFII6
zgl|X(WkUW7KJ|P>J+}(W$WF9GDXVmnG|CJ9hWQiQ1Y7njXizBSd`SnDrAY8ZX^FDJ
zQmXI_Xf(7!b<0kbySe%TTOZqHA7R`5VYxG0FV)d^9qc{pqR&jLJW?2`)O)i{qjkpY
z#wTB+@?ZE0Y=VumR{OlQ_27MEM?(Z>{j`Brt9b3XWe*)_Gqx4Mrz1i}{MkMd?#I5S
zQnI{nJ;h;4hUoi`zV9;lmJ_1_*Ze;bU8kB;_S0!wc9nv2zdwDCW5w}d&^YybOey0OhpFwT
zk+jvm42C5UJgl|O+_tz2MFhFW2WtF>mR~jrq+uiNwvfBg#@TS=5Fom{(iDSL5u426
zY(_v#f3dxGYw^^5D&0{ccGn%Ra$7I^aA%6PNz*&4ywC``h;v}>jWJI2Yp!OY%Ovd9
z%q}T-zMn9=q~G%dx$~*SgHGEZM<(^%nM5{jb+g|!F#&z=yN2Rp8U%|bSTcH|U3yuQ
z2u&Yu7-?*8<*n~%sO_}Xo0&rQSWGf+vuf^<%3U7g#RRX;*=|DYk$<
zEKap5@yt7C)XPm_7Pd1k5T)#_1{i9^K^yljXi#&UT;UeRO?({udKPBglhb&TI1nL
zwMMnBi$7AmPGLNJe|Bq3T0tY^Qb~Bb8HuW^9s+i0i)N6+c>psKx@5cLgicxPsaj>z
zxeK6gTyTlf-4=Oiag2QFD&lB}I=eJiIe%`_cyUj3;F;QAK;<;OvQ+-3{yR@~Q+}^8
z;c?qqZxF0FLZ*07Hz>FQjWA>W-@*Ml8e%%rBtC03tl(r#t2Pj~?mBOq3!LU^?AFN|
z+ClA-RkKO>q9}7eykr|keK__|zfXIQHEEN0`{buIZ;aU#nk}|3-P;f!Ov7j8YIrNk
zh|^#jU%5LlBl+LF^(jr{xAw^vPz26K^(@#^v<-aGj)L3A9ttp_k!oCpHapjt^63re
zF-qZ*=RZo`#!G
zDn)M})}91MB->hX%XPiCR&Y4rNF+2Oa;GbZN^x(7SW)}k0u-2hMpq@J
zi8l53{#@4#V0GWW-|zMPLuZ(Co$KLqeXh^*=W~teyS5-%T!i^9wCbDd@ZHA0(ii9V$vd>v?Q
z;G6w);%_XTE|m$xKCYB^>%oik>Lf%up*q)gYlXC-bh=z7l(ITlmrr=h8}E(Qe1HAb
zTi$+8G_$z!ObgJv^Oc+T+$^-e97gdCM5}y!
z7y2+fkN=z`F3b^LvtP43SOTb&Z}idtlM~4Y(
zUdLVFN8f*B-RsHtM20XuD|-Ktsf|?qm7efh49NpXe<21~^nDJa&o!GH;ko1OdRQI#
zI)j9o$?qTCkiF*h!Qa=h@347($KGDs_cec;x46OHr2B|yZ{iMq?Tdckkj!oO*0j%L
zmj3dJaQ>-FW}g?AzCxc%VnlekV22+IKflqKX)-iK`0b&W{{WoAjY{MvXng`tg8fgl
zVsFuFzh_Sx#;<3eHB(3OzjFfk-=V+apNS6sd&Luk)wu7Z{8XxM%xEFL#QtvMR*DbCZ}1x!@w&v|hMXt>LrlLMxl=#m(O$rencSSj4`HN>r=Z
zQ^EMiP*^l)dy7s#PfzYP(+V$qt~CrqX>3H~xIcQMv_}s~pdsvet6rxA^Gcbu_#L-yBkJT8Z3jO^QI$2@cx9{m@J3<+e<
z<{3pPbTgx&H)vfL#iu*Is+z#gd$qCxD`hh0?iH$DCp>v<%*RhQur<@1vT;-C1d0!!
z`?fnyC^suIKTy<3$c3R?Tzz7u8h2Gt&HX|t(?WKq7uzd!-NJTD7Idbmf=NygHS5^#RAI-y_Ee63PhEBF9P#~!B9L0=#Z%=+3@&1qZn)iB`M)CqoyPtS?6
zj_Xz@1WM0?t0oHFZMaduFpu?=jGiJJE76nFJ`b`AqU|t?12elwwx2-wu2v|>li+jw
zIa&ucL*9#5!@7}q$A3*=@7#xHq0OWd<^NP2HTcwINN3OQ8T#A=5A5P}L0nV;D?^S@
zXAcqFTA%u$;UmL?3TRi%P
zPi@BfU{)TYj_R3kdoTC?l3K)~g|7LO9a_-@c*GV}mj9uzbF8m(=u7YGOMhEmH>fX?
zB+a>@ph=TS`>U_D;^srpC1#f@+Vy)zWf1#DmRI5rgeAL_^P5F`j4+#h&JdOa;CDt0ZBU;XLXVFQ*pxd=V`W-*Ule+k&ULzNfo=Pv2orKf%*8c-rK9ddc^+
zhdq7&5JBXdL!tJF(-Cth>MG*IwkKE=&tHkY(e6X;X0pI|JFOOY{0;8RMU2(9liMC*
zcUA;o4u~omdOsRLzhSOvt)!1U$>H?!VxpDmzAF)c{@T79+fI6Gbj#gqC8_WbwWfJ&
z`-`ttg|F4W(W<<7m3!?dq5Y6%uLIqKPfyR~v#X{!==LKqyy}v=NA$dN5{&Y7M{V(rK
zI4_`w0gM4}&v3>c)*;LE)lOl@D_DmS+A4hp^oKhxm10)6wh))xc?v5H$T^B9w9Lg);%f7ue&?>%}
zi@OYF9ba)wuo9FzY{G-+s(n
zUSUhz7}!KBN(3$qS{cZ~;H@dXtNTNua_|}VITv~KW1dir=Y&y<4=BBsEsc(aT~eMx
zv!C9FyrqQ(;XqrP-dw60uL#=`|5UoYk-U$z8uB2!^ZPy_Ps8>^P1)YKJrOep4q(QO
z@EATJqUCh0%3_d-&m36WtEYEh!Hnm;_&9bZ&^!+Y^W_b%%2w0(0Ud|q8RTAG56
zv^nFC=;lyM1uf51ed`|&Ess;nL_{KTxm5ler?-`^DvAamdTuSjH!j&jE(+>3_~fGY
zs!M2+Twae9LyA1wKo+qeXyQS^NrG1dug0{3UhtnE-cQ+b`9T^jZ3ZdgmG3
zR2Dc&qJN!KipZ~z$^!XXu2jTM=+SBKs5v%)0b>t<)`Bk04
z&TD8Nq~3XH7)C^OWv&&%zRzIS90ChaQTrm~%Hq^m5zoXke{ZaDYxkV3E-}d#$tAeO>4AB2DZ_vav7ls+f%mjW#CZ0hv81|CGpn9a|JP|&
zU{Oz%a09vQB>Tf}Fo&pH;)=!<&;W9ZJ>8oxUr^0$*~fvEbmF+oz5J6oEzaa7A?4$l
zfw~D~<9BaaBA5aXKM?GRsURw;^WwCBb>C&tehCuIfzp|Xj!~5!@CF@dXa3I$JeSHV
zR@@j(nnEvSg-1aq6vANt2Db@;Pkkm-xk)F4lM3ZNOfyN^
zPPm}%R=ybn`7s=CnG9Q-pTo+=>r8TLz=l%v7tUn8O;s)QS(&G>Pef0(jImHV{?>a<
z&oLc?Nt~M|lD9m!$AI}3^+fyZ4B2$Et&j~~=B2xAN#39*VwIBJF-N(n?p3m1UaVGk
zLY~u2P$QIk)jRQTl=4&c4*WAJ_p76o`_a1a28$t9-{^b=cFSDoMTqts!}KD`uQWn0
zio8uPB7A|qnMCD87RBh;9Fy&5NNAZxbR7C*8s&?4N3EVx&B0QZg=`a-7nwFqi)
z=Sb(d%%9W+3E2hj86N0<)qTZaR9|nq!+EX>_mcX4iBe12V#K!2yWIw9BgWrG*u0wV
zGEPu;c23%!!uhY~zj4>WPcbv9>KdXN`-IO@=$CeeziMcouzgO2lb&JiVd}{5{cVD6
zCHu9t)7RXio1U>yr%u{^6Mz4P{?;?VLFrc=#WpIJq;4^JwiC{CKIh^3#+&6EoHXz7a`HWBB&0B-Na{8
z1ji~*e||&u_~R5~Zt&&Tcp@Kcc{0(QtKOj#aJOl)zEw5o^bekZHCy)#ss|t+P~WY0
zL4#JhpszyP#V@iBw*UPZ@YN|jddicfoM@sX{(IiZBSk9~V=jH*2$77{xf<1vC|?~7
z3P_QxWBP);7ry9tJ?WN+_d&-;_X*;{T(U#_0k-15Q5^B9
zuZH@R2xjo>WLwi$mG8X3$EpgSS1;ScFVhqGB?s*I{JZv&w|wd6PvHh*l9J+I6c5i7
zKls?0v|H!R9{K2S*O4u8CCmZ~?m-?pvd*Z(cLS@ZrO^HyDFyC}k#raB7}^n7eiuZx
ztBRx_lxdeSznRz^FP^757{hTFK&J=MbfK`#ljmTEy<^yQ%BKMpg`IYH*;kN(Q9X?8
za_h@qMrBL#3lcZHQFr%h#M^};{?3T_J0s%njEKDpRb#-<87y7pbUGYclsOc^0PYR0
zxIapbdQ+&*bp*j&W$%9ik^*l%FM-
zsD+nsGE%my<&yrBkJT-(jAoC#f4IwBR+dS5DX6I}sN3OhCH)n=Qq{=Xju=?>xj?AQ
zXO?(D-N>x)LM8izkJ$w~`W=BIRa4+7de^a28AIpB1nL?wo1dCuSc@aDJIY3~ER)XZ
z*EQcis*VjDt=@@$;{r$bBBH2&Wcym!3H0i?{*mmQjOibRHt2hS;K)@*vna_@1+}{G
zFHlD%hl#daVP-5&zPttd+dRpeT`M~muN*}>G;vi>oo}$Wrv6b3j~3faB`a_XR1{G>
z*bMLJ8;O|KQS8>z5YFRW^t=ldVDPqT>O)VCkvc#9h}lqDoJmjJ`K2S(@V=2da8fhF)rh{4CHS^@p&ChJ+fBY%f;KLe
z*?a)?sdfkMZ=^~T4n#a)-4pJ%L(`4p@z}IKY<6S%VYwcKb%#A-kiF$k|4|LaPDBQd
z!j6nme}aGE_!ohH#z5RfBSFG(g!aWaVSTs}ZUO{y>_7h_LCZG>_%xLVPJQ_OUkG~G
zqmff_0z0;LUZa?8HIMLMhER!5WD$Jf2$n~xTXyRi&AjtX+yAuxH+=WQnu3C|r$1}g
zsc+b^YV7|{@NY~Y_ICzi;OKnAsuke)gAy>4ut`xi&Uj?qZ?posx%xdo|AC_qJVFvc
z?`CZU{Y5$aPFoD@k_&`rSW?`h^O;?8ymR5^t+2t+%Gh3w?X!t!18MaT;nIKM8N+u|
z|HID3F8lb*m&2)TKj=Zfje7gg%l5WJ8D%X8mt*xE;0uHX6b_nWQmSSWE)`h&vPFy!
zJ9YMk-->5*_4F6L`C!Q={5JbZvNt=c423VRWjAQQas8G3b)bLS##)_GjiHE(4RwMF
zATBl(aj{0k#TvsvyJ?P%e<3?5ZdMxIKk9aTmx1rQ7CC|IY8al$3v`fE6rw}OWB9j2
zxJ>?9#WC!%e*0V(?0^(w#8$JTY9yj_JRaEA2yZ(X{^H$G^|j7XtLgOF8k8BUZA6oS$K#%V6o=Lr!`bMf_6`W@L8;5_pX6XF70w`6{
zy!D`~`I4R_e4TY_oz9+oV5&6~x#=Y1`fE77VCJ^=(gmQUyLZo>ntZ-NJbX#-P+%Xj
zJ4W;e>5@y{@Rpyr;p0%?2*}aAlQ@*#CVCi$3F|Y^y2LZ~@Ej|~F3*|4pHM^)<3HFR
zZ`YLfN*7}kPiexNhbrY9VSKh~$PxA=>5_t*S>1#3xnFnuWDBIZw{N^)3`*b}fuxia
zO}~UJ9ek9k@Rjwve?<2%4s|)yLD4x}|+M30d_yC>Y6z3gG|j*;OjNRx;Q
zb3-z}QBW!Lj4ZSJ=6ALd`PQ5AsNiHxXL6p10!tTxb25a7*8Y
zQm$`tiID34#2su#UD&4##4)Mv52E`ULaLB`r;QR4ZL*C1kTav={sM19Jt|U=45&jk
zHF0HR-VB50#Nd%JlKUdj{(&6>wgqh@f2tY1+3AnFGWi;IhnVv7S3oZpO!>+)(AV|&
zd!;&>K9ygpcd);o!*hL^4Zr+qstr>3s#2!+UiQK2axmVL$OhrfZd_29Y057xRL5MB
zO!;lci!IU390^DK_tPTcu{+3ta6$mIsPiIa{^;uE&`1;zTs1cV8WR>t{>r&nM
zO(UR*1cBG&N^?#5_RSdmq&j*_P^|?c1i_jy%r6P^)$P%*%1)opwDhv-l5{Is4fqpT
zM|OikxghLa!>a7|NBOU@0@}~zIzD9|y)coV+%+$nq!)i}-U8XhGJU~r{eG(t7r!&T
z*b_2cdPjc%mMhr)Wp6{*yvVD-OZkA7EAU>MzXc?0FBk(^MybEDq2Jn(0Y5%g_b|6L
zXam-cZpaMw?&?w+^FUjbeyW}KcKIezso;{%s14b?&4Z8zF)vsEOW95|f43jE81{w~
zg!M-G*7fzO?1~2y**)u!QNQpuv>Jy`MrIixM>w-8Rfo#PtipNM($BC4vkOmChrxcE
zn!Xm+Njl{guHW=oxa>#2`fL@61GWka*(%&?DUwKeAkj*Z!w$P5)kt!gOh4(K&u
zh>x~m^Iz!BBaX#QUT|D}-iZ%9k%%3d01V$XEFi*LvtPFncJz6=MBA_kRDjHypOt8P
zg}7T*?W$c1r!5Ky;9MsDUy1fjdGH~=;Dg@3;J1I7OF`;3-sIm$znC7c>@VM5xh)SVlFnN8oyx`l@opo4P+`EPK-}8;$(krB?^v
zUH=cfD?l0QqSPPi~PvQ?&sQ)U!uyC*HIW3$_#oTJ(Dc1JXQGQ+yATNm$H
zo#;FB&F3}-7*0kXk2{L}SmggTqiv%Re=kgnh=#X5EAlf$Uw)JuX)CZ@%9a&GY;JD5
zS-AnxI}x6nuLLC80?_*O{Jq*#8}0D4`L7rgZM4I$&D#h7w1$(-DWLCTZ&9LzIDIQ>ZWwqp<+$%|e_Ly&x2HK=_CPCor1ysPHK9HHCQG4R
zjVCx>40+!Vhs#Z?vgTX;f62|OvVNW9|0@=Mz4j14QyK8>qhed)WXXF_vQbYG(Z(V09=W2oZz8&PcbUo*irvx=Uk!n(oXybUf=WW3D
zZr$;THb^hnU&JQw!+D>Iw~h0dy@ZeHY>O3|S!^KpXY9+J)AF9nn|f+ER(m!HUXu$|
z;^IAmvn@s_Twz+PG(5FAI37Aw*k$}C31(Nd*1Nfv*-;>mgW9QxbQ1BT81~isoV}ax
zhcrpQaefiA*V&SU`!{q}b?XdZ+Wxx&kBbW_cVK7bpuJVc>_Rkm$az`UV!f%W<>Pg<
zZ;7GPG(a-D`&r0N0igFxD)vC?tg77w$*NcA7P#f4b%l%oqI(sv!
z0ihpOH5T6A?9dhHZFsMqQ_oAU!zQAuwU&J41YIbEU$e{>ogZA<2I~`WRB$%Q$a?J|
zk5W^mev6*Zo6kANehQhgOOLZLUs1N5Wh2EMxfeF?=wtg}L7KPJWk=RgXm0=?O)4p~
zS8SmEufqymr7J#4w1;Z$A&PjIMAwZqdo@
zG-LYZ68oh`7kL@l$e$2#fH*syl_-#NVH3@~Z0M{(;SRDHJC#=n$J^mQn}(XI_rka3
z&7QhIv+uIiS{;$S1|Pg#k(l#?dBIz+M2Ysjy0IS76NVW6c%3@z3U)tMxB=Y{-%uY^
zEo&1h@v9s@9XEZd!}06cc-`1`+A-v#Hkay#x0C!wdq;owVHMy9sOohK7{Q_Hrspj)
zA>H39?5zXG2sqBHe8e4*A#IlhEeREoI(ziUNr_5WN|q~K^HfynD-}rc#@YXUWlksT
zT4x=EEeo=NJ4wn@~#
zIgfb0h8mYNlN>8iip{uBobz|QUvuGXV(56#h46)RlK0S!)LE~E_+_6~
zpORn^&0a03QIZhcIztyKIm%*mgC~@vbS>#{9o3MWk9zP_sc_CY_W*=4pP$@PaJV$d
zn>s!jRe3jk*zE4<3BhR=5`T$3YG}BN>Tf@c3iuVjkF-vg--H(qktr|s!tP-)oVK6N
zlWh-f2_CguA3S5!bF#E<8>0n6@s#0LC)!SHCe0P?&6>U3*|JiUIh}|yF2woF?vK&E
zL3EI}`0~lb-l6vukmZzM;?Gv*P|IINdt1k>|~8}w(Ql2R8IMLe$%3ZoXX5;F)i_9
zPt_B_P4R%qzD?pnNk8_ux27f%=>ifiuJuz_R^iJ~CxYpVQ`Rucbu8FN{bp)Qk4VNe^Oe`~q5`2K(iOOK#bMh}I+-
zW6zWiJ3Y%qIe8N7_no(>f@dS@b9D=_`rxik<>P4F>!-@&k!#aBNzI9g^LiL{{t
zK-LCu#u>0wE`gjwxgj`_duesFwrKbd==OqDHM2TsMA|(XkB?JjBiIs5t8+mMrLxW(
zta0acV1v{nIju>uxbTvW(Ll*tQ~obM!W
zp3&RYwInW&b|5OvTeGS~Ba1_}?mzi&X^?cMG}F`6^te1cZ+g>;2z@}aH5xUgt;@xs
z7=d|56+PyM8m~uB`!g{A`*}qB{3bsZ?sE;dm)KwtD7I3EmSr@W&Y0cVCeJBzWZ8sVi%*KWOd
zcDMeBCZnJ7XR5WqSZ;zeW-FxsqL@Z&Os;=7<1#2MuS5~uHhCw;=bd2d<$
zayWX4%7Xv2T)h3at`M`U5PZEy%<+ngCFmEIbdE^)E^P0hWt`SnR~aJtq;#4O`so^1
zF5B1H9ItgEs^t>SV3A07MN1Nm-!Y=^+scq0eSaNd67)`AFYA2q&nXRY2YvG&VAy?x{g6bK?Wfvl81A+L7$Jv?E?&yagDW*CXM3SHjfqLnwV7)xG02-{Vft
zKep%yAEz^Hd`@svRT3<2g-D>h=;bz`V-~!VT;eo2Zi;g`0G1WDl)^u;n{RJOwntjmb;+!l-@n$Cu3tl+G
z>IjjI@SorfZe$uNWKtFXca%EtQsE)(G
zQIa0=N02vbwI1=g;m9H|_Dn;Z=rj}H=dDSdJ(1bS01I%O=m@86lz-t+4aJKbWnjXp=Zi4VK^uS+1)L
zS^!<=me)sT(krDH*!$~m@xK$&z2&!V^6y#rKI>*!xf+}#4o3_Vc0lx|{rbfp_D-~C
z_9EC#yHNa|(X7VFx9`&IN65x``c67xj}!Sc}4^`%|z|JYtNF7+5Vrypm{}^Mf5SE
zhkWd+b3}{L2P7=iq?d>)d%Mbi$>x8=X@AFDa?)h*&!K%D<^U`~o2Z80il7t!+vx2<
z{i^)F|O$6Wk(*(rt@mrIqRQdzAvjTF;2@W`
z|Jn37aZNk&<{_n+-I6r1WXQDUl^wYs-`y)HH&$xvXVcrW#4tdSbvHjcUmn5R$
zpO~HOma`?yH*583@ESAdK&)Gq;;_5$rZpMdN{pf%6xH0A2RGK{{V9KP-rkL%uz-U}
z7A0@P>L;vq;)J9aXPji-yAin`A&K?wMVb%}9*Z1^+F*NI61<^uIpm{!vqLt
z;`Fh+bGy#))q6^b+7hLeQ9}fMn<4kbA{Hrr`e
zAcMJ3L@JmB+6ye(ujVN%`SURcW^5ZnO+#q?g<~{OWYTSaY3k*xH
zC$C7!0L>HQlVWmE-44*IDK?yEx*utMT>qn5iGwsLvyjV&1aUh1YKSx%GDsvre9uwr
z*H}myu-b}wGqvh_bc@+jg5
zMXTZa-6GPs%OlyYt@)=ly^emXAUzeObM^M$`3WUYi(8J;(PSX11B_foempq)?A3`>|lP|QeQWo%snx@*?#gmVW4K1?(-X4e@2IgT
zX~YNX$Kqb`o1UpJrSx+w9Y3exbi=0$QZ
zE+04ZX_9uyy7Qb+iJLgojf&an$rOqH#0xm@7^Ul{v^U;XPUQ}>Ub;ttcCwk_DD39&)MfG*v
z`kLW>B%NgaBZKE)b_z*rkp9NG6)7stcZPL|*m-d;+xf0vKpr>yB~+43d;jgS%NaCg
zneC|oOyBHrV@4d)zf2-b-?@A23Z|bgBMrivwSUy$oM0i;Td`W*dfFqZ3cdLQiZRAn
zkO>MoFW<8|?r6&4IiC5=iw=G91$kW_Z}h<<(a)!=H(d(gSPcCs7%&OUz0*;qjDX%3
zuG!~kEUNCJx9^z+lYRj!KzYr$MB5h{{A_6l@1JVhs|6UnY0>v50%Hj-8}927i~+-p
zcwVHlC))mj8`bdqr?5{%q%hjn_^4^kw;@L~osDKJz*2)s)?L{T68&_zFmBRv6ruHY
zo&2M`k$N>PkAcK>N>)eYfSYWX&g2GT(a1$OMcI09*7#N2f0L5@r(|==f29OHa{USN
z<$!M`vYFEO3GiS;pQE`ho5JQw^Ph~lMqsW1#gM56HOU-LEo6$1G*hq?m6HEy-qY|!
zBxZ_OL89&F_P|%^=9Joe#}j>e)K(U9tZ^m42Wui=fgMX*22R)nxeRZ|@|8ZGM=MRc
z$7PMIFR=D!AIR&mz@wG_p0K7~Oxhv_vb=Bd+`;z1&v(2ZTQxf(MX?i=z#n7_>rtKI
zqN?8wOr0SW9wjcpAdAzGdLNzORb@m={dUp
z%Qu=b-ai^BO4r;HoD43@6ouYhi**sy^ke9}aE)d5Pe}W~uSHYMG=pIgShuk&EKcjS
zVm}s9U9qjGES8R4Shw1TZ+Gx$aCYuba~mY^^;M!-sIf%wxf50%sq$6HJk46@AzPhR
z@LYhq(+*vh=t|lPJkApKiY2f(Gt5t)>-209$&T;01HuAH8Uur3zR9ntI6Y0~55Cfp
z%`P=>#$A;;64@IrcE!^uDVk&JOlYVlHLiiU-wnfPML+dRq+A{~8t6o&Kg@q6YaRaX
zT6&GBoD($3Uj>`X$9QHeU+cFh@!3=bMK}53OkAism-ZBpyO=eOD8+}w-;L$ZgY$@$
zI!RK4Af;2~PCfSZ;;nx>?aL!be=0lVmW!C}hVL?Qy>^_Q<&YC{z8cC&*Z*zkU$@Sa
zt(K^7+z}sqP$`GYuTIZy^Nyo#O^P+=GAR~*aDvdz9+G9Z&@7EvhC#X2EvGUHlRncA
z4}!)8W)I<3G(JM+zlrA)uQ%u776)_1A>!;NLn>lGneDD<{Wk-=J@xb&j8neqERB5Y
zA47S&QKnVqB$zY_xr?xWr0GWtKF71J_3Z9IpHx180hwPD27r%)!C|j-c`iUKD$856^fKA!y+!qZ)2uW)Jk+@AFn_Wum&yDM?NINreSJpkLP
z&&lddlCL?pGWY|Ar47G!+E)UqaU7~lB5>N*i5#kyndD=-DoNn0z7eKn=Tn|kdRbow^$7~~(!
zN}V=!9b}{6p3#0mm(hP5YeyBw?d-m6&*|_yu(Cx=G1Ew=o~*Mq_DGKH*o1#P}u(OgjIog
zPX_EhY5SLb4%~xfsr=%w;fHT~7g?3W0WDl5WXxW``Y&@?
zAFJE(74a2FgJexI3Xt-o2w3rf!L&0t^Fq%g4g;beIfR8>7ryjfoKmy62rk;
zaV|`2;FS|ve@FYa`3953VJRx^=(ci6-+u=X=7XvWKhPP9mLf{(ga(UM>S-O;P_(|C
zX$;KY5Vg#kRy>dNgoQtlF{|J~0rYT#F8O;@<8HmTD0O*k<7JM8MMcY}0t?Sb(1IXQ
zz6Nc?=O?PhN(|tn0#&WXxUOd?~_#Wgnks!Ky2KCtdSJ)}>
zz9co)jn65aNfrUmZ)ryo*L;V%3#d1C^T86HOGx|_-Z9oD|2HIC6f{*OnIzn!nlTxE
z>+ycSbN=vom#F=q70|ww#^JqZq-^1M4pS>EPK#yOKj>$0aMS
zwh?P}87>&YSli4ZcG-^UmZD8l}^tQtCea8gwgQL;d<
z6EwmP9gOy}Nr*u>0lJR<+o^wo5ra=@zkx%ZM;p*uWKgHK
z`)F6LUH~PV&;18r>mf(Mkdh)j3fr$eig`z2kXwNj%hQ%xl
zj?y5q^j34yGl(NV*#5u80g^IHTN0I$Hs=Xo0SJR^GMakcma66x(74
z&-c6j^9_#gRto~zPTejS)L%~Y;h|@`p#>gh&<^T5?jWp8z(LXmylJbU$#`2+Q~YC?
z41(y3ekoe@HuK~o`o&vx;T32Ecj2yXsqAEBzGTiJ4XtZdkGd7M91BID6GcRX5dEH3
zvEuT;jo##`X42>VplzFi?lPR41OJhkD9fh(?TBX!-+|cWQIj;UobkCWoktQBy@?Cl@M{HezgBl0^J(D}!Xy5}
zoZ7DX&rWNX>&n_!U3|OqhdAUJMer^-9B-w2?0h)ngG20q7PPsT;?1bCrMJlYFTx=@
zWfXJepa^cy63O)yKmUFWe{;?4e~u(9
z@StHeiO~q)A_w`-CTl4+_THw<;
zFP=O>D{{+nIBH0Sd83L`->MhkL#fT1oYw-4qJ4N{UEs+FH%`mnmrvvH5%SKP@pN7N
zzC3DMt=Y8mx9LPTNE%H`pX%4AIm9!sk7w5BFneV|CvJ`QjA!z9c4tJ16(`^dm)=U4
zhO!>?+!*>OK_8+@g(i=-i?oM{373^%rNiGo6lt*e#v|K7VD=r@5sidH-3tqB=e#?
zilU-^bhsawykyI;LZb*|(i#x3V7f-(LZQa?zpTMq0{^qpwpmnQh6sk1u!Q1*O-eKb0c7_ZFy{D@H-Cs>E$wl<&+aLU#S(6I!GV
zHdf0tJJEuZd!qs6r5^!nLGO4yc~D~p+eV$7u^*PQnt``3G}GJgfm!B1#g^P_G%?4el=+S8=xnRqyr#Q(S;a7L=n7Wt`s2!
z$wY%oJSM~=dsB;()R^5dPMlJ$(;1%|Q`o_=n@eVZTGy>+#4%0srgkT)(Ys^L*J~^H
zVCGRYb8RBBa%TMrGK|?Ik!M4dpq<-CsnxlvNZ(@AU0Nl+c`euOVf3+t?1RREch|qS
z%LlV-)7f)3oyKwhJ#-GhM-lT#EoN1QeerY*Pcjd1ZOt3io@qS{Nmk^Xu3_|JjdW5G
z`y_jdE{4rJOl!}9-I=d>-aY;`@93a4YaO@CyBFT$D?Wt?s@*Z|_29>VAF9{^hOl(N
z@>Yqz36{RKkd-65{!OC0d=E#)(_X!uhc&g%`om!F@M(~ylzJ+C@HhN@@#KGpV@0UD
zvUkiwh@FSdT6V?hsWU?l@048|vUBXecqr22ge5ZPifFAf_trfKZb@{9Xbt2J#O16n
zyr;3&ddjYjLrp@&thf=?bAdvvmP3cJy+!`rDj
z(Y4mFc5z`6Y8kfcD0}q560ha8J5YC9M;sIuM8Vq{^%D1TksiF?#{2X1QKc$*QziV7
zrWGrM=itetyKo^(U8hq?@wKE=b_Ozz9!L#5?UgglaIXfU%WNX;N@pMzi9Hu1)<
zAL2u!5oImUgN67Mu=KTHvKeDOf2VcQDycpN;`ShQP*uHCg5jLJ5$7||w0yaaETNQ_
zi}sy^aQX2!uF0n5(vUaSU;2N0Wu_13PZ6ADN5Z-%bKO_O~3w{{+ccW#<)1{yL
zVe(@u`toE4ahnxkCtqELaMs{o5!UCV@tjnoXG$E8i}x#F=Wx
zFY(Zk>685a;h=bQ!vQ;=ANc3tzI^!>LF%7ukA3@F$Di)Y#|;Ao(PwI5uYzaq8~=$>
z2@5O-7xJ@p;T_s7I$MNQytmJX^md{4`(w2ad3vjcKjpg?3rix$Nv!v6|9jdd`qh2K
zCQky47-gUciLP01`CGhc*Ier8ZUI;=y#?yNAGbqvBbvgk2nM`?ny~1vnzxoWL26hL
z_f7N}qAgV4p3?!ZW!J-eMfFvKE23Q|9R;$)9wtltCI~rNUdxwOy61ejbw?-oBYk!_
zJu#>&iF-k;F@o%hJPc_=5bcsMAZ;`&w+3;8@0~p2;8TWMpnSsJcIL)uNGcqix!6#ThTdeKK$O=Q{n}D#0LgU5@6-ZQLoirHrqz(~Jn7
z^W+Id_6BapAe}x;fHyPNYgraYHxQ8@vho$wBT23JrCVv$I|6$Rj`k`^qY8w$bD|0r
zLCTR|?LV=#$q#Bon=acOf2$G}+Hs4{3spCBkn`tOYV>#q^^i{CmMy_R8GmlY$UaR<
z8ltv4?!5f1&(oG#u?F0%_3aC|8wHw>$zVZrCnS@u3k3`7@#Nx^+%Ic_77v7(N^+JZmdUHRd^|s#X-@(>PtK}=rA5Pdr`Xpbif2}!l
zBaizr!|`pEK#*OD9Z#c(=&q0+zFI#<^U7O;co`o6?*#hvrs^K~@qSWSKbyVZ@5i?j
z0~nq!Qa`A}<=TGi_8F#It#*fUSpt?nUnS_QJK)CvmTx00=U5Q?Muy$-3}F_2f2j{`
z0^e{evENcn0&3gwQr~y}T_cQl+5&|PoQ>mFTI0#fjewP*#c7iT}tYkM4C&?pH?}HPKxe6w~{8I
zwn%{EQk4X(>8R4b9Ohoz8#2$HljKP6L#7H}4QZIrXuIZq_AXYDAi0t{OuaYhERmhZ
zpLYdXsg%ojCiUI~w#qm~z_Ki7U&
zL7sN_wo`K~{;D>9|Kr*^>FS8yR4|Fu5h~gx7cqQom+*{JT!*4>R?l
zI{eK}fpP?5L3>`4#~>5`qY~_R!pO(}S@)WZYWMnHU&JECH$WO0z{aXiDPDl^(9Gy<
z<*qpF}@3)f`rxg)FtEi8Q<32f$xTzsC+ToEz%!s)3SezS2Nhkh}L49%D
zgN|=ANJfyb_j>Au&t`57&88kcnFg^Cm8j@OKzhf4yBK_Li2Zd=nYIsv+w{c0i}P9aC?Tg4
z8fsn-?DW_xOXy4flgnvPp{-+7+s%Ua;)gkMuLvD~Fnm`~XCH-1R=J%*N2!9_vrtJ*
zI>ly17SEwv)c&ELi_+{s0f+VJk^gO(x4z8o7>7G|m>s{&w%TvU&szF{-@@)(JdxE1
z@Mcfh%CZb`dMbvod>+fG)wjISHC|V$qVG^uGZv?A=M4Cmc9j8vg!tu
z_2>62LPyU&2`wn@NOf+?$23QHGR{hZoI#c=zZ{TRZ8E&;frSH=ehLml;>lY7hB+7K
z(=zY5$mUok`C#Uks`UHGJI`tlL~E#Ggo<}w=l3yKMV$m^+hNML63#RKZf!1QS*J8G
zTQtU?ENj#g${M$e@{q|69ccrNK=dqG7r6goRo2p*TqidrT@?o9@SsE>6X0c_taGA*tAsbDy<)OGd%1^y;9nigaq4N84kIUPS
zJ+V9lU8?77U2Q()hwryOs8J@}&aVeK1mq^blA@2QbA9Jw>ttjZ1(UpJ>HY=5c$%%u
zHUxTX-wDFl@7Jh$gNnRNiUuK=!qSwr)XQhX>42QU+g{kr+M*r&BVtJhc?EM2N8QEh
zyigzK>j-n5_M`~%C}-5~w||Z^K@fH>B&xC{uKq
zAg@o$jV2rd_lz;g3jhz`Q^J?OZ)YcZ8pD~mgT=Oexde$_vXD(~#aa4m44qHuqN{H?&Q(u+PY}IwDq5b+CtGGyl
zb_{vcCrJ&~Frc1^PVCF|LzAC1tf$)vSRf-CJArpC^X>`#Cu*4Cj1lx^ow)tau@e3W%Tp5WV$r6f7xWPp0_
z(kfsB%$7L?UG+KL4F^qi8r?4M^dwEIWSm;^qWvc!#%DLw!mrn@SRQl7P((N1|$~a!`=ADs-eA>CKY(Xwn488M0y3d
zV2>W>HDTAoMB9r;xD|`+=&XV?*(DNn*QG=@4`>L`hX!+^wmv>zi(_}AV|Tx!_@q;I
zRN@!HOIf|fc>g`GB&i0bKvMl~P{tJ~v*Y5pedEhX;+xy5OUZyt;geetspI%Vn;uaj
zW~%rCzm0VU$(ixHl;fM7)&=H+xUtP^)Qu$Bkup>S33PimdTLnz%2V}WHvezq-k{#!
zZg~to+#!8O_94D(xmmVBX8&G}7R%2HX~d4fi+mDsN4V8A_F
zch_T(Wu18c&D&==s&5RRrTc%K<(@+{%g`5SmWzhWvi)b+Uqm3EAiq|^hFF?s@(s)k
z*?oMT^~KcxV|HKUk=SE)EbG$)&avL?{S#=`ON#@2b3MoAnivHQJGLnX^X{5;j=oX$
z!_KqR_GHiJ2WS;+1lqyybC4>1`&>XRR{a;A0ZJS$v;OFoQze2(<5Pj}uCwib_qII>
z>l^089?%Y*!ah`n=n$*7fBEF5FY5*;0bi(DbjoSvf-n=!*!;%I7_hoYPM~s>)y+6u6N??_ev9)j>V~Gyi78L
zxrK2FzkXmzw1Zws(`*jZ+$W9Kq4Y{5aW%|F*2U*xxJi+JKlzzoiqkEm$a;#f_a;Om
z(}jJH_a-b02ZwB!;{=D$gkXA=4*t{wE~
zC&Po8{&VPjq`6CUhc%;$Qg0AwngqSw)GN5)t^J{H-XJ+d*n8xRZ;38KPrteQyPTx+
z(3m+La_ne>rNAxUL6rk0c%x2d5mrsP)eY+9mb*v~yg21Eiap`&bCNp7_Q3`{_(tvX
zgynRasO{W7ykE2Q67)EBrgA2{HT2zaeLX|py|$8CuP3TC(8H9kNxMJgi{$Xf8xHc0
z%&VO1L3+F$K6e2YqGMz)vtT&M?m(yC*`|-v*4eIF5nXu-qqQ!D7t4QpLv)H?o*nSM
z66Z`?`lV=35%`&_)L(+$YDQ!cA`9{DepY7~5{DVLgMvQKKx`k$ze(_2f@??BJ_$Hv
z&HXc-cBgfVs2w6*+hvo%4KRm`3_hp#lhkji7+r$)%4
zB^eJkV0LUJy*d{fv7@6?avQb??@_%Y
z*%f_ni#KZIe~74_U2A*PLRr9=O~b_zu(j~@2>mgBxNw+|ea{Wun`RyIXR21lrEZ`6
zaf<5~+?EVqrzPD~Xh$WmJDEfSJ0@9&QKhjhMnH{=(WuY5hxgBWr{1_M&#hOy*D6F;
zaoi^@ipvCq`xV2X;SKKvE{&2OPjXkEv
z;A~40)Uo(PJH(;FHnQce9VdB2{hPL_ppi^oO1pKCYuSjVr&;4nu{TH2itr|6G;h|)
zKU5Br5b?q6Ru)~DW{2D|nnklEoLaYo?IL9ifx5U%1G^aik|b}^ppW2sl|<{C1el=){tux8dm+V>dn6U!n>X#`(Rqt`hcU8&
zd2ud!3;DWlpB-WF57(Z#&$sr3d8>yH+IYXI(o;N9slsaLr$*DwL#WNh?ZJVE;pvjd
z55&A&7rlA^Uq
zCq>w0G}JomlW;ml^hv0a`;`x#KciI=j|go)i;VFtY+lSS2~Q*_4(8MjZ!^tn7GeN6
zJ>)avJ><{iJ(TNTuIIm0;f7r5vs`bjUunBRR=a
zw_GFxCJC$Wd#uhMOLYT2R@!}N%?#G-KShh0Ro4))B2(pQ
z2mfzY@PTgyhp__H@M9}bfcJwdsBiVJVBXz)1^np^JFP%fXqD?vu=!u1`Jeys`L7x>
z|7rg>^Z)<51NBV<^B@1i9f19j?ZDE5w1T;x4&4C``A&y_Ck9tAHBO_um!JXi3_bt8
z!jI-V)k{BQ{hfslVZgV9;>g=i(|xFd=&yk|{|r^ac>2V$V=In4%dPxu&+Sh#i3WZj
zl31W^MiWOrqj$Wj7@hVoK}?AioXHCXF?o$(I=)zrweQAp5h9EwH*l$D{rmmDB<#p5dnrwmJVF5W!oc_qa1^2NhWz(Zi%I>32$bdRz
z1Xb9rRtia~s@tMg>T*?8KSQn5zo;VbK}AKY@sPU?Ku4>2`{0{a(gQ=4p|uxZdtCp-
zwMUjcdiv4XkLj#biP5B#2kC4bT4&EXTXCJvmQ#m0vynit4xBY}JO9ob&cA=a{z3|(K
zIMs^NDhd13#_go&Yn%o7TS>M-ek(Vwa$0e^o00PfPCTo~iBCDhWwT;Tk|R&zZVgFL
zjlIHC%x*Zu+sJml>H)te)a>G%57phms`E)2C`2~Si_s+=A|wQ0t0-@R-xV{cboNBw
zZWHtSAE_1KTydO@Mb;YF3fVaE_Y&o$`WK{E_+_hpJ+iKTJARPQ+^W)xz;xgUJTcC*
zG2mrn%|dO!RLayb8L~yvd}w7;YM4!n*NNBfM5=d34XVnq(cDbjl4P(z5zidfGtHIhO{^^%k)
z?dcGcm%~5yrbPY-id~|)uiDLH%qyi>9Yud{7(X1iC5bFwAZk|>up(_~b|uwZ>q>YW
z(bmU*OdbuQECIQ;JWJ4cuj_t{dej!87~Bn39fYs;d;$J(|zF)@qWoFmv5<(80;BXjRuA^ZmK=
z7VVj;E->aSA{!*!_iWK?n^uF)Lnm>Ou8I@(DV?xDU^#KF=wm+oLXEvV8DqlkJhtSjD`tjRT&Vo7ipGm2o3XfMc6oM;LK=Q~u_sq~vYp
zvWc1vod@krsLDt8G!GiW;1l8v2{tIbbpI;CcHRF7VbW%(MJlHN02goP8dVgzVK0`y6%%W;XWS;iLy&6NGd=krlY7oz?pJ~5MBmq
zA9yuyzdg9@+bGK9+i}$CK_=f(XWJ!s6q@vJK0@=L8U02i9L#x$ekH6RSo{XCNS|Gc
zSgKr{7^mGO1Xn3z9FHgxZc~ydvPbsa?|?JiL?*2;hc
zCM^YBm25L1M3!0`Y=IF|`Ms~tnE~wKd++P_hcYwgoX@#FPuJ&qd|%eie6=8=!o|H3
zcy>`afk!o0zBA{Yn)HOBZfecC16oSLVD6%5ZJeUAi&Lf;II7%;DnaVboCBXaMW>nf
zhz~`05NGr;;_V)?4$h}tqq4qv4O01(hpbt^Kn=~{^vgow#iiOa*6*m1pKIo*a`6NmY=Ph&^Ml-j1wi-RtwAiKQU}E-m9BSoGeOS;#Xf`4__QHsl|E
z;WQVak7mL)^*p2K`z>Z!fr??@+Nzd<=a*%$b3p+OL{ac5^;GgeQGelua_{ncYNa?U
zU|Fy}crMTmCR+pPi9qAU%8&uS#wu%&8o9W`+
z?p!d+{bITTqf3H-0l4h}L}@gGn-=gSU2r@wRcdFwGtt6V(>49Nj$rG*o8b+#Rr#L<
ziVchCz^^THsY(juq!gz88*Z*Ao4{$}c6vkyG3l5zNB?^Hi24&a?U`+ZJnu0wPUz9h
z|4lmNHlAc{(lAs?lFs30f2UBn8!^I=FKcIQ|FIS+X%Nu+Nkf&!tCUU~L_--S{BdgU
zvxddv38;U^|(4H^`gY>!k15ABX6qXK@#XbE}8;^sxhd?AG&bmT+jWdf!D*Ko#k&`R$x>^HDi^
z>OSO;)e3kjrTD;+r)O3pR-n7DS#JfT8ro^^(oRH-4B4&I5e-G{L?6TnWXN5aix@@N
zPT>Jg7d61Hf?X8xeu16^VgmzfMp~n1kmtI7P(ckv)1=qXnK%`(CN3b#&|DnaoGwXstl~#O3tM;Lk_&gdy}>S$_3a&n}Xr8XNPL&~^B=ejrO_Ajb}v8Qn9{
zoD=Bfxj6|vGG%L#nitVK5jf0BI=iXAf&Mu});shpGIM%4^^ST9)cT~PWa=CIXRL3v
zTJmjD@1(vhe)T`=TUTRXex;R*jB7R{qgaIp$^I_c-kq>Jj?ajQ*E`J6XhLCIMsIar
zZ^S$s&RO73e4sma!*F=6O$_4p!Ga4LXEt_ml5SZDGG*Kp@tKsglz35L)?RSqj4-mH
zV}?*U(D)jxph>CEho2E(aYVbt!@dbn*CXMuXd}af$&|?$u#X}>hG{nWtTOnD^)$}V
zW(>2Zjp>n1ZWSrc0-+&vhf84=BI2dh1Rky1^LtyB2DU!C!&@8u8k1a;bPFVUaXl$%
zKBHF!dPUGnl)|FfLzy&kama|5qKVjyGfF(j{Lg26*?$I7grVW)MEEJ>j4#6ni#mZp
zfjx!j
zy@zLObGBfv$TMn~J@kIrjOB8c&$8cu*4ZkrVsGj?eG}f&i)HgyXI>&C&P%8FTp;Yk
zFFx`6x!DL6{pLPDcTmOmnD>yFv^k4Rw!}M(Ec)TK_KU7Z|O(dmyg}G+Mtf
zMoRM0Rz~G|0;9QltPRqzp0MeHWD4MGK4{&cg0;Ub>|$eF{1=2kr<2d|BfP1-y2obw
zQ7?6SlKQC6X9kfs(iHID)Jl~KT~)1mj}IXilzIbKSPe^O>yhLhU{RAwHi%(l5pfy(?`
zb`o-dQ^ykBM8hW7?4P14Rl2V&3?&qOdCWpo>j?eXR58bHIRMTLSyYg4&I9Ol@L(He
zW?jl$01wTQ4Lo{sA3EJUpHf1no0Et6Sx9}x*`eD6>>om>!_y
zsXDPf-al@8FCOdJb&U;)WaM*CO4*N9nM--s?p;4Rf!D`3kk_hw@y;f{^%XICjHXdBWILl%8Ik%-
z_CP$NA?{_DDn)MXN8Z$}^jGm?u0rRZ^iJ{?!5(2~*k}_w!));fm`7yax4b8u8xikP
z(?w+U)$c#`W;!CLo0aTK{&*a8j^OX&BgCebq8jr@oS3K
z?->_KCiZhsME3$8LPk-(ZaGC%lNUhp_g#P#74EOfY5i}X(#T&U%-iDV*Pe!s1*rn7
zU*FydUxBgj1$jZUo}rW=_Mt1GjL;|O=@S-;{6)3L@|;dK9CHy)*V$z=;Z;3>v6^+ellFe`;*t^U%{=%{&)wlCty!qN#A>7Q;Nk_}
zTKlRX^ARQrwMOsX4Gaxnj@(-xAMQp*4A4|&+6$0hz{#(aO=T6bM}85NLB4uvwTT)@
zw!}O>H5HOZw>M3}dzhpF%*Q?KEF>I8>=2T)b&)*NxgH?C@w^;$?ub|DK9=b-Gr}3_
zyeU^F>A8{x^10Qg%V&P&U*Gb~>OGbFKc4d?Q6bHHvl)@t2ALU>4RjFr;JY=ZY;(!c
zyGlOGi40Ztp
ziAC^pN7m^zl?K9*#@^%3ul3{6a}(DRqBQ!zy}pL`<07lo0aRp{D&qlGsV^q?58z?N
zv#PU!VMz#~~NmeSd2+~T1R%K{-*rhVb5d$$8D_MRMIS;h{V&qn?T^B&9
zq&~?k)Fa%hgxBVt(=%X)boK-|QrzPqOkP862yWtXT8}~#Fj5gUPO&!`!$4K}q1%X}
z8f3K#{b83P{2ojLBIiR!46u>Kx?dkm<@-KT071Jo9AcGKQx$l><
z&qHZcCIS-Gj1vTz0Gfx};eG29vz1l&V4OKYjX>v(n`
z$BIKeF@7=1#s}N)pp~s7tcr2d=${k50Ym7{A6nJyq)@0Q)RQfLJ>Q~U7N?1(HbFt(t+ll*1w+^XnoGa
zpSC_>%#U0DKDwuMFZENxxHVNwr{9k-NqAKuy~%!(#&p+?pC9q)59w;x9v5)2)*rLs
z+3qSm^3Yb>~&e(3-PtUB;
zdXQLBG8|gydJ^JUpu^awU5J{T{RW0spDPy*xP3
z+WGK4>O>|@?;g!$?c&9DnI)9+UEUyTObl{^n6}dBt*@Uct14g!HFSa#iV^h%Grx7?
zTQ_k^lV%ko-$y=ya&Ov8ut1TXE{&*aJ4r2wcmubW^hY+H&${5rgpE$uu4M6PCU1Gy
zcQh72!P8Axfj5s0>}z`8PM{@hLp3DWD}lpHcu2^ND4ubfN&UKW2?04q(is`LO7V;@
zZj`bpIt$_RvWncxIOZL_q9*xSfi)=)J
zG)NVsmc;M2c#C&^+rVUQUqDgnWVX
zCWL0nedr%cO4GlkdD=~~bn(XP`xsR;i&y`3tTaHy>RI%5dTXM6iQk_m)g@iAp1c*3
zJVdfK}^=-@Bj_k
zk1@ST*s5D+G~KW9(tJ@1GtQEv-#bnbIBqm!&4hX3Np<=)5mc=6+rY_RJ>FjEB#CSG
z#0C*O9MWD%ei1iCFv$d=CFfkD>yMqm(15p^Uc{-N(-sw#L0%c!eIX{B=b5oPJrWi#
zp>ff92A`cNy2U0AhOcpijC@L7)8gvF%~*ly3I$q9+xlmUy$QGEo`kJkfy#iB71Iz~
zyF&7Q1zMjlsfqT6ZuYRiIwiZy>we!7MPu9-y~O&M^}OF>sarkbeorY`G0En*hvL*A
zVLk!$v$Ws8E^dZxM_W3|)Ud7~#~4Bg$%p}@cq(K*!J1n<zV*Rbp?~Uq}DP}r!3BGKMkd$pDaPPQ*>&5HW
zqsl?^0SV85a14sC9;SJ(IaNUGSvR4d%+h1^Bip&;=jz>Z@VS8B+zvU2dh1^LIxu;h
zrD4;Iuft{C)JEYOFvN`7Ds*D{CSj&L4fqI4`;&_a?%#vbx*&UUVlA_|
zN$YVcMS~*8&S6z+ILXe98BDwS0j=x^SOLmOcJGfoc#@sC_C8FP?AxyEnP17O>r$oi
z#7&`F@{RprSrRGkkF4jsI2;;#s|q^V9q=)(No?%zyF=G`WSH8W)_4O>L)D>^xdKs-Vqx^e76Go@URRXWZ*;}kfW-d$?*I^J4IE&=dd+x4*U&i
zt&gKccg>~aKiA?=-}lsFw%9nx_q~+$avX9zaa4&@?GBfr8=LmE8;KTWg$`tS=WRu?jJ_Hx6
z>3Z@XFbg~L9+=!qtYN}*Z`z>(TRd#7^KcjJ-Q>%nc`U0)aO;KkA85s&6C1xSx)rv9
zBy824fP^i57rDT9tOAm_+x(h`uEJ`o8V-9i>_=Y@eTxUBh<(PoB2O&5Xjx%*C?DSX
z9V!wbMjKKNvjCl@)tf>m;;d~wXSt+_v)=kG+R`XYVQnY@1H+yr6Qj4_ocO(y3Ph!pX}@1c6D8anP`VyT^9jgfO#w|>X?7p5kQ{B
zr`122kqWU<=li;QK1_ktvN$K=81?1^U9bNs9dXm?PG*UCmBrhSP501SX5FOSNSMFC
z>W4&nt`5JZxi|XT-MZ_J8e3`HWBA4geV+$t*!{?EHXqRu`BE6Gry3&)4p}x}rIwQt+KM4*@PtsGn&dfhdGJ0Sf4>j#P
z9(Y1Fc6~`;&FYaE7+AH7FZ_7b{-2qFrszY|YB74Sdj#bO9ylKG$o8D3MKyGe+B^bI
zy@}Px6dmN%HH5Gz0QoOP0Z{C*Wc9R}m-5;5&_M@TUoS#_LnV*1e)Dw>n4J&NDI5F-
z{HPGb
z%1heQW5{-^t56{drGLAc&H_pPrnPb#609tYw+!I4)nhC+%Wy6Vxkq|+YOqT^iPQ5P
zs;M(wK12vC{U>LAs#I|>U$06Hwpx7Lk^I6O`0j(>Q}W^fP&b^Lsj6io*652N%!@KJ0MM3H>}|Qj)@)p3l?lN@sE-C#V|VsO~&2t}G+DZN~TK{IQQD
z9r%6!l6(;G{d24T7~10<>?DZ^5nYI01U8-joM%xD&7waB_%Pyo>;IcY85DbS0<=hU
zNY&=3LKykDE}j136TGwMd@GhTN-sCz_g0zEKcIb~-h+8ZX#^M{bq}MHap*FHXu)yvsEQV^QRX?$8NUp)-JKH
z-Pzzp#T%~u&4zFJPhW_(T}~XINRe*E(ap~Aw+%-uwl7}5FV0fUG*>|uSK{b2d5dcr
zoP*ys7zdljX-k8qxx%uzf}E0534Do17q=eh=R#(<6y-@kd1;}n$}=hVoRwGk?PQyHxpHe&*8S2soL2bR0_r3+-lMg
zXCMh7(XM}ZAm+Lz;}<+$xQ}8`lH?ROg=dSsnG|6?^0ZVZT++c7lq0GT5qN(2cn9f!
z$rj`zE+jiRo!QtiFJteZH^6e~k81ZAQ=g8nHgndY%6_xa2fdIm-rG8R9Nlv|zc5oZ
zkw-N&*uv!VBpThj{Fw?8&dckGa(LxP;-%cZk@>us%(?Ogas`gqjNsa5TyU(?O?mI@zd%%Rv`#;dTL_ar$7?I8sK!XDv#V+d0lPYsgch{24a>R{zv;W
zSd|&$QB9*YL_>F$s2qp^X$G$|bH>+KL>pZzq6_ie=oF)gW)meX3gS4ME(b`7-6}Q^*qgWbo42##^4eT++L_OAoHK$pA
zEGo2#nN%!)+K*n
z_V9^3-VxEP*IbzB(kzYE2PtA*LFVzKdBRTYf&Bj|%_#caI$LMt;2YAM(=>)ep;joZ
zx)}LL|BP(N&6CDWU))Q75?Lc0c3PG*{~LqtQ!)CS80nzsK|XP1bfYZj
zj?Iz)TjTs_RPmmlFh17VE~i~qQ+&k2&tExS`)JTKXZS$_dQ|LvTc^Hc*Ww%PC4Ihw
zE744ei?lnZ&^PQsmCsay9Q~40EBU|De
zC-bn4A}-CX9;X-Vz*RYHfmDnYz7nhJXcW$vD4S%(@KuCKIRIW3cFa6ySZ|BfpHeFiF>U
z!ziogIcOx?qJU^exhcqwYGQd&;P62BqZ}2&fu+9#q8P%Td*cT#M1?HzTjHeZMLm7=
zAnsrC
zYf;1}N%Ad}(dS7VVYV6tMO5sRdc+xBi}J?goW*&JY|b9!+DTEc9Q4kSY+aIwQI8pR
z5PZ(v^)1P3(G@f!_{6OicG4(Q{r0HF%#Jo5^48R=bb9^&r)gHz|4maw9MN>uP1MZ#
zn+v%H$e{)u^nS7=5Ix8vWtr9?WCsOKtx4W;j7Gp)9#&KV`O`h;`sczpKK3!9wq)xyl3}@p*?Y9h@ZyjA}UcY
zj4@(Ywx&;JmiXH8{`Xs!==2CgcuKpfXtETsGlCmW(itQYfyn~M(`4}kpqzYa-0rna
zB4rutRqgD=J{O-ZTAQ!Kl84xObx+(}z+0WlH-=Gc3VeKos<-Jni&LRhHRdghJfdvI
zV^ni8(!~b9o!SKd3C7#KYlnn=1v@qCbJkdYW;QqhS>6bn9`w9K)=k){L)+DKg4N?x
z-XV(wU_U$o4Ud
z(*yQIJf}#nVR2a8?nU>HXaQMjw&r{+S+t3Y;5(iE-Mye(>cNU(H0Bg74_oO!0>0H1
z8lnNv%1pa)6Dnh1
z6&iEr%L?(?8{@rMs3tV-;h0&haV5zti{BX6ph2V!efIjXGJh-yfYXg_siRhb$_2zI
zdVeiAg#Z1Bq@vxA+=|u;Em6WUD_Uh*?5&tX-^7(MJ(#PA_m&qwrfHH{3WdE<^UJ*D
zwWc+f$uhLdhzgv&1X=+?mdSl98T7s;r7>YxV;a;K`wt&Zj
z#@{cWvNa_t1M+D^!sMPv)b=7Jjd%=p(`pVo7~ZdKsLMprdf@J`lIDtp`AWSs^01k@
zbH0*h$YnQk-E&lbc!M;4tmZ8u=q|H4@|No+hqp*QyMGON%Tp&VBg*}~G%ZHZD%as!LKkzxapkxlWJte4F`iY`X{jiaDavI}CZrp~&JdE|Bj
z^$*s*P-MkGYQQdsy_)wxexVq7;PLUEsj$&OOI7$aM{bE|t5UFR(@1;C^B4EZ3v=4YdKY6FiHafE+w}wKZAnb(jeaxG<3NTs#RyCJNMsT9)B7*UGRpRM
z^wYf~MuP~)sKUd~H6yEHV}mhN;CTF!yZr7zV`vjYhgy?!(0<(Zz6zrq3Tr^TMnKNO
zw4G$_s|~qY*~{B=
z+SlG4xF$zx8I{oRD?OXu44F)gEKpG5@YB|H*-q#W$dFo9JQsXG!XKh@p5@Abhe_FJ
zn&rSClK9&d%A?w!MmR()C(W?yAH6bVIN7kir@Av`+KS{n-tJOq)Yb=a0$JETyAPM|{dZ3Si05C%oS=i%p9b%E8S
z`a4XGI+%64?h)|
zNt}T0jXua1q0Yr-#i(!(tx4wjjyd;dmxB;t@C4b3>T?tP=rHw%A7@pCZEaC;QtVy*
zIgx0;>gnC9fX9X`xNYem~>WfJ7+CgS6gf-DziDO=_{`%_{#$O0Ly@bP)~N+<`7KNbRG7@s+`w}u^pge2fo
zYtrunqao>K)H7;jmMd@~rfY%6O4cFwD#|$CI;^adQA>Auw^DsH0{i(BYHw=lujW`vRh;f_*vPyM*_Yu>mMrel
z$QKon<$cZtXmCt^@JHvh7O%uQkSAt>0|wD(731Vyl}5H6__PSRIk^h;ZwGgjS
zfAaxY35PJBaQ%b_Si}Wlkz6XOk<6;r>u!ed@bi+?2#?1B76Gs|=YWOH7N~R&>v+05
z!=5xG8?x**;+ZhY2RvoLyrkCbEO@I&r^w1DT|&Yigg>iQw_qRqS;(w^p#9E7d%6Yp
zzd@@6d5oW-D7$E~%~
zkY(lsQYg45W;CVjZsDshjOF9Uz=F`$5cDJBMYL(S`so_b5y%%|F`SGJ)k_rFBVkg$3p%z&Pwb6H3GD8}w7OHe
z{J4{k`LSNo*{{34gRB;|vqs89B@7pdnwsm38f1|YCAQ=Y6+>}J-m5Yaii=pOVkj<#
zjUT^+m{VBUqef;D7l>KnHPp1sXVIp_Pn2KHyu^I2j8^e^iB>0cF-R+|wZnA^CTZ*;^%WN5T}#o){{(gI}ugWrdYhKse@kzl9iytTG@;}*uOo9
zWPj`Oc4nuvu4|F_N6OX9cio7_g*<5Hcnjj?oW|g5@*U4e5~L{w_S4y{1%eDOjJ=6
zfi%0#K>Qz{;m7-IP5YC>60ixt=KJR&*p^#g3`dw_Z;qYl&{i{<4|xR>Q76N+R@SX8VJ%@#I!L!pDSI!_1L^B
z=@PEZlhyKam#P|TnOh%~agg-PlwF6PYm;_j
zE5;!Du%&b=;=V_IL90CR^Mg|CsKmddN5!#tMHj0_IKl<5md~EpTqBf`~p~6(&oOQ8>MbzNZ*{Qv7{y3K4;yfe3tRpKKRW-97LVMqvUd
ztY4XKe(9Xeb2-YG>42o1?(wGP?5!vRU2nJeBYEye#oY})O;TD#C;6&6P%dYb2dFz#b3b*^c;`BRgvO0*DU+yZ>CRS9EdS}-
zcilj&B74F#&y~E!^sDTl*?LPmEG&DO+z<)u81Qhy>o#~lx&K{(Ecl;mci2Az?UpA|
zTht2m6Ya6KqATxj>wcLqYICpi{hH+Ck=A_u$X;iAbAacqYToI#B?G$v``@}XUumyQ)D3uT~3RU7|$6j6lH
zS8W$7Wr+JqDPBpGYsesi&IOU4Q?IMr;x4;_fOu_ZH~+J?H^0y*H`rE!b<5b{&jzgrBkD4u0Nn#O%sO
zAIvj`p5kWa>DPA5@YbFi&*G<3xS3C1!8|2hJ%D^O(V@6lCoJ1<-whiNuttggcWI{>
zb$M9*!(mk;TU}L-6E-?RLn3P)v#{YaU5Dpxh9t2oxJ4C^f?l;D?>-ND_wlHmo*q<{
zv%OJO>SNZ?71}$5Vggi^dfnQd-6G8p$q^KhN7!2wcg|lFIQ@daTovst)yPIWfmq}8
z97r2qJrPk2VJ6oXVKhEl5KD<12kWp-vI?Xmz1$-YL@s#Uujw-j>JZq~>jdtj0?Jmb
z60HLeos+H@4&Gj`dtR^FDp>nA1zDFADGnr9m6L_bBDC?_I}yRyd7E0UeIQ$m#TiEY
z!dvftAXYh<;Vi+oQQ!L8D>z+wKMW0lPwClk4l$sy1%Mb$@*4aTThVD#yk@qZ(
zw0X>t`Zc$M3xiQ{tnOOGLux|JGY+9|ib(9aq4a5Zr13#So}?7NO#80>A+{3hYoF#l
zib(V*xbXpBD^O}9rgW*rP4lbP(yNpkCr{GbV9Y}Pe-emqXf%PG?q=(%Iu2D7YtD&OLy__u=GdwBqPIR}#)LELA?APGT
zPnRu=UsJXR_mzEHRXTsQw98fLnaKO5XqY`0Xg!^-rJCkPGJthG0{g-+VFS2OeavHs
zz7>$Mf)OYekb|P^9sMDba-C5jn5+m?-5S|s8pWu*8nwER5XXuQ(+L|oF$7F*ck3Y=ak`uvh<_l9c75#x;ERtk4<}12vnUxVUOGkbLTSVHF9E0U+x+Tl
zANdb$eyPz^9Se4Ck`u#@6WWhsHO=!xa8L3rI?Yopup-nK$3l|eS%lXg0yr5&UaGZP_8UHv*;Z1>A}fhcXM>SmF(J6gLwb!2y+eu7;S;KWkxE%3iE
zy$?v#&HHgmp#8FRv9rwKywSz1L$HTOVm<5sc<;%PPi=on`SkbCNqZ4Gr77BV#F8#7sdn=}4j=I8TEGQTjDbZnPdU%JBa
zDv!R=>}hTM`;At+C@VE?QT9JoX6&cxfAPfn)rqxw?4y}yU5L(*)?V{}kqm`8j~SBp
zZYIly@+Qsri1v2c2KWq=hj|s7~2Gyf+CiNlD~#YMKy0lIh?E_4|$lqwGAT@?Hgc&
zWmKfj`X;1QdTRqBw7cK8ulM_mh|>P02yI|-Gnz@V^jqb0hj!ohH1sX6F6SQ8&+5w;
z%swGKK^DmF_x<(0Ctw^f4!}RWH>8Xrr=XdAMA{HF-MB^doqv2&XY9R;
zTmtC1IdssP6E0+3=rMNCc`qG1L01Y9N8D>(Q@h+xe?V<@oqef(f;^i@jAP#m(98}Uvu-EI;2m@GXL?$`DrR01r
zdDNtxAu`>c&LEPqiFX0psy^kZWg_x)Rum~+h*BXLWwwZnouxh{G*rfO-TytJ>e$k}
z1Xo5z1@RebIc2f6&tw@zJTeTPw5~MvH-$^#k&_~e-w!!}n|jdh&rZ>q9%26Nl={&!
z%LKPxmBgct-`3_{5t77-vzOZGEfZGyvzVAwjg3*(J*}tNEJfF_%8sb@1sTtT9E;l+
z6=cVe^tJ~hU;+lVH*Hl0jf^xdl1{H=RSNv)Q|HgMR*u}iWxz771HON54I~b#2rwA>
zo4;i@Ft2ec-J_OA+NJ6&aUsxvFrTnz*OyO$e5Qntlncm`X`&<%x*zJHrbm7#pG2oE
z#vaISzmy|IqeACx7)Am3b>BJTOU;Fw_eW_({FN0^)>LZF6+*hB*gw+80?1i&KAU$M
zQE>Gs<6ZFGqPAU-tIpwXr>I41_F*)SMqNJX+PqZmvLh=S?tF%gP#&_3>Sv+XW{S~a
z(o~RQ)QOWML$SIkTw*426G^f%mpiej#D)QU}druvEqu~
zJKSw+qd7=}SCBBUk-rJ4sP!>e%eKyX4?7-SVOkfnY`yhP^2N742HpASjX>5JYrClK
zXL3X9%fqQ{HNc5
zwHxitWPeNw21mUqlf~n`Nv7WeyH^J6UU;;;TUTw9JX?h8iAYg8ZMd!qvL}(g>ebEK
zMSiS+1npM*=kg{by42{s&^d&(B}Wi9vG^oOht!r7okx5PNTao>8^I40|1X(O@z_=p(rmi>W&Wn&{G86}3DR^eAezQhhP(w(?;S_Vm=CEv^
zk%Ltz#3I9~V-uDY#D{iY>nbE`kx|}#JzeuwL_$K@`~<2wO5^7JJ4JtDUJ!dn)Iy4^
ztzCn+yWKNKl1H?5>jG`nqxhQ|OZ!t>`>3V2zgV(CkSqh*#aF`4{Nu-aqU=rjJ<5?+
z!^dA!xr8>=Pyzf1Xj#`(dSzNL_?dkjH*^c)=~{3QAC&^Gg+$`LHS0%
z!H&F1s9d$R^Ym*j29x!JZ~=Hoix_F1;>2hMZRVv>)?Af=A8Q`|)n9Vb$~CIN#$vNnPnbCy)EJV$Y-S
zQ$``Ce-C23c+X&Nk18adJ_X^^X8Yxw>E*dWc%RVtz@odDAx9g~9IdFinVneCsu!Gt
zjH9&!j3c!Jjl;Er>=s0NTZu-!@MI{)SAMuGLi&cvB)PJPc*JRp&!sxRa3R}1=;I^)$5rMMfqyLmW}
zrR_p!C(r`u4y-9?pHA^n3oM=c#NogX3bBg^9f$?O*+dc~q$6%dx=}G{EX_pBbeF20
zwBt0#l3GnWRKn#SO^
zfi7VZyi|%P$QN&8ln6oNdXd~ZNZ^2=io0_CcNGiNO42xq7Txn+Zq=>BCtzn9(tZtB
zQdYGeKL!jfp#_=&kFjWM%dhVop!We6C9$!ox&CzptbX!~AIx8Ux;Dz8)}bCQ(?!po
z#dwTkRdJoDRD{_=P3v4iPIwrJ_K>$CfSiH$%Nu?h5&sa7P2gWBkNEBB44Jti!L_C`
zI3)gb-fz{ozWjSJgheIl>tIPo>|0^lHBMirk~P?j>DOR&YvZP$%~doGoOHKmZ7l=G
zjEjGbn-8=;(u>cYC92L#cq2umfsa~BKJzHYyBXn?0qqNU!qNsoz~@5rWIy6S!ZOKU9pFGYS8PDC1b#N=$+VcVG>jn$
zGDN;0=MT7K%xhhUzl%)9(ew>oYaZX8z}XB<#W)=QKVghQv@SP{p+gjd2W=fk8F>5N
z(hJA#Qr1tE*w|9k5jKj+S}z1NL+N|bOM&nA<@L5nS3NHWu96j6uhJ>}(d)34S^sh!
zRypM8BHNI0!)jW;!KZshb~)rA8r`2h+xXY($Q?%n|6t!8dN%r`OGqUvRc)#Yn5pbt
zT(5UEZof|TqN9*$ejBeJ$i&?_e#2_&VsW;16Ab
zNm&1L@7j7DSp|645a0L2tDY8JLb0NUTQzR*wb@2g4#$oejr{CZ|L0NOw2j`lpKEW&
z_3v1F1AO1nn^zshURQ+t9F4B)|6+Fz^L;~ng=ANkAXS7r{3+FsezelNwf4_PERk$~
zy_=bcEE(XOjsHt8c^!hB!Tb2V?d5NmzlgtVsXdDwyLZI-1`Jf7qef$}2=&XOr68D)!St0<@2
z$b&aEv@5}F^g%!7HmSR={e;`#t{!fKch;sXADKyKD{-5g!*ff(ZFKEl;7Ur)yYrDh
zL)=EKw)P7`4Dz8rJ96dh0RE
zspF_=_;!FQ1CRV{M73y`B$AXO!wMEXVw!PmDr*s3M(-={eILmU-dgukItQ_n
zcwU^OploqJqNKv7w#Sdmq-@=oR4?a+r>iZDEI(c@c&p8F6!s#!z)-Z4+`-J&1i7aN
zC3I&Et%Ajv&7;T!QvEG}usJ3{Lf0P&Ieja7=AK7aBxy2MITCp2X>$*MBt^b-9XN%`
zAyq7BVL~rvWih)=QW~To&
z?bi}D$f%t|(T)yeYfJ+7LzF?%jQ1;!dQCG>1E^l83dHB^T61)L{3*);wq7cTzPE@z
znz{Xf8LKrw=B!|A6n8x6+yB!Za8F^s$X9+yy+j`U5Z_+9hbI}9RbzvkggA1Hs%ZxJ
zkA(Gzk=^eSw#xI4(k~K?8&6O85PY^SoV5hYBi}gC=kEPJma|gJSzvvXQ;qbYN9mor
z2`S{SbRVrVx`+DBdi`0;5wGd$*PWL3_eqDKC@ZS+O_71ne{0jCC-lx%Rz#$Q9l&X(
zaeTv9g>z1`!<=9=<^kEq;xLna$0D?hv5O%UdE#{Ym9e&qdy$QBIf}9qg!s-#=xy?Y
zs5?+Ze(NMd-yeGg$(PK0z>)=|);&rPt-p|=F6qX8OMf+TsFf!96^nhder^V$AXc3w
zZSE)SMgHgQk?dHGIvf7>s(!Y;q5pY%MBlM)`f@&&+UvIV)Ye13y2$W7T0}@Sa=RFt
zSHzX7(iHnt8?rU0XwB^bUp9@x*rjazM~?-leO=!bz}ky(W#!kj@i)Z?K?#V23%km+|xUyEPb$XijY$yx=*xFA(ea~a?BDZ9(Sp&~u3^GA$
z*5tHgU(OzHhc>)UFuB&*Wg#BDFO&;E3FLf}0NPY(C2O0wf@)VsD3@M+IfwGRLskTS
z0}hM-H|+>vnsuJQIUEHQ5i6ispiS30TyNIHy=9`^4eQ|}X5S!BAQ?ob0Ti$%Ls%*nLT%FLFgZ5+2
zl)BdLlW9ck@9oz)muNx8$|yA(gW8ojF63TYL+glYLr7z`xMtnT9Q$(mg(wJVpgknT
zOxw&dIc0=U&N)R-N7;^Se$??;M!fwT@I?gfc%w^|*2kzr&dDeZw;|b@-VAL-HwyJ$
zS*A+oo7P*+T&QTZ`Z#3Q;Xc}V6oExJTY)GntmV9BoYiUa=gKrJ0?9T;$+aizvpTz=
zMcl)wcezvy23Cw}c!`Q^R=QE4Vu|B`yrgal-}xrZW8?399R=dfvQy@rWgj{0;=`M*
zJK<}dtLCf&dB`E1=Ei@Q-g31ybvchJ5OaX|>DCz+0<99wLl%O&lS?=MifG(^jk7(Y<~nygUDj7@+{Qha1jWCL^;hhD)c
z=O^aBL3Wv-=`KZ@(pD7274mU1DaVcK_YG|dkEhCy-r}2m`ZiF`Lj%Rz6weM3epKa!
zA|3^%Yc&qtc3Wn_8e132WqXc++N=uwI#m0MxAw1-hpeECD?RpKXrsg*q#cw?_n8{X
z9Py3)>+aDN-;9PbMA5Agl-2=tOpCP+Y~tvOXt;^YWlnBIMODp;sxtOl%(60)@T~*r
zo;B=xQzN({kq#(S~@M(US!fw4#mvNESu8ucVPZr{p5f6
zw?5(W&RU0}T(?*fTFR9)2{OIF>5TjT#;wwI9TSxO&}M6JNxlc3NM9H14C)e}N>-9r
z#a%&WO!y7yIagJCS4q1dqvz6ZPz$Sci?6Y#1w4(rJIgkuNvA-5J}55oyt2W+%GR&e
zD>>j)h2>!!1^dgAjh=G#y~PtWxne#l54ju(VU+D|E7EYOSm%c!wQ&5Vd{92{h&UxH
zEe-RfzMO-~KBJAJeP&_hl;N_`F4dUrs6IN+8#C(*8g<7~z2e$9#JESfvNDz!_4un=
zx!o9wT(KN<%swaWvSfh$;9ZZrlr3roea*pOoO0m)O+p`rS|16mCA&(
zCU0Baw#U(fC&ISTS~5TH>QLTsUBAR_J6W;(vhsrG?z{`14tO#$^F_|p(V;T-y}%86
zQm|;JWIa;Y7q$tNs4(`s#_f1qze1(kags*3(5dD_xtfrMxH_fo9
zXUxeTMB^?Cd4faTBi*6)?@j#~VhZM!&1BQ`RmBni)z|-R8NS6mdeGiCUYg%!zry#a
zOJ$ltANx$gIW{W;Q6sRTF
zO{Hp1-JWCh-NHAIsXeCz)uruOB_0(IiAw3rQ$_Tt;L%>J29=aVk7Cf{N>%t4?ZX3K
zj9uFy-=lhNODWA;mKdX**J+?P+QcftDG-|!j%IJUA;!2@(J$b8lWKEG8WDVjZ1zSC
zgM6XXRu-8{6nXOeQ5>!3VT)@0pJp%mO!~Cq;UTs8Vc^{!RU_>IJI-D)dl5VD93tBX
z%9im?&jq&zr!{fCPK@CN!$G?pv0{h{)GGSOkTbM##}UgI3v8Yv;c4lIG4yy8jv8oT
zrr_#2?9@0-1BeK&9#?M$KosnFF4x
zhHoBnttyCoisbc@vh!@7OA5UPvmGTHZOrUY&^*R!M)2=u@OZmRvw7TzPx;Da8ans0
zY=ae#Zu|Uk?IguCicJNF+Gp<ZdLSLn36ZW%0`%FTFQ=ED~)yY#M
zXaxvjVOBHVl+n+KwGikBNvYJA-cM1VTS_;jSp{MAbF24MW>)WK82WR*oc9GUuF(J`
zIANJ4Dnk|zE2+*FWl`Ej30iA*vT;!yKe$Q7kEv3YWF^Oy1|es4aLMgt_@P#P=X#|*
z7`av&Z)@4B=fv;^*pfB-^Kl>VQs_p36YK5{EXm53mzp63XDEi3)aA=tRGBJ$mgkOO
zi&cGN(vDJ1vp%L8!jH<(O83VqN5z#2oO;a`tFMZSRkoPcpbAO3iPmaK=4H0)wUdF1
zB@~UD_L+XZMy9>^p1~z}#%V9VXTUC**|~;x+TBpAwSABzo2aJU$Z;$?!}i;>r%Ff2
zMr&5sRdyR>jcDuj=7A)c$JQ0eOMFH0+>?T;Vcl~%Bu{DU&@yqGtWNe`v>R=U-`i)8
z(plB)CX3G*w%3UR*en@+hy&nUZIynt%`^9LEVFNVILmtNJ;;L_!b(SCA7v_Iv~_g`
zUVKF}rjbupsP*c!KH(?zgTlB!Bt2!4?#Ucikd3vbgG`zou|hBSy0o4;H_@~*$NI|O
zxZTU1&Y@QFr_f$feLlT8kem34Q89rx4!#LH{LI=yxlBI&
zEapg7sK}KYL-7xBXXsz5QIGhuT6bTYs0cFl*{0UliKs+P`>^?-Grw7>Cse3cpe5ih
z?aSWv6V5MKg0+TPhob}y&1UTS%iOPy*+yBk{206Tz_FegNH}JPUJ+(;VpLx`wkhqo
z)eAlkb3z)?j=i#{Qfq$OOjRA`ees)1u5idZstiTxSlQ@^m9*yOeEIwZTC>Z~zfk+T
zvr(JJf9z@r=cZTcUweDuhVZ+CZSk)JL2LBZ^?~gR5}h@_1G=38d%2lwfX{NN#%5j`
z6lrlH{@h!f5=@Bl2VYA#byzIPXhZae)05%fVe4)oyFuox%ZPw2EC?Rlsuwx_;#08N
zraeM;O&465pDv{RRN@;YJH@ndcDLt6crIPd>mYewFxW0Vg?Z5~a$agPxH6p!iDw0#
zVb{f_K@|T9uVN59r$KfVBGiI_c0bbG?-a&;KX(iWaU;3D@i!PAlyw<04sf5x<;ieg8Dg#Dw^gj7qt!PKi@%Ehsv%d5hB3oXpYNwbdEBwGS(&>DR8k
zMW<9o1nUdYJIdV8b}0)qf4lH7d;{j7Q~$6fUsLaEboEgP8=foe%c+;cUtIe?2eT$r
zA*No93PXdQiL=`FhxZptly!&~oF}vX>&if-(mMarKp+_4%sLCc3~%%E-ujP@+vAPg
zMb2A)@53V^e=!TOE4z+tD78Ofn|n>Y^PE$B(qgNg64ZH?Kbx#c2To7^gE;rMoLw>W
z@z{CyOu}Y;yDvDT+F5;XkM)Q5f(~Xv@7%WH9<5Snoy)aVb!pP)qNPqx-JX6z$$N-a
zt{%ua^DmkXV@xi{X#{pJ?>z8wr9Vwf;#kGA3S8{!z%ym7UqpP&1^)%y`
zDh;sDs$H4iF4SJSV9?X7R#&>|dP&Df8C|!{LtnNS!!D?8xbwYy)OJ;epD;$Ysq@}C
zn3-F~pA~!e?b-03_U-0-^85QXD!EtR=7yFY%mlI(_G#lz)mN}ua&19XAJ{Gxaq#J?
zweM9=g7iM)a=USOo0`#42md0du#1h_j(<9yNH{Td^}O@>n=xvePw!iP+WFZ*vy>?;
zMZimSyYRw>v%y14u|N0Yio{*@>(2VfmLt6~Cx%;{Gf7tz7ea`iT
z`poKu`Yo9YX$)~9%}7r;Jaed8c>M05hKmMz&f=UOH}7^Hkx#QWeXSm!
zZ$1CDTI=z!QzdqtN~W#z7y{o{zo}ml2K$bu*Eml2mWM@8zfNVcW~}6_dX)lqGrL3V
zx-ePn3ZG0GIZwoYKAM5m(0e6V^H&b}xl#UIyOEnL^VXleMQczR<5}O)co#I%D6=(>
z5r6)f?~^F|`t@Gb*pEED-=1hc{|x10uWH@3!{+G|je{d;O|=K3X8+4-|{bQ(xeEz>Yas7@ftfB
zT)uU;h(kG(uNeZrmH0%N^!+GnvBb9m-;YMnyNPO``C--zZFhngA{(f;p+EXb1GvIX
zuLWrbw8@Ej)Syz|zVXwZJLo-Tk3!=@lj?1-K
zH~JoyP#;n2?Gd^nJ?k0IS5M(~uONLcup+=O1}WJZq5JYPskfOxyM`^lBaE}#tXh=j
ztG*IrO9bDSkitiDztLJjch+!*yY^Ri&IH
zwb4T_`1)vmR6N>9_P5cn)|J^2ye4Ol3L_FF%?)3LtI*pj29p?&L$DPS>g(k!AEhy;I6#68mPhnhz1Apg+nRc_k
zQ%t#z(5y2#8Yir2*a>q>X$8EOPqU}bQr&Uc!|u>NaUK(Va*{EbwC$p
z;kj(>+@l7XduTdOe3&3xvmvx4=fhJUCdBza0VhXOszM}0Rv7#6G*SJkiF`bExd#b03H|4!nuFYe}3oz9UWRX-}J-gU{Hh&>yzf
z-9sdE{jm45MWd`u9f!;yi;Ujxt-ty=qfDVbQ9A#W{}`a>FG@SRvea3|Ach(@wG-l
zCYN+{NjoR4oHD{N-zKJ+mvaM1E0?l5$)5$3W#EPV<}9Iv1$<`(&KweB%X=6=V$Ve8Rnjbp7%)hV|PRA>q{3N@|c|Btn|kBh2K`^V3jb7syA
zBZ!VTT37=|LES_Yi*i{VY#sz3!d((Fq^-UiGW~l`2AUV2q4pelUQ^?PSJ>LCs3<{}1GR`Y#1VXO
zG-f>dV@Z=n$Xy+tVml$AAG$OoXWA}yFiP}ByIQv%yUeJFTZu`_My)(l@F`_G>>8?Y~(^d9G{0KT#vRK#OR!Pd5fi=lufFBh7z4Iv*As
ztlPJQOCI666qTg3wmsc*$&L2f@->&JO^SyLX+ari@ppf6U~Z9bl6;bH2yS1zB<*_i
zA2T(Vdl^siDCR?<#@{PtwZa$v58eNUplyziiTcPPTvjAuY}ztfzZuvYb<{QxJpD)G
zvZDASd7kHdK%Rl^$K)yw;}L^0v1^}md?UOeonN1%7}EpD&!U9XUs6hTc9KKW>tgHW
zUl$&vRpJ%MiWdKfas_PCJ-2Ro3jKe8O}eKSmKfj5WbyI{X~p~Uvzzug30KRSMFX#>
z3P;4n`FHm_7Cbdbr%Bs}Y*2%03gWmuPS&bYjWZK%MLsxG)`0~v|9wTVmADDKt!mKd
z1Q+>ZeIe@YA}-JhIt_a@EY(6GEY%^spr?l@Jb7&g+St>ZbWe~zZ{fz6A_A42NzhdzP)n2I@=9|bfAk19-wgVFxCqE`Xj^%wg7M8Vv8SC_|appb1MW3I*jo~9k9>MeO1MXVd
z%eYT#t}wx}^fRLW+KdX*fi#LekgW00fr$f=mP6}S=Eg#{JE-kfG-_dom88tbd+pHD
ze}Z4Z=lPTO559pIcO`vo>D;!#2wb1C9B2_M&`;o|CHITs>e6Nv5_B#x~gWM015VJU_Z%v&?Z{7sf@P+V`Js8bM$ltI&_1s!JoZ3n%
z>@uz{vAx_e2(&g_a|-r?aGHVZ^hu~sK-Pk*C1L_>7g<6s#;Dg}cgZQwVth#9NshXB9#bv&LhsXT~
zrz0u+hEY2qJjI<1>ilrHnlf`z|L9bPx#-0(>YtiIA8Ak53WV$?Tkf~0Io_oyTVL_9
zQlNgVc>q>$SQSwl!MKq4_n`gogT2ByX76IBq4L+f$OG1J*Ppj7-$=G{TNlMeb`GZT
zqOTIecS-gx>QNe-=Rdj;4aqy+sj2zle^~7wU{mh>fGw^SW6N3c=GyfdU^(&!l?|fn
zH}v#=*)z|2vzs23dP5w9>?>9q>N>uZfoz=W&3_RicZG}poy^t$CA&-5&@kWmYbI
zID@(dVPvoCDVg3EAidPL2a5SCoBv#%J(G}Fkewt1
z*`LeZ5OL}Tej-Wx4=k*!65UrZlQ
zW9#JMiN*Qe*PY7VV#FG#xv@$WXchd>WB7H$uWU#XN{wRd=S;Z!N(HUB4>w*|lOQ}^
zGP_QUZf8>F#X7%yIJzlN`QForAR4ZWcBDV0(X7~S)p_q?bT7lIsdO!JN1>(%ct^69
z9XrXAswDmU3&<;}ld;NGxMPBQqkIR+=+F0EPo(QLh1V6b4LEKhhuKB;RBdBzrFf4|
zrERRPBn)EDt7LCpyFo%5+8>4g8#aWq)dtS;0(91b3A$vgdfclK=nA_9ci^h7aL)wo
zAs%=74M*&{!o~^i7QbPV6~0Xc-A(r*<4{kiHC;i+B3Nu-8-uMi171M1?zGr+XBk(T
ztV_TaZEmgHpdqfNTfO>P(z5$m+Skqx-JNE(ac3FUoJ^KsRpTPJ#aFrZrBP~_$z%AN5skP0GCIcSUnmCVn)l0+tq!mO3|9)Ub2OKDT0n`JBj
z;j=M=BRKO@65XMBO7lxzEg`ffWxHM3d29dL=YRQ${$=O`VMXuv;lCDq{8-cC#wY8S
zAAP2dvxYJ93W^^_D`<#7vv{A2XoyN!H#`~KizsXySPXxV_uks<^NC)Sx=NAE;$Lo_H*nL9~&na(7w?PV^k
zNm>EfJbE-c5EIn*Y%^)+cuJu3NKClv8*sThpP(zWGRsO9))BWOig8hTw~HUy1_Nm<
z>HTpZJFFWu8d>v?K-DajZIck@Fj1>Zqh*;p`PiS!!(DL$cqqL;*85!xjkU0mIQCd0
zJXv~J=Jt8FyIsNuZnwTiA%9)06Fh>@(G5czGh{@C}n$g>sX`SiZj
za^J7-{hWAipfgZA@chJcGX6)^s0Zf-((dnWOSMS@`#9&@q_J^6h3%OR#-kS*~J>zJ_d`4v9t
zecm%ng{=cVu3=%@!P)aQF00fdh!qa~a^(lJ@f`WdZ(R*NldKSAfgt~(yl$$`YwK%G
zHVr@2VQPn6k%`n5_S|y4o^33CZC`os>ot&BWvLhAPBqgqdm?2%<-ahk5%Z7{VHb&O
zB5MdDMjw~$AqmYo!X3aOvO@@=5Xe44a)yvW7Lun)Gv==-5?o>w3*CcZ>1$wpfOiz~
zvt~yd$>krNAnv{!aoG70c|ITm_=9brV5%CGj4C0mi@bv&#KIML2w~3yMvHi*Bxgw;
zxFl$*+yY*xm8~cfh?c@5E_e!j6Yxe8>3GU)_n|nGdqIz+(K(OB6-bgv^YjmQI>|p3
zS8&@K)%+$DF>yQyT!Tvb~%TX!^j1Kh$S&o1t?McQiLrL3Jq-l)6~wu*iYmf{P(M|cK1coJ0XD0KuTb>$mu*wBQu;#TFyL@0v$bd2
zrEeq-=M?D3>CnJ4p_*v>#vi6r5q<{JagXl~{0t!r`blQZhs$U@P6LtAr8x(wkqtTzG)x$Y5DulqP+SYUhR1*H!Py=mH@EE{{%(h*T|=`O7_?tHuzt61C@#`i^hySl
zblGX>wb0dIEey*8+L#^k%X*qYhM_V}Sn;xb2h3A;pcf>1rdyun?M^FRoWoqd!i8{&uMkS*sr(%UsD3w1B`
zPPaW*&D1C#NOd0^^P9Zm?u{Stwa|}ljI8OspCx+$mzK82GaS|)4HFMUpD{_JNiBOl
z8Ef&=a&YGdV6z*ifwX2@h`21*@OURLAJ?c#jm1Sem66k;;@RlW#d}5z;@}o_;wR#;
zcEkW3(ZMP=`K=aYfDo3Q_x21&97an~NdLh_N;E#5-%@l!40y`u$4$#kLTd8O1~38XeJ)xeOb%U+x6++mGo}qoVi^?8bp$EerlgoL=g_eLF8%z
zkJa^!x;)}SDUB^zL-)C8-jbA)P&CBMDJXH7A|tmlv()`b?etxOnBboL7;>L}gYrSb^A2{iBAzAntV_R6CI&AD?W
zue1a@pZILQB?+{VXlqv(#kq+0bg3__@%V&h#KfpEY8s`6-j0x?o}T1f;G@;Gu>S$u
ztmMO9`9xQ^7k=lCO0o#Kp*LLET9b2~ac6bF!+lxuTZGO4(}0oUT7812aNI;~YZoNz
z%RfmA0+j|>ck?5PPa$gv-dpyygX8}T9G`c$PKoJvE@(NM62rmT1WS)n9L+~aPm(20
z=G`wPiL1^eN{JI6_%yCXc
zAb*Pg=cgaS|GHPd9CDKQ9U(7dOL@%Fm36m1L)K8XyI*E9sO*3?t^
znKRBw2;1=2U=#k%b~kUFi@ZwsRp;0B^iH8SLOfR{-s=2eaG13kMI&cgp|QOo+$Xi)
zjHtb_-sRv2jhiy4{WnxPYQM3ga#WG+9#tIh3=6dl-IeUjSC~ADuJAhYvJX;AHpvY8
z@<846dTLe2<*~!mt`mA2`jfMzQ;YB>raRJBXix({oj8vy03KmHECAn?6lk)KQv5N{
zi7pv=N;)<8$0A)s;UaG4HRi%gZr}0H3WC4Z-Fn=xBS-fd;%6|=2$7;~JT77Vl3rA?
zNy~?`vIcrQCS@M1&l9wB>nnjUXSCBIQgpw&2@iga-v?|-y@6ZIfsP6Z+QnVi7qK5N
z@Bivy>{}DGzv?nLe8U;;n2Moa<)DUePJ%n@DV%)(XX9?4EtJnTTJXE-gmtTmi##2w
zF49un3xJ9gtVwQ5SLHe#ovGbs)3eZ`{!pSOmvl!y}Y>sg{K
z?yMGrN0pNlx+X{0(OL3^Ub&6Gpf3b%OrR&wbFXX(y-(;2kY=auJonvC-E}y07iU=u
z>2S(C+dc4vpJ`-9HUyZ7UPN_7h?@k4=8Ueu2ZY)2%H9{ZtBAg?hR6FjD4dY3ZN7|c
z^#pB3yTMZk40A@8K^%sPs8$ZYcUj&MM4^>gx`ymr$f|*JUp`FvHAYqj>fU-2>#;Or
zep|Tm<2Yw%-QVlQygh&G==}XUnh8R?g5JP`O0(oMbsy?ZxqKFgN%T|?=1=RCHm`7Y
z*`p_!q_?7EAKEI)-madjOdstTpnMa_bDfATUZ-%
zgC~FG`CFHy??Z2T^4o7}8}g;zOw6G@Sud8KN%!9C4Yd#(jIdpKe(+K9#e7^x+R)su
zC|04r52nnD>WIDQX-#*c%`f#f^bhnH({1dN_n&-hpr?Z5fAoDM`u;jbIvXQB=)S93
z(`@teEu;-OEcvib1d(;nA8i#Kyv-}{QYOLD+(ki~Ewp3ecbGq&fv@rZ{6ruA*RA~S
z(bIiCk{>^NW!=O!^wvJql%Z;N=ihaFN*3$pQ;k6#^R6D?uv)@w+k{wo{eIIoqSA`(
zNwK+vp@e1(bWZ$Zm1-9>+|gkTKC&QxFNoz>g>kvTxa*Y2a6vRKPnkkF;}ecz8b~J*@&d+xua8`2T`tyAQqW
zyb7Zw-)KzQDullU`~P9NeW}l`i?LH!xwr4^Y3kK~KB`JvikbE5H*Sos
zhQhKx=!el
z^&?#>${_H7x2hQ0lHtq6}?Bzzy8F6Zw+=*##-RPDKbT-Duq6>
z$h2vA;BAJ5@S>R2ZKcAevaN^YIO<#E_bV-(;DE-3?2TUE?b$u}K)Ulk&gks4w^9-$@Xkx+m^0&no(_=1Z?3ae1o>{hqb+laV863?!0Vy
zPUsy!mUPKZDO)iI*!M~e%h-!#->8qgnl1aNAs`v7%+!($a5v`
z>mo!d_N~%BHwNBxd*pP|DqzvJ=T0NdgZ7$#0V&;{`wQDpjiNv8dn3K?ZFc`RC}Hjp
zBbzo)s=_Hp(aB!9$LeIR^wd7Lb(hJuQAk96iXxq|E&_S8-DrQDcK&FyO`}YZ^g!5i
z0(B*ATGMDVapHYN;4l+(D!LnWxQ=&K26D?Dl69WyJt5yv_2-0oApC>xqi9s5l(d~^
z`g@3E%X^;=C~8M*s2j)Vr7+Ps>+@P8r<}>l9|p1TC+TB
z^vn&{J^_(t_v`sRN^Nqy`eaEg(6LM5VG@urT#{AMqV(R*>P4OnzC|8~f01XsknJgf
zY!3{BZdMed)n8QLX@iplALq8zO0ue_`^9TD%fEnxTnh)fMJU(l)n4
zDlH6dtAkr#aO)3lg~{@L@xiS%xXqEa@S$T1T>)Mh$^atR$v5M$w$of;-w}FCNOvHv
zMOONh%#g2`tVPjH-;ZMwzhA>AV$GBq;`il;U#1mK-mH(|*?sl;s!~m2Or_F%5fzC}xGSbL=-=!5RwLW#%@9TJ%~;+7ezQ`^s+l%vP7;uyeeM)
zHu+6*o+bR!By*lmT#uMi^QuT8QN}67O7(441$#oiyYLw|-n*g+R)M;AkuQE9s$qA9
z;eG3#aIcEgB+5FzB5jgXDW}gqFINts=$=*MgHKN<>Q=N&TfYze5dMjyWjCs+QwFw)
zmG1ZJr%*mzSOXkgeD5$x!~e#sXgV^sSzdXOBOHhk+wRXZt%?jwB>VM@en>c3qh4>n
zk@e+~l;+;rl#DNrT&R^Kow~2>)Z-Vrh&xpHAY;DeN2a{;@W1}WePX;>jxTjo&tky;
zfYnP*t?9{P+n)W`wRzUI$9k^inUUYKlzEtbz4q>kfVlJLERD&n@3%|15fyxs^a~03
z0&8LtT1Z-h7JmEfO}g*Zqj|{GEN2g(s(F+@AmjlQ?Mh}~Z&&|{W{FL~C+u{)kN>G*FAW7~wBEY)d@Ew7N9
z3%nw}AvaOWopCW=pt?>3Y)U*s(I;KZTz7|Sel56&+NMy(*~-F(FQoXYQ9Z-xX`erQ
zBdbl_bB(A3Mb3C&Lt6VgS~(o9#w-J09PC(FEyXwJIBSwt_k{sg=tZ8vpfIo;c&=TW
z&d!|l2=ZJ-tc$wvTWEZU5At*FW4=oF@tz%??~@o$!S}aFmLUDlcK%G51F=gKC1LyK
zoVsz7t@WJR-H5v-%F>9aH=n`gu308eyahI87!TpGok1z_>JIin-oYU
z4P99XM7A8CMtyK)L(DSx@z2&mudS9M-stR4_0X07)I<1YxhLM)+Se1n`l%^ms%=}?
z7t3mtGq3(>l6k_PerjEWsD*wOq$Ta|V<}2^zsbh&!y)^Jp?aVTG~ydSjwIaz88%6`
zpr~8hTf#60%~R7;VYP^f_Z010MA5fIOZuX2Go_d$ihYu!ZZl&@9z@iwc?HAGPh$ec
zMAq%g+<_Qq6{28jNo${`3`O1IZp#YU!cyp4ggDoZ7ZLjhf6)Tu#esDNJP2`{?TBiF
zb({JfBLR-oFPe|$73}d`7qloI+6{a=kdBE$Rn+B~K0@}oAeGwUze!Z;YO8zJ&&`4N
zZk;4l8qukBBSEv&E>N9#cD%c-{kE+U)L`9ih9=UNmTgw&B7p
zT_NP0jEj(igvs(YKDf08w>i>Ql5;Yy;tPZPypyVce;>yru7doMcj{V}qt!30Dpe(p
zI3fl1D-A7KmAFvuKjAhCr8N}
z=nploD4t21>`T-p{qGddwXuxurI}2G>J7yE+{LY$*#AA^&uKpepH@cjp4Qz)_dB~&
zw7Z=tN8Fy95sG4G&84T26OZDVlAa#Ho-9dPu3|l_&4>w$ah=|9yktId&*>S`2*j|P
z>Z-7R;9Cdd{Z@_b{|x_U^sO6@ac8X>N2684`LZ;+<-;TMPWEo8I4Tyks@HBEd913)
zk6)|tYjKND{nubc$yKBKw`BcPYUxC%$D}z~=u6O=uU1mOI;yLGL)nnmd+GnGNM4fa
z*gKaoaQ9jzw@kDj+2diX~vpPf^eo~K`|z{YyA)A`E|?2fLiF5QC77(*5_WDMG~EF@Zw8IYZ!QkubS?tI98Qk8@&D>
z=*@2Wx?eOod}Ej~#MSd{&%r)iAi#reim3QD&pgQ-$SoDc*j*8mU_A*e*?&J>DfTI?
zqSMci-6Mu{vn7*8j(l6PkoHswFW!9~?
zztou=OzpUL?OWE9dbTmI~p=~Db=H@;^4>!^h4K7`DVAt{D3<&*`ewh9C5
z!F$8SUArPgm6E6PlugN&uNj0I*o5_o?g
z$bauv_7^2dYjU`074j9#Lp88LM%{2dQ={5rys^R7eTErQysmi2k;lCB4A|)Ts)8IP
z?SFoZwYq(m?c5%mKdUzu2%hc*N>5Mq^{JcAl!&Ts#0#}W*50Ih(Z{>8SlRDf6qxp-$p^uq_d(ZKOLWppUNs+6c3%~ElTkS=-!%Mh#hmfs}4C0N8#VWzkhf7|f4
z9e;1)?=Ae5;?6Ssy@5Xu{>p{)5aunJ=6jZPmVOF+xTE=XJC+lVhfHu7{(Pf&S5LYl
zt8np+;jmiaJYpJ#^(+q9&yN{-p-Rc~AuO8gF_+t@e+kkkk1-t8!=xCwGgkPn625}Z
z{`TF#k#JZ4CF4*it8+$fpmIYXd!eJXP_C0wx#6GL3njVve8MGhJg*=M75A|h@94>|
z|849icB5RY6ti04J>HA#ftQn~7?CSj*~ORTkVV7cgV!2%?90&ZmP;C$oE=6S-m}=z
zYGDYeB#yv7zCHBCv<-c6-`B#5&aKN52X`r6F;cW7P>$AoUW(^H`?Q{zsF4>XyBSY?
zGU4r)kX_Ce)}si0{oGHvw0z!i{2bwBdC)&)xNB}j`apaozl%>XR)psm
zVsij3WYKw(CG_#U5^+<Dkgjp>fOn&36MrZ4v(*0o-*1rH`AXYR
z<=^QYKKkf2V<7kZVsG;Gqhh6yG5@2qlN3X$`pPTemwopWl24wgqvwiuvCOolGV8SF
z>@>>HM6sZRdfd%EjfyTojH46<>Jf~Q;xMWcXjmn$8NXF2MV5PdWTc#UZ;$258j28d
zWckew^DbVVL$>k;rVR0AxNgEM!3-sP4N;5r_IW`>XxvdC3R#NB{lH<{?#Ec~u>Cuv
ztrkdInc}Sj(zg#`GW{5>567;0BUcaIWJ%r=ULRSI^};lud1D98w)|Z@;V}CB`eQ;<
zh4RKBvvz)<@~xinE~3_T&~)m4F7;@2^;8?DgjJ&sm5^WsTM{!T*stHiiY=|gv|I8S
z|0P5^U=`Bb#k`jy9Xx_zZgx{(N!`=Pqg&|k9cM&-m%_CiktvdHz_t1~bHBlQM4L_wwDKp`fH&{ppB6P*r=iwZr+H$~eJUG^b>rYJLgjT8QK4
zmxvWUi}bv0ev@2*wqOj`s$#@ade1mUETgT35#PYp7somphO@E4oD$JP#}*tvARm|0
z@dB1|Q-r(m7K6o&^h>`v_?37c&NmEMq)>|-k^JHox_=6eN6W`s={OU|Ci!@q-{NR|
zf#G~lF*{Y~Hi+9>aa@k$eCarb^6PF8-)yz$1iJ>$TI@LMTfBD7D1q!6xU#8rF}TTM
zaWnqP1yF^;#aE;rUR{C=0Ynwb{fj|cV@FHa^?@`hB(uT4spt-~{ax|~Re6jDy?XFGp)WOKl{I}K38piaJB6iD?c&0`KMRg!NcN(IWkVw$0w*~M>LW@mb-`^TUw&9Rm?zHM!;lUi#!%Vuv@@WP|fpus4#TM#y
zmqV_}PM1HS5faqV17^mUy-;ufH1xA}!Qs$4Pq
zbFS6Nz>)~$JMk1`mj@*ml`Z_d5~Afl#Yt$UU^f4M;Ul@FhN!E=L5Yq>)yh0?$v9L{
zmio?79sfPWc}6juRSA?6asiVRbXSkXVZ9%3IR@uIW$&ir`8YPq$I*1W8pq4z<56_H
z5ywu%@X#+v61Z9--qT}2_BLcrrZ3}KJET?q{MIzkn+}Tu$6-pM=ihBTjx*i3m!4kR
zakJGU6Xu8^t49X17F{A#FX0J18$jM)@LmvS5iz
z>S<&)|D}8pm(|X}zH2|Xq5LnK7m;?ix@0rBE9Q|*S4k6~=f*3n*qml9hN+Vm^og!0l>%HKY56gTKx)o6V;FYt8R}!DB
zmU9_W1_f|Sc?I|?MIhbxqvk7dOCzMPaz%fHJxQK~@+Hn<$RJ%WQ2M*G!8vT|;*
z^bP}`-}lym(#0nN8PBhPC6Pk}DsJ0&EeAOJ#Aj5i?m7RybxdXYHG4BbAfYdj@KWe^Ou&;cN_fDKgA6>ln+x`(H
zeI6^yYXQ1GxI5a`=7Y_d{(CWtJ+2iW1}Y!9>e!`0)Z&pQjX6-c@}MnTIZQtrb9~UC
z_Z{iTM}REdI_<8kH^Q{XpV<+pocMdrw+nAfnJX|tLp^KOGB%Ge)FYS{x=&oMbok0S
z_n)*W#m78rG?8VesMW#m4LKgnRp86nG0HvaRG{+RJx8Sc2Q-T!GXkY={(gMEC@7iT
zl@hkKJ2c}4=7%7uODBw8sN>tSw4We${X}7IFupehL+7C2O;xbb2jl0@v!B<~UnD?SOTL
z#9NENy(>y=X9Ol0>-XzUcRGCa9OrwV
zvt32r2|?V@rQmjJ7@*$gU`WZA)L?|8i))EIS%n^&b7;&eG{rC62
zdO}`9Pi>EN(i0+;$lEXgHQc}DS3j3{)h=Pndb`ZWE>^H7B|f$!H~xT8y1HA~OtY3`
zO3F4vxDI)RkM>3z^G-}cPKYN>WT_$zXJ5W#6M)Q`8>OyWeL7GXIK>!&J0uy?h1HO8
zI!>lW{^k%qJm>eoN=RRr^C;dP7LG_Uu{ZxR29wpP!(55=o@svtGG=a=k5j4hBFg@wGF&6ehdxXu3{eC}Ks^j^-dUPK9nhmCMRwASYtGgMqY#Yex{Z8`z&5T@PaZGxlrcaji}IKO>=X?ZY$|=?So9Df-jy{&)gVQl|T^@$lM7
zGBWT&pwkKm=LE}WO
zA;Oz}00}t~vH
zdz~WbO?9I%E*T45mC>0=&e5sb`=fqiyICCu)DM1X;*?g~>;5p8#a7%(2uVoa)LOe@
zl=+C%9xRlZ@-yiQy_fd^@QH%B)d%E?CZl?$(Umd>q^)TqGJ_Oq6s=#<4B-n`aAz${
zQZghGp!MAP4&&w-*-fyfa6O7lqeri2l7Xq*NXSa$w76Pg%jrfI9)TGmtR`I;_Rox0
z+9H+zs1kU^g^ytQHmX~qu9nr(HzPZ_!hyBNp;tzk5kn1cXsu**zY+X;e0zFcZE!s1
z$h6QnWdL{Xoc@CZGS-Ot09GcWOudBj
zlz&Rf6WxTISF$WMlVq!qJhf|}JSEY$_(3F3eIUzIxyD~t2_bn(wjm6m>I{&k!kh(P
zQ_Ums_kuByvEx_CW7x4pPPzu1-Ks!FUh>V1A)vNHo-g=XUYi%E0V}`6FkAXnr7$hj
zP9WpRBX|CKN0R*Okc1(Bd;L@(@-SOB1_GsryRxxbiJG`d(DCLwNo5%CH;ya<(($LB-Z7#%3R
z_dA`+&gB6wchdFuM6>w!giT&0Att1`K+wtW1v+e>qI-<
zKO6GdmI{h&jr3f<&eeQ#9TC}?$iaY^@hMAKE
zwLWp>MMT=Kl5Gjj<+=jZ=Aah8#lM*I{R}vhv)%{+oM#E=yPJuSxC(3*OGJ-#DfIs(
zVrlCVd3|~>{5#I(9mv_Haar|>3omZq!PktO6}?dAH-fJjgM1BJiLc=r@wK4M!${xE
zS$huMw%QoO$)Y_?nIn3=MxD^=6)Vur7T9pM3)8@brUf|}oil<%8Ns29xMsvPBRJHI
z5Cb(Clrm8kqD79gd+viSYj811wLu!=?LcOcz>?+%VbKQFAb!M}hg3pBft7Bc
zji1)rPjfkQn9Sv_D(>KNOJLjXd~4%RaXE=Q8~ga2J;>+mxA|NZs#YyKOu6Rfo`o;b
zh4rcMLY7B1$wOhz^v`L1{IVrryt3A5O-r+NBx~SXDCmmtsF*8mWXA+Gx=ENE*F{uC
z8_|kNYED6Sy=O3M`m9iE&D&{P-lN)$`bS+9akjme`2+E1)kjvHW(jA5Z3etb+r{s3
z){+cQbi|pzDqtM4N*{+=s#5(cdWKy6HU7HDB(qhFl@-}SW_uf(Cifl5-pH4NoWG$O
zP%CO5GMNvLGp$BmPZQ>-W|?dwMLtKTYP0O27PoXQc39)38M*;8v}=h2ynw9t@vy3O
zE%6A>RidYBiCE5KmbNV6&b1qnXKhehl;+y78S+Z1{(Ig`N8$ggayqXSv
zt5Yhmn$Ay$WCwj$NcrnlU|$%~+hyDf-(zh3`1}MXWdNlw_BfrZV4pFbwh@hlH2p1P
z3kEW}iIu#KRDaH~XU{iW(~CU$lf4Hab2pgZsS&Ozw1=X2?ZGkXSY@2b=}OzMPdR79
zh1DLXnJ2C=N6K*GQ5R0oqCSe_Oo2kD5)ziKcAxPX9B206C_X{nZ^XVexW9*ojUjX%
z`-Sp;LkIS&6N+7gJf~mLw>laQ<{d8v{w#s8Qgl{_yl2{G+5($~?PW8bIZ=L!idvW;
z@5f=^C+%~Mhm;*ZF8;RaY%@$g(FFZ`OWEd+&G?zJL<9^
zY9(lWNQCtvV87`@gdktVY-FUoDE6;Dh7_66{1~mwkPQNS&91Zd-0CF>S+YZrR5p@q
z5xMr+Hi5Eh#3BD1RlOs;xED`#>>7O>)>j^q9AbzbHTOrIE1{u1(GB}~=@WS~>!9=U
zd8d?C+iU(GRT1IRfXg?Yep05zJw?+h!d(MBM>OLdt?^$IHb1+GWFY1@zc@a`oO)RQ
z0p%V_D{!C6jx9>k76ipXa%>wZQsAtCHHzIR^@9
zEPE{6HNJv08dNA;+slQrm2AsK7M0GoPCZ&H;+J`~vL8W?!Vh8RC8_rT+a(_lN`wEh
zJU*`00UOwkIwwViE_rWMu(uEq!8N?V2TDuc19HD~@Y@6X?u~Rgr_2+7gFHM4QLI5t
zk|Mk0YmkdePkl?h+EhpH#MQsR7o&gMw)%e{xq@q0gVx{O2Tw*E(Fe}jx{r9P9J@-9
zdBtwnBp_KlQW;)J>zX1up(QHwBz%AzzlTUYNZH7&X-3vzL|uD?%ah&Ku1fvy(d*i8
zpCf79W*4G$VJi^rX9Ci$b&BmZ;Vw@Y;-;;cJ4RY>xNW8WyJ{sFRHsC?recTH%{tPy
zvQ1x-*6xBF;%oR4eSdle|2|CsB
z1fpztpltDo_s)!=ar6}Ww>Xd`d+F-l)$RrDsF4xR=!9_zH=^VtD~{3{uM|F8Zv70!JoGrbj@_E?o=nZ;-F=;Vq
z5i#oUJtgH+Ab$(lZsqg!m2!SphaKmRB1_cP4)$8v$}8v@#z^|
zXcIYh*C4JCSJ#yw*K!H{j?TJr=-jg<@)_zAna2cCi|7q`H1Kv(4M=yEDF&6`q}Web
zX0aU|13z7U7yo#T!}@EMGyNA!qam+_>bIrw7>Bh`9$X7Aba9Wrz73<1&&Z>}Oleao
z&kix~twG&yij!V)elns&TfEia-G$aUsG`Mk^=qV+CL$h5nuA$F)#n)LNu&Q$%S#gG
zT-5>5yEoP%Kf|CeN1EYxe%WDpfv0sq)VW5grInMk7B#oRXZB@lp-e61
zMu%^Yl52R8FKc6GI((aW$J-WW_c4jK4fRSM*up^5ua)#8vM0ko3&}t7ZjmpSyr>j8zTW=jV~#Txe)Hm*!fW8@
zS-(j-TdSxkylPAm^r>ZtInn>7cSKUnB}VtK4w(a=Mqa!I1I-EBb>y7boW;}}yu^4K
z5cT2xqtPS9aUN78i;w^!924+s<559b^s>s`)Ud<-M|Fzln);^a(oDwvc|(jx&7qo5
zRE&;mLzK(1%33vh?Zyb2f0TPzmt#c@hh+wE56JC8#-K$tSEGP{i~dXWBA`|3DAxS(
z4UsrXRxzE()mDOSX`WXV)`0Hv>4pJ22dWtXb7E{47r9qoqhT%Eb3eXre!dUnH6)Tb+lhXx~BM_KsDKLd%P6VaY)1U60b&8(K}8047=X)NgBjKo~c
zcOt%pbOzEx`dgAFnZNrHJ}x-kGbWiv!p`R8B@IMDcD9Ge&bGub_EB@7b7kO89mHW-
zJz!0HP!AQ@;fdOoZp<;NDJst~LTA$2#@mxWk^U-m3m=0wOq_HCwsbiY6g*mrG6(UJ5iLY*NGjDK
zvYezxdJ9>nlj}b3d4%-3J1s`pP1|Oy%R-E`0zO>HPBe8Anq5b4+#H{W9QL%AJLV%`
zlYUu0(yYG=Ybk8}_&zys!O=hlbGKu37-Mtr!@c`J{fnOY4tX@N8hEAS_;rb|gt)x4
zD(ndw$_2;Ow{QXD(uaxbJL1C_@|F5vrc5$&ueX5nn>byeAn|&~*{84{AKcH!zBRPZBNi>V
zzYF_?(mv;_=RJtWll6CMjd(739_bm#tN<>oD*&1nXUVfFpWOlfqr}$>pn>3>=xm6m
zw*ccE51!s`xNN~&AzK0EVt|GM{!iXZxdrlI691>Oy|>T0f@i_6OS%*TB|-8mP~UOB
zkI~;>ps)RiXNXA%cX2p7zCyP0gd|z&F)=!x)!ms5qMT<2a#E7r-#UHU1_%nujjj*7
zpX^}V>{QOu!u^5xo!vi3rj$9Uq1R!?C{?QQ$8yfy7C_p)XA;4CT>4o{R$I$*>@j
z$KtCzsv@2A^oGoOkCgol8Z54m1h2(6db}!BQHGB<%SHYkSRezrH~&tnw(i&DO$!)v
zU+F)#K_2>#k*K=5(wO^%^kh^((C>l&)YAQ)`+?!S`~EofPURkzvgqW7@u2ZbU(~4<
zNZ6&*8+5M~PLSfK76>sig=%bboKZ2l0wICCH17GN+sEM;>rL9XU?1xZ`&?rXE2NsU
z0TB`jT11(0jX}JSbgoc32df5)9!R*bTFU1#lQNA;R*1&4>rZZ=l_$S}&)}i8mH{mq
zakcUmYf3tiOWVQ^a=-1>rBzq~Dk_MOoKt((w^5>8W+
zEA!7G8~R=(x0AGD%52Q}E|aesxX}K+{zf{yM_5zSzjXL|F(X{03FrA$KVHpT+HMx}
z84#a3wf1(2%0>?>T&1Wb}Xl^njrC
z`72Q!j|YpG3yKN6=<#d85RhfU7W7K#CeoOyp;Wkc@Ic8q8#5UJVO0s
zNV(9?K^Lrrm6J`OJZoY6sMl*H{d?W(0sG1wHpQSYdDVZbka#F%aPBl!{KgX77Xsr!WPpVCA2|TW@nn00Rjwo!YgoGg)b@TJ
z^$hn+pf!)2I}>yZcx23JHHhUv1W0d^#M_PGuaOiWz6PA}+oL(?V8%#Y-a*#H&fa^N
zs(tId6!D((jKtGA-@O!dFkmm)DABYG!|XP#^1K&!cnS-bbGX~l=)*ka6mk@4P~dWX`qHe&*Db6mrtr&n0;hTZwdTN_KBbVAN))ibuSI@Gi4zD
z#2E51le{KNYw4&L7$#9Dxt6f4TmTY_JWNJqz*ss6>rtyjMu|Y9PGy7!w2#mTiC0Di
zIs1O-KvKSj!dIaKNj;wP2yh@2z;z;WmC~r`nUqZG6N3P%+GJ!eR1*`#2
z)grMS&7i`HLezIDB#)9B8V=5JxLzQ8lYFM2H%XFM$-@wgQ>QjYWQxOh#$C~ixhi{A
z$p<2FiL-mQ#lrtlbf^C#qi*cT??@V^m>kLb(a)+zlGG&gUw^E5C`r>){+FzIT$DZh
zeVRvxeF+QA|49e=vA0AVd{yyi
zEwomZOko{XC0BOLW!1y#0KLXAwQ*spsJx+ZvMHZIbtenFZZzLhS
z$qJ!p78Ms1pjW5_giNg&ojORE@cEHnL-x8#wq>5QXVb5vq3IN#P?~ABJF0!cdM{S;
zSfDv)bJc=Tt{){<`i-zF8;z^I0@lR4!g89AG~37BnQt)h3MZkqHWF%U_4uDeZS{Fj
zGYsMD?Q5TpZBd<#`;21h^>{0+nWZ+C$6S{1tr_R7oQx^Br$-&gSXZpmq%vbH-reL&
zGV2hTpSWW_(6fqUy!YO39bzVz?3jw=#V(O}J*T>}pGf`8d7IFDN;?n1-pFWmq5)8?Kc8<6Y
ztWRU)E3z-IFDn3HW4Q)_xqvJXws2qu{5}R=zN1PrYB2m=vLgedNh9N^w$7~p5-yPY
zRvl(et}NwB)Zw(KTa;pm^Gpe$R;a&#|W=aQZwU$u#)ICJ30V6PsA*ndP;w(6M=3oDL#
zghE9X&e!T0HH|Y?fL$EhGuvTlQFy!s3{{&0es(<0papst&MGJ@&VIIKVuO~{RxsMxQw<(
z2q}*(%L4g?Z43+KQvzpAWp8_k6GX3&0AKH9$zz%TPw##3^xhZr0w*|pnV^iL8C#%x
zs27sDr(n6?-Oz29_v0=hJ7jRb3glv~-Oyx!9`bm;6zRM1+@ovgi>eFI@xQJ2C<0C=j+l9axH7g>6NTTIbZyQo&AF+{^~4PEH-D4voMT^wn1UZNp!%Rce!L
zaQ&=I#^$vC{_el-lj|zwnQt6)S&&PGvqiTe#x9F_17DV!6NCTM18l7_=N;^mlqZe%
zy*>9$s#Px2MqO3tl=qjB2
z(+ge%KWOiywBvQ$@h*i;0EX3S<9fr`H0RrajFY=O{W#I?eaO6E81gKzmx|qf8Vzoj
zZ;q5R*4VrVmM8ET$|x)Gnls=vm5Vzhn(gap-3uO-$Hdr0RUWh3#G14XF1r#uYQvVc
zyUTCld!3bLM-PSY^_(DAqAEfjO#9
zy7)HZm^qF4o4V%G+d%)Apb1e8(<-~}e_vxndlXw`Uj~U>_rGe^^Z9G6n753n%8O#f
z^}CsQAA4{=)mkNPoWvbOOFG7FK4{;G*8a#i%p!ACS#t@`GAA*AQ`TIJVm<17hP)Np
zxlwr@b-A>k#6_|0nNfM1S$F&0@XO%4B{5ZOBO83bGh^Tl--8&q;jHe=ZU%3}9M7ww
zGwdOt)rPa%Kh>$;XUO_OHSCg{4UD^?!OmHtm>G@J>SI->i#f{}<^ku_qcfoSO#bvY
z>TpZIFz=DcGk02tTG>+`RlAgbhHA>XEobf9i$tcC*?2-Hv@^9hM^?Y2f({0`*zFEP
zCs0fiXN_ZK2(*2Gc@p$Oo1C1x`Is$S&5Yt{UeK&}`wH#uTI(>8xyBIxr!mF|osDZr
z|BSPaVJLFV9WO-N>ILjGS_j@3k|LvB*Q8cpFM72l3vO6qe8Lj!E9htru?R+1j6bN_Y
zn3=~qEM+Wb*}-z={VX^02+KWun&qq)SjQt*SlwV$+pPlUa&V3qlVk1>mYd764$~x7
zckXwLDkAB*1XfhzH*;gyf(YHCzhi3tk-%1|PqV5B&sQ%nNzZ-7I_9RbqUH#zdvh2=
zzoOq%;h38{55IA}7W$PKb{h9C#V>E)6-IYG->+p+E4TcT)N+;f2wR}mef1(!bE%0f
zQ0W$9ucMJwVQ)2)v>ba%-D2FktbtXjb&FRqNl!PiDo(d}4U=R$#;OF}SFbWjIX<>v
zFft$wCY%Ur@(d<9PWRHa!Mau74<;;_=hm&k``g#ut9$j<;I?}P|AVtmVz(>xn?dW;
z>ffF#p`QNCy2CQ9G0*xSqqX+fwGBdElB(0_6vmMsjA`50dUJB-&dj0G%4X-fKRue~
zHvP_C^XZ$6`>Ug@GNMht;pW=I+%d!ueX3;ssfy+34Y^OpFwdxFsAohZ*`C9d`zRE@+Qu^I-sbD$dSy0GSF=w$A
z*rg7UJ&X0+!6XX;ll0OhSi$v-!xxXSxr8_oLbB&6rA+E>obeQ9-Jojd
z)12$=z}W~+Yunwvn|;@vdRjT2+IXh-aGv$DjM0(wDBi1v9yJEmEc=7t5reMsN^>AF
zQW#`hY9Wh(PPy9)Jl0(S!yZ;IUg#ufb@smenIy+YLXM9N7)}ELbv}aZ09P11?;iQC-8s+*
z5}Q-<%(Tsz?nPA!JiUwF)3_#R7b)2O$n~j}(^cr<+<@P`M8Bhvj5;YL$WL^>g6x$!td%kudhre(=dxGiD;HnJyNrZH6bXqa
z5)x75Ja7&#-W>YG3a+sL*3cd1q^xeE(yhDNGkA#4DYRA8-eeImsI=A~2k+?;F~6I~
ztQU|!2lNcJxzGC*ddxfMbjzI98gDgvu8{ZmdTw1V5&0h6OS2MaA{#7p+z_iRx0UC7
zt(?pJa9#uACG5!aW3_!(ts<+1+*f0MGdVx*sC(mX)xP`~ORN(}IK$HU
zc*e#qUjAy;V-8;smvK=s+>qi#i*Fy!{pSw(~p6Flm(x5-gJ
zWS4*yHgk-1XQ5kv(LjFEefjjg;s!yX@pBD+)J=He?}V3`_IFq#7?*qdvFO=jnJQHo
zGp!!7DB`2A9?ws&A9-=NRa@R=0E!;5IwEALr#PQ3?46@RS3^IB`I-Ko@O^)i?#Z}@KZ`7`?7v;lFX65aA8!$Zb!
z@|+x#=JLs-WFEHCz#6#^_cWE+nT8
zi95P4pLzpGhuJE`Tq2`YZbowdmC!INcs)Ik%dAKZt&cQ}hv7)lZOne~{Kc8TJ{nRd
zk9vO3$NTct>Vi*qeo`f{lqsuodXL=FZrD#ECk;}2Flu^f9Tb`qobqb#csO9MoECbD
z@?m<)(h0H7(3y)faC~34ak=TNX$(fzebAYbIwaMScU=C$i_@j&kIy3vrs0T*p2(Tc
zOd>l?Z2eM8LVj?bBi<)q$cr8M9ePiu^<*P5ERCTV65}$-A8&Q+#hzNL(`ubgr{nVsEtniIMnoDl(s~62OJ}^LH8Y*DhywA7mx`!U6&n$4
zRnQ7}1K#gCCkS?)ndg1}PAe(I=AGl}QZoog
zVMen`soD3+FKapTR-KiM~)*jh&dju>A*qYCLm?z}Eubp!edHQ!24u%Pae6R-JKm
zGvg=6L(2n=>zYc$<^&94i%O=C#oCLRxFz}IP{()Sl>r@zacMKFgSNV^6mZBlFLtbe
zYGrm?g7mnmxmLl+x_uq3NlR^?EU-V5OgPGrt!bu{bYd1!alJy3Yiqto%yP{1OBD~b
z`e%Ay+I%M1|DK0x0uovm?q+R!-X(cutZhD})NC*9sHyN1=L3GykoMX!8nN9!tA=yS18w|zUOZK*LBzKd${hFO%K=o
zq6^&TD)MYb1EM2pkG^D#1mrydjSBzd5p*x;Xh}Pd@K$1$(pC)~+K~3>o-b@h$e`5D
zfIBaPTD|ShHlto*MnfHXp)p-w)43uPtmSq2dfP7gj*Ph)?Oy7q;f<=#I==Zo)c>Zl
zetl`MzUSfkU1z1u_n^Mtvx{a1{V#vGe%D!P`>LZpc0M06C#VWp9nO|5DrJVc=RMrE
z>$iq)?`Vs&s89J;_oe@;K6bFQN4HQeO?UR7mlGVPMw7l#vZy?TY$LD_A7AW1-5387
zdtJZyXi4W6i?=FYyq@*1zKHJ?D>T~jWhaeZxBr{^8AXI43Pk00vNNbZLMReW8yJDa%AKXM<7ns?!
z;SYAi|6zT4Do~SZoqMno{&TIi<;n=6KkI-A^&jkqO8xu?BLH;R{}uWLy(~wBBdi6`
zOO2MJc&xzqgMIOz+YVpa*;bneZ9S*7Ee^JQ?Z5rjN46Yl$b}7LMj#B?{{jTfm
zmqBVeSC^IlCql$wnPW^fH^HHWk;@q5P4@$q0sU%
ztXY5WkOG>1fHz)@+-DzHc_2H;}$~lcU4}>jKVpdE!PP6c0%rvJW
z;s9bGy^&io1m0i5%#mDN%j-W155=}nXnM_q^*}4Ssy4v^OUF01
z7Qhw*Tnyja)fK;^b|*N6nTc6{4z^Mv-87_)JDcF(EulEeSD3{>G4A3GnrDD%;53sk
zLA@=<{s+$?%8^R+@|TBkr$DpmA!x4GBtQe;kw_0#F$ZwzFHG!!>$R^s;i9%~jb8oG
z2_vohi3Ir5)vAK+MY(-is{94S2GsZeO-EmAw|4eLG_=D(r-f0wab|ILoE8W>*Q*j7
zMUw87sNOMFv>(%P@|2?>qz(U483Q1J3{36hlS0cWD
zNhEFf{VPG6qeO>&k_Gl9!~=&nDR>{B-xU|c=Xi_2auhyysh9~)>^(m#b#qsCtxFUG
zJw@6lSLK)ljawn@JWMB@d{|zun?PA~f=>J7GR<7u!p`~&=67bZCyp3y+u}qdukMm7
z!Kv^y$G}Z~?ApMkTN*kDT2%doN9|KCGU%Io-hi#Dnlnb>uWf*=-2x9phAC*dw!Pk9
zH^X+1^k9peu1&i|hgOvdJ04^wv>0)Fw(CfzeG6x?Ku6NBd;H29KD)V`cY-@lRA0F#
znPbPKFxZf@;d^BLnHoJGeQBAcRo23JF7|`3{nC2XOyAk>cw0H2V?#_P+%im52Y%IZ
zTQVcF$NC9P9d!{O5p^Zo*Eo~lrnd3P%w44&6u&G;@iY&hkxyy7_D#|w#2qps1i^W@
zL4PBxgBMg`&+ouE_?NzH@L70Kboh*Fs2oF427ZpX&R2K|f$SIx+mzMp!6)=gjb
zF*Fc|FPj_sz0nW$wGnP@Mud1Pn;Fy@h;?BGe&**l^jojLT)xHqnmV;{WPMClxuZ@gT(@KHDP|~n-oJce@^RbjGb(+oX1APO(p<`u5|5`P}?*CrjiVr-K7gTmg#iOc)q-
zs=@Sa6G@=T_+J_2xr;F`9<|z_%h15q0<>y(aExMJq{`TTgz?7g_=m|fpKu2pW@zBG#QTIm=-S$ZebPE98
zjd|lFW5xo+s~h(f!KT0!#J0zL@2{o%W$ff*_vqlIiT7kqTTAEvj+M{mf7AJ%q&;OFd~pO;_&jkA
zP1U%{1jiPKguI8ZsPhjNfZmiHY|=5%+X%@LUKR&E2
zjzKhf1^XZV6||qwzfQ13ZtldnumsvT9qwHgY1t;Z<-9E%avBI`WCblBXe+{P)5U(q++x*x
z#|WyywEp5@F$gPf5e3L#O7&l4&iIe(2ak{
zo`i4gqD~Rs9L%W0U;kUGLiz7A+?{C3rbXDqUAo@b2UuNSTA$!_;{NF~=$jEWh0m8?{&ef*uvGVvXk`!iM@XPTX4%lr&q0wwqB?RvUFv?koxC$F9x)%^5
zsT`%;3jC@CasqZK+#{E}k0bkmJGtjm23slE_%@@ax-+#dN^iS`AoV>w=}Zsnl<@bQHP
z>1`h4t>5GmY=QhM&HRBVW_%Q@FM?wt>!!kPuDjbU#3b@UPwHvQF1e=-+W*M&Makzu
z-j8V9@)!$Y$H74lwXP8W{IX*Bz>3Ezm3}-*CisjBE?W
z>4)qlMzyGfnMC`W${K2q*a<_r<%9ZnrBH=7bF5^~N}2*m5Pzr-BTWI?->=7tP7CmQRA!@$yYO7h__)0fq#yD
zDsUIm(D*)f=>dHnvr*J@N$YK?hY!oGSdo8D3%O8tr<)iRsupIJSwlPM>Z#$k>3j-o
zgO{NFhva#Wok!Y;oA717L#$R-XukznVCsxz-haV~EuXGFjD;#n&fdW_i{A;)z2mIL2fd5cXzMu!v3
z(Cv3DxL@b(KS(Q%>0w#=;7e^kbsfV~v%{^&C4)rYdH)^zp#8A8E@%Jx8@%-*NlDNj
z`JtCY#6RH{#(#^(|CZf$ktCe%fwx=W0NBE0i)Ga516~!s0{y2S-u26IKN{!?P1+ls
z&@6ks1DfX`r3P(ajlb7tRE>)hT
zl^OeKx;_hxDO+6@Cc~NMUp2CKSxkVwM%J3K$t78wEk8gOq++&@4bNUZ@^ESF-u~-X
zC%@Oede8SG1dF)b$4>1bIGtBwlUI+7Et{S!y8X(?N31SG{SkQc;HmQU)nyf>nRPoP
z#3^ZlNo|5*f%yTcT_JIq@|MvNgXEX6-@?~b&v(UuttGvJ3`MzsWi?kP2}Y7x06Rd97&Emjld
z!Zv*~tdCl5nuHmcx5gAEKmAf$B>(+$@UJWQ*R3tW4bpczY|6T+7}+bbDS+O*MDDcBHsbZpKDydpCvWh
zIQ>51V48V|NBq5?)#XZ>YQ$lgT8y{tfzP@Y^$oaC$zzB(u3
zk0&~YRBBG*Mym1rrNpX)?1V#Jf%b?pZirQEs$-H?ws~H8sNA>+cgE=TlanzO3bX|0
zy6=^{5yC#L@URN3%)zu;V^iVRl>thLK%V>kc^4$yYt3sse>*l+JgQX@@4`0^!+yW<
zrSr1IV&nN5g?rJ89ccZ+V#tnWz02%=#DB=vwh|@uOy>O>>=fEoqGj=SmlW@Z>|UtX
z@dn}K`?+w-bqrn)F*cpGDZ^FSlp#i+#8?9P^=$&U0C9rI%*YE=9*EPY=R;bd!iMyz
zE^A#zdbFXrndL3iRaT&Fb;gdBJ7vr7Ko4y@@smFD&+LBl`?)8{61V8Ufqhk#$IDOd
zdF|ZWXXcz5vgi4#1eZ6bnkBukp5-|gnbH4sCz&sRyQ$+M?91S>Z-b4=!F
zMFyFZ?}04hUi{-yLuhE@P3T0mY(;~Zqhmj=XpL=+@@m&7yYJtRc&(~6M_eAJ`qY-B
zek+-?7?)+UuQ%gXn3qyvoqCu0&rG%W0&8{mZ`uaR{SfYG4zXU@J0XeXu#fz)z><)4
z(`L{3bp#0zU4#l0F6
zb3#>d(j%3>1st`%jT<*)By<>>-!2!dqTy#fUwNy&b#tcef-k)n-COG5>87iW?)~1~
zE2Rb5*GeVfPQKyMUJSi*VmI`9X-#k3ERGWoSIN)Nms;+t&(GcXlNZ~^LhDssXgHtE
zL?^t*VVMF8DlSxzy5I2?Xub9I98ncL-(V*@k+Z%W;YPmOVZn(k43>p!dMrscR12Kw
zqSjx*Grti38@Y`vT%Et!?Gd9iCgoO@XZo2{5wDji_uAl
zJ~gHU*^|D>*s_`^OH_xUpNq2hl3UY{7u2E}dFBNZFRFa_tLFnTzFJ{yYtJ8-ClNKe
z;8(QdwW`e0(6LRv$gy=k!E*R-edg0jc=P)?r#jchnccK9=AKN#ny^pSFnNV6@pi)s
zd43yD6varrW!>tJ0TjxF~+Gi%Di$9ggI9iB`wIr%+ls!stN0|2BP>8$AOnC+zOOUOA;Z
z|7qn^fu?8p5kresP6hs6msd{3IPp5IoG;Cv`T(Yt0cBf&s*=bb0wL!vVXBk1hpZm
z7hA9@$+?M%D)c`0i5RbTBNMOQ?VUN!ui%k}L3oDE&o?-SGEsx?%z47#)?)2k
zzT3m@A1HhN*(;*h9&G_UWh>ynkC^!^w#=Zmu*}Vdb6U>ZG>oG+d$hy4(>n5_PK7TV
z@W-?HUEvQ8!XL(sGxSaDfFJ9I;3wD*NY!3@6`=N4NCn-!*V}M%eG*^xUa#To{+HMf
z7)cE$_S7N!mUf}BUpo^3|AUp`5V>MDvdN|qCa8Jt*6
z-4J1L))N9OSFo~5)c=0Ph`oF&X>5AWxmYov(j|k~f+cTP<(E3KV)C$JK;3_n%-g+A
z^9Jt$smYrh*&pXcMSiXrM*Cy!6Oj*|3>=2vkLUCwDFspco-uCJGRQIvxi^t@2>&+Y
zUx^l;7RlV7Hw5+UIH?%a4)Q=~+*-w5i%O+NWYotv@TLCM9zVBG@8U%C?v!
z;R_S(X}YM5>gmZ>zFX)?FEwNjWkK1uFH!FN&*AB%UgeiFqW=N;u2?&`3n
zn>XRZ_hiFUTkOA#@IzKT;u}RO@prwr<+l6-Vwf6Sb^!A}3;)zgj-5W|;0z1h-IlJ%^l8z#IESYF)L(>&eu{hs{2J;Toae0e>OsuAsELVdPN@<-Cq|M@k}@uHtw^=oDPg>b*!~`swWPG%uElE>@wtjYWq`oY2
zPtQtw%^)`1W9(bkcG?$Pw%mWV^w7xRSvPK+*gL(9d^a(ZkXGqEjb^NmpH$H<=a4!y
zd<9u_EzIC2&1B&@ig%lG?u|dtF_*zJ?)`?w@%c0(lMdS_OYl6H3A@JFvS%xYl-nm-
za36)NO?Tt0JFF9~DHJ}a&izqygv-`qHcZKab{6~l?|j{sj67V%R~NHnF*AjH8g+xU
zFNBUuH;7|<^WN+b&I{e44l_q`hHGt;#^rA+5}Q3t(7I6bN~zd@i>;>
z;6sk7*60$C&V$+&O+{t1TBF5vO{(c5r6X?aGh{K-2mXp;Xp^er+)jK2Yx8<$Jz0Ie
zRM~NQKQ5o&!9n`1J#ma;H^{n^imMoV)-jw^GcE8Mmbrzc20W{F+nb0nChH%BYvJTG
z*7(xjJ68J&n|PsErQl-L37xgroM+=Mxh55xGi}5tNV?9koh>zd)D(fb*XlKtMHW2y
z7@`xH-BTpcHgI;oMl*FJqQ&7fzf;4(nn}q8AVP1Py*#zZl$%m37P}w12hh?$A8a$oqP)l-j3cFx9fIx;HxGfj25}T||x(
z8Ls$!9dH@o>np={r-n@(sY9%gg&9gO#J`9q*e7k`U{yLv;-FKDXy|utR|hVoQw_E4
zO>uIhDZ*Fjeq}DSHTeO;2w7u`y^5jNFXjRvzP8mP>w+2rg`Yc4V0LOt8@URc^D3$z
zaB{+o5^W9spUy-lyeb>l-G!gp71(WIq%VDKj2+4u`wRqJ30caVZEC`OOJi@KO@yn>E)mVdFOPcq49_%^#j>U(FM##E(+kMH(
zdLBew6LgYqJo68nY0^&p+V?E$H!OrBAK+ZWEUoDjo@+K6wCiI|?KNoM=yl2;Zd-Nm
z(7`&(k|V2X`rA&`K*t#Rm%YQZFX0S1=&9R#5fW$cpN=3N^P**YkM3QD+aNadsDBu|
zI}Ms=-(Pmnpy`)(^dNqRxP@omUveZ|bM(lf(Ze*E?QWsD{k
zXF|@tgNw!w)8K^up}ov|
zhG^sy-aeN5eT7fECxl|&T+yzs^l5si4r>6}s^xo6>|O3Z;V1f|U6-%O90)CyElDai
z=>`h1%F~4zG!{frvAgR(Vu&`iaA8I_@*9s(-g}gs+^wRc#rLOID9?&-#|BIOJF(TuGwsFLvf$h1>A{k}dHP|W?NmADC}VoHTf6?A
zF{DWaDCGQvw1XoD+sc9aQgF-i=(qMsne0f`CXy}xrr9STDmidND
zXMH=R!@f*Q`lK7B3!rUB;5@~a~l@Q^uACQ5`X;VLzBjju@YU0$nTN#B
zaceShN7|@I;1gw}7N<@>O7hZOxa
zMk7ccyL<0-=hiVkA~V$zKk_Ff8s1bsRMS+w1S}n
z3N-l?Td_|{-n$WMsqj&JIPppoP6IxSB5_4)bb1aXM4_TIE%`)p$)aJ1?46WdX-bcp
zojZ(YA@-U@j6WqY@xKFVujZub%F-n5QB(d8;zg}+G}WuQZHlt&SSkMcsH(LWPM?Fk
zl{;16tQ7ZZRQ942F4D5olb7p7jAU_CBW~IoPkH^t$OvoLq-Ej4!i=%!sTPM?R3|XC
zv5m6DgYTa5R#u{)!1$y0PoyGRYHna!BjP+^hm~7LLvyH5Y6?@Zp?;U_-P9)7@VP0n
z8qwva@I$xtmHiL@`y@EYu-mR@5v2>`mb4VXe$(!KCfeh8+pPO~b4(7sNsqQyJJ^Dp
z&`RFAlZ(t*kQ1cq?Ba*%dU-JuZ&pJBPoD$}t;3+Y^OEhR2~j1$ft9_O-VwdaeAu-1
zprYRdW!D!&uNIu=H)tzH%4o7luFxk5HLNw-5V9yNJxBK+A@WKUf1}ZP{)U~}rF+F*>|$#U
z+ADmVw4cW4)mEF*d-+0G$czX7nyG4dbN$FM2`p`C8CUHJ?T*ka`@9ZoMHME
zSzqKD`qyW0-?_Mn(KlP81tC2L`oh!5bx|}n_$&!MrRU;($en2May{g~BDK9Hhl#hf
zf*2E~68;zclp*ByDa1>`7}9fIETxvlf~>
z%-m>htT4*GxVhaOsvi`7S?s2R9pjI|Rl12R>h6eP;bC(hJexVPp?2OKF;*AGSqAzF
zq`4B-;ei>|kdrjXH(Bv#L^;~XiSvCL9y1`SvLBVg3?EiU=zjHlRlip5e}6xr~2Z|k)_vz
zqqIERP@8)Za>)KCe8hdHEzTTG*hr7DPjVp(F#rE_h^bh|W*pJ^W)7Hrkhc_ZhTBcN
zTiX~hVug6Cm{xv-LEX~+h#HZ9_l{jcv8jx)SJ9K+csEn)oN
zF|1@oQuR>Y+ccCPv4VK3_`zS4ac19TCnf6hrEPK6qz?yjDSHC9m)zwCYkOSUAsZ&m~W-nWbrfjUe)Fv1_f>B;6+8!E$oN!WQS$u9i{!iKKOk|;qD9O
z#~;T%3HArvdp;6(g7(V{6Yg+K*UJ`}KTYLd$z%%-ixKLuj)=kD>|x1DZc6f%v0J|m
z@(|mX&w40JqYTw1ZLin~&j)Wx-N$4{io4wcV05!;)_-1qYFL{F6*{Ur~w2
z2Ju1u)&tO$l?3rJ6Tjx|$}l~BXnK(I`ZrQ<`MC!Fo%Z3L)?U<)oR?zGC2%j~GtD2y
z(^tircT_=qg`0>g=oqpQWBiBE7|9jk}U>C^h+}CMW|71;i^oP0b
z?C3$;Wtm*rH8zI8x`xwK#_!4Z%OlOwhF~@Pq+rmYoo>#n@4VT?txD~YuclA9R%c=R*8?saCB(SfQR*d*n;R#lTbOBGf$uucnxNKO)b+#HzCtn?kJ%vpe4U
zRlj^2F25zc5VFz8JH3M$Vl0fHOwtbE>^499!taaDP?dN-)!J*cEZ>UQ;yuOBYjAEX
zapd{KY&y$;{q~=N{AbYWjL|WQm9F)k)){z!46wT!MtNitu}kv_VsexVBNY
zK33S|Vn=R_2;%i;LyVavWe?z{k8~2W6$6q1tABvrUfEM0pRZVe5{$;oTY7PE78BGj
zE;2-$S-gkG=+kSA84i8kPrrm~E-VKWzew6QWf`)zSWQt(cEcMqI5$6GzdhRc+hK@|
z=hkTT_90W0G_1
z#xS}kUBTtp3+2)#l#tOGRy)1){63A|5N&0y>Px0Esov~MEGa~jyu=@tj7V|J@E@1i
zp}msDnB`;ksTS-M7?m`Lxu*L1*`XJa-f8Vk8J66OY|J$&y1#v@#1I8+kRhcv^GZ?4
zBz?OV&63}RrEYlV3$1uH>R0X%{UEm#HON~X#b5XX#ZIJpIIs7!BQ|ua#eEyMR6j>?
ztv0%^a<9mip>Itw{7lc^VaoHvxfBO+yMPQ(gI!a6{S5ZYh|oA|z1{XTx8P&>?9ja}
z0-Eb4(l{gL8hWqhHo;e+g2R1As2Arix3q}v6ni-B)C1woK2A{a#5EKS)iQHP;ki!cxsiHt1SH
z?3Ow%bG#w9uHF67`H1|0eS8z5|5b3#x$Y3AaW7r^gzM2q`w#05%!VvwWJjD3@)@+$
zS}r}seJ+u?UW@MUN}07@$%M79-Fx{q=bAdJA8(O3_a9*G@j-7c-9j48L}7ofL8@*i
zT~%vTyx{&iitW!W5DYK%WruSgji7rjIk%7uqrX4sF5}guM1981e!bn_3)ZwuEw9mx
zX8exFdPQtH{k*5v{wN8qucJ)ccXi-`@DSI1i&oL+Q`Wl}A8{#Y)c(d7+w|cLMu$&t
zEGU*E^DY@bOv{!*CeHaS;#A@kj5?hhJdV?zFkRo|@|Zb!y#josx%z90g^9asmPknoue%UP!{hQ_<%5Ik3
zVRu4jJ0&~g>^phdL8
z=qs97xi3Hazx0*#UnT6qt}Z*Bti=n?Z87+&nmk|W?L=k+|BGXZE{a}ivw*t{wY#$>|pBlTpny3PqZJBb8
zdazfnSMD8nix%s~$XXb5aNjGttae@JyI?#y<^36j>a}a^mD=Ea2jVJc(7q&w*RdFz
z7*fYVZ6aci9NLTiY7W(0D_!yrihhNA40#8)JNXngsD34~v_A?zi)Ej{It+V2M(!@usJT-L-Sa;#K>J6#6lCzaVrt)1
ztWqGI^(ibPG--Zg?;06iy3;tFv&7$j{TIlH(u6U8a#(@O4|!&$9Q$gS-?*|yhS0~x
z{Q7Lpn15U;MbDSyo|`**_AjBHjqwT|s9(z9`d;p;E`68!mA(r~l(dP#*!9)lI4#n{wAvzDU$HJ%}C#oy5_X3LyEl#G0D!1$81>4M#uujC3YO
zyEcpbtmO!7vWBP5LDG(R+Wl#(6t0g2?n*>W5ZrRKtnw3Gu9Y1GSP2{8F>#2kQ4
zu|dWh-7S>MGx2=N9iyF|e~9P9ZWqdB
z?EQXEo6$kfSFjb)g>q>Vo}zb&o_>v%=v^*XP|JJ9EP7sz=jdH7*Wo#O&!*>11i|e>
zlow{;p4+OkHD&1bHD!$O=%zH29nUHnm!jX+R1ImE
z2CaY`uL4GjC~rcZ@HJL`Gc2jA+kunzNX<@9VfW@Xdu1Jd*R}8T7$fk@*3@pVY-;~H
zw-CPqk#+aUmm2xXopIkUMnr~jQio65ki|IHU60FJ3|d9$PJzP^s^$u^qZN9Z;+ae`
zV*DZ=oGVX@>|PnhrT#X)vZh^ES(#BNm+R%SF_)gVv{RizlmnhYtuLcr>?Vz`U+$J&
zkWJi=2N%oJMrwDgG%khBy0r#y*0gV5S}6aj$FF+)GUn2|7W`^y-?6d~zXG2QYR$1G
zTcamoE`))(aoKioU_17nP_4@YDGjoQF`}g{2P1B23-lP&o@ql?x{R=p;H-Y;N2Yb1
zznGr*5es^XJRht4ZLPhk@A7`!g!+3jr`qMISNh7m)s~-&{B`*9fc8#rrMPM2??~P(
z3I>Nb3Xwl4)0S*=k@eVQx!2F@+i0D=6_RWvdotHa59WSoZU8VCH5XLbR_T$(yxtU2VsA>6^Gc>-fsaK}1XV$}ZcBLi!Y)^+tvl
z5tos7cXBl&yEWqKedZS&s;bPYB5fU6+5l3XAa#e9se-EnIMCG$gKcCWzea}G5Sqz#
zz&r@ggD|TvAYM!VQO;2Y&3x!;;w0o5LEbEJrJ1KEvM+sO-ve=3kIQiPt$x^&W+0#s
zxF@#8W#LW@$J
zdARf|eeWG|>-MrG3ZA}>%UZ%hV8_1h#>=)nwoGdzc;AT(*Cgyhn!x9k7}0iXk_Ix9
z)ry<T;ijLRy{_M$c4Y6#&F@ja7?Z|!81xdE2U
z))%dPHoGjR0OdX=gzPWXjf~C|w7TyEPJ$h(8!ZfrdNEfeYMi{xM8jW@MN81`$qIaM
z3FGOhe-WG;P)^0Ztfd&vJfIwoyZOK76l%AtkXxX!6jVb{DKS8+Du+m0ocfR=iL9&+
z>`SP8)(O~846*1#b`XC5LX^t%Ph(GTRouzIZOEkThxP=T2jnqm{G=qTw|wGUJ1Q#-
zmUNiMGoABH_>7rfbSCRu!S@GFRh>M3;^gr&N6%ILaOl#3ANO6ad@-fOAq*!fwZSqpplE)Xh*C!y@^@Fb@92
z8&rkiWh!I$W2(aL7gWZG8>+&HJQek7H=*~D#{g9spxO?oHUKI>F)lL*)eJy20Z=6a
zs;2=}e?Sz;^P@OEbCdzP)%0IWqtjzV!|YTKI4{nd$oA^XP_Sd`H_kJ>s>}-hWd%pm
z>rOT?!b@0hUN$_-2iOnVceM*_k4a%B|o-5KW865Hjrc#>TKeS0zLl<&x^Q1xm=FtMTqM{&rjfaF;^&;
zFXDMIXVlX3TPXjDD@56F_P0zEmh|qQxGa_7>?h3oLjhvu8(u}JVJoMJFq}nP|9M*}
zQva)z17Hh9@qZQZ_UEF+8_psIzgS4I`d|G6V)bvPX#B5!h=}hf35K&M&D_Lg35Hh@
zzrSu1hxq+xf6tQME~1$JuYSb5mx?%z)^HY4`)3t%St$LHdFzWg_dkBc41NBad4Kwn
zGyEFmHUGtue)A>gKJy5k{}=QASi%{mp}b}ROPW){xlhO7`2yy>@&#vj1?4rrV@b2W
z;G_)0n)jLa;zrJWRF9`0FmLU8PBqs3oq>Hi_R(-}pb)>-hG&HtUhTt@-rL0)(pw`6
z#?IN@15XWqybnxtKHo8R&Yn0tci+7E(DOZG=adhj=g20|wf^z3b1FwrKgcf7_4yBD
z=j?l#>bJE$^nA{NH^;WVYWP@rI_J=D$5NgG%3qM)XHJ!zw*Wd0==bGZ269e=kDwib
zY(RFa?tAwl4F7#E!hQE{1adP)Aa`$sVZogUveyn6ui!G<^z@mT$#8m-f-r(%o`X<^l^shV+7I1
zG@_63L?35}KE@M$Oe6XjNAxj`=mRCRCHg?y5W_U0j})ShX+$3=35IE)g_#zjiZetN
zR-%e&L={$|iZetNHlm6%zXMgEr0y68&47$;U{=N=;Vg)&4m?r5hlg+kJP4x>f2A8U
zF*E6pSFw7-!uT<2mNaHDRqby-g4i|BTsZ^#}
zT*L{PhFF?Ki4ztYR?{qIaS}>2izwL*u~@Cp`gWzl|I6$Vb<;{0dws-7lqWM}<~M?U
z(l@kwx+*-7G~`pz=QV9F!fF)f%f|74RnGmS-&brU6P%p6%-pbhTa<2+6Pj+y&eK(o
zolnxOS?6yui_reU18P|6?>u^3L_4Ce9+7FUYKQsVh`Rg$lm
zd40E`3+63J5+tw?oZRQ8KU$LOZL8$Ck!1@xOWB*QVf+hXz%RF*X-;bQb7l6V>^9Xm
zi(IQN^-o%K9hPm)D)HybY^BFg6T*AIT?9$n?0!gC||M?8Db
z*DUn)d;G0I-@242%LtUoe@Hha$|8k`7x&42B;PK5&u7q>5Vv98Zqx6fhgeQpk-qKo
zVS_twcfSwaS{5e$!_SfN=RO=4&>b6Ndn*W@a*pgCN+;4b-|xK=c&`OOx@G-j$5)_lvFrE7A$i}sl^>6H4~
zJ|?d4K@WV+e5_QL(qc|B^yZSp?>OCmHkn~@aWV>$e`}N&r~#IfvYSl06r6!@V$n?{
z=|MLcCu-19MbOiS?(8%;EyAbFJR{ZJR2~s&ty=L8;(%m~*ej5p~VG~e2=yVj~u
zoPs49u|l63Iew5B@-^h|zE`L=&1n#m*lkZD4hMTS{_AJ_4fP6*dEGdRr$$t}^R3!KU(3YjgneX8I&0
zOA0gyq&XQ0&4SrwZ8m#DE}OiIPMKU&u_n}~Skkalz+)h9R@?KE0=c3!$l8_&Yqvaj
zj|2Mqp@*lBNyrwEDIh<0`XR&D(GRp$0{rp3R`B^6mP81zKaI~uG_@R>r&Q<^WzoY<(+?L>a=&?QXwt2=7W5>si9
zAH%B1&$;n@xv}4usHx)&x{K|uUpdv{xHov%xT}w6#b*^kr-eGD&($8!qO%75YX5d;
zTKvS76E&|ir@lSv@MCttBn3MhhTUUFM=CaB?8LOgKeLq8VFYfs)U9XV-;s=*-(mT4>buv3e
z5(4|B`+>-Aw`a?mHHugY4@yLy+Hf%1LOO#@@N6sfij#z(KBs7+1J0>U`}Yf~Rl(Zj
zjH(PohTcD2ns4(;O^8`2Ui5*JFU-(IH>szN46Vn>4|hJ-e6$*9<;9qj9FmIgSmG$a
zS4;0deGPut?Ro0fDY}ZU%v@b-RA6;e+e$$=T=vnG-2A=CnPs-*S@5`PoShr9w}0ja
zt>GgfB4%%7CRXN06)a|NXr@ye>WnOtwB$>cxS|v59HLA1PL8Tij&xe+Mwh7ne2dIQ
ztBRpjApNIjs5~G4E#GB&X#b)1%Ibb)e!+=1LaJc98Yg9)JaCj&Lt^C+XVGy$zG;Ug
zPBL_3Vd&H6?#2+Un&$NU4X?VyBz~`Eu>N|8R*6QvgYt3q$Nf#uJEjfgUg8tY#5G&`v?k$cXPH2&_E1@TrRS9^)h#E>)fEqNZu$fe-
z;dLqDgwrCwxgcZsAnwp)+|HayPhZaz#|Y3yQUB|_9Z_Xw;ETa$g-t%fcU2YQu6EFP
zNY+W>Lk+v%5MVKE?IwZV)lQ3XJw?C;u1`gkiOV5dAcC*5DnQA**Q=;3V`y9B+tog~
z=K07vNsbtHe(`?b2rERP`qiCtMDs&D(=1uM&#Y%uZ=EzXEp{T+IRL&!@1b=%)X*4l3sk9A`g+|ybz4tmCOs^{pt#~&?#`upN^ZUyDgPlLyZ114mh$;8Jk+GH6`k`o!@Ywmmgh
zjF|{L;>NA9eQiv|acLTr>c~5x6KkDZnD8g#dRYl(5Ybf{Us{&nq}B~LZyXJ9q4&j>
z0nh>;a7=cLbAG$nUNnliL(PltP&_Y}nz@J&!D=8Wv`JJhO)}{%HeIYLdp9oN0M^g)uR*hjDO!gE4M`!Pswx!I(Hd
z67?d{I?_0JL!>c&dt}45#;I5vw_P=<+)}k$`@WXsbFtC(E5j?(m@)S;U14s1xA4*U
zhAOyrMgsnA%bp)6aVdr{l}@bM_}4oE_@P1Fot?
zFWXN_ALp)J*qjreg$xv&pYicqoH6kPC!b0M
zoIM_S=bF7=nE@HU40g;Va-bTJ1GNWop!TpQB=_L|AJ@bF|H>kH%$WW0Cq?6FQ^!IKG8w%N}T&xmcMB4fwGs+PW}fx#h#_7i}VfK
z^v_B%M{U0=Sq3A=O$0a>o;Myj%3b5k-rSgK5*Q5
zRrAkgODp9hGY6maK7i%TzyB
zu*W8;U0ba_dhj7Bo5Gdw9XOV@k(YHtl^}hUmzZ
zfFRuL_|Ew~f$l=%)!u^v<0oqaAwr}4t(o|izvElg=f!-rN*Q6q=i)R$^|=0hCV%%T
zT3=nJKg5L1kL#6hm+pGC_4L<=z)7galV8qgnz`#;_LN?(ee-m-jPZLg`EDNZG%a7~Fp~k$wB!U0`c^3z(kVHrP0m)M0h?AhT$6dp`8`Dig
zta;X5uIEz9Qu>d)(KBkCA-l32w)8(1sRit2;#+mB_Z|t>A|!h!O2nBAEzzvcL3b0`
zW#m^FT0Uapts-W~*23EZ<=^~;xj#gH?&|#9%!6WfG$%^4NTx02Y`U5gh^smI1u5J0
zt>y*JCcg76b47inK9!s_rG^t+xPj70nqBg)KHo}FJqBYhKd`%K59lp|=q-ilEy57$
z;A!XCx}*OU$wH;vA4(igUyx&IHl9Bbb@*|HnvE~zhwqQe8lxxf+V}H5Wn=VD$vA)g
zv(Uo^O*uD4KLl?+$&aj1dO2SunQ710AjjBBGwu3g=NtR=j{+=^E(V7nA7fACW9*4c
zjXjZb-GIF624ey^>EIa#@IOI@us8T8{9;<d0=uPilkOiT!C2?9#Tba|`=JE{9@`
zpcLADGw#6Vt#u2jhLmogz%^;z{uGlE3CdlD{M6kWLzi%a(dv_25t%~MA|K~2V@&Io
zirs{;tMcr>R5_!<9O+D*KYGI`cTEgi65?7htABjf;1H6e+FfHSc32FH&22AdrC=Sk
zFHSxDcnIxuPkNH~kCAUQa#y}m<_vW^9DHEeE3MEOg*tmH65_nWQP+wjYIol8M44M~
z+)wLG6t^zxX=*D|=6R`q1?22D2=J{tAOC(Wkt(krL{gB1-)2(L~91F@Xdz81irzf43*OSZ8Z9n&1
z-8fhyQ~TVeFV!ttVeOMrAtm-EOET<@4OPz_J1${#kfox|9u4+%~|oUDlMj}(EwTt6g#^U2F-e?8o~Snhf2-_aiT-%1bTHwL;1SG#2?(4i(T
zTs;c-3<6nH&MP1(a_p`r=0jT0Ls~#y(&R`;-Iyt?j>Ur+Bnv$x3rG-8LxR{nv17IN
zlS_*b?=<5->Dgt>SnbR5+fdA>TndT7d`=KoIdC&f^ttXlvRAJ+I31YPQTV-eV<=*+
zn*{moHuj8Q9=hHQ9-z$mk%G_)dRqYhCCpIm>o*4O2j%L?vo8DsX9oR6#z~;SNKjxT
zC@>Nfs0Rh=qd*UCshk6Jwe58aPUBm(pImz)$VbLk&p-AQE06$jCJ7y-WA_~eP?YQ*4H>VG%%Eb1%YY0N!71N$TT
ztUZ5j=&@igwSCX^Kie2GMxO%Su+{Z+^|s!)-vxJQSls`ZWTB_?mM1tuvA*c(R(Bv)
zxJq=s7S}vBZQ3!
zRocIPl6Ii57#c%FCE8yd6G|f+UlC9VSGV;ZqbCeR_(5SmHikS-o?MOdGO@$_cw8R$
zlN-_g@>A?8dpI(zx{#L
z$PXZ`|Cd;Szis(P#36y_U+8}TsTZV
zDRtvfk`5|=y=S_X_v%aas`e~iw$6VKY~ca?lzg!%Na&8jV;
z)7Yg)aa-I_To6`&vtTInZG?M#=>F80#gZ+LU@m-&GjJrgG4uiP+vY^95e0A7RFYk?
z0AK!?-;@1UH=bR5-4N=N{vTfqK&S(Rjeir*fxQ*N)K|E$fV}5QwP|R8*ECK|RybHpe00jIB
z5bg-NHh_@H*O)=C^}*BswJ9^F9-m6Pfgq(?9`t*5yd<`1^F#iE{vTc0Ibxw0pgB!g6YLGEFyLIpT)2Ib@XSN_|1HcD7NBykYZ-Q=yg?0lM87_t_9QN1mE9%
zp3eGCn5W>q_xDxHztF#v|GRn0Uk1GI0)Eq5{x|cqeQUjy1#-^IJ)8vLHNKEYHo
ztm}H!b@48|d(@G^)LDT1*uEZ?d5qXbynB)~r2)F~wZNjLi-+yphxIHX$fZv1MSoRw
z@vtZMf*i_xN~H!Ut6_T_u(&f4E^z~`S3J2CcqGx48+hg
zwdrOQr{4=33zMR@(0TL1-6iyGDZU-KREBRau$ax47O)4EgCa0A{vph
z;@cUP4_U&m`Wc)W+HUTqJ$C%@E(;{OsULrE_TIVGg&Fc8g;|k9q?vI;5ZO*
zL|UXi;k`)xpid$bYHe0c7%SH(7+G&+*wGtISoW{b+i!lm^^U8fy+1s}Jfu0l243De
zLgc+{nZ8pOo=s^j?C*PB{!Yr|p5uJKJhM6F=U1Le*)!)KzMoWc!&b|euonJZG4(1F_wWkF_6)baWN?hR)Mk6e
zD~V&D@Thw6nNzCpUA$HGrzA<^u!g5_3+GQ&*e_4)l>5|*{46&{f=D=CSKaSzVPsJ(bd88`uId}%-TUv1>%=z3
zTf2%W+|)}_SbpU0yQ{XWa%y5DoV{OFd-uJ{^eFJ|D`ehXrQbeX!h|+IeEruOEB?Lc
z!4k{fy-RjEJ}(?qYBM=E%v3wqSE{`SH?YnPt8lCE1?wI{cPUvLoCnvN`c%*6omuag
zcv;2z%Nx80lUeWWT*iCwFU(KtXK#4G?A&l3`vDgEMILcfKKUQWMK=&j-R21oA0Zc^dI*Xsr%L0o2B
z-#`Nmnm3x~NE3}T&`9%aDSNR{&on^;uO3=;vl)FzA6BnKsnA`_rtl_aQ%}^>^9Cc0
ztd=cpEQ{w>R&)c=?5VZ%oPI!oLPVO%EyGI^|a+jg?&Xf2+eD?cSo9Sunae*
zJJYumXrwG`TYqMpjav%xBb}#li=k*lpv``hI{eAsz6r
zrc(qN79f!8#X_nVt9^~6Bby%rR&h%TP9$;vk9j)mC5P76J_ZYwNT7|FlXPu35w
z^_T6KOK-xeR@U}nxus2w7AXtihdG9Kg%s%YAy*;e-}u8Y=u(Z8*T6ah&@AxVJCS%a
zS)ts@o||(vXE5kHbm7=ji7N=d_?HT1N`YHeZ9#j|0DwYJWvu;s~3;M)ggqF7k
zTAn%O^C{H&$c2X+j@NBpVLwuSXv>!e_KzIPriDjoLRlGTAg>u4cI1dHY`T{Tdj@_-
zr>C)DN9t|)4~I=pX64f62fn%+X|Z+D;&4Mj*f*fX*v10*O8#aoom|#}7S@4GfjU47
zSW*deAP>}_3DM&BX`o~+pn*Ee2ssJ0e8Fge8WH}oqnS9BC?T6IOUfi_Xyik~ke(sZ
zVG5UdZ|Tt#q{kh@E2eKuV>9+-BxXJeiue}Ic&YC~#GJQ~eaWc9
zWNEVHY$VEqA`)0GN!F!@?IZq?!iJ@V+{Zt_J)$;*46u0R=+nAg1=*^Dp%iT1BVOQLug@AK}A`2;=+4iC{xUyo4fPp~bkRva#zdVRg{s
zJc$;YFT)pk*h!IN3fME)Hpuml5?-V@@!}1jlxV&D0m#By^v4~@5K0YU#*$5BYa
z;WsDRSlSFd!WwNPapk&r$W(UhJ|e!g4D|2lJX~omY>=~Z%R(!88zU`z?$1q3sReUS
z&J~_wSZkS?H@o`~-?!_yBA>(&c$=-`N_|Xe;4S1~4t_VpeD(c5=fyhWP{;1ZU|dhq
zDEzy3*#aG#)K(km@7mV*Wn2gta0?EVZ|erCU}
z;33qmWB#qHc78T%5j|F#SuuahL-UiEOx8R<$uI%FS>%RTI%jKNMQ_QT-|0^>EL2v1
zV(o|faRYYCm@iRL1~)Xh5ceY5or2$DMc$efy&HVHDk>bsF8i(uZ}BM!`T5N~75z{2
z{5~5rNMfLmPA6Z|ItcpKOmKit&Z;P4P42~jS$%o
z1CG)d`=~X;F`pi7LliizoP(
zW!(?qi}TAnV=+qeo{HSBQBA3&yNFcf`~_ZR0LLwCKR%x6D;HX--z+|X&a#=Hnhh?tmv1=Ql2D(SY2
zz_{4_E7s+a@Z&0sp1NDO9WC=@R1{M?xwjSJew|@JLdlFE|2m8Eg(56DG!gn0iml4L
zra?4IO<0>`ahO9vYF2ZFTQZo5c4{rPbYvlox3c_*LeV;f_*@EPXQXzd)%m&SENyOm@!DBj@!&!
z(C9h9?Qt{1H=e(`JJ1h5s(fNQ%|8KtZ`Bn@PT_MHe0ei^@7Y;_e4F8=_~{cb@8qq`
z%*{Ju*_N-`eIpiz1Y+$5qK+qBcq{=vaJSn7dA{2YUFD5OF_uQzEHNbM$W~8-UlOSe
z8Z+Aw?>;Fv@K&3=LSy2Ad+*svleZd0=R5$hK5VS{kJuAR|8Lv!b-Hch3pW{*9pEru=obQ
z#|hu3*NWeF^bCHVbxFv-SNz@<-f!Vbs|bm27I!M6_R_xPcrEr2)!H?*0?hgo&MZ~p
zY7o~3eD=^z#ig<_kE=87*oz>Js#+OYpntuzh&pwYr&4aBS%UQr~Cb1>pt*%JwP%V2C~)&eg1cm*HvqlmpE
zL(2>6v0uP{%SzJ~A69b5b%I)YU7|KJHNB04KhV5-y_eJ?hh&*&3h^7X3A`Ul+|LAM
zdO7(el1@Z!HFD#Z;;xWy)BQrU`rtef?|`2>EU7QG?s9NFZiJvcAva_WYea_8WHWJn
zA$Q#ueRQT)XT8ADk1~1lM&VFrV?$I-3(_lv?ZWPXy_F;eqAM@S9*+g{|!&h
zztuHA>-fdBcm%__RnWDKmD6aN?sC?}nn^plY8AKUMHalJt^X>y>R6R)@l7G8mycyB
zXH^+;+9+rLvS7|PSIAY(S&rLJR0ZoTxhV3@1C1jC^**xaCSWZN)+!}fcb$N>iC|54
z24Pi|h_LE*2VosJC&DVJ?H7Rc(q}iJTP;#=^FG?|iF=OmwG;PFt;YPZuQZFP{Jwzx
zdV?E!?AY&p1^!i3?uakZ_67G=IcnW+6MYU04>zo<%Qj^4VQUW-&|vTKt;8Qum<){E*{7_8wMH?b1MxsUYAL1jha_w64fP)
zVhQE!+7l9GuvcxXYLnyd^tQzdH(1H9<|f%yCc&XH!GoB35EFk~wArgH(#vWXeWZ=i
z_qocrFLdl}Ey&vp-89)ymcEK#4DWMtm84(BI`dFda=QajFM2FXZZCr5%)jGhXP5My
z&PzQq9MDWmd10nx+Cq&|=}B$UD3jEwXSGrATRiB6zn9l09v*gZ_<<)IN1etA7PdQ*
zbBI<883HRwJ>gdW0t_xpth6RHVa2k{v|KZ<+&Ahp*7mlIKVv^Dji|*e?Q43_h}ArItc-iYDlLhii9-E&jKYOKIX%%3X_T@b`?)vtGbqqT$Vw7~Zy*cT>w
z{@mP;4_NR9%Z1dl`{hd)?H?t0m$IspZU79lgCgh_q3Wc2$lX
z8#^@eqk$Z8r(Z^nqmrAT!SBJmdsTqh-UV~>38Mh>Bb^BIykCHcz7N7|IsVxo5oW0n
z<3*e$4HqAfCl_yp-^s0p?0saHMrUp0_;D-a(!zJhEX-p0tn;JRAd*~NFnxZ~hqvb^
zW!=H=UFtPF-wN)8XDy%a8F_-Bi2tI;Vg8LHPpHvj@HB>=#M|J^qw&WJO>!pDG0x%^
zb_knSkyVwyU_o>|FOF%?;KG3pCZWEEbyQ=abw9j9!58G8PLap1P)HK3XW%=HgSRM^
zm3;r%tPb2|>JbedVe|6!f1)q=
zZ4UgNj~7P0AuBjvX||%|_kE
zY&<`zR&13aI@c6zlZ^dsn|ibNw@GR>vDBtO8~S&I1Ti*$4@_ISw}HQc72{hG_oq(<
ze!rsGPGhzjT!wxNQbpPr1`Q#JLz3-mV7?ULUVw4Mf~2*$o?D~URB3j^s%PJ
zO@-Dtw%rEXfC`GmvxKaq(UEhq@}^scqvIyM5x*o1d)-JoW#48*ELvwe5`hP|hKmRoFeP!P~K%
zV~46R`{?;(&dINRE3M5d+wZ8)EMX6D~3&H94P=zG$b5Phs^HNWhg!xVby1|8O5yjD)!
zgP$CKd^n<7l0*?PPdwAsR9ev9k{dFv@sxyH781f+*$lS|I{=4j5?63T+2zw&Jnys&
zFwdCp`Fdrkwb^y!PWfsr@@iBWInCj#Z)3bf;cV^cTydx>n6hnrbFbC6Xe3d}wB?7Y
zoaWd~V|h95sPapjA6$25F?Nh%jaQzjqg1_^y1_}QM%Z3%IexYgdgsnpl`5*F&0o{{!Er6%+u
zzW7U-1O3o1MH=jfg2&k3*glJP`u`)khk@=@ME4&r
zh;*+L=)T|&|8I2PSbvZ1w$>Z}uXJBL!3O=lEeFn${j)PioDq9PZ)X&3H5j1+@heL7
z4`N1yv5e%Pz9$Pg#L-0VInM(IjQ<(k#{cLHhNmLsgF}BP|qz
zlSceeok;mLmOm(I#3w25AMu0@jrhCU?@_)WK>0N^;{UTc7h=R`R4tw`va0XG1E)2r
z8n*o0;ij`kVWaFA?o?S0*m-l)ar-x0&K^I}O=la^acBwLfU6}N^$d^??VrIe)KjwO?P=y
zhVLvNgZD$n`u-@j$guYlOU{DF)cs5)QpS8zY5l0`75=J^tnx+sJw#2ZC;R-d-$)w$
z1$i1RqAF<=bME*QOq&q*Adg$s8sbyjo{2N9K|2XINkcjeF4=|KPgHBC&}y>HAdOQ&
zO1xSH+eqv^`g;cdSZSu2E!H20-C@-#G0&@^VxFgcmFA%}0sMOR_#g#w-nccb@Xvlb
zW=0j>JS%gWm$v>Q+WK9a614UcOPHbiUiyA}&LLk{E%IL=16U^3@_d+B%f`k^$j>9{
z0(hveAb(^4D;_cLraLHqZ)JpK4Pw7nFXA#ikiMc#@)p$a^1D}aj6Rp@eMy8RTnV}M
zg0k7A7WkS8jElG)*k|z~gaPn*<7Yg7>Vi-Q4g4{0|Clqf%B8v_84!T5U}mXhz&!}^
zFi^`Dgs=e+3g&k~hzs|79$kASr+v3e^}I9)A^W-R5L(Fo>~;{sW1R2c2?yEWKr7S}OD%)%wPJG!
zwCAn|A$(-+@o2a5;5a`zcIL#Pyi9(t{P_FI%Tc~9SpF09p+~xvSD-xqNlwc@&<|bZ
z$KF?7hVnm%<%e2!n#Xi6AA<6>k8)J)?1u+}mKZs_Ktm_u-VDb5R@-BTx}YXWW+nDkvQ}=22T|@!?0*IU1_c2g
zfb&ONul-#R43Z6rC_l~<;*wut*8qdQOj!M3U_d?)L<~;d=_=3PMfp0hybA5gmh?+R
zy8_gKJx$rjv-@+N*dtPB)-AlBIhOOpt^j>I@qYSH&QQdT3(|bn9q6dFIXBCn()a!p
zw|OI*MCcKK&PXo~>7p9l^-Vibmvi%rLV2(>e@7qsDQ+jfJ}#CTO0<@ai3LSuSWVbc
zOAiZlp%K%?2rZW!m54{nZD>T}n~mLsU+@!OSDi`HHL>0L`!4$T(7K$DJ{3#i?yjug
z!3{avy5sPxKAdpaaG;AWjC@2l%vJtjj>R3bJWrIU`pa_5-5q!D!Y_V;eo%Y3_}uV_J|53PY(T{-eQbNU
zHU}JCCTnsjlGMCO|3EvVtkz4{Fo*+GEyy1iL>pF_1AWr5tO4}fqphR+33C)#CF11c
zDzv^Am^XDdxVIENK`n+WbN4JXf5Hqi7n)WwZiXa@)&JzyydPd^jy8z!Hn(po^o66n
zpNSA#9uOf;Tiyk6bH~Y6Dd6E;`)~)MZQKvh)5N*nS9U=(-_Q#XH+&kvv4;q8q@xR>
zxnpw>VswY>w-5`CaVy`KbwO-t-?W5q%>US57VQ#cj&hu7#1`=1gB~9_eBxV+AN}*;
zl)#((I{N>^E50bBZ_;=Rw4Z9Zz8#XuMxS-O5xa#*?tuhP
zp)Y9^#c?A_rv)R@;tVgwEgXMv;sMdtVQOOnZX>Z9JZG5F3y4DQYg2FS!z8cepWd~M6dm>bm2ZPzR}1
ziGP9GK(}CsoEz%K&Jp@08%UR=a{^#qLN7L~QA5AEVyhz_|;;o|Li_431f^ss_
zLW#+w(W#F&vlruW-`Fi@^riP2qYZ@?8Qa6UK8@ROnc)f)lJRyissXIC_s8=e4W3Zt
zXrLSVCGJjW3yHB{V>07~Xt1xnH#lcpl}46*Yq2js=S5#!&Xj;B7V<@zF?exKRC?kGHZTavN+Jd-~@%)GZ^exzqr_KiDYhpa_{G2+-^+MoN
zYgldE;E4TE#uy7`W!ieH?Moq&S@Gft!Y?GtE%$Pc7|@mT-0$Y((&Z9@OR~he_vfs=<&r2Wx_E$}RHsNB0q3H*|w@`W|wFi@J(p
zmn1lr8WKyWokRAcoruDe|C`=fCG-!hGY40csIDwE+-v`VCvwhIMGUC`gy6T^jf-=d
zZK~VShEPbFHL`+R+(U@6wl$Pl|IEq;>bbG#C&V%{P>tbxq5sgg{g<))gdtrpzNj_c
zH{K9E&NR~FHVODHB7CWA)*h7Y-F_#Nj~kp&)c413<*U1oE*e{WLU$a$*wegJbql9t
zV8}^2BmsDz0bVrW5*OPA>-Im!`JxTy{&*GfHAKu`ginffLzLAEyHRy;&WQaLh;y1)
zzc^>)kcy%Kb_mUGt0*5tSj#=EtZ=~o)?
z8VQbmW(q_RW2
zZM@RqH+;CCJc;Z7rpN^+0c9rcb!QUKoSRF1-<@~Z{4D0EC?ywXzc{|oLut_BdBmmI
zA#L_=y)E4m%GgZ2*#+Gec=s`A-X6##D=dhhmb`8aliWU#mH+5%9mwYHGXl?ph>s_~
z5?G^4{AC|~p$RFIxpDS$@o`S^`z)uw?9n}}hnF?Kb>h}XRfL&Crq?0TbPTi%V&#mf
zu7W2l4D!A|QmQ87=G_?nxchWk^5TJr7CDgh8^Zr#gHF`u*eC8up_RrBvAHG2v(7a
z>(e2jyahAl7I!<=Jif&fzottjZJsfIfo^spZaJs@Ob_Op^={^xi&bLIYZ;lm
zWD4bF(!@KI;Fs>BQ1&E^Le^~aiz7^a&9Ba$q^u_IqsfR)30^DQhteHLLeV(7sWi~a
zC2!FJGmOYr{AFV{XhL*S5mWhm@wWmZgd&V+
zrlRPzV})2Z*bKk!0;Bp7ltPJ`stR~sS+cHgUBm~751@=?qs^TiLYidOP5i3c^7DOk
z+rle0DJk9zJ=+>Owc=a%Q850Xq(0)x;0eJSs%t`IXLw9LN&3T5#BxDoQc1JAOZwxn=fy@gWI~cH?K5X<+mV%T9Ah|QZ5HS
zuqQZz6rY7MkJ>TMLPd(VObWot!Tc*`J)|k+&&$rPgiZu>w6oVSm1e3H{rXI$Rdr>l
z)o&PLA4ap6A2(s8Pw%r0zbO4Er)tbj3~IIV7;;BpM~{W+zHxD&8sipsZP_#
zO>*2aJo+{V$<+sZ1+7NK9kjn!_{~*221i#d?
z!ma-W|EV69kLWJ_f`9))NO++~C<|AXAGG712ilt#KCXdmlS#0@V0e{5+zWNVph_#E
zZtA``^;DMa$e*(cC(U6flAT`D!90~UB>RP|C2rC%W6g0G2a({@{1Fj%*37+oSz^R(
zHsUL$^{W=!ut5KU0XXLmGNC=V%@1&e3oDM%YED!bJb|9It0Y67STd3CoG{D*s1Fy`Izm`eXK&Z1y&12p%m95TS#pR28owpX7Q0_<
z7@n}2lf|;lt7UgcURl=f+V5~^YQ^9QrAI{EXGHcPy{
z32=|jt8h?Xu$CG+C0y`tAG_LH^tjO*TEbks9mDVUiFJ_{xHxMk?xpo7+PEFNoa!{v
z&n2wm`6o+&WjN;!mH3l>*rp#M!&)E<@h4^dO~AiLmre}fA+DxK-KrlFE7vDJF4ybe
zaV2Tq2k1Gq&Vb#6y#4l{vyNk*(0w#W){PN-)r2%96b&-JswAn)CoC*~)w-eApox}H
z@7LvehncYl=+_QUc$7-xu-CgZo5j0k)>0=>_AyU8?%Lyzi?{7$i!0jZZp#^bn6bdx
zWt8+03zJ-Amke{jD@uvYv}Sa2&IyTM_m{Vb0};o{M9;rt*s`V^{a)RtVl~ISBjI}D
zc5VF|&@aBd#;bV3$lWMrypC;#v8&Jc2#c;$TIIcSTGyU(a1QNv2Ip+sSDUuspvGa6
zCl+PW*sF)^@pYHt(%qp}ZbnClwgY@xQT!lupG?CnbXP6#W1J>$m%qM-D5#N1-`D#_E`C`@JoYw-rd=ecM4zluP
z6kGP%>&p>wXLv2V_vBqzG~&=OOSwgIv~yBI(L5z?DSOoj_E&o5s$`s{)EXhz%dR5k
z%20Mw&jIZ4Zv4X>8&^aJ&li)sD)N9P2
z$c3+Fjtw|xDl>8Q?F_fdC*u~>$yCd2R;7tMG*Akcl!FqS+(fwyD_MU;-L_4V)5*Cz
zB#~a5Tjew67kpj9T8{aWi&LaI(1E^e2%FSyi86(0J3{miSg}8O*=I6v^3@XC;BzLf
zrd`4zI>34pH?N&JXL!qyyYH=iOViJ#FL7fwCq)-y^`4UVb8~U*&(S8Q+Z|GPY7TsZ
zuKUtk{J3?z};?Ish5%SI0risU=
z9<3}|7Z1y@P#ZhI8g`VhY2MHZOFNC?d4{VSD79tqnc6U{{$bz$%GC^(ZsEDFWH{HS
zDL?r|;MQ^nGOyee2HGTW^_q`|EB{-{o7}VON
zbEE1IePki8!0F_WTOpihElT6MFQJK_l#5l4cF@Zjw6U{Yo{bI#@4kZM{$IWaKl3yFXt;wTf1V
z2IKak&Ix3#IlT5s=#5YR@d0bO1s-^R(8tKYtD*AoFp{T}hmqec62vv@`B!RU0r(ndGp
zF1ba-s}d*Z)C?L=m=C~~Gyx&mlZf+rdl7Q}2#X*Ic~``G)SKEg{hUi-Vsjg#54uo8
z^wHd-)xro8XFaX1;%l3jDoO{Sb0x1AbRDN(7-p#`8rPXW`swQR)wTOfjpnL!jNJKcRoAx{%dM5X
zrpap9?c|CDjn}2E42?CLCEYk5I|JU*0t$&1I0mCo-y!VzS!EWdUL%30A4z&P_rMzH
zaYK{g49%+`Ricc!M(Q(Y0-WBD7!kp@>8EZAa%0h!L6#J4Am}_eD7V6mvxvKeq$B+6
zTKqy5@f!RAU5L0S3s79(ED>atERG%co!L+Wk1~jOKgozW%c!{rJ8RopU!z1^Cs_hhiwe&>`Kgvs3~VuH_wn;mR&NUSlLPher;Hah=4
z`SAE!@CA4&;rht$m9S-S3wBC^<%P)5_tN-`=I3|b!Jbh*L4vuXi@urQfP>^vvqTP^
zXx#deJx=z~>0C&~y)v2*17;W2r0neHc&pRBI#oX;gVo16z(a1r!^sG=g;prK%?Qp_
z_E4dKuDka_D@^x;&9D3Li)fR~Fxg-;?^)g1d)=~RAFLj%TE<&^
z-QZl^nu@X8X6ohFJ!Q{L=iG`1{kkj{{Eg|d{sE5yX5z=tt=DB8naAki>7Srx6^%K`
zy-hKxqYOEQ%mew_$Q9nARz%&pj>sh)2FDLJ6YXMxcVD=J5n`5R9w@Zdvb^)XX0I<+
zj8otHW@`L__YO)2o0uq5a_B&eEt5F5-o9?|Dl%B^wGLUZtI{c18q
zn<6s2C2m7<$`p2DN!Wu|Qj?3peeSd>gZYEMSY5W;s+3vd?T9Nx<8dIj;B8=^Y&YSI
z+iZd%>=_|ifrqj+$u$I#eIjA25y)O0ojh#CQgDhn{Fj&wZeE;GkDR2nM
z_ze!ZN-xxZF~0jnA=-qAIWAz)y{_Eq=C@=&^za4SSF@j!%9Zy^0!bneWsWu$4l*;+
z^g8x)cc<1{tTlT74!j$qnB>A%gXYgsh@!4Z8&>a(3Xy;IlLd
zcvI%GXG@$9-b(cr=dj$X9rt=snKcpjMdLv=bvV~1_FK+xXy%nq0mamz)NgP9f9to4
z4L73GKRK^VKMZfR!CnimrCwX-Q;wNvhh+fj&X!S+%@KNR>ThaCbWGecqkf6lW0gXW
zCEEkz1~f#EmC1e>>iejM?wskqneLtG&bgv!M2$3~j@=Hg!x@RC&lDS^4FxNZo;T;*PL$RJ_H`M&$zGMx{C^bG#ue4>u-{4XH=74}!i!9}WM<#w7G
zw5PbcF`>wO%&-3N=W`gxjorraha2@3G>*f6&hWwV6C7d4zV+~ju%;ncW4S%kK2I6X
z7g9d5qqHW=VvXFQTN1q|hh;Ngq%)Ix{h_6e_}gA7%#Y#4kn~&px_J)$2Qp@WZ&b;e
zDxy&^(zQsV1kfnTyvvbej5ZE)e7;s{sbe=R-(KY134c^?&>XyMaMeXJC85qfzErN|
ztmOCkPY~1KFSj-neuFZ}0v?|KD~et`nVWv`RQi1*VcsU|X${2AtF+Q`
z&FZyJG;*(l>+5ie&zMy;$}yp;FV2JMM(jm#ThY}gw5Jw#46z^4?Z(Q6fLzz}!%Dv=
z3$mX|#G4UiEbdn9Ac_ZGM_g#rTgFD?Hj8)CR!Oqrlq8vc7oC!
zil236MRa{({bnXQb#kiQ%oS}3Rhc>amQZeW2($a0k?$1N^Au@s#p2gihLne#T%nP-
zzjbL`84d$#lN%vfp^~wH0A{82%ouERB;^N(W
zZQ)i6WTyG3UC!(U9O#l>%-7xoyhvsy-u2}-l+vvsN?^c<_16jY7uG!iX{x5<)Lm|M
z9iwR-$ml(nm2?gg>nQ$O({Zwwvtg@A)%sQ%ozdUg*BMFCT;*17wvRb2d^^3btHhkM
z!4fP=EPkh3{#lfN@jKmf7oS4>cT;C1YmR=#)uCwnx-|SquOP%)oNv;
zg?fH`rzJpvtzS`&Pb|5Ais!Nak|}J98*j2n?{K+&flMd@K5CD
z>y}--H@mTia`_^$hPBI1r#T~ivJ=J=`xZnT+_c=9
zi&gL$8rv>>S#QlT=GJ`fK9|io6tFv)-WhC?GlH73*thAIV#Pt4B48r!`N&
z0WvL{)t1R-g_hVdip%}WxPk%jr9rgD)!*hWa45&M2DCeJpC($Ktv_<>AEbQ$OX-&o7
zIx0$HmKoBV)|}PrAlJg!iZan(qYq=~?90A#>-y>^d?bVG
z0lCS&dC*pMse#@ft~(bt}xnR`4pbz0@LIP^{7zzlfYpg5jO-1J;g>B~Q4VwOEuI=1Lh
zpT^pc2~~I%mzZ;D?Wab$C#Ut@*E?Au20+0@EuPp|J^FDVm;2s->yD~aVM5IXE>Ke?LB8$k2@FzGsXAvSJ7!V
z&x<8Cety$OQ7rq`iTBCzU(ScsDc)<8_)0wo`B?-cs;<6u!u-Na#EevnGFa?2U?na1
zwzvasQV+c*l)$JrQl8uzzB$*}d5XMz34BE03?~IX@RqhG>5
zv(XpL!?eOqaGlHbE)
z^(?r#Lb*3&XvvP0F-r!d@VCgy*@vkb1
z5{u$u=^juzP~q*IM0%E-yh9d`nO08P0tQ2R59mjf!R`n5oI
zwA!6Qd!;#R3b!d3x;u6$bdu;A@dQ4WKfqUJh|)4hcUE@YYrt~>a%m@!gr=pJe8zmW
z2hrTRv>NH=g)pit8eVivFJig%17KN_Si*&M$MV9+5f{hWQ4`K5egiWyqlIb}aW*_Y
z;9?iXdC5;4qBp<#LL6x;-fM}KOO=O<7}M>|ME*FxDpS;iq-W%h8M>dIM5q@M7v7{g
z{OY^`FP;=3R_kUQ!yG9TTMtf{X@(!yAVDksYY>_PT<+sv#jjic
z68tJsxgYd_sMUFhTZNnEqzf@G9uspa-U#MYQF%mNRZFO*=$c)K%;eXVr4YTp-Z^a{
z-Q9|oOykc@JUjLDb4@c(%sxK%=qra)lxjv8?Z@PiuCZt!OT~C^T3Ez|xp8>S)l%0fi!nvn
z_OyE~+G)4z%2JaX<=`vHFZ_XZ6>F<2+?o?+wkLEjyY@JgFdL%P-@qG_Dn=$Nqx5R*_hl_xsqwu
z#?aiJ0bcK(B(&$RgilK6&AXZ&FaI4nPQ9oep*^}C4`RjSp(AB544P;^Zm)1AI)(9_
zR2@UPwwGeJk;KGkF}C0%M3PRb)`{N~!nd&-;J++%w*6bQL)TwSX`Mp3
zQJ+%$?&%l!K3V*pr>M04WFLhROmqPLBmsW$_R`t>xBMv7ocExZvUQ?ZMkffy;ci#&S8K#x
zfWIx2Pgu6yF_*uL8KTZ7x}d!gH0~$-K&dl@ek+(u&*HeKevx`)_fEGk2OBIjdW6xY
zD-(Khg+K~Yh%-SH@}%j6H+h0&Zxd9VJ1@&fww(kcbVc12YZ6yG`Fm8;(NR8yA&oop
z>jMJD`+k+UPK`DaXB%g2p5D=0qcBLliVj2asp|~ss&b|7p3O^S*9cqagpH^u;ob>n
zxD_g;OPjzr3R9@vOIww$Nw?TeZSov=sgfyrrYJ5Lxe1GUAvF!ZZwhrCzZt?!lLc0g
z))?xsVf-%i;)0nKB}1#a+TUzbv8&s3Du_~cGiMzZRPp}A1@t;(m$Q0*3J0PkTX%?06YQ!zSe
z#mx7im2W1$0aGk97ZECP$J5GjxldW@iPVYwsA{w?XNi?&jz+%Ywoi_ArzyjzDQ>^(
z+akrs}A2%a-}1AA~c7
zA7n9dMRMrp26nV<^wh#{3fZhwdp)h-{DUVRZhG?gsH3UXmc3X#;w9;;(i4|cYDMXB
zSesmPq&8Zh*V-mfLAn{xHfJ&H81OLz(FJ}1>t6xq84JAI(p?iDG^B(ux?{^zdMcS~
zYm=AT*@P9>?5t%jzuoc1vVX6|T5Z{GUt&(Mzk-?S=^ryTHT`&c;)+!JHJ<8Z&2LnL
zTMMh5$n*31&9xr}mDOpIXQ;+k_**E+M1MQBGSxQbb^BVRWg9D&CN7o0+>8Sr^rfTu2d
zIB{u(kUkgfqS8Bti5zTBhrq!OCqh1&6ivCuLta|;P-4j|pb_Ope>^7U-Flt!CN51t
zkG{gE9t3@r*V0qRTI|=rh4U2K?WErg9nK_A2+x=qKiK^DBT%^(H++SPOd$
zbyDQFV_=(wT?W;JHBGJVEw*4?>O0=GuRP1}1AxEd{@aE^Kh0!Z2cq
z%ijx>(j~=-@3Vz>g3g+;C(-TD-z%fu(Ie)Mm4AHD{;nP4G5mo^6{Xuto&?ryag@Kw
z{)+uOekMP$8u)~LW1os#WucH&<5wNZrl<1soJt-pbxD5~(ser)eP^GE_9iX5Hzsup
zUSBdPp>(@5zpt0LlUos>xb>_QCkN7(WwT~te=4kgy0Slww>J@lzSvtjY2W${KbPNw
z8$xvyVLp|1acVWRJ*Z5gll*D!Aq@IZD$X|0xW&q(z5t$AW`NfhXW}w$Z+pDAxZSXS
z1-Dj_8tCt{)Q4hTT|TXE@z|*y$NA@T=P0V}C4%=Ht$#YtVpxcda!txILRR`_3OER4
z#MRzO?S^mNnp0LIq^EDXLJ)aFp{@3wBxyLw0*{SuU$K8ha`E>D*0SC1{b#Fz%L!+^
zVGE3q*3f8r{(g+BU)5|F%_bHF@HE@@M=0!plS8Inb@I<^E#<(_17(!
zny?J}#lW0{F8!M#hSo;HkWQ1}UBP`o1ARkpOcG8Uy6V4(d5i0X@9Kit;&;P;1ise=
z^5+EdFAjXK4dmwn`Ts1omgu%%9M#$NUhukmB5{1nVH){DPojOF!^<~D`&h~s*jLS^
zax?8`1>OOF(SM?6=v_~{mq)i_w7@5HNu$Au?ZlahL!&*JUd3+4)nql|bU*HBEbYDF
z*%af{^GZd@{I*_qT<%E5*HmWU3n9U;;?CZ9(3dj*Y3N)Tw!8PQSob~k9q=(vq&js4
zIn5dJv)Wj!eKJ#}n(lE04paRiJ%gSv64Z}>k#58K0Qu3)&#(qB^~sq6TjqPEsISAl
zOjwV`2G=9VK-^ddpLT_`-fjMRxUG3~O0k$HD@(csP_|?-fz@!NR@@J6qR~M!9reu=
zzZI7YdqkXS1kR+Z&eJXu*5@4hp6ER03#S|lK>7Efh63L{O_vjCQ;{H=KucZ
z|304wQ(d($Yp=a-d+oi~ngSUy3hj{WdGSvA{u>>C8}69rBv~_lYs5MrToW$Ogp@^=
ztA=HD#im3(ip-UFdW+IN2Gz3o$DcAkEt2=RfH8!sItOLhxz
z|L`}4WUXCj{!n194;^92>sV-h55M1w{H|SKUW?yr9V``RM8oqX&p7MrnBw_p1kvg9
zpV|A7?PA38lV=Cm`h1)h5t`%Id6cXTeI$67)_WC`5SuDO=J4%Zrx5>2wZw0e{0U5I
z>(A7NHta1+{&?1}Hpk@=>3KMF=O4=C9?Em13PYIeu4U5W?OaEkQoDu~`ZS@2jeOf9
zR{I5!pLgm94)-^h2{uOVfVE0tLvJeU5p&{)v`0#hRBJs(jj5Lo`Mx|OO^|SM^9CE?RC@gew%M=neOM~31&Y3chkxs0_*&uF
zH@y1ret~=3u3f%U4V>dplhjbbZjayWtrv3su1;`rhfd^WlDEMl%IzXI!tLhq9=T&u
z3bcYxY-wJtw1R0_iCk3iA>W}b>dw|K_25OWV#(6V(6i!sf;{A~c5W@mb8ZZDWGSZe
z7KxV_pZ94cQ4Va^k;7B1X2nJhMWnL
z0v_I-2d`sE9NL6^nLDB+2fzIZ;81V&t7Ic%gqX|MUeY~2y7{N+92B-KY)Y!CF%b9lkIJ>t1-i>)yfzOM)!7o#)*#Zl-d8?F(
zF;~PhZB99pCvLZ?OWHU&6l79D8uJGUj+R@}{2A#i-Qih=mE$n*(YBam>>v!w+?2W6
zGYnX0{3C3XeB->p%VWPCyV^Y}d>cG9isecfm%6mse}Na1N}V{W`fJ!mm)x=j@#GtA
zhkX88lEI##)MJX@oD9vL>|_DKic;L1=do9L$hQ?TwVvchEE6Jq8`^%zE9<>E3$?rH(LEcoAyittJwl?Z9}G=&S;S?ADLejiqPH{dyN?jjyaJ2
z24oQH_a$~?h0jNLm9YoZC=~souxk`1LpxDm#R)q~$mAVG&#%xIYdz7Hp
z5^m=)^IBkGt&=G``QD_@M!9PtJ9B%{KEpb%ktslhUu=Xo6mP`%ma=Y3ycXVxg~9ZzzVyh>%}p6%1K
zQR8`^TH@r^c@GsCaQWl)`5bLnlQ!0~meFSLfd~X~0VM_=7~H*FSLF=7&~){f^APqG%4|7BXklj07N~9lI0AmI
z_IvfZ9SLbTs~WC5wW;%%^M}fH#oTD+FweBqGN$nxY%7YiK4|T65abUv_%`x2LZjD)y6iLx@rYh0SaO!*^3i=
z3)?W_CZ;uXGA*&0$xQ(!zkQlX`>mWdahgdjv2s;;YE~ako-@sq;z7nc(
z^-G?%E~O=bQ(D(B$o4@l?b)VLeWWRUIIRIsqWnUT(>$%FG_Uf4~+7e)AczWKs2=b}ok**#i2c-(|hT)L=_LOGwn4RvY_
z$Jy3W%9=!D*zDIw@lG4gO~u*ybO~9|q*5zqpC+MG3Exaq7#wJ4ts;=EzAX*1x)#j3YeF#`7<&>G+_5xB`k
z%iKzoH9SvGVxH*KGcpHZBz9-$`->N*I`b;ECC8au*Q(<+f@}4tm6MwT&>MAT1IO~5
zI$z$&>Sur@HsMX+i@gH3L)H;)qR^R#;W6*X_2Nt+gADPHAj
zE2}M$yfiOyn3q=I81qsx$_&_)5UVLy8teK4r(JC(iRe1DfheO6Ia+k8%-)miHzOlc
znxFVd#yK%%QHzPs4E>|xtX#f_Ntto%E_gijnQCeVrGFXFvYMGzI-MOUmg_)C{%K5Z
z00n&`aN4wXCeLXyt4jprinDTR1JB9v)4^X&fclV6^Q|={7b{oWxeCA3rxh?aFr~Gf
zllnAuRrob;yIpQ?F<0|dd0ImYYK-$~1s6?Q-O8U5xD>zYCd{D5tOWS)Te?#GQd}R-
zK4V;wDj7gr~jX81ee#WJ9nYWcE`+mxya$lW84|Q{B
zggYy|e{e&JuMh?q+&TOcrK={|t|+snM@#0jh~T@Oz3Y^J-Nu&b+_|;XzLC>jXeZFT*2WP$;=FE#G
zd$w}!xRt0#nVG<01PvF%@}&nQA@w(ht6LNfQBWJLt8p4qW!7PvZlopF*s;
z12!t7!>pH^T%?zSH4=fDo??nNMriTd;}?%Pw}9840rl0v#|8||37R6<`=Z$3GU=$m
z5eDU~AbQtYz~kN~^xtv~WAsGlI;nQGP&LmeNu{(V(Avc&@R!mAtevN)rA0WA+EVuq
zaMXo13(cmMx}P{|e;f1fgbphhy>!_U^L8ssQ)yPUf^3^onr%|Pt6<8rd!ae@+DeM#
z)Q=f@ux)maDTm!aQm`?;4umXjL5Z}a5NJ)9=)HOqZ!
z&2rx}CX$*jzeBM6!LQ5=a<7+4Q$+6NQu_-zH^_5>9OPAd5bFk|xrQlk;oobmOe=1{
z>Cy(sfx*RXUQKMZ$@jFfMMZ^0vI==pm%z!>-eX!FZo+Hp3f6l^7NocxE~Qi$V(?V+
zJe{Yqm08WvM3Hi8ko6Je3C(Ps&Qr9?NP*;RvMIeFqe>b;C6LOA_3RLOILOq;K`-@j
zW+|R@hni*P13s{N9i^hH6C=(uZi?pOWQfQe5bD0VhmZ586v%wiMx)ElU{?weFmf4kCW3=
zKqIsFn>ByHpq?A>4I?#1DP>`lzus?P-_WASSQMParAJVbkf)g1HW;v??
zrJ-X@Y67^|Rp$fluV&LI3HLgkWnlyS5~|Mix|fp|MJ!u`0+87se@VHPKbiD1VBNQmv5p=XXM5
zX^*$D+8*|#RuHi#<2WtrJh%%Iss*@;lQ_yotIY|R!u$mtAZG<2fg#t#X2{=WR$Zzz
z36QGvw6s`juP~&4J#?A~=`YknW7V-y&{#Y)7Cps5V<8#_&d-Ep<}>l_$DAJpdhpWB
zZeD_Z$|C(_hW(qSYgnxyXj7I3p`UoWIuX{1POYS$wzuq&krWXZvDq!h0v2!J=E)Qx@
zs|jB5=B{%kzzDPyS%C7)dbYF(D*e
zz(;qSzikK$zodfii%Cw6InUqz>AuG~coI9R7*(dF9!v+nELK^}TV!xczb0D0D}(Bjf3;TP+q$?DX-hVj
zYN;2oLgF2h$}rn=m45NO1}UZF3NHo(8@p7D2pew-L#i@6)=5K3eP_%H)AZlggeug&?t1^`V{G)_tE`#dL3eY+GJmhi7%RCZL3BRnu)C~*Gvh;W&)1cdU7niZ+
z1H~JKOdg6KJ9En{;QO<43)dnW!s1ITw9L}UW#nXaWJ&OLm1Gt=)F!~`Jv6$=q2wMK
zt*B9>kt>At%T$V2J5-Mo=ds(cZmsZ^zZ-6K30i%}l18UuN-|&i0PQZhloncQ>6{i&
zvdVfZZ}L{+B18w;P2AJ(gj^unNwR7I5qC^@#|JtGg}8X+6a){9)_LIJ)s`?1fc}XO
ze#!${J!thuEe-ReM&;t1*l;f75$kgX$d`t5qvnsyFMpp#9O8EDG&t?q%Aat6XmCJO
zv0MsX>p}l{j@Nq7|Ew>F{(toy(Lq!b(f_jij!$)}Uv7omyJ(Ytd67Y@dIbBj{Ir6>
zhzp6ii4W6$u{h!yZNDXssP-<)|Dr-K5utupj}nWh1i`&5pVNLs{Z5_wAN~pTAB|9d
zEs95|Ux&%tY|~OmPBhqv2bSfBxu8!s7wm-1^v}4U>c?C#yLoQTN$r_-_^;rVX;j{{
z3Q9kIkeYv@i%vBY1!&DJBm-|!>p_G46IjY(wKM^{7_&jId~K9NDcm(M#-S|SmFUh?
zmPg@B8_^cdW2hCiU34EVW${$_q5CtwfOG8Hn0ZKZi*~s@z+}K5RZN(8sc68i$jAue
zv`4Wle^Nke!769DcwILc&j$<@PEL+$u*p%oa9Sgm$+LH{+iT_Mi?*f3@-Ihoav{yS!lDG+
zU2W{zBnj@W4yUpwXi*`{7ZuA1yWn9s%nlXHiMyHdfJfkpB{80%Om&M+>jR24Kj?1)
zR!s3bA&cacZ6w7S5Z|I)%TDI%&JRZZ%QKDle}qWBrp$mUxI47?!;Bj}u9A;eNfy@E
zA|H_=2FOoqS?bgL@H=K>?sbZ&*<#2hS=eFgD1P@ZG{U?s^#5JuBe7GpsC>0M^rq#w
zTHy)Lggdiji#sz^U}^4tx7zJ4=bVJsyv&@kYVSRpBhrJ*sHz|un7Wq!kF0h0haNIp
z|H?U+~1c+MHutpzu4@<7M`(r>=(LEq^X7
z!^m=@OfirzCz!GTkwtWwbyr!GGxXMp&QPJHQ*D~S(!4QiH@P)P&`_c9XQSmjz0Uw<
z?Nafg-O!Qf3HNy}<4spbJoIB-Dx-I5LIbzU7voX}V8!a=5Hl)Ov;w1f83BBKR2V7F
zD!$7#-q&f-ru)%Tg?DMy%(A#2#fG6>W4cowa=Q;>1^U@0cZlcTUsV|@aKE3IdHY`}
z7T(0&)2ju<0HAmPkN%C~?mV>vyHX1)=Ffy3BmEuL3s&sXAFs?+|Nc3X4!3fO(2G3e
zbCq6K1hQm`dujhMha;_{eSd|i1MWf8mFu^059VcTDbrd$WG8~kf?g(^3~YR2z9dfQ
z`oXE}Y%#Su)F^isB-C5~3x4MVs5_g}2Hef5{Jw4Sf>pMv0LtU^E^qoFp!NcFUH=M~
zhir@TcOSAb+XBFa)_w)Ct&kgbZp?#K8N04XCA*pQ7+|d%%c-+k=QexQ!!X@7jqv4mEIN;cDWk+UR~!_J^Cnj
zHJD~ORj<1%&L_uRfUW!wCO^Ff>*lM-&45wz0o(Y%bkx~<5n8}>A|Scl9rEHoW0q?I
z^7O^rfIT$lQ*ndu?A!roVw_bOOObOa&&g%-*jc0}`V!^L3&c3@sZ^%F!YPXv3|GFr
zG+ZjV!buGSm|A*?Q~!QF)1GZ&QXC>h9`thZGi#YWPd@sgNxBiJl$g8=^Sv
z%7>%OsX$zCgr?EB#Hy>SNlKfHd?rH67Ol^g7pKst%
zm<$g#`5)9m@;+hh1pk9tcp59NNywdtIIZ&_yh%sR
za{gClxp=QxGZ(|(DRMWwt<5`UR%RBnWp7p~(y#k)9n!Kl<(aQDwAMZc{xu~#i#?RD
z+>m9$io#S|ss-X{*egphkijD|)IU
z_uUIW#$?|)_|?cCpo$S}v~a3O*r*nc6svyn07&~`(H76Zjn5Xl=Ib)azD|?YXTMp^
z>dUpg)9F_(G;sE5$!|;h;ZIX_e_AUr%*%84a(^gMre`zdy6j(6cn9x7KeRHMDw_4T
z@!82r$69@bq?W?|`XrunEE(m;j(UI8$;X!#=)!{5`<2I8KMB~pd2f_c{SI-c#S;SL
z8ap8*8?bBe9ys)=Y+gaM;&EAb=9dUV%%+DV6Ov&HleaZ{_Ol%nDb|_rK
zutG;DuHo`+WfMK80_u19uxvr4;J`&?sTPu7oC9=R8PzO#y)3ix`A%9ZPesfm{KXpK
zwS`gvZ<9pqb~;2}YJeP74vwU~uO)7d_kh5#BZ8eoV
zBC}a7WGfHzuGkG5lyD*(GGUB;4*}azrmziKw3C(!80LrMZ-y-QiGnuePY}CcAua4b$TP0yz-CDi7;^Xv8|~F}{!NeskDI)!{yS
zAF`lN{*XmUi~>BEhfKv)VYz1amSEP`x+ju_r>~$OL$O04#9?QoDP2xP`(bTc=i@Rb
z2cnuugB=Py-$}aXL~-738X3(FAL5;p%hh_qbsbmdi^&W17LQBFZyK_S#~~fRyNOLI
zuktP0TWC;-fy>^PnA-^&VI|HY7nR{MIp?QaRym(P>~?kp@VBk0GL@$}Cv0<$s*JpH
z>JNE7d%V4;e55kP
zk#)M_1Fel!{w&|fVp`b)%7KtmyLVui>t(Qd-Ap
zF9ca=NuN&TMl05$7xg=NOOH(|9$Jme=*ZFtm=D97Bl0-yLGhH9)}~-zTbb|)W`ysA
zK35XDl;y`+XvPayL)qKAXfy<0Q`Zmh{2aepQyKE{mqN>VxvQ0i<
z_ONYoi6zfhyKNKLB+_EoC%Rp7S1ws5w;Ps;XjmqFERz?K4K;b8#K&zT+azL_ta}Sq
zi9^f$EqwXcGvz<(`y{M}Wg>Wl`NAexCY#7I8G{IOuuN_a&=d6=_26B)WwK?v60KV%
z`{tfg1;hH%?GjP9OZppj$)ttdR>>OMB(h5O%{^m`P_mF!vhcsKO0b&|wn{$jVU-lZ
zD!H%Hkov?^d6`uiVF_-51kdf{CoPn-{{qRo`M;ImRWC@z@PubYV^2W_%df6=Vq6xPr%A}btim*wVXP|!pX1i;6_430=uuzFrFZ@{qhD5F>#v@V%7SG#cIRr+;C8onoz3y
zUP#AGo=3X&OW*1~Q+--X19$W1QbPh_FhaW~T!4<{b0sV6fk#-3ZVzk^+XKB$SYQuW
zPFSEhEn$1W^kaJWJuXw}W)6?gtuG-y2@OvGq8|*8~sW`%FHFeR|!)XXtONjUPMk-{|jt4#id5t-lwO
z{^lpjf}y|Vi91Mtd*b2$ApQORHU0gi4;fg2IYWP+>LC4nETX@GUDDsvHX8c-0O{}C
zP>i@!*WXd%PD6iB-S|Jy-x-|Ky>XTE)FDHEpK3+E3baqW`|ie`e0=+-|DDI1yxcv#
z-sIz^wW8tUCjT~RNC_Gk{%`Vx!~ablZ>6M$k;iesw^F(UKg(Zi${_XMmGRrIQTlA$*oDF$QZ4XWE|l)>&#trF_x{iQ;&#I?eq+3uYMi)CJ^?Oc#h+DJ
z7E0`2OnN&7!t8+VEhngOD&kFHggv8XWdL5DFN#OH|5blrw_iTu5&tOS5jVAsNc~Sd
z;w#?AO0cI#{D0^VoVJJjfw%p0fB5JDfBt9w@Fv3_9`*@x$RI7^He1*uzF3@I?TsrV
z+e?Y~1U=$YJ-$C>cunB@{lCB?t_4MNRgMp=De~
z$g`?b87Sa97I~R;x`rminLt3&bof8_{3v4mWB;3;A9sa&z_yt~`v1uDLtY=9y1D<{
z8;`x;3@-3r`{UtP3;W~aG725i(^w15*ZuJ>_~T2j`Q!6ekG{4pfj_<|;^ilQylSx#
zzr|$?2tbZ6zvhpBd|S6aUgY6v`7iwOe0+`0e`9{KC-wi%AHS#DA77-)fDrr3wg{h3
z{TDp)FZJ-qKd*D(k3I6`|Aj|B&hW@bcB6bf{O!vPkNo6~Iu*WgZ9l5pXRk&)^0b!f
zu^aV&)E__VH0?$Z@4+8`9WN;Tg`fN5U4rh9SK|^`MM=aT&t>TT_=UPZ-nT1}&-my5
z_==Kac@$~KUC23>Zp=LVFZ$!(`LRD<-z)9k->gLQH~fgl{c&dOsIi}LxHql~Qidtf
zLf9Wa^iwY5SY;?m*v4=Cm%Z})e4qY*>6M=l_R90*mEX5lBg_3?_sX9tH>9KCmEX0A
zq}d1M^#55~$SZ%}mf`uKce*|B6(xMemU2ELV{tmrgS9rB4hUF==Z=isWTZ
z+e*^l6#VdcIQLA_vRwDcH~pojPkvdxdqc!4|L)ej9$tBSMvh*WbKLid;gx^30$%wN
z{{6|wrTgD`<)x?L>G4kbYslsPj?0MK5-N7T&t-h@mt=3m`+z&mI8FIwUaOBRlrQHI
z57I3PrDPR64#ydPjOYgYwJLVmj|U;&tnex*YMn{WKF+wk9?1z4~byXfu$_Hplj9+8@{E_WhQ
zt6vl*6y4lJJ)E@0H|_i!HYZ2!O+|(G=pwtbLT^vSzKE7^
zfpHl%0obPSk^MZrC+*D4Odf)DK{@uE#6;W-!W}i~5U`7z12Wwlh}vM&3QyQ%OPOs?
zzETt=z_YQf>)g8eQm@8zxz}&)$ex+5e331Fgg%u0S!Pu%Gbwwsc-6AOqQCjmYz#J@&?K2x=|Eb57{H?(4ws*c)qj}TR
zfa?8ChXyYL)-aW-_++|rFxx!TAqx}j!{`Rxws%5^ijhyxl4rj8%(f?*d
zO@McX{?<$Pn06Ew?lvqn?E9p*`Usokm6jGaaM(*akjf4ryErVW2e>hqzjAxO{UYCJ
z#OfZqjr@k{fjOLd;X+@@i&Gqn{fNfc()Z?E=}X&(TurOo<gXvNJ#h!4-J|usW}`1!m9u{0^I@+&=eT|CYgw`owCQJau!~Kya2iH`>u%ZKjJ;T6
z2YXy#ATJ~8eX-E$+Eol6yE6}`Q|7ReHl?o!KS?4h4B%vbDUQxLHU{0!6_sCpu3{yv
zym8SKu-b4AES^(8Nn~$Yi-iEri6c&@aJFwwW!~tT%Jl^wT^cI7N0$fOqgT}p71tLO
zVNU3K$!N%aOOCG}){@XJeU(1V7QDGiw-@MlkxNNvW{O(`H`s8_VTu5J&0Q_NR=mpf
zrLU9!!l&e0+03#;_G`Czc3y7YXliv<08wQ|PY#5Z@Wo9IfK18@&gCwn8Duo#R$(jcS2Kp
zwfScEp&4c0e5=m62lLz7w`992wspnS=1k<)^1Ot%{XXwVP>O--IhaB=qA$PoM7$m57(e1wgN7adQB2wP-<+W5t<7
z`*OQ7sNM8Zd_R5>A39Ns*jRwK+KruH>@~#HF&AJkBQ`0|yZKN-OQ-B^u^F-8sN}Iq
z#03k6jU`2{E%wq2IS({ve>7!>YuKGcK<~Pm47ybGNIuoz~R}
zNvr`UxmqzhTM$7xh`0%akuiJR!d9GW=Ml*ku=`p%L(6CewHCrs`S+?-=u$6QyQ-`*
z&H#?^uJiU!w~JL`(%Obj*KlW7(mMLFFMEvf7ow!U2G1VLFbvKuGV3_9@kP%^iUuODxUTxC#Kd_YQrMI*_GX1fbsnqJq
zuhTwH&Zm|~xIIT#A5IBw%I|J@#Eubv%N*Xb6hhXWDSM*Gm9T@k;=V(M#~;H}
zxd5jMkYATz;IlX3=JKsOyJ7g}kkMFXls!>MvXZ36q1~|ebeU5XRPr0FJWp?%uITd5
z?`B7e677=8bF!l8@=tbz7|B0P6gZ8C+;g;HpSr#42gtraL2m9LpITtGYV8T!iqPZs
ze!T3+#+gA8Wd&VEQu#~1=ZkSy3uP{SL(*<(P|0f(kc|>Duj2|y
z?WsanrzEtY-yjQkAcN88C7@4ac@tl5s5d>5dElpC-g?=p^s6_;j#)hBCv_ITY#q;k$%p#Zw@J9ML1#9g7jS+X
z&kX`6^X)dAH0rwuYcsnGr#~XUk7127r@b%MKz->Qav3@xdr3}1Unu?SStwEHl=*sm
z(KSrJ`cA^=Q2t#$bbb9*dcKR_$cN&LXFFfThiR-B3S+<{nmkhgQ{(f^m|KU5g#bUA`uW(OjS
zJ6pPxNi!LH9M8HUWvl#rgqG|#5d^w590p}R;3^q
zqula6wCAOukZOir2klDc^Jj>9V;+iH`%?T}yOpJ)g>b0M*<(p0N)fY}G`hV@YX?1p
zdP98>LmAjN?}YE>9l@OJjaut+h{kWfV1`eaU;(9W^1JzU{?>DZcTgK6=J1iPjF~RY(`{
z;uYoiX^SK-xvKoG!J=%lS~?zAo>|Wn(|W-@TIQR~_m;Rt^G-;e0JUu1DKcsuu1i|w
zo|7;IIBjLU?com`&sKIkj=c8b#Y;-_X|%oMa%gnJWwdEhEEYz-39eRo%WCRfJyMtF
zp&j2|ehKA=AlE>Mz3zU#o^A%e?yd!6Qs=9Ars06{foto@(WXc~TBxW>cCtkvCz#BuAB
zev$V`(oOd9Nw>cHaMFl=k0d28dL-%Aq2rT=-!(pI*mziQQ^zNbcsW-i{YCfvdeTr{Exc@qC7vJ2x2r;YPnn$;0^syHeB6e5Wq
zK|W{!nC8L_szmu{aCdv-WMA?o9!92cGqOVU@CE)thi(=TD;%2MfkjCFan(%+0a
zZ;T2F;sps=@DPP1Ze3BxWZ;eP(=mH_I@Mo^lQyoy+05MFWChjAcPCNr$vFk--J_NK
z$;=&{q-JsS&I{gHo_=ph&YVG2dYO+wU7~YCQdxi?#)^LsXaUp#T^OMbrN0>8fpJ-`
zN=Ub{*{|dEW5OzNPu|$Hx2Yv3T1qMla>yrc32_rb9dmS=2YsMdd|RIG$^=iwgO8El
zL-u5G&~F~c$3#0TOOvb>J7b*Y^#Wj35>7Dl8t*5_lx1!=McN*URs0mU-ox3w>mzT?
z>kU44eq8Ta>7U|#*>f5+Yrv6f?wFWd80uAbuxDxHAc#fE8JY(j;uw}xhP*kkcfRz~
zQX4Ysm*-qhZ-YA4^cl3#Zv%^qVnCy@`|j6E=p)PCB_I`I~p@?9Iv<#?Tr
zG8*w5d*4qnJRlUhvDeA&o>AbylM$uCvGUI0AH}sjpAR357bk)gBSX3
z)!$jfJxeRpQ!zuR6>)>#N$adN#njgN{3<8Cb#ByKhCC@68*()MEix+N{>9r7RWTv*
zW^sCGFpqX)ETMRDx0z%TnbaN2Vx;mqCJkVwjeMiUPS^~H}%MTxaNONAb8yc%gg
z(&N6^&;b6E$Xn`Xar&f6_0(XDEyl7wKX2?^pVF`O`GsSn^rxPq3+5W5d)FBgFiIJ#
zOJ{*mioSl}91zg)6DO`DoWYjnX2dqmR8NgVtH(C4&-bSiro=z}5QxCB7&9ul#ZQTc
z(n`+6?tAvy7eo^z$lPPcSA-$a*R!|eQD0QbiJ4rVPjaqktlOBaL~)tXb1ixv^1K1*
zr<(zlH8fCMqPMNjKhdmhrZKZI*7fs_vaqIJIJ~3n<$+FsyNd`imwGU>?t0BiShmpum--%d6>|6KxunB0t@b_>y>~OXX`*
z7N;wnO~8%hO~tLc@8Po{iXmQ)^j*`288Zf2nB
z70oZZ1?(309Uo8@2`_g;hMm@ze^TogIX9x-(=BMh_B*m52RK46HvcV>Qvrodu)YcmWH-tL%c|GCfuXW6B`VxLVv4MDNzn$o+sv9Z`bIp
z7xP4V&zLdN&q-x19Oex6rSZ=Ev0=~YCDXe(WB3EONBdByU#~qUJ}_ExPbbNJrAzYE
zrVymc>&-vmQ7_~)cyvL13ZJbCBCJ5|B-x%izj|snsKxD0RTOh`=0NZ0Hn4y@GbH=9
zqFPQ8_F4SkO4TzwD`76Uv+o_x4ch)Q{+!xui563U*OV}SI`z4|&8a-rZqhCv=8|$h
zV(u8?ziW0(yup1r*Mt8qOYPCIF~ErgeM8ig<`2yXWcB>5%s;gprQqWee~GcXjdEK{
z2oKcT;&cNeEBy-%$*ao&&H?P^#;|$1q&MhVmv~q+pf%INQPKh@!%2rbrS|y@Ho`BZ
z_OXm)ye*2_GioeJPl{c`TK^pB3lbe;qW#N1_+1I`^jx#}hE}50Cqa`#LJ95XjQ7&{
z%imNvfz#*Aj||#=1naG6EBANx^5ynZ`g+X3)jw^`85-68k2<52J|4OKG7CkEx~4Gd
z6@G8@@-FpoGI|K+x;@$kY4{3ySTnU;UvCaM3%>52%jx&htcT}wT&OSKY%f1NpX?U*
zSi%mdqKDlA>33^rg{aGzZVWnpv}$v}1~FD`Ac};OCTU>oqU
zxCh8y$xT))(+YdqD`wqZF=J(x6R)|mu_n{)m4a2USH6I~!uRU28WVAnRbPdjY5cf8
zLUV7VPw^hsS6#@k^NXCUd2@|tE149
z?Ye9?;E)0dI%d5(pN3bn`kF;=?_+*7{WWHLNxId5N-s;)<_)i$B4sF77wGF6@6vmt
zAG!FHO^fbi^~--Q&!N>Czd3||-{34$mo%rLZ%7mu>iz5Ef&4Cp>^$?u2Aogm-!(tx
z;hV3mUzVqXB5#WHZ|Hk*qxnM-vTKn@ln9?gZ}X!{|6XiHW91>l-;W*AFWD99%|EF_
zr;jCR$cK!4Am#>x5>LC8XBvbE1O>*Z0gHY5lI@e?L(kSf{jN}r?^W}R@x92L}Z0PY;jlYGRE(PU*=99{%bIaV%dFwqq
ztwG@pi@
zM4q)fEfFk4{9aU+@HOs`7CptTx(7nuoSU!DuTJ-sjmme^X#N}ZIc6_DHQ?Bc#wWfZ
ztU~@ArS_aUHxVA4A9o~>&4f7cI=-oO$luGCgL$7D{AGOSdqv;~uQ$S$ANcbJctii#
zFe1jO6gOAr%=sbS@Q1ebrFJR*k-XqCBYXZiPsc#w@Uq{B2K=_GyFIDkYM0jgqHV_6
zy@ZXhwZl2Kme7j$jYpCB1QFq)cT)|5&yZDwr-j?~*wOp;>OLo;B&@{Y3yZXENF}P{
zS_=>Hjr=eNPO+WYcjH^Pz(avEaev@46ZPm)4UZ@+G+FbZKHU1)FBNC
zd>@jGLH5ySRMLRIpObtA%ChDH%t_&ES)m)62IMefarGarAt^
zJHKlBp?Kv&Grm8e>lCB?q2ef!EDgKMXj_fD1zCpAut)4P%1T%TIp{UGkvN-H3d_?I
z(+QpyYDd@8gyXP2m|Ab?)(2ERtPR+U{~m!oJT}xZ@NPf>`Oggb|I%My%Ti*ShUlY7
zZ)`J0!X~1`ypXxqycvyWI;br#s55LK8P-5aDx}BRdvtol8pgVv;Q#olPQS2pI_4y%
zM>K?WJG~8l?14tmVy3}&1**DYpFSyGd8HoXdiXN+U_eIWp?*li^&HV7cj)c6{~SO4
zb^Kr*dG?O)x^dpOwY$xpIClaQ5uC>+Q=2nj!Q_N-PG5hF^BeQ29fD+eI;?QE2K~$c
z6y5KvH~|zJd@P8S;WB!!Q&d>i1~*LXA!}okkS{B&|MgNBry+GocF27UDeJD#-@=bU
zT*Em&aF9F!)i*x;sot-Se_3d?N#fmCXs8vS&;QpEdNAhSC~M5WGd%wjX#N{359ZL=KPFo|f^*r^VhfeFoC8cG>RT4hBwr-*i)cWH(0{EUy12w12%p`+e8zv>$ut
z?5R5K_x;FNz3g2|C)IN}*$JNsLWTtTD)igE{<5`}ba0|nnc$*bZOESH60_MfY
zMoG3pY~ni42(MmNm!fZ^_pg4u8Y|QH^gY?eF2eWxus3Cy?0t^8GI3gz+TNHW86L$X
zvQ=YWd@9lk$;;67=Bv=XC3$0KH14gYFHX!8jX>Xb4DaO7JEAv|^mkM#`O%o+y>H;3
z?g13>bxFDb$H&`x!l8Li!ai!#;qZQ(lW@(m85{c>>dULwe6|a%!k;pj{px$^{OwG!
znk`bpRr^8MT;Z84GiK7K>k*;~lIpZ8$Pa~IqL_9CA!CcF&7h7SrC5w5$^-Qm8m%Ou
z4c#7WydyW#clYk%u@N-3$^yNm#`_C8UQzQcx({pXV&%KXxEcGt`JsoU7aRLfXz8-f
z8T;m*U6{VU2-??0Z4xF3Z}dz!GxjuscnV8>eV$3`uNqEJk#Aeq`TOQ}&~Ng@C+hml
zxj~C*f}{pL=w240kFW;VKo-ED?UDXyULZf#{2b!S=AICr9c4iLM3dfX_$%+18zi_(-FFr%@kiPdXh&bo%aR<~1=)vA~{yR04L6
zQ#s;6{VW8q7C9$@9lU*AUjvV)agM!QKhJY&#*5#a`PEA!52Vzm9p2>m_gMX`kNz$5
zdtuML2S=Fj2GYeM|X{zkI#7V{(s=iylopIdGUR5
ziWlW1e$|o46OSj{Xg1mV8QPz}ex#f38I8<8v(I;`->C%H1c*^KfU>2~Nu==aL}UZf
zt%aHd+!5J#=H%2P{eEdzfVl9<8VJpA5&)L;d!}5dZzjj`NP~sJ$HYcS=u+F
zCDKEt^y3~fuZ#4ssvotu_q#|Bt0w8cLq-n~yy5)+i{BiL{91Kz#*0sUN9SaRR|~bt
z`J40o0Xol|{YAgs@Sy^A>)Ad!Qy|p%|;wo>$yxdtY)gSghcd^>F?&PRpHOcuC-NUz!t=e<+tFMpN
zpWHWc{)nQALLqqg;I{{wzdF5V-Zs$J-;+H!6PEGZ(US`h_s`^?PP+h()2?7IrW|i&
zk{>=H$Q<(co2uy?AAFL9Em-NEHEqpDrUPM$8)wBH%p0TfZb-%b9d+%vfqfCEN0wu%d!}xf1AdjexzPp;T&8I!
z=4-67G-{AM?L+LjDslX+%5pkM_l6KEL~h{2e(Ym43QF;XTNO(*EV^|Z^4yNuY)j5q
zmJvN>`fnV+t@!Qm-l>34|J;D3s;9a6{Y>A
zb5m3?jzOPvr0r~5z>Ri~Q4@Z_zV##b*+Sgf%N!7J1>q^DbCC=1x4k_kRMgP>H%DF0
zUhMD!zE@}gDAFT7&Oh)``9lQ;4%GGw9g_Hn1-s76T25;%A27;tytLuv$tup8O5$L4
zFEBlrg^Dj&RGdOZ4V*c0?xI&OC2hRmbb=P)bFFR*i2G^WTHzzGY#
z3y%W5WVauGd5VNOh{0u2MSZR^Zh+VA4YOnhP5k}sSCwrgCUxK~Z1b`-(77i%?da-d
zu8aiu0HZrXqts5#8??Whsnoa5E_qI!fB9G_M)+2Xe#9PH5cO@fQ}bT7rPV5ul|58Y
z<$S0}*`LbU$35jnp4x4`##PQ?qxEd?M^eqInA0WU5Q;w=wCwc`-VA>sGE{E3V}Ekt
z3-0y#D1U^!CwhkOGT&c~nz$=dof)r(c3Did
zr>syi8=@)ec*4_=`vrZZG19t_|Hv9>Ffo1}p@Ey{umPk}D6%X^_dtT)P^Nks1W`$94NftR!B)+L=&
z3vuo7VSRk%%o}$srIsfLxY3~dF>c3g<(r%YY1#_qcV+jfb2?bj_5@%-5^sqq1{X%4
z1kN@*Ty2b7%8BVx2FE;P+VPYZxm}Ta724y@eJ@}~N8o{pQ4a1wH3%Ec+v-dEn~Ix8
zQbU_vi=JptJ3z7G!x&;b{b<}E{igd(3ZB{*b2aYrVykJZ%N#5?7LAiH;uX`k$EV=Eme{o2B2cG9El
zU&A5))c&toGqNl0W5{E;@N1hKbHp~vp=2VW%|mDVZ^Dh|vjdd}-?$!8-Z^;1JOoMO
z&47gQ13j5jjNiXXUZ`04#NTBeb|($zS=w$udw0mj<9sy#@?rN=sI%=wx)X%Fd-*i)
z>lTjKb7q6DOc_@e{}pb&;1&%k4QxBV?IIt9QKh^5}V4%H*;;Q^gI!W@K#=?L^I^
z_N47Y7J7Um`ks#1vu8H!eNU&$vcAPHk4CP^!u8%^&VDV_YmQHeI&Sk2=I^}IX3YDB
z`w#2$f9L(*>VG$+-BV6)XuLM@D`)b8F*Sl?o$=<*7k~ei^Y$-1naN-2CGOn!zuuhq
zm9t`7XyVzEp3F2IbGCjo&p7>d+!&4cs4H1yuG^eg%M39kZrf_~_sekqsp0-pPaFNG
z7;xN~Qnm3ZN0>HWU$-EX$baW?<^+zqryKJVjd!v1?pd7bFzvf{&ymmkL7EM*i)Q0o
zCgQ1W=&OF^9Pw3hQArDN-$%Z63&)gy>l`&sgHPny&p=~akr~6rJ7nD8ymue(ymwFL
zXY0M|7H-_4^oi>4MqElnQ(0*Fy)lz5tv{N{%E4QnJDN9k{3g;TQJ-RFu5Mo3Ju5@*
z=s7Dh=IgWaM&$*Hrzy8r;I?SlpI(LxQ=V_XPQ~dErQ{Osa)pX7p9Pi7RrA}sawaX>
z5{il0A;*;2d-8VnUgB*UrQX|)Gi7@(8@#Pf9%l>X$5eOVK6N09c6-xy-*O^M5f0HkUi$%z2NtF0D1Ygx<~B>zH%QOO<7B!7mf_J4ef_l_HZwOyInef0!1AJ*pyC{Pj{k?b
zcaMvz-2TV+o|!$HfkDAR0i!}jK{*~Or|jhCNHYqv1@V#zs9}~nvHYAeJ10H$IUI$V
zJ;QJjb;J=bg_f9{vSd=qlABxv6_FIoypUT4wG1=?QGwt4nGLCZzUO?ufBs(Q<%!w*
z+0S*Y^{i(-YrPk0%cvT!qwjK?Lk
z=db>mpT+!1T1)N{dAdv>&lh!tTgfVhXGb)CmUA#`$=Ah-+48*`3#^Qja7z0ZkGH=w
z&G$zpnsChOKC<$d-)w$68#=i9wfpR>Uc*=Hew54<*0-T}y5ld{HL}LnlKF7~bsT8J
zGsx@+74iZPm8gUyZ?VtE(f6mB6&d#$T>Qt
zvRKiv8vVcK?EVs5pZ^c6`K#T2&$8?O5i*VcpYDmhekt>1mD%44Tx5mD`Uu&nvHv4V
z=GMVXSi9O}71xW2+)OEQ#1nhuk~w6jXjuUHbn|B7z_S-#4?vc~3&>4ApN4Kic5Mfw
z3HV_oIn|o>aMYoq+@*-_`te|f_(NNI2{PtBZrd<_nGjiz*?W7P3NzS2aw69w8#iRm
z*Nt3JLSY7ph`-70wUO+exuR4j_eZiW?fIoA#re!Z3rBi4W*;JuJD#{Jl?V%$N_==i
zG%$VAv!&z6GooYR%L*|m|G@Xf8@QS2o3TsyCx9}Q)pPz50O=I`#b502zYC;k(d1bN
z&zx;{)V$L3vNm{`TX)0F#N~m0s0YU;(bw{hi|JE1jU|v0xNyg$BSivFbt-1&)(fL%
zrVKaCDzfp*k!cIsmd>U)(PC6L~&YodId))oZunc*E+&B4QL(tLo3K0y}aZ3HAIr6ep}A*HN`{h4(O54
z@SNViQY241W~xzX^sTcqv*n*q*joZ5xtyPz%kgcAa{olKi*tHAJlqfBlzh;UX5GXc
zh=LsNw_Bf`n&KZC)05T6p3k!P*r>V;F;#V;7&%;>SM!K1{dTbekwulaAVaE(3H@Cy
z4UIVvb+VMSoYQLB)xi3CIjTWj
zme5Z&PbK+7&rO|>J+bj%mUodfx>=QtMhUgm*?pP1TEVBbjl>RSVu!Wnd|iY6(Z&uV
zv)KOR7fCxgVj~c0>_obBNzw)TJfsUo`+Os0U5SN6d_I4Gl$+?*;|^Nd*Y$r$`WC`j
zI8n)N@ptc?VG6Qy5*mvn{OZ&p+8OnuoahJd755Hw=%6GyWR+Oe_Ae-jgQCY1u39q|
z^B>T8R4S6>jZ`==0|jb3wHdv6E}aX50THUIbGUGLJ
zx~pNd=&$M`7#@dyyAqzOi=)@K$-~sNz=@~ZZe0=>qkAuY?5q%;g_(#D7v$eu
zQF@bec8AeI^VLK2bVm}API0Rj9*}0MAx4_5p8xA?E&6D1whme_&-u^aBQlxH1R{3V
zjO!tDVc`PYG8ueh*~z6O=ADpwT&#pXaKuJx|jmc|=$2_3vFkW^mu3lthw`Th|jtA1}i0p&;4+
zdJ_qPL~mC4L9(V&FE8G>-^(Yuo;q*gVAJfyz8KhZoBZ8=$5BA&uD}T?ux`N8vy0e?
zggWq4PK0IP{XSSe+|QX>SOT-(TM^sfzX#ftN_7O0mSa@zm@()gr$QT*O(aiqh^xKh
ziATkdDbNYBLpE89Z_XXyE^I?LZ{UT!y-Y{1-pJZg7
z@ESpL@vkB_sWE@%6BQJCmHMLJuHf%WL*^FEey|+wL;LTK%XUy2*We6TcKmL1EsJ{Z
zk8akL!O``9b$@i$#(y`uuoM61(VY+<9Np&~|L>!Vj&P5zWznzyZgizLXy1tRkYhzc
zxOt*wK<;exv_i8Gl=ZfVH14K8LaXO#0=$y(6cj}Uant!EV*vk
zk+-V%W`x@&WJZ`B*xl@wl@=4HK(;0Z)Q?zFobE$$6Z&-SQ(Rb>4i-^I0{u
zCS{=}?p}Xt4DaFTi5*0F$FDKdzVMFWWy>#?Wx^$)ecjM)?6>-MaA}f09%2-e-W&{}oU^hSU6i@0IbYy`H+9
z&t%Lro%LP0{dBkCeTQ?%yK>$0_$M?2E4`C?9|#U5xs1XTb*q0#amu{&rKFFhCehI#|1n#JrvsDm*|_b7td{+J7s>+{E!737RX+@Iel?lW89P(MKg$fSIqnBR?0lF
z_FmVHVzTdRgL^14CnDo@&+d7vpZxu1Dd`KJ~_U@HbAjdE7mPtE#SX~D8F=-!P4=t=s9=S>DS4EvOY&K|`Smf?wX{}EyrS;uU
zX@_-ES`AQ4GV-cTi30WNs_%2Oex0y%YW*0z!M|bn=Zk+n3`(^&T`hG$U%(whb=K5|
zshhcToVt8=c|cWC)sBp-P4AYH@8*~OxJm;b6|G+@>Oc$l)?Ekc+L3X(aX#>`h%5{_
zB}_Yr{6&1)2*%+c8szT3lA9sZCmgkz+ctgTv60orBa`YP>;Fb2QJz-pTfEE|ZZ5RM
z0iA2qvyf;)$lMKci5zoma?9%FKceoCQ?U(mjwRGBI5N?uMD~-J^#oljxgsJXJhLbR
zJYpm~GI8#I;E^>FkI-?j=6UiSDj7IK-80Od)MJRXxGX90z47g9KKwG)QV5i;-+o_>
zwS=$r&UdeS_N`$Om+ww9{Y%n{htC9tPTaVdLEdRKKEye{0OO5tPGcC$BbJ+YeNFLs
z&(M7Lzo?XX5=WGm^0IeT&b6Pqd8kT8cxa^qI5aY6WR*-O_`7*%rJIL(iV0m3s!T0*
z^M-4HH!8yJ^3fg&-c$X*Im6;fI0KQ_u{7B)$R2PrW^rs|?3C$6(+4vyi0hu|0atK+
zUE6^_MY!TFMP@{_dfwB3D{9>>GjXKtll$GXk#`H|5)W{}hix+GkUoS5CeKtUdSB`d
zG+=HFF{k%GSWaBqb`Rx(ADu}`j6#V~F}3?q(kQLK>TL!iS%KevpCq+}uYC_10_8K=
z{S|rg-u~;(0lvv4JNS~BR|ok>`aR>SGdu@z^;4k>%k2|LT*!Zjt7oLR`qZh2uvg-q
zfHH7=s!QEFM|Yu7b|A-jvr#tc6Aj^h^%eEAd-DQwr)Y+JkhcfX@TriSB;Nj^So@!U
zk-1~-XCv0W(nB^7YpJt#z6hZwF5%=it$SVpm_TM7ugLccF
z9YXn#NcuxlY;4M7<+I9-&paGWPc`?UOz`$8DUakE9GU~%NJzjvkpz6OUd_#
z@UDE8Z}Eyl53T|;amAo?bFTvP%zk%tJh?fFEra~Fb}CGX)s)|Yc~c-ed$l9Fs0n6G
z4{%d%0cWZ%X#qc{TNb3(SiAcJ%09{o>rc`PY*HDyU6KLCMY`81B6rwcZ=CO)+gj`w
z8#E=annx}$f@s8BH_3v|Wpi43G?R2jqf{vD%FzmeE7H$9=X1udED5(y_v`8PXV@Uz
ze9tH*cTo}Mtoh37?d9;eQ1IqXs{NIr`;(HiV->QbvectNNpy6OyC39ch~U5kOw)$o
zR;!JLU5X&Yq{JUDes4uWoin3aMkL|GIhv9y_zX{F)YQFM6Ef6OCuSDfCYcj#b}v@J
z-MH!c3uHn@*Ldf9fc&SVgzL(*Cc(9_=}-PAW00
z%S17(Hx|}A*k4Y~(+BC#X6V>3LuB5(GHvkahd6$a-xGw!SR!AgF*I!?BXF9{2Itu*
zIYxrk$!NYWeszU*bm~ZL_zQvBv9AVdgLedKLw!eTL)MSf29J6~8}U@2cDw=4Rs^D4
zAf5+mBlh`Ij}Y_%U=?H%)Pe*55wSp{hIeSlP9;15;6u72Tb`>L}^&`Q)s0~o3n(6+GN-%gKgFx(yZ$85QEsCHI8xA!90tqev{p%>@^vKsN}2{
z_Tw$}?hoPzUe~^N|1F{o@=lW+iubwuHOb0ghdXX}_qW>cTds0W8*$6!9VaI%lGqZU
zS*27UYAZ;^@!mgAfWNHg&&wE&r+=P}jFJ@YyH)}9XcZ`D{4E!v13VBvOZluc?M4)v
zHI~w>RC;JbZ@IJ)moEoiLd=dQP;@Rq?eT!O-Uj$OE0{l-!YWrX${ymgDOmP))`yNuHh=x&I1;0Brtm5h=i$-a_
z+9Y7sTiR{Ch!YV#JI9M77`-XX+(x29JgG|?djs9S+DR|-j+(-vT)M0~q=d_!FkUbA
zcj?!=V;SiUM3a@O{eCtnL+Mb+s(y2)v
zfnLIAJ6VZwiZfbVZn{WkLfmv=BXpr1U+HR}{h=riHNzJ108KJ1{8c5IByNS(zc+G{QpEmtGipbF(dhG23(*GRkTU1
zm;N9hi}m|`4-{;GDU|f!JhiZxj71ff;vSPkYi+rN)^-fg+6&*15{??++gQ2n5-geD8ZQNd@Csn6^NQVWrh-f=(fb6%~b#Eq&iNm+w2Ig36(IHh+!;S$Y1fPuxZ
zi^Tx-pWHkG{#ftn<{g=G0qz#RaPtPdZ^F~zX{{u5A#c9V8_l5-ZOT>3-+jf`B;U^6dL6s+(dY(0=z`tkuvQKrKfrm$y->?
zhjgwaWx-pK+F%bzkW&xzt`xo}QK$#+{g}57faAnR)vuBH@bwVWS@M@F)u=D~t
zAXtd+b^VP{t@u()^6%#$P{fLK@QUlzTTe-bm;4btkC
zR^UdGWnL%Jz;yP%5#8jLd_C9H(&}RFU@L}J>N&W&FVWfvb1RW{?v;!M#au@JzT(yK
zJQ*w5SBTs*LGF=w{$8?r>I0B_=Lh5-iRdSC&wS-Uxo5tDTbj#F77c5@Le}aMk$VlR
z54z*|(}C5Q#6QNouMNho&i%I5;|ZNz##l&Ew$tmI_LtwOZIkVzKArCzl&iYp6*
zw9SawA8T%-arbr_`yBF-qKEDn{SHya8sXi#kyrKn%`Hn^d61=1E?+f~rj@Nu&wE%`
zg^NVui~s1xUQMF#`9&@7h`Fi`vU0g1DNlNq3aN@On87dHE4i%uAA+|jJgPN0Yu8sA
zYY*bGUy;$X_%0Wv$;s=rtKOCgOYQ0G8I9U})%p4eV09{7i__r|q>xUp)t4PJp{J~^
z@3s&1RzUha9Pj>$_&_`@+HV`j@d@3aE=8O3HoSnSPbkJ6Pc;xto76Hyilzk}Z&4wd
z*270t!!J?4$PZ1wfnT&X)USz-Wta2=!E5?R!DLyN)8S=lwZ?%Nc7k(65Bwu7@@
z@dze$pawl8TqNq)ef^Mo*ASTTd`_nvqY1tRDRCM5w;w17(qQ(9ZqpMAm;4Fv0mepl
z5^2`oYLQkU`50M|hxWE1Z0O+L7JrD0*yFI^U7tbtTIZ2&(5Y`@e@@Oy{hB;MM!47P
zgL()w6#1t(e|swb#4FTiXM)ln&nQgiWz3UA#~hTi+Tc$SKgGY=tS}^NLq2wCM_+a!
zws2`v1c|*UPfKve6ly~u?Hc;waa`$=gC0$gR?uf;%y@17zbNg79}piKMm4$P1);U%
zTj*+G8N4(YBRH%h=K$gbX=Wmy^2}56F=`-(eu>&1x0}XPx_CMBBe3i+IEp})ErZM*;#CnHoLk_vMdyPB@)O?Oo)#%iR_55n}8@+*i
zsw#v?96r9`9a5jEN=Y^5nt%tf!^Yd0;E`GJpdPb}-^9XpIiLkX5)RD%GM-VxCQe2$
z^k%pP^B>^u{eUFY1|K7FZogg&9h8DvJLF%mK-)c~s7AM>gRWgdH1`gEt@2wU6(^*V
z-EVTfQ^^`8S@>HCD)cl*<<`R>IUqyOQ+!3fmcFd2aLdjA9odL%&RPmMlaHwHOtQfK
zh!en$D>GNw%&|%2>
z>XfIcuS?}X6~i3T+7NF_vy_Fc2ND}Na{N#w<5VdP`0wXhN=flbHDwn9DgJW&6Od~z
z&^)Ld@fctKyBcuY^3}h4$ERa12Jp;q5B5p#Lf-6ENVvfC{eM#gv8?Gq#IlCvXMRI0
z+cd5prMGw%;4W=9xV(l}45d;Y7gSjBHi0F&%%}r8ApF|lOTo7?toBs(u|D*t7QzKv)X%six|
zU3I&^y`}V5A`#(F_NC!oG}
z9;J@&D^J#fe-Vdv#q~Ccf@xPmcH4tKX8o`H9-^>`BC}Vt^bw5Bt4**7ExOkC3BB9e#j2%^3a&#WCysOgCYeK}2{%|w^$ESXu-`v+%tR;8$7&ftr-!I{N6cer;j#E?z?l1N2(iI$6=
zOatMTr<|s7QLaJFYUe3Mp;6)X@eXz)$a(yO7NGHnx`LTJstunDjSJ5r6qmIjc&;YT
zpSVKilSn;2>Dd>_>eF!=rME(gM_Qa-pFU|D$s)nqm`QwUm5fM>N>C?uJm^jBvp-Ll
zW5o#VLUKHGYU3&PPvp#$8ck$?IPKZHx-4X1gy-UcJZ%VxV46%{+W2UZHUj-3eMO&0
zzY*WjF)N4kh)6baj+1mO*l}8(|C#hwI^jv0h+q^`zh6sw{9ydcLz-EZ^bIqBXy)#X
z)s`s^(oib%XWmvdc>dIXco!r3{YWMap8jSO3(>tLld@ow=UylR?+op%l#ltnwtvDT
zAJFze5v}~AOhh(!U?V@Gr)*$NW!+`Hf#8TzlW{!G#1=}W#+~U|=~t-xSLydkj|oBr
z=9_32m&sbvAw&89)2t5oz58Wp=v^V}WSG)f4HWN-mggVg<_LNGOTubEE;JN-h{MVG@2j_Lg
z7euzpAKE!!;~+bSpBimG-}BVBhzV`i~Dp^TVEFx;kE?
zCNu%N*zd}x{vwrUSjj3zz7w}yg@+tubIZk(?y=dJVBRJW%K(w@`bBQp`B2}}m5<5Y
z7J=jNhX1$wlF73ow}|9_fPQ;P(>0dtgDocL!~Wg<{Tg=Z2BJ4Y-n2>jF`v~o5_X!y
za_|%Jk&qX7Qd0C(`vpGR6MBL9s?N&NBw{Khz`cVIs%W{GL)KFC_2|Qzf0Js2?AiA3
z`XqX)vo37}?VbI1B_I_JyJukyGXh#d>wuPk^RD|$tY2MA&bcO>dLNRuDt6eQv_&s+
z-ISlB+(`NiuSR!tRf@m6&+eKquPuwr5`8FKh^*>(!fqM|Dj{dpvPJEIB+BUrw@hq#
z{s&@hQ2nIJ2&~pL-!hoX&y*t;tk{hIFFo+@#z97zbIb%uy%!#3IsNi6IB#I5l57TO
zzpVd?cJ#+C#AV$h{lHk=Cv=@hD>+%VSy-Zhc_4cEbE_%gK6Tn%O6WC&I?q#AoinqZ
zIndtn#QDKB+qa*T#r)B3t-)RP5bS*3?(&0L1nRs?`VH!QKvx=|_&nuJ%wQVB?RUZ_
zhvFY;#ztc`0te#T|`KRF5bSmWIqU83#
zKx(F?U4L;;p?OTL&T|ZO=~xm~zwTla4cQz;E6!-cpO)X$FOF)Ani5kK6B0{273>V9
z2jzcUX!SlW=SC~+K=AT7Gxy9#Lt7(FMn8pyJ^ehs&uPXlh2o>N&5<|t0c8)@krMxA
zG3~3Y4>>0F40klPPM{yc_rM%j9<;E$h9Ko5vV-QQv((>b+mcV`^sMY1@or89TWqE9{IbF$Hi5HxEpx?Awq~m90iq=%-s1}g$AF1xrU>dMU#+h`WW^)L>{WBxVYA9f{`}PBuIpbysFd3eNQtt
zE^d8hUd>#6(7fTt5~0_<
zx+jOM19ouAuS`8po1aImClQIT_jgh_m+BW;w7BV_qwmugp)mO#h8C5oJ~O-(S=wOo
z&eZ0Qp`GT@hE&d1JQovG$s5;ESBt~*#244yOPU=QSAdKQGlevVElV`!_qp>W#N&oZ
zaZ^v)AEZ4}_nC#FzNO>6;<3{nEq0e1=%?Q_LRp$-%fPIAPKM
zlc$}{Ap*%8!Mr-=(5Ujkul(O7bP)YI;fM7n$SkjKyZ`mhfiD90hgYu{
zPu@<5zW&|yVh00cQ=#g%znh9$*DwWyJ{-@upFXbIOMX4bd2=cgDi)OK4gR%tWl`!fi>F#4d)F#C{6OCHHlNg2&=tIR1f>HB2SbzV7k8
zrqMRa|6ka}y#7$@D1@y$W7#o({8!@{e$ufAziqXr%9m<`Uz6jGL#`biCD(>NE!Q90
z#h#Pe*oig}xu@NUe;?!DC-_&0f1jcafwXaPw|sOhywPQpHXpU@L@ghqmV&3{mB(t?
zq{{zWFUd&S*RB2t)bYQ1u{cWLwBvhZgA#8;tZX`2ErV|;ynWXw?PkQbnJZ*dzY$VP(gSTWSik
z$qC02DLALH(01}LeElMN=laH)!eS^n<`I62%|MmS*C@=02XiRoSm$2N|4H;YrdcYnWRmYE(v#Mv0eXKra}Z>2%}|Nb;}Cjv0_$=>qqyS3O$j_!1LaH8AH}|jv(!3
z#2ayDz2xQdaFR$Rw>){?^`IslA;-g1g1E`z@{;-7o)x7bOn&
zx_966Me=)@BP@2`f&0X0F2w8k7wVN7c{HsF2!(%l1l4OBxp|A@>)Or0S)^p^S?Agk
zy)&Vh;_tBXE$N%5t_PBq&cB(C&(ZF^(kI_t(@)-tm)U-uvfALOTrpzgCcld8I$!1F
z{JFIwEvzZ$v8$tLS<)}UI^EBRj9n)xg0
z>mAP_K6B62Pa2Q8D#A1NX3Z4p8k*`ZRnDoNSU2fN6;-
z&oLR+=j=aj_{Cv@zX+erhL~^zf&6$;(vwSOWRR)x!yTRUyYp^>r5+Kw?dukmA%g2M
zW(ZF!^rjkQfRJz0+aJ-oqYu#%6Kdwy77x+pZv$3=m!Fe08+!e>gY)^OE=sT>BUgP_
z--PJ(VelDHMAQ6=EIl);Af29p+m@k=3>vI~iM!QrABulj(-7OhX?WRj|7(J;H+lX~
z^DhqK^`iOvZAuq_=vQR46<^N+CdoFv%A(Cb1KD_#nkd+V5`d5Mq>pJF{0A+c>iMI!
zLGT8Porrr}8^zC9^{gDc&VTn)fYWQ0fv^3q$4z0i6td8zHBUkox~%3u3r0S(dD4XF
zvw}uJG1vcC0bXONn0zwk)aj}-?s3B-kc^p(Kh!L4D(*0GzzS!+knyJC@g!=Nw-x)@
zJ^YY89`jhmQm;nuG}{rU3r%XM_*Uo7rkVi6cLq@9!!a(rZ=E*(I7LG~b&56mH#P?<4!~Bl#@w1f?dcFvoyh|Du?zOF@@#W%99)b6)i(;?N*
zAS<0K-FHSwR;n@Pkh}_G5!ik~;k15+`w5nseA4b1L+y1~*g}VR@{_*2Qqsm^P(}X-
z@BXM$B+<}4DW~;3MX2h>6NK_YviNNW2Iw;g9t((2?UQIq^Nl~n%$WZT6U7fzQ)K>C
z9G}_d2`_-GHcy-y1w<3Srl85pFQpst|Ep+KF)U2nXv*#}no8NPQ%p4MBzHpWX48JZw5m#-veZ()I+z
zqWrZhs6YsqLNW;blO>X=wND;a-A~?$OS%v*yVS7VpJb@RJRtXia-`1c(5tN4u|FY4
zxFY~NASHP5b*os?dh~w#s_~SV$zIu}cP_n037NV5WZqxhPfvT{(1d86xmJ(ZI}7+}
zM0ln%GgD7Ecgfc}VJ=OwL=~EWHi`2jgP38aM3NeVPprnZaoZ2M$ZApzZ-r-lw%^WN?kB%G-t>+WHO%GI{i)NL
z>F<4gi9=?<>PAkZ2v%-B4839OU20pIL?y@fiH`TG#I&A1yU^qQ+GiOoa}|W!dy4U8
zI$QC5u{-85uc(&Qz
zJRg)*vT>W9iPHH!O{ZjOo<_D%g`e!}Z;GN!W2VEaRbW0FO;)Wi%g!97Y^-Ke81)p>
zzUJ|svyh(g<4wEOwA~y>Cuhzt-dI*(UGLJ4gZrVu!mmdhzedZqhrNTM-~c
z#}qr6FZJ>W4=RJvWjOT}R?}V%7}h$+Oj@_JhSpsup|pG3fKpLIi(*^l{DHM69bH`8`%(hPc5&Cuvx`EEIgo@8`HtllvYvW=yyv~YtI<|5$y?|^vzQ@muEq%qXaj<5Ack
zRkWR{1*f^=$=5vZ=6BQXT7}eaZSYm>ZecX3caH7Bnim#3LNT`%<1pF?uR<^XG4McS
zb`3+$kY~w>aL|Htz_yFqp;Xo`8K`
zEyl1jkL;g=rCy!PxJ%jkr149(pbfDR0-1qviZQW27Nwg>C~
zU|97=PN5Yz5n=^vh<=u(`crZO#Zk;o7Jqk;zkQhvK1U5yOELvvB8o65%D
z&klT%=Mqc|liD^=8|t;0NKGoH^UnF=_4xZ)%9rW6bG>*6{)X2abK~aq;&Sr$P($=_
zJh!1G73AH0nkN*WcjCy@r^*8iXATn@7r3ZeE$BU{R`MJkr1hblgx25dkyg6kS29nO
zpEOU*Eg-uEtN`Ll2qFxZ-&}EC;F8L1Tu@aC>LG&I@k*0bVue`J-5
zr8SR@qwH&=XnXEBYRU&)x%^*`47FS5(!R6!j!qv#a>@wRC-#d&X@1L4rLTvt9PhnN
zPe3cYb%JU=wZ+txM#so^%aAcvPOX^fR|e5-6bp*-up?kws^M`IrIcyQVPQFA|v(
z)}J7>PFi?e&
znNwJzuYm3~c*luD}{dXUV=xCXf$2^x;AtSUGPE0hJWUS
zno_x5+}+D@-+(=EsB@)1U9!p9J)GXYwmg;aXLb(w(ID}nvugzSk<81*K3{pcReWvU
zJ*SYS|7>`?!j?*N{N*&*;>S?`bofr=Thl0k(QF<=Rcx&IkncFfl)wJZ^a7zbV6(y3
zV?CooOOc!G2}%QL1sFt-$hwsy=#y);5oh{P_x01g8f#xale1#$KOO6Fw^Gxe^4JRh
z){8`PYR6X5gBn7Cm5JGDjx>)d7N@KF=olJ%Onb-j9;Q~3u|c)OwlP>*TD#;A+_XGe
zTDz(bfKWVDdQ-iPyb0DyZ^mqI_vtXWBZISx*|K}co*n-MmC8j5IJe@&dr~;gAqJi*
zW+CfN7weH9(puHm1M7jniS@2~#VobP+1y5v@qpqx;L%@
zeaqbcEF#HuORpkl{cdE_sHEftQLy+lQKxgB%TMK=`f>36gL`r$5R}QD{F%|V7NdJ!
zm-s!kFejDcS4PpKB`4a5XLQ5&P_;Qf7L)&yT4GS*O~kt;)a}g>q9uEnWC@#Ko0xIX
z*4{Dn(!yF29c`Z*Lu)ME{kTzC9d6dG45inXEnGXHn$Pi6jHMDPg(oL)h1M6!LyWKk
z$!u$#Bbup`YjugcskuicRqLK>p%_)bG40sV^o}yS`P8>18#O=^&<1Y-Pj|ZKXD}9T
zFkUPgqj{Yg^&~WzBSjn&lXS$+GO`;T8vk)X*!P%@xWsP>Vo`fXd(Q}!PPGTMjHBNy
z-D#YA#8B!OL3Ao*3R(O7C;f*LooY!6vde`KyI+KDJSB~DW__V;%w!Tp9V`5Wn*5AB
zOojPU(M86*oDgmkJ3Qy0Bizcr&>?GNBRB4~km%@1miAYc@4av1BRy?ow`U(mTo2)L
zq7k2m<($8;TShWH;mou>XlmS4>2Gc;H8pB#Bu=vhsHfDK5(osEKvmzMjvOfvYq2Kq
z8A`$&;ogtT!zqv^@1b+LxkM`C7u!2L7aFJ?G9*Kp!IW$&%;j%1%fgW_p6vC$u=tUD
z@y$4mR}ad~Tz=JlXgb;mrcZoxKQhM##Aur0^>!ts_re<3Bg2rXm%rU5lf%w{AL~LYo>^Gq=u{n?DoV)GALt$qWF`YI1@zUOdv4oBSm^37LzjEncvF9
z>B-p})VS9NNI7<4Ff2OA1K|VSsQ(%a&M;sej
z&(HZnX=i84d3mo)K!({{p|I$9-BQ~vo&9{CGMGf3s;HzG!6an*eu`gK6|y-V1KJ3(
zIfl3q8ai?c59mXqHbp68Zq8r4pmD*Jmx^B6kR)5USO`ga6;zG5j4ai?)am?2-23m2
zL%htd3Y~eWKC+%SW)u1?`jam*&clH8$03zgUa8TnmQdQD8SUZ23vW1
z$D-4)N>EIkvuzc89q&?yN=>`7DDmRbdm8phPuyw*|3tw?7<|zkCr!R5b*4^#x3s;Z
z|MaEk@T^c_#eWsxj@Em!=5M`pp_vaqMh4vX(BD0
z_wG@rpR#de%=nJs&1xkX#eQ9(xjnf56KS^aM)`Gqp`cS9*T)iCX(Ow>V!z8xIsH}P
zS)#A{4%Wl0y8Q3k+5eo>j<`;Jr#<-jj|Nv_*C9=Fg5H<)WWyavQ^{T+WQGdBA?;XH
zb}8EVU%)oQ>`s2Jh}+U8g?-kI8qm4(&7Y}LQ9
z|J0Ga*4#^Eg?jg6eZC3Ldi6XhSw6ir@|~$CzmewXhI2hzyFVc21*SKFwEa{*kvymS
z_?4|xkfHO3UjLwS17wH6_nZNIspz7~&01_(F7%|m7XG+Hsd@JnZN~-maPxCjj6&l-
znp#sA;ov)3WqYkD2}HxJ=@YNF^=T{#L`VEbjjSX$u-3G@3cfVxD}&wj^lqFFcKs$_
zCra{lpeFHpE6#sTws}B4mgK&AzP32r1`nFsWR;M`??$2Jv(n)!b{_ZlyImn4t?(~6
z`trp>^MT9|p{};+aPkj(GnRcnq26+$zNWG2Z298zZ#5sRFR7ejYhN?#bJM3@RAIWT
zN_ITqXhOC|2^35B&XoLwoP&qm>#hNbyKU+LN18PadmKRuTH1--TI|bvZ_BEe>x^v!JW_X_gN>X;p$&R2SkIL&gsmx&4v+5BzZG>MYGzDHOhoJlu|uZcd1+bF
z*`(No2N(Vkl7sPHcJ#SYG488wJ97F)ZdH0MaA>^P-tEPMeQE!QmodZMG6NIxRI1Uw
z>W&)|63ASRHl?%eGhjkm>8itLV+qm($;2`VJq7x--yP(O>sUc>C}<-eaEIVRTEj^{
z>%w8F^dz{D$=yk09{Hd<)L9O6KyV@5;}lp?eXY;V-T}HL9V5Qi?a6QU_R%f*l;TG+
z^B^^4u(2sc`JG{W4L1~jD@5-*kZ&yt{*gPB16qV#U<#(GKpmgKaN)PiNaiKs=sR5C
z;j>)O;cCuSQ^?udtW;!`I8^y_XtWEwTq;}xXTYQPyYT3%`{mrDm~UV?0OykA8i&3l
z7nL=yqld73L}sIpUd?^9F}|6J>-^>{w{u>#L+U+mMg|?~?SGIF@rrBY@4x>J!P7lT
z(ev!U7%>yZ1v3bOr^eH>H}cf7bUI3yai3b8s5rMS?*3%}cj}c{@F7|t?9GVGMESi0>16?Y$lGVVuQA5x#GiMldY_VbDR-j)h
zof*Xj|3{$hc^z%DJ0?+Q-MEtPSnfdAYTxGK2oly>_AE}yzyy2c#8%6+Khvbm$TE6b
z0k@Kiuw1YZ9N>4F-f!6RC)uJ2FN0eq($jtOlc(!4W*Fvdl!))d2mGoXc<<|(G#)2WgQ@m$w5o#$OWAFE%=5Aj6w+oYOh
z(c<)$Bp?n=?Vbxnwwj>Yq}majD{)dSZW)Z#i3iUxaj4^P+nf-~OzSV$i3uHEJm@lp
zBp6;BM9wU!hUW)Wa>{NEqDmSqoK6*LAUK-3Radc36gEscL&ua{Nb$4G4;4(iVkl5@
zzPvz17sMB44Cpv-Kk@4|E>t)+74q_fYtiAEPciFa_DQzTx0m0jGalpw@BnTBPqnu^
zek?6vXJVmEmk~j?WTYj
zV6jF3drZf_c%xbuh}^b660TKYe^7QM_pibc1>
zkMq8W2}Bvc7=m&j#xxJBPQ=V^Z+rhB7m@@VzM285u>InmqeaLYr+RV{SH~T6ypzah
zw~d8v^Zvm6S)1Ht9=E!0;#)qnG)liMr=4^Zs$1SpA$qRtorXIZ{y~rt>a2gI
z8a1m%QuGN^XdFB|q077beDOO{r(o197^xqn79aP#CvH}LD|*N3Q=;7S%ljkvc?a2}
zN0L~?hel9Z^ZOA@E^Pvu7~!GS-xOxNyKkaVqM7GEL-g1peeLn$0s8;fX7C1~^+^pA
zn+Uy^b0tjz2aY&9@m%C7@x@IiuSM&!kLe{^{_sE@WM^`X&a&Gup|*8j6DOM4CP!j7
zb{5u`@EPG1M2nX=R*`4i9yjl0@6DbQe<>c)f0NsGQ&UVYvy@oEPen9fWxwF(F)zCKPf3u|IAF
zIt085!w~z($^#D*|H8ts2mX+J!hwBpy6l;inZ0Po7KU0gP>RwWb^qm
zefhFzxh61-nv_RStd*+BqjU1)u|TnARlVYrY5h*CzXA8Dr#goWe?z0{`H`oU9XeI8
zVR^^r?E+T^QoGmj7YQon{O#Ug-HSqZvoG!Ugv4GY?5(VbZ@*pAwh3vVZl?D
zY~uTxSCVs~s4niSf@a4jZhu2msc&D4J{KcoiW%$$K0x(%oS;2>-`W;)5~rFBR%h*`
zU_)TEdvUJmYNfWh&o$f1$@e(3owJo9E|2CL+Ma&PbPczyp~9B4WEWii>CVK27m3x}
zw3DU7b6${Z$Hqf89PZZ$9CQ*A-&K(d+c+l=8$y}1xM%TjuC!9l4ijbBRI-U!SvAda
z8kSt#uSoXXAJ>xGl{0<5LtxD{iI=~+XICzweSy+>n$lTY4S)1svDKH=St|6N%1N7x
zawp~T?|voogZ-ujarO4~sc!TK?5NejOXyJB;ik?;q!n-9+4i
zT83R6IPeZbWR336Yv?5h*UK_wBR-UmnMI8tBP`oFr_dUC>X!}jT~nYnEHB-eD4yND
zSsbpucP)Bb48N!&;!I2is}Z7UWV52|RzyG&-;(~C@&EpGeqi8qUPw;o4rQdyx|^KN
zYkAMk@an|0I)N=YQ%7j7c1)49Yqj4D2R3bK>O`($q0W;7wV&v5EOpC`r9?)A#1q~h
zdN=%R#5vGL5RpT&Q<7w9tC_QK@qAKhnNUY|nd^KK6HrHR>|R;!Dy#!)&%M3Y@P>${
za7Y!Y%%TP*ym8#M!O{Y&%+PLXpuJZ}P0(}C^9vb@j#=KZI(27aYd>vFHMY-w;+&Y6
z-`51`L&sngb&&$J0y*@bruJ7p?<8%2`una$Ge#nHa#|q|t=EKJe`q|lla50^WmhMX
zJ-pYyPmq^XrIPV?iKXk^ANcNO>UGtm6X3GK@H{#W
z$eO8LiMk{3z0U}n%KNK^5gH!BRVNbP=U(nwG=JLhh{hUCyRuV^PvxgR%BXx>jU)t85@D{7Rw#vCN@lHI_Q@0i%+H1O*}i{TnQP=O(#>P
zhgSA2VljR-h2>Cu>P;WJbqbJGhQZRN9otUbaS$8Z8_s2>U#usAlSxM2emWeIX?cf}
z>CwYGr{%-1u%cok)}D@uY`BydiMrc=A{rIhPa;n}dPqB#c(G7S%9kPWY4OXTL1HDV
z___HvrJk}=2?nzCeD#-PKfwFLc;9jQAknKLbEg?f&SIYIO^M;wgJ&f@Yx#zRL_W6l
z8sboYmg=!al06MKZnDTKw?>DZZHi6W(FjeU*OyM!7FzkO%3<11;GfeEi4BXcg)AzxKE=qxhQhbt1QmHo#cFVCbmwgQE6;zMuqc%15Dkld
z*_lWrNMz3U`{}q>iwLsu&>UAb!|{uXY1}XkA4f&xP60o*XWFg3{UP(j>7AFaMOP;#
zTO`^^u7OT|CH%NJQoSzz%WAI67@Phl)ytMR6=u8P^9$isc^p5o({+N^B$x4wVjl}zGX#*_jgN^N6FFuAz6}_^
zEg5*rlQQ{P-P?9165Y;e4U-U;S#t7a`v*?G`u;-D=H|D|poNx;SHLY)?+|G`FC26V
zxdxm(GM~Y0A_p}7?nji;6CX)ET+}wO3w_9L;)kodu75@1B2S1KM=0fRx3YUUH1-oF
zAiMI93{jI?8|Tt~a5&McBTpcf|ECEr%NE5?*LnR*@8Za5)r|@5{W1A0)@E7NwPDt_bcpU%bb>v#VIo#Pz7N7QM58W3pcF+YKh
zxPV%h1NsBGxt7hVom3N9bxA;pHLt7QZ+fQz=p7ejFHcxRM)Ai|A`cd&1;k8>3P0`*
z`=*m^rH)M1!BaIQ9lUV{7Ga9)QjtKGCtL}S%S+&odt~m~4V?k_-up(FmDRBImaVQznj3CgUlSJ>iij27$N-xTktE%$$G$f8y!-Jn7?aPe
zQ^a@wFZ%UWk(bLRHf^zx>{pRzN&c&m)mO(#*{{gkR2j*Z6=B(e6Ry9zrCon|uxv`O
zRQC1@@2#*cU2x<N$=(CUT(
zt!@|)?0kW4=L>W@JYV69=e~IE`^&|N)!`Wtwh7sERnS5{hn*w$haY&d-5;8mN!Qg(
zF_+|_F-qssW~zdHZ&kT9#eW5&t9tND8*)`yZqjsHDa7E9CwG_7+s9wc9EY49Z4p1N
zx=h(?SW`h+T4h>ALALCOtU-24)+nn)HWXrg&Spn0GrN)P);2#){KgqY?_H7TwdDF6#BswZJ&aTRrG2R+wK4Z5k`}pNuGJnV&4ZFLE_^n7-vvd^R
z0oM(2-or;z5gV0?$c|A7!8TZr43z&+^eKPkNBrg&1bK-Lu?-jX#*eo_PeI&eR8`co60TMDEGlCtj#|T`>}TC
zajK-UtKw0PpV9p0O3Q(4VaN_8pDmNU9bj{pQ9W2@Ve@h^m8GQd|FdqFZp`%&#saQ!
z)+rDBkP%ctHvC#VcysAoo%$~ZK5EUPv&gHrkk;;elOAa0rDmGXVjq)g7^7pZ7jOj@
zO&{*pltU;T=_~ijTnL%dTy`;8F|vxtMsc}-6SuOVro>tzJrv>wHXMk7
z!{nf}kZ2$V4g+G~Fdzo{%EMEAff(ou#6Vvl2KoRo(8o01-~+@!pT33hplw*I)}7dr
zWQY_Z8{1zYv7K{-k_?*lxh;r{cN}*$
zQ{33rX!5^GiDhgf8FP`5jGl~}jQRgG-oAy)EOi1IHJOlA`34)R2<@U6Fa1P
zTx3ko6cc_DM}B;i@W<(WX%+5u_8v0Vz0UJri7&7ixDiG%eyO)(2y}(DGru*&ZI7it
zu`{964&@|^;Sqk(U*zSihG4ejH-U~UpreBoV#BpQaPWAEidNQDJ&n9G7e*KjkAN0u
z7FY=Ni_w4SCDcd0O2$`vLF3}w;;KB`=l%-K?nPt%O)5_-(x>BMlrkkf(o%N)sK-`(`>px+gJV%Wl#Js3SJv>-G2jV
z_(CN0QO?;uGTTi;@5mK>_HLlV%`+L1t@3-X0OcSWH_@|8dw4nXH=S3!;pJ*N?hWSzcX=TuXsRze
zsamVN;UUSCcY%gSFel2CywLRup_Iub(vvmh$;)`6c;Aaqetd{hOHnaWecuM=&kFv-kHscG@YRLTDJ>oxL
zr;)Yc^VoUrS>M7g*7T`^d3wmaot$<}7v+sQN&RbJyNIk7lN6s24aoj;9JK-{eHg>f
zK~&6_gs;diaT{BJImEi$knJCMA4g?>Np9N6d-8n!x9;y4Sc2A0TtZ~<7%n0k_s_3(
zf9!rU9C=C71zPDr@Th*1(tqvlW4>gJyrudTmCs!IuSKg(1N0w}oSK}m>
zI2|W|dRq4rS>>6CY_4-lh^y|kOf=MIoiBk&z*u1Mb?SybZ4i@M{#72$f7iOu;RO!K
z{6l8>%rD6+NMV+$=AsXqFbjFkEb4#$ix2EmE;8@0ypgn#>f@Qe^d+zK%
z@fP2vk;7Z3?--Wc0j)0D>elS3lv6u@xf)tEAG1y2|7TfOEMvAtqd&V{NPz!K@L%0J
zom%#F8ESifDy#B2==VughScw&UxX!VVLkmwzSM8Fua7D{_`<0+#xSpZs<**Tk68Aq3E-|mb%S{U*1=xd=^^Oe5q*;dwKp;Jl%`*nt#`JRo3vI@pjJY
z%Wv{@oPYTpynz%Z+#cB98YwaSC+uIYrhe<|;fGVyn8dzpdD1t+fO2B#;M?CaN8fUK
z__p11u`>9HU)8YJ=1-nOJskC*v2T7mx91zlX_ist$t$j5w!h$j1F;^|qB@k?t)S>R
zJ8rU!dC*Ady90gbm&g^7s;3TZxrQ&Q$XHK4AocnBR9oW`iu(?uz^==i
zk^7z06v66BxN+X{VU%xG&DYKU`)2A*F}L~cR7BwN1M_r4bm)b2!GC{~+BtvG5&(9UgYIT~*+zInA!jymQuWUv_Ho@~b!l
z5PWL>l|L@PULo594L{S!rz;g|(&cW_*X|
zBKE-^8gf?2Igl(%g-GcaKd^)uuc$eX8h{){D*Uo^K`XY@RK>8ZO|?tHBZmN8ZE{yU!(0y!aV9!r;Md{UP@lM^Y~88r;d@2KD$LvfG;*x3JHC7
z&v;!eM@xf}jmGqnw^m%D6{3vz0ejJ+={J1PRNotVF@ot1P#@sGFBCiFoty8_KiB*t
z{n9g0jQZud>CbQec5d=3Lf*qMLf(h}6n#}Fdb6kY2rbOJM{lRp3SQphF>3cQv%YN1
zIQH<7-N*JGLx1{-A7bzwwXg3$n}>#(d9RnebyoV#Xg>oLV-Vu|iL_xX3;!Rl$ykke
z+do*9k@uM8^uzwg=H9z|MGa#1XpgIqb_CLt4-fJl@-elCkYb^pTVcpx@2FEHIJit
zG96z$9bF~bfCVwnzCkr!*k0%bu0OuT_oWv80bZ+
z$xz%E=^XV?dgpfM@%qK;aP*`-7N>WP?1(oVTcr1xd*Mjun{rwD;gll-b`99ye=mKF
z@htXIafa+JBW{u>qX+l(S+$4H$K}fo7*l3obeVw>BX+hiy39aWnKLV+7)}Lk?(lW-
zr&qH-=P$X_{ihXuFYTPQ-ghXSBwh9H%AAe|>Bc_I;g({}e#fjg4uoaCvo91kPFftu
z%EVoK%ogKJwMilS7atIFd4B5iVmJ0sT8poTWCrfirG0aeX7oRQj92sU*2HPN`2P9!
z0af@y=%e*ze|cf)MPJ?XI~PCp_)lS(p@k3gaLLDxS)bztOy5Y%NR(6h*Z!b$h$Y?0
zcUY#FU%s<7aO^`L@|QWVkAal~_TqkWr_~3@nzHpORvz$%N6FUbGgjAnHF*g!Z<~g%
zK(nN2#x(ePpT3$g>;TQr=_Pu)SC4iMue#vW(HB_fYESF?mvJiVWU!^^5_Y*R2X{98
zgBb@K-AhfojKk*G7~Qly)RA7KwwQi5;dGG6kgWsT+j=v;Z
z{SpP%P41$Z{jj;;@V7u{w~b!&_+k63HoL{^Gq>aQnUVDR%-jO(g5bLW6^Hw67wai)
z;!!5Mq(;-8eB0WH@l|-UrfFa5D$9GX_Sn^_%DnsR=4XB}r?0{HwIk9ogX%=3n$nI^
zOr#y9qWIp(#9Er$n;)&gH%EHEyK->XcSA3AW3##hu&y7_>nDAivC4-A>jsD3(X4hD
z`T|RUzkc5wOWCcuV{@>=G{PM*tJ|ZjW)+=|j;q2s^e#164Z)W};g|SNwe!C+Yl9Cn
zY)EC#`pno)uNs^^S9jRb))+~3fkL7XNBlGNQX6LdZdTN6=9fgFF1_QYI`o(b8Mm1A
z{(+&Fd@&yNZC8Nx-Blf6%k239-m}vMV#g9QqvdTGUTy#UqAo7z)uh)}E&aT0(!>?R
z@P_3N?9I9T=b)S?S!Q82N#V0zPuI+YmP%meM6A;<{7|ftUD}FV@}pdetJezkb1NVjiZ#ID=tPn?5q4Q1JnhNng(?VGzLa7FTuD>`>sri-Y>U8P$dWy4l)
z@$Z8boc=hq>hCAwLb6Y_^#9F(H%3G%1Z~F~1Zg^aHQMr+zn_H}1CBj>;4#aueRbO&
z^Gk}z%+9o2TF(sKXR|)5EO$)xx9s~Ogwit)={a)+%I+AqPh7KGlZ|PXz-D?1_jbIO
z*FBj|)pYLCLx&aYKXqxMJgR5i)o&%}hf=BJxv;tJ$w?p0LQPc5=8Vzj`MTUJir$|N-5!x?
z`F_2Ae5S>EnaatpR8HtN;aI8vmN^&o`W5(=VYd5^IRAdhKfH?hd)X@8zPZDA+P=6m
zA~igTz92koMZ~V~+Vgcn*MW=sT_*nGclOP@eg5#5^G>xlejS)ewil}?ma!R~-9KVA*f
z{3_Lywv*NzpL1f}v3*Am969_6mCfkcZ4WMexVO*h9jkH6>G=B>vkJ10WT)Tt+FiHY
z?N6(BkAH*PQkK0&Qw;73oVZ{~Hkw|}NG!&aBWSJnubi$uR288SfOn
zmUVgI)G2SSxFwrT?9un9F!xJZU2C+`3l120R$3{Q5CXmDLVB}L+Iu~tXSaGcz^DH*zod{_al6HckO})dBVxzl
z)ET46P9dQkJ-6+P&M&Nu>hW;f_s!`w4=*(#EOE#2sn4#JY@acD#`a{q-9z^=co^So
zHIcs2vmf6>cbe!nanQR}=@!FhK3B(B{65o1SCN1H3ZbXC!O3&rV5d2qQeRG@-AAI@
z&uu$MF(I9nq#DyGMxqbbah&KgMwf5Dnqm3JR=kn@Ue9ECOFDXX&1~brP^@nDSP?O3
z{<{cw-e*40Vb*6povJ!3zHDZ_(1lbH0>%35xd--(IJeqyU5vL1?jWv%e;TF0Juu=0
zBasR#&~wdNyLPAL^m-HSn)mE6d;Xr#HX<#IloooP7QUb1`%R6d#I|h>Q=wyzxmQND`HIHb=oC*>C;>AhF?$9?!|k&
zrH_|X$k?`(ms0FAX-nxpAmMXO$q{Lm{~~U|n+!b78sy-7o`bXhS`Jcq8nC&kJhV2*
zLyFC4KI))b;HCq^cGGv{#Y=hT`3N&?$kHhfv#?!DThqCXH$I5S-0*>a!TAOB{vEx3
z_x$egr0mQszPP{m~(pT3C$-j0}
zZ~`!dg&x7pYtyB=(8(7cTNRyr4Pa~Zcci9K7}^=<1(cUn~GT^)9W%Ub1vfi*pb?}71+1;
zjY%H7aPh(|pZ(7LKa}>-R*H`?gM9Sfnw;_ZR>qExxtjMq%*m&&<|%mw*3_?sS?gl+
z*J-T5z?+A*Q*P;L?l-WKv3?5-Y|kVg;^?%db;86^2?-EEvgVHrRrZ3GYQgm@?_PmqVwUi!j~GVZIc4g~l%AuK_;Quj4zI!0ls
zl6P?m*;Jl&oT6i@9L64z6qV;{-9%1d8lEANg5@Bob2O(=3ge+HXyMNSSTnrJ9>kiH
zV$h>0xBsU7|2*xf)Y$yP!jK7+)*Ti6C8I-i%)fFaFUN4NVVuFhY{0i0wi(74jLZf6
z9mCs(*9<0B0sJe&3Bxgi51S4AbHh=?C%_j0|JZQYZ~*vf;2#?H8}$$P>y)ilA>mW2R+(zFWiKelBNz*n2zFu8$80)OAM*HmlrV==%#
zHXSzY1D*iXgZ@Pz
z|F^rZY-4l}JLTi1XgUU5%`1B8O5T;N|JqPH>iy9uBze@J!Gmv*TK~!&qgVKTcY9r3
z?Ld+zenn`vJq~`xnk9-Ri8rx
zmSlMS>w%_22M7Ihb;tk_&L2d_@7(s)YhKEy^uZN+RR(6
zWan%wY0%kWX}3o{uy3ICi}#n_KIg-My5yTTOmKZPaOf=yM~oi*>A<>;_Ag#5`C_0U
zj((@4KffgSKk2{cmw{Ie{f`s;T{kZ5WUm3+g!~n^-Sz7qJ3Ev<&y#5o;@!_y9hf^_
z*>-5{HfM3)f&u66JN#bqJ8un$I??sTiDOy}T>8$o*0vo50|)SUzbC`_<3SmZYf|1r
zLhnU1EXMETcE)Ov&0i%y-rKzlaA5CmUc{^0CkG1qK`AGzpC}7wA4KBOuWjow-#z`J
zVJGC&K3G@x;DeNpByn)+kTin+T`m4y%fvR>D7V`Mnka{@|r`@8sa?9?Ej*jM$x80#8iu27IJ
z`Q@&u{kxWR?Fx-zV{u5t#vpCUGlCL;&ow+57)#(Hm
zq-LfK$xgpDCOV?5PdxX$|b@s@;)a
z#w!X6HbtMId~wWTFDc1I*`OROD|a~TPM3l#HP0OJQfhtu9z?~WY%WD#ar%>7ARfs$kI*RQ?E3%iP{e~Z8-N0>V@*ssO
znzgK~o}UHh-&pDK6^aB?FI8e-R;>
zF49Kv6)3gfDp97hYE|2Ok9}V|pTtU-YM5&h5}vBT$*wh<8`w`vd!B^hH~A#0`CDkW
z<)cmKWfeW9-5KQ>PI$_ImWP_eDAlvfH)Kziran@UW5|~4Xi=b#q>)vLHNQAlcF>?9
zJFeqJ)^RyBF5qPvkjlfz2EIqSO3`T*Ccw$un@7VJV#Z7a8(t;3#^=ju_9|uzC{d02)DTka%lX;Wx`%q
z?6q>;a#8ooWjGWj>{h48u9UgtK|!H%*O12h8gw`R^1qPDtFY)=6saK(OH0?P>K%Yz?_cmqmDQ%Iq3j0qCS^Cu
zCuOG$NxLrM^<&KInKlldxHW7JwF-D!1FwJC?<(~ohq$ZFt(t18otj^fJ7S#QpI7Qe
z{y>HpyHm~N<$zZ%QD+mG2+w6#tls*p*5(Fof2j^9R%m{jx?G~%M!m)Wl8)ck+NN)HYTQfPyiPK&jQ*DlyXdvqLkQP
z=3eoNmN_2GND3yzU@(pZz*GXgY$4`!G)LtG1Wr)Q-9#GoX9^_<{MxM46;p4IG`DoM
zkUZ+KX{2tM!iAyB7Grry<7GooxPO=GpWM+#sZJ!D1fyotOc63&-mvm8A1$!tSnQ<*
z#f9p~K>CCm4G~-wWyP{N!k|RS7=dw?TY7NaHT2)ndh3
zgh+5#kyXK*rrb)YJ&sQZrre{T?-!#Kv{9IMcC{$TqkPP5`Eb@V!jod0z1rDm_u;S0&O+S
zA(#lzvS22{%uIP=l`grUU}kb$+`Dkor^Lk#;`F$%MW`aj{n+W%>PxBnXdwf^g{17735$^Qla&5(k1B$&xC_rp}eRKYw7vk+z(
z%qp0tVV;AjhIs`hlQFi<&D_XVcH}MQMv>=mG+@fp%v~;_6EI>6a~A-bpJ(oL35Nmh
zdY`#V0rvuy07gLGP{0Xmm^%aT_*&*J1l$jIBocc9_B_C2fV4ms@COISASSCxh=Uz+qfSLNgKRp}1%v&{~Sl
z4NZ0_CWbk7XHJ3LhUpjDnJ6yP<*)$n)%1U2V^2NYwXDBFqbLk%__~S;V+o-KSB`g-
zvIm199Q?^(#e)wr?c4V8=8CN7UcmAig{=2%D|kMe+weJE4M1miM&zw3XXcd4sFEjf*59xVbj6|T1IAmw=R`zu1U<&Vc33x6nhO(uD|Cf*iH
zZVt_vvA)=!XER?}jmpipU=wQ5!P2VBsMN33wbW7fd9VbeeS`|-%}IGmX8on
z^s7WUIgoDyjg3#CAFQxr*emQ)m$
zG)`}vKQFIQy5qiltdCtUAGv!yzsp%RB?n{uM)>n{8{vokE_)d{U9W#dUU@+ya$NQ4
zK>;G~6$QiF!dwhQEiR`mr)UaEw22Hu8s5MSEp@KV^ao)OJs%LmxcjMyBUv(f%diC>n=o_yg--uE!)
zVE%w%p!vasz=Xr_btxJadB#cB3YRk%yLhGjyLPr!V3Z`sPsI%h)VvZ47QLxapw(MZ
z_9-tNHXABlPJZ#^I3-b*{QC6xCg{DJp!aElp3npxoxB<_Qn7y6vF4`TudGxVGlvH9#|tNabT+<*J&vd
z16T|kT}9YTqh^Z_WfRqQ#!-?}JSiu4a$zJ&XKH#{&Ycj&kzIaY7@yaZW0EP5JStC>VGlZGxA(jl?$cpyVNZdz&ht&02tg1YbF#
zwuS{9Hm3S5dY&2oNRFTR*gw
zOIvZk$Lpfjy@5wf#nK4$Ryc~AsAD$};;E8R+R$O~IFJ}ROMx2XZJV?bwH}Fis=9TI
z;X5`hY{ezTYQrG+l(9Ljb$}<0d^PPFw5M7QPuIZ$M61cyTPa`iQ%a)5uvS(jX%Te>
z<5ct#VyJ4DJ%FG&im(ofE=3RnD9YIDmHEnZk+#bDcvVw!uvR6)$Ci0L6=1KYh1V_=
zA$udbc*xhOGZKr|7`Qkqr2eAVb1Ua1JEeV4z{s&VgGc0KBo7{zGidnGtelKNyfR>w
z=6V-iJsWl5mAO$DPgCLvD=Ra36gu3-0;}g#KeT#I^@FSD#vs8HIhh#}=K4tSKqZzF7;
zEkPz@PAhn7D)82l1W`MiKPf+tWHrWT!&x>otPNS&kSw{cOfJ^aGQK{^Pc_lz3sq;V
zAflerTvCd^u^-+xT<<4~Z+`#vK$_-nJb+{)RaUE%=Io56UVHrj=}&8pILh
zu?Qda?3f+X-Z>P`E<*vZJIRBZmcVgb?)s>ME=og#1iOKV2Aq^w9x04vU_qol2W@A0
zN+cyGlkvpXsx~X?@j)VI#d!&JsmoLDyV4T2T86VLltGy}gX~Tx+JEGn)0v~XM=97~
zt4E=miOf1Vt^M!f6%^r0P+w=fg$@_LOrmwlC&#G4FTb7zkIaxSs!}IrA-;
zQ%=UxK@NG%!7_taheq6ZaK(*;hj`QU89Jl%H7F_d-15uH${I58aSY#BFSh0<(OK%8
znAo1N35ZEh09tit0YCXn5yNrvVk|!umloJ@W=iQfK$%of8XpsxXX}Ga5FYiWcuFFt
z9TG8gt_+XB{NU5WN|X+M{Ki;~Xv`;*_>;MU4fNgT3!1+26reYl@~
z<0XBhgkvS_BOwE%Tg5jqhC8y1U90;Re~ChOt%+j5?PWp1hO6Wew~CG65|k@-w1Y|a
zX-$&i!_1uG%R)GX+-P@`BqQRGqr+dpW0G=+LT);Q>F4308^e0od|)U%0}Odq@rG_$
z(v5U)=(b3@kze|0WxC-;+BfD#f=C{@HI#Xy@GAeq@HWGr8s7SK->v&@(@X2lue-46
z#dT-bo!cZR?sX^Eo!qo$-Ph~B-gIGIzx9>t_pEPTJ-T{z_37$cH#j%Ev4PcO)GVm^
zv?gL>{>F_PFKq0$sdCemb%WMFy8ff}ZL23#udn{4y7z|Z8{XXzP&2Y-Rn5toZW~KC
zzPjJ`-|s=IC|+3?DSe{M*rnOk$Hrp?BCH$K1d%*Oal_iyUAz|t{d
z&!mo6m+g2uVL`_|lU8@c-b}{@r(W;qjM&o=cZE9kTW|_I=fT4|ola=pY0spHP8(}_
zbXssKp_4NrqZ9UYIzdh+$ms+*ojL{`ZvSh~uiC#i>`eO=_RH;y7nwTz?WNETL5GzN
zUtQ?g;ib^Ob(j^O*#Z7K&|3qSm)kphuyuNer;pC<;JCcJLrS}~9q@)ghi}Ji>+t&Y
z4>~;h)X@$bYXaJi9^I-fV@g|u4ZJt-B;dCL9}Rp0@QJ|7fmZ^56!_!7-N0*rzY4q-
z_&(sD0zcXIbi#=+XT*15xK|an;M5;s5qos45KgOp3qo5Vj;%(I?%L{fLUb!}xr7-K0+f{`!53No_`Oe9QCm^hezFi9|(FmyI!983X>6Q&Yo5zMnN
zufpty`38pC5(Q=u%tV+KFneLBq7Q_rg82j{3JuRfm^v6(nYQg98EV_mlpFCkbPJLG
z8f&W@(v8}rhW<87x5nD4MQ~Hw4tTAvCj_Z_H0u{c!TK+g$qYpT7ig`28p
z!#EteLHx+=KlMlbN@MA%4KHsB#vPLjb4e$h*JW6b#SV43y&MN@Fek%VUd*X;Fw?RU
z#978dengkf(8@Ej{A{gyo|d1pwL36hMgav+31;7Qd30tM>xx*+
zwOTlYa1I>^is(){>jX%$adpRo(>)?i$MN4BzJrugHnk+rPDhi7&WE7bOb1d%b`1Us
z3$ff)Vs#bS^HtecA1Z||*jL9gyOoYF5pRJN$4+uB_wj9KN&|7Wm_x3oIA6@|Tu+Jw
zokJ%76an?DGud$=!-<;^bR>zDmDt4=Kk!m}X^|_x+(C45oCHH_v2yo|@&E@8F}3Aq
zh}2Cn@L~`~E=vVflt5~r-Oi6$qWS{@qh
ziPd=}5__mr7@T%ncgWEkbY$4GD=ouXgMzb+XADM?|eJam$hRzomiZ7K
zOb(rKA_B<`f4E5I^+;EE_4b_+!1+BLdE!>P1i|?K(%XWSPcce)A4-I0nVxt3n2_q~wH;&?ZXNjt51Xo`pj{QMdeZ&x4)b8M_J
z$yo4KmhPlPp0vhb27u2?$Coeq1Ml{qVDWglU4NT-oy17gGKaNbm<
z2z?FC*I@;YFo`$LCi%*4#K#?lykcrXdAY%nwc<&XzhVy+%eGExR-`;T$EkdQPhMT%
zd#w%lMC2tO_9m%TL2vb3DBr83_D;lCz{VpYPS}X}irtGwlLfLUT||7F;Ny;hPsG>T
zw!1vBw%Dx&G(Hr3BEI$bWUP4-NoJA31-uUv`CDM2>PvmTbd&jBpppgMRWX_RZtjQQ
zXoMc1;Eb&5&J(DfyGSyIQ>{5%Hu;0Tf`<;~h+4;2lPDf49~uD8gB2((2f3F!a7DtJ
z!zBrvuh-P$Q%{)TbS;kfU<^$_!EUW+Hc?S<{tk5T(H6cqjDXUToQl(IgK*0$w+tP!
z$DP_CqH*^uzGm)WVP)vd(4xyb9#e1=5TTV&4I~$oQ{j$)@~K&7IE?Sa-C$6uSmNkc
z0ao+L5oi9%9euT{!VG~NM;*00XpG|N6X4DraU?Luk#EHcR6eh(s-2dl$S>LRQBMh$
z6x%o~ME;Q-yNet;aHpY2a95d;GzP5%*=SPS7Llo
zFA^tsa&2Re*LA8K5QFNX=1mE?0KkJb^sp33<`9e!WuY
zJlb@A7;QQ~hDLwslo=ogbRKPb`tXs1(sG8Ur$eHshfdkvP#qx=JSe6fYP+6?yKpA;
zu-o-K+=cV-LvSdI*Yl8z2uteO2#<6Dn}|bWa)b*>^2F`>@X+##utc9leT;%cn2sYr
z(?lBixJesL+H?P!a)p)RS$qM+a588=kb3XET+5^Gq`0ONWX1<}(iU@)VOa(PPx7
z;G}mU9sa$ZD(gS|da4R|J&anSR)B{tF3v%&EIa56Fj>I%6lT>q@wkgmc?s!6#R23-
zsDh*wPBFtqxf3r^sDktIs60ZThtEUt@Muo&@=zV+7ALjIbaRa#20)p|g*h6>VDNyK
zN6>hwE`mNV2N}y$2<=CRH>vk6dRXd>WdE@82k=fB6hC
z#fds8^jT=T#k)PFcASAmFMuAR7qSF-Qm90thoTM*$FMlSkvB{O@Mr>P`6!P0-Fs0V
zqeK=@A{#nBI*`LL9Hhx9_F%Zrl#c}g1c~L9{)*a9(nTjM7Aak$%>}%dgpFH}kThh|
zYS?Hvkg2_gfdNlUKGtn8p}@_k7`l(q=v5B74boTBuVE|`jWJFRZ(ZdkGtty>k=8+_
z^KCng2clzqq-CYCQ8X!o*z-a+isqodGmNchn$R^LeXQ7r
z6EtedAx+9gZC0nOb|1ulnH8NK|d`FHi~})tRf$8*tf_&_Io@jPUvnTwD|J*wD&&
zo$~U`o^(OlH;@+7H_qHg=`7MAF-A67iG2y-QWN7i3XzFsiJ24oKrw2jNwHW>BZx5{
zRkbp_BE_(|UQXwe#8WBQjdh8`RrH1u+;d&_g2=9A{OB_AmeHaCZvOH7!<_@V#*5Zf
zWGID0^`BQ|KsxIxDl=z6BZ!(k$;;2zYH0aQlsYWfP(uzozmP$XI+^2R%nBb9(<2Xb
zwpw-K;b5#x3&woB2!EuMXRXI0R9*Z*xy3RN7BUlK6}juo7ljhX#q`2G@_Trcgnz!;
zi8&(Q9~Ub}Ub&uUaA+L|6-hn(C}xQ=DvddD1|A7YBbvhjHpWPEW%U4(f!KK51mVL@4@+WmguEQh8kj~^Emad}18p^2O(=}C5)sp|f~M-%=vrHS6&tL(sX8JDw29n^jv`#}
z(MXVzpa~VPh`t*7sQ@O=*fagryzYK=Sw!S~k4)Vnl(LwVy6vc^yW__t~pj#friE(Dc4K$`w
zkc=wM*WEB=;4Mw@B+=5~cB4b=*vR!GxppAeJs?@>>flogC6d$1rr@C@3_7?+djSR|
zHrYM$eGzpBgt|_QIH(U654y?z(z|9YCZ+Y>lacvGtqEE#?MpKXy)%OwIP}a+d<-6c
z6R*s~()%+EMC|2o3f;j}3r#Q2J2iazg_uODB_1(?9PgQtP|RsKK}-(Om5bHRoR|bor%0=#Ms+NQH^V4RYz`V=
zs{1#*6sS*CQkf{GeMz+(qw9nltxOi@i{4oj3e1-)?DvW3J5W4BsNx6&Xnqt9gJ6Ke
z(N35(2_(Nzb#ve*6eSYu(Xj~!<=xak-HV9J|Fk0UAt#WuRS6-y&18bHPN
zR_Ki^xbdA5vF|QMBovN(AFGjYR2Lpj%maNz81XUv`uw|L$j56M2}5=H&%;po16|`{
zrpJoGoZK^2-_>d)OwFrXiVQb4_TP`3CSZjhRKPH6I%9-6Tn4)
z#{pjlJPr6Z;2FSLz~2CO0bT*z3+MxV_XCCi9s-O2`~)x_@F-v^;BmmQfF}VRfTscf
zYCM|KzoEVj<1-uKBp{r5fVTlI155&34VbD4e=Y12V6O(u2iy!;1lTZr)pT_s-jvR-
zfX@Y33pgEcKVT)`QNRj7dLT=zbz`3C*@VP)N+I3_#ca##j!RWdx{Em|-r$t{9y@wd
zYUhQWaFW+>{Ok=)xYrv*YaFFt&CJ8=NN)A#Q`fnvGZC+YSD%J+((8CUb6Jc4X{P5%
zASpwghie^3Cru}*brR`-WAXf?kH&@ksAmfZm*a8Huh~b{Oa;82MR>Hf+jL%v9l6Hy
zlIipY$|IAHp7|OLy64ty*!behuWo(wZM-w}>~rg$dwyN@#ur}N(kwWjxqpyfAo2c{
z-#l_y5FbW!(sGDvXAH8uIZM196$FOo_y(fmVma6HypviiJZA
zIdGoc#~#9BAZx;1z+oqR+<4$;V>oWE62}KQ??To#GDU}j=#^|G_;fM5iUZnzQXJ52
z+0=kmtEUFAN?k%nKNb?s6b7CILlO(T3Ahn*`x|}2a2C~v^O#sjN0ldm1$L1#hz*&q=VX4W`g>Zas
zDKS;zI8-_yL*lWW+jqDf_*o?=atQp@{jIGnI4sO(;jUdJS*am@b!J@xE(9c#8`6T(
zO@}wgdL8>IX5kc+dXF~}!#HRyy>-fWaI^*T221>k4(J_#L_kPa__-yRT<
zuv%fAULm}hDe^TASqyYYegnMrW{|;HM>G+HSMGq$yHZ0OFt$C=+a8SYp!YsWEoh;gF@EH&r**~JqCGSriQpqLLOiRpyL#!hk?cD@#W+0_^cbp
z5ylVjC+Ipa9pQQDtoygbBg&E)&}X46OJ@kzEw2DA`8=Mj1D{{#w2(#kdKY~Lu9onN
zC}USrLzXSnq5MU%PM2kPNayasSw738-0s29&xrD-)9Dh8sLNCbz*A~WqkN2-8vq)~
z2}%pu-C}h3u3$Y5$wNMjPjIDvEahP<9jj~yK4}l;_B2K2nISQp;>|)LJ4^Yb_syUg
znIXYoFeEDEmxUw{op?w$()kvdULKv1j#N&fh#m@D$IQJr{>$Cuw~vlZk0bw*4>X_P
z7Ey!y>DW9@hacj*jr_Dk7$_?PRar7!79#9s=g&7!qmS}c8mJz|XOiBP`pDY>7wUz-
zq3{P>8O~u?;TznTJu`F^#L
zr8xZCow4ta`Xq*Z?vpqHrUvFTOgzl%$A!5~gA*;PfxU~gM`-A&z_-Ed`afu1mSI&w
zM+*1#M#9$Ww5bty@<()v|MD-IHb4Fgcdg(4$9xheN`8k%rb^TD2EzRUcoQ`8E8w4a
zj%a8xz)vIJF2FG0&0#402f$>)jD#5vQvh=}{1?GYhM5hs1V$9TE=jMquli}k>rW39
z_HzScJRdU3&9h+Pm*`$va>}68v~;4y|E;d>UYH`7=`eF(7Qq~a@w=_AE)1qUOeBmM
zW{Ih;?rE56m=|DPm-e(0hYRNxZFaoPMLWo}MojVv(thQg{0(%k`!G9yX4{2>8brj#
znD}f&5l&KzW2v|w;=xG*KY#3Tqn#$fC)^+pTOLvck2Ji2M(^@_gQa~Yj|?v^<>%XD
zdm|ivPnn>lg7Le-bY+;rhkF9H6)9o@7Y@MV;`qH{L65~NkWP4TTH?&)&l`^z4IZn(
z&2;`+>J_8GV>P&0qkD`7kJaF2yv^gtDRIO|7%QQf<(AXYF|juza5a^&-^nL`A}*ve
zy~j)WMjbZ6SPAKzL7~Gdhqj$S5^0oQ%-3E$cd0=aX_PnBfp2dRUwK)cnPg_RudADQ
zb6s5z!1fvwufer+6(0ci+fgph!0dxL4s%-CF9PaOKB>%x!1%yW*}WyPuC5QvJea#-
zY%tSd=D@TZ;5FI6D`9G2UP-E}y9W4)G#3F)15qzv*1)_5vkfKyd?_%~VAjD<99f@I
z9n1V)$IcDLmEb&m<(u=ko!-5UQ!uCjjF)h@gjo{a&!NfK0g!%lod!qy`ARi^m;@6*
z%mw??>*zG`!@J`*bccVOA?7Ufeh)tAfm6qP6ThAq3P{7F9sgn&DqoXf&>QQ2MV5x|MzYlKZWwn;Lm6h1vXEywLm`*kTg|lrYFV$>UWS1bPczeS;n{y(++s`z4C>OXbCJMUFb@A6ClfRu;cv$Da5@=iUeN=Ovxn1lSI+0OrSwI`55@XPDA~EcBb;!~XD1
z(x+fCHKk7qyWnd~EcG)cUIg?5RPB1;e}Z-m#+;IwkP?@fLf*|O@$g9yG(ZAGNa>x)
z`aoV>dsb5yLE(_jOCobVw0
za(XO0ksql7i;Y2;y?b*vh%1y%7j$N&d;6nVFJ;^h_a392_8@N5Ty4`+&DE3~88>
zDfEm*;FNTfIQ$R!Ln2V}QaX@Kk__<_9oC1Z7VKt$WU6+_OkN<3E1Z%!g!`c=QSAF5
zNOF;05pPO)q)n_@=ortll9}Tv7Z8R>Lb!{#nd7BCly)LnNiRxXW|r~k!!r+IfR#!F
zf)?on(S4DkoxmI3>}np?2H57nt9j%Y;&U~x8KB!&(0zig=3!3D#sZoEmjTiMr;Fd!
zJWScx=~h^8Z+$h778B{)q=Xwo{COcK+%HVeZqr}Qo1nXz=N}??*1{eTf=M3S$pnS?
zvV7u!X%X@(%QsxjBc7Hj9ezVY{$MuHi9bxralzh7;v~OyhzN^#+GyzE8hTre4(&8L
z+@$g&+=vh#mMO!!SwnBHp?A>8Q8aQoOL`!5=n{hO!b>^b)O3LS$S@(FbnYJEO_LrG
z-ZbgyV_@UK`wIL=Yr^WK2`d(pWi<`saI<*2468S5&obec-1=z3?W+klK_j!D#6N+b
z{vlV{Y$<18NC1nHa#A$>gETs%YUpVidb)<5p`lYHpmIX_J6NOt2+2PWVUG+s&t}VT
zM@jwRjg8jG9HWtWr=%}~-?18=yEHs^Yv|)N^qeq}&Ln>VK9f%6kc>rBwu>ZBHRv`e
zhw`-q<%;4#={!{5h1S*_I2AJWigV#$wW
zQn<5N9m|Fc!m-xJ(>4`$y~IhrS~t%@zK_%`3v{EDp8#2?vD`1ky_uv_90N6YkmMnH
zbCfsYrLcpc!+1cl>-@ZJg5FQaq%v%fIO$;YGqL@o3v@PNwQ4i`5$-E_C{6wR6!x~H
z`)lw3KW~|Dh850Q$rI@3&5IzvwrnrxP?t5AGD&{0Mt+Ef-U4z+cj9TO!9xR^vqMr&
z7*_VEeh^QqK#~4OVQ(#Q3agFO^CaluQa;7EZD0gDE#2A%j#vYjW~
zFGSP}N@suB77;x_gEtFr&0dFJ;t34*@&|>tVPiofdUFjuSho2jr-i014b`-Jtu*vD
zvJWEuwrKy~mU_0+=ysEaKSCqtX4%$}-wqlcMdG!Pb!)gkqdLLMl19&-8az5YfX$O}
z>7}8^gx|vU%DBgA=<%9%J1sn&?Uy{hVPR~g)Zbs~Ky6W=#HsuQY5K(GGLNWi1Z&#c
zkg!(FE#>Gme)TF2euGB7QKkchWs>xG;Jz3Sj7ONa0awRG#G{kpu7#Uk({~s&Wkzkc
zsk{Y1=NR}SJzFT=_OPWQ+S`?o(@N70I5hp#B;+IYV)OQe#`i%&Fof?|4o3DmKZ)U%Ey}}#6BUHs{m3N>j+o`*a^@9*cq?_
zuoqw@U<@GXO%q89kJeYHe8vG%8H|^7T9YF8K7b^bHa0R5&whXu5A2I_{@bKGEeb9I
z{Z8pV7H}Etl+N=YhtgSx_Jh)SCG3>WZa_-sYCsxmZwBOJb3mTXfRxU!15!G_4M^#{
z7m(8V5Fn+q9&(!l9)%tIHS8oHr8~uw(w)+;CE)k4Q~FbUDg7zmDBXX9ozmS0`ck_4
z0n%JG43N$Z_!v#TF-E;R#7FP$qu09wb$a*ye`1aFicjKdm``99!A_d8?K>zPJ9X~Ttu!ykfxFps4MBYZk$GuO4^1u=@O2)C
z6^Bf*_R$;LZlm
zvZci1$J&6Y$KUks?#QSsef91hfHMJg$lyo%>)m?5!~OJb17Hy#ZT=~MM!=om^9M91
zzz*5zu$urKu-|8M_5BrcD-)1)^x=XyKvVmRerp0SZjfw4Gh_=#UOngPk*ampp
zbYtQb7=q&;uWz<3HztyCg8t_+VYB~D8uGV!&Gr6CuGZWQS!51N-X6dk3o{J<#)2mr<`BYr6o&BM
z_8Sw|eJD)(gI+x5fWR+EH{_GJ8T{r+KbydF0r(#5ThHx@(!Vu5&27a{uRs37Y69cH#w<+BAFZhyf;O^7FjdVDTcvk?b`e-5P
zkg7=s)s5m_^p!EO6U@vLi0_x+1HS+0zi0Zu-vgf;6KBI;Q$_)g>Xr$-<~Yg+Oc>0B
zFNE7fgst+ZkmPF3GVqYueGGmPo@)AN>Q*pvL`exU2rMB)$X?D`P3tSP&$H
z0IfO^6hB%)`w}
zt5d*-q=*2hx6tXCUJr<0RQT0AH`-A>>xS_%W4|2IyD{u%nV+FOM91~pCwe!{9fyG4
z0`xNn_3lu>EWke0F@moz;F2Tgv%nW{0RCYQTc~&E0ABc3@9qYe4);jF0Kj1QPx@5v
z?f{toq2ApS^!5nnX4v1{uXo=BXa)>~yiPOp?jXP`_oJN#e0w_Db?7w)P!ISz=mx;m
z@NWXt!>+*pzG-@Q1Ypz$&fLFuA3d#i-w*rI3cY(e;It*s
z4+DlZ?;-vez?@i$_yeB%8u16L1T+Hf{|e~OT-f}dp_gOu=%=}*O4g);;ccc^Gf$#M0)_^VH-Ue_c?3gC7X~&TcfR)g<
z9bgjdHvwKi`bGd&FGs!t4ncZ#09^M1@(1vC=+_Z&&KG)jXTV2}>D^rb`+Tl10uG7sqsc=$1-FJK5@4B(%3y*n0g0m=>a=euF2{`~D-
zdN*S0`Gvf$cmIa<)t#WkZ$%nm+_o5a>d%5c6ZqPf^ln-om<4g2GG@rJLT^n;44>p!wQpl3h0|xc+>VY%CcG>GJ&f)PkY>p|GCJ^{{rwKkWcyq
zAYaJuyTD&}dhsamsAZ{kq41jwp4U)Mv%ydKvhHE8%u2*vk96X1>bD~`DK7{hT
z3-~QRddtQkv_EQ@+>E-e;wG0DKZ(3h>G1CP1)$E5%-Nuvdr|K`3Y^Mnmv{BO9itf2!Nw
zN#1h%+cRGL?RP|)P+dDW+l$|JQSeY3a^aL0U#G#%72dLR0Chx-uY$HkEn|~q-Jx;0emoU@oT|f1}EH~-OQ%4t(<(4jncJXeb^|$
z#Q)lLktCX}*IzXdB%j1jyau0uX3a6#6@G|Qa2b63xI_3kV`BgF#>7mRJeV#QjEVU$
zDjWk^-K?+LnEi)+^xcP#F5dm=u3bqT!-tKY^V{)9TdhB{uZ(pNs~aKlgt
zb2^NL_;5(XQ$z~WaNocn6HNWIpj1;+Ab^EoH>f?UV6U*-@IHExE`rj~ST!ke!>rl!
zm%p_?`$~!(Pn_l2>?zr5i2whAb>YwdcJ}bSdAEiI9z1gX9@g#n{Ka!}7W@AEN7ok5
zKV5ma`=AG|z59%P?7EJrEBzfxtFAv@dc$6|@4>2?x1M_S^wekAJMZ1}ddgFqzkRBA
z^Guy#{})$(+tgz5Z)e|l{_+p&XGPr`wQa?P!-mbuV~6LqI9Jnz!TDECPQ3U~BLP0iIiHaJK*q18fNx{+z)b3i!ktgF6f`3$PVn0{pcG
zJo&i6-3HJP_He-0U~da}^a)GJ
zduKoe{<;9_0iyu};NA;x0o-E&kGKu)IKa(-y#dDpCIFsXWpMWcd>XJnU=;WV0*1gn
z1+WzKL4bPDQvnCSo(6bysllBN*c|o@z!zZ81YG`%!95soAK(bUdjUrR_6Hmdcw(i&
zJqB<#`0oVV`Lw}37H~D_cL8RBem9^E_Hlr>z-|MKfxQIqk0l28R6s0(yQcvzT5WL8
zAUfnc0C;GH!TliM5%5(4x?z6^@DLtQt_Mtk-2k{8;rIalg8ZfPHGiJhx#@h3>w?Zr
z?WFlvoqHzqnF+pGfOB3&IfUGHum=MkTWoM|#}exPy0diy>#lUT5d8hMftME6MKB+h
zd#SGO!36r+g!ku*g9{yYe|YU^hx;E^>kF2{`A=s=xLcqf;IfyXAK=$7KtI4=U^fEp
zgnlMK{oi44!Pq8*kE8p%0=8diO5DA|l=y^%gntW@ps^F}g0wfJlUuIXsH!GO$Vy&`0
z;7mX|7k3w12@bX!`h7b*-7
zuYEn?;6T4Z|7AbjQhnb$;qf=UwcU9ssdwh;5xxF4`c&;RM?d~`{!4Z12OOU><+F7y
z{`uRROBUzPIv;oTSk$X8-}=Z$t3H@F`{uBRR!rKL^W0;1-ZpdB$ng>1yM11%y8U8k
z_G@1Swp(!GWWOuQlU;^wSo!qE3lk36e*AOK=j@XXrGwr+GivU&Y4;3%-@Nnk6MvMn
z{^G9XsXu)9ZFuQdsF-5yzbG>U0M3O-|c$;qdmr*GX-VX9Zx+Fa-e0m
zPlpUYGBu{CPx*|~KUYp%)OXFjlWX34F!9CbziFF$b?Ef1&3^g&9i4vvuB>y%y~ckO
ze7R+8v1Lr~v$2o2@$DbU>iu-I{owuKZjIN%i^mrlJ2lrYdhNXRrfmfA<5vCRdRE3B
z*SZ3y?GOCamfz%G&&u?)jpA_yM%xoAGdX=(-|F*JJy)i~wTybd@9NoLnc^s#Fm`Ch
zz}Oz0BU&{_H}rM6d*k8oPYy15?8)u6%?p|C)WyWfcWrqveCODM7tfwWc-t=8Z2ey{
z1l--WZRKMSp_};ns^SxE(jWY|Y~tr6UuQ9y7az+yGkVg<46>tzT{^PHR-2tZ3$=~^
zwp^;a^7YhT-DT3wp56G+xIJeoyQ+4kf4{QD(al3Wc4l1Ar|Q|+pegn3jHXN4pRST^_MdR}jjJIopE+Ip=HLIQP1tE2Zd!Jw?TLvu
z-7~CursL=D&p5ZVdbe)lYZ)*Cx5(m)%37A2fs;qJ*lE+{~z)@ELk+8pZ($@?5t2D1pMmijN&V-8>1X$QTjIJ0$?c^#(s!IW@%pvFFG+eb^H1*B
zQT*iTIT_o|?tW@V@cw55yV#?C=vgz{b^GxRo5vq}23XgAO8G-oR_6KAKp#>V9P
z`*)3tDMOH5%Q&&Pls;#c?|qq^zs$;*9iPvmo4#~t*_tniT`lM@>3#$~=)oU{Q^pR?
zQj+nAFdk3BU10v&WjU8SWH^06dU$p+;+>sa#_Pc-{xtwa$#VWb#hndsRMi#7-{Qh%
zC|cTTixlkx36o(GHl%5qrmPJlq!A-h0i}RIHoIXLHydU*2?;|r+GtTzr8Wv$uuqDb
zp_Hap9LA=I$V@Y%BDG3W#&(cN8S2o=IB3yE?eE<8v2T~nhvSUCng9OJJ?GqyckkV|
zZ+G84H`>TDj5b|ILl1FWB`@YNj~I^^j~^*6cmHlg8V
zCvLMJ{K-&VZ6c&u?9b&&O5em%ol_ZQ=Kw;6n-86*+hnZFa_Va1dYm;Qs;|s4mBF8A
zY>)^rX?CTv>Zebd;{{2!$Ye8)a7YhHb&XAlHnV|C7wJvW2HA8?Z;)WBF|$iGmtK^5
zsJ4w2*h-8vHYaSEK%31xwryFG@@#fU4R%sZQG)HW`d?b2;wYzCei(&x2NiOO(YxPh+HE37R-tZhIg)RJuOaf^xs
zC}X=KH*|Au31?K&tX~_H?0Pv9N0l+JhW+H|7i+7xIPVKtX|8OQ(WLCRr>=?fs(3RY
zuaXEVQ~}YeM6VO%OPJ{AvU-6U7PZnhaItWJV_tJK7AjzdRG1;TlA`47gch334~*e
z*M;+m4W@P{4NHXd@9LJjmRnHtEkdTMjuPF{B#0^^j}Zz>0y*0(01
zV2rpS`G5+9_NHDzW}o5=Sy&Cql<$I@3^bHfjA)+=J+S~_*DE*nPL
zQ<7^IogCJ=0*Azgrx}(j`2M)SM$iH70o%Z%pd0K3`@sRw2abS#a2mV^v=7Dw#)BBL
zK&=Nl#FHDYn_Ow1Bn6_EU*W8qYUP!vCn{)d!_`;kCRY#;?dCF_>m~ud9KA#wQGu(N
z>ehSrLYpiSRc}KrT;I(2t4$gtr?U{u$rEo>aXn3gTn<$ZmANU_azRcfpBPgm^5!&a
zbnJ4`wywS^kQ*hs+9F{h-OWjzAMHsqrZ-7*+LY$RJhl5x9MWt~)2#Y~Dk`zv6HY$r
zO|xXFH_guYIeF`9*QhOyWLZ+{L*I2hfpwFQ}XSU1W;3JES7$nIo;soaI2+;tp2VV
z-2SCQ`In|zWcjzQj)c_-XO?dooaR{POI)=`SeE%voq7ro-vMIcG8|@@6t@*K{JGPs=aCU)Oe=nC$u;p3ac9vMAzl+b%R7(
zGz%KR&nZw<<80gQ>aTQzbN*>+VkxD~!Azr*i_bziUArEM!9;6^%_|PB{ORXo?@B(@
z`8syzJe~Y90l7g`IjvZwO2r5B1wK~pbbXW4sxnc4O7z)pHjw
zo`1uVvU+`LKwr4DrbcWn^~u$8uQiMBsoZ~<0RYgu{KZwW%#5qZr)Hk0B*>(AbwYM$
zWYoEbQQjLOe63X`^V_7l{m51(_r5$IbBQm|1=d;E2JZyB!870qi}zam6l_#^jl}o8
z#sRRg+G|uT@EWJ!QqU$lE2$T1ms`&^+7jhUBj=^mRv1(J##`xXc`usV@o9c;rTyU+
zz7A>H;l-4@#A{p)?}rb9fg8LAMLGASRTWj%?~bA@tdLju1)fFYCv$!@w~nzH$G8y=
z-={osKIdc8a$n%SmA*i$#kV5c>2`Di(TRPf3-=%w1x+k~^DR`a@dfO($fB3@Ocy4E
zd;yv8=0SAWygWOR;>{D&4|{;TUQ0h$9da+9d6*9K)M5U&p8hI!U5)?e`x55MhO{7f
zn=kO6_H>lrm7cckV{Z2aMg!YF8&9JQ(SOvz_}%FXNZLlG|73h@-B=a_EoAaG9%LCX${-ed}PmU3UGV@7wGPEC)7=
zeDWS&pa&ia;yV-$WY|KKxm;lB$KRcjZQZeqJhr~ymCx24$)dAu!k#7?%(>DX{C!L4F3GBVZjkg
znOGvf8w^T3iA%Q(2Iraoc&Wfi;gI>Ci9Z&KG&Y3&NwzWBP@4$*n;IKq$)Nm$;7`Wb
z3bx2Eo3$rdBpCKD!N&F>(YQYm=GWA
zzg(xd=Vc*~WCdym1zGv2*rLWS0T
z;@fR6%&pLj{yT3fZmH1v7Ori0{?`>+;Ad+Fmc3a~-np;!ir-#Vx#;ba#|9=}Tlv82
z*NuDSY2E&Gd8iif
zBn+SBJTnDk4X!-6@)aNteF(Q)2zR!%gjHeMdL)J&Q0b@aIkFg22;9JTtdEL29Ay~@sTeji*AZH
zl^(#BXZcJUzQ`U1-5z5-vW{Gce0m4_2OuAR++(bSBjWRr$LNH&fp?zr7(H+=
zxbkU_u?_!znZ*at-qMLmndrZvth=+u=Rn
zM&y^^*T8{iXb*f26z!$VmuV+x>G2qq@FH;FPLI(9w}W}Kxt(*_CF$RIjP3{7;{kd9
zc8_rwehEB*e?L3`@^*NP^V{eXK<0PRtaQ3_XsbI1|66`cMh?S%J$BL-!{
z{h;bG%7L|427@KLDF>bc#ysgU3gJ0m*Xh`pYVQgVynk^O&CnS
z!($A>IY;q9o(>m+zK1xgBg@_7(NP?koOFH9wd-2{WE-H0CEIw0+G9E8{7$E$lKv=u%CAJ!hN8Va^8T?fC=|{4DYLqHQ3%sJKd6RRU
z%{shk{B}6VI3RyC)obLzg&>4n3Dg!%(5Y~!_*E5ColoIa&dEpgaV-l=`6O+A0K3oV^A@k9p
Nj+#YPH`#JF{y*0C$m#$9

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl61x/board/config/bl_factory_params_IoTKitA_auto.dts b/bsp/bouffalo_lab/bl61x/board/config/bl_factory_params_IoTKitA_auto.dts
new file mode 100755
index 0000000000..92228f5ba6
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/config/bl_factory_params_IoTKitA_auto.dts
@@ -0,0 +1,352 @@
+/dts-v1/;
+/include/ "bl602_base.dtsi";
+// version: 17
+// last_comp_version: 16
+// boot_cpuid_phys: 0x0
+
+/ {
+    model = "bl bl602 IOT board";
+    compatible = "bl,bl602-sample", "bl,bl602-common";
+    #address-cells = <0x1>;
+    #size-cells = <0x1>;
+    gpio {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        max_num = <40>;
+        gpio0 {                                  
+            status = "okay";                     
+            pin  = <5>;                          
+            feature = "led";                     
+            active = "Hi"; //Hi or Lo
+            mode = "blink"; //blink or hearbeat
+            time = <100>; //duration for this mode
+        };
+        gpio1 {                                  
+            status = "disable";                     
+            pin  = <6>;                          
+            feature = "led";                     
+            active = "Hi"; //Hi or Lo
+            mode = "blink"; //blink or hearbeat
+            time = <100>; //duration for this mode
+        };
+        gpio2 {
+            status = "okay";
+            pin = <2>;
+            feature = "button";
+            active = "Hi";
+            mode = "multipress";
+            button {
+                debounce = <10>;
+                short_press_ms {
+                    start = <100>;
+                    end = <3000>;
+                    kevent = <2>;
+                };
+                long_press_ms {
+                    start = <6000>;
+                    end = <10000>;
+                    kevent = <3>;
+                };
+                longlong_press_ms {
+                    start = <15000>;
+                    kevent = <4>;
+                };
+                trig_level = "Hi";
+            };
+            hbn_use = "disable";
+        };
+    };
+    i2s {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        i2s@40017000 {
+            status = "okay";
+            compatible = "bl602_i2s";
+            reg = <0x40017000 0x100>;
+            mclk_only = "okay";
+            pin {
+                mclk = <11>;
+            };
+        };
+        i2s@40017100 {
+            status = "okay";
+            compatible = "bl602_i2s";
+            reg = <0x40017100 0x100>;
+            mclk_only = "disable";
+            pin {
+                bclk = <12>;
+                fs = <29>;
+                do = <30>;
+                di = <31>;
+            };
+        };
+    };
+    i2c {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        i2c@40011000 {
+            status = "okay";
+            compatible = "bl602_i2c";
+            reg = <0x40011000 0x100>;
+            pin {
+                scl = <32>;
+                sda = <13>;
+            };
+            devices {
+                list_addr = <0x18 0x21>;
+                list_driver = "i2c_es8311", "i2c_gc0308>";
+            };
+        };
+        i2c@40011100 {
+            status = "disable";
+            compatible = "bl602_i2c";
+            reg = <0x40011100 0x100>;
+            pin {
+                /*empty here*/
+            };
+        };
+    };
+    timer {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        timer@40014000 {
+            status = "disable";
+            compatible = "bl602_timer";
+            reg = <0x40014000 0x100>;
+        };
+        timer@40014100 {
+            status = "disable";
+            compatible = "bl602_timer";
+            reg = <0x40014100 0x100>;
+        };
+    };
+    pwm {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        pwm@4000A420 {
+            status = "okay";
+            compatible = "bl602_pwm";
+            reg = <0x4000A420 0x20>;
+            path = "/dev/pwm0";
+            id = <0>;
+            pin = <0>;
+            freq = <800000>;
+            duty = <50>;
+        };
+        pwm@4000A440 {
+            status = "disable";
+            reg = <0x4000A440 0x20>;
+            path = "/dev/pwm1";
+            id = <1>;
+            pin = <1>;
+            freq = <5000>;
+            duty = <50>;
+        };
+        pwm@4000A460 {
+            status = "disable";
+            reg = <0x4000A460 0x20>;
+            path = "/dev/pwm2";
+            id = <2>;
+            pin = <2>;
+            freq = <5000>;
+            duty = <50>;
+        };
+        pwm@4000A480 {
+            status = "disable";
+            reg = <0x4000A480 0x20>;
+            path = "/dev/pwm3";
+            id = <3>;
+            pin = <3>;
+            freq = <5000>;
+            duty = <50>;
+        };
+        pwm@4000A4A0 {
+            status = "disable";
+            reg = <0x4000A4A0 0x20>;
+            path = "/dev/pwm4";
+            id = <4>;
+            pin = <4>;
+            freq = <5000>;
+            duty = <50>;
+        };
+    };
+    ir {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        ctrltype = <0>;
+        tx {
+            status = "disable";
+            pin = <11>;         // only support 11
+            mode = "NEC";       // NEC,ExtenedNEC,RC5,SWM
+            interval = <100>;   // ms
+            active_mode = "Hi"; //Hi,Lo
+        };
+        rx {
+            status = "okay";
+            pin = <12>;         // only support 12 13
+            mode = "NEC";       // NEC,ExtenedNEC,RC5,SWM
+            active_mode = "Hi"; //Hi,Lo
+            data_check = <2>;   //bit 0:check cmd, bit 1:check addr
+        };
+    };
+    uart {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        uart@4000A000 {
+            status = "okay";
+            id = <0>;
+            compatible = "bl602_uart";
+            path = "/dev/ttyS0";
+            baudrate = <2000000>;
+            pin {
+                rx = <7>;
+                tx = <16>;
+            };
+            buf_size {
+                rx_size = <512>;
+                tx_size = <512>;
+            };
+            feature {
+                tx = "okay";
+                rx = "okay";
+                cts = "disable";
+                rts = "disable";
+            };
+        };
+        uart@4000A100 {
+            status = "okay";
+            id = <1>;
+            compatible = "bl602_uart";
+            path = "/dev/ttyS1";
+            baudrate = <115200>;
+            pin {
+                rx = <3>;
+                tx = <4>;
+            };
+            buf_size {
+                rx_size = <512>;
+                tx_size = <512>;
+            };
+            feature {
+                tx = "okay";
+                rx = "okay";
+                cts = "disable";
+                rts = "disable";
+            };
+        };
+    };
+    spi {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        spi@4000F000 {
+            status = "okay";         /* okay disable */
+            mode = "master";
+            reg = <0x4000F000 0x100>;   /* 4KB */
+            path = "/dev/spi0";
+            port = <0>;
+            polar_phase = <1>;                 /* 0,1,2,3 */
+            freq = <6000000>;
+            pin {
+                clk = <3>;
+                cs = <2>;
+                mosi = <1>;
+                miso = <0>;
+            };
+            dma_cfg {
+                tx_dma_ch = <2>;
+                rx_dma_ch = <3>;
+            };
+        };
+    };
+    gpip {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        adc_key {
+            status = "disable";
+            pin = <9>;
+            interrupt  = <3>;
+            key_vol = <0 100 400 300 500>;
+            key_pcb = "SW1", "SW2", "SW3", "SW4","SW5";
+            key_event = "Usr1", "Usr2", "Start", "Up", "Down";
+            key_raw = <1 2 3 4 5>;
+        };
+    };
+    qspi {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        qspi@4000A000 {
+            status = "disable";
+            reg = <0x4000A000 0x1000>;/* 4KB */
+        };
+    };
+    wifi {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        region {
+            country_code = <86>;
+        };
+        mac {
+            mode = "MBF";
+            sta_mac_addr = [C8 43 57 82 73 40];
+            ap_mac_addr = [C8 43 57 82 73 02];
+        };
+        sta {
+            ssid = "yourssid";
+            pwd = "yourapssword";
+            auto_connect_enable = <0>;
+        };
+        ap {
+            ssid = "bl_test_005";
+            pwd = "12345678";
+            ap_channel = <11>;
+            auto_chan_detect = "disable";
+        };
+        brd_rf {
+            xtal_mode = "MF";
+            xtal = <36 36 0 60 60>;
+            pwr_mode = "bf";//B: only use power offset in EFUSE; b: use power offset in EFUSE with incremental mode; F: only use power offset in Flash; f: use power offset in Flash with incremental mode
+            pwr_table_11b        = <20 20 20 20>;//1Mbps 2Mbps 5.5Mbps 11Mbps
+            pwr_table_11g        = <18 18 18 18 18 18 16 16>; //6Mbps 9Mbps 12Mbps 18MBps 24Mbps 36Mbps 48Mbps 54Mbps
+            pwr_table_11n_ht20  = <18 18 18 18 18 16 15 15>; //MCS0~MCS7
+            pwr_table_11n_ht40  = <18 18 18 18 18 16 15 14>; //MCS0~MCS7
+            pwr_table_11ac_vht20 = <18 18 18 18 18 16 15 15 15 14>; //MSC0~MSC9
+            pwr_table_11ac_vht40 = <18 18 18 18 18 16 15 14 14 13>; //MSC0~MSC9
+            pwr_table_11ac_vht80 = <18 18 18 18 18 15 14 13 13 12>; //MSC0~MSC9
+            pwr_table_11ax_he20  = <18 18 18 18 18 16 15 15 15 14 13 13>; //MSC0~MSC11
+            pwr_table_11ax_he40  = <18 18 18 18 18 16 15 14 14 13 12 12>; //MSC0~MSC11
+            pwr_table_11ax_he80  = <18 18 18 18 18 15 14 13 13 12 11 11>; //MSC0~MSC11
+            pwr_table_11ax_he160 = <18 18 18 18 18 15 14 13 12 11 10 10>; //MSC0~MSC11
+            
+            pwr_offset = <16 16 16 16 16 16 16 16 16 16 16 16 16 16>;//due to the limit of current DTC, negative value is used. So we work around by adding all the poweroffset with 16.
+            pwr_offset_lp = <16 16 16 16 16 16 16 16 16 16 16 16 16 16>;   
+            //so 14 represents -0.5dBm; 16 represents 0dBm; 20 represents 1dBm;(step is 0.25dBm)
+        };
+        rf_temp {
+            en_tcal = <0>;
+            linear_or_follow = <1>;
+            Tchannels       = <2412 2427 2442 2457 2472>;
+            Tchannel_os     = <180  168  163  160  157>;
+            Tchannel_os_low = <199  186  170  165  160>;
+            Troom_os        = <255>;
+            //negative value is NOT supported. So we use '256' for 0, '255' for -1, '257' for 1,'511' for 256
+        };
+    };
+    bluetooth_zigbee {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        brd_rf {
+            pwr_table_ble = <13>; //range:0~15dbm
+            pwr_table_bt = <10 8 8>; //BR 1M,EDR 2M,EDR 3M
+            pwr_table_zigbee = <13>; //range:0~15dbm
+            pwr_offset = <16 16 16 16 16>; //step is 0.25dBm
+            
+        };
+    };
+    info {
+        #address-cells = <1>;
+        #size-cells = <1>;
+        brd {
+            country_code = <86>; 
+        };
+    };
+};
diff --git a/bsp/bl808/partition/partition_cfg_16M_m1sdock.toml b/bsp/bouffalo_lab/bl61x/board/config/partition_cfg_4M.toml
old mode 100644
new mode 100755
similarity index 50%
rename from bsp/bl808/partition/partition_cfg_16M_m1sdock.toml
rename to bsp/bouffalo_lab/bl61x/board/config/partition_cfg_4M.toml
index 7b75961470..f9ade510d7
--- a/bsp/bl808/partition/partition_cfg_16M_m1sdock.toml
+++ b/bsp/bouffalo_lab/bl61x/board/config/partition_cfg_4M.toml
@@ -17,69 +17,110 @@ size1 = 0
 len = 0
 # If header is 1, it will add the header.
 header = 1
+# If header is 1 and security is 1, It will be encrypted.
+security = 1
 
 [[pt_entry]]
 type = 0
 name = "FW"
 device = 0
 address0 = 0x10000
-size0 = 0xF0000
+size0 = 0x200000
+address1 = 0x210000
+size1 = 0x168000
+# compressed image must set len,normal image can left it to 0
+len = 0
+# If header is 1, it will add the header.
+header = 1
+# If header is 1 and security is 1, It will be encrypted.
+security= 1
+
+[[pt_entry]]
+type = 10
+name = "mfg"
+device = 0
+address0 = 0x210000
+size0 = 0x168000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
 header = 1
+# If header is 1 and security is 1, It will be encrypted.
+security= 1
 
 [[pt_entry]]
 type = 2
-name = "D0FW"
+name = "media"
 device = 0
-address0 = 0x100000
-size0 = 0x200000
+address0 = 0x378000
+size0 = 0x71000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
-header = 1
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
+
+[[pt_entry]]
+type = 3
+name = "PSM"
+device = 0
+address0 = 0x3E9000
+size0 = 0x8000
+address1 = 0
+size1 = 0
+# compressed image must set len,normal image can left it to 0
+len = 0
+# If header is 1, it will add the header.
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
+
+[[pt_entry]]
+type = 4
+name = "KEY"
+device = 0
+address0 = 0x3F1000
+size0 = 0x2000
+address1 = 0
+size1 = 0
+# compressed image must set len,normal image can left it to 0
+len = 0
+# If header is 1, it will add the header.
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
 
 [[pt_entry]]
 type = 5
-name = "media"
+name = "DATA"
 device = 0
-address0 = 0x300000
-size0 = 0xC00000
+address0 = 0x3F3000
+size0 = 0x5000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
-header = 1
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security = 0
 
 [[pt_entry]]
-type = 11
-name = "unused"
-device = 0
-address0 = 0xF00000
-size0 = 0x100000
-address1 = 0
-size1 = 0
-# compressed image must set len,normal image can left it to 0
-len = 0
-# If header is 1, it will add the header.
-header = 1
-
-[[pt_entry]]
-type = 8
-# It shows Dts in DevCube 
+type = 6
 name = "factory"
 device = 0
-address0 = 0x910000
-size0 = 0
+address0 = 0x3F8000
+size0 = 0x8000
 address1 = 0
 size1 = 0
 # compressed image must set len,normal image can left it to 0
 len = 0
 # If header is 1, it will add the header.
-header = 1
+header = 0
+# If header is 1 and security is 1, It will be encrypted.
+security= 0
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/board/fw_header.c b/bsp/bouffalo_lab/bl61x/board/fw_header.c
new file mode 100644
index 0000000000..caac91b0f0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/fw_header.c
@@ -0,0 +1,165 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0x00,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0x20,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xf0,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x07,      /*!< 0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.mcu_clk = 0x05,        /*!< mcu_clk 0:RC32M;1:XTAL;2:aupll_div2;3:aupll_div1;4:wifipll_240M;5:wifipll_320M */
+    .clk_cfg.cfg.mcu_clk_div = 0x00,    /*!< mcu_clk divider */
+    .clk_cfg.cfg.mcu_bclk_div = 0x00,   /*!< mcu_bclk divider */
+    .clk_cfg.cfg.mcu_pbclk_div = 0x03,  /*!< mcu_pclk divider */
+    .clk_cfg.cfg.emi_clk = 0x02,        /*!< 0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
+    .clk_cfg.cfg.emi_clk_div = 0x01,    /*!< emi clock divider */
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll_120M;1:xtal;2:aupll_div5;3:muxpll_80M;4:bclk;5:wifipll_96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.cfg.wifipll_pu = 0x01,
+    .clk_cfg.cfg.aupll_pu = 0x00,
+    .clk_cfg.crc32 = 0xdeadbeef,
+    /* basic cfg */
+    .basic_cfg.sign_type = 0x0,          /* [1: 0]   for sign */
+    .basic_cfg.encrypt_type = 0x0,       /* [3: 2]   for encrypt */
+    .basic_cfg.key_sel = 0x0,            /* [5: 4]   key slot */
+    .basic_cfg.xts_mode = 0x0,           /* [6]      for xts mode */
+    .basic_cfg.aes_region_lock = 0x0,    /* [7]      rsvd */
+    .basic_cfg.no_segment = 0x1,         /* [8]      no segment info */
+    .basic_cfg.rsvd_0 = 0x0,             /* [9]      boot2 enable(rsvd_0) */
+    .basic_cfg.rsvd_1 = 0x0,             /* [10]     boot2 rollback(rsvd_1) */
+    .basic_cfg.cpu_master_id = 0x0,      /* [14: 11] master id */
+    .basic_cfg.notload_in_bootrom = 0x0, /* [15]     notload in bootrom */
+    .basic_cfg.crc_ignore = 0x1,         /* [16]     ignore crc */
+    .basic_cfg.hash_ignore = 0x1,        /* [17]     hash ignore */
+    .basic_cfg.power_on_mm = 0x1,        /* [18]     power on mm */
+    .basic_cfg.em_sel = 0x1,             /* [21: 19] em_sel */
+    .basic_cfg.cmds_en = 0x1,            /* [22]     command spliter enable */
+#if 0
+# 0 : cmds bypass wrap commands to macro, original mode;
+# 1 : cmds handle wrap commands, original mode;
+# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
+# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
+#endif
+    .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
+#if 0
+# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
+# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
+#endif
+    .basic_cfg.cmds_wrap_len = 0x9,  /* [28: 25] cmds wrap len */
+    .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
+    .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
+    .basic_cfg.rsvd_3 = 0x0,         /* [31] rsvd_3 */
+
+    .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
+    .basic_cfg.aes_region_len = 0x00000000,     /* aes region length */
+
+    .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
+    .basic_cfg.hash = { 0xdeadbeef },    /* hash of the image */
+
+    /* cpu cfg */
+    .cpu_cfg.config_enable = 0x01, /* coinfig this cpu */
+    .cpu_cfg.halt_cpu = 0x0,       /* halt this cpu */
+    .cpu_cfg.cache_enable = 0x0,   /* cache setting :only for BL Cache */
+    .cpu_cfg.cache_wa = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg.cache_wb = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg.cache_wt = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg.cache_way_dis = 0x0,  /* cache setting :only for BL Cache*/
+    .cpu_cfg.rsvd = 0x0,
+
+    /* image_address_offset */
+    .cpu_cfg.image_address_offset = 0x0,
+    .cpu_cfg.rsvd1 = 0xA0000000,   /* rsvd */
+    .cpu_cfg.msp_val = 0x00000000, /* msp value */
+
+    /* address of partition table 0 */
+    .boot2_pt_table_0_rsvd = 0x00000000,
+    /* address of partition table 1 */
+    .boot2_pt_table_1_rsvd = 0x00000000,
+
+    /* address of flashcfg table list */
+    .flash_cfg_table_addr = 0x00000000,
+    /* flashcfg table list len */
+    .flash_cfg_table_len = 0x00000000,
+
+    .crc32 = 0xdeadbeef
+};
diff --git a/bsp/bouffalo_lab/bl61x/board/fw_header.h b/bsp/bouffalo_lab/bl61x/board/fw_header.h
new file mode 100644
index 0000000000..fd230929dd
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/fw_header.h
@@ -0,0 +1,197 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t mcu_clk;
+    uint8_t mcu_clk_div;
+    uint8_t mcu_bclk_div;
+
+    uint8_t mcu_pbclk_div;
+    uint8_t emi_clk;
+    uint8_t emi_clk_div;
+    uint8_t flash_clk_type;
+
+    uint8_t flash_clk_div;
+    uint8_t wifipll_pu;
+    uint8_t aupll_pu;
+    uint8_t rsvd0;
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
+    uint32_t sign_type          : 2; /* [1: 0]   for sign */
+    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
+    uint32_t key_sel            : 2; /* [5: 4]   key slot */
+    uint32_t xts_mode           : 1; /* [6]      for xts mode */
+    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
+    uint32_t no_segment         : 1; /* [8]      no segment info */
+    uint32_t rsvd_0             : 1; /* [9]      boot2 enable(rsvd_0) */
+    uint32_t rsvd_1             : 1; /* [10]     boot2 rollback(rsvd_1) */
+    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
+    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
+    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
+    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
+    uint32_t power_on_mm        : 1; /* [18]     power on mm */
+    uint32_t em_sel             : 3; /* [21: 19] em_sel */
+    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
+    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
+    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
+    uint32_t icache_invalid     : 1; /* [29] icache invalid */
+    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
+    uint32_t rsvd_3             : 1; /* [31] rsvd_3 */
+
+    uint32_t group_image_offset; /* flash controller offset */
+    uint32_t aes_region_len;     /* aes region length */
+
+    uint32_t img_len_cnt;  /* image length or segment count */
+    uint32_t hash[32 / 4]; /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
+    uint8_t config_enable;     /* coinfig this cpu */
+    uint8_t halt_cpu;          /* halt this cpu */
+    uint8_t cache_enable  : 1; /* cache setting */
+    uint8_t cache_wa      : 1; /* cache setting */
+    uint8_t cache_wb      : 1; /* cache setting */
+    uint8_t cache_wt      : 1; /* cache setting */
+    uint8_t cache_way_dis : 4; /* cache setting */
+    uint8_t rsvd;
+
+    uint32_t image_address_offset; /* image_address_offset */
+    uint32_t rsvd1;                /* rsvd */
+    uint32_t msp_val;              /* msp value */
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /* 4 */
+    uint32_t rivison;   /* 4 */
+
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 12 + 4 */
+
+    struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
+
+    struct boot_cpu_cfg_t cpu_cfg; /* 16 */
+
+    uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
+    uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
+
+    uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
+    uint32_t flash_cfg_table_len; /* flashcfg table list len */         /* 4 */
+
+    uint32_t rsvd0[6]; /* rsvd */
+    uint32_t rsvd1[6]; /* rsvd */
+
+    uint32_t rsvd; /* 4 */
+
+    uint32_t crc32; /* 4 */
+};
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_flash.ld b/bsp/bouffalo_lab/bl61x/board/linker_scripts/bl616_flash.ld
old mode 100644
new mode 100755
similarity index 52%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_flash.ld
rename to bsp/bouffalo_lab/bl61x/board/linker_scripts/bl616_flash.ld
index 3b24a2e65d..ef77620e6c
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_flash.ld
+++ b/bsp/bouffalo_lab/bl61x/board/linker_scripts/bl616_flash.ld
@@ -15,68 +15,103 @@ INPUT(-lc)
 /* link with the standard GCC library */
 INPUT(-lgcc)
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
-StackSize    = 0x0400; /*  1KB */
+StackSize    = 0x1000; /*  4KB */
 HeapMinSize  = 0x1000; /*  4KB */
 
+__EM_SIZE = DEFINED(btble_controller_init) ? 32K : 0K;
+__RFTLV_SIZE_OFFSET = 1K;
+__RFTLV_SIZE_HOLE = 2K;
+__RFTLV_HEAD1_H = (0x46524C42); /* BLRF */
+__RFTLV_HEAD1_L = (0x41524150); /* PAPA */
+
 MEMORY
 {
-    xip_memory  (rx)  : ORIGIN = 0x58000000, LENGTH = 32M
-    itcm_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 28K
-    dtcm_memory (rx)  : ORIGIN = 0x3eff7000, LENGTH = 4K
-    nocache_ram_memory (!rx) : ORIGIN = 0x3eff8000, LENGTH = 0K
-    ram_memory  (!rx) : ORIGIN = 0x3eff8000, LENGTH = 64K
-    xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
+    fw_header_memory  (rx)  : ORIGIN = 0xA0000000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0xA0000000, LENGTH = 4M
+    ram_code  (wxa)   : ORIGIN = 0xA8000000, LENGTH = 4M
+    itcm_memory (rx)  : ORIGIN = 0x62FC0000, LENGTH = 20K
+    dtcm_memory (rx)  : ORIGIN = 0x62FC5000, LENGTH = 4K
+    nocache_ram_memory (!rx) : ORIGIN = 0x22FC6000, LENGTH = 44K+60K
+    ram_memory  (!rx) : ORIGIN = 0x62FE0000, LENGTH = 320K-20K-4K-44K-60K
+    ram_wifi  (wxa)   : ORIGIN = 0x23010000, LENGTH = 160K - __EM_SIZE
 }
 
 SECTIONS
 {
 
+    BOOT2_PT_ADDR = 0x63027c00;
+
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
+
+    .init :
+    {
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
+
+    } > xip_memory
+
+    .rftlv.tool :
+    {
+        . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET;
+        PROVIDE( _ld_symbol_rftlv_address = . );
+        LONG(__RFTLV_HEAD1_H);
+        LONG(__RFTLV_HEAD1_L);
+        . = ORIGIN(xip_memory) + __RFTLV_SIZE_OFFSET + __RFTLV_SIZE_HOLE;
+    } > xip_memory
+
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        KEEP(*startup*.*o(*.text*))
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
 
         *(.text)
         *(.text.*)
 
-        /* section information for shell */
-        . = ALIGN(8);
+        /* section information for finsh shell */
+        . = ALIGN(4);
         __fsymtab_start = .;
         KEEP(*(FSymTab))
         __fsymtab_end = .;
-
         . = ALIGN(4);
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+        . = ALIGN(4);
 
-        /* section information for usb desc */
+        /* section information for modules */
         . = ALIGN(4);
-        _usb_desc_start = .;
-        KEEP(*(usb_desc))
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
         . = ALIGN(4);
-        _usb_desc_end = .;
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /* section information for usb usbh_class_info */
+        . = ALIGN(4);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        . = ALIGN(4);
+        __usbh_class_info_end__ = .;
 
         /*put .rodata**/
-        *(EXCLUDE_FILE( *bl808_glb*.o* \
-                        *bl808_glb_gpio*.o* \
-                        *bl808_pds*.o* \
-                        *bl808_aon*.o* \
-                        *bl808_hbn*.o* \
-                        *bl808_l1c*.o* \
-                        *bl808_common*.o* \
-                        *bl808_clock*.o* \
-                        *bl808_ef_ctrl*.o* \
-                        *bl808_sf_cfg*.o* \
-                        *bl808_sf_ctrl*.o* \
-                        *bl808_sflash*.o* \
-                        *bl808_xip_sflash*.o* \
-                        *bl808_romapi_patch*.o* ) .rodata*)
+        *(EXCLUDE_FILE( *bl616_glb*.o* \
+                        *bl616_pds*.o* \
+                        *bl616_common*.o* \
+                        *bl616_sf_cfg*.o* \
+                        *bl616_sf_ctrl*.o* \
+                        *bl616_sflash*.o* \
+                        *bl616_xip_sflash*.o* \
+                        *bl616_ef_ctrl*.o* \
+                        *bl616_romapi_patch*.o* ).rodata*)
 
         *(.srodata)
         *(.srodata.*)
@@ -98,20 +133,15 @@ SECTIONS
         *(.sclock_rlt_code.*)
         *(.sclock_rlt_const.*)
 
-        *bl808_glb*.o*(.rodata*)
-        *bl808_glb_gpio*.o*(.rodata*)
-        *bl808_pds*.o*(.rodata*)
-        *bl808_aon*.o*(.rodata*)
-        *bl808_hbn*.o*(.rodata*)
-        *bl808_l1c*.o*(.rodata*)
-        *bl808_common*.o*(.rodata*)
-        *bl808_clock*.o*(.rodata*)
-        *bl808_ef_ctrl*.o*(.rodata*)
-        *bl808_sf_cfg*.o*(.rodata*)
-        *bl808_sf_ctrl*.o*(.rodata*)
-        *bl808_sflash*.o*(.rodata*)
-        *bl808_xip_sflash*.o*(.rodata*)
-        *bl808_romapi_patch*.o*(.rodata*)
+        *bl616_glb*.o*(.rodata*)
+        *bl616_pds*.o*(.rodata*)
+        *bl616_common*.o*(.rodata*)
+        *bl616_sf_cfg*.o*(.rodata*)
+        *bl616_sf_ctrl*.o*(.rodata*)
+        *bl616_sflash*.o*(.rodata*)
+        *bl616_xip_sflash*.o*(.rodata*)
+        *bl616_ef_ctrl*.o*(.rodata*)
+        *bl616_romapi_patch*.o*(.rodata*)
 
         . = ALIGN(4);
         __tcm_code_end__ = .;
@@ -146,14 +176,17 @@ SECTIONS
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
 
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
+
     /*************************************************************************/
+
     __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-    .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
+    .nocache_ram_region  : AT (__nocache_ram_load_addr)
     {
         . = ALIGN(4);
         __nocache_ram_data_start__ = .;
@@ -164,28 +197,7 @@ SECTIONS
         __nocache_ram_data_end__ = .;
     } > nocache_ram_memory
 
-    __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
-
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-
-        *(.system_ram)
-
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-
-    .system_ram_noinit_data_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.system_ram_noinit)
-
-        . = ALIGN(4);
-    } > ram_memory
-
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
+    __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
 
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
@@ -203,6 +215,10 @@ SECTIONS
         *(.sdata2.*)
 
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
 
@@ -236,12 +252,13 @@ SECTIONS
     .nocache_noinit_ram_region (NOLOAD) :
     {
         . = ALIGN(4);
-        __nocache_ram_data_start__ = .;
+        __nocache_noinit_ram_data_start__ = .;
 
         *(.nocache_noinit_ram)
+        *(.noncacheable)
 
         . = ALIGN(4);
-        __nocache_ram_data_end__ = .;
+        __nocache_noinit_ram_data_end__ = .;
     } > nocache_ram_memory
 
     .heap (NOLOAD):
@@ -260,5 +277,43 @@ SECTIONS
     __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
     ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
 
+    .psmram_data (NOLOAD):
+    {
+        . = ALIGN(4);
+        __psram_data_start__ = .;
+
+        /*__end__ = .;*/
+        /*end = __end__;*/
+        KEEP(*(.psram_data*))
+        KEEP(*(.img_buf*))
+
+        . = ALIGN(4);
+        __psram_data_end__ = .;
+    } > ram_code
+
+    .wifibss (NOLOAD) :
+    {
+      PROVIDE( __wifi_bss_start = ADDR(.wifibss) );
+      PROVIDE( __wifi_bss_end = ADDR(.wifibss) + SIZEOF(.wifibss) );
+      _sshram = . ;
+      *(SHAREDRAMIPC)
+      *(SHAREDRAM)
+      _eshram = . ;
+      *ipc_shared.o(COMMON)
+      *sdu_shared.o(COMMON)
+      *hal_desc.o(COMMON)
+      *txl_buffer_shared.o(COMMON)
+      *txl_frame_shared.o(COMMON)
+      *scan_shared.o(COMMON)
+      *scanu_shared.o(COMMON)
+      *mfp_bip.o(COMMON)
+      *me_mic.o(COMMON)
+      *(.wifi_ram*)
+      . = ALIGN(16);
+    } > ram_wifi
+
+    PROVIDE( _heap_wifi_start = . );
+    PROVIDE( _heap_wifi_size = ORIGIN(ram_wifi) + LENGTH(ram_wifi) - _heap_wifi_start );
+
 }
 
diff --git a/bsp/bouffalo_lab/bl61x/board/trap_gcc.S b/bsp/bouffalo_lab/bl61x/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/combine.sh b/bsp/bouffalo_lab/bl61x/combine.sh
new file mode 100755
index 0000000000..11a925dff0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/combine.sh
@@ -0,0 +1,39 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=./board/config
+TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl61x/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl61x/flash_prog_cfg.ini
new file mode 100755
index 0000000000..41aaca3979
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 2
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread.bin
+address = 0x000000
+
diff --git a/bsp/bouffalo_lab/bl61x/rtconfig.h b/bsp/bouffalo_lab/bl61x/rtconfig.h
new file mode 100644
index 0000000000..76ba4e227d
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/rtconfig.h
@@ -0,0 +1,244 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 512
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL61X
+#define BSP_USING_ROMAPI
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART0
+#define UART0_TX_USING_GPIO21
+#define UART0_RX_USING_GPIO22
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO16
+#define UART1_RX_USING_GPIO17
+
+#endif
diff --git a/bsp/bouffalo_lab/bl61x/rtconfig.py b/bsp/bouffalo_lab/bl61x/rtconfig.py
new file mode 100755
index 0000000000..1e198c0943
--- /dev/null
+++ b/bsp/bouffalo_lab/bl61x/rtconfig.py
@@ -0,0 +1,62 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='e9xx'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/Xuantie-900-gcc-elf-newlib-x86_64-V2.6.1/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl616_flash.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl616 ./rtthread.bin\n'
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl70x/.config b/bsp/bouffalo_lab/bl70x/.config
new file mode 100755
index 0000000000..65389f321a
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/.config
@@ -0,0 +1,1001 @@
+#
+# Automatically generated file; DO NOT EDIT.
+# RT-Thread Project Configuration
+#
+
+#
+# RT-Thread Kernel
+#
+CONFIG_RT_NAME_MAX=8
+# CONFIG_RT_USING_ARCH_DATA_TYPE is not set
+# CONFIG_RT_USING_SMP is not set
+CONFIG_RT_ALIGN_SIZE=8
+# CONFIG_RT_THREAD_PRIORITY_8 is not set
+CONFIG_RT_THREAD_PRIORITY_32=y
+# CONFIG_RT_THREAD_PRIORITY_256 is not set
+CONFIG_RT_THREAD_PRIORITY_MAX=32
+CONFIG_RT_TICK_PER_SECOND=1000
+CONFIG_RT_USING_OVERFLOW_CHECK=y
+CONFIG_RT_USING_HOOK=y
+CONFIG_RT_HOOK_USING_FUNC_PTR=y
+CONFIG_RT_USING_IDLE_HOOK=y
+CONFIG_RT_IDLE_HOOK_LIST_SIZE=4
+CONFIG_IDLE_THREAD_STACK_SIZE=1024
+CONFIG_RT_USING_TIMER_SOFT=y
+CONFIG_RT_TIMER_THREAD_PRIO=4
+CONFIG_RT_TIMER_THREAD_STACK_SIZE=512
+
+#
+# kservice optimization
+#
+CONFIG_RT_KSERVICE_USING_STDLIB=y
+# CONFIG_RT_KSERVICE_USING_STDLIB_MEMORY is not set
+# CONFIG_RT_KSERVICE_USING_TINY_SIZE is not set
+# CONFIG_RT_USING_TINY_FFS is not set
+# CONFIG_RT_KPRINTF_USING_LONGLONG is not set
+CONFIG_RT_DEBUG=y
+# CONFIG_RT_DEBUG_COLOR is not set
+# CONFIG_RT_DEBUG_INIT_CONFIG is not set
+# CONFIG_RT_DEBUG_THREAD_CONFIG is not set
+# CONFIG_RT_DEBUG_SCHEDULER_CONFIG is not set
+# CONFIG_RT_DEBUG_IPC_CONFIG is not set
+# CONFIG_RT_DEBUG_TIMER_CONFIG is not set
+# CONFIG_RT_DEBUG_IRQ_CONFIG is not set
+# CONFIG_RT_DEBUG_MEM_CONFIG is not set
+# CONFIG_RT_DEBUG_SLAB_CONFIG is not set
+# CONFIG_RT_DEBUG_MEMHEAP_CONFIG is not set
+# CONFIG_RT_DEBUG_MODULE_CONFIG is not set
+
+#
+# Inter-Thread communication
+#
+CONFIG_RT_USING_SEMAPHORE=y
+CONFIG_RT_USING_MUTEX=y
+CONFIG_RT_USING_EVENT=y
+CONFIG_RT_USING_MAILBOX=y
+CONFIG_RT_USING_MESSAGEQUEUE=y
+# CONFIG_RT_USING_SIGNALS is not set
+
+#
+# Memory Management
+#
+CONFIG_RT_PAGE_MAX_ORDER=11
+CONFIG_RT_USING_MEMPOOL=y
+CONFIG_RT_USING_SMALL_MEM=y
+# CONFIG_RT_USING_SLAB is not set
+# CONFIG_RT_USING_MEMHEAP is not set
+CONFIG_RT_USING_SMALL_MEM_AS_HEAP=y
+# CONFIG_RT_USING_MEMHEAP_AS_HEAP is not set
+# CONFIG_RT_USING_SLAB_AS_HEAP is not set
+# CONFIG_RT_USING_USERHEAP is not set
+# CONFIG_RT_USING_NOHEAP is not set
+# CONFIG_RT_USING_MEMTRACE is not set
+# CONFIG_RT_USING_HEAP_ISR is not set
+CONFIG_RT_USING_HEAP=y
+
+#
+# Kernel Device Object
+#
+CONFIG_RT_USING_DEVICE=y
+# CONFIG_RT_USING_DEVICE_OPS is not set
+# CONFIG_RT_USING_DM is not set
+# CONFIG_RT_USING_INTERRUPT_INFO is not set
+CONFIG_RT_USING_CONSOLE=y
+CONFIG_RT_CONSOLEBUF_SIZE=128
+CONFIG_RT_CONSOLE_DEVICE_NAME="uart0"
+CONFIG_RT_VER_NUM=0x50000
+# CONFIG_RT_USING_CACHE is not set
+# CONFIG_ARCH_ARM_BOOTWITH_FLUSH_CACHE is not set
+# CONFIG_ARCH_CPU_STACK_GROWS_UPWARD is not set
+# CONFIG_RT_USING_CPU_FFS is not set
+CONFIG_ARCH_RISCV=y
+CONFIG_ARCH_RISCV_FPU=y
+CONFIG_ARCH_RISCV_FPU_S=y
+CONFIG_ARCH_RISCV32=y
+
+#
+# RT-Thread Components
+#
+CONFIG_RT_USING_COMPONENTS_INIT=y
+CONFIG_RT_USING_USER_MAIN=y
+CONFIG_RT_MAIN_THREAD_STACK_SIZE=2048
+CONFIG_RT_MAIN_THREAD_PRIORITY=10
+# CONFIG_RT_USING_LEGACY is not set
+CONFIG_RT_USING_MSH=y
+CONFIG_RT_USING_FINSH=y
+CONFIG_FINSH_USING_MSH=y
+CONFIG_FINSH_THREAD_NAME="tshell"
+CONFIG_FINSH_THREAD_PRIORITY=20
+CONFIG_FINSH_THREAD_STACK_SIZE=4096
+CONFIG_FINSH_USING_HISTORY=y
+CONFIG_FINSH_HISTORY_LINES=5
+CONFIG_FINSH_USING_SYMTAB=y
+CONFIG_FINSH_CMD_SIZE=80
+CONFIG_MSH_USING_BUILT_IN_COMMANDS=y
+CONFIG_FINSH_USING_DESCRIPTION=y
+# CONFIG_FINSH_ECHO_DISABLE_DEFAULT is not set
+# CONFIG_FINSH_USING_AUTH is not set
+CONFIG_FINSH_ARG_MAX=10
+# CONFIG_RT_USING_DFS is not set
+# CONFIG_RT_USING_FAL is not set
+
+#
+# Device Drivers
+#
+CONFIG_RT_USING_DEVICE_IPC=y
+CONFIG_RT_UNAMED_PIPE_NUMBER=64
+# CONFIG_RT_USING_SYSTEM_WORKQUEUE is not set
+CONFIG_RT_USING_SERIAL=y
+CONFIG_RT_USING_SERIAL_V1=y
+# CONFIG_RT_USING_SERIAL_V2 is not set
+CONFIG_RT_SERIAL_USING_DMA=y
+CONFIG_RT_SERIAL_RB_BUFSZ=64
+# CONFIG_RT_USING_CAN is not set
+# CONFIG_RT_USING_HWTIMER is not set
+# CONFIG_RT_USING_CPUTIME is not set
+# CONFIG_RT_USING_I2C is not set
+# CONFIG_RT_USING_PHY is not set
+CONFIG_RT_USING_PIN=y
+# CONFIG_RT_USING_ADC is not set
+# CONFIG_RT_USING_DAC is not set
+# CONFIG_RT_USING_NULL is not set
+# CONFIG_RT_USING_ZERO is not set
+# CONFIG_RT_USING_RANDOM is not set
+# CONFIG_RT_USING_PWM is not set
+# CONFIG_RT_USING_MTD_NOR is not set
+# CONFIG_RT_USING_MTD_NAND is not set
+# CONFIG_RT_USING_PM is not set
+# CONFIG_RT_USING_FDT is not set
+# CONFIG_RT_USING_RTC is not set
+# CONFIG_RT_USING_SDIO is not set
+# CONFIG_RT_USING_SPI is not set
+# CONFIG_RT_USING_WDT is not set
+# CONFIG_RT_USING_AUDIO is not set
+# CONFIG_RT_USING_SENSOR is not set
+# CONFIG_RT_USING_TOUCH is not set
+# CONFIG_RT_USING_LCD is not set
+# CONFIG_RT_USING_HWCRYPTO is not set
+# CONFIG_RT_USING_PULSE_ENCODER is not set
+# CONFIG_RT_USING_INPUT_CAPTURE is not set
+# CONFIG_RT_USING_DEV_BUS is not set
+# CONFIG_RT_USING_WIFI is not set
+# CONFIG_RT_USING_VIRTIO is not set
+
+#
+# Using USB
+#
+# CONFIG_RT_USING_USB is not set
+# CONFIG_RT_USING_USB_HOST is not set
+# CONFIG_RT_USING_USB_DEVICE is not set
+
+#
+# C/C++ and POSIX layer
+#
+CONFIG_RT_LIBC_DEFAULT_TIMEZONE=8
+
+#
+# POSIX (Portable Operating System Interface) layer
+#
+# CONFIG_RT_USING_POSIX_FS is not set
+# CONFIG_RT_USING_POSIX_DELAY is not set
+# CONFIG_RT_USING_POSIX_CLOCK is not set
+# CONFIG_RT_USING_POSIX_TIMER is not set
+# CONFIG_RT_USING_PTHREADS is not set
+# CONFIG_RT_USING_MODULE is not set
+
+#
+# Interprocess Communication (IPC)
+#
+# CONFIG_RT_USING_POSIX_PIPE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_QUEUE is not set
+# CONFIG_RT_USING_POSIX_MESSAGE_SEMAPHORE is not set
+
+#
+# Socket is in the 'Network' category
+#
+# CONFIG_RT_USING_CPLUSPLUS is not set
+
+#
+# Network
+#
+# CONFIG_RT_USING_SAL is not set
+# CONFIG_RT_USING_NETDEV is not set
+# CONFIG_RT_USING_LWIP is not set
+# CONFIG_RT_USING_AT is not set
+
+#
+# Utilities
+#
+# CONFIG_RT_USING_RYM is not set
+# CONFIG_RT_USING_ULOG is not set
+# CONFIG_RT_USING_UTEST is not set
+# CONFIG_RT_USING_VAR_EXPORT is not set
+# CONFIG_RT_USING_ADT is not set
+# CONFIG_RT_USING_RT_LINK is not set
+# CONFIG_RT_USING_VBUS is not set
+
+#
+# RT-Thread Utestcases
+#
+# CONFIG_RT_USING_UTESTCASES is not set
+
+#
+# RT-Thread online packages
+#
+
+#
+# IoT - internet of things
+#
+# CONFIG_PKG_USING_LWIP is not set
+# CONFIG_PKG_USING_LORAWAN_DRIVER is not set
+# CONFIG_PKG_USING_PAHOMQTT is not set
+# CONFIG_PKG_USING_UMQTT is not set
+# CONFIG_PKG_USING_WEBCLIENT is not set
+# CONFIG_PKG_USING_WEBNET is not set
+# CONFIG_PKG_USING_MONGOOSE is not set
+# CONFIG_PKG_USING_MYMQTT is not set
+# CONFIG_PKG_USING_KAWAII_MQTT is not set
+# CONFIG_PKG_USING_BC28_MQTT is not set
+# CONFIG_PKG_USING_WEBTERMINAL is not set
+# CONFIG_PKG_USING_LIBMODBUS is not set
+# CONFIG_PKG_USING_FREEMODBUS is not set
+# CONFIG_PKG_USING_NANOPB is not set
+
+#
+# Wi-Fi
+#
+
+#
+# Marvell WiFi
+#
+# CONFIG_PKG_USING_WLANMARVELL is not set
+
+#
+# Wiced WiFi
+#
+# CONFIG_PKG_USING_WLAN_WICED is not set
+# CONFIG_PKG_USING_RW007 is not set
+# CONFIG_PKG_USING_COAP is not set
+# CONFIG_PKG_USING_NOPOLL is not set
+# CONFIG_PKG_USING_NETUTILS is not set
+# CONFIG_PKG_USING_CMUX is not set
+# CONFIG_PKG_USING_PPP_DEVICE is not set
+# CONFIG_PKG_USING_AT_DEVICE is not set
+# CONFIG_PKG_USING_ATSRV_SOCKET is not set
+# CONFIG_PKG_USING_WIZNET is not set
+# CONFIG_PKG_USING_ZB_COORDINATOR is not set
+
+#
+# IoT Cloud
+#
+# CONFIG_PKG_USING_ONENET is not set
+# CONFIG_PKG_USING_GAGENT_CLOUD is not set
+# CONFIG_PKG_USING_ALI_IOTKIT is not set
+# CONFIG_PKG_USING_AZURE is not set
+# CONFIG_PKG_USING_TENCENT_IOT_EXPLORER is not set
+# CONFIG_PKG_USING_JIOT-C-SDK is not set
+# CONFIG_PKG_USING_UCLOUD_IOT_SDK is not set
+# CONFIG_PKG_USING_JOYLINK is not set
+# CONFIG_PKG_USING_EZ_IOT_OS is not set
+# CONFIG_PKG_USING_IOTSHARP_SDK is not set
+# CONFIG_PKG_USING_NIMBLE is not set
+# CONFIG_PKG_USING_LLSYNC_SDK_ADAPTER is not set
+# CONFIG_PKG_USING_OTA_DOWNLOADER is not set
+# CONFIG_PKG_USING_IPMSG is not set
+# CONFIG_PKG_USING_LSSDP is not set
+# CONFIG_PKG_USING_AIRKISS_OPEN is not set
+# CONFIG_PKG_USING_LIBRWS is not set
+# CONFIG_PKG_USING_TCPSERVER is not set
+# CONFIG_PKG_USING_PROTOBUF_C is not set
+# CONFIG_PKG_USING_DLT645 is not set
+# CONFIG_PKG_USING_QXWZ is not set
+# CONFIG_PKG_USING_SMTP_CLIENT is not set
+# CONFIG_PKG_USING_ABUP_FOTA is not set
+# CONFIG_PKG_USING_LIBCURL2RTT is not set
+# CONFIG_PKG_USING_CAPNP is not set
+# CONFIG_PKG_USING_AGILE_TELNET is not set
+# CONFIG_PKG_USING_NMEALIB is not set
+# CONFIG_PKG_USING_PDULIB is not set
+# CONFIG_PKG_USING_BTSTACK is not set
+# CONFIG_PKG_USING_LORAWAN_ED_STACK is not set
+# CONFIG_PKG_USING_WAYZ_IOTKIT is not set
+# CONFIG_PKG_USING_MAVLINK is not set
+# CONFIG_PKG_USING_BSAL is not set
+# CONFIG_PKG_USING_AGILE_MODBUS is not set
+# CONFIG_PKG_USING_AGILE_FTP is not set
+# CONFIG_PKG_USING_EMBEDDEDPROTO is not set
+# CONFIG_PKG_USING_RT_LINK_HW is not set
+# CONFIG_PKG_USING_RYANMQTT is not set
+# CONFIG_PKG_USING_RYANW5500 is not set
+# CONFIG_PKG_USING_LORA_PKT_FWD is not set
+# CONFIG_PKG_USING_LORA_GW_DRIVER_LIB is not set
+# CONFIG_PKG_USING_LORA_PKT_SNIFFER is not set
+# CONFIG_PKG_USING_HM is not set
+# CONFIG_PKG_USING_SMALL_MODBUS is not set
+# CONFIG_PKG_USING_NET_SERVER is not set
+# CONFIG_PKG_USING_ZFTP is not set
+# CONFIG_PKG_USING_WOL is not set
+
+#
+# security packages
+#
+# CONFIG_PKG_USING_MBEDTLS is not set
+# CONFIG_PKG_USING_LIBSODIUM is not set
+# CONFIG_PKG_USING_LIBHYDROGEN is not set
+# CONFIG_PKG_USING_TINYCRYPT is not set
+# CONFIG_PKG_USING_TFM is not set
+# CONFIG_PKG_USING_YD_CRYPTO is not set
+
+#
+# language packages
+#
+
+#
+# JSON: JavaScript Object Notation, a lightweight data-interchange format
+#
+# CONFIG_PKG_USING_CJSON is not set
+# CONFIG_PKG_USING_LJSON is not set
+# CONFIG_PKG_USING_RT_CJSON_TOOLS is not set
+# CONFIG_PKG_USING_RAPIDJSON is not set
+# CONFIG_PKG_USING_JSMN is not set
+# CONFIG_PKG_USING_AGILE_JSMN is not set
+# CONFIG_PKG_USING_PARSON is not set
+
+#
+# XML: Extensible Markup Language
+#
+# CONFIG_PKG_USING_SIMPLE_XML is not set
+# CONFIG_PKG_USING_EZXML is not set
+# CONFIG_PKG_USING_LUATOS_SOC is not set
+# CONFIG_PKG_USING_LUA is not set
+# CONFIG_PKG_USING_JERRYSCRIPT is not set
+# CONFIG_PKG_USING_MICROPYTHON is not set
+# CONFIG_PKG_USING_PIKASCRIPT is not set
+# CONFIG_PKG_USING_RTT_RUST is not set
+
+#
+# multimedia packages
+#
+
+#
+# LVGL: powerful and easy-to-use embedded GUI library
+#
+# CONFIG_PKG_USING_LVGL is not set
+# CONFIG_PKG_USING_LITTLEVGL2RTT is not set
+# CONFIG_PKG_USING_LV_MUSIC_DEMO is not set
+# CONFIG_PKG_USING_GUI_GUIDER_DEMO is not set
+
+#
+# u8g2: a monochrome graphic library
+#
+# CONFIG_PKG_USING_U8G2_OFFICIAL is not set
+# CONFIG_PKG_USING_U8G2 is not set
+# CONFIG_PKG_USING_OPENMV is not set
+# CONFIG_PKG_USING_MUPDF is not set
+# CONFIG_PKG_USING_STEMWIN is not set
+# CONFIG_PKG_USING_WAVPLAYER is not set
+# CONFIG_PKG_USING_TJPGD is not set
+# CONFIG_PKG_USING_PDFGEN is not set
+# CONFIG_PKG_USING_HELIX is not set
+# CONFIG_PKG_USING_AZUREGUIX is not set
+# CONFIG_PKG_USING_TOUCHGFX2RTT is not set
+# CONFIG_PKG_USING_NUEMWIN is not set
+# CONFIG_PKG_USING_MP3PLAYER is not set
+# CONFIG_PKG_USING_TINYJPEG is not set
+# CONFIG_PKG_USING_UGUI is not set
+
+#
+# PainterEngine: A cross-platform graphics application framework written in C language
+#
+# CONFIG_PKG_USING_PAINTERENGINE is not set
+# CONFIG_PKG_USING_PAINTERENGINE_AUX is not set
+# CONFIG_PKG_USING_MCURSES is not set
+# CONFIG_PKG_USING_TERMBOX is not set
+# CONFIG_PKG_USING_VT100 is not set
+# CONFIG_PKG_USING_QRCODE is not set
+# CONFIG_PKG_USING_GUIENGINE is not set
+
+#
+# tools packages
+#
+# CONFIG_PKG_USING_CMBACKTRACE is not set
+# CONFIG_PKG_USING_EASYFLASH is not set
+# CONFIG_PKG_USING_EASYLOGGER is not set
+# CONFIG_PKG_USING_SYSTEMVIEW is not set
+# CONFIG_PKG_USING_SEGGER_RTT is not set
+# CONFIG_PKG_USING_RTT_AUTO_EXE_CMD is not set
+# CONFIG_PKG_USING_RDB is not set
+# CONFIG_PKG_USING_ULOG_EASYFLASH is not set
+# CONFIG_PKG_USING_LOGMGR is not set
+# CONFIG_PKG_USING_ADBD is not set
+# CONFIG_PKG_USING_COREMARK is not set
+# CONFIG_PKG_USING_DHRYSTONE is not set
+# CONFIG_PKG_USING_MEMORYPERF is not set
+# CONFIG_PKG_USING_NR_MICRO_SHELL is not set
+# CONFIG_PKG_USING_CHINESE_FONT_LIBRARY is not set
+# CONFIG_PKG_USING_LUNAR_CALENDAR is not set
+# CONFIG_PKG_USING_BS8116A is not set
+# CONFIG_PKG_USING_GPS_RMC is not set
+# CONFIG_PKG_USING_URLENCODE is not set
+# CONFIG_PKG_USING_UMCN is not set
+# CONFIG_PKG_USING_LWRB2RTT is not set
+# CONFIG_PKG_USING_CPU_USAGE is not set
+# CONFIG_PKG_USING_GBK2UTF8 is not set
+# CONFIG_PKG_USING_VCONSOLE is not set
+# CONFIG_PKG_USING_KDB is not set
+# CONFIG_PKG_USING_WAMR is not set
+# CONFIG_PKG_USING_MICRO_XRCE_DDS_CLIENT is not set
+# CONFIG_PKG_USING_LWLOG is not set
+# CONFIG_PKG_USING_ANV_TRACE is not set
+# CONFIG_PKG_USING_ANV_MEMLEAK is not set
+# CONFIG_PKG_USING_ANV_TESTSUIT is not set
+# CONFIG_PKG_USING_ANV_BENCH is not set
+# CONFIG_PKG_USING_DEVMEM is not set
+# CONFIG_PKG_USING_REGEX is not set
+# CONFIG_PKG_USING_MEM_SANDBOX is not set
+# CONFIG_PKG_USING_SOLAR_TERMS is not set
+# CONFIG_PKG_USING_GAN_ZHI is not set
+# CONFIG_PKG_USING_FDT is not set
+# CONFIG_PKG_USING_CBOX is not set
+# CONFIG_PKG_USING_SNOWFLAKE is not set
+# CONFIG_PKG_USING_HASH_MATCH is not set
+# CONFIG_PKG_USING_ARMV7M_DWT_TOOL is not set
+# CONFIG_PKG_USING_VOFA_PLUS is not set
+
+#
+# system packages
+#
+
+#
+# enhanced kernel services
+#
+# CONFIG_PKG_USING_RT_MEMCPY_CM is not set
+# CONFIG_PKG_USING_RT_KPRINTF_THREADSAFE is not set
+# CONFIG_PKG_USING_RT_VSNPRINTF_FULL is not set
+
+#
+# acceleration: Assembly language or algorithmic acceleration packages
+#
+# CONFIG_PKG_USING_QFPLIB_M0_FULL is not set
+# CONFIG_PKG_USING_QFPLIB_M0_TINY is not set
+# CONFIG_PKG_USING_QFPLIB_M3 is not set
+
+#
+# CMSIS: ARM Cortex-M Microcontroller Software Interface Standard
+#
+# CONFIG_PKG_USING_CMSIS_5 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS1 is not set
+# CONFIG_PKG_USING_CMSIS_RTOS2 is not set
+
+#
+# Micrium: Micrium software products porting for RT-Thread
+#
+# CONFIG_PKG_USING_UCOSIII_WRAPPER is not set
+# CONFIG_PKG_USING_UCOSII_WRAPPER is not set
+# CONFIG_PKG_USING_UC_CRC is not set
+# CONFIG_PKG_USING_UC_CLK is not set
+# CONFIG_PKG_USING_UC_COMMON is not set
+# CONFIG_PKG_USING_UC_MODBUS is not set
+# CONFIG_PKG_USING_FREERTOS_WRAPPER is not set
+# CONFIG_PKG_USING_CAIRO is not set
+# CONFIG_PKG_USING_PIXMAN is not set
+# CONFIG_PKG_USING_PARTITION is not set
+# CONFIG_PKG_USING_PERF_COUNTER is not set
+# CONFIG_PKG_USING_FLASHDB is not set
+# CONFIG_PKG_USING_SQLITE is not set
+# CONFIG_PKG_USING_RTI is not set
+# CONFIG_PKG_USING_DFS_YAFFS is not set
+# CONFIG_PKG_USING_LITTLEFS is not set
+# CONFIG_PKG_USING_DFS_JFFS2 is not set
+# CONFIG_PKG_USING_DFS_UFFS is not set
+# CONFIG_PKG_USING_LWEXT4 is not set
+# CONFIG_PKG_USING_THREAD_POOL is not set
+# CONFIG_PKG_USING_ROBOTS is not set
+# CONFIG_PKG_USING_EV is not set
+# CONFIG_PKG_USING_SYSWATCH is not set
+# CONFIG_PKG_USING_SYS_LOAD_MONITOR is not set
+# CONFIG_PKG_USING_PLCCORE is not set
+# CONFIG_PKG_USING_RAMDISK is not set
+# CONFIG_PKG_USING_MININI is not set
+# CONFIG_PKG_USING_QBOOT is not set
+# CONFIG_PKG_USING_PPOOL is not set
+# CONFIG_PKG_USING_OPENAMP is not set
+# CONFIG_PKG_USING_LPM is not set
+# CONFIG_PKG_USING_TLSF is not set
+# CONFIG_PKG_USING_EVENT_RECORDER is not set
+# CONFIG_PKG_USING_ARM_2D is not set
+# CONFIG_PKG_USING_MCUBOOT is not set
+# CONFIG_PKG_USING_TINYUSB is not set
+# CONFIG_PKG_USING_CHERRYUSB is not set
+# CONFIG_PKG_USING_KMULTI_RTIMER is not set
+# CONFIG_PKG_USING_TFDB is not set
+# CONFIG_PKG_USING_QPC is not set
+# CONFIG_PKG_USING_AGILE_UPGRADE is not set
+# CONFIG_PKG_USING_FLASH_BLOB is not set
+
+#
+# peripheral libraries and drivers
+#
+
+#
+# sensors drivers
+#
+# CONFIG_PKG_USING_LSM6DSM is not set
+# CONFIG_PKG_USING_LSM6DSL is not set
+# CONFIG_PKG_USING_LPS22HB is not set
+# CONFIG_PKG_USING_HTS221 is not set
+# CONFIG_PKG_USING_LSM303AGR is not set
+# CONFIG_PKG_USING_BME280 is not set
+# CONFIG_PKG_USING_BME680 is not set
+# CONFIG_PKG_USING_BMA400 is not set
+# CONFIG_PKG_USING_BMI160_BMX160 is not set
+# CONFIG_PKG_USING_SPL0601 is not set
+# CONFIG_PKG_USING_MS5805 is not set
+# CONFIG_PKG_USING_DA270 is not set
+# CONFIG_PKG_USING_DF220 is not set
+# CONFIG_PKG_USING_HSHCAL001 is not set
+# CONFIG_PKG_USING_BH1750 is not set
+# CONFIG_PKG_USING_MPU6XXX is not set
+# CONFIG_PKG_USING_AHT10 is not set
+# CONFIG_PKG_USING_AP3216C is not set
+# CONFIG_PKG_USING_TSL4531 is not set
+# CONFIG_PKG_USING_DS18B20 is not set
+# CONFIG_PKG_USING_DHT11 is not set
+# CONFIG_PKG_USING_DHTXX is not set
+# CONFIG_PKG_USING_GY271 is not set
+# CONFIG_PKG_USING_GP2Y10 is not set
+# CONFIG_PKG_USING_SGP30 is not set
+# CONFIG_PKG_USING_HDC1000 is not set
+# CONFIG_PKG_USING_BMP180 is not set
+# CONFIG_PKG_USING_BMP280 is not set
+# CONFIG_PKG_USING_SHTC1 is not set
+# CONFIG_PKG_USING_BMI088 is not set
+# CONFIG_PKG_USING_HMC5883 is not set
+# CONFIG_PKG_USING_MAX6675 is not set
+# CONFIG_PKG_USING_TMP1075 is not set
+# CONFIG_PKG_USING_SR04 is not set
+# CONFIG_PKG_USING_CCS811 is not set
+# CONFIG_PKG_USING_PMSXX is not set
+# CONFIG_PKG_USING_RT3020 is not set
+# CONFIG_PKG_USING_MLX90632 is not set
+# CONFIG_PKG_USING_MLX90393 is not set
+# CONFIG_PKG_USING_MLX90392 is not set
+# CONFIG_PKG_USING_MLX90397 is not set
+# CONFIG_PKG_USING_MS5611 is not set
+# CONFIG_PKG_USING_MAX31865 is not set
+# CONFIG_PKG_USING_VL53L0X is not set
+# CONFIG_PKG_USING_INA260 is not set
+# CONFIG_PKG_USING_MAX30102 is not set
+# CONFIG_PKG_USING_INA226 is not set
+# CONFIG_PKG_USING_LIS2DH12 is not set
+# CONFIG_PKG_USING_HS300X is not set
+# CONFIG_PKG_USING_ZMOD4410 is not set
+# CONFIG_PKG_USING_ISL29035 is not set
+# CONFIG_PKG_USING_MMC3680KJ is not set
+# CONFIG_PKG_USING_QMP6989 is not set
+# CONFIG_PKG_USING_BALANCE is not set
+# CONFIG_PKG_USING_SHT2X is not set
+# CONFIG_PKG_USING_SHT3X is not set
+# CONFIG_PKG_USING_AD7746 is not set
+# CONFIG_PKG_USING_ADT74XX is not set
+# CONFIG_PKG_USING_MAX17048 is not set
+# CONFIG_PKG_USING_AS7341 is not set
+# CONFIG_PKG_USING_CW2015 is not set
+# CONFIG_PKG_USING_ICM20608 is not set
+# CONFIG_PKG_USING_PAJ7620 is not set
+# CONFIG_PKG_USING_STHS34PF80 is not set
+
+#
+# touch drivers
+#
+# CONFIG_PKG_USING_GT9147 is not set
+# CONFIG_PKG_USING_GT1151 is not set
+# CONFIG_PKG_USING_GT917S is not set
+# CONFIG_PKG_USING_GT911 is not set
+# CONFIG_PKG_USING_FT6206 is not set
+# CONFIG_PKG_USING_FT5426 is not set
+# CONFIG_PKG_USING_FT6236 is not set
+# CONFIG_PKG_USING_XPT2046_TOUCH is not set
+# CONFIG_PKG_USING_REALTEK_AMEBA is not set
+# CONFIG_PKG_USING_STM32_SDIO is not set
+# CONFIG_PKG_USING_ESP_IDF is not set
+# CONFIG_PKG_USING_BUTTON is not set
+# CONFIG_PKG_USING_PCF8574 is not set
+# CONFIG_PKG_USING_SX12XX is not set
+# CONFIG_PKG_USING_SIGNAL_LED is not set
+# CONFIG_PKG_USING_LEDBLINK is not set
+# CONFIG_PKG_USING_LITTLED is not set
+# CONFIG_PKG_USING_LKDGUI is not set
+# CONFIG_PKG_USING_NRF5X_SDK is not set
+# CONFIG_PKG_USING_NRFX is not set
+# CONFIG_PKG_USING_WM_LIBRARIES is not set
+
+#
+# Kendryte SDK
+#
+# CONFIG_PKG_USING_K210_SDK is not set
+# CONFIG_PKG_USING_KENDRYTE_SDK is not set
+# CONFIG_PKG_USING_INFRARED is not set
+# CONFIG_PKG_USING_MULTI_INFRARED is not set
+# CONFIG_PKG_USING_AGILE_BUTTON is not set
+# CONFIG_PKG_USING_AGILE_LED is not set
+# CONFIG_PKG_USING_AT24CXX is not set
+# CONFIG_PKG_USING_MOTIONDRIVER2RTT is not set
+# CONFIG_PKG_USING_PCA9685 is not set
+# CONFIG_PKG_USING_I2C_TOOLS is not set
+# CONFIG_PKG_USING_NRF24L01 is not set
+# CONFIG_PKG_USING_RPLIDAR is not set
+# CONFIG_PKG_USING_AS608 is not set
+# CONFIG_PKG_USING_RC522 is not set
+# CONFIG_PKG_USING_WS2812B is not set
+# CONFIG_PKG_USING_EMBARC_BSP is not set
+# CONFIG_PKG_USING_EXTERN_RTC_DRIVERS is not set
+# CONFIG_PKG_USING_MULTI_RTIMER is not set
+# CONFIG_PKG_USING_MAX7219 is not set
+# CONFIG_PKG_USING_BEEP is not set
+# CONFIG_PKG_USING_EASYBLINK is not set
+# CONFIG_PKG_USING_PMS_SERIES is not set
+# CONFIG_PKG_USING_NUCLEI_SDK is not set
+# CONFIG_PKG_USING_CAN_YMODEM is not set
+# CONFIG_PKG_USING_LORA_RADIO_DRIVER is not set
+# CONFIG_PKG_USING_QLED is not set
+# CONFIG_PKG_USING_AGILE_CONSOLE is not set
+# CONFIG_PKG_USING_LD3320 is not set
+# CONFIG_PKG_USING_WK2124 is not set
+# CONFIG_PKG_USING_LY68L6400 is not set
+# CONFIG_PKG_USING_DM9051 is not set
+# CONFIG_PKG_USING_SSD1306 is not set
+# CONFIG_PKG_USING_QKEY is not set
+# CONFIG_PKG_USING_RS485 is not set
+# CONFIG_PKG_USING_RS232 is not set
+# CONFIG_PKG_USING_NES is not set
+# CONFIG_PKG_USING_VIRTUAL_SENSOR is not set
+# CONFIG_PKG_USING_VDEVICE is not set
+# CONFIG_PKG_USING_SGM706 is not set
+# CONFIG_PKG_USING_STM32WB55_SDK is not set
+# CONFIG_PKG_USING_RDA58XX is not set
+# CONFIG_PKG_USING_LIBNFC is not set
+# CONFIG_PKG_USING_MFOC is not set
+# CONFIG_PKG_USING_TMC51XX is not set
+# CONFIG_PKG_USING_TCA9534 is not set
+# CONFIG_PKG_USING_KOBUKI is not set
+# CONFIG_PKG_USING_ROSSERIAL is not set
+# CONFIG_PKG_USING_MICRO_ROS is not set
+# CONFIG_PKG_USING_MCP23008 is not set
+# CONFIG_PKG_USING_BLUETRUM_SDK is not set
+# CONFIG_PKG_USING_MISAKA_AT24CXX is not set
+# CONFIG_PKG_USING_MISAKA_RGB_BLING is not set
+# CONFIG_PKG_USING_LORA_MODEM_DRIVER is not set
+# CONFIG_PKG_USING_BL_MCU_SDK is not set
+# CONFIG_PKG_USING_SOFT_SERIAL is not set
+# CONFIG_PKG_USING_MB85RS16 is not set
+# CONFIG_PKG_USING_RFM300 is not set
+# CONFIG_PKG_USING_IO_INPUT_FILTER is not set
+# CONFIG_PKG_USING_RASPBERRYPI_PICO_SDK is not set
+# CONFIG_PKG_USING_LRF_NV7LIDAR is not set
+# CONFIG_PKG_USING_FINGERPRINT is not set
+
+#
+# AI packages
+#
+# CONFIG_PKG_USING_LIBANN is not set
+# CONFIG_PKG_USING_NNOM is not set
+# CONFIG_PKG_USING_ONNX_BACKEND is not set
+# CONFIG_PKG_USING_ONNX_PARSER is not set
+# CONFIG_PKG_USING_TENSORFLOWLITEMICRO is not set
+# CONFIG_PKG_USING_ELAPACK is not set
+# CONFIG_PKG_USING_ULAPACK is not set
+# CONFIG_PKG_USING_QUEST is not set
+# CONFIG_PKG_USING_NAXOS is not set
+
+#
+# Signal Processing and Control Algorithm Packages
+#
+# CONFIG_PKG_USING_FIRE_PID_CURVE is not set
+# CONFIG_PKG_USING_UKAL is not set
+
+#
+# miscellaneous packages
+#
+
+#
+# project laboratory
+#
+
+#
+# samples: kernel and components samples
+#
+# CONFIG_PKG_USING_KERNEL_SAMPLES is not set
+# CONFIG_PKG_USING_FILESYSTEM_SAMPLES is not set
+# CONFIG_PKG_USING_NETWORK_SAMPLES is not set
+# CONFIG_PKG_USING_PERIPHERAL_SAMPLES is not set
+
+#
+# entertainment: terminal games and other interesting software packages
+#
+# CONFIG_PKG_USING_CMATRIX is not set
+# CONFIG_PKG_USING_SL is not set
+# CONFIG_PKG_USING_CAL is not set
+# CONFIG_PKG_USING_ACLOCK is not set
+# CONFIG_PKG_USING_THREES is not set
+# CONFIG_PKG_USING_2048 is not set
+# CONFIG_PKG_USING_SNAKE is not set
+# CONFIG_PKG_USING_TETRIS is not set
+# CONFIG_PKG_USING_DONUT is not set
+# CONFIG_PKG_USING_COWSAY is not set
+# CONFIG_PKG_USING_LIBCSV is not set
+# CONFIG_PKG_USING_OPTPARSE is not set
+# CONFIG_PKG_USING_FASTLZ is not set
+# CONFIG_PKG_USING_MINILZO is not set
+# CONFIG_PKG_USING_QUICKLZ is not set
+# CONFIG_PKG_USING_LZMA is not set
+# CONFIG_PKG_USING_MULTIBUTTON is not set
+# CONFIG_PKG_USING_FLEXIBLE_BUTTON is not set
+# CONFIG_PKG_USING_CANFESTIVAL is not set
+# CONFIG_PKG_USING_ZLIB is not set
+# CONFIG_PKG_USING_MINIZIP is not set
+# CONFIG_PKG_USING_HEATSHRINK is not set
+# CONFIG_PKG_USING_DSTR is not set
+# CONFIG_PKG_USING_TINYFRAME is not set
+# CONFIG_PKG_USING_KENDRYTE_DEMO is not set
+# CONFIG_PKG_USING_DIGITALCTRL is not set
+# CONFIG_PKG_USING_UPACKER is not set
+# CONFIG_PKG_USING_UPARAM is not set
+# CONFIG_PKG_USING_HELLO is not set
+# CONFIG_PKG_USING_VI is not set
+# CONFIG_PKG_USING_KI is not set
+# CONFIG_PKG_USING_ARMv7M_DWT is not set
+# CONFIG_PKG_USING_CRCLIB is not set
+# CONFIG_PKG_USING_LWGPS is not set
+# CONFIG_PKG_USING_STATE_MACHINE is not set
+# CONFIG_PKG_USING_DESIGN_PATTERN is not set
+# CONFIG_PKG_USING_CONTROLLER is not set
+# CONFIG_PKG_USING_PHASE_LOCKED_LOOP is not set
+# CONFIG_PKG_USING_MFBD is not set
+# CONFIG_PKG_USING_SLCAN2RTT is not set
+# CONFIG_PKG_USING_SOEM is not set
+# CONFIG_PKG_USING_QPARAM is not set
+# CONFIG_PKG_USING_CorevMCU_CLI is not set
+
+#
+# Arduino libraries
+#
+# CONFIG_PKG_USING_RTDUINO is not set
+
+#
+# Projects
+#
+# CONFIG_PKG_USING_ARDUINO_ULTRASOUND_RADAR is not set
+# CONFIG_PKG_USING_ARDUINO_SENSOR_KIT is not set
+# CONFIG_PKG_USING_ARDUINO_MATLAB_SUPPORT is not set
+
+#
+# Sensors
+#
+# CONFIG_PKG_USING_ARDUINO_SENSOR_DEVICE_DRIVERS is not set
+# CONFIG_PKG_USING_ARDUINO_CAPACITIVESENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL375 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L0X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL53L1X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSOR is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VL6180X is not set
+# CONFIG_PKG_USING_ADAFRUIT_MAX31855 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31865 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX31856 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX6675 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90614 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS1 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AHTX0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM9DS0 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADT7410 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME680 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9808 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4728 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA219 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR390 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM6DS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO055 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MAX1704X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMC56X3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90393 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90395 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ICM20X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DPS310 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTS221 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT4X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADXL343 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS726X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AMG88XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2320 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AM2315 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LTR329_LTR303 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP085_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP183_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BMP3XX is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MS8607 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MLX90640 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MMA8451 is not set
+# CONFIG_PKG_USING_ADAFRUIT_MSA301 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BNO08X_RVC is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS2MDL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303DLH_MAG is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LC709203F is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CAP1188 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_CCS811 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_NAU7802 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS331 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS2X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LPS35HW is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LSM303_ACCEL is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_LIS3DH is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8591 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPL3115A2 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPR121 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPRLS is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MPU6050 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCT2075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PM25AQI is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_EMC2101 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXAS21002C is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SCD30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_FXOS8700 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HMC5883_UNIFIED is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP30 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP006 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TLA202X is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCS34725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI7021 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SGP40 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SHTC3 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU21DF is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AS7341 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_HTU31D is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SENSORLAB is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_INA260 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP007_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_L3GD20 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TMP117 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSC2007 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TSL2591_LIBRARY is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VCNL4040 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML6075 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_VEML7700 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LIS3DHTR is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DHT is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL335 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_ADXL345 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BME280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP280 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_H3LIS331DL is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MMA7660 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TSL2561 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PAJ7620 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VL53L0X is not set
+# CONFIG_PKG_USING_SEEED_ITG3200 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT31 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HP20X is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_DRV2605L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BBM150 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HMC5883L is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM303DLH is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_TCS3414CS is not set
+# CONFIG_PKG_USING_SEEED_MP503 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_BMP085 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HIGHTEMP is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_VEML6070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SI1145 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_SHT35 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_AT42QT1070 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LSM6DS3 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HDC1000 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_HM3301 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_MCP9600 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LTC2941 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_LDC1612 is not set
+
+#
+# Display
+#
+# CONFIG_PKG_USING_ARDUINO_U8G2 is not set
+# CONFIG_PKG_USING_ARDUINO_U8GLIB_ARDUINO is not set
+# CONFIG_PKG_USING_SEEED_TM1637 is not set
+
+#
+# Timing
+#
+# CONFIG_PKG_USING_ARDUINO_MSTIMER2 is not set
+
+#
+# Data Processing
+#
+# CONFIG_PKG_USING_ARDUINO_KALMANFILTER is not set
+# CONFIG_PKG_USING_ARDUINO_ARDUINOJSON is not set
+
+#
+# Data Storage
+#
+
+#
+# Communication
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PN532 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI4713 is not set
+
+#
+# Device Control
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCF8574 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_PCA9685 is not set
+# CONFIG_PKG_USING_ARDUINO_SEEED_PCF85063TP is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TPA2016 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DRV2605 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS1841 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_DS3502 is not set
+
+#
+# Other
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MFRC630 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_SI5351 is not set
+# CONFIG_PKG_USING_ARDUINO_RTCLIB is not set
+
+#
+# Signal IO
+#
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BUSIO is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_TCA8418 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP23017 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_ADS1X15 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_AW9523 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP3008 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_MCP4725 is not set
+# CONFIG_PKG_USING_ARDUINO_ADAFRUIT_BD3491FS is not set
+
+#
+# Uncategorized
+#
+CONFIG_BSP_USING_BL70X=y
+CONFIG_BSP_USING_ROMAPI=y
+# CONFIG_BSP_USING_PSRAM is not set
+
+#
+# General Drivers Configuration
+#
+CONFIG_BSP_USING_GPIO=y
+
+#
+# General Purpose UARTs
+#
+CONFIG_BSP_USING_UART0=y
+CONFIG_UART0_TX_USING_GPIO14=y
+# CONFIG_UART0_TX_USING_GPIO16 is not set
+# CONFIG_UART0_TX_USING_GPIO21 is not set
+# CONFIG_UART0_RX_USING_GPIO7 is not set
+# CONFIG_UART0_RX_USING_GPIO15 is not set
+# CONFIG_UART0_RX_USING_GPIO22 is not set
+CONFIG_UART0_RX_USING_GPIO23=y
+CONFIG_BSP_USING_UART1=y
+# CONFIG_UART1_TX_USING_GPIO4 is not set
+# CONFIG_UART1_TX_USING_GPIO16 is not set
+# CONFIG_UART1_TX_USING_GPIO18 is not set
+CONFIG_UART1_TX_USING_GPIO26=y
+# CONFIG_UART1_RX_USING_GPIO3 is not set
+# CONFIG_UART1_RX_USING_GPIO5 is not set
+# CONFIG_UART1_RX_USING_GPIO17 is not set
+# CONFIG_UART1_RX_USING_GPIO19 is not set
+CONFIG_UART1_RX_USING_GPIO27=y
diff --git a/bsp/bouffalo_lab/bl70x/Kconfig b/bsp/bouffalo_lab/bl70x/Kconfig
new file mode 100755
index 0000000000..c6ee6e58f8
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/Kconfig
@@ -0,0 +1,26 @@
+mainmenu "RT-Thread Project Configuration"
+
+config BSP_DIR
+    string
+    option env="BSP_ROOT"
+    default "."
+
+config RTT_DIR
+    string
+    option env="RTT_ROOT"
+    default "../../.."
+
+config PKGS_DIR
+    string
+    option env="PKGS_ROOT"
+    default "packages"
+
+config LIBRARIES_DIR
+    string
+    option env="LIBRARIES_DIR"
+    default "../libraries"
+
+source "$RTT_DIR/Kconfig"
+source "$PKGS_DIR/Kconfig"
+source "board/Kconfig"
+source "$LIBRARIES_DIR/Kconfig"
diff --git a/bsp/bouffalo_lab/bl70x/SConscript b/bsp/bouffalo_lab/bl70x/SConscript
new file mode 100755
index 0000000000..c7ef7659ec
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/SConscript
@@ -0,0 +1,14 @@
+# for module compiling
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/bl70x/SConstruct b/bsp/bouffalo_lab/bl70x/SConstruct
new file mode 100755
index 0000000000..da9ba9a91a
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/SConstruct
@@ -0,0 +1,46 @@
+import os
+import sys
+import rtconfig
+
+from rtconfig import RTT_ROOT
+
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread.' + rtconfig.TARGET_EXT
+
+DefaultEnvironment(tools=[])
+env = Environment(tools = ['mingw'],
+    AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+    CC = rtconfig.CC, CFLAGS = rtconfig.CFLAGS,
+    CXX = rtconfig.CXX, CXXFLAGS = rtconfig.CXXFLAGS,
+    AR = rtconfig.AR, ARFLAGS = '-rc',
+    LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+env['ASCOM'] = env['ASPPCOM']
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+SDK_ROOT = os.path.abspath('./')
+
+if os.path.exists(SDK_ROOT + '/libraries'):
+    libraries_path_prefix = SDK_ROOT + '/libraries'
+else:
+    libraries_path_prefix = os.path.dirname(SDK_ROOT) + '/libraries'
+
+SDK_LIB = libraries_path_prefix
+Export('SDK_LIB')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT, has_libcpu = False)
+
+# include libraries
+objs.extend(SConscript(libraries_path_prefix + '/bl_mcu_sdk/SConscript', variant_dir='build/libraries/bl_mcu_sdk', duplicate=0))
+
+# include drivers
+objs.extend(SConscript(libraries_path_prefix + '/rt_drivers/SConscript', variant_dir='build/libraries/rt_drivers', duplicate=0))
+
+
+# make a building
+DoBuilding(TARGET, objs)
diff --git a/bsp/bouffalo_lab/bl70x/applications/SConscript b/bsp/bouffalo_lab/bl70x/applications/SConscript
new file mode 100755
index 0000000000..c583d3016e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/applications/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bl808/m0/applications/main.c b/bsp/bouffalo_lab/bl70x/applications/main.c
similarity index 88%
rename from bsp/bl808/m0/applications/main.c
rename to bsp/bouffalo_lab/bl70x/applications/main.c
index 46101be0ad..6897456dde 100644
--- a/bsp/bl808/m0/applications/main.c
+++ b/bsp/bouffalo_lab/bl70x/applications/main.c
@@ -13,7 +13,7 @@
 
 int main(void)
 {
-    rt_kprintf("Hello, world\n");
+    rt_kprintf("Hello, RISC-V!\n");
 
     return 0;
 }
diff --git a/bsp/bouffalo_lab/bl70x/board/Kconfig b/bsp/bouffalo_lab/bl70x/board/Kconfig
new file mode 100755
index 0000000000..9bc940982c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/Kconfig
@@ -0,0 +1,16 @@
+config BSP_USING_BL70X
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BSP_USING_ROMAPI
+    default y
+
+config BSP_USING_ROMAPI
+    bool 
+    default y
+
+config BSP_USING_PSRAM
+    bool "Enable PSRAM"
+    default n
diff --git a/bsp/bouffalo_lab/bl70x/board/SConscript b/bsp/bouffalo_lab/bl70x/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl70x/board/board.c b/bsp/bouffalo_lab/bl70x/board/board.c
new file mode 100644
index 0000000000..0d2c02fe0c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/board.c
@@ -0,0 +1,197 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/25     flyingcys    first version
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+static void system_clock_init(void)
+{
+    GLB_Set_System_CLK(GLB_DLL_XTAL_32M, GLB_SYS_CLK_DLL144M);
+    GLB_Set_MTimer_CLK(1, GLB_MTIMER_CLK_BCLK, 71);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+    PERIPHERAL_CLOCK_IR_ENABLE();
+    PERIPHERAL_CLOCK_I2S_ENABLE();
+    PERIPHERAL_CLOCK_USB_ENABLE();
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_CAM);
+
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_96M, 0);
+    GLB_Set_SPI_CLK(ENABLE, 0);
+    GLB_Set_I2C_CLK(ENABLE, 0);
+    GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 15);
+
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DAC_CLK(ENABLE, GLB_DAC_CLK_XCLK, 0x3E);
+
+    GLB_Set_USB_CLK(ENABLE);
+}
+
+#ifdef BSP_USING_PSRAM
+struct spi_psram_cfg_type ap_memory1604 = {
+    .read_id_cmd = 0x9F,
+    .read_id_dmy_clk = 0,
+    .burst_toggle_cmd = 0xC0,
+    .reset_enable_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .enter_quad_mode_cmd = 0x35,
+    .exit_quad_mode_cmd = 0xF5,
+    .read_reg_cmd = 0xB5,
+    .read_reg_dmy_clk = 1,
+    .write_reg_cmd = 0xB1,
+    .read_cmd = 0x03,
+    .read_dmy_clk = 0,
+    .f_read_cmd = 0x0B,
+    .f_read_dmy_clk = 1,
+    .f_read_quad_cmd = 0xEB,
+    .f_read_quad_dmy_clk = 3,
+    .write_cmd = 0x02,
+    .quad_write_cmd = 0x38,
+    .page_size = 512,
+    .ctrl_mode = PSRAM_SPI_CTRL_MODE,
+    .drive_strength = PSRAM_DRIVE_STRENGTH_50_OHMS,
+    .burst_length = PSRAM_BURST_LENGTH_512_BYTES,
+};
+
+struct sf_ctrl_cmds_cfg cmds_cfg = {
+    .cmds_core_en = 1,
+    .cmds_en = 1,
+    .burst_toggle_en = 1,
+    .cmds_wrap_mode = 0,
+    .cmds_wrap_len = SF_CTRL_WRAP_LEN_512,
+};
+struct sf_ctrl_psram_cfg psram_cfg = {
+    .owner = SF_CTRL_OWNER_SAHB,
+    .pad_sel = SF_CTRL_SEL_DUAL_CS_SF2,
+    .bank_sel = SF_CTRL_SEL_PSRAM,
+    .psram_rx_clk_invert_src = 1,
+    .psram_rx_clk_invert_sel = 0,
+    .psram_delay_src = 1,
+    .psram_clk_delay = 1,
+};
+
+#define BFLB_EXTFLASH_CS_GPIO    GLB_GPIO_PIN_25
+#define BFLB_EXTPSRAM_CLK_GPIO   GLB_GPIO_PIN_27
+#define BFLB_EXTPSRAM_CS_GPIO    GLB_GPIO_PIN_17
+#define BFLB_EXTPSRAM_DATA0_GPIO GLB_GPIO_PIN_28
+#define BFLB_EXTPSRAM_DATA1_GPIO GLB_GPIO_PIN_24
+#define BFLB_EXTPSRAM_DATA2_GPIO GLB_GPIO_PIN_23
+#define BFLB_EXTPSRAM_DATA3_GPIO GLB_GPIO_PIN_26
+
+void ATTR_TCM_SECTION psram_gpio_init(void)
+{
+    GLB_GPIO_Cfg_Type cfg;
+    uint8_t gpiopins[7];
+    uint8_t i = 0;
+
+    cfg.gpioMode = GPIO_MODE_AF;
+    cfg.pullType = GPIO_PULL_UP;
+    cfg.drive = 3;
+    cfg.smtCtrl = 1;
+    cfg.gpioFun = GPIO_FUN_FLASH_PSRAM;
+
+    gpiopins[0] = BFLB_EXTPSRAM_CLK_GPIO;
+    gpiopins[1] = BFLB_EXTPSRAM_CS_GPIO;
+    gpiopins[2] = BFLB_EXTPSRAM_DATA0_GPIO;
+    gpiopins[3] = BFLB_EXTPSRAM_DATA1_GPIO;
+    gpiopins[4] = BFLB_EXTPSRAM_DATA2_GPIO;
+    gpiopins[5] = BFLB_EXTPSRAM_DATA3_GPIO;
+    gpiopins[6] = BFLB_EXTFLASH_CS_GPIO;
+
+    for (i = 0; i < sizeof(gpiopins); i++) {
+        cfg.gpioPin = gpiopins[i];
+
+        if (i == 0 || i == 1 || i == 6) {
+            /*flash clk and cs is output*/
+            cfg.gpioMode = GPIO_MODE_OUTPUT;
+        } else {
+            /*data are bidir*/
+            cfg.gpioMode = GPIO_MODE_AF;
+        }
+
+        GLB_GPIO_Init(&cfg);
+    }
+}
+
+uint8_t psramId[8] = { 0 };
+
+void ATTR_TCM_SECTION board_psram_init(void)
+{
+    psram_gpio_init();
+
+    bflb_psram_init(&ap_memory1604, &cmds_cfg, &psram_cfg);
+
+    bflb_psram_softwarereset(&ap_memory1604, ap_memory1604.ctrl_mode);
+
+    bflb_psram_readid(&ap_memory1604, psramId);
+    bflb_psram_cache_write_set(&ap_memory1604, SF_CTRL_QIO_MODE, ENABLE, DISABLE, DISABLE);
+    L1C_Cache_Enable_Set(L1C_WAY_DISABLE_NONE);
+}
+#endif
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(HW_MTIMER_CLOCK / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef BSP_USING_PSRAM
+    board_psram_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl70x/board/board.h b/bsp/bouffalo_lab/bl70x/board/board.h
new file mode 100644
index 0000000000..4d337e73d6
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/board.h
@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/03/15     flyingcys    first version
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bflb_spi_psram.h"
+#include "bl702_glb.h"
+
+#define     HW_MTIMER_CLOCK     1000000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_debug_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..6434eb89571d739eb32868b8fece64f80531a2fa
GIT binary patch
literal 43216
zcmeFadsq|K);PQ;$z&3|01gQDV2wmjIV~blX?rZ4V3Gm6lv)(D*op&QPHVm2&a0s(wpO8<)*eehZc?jg6|k>uu@R_kHE6l075S~5Nd)_z_kEt<_k7Ry
z&!>ID%&fil+H0-7_S$Q&eQAtgS^|L(GE6eCzK9^^=l4kWAlnUD45#4sU~$XKyd7LgZ&kgzdknDA31TCr_Lh
zIWK|eY0a2hwU?)PQ-~8Sol29;usjAs?W-@8&RMp%qSij`2Xobd^66J+emA@E_4;|2
z=3o4KU6Cc+5^3Uixz7nco}W->xWiGr6V;>>O-CAXsktdf(g~hONzDZKZ
z!?T$>M@Q>@v25j7CyI!{WsT2N5E#a9q4P!}p*jFzOu>1^|ExyRzrwGGC0fj{o4@0M
zI*k+6MPKA!=iQuAM7;hQ`4-*3Kf`hF_rv&t&9%Hx-POZyQ4{SbD1kmc1o2c*oiiaJ
zyvVfZhFCv85$b<|*9|Yt)W`GAgovjz^}cSJ`OzJx+`0bxeCa5KGoj#Vo^?FkamP)2
zILLbfu4fvQY#PAp97^&xF^!A>e#fa{ON=^HhB9^O9!ybCpJws#64Mkdw_+Fi$s}yn
zCL8yAp-}T|UX+^sI&sF0<#{Jch&W>t(>>gxhaL*azg5~oKREC~==-B>Zc1O&+oWtL
z()!Zl{SnP}^^m}S3ksYruOg|yi_V0lPZQsWdG!p?AEr&;;9tyWiH#YAzPXephy%2o
zk!0#e1**e+lhw~;Cac48lGUSz&r*kuouwY3ouv+bWtLi%I!hhCED6$+AU#PvsxV0%
zdMs(`a9W;0X6iTjNXpf)iAZu*at@x7jptH_OKK#wpk*P>gt>3gd>OPvM3_sDCxb@6
zBHdq>0Ly3#ms9fm+_$M-(CpTf}n#9Y~}^|MHD!dH@qrLhYB*6fu+L;}TBhNe@sbpuYaT
z27&aNK1w0gjYX1+l1q|$Nu%0}kciZw=f*et8lc5J)Q%qj`7MxNOmB*m>c=7huuG?A
z5+&qu>BJ#l<#K4iz;TL*z;)4KrWrSRR(;@hGC396H?S`*G}gj$KJES8@=7{f3bgRG
zk8m>)vo09fOyWw9hWrTdMg-!TqjQ}J=*_V=cj%RAG(Y*(y}3?ge`l~>Ynb8_oGVhr
zd~0O25|S0NsBWRF%iHmGS9`1vw9Qyr-qBOYI$EmR1@aY%hl`BRDLyngWrh=}{(~%~
z$;mUFDB~YPZJ4)-LoyARuZTcm>Q}k9$Ay_fN;3@+foI??)8-f~`x!u0y5nV{*0a_BoEhjagOQ6Hmszds#THC_Ke@fPwWeGSnb84M9f
zJNYwMri_WAg!x&(-{L>l8C_n|`VmpsN*Xrvu|Rzj8D_%yVbmZiXX`_ZEP)D7V+igg
z{G4?mF78MsWa1EzizFhD*L{_nKEctCtRH@eaAV0Jcs9)BAiC=vn`JJ0j`8W=$b1&}
zMBKB{K>Szb2ji4$L~44CCUvRgv%S5uKyj@!ljZz65ux9hp`kjE(LfPIz4qrGVIYzSYeyk2OVOX3
zDVJ&Fc1BRtNj6)Fmk&?kK3wgk`DeXEGqYau)Q8e(0}<)Xd+)QJ@7ZwY#X};#Nu0h^
zSR05iCdU@VeRxVY*yw-8B0+If!VMmXguqcqxT}!N=oI8gszw(O`SL%^+^an(+Dxwv
zBz&!0phCj&3dFtIgf;|(ZPG}a5e@iCk
zV%m(hVri;QBFG~o0*Rz!3%CzQ67<4YG|g;e2O~i_7&N!_A-zyR
zblbSxHITLmU52*?1Te{sQZCm9Z-J<+lm?r(-@vuB$Ov}7;jsSs0u5!8@XF{snxeXm
z)k;L0scuJS)kA5O5()AqNp}+GQ!h7G4?!UY0caO^s+(JM!Yh;AuOB^)JS4~qBpZ?(
z`3(=G2Ngg|D9TYdrc)0zR1gBvrth-IlDe8l{TUB!4T+R)wAISYyB@^TzRqy(zp#;fE>Q&roJt2Uk
zv4o{SKbA7*MLo^6v&25s4BsJW*>M`EuGuh=s6aixNsk#q8T
zpkkZc5mSk$lr)A%KB;3y%HCerxcQt=AtZUec();u?94^d$1$E
z?x8?+^#BFXOTRKt$mJ$AA(GW(wK60{n*l$_2XpPwz^}|N~5vd6#jVIq|TBY+%5yO=>_#vZ8Zo1=P%Px&~B2
z9c46G6aimCgQSGI3|2(Lw}MP68LsMt1Zsj@8Yo?q_x`4iFG|P`#NE{s8bzne#;P+&
z;O7GLZ=e9JCP?`eTlY-PA8T+R8qQ)#l^L*XZXOr=Q>Ck=r+xuCCMz>cJ=HyA&apzn
z;^Q%Lt@+CFecoOVHyi_>^k3?*+cD}<*J7jx!T${RWx(%b)WOGM)FaAb)S(w*)Xxx;
z06vNQI?OD{wK34c7=?m1X=hES>WCI7#Dtl-_JfF)1Dxrv$cw-;q=L~#Rhd>gB2!D~
zp%&f740Taq^2Q7s|M^WiOZ!tM9-Sj;68W6S8g8H)0}#KZglc1MS~m33#^YA(0qmMYk}qzpv;}FS!02+f
zTP1#Rd#RwZ6g|CZFiO^{N0G#dJYzM5f+2TGS)kU~02pT4U>xg|Bx<=XxsqG}y*y*6
z)jw;H{A8Y5MH0Sp^|lUFoNHm%Ul=}(U&ynzfrt<`DKh-DW=dm(R=Qm;4UF3>_bW@(
z(~1C;;Hv554kPsBV0rP5#4_n9FiJ^MND*d!j!Mie5^jCHmtR?l`DZ5AJRwi*<3NrZ
z)qkvgMMG6Bb~fl0|6)%M!~lB{t04(k@9b6<8J+m!jV*$8}=f
zzy|`}zH--RYzRS#S~}@-q@lVb-0c=gVA6yn0lVdv?c3d^k3Q{51b0RyrD(5
ziQPVVr`EESThV|{n*FUi%V@T>X4|lScSW?e*w4lanJdfI#5%@~b48k|~to&SPZG6qNs_7Lo%fn3Ex-PW-
zm7MB`IDyp5Q_1X?_%zy5@rg}|GH5TIJUCz2EXxqi-0SI|5SSRmaGlL4Fg7uk>uQl;
zeStb|w~hmSv8OP8v2LU1OyOZ
zcjrdtX{ZK?V3ysQke6==&f~5f@DeqZ9@ysX$AG3vyIh*8hy_ixC+Y-+KT2TKqx^`X
zUQM+dN6CichgmL{p4`DLpD8hh%ZOmP
zk3B(0Tb~A6)uXNxt9M8Z(BH_g9SL^n7#Wh*gS^6Zh@MdjR<%-Mrnt5v5`|sE*E0Tm
z*baKy!yfgvDpYc}hH!NE+;AFn0dO3x|q1)xZwEr;z{t!M0;_WNwkahLWb=H;Nht`
zrF2&S8gCHl1CWy9(mK5azOzRYU;}G+k9n?!9;lmhGLMKQ_1NB$F9$Lj^Fbt+F9!{1
zkb<5PZeEOmE?&}*p)W6L;3Wz77#&#n5|_=DlU#Qr>cfvu3wX(nw9oH9TdI+M%aoWK
z8RHlkDbfmbs=#T5JemM+;-7gW`CQGJ(&uV~tP?#^Bq9PCZs|dZk6WSwIT)zuUlZAf
z20tc&c`laU=)YB%(WwP1U?-`YTZ?yu=Ox;otLYB-zGn~xd`eAk@`fnjk)M_m3+*M>
zD85D9(rRgcPiujVOkfl>;V#_4@hGKrfAi@#JTa
zu;cxJKltOm*&1^t13iL-UI;eZ*Q&7NbWPqv^p8AV{#?zK(h}ZZ)a1sQAgRIH{-Q2}
z?qO@k-M%c@OZK<-k4?n7yvZL%8$aTR%W6z;X*0GO(#C3)05+q9mrD~F?*0i`$tEwY
z(3s5hw;Oho^?vN`=q$
zXWwfLo)`<%lk00j4v9Ra=wJkO@gyUTct%kBu~L`jnq8V(k4HKgk!uAT4U`r3p{$k<
z=ACWc_nNAGdp&h1_#&fbL0%3I`{8n5w$V2QhhXL9oT_&Pk33o{)t6}?aQ`&&j)
z{#8bL*aUF{nJmXJ#4uDpJT^Dhq8~7coHqIpr)(I;cOa*frs5?Dp8T4A^_HQ75yK6a5l2@&<-$uSS}z1|$vfx)pe7qHf4FE}x2~sRD`8
zYO!8o#M~O?6^8qLBoS?Smx(t|%RQ0nY$|<#%S_b8=W;_jB58S>RJk=%KMhib-8GK%
zx>cK(QlkzXM}QoWt9`mTIr+3S)azFN*vNct?iWu_)MZ;IR&e(#Ck)uCR@L4*mkV*`
zreSTDKjxIx3NF3H%i$Z)v6B(Z0qBxl^sHzK4dmu^Jq1|hFgKBmOXmLG845FrfCiZT
zKi3G+XnCPwZ6ep&89MP&j^Sh;_iN{1o-N61Mco1GFX1r}%F5JX@OuV+;WC*(=_tU<
zsJFEu3+32-|6zAhkUf_Ts>o+yoPaq=yKJJ)m*rM>4GPqOOomaan*kFmcH@2_OF!xeE;Y_fh0#>o04}`?W?kH#RvGZ?qaJ)+
zhH(?WZi~I7Ym6=4;cN9fn|ujm;;KhILM8$JB~X$A&rU(-QG`uC46U-RwUfa6b->cr
zk6YU%$z}J+WwL!BjbmQ|M%lWCq58g&f{X500ge(#*-Ns;zYk&eiRG1!Rb3bVZ(0Sn
zNKnP)FO)1qMDMD7(#Ymxk8`U=pUJTAxSjzo-hQJ`>RJYS=OoNL*4wjPt+xtNY0$4a
zw|=S7CD~qTV#O<8^x}L@=P5O@!pQo`uGxgFsBSt7Vj2*aeXjBNm){4F6nw}bMlj9OK6D>`4jcLX7QMkWD0
z0nfEUTGHQ1fyPhfjKz(Q>5uLA5TD0om
z5hOQQ=`~U35U8KmCpflIKc_H`-BgQ5mqEs|4PQO$A6xUuv8ynSS2N)|>g;Nj*R5T;
zM&^P+V{T=*hgFj8Okm9?0f`mkbOJw<;L^ZbrW#O64erC|?G73FQ(){>W}HqV?_wM`
ztD5qyC-Np%G};@PUAhZ~e5>Qv&O6f4CRrbQ!JowT;tR}gm=o)#vh-@KW9yomxQxTU
zt5^#50w`bFRea?*slQU9^$jgAG7U|KXzQKeig>%cD%=9=P2ORq0cGlexe|3)h?Hl!
z_u3_}riCH~D$XjKfj+d&o6r?A!F;gpJ)I;D$Hy$JV`uwA^)nDrdxn%;wh7cy3HP&2
zuJskV{1KlSTp_QrP@j+`5PLGRmD2uK!c4orPM+nf=hAGFDVLNi^g2mU3U}KkQNZfR
zQl%mp)?X;aS>guR56J*M)ThHW4NZqNf?%*NAZN9_T^6<-`syu0Uuhcx^Ci5-DX+pc
zK*YUTF%{PLWSCC8GPMNx$c(H%SauTarRG?TYzWN6#-noTigg}2CwpT?iWbkc#CaB;
zam_5BZ4WbrZ;rH_u;jF6vP5i9r8<-(=zeX|Y>1WJN5*&x=@^I?tM0+d8{KiA%7jRD
zQ+SFlQ1^{B&YDsozFYc-~JWK0a!Z$DzX9dG}wQ!ck4E|$OCz4kcI~B(J=r-K7t%kdCNShL+=2&b1DCx5yN3;eO9T(I#UE#QAucSFrg+
z?h8NdySF3OyChZ$1&?A<6#}F;mU}@c=f1p#Qw=cCe!_8qz%@z
zU`B@g*`Wptth;fWTL*J*cRj^zYzT)jO2TcTMmToZ9^#(B$-74E0-J@c4aA1S1S$Ys
zwFlOyQ5vzT6uf<*brARfA+q=bd{E7<*pwRRk$+re0%Ltr-i^(-CZ|O22(w_x$Htz_
zdyat_uFR4ho>wx#hUc!MbP}JdDOaDfue5V--c@n_cVX7ZwN$IX(l{DaI1U?>$lYpv
z8Z0=>T)<~QS9Ly9@CdV~NpTh+zW1IEO6Z;mGtKP{h*NYSzZ7mqXHZHCP!<%F2q}pX
z%tFSMDufx%Tx?*}i;&Td5mWM`s0qrgfnc
zdFv~3*yo_7VI@2zA%*UWLL5zn{Jgy~
zqS)m}Ym&MUy{5~X3u+ixNTt{ve{?(mO#rQt!KyySH1rg=DJhD(abLo{w?Hav(IGxw
zIeEM8UFLOjFn{>@Fbg+eM#us1N1MmaIOKT0x@lapPb_i7k-O#^hK|;RRN_@JCB)tI
z^J(%UFK5%sKWLi;FP#@*$k)#V-hMn2W}!)$SN8-i@UVO)|NVru$rF=>!L5YFc-g8n
za=Q=8xW7~ylD&8c*D_=5kZVMo{~>a!8hu0zfx6CuC6z&4
z)&?$!3?~d0Jx!*;_psBrE|XW>1WtBXGBnP}ULv?XR5$ppl7slkta|P!K>bQgRNCBR5$vD!a47|ka
zVXcgD^fb3&Z&E{nwRq-|LaL{{Xv#<82yDJXXN?5db;Vw+3to;rC)yl}mRs2rrU@cP
zkQ4VjXWOt{VHQUa`I~fPg%acDT3RJ83w(7V_9Q`V+ju{yR>ms~z9I{YPY0%bswiUfCw;vLdZnes#)w46dc;<`c|+OD{U
z_mDJ|?!o2NqdtO_up}++uNo=|BBtYjmQ$r*$H3RdZSQP*Rg9tb=a2
zGbz6**6$mbi$a0#G3{#ANAbQlg85t(p}PYf369C&u@p=DDlwa4GcI0BkqyHWOV^CTmA7dh}H{P#O&>pqz5u*X|fI=ZcR0Uy(F`Co}Q2^
z#$q>SBx+Z!84$25W;1!u`hE7h<)Xh4ZVD}jajm~jo2d`xukZ4S
zc!6q@3isQk+=D!sh@rqIY|D`?bbm&UDdV?XaZ2H7G|0S!HC=z?mkSFhm=92d(2$0-
z#&Sv>{5)|5B1`v>&46&M3T5fv>axDL?ohI#fui3;Lj8sGA
zGGdN&twZQ|=;;2n^IoaDJfWd@S1OURn4>j(J~U1|Lxt-mL2-vAgr2Ef;vH7MVCHPKZIjD-6JKB~nVY5{uzJq*^%
zp@-euWtYr)FA=Yr<2f)$jk<9>=TxGWUjUKZwi9_fCk-$R*uo92MoLzFq-Ef)Nn#%k
zg?*7nOh$b!VzmBxr_a%}(QFCTEZM~PF{I(%`y~wrCAm~dL#rg2@w2b{Alcp>fOQ?W
z@fB-Og|TWS3SyEOF1yN0Y2d6?Ufgy$I`zSe9~i3=@%+^a9*;FgzE^(PI>UNzwP5ai
zr^9NjN<&8gVyxPZ=+1^7%jW!Yx@9ElcBT8+S6P$oDN_U(VWQ-j88<&jIh&%}FgS{O
z2i^N1r6P#2k?5UbMrdVGko{`RhONfxk3j40S*6vVq4#w2sKwSR)(h6F<-1~Te;~A0
zqh00QNhx)K;FHk{0#Kk`XbnIqcG3F=+a#qIP}0m&ptc*R?FI+|5aPws6z%p&jg#)Z
zzwU$WryEb>dD5j<>8{le^ULT~Gtu}hhHQHE>Z^F4fMHo8ODR!*-=yvqH`%?
zUAA@stTwi7u$CETWkU_#(O^|=c|;7f3koWO{Z8brGTdT_EtgY{Z|UAz?LHRpI|U1=3@
zlg`zl;M~5mE<8%`GOg0FTh~p%tm`N0pNbOTcsk4mzp)lWs{})zR;xP3!HO(NMg(a=
z9;%=+cy@LD7zDKT)-695W^(t#ukgG|v{14L@T`3DonngpU%hrFM6^UbHy-p-gy~7q
z4rlrK>H;c4UCUid1zF>`
zca^AydH$t&x*DbzU-PLyk(Ibx=VT`;aUIrcl6J7(?3=7-{~*Y^ufKw<|%gLBrX)=i(Qq$$wiWQUJSfk|VdFYb`
zcgN8)VZR!$7+0Ldt*C}LJGRAIBfY8`??CZ~eG0#{f_0#Gj6@T5_{8wkwz8YHzF(C#
z!dIX=d&K@EKR3ZLtqNPE{e~AzMJ9sfe(6L}3xE=eT5X0nrnG@VFeiL7OEO(vOlr3R
zj}-cR&Q^%Exw))i1Pe8;V?qscCR$isf$8|56LHtFB#*bM^Z-O#U}t)Kp3iBXx?O5~
z^z8@VW#ID$pM{uAl2#I0TW-QD{;;ea
z4l{dGeU@bMd-2n=&Y6Sbi{nDg@jUKXd@PyzNeSUQy+RsKKtC{;u>Rwy7Va0)$(fP~
zmXnsf=IL3Pv7xnKKTY?dAICT?tJYi`7ZW$#9LfjBU({iY!@tDsNt-ff7nv0djwls_
z&C6tmvjbrFue|En@d~EaEPnI)u`eoI8Y782V17?0LM?g-w1E#5dib=VxQ7}I|!oJ~e3g$caSD{`HU-j;<{rahp
z^P>Cfu>KWDJLmrTL_Z7CJTxBD?}xMl?zC_8pFmo0VsV0J|D70B|H&LYMWp_MUZ0v@
z;(Ie{HSDKe1^cPt2m4E`5NpVTNUHG7afsmzgB{iLAswO+ct0$puYvRpkiM?chHahv
z+}InoHApRFvAd(~wzZHCei#x3KO5lgi(l9jyN6c99)#TcX^Pz^m<@%1^8>({4>)sY
zym*Ikjc9mQ{?Lur_`l$F(*<~Wz?%(tw*X!X;LQTOnSl2l!22KR&`*NT;#Pu|uFckk
z+9l)dr*a7Tu!vKh-$j>?3_8f*(cgk)^`2te1^)QD&)C{k`xn+%+7>`9JN2m$~tr!ugN%!Z98T;K{-H3wq(F0GD;rs
z7k(V_R{|W@J8V}k+~S5;;{5OT!ZBYsKZf_EKO5j@0KOmR&+E;P>BsOhIRB1b_!&3c
zg})E|I6tP}B~PI@Kb8-cvy0!HUO1)`^M&EVw)Mg>ek>m>hdo;#hd;uf-wVg|W4KHH
zTNDh>Mwf@$aogjXJtcbFJ{8uzq04G(>dU{go6qe%d!Y7Q)y0a}f0%c5{&#H*w%V5r}oh9ub5jWoT;K5q=a)($BY0qW_1F`=R**Yx0T*!(0POe@85_PtH+5x2j?&&$Z-S9E(3I^x!
z$Q+l!t?}u@UO3iP3_lF;F}D?rSc3;sz8jO(Db|n=xy3#x*6e*tgkvnbUD!pq^*0fY
zTN>v-<;LUvs|d$^Di`3#Jos;jaLgITNsABx`#OKjXvMW%-7ZH3~?vo
zLgRPD%O~G?ZC=X7l$bfib3&kxIpp`wlFG$j+<4%~V*ktWKJ@^4`GKh=4k7+pw$7t1
zxE-)oVBI`_{)}t97Efxxsf^{~T-VvQ7##USWG>#^ut{%iuKD
zAUL5#({co!^O4P)l$m2r!sLoAt!?bj)5e>bEq|o)Z!MxV;_dWSoFaF
zLm}39Xdkg}yEyus3rLr4m;rlkY1ng18-W7pXo5D5E*m5b%N%43(+-mUl^A6FYnks@
zkePxR&YpAO&t#o#&c?pDygzgFPya(&DMKJf@!K*ZXnVw^~t4b6H=PHe#4J
zj4U3UyA8fBJNM~ln5XSZ+;0I3*hEi@;1bTt|BmI;5B@urmyf!z3=y%s40U6!#Tu+%
zVF}y*1N@qQAT?OlHn9%DJoyvR##>80koZqUE5GC`Jm!ct6psQgpLk3&4!iZ`Uynim
zQ?%@#o)pXCK8QyQYca0>U8S?FCl^!crx0s(Lap!>DCY8ZeQk#{Jc5jY`b91D(D?Fk
z55z;`7?50F8ofW>t`qZ!)Qu_jv^H-0F-JUKxb0ttmi%|EKE{6O5e}F9AzvT;0Z&W(
z!Z^I)%Y#F-Pom~Hzx)&bd&N@j_TKN3#t_hW-qmKnKbEjJcv&C~&;u+pOf7stdtzz0
zsC8=`&btIWCXZg?+)Kby!jixe$N86lhG6M=ByBBpf4gOE1wF*+9%)K^Pq-yRb<$+4^DL=J_|iV^x#Cu}U7#>D>n
zOd=RZwrDC#A(-WwZNur*!?IF*hThhKn5%{;is;!8aL?-6
z5np%3dbJAXuFTyxV3vNnd$9I{yFWs$ik*{IS$Ces5jGkkYyi=#RTP3V2}8Rcx}hY@
z<`M9^yA{tcn7glGJjMgSVbVcj_m=Je>>rT^Zeb@%H4fM!w0254ziNnn${$4GeP1KG
z6x~S>SLu&quCPwx<60+~E=D7>>^d
z^2JX38;;*c__!bkFr>t3f9a>+Ln2%dDES$DU!zyHzf{O_5WoI}<(_IsIkFYo{KoZ;
zbVPyHS5o!+NY%LLsz^Poc*r0U@e=GALLl>C0b-CRA!1BapPi&7Bw2WDT(wMIJ-G6z
z(@&Qb{cz-J@pmU0Pu72Rsr+J9-JNrtXYbcOtl8LNzP|aVtxba-4u0^|{ipASb%wV`
z-kH$$!ma4vVtz6Fyu4-g^?&^I&!$x06(Oo|zlZpY3o8$|W8QOL!fm!uKS;k~oBy~K
zJ|W|V6DOIXn5QOfp0s*K%Z!;bt7c9}I*>Ft*_^z3TFbPVFIT-hVeWysgHz3^%a{MO
zeEN#=6_Km>tz1u2_YKR0_!#UX72fJbn3{5c-z(sL^^|h=8V52Ngimz~=sI-Y8FS(zaAm@#|H@zx;r3wWM6O|n=fTy85`^rDCU?1E=m$Dro>n6|5vb{qLE
z+y|83Cy&xacydVHvcwu*M;i;R4uzazkJ8VF)u~njEF~pJ6dS9uZ
z^`e-w(0Jid3xK5d$IGCE>auOOEBz|ly=6|RQorAY_bOZFlHCj&Y$ITTUd2>dzE-@3
zdB!q>{cCMK-(tMdk614_0qzCXO^S2nw}M}DiIiz(@RG7qup8jNJbZT8aDF3b{cVs%
zPBl=P-wK}YOIJKOh7`cp1y3#)1=Ii=^v?zi+r(-!!6L#+r2nI~$1VHGah!T}66UxA
z(}^kg7ULA*ST6UBH%|4oIMhm{bhtf|eBRlH%T
z;(|U8;ZXtYyTeAZt~Ei|I;Lk$P))#kA*^GT{fu*8gVXfx`~`PdA}&*>hLz1i<39MC
zA6G(cN770P@iH+_!Tzv($BuD5#-wXRN%cqqG*x=oDNu>fS4SXe6@}NbVfV5cRiJ$t
z4TzLE26w@zF79NAnN{rCxd3#sxNd>8%QSmEwnZqBF-ec6!8!}g?#5ERU*Ci_ljA%VI+c^H!`lH
z>@8}LgcwW4(Ux4c*bMSRLrEMx4>!XN2L2&nVFIK?&jKX1Zp;Wb6E{epwag7W4J&h)
zBHUwxba)nc>Vu$)ARV*-f9-=gTYV~?4Gz@7Dn60l1S|RvF_lr!&Oz1h=?I9}igxPK
zWY`7n4rLW`L>i4zZi!=$Et&JC+ak6LcV@{&Fdt6o9t@`kOYKhZ{!9
zz|V`P@m}$5U}afm*l?=xbW{>ve`p=Fvs!!`>E8%%aMK4x4cPg$_|_WG2yZxF^y`;wU7tnQ*hU6}
z*E%vdy4JD)KlAmm3VFRc=r;1`~NLClC-B$2x|!
z-Q6#z7BiymtXqa-;jb7VvOHoT63@{)kN$YemK2C+Q)U9DAjoc`6bc?j%U7TV6Rb@;
zkCy&s)Q^C*;LL;^Qp8#CH*wFqSeq>g{&!KnxU~FSbcM6&{7yQ6N3d?K5CXE0P2K~V
zP&Oa@?6y_eXRN8PS`XTjam6|c73!niRAx-L161PHp0fEZA>HOc&D4RpPxz
zkrv-HXWdJuFjdaFJ*U8{^uC9D-Mkk>`|9xxM>|}19N`;{4)DH)A`9G+akR7v-_4-|
z9Rhj%DBVxYg8i>`d%nbP0#D2xE_2qsQyOgWZ@~~BI6p_sb=LK?+mciWb0v_BWFhiU
z+VodKKdW?*o?BBP35FdqqC`~laoN4*X=btXOZ9u%Olx$-d+gr4=<*phPrd?fuL0-u
z+{+WSoMtc#jr!l(~hcP>q`6T3KQlFbF7!@
zqx4f|(d2Q)>5~yP+D%QFj+}gwVaD%(#((25_NDJ&9ND(ZV
ziN4jsnojW5RKp8@O<@F+HmMO#eL&vf+}tkNCODzv*2k(8W*eLpsm+Vukz(Iw2VbeF
zRf6q?^xzr9yG|@%31OcxAI@X6qp+&{m#_{;>curC+-q{!?_s>??KyLYc)0BgMS=eg
zS}?d5idW{eDN@!C_JxDR=?{Bt$+^RwZSUN|PtVA+58;Sc>94z8^pNa6{#qiT|HdY*
zekBF#16Zg*T{4JV-+GuCKD?GY41N=>X*z|+AbAzP1x^5*m$H{(Uu~sVuxmel
zvsbz6+2QpQ?81nu{^SRm>bk}4YK1cciQwU?R5@FApZD+pBd}Mny9YEKh4U_Whprpb
zbvLGV7bZvM!3RKr>WU4o*WvzHSq(b`j}F_NdPB=V#PBYKFD3T57mN84VRwuzbc=qv1ML
z?s~RUKgln^I4d>yDZoEbh^ZqKV(K^rPThWfNVPhHMBg8$$p}>?{9UTL0X{aCvp}JK
zw9H4v`F2XedGPFh4l@n8fm_mO2!NK>&rO-P09j8r=+Mp)%T$Ey)K7?$HCJp0vxZHPB$4aDHRu^@s4|kC_c4|wUL%F
zKA7v$e|_(=f^f!VxofqSBo~5JKB+!Xm}1L%8l*(UMwe%^`@jc)ok!qF@C(YQDX?)i{0T%8H;hbTwiN*_|S8W(D4{^i706_{XGotkF=6hCn#aGF!@jl|L@;5HR%XE-50Y@!{rDkB?Ux`X3V6X#
zkmDZMBU%gXwFY>CH<70d*iq{|`c4hO_WJBE@OZy5o^Oggp!pu@WAA6qvIFI{c6_5D
z9_gq3fbTU_7s%mOAGp>GZOY&o{95}NGyHDI&t)sypQx^0;K#Y00y}-tMJVN=s({$VkPBYOhdV*+lC%1{
zc?RV(=8)c8XO_gZhk>lD8+!=G4A^6t
z?n>cV$Mvj-?zC@!-j9K*I%g5S>u+=cejigr^znQ=w>!G-bi}(NNd5U6Hf{Q1|J$X*
z_4q8VxXT%z#>FRZXV*yMLeY`UktSitXhg@|>!H`dokD)2QE`6p_Bx$${}~jv*l1ula;Kdg%_X1R5++s8$3Wj%OoyBFI$^?*hEp~y6#xtJB}NjV#o
zAlBo$0}}ZR)OHu^MO-hvuPt?BX#|Uxf2!0L^^auin>M@?T_I2fr2HJ7d-$G#`z^sj
zjX93*Rut_9zB3V@f0|YwZZaMwWue~*B$5@Gg8BGH`47`CMY?<7+!${AVTH?glp|TN
z+us{w!w@ge*9H8Az05JWuADB9a!kG}isXM!VyyN<*}sato#u&)U~xVkTP9Mj{|@+v
zlUjCFZx0HdjeC$|+sK|rWxl&@b94G%kbg5x9#z3@Qecg+y*H6!Pg9M@5P^h~t-Og6
zVNDuBKgWjkAl&q>Ry=<_?Hr6zK7y=H#rrDsd!>w}+dghe;x|yiAX!
z?6D4WpW%ic26}a}S77XN9zFk2BV(f^aP#IptL0ZL%?k#P)X(q1o`@t4YI2R2Zi)N=
z^1LU=wyC~>F(tGXk8kpGf~l-dT4jP8p)!+UCDx^Dd=v1~2|i~s^v1zm$XIQHdXAk>
zVKQ~uTaJD0rrZJe+C}a%0yFht7B4s(;=NCxOk{KgO_{vmjS}Rh0mBU-6T*v+u7a~2
zA3;pP-KP9?=g}o?K+$mQ(Z>M2;u#4MCqtKzAzHC6vIRK4d80I03$r!gI{1>j9%kLT
z++V{?eKpMcKXFaCb%BwSZ93WtVdFnznH6P?fAyoBU>WhJy1UF2k{PCeE;m*
z=c4k780XQKe}a3np2epPEIWQdrapSR)86x6kNTv&=SP8xQ)g6PokV9V`w3og>g+97-0fcJ1bQ!v
z*csX1-Pq?I!VnT>$AG_W*r}<_A`g{qU{5ak8s37La-28J*2VeO{zwDvTf|hZxmtot
z`pRkE;tew}F@2vD!=RM-jqXQI?Tf#(a&)s`IpaNTxA9;+ItEct{G?%5^XOJ}h8H?^
z$X)wwka#UF`HI0qseL#8cGGz#_41>3=mveR1}`e(4@BtrQ&FI2_pJF}yK{b%+Ktoh
zBT|=hN_xPHz~%6oPvsquM}_edFM?c54;a933r|9X982Mi%gZiIwUt<=YPnZmB!02r
zdZ)oTLAQSAN)Kq0vCPkj_R;>v^=aFuyVXJL%sp$$RU@mDW>>>}M4IaeO!3i)d}Tt5@OMEUzL=6CVy*lG
z==~yO6nG>}!?0h{^wQ7DW|5|*G2nBa$D`;vID_r6Jq6#viP)k-IE38SUtz8QKXZy1
zxIdE-F_S$I3qJa?t7PHmV#a1Wbxg?0`v=^>2IGlX8hieDXC`eT=49TqwMt^ZhqVXU
zvBmQ2*F9qD&oo~NvtX=ncA4a{eTCKLT0Ye5)`u(onFG1~?KfkTP}OSH8O@l
zJXZ9O#G5AZX|V9k#hYIlKE5K%;;-jSUNS*Bj>y!(nJI}eDGhPg+aaz<9-78$wycyM
z8_hi(B8@j+#P>-T{CH$&vq1I(Yt2aZ=7O*3>iKiOg!x#XJ0`_FuGl-`WpFo&WUc=k%#XQlO$XD^th)eq9pHOARD4
zR>6I9SuETxTJMGH4tLumdr7h0Me~k43G5@&bIv?D4KmX3A4zb&c(-(zV>lO_tf%3u
zvF;eejlkoo5UEGS#>6y)B^z5&V)_hjCph5Y>!|Ty=A6)cwdyd;9dyJr9^w)ZA0KkV
zc#wD<@Q3ULsfaM&vc9)xh`eV4-(v5>>&~`nBvF4%J;W>OIBKrc>k^zzpMD)>@J6&;
zK0-6I681Wg`VE8Oq^&@}xpSBeH1$}D8C@OLeysU;ma%SG@4cbZ&%#*|R~w*tVQw!6
z%_}n5?jeXlN{f_IF|}YGwt6s=Z93mAj_lZm{Fni!nE__K{}#gEJ(~LR>%KcLXa2j#T$^*OI1T+m|%GB>Xv|
zjbqz{FFr}t+NOjtV<@auV1E`Y+h&V?2vGA*R`j#!gGL~1}v*J^Ie6{porI!t2J`mfx#SQI34`B3Ase~?y;j2Y!g5`;$
zKB4Z`&d7nA3A`NrJ6zG7+od+JWMXs&PKOqZ>3IcI*nKy$0zOyDSwXQl!g9QUfOVckSIJdY
z<=4goI>n=y)%F(T*h1Y;VTd(&)g#@utWoVFL+#1Z*fc5KRRuR_(QEIbZ{EMMHPL=I
zSy%;Y&0SSJQ{lu{TQWVv45tJQh+ai{m&`u|tJRc(UIq8XCGS9Itn_NR&jo8+aug{+
z>VB6bi?&{XlMxcEk$<^uC05h&&g;wI+a%978CX*Z+ZMTw{Y=F#FE&Bk=Bo1y15jD9eOIi&p
zYSiK$4S$f?;18=81Hjf%NRnga;@Y53${!MJ3EW%x0>3ds6Htjtaw`$68KN`U-8ON*
zfz+o=GT`FS^8-H%L}S|jP`sv}^V%F$$ch182)$;&@9A%^T)qwg}|D
zllE`naXM8<+T+C@!zrdeDvHFqr>Cc;sphXy%}-tQ7Ou%dNAhgdqQ$8T(%mo@opFm7
zsM6B8C5x9XPhYXZQ$(a&w?xdZ;+8C3=PD$^UryAzK&lnXIaO*}nyX|;#B*z(0aPni
z{t2{l$;#BXRBxrf4Xn8McGat2p1LAkHUF*D6$@RJ0*x-Xi*`ej3#MAL5K4I}7t@oL
zFIxGhaxNL`mc0EKUo)1br9#Gp)a5G|tz5L^ZPm)ud2gk=o8pmRM4Xs))6)A7`y72N$g(_1ydgs`TZ{`^ZOxFM4~?N;k`BtmcJrV_z8e9BvCk`aIRx
zC{<)cq{fXuX3DDxs+c89Rz|8;tOSBz2wCw=U;Sa1FIlzp#gMdTCMC>JO#=N{2_LTd
zo(qo%k9yR;tJ9Z5QJk=1VX7PVsuk(W-vC_@;nS9=R;RwTC{2}+*oR&%w{p>HkX7Of
zP=|Iwx=3}z;`s|Oz4$TK{Vulua;#qf!Oge8)!HxM)(4DYItGh`h~HBU?4NY_5go3s
z;UWbYCK*^<13wm3E74Q`iGJ{g=L(iqaRSx-zdxUCAv>TjGK*TE23v3(xZ9uIHQU
zR=DtSsf%4txC|7j5QFBT3}i=$$RLp9%FmVoY1^HG<(-JKk>~$&&fmVgH1nPP{U>I0
z2MZZ__Q5@m|9g1y$kmolV+;OPdhzvl>n3Qmk0(F&^{}Vs!I(ece?4LUQ#Iqh_-(}G
z0X_3)Y&!PRnNveZ|5uIqyA0*!xp!=-|0-7hpT@2Qtf^yL&rY%v&{m}Zk)G-eMDSTI
zf`YY2jgSZ63-SG=8hLnI#ezsZ_t;AaNkEH8BSl+lL90~n={Xi|&C%NyK_IsFv*=ev
z&u9H=u~qBo^-)o@0{35gXNTCH+NRi9Yi9PE*|TTQtUdFuHQg76RxLa?-hc4v@Nq)>
z(mnmkkNcH)ibk5e^*7Q_KPDZg3#oQLCSA^0-`vNfD;Vpqe@wa`V?&BxXw8U8;v251
zIu9v^ypSJ$LtB+SeH+sQv1zqd2w&l}L9-H;(i*o6>v0(`|2N3yBKrI6^4zI*U~
zP4KRw9}j=l_|P0a%ai^{J5ikUqw@Ek9sW#8cm6+{i(Bp{eyaD|xbF1j&rcmc@PF*1
znUoLmsa)yjE6bOb(tSfA9U{;ddVjtdh<;4EbiZA_R}1YSiJ){D(jNMxQ#(mNJR_m)
ze)36wC?z7qGh!;F-SbKB^hx&{v^8!0-nh9f8-B_imA@izD$C;$EOk&w$vzPdeo{>h4Y!d&ko?_ZKA``6lsOMk_j
zzLuuTwBCVvwRt%vk%^uW9`ix^TC+6XuU?1gL}E~yNuM@dA2n8=7Bx042BXsS1!+?g
z$3{u4$d3m6rVP4
zmXC}Df{aA35D)Lo;o)PV)95dTdHC3|Y4`&VdHS(Y@lq88e*B|6>NqAgK5fi6Pk!(*
z(cp!B=0NCh#&pbIYchN1I>cq?ty`P7&J!!?QpQ!#cvj^?gUZRtTf2_tQ9*B+fr)Rq
zCi0a(X)=(5I*k|)Iq`X!p_EV1sYq*Gm+esxM(nCo|(Q9T4g2#XKP+so|Bm#ip#y_>jhO*nsz<$DN{92Xh_M*7S*iYcr!H6
zU&PN&GHD)75amxX%+@5$`&p8wZfkSXR%fpy)n{~i2Ku`uYsDJOzECdGa#v+~byuNX
zM4bcCV}xfQv?+A2RT&$Eil?s>-b1lHX4A#Fc%-A}V4j8Erdcg$Xi}Rek^=0#1MwOm
zZg!s842|5kZGH5X)yr3{@wS_wAEM@hl0|xpaFHl0Rg;C@lb)l=$bkwgy~I*l%2Z$Z
zsT#DLcu&H8rlPfc(-WY_XHk7g=NB|EsQg~VUTkBrE;-Q0G#-Uaj9(*Zo}xb1`^n;I
ze<6Bt_{yc4?2L?DbRw#%W;D8P`Y&Ro{z?}Bz}Z~=r844BMu|~AOj*zsY;lKdZvR6YaFISG-K1-T
zbqN*oGyl`2By0N#o79yNg0BwcNkTV7Rz?;bDuNA%BD!QuquJSkeID$4@x@`+977l{~Cszqv(6&^(3N2>^B|Cx66)qUVesV2#fFx%x{&|a{%
zs066WpUX%74ZrYSvhI7Vx*Y91RX=Bn=-UN&c)$B)OgI?BOH5!hFcu=-3Le5%14O%e&SBMBr&-)T9Uc3
zLl#*wvM4CjS8CLtT8~u1wj|q0Zm3so%Ag2aN2DZIwvg5^e_ir5w1H23pZcZb^IECK
z2cL?tO^k%?kGR7ua7Maz|!u?!(GWuP}>|H+~ExlY-3}71SU%e1Mj`*=OTi-#vEG
zOCIgCbNY#fw?~=#^#RHOp1y7OwbtgokP&8w48AX$J~G+1W0WXmtCBOU7JP=JHmL(`
zEOJw;O6S>2N>gpm;;@%w
z`#xKR*7wbSJz2zlQj0|VBlXL_7L6>5-efTZ0r^P?e&t270rn5&4Yx)#T!!C7PHx!7
zS&a(zq)7{8l=H4qwnue|eWSY77+@kwJ--BNtdl->2A6P?PId&6b-m4CzFHw8yrMII
z7^`S^<^|)Oxhy~RgL$*kFULgQc_*E;8LTFtu2g$ex0u$inq{#WpUuVInr{nI+o9ce
z+`;utsLPj}*1w$D$fN69mzkEX^uGnH)E&XwV0At04}`q%2yFW5zpH2Gw1Nez5t*2*Wb|`UY$-wql3>B_0e=+?`z0(!U%3Gv*???V0
z>JK^8SRu6-mjaWAU4^kvVCPI25itfkixeqb=+a9r7t@_f09t-PUfHZK7U;KsF(~mI
z@R5P+!qh1@>?)fTJCR#yEm>|F%93sXbI3y6w1(YA*!ltI%gp`#L2VUm{Sf1K9y!Od
zq!TXXZNzmA>?kt=U5R&FK`DBcbj-G1jE@%MW#`KV=_j7RweZ^~$M`u8bOGV*QMV;0
zLaMp~4|j?y@uJsfudBq^{#08hIL-U@s8LWG10D4-#Sd(|3tCs|Le1_`?LP!{
z`zL{_j|=YZB5D=lm{4z`3Iyt9SEwO(93NF!kUN0>&jrwKjJyUOeiAJS6Pk=I@)}2v
zWrk(ugrh?miJowL{b!Uu;qzBd%8aiY;|-?`?N`q{G;ce^+E+F|3^UdmR~T*^+J`hh
zXy19}!3yJTW4!6KX@aeezsq>^o&&}5nndO|1$%j`U4AhOTrw`9&d$q&%6Oy2IO09^
z#SRWGz?oZc;NhxGcvO)9)CIQMFBp-Cj3o4O_oG$Ex0SkF#0o(m!E*p?cR{E+*q7
zvlYgyIm>L;_QCxgXsh5BX}2GTc7UIxQoQlXlU?IRHbu6;4-#K6X-6F9MnkQDVfUGF
zi!M#3dH&PMznHx<9gobous;ojols$+L!{hZN@bPeOkT?2rBp@UR4?W5Qf@EhD3AI%@3{-}y+qYMXDo
zC`GkhD$n$$L^P4i(
zqzuPCGAxJ4!+F$jYjeXQdGo17;#E<@YIXAFON%J2H5@&oMLq-VsU$5~8RDF~jBVmS
zsj&WyXEsxe)6F>(f9$F2>ExXKc6Dp3IyiMtcmE(`j>G)Ycbs*f-LI~)jq4~YajR9k
z1Ru`M)L`bq`%U`zCfO&iTWg@3uMfs4Zt$&cGyoYrmst~nnE7?(fG73NyLdNb#WG&+
z{4SW82Nq+FxYAR1BO4?3IP!V<@X~eXcS^30viVJ=>eQC=TQ=ka0p35a%=w0u_N=N-
zLzjBBhic|r51rLy{<=*;`;@IyZ8J+v&Utp$wJE0Z1~V%=SzTru%IM_i^y0ewHYUp2
zuti-I~#XSsq5@S`RY6>|o}Ncx0k3a=({UU3Bpc@{
zHJbaMQ($~lpHnofr}3EX+@);oA=+vj$4b9
zv@guT4o$2jjTq3+i}pVcPu9%8S=5nB>S(N|y9j6)R|kvIM58I>Wwl?{*w4<{FYdmu
z?;r6kT0f3OmV|yA2W=wOG0m^m9?GkgM|s%F-z8j8qF+bs$fAkYoV<=7?)O9Nq50;D
z8YTAO`O)xCJ$=$$pu{rfoSkD_=uhKs5f=k2*)?@#5p$W;%!%(oA@_mHfeoJ#j|
zu)kNipGz{n7H@vLf_-4DbF>j^fKRq@`Xe}H%@(`SWmA2iY~Skc=JnHYg2a^M?NjAv
zGnw^_iOFF7WP$b5hL=TTh5stoLOB=qW$Ne3vz#6n^klWa{~c$^s-`ShJe`WGHSNEi
z#quU2yi&<}7*0t4ko0EBGniSwg-Y0
z%QWq~W2TqH?R7crmTCUiL<^Xmje`Blv}avp^AeP<=F^)#MUN~8LIsE?0cY0$Yhv*!
za~?aNPqYF*W8V25>j%$!)|Ozh34ZH4
zb|JxXqR_#ss+H{nR6T^NQ1b(TNub^<2da>;1j$D$zwX9!`nukkZ)5lp0A3zeCN-AD
zP6xNR56Rotu=q82d2U$jrz_8_R?!I^IA`bPjqTX^UksbD3V4Nvw=+?W?xTj{>Zady
z{WiM3Rwql6BoG3mf$$aW-7J&sartUak@f>Ns&n?uf8RpiGQK57wivltQY`zL-*2%UVmHP3DWD)x_!*)A~o&|h&Jcv=v_4rIq7d@4}IPAW*O2I5i
zKyzapDT$N%6mj%@|E=bX1|_%BmoQ;n@$9vnA)p;r)5C*)*r~IepqRrNC(di<4LdX?
z8ba97H+uOALe%XL5OtO-OO}+AB@wSv!XL=JZ|lW2qcMm|f_IuKsbp9+x_S1#yLE~<
zdeIt#GrxsJ7FD|m*=y$f75;@!ZrV6djdL?CK>4Ci+6L%R4+Z%SpKJ@%FM)607)Jz0
zR@57VZ3c?}uR`=!3#^uaju8=Tp0@}6jsCl^aGL>GuCpet!8&o1vm+R*4CvK6Yjw2d
zA&i!c<1%*i$lqb_FhwKd+?v#LN?A1P%k|}+=l++y$X%CRm&sDF1BUN^9BR+~H^*a5
znKom__h@?Z}o+EQ*b^qkN-}Y*v+H@#`jeHw#*y9Et8{ql1%LS
zJz7tlQmW@Hotn+T8T0GraAA!aHCqX~DwXI!w$4iju_6y$tqWw^K;J>08*78uyPy+i
z6FrFikB46NLJ&Ldp*6^V&PxZet6q8_>-5sW3gy8a
zCJLI=_JjuVUk$A-j9*w9CwQOPP};~(FD*V67tC}vqc*awTN|nB?$ty@YI}k@)6KRY
z`*}Q#^`x`zoDt{wP9!Vx;*%85SOE4Az0c-%yc@sXk9*&@EcotZH<=C)2I2P-@r>!P
z*@{+TY%TF?1%4RuuXxh`DDGLZ0^+Nf?pem@)n>)SS2JBCC-Pf~-_3NR7*kUEcH-Y<
zI)D_OAij$D2B!Nr#;^~~*k6cmB%TxazY~9qc$vUA5#L0-T;N-YZzf(L@E3@0A)Xib
ztHisBR|@xA}shWHCBz5HO}HNEM$MfBHRUPJt7;#;vE&X}6`vBaZ%fHH*gb;R$($~|Mk-ch25
dAL`*#h~Lk20B+E8V+)9XpXovw>qk8O{vYpJ%wGTi

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_release_v8.0.7.bin b/bsp/bouffalo_lab/bl70x/board/builtin_imgs/boot2_bl702_release_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..00555439c1b30dea950feb252ce67e332a701633
GIT binary patch
literal 43168
zcmeFaeOy%4);PY;nK^T2@CERIKw*xIpmGb5QK_!c8Jw8|_!1ck8kTrO^Ol+KdLO-k
zGiPvAL^~oKtk*;NMOO;bcuz#c1X1oBo6nt+(dZ|ylVg5CRkKcC<4^ZoCq
zeTH+++H0@9_S$Q&z4qEK#Tut35(pvVL?h>m2x5MIkL)94yCLsEM74Taqk@b={fK_V
zUx}~Ko5U~VFC>|W2tY(6K@$H>P~#B(K+pCR^sJJREd1J@CXUFD$fHo?3P1F(#Us8=
z1lok$g@(o)d$Q3-CPM`qpiulzjga%yr$4yf|F=Ir5?)~JvTOev%47Ir2|Sj-V+lN#
zz+(wKmcU~PJeI&?2|Sj-V+lN#z+(wKmcU~PJeI&?2|Sj-V+lN#z+(wKmcU~PJeI&?
z2|Sj-V+lN#z+(yg|5*Zgg~U)XlgL>1jyy6i79nwc?33b8QE1uLX^|p{5N{^YvP7S?
z0o#b743XKL2QYCxNiEyDH1hWlpGfgGN%C1F%AdQefQ($`6N#LWM^-o^>)vuk`nhf8LmI;1WZ4z?@0|ZqHRmM~
zJ*^pYs`dzsU=DGj#3>BL4$WgR)V}gU>FgzYD$dxa{$Q!vUq0>XjPGVOzE(f?()^2m
zt1GfbSfk9mpzt{^BnacHoQZXj#fBl3(dkITPzH??ZH=?)kF#NVMf~lVb7x(g75i%O
zt0AfHrING5gdO^{wDlPhE*0uTbp{hR90eJlR&J#Cgw&Ox_42RtF$VDJ0MI-_=O=7x)!%M2qD$%Xb2B7wJSt
zVlE1=3GSNGM1tWO^%m2=Kg;v)_rvr;EN29a0_S+D{kEI;zks~Q
z<8r1#PP><&cc`der8MdpsP9+}Y>Cl?$x)_0-9u?Cl&4*Eti(K7$1mH3elm+2bt$HO
zUMS2mOOT{yzfPQXQyK3>k&&luQo5(M=z)hr>e)(L*a!PR2z!5&&CTia2AhlvLpon(
zoIhf?&K?Tt-+}_CDXJ(s@S-y@@k!#Ggll*K_z%~muk$Zvb;SA%!q8mG5X62)!IGJV
zk%5{B-xST$nJJp^Z7G_O!)9v2#>~_V*Ui*~ygXB*PMfKTSdt9s$&j9`8CjUD2|Jo>
z7{(|vs7%8KAF^Bnn~2D>WGy_&^|dpHku~HQ(6SI`BD;_g%Ah5DM!57i4m5fyyrIaE
z(ff$l3+W6+{pwT~45RQH>r^)l)9fis0gS{Wnj*o?{fkcY&QtF8zv6o?8u|u9Rj?r6
zA-#Q|Ahz8lnM?y{O)S*+$>{k=V*@>NQBhP)6a_&KX;AvsAPl370>l!n>C;Ei?8pA7|MkAFHcTF)E|7j)E
zWfIhpi8c};HUkk74L?R2)z9bc!Xaxet#3*;TQcD(u@p(
zQWowd3Xzp768M02BynPxd@F_-z=oF4`(zAF%wUB0DJSw|`|0CQUVmSsNO`?9QYq7q
zLF7g95?N0+YP<+i;!geSxMp7?w6}-baRUI~3iwhw(#i~DkOX>Xo(5YM=
z4H!6985w98A8wxho4{%I-%6pTI1}6a`_fX6v2wi6o&IilB^@dSUW79bY0rtAdBMbG
z5?6Y()W<+KG7y&>lj}@GZ;bhEhe0)u5hf+>$#o+8yMqln<7A(ZT#2hW-+ItE)M@#h`k$Rc*)S@74vJXQ|p5{dA|DsA6YSJrCl=1f=
zHe9y}L77HeugE}R%BkG0vEk;>(oADy;01Wgv^fULe}?f5bWc5T8)(KD1Z@!Ok_pX*
zYN>Wo1c?{rnJ%{;6KR$#5!%TKK{2@(D5wQ%;tE|YvXMTKXF9+gE<8V3sZ@eSPqKkd
zU};b@es)WGPVh8iIrJQA&MhENknpu(>)1oskQ)|yaP?I<>M
zLJ-J>j0_a?r*apKcl4v`haDs&D(u#O2wb??L3GzUHp*Sr9MdzTW!z>I;M@0+qOqeVlj{!Pw{?(^2XI|^Ag@4cPy=%0RXu$erP@*?+j-gas9f&X`$0p@H
zc*@q-j^mhyYN)L*$FslOz-yA+rN%Ddc
z@vk(YbphcUw6bQz0KF20Ovkfz^5-}3uh58yTNekrxZKyTP5B^MfQ7NX=
zj4Ivv-asDQA0K2Id3_5}qG-_-?N~Qs-B4bB9`QSAbUaHdv>--_NUDIpdmL%0YlO@|
zAx*}9Bq*+x@^@_TP7?yHRkX8?c>4oaZ8)3@k7#R_OglT{%&ZzkeaNM-iwSj8YhSCH
zTcPzjhKe>G-w?5hUr~gZN$oxBX6fc(-)e@ysE&|gKSZwc6U`N`KX;I!6G`6GD(9CQ
z2n}jSBJGcgt&AlI#Rw)&ftr8k75xzZUxslSM4{rukfisL$eFj}=O)BXDxMTFSxZgV
zT}&{5uSCQ#bR8)wB1w@#vM~kxha(8)jW{&bV&VoPQ8gGexAg(@hLY&E@wuxYZ3DUt
zZw&}w=-_j_PJ8m^q;*v5HOvf>AKB!(H
zsHC#n6uh!Nguhv(fSN1#f%OCVU#sMz0;K9){}kk)c(Pv2uQU)MNE%C62K-|w^Ir5*
z{2h+ii<;p(6fHT%0GIsEYGlGZT1Ekn@wVgEOzve{rXjvmRImzOQ4d^fRX76c?=f$T
zM2C!DLfsN+NB{Zo;qMrM
z@=8Kbbd?HSX#(kl=uFI_Ag7QcEsN`5L#u2%f@OlD5%c`=-Q9xfmY(t@=$O3BIOSw_(Cnjy#zn_s6*|k6V|%^5
z9;`bG9_c?d;kRNnBd^8E4uJO=;md;8$!bE5#%hL_#cIMX#A==V*nC1mC$YMZ#nA*mvDE{x{lzl1%)r|*tQ==90tav
zqFkJh_dkXhLr2g03=>Boab<`1u=U4sum`YfB1OHhrP3Cxiw2|1-)bfO;`h+OWvK>c
z!(f!6(~P8u<9ViP8ifFMYFVJp)BqG_*kBy%Ad_@_r$R+7fL@+4B*#B%km5w1MokgE
z3eDDbRGe$&)?OGkRd_?-Yy%M?Zct|U=`6I?1g&(dUKSX?N8wkNWMGs5DA85Yi5({B
z$svm39Z6-fkzkaPWsoAy_yUz!T1b9vy_a8EiREWD*D^j&rUjY
zy@1DST32FG=$OW2RFXyO0?U%hFef%#w|6?p5IV3dFh13=M}f=4bpsy=>UPRqo~a=e
zCFz*tFOZh*B>7t{WMJ8&wFB?iN3#vr?GWd0(<*-k{cK@V%9w^^l%Ip^j#E!_;Ge74
zUVw4UM+I1oY>A?tO)3*-BqNODpM$v<=uBIR0Y?9KS`>j(K$q9G$Tx7?C+*Z(xA4mv
z&*xv3-3TF9^W)v8g6vubAkXT=!j9aZ^L0{~t
ztX~|HmxWUGjAbzLsgZOBG{#Qtk4&*C5R8&?#iA|ztp?JCug5Kr#Kz=lM#>2j_*P7w
z1z~(9z<{Fi6to`;Gwo!KW*U#966IY|Hd2rHC4oaqEcc-OkAt515t=7D6=GI<&nZj(
zwWOr(!7_~=@XQ2Z{yUpj*{MaYQ|g^xW^&*VG>ylO^X
zCsyu|8KJ*X;X4xTve9xRs|R^S=n*r$6s&3`X`%VH!=%!#70$5!Lii45>VqE5)+$tT
zw}x9UZ#O>zzWe3n94wpS)vPhX1g$QfUu8o^;c0%0R
z8X{(GqCa4CqFnAn7}2I8oUq3xt+05vtLiTz<&{QW*zU!=3{A>JR#gwKY5s
z&jt1<#^V3rM5OB$KAX4z)QIgt(?{=pHLGScM;|#
zX2N%j!=E~Ho1Lq_sE>^=jt@zAFM$HTOtKf3*(AGUFXY%>03CszUCML@pm9dAJ^-m`
zeqM){D0K8_18iXJy4YuHn1TA)C-R6m%7E=H^->_KwH!bS#Zu6K1{vrn;jW7*&{dat
z$k?|o8mLP$?lF3>@FgyrtDyMqM%1T1J}uxSJLY|H@0n7q>|3_P(#V=d%PEOh;8P7w
zE8u7YyorD0QPi_Fr%Ru$5wni>L{o?eWchavkUnmSiqv4>qJK?PA0GVJME2P@VZHwr
zae9Xitbm=Of7?>LBO))!{%lQm!1q0aXsD;m{H9=xhB^vUx5YtwDYVLO5&urLtiPwV
zz(yvr%9;ol?GQy2w3U*TB`eWnmYH!3dMS)2-IWOU(tklOje_yyXOOVt{eVA&W4_s1
zOC<|Ef`VQMHrqExX~*f>ya(v-d4l5Enk%Ixg1@B6jWa+}gLVBST?XC5){eh*ncPG5
zxA%`r!n(Y{A4VHL;;_qVjCW}>wi>d=YPAS9qeM{1l34!Uae2uGFP+$!!uGctcWQRf
z!(9EMrCo{j46I@3WVfDmko>*NO584PYxqRx@E~rVOXojz>Ab+Lt(*CkHtP#E8)TV+
zw8}5oKzowiMHSkDpKDY4v9bm(1lpStFCWJ00TU
zB~xp6FO+6);zrd?>P@ZJI6}0>-^4RHMSVgYp2>xq51WhLXZrm$qbUC>D?4O{xPe^0
z%@|}HVi*>e8)r2Pm`F_>b&yvzjOCkK`tx44NSHA<
z+-er=J=mxdSt&_=iCRSi%ipO++N=g73-!7gcxi$@=o+6-$1rpOsmihDTw*0`t?CNP
z|2~3B@6Sq**`8SpP%#PQxo*rITI@QdzIq{Y|*IC+^o%oD09=$w#%RJs%j;l
z-s0u(4QSuVik1L$$u4pIRs5Dr7bF$M0;)C6I}$9L;b!3H2u-Ck>vRlF6e9n_?(hk+a%PLEWzdm9~ET>P|A3+pCbv
z_kuKzegzceYZ`_a`bG*ax?=@6N+9Dd$rt?|#O;;xs~jsjFaE!272G1h6_>wMaS#!`
ztMQpfH6MMnwi@)g9Q%%IS@7cRH~OTmX0dlp!OUZ=J=@iKDS^&1dzVToWoxoS*!fP0Wh!X0jlr0dd)98;^bUeE>z{_tlqXmhgU8V8*JlZDtwp
zI1<^zJ8JCGEM#2(%tP#f6)V2F!12ExP+Vm->Y|%5`IKXsInoo~jg>k%^jo49V*QmX2?$S517mQjfKqF4A3kq)$f=(K-epzDL?0U-h_%q
zdn3C`f5Dia-yQl`NA3#~j$
z+yMJQ4lqD@dR)?wbXX$@0qX*C)+p}C!?#0Uy-64`nB>#~Y;?=9Jg|APSEBebA*-uJqyK{O`#Cy6XaeYmgBk4L;jC)O(WtV
z@?=&KhCO+jkS>UmRj8u2Yd$e6dH*{|^NCzZx!S|i`Z`}lRY(PnTZWr8-k<{^Es3GhZ|v(!&a_oG47tj2uhsn-nyO=`W{ju%-nwGUU$KbO*@^s8`5hg>sj0wOaBvc&Bt^1su&z`E%yf5F
zKfw<^@Wfkjsi|Y*0#i@r2B(Y%ZXgnocX)@^){0Dq3h=Qe)U2)%jC}rOBw9FBV(WnP
zu{CRJCQM#E`I-Uhl!xmSc{VZ;?DpBY;3It0FhRduKeCR=3II*(M91^iR&3**g_eeO
z@YKXqrZXDx3>}_}Z9McVSAB+dk{k5hhB}rf_Yd68rm}&P87266d*np1%a7J3cOqt0
zr#BzmFtCtLwLAW3zYm%KS|f)weN1V{Nq$3eG=JkB$-lQiCT`LrAwe~1yM8nKnk7Uy
z^jx@=A22<1Klr1~W2PT;ykFfkHpM57IPAz>bqzyDX+taVs+bDmZU&yAKK61pz4U{w
zS@hC-5ypJO45-_Wr^BrbCHLwc&j%h-%n-gGzdB_?ia5BHu$nICs7(Cs19JXJ8Z3s{
z>&sRdx7`cI41$X1$xitT2XQIW#{^v?;{6X&Q#9yfA_&SlI~P-QHsv(%!Bhlcv>F&{
z9()h|8kc4EiXYF*50OLSP244d|A>y@pHw}KHF8Ki4-t!D@tQs0#~suY7d|#|^StuE
z4vN20YT}lAX$Iawj%D4KDoX`=BOTm``;3)y^&XHG=4IG(FI+K&R;U=29BO#WUlZ}U
z5^Q$UyI+~YDpcXwTIvcKU!@xF81(5~ob!$nMp!SVvs3nRkJw4ei;dU5W)x->_VIt4
z;M$vTCs3cNhd2lA=M`ATU!uJ*B@fOOj1$~`8{^0To_fhN!mJ9sBp6_=jCJ%hw_$Hm
zOM|s|`jS#+puHH{hjaus-)6E#0PMPQ57q@Q$4AH89LkoP*)-+}B1eFUd!Dmx=&o?9
zBbfSCHljj>Y4a_uq{{+doq&A`m*tSlKxZhdF_~YkOYTm#mg2ucDJ~nA3o(ak+Uv%*
z=_fC-JN1r@E!V-@0B_-}U7B$?o}^nmx?P+X2)*{15@>G)Z%UT&n-);~R$7j0I9C7c
z)wNe0+gq-$);oMVuWRHu`V7(#a4p9SgjiECo9TzBX=qXWQ!^?)z#ND^dYavzR;_m2-SZH$wE1u4a$t
zWpBFmhlKaz2WhY(FNggDa?05>`cub~RDGeV$4Ncbq1u1(|I}k0Ov5Elk3Gs^E!>A&
z!qszeE4+NvKisqikBYp?
z^1GvnU2**T9Qb3`iEUpGi--R2eFt5zX}slVT`A!kcBaV8P#Fn00vb{E<;ZZe>Rhp5
z@4#FX2K63&N2C5Y!S_apkgF#2x4|R9F&R9TVyXPNqub_t4toUQW?3keps0cz4?Nz$
zfP*mN9xhDL6cDpCpB#l~y_iMJ+CEXXKXaxwYd_*wRU_HHvY9)-9-k}4V%KLR=~k>7
z5U?wDBh{7jefH*Z$=`@Dhn2&))?cs7G=vC>sysDb6F^}ijqZX}6uVgLyMW*NhuBJ!
zyX^0|{Fp1Y{GV`ycg>Q7I@u@#!n4t-wKL8r>ZhHZRfFfGc>I@DQ(h6~V(W3Uc(3!1
zps&S$(ehxHxz{P%pBHTB+w)K=cps^DUgafc`XRZt-y|LHm`92Ir-8_YmXdbzh^N38T@)?ZC0uclktuNVmzvdv|2~
z{XDru!R`~j>F_3|KdZo;37f7sW$-i^{XBH{wSs<0P-v9ki?qAq
zn1(Don?^AALreorTr+8i>u4|RUb`x#k&s3{Op`&H><-#B*_BTYY4V3@6r@p*PfAlj
zn&M#^4QXKEcO|;=DIrbyFiiz%DoA6kCKzSB^EVxJUQHD1fiEw>^SXq@dKX{)E}^~s
z058dv)*sUPd(!p}fYDgQoNxQuouw7V7(lASl2E)IrF_F
zylRf;z#ujH#<6WDlXSuYh~%~%&)Ye1fN{VkesDEXahk&|19wf7`fwQRiacyK8FCS;
z^EWtswx*5ZO6X>C1MA09#;*5E8V-=TbV)-inZo+n*L;v-?+(Daj@$T3PH=^(YB>sK
zQ&>K`%1dSBbE>@f?Fw}AgBLz9RVCs1YYuokIolL_6qj?R=X9+UEgkQ+=a{PIp~C<%
zRc%L1M?;TwV}3c)G6HqG(tYeJa#HN6lSLR|q7|7LzkQH;HdViFa5Vic>iQtHBAB&N
z=-pygY~@g}{c7yGEvD*^LF>A5WYwRe_w;k=MLAb;F63M--xYi71F^Ll?JDn1POS?B
zpNv@$fCBAeYXC~MOWrrwCKb6g8oY?jLnh&;r-S{=0
zCtZ4l>0J3Bzl>?M5RKnr$c9(0zJhm2u5-n8vULk!wXtno
zPMK+DHk9BU16I|RN5n$Apx`pt??mk?!!3p={u@|d4HyS=5?#pix&6x$%dnjs1-o`^
zbOs6dY)meU6Q~__)8P4$Sp~1R2b0Y6WLqX%+DsldDG|xqW9{
zc$5(2I+bI$zMFtq*H836lqFE(X)qf+ms1R_5(0f%qi!DyE3y<78LR_&sDsPk+1dGH
zF!0)2wxTxN?CyuB@VrX0Q1VFdtbFpFQcBZ5d+ki9WQlri-0$TG^OLF@#tHK^1$3mQ
zpfyr#pPlyKEH+#F*qH=l#~=u|;bn;)$y7&R`xCXPKB9mmdvaZp;9
zpwbF$kJ6XM(>NWT&sPrR-HdWmf{w&8
zlj#Yv$Q-A`b9<1T74H$5v0+*T(B2p#_Z=tZ#S@LJcAlP?y;%%6jmn_qJIC@{yr7(6
zFZ3-(TJ7mB>6L_M{pUaNKgZ4g6z#wBU#9I#mr7gsRWD6R9{(r)-|55uHtqk3|H8la
zEl1+^h5x|6&NspC@PlWecpN9GkvHQ&2q?ba^asUh=`>bc(85W2F2#V#QIg5F-t+-=w35
zS<&ttI+2Lu|F#!JzX3bol*(laDmGV^LZJurGzGR|#nic+Xa#x>`eeb~vCItEuO=wR
z7H9Fxsv*vfZL!Y8tfASKUzIk(SEM_7r2eF+
z9dDglg{{&)Oj#8fD@WtW`Q`Stbs-_Cww!DoTezIbX%Z~H2Pxp7KpXE
zYgxmJR(fpv_!{D)
z3o)5w9T|3}+>BTJXW5TiWs?Z<`Hg!lVOd06Ld}eF=(8Kct-p=m10L^fcGiaaEOOF&
z3DdG_Eg=cT@nMz(0rxB+j!OHqgz%kKAxj{j9~jM8|8Z0c_Y2viOme*SgmsT)T2^LU
z*cq^&=B}7WDNfBgV=0c0jh|)-6G9R$>M_M(U*Yy-%$c)_EJ_wfl#0RTWpcx~0kHd5
zQT5C?C40sqeG7&$FDP9aL&op7yr-9-Rs#guz=sOCgsIFpb9^JFG__Xpe51h2e1798
z>o6`;qF9f2+|8|swN{y9Q*UXN><D
zy&q$@tp+^!VMsLmY(Tp&eQ`tFE=C#mF<|duXs$rC7(WD>JAvj7p!weP7jCnz5e?7E
zAGqme{4aF-@C9_&1Ko{4cLUJ109`ZC{Rhxp3v^efLq7>Qi(3g=`b@Sy%ubeP#tn$u
z#tq<(83#ZtMN#W)`{)p)x>I&T%9oImZGbua!CpAdaT4IU0RL!zFC62S0o;o5_w~ZR
zbeC`p#Q5*`!g0MYK8E+@KO5ku0lp98=k?-a{xSSC#^2EkKkbIQ==b3t<756^
z@)UdVv3#(cUG?483&(uodSUp`t-WweAIk^J;iD~&!XMJl?}cOjG2A8pO-feaV#>qp
zxb1Pto*X@Hp9<^VkR@ko>dU{gTWa^5-G8RG>SD!fKg_*4|GU36zFl9mF=7)D-_2?1
zzYusA2H&5K>W-%pO6b25rn9i~b5cpb--(jWJOb<5jc=6f0Im>9$69f|D?A&2pM!5K
zh4XidT;G_73;4UU$gE_w>rN6<9$fRBj*>ec6E`+{=wPjTsa?v4>Ez?@JK?oBJ>N~|
zrQfA;aJjp2`t94Cc;}9HNoO}IS=EhhWV)!9|kG`d3r4l@p^4*kjoKgw-fGzbwsbue)5*$<6?V>KhbAFZJxTP`vNjDwu
zUnDs0Q@H>?>Y;x_g5#QDI-VMMLk&DN!}$9=_$|HkG29~w@8(|mxZF=Y_>NwDY%9L>
z@bgnI{l0v9_{a6dt?QA4_m2`juJ0rG-%D^0zNcQ^S0y;^gMI1beD^5+L;1M*$M{$d
z9zJs#lfF?esj;(*XNN)`b11sbQmRE?-nj3`;{M0+K7Aj0`Ti*-4l&_cw%(&HxE-)oVBI`_
z{z*vYi9@jh3f{%{z42g{iV!z49HB$4&!QF
z^fNhUo3pVmE$`1A{nP)DRmu^_(ex-UFV$nrOt%~t9}VB=7@XeqC^hd(eQ`#A=I}Rk
zVk)(kVc@%9Zk-pDEakFgxbHg8dA`1cFK_tDj)%CNPiCC2tN%;AVOIH6unRdL3jyo`
zwk%ltT+}{Qvc3ts0gCNB#?CiPtsu*%VLNiI*ZXnVw=()4oyBIts
zk6vQz#o#GnNnnX%{KcRlSb82w=M=iX-LlRBJ;doAY3FK4{Xb&-t@44K>a)^SX$PHJ;xjBn$O`h&zSDXv-lI}
z-$vjw5ZBtdE0e?aZF``W?tm
zXZTF?rMJTEw%+$!Hk?jBC@aM$=xr^Cy=si6iJo-s3Y8t_rgdv>|+)xT;^9bs?yA{tc
z*t@S{I;QG#k`7X)%1h3{+3@;fgUay-PZKjru*?x1b*Wn2Bm_KtK!fzFq#
z`hA3YY)n;@0aiTZ5Q%sZ_6#AAd58!x$P*ATCaTX))DdJB9vfFIQB)7EeB$e;%8GtC
ze6{$yR>ao9v`iu=PkFevq=e~&BY`tNSVcAyyvCDiy#||S-
zutl*?Ox!qe<@A>6GiFrH7@xd9d2os)W#!bCsWV=xdTIQe{c{GVS<;p+{b}j6W#!AF
zR_s|ZXyy8qOBejKVA>nyZ$!Pl=j}m@*DsDwTZYt;|M$2DOWOQ@m$yIP_3-cCE^RxI
zu99n2P*a4&{)kRZ_;rIcYww8V3nso7@h1nRF2$Q)o@-1d5_#77YHujax0
z-wu$#9cuRB7ac&r)v5zZ;EHG-D0!B+Ea2pc=7H|LSfD?nI9}cy$iIDn9EN%H3*{V7
zG`lQCFn83Hy=mVs!Q7YdEUTtCEEUW@%%yI4>ae@u8P4I`d=K+?b>eQ5unG25_&M9&
zZS`QdQwlKOyI!>dhV>W9u;>L>jkw*L1e(}`rHtj>ZUe5(t)z;>5XaWmdn&N_LvKj9
zg{IRFTLL7uFF_7@)R%404_aKMaNV1xl;Rvc&C++7OO9(wVN(Db{0ipI`i=5cTzf1(
z*p1fq;?3{eyg+X#Y>c2J6#~J9E19P=c!G*4da`j2iyXwYy+wA
z`B))np|#2kE!
zX-aS`oi5XblfA7ErBqKp_S_Q14|vBG-mgX0S~>paf&Q@iVUEh0(i~MK7~fG|FytX@
zg}?dnCG>VA
ztE7=2mvEX6hUYtWjO{TcUn5GYM-ZU3vO`XhPJ(_r9LcI^yfO`Yku|6S?agRFl-x16
z6UJz1UqbB6V%I(d;FH5;irO|ZVV`Z?^lLU8^(+#?&6JUV
zD5ok~Ba_3rsT_Iw5{{IGor!?>F~z-u1c-$KUM*QA@r!m8b4XY3RC^A9kW(a_Gp)$i#Eh`&lU>(V6H)9nxA
z9oOE|wdK+`@IUKu{dZ~7^z52GUxZ;rPUAO_M}aj^p#(~|uup;aO==4ED_wRGs6)J5
z={Lzn-|y)T=-%S@jo+kb<=vijfh8RZqL#Xxow>3-`$BgAZvrQEe4&e(snDBZ!?c)=2Rx|h(!h1FM$_wGt
zP=pyr|6zX+bqkfqD-a*J-7RIpfaQ$$2#y3@(8zBgsa@=0x1>J$su%U!2eY%4|AWiG
zx-Q#C`$%t^f&)Gnn(JCyAPkG!-aV2Jw+*x-mEm$J?E8ne0fygf7>6H9$-!$&VDQfG
ztzdCEcIYs=@$2YhyqZw$y|Y?+qX#v@8{FGL(*t&XBfYf-G{PIkJ1}zRdFicnlqQo#
zjpt!CGy&=kC72GBC9Kaf9Uvy*zh$n!#N_o^F20k!(3&M;R_Et2HMS8U;De3`i8*6k
zfS>t>IHjUq6MPGKbh4m3yb5lDFfvpj;XE?5L#h1I-2*dVUj+eiZmeTi+ui*#v6z)~
zXU!5E*?!pwapGZbAn8=R^GMGvTXG;`%$bRpgJ8RjRw@M;IbVhn%&^kzJo2N{WEc)B
zyP1jGD2ZlMjI@JYD$SM*|LZ4ToLf;FQ{ilKe!v6>2v(t$Vn7zMDSAK?%COhmwj%p<
zP8zJegZ5-x$r*_X4KZ#m?a$o?E^%wmUV?9d*^&M>*N?xXS$qkjvA_`qp6Vve(J=v`Z~8sS=r6idE=Je;aW6NZ_kgADwt
z3Ni%tyGRn5vk>RqW0`7^a=(6M50{w}Q}G_RCoiUay3K>vG=Gl~V|ws@tS2jGLcCs4
zi|r89X#m`=;I31_SjpB%a`837$?}hNDTmF@Bc=7YKEB2`phi8Hu@8(blSm)I=L}FW
zCsKO2gaf~UC5C5|F~pG9hVZRW?-s*;Cr>-h30YIxS64Eg@rBXw#rkN&MrmE8&_KhESO>`1k5wS(W()JkHzAvSKLA2u&?ahcC5uw25HR*_nU3pWf(Df`%Xr%r@nom>L>pb)E?9e#Vc*P
zR2k<7`@F&C^oPB()SO{3rr*R*&)BmU;Rx18zwCB#L~(nCYe|IRoK05!aw^scuu+3L
z<-q3+*iA=DHO)B2WMwAFxMCVSSu!r7gEv{3hAcbQ+I~iYj3f?C3u)<1WKK*-Ebv*Z%ruuX5M3-RmdV
zRS{kN=?@Iud6VDO3TFV4z~5D?w{6;e-ctt{gS|rBeE@w9=U4EKTQ{ZaZc2AtlpL7{
z?gIzvD>l6ThI?dX1?>1cGPEG=hK$qGxIW^H5h#1321b5yWi;}I`KTtd74|46(byX>
z8Ix!jiPyKn{;0t)Chv8{yv)3G#ueooJ&r{^?Q%Z!(3ld*yhQB2=rGG3?4UC%r8Pl^jL
z(#ni}O7KvWQtEJ}lsZ<4Q@5WFs@7ys==);~6{)U-zwfAToRs7&(x@LJ_fhk{9b|+6
z9_r8G=Aaw6B~8WvXh~gaW-YXTMk~U5AbY+6>B9L3Jl^AVm!Pi)fL{7?l`d~aQ59AW
zd+U)&Ux|(y_Ry6%CVeyP;V+ltw|4ZC{QJ$4uAmS24?jjaBh0=9U9$7Y>tf%CG2Co0
z?3`=2Cbm6zjT!n^s;SBkfzQ9AMWN#ud7GMNS`-mhoF8oFkry{72(Tv{Yi(z^c~mo;
zZOXWVY{@=IbdMh(_2gZ4osj|igz-(4kB%Jd|J-)(_{67hu{JVt)(6-6qkn$yvV(AD
zWvOfRm7>y}b?=_k>@Q5UWjzH_qT^!9v$?(C1;9=s@Fj!=W%Oj&+eX0dyIU|O^n56-
zr@{`<)J((Tx}irg9UPOO(qSKIUFjE?7TEg3P+FI#w?4OI33z>RsE=Q4cOJ><##C_J
zXrmxmPUO|itxM)R4h&+AhfC3G98;
zj%!CH0^XCf4>{Vq?n^hPX+9xl;c-)Qn3(0e&{?Y!fekv{f+W-r-ae#VaPC&Xj@)F1FIg_;5d
z+|mPg6mC3j4yq~^5xjQB^jz;4NyC=$3V@W;kIE-zb^SrSP)Y~R-JnPX#{63
z?L#ll<$wbCsE|XLbQ(t7oG4A?W7?n)6j$MviS?zA(&
z?`ObOo%2(CbKj@}{66|qqL1(6xvSB2LnGehKpD>7u<6nl`QIuXX254_rCrPTbS*wf
zJF7+(ABGNZj53QsqYx9{)x)fTJA(X1q2m1F?R9$7zSAgtqr3cCDF47&y$oQ>5#0LO
z_U`o|r-KtU#Bd_Sg6~(X7npHRAUMJ0m#GgbE1TEthsRjyP9(f1BTRTN36HeJ2HYCZ
z0vAD^g>`Yo9KQy3@3{D_{1!Z%f<-n@Ibbh;C^8RdF6N|iQqKk_O69n2bVNP_b=}1V
ziPnp|b){}9m%-xgI$3Iq{(B1cP8;5hsSxP`N>PhvAHJvIwo0&2qrbp6B}#S!-++kE
zGfl0JFq;lh^04nj3dxJiAwoi<;)iLMqTD?&!@zGpq;z?Y3M3D4dwio$V2GFJ>k|IL
ze&*<%E=-qCIeM2XrsUs6nyUR!_AgRzX9NPIkn`D?GKq6T1Jr*jL)q26Jt$-r?m>>N
zBYGa@`R_Bq~N5gV5TJ)iY5%RZCDQ?%$s%6
zdFrXPFh==^@;WvDlTE&j3b%#`#h&_(@6U!;`5L!TdvdYI>HHYZA2th|51d}mgJ)wM
zz?-}9bBLS%7*CsfTH9T(?_fkQiSj13G?FFQBh0cx6cJWlX24SRSciCU$apBpHD0ynad0OxRhyxlqvuoEOnvsIqu;nWZvuLq
zQtb-hj?i$c7o7F*-Y?Q-DyD*=&ED`viwg6AVMdS%;U&aW!C8$15LIxusc_ACWbyC7
z(J<`O#{$37nFopHoWUhjs7@-2azKsSZj`3zV7>;m4!NYLhk3U?_m^;UUk&pZ^mj~3?$^NCpJk(Zj`9;|2Z
z>A`pnd|4qzkkJo~xsFT6P{R!<-vMV)8D1`^LE^sm)oz||gM6-m&JXLI#d$25bnEQx
zDcGXH`BI+})yFPNQ46CE^$WD$_ojWi6p%!}sqRr?&QTWxbAjwj!Z-4Mln<7juprYA
zv)yU$`Qc%owDZ=o(Y*jzeD_)bm>59AED}M!k8zt(j{BLgR8UKwT6wHr-
ze%sKKQ<|kZRQ?9`h7p1ed(80j%pUIr@g1{HXTSnMn?twm^0WT`!4@BsNlhL4OT{-#RxG~SAb>p;qh|+I6DckQw;Cy%u
zr_u@Xs5X7-MNo^F0Rve6jS~E`)Gf?b?Wx1@0Zzpf0noxeuwri0~3p6$w
z^*}5pwks#~s)^Ifva4Y}BFl9IruyimdSyb32<@N`|D2pEQLVfS{Qfg^BzPoEJ=gHx
zp+BpdC7zHLW<}@mD7psDRC{cX{d+j!T2u&!iu?L2bFM;tW*4(?A0{hNrtU*D_{dAg
zan8a~#jMSC@~D`V_jkBa4aO5GH=bePotBK5n4S5Xt(A-gAJ!gh#}>=8|MsxCKihmI
z+={8fS!7D+2L54H{)`Z2aqGj?{_OtT{`MQTK%I?COoFJ;JpQRpSW$p^KvFuwr6kzP
z;5JUaEzjda^g#Q5k_o4ErIKO<*IZ&0o-s&N*(*GK$TQv&r%OeMag+$3gHI$UO6X%K
zW1@s-uLu8Qz{mHbS{r2PwoEQYfKynX6sBqlj=rWjT$TzeDA!cr$Kn0%qP1+c>3|BN
zd*Bl)*ianR2!|c4&!w-=!(M*R?>LoF=|geq8KKDh0;IsnxwhADQ(RFNzwJ5+v-i9_
zq|}>6RD@zb_tCw$DuZKZE8GeCn=L$R)afW8ms6dQ%~$|8|IzsFy5?$Rb#W-GQNWp5
zBgy-J0plO8osERK0Nie@s4AmQU#EMKEO1ak*HF;#%L1VqS#ZkP@buL1qgJs=ec
z=3CbHHVmomnNV-3_u+M9TQwpzpU@BR3OSCOs|@-?XVdvJ(ME5?C=|oBGb&;45@lF7
z7*42*1e_y>*+A2e)?!v)hqWJTKAvT)S<-tC=(MwN_QTZ%>hy58m!nQEGTXWkL?LBG
zDw&jOPsdgdX0lD6bxR{Vwjre%a5@=ai|@UK@b{0I#T@ik;R>w7Xy7E4l(%56=3u-kwdP24AK&6)rVm=VvyU7pfME7CzP^-mGniZ-gYl7v8qdsBo)-Ko%Hw}0>
z`nS8HJGV-0V9BKD4xIKZcyay9pu+CEjwuWon)wXON+Z=%N@Z2xbs70V^>P`Ph5VhV
zEFOohHp
zC%D>DnCTWc^=CxP3d*}={y|u~rj^VJxc@C>2Rfa@tW@}1$Z1Q7rbwjecZpoMU!-=up9=RB+)YinDmwsYk1Hrn^Tc(M=?p|yw&0wm{bhAb
zR$1M)s-v42DpBpohTBOdI@a56rm)!nnWJ9v0hUQT-2NeHGD1aJvT9gWqZjpPg#+w5
ze^|j70M?F1z72Y%;sL>xz)h6T3+pqq0hOpEw-Uj+Av&GiZIf2%WjRp^S7)n3mksbj=v5xswDh!j>iMhG^V1f-g-i1AkupoYa8cTVbT`b!XZ)fC>Urt>;zjQ)
zO<%UmlSSfNzgWUo^NZhETGIwQ!y~F{ux~I)3@Wl_0C6=b;SUf^>=N
z$VKxPV1DsqjQd?`|D{;J0D_xufvdHj$E^<(rF0CI7?HlG7`Z>`@IyXaUBkr+GEOvd
zxI8Hj7KbDaoZ1JrG=2GsrEfoMjEQfg^KYuBEq?2*xoP~Hy|^BTdI1)mryZpBo{~Oq
zVVZg_F2POBEl#%%y4nLLM|t|g$f?sOPacI(<8`
z>GLtH8)7B1;5ifiq|M{eyfhxA&wrg?zVt1$;GKnwG0qBT=}7l;3_O>;vk-rxcUCQW
zeI)?qElP`goqxjxbH8IW4?L>RySC4}OUK;!}el
zuyi?(($bfqXK@98Exq{K=DP7Z-J{8md_Cytxj*_(^j}Nd_e9OuFMl0AX+Y2X=^Ku|
zc=}`z<^PH)f0wbmJomOO?VrW}Ph-~t7ge?H*PfX@16nE#h;)wLff0PhMNlzI9bq1T
zFT__qQAZx$j$$B^=N>x@!_0t&NF%9b2AGoGI>+FblidnIU@ZF?`b*LCD}Nc5+T)5Q
zipJyqzrAM_V+TU7x?X}nX_FDh%TiTv4hF2`UFv)-D+3*QM`_euA#*h1r
zc#1}vyybV&&psp_rv<619+EC+tbfi!(iMyi)ITKMkFjAzD_hcI68ZY;s?MW|VJq{(
z-@o+J*YOLp{(1UOC-3eJ`P*i+Xb)t_5q2X)od99+#F1=jaVaGFgKzJ@T^+oy@TX&+
zG<2E6=X%l~XeWx3epLRU^CSP9+>`f1Q&IDsgpc)pTQ;7(^68nAhyRa#Fo*I%K9wu|
zd}aC4Qo3&_q(cPyLf_9f1JMsjm+rT_?`okvBoUM@Lt2+lI<=GZ!!r`v?q{F$E-4Wq
zo)J?a?XFLHr%$@ykR7R;4#X~K-u!dUn7q~DgL2<5?@ImgD7X1))aOGE1wL(iu6Iay
z(Q@0_YxbfqLw^e2mh|40_d~8M`|{SjMW@Rb3Uj@Wynjog?B8l1F70`9+6I~~Q~L(y
zb>>x=M5cH~c+3ZB8_d#pziuO@6Ny1-CVlEGebjh;YSj4D7>r7@o=KgNFg{9RMSc?a
zNkX#7kDHi^Kg!OGvr?lc%tZ$LQN*IP>sKQ&X`v^F$VX42h-i=laNaMv#%<
z72@H&IXrw!bSnMDFb_X*d@BCHL!N$oRGd@=fuHmsk2;Q<7?(P3f+s)tm}v0AUCd9Q
zdl)w{L5jeAL8cHl-E&Qxadt929C6Z5#PmNebJeqHnXA^X(ag)u5#IB@G}4JSd*(ps
zaK<#uU+Xja<~qb>@tU8KIO<(5Xmk-I(Q3562>VjxgD41XXWMA1%(`;x!p*8#U|GpnK-|sC*uI
zqMn(y23lnX1ZQdfvMM_xEfkk~%hwC4s5I?*;*)1+pwN(#l_jcKeeq^!pudWrmuS*F
zm>|lZZkVS@T=
zZ`=ClE$ddTUGHr-K|e&z1tp907U3dMR*EJQy(cYOlb#I~R(gr0wB#AS@>4WuIq{x^
z`%FP=`KHH1kI$s~lFlz^U{LwJioMvzVqLPKk7+y#nHaxb(mX|dtnZV>)BZyA((pCQ
zHCgHDIp{=GRn1s*-LzlDO8t{=)$?s7s-K>I;cbr%tFq}ML;MU9?^#fv(Ht1Ja_MnM
zI_rj2`1(QqRqOitwa>i??U6iRV-P;&1R)xOPk)rs<5S}QZM^3?-_$tcbYTo|<;iGI
zevr!!)LpeQKVVzP3E&5RcDaYMSO?P~trO_K`~X81JMtKh`){T2=@jr@d3OT*`al&SX2|l|d1V@r>Zfu*8
z@2PbZGi`n~keb(lDhq3*HGINgDVqa;v?c@*R_0hctuZqXqMUv80#?x25$q!L#pzy%
zEvGAa_TjdBuuo|nSbP;bJuHhI|LZT;@nj7)?P0WJ^61A5RG!7iVFwNf6?Oz?@U@SO
zuvKc|r487ni@+GS47BJ)ix>08yYQw5UtLQ^0nN;zBrUtgWR0?BZVWuq@Hpp-MU5b7
z*v)~w>)~UC5YHgzQS2Niumj;h_#wSYr9KCY1oDh-)K*n4L9dB`H;QknO#7Ah*wATT
zPN^|aK9VAytwnumw#_g~8<5CJJEg0Wq`gvUwKuXEJ09HJ`R4!bz=>UNk0PIHH@W=-
zIn->&&}bvIQI(BD9jI;ggkyKmaFfH%`_Kqm*(h=6Puy#lBqp^)OER}~$RdkJ7Y2p;
zN{t#)|}mLxmL4fV=R9ui^eh?L~Y7Sk%`Z%e+8Ht?zMW51SsQ7hH>$YT+(o0$->M=Vvg(7_0kn7O~B_
zO~GFK3_Fa&Zp*Aq{aBgld1f*4#t(sIQn0yWg6idlchHjU{kAOd-DMa3-qBt=r=MbY
zZH#$9Kj0kTyW4h8Yi;Te8DVzF;QO;#qmyiV#)wjOC^^GA!3#)AqdL&WBDYSoy>FAw
z|5(^?6#jLvcQ7W&ez^FcjWZ-_X}x%{HZ&jJptSWR3+=@vDYhqYd`pu3psif%`{uut
zB;r4*MI!!{^7%gsM;AtKwHShc{v;H?@)B9~`iJs{o1^Nlz!M@TH|*rBMg@D+qy;w0
zc}FSRue!{>R^4m}FcGC*RE$;Dsh>K7i@B+%I|9jG-exdgE0+;s(U~`bmA5%_gYnK>
zk)Qd|yiMtsZ6bfWQ%~CrRugbns{N{)OzT(4GTH1;7GQVHw*{%~(C&L~X3B6rYgvfMPBCEft)kcGHu6}y%2^@A>!ng{xW+96o)A;#|_a*k(-r(DWgi0dBQ
zQECLf67RNxQuHkGgl&@;A1%hqE|w0_PdSBa;fYU<@pA&`e8SwLZp%)ERCEU(>lD}G
zML*8S2{iQqSFy3}vDQv-nz!pvqo7s>I_g7;AKZEew64U3n%$+^zYFTt&jM8!8{E@P
z)LO(bq25I03)FM2P(#iHKB^!;XAu3L3!wcNc{P0YBv|4nHyWGe)s9}vY|EU<$A>i#
zJ^AFOPbhuzr!SnA8DBES8O|EouAS>L?>x%d)--j68EcHI4Yv$!!&dY;Jd85TR>P_{f4i2Y=Wb`n*
zQoZ61XXk6vFX7}3vk_-@y#hZKMLc{kU+ppn-eqmy9q2Nr-IbYlUS;N0@5*8ZysN97
z+Qbbl&9=o1IKg66txM^<;S5N;Q6QoZ@lt!_k_`nkcd>~%6(>Gp}qS`H$XL?1V
z9Ir~0+e?}D7C2&ebD{E)MX$+=(k8aIK?q3F$D&Be9bV>ml-4
z9yQY1RKG;tbY_WoRn&+YoxJJt5=v_cN6%=M&qjN~F30ImhBz0jU|ac*%B}z8navdA
zbaT#xpL%P1J2~foeLdQW4o=df|w+c)O{13oaf)cLZNcC9MTLYI1>mulwR
z1fA7n{;E|$JC!XnY;#IX&V_c?y)|an4Q5t$vf7MRl+nr2X~ea8txS})dAoX-gUv0a
zt1g@ZCi45MJdIG+2!|g|q}bQW)%ILs=KKK)=fYtq4flnUN_NCK^M>JWg4nsXdwJNS
z9JpmW*_fOu-P^EtdTnPX+Rq$_GOyu1tq9_x_4GUn@_BvRD~?;ZC)os7iP1dpf&$~C
z`huc<6OG4o=PqSSFVR-x1Xl8$OF4+0D|IPv3vo$G3-X;QrI8!Y>~iwdiyU5Cu`a`H?O7Xa-q@7_7wrFB4
zX~ckjUU=v!_@-w5O`?umTuWm;-9G$Krql?Vt)k^Hd^JC$0
zde+oCz=@^LKR@5N*q_GVLM{eqvg_(yh0JAAlfP3(FyA)pZWmcRIhF1wVNtJgKbdHJ
zG0yy2IeW)g>u4q10H0*z^zY-`G~2{2E}QBdW!nyS53iqvGa;rY?Vce&pTVr>OiTs~
zC<`p0Ha{m~EBx2G7R$M?&r?2Cp6B#Hp(m;R{ck&q*EVLt>gh~ujp@+$nJjl2!mGPj
zFT0wrsUf{t^7SQJA<@|7RIz?E>T8|DIVX>PkFhOIIlW+L*z$|Kg1)S9=D{7u{dIM6
zJZGyZ9M%9qEKE7|!KCR-Uh)2X66$vvU>?iQ}bz!AEQT>0iy!UlYq3Vhjp>|lsS*BPtr-e
zH@Do1n!-#LV8j^??XOox8@d+->CFQ=nA+ah>*N!Gw4Vb6UO-cbNn3GwS%^N&wwUG^
z&-WM2mI3+>AXW(5P-*fvn1k=gU@7DmS*WexmH}0>7bro<&-8=*S8o|s8*F@W2|O+w
z3#fn8FuFN>8ntA!U^V8Vr)zi2GGs@TF&M4kioXSHERn#9K}k
zICxd1vTcy6myi`|eh^Rz)O+Q?6%v{t>G-a%dhnc%*E#cS3||63%)`#4+OpK?;Fk6y
zc?av4z6ig~^-KM9Wf_$!I&%Xj=d|D0jlKV+unQ}PpJ(_l6Xj?=s4uE){6p6RjZnX|
zMkh;@BoGFqo)8voJq-QN<*PYG+7H{P&ROmMxt+dcd`l4frg#R?ie`0)lCvJd`ETd(
zwb>2?$YOtv{9~2Opz_T3epXoBPr~!_C{~5LYf#A%3tL|J>_?kHU$QLa$#&(f%S!?>
z1a!U%r_jlE9+&#@>Ld~UGuw76k-n_pjpKfdYJtZKa+>IS^w|;jv=s_wNd%r7<4AF=
z)TfA}@B42w=QJp}g}#Id?TTlw%3u)rdUH5JNia1
zJ4KkfJp!iAa&_6VGO{J&bxL^nxcg0=*k&{aQAzMOQz4ZM%SJcP-gdW47e_BzV{qm*
zv&h0qH(`6toWH`q;L)vH2CH!rro}+5muefNM?DlkgS1bx1?rcqNXRk9w1LNG9lnY8(H0#gx=bqyJmp#jUFZ*65OU4cuzW;GZJ@-Exk2Pi5jG5G{
z>CKbNbokdkmOG+2qTt!J{6MDQd}N;dgEFz3Nd-*mt@wSJH-29xNA)C`*!6p`o;sye
z&$&7^8;(=sH_qq68Z>G)9&|+t(Sc0wrE$idhpyBGvNfP@BhQTuL2M)Fgn2{{VTB%g
z#mXSI+e2%R|4lC)#NPALgV{+h9n3Cx=oQgwb`3PuVMTNx>y&6+5W}(NLRl+xgV_)d
z{XNPW37YD&Vtf#L+7lnZxM|*JI`{Y6N_eIZX@AY^Kmcz4$C62ceez?2B#uwrt~
zQxP6PIV%w^gPc_eqYzF+xEk?c2#w(55LO|-M}xLW+Ni@zxxJKXyEpYEiE}A|karUY+4)yHETwp2m98
zS@+J4^?WCiC3(?lif1eUdx+j=^9SCI-|okK@7pAJy=3i72MB}kdzyI0bl7Y~D}f+>
zgTRjSrAg!m1_
z*E8LJFou0-#{Ncp1M!@|7ZHDgc$vWOB)*Y&xxiNt-$cAZ;NK#?nRs5{-y_~lyi(vB
zi9boaO5j_F-_LXaCa9?V3&bB_I)Ekm6aSTmpTLRyHR91;@r(sh`VYkGg!cI}@o%m1
z@h(E-1
V0B+E8VdO~B3<`{wR7?#mTX9jz%FfV&h>3jP?{j7ZyFAZ6`{(af
zy@d0*zd!HK`~JBQZNg8$Tnh=2R@-{r(l{A`7MuUrp?`T4(}G4L}6e#XGh82A|jKV#r$
z4E&6NpE2+=27boC&lva_13zQn|A>LIWz;CAjhYvBSuu*IY<)V0=y|4*(`p#9BYxdJ
zMXXrqP71pUrOcj#PQh@2&!w(eZZ{Hp6hpL?3rG-C%(Q*kcsHzzB2Z^ZnGt#v_9(&@
zQlogbD&R-!G76}>(o(iSs>_D0!n)C;ezdOK@1in>8tD{Pc7?IjNSfZq{B6NUL(+5~iRS%9-
z)s*p}45iyh#cK<=n}$u#18p58A}L~-4_r8PO0lp1ABuD`r>jon;NEJbD}
z-)uQkrl3t7#K}EOET5N==SdJNw`={4-Pl2%CB@8w=nqq3Qr}1oTy#6>x#UlilV?7$
zY?GBrc$w@hvwJwQGmlYPa?&VEaRzfp<-DMxoH-HXkh0zyeQ!*X5viJ9g5zq3DsM`)
z%QC2w0?(W##nId9s)T3B)w;HflG}6Ze3*G!B%_~Pq>s=f0%dDuVcXApo
z^3c7q&HggagIGo)uxyQ6Z<2bibTbF^x|LKsK=K-_lz#Nfk7TlckGdHBsaUDel%-Ik
z+O7IGU0GDT4*pSQn~7&hfKzC^1=K?JPmtRh9irR1#y7(iBB?j){z7TRO6xCpCWnW#
z$py5?3puNRUQBX5;W?le<9H$#RsI@&5?g{?mr9V!ndhN=hVT0YCg
z${+Q$*#PB__`Y9)@?ZJNf8}cfc?O;Ddn1%T>??m*&J%tQ05T2(c(ORV->w6Zffs+r-M|IMJ<%6y2?3
zeSK#G{wKNiP+HIiT7Gl=qfSTt?Z@PmR6}o8o?$eiCR3|}Ig&!{3DrIg1p(7!~R{|w|44~
zt9J8cl6UG^0+0sC?HB=YFz(xw(ZG3fjxo2_s+3?5tCDPe?Pepc`sx%xeICDcdB~y6>%8)4f$MGHEV3iW
z`RdVfT@9sm{THm-;9%nV6Q!m1{EZa@C8Cf13`
z2{8EUxjTMXZ*aX%8(zp8M3Gqn>lA@AdPmUHoPGEpiBNJ<+QS+{(C-z+0RMt^f<*=;V
zMvgh?MJtH?sRlAw?=0b{xZD^+JX>!yY&uqI>1`mQLpg!YwTe!16kwgybU@IB677p12~4lDC-ZdQ
z>JcI;DC(o=W64KmH`U~@C*R4NlGpf9MWT!w>g$V%IO}hLhL;#ze0A?N_
zr7tuPd&>&4MQ^aisd{{H{H@foaSRoeJ6n+XU}?+Zy5xH)>nB_EaqJjFoG^iEg!M8I0q=phhyaraa`r-$1z=9|Ft~J
zJhNp~H$lxunXZBz)mR`lYnD14wj1R$7_R&>~DR>V}pm
z$u`eDt4ObZ1gR6LQs$oML&6TN?X&=pbcx%bi
z0`t+S54WCwy1Av~vzW5;pV`f02wygi_$-L6AC}3mBSfz!D3TDWh(=is8F#JmdT04$
zQq>x7>?|1%E{^EW&*yWfuX%y`TKmrBFUw*jd%+N{hca((SWjW3TP#{SDpIcl_<7Ee
zf8CzwdGoc=Mr}Yhk*P`p*jqYTwGzCI8u(g11ip+@0i%{|qnMJi0x;*{8S8Xc2+_tF
zyA+HGtdDoaeM{FPtlF9#U&|N-d|B(0kme$e%CItfMekZe_JRX?tRd$$zAbuVK~KsO
z3#E`~U1q{oLoUnkST$g8$(pbR+CN4a{i_5P@Y?+wot&4B$+3vl#F^DKY?6;RG_lwQ
zAGKo;rNeaEvR=Pf3hcWtR0U_5Z=Ib^^aqGNA!9hMoB{%ku!0e$?IZZ{k<&q
zdH`t5xUU2FAA6Dcd>%+!nD3)9K2=
zTjN4ZajK&VW);sa-0Gjd@h{0+VLlV=;{wUs$H5}eR|Xt(^=@!F+E;^Z&$TKotGX4=
z4Iw1YQ);fw=u#Am2ua5zQN4DAzn8}MMDM<_BkTHS);y*wb)?IdFa%^xznY_U2U73z9k49Li0k9NBAoa;Sj&nS{0H|je
zjP^}6L5|isste@tg#U)|LMh|X0W;nglC|Kdq*>XfXwXZr-VfjipxKA{H9M|(EPwxu
zQTFhhnzj_RD{=N9Q|`k+tU5Ebz78dl4c9q#-)|8H?Vo^;8RlE
z)~*EG@9UBoDs$Ug*KW(uHr8n?IRZZBAp0JhZ@!K7kPe(+lx4uubz-x12)&!S@mMp^
zK_c4Ayci!*_QNu>`jSAP)Gv`*G0vN@i-7s~-nzpK<2d&Sjdw
zFBWX)V5Jtx-$yBNZO|f}0Md&kdi0tbw*uv)(KrSd%TY#)x?3T-_x(+{WR4|LxY-E03Kx|_3P_>GNPjS_IGUk^Av
z$LD}tPur)6OpNom6s6{Eh3W3}L|BpRT1eMA+7+sdT2H$ovLSL7=A<_~Im?pPsz^_*
zZEA=5rG=5rkx#;?P`@4OwCNd+#z9W_*(Vc%6H@f@*o{pP7x-;>syb!X
ztke`=-bVoc3x53oo}ZC2fib2onPGYH6Y`<(a4y3Yb8QjTcO#nQ7R<+@cj=K@x{aC9AG4pJmjax(cJe|W=e1T3z@zmEfHehV
zY3l2#ibY1yP2b1k(wT_IALqu(q>ZUZUC50<0gUA>fKnJk#I>0W&+Xx2nt*?3%h!N;
zckH4AMj7VD%c56f${YZ#-k6p8F3hu8*|xR)uH3_1D&Jg_)AmjE9Z3_py%NnyyL!pK-+2_
z$z0Ira)G_L5^a})M8LsZ#$bvPY(}7yEGNXf>Nh!Ca*5$ZEz?2lW&>fAhKz?xb}4s|
z?68`gxT#jc-vnuvdyP2TIR$(VLtU*^)Du3>r>|pUhdWD^6pkB}TWZn85cIF-)}1G}qdm}Q%e^I`ag=p|aA4q{uhCA3?q-AjE<
zSJ!`q)+u8=e@5=VbsOlQWV!!Vf?7}i3jS165Puq`LWqWgevg#s_&Wrt&N4|BYbsGN0
zITr*|JZqh9Gku=VgO?`iJ3_TlHJ~-~^5r#hpYykIe_a4ws
z^jx3)g<1hQbic}HA>Aj(2-S-=A^0`Xf*i%MgDx6i5x08(*dgfyw44C*|LMp4jz`}_
z%y(6jUbE!^ztv^z)$ZK?wb)wphZp*B-@5PjU8$=9_kb~!RMN`rco;A?hq+_lV*ne(
z@U_8j9rlT>`!<9wwK<$F`W9A*4v%7m(+v@JyqZx##ZAJC%!~l^j
z-4K&Ax2qqf*ts-2m$EYkA6$*YVFl*|4S+*EXJcv*z|qVi<-Qy~{g4aRds_H(_pj71
zt5em^00YejP_!E2#l}zx8?F0NBGr_6hiS`<*nmg3YRP*gR&=Hrs%}e)O0s(-cP~K31v6!plDMuWjEUV@Pz|>#!|2hHJqiQJs{8AHnQu=
zz4a(U-kc0}c~J_CF`W4l$3U!u#2UE~tWCgXak~OAv36}L)Cgj}z#4uWKrIa=&$X!C
z3$U(jHbSij85p5Mf&gIz_y9_TPl9s*jIgd_1ZmCMirT*x%x$B(KBd5KKy9TN#w7T3
zSasWA;jTP;;{=$`uc(A4YGrEz<PCn)
z%h*_obfa{^eh7{PQRx=|y8i%voYJ3X%!0gM00+hP=QXYe3-^~W-Y=;H14=B`QrfN<
zP`(kc6bt3Qa6!Lv-@+8=C$0l#4z?V4mZCK_lDaO>ka-CDk6BQM*o;k%$qDjBjv61n
z>Vh4K7=NTg_?6h2GX4=5v02h?P~Yku@~_f`@loKXF&_+&xJBBm)cS)|P>rB6JxgF8
zZ7uc4v%~Ie4wGXzNLLil*M5_%wWy>4aSY9=j
z6no^k84v8=d(ThQsQ;KO7#^4Skx3wnbjXQ3vx2<)xOUJEqFPCrW(DxfL$ny{PI7MO
z8dfaXfqz5GbUNTOoH8D)DV5|{g&Wo&9`F&?XC78IOO7aiCq0-sYiUKUcJp-;3&$rT*C(VYb#8_e0k>Q&m@dZ=S-O(RI8k
zgtV1$(3danph;Pc5G=VOLogLadaF%_AQiqZ{i7eF8)5!SAG?19X1?)Y{|Lr~i_w!*
zV!T53g@lBTFiT&jPr^ggt92jAyw6TYj$LZFzgOd;w-2J%v};T8m&MSdT4~t|J;M4#
z35q6=zjS)Q^dtQGu3?uqI6a)5VKL^njM9$iAmY*v^YbJC{0x1jUq2et#a7M6DLB&0
zLGQ{GB|J0XT`I^0oE7!aNK;G>$kb)yfqKz~6qoLwVK)U6+N30^3};y`IbG;vS}4ml
zm!cnY`xe;EQ-L-ZlUC6|W)X=#qWrp0jv_jlcFMASV5^jQ16$c)e_P
z^<)=&n!r9X*c5LjOvC;BMh<8>X(^)=TlGuZ!bl%O5`>Xl1NUgZS+oj63m;?qQbs9HGp+sH+6_L!o!4
zgR^$d*Kx#pp`h~&TqwHl|IYcmxw|i`@Yb14u+yQ#`W$Cvn@VQrSZg28-0X8+W7Q>x
z&pz!6uo4|hsOtr_*FveYpLNc3Lg~i!HwrqBm&|;O?RldFemk#4lak|S=XVr9yNPGd
zoK4fQclvnt=CF=}ArOmZ-KPuAwwz7lS?&nWac<{L)(bVMvn{C$ZErZQnMmp_DOGk(bd$z_sdxU5wavYZNFWqwU
z&j!%_>3}}|+4E9)k$H7Nk%!*v!TAKlz4ShjT2^sXGnB-w3ZnFI0m@{;=P&UP1h`4a3e0iDCCkLJfO;mY8SQ|0dtfY*$4
zzecUkl=D)C`_~LHt-dAUh*6WH5|)1)_b_X<;UyV{YvgQ8Ng5w;>+zlJj!mZvN+9LD
zc@x)!#qWAp6Ijuf=J`GA53*SW{3_{o&07U0oUFB73?UE-31>71Dz
z0#tLW^Y~wY7yfeC$#Ub1;#U{wi~%I6py*I@vd(z-R(8m;H=2)m(;)vG0Y8Cp1CO-q
zdpam9J7jgiLo4N+eV=)s9s+i8*W;@TMq{2HYJJumKNs^(L0e%kcoU2!si65#=Muwu
zSt`Wh`J33&1)Y~b*0H1`I~3qK1yro*Jacvl&u}RqZPd=2O?QBv6=yG%m?i1L0mXZQ
z7wgztAfs3fR1cx6J%NJBqH0m_
z+`BYLYdg=9A(rQ_5p79zpe_w|kix4YwN)*F44jEjnYC5zfhzdI6B1ZThjJrb@Y`PP
z2>&qG@=O&A`)|FLC09X;xA$e6EYDsG7;CbuyGA~AxW*DaT`gGog=HlBRm&C+$y^UI
zbyQ|y6?dUfySvM(Ew75)WDPM}jMW6RKwrI!XEpS6M_YQ;ZJw)SZ7&|vzOes#a
zS0@A_RoTaIdeC2VZC*8r$>F;?={VtSy|~mC2~o`j)q$YxXr4VvPC6{9ItqPzdYmcH
z$#`k!P34^kJIDk&s?2isD)yqLFvVM%>
z78Ihi>J7~*v`3o)k8T2bf$?)O&P-d*R)J08@ADAg7-Up^Htd;O=7Z2ME@zGw;taH!
zZoS{KJCKB)j1y=9uwe(>4Y4fkR-kmk(>G|%L%hKIRx4UBvJ{ujH$f!y{h5d*?e6wS
z7xZ~{h7MDjmJuap>1$$3IPc)p>KU$ukYCd@B6z-(AKfwn@>A4lQvU9y5h?Q5&ZZIS
znNr@)rbuTlr}=1}4qIy8i`+63zrZ3GuO0v1h*?q!zQX@BTdFbfy%AqOBYj1`7nvfD
zKFJf_xlkH!QpMs=by70?$_;ZM5;!2`amD{^+iee8?Pr1jL!)b1%g3jg^Ix!OP29?{)ZUL6W0?lea0M$2sPO7`wJ>$8^t=
z$FUZ;ObR%2N*U`{^0}(Q(qEnH2m#V%GPrc4NyYS)#K$E~fTQZdpl$;&W8?ly5B(SIAt?Srn&f_dgZz~Vr@8@qT
zaIQc#n)7B@t9o3U<%8mW^A*unWl)$WOM^p$YQMs~4b%|h6MHS(pg@#77W%tDi)~P#
zrSQ9e*UccG9PNRY+1(^7&0=p?WT!z|0qdfc&LqA(WbY7j+qU+*tTOw7-Uk?E#9n5Q
zFo;z?w%J)Wf>4m^eSlTs_hXv{&Uw3=xI)nnXwrlj!
zn;N-qvf*vBh3O=vW=nV{dE4ApaJ#eA-1ge-&fef{UX}6Nl;x=(r^YWjuqf)O*Pl{6
z{q0OVzlm@NgJ9okz@FLn&p+ydi9Ru5be@G~qS6zcN@a>J0`S${{ZH7{Ql=jP3HI*A
z1faKA-C%P0LgB>*i9+`{)b>3dwQDeO>jIU1fcFznM?Y=mwxsMxXsMreJRPZYDNDDzbrBD%I(Uy^+}?J^*^HNYrt9N~fgs7YZwmV9KiCl??<_7gJ&V
z)UbZ)i)SlRo!zcG&^uLe);=zYI7=oF*8_L@;<_D_vn&rV7Wdk2aN&E1EqP~2?*mvT
zuDcA%zC>(7K15DFg$UmWIQ=y)iSo@dKpWFT=y69iMS5o%^aOgtQV}@Zxiy2p85yCQ
zexU%YLU)lKbUo-E@CfcKg0y|yAabMdT%og@y92#zz9W{xz@dVw-rV+j&&}SKbOFjf
zUC5n27hu?CbZ)*yXNPBp@CC})h#8Ty_^o3}9M?dCXKa%+6+gf|`6RNhGqx?CpyEIsepHSBU3T!7Z+a!I)m#ref@v;pWd?ru~8w}aL~DR996r)1U*-{D}4Bx!qs+f
z0Q^@-7_03zLn-ETyo)CoY$jKtBAyR`H7<)LO=T4`Lax_4N{>y?wVdf9lXBx(L+;-M
z%b9jK-@wBa6@%k|LtrgiSt^d{)~`vK9Pu~dg6k01;hOHa3eqF`Q#>n=GQ=-8mVXp=
z4cFjEf+5c`l$m-lkv4hA2qfE;c35E@i
z03|~zwxYr5P^!<*e5kPea5>!KP-=iG#PT!e=gloV|8aRD_(l}?Eb8(j;fV_h!{Mh3
zY%BbF619aIB&!;&(kIV`r}7(Icc3l>XFs6slSj(u^BXpJ`3whJen#f}rMh(B2kK?y
zBORwi_>N!>u}%Q_pMJzAA0CQKMTyk_62i8Jb9d
zMi)rxJAR*jBm&Nrpj5`uvPU>yy**4fh*<5_%F%IKUIRSF!MZ!cwg4T}cBfH%*cNE3
z-P@@Ft8gyDpsndlk-pnAq;KDN{AVHxjGY9fzEo=QLE@_94w&*(+FndUcecMOH^AAWxZAG!is&6U1gp=itSp$+{x
ztWvUWl9h|LRKjVhIhQUb4nZD?y?Eq@I%xT#LE;wQ
zy+FUpC$?iRjB&xeek%K3)+4>twvVG;cK<4&J|nyE36Bo>NvYI~_w~{nmQ|RYe-+?E
zUueezJ_{}gEVv+1Uq4DtJ0R`B^np&K*td=Z|V8E6Nj&vb$A<#QScNJUA%rXLr*;=33Tz{r3TN^}npJ*@XB
z&<$j}`L5
z#*nAVaAa*%x1Le91*d*zGtV{Rn(i>hIjR*=W%g)~9?xM%m1(0|l6i+i$#T(U^g=Ug
zJL;5%YF-kK*T`{Kw?K!Ww5xtFuAx6==rX~_jLMk=R+@4#`_AnB8BytH*
zO+ar%7f2=z0S>0Y+PE|=ZCVSiHQ0_k+y>%B?=Rs*_gmlC$0_w_>i{ijI`tP*VC^K^
zXK}t<+Z=qPncl+%L;Y%~{}tBH+`x0)!?FvVVFF@JYL|_9cou-}DICH0TYIF|4ro1R
z7g(z8*jg8Mr!PAUvF?musM_m2a8GrrK^}Pu(^KegYYve{4iUYDZvpMMNo}R5fHX4T
zT^<>9GxR5qoD3r$X$Gw1%XHxZtlb|kz*%wCTp0caK9_zQ%`>vDzT~KONU8Z*UBprC
z34`C^XTlh_V@!?m4BPG;nPrw%z5+5{MyedYL`6
zozP+JR9-By`cDj%AHLy|+V1f{WCC;vw25laR#k^fr@y^@-vBO7I0geQPB{i6
ztcZ!>%=A)uL`OJk1durzI?+h%#+3xD)GoG^kxJ6o7VZ1#72(HVb6E6g@(J
zAJcot?;zbM=@GkWEbNjUU>6i>cebm`AtGJ`da|d04@-ndcKI2)`Us602XerMg<9`?
zp^&s$AI1_u`%nV3EkEvxMt?BZD$({Rq_C|>+q-XCapnj$V}=pJQOf(~vxcejeQg{m
zVMAM49qz}<8ty-e
znx2BwxDNySF;ZHMX`>W%eQZ@`A=s+*JQtu2o=@*J(>j=~TyHJ-BP<1R)HA7z>Aemb
z^$f^dJQ
z6-U#KxoYi{BV?6u>ugL*_+R8Wm8K>9mKkRYaaL*8GJcR6q8d<+Np=NzwaP>n*VES<
z*1N^UsYzpD{`SJ3Zz3ai=%HUR%AMfW!gh7&)eT&h82iu>4xMF033-;U~;$r1lr8<0`
zuzrudH?;S)til6W`Z3rSKMpa$NP}j*iwo+9SjuaC(ZvmyAnu0}alkhDAm|n)dF^a>
zkjMrnj9M{|*?@L@CRj>1Ud6|e;8*m36hlu#4Rj~rNa~%e!7{H@CgTAqP{#sgaZQA7
zaRll@fU;m6djF^!3Vtttr%zkn9%)PD*(Tx~#>6@c?$X&0X7h$Q&eHKDZgUrPptQsw
z1oV5X_UHh~o4rt=)to2ga0<
zNh@ftf>#BsgKgy+WWHTfuZJED@=2WNk1+xRw-rA@>kudc&iI|WbkwblQj&j8AhG|<
zP{!hD&yyiWdxK67XD?FJPaZHjJ3EKj8o>%kiG50!M6^!k`WQ@kpTyd5UclC_$2|BA
zEya}Pv;#)De)B>Z`ZE2xB2}zlhB%SF_*4{}Z^yIk-zFKCt?@4TOS=B(8PFOR&PmeE
zUTqF9{;I#uBSx(CN@c&@h1M2$%zFDcPm%MQnP{V1itgY2rpS%$+UV}00rkLUxj(1J
zS3{PTT+w-RkF>*(RT#xA%ICAPyamh?`A0nEGg&rk`y$j6ceBGb78FUm53&bv$u}Z%7@+m}y@C;GU
zc8v5y&cODOhyC!Iiw|zs#^8MX(4I8|JeyH(Nile
z4kbOCp65#mbIQk9w1*J57^BiF>J0&GXl@i-0Ij`}?AXv7
zW&+KPV=f?Zt61u909Oa()`Av%q$w}s9E_hur1j<=GzRth%bK{P2??yG`)rWSZ3FhpS4<
z4ZZ6#v$6_<69AvLdc$z1tW(l$cGDG*FKp0(l4C4dM3tZiVE@e2Nj`ye7HSc|tdg1n
zSluC6IkY*Lnhq(O&pH}IH9<|h+lTF@!cK12D<4XIS%GV?bprJa)CU^6En8Qq)N_!w
zn^sWSh2NlUR9~To`{Y!1zTMnFMsV+NM6Sy02Gr!I3nS}gY+i%57HRK8AD8{n6O94^k
zoGxYQ4ICNHHw59mN*uR*#^v>s5A9e5GdLV+K(2|{>+c8q4!V{pX<_Uu2q^1n-4A$w&PA(&$&`nVBTZ7u5j}J;<4o2lu=K
zeEqirO~R=+5nEXo5zqt((kF{A3#4B57BVu4$t7pr7L`;FG{5qO|}Foc}H?B
zmq5{Qc8v)Xy`#RUDQOFTst=*L^EBu|8eS*}_!-yo#%w9M
zPTo-FyACKnr~_*KqIxI=cRgk7&2EC5GH_-j;w0{k$gnLvhx52NBWSNLeby493Xt+<
z@+}UcwRVzSR*(!W9Cg{QwOt{*Y@Nh10&d1byNWqdolQ_@lfTX`dneJ_uMjM6ecGZ{
zu^64Cl59z%lWQGQCAxh|aq>*4{ZiK&O`0>Hz;<@uZw&
zcMVXVJci!w!ym-!;D#!k+(UVi|Ah|PPF->hH2btm7A4Y3T?3p|m#nv?f5o%v@_33Q
zN;>@oE4b|nky_2E!d9o?Ry+1F=NfmyH@{@}lsuX5V{+c{@vi=T3#;<2spfromVaGx
z)h^94v{Qj|`0JcKXf1PmcNqAwDi7#(SY4S@{X4ZPv(4P5z9P-}uXE}lcKdy7R_^y>
zvvR*5n+Dq>m4HpPJkH)ZfXh++xP;U&w16ahhWYV{d=K~xq#X>Aar&m&a;_aHu8WMW
zyqwlHtNX6q!w`EeoD=WvCRo}6wCF4S=q8kgkb|$i&V5+MT$l0O1Q@Gdg}9D51f2Vh
zAJgtVeoWuP@&j-pK*DP-w86EScB;dNX@4)hE}5SC@m-VSmzDY*1Ms~g?+XdPOOQ*L
z*BWK4zuu{ov5xo_5c9*}YRX~fO@}m}(l3{D%N)gaEdkEyhR9v}F7o}=06AxDE0;0$
z*EvtP3}GFv`moCo$3tm2sc8zFKJn3CxnIs#z8+;dU<_31vOofs%B7XBFNYUZ7_gx)
zRoovPrY8V~Cm2a>#v|1J<48|%+c=OYlZBJQ6gZc7`9GMvDW)Mui`
zjI?ysY}wvL?$y1ex&d_qPS;>VD6~5rla1?Y#jW&iF8;%$Bfpe!gI?Ep?IF_N!#&
zX=h_sUv2kQa-nW<=Ip=EySVVvr_Mj~Np925hN?ry+%XN4niMB-w4C|w`SjZkh3f-K
z%RJ`{gs5{~QZDR%>79cDtvk(A%ohsZY?Er9ai7ud9!I~Y$NN}p(zlD2KlSlb@lPLk
znldhfb$vcyJjk%V&oaBdHMd>4edkr~B<$vHayYL9la+POD`UtL@H2t%D{`onF6WgT
z61O6O+6Z|{3hqa)NFYh@Q>lR4S1XhOi(GLlUZf1Jyo|+L{#;j|aih+~!O2qisU*1O
z0pu$DRFf0%Q$so+Uk`Hyf0ES0Pr_YCoCKW4pUP~^QLn_GnkVYwR;-}Ly7<)*)DZkh
zCWCcO^mqn$asIQHd^pv^4sAg2Ocw_`VBkjt9}k|X3%J#n9gdN#lgzn%+xo8j)A@ss
zhtKROq#6+_nL4%OyWy@ZdSa5@6>xt3e=^|xi|5b4yDSh3SX2O~O1n?ze+23KX%%)P
z0{x>yq;_y1bI@E{R!#7=q1w_tq^s}*L^-+#OLe-@_77xk0L%fON#j9I#na$1k&*Rq
zK2dp2(XkyM!g`R;{9pa6S~ivI@)5vob@ZZXCpeF_xfd(ZDW<2G&92$EIssCjnnU
z?=s<;Dpu1Q#^;-P06xYCuQRB%-6YkfEvBeL74_CB*^5g{7^}LKO&hloD0^Um@t$&0YQ^QmWEoXz5
zu|_6MgEyAYIu(>~b2_nY+n7F(zP`5tFrKmr?EhFgTF|m^vxInmb=0MUF{L+h3dDVG
z^HJ#yf`O0-CHF(pF&rTYnlL#b;s)KQg!7UiGg(GdyC>#l^uTQqge!l-PeVl>|8c1F
z_n;~w{ZKU)!#t+rJ6njG=woByw!X2vCMOZ@=0trY#s&e$h((h%PEN0|M8FFr@Ln67
z9O4AClZjPO#$AIumAi(ND8-_=!=6nLV=LGD@28>_neX0j#@qc=!k&b5xRWB;^?*6|
z)V7F{yOWI<>JU5ojd1R`6mFwG)C=AQ!Z8xx3@F3Vk|i%ooP4`l;*LabuZ=qcbWkKeULsjPrKV%*K@DXcg|dv-H|IVR5%(v7=6@pMDj
zYUc*!oxD@nBhH7Agwtmo;qv>Ou;XZrXJPzX
zwW}Yd2Ef2JuaRL8cEKwe4{C!{1mUQNUnY6OqciwWJd+W(>S3zl5S5T`*5-FAwM0ei
zp1&~l9(&pZqGf;s6L!J+?XV*~-@k^|aKt{`FzOSFmOa!TFI=9CH$xeW8W!1piBQum
zuwMdWQ_0$(>x4dA9S(L*n3AH;dcy53u-9UbSN?-ryrm+3(H1{+5N$a0uFEngkRV1G
z7T3gB1^4TDc+~@PqH-}ucw5|O9p3hg^(I|q`v!K%zrnINQ!bo>Z~RkjqoC+BJA(-s{%4Hsg@@Pyg
z*QJ1)2cBv;S#J0yU`9>ZBgV+Xt}B?obwTuEVC{_2|66Ts)sAoA
zr3;8J!mCjVc)MicFEX_;#cJ)OAhmX)O|2b2I!GHmIY>Lk5TuQo3wO0cNKHZ3Ua8Vn7olj%V6aQOQ325
zoO>FN?`g>tq1D_b_Ov82!9>Gbg0&8h!j%iN6|PNm=0^X5GQLx$Eovt;)NnF-MI7f*
zJX~f^$jt~LK$;8N{d=3nxheyR42_DP6sdlTHFdEKD0nA
zzinZA!_Xs(Fw+37<@s)<&P8coHxYtJ$I1l2n5|oT2Z&3pW{t9d+4^*>wkvc(XHwSpYxDFtFl5I-rE$S@$9tn~fie
zWbLf62a~{dxJToc+lQh@gR2{T2-g?iH-ZRT&i$)=I@k~6zp=_k{j03{$yN5oORKzE
z1*<&n-YUyd{C*m)IOGJnLrr}-6m150Rl_K+PM$|FYln2g`uJlV7!9~@w*P3K1RRZ=
zj2w-e{UaP5gB)D|9Br03`g%KjO(pOu(3KzK?PY^&zQ@~!K@xB018)!dA9x$yBzs=pI`?=e3=qI@Q
z+yL%|HvbcM|M_3y?zPMMxw~lS$osilMDE6D1)hqeL0jRwT0q@5;9Ufepb*`DwrBAD
zlKr6Qm+ZC${?-4#^87CAIGP5ocW(G;j&G*_&m3<(oklkSZ8U=1mpDIV)c?l$7?qaa
zA7oEb3B^g#c~JtMU2_Ulv%v~G+IQQ+r}jY!oC+M6f2yY~yyPxINVl{{@u3{Gaf6fX
z?lWwP+wcj|mbFLGE#so`#$HyTwzxf-ZpoP7OKoo-?|W5`+qIcvwRs$S|9LG+I=eR;
zc2lT$_9VV5#RJ#5;0@@^8z{BGD`^m|#Rk_(*#8z94RAl*YEwxskXZMd;SIthIH3Y^
zP8*|C?i#FA!U@Sr`?x$-tJtl?mkfhUs14V(T?a;IN|!+w|Xt7WVNC2PX)6JhkqkF
zhxYFXpdTmiKOwK!!48Bd-*|ZkXDosJ_W&ouQ1U*{L+}m>?yI~Ee6;}T8htxGD}6gX
zS<+6=vAOh
z!8}dcG1EDK5(2viqn?xQRRRsci{Bi+SSERsYm1|5@_>HU?q6rwtO~H7%Oir>l>oK6
zyM{HIECJn0)hcG?ViwmF{6OoDxo|3-bHV5_IR?P$RgPgcl|>2ow(*-9cqP`lY^9Ss
z%59zzasp$$@_W;h83tm$Z+%UfLV#A6J@M0hKxyg=b=obQ@_wE`j-eYfhTz#&TmzI?
z>&D1-v}g_bBfKQ1#&;TGO|sA7IJT*5omv@-njU8_w*cCDky+tF3SnP705lPXyhBlN
z_SnO-D+YnpU>!|#rHCcr*s?KT*{L8;(+s^xH|4!=-CDCY^EZBc*9Z|NUZBKHusa%I
zs%5)KoTCfuPL|MSj#$dB5!fXy_1wjns}%hKOPJmR2MDZ_k4kV>c}~Fj$`ish9e7H7
zfa9byfN0>Iv(s7Gg;Xd>W@I+i|NQKbR%^H_gmtGYW;F%8F-Y41&B<6WWdt|8;Jh|0iQ!1
z!F^zwQ4+R^$rtxM-W}11JE*nrmb{jf4A>7tjpc;;c;}TCuznOoOdjtHYP5Tla3)l1
z&AG2O3olK2ISb!K9x-aIJC2C^Ug-$BdO-gO>~yW!SLc=Q_^;X5C&KF#02$Wj0!n5W
z@c#2K`R=|+S#r1p?w#XX$1I%4#uS`L^Su`_4c?28bBGQ7qmskWL-+*q`7mtYyL9mFk!?Baiy({5HMO_w}1d-^@kgxz`MV7L7SRf
z$|SWAa)yePdKJ&8)gU>ZugPTw9!vhcv;l(2FD+f%N7v;+nLd2qd
ze}o%*UZ;b)P%-01pDcfnie-I_ni%(`rZhd=@Xz(&y#p8cdS&uP$h{W*eu^1hse^v2
za-nA_-xwwqsW-wt^OyJcEbq)i1VofyUdM4J9h%bcaMPnlrXP#{$aGSUWVkvbHcyY*E_h-0m_HIud_5gc~Ktm3e
z=i0Z!-RUyWi=5{Y+?|%b%-@vz@~S^Q@4>n}S6z)KOGD~0IyWg7|DJ|twjs!7f>%N+
zQ~q#354Q_pms-*+DBXhc%vvS9Bvft7Wlt)a1dkLCgf=!)3fz`e91{2G`Qc^(_Q@go
z;MP;}dx5RUy|Z{`2kz~>E!UueVwxz^4&z)SlvXycm}34`k9}*a
zs%N_Z)A$X0j5s?O3r-zsAlCOFQ0tqZbKLG#vgF6x@pU3_w>~lrqTy6zi>T4Z@{Cmp
zZ<;^mDn(1`YMY$aq{_ebj{;;j;hqV+viW#Ll=OxL(%PtQdQZKG=NOZl;fG}|Ahp}u?`q%V?rJNzyKwWQ5A$HxqE{+=
zqy0zowA);F+qO2`*5yE?M7cZm@*h^u)c)riO08N+w8PRrAoOBWd3(i*?eLEQ5G92#W
zqFF2xI9Qn#Qb`P!)TZQoz7=oPGP<`(|H;v;SdU+t#MrIv6Q)y_0KK!K)o?yM}IoyDAP3gY7f%#?Ec9
z(7*Hbc1jv$d;4u|8F#mBd&`}HaZ~vwsuASE2LmIG(;&*2#t@9KVSG`R8uFW7vzzQ`
zMlu23*spcKJGuY~&yD-Vhh=tv0Wtbduw&MNoZ`zMF6BUqp^_|fIR(aroQ^U@0pLwF
z2j$`4O2ICfBQBks%_P|uCO`xbd#lZD0_)W?5q4If-ru%ri&%oCP8bDnHWABxxoHVf
zOaU~15xn2NbpK21ij=Xkq&tx0KP`k>0B`TVlM|C?GftKwuT$X7Lfd+6)L2TZEG4^?
z0`cGbm)`aRdx^;a-dI|^4%^y{H94cDc0lv%VsccH--2?HXT7)|0DphZI2L5$o&@(!
z-`g;T_L
zyj{#3bNHh?@;hE5j~aqdRzx+>yB(|8ChDVfz2&WHd><|zU-1IWt`e7?ei2#$L@3vY
zz60OLgt-Z;)-3H<1JT9Uks#Fq*1&1GT{Sr6qcegrQLjmtADN7
z!OJ#ygk3NQa3Qv3?Zjz5IJoJ>?=}@lHmT(HKz$uX0
z;jb9QkG;$bO2B{66F|eTzQv#gUd46BzdM4|1-O}u@0v@i0p-aql=;G*-qGN_?1<>c
z7~V5e%#=%w3uOH52$OnMFAbA=Rkw!ndCFD)jPb?c{|jv9aVnArH@)&mar?TWz*rqX
zowrwpX)e4o8g!j!UIX}w=e%%QZ-BR8m#n@BIDi*mV>gUX3ic
zmlp$u*V-1tTR4moU=NxFP^QBuimTs6)VXk9#A7~zR4)H*2W?=NQmbN=yWj-{lm}?H
zjAo!6{8cg~1>^o2MuXo$@LQ>X^rOhR{Wg!>6P#q`^6+nY1a&JSjm6wnuGAjcNE@$k
zSTo4R8$$?_hqR5FQ|8B_-^={SRKdCZuTT4|f7#wgdxuHtNrJg(^r05TSlSO8($8D<
z{nEp4@!S3%ZEqhJRhj;epEEOO&I~>4iBBQ8OhElOxn-0P-fTn1oWmMQn&D~1e
zGP8}3jKg6Zm4HS>i#B{D+1*mfriXO_1;(coO+n2P8ga6x0TU4w`M$4nW&o}Ie7>L8
z@B8}$=A8T7&-Zm-_jO;72dw7jSfRNCHy=YEc*~X`?U}1jb%u*9;0|=@;NLL?cTDY&0p*AJ%o=&P-=R?3S~_Y?i~bu
z;8Sy1oXp`N7~E}t(2m$E3*ieWKvV?%#4YHViHI6`CTb#JW%(8MMoUGro~z^xL)WQE
zf+g_^iVZ`cR~ULfZy2Uh7h-gd>Kx_maGN6dTEjzIGYPqw?$
z>g1<|7eebcF5J=wXD)ne2qBO$VpoD9Q5b*&(6a@a>dU}Dzr}N4@YmRj
zuwv_&+p$+rO=2vtmtrxK4}A-g2v0jY`;aURo_VAvE?HUj2dj76gD%B<4BV!!{4d;b
zh9AZF^Xh)N+qXxsN4En<2GAau7@7TO6E_7q0WIgtBJCZGk5(CD1&dYzTU%b3ccZTZ
z6sV(lAhVCFvS@L(Ghx^Z&kz)44VG~&)f04=kP`q5M!TqPveo<%l~oXAO=^wI9dZzo
z#Fo%Fkq?FK_j|wmiT2YNX|L((rqf>AG+N$kBSxc4MpcBsXrV6#3>(447b5P!1s+}k
zKwyAD;YWe;lzmte9>XlB
z|1w%Wv14$aC`aJ{4clbU0w;M!c}C4l=J%;$tyNj@JHl+r`u93-%ZFc1)^c{TsiC-I95BU4
zJfOaSVh`m%G9jTX$Gxu-~?p?XnWkH}P40eoO?;lbggkw6y?(o(ZZJ;VjC0fD3)3k^s$BzbC_E$O=+
z;>^+>y~-@KLu7(X+`G$wH{>?{*L7WpmYm<~@#_21(ZE
zUR?hpMRY_w)%lJ=qnX|7GiT@TYubZZQEfa53jT&6@PfLq(P3}za(p_3soBq&-S2pQ
z9Pz%=d=j|y0^?q%`q7fq>=cvS@5TH;qlNTz!G^e4@P!;|-DvBa(QJshyrBV{9SQSS
z6Rl!(4X#}TJtUsny9PQGz&dYC4Hwg@fouNY{vCIb_M7(t{&sWrepNCAy3z6aMs#5ySJd0_Za
z96Zac9KUjRkwM$0+D#g*O#1Q(as-f;=?CdVl+MERW#eN6Zl
z@ADrl+Q+XmRatZSk7dZ;Us!>t7KOOgotCj9^*NgVP60kz0Lo%j97Sq&pSmii$|{^z
zOZPU~Llh}V#$h=Dz+tnI52>_z(dv4I@Y+>HbbW)Oyq!EUMlc)QdVUa7Y;s~>2Wafj
z0C(i%%wNy%TVH4`-dD5NI!C_Y>1~6VOBI$MicNNTe3&iP*(OQ;-OskS5Cr+hvYMY*
zRBV#xA$0$xy@G;+jLz@1L*o^1GwgUD-t+Ak@^?C#F;L2!=Xgl0nB@`P#)?+QD+3t|a79U)42{s!
zUO;yx+OJi?n?>^Aef}G7<8Uu$ALcthKK$ovQ;8Z=ByG=mE4~MlfG=P~$rwOdR*R&u
zTe>>CZF!{+O*)%pALA_M{w3Bs#X5eRvD>M
z&^aDsXU16KcO>hzJMMAxQ7QC&p+o#vpZI1GgbeE_5yI|y1{_~u8Lx^Ys
zx@<&W((eg~Vw3N^(BrvA_MP_Z)Du%DKRQzkpF09QeED9P-g;V8Mh4)9ZqXpx=-Q30
zXGP36FRgdT%esD1)`qFjyQGs_Zr{I-(aRRHw2HY-D|CZ|f*8(fibu55Y(yXR)>ZsH
zay9UMdQhxG
zD&1!sT25*2#g9l&ky`*?rSZLDYXi6{=AKM9MeTOF>!(DV<9XOC?>tk-5^MOBJJSoK&QyEUbCHqmP3IVTmNDTGtuCtmY$;XjX!
zh4p;tJ>V!Z(HyUwP^e7h7(Jq^2~$-ntP$T1j8}RO;SFVNL7nmx$2gV^VlwSzu#MCY
z%z;K97d90BYSg-euzP%D!SOspK5PuA1)Dj5_)iyoQW<$=isO#oV9lwB5M`-T)>CbR
z;di!-Kc1%_1k03H)nP+<$W3&|VG;YtLQpQKjWwI3`>CI=hF#^;rE_RSNR4wnG)a0}5}10J<{0>e(uIE}VIUxDj&fX8--j
z!3RvI7+|vxS*u+Goxlc;HDe#quhl+6d>ws2!1O;%fgQsmh`>Bq2+}HuN-*?)J6Q3=
zTeEKWT_A#1D^es-#4E*n30HTUnr;@Fk8-qfbW
z1ubA^NQu=|4TvHx!@;b_b-%(uDuHQoWETzktX9>8+!kJTqoPoFj+VKt^~I=PkVK@%=aK|733FAi#7Z&f0#Toc&}j
zv`oB9@?zAVu<(I)7Cw}tPs66cscw|LeC(%ZpU02=kTW0mHh#EK7{o>T<Mi5E?fhGR*bgk^X<^eo3l%*r9G5zV0iBI(@`R{5Klc
zokzM3sp0Fs%uP7?CGA+ldS`Iq0z;82*pV|k)v%!<7;DKHHkJk(pbu(*-k8CGzje-`
zhCP+8kp>RqAVZ7!hzheBoi@(3&Zv%gqVI%(D#@{>mE9URg+dzwh
zBafM55K|Kp9@=Zq`~zorFeg#jkOg>&vVrDIFs0Hn(kgxK0pMcI-?0Dmeu8c24GhKp=ui5;&~Ga7^xr@>
zaj@*CbIXv!w#bpv{j$p;3GbSAAa*DAIZB_7iy6qkBM?_2^eJVI#K~Nzk}!C0dD7cB
zeTTezoN6Wu^XY}(%Q&)UC-@GHb06bxk+%w_k~EL;Ya|~P_@$dCJOp>-wRO>{CY?KK
z%&HEv8pJa}y!&?zkPa=xeEL?(>s!5GO7*2x{6^aOp0v@@%2ThTv;tcB?ligV?P+pZ
zq+vckqj4FwBZTXm4aa23K4)5-vg>}LQHb`nB)}@#J|Wv;;@}UJa0~Elxg8oyZE6~!
ztlJBpV=Fq~7XoKK{1K3rue4*|0%SSxw~h~4Vg^hGD@&_>F3T2pet^{1^+;)G`q@zA
z38wtY2HU`CB7Ffq0(NR=Xjh;#a(RZx={{I~&l3XpmS%{RZwZCS`5Tapv-WR}W!%j&
zdv6LZ>mJZoPlAG*=WWc(p|!EjSvXLJOa5lLCx(^a^>^*TV~;?GHsp#1G~LjC@jl3v
zJOn~xeQ0JdMWWWfQXLp{q&L_0YN=emX+G-DlI!Os7;k-tYNxV?MC_-Q#pm@Rc#SQ2
zUq*=FL^r-yK+sB@Yk!<<@|;~Xz<{|LhNp#t5AH>z-ry_Os7L<(NWDd!A}HdBeU=0c
zoWinftt{SGcrh)33@L
zZrOLlo$K|8bW2IDq*aN8PX;YyZbV%`qSf{Pc3tG#@c&=yBJ}5V|F{xc?
zSi!O0JN4D=K1}eux2~(kzf=9I-hNEF!42(Mae0^C*Fdylj~~7}*ZkBTnZhJZOvx|3
zO7>OXQxD>K_4m`8q<==%L^4Nho&mR(KnLu>;fX>4&8GC&aM&y=5MNz-n>V7@cQvT5
zvkx>AC2H8p_r147%0K)OJ8*=u?IyLrLjD9A5jh|s=7H-~hB6-Z2B7al{aV!5%w#$7
zM&dxX16~&kVJAc1NAx9Zk!J3AC(YG4#}Ir)g_};vMvnvilfDQ1G*Vio
z)Bn1~d!D3qg@W@Jm(D(GdkUZlgfP?P9kePZDNJYEvjh#qH$?n
zxw_Ff#4UIRbISTrEWGL44lu*=gtSIQ=3ob>8y#(S!s1GZ=M~C1W7r_mXGP_?!WSbfJn^d|>%(7L
z;fJTam8N*=@}p#nZ=KzTRYvw<91RzlONaFh2}V#z%6Tqj!k<}3`&IH}TM5p0pBs#W
zZ|`~wwqp_|sdpI-Avc)Z)sC+`%y!Z8Xu(f&b1o7O#8~jc+?=1mWvs6Erc`Mbtl9Ja
zT=Bu$an;ZYYhLp8X47uqcbtSOVPGozLGIevGfpdJN7-OvSD7XjmCq?vMlUN>mcdqP
z3M;(a3>mVJU#lWsb9uXsHH^H$xR<`#sT_3}dPQx<=w&umSoR%bhqrJW8_l;Et#j^X
z%Nt6S?wRe^&#s-hre;smRgv#_=O8Q*NxwWCF$HSsLDSS@KN^pNKUIww#xw96&*I%k
zaVHETRZQ9u`If6!*C^Pa2_oc1Mb#GnZmCKS0
zn0S_c8rlN8xu2ZSwn6(WWUAch#m3eo!hN*zz$x`~(m7PsOj>*aG)MjSVNgEC@$qRh
zeri}*1dcv-JXW<^Mss@ls>k#Xi28>L2XO-}Xze$@Z&Ulf)18;>5{O>Se8OR`t|whf
z!v|xr7gyZ0mTD1Y2R1_W9WG^U5xc>>ECNis*b_r
zB^F#Tj|Wf{%#gh6+!5uDY8GFwl`rdHZa;f+9+PLc2D5wLH#ADaKSl?hHj{+1pI47I
zHyk@{#vMj;+I4S<(v`#RadN6bs)1RRM;1BHO?5j)cTg$hS=Qcu+9j7zx{kLva*nsK
z-bGp5DnnKd)5Euu)($;w%4_@ObRwi5nkDCzv(4beE@a9*HHvcnssW{SQ2n|Dk&i+D%Zg~nIsy*WTaH?5
zUuErwqH{`(%ik1I>zQ)fcHl(ilPXr9_5&jX^kwvO4jcQe5fg-v25Db}#1rNN-cz?5
zK|PYJ=9d~(w9SJR7&MmiF67j0Msc$S&b;=bClvYWUgH(Cg&39y=;W5EGpg$}3M
zTDqDM#3Hqz*D~AJ!k_)pQ-PA4SHCAv&}bEUbq74sUJbkmd~>KC-hhK0*@u|SAs2CH
zpnTSU^u^u|Qo9FhZ&7rX@SJaaImb`3mL7s91a~(7Gq_tV=Sw^Gy8HG0(b_PQwVsM+
zSH=Iku)LvJQQp?9AY2p=T(pO9(csTH85fnZq17}dp)FULh&d|f+KlCG+pt4Ek+4xI
zTh0+S8VPLVQMiw_U6e+%wuq5NvnJcvyw^Rf&vn90k5+t~{nH+j&Cn=jfb+ScMs&KH
zb8nDNkF3GqmzQWSv8Eo~9fDLDuMk!XjTZ`?3}LUKN)+a}aX;btt(JxMN{#^fEImT>oALix=wu%Vpxz
zz=iV`DN%MFaMgc4?|Msr{raAefbLYfve|7;io@V8SlB7oJMSfHsU29)?kavv?pxYa
z!&W;}^JO^txk&Qr5F2Dq&?eYTn7RL=6C-7z(*t=p{vg3W3JKVpD*d82!LGtQ=f`DbcAF#T<1&(m8p3%dts(R)(Hy#;mE?90
ziPSdnEr=5znXRb(Wwb78V(spDt=Z9Vfu(pwlAWoV1GQ^nf)a$cJ!)qS@knbdXg4)n
z40@m5VT&f3;5pU^oomuqty35nKpYRLqgga9N+@67#x%cKQ0vGU437*Ah%qkm?)9!)
z28Q?HS{6EFIJZ#OK-5)(y0V~0J&Q@LklQm^W4qy>POX{MRu#u6xq*ye+p3z7J>uv%
zyYQEfRj@f}DN&Pr>;t>Eg;A5Y|C#VUlY&m$+o2j^UD&O2(c5?LU^?W5?d|Bm@RqliuMcec1+%qu3v^#Npye7Gr#n!$xLP6
zXA>xntas<)+~u9JeX=yeNJajgfom6afd0pucjxpqheqECqdca2X29@m^Co-<@OK{kM6fkv)PD)RGKXeY9vN1OL|P@te*1A~UN`
zHM81<2HjRBGjHJjT~>HvxiXlM^OVeHbNxN0btZ_*O#K?#E$l_5YcSi-Mfa}qoNY`@
z5j(xg?o6$xt~wFlD2sCrb?Et>y~@|vQNF)i-u<2Ds#NxZ
z=c-gTmxt|=Zj#mfCunQSWh;A^UE?)o1o+B+@3}0Mz34%lb&O#p-`|^+^03wXdUx5n
zUS+vAy~dqtU)di$KTBo5^ZZO@zjk@EcE(uE0o^@r>{U|C_ZoFdUrDd$d#U6P9*WbR
z^Uq`G@BP*}k=-R*dX+ReyvFnuzLMX1zLQG+>;YY2$@z4@H!CB`KT2j`&kWZTdX3B*
z1$$BRy?ghdXZNJyIpv<8@Z54Y=fq0gT~GndqPyqexh`^Pg<*#D~8V8yIAMHd5tA6
zvn9wm@=OKJpAz!ujT6*3u~0PAxk2|Ae~N+OeD4zrk>5)^1C*NMHp3nE!iMbHB
za`P4&E1$*u>;H+F&)1)E8p7h)@$b8>+Uu}H<_@h3P#H?@XOq{tg9C0+O#3@eD4Kh^
zGs4b;ZWql|%E!Ap9iW=HF4Rc3$l^-BpI$jP=}-XAeoObz0MJ%7r^De{xOYxA0kqO3
z|H=ZFpYNTQB0^GbI^SZ0^n+4izd3NF1SxKp%HO_za0D~4C?u}mVe2+a4(=&uK4zrd
z$BCuhbe)PVfi52xpq{v1GnuU+T1a7&|Lb{m7v=mcXE$i!n)kiwQ7l_RlKly*N&hnZ
zE7>#&yamKXHdHRrsEcRQaAvU!3uM6^||T
zryYk^bF_n&znt&;T61c-|Lf@){;y{j`D;EG>#yaTcYR;Q#y!3?)3>?)rwf~;uYg2O
z{2o+VI+I2?1QJ;zFiRrQnH=vP)_%*Esxf52;~npQ*8`8aG7Phz?qoV43sF0u-B!|d
z#c3x0e0-RsPw}%ehn)<3z~oQXFI<>z*zO8HIoa@jLpUU-VKN1$+-hm1y*O-@BiqtC
zq!FCWo5a^BuB06ipaMS`mdzSzNBZ|8SW|%uo|YxL9Wfe8h9CQ);t^AGMZujVM2|}N6D&Yn+(Nk5`r7*-oZ73j#7i}0k^buom>X|N;D@{8TeEUk
zvGHQ^uqlO8v`M3;<|e@#E_7~Ab_qGNSmAFYl@9)uF0v35zVA?RDw5B*gW|j7x=WgR
zv<&?*TA!WDnn=UY{kr|8Ta(@CRzKJ2;Md)vI@~QcZib6;S)=RG3ioUF>ovH&NK%rP
zigU`^s#be~6Y&S21pqB9A-JBAwUFg9>7!sp`zkn`Mcx@`=&yIPSs
z2xb3~YZ?zvPs3Yj-i)up&w&!wCQ4t~^(^k(xK-sp)9P=t#7a5OTdPRwQu5x~Q_}D7
zwY%i^HL*zTvZc~D8)`0@WW)LOHBLu2omnzvPBJ8#3*|N&C=6ijZS3UOpb_AMm|g@1
zY0O&ar^lVXFSz4MUmEB8ztHJ8F56cYC2QpG0@Vc`4q|vB?Imwx<+DBQ()l#j3~jm>
zh54n7Ql!=wnT4hFybPx)cuZnL7c3Hy&!Nr$v><2Oc6@DD%3p2BMYR}KmuARM${O<$
zlsJGnAFWYxYlOZ$w2eQoaW4^Frq^hK;5+OtXaBCfF@Xxksbn!ClYblqSp`x=Pm=sYS@zU
zSFMa#E4;j2;h1e;b61zIKMk7*;jgEdvZ6@eDI&JxyyB2I=R7N1MO{CA$Ot#QzPkP^
z2ROSE=arIbdzs0t6|Q`U+8*=Oc5A)xMo(>&n}dy_kzq?j4kOdK^HZ<*DG_L^%@Gl2
zQ-mK#JTc(%2F6+@^Q6;uM)KdfGAnh-<{G+%Ac~T9!IytJp5xlS|4`Mm^E1Dm{ngwv
zPd7Y!>ZN04Yscj(jsU+d0OxZ++daS6M6R{KDqW@hUR)r0OLi`jX>a()F+h{aeL8}`2
zu#B)6{%x?vRu}4BbVaK7i(}r5y1(3BXPO2SWv^P{#UZNhkyvOmXmo(PBz+%NMQ~^_
z%>@snGLc$=sZzBg0JPRVMI~uB(`-1uz~5m|>t=;nnA)y-%Pc_CNggFA{t$vjr5Szs
z))OL)aW((EH=||I?Y+_SDMNckSYxu6c{5TLH19>u`J14}7XY46m>Oq@N?6biK5v*x
z!0Djp(^Z1aGg7K|4gah+BjY)u#Idh@cL;|Kv!-boqUT$N$n~q^FoSX4DBXRaA^CK5
zmGd7uO$f9i+o{iytA$W*C~S}}c@#?X6HAEy=BphmlmE2SMYW@SSdmw2^*L*@^`bct
z>k-MBs}gh}4lZgC_@P>F)Xuv(vjg+DQ|I7}zO;-;B}U?)-VbT-Yca=~bs-biD-+aA
zunrosS+zu2z>3`g3gjc*iS^`3CYqnZaskBqau2?Ki~0!2`q3ll{z~(DQSKq`eHr<)
zdPc72>*PMFa|QtN5$UpJIIWk|PxL7RJ}ao7Q6n5&)=;^xbFoJ#t!4OG5m3-_e$T&+
zMpFJ6w_I6spQ`a9|gtNq(p_|&d$D6Tp$~>p9XW#ke?SkB^
zJ^KOAQ~a~08!XRS?f|{W4+6Xm3ejN}5`shiz20i#85*z1bNmPEw*)raa>H}ZSsTsa
zC%TzM%35CXs>20{h?un{&vVN?@a(N;_uczG+K*dKaT)Gt`&}2{Az*%X9egl4Tc-TPZKZNxmEXX$w=!PGz<}R#)n)Sg?
z3sy^lA3hYjh-l3x21}zIdc$8gu!RJhzLf{BWGMFc{c_##i^UuDJ+*V;-l!B%Z!&bI
z>*d<(SpP`X5i(|K36aJb5NTtRg`%r>b&qo&PQMTSrSp%I)?`FEkUhGTTPiR%r_$I?D*K>Rft?LTz#
zw`lbZq|;Y-QNu0K?7rkVgKK%Az+X
zdV0{J_s@U+5PANw=QwfF2*7!r?kOjBhVD~fSDkMDUSA(Bd5%i;G|ODGLhRi9z@8pl
z23(cMGcEO@X8fKCl<(V7A(gr)bDwf)zxVaG9VL&Puq0=Cz#COLX9loEou-D`*R<~a
z^`4dRg~nf=>D~8-QU0<2317^GCoVnK>?7dQ-^M5%A7lQR<>-3~(~22rT+y-Hn~}9b
z{A}rxi2Wzd#T;S{DIw6Sz6?oPVt7q*mD+XmoBFe7Pk&SY?a7NLzOVcFDD0tp+&8_Q
zy)1y2<%a{p%(Mz+_H9_htiO_9f!j~IX{*3}4DUJXOiA7-V*=&d0a>`jC;PbtX9i^cK9s|E{-{f4;M~DgJuU+nOh^>mQ`vHZG*z
zW-UA@;a*_gXP~nuD$aRJvK|JN6kj6kQ}D^Wy=Dccvjpo|{QcgHu=&4g=`LT7(UK`0
z^BYC`2z5UzX@ZtCK2T;C(n^NXTH`cVCu`B-H{O!4DS${_+fYh*EyR*=l=MbR(x+Wc
zja==!TR)5O-~E@_;0hjb4LTvNV!UL{hly@+<
zHSf_k+wzXT*@3uwLO(u?GYhLdVOGL^i`#o>#h2RUIkoe5VO6HzIj2VAJ`x2=cw_l)Lfm0+L*Y{YTgCflW1Kob7CcYT47F^V9Z4ew8PJ0C36B+$}4Fc0*dX)l4;H}
z(n{voS3)|x53n;%G?%S`R^Qaq4Crs9pODtFWW3z#$Th!7e_Q$A1D=fQd(+>i=)6u3
z>e&M(t2ZjF&!7Z*l5pr?!dVFhQZzK52CTl&*rB5Nkm&F4JLEZC%}>Do!s+j%Q-S_a
zYcW>6q*uLM4q^sy1UV^>0CJ|pz@DfVv^;ZTZZUJV2U@J2aT2uTc+#Z3kjFoVU4K8d
z(1W#Q`nN6+IT4SM*3U=(h7mu`o54gK--Vvtr@rxJW*>SP2MXw~aS%NcIlG?nB5i?;Djn8+F
zRy?vqixVSk*i-ml8Cr<{>7lI^=y{{JbjGFsH+yru3p+C#`v)U|Rq!D{6uIZMOSA>`
zEPc?O^H73bcJIqqwqZ3Z2eiVfPMXao&qYXhmVidMKr^`!Sl&3mznXPDRsSNxrNQ%O(F-qE{J&=?!mmn#<4>-8KyPo@J&o@#%n0;fPJA0h(D=+Qu
z*S%pGvs*!xr1MRfRfebYxkSAeRFY9$^{KOgAjh`qBZl_x%4%%2hop6IEN=_^>y|dYK-zyw?m#*e1V!&zjb}=?zPXceHf`;vUZAKO^C>
z#ue>{M8bmDP5HVc?4&13)G_s};r_JT|#&g**1iXzi_E_J1{TAmz
zMkHDv^MJlaU
z{$m2qMNls$eP5P+0Q=>>RXEkNRbe>O!btCTQiHEozd@A26vFKf1%HXHnCzC)4X5eH70bk3O~g={4Iv^VjJ9QO1{2
zeUIK*Ulcq*_-V$Pji@hV1l5-$)t9*FbJUl3?;h}A8z)Je1H|5J@?7Yy`v=drgg+n^
zPEWb>EdKovhSoo9SWgS$R+_<-xHA&oLtQ_3zUi*3xf>Uy=TE+~pDDd+fvhlWXTKNG
zx1AH4B*d{-RgUXv@y*1UsL1duQj{8VdvC-snrzRr56u><_#-(#cCRfFKhAK__Bjr&g#Xf
zpL@f?Ubc>c?j{%TFXaD=bySk{91c93wPdPMPH)WU8!tZ@Gx{d#xm@HeSzIW|HQu$t81E5qB=@gTKh&p?vI=t{=RGCuOS^mOfleIyz7TS&}3@ND(J
z*E(#mXFgkVI?icMnFZe>&w-*DpvUa!`@F)ItsV!jS`V(BYq!K(=WJz!Ggp{ou^zf(
z>HYNDB*m~MN?o2R6kPcavt$C+5>>~Y4&JDU&bb0lpyk-$Vm#5Pm9o-?+)ZC9=d
zZxScOs3^BxQH)L9T(sda_mAISJ@=UV()FuCf9;*$Ub=Jz-~QZjMJj`yh~}i!h;>Tn
zZ@L>jS0EKI6y=jFEzG+4?ef)SMnl+KR!(77hHs44?l2lk#=_1)TOq1M=ZmRhp)DGI
zGUCJp=oGx6`MqYAMyGj!QP)GFd5OJr*}U=aWb=l~g2UgM5dm0=>_{^*!QAFNVeXX5
z(rVDE^uYf_yR;_uUTYHEuAw!FTsv;f?$r;jc3^FKR^(~%ThUvY@`_{46vaUQisb+H
zipcA6MqUq*)+4+yWCpE?A?yd{@fn7a@0k$Hh#~BIc(*W=bTC%)e2mu+*1?!6UQAv3
zAIH1mm;ZUZ
z%qUNn;@)9Y(5*9C^PK`%3THN9IccBsjW`L^d*$0#&E6Rr?5{t91Ne!zZul0z^vau_
z^+KwIkGO=g>|DssWS?@-{dru{Ys_kye9l-Icg`pbLo89q6tJ7JbaVXvlV~2(5WoNjX(=wFaJS0H^D7v_b{2M)E>1Zp9Ra7xILa*KDso$a^9UI&r-pA
z&wh*?_*tw5zPTq8r(fe!O%;*ZRJ-xT#L7Q3hl}2<5=ny!w+*l7T6f)-JlCjhQ0dSi
zxU=q-UUhS>RGfwBkGCR@t~aIf4d~=vN;IPW*QxHt<+PHhy9ql=I=#{Fp1Vo9arT{c
zXF*5G-|w1(n^1SjOxyrW7KTg6MZfbW(KGb59>LsZwM3>Foiz+RU!U7wydPeVBY+K*
z-nwT#kbk?%Xsud)&zcVI=^dkWNX-Y?_8Kl8ajr9})p8%%_#Ucu*%FeONV9tkvo__<
zUNX3C_2X)u8Q-f)D02fjFVcGcnm)2
z2io-U$F||bEs4Lg%?y8=#7U_0hE)dAjL`T}#?8b3u$0|q!&bWKG*^#nPwH9H;*=3Hk%!M_z#LH}w`)J$1wX
z-re8+p!@V~|4omN15UF3aA%Jht#6imJuZRupuCDvhTZ1VafxxlkW#7E-W;)IOEPB(
zKgc^BdSvMgWC6GD>Ye_23ARtb_uGohSp!RuGiq-|TCBi}%tR4f;dJJ{GtQ7$HeTL$
zVKe-DH|2M|XTbRII30*&$;j}mb
z(G2CW^d1Su<%91X7)#@@JL}cqKIn&Unql3d%vt`~%iw#@Ui#?qz$@t??>Yrr5g;xW
zZ&`y)6S+mu>ccaXf
znQC!8k2s(CTG?;APkW^9d`IV;fd`e_*k53S@QbzvQpF>rjR?#5%kY^x&?i1buCzO2!*^!UbutCVVBIDyDPrt7#6MWj~xai#(*Ezc%2uWv$Mh-v8gV)3Wr=
zc1m!<_}i)Z2Jjaf`Z(Hoyr-R%B|YuPbeFpRgY4uwI!%>H9Pro-I#YkbDpndFE{@ll
z!Lfyp9YX;8`nygthCcKQueI-Z)S`I{-bh!+T58kTP08ZKTAcpSV1kdStjgz;k}80{wovpL@Q{kcg;i(M%uR^5`jI5BKnMhT|vYN8s~&;gQ|)#
z3>?oI2DLIp8Itb*<705+E|5~?6yqF0rBw_|+Gx_Zy@J#7zMsM4SV~WMKlytj$F}X4
zWH+_?Xp!)fGhodr&mB>tn7`3D2~W`e=S&k3t?Agmt?}{T(?19Aud|rWIceuY&rwtp
z-1S;2uB6FxZC0_;T$_VgX|B!pv%&@sBhU4gzAVGOk6C!j6R-t(9yAmF`R5Y0L1scL
zkiOWCC!B20)Bp5L;7CNur02>fUyy#8DWa643|$Aj)Z_J7##rFnG5Mq2@!YL)n;klakg}`JNN29B#ZBdR<7_Cm*D%7+`w>y%
zc5fb5^j&GvqLi1}IlKdFCEKGV*L4m&2w(2bzQnbGW~E2=G8LIU!M@U#QcX8&P+~1z
zUs&SDmRRD4>`OC+?xXQ3o&cthC`yB-8a|~g@h{d}%^YiBI+z-#L0ioncUt0?pS7At
zv2D&Rcuz&12iVq%Ehv+U?@!_TK(^Is2&iUe;QLefZeo|>X~s8769-tU#C>iD
zvmAMo>gANMr#qd}6Vo!{pT4KMyF}kp#_)|5eJ5{h>YTNsB4zT6-=I&7=BaV}^hKi?
z(EMMLZ#dXS>K-}-{XNaZY7slz&>y?GwCaQ&Hr^9zA38FzQb^{cxUAlc;SNn2=4>YG
z1oeZnNOMk@!}+KV@OFJPuWbo2`hZD~Usoi7!&hx!YgJZ1U$`WqS_bIx&?i?$F)89W<@j_4qPJ*GW7-vg7
zM$~JZ25Fp)Bh%7oj8=@bV80!s+|rLmx%h{~?oo~^rWM%c#13BH#^}D7^#$o2g8D7Q
z+wob)zo>u=lAce^I`y>^_l1JCTe>r|&XCm~oqvdpM6kr<^VB}!)5eIzG+|Z=rA^lO
zo?0Z$eOa%O&N%p&{e?Wz7stVJFWd49B!!IDELc2hI-z`YK!z7`oxB=JS6_5NuF}k6
zmKCg7SwEVwLp#S^eD&5|bM%~cg(Lg;0cDMfiA^xP*K`>p^wOI*1OA3H7DJvf{UbZ*
z4BUq@J_O%?x}@z)b?I#$+?%aZeGeA8L)&jzx5oZbcmTDgwkfO)O~2Ula9aPekFT;t
zi={^I&Xxe>c33`duY%4_i5k&nUXfxL<1UUlb_y!4Kb?72+wlW*9+YM4(KErt2hi#F
z2ckY&5)nnGZi)l@frZCk&ScOLOfFuHzHI{pZt`XXZbhDq`yiWG{2`zvBXB2|@U`g=
zc*@%v0B_xk|4#l;3V4DygKvEk8AUa%HJwI=A;8%@J80q&MXllxK__ZELNTuhwpsL|
zSqU5)y}>A3pc=}WF6+grUrdN(QvvK-xkB2HI?_{YvQeZ9_i_G;jCnIt3G>PpfytG6
zJLa9!GDJ;8>;vtZ#9=KgzhoJQediRRuSzGqg5(_N0dNd(ZN`TU7|{;=y(5~7i7pap
z#bs}enX_stl-n%75XS*gflNY{T1WFqryZTS6S9|s^PtzN;iCfdXy1?Rt<9emwRH{6C7sdGgN!abUsoTkYK$HSdw?NIT|9gzmofe(;+deZX^}kzKgLXifdz
zpC(4Hc}3~nng6tK*C=Ij&I$5-v2*8L!{YvqXo5`h>0?S;(}B)8h~TFnd;p!7aAhfbReKCN=SIW(o}tic
z2kn+Kv?K4QF2nokp)#kF@&x_IJS(&OR=>_7cw39xWZk>QkkxvH>b&+0DD5`A$hHA$
zulQ!XQu4?HUm}@#$RlaecjSExP5O|^wme}YABCw=pJl@-#h{nhlGTj1>p(AwobC{9COgZdQj_hCO=&nP{=AtbXTi}fWjvAl>uY#*GN3NsxLXEhK
z84=-fnO0#rj9d!42e?{6-+C-
zGQRk=LA6mMpKgjI`6TRJiZCd=7G&rWv1`@z`Ihe{>ENqmjlp!9A?-mKaaZ84tVr6~bz%N3KM$!XD(zg0@)!ZYkYI
zv%q`*1yI}4b&bv>Jy)lIFVPHd<@uHL?5*^E$C}Pm;MURt2yS`rs+_A4xoVJWMV6jx
zRLC^QuWLTvLN&j4<@TEMI^~)dUyy5F@iWyt>GJJ0-*-c<8T8OkrHJWnVhBbELM9gW
ztxBmP>WEIi-~3*aQse(lQBacWNLu!6HA!^BPf`?(r)!-q1{`ZEyd;&aw#0K&V-7OL
z@l&j&0gQ0$3iE618$R`|sf2;chZMuBke!LXz8v0;+5`2kUk`lOEieHJGbHP%GD{({SN^m!Ef1ao^
zZbDndm3oc=^%QnbsPRDMxwu{K|6DV4HH{fB-dXd`J8I7Vy^OQ+zVW7?|J)LqFJBAsoux_`sTMp$wX&i01&QiPpnOws44Az%6pZo*(N%HShB2
zZ=&sP4k+68aSf^6{JFo`Za`1FJ4bczLu1P9gB22mmOlL7tO-7ieeHx-fBN6H1nnJT
z%VWRQQU-XR{t@biQ%f?>3_Y7(1u4g_aQ)INf!_2LpRlG=h
z>f8XHd*>W?eCaJ=HIZH;?`AsNN^wm4u*ed
zF=sjn4p{J^cfk^#WGDZ51u{qjptrnBTKP)4y-EGV-Kbw?s?5QJR{-!UHcTe2qubnm
zYrGl$kQ4_dKU6ri>f~g7TYI3z^k9+B#U>DJuGl`oL^vN%zKu0yRyb=J!)Y8RZalbKgjU1sAx*n{
zyjX%q*7P-~PpgZ)7Q-`Bb6wWa=KfB#3i9fH$LU0g
zUip5y;m_CHZXNCF1AY1S_7(2Gd2T`+4!bsf#(2vxdy|uHGuBe`O6@|2x`pq^+qfUU
zfz&QaO>eRqvf3Eo(p5!4f^hY!g0$s%qteAO%Lfa`JhDyghkwv=w1$-;{B|~053VJ>KCTs4Rjr;Kwm^oO0|0LXbuQ(N;6sN*+
zAV(c0Omi~6KHO*LzU4Nf#Miloan5lVrFkH@Y@?VUq)t{J&r>GUbkYB|u4nNUt!`jK
z_XY8p(j6I`<{z{N<(ka>#RaGG4B_qY6iKs8{dqr5Trgrmj7G(v)hrRWgosVbQgi?4
zWjx!@t1RXFEY0ipgR&I!ysUkN5bRXIA6R>kYr|vcYZiPKf9b0maiz)MlOeJ_U}e@P
zaoRk0=Edvt%o|*v#AT+=;6G{D@EAqk*zhHIHP`&nU4h3kNeB8a7OEEa2I7haY)o!(qt2)r=xFPx970bwk`z`0YiW
z{dya(xj#;hXdI!rfB&p!Hmf(SJpSga^U%)J&6@1EIEb0G@0G{=k&mx-zVhX)CtKeP
zT7W!X-EVeWRO{|{!TU3)E?z<7Y+-1e(un(ZKSj}#5)dlSg@&c~o_U40AP@mP$SQPWx<&wJy`Kbm6~9MAist9WJ%
zuYt{8@d>&7ZsV3b%T>Q50JCOXeBrhl@_NbQ1`yr&hPfZx6>7QJAv5)=?t
zhwS_7-A2@&*CeI+;RQa`bp$U45ReS?i=;u<#m&1x4eMdQ7LT!e!?f5S94uqq8uRNA6%0n&6
zc?!+MQ=zkGam%Dm!UDKaWu1P~v0yZF@~frqoc`+c9L%Z)5Z2)9pVgr@TMO27epNi#
zQEy}PSFiGg2?cKkS6L%mE3tCd$OEzd)H22p(Xf)U(>dJ)oK1HSeRfm3_VAtain+T+
z{4u)=*tKO+%>)yj9CT{PIbD4xbKw41(dUTLzCEc`uOb$RFOBZ2E3?KfF^mfuV7SLJ
zzz|t5z%XWn-ViZfZx|V?H-yj78^Y%44da#sZQ)r7V`V=Hh+?Y0oS!GC`3UPF_L}nV
z=Dy_*r9eCMca(!|&a=A+{}${QlVemnnfYtkq+ykmBINTUDRQO;E5G6&lautYlhr@*
z1fx%akGbVTP};~e=LuPSxbjfz0by`Jxb+}Py`v5Dmm0o<%2X|E2CmgVr_!OlzG&~5
z6_{nCi$)&$SPm~*L%-BNH%l9VajG
z%8!fQ_%ie{!a<>5QcdE1l$*NYu^RYqSM!{eFb^LBJdw9+0ro0d4rYWeRVvDxOWc6p
z$XguuNWysQBWpOm^Gyd%H{s=r%wF?uc=x3C4Pose`sdaTqQt`Fqv(|+>cuUtg@-JI}Q(d~NhaL0cT~Xkg1`Z9%g&q4D@2Ucq
z)g-U;@UwW=Y?R*T=3wQ+rn}*jRyTxtcG?5Ua`WfJqrhm`w!PAv9pV{8U}FQmk>^bw
zG0hz1!}!E~Nyx3xpG{&MXQ0pg`cTHv(Gh6+{0~beo&|IqP#+z4V#3J>>mNEj`CP&`
zM1j~{Q+4p>7gfn21{r$t)RJl6kp2Y|MxH3i4`oj6=4$dI>-R+o4p;Was~@t%^7@Yg
z%MFdp2EFwZbY=N4WwhtI;-T8|!`Bu4yq4s0+YJTze-Kt*4`8RVQ_9!QV!21{k4D>G
zV3i5bKSE4XLAfJHP=7j5lEsK-m3FfwnRE%A&?BTW!n?2ciMBn*istST{W}=D*&!ZL
z3V|I=ce(ffy}GL6Sv9@S%W)t(^a@ArHgkO0z;~>A&}Vdq;c2xIQ!sXin|_vyGP
z_uAdJy8kgmyMkjKzUo_>)O&TUulK{h
zb*zq5&e$v0>{7m10k1;?I-HrQkHA8Y18vJfsc-p#cW1q4xHE!aDHxxvB(<
zd0XPxxY%g}6UV*}&-0z+5wje=|AZe8fNR8eepUqIdDOD>mtyIrE#xdf)W2HzC~ohd
zyuy6SS9HCp0x35r#r^z&oA9Q8^9*|6=Nf8a$7R33D1gt0w_D6XO}ovPjiHq?R;M%H
zTFQ2)Yq9rC{&NyLE~+FFoW+hZo2D`|wYgz=1hm?XfY&9Nsl?kqQ!zGt-kDC^R{WmE
z$iLH5Rq+458us=YjN6D4QRA?)9i*Y(nF`CZS>O^3Zqp=-^T&}FUP>qZ9t&E_>bJaG
z2Zdq-$lm-65hnKQF=g4kb2bKiS{-V%CaBnc=HfV^_#*gQGjqr;X=M?7{vC`Ep9+7f
z!tNqZr7Md%oy4n?Yn0;+94{L?>xl}zD&=}?Mdqv}&QY`GNuwB7JE3}MWYEEo*zkni
zrqH-zv*oaKBe5;_-AphK73WNkC!8}sZjK(+&XkvWm|?jx-2~l`j!+|U{Vj)OZ;fxo
z%l;bS&mx^+F^h9vJT;!iT9Q5`rVRpcBP`ec278OJRh1fJXzZnS=%WN>&Y{_@LXVOU
zSW9C&c`f;FqmwyuHFUKyN~Sybol3X2^d>ZhJCqTa+j!CBP**A)
z4YQ1nw@1UKeKwmGSH7{3iEfKwxt}ObL)!jW=vL{LMP_rC2*S}PiiazZd`5a#=flg8
ziQsvw4i{*Cg1ikV_ZE<@M%J#1TMgb@Wgq!Y
zN%y=SIrOxnl_urbT83cAYSyxl7s~P_k|vnuEiOq<8z+vdO?5(dqa-U;&J$7CT0yxek1X|GT+$dze6XGrKg3xi
zh+|FQ{Q{og@98t>_y1K>seb^zTi~hEznf`~L(7CXnJF2MYbv>Bd8N4k=*7hMtaO+X
z+{8ZeN~f6Ek{J@TW`$8bGN+TIFQju}F~NgRJw|pHq*EO)FyV(_-LRB;X#zZwoL%I%
zXz0#K&lbeIlHYo-!AwZwf-a4fv_<`z>Qs81z3r5tgoD=s!k#UPvTXNV?KkzSEgi~H
z0SxPdQn4>|Z5}=d31(PW8|>FgZ$W>i<-JyS5_er%FJqYR+Dogopa}Hh*QU9n5lOcq?9a@m6IVysdJOFOPmcUgB9qWyL;UIVMql
zt~9=398>-E`P8ptt}=$rIk4vWKjgi8T$E-0KYZOYbI&k{3XXVMDs&W+Empz9>K4tw
zFvCeh<&;sWcUrbvYGvhjV`Z2F42oa_B8i2#YO&QCtj(^wHh>%yPvj~d77ZPh)Jik~
zL4n`FUR5?+nZEb7!O#Vk+24EP@o(1K?ad(K4(A6*u0S>tM}A|HXC
zl17mK$g9{3*fWpo(02H}mDqYcZxVJLg25zFi#MG!(f*G%X6D)-*!
zwzSh2GBcj8rWSVZBWWq9k*b)JA7F9~^_zGx_|I%nK41eGpvH)DlNt3vRzw_3UN{+1
zSC|P-UmXQIW7C?Wu?3ap@!Cr79CjYLpAIcp|du-^X9I}f9c|u-QKOqCEPY%#dx9e3Z0hgH||ASPrMBzgRNKtauqN4*VCW;_2SaSoGNVuhjHOgQBG2zK$0
zZh7tz4zBsy{dKnnnbX&akabr50N*gO`n&7;-H#PmTJve*(~V4TmuG}af2n6-W~(GP
z2RR`Tu~8VOjkkMegoh;_$4E2M5pTi}FE}9<7_eEhqp*zT|2O3Y!l2EP!TW_Rt2vzi
zzEV-B6>erpmKG@2U2&u*o^}YEZQP|6RQ`sBKg^sX2}?|rMmY!Q=z}pa1HMHM+12YO
zCC;SzPu#k%HnQ-L-KOJ1Y;#2X41B|`xY9qNB&%_-I&Z
zg3Xw3#@@geAM&*(yaUEHef!0fQVVp77K7S+3)p_ZX)~O47DE5K9X91H@NvtHI`5p6
z__}lEN~)I{l2e`oT^P?4R6&(0sg7$wl#6YT8Bu_b&x99nbvJyI@A*eI+_OZ$GkNmD
z*M6pdRrpRqRMZHMe`FkLmF#{vcUgK8NhNr5$!UiK7H!F)ZHgO=yeo21FYtFv4L`WK
zdUy-*YWUEo<#V}haxJG;OyOc1k-sH>R|sK-(?WdU`?XK)A7@>hcrzj5xr*n;E%;yo
zII%>c!*+{h_Si*As&aO9*c&Y{0(2gekx|{|;HO?RO0L-tOEC
zPVWl5$V&~JI(s6AU*In2Z4W;gnDHv!7~H`s4A}I0K;DR}|cIFFQcAPSg*BU&Hr%f*R+*
zHy3*QN#I3#!2R~v(aM%g3XIgyLalSXRrGP#y?2sc=VWZz6aaLrsnprb6eCF*M5-`x)xIDPl8tI
zV~ShCO^Jt%+4c(-mSdC7vs_OIOobm#;Y?JR%}6P?ZK(41?5X_R>%LWloe69ius5Of
z)wvJt&I5H@2wG%u1t0%}-_n@%8}KWAe3*5u)MR*>i^u*4ACW<~*xWJK^Cu69)}g(Z
zeRR57)yCg2w42}V^0S`>RWZi*OHJxUi+q#kDAmN;}8fiFNI
zr52q~-65eY|0O!%cO9%nvq?k#{@Kwj(V0aA_0qZE6H*ucEtV@
zDr-AfnKf0Ks)Oa(?NX2{?H+8{r7zrJz>s#d?u
zwmcD=1<$8iqd};fAuU_W#q+Tw4Xq_OTMYG%|;0?ty$=*-Yz6yBy
zj8$|yq}vBEA+lUjX-JZe@(Np$B+Ws^ZRyUe{xJV?_FS&|vz>js&(=YR(Qm)rFai5+
zDm!O|=c9b>E0(C1xXhx%4%5U>`-gjlH8>>Ris?m_mmR2klhu#96BrwGI4O`7NK^0I
z&3O4(r7LE7FBfananQvG`kB&bRvj!zy&=yKjT)dKlIL&6EsiHjLX;|fLABFMBYaaX
z0WEVX(F+c-BPEd}T~Z%RBVUHkpGC$i$I4bY%CpD|kvD+5iRwZuAhebEM|?8*C}2m4
zHU(Lfj*%k+A%#nXf=<~}bAz+&ogZX0i07;>)@Ev3lsm|2e$sz6@r8t7%!(|G&kpTCVUZ5((z`ko9x_A7c5+%U-jfmKhqeeefl1)^bI+U0>&
zZ#_~?JX3FqmsZH`00*8CUTNu&RG#RN;H}gFp9hktl!xg_FYN%$)%ZPl*Zno@SYGtK
zRxkJW+;Rk0N8e(vXJ$N7_g{albuO&I{^a{c(hT*`t<#Vnk<@dCP0-JHX^RgcJ|%GB
z6gPjXQMu*4fgS~V)j5|Z1S*#&wElwg`yE5v+7U^uxT8=UixjnuOA*S
z_1c|3KFE!^xuSq*^|Ez3dvfPMRZ@$lKn2s{dq+|q$s-S5g{Xfzo>O65*YjDh3f~iKN?AZWjYxI~
zBhna;jzVr{)-Ua8KY0;;uN~&u2
z>GscdMgxbJ!$SrcI1R{O-E7e8T`OdXKDgNw(U_TG)JJQVx39Tr(O&|L+_5eitq6}p
zkSjQ^c)_<&VwcGz(Fww^LWy|i)PrytrA^a{@m=jNojl;Yf3~K%Tcir`E9r5^0>Mo(
zO2{jMcdAWYl)Ce@t@TO;TIiDnxZAmqpvWg
z3x1bnhRh;2L}(XOWpM{Ik>GR=xa0+WrWC5`M$aRL8eX08I&WyrG#ccJ#@DsTLrUKz
zii7C*YWOK1I0e4}VZMUx-{*h}KJ~4xfkyjmm-zQb8nb(qKeDpy(2mB&{YUDL)i&3B
zZMGgcQ}yDx#Vt$Eymso1=7?ImqE%LILpJc7Sve|Mt4yeGV4-MRj%X~Xn8Oo9I$eA`#7{w2v^H{1LvZ4v0_`(aNk{Kz;
zk@RGizv;;af9apNqozM;kG^L8(dvF`vTlL(oHe-Wi*;z>*T|$9$NS7WwDd^O+QLu3
znFsceB_$*5z(nvO=d25?uUURX+kwCK^+HC|(GvX!`rtz$N1%0ig4%&!+cU_4q*&&g76_1u{LOPnIWiP
zgKKetx-^FqUMr9}sPCVn@1HmL3onDeSsbSjmgtn*vShLepNMz=gu8#j$Udn)3VL|-
z*t&?C@Tz4F(%JJ0i+o#NecwuFdcZ8(W!of&Izz@t%Gbwy6%!P@F;*UT^ZCVT$I>ER
zsCXgB(yW^R?D*08ng=#3LMLOCt=5PdmZVK8hB=byT;nNKS2HR~CdfoN(rk{?spe_{
zG4RLootiSMu(5&JI*X$G0rh}W!Z`8X7VkvXX%sa7=Fl}Wqnorbp+R55q~uyBiHjg
z{(0o+nFHq~QnJ3w2kkgZBroHAWeAy=lhT;2UGYkD2sxe0Kyq
zn{zJoo*&z0HLP+9Ai9?=yBlcYEoVc&!LgGJ)A2Pe=g*leKnAZV!zbIkxZpj6M
zs&E1eFZ9w%EGl_|M6lGqDs-$yw9>yAKggmSr$;o>2*OKkl<@kAr9@|Q!x87CvdDW?Z*>fv5G}m=D*IGlnRQlD2|4$5
zhl($i2qin1=}8&$lex|gzFj$Zm)3r9JR+LJdCvK2VQB4!DDA(uk=-Jx^zrAmh;6t&
z+Hu$P1iWwLI#{E9SZ~^N^Op{lT%!<#X1Pj^m9(%KdE%;&F|S^()X!Qc%)iW(@vD=C
z`G?r*G~f&`wlv~7S%49
z*Yx^gS7!2b@aQrbH@mn|SfF5)(*wCMMXSa?FH9Mz^_B7$%?&Oy$xmY+m+;3w*S_)68lzH`G__H$({1W|kX4
zHJ>Z%lO?L3bX=IQjSCA~$fj?Ku-odY^@6IIDW$58sffhnM+k|PBg1lD*PO}0el-N}
z=m4T-G;$Vii`+HlOy8LGf?_bTd^Smh*UtF!-j)MsVMMb;c=rq^VtvLLX7RSm(Wjnf
zT*=^zUHFUDL)VqwsMIn11QWFTN7j58@!^QvV|mGW_T)~jFbDNyI>)nlA7NG`w)!x|
z9Ic>nJvwjmvEs#9t3I>n0Zp0U1&iaM%aZhD5xz9j&ZbqRbZe)ZC+X+z
zjlj85i-;7=f}f18|KPC8-)84Olzu9QpPSEI^{1U<^#`0{yWAxQJxeqD@)ZDBZb8bY-J7+>q!Rmkf
zdP2fG6^7~0?szu5(1iG~5z+EFZ_d9k@7RkG$rZ`tQnn3s_7Pt8)znnId2US0h%@h;
z3T>W__nMxX_w2@J<X7WNC%YBi1F~=Gk1^D@KJuUZ9~t?RLUECdWvBA9;^B@w$vh|?v|<$VZgVk;3Gm<
zHX1m^kd@|X&X)He#d3Yv-B+H=87i$;m@smu>?@mV-tM#Xu4{=~J1hTAbE@(NMvYLi8ORoiDnCisAv5xW=9zPyLiamdrThvr)q`jZ+BWoGeY|3s
zlh+T|_{jvWK_WyDRtjDX%)MyTAfn;7j-`UTJjHd>2&Urlm4p9(!W5rs&S2iJF_jmSgjs$PWMMnRTVb-tM;5^_|-40nfTHu*cU$GHySnvi~ujK1A
zLc}ha*tTKM#;~xXgn-s4;xKd0XC~zA1ai
zUnRuq_E9OfAgV*ND~M#^ZHldoG|)F7LxaQVy{U0aw&2zJ2COXQX5=vO3O1KRwuQWU
z2eJUHv~JzS|L6w&aa|ebD&E*fXLdPu`1Qx(DU-PuLR)?4j$HfISfLjxDdF1?=M2HcITYi+{Hfs~)>}(Q%0~7CeI0+)eLI
z(F<=hvl-Z+z?I1BmsPmA670%?>G%^i{V}W;J!dm?Cx_<<|2)Z7FQA=B_>o#$!3*c9
zb#OiFjt796@IuCMZ%(I-d)kpc=1B+d{fNVEHuu`l>jmx#MPn;F2;`JQaR|N%{
zOzT*^R5utDcRcD7%h}ePy_W@VS>TV>-(hX$J`tMiQtr58?;OKIbB#Y*eEdF{q_1{r
z^*0Tp-6p)VdO?Lvjfi;5Znf`DR$=3G
z#e2Q>U2=Nui{A%sxHFb*xL}!0-|v0Ic%(Pkm2tL@Mx(O!_6rKx@QPf-lYa(nC;9?f
zT=)aCAZGJ*=e=iSvJt!wKe!@y+t77=bq;q+y-8nQptooQeDq?{53c_lYkn|l3S-^N
z9~U8IxAgXJ%_(dY_$*LiXm5R}f2!Y%Vzd8FExK~{-lFfUu8J*y=Y!a%tvS8Nra5^9
zKllrLQPICd{2~``yiDKQfSj`ox*ybO$OsJd(@AQ#R}x0LHf_AX5B38#wemvlaqk@#
zJkkE`et+H8O7JkeU_K5U056j{aPP5(r^P!JQ9{Xa*|B6LJe#MVd94|oLgruzwYlMl
zsyUgJcoB~%4U+ej8N!mA8J{B*HAq5}g+V){g3<@_i4Vr*+8{r|$KCjw*C@!|?Jrf|
zjI!{q#=<_WL*RWNU$iiS;R_CB+-c{ywZ>RpN2_+#mtU+Mtb5^0K6dt(U)ic1h{ms7
z^f!{c!s|!tR)6VwbWlyP-sQ6HKW4Cx81KQ4@~jz`IQ18(@pWRauuhJ8hu|proy>%+
z^;>OQFWLE&UVF!hp~gAImsE-wz4q{t(3|&;nDQfU5Z*(SMja#_$TgGn!j?-CY5ho?
zW$@sO2Mfb4OS(tc6k0uBN^i_|z?UHEn!VBf?QY%P(J|Py@zPyt9nzQS&k~CwEDN=-c^3SY6foGO*^(Ouy)0tC^po^oI`MS3Yx$5~Jl%7^X`DlSR+rvp-44IYu41n~
zI){$kV4UL`b@}Eb2mGmFJ@sD+4f}iH$K7>s4LRY>o{G4(@KbJjot0j8c*nuU14kN;
z)iv)sQ~lz%)}xEhF8$YQr{6dkoD)(%-3%{IUGD;8j4_Uj2|pu^@)4%TE{K+#L`n4Z-zUtXYR(m4~EX9Axv2TLuv2DNfYK{EI(jT|r}y^$;=o?ZpzhtaL2j9ivRn~V(!hZV;F6=i8xk|-J$o}D*scl<>7For9V9G)EuBj~in6N=H
zN|^VX(Ut3#X^nB22I2M{rh=5KZ$X~pA1z
z58@!}8AMrc?HvhPlJ+JCXrNbT!uo%)uX6?KAZFi^#o5p1YE>=0+F9mFv$yWGZ&BdN
zU~R9%ty7>ompl@m2^_ZcGdG9*jdRj$a6q|ex$0g1!Itg4@KFBkopWy3W+S%uw
zV`qQk^t8-z@w3czf2YbP5hP7M*!F?HzXr{!z7|nozblL82Tj?Xob}}HBWsQE
zvv(WgkE~tkk@X19koNlSeg`O=n2W2B^|IyPWg1+!?tVwJbIBpmSIWCILQlO2`B_cj
z*ggJyOp|#egnhr|zOa5(f?u`2Dnv%a~)+n_y)hdBN~z%7s+7#5ZhyX7aY7
zjy`(gHLK?tP5X;)8ZM;Lz4F|Ub^P8;L+>b|^ETEpNp)S=1=B}T`!xoYi8z#dcmpfv
z&<2ao*u4Q7J`VDo;)cvV=!OhYf|edof!Da?wZekmNbQi(3fm|KK;^@vz$+gnX)La^
zEz^R&z0=JW184GTh{Cx>&Fnv8gU)>PT7E&XEA=;L>0Osu(Q@zkccH-q906aa_{Kw&miml$&HC5>n*mNgAaM>Z-ke4FXHYh55CK()^_*XeVQbo4xo^u4fKqi?svYr=W#uLK^{Yg{4cELJ9m!UWVIys0T&hZyvK0PdK&>f9n^?}@s@&B3kIkQfP
z&gU28(lgv_JTvG|T4TIW`#vxH6K};`-Ha!q@_F%o+?mZ`gWl)DyyLX7LL=W!#26gAvv6w+fQuL@Dkl=SNl5Uxj{}1(NLM%ywHz2Q1!HoAN2G>;?FB
zUWezOjEmZSRMz6QUAgm+gxVgt9IXwvT4cx-zcNiTRWk}Up0A41s$Ac<-3`#lTGBi=
zDfjcyQQ@$LEPUhFnl#;TO_;n@Q=FGpD|8?ZP*+iuR*Tp|t{Zt=?|;Q@G4j&E&*dfc
zcx0||6vOiUxzmF06pEH>vbmL;QAN|Y^*vKVqD)ng#Vs-mFQ8_hO(#))VprVir)w(g
zQj5%k_q8O%S~eWL?#pJSe{pBV05of)ug43(!hfcnwCyzH`J0^
zS!&fb{H?T})a)smUKCK9T5Gu&5N*4Lp8eK64}26^`&7J)!}yZc=rIX%Yn>Vt0}&Sr9;e32&ut~-meyt&+l%xt#l=251d?d-5NW9CX~3{v7-Z-L`bHSR%uut->~`THuwkFw1x;bih2SxC{w4PpPvj
zcwUVZJpt9a7JQpWu9+zC`q$L*sfd^vXIZQp$fpQD1p3~)uE$V;8BQG-uQz#EsiiU*
zt2*F#*k_(Bpk%*|ts)yY^}zoywDvOhn;G(8^XS9$U9W20S=3CH(O3Ij$SWkjB~w2!
zUJBTX8Vxs|)0Y!gkZwyH-}2YRu}@x3XH9Rca*%gU?5TOj<>!LV%xO+OwxB5#m=KaP
z-6qKRVaQhCiNDd
zE22a%)c5I)HFfaJmdx%3h6d)p$j80zpl_G@ed$O|vlv{1y4uD0N}J+%O5-vr#53PC
z)Ex9>PjgYLoz%uN)xi98&;&O;7o6TJ;x|i3pKzAi^?lAF-pNlru$N{N{%n|e(Mlbd
z@LI5W@BwiSfxVWfG;toGjcPFJ)$#%vQ5T9YAa4!q7jA66G%&Ajo4Pw!9{K#v5m#;~
zX6(7@&#ROMKyJttHYyD@d>*Ro?bd}s<|}BEqfT^8qAb=*5h%c(PgO-WZc!HYW<{68
zqP(D_nh@J0gvSF|jA)lA!px^Mr@tlW_{KfwOiS3}0>mGD22ar4$uV2R(eH{5NJAtG
zt$eoYw<}M(l-_sUR%<@${6n5b)9RkmQ+gix&HcEbhD&
zz02;D@QTHXMOoV<7iGK{3*^?^iSwlm(A63{i?l-;hbp$r``Lcpdh?!g%b29g;cVQWD-zA5ByxAiDTE
z@PF`wec?q-sE;PT_B7@gRGzJvy;8*f$&cfuM=jO`P8c8v*r(%`%A
z2c%h!0&~;(nDay<*otTOB3tFI_X9MaA9TZc#SD7mr3`%asoBUagsL^8`Iu$M@R#r(
z!pBNB0IzWi=2$A8BWfhBkCDB5(f&K}2^;DHQo;2|N+P%9dg+YlU(*u0bKbol4L`hF
ze17=(-MIP|xDPftwj7@JE8d1KDPM_o)%2DT-}AtKn#+g3DbgRmr^OcXeY>6L+sj_H
zV?`c?_W3E*b_=%;ITNzDePi{RM@C3*WI=rzfxli%~R>>*F~rYt`5-Y
zG_K1v94CP_FG75Zjkk!s7@I+B|
zA@|*-ur$
zZ4us!U3bQJi~V1`Qru4nzxg_op_a3)EpB@Nf93Aq?k^%HZ{g&p>Aj2>iBh?D0E$?c
z(>xuS`pSW&f|>UfvShxx4I_4hFq>p(R=wg@}~Ez*J-q9lU=(F#p#T*wHyXhbkgfPasO6Tqe@2
z(y>XW{V!%{N_3|*54IHB$bAp~5YYgO6OVa3i;0TFHd4PVYqz$=!bfYoBD7Jg|J43W
zQ?Pm2Y4|Ma3c#rs=Aq65E6zKmb6s!infc3-XxqW;XpiryZ`EY=C&;`ezTyIS6
z_S46EkyWh!;5_|o%AFiC;nX5=&I99JTVy|q@QSP3E5bYOhrQ#h%O2p`<;@|$U_^l1
zst-K3U#hR=c3AkF(KX1a$O0gZC89sQBL{jERKNA;q^m(z;cAgQw7yZ~L)L)Xol>2K
zXNNz~_f(yLT>b&kxeZ>?bFv2dzHo;6aYVoUEb36`a7c_)J>a2OM6th`r*Db%-jXWJPyuGh
ze_*D6Ym+=&uV5fr1NbqjL|3JG=;>89IjGhsa1ydI>pZJiN3#86WLQc%s|{+w?Cifc
zJFO!KH$drAW{WhXHEgel^9#fFI?AlER?6CJq9@uv{(FTXOg3ICyx)VWFNqu%n*>cg
z@M~I0w3x>rFmN&=eU@Ys{`odriKi6r%V_?ec7*2?dUzr7%XjbD3jhQ7#R3Loq=14O^>%{oH##yG$9`(w
z6e+xQk!5%?mPH^=oVaG`b}ng*iF4(Q7Z5kKlJ3(GR&{jsv3f|kg%eL_Z-q{Tq|
zJjIPZEWI+HY9~EY=NN8)AKmRVgRAJ|?Pd3NF?amSf-1!2hRn8D+9w
zgYeTtEeuXXYw!@H*!%X=kc_nEC1*y_YwU#rRCL%^{Tx~2thE!v$
z-Db>2%&<|&R`^=tic7&g%nE=HwV9(GqjhFlB4Ob0NLArP`09D{l|^^hiM-2}IfVhZ
zUm9kb=*?0STT%p}i&wYikYZm<}*r6t}Jw-W+uZzjrEd11o
zZ<}^jXXYLRTr8CNhN$mAv~)yVMI7ZrOt!cq*Z`Z%O&B|`K=q!cuM2NDu+H$+76bl|
zq%WV}>+XRlSNraI+2|yA+ZuR-`jhj3{_=L`kq0$aqYs<58;#>E=dl8-)Woe)Y_kQr
zC_GsW3gEk9VYf#+M;aC4R6@=E)$~@7_!fK2uPXhyGLh5$KnLC~hTiR`UCwt`8r6Gq
z#~P$XRT<{i+GS=Adt_kiW7MxNUGS`@Z25t$kD|_()o5B5p&A*)LW?X0Zw1i}mBpBS
zIB!-$0aK|_t-?<&ZD{j}Ac4*Cn
z%_Wh;t5U0wj}><}MZOp5cW_f=LFD_9y(8b>cQ>Ng_0~cea)!Ejf3f}eRSqdu0A?7g
zAPs9^U>>A^AFTx=dbpth^vy(6SI%c#yr7?m0gItSX+SR@SUl9a$FtR*Gw_nHC=D*2{ElfO)Rpy(J&PUC4&a9)EA*`e985oCUC-JYoO|#yQ-f%QA@z>FS-+sY#
znOQ{1X&}yop2`39`_ThWxHepd$As8hH`e&(|9(<6VTcNtGd0>Lf;_BL==XHsPng#!
zjo2T>;k?A-(8hwFnpGH315MalG)Euk+#1)^L~3DRU6y0C)Y{=Y!;xdKvZ!rf=c0a$>9Ak0E{UmIipg@xty21?Y>z*d>^gkMo4Fp7}D@82PF{kQJt1J*Gccu
zJ7HNnnYSXSXjCM%!ZlDEtDN-LCsGCPnAg|)?px)cRY7=)+`uB%mjK@_iuWOx($)Wd
zEs$3k)z@)H3Q>lWaQ+@>XQ2IDv1utyGV;Xold4Yk#x51i;oo-&?uG)Zo`Iza1BXgmA^LtxitERY+v>n#RF9y)n}G8I*CjcWNZ+0-=9zKt>Ld%2K5w~i
z{t&TW-rkR^z#ELS%!ST1A>LJz(+8~DWzRA0!g-v^QvIdMT>T~HKUSnxzP>mbcjFv;
zv-U60r^cwim}@+gs4g{TPC`Wus;=VJ<-4PQzcy2p2Jw@#)<&3jAAAH=7noes=0Dmc
zgG5!Oj2f5y6kCwhEb_(MhWt?`J4KNSLwksObheF)nn{wX?+S1Xo;Tfg0N(`I0T9*r
zz`jFqz$BrI&m+S6M0=fxy`^g?lg5z90U@j?b8
zB8H;&sQ3v{;H`f`7V%8~I!Hr<0nNuc7|nlgvbyve^G%KVk6X>^9h{jU8HgOFsJjH(
zL^SE9Mk&HKi;n=~aFH`WTAY>0=3`c4kzen?Do(@%HZ3}ZHVQEWYm3PlaXpO
zHeA2YZ@brk=0*BSyL6ejr!IV|!E3$EXJBP?Hm*9g~(w
zYyFJnKIhlXPUp=lB(5AYJG?|A@_jFNF?H!Ij=pgA&H#kQdiV;vxjHjLGkQNXp6x?V
zKr>OTE)C{Z-By>%muyU&6M>`*!sZ|bW7JV1S@w(HF
z7goM;q^y=Q!Ob~0uVo+y9P!Y}XBM2Y0$RpQJ8(@Lb&hej%BIb)a_n0-@PLV25vYLRkR%~(cF#PaIip=
zuelr1JMwPL`yMXF)Nq#1Jt~+}cvr?NcSQVqCO}i&PtX!NdKitQD*Sp?-}k18K1{gP
z1D>NLW%nJrzZVhZgQd8?_zld*!o`1c(y?_>v6G(JDn8@7)N{);aWIqa^nrfG)z@<~
z)DVDuB>+@^Fd&RJmv@H;Ij#lVU|B+H(e39h##rPtlgcRhX53GO!@$#vZ*
z@4H_0=tWV#>RUCn`ksx1w5MdB{ru1a*!R$W1`IH7(&R_>CUY@@@}vZNjX66)3N1-I
z;`={APDtSoUm;HUD~<5hB}qYqUtURMNYSRM;Z9I)i2Jom2e=72LZ2vhi&OCsG2
zeBuCUPkc*%8RNj30`I77D2TibKK^!Nb|meRlpDq^p_0Xv`iPl_Yz;gBof)MG@X(n6
zjnZIhXyD22FXXndQ5w6UqyO<|ujD;-6rLgm_4+p1=NAAaE46{#6A!#ASe2Oje>_X|
zQ>h))Y8_~4a~rNuHcgA}vuDFr|Bb0Xo5%-f)aw;8>>cpPUaTWod_ey>oouzO&VCV}
zAEkPY1G{`VSt%Y|;Sa&MxaJ@6B{k3p@vyh9za`sXpm-7C`vxD?@E|thGN(qqlC_})
z0h-J#n*sTE6y5BzL!g8{$Qyw5HnjWZJ)I^|DwSERDCNtZKQ8jDkjp$=YuM=1qU;d1
z>;R;{GK)HJBB-t=u_RH{==d_#z>0t5A!M2NtuI{$mG`bAmMUHY+}=qT`mMX$HKuC`f>UXqB{2eH6GcwC0*joGoL51tCLRM
zy?2!(vV2k9e*upx55l8<-930j-GhfW;PJo?MiggYWD9ws($%g3*l1#!ekNIwT;&ZN
zvsyNcug9?>mH33*-NnFSh3?DN0q{Z5BO}f|M|GeQoToItKNh8oq}He
z!*1sO0eUrAT|U-Axv;f+Ro3dSs-yg()SqoYjpsF2y{cX~>$n8pCkwy+dh5}PQNVff
zw0Wr;(6$yHb@N0bM^yFbM;?v{&(DbB)afEeWLb~=ZGVMt(FJwcR;#iOd=5Aqk;h__
zUmJ+EAe-vEQ^~NZ#-0f_PtVztGwHC(##xDab5UFNh3pS)9CygyAVfLfFZ8Pt@-9F%
zRA{b9vx`h%O^LyeV>7Kjzpn
zJTgGk=&1uwKcE*2K;Chq{z%arE7>rFo^D1xNULJ|VVm-89fK;t?ay3~>ILOwzNt|j
zI|Erm7c|Yd%Be}$I(TGnc=xBlt?D9tT_@x!t;9AfXUx8`kl
z;dG{9oKC1!_@qS>52wSPTB^F<`tdi^Qu$ipgtUwZJA0Vs41!L$hRKs_7#Dz2y$%0l45A
z&i@GN$aaNy@5Nqoj_zM?KiXQ2vyach)1!T8E5W|SApH!wU!QpLs)I$@WLSru7}%sX
z>d9T&-zAIDk41Z3H?G}s-D&&rN#Y^d*BSWu62sb(h1-MX?!eU
z_4eK1I9XGgWw&(VI!^ugI<7M78Z4`KneZMW(E*9ebpM?wN0{twt?(ISF9OdN
zLk8$SpzWZqG=*v%)G9se`*xud!7K0={%Hq4S@m8JDj#~WQ4wM9bunS+Z5E->nnr&j
zO_4M4%81)cni|9+ydsL;%9l^JubRPTW&6z$OdU))C-kGA9-lmQ%PY1e_N*>s_g9&w
zF=5>+-dhk$;gDFCB9gT2)>ZmJ}o
zEA@-ypEb@wwgv-d2(O=2tGCy~Uv;GR2^LahQ8;)Bqkfx?cJ)(#)U1nh`Tf*4&LH>=
zm8eovnd-g$im;Ibtml;Gcex
z9KH)0FCMkxv3kySrz&+K+I)|V^?KCH{Y;_b;cL`i>1Z|7LrTVE)9e7TJr(fg^$I7*{Hkl@RN&F(iYtx;|$k(0r6oThB
z|5Cl%pb+mdx;NXQN}9+Xv5n=2@b|xKkObE*a>x~`Rap=8ri}&H<~rx|to4-)37c>6
z9C^-j?m6-j&$;KwOFieFBQNuudyYKsIrkiSx#!$-gAJ;(VH&$;I~U+Ovc
z9OuhC=bqzy-gE9b&X;@6J;(V9&$;I~-^+9EInGyl&OOKZ-kx*MasD9Bx#u|F$8+vE
z&L8YK_Z;UB@tk{(^M`uQJx9t^<7i+K(~gFI>5i;^>CT3J*O-%imZivr(NnR}_Da}a
z>)CV*Vs36Z^h}anQz1tF9I6TX3Y6H&WrY@%)SRjznS-({{WLLQGAg>YNh0tD+k$-?
zdv1>fYf6#*R;gjKLy;lj4ckm@nvReG9))Npd+EHB{U7t6iZkAp*NmtgQ~&7xag9NT
zf{%nWg&v!Jd{%S#sfaWBme_Mgs*cq(*Pf|AxBo)p88g=iQ#ZKb-$*++;RlpQ(&9O1DWEFIAT=W~MTuQC&KY{S*{9
z)gj5q=p9zsnaqBg;5${-+{w*65>jP}=#!{SZz31oQkkhtdtACrYc#2)Od1ji{l}X~
zL|en5mE)D`-(+FVKd{Q7KXU58ejX_3`ViL+d6TMz*|vZTN)Fk)Hy21s~f}
zT)Ke|sro!Z_%NASB7~7i%>DGQPERX+YeL{u>cd+>lc!e7IkA`0of3u`cV5>M`u{Ph
zRFdE8q<;gWNmtQmq}yPt9V=y-5pU%Wn>uV^*}~98HH+pgzOeXBA@i+aZX#+IcKNk;erx^xi1&BAKRvxZJ^2rp|M1S5oaG;)l~4xA
zdo|B{D_=7C15H^(Xk<;~JlzG|n^Bob!w_j7no^T8FZDv|o6lKeM#S!jogP;ommGgN
z{+-#@7e>6e$tvLc|B3%NRwQA}o+)XvN#4qzH(9#XXq0F(HUDqV
z&;R||fhOR8m7E&xzeAa(*Jk%?EkB_-vV?qGw|pC=l?+mUlX2H5()pfzJ$m`Z6)8p1o>`BnEV72
zvKm-GwIIF3ykPs1?l5M#Yz=)akza32tVS(?$bjk-j*5+m`(|0Fs$lGX=&G|wHgs#o
z2K+n9%{LmLr?6HZmHw$ZtFr55uCDDYVkF;&1y9DEaA^-h+np^fM|DKus+aVS+8Ssh
zY9^HiK$BNy4L7H0T-VzAs9nL7B`=9kA%5H3;G?md72LX-G)<+oO(QHr7N0C__VCCs
z?;ef1G?o*Vosp48ycA!qY;QuI;y|uf;CN
zebv`@eZ9`8yW&{1d9317*vAZ9I_Wkc{qfE){vu1PPOXAQ{QES`Tu774zm9??Ca9)T
zwp$|FeIa*!`y)kd1VIWzwUC+6mWpu}B!g&SSq-Y8=b(4bl1_~3FVO^>E8pot22N8D
z-(PryzVz)$=|mmw&~+oO%lZpz+&WikgPw4nFin*8-?(%Cxl6~$V%?pm4!+e#qvv7e
zT_$|(0ID-{*_4TQ!G7o#Fr$N*
zTZc#14f1$WX+Sh7pOn-!x6SEs+BcFn|*`m!s1*6yP
zG0(CI!@cF|(#_a^2eI(1*aGcv)XM2sm%&506mo`bqL%zQ)Mewjk}AJ_vVEsC(mx(R
zWZhQfo)2f=QkTuOsY~bDge-3vS+XeSiTaE4)&b8EcP3xb3vM_Vp5;0}k#zX&PH5K$
z!MaJm`)jD5Cmb5>l-ueuE?Zs7Wz+RF)lrBowjg^!TJ@;9w7P%;M9-klew_ZMX9=>8%oaiTw_ag?f-l`OJ{iqB#
zv=~vo!bMoFI22(09P*dfQv%Ux=uBmf}Td^QdB2*$#NcQr)pIzC#jH=-AFQ
z-aPb=b3+P!0rMF<@lH@yD$moXcY6F3Dhs!>!+GlQU8(LTz;UH`^Ro&^Y3V5k>|ius
z1HKrsRSs%J$HU^HNRXm_O|ZG{qP=rQKlww@7f=~3uqy#o37?l5bnNtZ)$iD?okLNX
zYGf9?sb+kNn%5!S3rtbSxn}`Rb(-|!nW|_!;#&_S?I|kQXEID>d)v~YRZ3;jEK~{a
zX1+R$LinkHtsa4F#(3wMn`zMr_pVvQYyItM(Z10G&jnd*z)Rb8$e
zVV^o3a<0F31ocV5?RKDjc)dN){`Y9zbH&~IW7p8OA<5x}pdr<+@P{@%%)f&r<*LW+
z^gzxOWcV3uQI!t&2x9guL!vt~fD-;5mn6cg4rcs8d6o2h1YczB&AWuv(!Kexle=th
zo5+4}bZkEB@V{VhGax%6cU6TaM^&qEXH<2EL)F#RkF&0m`1`|V)VSQiG%Bk+HFb`5
z)t5__<=HLU|1>)<^+>?Hr(aPi6klG+!#o~?#Fy~N0;>5&eNtH!sfptASJu<>hu0?_
z88vS&$%S7o%S*}|bqq3H!e5_Xz4@>Ig4Tz8Ml9Tk@WM@6U+sP^vdE@>G1snk#wIxPB
zkSFD>SG=(Kg*;P32Rnc&YU>pT@;dTN_5R#fXfvQDwI)?Bt((BXgXP_}e#(hvhdwl|
zK5dS);RH0~S2lYqPUlG*E&N+trK&x!q1j;}aC42pm<6|gq
z5SBXFDe>B=egD}T9Ns{kvir|3q32g`{`u3Rw7vdZRKT7BH#7UCuE*m4Nj-uOQsGyOuAN2h8+%MW&Js@>QFAylyzshcANN4LKF>LD=1o
zu|~@A@!;qKwAs(o8hY?aTrtu$6S83vRlJ~xAgnS>W74Pzz^rkg&%_hl_tHVctvSS;
z8#5u+FJ=WRvjic5kl-_o3)KlDqBy}IV@Zi)OI^|l{XefwKzp>?uZ;XF5pQFwFkfeZ
zONBHZIgU0|WmDX>$SJw~$>8q*UHiwK!Nsu!y-lJeqTShXMf6ocY!XlP3EZ_zzA#fx
z>HeRBkzacB*ttK@vq2w%kGd)Rq1-D>8Ks359hHF{iXlz*tdl_aNgDB!PlMZmX!Usy(P4x4=UlrN5
z9EzLpbD8Kzem}x-)Xx*!`u1uVU#bzl|D#y@CCWKF3Avmym3P&ppR!fXl}U%4i;}4B
zSnU2_XhtbgQ}iqsNAp-)usPN;A!O3|9mvC{{G~9PN2@VhPyuXlmtqU{BDjqW)XuX8!|-zuP}iO7XRbRDRe0d}D#BLB(%$y9;kmhWF*%Nr+=`xat)>Kldsj9N|zU0TBhr1Wk3!
zFtW+zR)Y69)G{NVspai!Zn^jMVDk?lLJZH!5jQ|wE&1cFIYGOp$ZLy!n5Yc>Z_hk~
zTC(nEsP2S2o@1c$M7b?=?R3;8{5l8t(+vwzDvziIL9T>cVS|Tstkn&HkN=4nl)AAz
z@aIsuWd-?^wtw90cgcNs&F$03Zr~cz(>Kq025`_US<)exkyo!Y=Uyy|+lywPX3OkE
z@{xZZbb{n4WS?ta(@7CZ@Ms5)K2wi+uNQa1f9*@fmbJx4-K*i-+ARj5dneQ0!$_Lh
zDKhNE55RDGZDdFQLe|dp<-o)1fiJ#fXjIE;aS0O!;J>_58<)PYJItE26v}btzYxN~+SGLZOnK
zZ_2J(SH
z+36I*jBpF#&kU?-m13gb*%a4^OMQ3~)ZyFPM#JjfODO|XXe_9Z+oR8P7U|BB0$jZ|6}dR+3(lK3d$|x%
z7;fkf_+h&1ofEBaQ$50yvBH{(5hsy3{|r^JMu`J
zUPtw_!4nLvHbua$)HU?{++^T}!&|&S>M*Vhx}_x^p3wS$JeF
zM+K4gmu}2HK@jil3X|)!Vzfm2W9`qK9xPkAiPpt`E@S)YJ*(k|X(!MlOAMzP)adTj
zhgn?Z)vNUTp?;Mq=xXKF9zg4{3wsf*^gQQk+j)Bna^IwMtA77`=3;|x`^i2Bh7)}d
znt8SoxfTiU?OoGY$DI{;^V=W5-S~I(g+`qfYZ3fc&%Jal_ug~lvl81xJ}Yi|AgK?=
z{)F}=Htcnl*ihXH_#>BLmG`#^gQiIZgvq-`B=r~XFVR>OB~>#^ai>m>
zw9X0J&$g7n@2{lF^)E$FsIJ?I9Wz+`4=Ic6#Cs2VZS>_#@wAIqD4N@Oui6
zYme{SUu`i2R8u_dEDOBqQKurP<_oiZw?Bj5NAUzkx`g23V6${W48iQKdfca=|3nQX
zF*^|9Ks3?WlbJ!)9>b=g(j&w-vC?DI^46Cw-d`ur^m7NqFOBD6U*?&nZh%IPu3p~i
zyal~Oov|*&vb_D7{>+TgqO44n5^a|pOUPSf``-9!x2=V$Ex*(=K&wCQ|#{dIi{o8YteXvvQp(szq)jzHy>P}(cExqbjVZ0@xBy!`Qj1s
zf}n~~?y4}0k#*yXwOmy3feg*yi|eW=7JxJgC6KX7YRRi(AP(|_1?~zfTO5Oe6=|;h%WOH(e9~@WIoOQugo-=NpCUUhS
zRipiOc;q){hU==&6hwT}OtES-%cFGkcQ-sj)|`LAQ3k3xL5u_#m?`dX2yoDOvD`Ac
z?td}&K5$W1+5h-`X6Bgz6_rN*Xx5HSkg{g#V`A>6Gcd!5shNt}A7k-hKsNrxfPea~
z3BoX90@(;?tGi~U=5Bq;NvGOP5dWZ7niZgJnMR1VYnmx&3H;vYd1hchwEFDs_xqa{
zm*>y@cka38o^$TG=ef62>b0Mz-jX$YI_pO>=#i&3e|qG|#~;)k{%YShRp}=S>$ZG+
z_@mDbo;+}-I$|}>qB^L+=~jx56dx--9a%T=1N$^?3O9}UVTbwhdzh>Dr!4=k4>ECG
zAGO%KmtvlYye#$M->}E`J#NUqt5`Z+a+PLtMc(Sqqv>?JRjO~+eqKfXRGaPabXflt
zd_=CZ^?RvD^6y@ac_(}_@4C)*%?O`eK3n}rb8OO-x+yUa?s_nMYWY<4v`h1?=$-t#
zr?US2&!B{H2jF3Yr-&l$V^=u&-HM7GF@dL(R*~0a**|HgyEEvM^?Nr&Z)}iG$bRG+
z*ULX?eg56CY|T-8&2jWIdlF&ma72NA^IzD|;?Ihc3V64+<_`FUxinw1&!ex@Ppp_1
zJ#cUT=)iAd($G?;aW6ndbu_I;pr;WHyK=u
z-I!gz)8OV|9fL>zY0U47ptlfJ;J_w{4}e3eM=8acGx(k!TJUby+!iLZY-LZ?ljYEL
zc`FNdgcow#=xkDMvXJd&QH4TtVDk%@`L&{k~tIwC{hn|21MgCd?dNbfXU7TlnvC?_mY;<0|y4+b9
zS~bn`xg_}nkgIu+>2BG;1i!F(8Ow8xMnqYqc+>mlFn@jJ-Jj^pKWAf$q
zk!nANJvR+IDzpc#v@a{6m@nMgzG(f!Cl#}2sg6Ob!8i)`VO5CG$#$1|KT(u!2$1!Y-kRJIAQhR)pnufEE|)b;C5>+
zPMVLJc2?3}e%l?x=@j)`@!3X2q~>D#$O^am)NKWa+7P(n~dCh@B
z-kyiuOjeRL#oyfeJ^jZ#a%Tvhxg*e@6>CbdM;|WMNpc7wl!{Wr-hh;QlEp<=6xf}up9@Bn5{(u$+)+xg6%MR{IUL0k
z%aqvPTi~}ENEc$<9!o=d)6P4RnzU~;aa-2OTUo2PaDhiRluyB>wzQ30-SgRH3jCM0YEkmpY
z#IEKLCBaY)>yFSD5ZJ{()NoON8W6w|Bj(h=R}>Ib2$~wBYq1w@VJ`A$ga(59i~{>{
z%Wz{a#}2sFGTd@c7|jjVv&{+SGPe+VoC&o}j4((RVZtfFBqU*MFAh>VL;Scs`OY{s
zC&UE-H`7X8gYxzzOrp(R)ur8cf`)#0iU?DYy)at#~j
z5U+2g9&mVj0As*GJy6XTm7Xa6;yv-J+5x~``x)4+K~?wFvl3pY-Nix{V>MahSQt^E
zv}hzcpgmea2Z4n8^of$}yAt)>i8!=WZl!iES~=?z8T+Nlia}^)6JekK-qXq^=-3Ss_M42ZMfFN}
zh#|F*-=uJcsDY>2QsDl2GPRO$FVR^t`n?IQjNC0*7@tn(%Y!Ga<
z%(dtw6Z(FlaH)@DKia;Wpxmn%=Nwca_#IS;wtBW`opX+c8@En8rBODl)tuOq+#0g1
z6qtRcjk(sn&9W-;%ng^%ezh#^uDRc1bOm!l6L1xz<(zTA
z-D0=GGrs2VoG{m|sMdT@B4{8@uAX7ll{ljT7MwHWyim%8k3)C_4$ZsTmb3KV&Dwk>g0C;PXMDv%*U4=;o;rla6SKS$K
zSiw=NaF%IMip%O^yTA_`*`+e4#1Hl(S0kjxnf6O%z(~gY5~sSoU9i<*H&^2dZ9O1r
zK8ZOkjgmTrplrZO^BIg1ZM}vYR6(QU>2ew+JIako%YvW6==iSm-3svxR-<8y6_;LN
z(9Mi4ID}oQ*jTc|;nG|&(D%J%#YM%gb?CoZw5f3$bJg-(@!x1}Nb_TPuKfLQ9dr9Z
ziwG53-e%fQ&7AYoE1a`72J{xmTvv}X?c7>Un|*mXEYZv7muf$0M$CQ8Ij4>*@e}yB
z4BF6f*n2maizpP=B#spy+0_4?(*njyV53ugak)6SF5>=eTE4lRJ2!FNyXCIPtJray
zk9lMh`g*w-7|grCqp;(4x?62v*GllU$Mb649&_tM#!c-OHgVmAGJ?US
zzQTqU!mo{8Dc$)#uZFB&E^^J`k(ylC_?>e@Sx%{TNhlM}YS7*m?)+va&$l`0>;`ac
zc#8Xhmefoo@LLQ*`4(_t(3Gbh4qo)aS^2rPa@irF&~6xVR=B%d5*LuH3&<%LAUEEh<+NxK6(23Ae@oNFitbta-fJ;fY`K
zib9Id)jaAGKd;(B7~)K6??v*tEVgvVN(oER!5U!c!C+WeFpl^jqY%6mk|TtpbweR3
ziMb*#vSX!?w_G)Lr*!QiXeO>4S$GcLLHM<4mB=-x2CFOL%7rAU&~}s&v=zFwoRhPh
zcAt>$zo^vW1SoCJndQdw)b1f)W1c!yID@um)T1V@qaGMnF|mU1f2|Z>15Uvm&J9~u
znrE(d@G;Kj#ccl>F+erP*$k^~k$R4^F^s+Tl0*}C>{E#S_{SqbFH1|vAN@A9xY0gy
zhn>m~JV5VrN&>&yV-~giOu{o~qI@}ST6f7apR3G+An|DrR?mwn?}*usb#&OaqS
z@23_6`N7VDbL})wrrvj*X~J&&>bsnEpuGVhY}{IBc?i=sF9MzN2mE8iqCO%V`haVIQ(dT(e)1XAa!&
zGsY_X?h-Y8FpV>m`c9s?)h(<747)6x;9qYL{0|w3j)X;r*gXe?URMq4ON8;0IiZMp
zU1a`hTEDyZRju0Ij(uv5)To@`;cH5SkVDKh=QDPqL{D(lSJzS
zOI#J8zc|d3f)9cR3FE4Wd)1#|X**rX5nS!}cet_2axvp2>^G}0V?T3yt1I|3#!a49
z$p<@$2i6@R3$(^9t-!1=byYw+Oh(^Jd~pAJGEWlJ`wXomd4H!C=DkP%5A7V|c-^sP
z=N5az^QyDXU4@>Wu$#-?vzr@Ms?K!2+hVuxoMS~e*`2u6@J;@fhCiNbJAd5S7zcl&fNeYME^y6;QuSZu
zQuCzx+~~1uC2I~tE)p;3UH1dtz`Fu6u{M&?J14#(IaC^uFAl^UwUo0I)kJFifXzIU
z8?iIhV>CG>qw^mwZBx0DDp1od$ND|CO+k_^+-tR;VBc*g>t=(){#l+m?Qc8m4ZZo7
zU#V;;vA>*WUjG)Y!p%9HRITp#hWyckPaIf)vyFGG-nGgG%|-hU=qrER&$R#N$K}p{
zyw9|sUExG^Z<@I;7kmGxCf%i^x9iEp97!72KYwJ-f%h?O@7t?z_KE4eO|GWDuyZxo
ziClr5%r73z)oS9}zr(s+lj2H@)8F0>?)1msaIQI@BJU#3H4uA0@gG$Q&%R>VJ_Q}>t-{irR2b$>Qst)0R-
zbFM5u<8XfV1NYha
zSmRDrUfOPV7D{bARIkXv+J?Oy=j8=mhHm^XCM0gfJQ?Q|XwXL9ZFs~D`{1eN7r_5<
zE}_U4(_jWZc=EUnwG#6F2dFG-`Oso7Bb5V@rlUo(q
z3V+U+?`qkqXf6`^ehCZ0{8HK8;4DH8kG;WJ^etw*QA$^ez!^nn-|yR!V-8^AzldP#H6{<OPT>kHI=ry_DED-k
zn3Rk&5tB#ka@=tU))blvC1{k=+u-B~v2~j?BXX8Q<9a)oi&+;{v1_F`0C@@!1HUNk
z$}5w^c`Q&1Y=#~6$Eg+rn5a3Y21jG()S}j3t!-&x@K5SnuhKf8Wkt5IiEH0=yt%10
zC@;qRx0!`c6dZ9Za6l{5)DN}Ch+O^9qL_xD`X7dGnp22Vw!SWaE(T-TPn@zM&b6cC?y=V~!_^C)c9_rY57@8;HM14YmHugIKZ2RLJTuJjR
z-omu*ns%)v1S>0}H=#vtNBf6pQ9?ewdK(p;x6I$^tRr04
za!RNuKSZ|~c=yKtAI_-_#_zrP#vWUMH_63@XG
z4kx2Ul#oT9c%0DUW;;r*l(yz+ZQn0%T_LW6{tau)=tgmXRx@yu7zFD?V+{*xgumQ|
zg({rZ4ZNM?#nqU-uk}+2;6}oIr(nyr{VtRRZIjkGKuhA9;|gIRtU3XH%nhr3PO0@1
zf)=F=Y+&^rtU?j_+9iOo7Bl+3klC2k=ah~q
zp_x3O90bnx?Nufg_El58OYu#aSYFGy(rd7DVBa=zupefhSEaSA^`{>x2{@AXPx7=A
zPw-s8e)GySgLz19}sJC2QrKS@EcaR=eRoN8IqlC%(wq=gKSwU9?vcj_Qp4GEGCa&ME|
zKCOy$kkz-)L0;|9LGq+KSqE7I9VE{!^LQFTdFDMP55HD{U+1>*kE|Aw-vXa~_b2)F
zo^)*q?A&vEan9oyw@)ADTrD-6uyV4}RcKKP{aRqbJIiU0tGPkz1T`#`wzJ%#a%Vhr
ziX{hO={vwVpHOkaGyAwGzj5n?el<#$`mj=1HC-tvzu~l>A>Rw|z*UOb-#{lBRH2>K
zi<{syCTsh(vQaSF0kN@l{9Itd~u(!a9m1OCLeXbvO
zpj^bxlJ7omOm=FJcX>OwmzrxWaXAjbvj0PQ`8uKRKBcQ@qEaX=QCwQD{ZzwkUN3%s
zh@0?dNt(ADlG+xfd8QoN$b=YJBL$U(8&~ccR|l*90M6AH*8Rw2CX6+4=(k-bnezlR
zwefdy)7QGr9LMbR>9x-KXSi_ClQX1TvaOIrnZJT0>#@=;eG^JuP4!&Z``UV(r}r#m
zX~<$$o(Rc`-35+
z{ObqXV;Vy1e;}RIy1CB&h5HG+*I
zcs-;wS@2|OjXCgaoE>^gX&o3N<{#*k)@w;x^K%5XEUkq(`$$?B2E)!l()#5NX??7e
zGtCF)WNCfAm8A7)ue1hsNm^Uql%@5jB&~BB0yGCDY3;8$C`;>vH-Cn-HgOjFo3B{T
zpOB^X`74d`XvWxm@lD@xe9t>SWzQxXwy#Z_EZ8(Jlr7j~y(W1`vuRkj$<7VyHrcbq
zGOPzf0~+|1Hd+gN%3B68*!f#=M%8Vvo+FD+z-gKX!(OeeyGycB=c=EMRKX^>T03?C
zyG`}L%QsrRjk4AISHVikaqb72`E#b?zdE5si2dJEcx>I-Zpju-Fu~9IIrT`RY5!(7
zY&jp6jIsYxt6!(p-D~fD&1>)O+dLxjCid>)moe+}wRitatDp4H
zU)mBYVEG3Pt~uo9u`W=&rqO5`vI)M-g|D>veNZ
z-?Z=8ci9J4*>nTC*muabBT+VYb2~fMbWMTon_Jp(nzqN%9%L$t(I#TP^Ghx5f08Zj
zL8jquaPJC_rG0Ld*U}!qSKrdo-aB}|H0ENvtup;@EbXf`M|>^qgq;TUTUFk%o$w26
z?N9mG+S8;_*VWdZ@aD~J?Lo4w-MhZD+Q*W`6
z^#9n>PU{Rb-r`Q(b6UJjeWRT{Pc7Nmok1aNSDDw&&Y2`T`zp!KUVJE&H}!01-&J-x
z&$&N{*^9WCHSd@|`-OJ)ja}{R(%PqXfKpWRcXk=qWkJfo!`;U8%Aj`tb7C*G$Hsog
zo1E#p$_A#ce&EetY-#`K&pZB;mUgSh(jG*X_K&{&D{1M!+|u56>y%d3i^k`H*C5
zA0qw#PO`HveT(euU;N$I&i+C{@!MWY`^GMocBAP#q$dke-rGKw_Kp0@aeu$HrCpl{
z`;Ei;R)gLCHD?NY57zE2oaxQK``8rf%pCb)VW+$0u=q?$D{0LWW9r$lZyqi-o?DTt
z)qG?W=aFw5%O(Fq!QRN;`_QR5Wi(pE=bKf|kX=kWXCCzFjsMh!yv-hHKpuWnbWrg!
z%dt|?1Z!wv-EJ3FNodbMAr97w$d6!WUcX1c7dQj=+H~Ycr^UJpWUm?)YDZm_P|?It
z2F~8qaPVY_JOxjxtvKVEth+de-SVA#q~o-Edm-6HBH=&atVbL8tMq*?bSbo5A
z+V@y&n?hK?CSUmK0UvC}fbWiCc$2~3FXcz_4gC)A0XolK^TR)M&b?w3_HD&kGS1mo
zI9R|x`tu54*!Zf&zf?T9Rq>jos5FkJS+y|WWq4lh(9G1lng0xb0=sw$OKB%)J<-Ai
zysx#Z#yjVZh2QBS73$&N%s*86jK9!yH{j}+b;27|KA~wv?#8pDX|DWHM$4-f@#t1Y
zu)-=J*#LwAUo)-dx$)$G7>Dn)vNPebYl(>>%i7L?CrmYBJ&P9t^-efy$lcL}8UQ$iH?31Os7NIVh>##sgn#c0V
z#oV)P>0CiwV~{)=um(s}Z$;~e9TqCiU^Po#|C{C>#0&RrVkPP;`G-nir?li@U4Jnv
zYaV@6+Y-vwxNA$rayT2syjf$nyi$4SeJ5ro;&WFOZa)J&XM#EB+o9}vzY?_@eoOcg
zR(-MG9(Ug4{gtn;+<9$?#y(ouPj54P<+{BjB(Yn(m-hFuv7FC1J0=M
z<~n^}O3%glV(=N3S3`ZAXMRErTrJrT4~&m--QJ74T;~k
zeb^G`27O+vfoJAUR{U&n%*G3$#tlYsaEs!p;6Q#2-*E0gn^WD~9#Cz^+8OM#0kznZ
z5MNBy@C@J4^9?JT+5~$OJbPtJY;!ww=$cnhmdkHHdlBEoh|M)BYIlU=!zOL>!FKX{
zCGRw+0_Umkt5>~V_^v~Isz#yQrUsR-QR`pVv^RWH(?%FtU;5o2*JvhI?8XX72)80P
z!qMs^=UWIdU3w!UvYmLrD>h=d#y<6UA@6^40YNpm0H4RVJ
zw*`K+BG;wfYgnbOP%u_ro}9ad>9LOf5>6=BBfP}pitv&OSA>_8xFWoyz!l*o4p)Si
z7_JDOelNGP+G1xp&(#(uxSi#9OFIsgmlv*R$}Rk%Ja77>dB#9qh)IU0iUw)b5~Wf4Yo%!=$4V*9wJ)jW^)+H%
zvpOH&2lIUEk3=zf5=4z(%FtZ-G1M5TZg117n^A8Ka~Fb=QRlT%XQA5fO6i(^QcV;i
zzr9l0_zx;~KT4-E&x00L#Trhmo~W_%a=PHEiL_xYmKg~W+sTuZ1?lDBav8<
z)kh4iQ_nDd+C64nRxk1PI#qx3T64ENYY=m1onnUh)9x`ZWci7Kb&CG6Yh%0Rac22F
z%pc<$`qedS;Tue=g&1A%6vTbKniKdI16H{Et%2@h%*VQ;_nEW+d}jw8p&z}&{y8z&
zbAsp+qYicyX8l3n>+oJ0rMK0!5jKbLFY*n8>#o!NX#P!nS0>*Z`8|9?fB9Y>i)9zw
zg}_Z=b4zO+zF5(?7T2*|6~{_zOB;&ZZTT_SD=!8+4_KPo{Y#4v1XK(6U1Sr=mIkfJ
zJzbX%?`w>XMUnVQ&L3;qEx@{#ub2MU;Qs@MWp45sjsBJzb)*tJ2^6DMet&^zCSW?Z
z?Wy1)hu>);*u_OhRH4*Anq;P(jPFNUKtrIIhJN+e^U-GIL7s_!QY#}I+_wA}jr?4$
zR_47A7(g34D(w9Biq=ci=8p8i$FZi>5Yl}8yj!rtu{PJ$L_8_N@g~7^wMKO#On|_V
z#Iy&SJ0P$(4cH4Vr~wyTa0FbysR?0$NAmF{h!%c`FO}A}!$vxjlEyxL#ZlBad>eM>fVEkP@9vlVDA?(12*JJu{|WMq`{}zZIu#pV
z<~Z_Tp`dS9w--#5z7+h`zO-xf^^5oWn+)tlgY*Zs=fCa*0O0nm6DLcvj`^$8w!V+uJ$Q&T6A&Tq(|x>EpU|L76w1
zGlxYtP8UvIP--=Pt>O}J0L|4O#k1e4w3>C-#mDJO8b4L*JaOUcOvK(3_Q?X@sGLw{
z*C-EyGq|Z_7L5%rT8j`>KSxa!mpOkg;Z?`5LNi5`Jo`B55cuavnOUqCE>}bmg5^#^=(5QdNIb|
zjn!hu89-!Eh+;j9+ev!y1w$ot+Y|U|k~7OYU5I^}nUm6-tzkO~y^?+7dvfY8SO1*U
zFM7&uFY--&Z=!Y4z1i7IXN_VkHa#U<7dTwxq0YLM~%^?
zXDl9xpInD8sK4}{N|+ftEBc-}y6B87z++9w&dIV)ARI^Kq@*V5=2)|ADH-V#bS%r7
zYE7_N;}@jHr(|Tu+Y+CQA3bv1$g!jD88>eHJ;@29#|z@v1Yr#2ot2%ai<&hD^N@g}dX2}`xX>cs@w8aFJ(_6--B&6#`kJ619HAe8n%}z=4#Ergx!syWx?i)?%
zCR-CSbzwP%u*?zi1qgfWp;_~F9UVe6kqU~7&&dp~GtBuG)erL_fny)j8*%%(Wl=MXF5?w};
zE@rL{1O-|HA&rs2XsK`Y*r-8
z&d_BqwCbM9vF2DM3Y=-RS+jvFk`Y&#e+t*^eoRm8`4rbIT;J%=^mB0i>NciN!}S?0(^Er7
z3}E`%xXuh>`V?G$8_e_zam@;0dK<2nLz#Xiu2TjvJp>ec9#=TwvA(x6{Zd>v-NE!`
zTnGOO$}O(jhcLajt&csufV%Wa-AoxRiMnAiGbVr|jL^-RK0!BXN!X|{^M=c~=#po8
z24#~XI{P~|eNjScN}^80NCU&>GBO;O^GXNxskCxYh1j6|?3iHmi_&ALS#<;z~8
z%gk7e?g&dvj7sZ-L894P#7i_8m!1HoxY+6oWhYz`KBW55<>}T`;*GKX}=TQ+!S>VhzT_#|*S;Y(qHC@wDoi;0oJzccw(sR-lNX_fgHg9>^
z8Oh11R$T^(s4noJE^k~?QV+0XFNsgeN{biMvnR+H@7C^_^K>@i|J}=#-e+V|iCyXg
zy!Qaqd(slJiHqp6e9BJ+1!dW6De(!5k|%`GQ&N`osrZbfBn;xtm#I&6q>upaQhs(u
zHU#d!U22yy(=u$?IxoOz0O1sr%sJhUp)E}OBYkEg?
z2aa?zBqEiY3?}JK;f1Gbyl)NN@Qi-7K_;Wmvoq2?9glJBEyqh2UD9|6pi3H}F?3V*
z!Yr$8VFq~ZjpIiuYi3TmP81V#X*Z5dDPEMvM*M;t+foU4)X~z7HPJ&^-RcE9&xG3gSkeCPnAT7XL#?Bj|BdrFskz+;Abf-(5IXxRAAqCu50>_sIWmT+8R0mFU)YgRy
z(xK=ql18ylzjnkePI%Iqlc~#uKuQNxuuYDdju9^53hElF%kr&DhQDhX
zv@%VSs-1nPLkgW-7lF~W9hr%?9@`<8J;OBXC+qK;rlRD@*sP3)+JUkM^Z6J4Uk8!PkZEYWijFzq2K~QWRJx&h`}Wje)?Z`xYH6u
z9Z68i`V;?puGl+{AfJILUo=Si%MFO=n!bnT^_;B}Zn>X-0oXkk*a3%G>Rjlo$q<3M
zM9(nmtgoB$FHK&$(1?#>?uqOuyNhxzM|Q-?<;seO`iEzB*OV+7D
z%|t7bq{cMO3dsU~EP}CTEzw~Xm#rIyxa=GoSh1wEcCMs&g*R=NH+{D%dT19-X{fh)
zYDp(u$#_eU=3Vim8$SR}oVuiwz9hKg(x1f4976g=J)3wG=v&oS#WTjS$f6;W`Y3)q
zY1yRvCNXB1R381{q?!lkPI87OPP+c;Q+SswDervBsI!ZqC6^dFuRlaK8LaaU7mwkuP)D8
z&wbgWU7q`3#mTq6-Ylleb1(K=JTnPCT-Y5_eVxyPr20CaL!|mTpM#|OI-j*teVxyN
zQhlAz{kqi`z{Yf`zYiPM<+(Td&lkR4=s(|QfApX4vme@^c$n$^5c(p7BJ7?ahoPSP
zVYrS&7>h6g!GI8hFa^Pzmaa4KJO|-%garr-5z-N|5uQfKMJPmAjqp6eIt0r1CtN)<
z_eAJI9jwkX0!9!!1j~a;B5P?x|99vxNA^x@Y2$gT3+**y>OQyRKA$%J}1Wgi-E
zYW`QqOFz?udlzS9J!yl+YrQurBPS^-AvNRPPHWb^C@T|!Fg@FLZ@M*`(jwMM0aL^5
ztc+Bc8tzTWlwPK$-fPPe?@dijqYw{`CUqo?3B!gB%SlPk7RJP956@a+TbeE|PD!^t
zooG$c{r0!IQNwlNx@UZnj9M~E`Ux?^hwC1I-bQc^Bimr=989q~5|18-^1O*7eGx(-IrA*g=G^gH62z8T@7=lTP#Z3qP0_yt_l+AUmE
z7`W=~Y%=#Fo9st{=Xh=a*Nf}do5%nE6n$gD1hb=!1_P|J5|N7;@u`>t5VGkSzc4XN
zH{=1`^th>02|jw~`)p0kj?d13p**c?%5LvL?v(SMiAgD0HnO+f7*B7qtVvYNJrmQd
zOS0Jz4=nL1ws>fB*-M8}8DoYM9G?7`#&)guKQr#VczMz);p9ncyky@6QvO@zW3ndE
zcREe?eeg}s_e>Nsva)hAv*V@Z2I3tLn&YR&&YB%R!#I1kdFFJ+B!ehu8gt*24DeuY
z5n;9wG}WI#HtnRGbP+cJy`ahX@Fi3opP8Mdo2ct#XH>0(XDTqh8&Kep@jywUbwN&Y
zJmpSFPs%`_{MT?}OO|kxW=rm9*MF-n$x;v6m)J|Z$K-s^L{uFwS;-$unLm>7NHpl-
z8neN5z>*E<+rNI;lMr1MOFeklu^(`^Ul(=XZ;PA&=H07AK@+$3LZefb@Wl@;q@g
za%n2s8H+NpzLt}f-eHyU5GinsxFlE(9>5hGBpo-YzGX_Re3S&l2wKocNE_{WxJfRe
z-2|J>ngt*zIrXE@J81Uub5c&0hrngx?xGhU&wqygy6YE-&@U3fYb5r|(yfc*B}@Wk
z1ZPhAlNsrY(~0+Wj04~We-MiC*;qsDf}3dQF)8U-i9vb8!muTRO-x9SPsmJ4gE1YG
zQg45T*(N};Ct7VHS*0nCmXRP9Y_L*d=?vNLnTQmg$PqI7h71|v)3+$Y)4fvHA`4mU
zhj%8D;GBT>@nocDMA`KzJG9
zuLy4;{2gH*f~Sw-smc^v7V~-TxCdm?k{;Fj-=vky#2kq?-XJQ&rEbG&19iyo9%N~P
zm>QpzxD;I8SJxrIOTwTV5AjiUh>LXcknANS9R9m)>`C9wgnvMKX3hcvbo96$RqfHF
zZF?bAlU0Tfy|-BK#NoN9r42{E7=x5|`WpyQ4;RP7i$ZWiQEGxb&9!
zMhV`w`sT~><{R&WBcI+JC3ND5Xx01UpntZvGwl2ey%c_Y;kc6Jfv*1zd}S>LhrL(&
zFX8MzR);k~QsJx#QnAE4z4R{4+mawtZY?%tsp&)VETGqdRLHLsa$CVdnr9sp>*(Hf
z4!93sF)J+5C(gmTH29Jm{I9F
zc$aO{upp9}lAKQ3P><;(<29Uba#Cf-HE&s7n(Zu8YO1%4DA4AU5`lG=JC)W4d#o7v
z^^_~8=~k&HZWczr^=t$xr9eKe0DUWHI5zdlee=wv<#6&Cy%wyhgFp2b})D#i(7l{vMCBaYuP|(FG
z3$TDEkv+)Ln_+~!;EkNr>0Qh1G1R$I7^yo5$+cz
zq{c7ENXSZrNb5nqc#}eXNl%6Yt|Z8Al@5YPTBYqF4VfQM9&7;QVkD2ys9_6+Lmoip
zp~FmOax-H;a^R`NRNjXFwC=@*b=V@f)F4~b1cCV82|FM-w9SAmctHzxk+
zl;j0gnm6`P)(y$zrYB}EAOZJF^XP_USr@?j7L7-545uP|DuAN=GhrZgVI*~Hc3P&_
zxc`%|p!jaU-@3iN>3abDXVup;pgq*v6Me-DOX{Sr9`f`=Co#W}u9E&ux{_e@r7PpC
zSy-3ou^;6qS??$D-V?pWk)N5)0sVb4;g2gaE+O2
zoHcpA#MtCchf&Pq6ilOB(#l|)lO5D=0?SRxG?B9miG-2lH)A8O^63xhWZ%>oWO~!#
zzwCe9;mzA)Tf3J(FLuT+f%xZ_`M-g9aSD0L+iW)(PhuTC@r;gq5|_R?4NB=GBJ}C}9^fWA
z@lD%7gg=?qr}KYC+FO;|weJZUG#_lVr}j%G9_Tb!9f!Lvke8S(JC0^0#b;w(l3CN^
zv!Si_l-Cm_3EvU$VStI6{*lWXEw+!)QAWJ?x+VYb%kXhs?g2MmIHWG5o|g6V4$Y8x
z>_xg6*|Q0jcq|?yr6lWMSn9MSN%p2_Vpx*yKJPc61sx1P^vRI)YOM5%p*=7gMAOVa
zM@mCR9ZYJadofEC#&`+#q0MsQI1u
zqj5h~(pja~-g|njLzNOiKZZdH+Zlr_8=`~vhc7gKGF@U?0-STO
zj*oRUue-emc(UB}*jJQ?mfvog$Mhk-O+xrRLMFm92n7fw2x}4kgzz%L>j-Zl>_+$q
z;UvOYgi8q55xzYFUogog+KCx}B;%}_^P*9DC8vY!6!ZId+rk8Tso+!`hqVHZsiZV`
zRsr=2#wn%er!E+zZw>L#zfaZC4}6|S^{Hy7=LjhwW1)R6O7Y(3@qI2LK4Y@?d1=3k
z?MHp`2llHvdc@~>bib;0diJIt*zckg?|r@>`H#r01bTZOT7C=T>rSDRu
z)QcBdX@F>C*&vmBfI>&RR^xm?lojr_Ms)k$>fPxNnRr2S^0i(ZFdfEC6k6#$AhdhpW|I7E^DW!&Nz>7wTh$3#>P8px;@(f>kx5D-hwi-uKg5*uTf#@*M0t_jLp|sU
zS%(B{KXIe$=xQWP^{z|yP-YjNC$X__AuA9DUtsz=gah9(ebhzB72LyjG9y#^*RiNY
z?9U1kV$$o3oNV$20#hJ!g#3;^q0WSNEz;aedjLpo9*lkP1MJp6f(PJQjq72AQ`cml
z$YJTQ2g6Tckb={XK}bb-1L13gM-krglf&!t+e`-mt*u
z-5lJH8a+lBd*8Uo@%JYz5HXl&9Cp4lMn#*dwsFHT>LK-UP*Gu?ZGH;$fP
z58(7GkVfYTAN1+G_rCMJ`XT-qpY-0igFU<}#JlMTfA@)d)Kk818C3segf>r5Ak9d?
zwh*BNVLQTAyz2v4!x28{$LY@?==yW|1qf>q`Xa0fmcsy_dwS>B?OEY@p6>I05bndZ
zoIV}te@^(r08YQSFQeP>{2x;EseGzytUiLTy?V+
ziER9DIlVXRz?rS}{5&4d!s&x>ed92v55{%a
z2b?|x*Oeb~`a!r3K>ko%4}2zwCYX0u)ko9mN$QRA$Rwi8w_jynOjv=
zMdeXh&r79!Zphtx#eJ(X?>OySW>w$LGN1V?%512r8eElI)mfsqEG}^92kIl#j)iPR
zMd1E1=1YbJCfY^Y&k%7S=fq&+;HuUZJzCb-QUB7X!att!(aaCjbwfX$eq_$!M-QTP
ztHu=VD11r7F>0lj{|=@3f4F1D(Ai4!cg*(`BI*1gpY}gDP=?ih1nqw@*RbdJd9kg7
zBLBwe{lCt)e8+0P9KA^#XyWXamo(q8!>cG}{kC<6!3Ns@&8glrNUQE$B4)semxFrI&Q-TlzQgu8_6xZa|J*ugW`Qz7#TuUP)h52+
z4`&Dy_qn0rImc!F=CNE@rG8T^x4+VhHR}EF>M2!30V9ic6v%s6QQwAj>08~9&bGBV
zi+ox=${Ta^LhcjKi@)+$0P2zo)=3w+o)r8s!1vr>!-nX=RgW7)?C`1|dKV}6q#~AR
zE&pzR)-~@%Z{AOUkJTFtdfhd4tfT*^&%+O^k9cWP?k(;R^%V8~$5Q{VG>A$&3v3kl
zmkrwcg4h>sKVxf088QaC()AsUgAGL&I$QA3Fb@^hUdX+(fO>4;KR2KapLe6~z%Hx#cXMn0
zx$G0Rcd&>0Wt>fPY>2M?IdyjF&*#Q=*7xK3uL9DZT|R3@i>m^BsD}3X9K6@|oO+bEPH!C?&c!Ca
z>o4(L>T!xuzM}EzX>afNH&UE_lLm6ZwQ$#`vy5HsW`LC#$bG3>^_GY=Q4~9)GKKDJaW&_srg?$vZ=YXHBeb~8n;@!S{
zd&h&`)8n9&D><`k?qAsX(!3_@rhB^?`-A_*pv}J0Ph7ehytOJ=t1dcDeNu9$mnv!P
z&eD>(^C+Ze_n)LDSKS~ELe!YmGS;*9@R#XJ+
z*<}bfjWL&-)UlTyS@7t`k48PVf73%Req%9)(SIEy#bU(FrNpL-W}sK(RxO>B38I5@zMpJx7Cdb?i5X&>?D#0?d_
z2Ah0&{>9-=yB($RXE7dM4mCY)czo~ry`iRcHA4^Vu;|y^&5f~~UhH%@1bzP&w!?y5
zi4VNEEq^W~*s5estIn07v9E4K{!RIFhcoef1rx8hIpy6&Y+#N5J|&^mkrvQ$G52`}YxY??pbyMR7Pq^+DBU
z`xJZQ=(s&jO)Oib`K+SA()y|RZGn$|(Eol9rvHiBOVH=YhrULiN20%v?aQxMd2pJE
zl+?q7(~@WN>+fQM131-2`hQ$etvPN09@gNDw?e!dT+j07+>IS<>CNNOpI1E|y=HGg
zjqSN!qk7^8q|1o|{23pcSJ~MM%mW!wR7n9Bdv39Q=>442u{BQClJDa5zcRH`+pTV~
zZM{mo)8D6Ey5Gp{vY!V%=KADCdeVGcj#y6Ic$s}}7+ke}um0soj#~6_h5lEU+g_|x
zRq0vpirYU?+CB<&O8DdzrV{vJCLqU-qen=
zRXE-HZQFCIQKSz&Z}P{kt8s738i=ptkTDW|n97p159oj%?L(H|-m<~TFCM*2CHAB<
zkq+R?O}X<^3TY(d#pFC7LqIy$1C>4LKyrJ$tqE)#D(P@W?!7l}l$Ae6YgN`JGOn2P
z)z0~nx1CcCPCqacCppWrFv!Mh7%SkHk+Hy>efS$g3$^@V)dlv(ueRFTu*@fpxJgs<
zN1e*UWy)8vU-sN{?29j*CkmK&@*2wz^Jm59c35g#^21`;7srO$xyXnEOFg=rZUB|E
z*&dFPb|0dg4If{-`kgx;{ClYVNJT#O4KC5_F8l62%r84&CoM;wQ<2^>6593-wZHS5v`W%gH)CwrMW6-b46%{)S?kmuR
z?felMuNfCh4|Ub^I%!MpThe+uX4;23^=_HQy!b;OUvels__>Q(S4O&W=ACcIx;bI=
zn7czWS4ON2HCS6zRh|5g>YZ{>eI)#_JbFe-dJ45<^m*;mL`BZopo@zZO(zcCh>&q$
zZU?=-EZ464HPybwj#GOwCqm+%Vv6VFm{C%UL@!(N>(4Rq&}BvU5f%xp&lwT{-Ato=
zw<7;l4QsIb|Bzn`>N@$>5BXb**zUEy^XoT$?SX)S9ya9HU}o>Q`$v85T{!t32@!sH%0ZbUN;ZreFxxtp+Do-+4A4r+u8DyYvuNRbg$fU
z!uy}r`L_I&6hke)vqBmvpIyGnZ<5;z-Aih#lG@q_ZH+@)Yu~y~<7oFropB=iXX}2i@Ng1pSA}m>!EYcg(rr&A-JWD_-vHQm@D(z&bed{
zGa3yWhVw*nk01T?p@yUCw&M@2oTa_buANX8%!lQD*D*f4@XOTgrR?rj34vd0cqC72
z#wi6wU1tum6{{!NUKY98o-(O(?riL0ySxAN=zYvYr$ONao1=VEXJ6LMfUL%uL1xW`
z%)VFMXor5gqwjIcz!tqdML(n?y^8J#N8i13x}q(~04(+-P<9|)1pJ`bT9~ra<@`t~0YSRAvI4g@NP{x@Vov?D@
zVx@zma_Ogg+(YemMEaR(A6R;=X9+9M?gP(xIZWg20TPGF$nVZ!!Vk~fH>X;Cghu@I
z1CLg1Uo~=-uXSr_qnl)do$i(UV|vfhIE!(2{z
zBAE&Pu}1Cv1DUqG7f0NU^jje*hI88Y^IHBve(7Bi1$Q*&nMadceXT=Ns+H`b7{L*L@X9h(!!z#N^s}5HXhklUHxl0W8XZc$(D=Bj@`E?%*I^DwTNqIkFt&Z!J(qk_1+nR6}qckCrdsFptOEKQVKz(Z*BGnjPAW8dElgjxW1P8V^|AbE{h2ohv($8qSb^cTL_<9(?KO{9^sctAuc3{ia6F`Al2CpqN1pF}04%-%{v@bKkftrA0Mbjgv_yu*8Qj@KBVd>A$Mq?my>m
z?T1seLRfxu7*ocWabi;(%a00T;yQKz0F$%1>AJWgU%{K4XF`}*o{#gMn%aeoUvc>s
zI{T^l`ga$cIC-&`djAV*&9RabB}*4;H7)&eN}c5^*ohMTrY|8sZS4|di&{ude^sw?
zw=ly;59U7<#`uSva|&6prFE4Masj7`wd1_uden14I&;UhxSq-7EiKW)hWBtOuy*k!v`@jiakg0L
zCn|f4==?;rXHjeLl~TfjTm4Zx-RH;L$BMsktNXLsQn&iD^lpke59yATUMY>yp#M&{
z2G1{*@WM6j+>=yWdd!XTUs!bAt=6$~ZnyfVlnZt;4bp~4kaFvBDrio-wgo5ZSj2xe
z`9(G}!|W+b7uzj_Wmkopp+s0VUtEDcPTH)&xk4AOl%6Pk{P1=MovSU;O`*DfFU`1$
z0nzqn_cSUGr<%LhmCMZ?eS
z$#L4R^gCZ_w?eaeDXZ^=w(`c1PHk
zPE8r3lYjod_MSf~itF5acXoELQCL`D(QfLpgNRfqf@Jevg6<--q&R!xG(Cn*a?zLY~O`
zzMY*Fdrpt1=l$_|dK}Jhzx&O--`soW-fzAicjr3?eWMWhcDV9fYa`bnd0FyQeru?P
zaQdEEL$qF&PMBFjt-Bnr+_ZtrrXG(ejxk4&ryzb)1Vr39HM~-HEtaHtzQHjm9MOFl
zOImjR2J|(CxOav_?+l9zVi{E+@{V6m4ebt1Urjeetj3mUrbFbkUW}^7zcCVrJ-7>T
z$o&*#CulhXEr(cc3@a2wjfP=s%-9+T_13lv!W2QAFKkb7OmQ5x$6fwagpOfOxx+W9
z+-vlt+4CyLoP>BRu%24BpCq-vcW)0L*w^l6cTTvwV@UJCS2cB64p+r(j0n`?FC=vr
zSgucZ?Ju@X?t`D+YF$@U*4=n@+ASCv@K##btzn9A?}YtgH;Ws?uBb738*8
z{)W9?v9G;mebJ$s9{frO{+ZWgt#p?`EI@9Jz2-vQ;%Q>RKl=zP7HsvYig!N!dzg#g
zAFDKTq%l~mFRpa!9S{rN%neQ;#Vj_zqWlwlRsq`UXCMdtGQT3M2XWZP8_Vf?
z)U`i0`y)rEbS*}C|
zq58{IXjsGucA^s?-V#K}I%dY)()VOKC6^gtKat_yt__wq+r4^fVMYF=|3UChZCl|R
zqruW0IhIDDS#;Q%52T;DNERMcT2X&KSh{sd_E@?ks%drKltrZig+82`-cM5F7+W-z
zganFrAA1h*+K7HKpk=)PMa_aJnlgn=oj-3ii?Cv5i#)8Hl8-9+h?J&a8yx(LrE^JGsUHgc90Cy37DtzlhbVRCBOyv
zwu)trX-SEWIVMHgf@q^Ko4p
z&aGS(Ll9RJ!o8+Iz7QlHQgF@?B-SZ7@n<3ENC;|BAYTaLjw(1Y1UW;HF9dPNLgkwF
zICmEzw?ZEM(CdUVcK>?omJfcizvtuiZack`TlsNMzES2FC1CNScjDOtnYl@fFPZ|E
zizv-5(2i1i-Jj4GoF~BZWQF03
z$#e!smpQg)UYB{5hgixN$CqZhiZd0?L&3`?zl(JcKhe$Qs0#kauX1ynR1k>`G_d32
zUO&hZ?R8c&q=w4|t9wLGsyoLH0SB_W{d!_($92sjM}T>n7burf7TpysxY>&&uWPee
zxdV-KiLVpb02?_7QL(gIWzOlKc+@LLIp)fwNl|%I1})V3p|mj?PG;mi-3#5
zy5+*!_OSxWnh-BCtfG8f`px@~Xr_NwkD6slT-da79n_-l0*5z%Mmaj#uLHh~SNVE>
z7z5PabAOWw1qwE*(a`Qb#QNM
z`rJP7vln|K38hR1k8Au#y)<2$R|Kn)}
z+KDvhKibYJYSCQbu$>IawdhFPb=Y_HPc-X-QAd&hz7JM_3&v>jYzU4aOM-BNC7P@S
zIA;aT>iQGqQn-e
z*{u*`m?uNvrFGlYB`u?~sp2yo-}m7~Mf*6$AMgEdQj@n}us&y&kemNCbm_A#g(pjOYKhC(gO
zF|iyhfZK-|cuQlxNi28o^iE7~a~FyPbzR;xS{{(Z0zQRgJ6Ivg!CqEw-a#zSZyW>N
z$gx-Fxke0@W((>phV#2NItuUZ7^{4d%LQ4GfgJ?f0nclPh@uVSQ$b3tQvbkAJ8H}C
ze81V^UUQAOW6j`M{|D)VJZIGMuWjz6a%?$k!-x+;KxsNOmbz-rK$q
z#D%07r$f0amMM@g1aVFUCq9HK6dd;x1#
zhf_XgKoYKG{!giSRNe{dU5$HD#FyPpA85d~@PfW;WKRjkfvsw<<}S7B&rFPih4Kr@
z2wSP*ZGMoKDUm^qz{G)JRml5J`!
zxlGM`yHhQFTf;JQZLBo6jAiC^veG<_hDot$q?9rZ^PNtO^c@YiO}i>}TNRs%(Na-5
zxhm?MbX3<}MtR~R@gSdF^<5QT+EE-k2oT1A^E}TbkFGOwu?$Vpc
z6;;->H@teF6Xly{7qejVp3)_i-GX;B>eu@huY&7=_kE&sMol2MZIc@Ajk`m=9VIhm
z8=A5sNz+ZUbyJASwX|p%yBzq5kyRH&C9qNx9l0sN%moRef8d2m$!8s@?LuqA+GUFN
z*a$0X!*3_^t`C=GEpJ|q9IWrA>+1sBtEAf7`YnsZ%{AsA+9dkBgv{
zOG5-L_5XGRC=Y`~VgP*;qNJbope9#P#YN%1BUqbDkZX*K1)d=-aL@WN;?2ui=^+7~
z?GJ8yp1mOAK)87o%p3ONRvAzJkm!)1`p>+6RTglx3I6D<5y{s!5z^!sy#V@7QR`OK?D1CWv>>>eA91-di1AEFGzrKAOR|U{BnM)>ru?m
z9E@K+xyl60xZx@^kZk(6VM{H-Jrfc6J?etaKQmj@R~h9***1Kh9+s>zOq@U~B$V
zuG8^T;EYgK?F{_igK{ZY&YVzgYTsf1{pv!Tx1gsC7<%poYxjgI;bRRkCb*W-+kt@Ffyc)j+O?RNO3Hyd^l)!U^-rW~oSMDUQn12U(
zHI+;aGhNkmC)*pI%e`$9?q)WNr@OYz%1Qll7D<&`zU58clt}ml8`#@dgPnZ~*xBI|
z!|!LmANJvj52L%+b{jt7lQj%KH|Y$0v<&X}05zu&}|5M(`Bh&dgsZuRL6B*w)Fig(s2_cj-%?
zdf_>Oyf7pQ(FA<%WsIN(54j{Pz?_2-5+KLe@(5~bQd376Xhk08Xz8#rb~tiOlfCKD
z(NlR~odtAF)Go~qnk8$P=#NJYQ)*Hlgu67U4}onQ((F1pRR_}!kDTvNt{)7{nWm1T
zfmBq7v`UvBsMG{X0~UM3G-V$_4f7IcaVn1_Mw0{Wh=;p01ZqPMnK$f*tHoWU)W+J*
zxl9gKja;JRD08e0XEKzLI_VHtKA_j?!&nB}**0QU!<M~KW;Ehr6aiV
z`4j#J$a%mc&BNTaY^z$6sZ^KhTh?z1emuSw~vJd*Z{xzfK#dUx0WhB4o|=I)`F-X-udHyfw}l^t&vaK^JE16PDh|TpJr9T
z`FGmAC*6870#8QZ|8WHHI}-9yvS?W)N%}Da!J7ykbYg;@dI^3L3MZC9blAE{yr`qm
zf_Sp&bvY%eU~j-f8%zfl%6UsLZw#gcVljIDHHw*Ok*^Oddgoh?d%5rYY>|9xz%o=N
zf6+)TaTR_Wh55K&vgLSaL5R|7DV!k8)e{S8fKy2=L{%RFg?m+5A)HL+ul}#dKUnd9
E0mVa>uK)l5

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl70x/board/config/.gitkeep b/bsp/bouffalo_lab/bl70x/board/config/.gitkeep
new file mode 100755
index 0000000000..e69de29bb2
diff --git a/bsp/bouffalo_lab/bl70x/board/fw_header.c b/bsp/bouffalo_lab/bl70x/board/fw_header.c
new file mode 100644
index 0000000000..942edd6889
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/fw_header.c
@@ -0,0 +1,126 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0xff,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0xa0,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xff,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x01, /*!<  0:Not use XTAL to set PLL, 1:XTAL is 32M, 2:XTAL is RC32M  */
+    .clk_cfg.cfg.pll_clk = 0x04,   /*!< mcu_clk 0:RC32M, 1:XTAL, 2:PLL 57.6M, 3:PLL 96M, 4:PLL 144M */
+    .clk_cfg.cfg.hclk_div = 0x00,
+    .clk_cfg.cfg.bclk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:144M, 1:XCLK(RC32M or XTAL), 2:57.6M, 3:72M, 4:BCLK, 5:96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* boot cfg */
+    .boot_cfg.bval.sign = 0x0,               /* [1: 0]      for sign*/
+    .boot_cfg.bval.encrypt_type = 0x0,       /* [3: 2]      for encrypt */
+    .boot_cfg.bval.key_sel = 0x01,           /* [5: 4]      for key sel in boot interface*/
+    .boot_cfg.bval.rsvd_7_6 = 0x0,           /* [7: 6]      for encrypt*/
+    .boot_cfg.bval.no_segment = 0x1,         /* [8]         no segment info */
+    .boot_cfg.bval.cache_select = 0x1,       /* [9]         for cache */
+    .boot_cfg.bval.notload_in_bootrom = 0x0, /* [10]        not load this img in bootrom */
+    .boot_cfg.bval.aes_region_lock = 0x0,    /* [11]        aes region lock */
+    .boot_cfg.bval.cache_way_disable = 0x0,  /* [15: 12]    cache way disable info*/
+    .boot_cfg.bval.crc_ignore = 0x1,         /* [16]        ignore crc */
+    .boot_cfg.bval.hash_ignore = 0x1,        /* [17]        hash crc */
+    .boot_cfg.bval.halt_ap = 0x0,            /* [18]        halt ap */
+    .boot_cfg.bval.boot2_enable = 0x00,      /* [19]     boot2 enable */
+    .boot_cfg.bval.boot2_rollback = 0x00,    /* [20]     boot2 rollback */
+    .boot_cfg.bval.rsvd_31_21 = 0x0,         /* [31:21]     rsvd */
+
+    .img_segment_info.img_len = 0x00010000, /* image length or segment count */
+    .rsvd0 = 0x00000000,
+#ifdef BFLB_BOOT2
+    .img_start.flashoffset = 0x00002000, /* flash controller offset */
+#else
+    .img_start.flashoffset = 0x00001000, /* flash controller offset */
+#endif
+    .hash = { 0xdeadbeef },              /* hash of the image */
+
+    .boot2_pt_table_0 = 0x1000, /* address of partition table 0 */
+    .boot2_pt_table_1 = 0x2000, /* address of partition table 1 */
+    .crc32 = 0xdeadbeef         /* 4 */
+};
diff --git a/bsp/bouffalo_lab/bl70x/board/fw_header.h b/bsp/bouffalo_lab/bl70x/board/fw_header.h
new file mode 100644
index 0000000000..bf0b90fa7c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/fw_header.h
@@ -0,0 +1,170 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t pll_clk;
+    uint8_t hclk_div;
+    uint8_t bclk_div;
+
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t rsvd[2];
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /*'BFXP'*/
+    uint32_t rivison;
+    struct boot_flash_cfg_t flash_cfg;
+    struct boot_clk_cfg_t clk_cfg;
+    union __attribute__((packed, aligned(1))) {
+        struct __attribute__((packed, aligned(1))) {
+            uint32_t sign               : 2;  /* [1: 0]   for sign */
+            uint32_t encrypt_type       : 2;  /* [3: 2]   for encrypt */
+            uint32_t key_sel            : 2;  /* [5: 4]   for key sel in boot interface */
+            uint32_t rsvd_7_6           : 2;  /* [7: 6]   rsvd */
+            uint32_t no_segment         : 1;  /* [8]      no segment info */
+            uint32_t cache_select       : 1;  /* [9]      cache enable */
+            uint32_t notload_in_bootrom : 1;  /* [10]     not load this img in bootrom */
+            uint32_t aes_region_lock    : 1;  /* [11]     aes region lock */
+            uint32_t cache_way_disable  : 4;  /* [15: 12] cache way disable info */
+            uint32_t crc_ignore         : 1;  /* [16]     ignore crc */
+            uint32_t hash_ignore        : 1;  /* [17]     ignore hash */
+            uint32_t halt_ap            : 1;  /* [18]     halt ap */
+            uint32_t boot2_enable       : 1;  /* [19]     boot2 enable */
+            uint32_t boot2_rollback     : 1;  /* [20]     boot2 rollback */
+            uint32_t rsvd_31_21         : 11; /* [31: 21] rsvd */
+        } bval;
+        uint32_t wval;
+    } boot_cfg;
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t segment_cnt;
+        uint32_t img_len;
+    } img_segment_info;
+
+    uint32_t rsvd0; /* rsvd */
+
+    union __attribute__((packed, aligned(1))) {
+        uint32_t ramaddr;
+        uint32_t flashoffset;
+    } img_start;
+
+    uint32_t hash[32 / 4]; /*hash of the image*/
+
+    uint32_t boot2_pt_table_0; /* address of partition table 0 */
+    uint32_t boot2_pt_table_1; /* address of partition table 1 */
+    uint32_t crc32;
+};
+
+#define BFLB_FW_LENGTH_OFFSET 120
+#define BFLB_FW_HASH_OFFSET   132
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram.ld b/bsp/bouffalo_lab/bl70x/board/linker_scripts/bl702_flash.ld
old mode 100644
new mode 100755
similarity index 53%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram.ld
rename to bsp/bouffalo_lab/bl70x/board/linker_scripts/bl702_flash.ld
index 5d6b8c3636..d999c423b3
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/bl808_ram.ld
+++ b/bsp/bouffalo_lab/bl70x/board/linker_scripts/bl702_flash.ld
@@ -1,7 +1,7 @@
 /****************************************************************************************
-* @file ram.ld
+* @file bl702_flash.ld
 *
-* @brief This file is the link script file (gnuarm or armgcc).
+* @brief This file is the map file (gnuarm or armgcc).
 *
 * Copyright (C) BouffaloLab 2021
 *
@@ -11,92 +11,143 @@
 /* configure the CPU type */
 OUTPUT_ARCH( "riscv" )
 /* link with the standard c library */
-INPUT(-lc)
+/* INPUT(-lc) */
 /* link with the standard GCC library */
-INPUT(-lgcc)
+/* INPUT(-lgcc) */
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
-StackSize    = 0x0400; /*  1KB */
-HeapMinSize  = 0x1000; /*  4KB */
+StackSize = 0x1000; /*  4KB */
 
 MEMORY
 {
-    code_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    itcm_memory (rx)  : ORIGIN = 0x3eff0000, LENGTH = 64K
-    dtcm_memory (rx)  : ORIGIN = 0x3f000000, LENGTH = 4K
-    nocache_ram_memory (!rx) : ORIGIN = 0x3f001000, LENGTH = 0K
-    ram_memory  (!rx) : ORIGIN = 0x3f001000, LENGTH = 60K
-    xram_memory (!rx) : ORIGIN = 0x40004000, LENGTH = 16K
+    fw_header_memory  (rx)  : ORIGIN = 0x23000000 - 0x1000, LENGTH = 4K
+    xip_memory  (rx)  : ORIGIN = 0x23000000, LENGTH = 1024K
+    itcm_memory (rx)  : ORIGIN = 0x22014000, LENGTH = 12K
+    dtcm_memory (rx)  : ORIGIN = 0x42017000, LENGTH = 4K
+    ram_memory  (!rx) : ORIGIN = 0x42018000, LENGTH = 96K
+    hbn_memory  (rx)  : ORIGIN = 0x40010000, LENGTH = 0xE00     /* hbn ram 4K used 3.5K*/
 }
 
 SECTIONS
 {
+    PROVIDE(__metal_chicken_bit = 0);
+
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
 
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        KEEP(*startup*.*o(*.text*))
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
 
         *(.text)
         *(.text.*)
 
-        /* section information for shell */
+        /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
         KEEP(*(FSymTab))
         __fsymtab_end = .;
-
         . = ALIGN(4);
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+        . = ALIGN(4);
 
-        /* section information for usb desc */
+        /* section information for modules */
         . = ALIGN(4);
-        _usb_desc_start = .;
-        KEEP(*(usb_desc))
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
         . = ALIGN(4);
-        _usb_desc_end = .;
-        *(.rodata)
-        *(.rodata.*)
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /*put .rodata**/
+        *(EXCLUDE_FILE( *bl702_glb*.o* \
+                        *bl702_pds*.o* \
+                        *bl702_common*.o* \
+                        *bl702_sf_cfg*.o* \
+                        *bl702_sf_cfg_ext*.o* \
+                        *bl702_sf_ctrl*.o* \
+                        *bl702_sflash*.o* \
+                        *bl702_sflash_ext*.o* \
+                        *bl702_xip_sflash*.o* \
+                        *bl702_xip_sflash_ext*.o* \
+                        *bl702_ef_ctrl*.o*) .rodata*)
 
         *(.srodata)
         *(.srodata.*)
 
         . = ALIGN(4);
         __text_code_end__ = .;
-    } > code_memory
-    
+    } > xip_memory
+
     . = ALIGN(4);
     __itcm_load_addr = .;
-    
+
     .itcm_region : AT (__itcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_code_start__ = .;
 
+        *(.tcm_code.*)
+        *(.tcm_const.*)
+        *(.sclock_rlt_code.*)
+        *(.sclock_rlt_const.*)
+
+        *bl702_glb*.o*(.rodata*)
+        *bl702_pds*.o*(.rodata*)
+        *bl702_common*.o*(.rodata*)
+        *bl702_sf_cfg*.o*(.rodata*)
+        *bl702_sf_cfg_ext*.o*(.rodata*)
+        *bl702_sf_ctrl*.o*(.rodata*)
+        *bl702_sflash*.o*(.rodata*)
+        *bl702_sflash_ext*.o*(.rodata*)
+        *bl702_xip_sflash*.o*(.rodata*)
+        *bl702_xip_sflash_ext*.o*(.rodata*)
+        *bl702_ef_ctrl*.o*(.rodata*)
+
         . = ALIGN(4);
         __tcm_code_end__ = .;
     } > itcm_memory
-    
-    __dtcm_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
-    
+
+    __hbn_load_addr = __itcm_load_addr + SIZEOF(.itcm_region);
+
+    .hbn_ram_region : AT (__hbn_load_addr)
+    {
+        . = ALIGN(4);
+        __hbn_ram_start__ = .;
+        *bl702_hbn_wakeup*.o*(.rodata*)
+        *(.hbn_ram_code*)
+        *(.hbn_ram_data)
+        . = ALIGN(4);
+        __hbn_ram_end__ = .;
+    } > hbn_memory
+
+    __dtcm_load_addr = __hbn_load_addr + SIZEOF(.hbn_ram_region);
+
     .dtcm_region : AT (__dtcm_load_addr)
     {
         . = ALIGN(4);
         __tcm_data_start__ = .;
-        
+
         *(.tcm_data)
         /* *finger_print.o(.data*) */
-        
+
         . = ALIGN(4);
         __tcm_data_end__ = .;
     } > dtcm_memory
-    
+
     /*************************************************************************/
     /* .stack_dummy section doesn't contains any symbols. It is only
      * used for linker to calculate size of stack sections, and assign
@@ -107,83 +158,54 @@ SECTIONS
         . = . + StackSize;
         . = ALIGN(0x4);
     } > dtcm_memory
-    
+
     /* Set stack top to end of RAM, and stack limit move down by
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
-    
+
     /* Check if data + heap + stack exceeds RAM limit */
     ASSERT(__StackLimit >= __tcm_data_end__, "region RAM overflowed with stack")
     /*************************************************************************/
-    __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-    .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __nocache_ram_data_start__ = .;
+    __ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-        *(.nocache_ram)
-
-        . = ALIGN(4);
-        __nocache_ram_data_end__ = .;
-    } > nocache_ram_memory
-
-    __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
-
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-        
-        *(.system_ram)
-        
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-    
-    .system_ram_noinit_data_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.system_ram_noinit)
-        
-        . = ALIGN(4);
-    } > ram_memory
-    
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
-    
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
     {
         . = ALIGN(4);
         __ram_data_start__ = .;
-        
+
         PROVIDE( __global_pointer$ = . + 0x800 );
-        
+
         *(.data)
         *(.data.*)
         *(.sdata)
         *(.sdata.*)
         *(.sdata2)
         *(.sdata2.*)
+
+        *(.nocache_ram)
         
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
 
-    __etext_final = (__ram_load_addr + SIZEOF (RAM_DATA));
-    ASSERT(__etext_final <= ORIGIN(code_memory) + LENGTH(code_memory), "code memory overflow")
-    
     .bss (NOLOAD) :
     {
         . = ALIGN(4);
         __bss_start__ = .;
-        
+
         *(.bss*)
         *(.sbss*)
         *(COMMON)
-        
+
         . = ALIGN(4);
         __bss_end__ = .;
     } > ram_memory
@@ -192,28 +214,29 @@ SECTIONS
     {
         . = ALIGN(4);
         __noinit_data_start__ = .;
-        
+
         *(.noinit_data*)
-        
+        *(.nocache_noinit_ram)
+
         . = ALIGN(4);
         __noinit_data_end__ = .;
     } > ram_memory
-    
+
     .heap (NOLOAD):
     {
         . = ALIGN(4);
         __HeapBase = .;
-        
-        /*__end__ = .;*/
-        /*end = __end__;*/
+
         KEEP(*(.heap*))
-        
+
         . = ALIGN(4);
         __HeapLimit = .;
     } > ram_memory
 
+    PROVIDE (__heap_min_size = 0x400);
     __HeapLimit = ORIGIN(ram_memory) + LENGTH(ram_memory);
-    ASSERT(__HeapLimit - __HeapBase >= HeapMinSize, "heap region overflow")
-    
+
+    ASSERT((__HeapLimit -  __HeapBase ) >= __heap_min_size, "heap size is too short.")
+
 }
 
diff --git a/bsp/bouffalo_lab/bl70x/board/trap_gcc.S b/bsp/bouffalo_lab/bl70x/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl70x/combine.sh b/bsp/bouffalo_lab/bl70x/combine.sh
new file mode 100755
index 0000000000..11a925dff0
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/combine.sh
@@ -0,0 +1,39 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=./board/config
+TOOL_DIR=../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl70x/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl70x/flash_prog_cfg.ini
new file mode 100755
index 0000000000..9dacfa8a0c
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread.bin
+address = 0x000000
+
diff --git a/bsp/bouffalo_lab/bl70x/rtconfig.h b/bsp/bouffalo_lab/bl70x/rtconfig.h
new file mode 100644
index 0000000000..fec25d6a91
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/rtconfig.h
@@ -0,0 +1,244 @@
+#ifndef RT_CONFIG_H__
+#define RT_CONFIG_H__
+
+/* Automatically generated file; DO NOT EDIT. */
+/* RT-Thread Project Configuration */
+
+/* RT-Thread Kernel */
+
+#define RT_NAME_MAX 8
+#define RT_ALIGN_SIZE 8
+#define RT_THREAD_PRIORITY_32
+#define RT_THREAD_PRIORITY_MAX 32
+#define RT_TICK_PER_SECOND 1000
+#define RT_USING_OVERFLOW_CHECK
+#define RT_USING_HOOK
+#define RT_HOOK_USING_FUNC_PTR
+#define RT_USING_IDLE_HOOK
+#define RT_IDLE_HOOK_LIST_SIZE 4
+#define IDLE_THREAD_STACK_SIZE 1024
+#define RT_USING_TIMER_SOFT
+#define RT_TIMER_THREAD_PRIO 4
+#define RT_TIMER_THREAD_STACK_SIZE 512
+
+/* kservice optimization */
+
+#define RT_KSERVICE_USING_STDLIB
+#define RT_DEBUG
+
+/* Inter-Thread communication */
+
+#define RT_USING_SEMAPHORE
+#define RT_USING_MUTEX
+#define RT_USING_EVENT
+#define RT_USING_MAILBOX
+#define RT_USING_MESSAGEQUEUE
+
+/* Memory Management */
+
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
+#define RT_USING_SMALL_MEM
+#define RT_USING_SMALL_MEM_AS_HEAP
+#define RT_USING_HEAP
+
+/* Kernel Device Object */
+
+#define RT_USING_DEVICE
+#define RT_USING_CONSOLE
+#define RT_CONSOLEBUF_SIZE 128
+#define RT_CONSOLE_DEVICE_NAME "uart0"
+#define RT_VER_NUM 0x50000
+#define ARCH_RISCV
+#define ARCH_RISCV_FPU
+#define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
+
+/* RT-Thread Components */
+
+#define RT_USING_COMPONENTS_INIT
+#define RT_USING_USER_MAIN
+#define RT_MAIN_THREAD_STACK_SIZE 2048
+#define RT_MAIN_THREAD_PRIORITY 10
+#define RT_USING_MSH
+#define RT_USING_FINSH
+#define FINSH_USING_MSH
+#define FINSH_THREAD_NAME "tshell"
+#define FINSH_THREAD_PRIORITY 20
+#define FINSH_THREAD_STACK_SIZE 4096
+#define FINSH_USING_HISTORY
+#define FINSH_HISTORY_LINES 5
+#define FINSH_USING_SYMTAB
+#define FINSH_CMD_SIZE 80
+#define MSH_USING_BUILT_IN_COMMANDS
+#define FINSH_USING_DESCRIPTION
+#define FINSH_ARG_MAX 10
+
+/* Device Drivers */
+
+#define RT_USING_DEVICE_IPC
+#define RT_UNAMED_PIPE_NUMBER 64
+#define RT_USING_SERIAL
+#define RT_USING_SERIAL_V1
+#define RT_SERIAL_USING_DMA
+#define RT_SERIAL_RB_BUFSZ 64
+#define RT_USING_PIN
+
+/* Using USB */
+
+
+/* C/C++ and POSIX layer */
+
+#define RT_LIBC_DEFAULT_TIMEZONE 8
+
+/* POSIX (Portable Operating System Interface) layer */
+
+
+/* Interprocess Communication (IPC) */
+
+
+/* Socket is in the 'Network' category */
+
+
+/* Network */
+
+
+/* Utilities */
+
+
+/* RT-Thread Utestcases */
+
+
+/* RT-Thread online packages */
+
+/* IoT - internet of things */
+
+
+/* Wi-Fi */
+
+/* Marvell WiFi */
+
+
+/* Wiced WiFi */
+
+
+/* IoT Cloud */
+
+
+/* security packages */
+
+
+/* language packages */
+
+/* JSON: JavaScript Object Notation, a lightweight data-interchange format */
+
+
+/* XML: Extensible Markup Language */
+
+
+/* multimedia packages */
+
+/* LVGL: powerful and easy-to-use embedded GUI library */
+
+
+/* u8g2: a monochrome graphic library */
+
+
+/* PainterEngine: A cross-platform graphics application framework written in C language */
+
+
+/* tools packages */
+
+
+/* system packages */
+
+/* enhanced kernel services */
+
+
+/* acceleration: Assembly language or algorithmic acceleration packages */
+
+
+/* CMSIS: ARM Cortex-M Microcontroller Software Interface Standard */
+
+
+/* Micrium: Micrium software products porting for RT-Thread */
+
+
+/* peripheral libraries and drivers */
+
+/* sensors drivers */
+
+
+/* touch drivers */
+
+
+/* Kendryte SDK */
+
+
+/* AI packages */
+
+
+/* Signal Processing and Control Algorithm Packages */
+
+
+/* miscellaneous packages */
+
+/* project laboratory */
+
+/* samples: kernel and components samples */
+
+
+/* entertainment: terminal games and other interesting software packages */
+
+
+/* Arduino libraries */
+
+
+/* Projects */
+
+
+/* Sensors */
+
+
+/* Display */
+
+
+/* Timing */
+
+
+/* Data Processing */
+
+
+/* Data Storage */
+
+/* Communication */
+
+
+/* Device Control */
+
+
+/* Other */
+
+
+/* Signal IO */
+
+
+/* Uncategorized */
+
+#define BSP_USING_BL70X
+#define BSP_USING_ROMAPI
+
+/* General Drivers Configuration */
+
+#define BSP_USING_GPIO
+
+/* General Purpose UARTs */
+
+#define BSP_USING_UART0
+#define UART0_TX_USING_GPIO14
+#define UART0_RX_USING_GPIO23
+#define BSP_USING_UART1
+#define UART1_TX_USING_GPIO26
+#define UART1_RX_USING_GPIO27
+
+#endif
diff --git a/bsp/bouffalo_lab/bl70x/rtconfig.py b/bsp/bouffalo_lab/bl70x/rtconfig.py
new file mode 100755
index 0000000000..ea1198b93b
--- /dev/null
+++ b/bsp/bouffalo_lab/bl70x/rtconfig.py
@@ -0,0 +1,62 @@
+import os
+
+# toolchains options
+ARCH        ='risc-v'
+CPU         ='e24'
+CROSS_TOOL  ='gcc'
+
+if os.getenv('RTT_ROOT'):
+    RTT_ROOT = os.getenv('RTT_ROOT')
+else:
+    RTT_ROOT = r'../../..'
+
+if os.getenv('RTT_CC'):
+    CROSS_TOOL = os.getenv('RTT_CC')
+
+if  CROSS_TOOL == 'gcc':
+    PLATFORM    = 'gcc'
+    EXEC_PATH   = r'/opt/toolchain_riscv_sifive_linux/bin'
+else:
+    print('Please make sure your toolchains is GNU GCC!')
+    exit(0)
+
+if os.getenv('RTT_EXEC_PATH'):
+    EXEC_PATH = os.getenv('RTT_EXEC_PATH')
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX  = 'riscv64-unknown-elf-'
+    CC      = PREFIX + 'gcc'
+    CXX     = PREFIX + 'g++'
+    AS      = PREFIX + 'gcc'
+    AR      = PREFIX + 'ar'
+    LINK    = PREFIX + 'gcc'
+    TARGET_EXT = 'elf'
+    SIZE    = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY  = PREFIX + 'objcopy'
+
+    DEVICE  = ' -march=rv32imafc -mabi=ilp32f'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
+
+    LINKER_SCRIPTS = r'board/linker_scripts/bl702_flash.ld'
+
+    AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
+    CPATH   = ''
+    LPATH   = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
+    else:
+        CFLAGS += ' -O3'
+
+    CXXFLAGS = CFLAGS + ' -std=gnu++17 -Wno-multichar'
+
+DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
+POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl702 ./rtthread.bin\n'
diff --git a/bsp/bouffalo_lab/bl808/build_bl808.sh b/bsp/bouffalo_lab/bl808/build_bl808.sh
new file mode 100755
index 0000000000..3a03b6285d
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/build_bl808.sh
@@ -0,0 +1,5 @@
+#!/usr/bin/sh
+
+scons -C m0
+scons -C lp
+
diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_debug_v8.0.7.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_debug_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..21d90a07cbb834589c8712e94b7205bf12c4390a
GIT binary patch
literal 56224
zcmeFadt4J&+Bkk@l9@@k2sj|nrHYAyveu%p(u<`NOfrC%qE*2zZqd=&?QXYqt=0CG
z77PKAOV9z4sx8_ombW+ImDKK9f^t)-qE*1IZPirKRvSnMp*u`@Y}z_xpZ6
zzrWN^l9}h6^PJ~AxAUAUai-Zx1VYF(-NXkVf_SlPQ1L#pT~Q)LG=M_U&2p%5{?^>-OIrwxuXO}&OR{GD64yL4cdZquW=o=ao{il`bZ1wdeNG()fSb|m-
zk`MtJox;7=Yil$BauPmMyrs}
zg+z+JL-5r>`_Pk?bs4(g22@?rfOPYF(cyvtn?68OA90Xwtjvme9i;cqjUN8ZN7tP)}f(CC?i$h)ux=V^UN$A;s^Tkhzj4E@aQm{ubIv
z{T}LjqRlebQi`P3M`R`%&s+X1=6Q31V}m!wrpZ2H5u03tmOL%dgTj*7eWA$0gta=;
zioz|4F!>*%oI~(JK~%!;88qr!_=6QPQJYLW#5yN|b4M#e?ZlsPBK_xdNH5a
zRBhXe%)5M0Uh%JS5!ugMWUi%MBo4drL__|lIvdUtk?mPaf35h9k0tJO;nyx?>-WC!5J5&a~DLXWF^vS&RMtLy@r<|xLc*qLMi+UyAWEug})4v_Pwz?sIS5(zPH0e$d^`49Mg
z6F%@8vlf2gGcFW!?*n27%H=C9LU1pVDWUi)v8<9CD>B4_ykJW>OL@gBb~80VFCAbK
zEk_c@smz8+h&)N2BHPFgtrtPcw55Ic$i)B?$lFb8+74gHpOENzx0fl5laRuYNr=AO
z*a@L|LHkAv!<0T#RM8=`rdDRnx@O_Ed%Bw`1MuacdokI!N!K8~k~DK2-K
zc|A$-Vh%GPx?FyaG*@4|zcZ~Xiluu8ckqtOO+6wthxD|dykMq3Yw?-oMCgs6TGrw{
z+lkUvJz~S{nh=_4!YzspAq*#`Rc1X_n`w#;xiY0PYopEauJUrG5$jy|V;eyuCLy40
z3N9rw+*lpeONz{S@4SYJa(E}JExqKl(Abg_6y%?5=65JMP#*6x>^MGCrBXS=)0Wym
z2e2#}k}kV>jk4yN4uY-7?Fu)aG{za-8dDV2IM;Yv^%oRC1(;&pEk~ImWv4EyK+`73
zTs6-5)7YW9Vh>g?&qezklxc${9)ZVtB`OQ&+i3yqnrnfa1loQaL$Ea%=kFiuX$_WZ
zFGzq&I6T#%qB=(JA>24xUjnb^*V7i2>X-&p
zRg%fGroO>}VBz6Dv`)(Ho!pCaZ*97>E+dn_Sew__n~}G`g}O0j7U#-?{?fvnt|j<9
z)5VOuri&TXIelDS1rt{0pqSpiSm;|ld2#(R#)evPjY_Ex5Xw}_n76@$44a+GzM~=p
z+E2-@xjZNiL!`K791<)lA7MVN)X{d1RkV_s@gGeWw!h(3{Z1RHThK=4J$on9qN-ju
z4t-#~KA3*}u{|=jVSktfHH09H$C0nP1-}X-K;jXr_?#3yXUFr1&yhc#c7t
zru5*cB|%m}1vy{ehqP!J48(AVkP&M#2^b
z)#T_bmk_H$$T~LnO}V9UPda{}c9-3oNYH=OpWm$n;P#
zH~0A`_OMJ6DVRHz!s{i#i(atWAT&9Pr2|o{#mv*_;te6&8wr0anW9A$s!Gz#+cb|{
zcs*fBV%&_X8Jd|oYQFwtq7mX8BA#VhNs)>sMHNy^Di_}43HGIUh%(Il2*fH!AV+EE
z9rh&^F<=u)mP6WlbQ+#)2w>!uTA?HuU?HfkmIa@+%P3sDs3iEYrjOz$mFEQqkEWCu
zZswIpv@ipX)irm_MkQkDbL2p>@Lq$`%m<=fMohW5o*582gS<2OUGd{*KUOYM||L
zO9n0We&HuU9>>ggbUXiXlOGn_}2IcKQ|~v3i#<;6DCp_lz?hR3U8DE
zPm@T@TLq>a_$#QGFrlXueSkninXxG00H#nVwV^yrA3X-mu}#j(>fUV|xxFy)o(=LGr^%4=@O
z5H_p4gauuwdQTJb-W)ugT?5t|qVlQCsa9P?EB3I845rTL2z{}KrR_AEZ$d&@^YEg$
zvYk@Shg9T~*_AmURiIm&u^jXa^w(1KM_@gkdUWe=
zg5J}EI#m-_J+28I%*hM(pB`Hxs$7HMsSHi1nn8M9PA~y)8=J_tA)a`}X@gLf#?l|qZ^Kpub%)<~rau6SKTFu@#?U=eaZN!Nvz^7A3
zqq0R>9|zLqR4O(r^YGM0;t7#KTvWEuQvq5DaLz|n+C@PBaW38*UZ+=#$q7MAb_$6LY)H4hkDR9$`e-$^oMo7dhpj<5!|5+e
zwc!*IKx>P7p=ZnG*Pa+X+XB6+Z5SfN^{R|OeKw;rgY3H66d?&a>A<>qMphM!lJrtN
zjh8Ysbk*j0b&7EmQY0$?E-v^2RcBu!h5u;t3aqQnzRZ
zFH6^+fUzXQ=&Q47J=>9ts&g29NZq_TOot7(>m3&gOVBVObt%TXt>Rr7JL#|7wVB(;
zqIr5Y`3t0DT%^!_i43W`zhx|K^4D&}?fQrxYtyMNbGn>MTuL3=o{Y+@xZODQFb^?y
z_}UZD|M-VOt`4r6ZsX?Fi3^eu&J$$Cv|E^5TZ*wVM|k^^GGrE5(SKZ0uIIPRDAud3
zx-Tvv?^1etSz&RV2okK^EG*rPT4z*kF5>g2v(yN*zRA1cbcTiYKHUItL2Q)z!&h!>
z;ZO0DQRuydI-2kpXI)0foUr*sfTo2$7I7r8d3NL6`UMB0vV=EXXziShP0t&!dW#R^9hIqJt&?hNmUKl6zT|^=A^WufROC;73sAHfr8uY}T
z%FQ#dr8y`pp3M$M{>@lZKu_$~K8{YY(TGsQE9qAXg~4_tzZk#wn@l99l0d{Q}LKS5pe@gD8?6
z3B9ih`2+1F*pgqDUm#cg_Ao-{cN5XW-gsZ=UO<99*#qOvW`wSLTOl61GnluaQ>$CkK{&bwZ~4~#ds;iS7Uqrh{k3Cx;YAnf4c4L_
z`o!O_1YfMxF~NEr6{HtWC!+#uh&|qpr6$?n+hBw7V1xD)gJ=mxKFu&@$k0%+CGmD2
zE-zTAP_*--*wgz!`WI#CkFC!BNw#-M`kf;~`R%;0k|93gagEbvid5Ds8q3<2weizh
zrp2#qek68nQV`^Dp%VT*hPCjI#K3_b3ooj=6d@e=p7j+-cxO4nRD{UV295M-_U12v
ztf!Wy043hMaz_#;wgDa3@2qH32HHJzcqc1IJ8s{+CFU@)aB9*A-xUVOZ_3O
zMdkQ;&#k>S^P@_tq#&peQx#*XMtQ2HxO)D7gWe5_vr)e{e|Ge?Nj2tgWE}p0bDnR!?&o)`ZHyUf!0`N
z2TTv)*pLw*i>CjfJu1$-Nws4pCoYg>5tl6toW8d`?JD4;W9#x;`wj#ZRA-;&6ws=9
z5~qW#D!VtN>q_sSw@O($1U=q-qPE%+Bx`3%GWhvmy^o}yog<~bZxDOAos^G#ra^>0
zNjol(@P?6>oUs0uQL6W+8btJha@Vn+(+V>gv(H&=v9dhX~|
zsW|XtV`p+K_yMUu>AR>3vETJ&@Ai!e<#$P%{E4K=7JhB(vcFenf5G`$#rgA*Z$Y3v
z#V%n4{tMS?=s*svLj$%;iKlCj&T^5Q$q9FM(XwW$?9eA}>eNh&2db&H&D5SScS~5X
zH0*DCp$Crz{oZa1Ezsp$+2%(SbZ1x?x^X@bY5
z?w6(a?%Fq3%x!u2<=Mv;9C^OE;AQI1
zqB`*x&8di!cm$Q$x}^R^=;c1m61|O#xZ&lMtoKtHm1So+#Yb5F9P&=xIW_oOXy_4TNGB^GnF7X@=1A!d52s6vr~MH1d+opFiTH6^o4oL!$;bUsjatj{mg42dN$&o!B)yA6c?AFkgG_
z{r=t$1*Sna^V|zg+#eq)4QrMAWCdTZ2tA%MPblt$9#~1{
za~)i>VOxA+_Ln76{;Oe0sV&>$kCbj}KFb{`J!?N;yO(o9HWS4%UB1FH7mSsJ_dAu)
zYJcsBAC(w0@pDo9DMLqm)#d6xQiib6qtGhr8ao9X
z_z|#lc|!_W!hb+3l^+04c2omK<(usf8}A*rpLCDhH_gPOb_IV*x$H(L|ACA_?Rd-8
z`oEVAmP=TD!(KJ-_^a!t)_*B=V*kBu)uR7W;wWz|2a&dY*?nniV2p^N1(N($KpKt&
zTP5w%qEpJ9%(VK2d+){eIE+ueES**lBYkDJP0WcIU~@(wJiGaLhrar|V2Z)dYfk;C
zS_nJ?Bh2x(d=7h`B(B+x{f~xD561mVNPS)P30}BbL7(Nc;UE7JTc+JPhA>Z1l8W*5
zgc+ou%b%d%csvzkd|Tqa&rB@gCD}(L2|sfzEU73ywPh_gd7E}m77<&fQ@aBN{NuT654Fqcy~$0p{oM~{K8%K2YC5)|KjVDDLo#kM*A?Tll=<9jOLYzQ8SUURz64!<{~-1@+VV)JteKN+XX73D
zIoEJW$HT7AC0|s*fIo4(;rcxN0A)N=O$0<7smywK8O()V$K!#Cjj(R>yQnPRx+Ej%9LrM_JDu?F0(Jhy2baGOv-s
zWgD#z5M4pYlBubu8*`aYsOl0MGV=`zpEFTe+mEI!3@{2yZRE^TY98#33`-TdZKP@@
z;15!zKz+kiEyNY@AEd9biqjbIjM&4=EZASrnA=*qM;TQNR{9HJY_NsGxCXBi(v7%=
zsI1H;70h=R`D-j1176*E6}9@A`5^H06pT6+SeA_s4^v3zqY26hOh7?Ask&v%MzqM3sq1eVK<3-zcrNQpVm^Wyy
zP$S2=_FIJUMD1C9NJ8|&*B6#q^#QT#GvjgFR*#_TqOzjTynbfA-hbv-mM5Vvc+_0Q
zsajAZ7AD#s&Yzf@udkk(jl2Wf;vx=KX2I;Wmj?XbmnAgN
zJ?edPWCBv`&QcS`ouyh$KQdR;t0xz0Kh9DKK|M(Ou~J1z64+!Q6R;HY0d%9L9?uy@
zWoi9D>KaM%c+NtB=hZC==efbn5dA{$fgw=G=DmCs%!Mdb+KD|Xw=7pIIs4+b*~fOa
z>^^d&`B>x0`nH4L+W+|d%N>7hGxMj3sQgd!H#+7#qxjF6Fel?fnLqI%cFfR@`wKxO
zWG2KOG4nnshz~VwH|CmP?3vpcCZxGELN@f-SNllt#1kBwEAA*NWs`ZIa8TiFmZ!<+)Q%y
z$e--m34bBA6W5a3@D@s|IZFu_*F*@L*C2C*4=Ffb9HWS6A%#D;jTJ_;5$4EzQn=VO
zR>8NxNJaRa3n*zpP%DA^p+Sds!pE?ZECdZ`AQB)47APWTl0tDi61*TM&?c1jg_|Q=
z6oS|Zzxh&*782T}G>@IBlycH8BotSS6o%VI0<{!SOW{`G_9({qC^8MJgP|R!7Gia9
zjve>}{rPRB#Uwn`hG3P;gi}3GMPxpdZ-MeY^y=UW`&^@T0_2}~TX`N!{|ux9H(He1
z@Q)!qvQ8UuTe*?fj)6SDc}P`YTE#bFkRZ|%OC))?TOR0Ans?=+bd!1aOe9!qhAChz
z7-+?%2zEV;XLtI*jMeE3U9tS(aEndE!jDW0UP$
z;2Z;-V}Mh{#@%D%p&vMd)8Cx*NCRHiQp36y^+%Ta*vom&dR~8pRnGJxOl3y!m*++u
z#y02UrJpKn`;gXHcEy?_08@kyBeqAN)l9_qg8xNYc#lz<`FyXvKP&icUS^OxHA|pe
z%8li?o`)xeo+oBKvWJ>wTa8k*=wl)jYRp-L@jB1F`mOLVHJLEwg7y6c-UsWVT39OI
z>xroscpg@s9f{a^0a<@q{6XvB2ze)<&7t8pQj*%C;*qlg!T~%G!Y;L5z93?ef4xdX`3m8n}
zl2S9|1gR%FyPgrF3LO5_RYhcr8erSZo937C=7a5l&4yo90o9O}58B)U{U5|JtvJ%YjmG~Sa6?MV-BRa`5f;f0MEGE?s(`~P
z(66nKkAZxk6(6hI)Jk;Bv6-P=;C&?RaCZG5epGFS7UK9%yR!xSZ(oL^jA=82mn9pk
zAu5_$uQ64bR*%?i_ua7KI@T#?*E>avVWr#$_6zt>U{4-(yj@+7K|0iGI
z2yAa1@&$Xb#8kVmv?QN^Tm0DmpjoH)f+md|IM&C#XlOH-5^5465;rH(Gp_$(N$Sbe
zszonb;uejC-dY&$OJcf(_m&g5Ul884K}30#*m!94EQm||Zlm;Ct)CBCRx8IoxS&Fe#BJ|Q-
zuU_{=GQN8tZYba3rQJz*X+PboT9+Z_=)H=kD|XkZbve6{u(}B;b`f4%4oxkQ=X-H%
z!>*xec6A?-H+A=fyb_yIP^*+8?7tG!H}S7h@V=>p^#hobuVu3dP_YblM8zdhU!B&xP~(u)4sl%XoyxWzXC2_ai*ag(=f($4jt9
zwSdci)^~u5oL@UBUU!pHZ0BK};3}hLgU2EB9#hZ(Y4nKq>r~%_S=!)BsJb(lAo!l2yqQ~`VFworD`O^_#1=OuA8WO`3*!dj?nf2MMZWH
z5&!gb{p{)x1)&?fjH*Y{gz(T0kpD#_9=kcHbNzyJotII7$}y^WKwH@tsQvg-AWOgY
z*AoX=X8oWSgZmQmp6vgDvW@>rng1w-sLDa&&71!nb-|cAlSCb?29Wu!G!#J_urPy5>W*2%(Q7S~ksdiz#S_!MqN}cypdf~!SO7vEe
zCoMY5Q^fPxGCk$X>z3zz=`~HOd6Up}-a@&IHv9^z{^=GHbJe%C;R_+sIaUlKey``>
z%}fxPE`@ljM&IPqcL5UygH`>e$6J>3A)<#YuQ0@IiqCTmx664
z5Uya?Fl~50!dff+_9$;#_=tBgb|J@$lre@sjWLQ!561mYmQs=nvQJuOm&i1yrOG)o
zo|NW})SjF>I*ETf^2SlUTp}%Ibg9#ADmy+4dYf
z{{k!4KO(lBAqdGfecC$T+W&@_-Su%11*Ev|d3*x7`(9UMqbZ4Kd4Id*w43bBiw
z!6?=3Gr)f+*yW5Ovlgfw0BQ#SLI8w#x;9l`JiTLj|GRH)Ek4w7XkCWQhQf=dXY$^*
znh8Wxo-KQvg^2-J${%7Plz87C66ZG|v6oVOZPgNeNNgX0a`W;)3O91haPo
zyPBcr1AQMrI$(@cE&=JFusV_9sBLxYGCtv>*27$b66Ryi+voyb_|>Ld8R`F|=z0u^
zn`4kJxgD{q7?r?M4=v6MJtPqHL*~f!Xh*yvQU%=1Ap~Lsbv|C8MkruUG8q8=P|Pt7
z7MKX$@k`&Wm66d;&aYh=iJnZit&9wRa+ysL5s%VG=+-nL;bB!EwQi18Z5|D>Z154%
zYLo#cA)~=dSX@Jbd@T(s;iVcR6i`aaB;+;F>oR;zLIM5_mGV6-eFvF@oCfH}Cz*t7
z!19+GG#=;ndPMpjYZBHqc&*EL0>Ak@EqyoUyJfijm5+OJzExGA<~i2JYj%aK7-tF;rqReN59byD=*F
z(=0#K30z1^uCtzj2cM9yKps46DJy<|E?2gcbMf?y3Iw{wSSJvrcQCaT(qpdP)Vy-Cl
zAIfML_xP7N-TlES9aF+p$H1-@%UHco+>0E8S8fl{gWHy>AI)1{)Rr^R+VV~qzcJDC
zt@sJoHM`M_`)+6{v@t6-_h8o7JP|+JLLV!O(Uy;YtgJbnI}j7kErB^Zc@2_Uyu)@s
zemP!^*K1l5n`5)$a?kLl^_cp`Ty@M@ZnAQ&TDNoz%q`|j5%SfjnS0`yC5C2h2;ap6
zzr}YiRh3y3&@(mb$=pn^s*5~*Y}I3Dxw-1eN)Og%uKTfOZr0O^UFv9zX>q2T(p=p7
zA?ju~#$|n#Yg#Wd;Uv}#Q*HrZ(f}S<1;Nz$VCwXb-A~;||3ck@gXTm%iFu|l5M*Um
zydFync$bU!b1hhpHO90-qYQXVEKMLfINeeMu_#{*K8)%>@~$aDp%>IM`ssV?kymyH
zs)sn?S?m3G^ryM$pQZa(`s;M};-wb<>F+~0Wq$lm^uKlw{Tp@v6a71$y0;#g+Nb{w
z{rZ4JyA&Tn&lkHsD(kDPL<>kjK{uYBqzzY3*$5goNf!@uv^dJdbA%W7;u%}deBoR=
zRX@M5ikejjyFd2LFVvPdO#xk=LL8UJIPrSAv3rtSUQevryDq~#&ItR*`Ucrmy?$e-
z6Y;{!AE1~uus2oJyo9FWN)#y+y2H$+alchXeQk}Q(Gy^k$n*`$_Cz0>nmfA@
z?AmXa>B+3hEP@w)>O(Ow1H&>+OR{0bLeb73wOROc4mp>uqV$E(Mh1Pcs1Q~k+^uZp
z#9U@d@6=}QaIE-7J*H!89}>>zkoQYfv0IJU(nyq8>VF7!uGO0Fz6Zj4o#f48v&_kQ
zGUCX=EbP^ux7Xwxj^znH_N~fn6&Gq-F!gB=3CvW8-9q)t}t(
zRqkk*kC!k?^YlyV<8m9b;!?YHD(?Hc*wddfA@~7+7XVz!|Ni~(jR41V
zzQ274z7O&@036plYTFPz*A0i0EnV-wI|Rq=!uc`$Uiu3Fei-1paQ@Pv{Fr_WKaBHl
z9)cfs!zKLp(2w(D`XzpfL-{d(FrTINZXAMRI&r%&d{og89OK9Q!F+hX@P7DR{AELM
zOh1N8{LfQy7C!c1gdNKs*X$`VSR#8jta}fyIMR&QcI34lywdZ>@A29XUg@daFforv
z7~plx?+FFZAi;;3Jdi*oRx?i#<`&qcJ)=7KEuz|0N?={Pa#Y3n@;jh*tQE)mqYCi*
z*YJ+HaQtSa^p0sbf!|$~St?GKet?k6;Feqas(U^puH<|0V6A($S1yO~l;QWDsAD+2
z%#G*S8*)9k-t9R3`gLCH>G7*}4WR1P1L%qs_Yi_;7!Py!V{l2#PmK9}s0VzN#1)MB
zeTiSP95AN$H>fz_eXlVE2F$+_$cb&I#7F{1VV1BLN(0aJv2;h%)t2ns^52i9VCaY7fp$u}%HYnHZ_lpe2Shh>pWw`aK49Akj`4719
z`28%yu}zf#e6I)p6&a3OhVgh>;0G=6v<&Cp<;j0(2tS5gXST{NK+`$1SRo=B6EVe+#94
zW&f4ijvW4Nd0qqb=wt29
z9dD@*YY`r4$&nmh_nkBUbnW;RaN2P=oPcCm8bRdz>4x>{Oe5@Q9}XuZSvVod;>ZDZ
zy$^?zk}RB(WZ{%#fYUw*JLnOds$3uHv_G?N&U}cVmD>z+=I=dv*0AHKz^IkbQl;FV
zP&0r7dx4V>IULEBsl^h)eIJHFU$oxWv;%8A$VawqsYPE1!OIls^I@+%3wz~RGfr@+X0IGJkDKa
zoLx^IoQwU)`Jw1X@^43EEiK^#ByGenKj>LJIJcVuBtQ4rf8jP2tFhez7VwE4iQp2>
zhJVHK+17u>^6cjlmQWeXvrso~wOoVsE6ibA9>gCTPzrd~F1Zdd+xuPF$6ISX5U*{r
zmw)vu+~>$X6!!wp*4(EVo89{IkNcooWY7NDmvUKbgSf}AR^j^d)y}TL5=>>FO0Lxj
zwZdD7oXbyoD~2@OgFFiL%UbB6@!5SIh=;~UfphoL==X84LCzyn_h^+z+F16Fe(HI{
zvVRsN`R}CusQuJk91{N_-#z*Rk(T_1arnWT2Z!vRWX*B@{WtC3DVK7~dzZwGP|$db
zBr|9~=CB_`S-=g@1I#l_Exds|F*hV?-5Q7Uz6ueOM=x>iS0PfuoWLB%`CkPM!QAt3
z+PcI2?&h@>^bn_exNUtOq;v*wxb+=tHsCoo2z?!nS!GGkZ@c9SwGHv)vn`%C%#-5~
zYhnAqzFfAZyY>O?^Q2&I<=(X%KWJ+ikJCJTx~I&mAA^0HfX)!yYUeiC-w6J#I7G+v
zqpvm>$AwIHY`avmk#UqZ-64zzYJPjC1WV|D9dYoX`WqVmDJ!+%Q{J_2J_vVJOxavd
z+ebD=HBUS;xn=6HCtG7r#+@>?{jKATZ{Irm_V+8(l+i4ad26K>MZbGQeC``0-q4|f
zIAQa1Bzca$;PvCMOT#aZ`01gmBY%nNns|M3&(yvrZ^qt=yKTC2{aoLLTR+~pv~q0t
z6n16rGo=cIM6+V%I&s1D-(X7Hl%`o+wK#6c$t6pK>jJrI(<;pyRd2+tKDm0yn(J%m
zzi$3(#H%&00wol_e`9mp%A(;@vf*1ZWjB12Q`T{t;xyB%rpFmi8kd-^o5j>`Ty@-J8{mP8=CMbLNhr`Tu00h*R6AEcMeC|4>d@;
zdot4QiG!U_OOW={zaee;I#RoH6RG`hC#l_CMQZmPB(;?%N$tlMNbRTBNo_evL0JmQ
zQc#wHvXr)RE(PT&C{ICo2Ff!~o`LcVlxLtk1LYYg&#WBl5Az{A(aNz1=J$50Mp(?6
zy1}T-5l7%YlHYH@9F1Nl@wo4W7hh=mqv?+|iy{_nPNh@(X1q9~Ezy(+E7l2{Gxg0v<`YrLCQ0cl9M+^)p)_c#qkl?ciJylx|uQQF!`O-wtK8KKk+
zrO`f6h7@y%O>9o)TS8|i2`8aVe2RA)pR%yl^R&$7d0KQAcHZXQ%BS?(Y{@7b@IAg|
zIv!Woy|`lQmP2fI-(XSGmg#r|4Wrrj=3BQM+VWgHg0ydn+P6G6$pnyZoObIc79*S?
zKUZ6NBN9ccm*ZJ$CK{gC#^i8FdRrUAWSmQ#ZZHVP5nMTU^#Q033
z+Bh1%eU0kzuzDXp0QXk70_&Dvhf^Bb39dlGNG(3U1Mls_bwTJMQ+1azM0jX$&s#@W
zOcdM{;cGlS5&I?i4viS#D%`z6HN1!S2u2)q+K>OTa!mLX4Bu&inS*kt{j+N~#`sGR
zd}|A}19*M)#@J{H0wwYL&+O|x&+Om@SWWzd7arp1t@y~vGV@S@3HE0pZ&MH4deDQs7q~*TjaH!i7*#TNgT%fqmPk|rJrNIb8l6_YG+QkHseQBkf()J^`Tji0=_C+
z=&Qi`40C`%#)m09yFD=*?(qm33*)TdYQk$d(!L=w4X`iHCC?V-e-a
zX92q8oaU8ywlzkH!da!#e_A{qy&c#(t$A8JtTb89Z(URv-7ITQ+V_vg!`=v@>>TWq
zxPx1Q?O!|26}ZVjz>F)bt71*w&CG!_9zhi-&lVAw`SoF|*f;g|21eTJgL5b0y&|l!
zckqh!JJ{ueqQ96yQ=6z|TNf5QU3R!Y?Ct&aA$nHfdo=q-pKE^M=SRPo0jHH=1^J7k
z>oNv-;g>2Dhk$oW6t0X?J&~;g-tjE=8}+=EBy<_yeE%Fy3tc7}(>4
zeeCnFa~#UVFDlS}xZ59>vMsfCK(46Ek_s
zKVuk$H|(I|I^by-#WJP(EkDFWz6?7Qo9a4#h+zU4mg#)$=AkcUz{*Mgz=%~=_$6}p
zhzwdP+;U@#8Rx+mjxoZ`W=u>p#^|eLndK73k!t8|GciVgz}WsQ5354V(V8WKgOVf(=rwQ7{e97W&0ds@CLea
zxO=(v2%JSgp+di>MXZEP&-^Q{90^w(;3_SeUn{qtyf-)CmTP99=H)my(@Vfp8m`$3
zQde^eZ6VU`ktVBfqZ1M3IOdSok??AbB(v_$a2um|CXLBAtHQo>G^F{!8ESv?S(ZiQbsLlM#er*@362jnj$|1AWiMYf7Kj$1VPUZ66zc5w{GDqFN)c3
zhV!5B4phZwo<|YI9_U^)i;2*&z{Rc+ieLC|HJ`-~t_6Xp8XJLoJrsFfeSgK)%
z7wxt*QK5l)*Uw6
zYHv*K?*Q7_>AfG;1!0!~>=1pYW3myi^}LFb7U3Gg;8uWeg-l2AH@I&x|1+TOJKIoN
z@7AzGa*E>&j{9)D_VmS=A3-bQF)tzABd_+b`0+;Ql?FTzds|pMA^Etl=J9Tg%Qzht
z|K@LC+^Mj5DEC8Hv%EUYLO-l0-1MB3>w?|!fLRQl5BfcXt-MvPA>AsL27pPDNWW0`_ZuYY-R7(@A8$++iUOXIoC{!ryHSdolM#^cWcq%
zY0&;~ML+bWZhdN!A+mkSu<}M3cI|GijD~6PRh-Oq9_$!L3~v4&0v*Bq!Yf18oCKo)
zh_m+e!FpPTkDO1alPK%K_Ko}WWvf}nWu+VY!R|d=4zIA^4q^V*w*^9x%KwLS;C%xK&a
z>HV9c=kRaQH?7Y~@5hUz-=gEKGo<&UMbdB4(N0^OSYe%I?Pv$esMf(4IvioDil?(Vy~jmM@9q9VmZ8I;^r4RFutrJR=z+mk
ztaGd#Kvg&FgCpTA{i?!+g{?ppP#KM%F=Y}AD3jiSGU**CliqVvS}M0vmfoRq*wdwO6m?$0_Ii)p!guV$whH!Mc8`2voZ`u6
z179@&zG_IyVbgno;!&_`JM0kn$?yN2E>>|KT`c$WXpnh}L_=xk?SG3q9BYt_`x!Lf
z2C-2zXn0@@1HKYspBSbE><=QKztWxtPo{{1>G
z6ngN5ak3TTJ&tbs%!mDp;BBzYrn+Hid3Yx@hF;q$?}B#QXD+q`MFqp&qx*ia$7)aK
za0OV=fJwoF75%PV3ED|vi-Bk$$rFdjvBPiTkm#F-+#CslGW{|~5cn~$c;E;}%Qa75
zC&IaI$M4#2gPy8o%>RcdD`}C9;ipc#6_X2ZO63YX(oXo$`MI-K&+rUqOwB!-zs%_kkyzS2P!1Nwpqa_B;gbwe!
zjk&t*If@tFy#(>L%gKV5#jq{kEV8k%+tu-I;~jw40zCSn?JT!=DfK6@GY6fud+@Vr
zb%v*oj91Tc)vib)w=+F(RZoENPqo{?-(B0f&F&s8z9P>LkO}grhLHCE;k|$I9XHS0
zEj-@E4SVcJxUsM61t|)^wq>JXFDQ8Y(^jn0GPd%Ue$#s8qI`C#0c9LqycAOx(?8Vu
zbIb6K^c{H{CCVtkJ?auZRY@2uiQsDqe5!KspP(%-+n^Ne_V9+$=%#rJA#f?7HXg2>
z=p2G(~qR00@Hj`^4QuBJ3*hq
z6*AS_B52oLj-{o_<4@1cBjgMUW_e(g0{F15wLF*p221z(vB4J9T>!e@Juu=-!4j&s
z;BZ09H~G(X7n~`;&-vf9JnMOGIi7#_IsbUejJxoo`FEf5kGAl4;Z6DcD}{5ctE>wP
z);Ene1|Pz)$f3C&8n$2$5Ao9~>))sZ>lX0%{e|-jn%g}&wMlL}f>Bqu)IMkW_R*XfvXZP@-lI8?Y
z$z>45q+5Mo6yYXfT#8K|i!=;Hfv&EHH@I*b_9ep%-TAHR%->?s8a+M(8E=5F8kl=!=s@qL;9(4~
z+r8Hh&-+0BlXESTVj$-hkkH0V6F$8OIV%+P`c-U!exq2RUp4D0So1%zuNu_=D@?sE
zzgXz`-*2(NtP`9Qt5VeaqJ@_gku%^Fj4xVjuA_ylOR6d!sD5`f>|VyBqM>p>*yVDy
zpDLPs(IhxMb5FVTmz17zl$V3O)n`!`z?sed>y)~Tcd-4}Ey@yn&c7=N*DOZ{?{)r?
z$@_==mRpApJek#(q_Mm>uWg=bVa>vb=Qlr3{{hx2X12{V&8nHD1`mWam(3zpg~3XC
z#F6~z(4Q4a_YZWvaKQ{5$h=x*4DigD)~h&Jzw3gQAHljC0ecv+7c=iBp#SsqVA>7D
z-&iIbZWO%)XYE1r3!<_JqnM>%39FP@Z_E*+U8X2bSiem*F#jz5Fu=jQD#$td6_1;bRE6
zgXKDmv85g{d^ns5%;-V5m&W~)q9GYhTgWHqrMPNK=WWm?xCcd~GLk(toZE+M@VfvX
z*I2+k%J!!5O=-LWcLZ+4r}tIdVre&}v%I!EjQhaMpe>xXxD!G9U-!(=;}wG3Jh+wk
zZyt!opxv|ab%=eKA~M3V3Es{Z!L0~ggFlx@`(g>>tLH`)mcbphy(qwVx)#n;z*DI4
znyo>4S_XG4;29!e6r~h%GFP$qUX!9u6vK0)Ml&6UVwOXk!8DOun&c;j>S&6Igxj5&
zieX!h%1?Yq$5D6cur0^sC*Dt+$)JwotR-_5Xa&>&w))1p9CL*pz6luHI{h;!_g%j)
zI9r|Tw7Yk#vE_`!W8nDMg9ZEt%5DUl4ubFHb<9jSb3`C*a5r+=-)WHdKH}1PSd%cm
z0CBVZhdUU9)BeI~kld{*PL37cT(JVU8jtW@tEAmoKDa>v_i?kZrn|vXS}x70>tGJE
ztAd6ZMp)}jqUwwyqxio0LA^2)d2++MWNDhephuMJsk6JYvT;*=INIte^co
zzRzA;PQ#6`aGO1x(F<*?g4^t6ipveo@=@R4bDy~Vv$H#vL7nzT+bVMfU&^0a=CnV1
zHmaUlMmCbouQQ{h`}lJF{Mix0i0|~@eBZ79i-F^EDP!don||3VLEW{Z
zjpyM;DSX-v??1+;A`@GmZ&oBkpotqMXXQNXr@!V%f{L@8W&M
zV59S}9#k2zB!K&$JIkN>vNgU6?nr_i=yL1#0)M}F#pbC8`ik!>vwSaB@p3&df0rcJ
zBi;Ouy2A7WRYn=tJNxvtZYt2trXb%p40vgoHb<1Df$@nr6}Mq{7nPo
zEPwVCzE5AaCpZ;T`@{;oA~Z4ULw#b0NFilZuEsL=6#f0|w#gf0?Mpi)Z2nNC*rh*g
zJ40%~R+O4-5q7hI_FczNFZbKvdi<6NTKVcp{3Pdjwao%E`9jbw(#(gVf}dqeWG$oX
zo#ob}lj>yJjr*MCKkR||((s{GAIW4@`J=)Es8jsvP5_h-k3y}9#
zQF$)BL0Xeav`@@Zd_)lu2kVTLSsDv?2gxg;uY^$_fvwdubKvBYv;5J69WaMV!rxrz
zx0d}ZaUcIZ0Tbpu1-yUtTih3s3AhiCRzGD;+7J3#EGmn_zlJr%h$HwM5Pb~#&O?gE
zG05Cd2PcbUx-5T(erKbisje9;as=Ep(liF@+Iu{e%QO_^?LF$I{wu&|b$f~IOk-58
z7o4?vwqInF>ezY~j_JaaH=I}u7;O?M1L0+XxTf{hTd=C;maL@~+7Bmli$>!fKMv@X
z`+T=g%&exy>gBqqI?&(sS87v0O1R~kQ*>Lu6-Hi8I6aTG5897)4Y&T$3%E8cXP~Ft
zuOcc7{%V560qPLcm&Gby8x8WXXe8Tnw*@rr{dL!DxIe&N8GJ}L+)f04AEYY;?|zXf
z%J}@Qmj?a?m_E(=3zAQ-MdiZkpd_pCp2;SNDg1>?O{94ju_*xN%M#E=N>1g#Dgb8s
z3zFaM#Z~+^yC+u1@ecl5CLTF7G~mBzvIPE;$;AAseEb(qJb&Hf<<`F*vyD+M0bOuG
zODDmNJQl-n(8TSC(;^=<=||iyd{2+D$yx5~fwqhlXv-Lor+9men;R#=;%|Umjs90(
zDgOnO>$9-WgxjJt)#?u=e{{?Ot8j;*9w%-a)I4Igryu%Jf?z7pYu-_L!tW@!#YKPE
zvOLomTMTj8Cj1uj9e4@K7o_yrW--SwJfrFCbh44%pdL|>CvGqd-*sH3t>FlGfGctx
zoD$A7|39sL3tUrIw)Z|KISJ1S4OH#bHh`cq)+&gpFAPEwv8|(yXdi0DfXIvrDyYm?
zu3!ilkwGRfl&S4Stx~%Rd0U*g09>l0i|Y_$WFP*3U(UxU8L0cdS~0qPmA>veY>_C4fyh9J9tS9^Zzr68c!def0NFl
z_m~jlepI&KgQGfW?W;e7{yJxR&w~R`!ox#rT=fa(px|fg&K|Ko0sS?&Rw)eJ}39o*eiGfvza&ix$KJuB_m=sd1sK
zsPiMOPfWJ%M6OEM-qKl~()d@c%6#Gi+SeesUxrZ{~7qz2alnz
zq%)t>-_8r}?UEc{y$WZ;S~@jwRpLoZlI~B14XcB@H`BT~5PRu4)4r&TN^O-;t#!2g
zE1ay$e~weTq9Hb@QfspvJ%sPkUq_bE9x9b4YhJ{+!#7Yy_6=K}KzdX)BWj!+EXwtM
zj+eImVyJkgfTb}(xP8Tk>btc|YjuwarnJ-M
zP|FO&;|$le1*6&cFLznCq3wy_??%MPg6o2-Y!xiS-ZrxPTeIP1`;_{FdH%YI4YHOb
zhSNH(MZj+WtnF1m3ukLql>)4n;}>AhrHZ$j6TUYolV;)rd2}j*o&zKei=h9LhH#v01&QgU{spaRIJxgw@UGuS@Q9jtfQ^B`X
z%pqN%87Is-3I9uzObZjBXQSn3*Hz_wh|>F=EekhQWM_D`lxeNz7;b@iYbkL;hF>>T
zaK8rh;5~5BBE|XEj{F{%$}G=z^n`4*;8vS-x3K6lQ%JqPrt!V6z@Ppb#zgK_9ySMs
z8h;x1xOpwo^U}{uqwC<|DKN%TXtfQ6?+Y65G*ZPmTqDk-CDJagHQI2q9A|}5RdLn4
zpzHO|uNI~|cKBB@CcvW+AYn^s-tsBk6J?o^b!0E1=MbHhsUL!r9CN_BFRS1EX>u)e
z2%GKuOon&{JBM#~c=Q@yP;Af)qEIB(2bvkAbdX%HGcAr@xSaV_;KUf`m!o
zMN-^Up5!;)3n9S{BN>hfvWQw(YA9tvd=E;^JOsKHZHxAdFpq=2;z8$I{d8D`-0gf5
z<|AjN^tLV=7P@MjVXNQ|FFPoCz?s*)26-Ft`&i-@(tPzcxa-<}-|@f-xzr3uoe!GH
zwozzKXLH~CuA&^&D&
zv-c{m$USWuuORW+kpT-JZb5EWtVrt_R+Phiop@fLj3wZ_+i@9(xdK_#fw
zy*mo74eU(h>1lfh&2oE|u9mzWd0eBnGkvj5uq{wDsZS+LP!Ft$&b#7t)`qQ!qI$Wh
zA%qqDjdt>jg-g&^TvJiw5=hLXcan3bsxSYiN|7bE;(G=3l{waro18AuW>fI2yU>Ce
z;_hz448a)vo3Z!~Yx7dxTcVXD_iJpRnY!A}>4Lx5i@QF7ScRF)bDnM(Ai7D=mj6|i
z7j=Az)>B`aWzCH`?r9tCWmI0JlaO2`%u|p2%i&^KBY2y4G^~xkdfPky=9`4CN?5M;
zwh34{iEAMkjEZ&||L~pzP80g@V4kc|i4|l`U%0tKo9Vwbi?LUAOJ7~84&LDHfv}#!
ziEGo=XCOwsHYH8HG9`U&!Xwfi86O*?4o(Ar_M2f4(qEj8bn{
zZ&b%8B#0%0Cp@=#96)VIdnhU`B`tondUfJjG(~K;Sg&q<{DwsJ%GL23R*985=_cZ?
zUo6I{H?2Y`XXO%I7q3rFd#Id9VrdI&uAa7y3x?$!n9-98G2u!>3LP
zn>z71>I;413iU*dI&4B%xC8#I7k)8MJu4+8Elj;34G2#S-Z0K}{211!q^HgZP8b(G
zFHRke@soxZvA*ZVPZ+Q1@86Ay>rs>vHmr(wz)s(gxc)Va1u1@Rih5)G>f{9VyoE0K
zMj6wRH-c6Rr=pIiq(lkp32Rm+5x(@8=m<;wzn;byVyOF)#NM7ty$^^|Iz>x}NbfJ|
z4G)dsemumfA)>zbY3b|N_IF0~szl?j)C*EpuU-*v{MA5S
zXN)?Di0AAFslQ)LOh}Gbub>(n&>ZA+%pb8oC^^hIAI8j$d*Ow#j7^vr7CtFrvgWxd
zQM00Bbb7*fATEA|F(Gj!#r1*<^$MOZ<4;m*atg&Iu6)gywth8BM-S7L5qeH^Jj3uz
zOJ0+>9tq+T3Gs;=SlarvVjrabDxSeX2K4H+Y&pwfHPD~W;uwGNn#DVzxYKIcGNE?#
znSWn8?UQqhw(Rqop4A&@%_^;VqHplO2Oq!x#nnH|E}v%qeA$lX$x%^*lLx&$=_hOE&D;0nr<0ESb=33TeJkU(9h%v6bhzOE3sc!H{jp;uw`}o$tPFba#i;U^FFfZy
z^7G&bYTl3i<9;L&X|m@3CH?asN#_|;?)i~)+#B-T@FVGR#)icFNV*$iPiahPM-br
z;NRFEe@^)TpXzn~bA{y^cBZ>N#dLtcSQz-{nt{SUlJ0D8??7ph9!?OH&Li!9;g10R-e|{}@+m``<56++S(Up&fUs>|ytzRrYU9w2rJ6+&CGKji=
zh(1KWEc|@lz@Nm;#>7Tu|Usote#kF6H|@OwRBAymTKn<%BQc|@EZ1+
z*H*=^O;}AUy|e|e-~)e0!$=D^6H(=LYzdk)Rjn-aqubYd-GG0A?^RLw_k%I^$#RJZ)^rQgFC+@>^(n(8k
z94W>j`v!4?P>aWdgn_WM=1XOg64TUc6LDVIVW$T
zD!d_m!-jDSu_s`!SFaIwbtlbd)1j%q1riO#xL>3jjX1@*($;0KTN9tWwx4d|nF5%L
z8#C>7Vj&6E0`)44p2YR)mFscraSl#r+Pvpo;V)2wa#EYbb}mrQdp>LsEToGO&hoK~
zT+2t}Y`BWrL+40wSI053|F9_afrRUN?D1;HCNIUWb)IIVJ$~RA?4Y9<{c3Q+QgzD8
zl^Za~s441k7}|;7i*?eTNZ~lIOGlcAVGR^t6~8)7ZA?vf94=gO1zl6)*V6%4I)Y1W
z7mscrE9P}Nb*uBdlp2qdH}c1?8JHg~G!W@JZ=qTzenyBu)H;`O?M#ne5dFw_M>*Hj
zS^By2XuQqRM~P2Zb5afV&{}VIiHm`c)fls~9=yP+q-v2LM_j*x{Lq||j>;VOt>Z0C
zGp#*!ea5mEMHht>>b+soedHo%_c#Ov@Y02
z%d$19DIbM*`sz}AQkM{)rAcE;64a_Zr5nNUoM(8c?Wvvzk1U%@Wm|V5-%Wxs7Bcb)
zuu&vHPeZx0DE~&E4PoeN;(Jt?<({AUUm9Ql9q6t%j#X+ksGY(=Fvrig%4|%p`4>*ePr=
z9(?tTkX%YDfo(ab-M+v%i_GMWEXBts_^>5AMrUuDQELmBanb&Lz65DK1n8?4b!*Mr
zi@p|=q+!%3jw@Fkw3sO9@Z@y*bUh1;jTV&$tmRh3xM3{Giq4SaJ}4&#_by$b6YmE3
z$8GWtCR@1~2k%4b^zB{y!YE(5>(OPZ(7S=t*C?xRa3gM^?Ez%Q1CXZa_X7U
zk8G7pDbLsWy)nmJt!aBn5O2CUXOn~_Su*2djKk_6$qwxIUlL*tYZzabp=r|#5BBK7
z^qwtd=*nG}ZV5nY0Z)CBt*AZv~WU&^QJ1=qOLSWPgM
z6xh-HyO>R_Lo6NO;IkCAd<#aUlH*9$KGa8XIGv#~rlzxBu2a){m(L
zN5%Vyr4t@>*vrH@R{(eMYMiL+&9!CpTE$U*3FM^2(9b%xwJV<
zzXuX=qBi`r=!wSh<3n>`W!T31mHjXRb4C3gK)L9EqTTS1
zLD8l@3d+Q>5-yk4x1>N&ORm^$C4lC>=+KR
zuSKBErKe0f50u1OVNsD*2HP1$<%-5}y34lV>rPydv?WiUA8!$wY|!M&)`b!ZPQ&N7|9A*y7IgE9n=E*(ggO-q7njbYo
zH3FoLuv7@2V!{h7KsXS(2Wu51IzH?P@}WUo()xMemv?Qk!UxfHtDqIeu&A&*kW5$b
zRL3|*wQR|E)h;A$LNk2xHr&Zv*lsJcWsr8L+-W6S0l)3{UC2*^M=#kW^Xg(8K8$s8jsTKEo%!jKQmTL_uNm?8z1H!RDJ*+
zfKFg{1U=mcsLknUKGAq1c@~Yi@#aeNZvjK(E4z(
zFuQ}`U;0-^{hrRg-EXG&31d#=VJG0Jx22e7U$n#TF7@53&NY>8@k@1UFFx1cV0
z$N24&%^#Zy56Q~oVOV0V#7Miu=Hwo<>?izLS0<#2sO5t#xFPdWZNZ{kO95tO*B@@r
zHP6Z2kCf*B=d7br^kOO1L@P1LT7X|h5POID);m|l)J>I;xzK($yf%e>kWLabryq0D
zrV9BS+EmYz4C}Kl5{H6Jlt@GEfVnm<0#hA%mKfegwSlKGF2%V~z5IgMR@&^>%Xm+6PKZCdiTnQ>o2$B5QqlRiRb((U6@F$VaC
zD2>T*4l=h}+Hlxutu(BN$t(zuC}%XDC2h00WJ5Wp(&EHz&IQb-u0Nd7pzb-jqW;Np
z=*>2U6q^h=z;(_E!qjY_eN-j)8BX&g#5`ZaT_22_3b%0xyPAn>x-#Qhu!01h^Vh?N
zm<|*;&)30fQ4?Cv4YVHfWsylwD{u}!0psy(gvszBaIc(4xbHDQi?e`a{oz8n*0~nY
z{4?qOWjtofTVJo6iS@s!cOlIwr*4x;F9$t}L61Q56wQ}5SeQq6UxZ0NNeDAsyeiYz
z@n%DIOjT(kv^(zpU55PT7$g5X4_G+BIU&#-F~h7^Db6xlL4+ApPG%_P!}R;E!t)*P
zS=ynfD!sza7DhG%n#azJz3E!xI^_53um99EnPHMpX@HhEN}6M;im$NV9o7&1Se1OI
z_JEDxWykE!uUgzgH+zP({l4{%zx^>Kq=Q4q4ESi9xFDgRsf;ZNLQ
z^9!do#M&k|9JQNb>iFH;s?L=%vZh$JqiWJl_M%9A(zct^Om}rkW=v`K$DRdUI@p8*
zzK}5PRo-OQI|`o0BH+TOn;%zlqAIVHU!g40?^T{<{ON;m%zUvh@+8W!3DdK2Ga}HO
z9PWF=xk^*7NF@&97G~th%XW-{r=e@?YcdqeWriHNS-uA;Re7UjZGSJlpBZ=21v46l
z*QW)vOCu5Eqe9l`#0)n>B+ME|aaQ&09>3=YUP!Bd~#;doS`MGWT>qa&5BHlZfO+L?O=GupL$pc&qk+e{D}z
zlR4b#$@t#krp8H}slJYd=WW*-a|}Y&rb*oHHrl}p3J)rc-*xcTI5`($cArV7|JtO;
zVy?YyTajQXAwP_Sr)LE7Hi58IVVNAkONQn8F83bu}
z(o%a>UZO0-oVlYa?nC}Sc6_+0u@1fhx`!N8CfhUPr2Q)7^UxfBX!EVY{8F69%C-$_
z3r1WqTP3c8nzUgg^Cq2hH}o!6MR_@PCx4tKynV0Js_2bVjj$Yh>!mHd!^?3$u1o4~
z8i5(>=mbdqJm~b#*TD*m&yfzQQ5x}`*(Sp%InE7oTH}H+?t|RvOJR~+7V8IJ12~Bb
z!t%&E*h7Qf%h&Q%EaW7uc0q0dTqLYV?euaTTZ7j%sugS7CHr?KLjvlEd8m#w)Ui-L
z4!+);b=Yt9*8%uc57jYG;aUf^!`h?d4;-i3hbo6c9{DqKjmhwigMLIg
z+RY^x(#Z*HDLVygEK&~)ti&kaWzr=8qcQM7HM7%XNCOmtKr2EgE6*e-L|19Qm~(+@
z50mx_x5*7t>mrXSzJgA~Uj?1z+20xh4VC)ZD>8i!Jkl3)G96|xyk2q`0|LKy$RV~u
zv97jAMNu2{J*w#4`VX@6LzA|L~Wmw7db-?8u7sM6u
zW_y9o_~wT!Xh?AsjRbGz;EEFtEVBhHVfyhXMmU1nU{8z0^q$UTXd=|}O;
z*nq{kBeoTa61&lxcmV?1HThiF`E1==wmpR7xi9Ui$xq~DvH{_80u;aXw
zSxwrf`;WbH;r*P@oUnXp<&*SIa~l@@dD;0D&_(@a^JJXi{$zn?-SbV?u!?dfeKBX6
zBNuzAz+k=S!5d8;_-g6)6IXGfqrrH!6u9~^>!uK9ZWFef3|C}JuNw0`Jl5-vDY09f
zHW_fcLrEoUpI{!ion=P}mOrGgO4_QZsq8l9ZXK`!
zjopjbTQ*pTdGiY5t|0C<=bT|jY|v&A^U8Vbiah0g#_nqXjdxzTCo_yf>?GcqTd=h~
z>3N%Uiw?nCgvD;$>LFimurA)t>amtvhi=EM-^kP9ImuDRnTa}})>1zzR;
zL2Cj=UY=tP%>4>0#9xjE{yy-{z%qY(RYwdLc@my*!5LD?nNO`fb7b4Uc;C;6n_`!G
z;zSK}QY@7?rO-)@dLXxfw18i^Ks|AI`^Wj1FGtbl?$KOo>oysP+E-ZBj%iV}mxlM;=Fgj7F_#sF+e*3oT^+Ml=3+L!j~gPqwKWGG
zzec0Y)>3%g#U8ox#MR=fWmkXi9+3Tl2=NQ|>uqfr-*LJEdsR{ycG8=)ODeDeJ%O6A
zXJ3(A}rX2D4D^yc`E`jBA6P=0kN?r-8=MBr_&r5e*{xmTDD7U1qnw>z^ig9OmCokvde
zIR4(w97^ZAyM@0LnhFUQ@H4#xPz`DPT~R-@U?$ZJuAbXRxP6&*pYA<=bo^VoiFv6~
zOK;yE7x|dTwJVxyg5?{Ws0h}G;{@kh@kVUDouJ%*m2jk+tF#K=0mWtTcpGpWHYZR<
z(932Aqdy{`{ilOPhBgmENl^}J_0T15-kn@!beQ~l%SH$
z4$7aMsMS37ZQoc^)wiE=;YmX|&&7#a*qIOVGzd{bgGRyB^9u{=@zl;QENQeUS=Lfm
zfQId>ed3sCpPQV)erqanS>@Mw;|v
z*fH_>9Q#^v_BZ+GE3`$*v-a9rQzLu|Hwx@2fkvLJF&JLQ65HHN+vej_pxg{Ee(Jks%+R>BtvXXw5Y^@{}Nt*^y_TBTuy>Po9_uoR~mQ@M1v=
zKp(MKv@p}^e7pPR2!yHLZHonq6tXlK{T1-QSm6N;-Tm~JyBbt3zP&?#DYtu*u|!~)
z1$dY3YsBB|c4*CsZ+ZAj-0{m(C@0s1`^sM1qM>PLq0zY;@(1Ds&}oS5kinu0&Ox;^
zxf_)Gi|DeGm>IcOXlB4tNx-|fzu!gN0mmH_$4o?O4b7#1a)jndqkPHn%YYnm%m&C3
zr@@*dFMn(1y30o?=|m=Cy%jeL$vYx)bCg@o&K|>j7H0ra#o9skfQTwDdvqc!)9MNgKsMK#q+V9=!q=yDs`9Evz^pC*!|ec@KKwnhs8vE23S}-i9hxX
z!dZ^BZpmjvts}Q34wPdB&AM1vZL{d%{9Ylc4PrO-OWF>!sPP?i|V5br=eOfC0tQ0w|2YBjzT6Lhe{ZP@If|LAZd
zikT{u?(=_uW>KB}H1l=R?Cc|G7W;!Vi+v=`X1LId=;x#vEcUsHRO@<}YVQ%%R1(#y
zU8rUzstuK>R?<(k>VB$K_fsvopK276sJ6})pxY23Ody|Q^q2FsHL^>x{ds++{qVl?
z^X%x!b^qGX|2{jc=BZ=-Z*#*w)t_*_O+LBtG_U`yo~#GAU23^+EI!QIR@dJPgrC?I
zx?8%oC+hFD6}Q}5p}!^O;S7~|oBS(kXk09e@`)Os2OfTOcC_)o53}&E4)fgXs%`bM
zTPAoFBS|jHin+t0#p*fdll8mfrrbF_z+APYe9*^BB`dB9!GyTKe
zgkyZ2O+N(Qa^Vdy$asIh{4#8rDSjCq*TRoAgx2jbROQ)t;%<}2L3%#kAA0L}m_CfC
zAzD{d0UrFM<0Oq0qpNsUi(QJR72K-GiX@1kb%BO(rH!8|!fS<1Qwa-N)dTAef~P-k
zNbqHMaJwl1`fjy6t(&ucaH`%B%4vvTtMbXmvAoTvb>V
zxS#LVisvO6yx#e>Dw+)iPaFLDkB3M!UCD8pRWDdcSz{F|m55
zpX-)bgq$$VGAR4?ztjYiGBAvdJ3PUVq>4AH
zrPW)y(;wvvc@AV|+O?uQAT?V@Pjwpo-H9~FY5ht1LZPfBHmq2n)4Y!iiEnn=C
z)WJT2b(EK9bc<&h(XON#`}GpipQhZV3IoE%RwaWRMYO}2S%8!tN@?_oN+M}#*-F?%
z%T;6^niU>`QRzU9vmO`mOs?yz@u0e;MvQrd%3w
zfWGHt6;Ye5d9|A)52SP}nm9c9bsaH~vsm({D5krIhi-p=d%^R#NwC>??>jm8J2=gZ
zVtdF}7UJ@4%IP@iFypSPuwoOnSx^f3L3=K5_Du?UhuiF{G_LG{7wwCTzT^k^`j!3n
zpY{j#E}QARu|ua6k`5mTEen-3Mja>ls0ue(ap&Z5PUqVu
z=ne%&w3BRyWNdUJtprxYVjf>Q#%hi_4nDQIBoJSJe%<`^n3rCf-u$}OQ=^Q6g~Ptr
ziI>c7ga2|xeuQk~DsRgp#tQlYiPL#wye)!IA2E
z_MBhL60M*Q&kN!5ZJS194mIm2en>qyU9c7QbMdw?jdl*TO5;L02QHmPvhUieFJ3N&
zy&KQNhNbz{O89ZZ9hOSh_NmgkhtO?hjQKdyZV@HsK5Q=C43Kl&%#~$*vVUW?>+)la
zYg8||px~e5JvmQq8utnN755GQ4bPLF4W}SgJ?`H*Ap!wt2R_%gudfC=koftG<35mo
zAQzZ=?lbJC!sPxJnAftNVWa*TJpI3q=T7dLtQq{5YgvAS@$_`IJ&b*??O3AG+=tq(
z?%O2ewfJ?V4wc&OfH|X|p5}iZ<^Vn22IKh;!0e|dG?<_38^F^QCYm(R@2h?)p5^^*
zAAl*+bD-^=KNaSq@RSX1`#*r^|JHWuBVX6H_mBA>?spL;O#u8JO;5kUmK`-B)j;%Ag+
zs2ENa!@~x`sV-sda4|k71o@Xs@WryrC74p!1?F-Wn9E(@WVz(Y8i=2-rBf4Q!+`Ur
z4*dO|p|AvB3QJ}GD8@_hrLY7?3_EaJO>i8zNnxq16qd?LVX3SbPL$fUir^2DcuxmS
zo*PAB3H}At>*?q_DSn_Wo>~cx81JBin18v1KgF+dz?_8fu*yN_FT}6}UkXe4rLY8F
z3QO=Qyew>h4$Hy@=&)>(1c&-!*>Wiljg4gve59~T9!I;x{El`>;eq~L=4cnis~tGg
zcvd^gN?{3SDJ+$h!V=D6*;xbeyB%<7T@Y9XRg*-OP@$B!#8AE{X9H
zOerkYMd7y`W$OUvEk{`?ER_|*sS@3!utXCnJdo#<0}hSPZyaz4=Z_s>>fb?o@&CcP
zq@Ig4*>(N=$uRr+_YT*!ZV;Yt{m9;dWth$(53ip!j4AMA&b3ZGSD^2$fjw^ikHCE7
z{{H>-Q$6>gGsCAp73QP%IKX7w|Hr;LK+l1;KeTWDWIX?=wsSZu%EhzdKTglb2le|u
zfalF}e=3H1A+cL8bi^LG3&z8L*9_{HHz-we`yX5uV_oY<@6
zU?<*|2fj5lL`jQA_D&R_HXkV;PR}o@@;Z2xQv39KCJNb}_@E76l#?{2
zZ;)Q~sz3eC7~d*~RRBfRx!aIsWhtw2Zu72MEWre2xdf$r$a|(W_OTRG*J~5uzpS&_
z8q&yHP}-k<*Ou0L-*#u;b-cwKE^SNbxibK{OIRxM;U3xIjj-XjGvM+=E%ru>FJ0xu
z7JHz@USf-fv_jjLEM5|S2XeLVG=F2vfGRup4mTsY=^wCqM
zIJ;)_Z6?CiCfa=4HNkTq1E-}%u#2)VHsdIVFFnLNeCGt%ogwc}==S|hSWTcFh8*zk
z!*5W3!k*i;4rVhDU&nCNv%UlR>LSNCaRn@p2<4~j+;z!oPQI;T%#p@5s0s3%q3v>K
zY~HBsZ-`?8Nk*_|gunbfoAGVQPY8G@!DL||yF=6RxN2QBr_1<6V{RP^xZ0GinI~+E
z!9&VZiq;{9w-aw=*Q@6I1INpxI($(_hscTXC4W6-9Rp>zG#HC37^gc@qI1jyW)YQ)1xl~j
z8C3p@=*y;}ci%G@S@&ay3~f($e=B{HmmGDrw*5ONw=7ole6sCT%0YCD;<~FT*S1&b
ztv*8HN-5p*ZF$or4@lW|*gDY+#4DFVyntG_MN2TM$3=0LYE2rO;0B1*<3`R{q9yII
zCfi6|dxV7Fb(=e6?-&7&9uzE1;boB1W7h5Lxb2K33}UCvusLz{xB2RpMo7KW_;|XA
z`7Ti&DjTIlpBsF#KLa0c%ertu9v)}rmsSTPqSu=RJ2_r%E
zMzntoNn7FysW09*F7ZKt#e~bamt!ks>a+0GjvO^4tGx+clmISZx`xvwYMgu!(smpV
zD=ncpOUIiHl{(NKYlhLcTO3VPOL4RYavzlezA9kFzBn4%Z8a?gI}l1Q99|RN(IBp1
zR6ETCsrH+W+R0~;qTvuA8#xhs*3BFJ1?H}MdD;NyQ}T5+QrB%8i&YPKeb7cw7`11@
zJDN_lsmBgKXwi87g*@&!(lS~e%1e@>UeWIKF#)!Kfst!oYN_J1*#O;RwehKLFUY$x
zmuTOJ>fH$5^^o4*m<&pA0$X4o0$w5RH1?ScLrFsR=@Ps_PGA^~w+NK~c9ip05?DkzTk*esM<*tRp)t
z<`>M8zqljovkT8-EU3wE(uL1dkYAZb>)kVlS`~WtqWpj}Z5HJN8k@5HjgN!pyHU{<
z{>u~aSZGk~nnmRx?LKBjDVsvh;JFOmTG9&(j<<)n2>
zJLD{QD+$DnAV`uiYez(zS8_VCID>bTH!H@-Do~Ss(|@!d{U6l
z55i$32XBUv95qGO5D|T5n}pvqR{kcP`7jXaW1CbW){nJb~wv@
zDVF=vCd8bj+3D3yws#(b-h!_nu3JIx*!;vqHgHK3A*vHI^Fk2$gp&~YTHg2xxo)bi~1Fn(R(Cibicde*xe;oy4C
zVA6A}B&jN|n-5>y%9FG&D#_T};kFmFQYpJ88dGd;f+2{zj5oEcs->NeJP~<1^7F{^
zk$;Z-s>~3?A3|>$W!=zag@-%z<(56uS$;{Lqc>lBC)+@pUXf?$$fE5N5s(fut>
zWS-s7*~4k!4s^U2wCUkh3o>?R*zYaq%Q@nQ9k3&HNReoRu&uk}j$qi!E;BREj;WEj
z%?RzABgoM;hr;lxi!l5iA?#}?L!Jr0q_Dr?8H(RX;o*iEHd+rhS=!QVw*m};jqdD^
z!M73r15b{V(vd~{mo|-Gaq#y%dmT@9O~!KYjEj=79rUi2v0^+|Bn_mCg(k1%*z9W@
z>x$*sD=YY{k9UagzObv%&lmka`eytq?mn^Qf*J-VMpNBa=$$e3bjeNwyG`%qOg&Ee
zRAl$*eK%7-!-=1cOb$QD>>yK*=cRWqdf&&?;P$~?C}V!~zLQOe;H38v^sZ%8-v~;7
qDXsr~B)zK#(x0aHF$3>vdUwa~Dg5Z06{cO7$eVsvz5>DifByqAF1{B4

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_release_v8.0.7.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/boot2_bl808_release_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..71ad7a7b303b789facebc9550f3c031cc141732b
GIT binary patch
literal 56224
zcmeFadt4J&+Bkk@l9@@k2sj|nrHYAyveu%p(u=hdOfrC%qE*2zZqd=&?QXYqt=0CG
z77PKAOV9z4sx8(XO#R>FdywY=2Oe&i?*HJQIbSAbY;qR`+
z>Wd}eq*rHp__f^@mNGo-M6Enaaie4?`sPIK;*~q=kJ#sYm({rY;JmX7zj?mnk8Mj&
zy?FBF*2MmOxnN3l3+)%Xu3{IZ+~K=EtB=(*#v+aF4Q?mnpE{T;jnu7Vu41
zKpqR9VQ}
z`aRV5M4M%vr36W>kH|TEbqM3$$$-0wUzHcW1?MQn?BclW!a
zZEjj0d$ZQeM<9Iw`&bb2aG(!`&7&Kk{U@RQKEzjYUg~ksmofU~X+c$-o>-qw7%$ec
z1hJc?IWogIE<`&qAXz&hBUu}@DOo#i^dfD`bApJ+(p{(C5yBZS0+Jv5~L?-
z$CW2(Blafck7wz0D#N(JpFF6A4M$`Pc?^EZ^~cJ`lg;E2XKHJRGxgl_tVMqao_{at
zaTI8DG(4ftG%=@1&57k8V;^UD*=PzsanA5_qqSw_n;{33uC%zRe-ii~B5OcuU%*$`
zHdre2DbT0jAset4_DY<|FaoBhp}j#dZ=hrw=$V9t&YCV-jL%55ApbxN^EFv;-dNCA
z){{@PPzIK=7@&NBGxfFcQd!DkbcVN%*H)G{JHyle;!F*ntIdMv)Wq=trl|S}Xq-x>
zu51_1KS9M(4Y-ZIF*Lcv*-=z~wpf57jX@PXf$
zb?^(HaiPvs^oI|Ka+JeYT7=+UBvV51-P2hmH&$ebg}K3&aF+6lQ|xAHfL=PlBwCKd
zk5icqlMs25JVmyV9a=Aflxa)<@R5rFCXlw9*7R~;$RD5Jc|TXGFit`WLk1!Ga$_fi
z<_7H>EeuooOi@LLESOrEIs2N0*Y4?VrVPNBhwjC6ZhHvg7@YEOw%@w?-KCrdj@)VwqyQ)6DBh
ziWjq)0nz31bELZZ;{3sT{hpX1-j}fpU45q5SwPl}hCdPhDmM9l)|^
zNWARkb$I4H(?PHlxm}$3q%qd$)|kSm#(Bous=uHBD!??|-SY4Zk+M^lRiJ4TWUd2#QAnwK)dEyASZ!#9LErB4aNog$9h_W<=P7p
zpyE$Vb*QM0(R&Ctj;@!$=lS)tMP)j?)soM~*r+7+Bc8qpy^3u(e6^=9O3h>`<)W{C
zFWI0!_Rs0b=W8=~A+Qe-#`WpBrrvb#rrva+^AdPu$LjVw6hPA!tWOtuc9A-!0aX=e
z@T{qCa3ENCxDTzDa(gHB;@sPs?yOJG;4jwZHuk3HE_9)8jG4u`a-p}hFsEw?KG$?H
zJ-6v%dUbXmms`Pvl{zSs!t+-aD)CUNqDrL;u;6aAXNnzhn5d!U}
zWY=CE6o(;FTssa47L|{%fL7{gJI5+o$&9#3dJhqt$W;Ogu-}Bq>)04P9RHM
z_3oQ!dY1Q=4vt+LLIhZaU==A)3M4#t4y6TGX6c4qM4}%eb*k?;;aQ~kB1?FVK^dmB
z;HkwyRzU?hU*CtcXgTDjD1q`*LK#H^VxjK+WyFlRwcg<6T{gv0Ox7xl1*AavoLnxWLt3u?YJwjg%@@^QHu1(*KEOa;2XM?&K!ouk2UZ~H02e*RYaS7ZTy}2^tl=n6Lj6_L2)Ntk-8G>y5~?P%$Ux
z`6u?UOd=_mJC(xg#lVYRu-YIrIg_OW(R7QMr_se5LY6lY{#HCiizrl;sF}ZcKDp?6
z{L+NjnN>42vvkw~{mBF)L^(tp%e0ar6-|mNq?lADyvGylOK}imnE4TiRgOT8lFmEq
zODbZ(CKRuLv<>JqJlPPy$Sbu%aWKF_P+ctxK5LgzxOh=X@MBFM#Z4;94GtbnDKXs4
zE0Jhn1{`Z@?wE~A#M0-;fh6I*2Bnz~M7xZba&ZGQAan+KXYjk?#?N`IOr*-lv?NEV
z?Y4K5DVbG9AjfmeZ5?xt!_>S|n_Jv8nxe&QYQSuy5o@Lf9Ilt{2w#J?@RKvmak!Rr
zTI~JYPuSW(Q%Z#iXrQ`ifvyP`t~JomW?JyA@ezJ%P>K}r)3+u}q|zw?)r=J0CkD8
zQF#dqyHNF>Cgi;(cm}%`tT#mEQ<+_@x`B(X*SPEtR=wsRlM}qy1$hZax6SleOS(A%}8Rrni>#{pJiea+=$LeCV
zJ=UXFUuHd7Tuq(kgoMw)#|iV#!FbFySXok)rT>S}vjy!;Od)779U4pphYHG(R=Z+cYb=&a~U2o?4lG
zA?w;+*-9EDDR%D%?NQbl>kgy^*6lAhp5KSH#8J|G)w~BrEpLoN-n&)PN-ya8#u1-p
zt*-sRs=QOT7b3@hYNNViwd2mmDk?G#L-fc&bjWEndtSDDKCt|e|h#3H%K^=|C
z5@~%bNS9No*vyQ>QyYmVLg0sRMxH;32h6=O2=gb`{ntWVc|
zT;2?$kF3wH5j;dtlSND2VU|MvUu2h?*bW#uR4}O9IxwP|zlkp1%5A@Bpcu#S3g|m<
zzXH8WcHLp2xEHa;zCpQ1V%PThjb2~fNE5lHc7ug^tf0XbrjG%KBy@F>JDIS$u=x4L
zWIekf7-`2*L~c`Gx`z3pB&9AyZ*HfMxX^}l8~VukdZCY2Q!7}8Nq^WHls%mOqC^``
z5dpNeuorr^9Dd!2(Q_=&tJ;PkLfoKA57cKdIy1
zT|-xGnO~a5FLan{rlt-k{~er)<>?OYwxr2nF1
z-3b^;GK{`Di`KIpNvJxT(TCK{ufufMaJ$}dp|E%j6H=FKyxS_?mA;ey(p{UmeJq-<
zXOlihI>to`-IvIay8Bzk(k6fHCfu%%_^~#f>N2OxzQiThvF%By)Qa1UQxEeHV~4Lh
z0sW7EDCFwks_8avex0~53E@0JR!qBv$+0CHE3<{SFDXN2gBAV9CFKTw>&zm(+N%5f
z67nvgXOtEc)rla%$}PgO-KceD)s{j&Zw5<^KpUF88&0QNXz$Yv02jnYsXu(>##a6m
zPZ@>YOQ@p>k8swfhs+IIKm=%7=wlH_5}M~U&Z}Q|Fe+1c(}mW}-P9BvFH%N&3AN)H
z%Q7~n{u7%TrL$fJT2m@+RHloE`v-jzL*|EZLf=Ic5;s3i=(|K>ErB`)I-@~P>?z!Q
z16z`f!s6JhVC3J7H3jsLM^bJBO9i9(oC@-Frn4nk23}w#IOr&s9M!a#&N=1LBG>w-{OL@v0eod+IRbCF{^j5CcE@}%KU-g
z#6;CBf)73D&G)7&w3+m}`Q>rd8(!kBS#?RlM0Lpuzz@AxDx0nR*}EiobSbYX5zaH-
zvOcoIy8PI!!3f&d)vmzwg~cTr=5wN?^?^h#-v|0p0~9K>N|bA2%FW{ph+SBXbaWee
zFk2XCCjITYtZ%rWtg0=!3z^Z5H}BkHvx87bYi`m$7>6e(3aeZwr4@QR+LsqzcKK+L
zl3u+}r#QsvvYNR>JKMGpv|<_BRDjEiObA+Cs~D%Gs84A`s0&I5~%5ChBZOYw>
z&JXTwMHVA;-P;QB*qy=Lg`Ha6+780eHF(Rn_P1&6)LNJ~HuTqy<%Jhrs5e-Pdgv4X
zxDtG^R>uVEbySdEJe`E{ts(X}JC>ScgKvWk#(@pmlMSLJ82L2Am?2$5O)rkK`*69z
zN`<1GAH|;D2hzVNOMh&2){nBiOVaNg8OrbAg;fmk5szz}HcO;3U(s0BwXBPq)-o+_
zUGpQ;*Chr)4i_rs-(y${|40lR=dtjjs!I{Vf$!N+frNKfAWTJwEN#$8pJs3V63BXL
zNitC4%`3|jIk64szB*QWW_iv%qz95D;Pay65E22nh{>^Q?Zu5
zL0xbK_^y8L@n%+GSo}pvMjRD~eJAy72&XGxz>l>P|1<4}J{Y2%Rtafs=w9j%X)P+p
zPkV0dwV5APQpNc}1(>QJtB*a=?wxcjla6gGZtXh|lwX~7no~fl=1ZIo
zva0OfkghAagWf7(=@9gI^NHGOOOULc$w}bngY`a=es+$O`o2Nz<#tj&_E`oI`XueR
zK*AeFRvPL_&`|R@B~qMj3TNA)KcXtgWKMX~rmWsj$%!4woR8g9tld%(F6p_WSEb^>
zlZ~ClvET=!{-p1sD#U)*m%ZCJCY0YLY4RtMCR_M*t;_#Wo%K2AYZVtPK)(5b_GG(+
z5%@1$tDyrqunrB_E+w9>K|0Gtauz4t*+t8msj@?#xVcj^Ee@!r)-_Xm!rU!k!P2n5
z?S&qEI_UQfTWG#6`y!WY$NiSd4n3DdP5C|49IfhpT0eGRvR=TN;7!G@ee!
zR+3+vQ;?I-E=WRZYoL9W9oH@K@XjU7L-0e;FUVTb1eQg8Q9R48f)+GsholJ}o4Q|~
z+V?s&+6jTwyBo&V%JP(DsRFCPY3pWbCoWS?H+R>*xpH31!!OS{w(!XF&G|1=e-_mV
zKWk1!oWvujgx00?FG4T(X{P9HWWHQlPT2nuyJ%;aa@kk
zcLp_Q{2l?dPZfT?Bm*K*ZUT`*VM
z9-BNrFi}Uhb3#uO(q*?p^lBg!yO^ItPE9j}o)@+;(@$|MQ%0(-IaZxirYTmZKEvg4
zI$I>+UD_F&kX2JWr`Xx`cZ<#k%8vE2q&_XPm+Vz5(8mYr|Mle77#7!<0mh2xn&5&=MRxk85O!Y0$hBy6utQcl%&%NK@
z`=P)zsRZGYmm?(j##T;*zWS6Mdta78!-Qq7hX5}PBL;FxvhY%01jPQq?J%BxyaQ%*
z>2lNB`NGA%h-s%bnZ76yuJw(u@YN-qXdrmqDcqkyS*11#J`>&&Q2a>|<#e7(ODX-NiVRYJ~oMs5%AqE*9VmQSKBbo4P!PDw@U^`I$>43wh;<6)%
zxiZaAWN6`pjm$V<@bpNkaE3|-7&lLBLljjRXozMd-$vm!u
zYc_0;OUU}7SjvAjEHR~Jd)$$d?agPoBPD0;2W-_^Nzo|ZfgCPQ787_+g2_5FC~uh)^QMN+n3*$wid>S7@9B1ZzZJRNU&AX
zE-gBx+{sL&hE1j4hMk9X*+zYV4s{Ji$mpQ?qx
zGcdv&Z_DGb_etcM?b!cl=(J$mzl7A+RiEI6s}=NFP8SfQ)ZT-1nJ82h$P`>j)f%_#-+5Z<0fy{?#U#km+I7|daY&*C4{QI
zrWqVtnak@E9mUM$6wa}kx$Mzn;Hz@MmyZO+H6Pe}7UH-jZsL|!yEdHpdAp&5J7Lmg
zb%JMZB#XF^=1+p>*H3|HXCWahs{tR;j#8Sj{redmC+8q*K<+Nw%|bj=bz^
zxTND@*JqM1s$jsMINor5mUe(Lo~b4RB92sMKD->}La*cTz{EyaSNdI4rf*%9Q9G=d
zwD7ae2%CDyi58eg4^_3OF9Mw?`gerkI;XMVmMVwqEu-o_Nd&lT)Fh@i{E4&+u5@F
z$dTq_jVJ5d4t`_*<99E2{I$)@pC+R6KF!e2{V&}U!mBf%3-aBQi#qo|k#?a4y|>6&1!fOSR~
zV+y6rWRZbbZYOwvaaR%aLFhIz)p`&@QEU>@1~}lXfAYsA8lr+%^)ZrGQ!rw+gpMF~&!cVOSFk?J%_vYl5@w
zz$fU>Z!0Y(;h{DJt6V0W>VYaE^PqeSl=q?61XtMS8MPB2|HRwM^H}<4ARV~TqSS_e
z4C#?|+KAiAO}ustxc@)I6v_b+F(n%l^+rth|Pf)D7Y5AbTz0b%``rv=9^
zN?~gg$!?s5ED36ZsPs{#EgD#4-km3{L(j`vYWa40RK7qj7=OvK)bhy_XUZI#ZQlUr
z7~mWOoFX>u9vcV!z!{wW=A=g&@Vb^7*0rcVved_3&U4oD`YWt*mKR|vHG;o9H|j99
zIUg_mRAKvvw8pY)x;X+cMffmcdjwj;M0_XsU!;Zi7^Rud^V<89g5U0C2DwwS1CPJac?8O+b^W3Z72oF<}2~!SO-(TQ;ur8{FrSiO<
zn0kR1vMR`jXPf!6giy##5q{?zEom{>#KW@%g$s?It=;(-Lc8amu!9Fm>27EDfEM)i&0)MbsuHvJoS&z%6-#d
zt?i-S9*`}_xCJD4n=~_FUfS@hr0@;ng>icFX5hSmz1KZ?!Ftr7SEM;IPputum9!Xj
zOdsdCaj^?WwmJrEeZpCl!pL~Bj6dlZd9jPljs)0M)rBqQM%v3!T+`+7xpXz3!89%{
zF+)y}dV;g-88Ir~;ZI#vM7F3gcHwd-%sdl3a0BAD+e(OXFh?d_1?5Unns*F<#$(Z`_A5g~lA0!*W_@IWb
z_JUT>LQaxGSf5P`#f;L^Vz6_FudmXOi*~$!=^W6fbo|bBPOD5|e9J&nRbVG7uxaoJ
zz)NKw*dEwy_*E594QY9x%`MRXK^)VHBkkL0{67FUq_o^Eb>0|Zk^De}59X>0IIIHw
z+6MU;$Ol^SvC2)YM8{m48QKNjN74>w*Z1N_)n;fRj{mefTfqPJr8`QQHZyoxvauSX
zqN(*7QXC*h_2bgycCx|pr^Dw?6#U8mM%??%F!CZyO!cx^p2wOF3-#jy>$
zmZsS?eMIim-4k+)ZAw9{Qi`zqN>Ja#ze>UTrV`c5gwO4Z^Pe@@GuvqOsgF)!4}s7
zF8|rz0xohv?W8!}O-iwYhjoIhjG7G|hs=9SK?kJKBi^l3eG_JBgD;`#&R~MzpPo}b
zM+}KXI(8(Xd*=qK4jDlRBS#V9TJZE6VVz6WNQiMa2CH2+QT2)&h+-U}?E{L6tRN!p
z=^6St)gcN(H+UIUkE99Vq3-L|CjWA4D?lA3bfef
z>sPPw4c;ERk?Oa8o1b?OM`IBOKh4zCL#*Y)=`+Ay>Bf>)ylQmrb&%{$ZF&zK##M2f
z4KRZG18QN3IuJ!VbN@`n0?Bc
zAj`ok1CHw--8xbG$-W}}Ss0D5?QKK>_~+abX8rVfv1BU3PgqKLH^6k5)tc8L_Vp=X
zyrnSc-MbmDwhtGXbOr0BhFQRNZl1I|Z}iinO%o98o|E)~d$!yp!->bX$Fc3%c>V=e
ztbagkJ42i|Yl$Dw2e4=Gtei$d8hJNO0cnaJw0)LTP6=tsyJ-}pQBY1!qalsHo5nyI
z1LYE>awwOA+;Qa&I
zI$uijfi$1HX}*x=`vWRH3BWW8kt_^z&8lZ*2;#FdrOfe{);1eIVFX;u;oKZ*F`YR+eCvIKR
z_EIDokkb9_tF6iQlvyIJRK?Ke&t2P=(vo6G8xg~dLjBuP>ccpgtshmziJd$Ov!9Jk
zD=;^G2;<&j~@GgWF@fw~3uiX#2r|q?FbWE`?)P1fvkU*cpsc
z+&%;Rhk{+fC^Bk++5w<;03ZZFh^K2)^hGl|X7s=N=C-0k9f#JZ+iWPjXhsI_ZL66;
zH09c|##xvcfF=JSCPIn#{ULEd6B2tV#aC7>(TBwL5hy1&x5ngu+A1zwfkrTUH?nIO
zdI8Y)0i*-QNaa$H4hpLi8IIasw?6$7K57HZH7H>|_PmYG=Y?Nv%2kp6Pl~R`khmoV
z>5|$JyP8o6EcMWm+|WY;K|f@U+;?RiikLrHbS?y2?-CY0;%W^-Vd*=_BxE;0KR(GMWC51H
z)S&S=x7Q=m_gIs#zQJpK`V;ug=V|HtF%0urpT5eUd1_SzdJ^Ub{qXE8%ew|wTB}Ri
z(PAs4J&AJ!Kh)M5DMp^X23Qzlp{lO&Z{A(dGpmC1%O;r~sUNU2PT
zRHi~IW0T4>L7C{^D09ZTsxU?>(=L_il*+iEj2gI)_rm$Y2ggte&Ga!%%bdojoKG|T
zP?sNJ*c&f|6~X);ej8dM|L!W?^{oX0Cmx7|A!}MSQ;jlYG4;Jx#80e&2FJ4)vk40s=`;WHD%!xUo)PE?W
zVcg?i>U8%9r*%v*R~-YpS}bGrLQyYr3|_fCL=SFTiheY2c~M)&L~F}BVf@BKFRgrO?LA={W~8zv79wITrd@X^ggP{9~ofaomBJIBqG-*~x2=)RJ=B{rKg0
zHBPT-Noby)8Jly4H*LVwH|D5g&T^BL^VGU!V_0_%OJIl>ePgZ)cHgnyNHFL9{R_szoV@yjj+?3|v)(=rP
zr!hA3%N)}NkqIZUZkTfN0h0#sz$yr)&IePcf9!thKKeK679KPw=t;~og@GU|GvoAF
zTEM#;yq{~~2COlrjT&XZV`51>(ZT7K8HmMsV(?*92a`X5-H;A7va%u;a?2NUd7;PW#0(Y!D0ucsRy
zc}&F}$&%kK#z{}BB#j~CcV}%j$j}_4o(R~7=ixDyg-2>OVodVR*FQE+hFJZ{jbG-B
zhWU62qcl&yv_3YcF*7!$Tc_f_yNf;TDHZpP`>ot)gts>L+b-j5$a&KJ_K|Teq#bj=
zePUb$X&xH)8h1h3Zg<*O#!nzkGrua)vrAT9ZM%@AnI%(y!f0GlS{-mrI$vRdGYjy6
zC}$na4B|QW^sn~8jO{2mv2fq{3wjx(zYOUwHrTMQqmNCxV#`L!5a(>1Zntd!Jn+Gg
z82H$-;1@nNH-6YZm&dA9MUZ=>B;OEW
zCl6-C`NnPHeffPRUzqu%k2$;E{|HjuDLWu#KcwUvon52$48d`U0{|}u`1`wu;5dIB
zz;kf^T|@Bw?i%*t{C^*U*SYZ=!1+HNf@3^6fM*lVUp53k0PuW(OZnfwAHE6Tn9lci
z48iw7{sw^KdPi*^g6Fv5aI&TA{db4pxLr6uhTltnKEMwHd>77NGL#?FkKu=L{w+iB
z!)~~Q{~r2reoVi_PjM(e<`3qx)ZR@)a7-s|7lw~29D-x~m_L{g?-$$;zl*gu-VN*C!z+(8Ctd!m{4JYust1?r?>Cz4mav9umYhQKGhs2dU4<4*_&-TjYFrHHU-V=2Ur;1%&-!YUQ`-=S@
zdM*s%zn4xA{kXkYx*k6GeJ|(7?Y%Gmw=&$5-_tI?voajp;JtXP-`t=7E`Qwg{5bpah4EmxCzNT`l@gN`Bwxt$*E(9-Eq%DBG@+|C?XU#x?Vm!f`
z$JY&4L}d&&N9l(veoqWH|Gq9@68I$*H<~{t;m_cmUCxesaryn1!)N&~iUuXD`;Ic-
zPs_7yIA?~NkFV~H+UOXuy#Ib|ey8ru^XT6lK}HwGax7~!#4eax=Lr=@Nxlr*uJbF;
z+kSZSgSY&6m`(N1hzpSHU$%zl56%IV|f{X6ASZh7yLxDg5(Z;@mM
z?Z+JUgD4BQ0eXOWhN*=&kSFGbM6FxnaNbuTV)E!E&iyJxN|+Ov<2e7Tpdpxh9!^`!
z-S2K*TR{(Tx`*4=_d!Z$0Eb)Ov1S9FbA!;=;h0sH1pT&KzEIl`PyW8u^M-kH9AYhO
zAJ~`6)^yiCpnaYc%&nZemg5I)E#+~Vr%(5kdG%wkZxhfNf?Ms}4*MIyzZHe(n11x-
zmZI2@8IJ9jYBn*BlBPR^@j%VL-zdQn`d>yIe5n40#(&BxZTOUT?OP7QT@_Qd)YJBn
zjZw`Lk4$cvdhE&8=_g}PncDu=@y0iAoqhYeRjJBomdLoZN{gc3Jt98$H4<;=P=2hi
z(RQ~GAUII}ImlmKhi@mu2Pxa&zv
zlTI#-U0Ah1vjE1a^RLfXI^$$)Y;2W&GpEsGj$_QPcD>N?f5&GV1E=@#c+^BnGx98x
zeHr@YTH$;6O>Wf+DT1JJCqrr)C{H3
zK2U}fvx&`YcE(#mXD10~p-p_UcN?F)sMhne+~#>&d>3}!=H1FC_uFhqC>-!TzI6s3
zS=YU|a@*EJY*yc3Vbj(bcnl5W+4mM$w;tO1TpWV5uM69^J~zn(kguKgS3j{B;S~9~
z_e*X>qGtdMnb15^-CI-c*($AeR_vgB@n2)un9a&ZoaPCT^
z5am7Mva*`)Lm#Bm$UCtQX)|`?b?PA7otWVCbNMDM>;T2{*?#^AdBY!Rf%S`ZVs@tj
z*ATqUlj8aHhCf?#1LuHMnS0as@~aAy)-HPjQPD4Av6-XGVCFjfW?mk=>1RpY0cPT@JhX#4(`doy?
zM8RDVzQ)rNv0sw!(1-!9!rdEG!+Us_V8lVE{qH}o8WTPR!*^O>?x4(Rw_dw3#$STq
zTU)4d;PurTW1}Sql*I2pv9I?$Q_c&pp7;qbJk*0WDOVK+P8o_ui86fv*?1!|e9H93
z$wpW$R>ExIGqCd)fxgW2ZmKW^H0735&@D6c1exvGx0quR`gbE(C!%^)IJU)bm^}tL=g
z++4u~?Z|~Q+zWb1V=dmPcYm(3lq%Lq`S}n}LL~oxl)|hMK
z11(JyA7m6Zb&?pfVi!M_%5n4BEajV-YYUz|*S(UQD)vgVFt5QrOp3Rd&V#J!VpmFwiPuk%EFhCvIf%;n|};JY;5+gOxtQMzd=j4E|(
zoib=nI!{zLMG`R5R(#}SnfWN+1Us~lx2Xs2J?KH+3tgdbvY@0LdfV%XOXr`QAG@e(
z(P*F@=mXxorV{a4YbBh5hx62gF{jo8g>$_dd-@=i*=I{za6-CksL}!)H32spLu0fG
zC9HTW5!O7cE%NHlM3@bxBo1T#(Z|TflFu;Txwoody)!#poBjjJ&(*@Z`p`T`K3|n3
z^i^PehFQQM);ui^)|xEmw=FJ+ZkDwt^}EO8V0Q#jdJc9<
z+`%ou_OBi13fycUV9pg*R|{(_=I@Q1ae|3xzvyyA;CZ3WVt-
zg2Zfoep)TSDB+3>1FO6(W@pb|ZiAh9#@U!Uu*{}ZUtaLNND8SHq}a!FP0gn2)F!qQ
z=HGqbq_>OdVmo8dq_Rx_gL_m$PT#@hw7WY~aZBZNm!j8Zb75;_{DDt>7;lz;4D52k
zKK6OoI}T;y7Uyd}-0hD`*%sm)^yB(9I9*%T_c*4$>~+Cap#(h9F~MGbzyW`jiJ83h
zUonir8}?9f9q=@aVwn>C*6(8?Uxq!3O?4gL$1nj5%XGeW^U&urVeO=UV8m)G{1Q2P
zLpOM22I^)C!;?
z9AlUYt?oRBG5Fy2Ck6n9vhhN%hg(WF4Gf8CK#(WcA7fC#d6^1-jNuC4vVDdzcmrM8
z+`Zg-1WqHMP@&(`B38ntXZ{^mwuCDdaFrA;sFmAK-kTe6%QZ7l^9r1s=_TMP71!(q
zscX1Jwh(FmNRw5#(TRvM9COGkNqD_Rl390WxQ$Uf6a)M{z+l@A`xjX6OVi>M<0({`
ziF@^F&9Gl+xV%><6-|o+nMwV543i2`$Fye37;_6nvq~?2IZybV$Kx)p5p!JD>NPP0
zPM6_jw;$(h%_R)nX*6PaSSts!5_VZ!QR
z*GO|pb687COIT}4E9iGbNOIVzQYPgTJgWzS)2#3drzk=?;M|T8c7YrR?BS2suQS9j
z=OtR#)ju9*V{)MG?3*~Z4tnJn#bWE@%`$E0u217)m{uw8w7XQLcVmhNFvU(>N&)*A
zhG;HxPK)zh0jm+w)vg#q=7fw5{S0@Pb$t&vAf&3@_^+BHk09vTK|+0l{no9VnDtQpGd#<8a|m16e$nbMEbME?l*-6-d;;`zmYk$B3(G%;kwjw!dh;#
zt?|ax{tlp>o!zO@ad
z^==D0B&Rse;J6RRYfoQ{`2n;t4)YSyJ@RS~iyLo*UTMGsvA2cA5t5G!YaZ{`xb)Lu
zac}+##+?d_gL2=8HOuS6EcC;A!cEUfxh~ir517T^1)$$U*veYv8q%y{Ng&93C%l3f?kkh}l}tI{`(7+5lG0?2upbSJ%To4k`!-M6yrcG>o^$QAIJyzq*2$z!bGH^9
zo(Am?SM)<~>ei@o#o11tfyxS@H9CKuLAV}jlwANoc#uaD-Jpo0;9d=CE>e%<=4^nSch`Yk-(I#YT-S}6S%9&P2N_ohOArS(ifQBzS8w5^+^U4z{P
zUlkO!cO(Hdij~&c){b_djA|W>p~DfTs%QqA-FsZL^xp0-U>Q0bN+0T&0jrdxjUE_$
z#X8s80aSIvPB;=y)2}XARL}}k0hQ7C8B->~fHLVFD3jiSGU**Cliq={?gFT<3HQO^
z(Xz5`V$Og^%bF_no2Q*==iCb@O-ogzKf2Y
z;^Dceh+hr(prtN9KWM3+r=@Z$W$7I%gI!$;M`7nBY_IpoExddmwpFnA(tG3!;}lOm
z8~CaL@Kr-n4x7;n6pw;^+hK>mPk#4Xx>&_|bg|6Oqe14a5)CDtw|^6NIMyH;_cLgL
z4Pv8c(D1+*27D#NJ~2!S*dIhdf%oXQc%OdXr^m+;-H5f=qvvIX9{umP%6=dF{QGrW
zDDdD5<76wwyByv2nFl)x6gbMani4868Z-Uscr&m3$CiVB9kNB8|;m(`xm
z;R>*#0h59UEBal#610=T76Z{hq9+cKV~1bGA<;Jvxj7O9W%^}~An;>g@xT#|mTR7|
zUWAj~j^DN420c~FnEww^R^nnC#cMa7f8AV>u?e>y@3o*CKUiOZDlKqFDvY#Y6uncu
z%=wwKFD3`xl**NOq#ggE^Rwf<8uvcn@D05%+L66}f_?OlSjJ(`ZKlp|gUH|I>iWtW
z_BC$7_E6S@_U9;Gc=r;-+b$;yUKYc)e!bYn!hToByN!1MUJLN(i?*}el4aDN#LjGV*6zX2
zs@3V9I?`V~%T>D~iJZ=~z|}ng#y{0=2Y+{M+jhHqwD^iVKS0LIqZ&fm0f=}1$+z4*
zZ@2JxA2;l>BjL`zt{0>z0Na+0hTWjx@lRW^PRrQJUiww*m5cM(Wd@XfaLF=ET}=N_
z>(4F6d(z8uH%XLHfP2&>e6Er(SQ5b368K!@l0QLPUbaCg*ze&DqtVUt6++-LLTx-;
zJJ-#{)FtMMcvS7;iPBC=*ntqMFpn$rsT1;A9jL1
zg)3yLxy8_~yBteRk;k8&yGO{G6wLC#C8Yzk6WBnf#?x
zZ~o!@map@k>&`!ukDv3tZh6-8+;Tkc?sMMpmYH|qNAvDJ=N)a~@4}n%_*V+%T31^a
z@9v;NH0(@<8M^b^)EU3VqBVMa5@?BkSTb0@
zzuWr#u!jrlQ0&qdE_w#yTW=W2aw#1)82dq_tPeYDgR!5O-Bg!y)&^rgkkHC?c3X^&
zfaqB#`#yL4B=OKZUDj|}zv*Ly!8aa{4T=qd_ZT7rpFZpwJg#WauMWLvj!Zz5(h*pM
zXGmaPN8VxSj!8Y*0R23c1RLBy^yVAiNCRD%Om$;jIMf2Va2Ryqj9V|{XIU@Ya7i!R
za7i!Ra7i!Ra7i!Ra9J<%SLb8B7}7~eA3zUR!^!O5)Q3kySBeZu)Q;?ixfHEmH-ea2
zVS&pvM21V$j_4+B!Ct_-lJw~vBJ)|Q_MvVP_mpiXv%cGTcK0_&I*zrSJoQcMcgHTY
zTsrb&^UsYqLQ3OBuMCAy+&MghkMlQQh?Nw
z-DHL#<`)!QH#5xNyP+hVh=+c)!@D6WBO_kBv%C=YcKmCd%DcWlok+k^81
ztNm2bH?5#eFIv-AL_Ft#erM!dfziv?$mT7j)Y&CcwthsC^u{sRa
z(j$)K&4B)_P`ZJj>xBzu;6TRJDr10W#hrw7w+
zB>u)S;c%zuB{*#lnx7w)Nf^aU{VG_etb$cKSPMVi1nZecU`-Krr#;#Wa2Hr-xH*!4
zr+*vFhQDp*4WJ2%@k)em?*J{E9A<|Z!^s{>&_A&>AH58p0qo_UIbg)!`(b_Dr41iL
zz%4A-VT>*Hh~dNGRA71!!o4)^mlO?2aNa^bLodZuTRU%qHo;9OB9)%xso~r{T!Y^Q
z__)Rb?oqZkjc-ch6}TmE6F$GM;+9DJDV=5SmxXa3m>IN{(-w6iX#eY;8G5`zkdq7d
z693Hu(HOLQHoXq94^v1+ST@7k`9ioCp=rwfM59v7SP93)OxctQXX)_qqah$betOl)s8o*ZHSf6dK(8D(YV_TqGZu-G|{sUz<0!|0P_li1Z7MwaFkT$p*Iqfer$h#kLX+5k-
z7+-+6*dd&eOcG&PB##;y6sX%jusQPzlkO
za+f=z6cON`r$2Zw$HSVmR
z^Bum=URy@Pov?75J)F`DZLEUZ>}86}49>E_Z|}KL+-^Nvz8vbb`?Xc(2)>j*wcKfc
z^lVf;wVZ4un_=DMUzQb7N641x$71lV4ERju5Awor7s*oIy8+vYokr@#g%&r(UMsIz
zR!nau8^3&a0)l&mKKuT{QXVj53PDi9GP45scuY`xp_5R`LsjZC+c|2*lcisjz!|I-
zW9w3r`k0`?c|19|r?+!Ud7KWqN%hczGaDo<5IxG(fv_&*C-h~LF>;jqpOf~0&ca!*
zF%cYE!S8V#_uLO11
zjy9f$JEib>JG=uKpNmXreZE-{AAu%roSd2aPz1%s_YbmfhN9fS2&&a!-gN|3=D6$r
z*je^WZHqwxu-6e`0>ALX!-vBXwZs@glZEf$hx_5+Mt-;rU7KMDt*cu$5Qt?j-@l7@
z7K4q>$9hm@#F7B+f95P3^+ju372J{pd(h?9?*;yT{))|05A+q^Rc88Ltm5T*VE!&q
zu1C80A9aQ42da!Rt{3*{Yu#9?on`O**MVAF%v;H@`#rn;9XM^slu`6C=u1(+VfdQ{
z$XWL2DSV&4Y)^15ruK=IctvPp=7;)(4v|92s2q)D-YNRKIc<|S%G#HDO4#zDO0i3S
z*mj20fUPJsSt9Ib1MRzxpFGL4A9DFPvR#z&$De7n8_D{Zjoj_6y^UUTOw;2
zUGFS=_2{HJnReqoXIbqYm@f?%GL79fcUx;9|1OsLEFA742J6Ku
zl4`Zvz7JrCNWo1^l-gT{rT>#KF1Brl)0hz_J@+tU&nGHd!(nwsIWaRTN3`&8|5jCw
zTmm)ta8Zo`rcKn&;+KGLf49R8I~R9aEWCH45#*>25HkBA5>StJbE(E7caOx~E&Ckg
zy-ie}3vZCtq!R2CGZi0EM8v^5V`Zks0^ULLO6W^r)JI@z^~_v2`{XS1JJUlcH5-c!K)XTQOH5gCvB0BQA8)};NQuSKG=F#Ic6Q;ax*PXf`$pzl1S
zXdHvg4Rvs~NT$p359oI`DVpkg%L_K6wQ)L6Y-7gY!PyWvW0GDr!xTyu(U>$k$l%L(V_vGzgxv996P`(41bVL1am
zWzOAEnecZLBo0uApuS92`PyiZheadVp1Uoeaqq0ZX2bmf_R8Qxy5W8z`1>GTA$a$T
zOi}u0cfB<5FTnI^=3kI}el02oRtF_nh4)N0K}_Kx%w1M(Dak8yM3Bv||nu&dGk
z?knZLfO35{_L*>Bl%`t!q2!N_Szs0JFx2D3ZG)Oe%<=R?KS&Tv1$xapDp&X&1^2k<
z4_j7b7^fFG?Z-Fcx0r9iOHjTbCF>S3+b}%6>Ff-$k=>{sk)JDWGz{N$T&Atz2zY=i
zavhxV|7q=8;F`L!z4tlENqAOhplYwS0R)w?RzXaCVGxptZ5?$)`|yPUkr@>qpfX>%
zf+1i;2ARN6rnZAxrFw5W6^g0tI05BRtWxYJqI27h77@K22XsWL75V<_oCJckz0>)w
z{=(U3Kh|D*?dMr*?X_^LS)}cXuP8>)i*4;%el+$va2tj;-6)qk%6*C+Z(qYyX3JAJ
z7q`3SfBM8Tm&4|e?J2WC<#Fn%&r6N%<%+O56Fuhs-c&w^9m#8Kqo=Az=@Zu$laxFdc!xbpp(^YzZQmoo*0}m(&OyOXH=I3YtF)|*svJF)Blvm4
z@6DQ<1MZPT?*`dHPVBd)9I4m-STwh2?i(3)-)mBf%>NhkZo*m{koGa8C68+`CROs7
z$KU|7xrbtLkP4*NnWYA`&!7}Bh9c*@}GOR29+K8b`_W7K3votB8#>(`rWhj5WI^eUBD5%*-lXq8EV@+kR`$KWBIkf
zr_Ppfidxv+NH>6;QsxDk&S(s&fc2jOvjPceLKGH1H
z3*Z*G}Qk@R`68t
zEfsS_7ih)_vsS|Y(j?Qu1nAjl`PsFV*&m?vL1)XtP32kXo-L(Xt2u^SVBTIroRHzy
zP37FL0X=vhoU}-BzBMDi$E7mMvm8Ak8!foiB;742{L~au=dWpa_bc$H|Bf+{bCrkH
zL8028#y##{i}bwoGt=l=cz6nou@qQsL*e~`#ygEvaSm6D^Js~*i))QG+%3mhVN_*Y
z6))&|{qw4X>5d)#Rg4MnXaq>uQku7YLN`TOMr18njOaN+XJzV#ASK5fu7nv}wG8#Aio3Y=F20xm}U(ce^d`Y@YdBm5>1X{q>*~)>cCv)ZA-gAi^XLzjoR0vvG#mVw9c
z{_Pl=)`ynzUf-yYryw++nb;g
z)au?{`PT+^Ci3;Pvx8>&A2M|{8N%PJXdq3Hpj_ENoZ;iJA0Ha_;r&%l}uU$dp_0y#o5m9P7tTPM2u2DR|ah
zV8IM=cei1NV2u9VSagTAc`5HL(Mpp0wKmX9U1jHV!C&mhZJ$7_!c68lPd5w@-6Uu$
z{-(-}I=MvasV~X2=0u(Jw2k&MDzDN>NUjp*sYm|xXpyV|yv;ir*2Z7G?VWe?4Z>F?
ztWbN~1gxCIwGa$OMLUgu_|E~S34M4tSJt4!3bM8@++42B@ZX-v*sHpwuP#*wZ}Rp)
zSWn@^b*UTE5u;w0lB!;nlD0145owQ%kBw0WCk!q&2&RKFTJ8pUK^j3=!g^Xj9r_gPDnJStX;n`anmMe5ee^@6e+*jn6f@yEF{JMd|{Lr
zrQWpBsE$ua5K9J6cy8-BfZCM$P*iG4YWy1Yn#6Tzir8+kUfss{O^NDNYvMPp7Atkq
zO~hTlSd3F|S&dT8$|brk-k6;FP&tvtF)8Z?wJUCYLOe3gi{F@ICtofIe}hdZI=hHX$tB0e{vDznG_#C@*3Sq|
z7#BS+P92T$lZqFyzURhI7_aH?-_3~|QIrxkt&VrVPTQ2YaXH3<6hAjby*YkOa)Nr^
zLKl3ajH$_+L92yRQAbo#qJ;H?wX2e7?9gMPBP{j*MjBs;q3%l(dwVMNJ|Ifz6fGel
zy}zh8JT!*;@erqmhziq3>kU+&REEeQQG-%l;x;Cxrfpo;-x<-X6OF%8FGyLlW@Wtb
zR|9#SG3q2Dp0gjM{(dnrAvs>Xl4@{3bCA<9f5iTv%0H#L-3c)JMiQulaBpu)brkbtKxPXnb~-JxZwW_Q|TW4i4(=QZ1I1p2zv0vsIr$Y
zJm)_0^WX?--jDs`ek2iTvgZFG{qrA5=NVJ(`;m0q8}i)rBk6L+hQ$0xx*KCp?O4&g
zDm+%Gxvu>7sQjrFTY^9O>K|W6FG~4i)4zSvvuF5g>7eKXz>wkDizjemoHLGK6UCiR
z3jgWqy?4upzLoutW2a8sHwMplqz|GK#X0{`{fEwv88Pp{mcP~QsJ}D2F~%(;_46yI
z&wg_F@9a-Mr+k1<^*aB#!g38e(_NopIzV774E%G=K;a)rceb~8ptML2CkRUCk#^rD
zo#^EJhdvT%_nk}neP<$`=p&{?T8~Tmw=U^!!*(yJ65j-}?$ujTCcGTFz^3m`sOTN7Ii^WaFi^RRt1>Pfr
zsQZWLL-fnU&*ydgN!)5oTu)ok@_|KftuY=8^bE)9iM2Lyz0tXru1&>K?R-J`wAGuI
zW1m^RI(}Wk8d~Y4Er10lU{LW&E);pBO(YiE3GJilj&&3JzCICa-nyiL^$~F?X{qbe
zQXR3*{a2riT{3wScHNB|)7Gcb+AHpLbFo;)tH*EswR#nD5MiWvz?qen6hQgJeV9%<
zsVR;l#W-Z&ByJFD@pzCh5SG?_sZ3I0s(M`_&MRA7jtLHU(%B?20Vk0p08UY_iQkx%
z7=Ysa^~Z?E7w1y#h@bbo8k-<(%qh~=JP>chspWg|zlb%c2Pa7IqjbMe$1Zv($${JY
zP0QD&B+zy_E^!t5QN4QQy5&aNkd|*sPU=7Jh;)(mDMU{c`#_{A_Uq(T=_2BZ2}Du{
z++R@PO=+7pja!I40eiiAt+=Z@X+E0{P5mv9Xeh@0BF$*TDbAI)E_>bD_~do{bQ8}M
zz+BvzX|EFtNw5~ES7Y=fZd9+@h+~g)a5~fGJ?{#Cff|&P+9bAffqLHaVS`{HU5s#+
zk6q+iJ{o7k)zlt3M~b^Tj*Cj4eqLSPQ9}#WTGRk;m+w2C
zv*8=IzB?1Q(v%mpZNh~IQ^D=9!CN5R-r)@3D})*S;R_LO@csvXMlBOrUNr**>(Etp6jeZ1G-rBxJj7VJ2b0dcph{*
zao6hM77|Wmc}vkWb*J-g$f6S}C8R>DY;JiaE%Kw;#`qq$FiS*}iaf$3*l=rxxn;$Y
zhdy|M%EcXog`=7E;%KHx5Y*#~I(^B{7S!A@p
z|Af+mubL5(LutjZF6Xq|7dU5;nf#HZ`1k}LwPeNU?2R*OYymSa+P}}2AgzZ0edVHV
zt$AnR*MgEXj2gso<*I`g69pZf>`tGqXJNC^qVj;f-0~PVj3rs&XC%1~%Ff2UOIPT`
zyFvbOTl|B`T5kH``;a<)d)K}&%9rkXbeYQaZs7Da$m;6dh+8OmN+u0EN$WKfyv@q&
zI%f1EYb8_4@^pT$&oNhN+FlaGn{Lk8Bw0+3q3S08kfeGR>NxDU!mXJf)#@WL7CB7+ymnxny&^67fPHEw;Z
zCYVYJ?0DW?%%;{MmJV?6SqfXR4Wm-YaU^RW>Z53itUX{LJ|N{4>wq66i($WTlTqv#
zmIc__KuPj0=_AZ(CL7HQPV*-){vt`%7kWaKEoUlAmWTHl(j>E*$O3bxPxWgLV_6OR=g=4MneePdw0}q3H`F7aztEW4&5y4St?l%=
zv^7k>4-#>rHaxZHiN^8cL$hIL-KT7eYcJCXaDlKH5VFHW7-gvy{V)P^MExE>x#)nR
z-Sp2v(XM|Kl!;>{TrRD1g+lrS7>T+8Il`h-`vs02-3hGWIs6DCX<6JT8c`~DSfOFN
zpCvtreV9{nmj4-e-Ft5HCY?JgG;C#AdO?5OLU|#})eS!*(;Z56#q#
zM|9xS3*os(dC%EBTBF}PZXcEGfC)iw1E?>*j%9-nGpNFGSa^f>s#AqQdS#
zGF{G79pf0)vMtY5yO6XA&G61!egS?5&8%}?lz0HtkfF3GoJW8{-v@Ov5%vdqq^B_rYe3*Ao
z*&+A%+x@tPX;I>E9jodpi5}pqb()j5(Eyoq(s_mSUQH(GI`6)OW8s*HpU2FV(G)GkJ#J
zg4*O=<9ALre`F>+Bs-5sVT-i_BkdBKlXKW|knm?+8IUTXmiM>ehRjPf`HONa`Iwbm
zf4n`{JSXQMQkwsdvyKYUkEK)-t;8g20e}}>-=Uf%nZ>fOHh4#DQH7V@
zJ(-g>RmkVirh1;d2+?>yYJs<^;LD{!<28ZcY0RvFJCR
zM(a`yQT_W`Q!2&1zD2+L9CSMnRDsojpaq(bN8GfL-qPIj3(hV2{FUZqO^UDRR=X+2
zi3Q2>j*3<$B|N+}O*sohJdW>34EJvgwKP4{2bt-F$CR0p{!zutfv^1b75>#*&(AT>
z67Qe?C1(++w=9=%et%R2G+_v0p!rPr<)4Vl%QFUWnKo3A_BDd-#Gb!w+lQwB&Cy;=Y8A5v|20eT2-UJHW5U
z7~t!pG$zA2$lPve!(pkl!mu(XBR@Q%jL~?Ow9V#{73J&-ixamw7ciT;{`i>&bDRZm>ol@Zs16(sPS
zzaC!1bfCa_z7}?i8qs=gp!Jw9i%fc2fwTDu7>{QoOok7Dd&NA$eV+kZocSc{4;RX`
z&b5H%pGog8<1t&_{CdMotpAO@3u#U{b(>6jIp|RYdIXxMXuh<;#yr9YB24;8LYU#=
zRhhn)Hyg5IDoYxm-EsFHGUPYM82R6Mz`_B}34!K_8D_moahA~vBFvz2GD8s`ray2M
zzVCR?k`6^>$rX0CAhJHtJa%U6P1hPXAirOK{b#1h43mTk1GL0Z(i~G+bcOZqvVP#l
zD&@Pihin8dD`szA<>DT?*)yc=_pNvQ?T;xT9UMZQAjy}<&4TcftB_vB+AaT0`QOY7
zf8q|CUof>k);78RxZM;}%kSM$d9H+!J;l;pm6LX}7e(rmw%wd&x~o$>V@kU}_AKbq
z!73c^g@kdx@+Pz1QSdYt0T*7~{J7#%mANJSN@bybzw#{On-0S@^TmS5(Zu#WW(3Wy;;77GX?vVms#X#zKL+^3ZvT^
zA?7cq48QJ*)7Q!~z~-(4n=&_3!v}I%!`pIU0Gm6xz~<&d*c=HTz^34>M`1Gw*vPp@
zW8)JlVRK;Ok6^=^x0xEw0h`)KU;|6{UgSw+Zc{*VO|sLMh~!5^AG$I*FWdyFpgDWfWJ~S(*E>7Le{?Ou|w~i20cr
z1Zi*5QhQ}?qAbLmv8yuf1O8A}e7LEh7TyB7ha6TW+cV;%{VL@1&}@Hb^R34GQk=)i
zwgYPmMqCkFEv|!_)L|s^CY^IP^e$FKc^P&mf1D<~eXrB1=#5j2umXGQrER^#%Wyxg
zOX_bLf$1CQ1V|n|==9Im!U~Mfu@0(H8u6W3Cc`K>&JA)}j!TG
zIEf3wipW}6M1$VT*YedYHli`*$Wo0_uo)sE$l975bVhGJQ6D(id?u9cD26UUC=%0>6LA
z5w=pXp{7trA!|zxd+|46=TyJT;lj>$`_X!3))}uA^QPG(`yRvmzqWP{V>0~}S>p|(
zhu~JRXqF=GH(}?^I+Ok;XIAVVau$A8IN8+CSG#@LhBZk!utSo*GGzXxSjqIYz~vkl
z#1-;pd%n*2#s@5DNDT|(YIxb~+Z^C?d+qQoA?B4M&X1?Og|KFZG+4+^wMg3*-WSrstY=Ljx^NrWAigG4>
z5oeks7keq+V7=$T8%-YgYU%b9S8<}F!FaUKbBuZ5XrWd9E-fPJ<82AJSJPZB^7%dK+`M
z7FdDC?uG148!W`UaRqT#5OWK(!{a+EQ77jIQgVmIGdO>0HI
zSDAm%+JKRl=a>U?zQPLe*W-b|4}2rA)Zbp&5yM5EhA&)jhE#IqQ)AB<+4gVV_tWF1
z*rlF0RSlgKO9f6TbW)=p$f+kS;8!kCPaNI(Q6A>YakRO6G?#BM4!_G|K65hkh2uo@
zYY)B8QkvjqI-?F+Z)&euPL^ph%487K?Ajm?qvq;yF;)6{dp)xck!W&P>c80rYI=
zkrO?Rzqd1n()sRg!7qiz0>TCSOfLacLmGcq)DO*{Ni~D3=k_6PUuNE?dygNU{FZKF
zUaHX2+qWl0J|=SQiRKz%`35H{f;HkK!TDCa5nE>`DED6_9O>pNt-^OeaT$Ex2AqV=
z36v4^vf07tj|gc0>0l9}j#u63d0>>|=JQo0*SiH8LNhbq->n?y!^$8GP`!A}a
zORS^DW@K)>26{zjaijJ&?4it2(%o2h(c;HZ#a$bR8>2T1T12XkKnuD=ivxi0AyYpk
zsARK)@@6M$HIIGUH`Y}7?I&D#(ooKGaiSKM=7T&9LX=RiQ84xVg8Vu>wet*ECJ
zxfGUQ(8_{C+v5s67Yk8<2ijyjv7z9y9ieIpU9?k9I&)?eG}@_$_bgKNl=NALK7p3+
zIiKHHXz)D++n@&0U2->oSFXAW&#%-*a2bK!)ME0!kYxzp0WT4%9tMqA{V+yc^gyhU
zCjA(8LVP~QzE+(5P2Tx(ZK3k4y{5+00I$Lg0((lJktb^ihTn0;_E};$f~|y=9O@Zx
zj{`jyw`fiEamcM>`xF;{BWp-x$cJYd^2HTca}16=#mHlJETQ{~8$E9LV!ve%AiXxdq5bnb=xfj9wl8X`Mnu;_ww
zP|Zy42Ic-Dy7V+=M$Q$Q8L(6m@DA?pcM*5MaRc+g94$6<-1??JwzyWm~q$V5xJ3!vi%ZEKN+qRuAKaD2TmqeAy$JN3{7
zk%nmnx|1)(y#Cp+*%v;;Hx>Kh`PfeML?-!_x=ZWXZt5NEe(Ys{%CUlGUM#4xS@iJo`7KJRkK2Kbe=9?HLcSgG!&>hktbNl4
zym|=p;|SgQP7K*KLm%`~XanMyxV}*+Qw*hxcc31omU}p;b$t-E8eWPCI^5wlY)Gsg~SNH3~^o+h7aOZHf>kkk>K#%lXwl{!>%nc8TJ9T*jWfhaa64ZT#<}Ec~mZJU6>?
zN1g1J3I5Yh3bV6jA2nC}W=dI)vgfZoZr}b@p;WjT^E5
zXzloV_#zTABadrtX#;f?B43u)$T=tG!dgpc_T`x*BWs-LkbJE%i}I?+W4DW5)=9=p
z|8O_q1Yc{@4}rg2_yY_w-ajb63|nT3UxvrE@M8_3wfhW}xi+4-+vIbQo{#s3-aHwm
z4v!h%-yz}my$
z>CYPyeAyiw@3QbsxMfZ^&8?eB
zII^3O+_m~=R;9c>8Mju&`Yz)(Yuq)C;_$Va84LSqY6WUgwX)sO?(LLD@x+@xDBgTb
ztlDj87jITd_i(_snu%L7-<31f%Lj0yQFCAjGs^=sZ6it_kS*HbpTLSyWVrA)PcS5@
z;*Bb4^_K4RNBKgY1DTn2ohT1jpQWRxI+gzJMjGU_{v>^&Q05XFRxHqI-iL<7H$H6m
z(4b1{U?0Ld%F8pl#j}iPS5l4rdI{-IQ*Kka0bygSl0l9l+TqN|M@kQ+H26d%k+igQ
z6>OsAC^C)1TScxMhg)XdjHLfr2Eou`A0k@zogiBFCAjo1*&Sy6)_p17`6JoC4EG*W
zE)6+E-}AEasIAuAnk|wKQo0pQ9G<+|ju^;UEO}ED)7`^EcfPkX|9RXb*lN7@ogDlf
zoMuL`edH|*ad|f7bewdUanDs)v5DF$D22SBeV4cTCI!9CZS_?eSM|V;_C-ct@&kPR
zivIi1FHYRzuOmtEiiq#veGENyQ9MVN&UD_`p;HP;hYy98hRPbEPLh07g`2FnbMiQ+
z^KBD!M*<_-Nwz~WHoB2k3@c(Wk1ri#HAkHUpITiUh_64tZhm^qOD|1teogDCQAWYS
zVc%=SOJ=vhf4L$*MmBPlx8)II2oi3hfID8=U@|O}Wp%u!Ej)>PEciCjh2O9b?C^wH
z=cOTk8o(4MCg5OI#yqa5H#IcK2^)fPPM+1V<^|va=rIa{zEDxxvF0Tjd+xZ~u(XVz
z(!4d{?D=j(bCh*UJ$v`0=&KF4ge3|Xd3U+z>L%2NKmJu04%{q!7QU^{KY=ud;g=w^Ns8t#l(m8PHG?IPSRDSVt
z5$xS~9yKh@t5U*~8}6`FxVBG~+C7ABD`U*Zk#>tHG529}>1KeO<7TcZ?UVh1*{;h^
zFs?zp;DUmGj`!p|xoO{r}3{5L#LdN!PbRQ0(3;DiVSpdI*J-+{hr=s@DbcLbp9+)vA7Ea~e1?tsSMc=zKAyX|YqDnWU#?~P4aU>c+4eB@y|!bCMspu(
zySi_SjMw7VwSK77b_dKE{q!{d>o5oC={6Y8e*$JdJ)yz;T;Bkmt}xN0fqq~8Q}Hb8
zZ~FjDk)8u>@BFDSABCrEaNGY0JpZS*Qy=-dw!MGM|8T#HFlhqd_h@?h4IZEWMB4}B
zIY7_doK_)?PZ{%rg37->mIh!t`-s}!sr5rE7^@z~uk6%fg5ckdV1(DZgtbqI@gsgl
zd4`JN^mK)s~s>WVLYsM(D@57EWww;Qhq5c
z!I#1kdr$vsiZ4K>S_@92!@99pj&H+v}){!e$4~yFfRyV=PHwsjf?6
zyaZDUOLbBBO-I>Uz@jxhD_puPBi
zVO>(s#hUE8e*R>bef@if>smJm&o_T$@4zxl=a7fj&uYdL_%Y{Nr=Ba&_twB3H~&Xq
zK5~Em{`#q&`_P%;lb;InQF|OdaKC?_p0vk}$2g$hEc|r%(d7jC{m{FBH2Qfvei&bjej5DZ@S|@A={_@Y7D7(#
zS8}iuZ_5SW8XBUcMI(DV_uruf^9S#C8Kh)3$On3d7V0k-7zKQD-?+-)^MtkX`Ff+g
zRRIp!W3BjR%6g|*Z**@}l`s}@TzL0KU|DI4;xX{~)M#nkrNMEEc3
zY_|GT@)nf(=ijxZw%)hhIdC0sF-J?<5_;|oK<*NjihQ_7wsCA{Y6r$e#B~8?qasU;_piz|
z<>eH6;iD2x*LLmBJ&myJNpLE*-XgL)4yw08tlgeOL;TT+BKSqQn>lDO{L8AqMoH&=qP>s
zj495p8GW0HaJ7jx-*!##+{eIasTS;_ER4-K&f!ZB@ebcP0d{A|`(wI&e-l;{sD~j3
z{KxPc)Ss~DcCCZi48+$l9QUm2fWErO@l9L_3nW6>89R4f@|u%pD<5;LVJ&KcJZEUT
z+!>oYD(f5Km_U*d>>1%Nf7fPwOY#!}9!fA-7|80-v^=ibP{rxeKh~IAhXSrPrEBIX
z+hXvLa+RWWh~e$TTiNrfIq%TPQmGDK)X^bwVtmP8PiecLC$m`IQelcq6+#
zob4+gbL5>v2BTZI4?OYkkZJMVUIz?q!@KXp9y{zcd)iv(x##8CTAy3`&7N6AC1bwQ
zD|QBz|04Rbsqme54Mx`e*bzh9)7{@n-{i%|ovm&E&dDu{6+NHqc$IPx9izDJD$2Fv
zReGz7khoGx_dHwfbjbr!mL0ZEGz0OV+n)UX)|n2T>Wjnx}_0P?=(D~
zCStxvl!wYjDbeQ!pR7;8$J@3cT#$#ynfawv0g34K=JexE4c4(^F`MPx)D!;QJVC-p
zP`w`QUro}MxB}{n*H21(5MVLkGVbNrN|^dAytN}oHOXpkf)^!#3z(+ibcq@#AB40W
z$HPiXX!g?aWt3EV!1ruU%!Mh&P`x}!%2~J=O>_fmS#GQsdlVK=H$Ua$uH^>PLqw%(cEX#q*Ytn1j
z5-r(Xe@g+4qOKOmno;frl6iZ>X4HkKFtVn6dW04hw&BMF+7rdFCQF_iwDi_jGy=Rb
zQ8J3Rr^Po&MiE|a9Y~?lWHTQ53n`ZD!b7(RVc2RDQ{3xSLNkx_0@_8S9zeU&gRy2i
zE$@(haoi@@3G0g?p_by1%A`Xg|MjrN(!l8g#&fzO;~f-rd;R$uks4_Q`{WmQWy3nM
z!(x8^EcuJOGC#fWJjQ~W{3c!aR0a8!X|&!wW2jZ3cQ4Ef_^i#Md_ZGUcCg`b@O(Eb
zy25{X3LXm$sy(x)9HiYRtSDtu$QeAB!COmOLH@}$PvwI-=BROV&1c8qfHe5O&bN%T
zZfS>{1#cyRxDf5P>W52X!jZpf
zoD|*@?Oh{aenC5eAV0E92HBb42F+HxKqm&s_s&9YIY480-Lf2j)Fe*RPv2~!uX!e?
z+c1-AJRR*yOI518EBuOuRbyNeJv0g*@*HuJR!O4lo>>_~Zx*{(w?l)jUkg0ZAs(Z|RGzaC
z&_rqHO0t9g_Q8cTlWG2joKiHE8c5443oYt~PMn|{53AFCe}W842fJwYyy9$ypclh6
z(ztP~OX7ZsUS3nq;9rx$q(
zPqt$m`3H|t?5yxT)-#$xGZr)BvI7e30%*}shBH)zGa7I-pba#HAfLgy;R74cWEn_|
zQ~H8Z@aYA;p)nLo`-J8S+A>=qt_b8Er}I)lljNlay#?PmBjEpq!`eh4rze~N|2Ndf
zIJv)MD$jj;>4u#8$m)Hyd@Wz^@rlQ2k7kc^9v3{mfTosbw}-3SNQ
zaR!r~W5r38x!rvD;#QudeNjoq-VV3@pp{D5HPM)2a}x|f+-1C}WtA=MeB`OfrpV7D
z&qw|x@~cuq5Pt-{X_R$CmlYoF(3jixO=o$4?AQ>>X1Uw24P!w#~s12pIv5VoE_Ik
z;x;3+Z;l~H*BlDNuP(yydxWsBp%i&0{F1`{hG!^#Glhp6X4q&w*kWl*v)u|X2sXO2
zKL+1M{0}@iPD)1>@n7mRe&ylc^XxS|*)d-T$wbGE*6@+j$^a0
zajYwrXRoZ}Ge6oTzWc(iLO);hf9ad?Z@Bx!RtRbsoES}YU!ix#)YBz94eU0(mofD?
z=~I#2r}w=~{R}65Ix;ytA+y6wJ)W1|z3BY_Q-j+FccF~=(fe*TA%c_MN6@>LQGFvQ
r{iW3Y_mT9j9!P(h-p35QtLfbxzo+n{Z&sLgVIpt(S@}u?`~UqvMVz{a

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_autoboot_v0.56.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_autoboot_v0.56.bin
new file mode 100755
index 0000000000000000000000000000000000000000..33555dbcd8c864dce145e7efa57ed08690d864cd
GIT binary patch
literal 468448
zcmeFa4O~=J{y%>1%-nki6vZwu_*4jq#cr;83tD%VW`LPd^0^dk)74H&wOf{^RvQTp
zcLr1#@d|^cg_cjWnR1gcTSZV9b<0SFQ7c2QfZ8gg!l()J`<#10u-eD(|M&m@{=b*L
zUcqemS=^<$Rj`o))
zK;NtmAuXjvlm;4-_V6z-`*Ay>#?MB{Z&NtMS2FVgMY1DBY;dDbSC!5lFpl!QV?I5AZ{+)P&>tD^xeofC>!9zs4*H(!
zpihAMq<;bUtX{*FYkK5;uMqvvft=jdkEZ`rKZ^W!>IV(_p+{SOePh~x(>K+rd&7zD
z{e0hB%QC-J`UVO8Pw2k0@8+MOTZ{UARjSZ^|9{AnJNy1Qy0vKRjITETgeM38dwxe~
zcl9Xh9jMr&HE({l{J-h@U(+3eZcce3?(^+#t}0IePG4MS<$i*)xpzW+k#k(kQBEGU`L;(elO0
z_NHMQe=Q0b#((%6efg&*)Mt7V8vduI;E7|XB1l*M{eKY%^7^}<|C$H?KBw>2{J)R`
z31cQ%CYUCf{x6)`-6`GWz+Dd9<-lDI+~vSs4&3FyT@Kvkz+Ddfhy%l3oRj*aqPt)3
za^Nlp?sDKR2kvs~*~KH5tFIhwJ$|#c{X|o9
zNaWQ>G_2s1Z9{pT_B{=vwNXXSAlEaR!?q1eQlg3?(fq*?54$z#>Ee
z!`ze>YGTFEeWE59wQD%rJcRqt*16`9R*?nT_oy>%Gi*^>q#c?FCkc*HQ5!0#sG@nu
zHIG5i?>Q-V9^%X1LQ?O`R8+(cq1n(EJsXh8bqT%m$VJMq^rH{BNkQowQy<
zII$st%wtLV|Lz(5Px~kGD_)uB=d|hJ_h_ZF&!AUAqar4gvoAM;%LlUCdN*Sz-G=AGOU9%3`ie0Xl$CrpQA^TA{V=UuuJ@-+745Zqr70&6e|-~@
z_4-?4RjZ%(Z9>C~xKY>r(xP36vW8bYU9s0b(%ux2{#1!E#<9)O*-wel&7ky4xs+L7
z@nl73DGp+g$RbUi6OV3&m0{W`D_^q_?G~1#^WI9tPp(8#ehV6#)8@XjuBgXcdOoEU?JlrYF{sof!qI=;(Q3rYTVclaNbaE9sK0lswFNI${jW|c6p9^KEX*pEl^er9yd$Hl#
z8Eak{)gX+LPMp`kEN)y^W`VC7s6kfAdmimAuz6sfFo)ePWft$Y>Lnr6L??1JdWtL1
zQ>G;x&@6d3YNS^9(5;#ZX0mgy9lz;D7MExT8d8Do1#aM0qu=5Ra!QLfchJqJY}Qn;
z{ACZtGYy*EK=%=#TVy-wJ_51^bmueF^qe&U4$yb3(@a<=o-P7OaDyb6tnzo)ug$V%
zlu3o>5nt1y@U@fI;%Pm_H@K0MQlnLQ%rC0Za+4V<-bT2Uz>ap}H@!eBXX~WZi#Qvh
zRbsqG-dC$lU`$J-TDY>3qedgm_Mlh?zSV-N@;L`tmrz)j7T__gOMZeDXu~q9+==UI
zLV&0KRt-nwI?hWZqo%b(Dy>|MOKW9Oyo=})Z)-H-yhaUemj7Pb%d8jvK{Y{Yv(g1%)aX|@mXi|VyvAw!8L^pxnODL!lt=vO^Z
zebOm8w`gK=@hu-!>f(B}0L@;6TYMDPtKMJgk{mu0?`zan(B&DDw-H*5bxK*+HG2j8
zrh$rei2~sav{+!EM4{0i>*7LtQKq?Lb414P7bnA5tidF`R)fCJH7((DPiQ22jfTjw
zlyy*3T3F?hgh~y*>P0v6#afms&Brs{8o9r_)|8rNxZwmDcGeFf&rVaZm15Fq&m=nlpn|tH=
z`_XzU|3oWVqiE;e0+sh(&`vLC=WHZR`4+Sj_|{m8_|UnC1L=__d$g*gizzfEE%az5
zx)h|m#)+@HK{s(d$oExpmjgQK(I(I);38bvX*m+xs==?dAWJ@;4N@|n+zrg(C(lM1
z<}P_Ac1M-xICw1+EZf{UpqcACH1oQ~l!~vM*Apqi^9>ZtzCq(5%#(o}<)zZRc&8$z4#+j!s!Td;amJax=Ro>u5C`K)i#(c6?tPxCY8iK$p$G^06c3CpHG+;i>S6rG+Z-czyra=bT30aT
zOVpaAmQ)Y2cD)|-3)chJu9CaeIRo8tW6j?|qpr2;$ZAS)$B0H9YelYbuu)kLoL*C?
z-LFUSB3V@_E7gb#QZ@KoDZAOFa$RwO6rsvF{`>
z<#VU!O7vbMm+SZQi>oNk3;MQ%Z$Cmw>=#(4I3pZ3E{5E`EZ$VP7*Ce^UUg7R{*b9fQ#
zNsWQxXTOJ}novrRinF#kMr6eb78@>LB2=BK@+dl$iWf8l5{cyFJg67TPi{cPicWDf
z(!_%0tT*BwV59QAASGax!)wt=7~upGr-HoHhHAMm;yc6?EyepnwXuRk*LL_jH>z-P
z0;ga&_wqFV-Sf|h$i3*H9qSRSW>e{R*p+wq@|p#+g5zGjXV{M|9|k&XTY
zdSXt78N3~>_=vfiz()|BqOJT?57DW`ojS!*gUo!&7SJgzcsmZfT@1{i!H7c}^pb-$
z31&jIN-+l%ORWYip@Dchz86pcb`rP^R1-T1R4?#Q9N5VOSbdL4TGUB5p8{=IUM6%m
zXhwF@&2*!iQR!CW6q8w=eZF;;Ip58PLmXGrhzJKIm&#K@6FYeIl~{sz^rJpz7>=4(nj{F-N@>eq-I40TB~$U&ca;@28mukbq$
zDt;|UwIybm_%-vFZhk89YhZDogIOMHMB)sPk%h;!lFO}1&%N*rW~$DTOMzKFaZKgD
zGgZ?MX4y!%PhahrWh2GWvcmmFh?u=vKE(^Q!N+Pu18A?U#tFQ?l}ctwc(2G=Dy(}W
z%rb#4e`#WlXm9s(Q+iR{RIs5Cee&~bkhJhL;(Hy_NX!WhiFtVKeod^{&&BHxYVdq7
zT39GfVX4?cT*qqVRqV;~)HXw!6FB=8=zHNVG|!b`mam;Zn-=<^lwqdK!}rA4Mr4&b
zz+>fidaQ;#+*%n}{v3WYEI`zQy}x=8JeD-I6;*YMC#9^;cruidQm%q_frV-WUWIa$
zIGNaEx28kCzz6UtZm_^$*VqQIzYVCO0M|2MRmt7zT*+6eTK`(`X)IWOrWQO_4N3ry
zMT5s8ccI|1La7Wh#9OM(d@js)#`>YVn=Z}o(k1XuDa1c%A^we5Jgk)EG2+!8@K3Z!
zoC48_BCW(f@g4ptfdxA%fPZ?;4f2X-gWSz0ci@X40_*Zmq>gA{As)owp*m?Kci^GQ
zI-;dn#6#^YmeDG2|
zr`Nw~DYT8!qrHVn+>vE4;R1tJ^-%l4L+w{Q)O(#CYEN8;hhjQBR2U@{fb3r;`X5Sh
ze}MSvUiiMS5quNKX$nXD6GUcYZd!^&T8hVEzRcxq^~B!XnuD$ss4`y#nmtF6`6~sI
zeU6d8+Mtzc8^FTy5aWvZEc7DHmQX1~y7lNvzNpxPN@!IN`B;PhNIcZ_9fOdTEB>t%e{1be@
zKk;_rpF9u=uFEaC?Vs|&KS_nKel;+s`Yqs}Xe#GZst`LbN!L#xE~SRzUcI(hY-w3M-N_wmg(r_7aY`+ftLN#D
zja+yvk{ZIO7(32?_F?=~Q7~Rb>v+(XKJ_BgyciFtjrsK!j&Ai+7vc+d7f5l}Aw!}q
z(~4lV7vnx*v;&H&=Qidg^*I)pd&m>v{WvBa
zeVNNK=~|q;NuOrH#!U?ILjk$cRG4jk73lauBtbO9KZ+>+JZMhMCKO*dGM~^OF)b+4
z?q<_bi*x7SXa+LT#aP=K9ml5o(+pxtI9lN3UJFP3c@}2uqb_X_X}Vq1LzDz|o3da%
zNE3r}JiW=t7iVKC5ykM*}^fn{-km*c}Hu!_69jQpll1c1DGx<9Xgjjq*H`
zeX85@rz#wTLsZg>d*bMHG}>8`rEn=Rj0G+|9;PLJhNnYKeAs629R^Br!F3MAa&gV*
zODA|-s=@{FNGYKvK5MA`!XD19Z|AhoYKjL@W}NjL;231?&`0QIbjYc;q^xJ$kT*du
z-;{Ao2;vqrEH+&t^B!~#)ASg=0p`+!85UniRv^|D?;`xa;lx>NGTixz?awe*IB1L5
zx(L-YV6ASd*cytklbIsc4@T=gP-J4@0S)vvBM#){^;|AC4Bf+EQFyXMApQ5LBIOHm
z`BY&fGx(TRMSNZS!Hf&IFi7((Kae+&sOXR
zKsi?Ix`FT-9q4`Y;_NNiR=ny4lGo_ksid@&wiJ%3TbysswutpWr{mY-CNn;3pj(ms
zunyVJWryCD?YG&X6^=ETpO-2%I;G#%twtWHLFitSNlAA|zg3a`@jsIO)1A^^1=TyH
zU!lp-V3cBso$wlo4y?)S(1KoFT5u3zrk~S-@;kL)VZ-9Ii_&vGz^?$6slzMv4DLe@
z5Hm0M#g9V(QOvMP4UNPG-Y?dI42Bp`>?*OqfVkF$Ag^>)fCXnC>KA0e%MXPMX1q24
zp0pC#VmBeNw8}45g+Ys1>0D9>qO&N=p&jOvlE9kyoo>Vf{QOi7==L=T&Ml%zY}m>Dp@j{g|c0h`z1K
ze0@iTxy{Wl1sY1N6d&L<@&Sj8M2`4{htNY+eBgEC>RkTOQ52s|Rvn`NCRu2z^Otap
z;BT|yBOaXywmdJFHyi?l;S@TV%ZDFE_;EW!<#KEof;ttAimdm|m0TcylObaYI|#Oj
zkKISCn70AFxKm1vp=z!UbWei5AN!D_X^q(}GD4dab_!9W#+K1xBC&!OYSFG(lir
zE+D*2hg6$2yePmbzkQ)y&epYy^^;M&BWO#BAb|yyvzfoBJ!dFmx?$CBEmIyLUzrV3e&Jy0wFhBIy
z*I$V|KIQP73Z^#tXma(qBa=RR>fns3XAZ<TtZ^Z{2H7yn~K=6ZwdiytkJ0FL(3n{7Z!<0x@@8g$kG?u%ezJo~D_inKV
zNLT+?sf^K|yZLh;pwau>zzfOu11iqudNeN%8dIKh=m#$UFyfvBT5FOiaY4)C28Vd+
zCiP)CM`+Ei4-~y$Q(Wl7XnIbZ4m|jB(e+!%=|lHXRx#|CpbHZHfw3*@*Jj@G6op@?
z2{h0Qcx3aJOPS(=RSCrfOY9ksXN;yEr^gI*lRGkUz?cWiq|{Z^haTKhr-_6)_P$jt
zh<0U`hrF5vR?#8&L!Er+HHek}j`(LcL*9G~b^~CRwA(n*JqOx+aUHyX=7O6Ogf@QF
zUtpCh-Ta(YRNo_H&1X4@W$xP)WGzoxT}CBkSSd4Y-Qgy8a>^JRmz2J*37(6u#9+a#Jl}NlI?oh&b(K$W1|;PjA+6t^h#yB;RIDYc}8O
zTR;@11A4>KBg&P~x|c3jrp_7i|6
zo!0W1N40$J7g|Z13wS3>-TRKTmW+gxWEd;&!76HD7Q&Z5m
zOnh&O1~LjwRe|IVgD5NB#bw?A1m--#ea>reQy7Kkq(EGM7U3InAb(YBao{Q9UAzr4
z4mQOomCiw-&bAcHp6?}1+66)4SYzMN!&wv&NEoAhh
z4d43g?L
zrD3TtxNVD)A&CVLf9(pREQJZK(kvVTZ8G6WBlyCsmdEf^)Q1CZ4*nv*DxM2Ln7zP&
zT|*Zb%mpx<&xi6XxR+PQIUwGO^P%`vyB#}<+Cnod=1(WtXJj66JmY})jP*te7EE~~
zvn_I{_vV8|Q|y=A;<-$SY(Yvv1M`aFbi{s97LenzfCkRtK<2U++exlG%h?yK8-g6+
z_2pa^ZRFUx#n{5qoEL1N;W%~D$xVJ3B{(Lr#P*G#7dVG!Ov`zT;ZrMN$1h%3y>EU|
z2r8Kn`Q*wcHPfz)ekS>7a>C;!k4KJKImQh358^=W4Glz{dWa7V0YC+z=)t1dr@?N+
zSmL=SQM@qLJ-fBCjJDzsy^h4nk&bnTAqFKpVNPmbj=fI;w*xdCF=);v#JN3w&T2rB
zF0lL!oZI359A-4jM#|`Aw3(-AlSp!@icLM+Ecoyyoha0s_!FCv6!tOL0XJlMkoSW}
ztbsko_YoQO!-|eEd!E$6nDj{<4i5l&U>(fZR;s%l_vXW@ZxN=D2v5nNz=pyO1rrK8
zBlU@VIP~A)ZEKvAdAd8Gfq1Z!?ibsM@41khahS}EtPU;H*6BONTEgoZs>T_VA@^j@
zbG{JRt!2-Hbv$=JnzpmtnfFDuDj_N_d)`2T6=VeETXSrr4rQjSpX}LaeeslFZF9r5
zwZ1HlCTmW(OVff
zV&iz98x9|L&kl5@{)91P(w*Cd5~P#s~z8`hg|eJ65R&0`pmT4K^1rni*N|gdh8r|$QY*%12b{oe!fbN*Ikne3!*$ZP4F
z8P*rw|5K_1py&Vhss7ioiAZ9T)s;y60b-Mrhagsg*u>run=Jc*5lL(kAYF)4W0MOv
z5Z4b-mStVB$yRg*Vv_*PIPk&F^lq_V49(4@hiM
z{cc-FY!U#m3B)Z_GKo#LB2!0fas$OI6}w^+h)K9r5T7V<$?$X%nLMOMCafBn^wLdV
zPGYF(%Q-r9ABjymA(h#A}d3-5T0+C4xiA+XQ$r%ut
z40e+{GH$?_;Ywt(XFm>9B9rRHS42jQzLdCxRpOEmH7=R9yelf%Y@9}-lIq1x>I^v@
ziAt9Llc)rCGdiM@Pr5}V*$|cdu1vN1M5i*$)9vUd_cmS0UDBZX~@ySKm4`}X;2ST@;62@g7g-9TqL;?fAZv}V<2o^cq
zdy`1U>=*sk*~|17(W;zSP#~zXc2NtqKm5P}>twzT{dRN7nBcbKji@N-}W%TKZyT+|F-}B(n%#v2hOSf`%)Y6
z-)B1gH*lBu@7X(4|9zbJ?{qncJ*fEa0QR8jzh~|EH~e=JWfgX8v|c)?`tM6E^@?5-
z-Ce(D5cCse_yh?UGxQ&QyyH=sP9=Z+BmQ#`N>
zm+wTxKkP)rHLXMA{sAJs?tRDvyCdTNCLTEZ2*Cp%{CPZlRNue+93Eb;;^7^bAZ5ii
zHtaSkxQd-q;Rr1vu@~;d1nulI-JU874{HmUIKwp3P2zyB}fVcolOG766G^7y{8Z_w4;>2kfoDyhGpDV8qPmE?u|~b_W1)%sb?!
zVecR(uilh2sEA6E?Hk*1KL*ZY5tK=hYw(0{CJ-p8KlP81AI#Q1`9DN{gi@jJzWEU$
zcOX9m^--jo`p0NI?ENND?thNQ1FqJA$A>0mTexQ-7h0;|@ixHY3vT1_8JkAk&PxD~
z&*?<@2_7%%j6~l;llr>Bj<3Cq$4}kYg~zjW#XrU4>99&g|3?34PwKzJb={DRA5H-hLM;PLm+3=Uy_ipSd+1&Hb{5Niw7s2H
zB*Q#=FR=!f0Ef?jbI-(D?o=@O`j5L~@@q1M?VYIn`n?(5Pq6wHe)T6C}92%w+xEJ=Af=U2G>9N*tU$5WO%9
z`nq5A`5?-IS>$kD$d0Y82)kHja?ap-GD5SdZ!SLJ(ct@7odlf<rX3oNop2jYD9bw{u)0
zp6pyiao?9Ea;66H@l+ZJSUYiv!tU@%#g5_y(N3Pd_*Xk8KEq_!qry
zKAGExNZXjrfG$69kVv!ya!ztpsh|N)mrJRDgxT49IF|v53m2h`Q39Z&Fj63lM4bo}
zMk!-0gt16&h5E2Bc3`iR<)JOFr|^u&sGP8Xy-1=cEkDV0yqF=+2Ika>&m|Tn+W+3UU6OH)*In8
zPZ%Zc3P&sTxr`f5`_?!?t9qxEWsIsU+m`j=jX|t1YNuNmwXtRpyDcjR)`UFI9|g8U
zm*(sP83ANhy>YJw9hBT6XVA&_92+(?AS|$mtaFBW1_S(Byor51ccbk~XFL756KCqt
z{GxF5gupg0NzWKXdR^eAEE%JwyX8Xq{Cf8JopL69zP=1>BGQwc%5c~ZSqASak<%5u
zm7U7|=V7N3vW@do(ev&M^W5N~*B-QxYx6@}EtF+$@Pr43+KUD4#&W~l>d*n=B0$et
zTYBg37ui;SP*vI#Y70$sP}=8jZ3djuXuE1
z_A!pF-*K%6{UXb><5V95XPq_M?7JP>Eeyzc9uu{V^~)DM?Swz8o!`Hm$Hu$%!Y+*g
zbUnr)zZL4Ykx^NJey_K$U4FsfUy^RCA|>LYIP_j`Z@WNO9{X|04gV|d<0jh%8reP)
zkoF_^J>_jQrQK$xwC@R&c1tDo1X{KY{i7T_U`twqUVALiya7ns$OS!=oofYU7^2dlm%@xT}s?iQP
z7|7WTU<+GeRSyQnwN9MMF|`T2y$bdU-5RO1R5Jq3lkIkK`34jfeLaxQSd#w8EAe2R
zj1l(J8@?VGue)0SV4n5w2~^8`GaM!y|ZVk~z3_F!ZZ
z@s75X11N0~v56(dsIY5DEhSoN13yOf={#}C9N~Oy@X*X+rMD5;rP)EU+K#k(Ch3at
zh&|a}GCE;&v~V;Gh;nXrNO|j3=EB
z9PFau=P4s|nOjXK@?eSDo(Nj@dZXL1c(Lg4`GQTWOwzno#N$@9cO`kF6c^6xiNkA|
z38v#eezJOAAnsqQ3pTGZ|ESGMcye#8W`gH~*Ps{ylZ;|`q^bT4MRqsu7IW6B;dy|xtcVty-
zy`!nn4M#DeSj7H|a9=as`#!(x*F$Y$AVH|4tApp*2
z_`s5Lv{(7-fxqx}a4&{YXSwG)@E|ulOq>>cTNd~>?bRkRORo;xF#w4(Qx4Y;p82-)Ymj5fv*u*GI!)$cAw3#b;M1-xU4
zOQ4HgEmssB>1+{p0`_U;u-03b+`IsX$2+WcjAI9(>$*qxQ@Vf##~j2RY`sl`&=|5G
z{3#2+-~Y@J@KPdcKz)wbs#^RUoV0z<>21$A9Pdc5t50UPE=eC*fc1Lt7wLEFGFtn$37loj7~E;ppWfOZL&fi?LIqGm>67eQ_C_9@4lPXn4od
z{-Mp&1L5;6h;t2rbFtxxu`Z26Q^5h_sK>FrF$^Lt&E8D>XCE^|$QTRfl}3y73hkgo
zPT#D-2l9L2WIl+T4B{PjiebUhE@#_lI_9)33H)HdCWkz(@K&ub;y~ZuMOwyX4L@@w
zMRPE|U<5p8;Jr;<+eRyHNF8xy22HQYlm}=dMaR7;{s
zDkC{#^loEJ(wd~e(Q}@%{J!+}(N7mV%}j3{J4HAm)IQZZZ8X?%p~sBVZ9Bz+htTB$
zJ5%ZsbJ(_^GD83A-lqW}>StYydZrN`Sv
z$F*C7tQh<5zcNE)Ly?%NYl}bFx{Mknj1~>QL}y)gmR}B;l=(ro&C?&jDF~Wd23Mai
zNY3&0eCo8#+5??hM)#1HHMT>HKb3x5*fTCm<$&nB*2b|DbQ#I=+l`l{#;vf2l}crN
zHE+7eZr5<^Kr|A#JP^sb*K{IVt$~x{h1U>m5!r_bhm#%x@1|=TY=szY5}ZEN;Jo54XF*u#gjZOS?&-HV7kz#D!V{M9?J;eGiUvELB1
zdriDUVC{kNr#G#!B^e;22yBxR#CFNyF|9Y_+Lnd+FNjNTo{@VoXQjXiCV6?l*$S)V
zxM_^9!kiwB%PO~y%fZLuDAU+ygoFc4%}uK|S|dlrWN*vF-^6J}HqFnu;*hHmq}Va!
z+-}#3#N&xgb-!}PWWOYA%Y^!QG4^ftWMLEJjqhGpTSBx}5f?N9&bhEJlvw0R)tYHm
zdAhe(i3Rwm;d8c{cs9-yyAGSZfl_vy$#9NFoG$6K==wF<;L1w;EHT->$qpycvPyu~
zI8!dWp<~>S9K}nwWn(%JI2aXi6Rot$OW6}{z&@lyanvjcBvXf%U3&(kQYX8v)w%?b
zR$+GTbKyvD
z()e}w>7w6>i`r1megklUV?D=mLH|0b1fEs@pZH^Xa{AVJ>x}3MwBn3_}#UCeUO?cl$)MglYka|46*0ymh
zL@Z6isx8IKFhxgeHw94}CJ(0rm_Vkfxp&zvbR0$750ep$bu)|i6*~?u-IR@W^u2?ft$6v+BXGvyYdp3n>?oXdWe2$8$kWYng^6D$
zW{eq`6MxjrHa`{zxiEkI9Gr=P6I;yr0g={$e~V*_82lWoH9&tH%Pv_tEjaPX#23I8
z#aAalua9}>jarg|rxy*2W4ANA;jM4hM5H<4NPKmZapuS+DMY^Kz}eNN>TkbQ
zEE`?PSc*GJCd@c$edu$$Ip(NZWBWrZryRAG?vtl9U$mR!70yLy$vVpe>GOs~WHy`U
z+hSN`d(aB^5t{IQd)4t`I>vvnWBdm%tK&bQ(h>YX`Hp8S9kTgy@iIA_K4-V4xlapo
z$SA|A--NPYQuaKYKhso?Jo3$_E~~=tFtQp~%;Y@AeP0~44m}!^lix_R??Y$t^3glb
zS`)@f_D19LpMs3-g*WSrw1o%kU?jx0BafIr-R3A>zGDyW6%Zo8xi;91S+4t&x{_@F
zJ65u6;GP#wXCzN6A>Jh56IhvByH|Cs3L4aXRTfvNt5UX|oX6vRrGQfuy*UqT7=F=r
zk8%z%{|00ga_-G$kdnn>rq7=?EpLw;6m)HrK)a=)5jX+
z%%F-kI4|rD5Pd;Z{DBOQ2+|dQAlb3WVfYGcLyu+g6uj9o5ak`wM)yFr=*QuAJ@yI-
zhk;*zoivL4k_h;PZw49%^^n&E-NHHsjm+Mgxxp%UIBybQV1SB&6s~sSr<)O+(L2`q
zjK~Iu
zf;51KNI2luH7^GGH%Y#aLF-)KfkdRgZ^!`qCF+~sgPTp*}YW$sxfQt(z(s|Wv`s}f)IZMxK~uyv#AIT
z+-8rl9}!*vem~Z7)LJs7cqzeRuUNNbw>VEa^JTTq)L)ZzX{s*Ek*CqS?N&nF;2nT}
zHUH`dwT3lTt?}+M*+jRiWsXNk8Huo(sy}L%pDrpr>0W6amsJQ}!cYs6$;`RuPvM~5
z5!(~QHx|H2b=ekpcs1;R-t39lz;jU%FDQ}Q+~&FG)E*lj>YSS@Uvrzk%}TIx_P!9m
z$GAowEDjtl>PJ|&rpTjwSrt|y;gTc8q(mKF5_Nc_-nZpd)&Q57etW|;YmSP(Y9>L40AZjSo$0m=?U5`@PAsT2dZ{CeQLfH
zH>PL}&@0C_`bAd^+U;7KxZAbFQD7}i0z2*(9dU_ihUn2ZmLFxmSuWnlMu(Tm83Cu=
z0T5waSdF0X>uw!N7Y|$m8&c^e@^_&udUR>hmt|yRr}s(<#O`A|qgSYZoO8t@mok$f
z6T0FC*lD<_&Sw18aao#!bDO`YR5|Ynb6G&T>{Vrji7OJ0Cw!eaA}99f?&U!x>g=2c
zj#|`HpOWt!x=?{L8vB6g3VGC6cv}d~2&4JP)v-bp+$w)%qO*q62VDPN!+ep%zFmA^2Ak_`c^qU!+KbG56coaVb`
z8#0E)Kuy7Efd6|3YMLJ8grd#J}
z^%p9|ZU*9!3$5r&o5*ZuB=`*^-rz%W@P%{aIUv_r*BHVd>Dt4TJ0KXcu1%{q?ja@c
z+%MgDnA*FV#ENZ(wx*T)arfAQofU>+2`)#DX`By83+DUl_^4|O_=j*Q|S996r
z2Ea512Ov@x;*R6dN1575N2Yuh*#J4gauPEYXAaG5TCw7hhb~168^DLmt$Sj~#t0(g
zj?Iq0KcU+gF@H!fI_7FDnjdUH>%LH>KlP%P*wkVxVsvymX*tPWYj0W+JUrmS?Qhjz
ze2T3_$TkGtlLKBC?kA`1pP(}%$cg)T$!C*CJWEd6tI<9E7o4I)5dY73B4lI4$+E~N
zOD1%$H+R^C>37aao$-%mRrjvHYgWS^=$uvWV_mZv^6fvG75mN4&uV*A_gT%|_V3SX
z<2&lCR!sayvuYj>C}LHyZJWbz3@o0O%O?m&e6GOqdKr;7?#1g_NG{N~kAywXY7N$(
z@5w<%i+i8fxqE|+`@-+1l6F>@tg*1e)6i48(xlB8MVSXD){o;)H)%Om--ch4VFj-L
zfX`pnacto&{Ipkx_vv+QQ}J`#5Y}vCgi$ZED*U!y)3aiPg3HPW
z&fa_l>PKjzie&Vb@M10bU8c8$N;errnFowQCk-wuc7EelM(TH7!Fo6vP=H0gAgtSr
zOyh%~z5%Y;Y`LXx8R3+I62Nm==WQP}e!Ycq(^l+g0Gf;%jJ;^=PO^{Ov_15BKxC~0
z%3+t20%XIAd$s~X0(H)N6zxzoCx4Gx`;j^SPVLnleNV>SYjYH}E$WvU6Qb@nO^kYA
z{rIS%eI`W3;<=;0HiA}7Mm%dCk}LthyW^~S@q@lnw`#&bGqk`_?vwnd_Y
z-Lb)yHheN3Qvp&G;Ld^cF0(SpR5bk4he!juK{KX?=LX5J;}TYZEF*=zv#NR
zeF#s5AoLQ6ij1V(u_JB%26)3vyDck`r=CSL?w4naD4(dkKVzZ|c&>ernrM5le1bM6
zV}dQlG(r0dYJ%+-<>R%$YuhhPkAroZ1Q<1;W=fsL799lg#-MR7f;tRZ
z7POx{5tyimZ{W?1sK`r5=qZn@yLC~3(=x_=p|ehEJ-RzMFX-ff?B5?Mvqg^uY&9z4
z65u?oe$w(MHG4u`1AFn;Znd|%U^$S!tj>+hf3?S!@;TsMtWLJGO1a9H)$-g36mTbR
zx_vvDipU$Lmour+YmIq2Iv^{tDdOdaY?}}G$$HCSzxJms;#kLywv}o4#
zvKI-br|sciYoF@O%W@4$<$=IZIL4LARjO)JX@P+GlNcsfgYo_g}gn50!-d+`H0BQ
zhJq-4>A@hYb{hk
zXTJeeB0X55!9kfiCpftCZ>3BdbfrOF5}pY?Rf~it*J)_5P@msfD}b%)UP~TdcdN7i&Jn9e%YErxouy=)
zRf*He#7hHVZb7yTe&(E%J1$wXa*@
zPbj;A@C^3$IkEFoph{%73Bo>6QV=$`Ax&>M%;dqSe!{H
z6Ot#Ec2J^>xH*H2MQT}LCAVb~JC~CzsH+vuu2Dy>f|2X~q*D6HZlFpp_hSo{zLoVS
zG8-{pUD+W0w#u<*~%K?n_gsfOU;ZFQ5kOuh|XMMYes)
z|M62w9?)YY>8pI~w#>?1stqKztm-3T1Hqp82BNhUvW`t6+OuzZ*9eOJ`>4D9tJ-#_
z{j2*U*gtq%f!M!@@rwOZEKN82_tDSUzq;Q4#QrII+GYQU4FH+_sJs0G8X2&44)#zf
z*jd#sudN{Kq}o2u_DEMo@__wK5p|ErJtvE*rBgXa{9&i1Q*9ivZ^XJ0yBB0tt($EV
zy9+!BL~g{YJwx)f24#gndsigZ+MjU{D+V^nL@d}8n;cNH9PAcqUQBEOoGc?U0Cfu$
zX&^e^X&qA$U}|UJx!`bj)JY_ipN8KK-kY!8oKZbV(6~r@(n_#s--GiV`WprU-hgDQ~ng5;An{uBQv`(RjaCL2>w6w!cDc?A6
zj1fQU1N)aANi-IAl_u1^D&N~-_mn!HG2IOZ>L=EX
zlzO(!Mb!^0cQ9YY0!2jJJHVt$--d#<737%}`c$JtdJeRKnjHIsU!<#IS0&>1df*M`
zh=boT`3}xo5NRQL$n~g=g>vwSWR%YKDz&#GPUxxg-qSG#Sq;#i*QoK*QV+ZnTcj*8fW&V>x-ZdqC5|
zfbl26ng!`G!!Cq!-|RBnzqi6;B6AS2eg{uq7JH+YaflDB&AwsKPG~?N(d!!K2@ISJ
z?mf|s^O$)GZ={q;rILB6b
z(=Rd;7;f23Kj*mR$Mzb?gC^+Yf*MQby1rnaBou;gshinZQkZyZ>F(vw3xzrMcvN~I
zg8P{wgN$v9aEKSpMJwRsi7HvL$i7V4by_~y9fim(kKLOi_hMty{!CVkqkEKcOpinH
z1@ZYAmZKy-f0mTl)#ve(I5NU$zvG);;iU$UCi1=U5)v2{V}hk(v?1?it||*04{LvDDR(1@1h5}DZGiUc`=XxpibrbsYpqe`wC8(Oz>SKAyLT;hw`a3Zzk(mMFvsn#j$
zEz>^*T=w18C)ZgPNYHn%OtW8ijYxX5ZdW4;rBsnpB02KAYU9eIjcbz$abEbP-d>I?SoeQq)#K=JViyNe~5%2qJOtzm@rlQ
z()xq`-Q;|M!9lZ6oINwqP@xh~@?aM=uSGKH+W673BtgI;HXOh(8C-xal-yL$86ax3uk1?_|Z
z`@ex)D^O2;CEmR0yQJh|R)tqT+nZHR@cq3;t)jBvbooDtRfrx?k3*~yJnRuT
z-<{n(R?#Z4iWai6v@l6Xg?vnjRkAihtnxX;Ds+!-nHUT24k{TKyf^Swr_8NLoZ&d7
zWL!fr%N0D7JzqN_{
zGBs)-HVbmxDZen{A6nnaQ?v-qCH=ncO?ge=l`j5tZ`+v}sclJSB+v3Gwq2!za~l-S
zIuzOK$Yd1>R{Hyh-bAkIY8NKzRjQP_MA{r3SyN}7sG?NJsk?NSl&jGSRIEa+ofKrLvj$pBa|-uQ3zPp;`|NtA0-l#IQRnxPAm&FS$mJsH<|w^F-7Y&+
znAq79i7mTEh4`JJXJ+k>TIuapDuxY#^Hv~vAoEd0bEq}K3yxYl4fd-kqIzDj0H?oR
z#&ahBdD~jp4S+}+C{W}=Ud1XDt81mK4tTF1eIDeswhul20sG}3?J&G52>7u05NM^Q
zDY!YXc&QvftNEwOiK6LLR$?a~;8&Rc?CtiH&=#BDL0iO5io7X7GIy{QV5{Nxxe+;K
z*h+ry_mkCUf!`HV><<-5@J_|!BysA5X7ST6WdnQ$;cbk%qI$5R0j(
z2zkmm`k|=wQwa9rZ|+{2R@TX1kTr#CWWL0
zm7hZoh;0AiFYqbpq?>qrMoV;Rgs{Q227EqbC=oLgW9+hyCLT@E7*%@6OuFco0&74b
zK13VdnZ2j89?1XO1dHm_QI(b-tvjvNsq60Fs;>LYKf<~P(ZiHpl(|JI>u#$B+zc!+
ztoyC1$gZbcK{OhX4``_9h1F5logk*Qf)-HWasP|CcaLl8%KFC7NpcdxMZute#a4-e
zG7fD`wNsywCJKolUg`*_)oMKzTc@qH&$Leaj3bbo#BdR9RJ65Iv=uAUddncKt=!}y
zctc0QTD8<8ptcrt1Vjbi?>dKg>Ads2zdwJUeyB;#KKr`X+H0@9)^}}G;x2Sp2LG7)
zPb5Kg!XT9T5;ByeCfSX3YX)KsDKf{8ajRc4ffmf5g?>INT62DW9lS80=|5E0uuC_E
zL}{%ZSVPZR(|XE!5?R&Wn&6oQkIjq9(tJ(*&h7n@$t4Viyt$bnt*=D)y^Z|k#kBs7
z@)|RvLw;P=_{k46tB^lGP<bKBFFD)@%ompo7Xra+*%`e6g)PUEVh
zbiQaE>i?Lv@>;Jh6Mv4Md$G$&a+&Hh@#_!G(E({_z%cbh$R$&sq;w4oXNXf5273A-
zb1Jb=C-bW+$dDR>g~r-kZ~_Gy~qzWv~pdewvdfXaJz1LnR&?i(B4k>|Z{lxmKV<^S?;
z-%IBGn}$lGnbg=Jk7P!FQOTu?N}u#)jZgN_JUBp|eHxOi4QzOp!H%{{qDP!zybe+S
zTklEq3r(kcMerog4&il(ey!eZ$By9kTMWAusOqjMWzHb}PxTmA&K+q@r1_`uP&>54
zJv1W!wm(btcmDhQ1WNORb7b3-mmkde^!5jJK0N0Z%tYUu`|tU0s&h9q7|)#3(?{og
zfsN{+o@|)}Eu7hbc9x+R4}SAP)Q*4ktZM9vAJXpODyhWUc?6*9$U0Aq(%9
z!Z>BAOR~ezPnNR6e(6`(F^Fqe^G-9#6XLr52k41Lnty}3-Kf(%bC>QJT;9X)<|g7k
zPH6fOdPeE32+VJ$a)i%)p38#PS@(*kwX8|dLefe1Af9?YH`{V<3w$pwO0`QPRmwL1
z$2-qMmR#_(DzCpRr(E*-FQApxJXrtp9(s`1UoI=Jzol>e6KVY$OU|yOvF|2b+%x9}
zcn69bTW*36daae+kWDj%?jf)^&Vy9gL6REp&`ICkBHfvd$?da;HMaiytr^gLzHi)@
z&Chvo$M&XFp7#NOV+5?(YQbAR3({Si82Vy&Jv5sW7i10?y5O}l(s$`}Ew8^s+Yip`
zSO4YjcXlNa`Wsr5q>@G&Q#DKb
z8_|nJ`i|Qi=BWjq@3I7zeJ^|A6q8%QJ)GH#l{nj;Lyfj
zGT2EppQ}<$0Yn2gV417lTlNv{W;6!x4eyrx{E%CRw1?l6@a#wqjPmlXA~?=Sup@L-)nF5!@$JGf_a_jj>sX=e@q)!_R#{
z`<}ZTSTA<{U#R~vnfhD5l&RnNl}<56-~bGUy%&YDD!D-
z8jNSlq@V}}YZ5V(&uGC(AM1}kub)KL51e=ZKps(2SxLIAofKF;8@@!X+oT&=dA>9H
z>?t1_97`E%EMh#V?!7B@+j2<`=p}76^)XK^Br(Oul=mPj)~CgTI`3PLX$11EW22-=
zTCjFRZzSudm+>~-0XMd;#h+vY)Zpo+Npe3Mx2b7-3sy^YHU8k}{uAO{
zBuiHDdj9e(c3EA?jfeHUMzy&4!=7bz3)-?K?aIb3Z>3skHfZkXGtHZPt5JDvkRkR}j{JyLFwRtKD(
z|L=WX)%;MO{rCKj+~+5nq+0v@2{4A{pn=f!x!CEg{%jpy=oR^X>N7GApjR6{c6ylzL^1L;8qg#_=bUH$7M4yy<>8W#;A3vV^HR9fO)@(ans&TdB4@V!h*Ka$Wf9l-fi&fW3-@G`+*;+dNU&=3h;Q_ppf%RW$
zwTxzz@twWUi9T+a+?AyB`aR>e+f6Qn4_Yl=j3HaiPR!!G#Ehbz+=H+HXZvOSl53?K
zmmE!))#A&rQ`i{!mrJ&^Bi8CbMo`J$+wUg9n>rl2(6XC|kn!jI;U8wS!gI!;TyJze
zrkA3-&=MDJ<5P?L^?6$uKFBA~t+AQ9gFc3Jjj!)u1P5a7k9YKpiN!AFADQV=#UjT}
zmXVvDznYzzW;XO+VA5d~td?87uKxJTnhfu8i;haRz0Cli{bY
zcvcw^$MC0r3U>RfF!8nj^@KH|h5^EatzkS6Ce}3k9+<}24dcfkZbqkKxK`#ZpK=TB
z8gY3v?zAZ(r=_tYs*T1?a{z>#^+jz~3p@)rc=p+fMpH~8?<@**c>!;CGUl>U!@L~3
z&E|5n6Fy6S@%8qft<}MZp$lfp24ZA*-ZXj6bsl)hZsY=`dEE7p=;w3I@Jt?SP^B7Q
z+Z3YOKO;;CpS5w8dQL}NN_>61dCLAN;RzcP)KhQHUkn~_J6c(>*>OEupjCUn-hBG6
zr^eMqA8#$qslRDSPx@fNw%KDA&`jgBcrDt7`MXk9=yI%vRpKl#Cz@9WOfAkzGn)=7
zD=`*9(<`XljxTY8r(q_XbmfjFi+zD`eM#mt1UKW#GxX2<{HY3jL
zl4a}n%19qJ-_f0<3ylQr+1RJ^)@k&+G(CK0b?~N1qIW|Nr`dD}w_eIygI!%+tWM>x
z5OcI`;aij=j`p@PYoWa&FAie$#93o+SR;H`enuP4$5U7ul}?=rEJb+y|93}dz7RZ-
zqNM+-A^FtQql`fI3Oo}RcOWWpiRt4YLZZM-z*kE>*x<-DY90EKKY^=qgRS5L!H2J1
zp`rHQJLp<5nh`TJSGE}4OYQ+1G`p8(eoi4fIqu+?Sc9#`hzKWpE3@b6$V_);rjfWe
z@oR%HizQ5r0vjyU*xxxu%;bt?+2Q%+dKZ`NdTa!9qgd<9PJLm&%u`Q!XX|B-;=XbD
z3T*!BH1lu2<`Om>Y?jy4J2Go~p^LlRORKw3>z5!7;4V)%2&~&F%fG&4!QE!nDT_`u
zRK4ktV9}4f%WNr?>7;V6xZ%A@F}f)
zO{H^Ka2qXX=H^l@f_WD3PkHV#BgWpjA{0t~&#Iw{?jZ5wXB%7%b3j|g>$e!W7(?JQ
z>`DoHQl|=3?EPk6jCI5mU=j(O-!NLWf-DzzgmG$g8zY#fxz;_O95@FVS~$$Q!Y20h_6-dtgri@`2g`uGQ7O#kN3`ewV68
zSv`p1Sxulh$Gkc%Hfc=(Vwqdq~QN_h2_tG?Ty&h
z_tdPe|KVPJlvmG(>F?uBWpz0E=T{9`BXRnT27%+0{M3J_l@VUd0L?*Q%j$>T#<`Np
zz1GWXl)n5sS6JM;UMT9vuT*QtILaLl?TvSD_qgoA7+o*}@3@X;-+i$A6W55{w|mI<
zadQjrH%M#Uak%$JaQF9bBaiybxbnC$@dINC@lgD;x|4dxT9zZHOI(o~xwMo~UQ7mO
z$Z#9W9oAhI+9B9x+
zm{ukmk|Q7w^t*2L90U^6S_RK_Dju{RAhrH>3@9+~HuGqooa(@`VMT6-mx;KLD;XB+
z<_eA0a4$x;VFY}{(Sq_*^zA4#1OqbZCg!;7w@dw6e@JX@=@pl$uM5bowCt&cZ|gX&
ze|oA;NIU8IKhQ1}rhwd7vQvyWJ4PV%t1-6LJ-rP9*JWRPp&nRQlHYdU_cQ6Ka`~py
zVM6Pk1!rEqkPA)EC2Zd#eLwy385XEr%1Ra`vnyp>j4+|^os;B${lqCx?c3`ft$q6m
zPwm_Zs%_N?PwkZj()Z(X?H-+O`vA|U#lh54csZeW9k5wtn1gh|a6z#N
z^(r2&cbr46HziLn%g@CDsClT0p|+{^Ev0e~sAuU8=P}+}t>ClN&{NdRmNF$)fN-RM
zq7m>qkP-N_Uq2yFbwW2_V=t5t4*YwG-9>+i_4G5oG}5-qw&9R&!*Hem=Yk=X!KO`z
zBrP(WlltJn4AZIo73*SK*K*2ND+(Mhcd@a@inusK$Y#vS9L8HM#UigA!7e@%Q>Gt2
zf_&!hFR|W;JlZsAQ(4v_k`>{#wm1_Xc9b&KsgKXBh;kM<$JunNW7)LHD|J?I
zZ-AHJL6XS?its~-?X^@ib6CyK)98-oPCkR&q2`NQe
z?|JeH$!Y738kO8{{m`q>OCngRcc$~cn!y-S!wBog#0tXu#B9?1R
zvCmSDjGPd07`IJ>&u#QMfctkTb>WE+ps|0K4A=*7$8#QcMIve|S6_DHdZ$PO|CL5oh?R#T$vtZ@8w3fcw
zP_NTUHEFr_I~R)9;q$Xh0M~WrdeK&V#$7sh)aS+MEsA>uQ^5>rF*>7g|;ul3P-YT_)S_4m5ul@8CKd13#DB+!Axt
zXt0f9-8&pi@rEy-<~c5q&WEnx;mn7dK6LOabS!E8>onr^ARwLq%m49FjB8B{>)J4i
znfSMk4g7x}?(cHUVgsi0ZSDRhKN;IX80Lj!vcZ
zvx&?)#X7a2tAaV6`?p+|3+=Ut*ljNLC>xr4f&ZiFRK_ENj_VJo|I&V`{!NEy1meqw
z+xgg3=DEC;f!Yes4t&$d)I7*HMSN|@*0ga9A0f4RR*77
ze82uZAuvo6hK%J|t;!=KINPIABGUQZEswQ4>z*^%1Nrb0T_^gr@QH
zkLkQ{4u0t=c7rxUYtW2k%N>21&&Mr2dqbveT00rCkJbJ6E!JBd4Qw5y8a$wI3yY2A
z(3w3piY3q=9<@E(599&BQM}aLyM;v_I%a
z#m+B;+{W1vNPNq$AX2BgSD9bkyFBPdkhr?4$GyJ_5odKq
z-Qt1ROVd-g#0AI8dt`j6x{7Ac;B3KNf6D;Zpa|w9r_-2Ox8n@(eNbO_yFb-Mb>0YC
z9wd6z_wY;W`yDmD{5#%{^H=UtvDPpZds5|kJPKKGW7rIZtA8w8_NqR71e^c2@(=!+
z6K+kjbO#d$Sw~L!N0ZEp?v6p=N1B%(dIFSX4)K-Q
z_uN9d@ymgUDrXw}jxVPJeP{&p*W7@~d{a6jaJo$+nDX`IpYUy`xw2RPx;kIz4&G!6
z@LIl{73T+Z^3{+he4*&0#ZyYlhn
zK}|o9WIY-JFa+YZ*`jU3io_|}9yX4}9@E;ktc$CWWo&2-S*ARt<+W>mMxy26
z^4i6Yg~!CJ@)NUxo($E?PqrIchvub7akJS)n$mkfH%#1v%plPMEDo?$oD_~(5FySK
zX&~#)6d4i!=cw%Ig6&7Jh{v1n6=|4McS8$ue#lygDlY7(4rj;=)wcEVhm|`kdMSf$
zys*ouJ{~ZJ^l!Ijhf$x`#q6}`GAercx*h7of&9uCrFDm`cSwy}y~Ai|XkZK>I~l`k
zR~en%*842ttPM-90!wrUJSQt)QICPWt{yp-p36(KJpH5R`NMlM=wwVP;tI
z6wWp7K@G^mYe?R~%sM>2%J5tx!)b$$>PHS|x0bqWr@t*;k4QbGe&~nb>2_&;5RWT7
zoc}5oqj{AX_7pUk!}}~;+`Pjss&Sy?&RS;)%!GTT?%|{UBQx_4JhHOCnZdhKRb>ylVT=C!wLbsqO~WwSB3zeB}Cgpv`sV}Eg|{pkcBWe
z7iU_BW_t8yoZeY_4xLlt61hxZeD}Z&&_G>~AsOlnu6Sd?2L48aA`*C>wATl~UQ2kM
z4X~nAdF18>enlZP9eotnBfe1xRI}hXU45d_rH1sLUkz(=1W@Go+Z_reti(5hR(>yO
zS3%+URZMK|>2|iCTsw)2H6-t6+yh}l_Sp~1FP#hSTd7lpNmd}exipPjwp`{;K=9O-aiF
zGNt-B`~N6SH9uUwa`=C){ki2~=i|@LJe_oEZr!*H^~LaW)9PP3zUXL5?b5?tM11ri<^Z@cCFtS^(ga=tF%
zUT<0)@8#`X2DITjfu}NE^Y55mvj1XVDqIp;Q+GS*b3xW6!X$a?hf|SjcCBU+-<^gC
z@5ScsBtk9Y|NJk^-mSa*8y#wwWBon;q(#g7okbqQuYjgIkmdilOTlY*c^h)RRB)3G
zj(3!n&MwL_;4A~+S0QXWroEU9t67BeT;?fZytO;_KmCa
zT_(iBFY8nUL1O4MOCBd(P(~?Pw*+!h8NE>-Sjn6>Z8GWVHLNR9!|MH;7=1t?qaV=D
z=yjEdrQTd+O%|A!SHR*G*bd!AAIRYe{s!PL0Dt}*N;TDAE$QQr>a0n1lQvn-TYSrA
zlm%DLtK6D#wf>zFdT&n2k1KTWC({Qup$@cwccnT|*Vc?Pr{-YKA@ql^)57Ef$nMOi
z4&q!6(|2@#YyI59Y_e>bGVbW$D)Zs-wb94_#LQ#79XJm^t}sX13hW86PCostXTKon
z>$01^yMa2xPRG~HJepKH_wYEU8aZL79j9!tDdkZak(v84JUp@A@xSmys>~C(Wm$8}
zoA=TxzzM!x16=dEO!4++`^v=b#MZZ-|1{oSkh#lw|NGf^d*m9wJZYV?Zw-)VXi2#h
zp1;p@!9rFKo&`4^x-!s0ZeLB&^iDf+N4RF#~8YgY=BA7EcdxEDa9SYFgU
zyS?ZUjEk6td;AGdi%ltGT-5S^^J09
z>bzgO&^@cEC@?;B;^rzI8PN$DoOf(ggr3i~=-J`iyt6vBO65`yR|%GV#@Xln&jyyx
zD}A`0?jTMR3SX3|(B}wKIctu(>fzof~s!l2AGrZL?lXhi|$?%;tF0;Tn
z-j?Ka`Dj%9jagiZ5N>bHTlQ(FF?crBnx7k58lQClc7XgX2JL3!(?@vK3bysF!lyhv
z+Ih%#Ua`%$R1_n+7$+w
z(T_Iax8)%y7lPkI^ig|*n8yfB1lS>&gd(#4e?<_{`NCs6?D7?gcQXDSzG{vRi#}4-
zoHm7x(?{Xon6#-u8Q@#*!N1Xuyw&Vh!zZUojh*FKGa?Ux2hyOR8&1|th`2L2ofq&x
zIN*Ue`tU$}LxHQ?q>%M%%a;%EKvJ^E3(A8BqJ+P{)r^Qn?|NU}=>vozXbXZj18>U4
zA5wL!stHIRgWnW@^)VP&AA^DQF&J1MA;9_w0oF$dus%Y7^$`rLk6>VZ1Ow|M7+4=c
z^J$hTxL~tHDQ0n#d0{Mz+r+mL1C$ZR
zl=_i=3O#)N#QqwyG9nvis_RnRgQvDLca-po;CyLDfu-@Y__5E;bwv+axQ`2hQi7_l
z9PmJXERotv=VEjk^iybJsLg?hR(+^VrDme1&6Lt5QZM#}ex5$k-=eiNQC3>}w76Un>HNw_H5nJBOrS;t*(zjOX<>n*Sh?r(W
z)*UL*>`EGK6uUc&>!kQ%HbH!;@%Q2szs}D#L9+RC|OzhI;6O
z)(_|vmp#6UGjrwB2y!%E(s}u*hJB8R4tOilP4WF_-kL^gTTsb9jD#K`weH{s^VuA@
zKp(DZky~H9P&pFo_v;=gG{M$z;))B*{305QHesbSCYjcjY$RIS+DB_Id_yI2i-0rb
zsD6c>?Cg8;GEJ+!QnF0N7&Dua
zCHfiJnoJ*2d}E
zyOZfD>@>dZ?^0RtR*=WH`n(*coAqZf9V89udRhp
zVzf+aE{k0RZ%GjYENb^9=TEB1QHN7wWAdz@ZGXwE=p^wPEFwjNh<;%$S_B;5;
zd?2sx2^VmcIqp@G2G(Z#axC2
zb@JYcJdKt16_R^a$UVZ>=%&^4-4D5Up-=7+!UoAb+m(mqp6yEO+FoD;=`^-0v{siS
zxz|5a!q-^M`<$7_hjQ=hhhkT^++XX_L}!<=)(gH+V(!U?g6N@sY8yl&1Et6>XM<=V-5qkb-T4gOuz
zFTvH{PX)>MDE`Dk5x2{p_;$44GRndyb%L@~E$-W}e=(mkoD|>K7u`Ouv7a2>4jTSY
zi|BSQe{D6t*!K@SyZT@F#_GcZTlmM}WgK47f|0ebW?Bb51D*g+r{`Kp!j8n=;>3>H
z34A>rvTk**hL@z~bzSFVMpSD?E3xBJTzci_)FX-?e^-h|r`_DsvyXva;k8hwMm+lC
z)g8Ky+lWMWy{eu;Wp>gtud)Ah-M-y9q2$pzhDp*`GTGz7G
z;=1BBlezApptNHM+-N?hU5U{Qy#)zz8GCmis0Wf@;hDc!pHwv~p9BwJ
zY_yBWv%c#Yc@^@9(uzE?ul3V}d-k=&gEV5VLxSJ&4B}~n*J_i&7hW{$Q?k~5O~3FT
zYF=@9bP#AK$}e!%_E!InSNoou25gyC-xsXr72H##UwUM$e&`p7XXIaQP?=KnVV^bY
zhhJ_+tnZTgD2jzDOHYzweD&dwbd8^Uj`eC*f*!4qRFW<;TA%lKM*qS0h*ytb>ZSNy
zXe@blwn|v)IF9&TXccWI_QL~!<;L+V$3Cqb;fpLh|3GaepIS#$H1kUCDe6P_7oyHr
zMcNaMa-BD_f-KdKzTC`vX^umND1fnk0y0F&4M+PelGLb&9DxROs8b
z_e^k^&WlkFTaCSv}BrQY{RLH*F96nFZsYvCRVsCPm34Ha0Iw;W|GNjaPlib-p4<5SheBoW7~
zrk!s>o?ERkjkoi+lCD?^<|f2Jz&tHJ^di9tt&;*u5tT_0ZCYT1te-)pKgB&|heM
z4eB$@*Ck3I{9z7ReV8AkTcUwo2htjtj(mSL=hmuCJgeTTXVeTR7JgPC41YQCNyxQk
z&^)Ld_^${4Qwpt0eA3bp6
zs9u!b;+>C3v>o8`YF^c!S^0#Z#frBG8q#Bi?KdDxmJ9a?`_>Q6(lfru-k`}6d$~-n
zNkqYjoNE`oxD29O!O!c^{5`O0-{+0~0=#HWS|e>OyVldLix{xKTVrn{`V2D*L{5WM_C==FlU|
zvAty}dhjpeLa#KxMNx@}0!93%+{Y8wsDDa4=QZ4$@;g5
9o#OC3i7xW+7_!ZFx
za^sn4x8en&j@E_mJo&K1;(awS9(ur>l_*EVG)oa1jk_TTfp7E
z*C9IHAb#>&ipdlg*Ef^oAs#^#Ch!IH!-<+sG-3{+)7zTmzI~6FmHuC%&)D6?L7f?I
z>_H@HNYk5APZMPAowvdFIl|WD>FF8Bjt6H3$ZfNyr!Rl?i1g#@FaD|zlKjiTsf#-=
z%`M~~+J3k%^%VUnHaDN6nWf%8JiD!@;c|2qZ?t%37VF$5?O@CfX2L&6DndU!1w_m`
z;+Ch~)=@Fd9<8kZNl4Fh(#w{$m84}`F0JQ7+Vhq2i7v1cw7D!_IijLTp64fz>!Uuq
zj2O#0S|ug)27_;+JkQXkz$bUG8$r(F4_W|j_pe|kkLn|5LEFM_Q7Wtxe)px{m%+Pi
zDse2s&wKU{wEAp}O@iYT1GURpn7pFRrxqQ0U})Ne#v
zwdLeck4Uo78BW%*V8dx#^)vNWKHYg@(Zsax)=-Zhjz)V#Gs}|S;rh@8rQSH4nPPk&
z4W)6v=be?Fv**GM3`X?pk&O48{H7KOvE9YvvtWO>ys!_v!?sr`;UDpcreD{3M%kz7
zgCd&vAzW0pW&e6UxT~~pO;w$x-67zJQmc71&ck*_>x;O+bMm)v>09r2YOgUuIp!O4
z4c%0l@5W`jfTzH6h{>zy(=nhYCZNT
zymO$W2cd^y=%I94LwloN!Cu0>ZpBH6s1xmAPpN2D>Pc>S`11npS=FOG^SXQw$#&%<
zI|u9=v~vXdqRmxZPk)OD&Bj&mkEDGMJG95fg%cHQTsZL`>qFOoEysFww9c1k0yeQ<
zl~4OcF3)LXix|BpZn=saACS$BPn?p*=H!O*PJyffB;OatE+Ec+r0=WMk1Hi>z%kqd
z|HpmF>RrBJALUMketSvRF_QMdMl1B;pw3>{W+GgqH$vXD$oes&JO(4bQI!(>L@{E@
zd~c>NmhmE=?ftDwW4mf_XjqD0Tp29wAjE}@PpqZ26a&0^!2RE(nIU_&{HH#N-o9Cv
z)+0Ld+ts)_c^Pi!)MsG1Sy*tX1N9R(_(b8200ZwO-IdcT)sV&kgs$GaOVE7>o7|Ha_
ze1_jmt4GWEKy#Dy8$`N)L_Px2-NNzkTJj^DSpoT{;#1pI%26>&S4apm&EC4OGOEBf
zqQ>Ao0=jfOpjlrdldO)sBd;^}R*E(J+6W;Y>M`)Aermpm%c0HD!)J*U=3Qd3w@)fvdxU9e3R|*Si{a
zZ`H8OxK>w-1#^0f37+lhy48Q4k#bQ#cWCx({+}%m-S9lycf&*DBd=pQ^JRMKHX&a4
zZtTmr
z3GaCFh%p81cPNo5blVdeg<0~qKLIjLPFCu!OWVc5wd79uWk32?s#S;B&^HaTs_MeI(uOD=0o%54attQ
zr+G>RwEHS|Xc?LfMB4bbn|ZE*`OXY%Mz6rh6lvSJ3h^XZM`!>{V5#qHeconf9mN*o
zuArU4xprZ!Mvq%EHueFH5`~gCv#8eg*pRP9!QmNAs^XKrwQq~&MeWK*CXXFO~maKd_Jjt5A9OjXXlH?#VA)1D}tDv4I>Y4E`q-ogWG^#-m&oMEyz2^=Roe^CXd>n@@Yl#
zcmpSQ<-orI<78vUfK}=}Nc@2dbX*13n%cj^I^4+weS{s*=kIHCKZK1u5=Q5uhK*PNHz*oHO`>!RO=zt8aZIsOXp_XXMz
zsEre?%HcKey;LyzJk+ucwS0zJ@}E&w9IesJtN4HQl19>+y6h)V#=rGq5k)tR?oynR
z5p(>kMYR-}zR_B1EY&2ZMM0v?)b
zYNdY@Zl49&XHSZafvnF`t>v`fYtP<}3R4S|*ID%-+
zGeU{mhHIICiZJKPMe)Kh!VXbH-Rpq>U@{j4Ou5rDg`xxN;iwL!C^Rb90G)
zsFvAlA>Y--MKYbm=F8Mqx#mnBX!j7JfZXKeO#jLBIii6md*|m5f7_e)+;W|=Ofjzh
zLpw#gN1vm3_rX;_d>bXlyVLVD1;xfk**`>t6V>r($r%xHNjV}yrfqqCqcUCITofBG
z#I2lT{VbkQewM*>2l9th3gTgWy3++Ic9{ticp-vSd}LT!0N)s!T3k20*IM9>Y$o3K
z9!MynikU)~OKDOk-+YNg_Sdw1pbwh2j6i|G$q
zTsyp1`5PZb9O!fJfsf6pc)Ed~DJ+t1-=!VpryWf064-qmK@*}kC}TNhm{ZZ%5AQPq0f@?2&fYJRV5GRz*3yzq{>atm;wl)5wn9{D>XYlXAug`9bk)b!5n49h
zwzy>e@|ovTPL0plpY=PhKY4Ad$S&#Q^RWH>qIvwdO&M0@9ZOE*(
zdy!fBr7!dLB*Xx7`KBmW)X~Am`I&pvF3k)juk2O`7QWxDaHoa$x#jD!xA*d!)kDck
zOv}uR6RbjJz!&)D&>}O!Q3hp|oncarsL}=N_Z!1wHpZyqZq8XW_te~pFYbHsgL#Vi
zi-fRwFGK#|PBlw=FKr6H9(wzZ1cp!km&#yUVvIh{o3jx?=F7r1hI=!HljJ2lu3Bdd
zgwHQB_?5jqDQyb!upz7GHBcKeY{BB`!*B`imKCs7-enG!Sa)PG;txyi=`>GyL$VD0
zi9rPYjDf7@eX28U$~z^<0atPF8r7TEX@)u1htvo#d6eRxu9
z>GPlRoDj?p@@14?Ae!SZq0HLJ{DRWJvy&k&S#NdJMwi1TM|R(+4x~5>DXRO6772Ai
zit28z?x8piIjVaXMRl)L2O1nji0a;Sm|qWXLF@@{PjdM%3QjrrczdDC_f{`&^;Pq}
zzA6`D+}BCHIX_8=b#K|gl1H}t-aY2b(@qPG8Sint%~wsMC^QtUQsr%n}29?_fP_+ROjBox2w$@GmJThxw
z)1}yOA#IA^({E4e{)YSu3^s@HwZhYfcR4m(q7~{cME|x&X1#oYN|sG&ihg_2$#3L2
zy5U}@sVNMOdx7gtqPCyTBk%4rJ^Z^(OsJ{-`|hC7GLxi@o;QInRUIttZt)yG=x}YEqv^`hJsdPcZnbg{-T)wSIvCFYCiK2L_d&KK4Jvw_5i#xl&R4a-%
zgw$AfRN^d*zH*3QII{yWSljRWu#b~{*!yY{uQwsa&aG+a^Fc4(@bZP4qDWwW4+mh2JHmCUuUQ_-v^w~rht?<&v&*gT`I6s(&Eyly3}ixTVp3o)~VazQ*QR*
zj~8lP@M>|dd6u>JJMcG`vma&BKBA0Ae7oOFWYRWwo9){K^J(}JXFkjh$d
z+N~MHMjuhu!oyDOO&PT>RlhQKGRKX{2q_1yy3&P6aXgO?W-5y|TcRs(T0&x-)i<&0
zCbN;TJ;pa&DR*96I`7=P`1uFs{}z&i^ILl4xe_tqt4!-Na81SYIS*cH_nO!UHNLi`bI6k*U?QZ#!akn_w%0uVk$qSs2
zO~<3BgynPx`0H)U$w!~=#21sSIAvG0F~y|;jc?k@EN^D;|14rn@zCDhI&opUC2~zv4p0a{LGR1?wk3@r;KPPz+)4?|G})tfTzfnNv*$O_6EbN65dec4risg8m5qJD(}xuH5m=ImCM(o%FW-
z4(t^t>Y6Q-i*t?U98hnOm2~0m6ZXl!XQ|ETQg(8_Aq?394KlqrUcsiv79@pBhG>soP_*?b}hqXMei6Q2Cpax2Sfr7`@EPcQ$3&%{5o
zH-$j$`*vynch|;_w?rO``e-h!CIJ4NYh+L1t~2N7_$evXDUO-=-MS-_ajSo#h*i`6
zv!I3QhKbf4Q<&m%@qEW*gZEt{A8%a3_w$D5%J}M~vEr1*d5F}X)Hw?|VXH%H=G6?c
zG$)U*5m#%>Rmlg=atWy8P|M6P`!vTd*omnhIiEF~!;(y|cyf0aSK;)<6rXlELYd-I
zc8ft9ZlX-yh80(_PZZRRKg-4yUtAezpA#-vx5qJ{_``CHGY)tV1j1n>Yba!v!srZ7EeTXKQZkP*%rvLj4ljJJAX
zvfIzXj*B0ZygwJQxhBM(nUL%IbPKaN2Qh*`yBYUkw4MLM9cHHe7yP@Q-Pf15+u(i9
z=*~vo?j%03R6!U@$aG!WziuwpvA`*fw=nWF;er6qN!XT@o;)toV2?2I6HEUpKA|4m
zY~iQ3J;R%gWBJ*8*yF;R(poM1uE3dOm*3ibJva_oVl(*47U)xm_=#4Is%4Jjt_`bz
zT6eeDaXQz`6=&x89tV~ibihw@HDpO~R1=*=p5B$+x-jQs-kkSmv7gpAw}|xT>OWJC
z==9q0bvvG>kWX$Zx
zE$<(&gv~=H;A)8~_I&cMU#NvWPy7prCQpsG)LIVYzMafxw~T~t^S(3_dluZNm&*Lm
zCSg_WSxHb&mNWLeL~z4njav(cq?
ziR0e4-xRpX7tvqhxz@I2$BFCk*5Re*#s5e;!p80W7WhoH2A_qfGAOBQjNOrN7#9j6e5_QSbrQFqT+uhzlZ0o}5*{0BgmU=`{MCFLpj&9xicNpD^)7c`m
zf2!_(?yl+{r1N>K)UfIYDQ+?8Bg3**2Hr2FZ`a+)2znhd!q@j&npwAEFvFg(h9|&6
z3tgW2yl}UJ>J-enxr2?ve8nfc?}?k#-zr{8%K33Wjo_d~yl5FFpSLVml%HD^TmC>J
zn0P9>?tdGB3nPG~a}`FAK_hrF?f>ftXf|jBy^N^z{>Ot6yxvHA^kDKOdUymgKDqnr
z5lkqlM~+jX)hD+XWW2L?oLQoo($6d^b;hcj
zxz!SX{Z8V&>|NP26E7t~`qvgwd~9_QyVPE6k31b!*E(atWqvmI(#)hwNlS%aKtl^e
zaV}R^U>TSET~2f*=svg>djiouvLNhPRVGt^Z>dcEt4i&O#4)`kG8e2WQ9^pxS|}dC
zg)>cbF!@own;o_)fGLv_nm}J7^Uw
z#n3*7kR}BU1wJ&5(b>4SX-GeOz35u3yrTVAAHW)%%8jmm?LcljW?5)@g|wk3e?rEJ
zU(Q+je&Z)=Ayg_gExXFv%*k(-Cy68Su*eU)c@730lIW4jYwNl8YRCKgeu#T)sa
zhIi>)DEb!lR6?`klRth<)cW4O7JEKU$P_a)7x`fApK*fr?tXJi+)12jGBgH9I|Ca6
zr{9HhO-B>6MLO4PDWmssW;^dJfnN>F*R?$Jru7<-h{A;r&tVtb^Zdqb$w_}8WCH6p
z4I7#Bf>J*+5whV>uTHQ)Cn5ig@(sWruqY$?F;+dWEWF(BIv97Gm9cLu-bj(`x&|eS
zX!!;;{T~+VAJ-6q#o3;Keu$X2ikH8-=Ta|V1CS^D3}bLKnSL9z{G$Mk!Cr3kR*&Db
zZ^QTv{5xMM0udu0z!^I2xEH5d%hKft`ImEmcK}oZ)U@oYd;D5Wc=rI>N!~xkAH9it
zM_&bYb&Vk_*A!iC_FICjwK
zyoUE~kE}{guN5@KXKRV(YDVmncde51k(uNLG0svx-{5TlwV&vcWrU-HWJFjZ@qX{F
z$a7KWK^vhYhZLuCJ4uSPOqn@<(HttZRH&t0W-C9B3$CRY(}g7;6x6mZT=4lWM`T@8
zeI%rcRA%9mHZ`#7q}pID<0fz!4nH}$gSG;`~WC)SF|
zc|G-zK5QIDQ5!8lD^NoJsc&7_yOr7i_4izh<;+Cw3r;{DI<5)bLC|<=#vg0lv#hf!
znfCDRpyIROoQ`Wa^x)6JC{
zacBE2?k4|bjmTm6w444e$3#R$41lFgKeCm%lS?+X*W633zc^0rm2{vzB_)xNOv~Eb
zT$gb!A`m|L3M(p}!rHTO(RG)SqfvM3Poz=NeiD6p$U*%`Xk)Nat^7w=VtV3IXppTl
zp6udh<=vEfs%fNCg8ch}E3_Zrc_*H?ojE{yRrH3*rs8w0d-`|RCr3ICoRjpdJx|_C
zO6KF6uE7`PXSp87_q3-0)kG0pDQR@r*(N&W9gS!Ty}oq1roh2}q#mIE9C4=w9JALA
zu2`#SBx=ZMw1RiSh4)XxlDMb;>97R_j;A?gM1SBnonWF*Yc)FfOx`&MdN`7_Ae?lF
zJ^jyaOC|{to%3BGoAB~J7I*dibDFa`3%{U<1&YVOQB2f^iQvcG?Jh@mZ`f>cO8ez&
zu~o?_cA0iks&U_cCGwa!*mrH>KdLMp=J?gW)4pU+(1OnLKKUZDa2x8w0Hbk9{cJRy@m0S3ddDAg0wtHaN
z`We?$xrXxvMrf(JGUbOcZkn2xyd9&925FZzQ!Lef;Kn3X#*`Z{%{4{
z!gTkO$MeDgx3IwkAIQwHm`&tV!slLi89e!^+`|PeeY?;nnvMKG-;V2FkzdmZQI{Lu
zXOWLcgT{V>FqZkp`uP$vhI>gbIGptAXmI)NGh<#-EJ&PU@cFy3*+Qq)2R&S3I3S&r
zlRj#lG5zB2S^H$t>!M3_BmbxbU9PznyAiq!$3){6Rh}0iT-Is$CwzZi*4At9NOo)5
zjAb9;W&qR=9~=Doi9lX%E5=vy>v#NgK8|0v<0t4G=kY$g#(L8c
zJ;ILo33Ox$u4&GN{(zSJ6|-x`S4US~5>O)bRqgxrZ`VQFs8PH$W&w@jwDDwchbI|Ssm7J7!5ihU2s5-xMOVwS%m@2k0)HU$FxKG^GHN8bbDNoy
zIijuMHnnm4h4+>_m&`r@?R;9%Z%L`EPJ|8N4jdU;E>dyoqJ}xM+cV!~os_2Kq11iji`Cyh}&ds<75zMi$
zm{}t-5&3cyI-0|zAAXnF>T~R0Z0yw{;I8UU76qFF4s9sXhpBPDo1XgGa{bU@I>a&t
zAjUBOF^&Te&o}__i~|tk7=ZZ40K`Ay_vHcjJpjK4{PM%Ns>qBe=a_7^GIT!hh-WH;
zfX18R3c`MGHFPvE+$CjroZ7vlfhpI#x1!9kGH5yO(7W(WA9ht;X4Q2%71JnUF2G0=r2XDZE!Mm9{Dvr*@Fp)tlgzZz2DiU2FJ_{Ta8n1)Xb-}q@%1or+_6FP6%8LywpQU+R
zu3?0MyPj{!x9fUvi=*zx7^tt7g-`H*c!r&33qvM6%;^TrB3dz8MKM=%Ip2beN#WMy
z8ac!I2bxI4lny{d>430U#FP#|Oz8l`lm;NCGypNB0f;FLKuoDWVoLoHQ|gbHQvaU$
ziJ)!RMDjkVoo9*`qEBJ(I#}SCDHLZw3(kAKCNws>PK4t+t;o7UXt|rN
zcKRy#)tblmSzH+_kXbXM*P4%8)W3T}re-kFRr}ZQ$JCE^Cp9~Huk(yM<$KoEb+41p
zRKLov>-Xk%3;)ZKH(VMYKsVgzcRY*M@J7E&PW}(Cv*(;v%U-4X**2zl^VmX~W1s?$
z!s#HC#yiS#HB(&Qa>|Nq;$o@h6peYGnMP0JrZNBD#@jQ0sl8U9QPa%K6lh)&Uq+j<+kMRp$SC(mXrz`7
zP}?i`tU{?j?X#p!8&{?LUc+2J_)v*0nuSt{RL$G_EO`DA&WA7EHFem<26dx*+(Opf
zug>INbJ6I+y~?M4ClxD`$V$}g6wG44(Vsc9m|b;IYv$9d9;aE;ZM?|3-u)lOmHc10
zfl(_Be+2f##c1Z!oO3-i+x0^C;N?B8PQ(!8XhLaz`OJ>cu7RKC-09g8V#q8q9?#m9
zQRYU*<^RLlyTCPdr2XS_lAHvLN-$uci)$nxmbMl}j*MlUQvIPE;WSLy87Mz`PXr?^zrIeCMDbFB9
zHT)CTHChee-JP0|JMB(eU_H<}2+X5V^#>~D^%L~NKX%%OPRp98M3j#;no;$V^;W}Q
zT-P3Err%yxjM|@Pn<9;dB20uxcvmx)#zrXCOc$~Kw&pqgt)51K>pi{9Zp!Rry-+9B
zpNSLlsCw@#)%y8bzVErK5>`tZ*vma>c175(y-Xtn}}7?OB_6H
zTXRAy6GMh2duLtxTa8sX-ZI<$G*(Fd!Qh&S?~ImLNUsq&$^C_6|Ke*jE;X%?<(TW|
zG1ouA3ORO*wBXWA|8t|S&G)mnFaN<)llt0fCMNd>)dj8Y%ibC7-TSX@y|Vyk8tMBV
zNCKuiZ
zAJs3zm#t9+Y7hC*Yv9YUf+r7^a_*UGjMmOo5y_UZB^n9g^X>;*I3jQr~MpzkZxZ
zP;D*H)98%xPF(Tx1@xZkSdQLr-}{cu`_hgNeFIP5}P$lpIFIu|Ta
z!gn>j@vai`H3RQbLZ|KI=Y$W!_`Hm%zwl1z<#hg@3tlzoAR*WYA~O8NMA<{UO{uHPLB{+zDtv
z7l6%X2PA>uU9N!knZd1lqwTI~{^X*)=jaZev-HJ?dTA$E*w#N&s$oR^@=pWv$ki*E
z=WQ>2A=|7zG-^L6nqu3*|Frk&JEItPi1vWsMm_YgrrtG*&ApE*T>pHS(Y~B#E8lT7
zFL{?#Uq+l%-`77&dzBu$**gsq6hrINst8-K*vKckkMmm>Z$F!Rs{ZW$v)E5h1fd75
zL|^v+nyiUK#a%Di!ILl^w;5zJ^OCqp~#;>uN1`UAMZ>TLk
z@5fW7-^^vUW1~-vsvY&!$YUKOBco
zB`k@X5ew){)hM*P@SpeBef~#Rr-m!vyC#4A_hDo88M$J+^hJ&14E&=tgK!ctdKI7C
zAS<`o57F0QW2JND9#7BdS+GQh-8H1-IIAbrJxcjx8;ZJ?db(j93JdL*JmvP1>bsD9
zj9y1t5e=W|dhk|!g_CZy7>{Xiwz?j6Q%623nw1)#x29pjgn_WW7Hm9XGyx;%(Z{Vl
zr{A^prZ$~}sJ$1>YwGA%c^p}!qMsK`eO2%a3ArF)Xq;1#5{Q$udASAKYtOx
z`N`e!wb9O@z}iRELv3ZaUm?ndQ)4u(X2Kg;$x3)53`$Y=UZ^H{#?V#U5qWR;zM_=a
zeR_W!bHwyuu?NYnKS|3nvr@Pe{djHlMC^Y;k6=Y(j_~S3+}Rw=w<)Djj<{89dojg!
zO>|b6O)=Xc0pcU*TPp8;Aov%@HWgEDv#?F7uX!FPl)6P(M+Y5sKqHi>-`3n
z-s*Tbn+2JvRoD3MZ-Yxf%eXy95!_Sn*MJAtJTM=U)8hX4HTIE%@bu(*LKleB;D$(s
zSVm_$xx`+(&7Tyz&P1ADa8HDH_ciu;9->Y7HD{U!L@f>8sH#w^`7w?y^t(~Cw9nDB_6sn*7*P^4ex&rfZdD?Yx
zl{zq11nnl3H$V8+#GGx`=cw293+i}2QR__3tGWU|C*S0dD^X^usSy#+VBK|X_{rZ@
zMU54{tx(JwE2MYPJo$;{3EhP-U539hr&FPDZ_o3lmflDVek}RgZpbWNE#?~YCW^Q{
zd@jloVXn+gN}lMBs*R|=ep`a|J?~>(RDQvp#?|8r%J)1YmiC>Yk$5IAQL{Apf;*x%
zs=8%2jqmQX?W?`N<*)P{OTWTrP%nqrO{L#~GWz`-qK`(hQTdB@53y4YrFZOEp4PRS
zR!ZcevU52Xww`S~edyG&6ErsmXGb1(+Rq*6oIF4ERH|*pCo=}l3?_-?
z`WD1`7xwe&1l-F#+$JRR>Yer{79fz1IdNGR>smUh*qNb!ERyM0X);Bfxp7GfwLIW!
zLlb!`+Ao|w7nplN)j|7d#tEUpu>Z4jos(%s{;I`k5{>6l)*nPGDyh!l7OImQm)1dR
z<-yz6H;Q_6%`nkJ#%YhJj@UnIf1Zcn;>ML%Il`N1FEZ}_KU@oanNme_mA*1S+F6sE
z;+e6i?8M+~>fhF5jYo1$?aUsLCw#>#sGqx&1Us)7YTuLb$>grWWlKMI4@@OnIEuQ8
z^RBt1nop;j!@zB4rW2OX0(mQ7B?c8A{A4mpYnZB}T0LV!Drcnjy_nRV5YM*)wP>Fta?s^*wwc^dtumOw|1;g6a=-12aIZsdWX
zw(YqtHQJJHXn3dT)=O2()0S5y!!w1VNsDc?c+>>%;OzAc6p@``-S^t(v4RrgdO
zs7W!{N#85n5}Xn@B91_GbWXHorC4lWRCU{h
z%N|6Jse44?3)J=SIm_k`>mkvNcSnsW*oSskH>m)Fqe&I*G#NE)<$bM7wMs2euYJao
z{iQyK*Zf4^=!y
zTP4PS4EQlfwbD$bl;vrJU+O*hP2+?{da?4<9t;>?8B=H8ik8DF2dXSRrV`o2P~6!G+{5i1Z!Ec^f4h|&C6uli48
zmj0_Tqh6$m90qwQst--9kI$nU4~Uz)E^^ah6I@GkSy-*BFIhl*b}(w}wu8a*ufIv2
zpyUTyULRpj9b2ivZ42j{)L|CA+Q4+x-F?GqO)QClAAm%X;U@AWrLeVbW?dGQgcRak<8
z!^TKeKfAKuQ`jDy93SYxg>3JDSx|=<4WL
zadf4gZ(D)809Od>%UNRjw~W8+3Tj)ySp`>LzVh1!Cb)vw%1ps^QjwVPE$r)(a5qBY
zpT3243hn^Yw5tE|!
z;nG}s@`pEtgQz`9-7~RuE6cKHS?7LF_bSjjfd8H5$Qb>J4&2?=0NiKKnzQH}q%F=d(QOL9Fs%#41M|k3?0e`B1h{5UeJB=k2WR
ztMuASV-mGbC!^&t!q*v^zuN)P@o7qoxI#EQjd!VbC|o%+;nA3yT$#EKcS)RK=T|3&
zonS6^EqhA)v7<8MXZF|N%Byi)wDS{ZDYhA*I6+eqtR;NP59X<=6YPYGrKFp
z+8Jk=4NS}#Bb?4q4zMMvrzS@`4^g=v<5z!}P4D`gRZ5?3QhVaO-7IlfCQF=`&27!w
z1dC&W^A&|~2yns{O`p388rf;dmDAc;W$`suc`b=c3~R<*&Ai=haJ{yeRr
zWiE9#d@Ojo_bcr!k2({+(Rqz{-X_b^wlN)rgiU?gFs5JE#HFluok(J5_GDSes+LRP
z?ALa?{jAZITk(LQiL{*=Pr3(kjjo*e9s!CHcO2exD?Ty6A{lw#NO@a#3*R-Vq`Wwd
zlvi;^${VN_E(h{5cqy;7331FL@C_^vv&@DHu2HXvGYhS)ij|pKn|-?WlznH%1OWO4nDrd&1^$t7agSdy0c(Kil
zV!i)+Zfl5?L#t6;|5F@G2+lZD`087l1iZhVlxt?=q^cnuA=k_?%b3T!4#6ANK&At5@(w9Lp}jnlmj
zYcM6%Y+b@sEoBL4P4&NS
z4d08cK^kzUHKfU{snR|9aeS0;K*Kyz>P`3vs8XnGun3uydIK=JYci=}l@xoK*
z$ZwQ9Msw;VPty3>!S#wm)H~%i&2;4!`*g>a-099goJmRQkqP~ADXid)Out&2S!N$<
zKU28AmCBk*<7Sx3a;KZNxTpWSS7umgFc
zHAV{elPCG7l(ZW@|*K-Mf}j^4RXG
z0jLRO|KO*aA_`jjLVLWfwNpPYhB-a4cJI5b?fQ8t#hNOs_@%JGuNY2W^rbHzp)bOQ
zQ2jr8G;gqe+aI$Ft6IZg`@fb_m@2PqikOln{!Kw_{MNAF;cna3HsUwJ%Y>EF48paW
zYVsvQtzoEDv7E~Gq59J)?n0j>RR2F+%_?2jZn9w#-fY#uYgGZOCQ3D@@6ltgz`e>k
z;U!4lG;b}s=v#=j3
zf$yM`m9!^zeNmG!d-dfnDDFWER;r49jlV&x!;?5~9#>Q8(U`GwCC;;OXUtX{>Gs(b=kQJ=Xw^vxQ4tQV!b+RyjT7`uu0)Ana>?o|mnJ_U8yvlbC@NiDt
z(16&yiwg9^!?A-bpL!mvi0MG9dK2#|MJkzCuQk-EhGq+wT6T#(S&
z+9R(J(MxXRIrOPCWN_nS>T28B4epBMx>6Agdd4NNWmtie!Ny^}jv&LsxH;r|j%0<-1cI>O*v`)cV
z++pHQu+1Fe-Au}|MUHh%L%yP!ZC121?U)mppfR?@w0&kiFZ8lggI(l-zPFv~FV}n5
zs&NCjhWmRVc4{SWb$a!hR90Z4xVl+vkwEI!=}@;w=IOtH3L4>;D)UB`GQ3A@xo+P}8TeVo%o
zeH=8c#H<~jz94Jkfx?pNIZwN$wR75G&CB$LRQ9&!Orf#?kvx|AyHHbRJ1a3m9-}Hg
zyxuD9cbWSW`7P$e;iXL4<7jv0ttZ73V?3f|NKjWF@t~z&o*rt|?rK<+|4GJ6dc!={
z;Ycfd7cH2;uS7vQDM@;Yts|UL-PL;ob<4eGPhWa^O4ahzSLL*VK|Epdg9x}=WnpR>dLEX?m66`POY6j
z=xBhSLxUAsI7d_Y*N@Ne
z&~xNBdx-CrQ%5$vR3+wq^SdhEMz?qY2R~HwBuzpmOs&NM?=$uF7NgE
z29RRCrs5k|Oc~Q`N3ERIXHK2$Gp|d}vKodXk8e5SGuJ}$B-nU`l;S+&OBnV%N*-}6
zOqx2Zk6xXV;TB^AIe&{;Y#z2iD#xSTiMfWcI86lYFLo!u47h`;Pc?eMog
zZ9p6$JzwtdwH-I1?Zt*A)T;BmFCpw1xxG`qgw)y6d);YY!n#=`RpcPAgO|V~IH%!6
z0Ul(&zx_^s4pD!euzhCbA)S)Gj6DsFW5TXkTq&I^e7fwg?asS(4tts_eU(ktt<0o5
z&gh1-z`bU4%h|Zo6Hm=N@^Za)@@^K7+mE%M@FVfH6+Pq2-}WV3N^*}w?^b>NLQ
z!nO%yw+b130to5lWSL%wR%!`~Uj}vO~^j=b0++i^VrCR}EjJ
zSDS-gWa`7dg!Wg3r%NG$Fb5%C@qr4+fu0BV_~butntOqc%VP(eFSd4j+!-|b8F^7P
zZacj-yiro)f;>HHFXH!zd2w$dZyM!ka_{D0HcRs*$UPi+&bq%yShqSbhQ@?th9xux
zE&b7MkusodjKa6=p<|^j?nl_7R5lH2cyG
znBgPj^e@qa;nI5x-gga?%EX4Fe4>;di}YdgdpeaLDwS#JgYrY==T)VZ+jC&Qf;@q)kYemu~MXxRh8iSvEM@u)G=$DAol((H&Cc^q;-&<<{F)>uf7
zY_Su!P1M>?X7=-rSg*vns~o=gnr`f`Awug_M*DCYImB@Sbrx4-gmzm%U
zQfLjQ2Z-hWRv0tMaZ6x^?%vtg$Vg2i|awrF$!-9`GJoohPEDbqz>FDWnvg
zkfMpH4;dB%YE?GpUVwR!7u=;^#hr7hGDo>z!0%O!T0X__2b9qM%^zi^_;K*Vtd2aa
zjO)P?o0=7g{#He#*JON%tMt1Sbcabi2it?T-?IZ%GZr--(FZ59vJ?Gq%bPo#=u+Ju
z5ku!#4k*u)E~PyT_RA`UxbI=P?Br@!Zc??dv7PxY9eJL#JERYibUk?)`kW-Cu&!3&
zun&V(_*N$@L2>ta|;WU*YiU-
zQ*h0FUpega7;K$U-(qG8qGvYSjHfT*_8SiS0FK%lwa#JRg4RqS*HyktuS7aM-5Q~&
zU4#V``;spHGfxem)HDch{U<1W)uV%A0iA)$s6^<{1K7CBJ=p4eo|O?tWFQ#k$*?RI
zVIi1I!GNi{OnY)Sq763O(|YyjzBPMHs-tYP>N2Ew?^v|fyi8u@OW3m9`E&zX`kQ?TmgUNvkI%{Ja=R@^ul-A)7G6$uw)hg}{h7G5ckBjG
zEfen_OI+pM9?UNc^uX$r;WiL!nI7mt>>E-}Y!k{a4zz8}
zmCGY_%OCIdz?mc0kG(Nw(cK<6<#uV$+=6?=rGB-@rPHxHTV4*-?Q}?W@MnDq%`Z~F
zHc9;o_CFrz*LK`QY5)zQ-I{vRoPpgw;iDtkSUw8!zH_FP709dWqH~!kyF%n)X_qFf
zQ2CHUkhzY+ohQun_NH^%;rvLS@scgD;tjD>bKPHo*XKGsvlo@s=G04(vq%P_wDU}{
zS5d2gbl$81H`3RyN@WSmjju3AUjGy0d0)asN13&c&C$08K2sPIr>Bvgo3k1kp>GI*
z^gl#uCHBu^{)VRgzJ%{^H&SFyy3rsTtUeSeGsR3Jt#Fu7bMjm`)55LhIMwh
zd#^o47ilx8t}Bk&w>m++AJ~ldD|XJZKE=deSNv!<#G@ZQRxNYm=~}hwPn(gta#~~x
zR*z!sG*AKP6ij8;AMhmS6mOO6V=%xeASkzo#y%IQ!Ka&$Y)3ratl(<=}x+L$L!O!^MSWr
zV@MlGd@tSZ2TQVq{_C~F_>l(e8T#P7P0~3W@a`Vy)K1Q$5#5p>!$;AsjM1b$SvPE)
zK0E82!=B2Dy*}Np=jd%Sw~lQ)m_^*N@vTRdX|ODNW!*Rjp7MG)2zZkm{4n`<`d9cp
zLa83cU^|V|L1bTFTbN0SeELS5`A3>H(iu;Ya(9hLa4Ri5d&f>ABK(xg`oW_q>s+v1
zzpOpPkdA)v{Cbn4m2Gy!ap+%eKGu!H$=T#_m;t)>klU?jG;MRA_36S=p?z$7a@YSBs`C81P<_;W7pmA*zP8&}o%3AT
zDkJfCjtcwo0AyQV4nSs`Tn7J639`CLm=Dn+WFNSX_;icM5oGUe|21S1wn$R2nen(Y
zL;5;)BIeg`l?P}|GbN3spzl)q+ER!6su#a1jp1ay2V9TogE*xUql>dtU%x{7nja7P
z^MDKo-nT?1r9YefX2llyj2;+2cpxgheY$Q*EhO}kX34NY
zcV~%p8|n+YJ4^WO_^qc|l7%%E*%z~`Z5O+5mQ=4xPZp&VB-L`zy4RTb_-ycAy@ZXe
zY9;AYXrKIr$8d+?7E&dLS-;2L-(YCcV+_oE`pWc}qpS!;y(YhZui1Nw$)1Art4<=eqOTVW3
zlXqI*IGkwxR{XvHusj|kR_{BqZ(YM`tTuwk_#5n*q2V66{l|UA6Myv?OZ#G1=_&Ur
z+CMcEJSI^D!rrC^+QUp7&!lh4|I24w_ZOmW&o*lzpNEgnZ~Y{l6ln`lgDr71>!cN`
zU(yi*j6L1$LGPXp%(wF4K4a?AYgI&*5wTH4V4~ahG;>CeI
zk9h7o--Y?((-xK0+J_$bY+RICIM$^y8HaKCR!hW8Xa30;
z&Z$Cs^SrLq+Xg4f@##1Vg$Y>YY}b@PuUZCQ|3QMzI%K%Vd(7T#LhSJ+Rl-}Xy&*r~
z#U2=+ZI|&n&}VFa=Jn7~XGeyPIz20N)TyY@Q72vx9(8PF@TepI`<^+Yea02H{=H}U
z{f|=5j{J8$TRin{&+3L^JkqFV!zONb27fI<+hRn2Q@8E$o{)M~BhTUV=sd{(kEoz|
zXr|Li*khqBG7e0!yR&t3At!{bMZGD40|wt~mVWz;x4m+`12CT_{`)u$%yEn3RQ?0L
zy3Sd|5fb^79>(Gna2J-RocU=n9C1nDM2xB9ynTnsV^a>yrlw?Bi3X=8%&xpUXTeG6
z19SZqjnL1}l0$=eaC*iSA7Ks7ymyvMw9Ckglr^eY}`IKiP8am0^vLp$xtdr*dcQ}$c2}_xMscl|Gm>KLG
zTrZ^>qjy^4$vfWI9xFnV(SGyj9#hW&SiASlod|zlqK(pMzNLoFtA~*8S7C=kTx#gQ
zUM5`|XlQP0AK;Vnb%8ko9h@2(vs==vci!+BhxK=qbLXVr{H=26$mVFEX;YIv5xl4d
z8b4^!%o=FyZc3$MJFs8;#+?R^q&!xpA}w7{;LA*nx1{xkRI2Vrtlvo7?)*CFQaaJ9
z*d7nQFSm0Y^TFV7*2wKT+wi;Z$5nFuKGYxXmgr+~AgxQzwPGc<>kZ(_^y>P5Nu_wX
zl=ENcPoGe^Wchbkf1wWN$8swzKP-@Q_-kk{#Bnk!(C;6T19YSn^rg3>?x>to{=++-
z`*0rySI|56EJz~&9Obk^Pnw{C#u1o*MGal5TH+i=gGVLJhNB|+f%V_JA&CKx@R2B2
z{+s4Q#25MIoEaQ>rry%rT~m0j8nG?TWa968XMDOH{gwp!d=>Dje7d(D{Q+?gCihRn
z-&dkx_o~|w4PITh!-UAJx*ajZA?$C6ug~09yU(-*T(0h|sG;`8oPm&L%6R+){bTDr
zWTpAoBK3vnbCQgfm#@ZzU
zKa3-5?U*IJ${QXN*zb<|jH<;`s$4jsd2^d?2t}=O{i!{B$@Q0?#rKQu)E^8rI$F*zK@}auc21atn3G(4Xg}+W6yWKSO%2
zJK{5LneQ<~CxUa-jjE>zUG`K{#C6De0z-ap2Bf4t9QFXC;*
z4W)H4Qjg-j%CEF$&Fb%tvtQeu%Y7fD2o=K@I0E^ho24IJ^9}}BFX^&Sx$R&OEiL|!A`=r-+cRqH?{PF9BG3yi(
z_v&1S`H*zK+-5Xlt&>HKYuPa9dxFI{A6T!$@~tV;MS3tySigXK1~6qO@+!%8S+ZPk
z;Pijzr=IoE0Uu#8awr#ulP>I@XK0z7=1CPX87sDsld|
zd}g52Wt=|~^~EJu)m6)DWjlTkbYO1E<^D!B!C%feFLtLa`zc2Y*)hf6LboW^l}^7+
z`rynlDOFnov>j=dXrztWBkvn^e*=C8+^yNVmEfbAYx@Uk<}08J7z6l!+bGvlz7_fX
z9tqU3&1Yu)
zRVuB!WLk22rvpBPO8ZgJj2O07^SS#)Mmhk{r;nA^VREVWb_7bv^P-qa5`B~Ld{_(I
zmSN^MD;?pN<=Mg)3zcb?8OrZCk@~UcUQAl&g6^)9dTnz{
zm~{4*dhL7`^A1{@dogK!OUkQz7IMA6-j7M=n^GP>2lB+%9k#{5@;n*Kb*rU3EAoc@
z#Q{x?(v~gf@%eIl$XmQjY1@MNbp#PGcEP&5Gl*nDLQ!WBNfd|%>q)}MQu`_mmsz9WTN_qUVr54g>`E;qTDuFTIj$QrlVlMp+
zq%V}mcXDK4eEajeT{#)IN&B`QaWK4BPQv1FDL=PL(r-Ce$o-v${=THNZV^ZO;<~$|
z-5+NuX|!qlXq=~jub8aDsY@l#6N4X`tlAa69qmv2?u&azrrZvj_nU^kw5!fvA&pE+
zyVPO}Y+Fyvm*KVYGQ4KB^9vVmR0;2SjKsAG?=`6JtlmS?5BbmXN@ydN{M&q#UY$XhqTfmyD^
zN|3OYK1<4LLEedR4$O4YSxR~3Gv)RGOIV78(Sd_#A0}EeM?2+9oQ75RLhX#jc%GJ^
zRtxfY9+PURGhsX}QZ4l+d4^QC&HwBZ2|N5;jGH;@6XMGxOR>S(y;?rZ8Jv>^UxX|x
zur^%ON4*6ro-8+Rqs}@f$&N`E<+OVr=)jE<>9;==%WFrdM-q;&$#O!{9FTT|Bo?uv
z6dvodTM%-|?td}l#Nr6?GcjIC%TrPBJvT9VpYz`um7QgO(5_wAYII{?fo;A#rs>mN
zkVWe??YFfDS}pMP$pIb{A%%TOSr^0dhX-S>^#94xkjnOa4+-{coOPu6f)$!NL^~XF
zsdQZ&<#Uz;O(JG>)dQ6$Rm?Z1HrauvRK5i(C3UdF30;IVm&V}tBg&k6q|BEr4=9mO
z--x=19Wg6ns~}In$}Al)SH#1>z3>PlP6RN6$8fYW+3unj{QbK(}^rXFIvIW
zX>nWaw^So%)vGMs*b}b)-A?+8M=WIV0ewWbVX8U!9yTX@I|8u1*Krp%UV+3xuCQRhbCux_FY|0p52v)SwOlR
z5pUKTCPx=^IS+Ec=XZBuuImIok1Oj{%uyePJ>?Zp!&5i(Bl;rFvf$`s!FFY14DMLp
zzy@nvn#NzqNA+FU)7KPM&Ot8Y+r&KOH2xV|4V0
zK`X6Nsk+|XkUiDTR9Khi`F6}xj798_NnZ-#{GhdRiS!Ui$Kh3$J-v?=lu7B^k*!3`
z4U3N*dCX^4;Z}enV@YPeq7{)d#^BdzK7GbOl$ekIDa)bV-Wlx~0biJkoJ{yGiT*;S
zEuEQi`&!JDNx<33TerdUe=&%Wtpj}65U)K;JP$&zWPDhr>9Lt8Jz27(tN57CWAOdj
zQM6BbYxwxI{1#VP)F7qh?m8{MweBuDD5cpwr{%YbPm2yqX`0VZ%WoN96djlA`^V|y
zu;Mqb9wWi(RC;}jkJQ&0OR-2Zj-WnyuwkQui#T+
z9|{%Q4vp?tMc4&(!VU%78i#L3CA^Vwd#n5{{{!gMAjs*)!Kalhfip}?PiWp{F*Y~a8rG5Ox9ttE2eXB$MThKvDd3K*}e8$2-NW%`WxNi
zfp@{W)?WgtvESnsQp|F2VjCRq+nMtHTz0}9)|firEmy4npRV
zn{^>M^o@O{wH`*a#ZETr2v{}_d@3zBMu{lVa
zlsj@Wo_vN=L!OirX-v?<>liUtQQu8B?vjNxIq2M1)Gpp$E*fLnKp3H$9BFMU<1~E;
zJE!-7r+(!wekcyJgd^&^sh9tGL`nf{KK5RRI0EMh%8TvN`?e~vUlp2{s5I*QJtEuJ
zhuU6be}@lKCi|iAv%^v!wmx4p+STM_`MaGX0Ru(;eaRzww@Ud}=W81}ExbnC)M=r*
zaFR@kDQUuaB?mb`>;*1~=#tu*J;>Uy#KHu<{>`B^U4w^1|G
z$Et4M`wjmz@Nwzq@@}QIi}g6WXiPt^fhb#yW|sJjmY+uX
zIao83x07ck!_==~M9?=#VnDoZj#a@R&9W)?!%=
zLH0yz2RxLe)QnUqb?kkqn%~Q1$4g~NJ}2ERu0FIqo3prs!S&^ByA@7amCT8x^?5}$RR@r0^LFY@!vU^4QtYoL{^fYC?
zN2yKHqzE^zDwGWku;qx>%y^UbCdXE_g|`buS4FE6r87wh8T$tTok!8M0-H9eVWju!
z)nBv&)lrqWpMkSo7Bzze9k_XCPcw0AJF_t#_C=X@nztefQXs+{m7(1D?4V>S@m|fZ
zOZ2QUDR^emsZ)<=?4PzS6v^K5}%Fxd)=Z`0&;9bRa$dZAvh?83rVGw
zY4b$ODvG4&AaIyTfTI6kE+udETh?-cxGcWq9ar>XDC28x_y?{M$1X-GO3GW0W
z?irm~$ZL*nTMpdd9tCe`swuB|*4VC#E8W+tw&o&A6Kl*>&Va0NW-aS!&fldOnV1uw
zOj3cy^+IOAHwd~E_u4q%#r3|e4hHyhk3wh+wC75h`=skDEOba
zvza4^e}t4FaJw?;VasxbpR(E3Tu15wrUk@~X$u%`pJnf?CYjTh>xHH38194vU3<1-
zN!38{t!gWkNK~&gCpwE6`HB-)u1u}NDdD}VJI&<97HtV&{6Ay3>X-i=hPV8W7~Vn{
z4*#Dp4EyqM8N<+g{2IeokKc>ofbHJOOq>Rei{6!E0C`&|b67cPCoB5}FN@US(WEHpjrH?Pd}Toq3z$w?Y^p7vlo6|nOEpc8pdTn4Xi
zJUs^GRr-uLc6#4wyFSCfPB+lgENEmBGwqqmPQ6Fpt``=Z|`srxfmr@D=}3*;Q9v;mGqg-PnmwrQH~lq-NE-
z?3BvPQtFL;Nny-5%K`~TP*O0{L3{D@tlE<4Q>>M(aa_r1X`WoVT{0awY9m~goQ|5l
zd?`4tkgmcgyf0Wvsq~hl31Q1#JA-#fr+^c^x^o3#P{c`wCW4-e3iPVP#qtTMH}mQR`{{doq{yZ%0Lg*O`yIV|FN_R%R}QGd6a&K^TR}pN@C+4QER>
zrWJmA@YC_jHm2Z-v8BAXJ{>=#hA=@n9(6axL&1!qUx*c|l%GB6xumdWzEp!p-HviJ
z>MD%&r{MONY?QvI^kw2ZX4)^}*Gv6BNncAPsD&kk*YC)Ae~MuVKP^=y7>0qXP;EKn
z+cEkDCDx3ubmf!M^U5pYv$|{uJ-LBOyNW?Z1xq*Ij<&&&DMWzBlH{LPe5~+$u{7H;
z89CZOPWnk7^Ia2jE**PLd>%PAQ2Kr45AyR7DgDY)>35$eNs@5;dtd3=Kg(@G*CJs$
z4l$hyz{|HI770Zfxw|`q%fncJH*S>HkO4e1;IYA5zd!2m!qT-baG~K=P~Or%zU1M#LCH9~
z@S&i=Y+>apoW^~Z{`ibUSLsVfoJI$llL@M6^y@s7vQ?wg!{WvJmHO6Cv6xe@sS+ZH
zQtD{FIkwt$IK#!QFZA?fgYrF^k;<*Ml2_m26C`QEz#T=WOdC2CZ=H>(G4<(Sy1D=z
zd{v&GXhYX+SYCjqc{cqWWGby77zQOF#ZjTwbrt?_yPp-~Ir~+eG$)8_qLQ=*Z;XMw
zYDM>J`lXu8l)@YPZj2$goLEse_E9Z-hNHrkN_8M&)7bLS
z4IB>h9@5;}l<}Fy^l%r$3CGx_NX{?~yoR{TUCfO-T-nXXsfL0|a
zSGtE>+i6eA&CG;k>wAY(T%zE_{v8EK%6j`$wH9724z`Jb{Q|V3-le%5%@n+3G
zaMl-Ld;+C|aVwZE&J=zfwi!}tg80p2$P29_jbHA6nZoYo>eX|_{NeZJ>#sBAw7E<<
zbrW+;&0-#V2=;KlX_Wd)^(YNSGiI=R@P-dJBu?#ARG#Won8IriKg_Q%g&k$v)r4yk
zYB&W=z|q247agd{ftnIMO-ye$uzdGbGu3+UZz^w!ZXe{Z*J3{LY>hWG!!)>gU=n6V
z#7r7DSA&7M>N{`W(ky{@e$-iyCW1p>dWx+X{k;PtKvFTidf;DawC0L^Dv;#Z8vpA7
zj2LiAflhcEmFXwrtTe;iNm#rA7t4XdR0_4eiPWZ0pi_ciw4;T<-o
zcrUQeMwvOm^qyy5fb`N3dUx8FdBizhs41E2xwA&Zoi=W<3m&pTW0n^L$?JsnPw4&r
zSTsgi=NY75nwt>mRi4Zp1kR66vT4p@`OV7XO)A~6Q0w7GzH!j>b}QC{z;`Ib)yuOu
zR}LbJ7QBC!kQ(bgAiO&uNU4*4gTh*64tw|zngbjnv*LLBuNa?V9I_zQKP*sfP3webq
z?J;b$_#DQb)66b(Y1BcdzY(o1>=st0KJ%v1K95S^xfmtDgIyGDDsUE*a<|C2yTshn
z$UT7;YUSK!Ik#QR{d6B;#+t`%C@ZMTdPyo_oc$
zRHZ7|N2LjlqT_O@53fEYmiif`s(<{8YiSs}yw7R(fC8FIyA+1UunL0nCKDxe<_jw|
zQP4NEJ^Qw!B9B{Z>7LrP(eyzV!|9I+xlIa;v2MAcGPm6<^5j9w48n`BDU3eDs658L
zn@anRtjwUZBVwce=Whm`VW{oSjPX?u{i7r90JnS^EUs~SL_e_8bkj4a%OEtn0aev%
zkrz3Fo(5$dL=N>dsOUKOfqd7}Y_>*BlW;qGqllG7o90#G1iGfdcVy^u^hNe@*U}jF
z^*)b^4a&2Z90|56w?TW-_TE9U?jlKImh&X`vO&Fq^=e&QqdVUnr=d6;=wFDbv~!S4
zeMI?rZoc7+5mvKtNg9?}d8!GV|BY(E6W6a$>#jFC9gvHR{Iog=9HwKSro?p>x49Ub
zN=z~S5|LMbYq`PIn#)Q~mrMZ9{#D5Yis@GJl@l=eE)5;xT54fy4il7XkP-?GWkpTN
zgmCK*8%w_Ol`5W3ej~V+`jd>AboW$8XFA`dz3Q$#29Y9Y5*E87q{cA~5>fO-SmuYM(|_8e>%?ud
zP7UHS(}@f-01(%#%#3xPT|d
zU!*}nMTd#w2&^)f#;gz!VTSBN@1CotHU{FdkH{Ok>cc!}0Ksv)va^i`Y7%oH7trMP
zEU*c6o$%Q=sr)_j-PtPB_Bf>*yAk-fP1@Sr%&c*S|ARH79UrL{{SB7PDwyCLKXn~h
z&S>4;>VBbG)c$CfrdFvv({2&g{h7ZzRwNA`J$~o-=m~2l(73rD2PCV$
z(>p2}IYftXJ92v{y+N9Ys`1(2CeN>#5AHf^O~duVmW!tNrp&L=MttsICq-^@
zg@YEfSi#rvI{uKf(`CdK*zy}%Ey6WKTg`>eyFnA&D_@9gV#-r-+%|inx>K>RbZE$f
zbjqncU$wCGk6|R)a)bW5^700Z+pj&a%|hd&KJ-+rKFkT*UuA5Hg5spbUc(#X>ZXMI
zN~7&c$j+qq=Me3d!)XK5tCJ$%I`MY9qYV0*1RYKgz3I(}w`0BNZ4Tas_KJ48__h$#
zgQya|($S-7e6&Z3A)!2Gp)sNnQo_<0Cr|TJ&KVS^N!y{qNfW;Ez+Ar$l^dsZ=;Ahq
zS{Ih?eSt7bQWAB2FN?I790==9g%6QMzob1RtASvuy1qP&?CI~76eI&~X@=H?E^K=j
zlBd~=o;oLu_;y{seY<7ig+QD^S8!X1utpP2k(Bj(CUl*?(y~F?w0LWL_B$zpiZ|-R
z^I(IZPqz}>^Ypw$;d^WERFgp!WD3InNc?{Q|FxQth!fThj(zYsXp|Jb($aAB-xtT_+vBap2O;NHytL7j(+Y{VU$JE4=G<1r
z4|dZ7^rb~1S+~?5hQ=imUxoPlx-^+#rl@v?GQW|^$a%b+*N@uHR+vKDgOp8M6fVt<
z5J-1})__abJZS3E90Z;;i0aNqoi6n&MpOS2%+wq4)$reOsurC0i6BRPv%;jNXS-rE
zo>+?;n;3EWnr)xw2(S9tmpP_B$e)J#LR1P9Q>jd$_#dWH>HV#@Va=tW`(Vg=2d5bW
zwWv~>dbO*84<+yc%*7~8zs2t+i_&CNVb{n1{_W}#^Qc;+LB4*Sa3@9;aWo(XhXyAm
z%c%Y5ETbAr#*X?5J>X2esZ1*T+r+XQVuMiMIg{?X;@pH$$4VxTI)S`yXJD)MYX-bvgX$SbaI
zJX&Z9@&~QV47?%6Yp}~OkbV93`8Q2LO+gEFnZFHC7^#Jd=6tk3YnWDVUPCWi9#+A#
zHv((#xyPe(%0yj?o;T|t2Q7WBKhfsE7Xur&BX%%xyF+WS*C$K0+Ar?3<~O)4(KhWV
z547NwZVx+9DCu>MSzH~6JT-S=Y1uHD9-Si?@*6ystOjMBoq>yn1kI$_&2%+z|3~aS
z9%)Kz8vbrp)Zwr6UF&IWU4p#qXitzKOjGwQyjd8Fq
z-s%)*2WXq(6|{OH52ZepU%Sl$&$zY~
z=dqWzJ$sJFeI3{zbPl_U!<|!2F~Q;)ptwCqs*`T&p<8;gU^BL`t;);W8WF(@{Q4PX
zLoEmTsP*?yHk{x{j;Wm1EYqv}5t@<0jZW35+-;@Grsg0>i-IB#3g3YOH#}%v(}0L^
zihNH}Pv`f_X
z+MYb*?bG95a&O_$|Ns7$eExrhho8jS33_N9K?ynKRP+GQJJPl=;oVlGSvcYC20XWL
z!iFZ1o_gQ#Tt(}1GE=;I{wm!SFwSX0oG3^x5b=hd&CK);o~XlAvP-HPbyD4sg`Va2
zVBat3PzjejDq$_Ja#+=@yvCKg1hF}3MQ?+-1W3BiW_Keq!TIaju`K6
zP^N(V&6M`O?5JJn?`JL6%N~cdFZ;ioy?tC%W%@sUX3m^BGmI!O;E1aU9F^i*mXfmd
zHA9=3Bcw*HLKe2_sANxSW#n#t0uRGD91(TI$;wSZCE02f(pmeg;R7%}*{^
zWUhfO57KIW-`6=ag4KS0zt`svICGxvbKlo}-Pe6RUlWm~K)Du!s21B$W+FIN!scNG
zP8(UkRD4Et_0~tL;rrH~%^J*HvYVkPbKGibW6pO`j#<}{9Z-LdWBSP`RXb!aGTH1lY4Q*QJ9V~!
z9p9iy9_3}s_P&f9?N4R1YzDGmChurgu0f_tt=^HS@znQaOlupVyK*9DUY&+4uGKzx
z2utGItDBMijK
z9xzgq?kYok>JhR4PS3li$64#|cQuGl0naBO`zkbT=6H<|oezv(35*}EL0#gpzs%`P
z`z^PnItBhDG{Tt9aq>=XbW`8`9o#IlPPe7nSE$@Et?n4-uEBn$rJ5}XwM5ZWzL4m}
ztu^aJj}8)9M0=PrlQ_dnwg(I>&E!=&T0!M7lm8CrX^lEM1A27@)vS>+2h(U_OHcNp
z-hilT4~6J()9vdzj)_$OFKh3alxldO=^R=Jbh!|je)6}{DLc;XyWZH0BXeG#$%=#0fOqQiShS@1qWUL#~?)t+sE
z9#cElF8i{g4GEF@I??JMR!8vYEw5v>W=;@L}qk`{R%{y2_mzC5CN5Q{u)GH
z)u|Av|5Sy@ysIII+<%SW8H5NRN)VwD3xp8_Az(lVF4x#!feW~CJ@!}3+uPEe
z*r#57qRDNY-JV{ko*g}_9tRaVtp|GKmkQQbcti$9vWqy+Y<32L2shif`u#45%C4Q@^P2%l+vM@&LlREJ!L))}>a3g8yFHi-z0RBLA-fZx{ARti6`$
zyJIx=1m|YjmAlmbh9WtB*4FbC!M6CjgKZrRwj~D`w%(?+mpp1W+RQVD+Pw9zpSL-p
zfa>9pP0-B6C=f_^Mqt!&&?vOM^F>Ri4phOFH`{Kqb#8X_Z(w9gCwZqHV(U0&RN)er
zlW+3)k=9ru`GQzu&m(o0>p3YRV=d)G#%)$I{FxOz%IhGqJU0n9Kw9Lk8OZl
ze5@)~!1hVhcjcU$eFgJHP!}Duu%yztQ~Hc@D4MYv>{E@V3Vw9)k%fxa09`8&Ga6t4
z%{X>f>;bF|$TRE|E82UtFRr$}tyG&K3#bZ9YO{Dwdr7lSjUe=
z=~k}iW^YhDUXZ&7bWv*+BAl2b$X#|hQ8(I{<6uuRTn>5?5nT0=bks4~ds~6}SJHa<$PqDwBRG`&Ig)r`W4ksa
zIgr#qo;e3ZP*&utoPAHXyg|GqHv{!#KT2@I_Xq3kFMsa7tKK`h)m;ZptMDTDCyKPV
z)kz%F0Z0IyKaosySbPaI8yIoKbTXtM34AqypLU^+Ua+%U@cq23i0r;Bm+I9Xa=LU@K7)JMP
ze30gSzd_kKTb9#4QHDAEOUVcuMla9|s?ZE&CJEBl0PSz!os~A7N7>Ac>=vsh#tC1x
zHCk087#9H>)rztVHnWzUX|1x+9m=gwIyubv3hfgreh_vL4MTMl1wM|Z&?x-pXcX&i
zL%Vwv#rwF~Zb)|XInw9B!(c^13}HKV^EBE)e&0^eS7%u5G5?hbv=F+EEFN-0098C~
zjFYc+flFUwVV3ibjt*%5>$TN+1+-T@!HBN+#>RnVwD_?M8k5jbW<9spq_qWxB^dN{PkNMjkA
zDMVe?QsgY<{ztx-wh^{6dpNS$wVeCrU!m2ZiKM5Dx1W0S8a-uHo_hOg=&7-IidHCS
zz_~%K-86tQUWUdTgl|3VxX>IL+;V=)?hIrvYKEs6W=zPM*JI5Qp>)BUDyZYE_
zW`_$^0*ta{Uz{l=v6tkpU>vMZ?_hb}5pLm}^67oxnva#;SLtS_*x+qffPGhk`p2u8
zF{Lf%K3OHfLU{x{D@E+l*QpMr;B7OsWH7&t*)!A1Hl!i`Nv-HWI^B84#{Hj_^2Z3X@Z;64bSmyiA?&)cbq#C!+><_Mo
z9j1d7R);YRIzkS+SccZ&=+s*-VMjAw8oVt%-DUD-#V5%m3shkwE^t~KnBiPY-th@S
z!br$MI?x`EK9x1C&5Adpj&PZC2*<+K*pjzIG+vRiC{8_Hi`>NpnD_bD-a>8R)|x;!
z_odoUY*RCFxqc6G#Ya_2H=i+sqbvNHDwPK3yMiKSKPh;)z!7c?ld>)mCD5G>u=PVA
zy+FQc^Ftm@)k+OkWybDiJ}+%K_IW2|I3f6;eXV0YWhyhmIxw4}42_+7bzdV~FPl@m
z-V694-Y8<5eG=f;7{}HRhTP&}9Bb>to_-8pVKb14<@pF93R;T1B{`9M79mz{k9N5I
zh)ed?$5Goxd$_D%73bGM$ENe^I8@2>Yn^f_?EkcT&y1k&JzCXWYgJ=20s<@LkN@H5
z%|RyLqfIKz2fu_B`2AI2&P8C(0pB)}D$KGcb<9g>LH3_cUE-bA03Ej$emH=^F}BIv
zeuJ}v@2MGxoo@oxu%JB;eIsROc>5n|@Oew9CAbo&oW5Iyt81lP8?ZiH;H)(}p}U{I
zYDV_hB)8iy*`S?*CBQ1GRk8V?WR??kmM{3HoLp0^!
zM?=0lR1Ia`ikS*9%DA1yam}uBUw*qJll~o&eeF!Ty)}=
z8OEkcxB21z3{|gn=zYDxTWR2BbBi>QPO*Bs50zI7IVJvhch&D88AA_XH8^^88XVtO
z7|5>ROm~=)Sa!-Ryw|3_XRY4;X^;0tWI*erzQ=Xy9ZeN_0X7H9%FoR{(nD9+k~iXk
zkd_du6B3sqL*iXUVuB1sJ3h&z#20o$fIQm?3fdWtg%w(1z(!`f55J(1*vQPSX?j2G
zdQTci&n|%#waJpyei0dTHt#*SJ5*hYEI!Yj^jehlJD*@TtjKAr#LTpudvr~bTS~9h
zu#ZDu=rS@ZZN!!CzJKnAE$3=Hj!2sTEIBvG1I?+fJ$fB%FYNu>yA`?+O?@OpE>>vW$hX2Tw`_GX3Us(ZqN#edSRlBmBd`uP$#_p{)Rh2CExwh5~cb{Bl9{MWw3
zVHZ@sC6R92>0ap5;0k(n?pD5po;NM!zmvq%%*O#1v*7Inm2&yx!bQ1G%y;zr9yH3R
zF^UdPGvl_g;sGZ9vV@tEGTn@+J~tojWSldiE_Gk-2kPfQ^z$#*L;axfK390$S@rD9
zXK2*uN9&{eRN08{Z%XgX8(ZV;pq+JStbC|B?`5BaFSrk>PXsKo*qNtT!_dE#!K<#m
zbd~I6n|9@=mF^1Jhq~cQHX_RI-4p*d@4bzG<7sanCg_N=kLEzsq
z*kHjS5XSXsT}j7`INk~q=CZ+0Z;)46%yLx&pHj#`Ely&b>d`VsYF>rZGb?bsi=
z+2PQ=Xo!|kh8EdYm&cykXeciv+}g-oSuPY_fX+jw5lY((R}V^cwHn#JJ#S&j41c)j
zSbb3kPaT~jkLOefhz670pGVLS0Q%{u;y0`oJ<^S^m)R-{h3JjY|F)#IE~s=z+9w`{
z%@4S$Q#c1;Ci;+VC5ziY*lbQ{*!o)FCZ2B{^hqY>gns=V`F1Waw>A9#7NFs$xm#oH
zhGx1`pO&v+(ES%db#?6tD`^cT{W{zwjFJ^UWljS-?}b*S9QiMWUcl0D%4pJZo%k<&
z`P}_y2yRZ3SY1-Ez|<20<*J4
zB3p(I9#I6{EV@Uq<{m%2p6Z+%{qPyqx1m-UJk;TX)ljoitg8v#DaW0c@3<4h|L;w}
zW1BD7$4g`dUH~7_TIO^MdnmLL6ThRCn1hvg87ooOV*Gzs=9+a`VG8hM9)v=Dtl!I7;`RJ!jwAF0}D&Xs(A#`#>Kf&oRE$0d6$=IjLR
z0L%=#&}$EKuR&v{xl`v&xQnRE{b!q^O=s@euJ%6hYt!SMdE0`k*M62(@4A{02A);&
zp3yx2<-ZADO)`IwAPE|Cdt|ON|7m2X?|zv^Mp|8UbSHj1&j&%G)Gm~&-s!tz|&!2O7{xOFDS5R
z>dhZi?-m|)%5;CNza00bY@`2OHT2w!ouC9gtSPKr&kWh?;ok^ZQ)VdE6yjW!oe#As
z70#7~ooms1<*=nF`4zTfRo%9xoK~zUvk^1L!g`=uQ*aH|6xOaBvte%=|DX+Y2Hl}LTc43c9qn1f3q0!%8yh&_|Y)7_q>`~{ADqf?KxC#3^
z?e;8uN+of7aJMIqQpp~TT4j#kG%{Xg4|G+*?8z!SnEa{j%w0k(DsGvl4)2lJS|y5J5YZAx9+3Y!kq7Oa8%-Sa2jgHY_5vR&TAkmP#D2D*q9;<)k-{eejc`-$+*ZeeQ{TwUxF1
zv6YhMmuskhQ*P_(y0t|?O;KJ#xS}b_fu=~oTpoS^&=i4cDjFD*AAV4cntXe?7TQL?
zUn6Kq^V#acDAsyf
zk)p_-HC#45_+YO>K1}D(HAb*m_b4_PSdDeC$@i8Zo563Wb0}jBNOd+Q&3v^_q$R@1oPW|t}%LK{Y{kZyRBwdL6F|Lz!A3SMg^u0iX1u_v}D
zdd*{xe%aKw^e2sdo$|!}|J_wXmJUrM**X%w_!2om$!69XfvB4KBW4ESUlD}=Q9vBM
zL9dPm*XM^OXx~PFgKadFa~DC0T~=T&czp2o#NUG^5RXsN4>x1p{A<%mo>i$US+qFV
zS4f-Mus66y=3jdzoMh5h5;Z}5E|dLj}K*D4YAEX7RuwGyYgP^1LL-z~M
zvIAlRK`1o?_cvnhb&zFYr^Ct_5vIZ-q4bsxkx2e~ld8z0A0E#+)>k#-mA|8Hd
zDfRihZ-jGfWPCnpIpVaWQycemNT>GmJ7t-nI|S8`MJRoD6=JHl*oQ+)8?+_OUu9D)
zNr2S(94s8l$g^!>*^sHQcsQohtl*!*ZGos~H!Imr{8_;3!G`1^{U?*%Od$7;3&
z?S#h$ZCT)RBU?1>?T@z8-rm#pSZr5pk3V!U7T|-K5Bw3_qczeW)V24A$G3$IPl4r~O>gs?8?cZV>-Z|G>l+7<@j7irD{BJ_b>hL&T4O2HqQ+lQ)c-U>)!8XGI3
zy7N$QJeOTVkqI6+$wH5}Q1QF$K3DxPyU(Zn?EWLS&+qh2p*L<{`L_TL>y9gY=n8!`
z#Dj&t(nvm^!8g?VFaPX(+Rx4(xqVLGgmxPqGNBf3U-|bhuJEBN^pyZOK>_q2)QbSY
z;*N8`;*N8`;*N8`B6v>U45)rOKfm(tUp&Kyu23&Ji68CJYRLaJ)T>T-#@=}!u(;!S
zz@o=DJ5^Zx{K~(7@eCijLcQQwz+!1PEO-{MxZ@nK2%al;6c(_+`F-mN?>5LyEBG_Y
z`m3Syv(U|S85UFz6dmse82E2>xq>+wL)0xEbx)N$ovyFXqEdM9><8D4;$8QM$o_u=
zZv|X8?m;vI(GQ{?;o=BH7l2=xTcKAev-lWMk>U1DyMz1cvH7
zM~F(m;Th4zR-++RUq7TSg)9oZYr2QyUt}9mcQ>VT^uR;XNpM0qV{t4*#YDZ1@=qWu
z-M_zFF05#TzcJ6~`AC^$#w+hmL3SKim0T{i=>s1m3V4(!7*f%vY;PxX5P6W4eS)}c
zI+rS3nl1aNC&X_^)=kJR(X#tbA9->|G8Wi#SzAL<fHP&0i4QZ#6
zPa-^gl&s#!w8L%G+|9J?e&r^;<&>K&T{n(6ab^0ohvt6Sh5Y9UUsyoZ0Jpm*)k|sc
zq}!ij#JAz6?^!(+mX5TSO#Z2(z5khzlSce(3L=U3)eVUogw)Uq!A_hqU^u0
zegkapMwslH=9GSQ&*=JlqOj?vV5tp8()B5c&U}_u{>$I4rA8?g6x12X`R-%C
zIwP2i)^CtlUy0Psdxzp=e^TSym8=H)lq*_nQ(z|%Uy@G*
z;s}Bjz=;d+FYCN@Nr5D1Q+Xc3C=IG+lU%EZ4Cn=BW8eA5`>C4(hy&nuvn}(N3|+cA
zsUZHa+M}FP*14pc*Siq}&4LsQ1mt3w|eiw|?6uSX0)wruZQPiwyYUHUI)cE-^aXVJ><=@>tIaSUC*w4Ck?
zb5?=7`KIp9KGFQb(`9-WJVRvhqS7y{f~?y3Ixrm+Y8I`yg+za5;hCJ^+53SxDt!ofkUsT=o49X8uYi|`Zoe0i
zGJhsKLZ?Hjws2VAob7wS^Hjb_tIJcE`90a|Nb8S6d`63zY#O}
zH-*NP@t-QOlU57fGwXLWBNMrPB{aMlh9%yX-Jg8zrL`+nd`HLf624hEU&c4nTl8e`
zy^Am59Y(7}4HvD|0(SZ~J^I|gE$)srndgf}++%KM%R5++vy=4ApQj
za}kJekG&(pov=l?yR(3LgKQws#q)V)K6m;%d&lN1;!oA5@M~@XQ&yOH?|tw5BZa3J
zLf)c8#afWXglBP{*zd3ZF!OQ!uK&Y_H8NKGtKUe`hL0vbAnzSNin8k$8h}?lt8OQ
zc}8?HU!^aOO+j`^x_(~Cxi3U^GVf3FxOFQwNc0r?86!l|wI1hYWaQXAsU~^h5KZ!I
zn@0F(iyr5n)44N8x$?;teM%x|U17yaA);}#r%+riL^s;eT8YrFGsEoCy))p@=-;3Ed?6V~hA2NjAqXTtxC4D5|9sncJ>|LNym#6Ef3lYeHqZN|I@
zB8EML8sbCGn00w4Nu%oZUsGLis#!Cp=(8d<
zcWKM+9|}Xy)a6w!tA1!b1N-~#<<3eu8NX9{VLfw$XU5vUcg_SYn&hrR)J!knPQlEv
z_8rQ#-b)>_37W0i>1xFG87EP#PYQ`nRTs2rJ(gI8GFpy8_Px3IC1S^1W2_FOXu|M6
zQ8Oc#@{ehhTopt+XwST}E{^uuYmd*IaD2kJiSaXteyQ}2-l6A}-S!Sz^UG&$#@u{^
zY_gOe=o7A+GMz1!r(BF%0vt!1pzMTm=EB11Cee?5Hl@I!&A$C8{$n~f4s%+*ruQRLk)y;a%>E!|gJwBdd_wmdw
zw`u>WJWu9hjHMp7DSh+EC`0n|rhf^0x`Xn+C89cMEmj^U3;9&H$&6|<0j4~!QQ>Jw52<+gqwgcW7~);s5yO1b(vHaG
z0q}*kBo5f?g*FANZi)%|TiP8Exy;#m5tnE~UtbI6AITRrq6OajsDr-L!)0haCsP>N
z-jL_Hp3799>^s(3lz*^V{~g9%?t&M3E-H;H)S~Hq-wm1%p(IfFS_EY+aTvJ1(-wrH
z8daP3=qDFvvFYsw=*hJneX6lqe@6TC*tJ2dx1@rG#>kD$;1nB-sB)Wj_~_GPv!_Y+
zcEh@KdP>UB1`8Uop_`AQ$#-Cx~Ddp=}M!R28I7N?vASNLgv1$zdy^0tBrrsnMaOfPcJj)
zcJ)c%PcQ4w`LNCoEc2{MXUv7JT#A>FPt?bmT@|_TP%@gQx|ub6@})$L>2!0P*Ft$S
z{aeP=XQvh#pJ!0jalFufxJJ;8Wyc(WEl%^)v2v|Oi`WFM%AffU2<%nuO|cyR1rB%g
z8g02wgV@e0coLTz+6;Hv7RjD#MxO`z@~xV*Ek5FUp?ALo-q3x|!|?V%^b*Ntl&kMP
z#E}gvB9BAlx?AyWCag}zm44zKkquzQw^Lw^;y1|oej{X>1XPL+!|dd-W_@d)VmvcH
zu4VeG11X~q`GN>xoOW$3PUba6|phPbbvxSgL>d
zo$OTl(p$$`w*KjOotV6^9Xj9>Mm?8*$k7M!zdWKhpl@4j%SQGspOUL#aq;-w>wKK;
zrmvevhujwc^j%^CSv{miKfg!baA=)~Oaxk$MvJ)`%6`;m74NP$)dkiQXPaUGr8V50
zEAQtwtmViPri}Akzuu?%VvI&^;Nwjv199$p#Qie!)<;bVeS;s+{fz_ubqcSX!lEVi
zv0P6sYHqtM%Ib{bH8y<9mZN;jN8eh0cdlu?Klm+*95TOYxMhBRJY#y=A5VAi{iTLn
z&`uNWNRC-qWhxMA&H$D56MDgCB_XbC~M
zy6_CDQs$T;A;xIZNiwN+)iY!2t6j~IOPPo<`#pT;tuY6YdA4=lyGhI9FFBa7F{EpJ
z!TMwB8Ebl4Qu@2;VUKq_J16^Owtd=;X_K6vrG?L!M|t^MpIDB}j;$?g7I(2(;jjhA
zBB~a>xd7^~e?aH7Evz9P8C=zaQmvmMYJn^YFRsy<{B7&axs9wNg1_5ivc72YzrLZ=
z{s=N?Hzt{R>q~Ooh4p5Aoc8&Clpm(76l+3~GG}nk9CKlg-|U)mi}-!VjOM}8lz0yG
z#&0g%bc<%ek>gKbv&M4x{vg~>K-OD4naumNMS91g#<&j+h!}l~!~RhbXXbS;nGRl9
zZ+bWkky>GQdALdqeJ|EtRyrQ}yN2B`^F<$+!?6EniL6IoFrDC?%!{lky>Y$C-nicU
zhyIMQ$PuO=V1g_cFFQDXz=VkB`?X|5jY3ZM{;y`4Ur1seKFMZjbV9%L+A5K4
z!Snt1io_Ab+9hPjAFqtFh(m1i2h|N1wS@E4P8^+1M+gFw{`GSTG;WGVzwt%W{uArb
zw-@F56YIyJX8f!dNfM*|+oP{luA1tjH&hmT+B+Wg=$XXg<)%^1qrH%W(E44b`noc`
ze&up`vwpOx8t~h#j}r2xY0C4$QGGAl=Clh%XSHlY9Y3>htlL;;s(*chX;fx(dC_5b
z0dfXZ6yGb=Uo@1|DnPE6>6UVS}#!k#S!LtLXP0o#4UIeqJXOoP~}0
zs!qxr%as=&X6$xh#aXTJ$zeP-gTtHJX1lN%t=ac*!cu(O{w3#mqeBz3q#S30`>+;1
zPFr93HrD=9gxPr$eAXxDW9<|0dm3ox59el%fAulKG(n!o3LC>&Vb#l8&(a(~B6`Cs
z&Y4B>j^@$j?z5oJ2{!mjeH&Z-YL@BX>l+?EPP1fs_=SE#^m%*(_1J&|KXh!{PQS)Z_Xwgulb>-PpUlQNgt@fNP_B
zjdtjI={?*>-MEIfUuht0F!x&aL2~v#vDX0C-n!8zxz|6nCh@EFvh}O=oa|nDdKtXf
zgL_aM_Mn83m9oH0QFbA~pdTvFZas1gwcMu9Oo{QmnkCm_TxV!p@~5-<2?Ne+_xRY%
zVr|S`HtR6&d4t!u>z|bO*s<>5U3OUOw9|UNwNZ!;*Rq)(Yq@%Q&TaQBOw>3E8<_5A
zuLPfc`$HiH&*CZXr{Jav20tDzkKM=CPG%ipCcR|+7<2N<58>{z)k90oie69M$H=2m
z2>%$fxBQ>P!zOsKw%AK=K%+R|3d1Ib>xG2-K=FjTufW!IZIELCH@MsoZul|v1uIdd
z&wfFd!m<0abyoIeA5l^GQuigw=@^t4
z95IQpEn9nE2zMu~o|}tU1a|5&ysH-m6r-+*1-&`U#!z-9C5xWYqpicv+psHMgf-^qK8`*3I=H`Aj)%LSTAgsm{0YX7byIdZVoeO})~pbI1^FQE
z1^-gZ3Z1Jw68YR
zc32S!YL7NTbF;1k7HcPJb9DAmIWqD%L9|aJ@lcfoPTR-+>}>E)dWGA}i@JaGWWtkB
zX010T>v=~rxcRh=SUt->^ZH0z+1YQ*+HiOJFSxfH$QUU)ip<=rjM4?+fymd3&E9et>%0(AZOB_NXg!5fUmtV1(`C*<6Y%l_!!fP4rD9V
z=V8r2JKj!IK}-2JJMxfM5P3ot27B;YP-7hY{;R~BBBpP@#pw8r0r-W8u_HY*WD0A1
zT4A+c+y3kCzw*oXj~=_@eJ|cGrT0T}tNP`N7wFA(eipoUyc~Jx#A95}D6hKW7nc0>
z?~xzoA3pWi8tyZNQX#Wf@kf7GrPak*hf&ui{ghhMSk(@7*R^@2UY)Hivt)6L)v=C$
zHK~ZQ^DtqE;mSBZ%rqqp{$UOc_bPnwuAB9Ay;24?ZatFk?Ysp|Va@~D$Go3m&nWsn
z5WLbm8(CuD%YNWt$}poP+Yf2qTeeOr!n$6&HpjfEi%p&jPwN4LHRZh3_?6YOY!(x1
ze+yY-3N+15)NxRA)c9v<1ta2N*8lX4NSMH&-kH}HoSkZx6=V>C&!O3Yvg4JC->FS*FyNC&G
zD1p{-<|_D84at=o55!SBE9KJxslkd|1l&02OL9%ew#3a|KZV-RE)=0F{}GlgA6o+q;2X@BA+MD6L7(V)yQp|r%zWtTLwKil!Xr1S!@udJ_QQn
zP%RIp#;!OzCyitG6_qA>cgj00I(bJTvK-X%n~i09r(DTbUpmcHU+Q8~!XXvqx={Tm
zJj&tXA9T+4Df0B!r8kSAeOR$~1j$fRBY!Y^zvt3aMxMGQp7j^NLcrF&uEjnvibmy@
z9r^qS4|quA+Ea9u9_T9N`bJo7GNT=m{sGLybhpHbPDD0H^*U`77p5=MA3)}DAMBY=
zmUz~{2XX0K^OO=(mNDK@z>P4w4#db=mlW7+lR-o9Rr&(*l}%5^S7b3|gY2{DRvuD+
z@uRQ6Rwcq#l@cF<7rttSTolPaKsm|z2vb&99Lr5M(l@~m@~C)W4(bR7JG2*vz5hhM
zZHbq(0H!Gq#naqElBW>?_Ry3^lLQvUqorJGj6sVj6g8)rOZUGH~v
z7L(&COvG8%6go4zM6*Yq!O5AI@Y{tIL&pl`NWI0IF`O%2re`JlEF()AtTjWKDE`S3
zf{7bYzo0P}CPsPQfF{9Ggsk7leX6C|Hf0@%W8swvxH1XIBkC!1MNvB}y!NE}!NF@4
z!E2Lo%^JMsSFV{|iNXGe%2Bq@-9Vn_B*~#}>eaqz)0Bl3?h2TL{f<_T0p$pc>_;p9
zwR_Z@$+UC34ylZk&xM*G>RvNxbr
zd6=$}?61)NEO5k8Z&}NG>kQfZUyCq4ps~ePvhX@rSCw<8ES`n+ljtmH%ye3V9$w5f
zW!!{Z&gaVZE9*TjW3F2w7+hW60KLkUxQ}&N0aLlVz+;G7FeTOo5y3wz#9)&nT<&B0^
zWXD8iHMJl7dE!(~JsWxXRMx3~#QNE+90sfXQDH>@dGQhrUpxyRVQ?@GH%A^S2F|7l
zEFGJSe2lBJ)_&{YxVzaSiALLne)X92Zw(3%6=~G;dV$76JT-BzGK;L=Vr1(BhIP={aWdtOJsGFilU({-S^=wg*dSn4>KqM9IRMbh
zHTj`o0%dvRJ_%j69$~u7Ni=?V5|L$5xLz#&~Y_(T#FCoZ(EQp0sDxHy=f=
zA?!o%=o#tov#g^a991h&xnj`o7^+NJ-SPpGps#K@3OiDip}P4S;M3D_^3zM>rIU$<
z>W)#G(q^uY`Rzf>A4r}DrIziv*nv7mlb=AA;z6+MT@Nf!a%NVXBaB7AT}G)s*Vtd7
zaPP#M#5a|3&j7u96ZF$!B#4!RKY@M8sA-V^#RPkG;bzw4w{KW1KZ(_E2W3t)a=p#}
z^-~{?7u>|l?AqRB;F<|fVlTfl)_4ecpEGlq&zzv9z^F!G)NJx`GDxRvjOUHcN8Q%y
zrTbHNyd#hDKPdkdxuZNoHBPHk?>A^3OCEWWG23Dox$oxG5jGR((cF^coGgvtxu{@b
zwZ1Wx+T6Y?-+p=*=8543s1+fRwTNf4Hu0?eqQM8Q>NEH@VXgAbh)4$aH=tebDdhT*
zZ-)fSji;ltMTl&mnBut7L$LT5q|A#v`}8IrnmV)G_c|zKhPJw+13Rxzv2EkY8$=m>
z$O+k?r#6Iv9Jq^h{?TcKUn^%jd92jJX0zivUzmrBNW@N&Sl#H;o?m$Qwy%j~-=r(9
zm!>#%)ZgNg4YR3tT``W!?F?kKk`D4iDCr1;&4ok$PsNTCaKnx>_P1$C1!MM8ZYDvu
zM?2z}(Elnk`pI&#;=o>mdS$TdY|=ar&uP`J*PU?Q^E7uOIb;DvSs?S%N5$@OpK8;QJLGmot12xaQ*Odk5g2xc?xr4Wawcf
zTOCUy$bS!G1Z+3>2o|XI7A4zoS1e^or+Rp85wG4?-*GDMTz&5<>_(L5C@9}}kzvmY
zyAd*ysrBsC48oCLRJkh))?M7}L~iE1r|ve{)>>OqpL*GpvDVtt>;8B!$1hnFDN}?~
z(ccAgMZ~wHMlBMUk(!p&SKsm&Yqik6rS6TSaaI-$eB2`^=7vu&7m2x&IM`U)G+;7v
zuQZ6rfG~4dQ$g5uwjmwAzkP(>n%TRus2#j8q6S6EERYi)qAR%@!evK4m&Q~lZlK+%
zWyO*tYVW3nBqVwoI3km*F&F++dh(`HWM+OT#Rq|h;I|xVS%3e!*E3QA23QIC2a>ZI
zwZ00TY^PCcOW3Sg{KKWm4HeqalPQz5lsTAR9COpsGxt`q4_ZIu?J|`HQia%!deSM-
z4y5MSP$Q?6sA=WPIeFwMS?Sgwj{$NS)me>l%Itn@U9G_s)2>rup;vsXO>(PuAH>}$
z(QHFOkGon8duAin_+UeIicLeA%S`>-Q{6dTB|8IBrB!b^0ZGp~_$}-S1x2ZgqPe_*
z7-P$FNLS!3BN8jU)vhcS((J72#tQ8ozPd4>9k>j#7{At^>;tb(V_6+Y^LYEY6PMylC%WQ3J$7RMOlxa~RCmG9ott4*I`J_Yk()6u
zZ`^+kT=3l2-b1w8{Ga({uvh-sdUEfX-GxUsA3V7KNd58JnP1I0^TMfDPD?7XSSCA6yS0VjI5pS1OClSuu>`{cz^>43A>lM??oWF7Zm!
zA3NK=6)7v%=#0<2+54}F3C`@@@VLEi;U3IJ{fjnf;zrHqtLbaiZG$z)Kt8Zd&z>A=
zI4hcShcYpK$-h~*@~G6fnP(ddF<(++p$<9gQ~1&6q38IX@#NMsR9mEhmn}E764uTb
zWV9J`tx61ck12iS4*esIn>2<^Ue{%s(IyZ7Jxk-noPOqIG0wHhF4L6r<99Tl1ozKZ
zb29Y|Pzuf}o&9`X5y7X-=pY}>qo6I|W___?JIzx$uQSZ5MNFR`aJYLi2W^PHBXy4T
zq}86bBW-BIw5n-CKzFAdCZCz12a^i)N7DDV9GiFaE$f>Zq_?be
ze&!`CrHuA(!GgaLwgE&wDlqf(qBKSG?v49^SN23J%Hq7bj
ztB!Pr=;$Obka{LLL4p#30^vaz!jC>g!tS(|0b|EDWYJORIa4(I9@k{Jv(hSYIjx3v6jyX4s!ik>o4Ij4PMD1%=ur9doxJ^_DV-@qt4`Q)=C&V
z>9dvbA106QNox;+8*1$X2n2n-X~!a+AN8KIqwf(b{qx7aHDTcLWaL`wIR+ZR+aJT@
zdC8ud?%kI5*ntbmzEEi;QB9(r&wU-Dn&!6lK9+;f9*3p(m#szCq=O^ep04&jTcCCP
zR0r=1|3)3;ha~|+xQOg&23U#z1lc*J01{AZA9c@ejcZ9=r6VeCH7d66Khysj&tE4%
zL#OM;roVk5l%gI7qJ+A}JI*JDgX-zKdK0J9)f+k5!v1HBz4Mz4_=ItbZ8cI|0W0}e
zv*00I7jKoj+YCa{r^t@m*~jriGd%NW8Mqwm&s&H?b-dQhd{!uUPM~@Q!4+eHe>w7t
z8`NyrGUeD+bIX=qFtldSDDMA&{@*IR^Xn1uX+A{q>$*@2zA2`wE#EfB+L21D?dNN4
zl5{4C~$Kb_TYzsOb`MwNss
zI^m-$I)anujYP)XOqJ*eQgj9RzTQYob;O>8lroWV*FzdirF-VwWsK$)TQQN-JSKc{
zMQ6@^Ngvs1&h4eKfi~S|z;gzA4w`S*6~p0O9{mBu7l7UOh*8>9%$bAU0Pf|gJ>}v+
zlWlgH^x;Iko^vbS0FGL{PVk=93!Byc8Hk4n`ps{KYc-EKOa_A^wwGbs?Qx{WKYRou
zfS1JFmuLp7z*Ct!IyCZs!{dF&oB`!b9V2KEyqV(;&l-
zJ;wz2j3`HZX1RuA7Sxz%RcgckN?t^gHQcyPr1eK!T!PLMX3RB*-IHrJrRCCkEq>hG
z>#)}QJ}CLJk0zLn#wd!Wk;MCqYyGR>!!sFCFNhhs%v$aPpWTXla?{>J#7pE&!~X|`
zI5!Bo9_t2E-K-78GRY*4CAqvq=Jj+nQiR7f=vOB=Rp2qAxHbN(7UBz~`wnZzluC^+
zgN{vPK-C`o%KC$M8^?HVEFS1GpHfp-}oEx>s0nRHs_d1p5
z`(N$cUgB6PhAAA2)dC5V?EeX+lkVXBgyN0N94iZ1hW3JA@?8g=_B75;y=|$Y+*oQ}
zEXt6Txz_?72G~?amczA&paD${5au@;p<===iHm;dbvmMU22A!*mo
z(x_6HxRP3c4_Mh15s^;@;Wrobf)U5TI<1g|zX<$BR%NpFaiY2-JN~QlUg)8tUlz%(
zCq!Q`keyGUcJWksn9e{pOR`r|f5AT>w+CtKTbyKRB-;$e(CItaW(E`u(zsb4Fw3yYAj<_Z8tF6xA1mX(EHUe$JyNbd
zh^vD&=igMXLVu)Oos6rUHRoaNWaKz{-Me^EttzOF4o^<^5(;Cf!L?Mgo{!S2P`&dFNcB8v@1dO`>j~NKfIqt~zn_76IQqBtzmt(K&L96~
zEhj$k#r!WYUM)c_UnDt-&cG=~Huqv7n|Y{47&xEb?k9OO6a&X0Uj^{++}rKsGa+SK
zHS;qh$SsjJjo30@`zqp1cd9(*z-q!YT92S7!}m{sj=PNP^gcujCKZy!i283fFo`!~
z9Iss0KEEGX(r688SK2hle@ts-gAJaV%r+bK2Ra^xlT1+VkMO3z8*7+%ao+_cF*Q`9
z%*;bCf!31W@F7DC$=s&;<~-DQLB{na=49If@xGvTi@Z%jb~3MzWW1cIWO*2Fb^6)b
zPD3Oh<1k!+cS!t)&brD1CH{T--q(rxQihnfKPPJzG+2tSh?+}=xU7JIqD6b=2+iF4
z%lg+63sjC6zLMTrE$B74)r>L?3Wbz54=a_nHI9wJMxU${Iu61!jwv8lskZE
zqW1AgPBk8s-gC-b-$>#tHB`-Gpp2&F+yCuoN*eyB(TvOfPosJJi~ql)`B%_NYEkCI{Sb|2c)I2b
z$uiiGoU#=b-(3nH(`HzEMU(#83ghj$s7j-`c*?1I@FUm7xp~MUHrROS8#cYo(9}Qd
zhB`l&8fkv6BCC`#Kl^`WM6chTpC^7kB28$1YM%7{+We?m+M#=u75S#_0q7q}Ga!yGOrQPLTN%#rLPV{uh$CCJz(sSg0CN#v36U4zk^HIN@n#1+
zKdnYb+g~XsQw_3^=rp!FBV32u>Ta){5EW2Yj(>;=)q-N`SnDR;z;noM7G0-9h7?_l
z-OM@Rad_8wcDz7nH+
zWzFrcEd2RbZic?{#PyzEQD>s!I*szcZJRpDWAGfYDAwAg^?l8~`!XBGn=&rKcO=K6
z9$mp>MeyiXj<5mX*dCYkPQGXof66mG){&RMC+FlarmX96ZoX-a<(8+gK4w(uE@&QF
z`y{*C!O3;rGS#=|by*VNbz;gI@>|;bn>>xk_}&eLf8E9#zv>BaM{lv$nvvVh*1n!J
zm{JAbN*0qP-kxLC0ORkR-9+RS49>1I%c#!oolo$A;1mAu#2de(h#->OevSv-edCoX
zXl}o-)~9bdS8}H3_kV3H{CN|4!0nT=5)Bk1PCCE#l2Q6;%Z2_vy%6aKUfh4SXDg7H
z!W2K!zCZILRp`3$tL{34ZvRwxi2|?o!k@J7&-_WZ18cbI3XLu{PbDYt89`9^s6?eGA4F1v+XoN@AMcDt<
zzPOH1U!1q+ociL?=S0)9vZ%&9QxDX(8seN{&$lZM(%aoWBe6w<;qVfPHXh;7OF!BP
ztTAO_G_aA%QyTDHQwIGHu8(?p-|a7#L6?{L$$LYk-*w9MqvWZ<$;LzEfq@>?m_%Qh
z@LoW_B=5DmgFY`Mp$(ug$dacQR&+3R
zHHh*D2Ux+QQZ1gkF814d6*Wry`oq33uDWBhwz8C}@~z{m3mZ}$`x=?bHSQ%Vmz%ch
zN0XhAY>cGo@EMs~WD6iURDUGjYWWniud{yU34Z*<$=A1eyL7G^?DgohSw_DeOk(a(TGnfqKYQAt@pT=y(o{T;}`qX<5(S?{z8imD%x*k-TZ(HGP43I`!!jQmt3plK06D+J`BUguM8W
z;{;xOY-WM>>@rwRHElXt{lb9N-~#vx6
zwQSh3$|6U2=iQ3^E2FBv;*00ps8DBcW}t?YWu)S6_t8*PKX%g^l`dY4Lv*{2q8@7w
zOM}CqHINR}Y878;B+DmX=~YIDn;%Lv!^0bMW%%||P9aALKUh9A+4i&5AGa!7^8cA5
zSR*44Dx?RrL*?t^NlIPZH>p6bPuu`6U7ZYSr1D&wUzVY>*dm(V>xh#w9|xrV4?})L
zMf}y}mp!$BsQ|31|Nu5dvK@s?xWrE6wHBP&|4yd%rt#|~cwV`Op6&h5=2;hkUaI0;c1?#*eV=3_B8~im
zS)&}Y&m``IUN?7u@u<{LtBVCEKbW#aC_Xc&W-$Nj?`1qe^%sl%sGqANzouCGm+;r&
z@f~=CGA;A}^c_9pl$E*^=u;#r?po1Ds|N2k(^zA0`*Kd-<8@0?;stk=N;b#U;##)(EQJ@DA~T8&|2Es4_2-{qS$~#
z7GNdfW9VQOS$B2Vbxl+O=8o@Vj2lGjmabK$9aP3hm8(@-`8OXr-~~8vLE(|IFG3zO
zZ2Bh71AVD?Bk1tP+W%W^e3+FQE-=XDZXcqXJeF;!Wkx8R0iuBZ?cpy)n;H-~(NLga
z5eYCkbp#@H?*Gxl&+SXsC#OmcgS8{jB
zt7bYD!cp@$ozHN@s8$
z;P(Joc>Y}tY9G8+-4R=NdLv9Y5u68O_dH;(GqgO-0c%^$sdJ-3|JI5nd6Hk{eJKB9
zId~umnVAI*9Y@0cL`R#Fms9djK}8TcpUns?9Tzg?bZm6OldzrHAeH04)VK*63*`*|
zrN%nsOH$61e8(4|&sWayAK%qbT|<0VQ?49`XapmjkJOYaM;o9{=TkJ`j+iCjl90cX
z?DPFq*}($*Fzaf;`RVJ|`Im}Hh4r}O{D9P@k0BB*u58|b)cwjY?L2UGab>S~u}XwZ
zeBY2Sn{xg!A5C*Ie1ZO(q5nufJ*hF_>{AVye}Cr7=Z?-iJm=602VU_@kB`(qbF{Tj
zMUvaQg}gcDMu9f}O{y?5#ruZae$04b@|nr$Q$L%U^vt`@ggyJ?<1b7&Ga-HAXA|$i
zd{-7J`OUbNxFt^u>$d=p7d806|J}5}F2d#8s(<{E={=vfC=uT!hNhRk7Ae9Ei2tlwHk_yK6EI
z2OJR_nWL5_XB{cQ-e4R5R*tXyA7^B|8sZ=o&(BpYJ*+ENryuTp|T3*m=d_PkdZaa?e
zCy3q_x*8|5&?;7+E%BTVVXI^8
zMlXaeP)_f&!FgBNg0{x7R=i&OlyQ6s)i7OMz5p5F#ua65Rx
zUw+|gzWW6gfL~%==^I$+wO+ieyeGc&Eo>ECILv%hjX$iq@JxewX1#)Ob
zTpyzGZV2H6kn<1}H($nSM$n^Osle_uuwytlkkjW-m4-fn(UJ5Cj1J*pZNzs4b`c8f
z!rz6xjFo1zZ`F0V8t1U^mMJ@noPX^XDt{nO5E73@nqk!DFAQEwe*8P&A^*9iW=b7&
zh!%n(U$TM=OR#flgEP%Ibm{j-z0T;_^y)VreS*=mcJ^H3AVgIS%8oD&&Ng~nf6?ft&#^j!
zgGRcnuM4VXz}MtDbXr52lbQl(PADVG5U;WD6JNAzK4{PoF8UJ$Ntq0dU?({;$gRtR`<7(GcjZ9E-Wz?#&)`f=vaTK>
zJy>X&Y%Qu2D`Hu3S1bokJNdxs@HXro4%!7?AJwN(vL%$PV*g^$C$6rR(q5}MKu9CiYlJ=6u8;mS0`A->#AVX83{S;(C
z-F;ueI#if`%A``1Z0wZ8+YQx(NSxa=1}4~f4E=SU8j+Oi<^MqC8tx>9zg
zZbW~sD|u$ceJr#>e?|o`l4$}l5vnKX><>tXH3e3E(lJmqz9*1JE#?GtS>PsMV=O94
zlOCLM3+b^?kujXII_eurEVIrzwl5dx3R)^=#|71Yi?UfQG|7f7%hX>^Lw6-8yqj#8
z_!llNn2`-XKB@3F<+^n@%l-F1xbH!d{UuAz{`M^^uecKQH|e6TWreJJGh26N-&d}Z7%UD
zN?iqa$meg(zQl9Od}L9-Qs$cXzks4CTgl4?4S-zs(WUqH>wPbm7v2N=`O4Fp)xDg3
z99L=+bYd_v#`x|nH!kmG9Ov>8mslf|GPefF3!ji71%{r`thGkj=z8?|(8H_Kz5I7P
zYhfS8Y07mCO?};{O-8ku*%J5g2Jn7E3L?OL7`07z>TUVCBL4v&YI6*0(4@i}<$Go^
zGEjd9Kd^htqwv0dO2K`LBhc^Av9C+E_V5$e=of06vP}xi-hPCVrUp$Tp%k;Dxu1Xp$FRJ5$*7
za{0su;LjK74f#T|<13f#-+cFRm+d~@sAUErT5(W&Vbf*8Ca!57;?diCnl39N81yky
z_^-c?6hjtp$Q}w0!OzRYTfTswDCLCn0B+DIVkiB0uRf#ZBv(@VW@-388&h%h}cS7dM+Z(OJa}*TL(53F+Us
z1U)lPLR|{R>;4wIa`xRWz=k}i+h6?pOmuBZy~{3eZ^$GEsuc{<4soD4P$GlMWj_S^
z)zE2?%Ql^z0^i$z&tDx;G#0CUG5R98~Wu{a{63zcxYjt03LQ*(y9=-$r#dy2iZgC=H2p?G9$V`MjnU
zXO6xh)p~UVmrAXEbTo55_t;LIxv+-cmR!>_hlPhKV+caq5-+dw1jBSQhr5VRWB7t)R_GUKAAE0Y5g47|x@L@jx#<
z&4Z*pBFcRro@ke=(zhR(d-6N|I^L7-1>!(TH`FxrKqt!tNj&9z{rmjFttA?QT}?q|
zO6Dh)x|-f}w*9%@UuyW56_~cQ5L5}GVoWCc@P5dvL5F`TvZD%Y&>N_k<`{ZO<2dhQ
zB)g-}$B-595+r(5e2ls@gtS=Ds-0G`UN@@mBf2BG3w^bg^GBhl+Tq_1w{#z5Z}M|7
z_7ZM(T8@37e>0qy%Z9!|7#i=^NA(bPu18%}U}vz#aZ4{V5Q_+d_UB7fVJUgh#DCAH
zb;pY9F5k4XT&cUUv(CKd=fhuqAGv&f>UzG&i)OV!yA
zTmyo?qQ@Al=rNE@NVTd)Y=aCF_uAm7M%i$GCe0Rkk_Sa>CH)3JXk>EHK}DlsSi8ut
z(J*|K0gZ-XZHDsf9$nB4jfVPekaB;g4z@m(15tN%s*ZMbATC9%3;aY=l6Ch{@j8~U|6t5#LZ5~NzmqAliQ6x0IkX|}_*M&zBKYHPwWI9f#>-l7
z!MD&W!XM7y-T0YSeDPZiRa2vEI*_a3^_swl`8~*`1CM^`9O@s;_zs>;kY`B}&1AfV
z^f{UJ=I60qb)MI@Eyg$J4K4W0rm{12x#m1L9TnY~z%
zJl|F%Pedrs+C(zv)I;4XVPE=w>X8n7mV7hygKgPF={*JMb2FYVezs%_C`-jxt<->8EVSn
z4*xft8q)Kt9825Hz^Odo)@4MNHvpr6S*bkh-57$Hkjq+eqgm%ISkH+shCoNtz^sm<
z8pf2dobc$&y;9m+Z|PfnkZ6~)V{HzPFf7_8RB%l{E9d#_=~Q!`G7Wizj$wL8q>H9|
z1i?t({)}&N$~TWNQ!oZujg?zuZH|kH7;CeEyk=q5=9s%d*
zsag|fn}d7E?V{X6)(zY%c?~$+c*i?NEi95J2_A=Z@CylR-*QpjXI1YkXUE%$+v05Z
zTOolDr&;R1Txm*0yE?VqrcZQ`$%h%kP{d?rA;r)!e->64^=`t0;SM^eAfH20l(?(y&b
z%2!9>CgIL&b^2f#DN#M?0w)G#b5l>6bFYymz38Z5Ri*68U297~Zf+G{*KOb`b-CT}
z@L91*EbGk0*~1)P_CvS
zN;`>%bDgY=AQ>eB+_Evabc@R#%{X~~N1qlZ3
z@D%QyLrNCEh0QgC-A9nA6I#omfw)wXT`0y^UiiaaT7e@a;I@%@5&rtH-V$BYJO!@+
z9j_U9PLp1MYfRuitpyAQUt%1cK8Cf19uTaskA8
z^v|Q>sNmt^X#9-{9)8g-8v2H{(HROodfzZwH`G@P!!u}m4&x}&;WLu~w-ROy8BrpJ
zrG|61JZ4H9(cP_-?|y+i^L?C3i^Dj39;3=qx}UMO#=bB*iCyV-<2Le6Gm$4EG98ZS
z9p*~U4*PH3Yof6iEoCxp8{5edr)2X)WHalv!*nMRCq<_NwJMJ89Y&Zh?$8Zmttu82
zWUehK_MiSG!^DW*VLP(P_XIUDhLQhV`dl%J`nDVWqeOL#bU_&ppq^w$27TD?muV2W
zOY@E&Z+B$%#;cKB)F-_qj_e&KhU$iiQMxd31paQpUj+Ul@n=9bSgZ&3RcLRl%Wh%7
zEn&`1`|tjj;1hrieSU~Y^qcPxys#?6#@7mz1Mf%hPIL}p7Kcp83bujqn^
z7lHO*-Q)*XJtq~e9^Sq2ZNU4!qxU^{6?FFECg~}<;_#l!77IRZjw%rjFHj==qme`F
z1+oBOX3FYB^*#q*8^nY}9VG0bOn?f8kLi03RUlVJBZDD5+lP83xPvF(lav3;tBa&_1
z>Z;V8icj+91IyBoKar<-6skm7=?CvrS
z9)0Rnr-HGlKr>3*(ixTmJ6Pv1=er#8c{SGdMJ#^Tqg$xS!2g+=)OVv%!;tWYX1yNJ
z6F@B$$QprvqjcE6_#1=2iplI>{C@DDO^J&_K}idE4SBh;)+A&YORY(=hSsji3CLM=
z-UMPwO7cKGcUo>wO0BQs4xiIFbistZgZqNm)c4Bh)QPjH=Z>%$r_Ri&|3HL0;#$;G
zhdWUjK{-p5y2ptJY#e^`pD9=wWTcs2Qh@e-C1a(Jyn>U7&K0#z<~0jz(Kott1zw){
zlezttt=F(VxfHLWQvV-OT`f)0JWBMxLQ+qhte@nWACGU_Pgv?o(B*=n@t`EAI0bz$
zsH9uX2+L5kJlW={UvZDlv^IBX*U&2|q2_!cE2crRO+d7XU~pPdLloYzA|o;W+G2)9
zci;R}xc{k%+`y+aQ`9^VYQ7or|EzMO9yU&IPu|WMEKb?tG?$Mb*yloO?0t|7`+hpSU&XHMRCvn+uIVF$
z!YCh@Tb!i3b?uQSaq3qLT%*o&U>{r3
zsF(Iv6RtK(z|O8?(-(i*=bu~Uy{@Kg?Ch?gtktpOYlilLV0A>EhOB27f~^iuCo|Z(
zB3!LNNA{NZ&&a!P-f`8pFXoHcC*;i^y?}bEGhe-EhL1rB^cEgz#Ur;OVv#WvJ(IFT
zo;f-XRt<$K+CBN|2v6aaF~&iI%8Vx_C#P)%t&TEYUd|vle~M7Z%Ai$yz2
z6Qgj49X#JE?1lD9o<+V)*b+6Kc~g>)yudYSqdY5DGLzQEEe|QaAf!6h1(QcymId{vWu{^Q^f(6Exe9iUuv~R8!MyMk@)cYz
zvLYK5b6m-y74T9E_?%HzEm%XD_Eq0?^~37ZO>OTHwu(;OU9gYc(1?L+Q*$)47l|s2
zzBoLf^C|&P>5=08HJB>eG8In~_iN;Lj!@?jYv$rCL5lYb^VRP$QojAgylb#go1Ip5
z)&i;{yy8^fvP3}pc^7>7OyAq#|2GmEH=Lq9Bcp8|-LhqBPtrd1J?lt#8;q7`Hh%@*
zK~zFf@5YS-On(8jjZ*JkEmZGcG{esiJ^g@ev|FRpv1PVJynwN4<8QrM=pED(SqiSc
zo7tZ15!$d?YfIPif@`=?#+4*OriEKy4Vc-3;BG
zi*_VC+u^czgBEx-J?8DnLaL~XX4Q9X6X~f(@l;g3$j08r&D&{0reCgy@xoIFV+Jnf
zP9@7@ku?fysaX=x`O#jCz)HbCpOfs9pPaO*>^bG;*bhS&Yjj3zzj7;aj9X^NELc-4O^RQ
zOuvIssbRs-|0;3$e7aF?d@!%}!xMsY=s$?__
zj4-AF8SwK~-xwjrhdd8FY{BrEO9v+#ig*TQ*aI{+b!1e@OM40{*0rWD93F_o+zL)a$9L$_7sdpG-t=B4Zq4Digc!eA;-h}>p+}knjYQOOw1QE
zPRTPTyZ}G6jwH+254rvkb^3T0`rnc2`07)h^G#-8TMUftJketK65xzQ2}6vl9{!P_
zJAjH8Pzj7th0H%T{Ps9qLus5pVw{WSsAmM7474Tz$i-!%LYp6Q@yD@03Sk%fe6Qu<
zMsB(axx*HRtV52An;`epC1eu>kpCPT1CIS0VQ+>r;$4N?ISM!mV;l`z^})U~K~Re@Q=dV}0h{
zm^FA6tWWaPU$8z$_gWqwIPW%{p0g_J^WE+slBkOMai^W;Z6OG3#LR7u3zw7`yQe$8
z{->7aYUBpYb;-xPL((yrY3Db*GSl`ZUb2aPy!Q&_@NoUroNuhMI&V4oS~smeaDjG1
z>zeO>bMDE%Uq*8${S|qx$4keR9Ge4Y-+^rX{x$c{{)z9fU*6qo$r(8NR^4F#>@VyN
z`PJ;dx)kD{ebMP4%>G+I1MBU!IXd1(#j0Pe^o38fuAo@>K_v!z@_*Km#OQeLW5%Ox
z(K)^xE)W*D2@5*E{{Ib|sja|AApo2GpZ_*&JWu=?`OivLg3cEe%mWSDRh1X|p<^)UCDx3!>;TRw5>oQV^V@Hke53Ak0P9jh
zSsQXn6CLl`-$%8{ijVF~eqV|J-9irO@rXoB{`j$g4(!IWE$lP&Y$={)ZGopd#?jM1
zrK?Y?l$AyX&E5>or(^ESV=oByiA^FZG0Mre_f53HermX+ot~V6F+dY}K^#)f1XPn9HQj&Jd|n({4yzn%`y+BIuBob$LJyO6Q5~l>!J4r&`S<>-j$7#$x-;n!^>@L1
zwKgiJ;*0z<{_$9UV?13GZKY(lMYg&`0Tq{mbTkKzH|l&S2=di8jcsQJ46@sGmJGaMT-5(y09~Y{|IyW*7>i31Y_k)c#%@
z6M*4Q_o#Oo!*3ozXX1a3K>mE9Z5ypAGFUpT@a#!`|7c(=dp;Bg^{;O82Q;$4>i%$)
zMizkJkfQ`okFI4JjrCUK5e7YJVeh(myp0jcc$3u8WkuZ>@9qBahEQ~W{E=8@l&wTL
zg|njKB{fzB^t4h=9(qin$&GnLlaoJ=SN2}AD%V0{!bybPK|7=Dt7&ob=*N5#Jtv$)H@s&zz5xCY@`+?SBE?8@a_F3@ys`LBV}Xh#++_!$h`l`I}
zHpeT1W+LQ`SHE?p2HLne`-w6AVseeWgFyr*AgO43GvVi!FN9E?&J1hH_j0mamU>=J
zP8?n3PHmIBa&I?2iW;%H;Gumlk3iGyM2k#@gZ!Xq)!rDWlt{n<00l%o0(-R18H0Q;n)i+XC4K
z=Lxfjr#zbe@!2VQDZlw0AJxIT)qwSuf>5ze6SNMMc`9@%wn33WpgJ?or`R@-ZZ~<)
zHx+Xy&I<~np5VQfnqps{4?J6?VvIFauD+j#)}OR|+jJJ?)2Xw`W$gciH%hi(IWk4tm%50F7FGx7>zz
z^#k9fR-8vE*P3Jvw#H>F?TXIeY+D7oqqO>h?jEN#N%`f~3;k==aA*7hmxUKd-ZZ=4
zfUJ6s=jJx>?;&eJU|gI%Q$XxwdaSUz2pBJv`slZR<*B0vcE9h@ZBt~8IJ;wUFRI$^
z3{oNU+Ff$lzCZ7%3sk#uV{BNBu8j1QtkvOJsA@a6RvFz(xcfIwF
zoD^FL_N7PaNLm-9))~cmd=$7VO-jGj*8YB8l&#QqE?3Y=I`5{_
z*Su>_GwqSSYa4=6Y(aRs`RFbw$wn(Y;phfKij7uyyFj0lXWgMz?i)-r!MZeg*5s5>$l%E2rp`Ss8ZM{Z#F#GV1@`Q?Ql#a1Q7r1*gwhROOB)xF>()y8+)3
zOOu=b8Mt~4S3lGSt{QPQq?TsOS%q8H=1!2D_K0+nn=Aj3WP@#Fm*d5g$gSP0{o;XQ
z-`mpK0!i1t&38@JBWRoa;~g?Va-FJVxl=yYb+Uj(&aK?Gc>%efJTR-U>nG$(*sDe%
z+(5OC=_Ei@U{}g8?$gDLdA(<46eG#VE3I+#C2-scH!`q=F{9cYKNe_QCw3#VVi@C;
zL47WlfO3W@RzXKk3FF9dYYy8*=CYE9F6sUNjiwV3S-)sy?G>PzMr`jfUzRd`QquN*7
z9XY2pjy1K2ZTGB*V2aP9dLwh<=!>vwnemSR8h&_
zJD{g>RvnkG?~@0`&<^Is2j|zje4UE#JH;R3{mB8Cg5v-c-9gp|tqD9T(Nc`IHD`5&
zgsAG|=2Gl^gaJG>0trm-AKCpS@FLeWz1TY>I=wZn~42MJsG9j
z&`a^N|JPm&)C=^Oh_xhtXtk#a>*6INAJzqUj8XK}gOEkJ@HWHh1&;F@AoKs$Y(oE7
zVW+v!Ed2AKxnTVM`IxAusyuEkJXkR!w&-CYe%tuk{_&#vY3p9cZ?+OCD6OD1L|{@2
z>R8n_^wmobMV9v2eaUO-L@2DqK&ftE0QL#0!e@QQj`OGutsdVzSW|!T{NFTYTcQD*^
zU`%=zeDEaZq12$%l6=t4{HK~(o19z!2a(xH-Wgqcb^UGc#qRB4P`L>CP>4I2kni^I
z3Zf9io2h5M1V|n5Xhq1Wu%)d(BtCctZIl|xmKmG0h^RPV_
z5hfKMsFbSQ4=KtnPPxU8H}w0PR=5GL`wD$gFADHuN7nEmu7{R0QT9};r{EV=ubAB%
z!Y#;S9NeG~*JBn`at#Tp>0HlBg~u+q=H#&#;lrW(sAH4!=-_ORujjf^mz~(R={0%q
z(;nT^iK$jcL66pT8|HHx&(^}z@@fP{=puIQ$`xkP->%Snj!_({rvdMVe4AL)V_|D1
zZ)V2AR|PVGnLgU?kpmYl|)C_Mdq+Qb-&zF
zy@c8YhcTuN@}D@8B9PH?L^y0Q`AWtNlCzO_5jg@tJy92@KKp9KtwB>yh=w+e7|Mb>
zWHqv3nCUJ1SlBbdAonG)iUv5{0)GZ-ub%CGS&X1>(HeYP!bN4j!5$Hsd
za~xIfq&8Q28v{QT{0^BgtPlGZ@>)yvbTO1xJC=#I?mZ|cUjNr|t7IQ*Q|XQ57BziX
z`{)0Uym{}v@Or_{oyCXnlS}FgJocLizP}Xyp_aH|o~Pxha#P
zt#aa%Z_%zlkJCT?K$UX(-=IDUm75jhYT&VJU>PasQFqO|QKjU5yH6|oS92cM2nKdpL)!JOpyJTn9mkPg1Gm|$TgYB?N!tTJF
z;8~e2CvNOXY8-2WuZwa=nkOgj`I%^0&XelceZSx46S8)LkC=I5)a8#><>8s+&`0P^
z%r)`Zi}>HwHfSIYxK770U;6rO@_X`TG`;PXHy3MwLnpC!H-9x2)x{`koGE$=nbPYX
z-=t4~ms@xT?(vM-T_s)IbW!oNg?AV9P;`=V_@x+CO7C`E+;k6oljt6e6y8(QT}=sG
zOg?KBw@u;X#98+Sf5^>sqo0bn|2SQ5%s9&q7@U_k*RSf{PqK>32mcbt%)~V-K0Dej
zzMpGm(-fG)t|+&LKHrbIs+0qrh=RSAWEFeg`3SP(=C*{p56i8s!w72$QzcvX%Z{O^
znXm_d8Qoeh0ObcA6p%AYsOR>c?3}sZSOregOOo5A$VkcdG>;O{0ee=M4}C+?K?&`}6zEG%o4{M@dU;m^Y~R3i3&*GC0PpKjfRlS)tVNA6Uz3he=nsejaM--l??i$VVNNGP?Juch`cnOt_A
zP<#|Si6g7!)d;W7hfK2Ybi^I_i6V>n2~Bw?2ki?uyWtoK#t9t=G$l^d^y%S+HX1SA
zu?Tc$ju6!Ws?!4sHMj?QA<}HP=I#Woy8iLNQ4{4;Mx3jQB?{VxJjD~G2~BrGzLi_c
zXGr!6+diu!>Y~;U?~zd$^VEF(3tyW!yH*(GiYdXPU!PAtpjz?ra(Nw9O41oof7yP=a8>|#+T
zVsbHm&@CeJa&|0
zl)(eM>spgi{O=E@%#K{8ZX)qAt2a4@^uli;roqSyK|)rAL^~^22*^TgF!&w=WFbiH
zB;kq1i;Q36*&2$>jpQQ&9g#v?
zo>i(ok@g>QjY3y=-f1aWh27{r&k3m%3&*`?k41i;mc2P6leyOll<(ck5R=eSybN^%
z7=6oRHk5a~96K=I6?s0@)h9@n)yQL)_Q~uMfg0(?M+4B$zB-|)@NfdCS9!udt9kvW
zjhyc=ve!|zHHV=$Buz4clY1zLq7l5ouwK_?Byg4_mYbWxM)8w)Nh7zkAQJ6}G(AW*
zWz6>IlC?3CV>vR;2+7*nmgD(?Eq<#$Y^O#)Ic$l*uX?dU!f9pdzGd+Fv6Qbza>vMt
zLpHmb7IOk6=T=B#`8}=2V#&H)#
zw2@TuXMZlI-x<
z;3s59BtRSE1YPT94!5^=zkIo$GhX!A@yFCWnUp2-DQU|B;*{yh#-C`cv+QY7O+lxI
zd)zYql-szWU_wQS>qGnP&@z4(v)zc%zqVics-_oxpGsf~n?B9W*OeC5oW7J?WNUYw
z{<+<0?*mOQ0QCsuw%S_?+Zjc^8A|77
znp0KPB=qkDAF^I1UHU%BsQR`Ipnr`tL&*xeO`}IZ
zbiQN}(08J67&0by|2V{|bzUb~s^0F!f1pkjPU%B2($pqVh(`QrnL%{M-r#&xYgYUb
z4`4^9GSxCkJLGZmK`K=3?+aP_!zGpp>-R!3AFOD5nYl-_3|)
zCbNL8q0JGWPb*+r2+DV-Qt6RPhQ?$EZ3RA4J7ZjR*~Yo~BVR7g=V2h>i%*jcfn0dQ6@CuKfnRad>->)wfK
zKsz-@BmwQr%&3A5vmc8T{4ue^i>bHz)ctQ|b>PfaWtad}^OezxQ}nVK@k6e;77hGv
z5t%v5DrD`F+H80DS2|~;Vo9UyzZ!uVnLH9+apyS7aeX4}e9UPp>Szcc?0tJ;!cvopG>VvDTtb%-`jz0c?fBZ#(wI%)oRHm^9oJS3^
zzsrW4zq(HH%9_xMBu=LlkqyUI17q`hc={fFZ~ur?2+c|$f1E%SM2a<6`_UCdJLx0<
zN6C4F2CY#Wt1|}Yjq(KNjeP6ik%AfS_uYF6j3G{DpOnc=&G&@lMV`usuWOWCJ$w23
z{28!SAPYzJmgkR4p;*VfF|z5*cGUF6_Xd0)y?s4!i#J8vWYZHblcynh_EC(3n)TKg
zQqROPe^TT_=(L>RPYmTEdp-uWLG~rLDXUw2OW*_~Dg{?m$N~j_BlyrhAR0w5qIu^m
zLOxa2;i}Z2`h1ge$3e7epVfUKfVC`Dg)}9uQTJD1Zy|ypPi?t#MYK~nTYWxo8^99{
z3+cEGmfDV`ZIVQo67#@O@Z-{)LCN|vJbWh>?>+e5cb4O&7#=-I|ye1ye&z)>_3>6GUExjR|
zu2txftLY*ln)2(#F((*gP0!DNR}75>1r~>&(1=4o-`QBf8yw4tWAGP-++P9{BG(;z
z0GwgOPSj57nJC8eOvH+4<(9HZq|rnagOC@4_1WRFg^8Z6Zp5v_gG}cQIuSDt98#>#
zb1sa*@41d4W&v&Xi$%}dPi
z^0Aa
z7Ty1#6`a7$Zw5v%aAcHOPYjB^O>QY)p#I*P@dmWh`OWIOXU|hJo1
zFa;~nEW=8>IcD%6*luCPH8ua>;q#()Ns7(Z^uzZC!+OflxH%>Sk{36~fYF*Z|Bjvx
z!M7hS(3AAuj0*@pqgYJMXEb_}D<^8_|p4f9PFxDaG;$dZ`KJRDJByeQM(xj_aK>w+J
z9dsPvr}8+or~LcNI&g29-PlV^@n4WD*u49oF`ti{C{2Wi(Vv%0w7D8HL78Ne;c=z?
zqa5~|WcLWw8V8SB%0i1qJuUp1I9ke|2)xm?K&|&f{zWk#5WQCW_Wh2|3bfJFGt`R=
z+jMHk%-&~|_Hib>Y2NmcQ5zV;#7v9^z`BpA84qoB{FeWB+5ow;zz6+j=e+S&_ug3S7
zIzBvUYDxR;@!b!9d4*qTseg#ZN6#7_JhngZv_acGxc3*x$J)cV*JBp7yxFVg%~1!v
zI^Mhkx(j4OFpC@?iTDSFyF`oNMvhyILUjhwq>S;<7Tkuj$}CwwJ>9q8m>z(3XMCZr
z)8cCCHM@UsHTlfN-wJl`rcSe%-)Z(bb^Ow)0XYT~z(bWOztf&({N-
zPYj~o?oagyxjcX5T!GoaLC*clJ3={UO+zYgg=8`92Rg4)kb9Lfgjcdgp_mf~b!%wHfIjUU
z7fHLJZoV<3!E_4Lhv5CJcU*veRUG%zt_c;~Je86dL-KC9Uwf>GD9ZZ$6#MZ4P^{cV
z6R}1uYrekm{HsU&v~1%mi7GA2J$}!?vG_2SV?2E8c+k7;-;ssGl&sXoy?)`+%%|p@
znqzzP?MLGud*QKQP@P9}b{#*`(%gLfgZxt!C)C+@UM1>Flvl73f1YUupBiTj<`X6j
zzr?r_8e&%~)r@JMAz};Ftm~O~4$^2-2D#$$V$%vd@ZX!Ak2}=|k_g`vZwiy?e`uGk
zaUu_mP{+$H(Zk=K89(QRIod}rr9PFGh0$;cmRKir-+)%xfrw9Q)!2g>r&R3(#ohJO
zsDhtVewH9k`(7N%4+qbLe1Q$7*N$SnMu98J{c&sxDp3*b-&mLeok9qp@x%H6%sKny
z$N$iIjqw^uR!U$M#)Ndv{PO)k;zPD!7(!FxBD9O(G
zVk3!<9>9NhO*>C^;!@kAik%n|blt2!c%)d!d(ih8p6?|nbPu6@HMB$Bq2z7n5lkBF
z(z>KokLDa{Aw1f3oG^-ZsDD3wLb4uFYglB>(m@yI6hG(fnJ>(tl~0qjk1COGTvo+?z1~_cX)}
zn41-y(!!a9d;j>9aIXt8WzMs|g?pT>n{h(&1^#V5zVtA3%A^UPGnuNct8>wPKsw2)
zJh|nO7ME=?S0!=tQZ>dEJwtbV>$0Ecr3)UNNf5PrnQ;tB=3;m~xHwZJWLsSyPosEb
zS3t5P-d8rYE~dNkM?{C!bEsU=&Lw5CN-U$=ZviaFDqp;W@gj;xT&FW5ClTkbP=Fl=
zdJ{@(^T<(^${ki(Ire0Lc4pV9w3Ftea_wff5+Qtperi^7OpvR$ISbHOjR2kEvH5D{5QE7#S<
zv5h!8vD4@m*tEBFBInbaX7^F@%ML`jz%TG81^1({iwxJA`}e`rX5!w!4UX~XcvHN(
zhnLNsjg{wiDJ$PP3H-S^z_Ajidhv?eE@V-krMAa!VEW#19*juE^fQMD(^D3XdWtj#
ziHktxelOP*KiNMf=*Bfx%(gp~)(E-iyX2aQ)*q9x7X*Sr&h$HS;*X{sp5dF_IPc(@
zGvvqkSiK(}m4S1*YCS5YDp(A8PY;*`=Z$uh>V|;Bh>+|vB*)0!5V_^ab$^^QZa%aY
zb;*NMY-h-G)$soNNw!_cJuVwYzn=n(CAd8QUJqjk8f3ul%Vy6{v3MsJ|!}Z
zXxp-3PZ(ER9(qJ#Z5S~Fnq@^TIcD$EL_bj}WC&*=-(tjvRSN5IIv@aIK;`L
z{aS@@Ff4m!9(GZ#My?CJNA-wIOZ``>IqjvikOwdQfxIJeZp~IkO8vi?1ggcGXsl1v
zC}XAZ@55LlG1j1BVq(UE(g-*GUKg4`S`szVQ^kdZg23L8-~mVL?gh3Y;|_G^|2Qvd
zc4A*l=8KNfnWU^ET3$F7k)>Ryag^
zZlE{Nuda{QVITTAr$tltSruPd!{}1lor=6td;|17+Tc7Mxpig97}o%KaL&%Kr7=C0!=2yPo`!
zXsQbo@W*5|e}T%4<2OTfYCzwnj;3=lEJX?jrJi|Jd9MIaog?l_IpGj97x5Ul^pI~KrwZT3Rj|6j
zmLN0Hg9v({&D%PI=sNUn;<2j~>YB_z*6y0tNB2{n-)*PLavojvFvsai?Ya+gACl|J
zMDu#Z0>sRkc-*dqtum9VC^=qISR1iK()GP86fR-5e_+hc)}%=k4>|RaY?v8`R$I@W
z3Dlj5c?@ycz=dQk8nm_i&xQ8&mJe-W@oCuhI>*hb_2}w`ZT}!um8q0@SI(k&BO`XK
zt0@7q?u?b192_E=6>81B<`d=W?y;)wXdmb{!H3p;7E6+Npw_p4Js+agB#MCCBjz1P
zkuxLCoTo?}oBzB#1|ywzg5-{^w8n;NTfdCqLGCwd)tRm0m?Cu`f2S(x5GC;AuZ>oW
z_%d@I;$qF^2Z;-Vw*{wq9msX{_xJN*Kb%27bve&b&#!*aPhoH-34|l%3yl(gYYI*_
z*)XBE|97HLYhY)%Awl);pQ*Hez;i*1XLfs?J-oP{H>3ToWlL!7m%vMh_>4{#as`7s
zkzV3A3@srTN$Zn0aRD!$E(80J~^3t0a*NmsELQQ>Nin;Fe2{qy6`t^HPPul^m#pmJB&
zJePfOKU^6FuJ%=2X{riY(+c7|=!}Ve0?#wf>71QxuQkDUaHKhBZL}tc)|pBE(uK&v
zh#ga1|92Im1MgwWdV7;(Zx=3J
zqmzhs+A`v%Ti0wK_}m)`&+AMacn?||!pW{Dza~1Z`WX1}X(;VGJ@%c;z7^vlk3J84
zW=7rM3RCpZMJjxuer7oMmI;-d?HuwL_UMelD(rv>yI>(fF2r1%ZANJ&GiqZRIFjc5
zv_ogz*MCAQHh?-d0lcohXLx{Ge@NQ(uCreZgtR)cO2MO?AX5P83BdF@kxrjr_YOH{
za$)wM#V>r#BO_Xf#~r|6s&zvWTQofS2!rEb_q<~O2IovdPEnrVLRF{Yq3KcdU0v5t
z6#I9LVVPV#>+gZLsZTF_oZwv?p~NFp=RCg}yxN?|;-dqhOORbtKk$xXPpwOdY#$u_
zONw8^M>NNeKR@^HVGcXkW#=OwZs*W0>z^UXiRJAIkB@qIuyYuiH_={S0{tmbA-k4#
z3t}qor}bY7t=vMzdZ)@x7*Czk@Fj2$n#1bc#|Iz2>0O=ru4x**`;VXFr6Mc#$KZhy
znP2~BNQ_Y0zvQ+)T)X1}o!sE=70hdWfJO}~(r|TUKo^*vaViW*kLV;U>^l1uYR3L}
z)w&IGB+XyZbSkHluTy`x)?(DoLhYkHd8`$bdf}|ch$27}58IeRYk7*7lnuF)V=&U8
zKg3AKFw!>7z>%u$s&Fm%itwWQ4T+TTwRP#&Dt%UPwYvMS1K+ZLPW_RsW}igwa822qY%o1d@5x`O@0}zZ
zug+Q7FBQ&cR{P98t#7D>Bu)4YsqiSUx}bAF21cSm^1{9IJ;AZMvFC{^CE8GS|K0W2
zMUdWZaIed@=yCpHUl>=wDr_j5LhB}frbt%M{1vx%D;yffLXUh~DLB$MZ+pk*&<8WLVq1t!Ej2(dt7qM1UQfQPu{!;upqI?l6SVtgOI{9Do9d#U5eGqUKA1PRj|{#{
zv%TJv^daaHct(@PF{n?|e^yh}tY0TzUHp4$<>F7IV^H@sV_F4Wj@)wgyS~~0?Fqa=
z`X~YW@5uss%aNB3FFr^`Jd1H9a=;-&t4^_GRfmEPzd3HZ3!+uOQE3vEhS}TTl~&}qj_e&i
zWj)4FbvtltYs?3LFI~6SksfCY>2VAu8-4$fzB9}I$JLm}ai=mhTOXRx1pDU!d13L4
zebz0u7@N6(TId>IB@Kq{S8jQAQ@^&8G@amOiTkcTc28d_$w41lXXI0x)hnBkg@r0g
zl3p~R6CERaf^#)(e(Bo3-(MstyRZRXPl_Mi1o-Mi+x)&d)qBI#GfM)0xjeEMa^ah1
zNvA{xg98hkn85tHdYg*L0qX~8Q`8>pTgduB`0M@T`7&
zZTks}A?HDd8}O@$P`GJbUKR9!dP}8+1MUXPE}TmN=#WhM9?@H7<`dK}AnYUDMvjh7
zRm$`Zf$fTmjiNVhNR?f;Z-tJ~PSShA^Qvddj3y7H17J0>`jPZFb0KNl!5`capi_)u
z&ytR+dG+?UQTqfVWha;PX;sLp9#(-Jd3!Uh%K5W6J;%8}a%>M~20o>pnjh7Hu0^|#
za`xrWnYKs3TVn`sdc2lq3oeZ#n`Zm=;Gflgr+t=FOHg-rk{yn$asyjbVY_$e&G<6!
zfPyjVe3u3=#+4Q}&XE^_^%{7xt2`I=eaD4?d{X`5|IR11J>wV@3`dR>pa+jw2YOp;Inm>In&(DTjwT}Jrg+8ekH
zZjtmx+wdQ~`Zdccy&?>|VU?_AGil8vYv}73g%;ID$X?VktrI+z@Ec>QZu=|II^txs
z&9FNvFzkGcC|jYT6~|fbTYTG&gGR+0uhu(DD&^P>AZQv7&W
zIak|MC6R=z;9&za)i-c3RMCGi0{Jk}t~F{I=z10Iw>o7eQd>08wsq9*X*l
z3^GMBLsZT-$|x;HKC%g45l^!hnHmFBNgT`%myQx;n&uK6?X;Sd*)*Q-;K$bVZ5jRPEJWf4}+pGCfg?v#>Ides1p34)eevCYFS4-E6@@}eAJ
zpJ*K+I$pKVPbk<|P%@lH)sFZETRzco*yuN}U8L@W{awIY^WGcO!Ov~AE_Kt4Jc1Bm
z6s+O$!un}%>?h0YzWfRKO|VlQc(lGY_@k-oCKl`|pnlXIwC|ho>#F^G^6A+s$tHce
zKR`jK<*OtURkz)#>b~IXrPAMsXvNnn-0m&xL>@a|v?2xOc1CWq!g}wQJ+>)w@*2bu
z1^j>&UP@^}XCy94wPb$z|JWMy<}FkGI{4(HQte(u&)tUGm9zLuqGU{*iT0tosZt@#cB?#WH#2yws$-?KnD#lX4ZgLk`AKfsbVdCI+C=hVscsv(Du;TBIRU9t#g{I%>Vc|l
zMP`c*j&h@22mzF4;Pm3noNux@EU2*L692Cf=*+K!s<~rz$f(Y%T3O1&uh93hoW&Gf
z3|k7bht{e(X;ciL{K!v`eEoAL*p?}0bw{M!g9QY!E
zPQPtFBjS6IB`HOW-5Kk`E|of633;(a?J9Pwyc(beZ*zD{j+4uZr;0HEF@8^E~^x}l7GmvK{rCSe^Jg3NmWz4jP>uIOL!%~pT
zOjBp!oO=^d9qlw{sr_aS`0U&2jB{?M8Mp1nc?|f80>KdaHt2}GxF%To
z=R)UuSq@g$Z!_-N(Lrm)uEv~NZvVKyby!MCUN4)K-G2|)@adtsl~}+}NFhn=6Pm>8=TyaoxQxPy%6VLaUN)ChUl;l?}L#gr$C7
z?{ns1z}nBf-|y#-Vw`!NbKd8i_c`bN^YzxgiOe3dL1yX?!wlhB_X5jfMefpTH8{-Qx6XmDF0
z&X*&_QXgxcfy{kd@Tx&muHFV~-*WNbx8b+S?_6_|_tGQdx#-{(dhP|L<;7tn;D|p`
z%@jAZw-w?hKeae7$Ez#W%C`pvNaOf->!Q(SV~Gx)8{On5%#cv=}Yy6
z)X%@88hz+#x>-qHi^D!foz?@RA4CoxEKX$?Tun75Skbx&k=JQ|?7@U47kmxQ3!=5g
z6s)-)QU;yZbVfs7YYb#>c=7J~{nl3GwD$-ia_79jpG4$~3;uSEt8s*oW-pDyty!o$
zLivrKJ~-y1sqR*Aafb?Tm#ZT8TSs(=3oU}Ur~^m_syl%**1fF(x#=pBJXq#`dv_wY
zrjr$`+Q!>!desVhsI;*X(IJLso)MlyT!~SO_>k_|SLqBRn>$&AdN@+(Ge8stWy({O
z6@)wSpZ!m=cDxq~LhS$*4Ut%gu
zF8D5M+BWsWq6VMEy%EuM7m)Rj7;$75BqQTWng<_HD|*@X9`ir|>5Rrnqa>Wc37@1x
zT0_j7)QY-l(kp@PG4C3dEmJ)Qy~3z<68&A_dHLZtu2&hBX$HKp{`~*+#@W4yR2cBa
z(vI*O;rV_`Qf3nKeNLGpWi=WH{JQk4GABPYqU&!NmL0*WC?i^bCfu9bqZ;b%+yyIh
zHCvTR%&}3|iuLTk*w3{oy)sl(tZ$iJp@~)k
zR(gaeQ4=NS>Tji_lSN`ti-GQ&z(3@BY{JoZ@=22PN^6jPmyS&RRC*#?^)%+<<|g|i
zxOa_W39?|E0-+UxU;bOM`tcUDAD7Nx_L85Ft#vX^ky4Xk1?6IOpr&jk{*Nj=ut(5e
ziqne2T|$V3)Yf`f5P2)!&d!@OQ%Cx;CM##h
zh$`?XHKB|(pP+L
zZkC7VhWLl{NXUC9nY=eA5_#!??kQgo4t2D3TNh*)`s;T!jRWevr%MDvvgAofS{u=KZg`8lRcsjf)eI=NR`5Dn7%9
z$1pP_-No7v|JdnGpi@}o59mEZTZ%coRJ5;{;(Z{hRWpQ@-_0SUv~6$#cgICzM`OeiYSIXrWAU
z>|}WJjM0d6DpxHXYL}xrg*}Dx(>}EdlB#6aQ~eFK3;FrU$nGZI~I9$
zEvVWX)XE(`4Llr?!3g;h@K9%z1NBDX(*2qDyJ_ck+U0-vgoSpG-TyP+4JU985c8tO
zJE)e{N{E?SLOJm2V%cAV&Vl?L{~evzLUCi|9S)M{WAaYdkhW^jni1Cz>9KpPdtoj8
zvi|ok)VLb9kgu`3_I-R)H};*C?3dY9nFAx%FgiX~Uvd$=@-(l|ar2c?IWyU)A~33U
zHY!~(QvOOA6`wgZ#zeC>U`#)!F&*P$l7c`XKF!CZ32NAwqJo;xn8t?3RPpab=ef&#
zOcXT&Jxa5cMeWK_y@E3KqpLDXM^h
zn~IKbE+QV{D_DPT!ZC$2*q@!FbSzmL{!}K
z!|i0Vc8>pJa68&YmrW9opLeoQaBswJRPVL|5$6KW;O9I^HXq8g4bdNgOdG5ldEBrE
zJg^K*B)()h0^L(8=)566H>!JpFLS1Nbq)cUt6}USu$G
z4)Q|hhK}F8@AHFi!v?1DSp0_I4dPsGSLW6ooJ_iM3BPHAH^3Vbcou7#tMQKsUK3$m
zhlSllK0rhu4iS+Sg@f6eWY0l=6{
zDQ7y~GL1mBK%xyXfG6ph+3h{GE*q>Duv~d1ZWS>gtHg`!lHH-qlBvin+2ele6>b?}
zR;xU&
z1uc->A?&xh?ee!ZLf;5OZ!ku_(IrrB)_Cmn*QC)A8MZ%fB_3K;c&X+!33XW2!BAv4
z#U??D=;tE)7nD6syU@f=w@P?4-vP2PWI|n)D8~dNFz2E?Ca7`Q$}rbuCYA|X)&_6V
zA(Mz3NU~KoZAJCACSdK41L~GM`T~5xcj2rTG%}Drkj*9DQ(zSJh)do4C#-kf>aV;~
zJ9#zBlT_hzisN~prO{2ulpQC?@fYxywIeRC?X#0zs|C4&$El6>n~kRtF*<;vZA}^x
z6w#eHhWzqdyYTOEz@`H313ukFH?jt6uclTwHT(7xHJkm&?GQKB;+@}i;od~gamdx>
zZ-{+0E}KSJi_<(4eywE66=ru)(8ECgnO}Ax9A*=c(IJ=;;7hHia18Y^hCRaJ#_>Kq0!0@&kMen7cGS&sb|2yq>
zMK$)}(RMk%OYoQKzQdj8zM^SmRPhMi@Y&Gy7v;_(>S$;7s(~<5T>UfPzK;#64b0b3
zW?Q59I*O71&%6-uWiAF*AmI*_=ln7hl~t}%G4FG6+B1V`%;>KH6TWLxfB?|NIg0m9
zw^i}b=M2(vM6u%*Qj?w9psgeO3fUxz)66tS@Hx2QbATNN(G2Zp|Asj!&-mG`{n71A
z5h#1ygznUj?pWM|jDL>q2owXv0FmW_Yy_*zRjbK{y(d5GL!uGho|776W-2fNj9+v2~{z#(F2w3>uNIPf=Plr^Ic}1)Lgw4oJ)Svuo~P
z&*C|FjKr;e@|-%6uhOlix2TQNHN?3tyCt6D9+%fv+X*?0GedK>=abmaFCvkMTW6GtQA~_z2(eur`3%$w#@Ow4QSb8)x-!Q$9|R;(7NE7-ze}
zC5(UVx6Ux*j>URHh;-*C6A$6`9A}UgU@U}3@#G&m*p5zTJTu|_5*v^lLH!O|gW?ik
z|A4=N4l;nhGdO=wbtnI2Do*!w?DMp{JyzAR{Z>x3?$ru-ENT$rW!$1ui>HWt!2^8*
z=bO$pNEfuKjmjBU_zK+#QP>gt(Pqyyk9FuVAZ!cGRzt5YM)jou==%*;RhMySpW0~^
z7ipl?BA5Hh5AE43`b`Fz^(qc%Gjk^F}8O7?oj?kQ-7p5Ck*eOkx^h)-3K|1XTa9BDaVnD)8r}GujD(RJE
z?=H_6!)I8LF?rku@6GpPFM6gJ3i#Y6ReZ#K*B$6JRvq$P7dw}E5e3C|BK+618{wG_
zp>K?aJ^MUvS|D*e1SAe1bBulnNF3#=k?$wxAP^o-mX;Bmmt-hTac@8W!5
z1m*)<3a9~#HL9GvN@qS$rjjj2=M{lle<>4|=fUpy?5#7WJ~`7e)kAV>i2f(`KwF$)
zEovI^1}qWqXmJS@UZ3_$K|0-Aab|XFAmfab+kLk&`9L4MQ@-F+LrxW>Sg&r^4T|Q$
zox8U8wy@MHkks0~^gv&^S7(M?gec2vkUxcBvRBux@sAFoGTs)G{N~j=V2L+LHsto)
zl84H2P-E&bTko3W4Z2atS20(}o7a?|yQLPk{l$L`0`->ObjYp}_~
zq){YCdf_>MU#opRqIs8@=Ga4VN8%Ne{B-X~NUGxlj!#~|DC?#j8v*IsEXnGi2IC|h
z57IQK#ivBcKO%UUB+-2bot89=he_JE2fHcnR>`{6{>KFOsRfjKOJk+6F?suUZOH6^
z#}Y^<@W5H`BKbIFhwj*Bmvw>Zed+8bjA#%jYVHiQZ~BC0YhnlbM+_`qv05+x
zmxkqPEUf`GRka`BR|%hra~?~pAwRI&#&X6Se}8-qBySpV3G*epZD+`1=y-a`-h;03
zN5+8%y0@R8PgtGqn}4OT?R&H1U^IJ&`lR)_S&Z-7W8R!|kY+-TI|ccZ|8j04>;F#*
zP4x8Gcf3-zhNyAQbst`9TZPR10W&_lcZdrdL$lM2IjD?L0cAGHeCs^ySRS5-XkfmM
zuti^|-j#Kj?P9Iy;fvQD8MpU?h}e69&0q0v>2?=p^b_E-V19Gow{!1bYQLOTG2WGO
z1YUOXAB}E+pTB)oJ>7pjg!)r8cAr;D)I52Z&!H+biyLfPYh4p8<5bXt@T}vt+gH^@
z+g2T1;=~Pi4o^ZOgZr$`1
z_}q3vB{o^7`9HYu-3ztv6*_IlYNP%uWn9t68mFNYAXa$8FHB$2h9@;Dw@&=fI&FGk
zo7w-U?)sXV_X-<;kZYaxUTFr?!$RlzFp69=HL{zeUx&zzT`%YE5
zG^P$v!!>yh
z2cGTk>+f|MS%d{fT7HdecF^T-?EKDYISs9vbGN*$4b}v&G)ll3f>B)JC&gPm?4;->
zU9o-cXB4r+pLbgPV|rm<4!?2i4dQU@eYUqZQ+8L?O`HWSY&TVm+B@*wvAtIYz8k%j
z@vm!O3#)@<0cZ`yzbJ8=OmAi~NYhn*GeW`~JU?SF7ot2Y$gCXftVEQw>}pd_aIdvp
zv?9tIXex;1I5UuU6`8l+XH9xhUiD8!dzQfWTc!FubXybRu@Iq&PxrDK;*d&AMolN~
zk-HEhiJKiKF}vB@j}_9+oHv$sy34vnbbnxg{_6prFyyTEKs${%@Xu<}42tU`w$|cT
z#ONFgSqaES02@A83D{`6x=0R0G-a_fW_Nhp-ITE
zlkS}lty%VWq2j<6;XOh=lsw7zGzMB`AsYrax$P12^n2<^>TAh+8TJ@H9-(iXGB12i
z$l~UOeojw7eC-h>WAspC4_tz&QclQQ--a&*}0`i)Ob8H6~%kGg!i1l6Q~C*Pd!_mncAr`37i?}
zqO}b9LN5E%w2nkGp>hIUI)-Q`DZP@sa4qMq@s>Hy{_tGsb}MaHXHN;Y-R;wIKDolG
zv~xZ=cwB_-#tp>fUJZ7~ZM_<&J>kpHe9op((j76hwxo;w58Dbu{E8Yme9oWO74SQaY(1yX_ue(sXP0bg43>o
zWbVF3I>vz+y#u^9+-HOQNzCR8y|A=u%08%+^f*=fG<4dM4K~`(a;`9^w8E9Z*TAjv
znO7>7FeiB>ljhVY5op)pKc&@&X3ge$`x%l8Vzwa8MBmk6*Z*n&
z{p0>$=>Pw^0_TqO({K3x3cyCmR$x6zX5}{#rxacR;&0U8TBEE)cm(s1RUpShqG0*A
z&~S(+*{+Ta?dtW1S$kKZJ!tVMuR3b*ZkmaT$b^=h^(p1f6DrYDA3yz|iDbxJ
zBFWGAqTTibr9hVI?VY5u4edf5nc-_~B_CLAp#PtC6|Cs^I|F~ci!%kt56gNZWrH@-
z^~l|V_=r_-J-l2H{{t8d(4>S|Xn}}5pwH%%t*G#^cp>C7ar(pG3f{jwAsHTdLh^p}
z9};F8vVl?9X{;11Mx$zru~L<9G^+11R;qt)MBa!ID1%AZ83&+Wm7hDm+ls$=6>A5g
zFB3A-<%ges`7QSFv?=5hDWh*q)UEM
zq0SC*d~v;+;?xoUBwf=;Hppys!bq1DJGucm%D8=Nf9=9wX}QN{MV}-)c4RRNXKYY-
zlGzi<{uc5cvej>od>&FPbly^~1!)r@iR#rpHOBvJ=D^zpnPDqMaLDbw
zS_QQmlJjUtCy*0>mJC^gFf}oHhYA&5Is})k6?GL*WvCD}${y<#NKa&O;&m;k(l!oH
z8el04)a6d#ITv{%X-qUbs+r7QM)DQefb&|P3(q~D`3&akp*aglP;Ay#%usF%`2WLF
zM4u09Kau1F@4LX5DUKgJOG+dk%?T<&^7&7%a8g_-&B+8H!Eq@Q_1jRT3i9jlAjyZC
zU4AhW`G8|~YslL{5luvW(iEPbQK=cPf)?Hq-5d=L)rc%Vqh-p6#9P%%D+x(6H77lg
zTcQo;*gG6}|EXP8a9mzS=B=aVG2%Qjd`~{p1{t+oDJ1{TutLJl%bB|b8bCSipYF3NML$UAJr)OxN>akaNbR}Pnt^|X&p((Uqk&lP{GqRfMyTQjm
zvzcTbQ{V3gx`EYRq{pZtBjh*WqlCXq>S|{DnC#3rjZmcrH?TcS;nS$pN0NsK9|j@i
zD7;Meq>R}vd#ivmGiIpYZ6~x?`Yb*^QJ5}u^7B16=UKmF&oyHnbS?B|08%Ted8si!
zKZXS^p72^v|CKbo`oD^cj;N#VmhPLFrT_JGtxcpHEZ`^Pb=*(C(7(zZ^gVXpEKkU4
zP8NS=WoB!gqNkgukZk^W6{$&KF7NeeXg^8Icevrt)aFW@8#6StmoVNRiHn+nb$n4h
z(ejpi407$KKNkkYu}cMV2CDZ_CAf5w5IJLfl1BFz7wQtL;%`*Agic
zbK6I*CS+oM3I=z0Uv-BSV`D#F1tsF^65s)
z59>6zzcgFBRMzj`6@=H%`)xi${q`j~vzCD8fC>fr=nVC~2g?%p@0441_eFjTE}z@-
zB*9(QJrDW}%tH=rwK
zjuKAVW&aFldNXDu3I|GOs8E|TqHpu=kBaO?7O}}bIjIQ|NADwsZ?Zh9l=hrX{_S~a
z12ZPeg~06|feKj5M_`?D3}a3zRJyT_8`f7SOdL+SRkU^b-S8@fqMmsE8muqw{80us
zkP_-FZ{X=CXuPOI^#GyB;L0V+-VT=~S<8E4@iT)C+tTE*~zjQS$
z!@aW_`3|_7G|+rBWgpQtpSpN)RGg(UGw-wNTY;ui#Wa9
zo?oE?yiFFE?7voNZ>j6`*BqzJJ<8N$Itt&9Erah)2k193#G7&#;v8^R??wbk7tZ1`
zkt7^J1kzPYU{|_TY^2`|FI|n1|JemkrK=(IE|APvvE};zC_{IaBjWxtCA21o<)(EKF>Sv{}Mc|*LyKX_97!}j}by|{f19dmPs?=5>
zG8uAhOW@bHYOh>#*^@tDz7Eq}g}A8P)@3sX-c&3yPqK$>9I#c9J;iXfEk>3u2qWzB
zmM&PD+ST_E{#r|*m_`k(xw`V_2g}m1Q?uu=TfF3HrkIeBoDkk0?~v)OfD{!p%td>0?dOW-^
zydKwm5fsnpdQ77ht;i2#(PQv_qGGBc!a_b!$h`O08FcyJ+arQkYk~B4UJN+8pEng4
z`mV%`?{uLm04#3#knyTo9+Z~f4W9%2lO!YM_Kf0^_EzSV{FikB@{;C=jU?rkqb10>
zb?bY=yNKV}F6Kd^-x1Szg)F2>MkH`{`bXKcRT<@)S+_{Fc8rcmwRCsWc$M*a>}+%x
zS#rVsbu>B}DKbtRRm*5>(Dc~YV(*cbcc9`y$m^P$hA05C5dKeN%bBgLuVU@tT%#+Z
zlaJf|QCS0;OA&1SQ}dH-29E_A)d<+MX|&ravCg?`Qd>cNe_ToKJhRIlDeQvf7`D|-
zkU|`}&ksdjQ#r+cI;z&tSyWlL6Q^;0oLB0`x85$)hj|s&S4Ye0gkuscooKfz97#=C
z-kd@f36N4UDuf`%J**G_m
z?)YS>t3eMeZD$1LZlzD7vhG6so-f+5Jvgr!Qh-XMK|M2*?9yw2Qe!&w_Hw)YV~Tr5YwLhP
zMyLV0@yy~zYvRuI=k|syqCDo5)hhD>Z&wHuAZ@f+4%zLp+0>4*n
z-;20soFMLv$4IBDyIH-4MG4cXalK}|jVhb)xRm4pv(YtQ@g9ZbCyJcStzQe@nws6|
z0iPgiq)6pFmT%y+M2j@$4oHQuT7N?DM#%o3o2H}R;5io&wa8F;LNUx5nyH`1H-Ci4
z3ecJz$NyFh5B-f7@m@2hy8`dWBU>=OQq42E%YYQZ&Y
zb!p4Tb}9VFC3$$FG(bYZiOyyNv6bEAUC(ts-2r?wnz7m=RL7)S-N5_(T|Mk8Cu^6i
zDL6&A-lvZ4I6+9vXFfzM2c52rd%9**EJvw@$8rF#dNkkRu;tWEIZf@Wo*}uqf9~|s
zZT)liPhWrR#`PVLd?lK@e=%d)-qAF|k|t$tbJn<^R~ZQDHd3VlTK66D8@k(w|4#Zd
z5D@@Rd0ljC2rm}4hB+-E4DGtT$A?6GQV>bL^u!I%@)<8yQ9N)Ys6K`YK9=}L3-CGd
z{naX*iL^qgYByV{@?Y`4!ppQme5TG7g1<#t8>|ysqa!9D;KtIN-fSC)4Sg!h_OQyj
z9GvVz%?A-RA6yHU>E72pxhXq7;7A=#bQ2Am8q#c!!~u$&Z&}t-JM=bnog4<&S>e(v(xBXetQ(cSCt9JwQjdZqqM9ziv^XV7PiS%tC
zw_@J0gGCKM$kkpmyLE(+yQGHm*!tf!AbNt&+wpHs9t`h6=9gkT(iJd~^e{TWAkDu?O3~$48-Er-FVDS@*8B2gJlD{#+n`3~nKlVa%x$oP?0=TOVHQ9M8~{ngxhKanKG`y_uSY-_n4
z7+GJO%eI^O^mctIHYEt-ZC+g|ukh=*sx_)F#@|y=Z$*UA--*h(?W<}?7D`|evIN^N
zw0XRR*e7)cRc=<-TTzub9?zeHM;6jaAUA0|{$IR)v%8jBqqffd`g+a&0+NyGUojof
zE9l9prS9tfyCHO+sG0r+>4RdF$>U06bx!o^vel4IBjmrc{Ew*MZSvRTD;ZHQ0vX0*
zA9|eRW@>X^-^_Alb^L#)43O}=aP2B|o+5@FNHHpkWiMA#-T?WrxX1bgEGi}@e?|yiru?uRQ}_kfQm~H0W)AcRYs4ldv%*rfgGp6{vy2@ApD6b82By8=
zPUprdXNGMEofUP*@(cy}39P0~;^ooYV#00dPp+Y=f+7C)Q#HZ2-k<*&QNh=}%YuA^
zTva6G8ECVJBI(z?H(3t6yHhC85N5MB^YW6XAD`fU-9pICVis^zE&kzqa0l``fzd}h
zxN6on@B~aT3KpE$`J-@i0~s22wyMKd4f-RARFwjIuj*_tRPCl}R*>pbU<_5;u85(^
z77-CjjRmhR|Mm>~#)3fN-x04CC}02iCSX((LbWoclv6aO`Ja&-P1bGVWa#IPo?m%&
zW+21`M}d>oJ$A(Lfd5j}h`fuX5xpK7lgdgX!n0cV9d8sh4S$2*J<5rcp&x1^$sd)m
zs%CY9vqY&Ai0jCWpvboTv2?N?Z$ZpmyzG{S!9GezUb-u$iF=$O1W5kO=8r1{)Ot~A
zfK#H{F|Z$skbv}|rkI#~!mF>kj=K$?$Iz_I@+-4~+i$EgFA)(>#6Ak_`atadXNW#f
zQT62CRF@u!O@jueNyL1g<7e^aDt&FZ=j%0yMimB)(2@2_7u~UuN5*dZlG8x_9{wAr
zfzfkDq2Y;Gg@XCKc0}y{r-s6sG+dxHp7mG%9TG5N-i35RGc|YyR^$E|KDnfc)3xu?
z-oxz4F5H5#oaS}F{#y{=`PWs4L-)U9&6+Sp+dc_XbhcHYXyB|wx@lI114DlPLQWOU
z%h~2=tlRL(o-e~aojrzHJfu?=Z~haVk@)18m)&__D{vzDDglj6-B3fdrrtVw^uv!E
zcl_m(Bd6X+G&uN-@20|cNGeJRMYw{FkW|F_B&0Y;^#btSkl--c@6&YJDfi+Bw20{7
z5RW}v*=a)7>sj}^$CLB`4ok4@Wp~x;{1+fO3u@>b!@|8imZ}|KCysq09xDd){6Oq$57KOu(Y(j=dB6VOBKrEojajIR*-4y7
zniV9FCG`D%PJx?xa(_T4?7r7UtS(LrR#lJh1A2FEIXi#f0?LMZ{M*LccADtlOaJb)
zOEvUqn)ip_JN_p98rb2L%vyYMRL?-(4|*`X+!q5YBWR#=f3J1E`|M%bBMf)GYFqWk
zI62sOt5{73jMA&qBrXC6K$eOfb~jPaaAxZEz0R<4%5VO0E9OSoXY2MV^K|wP-=C*p
zX}8YPx;@k)pQp_wF6+-p%C3s3m%t~SOA0>T!E*IN=k2RXBom#r{6xVm>qwg(v?K0W
zO&oz))ZmWow<3l)fp|cT^wu6Wh6Dk18>(hi(EQMB$-lW8K_?aR?HoO`
z!h2=Rb{ZRB`(cxDW01^Qb$FWrwQmSBD3bQbo3Ziy_E68HC+NFvza{zA1^HEEHOtO!
z8cyHGev%Tpb*k2tDXpD-V@O06lcv>ob6NX%gUULBvbuglcD+<&z>)O1$&Xrr|EX#y
zW5`r=gA;n0S7H)H@#Y;pxTX1O?;_t+)y)&DV9O+(wzT(VGyL-}k<@~iP3%H$iD2`2
zhgTP?hP5{~sAUnB=0M%{I+_b$usYI!J9uQ0vahMXZ9x0jf?ANUd;@2naL|weR5kl!
zCiOd7V-z`tTSXY>RMr0GQVoj(Mce28*oPaP?sM|!Cw~??6&QsntN!(=u&#i(d!FGU
z-A0LUj@y!v5Z2l+S#ul^;vp(APaY2G+hOG{K%K4**rO0Q}a4rm>N`lc&Q&|27x
z0_T=cz;kRBR%p$&9VF|NpZmDE=AHuj=H?+~FHHeD@{vS-Bd_`v8f`prPXz8x$QQV8
zo*#lYi)+v3)HuJSU0Fe=L)H2}?qXEYZ-K6ZsQbbBaLownoqEl3=P+w6vU1rx`5q?=
z3zvsT)`lE{ol&BKtf)>dKrE|qRY`+fI`Hz(`vlI?_4LDACO?3TYy!*BkPtP{hSlcV!W7W=F;^
zI_&Znl;w`-3Sow1R!P#u&8>bfPA7_LXkUX{fAbZSDWCj%wEKo4%5cG?ZA~04o>2Jc
zK7(DSdgD$a3crCS@c?lU?Y?y&=EmfP6?t$2}gND~4Pv<1k6sTMj%wkt$4V
z>)LH+Xd8sGQFYFZbhV92z>>%zj9oTY4ni2)#h8#qr?T&g4nZl?p
zai8%uc#a)CvU2874mO=Ph9!tCyMps4-!cu}*(2kuQ#bC1j9G!~zid$+Nznq4!r?DP
zoWe#yGY(STIPVPDG9g1yrFUM-6A=X>)et95S8Afwgiqa(ArG#DNtSoSbC5(*?f}~G
z3B(Ua!VA9lc%XRu8v|FIpH4-fhHB1>K27?%&Hjkq?>N_0*bK-|QuwYT$rw9c70yIb
zGL;5rB;A_11pfT@!?l6(xxpOlpO9zGkzxPec-GQsKOP6t0rPT`hsLlNv&guyYZSNw
z{uxB*IdUEt6S5;CBI#xDW79ZID4WK4MT58oSm!Bjq%H?@H5z_1O^IC|*()5fl7D6P
zSA55F>layX`_Gr*biPnjV1Fc+qvGFo*;#BdGM8~D;r7nJxxer0de+wZTWo0*wMFMU
zMQ)LH!D&y4p*tO#h9}`emwmiI7G07RowO%&mwt5GK-Ffy230n2M}s;rWrMedv=Z_?cv@)W9(1$`&U>Rf8TtOy=x$?%qK
z)jg_sZ8njI2HqMk{1yiC)G%KL^V4KI9+P9GM*@zq9+wT4$whbyo(1w6(!F|a*Q}j%
zf*$;K`d0WS5gAfgc5$=p)!k8}6U_MZJKY14=kAkX3a;-sY?m+lMm5;|w+FBA?@4pv
z^rnjP*xu2K)ULXx`W?tBk-;Bf%o^NV*M0Z)*!^RJ-Sjl(Afb1Z@@&TRa9gg1aj>yK
zM=K59#qP7MIt8=+W61QWxCg|`OfJ~`*L8yK94^S
zI65ZxxBUu>)1TyQ!aS7EJxx|?!dylL1jqr%1~cLN;_PI49&1^A^N&N(Q=%wG1n+_-
ziF*(>AT{#TF8MTGU9K7@TA~+qb^Woy^F%=d;U5h7J_YsT$c}+}Mjr>t%kOc)mh!yS
z)8v&Bf!Pp1)MX;=_~O~MOCaaBt6?MkoLW0;2XcBuh!(Tz#a;L{RqOx4_Zdd7@dtc=
z$6t|9NW8jOjsK3|88(|C4-B>7)y?>hSyy_mf=>iZbh(JxK_&t$ZWNz@Cko^E6JMiN
zBW2G0ri)p#j)IeO5U3AZXx%g5~g5xqCQKhh-BIKZjJ=Fiy#ssC7WO`trc
z`UT|RDE!PRgEeS)?=^)JDu#u*9QC_Hp2`0kk0+Y+oiuC5Uvby)NPhCu(aDOtHoJO0
zwMUWsM#^=@efux{kdA5%^P^`E%}uD~v|$ZK_I7`NbQuvM>XHPq&3A0IZ?$6g0%cW>
z!~d<&rSQFjW~_MozP^LhPP5%_=>6*Zt#pW#!^h5y^12Z&XjWwV@3;9oI#e_(u=zVO
zP?5tj2{wJqCvohwcj!~=p9armJ$6^``Or*e5B<*&$CMv$C_7lvv6W=B^1!|+hlwVf
zIU{Oy#={$Q&dKlXQva^8(Ei4-W1HZw?E;S^ZM~oA{RAq_;LVDpXXz
zpimL`y8Zyk-^#z|`g+(bcR+*fJrnxYT(NZJpOkld*0>KVD{6ojNLkZ0ci+0E;I;pI
z#;c>_8EUl(V=Z}(a$iUMN%7`~Z=|Mb%AI#LNw_W28<7DWAINTfjNNnUe-%MO@$%fx
z>9Q;nH?>1sjF(^YAt&dE7;Tp~UJ!uJJDKjmu?OI*uf1+5u~DrdR87h5xzi|Y#csQ$
zVoLVBNvCVeEFCPqmEsjiN(J(5A7l@Y#|OXUC-eWJJr#9yB3Wy*s~>H~iUg6hsS&uu
zP3PS;a3L^;;YW;WoM?4f#|frFr_B(N8{>_*OE8F6bu%CJ_9D7u**^sNks8gOQiCox
zMz;0}`%5b~Bkm*SJ*{XT4(i4UGj;MpWEr9TEcbIPE+i!sE#3ji>EhEQ#ZcJB{K@jQ3$brlq#}8wE*7@n6}^$ubyoz@
z-j)t)@NM(#J2n>mrYjLrl;CQ}nkF87eA@JlR#Cobk9HSz1W?0H2>!O?OYx&;r@2mN
zP0b=3OV#oBixPgHxZmnJ^DMq8s?p!)Eh`ibc>2tNs?~>!M*Tj~ILb05swVP2Z(N~J
zw)sGFrg)&qE*2fq-&a(lyN~uD{8Gp)ziYZtIG;|t30}4sxj3laVsYA4c8bcqyWBWR
zGnu~k>bql9Sr=gk{V!MPbmIE`oQG*wHJkE;tOuB2mQZ{ZS!#yLh*0rbq
zg^vr*QT$T2nquzg-E)7Vtbhqe7rh^jb9lTC@vMmbEbSsKzUyUL>%~^mZOHOXk#5*A
z&tvakG{7htCffCw)81II(IUuWw71Q}7z|S8)Ij;Hz4Xk{(#ir|x`=A3uo%T9z7qIEl1?wh875z(`vxc(;xe$~@B-*O;S=WW6s!*6CF8?Yaml((v-N7`N8{
zQR8>A6p1x$PR~GH^t-?VLhN*1lUhDV>Qcbw`DHGZ}l|^Yp4o!!RI?Zn!GWKNx4
z6jakLTm9;OtGHz4)TnzS?<-2!lZX*jZ7z(BIOUGQzi2NRN{fvxcchL;`7xtj8
z*L(oj69<|RsS(;?@G<@2DeMuNkwlXRXBkBd@^hN=cFG)v8q0iYDeRQa__;xH123rB
z3b`K~z7pK^t_gPxP#)I`X~+AR_lq(YabMs&54>weWSIuCD{@VRkT>B&g!KkEO4x;e
z^8!B!y=Uhv$NzI{k3)ti!0q+`Y%nFt*>@Q_IcdM7FTl4}6NfAWlI(zsNVzM>=<8&;
zd^q8OI7xX`g!oKt1%#Nmto$0M;0TZmQG%vIN(fKYwNTI%9p;*B=+r2
z`;*AaM-lcPrYJp%-3^XmGgZd{;ndm|8GeZU#
zN|sL`Qk&Hm57G<-g!=KQcLo}%;<}=1T7Y3noQRu+vYqK{!`)!ScaY=%JL4d4BUfB<
z5Y;yrM>LJ$5yM$^z!8B)j9d1kTX0$_@+puT@Zhe=u7A+06GY@zup6Cc&xicw*&Xw@
zSj1CwZ;qo#)70u;4z}cR8!+cX7MH?$T`^LL;~8LI2OlQQVm%4{HdYPr4ErtY;X8uv
z289c`g&lgk7TTRgZ@tKP%xy=$fZ&?oL2OngVzVZa44zu@xXQYUWzQ4;on*Gu)n5gX
z<4zG$etj?FVVY&im{#)pLK)qBz9Q)cq|-SkeM~qi6S)oGKg9eRq=`nHTjg^q_fzXa
zMw&u3ztLzunE#$)bXbc%iOddqJMA4I+r1f{8qi!m_iw?F#g{BG
zhJH$Q-!eZfll7d*l3f;mSi)8~fJfGeTd{w2!lRHibW#dQKJv4`iECT{p0U6R6UaXI
zimAZW2w4#^*5tWAtxmXbPr){v9D!p_`7
zuo?AJx}uvfh{VkC!h#I3Y4K!zli0LkvK*Zv8G1(w6TfslbWo5Ul9$Iz;z&1EPI%Oy
z)22kt0Bv7(s$JGy!eiFT4Z0~tSIQK5YlO->GES)1Qe>McA2U?k{-S83oi~AEU&{j>
z%80o&i(7I-`>Ts(REPW?WUrnI`M(0FIf>-=7!iyh`KTQ-V@x&QS@?AfcCH5gvqthG
zGCO^F06O@BNn26x9oD(>5e?t7P@Cs1g>MGBGOLi1on}z%(|AwgJkBCS&DHA$b7L9V
z&+^tE;2sj9V&B_+p}XVpx)6W%mcA%-bx#7-@+=%qmM^&UE#T(&P&TViD%g_b*U6xt5~yX{zKXiJ24914{1NjZm9zcEUwIvcWtQ=uVxroG1^CQW(GT?7&e9<5uEVWt54=g=dvfI+AIW
z>q5DY6a$~t!tAwdlqv60<{V)b$`Oz|aW^rmi=&o&)#j4N*-Zf-Je`RwUP%m&48<~z
z1Xm*d>3dQYA&iJ*am&-G
zbr;F;gqdk!b{zNssE$T)?W<*>7APjIpQeP~%hbY2vb|hZXzD>_CJW@wK~`}!SeSE3s>SSL#cvC0
z70y-S(@CS@vXj^Z-3qy1u*Q8SHqE4!AJzL^$f{*7vAC?7P~FZ0cUK`Btos+335^RD
zMRDOyHR{7Mo=COr!JQDuYxyPpKW`?TIjg^bCiMM&ZU;Z0AB=Nk?^UIrq4)EXB+XdH
zye~YOoqQquEbiLCeImF+%xg?@!v4T+UnC;Fh59COp#^(Cf7nRYm}N0hD+`wADZC
zCd?&Nr#biDLaZuB1|$h_{*i(C;QD8P4%kLkhr*vB!&LiLUVm1&*_k^a%hcSO5Z&CL
zWqQS@7SX#`r;m{DfCOlzvrN8FgI#u)AP2jUJ4l)1L}4i7G&?6T%oqI`6&_l&m$1)Y-uZq{@B^S_bL(gun5`C!2wNaCj&_o=~;$UJg&-Qu<(++Qt
zBwIY^Iz_;c?|D_P3VBJ$<1=OOc;Vtr}4izZ&pi)-lwQOk`j{B}`*e3v`>4?z}*K`qYS(GZ$RPK$lv56DU8B*X$TOfNlQR|C^4p2vx_JOJOu@03w1
zl#MBLS~F~*G9^&_WC40~EXDoWBH@!+^;2byxg1U-qgHCmLQjO*zw>Xj7_s@)c}l5
zbL)$PXVFVpC5+eX4-hgbs~YrWz$^@bw;K4l57ilm13k9}8i=_LwQKg|KNJzj%T1VX
zg?BLadfbGq>o$>%k4IGSmVC2FzToIkgvrJ7?>z95n=_U{;{dATI%el0^jSz7%fw8JU)%c~YQ(!yr#m&)xYDxltk^^v
z7oOAiUIR{n+FjJpCLXyGr}{@$0iA|*4$RGu=GCTIGBAG}qlWA?F5uMY?Z@IMFTU9d
z8@*$0McLcT!olXHDV1~-j`Ew1Sx`N;3)!T=rnx=%UAo(8#q+xB>9Kj!HYhW%*kn{gX}|M1TVdjJ7Q#k`y$(5x6j@+a&BJK}j7a$#
zpTN%~eWvW#t*s{Sr(^T$s!R{GuOqNlq^hs?lINk!0^fr=&|P;tp#<_#Q#Tt%p$>C{h8Djw-AvHFZf^rnX(M5b7V6fBr4zAJqbo
zsb+9zVO@)*i`KQR;*pJU^u+W9SIp8Y6M?Bfa~@O3QBV)raHB)A=W=z@aMH_BP1#no
z^^aPw+bWUVv3DPFGPRNHu2e6B5AX_fnk_(V?6DrK!HCWE_qy$-BH(f3B&61-IV)dz
zc9LkDC@=)dynXMM)#xoAcD{txD~6#!;iTsLoldo(%o&JP8BuS5kGL8LOt>Q(kBEBG
zrh!f{6}Gu{@JL0h)1K`9Gvxg5BS0w`Tl0Cv49Da`arZC6(@eR4W}BdMcs1~n=5R5C$%_W_gIHLCK!Qg
z!Z6VY6}oL1Lo25q2rDg+nzo+p?ChmqeSc@CSx(lhwD1#~pA?jD5jsEmXv9++DH05E
zA?6PFMD&+Dq*-Qf?{fC%7I3@7RP3#}?|SU3PA1dZWv}maog_P3wQUMcM0kHwTc4*a
zO+v3G&LEr-uaqeb1!qM68f}_O#=n4-rMag)$fEMu%%}8_Es0}k!^dXMiBBJhqYZ0j
zHJumPOFvh}r`!be?aj}iEyZm+&M__sSB_KDvyxE*dVzK)+;#3Ssf-)w6gmN$edUHL!V~5<5jAvPG`jHlq0f$tHotjf^h2M07%)43rOM2y
z^;i>_9!qx=NmXIK^ff^{;Zai_oI0sJKh;~pk$mh#z)ZahYwbj!z^IxGnryWj_Nt%9
z<9rZ$5oc`Nc*QiPOFS|>9=*p)=jm)JC;mc42JYhQ+10n+RYsR4o}NM#^3)QG3V!Jf
z7GXtHkxh^9T-~3sZ}USq<*93yd#s8@6F$BF^Z_5Kcy>a4rJ#@B;YM~j>$7?`ixSSh
zxqGl45SDSmBiH>`x+kiUNyP4V^3y*Cmo8QH+bh6J*pnXe0c4NerHp_}i%*zck7<$L
z{){;KeUiYv(go2FVN)ApuBt~{47vh%_iVxw?>}J~-3WB-Ms=N6*N8K$Tw}`LLzbTG
zo7eLd-BuF6bVI}2z
zB<_UNv{Ysr%HEzw+4IqMpclWQ
z#2=<&56m0xf-FjYsY6{rP$5~bJ@01|>#?_9Mb;1E712uW@x6ie+?a$0eyY+AYmMcf
zfl`t>G*-Dc!V<3t3oY8%a77c6AoFgvzfj9$z3k(?^-Q}ZSv$1f3I|Ie?|9NNrk*J{
zPxHx2LA8twnq4<2s&^Ab*!l}K9&6d#u;9iY0=C!@Q$-iNduk>}Cl>$oqBZ&$Y%~S=
zrphAx=gfz`7Ra89*ryYSg)93A^5!9+@R$`Dj-D8zA>;t?1af{i
zlp57L1^zD&{#DukuTAuuxD(N18j|PDNw*-dRpc?7R&MTUYQaN(kKC%C()*j(=k8U_
zHLw(rJsnZZMp1$_mY<KE|31;7hi!6gYEvMol^L|j2EIf7J>)pB3l+WJCt4r}Ne!)Cz
z)0j;LYw#wGjp#}S(jRU$s=Q)$4jp`QE0{q))UN7rrCoC}wMDIj+GB0i54p811%-hy
z7_^PVKOO5m*0g?4na3)B2YW4~&N%R#LD#e}%Gzsz?-M!!JOqiU85gan#J6x9a21xp
zcgJj-i52m@P6oKP_+0(qJ_qYMrj1O>;{2RV=VK}IB#Dlkmj*~!UCPa~`tY`L*J7Yc
z;S`pOOSQ13O5#G35J)VJa#?>ap&q?$iv;B5(6_lU)=h*HW*m!|U2GCATK(I6*SuYY
zf^qB>_)TeFP5UpLuKFvcM+?Ztnv1g|;}OL3yp0nuRkfOV
zZ_((<@&|k5`u+KGM~ynk8ORlu_ty$3-d@e;fcu-8t)19STKK?zm^&(Fg(Yg@PtIHI
zPa22qq`i@PYXv3cE~lF3{g_H@M!W7Mxs~z)pgV31q$WM>fh@!E2dgb|3@`_eG()ea
z6HNXs@V9{6a=1xBZ9`wN9kNJhEDaZp?H2-GnD7Hm(%G@xMC+JMH=!*U4rT
zbPag3a}(BJ7fpDdI3%kMa->HSan#LsFwGuTXOamuRmQ^(PUwPx+|=R99Hl+=eXb+f
zxW9HxYR~QO
zan0Bhde68htH&~dau!j+*^5ffs9}>>95bSUzV}Lr@ED=8b7Jmo`eXEs>y$
zmJPsjLx4$z^?!inQH%jkVZ~`R+FzhMk;WOwn|*j7m-106Eria)5tL5=Zle7;D=n-6
z_4rWt!kpxRk2%P)On9xYeL(Be3!6TYmJ?zpNdcrWR>UwQz0{ruq0K`2GH$t|9z1^I
z7LEEklQQUjBi)tR)Y(e;q7|F^eo&#hd+;fNm|-C2_AG3D8}!739#o17w9NYt!jJ5E
z!sJOf1|I;!f0-ev?%cE0IHFm2bgSXTtFr@n(UmOM%aJ>4&ROjJmb5338*le$PPR$Q
z-*Q*LwhLr`qF13mC*jxnLJZbD?#b=gv(%$hIG2ye>Ewfl7JW&tX
z4iWcjKHhCYo;Hr|2A*WBz$
z@YFd_ev`?K6+^@(O)~n3@yGXGL1l;JiW;x3Sb_x)`2x9GS
z?vFrXg_&oEDJ^BhpJg=Vh^+^`x>2lxj%4>g*ZYMV=Q~=<-gjcv!I^8aK5ez3mZTKx
z*zZpMjBtr*t-Q!|3M39)Dq1+!qiLg*CyzojiG}=H*=qSxX=Ivxdf|C>>FcP9Tc8ad
zD7+vZ&
zLM__T^|$qBr$uRP;kO3uyEhCkz86E$r^~glN8N-SHgV`vE*qyT-NtbtWFT?kw9i}p
zZc;gPlEk#d19>K7?Xb+LU2c1!b_bq2zOSKX$r{d!D?TXz>J3E(?>J!qhaPQ-0{ZCw
zeAN9JkDVs$Sc}s;ao#WB7nYE(iy5es;1SjijD!s#z1Vlc7TYau3y=n6&}&k*9*>Bq
zWO&)JPf=Z$tU^>45>VR(8Q2>{=rX7uKsr>Q8GU3=`>R(nlW#1sXT=;=2Zww%Oxx+6
z_iQu8PUqI1qAVx!-M__NnsROGq%}whn=1)-la5N3w6kI-_D5Xl(P7O{W#7^Lp
zj?Gx;K}A}~DI)&mxcR!%&TDP)K6DJ7lw^8-%CdD>(Mjlvs4eOR))wWL%(DZ(16Bso
zKon#<-k$+C0wRavI&W}mz0zyP9K;OO8Z?AyT49@~oWqG}Gk8rpsVJ`K
zG2>Z6xC;4C5?h}N`A;-XhVBl{Rg__QHej#go0b0(^O4h&&EP&)2&iq9&t%(TLmnV7Z!(mRiG`h`LjY$MP5
z1|Z4sxgtM@ClF>hj>zzF%zDcX0fMNY+Ek4PFW#CjTcBt!k!h@%nobLB%5LsMovLov1K8*$#Gxq*F*oGvwK@?L226fwp$`9P_L_DUvsQAuV=T!US_C%c@&x7+
zC+`T;Np=aMmDva+_}XH#pF=GUU2H5+k4<@CL&`DNWLl%RswKNamlPoRCO{WWxU{wR~Xre9C@7gJ7
zv1iDiL=;lnDof|L%$jXJe)TL)b~?=|-{UQYW_ISo&l~@K%deOKMkPqru?%b
z1>X(&9=Ck%+)79z>dL4-^$X>Q__{4P4l-j@@UCOX-3xxlJ&xqbAuA~DxuiMtJhSN#
z1}JVQ<8b_k9K(r!V0bTTx!tE(PIX68F%xYd5}(k!
zFh4BDEe7qKr<~OmHL@0gBGayhOar;IN)7tHa@jK{IX|KnFei?4K4YZb#JGy$t+KP%
zcoAF>mzxP-_e)4>m@
z7WQ-S+$z;Lg7!+nE6%OWr=1gcGXs6)lGLUlDnW~c%8;MK%Bt-%VZKdx%Dn#Dy^xXH
zC1?htAfIdf+Ta(MAIUEUKfg#-<+InjD`;5K17BpGBNOHm-T94hb1W|w(h0z4F{KP&4lf_K4j@|6h9yjxmzV7AB^Gh
z=Fa_w{dJ^1C?ZN!WqS+qX`*$HI}|S(>##7Zh(mZ;WlbwL0Dl7bwZ&ZnP*mw=+_cP1
zy`-&V)@CiMamZ;;5eJ~>GTcR==O(J)D+*r2tl;FNmE3_DsF;b7JC^=~W`V%_U-3hg$T!~z-zZ`0CTI{q
zgX$ownM(I4L#yh}G0&;t)y0XHV5z|
zp}e`j$61I7L0Y}pT?1{86rtGt0OFl?Ukb_YylwkuKY;R+m?To$K>0x~kU?r^ZExN+
z8oXef&^Hbm!Y!E))OtHwpIb>dK0I{MeQcFj5_*Hi8fLo)2gnOW6~
zi2On4Y-~xk2R^d|8_CbuXO4AWVPuItVp_Q|Vy9^;W_enXA{W!HQaB^|L^}9XdnyoH
z@?tu2x`!U4D1@ZE(0m@F%CJREg_eYmSZvwyW@iTMI%$b?P!{7)Lu5Q3V
zP}+5IF{##c$QedVTWVFZ6`v+0+pTnc%I>&>hJnTr5l0-cOnjucw^C7OYco)R(eeRX
zmE3P_7{X-T?O*{TZRGcToiig^?e};8Ucc|}518}tIiJVtb3I?zCw=>0<+YM2KVa1%
zI{aj1OTPikc1@um4Rmg+9%l+EaHh}&=n9LTampSobk+wV0EzR^S6awwLfX7QLh%~%
zUkS;q`k1Hx=Mo;|_uPh0p+8Y=Sa1N?jF!T)>|@W5#!IhFkBW*sA`+w%_EUz>I)>6FlPpM_xhfMe>3N17gMB)oH=gw0vO
z2J{dAktj6$_VoMzKs&Pf1G?Wp_fOJQ4X$FIq`sYd^fFnAHSp-+s(r{$&K2W-@?CFy
zX-_pL8~%m-4SsuSNwU-TKAjLf|19#3ZsJZ$C0~c^HRCSBTCJw~ES-K7k9{bw;lrav
z29|*siz1Mam9JV%Fgs_BSK9mOFZk)S;|;kiBp<8}
z^f%OJ@b>z1bMdBeX<`cbL+L9g3(fb@uYq={(0ZTcR{uL$BM;B>yD$Rl3L|NfZ{Hc$
zeooKRoK?^!m)x(caVSl^>-xc1VE{XN+Wxs9?Si-nYm!
zC2%7tQ_@__?7#s?uKIJ63@b0d^SP0Q_8b`sHX&!uCKlONI9f-$`SCPcC7kf?GAI9I
zts#O-Ir7>@E-U*VjuiCqlQ%1;LRw67_aK)nPx>lkY)!L$pC_>JDnO=xRXYpb`zqQo
zJ+t+vq$Gu$(b;z&yp+
zZ>1A%A&0rO@KF?_d*a-xao{_+w7}9|y^dL;jEL|Pw%wsZJOh=g43*laqFNq~llzje
z5E{Gx*nb2X^5MN#@Fw@SZ@zuVt!h+VZE#pw%tc3!r@eouA=ndLIkltH-@cIpcdNYc
z*V)V7$4OKg{g@V6LvZE{<^$eRSSJ^0Ep1N3iB_tVl;3cwBj&Y4WI{y!^9R-@X8!`Y
zGGR-ffB)L|OBCj#IqsEB(J|TYS3RM@`HaO!qy_-&8+No%xq*|CvC-H?0p2$t{Tj=qIdoqgu@@VMTIgx2L
zgPoiE1ZAPdb<4qhTk*j=QIEB)|g
z6GzbC}mz5@#jNU$hGFTVaw=69251U
z6}vf@MD{r3V@@l!gkq2Z-5QN;9dANx>F2aZBQzvMOrrSf^m*+^EJy0V`zmc*=Te+7
zpzgF{7AT7Fi`wDMl%c9yu05T_X=unPua)p*?)*?bDE&17lAy8&S${^<#fPQp_FBX^
z#Z!J9V-R`X=`1n1JbcGEo1K3eI@mMiXm`HSj&in`&be7uTcsbqPlNft31?xvsuaim
zJ>X(F#MCB0PY!MhGPBTYBHe%_do#ULA@9IW)jI{YBFbRZMXevjS(8DW_&C^OxkfsD
zuTi<6#to?&ItoZ9$oFLI{Y+{bJ1;bEu#Uj*ID)Vv)|YZMroV97jYz?_@g<`IEaq^u7O(Yt!FaTVXUNVvww#gO~2h*7;632S?k!=
zbzQ0$TN9mx)iGH1S
z{X-6nbpEGnrT*7^^4CE34afk2?(MsJ58v#$KKPGt&+Xaap0`T5?r!P%=e-hCZGQ#p
z$`;paG?mbGzO|FhewU7X^i2pK6;sdVc@9|y
z_TwC}t)CzV0L^Cti}=j*R0oZB5brF2tjNI&2^w+GKiFdJk@fTibd4i|tv^vd%Wf%w
zSMuY^q0?Y1ZyFCsC>npjvN1a;n=*){l@XS%iLGpm-frO
zsZk>S^nJM}ScM7H4&gQlv!p-MzUFNz2R-G_f+z50clyX>(wCo5{H63{L&O_W8Nyt!
zaku=qr$@(2KAGu(H;bi`z`{d=O}Cbl@mSV4;!d!`SQc27#&Gkr6pbT0rIa#cr7sOI
z=T?#Rg0!pw=Gq#&eWd)^i0
z=p6Yp#1zO-#N}tD&>NZy@?c1TM36Xg&3m#pa^UNeI1Q!QLX_sWrxzT~v36|q|K-PH
zP>lLFW6%LdN+U2~1k0Am-lR2mOZ~j3dlJwe1r2P1-z=zWnv=X|P4k@b
zhl%olqxS)8z1R6}ApI@qc-vJu2Sfe!UpTlX`=q5k`0gttcR?zh+RZo
z>A!;3R6Y{{I=S6$)duDL@6r>w?!cvG??NW?&qfOsU-Vld50X?x{^m)iWK9>eGWw(Z
z*jw{*afwC7*U8UF`wzA`o^hF-=E%FmDrBvNFA-_HEUG22wa!m4!l66ANwHH)4ap|XR+p_L1WNmEW
z7~*>yarUTTW(hd9xAu{IOCDRd)%V>0ygq~4q&$Q(mgM@*z9H9lQ(wi5U1d;R_!sG$
zu3BM*z`RpdO)p=>?coc{wI>M!>;(QR=4h;w>IXGyy{jV&417VlyUcU;YQ??fbhmoq
zn)1(Qk6B-SJtWvEyexSgbQLp+~bC8KKH=A`g%ki|S`}qD1BUo>kK}lTmO8UP4#PSFUuIcBLan
z(b<(1SIaMzk8wbrU#&8^S349jK0`2;i9hc4LvfG3@kRBkI+^MgcV8@1+;XXc@^Hiy
zgr6ZBYUr6TQZ>OgOT{>y)khNxAQhob_iDWN8-gR5m=5^%t+p@<+*z3T4$9?*7WIlR
z>8;i$q^gJ8%sjFc@p?Q@pyw8PoHq>&g)t;w9PKHh<24nDF>#vB!8`7h^SOhz~qZ8gx{%g$*g{$#)Y<~snPe1K-
zuiB%~TCs;VcQJ0O1(C?98fgw%msGfs70edfM!imm=_t3ZT)m{iv6!Av4`MD8%*)nZ
zyIG;6NMFi^MxNqreX@W)Lmmt1S}p`WT_DmvQhN)otI?IinO)QIK8;
z|7DVgDFfUh%ntLND>j(munOM0hYOa@qHWIlDlhX?sEi!hG3dDlxyxzb81?L_o~@)=
zdjA)0u1IaK)iJx+EQOpOBMIlUj_8cf{sr=51aj}+6?vJWBQ8^Hb?&xW)ep|DrHBWW
zBqw%^*z~Q!0vKBz%ar>LQU2YdhSiIh%52+^Hf2l!MbaCv|6)62{2=e3N-Af%+~Caa
z7}EAVy$Mdb+^{3tuu`SA4Q-Poa9dm_LvO4J*N{_-AqfdE+1wyKOJCGLyr*p_m02mh
z?-<(oExqH@mo>m%s_n%}liYvzB4C80FBZit>THOl>#+pSNvDjPfb+SM7anS{=WJ3;
zJ&}2@Vif5O-J5c74)E)4!I!*)GT_9dF
zTGiePSKE~YyLFS|Ytx5j2VYJc2_r){X%$&3r*I&HNTve2Rnx<)Z18Npanjy0eht;O
z5z-6q7FzmhgzL}FN9bND7!L}W|0Ue2^KFBNTtD2cl5b+%U
zmHeH%x%WnWuS!AR6@NuFJd^v6&C=H@e2vom4KEhSRKVjwk87<@6^5W}%`$_UQ5IW_
zRhUPW>JPG&fwIU2atpUtT0Pb1s}twvQ9ia>EwdDGzMnxG?28^-yy}hv*37b^BFv=b
zQbi`uj1or$&8j7t;}oNit6-0KN6*H1XAiK)rog_V
zzo55bY|kcl8Mhri9h=;|lfJ||#a;Bypgp-8-{QTw2H$QH^~s*VzO2#o4pyZd-W0_s
ze7{+Y+q78$UtvZKx|6@hlA*3ux~vzm0{n#Hmu2eU%Db4LLM9aN_taa*Vyv0TUD~pH
zQ`@G=7{!zjJU!;_Q-9~~y2xxgesu9A^?BdGtn(iXeK4u?kBqyoj~64)Gj}|wvIv=F
z_w0&C8%Va|VuitWz`v#~lf7!D
zC{xRfg5N}7%keFfXI5-E4hyZR;|%}3<8f&%%ec^5UXGF0a*2Cw6Rio>^Q63Tj6pCa3)Ji?~2#3`~CPN8lYaWarFeLZ0tx6uNqt9851`$0kIBnT=&SmLULn^YE=
z3zbf}wp?iNlmXVttj*-RKQIgDf(xKOYUGquW~QRHDBoN|lz*;)<>$FIsq+jP>pbv*
z`L2s?iLQ%2{1qg)E*cXruQD|E-4HJDiEK+OBFj}wl6vNP0j1cMyKz4owCtO<}v-ljI`V*jC
z$=(BP6{Dtp)|d8ysubi)R6z}Xr&6ttWE@?)FUz&5lb%>u}P^ab}
zwPSzhyDqdOP)m^Y)V*rZaNd~e;HmCw6-2v&9}O78ceHvGwSxGBT8o}ErgmSD`*n%q
zxV?F#V1Rc8q)OXPmAf+*^5jvYz1FPXRmOAh3edAtnmLc!QcpY~>Q*T8*-)(Y~)%$oBe4yG@#V1A_MYa`vhV~LPgFfz#
z$!b1+y)ZuRj~T1_lsozS^+uIH+ho>Yc*TjHG7(ADqeoRY5!?it?d$z$O&>rbQ|>Hx=J
zEuV8DbF^ZV(<<#!^^&80DeFq#61fQ%S+8&nOXwTXAT97-ri@SW*UhB|o$v)tbp+L=F
z!@LDe*NAFq;1vOWoY%?zki-|09oO!=$QiVNyfo04(msyXGDAC(eY1o``);i+f8+;j
z(@25%6<@#j0CS~BZJz(aT>VIRm_zoJoJ^}bk?zwEJ(j4n`b;SXgyn*{TJndvmT
zS%05<(H#%^$d_>5-zY{UF7fIZ{UaYQJYU+f_t@eOpKN{l45Cnvxv$1E6Ppa{?(!7I
z4-B(skBfkW@p+rho;^dT#2Ms$kOP{cv3|@+_>w0Jc5`w>lEsBs6!HQMw5Pvt|Iz){
z`V!oiKIn1zN(y?59z*jew3O@+
z#;Ye7R;{{Dc&8*$8V&U)mDAfVmZ8so@a%_Pm5Vs}zmO+Ex2MA$!Kn)Ky^)M&G2(9b
zJzZBewwaxEMQe*t$IZyHIrkceSnJho@IRcTuzmJPoLX(0cX25E8nFA%0KN^XqJ@F(
z+=m_6B69(<%Z3>Ttn7s{WUz}#E%Z93*k|t6Z9C_(K4`JG1cj?D>=~m_4BNQpY48y1
z$7n`O&Y1PRNwwC{8;p)=akYHE({}B!uC5eP$EJesJq09T`_w{nTakRtt6aXeo%M$i
zH_#HtxI7n3`!OTumD29noXJF~>bv3;?yhWxFz~H2k^>B1l4zjyz1Wn%&MMKlOaI^z
zE}l;?&+C3b*n`|Xx?dg=6MA%2uho_A@v>)l0da1j
zaXkHP{N#F!1KJFXqf#12TB)t~FiB5?)`yr|cj)=UwPwaz`W@YItho^G-GCPdT$d)v10zp%Icx7Jq1r;#-uSV(6p=F{vWIi0OU
zHRPkLfjoFR5AlMo)R$c`4a5P<5RP8m2ORAQ;b=DRidN0rPWj=}I}|pNWPwFA9YMRx
z<5!Xuc&wFVQ;EK-3p_$g8)OOf1ly9m8vDgP#CcAt+iZK}q6YK`^X{)%vucD|rk6x3
z>4|i=)!l^^#uL_R78E|#IzzbE?;Q`E?@)ULpSLD)abX-uMawD@7e8Dfw0W@?Q}71u
z;i+Nu>g)6?w6$SBj*A#D(jL5ZXS%DL3?LYgOcYFptcc)_4=ww*VdQME>
zunM?OG3y5M9(@2Zb==@Qc~vqk>;3UO9rX{TIg;jT=3XWfTt3Z{LEW;DD7CQpY66XE
z&9gh6FjOq|xEJUtNq2F_tWgbz}3&7}qiX4%Y$Y
z1Y754nlz8?!_PD{D>UYe)x3h{BYeN?WkUh9TX-@!mt((V^VHC_@Fp9#gs~ZTPVo68
zDKlfWQISy)RLHaEOZ=bDXc!`Hg$7&vl3_nJ)A}g#*+5p#7=lB2o{!pS&Z|3UrX{$?
ztS_ALb?yVRlOEgnnDX~uKe%w(htnRIeqcJ~T>5avf!T=*p6Pz!6}#`0;8ri?S>G=N
zwrM!>PWEBviR-`9kt8h)y`nU{;$+tRhg;Bk3_7RB5Sim~M=tS@zo6ld!y%iE_KXl{
zpL7)QXZBk&xE{z{D?kN;6QK7#<+7S3ig4ru@*L`p{>%aGBk*3Ug5HqM3-H1Txn@wr
zFeP7oop6#XFB#8vOJCOq3ly%r-HFr=^-?~ecUSRu5mF{-^wy648^#TVrF&h3FtkTW
z{d>dfvL2MazwkGEZG`^P4T0**%uIj%0|9UBd#CAWr6zjpZF>
z`FPgfS?k@f@Y-`m3TY*ZY{{aUrqb9`n?65srcCXdfeKZhPU*=JI&CsTmaLM&;9_3ZO
zlsA<5zEjyV_%BSvliDWp!vXt|a`_B(Y8LIgmFsQ6W+p>@)wB{PYd4yRd#o?LB=Nt(
z-8lI{m6|^Rr;TY9!iB>LZk07(xO6xHy1Iw@R}vRK5Nmt9_YPUd!B6JDXMKoE(6y1Li4e>klo#!7WsL1b{tiIPD0^-8bcLKrv#xI%i?0YuGB`T5
zI+gT;YugfR{=O(@wymt~=jGWpSKH4WbUln(P+9H1)l8+`wkr65e6E0PDg0CMhNL-A
zvAJwZCbOe}BpjFZio^+mYTl`a4o5nP-
zYDBiQH{xus`i2dT$+1{&<@PzvSGBT%?x-e%n&CV%N#oT#muh{g0k8wv8}>@H&9?CjPBBp{vPoVFKk1m!
zb)ER_1Dk253%y!##H}87nU+Y@7TFM?rqMF!NvnK`L~)Q{K%{tSpSZTJi45cXP5rSN7&)
z!OO$Xq0Gp>SLHT7$_&xe`+3EBb-mxGxKMF)@n+S9idT*nTWmjP$uEuVi*Wb8#9Ziv
zo;PXaRN2xG0KlHcd8{JsnPK0$pkYzIHZ--o}Gy@38-eM$R`WXlZ?XR&)YeTPm}
z1DW+Pv4+zp!n#g&b!dOID$3d9^fR!B+5H;QK9CNDwd{e!!Kl5!ZyCr0<}UTkb*sz@
zS9V*CI0T+xrT)3nwSlhrdD8Vzx=xj@q4Sw1#-3wb)?m%+*<#!^rr4Ux2-$r_g0Hve
z;R;-1*FoOf-1a>@z}sJdCl35EHCZ^z#G;_q1MQOziqV|rhl@m`8
zJs;C5suW6@p39V+C^$tnV$Dr56~8=;D7YNiPgXRdvy^MaQ$SSK|Fi%q8)(0?hD|Ne
z!0RItX9GmLjJ?YHsxl>hVD
z-(#%{Pc43*WKy|}TKHntn(Ip5bOqYawiO;Vu7d_BBH}D-eMR9V{cvfjdk8N~ZL7f^
zb-Qxtx4;d0=N547ni{Nuyr7YLQ(yKk6YP7iZn}=(T(9rGjZSk(CllcuBH><~>-Ems
zdu;z1WZ=sp82F_;&d6m*rd0T$or&zxxmOQks*mGjsMibwYZx(Mh1RBwR1(Kwul3Jg
z44b4quSqwt3ci^-F>bdG@&!*{r7_onV$uq&d$o?MK5mPTWL$6GJIWor%AD@l70KxW
z?a{~nQM$PF@01bR6m^Ql_ilc^*7l7btIp})4j9*9)Y_|$+IgJ97T2WP#dA8^7q-9m
z-4U7XGWwF-RV9ohqe?p0_Jy{lKFF($3y~AeMD^K?O}cs?Y}?j;WpxEI)9OUjA;xi`
z)ukMjKa`+o#a*?L6Ko&wn1_Rs{ABCwVpN!oD>}n!o#Nha46CQ=I*j~34bQD*Y>~*s
zgnkUl%S);Kd-@M`oaNyeiW+EEJN*oF%QT<;{Y<&l@Z7zO&CyT(pD*`wu!Y|7Eq8Nu
z%Y0Z}S5B}-xcA<4X^iUlTk1EV{(X1RIZ|HG*0i-#O9ezhpQ#F@-|s^dPkZYxXM%eK
z9@x%*?&iOhGA5|39Zv*5ccH$H67ADfapRvcahqJk$Q^XYxKI&3kw+rjDn5
z;^9d{UGQ7g66mOdH*Nr{r$9$7ao@FnA#NM?$nv_9IVb8I|Te$s#cG-5Uxga*l$3^)b%9?mE~5V2D@}UI)l1ku9K|FzA!~_
z5>;t~b`1J!Xs&r4nroTIAk8&VEwVk|u5+Jy!nj0&@6m`MF~4pmyEg3HShu>8Z6Exf
zs1ucu@qN}pb|j|{w735UMx=LZODKM}wN;#bl$~h-J=pOGeD|S6C_Wo1KM&vPkkwwI
z77OOyzET^oQr!^-Rf!T_aC2#{ho3kOHO5G8+_Apn;M~-%kJjZFvjw
zrl@GN-9tN~kql*~1LMtlc)**#Z11s0K9->?b!chJ&L&x7{@6!zFD^VU>&6Lc($)gE
z9!IOubtP}$cU-g+=eZmd*p!k;TLm8leb=y_C^4les#3=EsU?x`c!2Yxsw-s7+E2fl
zHAdS)%0=RiUCSVYTGZgK>c)Jwucn%tgIG^J(>)y(`j{TEi}{mf#=+ui7n1iOdlBG
z6&Q``LHLc>jMG@g5OL}y`!7l&vD(l&d}pc;dZDHMm&VqZs!cH;Hf=VmbH1K^yB7Ts
z$HK=JKx?%9qNIDRt5T^jVdual{)=&i`$yG`)9i7w?k
zOu?@~LG?6eF%4`U7bRc>D=~sA5!wdWpY?_D`@JNy+u{pU6I<93yS4VwC7M9`&)1O_
z1bD0U#y1D74?_#WLJRWFCdul+GmqDw?@?amN;&uzeCM!dL=KpQUq()FWdcJ_j?_T&
z3$GvSV0FSnn8yg3q53i($&c4d`8g+SOTSdYPgkgXvHE=#PcvIT9#S}TJa>I2qD=X8|L(j84JMxzoVcT4(Qno*+ZOO6Z-
z2REPU(AIzVu0nW&pHScbwxZlCCT&sxhcU~hYT=b)j;f5H_X9@i-<&BIJ#$XXmS#iL
zanM}j9BJSvPP1k5b)We2-H~ElrfT;Gx9bRgXz|cCv*3}Q>7I0stkH62Y04BvXCBGW
zZ@ofre!+@!Qk0UtMKF#BY^c=**E)zUsI;7
zZKgRV5GyvbNn4JHbhE~@0$fZ})46i)+Lre=&6z@eWuP9CKiqqpT$>ImE4_jA^6P`W
zrarsZ>h$&gJO%Z7V8-iMN6DHN6I9Yj7n;v;1F>J5WS_at@~I9PA11!G&`h33@^d-s
z{WIMS+iC4&izKaHctKKH0-Em
z9{38@>5*Jv+_m)?{05Vl^br&3x>ikl?wzX3tH<#971J8U;a8aF^OGDOPab{(@cuJI
za{Wv-oSm91lrMrD>~R~1F^2wN^nR-=7WQaR5U)-#YHW6viX`-l;95@q)wu|`1KIRd
z`L0-;u8A_l`!Bm$;*GZrB$4r7C`nc~lRFLY)5YQ$ID)UNE>nt|2svfv9u
zSq9b<1oK6otfxEItl9+FJ|PRM^4(t8PEZz}et1*76(#W2T{be`b(llRU;^x&;5U)k
zKmTZvYlb(0N>f?bXM*9{WNXV}kI+iC6+35k=rQsxKLX;$;Y0<9;e+!yhff6oJdo&$|{!mB@fQQcua{d6FekyT7$<3
z-1)e+TFTqkTklpgsU08owY%Z%Ku|F-Gz=Bkz4b)jZnX;4fV!DjH*x|DZr;M=h8FaeMgFbDu-hb@G+?It+i;q3o$Xa!bj0OE}+DS1I
zG}k!^m#F!|xJ=M7J8*h^sn>LEy=~zI(8exJ%n~oh=%+On#xMAf%fBBOYMel{G-9Y*
z2MUl^qG0hwl7p<-_5K2B|J%_HNm%cAIx7hN7yKaySgA=n`Z)4|r_zW~MiVGD*bE3>HL(MFz1Apqo)KESI?pzj
zlYiUgf^UyJx+Djv1^I;QRD4CNm{=2I?O5jz<)oD~84?~Q_@PLIh$%AUpnm;1
z)qruJT!Nj~<)?HV@C8~Mc2Qq(9$NY@x5~ZE>>cdw0ZW+vQ-7)E!LM($5&aEx2M*u<
z{8t}^_439%Kq&A312BkL3#~lsn$|OgU`G6@)0UBOXncbm&mdEbn8&-`qHRZ!>u!!3)XS3CmNpPwJ0e@f+w;bcpN_wt>o<
z1*cV-5kzl?zkKE|)6kCG^7h_vo1~W@odjiW_n_y{>&zFLyk?u08-h6k$zb$`vfvHp
zx;duum+Ch4ud4?KEAzlucRHhdMoj0n9;$_di8AeJXz*0+plC0ht-
zU3TzciwNmoB#fO)8ki?YQs%BH$2i4U1>zeoD`+&(M!*vQ+_bQxgZT6#9}u12L-FzY
zVjp~1xI-PlVCs6cY~vy+j4a_{>&Z1(!=W#Pj~7u*iRV(vROKpi`Zj4u{{_8DK6IV%
zg17=s-I@!iQzbdVi3r4&>iCtkqn+B)yma85|l
zB-m7{Vfo8Q3X$!Fq4{ZrW-1G3eL~~X9Zi}k_{egJ?9|p<=W37Q$FpR&S|ZX)963+G
zFZ>#!Lca>isi
z3){rbCzN}k=WzS4-!lz5m!%#5^!M4bcMC)ZaOzZs9s76N`tr5fY@><+CS7z6vE3|c
zjPB7D!-rZC^GFjxP}ijH{`o#-L7JD73WHyyCo4{i}WS_cQ0JYQ@p6#E6
zys=EZYJ8UK(8xa)pLA8d&3Pd$4aC>?->o1G7@Lz*>5hZ`N6Vzb=g*X()n-+$%fxOx
zvkCNhJhXVDwcy-rk0RF78JFtdHC>EvwdW=YiV9S^nasE|(I
zgZyLDZdMX!Alv_Ce-XwOXx#^nlZ%o#45G3@zf$rBXw^f@HA4`S(VG#;TKJ$L(wBG;
z1HZwL;Y`hP=k;f0oJ>_@X!}jBRP6-Yqa+yt9`TOu(VH1TjyMfF}9BjgL3)4g@M-j|H)c*3nW!!sAgsj@<$ZGL9~Q?
z1&JG{^(X#ZUis8$T4U0Z);S4&iQ9Rz-f!3M_#U$9g02yKa^Jo$)
z@t@4pkXCTzP5!g?CjYrE%zt`PiB~CDNjxa=pFfs30Zpu!!fB9QKsVu(n2f7maGIG%
zw376KmCP5aPJfW9-~$VR#4;8TNq$E{pP
zk|WTq&sH5JDqc7XHdr>$J?|pj5e=t&R^T3s2JQQ@ec@K?LZuZxZcJY;B(n~m8k7(J
z-N;uF;!iFMIYGowLgwz?@H}gsEnrs;!5*{b2wF4wf!a2eafP!kSyE7<;SBz_&pU|!
zjg!vAoF?igpY=p~bkM)Xh9+c>R`lI+ZjAf}TutlQb@sHA(eilxb8%8EBPPAhAp0LY
ze7-=OOxjvoxu5HBmwhMIe*z~rJzxa(X02@|vU?2SAq~5c1*_&mM~Z{IaU)*}wEyZ$
z+Z~+gA!NV8SKZs2WX~vBvyYgy8R%8}o&Q9pO+nehnnw$^?R=V4|1q1O8s%9G>dWtQPDt$cXiQaj*a{W+b`v
z;?;!b^T|SHcxf^0lH3k>rHAZd!HS(cS;oL(Vrm-tQc8}y^?^|7ly6%a@-)b>%!QU!P|jK^-H62
zmo1)4wM#X>9PUT>3Gm0+o6oXQ3e@?jt@K}*gS<}C2o0|I33(oQ+@LHLN_(-AkD*6syGWQB*1N=a4
zPl7lUCqi3U)Zxs26E?CoX2ELGd?Bj|o_#!-@|(oh1R5JQ&`#`DcQC3`$ix`h@sm7&
z*!G5_Pwkg^)+)6U)T-0!f)m@go5dM)1Gjv~=
zTsb{88PC1LxTc=32_&pPXy7f14Bm=Z^@NAKp?FQQD!Ja#O~~MDl^J0qZd>J8Ow{Enk0iwnEku*Oz5x^;Q&T$F~f?zox|oZ;!p|
z3Gi1d>oP6jsSJ5J0Y|0|#M!1JA_Gsrr;mqDYC0dXxr25gKEpM$33Ccsb`gG?v#uo6
zL*HEP5{F)579AOk$>^F9_(&7*p{7rd^S4lkt=$K@Y3ue;rX{v-$gNa@_y*uU
zW8e1%l$1FJew~1mM>-<4-^mzuX$lLxif@MpCC!Gc*N`J?pJ_k)k3i%0cUa&QoL{uo
zX2ATD^+|P5UhOihwyziK8=Me2=c+q^ybrSlG3j1J58I0ToNYl+32p#!{D7p-NLszU
zh3(rY{?*^}<2P^pH+}QMrvztjoox2f-S&Tk%Mrd!n))F;2A*l3_qjAaGi1aP?mva*
z5@|MD@1QGLK9<|0vY%FkYe%kR5({C)xFhl1Bd$t)`ijZe19AWXJof35thsdn-f5d6Y_IYu(*7;GI=G_Jjtx$*x%eS_>8tLyyt}yF(6V0<
zF8D~7q&g0sNE6;$-@@M<*BbKWg}?cyel>CFfYB|;jz!!LL^tTqqJJT&;%N=as`hWxf7g0i!X6Sny<(~e$P%%y%~K1h}-T59{!4?M+5
zl6EaaWj95T#sR*o%;gMOgf9!A#jGXEK^ONWR5
zOkRV=6>|MFZ*P4qCe2VFJEdf+`g-;cXMCzdowESY)o|5?6(%X5&c4}jr$
zp)SgbTr2Jc=l6*xItl`(Dn7aAjo*80pV4p8uml{Bv0(&a@UX%4@SS?yrGA
z>h8$?deOzHs}ZdRPtpj7T1bO0>GP*3vH;%FyEralWj*=adaR_~DR_XiI~_a+4c>WS
zaA&}$@Pw>4A})~D200wN+aI$-ZbODnkMHIV3A`~iv_fP}{NWnW`kbvKC`R_-ra)u#
zS9MN#r4wdRU2jP6cBo^H$+iKfE&+0OKqt^7ye?@F_WPl8QUvs$w9Amx_SYYC$E4|$
z^`N(D2)h#uicZoHo_vqs^X-N+jzxd{e}JUcdBMbN#7SE~Aym!j&*-jyJPFFqIQxnjScu$sOqqm0phB0fNmEZE+ay$t1T!5U**}pCmJQq;1c5akz?Bo%e
z%g;I<(%L0nvW;p;mFh>W>`nexdd}y&n$Oo5F;}d$wt`Me9&pz2@Snfi$n8}LnW>u7
z6-nT(7pw+OL56lgnWF+sJ65|W=?-df)^9uZsg#J5A171X##)Jkg*fBr;!cCz5w_@VMZ
zscZAX1m}z7Nh-?`{si007X+F?Lz#cR(0T>DEWbehO%458L%#)~-?GqeZRpn*`t?h{
zz`_fKR`^Cj4yLRqe34|gx9$e#GDGnu-(OMhHzKmP30@8q>2218?ariU8h+xN(MHChrzB{ij-=IxTtZ`Vb9@!6$XE0-l^1*P7;fi}(nIWx1YD
z5BndI=hO1gOvt5EyIkmZ^$F+^8lyePqUk_B$OytIZ+*O6uT7V=0?M4R7TNDGtly^-
zm}Y%Qk#Nh?Laj@9E$y<hZ)m?tZt1Jm9B$L<0#KD^au7Hu79Yc6ZpcT
zJaP01>_OUZ^Ji1+;?CbFXiX*swn;uHYQDOHz93HxJM@qls3BuDYWUNa-&464
zjuayUx12kHPC=&Z31J(eSfpZZpKa?|f)X3g{bHxfb@IO+I(B&|NibQU2(wI*
z{SiM$dxyn)vJkIXZhsUWEYKSWabF}PKJ9j7d)yRH7mB5GU%x&{F=gy;RhAKK;mfV}ZDw|F6+?LtYy~b0m4X%|G|d;GBY1{~(eM
zQ2?QcP1TfJBlK>K*R(=ABgbq~zHh~)g$pBI0q)Vg-PD%1W4oyiT
zk2rGM79J%C9+M*o4vAI`&Z7ZZF3_WpKgFu+?ygdzNePrYf;1|K+3s2eI_67YFIpJ4
zx=hlEAp?aJ{VG}Wp!K>Y#f(u4KaM3Q4zkz}n+{|=HpeX3I4z^dIr7>~{Ib>mJ>i$$
zHrIpqSOWVRj%Okwk1$N(Fkl;v6ZpcaNON^`efu47%#;@|$NS3&>nsChLi<x1H$-BDSm#e|Ux@-(|XZx^4ZxIRxzE};KB(pAk9q1y_{eRl@A!2Fmo
zk*C=_i?p`IQ)ay+ZuT?8!^)bCvMyPFT-(XcY-TO=;cIh9uOlnqlw
z${sdIi%YfQ&&Fx{8}^%+!cu*lz2Mi%RPZLHlu8t=
zq7v1|#qD0rPrhFR-Fwbk&t)L4v?~Moo0S<2<}Jpr7t!r@;DXB#znIO&l}j)Z&ZAXfmF?
zj+vezz(?bW>+sQ_%u}|2ALsF|h!pjYM~g8tqD8~FXfYx=n)EP}u7mrx
z0fP8qztny=c>GZNgIvV}4&o|q<*IJdOKF9ya|m+BTJLV8nw;5VL;4rn7k!)^81Lq1H7k8h7baBf^g?JkoUVcZbJ=Ws*fc53kELheUiK^M!KUbEjMW;7P+~SK8ceh3D
za`I8)R{ZVdk)LF_UIPxyO`3OPoXaGxm@k;?vUW-u`fD$PtIz91CYv9Y*r^Ja0S-L-
z?@HC(TB-r1APM|beg1jHR)am3$(oYpabqJE5_+)oPb-P^aHZePBX|Yy6>4QV)E-a
z+f97AL=)!SWeczbHDP{S{yu#Wi}-#L5BYx?!XmH!G#>KbMem(H(dE_ca`{4-W;y1M
zBpP{6Ye!R=@(*@Zcp?AZ25I@EL+^Xx&6{x2TQLYF%k^r&rlTOkhm7(ChCY?v-KR>(
zINr;+PxRg}&>v1TrAS2~)0Zw}{B4~3`Y6Wm>=Y(Sy%CXo!`S7&y0ssviNYChxT+}5
z-L}W%dUMYNVUJ_NQJ4GsC}p{${_`i0W3%4hrpS2W4#nw;jKyk&d!+@Dn~BbI>rYn9
zL@rAsLlU&8`Chk6^G}R58vVN+2K>WltX0R^i@acO;RV)b6by^w^u?$9w^kn$Uux5>
zc{%?0u9y7ynsy#`rS6l^N%G4>T!}nuR`~XyrVqk1Cc%E0b*^CPts&ZJuPun9JgF~w
z=>Kv(sIW=)uToe}HxL95u0UA~)wTb)L7M$eX`hRGy&CZqK;Aa|?e=QGy}&8~Urx#w
zHM1E!ieDql>P%2sca``_R>KZJCK^lUZSY96{3cA^N7|$JbuM3>`P}iklJOt$;A>2_IX(vPec0~PF?Akjef3fVYHNlzAxqrIsm0gKytp-)H#nM9@X@&EcIYQ6
zJyyzPb}LSQr0Hhw<^BIXVfE?I5k4L<-uY|DKy_u>v%u~ao1sk&{#MOGcj8txv4MSW
z9ri$@W^dl}uTrjjogE$&)lHJ2)lIrbN6>>MC0t{53H?Xp|-mC(Vu$
z{TnkH^1Xp-V#@m=FS9+;EZ>UhlO$ho1FR$&j@mGG&c8-6%^?g8%N+3Yo`$iOOE|wJ
ztO2;4QpxiF-A#7$;}J*N-JV!R?)S*<@(SuT^|ZVK^G$y26?4wZz4kq+?UMV@YogT;u>j(Cm>C{s-q6$-vg?a4|e*K*0S9`*a`BhnA
z4`<->vfj@~TqNLkBWM`WU3osf@(#}S+3n<=ak;^WbpnmLGG{XQrw?dXuont!uFTGR
zw3ZR&v=@d?cAll@_O^n2m)Cz!vEQ(0ByhH25oNKwozL=rN;^a1#G3Ok64FQ9Uc&bY
zm8d?x>qT$q{op*`qG^%w>Hnh9-G9RF8_A5cj&b7b(WhatD&^tR!|AKPEVhgVSKgi=
zChXRa1wR#FzUrYj>e;o*{1G
z)31n!x$)KQ(EejwZ#{Q&q>f++Pt)1e4_%aXB@0i<`jbb_zvq(ID)kIem$Y?nI)Cjt
zj7+;>Z3<=hstgb}$fyGQn4#j%-Fi{2;^_Ge}tH$3}
z{Jo67SMawDf3M*;*V9zT;tVHn{v(3S1QUC~$^>#N^B|+&ER9@b
zZ12AYtyQ^80ZkEe9<{fX$tQE|W1{CgD#`h|l?%i)PDwZ}<$VwO=`Ly7oph?mL_UmD
zflW%39xbvpI7g?BGa+NUs)wsAkhHBnc;G-b=|5)oEtY&63pbq>h0d++-`1ysk&p%qm>^F
za{aWU=RA7)OW7N7@_64h{4x#&tc%(%Rq5
zx+QL)QoGp^6>=*j>^mOJG%UbPEX_;+CmE0Kg*{H1fnsP8cC(SU^^e*oK8oN>YUBTx
zUewI*__^u}>c_StFPQ>08}euui*~u3`Md(u=um!
zs%xt$D$<@;u+nbX&Cy$AiP_Z5R3fSt?^gg?0Ij4|Cd~6<(ZeCXclgjDA1Gxtc-wB<
z=7$ILSKIzwJOSkj4PgnyGYoppO*-bmsO-DBKe0{F#4x9;Jv_PmKV
z$X3}j`1K1XW%*amo{3WoN&+?8Urloo=5OQzHA}~NQZb`DYX1m7@C1Xp5$EthSI@jr
zCeN$y8(7(-U3u~=`HBB?M0R0E5)1?WrN}Nfq@Xz`0vlTA;pC7P?Y@)n72mCNE*7ze
z2*kp7iwRQlCGRKE?O#Pt4eHXpky?7bvLgHpSzgziyg|L6G@A;
zYo}M#sb^MDew`F
z73eJPljVC4-Os?iS-#&w_bYJ!xO`tt_nUBEBHa^i!^~~!>$x@Wg?f5Fp16Ja^i9Vg}
zza@Vc{FnFI?kTZNlEtXCeW4v^U#YTf%lnjwA_W#1gu)wD@O;tqeJ5Lch&P1SJ4dv|
z=4k=eDN#CIRmWj_Q(&LG+Qz_sz!09MT14RBe9E@Sp2m4*bQ+Qj|7FbtUC6m#HQ3Jf
zt+ZF%CFV&*riVY0`vuDn>Qz}$^A_yD?vFeFXFJg8Eip+uuKV53P=mCG
z-r~nU(|xDiI1+F=a%5)wNt(GpO>TtrwuT=s$FtmkJ}Mjwo8}C2)-;<2t|?=ZxaqL-*AAy2=bv}ad-s5aG0k~Y
zj2g$D_D?W<(qXZ>yxauaau4W~{UXsNV9cA8NgT0BIqf61&A}k+h!PYD)C<`)K`%tr
zdG6r~q8PW*tp7_CtFgOK)l2l6sD;WaQP>UoVG2u3NHQOkVr0nWM#P-D$D}w5KOxSM
zZL4Tw*qOxN6z33CACzSXTH!Us#e-WW?qL47FduL^TcZEnzxoE}xT9r)*2`X6ZF_C1
zaStN)W1&M;Ngk<0Tfl>@vRm)Qyo|)N3l*Y~?q}lOBH!OZ_bYL~NWPD!`zqW!5P?Zw
z&~ERo5QhayK8YuNC`+w-yS{I8^L|jW
z@h{bFHmLp2jwly=eMK%yZ&4CYndVaO>Dc1?o*)RZi)nyIolZ#k(4MSg$o@#y$3ffU
zmKoXw`c5zzrCp}N^;!SSM6}`qp2DGP)@e^>s1AiF
zoG^5^vT&UoMdFb(4t1^4f;Qw5Al^G(squJL>l=imASvpHHLz|pc%4e*(S5aMI
zd!nDCK5dh-gOG<*(b7Ooa_p4Nm&Q$Vk(<)senZ+fP%eL!V2+-w&hQL
zXJ|t-Y8%J?Z_3_3Ac{KwAD`LT*#TD&ToEa}&{0s%48!v5?dfW}J7Q+kkz|L8tw?tL
zzh1W@U?a{7_5%KAtnXve=K$
z`}+sX&dh6GzhBSaKNN4&k@?QIL9I0i>MG%!Ufh5P#KPD)Vo@`5=J2Un;^&&uetV2-
zgpcHh--B<;coja9pc2i?Ujy!hw`S`oPAu5PP_)S8vH+A2y-`lUKl79lp+0
zKTKhl)%={VlUQ_qy|`Yj`mwB?{5I)KYpVxNkxyI6`E@P*j*c?DlT&
zRmCewEb3XGRrA|}!PJyzU>`MA_cc*aeh)DC$?cG-s-L5#EHX8P_(?oys-~O>NEgDp
zRDG1uoi{0?M4JLB>(6mgJqMdU@ED+pClij4S8A{DrIHIO^|#tn@BjBu#(Ddz8FJcj?uPJikQhdt%TWwlAb
z;dRs}&}7Q)X}e4A(;LF65oN$-8sM^i8g!cPNq}tD^d+0f`nB-`>s-?&YkK@94o?or
z7TBL5UZbgin;Q=aNAEPq@e;_IJ9NV#A^INR3}eTXH{BXObi+q-jPT+OutUEG{v)tN
zwqgfg+F*WMfSx=GR>aqa($h;DF0B`fI+!yp;+76oQA;%_0GTFQ4{k;^!ssiU_P%RC
z7q{}DLOWI8OC{i;keA>hn{0pv^=Dtg%1FL*7`4z`7OXXIeLDoXkz7vrFlZ;=n?%`d
z;C))S@W9>1dycs@DJ=O7(YedPxzpd7xHbk^x<~N7&Zip*XH&$VS$U#xm9a*vxyRD>
z6uT|9#e2SGw4md{I){)2jK^zu@Nn2EMR76
zV>PlvAoBuw<>elofY?A!7?k)5t1XE(qPs0>WYTz1jN8jp+Okf-x(zh9uXCN>^IZDq
zjQ>}H=M3!HRG{^}_aai7N-XFCJ*s9h4B{5GD#moC8GIjuobZ5qV#zsG>`d8I%r?X4KEt&UbZ
z-%beGsR6C*T=c@D8!8b?!6j_wmAI+2lRzu4gMJx(qU$Ko$aFP;My6{nBW|bb4n{2W
zuIHqKh|Hk#`(S`3UN064csdHPPZl%dg`J?qH!j(M|1uT+ig%s3$+Mnoty765sHOFs
z3N-FI$Vt{i_VNnVSHyz8VEr^S?*ESaUCO=NyWVQ5V>zi=x!*$NyYT*;a$iFCL(sBX
zMc?0~q1Qvgvffv?{lhb9m2O>cG&8|FNw(a*vcYAF&n&yBG0FjA0Uv`pIpEX|mC)MQAcyFwVS{2>BVP(N8Kc(O)x`k4p
znH}1@{uW9B_x&gZ-1nmtaQ~B(!g_^L2vG4s_E|Eed~V$u{RG4CgPftBi>w2EEp(|^
zL(E^XBWs&RgXbwcr!J$)MzAfP^=^TXnF;%#siBPIwUKHBc-gw-Pzw
z&OR)%D^KCcx83B)6$#L}i$8}+a{6JC+FzII&mQGYS1{Ij=TrsQyV*(b|C?6TIEfXb
zMqyPDPr&1DQ6buA$GOR-CxLOFmNk6QJR&6Uqla%ZE@zw#Jv((huubea&1`JYO5Hon
ze@Y0wJKrv}Z>qjdR6g|jw>ulW7TVt{Ul0*zmTOJewq7$_qwtd}E`w()@s?UoO4}e6
zQIS1jxNvE`f8TEPmU6AqHY!WDGvFKXWQ(3`k+5q^`E1DaO2J!Jh{fJDm_4RT-RCi|
z2sq^K{MT!$g$QPcFtq`+6(F&opL)1jVk}dSuu`t1jD{an^3$XFO9I<}Gznp0HFxK?
z$iBmnx(y-j=-e|Tbt9Quz(zMCqu_(+$ppPFG!yjl$KTQ~i_ge_w;}j^%4}@o-tkS6
z<0QGSV4fX&ztth?L>hPloPMq*ze8f8t8LMzM?Y5lB?r6v(UKgGi@mF|xf{J_Fol)znW%Q93K}%r10`OFc
zQlol+cpi8wv)s`bV3Ke1!yKP%oeL^Ui9|ux*YDJfxYehz^J#k@HF3|`pQk2>me~Gn
zpXCB*2);*c{zj%A@IN|=xV`$v!s->snSDkK>t-^h+l?8gk)?K7A8$JCE6@$0!91|C
z8tO;a=$~&PJXHH^DLBpw*4I}0JqQo*4(`_bWEl@pI;DE^a@fg%auf?Hn5=4fp7si<
zvPA4}!ao#Aa5PpJeB?v%htzsa!?wfp)>@HY?KmpSVD%4&%H_+2x6fn*Ryi^x1T)_>
zLawn)nBB*vlcZMhFQ%R1@9(Tq{l*}?M(aRppx`z=a9h%#HMQ_uFC284n>UKF>FKn3
zld7aEOxV&&hfbphzKgf(LYF3Sk1u8@5{R$uUu_D^@O0e7e*X+$zXVSJ`$2QURGm)Y
zDDPnU2ZRgVJ;09*FMObVJ3eHjCV6rkJ3bWFfhvNwL{C$Utuv40II8%G(6!tD7<2Ri1P>D`3NsUNm^srxM1ZjLJViEAb7o~s)
zIMXuL+TzV4N((-Auli+2d4AauuCnYXk7P%jiDXA7NOpvK3HKyB!hK=u8j>BIC2vJV
za~hIr+PTX`}UPfW^_E%K9wB@E|zL3vW5l-Z0jdCZO_RFhxs
zv_>pK&q{?g0jvk9#5)SkyYf%kQHa4ApG&&2bzT)LG~_3q(Lagv*4%>gaNiH-;l3Zv
z!~IX6=oeyqQ-SFXc85yvCZb3|1J^L8JID%N9_z~yK(9bfN
z=(~Mjs7PZlD^6wU3D;U;1yE)3}
zYpRVzi7~(psYSnsg}$cuMsjZhv*pvG-y_EdhxqiC)9Z^q-ST_VGC#jz3x4fbvJBP_
z^ot~u&m)pH-En~R&H5*qjC8x981&Z_#MzF1I{9tHC^aDpmAgStvD{_-N@>qi$_bV3
z09LonrP~y&01Y5}26_{Az6cGvJ0CE(AC#+4nOAITLIYK2K
z3C+dyNa87oHjYcB74sEZo>d^(Vvb-F^B8Ol#z5Kvt7OgZ7Af)I|Jw5iLDwka_nP9=
zq_?8=o>l8#;~S5q!4F<_Egc6Qxe4lW%|dSo*Eo^j>+Uc|l`xuJv;z7u4i*dk2yYo_
zv4`R3!yP;dyu`sqF$9z}cls#iyf)$`>O=qb`+Dsw%ryJjV#`4Pa)2(J7_LS<*QyoW
zs(0PP(%ux5s1)QYkWqUrJ)=3c*;+?E`Jpt-QCS45yRI${>lyLcIx)5gw77ydh{}3y
ze`+dd^ZlI<-E&2O%nI!lRHAd*x04%{otWLpc`Ar=9n#AncH7st`0}^?P%PuU4&tI)
zmi;o`yW^YSh&z22`4kBlcyLfpthwC-uNV67#x8a_9AEhg-`HZ^6^i(72M>oDeU>{;
zn#1@Z(c`ek2abEtIt%ezk(*Jc9p&0IK->7#4xi-mW7^!GKWaJC?eHY
zSayG+O%!-$H}UIiPfsA`P5*ehq_5E-1+-4R*rojtu|ALHmnp02obo?YwEy!zV_X_7
zxKygqGF3YT5*6^bRC6)=c;1)AzvX>x-=6kaUao=vz2wp?XLKQu)aS`Ixk=1l6zzxf
zto3BVvu{c>WQqJ*@Enk1wZKms=los7g-_5U-=K_hfU#Uo&sA{Vj<|BoC|1dWi$in{4nY-aNhzu!RDsFcu1G-^<>K~LDG)MHR`uhqi+VGEOj{p~aqY=i=4B|&T
zBJ+_u4eZaCefg+zhHOV=4tal47UJCYi=z-+^UJ4b?}@vG!{C%|rwboYeTtE#~#$m|qm~o(<)Epv(s1V7V5kqlpwK1?R
z#nr$dE-1+x8S!>{zl)(0T#l^a*8IOSi0g!BbxgTj_8hEWy8u^Wn=_hyNo_B1d^0Dv
zR^fTaZd~nFdLi7`pNCdBX!xMz=d1lZG|7awc%K9h&26Okc(vf9p9D|Lfs=j`T7JBd
zxoBKvF8V2ji}qvrjozm?kD8q-5TD`anx9;>VqO8+ABvkQP`Zd4FUM7Z{_H7G56>
ze_Qcaia+R$`mldZg@XP0_X0fUe*>2K^4>7+nP7-K#u;`i{3c8M=7civoBNxlf_B*M
zm%PhdChZux_0s&O{Qc8U654Jk{flGJzp@@ZuuxdH>KVxShZ|+=QQI_J*<0!|U=K^u
z@;CK_I~2>hhrtT~N61(=^i^3_1B?@Yi1YN44>vSV!I1UFReuzew%Lc2b#?#h|Lo_v
zzifGE2ekl;8dWgtCX7ctB}-^PQl{s&M2GonnWw;i5ec5wR&Ys#nFGG%?AOK#@q0AV#0pZ<&#C81@)kuPRONijHO`
zX_$~=zYQX^^4UFzS}rh=!t2j0xgXpi8(D;LzNv+uzIPao18)xEKr#w=t*z>+{3xK_^3D089*G@tV&$V`X2M^*md`&NY
zcRe){&^B^e-WSn4@v;0fh$CW2nl68}LwGt+58!RytzVaZt$ZDzFqE;MdlJ6J*saAr
z;QlQ?vYWS2Bx;>d%b6G8oZ0ErXTEH}Iw|{_sGZE|ef+0PABPfsywoh8R5|)zA0=Ym
zEW{_Sm1U}&&$2%u(FST`6tHn2q^evl`~lrs>^J8F3rE_yqqifr)s(CLnXe7tjr?;8
z-hj;e3(f;g{tL;S=!3PHj`h%ITd2U$bO|0Y}~-JVDgIF7Nyv#Js^BIKr)*=huuY@9jO|
z0x%EmZfC+}tRlXOI<`x%h=l?q#jRVF^SR=~pTlhK{+R7q_{*x!zOY^my!I?7VHUP|
zp9NmSa~ZGUD&w^rzjRpPd2^ycFMtm=-Q;F-!bs-(ETm^HcaBb|-UI1b4#u_|V|^A_
z=vhA|qh~q5P&vR*Ie3?YcR9dNIROkbEX@U|LY^4}SqK(cPc}4CAq+)MzlD
zPY8vDW8Rf;mxj6IM5ZA?qwD1F=IB@z-9D`Kdah&_bXR)^v4)THwNma*c(rJDOXkon
ziorGf3iG;TX1g@+NiKCJXNGngxJnC)9-`m@MLvS&p$>55hrQ7n>{3nq*w`7-fH#nD
zjuDvzM5~Zkk#Vg54ZXnGgczn!-b|HvOv@C2K@H;fA3L4mmheJ-@*d9O#ONMPFPUjpm-Ye#0~1p
zTHhVfSO7o91>_|_Pj$!?p>3k82mbG#xC=(KsnpP-p&I-($K$so|K=Lr=3P9ZG6)q5
zrfSH;LXJsAF`ygv@DF|oX`Ffjtjn3nc^ZoAQI*%ABF(6aN3>}(US)W-Yj1b?$LqGOzLWlYA4G#HAqqNYj}u
z2+0h-ZqoBpOTrxetx##_!}BSRq~IBcK@F7^KJeSdNaOUH=+i2S*PdfV9o(!E)RO^8
z^T#D~`r8xYJNhbV<_PFmm$KzHwVF#=iI^rg`6~-xWm9Qkm?N=-cpD)CS{W`7*SRzU
z5vM!vI6kjh#Fx3%{eAHiA5xkAz1RGehx7&bA1&kiz2~fuhV7`eQ^dToq*eaeLcABQ
ze!1G0v%Lv%N^r
zIO~!loFONXv7nkFOS*)m^3&)~G3(l2&m+3rY!PC011{jX0XafjCz{s?x48x&qqvl|
zBSyOBG#7erQ>amBuhgpwtdf(pro6%)K12Mw0~Cp;{tV{+!^@yh{Bw_}eH>-NIg=rl
zlJ{ZhVOV&ML$v!LRI5&KAeKtX0)lY4fN%+jhnXfz{XuCYTTcqiqUWzX??euQt
zJH?)qqW8(MJ5wo&UmYUtUyG)6g7p{`xSpNur_t@7neE2X`iGq^pBZ>BR0$-pGelg)BL@UpcL#VU$cPUW+GxU%okxPKYie1tD-YbIg6_izjol67*Ov?W38s;GM*#oT$R@Y
z>fZYV#ZU~J*%#NEVp>(3>e;Ne{?)|n{y>IpgWa+WC;$Da4QFPE
z>K&@Yrm2U|%#yR6A{x~mR_2K)qbW(1Wq2pW6Bo1>F?SGQ8oyxU4Sz0uil{DEx5us;c~MeXYeWT
zI9hr0Rm9}olFn4U^%di)kHWiu=v{K8ySG%6L{I|Z+Js#2#<0mvgZCc|ceKD70zEdcSlor|=0#=Rn0k-?~nb&IPzRNJwPtIBH$2
z9-RF!MIu+r`*Knr4ygrn90ut7E~8Hb4O+`9mXS~IQdTixV}Q4kJ_TFpKVei_+9E*_HwREU22Fu
z1-cO&)s$Mu^jKK@sjaYbMGhOa)iaUs6s`vF&}ubgd1}b)&iLYL{|EVDc>6cp%*ATh
zVY6Xbxijem0}8fN&%keeiC6)kmt6MlFLk_qpD)fb4-xObgl>TECn>w+mz1gelCqmx
z8Awqqx|!WKC__fkr-i?_&NZkZIlg=?>Y4S2pzAAwt_CYwOPNbZQv-^k6S44C2yBY1
zrFmYKXpoL3z*i6+E_*2SqKL5&_dpy;uuN%!@#2sC^`g74gRAd&Zh|2O5;wbA=0#K_
zahpsMx3c}hJlLo_=ev~~v6`OmccxuJ{zCZcEz~ymV2_=@xyQ(xmd-YMPnwaRmd&ZV
z)zd+5#UFBaT_>25J+cng2hh{Rrd{yC4u`j!xRhqj%(M;wJv68{Bv*>@mWMQ}N04-2
z;Xz2%m6-X^ZK*a|36~6OCTK&{DR_^D-9JCN!{uUJ4aYA=}3E4dZWJ#y?`(qk$$kS;S2z4yw^
zrw;#9;A`0C_NN48n-R<%=Q)D;{seRFWqh?$&V@NRJWVW7G&w&IX;^wfmzN+%8`hdUWrsAxm!4RkR_Ds2JQ)e|$>xE2hI_YPG%
z?}-oD$?wtdYmco@1dLw<@20tG+C3-M>(&U!-$a?7gb^emfDHUaYm0`_<>k*OeU0-`
z;_KsaUjfg3`fb8*kNg{!8mzT`C_7RE34z^<{2#!{*3i>*?evJ@CZA<`<_5Tr}baDp#B-`91+OE3+>AV(ptj?
zJb2bO&0=Z3JExtodahtcIEWL@^=f{6nz@wStgklquL^D0YWp!SyhTr3ur)oO1qS&5
zKC#Hwb8Bnz`7MraB;L63C2rPk);jA7>Mh+F=9s(nk$$|fQr}4Xtu?~N?a|REtWqOe
zz9Cfhj^hlcQAftBTl7S~E3kz#wsMevfjbamVS@rK!Zz6GO}?4mrccHV{y3y(93fG!qEwut85}|!GB8Bu%b$Zo&b-mW8h@<0mG!|5;E}brM!_e&
zE=e_gId_$EmC)lm#F3SZ^$0ACVK;1EGXPwAyZh=7obeO1G3}H&gpVcunB;!2S4#z-
z9I!6Wmt1t(biMa71VhY`!fnp#NyE(B(qquO4|(J6>Mdz(K{?Mdq*t;YY36bz^J3&0
z5i0bh%}NV*d|c@?tNFpvkmKvL+7wQDB`CizooKRRHy3ImfEQd^V{aK}_=I~A{OSS5
zmA4DhK3$%HbMb4{a!mY)PFA5Nn&n6gE&(t@NOj!|pPx=>T@uST#W>M0DRkmS4`3yW_O?s;9U>(P&S$#1U2FnyW_Sv5q*g
z2$lhIPmT0O6i|4e>lAAua-fQ
zP~v3*a;?-PK8HhT
zYl8>-S*_ygT0vE}0{YIrM9+VIN8hpUr}y24FQS1LVWZd(qKEZDVa~!3{ZE&?@h=(b
z?hxwS-H5wk-~ERe<8zr!FDO)P{hdVWV=xN?Fj|@C%geZNse19tpcAU&vrH>03OgJnB_QVD3R^PSNj_A{kPC0
zlr@dK>B-ZBt51W4!Y)`Zs2N!w)jEnP2lXmOcd2CkQwX>qJmc^_PtiSj41V2{Ox1QS
zbOr3=sE%Q2;t)0CEFrHaMF&e76B(17JU@LTv?XhA)s_@SXksoB#Y{HhvaTdZ@l0C6WBiakIdcT(8&Tb8(!AAZc8v~aZ7mzqf4K)ao2L+#1)6e$Wk3SB9$
z(=YKUKh~{?gSu7oWNE*$Kh@hpz@_*yQ*(l?2Ofl<6v;=FomICrHe=BW^0891yYQu2
zZG{&sQ3c@44P2{fwNvV`5GBwvh^SS&b(t*V5;yg%R(63mjI88u>U}F`{PjlsLw`vFMun~tmGskb;tXLy#|2CK#U2O@@DfY;j
zxt~x3ec-b2o>7%+b5qP;dWPC1`tLuZdFFxYA->En{%$u`+Hgt=JBQQgl32jF%r`C}
zVqhpgMA7E{?JKM26?W2nSa%^2dBC+EZ<%hz3blEtfJ_jxTy#Iy*vFDLM8I2c+1j4T*3(EPmC)hk{Pfj6}CbOzNmc$THQQu
zUSgiL;V28-0B)jR6GNJ{iKNsFSnVsqI9salMr>5%py3fDh34ca{ML3V_
z1I0D58OipvfK7)QnS!99HgMd$#T@0b^3{%W0q>0ADx`2%>k#H$WIn{`1XsTB!x49|
ztpwRS8frtO*fX^E?E*>-f+kV+haFp%Og0y1=ARgrK@bjc2EPfm?ogmg-VY<~x9DFB
z+w?IVWP_DkO>m{L`qnwyZ=^Zv+m9ovqt6kvw=I(8oP}*G>Fbg9A7@2a1d8&;F}D{K
z{cd3aq+%WTZZyBZk54j_CIFw%+dV>tf=`qZ9lxjCTSTQ%+zHA;*hi&N+rVk_AT4`U
z7`kt5z=G{Q=e=v+bYe}0Lu$tILxF$t6sZ~6vSFX^kG-V80iix1HA{F`!3NMRo}#&;
zohIuVTZOM7e?9Dsp2uC;aCT+vVKH_hOR_P-6>>zX{Zmei13$Bz6K^+g;+Qn9JbW=H
zjx)eJ&KIE{sH}jy>8JGfE=LKUoIOdVt_V`WmcYUVM=B_#`-z|gM!_Z=R`1*BJ`MK<
z<^EONL$B{3OSW_3cDj?b`>SuUT3Zc0ezCARMu1M=B5o2^LsM^orrsjDgw?X$`fBL$
zS3{4#8hU(syBcp-Lyy0jq=iB9u)?xm#hj&8CJgaQI(lSj8mO!qX>sk@%1#+IjW}3w
z6JLt_*zm~dd68^?71+J!E5Pm-71*u7ZGzx8VfTxG*!#L0tfo3xX9E{4F8SIz*9KcB
zoShe1RU0=b-eF|h8U6Gm(8pq2?_p(~vwzhe-WUI(KW%ET7gS-+?*Z#!lh_CA$KLAM
zvj0qL5QP8xPeb^d);5Kf0c61dU8uZ&)#GD<^WqN`9}PtGfku?C1@vzUkA?i+gG{=`
zjGTocvoI36(9F!27^jB>mJ5~4uXq{o
zCpWbb#D6X9rBzU%2xPV@^DI%EtDCDdc}t4y$f=&voR)GR3WmA^F{~v?{?Z
zdmovX_GrwlJsRKs3=cssE1;L%axLclqROJ!w5l%ng(6>=v&gNg>Ker=Hg3wP@a`D)
z7@f8Zy+XPBCA%RjquXEZ?ZQd5G_ByzifFr!`;_HKfSE-74{LtCW|c9jW}5^{K2TRx
zZV#}*q|lNN5Ea4)y8wbHZwNyJ@CE@y6mQbZxTpN^rc4;Bz?+rJMmB3s#(#Wk#P6qS
zm36Y|I8n`*Be~dp>lFJZMr|sX;e6k5-@3PDc+)mlhBvnXch)d^(re#@HS8EKjXl21tqCQXN>FkXjnM%E_2wCR<
zZ*I52?tMA;^_s`mM1vlOJn~tVBBVvMg%XW~bHXDYK`H7E2c=Z1%zJe{K_e}EO-IVU
zrY=XL2Yxn!SbXoc`5U04=EcpL(&X#}R@|g1C2G$Po&Kz};mPLYI4zz(b8}$}vW>11
zY(jAL$7vzCiMXBap{GQg7Wux=gG_Si>`hOb7vWQ+At>N^5$#z-x5g4h5K3-^lU7_4
zH+f$KEc!EG5yk6zQHE46!uti~@#n_h7W|dqZ!7*vg%=IAL9oiw`Mc1L49FnVpvn8-
zRevw?Kpb|}gGS)!A6XX3c&h%t3cc*NpADjyYX=a$yb#g;$`_ITZf+chkehl4yaLCZ@Et!5@{QrP%mi>ss8hn-%Xmsuivr0YK4~r~0EBw~A
zck~X>g-&Nio7~0Vd+ql75r2RGIM6h8s<*zOUR!s29;_BjA(JLCaTf$}R4;6k^<$CI
z{deN{-Zj*BtEb`Q_de?cI1MJXGF~bCfBe#MQbdv*bzzlV0!y26K`;+74+{=
z*a1F@NRkl;2laWN8;L&gx0wIn%4+HXFGYi9hb6!ZumoY+w+cTf_Z{1O`=>wlV2!()
zc=i0>agEW;0Yu`4Wyt<&p-%NeWK
zz4h%(+KXJhz??-!2y+;o;ZHOboT{W7VIH8gcu(=LmZVmLmatrh8Q>EesSFN>E?~XTt6QT
zDO214v1~5`URuMa`BH2C16~@oow6Um{&9Xk0MBR9m;vah?!O7uP9RQ|Brx18M0=Ha
zX@5SL(u~8z-(r3`z*i&gk?zk|x#XwFuG7H679J}`79B&7l?bt75%c5S{E|b^fT_yy
zygHhpoUY`1Wf8~p&bFGGRW5fP)3V_p#R5yj6VyO`fo$bI%6>|@Rjz0%5xvEEFLJBE
zj~I{+cemtL0bCP@^=5GR8vCNd%c$zap)4~nWDGMlf#@oNd@UweQfA0>)i$~wBwu@6
zSr+sbt|M5n(7S+>ruV_M1%Oox0HL0ctqT_bK4kztW%w;77g#~TagYs|+j|Bh6cc1-
z4G%l(do0TDyho5*(*N7^J8eVYwqnK;?ABYXyz{X=%nfL1pTlX
z3UoLKJQ-i!A*D%vc@lD{8!@L9Q4c=
zcm~TIH*~5TN%|ofy&O)Iy1y)Cf~0bbln89{Q%SD%d5R#m8POzEz<8UpRsef#)(M{7
z-~sS-mn!V|&(@2#q{|Ce{7k5pRv}O)zW$}vRN_XHH8MB`3$3RzTUgIn{0$c}5z+Dq
z(&*7lc5iUd2^-prePW=9vw2*+601BfR(Gvp&bL^SuL1_j_}fl9Pr#ZQ8rmJBZlj5rS?MaR|My)g@%yf
zW%U1oK=(4#pCm*5a)SCh-t(6d`eTHaYFD1;2H8KhXSH6w799=V7j^}=6L0J^_FA};
zqnHq6Js7u<;6L3}3+$Mw#REfpWj}P$E`mP&!BqiI$JrYZr>JJ_aHBQu;0zAX(mHDT
z3~nqt!wMA1CFV{CWWArDvPMYg?DP^_8|C36AA`oL;N^)3jlLPS#4CBzz@e@kAO
z{|55*Gy{+A+V#wYl!G5~jiA2;c$qi633274lie%Gs`WU@mI`9J~=Cjway&R
z912P9_$y|kf?-Y?k&`$W1PmfEIU!#KNzb~WDfCFU!g5yGV>*0)e*(ILTn7#
z7HQ{1<+?(OjFo2U@1
z(8>7bSs!!KXvkM<)y@PV)?6pxH-r3{Q4Hu>M)znold@iCy7#iEKFACZbSIZE4{y*(
z(&cjXS!S(9*P6|&McXcqbj8(h@-m%Bkw3wd^OqP^11lwkxKu2=!!(A`8api7ROI`4
z)Wh%s*~?pJ<|2yBMtJP+U^(LfmYaEyqD1V-5^Ho{s36i+J0_?!8#|B
z<>s)g)i8n8oqmbYgeN~co)tsz&72WzUbt@FOH9>wzwJV
z7~?Cs1|~zPwp#0F_!6RI{j6YW|a4bGh~)n-`+{
z`~{}!tHW%bMz;XJ&Nr|c{Cb{AUV>k|ZUM?>)w7xq-GcvRlAk=xYB=436-=`E14Q=F
zef~0&ob6%r1|cicAcAhtU=1RgQun9JgLMD<-$B4ngIqUm3_5Ub)g8K*ZwzYx)u8V<
zX#%^Ak3Nhu8S>S?Pj8@^{#e>!n%a;n{f5y>y%ue~kejUO)Z2xzWVOb$7q?!&J8fs$
zU^xQ~JIDFap&uuQJZh53ziBd-VG2D{Ht95Ml2lp81bvBu72uJ{rwDrI`^j
zBRtvsEZ*G1Yz}z>v;HhYCtAB8i>V6FVss1FGv$`=Slz;KR<~e1Tb}z7PU&~hryH3`
z;Y?ChPXk-vXej^`R$p4*QeZU+DCA(=~xPf-5xp8l!xAoO72jRs0f0
zcQOyP*W;>T&#o48>v8&9ASDAOYMR7+32h(vP*8{I49?d28QA?Uja@!L+SVmZa^4cg
zH8&qJmXo*&>>{hkp2T@R4=JF)B>(9v2H6N8MNPoke8ub(bV5B-m3>+E|8%BjGgX>w
zW;(BH&1Vi;#oQkB
z9qnqLG$5-`;CWy7D0xZK<
zd~$mhe&H*?vMgrcp^YE81i&-kbNXtm>HT6r7DUPXm;G*nCBi5+@Gb`L?j!tSGp`PX
zCd$T6BB+2bt2Dg~G|P}a4u#}#{syt|0^(Xi)-LRlzn074y~tc)HXeSaA4H*?W&JrD
zg8G4Zm=ul{9<4{#`}b{CLOmd+9kW%z=>BcTZyvj(0<)QomXwiePkPv7yN7k9W6hxx
zaiwe6MXN=&8!J}Nz@fmA`w`@_^6ZZ_y>0(vF^%=xp5U=g!aT&7-nCCH_LYGr3mT`h
z*~?Uc%GqI|k(FCE%k%b(+BvV6AtD-TcQd}RZ_>w9L$Gh?i;?89#rZqD;v^m&xkmo2-Xg}M+Nh^AZ!FsM%JeKS`
zh(l~!l53=E=2AD$;9FxC_0uv;k#iYl@2Gpy0H4Ivwn@|@$j|14=-K**qcD~^AqM4F
z*@H9v&zJ|JTVz@Om#}?EEt^Pf=A`25Rp1$iBYUbm@($py*RI&Jp&w-$C3x(Cw<^0M
z<8XEKVDQj_CH6x|S;M;+id!Qj!3#)r0iF%jUm+u;YOLv6x(hLQl$!W7`1K9Le07b5
zT~gqwJq`8$my>qstkT3GZb()UbLsTTSBTSwMt3my5?wjlHRNo1IeUpI)vtV|JpA0?
zRK~?mU_vp+k@bkPUzYJ^IlBW|x(Q6KF_PCkUw;SYCFaSxm`2VtftigGPk(HcCNO_8
zz`}+(D=Bp;>!q1Wbv=l>VvhO8JjECHaP}F!|NWG+MtTdm4m2p#hro0Cj@CKqn5@Mf
zhj|_xE$^th4?}7(i@dUWSr#47NBPRe9g(&8aSuO>T{Z+-L4Dy%{{5x*#ciC+N_Ox}
zZp^#OK3cE5**z6~2>~S=0ZKLklx)Pq!0m4AG}vw4$u;D`#$<;vIlV{EJ9XW?gCae4
zp}nN~I*W*>yi|pZ&nGsBwjT9roQv)ogui1X=$lmjF^shu^VF|d~0pIkZ6+gcq!Ulo^
zcb3zt<~*&O-DLh%t18!Itxs1+n#_NG8?kY+$%lpSQQ2kBC)bK7Ce-0{_sn4H-z7QA
zps8pbJfw7~+HSfCdkx4J@RYIxjr>sA@uP;%I=ovN>Cnb>$C0%t^4Qrp=v~P&ilXs;
zaj`OA9JCjFZOPF$jiRNS*)3^{y5dSC-Y9E<{d#vEGukJItBa05v|HL~a}Mc_BfW5<
zgCe9JI0ju6tOw3jw3?M2=nl)7KOKy_!;k=qTKbU
z1_+Ti?@p@1g%SR{KHUU)AO+@nv1YWiGv68AAHrkB5n=}=Yx{@bL5m*<~mpY}RuyhpVvN_P+C
zEK%+|*#7t3jG|Li-WqTC%RS0Nq9$8S%966i?`IuOba1;H)rzgjc-xycoV`xbvWuB)
z$~8h#S+?%Ao%USVO6LrkY%;gK4gL!nf-@ZqSJ9}}O4SxSuT8(g;3RGGT<@>JP};U%
z_RH`*y}h8PIk$XfJFYrBZg5k8%=bN4HX8{OiGOSDUgSU1S-pYx_4nev!~g!js6nmN
zQ2%|P#OTS-m5s|MOYlk?wFwAvouVKh<5k=xT`;7uU-Q5J!56o~I6VMAzQ=l$4Yc0$
z7WY5jeHFfTW$SW>FWYmZ(iReu_tDM|%LSG)X?0HPRcgxW^~D_s8wkz&B}O^zQtx=X
z0x|Y<`;w;L9%!Y$3#}CX3mWObligjo|Gr1R#BkCu8Y}C3%RXg#6Kja`70Y(L@jd0;&$Z(E;5a`DKj`a9y`16%%zx%m_2z;?eUPf7XGV~c1Qr1vPQ}!
zCC{H+rhYVi_2PGL>ZugTQkDAO`b_zy<99>iI#%*Ssc&dMk2OuTKUer-r!sas-Yai$
ztUb~Y*2gd5gHP>h?~vzG%lOrn(f(RI%~T7d3EVUNb}!!&Xp{FM%YnbNu>3(XTNd)o5&etcemT!N4Ae{X;`0+iTB+D#gKrejy2))SI8PbtrJyYBM7p>T-f7nge
z-qb5?(=)q7PiZ%mYkKRTdHKHYEh2!W^US{dsrZs$nE2}XT6_;_c;NdVl_)*`K71v6
zgG(gl6Yt?)*?*3=i}|g9g3+J|%JV6f{j{#&(!~8@B>9a-v$uzlTV31pZmtnjbm#U<
z!6i8Xe6psD-m2vqP?%=$U04fECmocx$(AZ
z(f+YL(~D@Y_keD13<`_uy_c?)Hb63-Mb*%<`vuL4QRtVSeg3ssj7vU$TWp=NF#^
z@0juSdU-Fre5S8erOp2RE4TLS^!M*{pk!s9wN=ARkA$u<&wG8mUDH5v7Z>lnZvL`f
zt?P+q8jZuxbEo2&-$v^+m#@=X^K%}?d{JO&pTSo36-13^tgZ3b1JD=1a`VQ&1GP6I
zXB_Ql^d?=y@Y&<-F0>*`f~kd$7EmSB!htWj$Kqk>gjfJ*gWj7joKl&+0;gcx^F?B5
z55vucHM#&T$F>H>yd8Zo_p0RmVHb*Wp=W&g!$7;By%wB0EXoxy$&=1+x&x#Y!
zqO5MOe?Pi<3Y9t8emL+oX@;zGdFFMZwrA<`H9aIT8lOkI*sJWwlGb&(#=Eg2r`7lS
z>c{)t(X-ZH|Dk>*(Gxlst{&mW#`E&YDCt?Fl)OElX
zC4e7y_b=ZEe^CBK1^OI>g&YqF8|dNGw!40z{7NcUE|;aclrj|GQBVb>K&ZrfFg%dOifbQQ=P>L2Z2COQON}#pCmoZ`FXIhyk6mR}w+V(|0;p
zS;9kp|Lc+%VMjcK4%9+pDjV5%B9vL%7}PrRG_@m3dRw#qNcDhoxg*f#Pn2KUS6+I~
zUmkJ8f=3s;D$J6b(^#+A
zqUsA*{(LFseq{tJQUZMfmkKH%xYm-JBS8Q4ffc}hfeo)0X94@ARbVN1tWV$c$DjXJ
zKc(;6Y(3YS&nn+m_`i*KuK%~eqp|!Z@GYYB{g(O)TIA{e<%7?e<(`}6TfO(m=SCl~
z^cTwC-B(`tjlcYo{^k4i=dPROJr(!(`(y53zF&XF$@AQrpGS{@o486q(WSg+sr)f2$+yfoehEb$aLf9x=no*a#nS3amW
z(HC)Pjo2T6I_&kW?U$Cx|nQh9}PWyqG$0#fZa`
zYe+FnD1$s8>5H>>n<{O5)&c+i1w0sHO%G)Z2Wehu9j>JlH23LqB-VH*Vrugw4WEYR&An#&l;ciy8o+@a;#RYe`unOGa}-+RBtf1SHMz6r3tw^qu$hpF5>DyZiN~4ZdO{{5+Pi0R1X_ZF`_!oyfx!
z%t5#`5$gUt2m@OaNGw%;zBf<){*@HD1=v>?e*0FSt|ZU`fx2i9y=fzUVpc7<8b^Si
z!0aS-{yEXM$F7|hH7v%2?>7fHSlM!3-*l%k2J}QlyWY>sBo(fxv?toMO;N*)Jod~w
zf}9b*?rZVpSL)!el9mU5^^n8G4}op)5Xdv`T2D1}0{i#%nRfknTcurFAGO7|f5Ru0
zb~+nx?CUENXeCaL&l~7l(=&-S7eAW8-0UCpoe1nkbtjFu^}9ZJLi3RG6hQ^VwkdoM
z6qWK#=kUI7Zas%M-GAss`GR)NsFo!qzQR?jWes!ZbGzufz?t(EZp(G?ZK_o#PRp@<
z;t!3tX&NeRh^VGNCZV276_DNTu`6)Ee%WU!y$;DU;uJwXoU}h%feCkQ53VyY-#Js-
zLY$rknyOr^KYxGN9P`#wjCnl|?(3n_08HW@^WM;DLN3en`qLkPb{3d7Vfzbz4_Oiz
zDO{*-ej~ZbEMzFGQr84`+HwVuMK|9XKGX)B?J72-@
z4)Do;Qpyf03NEXxrY~t>xg1-s^R7*OZI>i74Y9LlGVp+ArXG@|acb0DyM2%Gnk>_EpNk6vN8(jwRe$zx4%Wj3
z5@HKO>z1Z&zrFXe-QcTTSp9H!pe%9&qO4td3%tu5M3=3({$5RB-xvD#J*|T;DRnC0
z73=OS55Wk_Af9&|^A)c11Rw<ZxPZ#Vk|)`x#;YP%aqCwxIcFpCi%X25xZKZ14LD
z2mbwAL!zw&8WzhS$nXlEeg~3@V_z8nF~(4IH01LeWbVpmbZQG?HX1NL%SwDnNikp5
zZ8L^89eX>3Boh5IDS*H}(8(4eAdqMGCKy4GmNQE;%
zgeRP}_q;AOqd7gx-H2W~md?=)uxMmUFYaMB2|V&LCf*MHz{METI0k*ToT=k4SSuXz
z(}&L@+9za;Vx(+KsE^AetI)ofd90CqOYLg1!EWDd`2G^)#O6}3np&JUD;g~#%8uli
z`sk2u^hJvNMM$m&P4
zqb(UV-9M%+i?6iDhF;wUeF4!Q7ka5yyFl2mpnCqYBend}IiHWut8^&TYiPvIy1a%x
zhXUSKfVVpMY7NHdKnGYow7Q?QUy~_jWybyEP14bP|7di-?VvTruCkQwx$`Wa^_l5W
z83&Gz@Fg{cQT`=m#6RqXEYzs8!zbS|1r!SDSV86J^?LXdfewV!UO+?^8ACABe(aCL
z8p$KcKjv+tde17mLPNMh*^ALfu`{%P8x6nN2>S!_j!e*EErNGs*hQs(*po?}T%{w>
zyVx?NcPj}#y*tM)T2`_?z2#o&o6;|T%WlK>@6zLU)&
zOFO79%QJO%8;Mq_`R9MYP0(p0+HbtgK@uW8^S{cMU%b=zrSiT&dB4p6zPj(doJUGN
z2M&0nG;#zvG#|}rNVM$(7PLz9)Fnq_Ot5gOCyMu;m$2W~*`>&1Bl8?ads!uRqVk4+
z5o_UGbR}0BEgf+6$?QPXzTjH2eSE=eM5pS!VYteRjxwe(1~KK9634_uc>h`fPdP
z$9)c!`}~FNr~5n^erC~iSZ8(J?}073IVTmU^++>#6o=XA4Ud!%H~KHVOy9cOGkliU
zzFCRr_-SguR)=>WG?stp9l!y$L+|GG4kRqPQO2UXjV<5U4Kc`7KL%%G-9^MfCJ#Wi
zeBefS`%%U}2V&Yg_rP}_kt*^8;u*x-&H{@rW!x3e3FQl)je(trcc&Q6B5wL6$eZ9N
zFr0Aw8=oew9c`?#?SkbxwNND#AqT@^=-0feWWI>nJ3q(%v0WTB3R!!edlhpNgeeFP
z(pSn}Zh6ROdHVC=*IqY9mK`Ac-1*!qtnnalb&Cw)m7MppP7!41q%4dRvvbxv#ErRg
z+0-*(iO4}8;4pvbg;p$0y-_k>_o{>HPeJ{sMs)DT$iMc@WQXLl3~XI=#T8{|Xy1{=
z-kdywE^RpT)Qdr`{=MGxIQ5&WtK%^9L(VY=P#^58)$Qvbebqu6w?<%gEB)WV8c$dA
z24CCp!qL(m=pfI=-S{rDruQ{C>vmQot*iy2!+9?jagta=0HG1wKw99Lc*v0Uxh_IDxw_#Pr9Xn|k
zcaCED>PBM;W;d_{cP01Vfpb5W_h6oP@Q?SPaU$mPgRy}ZQHM5b<2X*=PuOu{?bdYL#_P&PV=VB+7Y|5
zn_qipjvX@>huz$^{nAhEivz|e%qcH>m_uvifsRm;L2jpwjNfbLgPs
z0Oi^qI@yO82yXBNtvq?m8?gmA3}=t7=n?zB#Io6}oEu#1
zb|=1InmsKDu>Olu1v4`-UHgciD4D$*LEi>z-&{^6^tm&wf-a5FUnv)w?PPO%(M2l4gQ4!m{o5fT3Pf5ItB+IJ=9ta*ca7;Bw*ZSJt*jnkR9>7HSEZ5c^{6pB&iB2}9VD`1!TuyD7Zr~4h=)&rC
zuC&Q|t*6A|TD6kVy>Mkva(eZ2-nr7ZvxxKT(vc-iHA_}BS2iF*=3qV)bE|G2dgTWz
z?4tZMit5TM@HZTc{_C#528w=790GaN_hcRAi_0_|lgz#f^$Fx_)eUG(r?vH)1B<9^!7vNJF7HBuuNGpIA(2fxtQI<7uO>K5{^pv`6|RkI
z;F-}W${taFlB|h`FYP{9EMn}99?o2RAtF|P!h;AD+{n!&8?xwqZPQMYlrW4ab;wnH
zar++@nS0oQddTY6ihMT{V~Rv{$0-*fFO0m(JYp~B2Qa>*2z7`a)^>3@>2h!O3LleQ
z30ch~jF7ElnzsLqo{*JLZ=4to@7N$bzUgu0oM!0v2KAmeh{`PVu479_>JI8$!D@FBVN*MuV})ggxIr>RG&bL3~cgd;fla>gC)=7bT5
zO$G_#5)R|_?5^ge_L2)d+>t0o{1vd`AeJ#R1608O;a9^$^yYAW7}c~tMXu>@Lfyvd
zC|MG~d62bR9%DJ|fw+3y*_~0NN4V@+9Hd2e4bkstfJG8Kr{ozidpohxfH^ziY#bv=KLo<06kJ^P_yj{Q-L
zrsdOHN0T!~`6jGprarWh)~53=d2QYhDzmCW4DBlZ6M9-WUVgeqs7(1MVMgU7EZz$)
znMc;c<9wFg#NXUm5h8Jt$d{1L;k{k=^$M_Wm3HF&d8r&vcYD5^GDebKh$6QaSGB*0AO}9y>E9;{ffv;JwcQcyZ&Pw-i>&wj3QM#A4mHQR1<9H+Sdu+
z_3<6;#lm+azZ(+)YdY0b
zbZog_TD2#7E9l?>Yom7BL8(V{&VTsA$MUb#`D{l_XnWM;8=Pm<@DeHBu8r!ABTm|$
zg1L+F<&fUH(3D9s=YG692KhOvksaEI%pRoB2pysPLfn4scn3pgl^<4MQT9x>NIh(^q*jJ
z+X|&-(ir%1esBe92H%tu>*9=cjJq0A$O=KX+AZeq0tFD%mJMxf?qVLU!MtKFmNU`s
zkX+3X-YB0@CPJs_yxEd|S@0M#3c^euBdY_oQ@YNY&n*?Sq;O9W+x11iQBqy8Po-n(_&nNJ4y=0#Y71$y%@
zYoIriK|%ZNv6`kq2cVo)nh(S(TS{jVzR9rQOjnb=9M9|S8O`X7WPu5ry(MJrwUMm7
zH1Qrfv!u_!d}oq;O@zi(reMipAt`f6A0175aMoePFWmTDrR{FV0Q+zg*<$)~2401w
z)MeyQuBWp}R8EQk+^6h8++s3++XEg$RI`v(pM_qJq}0dXfL<{Sp3ht^^j*W@8NQJ`
z!*fQw(EiG(8~@Q$eC|NT@RjgRnAN1TJldNWXc@5~=HSfD{tqm>Iu96rTTl8CY8zQU
z&Q@rwkB-7!(=_up)oRXUV78^0&o`=(S%ztm%x7EGRso)nAxWXS{9b{qpv^BJ0=Cd3
zn12UYCY7sq$bCM`h*1aN4Sf*(KEa3r^?lH;N`K!sGOXP9T=Lt?S@cxB
zKPmC{O@4o^Sxw|qKeE~VDC7n9`UQ8}X4yxZD7J;%|MTt&vN+2>@2h>Nx6&4Q%p8Vw
z;CG=v@x*CHbuh&0kD9F&F?sW?fNunNNv$W
zX|)HJqr>RLHV3@?Q)5I!r_}M^#HBZ#jO*MHcRjw+urPPX_%bm
zqX(raA5;rtnE#Krw-1P_TKk6A-h1|J5RkzUMhq1h1>^3RNy@3abWmnSOwCHAI#%XR
zsm?L;lzBYokl-+kI3ntZBc+9(Bz@|nbE?||C@_9YCSav0jewRmm;zEF&+pnB)Ozpx
zdEV#!t6+5kl0v*Qt~FL^8dDE
z^7AY^y?8;7UTey+$B)c7^jabtadnYqgu9fa|A+oflJLCa_nBYQ_3HLBr8zx&;)#i7
z^yTop(mYx@Od8l=$IfEL;!>QTU;0|FrMSje4^FE6=(}_aiQoe8RTlBscN6|oPw|I<
zGUJjiG7lu2$&i>WHYoT61Me4%;X{NW<#G0z2VCyHY^M?}bae(HGeB<}{&1_Z>igRN
zxc93>jL4vxk>;IcSBG}j9+ZSwySsKaqfB6}NK-!@pRDDsW8GciYRYAw?*DXrX4E(l
zvC8w`!*9$etevi=C_I^Ibu~+~X8P=~-UYpA+ef~(N*qC`eU0#xFbPROx+R&ndk=aj
zH~v1Vhs%)>9#UPB>TxuI`$Yso;O!apJHcT%p#LK&;ap)0kNaAnv0xps)n=dv+(0M<
zGADf4J}a<0UCqt>B-oT;WqGytH$R(bu5!?pO+28Y0|PZ!`I0Y4KMg)|2OX)fg23MY
zl91gDS;wpb;4+v5m1ZgvoPDpwBC-d|KMb3-AaTwn%VXG`)zeNnZ)9fJ;@DxuCZZk(
z1;vsrRyTSJ_DdCkh@yl{w2w=(Ly|u~))Y(91y!mz`v^%*rqn%M^XxGfYSP{QF6Tja
zD%HRPZ(_senESn69;Clv
z)gR=Fj>|U_xI^~YNcs3YwQY4X2iYg?U%lBafe+}O+n?zC-j3B`R^Ute;^U4G_qEtH
z7MG!~;uZFdd-U601<^d|AKx<9UC~TPbufyXYV5N}2)Vzn<`qp+>I+=b>#qwDmh6Jo
z0#ExQ!KjBeAl=Gb>kLeOt&XjRJ{+TM-^wqSjD72QNKb>3G^H3nLd1AUSRfjs*7A@D
zk@Nq{Dri>MZOuib?En&=L0(3U&T4w?KBd~IOwLnY>X(x
z7!2izC%-)os|MVO0ZJ&evnS24uX)-Io!I=?EQw}C{2`hJE)DuyvzDj$^^aHf%#e~M
zb#}y|7w_Gqjzy^!@u|4S3ymv-dFZzP435w={K7;#_}AE3kV3!3?#7xGc=ghHb-rxA
zqnfm*<=x~;4fB{a5kTpldpT3
zr?!>%*u6YOWTG()fj5pY;|0z(EtQ*=>hV@8bm8pVW^#V2c_=;?EqOUaaK6Z<$8?i6p!#
z@)y=BNZC-*tM}wlos+~yzI#qzO>&e#re9KQT-C~gkJ%8>*=F%_N#1%j0;9XhWMpmF
z8M^bg(EHR{TYUyE=Xu%2eCIatA#hef^G#E+?>@C)^GO=F?I&E&Xy?|c@0A=rRCD4;
z-Jx#|d{_N_Wz)W6#}b!+Yg7
zAdP;loxwuZa7CHbLP_vQSBQoroiwipT;VG+dWCjIb{dTRvIS!_2MPO59uhy^c-I2K
z7_&ggERaLndE(}uJ!VVK=CvaE*UEoyWu@*;gU45b+11KZnk{`3FT-ZT*mo1Yzlk5F
z1C@*)T&1o~->IvUuH}#5qOn4e)$KxHF5O8P=l;BBYW%cy)3i^urOlmKH_`IQo=4&*
zt(!ClYbEd>1&?-CO8)XIZvzd62gVF^G~c-E+@4>40D7lM=w1`FmAuE1o&u^5If&Dp
z6aL0gnxC}0u?jTvqAeu-U@Y~5-DX_?=II^4OM~
zUqJUS35Ct%8F+@YYa_l}Z}Tn33i&d#)lFm}mb_wHZKASL;_1|`8vJi5b3-CzTDg;~
zeDF&*)zY|o;R3BMu4-b%vF}ctuKVWulT9anI_7%X&f@ofbLzXgA8LjlNrZHK%nH3Y
zb(T8s61F-k)6IMGA6&jGPk-%~@PKZ_%+2-}bwDh-v1?{Pcl?se@nKhDCH13TDt-bI
zW8TyJFlTob`sFL1AqrkE=BgjS?_K3(^;F)oJ6%D}2P8>$~UO!Vme8)=>>qQ&;U>EW+opzs-4C
zw+Z%a%tlR|{pEGSGlMlr+U+UAGZnyK+%DWPAK#|;Jd1Y=F85uGJMM9O!MVPTVV+;V
zz|OrW#nbK;awYZKo2~oIF3^qVMuu?0Y5>23lj3I23U`Xf@lVbhis-O0o_06)VL=jl
z?t80e`8T}&Pj|uZeg+4hRAyW~7dUkm&iTxY!A4guhY=2M*8(jFHIReqHS${$TVtK=
zIFb8G?lH2pn>uKVfEjbfOgq<`C*VcQQ=h-u?{iaP>i;l{K>4Dzs4VZt-
zZzJ9xF|dp1jd6B8;zXV?2WH)@afyt|Z#jO^tZ1UhR*-qPxq|Yi
z?V7q~8p;;T&(GJ@i0Zixd!ACdGI@
zONzyav}#<^EUgUrH%4k;s|K1$0rH;ccKmutKpNKhY;(3%tp}|}gO*V}23}O#xh9o%
zp2=f*qxOxGPzn0oZ%E5v6LuQR0@5(l-v
zo-EBltWUH_9f=U^j#xc(@x;mK$`}4WxtDWKkZk`J_kuPNw|kp=5y896(k@;Qe}d*Z
z^_D01Bu|nCZQYb(>Q^0)5qE3Y3JTC@{tE9?@Twm1Bv$8>#kP8pv(=ed#9{eLQ=fdZ
zbDcLELeQ2k)u#@uMAzXVJAi1%7sOE~tCmr?F0`bP133G-UTL36mI3A6<0zsI_jv
zfBHUoQq!D?w*!L|(WI`hnW+?^We7(Wje%L;6%cJbdk|D45S23Er{OH}qaBt}XtzXr
zS?>>STQAaiG27a?TaU7-)#qW`GT3|j&bVD-g=P9DaiUO0+WMdYSDeiLrJ{a*tV6#$}iBUm+<&rIK@^Q=}>H7U$447>gT+@_1&Xhd27@g0s%ItjcN`K
z<^QKKFT$9|+j~a+>)(v}e?Q*GT9olFooI*lRKR$T{r%Y9Ihvw1?2fTL>09ijk)_dA
zN4Ml*r{O{@(RX6CF(2ddwvV0k1zG}MjD&r?3%ot(Qdj=R9xG_9W6}s7^0t+&JW;<&
z=fm@MLRNf^?>^b;Vk3=g=q*}Tto
ztF!JS8K)c6?#daGG^Ltq?RpAaJ7(?0SUQcARkg)S?rP8_>fOwIdr{=C8gK%NscC-B#ji4$hABer}H|y+73DwhCCoW
z6wqY_(R^^O?T9r-Oa~W?R`tPooz98%M1hdb*5|;c7}8nYst0ecW@{!sZjYO&oZ5Bg
zhNMIo3PD4nxP>exDiYmpl8Yp4PRz+}jxYz9?#bW-II{xhw`ZqX>gbW_QO~>AQXg!6
zC*Dr)rzCDL(VM||^VMk)zj>4PK=oba7i3^sSkuSv>p^|(uE*Oukw8spV2>*nfJpvc-|KOUhj(@VcVBZUrf2TPxM6#jM_mSCqDO-&M8K
zS4O0&HE3LuAFKW{uii9lm#Mp6t5dig#l~2XO{!R$6_ZjJpqUYOM6GK{L8*Opb7D1>
z^J>a2^J_y?DUlWE>6Tc6IwCcfi*8m{sFTi7pu0TmW9;R
znr7lFNkKkljFq5Y8Rw|-#-yxn4y~9}VJxQiW~QvzUt6Z8O|3A-YVS<*Ppa5Z5vtU4
zwQv3SeihMv`WpG1$E1|za@Hb0p@YZ{FB{|7F#c#+%>Kc}8&c+VZP<5uoM@KUdfBOc
zRL{JNF)16y$5hNrkzGEu<>NL~ApbZ#xs|GZeM3c6S$5+tJ7RjZ!VSPbwPJlrzkREy
z7HL?uvRu_|U9AOfJLZdhXlBg84JnBZcnKU|H6Aw2Om=J8stVDJ_M#=L_K{!zzjJq?
z-NZ9#t7FnI8_aU8MA3hKEw%TXU|5EE8?@|iRJJW4h<&}X?*Y!Nf1^D-J0Qo1khCm=
z?roPTraUfnxSeLg`bS)UYY+F&j_Mj!K-3k{Y#Ua|PFejIFWeYo-!Q(x%PK0$+_|V>
zuJ*MJ<7zBIm6qFiSnx^Q5vx46gb!BU6Px98ReZ893^K_olU{27On$MQ*GpMrNJa^i
zMK-`ZpS8rwomDKkb?Yc`f=d!t`Gcg+1LMXN&Yu-l>22RS3ew$GRX`P-5TvaOOnqjL
z!9jbO$H;OU&Mxh2rgcoAya;q|r8!~@
zYG)IC)AsM08u|$Br0}V%pj@IzzEOmYA|qNtH+5Vp(YWzF<5uYf_(ZppED__@GJz?n
zJEYml_5JQ^UiWpiG&?YL@B6!~Dit+y1I$!wqp^J!=tnoNOqEG4UNFFX8;?8gWPp95
zC!hM^)r4*D)v&DO;4G#;bPXp*cOH5>@9vqI(XL8Oi?B7AMO?Uz?K>MXWZ;1}$4qdw
zLGN;*iTT$w-JF^lXZ640yP-4b>m4j8vlNa8?swGtMB$-Tpv+-JtuYk;
zA`3Gm9O&Q&S2x(roMnE?+3PWBa*f2(+J$c(g|xn9>{$gzq2+A7x_S}C4z=ts>m3Hx
zufpb&$d0s=&b5701fLfBrPQhDq+V}Q=$kmXeic1WLfqb1XR`Frmt}|&X$`ToW;v@{
zvt&aZ+Tt&2zA0iApp_sZJEDPp54C1n-3v+gWd393lTJ%x7EZctZEW?@km@SDTbs3O
z-5v#-$KOZlqV;6Jf)ka`e)mcpp@?ihbm+jb>bia3l+Qjr_nVhbjjVj|SgF&KU(1pn
zEM}`4xQUplIQN!=i-kg3dhnQiV#Q0(=7<(@FaoxBPKKoc_zPvV+-)v3Nyq?0DjjJ4NZ!z|G!9LMnmL|;<7e1&_w*UHa@fTfd0v9#l3vxw
zp&h;D9})zY6swV0M<49A8ky^e3Nx$NCYH24Y4H=+P1HW}^PgtVJTY_JGrOJ{N^~b>
zY5W5_ZrH_+BE3F}d2;43xmPcs5^RLUAvZ;~9_vkMu&UGaUn@dV(9ut*JKy!xX1#b$
zD~IgprI$uX@{2<`J#zTNF8+dh(I0v7x+@3B3qNe^Pxci!MTwuUki$NMrWjZZ(-CcO
z()(FX^A}kkZJ=I4BtY;2=V4m~Ol2`v5H)hJH;VXsS)!{>@W*(67AJT1{b6kqdRD(8
zfpx5yeT>^|w~n-Va;nf5sIz}#U-%m_+1ZPav-htKOug~`$nmJTR;hXaj!>ccTGy50
zZ1`McMiDO?0yNB!T0_5izg#Ta?6_Qp7`t0s-#M6^NA&^H8>{7lMX~qgy_{2;YMLMs6z$(-ghua*JHD(8WCM
z8H&E#(>jVfSa7t!RqH_RYpeogQf}aul~K8ReY`pvp=eptMo3M#DV~*flRV*=l1^>f
zZhy+-wAQBR&pJ5QS=4)_T5l?=l_L-MEnFiPffii!IuUaN`MTTH$m!2YTmujY8@VmW
zccmy6I$RKrZNY&ns&?`)2m_NS~z8scgov
z%oUr?%dhQa_Ee&kwJGs-qLu&s>?Jx9C;2z}uG9CpNhxLicY6KuKhx23d;VKG3I`p%
z*iA>_prcC(kpF>>q;5LWbVTK+7J3z0iRrj0YV?s&Z1H+e-Zmx+A-w$Z!-GB2RwiHg
zHI|#=G7My%mB4-qzsBV8$8?m7s3(!Ar*B7pVaE9`vr0YEj?mvwkEWY?`d_?GRHG-V
z$&tAoy!#ETa=A?x^>4z~f~cpmIyN{5+D6LlrljlAh4R25;pMSsK@2E-W
zrY26MCOOg@WuKhc_Z3hR`hR%>TfAb%vAcT<tbT>hTVGcezu^(P|+NvUfR=F8?lT|<$m$jiRrb4eV
zv+Vcu-${@eS~+^MPfG4hbml{zDsLD@E1oS-M~g?f^23rcS`EKyxheWV!WTpLbloX-a49Q(`fM2S
z<}OFcbKr6q$qtOg_}h%X_wZK=$q3E|wL4V)(tvXea3E(AuWAOmuz4Kmo4}%19
zL6Lg)ix780yVT0=GxwYVIjdnkY9BNq)fH65#PJ>n_%5f@a9y+EQ7+XEen1msn=u4j
zL>0rC`bxD{<|OTC`vaGfTYvr;r{jAAEH?A^F+GI31SZeg&daYyaciwbhY&ptEA9~H
z84cXnYRJCU)|*a`pX?ozbGfWY(F&1I=9snjy=QJO%^htINfsaSuPwRRH+81z^uD6~
zeN)%^8WtHN&Vw6sBstSl{|IkNmT_IQW|ws?+AF!VRb9q`tv7}A#xA9osQ1x>dTsUS
zm?^gDT3(*h%Klv_-`K`x;y%9T{^~YOwl%Hz%301rRsx=7txVo{iXZMiIi7HSjH{bj
z67XE*4b_b7Xh*s!<~0FiDB-#VML*_{8IMrngtaS_c}*N^rA4TG$NqPh%g_Uqdd@w+i}_
zTC6UrrOkb!2wsUe-?+-2(=xmzx>TB;GX#?P)pTYiiA)&DVp_Tm6V?TB%3ar09{IT&
z#sRxgv#Oimy?@2u1!4Le7M8Cf2&(7v_(MH2tNScI5cIv0=EwA-wi$N#p3ed1Lrlf!
z>XDVUX=d1_pzc@VEW0d^T~_HWW1VYJTR0GOQ}yY&u*(2X@Vd9xit$G)gxV68B4?NN<*LBsMkI@-f3xv)M1a7W(|3GcSp6(aZYb%?qDF==B1rCyahVxbx30xSHc$Lr@=muJ!=%jQN@STz2iU)8=FgqM=4zDR^w|mj$P*yohi_
z@i;C@8>+pAO3mqNueJ|=REzqpU%UV0{9GDdw%^g^Pu`P
z<3`NU?tJHCy3>QM{j_yv_b*@T%%fhzsY;BTX=bfU
zD*n|N)XG!sC}JIPV8fVuk;1E3mb$y=_2D2>=8StFrHg$gVEV&1N6XylH@aL7-{%J8
zG~UxbuKWI^av$Gw@9-%1iR~t}77j_dAJ%T_=?$_u{Oq2QW|hvQs%87VzWw`Mj^u}c
z*Uh{o+qStJ=}*hrR`#ZwSSp3lCH2>7#WCte!6>lCq-&LNzVhZ+;sK&
z{1bXHOM~Z6sL$sls`p$^`eTq3Api4^xy74!-z=*4Tu=I=oMn^wF>~PDRC%P8`pfuH
z$tQHhNbV%OC}wicAt_H|e}iJhYxV~iH}7YYVWDF8nuxW+bh*x*fjo|q{=o;q*T4^?
zk*O(;ezd~LoXE=s@bo}?gaj!8vdf@ss}nLNyVQ5Te?u!pxxzDBiFN47@%m;9i>}bO
z@98>49Ile?Gp-%4Z*S^CdUF(8e=FS@ck+o->Cug}g3NpSe9?$34h&qz$Bc*cNbu*^-&Cb?cUQ?dkf`ul4Sf~-zG2m219lf7
zJ~!&*;T6XZ9G^MPl?$!_9DvKM<-RV!>H(W2SiLY;Yg;(Q0vp>}0ejJGCIOhNK)?YuuWL6H*bY
zFpKaM$BN`&D8J+F7>tR!WAtzwUOYK9o-APg*8R#b%{UeTjis#EIYpbiHLqG7H7
zN}X?*`&}pZui8)f4So_4u$V2xGQI(Y3iUuHlNw#&gBNB+^+xem@yR<{=
zf7_=Z@$RsAfGn%Gm+%i3e(n~nMxdWjKb6`CcXL&9{(&{dH0ei3QU7#0Trs*X7>O8#>$=qzSR&`;o73Aj;+0W75(s8bZ9uG4XBz`iG6qr1W-^-rC+JI^_r{ifU)j`T3^nKn2vvL2X)F
zdQO*^;nL!6MSY_DW81JyoE4=Oiux)&BwB&YFs#R_HSXy(Ppej~Cnk-XJjK52slm|o
zp6dr0iBJfwah530htw0Xm3wO7U>ltt)Bt6%%lqL+)djo7Wz9NyRy&aCWQ}7yo{(3XgQDP*MhD3P{gu>ce}i{8P~1Moj|Lg&mz=IkXa-!
z12h)!PMAej+eXA_a68fW&PQf*(>3`xkn>U7MIkop#jekOyqk~~U|$FPa$cX;+~tDTGDb}g1eMYeDby-wxAO3b%xUFuF5C!v+FL77RTA2_CAt`vpnH0}zHUFAGmIv2Uf_j6Hrn3*Lhzj!cYy82~
zDzDnh8AA=|ZLA){>=vQg%gcT1n9(lrJ0yQ}`_1gsIc4C$wj}07H*8E@=-q-S%!CC+
z(tG(GH&6b7)7StJ^K&)4O7Uz6%{aaTRQUq#?x)#^J9r`^h32MF=wS1_(RgnN!d=TWTb$t?caUYP%Mmo$8nCuL)^(b}&^hbtthi{694Rtk%}iU#)GzfIQT;gpW9+
z)EQbhq1wksf8SkmSMyEmcI!)X?yE(_HE2Vq&Re*liq=8EZ-whbJh7hIPqN=p`=zk_
zx?OwR-BEknHP*VDP%-u37D!v@4>Vs=>*mv`b<5CG-G1Mbs84}ET>L?;kC78mA3NKz
zx2Gr0>{aBj;2Pn_w0yql9?((wSou2SpxB{}Z+VvyXKlt`&rWCwiLi!L*Jp+OfSqqc
z^G&XMhqMI2L!7f!kA_t?Y3ho8l%s&bD=-3K{?y7xP5(8{w2pHQCx
znTpXxbYehmz0{m-OV4207I`6JXA}^RWYpK+dMag+P9^WSEj_|iP`9D6YL^PD72BTM=;7ru|DFWE}q
zr>5ENHWp(JB?Pm0w=wo2&LKU%i7Gx+^nw#7bHCesdiytrP93YOJ28CU$mOzK#2yY_
zy0`5qEh{bZexVJ1DEE4cdQL_OrFxgA_jjl(1Q81KpMV@zD#$2e@T-WY$M-Wd0o9=(<)_AkwQ_#h#-m%7JP
zQ?Ko^h}QVrzXS~nnsRK)5#nuuvD&!H;&MczHR_WwNMG`OVh(pvpI5|XPqg`>nSAsY
z{%5NvFFD1idyqq%9etb~k#_Wmw4+DNNIhak_Cd_ZKDNY^KKG#|F@45VyMj4>ffr><
zMK^=*D7);m++WmD`e!%q{N~ti<$+>vNmbV__(vr>+yJKaYwHha4e3!}?v8+r2#Kh(7pYcyxok*Mhx?Ip*C)ofclIlXnkT
zP`B?+4d^%JyOzsKMO|s$&??(BjON;;JfeW@xf63kgI;7)ASHx+5BQN{qdJm3PsSj<
ztV$Wn<-jd^L>Wu#ulzoBELT0qwSoR93dwCv{ZN{Tnk#}UIE8y25rvkc#lI=9d=zNn
zt>2|SSM~sCq7?mbXWp*8z`(kd@;IIO|7*a-6G~6qnQzG#BB-wyJcaK}9rU@r*IRsa
zgBY^Oo0zlHtM<=lz$u*aU2gT}%I*6Ol|O!Z__1AiIAixo%o&~gK$Wd7n3b*@zD~4;
z>Rt?rt09>+`hPdPz%L4E8YWI8xwR~%kxjPP5wtX2p~qEujF4KiX+J+T`{{W5x>Ujs
zbZNijO}gpm16oXssDj6Kx$(OuxdEH|YCgYQPPA
zNO?9SW1%@ugXY7`BggSkad8s1;dzfnm^v;epC5F}j
zE1f_LkdWvlUof--SvWz2%WpR`PKlZYzEt3>{KyAOA`R(ebv+SQ^>HVs95WgalL+!}4m6IpFN;7a
znV3ty#F08+E}b%htNZM|l#D%j+15;hOWVLWNF=c)G?*_3r3PEvX7svU1Om;9%Yz$*
z%4nRgfTKI3fyHT_Ss~6LuTse8P*&h80jU%tJuo81IT0AzMer=k!?_^b@mmY#pj06E
zs=oO@21bNlpwg&LVU6M(wXA!Ocb5e$<(av0cIPxgu|5V%_rLrQXV3KZr@KxWt-Y{_4)}ki;
zLMx+FP(($(Rk6sj=2`urjW-8dDbs&i##0e!#dCsk%t{o?2AY}L73QMJq9
z!27VofHVM{Jx}Zn3f0wIp2dGxU5omL`o(CRXAE-`KJR=LaH=Tm9W8<8g+v#u`cTo1JyEKsuMG8
zGg7g_pq6WzfF1{Q7_9I0m;v?Sqb%~;YOUaNaGWpGKxa^#M3*;Xh6AY;(w7XK{5IZ6
zho5Xtd)F0s$9JsAYZj(!xIk>N3~AAI@|(q(qR9+63Je2ciJ&So06IGfp1kaH8#DsjmIdeV+)G|4*m3p9sbI3y2h2cKAlxZrY5
zb8pz(X@luk=qQ{Ao3-8fb4hk3ht-#7&E1^9`AhcPOnW2MjN*Psq
zl?=VN`rBNIvHV!@rE;i!WPAMV)Spc%0tnWZv(rh=gUIo(b6CqE%K`$h^BQ}}YfEor
zHp@bApO8-WlU?W=-&!u%B8U41$_5E%u^f8iMc+Wxvz4=UZU#0R*HK2&@1vW6%f`+i
zC5OYgyRlgVTp+T#U2%;)47}k+7HqLuMsZ0FI)}l7ne)ZmQR>US{+&_uj6DCggw?Zy
z-tF!!`I4fc>#qB`@U^a7jI`1Zm~8{wf9jWJONR|H;zBPlIMaRboAZ&STvi*S)=JSZ8eHRIQ>)bP{ori
z_`P$tKPdQy-D=ccV_$nI@55I0n_D1biLlyGLnF>i0%pb*x*~@&9;JN+&d|CASU8((
zM)5olRIV{@cXu8C;13bMqdMQNT~DpSU%c&)5l>S+sE$-ZgGYU@@ot=2zxnNZ)KbXL
z*Zcd3-;f;9Ncp{@)xWy=dl74{cL!U^_iEGL9?df8
z;da{B`-aa~ScuvUY!4IJi-kO+u0;62^
z7Oljk%jK|EE$z1QieUb62h9Q6(@29*W&?#qwDQ@OG)T-8okH&I9kB=FgLXl2PMm^b
z04ZQi*LS6PTw}InfCWh07@54orS_h3sf6B4&??b<=$!WO}HWRTMD}9
z{WIQdAd_+CDle^Qw2Gxfxau0&xey-xEEM3WGj&rYPvphr(?y>a{q0PvO8}&F&XaJG3_Y{?tZ$6Y
zTYVgn=4u9guH?>>URS@W`bi>QNRCUYf|k3rtD#_5PD6fvV6*6IG%HxVn=G6KG8%k+
zP?b>!N(8P%wl%xbD|OW$a?h-|!~e48Y_%)>Ja!W~yO{?Eb=~QO_0yl*uTyC%vM-e;
z&M}we!ApZ=CE8<#Y0!QR+4`5EgwYe5xx+R+8=kupOtu+0;KIz>WQplWKLZ*`$TY|=
z@8Of-ah(~JB(<6r6ySHz;wX7;6ECkT;XiW7S8HM2<=ibjL~FYU|I3XRVP|m4E>RgB
z1r^>g_A}l+_M_fxbLR9bWs4&*HWy$aH=Q^D^9%FK2OT21A$my;W;$;$3yMGS_z|L^
z>{P?k$kpqI=QE=_qN%nU-w}pDHh<(v(;90LeEbtQ`Ns}mItI$e9*LQtF}m<(
zbi{Kg$62g-UN;*19iCMf8`w5J9%GXGwDMS&%FF&8V*<*lx!X>zdo99Q(%XZJp`j$|R}ARP?=kUJ`54JlgA~Nb|0B@}FwpvkEKp1W)xI{_}P6el2g?
zK7orc?{Tj#@HnItd14F0`ge-ZAwGBOw@EAvXN1XTDHn%al*j*M%S~5qJ7S3-Uv)Lg
z@jqH~<7Ap>E-dgr-EyN7*b+YFZ3DbuRH@zsMl%&SR^y0&(U=0UAHqs68~Y1OSYvf*
zt%DRl+<(*&*LB?q9+XDUE@8w9wv`_+(Mk(EsQ=KVM(5L$OoOd9hb_(zt`;nNxQP74
z`Q7u{QS#e)y|#qOKi6V^$ea%Ps0hTKIbpZ{Y(hkA@Bpg47ClpW8Jh7AV^)(TCT4bX
z2@md8ncHGA_KWhd8`QhT(U>=6yG5(VN7DVYTaZu2D|My$6O_oVs!s-4nv?yx>X#9S
zofkM^5uVKE)YkY0(%2@6_0Z_Sqbf8rKje==3Z=?_)`qzM1g_5Myw_IZWE&6Ls=S>2
zAhppW)tWM+yg@AJN`c&dop~JFO+ZMHT1>;;GNORd%oy#?j9i>Ae4WqfXCmr+IIMd|
zeRe-I7RzC=fp2yiL@_fTJNeh#1l#t>-DycEDYF32gE|cIg=SbRZr9lA^O<~I5@GAi
zi~k1?41Lh`Q=&+1$jpDZjNUYE{*cKX5=Y+@MViBuf}XwM5QObvoUH`kR`GzOHj`Im
zK?@7ywnnxZ$UjMF5uS4{EoN(dJ?~FxziulDVZv6Y^3IsbkhKm|$OE6+}Yp|9LZYm5dxu8?CwLOJtL?`Hce*ddo3
zdcGDXHf<|!tNM@=tXnyGfmbVF1Z3VZ&>pH^SQ{R4*9(e2%;p?_Z*zydc)1{K3*!W8
z33|>WHkv%G(>b}_%YuPmkG?dL=R@5l34+(mD`QqYT&NT1v6$i_Np_4e<^c74PHi?xM
zCe@A-;5Qe`-5EvYEGz);@NyGYuhs&&
zC|RJd%5ysS?lSx+<9K4uvQ(~0t<}s)S(SM{+S4P7AGmQEeu075%N@7(b=uXJY|Jz)
zEWmj*VW*-gRd2T+vvb(IGGT_q*=9g5#nowTPl(_S5;$SnP>#GslY;(c
zvOQttlK#jz)uvkNJ_3*H{Pa-C70ah_3g8Qq28w{5ylk$8G+@bqxWlimpOT&?Ei
zWdh695|TvGzJB9(6nn1vc-xE;wriaySDWI=eZxf0_7pk`MWHh?sjZ54dJr4;^|MS~
z^agL2#;kKDYadE-_&E8=4BoTsXA`yPO-JN@|FxUf!mJ}xA5^4INx26&e@*o-o@M(}
zD92-EZ#iJA(Qp&GLGoU&b{nHw;lUMVJ$k#v1M677@vXa&@8Zp$)Lh7od`EZVY*u}A
z?*j{Z;#^FrQ+gS;-NI8tnJ`UcHhAh!2->(}cy&m02fQ9O-hA9jYo=iaI0J3dzK#Nt
zT6wPJ@Vm@Oe{AXIDjUnA1ASABOv|}~I=b?I0)0*GiPl7sELyMjOTliaTX2?aif!p7
zEa~bgo;Z~Ztfck8vua13k9rY}n3I<#i$WcExvwmot-hKi{V|v6C-h?@?M{fDLn1Zf
zlm1w#q$Eil7$ePic~+w)Y0-8*+Nae5uZNG`w|3m_GNFDuOS--l7;{NdhAGjVvy;&xG(oLtI%r8IgQh6#ZP`&JsWiGcH`&>cG
zt6=d@S5b{DS7ZTBn&#josc}E+vk@DR;%Z8A$=&b
zL5hml=6ygV*BW^mVIkhK6(099{?H`5r68i`s>2=&aH||`ynM~u%LdsKNe=90@Q-_%
zRsRroy~!AP9_f|9s`*W7)OoaH$-bdSg>={s(8{x@U8~wgD420AW#z(?T27dL9v+qN
zG1_HRKjNfOrxc`JXViNp-MIX+2Xp1;>v<2*A2yaHT?hU34Pv_-qIq$Yf6ksZza-ww
z_j2aW^rK~+>Hb&RuThMs)wk@%vtd!#RipYb)2WC2n1|=_<+N@ILxvRQr*RiRA5!r(w!d8r_LX%k-MmW%_6{qZK(xf*i=|V>^6aLl$4^UL)D+C01l{dXxLgZ`Z?*
zqBLi=h
ze47!r-8O3>mv7sm{Mv?J#;{gMYom0+0j*AN07htSlW9^KA*&_@X;W7CLQ|l>WBNZ{
zU`O`b&Bk0Wvps1BSBzHK6PWW!$bR4_WPh=9yQ8Six0sF3}Y1fj@%Fz6|nRsZXAbN}ztTO%ZuvN+aire2?k7
z@V#Zdb)8e>t3RPOwkeT{OzR_Qdv8x;ElRbSTe-O2o@O8SjtHOW<^&B%z?|vm33Dw;
z*57RnvY8vX>__zlja{xqXTyv9wntkzVM-O3_lhfsXdMtG2k
zL2tp6Q{plwxV{_CoX;8tJ11lm)4uMyexS>9;X3DhG6PU#cFy%TptQW!kIOXEDR;Pd
zut0CG?IPc;&d7MtwL6j>EZ8jS#|~mg3kHUJnwz;E?Ghy6gE8;2o>@t=&-k8CXY)lN
zS_{)CG@8|h`*_eR7qH}koY3JUazMzqb>-~|W`n;m$EZXa~V$L}-#tS7@
zU0A@FPAgbet-7WTr&fph)U`bQO8=Hsve
zL^+5@{iyslc1-*>Zjq+o{b4bW!kQY-Nm^zArRz0YAF?H+>a@r5jzb2eo7_fsz}D8y
zPVJ*|?hcYT)80pNEJGUJ3BG$G$$xEk=P}{wJPl!1bf&9X7tI$bFU&af^nquqXIE2v`f;9#6lstTbAv%YEUdkuSaj)rE1
zam_WR%8amAVwS=8Vwma`ESM$Gjghr8Xzos{&#)jX9>erZ^%?Gd{teAgoXm#UswJFC
z$QyZjfia8rB{{5-MO)<{=(Vh}z7Z=a%Bw$8f4OYMw`UXyqgu8!*k+L+NgvGK+b_FyqmVf?mQWeMQdMi)91Tt#ZkpeO|%(JIY?-
zQ_FTlI1R}AfdrkrS}L{va>2}RuXM{_QD;pnpWm$^s?3%{S`|xQlF>m1`^kKu_|M-P
zV`}|X<#)F&K^(yElvAZsdh=^Vu09<00o@+8&f;1n#m!&ZwK$Nu{Z?iO}~E
zJu?sZiDDKok5z0%@VD(QjU66`hwLd9?C!b`&gg@4_+z+(AExfeX|i+t*|aNdV(xYz
zf~&rUOWJlh$kJw`pZGNu8}oTH%7nga$;cdiWB#B)&D{JU1IJ>xm@a|
zRK>nY_d#b&P)MyKRn)}6%E%wJ_GYLKQK4Iww5sPXI(rc(QktXoz|cPvcc_KkX5f>1
zYgA6M`K6fgi8+OSrFU0IFAg{$=VJZGI@>GkY!mUi{eck0_g2l|=XDxL&4Nb8wt-Xs75>7v|&8K>^jjmkk9%^Cmzg4d5cDYpQLT|scg;+2COO*@UI{C+I8hMSRMJzzr_-(-ml1{?^QvD5RyZL@;-F8Sj
z;M1Me?^bQ*`k|-dd8IC@%zs>(S|94cd>bqg5D8MHOgzCH7t#u`*2sK^#vfU9Q?M*V
z&(Gm)=IK1ypV+KsezSNcKV_e2M(n>2CmeX7HfDlRGeodWe}UgHeslMnYWgu%K_W7+fOqn{3aPq3oK7P(hF^T)LRJS|O_f%;B2^HpB_wy3}9EBCIMFd?`q
z@X5QEjENeYuWy$(zvVfQ(pCo@G3qM$X-7y7ju?x|erL2v
zyJ9BnvTx4qp&Cm$z{79NVWPb5S>{r}F$r`Tl@Bi;m
zy|8z|vxK}A<+nt3x7ZunGe~M+X+VID)D%OD*IUu3>sG8Jivize`zzgJH{xwN*j!Q=;|xN
zb9l@-5Ra3t)5
zvH!Kup7B)s_O%{VN#(RYbakM3?Du!-jMZGF_MUv5K{
zjNGk7&wlgU64X46PV6Sd&z%NpTm|HH;9FEn!A^Ml@7`8gs25E-Pwh6I_J_D5R9??F
zRUR$Fu~T#wLSt2HX3#&Fj$Ykmj&4-T9-0eU`HH^U!^Qk}tuyD~`zI;a?K;Gzs1JD(h=@b4Xd
z%9(&xJk`&{mVQ3Sh3FN);l)YZXt)*xd^yCR4Ra4@ptW^Z8u2c~r$tz3w|T}DiIp%1
zTDKf{z1;wk#`z$M`?2?Jdbejarn2YjHom3W=#qpn?qp9*OJ2;rRns#osiu4L1x2vs~`OzPa
zs_k&)<-o2~?FaP1b{nLaly93frqJl#%5bV=|Mdy=5a0;yfvgX61~=I1$^PXSYNr<=
z=R__brv(P!>qa0f;bO?FDbHzD3
zEYr1$o%bgnx8#HOzRxP3j~BYvpg%gR63p30Z9XwL-zhJvXOWgoBD@9J>E+N(0gKUA
zPuvY5OX1|VNgYEzjl-Ds=us$UPcF;10BxZ$S7T64_RS-msgBhABZ5y89OjgR;f?$H
zweaE9advQKx_Kw_tkIW+`tw04&gdUU;w+%dnq$hfWl0s;n9%8N498b+Jgg}8tK&(_Tij{5c
zD%<+HYZcohBY3Fo<6*V>RCheAZe8`M-EOz_kr*avj8tjF6c6Mm-5*d;~T`4ZR(}Kfe6jwxy9snPAl=mA^NU=!?2(IJ;Q&J
z?|ppo-Pj`VXm2Ab;3jyq_hHjCYnaa}8U!($G$1cG;&fO|xmq~*;J3gZq79me2D9Iv
ze@|I4M99~jmU!mN|;$=_)jRjpu_f>+rV@y0GqaDCcn
zWe*+Yd~$D5)oL5o*i|$zZ1-_PoW!s(L{~$4oBc99(Yem3*~dz8H)oF-~?K-zB->vje8Wb;wWJKy9y9UO0y2y(S1}01*bQ&^?=z5S_OY|
zNN?v=uFupX_6BT1t?J+n$ggb4{FZpiry~32U8~k`Q?d}}poZUfLs+=R*t-Ot3NeEC
z^K~Z2VoW@XjCDg;WAqS?gUy-ra*|6QUj+NPPxV+BRRc0U3SaP=z@CH#+tfL*Qsb*r
zt*p}q9jmHwD_L>L0-R$(UANw3u~xI;TKzCY5+`0`>{{{XYVcjQDgD{e^Onbt&G7Ehy0c0&l;mqD+^i|#AU>=R2}YNR0`7IyM`g0vBwaO#{F2BGBRWAEmfc<
zDmT53X3kAZQd#AhJ8y7PM?>?OsvS5wRcKTFJ`cHwkkcxO1=q1;IlSVN;Qe7@ljb2#
zD@}Z%RZUS{=P<4kw$L$fw99k7FDwu6P;7@!YqcuxC}k9P+MFwCzQ!KsRbBPlDIyRx
z2h#KdwIh~;|J%VBW7VpYhZGOmDU}-VdgMP#_J!d7R}g2)WmI9F*AW%HZ&m8T+ssg>
z;UBl7Zq?bQ+7WpIi+5ZbGs)6(jF^2L92CV8R4{x7YT=>Pfa)8~#C>gDUS*qvI$JL}
zRVgk>UFcfI1(@->IYF&ba&I`^arx@E7iK}jtYs1kvzBqwrNUBZvuaLf;>1B8Sm7Rb
zP!;i+4~(c;Z=0%PV+6a_t`>i;$4(jJ?%>`a`JQseot0%Uz`jv^aZDsvjg(0qRsO%@PdnZ3UG+Hg@<9O1f&=Z
zbnP!!V1VXiyG^*L%JJcj4*Xz3b66J_9I|c@H#~gli{}Tg!r3BMuAczwz2@5~=cb=I
z;0!Q_E-Gs-9H1&adnvoZBe$7d(i0YFKB{e#8yJF!y^X+U=9wxn+Kd`T_{)Wzg2>>6
z_%2@sI?1=FkwrABCA`aPMai;4`qODaPgDPQ`S<$SPZ3|+w4!GDcK-$)Vgw~Kelv&8
z1Gk|AA=p*;>2`Qel&ZEJ<^E{G-CE#GDX=mN+3NetIwBfX_OSxz%ocD~lYW}`?6d>Z
zly4#*-K0U5q}hwfqjWlO8PLE@-+_F;Q}yD!+u@T;uoSUk&h>C$r2JRFEFKdlyW6!?p+TTbQ4{DmNI1`T2%0?J@DMzo=rzh;RNAcIbJXvc+0E-zSPi
z@T1Xkyk?M@;^8Dmp?w$bpo&30sAE|?gA)rHB!c!S=LWCxWI!TcRY~W45bpIA1t!h6
z1z805&lKd{hxG*P#gz|2u-^EUymI+sPjeKtuI$3x^eqn|1|UK-@Nu*T$wBE?fl_gk
zwg;*hmm7QSVEWnRwQ9P$UZ%KHcc}9GqE7n|>`o_UKnDlv_(&~t$YNBTC3ptcLU2WG
zf-7SWY7tb?m7oe&3qckAHnAfsM?z-=n_f?xLkT!%qMs=yE)ToFEZ<5a(^(`J^4b8d
zaBs;I2O=#G;s;?z((J{|l{`1Hv*28F)vK{;HkBQ#Wnvz6KSv2sshj*X~u=L|@a`O?#eTaENQ}Y
zJvgdJlhb0GS|3)BCAkt;lPo5#x}XsoK2?ibcs1cvf@x5>Tl2SjsM;JQnZ?=*D)5K(
z>j5P`Rm%pWrdpMQy%-7&+sW%gEusC`F6+Iq#)_sI9Gz&rAj|EFyiQnp$l~u=b#H;i
zTui?f6cfjed+%SkOW3-gNEt6>EMvHclkU)
zUOMMEbb7(Bb?K3IfR<&dQg!WV+ve+s>qfN4`#T4AC=hq@Cak=%Eo$Z0q5%2Lv6gJJ
z5s`43O}ZUWTgYn;ol?eh*wkIZ~S&M>Jg(?rt!O6!5`o9Q?TE<
z3HDtQy`5dFjPn%mxLqD6pePRd19_x$rIFHKXr#ExBW;J}#i)U=Xj8G|EQZcqb@32c
z4KfZZE1Ca)k=Afu)_r{)(})SoK8qY~+AVvUc|bq;In
zL)R?U_?Q}f;jAS3s8y@56USJ~X6U&P(bsGhLi!9vN1IFcne4g(N92VofXn1clIoO7
z)%{LPD4%j<`r(vSn8UGL!JxxRMYn`o&CozGCo652OpNVfe}?-8tA^D}$(jyYHHBcs
z^G5npSTAUIbjYT7tzE-mzr;nuc=0b&d9mTPnkciFJC85?bQnvSys}V^zZ^N!G2bu73zI_Nu|~28>td)RVlt0Ovv7QLMer
zpxMfmxNhAbd?mcKO~xurCYZVENViNr`JW&p>X-r*yAA?B%CRd4Nmi?*l{`qWPAf9h
zY}ck1;RF`o_v5*qW=xQIRQzoR0(1ZqNw&AH+8|+PyZo!_?+(u5s^(%hC3&@M7Y1O(K57Q$sLWRs
z3b1JB@>|4+2F~G`GNa1ciIKST0d|f6pbiXpcFmH_GTJ?@)7d!
z42{2^GJZt!DwQlB7=O#J$In5_>DGSC?aNBH_zi7$p*Lm5Zy0}tEAP*2BV2EK@+;Qz
zn(S+kao9c8&cx$HGH3_hqVKv)ZKgqIIj&*EkUXatiu-=QTGW`$bXVX^|vvHGmG~qIQ}d&vWl)WfFjghuG0-5x&j#^!VKcr3RPQ_1W%TeKLuhbVf
z<6Aosu~`0(Tso(kM%*U73bpRuMtyq*HKpGpdfPy)yk_KmancFR7<0R|*M-`^t@WYy
zK-TC%+u}4?1+Myf81G7e_Po3cL+z*&I@P!l(fW2!JBON1->p$^>*)(qG5UIKm@%O(
zsJ9LA0K`!!nb4G-)K*%}ivAB{Z^DV%)H{$^0xc`wqLKHr>8)P?Q|dgwF;jitE=B8!
zy;rwiZ4eOmuZAuJFltiw(!Rm~`nZd0NMGtDU1{|A)nr$I?A3G`RbxZeC*q*_*^8TI
z+zjePo4&j;8n{R2EuX&7DU@DIQbuW8YQporj|GsQ6t;0&7Y
z>4)FL1O3fc7gqbyB$u;Z&gx7$T*1fkg5o9a
zf2HkqVAhqQMuD}wLY4VwCF5sQ*+3(xL+_^#M*i__^dUg14M0(VNHw|ZO+o48GeMbn3!P$;AhNF0#9n5
z5vX~y#b*8;@j13nz;&A#udP%am^Je~7Cvco)Kq?gE@nX|5U|-Q`(us8^|!;eAtw^uXJP_t
z;hQM?jcHErCQhK~Ez~R}ofR+@JV9XX%N0gu5)a;v$w8K)T10YEf2o>Q)oy|QkF*EY
zjzZ>?Ik1Dk*A&meRt4?#GDuv_YSuDAI)`=5{<>>jNrR=Vt&vfyjWPK5uv$&Niy>Qf
za%DHD2~(iPCz0-Oh~=3sdlR5y07Ivrq0P}b{6?ND4|?mT7`JAv+O0+IS;CN-R<#Tz
zH|bPcrygS2Tn}hbH>f${&2L2eMW0u_5tgsA+1
z`*fbNJSw?tvcbV2|0blhe0BUlI$^bMDo_x6A_xQFZOFrurH=K%Z-*5*{Hh>$$Bs4*
zWKqiv@VY~7Gk*eDeB!QG-JfT{%gFFp_UkWu)oS(0AWgV$m8gMLLjLmnSIH{DhpZCn
z2dolJch@$7B(m#yd|0arW(cjo}UC
zFqJv^x7L6fM8JX?2Ob-Cifyuef}m?lQ2I#Ttw7hNcY=Io(+pS#0DWGf``JgylJ1Vp
zVkq;30$U*{li}-JXca=IERB#>e?mFgefMS2N&XpfPd&wK3;dcoznll^9NiM6%uk-Q
zm8-!wWrhzM$UatRr#w#D5lPU=vu2m?`d0D;zqQ6yeZ6n!n~Hw~KUY}?VWwM?rth)|
zx+(@@9(~*w@9XVwMuApkhEuc#*#?o-2GYngyiwnB&*quKcpt$P);Ywc;M$)-WD2ee
z)W(PSdtPc+?_j)C2M7@ABrom}-l(#BG-{28^z$^ruW|veAM}&>;Ay6e&GBD^BX003
zw2m^~uU%0}7)GZV(P!m3?F+<9qMm@7Y(Z3^2HFaFm*+q4Dz7)e8qNG(nnvD)jB!f*JSPDPGbygRH^~2?1j4Z$wEa(dtwJTjkS9#L+7x<%~7lx
zS#p!lO*n;UP$#VE7IAid5Jnx(DJRR$5YL!ZuOVKQBqYhTJ3y8+g3tXH@>O0NeE?rr
z+!mCClHl0@`u9pLLFjg1#^ZH1-yldqRF=|SQ|y$iY%uB{
zT{JEvr6`<6yo{Uq!(BKVINuyyqTjgclduC4~1^3ADWY8ks6mdZZi#Tvv)5T3$WnSvUm45KwaN=uwN{IiW?~bb?JGc(E
zT4Ojgr-1E#Qc&xlzi+!`BH_O++q0WipQblS6aV=-mbs`b~`LEF>wP6
zxTBsTHiRJW@k6%wAHobp2~3<8=Y7Y;HOBbcz$NJNHgM%TIMji{^IIB&dwsw*^#^zw
zv|SytBS-KX+FPd;!51#7B@Smd#fxZL9s)NV37deP2Um%|Xdcv_t6n1gIp(Ko>52Ji
zT6#lc*r(-gKZi%o)~E4fzET!^bCDbG@QR-)XFSPiuWV&4i3Rc~CT`BQ`F3y>M|Xq6
zew;XL)Q^ES?l2#GcF$%WSXJ@?;RB8SaTooj*0_Bk_;$NlxiS~`gac)wVJuhkY
z;+nTQDCPijtGRqPG|QV?VuO7}WD^zm^?R~4p($dG0TL-j!s6|TS3Z|lXktg9a!uSD
zTH7QR`oaRj3)+X9j?m~LTrw=wYx@$!3_28A+11YMFS<)Qd#r#6S<)f=AqXT-yW*3f
z6BSS+!Cu+`8FC|JNNDnRf_4-i$6FF&)H4@Y%8G5UkBPZOvUTiaQSdzcn$BQ@<_xDm
zd_x=LOz7t;f_0@c&b)YnZ0HkC?OPQOd^Cg?T#(GJbi%)(&OptVcYuL4n{JEx$-0xo
z)q|%w!->7f!WY80QSTXmagl;J%b{@zt4!PAB`0Io+mM-P)hC{;4dPVI!CRltZ60_ip*lkx>3cd-8wO&vjh;a|XddvU0-rab!KNJ?aTgj08N2q<*lokD$TMw|;_&VU`r
zs`SsN09)kwrDXRy2Vco|Cz)q2t{HJn`R<`reDKXpr}hHpyGGfV`Gf+OHE(@Oklx*Y
z>|BOKK3+AOYLs3YJBL`#7Kg@gw<0u#x{ZOuogdK{XwC0lWG!=xW6Xif#NrpqasZ@14Z+@&n;zRyDDmbzS-uT8R~IE^t+
zAt!^GCE5TF#hMQ@p#fVv>b>C>wn&WDfzpSl;I4POXy7RCGnTT0$o#5gGu118otN*V
zTN(~_$Kbv9f)Lr3+kK6izWi}?aBd?`1Sv$#jMFlt5$<~0!(RKsTG0_p{^Y>LUy6Wp
zgoP)8gO`iz1u)Ivh@-4m)mUn-4)8Pl7
zt&pF+TH5uj!u7$G$}+L{qx6lA@2%dI&av|??I
z4rCUeRA~CVpR&n{RrBTNq~#g}sDBIgf6~nwBVlDS<1Yt7y3Lorq%43mFXRAJzW=Vw
zDQ1yoR&wPizKAs=KEW&!T3{R9OW50V^`A);wS%7I`{0!1{b-8nWX;33D(|-ci}X7*
zdL<8Km$W#cT=~{~7tNLY{K$(~I!--q+KV0$$N2BILfVO)^4CB5g*9I&8Vv7ZJYTRs
zJ+|?|mFROwS&8y%*~pa{sOephY^U)Vvtd)Jxx9T)2>y5PhAj{CsTr{=n{0W%D8DX$
zV4J!d`dl}k4x3dAVuIk2s|uWX^Sqm{V3I5boY{dh8~^3z6O>=j_oVimG(sV~%UoKk@H08=Tgk{~wku8tot@Rj3Sl2jY%^X3!
zJcdylSaTz^_86}lBao@9Y#VHPzUE4Bo=V@2zjp6ilKcL0?Z5ZUT1w=ex2$8$EppE@
z-a*gci^yt1EBMhRvgd^?d89jm^tMX2do6%oP+rme`Fcn+LoDXQ&|?t~xEdNQ*~)nl
zTFX*s!X($(qtI%}^4vDp&inEl!3s%qTS=nJe0f6PDow}~DOLiP^C
zES&k`6I=CeW;E_pFvd;IDw$_H^HL#wGg+dO0oi+1fy_~P^i394DF=C}q;2&v~8$y;Tr{^wt*#~MO
zZu2zs^LrW0{9@?_B1_P`U?
zY05*JJRFF-HpaJw!D<8^Yys-uD5E?56V*8+jg1m9`J(LGot-ZJ=nM<)zd+KbsL?@>
zsiXb34%3mB3A8(qB$=dK-p-dH)~T?i9MduD!*3O)0?kc7d2**SX3?0_ThJ3=)J`sb*)ushw1c$Y|ZO{
zpeXd=zBlkjy-MG@_b{8tt{A4V>@u5|7%3cZt#r{2sCy`uwGZ(N;M-2EM*+p;!>
zXt#_L^PkSPz>m@N`z*2HI;?bBhErtSKGlq^OaN38cCFbGvZO0^^q|yRa}zaz=C%YS
z-I`aZz`s8S&OV*;6r4%q}NbkQ#`;~24h4OPrhdUIp;QOKBq3p3wK|bzxB9IxV$-%e040s6A_aLgd
zQcALbk2v$2yInc}IbLXO;9asHz<1vn--|fk@MP>5YzY)UM7Hr1!iD1n*uB-2v81O6
zZwXtTZu2=A>uH0%RHbmQovoy$Y22u2Xu9)OR++PU{4AYn&=rKW|4iI*lAxSgIsV}S
zt%*?uKdj90duT<*K~B4}5xQZL)tX+Z+b&HYYg5h5BM)+I#9^9eFRppKEV$M+t4nwO
zKYHD7xdmvx?{yE3xx3fB3h(3_ly-ziBqtX7L*FE0o=5?>^mexRTa5#gJ@1NQI
zqYbtr(#aX^)hb*000uD!VP3iY6k|kHLR-0+@ygf9jPY&yJ(uyy*Vh=MlYT>s;DOIJ
z+VEz9f4riNqZ1uEMdduyKk&^{|Nnk-#f1mINthBk0g;1-W(z$qa&}>LI9LU|@|9*s
zziD=KrP;C6J
z2PvMe!Y!c+NN%nxKxqK=_xs-E;R!i{!Ag(am
zB3u1`Y-QpxV)z3z=~1UV#>WY=7Oht`Y!$#HQ_Sh$-+!b!=AiDNHwL>85b$!zgB+~Y
zjNA$}5o?^Lxh+Avf6Z#rGJ-a3IVzbdz_BDBX+X6X!U`7I9B4d&%#XIX9sL>Q1kyEb
z&{lem9fh?SwBe)xk1vL@`D-)b1IBC<;30;H5$rJhE{rf;88tj=23pNefr9A&<<>UE
zlW&q6zUy9{TJ}#e_J&Wx!1SJm+&N4}uJN%JWNCBuH1=u<$LcYNER^|Jg+q(1GyJVJ
zO4-5rwY@Z{4j(-4v=KT%eD69a{5<{0+yu+wGk@6+c#i}BXV-iOZ?&4
z6j;@e7eb++imh_ODa!Jrth2KURU}iK!r)b+rmYup7MN%ZO;JWwUJ9&1KY6v#{!lDA
z>^Z&oj9i<*M~FF|o*eA0z=yl_stWRMTJl84gR=XxV_DfV$AC;Uh%~rTAT8+N%tS3$
z)SN8>jee*Nelge)_{jMK)wh>h{BKp=&Y9pPUKt*+MloCx1|;y$Nrnuzt}93
z82|TlodbKB-(UTULB9+diZ+bJnt^zC#?!(=TeWlbbd2fA3s2pWGHmI$n0PJK*l}Rb
z+>SvEL00K=Hq79XDlH>jF-D_A
z*GY_5zQW>ZM^xUK->kI?;yUtDt!2DUAI=dJ
zZm17W+8RmKMwtnD1dr_zR`cA0sr+yjvT`gSOp?w6HuUI!ReSM%^U{N4`ylHx#j;H}
z72gB6tKRV$_C?;!{bn(|jVv{)<`hogku$6ytHLbS)FY~t_7`;f{QbS{O|k*)Q^%14
zX-K28Pn~5p;TG0vyT^7>8;*>s(C%(FC!T~3x;*y1VX$Up__@r;b;jua
zde{TWb{zq$Z#d-d9&N}ztcDL9;@9l5Z{CvZOWh$wffBz>NBR5@ulWdh*#E=4`tSLF
zKd(`~f1lU#gI)7l@z1V#IWVv1cm9WY9sUNHEbh;%N4I&!{%T&)n<23g21K6xzn@ps
z_FKg>m+m?;;oBE4Q)RBo!yfFHJ8Q@Lunwl^GWI#eEJ2szsR1Dg7G#o+vDI{aXvHKYC5g^YjN2>(W*1K!Km
zQ6sLOO-RCiezne+nH7P0N5yi)nY?$(v#6}X3^6wr82BWLgV`?jR|T(|s$FOqBXQ3F4O;OBkRsOv@d_PgM5U@iq*oyYyi!(xnb-w=Kt
zbeeqIVSfjtWHINYBieqb?ZXMn@bot3;+l~-D`E3wDE{da%%85M_&Q>o4!?8>wKZ9A
zrz)G)#Ded{-zKp}j;?c9uYARCHT}+Fz4CP(iyFK5O(V{&x8<99jywY0c2Dy7erl_y
zjwptd9uF*o_2d1(l8yiUM8ybnzwe2*m4?)hNFO8aQ
zWN+~2tChdyo;HLpQK5Ejyg6yKMHyk;D1-Dm#&M@K;iOF{Q6)>9C5h4J3P~P0f5?Db
zR3q)1`QNl-_A4+ulj;pK*X*jArR)R-sv2vqIxH(xph
zHeJlSji{ggfQ=r2jX4ZuqoG==9O!;O?GY_y95gZ0-kBhMhrb~2e%Xs8OD`Fp+a32P
z-oh8(iAZciBE&Z+yx_E@+s{{?Id#fjwd>ru6IGR$j(uDH
zUFr2Bw&VD|4&T=;co{V|^8Ui4g8sW5zd<$Sdi@41xUC2}l}MIti=ZX3xWJY!}%yaWm3oX6eq3z$X|x7Dm$Mej@%P%poL{PMM%<6uZ>?{(Rhl_}
zc6hVFHJP=Q%|!$rA|>vL;CN{4?o~2npr}XRI>@zI$etdg3_hX^*N8G8ej1d4u-*sC
zK-lgBWxy5t@gDWU3OTMkKj-@$Xuvg<&0$h#0O|zEG{859C0v9L1`AI%T(eks4C1;D
zaww}Zs_;*HOGRfhm#@|TzLcvL^u{>CZQ#0$LsCiJz!25jGp$=o%Hr3
zXfx-vZPXiWcfxmKws#`HQK`5YwXCE~UG3lkhc~^$3H>=wJ!rAR_cO(6>W77oFmAdL
zR^S19pHS#76=~E=j)rP{Ogc{W73^BK!(pH*3zF9O
z{vFa8vWV?W0KX|rOA(#ghdtGuoo+|IWrokVW}^-Vu4pJ|!HU4jMq;P#-))@a}Y7
z^tt(UI0J5gveRD&fje}%N{+gD$_L^4p5|)YL=h-zm2op&`>Txa}?$&`!cBL10Xs|eZVkKw5nm-XUVx+~gmJdpu$cMP##7{t^!v%5Tti
zD!;VMHAEai_LKV-R7&6Fupq^nAL#k+1;+4tb(9!}xMS+~U8?!CGL!lq9h2hFl-n%v
zfP%pic=JHDD%f9#hbNA|EMla6z!=*xoSlv^PJVv_{J>Cq8gi`)9-~Z|IccjgqN+D`
zU{>PJkWOU38M(|I7>BIoasO=~Ggxw7=gJ2%73M*wc-Iqtt~?&?;pO5+1P0-Lnc497
zzcFGT4JSTAI>mUp^S9R#d+k#t3VGjgzJZJf>*u!HfA(fxf0X)8w7@%D?#Y;0{wR&0
zV^e4Z7pfAWQB-D#3Ip)LWF8tUxwTX7k+&M=+RzHxF_6ibhaP(XUvC8OH?}gt{c1FB
z_MwK~K=iWN?pus
zoYAwEyOlFqIiVFbY3*Qr9r)5fB%8JDZOMjXge
zX6!fzqTQErX=3(B?PK=<+eT4xfNReUEKW9DUUCa`47N1+k?`;&dzDXu#7WapmH
zlcBllH1}sZ>*ZEFi=A)-LP!fm?_qwsL+_CGFXa3CV(FA4!8w(X)cxfQ*rA5S%YNu?
z{Ozb)U2y@DOt$FC+k<{=J7n}yR{$uE7Sy^
z@6r3+F=VG@_5*KsUW1nY@Nagy5lcflEM!1r+*5gWw$+Q4QMH3;yI1}z+KBlL{?(`k
zzlUF;FO7P)>r1HP$MY;Jcw}D!JIh-r<6NK3p`9TuqvAw@-M+f-y=1dV(B5y~q{8Bhk3HfV7*
zW6)%dOobLV+nivQsb+NBr-5006f5+slX7hcW%NXO;vo;BUV
zA2R+my}asx8Ss2fS>wn`Cv;dMs)!(7=%QP@M5SNX+*kR!RmhOx_~a)cY*Fx}0#%FO
zSUUZfqW2^{8F^6+b_KutQ;{lNm@a(|40vMyf0iJXarMvYKCY{o2h2l+*)0ZV55$fD
zt3Hnvz|AboX9fw|A+y)@wfUy@qS#DX_a!0Q=&UEc(h2^5C$A789Q+IMe;Ts#-amWbReVSi`DiOqKmbL}q{vH1+<%AkVk~eXGISR7$k!L^u9W
zG1^ik8F*my$8R1RZ8=A6WQX{|#|p7U)^u~Rlupq)q+_Ry#*{@Fad$uNH?t>+IvBKv
zaq$ZE<<2k+U-
z&=$|coHn!xOyud7jaZvrZoV`jSwaL!FWAi+CAGV`IckvFzu|X?Bd5`h560F~#F?`5
zw>DnG*U0)l<%kj)@M0-)Qo{rK$*cQKG;`g9GoRh2sxVEFFy2{<)`p;{JI!_L5{Q4E
z)wnU2aKA2JpTSO>
zT&eV4Ivr9$f?`9@IJVC@#ALm}nas#DXIQ3wDCR`EX@az!=40!ckFq+*3F2KY=WB6m
z(^USO`FAUkeJ{QR`@qlrYvAKMUZM-x;AR7}UWRW`wmHV^&2H`)n6=_C#8@p>5}_WUQa-~7}E?$)X(|LV9-UQ0F-
znWudu|E}i(>EO&UnDfM|7c0y$4cn!J;CT4C7|#ZorcAujszBv~Cr#u7C(ZMBkVl)x
zD9?t@jKIF`XGXu$Bn$ktC1tke383sB-&vPq4*nhwzT`*Q2Yg~jpzFQCl2wR@bZXG%
z$3Uv%T;{f2;(Hh5%lhIGCXRY+_0G^f%4B`
z0uwji*lT7RD9)IJMM8YD8rBzR6(%04|2!?lw80df-a2jG^s4EWmsoQ;^fSoTA0cTG
z(V~_t{vHQ!?>8gk_0(F#gsWMiH%
z@wIZ$+D2OZi?27M<|>|~iX*Eu{l#DZmkjZ}ps7KX;jso!0)rf0(a>9v&L?&@bRoDJkXx$Xx((W6he==O#=aap?9G~k{7poc4bt!AI9t-?
z3@)e0TG~TsSaB_7yz+Gt)!hNLb~Vyo957SNEzM7k+NG>dh}ng535~;EJz9|Bh=Zc(q$<*_O2c
zb&cQEs>!B0@@vJGdP^0#Rl#NHyn;^y1_dS-Z}KPd=XHl*-$HHqu%3b6ZZ0d3{A&Ju
zw%J(-ExSAeDH(tHcf4cqru5*=Vx^$?v%2v
zt5!b>O&zpsGse9r8KYU%$n(&ls#NE^1X-kE6il3~DU-ErI})+FkjzRG@kJG)z8;me
zYt^PlWvyEEoJVDCnlDSyrhR-Fu}3=+@^0|+B*CE3+$MSqZ#2;3#n+I%f~C0{BnRee
zMBQk@+~izfz(@>G-Ub+w#%?%%S`!G`L3IvltP2-s8|X53sI
zCRvQ{SBKfkC#8t1HF2JDXwU5B4^Q&NAkG$^5o@2^k(_6Us0H+YhqF!>j`f9)yISSt
zbm4!JB$ttEC#@fBnl>~1Gbdij4{6$xf2CT+8LokqNd@a!Ogii4Ye7F3V7LDAsZDqUZPKba
zUALf3>yNwogEU$LuV~Y*oObhBxcgxt-F;U#0lW-pnX*7h==vMhm`K;L$ZkSfrykI*
zB72OqL65WY*thGBrNxxJ5R0AJXxt7OZ70q91G=_ZPv&&jwE-?j*EVZQ>3`C+D|&WC
z2d52t;gFGuh^RYAdiLQwR#LKN(4C8ipnv(;b#wsf;y%_N%`5tq-fdRE`2u7aTCLxd
z&^qye2_w@03enE^SB4`ulCoCHN+_DQ&6Qr2qIr|oV>_(@t%s892J3+Ayz)Bq46cK&
zovAwn?HksMv~RUcLy=oMfO%u7!YletZ_xHTuc`Xna~YL1tl$v_GO9|i_AFy)jbmaE
z(=ITQ*%(oRTsQNP`--j(M^DnkCvAnjW>qUgF*bp;L+_9b
zK~W1Knr6O8)JDIi3{r^VuSW5T3inp~6bK&=AFhYpk}DgDb**90u;P>!XSJaP4~kdXG#spz34U>YtA>NegihB>mz)RM4*sLW
z!UA?!VB?lLW53;4uUmj0t68xHUw+PL1Ii;%V)n%@$xE@?*~&EFTF6tzVBe{5kj=;N#gm5;j*@LZPw+cin!wA*
zu`%QYNInoRo>1h7IlFPnDeJ0g>kT=575PBWx^9J9^(HQ&apXF9DKW^u514p&k`fJ~%#Ra#G5(viw{t8aJm_Q(3-qzg
zBCe{A-fXEbiR-GN9aX2aZ$$iBbaRT;w2NfGiH+rxkv9sb&cx*(AUdEWv`_uyecJEu
z+NVCpX$-ViqXpWf?Z7zN71|NwS}oR+_RP3aEAIzE(RP`uP%L$QzQkXxfV3Z4P-
zh{z|x&{hw7PA^%frHqff4ei25qjSf;$~
zvIG%dCu`No+6(Xe&qDg2#HIFA+fV$b>g9h$gsQ}PDljtVf^k87lw6hVnTQ!@2gBm4
zz_!&KE^&JVCb0FJM)EELHgEld+zJZ|Y~6TMzK7PG8(cbgSNKV>8De<*L)=UK8IjSy
z=;l9Uiy}~;5B2>LEZ1|xkuBv9rx0z<8Nyv#Qm5Zmxm~MgQNGjE@Y^bv@Q-b-qSt#P
zDumZ_p?Bz;cPc@b8TbeaCYR2Kl~iZDQx9y@0P4oL{gd
zYd>KNvW)Cx){7_yFFOEMu~ia$iMPH99}c55iG4iGAbo;$eDhP%VFXU5Z>95T2c!V(
z$3ZS*8S9S<|A}Udu}9F__#O2>DP#8kRR5D9ye4W$u?>|4Km|5j*XR!lJ;ZgF82!P4
z5l>X0Qpr=`P2q=v*~GQQiE(_KWa03%&7)2cb1%h-eWt{o+!zio7vtLI6mY(%HB-wv
zecWX5Lu>n-ZcUqKsxn#9KTS{0Sf8O8`_oH*nsIK%vojCOWX%I`p6Cxc`ujKi@QeQ7
z{NAI%TlHs4j&d{9tTewP-Z1k7llslZtX{1>o>;~dv~h|HocWES0s4Cb|i1__FonUJI)Z<6t%R-&Hp9|P@T5o+b4ke-z16e59Dpa@g#9W5w16q#P#{S
z>_4dQPz@L0(c-z$7q;^xk%K*VlOqZIdXtCi`b&P280KM(n>|UadHF%sTvlW-$I2BN
z%m*d?aQ%QHPkl#)(V<$2gSH5$^>-xVeM?Xceov(&;q`w9I0N}-GGPn1x#
z&qER|;T&==Y`wFV_H#KXgh47|65oNgXX_UQ1efp;R4pyEjjLt3vHey2D{lS7hYS%T
zqTP{aqTRReMv2WES$FuvhhQO#R^arpk*7}E$@>U!juAUgS9X0zQ-lEYajt`%9y(=7m^;H#bb#Sh#A&=!KH|?(L|+tmoGo-n#Bl7v*dKWFB3ZL}z>aL3cKAkcivL$#o04S
zlI@fwbYr&uLXVz9E&dJtJ0r${TV4B6rctB5pRJRkHmH(sCj3t0>qrl{^Ua`LVyph%
zW(zDoxC@)~o629y-Uy_9^mX=}_*y)xuKl~)QHnZAu-Z6GJ5W_xh2J}oH4;}-K0LAM
z_Xqep{Vu@Y)p_v5E&Xsvu-CdblwRwW;T`Z%QU7u~&Q~Ctq}uK15$?{KgnZxYG&ytd
zrpE19w+cPsdcG3*7sGPUQxAQpr?OyAWlQkYut3`4Q@QgE4#9<*Oz1~F*5Gg)hlh#Y
z7`-n1K$@|4Z8-Xj2t_a|qu^gzoOb$53+n!uXBOnnHdB=%PojzJxF_yd}h+p3aj%~Lj>h{^Pd4+^vjgVs7YKV@
zu`PX-ccdAM)1nTsux%t*N-X*@Et!&5|8*U5pZMU%!fXBU)%R9r+F{9o_oeDx}VGB#(U+~PTWQBh^a@tW4wvp<#rjpdBSA
zo2joxR06cV)%S=$%ROzz$yw;ASH)N1MA29(SYfmockJMU;Ai5pRAtKlrVM1Tda?QU
z2HS^9tDxt<+GZ8Z7QL@I(;YXA(GQ#2d-586bu;z7-Y56{Q`$Kb{F#_$WDOx)?LO{Q
zLCXe5?xB$zv^)!W1~WxUFFuDqhy+m6podcJG?r60H4m}X!RCfrtuvgvKLi%>dVVBy>h!=ZX4Io{kBee#*4P!
zGqB@D^h@@xm%k5pY|>Z*BP1
z)_GvP7r*@P4(!ObjJCwXwt$RYxB5A3s9kGA_EMeJL1^S!(^;EwR+
z{+-?PgiwwUs!OV@;Lt2D&jNo&3oc7brfZ7a>&E(fglBWYMq6CvxLf7H-aoa*k1;?i
zt4c~YX!gUF)=yfV0MGsF{si4Uy7P*hLv+i9e)d;L1JSglCiGqUCh}H!(~`{CV~Fh_)my-G1U!x&0JLOy^3gj$ou5jnu6xQ3bIC
zYoM0Qie0bpjj$skC0#)9`%j5-o()zs(=Ma
zt+Jn8)|@o;x$qzdOgyjOJ*lIgJs5HQuerrEx?Pn_G)}z}PfJ5jVKwZ(uN-;oX^a?s
z|1i|t&%T}3;8a9U@byi_pG5aOAY0KoOI9oEbg-X&HR+$5w%mGAI3kd}#brL9>6%>4
zNE-jfa?EJIB~?=kn6ohYs(QlGgz9_B*l0}3E)Fgo3cAaLJtOGL^E36(Q7LOnlqDki
zF;JTM%+p7_&;|pJ_q=P_E`>!uZKpBP?kLcJ3cKG9E@j6=hkY)Iv%god!ZQ|V3By>{
z9cE?3IiE6O?`meS!)kfPlK6qk{53`i9Y|P3vHrPuE3ei6i)SVNTCp2%7~V#X;&MDu
z^*tjR{>iXocKUULh9s$N-lq2m=OP^(Xwfj{Ov{HZ?8dc)b
zU6ln{r^<&)`<&5XyCjmHE03j=KaC8Xqs|XCMW2T8TN>t1fP8_b?q~)XTs85m+aqezg+qCsj745tIl0I^X;kc
zPF%12;nkE=?;Ci{IYq&NDL#opIPEcw`z_?#a{#ai|*j3OKd2
zWrp?CPmw9}22kebVmMnG%h{ey;%v_k;kf5VbG8XDaNLC19QWK(&Njx%abt2g&b*D|
zEc-c|rG(>zvz$%1#@S4_I5vY#cNH+bd7XGQ{8>>It~Q3nsJvlIRYu(lDzEMqXAHl_
zdBe|gMtuqA)z5~fYz*g(U^!#tHkCKBL}h&Ftjhb)H5KdwDsNPdih8xBq4(#`VpJs<
z)qad>8%BjuOt1z=H5;RP0izm?Q4PVUk}#qej>}*A~NWdTKt)>pMKv@Q`n^%H@?_yve{gJO=K&DqA@;<$0FYT;pS
z{0kUQjLP?H^z$Eub7K@8?qJd
zS7Fr^07oaTen(;cV&qIWB!0Rx=0lwqo8(xrOE2_#|%OF>ZVe
zx3H2M&vFY-7&;zdL{(%2H(t%8j^Bd}a64FTd=Dn|9{2O%HBRkX+|Or?T530=y@&OpZMgD3j3y%Wl|8IoWw^3}
zDg16bYmYL_L@V$StBEpP`Cle=@kgxvA;Zl7WeR`X$7;}el}Y_8TAbm^-^ewjmB{0Z%pdEU94SWnE5(WczqYE
z(HgG2&ZN%IXYFXcg<6OCtos{SJ`&$#3U7SK8eT$s^FNr>zkJBLFZIIxe=vnVKzf^w
z_U1R3)P)7C`(gs_zrhqX>}Czq(B8a^NnNm;l`;*RmoSC3usWTI#@$z$!kVqDYP|bj
z2Ik%Ik46^yz4-Nhq&>ngGm%MMbci)9?}*wye&OMVao6zHU93dc{R86{9_fes?w@{o
z;Qo>E3rmO6{m#w@?w=dKu>4u-XT^i}zZ<{s*o*Z1y?YNlzp(O8<2z;={#UuX@WlU&
zH@y0Dl>3)oqLwEvJZ1R%FHy1<5nMfaDiD_@`z3%kaNoTf<-T(#iX>L|?b}hLrE|Bp
zM;YE|k0SpQcT-c8`{$pd{IQ2F5N&(e**bCFq^e1lX`fC@p1yv%=B3uL^Tt(;vyA_A
zybiR^aOqXXj<9ULQO9UU!6MRf3_?STOF`eK8
zExb$cfp^0U(+NJt5PVE0_&|#{Ob0B?H4{`^BB-zsR7@wRun<&SBB&4uDlRPpRG_5}
z&4YG8UTv(byo$7D!L%Hqqsc-+tp-!1f{P}xk
zy~j`;#vTd#+>@&9$%?PWgGWvAP`yRSvek>JrX`1Z@AyJ$XE|$~P_oiGrbKl4V$Fp=
zQLlwjovQz}>D^QMrfOeSrM`_`U;UYV^gZ`fj(wKvS@ja}H>!`|NpU$Pw2`yfGyxtAXv-ph#0U<~B*fUf+;5`jrQ3m$-YAt)sW@KxjuWv>@
z_87H)egAGT?9V+!~xlYXamgzkDrydV7L^2rEjLC$m7c)scNo2JUEM_
zb{Pil>Q2rWm*U{fPG8=d87B+}9;>7T9^*MX8eHUpzo30iQuQ_KYS%ZFce)XR`Ab2^_&{dxP
zNBz@!R9QGhV=FW6`S4znZuuiQ`b9+x&X1n^7GpIpkJbA=H>LhPpBZgS)qJmVPXSiM
z)%P{T$FaY+>*KY27FEz!rP??0_%tSl}NXYkPJ
zZkK>tO`~dJ8d>v$GL>{=mt%X@$gGlLNf=rF3i+&JFK-q1!C)sV(u9Wi`<^CAm-HXL}LZQ^6vI=5t5hyvVQSmM6KR&0cSG@Wf
ziwGMCeiKZoS(1wIuOMqXzFK^DNF$=QI&;(=Q}tz^nAp0GSpTM$d+T}rWXbCdYx0hc
zww4H^=fgj-X~CL=qe<3n@CxOl5{|}LftjzDF$qU?R;O0yj46Q^qZH2!&Q#+%9y)*MeT807r0%S+Q>O}?{Um$U
z{~_(ocz<
zjT))6Qa6+?T6i>17t0!OMYQ75qGBU1t!;2Y-1)ulOd{&j=l6VGpYI=#nYr7!=bn4+
zx#ym9u3%|40I`a;90BB;OAO(h+K=)_old(S1wRxrrf05{N{V%CqlBUjkJ4%?=2mI%
zeC+*kJ5C_(x~eYaKG7uyuZ=qz7d_cY9bR#?Dq7=!_M~>2yW4f#h?rrJBi{AsrO}Ff
z9ZxUU*zt_WJtpiHi6#VjatC8bE875G2Y5_-!`_ws&B*5x;j|i`eaCRnVFK~nzB2axn#~6|EA$V#3o*@%{_oV;Q#D+`+9${(M(*9Y9>j*g$ZfS3h9$H9sV6DUBo8XVf
zbzU(>klds7VqTP$l=fV`Qtze}ciFaH&;swXOty@({+MIll1SMVdWr&sk%|G?_Ff4mZrrpTPoP&w;GZHR
z@;TdL>aLzP9UioOl^b*O{W^^%c8lJ*vl;NGKmXM@j*eIRQxeAk=y8_4xk}xMQbj@Y
zXEqV-H+&&vzsh2zhjWR3oBY4f9*#HL@krfDsr$36dpX&8vyR4zH_9lbrdxn5cvwK`
zo{N-ib!33j@xJQY|u4%?atmD16m`gTRMNlpLhC|&HNqCZg6
z(Y1e2wog+7N)Mi*-gcB`eL&w{{+*-7#)f>YIOaIAdYpaV+AV9ITC-;T?avr_X!)3O
zZLe1;ZDb%FxF>0kw%>JHJK!kI?@Af$J)U^&4|76k&LNypPjd2pQw@uJ+@M8q)hJ2}F^f$ZlD`G~k
z-2KVYZn*=@C7C~R!?FT+IYC-ug*OJ7RV>b@i1hABzw-rWD$ymE3zFHSv<Z&j6E5Yp!SQA+Wj&leK%B^IEn3_l98NkTkV^CnSm`aCocypi~}&A
zX6+q+_;N7e>OD61KV?6Th)b{Cx@$At)|Vc~sf6v)PwY|&wM-S6MRFhd=irm@+bMh#
z_J-triEB}-)tR9`>nxe#Yh`m)KOUk(m)s0<)z{9MN_S_b<#KQzz_{cyx14F=+e$@S
zwZ66*&an9sk)7dxsGn*fyqVGNWt6_0r#e6}Tl=Ymw##0b8;-kw5Z%9J!Ifm)5aUYYZrkwqiuj&!R|12^sk3X^^F8cuTOva12I|*gQSC-`<){jmpk?89cx7FUtO&hPu^|
zpPR9t&DPK?H;>4)Wwc3o{3vDHIT<(M+J2Odq)qH=KT@`!e@afoL{B+RGd7$+Njd3m
zepOF163f~?Sj+d7Z>a>mWfFReC-jz~R#?Pj<=I}+^Abn=rdo1;g}vh0eOw>({>;&!
zgZ(JvY04{!;!oT=mVWX+c*
zL~?8NWYr&=rVZ;E1Xv(lz|$f!AW+*YBTyT@GEh5Uuv*(MMy-tkC+#y^?MZ+7CJ$k-
zC*9Tt-q;zlL+(l6e?u*?Vtral1K#y^X0QArqKtRJlcMuhoPjO)46%FF@vt~N^l6gc
zmm%>1pxiuG&U9{3ETj9N)RJ75W;!PY^rJ7LPwQ8(evJQRe)M0gneEaCSQFAlf1YSR
z9zrdX+g8u(8JX2bP9&*z+gMkLL7k(&KOrj~^Qb*1;b1>GS?LBkV)l;VPc(AZOslXe
za09s5oj2_sbVdqmupl8WI2iQD7LJrVW9eT3OY*x(!Gz-0XALH0dCEM)^>jhbzAvP-
zTRI&S%Fg-@zLm@s=u&#!VGQ7Cf#7I?;Any1Xo28pYH&0)IGP$9O`Qfj)3{;py|i#w
zVnrIF_>qzKHnrbgdN}S-J;LYAZQWK_$CrQUY68j&wQfH)?J#);
zq%GUO?tf}fu(yq?FEqRj`cRN8RFEtnK@5fj@kXt0w(hSXPfHPj=V|`wB1X*S;!_nE&ua1{55ag=
zvuiCl87B0({!El*TcO%&!Kjkiy?v8nFV-oBPfh<~3!@)eXa^4v#{AF*g^Q$a;0}`8
zznf-ViP#IuRe74qE_OOg>p_3;#{&fhfC2+RfdQaE6(~>@1bVP@)ij`MYHwb25^Xgt
z`J=y=kG#~7c6boAfdj-X1CJX{;jEXZ`US@(H4MW3vYOtC(amkh$M_Sz^U{&=CkLSi
zXt`zJ(U^vQ)HoskPeV^3ztB!g?vdG8A5mx1nbSiLduwUxak}TJ7Wo)eJb1%)+u(*B
z!8qRqcktx&Jj@x$*9EJhEV#Rd;HqW2-5ttYCUl+yI`6T^wR?=JMNVet!0lxHSw`*P
z=juyeV}x5suX;4`bl8oWy23DBgj_~~+xC!Mi4x%p0!A+aaw7X?kdni>1foFS_
zn_?~|DZUIwTFaqIw}LsJ1T71}k*5OnpYKN{5nk3b>n`d)S7PF9-|X*4U8FG**Fb~k
zF4MwlzTkk{pZWDN4Ifmb_1KRU_}Av|0}k>$zp2MQq&6if`a#3A;!2J7Q|E$_7-F}A;cI9KT6`=!#+bSJqF%$tJ9@4?5QvVo6g)UCVDT=1}+|S
zwxleH^2$F=Bz1kg&)0(J!DgoID<`q_imf;;&apEouri<|nw`Xst+|BkbtnIvRkJJS
zI}7I1N_cYqlUS|kzrks7ZFah{=2rS(*xT^u_^|z{FbE|L+c6imV-Fm}uJ`LId}B(m
zM%14^S7MlL6uzXEcoyDiaiA?b7qNqkNssMky){IjhV@?vY0caD@%qY_*8Da4xJ@lp
z$^7L)O@^&nxn73x-bJ9dGv$o%-L(blA^cB?4aRjJv|ekJ4ro(1p}tKHC*a5~+DL4a
zC{du?R&!n#AX_Q3H{j%D1*~2gr1VDq7d|t&P7y3+MD8bR?;^L<2Zw7t=I7V@vf+bb
ziLJ9QQCmq&c*g;cyR{O~7VDrX0;TM=ON(%@G@
zo(Q{V;q!+>;B)US^D*A*^9{lqw-W8yhzGdv-kgW_>U^n89@>L0gp%cW(+x|(FC34K
zJ(KNO*!_Hl3H{{9p6};_v3KxP=OVYVH@pR#yr2jBW`L?*fKQc=f{&EbnbQ77S
z=idL1vy?B{{H~|zrB=?wuDl&6!0r0LQ~zV}Y@-9|cCPt-;cN2;7|&h8x6SVnjOAVj
z#`romqmC|DgtSyX?a)XANBp_
zC?fN;_x%6kJQdnY1+TgOf19TRfBpA)N;n8qg13GIu>Kx;!VZ-!VmL(soYewa@1dr5n%+lQeVa___bup
zv!*Wa>X7v+ZMz^6Zk!4&7p$;+eRU-P-c>>=ZoH@de%4Cp+>TZLT>i@G0k&dWNym!9
z_s=!9!>edm&5zbfOIF>89HSNRe34<~xf4&h`q5`$A(oY{tUa1Oe1-B@7S0~rYj4~a
zdY_s=djHY^U++`n(LcoRIPL4-Xw+wW(7#0VuZHJc!uTY57Ou1UQa2}neqB88;#2Xy
z@cV3EstYv_tm;egG^Y@%-~Y|+fXCMtBmJi{QGJH
z_)(@Wb*CP)Xt!G0Le?-oof!$Pw(rq-;TnPV^8X_bLpj7>eU4yb!S_CFaL=N@PGOeR
z4*P$ZCCx*?8!P^Av*ghBjYlYRl{=xW95i1_k{hqUS18{uZhS1
z8EfQwfXmhK_`hzo`~c*Zu+Hm=-7HQoo0j}52d7@R%Wt9b55Y&!fSOO47Ed8|q13J-ijgWNso&@DsS>109;71v9;~5|`pZ&2
zRf<&UgH#z(WhC`Z7N06ds{BE!0;vj;+MVN5{gCSCOWmm4L}``0*F(#TEyEA{PB;V7
zHk^vG#8Y+0v(9Y!W#7rKt)g;I{eVNf&KZi4|q#t9rr@^UpKjJTRyn11FlLH)#u5&dwJxWw>;J;&OvR&qV;N*%K}
zSvmH3n$7SRvE4d}?uD=xtHSLV(Y}#d)n7~N`)jF*{W;V8LjLTw=}g=FdsfrVt@bI4
zbWc`ZK?iu`a96
zFpWR_u%9i709-OUe9XsVL}N#BWL~LH423-d+x;e`ZWx9q*l2WbrJ}h8VnYJY2HVs&
zoW{GH%J>_wa1fpqY1;7F8ts6LZrXk;yJ@3(YP5X@YqXIu8f~xf8f{n_Nee<+kT&Y`
zAZ?#-f}*N3Oll>~sNpjiC|B0spp;2>V7Kr7TWb&aV0BlYSxvF?+N4aEj6~=0
zrWwy(F!yl2&#ZfPYUlCJn=fsC_S)McpZ#&(_s%~RuPawEnRJ3Z+i_SebAE!T3rp4V
zo4xHzx4x_vYoAqje&wQl#XsiSm6U`T6JDdxvrpwx885K~Ieo(o%QG@wDiuZ0LkksM
zxWs8?_^!(B>$dpam&=t&tu)ugU9hB`*=no0njx3lUgp1i(%P<;P&bid;!cXgPOe4F
zrv0-QG@9LVX%f|bh<-!O;vRMpO=rZJ4~eLiBK4|V+I;9pdu5jm>&4Yq+sXf5+ruRr
z*4t)%sE^TeVt0Z0?$5dAZMkCcrkALdU2OK@0k)4r0!l0YM%j;Uqe`nkrpz0=h|C)f
zwSV^UmXB@fUIDhicU7fT?^2!8ORLP(XCG_7o+YCE+)rJD^?i^uR~dp9OP2?P{=ndIseOqWljizkn}a`sQ`IRP+^9dUp&R{T`k#e~H`^Dt{|@
zYB~GKyFntu`Op6GS-Abk+HPx$*Nk&~=1?mX5_gX-=j{zEC@sBw-5Y)<;ayCA
z@h&32W=hMDUoq^~@Y}GI(#puM9Cm5sJKh!K7w>ZNJ&W21e`l?dJWJ`bnOeVNlznnG
zVi%l890T$!qi377{^wy;gRk^4*vZwv_H8aWayNRT0z1AgHxQlVJY_!(3p7~Xs9zzL
zXv6}ISe`8BQ$%Fu}W
z#%RoaX^l9lqMJD?qnr5Ym~Q5$>2BhF6+z~H8A0OyF+t}3bWjN99-+6L)Y$LC4W;4;
z+E#gu(Axxo-j=l6Ii_iGX?RYZ`5%_dg!8$bb`!ooV1>Z*VQC(0XDE@fp5L8+>b$==
zKEt$3u2#@8JM5a2aZHBtCnu$h>zuJTSost2L2$3pw7+1;FiBJ~@wWIa>1r`e+ooQl
zY?8#e*C*}F;{_w(Bs_>+&yS4@E^U?sM
zUk%TaD*(qJ=yiWY^mU2Zcvv#Tv_ZDZVK$zX2)|eOU#GDP{9mMyH;;=#t9Yaf7UoQ8
zG3S@H6i-Wb6=wyD{jx~PQfO;lEP-bPJR;=K;*|X}!{pcksVXb-bJQ*(HsH!*$4Slb
z0D)ew7qoi4yz<(5Koyahj<(~G3!YHX@$e=B9O)GKBKQ^&s6H(loEG`ZfECg+;it$L
zys0|JTb4aO0z7sx0vVMc(*T
zEoEKf24jl~J;I&QQrHsMrRiaaodX^J`pZLLOZ5U%VT^{?iqhzU%|GGM#0%wi((4m{
zp4b=o9h^4q_<&pjU*s=|Ctrxmi1!b+D`-i~INP`d>9*7VqHN>lrY~08PCrL;a`&1&
z?W^N)CzXO0^-{r3Yn&!S`AQ_MtkY!N3s%0ehGL}dZgX)L`!Fh9zL+7gK+Ls~*h^5b
z<|ohH_=rCQR^scCVIm$iHe&<)Fod4MtH!uAIF`^?T@17U7{QbobpggV<#JHh_XkN7
zKj9u|olkti!h#>6MDJ)HzfVSXE5-AZ
z?PSMv5m9|+;ED9BCnD0V`?@FkwN(y!_zI)!zXRHEVjlte{_#K4cZXH^2u{KG>eV-%
zH20$!V@w1c2X-i5Ur%E5^x`C5xUo-=LcZH}eM0(VQ-J%+t+VFf>^AX#+y-tVY-d=N2?`cP;L}jb9vMBa_mx%qafnqI)
zXlh(lvDEa9Ng31@hTFj_w1o_{XNn>h=d_YNrp$C=hsK#Ss6iXmHW8Ze0BK!l%yKvE
z2rD$3AV2!pWS2Xs<=(fs>1>vh67of6eg|y>X_2#{J-@3unzy1M7B|GE
z)N0xVJ6hZfCgfS_N!cNX{jkAP_%vb;vj#@w*o5{ho2=xP=_}yb@aAuXE>7JF&!8(r
zYEQ{y8k}?V2Xw@P)msnF!xyBeBpMfKd2^E|B}q(5j&AT;@&Mz14MA!;>Z5oFQu0Co
z!AypFQ1@z5n`;TFTlbHi*pKxg^Y7z96n~zOk~E;i7;ZeE(+K(g;Yn%w5LSK$Pf9(F
z)>D#tcC^mTrHz7Dy@3|;8~(9iVbT!VuwY@{3-FU?biK$vTeFI2D660IEXQL9cuAE0Ka6t5@$pd{(E3J3ZRnd@)RS)_dUJsF{2Dx)o%D50O+LcCXO$c~nB
zy1^#QG*M|*EycckTrw1Mm(>?hrLrR3s8vEO5pNUBb$5Dk^cLam;j2AigC>yqdFC3i
z!NmR7de~nM+9B4aLr$yL$QL6vxXnZW(
z1WLeB>Z=&Pk7r);;+Mtf1QuIk4tn1cJt-+K3(v06o|M7~j!!T?IXSZf-q7Gl?e{wC
zScfmRr)Q4?u6Kk7Au`4!tQ;+}eOZ&U2>z*wyj^lil4Q}nM%}Xb#H`W}?%;-zm2R9l
zrlgNOOU`#w>NOaXLAp17)IDrhlsMzN8BxifB>T<0J$61YAwaTuCTdNrC=+i>@X`hI
z3g%K_RF;FMo`{(^9ZebiLvc3gC;N%aAM;Wcl{33SC?D|x${U5})KQ)kok8eT@kF&h
zB1kD)L@VDEdS#oW`4qkEH1=fzYkgppH3D5PhTAbS-nMOT~06*&HNK`S9y$pBkFH4J{+~(rCtY)
za1%?4?)e1g1n$ai0b!mYP_`ULJ6Mp5}i)PVtY&>;z>2PuoA_6*qf;63cl
zpB*K5i}^vn7tM*k8Xs#qVu~ssP#K=J#S05=Ep2J9ee|@ZC+GliCU`!{#1lV+GcMx)
zvtZD|mwn$k6Zt-?TKKM-;QQ_}^7(OJ0m+|~^kmvflTcH$L6B5NRT8=7NHt`La?MVj
zXOG05rOf+`GpF_+iKJpzWKhqj60;zSP@X}mgrEvg?=-~i<>BIDQT~UAwXgYp^4NbzLkRv|ZjmBXYXNyOp3WhAs+8;(5DWM(Ls~?w^WoL+hnmR2GnMko1|pB}bnnxBTe@&2;p}@3;3I
z__gQ!_I{_)j_(OK9zDrD!+O)cXgI|>6tK1J#Sm(mWw*I{k%-JKWgoMv=hNUVEj>PF
z6o<>~ix8C*IZL@-G|5?(hnyKCXOBEz&Lz2w!ac@%cW9Zf-PacgeDk-c7rgE6AA1XR
zE%LQ0CUv#jP}fFM*DRZ_uCg4VF4t~fUB$0^d2r;D-nx_tw_sZ>V9ymH#N;P32f4*!
zdO7A#7NTPFvu$&P<{a=Kc{SF7U%TbpSnw~)25V%FCLiAw+aev`5&T3^{cIem!^B6{`3kxt=B-Rf&JVj0Xn~M4e+a0+U|&ZE2!it
zpUc?yu2Z2i*vr=+l6k@tKTZ^lW-zkCt+FrGvab%M**6Tde@w>Sq?pMZCsB6W4+sX{
zW+XGcry|62ab%3RF9&Z2t0y$ZE(xJ%!_Gqz++a-P5#jFF5)1QNe9WjUlIlsC@l&$y
z8C|fRHtcdFm%D$za5q#ZX-qDExI{eSl6sQ9uYXRLtPj*hOPh4?)v9J&k5i%g5=U}1
zXekqsk5FGnOEmA1~01<7mV3GDY({3nha@d2}IHNluzN)v)P|
z2(-$Ks{30!tGp@lr9b|=`wwp}qr1nAyH`!aNDL|S4N2d^t0v(ouX4}nFDrT7OIXv8
z4aUV&zl?2sB`;R{r4-SKT1DDSDN|p$5&zYklrH6*x)R5LH3c>Gkbc6{8xY^xDDn(S
z@9GH)8@$0d#59c4W}TOmB#~W`51J16i5x3Pv61^qV4D+V$=@5z>=czw*(qX`*QLG^
zkWq1W;lku%OT%
zu=k1y<$B@mr@)Ov|bvHWGrR)8wD0pLpfikQ!FP1hO`!D`@PK8`RX9;9j^5*9ZHq
zoUd(B7LRJj+lZwhX1ZqR6{8nVC-HjVn<1jnc461xJc+GH7Rs(NK}Rf+;Esj|?;G*%2}@DEN%fH<|8!Q(gnGhso%mYm
zHh;9x8SnmlnN6r8F^_to(4Kw0T@CM18@@1A$w?~@K|)n6G^945jyVsfzISb-NRJWI
z`FX;cWIQC^T9~a5=j&7z8lQg%QmIN6LuwiH%EPJeT|?|{zMgUhX&{mi=g1g$mh7?*
zQ@-C4lRLNLE5<`qLTo8jNkcuVmL(7O;_>#Alk)jqsD|_HPky|8z8|Xk#pvgU|C@f~
zJwxi*G5+y-_y$iEauQdo2E_zC
zg7bj=$w?Xe33lrH5?EV|2c7q(;5=CZSQg;@%?JHN9ij204hj8u9ij0;9eELae`84<
zh}erdRBw1xDSyW<&q+~47AxjwA=!6h&S3Z7-^I_sa`^2Eb5K>E`iw3)IoQW7`hi=B
zswGp)H{w6;$$BvNLaV1%W4J~;a
zDd4>ZHz&EznF`7o!!76FijgrKR=Uq?LuXE%$+llWjFw3fP8NFV-eg;E%*GYRMRr(k
z@V_#6F7mClqO}fg?rVYcG1TBX<9kmYPax>XM>Guv5gDBUgyYB+E>=SBNeboHO2Oyy
z@tqO)mxAfXW-@`W|3j%ky}+dcF&YVyWOk)Q1%70eJ;ietHQ`%&ksTC-8I<5rl}`fQ
z!AI)9@Fvv`$c&_hdKDYWbjECm3r$9(*(X3>8225q59l16>96KAq3`k!dHN21d@c%e
zI!_14M?IkRzo>`sCc@!#ACP($;>NoU{`Y`4sZ=9D@95dW;plyir1KyhT{lJ#8DjOA
zYW5srOXqT>zteCFX^{uTcv
zy-azFK$qwDD0D&}lZIeE5B%Tsk(y6x8HD(Zf7QqO{vK7>^GJU>G&z4iMx`J68zo70
ze2Fc!v8mY
zDxX2>X+o6Czv@$77}EL+ytq@DZwv^(L0_lB)94)GuKBwu>T&uXP-8eaGR9i#D?{c$
z(>ukMv96574E@6tKPVVfYnS!GjL4Bi!Wtd3L=}R*p$`kY{r6dr)J>QLDJg^h06nNt
z+X@-#sK?*Jt`BfII*i2N`0Vtc
zuK%#o^Yh8b~ZqqS(sInZ1_O>rZY5L*zJ3S(=1neg(7MaZ{Blz~G9CQk8
zs&MOeN+(Wl-3?4F3Dvm{dFgd9=-{J=@$z_$zI9YLl+>6q;h)siYw9*wimFRa1;yzt2*JmUm|Es9s
zom&L@H0(@N)Y#%2eEnPhGGaC28{=R^4Ge7zsSS;{{*L?$xy1K&V$O=?)%TnN%{TQ)
zZ6NI)bcP@*Dv_SCVymb(Da_mQw}iEnXghp0QdB1wPOR6E6KiSD&kZzUYu+%b*E~zH
zU7Go`PA5(tQza{FJIX8wD|||W6BOLX^rSMW4eLOvWW*Y6xRkom-r$7oFrRjzdrzay
z*k)7)w@IxvI4?##McDgHYBOrXx5DxVKti%0dX&WSVn8_n{_w#6Y;&z%0y{jchU}^f
zh?5VQw|3$~UpC?kdNjKr`BW|Pzd}-#L@s?LUDTNL>3+49mz87!w;(Bc(+)-N!+8c-rFngJHL4?VonIRibYwp
zVwqIUnJA)_3>zNuM}bb0O|WkIB`~gj3TG;H)FS3VTYGD6XceRv|Lc+hUE-?pDt3M^
zv4%r^5fNW5)2)OApEAUOlJHIVd2Jl~&N(W*s^biUNHlZwLjKfk%XH+dh)6ms8D{o^
zu<`-!EXD0*x;c8^cajs*#t9)^_cS>{^PQLw?Zvg;)ShdRRQWsjCAL=r%(8=lRmoM3
zEJ9~B`^9}^)PY!Y9}|@q%U%kSvE09;8sGxwIfe4LF>#@~rIiON*UoSjZQhK?w9^CQ
z*wr_v6V7N=18grGutY(b0%dm3=%Wdg;G(rP=dz(ehv&`_4^@E@U%h@Y|BXx7$Ps
zJ?mvJr3TWZO)}PM#ibueyQR)1+8i#SN-d*kag+?V2$_2+D07qvCrahI<+-Jdfi5+#
zrb@ppr%I_Ux>5@j6TNdY75%SLwES$08T!QNVcqcD7ISR9d0Qp3GB;Ybc4f3*S4y;DmuPL+edOy*f3v$j_H%@rof>7G
z>U@>91>Vsi52ZiaYmYXH?2~oSj9MTS)GtxPVxm;y&}EqD_>l*+10+lUb{o_l$pKxx
zHe5n>D^ic{!x{!(Q3syCcTLXHiX~D$x{k`WS6WNRx)UN%V9RjA277d$oWE(N%I`%~<>>wW^>6t9pz7JxIz
zROE?HXf&0Zl6CAK*Zl>IzP?oRA=**?KEr`uyX}kVOd`FNsiv4x25pv{%vA<`A<-7z2FB}Wn71f#KRNWI6OT>~jw^K@
z=i|>PLvF`Tx+cIHuoe1WzU`+c3T^*B!Ca(7JpGcS#wol$*3*R-Hqcsd6e#;tJE7IoGLjM;$C+@?<3msuKmSdc7vAS5SR8=dp7Z(~nhNK}WA$$t
z=`P5*FMLf*#coek|GWnHP)jzY654MWp?ME)3^NZBt?zk0X3Fr6?>n9&w65JWWhlW7
z|6G{;%&DDZ&P?9tt@~9o=<4D5BiM(}tz3DCU|krUzK_j!VPqsTg!x^dYra5gHy6#D
zcI%J>V{c!!Y^J%$pYo3N?21~Uo^4NSz+tf7OcAKzji-eizrVsHnu`wbJcRH?RkRwj
zU=I4Za0n>Bw}SfhamojGLC^bKBAO_Nqn-67B*{(S_Qx6^*VH$_A6
z(64QR(7N?yG1j#wtGNVvD^4PQ2!UnJ^Yr4tfIaBRFNAw74n&M~w2*p}$J$0&5}7OC
zxM>5y*77Q${@SP3#{E4mVE@{z7{yq%BFT@n-j9@Dz=iX>F*1@Eg~Gd3!NmM3t#lJVw$=;2)nQ1@0Gu7K|7nPEgW+3eqoJ|l
z)XwF#WF?o@#adW@Ii(h-OP{D2GLG&1_5)40ue9&?$EDgn!D4ItMp3Y=Bz`0Xf9H10
zFP!?4nI6ttK`lxf2YEmp1X%#Li*>A?kw=DD2k!7aXiMD_Z2Dj^iIcv7<00k_%<#h8Dz%u{L8BuVnUvgUQ@rx1Uuz8OK%zYRj96m62U{h2sukilam^<
zqg|Bt8kHpXmlM7!suAt+P+!)^8iFc@=;;Hv^-GHLJJSRs+qvU}#z&97->dQR6AHsf
zIc*AGnqhRjhf`I~FmI!1lT_2%4vQm>g?~8jtJH4$)kJUt8$t4DU@AI{r
zT5-yMsnx$YXGo5Bt?=MX9#IFqyl&6pK&8eaQJQ|&M{^FuVq=WT)y2|){m`9%S-i^b
z=ml>c#Mi^O!69ik9e~cfIkmbV#=2ht8<#WNidQLDuab~-A+5R6m)2wJqiOINzDCjl
zP;S09``v>l5z*uKrc%Pg_E7FaDweSm885_
znAe=|UVvB^!U$wv42`34e@JK*!R6y^2zg9r$)5Hv)BldyE#K29j+A3}8BdX3gO*M$
zjfrNv(I;Zq5V1(Z=aHWxdBn&QEp_Rlhq|a}nJlJcjUqRCR}F5&EOD%=XspOg??~0~
zsfekI^b$v71&MUJszMuf5xu_2>s5qNop&O?7M8Ar_IkE836!G!Qg(VlOBe3R3Zi)#
zU=c=x+jf>jJXKMH$Vp3yj>Gx*f~FU5_~r$(_u<@|x17akthA=Y0`1Gwizg|AR$&H~
z=(Y&9hD~KxedT<&@+2F|P2p1zR}f>MfE`Nb}`k
zV;`K?3_nO(!c9bwB4}RX5^9m<2ZC4L#O~u}C8@!@<$Ntk5%<2ZzaTEKVrqp?3YoX&
zKS?1SS~8(zZ53$?Jg_#nA{pa2)Wv2nQlY)ts=zpsiu(grX6z$a%Y#(&ZY(E#w^GB)
z(sQfLeWcW?ICITh>GHa~IL@dQOQqOD9rCrG=aqs!iWQ`wVO$3UzHtz5WvIn3XBgd*
z*X|0KnfsmiYbj+Oz))hXfnt}|(d>C>0AMT48OJ)KSG=Zk|4-+3l1CL=Dh-bLWDTJ(
z7oAj*VN8IP4uM}A+4dc57I{vTidKbwX76GQ8T*B=h8-mGt(3`3k2uI{yZF7urcBTa
zFnfk%p+r&{XUyj^gz0~J34>=#7WO3VE?g~
zwVVewWw31N7zJ{A3ja=u=wcB;vBpC!{78VL=Ci+oXvh
z8nmsJWiKebAfr_WK-ob>*h69Mc}JKT!YLn9@%My~Ln9NCCYA1TQuZ3$PU2|Lu?(V$
z8(A5NC+(vOQlGeY?R>UNk<>R+6U&3gCO5ENuaZ((n=bU=)C9+?pi#@YdCG1zxN)ai
z!phscc5{Mtgj!*sqAbvcQuS{$2jeFS^r4p3=8+j07)NI0KCS^;O2Q{Z3Ch)*B)nZR
zwQ!yf8sALLUas=aWIJvXy0Rj$s=_NpT*%81c1M64x`bEO#ub3}i6+EHd$lVtKl#*o
z$-epV_%6YBj|{m_iAek;{)tcKf4fGQjV6l)bwmG3F~DA%M7{c1%0neZ8TQifA&Eki
z<|R2%IqFVha36aAgDXcnK7ypMtl#lm>p
z7?h_Z|GPJF3fyScX}QQ9IO5Kni9$pLUzCrlqlqM6GIkC(XH3u83#f&?I%Itz4v0_M
zFBwZtUIa|lCai@wtHL~y-*OXD)r6)xYH@N#y7&
z3_Y%Q2Nxsot^%D&#*22>7DF|2vyVlLfjV#?5EGEwetr!dMr-ADEAR
zE4IBxBxXV1J+5Z6heR$PIX<+?tT#wuJ0xnA@^MEqZuqmej!SUIGve>#w&G9E`>~em
z{(}xfO3b`2MSMBb;-l4~!T*U?eb5V52Um`a9Df+Ne2+i>6Grbs|7D=myBLAH6{{bd
z3)=blh`k6^KNRzd=Nq!AfpMjdO}rkaA=fb%b117O3Q=E$^^vL{5IT{2Aa#!%&&fs}
zww94r%tf-~&mUM<5Q`AuYwt+1PP=bkxJvLg)EVJoKf$r`v8b#m`
zM>H!#;|?BAC|i_9cF}^yX5Te9y-zMxPJB?nMs7PF@qm8(otG@lf%!W$S
z96ehulP1TL-8;1H)Iw70R#GGTdaJ4ubg+$LS9}n_y6*U~=6P!N<0*_7m^)%p&(ly^
z$vIKzfri>**sxN2?5KgA-x?^!T0mOzP=$X_C_7@h3TvlKN2SSKCA&FCKfcVp;PwrI
z{RyVPG4>0jmg}NYtly*#c0p_Bkmc-~4Ude{=f?|lTvh0p2_{i}_|fkiqYz8obAG9g
z;Mrg0srOua@&TUN^k)_9;aehif#b^Kkbd6o8x42fv$sy|MlEa5U)*!fWAJs{;@GMu`{X$?C1iZM{eBdGdP`CA_`d8grNBXg7H~Atw
zCy@GAl5uM^nTu;FwJnjF&W(*Q*XE#%i3<81`7F0Z&;g1j14Ggj(9;EeybKzi04X)Dn+38-}i1Xb&VflTx^0?0T%l3F?dz*X-Pedb>{%#F51mS
zUFp3(jxWU1_O&d~{5E+a*Iz5pdoM*KH~eYZyVXHq
zpf|=twYxXYx)~c8az$=F$&YoK7UBE_mo2ShNwM%
zYF-0Z>$4Owu9s2`ZkCq#*`=_jZIiaYu(U#ETaz7ovPSbZaM5{1yBR0DY*T~Wi<|b)
z*uI5p;{s|&Wqp@@BF_EB@%s+cX5RYRU3R&KSsO>is>PHjxbj3?j3k;lu4CWaC=u{0
zy^|N4zg!#kBgI~GQOhcY8qePfjE#N`yY3A#TAdAl^g%;mcI|!fMk5s;Te@N{^ufo((c&!>E1!oNS#u4Q
z2dGw;vCA(~Q{zUgj;~xB8ypv0dCK|3>OGaivJRJN!@ALDy{q*+Pkz;cmNS=q)I&xT
zYxtk5YY8T!B|G_BA|Ov9c73r$;R?@!b}ejO8`(t&{(>EQgibDVq=D!9;@-V~D{VVZ
zW$ZWiX4-}GNTSd4wL)}wYExVLd%0w^v{B9X$%xJR$$@nUakI~_iV;WZ+wC%mcMZut
zUxGcQ(D%0c2V$c++`4Ekl9Y0_xXH>XT3f}MZ%_r50+!~v1$`LVKM>u-nL1LhdGqEb
zx4-i)aI&Tzr-s3CYpX6f2dt^D+?Acm&r%_Fy|CBh&$j?mkA2_rGY)(5#^DEqHSqOD
zb6V#YE(Tj%DF(HvW=I@+g=jMyVk$%uvCAPyx1XAka
z6*1j#{uK6n6{+pag@gyX3t~k=Qr1M1P#rQya?GXu^f=l`
z$J=pVkp_9xUAi1%w(@g)v#d@V<^lCeLAm$~*U*7gyRyHz#7L*c*=p;IyEtath_&DD
zSDIW#yR?n6|GkZ>_#|2kdkRiY4a+W-{iGwe>sEBD_@s2{dEKsT!!b6Sk+64~rH|IS
zwu038BS&f_b)IU|7M4*w6vZ-rPp#b~bFoUf$SI@J$%sR*TA7*7N;?a=K9^Pcu*;X)
zE-UAMx5>(V-&sj#^rP$nf3eFrYVnlhieOi=D-`k>gPpIo5BZ-Q(^#?AwAMAIYFX{l
zy`hkuLo0|5FE3{C6jF+%&WnD`YK&VO=U#mNeq+V5+EuOtl^r<)6B=Xxa88T~HiRau
zt(h1zvFbz|t07A7xhT!
zPmxPPbM6XLR|RQJsH^si=;+KH6g-^9*uqe2+r_Uq`>R%o>CGS@wl7GZL~+jjpO
zQ}lb}>+rP5pB;g~pXJq@@J6z8hnFSd&2Hhw8(*WOrxQ|*;1&2J4CW(bai)Add#yKZ)svH=^*8vN-4?ZW
z*}~zy>5c3<4s*BZ_bg~}>+kNpklq9fZ>=bXUan`|z3ET&yeH!|QcBI2f*zzvY1zk@
zvYCCQ((e$9cE;eT|Nb6h{D!w}*S%rof5TGjT+CTA)5~Av_%DU5kdiXPmpA=2@0Xdv
ztuA3N2zNkJFAF8oQ(#ZXkUGL%$>8fqpY5%E3SaY_hqVE;foK4H6q(%^xzAQzq$fN4
zC`8&v{DYRT)DpwulUmC^<-&*xu?b?lG(7Jl;qpq9@w7CtioIe(wVd4LNY)Ut#x0&i
zqT!wO-5b`@G?6wg=b@sKX`=vf%8YQ1Hm)?F*V9Qk!7D2!fI&{;Uy1djC2Shw&7D3q
z9H$N>chi)IbJIpEa(i0RCzt3tY7oBZCUtxxc826`Byz4ncyZVi_miCW);wQ1X^q0f
zc5arisYN3833zX`v|ppq;+b1&rd;HWN$}I=aPpQBMH~7SVu#N(OBSOY(rb)v%NbBR
z`2P(xQ|~Ro)jt_U-fm%+(f+4`5*f;{&inz2ZE3%%#z+dSaR>kC
zL*5dA&3}h($sYu|7q4_cm%4W^@|TNd_W5h*X8lH>>+xp?ben4oVLs@VTqMxFc)0_*
z2v-791?bkFC(zCMtpmEvRjZLopj&QY|HQ3CQwYbIH@_XDCAoa*3+g}IxuCwg(<1#(|a1;8OjWT
zRH7pPNo@oho~EaZeB&!V{&{!1OefMzqV~ZyF++&{v3W~oI`*XF!L7z;X5(orp2m_V
zQeN=jHR~A)w*g9skGOzy=02g17hA;!2^H@B7I7Eja)o@s*q-wKo+Q!;k(jLHyriWt
zjFc;D{sXu2X=F4d?rn+*KPo*Id1OTO;we*41)rK~5bcAeh#Ij+Y+`7qvswbFTZbEr
zDX}St9#sRrq9o5lY0&{u-9|s~C~7s?wRUflZ$t{=1*DDg-d6s%FqFLM5DAbCY9%Kk
zEn%JcTgjV}KI9`YwuJTQ$A2$WiA{QXxrso|s@kN!ei=OAc<0Gi-xux=jImqjVUI)J
z-~ExC)qpwHRX9C|P6gb(cSg3^6JjINW4O?i&(pNlEOD0hUsWi(*4MB5n*p
z^b*(*8v@sg4GPqOQ7Ii_yoK2zc#B7vinB{BtgX2-8{?D)negP#j&q7IPtACG$qCyl
zHnZ6e^E|8BZ}CKMk_Wy;0Vem_=KHk%y<=vKjyC-|Y^a}v_jR+pC;vZ$q~E3WX-JQt
zUC!Yq*3#_9j&+I#!!Mv&jwhAFGRih0?UEDkfG>#7z*DCq&?wPQA`g99s5?wC%_%&s
z|8l1H>BX
z_d2r(vob7&_ec=d%CKy@ki@{meNLQ^$F(T($S~MJl9)g^K@3ajUSfoGL(UBeyXUxw
zT_%-sCOW|}4J*Ah;qPqv4LLb67j#S-oX8{Y$9sm^3&NT-%Yo$^_cyH4ATNBF-*fw~
zx(mt(#`+sZbvsz*OS$xpyUVKEgl0%eO5njVo1xdnaU7$7f2G>}ME?Cn@c9;6?3?By
zsahemFo2}SIESW%AI#yR5CtM#!lX(MIhu$ZKq&-yj_BqZXo4aI%*VWYF`3?=d7g!1K27ngIXOseqK)ETi+`TB+TborM!10wAS?_r`Z
zDL+1kN44(mZQbkoXxtVS%@pc7VMhElgiZGacud&cHpY#A2*M)C0|-T4uL4>AsFY~_QBYb=Z%0c
zm|*euWe-D`qInp?^xKa@7
zDDPOP*t|_r@f2G0xoOcPHmFS!ZgNhUV1z!SntifOI>h8OO^5++4`REuNn=gUXZ3H`
zv)f)}d$dU=n4I$l<1IUa4Q`VRH`R^BO&dx^K^s>a4mg`|4_hsN{1R2jpnG!lzkG
zQ=)3ElyILIVi7!UUzS3UR;j#~*@=a?0moYhYHk@5C?5}56?md{jAy46%FQO4wi+3u
zR)TnjrWm>(CGfY1e{AHxWY8IUyI+b#i`ZU>dWoA{>m`mE;ET5Xx{drdTEr!2lF`2Z
zm&3JE%#D^M+ia%%bT)Ge!&>IaUf~vP6(C53=U=@(b>hSE;e0W*=Ohz63Hh4g5ttM^
zd*azLvmpcbP6_l*y++=I90ueVr1SQxfBsfBa0G)`UoB_OMOmI~ez;WOs~x3Cz4ar7
zQV~(GH68hB*&I+z-t%tTGj}-sHm5t(@4k?pIuPk25J#mfB<;x2s2p#*(Z`MmF$76G
z!Jq5@KgQk#E~;wnAK!a!dtkgk1A>JoWMEJ-GEqrivq9z}sD%ZhMaOi9W~Wlm$;@-&
z4V)Rq0TFFfB=v-N&E7f)>6CBApj^D9qN%7^Vu)mAU~v%>`G23iW)jcm{Qke6pO4Jm
zd#&}X+q0hatY$4GEupyGSE1HU~-lY~#ReRes47|y5
zrJ`wN{;wT-=b>ENpN>~HZSc)u)FYVhA-w71N|s;3zpzyGIP(^19##((XP2mQET5Za
zsx_9b>=boEh$bC63PKZN!1S%D<`LXI+@aBw#(Pr>=Nr*~tns!bCTlPC2i_Jt*%u|S
ztu2_Kr>He`(K#A(XZENfO+z#f_(ctOx42opnn$)^tsgx+nu~Q3hFtW}eG{#8x^wc~
zLA`Muh{@ljiI(!Qj7tNC=sq!-Iyq%|$ga$bvUo;|8W{AWBr-SQ^nMa9|PnN2U|*vw)c
z^YdR;WcZ?{|TJ8-|8`=L&F3`M=PHJ5CU&R+nWCdn;DfQCPnn%%|6G7^shz(CUURoqt
zN^pLa_MBL>Z^7$nymw98v6>oRS)At6T{fYg1?Hi+q4f3#YvkmS(SWsCf>rVtF}cK7
z56XsTF2JrvB}RBlG!Mr;S1s@?#gnL3x27~2VTYTNZT8kr_054)q|!&BnulRLUn;c+
zLe|zAaIC%5KGckI0gto~1rB`MjBEl*WWvzEMBbtI{DPI$9LOe^C;%>V)HOA;;gFS
z>60^#$qpLOqmNojr9DD#-}?x52;9OG_dW+UA(~@vckAYOtFu?oc<{^3zE++VuR$
zr)Yy0N24$<+2cxciEGl^&+5gL5*7F)&S?%dgF^!Ul!JTRHNG{_4}227RdL{rB;E=f
z5q=Z+t@uTIib`{pgny9!&50E!{jt{Il_EUu#nhw&-nHb9_fd0FllD?w?3>A7C%dVz
zni3SQj*fvyAIV?^0M;J;y^%Em)=ROoQj7bPwfjT*jIz_cWnUUmnmZir2uE2y_Fh@?
zj!_bmmO6ZIXH7$Vwn2h1B9ygcJFx9vIW*(2+60s#BhWK1HEY%Y--aZmD*xA;
z7d#mkHa%5Y!QL~KczNk1)i)Al3nK1eO(x)a1`bZ$^SQSiXozRPkkmbW>d%DVeyRTcF6AjD
zN#_=JBOc-rRze9+2PK+>)Zw4gE=4)mcRPn0${XUJ{JnT>mx%*mO|*0{ZfWnc{H@o@~+zT`zxL7>_eBbfKcg6}(tLI>Jm-m$a0gK0($#Y>$2Za14BKmOIBf
zak9A$u3$h1*8^!#M5=7ouSs*0Pb1O@w8yC}plg|+o(PSF
z*p*}R_vcS4s4XDxgRGRJ74nuYje<|gIVrxN;VR-+^KqJ&65=$!8!Gy(PEaPzvtP95
z7`4xLCREJd3yUxzz}2adDdB(_me9v;@W0TJp8ey!tpxy#@dO8XE-P3l{#HBIupdi
zGR-8Dw(Ak%0c3INk2$}(3SpN)tZg6A*R$yQWYv^kUznS5kE=bMJL+(2Znk?j=AUL7b-=$pCW6p%hBCC@o3hAJwwEI
z^LUz{Q76WJ)!G>IS-It}=I_nyYKc4?ir$W-tI+g9ct4IjI}aQk~uKlH`09j(w2LI>An5=JHjoO(5RsJnqyZU
zT&YzwD#Y44Zj?=YPQ^jC3ys02?MLn7t6STC{5irRPFAXQ;ke{f)7RGeSAU^ZG|6<@
zL^)kf1@`u%XW%RD0eY8w+P3+B2QB62OB4)8>ki3x37mD8#f!6e{|N6NS-45LwYjXs
z?wil&ewQ0l5R0{$*UZXUJic^fF6aX!|Jvdh|*^1#xE2ffE0Cc_e!E<2f4lxu#!Dt=va7tOtWb#g`-brUm1A#LUtBR)<1y
zpi(+FsaDIe4&>_ul3vl-tJEQ{gC1k%HQWIyxGj~s>;_Kkh8`Pi{dz)_f-bv->&90%
z?wR^=cn|-XYbxq@M{KvD#2MVBRJoOt7q(Si5j;NskN_L;WPoC-@U_gXF&rew29S16i};{K6B6)@{YuerSoC-z|$v>PC%%T*qJK
z`o3@F@V=m1R_Z|HA-U#4e5fuP+Ou66M7H2zr7J{=8~Y7PwrK^lOqHT|a<^+~DC7g2
ztjQ_-h+p~ZdtIPh&N>>sGT9Nl<#XgWjNUofv;%V;eA1P@akiBPHX;$eQEU3EB`jd@
zALHS|c;GgXn|1PgGjDO>u2xK{S50(iflZnj(V<$5&DQKX(7Ad8;y>W4Sks^wTa;tg
zAX*A(l#V;CnbE-6RW+3^j1pwj+&tUI2Q=p34VoDtp_vD=1~(b~ejy6myw|0ANfj0V
zO~AH!w(V{f2L}4px#Ie3oHiF)s=&u`hsNBTtrRrpLPF{3^PvN%VlK}>8^i(jj_9J4QK(3i7fpa19c175g0<&CM|O?`UWm(#|sqewzZ
z;lQq*kc3^Db0o{4vQ1MO@9uL*r7b;!zAWCnY8kvBVXS4x-T4>)&$-rB=2*UUOVW`B
z%C#9I+JRp?W@3@5>A^d{COc@P@+~17Hhsd+qN?#zdS1wx$|sR*CMU^hjGC(LUm|n$
z=VU`lp`8TG5H(#YvAIRz5=P2I|1K5UFB5~hWZJ*v<7U}zIlBujmx=uvjAG|3zSOK~
z7!*3T+U^&TdwrJ};^wt~(eRY-X2}l6l@eO(Vt-oSz*flhwSRd?f|7;Q*Gsg2c|>|M
z;c1HWG;0^i%c%U~5|>Kok>Yc_dI_su==spBDY_KCe8ii
zp9>tZsBKXACH*mqPc-EgbvE5;{~5RB)`r__%n`Xwh_T{Qc~m0T;NSGywL31AK@imq
zqfuHA9|9FiI^ssU0+62Y!ziTzet^)VX}DXlGm>}Jg>XA^^9OZL8v9juy7+Y`HxU-j
zjVh7v(u*A}V=)T?#_vI~twoJBEr^P)2hcvD$|4SF@c-T{=BR?ijQRkjg`Tg0QvaQs
zvvGW0zBzB^*u&7KJUTaNb4k|VCo7eHj{+Atr6}(LB=C2GXf`zJD$DDYbCaaGv}hVa
zLMKXdnPYj}?Gg;sj*)ZW%^MsK)?SxCAPC~02pcrO<>Z+Yfk$(bsw`Wkh_`0-udt6#
z_-@6#70){+nNOP$6Qu25(3jp_G_iVjaYSy8CG)`Cq*1c=VeS75=OY`0j
zEob*GOBYvOgXZ8^XVZJvIyIK$&&ErwEyli|yn#J`h&7vx+Nc*#(s%E3|H>TG5UHlE
z!cE!SB&ErP--##Sn`_1IT*c0hn1`5kzZ=A~b-ZioBb@!1s8OmaRAcxPj=x$e{NfYV
z?8*ncA~Q}Hu+Paa>NHF|F%fI`h3vUWnU$`k4{>W+e#xzHOyHe`CL0s8@l=NPTvmRj~iax&jhWkXW_}sdI)B_9&AM
ze9ro|`SWti#Oj$^ODaco2TrXqMy2cs%qM=FJ^+q
zH)Z?ZEw_C6{?OzG-UXneKF?or9gfw(AV~`@}uG<15N@V{<{D|Fp2}@(ycV&i7lOr5&3K
z`Suvnl4=fRdTY3C=?NK)FN*4rBK*2+iV$&1iPs8~bk9hqrnUZIE9p6ObT_+~L&wPl
z4Jv{oH$??ODq8~jz{lL5VHMZ;<
z-H@e9dNR!3bKK&I7a`R>J?hNZbK}oXx@7*2pg8NM29W09<==jVCLZY*j$2GQVsl3a
z^rWdyj6Xl|BIQLin6`&E{Ayr1#-4jK;QqAP>wRg=Mw9%r{JWhd;(2m(9?CHmAF48L
zUU_saBJ?C<&E)yt37JAX{**gKzjJg~n)KwL1iwV-f$hA2-km
zK@-=C8wb)@=VW5{qr9f(^PGIkx*S*6Qa@)MG|aBq`**`@
zW25XWlVG#?9Zdc&itGADB!bRfNo$MR)04jB?7Bw-kEji;C6})j#Y0behcKuo{X*rH
z*f|$&xFNdetmf{ulq_vhj{4cE2&<@y@EO->Y
zQ?Af=vKE3pK*_*8%Tj;EtdsPe`Akq^Ms<1NV&btot3)4
z9hD00s6Q|?Y520#;NzhQgrQ;35h*@IP#LaXSCO3=^<{P``tm>rWRK&9(l=i}3b);l
zyIH9WXU=9s{wsg01cL#QVtcFcfzO5V%Ek<8WT4na_Zzat))d{jG
zVo@N5rw%^O*1GLhjB|w{Hjnyw*@b@g@8GijZFZP7LbAPT`0hNv>&$|Q=CN??nA8iE
zfg^SUf^SToaV<-2%JI7+uk(japjMH68ybeNKJe!@J+r2cX6|We=2jS}#>$m;OVi+v
zTTk25M%;rjurT31d>ed)H$GY7ZSM_gFO}_GfwDmzca!Z=!((iNZ}cgj-xs?Gx9l-}
z+c?nKw8HPU+@e4WMOl~33(pF8VbqqW$a}D!$(`;FGhBM^=4D^Y7hHJSUOYnWS=?t-
zho_D^vfHjsh^<|g`Xr);53LDH=x-@Efpg}iF~A&cO1zYQAAU9Z@avg7KK#mx=!0LY
zKe&6ZAJhxNul`2}6IflRVgip-JyeTWOf_such;5TUW;&zC?%C5t-DL6ndVEDnU=Vy
zF7OI1+>ipI;ken7=z{G$(FOg%oMVhKyk}(5${shhdMZ6c8(u&AIIY~a+xry;W?g3b
zy|tc8T;YM0cEa_pR?qB163zHTI1NgIk(qI@XgnxF-qF)E_kC$cPAiW!+IRIc{K5<+
zw$_I)2G1{VYTbE9zQdo(G1^VwRpqXRRD<^YXf94L^BIY8#p}4Zj%Z$aqoO66&p4ET
zc0RQ)#-_X;Vv_DSOR-ZFX;rHgMR-R{w5{yBX)7q>`-r}wXxeb*_Q#dfGADdbj^T9?
zIQ2&=Ib+RkJGG)QdGHNNC3~6(`{|FN0v#Jac+f52_eH)8DZd-1ZE
z^P!5Z3xZ`cf+v?z-tpfl%|&CRvD~a*cTa25G-qMk#qVRG)&C;-xN6(~jW3`5{p595
zDp}57lMw4-7UkVv$?lnbU;1L<%VmUxyeX%ZVVLq)%tM&kLo)n0=pusFO8WnVw=uTq
zq?zxzydJ@Jo7wC}<>D6PmR1!mXS3d%%f2^TaYJ{TFPSc3@WoXGhlf@*jbp@_>E;+4
zqP@doUTfQf1-L;co+fJh&WNL!ok7%E6Rjb5?IOy_@Yu`CY$uE71$gs`{1Sn%vuvf9Aw!~eL&ryC4vch6b!yFxM?oR?%x0bO@P
zuqw6wyNfAWls~-x^4CK!uUcizn;5+xvMRBv$8}hmuI;=_nj-IBZ?Y(F<9y%t;Fr5?
zh_K@MS8t3HBQBLOq0BQ^u+ID$ZqzLF!g>wotR}vMqH(ph?Y>kFdn3dFO)2KeO;ju9
zHK^R;cYTGW)pN3U6jtxT-sx#;+~hTiH~H2T=+X5LNsIaq%fU?v@a9(=!YeH~#-_E`
z?s^inN~01wZ;!oVM^|Wif0&N|I%~z>+cwbReyWAX@K%}X>N!Lao$wdq9yx~
z`qq8EFSWd+H&=ghZ-4X0q(N8z*p|hRm_zQN=%+6IDi>BOh!9xcx&gW>TukmOhBrA_
zZ+ikl%PsKaS@u}#gsC|v-=1nspU+9Q)Y>j?!qgEduS{Kz^VK|HS`_9X7S)
zhyHm@mLORPcoK(rSRWQey<$L{UmIp@^@P9n2UVzV1$(nRn?_-H8sRMABI!N!-OC?`
zrP=V*&+DuoTDYOLqSa5~%1ctl=FPD8q`~hs7Z7f(cB*(|Pmt@=Ag)5O+92Paq=-{F
z4X{ziX}{G|9~HA!R6u&XR&f^=fZXbbfBg>>ntCxjt>7eUyZ)djQ3=mWMrBVLuoXTD
zc=G{i1P2z-d&)z+iQ3JgYfvwiXFpj*5cVFTKIo6qdZKkT!QaW<5NXV2(3(J83R>a}{Yv)jyW|^x6vB=!6RYJnqV!2>TH?tBZ6+eEbfr
z+pvUBz~y)nDF!69T5lf@4mM?gSmZBjEvx)MH$s8E0N#1a9^N9gf8hP?V7n<&H|s`3
zDs{1=mAY`F&|3D?KWXO59s~EF?6~vx)YIT_`eK8ucp7wj$XX-DHq7*3|&ur2-Ex>C%0iVB|2
zxQ#M#05rum{he`^G9G*)2&hXR^4^<~_
z{t7pXqj5zOCGDy6N6*y5fFuF-2L5b?$cBp&`NvI}Vb5*eFCS-*3a+
z!}4**N102_vihF%7~5-V*%{qH+|~~yTbY}(>E;4Upb{FjGTng3`K<$n@?%fSuxspI
zMKe=bODCasswW(d$kiM787Lx;-oD<*C}Wgv&K$p8_hR*ArI9`v&16v|owy?n5wJO2
zVR-f{;>4dmK{gEKPSBmzA6x`p1i^;L$!zm3m*CWM9Tc_1!s}K<^LQ$a=l|eWS3iT8
zv&6%fTUJ;GSAo8MILgF!zL*bSlLEaTU;JaXLy&a~Ys0oDR$%{)s4jTK?|KMY1$jVx
zKf?+`uud)Qy=)!R?kic$w|#JjJ3{N5sM0+s#?dPbEQVpoa60ijT^cE#A1o%QZ10nnHro4P)-
z0vf;FHlOcn-+Gu^9h+aC4{Z2VtWor{CTH@GPleun-h*6)U!ELxm!5^L79$OFH1JB8I)9>3=NiU#$O2ky!UCHiHZ_kPhoR_p}
z4W7~><8t%lR?Ex$RAaIozD_mm+^NC1iTrsosQP1T`WdzB$8$Qp6e+NA{7>M$JSX9|
z*vMB1UJ}C+#GG^`oveN5_4g2^kByhrNygU_gIIkHr=^f@!qb8(FrF*~v{^fPI(I6_<%5sKZGKy6lGI5=o+hi19>)zA_jQK@HDr>`h&YoX(oc&dG?_tH1c{8P#`BpCb=k<+fryZcO}h_@Nd}
zJ+-E3a|@!qYlW9Nu_juclVnd0(SSS9{Peq6HC(>KE`E(Wp|r{B;Mg1s=&|Z$ZhHx0
zQRwYLRi(x>+LAwLv>+be&AHOkpnrPX7`JXWH>*ICcH3z8%c>+9)X77Sf+Chf19?;8
z^SO4@r76pc&O)-=Zg!=mbNQzI#<-Ac-0Ovd>)?xb2YGVQG;{)f)5+)_J~<}|=bmJ(
z2JNekluuSqixlNJ3nlsFO3dTd)AsUNBN+!`a`G#tb4{H(qSe
zs-SLoXIkuw(DXe1$e@TepucvcSuM$G_r77YWL6f=t^J43P|N6RvdK<
zx9rH(o*T}cwzCsKa|dKcz5Sa(Z_8$1!Wu2>{f02+gKx4RSGgxmBJ3nQ=S`4Xnb7_f
ze^9NG-rMqMrN6IE+#D+=q-ncCIAtAqk)gj9>92!Rw)D4bF`q4*a5mJ#I2odJyam3H
z+)9hn{H@#1vc_EF&PqEAX$7-yhK#c0ayw))nGSeaQ~JlFZ@4Lv?RI3Pk({R7lwagf
z@TQ*|sJ+r!l&qP(G_~a6n#o6DoI~-0WS=ax!$ellbP`h1Noe)IK2m##
z8v9O5lt-PgaP`Bx$RDSwwkKVkAg<`ZIUsvtg}p;oakfK-QtdveEuAa<5YDJ!>*}Dec8P~vijIbim#!%W^Y-ZJ*4LUT-(VT<%XC*w+bOa!7%;p^L9jwiznM?B$em#un{gN41jQ<%q8g37^<{
z(jwrcZEW@UgP^E49}N150BjA#v@)v#WbI17efj0X&xoZ<;Wq`982tqt?I{r0hT
ziSu`LaOB$$
zu~kpp3FAf>rx{}#13z`2dH9=A=8UPMoZ`$jl`#c$Jg8IUqvIJcpGl(mvw?(D`(0FE&%<27+z}1r-a6a8~j1fljt-Hal=~
zZVbGl@Q%2&q5~7md3J_7t&No%aijWB2mCcAV9jy?;)7k>C{w9rc@dj&q8%*d+>Yt;+kxS#UN-&gxu
z@lkrCC-GVX{CMHnUH2L*J3mhs)Wx|~Ws&k7W~qc`Z0&1z%-Z{M*7nI+%W^{UM*AFb!tD0TltUx&;|-Fs!LI;%!)0qNEj_vo
z0(o8HXof4>B*|Rc2RDhP!RlxrbcTM%d3r`G9E=CYP-_2DH^xCLaPke8?I!Ft0iH;!
zB~!Mh&T28q!2|k}hY_Nk&}ov9yj31)EFj#-T1gUZ>$XUn-&a~y{bNN@Bwwp}B?P~a
z$Gif~<(DuMT-j`&F97lc@b2w|zs-QX
zQq%;=b45rLut#bC%R(+-DwP`-2}@}O`?~#A^e?&Gz}`%+q9>7VUzdNeU=!v^g8$Wp|32L
z62lH3PLQY9K*kn$Qp^=Nl5&(KUa!=uQbKl+mT^FK;!XFOI<0EaVDipVQ>ohlneaAv
zEsjj93^O`U-p~KWE3>heEaXza75C*lXkAKUkSqL|M&24-r-nYw@9=1>W_UoSCmOqq
zgcMUh(+bPp$jOF|7&cz)G?f85w#g!I5O`&NFxKgpxqhu^mls2}n;C{gO{kt7i?t3FZy(e5()v}q|HZ{yp
z{L|yZ2!q)iE2q*NFM5P9yZ*7`?xN_swEptk9Ut#6GNX05J90vzU~i+`erV!~y-Jtb
zAfM>aL1$D4kBci0!4sMSp2j&?Ijd6Z#^+`n0$y{Plxr~~PwE0fgeutT?Yu)!k^eKo
zoDe;rscQ4E!cnsBL0w5psQcP?o)F|gyt4yElhJ||>QBboUAgD>?|0x540?H%c&#-)
z{`{e}hlnDqtkdn7&wX{QY0VFJi{b&hM0k^xceGI*x=&gjbi>|ASJDtlvk!ju$s*JX
zJ&Q85mS27B%rW-e@#Ka>A%Fn?NDEigoj>FoFPw?7L#L=2704XM=9p|-OCF{gtUDa3
z48r{Q4bO;*1}^*Lc$>tdL@K!RQy{rg=>CLY_lM99o-j`r-VnNBisx8hQ}!{U<+R7p
z+^}fZG0snHqioQ>V9=UE5J7_|@DDCi@q7a|%d##m{s@;%$jaZiiphPi*4lot)o1txEN(cYFqU
z$0rQq)88$O@PqFw#l*G#ioQGQDGNnDCu%|~fmVbU|MiM#v9|oWZo?_Xfx7BLPK#KG
zGwF3VZr+tLHg;X1e!IYdZS0WINF+es(h_>g5(f{HbibT`#wo3O<~^5k47GGu(r=*U
z0%*#j(X5@#8n*Lp&m~KUDtMs54!BczK$+yU#0~zO6P+DuvBfPD*DL$cD9U%_hHA!|
zgTy~|4$!JrKhB`o1=d?-@R*VUv$*-}fO~mWCh_4;NVXS^WO-{qS!w?;^@A_bw?22f
zgXN%N>mRhw$355?T}fx?{&nPQ=cym5wUEpE$#>SN;}%@!bUUK`#z}nuu7zSBA1!X)
z2gvna$Wgrv@^lUlnVP~(SwNWm<`Cg2=n)^^Mfbzdu_{&6o*jTMtb|9{GCCt
ztJb;Q_CImDlJyUQw*eoloXlFLG;Maf)24E|Pu7PbB^)WAvJ~F5$E{Vhc_C$XGDuO2
zLB(Gm0&L-N3L@P8P!Eh&Vwab89oP=l?{8(a=&H*5P32aUMD~9adM?mqSHLSX`<|)N
z`GMmPZRZ9*il}aoOt9}!DxF**qewSBkLV&5vQ0+zy;-U2kMCjavTt>|ScU8oXq-;K
zDjd|Vz$#JrB;UkmGKpB|G*}5b-?6w_gn)M>|H9t=tY^BV)RAA*9Dd1C+yuVk46H|k
zy2E$awMrwG^oVb7c+V(<-WRQ7vStbK!|L=)`Y&s=Q;PQlUIUTm^{1JY3rWRjhQFBY
z>VgeqzVLwdtb-d|wc9b&q;0TpgAWBN_dB!=(RlL1lij-JkW#rISo>zjK;V5Z&c9f1
zgMKNJxRT7vY`mL)!FbQG8(ol{R1~#y@u=aQ%e3==p0$M~o=U1%Ya_1z5Ta~xuIlz)
zx27x-Ez@^%6~bt_cm4empI;W~%Cm4M-v6>#zB>tC8U5AP=sf%j-_>DdW3hl==7wYuCt7kwSX^l?is(yRc{&?)i66Vudpd8&RbvugG>;!Vp
z9;keZX%5j){lR$U1g=Pu+}f^0RMYIrFDR6s53QOX58Ubr37xEo7bY|f=^}q_&UQsu
zz0(p_zXt!e;D28XwSU`M|9%a_DCM_W1#oghq;h&J(R##nxftffLi;7%hIUT+nlD^j
z$I^ES7c;!+HQ(soYnMsscH!b0mc9k$z1XV!Mz_hEUMQRoX6YXZ=QDt{5k}qmc7+%A
zdBQTbSLhGI)>c|andfPB^^EYg^ZeNnI86o+FHJkO{mIt)=RXe#0v0HYXLG6%{ZCfa
z1RG48I75Q*RoVP?YyEh4eBIrnw0pW7Ey-G;<)ib**iI-+I{!62>2$(W={L&z>w6z6
zOpSM6+Fvx5cGMkXQFc$*SD)3U9xeiO(1;V>cAY2!ucONoPJBMXjr<{_(K^MpB-FPj
z%mc1dH(ogzzl{+tA(&H|;^5he+N0YdOs-lAoLUri7s@B6<5?`;?DInX0wGzhm`vEX`fM>4J4l$vz@Ic;u7?;7Q(q74mSHBf)C
z$37K!SZVe?M~RAR+~emeHe3b|BZD560{n(dhlm>RHHrO)NsjK(6~yxeUCBtX=Q~e=
zMh3Gr8?}wC+3owV6Fl^eFd32!zHU?o8{_zrwJv^C`mruq;k;lJSo0H@!3O3@(
z0yg6IEx1=yY%;9*DceIb720KdyTK(x_Mr}U7`$8}c2*ThUul#=Bnn#hQCQ*;M6#gK
zV&7>^0xx%ONYt7-dY2Wf@TT3nIkN5AV7Nbu+0!Sol0$GR!rrj?NOH&{c+&jET7+L$
z{v*YF>wl(du5~wDN+}!9a%s`YFCCA2waNngE!`BUE>1=gL8B7(^q_b4{EibE7=^-F#%Z{}j}TG_N9D#K9W
zh)&4x#3|bmKcn5yclQlc5@m!>*1r^Sq6QqWAub-4CKgEU*0vZnC1$!O+HOcUHN>yjQ58JsQ#g-g_V3!V<$g)V_Nsun5U>u=qEpLL379B~`!xR*Okw
zwbZQ1)Dd*LaS|VDN8}6LC+&Api!(YQd2P05TBYt2+g)ABXg<>&k;fU^agH*Ay1#t_p0>YK7mgWraIIeW+bPpJLopv;@3yS1*!D~Ug6x`zqeQtyu
znq>9K=YGXq-o2AEJ2?`^A5kq&-QK&-g0WiKK2YpwK`&A?UidQ@{7lF3q1rdA2lj7t
z*^RwykBNF4cYd{O1w%rjCVYDLD5ETFKg%&gYSQ-9Z%nE)yBm_gW_emB*WYU=OzT=z
zyACG~v1ezWTJ6uUT9w&*hn5?(W8g1DI!##{OkB^5o)EFPfg|}jo;J|ale-A-i5uOJ
z;948c#i3IVo)U;hU`Jj}48=y2k_7Sk@GKg#ru
zlHm)tW8fMKG?VjOsdi56aiE2bKKwN?C{fF<>v6Jf``|a4l{RmxJ<(go+e`EzgNZU+
z|HlK03c<-)8(KI-vjrs1pN(*hf#t1vD?y*UmNVk4C!_YJ_|hl(((U?u%i2=WYEf#Q
zUmFoJ7!=uW!AnI7=tJ8SKQV6L>YpJ?A#F2mm!(F-|E-UV~36P
z`1Nj@UElh9oaNm&@L{jo!R=J)|s6x-f`ae
z@05b+UCN{LAPvhmMQ_bt=T<>;^7L*;+6C(j8z-OfGAB$fhB3oV>Ad~~
z`Wg;wSSgQ$7_pBei*9akD!3)zsdymFSX>C6@Q!#|km0tnZMMS-DgceRG!y2l4N~5B
z4@l#KhZ_M0k6$RrreBq8%uw$kdCd|NX5@HFXvL(laW8dIVe
zQBR}%jZtRyrhJ-eDu>3x!#{h|jjZ0MTJEnm%82$|_toodi>cM~!4G^1IJ(TaGORkK
zvV=xe>J1lQ(%KY;FazCkfsYP&Y0;Cz7QnxIo8Ao{;^3F%86H?-dvqlVg9}zFVV*EU
zyzpKm+^E5oXY8`CP=PWj%hM
z>X~E0?A^)4-*@jUz~6`OypF$>ze5kDZT9a=@VEE&GW`AEb{76Vbz2L23Z%m)^CBvb
z-xPv(OREg0cl;XYy-TZniQc=0qts>Gl0Hf@__n7y-NKs44T*!BE+uY;mK@3a*I*1k
zODqaOZya@FHPtOfzn`({y_C86I_qEaC_uYX>L4t@2uWUq-N1Vq|B@-LrB{22v#$?i
zqhi0tO4YzV{qncik(RU%WIGbAs|~ZC%qMwqNq?4mdlSpOJptVOS)vRif!Z?-*ws_$Vm+y8MD;zszyKNN>4q2%X*B#Aw7p^%;
zQoZ$OSxc1{SWE5WFgx|}fNPDm06XsVx^g=Qb`+Afw=SYZ9D~>SwHMwQ2CwD`z&l3pa2KzB=Q+1Z(bhAlqcH9|!HX6qq(hF$k4{G$
zGb$WKGRPU*SSxQ9A_X?Eoda*Kf+j$Ne0ZG-HG4GUl9u>tezs4|xj(R)GrwXrZyy6}
zImCKWhn@s@{-{?UJrI;{07guKG4kZQcTT0cG{YXO!KVl=!PI;%Oz7~AdF@XOVoeo;s074^KX+q{AOjhI`SZlh
z$LQ>68L-46&MO)QoEfN{AJ4_(4o|nMWq?biQr~*MYQAymj%5KY#Y;E!K)Ifv2{07qHR3UUA^+71bwRf--m>((h53AU32xtLWqt9?5X%*-_y+7_RR%8&FzsM4
zYlee*ZKipP50Sx6UQpw%C;N#LxG&3Q5QTSiCD+uqEVvg?03+T`1Jqkns^01uw4|_V
z9^SAr*xl!6U&jkXiG=`2^8(HvjTct;;wD6O>udYV+m8Cp$GvC-Y@lU9r`s)AZ)FX-
zxvFMWdtJL_ne==C&srhE^QQRvpnVt>6);hh>prvk&BV^b-EQlbo=Ws@XebqRCKENBdgy0W>W&;?UBMwRqvR=si@znC2bOk
zT6-NdsEs5(Y4t=lYW-L@j!Au0kSIN|W&gcueI1+>o_3qQw`TKaB46q($r_ohTRO
z43+DTgj)4}gY)+)z2}4GKxim=TCYRG%kXrncik;$^p}nrr@buxHrxImbYC4w!0}#$N@-HM|#t0-ehU^
zfqUF&aR8ND)vvMZXDR+O)K-&_ZmyHhjbsP@}_xw^}Wi{YC@0fbz{}B*3^4bGhbn;&4bgB
z8tzSP^rqV9u~g+lvyf`=rnY%gx4+C%GsCtcmE##?F527Px!$rvKBQC`OAYX*HoxR8
z`=>ET4dAj?^3Y8P_ogamv(%c0$L;lT!HfqUWoNd;u{QW!Z+m9j;3IxU5x!mF|E-I~
z6Ikf#zsraB#LKKs_O@r17iKf^o+5o(;M(di0}nkQtb0k@mz~~m7dWi7{(~0j^xpWv
zMJ83M`)7zi5>(5M^M}||^#4GvEPWHoAy<~3THNQqVNZ1jZh7WD+sDn}Y(ZTsw7q`dE54>Qa(Y&aBV2&>wZm{A2?
z#bKktG+D!@IV-5T4QcoW3`V`Pw@72xHQ+(-<
zbd@6=8hWfQk}#4+HCY;P3AinWJ@nwO%I%~nx4byaFv=WUBNpQJ47~oDlO)^et6NU@
zBox8&tXmgRjHm*owu!bQ?pQmtJ4RD4LfY>@GOtMMXHeC;_69@uVD%KcrQ8taVSFsK
zb91Yj)|fSx4){=&eD`i_xC{L)i_2csG}N4L?%?7aInyHrJ6u*YrCt#06S@4?%VIn$!c!LzFc@?Ad*-B62v+lk0NK7Go?#Y2>F(R(FX
zUw&}2LF=e$%7=b)ew~{e1Mg;rfzULQJx+ek28zpDWRK#>Ge9h8;k4_b5xb!x8oM`a
z=Cwlh07MWmEYIG{N(r4ZL@1(CvQF8@tW$=mtF|hU3#H@LeD4KiR%rZyUhbfhcDss>8vZOGx$otHYn!a#4(0V#
z-z)p3Skx~27#Y<}xA;gYb*tr6`woj*tJ)!pP{sW=kBfV25Fa;h9`23nq_)YC3XVj6
zP!;z!YU`}!E3T<{T`AgxvMhC;d~w0|sw1oDs~r8t-849yIyu#)g$F2{8Mn1Sv&Lr)
z7yqdz(q{=kcc62tt@so!`h#qcdcLdK(`-HaiS{OH{geRn^-wh~T+eTKWOz1biL4<}cb@O?EdPE*QY2?zZDYaJ@!I@O^erBva{<-_l-o8o
zUKqx?&EQ$P1P{0r+zr$B>ajh8;#C26Si1yXr)OWY2F0tT-MSEYQ+!{w@>{*`RsLK>
zS3D2M-n{5-H*rt+6?|V6@$o_qT1Q`JQY(fLT*Ug@oxk1tQiqZCh|uTN?F^&7dkATBeQ*M)C;!iujI9l+COCEh=!S$jhHic6`^uIQ@6
z7go*CFC*qc5axWI>A^;`Y2#JuAyNMAGp%It9xYZoaK}Tq0
zrFRJ;o~bOYrDX-vq|)*zn*>X0QzXH*J%O3xy{*I->oD6Bys6^Wd9LDz^SmxHXdHcs
zyL%YV)zWkP0Pf|ATR$LO?M<(KqT<#oct;*R<*$AsewCc7xOEuX#_XNJyO++&f5y^x
zDXdgJUe4XA_~8}YrUY57_!ifB7+4g*#myUp_@vd#MR_E9|u4}otlQ|=O?fd>|V)v?e!NXlx_35Ec
z6XP9iG}o)<%%}HT(6Wo>rxo79lNRUxTZeGU*^Bua58TYw9_}O@q*dUDS;Hz)Ou)**
z=};3+xp6|!=)$i~pzma39k;-V*^PWszSAb1DzU!*huUkiW)&hYG`Q%k+UgeCdgE~F
zMEWOJms_`2TYCyz%}RytlTWGdHn-sEjeASQr-8;*+vrQyD(yU#g1uEQcRM)vy31Nc
z+|`S#bUUhPgzOca^FV`UV2sY#AoH`+I+s@EuB$fS(#Sd9RVm@lNbAmOdqsCV?-oXK
z71z6=wKDoY=p!&&At;POXM@>oKYapg8Twg5_JbYA7>SWw?jGxjy!33mP~}~Bk7C_jg7v*FwjCaA
z>H~n?%h6^lq%TA_AiLAW&=*^dbDlO=Rn|?kDjV};O}IyEhEWa$%5b+NT7!A(!VNKM
z6W&v}9MMUDPEZ|g&{>HFsIjhN+H9QLH0wb_8gd#S~GKewYJb8V@+72V!fM<^jkoSJCP?z%-R%ZCEmO`c32sG8Jmy7Ou?|3O
z^g<24Q0U%^(L@_U)*HUTsry&=PEVvOSDDRonz}lJrol3^X;Z^p8grc49l**)lENSk
zBwDQ;*MpNV-gb37;SvlQ-H5K`PRvJq70xXy+(Nw!nudw^y22XmuoJaqR2^SzG;dvP
z(22z;TC5>EsCLy~Itr0Xg;9v6!9%;zgWTC$2x=RmdFR3=d$g_;|FmXTPks
zwd%tk)B@?b>-
zV`PTgH134ogxzxBHsQ2Z4cvbF7I2&Amvp(2qZB%~x^2P==%0UEo}$w_IYa=PiDjtHl977VQxksab<}+pvxl8E0mu+UNI#fOdw@#Pjt+rHSm#
zW}cBp8}&;Fiz3?fD6c2k5AiVg64|cDjom}^626`=Kn_*K7HXtnIYUG&vgq!bl@i{xOFlx|h8u%uuXA~A3Crf}J=+D^nA
zzDrzAc>61wy^0B~;cf5qJ^8-4c*jAqASSEgXD`jT`26`lpPPGT-sxBC-vEuLH7i7b
z8r+d6On6s>_Z@XgR6-3Zfv>x5Vy^PP-RVDoRtVWmxL*^$-zjs)zd`RWi32+0m6|
zx6AeTu216ZFIT5RK3?-MhxxwHTJrprca!;d|c*s;B8;1xnsa>
zh4~=I-JZ<1u8z6lgYNdb(%Un*b@fF^$5>kv7Gw=>&3^yu){={mt>Km;N7-`
zY3;`Kts?{e4qVnoDC3qy@fBU^JUGwTZ4a=t`gi0=!)cP&+HLFkjliVX_6J%=*1tt%
z;{CBVK3LIZ;pZxSrEGw>Xc?tW0>n%}#7V;ou^MS3|7ML=1l?C#__iR}S|P1%32-`y
z)ut$tY71`+FsV;STl50vBiK7n#ZsS!QB8}|r0=Xx#oj(iDJc@P
z`)ZP)8H>@rXE9Ir*Ayf532F7Im=AAFHda#%)l~nq^quv|SCf=dHl3i|SCa&-8qgL^
z!93kx(+H_gNE-==Hea9Km-;k$4T|VHPvP4JVLc(O&4BqB
z3`1XA^B1;TXQYB>B#yqt!eyMn
z*oyHtIB72z)SyUnt@>)QqH`?HKDoRu_RL($0Y2rHl!oVXG*?
zKJ^TJ6J!Ka5z$TiWJHGH_{I#6HTrl0PBFjhVtWjmBT`Y<@%LTV%v`ExOAMuX`J>as
zqfj0ye_*3j9uR%4M5@$2^jeh8Vy`*SKAV`4N}Ni?PfJ0E-;|>bxM#>XGc`4TZ}SuI
z4EN2{R4@D!`Fo?(u*tsY`%-ft*CDl6>bdmfj_1N5jmo>{=VR{kr=OqnLir038SiDtUi@_$
zdHoTBjqsQLv9Rsk<$-we
z{C#2D-Q-pIf4=
zcl+VQU)SABySQVgitjFbZb=7pdD_F}QPtrtMcY$ufBsH|`%|vx!ThxyhEaJHe^29E
zOMbk~MqvJ3#=Bi?X)TF4k8_KBk}`|&2l{Q`rmDj+V{lcem~oUzE9XJyepKFm=R~L9ah$bO9S^dRvD}bDPuBWB
z7S3-M`?B*V-xrz-)Hw$;+UUvy6}NmMTxf~tfGbic?K%E{#eP&iTKmc+XqG3;11#soV&tF{L!7P4h)Xl%y3ilo
zV403E;s@Ty{U%p41m(N!!*6JI{3(${O^LhG9BrLP9O;HDT$FsiIm$5Kx4#RNQPLFq
z9%;%xtJ(@rojXjK@Ox4S-8(6MBe%lpBvTTXt?ivD(Qer!QEuH7Iee2d7Cv@24Y~$}
z_eieTHV<V69l$S}rXTac%kH0*4~{U*
z=SFB$p%oL`B26Br27g|*7`Q5LZqE1<4xZ^9_t0LWwQ_lEI&ouGx8=#wpsfO|bon^#
z+vIUnE?F#9RwVAvvWCuw%ZPcQqj#fNBCcGU`qr|~_u$_cW;?Rj0cPa^k(P33!bKhalm?`1j`9>vY4@k-ZT2G;+-07;=TF&-l%)~yAad8ABFnNLN$uk)
z^xW~Mq#|W{Z%^S_uRo<6Df$pk;fJmMlmXfHBTogv`)P|m#ex(%WftA`r!*jiPMIk`
z`BU`kEZKPfQ5-?TI+VZVKa(u$eC3<{DFf`j@*aOmIa26sd-9+Dl+^WNUxRP@Q)D^5
z@%+P|vKJ}T*RwzPQ}nsikFz(#ex$AiJZ_i=NCU<90l9$MXnb$#N^79BCFpM>aA*)_
zT?bxOjxT>6$~Tw?z(pT;4F1$|q<&bB8q{L0@(uPQM}`4D-;t((m}c21o42TN%D1%c
z>c-_awx84#HNI0fQ+O(F+*UV5cskg)qu>w1(}#`Qus4;$^KN?PgSyg<;`95B+hV;;
zWFN6aQDXsDY*YxjglD(-e4ud?N~Z|v`{>y%J{QrmZJv;RsPS#2i_Zrd-~QMrq<+x2
z1*wt3b1~&M_7|Ra3nj(p4~3E%A^m-N=A(T1@oW^IcMIvkLi&4+xp$ryo(?vy|5zM#
zapMM*QwymdAXOaCfyP{Ou`w{b39uUM%@y}7y>T(c>mdCWo{YA-TJfnVyY8$nEvw+~
zzBDUvoKOQ7la{3^Yzp$F+cZT@0u0Uj8Z!xoy?rIznfRg*bGg?*AI$e`T!YdnzVr;F
z`<{&%ghj(^saNjR&@S|)^O+yJ#oTFBOQf&e49x-ma~hS56iYTyNwxT#wi+!(`O^P_
z-uRx2-y%IUU;0W&@P#&w=^vjJpJLubIbR*cZ+-lCG1dJRY6t`uFRQeNd4__49Jgo4
zxWCGC<+Ktkj9*UMe_=mCUktxB+Jv^MG8&`IoaK1s-D_
zn2WZwsTbLQ)5?C=vY>H}K3ay`Yg}I8Yr$9h0rWtF+7H>5Z!6&TRzfnIh2EbLYu=wF
z)ckMze-M3}^+&P)%m1p#RrqV?UdZzI|B%>%`4GS2cRjnc@za0UMxkp((72vG(f1Wy
z(An>=y~wpfgpO^+{~>htQ2iow+$;S3e*pUxB6Rqb-Fp6?LTA5g1^0Xe}
zyU*`a-B!^-*9yfr$L3KCx8J>T=w^jpwL+00)-Qv-P%*wDO4gf0H&4>{(Q8*!GOE^=
zF;B~b^s41vPP;(PF3oj>*&q>Ax>AQgzSkTG{~yo+c$56;tFJ^~PQ3JN-E%cFs^?sI
z;oST)3r@XK^;)IF%HHE@8W9Yl0^Ha5A5`HZnMd-J`Arg4*i(qA>Sh9Rm0R4BK?z(~
z1>-EYNVqyHW3JoBxRlaPRrn}I%k%M+p9_aJ1A4EOg~mU9T)A1KQMgCT8E$}aamR05
zLG6ro=~A}i&Dh^S=Qr~%m;RgBc8-ZI;p!GJ+!X^Od&LnL*zV{vig9Ks;#Ga(7_Fi*
zURl6%W6QJ#tE5WiY}w47%z@;X<-TfU%->Wn_D$hj^g2~vEu#&1Stk#0X2-Cup6#8n
z@OkOTy}w%3vu8#u7ulY!a&gxu;{VL`UcelZnnMkYv+ZlvdAkhUkP$3K
z5*E!kZ@(n8re9wrGgn)gUmwdav^B7MTejE#^R^cJ&)bUX-WLBqXv^?FYD*p<%vLuT
z+LrvM*^
z*BEWRiAj{(%WaX)6)M*G`V7XA51pj%d$G<=FRQ(yV4a>|){(!L)wX=dXgixAWB3rf
zw&KOFPy24#bF+`n9zLgNPOm?#{ln{%zMJ&iuhluM@!y*-HZu8MaAj;Ux^_!1aawFQ_|9v1J%9o;dlxi?A^&IAsmdm!OX^8kLCA9Fe$*9zF#)uWy1_>H|F
zoFiQ7%v+>07gS=8EoH62e$2}CsbsWM@+67ikse_u=Qu51mUHZ73>D^rREDr9VbHOa
zLpiQM&kzm;O~lqHoIkE$`c;`X4`31%VW$YAa+iUPPkQ@1SI=Vpa^^=F;Z|*13!8XO
z)fYNd0on0C1Ym6dk2^xoGK6oPZ8umt3!c4@{u{#Eu^k*^-T|z&1DJ!PBQ1MzTHsVz
zcb8M)WFX8xojnvZBgol)iq)=K#Vn|vUqjfQFuf1U3m9I+?u6N$WtozGz~lyCG1W48
zdwQtj_HFL`dQD{hGQ!v9YB~Hisv@vmc8XE$7=ia4!n?WmDTW*3UP`#%
z`PM3S>?G%;^}<L5}+BmBl{#dhB`u+G#^8Bm-8ZZ3ta$MuGJ
zfP3Y024~Af_I%EK{H8MJb6&@9DBdMA2Gdb6p
zJt*D*Eb%Wbp#`xeKx==_RDzH9BRN^J$w$*8OVi2
zKR5^fL%bS|JCJ}^jm!Qo;#GC=vSkU42{R^COci#E-z7gc_xRiaz^kla
z9qsq0FoW+fHSyZCFR>&D^o@d#5RE3gn6vkYT%(@hhL+!p*FJ%~MEcdYCfS7;!82Im&aW
zDbT#n805Qq<|vKD39;ZBL*Gsgc|zEdJmkTBngfr5w2PMJxui@pY7QdaS^S^U`$CU2
zq@#CiUiI1=Q>q(lGjlwC$jA=}G|~Lf~=BQ)0t21YNYl
zvRLnGhDy8m4CWhX5FbS@ft$^&&46DG-Q;8b_C)Qq<7jV;P=eZHnD|HX-R;oAPg_A2
zkSe|fG3J`o`4#Oa&088*ml~al8pgg~G1^oSE{mU8VKY^HuTbvcM<1}LZQ%_J^pGs8
z0nh)UTFh?uYpSqJ_J~{Tr(rS1Cg`L=x3;KtG3m_5gTs2j5^ogCmcIqhxGu3Q|0m38
zNZU^;d0~jd!gi=E@jrk&{$acUZ|y1zd(X3B-J$pe1B@Br35_qv0W
zH{KxTKJdO{=IwY#4X6jcn(1NBv4`dr)PKH6dX_6L<^%{`Ve*Ti5g!*|9O&Bj`0Xuh(xX;gh!%YBE9y@xwnJAD&w
zUbQi!>bJGt7i~)yHRruMdxlnCDWTdXA7hx`FA-y*Q5>|_DzGv$V()f(+E&V5cJ*k!
zTKbau@|<%ooSA=WLDegj@+$|{AF>Z$ubLam&{|IK=g4kbtqK^VPfXB$p95`&d(uu6eypen}hYJ2=VC(NP+|%YCL28C;DUvQWxgR>2(Q`4&<5FK>AHXeUcFHrA281UmHn`zzF&{~jTY7*t`Yr<
zSYMmxPx~?Hmm|H2xdy!0f8L@Ep113zJ=*==yMH+<9Ig3VuWwxBQZ!$Ue~tW5^fj;v
zDg`WavGW{je++iy1vhu}Nq-DsNqG3d}R#JisBPt4I-GFW7^
zL)UyrofHzmFyC8rwUEOct?+*zNZ&KVT5={s&+vNKCf&ydV1xFlc^_ABF_~fX>`ZGU
zEygg|-=5i^6Xapsi07b(!ENK)AT=CufkO+R;7c8$78X1jIWy*Fu20(=U!V`q+*(Su
z$K1XwnW)>bG8bCj2P>sia$)X-T#YXuw@)DxzU`-PnPGw@3R$5^!(!jq1hPT`#w80Z`LU;rYr>-h9$AUOla{KzNb(cW*SeU5|-xW
zkWG5X^t@4JNC%c+p&1G4NX{{+KUzE~w9B#oNn#IqJmD9z3j$6laW+<9*HZku;2ujB88$2j0uST9^9ZGnR01!F;7M!JAW+VXZB-!T?@G2}d+P_8(0UK^cJ
z#nSoQ-h}zEftdFW|ClV^qLuBHl-gpY%~#WV&m;SY6y;`bq$gwDxA{%PNw7U4$m|yn
z{>GCr_}pg+BCcr5>q`>l$glH0D}&_%G!oc$aeW@a`qb>hsk%?pV<6oRrx$zh0Md#x
zNyj1sclA<1-@gQT4^sL=n5qz%1}RHcZ+xvAuJWa-+^wBk^*&rBq?JXo<5fKwNt@WN
z&>P6y9|z2+9~h~NW5%e0J7ED8TMN5(p4SQOg2u#YnA@}2B?*b7bp|*^^9n83lf?-L
z8?shtOfF|G<~hRXJjAKfT0>S@kzNIzYu{r2{O8|HhMvXwxkYduNM|2ThDh7IcNFjN
zr8cJxF`(-d@y_N9&E_~rJ#9`>u|AEF#pPzK4w{Rkt-ulZUuf=lBR~^1nG5v9u
zgc$>_Lom1_&EPEui~W61w|N}3$txUTS?Jvip_kv}I>NJHlZRU&&griHg5D8&Nqu)V
zc^{mM)L$;j*WW1HyvL;e{>Eq09ZxePKgBAuhi68bUT=|DWS?it6s9#xB^`b09sV=Ze#q8{a-xYqIjkD7cdOs%tR+l{^#?raQ#Yh#KjOi=wPuZ3dE?t-$DzwZR^*mD?s?h?|d?=8{Q~6JBH!s(h*NXpK6tmP&E9aUEf8
zxvG2{G($w$+0wisQO{ZtF;=vl6Z5C{wY$=WP+qe2q0<5DAo4aW%BOr}jww?F7zO?G
z=%|3?@uv0HnOHsutNCHf+=Yo1Kl?`XFGT@<;mpX)1y!$A9A1CGekiAlBA#<@{;5|g
zJ>=WzXF4PY{
z8>pWb*Le5(Fj_byq}cj~25kLl~pn>DJkImg(vX
zf|~yw?fjZWjHw)#Q0io6Y^ew*h#y*~4qb
z!YUkIifCpp8!2D@!tVKO^B&G8;$;4taNI>va-H~YEEC>`db51*9}DlWks+(1nHJ5i
zTa9Zo<}M-Yf_=xUU|$g1mx=sW8w2uj3#j|(j3lgX@^|Ywcl8H+!Cqj_inNAC4ePY%
z00}IDI99(ofv8Y;))n4WQYM2akIpk99XG(Qz8zF~KR
z*6=+GRH*-%XpA;B{8U_rcVMKmXxCdeJ|52wN(
zC=K-uxjFizoK7Z(*V^f50``t>lcPt$L`7JP=rz3FoQxFpnv^&J@IBHTGogPQ!30m)
zcmhO9XhjNNPdRh^dDe0l>l9a~NlJSbso*-evZT=1cTQT0hA&5R;pToF}zjO*BE|BsDp!kvU)9oM?1
zIAL7YrZ_XkMWcF~FGw7qcLlbQg=q8Fc{{2wUmtQYm`$v~j()R@%`;s=Wu5ksB5t}}
z3k&~XnE@yFytZvh!eP*zAzh{}8vGfe!J(PM?K28`u?{(`U6$8?3Pf75tv^nW`?1RA
zt3ReclKViK@Qj?5+Fnd5TY4$&Lv
zIt=+nO8hZ_GEN7l}xr
DvPoLC!pf{2Ui=pwg&SBIME|LT`&Xx(5#~
zOKAu3fySs{gFsZHc6k%}HaJ@>C6pL=Qx3bY<|#j-Mn0A+?Q{hF1f7R5@N+m;rd^)T
zYL}L?vvaB}RHnZ{Gw=gBbj_Qmcql($TT1mia=nQ6J74DfOD*y@K;C(gE$UW+T6prm
zsZUfhaSF6QZ9#9`tTrtT-V+LWA6#@A^an96DE|%QPf>-JGqJ6!LGzAeY0g~o3|fDY
zH&YI*_mz{bfny-#ZycOE*k+n0!!1Cjd%c9C(#ySL8ZD64l}ydU%F+2tPcZ+IhV;Yg!`
zC}i!8XmAZ;*xtr|Qq@oGt8eB`U(dLE8;5hGyG7&F*2DKjR2nnQXpz3FN12l8Ipf_b
zX^)htK_>g(z!wR^N?6bIa5`PRS<=Y27u?qU?yue79zELq?WxZyGRI~f%8JYS=D`#D
z;A!C(=IEToqh`?ESQ+b{C9K!QgeACvrx&}R&GzcdVKZUR44(eLnc5X~%%?KZ?*w^W
zP%Ufa+H%zL$+`BYQirUQsg{jwhBPqx^kRa7c|eaP!{&ge=GT)$jTGCN8#sB%tFwpA
zrrLyhXMZaDmD&dTYs*)q?-0eS@&EmQdGtKJaIjGgzz1AWAT2G_aa@1<+R;%ULYaQyZwZ|Li
zYhbs&MxK6y8;DsSFc~uI@qt{lBJf5o%{wN`{k{1Q^u^F`?7RBvAa6^=I_md@pl0A4E(#gy~bM3cH9kT@+l|8ou
zfvw>+=XMZE2g$&fL@D7}u=x<4GnLLJ8%w1Wq}RE
zSBXJ?qsszI&7W`6L{|rz{t?5Q-n_>+!?&?n4#lRn@>s3}8W3RYfq});|AxXJK?r3QhyuX6y8`j9!XCR~?U%#`sonVXG+oZ{m={x0ngx2fFUAw~?=OJD<-F|8H(+&8!
z%Vb|qw)NJE8JFh6&OUj3+gqRwz22WtvlKk`k}>zdV}G#c{IVC7y|ice=je5h9uB_*
z#szB974SIY-+d8v$&+L+r_Z6;NIn%S{kGF#yBC};*yxyxdj#U1%{bO&!rLD0u#P};
zj1u$PBT$Bzt}{7vt(&14&Y6hb1Yh*!=)uHKvb*yWG({ajuuxr1^*F+UK(md6Uq0AB
z6@G*AuqaJ8@0%QGF*@^?vsziZj_fPH%U5o$)ph)4@cR1A6FaCS2k0x3kA9mg)=wpq
z-ZU3a7S_zxrZ%I~WfSOzxECvXaC)7ohFflolPs3t)c1sTr!kSWzi
zBw>$*y!#Kov@E%j+KPA{sk--?k|(<4w;{b~$xHqc9`c%9_y+9>$UYF0Eo~{FDcU2c
zmZMfY`(^f!skpo9Iepc0?QB!2OOrv7QsmGzfKPt#c-$|?ZH|8=fFeGo%<<&AiAQc6
zF7U{8pI-E&Y&(z0Ud6=>*-ZAA5g$ki-DGZhIpR`)b_*s6;=k5&=?AeM_Y-10PoMXs
z^gI3U>rp;s8AkPx-Jj?MsJoZ4*xwKo?aI=(N*Ac|jZD1#bNCAA_zgvBTAD|g3~O%4
zJz8^0@D!S%jRJmD8}g`X!{OZuX(3B!T@Iu?6O~h!IV|w@R%>I@!=C1EM<
zI;6yIW=UR;1yrJ=^J}E2FbsO*kdE?$?*XSN17qO}Ay)o4B3z?}zU1HO7QPae#0_#Z
z@WWydG$><_DVI;n9K=6CcNXnM)ZEIN0!5|VP;gS3~uf%(PYS#IIS)33SK7+-q!6QgNe3#bfx{t+o8$Xh@dorel^?_@Qg9??#`$eX-dU$Ch$kyMey&sNxxS35)DZ`tj
za$Xs_7j-m+%4KxQz?4
zE6?SxX>_`qBvhX!%o{h8t&B3F23XM
zM`^=@e)RH=+rtINcSJ
zMzsxcDrx8z1(Kiio
zlWB~Q(mrP162ox$Ji~1^LT@w;dZRXGWd7iM^Oj<06AjNFnZMPbHP%YFO-=aj#&;uY
zcBDaL+Rd7GfzsV&W6f_jvF3te*8C1H;oga1xq=u8w>eG1IgFB`&5vzy+Ga5KH#_Bx
zY{eF>wVZ9uKb}9>p_|Hu7zY1%5-77<%
znX`FutlofWh-C$R%_%K)oU($`tr}b}2%$E>NWZ}U}
z9X*P%&$Ov$Dd>Nh)D$>^Q@ZWy`otS|>;I5{*Itb}XD)TwYwe(HexAR+--wRbP@G;d
z`laTXYZ$K2yReZdWk_;mS%7`Ob-eD#lea^ohxwsiE
z_CCjG|9FQvEHj6*Ebe~b@k=|&8>a()vtqe+!7E~-ob+HIl_5)&Quyrzzh-jocRWcw
zNf!e84ui|V#h1Os&4_2sVe?ond=1@x+UaILH+P%d9R9AL8uyf%dH?#LLVTVoRwJW5-8
zB=JB>wAAe4*+>zS@9pVm3`2VLTHs;x|Lm`9ts`@qg?N{OegkUATzfBAvjtaK_OMELFcRmhZNKgaaM;B7p$;pZNY38`0`>J
zqkvTP>pruz;F0#J!fQzs+BfHv1*S`&s%X0+77+2KPIT;
z(UWfGf@d04-HVGU>qWNS3-d6#=8k@9Pk)m=m#X@#Lbx2hXZ_EwMQ~+}0y-e}IXBd^8
zhjUbrCHg&uAO^x=
zwXqR=)vpjYWrL?=bwl#BN77`xqbUu3Qj({MtHg2(GLdSuWa^)W)l6Dg@P;BrnnK)<
zl+I1RUqX98^C4d){C?p3-OgA2JF7a%XReJoWm?Y<6`yTo;;DnkG@;5v{AgGB+5ph5
zTj-PoM?AbJ!0{NQN4A))4oiF!ZZr+~2eALv{cy&Sy{6HAsORXoGOil&s?)efv4aZ0
zG1(EoIM<$uM~&MwVYhHwS<}E>V!yXaWaHLM3EvC6DJw6rOp2cp{vMtKCLAlB_W2*S
zjx$;1k2(6Nm}I6RpQ~x=Tw^pXw=y|_S7@nC599kaj
z=I~VTvn$xs(2X#MTA0`t_;rN@;bri*t9ZmQf#2Y8mi7$x_83*Zg(cdU2W>CT1)}H<
zZuMc+#^M9EZur!|E4uJ$+TN3=37<}_`Zc>F)2u5zR#%`Yw>HG2*w(`o8VD*%IsTry
zYhL>9H=R2pTQiwvTU)u7vrM7cI#A%BulhNi*Oe~{vlI5`EA@`x#+^s%lijTXwuZ`w
z<(OF3H2#XrGKC%gwaXkX!>kR!nTMGROJ&Sq7UuZRu=l&JHP5ohzXtpZaqRknPmZja
zTz}?_w?6sGJ#A%?uP>XAIc%++w4SlgHMR1+yP=K)Of=s)cp`d9&wR>@>`?-Xc#y_0T@XKMs~_2**w
zZ#&0I)5Bdd;u|bnKX-lM1^-?2;c_xWuJoi#`6?C^`sn9-NmXx1p*Qa>nY%vnD}MXc_g+|%5pd^}(OcG~^?eA0+7PTz|d9Pu}}nQ{g;07|c-hY>#4GvmL9
zj%ts04Y(($l{0Uv?X|bnJ$MUGlB@bHwfFP4qV(2)H^aAqj_>!ws=?Xd8occ(nPTT=
zNSWwq<{Bw;G-=DU3$|x%3ldu=R9WP+eQ5a$(Eo
zM(T~}bS-nyXzJ&c9!-j#wq=@pcI$)%iK(Cx9QxP`;WTN
z9%njJ3!m)uN^fho(t5Eyu9jyVwxa@{%|5e6ZJ$}KR{GjIdjFdv4*nyl=~S&`Czb!P
z8+56>;Z~8#wwxijK7e)2ZQ_+VT=y3q$u`!r-sXqPD8p|_%rkhY$`hQkZQCPGh?+3TGsSr>e->xEB)N7`O5Sc-$KBG&M;FqAi)b%h
zp0PyKng(rfxkfB2dv;OElZD;C`oAycYRZDB`K5OewJMlSU}_
zWsY`Sl(J&!y;HFNx4fFLIN^;1@yv(MfTf7iJ`ZIlh2h0)?r;&itJe$Rj^Iekn64!=eGxey~rrws`s<9s88I%tSn#M6S+O(t>%MSHtvJ0
zEb|BBt=s{H)%+g*@XNiA-#vyP?!5|$Cnb1IKx+R#!s>E{6uR8nJ3Ux?Y>&BG??L89
zu5#qTf%YTYqr_S*22awM`>N&lIQ!ASsrIMVjaD9=Jx}~5o9Ibe-JWQ5wDe|teVF7)
zdhy<`SZD~Nw#;+d~#+
zwxF&^P8uP_*i*DQvn)VQi<)}+W0J6XoJb!9*G|=YK3cTXx5uZt~BiK
z&Y$|N*n;ov)`K^!$f?lBhh_-wG5c$i=pE9n)z9dcJ}4{nZadXfH)UyF-C55^XU`ti
zO{EBVA9*&j@LMb?lT=t>dDbe0wuH`f(ajKKK0UdL8O6M37;FXIgFZfaXt<$BFV4w;
zSWnWfE57*|fZ=N`8
zIAB3k5AZEbU)m(A6r&XH8K|`>#jhK_(;u*kHKzU^?bV9Ud;b^Ot0C^49y>J4fCx%S
zcfUBSA8bA85_9N(hxV)eITn5N;pvr2o;~9N7eK@S6V!+T8VI|$#m`#Q)m_n==a(%w
z{z{3wCi()_MHN>Jud~JQoC~a>3dnxUvBJwKN2Lu>KIKkuwBY$@+7SCucLH$ST)Qh~
zu7>H$?q&j54f`Imo4vtkB%d(5B_|mT_cgPdYa`CcY2ck6Py89cC*5<$lk`e+h;EwBqYM0L@H(!1cHp6Po}|GDCP-;jw+>m=)69D(
zfMY6p{T@5<@I>{bw0LI2iuEWIo)xcQCwqCms8Y!M}&$eloBN?i9`D
zxl>(U_6Y9kYEROo!(8!6@caYhKDf*O|H6HZ5AHWLBHUl?C&K-|`-yP>M}!FX_a7DE
zKDcN9#C-zXSAS&JZ)H@OWq>{4`Joc&riF&p9Q3^4D6@o&*(jckGB)eA>x^GNTL=c
zJ)Zk0(s$hz(`0D1bG^TY2E4s_a^9`4UGNcF_@Yl3=V`#(-Ln223y(pYsu0m^#k2B0=FjTSliG>#9V;S6~6wX$7j91es*}0g1bFW
z@j+`Z<4J=5KmWXNG%tC#>5NCuvFcts%Ew@0rr+{)AQYao<-l&2-Ia5LqMy9_TDS!24^CYf=D0YESS=$jFpb26}iUvsg=d-uyn3(
zIQDm69v1Mr-nC*=B|`tcdr&VY*84+MSG}nybM~4Vk=|&27H!z|qgdBoq))lpRaXN`
zbv=27sN}gzs!E=_Eb7KTd*xxj`@_-yrz-{{PP*xmJMd_>#eWWVig@==osK}jT6&HX
z@$qk=(_$~*n(&Hc&1Ar*u79DWhl%@?w@>=Ss64ebfpGEDhXz|4E%Who*SYZ4KP_|c
zly{LzDNlWBG`kUDsMchIE`&QY>&930J8k#P?og)us$+eqfXjdQufbMLuJGX7DHmYzlQ7Q}meF|t@>TCKaN%^|o#G3nA2(8o!@LVxpaLHm>C_9AmoGVN
zq#lZS$@YW%=&W3#u9nx(SXL#6Lxv9@qJL2+AekKz2OHLGlEHFu75RwS0en>`{Ab)L^!E(jv^
zi{I#ip){onhSHSoFy#Amhhg#M?l3f7_QP=XSGZpQR=)tlND+q8l%K&6U#Qg2V2E_w
zLsA}sA=0|T&>z>2AUSH5Ba;ozk0qF;^#{&aT2L}-7Iz3dq}@iwyx&Hi<``9We6T&1
zpPsE3NAI2=XrbtShqGTV>37^vHnsw>Tiw7K_BQFLSvz#NE0xmReuve-ASy8|XzO69
z!Hk+ET6QhXJB}}7gjpY5N6{A6`!H$hm%tx|1bLD2BTAwB_q`|a{hf!u&t4*~(c+VF
z=fo%5$++rdtWWVR=44zQ*1{$6&0QIH8EfH+_?A}rMM;F>i{s)OU-?B@vf_&h@vYeX
zMdfJ47ykX={^C@)uR6<{E~I{Tu%3wm71nc-AF{tp2(I~BJf>RBB3zcqHhO)L6l9T%F
z?)!(w$AWJIJ(5U=tq-HRhc6K!zAs=9}}4-S(O7+Tp@=?x9hZs2MI@#o}{%xQX)AnDU&6bf~|59I!##*a7cDs6?V}nF+C7A?pz?OTtEDw$Y{#2LHCV?Cia*wL|Q~<^XQIM5Unu}ZH*5(U@HL4
zq&x?|GVe6qUu*1T1m|^Tiy9?9`PwB?HTqQ^-RcwmGVpE(
zC3@wQ2!+(u9^KFW2o*9u?Yx)=A0Da8E@&jcSzTJ}>kWY0{byn-`MV>sNI%!Zek$9UXTyrAiV
zp$`CQ0``h&-ZF=*6&eCx$lpyB^ac*$PKJAy+3*I#@tL@-$?jms@wlzg7u1CFC0NZb
z&3$(PQDI9-w*Ym~7mnY=#L5v-G|Ze31zRh^wX30_h@FZYhzEY>y?WQt66`E_h}k%T
zjYYIU?BqMp2QO?4;bJN>KzSfiAJHH<^`cud=uVw)gN#0d|Nd>k-;+un`Mh|?xBOL{
zEz1f|Na46t*P~0`HO7?)SmrqXS6I&!o!VDLCv{b2T-lk53uQIOFO|G-MdG72jVsNA
zA&J1Bc@Tboi(mZtR<^Lti9@xVs#8c~`Ci`b#$xuZ-|y0jzQxy;2#jNqa75p2?gF9}hAKqPb*c_B@G
zJ*t-helmcmhUecDZP$>7lRpZlN5;3yfT<#d_W>$sjuO^Sr}-FoJxXolqNM|rPp=y_
zHh*ER5RrD^?Wn_`?aQLQsL1B5Vs?>rq3`bXNY{=RyDX-qHfM(thp*B*av;>-h1
zLRpH@j~4=Bp4~>%d_`2mI7e$Zv-3MuV>s(*_1+ITK{{Q%
zPkaK|B={S`9lK#Ncn7*gmmG~e+xx`l-M;82(U-GzB8MXScwz}GkgB@sJ^hRI#v&Rk
zG?KD9-stEp&^%GMv*;Z$J7gJgg4Z!$N^C#{)&o59;N7#K(<0>3w^5u!p#^&kQWqtbcvZ?g@=~RGn&jzAuk(EZ#VTM+-WOLTlzd=4bk6My+cbL
zL{H4Rjrizd^hDFf+X^4-hGTtw5^b^Q2~wVnWA!wy|NU%s&E%9DRKlmXIk#E&ar$;u%SOZc{V%h@^fU{pz@S
zYZLSX9x1dK!)f#}#?-Htw}c>PpRcxrm(<%D|5?A8|L1tfQwDE3ka_xZ-?$^Oe-4Px
z1NuMcneOaGC7GTA{mrfp^IPX|o)M80{^GwjnF$TM0iE7Uz7D7)qv*6+NSm!C~}l_Mt1^F-dg
zAf_2-33e2bgDXA5o^He~kaN278I?_X#~vLJ@q+b|MeMb#pS`zt>{kJ(Pq%0%Mg6Jq
zec9X3qnonhd0AkyXV~3~&szeT2WKA2L~R$Dgk{yvWX`k)wX%qv=2j@PJ
zV(9V;X!m%UcX|9+!_t>lWpFk_TlBOxXO6ltz
z`ub1$s_=g`SBzll#;F4Dt}cRIA2dZ<<%_@0tv}9k24L18M#ZWizv-RiP32go{f&(2p!T@~w*D@Px?9YLNX|(v0Fr!MC2q_aaa9gp
zCyzVj;7i&b+%@j`I7R}sW<22I7zuA_cYPcq;f=rR;~0tG+I$=%@mrgZV7?zo;H+O%9>`tKw}>?bQzq`J%>iZS~tGCP325xYKC5
z)g<{;H#lKiLg0kf*$d{>%rX370$}jAu?KEk^(OCqaGz={6Jmk8>7*Eec&2A}l^Y`j
zZ2aUd7jT;jqbs@gLm1Vy4GkK>rV~G`cz4!V+A~ioTzV`d0%E0
z%?J2U+F0BKuu}J6r6M)-gH{cbbQYBGx%
z&AKLbH+sTRkI>7t)0HES4%4i4Gs0>s=7&G@yVv)=+xPqK&)@%QjHtsJj7zTGX^gmB
ziU>%nN`yL4<~yTv|V?@~nV~#xNoMz|glr>$3y4L`y`aXG31;
zK3h2E2E6bml;^_x(0x2&ybr%$&}6_945Xf(VOOhWC50qS8b57P#H3#Gez2OJoR=%-
zfD5MQS^2qn76ajW&BkhGcgA&a8r+eDMP?{eXvEkt65uy`S=^7F-tKY
z)r@BI9!6um&g8GaJ}*#2(%5!erNXbqA&u1RON+z|2h;d9``wWgD_nEH6{$JM_s7Z#
z#tkx3Q;2yi;?<62$g`(bjrkv~*;lLv?n0R+wdMf6ALP}e#xK@s4naH0hm|x3-I0!E
z@W1v3AiqW4&wr0xmGJAg$XCaM>yttEoYoAJwV{v0CgU7Z(AKTD1AXVnG0(6ue~U<%
zrE_dDGCS83Os&#_FI{|dXG5N86W=R2Ar@&-Zt&-W9ko1p?t>6TB#e(C?ZaM0<`kzei0|FI9Q?@#Xk^$``_
z*Twut!}kIXGE4f){j-nw%I@_HTfJkd?`^NuGi=xPou4xds7Jn)Ic#C|Bdv>?kL`$m
z#8>BEan=ueajXBV*B{1NKkUT81kIZz0$H0QgtF!W2t6OK9UfD0yFdDYl?gWRF(K)NH
z>ztX@63|g&KK0Q@16(^ZwZ-}HiPkiBAHgS^C>n#;V=sFjaD#xu=dFQW8Ms5|W@;o}RuklcMpF~3;cD649I&}G
zjoB>?XEgylyE_0FU5W3=vt+qLF6Gk0SLUj`z!~xk>A70Og^VzH8i{5#!9xq#cix%3
zUUSGcpYHi|7xv$E{agwEt(M*)oyb^yoo?WQZRgK<4jC`L*X@4Zjq~uVb)SX!7Qhp@
zql?;yhi4~R#?FSGVaBod9mZDpr%TV>__?@-Wyzjlp5`O2--Dtd{35^dG`P4##h9e6
zJ}#;I-R``kw0FDnlK6Ka^(v;7RJ>TEBw~uer>x#ce99Wgr>-r^k?0Q_dO?@Y)BIwc
zxcUdY;~AEB!_`h=Q5m=$=%LFM%9#+I+
z=wqCy9!C@|$+~Xk$`%ZT$0B(Km3Tnk?h&;(B@_I5oRAj%^TEDeNBjD0b^IfTtwXKQ
zl@Rz1d-v1sU-T7Q2#sF;BT&P9ulPqC@Z@x0ORW5(sG$$V{WQnOdu`6Eui)>C7UIwi
z1vkc!MLzM5%i3~cdB~(--}Ft+9GQzR2~N*Jw78<9S!*)_PP%x?3o9^J+CmM}!en<#
z;iqddT3`haT_%w}T`lUg+RKU)vW*C%9M;10PlblfwSKjIbV<7R49=NuiI%UGXz6!(
ztz@IY^b^_p!1g$whYuAVR$V*F%!WO<<=5$Cf^}|y!L$xGx|`(8=i8szZZ?3^3p=xw
z%Qni3AgvPMn#UP7F?6Sxo;MV7ELCf5r`d=Yz&`5V%9{;k45cqex|BU6pPrY?&)q&Z
z&uqNSoCL=!mp`A^l4mybW{;xI9VK-obqSmyinSOV%bPk)y=xdpS~zpL?D8beSPg&F
zH?||PSsrJ+4te9{Q{wy)Y(dv@phvj(po`$`K#w|*LKF)7uE0AX-8IBRxKYfQ9+TmO
zVK~pVOMmNM2yM2Y7I*_7ZI`tfDp?5E;8Mv7xzqSRQsTMx<|h|jB8=UCv{xV+1nfjW
z(G?pMGDCVE>4zLgf3Uy5rFrC_8$$A7L>~Ztk}J4!SQQE5fL;^EVJ?4)kr`Cp+D_A^
zaz;h6*1|>wt6!TTwqcvE@?H$KyNeS7nhM6z&9mS{M<~%sGNWmMi*9j9t2@zEBJD+g
z2^J+*Zts>qmGZCL-aWT1S&6zkLRo#p6mSchzsU)LExB)ebLgAJ5HZe_e-T!dMkYdN
z=jQf?V`7ftSz?Z4Uyc|iS;*1yAct)R<$%}l7*JuvD}{I72lY>*Z+|r;KX2M`k+DF-
z$P`+`SW-JezsZ^O6^+PZaBe=z)Cbhuca+1|XU<74>0J4maEeS4
zUFFDJ6RtkRl}QmV`_W3+6IDP~f2|+l(+=X{h-ctmZ|%qcNUgQ&6Vsj!i9D^wie2TiFROfAg%h
z$`Wm%o(<02=fiCJXK-Fwv`=LqieI7bylYLujboMs;?{}UVE-R`?*blGk*y6^cRC>n
zAp{5zFu*1d3>Y9ct_LueP6!y1kObIVo20vwG<3R~?oJ4Z5+FgYih|rkjSM29qX;O7
zj(`Fp<82sq7>99CQBfI*il~U>dso%o-8&&5p6@*8eE;*GhRR#DYSpS$*IiY+s&>qg
zAiUv&gd-aoetF}In);oehSgoA7ASg8>Vd`{3gVgzji7n0`HL^~ex0}1kN-8=(Iii
z`tW;IT5r0PYOd;|qne^$qpRQ3s-Mnm`O)yqim-7zm+!8fST}a*$p^9e^>1^zt!c`)|H`fiOVYv&uiW&hlfAP@NN`HSe^j+hg{-$OZobzSL1>&Gz?gFq2ZfX
zqm71CIdxIyE9-uZ+_Wlr-$hXZ_gut{s9&V(GR+Ofwig<@ufmKDN(zls+c-rl?DU~o>s(zolzQhhvPc5R0C$xDrC=1Z^pN;f!XPu&>Q
ztog4-8TYi>#PW@MUO=kqzDQkrtP^fJe?NWNp=qg+sRuSZcpv!?HTj+|Qdf5VTl%Nx
zUT?T?=IVjy?EC*5jB}inZx~B74vrkRm;Wx|yfx+UehuF_1_V!0*MyD-_
z%VYuBM|B4_;LYegozwR0hu+7dSn`rDQae;f;jCbXjHF{Lqk;lo{PPQ_Z3C8@I|du}
zyzn|t9o_HzO6{m)PaY5GXJmUqsqGhulH=twMQ5J#W00yxb2NX~Ibe~I_GS22oBPx~
zz)y~-yvDS4W0PBNNZm7JmhQt9E4yA!-*Zoq&g}isSBk+o6VZ1SAlEMMFgJ*DD{7W!
zdjcmT$1ZQDa@+j-%I)LVFGXiR_pjjWx9{DoUKbV`^5Q33jE7P;rjAwDD~>2zal2cgrM
zkN&z0-~RaMm)*R548BK)9tJ%M&Py3s&wZm-Ja~}ui1z9FPuTTC9z|uou)HWOIxT7W
zf%O4dM|BV1`%LYg=Rap_=TjT}Jaz5Sj%-Ef%1-;z&7Xa!Z@K?bHC55PK2*OQ&nP?>
z8%%3<*4o~mmi_VHvYXTd$CK3SjXQ{X5Ip!8Jp=JhWcBW>??&%gIx)>$gU3kQ
z2S+WRaInkK=(Oy#ZmT;C>WGRuYy|njUJASxsbTr<^v|_{S@V(DB(%SWT^_kkW&v#@oM`*0m
zy36y1ezgIyV~~?QuJnp|l8N2!`Z3$39N|(dVhL4sku4#AFTo=eFr+PFluIchdFA1FB
zUjEsJKw95B`d!Xp8Wjh<-47*o`{msja|RYW8y@|YM#?mv*;%W5gQbc6YnU6K+geMb
z3Oq&m==XGLC~olSQ@40SyQ6n4Y8|=Fked4K!BmVq7h(Jp7;au27*4&+jJLJ@41KwQ
zr9HE9XKlx`VTZS*V!fDcG1j%(a)h4Lb))^giGJ#Lca-Fes-s?o>wtIYi$*URtIG*p
zv1m--9V5@S?mR89SIk`9jM}Kwj(;|Xgz0fxG;8yEK;IQ??NQvd*!ha#bVhQ>u(S@t
zs7K4KGe3L}Ziv7Ap9Pz!yicdjP*TwI=;_q0bu*SyYLJ%B+YGHY56k%Ao==wVToJP>
zHDmliId%NMA~Ozu6lwg+hwIW0f7na1=%{W*8R>7@KGdNPEB0;0JNH5RMxnm7IjYuk
zY6l0;?yT!_)OVVKuT;cfu0^A7s?X7B=GCpDXg}VG<6<9E$>~|AmcG6H#M{Sad{p|O
zMT2*@x$LnZICm%ycU^p|2KP5IOicWJ%q%W!9^P51FW
zO6NCdKO%)I46FaVCF9}OzoI!uL*v0ct+ue^uYI!aH0qrQaXR&M2Br6O>Xy-jllN8p
z6({KbB|B_u*hrspPO4(azcM%
z&P$;;#~h1#64O=mCdaybOd(L~(}-u<;kr+!rTzN1@AH0OBkvjHv}qZ?
ze*f*kI<)3JhkU%|)U=k6I-b4Aa~8n=sc1mX8yG$U21EaX_`g;@Y{kSsf4&My8}|mu
z4MX%XTYwjVHDGYVl)_Af84r^UgL2jf;Ac>Nfz5tFzwvAJfB6gkAN~ypy4;u=e7Uio
zf(fvz?j+F25RLr9HD(0tXWIyK1^AI-F15bgsJh8cbaJ28m{;0fZe)`Bi=&_F@Z++G
zra!fS3!U-Kh>iOT+e_!rUVa-%W!#%2_Fnw#GWbF=;=_hxyI
z4G_G~0OJ!bH+F(4g2{zRSKNb;pKt%t*!brF>MX@Cr3Ko{%TI0CeR9i)&ZjMLLFMh-_>}9_p-oNxsHSe!zx}YwjW=Ud{+2Ka
zGKd~N5@~`Vw`!X6_Z#8YqYrqs{?X0cYm0%^@Bc-#
zYu_QVW2eqhU6in0Z;9^Ky~p(h{g(grL;kn;)c-L^zOpk&t{JM2p$IXEWt6nL$l?1n
z+%BxWQw2^In0lYUWv>aG^%KXM+5u?{zjxc4IoAGd14rvyZxKqSdVM1*y&CPFxxmkab
zd$YXy#{}XS
zGY}>bhQ^THcU^A$e5Wvx8avUFp7#4)eim(B@lOHfDE2L&zXIOhGHM(*!oiSLs)_SP
zyj;IO`t>7s5W*9B6(sx4y-j(Dc0EJ!&uSKbi9(yE(DN19CxC+y|8}72NAXVt-z80)
zmlZqF{gW_ZOKA2(aWFR6p<~(SbgW^Fo=qvy*Bn^I-2*Mws)1hbyut*=#yD(VDI;f$
zG}q=Wm#kG*hgUMXZNN5EHQ3a=!s$|>x7h8qIm)DQS)(Oyv1j&x0R!M&QCh}sQ-2w5
zo7ZM8wo94SkeKCmR!BKcr%Uy|?KUB=-%bAne-UDnVm+jSdA5{SWp$U@opU8~xz#+|
zY7so+tQAi8JSoj?cbbd6Rw=94X17`fNEwxGH>JmJE%izs+kC5J^GLB4sbrql>Os){
z+F$yF(NZaCUF`Ij+}2`?RO)m~ZmU;`11X-JUL}}G7qPX`uEyNqo(CTI@^)kCYRf3)|3!qyhOQQ
z^DudZQX#U@QfarkMR_KUD{*;{rX&Ri4H(32iHZlxn`ef(!ea7PCnlDeJXA4Qh1oMQ
z*20+G>fl&vvwN*>Ze_Mo;pdv`wvFpUQ@|@lexUu
z;jr3GNW01GtZ+%icDpp+>UKg#6JB$<&1FK>j!WoE@ip_iz7Xhy_}SDVdAc;gW0kUt
zq;VOAvG&S%Y4jM0qqiEZhjgy6APY%4mv2L}k4s7DmxykI|DlN8bD@UYiuA;BJt`e&
z&|V255DWY@Zr(d6Znx?`wLq2%tqu=5f-0ML-gNW=#T8a5!&!+&7z?Ee3Jb?bX;o!t
zgz=KGu&^-8ZJm?HbI?c5%QB9;hAi~f#K+^$D0WF^r^PC15~tFJ^O9n$u(--9jZ4dr
ziY*o-%_HUA!G)QNT|8)+({8akq`Bz5tdiC3cDm!y=Aj_CTIBImdMF!tT@Y38#(#Oe
zkyv_8rj$QdtuI{To0oBI46MX%ZBhfJ8zlrf+?ZcU6!_Gvl1eM>cBE5vQ`S*7gN3&T
z30UT`InkY>zDVV^vT~lU8XEd(PEz@Jr^=hI=!dyyuYSGykxUD3-j3n!_isA(z@{a6L6jp`Kj+T)doNJ=#;cdmD{
zs?j134G(8AqEb^M?Z$UHe02yd)VKpB4#f~zoct&#qA}6Ggh?*C}
znIy7?wF%{^FLIWZp{0oai=HEj7(5u9(jcBojG^mvOCFcijD%2bATu21c~Y^%f}w+>
z%u6-936G$nsO<{785zJ3r<6%ONY7lSSF%;O?A8hze$2Cad-m)J2JsxLq$En<48dbG=IIR5#B}mk`BuC3iL6>HE#rsyf)#R==VVvYedpF0L
zN#_KN7pWg{mzwcBbClZ3)JL4?FUe0l%RM&bS#Gj8m2OID50L9sT118RJ*P2rl1hp_HnZeLcScV}UxW1V
zD9>``QLbfSIZj6zgBOJy);7O3G}*c6_U;6#dv`ChiaK==nnD3U`)`=)mly;P2r-M
z#OMiPWx(FJEE-8LmFZeVa6Qh?mVMa3B
zgnq+aG#G0k1@3^C89G*8OnBZM(VJfpKn4vnWU;qcl#U=iJ=nFcWsB3dhB7}Q|g
zPi@L=HCr)X5*?Gb+$y2_sI*eAG?gMLojaZ8FUqikA^)XVv!v=o0(^;8{F=~8LM$Pr
zA>|>nLhK=q5Lbvh#2Zo-QXMisWI@Q?AvGb3Lux~ohAazN5wa@e-jFpR4}`1>Ss$`7
zWOK-tkViu5L$-!&3)vpBBV=dD(;?4;ld}}e1)l7qlO4bj
zzzU!~RVR-F+Hcj#qk$#2>tw3f$42R7TIigWu9HiEGlA3ry)sfK=L2hFbux7jgmz$5
zFP%IFnB89|PXwOpt&_`vUE!wr%uKk8i5{<$X+f265-_EoPR;>tgq{V!rNBbqmA*RJ
z1{@2ylYzYl>g0I};<3xt!(Ubq(;oI=j84u3>WAuN9q5kela!Xi_vR
zAfOe!_7A|fhIIM>tUCqg2iFHz<1g9hUmX6W2G@tx(_h6sGuXoIuHYJAJ?Et@1ObM?
zpjN>lp{?75xAni35U(4go-w_8$M#`ix5jEX`?LkqSawp)WB?h?*F#axs+?D8e8{}Jn4*(@#wb>x|1P-+r
z3pk2`q1?3q3J2q{21)q0%XL;X~ZqU
za00gyFBr)G$P9yAJtasE!@H#Yxdyog_F&jcT?YAhageOXd!(!L4e~P3JL4VGS9coZ
zb+EU=s$|sygM11+*nPrI`s}UQh`Bl?td6Z&Y>>BrKLj$Xk)NtP5;8?t9b50S2QvFA
zom>z8AnzJin%^w{*54)Nc%2V~%wb0MARAX2D|0{9J
zv>N1JFC2I`;%y6zUZ#^H
zfYp%K4)_Vu-x`Xg&OOKC8m`%#8uBf4
zGdIrTR~cbw9;D8{Ak(h`{CHTR@L3-S=!O<+;GH&U(2T_(&(coB{s>U9hnic&Q`mGb;Ak
z-g;RN8~_Xe9_gi*4ZsD!Kwu5{apf;t4Ee2qDx3_j^bm#sdrfg8T|bpZ90I+z#{-U*bE{-*yCYfeh|YV0XA%1Eb%9Uce6?
zgJ9{h2@v+tuH0$zkZ{eWY)p_uGfB^~;HTz^|MBe!YAJdLD(GoB5@$K|g_b
z$AbCPeL_y!%>=wjo^S5->s+g`FGIOdelCKXT#Y?Tv13@s#{MkA>S4b+U(d(>$6((z
zPuQ0d4|Jw^!yB+aa<8y2hyCnoy*$E$GYGI>Staa7*r&iAh4hYw{Y}WH^38z#yOsX9
z9EzPf@KD&*avz1duhxgH%l-Plx6E(vRO{zIu>@@c@=2d5r~?%CHQ0kSc0G91y0m_=
z2uu0D5$!$>{8TQ>kaksv5~N+_f3+HY7kJ(U&z5q%yaxGs1oqAU_ScQw=+D$T>6qiU
zAJNpw1dE@J;J#n)SA@)3P_DkDmp4K_)zv82>tTNr_IqCx_EoTtK%ct<^tQ0~ft}Jz
zW8eq&>E*qkXTg3mzpq~K=hdsI4=*DutrbOI7Wz;*Uhj7Z`Tr*PUkAfF$axQT((Pt`
zA3m>_PlJC9nB9s!1okMazYcGF&~Go;Bl3jW+R3?oyB&Jc{FwTXndnDVd!)wRfIdX6
zOS=~M)BBOlPnSWbuv8CUR>D$SIKNBuSL0z{@vL4x4<53&e?~9=r05SPe%C)U(~b>h
zv_7W(oVqv?&7RQzN=3#)(is~%UlU*mZ5@t66=8@|a0M8GxkuxYe|1g@$^FY0Z>_lh
z*!xG0r1p%;ov`%c=@lKHIRC)E))pp2ok%&j_4UbR_Z?_cajO4aMWK^6xQ3ma|5fkg
zx_@u(_OXA?<@L?E)cFZ~=Rd47ab1OCSR-l`)+Pw1X?iH-YAQlm
zBt!KN@;n`2S5!pQ>b=8SxDN$u+OFTGiGr7`O9ix*DLD7h^%?41w3oz8AO
zz54#8ru$p{`={7;k3Uj#vTw%SS6_S7DR1v-+!*4LI>vtW7CQ)87l=W74p{1c))!$pAj4lHU!GZ-@UO&{KhX-wBYz
zF$SA)BtUKp3_2Jf>o8_o2f7*P1=4(I3NR2j0vG}u0RB+m=~n{eHo%YG3Xt0Y^}zPP
zpf>~L4!~u94v-^(qktWOS6>T|I{~*NTxa0ha7O_bz}*G-2;5zPqfP|Kw*X7vjs{-*
zQ-ItJ*azbq0&pAnCj!TUe-d!#>j5$r@mLAylYyN;p8`yRdn)k!O98SScptaL)%;9}ST20-k}KyMgOLUkKa+z8YXD+>3zo;nqb!54iP&;12+Pehl>o
zxB?gmJcoJ^0+iuy4SX5yHo!H&FyKrejoA+&UL9(60^E9FKez*c(-4mV_yOvP3#%?;
zKMs)R0FMCa9N^+l0_4TeCmVcAfTzx&9zyP!1E`0sv#(*~)FErlXc%{d8ZO>i3
z{m1(nqnUvf|Jc~LaOj~%?GG1gv4h9nx_YX|o%g8C#}p)NxPC
zjT`?BSQF>Yi@M8fJ+rVoSQ2_QWTH-|rz3Y{z+%8lMB1|DcH-42z2AAdok2bg69y9n
z6CZ&!UzjUx4f0hOo)3>QiS~{1-%JDhsa2{z9aGpOT3$}hrpFWPDcJ%+gN3|^kUl7z
z4F+#A=E2}kN>Bo%7bfx&v)3cK~AEM-nq-Try
zKe>}q61mL5SUR9ZfFbEQiHWq7fH;SwC*>sZ6rlbg-B1&;A${;oh60pWl1(&PVL(38
zG6PG72jUiafs_pf?+_T$K0RBcArXpEwo=CNKNJobL|Lz7Bk~P$m3$bi>Y*rBx}}J`O-iAXL0lqRSs^l?hfm>bEE!J76f^}<
z6_}F!q$3prqgs=sq;D`UXp|X5Q0;*#Jnxbb0zd($Uj$=+h?sap6`1-5sE?U1w-vJB;vb%$1GZYN0*U)=tOvd}A^GaNU(6enrSn?aJiFb%5-k}nN2y^2=y
z%Bz$exhpmHs^~^M$V7dftCV#x^sJ5!VG%&81M@Vx&DZF5r$N+bsxu2Pz@$1!{C6q*
zN8r9&u@ilvrk>Ym=!-P;#Z1Vgy0HYWXh=7*)7Y2Fl_y`9|XvvQz%hSVgsCis7?|qplJ!#oZP@UYQ!ChD?
z=unr@*qme%KaI~-`Lu4V(%V4}=}tWDHTDi+;VfH`6B!)HsBIBXN4&tJ{xBczPKur4
z>a6G~gC3>Gr}TCSi)PalIbFlrGYi>K*0-o(VUO1EchjV?dvE}wIW)!FL*b#YlByf*
zJ@L|y`Wd3fVBs`Mk>5+VG_He#Z@
z05q~^MrE;D*h$ZT$WRug&<&b&wTg^n(F#38p;KSiT2o$O3Z3d|8?`J@_h_z0^?~YP
zTTR~{5!sRTR%Et|3}*3U2air8N3ZGtdVnV0Kqdc4haiRiH0o_DjA5vM*bBQlmLndT
z$C3`z#`T(K7R_hXx~e`es1Aoh{~h2ZecDO>ez?6P_`~4W0WYc|;ZHn~VSy}C;qR#F
zmt2}>?i`en1Rj#_M!fuou=Fe=8a>CVsSJQMKrFfN@eGY;c{+g<7cKs*fK`Q_)v2DqBfuEoo4{Vc_kaU{VL&>kcp8`hq;w<#DBdJs
z4lo%=Z6rmZ4^og0Ymxk+gvi%nK#KQ2fW$vS@gE614|g7r^v(x1z)fqcSAYdTl0)mK
zghfF5O@LVjH|<9xxzt#K5f7EuIkYn>FCF?tDzA%hQ+ZthQh6D`PfH4vJ}NIlDz6A2
zl~*K?$}0*;^OxR0DzA7Tm6slJ!+|Mq)B5`eAg?mWA1Xge2bG@@bSl3bAeA4LKb2cP
z+*EEefmCi5AkFz*K&&tD4R=es8|2b%26@#j2Dzjw_7GulkkZtlTl)yA13C%sC9y9>
z4?MKNAO`>)a0ddvdIbAgfSZ>ZWDEtEeHr$%0Har6e+$sK9Q$2>L*YLN_~t6?2?BQA
zfwc*s>q+b-0tVM(j}OoSd2NB~5l;kAdKi0xfcFC112=Cm$o+tJ_}>a#_mDx31NH{?
z1)kn)kOu%C0QLu#K4_3{BY(K#fyXu(o19k(>48r?V;1*yq@DeZuxU`jC&I2X{>*ai4
zpAfuX2KElcdskp;YrOXau2^S~y})=Ns(`3mtm!X+N{K2VGZ=LJKUw=qX2)l$1Mbkx#gvU?jKVJWp5cj@INMedg#$pfBk;-bB#}oI=yu6-?q2=
z<>G+{?zb%YHu=Jb@z3wRZP{No{drYwx5z~s=A1D7VdbO|i;omci#}Ix*jqRDQiq}!
z{uS2s-jB`2
z=j44bFQI&Jr(vdxCQ%KfAhyXVt)9-)2rw4z>iD+
zxkt8{C$@bo@xjimhQ~F{869;&{-2KB?sxDk`-jF&IryyK%`=p`5b@(q{rydxj6JCJ
zg`K)U{5Uf(hsM&F*;
zuUB+O+CcM3W&KkpquzVxft3#(wC}o)={~(QvTE|4g;B4{?_9cY0r9(|)KZYYBBd^xN}e
zpE^-5Jg)6efsXnlG}
zVkht4=05RxtAA`8nDu>eX4$7?SDS>)r?IGBA34NS^ECe>i)yOwDfpj&0WKsXO<@fw+?Ho
z*98TJhJ?3atqcJrUi)myqo_#Rho{aC3cY2)g*SP>BK|BSzvo`eI(+`4{a42%^mae>
zc?&
zuTC8HZM$zLZ(Dr(1Mkm>ern^+R;P4Rm$ZMSF0uD(cZE&xPJhLH^|_B~o(MYqkoVh%
z4j;BXbav_JS1ufT_;A}d9}Da4jQ_I#&RXx-(@*Z2_TjRhs|v=C+E{TcamVpn19rW>
zaPq0A8$SpRMxj|WL@aKTZi_%Wx$n+_;DTD3@t43gj!z;omDm9jaL`d
z#k(JP?A*bvca(PB;aYjetA7}8f4$4O2maDKXwwIEgTgPm>SslCI=rn*uzg7PoVnSz
zKL7Hrls#e5!^ZABm78~B%hd0k1IoWye4p28e!M!e`gm=y{`FP3X<^OR_WW%>{^93W
zzN?;dtnBlUS#{5pz2yGhF=F@+d5MLmM@%7D1%bZdr5!Ny15X
zD|`n?@|b*n+(C+U#bbLVf+z>Sa`H0La-_VXG{~a63P@%ljt*IIEknNB=ES+;d6IH_
z0Z6@IlwUdyU9<_k>FW@hF_QM;u%TqO+vsGu(~L8w6+9tI+6Hf4X2m9xIBSpMpHj3E0IU$Vh2Cz#PdqX*wwRi8afdrOYuA$!s6C)XQf-USKtl-Y*kf!
zl(VfAvxiqv9L&PeHgfax!Qu!gb6e@8nb2>x)s5r%l5*Tw8t!s>Y;?jb+lqtbbZNwJ
z98HwcmD?h4K3Ci`k-?8XR^sR$E`yNpA5101j@ceMUqgjEHP$jcb}&*jxKg@c(4pc_OBF^0!ZJuJhYvX-lrbAdKc#6xwVKtXK5!FDXVt|xM
z4jigAi~B9?^ArIh4Cm!>De`;-m+xG!gO1*MZhWxUV)MA{#i$vA87F&v8?bq3Izg-O
zG&#MSIQTzv)|Vd~LcRb~s(~Z%<9BQHNA1WEhcrDzM9K&XMWv#=$FVsN^2Th9#{p-T
zm5x;6iVx{OB!!*D_D>q*QF57R{CsUQndMfy3(+!M;D95$xP1ckTG-L3&_Kvf9CfBv
zCJ0n0MCXM=w}mK&NjVL-pb(nvPMod61uL+l%&EK;xtbaPKh#;&Ltouh>Liw;d3{w;
z5>*@gYMqAFXIFiB#TPQsRf~2&d~{}>P-!3B>GT$>Zn83OIX~WMsjP4@-uu~c2ohn+
zt<{`He|WbD8ZL(*qdFNKpd|SrvF4E2O7Wj6qFj((Xav2e!abh+fl^_WnVq9a?Lge4
zR?j5%7|c!>i6u-*E65!#mDo*C)a1q)Oh>8HM7Io}&gbS8`A>;i#Tij|Deu)sjf(Y5
zjkQ~*50}u-S>le3i|uBgi_+rbFLt@?
z^XN_-v$#n@eK>*1$D?@hiv{?d2cn&~?4PS1pS?D`;^hlRXMNqJUVD`qxwy)}=g)N`
zKXE;Vb2e$N(Orb+nI`UyK#D~we0L)FWaT%MI}zdl;D_QGhK3V0#KRKder1!CGsCK=~@A*mi*eFbaX+=ffZl8E%B8!Nxyn+
z2WcpzY0Jrh!}DsQugQIWOy8gW7V@7|ykXvxexe@vq9N@_lvbe|rYGwr(@hu1Xw&A4
zS4p?jLfOzs=FVOMn+l;5#MLN9XwM9)D`odnP?nz2xQo59q`Au?46CP#P
z#FNTT1mYP%dECTbn>S4h01sY%6-x`c2?^J>3XL9RsG!8Axobq+b0fv$$)MbH^Beq1
z6Tp>5+G^p~r%67ybn#J(S?v$+%WG|VL{9t4qlNm-?~l-?OZ0mVr$Y=}ePJtI77W(V
zS5rSi=btDUUK(I&yAnp!#KaQ6UJ602n!;Ju+`p`;zoWUoL-qIRgCkpzg|SPsHgSDD
z)oSOL&C3g?)6Mvsrzg+Hbw>fY%m&xfim146R?unz6
zb3s1cTITZ!8zj#u9My()!&y+Ui=u?`Q!+~wS5iI=iACkto~}$B#h$cQ2Ho;^}!8j+PrAu
z;fux}|Ml7~-4USlxxRRP{RQP>ld9ib9x}5=Lxv73E-~XmBjWVa($X`GnOU5MyO;)7)5sHZ
z7)fFivkFaVg@u^~MZ-&_o+G8)2{}3BS5@jU(YSg5))+8O@r}1M{KQH@`Z<(#MPY2@
zKp>7LcZtdCMv2gXn7HSbV@ZO0iIo7+c3O~$xeMM;m;>chOQ5_8Cfgb)N0tT3dx1eP
z^XM8u{s)q%+nxuxxEqZorJU@n^wJqzbrQsBbp4A
z%>74|TLzTcFexy(N-QRq*Ns`8lt6PUkJ%pra~zCrtr~*cT4u6Ys-+PlCBFXdsIDkB
z)1v@?lj$xTuhoPuwKT3T1xjLC|D@mWPy7x4gckgZ`E42|OrNY}ba~|nDOWZX$>U8K
zxkZ#esdwbCn%eHH1_$d>+XS#UZ@H!aC_KiB`B7m?cpqGUm5|t1WB^UmD3dfvW^v*=
z&k@ocnM%guHCCTK(rhbTzX5K$dn#v{KA^PHfeNYosta_yj8-fcWu?-u+#}qpyaH1d
zRQ-2V33{hRO~a}FzZaiY^!UBu{WmeE_JYieg%4
zK^PvDjW;H|+kFCil3*4*OLsr$cven>n=JIzmf!oEnvs_)6=Y^iM`ssL|CKS%R9ql4
zU7A{0lvXqWH_T2oP8gRz9o-iCPE_lpl=Ot5i9?6dB-}3ZzqqjucIB_=-?Y5LeuJ0m
zfdy02gF;WGPFQhFrC|f?q#8=nY_hrMsJBLWrji5sHQiTKH=PBMTLa}dn41ppI~W}+
z1Lf$q`Tw%H67iN_$BsLdL=w-ct5MG
zR9@2$W=}FHi$?gqjIR}WtKFp*E7l%u4s_CH`)p~%2x%y~u4`jU&dN$iP-AN<17kRw
z;~FuEEy>Bs${@vClH+bkm!yPimEoFbgdoG3>cdrWmpUEVR3)|`2|~C+sya>NAVcVm
z-)qv0YT%xpTA{kl^wEJlIAb!n@I}>4Cp&d
zMR}$>GAGC3*;$Y|F0Uw)6VZW6{UtmZ(W8p`hc3=E+d7Z>JdC6))@tQh-?WV2>nfk;
zz>Es@EotzzWt_;XiNB(tjBilCF);Dh@3f3$iEe^+)A)%7G`!bEpM%#I+@MeD8AnU9
zZWCTfS!lM}N6JpiF{NcBn2N@X%PcUZk166K)$8#k-XverP4T5?$x(
z4(c}j3CWew-XBg0j|rRkHKR>L7tjR
z*X4s6$WNh&F*D8hTY7*W`TD!~k-xu-Kl%6Y^J2M1JnGJM@|^NLKYQ|+EYpNsBeJq!
zLathot{VpYl$pQDhw{uu7D6f&t0p(8E?-9aY}yM`$E6
z4W|2pO`lC5UGuYmKai*f?2%d@$j_-x1k(A`lfWS0ZXn$iG60Ba8Sb(6@)aWwUf8Jj
ze#T3f$+F5_WJ&$
z-@EOXq!HrOW-14EhUVF+@ANvy>FdV}WGp{z0{!Haw5N9N+&RlJERFKmQ*J9oD&~%a
zQt^^)4#oy1o7ORh9Aa#UJ6kiRJMkKge=fjj<|7crui2~gYn&1VmS{vO;TcmB~v*_~=lrhMR<`of`5ns{n;L7J5|a&0)2HN;k#
zoitONgQ|*_aZsKyohs@Cbj4#0PE4DzWdP
zXTJJ6$5MjpoblBO+K5o;wu&!5pd+;iA6jE*LKF4Bm_Ad1ZVj8Ogaz%>RADW4h#rnJ
zfd@MrirwaN|1O^be8z)zAkqFMN_;_v-#Niyt;Vh9wDZP1S7}W-xMbB~cJrIbF@Zz#
zkP;JayG_~uBy=gN#*PcO8?TL^sM~Fdwcu7mu03v#YeEtH{Ot~3*H_*mOV(#
zPx)I7o4L9f1$zvt>8%$&PeSiW_{%S(f#0)@g=o;}wFtUvH#QYm=mHV)qRePYLu2FV
zEv}+Ziuj7Q8Icq_Kb}^Ozf{(Zc{ObEr+)jH?Ps2DLi&H&@%8qkC+0nI=!xJRc{|qc
z_~(w^PtJaF_me+AnY#0yo$u`I^wjjHwmtRrQ%O(H`~Ogy{-4fpjdIJE1xL1P*DiAN
zrY?~&F)@)(?d%tsoSYo_@=N~_X*3!m-+D7A5~HKYkN!D5vb3}`^1?Tc$hmXpMxqal
zT)u1>!rqUtn-F#@!tO-aJ@C`vgejfYxYF2wzpCq}#?Ljbi;brhS6j|`Qserm@wmoy
zvGEnfMMKXkje9k&pBi^+To)Vbxhn{#hZ*~|alOX%bK@$F>xah0+|`N(>g;M`wZ?@n
zm}y*>8ZF#K-<&3yQ#7uh8}l`;9~$ZPjE)8Jn=gK9r1Lte>tbV)#?{bB8~y3-VcM4T
zOCy~yQe8hbA_IM{@9~8=Aw>uLk?$!cndJJu@eq6ss?h4?3mm5FPxGpuGf-4AN
zC=FzYiQ;Zf!;bs^F`5l=&w-)tUFqGK`1S*yZIZUr7jq8k!NHEX5xxTEE|o0wEiq+2
zqC77(;paNtv(?#^@+l2`&Vs_@VW6^W_#sfCN^uw;DYuf)qKLQJ_st1>f1udmsX+W7
z(bqq`*bqQ6RUZ1f1i$O_I*j5O;Pb?m0O*E!AidnB?_SZj6NC(UerWh`+rO5NzK_)+
zpQ9-seJg|bFaqWl`r{LeIE(prFt}FGo8nZyIpF5sC@ZeSPE7UAR>3P?#<}on)6a^K
z*ceIM6tw{azuAr=Qod{DligwfRTp0#-k6=?2}*B%u`|*IyBIr(y(mP&$D;TyTAYQV
z&t>^pZ@^1$ANi|gMx!iE5bjnsx-=0E+09w6$LkZ0Ff?Tr0|>m_#J9c}?e)@*C{$*5
zHO+fbr{IqoihG2G+s!A`<>I|QA6?LNaf|&3-lqCteN*TsW==vsG5Tp)Kfx#TyAB`s6nsKIe;|B(?yat}A`}lZ*Nz?R&;u0g
zP*nYSCN%LE*}}Xovx&>5aB93_3nJfb#7B>m4wVnpk;}n|Q`Bw2fe$|63pw~mB7R~A
zRQWujiSHvpH}WSB_|L~1eUF!R>tX(l;|UbT%J+av$_@)^;e0z^6JFY8j9u7#JbMkJ
zBA2=q^cqUvp>kDoIZBrUKlC|%FY?2ryM=IW9u9s&ah@*Jcq)=g)I1TcNq^$=w74w%
zON1r3EZyXEFt{b!Za{AAA|$uQpI4P;JU*JA&s|AH)Ra%5sVg$r41_5$&TA4#m?81{
zBjJSuR`NgxAI-MJgbQg%Gh+2816v%5J$T6Z{HY%!8u!oVHNnTiJm~n5V@!NVZZ5t$
zhuA7;k39LHy$XLsWZ`9tkHp}uKT)Z_z*0#m?lvb+d}D*s!`r%edOAc$q0F^-Kf<4?
zobFM+u_oH3pI&|)y2?*W7{et?RatQYRvO4f6GW_Vf|A&TB3i4KNAxEeCa7j9#VG|#
zS%L|ZBt=qLqSle5Iz&2L=HZeTTfFK0G|j#!b7{$h2PZvLQOcT~yL7lzh7B7fSmq){
zh23YZfE2!Ziwi~iGxxkI=q8*6>+AcpM=#}sW~lebVf7Uoha8BGxq<`*&@V>WW;z%Elu3CZiH@7
z@l{;-ik8Ewkg%pp>$y0Cq>(_ARNF>dvJ{)Uq(re<$~3&#>P~A1iWgpg
zyNlP~gkZPaVAAI#yzdLGsmVv{U%BntUhCdHv9Q^ogE%>`iP4hNIa!^2^r
z4`lWo$osT7tAm<{$7<&!TDzCx@YE+h$yJVONW2((&&8f7ydO~86LLht2Un%o0ZFC2
zHNnLl$U%Bc&2{@V)Q;k5OBtllp{96=-c>5^Dn#FjV-ce7M88Jw{djROb>Z$>9`3`L
z)CIk3dAJYf;R}7ppKE!@N5lngzT$T+kKzNiB3Ud7w!}j|Bq=MeAS2V1mqoL~W_)OV
zA}-O-VT`5@+LR7c>EEcQ6jluSMDK%Vb~RS%l!J4$rcFZ%wWmx>OqBYM5}ocy(V;3G
zuFvHzRji~z^Y94?n(!XpX{+H?*KdSR@W-!);2r)*)rIiFO7S;eb*B!CI$?Tcq1wf3
z3ZJW_M9C7cp~Fe?<;%5e_z6RjlLkw@L_Um6pdKB9M-CwimpU?;TOo2}l4465IT(t0
z6~z)o4{xV4d(q4RZw
z=JWO@iD|n3C@H~WE2Acd9e@e6>*sn~j}nIXw^32QNKJ&+YkY`l43QWF%{E!=d<{#?
zi6mF0*-b-gv4Ig!ZOt1*F%-pOkMe?3<>F<<-(ge#%tyuaFh<9LwXHI%)IVkD-M1yB
z#CvAj#2A#fH%xK)Sv0Xz5_?xM>r+O%P?QFoeKC{}GZEfe`HspK`FJyi7QXc%Wf#4F
z{YMZ~H?2yk=M1UGllrA_GKp`h*^(fINDp{>iEYbila_8%;nU3NTjdHo_1)pa5f3T8zn
zO$6NHWi1y7w^MXQ#H#$>yN1
zxit!7ji3xC9mM*W@S`0b7!&yx68$WGe;f8|pOS!)-Z5i9ywXxBdtmBur?9ijpEA8^`6HZmfdf(}1*_9v0k<
zf)zFNampx!LA$HGnnDNI4Onf0qHC(O4#GN!atDV%e&Y|hKspiX9+rq870UhJ8rli*-NqG
zO0!XY6nj#jArjMO!+lblxZ4o!(c~`KZ6hNM1J*^t4!zp4v_$xGJGR?_$AGj*givc}
zqMk)$7~c(M5=+H9#j~ln9*#-)HfAJilX|=&GK1^Q(?ID4pKhp5$3|hk8QiL#+eeOp
z{X&g?XhcMp9yw$W3C+&KHE%G%_(p^@9&rI@PG-9jCb87G32;9f77CMeXzaqS)7Y7?w?)3Uy6|myRSiA@gM5Wa!XO8EjJ!v_E`VITr%XUOBrOD;
z?3DL-qf7agpvOIFb&7osbXx}d1-)Tt&n|I2RwAr3G<4_|iN)MY_SQjhYdDQ1AZ*%N
z@H#^w58F!Dlf5;oc?kMHVvKOX*dIe0oNW;|(y)#E$&NJm>_`LIFSJgI+YY%GT66!N
zPYPLQo-=+pZ!hHSGe&q1KpwCf==u}nwhe&pETHed!OQK4<2BXJbbdPG^V3=1LkbV&
z6ViaN>#Hd(Z{b=^_yxaZj9AlFZ&~&Mu08x3cDRH8YK&NiZ4-!FS=ag{twa2nUy&|O
z?;y$y;S6otBP}RXd>60h3BJdS~Pc_quirBbq^E(K$4Y;j?ZRSii`K2Wtg?S11Qb$gE
zc}b_qFTd%
zzJ_ii+U_OcTH~BPoyjNGMoiKeUJqVGz2F9Qo87d23dF)1cz)VJZ$jqWL
zYDROEBJbbGjv!NvILOSHG=vpwM45AgGT(?eCX8S?3r7TvgUMA)`J_=SZ&_+kzQ)WN
z(Vc1CWOqzM``Db_YLdpdZkL$WP4=SvAuQ)lL&C`1@h2xYoc0Q6Fn7EH8q8$kYeusU
z>BjXV9aUqRFpA|rk{V7X?~x_kSSDUeD<9gOr-Ra>8cK(1SJ8o2ZlourMKzQT)vjV@
zYAPFXkF)K6z>K)(9&YlwbYUZw!OhJw;Ig)pyLTtPFs-rn>cygLBZ7OtMA^o3BS%HC
zk@ZX33sVoQZ*S?*gN=N2Nx0V7DD0fnkRC8mb0%^_^{RVuYLM1ALF=+GJG3WEmxaaL
zP+jX$k=;sb78mtq&WFad(wfy1Ze^qEZf!MQF~jNxwR&J;UzWYDU*H6oLYQIeh6S#h
z(wF7l)h|$M9-0=*^EHG?xBwG7tw9v0o(kxCHNO*k>LuDT;l-hoCLyyjvPRS6%7FIg=1u3y14z4e>mQ1;a63#fp$x|v%)&igVzpoaTUZsuhWSaA(b|}
zWuV87?HNe}Y4ahji7;CS7QqiI@HWRlx7Cgv9@hSDo5x($KVjei2%z&6135wb?T>dd
zc3a6n1z&iBaY&K#)51;S*QL|MFCKX|;MEap3UHQUW{`XdcZ;8c
zJq7lqVfZ#|VUU~+`xek6VV7agZiDZ11HCXOV4n$kE$qj^Q?oiqUIw%KvO!MWhi~Y>
z9{)4$Rlhe#-UfU5PX>7}@MV~{e>BMN0#Cv8YcR-Xf#+ckfX=`l4AUO=D4+y$`I13S
z0FHq91oj+Y5zGnLEkHX=5bV{!1u)0IHOTd2p%3g2d}ol?ZGb+o@Bbcj;0~Cv;Mq$w
znB&l)es7TcG)zompnL@QE{wM$&X54l!<^IOZvE%+9Rrxu02p8nOi4_TYyrApLVH7(
zB7A!m_5(c-50LCDx&+C)pwC{|zXJVTAlZq|?g)}k!`@X2l79k{o#=)aaMlHe?9sqD
zm>rQQ17H!%=biDrC15Sgnhx*-?uGdT_EW&KF!f=OkFtn>No|9&1sY*Kgnb&&MecBf
z2X2Ge4ExK#BQSlC-uHlKV7mVpC|>~v@5i^dVDAk~fZ1=rcM=qPZ6IXAZh^7ukaxfu
zm|XC00q!6=>_>p_!dwCWdEiel$AfUD=S6&z2PXbXpqv660dxLRpqvAgVd8!Yl_E`wa4&d7dFe_k>2abUG2J&T~1!iUl
zbOzSItU~#&0d9dwzZ@w4pZ2~5s);OH`&1=WMFBrcO
zyN*>JV^u4|5WeHsaKq}@HkZsuAz>h-$}nbURl4>4CObPi9%p&ndK|MDqLHej@eyaI
zWE9KgH_)BCoQ;g!Vn{$I8X#qts*xd_jEUsJ+iC416k&S+}31A0QAmd6?6GR-XhuPOvmL9ff%8WGP3
zG-}?SQsa{7$pmOdo02fc*a|fp&j{prk)MY&h`oApu)2bF$6A{rB7&mtE1+)6R{Zan
zpkMwOF6a6%#9I!W;sl$O9u}Gp;
zZcBA(XWb*DSYwWgqD;vGltn`sP7k8qvBF<{zwQRr}@(eD=
zd>(b7MeW1i#NDU@G4=)i
z#;Fx&xm@t{?PVb@+gl0W<_6hbMvP^`H`n`oI>4oBqSc0)ql-;E5h}R#EFEdWl3QYaAi^`|fn0_M=-ITO=w`sX{>z5~TVYw(hWcicug02wzlfF8un9Km1fF-SQ9B@%a?h`i*
zrjmqk2W#HrQW)z$akuuNMm!K8W&SfMM_t3|cDNt*NvAstoHsqj(gD?Ph#(An+J$37
zTta*IQ#;+}un9!4rb@*6T-q7BI@XKzNVg)P#K4i!N?ey$MXc93k}tfc-+5us=+Ufi`1KM!PNI|79E0?RO2{j=Gn2?k#>&wm+{1%h3%~9t8c9%Vw+}=xOgm1uP*Y^xb`EfF-0G;A!nc11v$84y@Ii
zE-mx$F%BINv|&%XaA*(EkSO0C*Q*dUi~~gJXAw1&zo(BXZuA>8IqKJqei&6t5u=#<
z9Il2YjB9eEPo7)QKRl1?##iFH@TIs;{daJU8rI<_BHQ{RviwVtJs|*Mp?@W^!LLF#
zx(C@kJ;>(wAe-+Rw?=(KbA4LvZ>+Iav!TSc3WXZ!n`u{PTp4TAY;QsrKeDiT*(wwT
zn}fHRq;qLiPWjfPsYz5?Xi}_|3osDE5fqV@;pC~s)A%MdY8|1E1PeMps-gMebTz+p
z=H;0wb4%u`=S41&Mg_XsVoZ=(4138BQLL48pO|Q2uaK1Cp)NkO4VAD<_38HbgaU*u
z4@;MJby{t#t;9Cc8VYl!RfxW+xqj3NC9T&&$(oF69!9UlO=#-}Y1=KV6=c;^VM%#5
zif%zpc~E%pSUxq4e^(3g$`c4eKdwMU>FBPIrsi%-Lu+3tv5XtnsIP#TY6hVYa~E
zHE4^iinF{P+d)dIhQBP1YtYvLCfflMH9uTiBUlW%5Vj{+^kb+v_T(Llv4Z5;(mW4>
zKH$$dHI>SlG)mt1Au=1(d~_mjRMD3Z58;Fa=!q#AyPb?P9=UB{D@bKtBV8JHA6;@J
zxz+r*iK#7p%UhiY{d-U8UGdPTP$g_6v=As$U%LGc>dJN=4nfBS%xh0p>6{L6URM8U
zUb|Tz?ds1sndZRKyhh}#?C5TB#OK|Gk#?@jb`PijG^=z+JDTMf@184Y+^K>^4?H%P
zUdcnw*4DuM?9wq?QOya-4%4pEH>cIkxDsm}Y1^AvY>m7x)p-+|J_jU5cJ^}y>J(nQ
zh3yfzBWT}5Zgpv9jBF{BWBi=Cgvjb*W{>5XBk9~KG(3(-6o*&Hx
zCJ-;mc$+y7(p~aO_uH#rZy?6b)zF$jx{8-b$1Ob?uyIY=#c9=%t52?0U(sBiac*|iyfcg3ODpKwV(Un2T(;AH
zAX51^2db1Xa|w4U5!n@PsT@OCPFJA#%q==@6HAqD7(?VXIboEuJBk^uvypVpk`o$U
zp*^`WX*F7Tfr^=_0%d^wEQPWJHt0zG
zvwel;a@xfv^yLT(J5+Ab%jLL#iUNC$QnVloJ4P-`4UvyP!A9I)B|*RPWfafemP3Da
zF3K;Gz`a#c6?7(`Ur!|1$-&$FmN
z|M|MbunhDb<_GN~+`_H}E|>#u%b;&9=7KpaTvJ%F@6@!Lxcm~E*rNQ#y2n>!xU0&N
zY)vRAj52^E=hbY9@zNcc(MrfBZzp61+}@&K16#F@B0mpof!9oKJekAdkkgZa7Jlr^
z%OK*eB-OTs;2wuJaQAXy%^QML?J+3ywzDk^$&7bommY9R%CBTj3cc{-xLV#|VOt2E
z!CaycAsc^rl^++P@Na7V@$I8Jjedvz;oLNyPF(_W!)h$Q6?jyDJXeS)B8NO8^fPk1
zpm#Ff0a_~&g}D$dWR45gXkuD9DVrQZ;|x1)7b$5?5ZPjARJ$)%WK`FlT6A;ijTP75zxvO$W4DaAeGM32MAz;?&qr8{+X+jWT&yQM
z>-@o=aX*<&BDG%o_
zU2u6p%EFR`(Y+Y66(AX4tjIxjp&!fbx&tG?9iRcm-j;R%uY)nhtek{#jl^k(xPn>A
zQ2*JTM>2LOPyuCc>d~(HLCRJqxFq%nx0&MtXZ4r=oORCGf=)x9>kQih^W>!Jc{v_R7+Db;eEp;G61C)VtLAi9%_ko=7@(3p^kw
zNF_%>Ekf6j`cL{jQ5Yg!lATwT;Zd#x<{5b8n0><+d2Y4lDak652K)gF2CBHmZN|Cv#xc><`wj1#~gWOBLo+l~TEwdgszR8~1Mv
zS8co&$Po&dok%uIr#_s!bl&B8Df3I_s~2orKrY1g3oVk6r7jZ@w6VCiTJ2Ipn|Cy=
zZnLl$$vY_CJ|P*8h4CG&WGz3B&v(QNMTCkCL&{GZb?;{+M{!Dj(&@3H(#9Cj+?i)3
zl3;v$zv{c~-{pVzNmFy+PGTzN+Vm~w&lB}^8y^#fgF@-bd>9FD;jxWws_Xs^%9BHR
za;l#+^5)6v+l#u)uznRPhaz=_<`nG~)>3%g->j{OMo|T=CMRQU#&?z6+7fJNs{0Jq
zo_ls6A96Dp&%QPS>>6S4fx3_u)oh>Gx-K#vxz
z2l$%mTo;5!ImRtQyPk@$8D%lFsVmG}8J<=Dy65SOn&TSTxCW2jc&x#*0lF4?d|RCD
zs1Y?W_bu4M0i?;O;xP|by>Hxmm@180qMyn-k}u)MW{C52y&Tci
zV{KrIb$G6HVzYBY2kHz{YS|!M#x;kxlx|6akFs;vUm&xQGVbHmeCpd(nJVy5`Qjky
zHqaxa69K;~zLg(gprF+e!D(l-3M5YtpHUINF`5{;Wi0;{PgkqYX{x5VXP+8t{mNRh
z1!TTnY|~^EO7eTaZ~NZtjMC-D(F}g{&}lq=0=8P~<6V-fPTQ6ym4Gcn^ibA)_Wz^M
z7cfpp9=@N|eR~O81+IzklRv9_FRMa7K)HZTU35*Y)
zQv_P4t;(2|@l#l(BqWBOEw=XR>sbWQw5t}qPm14ciOV{gHGa$2q8y>x>Wmqp
z949tUoe+99)>i!-@;`oz<)E~9K7Dy6UV(0#N6vpZC5=y+i)a4VGiGP(;}>PBdH(GZ
z1LOyOYX0U43YJpy@F!Ik+=mN*-qft3LI;M)e~!aO3IprOR4E81>#VG7~fur2sU`Xa&ns~%iU(;nRw=^
zuAaL36#M3-xhh?YTlGkHTt%$)^FRXSMaafBn(BUC43^YFoQN+m6dKL!$P9ul5+IWg8MGqe!76EwV(esM8a507W>cwV@1&C9u(iX^U)6JF%HH)84piR-u?u4wPe
zx%QP*S19qkG`hqT1T#!W;Xp
zSJ#fTQK!vp80rhB*t`H%MeC>o`;YQ*{81P~VElCU
z_Bfwy)k2S>$t=uJ(Ph*-D3aPU7WX;e>#6(p<6vXnY573HhClhRSc(5DgY
zEVr$Q#C%7fG(H#hyxOO)m{~j1IQQsW1=J|d)c?QAcFOQT$Z-i7#~!E*ZQTS5*u-(6
zpe4jMnX)PyOo{eAtm+q`h%$3BKa^naf_}auu&aY&Zn;Kg6hohQR)F7n!X6I3Qs6Sc
zg@1sGuUEw>c!sZj-iwAizO-<`S#KmKh>0umyJept;l8{H5tR`$uF_;2QW8pH0`WWa
zPsI1+_ar$TZy*tHD4igFMNqJtPr$+Tx4I*`H^@jGT+Lev9eojI?e|PFIK2KJ;o1CB
zo^yv;jywzRMBWEjdk&$!{c^1zXc@lu9yf2=w;yHr&QvRi!LJ`wK
z20T+oFY^2gb<``TkLNuT$cc!=zop)vm9x7?cOTD)X;ANd@jT_j^DXiPTLSX|8|<|u
z5zoEdWeAaQ1^Ia1GrftPsrSEvrzmGAW{&Hqm*-aEp3GNAO*;Ia)(|>2gj6@_ATfN(
zUdQ2qeZqspaL8ax4;RC$aCotlS4_XSPu|6S@-7bR&AYe{pAY+_|F93;)F-d0mwv`8
z=f6U^XS{MsVJZDGkpGNMDoYAWdBw0-PBFb#PAM$qmBLb9DJY$U
zUWZ2IXUcsRJla5bhd<6b~7lqGBz@FSC*ct1^bfmS|ws&HzZI-qN
zPb{M&z&GC0^sH}YFB&@%d4gx>@&T?Tr8ikSEosu5b;!u23
zpN-LYQ>)?gfzz|vi@L+EG;ruRcoWVwY*iSzzz!rZ%zeVZ`9o+9rZdxn4V
zWf$yLO6es;d%q#Ssv`zZA?
zwa_jwC%e1C((R|HsrIPCeVbL-k8$y%o4&c2z!3O!#Aao}@(*Cm$C_En=v?0s$Tb{A
zD)2nQ4#dE_=>ErMH_za?4aJ-n_m6R{7F$1O2qa{JbyF=!_C@CZZMyi``F;&D7W`>&
znxQK!$9T)ZQE-Cf!ChoCa>zs40Ur+yDE0Rsv);Tv*T^Y6biT3vHP6#XY&92;7lh;c
zjnd3UQpM=rIB3BkVc?hbF#j5(&D#kxMP}94JGdntxs%b+rB_->I6cIaT3bnM^}Zde
zXv}4?#HAqcpydPCa7?M_5=8!U4T9iadk=W7{d!0JTF(=qeeZpU>5t~sFY9RU<=jjy
ze6_~w0n4u=Z#}0m>G9|4?vkJ}8l$1r{xfmj
z;;TPxqpA|Zhc*0HdA|BDh32IUZBAJSd&SXGTGJ($Ry$e>U%Vx#7*hbQeJw*`i#c)L
zGRvinX+OMKRRbD+0=I6WL0dCGH5#8`3TcDBF!%_jLh5xk
z1*A491YfA(I1!93pRUI3py}ebpN2oMfbEB~+^P-~79$_4Vv71J4IQwTitAjvd?^VW
z3eLNT`?$B;Jt<2l8g`)k11KNX%)t$EA2oBR`FlLRK+BBAeM63m%P)d9<)cLV9dK!R
zPZ)61*^diz?h(*~nUZ+y<-@6Hx4J_11rrTAJSjq|wXGlJPo(7Wvv|_ySBYE>c`u%K
zg*V`SZ1;RVYfpJUNsb_pqYNG7Nw+O=quA8gAg&~H91WCU8f&%sc
z8hdJ#vKiv@VZQ)c^w!4K-g*v|ADECR_+$+gf(;83q`Ijbuaf=r+@tUUyT{?!QDUJq>%Ezo|u1^=LPk?=pOVQ)^YoI_|3vW_-#P(U%sT@xA?xnCxMdxaZ)P$M}}8^{?c>!2NaOE+|}J(
z2EU^5^?PSZNcCHPfHxi;mZ?8f`lym$@TUs+e?bZq4F8g@=kqqRCI&kN#k(ASoG*Uh
zanP5HBrQVtjyaXhB!*#cz&#tOZiWjTu8`w*#=`IIdpL38;KS?>
z?-zJBE`wAIg8$Hg9>F^Y@QRZ`gT>fg_{Om}#MljQOiFp#8^ivC-gge*^YM>*-Z>B~
z#twT^2EhGk&pQWj?1%0G?=yfHp6%!p`@#Fp0S3y)&#-1#799J*`_2Jcj6L?gbAST9
z5bE^4b3hI{qpu(SI(GVZ_xtajvS`lGb9;oj$1=O?(${JxA3y!)Yx^q>)#L;dDFNeZ
zzRde{*p-L7zUW%EoX#G;<7wfVsegVn^1a{poA;B@VQp)f>geD8uK{;2{(i&_kOn?K
MBGuja{x^L74V~{e6#xJL

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_v0.56.bin b/bsp/bouffalo_lab/bl808/builtin_imgs/mfg_bl808_gu_7c2526e09_v0.56.bin
new file mode 100755
index 0000000000000000000000000000000000000000..d4bbe28abcb001d2789c238fbc62852c0b36a1f7
GIT binary patch
literal 468448
zcmeFa4_s7L{y%)~%-nki6vZwu_^%KWi``uH7PRgz%>Xl_qemS=^<$Rj`o))
zK;NtmAuXjvlm;4-_V6z-`*Ay>#?MB{Z&NtMS2FVgMY1DBY;dDbSC!5lFpl!QV?I5AZ{+)P&>tD^xeofC>!9zs4*H(!
zpihAMq<;bUtX{*FYkK5;uMqvvft=jdkEZ`rKZ^W!>IV(_p+{SOePh~x(>K+rd&7zD
z{e0hB%QC-J`UVO8Pw2k0@8+MOTZ{UARjSZ^|9{AnJNy1Qy0vKRjITETgeM38dwxe~
zcl9Xh9jMr&HE({l{J-h@U(+3eZcce3?(^+#t}0IePG4MS<$i*)xpzW+k#k(kQBEGU`L;(elO0
z_NHMQe=Q0b#((%6efg&*)Mt7V8vduI;E7|XB1l*M{eKY%^7^}<|C$H?KBw>2{6CNb
z31cQ%CYUCf{tukm-6`GWz+Dd9<-lDI+~vSs4&3FyT@Kvkz+Dd9<-lDI+~vSs4&3Fy
zT@Kvkz+Dd9<-lDI+~vSs4&3FyT@Kvk!2j03nToIj{i^Og7x>v@yO-sD@R+8->hvv(bOCgc{LIZD>!A_
zP+q5fPlIS}RM9iY^^E4QZNrk3sG>+Te{jUZZcTc+xa5kTUoaV69US~HH>HJ|STS^;
zs0l{x8qPKk;r_FAu6d+YWP$cQ>P*`VTa*@QhbF>Ff}>Q_h6*aGXdZISV-WOvPRgB!
z__DW<)cZ0O6>*G;io8l0USW`S5G6M?e;hXaP*d}hQJ)m4W#wn)M@2l$&A<9spjKRx
zVO+D)29z!le^-=858d}+0`5B*sWk_E+thsgzP?+oMn*h5KPvd)t5IlJO&R&tQr0=c
zG>**BfHjA;QFyd=kQOaTn7`tlhifOzU!fUBX3H&Td911V)q7SNHzbTmtVo=cbT(<8
zdCBB^rfirpBBdf_($uq4=S{PZ4olvY9Q%0H<5R{oj9EC=K0R#4rWvt+sQLq}2shFLJPLFK>En3fp-8|rH(t=AAvY)ByUSd#v~
zdItZ~{)zmGSLXRSZF=}UTIuXF=#|i@h{@#a%gx~OL2yqa5qN|h8s!O%+U}_-dnL4I
z`I7YiuNw=o)@(BM5nEdqGgVwx*uKw4ZF9sp@L|0ckI^%3CK$Da@h2FQv~U+Xl)L_H
ziE*T`SBPU#`VFVPVoU{PCErcdl5|l&Oe>e`{b^H0d+lCn$_d0@--Kkn{+3wP>gRo%
z(C{K|)OEkKXcwZa;T2C;?6r@yH$|jBRbq^BY;$z>Q(|;8DE(3{W!6_bST
zNR#Kpqnlx6n0Cs_*K9<)g(c~{w-WJ_E0L7ng2v{wx$mqiDs`pMooFPfYasPV{T6fx
z>XxVCg)JJ9ZSF0(H=|sZgE0m=$y1jBMs%ba-S~Fxzs3pibhgg5t8Wb#&tPT
zFX(M5{)&OJeMn-ejf7k4a(QN-u_P*+cP6gJw6-
zeFW$h*-pBTfUE)C`3yBZXN`aZ^d0Lo6V{2Ri$D_GAPFX`{N43yv#c3qQsH^T*R&{n
z?c}w1T2Ju}ZX~7DXjLBbi)ysoWQK~j5pE^0qn-FoFVM=_I%)MH&PHgJ7_X7{)oK$M
z(-Nr`uB_y!(MYpBDAs{*wV>2VTbvP_>h3!~V)Z6UGbX1ajKu-gy3gwBE`;(Tdh6
z+PSwt<-HfQ(+k=;8%a~X1?>dBHI^bibS~mRdZfu7tt#na3Qb81Jz9w_1u3s_;_GhE
zOGmj>NWV@M|r|l8ruQ&R#nPM
zHR6I)4L(x*Sl${f(GFbZ_*G{`{;
zP#$_8rRdhZVHCgcvR29ur9O9xV2#Q%I4?`_GcJQ=m3`fKX5D-J5$+tZMI4PlI;tRqS2tI|)qr-08Uzz1PU)
z`u+UkDvI-hzAfR~k5Cf(g_iGCrR94!X^7RF_b#F34Hus8q24OsX0X(}0@F)r_wtK8
z6xb`DhuZDJ4V4JL4WHLrkd*5+Np3ILfq}WL4vB3s@{hEjyqxSDUIcqmW1#ri?;)us
zloF)ktZj}FS+Rn}h6|VoRi~;vicY2C1r32jBKbHE>c#St8&I*LQyh&nv0yptjkpKc
zsC+L-30URuT67XdIDy2eATPC{S}u(E4lzYb@xD-PtRT^~9sbUZDqNgE>?#X()r~lz
z!C#^1mO-1K<(|-jw}CsB$Eo0-TQ%`^{O4mRLF9<9nWF`NcMN=Fqd$S3n3G`!Z$~RW
zV(upJ5k#kGD?imkbZT*@PO;P=GoP{rbV>`}jstHO12bqa;?M@YAfArz1r>1a1S>#7+X$3p^ADb}|80-(!*%b<)kJKpU2q3Ed5vk)3oi-RNdi
zy45(vWR_>2Z=Ge%ck|&8$JI0QU@|4iT&+&oX57mkWh#qVrcr|`EEi
zmlq|tL>erps)r^nOrXnOnwTTn
z+x^^>UKBSKY$!yZ{QMduEj*3*UdJ>Nb3#L69$vd&6D#&}@%n=rJl~5J7K&3?Dz*^U
zv08Z*d$K&W&5-5<&b|fuUbqX*b7h$2Yv<3Vg?=bym?`t{Ju$WsS)~r}SoxhEt051!
zRtACi9m
z0ep%ZEHKzLwgK#K1F9&%^$b{5a<@8H@|CLAzZQHN3)Y{h1&>vO62N28;IYVED0r+;
zD#Hx%mTEJf3-g_^e(3I|OY^&Q3H(zE@lRTaf8!MoD`k0%c(n)o6KxWwKy;!=EAdZ!
zhkr_7!Hx>xpI&o=yyDp)ck{^|_#%kFy8IKVBN|wU2Qhf4P8!J_c&M_DXlWMlP&>=`
z@Nlp+l}JnhJ@K`IhYF?mDf`jbTrrfy+Jsx&6A(Mqwu0s1Q$Z^sYQe7&jZrBecdDj9
z4J8I7HAyWJ1LEs7r~*6`aOoy|Isq{syj0KW^{-kAZKL#P
zZ=n)*WEo7jz@Sw<)PC?#`xOuMUZ;oJ6W8IPm<|sWMo9%A`@hAila6zAtP9
z-vn}+!V&)jkr|nrmLids;>Sb9q}mu{XEopeqHc%vXVC&rxLlN`YjbW8|+kXrrWX$s=7(Z1Mj91Y*9<-%Ty~s2##sg|&e!YdGTm969_`=-u$6-1#?}
zflPEU*0x5+vFZLagP0PI7C5=r!V!O-g&F&(OB+O*ZWr|sC4t?hELacH#2_6{Z!+=)
zo4^i(RCSC)nV&D?&#T{S%F+(;cELF4JP-Lsp9{)3;DKWu6%I@@##zOp9{l!dJy=$L
z7fbCfs3?ffs@%!ZKu_oJkMmG>h}Dp3J2j3
zmGt7CI657Tc9vu*TuKaMflH5vX^EfV=};3Nwi$effs$NsoddC4Tr>L82_BcKa6vp$
zN~np?8fw3=hqLS3IW4rB;z5)dXFUfv2AMnb5xN;2a;hyU>lruXP0-6XWgHWNxCIT1
zO_#{L2c5$-J%(?9x%6O$#TSwlh;_xg2>)+5aTc2lcYb2~Gt3nZ+9I|tLNyIotD7pe
zh9c}_rik@}(Yg;5nHYFL1HH|N19^Epmx~QU_b^x#o-7ea|9z@R`GVX&XUomFFFlFy
znMxw<7P#@MO2{EDlx3K|al;#6i!mzIbkRaqnVTApB=BvtjY`_H6*~e@jupFZAiPEg
zdf&V_drP(zueyQcHM({xDJ`Wfg=6X#=bN)FVm;95I5{fEg40iq!eYQEu@%q&)eDfqh?3>j=E6oiVM+jL#bAR%Ab{L-upop|@rG
zZFXpdV@>AgrAm!X>9=*Okw}!P$rU1zGU&L*arMuML1FtwgriO-L-Q
z@{3hr&|+3PmlT5NEXs0dhxw!=uqJ+|8}UGYKrZ3LD>;1+bwR-27s%ga$e6+of-T}>_Yo`RZ9p&X
zlu~1;nyUldlc4X%KICXxV|I&-&?beQLe!|SWptQGY+-E`%CKVAO>kP>YNzA^+%Xl_
zUXh5(J*sWunFGeQ-1Q%m8D{Jue-G^(0qAeu&P{^6Qg>b~wRfz9V9wtonB^>8Ls!`*
zLD)%I312hJX+;%|M|O8w4=Sm=l*quWE#&WwG73I0g1P0dlyyz!A-D&Lhf>nE627U@
zEtF5ZIRs2rtti)n*MZ
z3b4v=Uuc)Jb?svPWEAfR+EOA&U_s?<<}Yf`8OoS$ShX9ud56JA!boyJ?M*20w}pX!
ztcgRUOf-0@L(U)@?h6^Kld@)e;#fU!G$Y9kPbV=W*af-6Z4;gCI%$pzMk;lzE}vf%
zimn)+NjjR8FuG)PWHLd^=~+wCWkEOv8R(}af=tuzZ!D9ug!ePd5B>G^S0ay3IXtI=
zsf|9GTs`i{q|cr@IHT&B12LH;%S)Hehd74&3ZfUt*ttLduvq-+Z-_h9LSd!{LC6>5
z9zQT7lF98M{c#aRypHtU4@m6$2;zG5-$#wfNZL~*HGY6Dc<{0wni(K1e^|<~ll|XY
z@xew-i$x3&{9vKp{te*H$D!>)O6vPCCDPUV_+=Z7^gcK6Lh}89inF;M&5MJ^lqVhffy+OPxF>FL
z^Y%qz!3|3Msy~vRuSZ;HCgM&wDE_%E$dtjK{y@Xs2WY|{dQ)Pd1Bu=MO8Vgg%{&_q
z$WBEMsc{j7Z#9zKR0~*=lAAUnPJ0=0Q_$wqn>Cy(0MI?jw^`Gg&G-5i5QXW0U=#d7
z%qHj)4@1fWT$wS4ALEuZ^^
zR?_AI-pNw;z9TKUqQ&!b(VCUzn0ulZ)yAz^$=^TDDi
z_DgQ@TqZ=eAf=#zc|~zLV!tR0$Z=Uf1LtrcbJ>gSBv+p0>dH@_$Zl}w0ya^;hn
zX;(%+lYBHe;qj8kBgd>9V+Q*NaiI2w2BJ1W%M%I%+s_ZGS
zMaP&uPwHSy`lJqr2LL^=4rXjC)!mMJ^I_Gu2vbOer({rILt%%435A`J`b0h)`tR_z
zHBQPr-5td$Q*_UkL2hvgg4%
zp1U7S+ga|+`yyMF5S5obZy>=6GJ^80IW|&%1_H4AicuKIgx#8McUlvD`H7DGr
zEagcVJIQz#?kIg^=U#iMBj?kYtgAyHZ)Ss$c*0Dz8MtE>DkfLFetj{qalFrsN^)DA
zZ5eQCV{zLOTnJG(pfkhkaR|ruEyAIIR@8e?Xgv+F+;ckI&j)-vP2=T|&9Bnyc(6wN
zBXwv=`uv&UD0B-27!vWaIPZjpe-12FkRG`iJ>;jej}dC2m%cKZo(q`|Sl}DZ3tk#p
z6g%bvjd4I@nt=lBJ&)wMFWr(;_xs6g2z~Yb?*aKaf2*=gcG5TGwe-yl>x=IHDb)ec
z^Z)Zy|LfR9B(cfrN+kXOvB}9p5UW6JV(*Aemi@qpBsK|jx;yvaZ-<
zD>?(QNq}Y?_+V#xx7ftW1ww4%lva-hH0v57eenH~D6vQNK55wpBsQsjx2+>K34quH
z;ub2I#3oyjsUtSIfnt`5U9kzoB-|>9Pn5W1cshwp9#SI{R*g)0>839yG1TCCmRwR06vh
z9Z|_A-J+6gh)RA}rdoZXQyJ#+qz((N0}GzsPET9Tr+y5UclW=v;N>rIxqyVH1j4Q|
zX!09}VMozJ@mZs^lHCe>P(Hx;&Qsh8hU!j0IYk1gbTd$baBSj#URr{%R5Dee@sTf?(nEq?VPL@E7T+!KM+NYRwa_4fJsH!eaC
z4HS1gfJz9IZd{;vXPh>6&Cz!y`=eTky{3_tWWhdPD
z2Ybd)ZMl-;5Mci|3knMPUI(;NcD$B%=4!62=8m(}hSm7$A!_8iihuVVQs$PxzEuG6
z$w&*}mAuYM#TH1hwSfDFP*N|z|Km~-|8Noo>sERii6XoF0~1h?5)bU}
zhzELH&_O()yPyNlsq2UbGu*SG7FJwr{51sPjGxM{UiTf|4ldlojF;mZ~3?Vw*}`^
z-QmB1GR1#iYU}jhf`#~21qVu~?FlGfa;=V|>jB|=AMqz(pI$-uRR0aR@sr2@h5znj
z!M3U{|GkR%Z+Z&PsQ#Oua)9`6dl=v!#DBkk+kb!Qq>`os=T!fFsg3yWGoAh$xJ&%^
z>>aBAK2H31x*WtFRQz`Udrb{iF3#m=d4
zgcgz53wL6IcJ`TW&!16I6Tp7|H$cR3KRTF)wFOL^VV)!sgaepIyKrdYSpgHzW+%bj
zk1%n(in#|1fW#~ef#{oi_I|Vj_Euotq3>%jVrF!gE?fw^1AsW@9dgsKcaW1;Z%P_e
zL?y}gjqSJ}1Lv^_%B09OctSW62$a;H`p3u*W^14PA0j_OsnB=d{D_b{kRO8jDAG;+
zV>BN2ev>HoKgZ(%SL?vzLzA*C+_R7iEmiP%8{qK;xAFLlO`~q-C4k50bfWwOj~8`D
zqHm!|ecfQk*WSkCr|#>*<5{}mpW^X!Sf!$Wqkps~_21#~N4oI%9K{C6=;M8zdOqtv
zK;&QPhRDCDXyBcQ{LX)Z$cL(keCKYIvm4&NRz>8e?@*+0#qIs5F3eu+MC3^>)onNG
z|5ZGG!DX@=L39uB_7<{><4g0;
zWQdiaNXVuvt9O`B{fBt`yLaO8%3f(mh!zLZ_uir7u23!PsG%QexFggLRtDifrUQ>3
z^a+)8rc4fC_R%~3V^qG{`N{vCsQly(RGucNeDxO+iQNBlRQ}RV)jF!E{Gk$J&9?3&
ze;4c_sQmBtL}$wHb|LVk`E=5roph2cbT5m}+`5NSQ0`ZDsXk)b-cBo$VV=F0Sc6M|
z!)L&`XJRdPDwurz$K5gcHJQTpPE>yV-i&UjyeTP7X-iptw@XFkpDzVeKA(Pn`p5qo
zmFJ!Xq{lJsud+=zMsk#mLjsidtRcS9d)%@jGoMb5wjHuTtwxosKP3g-adX7m$t
zOc$0wo>*%QX*yU_1sXhRQ6
z49!Wie(A(XfSi&O@vyHVxjeAP0!T(&HK5X~%Xv6U+;{){2m|009PHG9Pi89N)Kl#~
z-qnbp4->&L;1o<;9h}12jBdCI5?o$pvVQL#>Nw*rwi65`4$dBkUYG@a-7orl5M{wE
zayTz!$JSPaT`V&>XK+0kq1n_o7oYHG@O`XKf>Snx%7H*7p;2^r_mUIzWPhLR-Hgr2
z`I}%J1QCJHUv8aWWI#bh-D&g!jr9tR19RXs8l1&{{)Z*$l=*w05h(1#R7D<$u6Xcs
zF{Q=CAJ~irE*GC{p#U+jZps2ao3>g5ocQ2o&4<=(=VY2>-F(RVC|W3CC$T$hZ_y{6
zB}Tq+Gl~=tUS8158y+=7Z%;)pKpP`#tdEeoKsz
z&~qf@qdROQ`YTo6S%BRM$#4x(NtJGh5CN$&^*P4Ubt>)2`w03Y9$!R>*RJ*E9IzL^
z%7wT^jlBn_b0>XN(BC*g_o$fiFv>_;r~|s`9kxTxw*vUaAu!L|Ij)h=uNh6=kr4il
zd+2n)gMDS!w_5QRn-Q5k;1CMxz=xbe9J}IC@~*+yGVwNTE$)GUF&NPqXP#`blJN*~
zwNO{%+?`20#xz2^*#v(xk}AvQKLEQpAPwSczQv-8NK-i4XcMQ@P(b7Wfo!mN{sA<615VzjADn{6HUvWai(WUM%tLUj{Z2>B&xIIP8ZkgLjq4>5AUUPG$e|uu}=y
z#`&q}d3T0+ZgA0S4_e5z`Jt^A$}%^2!UIF?#e#NYxnXW~=m2pMpl7Wuz4P~rY^y)0
zDs2k2g{CC@m<0674DSnL{9MAP!J&FxB^{-h3M
zfW5^+0ZtR`LSi9JN#}Qg?ee#~g>*n7t~ZGStq)2JH}RhHkO=}R0JioO=ZntCKYVZK
zL(9)zZI|=en`7M|r_FHgJ9Q_@S(am2*A#AAYr+G3npeV<-y6PA)h;qXZ-oH+cz_fK
z)gT+tsrAr^rUhEgYHa6)MtFxq#e`e^XUY(gJR6}mNneT9H$wkcJUTM_7{}J{xYmPy
zk!9L(s*i!Q&YErZ-45**2IM@CiQ2~c<%^zn!k^X7@88a2<6V1Um&O3P9^;VT3iaE_
zsH{N0*W1@FzhLk$Nw-yz5^+%+dat*)U7#zE{kY_Y{}uOflWhZyY##|o`w{$}@-~{%
zZZlKb_XJA2rILDb|Eh^m5h*C@ejgPT-AF|};H9EsJXF*#Q&H4VmI?t(+o}--vqt`t
z@8(uFz5+3&15PNs1@@h-MCQY`Dj&&;3{l7n=WtqJb@o{C8IPveL3lU%h`{WHGs!d(
z2<^_sc6kk1L8*~&Y3FyMp7D#<_5N}_4=1>WI*J`3i6*w3joRXEw?$k1QN`ry@JIcH
zTs{7%ZQgeIzU#NRMOEb8mDgHP&=*4;d$WSZX`@)sVu?9#j4FB#Z7ayr%c-Z^IrgCc
zmACt_K}&bLcIWSL6YRd#U+nl0?h@>uza;`UyrC9
zni=aEc_`s?%NJ4ozDF?!Vm|8|UF?Xjia+9F;SEoRr^mxo{P9TpFTo}d9oKxlq$;Za
z_b9faDY)q6)(LZ-44Osy-0*e$-(oUJze5H4=}o6%Jtdi4{SG}a^s}`4yZ38lUWI<6
zq2EZMEv0*}#y^r?Yn6V9ryiPV%dbaFRa3Qj0v=7H-;OFV7Q23XFfxgFM_bAPl(vZ2
z#1dmv*fpe<5-qiXAEWwop15R=a6UG8XlAj}+lcJa>>ycfM_N6Tbj5hYo@_4}oiI9D
zIGRMynp?dwIUDR-Q#Eb184e&@=s83pl%sutaT71TA~L(d}5gSakS&!KPIvXJ)A1iaSv@Zh
z_pj9jn^&2C)Mh0-xwlp`!F>G3Pu`xV$9-xw!J}7={!yD%^YjzxFKM}VZ7T<7&dIJb
z*hV;k3in=y;%T1|&Pw#ogSggYgZ=By?`I%BT;%Hw@ndgN22yGP`$KFM*i0N!i{x;o
zou_NziDG5@)V7nA8APwA<^Hv|$o+772Q7!H_a?fWmhY>*Ny^DPvZ}S-(Nt)1+kr>+
zR-d%Ui%MN5oi)z1Dfn%VF2Flb;aTJ3ocHNby+
z6h+mdyt7Nv-=m0*7dyJ!s|65?#@J7S?t$bhmV8}P=g4i7gA>8#EUJa^zl8DSYIc0OvD&V97b!tNiuA
zUwAvX7sIHt-18lHkQ*K*P7A&*3w)dQYLl3y*9VOY*z!u)@WXgDt0O$bi;n2RiKMWp
zh#TeeOFkBM0t|3k(R<4V+}9q2?DJhl8{-JrVzaR7cNe1tREy98-m%0b(8aEnD~gVE
zwg@```?PXc>#a*}UVy{n9acNWv4hZc-J|;{T|k3l4&n~B-ljol4A~F%Xwr3oUcO=-=C$n3Zq>n7XdOi4y_nd6Iyv_sOg4o@isMwKR
z|KJvZ#jszZ^{^=I2VNlW((=M4_)92X@Jj6|*F})F;^ccGD`PUJ2+{kK%a5Es`t|AB
zi`65R4$UdeW;~}(oIT!f^zxA<`{>`r*s0MONiUqfxC~AYXxoag9uV0&2IpLR0P6x#R75eAk(@Dlw=pJZ
zO;X_KIZs)BU;6v#rwg8DrniorA{-HFpK6^p8tk~xW5(&Wonpa5=yHLbDRqfCY+Fzn
zp?~#nO!Ze%A}u8@LLH0bl>tKum*l*2F|>7{Q-q&UfCvfJvg7&EFNX*o=#UE^4MvW3ii-upKvo1T!FNaLZ{Gi+B>5t$P1kEjjtIroC=XiTQb=qd_
zfle)>d&tWg+aboEN-OUR@lQzr82&nH(g}6YdCfw
z8VOt;h~(UBI+3l`z{&B#Ylyap>_ddZNe_W{)3pt@LX0*EP9JLV+H2?vob*82&N&FI
zy!>3pEMS!9eCOxQ;Ghlc;ltTBWu21lMMNIp4L=S3>Ydl{zI=_?ZwT7GCf*^i_Q3el
zo7UKp43JR-w#f-%yX5eg)|+u{%fkE@#HBaS$i0}eQs4xWygcA+g;jFgG{#q9PLIZA
zm0QQ<;A3%=Y3wsX!hxpdrd1oQk)vX=w`JmQ;=<%xw`)b>@x-RO
zUpZs4UlO)uLjAlL`!;*BunF?Ucdx50AzG`53mO6ET-X;%Eb^pk%`~e#-P^0g0({i)
zIa^IU8)u4Lht1wVDLc+&I7cH+mvmZm{Tgj>WhH)=m~7uQG44l>
z;-%ZNF&zjTjEcC4R$Aqy>(pT>?m}Fgy3T@TOtS
z9GtX1J}*UN(>3HBW0~@W8O)#^bp7*9#_a=1&(q!1D3JQmg5|-TC00Ud{5t$}(eK1X
zZ765I0l2`io@2S7f1OkU&#M2>uFjiF3-aTELE|(Bo^c$pC)iI5kWCNUKC?InGc<4_
z!9tA@J+1yWM~gH5GZA84&f98|0;ibbkCU?|yze4vGmJb)Jsw|c+c*{?mZo9Vmf~fY
zqNBB&f~XCXhtmN}Ak);`yKEOaj-u^{$q2@}nZ^5x9fy~0%EmhSUcpS-t(X_H4AXRE
zm=&AZ=nCsu3m@b|8?2jPKOkb?K<7|62{u!kX2@~k8J>u~xou|n^@7UE`)Mn0@Su@L
zG}XML6>YFwbVNB
zr-WyqP0=$h2dtdKVJGrdynN^pIOFg&9$OT46wbP`16*E^h?#IF-G#*EB~Kk8}pf>x8Evqx$nNi^G0pU1RZfi
zTKhDTQPZ3_;JneUa6Wj1y6!86pHkL8c=%c6x?Uc37<3HFj{)3m*@gGp>2!5b^$1|1=*?hTpnH)}^vs=^Lr-eCWlws9xLRl~=
zdmhf8X{tva`Q}rXRpECSS&b`ZavtNpFOFJ=9*xP#ZzS6Hp|g1T=$&V+31cODqw)Dq
zLB{sNn{`Io!UJ|N5@OqtN6epYa}+P%u?P1G2od018|=m`*ZoOdNw)tTD_J&h&kLtB
zlBbmrZxZkctjw+5tGZSN4eGusi>uUCDcerYS@7j_4T
zz91_8K!!&I>54y)?AYWmdK*c}`S3B|3%?Qru9cz6?WQK4B@Z&aT%
zv>7y}?%NWw^1$C5ypE0TT>V2kASdH+#pZ#8Q?S0(?#Eq!2d}aGGbiCs1H82WrkEtyihlwh$}tlP3%oF|?6vf5|rugSVJRhQ++)9BrHE1_=i4#2;ffAxb}!y2pB
zcz2m>qTAIn$0MYSL|9GLAGOO*7nPoLue6TKDg-ZKs0GPn=G^nAaM13E?Fr%=3*e->
zYzsWR8g@W$_QY)9xu}R2l*nyv^W1Z4kBtv?&P|oCxy|2ZC0IFoUx?phTq6&b2pF~K
z#^oOo28~M#HH|OH#&h9KeTcSrhlAn<7!dAViD>4CP?9Y#*xN3T{-Rxt_r!H!sK%X5
zueaiTarCzAxy?=WBdl9f>F?YbQQ>Zu4X5#FAwE
zwcLt5?p~q`qDYAFq@b&4TQ+5eIUHpyeGZHC1nn01KdsXPRlA%%HQ$OGQ?v%?m17(I
zqALdNcCAg^?ONg}u$Cr)9ruflxWqI=^ynMQkFwt^7jI;v!%O9ifYa^(h%hd!M$q?l
zw+^L?2d;q)sdN+hyHFNAx-{v_GBUE$dnE;8_pzPPE7U*Exnhw^naPj|U2y~KG~85Y
zGydwhEX~2W&0kciocDyeEFfL>s-O3S
z_VBAKq+YBN$L+Q^?Q8mq&=zU6TV;k_V^F+}HJEr#B4hEOuf3aiz}ujIs3(W8g{lYI
zvs<+sngg(^P1}*H23An0{|>Y&qWLZ0e|XFJQmZ?ldGV%X3C=(Qe`E=?VExq%R-DTQ
z6Z>56B%T;seZg_;%Ub-DFVGIZtZ~%JUl>BkhJaSlbpY+T+Er6d^IfwI8AIhYYKQcs
z1gl)rc2
zxpm`Ta%=pzo!r`O2R>Inwu{(g!ilD8=U*SZL3m-ehATE1^v1rynwGNq3zcFw1M$d(
zR`jJ!WVSOB{00(l@F6+)!a4FBkn5~#4B?M-?P1Ct5DZz@rqvtwkP>+Amu@^v?Ojb`
z#Wq9RQ-p&%_N1jq&;x&C2=#dhcn=-<^^mp{vUkz8ynHuVQbu15UC4s
z$MNW+Ozos2Q$CAqfSh1CiJ6Kshh{ddSnq86U#QZbdQnSkYOxhDIy#-SoMf-HH?0UB9&q9Ix9TrG#nvKZ8v^gi
z0j~@9lhgK3(3uhB#QnVFv&kc#B`59G=$`%yPSGKV|7ScAvN7UhS>%%?6S~)%J8Z)A
zJLja%_(!vjx&Z_sZu2~KF_8-lP{pROqwLPl)tmba}_h+^79d%YKCjO&Y
zHID}rv8vd%&0#nO7EjCN6NDo^S73R)jK~}J;`J;f7wFqZ!k%Zf2J6rFdB%!>`G(0@r`Q=P&Cxw(u5y
z+N;C+^t!gG__=KeYql}MD4wp@j?5QW?Li-$2q!&j53-2#4hKib?&cMe3&XoE`Ul5v
zwLD+eHucLg=<^0{xD0(4-jqjqZ$h7t9q14bd(u=Dep|2USusMvW#t2BZ@vQcBQ#M(
zGI~pRv6lQU(_2ENn~b8&14f~f2A35(zi}%g^*gU%Jsb@vz#?A|)@??n@j+1E0M~4`
z+|sv-)!k}axVIo`TSKX+gLg6)
z^_Axa4_g4}(=KtDV;A(deS<5ih*kRbK;NDB)^7KXj(gG@U}Ixkhrse?_x)4++P!Z}
z_6vZWGHCtMGZ#5#f(GB~(P*o52r#I}IeG#u_DW~CUi%o1Ep1aUU;$2j&8qLGdQ^64
zAna;|C&mMswk=aTWGuo@)&*;a1VNwI05gU67ns_fWZs0fwTanZbluxNgr`CfdWl3u
zMpEwBkv4w=ykVx@mX*j;&mtQ4%djG9n0rA}ju4gz^&&^Q-C9R@86+E1PcOjN`-
z@a9HTxRW>CzMV`(n#Ob52j696@s>9(mS_h<|QjUn^8A{^9AYP6u`qlRyp@#Y#%GO
zUwngT-^B^=PV2ghPhqYHO8Y$-)3crAVv#QK=0G%HKVB7x<_4pOSMQ%2ygiyw!7A(C
zwh%Db?S+XO3i8;(3i6HFv7vyw8l+!afkU*==HbgpqU(l0PNgEP*NU<#@VSf7E@DwuV%Karh$)4@C^3a1We(7dwTUD1(-sXVSL%EO
z(#2Z0M-{mV#jry^0AvBA1LUGpI&cUZ)&}#^-QsfDL%UrHUq2#TCEAmb9RCjK$qGG1
z6?v$ph!wqLYO>t6NRfGv4;U4mtxdFfpZlw?F1^Us=Ad$3>+drJcN*
zJxIQ(s})rggx2rx8buPikHL8d8)+85ta6I9AX!o#t=$+15yrkTeaoYYiWOVvP~=Wo
zy&VEe*6$~}s*~?wx969FULg5C_G6+4;-!Z`7y9f~%5?0J)urO4pa{|nyWM3a`=mn-
zlD@WOmRm`wb%)Y3*pr-O*;4me=d6hKui6hW&xFpBRf&KbLBBydIgCB5B{m7{d#BXF
zJ9Y;N&xD?;MZ%NoG&ESK&+n`iz*cpyC6BMW)!BdNh}EOzzVxonQZmk}#A#*XrGYTF
zAlEvy%gqyY92I?p9~F-WudqYq`|j;ViWldAilw*RAj;l-)ph2K#>$
zoEDicUK$I%p4q)EQ{|Ln=lAYTI#$7oasvAa(V_VKreSp>Za+yZ&Lorx$rDREC{ae-
zoI%DSwXCp`+cJrr%Sjg0)e2|Vs3TXw$aQ~GDg9(OP^Fjqv4u+C%K8(TjhL^lY><9i
z=0i{?h}xD3>s>@@sn&_};~#0+dk$0_$eh1=&_RY
zRX%oGX5}u`1`=CV^%1dwV9$I5(b@`G$0iZ&**Cpw1jYV+)ZPA7ZM)O{)%_9dAH1zV
z>|exq#r`Rlrknly=;!QTUGINl{}es#vVX(|fXsf>-TncM4A?pcd#DubtZJ9nR*-d4
zZJ%d*q$?wN!2YI)y2s?6lSS3ishlJJu+!41HjdagV%><{3$m)#&9;f%1s((bH0j
zBYZ;Spy*FQ*4ni)y0EarDk{9p|4!*mxz7t)r%*(=x;9Z-+F_@ZZ=5&Ah@bU={Y#G|
z8VkEh6Y5@-@9nUAN}W#{yZRzC6+Gm7M{k{0ucJ4`>bW7s(
zn6F}iA|mb`U{a-TL&4e#^2`c-s!<|62iibQj{U(e(p9mm5^;My@P>25!S9%S2j?w_
zv=BYydep{3Ie0`eN@shO+S?H)^wfFp=@^5o2I$Xg)OcyB2i}RT(;2D=8phnR4F(HX
zNsyq)N?eH>FQY(qgeyF81jLfc9F@6~OaO;(eiQUI0_#}SZ^1}w6A5)5piXRS^A6Y_
zm0pa}`U`>G?IZquU9><)MeIRx-yYYW-^{b$!aLjSYtW*xoV?pTplM;i_>*AGg7lbS
z7ecvjb{X#9Tj4R0Ifz)lgQqWxz0u1!#0S=9-!Nz=G$4@Zbq(_b22KX|p6JGT%shp+
zN*nBA=l!VFFVpUWcF#5vOZha39{XD4mm7WywSotE;4hr?of~YNW2?OB7nunRx9p~$
zbKLS{dky446LfMxjiqy4U$9RS3c#!Il`L6gUncE3Eg$TTLgbdm?#+>Vv9W1?CM(9#JxV#I$D#Ow`1}mZQ4*g&
zOUijiDy1FFmf8keOSRFCQaHU;DlZRw7P3-nSD(uhql!YQ6H3J8_=%j7Rbz>Djc`*x
z^~ks{TM9_)9(Xt8oz|ywED!C3nM{C4&4^+5jPMC-*r&-@>gvb>dl5<_1~#@WN>fUS
zOl)vPf*e7#?NmlnB$%{OC0C6Nt=qY)ZH^5t@kMPok=k-;9sKT8>y-7D>7N2F`)=!#
z>nsZ-=sQ@Z*{{1sBt2TUs}Y4#sz@o39Qj=~JgvV;iPng{AwEylFXEe{iW(_cv+)0;LQ8kpaSH%)a@mmc)(oqN4XwcDRwXt-n
z$gmIrN*77ospzY{YP*>0vx+R6p0)^ljuQVe@GAwx?n^mU6vtHST%eVreNL_63(&~k
zb1w|o{}cV3)u0PxJ5Nq1GgsF3K`VaJr;%=+qN372L_!eJzuPfPn5ung{Xze3a=yUe
zAm9lHzJ^Fsyi1c`idxQHz4>jq6?poBcEW)D-$1SvsHeUX
zZ{GA>QgSh?!mFR{%_=AO{$8WjQs%?^ZX!95RU%}yUG{hCDC@}x7Xu?;t$l$;u!gU~
z2%Bf^RC3K>5i!8a+iSV$6SC?Z>-m}7n{F`eJhha>EJ8Bj4oF3}m<6og1M)gnu`yj7
zwA_)gSs?yUGd5YHeHKnc7b?+8@Ps7TU++P$B%JfWJku7fO(arAbWrdxl?)8t8~CbI=2j%maGX*yuBPA#v1uu=
z*A)V1{F=uvf!$gqbMq+cw^}CN{M6dEehNpFGC_$ORGXEf$S#@R+C+Yt8Z{7`1v&1N
zUl{QZt#9QiS_J2keqZ;dye9BU7k|39?aYkSwj?u>XZaM{uF}D|4GL!+itKe{vWf&N
z{e47lB3E^_3lsG!RZ3kVZH|ttsk2U0Q7YurUAjxk)p7XTOGYWM9o4S=sXYg;R(Ibi
z_|(CBD}HW~x3|o)%a!pJzJUGC1>4#5`F41hAjH2kX#C*Yxy#x_kjVQx$5;J5yF>c{
z3$`ndC6WkuLr?7_9MS{Lt@EFpA~XfB=pSQ)QzkPN>Xf-eMSOq={-O1%l6YCb&v}_n
z3bNE$11+XGh5M(4$$zSSc0E%8&&!vn^Lt4U^P>^uauIcNlwP53mmMlh?CgoemR+Ml
z{Laubv-U@=^mZ#1!-l|lE08>p`KY2f)EeOhN3ER(`_&XtJ+D}R(_b&+Ig|gqZ7u8u
zK%@;6C~_gMVik(jwNh3GyjPGu5As^uhaUfc{c@0Y7+w_wd{}%4v{KU)+#FcER1Tok
z{8Qyb(R3;+v6Bz*E6jiPc6&-_i_Pz#En+7{-jpDjJJ<@a)$se=h@3KPCBOIk$?CJf
z?}{n*hl(V4r(*X~+&m{Ztv}ZF&=c#Ar`IVhyXx<$BAJ3n!`Wnr#Z**;JmnnyP*nOU
z1bgu}cP~vV>*O!Un!+_QUt-%<0QV;-UZ0e#P2g?5z#&Osm20iyCD9{IbJF
z^}cKuiG^@Z5R47G&NpTw?ZzO~6k$vzIKhX?7!HLucS`)JwVh}LDJRj&&!GoIw*T-K
z_>^?gO*}rMB|0@i*x*_NJ|8lah?$8oc3DRgkEUphDm`Q-UGz(VH6Rfmq7CoN-qTqR
z_E*Hf+_
z8jZ*YG*tA$>Zt2Z5Yt*g3#jn80xj%?4*I{Cd-u4euB>nToFpe9ToeonSZtLjDC5x9
zR6F$4%!+?6a?Ht-bczYkgM+|CstuBtdn;Ae8zN
zGL)ny*^PB;24W2b27vMscuKh^81MkHY79ftJzrS|T@#Nllt#E=(zAJnH?eXrN;
zd)tVcXPS*ZZHF}%Z$RnBWhDix34`0a*3&;(R?$3V9ip4C*0<_b&@-YWoWfxT^VBU%
zB^s0Ub6AIU+;B4@&RRe~zDfvCBzvnd&t0>krM*0cmK!F!e;pB~zcIbPWt=h*K8^dio)AD!n7qe6`e5
zNTq%x8LOEuzj@IA01Md(_z#;`V@;gzC5yVI$0cbp3s%I&1-B&~XJ{KJi_75GcxRx$
z8D%No4dQP#WiPaXm6)~ay~NpcQrI#n
zcoOxeh3b*^X`17{{os{))r0+j%6oPL=DtMk8ynt{=e=)~YL1cR|MG9&OXmHXhDxKE
z)Yu`9WJZ5c$)$@*pY&yoPxjC}I6$3!8j`FHYaHne&LI9z^%z&q9cfLZ`KR$vJG8?+G$Q}DKTGv@
z{`>p{O7nwrWZRRMAI$mm_6K!7Jm(h7MBkkI@A+@4b2l^?&z#fKN9TNjjq0JEY?%Zt
zoY{ePmZ299e)B@qj(_#6YV3+1((e*Q^~u`mJxLE_t^c0a3o<|<3-6c0IAy6zvcu3%
zma@Wr=~vh>h-+B$PBY09;=29^=!r&}e}lT+sM9=im+l!{-ox+aCgMI$X!;R)M(M2x
z%x|W0gwK7R%YxQf_ll>rtVz&9(n
zkV%N?52v2fOo+zhUZ6pm>Nh5Rqz{8#6Q$2#HK$XH4r)>Evvit*HTT!nHJOe)J@WKl
z?u8_4J{Mxs_9?4|!!n=EI92G^PWjt!rEmRrb|n$|8(Ng4l13U+HB0*&(Thd;j@umO
zsRf?zvIL@%v~Ti*xRKegV)80@`ZP|zM5U-7TPF2Up9&Vm#uJU;(8gaf*hw^>t5Qt?
zL<2WqnXBGg_7Ux7GzR@P4a$C!32ogWm_gGu^og5}-{jjH)JuA{rzf6q%e|I=r?%;L
z$nH&2IjoH5o$9`4o<4fs_pCK`pgif>L+^N=(eIDE-?!ozbGc_+%l@hBgg)Y@8B8=L
zS)kUEeII4EVphPDa?f_>O8Uw}_ryJLKpG4LVoOk~~9#K+RNxH0^6j(kRzC^9tq#IdzzBBslDIXdfOBrh{
zVmztty(@Lwa!C&8C2ckJF;6WdF~!G}_aH0Qr^SOh?^};)1oEw8qohe%uy#amB%JIea*7R?bif}jnlehZ6PY@+X?oNCJ>4}Qf`q}2b`Y&?|oj?{7|3$
z_xz9C=O>z^TKoJ7Fox!!fzb82*y*kQZz&`#vhn$C|6bcCKR#Sr-Meya&o@e=eTZK7
zyh!w#_Kk9fAH%DlSu~y?Jpoo+nHOQZ6_?dL(dO}%pl_d?$1lJ1`N6Gy=eN%-A9H$K
zee}6~_TT$^{N>cg$Df^e-h45-s&#E)e?xm;VWlgU^U1joCFCR2`V_fGUrRo6=2yg0_$S~~q-$}fE30lbre^$09O)i8FS}k6TAzRH(%;LPnjG~_0gRlT+`(^!-Yo!~P98H+j;>)m8
z*ckbjOSZHl*6Kh;P|4rh?UIvl#tvYUvI@#p;EA7-?|bH<=tZ*)DTm!iAS5*Kdc
zQ;Yodd0QAh$S2UPv6;GqK8AITukT<42V(Azcl3;j#V+O_ndwr+BF9dak(-{snw^?v
zHuPU$(qR>>mRr59{`kw94DWG^j#nNFx+Vnp(eHn?{gO+*W
zj9R-s?<}Jqd4w4!xI&YdR;KMY)=^r7Rv8h;@TY$Y
zcKfU_@wNZ;gf*gu0m6i>VLT8f)-?Pcn8w)+!2`S?S3LQ7&*l^hT
zNUP?j{5)8jKxHpPZ~N%_H?FL^y?lsoFu&P1Sl2Mm=&cEdq@_1<*{+<;hjg!xW-g-i
zkK^3V_e|Ot>u=(ioh4SYFSE#odq6+j32=Ny#~^)P7L#4L$Rb!aBhKuSW$X9KNFO%e
z(Ve6VjRfu4*r)T>Y4p1^J$z?%@TN(kcS8@S*>niEUdmg8U0q$QPUWu!>p}it64r2AhSz~WlBYaqXMjOt@Q&<|6PMrxXMR@%GcSmTx5Im8hr2ncR`P9^-
zj6n7ZJQEjpAS!W*>Ej?mqQFeRS4%zE;K(&<9r}?!fva+Zt>6Q}hp%0sq4wW9=vpzF
z5i>Mbwiw+@?g1M#yO(BuP9Zxv?%t&AOzH#{qZ2syr^KZZA
z5;h!cmeAcJtlKHezrJL_-DcG(i%vCEz3Gr((T}{#
zY$=uLq;jvg;k`;Ry{pG1bV+Zga-uI+P8{D=gg5P)^6!e25t+;>2cL9JrE^$t8!c$&
z=29(!c^2?bdG0bJ#@@Li6iR;2s-cSRAo1g88(a-@KwHJ@w-~t?L*O&)N(p;XrwUZ;
z{bpZ`b;J~45(%8&Fj}>OEEji#acXoMBbcYT);*sbI0qS8ILx}kmvz|^*p$pUMe9rR
z9qXF)BYm)E_%MZq>ohwL2AUR6R^pBhCn_%FIC(PyPxda!3;vbc&v(@8eBnbvXLxR}EPsar%u0f#a0?)PJaz5njvy%|T$x>WALOxsuAg*2`;@zWh5^
zSlqi_DC)d&u{3a|`b`NNe43
zxc5eI_xEojkNV8G^0+ba17ivCQ2evHlX}NmmLsQ2T#*~Ow3Ja^Oa^Dja2v}V)?F6d
zdmD16v4$nptl?rYqucFyLMQ(?eiMWs}85Zm23XRrqFGjav
z1boENg7Q=J?I<(^12X9*=D6#(OZ{4ZNNjHD6_=^63&^gt?5Txs>o~4|da6!HJL&m9
z&@L6GfZSNJQ;aw}Mj-U7F}Bt{y$u1^WnX-u9#~hB-*(^kGwG>v`KHrhLhGIdXI{RL
z3r)`@Y~Le&KmGC<7N}jyN){!vD`i}aFrn|AljMK>#3@hh+v^^!eftSd?c52fZPf`+
z?Ue=6_v3Qy9-VIc0MDnz!PHWCIiYtQuvvGM)dkezem9wC+ZEKt2htb>bI>3)yh)n3
zr^V7!QP+<3Bj4RTuYJbQQcpQgUE^%l&&q;;uu`}A*gkuhgLJ`gL9q$-Dju$PoI|cR
zB~LKR&&2_#d8mq^wyE|lrE(9bXXy^-G2UCP;Iq`wQ`F3sG9^}kaHN2u5%4;Y5%{!U
zKOs+bLN{PzFO(1t{CkPrMSqF)^fSIR(zeUC;gD{_aHas~f+3Z`rcH+=Ei#;w`ryF~
z)2aOx>tb8ia>`dL3LGzYv9ZUBxHv<|X3WYQ##=4LBCj36EtO8*|f9bvvpRxC^FSx}7Qb4W2zf5{b^$M_uXBomR7AH6juEsjz!PulnaLh077cWN2!0
zOAiSu{m9LXoRx-h(!>iB5Q_C$v9x+Pd=*^ENQWJ;2Md?8+zh}!m$Oyh#J8XS`$;V-NIkAa4zrlOucR9
zdVn`Gqs;LFJm$JrP7qYMz00-r=u{cKN$dF;nJrFUOTgb@-#+e?6dKf=h$h8U#NAC$r$h45_8mOu#IBfI~+{$
zhA*GyIWCaShpyn^%!ivkbnq*5ENT7gG~)FjAf5or|M5|bYfTL6+AxZl__vM?{C^+r
z?{dsy1E%wB?fxd@l+=Fi`k_C|f7o9g;1!_6b3f~o(C2TRV46;UXzfU6y++ytHDznk#$A`{yM?Xo9h&AN3P<)#@dZK;Pl*B)02B3SC^|{zgwf<_0JyNcN$h~
z+;`8d5z(^kp{^(tfG_O^0X%;>(BI`PfwExxAHu
z+6vDOeACF(Jjgdid~L|tVEpY9x>YB71Nt`|%pHfF#jajPD^@o!Xe?wmw|E(D`@)Df
zW$6=M>sm368DlGOMme|tq_sU)YW>WqI(XEzB9L+Z#My=%UTqvz2A^Skzy3WTFiaDM
zjOAIa$|EB<+oMt<()r#kkHqoFn{dPpPD3Jt)usBOq^V9ViF76wbq59QAdkcyUt~y8
z=xOFN&qO*4ON7{ILiRHSwh&l*{3GT`@<9LDP8Geoy+|Ha{>y!ID2<9+1b!XJ2F$Eb
z7I5sA*lAU+IZ4K8AId0IN##JP(hi2V^cdSw6He##5v(k8B6^dArt$NS>AY|be(5Q8
zgEm8J(2Qlv9etY5$1Od3L#Az7I~lT%)&2J^)>|D7Y#pT&Bxjy@+xyLU_MmAaa-adR}+F1
zKe$top?SgUBxlgv#@P`_e9NyOQm49CnP1(zJm^M{xVoyxy}t?(XLUy1;(^#p(^I#^
z1;@*KWPGW*ie}H?Y{6ZB%K+D)2<9ZG)0kPe;|%b9P+xbuKh;Hb-UwPABzo2N@Js9a
z9W}oEJKm4;SME}=)-V-&QssI)3R!St*bIfMe=J+}sy=)KoBy}+5B{1HZcVdv2NMTb
zM_>=^?|wIkE#Bzv9Ej|YWog8p**V}xlgx|mjzQo@nwKAX0+eMA@s-*4+(NqX%Ylh1
zXBzyDFQ)^2Xaw`u+YqHV*9#3|YyHjc#})7rMIi>r}kY-kNxraYzPwQGJxqUGW8+Qp8A$Hc4h
z6SIMy4Asj|wi{Z9=A}q+v)M(O(tAKROx%OaAkhLW4zN|66pmRCA^I
zsO;&2?MJYP$D8jJX_!=ZLkn_#$XbXhF6^idXUGiIw)OFcl{+hXDT8jju*<1F9x#UV
zZ?|TLQJ>ev?6l}IDth_49qPn^{K^=mb%(8YNR3;)!)Rz|U<@HU8N+K=8J*qM`z+$D
z4NI;9OLPZ3Co5o4kAc0e9yykt%S*F7{iEmk!+SF2AR#*c((GJ=(LHZS{*IZSlV;)H
zjbW)JH`++#3$D!*Nmy+bG%g}nWPHgsWFxU#|vd)W?1nQ&Nc2q4amc5
zNZ!HBIy}D0@LVIqX@igIM-FGVmbz@Gzb#&mNIj)~=!f9xc4>YPk1IT!|0))vd6gOV
z6f~K``z&1Cyu&W!6S~o+3mOG)Dz7OnN6WW_=hNEO+BHaP(C$Pnqu4h}wwY%gHuZ6|
zT}Nx5_msT$O}f^hjb@75jdG4=)tf#Qzih1Z!0W0etF%$JtkXWpC>X4$A2
zh^)#$W_+PdaY_@tewUr%iO1VpQ$M-=AX^vp^pxh~>|;fy0OE2w1zfPe*A6-6f;ve$
zTk1k5B}|e(JB~AxVkSky3IV*LwI{k)h5(->MB78OO*9=XA^GZ%g)lc4XIh75dh}+T
z-dTDMom1ixxlCYu_rML%KwXd_8R`tKcw@l^{zii$5_q1p*9X8}OL(3Qu%c9XMvoeS<;sZ)hXRv^8(G>u&3YCh|>N@pL)q=AEghpqAQ
z*QYixf=0xyz-M|Xbil#W^{Z3ply#h26U^#UTYzp#yDU!lLbZ}#y#)ViaH@^8R~C&C
zNFVGV)X~Fu&prZn4k31Nku?^jvlc7(+JQ=~y2>E{f%7(ee3}{YNRf0R2Pag*&I-)7
zsYPyKpowgk^zDTbmsg!4(*8mb;h$)>FHz(ChfkPycpMy^L|h)VI_&5^A<{O^?sBA+
zdpm%oBB+l~h)TEIG=>SGr5{-4m2R_yR_wFPt5^hlMtUdg=zd3}jmi=-rTRGg|0qp0
zKU}_Y_R&p(=x9pq(!+07?aGLBj>(L&LUVVNsCi*1BD#yf8X5*`_EyXF0?FO#}*zAoWjZ(1DhaFY#=ca*L(ou>D5
z-TmHC8lK0W(146`?acc?N-f^NsjM-#dKVY1oPD8$`e=<&G3ci%oRRw~hI-$Eol(gP
zw|sX_Nt-$<-dTdyyZ97DR6Ew+5f53qC@bP^6`uhc`m=eEH+zh3p~YxGTsSg;!pqtV
zTG5N_%^8bkotiaq&b~Qeb3d4?c=6_xMG2=8CQjWqm2PCj&0pPGIa{o`*Ri$8MUmq}
zyBL}ik@LCd^1jtepWi5<-mz1uchpxQZvH{w<78Fh4fOECTcB(eq(Lf2C~`ay>B`XK
zsfE@U#Ai*>s?w&K;$JxUa2e6s(z6w1hQ${i1iILLjD_xR9(+FbjjQurCd9%o>r@0m
zV(2tW9w%K;Mk!gh1aeXty-^=n$(%QBGU@6ytSeE&>iwG-eLx|jAJER|b(M&v-dtr(
z7MPb;z~U9y4&6l`$l(e82H-CMfBqawHPv4&>En;;tVwl~Hd)SFe9LB(1y|0i+?sK<
z{+$wfZ%)aND|GND(+4)84zz%Gr8-d8){HZ!=3vhu^oOw1!sG+U?#!nS;#>~XcXWSi
z{oKNAvTT_$?&#nu^WpKe(Z~P9%wxPAI1fLrFh|-7>%Ea!(*0-MjG~Qm2xyyO~``LJVt6GP#50u&
z;+c1If$ywvM^`EgLXgBW?@Bz=RYY`1RG3yI@j`PSFO)~zpYa=+Ob{W0!vTF$FL$27u;oNMns4AJsr59MrxT$ptesIO0%)~mil3e
z=09ms02#-hXnw*pt*ZOQ?hq5^#uRs^@ZoaenwEPgH+0A}Dgn>-gkf&>Z)(1Y%mL1Y6&#~DO(bKEyiDTaNnBQE#7;`{8b%^@2m>iYd{^G={s
zc&jQd*%_tk8&ZLb#x3RG%=3P&9rE1Pt_d@D&w}
z{XViq=nloR{TP2jwm3M^sag4W+4M5=*hkSVn1&vd8T#?Wm5*-)%EfbNYvoIZmo6&G
zrXQThmeBhL@vLlmK+*Dp4`$!=(B~HaupLeclJcc#%}$f4xFcT
zUBFkr1-$m!d2{)hor+MS&e7Q$T>5EFMDIMKpqW=nI*|gX$g;I%A8uIcykEP}J*%lG
zFg|qR<|-Z;(FqxxcWhLIp3k=E+2P#0vpTg(jg`qe>y`oDXNJPATUzywx$2c4dvp@SQX+v%optmgIE#XjJ@-
zSzL+`Zg0(7_GzdwcsA9VpBq{lpLGCsfcz~6?PlZCM|jl=w)L&Tr#wB{dB}HOvCX$s
z6eGIhfkD`sm-ESNW2o_5hCvfyirzdM)`Q`XaJVPWY?5#)o@A*!hWhn10=La(a-WM)
zVkBstM)O_K%ggn{(+2A!UkK5Ud^tovbZdw{JYcXsY~5h}&|#11qn-}Yk2c}AX!ecw^@)e4AGX5UEYK{(zK2p`3HieDTN8#U?
zw5dTE;9Kv(ztNAp)$CToC#On{o#j|FA`gKF(x9LlPS#9_xHCAN7w|wh;DI>$@IZV+
zfvel3ko9ZJmk;njQnJVk%7X`@gulPljEF|>dSBk@1B4-H3xYQTZ_36WQgy7V2}mD<
z-xPrLF&J1MgMsxi7+4=6!1@RQ)<+1iK0<)?5e%%4U|@X&1M4FgSRX<2X_hIvKnui*
zq`Lc&2d5}f0i)PjOHbu!A35>>2p!YvDE?F_W^t2wVJwT=#J3Uylo7|2`jLJLJ$(Jd
z{u;9~A{%F_>r&iPW}>IfnuEF(9bRIn=4V~*DCWRsyY~1-ms8zsHHR`OSuYgg
zDf7T9M?&VBHF}
z3XzndxYhLgc?|B>y?$QGS$Ov68N5r&0JV1oZueGzaz@{3M*O1};@O$HcdR=QS?Y*q
zbnmLY^x?Of^--5Ehg<^Qhqvg^T!MPz1;2F>@dpa-ch-oCX65-mBKm6z{Gi2m&d*S8
z$ExF3LQx*KL8l32LLmnjh2HfOD0Ehfe)z3s7iNb|&=0-U+}hZBR#Xe{%|P@3tuMS%
zDSFE-IM|hgu%21lf7XW`V`zo4Eu1eO)Ws+xR99i!@{*&sbe!sH>)KVlI*sb;CA&^-
zyIN1T$c;JYx)Hl2dbN)h139BL!q!3&Ti(p2_1z)Tw^r)q<|EdKm}W!P9V*f6N*Zkx
zyE}~Qr1)YsL42w4_u?m7;GR`9J5Nwaw;-3KI4oX{)YemN*2sz`-M2x^rH@mxPP%m|
zgV0OFQKYCbPH}2uvqTqmE=-~eC((s|bVYOPTd}Vy!)-uRdxSoQdgz1J59k$_J-&)F
zbLGmDdH!Pao%iVMvAA{vV}VWl)CnbwwUBwE|rM{6&9LnU&HfHUQ&eubXw?0fR%
zH_ZZ8=Vz&{wkJQJb_%kf>0nmA{zjtwCp6!RSw1N;O{=|9vP{JoGn4^2x5PV)damfy?2&n6_uk0Why+p-T__tK@J2(p%p0~AvSU&d)7_B#_8L;lj$k!G`{Wc
zQd#g;w0@`;B*^K9d$*q2qaMO@$fvt%Xoxv`lN`s%sSe
zwG*+**r6Us^FYm7zi;I=y)XSBk$6rs1MzpEkI23-&_(3s%gFZjJNUf%&a<_hVX1haCat%U`8
z@EO=YR9C2X5@tr5sL+_cKu0`qs^NkM`M};d`Xg4G`YR+VNF%dgp48nr4#!!
zpEky-I^b#T%UG4QUmZcK${1vqr`=rDPR;rE_!vCt;z2oesYc
zMwhd>+ogR=AuMsN)|}P(+OE1^9fW*0s^&$jVGC2`+R1vOelB+n{$0~A!PVbS16yMkv-9E3epB&u|8vam==yorEZ8g8x
z_YXX~`d|3Q>cazD_{ZU89A43ak+ra9S_eG?o&Zm$=UPd^j>O*L#E#ktd_5hqZgsAP
zm!#%(UFT#*RBJ{nvEx!)dgbTTBZ?n?SBgfb-Q3f&kAYv|wNR%Oc)f
za6vTc*m3=!v||X|Xg;T1iO~$b1qpE(dv_qH2a;gnnZH<{R5dG~1P@?rw2R2IzUvuz
z74nDDiafHf_0xoV_O--=G-9tqg5U8B;%S4|YLmeiUNq}dvetb~zwjSwUU7MJ5NIdL
zFL2iOR{xGy`<|NyY?)Qx7p&$L+*71qdStAA=og4*)3nNsv&pEc`;Uv5UM?~?i`
ziiIjmPm*GM_2H0ojh}pu^=ejv9<7j6k}fk^pZ9l0|H1c&SC3%orTATFEO~aeN?7VR
zj`&?@6>TT>!vlcj#_=o1KCK+#i!40O=PzqRv-E+7pd(oj0R=JMd8;bwLA>VoOmLabi&02A
z0Ce4%o>a$j=nNu6ccWwCHJ$R?@*BIUqyOQ@llQ%WqbeOEUA{BaJoCWtn=!Gx**aZ-;FW+W*#Lp!8-w
zyPb3{+GR=aT6ks#@#L>HpMljL3N@A3y(bFw(9(!nN`%POb84*6Uub;|>NCvOB}yRt
zVGdb+m>;8CqJdop(i)hKe1A3P)~ZcBtKO?;)C?#VepVq2e>w3<$hBtBJg6M_uLu59
z4HSj>pPuonF&BN=$_BpeF}&Rtl#~SA@sodhtUJ;KG}I6J#gcwUXC)crZEfuR7fD29
z#Q2BlRsHbG&BTv$g85et|B2#E5oL<_QfZAEr~g9hJ3ldn?yh9S=HZ?f^dH;!710KA#rAv)b4e)3z2
z$rKmYH{L8_qi#spPE#x2Cez-67
z6#XeSH=m=KrQSb0yRE0;aNw0LF~>)a;oV9X9?!aqnVLO(qPM9ezkmZ#m;Q8CRP
zt*rk^NY8ZA%a*m3q-9$!t>;79^Of?6F0d1{xh!8fqM}Kj=O>TrqdvQg7|S|ZB_;F*
zgKwfd&(Nm8CwH(LLC)h3S^#eMuV5yR>LX`C+rn>ADy$QJ_od&L!MkiKaV*2nd-e~s
z`fP$u?WdCC0~f76zIyx?xAUrzcXH$Tv`Pg@iwaODc0A}ztqTkNlvpvMT}X~cPHa4*
z`5m2?(qc&lh?AeaYsm6qDfi0$&H6BkD4f7vT0dl;J_`M!zM@amZ$w+Q<>XM0NV3rx
zPS&wt!)aXgGxb(J-Fafs#I*0$P>&yuMtejv%aY&W`p^ZX-Z-3@VtgMBrE$OKot2)m
z=fVvPM)d2EjQ5=UrWOgY-NoaxV1Ku~un)Y$wpS_PAMuE$U)Op@*{A7)BAWOiTvWDY
z|9U>StF&)TRh^~XA>fEot9dle!*)jNi@3mZ^0#p5Tkm&juQ5V7<{NVj-Bg<
zaPv-6fXn9w$e9d!t{$Uc$X@#Yu>$6YXG6sc2T}Np5-g^8)T!)uTQ0x_l4GcI6{G2kaZPa|HUL
z%~f4be~Sps##Qi-q7_UA|!-
zzyEA-)@&R*DNB3z_5Lf*8<`Z1zB1|z>wl@k0!F=EPmZ>BGn@gkq?
z{jE!5yJ~P~Sc+d<87%D}#D$GdtfjRS1H5{`{okaSA$zv`r#^|^zFC*nBRcZje<}gG
zJS5FRDmMsPLQ|iXfU~Z29$vV38l7>iIPpFrZMB*K9%&28+aOVXntCJk*^P*5igjEW
zB=uRUiT2G;Y%+bQni1#Nw#;Q61uCI)YF%${2x8)Tzn5fU%sFa>q~3*`7&*Pl5jbxku3WYkp#8c}y7a?8gS~*eNBzK9
zrPH~=tBFpPEp`oQU|v8IXmwbV9#E&NSq;60sPh7I)jch1?0%eEFM8H&Zy}Y%{IQbO
zAeB7`8=s$4-lIi;tL{?2L7fljN_`Z+S$z}zP3J6yZe$f;_#q7#$@I;9hTl!AN6Yy@
zbCdKNM7n=OJ_6F+!twB0@*|vC0r{umQ`=R_Q87waNC-2{-ny_ds=zj)#^5~yx^z6D
zT%>-ojfHHEVO3}KkbkX)5;&_cP9RAd$kaz!p*#I=`%%vQ8o^
z9m`MAFn^xmOgWR&^=|i|cXG-#WsX1B(G3oHdeVJ?tHXjFcilDDyBc?|AZvF$L^*
zD3K|3%xZO&b!0UYZ71oF8>EJ3Ld0p_+l!Io78aj23*Dn|zrCa{XWD1ct1sa0X`h`n
ztE=94-jgkqJl$zUTpbPu*+QKcu5n8cN0WNmggg61|ZTFY%cxELetjpY7J}gmbwg!cgK=8jo(*oR{0!hBgrEqThzU&+zv-{tEE-1=?cshzx84fMK_J^Qk;_H3Hb#prqD{6
z0>aC6>QuGM29GdXg(AK*%1Kd3E+IzKI-_t_q>VlHG$+r^aMr5=9-3-urGFD{p9R@x
zPl}C!uYOPn)@IbzE!GI9lDL&5=*)@&=gC7ltv0HARzSQpB92jF9+9=B0qD?qI+ab$
zugO&@vCiE=Z`>_gfz#`+)&k>xXfbBTVamf33|-_^xM
zGM&Zd%hXr7=1d-F_Yk6h+~nm<|HL*nJ&A6QVaLV>xD+Q{GYj{~Z0_=PMEC(!{Xg
z<*tn*7!
z!~k>orYKj`(ZR?0nS0bO%?u^4>{bXCzTd5Ir-k>qdozZUUpG*5X$vJCx+K?MDbfvo3!
zsxxiMJ0-{gS8^#fGAmqI{$KgfvHT|J{?yGD*!U3Dpe>WLH59Xbcv5TW^PlpZ5X=wq
zWt3kan&U5_%-YHPg3`dVlOZozZ*|m0m%}DUcHgKDq&N#Hs{4x;33Wn>>Ta&?p*RjX
zs(Tkjb+1(i8XQH4>fUsiUk`6V>nh*GauO
zKS_vnZ`r_-N4ERkJ?6~QP7940?{U1%S52cRG!)ocXN-7T9xa}zzs@TV4C-UXc%qe)
zwA#xHn~8GjcJGeN5(9kiU_ETw%m2BZ!sq06#I?S6T4yYN-7}Nh59%6{i~$;NO=Rx8
zN#t)YWQGes^{DG#a4FXPUwI78?u6&|Sw8Rq?(&tlCutA1)=mFBGHYPdrPy#GZHnL1
zZ%^v}hWrZ*Hiz-G!qbO$IW}CP73wZT|F%bFy?lX6mQ87jetXi%Z{#_;;a;byDGZK#
zf$L79wx7-;@9r}_{JTv|sHy$??x4^zlcbHFH-Rrz9W3o`@ueFOi?YkkAInwi-nqrP
zpdb#kJy*%8bV0+J)Y_h6%Mb^@mcv-<7fSyD`V@CyrO2sytV==)#)~2aXq4
zOmw!UPTy_)!iOnXt*BHSOFEL2ty9-2a^HpYv^RgKw7^34YIC1g`<6-jbJHE^h$BD-
z?F7DGXQ(yb2b|ERfRs4TceX5DDzH=1;?kzN)N7SnV<$}3soUUFZua4i7iwMbYH_c5
zmbLdg@HdyUA7#=$qKrp;yWdP?(l&RS?b`(NY4}Kgv2FI7Hdv34%35*Str^5dA5qrA
z!%po@8MQA}zcP0+$BoGdDF?2)(uGKIJdY1%DvLH-qAPD&LSmiOH?iv`vyrhq#y4Xw
z#!QPVj*E)_TYSGMcV1jN@7%oj`3L6z7LtSWTYBWV5;5VcP8agyM1Q3AnVYNg(R6=Y
za3!L+9ej3!IQm$D^l&<#Y%5
z>ut-)N1QeD!FL#BAaz7iKWigl-}9!-)G3|wXdd~{JIpx?=s<}am(n-|jp%!=$ECT0
z{Mu}s_+F_>8ddybcbHrbrz1h=
zn5;#V_B{lL1}-(zyd)iY+Y)l9Du6`9gtcIUwHu~t((8HP&8@Pn_Z_Zh^&92Iod(Yc|
zNXxwS7a9?-x<;S>%srYzTpFe5eXehem
z>>x&{7TG&Dxsq*3)*VL}&f->oXWW0Z%AB1!zS3ZCFlsIPN`aIGOQ|2S`10@%cNGOO
z#iap_Z`#T%Z)WiSEMiUZ(B9rUabde9a!phYPzXRl@5}kNC5<8Cw|$u}7e0Bmz%f_Y
zl@XnZ^5+PBb1v?HT4yXPqc?Rv*wx}b(jK(%RYlqq3-7J@eY2U5sl$l(yoNJS3}Nu^
zd8^s1qx{>MQ%wd=h^Knk|%z
zbB*R4P;Zfybm8t3_Q}6zsmvsN5v0%(g;FfXhlz_aH
zDTa)xrkNk{a~D4AT5*@zd?E;=0;<~+p8VNzE6Zx7G5n8DFaLzk#6Pn)g+T55c4_~2
z*T#;wL>`O!XfCWK0REh7WKZF)Gw0{{DJj({j+yw~x+9ZutAC=1Rnz{npoQv&iPjxc
znBsEre8*&i_gy0&Z(PFn^M>cj`0Ayx;*`dDh}56dISV;qt3zw%)eN#UCy%cYS8L2w
z$p_AI38>>x%giwQG{-O4iK!nspEaAql1#67a(5S3;q=86pLRJync`D+i$NQ1qDP^392^WrH7v8=4T5M$I
z)7;v)y>h(yThFJ}nh#h6@BlD!P6NlLFg`KU0qA^xE-t(e=^i
zA+HqU&lT6Raf;L9&9xTFxC+FcC`IDF#Mx{hOZFWa!SgxZ=E!U@M(ryOR`
z!;gg}eKzSqzesw}?hmfTE|o^n|5D^JJ^=naC=(b*9?D`|!+@$}%%!^TrqF|ydPGq~<%rdeZr%HL7~PB0*&?-ns_uX8uIe77
z^Leb)u<8dXZZYX2!?IQe-Y=zZ*WJkodL1&t*Y{eQS+`;^!=A8)C%{4rU7q^9aJPf%
z6wJE0gN?&{#V5S)iJR2lDqc#;`Efsu;GjjkXc;D-w=7qbpIa1L{y-y`cq+Q?e;a`d
zBY>rI6-JOjBX~0H|LX{7HfRLBjHvYf$Ab~P-bj1&VDcq;cmy*(x%=x8Oem>Gj#Hx5
zC$|@5yt8+lS)!TJ){XG~SYWIrjCiGW#;TjS)e?XGPU5}n
zUD-1eFC{|y*A`KHY;_U4)Lv|lJRMcnI%C0Qem3{g%%n?6ONC!RLkmQ4E>~Az8JGNB
zPIM*cKDZWp0?|IQAnaLHCR2ZJsZ9N=O6`fnF})=+7py8#LVDL)C?3FtGfi~mHH#k6
zj;+Qs23Zp)>He-o(1adZYKFhUz2;=zrAaEV1jqmQ5j?wL)r)}dl13SFi0pgOm956H
zPtlu8&7ozuf$2IoSqBYA*RKs{QAsze1+p2pR;lxXE;wge0ACub)P+Pa<2Oe;1dUo7
zePrflWqc5JDQ&knadNNQ5oFpL%b#xVH}Ex`w(CduPP7@cLru6lXca8Q&_0KdCIt-z
zJ~WNd*|@i9NI!hN=vu72qWxDNz#5#&jjn#}KyEu`S!jBNw4o<|LdJ?;&RP0?<0oq&
zSB|vq*?pC5I*0K_AEA-^S;kk==rJ0)0r{DJ3+VeT6#5hCKQ2wGLJaII4L4sDsOFq2
z@|-O-3!2DEdT-g)1F?pzZ;hh$+vcUQd{XKg1;Qetw>{7IL>{Zf4(~8U*RTm&3*{W<
z^g
zvf)s#POv~HA^(i>4Zt6;C?onYRz0vRyxi|P7qX3P;UT*YOkKeR!!}tySJ6|aR
z5hEYK89ME_7pGdw(&Y&Gmvex308|3hwCt;U{8~+T_W;^S-ap14y@`8AUj=q`jUg-7
z6kTojeJZ>7z&b^SV$dhb5!0DLG{S;yGYcHir+@iCxqTvo?>o08i|2N15(oO;yB518
zj$hCgbv7gnK^&a94fU`sHI(ID?g75uB8~$g(V*p)V3~M@cAxBWL;E!B&3Q|X5o`I
zHL&WW+F)scRi=L@)7M@r)dU%}j-SslY#i``)3zly^|IzPbL)&J){4n_J@t@2Y#c^W
z8!bR9P(uHyZ(Z2CmD&LH_gstR%tY-APCy^9JRq%Jo()G^wd}jmms&@Pd?D^{>H?s-I?VZ+Y?<=IoW`r}NT=aM}P3KW~3X;H36*6P=>U
zcN=))`yCTx3BTjodPHHyTMk&p)s3k?AW8T|r_*c4of~t$n8tF`&6OH)XZtPgCjVuP
z$YJ=joBl4xL_|dlfTc}8vX!}$OE$LG+)J&$I8N@Bbf7&YC6SO!%i7#rmvJs45I*?|
zD=MDC+Ou)db(fN(QFrT4q*2j+5`B8eLH$T*W3W=K{6|<~dg4-OkgYSG?BZwT-IRN(
zX{1wv{QH6{v>)JkC!V*RIY4?<^oGf%;&ZKg`ghkSM>-Cilk}`TPu@#P=Hr{L!58Ld
zxgN*&w5I{pL=jynX>{1xCOYLEjc5wJzI3{#z`=i{9-#jmai;|wv)2u-SgUCyYRGA{
zf_K7&_fNx;xTpW=umuHL>@|ZZ-cWvT7sw^Gm_|?DDzGP3(g3j_j`69A%vxOhr-h9)NbOa|}5u^A(wgO<@
z*Ad-JKd{llB@~~m
z+hdg&^U;B9HWpqWHC}c4*a}u&O(~3=R}T~0Dct4?@Y1m
zOdg-fPw(8aEtzyXw<7{~h|e;)$s|P_6Z%fR#vd+%HaER#11&WEa0T4LboZ0T^TGkQ
zu)zc$$jq^rP2^O<=U#XjJo%~I!v!sUyU-_^jr>60j_Y5MU(*RummA(^k&j4&#(sh@
zmifo}`4TdQdr2=iob>8waQW^tV_s4$NStEu`Ma^%LZ{USJzQcqAf1$xK5CsY{o?Og
z`()DVqDyrn|EL6AuDKSw5xNY=MB^4!o);lp)@k@Be1Bfn)@$!bc5B*Y0Mrj3
z8~pl-Kx?zK@>;C8w&lu}IJjgh##i#|cl>ldj$gOqC+HmK@jkr9dead-!jAX}bYuyx
zY0icIfR_9fvunmzM^|1FP$KnJ?fdm_*FoE;QM@!}0gd9fC7{s81?j7}
z_m(@C%su>YG-OgOMQV5DjL9rK5^A>oM$HhSTld^A4=KOE9m{7vjBf5|WQX@wrNs=(
z3sCVsA1Zu}bT8cM&jcVoE-0~gWg^|G=!e4tD$IxZV3uOe&A0~<%(1YTStBwL`EnFG
zn!}_YewW$mbL?Mi?A0RRuIf$}1)Bp7Z79-*sd2xXp8DEy{m@}L#4-jT#xVdfjsp2$MVgftGqAS;~Q}Uux$dnzoNK&h9{1n1$l7
zr{#{Xz)B!dI
z&k*?sZ@_`WnW*(@RrLB17W$3z6W{6Vp*O{MI_?2w&|j}U=|!~*aoiM_cbONP;JS&G
zwkjB>c97ZCo8XmiA^)3QYxs@*8Mn_fCO-bHcdW5{l`eZWv!P6<-V58KKJOT;l=^MQ
znBt0#@*x&}YQr1v+V^J*{kE$4Y=z>jV5d|@`*4~04a>wd4UlSS{C}<8ZWwWWkU8IS
zYWis}SHD3_em1;mym(v5EQ9asCO#&0!MR+@Or+oT2HV%liw!KFrFmSgVT6IZo^Q#w
z>w0jDqwdETsIQiVPw;Wu(1|X(105PQjh$#&~OsPL&O8pU2>W`RG|DO4Ypl#Sh@;<4Z
zXNnf0PhsymSm2l`6lXvS&U?NlG&Z_UgyTA`$htylU4Hge{Pv*hXJEK?`YQO;8nvYx5zk5TbW-!rJ``7Tt)Q@*3H9L8)^Nc&?d)C!;uanPIzsj%c_vUsB
z|I3m$TpAxhH{9rVJd4)wM!!o={tvIS=bTo{UZwllHl}#<*g~3PpaPG==^&KGJIZo3
zQ(WJ2%8G2_VyWg7jd`D$Mo;6WG5_Dj+cSTuy;h)6)6C2iXkHRuMx^K9`(sJd_&*p6
zjl;StzHcn(c}bdCqU9uBc{I>Kqq*1B$v>f<#t-&=ig&5!>F$OgcM98I?B{b6a#$J{
zjcIHV@sl|Cvm?YGXZEI-OY7{{Z^*LuLgqh%_3x3=;bF_^nJ$ZUEHv^Xu_
zPSh{PzTQpLM{lLztzDpTaaPeeyq6%q_r^2g5bj*QCGMLs7OW}jQd<~M+bj62La9IP
zv!qQMSEc-3!(2c3P>C&?g;I%B&D;Adc>WR2hcDeVb=buQb)$RSLe|}{&g5Qm(dfdx
z%BOxO6)Tg-O4RHW%woXNpEDdxu$Sg7*&)Sty=0?WlJ2n5<
z_kUP>7r3U5w10d~l9PZ@2?h*wag7AT($=D=yzS50pt*>;Ub^6|+G>wT?Y6aUwXVB$
z1w){SlxoyKr7faJb-S$O=nyQ0>6Kx(_)pamjr(ckwu=fq3*-QWBFyr2Ka
zkDQa4IWx~ZGxN+d&u#29RL#>
zJ2fMB+MTw*dZ2X>m`9`P4^+zQC+LTN?6eP^mNij{C?9Jyqv|E=t%kq2u0705zrCy&
zwLi}`MH&r7mE6gD4){T{6qYXhrHp<
z5$QyOW9@?rpyizF-y-IOKg<%}aB}J(@>;q>rC;^m;&<^jA*X&$uI7A0Mui+C*P+9SNF36t{v`c+?GV$%1}l9kZDb!F1A(Se=}*(q$)L@6;(aEt8Y
zLXM)(>k(hp=Ry8-BFH)MlY-ZBXosU6bjasd^B(yu*(&^gNwP$@UiP8aV?y886W!`H
zIH%?}!qgQ!;kO2R=y{BagjMg6%3DHSpx3V*lHs}HjpWx--)lg>ZcHSowif7VbjElm
zuK4)^dQWvMNAI`qeaGhgYHRzZUasEZEItPkgq56)w{9(1T_ojc;gb3Hl&4t@<9h=zwfU~DJNBhglX^wgg^RC&@4NY^1x8Rqbg!R2y
zx!rp^5CEd(oV3jt$(Ie!-)Fjp9bcUt5-75+g|!Ywpo2>
z)P7Jj#kPb0Y46o{MltRX?E%4!dgxIDm`|ycN!!phSsN55w>8lkxz6V=eI82em3`1{n`Czv7ep@LJwMrzU~1uSrdnf
zyI!)#Ve1F_+0)4PLVr)lzrf4l`{QNy67+lF!D9P!`9gDU@Y%d)>fMkWxK{Nzj@nM4
zHsjZa#T_y~utSQtM*2~)6=3-wZmdBxLMppE&@$2@J(zh$!i=~BBL%lnwH@}4$dRbb
zA3p2;1oPp$jBl>(x;qUX8&eKyKZbqctxodqsFv&dn_S-wxv%&=
zWzXF_wA3cTjr72HhIj*OX<-FU)~BD7@%T~mV5dX_27k2aGg|S|uZbU`)Xl4T=<((5
zX`^aU=gASyPNxk2-&3$_DL+8{tFTM|z9(Bgi?BPjelX3yd!qi}yX}sqI;Q;4s#YFv
zL9DMjPWir7q35_yJ2vVy%xro%%Vv7uI_#TEBCw0bud$g14S?5gs4YJ4#wpWp<}%x{
z(Wge$j{55H{f{3~K$rDVIjods@UZqv#_p|A6*t^#y9<8O4$jgJZV|duaF%woHFjm@
z!whyOM|}Ghoa|0LBgXj|h{)}Tjc%Y=kj49oo*i(QY%=NW=7L1H#_`#qu(5j@^@tfA
zdT8=kvXSMiiRx;z?yEJ2C=QVv@wqdOWm!Y7Oc>jD%Cmc-471$3rr
z6xv<*&-?2>f5X+O;mY@}$zT6{*jRl=uGlVpQR6rR|7gu1oJ5RX#V0q(%5C;T^mW)+
z>0G(T({p+jEYV?i4JkR!>Irp^Qa;&+qOPT$ZdixHLi;68xxJ+NE+ikL*O694!)Ll4
zycJ*Jq#G^9V;Y>Tu7};!k&lXIrN-y2X_zo!Agr$i8;=-GzzBNuacj@%cWu3?P3ItL
z??v;PI{H-}M;58*=LJ(=75qX%E=U*}=TxKw;v_AfK{eG~>^WBaK4!V6;Er{)Y#9yf
z>3c1s$+ng3s5ey&hE>(0r+13>)h)+cJak^~cjxQ>*|s{eDxU1JPB?(4q1HeR6hCg_
zA(BfBJSN4F1AT|j10u5g3@OrYNqXJ|o2N@5!t;LUkh(%l>dTBz;Y(fWT7F{Aiwu%d
zHrYtAS_E~68n!oTrM-q_S(eY-Hg3rKQD#?;0V83`gpG&lbwqO#uE+4Ck%_XvN~_j;
zL~|=_!smz#I@2lCHZgC+v~Junr1d^v?Or}ZvKS3WG=Rw&B+;0d*CJZF2W-`^RXGgx
zl5fU1_+~ssz8QJ*p<_Tqtv?-mtcnw@)|I$ZfVAC_)lsvY@aFi>Uj%S|a(8@fv~wu1
z_EGgvTN&8CP#gyADY?Eqv6i6tamvqnzk#Kz
zHU9hC;1bX>ZqHE!_tg6};K4Ny%!lN(xIcc4edHiKJ-MFH1>!WgA(A1M(V0#zvDa?%
zC&jKak>(fN6XD%`jeVYnXcK;oS#aP4P3;@kFWSBuP#SxVeE|~ik6NWQU#MSEa)XH^s2)BS5|HUqIl*92MLVtaW?l*zVKrb
z_ho*NIcjX`SixTb8})29qF5NeELdp#Mo0L34)|Q@#=M~R9I}VSzD8=qRnOz`R_Zc3oVh4vZB+yGiBE
z556@qXPfmo>UI5sI-XC|I+OFNuE5X9H#y`=l$mO3M8q>#cU>EP@^@8HV})-k6tl((
z>0LBWex!LqcOgud;jhf;R4Clr^Sr60Hxq*&OTM-nGK*J>xyHPSB5n_#i?T$RD|3^Q
zC%U6*BdV|8mSBC)`&bv1U$Ccf^|*raJ35)vem{rkqmgV>{-WJO?36?49eb9ib?v5=61k}CT+W59
zXB$r+I(6&>&CS8tk%wKm!&N0UB?p}La|b#n&rdy-YMb%NjDa(QNn*La1+m_R{k%E>
z_i_)n3CX;Ar~Qcq2;^f9MBa+_3#ZQo
z=3Y>B(0-b6LTE7T|Lk1nWSWt`YH^xGg2|ybkMq8?o{
zO!Sa(+9RqX_Rrd%=OMVbaphHx@MhYJjJy92*Fs;WRMA|euMCiO*5symW-KZ@F*uw0
zxAj=#k(^UIvq$6!U-1g+=k6rI&MSu6_hfuBxvOy5($C!kQ^^*NqORh+Yc8qg)9L0g
zaNC*bge9~<-U?WWLB$6@nT*mJrYfmc&)AU4S*e7ahA;1?IpXRbDc(nW2mEIt=_9+?
z_-vnX$#8gTKOBrbl@EfK45B4_`*q-^BHF`f_gbEI9&~hIBl#b6+c7#m4?GX+9vPe+
zzORSs@pVCFUA5#OrdDfVjC?UHNiVLdwl~%WT#m7z4ke6g0e}~Jyi&5QVe#|_X@WJ
zr^JnjBM=>(6K&aPCcPe|E;NRls3!!|S_^Nb9!a}1C%#kq^0XyY-FD%!2hn5d9+CJ0
zbv=B}viZY$NOa@fQDX}Bq21L@D!|}qQbjvWMh#neU+Yq>QVY~;pYddWsn6jx|JGxV
zRJxZ4L$H-FFdP3R{~QSm4(wV&bA=jFARdX&E@;pjBs}nh2Ze|SO%o!R{&!eN>+@?Y
z?Cv9B0dvVJVe5V@lvEQI?nd3gj>GoiJ)cV=G3*JtjTEh3)2uTU#RJpF3K3d9l1{{J>&G=J8s{?nMH|7y&r7il7g
zL0*dLLlf)c^XSF{;^wZ4+;rFk*V0@TR_p3Z77(8uj2gS`VDS9wZ;~e{`GJ<#N0?K`
zR%&qD!uck3m_@HPFkN+b->_N}OX8-Fb!y;O5k!>4nV;3L4fpG{t7(1x+C$XW7P9Y&
z%Sup%;Q3dBgLBG63q`TEkb7&}
znKOZLuvidl443YGqPEB%wWM0AF+TUlI3s-Pbnr7vyy;;_vpNc09UUu}xnoCdq@TPDO
zwMVIYCbn*6S@taJ-0$gL1zHF2ztbEUqd(DsyW1Mzdy`eDKkZNU@GLVC`h-d+pG=z2
z;)2=L`k+f=lI?>6prvt4uiC09)`=|M2Om^0()vAK~nefL~7-
zv*t}uxPwg!BL04IM@+9N-SB^ki{0{T_0%|So_^U<(TZS_^
zQ*d@6rxU$DRh{T=!Jd?moKm=^u(GK`{65Qi)Icp@U%;m0SPia4P
zRA&6l{u*3)HI9pRe&USW_v$4b`|tQVD`sOfS}ptues+qv9#`(n?#i%s##v?q6LZE0
zr!$lTY>Dcr$JPK&U7xc`>C;VWPn@@#B@WAEiSx3#t$CYZaZGT&q7V)N
zPS~R9b5}tlJ1x0#T05&OzQ!uAC2@&i&6um1x4R9l*A}x%e;4EI+vHM(*u
z9xybKwlm{N_du@El{4QXKvCk3!+UPUCk9v~Bkvn2Z|iR1yC#*C7pIZ(D$YoG1J%Oi
zKwbtf<+U~;j(G&Wf#qSA*-*hX>NRm@p|w@9GE-}_PuHHZPfw`|yrp>pZ?o^D9rb9B
z*r#_P-h7)%xLSepYL+?wWQApACUAL4yS_r@%ow%aVTXJW_b?JKwwY0^_kYiA4Uuwa
zHLB}>jAIGG8D|P#eM^&o_t%qh%}o6DdJ^iLH6|%2^Abh1I_l`kH!(lfJ!c13s%CtC
z-)~`?(#f<(I+-b}obej3q2X4NA@fp!&7^5!A*?MVM8}wx8QH6Gy4PV1rlgt;uLp7h
zPc38Ik5mFs-<#jd>T7%U26FzIr0GViiZ1&4udlwMO4wKC0*QhT3`^cne$sykT_<_v`Jr<+h>Yc9403d09bsK~VLC
z>ibVXv_g2bx4-S@77uSF&;97yBo#9f_oi2=bR)+?rsUkSapeAyV=r%<{bs^`w~lLU
z&Ab%%Ut?Vv8m{<~YpMTMl7<;ggZyFlav|^7DOI>qp>Pbehxg$3;9ggZDkAG+zJglM
zM%2)XFydh6hC2r4{`Vywt_bU@@}M5aR?QUNo)})i@;w8?vc5i0=;|Et%PP&uLb>h9
zRFmG?ar;`~c@L=LzbX{;ohw(9x^9g0C1IoM&2{@YCjDDCCavI&dwy}&C51)s3&spo
z;vtp+7E#6}*w@S8FrN>_hEm3fH$%SyO4;
z3{zR|bki31^ndpXjYceS@(6t~Xb^6-sXDRj`VG6_Od23u?&=9UkT+VRgt>loxLwF?
zeELuKlDYUn0~RhFTTN
zscavrKb_((^jSjn|I^j1(sk`78z$k+Rvo-n6|iceRCD?sJ@yLRtE>}Vg7i%@M}expl+`23;jF``=Ju}4mw#$dt%oY
zH5s#4U;cvP9<*Sks@T`~8^k(1iSy=hHI*KX89P_vJPVih1u$V;UWvb4dSy+<5)XYd
z+mn}3=dp^I4z#K_@vc&&l8NTY91C2J@z>#OLTtmpvuU?bN3TzZtS8Hp}%umDjQ~i-njn@rN#yheJiU1N{FZc1BXFhK%nK;y{Z))O9
ztc7Vko<*C*r+Y!ZCu6ROYXNK>tYq{7#~Qlp81E!umwHJ1*LJy&bDF4+gQk_3wZqdF
zWNkc9SW-RbY1g!NPCKl5nck4f-qxHcR5l=z$5MY6YRYV9C1%KDRKgppNwDilIVS(m$xKARvsRw|(CoU2=w>+A@j*QAji|$%+w1neHUHLLjYs_??wUVS
z_~4}^)D(3%RGv-dQqD%W9V*^4SD8U=o`2J2$mMwZ$wC3=Xe$5u@fjX^j{Ig1@!fLj
z$flR7#N2OwSH;`t7BAr7hl-xWDbXw=$x^V~PW6tX-+EBPx$*j@z*=f%`X*^DVdY>g
z)ihIyqDl9zCfoyV+cY+E?El}ZN|Fs>^f$CKYW0`jmwV{>kEflUyQ!Z}TVF+~H=o`O
z9+1`#XCtZ20BG2vYkil-#JQJpjiyZ%6Mg1p&NtceC;IJZXqwRFy*}RnQmofhd;^Oq
zW18)#m9zTHsgr%?b?I4F!*JyBEoXe@T1cJ*8?TU3oM(Iq!=6XUBaVehQ-}4@t8+5k
zVvHc?Z!wF_!xl*8c$7Oa*Dw~RiJ<+(?j$;?*drga!&?sVm))ox{??}rh$E!u%N@S9
z<0iDd*sz3Jb)NSnggqm-cgmNLI$L_LJMBwYH;bf-9OQNI5_kmXG@K~FgUt80-|5dG
z>dzCl&#XM8Q_`2Qr=f97*fonQrE`T(mmRj&7K-y&ZBUt9Titrp7Ui%GW6*!4-k2=i
z3wHmlU{B>l&s@U~n7hzu7Pyprdra22d_Gvn&gF!6-F*HN+L5ljek}j9;E@yMcB>8A
z$uS(Y{Zx)v&h1wI%Ly+Rqw!hqiyPbj-#3sQaz;DPRC!-4zInN7_#(a99P}bnAND1*
zzbZUk3JHWc2=R&!R6q{&Jh;av|M`=-7wEV=cEI^!Yq!UpL8G6M7ggi7(_6zEB{eR{
z)1&qxevgT9dbz6u$vvsN%nF`lQ(4|*lMkGn^<#=x&VOUSIFWrC{K0;3a5_f*D$F}Y&gm%O6jpkA11%2Q~9A%nU+2%KSZu)56UNCxlLa_m2M2+%|2u8GkRy%
zSsz>cqEtqNXRzVFXvGY=B%kdsJ|SVi>=su{d6fZc4SlZhwQYVyZXd7@dx%b*3)_A)
z+*uJX_}lKs1FeXbJs_Mo-&Y)u8Z&*&nZhK^j+l|hA@>9A;KpW+h4jc4J8|1Yt^H(X
zKktb3N}RjO;ft^7#{L>2v|eSjPdGKS>P)N?9GG5-yjOn=5ng_o3C@1fOsB3fG4fJBr+O3?`^nwa{KVKJaq
zWpnNYm-h50i)TFg9FIm=Q;S>5hB2jW9eh2vut0e|KZG*{*WCA&!#Eb{0
z)Bs9NgYedWg3?z#Iw%&<8K{g(gbqD`jl0}~t;x`n`Wk7Cr(dBNGE5nrBdvq<_43-kf_cOFjG6P|jFJa!FiA#IOZUEIX@&2*IRo?Bv
z{K7yFtWFu8Q`7_1(m)Tac~W{EX4#e{KI5F}fgZ%ZA?3t2q5R@N+tysUJW{v(@oo>C
zIdc8j8)FvT?SWHnm-fspxJO*-SBqRa9lNvT-5asVB`D*zFTOI--r`qag1)XIfc-yt*zrmzlCFL>`uQX~GJX4><&x>nPlL
z!c1>(I;S1ZkMtQY*#axx5KA@J{S|n9uER5XQCV$Hy%af%WFSgA&lGzVwF*e*%^Gkc
zef_FbmcZQj3UlQ3KQW&7C0ulrS^L-=eQV$|g)wn@8tJ(?tDzD4h7d^qL!?$>|19Qj
zXxi^f$bMRheGxK$wSdbT{wv58l&sJPaf;W2QiF6sQvI=i*7IRlXNSA@+GBK)Hk0bQ
z;+TD_6V&^G&3M0J=Pc_}O#F4l4Z9&8{phi3nHx{ns#Sm5jMSCWB2%z>6ljA#9k^VLhst>ZDcB{FFB$=Jx&48A&daUzZIpi|aVAkmi?gp;uR{T(99S
z&v)y^o=^HzI)j$liBpy$LF&~yl~7a<+b=1P*-m;~>QW`*!zz@PaKwQL=H2swpS-Id
zKw8-COYl|3=fu~87m>!|CCr0qJy4e=Rzl7PJ3s*-9dUx0aRmEO}|z`V1dWOeOSDTRL#^L7lVQ}wz<
za(SevMuVHE&K}{bwoL6b&qtqP!Bs#$Lz0kNkaA9U(!D!opRSz`yzLr8+DPJi>2^O@
zk|p$CuN}sZG+@ur2j^{)&f$P}_dut1avqK7mi!n#igsm;Chf_(VdM1KS?3(~R95Wu
z>2^IwZ=1PwY}>&s;*O1PJ*rHDW!Wq1#yRkm*TX@;o8;h!$-mRT!tW7E^)Lq8X`Bus
z`}*3#OiJX_H{#4c(yWorc#4#}Yea%uY2n#Bb{Y}k$6VGA9!**2g6;Zc?IDJA^n>Tu
zn;fldvm=f}|8n!Oj-+&_3-ahT=RBI*j*8Ztn$_<4n1eaCKjpQ$2h!Ws8D&n+CXd4m
z(6xu$ZbhSMoBOO!7nTa`W80Iv{)lI^Dh!!FHz*QX)FbOm)h5sI^0*i_*H2PC+j`ndQ2b0DU}#qoTd8u71G!Ic+j5*WH|7?B{C`f
zIR$WD>YEd`)MtEUBs9|r3$r#Ww#aAn!1%!fQR(f|bxUd?p_epEh7GzqORU>aU)bGQ
z!f(fKJ~fOgZJtsY;094NuNS1?GF6T
zWWe8>@ND`(Ghcje)y$WqND@_$`)LNf(PG!^=alGttbd-v9>d(J;HI*-2y0sNh=X2K
zQhn5;=VM?Q^W=>;s?)0=iR7{VaI>G>avy(?RAbBk!F*DSEmmlr@foXQVCiUNvGKL|
zJ1~AP{>DYy*4l8}ZiIe%XL5Y*{)R;Be%v6+C+kmlChtF(Xgw|cn(j~DX?^2xqV-$x
z_x{83c#K%R@5sJ&4Xd%*2qNQeuxEybd*t>X_Zd(8)n_d2i(RFs+^cB+)KKu4L=gyk
zn;K{jGjTkVzA67NpK;w^h`K%7tc83YK0d$olXOy~Ekq5r#L=viR;YeSM+h+Xbhih+
zdpa=R%7^=msY|a_5miRSMiq^Pgqu2C5t!d%rp^vGx9qRhgvE|tkRjLWxLB4#@CPsVUg722EUb*0`m
zI8lyI$5|*$z$$0ErUZJ`GWhxr5_Hxf!#&<(_HGkmk1web-fHa)`2jEX!1!#tjMsra
zWBW6&hmJZsGIZ4GS)rp&MTL$!@p|y6VV41x_usr3=PmAG*O9CfiOdaR#J4_y%a$q(!CCf@QI5lB*<=r_8PC_4;>#t~petwo5
z8q9;!Gp_guYjEbhvs|KGMqZ>`@3o>NFP6Oc!FDI@sx0Z=($boMCON_%HDgiEsj?Gf
zsdwnmv9C@wp50Gt0$LItQLcjY!5r);7IBSEtc|uuar#-r?b*j!9vSbnxPp%;^2SO0
zSdTvW_Pk6}Z;oy5IhQl_TEm3zF?Kz#vq3?o5Ty2+!fo!ohPjW3lK(+UYZm9U0vDGa
z?R4P%DW`sMJ68X$|DqPWFSP#@IQey^%pZ4ZoDH_G=~!c?o_h5-*!n}WnBbk%1l-ZZs=2e85!Op?;QmQd}r!}6u
zNx;w_rAFk;qObdQ5wy+)X;hL5YqiB>~M%n4gJ^4q-z5W&28-i
zd{VwHFh`(+Q$u5ROPcl0n?B>P{*H3)ob;Q&RSq5591S#WYSJfy7u7)H2Q8Xe1C8BJ
zQmNPu>=(arr-36WkCmxNOV<7b;-F_ti*P`0bH40UH>ns6fc)@{tNx-6DpT1
z{|@Uf)ZzSCZl&di1#%954efTbjFT3eQy|w#AuD{C)3?Pq(Arl0cuY0$!C*_tv97Anw8B{%QF8N;K?VbvvTL
ztLt`{5SdlCBZfGH{SEQ;nfq$@nYMt-)x8xp)ZUmg5YkK;kDs7_Y`ur9G#^`}z7Ty*
zlF^df_RfA9iYTkZrC|3I-fdDqCZgsTWNp!b9maa0xW!?u3Gf0JA&>j>{gTiDfnBqt
zNi~nGirFxAio7eeTtfM!oW<}q#;`|^-|kM4PJG+XKSmUl!ROpqyF}oJab&F>vxHZ9
z!(#&b-BF)WwRlRE3nw&hZqrSns8y~%wP!E6{_?ZamAFXZ}1>&|U$l?3QUmE=#yeKjkx8UgRv{DN>CK-jpch3vU)%
zgq|_n>ny)67pG0J{smscx?3H)9oA58qO)6Wq3#&^^So3We;n;+Nbhw=e8w&FJ%;E+
zaE`iB^%SAYo@$D?4p~p2wY*%ZwN<(Q-dgi>)Y_gsf!1&)S9v4+SKZ=`7}5oI5M1G0|;w8OS{x^?^a)3chjd`{3n@7N*jD@}R;j=D2j6G_@Z;=iQb9Y2(`@!d>{8LcqSqP=EB;=>Y|95||6vy_Nlc1%
z+%mF-IZ|ucwtd2zD)|IwMTsr(l&YMug{Ym5^&+ls#n+(Izr~44oc}GK8R&Ew=g&la
zamiJ6)$&@|j^6_vn45CBzfn!_mov_b-6_j{%F#l0O!2qSEsAxe({GbLICD%&)z$!Q
zN17!XX`}YY`$pa0fZqXkYqoAB_^9UE{(+kL3g`mH0RG=L%Jr0QMSj0W0(ETj8JnY&
zzz1PK2=}X$kX-X#lBFBsu&y-~N^Oe2OnT4Y^DX|e?mdtU0LN5jji~Q917G1RyEmfg
z7fSnB(;-vD@^a8~1DA4rH|Z_zoYmDvI=8KD=z;S}82Sue19}@sdVTN9bY`nN4WsRh
zHA#7~i&0Ow!$$f5oW+47#9-Va<)tIfqIcL*k!O+fVmC{9<;cqpmFp~XJH_vg%IzVq
zHpFeio}F{`fjq$O3AO6x9}mfYUy
zfKQ>)eiSq#hOO0n?tYPx4gmD&W2JSNTnEB00NBCuV
zw(!OHt-u{9kZW!hzi@;gqXe(bpylh(PQyX&N0+uRZ+oxP=AJDRE?(S&!$5~1mZ5lrs
z=PBSTCaZAjQpxkg;D;uwc7<<8`xC$W;@*)dx5MWBCqrM_Rp+meMy91*YOw{jttaNo
z@LG8pUbEWyg^M?;g!eo~;@X7w8r1jJ=p60Sz1JbtX#0y)W1UZ`u?}*YU2`2+6-tb^
z+`mO~|B}(aXB`+zC035C+gm8*S&=vF83_{G6TM_e=0u$TSSW4^ll%A^S_>!TxqWe^
z(%Ou7+D-efbXbmpHeAMPkmmkc)tBqAKW9q&^JSL5OEuC*_sGfR4A3m%{P0R2#H6A-
zq~kWw$!XL&?J(6y%x_)$Q=oxjnev5@$38`?A!eQ=LDuKYy9Hd2A}{RopWTa@mIT=4
zdnL?VoiEdq3sMhbA4NTr@5fBbvr=9<@=_<>kD1tKq`Y$Et()M$ELUPBNLWjsCFQjs
z@5DFW6scE(~nPfJj%1$jJ=Nww6O
zFrF5vmU@#sL#o^6fA)!l9eysx&7AcK@nw>w*x>A5Eg$9#&dGu=LY5U+8!qaj-hvfR
zmK(QGXPuK|$E1sL+Px2S;6{n`+aHSMwIkFc3CGuDIU#8dNIOCji&#+#kM-Ft2)ShU
zzZi02afJAp7_X$|si^m!o0z=M`EQNN&ayvf*RE?dy0NdoHeVjo^yx0hqV<~g+u8%I
z7Wn$)0FQ}~!oH-ei(&c0gE3e7|LAB)WqZDd1ba5lI?{Z>3QZlN9gewFx-O3LIm>}2
z5wp7Lfy$FA=9^QS?7&kh--4BrI@sZaE<&11WAOVCWzIcP=1Z0bl*p%VL|w#=m=&>A
zkSAbemJXOJ;$h%kc!Uur0+_*LINF(PchL*}{@t7L+oyZ>wkYKntzhc3xUKeEs*$tm
zRhDk-30MDaC;i1E7P9z&KBC(&Rip<#aM>bdP#?Y1$MKjqCihb4A~xqfy3N)6lX2}uhluyg2gtU+y|?uYi^Y*ay!enuCY{JD`wJ6
z+4_jkw}<>b{}FjUotAnxzcJ7|^#{_7uY1U+i}|bAw-1sY@v(UW<@xrAL}#pl{ro(Y
z)2qX}Ni*!mYH>MvnMZ*AnQq?eUq1wmyp&!j(I)FEVBJp@m#`jb-qSb&DgEtexb`?WwVbutfOy##oc(Aftz1xetswf@n8SdyHT&O=Ho
zZhf&XY)a}2c|9wGEB0e$G
zd4!}siu!F|lO@~s+(gZ8>|UtThDff8;bR}PO7~Z)IiYAP>kijW_6O(h=12a}LH$w2
zwj7AOnq}i`UxFJ;ObUJfOJ|nt74RcJzP!_3yw7*!IBa;O8Il|tF5{@YFVSe6pdsOT
z^bGd{tRkvO##;JyfOZm94wXw=!|2@c(J6SxwD?$?^?Frs0M~lT2|1ZKtdu1pGT8yo
zuO&Y-j|6P?e3w+?aB9R@fZq=B=`6FMFNc0w?@W$B9oKsx63R!P3H|v&E3Hzgy58N8
zJ=M-sSeNJdcFa?ZMeLACUkc&;ptW*|^bknL;Z>GBy^j@?N$J~>twhWXi;o?7%x6~N
zR)8a8NoK#I6_GQ>;MZtAea1kPn2-M{%c0%g8SNPXUzm!VO!zK|{z9fLotbj`TFjJ5
zz}d-Lx54v&F^G|^1AN#JuRTjV4??eGd|0OGv6(16S+b<7_?XUP@cr6Rv`>0#`1rK^
z7FSu+Af@H*IxWAo?k+kgrP)2F<+qAYiw;X^n$J(mZy8?{9hd9-$LZs+;y14zBf;ua
zdU`NG&};|MF@GherYrO2L0@K*`vXj=MoaHjyjzlGJJ1c19jK7@kcp*%G@Tc3*Brg(g{jD}VzC9mz`-H(J
zbc#&#+~tS$tFz82?W;v9Xe!riz=`HJ{@!Hg7WM3&{DQ-toE_L1Mb{xs!Pwoc<-|0c^W@gzBK8%AI?*m8nt
z7sllC$=DnD@wdyb3xrq~Htb7wDxfJ7Gbk^vih-_{A@y?+5q7OF=b(_izoN0@OJJC>d5HgqCtP9DZZ|pOz
z^)R9>rlL(3Ncw$8jwjNE@?gmEbX$J2(`+ivx)9LuDo+l$NOG--hX%{{E{;30Jr9z$
zZ9A=wChp?k9KqXx`*gLBsYkl_JPvzh!U-kalx$AfWGBm@_MklbX8d(IlP{WhRnTVq
z2e%Le|I{}lZ7yfl1?cC3LE{Pnzq0Y`@M=>C%HqH9Mlc(f10PmC`(dpAe8_^@Ot1hq
zeW+sDM+%_-gB_{juD`6bGtiBZl9#V^ZzSy>xGDF~4m%uj;0?b9H$aeoB&93kTIUH5
zXnNC1G&wbYqJH7_ogX_8w=JLg<&^qmd2M^P_3K~vE6^wU+R@OknEK}G5fiNMksVyu
zivFGVG2F(Do^lr;>0(dH?-YY|#Vt2h4t!S^JDSv>&8i-Hw;i^M%|Y6v+>x8{R0aK
zhvG0xIHJCrdikG6q!hsBWAAl{BXFLeyx1tjfRiSx_N~6x-BeH#csO?4ecla=6
zvL6aRJ1q5K>+?mUT}@7wzuP$yFi_;*mpr0(tCW9rzP6#$!fUimoffJKcS&VLje%9_
zKIvD+@1n*a_R>DwlK@V9z(tBQe$gxCRXit^yzE(-**(ql;q?n{f_;by}?^as7SdX)d#`NOWp0XW%g?YTxw0{<=3{l}+{#biR}sG!wVBGaK_^UzB;Lc`KqI1tQE*8On{%4oapH@74UeM9&(Nf@dZ@
z{;TjGbk@|jj)fhVejq@9)%8&+@!7b)*DXpVAjd{jr8QR-f`ekXkW^ZkHczyyqPSaH
z*tQV`7t2qpMcx*+-Q5L?sEPGE^P;~RxBsbHlD1CW3)u5Ukfm9d@J=w|p3#|wyyob(
z<-iT@QSgSQn(~@wjqSR)(tW*ZYc8TRvBq5G49E&+*0P@F{9T%ni8=AfBo$~}FLc-9
zhSR5m8`2BZvu
z+m%TVTb3*Qn9a84I#LfXEg*JGTflJpEPH1)$(+7iFDzZha3>t-+Ori)ss@U0Ra>b<
zqI#V<(OJyMSDd(VWojKx3GZFqX(lhWXiEU&{~5zozx?koyybty@D{>w`2U1q*q4XP
z7>4HK*BHKf{9X(PZ1+}X;xuqv^sXEuKW)nv5%(5-f+FtGo~b^?&vWmflgXSh@$0r(
zB#yI3e)kMRB)G)j2Uk1Oqn(nCgSmuugut)Tw}!%Jg0q!5X^&gicc)z_Oyb5lyTh=4
z!>_g9yBE=a0$k|A*)0!j7&$lF4h
z!^+82sT^&c2tn*grm&j&US~UT_9$!%_)zNkIV!i6&gJEwf!LH
zlUi{SiOWrfhpq8sq3L12d1a>Os(3m{PSUXRvt+41DP&8xF@4H@e<#euCva#rR(eL3s(n?Qw=^sBm
z3H7vf_gzwW`ta#V-LFY+lASowm~qv2TU)Y`+FG`eT6zh8rTUAWMh)Hc9i9qmky6?i
zy?uO{=;^xO7yUj--JiKS)osLGAm=!x4R9V?dF&yHLKobr&MN^Qg7}{
z3S-7u7DzCHl7g8I+KZoO)s{@3Vy$eA<4R6T^W@U)lIg%v8{w+tbky|aOTlr4bQMP7
zeZf*nrMDza2wV2r8N5R}1)S*Boht}~B2F?i5%gSC$j_ewSWZl;ygHCO0h~+$W=2{N
zyXKZO64i)$F|w9YG~$~ibCP0O65gO;Fw?%0y22px8o8IF#<+6)x5M`3eNSf@M_fY?
zdf_(>^an}%w}GeAah(A9!5^RvzXU%l;xYbSaZY^xt>N5C_{iS<&xMX<>OpN?O)
zF$GVIE#G&ZvgbB*=sJkg13T71jLab1w{On23C51Kfr5Zfyc9f%0S7EF_1-HLs
zqx3zcFB9J}(|!@ZUh4l*`dTVMEi5U#en-yxV+>39aj7c7FbrIUYRe(tj?phDv1WXw
zE1#5}S6&gH)n!BI$qiK6RSYsJSi1Rkv<-$#Ap$&>B>%kPV};*~rP+?j$k7IJ(og!B
z@0yr%>DY7P^T@G*((fyOke`o8=~tFYzxzB%l7!pe`%2gTS#A@$775dFi0M=SUcMc%
zNGQ_C-Q5{n9>xN^aig?`4B(j&$E6u^0r9QD3%P*!mf4qX=}SkPMhBXc394!I>pYaQRio3x;>G)w`qq!Jm{YH*5+aCF>S(?>w%T<#
z!^N#H^z>ze@;#c7%B{ANSKs0jBx%CH9Yv>18#)zlosFn5_32=`x&R$~Ri2+{L)UFs
zUVx{0HvJuBDy<+G1|=cIQK8m#75;F$pB3Xd`&FGZCx~mJlC%bIj)A;tMfYp^rJBr?
z!khbUjv=_5SW!3kQ7wFiqr#R-bs%EaKzU7woOZ_6s4)i$qxQY}mO4R_9ZDPvICynO
zk7eN`p%=cd7)0|9_U2{4u_&);E;A`OHtVaX{j;h8g0QWfpA*PBYrdi4~srWDi^S+f~6IqXxwyKNFv=}r-ox?Sq=X3alv))!%X0;Pj-
zE0`|M6n-7H8B%J3_|0R;3#}uKU+#aI!tUnk)pN!C;rHh2uQTPexlB2A6LU<>Vjg=4
z_He&xl=@5cC=Et4X0Utkh7UI+PVH1wp6XPX!fOye%&#zo9cA0qgliLOI0a3>(ZX35
z9jM8Hni4%tOm8=^eD_r|)q3x5DsPHzALOvtVm|R~jW;yIG`M+S5@trkOd2;=gMqo~
zJ8$38EP;1^)LD-vfJ9ZO(mzepK&D;P^s&T^>
zDxZ$>7&CRug8`idam&l>0(2t9_G@GftEBh!_T}(o*rB5LHTK`(9X6+UFR;%>nK{Aq
zo@ZZx^wJP|ciNYE#5rE5DVgiJvqr?7Hg2&C9xA}C=>7g!G)7tH8KhsD
zn-J+$p3EHt&W}#AY0hH#&C26VD&4S9>)}VfanSU3E7pU+cPPZw%d9Bh`>|x+gRgC5fd4($NF>JK>9LAp0
z%r10k)Iq1e5v?uk7FMP{^QO{1k4oUV7$v}iT@-C9a2Awux5&A>#N5-!J%JW#<=kdD
zw_VKrbRS{l=DtvS#IcBp#EC{6Dtemuh@x+Z#?m~XIY8JPV5i<r7GA*r3sFr
z<8rAFuRbM~`WdCFZ~VozG>l!|=d^o30ZpY{3d3Vq1;Kffi4r>Vg_W8p=o{LeecMry
z$E~$=Pwm=h`k;&9^v8tUCI!Y=x7<*f+in(l@}Ok~;YHXKMxS9+9%J84rF}&X$<>%pGU<8<=IP)
z1Y4Ecpgn1O@1R(Bkt8w8c@lfspkBdxwJxsFo$rp*P#g~QFT_;ZImo3xqWnBJ-*CnV
ztJ%0D4a=-N)dbG}W;Ni6>sP3C*BhM<$VEneTAc(A(=kv};<}34T#QX6rWk*T$g97#
z+~8`>WhJLeCV*%Es$>GibSwGF37CABh7NHpwXijZ3CcA{2?d9;qNZd*xb=sPC13eU
z70)NX5nN0CNybdNd#a-|o$u0Kb=Mw)ND(xNj;RfbsHaW3Q!EVk=5?6Y)d*>AsvO)d
zql-)Q!}~H#%_^Ik6!C78?kX!v{@h(s#hB&FV<%XgfDnrpssTL}gnAV{vNv5yfsIkg^
zqyhdSfla_TuV^2F$e@zMuzZlO?aR%5?9^AHKc8MuV%H$(LJMzRz!T#y(x9NC!^Cj}
zR+&pg+a@dz|ACNjmNzJV8)Oqoqy7%C-w6M{=R-*2=ucd8vR5B+HS)Xj{z9b_h?i&;u>M|
zO??GMP6YZYV&rQonOqg-vX?i=}9)@!8COd%&*Z#eC}W;MQ(D1gBG+{!PoIR
z{*biOWyBWP@*7$$!Zk!&&4tdpK@;37Ux;jC%2RRNHhZGFQ?amgXvl+f%BekHwXpP$
zVI=&lOo?b@pikT4EmY`9ZnFv>CK3@W4-8Y4&H|LigvpAwh+{Vs1m-?(W7a6
zv`2~|p*&`xF`^Mt!qONgPxDjG85E~U+o8fq6Tb4mT)z&L8>e;X;x>m`7nbgQfiO!_
z5_Nqqi?o*<2F<>kBm-_~hSr5HYL0v1H@s+*ZX8cGCm&r9~lG
zx6~ho#w8P9h4}lrG?`(hsCI@jzmdwwdAyw0kJ`>wm_plwlucU{F3pY*NOyzQfJ@gr
zXzJ4(1fDdA>dr@Cq@-gHYc&lkU3W+=NlbN+ypwfw~lWcP`>{=8gm;eXlDVP4g76
z`c(MlWd6pPjz~>kY|q2&)m;k3U!yr0f7vUK2CUwnn>o>WV+L86NWGu3TYApjBlEZ4
zX&Wjmk2OFa8C+n~-%MfxcUq$C#)Cz&S|c{U;MByJAm71uW&Ei?uBgH~n+
z-Voz8*ku^VzJB}so2HV~Cx*E9uBlaGTG^I5Se>W@Y
z@K^e-^|ZFG!V+1dweCj5T)96@RM*hlyn|HVnud}wSq&p{K6kFn4V1_|NhP+wG1xIQ
zcavCZTZ5xMg9VQj-cT!rmrlcqRt+txTEWADuN4~ox1Ba8_kJ&%P*9Jy(|w**T
z_TcY&i6sDU1JbyanG*jWz|FY*@p*)sfsGUEKg@oL@bjpQpRcuzaj-Am>J(=OXrk8o
zwuNZsb6Uh*4AD-0+afr-K>sV(yP2!5<8}adqe1s7JBD*RQ$(**U~#nZ-hE5lwZxN@
zrh)qTG5&fipY2mNWH8JWb(2E)4pcu%!-Qb9A^<;DU`P}C7J10zXkv6*_LC*S-v#>r
zbyegQ>a#R+24~A&LCr2i`xKZ{ft#=qB{tNaWfzuJfNv^QJXjiwUtVpCNJpi3e8k;Q
zR0%#^;&BjZKJSyfGUvxOz50?;&kxtBPd#4mdu!((huU#gWr%kY>SU&{7HBSpbEZDA
zoJqf)MW^nZELnG1(f6G(WOMM;SJKXO%`XOpE|7`lnWI*cFTI7H`!&i=}&FrYvr1%(GvKnxm;z^w2tj5^~C^=mDU2q-|lsyRAsGaKhUScy8f@4NW3F^}gY`
ziq_|3rg-)IRk|x+oYRCjQIK39;tf5Undu!oQHQBymsB_Eq`DysJ)n>uFsSH_+ZlCsNuSG2Y*xOab|uDeZmP
zQM=IJ&swaPJq~MM_B%u=5Yxi{FK2Hb7gd@5kDr+{XU+^G3Jf^nY63^4_?D%lY<&U(Xk!T5Lm^iQrfXn}-!RZDavc@fp?C
zTOX~4?^}O1YcO-kZic4JajQ9+Y@m*RcSK8>R_Md#M>`gtjFzSpFp+aShQes`Qs-sU
zZw;dz-y6(k!`42IIp0M&W?e^iK>aoHxx?`NX2K$+oYPKZQ5=B$_LZTP9)~pjfI!I&@
z?P1DH;tVs{9x$*plUM0z1(m~0{yU(jHR|XL=+zZevqs7sOrwP@J=uqP1EQ)u6r$U)
z4y*(ZXc2o{kD=?ca2<6FdS35K*9&m{;+@wm?F{9_1)sW=I8<$#S|f(=k?gUmFH^W!
zxH4^j5RsiE~V~71rVQMaTl6GZxE;4(}yp!TSh#jgXmDd$t97Ozm8|?8}Ni
zj4bO?!w`~Nd#54q$dsQ*`;NGBgLD#dK4C(%*;RO%bOw&50Jt=)=`}v|wLs%o(x^B0
zbu;EUcIHca6*&2=5iKiL#aI+OeskSA8?u|Uez0T&_P&D{#qTB1VN`Te;6r>F;Njy}
zjPtmBeX{GEqF`ueT2{OoLw!X}BrSMe;_a|Q5eKSpa#3xl)N;i6@!)Q0Rik+Q{whRr
zLJ&!uqC#ZB7eR;=-3gJaP2CWwJNl~-nb8^cD-dZWh|CH?1XRxXYY=%=r$VIuQxzif
zu7)6T|22YV5F&smL4-yu5JnJ$fB_-6Tw{L)F5t$M=fH;(T--@NhYMkR`fg8FAww|%
z;o>mlaHgyQ!5RpUfpZ7nBta$wo~#aNCDEwKx8@&0j0mjt*k3VkZ%cP#pL+F)CbxBV
zdwQXIcJ!=z98~DE9_W!@Dp+6P5g8cCHV&rVYA9ZiZM5Pya7fb$90ETI97=L`V^P8a
z6=sDS05k09_roXXASgsjYs=SwkO38qP~`%xksJj~qWI1rCe`+^e63hA{|?y>&``OO
zGUpciL{RM^5wHla82198O#BCIOT>!=y@}Q@8A$L8@-cf?+N&VtaS^EWLjFlBzMUg5
zpl*0i{i4Dz_op|=0|@J~AgMrEms%AH{(EUJ8g5^U{J#pkUDzYB_FAUzj?vf?oSSJ^
z?o#_3isblNThCVn+v4vIwskbvmKc(cg-cvczRBZ9c59VW
z9J*J}+vVzYG5WlTgvCKZubfClP=ws9Yy9m#U0y?R22=nDWwgGbSv8q@B+b2=q
zm2+&Eh%jCGCnQh1%)?pVY`fp7TH0)d|~5SeIe8vPaPT
zrSCRRE<_{=vZCj>f>5uBko_*}+8!{cD3$!99Ac=Cu|%myOlBKk9X}SOTe+T_y+QGK
zLGB*VMXgncaAJ-iciH7c-DqQugFVS`Ip|45aMefBQO9KOX<2b?VY+kpy&>EUVS{-J
ztz+y5e-HVqX(H424|8MfDf$^&DNlS{N$ce!N5l}0;861CNaBT!?b?v!KvDyF<{S_~
zS&^@D_C4M52Jw>I4AhhTD8UKeAFQ{({JHzCdhh5~cO5vb!i(UaDAM9qCvi*%AOUp#
zL^9D~@g>k~c=)01ZLl(hq8-pnRoB&8@&W41fW|o$`l8}zXpAbxqxM__@|6{Ev(5VL
z{^6*>R~bRA1%_;msDvWlFo@jnEtf;A_Hb*ZHfQ8!)
zA=%C6NS_A}gB1xegzebP(`X0zeLF#4onf`d{8uK>Lg+fOc*qR_RPnSiPQKa&E`5!K
zSt)O`CWC)x71;i$^w
zs>dMdl83o1Nu;X{Yao1*(<-e=3QpDeR|auvNmw|d&xYF^FSxX_SY#~??S@OR8#Wp>
z(#cDZM($C12Ym33WE{v=L8JQMUqaqS;FuA40ECr@_FJ*);m{f*jb&)25OrBgk+YQh
zANgL|M%c>i;mBs!a_*adg;s|qlAbc&e(KR{^psI~>g}tcr^ezbTA`o;=LWTQ(*VkN
z85(mCzV)=@LUU+v%lR$4GmyQg8J=#1`jNw-^9djC9B=%tXI~ZV>SL>!9WGP}Fv^yF
zai)~SUXs6paj-tUgXMWgxP^1dr}u$tK2~;LrJJ2%gSTA)_FWC?AFpP{l(wAvWR(O9
zWs9vh7kLtX8ZNYTQ1vKe!%tm=0E09mX)|
z2s!Lx8Cr*$0rC0BOwdvKzls;
zRMxaME8dJc!e!1O91B}xOWqREcty&hIQ4Wbau*k1-sfL?3$=w?YXaTemuf??VJ#6x
z>W@I)`~fm4s0@6MKBB#wxGp~=u0%tAV7usO^=a!wqL>0t8I89wFJX^`e1f^BxuHAd
z`aR4QA5|&ce8vopuJCKBR2rP`3W}Khq~PHKN4POe%DP09KzBC4)(?U70{N!R4|z0I
zD>Yb^8M~YLytL)m=be<{gy4hrwT}6esmuuLz-)>#GhWo6fJ}P$ko^b;_l%|I_Y0GlIVNXjONuRgKLE2&|Mp{)eMC2bp}2HmNWl
z{1R5+_g8^A7lAnkeA`5-Fw36QF)yJ7*?&59iFaB9blh6_;Q$85*d}xP4bBd}r)D5_
zz6n^vg7!T0jg+0??SG`f=PjX@;7Xiw`fe4ju9b3a!1{23v)1f{?tcEN8QEi#+-|>Q
zgLVp*AME*gt5OKl+utKRSNiV1bKh3?gkq60@^(;8j#lk&t89SqJK!`G{N`rNYb|?-
z)+5a|Js;#bQK^x%iB;}V(4Aoy4C&5}wB$uSx=rO-Nq43lsVUbE(UgN94f*a+HI#WP
zW-cHOVNyNOLZT6wdxQ8=Ks!czjM;ed7GxidWIdtrY)8&GSK}>n(TQ7T7@I2H=7;+;
zRK3=r_w@#ErGb~tEz(3f#p>-oR9-FQl=$P_RlkE|3_XC=;ONz9aC~23AiIJy-C;^%
z*(tN|UYq)!wR-!fJ>DCU0j-nz9@nXNG*##Y*c>P;KR5eG4_#qP-iQZ6T0*Q&NL-2x
ziFXx=2{IJz_#~4OU)T)+@@yw4XlFPUR%nF*8=37s{DMYeBQv+A>HV
z5m&nV{<$BvoU8FTB5eY&xy@_~&b2Y^ykPl)r+It(mAzR>gRcjbw>nagAj9)xqV8xxN@K{b~
zSsM*PKf2lld6ENNfo`1#FO>JxAmzKA7KRJ#dQY*aWF3G_pS1%I>?brzP2tvW8lNdV
zNmRIX&{spPJ5u#&*QU;V=J+#|wP&bvjn!$JF=O7jK`SKcg{{_bv)I#VV|E_Jj3Tg0~Y?%H@v>7v(xJ-_h@T&?uwEC^|gNjN8VF
z2blQF5@t%ubTg*<+l^rcGjV>@}cIumwghx;69{25wOT&XP#mWL;qF=ue$ouRkD+9+LfPH
zx+`QK>V_}bh$y>vPyE}w_cs2Gr@eicoNr5logC5OKO_~f2QhaCfq%#b##tA
zo>L(p8ccS79zj0<=%=HK->_QrNH@Y>W~(d|qBlbS+mhP4pwb;_pLiHHKj5lP;T(XO
z=tH)ZEN%l~vpJz*>uZ6Vc)oSeCz+TN`t^I{+quBp*6{yZfQFyuZjH4Yn(0n`TE2oo
z_g@6n)wL(Aq&1lI>u{GaN>==oISuT*7h08abj6-{#?lk>I0sKB_fDh
zZ6<$n-r|zshXg&KgWl2I6T!RoYwF$jL*>fdHU<(Ze8IM~Pz#_6%+3~xY#BOuL=kke
z=pMnEd;Iizs&j7i!)I9EhFWFtP=^mzL(NLDt|oM+9Cu#6<4zF&zc&GoZN6Y1FOd~^
z0enPjnbR%oq0mZ9{Ek*)4p!o2tVCUpm3V@AvPn90LPM)C9l0@KQ%qekQ#z^BB-pEL
zoAi}yAvrLq-v)*SMvE8=W~S$1{7%?m+ZBevlFxfFf;5zuRYAY
z292HOPMtU5E}|~?pKXdZow;Yb+WW+>O^uN$6cvi`KM)Ula|0Z}f
z$^1crBxua-k-5(Nr;(w)`(+v#X?4}nwWMx+3^XR1J5F|{NYI#hRXuU$xxzD`G2@;k
zTqPRQazpK<|L@ex5RGX*uF@D5FedEN993aI=S#u>Pltsm-774=punQ3H-AvQTX@td
z)BUyna@?D;jsADl&~r0(f)ezwrm%KBGi0xaeSu0`*a
z!w#)b!8KS@Si5RXabKkGz+P2ElBTMQhhE;Tek12c
zr;YYkXfe+9SvT#XB%)@b?esoLjAi!hqn*ns?+W~Kr_>G$O3y!Hr=)k^i@`og^zP_;
z^e+5kv2yNV;1>({fTzg|=<>yK9-i`rw42b%5c)xPbFR-y@?I&mVYT1V*oLp)r0g|M
z{N>4p5MM{qW{|%9jc7Tl$-p~diehEB3Jnr@osb@b^$!U`j)w-I!n!EU2uoB96S+^5
zMj8O8yz;Wyn5tFVg*`HjS|+K4Mt^_tCb2299of>cN1Z#Wc#TTpChYID+q3W~mBj7A
z-JU#3C3`e#l{tRX$as}K&{YM$pJ3l;=T9$mQ%kKMysPF*Cy9~jfU9s1d`mqfPZsK#
z88#88>;~NcPY8?1`S;ca*xDh?jCYbB%wziMf;)_~Da|oxB%&*omEx5A(ST;LO#sI&
z`3FN{!IAXXu!zuFy|wCEDsjB3{72lDliob`!B38UBU$D5xhL|~R@VNgxp3q$$CU>|SNd@#_S7uKXtUWJGdWYZ%`vaRFm0K6Rx}eC
zfM*Lc*M7d_fZqWJf64!#a<=`bc}-8N4fxFYBmSVSo;fuNpLy)j0O_7kG5Xl80E?M~
zHo|3;HA;);RsIrJQRf|39%L3T6F4VkdX~y*g6o7nop{aptKO6_YE)Yb@H!#3%P`4#
z9JqYT+f!0jEjY$+hA8u?S}QD=HR$6Imp61T@(fyomW#Qa@L|Ia1|0?T$ZMdX5ic>C
zw3UZK{DD+wHDb-Tw*2|dHKpk4jtx2$yT_Pz7Fyp6hCQ;gDQLYocI!*R!ds^hwWG+D
z^Sqz+GOXLJ4n^|iFqH5-km>GnBMG*c+0de#Oy*e6PpC6i_
zeH#G|w$V_|T?8d|S%JCW@xj{@e-D~KJU&T3+>CkiuT3X;R;8|F(c)lVA#G~I-ryRU
zf9;uYl1X1l)CBRlO!g-#UJQzL;++5k36nv5kQSW6dVwJff{xw~-7h@L4u}l|q0|iA
z--x-_L6(J`4l8FwmT$NNQR}p6y(&c2z72DCYkH@ohWa+*Nwsg@
z5dB-V;$sx+YO?i*>~Lf?KhNJ~TCre1^QrJnl(DC+#JL*Va-c=(~E)aUcQ5zeuZ
z@%g0Xh|`izZQRo#o!Zaulx2qQ5L81Jq4eEVh^gLU9}X>T(3UiRl})iEA*RZ4ml1Fo
z410Dr6$Iu2UaEyD7@d`ukn6Kd2VOvG**d27USzX&_4HNh#>
ziAHmwNS^TD5ngp$!SiinutL9iw}&0_*zZeKt^A``R6As71$cG9!Gevi(|%?;un{m5
z!n&Z}9l{8|p`#6JTNr>}q&W+S&~F9HOMJI(=%JI(=%
zJI(=%;5mIWp!(_j{K~(7@eCijLcQoDezZrcA^+D2ML;90=pj&r~wc&^w{Sil13_pK+q+aNcs;Lj-QuZGUgLO0W8
zSWrDsbi5y6;J?-73g&1GQMY*1Jyq^>y1qV(O5wq?A6z$zcikf*`~MBR6>#0S2hj{f
zKZtsSiz5(S0Dfg|gvM604STKw%0fB!onottVOAu0ifXG9lU
zjfPZx{gAp8vMBJb=^l=Mk!?iX-IUJJ0}n|j!3p7v#jy|-6ZJaEKY^@t|Ne5hu%Z$E
z#yq3vBW02que>`2*>PZ1a=F;14}6d);8C7nNJXEry`9WKSs
zB~mx<9g36vNsVt;vKs7Dt^_0A84bm$QLn%o1uDHM9HN3^E|p}T@G9AnT&E%9X$Qc6
zzCauF@>o&z8+ETzp*hPubZ=z=Yr6nDz`z47D?a&Jn{*Zb3dTQ!
zYOENMa%Z$VVX4E^5jI>*<}YdqmV}$Cb;G0AWmgr%&ymH(^^5xsbJN^hEs3A=CF;sI
z#?jRUZ!A{u;cAI_4Lnjy=!ww1Son?sQ{E%%9$nieCLlN>bW-P
zD0a}M3N7p~tnv(2!yA#%W8An%~MJvCjWBlyJF?9XXa=J6jSq1Lqo4Pyu
zMDq(zm+4*b43Wi)O24oQvM!=ecl0K}r>ec7ud|J==_dFC$LDzTowt&6Pcp*lz;sZk
zS+wF768)KlXL5pP?+50n^daOy`qUS0;=U2R0$w7z{a(0wA%hdQGj>nQ{F(3woertm
z!eM=Lw(kMYQ~4sTE>B_R_hhe=8xcdnH?0f&-0AP^9hUGYZ2k5z
z;oXftHAOyji@s~-clQ@I2A25rn!6XhA#CQCXhe@8)d;%)=CY$tysetEu;zX)hT~;_
zgMwpMORAx1SJqWyLtIlt#ZLr5PoZw<`{@?U33_!T#h8j6!}VKG0<99|8PUmnmA*JO
z1=%I(`gtYiz7W~Tyg$j~)~(ne(NpMWj1WcFdYqe)kz@Cyn≧G|97V8sVcYdYpew
z=gu7E$|qa&DT$zUg%vA>h{n;LLUFYa-DpQ^B|^W>46{r3&VWOse+SEQE5(G4{yVPZ
zA%{wUj~K8|Sg(5@R4C${3I8)Pus61(PJa#mr=NQf`{Zp;{+a2v8S@^981@iqhz~tu
z*5$F41<3^k+ELDDj=ivdggmTxtlfJN78NHajjGpwO?AboX3dzQ&x+LCr7gREC=5MQ
zmsh#0`l0mP8EgOEITN&KlDi5~GrfR21vAImcPQ6-FLlT!
zXtrvns}b90oJ6%gDI_{oUC^fWSYjE4L_hY~lwL9ZO2h+tIE=*Q1Kp3c6Q%UeAWW-vHX<*}
znCl^F)`%VW*W1Y*@ayfk9Nq1F{;!_x5Jv(Zmx5vSExV7rV+QX;J7s`@-`)T(@EP&`
z8>IR~#=9T0yY%^o*!?^s*PqI(vYFq!&aBc`H|sU0mkSK^_;`xl$1}U!rv0b#JeiL%
zmU`Hx^vxrq49U-*V#*nvhMqBvv<*lrp*B|O4=)!q^rnR|*-z#<^-=n%%frR$4$A+Q
zi0Y)ZSb3Z*nH7
z?^tJ1{=sVfcNllM3ts5Cs5Guni>CK|H)uYDl0e~W5tOyWVc_~sTM&wBRBhg)pIn^9
zrneiQC)axPsm5yk8ST?!*9NiPk_s9cBR4jKQ*1Dz%5B==qfd{`o+jDb4eQeBDK#3~
z%p>|5QWTpt#IPvMDODF{BFkxFe2Qxb=0UvT`LP305Xe01Cn}tB!|`%wujJE-ES-CF
z;*IK05&3}Yp4w=pD~)0r6#m<|JF2=1nftc>{wyo5HvUOx9yyXdz0923)hB^Jy{tdy
z!#X>#%(Et)F&DaWDPBT8Q6Fb^Rpi1$$!MPHX4de@ml8Fm)6H>S3+2u9Zy8gcomyyo
zoIL%YX%C#CTViU9~f95|RuvfJ=#d7=?INZ@|wBed8JPwiT
zZpF8musRu6`iXZ$Hh>l1PJuOw-yrAvjgV;)P$@bLvy;b~^{su1@yz_Vmg%n!q>Mh~
z3nGMZ+O@Ti9}M}{wfiLN1w*;16w!(!2AS&au|bkBnU39K>*nj#DBFd5RK6RMP*xqE
zRIowbc8Fx6maYHw4|V*$ou97`cMmO9xU#kiU?<5#8;Rzx*xNhpF!lM%%fHP)mJXh3
zLqOxCWFtbJBWU^IVchy?>zhwzE7+vs$(vL3eAD^B4fQ)eolw7Hss816vQz0xZyjsd
z`lsV{V)DXv=zvcc^<4fTM<2xh@`&DmzHPBB8`-yfO0I^*#p8Fc^KrJDzHS~Ja$f+@
zcZmsP^^h9<{2qD3p>-lM5olE!E#_({`%#}&yu0317g$f6ZHfVu)^K;Oyr18&mLpG?
zGR|}TdY|fxF&epnk2jqR#JTGc_sh&%A2lWP4SqoPHxBsMDZFwDi?oV_JJ)VmRnFUcFZp!tmVpMb)$e@1?P%5?Z6tNv)h
z;h~4p4@~kuRhPN%nLS^B{q0vjoOH0^PqE@zqlYhM$G}cELauZ>ZIOO9@i05a>0lEz
zFJRus-OGws5P3Av=(ck_Q5%83VsM0?)JvJ+hP8VgZ#L?s^qU5vB?RH>!ZWB!nPY~8
z7^6ui$)ws<&y1yN2ttm$b<
z>F=h8J>K!`oa~d?_Gvq&O>%yg7CvJh<>haEVmUH9wzjNU+{I>v!xkKis9N;q0;s?K
z0iDyfu!eYKa8(aVwSI=E1+pl-xJGC4x2-qlHnNTg{%()S`l8AI`i4^bBgmlLm}KUy
zFUfTm)|>Tl+UNUGeweaStO-fVoWVJB%!N6Avun;R;`bdhng>f$;yKV8zqxSJEt&;K
zjz59T8q4APgK$3qS#R-VGVjwC=^cw2<32PXV)QKz`$t8bnb*B!I(T8d>ESR$YK7h9
z;VL!sy;yr$>3HPt8g|3X7kyw3!~UNovL1cGbb@y>FS4fe#`Pw9<9hQS`ZLBNN0@$q
z39?+g?BMtT6C$4P*OC!63OU{TznW!!A&GhTB%7tt3H{D%t3&-dRe5=Rhg
zmyjWUyfV%r4zbN2R5x7I63$mUadbKzAqY(R*Uu@?xG5g}#urWdPpn7ZUX<%ktRIJ(
z@v~keNsRVykG@v9YO0UkP+9D0?|9UsXA+B-n?^N{_CgLq>vx&z>&o={mCNPL`q8Fp
zz;CxcO30h0DbEW>^}TGH(=HU9)v^tB{LI3!ZeyLP{`C!}QJK-@MTg-9$Qe*ke6Li0
z(NHd*)gqshZbCn^a~&hBJPR*`4Z8kE#(g2IqThRTf(J+Yd7V&j7B=duIw^B3S6+OW
zvD<|eXSKp7hw;=54sU9k?ZRfXX5YgJOYv>{mz?K~4o%FGa-0e7!&>+_ZGGk2So=#6
zX6H@tS)ZJbwNJqBX`r1yoSQlR)yD|a1bHGWYz$|GRWEBjOLG8;=nbzpXBNpjnn#zr
z&w@TD*x)PmZEW?cS*C-pZ+Q4P&64Ti7y1d&=kX2HV*?KS(6Mbh{T|;B_|UOy*KyIK
zHzzLcNAOApKXrAxT%T=|>W3N|&J^2GkL$+}{tmZyWAE}t1=qd+u8rqejCUjNjZ#IM%N*00ucvU}<2W$Qa+^LgCC2w^mRyT*ouP5bpU&zh3^=dd<6|?6wK03yti!zL
z4PN7}e^TCK$GU@e*JJwf}1KB{CK=Pb{|_inRSGj^pf>s%*iW1guBaD4=pt-dOdX?BacQQ{A0}C@_!N!
zo8ZOTVlTY`jpBeS44W9P7ZUCR#S`wn0$bO$L5>03;BrH_;m6b$tVESQ`vqMJ$L`P8
zS=pC;L`C6C-Ipk*V^Cs@<1SMK>z~C6#w$8u@O?bpXKNp19Y($%n>dki#3aVHZ0&s^
z+?}*~ZZ2XG*s06#u3i{WjJhTk^yV-dL)n>>EP6_hwhlXQ!>)J{)|9i@6*Y$(4A;-B
z?1~q$E7IF0%O&l@r9@-RVbEMGge;iwF#{T&7iCs@7|r#i5e;ml_M4&;|HY;)Hqx8Y
z&~QCl`#PkKOIr4xiHs@sl6G-c@}e}2qof%)`O0Z}qGxYY^o${yKb@MKD{2b;2FN!H13&M)D?RftH-JyAk&6&E4?l^aG
zwgtFz#DB*fz#!5W>0g{BBwS$#*3`ny%%mVVMQdUJ=zG(
z&AJX)tevRM(b-4k$jIXa(LRmDLsb?yZ6Euyv%x><6>c*x>i*G_2~R?qwcebp=N--9
z=F>J}^(_C)>mzMtXTLFP!`;06bu06&AzpH}uN>J}Y&E3YQgX^fwd;rnRxQ-XA9EV^38VY%o0Cm8H*!$4WIXjWGRO2^
z{nKqIf)ZOA@Dw*>F(A6N_d4j5Z(qCk$D6;%sOoJb{zLqO3H;}9tMMpnwHPC7ouUI7
zUNqKw*3@@H32rwdENDl2ItC3~j((M
z$}itPdhCw(y?DQr-Ve#G>X$2Cpf}g~S@7QRa^#^Ck8wGpyy}WySn}7uM}C-p_|#)-
zxX%XAN^gGRu^X-MqQiqQ)*3PRXfyO*XEUab+)$5lEp1n$2$Jiq$0}B!-OG*
zE93Yu)08y$hdDIdtMI|QZr0QFN*UO=^+>+A^Aw4|l9P^?sHhC^Qtp^O&l=D{OS60umSxl_`Eo6-;&@?+y
z$3e|e|I;^;{{p-r%W)?8+cZKLj;?5JIUW5EYRgS@9ISQZq9O%&RaW#C
zX;2_c(E=*>tXiYkeb=}2_T66eCcHzTGlBl`DR`I}&7H{ND3KQ+d1)pali1I^<>Azi
zF+ahlj$fSHRl?;gwk#?>P-5D|j}``PMC{CD?V{p|ViiBFSUs;rKAbiKbh(gl;nxN4
zdphdibx+4x8lf*82g5tR%|Li*mUB=aX>PoESx%HG!yONN?`z8Fij&gX43M?lWN)wK
zJzZUW%*C;cdGXCYj->%TB1d&&MF(n~r-?WRC#Mk!R(J8Ft8>clA||w<1X{&Qb)J{TmjZ}Ih12-R1Hq$D%$2jw
z21f=@yoOmChs2FyPY#CP8u8)uW}kOijGSQYw#UjO@i}@mjxzbX)?a-?wLF*_yW;4a
zG>+X@RGR4BDetuCS)sf$Sohg6j7LiL~UD2I!G&^g2~8kJji$Fi^n7&MZ0GY>quxCD5;#mV9#HDl1
zQ%X!(#&|~oH^S^X5F=+@Qed-91`WYi=?lnLHa!_%k;Rk^vd^Mhc}V@mkG=w1l?Yo^
zN_+@j_^KIlQ6&EWb!9V?V0^%if&aIScno|Wvgj4Wxe)(mB$_$NyUCT>9eg2r5!
z80C2bngmM`vVJ4?sg`EjlyxAEg;yrv$|N9*AFcS;?oo3l)6VTa
zglKKUB9T@Q={vLc3kk1-W}t`8mifnD7Ocjf9!xv-?OXP1r65c;jwjjol%*NtyZCjKQE?PsUT-hfu+VY*7Pze4-7
zz!68iWi9WmGi2|7EyDPK#ui)2!s}dJRnDEVcox=AqO+he(`gNQcrn+MaT9VmpDWw1
ztoOK#xo(MIaCLbD^eR{4KHe$Ucda+`;kgUmP_G*$K!(}jE3)X^hsbK+$x38UW!;5}BsJK%M4|z;(Z#bqGnZ;i<|-jC((Y3iLzp`Wbmx`pwA(=M*jLVaDE{!y
z8NmKrt+867+(o!DusSJ)=soXpD^Isx`&HpEfpW=~;76tu3&Iizq#&TNl+ErNf5cpSAg*CpbOXbnn!
z{xTwgQ_aW?TJ7>f0#7koc92EDzJq-_#~|BJma#U`;Bhq;IVF#)qNB8=den7fWJb;$
z%c)e^zN4(P#EUnuA6A*_ca%w)i3ai^$*=eH9m?S8M!&Xt6ygMxHyTor9TS<=)PC^i
ziBmcCY~u0la7_9b3g%tth#Y;4N@hp6V!NEA(9C@f1IGZN0bZj#6F|N*9
z`>liH?q-i98nIW0{a~zywQeB3?Pdl@{W{J6oh
zWLU0w*`!>L)H~O+?1$XN(dKaM`9-~>9IqYVU!DBzgMd}3b2KRB06;I-v7bjptG26LEVt7+d|`Q%{}V>Tz7A%y`-M=eI_n?y*0Ic&b&+}=k+
z)H2x+(2(Xb@_+)l2HxPbYc8%HTRrL+_}0D>gI2NPfy3mPcMy^P9_?vJ4R_ro4G#b
zw+AtQAbB2?TDIq62kID2egavF2f?m)J+MH@nOSj;Fc$rG8KwGMV}FIhy%TQ|-&Dpu
z1N81q&`*nzAXX0k1okDPrbPl26YSN6n^}|JzG1QaBv!v2lsVDJ^)~<4PklIEa1$@H
zYkQM{YbHF2z5LEt<00gI&dgyxbAp-zqZ)xxv&qNFAf2)?o;Nxlbz7^K?oZwEjy%f$
zp!`?lj`9rEIIU8>-=KLcdE`mPY>Q#!zME4=*i4{Db4!wQvNVF{qJoLl`o>ghbNjA*
z`{`YnCx#oKR)j>>BA(6K#IyE`1|PVp&*0mHwaPamA{pG@fOfs7kn2aj9TF@zo{r8I
zA+mvDisMQT!Qx|(GB5J%)0=o`>dbQA>!6Ss+UkxD?7Tk3wv8um5M}fsCuD=3+7JeE
z;4aqrN2d{ft(@)Tu~G}0&5rMUVID3b5j#a-;9q$3PA7Y_M96+2GA4Li=*-=-xMjM-1QnFQS)?TBMS|EtXC
zC(Fr-1A7hXmBFsFN%K5Br&YU-I|tuyMV@!nj+2)#iFSB=gQLvmh!QanH6%-}lLtLc
z1Qm
zu-)JzSfJKhlx)LYv6Lm9>fyCTyn0`K$Emz?^}VaG8&RI4pnT&+hCM6nM#xB}*0WPH
z2uFTV<*qDPcX6{5xta5xy4z%1Yi&t=>Sa^LT5C_Q`{ThJzhqIQOc72+e;3RZ5#N#;
zwMbw_YFbiXeamC4)k6E0x;K)>Sy?pjagUss8$Q8YB<4!uU}I_1fXT?c(jX!O!pvb!
z1!33OhIIV?_7Qq(X79?PcJRW88WbtBKu&y!uH$X#J44%TyXj6=FB)NvA+NkeXjZjht4Z
zrj;+}c)U};4;W!{91pq54<{!WpyCcgVjv(70npsYBR$lq*|Y*
z@wfufi_neY*HL&>}9qo~mTgTdZfRT^88RlSjcqj%YL4;!ibUeL45Nl_5uW
z#;Nkk&1Hy%=Er#9mpbr*UV!XO{2=ZbpjEIW7nY_jTJE^+2NiJ)YS&4kRk!mpo4Jv`
z$5(mT%mUp?c*fDXUDVg{N(W?Coz7YG`RcA^E9>zabc}uv$Of01H5gGYZF=IM@HK6l
z&Rq{bK?6MMPt5v)xL&us;iz;^fj$Kllj2`k9Lr58p0KFD63nZnXL@pd=r22t$4(?)qFZq>Y8Hb0|kHTAJ;8HbqpTK#=BZ)L1aqZyy(8+wG3
z)AmW03wq?X6#?HhE)9!OsVp*Q#W0Td!}>m1q^w+{
zGd}ZX@4qG{IJ0-d*U6*M_n>_sYER7R$`k9x-IM*t>OjFK}-_d*$+&^E<$<#AIDLAWi
z_Val~1fMdagM2iPg0_I0^~HwmG*9Kc&M>PMF@1i(;qJ*Cv?2PA)H&9ZR(slxw4v#1
z()EvDdv<2_@$7Nas-_JA-JN!rd}f9oOe)YHN#EacY~IngtZ!zJ-m=p9nU}DXGTOfd
z3;ssf1`zqEz|89>&0$4~TpzGb6A6MIz|VPz;OE@O0)BuTjS}$NFsG}pI?@@Uqm#Tq
z>Y3z}bIcUp3r-aL_f8Y!BR0)Kc_~)>*IClzs&@SI%p
z=})RTSiJ|(D|gy3@?~(ax`<)eg_Jm``DN+By)+t<8{lL{l>+bwhLufI?c^6mp3mg>
z?6lda-Bm5eT0SQ@$n|Tjzl6gycqNB0=YKWs%_IfbD;>R!I+M3qD`D)U&sN5Nm^{8G
ztvv{CsI?Cu5cKt?9gB2+)O*g3zDKO|&maHRgn`SGk!!8z7-$4wCf2;7$uSdkE`4Gvk>q0H~rkJj_eA^srM=GthpRct^&K+q(Ff)%f
zI8iNKo>*jUDh_XD8}BnD=qM95qB2%qF)YgU@O&+;I@R|e1)88SU*OBf=B-L9YSM8(
zsQiaG{7#<%k3J240&VM6d-vQI<%1_+P31>(vg|8*a7?}F5yNQDjUW4r^lKi|q+7sA
zu!(+Vj}~``iPy)o;msm*te1MvzQnDbXLFpB3p47RT8e~gpaQ12u_|i
z5*c?hRiYzE(G}$TdLuE_5qlC+%0$Lp4{0!!?wNC!F`8R!#Y9f?nDEIJojLah|MAq7eBJv&pelD3HM9c;s`|T4_
z{l_{^Y;reW6W$5e-{<>Q^c40@gfBWQ=8H>S_IaKuW}5QDnmvDfglQ@^U5FGNf6US-
zea_{zM!#q2!CUfYhS3VQ?-E}!9co)2E}H(YX|!YQ<=&pc7Z`$T=-XSd9`{-W%@mCg
zH5;t}vJn><@WY}C1yO-y&zYXTZJ;%9Z%@%ty
z*Ps=2CT6ersyGJqTK|j{TFgJ=6k`6tcuvajmBbMkN4O?1m(k~h(N9UYM}4dkApybOw
znqW2>qbQn267Msv^{;{t&tycsAZF+?Yq<}6b}RD9O?wX!FOfG5{~r|M+#u+BtQ$;q
zvo;jVB$GInzQlcp6{O{$sppD7`G%uPBy4*8e_3mOy!AqCrlv=r;3Z949A1hCE$j
zsvo++oZA8KWw~)^Ji(RVyH0fKoJ$46Is?I%VE5&A+IO0k=+?LF9^_Age;1-=r$;>j
z%LhrpF`e4~335|mt0emR#F`t{>lw1W$SNJ!sOjEwZqyr|faf3Oczwxx=4W2t$uC_`4}UJG~_
zU{e`c4%Z%n1~fI4t3b^pg-R=mEpfLIw!{abUN9-P#2IH>c7IciNH0BIPXHYswkv2i
zoC!;!VpH^gm;Hqo{g?c%A;d|zb0|ZWVoQYHTY$xocnj8V)e86O^q$T@4Q34UPMME|
zK{`F_f1QCgS`)?#{VwRSTQXt%o5$G3T2uz1^9xL0{BIs@4($zDnQ1^TiWXe}5mD`uI^ut^YBl4d%A-wfLw>G#Z*
z&5SP$RxADK5|1-1igZOgp;eo#1s#og%IUErqS}YTHADasuvmCt*D$-1q5uWxsV~K`
zjf4%~M|ld1%!=&>k=7npSn#(MzmwG8sQlq^r7OQ-ML?ftX>WqbC__)ki(gq?)V`}o
zu~bO7&tfh}HU|gu4fU8{sO;NfR-wmLskDXI?3;Ke#*C^c^nFiJB`hRUu}U8_dKDg1
zzX-cSJu0I>r|)2!8BjDx<7R!pEW;{;EEmXVq|*$1tc?G%#H@$*NV)nTt`63me^b2*
z{gHBYGOi;38pr3V*P&0sbq`+wD+|8O=LC-~
^?_nS?bbSF_66)YIRV~#pXNE2p5
zVy>AJbE{oBS~D+36E|jFBQmO&xavRZmZ}35HAW?CN1Q1`A8*Ro94FyzdP{ku(87eC
zRWz}9K1#1b_0BgS)$^pihjxanCuF|^{_MK^eg^8{=-=A^PDZ{sfBc)ZocO>O^S{7&
zwFI?%k>n^k1E(0-+>3>5=Ajy4;Cz0&pXAL@3>=4i6~M!DZ?}`rgp_I3%+HV@w?x`B
zV#|E(tB5zc82*B;Jg1ymDRp{C;Ff
zqcx~qY11J8F|CyiHh5|>+icVy=y(`TGC{dN!kYqbtYO~8eHWC()KHBwGY`E4T1$Sz
zhYT?!bDQd$^HARf8P}VblWhyc`-0jn@-_+C$-F+2@p7h;1S&@4UvG1!*BuK
zA@LtN>naPB`1k31UnlBI8Dif4oUB>UU@5*LYAzY#vH}K*7VViMG;{AWyI)HRRx#a4
zH1EJuq)XhE#_c9L)awMYUsB{h@E)0GTF74S$TMp5(_V`RQ!1HJ?f{~R+Q%n3)p$^P
z&nb6(BZ;$&=f5#M4z1(vdEdTeB~8bh8SawBv82M`oq
zP&JQ%GMbie|F@$lY51Q;GcNl-jppqy{{N2VUqLIWMVS-#Lo}M<>6$Mj%V0xt%2rr>
zcPV^Kn_=x0P5NsqjJM~aDvjpiDW~eek6ah$<{^vNVB@84*z`6-Q~$6V>ik@4r1`mu
ztWwJS?EjS!y?%Rsp7{BQG@<#adD8c5^P_5MhwfEYF|4f2EvE
zHONAu)7b8ea2;-|yS;WoR6t!h{vjq*3yP^@t($ZM&mp^6be#?vQgktPGv|cI;awm8
z+^=f5^=5FDycY71Qr2K%Jgvc9@Q@OX!s>uQSmigE`R{HC9-l!dZB(RO&hB^-*sI96
z!wMb$y2v~X3D=LkCdJ6v7g-cZ`1TW{@I*5`QR+9e{%)_6@;dg}h78Z=zIg{D>`^Ol
zxb5(N8lQ!FwE=XYLU+%(@@0N4TQ3^JMZp=+(aww9IZeXqMxAW;l_4&yOjzdAIu23cF>ixVweOYtc
z>a5HV&r{19+uD6>gNr8{GR1R~y?|!&HL6~Y=U_kAnd}wT_`PP*jR)iANEdE?X9!b0
zax3#L7qV@>{9ba4$#8C{M6I8?bp7N_|t#-N{sTAHMhUA@aJE-
z8T!f-*L!|Nor#L;G|B_FZR#YC!E?l-SZkNo_cizK%WN2L%D4#MksOP9bOnzU!J}U}
z!Ulk2dtA~x`JzeuDbMs+M_vM-oRhpm}KRlk92-C)at)
zRNtQ0Wl4b7i79KyZ)xvu@-!mjdp8vRbsKN|swco5y~SQ@Ms7D-`+Cw~N)>!7SxlCA
zdyZ8DjK6bs6OmUiIJ?d)qdL2HKEVfqPx!wRZ~TrTf=F`vIUaQPjaRCmx&6XgpT6Z>
z$(f$t|FyC3=S}DVw@=DSG*FB<>HOMDM(L+57yA43LZlyfasSz#tw3T5Q~XH#{>+b5
zq3g!4y6X_S{Zrv33cT72f6~4`^C#U7tmTHBhCgXu@9RN-Qsvsk#+$z2`fQ}J?>b8M
z9`dvx4%0cu!@FSR>FYHca-zwvLKZnimW1Z=I>iBT$Z0K_WqaNFQnGu-!S>weEVM^;
z%9CAhcnUlE5YN(H;+}(?;jQ4#aYpZXytA2A+~E>4_)AZq5gt_+VgFbA;yOZoao(PD
z>WfF86HU*`q8jr|Jy6?fh;xcP->x`FZ+H8Q#1;{T!%HOEc!WbQ{b(n!#*~H8z(y)h
zX~1_)8T3E6KI-Xxx4&ElU0&uV?+ulH*D2SJlBWhI8xN5O26|Lu5`AUDdjb8Dyw~my
z`mm_a@1^I5+mK-sZy4opXs!Ibu;L=~*C+bzbvF}*Hh{t)OP*d>(ZST!Aj%&cUW;nx(e4V36
zryG#U`h8liWvLi`zGpPfia2N>1`J4*{C+LzTBy27%L566kPGDjZ7+h5u%7?)mvXMt
zI<t#$CUaMsHX(LzE689tdA&0eV-8It|%sg>ttm!kSo;x|`_zTBgIb!)6w4?X_v(jPe
zrIoE8S=ZJ25X}wPM5y}lqSKzDdtWrWC%kBuC%oj5UwZLoEL*n`(It=ml{J^AH@jB_Xb8Zc!R+IjiY)_
zLa!UTmb_u_(lw08&JLlg}?S7Y59S75gM2%#T
z7s|j-c9*0g!r&;qR1wD9%w)3$vyOKgVad_4SEJXKnEL;yt>MFP?LwLY={xff`blk&3(BM?+El*iCCxx_B`T(d{~ldaOAt4GxFaKsr#X
zReYt9ET4R(R~a2{ekjol4{yws;oD0&g&ZaPVENEw+s{^i+^THJ|7VV1jf_C3kRH$u
zm9LK{DRpt*qyo7ytZ2dVjx2*8JA4(8a|p3uZCdtptIB^NEi88|{D$ycEejtO98a)_4A)AHhgi1pGAj(T
zYSxyJb{g6=+%4dsQG+(E92pn!4m9s=OkOQ~VE;t>sF^%Z{g)I^QW{S?^tsTV06(|;
zWq+1!*S?vPuVoycJZ@^$)P!d!_r$n~RTJkFe(O9wVdjKP=c;Goq4E6v?v|~8`3ky%
ztxsHB+|~1qRmwYRz6$d1oY(rn8swmIzKDE9&ox}yB`nqHHr4#k9-*2@s(nfldis8M
z+9w5$KBHL2xdYJR=posY^_c2-AYQ4xtrPMCyl<%>+Zms>=pUYr_C6+SqjkZFmaTohlCb`0^(DC-@1|(F-=wz&Ax}S1
zh;cKsL$OSJS85l$gLJH(cYGIs1sHKc^FP0$WczYLYiVmgSh@CyVgn9YfR%`kp@Ugu
z-PK{&HBkkaJHC@KZV;_ox>l8TP#Ggtu2ya3-+btR7vR7Jg-6Q12zkt~>6|e{v-YLq{f7^Pc>xz{h2SHJ3905oI@`hc*QS0K2ihC(bhf{Np9~J^5&Qu
z1={>KslvzhbWf%Uj&G4T1r`TyhW
z-Q%LF^Z)U4=A1JFjF-Uy0rN6&xa6b;YT0cSYA!-$>Z(|4B@V<|ZpyCa$K5pZ5g%XRL?WWIXk^fgr7{e?Rk%NqZ73*#{AM;N-6z4?ezE5;P2^rbAL~-&6SrmU!tCh3pEzq<#HN*oTD?IM=ntmu*H0pX}YW(Z*?|vvXrei(Mk>v(i
zXyIb;v>GyC>)YoX8Q;
z_{0eu5$!q@#!j43bC-dAC#dF+qwx+mjNb7CwGY#ujfgHhn;l(vd?l_C>GerLw7#VT
z?_{#v!3M4(Xc$-X%^#VV2WtLkWVr`+^6+fMbMO44MyBv#@x_Xuns5He7S5k=S9`?M*Ib7{Rk?)Wo}VL`!cVeI
zo}dC_;m0)cf^dBceO4-;u0s~KLco*5=t;_Hzm(
zkY?RD8FyoE+^zKAorAlU8+U!`UF&qt6O=v7=z+d9tA+`7)O2JqN-Oi%X*_}s@P_|<
z+&WFh|9FBrjWv|fhIBmyWxgadown_FBy;_xW1Zda>3qSO`(0
zGw8&Ie)MJ54!?TXp~+*Dvt3khmGr%nw3jsAU}Ry*f66!n8JY_1ryv9B?)wtfp~Cc2
zCY7ROW3Mbo3B)}3qapm6swf`9Wxoh|Nc>$mM{>y2mIbLd;vy*5m9jH+Bl>e)$uleN
zW1$uLGb(_QOcRKSP(49se?U5{DX{93j)AK2J%K!GF(;tQ0yhC0V^L9>^x%|RNRNez
zjNz2kQQuHvnRU*weYrqa&{8owE~x%nl+9|PNj7X*rv7pox+_89-DJbWzi@HEjBNPv
zNrks5*R8u*?!W)ReGiiCFIjT-w{KZ_#g(AHNf&h`*Jba)IYK)hw%*U}(XbFxn~CI9Rxk^+t#I(6WQGf#iQHJpNXL^v
zA$c~$KI3s)o+)_)d|1)=zk8nR8G2^}WP9k>K(q1-xPQHHXPqa%lS32+zTflGod+fj
zf*++7nx3*X1!FrZ?8dEjhV}+wyP~s#PgLkp`ZgdIIK9U-kaPb}A7zzR>MFQHK7VWW
zC7xU6Ba8Z#GS|HS1r$x$N?tZ-0OYcdF1@#3?|Zqt@E+LDSDx0a?&a*`xKf*-6N8a4
z#&>VIad|J}IG2yO#2TTLxiv^$_=F58F!Y3Gtu@L<*Q3ve9$ua9<-g-u3;QrmQ?6@h
z>gz^rGOEqYmbiyEfcG0x5CQJPsBOAaZ_CdW`49L|n`2mmCKcW&-!qGmf%-f6f!$jk
zh4=MS3hrARfqsXMeOBHbfWGH{wtf8AH<8?
zAYOm)-g0r=7l_6M->7kUJ!+0qKmD4uxqYfA^*%
z$QPO&U%71m=DUx(Z1?d-Ei(wwii6qJL$)J6-rr<{Y=$*edC2P*RBs)#RBt!Wb^9&m-hyL
zfu52z$0cZ=7G66kZd%WT*F`{22<^jK&aSS%xY^8!&MI!W4qpFDNdLwq=$UyE>QXRX
z_qW)Uv+s5RHsnFw{^HkXqH9y?U3P(cLnb*;tzeLLhy%@m5*bu3`ytS;hE9uIw(0B?
z_}>0|{_2P-H}bHNba*;X2idR_JP*m}3!ncjHmbAHHRfGMX-K4NcQE74=QXuBbMy_V)~h49
zRBH93qnY!$$9C$>g*E)P+^gj^h4Uyvz0>&jImJ&o
z&YfmF1(&Y3Jr}SNoj3XM4BFZArcj)|37w!=;cDD@DjQrl>LbpF`mjys{juhV3Wf(3
z=ZivC&tO)KQ?K;jyBqh$vatUQqxAap{Ah+I$0)2;wk6r-{%)@EzuC{Y6>z_GC#4@)%2#b
z?a%f8Qp3Njz_hJ}ph^%GV=~!?_d{L{I{Z_S9aUh1-aySX$Iwd}$9W$k*&Tg8hOB^>
zAkm}ZW7MS~q{V_(?X-&Zx>0=}(H+TM=&QAyKMFn74*!0*rTZXzlb?&RmvFPwa_j^B
zo8i1%HuMd`(0I2#s)w+1J?g3gJA*ZjTY8y+SVS1KKVPB>OUa8S{(C;HJ62qG`KF!a
zO5Kf}b>=-kAO70k%u=S}Nh`Os&b+oGkaVctD;3t}rthR=kfKf4agrKEJ}K{6Ng;7)gwQrZ{oSLdPp}Sl0UA
zxQ;*7j>-kwUeF+|hZO-<04NJ^}18
zzYHn#Z&$cU&s>2N`ZOf?olKEU+9{%{8G
z#?Q3ki{EOfni^%(fm{u**91n)??Emdc=Su>Q2$`Yckpb2JWG;jCgUxn&&jMeKace)
z_aIl|9-=?ltLag`;ksJ1Jfq|)BB?wtJjiTs@Dym_e>kimL4(c3yj7g
z&uctfLAXa>8EzZ|8ER0$Fk{h#&cZ{GJGTUlaBRCA<0$O66Ja#t_7WT-J&k%{p(vdQN;X1Ui}qW_1+RFs6*@*d`V{@Cf@sbb22VL;PtiWSQGcog*OPIL+%CBG2slSi)tWfl9Na^0
z7v&zZZs1eJ@)v4_^eWHU*KFk;%&!lb?vQjYu$nYl*X^mRQ^JtaZbx7+GI*pFZQ^-+s?Rv%v
zJfn=f)?|ct2(5%s3vXrRGXc^)U6Zs=pCs+mXQ%%;lKOq7x$n$#kAL@9zB&pw33pzr
z(+A5)iRwugI58-jn|jimdyO>dMMnjzDrHyhT3Z5gbF28eZUa}T%k74T&x%cAS!XWJ
z9_IKe{~1#eXlZPJc4Xv4Ms1RXLyjnxqb!~*M+yIrIx&d{{=POh`a{ZouSEq0$~@f}
zL2^1OQjK6K_jIbJh4M)UBymN4hcw=wp+F2{l`IC(Ej$1@95%**a(K)M$_S9wLOB6w
z#$0T}3l4@i_@glsk0&9Ll&Uz4LLRx`6s822gDeicagwW2ZEec+DSZ|>ttmF
z$tV%vmW{!sTU_>FX75q2u$L)!il|ZVw8W+98%uK~US8-mw!dt-&f#rvKf@u3&dr03
zsN#31t^N(Y_m(`c20#R$WfWdpV9i*%&>OB^Nsq}3+rw7xC%Wt@NHB1Rr*Q8aQnL6h
zY_1vXK7vf0&{_@+#HEt#LNUJb!XNh13LGf`w~fq;@Yjd+mgt)1DR>3wc+J3bn)Cu(
zV*>YSEnqPC665IfF|0N8fMA7v^gBcn4!Q)NHd=L8WrC~p!rENK<+;I6ZXUB`b)Q-h
zgfQ=F?f4w=*62`iLa0F;=QN1sVuKi;6e`B1ghsdtUa4zHTYwC7kZ_1`J#Aw~=?6i98XJ>2O5vFjsnZ*njh0
z6OFxSDU)&A*iMc(C7UNAn^~_NraOr^DLNgfRdIChFv5Ishi({aRk5HTb8Shn|MV{z
zCPwrQ+mTJaC#Z=rjQr=)=ZaC(x83L;C8}ej3(9x^^&~qo=)-=$OoPZ>ns@woyCbVN
zUXA3UKItuSWbZIBR5whF(uIj5@OKOTBJdZ9KLfJCVm+|0LVIIfb_)Y;33GPZfA_xx
zp8#y=^Fu_U-+YJQg;g0gzE+?dct3)7qH_={KN*rFWXI%v&pY(OFmdZnjY0=U?0)XQ
ztvKpYpcci7P0-%uPI}tTim%%-PptSY_!}8KoZ3W$GGr~s)9_1sMHfW82($<5CO^39
zIjL~<@a~Oo1K#%?z3;)RptBb@Nl(!ghxc5zSnzRkREcnSffDH-jT~ApkOcrUQ&uOc
z_c{35ASNX0AYl(>0#q=3Oy6^;0=Y6884T&!KGZA09X$D-tgPlXU6{4ZlkdAuHih=Z
zr+>a05s?iFgxuqVJ%!fZTn_z*z)#@$HbiqkyA!KuyQXeik9$)ak!nFd7wZglVc&CO*-+QmdIM*68p1(mXpHqAQ_M-{3*zv;u$wVl`hz_4
z6=)o>^TP3)04=?)RYy37{q;Ks(*fSQOXnEWq1pb3+n;+*#m&lLcb9SS=u@vc6^um%
zno;7G&afQV!8(UI-{p|ctFg8(V)45k-9k+U{?F8;z8j4ihJ-&f>-B)10BWf~)(HF?
zrNjQk-x&N=OlJS$_k#y*N?a5QN?O2c$jgqy@vJ4
zrFa#U`u~XPYH5<@QKJ79l6vA~{Up!)czoM_!ctd)E*BJy2PHwpDd>YiCEaR9ScanI
z$u>{@ihFdXwYf{XhF(btHRlUiF%6P!0-{X>gVTx{qVSFt8Hw@N7Beim`{t*@{ZCEg
z20o>kqUM26^UaX|XO$cEuyJ~O@^;Q(amp5_xqSQ}N1mM%c;puz>dE8z_J}#xe?%oU
z3#5LvmS-SJ(IfF8fNR&R^u?dTJ{MAB?}KF6_tWA1Dt2Y3!do72O&=i?M)|-QjNSK^ng>r(?8GU8g-rn``D63y|llYaJ5+i
zc6J?`zWCEV|J*9?bv0#UXLk){t&SaEGqeu`t0VF>WIekOY;|}#nZec-;c5jsvbV&4
zM&5n%j;p?XF<;C+A#eWZ1=LfW`RYY8d<;sUx9~_S9=R0}i;SV@nUp2+%+YzUYA9UM
z?#Wk2cnYtKF%BA3W;`)DIc+Owb(Hb)at68iQ-nfR2E~dZpIJNd{q$b%+XQc!$WdkT
z%(K^pdcFN+i%0ih@T7wC$dR3noG%xK=zS&3)%132?=KQhyS9B>&t=k`7==6R;Q3Zz
zFSJ+kEb?W-mZNd
z{!*kv`xYZu1zmf1#MQvePNtx$;LJVURqm)pwV$_=<;`bH{rDFTO?m2TX~qyHS;4_q
z(pi^pc}VdEA=R-im^|XLET}&%GZhP<$1%{(Rj_k}<*I`T=7pz_ui$c#71^km<4P8-
zfR|dp=Zvyy!5Yf6ulla5A6B1kYI~2cRdnj^f_?0UMhsk=nxmP$NK|3;#o+;+R|$AZ
zj}-T>!Bo+fsd$>WUn9SBggTE{GZ$wGQoLuFuYQk_^6f9?U4xC-{&6WbyuHM-+#_bZ;*VxwuB@DYQw1QX6Wu*v?JNs4wtg;6Qbk=ftG;WSNKZYAr=sdbHug4d-cA!T{c=5w7oIv8GjK6?Dp?+jtWj7?
z&60r5kM?2&Rto<4oMfN;g5
z>;XnTj;V5MmFhPtH1e(^U(%Hkys>mK6JJVxo2b{!1P_uE@4w4sT^xe7)5LEDf8Vv{
zt#D)ysbt353&T20M4Q~mzQfrThg3*%?zFA|W~ecWOAU)gs?d9D*xFoU`W=i)4GVt$
zSBcB#(~WW?S6H&(rihkko4Ur0Td5`}q`a9wG|*?o0*jVHRG~q2kkfq
zJ}JbU2W<-EuSpUz&ClHPiObG2j=%IVJ5WC-#-gD-IZBVv@4$;KYrhKj?C)4Bd`vDE
z+gx_tpqlhc$;d*~3A(P+;gmRe%@}8;(+gwwuGeX(>Sju4@KZuo{DDT>p1jAkB%KHb
z8mY{zjWXwXq%bDMCJ6G(jc>(BA_ED7IsOohU<=}`XvTyKgg4wgn?N{$Dr43n<@{Tl
zCg(oc5~vGCk`m70-GOTrKG|)Mxa_Vb-5}?;>gfZH2WLsgHRBytC8J?rgfR`sfS3x>~JIyl)-#4|9%9-y(QBcn=Q+EZAut~Gt(@IWLkZR8gtc=>MT
zR&XLB&m!|5d0WX|;ts69;3Vsp`}^PBe{pQ1%Z44NzI)-ch6CRWP5#%N$Pjo8+-jK8
z4t&JW&aHS3c0=J9d}7)d?+|MFkymbRnPl>kxyl}Xt}1V$J46~~Bi>1#IpbCMdjF7Q
zNvd}>`FpfDzC(|`FeVuEruRB=YYxXH#Q4P$AN7L|J<=R#B%&5QYT>5_od@!o4-SUk
zq7#z&s8qeRm?ZO=+=%vofPptih{beUhjC
zg7rDN*YfzldAI5GoK;z$?{)`~L{-#}JMA=Y3qfEbW^Qv_xTMV3J>Bv3KeaShBR62K
zOFrful8(VlJHO$TnYK6al1=pEy;mrQhwHEAd}Ec>dCSSyx@q-+3$z?f4rJ^1uepErPke{{^6p+s&cNBX>IVB~e_?mXuV(+%r4aw@
zi%th&_TK^;SZ}w@(eXAaR{d(FFMOhP1;xS-DlyoT|Fe!HM#pm>GahY=&hh1Nfv~_$
zSkU?P|8Lk#Z3R9G0od&S{I_A_dE&QVLm5Dgkf35tl-vQFmtOn##Jn^q4zz^wfXd0w
ze^#;*biSxy9%#_6s=Uw-9fLtHv1Y7g2XIc2kdi;1-+s&F8+E4xSeFvY+K^M4=y=!u
zKB`Std~{#(`%(nx7IH|BMIY!Xq4QBJHe$c
z^WxBQSmjvTACX&eO;wc?dYH6}>Nu?l){LdezxQ8t+)BUDok@?VzYFH8wNW`0U*w$a;S7a8brS$NWSO*=+2cxuii|CqC)gK4}L|9D0Eh3*(1Q15h%x(dmg&N+1k
zy1V~#21CzHv_Wo-y2J-Y{p_iMquzLuM(u}TOUAu7!%!Ga5HsGV_V?PD01SV+N4?V+
ze)9-A6aRAr^5+w6+h|RZ!P04kXHW9`M+0No^PxDXe|4KbppgYu_lKi2vH%2!93^;q
zbS=|pthXYMFz87Od)Lk5ZH!RHo1~5|E9%C0Z}*QkgrfW7kHj*gY$eJmoD~%>sj(`c
zro~Ji$yd
zx06p9+)%SJmMuLfR>h`xR`MpdPpq<}$So<48<+FRtG*DcCgaMv;Mo2EA5M08g%^jG
z0^TSqT=sOX*yrf2WNKDk)ReY+Ln<}k+*S%o1a68Iby@Fo*mX=kvf`4~EUQoP2Fi_)
zz}HzDm;3b{&Pse!@4dE+`1bfC@8@kpoD$CWbO})t^eMnA9-pW4aMsf&&l>;u&2=w}
z(~+xZGMxH5^Y8O2zvQth)Peo1$nFKVg3|>2f)}TYNZgZ9jMD{cT(US%92LG
z181&9(Z~JHwqBaLO->%Y;XS+Y1@M26PbAwBDMpf$L+4cGjm38wD}3j(fp2cPtUJox
zKyS-s_umnK6hVo!5fRW+L7H&jbl?M?NfdwkSl!iBr+jDOzV#E{0cmy_kP)bnz3;^-=OYMb1Z
zd%N*b)QHsu5AAz-BqEqHxp|TplF5Oy*F!7Yb+(7BeT-2#tpHzT=N
z`|~`slRuu%?)n8Ynj~D9V*!cD`laT%Tj*l)$HUI
z{gp>I|Bn5T9QpQJF8=7)hBG9X;m6l1Z(FExJuGDkT=HhosI*NEPbCjsD({x%eM}rWNe(0v
zncbu}E4598-Ym{A))s$2+q5T78Qn(R47n?1mWT?bVkjz@YE)g?7RWw0PnbnK<_haRkk5bSv%IIFwCDLfs=Z;7k=o#s`>#cX>q}WQZFFjI6
z(z+nE&M4O7qrhEh;ySF~p5}#-*vYM3&ws(N_V@FmY=yRSxq?p8c{iQD=3RT5X^-?>
z+Yppu3&PXQM|Vj{Hd^5cM>iN!Y_!4~k8F($$sZJi-^&(dZHQFwPB?5}sdrbSFdk2p
zef4w@GD0TZ1^S#k>khSY-(aE%)}_g_CZ~i#21h10b?$M|p!vx|T4{d38B?$wdHgk2
zyI9=GOzG7?y41D4i0T|n&?iTyBy3?`{75}t;@-tQQ?OMm&@tjG;BmT~DNevm?qVU!
z6I7n;ySXQ61oianr)p1?QUC9rg00ktb3h*{IDO8dDt9!&J^3Tw4fu{&n%w-)z}0KG
z`k^*()rhMhwKQAKD%`R*cY@@!N2HV7T=|bA8*C%H950?kZtY&}7Y`Ks-j>!DNV@iI
zzH6!;LEGdX?~nr^Gno$|4+lLahtZsoSk3&{QCfmwxJKOtYjUNs8g2C8*TCjp`Y
zyHbX6pDt$1>pd%@7)eH6X^o>Vf#XiNk%29Y8P)Fiu|VTGu^X8c!x*Ow>T|gSlrv1R
z3Oag97)Op+FB0(#j>wH*bsu*?Dc23-$z=}Hx
zutp`!VbnN_X)x!}IE$5Wl2!!cL%jo@am|hOztwp?)i$Z~ZAK^@)xO&9$T_WXtf@t8
zyJtlNQ+yuP8<`VFUxZaFk6~?MK_~OYgCc_%LDE%p&AO{!S0QAfic0?80X>zo>bQJ;
zpFAjrb}%nKIKSTI>r{N-DgF@ePY%Eo90#cA4zfOIP2f?9mSVK6IjbuqL{%p@mtx1`
zgzR7W7euvUqB|?MC?!M$tc~1UW%XnzxHCF
zUZBTBtR?wFt36Fv7cUw4ur9!3jH0g|ge=O1w;5J1aGc)&ng6$D6Z*#rJI#e=;hzu9
z1>^V6$3#6<<#BW2!HOBNMGp({+s4=Sj~CTXTlYGCvz16eX$7qz0+U)$$Evm=Cr-V3
zW4vKB-rf6!tYgT)sz5=3bu-B6c5e@Z%0!isGyMi$FB9KMjLl1I238Bs>VE;<$%-ouEwJku9Nc@{utC2Lp^hwZ_LFsb-JrBvm9
zNKtli$}N7pq2J%M!VP%cSLlm+QGg#ivW5?FJ+z#OvZq=-1;40z#q8b?Zb2U7;0A@b
z9XyglKeY_fL=!?p_TJmo(oyp!qfqpqtQrw;mg7&Wl#L
zw@tb-Iq~eryU-7CHF0z!*(IS1hrEFkd;wu@Ko|aaPQ|azj9mwg)a5tLID`EGe~mCk
z^#^iq7emzuCelw5jts=zy%mJfg59yOSBrImuL>~q+fMM6(9ZQnFwvb3mkw8X%GF@m
zu|bE()t$;!cqjCA8V*v9x?1Pe)v`mMsjOCUXAyaNc2O8I}}#8>lH@0VvrE2p@)QMXpkO_>yJl@p(Qi+25a
zoc{3#s+80J2K7;>+^is11CLz;%Sb_wx@(s8DjWx_W6V~Cn$_Pk5GPcJ7b{6LGwO9}t!;jI
zz0#Jm4P9=Glq)V6W9LEiBP-I_^&dLTYaJ%lSlUrZ?`G#!UniT7t&Q5pQS-aCFfRZqp
z=q!0z=yP&n3;3fLivo)x-5>jV*EUgpRpedJOvu{{?;)P~va@6b$plh%g|HXWou>nJ
zCIwT5+?uj@q@@bd2hRBj(0U<^i4w#y7q7{QujB#RtdCGu2X@X&VDhT%2hD?Nnm
z$Q(eQJn&gLKf+16b_eDJ&&qT;abr(X
z<5(MfU6ec0JUMaC&qT{|o>a%~`~5bbkhL3p#LOF`E`PKt56>irK020^XxmW`nI*Glz`Kz(0E=Ez~Owm)wlwSAvCVc|D+`>C>
zk7vy8D(T{;i;AZ$yt|->qLY-vFU6=*dbjK1rhDL#36Z3-tR
z&bl}FLvF4c{Zz#L$LV@w##wg2;Jm!KepUB=l2u$j_?JLtCaziW+0l0K{aiDfrobF_
zMY%Qf`F_k*r5xx)6zsJmtJwR_N01#iwE9Glz
z@=qssZ^Ts)Y6q=2r3v75&;muf158(O`|Oc^+|GEezjxX<+NKG4^0Ha1@V(2*Gv!z>
zWZoD2*y@m5Gp5qWBZ!h{d+)&+j10>O!6WO-vlrCkSLhr2ci}{dxVDTecu@phM1(Iv
zS2qb%N)S3ZUpDjug1yvM7;)MJs>Gwd>?V2!x~Dq>QU_~q1eb<(6xj_`Q(B!1$&>b?
zMukx91dK-5XGMN`=o^X-N@y>pKwom&1m05D%exw2`v#^XfA%%+;H|v6eky0=1eKJ#
zJ}OZ9bn7OZRCLaDucEwz8ift=w8ZL$X)c_E{ZK
z7qxzPkBq{Yr{?Ql_}awTwZbSL2h4Px(s82hYo5d2x;k7Oj&GE+=Ec(*FYXEv6ay{>
z;qFNtH>!E87bGC`7v3ADyU-+*Hj|l-l2=N&_o4M
zR$1~&&^Cc0!WTiZq{5!ngZxQyVp%o^&V+4Df}OJ@u>TC+4V}DT7mGR(lZ*L-Zb-nx
zWzcAlEDwq}oc!6qYo@7mB0#6e{!cxn)fwkV{?_2zf4IOxUTg}jF%&<*+1}w|q&IL9
z=l+RwN2;HLM_8tX7NeC-QsL%Pa?y&;+Hqc|Z=AUH^f=Nc4)nqEd)Kw53?ATJ*P4{#
ze}6D#cH}B`6N#5uy~#187k&#d4MtuF60#~J+F7|mKo(+y!S@&-3qfip2~RX$Wc(V>
z)=*?_Bp(szh!oly7ld7v*!-T~r}1sjhSu^JwbxFqn5$#F_)~Y#(z^QbtWx!fwEvK6
z6uQFmPD{xu>_+!_PDrI#IPNujEb{xb?9CaO%)M5ieD7X{n1q(%WvCm#=vyYUp}gbe
z*n#=3$n&YLK0&gqMjpGgPiCJ8)JQiz8i0QG)d@|7hZ8`($`kfk&FepH7_9M2bQ@muv_J2m>rVM_#l)r%DpPAgOQErZXGrF=b-J4Q|%vf0(Nm=i#&
z@mpfuT+oKxzF78kI>FQ@_NsOZY)~?nJ_P*;G6OQ8<5`v_jGlrm7n0{wE7As88DQWcP!=e)91g
z;_PRfnf=AQ&nRc*q7!P?O3G%b_EgYGIRTBjHk@(biYM;bu&)p`j=LzLjjS4=ITQEf
zIUf$(^Wq+BMU;Cg`;aFjbNoGp0?wf}_$_nRu!-{K6r*_q{tv5ir%Bx7vEyA2Po4;i
z=Z}vSObXh;ObU8E+40rO$YA(7SJPC>c|M6xE}TBnnXfHfUvuh{WQWHFKOs9J0ooWR
z=vp^(xV^pm<;(q?@uJ6$Kc?o%q%4_FNm~{Wr%X>a{zPM)Wlxi83OY61?pdbC0{!
zwgR|9dsA-7c|>HOd4Zln$x?&830;%M>*md>zt_H0icXbiFSN}16KNFGoT{oOp?@d%
zko7VFJ7CXxZZ5AG^`YF7d<%FjuFCCLTdDEz!RWcz_9xpef4|*`Y1oFWVW^7P+V(dW
z-th)c<_IU9_Xa%8_NAUe4T3FcWQjve?~gP`)wgW`{cEHdN>#1*19hTsN*{`mrZ$N}G~!Ro45Bmk2Ir$%v*M3<06RLBsg_CF
zA&;96QlV;pU&zuQF0o8lzZa7EU`5*_w}jp+L7ovA=;V;Y%p;7|McG0H+4TG=F?2F8
z=22+ky#k%n(SM@ZQSQE&G?_sP4h$PET)F1&^P&}Gf!24V!potQhR
zpI;1E0R!0Q`#nkBJ>#Ouf~o?td$*1824>!vv_BuZ&ilqLU6+g6V9I#LY!o%wHA)s_^SooVJWqqdB@`CiLk
z%W8Qmnb!kFFrvNhbj~O3ouRXpP!f
zoiR9XlqWcED*2U8Cgc*~{1G&w#B0Svab<
zJbzpY#X9DVkxgf|qoyyuH{ko|?dySCyeZlyo1S=?JPpaSk769uthdIHdM1|nlOi8N
zr{x5HVkj5c^D(FmvM;$!S>57W0w*9*DY&9S7AW`|!H4z%(I|ou%{yli@~N^8SEUBk
z=bMx}4x&~2tnLc|tYxVxq$zQYy1xQ@3lRi)YRjD~qMgdw>hpoy0G?=ANXKok)aFEU
zbMaX>YX
=fA5D-=!IAn}p0^70Qk<3Nsg??UwFX*cb%q-IMTrp=cAtNUR6XF$sRe
z@DQYYL*xTBvEk09dkWuQfBylSJ0g=b4wh%(HSvgk?qsWDs9-Q^=?&R*twN7nO&1Z-
zlwU87Il&-ndVc=9VrVQVusHmLMjQhA&c+Jf;8;!^gTFB3{t}oFx$f8l;0z;nqIOcx
zL@}mkB348zx0FpHjV7WPguEE6&kmO@O!RDZBW@iYWIAuqiI{QVkYaV7b72gA&vgtj
z3xET2Im9s{M2ko{pRR@S_QA7O$yNv5fF3%5F`387+--~?`d
zGcbaIBcsfEVo>aDa!dIF_4n3{H=v!)Z&uemd!Cx{6xwRH2j>H9w~_jWDOiDK8CKfO
zF@p!eb_*-6srd&FpBJ@DQf#)SAHFvj)>DSY%`qX6ytqLIjMlXIcl2}!zWs24o}~9?
zTre001>xT2wYtEsL%v-yCvkq50e5pXD+j4|VAGy&0`Cm@#t^B#b3Y&WwHf(;EjriS
zSRMQsbO&@{kzW=m@Bbz6#GZ43u?{&G4=XeEc|VgTfg?MXCSA1x`cL)ipyL2PmB*ny
z<==G_O4`Fz|&X(Bv~{=8(O&DEF*$|Rc%k1OpT<*?r*yGN+j
zIC#`j7FsmwY2nYr(Ng|I;Ek>YYP}!wFN*nq=(XCn?{{=oppBlMppiAU(?3_L;^_7TqL
zy2NPY)ikFxI@akJA&Vr*w{oFz@Ddk*F)^WwNb_{|UGQZ5JK$b_HNMBx@!?5ROWJRb
z?|%5pEBs1J{X;Z9de-pZvHgLk4chj>y}v*{)*i;a9*Ug#6Kw9C0YbGa@=ARsxyctWsHZm;5M99X36^L>AwBO^Z>Lw;|qPA7FScR+5Lm7
z$!9M9RIwVi5Iqf2v2w
z55rxZnl
zMgI8HUR6&YkFby@?!q~V4OQou5JotXb}0S`;YlHJ<%mJZ8#Mu16ghX;gZr#ple&7z
zE3qfKUVVvnj7Lb+mbMcI9XNxOoHQ-$gs7bSGrK-J@=5cl<0noXulPdk#W$Gt0_}k+
zcZvO7jW>-dqD=H}xcDR^Gq}N)Hq`>pD=0oCB~J|5W8Bb
zW=#7G5nHHcUC+F8kVcy_$Q73tn^xd~|K99;+^Ig0MEIt7Qs_&G1k(LQ=9^{KQhjD}0F#5$q-2DHi!M0{GS#vaT#rD`WA?yjFk75t>~vjlP4
z_u^1~ICv)H3v4jGb`pEs1T=SYWa9kh0=1o(p?y{_Gbd`VpQlxHYB#8ju9Y%GNp{W`8%cch0RFpc
z+Ig}Qm)agx?8K0u>t_AIBgI1AgTBx3d@n(vdkF2Tp&jZDC2u>AVA5ch)+McaH0MYQ
z;nA++gi*9Z{rl+?lJ$sM!y;>z4!SU>_&IOSd|?i)e431zOt!x
zG2N9vB08*|L*gWpE*RBp0aS%Q=~CSTm&ljd%3Ro
z$^J1xH?FZ_w%w_;M#x3qCD%-}{+NutAP^LCrr(hhe>Cmz4Bza=c?Zv&AwR~)>izJj
z44l(d>rp9H!D7gJdcY(&Z?vOSHv}9;gk+x~IY#z|$SqH<`{SH(^P#n>sz+p6>c3LWX)mRPJb393i^9oP%Yj>V|}7V87qx{AI2Jq
zu?7_*uR*`$>-6mdPw~EF)bpmag3t2d301b`e>lt_#r8XU@J5Qd+E?KCL$Ai6)iQ|t
z-v)d*lmb{_#SBlp;j%ZFOAq4hICZ9v<($PFR&FEcc44}$9Yk+6Z>K^Uv!kt
zBxN1Z^1{Iiz1TpMJ7E7D3YMul^ri#w90i!BLdoC(gd%{
zDM?psgny--kH{mUGRIX7EzXOzL?NA4T8+IA5R|+ddGkao>aUQrQn)0@(`kn!4Ju|>
zW~F_$We&7Uj{@GxKFcw>d|NrPmj$$>hzCXwYM;J82Xqj~;$?p4f|P1@i}{mp^E!Fb
z#xSgjdP$QUFTf_;`edIf|9IXC2hA)S6ySeV?$@AI_OJgg=`wNM_2iF4Q(d5dKPIdB
z3si0#zZt4i1Nt^~G@XlKDN;Bn^~|fvqcsKO7-t00rT2)NFjP;&ImdZfo)<%SoOh0}
zUJcf@b&ZVu5J}Qo=|PXMS3m
z-qsmJ*P(Y4k6oou*JK8=cGt8%x}Wm=ZaY<$^XRIFIZjt<*L{%tkX%c$?=lH+K45RuJ2``a0#>h17mi!CQYJv$f<{9!^}9e+Isd(pzch}V~EQJ
zE+li&psnS9F0`+=d}tGkPs6s?Ic`?1M^`s&`v5L;SBnz%XyA^e)WTX3WGCAARH-QXq5O{Q*g4$h6%m>zY~R8
z13SYF395hpOr`w;o(oz$v)k+J;l=g58SQs1TS9BU1YSDCXLPcVD;V5~^b)^eXbHhc
zTA#d$3z(^J0U7fZsSj&`SpU0JsgJW|BbUkPaSp>N#hR)_%eStnQ%6V`PouA&BXYV(
zY
zV<$;gm9yFxkn!uBGr(<(>o|>SdC2<#AtqHz^Bh5K$qcuUa&P?)`E<_ea?3n8MzpEG>
zcsFCtrzAPlIj6bo@0g1Y(*4b7vu(c0$^4kQOWHEWD3mRk89Xjj2{u5fU
z0o1Vx;C1yq!voa%L(;Byo&91Uq}7pC3LfPInF2^p0H)80bovClcgQ)D3$q6;e&K5#
z8PP&K?f?c;ts9cqqT$g;7#s(?=N$tuIA;=ait+>(syY=9O^>4Q>bicS*uQHG%jD`=
ze-FG(eR|>J1n=SqB_5$V=lRv()#gMN9~}r?g6x|5fp-*pYF$cX`{3YTQv4b|qB(y2
z`MG}&bJ)QyJ0JOQJBM~z{|re^EN@qMeAL5(ox{+)iT3&u=ue3X*|oG=5L0Zk*V(U7Gxo=;)@_g@Y5t0)
zQ#qY{o%+MI7Nd3+Y9H;%W38an3uiq>6akue*v1rE%Tv6hY{;D)gOLvXAx1iek+x|D
zj#O<|g=@iAlpmVTC6Wr4FchIl?PU9*#U#c^jaIq(*z?o^NuKI%@Z;N=8*evebM&rk
zNTiIftxLaF>9c~X)!ly`_?G>1>W^$S`y_gYYs%(igXw8{PyR}M?5P76S1IfJq4dzgn
z#3&LVq(71ZVSidfa^GCV`_|9JtLu4$W`Yb@h{!mHibC-Gs&1VeSKr~sLem{dz`_$e
zq+0OoTP$QZrJX;f3Nz8-v}KSp2YM`wyDNEx%gR$$3DTz<%BIl?dwX;Ld*FyUg6OP8
z)MDf3&^zOOp0BTscB*jgtfv)8S@FvQtBY!N*RM_8re?4TP?>oLh_dh%tB)#)Dvy=11IpxrlH@^Yx!R2Th>I0$<4!MwSBWbkF0?e(6d4?&l}
zGnzDxL4BJ3vznr2{W|&T;@?v%7k?rhgSxL7(<Ws|1o-R$@=7J;5}SP@AhjsgovyOE+aIb8
zW`Z1DQ}lARX_A;g)$<9@bv6jqcm%-#mCv?9lKWbg1P>oJC^+ksnK
zV?F?U>AJm+^f+5ck7F>|==+EComuujuEso$JC&)~`p|?X*gp@*3yWv$vu?4)*vtjg
zLf7~zX)tWRa?7im`n8>;=>#uJ+;{b{d-_sI4*JkKBcIx=UfGN+EL2gF^r8Ws=or}(
zoU3W`OV|GW{vt`)g$?j}QvB#9z*i^Q=J(a9-W#T#SrYim<&njZ3*R(LIwdj~99ZDQ
z1m@S(+f+;rSU*UcqV{0lLe>w$U-yTg%!orK-006Yx3p{M*T97#Jtq8mTak}2@azYJ
z>pj6C-~)?ML)U+bRv*&`PEhdP)4Y(-NK!+VG8I!beb7=_ZrgEG(N%Yy?Isy6u1q-%
z;HQp?b+8WMkA*i2p4)biY(ZoRg4Cf%mi<05%4u1h69>)cZC5{5pR3Dg+fP^wIS)GA
zfL}#~!cFV)s-OqdTPiIaa5q?X;amzphh)~Lh28`z=>+r2|?#+P{q6pT^lyEK3?
zuC%amj=T`8*T9oq<+-TuJ1z|5lj;}$cRs1@8ONYtSjrNiqe7$#W_(0~&Kv7d>ht4E
zGeJv%l(8>}phKfpapDHm>w4tf#_K9(l7te#%;-gdo^R&wGQth_M(<)o#3g2-xyPM+h2*+5htTn4;@fr{G%DVB#kRN``@4KzV1Gk43lR&0m6f`g7v0~H;>W|vx!R^Gi6mqN
z4;!GVzJY_GivEic$cKq`tx?NB*Q;>9)hRP6e;Ro)$#p4M%gozE%&+t#!VV|tUAm_A
zh{K@|PNt|VI)&Hfl5H8j+}3j>zjvK2YOGZ%VN^#i`BcgCMfteMUq_LF(y&X`A9+xF
zYDTlZ!A!Jf{oXd0eP_fDoRVSVBw5J%(v|_=8}Q=Q8Fokqh;pOzP}E;!kSUTGqH?xT
zMrkqfkxlrDc$&S))EJ;j;$VKbbd)I5G?xHdd)T<5c8?;b4x~@@DI)pffx`z!hx{E4
zW-l^Ck0*fQ`LW6mhq!>eUY(Le{@Y?`9N;i3i?E9J9mS(KP?yH#dz5!yP$@z{
zlPBYB4x9->26(Wqh@(|8**<|VE(Y9CrA5d>ytLb>T^P{8R6EUToKAqZdA11?=0zl0p1?i}*G^wZmffHXw
zLczX*lHok6cEmT>@`;YaM!$LOB6TP1?*iVM_uilmer~IEsheix5rhb%U=5cS)=zt5
zKUrq?t!maakJ3KAAGPmd9-1Nj2n+6J-ikT1qd1$z?6OTZlMhFXcJ4-(Z4Uf6
zJ}Wq&J+|?Qf_St|R`rS8JNpA(9!D^P#|p@oSKW9k&-H?~MnZaXK
z9V@NHw9jd6@U3OdPjbtqE9x)MCXyFRb=%NYIn+zc2}qqPzI3To4^(X{GFxz_NpwoHL-icZMdi?gcw#@oeN^foN(OtTYxzg}w}ifRVB*hwo;ZE@Gm
zSTS}td5l#bi=bBJ?+3POB`99#*Hqu2Ctr~yDj|X!p49NVebemaz!wR0`fc+W5#NI>
zNhxCN&R7?AsnqF8$crs%SFu~=)c`eko5NdjoLp8sRgBpg`{{mZ@oN~liAFAsMZT2o
zN5R#YjXc>)Dc1x}DUtFw(6?Bz0@5CIrd_Lh6#A$qO}632yGipX=LFfGR{yB{9!$G&
zXzRc+03SJwqbziJKlkgW7bjGmfjl!Q-FlehIYk~UW2QY^PdgPJmV#VnnmP;T+?$wl
zk$=wJNr5@^lV&&)H=3y>dBXe3u?G-7vML9|JCP0)<%?sb6@2+M?4CEZNe5m_r6a2*Lt{k-1i
z%)@}SpL@UG&mYA&^E~Ig&pGdN&im)my!PpK^7=O(`8vM(1;LVtEd;7r#B%7w}Liw2FL!EJ>&Uyc+@eXMx~
zGWTu4s|HQEdK;{L%f*A=hTkf`bInQKOOK4_qJvlHxfht07l)C6BmP7+Q{2$rR*0MY
z)Z)AxudY}t-yReojpN^~i$t*?gY+Q_qGP)rmINuV445z-HF_qPFAdH8*i`a
zRV(bF(#A?ehZvrDMtBZ!B}OgcL%L^Qr8A6d?qm__;Ygv+08tc_DNj*W5bnf(_CLwm
z@m?qhwF6W%L}DSrsz-SObv{Xv{AupH;Jd78+td$=
z8hjS_Mnu>(aBzocz#;uD@wmb_A=UjA;FtaBpspYN)q!7p%jVzG^a!UqdUp{wTMI5mkKr%MpLb$B*^?
zKpBy=(HKX3e?hB^8RKmX|H^lTRvrHJ+!5th7Ka6UIrcBJmorMTRVy%B=@FttO_ZFg
zzm<|s7KueI2D)zo|B&yo2}j?~CrQ#PtwHu(Ix_WB>4|LB)0m5!o9vI^-ZhFP$bxYS
zgjNWC`ESMQ$6L^TTsniKO3rxwrYReAULoQ=qKc?7hl+?v3=V_kvBDtehPq>M@G3e^8$2
z_ieBl(LFxZLuUt&q7j+fphcx#JiYgy(ktK^t+G}|1G3Y)&%HT#R(IQh)d7@j>>$lv
z+`!eqdh9_QomVGlac%)C1pHLV`;|6AvU_I2H_0dH95eNwIf3p=U-7xQSstDn;vdo@
zA@7}J^4^?C1w6W862W_zWK&!_1I$7i&ZO
zW2ZNPPGObbr}qqPDdzN2(Y|7e_jSCtar)vmGb%%b-gDzU!d%<$j?-xb)TFs=&=!kP
z4*_>A{?mTkwR;LS6uSFy*9etB!CymMN*ipYY@G^cPj!>$GfzoC`dIpYtTyd??d4M1KS_ZLn_Sal;<)z%nqA_>$!a
zbWf?E^M?G~sO|y2%$efVIW)2c+<4xn!5aB}>UARsLwlaxX_0e!k-^A0$P1ktI)3-Q
z&kw!@8<@sp@f(6Sh;zAJnOk>oGU>`C{H6)s0B=a(S*&TU#y=)_O@wtF7IqW)01<&W
zL_`h=^3F!}YDUHE
zi8jOlo}_1HxA)Y#Y_MLya^;n{Rm6a-5-+k#c84-crXsUskNeG6xMhS{t@70N32usc
z$KLhq$)6Pz(YDfZ;3&1c^r*h}hwT?+y+HhI?v9sUs9kFt5kf?Zh?oi#v_N);u;1#o
z%iq=reIpFL!5H~Qmq58$n+muO_;eTD$QrD@np)x1?AuS&Z1y9!L)=u0cYfQ2dlNm!Ay=2bA@QK?1Ii-a0R{$tX1)vT;+7*J02JV!`p5Yy_9~)E~n6IPEwnp)F6eIti
zc_HA-Tnwy0!W}5j`DG|7t6ZgG-sj@9X9m-l(O&~5eAlJ`0icU>6z`jEtKy;08KmWi
zV#h6{COfr3TSxX4vPl%DnQ4yTb8y4w06Pq#8QRbO4RcbS@v~d|quZGxQ1-Y9-Kihl
zvA72r{~X;BC+1ew&>n1p%?EX2
zikcx`6c3$Y%E$gJu686ejAwENC_nF0b0kMXc}jL0hXOyKJZa^v9Bc$an5(Us@?3?}
zxCth_w?Ch7T(atzbv{%}4TyZj)v2cZH{BF<07TRF!vo?XiEgLNbs1!FFpl%>BZ^5n
zAUTA48GuR!DIiajMY_9-ML9O832|O=>vC6PnMrJ1CUml!di6$wWPWf$0pS*$yNcOu
zuYK)S+9woLV@=Et;ts!ZvSxoFA<$G??{_1^8d`k#hJciUxg;riPkv}W?3#+~&M1=3
zis#LtIYx~E+kn|)>rOL_^-iK0G$LQ0qO@pEiQAkDI5qqnke2gj*WAIL#dGi&iCg{T
zIdvjmrCUvJQ5&agh;v$f_gf%Rn^hvyfA0>Z2<
zSIr?F<9m)~oFmup5x(tVZ2+^Ak8(w6J?9cO&g$W&e4HS~^X?xo&US@M82{RDongiu
zi}i#M>CR6k9>VQ8&LAzoSO|~e$v<|m9i7g2X2N?VHXu2I`W>_e#U;T00e=G>WB`9>
zaQ>d^PX1^rPWN=|^R&A?R@JfnR!+6<)e3klY7paP+@e#9r-*yO1APPMo6a^!7qqI4
z${APq3f&1&*b)2DX3sQ_b?7l5Yzxg+L$5AI^`!ym`wdoAmvLyH+G!ORX`t02m;1^O
z?b$5kE4-br%qHJ!7!TG#k2Ru|z`MoO6Ng^%P-GfWSe`R|a7z_=r75Jr>ed%Em0I{d
zD`fkunMqvy6#RZKNiPrXWu9?hFRBm%pn~e8^y2$Pe=o52(dsnA5*GF(hfWjl7{y?6
z%2vEE@D!6K*fF3%XlXIPOj
zdE5r?&G%z3dZri(_}nH{e8_#*9q2Vy9r9flJC}J81;utE{MWP_;h7GhZ;XaL`#f%1
zAaOhdBn}{RjD8469ObH!@E3=?*-F33M>2r)jNBODalp>re*Jat;(TBP<^x*_r~!*L
zs+_z^XFgD-k}XE(6@goSDHE3G!S49%%`>MyIny%LLvm_}{wMZ8TbyAnY8vqdED`W%
zaS0V(pY}^ZI^A1wW_D{J
zR{MHH^DZ;Zv4`T0#49HG>E4l$RL2J#pS*xk)=fJ$0@AfvlGQ;C#z{IJq-ju#Pl=L$
zMDQ|6qWcayEom4JleBLSc2nN1l69;7j|uKm3n=%N#!6#j^7ilBkl6u`C6G?wfwSI4
z@^Q)z-LcIs>jKkz(%DTI(=wu!WL`mo`{uVq&+0u(YRTV5v)E8B4wT>%dXZa3Ge&;L
z!I`@QXKeRzHecB^UlRt*SMrM)Hp-UN+!<)!^a;(@#18b27+AhywO;-&4a?P7S_5jT
zYTw7N5iCTjycN^6)%F1M_u+E&4k3uB^js
z7i&ciU%c+fxV`U3#NG>R{)&G~x4ST-p8%f)^PBsgoqPXM`{lHX@vf93@UoNtXmkVo
z{Ozmi>Hg~>)Ss%c`@B-3=E=i+4ppI9++f>U>zZI0r-B}YXC1HIzN#kLw(20Ar1LD(
z^WEwRNB2WEgJh!>G(lGLHToT{JyTr;7UEgww5c>!z>3=e83nvB^5k
z|Ne#VUZ{Py&}lnX8}(l)ausY10ea%>GAp*Voj%
zTi5`ET`P6$O&$W|Drm*BE~p`?tnLBW1pYSS
zEs~n)^X4;(q?cr;%o)m{3AE37KlC{Tdw}dPRqNq>p-Mkou2SCKcdF8*F?E0%uIY1&
zX!!JOilDQT>4h7)2606_6)33AY0wKvyVuB_be41@x-A%qa|0NEGEf9P@N9oyf3MTX
zA}lb{@@r(XgD!t#=XXxaX=v4)yX9?duqJq=Q3B2ojN%eMDcE(45Qk&$v%S5Uvb(Bo;w)%kyQyN--huCq?Y%Pa-RP~1e_aDxSREt_
zKx-)eMTy&FdNY$jny&Jj5fbL$`5A+`5anS(X60aKC8DHdSDSi*d#&xF6;a+mQ$Z}p
znSs2k$h`eNYtoDIs(&ilvjo21D%Izq+nNxMg$PZ2x|h`uhg4!RYC3U`+=UoP-0V1s
z+0EX5tdMr*ys@;?UDhq4`+WoSUk~tvA!oG*+G)gre^!%bP+T9ewHCi3M(0?_N
z6$iEm?-KH%44HratkdIytwU|A%4El^V1#tFb58X2fs`q9AMK&^3k
zpIf+itGd$)?~|s*r3UbRUh8^jfzd(Xm|fNe`?DJMqYeyNSjj4%<@VO32nTfCX5QQS
zhKseV@6o`KZ?g!fwyUM*5IG0?$(Bjmj`M7o-L^C(S~71Q5CBOtLM9ARjXlNQ1iCqU
z6LK6R7gZ&q(nD6O;v}8h4%^#E76X{q^OJ3C6)D~kr;CSK1=uPU!Y9luhIwf}8`IFg
ziqDfpPLI|p8v&Ud8!KNup)LvVnJ-87>AszV*Tj3_8Q8uA`0U89N+{^qom+uJ%x06X
z2Hw27uk|N0!&dvNJ`Ig;GUm+qL$d>$BISYr}9@T^sHrm
zmG+ol^KlQRj_Yu@j=ky6%GlS)(P69WH$F9G5aIwo>hkFpB)d115_Ub-999c`GrU+D
z^2{&~R(nk0|E8yugGx`WPyDN%d~?3vQ_6szR_A@cCmK47$bAZPixD#NQ!z+w@!nW|7b;k>lNmOg7|^+Mf}OF^t{|
z>9}*P1I|m*mO|&p)^v7SLKDv`xes>5A)RWcU4GuD?(Fx%$iMUnPP+<{x%(RF7zbwb
z4)EG=pAGUSF`F;+!qTcKd%sfB<5ca_&}mCH*l0h?xx$>%3RePO1Gma&Ua45ZoaB{E
znp2}hpk0UmlvW>_HJj`0XGkuH*@8G9iSVpQr)5^*{tt)c=
zoIBD_zv25U02?J+f%PPrmET01Qg{W3zfps0jj|Hq5zIqYfgBHsg5}>r!y%qzyE-ZrlHX(lQn6IycCr<6NSs6k5rUXC9yMte3S#C9g5lU=X}taIjfSkpC2#W*$&k53lArNKyX^-`
zfh^VAJ4t05+J!nY!`IqM-nZI7|3B?2Skdu!2L5^%X9|!Xmi0!;25qG4k-G))5v$;O
zc)1|{2QV0*NeQvg0ug&apUo*-QQ>3pLda+0^oPF{ydOOw86J5;@_zUq5@s8+fl=6L
ztQ0IpqiTz>Qk8Ess_!yZs()@o-iQ$>gGtyK2cTb-pF6+XiobakYX_n)6Ef1}ho64r
zlSdwy!z(cvbmfsMo8R4a1@zZ|Ue-&XW$Zg0z~D5i8~UT{2_19(M{j%RzEkXtd?kGg
z5a$oeUDQ#!`#R>4#SsyQ>~0TI&TwA+%TfpSBrF^lWwBGkqgXi7B|oW9XNNexxL!?h
z>WF`mu4yD2WVSkCq|1sO-GCfr+`hHHcHytI++(w%Pm&!wvY3T4HYhyF?1^N53waOO
zYByym{z#LD-*$o2`ZaqBNdnk}2)CanZ}p3i3c#VFv=Q^S9e1tkO7dWfoZ<_nr;vlO
z;~36iia*kxBHU0u4=ENpZzJ^=h9Q<9{}D;O&CUu$3Y>Tjs}NnM3$e?GUWr}t?H$fgru38lOD(|(S~#E9S*$z
z)GjMHE-xeV)=~2qaUL1IC!cA9jM}aglK*E|Az|m`%v}NvAS7?xfK0%ofBB6rtlv2J
zCC48}+_73bv5d*B@=vbdrtg;JmwJV2>|))2$=?>j)6IQq^;Xc@axQPgTdtI5^Sxxob;A5cKOfrwD@Am`U
zz-lkjV^on5@*D6`!e1tJHM4z8c4nMLsM3QQ*dC_vX;kVX$wPz>gOG9*UM71|#%!0p
zRlu1UGt}?46Iv{N79XD|OqV+O`JS8etlzQcnlTT$7J4%PsTI|{)R>w|9ZOCCQ=R-@DuVn?x$bqU*!(^9=mUrCuB7zi$Ak6v$amq
z)6G*zHvhbe)TA(%_xd!npQPnG-0){=b0yA=85-J481Ik7Ma{rEzNnsPdDA@xy%(r?
z-$^s*7qS^s-v!wDDpcIy*-YF5Jaf(b6H_-nddigI~wSJo&Y?xH9d^q%3>_NcOJiIj=C?L$`+GBH1N
zwVj8z-X;p!t3Y#HlLw>`x2d5OTcqLg#vwahI-$HWeNOu$}PM5B0mO~&uw`U_Krx5pib>Q
zF;bBKUaD@k%YCI0lHFT);>H1Zoo7G`H|XNTzRi1&J2S_WQ)}`Y&=oUB2`BBce+D$Y
z88Z@v1En)msLdJCw|V!6MfM_#*kqra)P#tm_YlK3SsqnNdrl|+_B^zK8I$Eg;C7Ed
z1+3*GuueIKF((x&-B`zRtc<_p%2lFq+6VetSBhRJX`2tpo%Z<9fwxB+bUJ<>Tu^+x
zh}}`{kGy)^|E7G{nbn95>nju{4kz6z+B*Gic$Gp?PdtAO))#mFD1#eF33aosLj%l1
z24i0SWLT^Ip|X0v7&>PhtEwcD9MhoF_H!aXae~DGrnDU)px*C?@-dT-&2i#2>
zXg-><4{4;_J4WLrPwL!C&TTy6YQj-I2HzRdRK2*HNIwOFJUF95<+jVJpjyU>&d<1L
zJ1lWO^@S{rTsJYIgf-63?sLIQHHe(n07*b<$qD4HdHf=zQ9`*zoL+9vuTTNrCJRjV
zU#qmY$$p^5$0U6&;~N$hAVP3x?=Ghq?nla|vqm|iDdy~CjR>m)^qUysO}Ptk4mhiKBZ8z0XK|TG5{@7O>8d5L
zE8QwK(r<>BuExm!?1HD#)ew3YNMU#)(
zttC)QqXyPoUHS8aWog){*>l(}Uh*_kOh`yh2=9+~NKRleA-QXw7!w}jRgAIUzTmQ=
zBCOredlD4%3W$6u4GPAM@2E+ZU!6brgyfNeR80bL3}lyMys_eK8Y#&TwA0?Eorw4y
zE(h(&M?1w!e}nrgH*G-)q7}LS$7$CCzYz9VME)rwQ=$YFp5Z)t40+0HuAB
z-KaAW2jd0m5v|2sm(yO)?pca;yu|VqI97aC%N~!npT?A(e1Bm*9$pw;kL$h&if42^
zrcsMl9l`1{~ebn+gnlS7OF@x=8tO3oX
z2)6#I`AIf|#{!LN1Z>(g+HI9s=iD`^t)RX?t|WJ!*=3IucENHC+v+ArA&%VVha#`3
zoMJy6Rcq)hsw~`z(>OoQD|O>rZx`yryb9~9qh)o%F$tDVv|AO9q^2xyP9ckg%55D>
zd8dk97O^`_yDHT&{dhgiGc>B)o(U7fvdK3-&Bs7>8S#c!W08_l
zhMXKIU~;b`7tzB+FMfAaJ;UhLfnGc4B}!pQRpw2x?b7ZeFAb+b_fk|-7u$7|ok@Km
zA~?5a%yLNXhzFKoQ`Dh4p8>8d?BjY2YOeEC13KhAy9n$Q~EcZ7E~KkM7>PcA`7yE#tAO#aMDM!OER4H
zg*EgxZ^^epsc@k0a$ou@t#(=48G*T5>C>pJyAZ$U%+yWw6n
zGwQb)S!DUNj)_SR&TEDgpwehi&&(vd^je_Qm=3+Q+%Er^;-1mkI$)3yYJhG$v$)Zk
zxHJ8^y&;Pzk2$3^5VICw$C4FF76j&P7BmGE|;W46}x2>gVyzA0n~>v}VWgzg5FS
zf8#~G*Uagz!29vY7L2b{^Nj8?AcZjbJvU87pUNH3B%z%hF`*7J;SW$<+VZho3jc9Q
z9-b%-kWg@x#NNtxT6H7@8?212@xRB3?LeTV#p?l$7Tll}}u1i({X7u_1d
zi-oOWPD=%`XRhzSU|u{5VQ+XiAopUSd5tgQil`WM8l?rG}|NbK-sOkg!mg^j$Zy@-(v!n$3AD!&ZtcK%kZ&lwssq>#Ezf1$YrMkq4N
z7Zvak3qPCS_E>>>wu=94f0p!A*W&Z)-N1Y!o$Vfxb7B2_`h{~MeH+NFn0M@8Q3DWi
zwb#sU9Up!+VhVr5I27M$tXOPolRe|A6g5C%gc;Qa>MQ
zBuzgb-GJ;C+JjE)!S?U*QE1nxpx;9lev`O<4py~%-xq`T$XZ(m?S#6yJ)Jl&$@-2+
zR7TSZ+%sIh!#T;MSh@i+e&p3T)bec<4^T{hHMibRBuVi;$=?avT5bnM))(ip?Pfl`
zU0;e#3Bq`rS69j_{5q~`jp~c>_Y~Ay5h3((|gO&X8?7q8#!uBFzft#iM=UbDY|WMukROb7G|da`P%ySo2w
z2;C=Yrhh^DpcrNHxYAgi6TP}@HKfxB`R^?MBPw{C{5APXM%0TyhVj^k9w)h(+T7PS
zvs_sn|KBMCBs?!%y9%ABh+zj(jEZ8}%hi-OKz=Olu|5HLJOTAIy|B5+Kk3yP#q)%q
zUq1WSbD*t5J_Yw1f~c3i(HMO~UDjn_ctwa}`fFw_-2?RYVJpSAU%||5K1TDg`UdS$
zl9M?eF22ik4%>uCa=ItTrcQ4;yNoz(=hZ%nxPZf$tGOTdvAw_V@_5#>h;t|Wbi(^`
zp-!#0%PV19!hM*A{zxKKrNG{+IvWgCyQ!KLr1}&XL)Eq`VyLo3M1)df!K=%^
zJ;T1SAdvWX#H$6$*MGhV7}bPOt&Az<6pd;AXCz0Hb(=UD`njX$S6-bN2ywwt;AC}=
z9dSJ1zf?6M?_z00uZPB@veJm~tQLO98%0gS-{5zTaw28uhuTQ;M`f(4S)Jf4QR)QZ
zI&vc@vMqlsovg=O5OWtVyQN{Uj}nrX?uu#R9%l#vl0UQg<4OUwUQ`<3l&E$L?1v&G
zAbqGQCMKWo>Z`8fZo}s>G%K_G%B`GqM8p%Zj{>_s5WD{wq7PJ5J^44)rAK1Z
zpn+);G2iF-S-iPQUmNcEdJUpcg+U{9r2W!GcWmU5vD?1nG*G{X|Hf%x^qf&>cp_Gz
zU_P%M5xf7Xp|BAf3=m4W5D3xPOLEE@|R)?Yp%1Fnh8Kw_q%%
zc^$C-7Q}b{b=Bd}{qI<_CQQ+`Pr?+PZB-~5I4hBEnw8Hhi+@
z%WzL;kD(S1>6FEr|4e5jJ~`%PcOKXZoJhV(Kx0!k)KIOdH;*3u;N!*}AANG<)O&~q
z2cPlXRQNVYMJb^OSI`lXiddh76z8a30KOX%947mHnoc|AUi^R-5gi=jv4<-=O~`sZ
z>wfomk{-Ze3AVlLu3DY{0wiZa4V_~+xLAw4!^rD)|8RhXO*@6Ih}=kJ?9*-(#v%Xr&P6a9PX-<@`;hCWU6{_uOp
ze@DLtc6cST7M~o|Gm!U#9t*Co`g4-9t77UU@CoOVf{%BwT)ohF`>GPjL}x8OQE~nrNriknN6)PAUKz8U#>Urv
z*ks%oBy(0B-ey4U8^R2Vq&@Px*m!<>sAtj>^xd}KlKkp|{3^1VWoI`Hr|)AwNeSIL
zRqM)>*3P~$BqEDR)9SmqtbM#eWgS6TUB4l_UMe!+Nc!C5N3FpBR5g?_WGcGB3BAlK
zF^Qsh^Nt?e(tNddk#DN%=809XWs*)?+IzDZ{`r?kYC+5^)69cjQFJTghy*VNxOpnYsXEl60tfwNCIXvhGnn*A}8`W>w?iX6kO
zB8+pYYJYR7hQ)!R?Q?(X!;Mb&IeGMxKMS1-jKY*v|N2x|S3ul7&v21$BTZ=akpmoF
z{jjftd>n&U{}SEMk+k|WZ=9;7B`PbQGsXd>SG5WUw2nc2)0HM@Eo?@Cb4w`TIkpNb
zwC36ll6A_@ecW7gPXT>%^N_NarT`uJNFu+HSA7eOHlDaA0(U3m3*0x)55b$owP$l`
zoL|zetf14OYW<&fF{~~IqkWPdY;=p
zSkkBUq883=CrN)`q%9B~=^SU2=;jxNG!fM64S7>2;$o`1vIsY`BjXnxcKHj+az}K9
zFheq{BJO6y54chcT)
zWGq+slq`6!g=~1F(F}?`WMgc4FyuLR=k?iEFuv3eeerZ%?|kj9tg!>^2h@|qh0s$2n6yXrXyF5c{3gL
zGR`_=xpN7VGLoaoF7)HxkY95^KBS}L9uLnIL#~x^m?Z2i2cDlu6(+WI?Y1+t4MN$d
zI_Ji^=Pj)*BYt)yEl^p*_G2q{5cil4Y&j!Mi2`v$4x-U^N4kkRhnjJFn%5hysynh?Ax(HPLFqr|!s*2iL(Q%RAyZNFphB0B!gL;)f&Q1>bu-
zP`v$(fh*2Wry@{8HRna2CVkyze?;$hoa-uV2IMCxeAkg=j2*8EXCf(?N`o_!Zp~Z*
zfByU7+Ccf-U=H?A$g}3iu>Ws7Yw5Hfj|1s|dAZ3$V_1w?WZc*_3S0sI3?lR#IS-5p
z*^v>E^fLIdX`CjMP2;?xL0ki@^AtBymxH+)4ZoSD#4eBQ6%JX+zcTwPzT>&|i>$Z(
z=gV+9UnnZDKa$H)@o&5AEH)XL%ea$pduQO>-}iMrYis>2wls>`qVt_1w@AC-w5P<-
zoeoXIlkkDdK3*V;F3E~c+LO6Uzs0&alI~^}gP5QNlHce~Iz4WK|M+X4X)pOV@0Gvw
zMZ$X+8O*MLFx}93f0JhzLR8iE;V3Q1P`=ic+0lx9#y4}Lp+EBup)
z3@I$TxLNkS7i|9QFl>p?@6ZQXEc`=*Us2nj@%G-~)FN-6$Daor9h3Xpeuc&9
zPjWV49?IvQCaX1JE~5ehXGVSB(=b(Tlpe{@CDoqM(8B4~Bf7g8Fe}$3Q)!j|1i9_qbq7dEV-2@=A%oYzQFg
zGLd$C@$A|qkn`Ksu#tXFt(~<4IXxmoi&^#JF8rFR^?%{}45Qch1HQlGuSh5)UR|ul
ze@E~Po6V31hFb9IW_-u2E4^32CxRxrT*T}k69E=Cici23g>n3euTiU!GUtBN#jIIJ
z!O1xZpsIZA2VuE{TNS9~V|M?D-W%T^X%cE2;M8LC=WK%1f2_GCP##nL0&;K^e&&?H
z8Z^B3n!*Vc!@^vS`rRSVc@?8gH4w8jQy2SH&f#!(^2ls+EhlSs)eyRUWd`oZATbmmdDym;ls0e&re}Lp~
z<==CCJ#3acpuzT@34Lp>Si17h%DX*l+=rDFHNXp`tm&G&Z(URH+W$S{)zR?`wOWO-
zmOMwfuOt4fc=N+IQd2eM&byi<+!pDL$bgOyWVb%X?m6|piXfqQd2Z))S(b^L+MzAR
z%dh#6lXFCjw#yqY2tenZO!wf}1MtT3yz0f~nAHGeqRZcq8r-4B}PY%tyVwh%Q<74?%vUMzg2Xpv#Sst-Zqj(#p+<
z`-pj0E82&Hx^coxoxBiPMrc3F{Tz!6NeM-ZcR+Hwd5NU2)xNOIr9|2lHGP`r))p=H
z3zE+No5sFF_La3Hq0cUA4aM$~gcyn&;rc)sX#t2E$)1-nBJ5f2BZ&ZBPDI}VO_AM(
z@R=eu1i2w0N~(d1T{4I=mZpLw-aF=SgY6t*#cvV84A>>C!TNFJ$+g)MkRZ{&2{6+yJOrNbJ0+dTV@
zjYYrdN`w?8xEiviiANuwHhrU2lyBOj-9;S%)UXqRzwP)^{P5XnuG3jlv&hC$b^N`e
zgg+$ix4O2nr;-%r_*kNmn}vv4yw0UoOYF+qH^ypH;&RwrtiJ_?if|p
z#hO@TS0H2d98rbXE@6x1z>IFx;DsKKv!Xqd?pm*uja$iZ&q%Cw?dgBv?~9OiI+c98E<%blynHRjt@VG{_?;|8VojUV
zGf)@(F7SX5J6+eLmXBPBkhkg8^N=-LsD{VUy#QR9KNZ!R%CEmdPae>D5I@v4m1fiU
z+KOpL?}}-a__wjhK8_l}}y5Ft8LUmvtEg;%y)<}z7|3L|&#O@OA{cY60Mcucp
zwl8y2Eo93q)x*wA2`F*fYP|Yb&GOo9nG5k-eNDm|szP1x`Hs(cCF(ORpMM;Rh+%W=
zTSmN%oWbmQLvD$~vQK0=1{FZC)1(`SS2lO4TW!gOQKfB(F8hjUWFO(Hn#$X1X`hGL>Sl
zU>R=G3(gN|MQPl#ij4xiLHbs`f2awy#)<1v)e}N1x^(}_8dsJk-HRGq{tahtI3Gr)
zlYpI8SXBB&qU%HZv{rkvhaykKtd-OJs>ttL*34-x`;uuB+^!{=Q>PaN)wIi2zq;Ql
zE?GG>>fXrviW2rDVnkJ&3u7Zrxufte+DnE~k8nUgBO}>eG=u(yJ*ew79{~2mfo4Q%
zgmxHwOn-a|dxT~r(d5BdMiGPjoaVfpGKZnYGM`!sJEb#zZjju-3#zt4?gxjj1b4k-
z!W{#Y$F)M*@jmALqRd6y7x>Nt@0t-=rh)8=TvH+BP52ODy#bCAcH!T=z)wQ&**VMc
z|J>T+kRb|iyFCCKOo?*#U4~9h+Arw~@U7LvAq#;dJK!Qx?g}#cI$16sPIw?rQeG7y
zKGWafCWbg!zO>kj2%Vge?TuH|W9KH{zxOM?+fY6MG+KC(vMZKD5*Fbhy-mKzESu55
zcKDZ=c*htw
z6c}KE>SWT*`YoNzw;?Ux)i3>8aAyz(btSTQ>6|3Fuu?^z?*dLFa(5+-Y5I(I#HgL8
z*#_S%Kn`;lqxvr3_ZtW1^_I^$N^{?uL+9Mh_drkX_8M9de9F#vWE;)02>MO_f~!}E
z#+f)@DKq5%FHJcU{%4w^>xrh4$B3F*AQ%(_O^fKD{z+3NdXW3fkO790FESo;+mSCIxF&cIo0W;!tcfIprE2Z-%D^G?&l)TQFqtB}|dSmC}a(tltPk^{48+d8W(_PEU>}^vd_I@DsVMIRz!?7
zdG1fE6E56Suni|i;F!}sr}1IAVX|gJXzl)Hm#T}N2f@J-jTw@FI^8E6r_jb(+n1ec
zmvxu$n6+|)Zi>;BGDY4Rq4JK56Y8}T*=EYe3>CM(DB5V}O`zD<@<4|&Vs6dimfX<(
z>S7tyA-@ONtEWQ#uK;RJBKbW=1S3d3YKP1iQ_Xi4ejS6ItAYQlk^G3vPG25?4!&U0
zR@8fkb*_9w!}l!I=6Orun}M#(Dx_qm85H|8-qSdbvj|ah^}4~_SVs1sgfq@qvP4yh&p6-3$_Nd+F|hwf_G)q37q8wl
zr9+R%Equ-!8^ZM9F^ge26Zhz(i*3{@und8-NBy_p{t5LT!v06jSn=6TqJ(9P6_4q}
znUd}NRYondL6}=tpf1}SeW%J=DeW{ZsSR`&Km5XJvRAUo1!l+eb*)~_5kv|L8gP->
zk-iqc<^iYQq79hy(sEAXS@ug^Dn-{S)@+*pkoLn)jKcRq+K)Ny*}KCr@24B8;6JH^(+aiS5=y02eC&*{g1$iew?lfB?
z)TW!AaFLH}Fb@T~Q)ewF%0r_R#;-g(aFoKhmH1T|WukH6S!I-tWE$nVQ0^nez-P5E
zdo3Gf$~%-fN0^0j1msTKP0Z@zs3l*ux#V$nQ@{sLXCjMN5`!Z{v5X_Zm56`(o>WB$
zBO+Pc^0fFH@73Xqyn{UP+`83=2qC6}>0tZ$4jwdEJpFg{UJLoe%xQ=&*Q2`aZnb0!
zq~@;J<0i`>vL1@-MkC`PFAs4x*iA(_kS4y@;;7!M)M6*u-mcQ`A}~SSMRGi0W?GmX
z2R;C*qfuP@YFVfSib?CIDWUf=wQ!PbFP9aXdQh3k0=YAgx<;ph^zglY@96!S-r8jM
zC-i>JEi-&~g)B4X*4tg^A5}!i-iGrd3G+-lZPq97vJTT@SLHm){Hx~Hnd=UQdzdre
zb3cu7z5k%zI_&;oz5h^Xtj;D|Z6Cz}<(VJyO4-m70(miCxqqmIk-g`sg>82K(BAV(
z3nh;n9wgC*Px_`3x;^(GIy&J9=Ml8+SbYP#-8>H#=3J6$F}qmt+k#q!bCvjX(rCEs
zBsM{}Lhcu=ao>qeGil{V^?nz!YMDzcE~_R~xAVZ=RmcYG{sm@2`ml^A
zQf+&1Cj|0Zeo6n&n@MNR>Mx)PeZQaE!4K#M;~d$0Rq1Ew{rn_JGnO&$3y)?eUkE>o
zyEbs22<{N`8q=JxKd{>uiHL8ZzDZnY!QRjKcjE{N(dpxal4q`uG>+(GxQ#Dt-s3*x
z`jZYjdIW6gHob(5z5BL({K8A?;`-Qk#t1#+kKGzn+i2Sby|<{Q=`MLgm&OPT1sYLZ
z>X?gz?>ZNY7SFj(5isO?
zUe&8YUJ~;7Oc^|0xOfx!vhr3BKq(D-naSIm)e@rjDXNd8#AJkI6LSx|Be4=>6XdQC
zO{qk`F9W9nL&_>XT<<9&CS
z2^2qBfF2!7alf`m_+(c7R9Ry#httTYmD;k9)McKh1ui*R!i$%7(g^0h)5oZ#ra7MNA@aM}PPQvSv#@H0uDDLZy+
ztI7N6*!;RG(*y162&@&U>g&Dac__2M_n;1R*WH;=Z;aV8(q&ly+!90}m`aXNJSxSd
zIxQ?x)Uo+By#EinO;Jf2@lZHBa<`ZBm7sN?s&=FsD_S>?f>`w4<8>hmBR@~?zziKl
z<}RbS!Mhp(`PEw}BZ;s#AiXZgw8&ju
z5#E>LgwuYqp=`CwH=DHHmqsEY#dT_#ut!Fzsd+Ar--`Q!FlQkpNX1$<9`7n}QP&-rv;L=P65*(5s0v2xr7A
zWlBTA8PUH+o92@7FJNV9?r9IQsC+i_DLrIM;#k`7v6*w?(+A>c!2``=Kr`sU!
zN1uSBix44(h$T>761xUePB_EkWwJhN;JE6C_vDj2phv6g|C^*dW651A
z;|4l~PQYegx#5cNg!y-f8agi;UHJUaXGcbxe|Kc`L!W&RFgt&x%FLd=PpOXKdVf
z#Wbc%JTg2Uy~j)E>1-+|{z66u?&9p()wkYNMwcd@o-p0E5J+GlOFN`WRKmYjDSmvPncbgX_4Rlj5zu|lEA&v
z1;QyXKhsz+N4x&nCjY{C=oJz*K$2z2a5b)8q&h%>BQW6Iw{mY(dJ+n>C`ccSog
zAa&kd)|#2fir*)zPJg|SH2SC9XgwtMTi)v`flXabHx6c3Dwj0gXjvAbHsXcSa{_3&%qdTvK
zck}&jiW7FVA%`Bh>i*xA!p}6dpfc*B+NkdXB6KXM?zz)xod>#kG#g*DrX3X3Hva_f
zb9lqa4#e`mQcF<(Csv(R0E=QI@p6?J5l~;!NrXu1)Dp@hNFeQDCFOhMtviIX3b7Kf
z)WQ08WReG2AMk7;rrOQ&A8P*w3-KfmVjZFN<<5RTOm{LY=tMc?10fnc@9aBXDStGJ
zI?fyO4vWP{whKk`XCcc4Pqe4~NQ7UAycCG{DP!D|cYK4D$<{>W_KrCrO<;h0wT0c+
z6hpxzQnH#tx=Kx>IKZL7$dCk=IuyDj?u68|RAw8>-kwL<^U-#o7r&y!AEsgt%p2~4
zEJ}Wl2TLJud(ttco+&s_^T|pb~7XS33HToEAGzIyl$|C&d%!j@f
z$exSXrxS>UEBg@g<{_Z)m=zh0q_=?Mcr9sRv`6+`;<&ZA$(u;e)~zG@fGE9~NB`nJ
zC;E(xKAvMXkV0gcNoi-T@JkYEVQ|4G*RbLCb
zYA%L641?<%Aoi8CqEzSeVXcTH!QE7urmRa_dIWUl=MVYpA+g~Ea(*|I8r3@m{x1*y
zRoVZqP4t_%6VYQDlIP7yw;-@p
z%eV#k3>K1w9wCrhy!>Jeo&MwJayme-MQ41&)&$ZOYts#!8~izm`w(2@FtCo
z=t>6CA8s|Oykd3^9ei>tm_a|(uIh26U2`(EMXiL|V{O$BxwS0?g@G^_w2j0+9qT>T
zw0=*S$0~mZdo85SIPjc7*R(Lo+G~OD6FLDr1c|8`7paoa2kSbfjZDho{G3haV=3|^iH@9?21r<4%FVO-@V0W-VxUXm6qbuiwXmj2
z;zE-UNGy(WS${5}9=&ag1mxw=x4ALaO@tF>9E+J(WMp_=^-I%Y`n<^fCO+3zD$>B^%%@SkoXZ4+TDa*w
zhFSP^mq6YCr;SeSycg#eP#yGc%ya$SgeNFAt`x!Xzdr;!?fM$m$z~OF4S2J26V_lC
zO?ZzuB&!Z`q(>8R)XjG=%^p@~k_k0c#={Oy=z@XV)Zxk;r9Jh1t|QsFzjjP&&b(@C
zbUkXvu$i*oNq%%f{@4qIv_g%u3kW=q>~SZ%QJt)K?q$CETmzwX=SXsK&Daxq&$uY7
z$1;I(7E!_3i%QO@VUt)KGopdM_ezQI7@@LrV(xAFWAu&dltvIwjT1gHOLj>9I$$q3
z22)Gi;W`PlBSOuJO`5CtPWx?IxIew{pu_41%P{nz#18#sbC|l&{ct@4*FpzV57Ph_xdg4J3Dn$ia=KTlZNA^5n@+2IC4}jsn
z%#c)f?%8S_(JVZ=)$rog*@3+1N|x*8$elIkEcSj&+7rl)w|g`v+oa`hx+`GY1+qWU
zFVg8_jNOWTF%H&rve7qeE`n{IG~QvCB@)IPgnq#u$Sx79P6JNFc{)Pt)2D!8>Z?+(qt2hJNrGyja8gl-io9Nt48;
zWy!84OR^z&Ev7OC6?oguCryqZq-o=5`j;lz)My+-pT;E{??B{hZuTU2>KrJ)$>he0
zA!3sz8GXd~<9n~5vO{u3jaOGJ!Gec;fm|)}_V71VL{$G}^gXigGU$wLy)C+icn?w7
zsU7sT&Y#fNO}`9Xm{f!3hV^xCqV{7ue$jat9-dKsU(>9#M{crDha5%sMFxWu$p
zUSv825{E7oEgb97v{A~FMCxi&$!P7`*l
z#p#_m?-%e3OUT#74Ae>R2x|vM!iJDu>^otL?H0EMNCPtHH7Q$WU=BSus7n=fz_DirgatbC#Zfnnucx)E+0^oQl)CA2B#2WCvZx~W-RoeA}!<;
z5&v@BeBEj1wYGR4I)+Y4GCeg87WD#ai}Fk6*@52yD+6gD3bGyV&wv{N
zkwbBvH@LN4>9u1HVuorB8p1TKu+3A>;l#8Vye1vhSu?_!1&syuzsR
z^5RyfQLR5o^FsIR0KYLiyH{-IcN~qW$JRfl@6C~NYx2k~+*NUgUexI6dee<@IM(lX
z+WTrfMVD?et3Rx=fy6}Z3nwL5_38K7ha38Prwmfgg}&0LhC<{BC)mm)CY|Iy`NxD#
z@pX&vsu^$PIz|ta5>(6|9O7SC0pMW?WdcGIB(M2z&=J!mzp$rFEn|I7-O1zpj1P9C6m0UB(o&0!7kpDU$l5c{MvHb*Vxkn
zP{)AU<}NyoyZlOAb>^V}Su9{*A$vtj-j6fuVU>xmRBh21hiox<0`rNJcZBIAy9Ck7
zYy=W~ZL!(Up%#ZOHWsMICOn6`@S*;mCqBkW@4*a?lC=ZS
z%DRD8W}i8(!yjnLO)wP&^1k+%UJWEV?%lI-B4+*0h?*fnZ1k!??%|zI%k|NQ=<8z*
zTaZ-)xz+u!dyd!r?ak?>>r@9y4-2O^N7;Xyw{Ekn?Zu7#qlhSbY2Ja-8bPl)z4=EG
zMT<)XPt-1^t7<>}G`1!v3$uD-64SDh6^U6a9YY3la>^-{OnuBtKqT05+{)_9w4*vZ2b
zH&3$jqaS;LCCXQ&a0y2~PtWHOIFIrOS#wMy<|46Uy%*?Fh|(HnK(?j)6JIQHBcqT@
z+vSUBrd-o|arSG<2yZ1_Mz+2jAw_JWeDiyu>8Q(gAa`v@aPqtma=QP5?*@I3TRwMg
zC8QB`WmKQ~g>poE-4+}NnK3GO*D>Vo1;67SNAl#56_oZ|(j0o8*>ng46gQM{IQ~P9
z;lw{Oycf0H?$a!%x+AIbDj!8LjSXH6>!Mr_^-IC4tY6s0sc)i&PQUF3sdjp<8Zx6v
zmO4#dotd&+1@h)djC!}--{rfkJU_edNywTG!qw_lzFXgzi8c_4Pv~8k9~R>lgZ9o-
z&T5MqS&KlCX;(w0f!tZ827O<-?3t6CA5sgL6URB9F;Z`0Tt)F#+1YEnh_@p8Vz!P!
z+h)o+9Vr7R(I9n(y!HOCeE$ehAoM(~!cz{>KP;$x=LozLJd8IbP@y$Y{E7q5qvi{w
z4H(Kf3cgiyM*jcVbUmLS&KY;QLey`#E@Sm1-P8
zdnMr&=ho)a&I$Z31AXO^)TSXSL5qaSke|cKs_ipjzD;<_y#Cw0kdfOZXa=JopKJZv
z;1`%5$u9;!zerW(v)8*TXm5$^`P@Lwl*2A-8LXn%b4@w5m0G=t^9O3Hm`dOc5=4bd
z>alWRF2UY=YS*7ZGcXK^*Jg_Tt-4dtLMQp1x>M3}FY;T)^q=agl<+A!5vS;-_a?Xz
z4P`$K8I!mK7SQZ-rRxp^9Q(dqet=WZ5k{y@R2c{MO`J)n;-ec}_KRXASrk(;g(n(Z
zDINh;LQ|TBCz_Ez3*C|Q$$r0IVg*oD!XqI2B_x^oOyfy(&XWF&`4Q66#viB@$+Kf1
zJti?{5s$9S`!Vs8-=+J2C?<}o-LUIWg`GH^&HV2g4&6HHia6?z-)0FlUPN&l@Gfk<
zC9@9kaU;)f-SR`UE~_tD50Qkz>;Q|EbA1J~12F$_V#j@h>oSSEEaQeA3v{QgFy`GMDN&M?zIlxAGeV-OcwdDR1rw5zk9hI7^*9L
zhzwO^V&Km%>(#;zOHxj3-Am&e4ldi83EOjh$kO2`en1{_w@O4l7{lewo%;>@>qvc2
zM3kt?_9o=hMC%@RC|)$yVPRGghw!q>npSQA{si!Ai@OG(sM5{2X_=dPNn6RR&01FD
zkkg(b4nWUkxQjr~O;o{G6ugF6!O2N0xdSs$F%u(qEd2+~47U&}G9mNLv76g|ID2g++3Y7Leg#|cB#2}i-Y6KYv?7qwjbcWQZpn^%*~7z!&G))Rj0#H1wXnp#AT
z2?}3zq;kGfv326qgeCT*J4n98+ym_$GyZa~U~v0xPz(_?W#F%CC64Y(5^fymhQ0W5
zk*&s3x$#X?lpTLn0MDSat&Gs`>24yMoPwrJ_Df_pCDwyKVMgc;LhabUjQDg-$)l)Kzjg;ehwqqZO~x`t_nk(!jl?~^__pXq~H1wff0Em3$N
z*{h+*yi?3qcFdK5l_$yU`gInUhsv^q)kJz=^aeVSZ@v+}QNq?u&>(;Y)j?J>mF`i7
zR@I$jo>RlCixVx!-=@ln&>`6x>i$mLd`lh7#17mVRF6wGpkBSy{Q!JId2|1Ovk(!2
zw0g6<2HGAeLb3Y+#5?W26q4O}+xE|X0Ocn!Nu;)c@`GF;gVfI2-n?rxc)>WKZyYp)
zTQVW2^>(yAw~}ytc;rZ^{Zk}4(rU5Tsm4I;nsrRBr`#WgWY~{0v#J*n`Gd~c*ph4y
zd}awYlAp299P7Tq$P#d)0SG5Y{jQZ$#yGUpRzmdpkbhKM8pwCEE69o?yXeR+1d_A!0T?EFE=Tfcw7|9lki
zz-c2nmHg>u9V4mR^A6fyn|3Jal+bjag<$%CW9o@VnjUK;ymO$0%~`<)^bh}$C^Y=`
z^!xunJF@x%y5B(ePtsKlu40~~zMXsYGFgc=@aW;HeaKJF72|*MU2lA8PcO|yNUC$R7;K&F3HI}6_XD%vqUv-PK>B!!&O
z*>@kjl+vJ`-UH9hWL5HdgA;UTw$E<_utkoIS_~Z*%l;cLpd@9zB#iSiw?^>5pii1{oTX;2Bq!2BaS
z%ctItynj^IWyE>L7_-jd_#n`zzk}#WOtua)HR5H8g|TByBQDd4x1n*hV_fs!`f{Wf
zrDN|{
z>-w>&;F?)`&cQTWJfb;qzOAiT3%%RT6K>~!`ZdkuS;yOC$<*&3R(J?+r4w!;hq<-z
zQ52(l;@qln;5)dqz|vp6j#;9Ni0~7(-JwD}1C^=_mD;DGS{{y*`;xE_8oU44e*_xx
z;k{SzCik~*zJ188YE)fqa9CN)MMsaPy?>}7*b`kjwWHJDzL5iWtGw{n*~{L?NmLsB
zm=;+>aOMo=1Kv_tCl_fgZBE3AR;rYg-*BoU=Cwp*LPY)Z2i7KL{{p!(VN0KX|JwIU
z6y~Ej?v+i^G1>1|J)yz-m%g^fNT+fd+F-#&T)?iPD~zFyS6sG>#aCdN=wT+FspLB1
z#tjU@)*|4|tn78nY-C?2ZN-^0)T^S`bCw5_GbJY}`FUI5`3(ZgtULs1^U8IaF{qSWIN6{U;*;w37
z0qsVH9WfdIr-*5Yqf5w&ChW8iuybuFWnLNa=R;P=wdS{B%jiWM6ZNANyE&Ld_BiBY
zPAj&AVvqsd8jWooZ$fP8=d?#7G$ch#qWJ6ddF@9mN9w@)Ds5cnQk*cL?zCbSD2nil
z+TqQVp{iT1J)OmAXvitAmGETl{7^n9{WSrSpt1*9e@4{Bho$QFTEsZTQ+^y{5P9C|
zEHSw}e8)JOoqrlS*fZs5cfQh&a<-Vxxmi|Qr60aegZaM+XJNdm6vzHO;9@z%)Fwbr
z4sHrEv(RfI-GC%}GrdzG@4!ygI|a5P%3#$+tsli%lR=#LIM`#kMml}3QMsVT4XGMB
z3P>l&_hjt-OlliDFEnqkj==9Yg0LgjmvS|xzi`@(NWr)9C8Gi?=&{GpgAE+^8zhxh
z&L-uQE#f-#z5kGF)8ATKWtT>(ZA4H_wQYw)x0E9Y%*x+}I@48h_NiPIzW@7A^ro_l
z3w^JYzHf4?Oe&mQLvw~P+|ut?x?n#-zY)tuC2t(X|M}4y26xP2*zjrB{J52lSGy1=
zfVg`^TiLB<#lXBRze}@`Pzuj6GYW>z(>)6(HU8*5Ic%3N4
zbgNsnj~k>F9jlQIYGhL~@D;QWH%^7FQ{mTk>ZzZquc`|f0MMftDH<>RPGG2Z?lNN4
zXxz88yrBybc_=v?EdcIGesHU}kp{jgdH)9*&6uY9j-l`O?z9Y%u-luZQ;~rp(7nS#
z{>}zxO(uOf8kv0wgJai6>7d7new}vxLk^5|{-XYU?b+d;w@SJ0Zt3~wy%JPye+BEx7T0SumC$v*
zwUf<$oLzz#+ZSH_Bs3STY=<%U5v|jYF;eAO;G^yIO$Z+qQ_tpk4p|2F;~cTApCAVS
z&1V9O_{{TE2aR_S?<|0<$iWK<8gbA+*kbLG_4EaFjU$4sKT$r*ZYhCR^5e>((_kxa
z8V^V)8h^mDF*_-nGKi&>5tgort#ib8;woWY(5=d4%lD&Kxq(ZU_RGDgQ6m2IeYq!C
zg$dLS;Wi1gq(9TX=4~nmJ>}1WC-7x=`p9L{m!DAlrSxPZo>!d$R%xBR%LN5@M(
zndyNyi=~pl!b5{ix0aLfSk^e=PO!sR7FdWMl!39z2U<+gTd(yzR7uI?DKW>9h)a-WBEO9QicF6v$A-
z_W^6Y
z*ZFQB{VnKt+f_LSL;dw%IJhSJq@`GbT;PvCQ(sw<4Uh+{hpe%PT|`~!zk=3OJ`({t
zx!rEn2Ic+l(i6Gvz@=sHLMHRiMhg{R^jjhil2k?h=1HeyO&7E>`lI~VTk~>piABcO
z$@SpZO!AD9bwbRw7gRWL>8EYmvhFTqZEWEf;(Hr$_NZZI
z2{^X5_K|!`9$UB7_uT)yK7-n%JcKirT49C2yi-<9
zFJHv%;S0;PCkX@W1pX`LXsna!2Q_NFt0M~xd_lUq%yaf?#l7Wpw|e55^3j*U`!M&z
z3R8d4Z*r{N@mZm<<7YlttTQs9N3$9kp~`O}50Dp&>SuMLMCJRQRpgPe_*dOS~{=N5XNLeJIoJV8~kq#|Cb4Y3Z$#u4A4LOa@mHRamQO0?=&Tm6|f)N-uV
zo~J@ihE661WAI<=uZYAO(xbds1UtN=6W&n%Yt0RXtMPVhe+BAKKkap|+N01~v4=Ky
zF>b2`k;thUX%1SKRJf59%of{5y-tYfD7UU$y`;jin4VA%VlETR%hq1IS)rszU&@9?
zp6O}!18eVdK2VbFIETEDD(3AD@bMAI5iIHG3-fHnen?XK)cQ8R6oK6TvhBK`iM85n
zK?a#QP>yyA?GuW|4SP!imaF`rJ4MR;2Cd{NY#*&=dh-lr{Wl;1eGiIx$!m=U4DiYI
zJZatZsj=32=j+P)woJDFWm?CMr-Oaf)@=k_3Wvht)y9c{}*nqNNumx
zF}v6-g`6KF3Fowq=#0<)1@dDAa_`?2d6}XkE>moE?zURh56-TohzFG$N|kW-5x2?;RS+#o$mU(`Unr)?;eSt-5m7~1(Qz2noD
zHNak~?Zrxy+<*5XV1%PD7R4;;Y>1@mu>{Xar;M9`^SP229%`}YY*I`;k$JCT6zL7!
zn{sdt@at~Dm%M{A;3&Qf>`TlZaoU~-|JAnS#LP^^D74~s`L5LLKsEtd)!qtM+m!^n
zb(7+2(}!jUUrrneBSSZ76`ubp73&e%q%kdvT3*2~m)
zsuTtlqZjx7g?T3T>CaW_DAd^Jsllza&($^|{jne%MFBZvEz~e!WYpqWehM;WCGJ~2?7F&!}m`9cB53-ek
zvd9H;3%6HVJ=N%|6X)kqKDJsdvlMW?pFtb!iym9N>W%}}%(9{)%%tX0MJCUT5=RBi
zswJ7@6r+%B-)<81$)3QztkLuiR;3-@6vZffzgdjiv{?aP
zVMYzQlfTE3p{`ZBtQWBY{Dk6{W$NI{yO^LtCKT`Y)LX}5teMGO+Om67+os7F#gq^{
zJ?8FHf9LMH$ZR@(bnzwidEdaS^B)X-Fsby9jJvOo7bDLzcRZ-F2$^N~?23eLg|~8I
z)D>pSWJ3Y3-*TL0c~?0<3mB5}*gr1L2s(z)le-Vfv+DWoFUspMbAr4M
z&G!Xr_Qk*hU%=nuKvBCnuz`sQq~|6Ea+eN6F764qUm2L6s|d`miG%-iWT3{hVsIVE
z`bBG@h?xS<$UyFyZC{&)SO|Y${iPM(Gwzw(H_k+c?ndJ7^yxZBWVYP?$PC<{BHN}s
z!ltprDY6z$p>7#*GLSHRJz*QS(E_Neb-T{{K|$yw2r5BX;;Mw3R2G>Fl}@>~Txjr=
z0oKZ_&E&g3Fbn5`3!p!0VDp;U+#GxMB510E%HgwxRDOcX<5OmW
zODc>5C&$s1Tg9Z}uBnp~f8MDS@9ad)n32*hX-0-$nsdQ*h@W6kr{*8EV}IwnF0>?2
zOOW-{y=u^K-k9p(sqSkPM7x3?4H(0Bw0ab^g7}15i=H&5c3+VDb&2D+y?LZyfOiF?
zO50AAyE7K@=`*;?7pxRZ%Cq^7awiSJb_7XIMKJJdmYCe9wFh1^&
z8LRq~JNf+eURv`q-#lSfe*(2>w>DE|Hfty6^h4fWBktt%GW^IVv{Qy^@-TpnR)Qm6
z4Y(q;&{S)#=c<&RREBn2;+)pd)$itSk3bZbq)t?#qe_1a#0FPp!?491D4SiL@TDj)}_ZR`h1-8
zEM&cW7w9{E2OJOtpR6I;9+ur`&)N4{kUP1HyL{GO>(Fe;KH!m|K+Rvnyai3yh-zuz
z6#;&n*UA2n#21qt*Y3N>8MJ`BG|-pQK91HhLpzdvvxG(aZmlkVLgb4`n->1oMBH=`^}of1i8N9S{1*
zmvG+SC`KhN@#+};BOfn3U)r+w*y0bLY<>C+qEL^yuf{VIn+)sj@)X7o46|pCi-3gj
zd7I9jJwvF(8RUJC1Dc|-e#}Yuk|zsxb8(y=WKb)noefCM5T5X$maVY#6u=~#dz749Pg@NwehaK4>a{;o;
zh8YK}?1eI9u!~78^g5>4XYST*JLj@KXtB2hg{v*>8KY1P+qmax@DS_AXhuxVnDxC$
zwbsxZjE-q>wS2$RcI~jPt`t(orh@N11tekn)IxJxk$laoT)wuQ^@kBR&=SYEJQqy+
zF(c=d((c)u$waB@yW$k?u55-d@U1hF0}Nl1XrT4I*p$G|D$%)1|KJfWo=-5)3br)W
z&=>W6DGGXTpM`#}7h})s>?nEIgWNs3Umg+@dURE<)s^n?vS)Y!ac-e;JpFC_e0m}zho0v^5!a^8Sp2^0RGsg)+ku@J!NM|eN)9fQTovlPQ+~zM
zwP8Pwix@D{9=vsDx~rTFAQ+HL6ikNXeaTn}(vNm`r()OWWLVC6PE6pi3b;=(>jv^3
zeE>3b+~7QURWdE>{qZ~<^$(>vlICjWUM3S`4W
z&oneEH0F%eyn^Nv-
z$g}55{GZQg7$RCAi0|FP!mp?gO)v
z9^3es^7mgqxNzEs(;k?9U^?Yo`f$d9*@+9D>3-oAyYH0XRxjmQ-!BBVX*lvu_F?CV
z>%Y^HBrOcRqBOkXWY+wLThMw8I;Y1Fnd5OsF7c4Rpy7|hA)Af%j1Xv_bQJMt_FFT!
z9>`oPKm~#mp!YuIvYI7|aO4B>9O{n#%mM8q@LsEe-jL1<@WKhXW>Ca1C0~7=aFQ!8
z8P9f0U)Ki<6t2A8iPR4DQa+(~SMhfdQYL8h){g!g#tns~dtHPuv`0z(d&BFp9+bYn
z@HcyHg#OYEf$Gc5On?0Y0dMSkr|D>=CVK2`dl4&9Dn%h4_SmK(a_DAn2}`%HB2Sn=
zx9K^1?X=L0@0f-iQ$H7bAE&L*O>M2R2yc-G%p>)o*M
z+H*zuteiCPRJIv=S$4H=2lhtS`MJ@xQ{|IQc=9nm+-j
zjcFCag~JJMl{H_ubT|RJx`+B#5*I!YYkR!+4q3;+Pxz|Bx#+aSi%*#59jO?lEpYG-
zyW8QIi+oUVq~XhGt5wz`*IMOq6@PhkeucbCP&4t}W&KjSsCS+{`|+rqYFD$rhU_b+
zB{_g_o84lLBK!u~yjy;1pT$Kv7dc)WUuL^<7<#2bBk2O%rKR%-cd^!S!q^TruSsjr
z6h*`zH{4-l*i=q4%_Nsn=U115`_n_aRi0R2Pz7&<_v?}h+ls$1I~Gj`Zfr{kakUF3
zw#+d(%ug^AHxpMrU@TmZ%t_3zPl()DRvdN>J_irA?ouk06VKrEEX6LaQYpsb4>1uK
z;Zo6n*ocIOjYPLZ-6ox(&B}PJ#2c3_1zv*>I!-=V0evHWiC4azn;{N{Bo399)-z+x
zCFbr!_Ec3QJK7StEv7wv6jjO|7K4nWH&du{e~g`7#Vu5TKPuLw#qI6AdDmGpya+Y)U4
zz9?t5t*q_m<=Hk@+s_?zJ&amVS?#{nOr_nnD)@kWu7GVR{8RCUq&ZNrxok@&v!j3{
z9GCTq#0i3G-l>KUBs6g-=P5cDb)|KEfzg+7wH?w(ZCCra>TKJKZ9g}_ued6^BfhPh#x$^MM7Fdy;%u+_
zh7FF%u~=^9_BqYum59p`F|#L+?8)x%wEZ_bvkY<9JWdg>dM!|ss8pSXR!qNTvN*IB
z+9ms}GKRPVaYWn3O_K>@iLq^)LRTZ&Hobyaaqv2^!Ob*xblveP|5>=rENLCH$ku=s
zsf6g@nZ!fkHj9x@Q88*_Rls!mQ+a)$0l=yZAPXvC6p=Vo%rnon`x&D
zzP&{%5MHqU7>YB=LgI_
z(@QgP*h6D5l=0uW9mekn_qYzJCJ2_UBEfpN$e|u#7mT$^(%qMXZiHcR{~`O7)ePY?
zw_{O$;Y#75gEj7`-W!7DV2$B#QyBNEzcB-G2F>4Yko7C^w`?BI2ou+jGW1<%=qwe(
zJ$En}D=#Q)oBRq#L4LU~^I!r&Ds;J1-px_0ER4Nc@$SiYbFxBL_U2^4%frv1%*ei1
z{Q3`hEjfkYnBgnSf>|D
zIdr{hB{LIn=bzSjc!#yv(s5^B&uI9xFv{3$oLgdj+dJC&y7ysgwfA<&!|r=QhCSNn
zmk$5Cx6tI4s*3=fSmR3#gdcYDG|z+hVGuWT9^T3SyFIUXdq)VyukNQ=gNAg<^#|oK
zT>s$ugGZ&&T>rognw0@>WT`)D>s-l(U~LLvFu9Hmw3p14O%w
zy~_KlG9`ZFpXxQ`cb60QQmO`aP&zC6E5u*)NO^}yV@ui5=ANOPXkq)`W33BMEqq_2q1=`QH6&^LNg9a!f;w)=@Md2m=aA~T02ro=+tHB<1yK?Bazzurm
z7I5vF8mxi5ppko1U-mB(?0c|ox{lynukXH%PIE~o6X6^p;a;5U_0HORZ2uW#;L9Qy
z_@z9~$Yn^TRQREtiR{t2R}W*VkK<&h*9-$|7%^dm)~1Y9631b$_0L}no1{IjNjI?y
zzL`2PZnqBd1y5h4G1r1((h9A6wT`PkZi|m(TyNhy${oDQobK2a$>{>^(Z~K#y14Z3
zlo8q#b&AFJZhpSj_KhE_>I{7}sFb+N+P+d7Q!)*QDFUb2{1=w!in?5t;2W`jXsL
zC5$AaN;=o}g|?O|Bb#&Mz5r5u$%l%QzE
zUA2)DY#;ELhl7&*Wb5o=RG5t`I>Tz6;@)oztEcKZjQl?h&#h%_k;ue^ehkXXOR4>P
z`VV!S<>48M8faEK{S0)=G@t$bOu5zY+`Wv=(NF%LFZXk>h2HTkcXM^id{|vqPOwI}
z_uh1AjOzGX>NlbOeRt70QeM#3w6#-91w=ugsS2du??V(%d+RS}f_nrW*v^0M=D(FP
zCaA0(PXs@Ap}vk1?dMb{MG%H1{Q0PHLy8^HMRFloRyXo4U#cX*xsC5L^;i2DcjgG@
z9lqY*FJ%?Q2ve#2MqX%5O^iKa=dUU=ur?jJZC~6z8?97#>g}s>Rat&ShIIZuvRQ09
zPC96uwO$fvulSi+*^y1r@ki0#3U;JfPgkZDf~6YRuyHxj6CttPrsTqM%zNlMdFTK
z%OHbV)Znh_#(cJ~rkb0BSWi9V4-LseYvSyvE2FH(w6enXALKthBU%gGo*YduSZK_^
z34o*v>y@a6Juf+mo!z7rhjYm5*Ar#aX?1EXG}HQl=iHo$EzVI)9~j{k7>(*d_>I_%
z(^$q3aq1=eFG?b@+R!?DXQ~f+p{4$p#@3jsO)(!fZ8ocOzMg%%7X1;&!p9asYqb5M
zqJs*Irb14ioKoGBMQb56{bW<%6*&|KpjY2YYM
zvt{yipZN3Lkz!q@YWD}X>j-{m@z6H2;E|r`o^+0^(Q;;K$`nRt9?8&ey+Uw)!HRQI
zl#;zgFpdXosMQ76I*2ai2Uu&9V8QyhlP6B0KA5R+z0FUkw6as<5UGHiAY@e<*`z6%T)uAqP{53SAoik!9
zTaJiyv&ORmTuf8bxpMB>miIQznL>VLpdOMx+w~?fKD*cI^!5Hc
z1@(Gh#_L!|$(j}uRMJQnn$K|qv0s~HpSjNRsSX(*Ccd`NOrA&bb2;n%Gu;i_Y3*c-
zB&}X}?aEF_l+8$#E%g)Qy;wJ`^T9BE^G~013Ni2CPsRyE%WhpWqHAeuWsQ*kF556Z
z0h%BMcwcR?nO4(P3*A2`lI;=?3C5U8tLxxkpT+b3bq-a3Iie0U?5JiQ_zKqPkz8Ti
zwe=bN29ucd5fkaUR!w{EovO>L$ME?T(;CI$SD5GXlN=vU9)1Gw{xd{!{Y*8Soti9^
zFM=HGaT|v*hW=pmeyb}M_GnNLuTC*)Y<8B4B=n2mT2BAfxd^xe+4NQUu2`I|i893d
zFS}XdjkgUXk?~(BNme(M?wLyvW^gnwbY=T$#8=zYuI$>Hfz|G^;0r`q2G$b<^F^Pm
zr#siI+634>Aq%VW-Co#EP!^tkcvHL;CGgf=HZtFJm_x~60_>gOH<8&t|7ekGhBtvq
zQ(4$&g5la^Ys+Gf&`P!ySY29SOR@RDwg>r56;1OOo=WNJS1~kgU1Nm`M9=P%G=jl
z?^ZLZ9Uu0!yW#CXP%$tx3>DbD^+expwF=dMx|vuvaso(pq4xRU+MA+xVXv|md<=Ml
zqH|MeB?GPcKY1h$jUNH{m9Ksa{!F?`9XGsH_7xy+a&Zh7Mfz}pXM$LQGYZQ%vb#x70F5--Q-r!^MFFZhqkzaJQCoItcRVyIgO3XoT#VDUwg
zgRI&0{sL+L+tCh5Snqf`D+vA<{2>QesYyHfIP!s~m^Es?s-m+3Spt+vGY;f#oS~de
z9z+j3c;LaLX&a|0r$6NQI>&-B{pwRYXur$Tro1Lm{VFdzeYe6sZ8$O+mG6smF5dQJ
zm93}lCM_a5l;oJxNWG%|5H1QZ#WvMddXllGpSip`V+nZm;mL~Iy_W{twvhCXRs!iy
z)kQkL0LA-Z3x+Z)v#8?HMxuO#J36JleR9MW4gYCLuaNS--8xgy%9@2JoKmf}ZRT}$
zGu0Zo$CF7Ka3k~HrbuVXZS<7-A4vad=c6Vs^f30l)+l$L5n8-D&o-Bnf7|7PZ;w2>
zBnPMk`Go7`F=owFd_}96SQBIISmzJrq?I%o5*{Y_p-6;?DKg}se*HPsfN`K)f}Pjp
zr*s|g1zH<+QD1Q$TKX@y%Dv6(9qjD^OPKysf2roduWz&w{S9;n4&VO#S09D-^2R(s
zDDVFRFo;S>()MH*V>9x~BuA3@fGJA>8eUSF-Jykk#FS(v4MCv0V*lXV
z=)cK5+&Fu0GkGGx3(49E%Tu*a>W^OW8|YGWi0lxyfy$c&r&XE}L~n<`
zeC99H(2m^l_TF%tq?aI_1Z8gbpy$x*%om!xW}B89f;j@oVDyHv;0@=xIi~WL>NfSS
zs|N=w^T1elI-`6>P!E(sve;)6TL6cQ2)#?n3DUM8mM34Uybe-^mxB^bynh!2=
zF5Qot<~p2WCh9<~IgY24N<2#Iq`&NRkR3Lq6jUB3Ucl
zpQ3qUmOVrBFay=flelcMiK2cAC<;
zwlDmUZ^@bmPC4lNfi;gjW^UopTDMowdYtpqdRzhr*(4mr{}mA@{Uj@swQo=k=DXc~
z_(DJqrf(eZH##VkOKVt#%m(2#bacpH$`bUT@3y3K#kY{kAb}5Z#$-7Q+r-W%lzXA)
zaQm;{GYvYIr5*qD_t~>|3q%KS>Qsgu`*+*=^0nG*qly70U33ny-7IR1?$H&)hguQy
zNE1O&+S+>c-zD8I<=vIfdYg63ptdfQ_l0katEr{NpiW&Vw6xT`>2#|K778a1*ASgK
z#<^9nq>hKT5uciGS?_AXbNDijns$sM9pyWlz+*mSpSoKBwbU4%?Vp6au}r;ce3t9b
z$UhdJbXC30c_A$g#Mk%Vtso5;o0C)Nj)VS3%cR2R&y=CnW>v1s#BMyZ3G{h9w0NVn
z;M{DFBG%Ixm+Ii;`+D^TQ~6qh+QbStV_Zzxqya6^!nawMeo7pAg|R)q7uK?a3dQ>d
zH4~qa*~Mr{!^J@U)z~({t0`hLXSd7{5VPXx&pxr|@w+iGMfCo*uJ@8B_@Jg*kOGTy%d57DV
z8>-_OL^&W&;(qwEt2_euVvHs_Q{sz{s)$E?q$-e*zt-mFhDrOmq*{VU$>Q*SPYvxL
z;l8z_+=q?OIh@zo+5abAA8zTjKNmDiQvvR;*}B;hAlB~Fw)LfJMS@8(~hE41|_82BYWi5cMal1aFr
z{4C-N@&)QW`VG(Zf5G#fqc3lH7NmFdjC4_f)|v;!B-p$F8DakOXc8;&pUl*dR&eD_
z{KbANFO{|#0X^>q&H{q0+jH_R8nwdwmlJtU=%onQU
zmBfxxU%R=Er@zA5NW5&h_m@Xynw@gYZr-DSzBA#-M!DtSQ-gfRtz1WvBhanSRvjfO
zUN{RjST@i-?;_n14X1oo;2w(x?fbHQ;a2NHr4>GIOkXY}vkspcln?*i$X5~KPc92N
zLBvo(=I-9`JZqgTU{?;o9<$~MS~K~9+BTJOg|jYMQc$Ad4F0#zJBa^{lg`APCh8}j
z^+bAf(7(opCS;FR^xbl9jQj>%P3zfp_Oz4H@_7AoaZ)TJCcVxe`yV`fzCfHz+FDz=
zpX+d!eJ9m_0w*^;U&?e414MF`J+oBF_eAF6lX_hB#q_Lgyn(88;7V?LsYRsuW^20d>Z^-
z)SKgssL`Mvf44nnw15+uG%NB+FW~0WpcnY6qE!3wF^WWnoauyD3|b{w+pSLZfMfBn
zQ?4@$mb-kH!n+98VOQIw1b9)rgcu>oE(ss37VI*}i1mGOumCS+B)RnB)r9Bs$wFp$
zX))}Q+zxo9hwNg(ik&=J#=v6aMS(vn%_mDGn>Pm6dqdX`;kre-wp-(%Sx__djiIb7
zU-H4Qj>of<&@=U1dd6C_@lDFy!c~zj?9U!)KcZgLvykkfVJ}1#c_HFCJzIkq04lev
zLK}K&C{s&*2!u!KgGQ397+H$Fl7QA1hOPB-+#t2LR(qX
z;mm#$HnKKm!D`ZcA*%_VeLR`+o5a@y8XGpyPV829Fsf6?#2DJ~lRSXf_J*TR?U#Ah
zD@vJPEr14u?8oF}mYl(I(Uw?JBLe>-4mt|)4RupH)w+z6)ro{$tkG<*%@K-DAGA-e$
z40$;LN2U(M*`^~R15d!GkB3fbIv=vRgLWZ4!!@%Ba|&8^5q_Jqt|Zh$-(2nzhhAb9
z9T|+t=&g9F!B7UyCls%dPkAW18~+5mz+rj*IuE;hdZUdqurIkQ8wJZI;JZNgzF*SS
zk1$yGjXkn8O3u3YNE7g(rcaOaw@`-JHmCAM$KtyF^e2H-wp-}eTTlsN`|
zoq&@^IwG~-$ryHN3Jbi7Z-)mZ&4#SkkRxlKX+QgqK;!mzSl|?#U$oX{!2FZ-Np(a^>0U$++lu_0Z9z~8ZUAxofTYhzTD`r6?b|5+)!*~u
zH*ftnee=Sn1ZQuZZ1&RK_J4%S5xz~D`XM|9o@t-=ximgAWW*BgKZWKJX*OH$petEE
zmfNJVpH_uyNSYcRWkn;|Xx?umsYv#qywx^Si5%00e$2GcH_qmlW*c${W-PkzfkD21
z;bXU3FGvo+-0Ss8?>AJxb0^ee|rJc;8mRUx0b$&e(@sduv;rU
z_UV$Wxpe^EX`3Q!uktC<{w=#YxT4aI4NkDR_#u1gtM0eFySUxZvR@G{_(+$eIu4#l
z6W&|j!rvU%8uI0Zzxk(rHF4>H(Jjc1McfbM3M%``>~g6#_oGX*Fip@fAupr
z@FTo$fgkm$nZS>r&&hCZBr|D!_ub6F(Lv=%bTYqK)$uYo`6?#TXn(Z#8&
z5v>MK(g=rINP{ow^QS1X0N&EOI4)vkJ^9>vtfbv3c!0D!9XtmO-g#kgXTYcMgse9r
zE|As+IUKv&AG1SlLxxU|@8%8(yfHPjLS#++;TqBUoUJ4%M)u*RKx6b*bxwJu6J}9e
zZ%FWVsAG=FwgIOu0djUgC(tCkE@=?<`=N7E1oWS@%aGLe*B^7or0JCPptorVyAuqG
zPSOybe2?Js?S?asMSuN&fTY%W!NhFDNn1c6RL$wn=(nAg&rU90ll2_Y0a+4M<#?uI
z?$*|gfu4BOKz!jap()KWx{)Ba{5ayerjsp9tm}dQC0$#kYjz}T^o{!zB#l5X-l)fw
zWIbUK!4jBHQ^MYcv828@Syg;Y*J*
znfY{_b+r}|8+v4^cLf^f|52EkY=O`E7)gqRRtUK4ykJhY5FM{u3n<7psHrqgS3TKN
z6VQ)%PnMOeJHxgn>v_mZl2=8++rtq9NK%r2C+%a}T@>#p>+c8UM^T$B?9!T{+k%9Y
z06SSyp2A^uz3m)jGkyykB{0K*(H>-m`|NQpMjUZoGshRA?BpLqQr7VEnhB@ElIhhv
zoGcA1sVuFgOVa2-9;8rJ2}csRcqiI{>=)R#FA}yZRbXFwWQaSODBw}$(MF>9Wc-}2pZJP7n$fSk+Ozb+Fz7f`ZxZj^59PM~YP5xJU&gZ+D&(|0+SFE+Rf=){waMtngpTFD4?NtexshZOjN#L#*tOia&
zhJNB8NfI!qAO%EOJ?`iNk0H9uLosv6ehIk%ehPy7SS)PMy^zR*(e-5okOIP%sa4nO
z7ylhGLA8hylAm4PTHiGu5nJ@cw?mc{)VN2~N^1~*{zQ9rvf$eIq4GefYxBYc=ZoY?
zD$5c61l!9O1e!rZnSZ{}dIh{Jzd-&?4gFd}zXhS+ve0jB=+_te^-I6N!V85~_(nnw
zrmQG@kz}{G?gr;FL-8ixUs3NjBC@v$UJexLZPtYC&ZK7=e&Uus=y#f5E`w@rGe&Z9ORojnK>)}?z?GfG!(Z}xY
zEQvmv&kL1TWDLltFL|AkCUZ^0@>F?ja!>fHoC`yZ0$)AGTRR>LUN5#FV{3c*
zGWvSW&#D9B&fh3#O(q4lNj@lQzPf_GAWscD^pF{-A!9Xa_|uo)Q@Iz86e9z-oI8O|
zL8j~pVH=`Yq+)KLZR=Tr5*yF`VyDY>^1mKBu=dT8w6%%{3+LFXw7_d--P>Q%iecV!
zlV*^uPd*DUY;m(-4(xx{GPcdgR8yP7*ow>8hv5H+G3+av#$IqTe|H9!DpYnK$H0pc
znLQtJbvb8xK|gdhUX^UyrW^Vw#UjQBhf-@FO&-YW&;*f5Fj=4ovrLlx5kE(JhsArc
z5U*Koe-s`p&>IMGUnC?x?RI2)+!Rk2iluX3zdlJZW$bTNmJw{>&oBQ8vLfP-{H*J^
zx5jlcxWoNT24g7u<_2(FG|7gxCp$G%H~Ed*u3Xh*du->f-V$F|AVt&JT)UW`jJlBzd~cKljYwoPt*WAd(JI0HKIY)s$N!
z^lpvUv_d;0$81vMQsi0#-zU!rd>Cv`ey*`U>R@bLv06574`K&{lQ1uzcB%!$T=uWr
z28_>7cuI;kvI%MhJ*6k%=tJ0>V5j@P8^cMXl*b-3e{k&Z6_KJfJ3P9N3;(K`5`P4k
z=C41s1HMU?@q%#*_zTTz+XeG$=CL_8fg1wJ08!+mOQZ-+N%BArO-Unu2P~&36wj6G%ASM?pg&p=1X8NS{S#wOwx%V1BDd*
zDp~WO^|~g-j8O|ejwL4!ve*xs4rDww$1K=5Eu+Xe^4d-Oveo}R;g{Yv*Ms+10{a?{
zXCfkxFihbvU>l7S_`<44b9Hom`yFu1?}FdSIHo&|YUm$EIOY!u@;kio+9EI6#bq1=
zPVXj;DFBYKDmuRY;(IFhtKjktTnHl!;)AIUGTnVuoQN8^d>
z@X?^mQ?`H~=kczH6!nisi!n2zMZ>sgF(Nsd^e~gIgZssNDy9&9{V{cUz(KGiM=6B4
zguy5qhL~^iOp8
zyykCGuq(ikJI_Kpp|Q8sYL{qGGGU+Uvc24N`w2?@7m5``$7Q
zySY{?MGo_=rbyQThby)=!EhngWcyHsoPi@B(l#6TgoiRzwI=appGJJG4f|Y^PSzLT
zO<2)8a&hj8s&oJ4+i>Si&R*&*KaMzL=PCB}rf7IhGsrEv@0lxN^6NO;O??|b3Rn{d)wF$g8g^=iPTqaeeFjPeDBK9%0xr%K2;-pja8^xiPg
zA5Ju-NJSyjmo8-dZJhi1D8}&Y6edc&5s`eu*yX>vwI8X8!WnS5swmFgw#VdpbI$}}
zk7L47m;3uDWx1pN^CysFv)
zQdmwm5CjjdKv@jcwg0$5n*B~`pNo6F8u1lC-ZuR0_G-Yrz$yV>PRbWGvl%>!Un9)w
zOi)>OmH0_k!wx_u8cXMG@JO`$CQRN(+N1Y%E?=Gb-0`}S@g={8z9z8mw|{jtZ8gif
zr7tvW3nGe)Lm75=lcth%z3{y+hThiby>SDwbME!?8D+JmcU!$Teep+>uPo2tYfQE|
zJ_hi8*zVIYbslJa^-=_CYlb!1OZc{r^2-_36+NJ{~dN`D@5Pb!FPK!0r~Cp-m0`R?R|p;#M`Wfqics_CTX%Z{G8-
zQm%ZR9UdEAa4Q4G@^u62%;&{BI3>=eM7&PwDq9@)fi_sH(@3hFiWw7dfIO@8bZbI!}X_C2ZXlKae$llwfrCD58HBAXR_
zKB(8f{3ke3^g2wP9>@vn2lkuk)KfL03R8}SdF>E>{ha1kd%}+SRas#VXW;X)-p@!}
zB;a==Xc*C5c|N}K4$k)3?c|+txxt8a0*$&dXEOMw4`^4g7Yb~y%+7nXmJ#K&7lu!E
zo~7sZwt{?@*MCp3->_&TaJFF)WwE@S&+>mtJ452cn)5Ic(ns80!uJW4s6M{yMQ`Z+
z;5^@=X_4{i|Dw^|f5Pq?$&9p)apLUJr(v-w<>AxA>8rmiwu}W=-ku;P?ADJ3KNVoU
z>Y+E~K9yB;5dVpoR?_+~Pkj{snq*nn61Gfer4n{<7E}+kAgvpoA#UN*uZV}a@zw3n
z{$pHkJ$G}Yj$jB+)7jMzU6get3s1@VlSj_K=aSbd^$by$v~_Pff9*PqOuJ!i3T61J
z3=lWSr~><#q2kWndQq+7==m;W{<4*5af-KOVHqCO1#0H~E3M=+#}wosx#1jQk@rYa
zRbjb15BYaIFDve^$XH##POO&S(7w;$ubK>TMy6i9*EF!+)^~x4DK9LKIr^A~+Hm6x
zhFzrvD!TsYxWel4T`gkw;`v3Rsg!s3%~H98wcp;i`9g)L?n7i_hu-@=mBk$I&Qs78
zJjc1PE@#lcLn&pNAze4K_P-s{QoXc7_F5}q+i|AV8Me8N`*`xiDtTTC
z%Vp?fn|<6XlfUv3ghQrzPIU9DVyxoJ{uScO{3`Jk{CW6i#Vz=&#@|-_y^OzC@V5g*|yQX|Lq@o->YvFG{lcEz+zIrv}ch0iMYwF)sKVa*u6IyqV`t+|aj`
zAaJQJ{_-vr$Au}6?ENFx(^SXe3@32@BZABX6MMnR1ad3$Afw+bja+1G@4p7ERk=$6
zO%Zb*wYQbYCv)v%qUSs+$@#gJ3&b=|NjNU$eGmHSE@|4GbgIZiK8#a=O-hs=EwVK@
zN2iW6A!EC$hpQ}*w5>jP;6OI%KW6tWmV6uJd~V{9;8uHEHbWjI;!wJ7c`iI=`V}|#
zJ!jA3w+{Mfih7j7c`b!`@TgQiZ=zUp_;6cGI4O1wZP1LE*2H&0n&EmlnwMX`_AD}g
z+H^r>cm|eP*_;y2e)1AxjX5sBywMoxe5iWr?cU?uZf=69x?|3xl^+ap{j{U!JbL;|
z;9g~*X1)P-k0D`w%#u%=vt7`+*uLpvnyphl5=UG?#%l+o%0~Q((mrbsypLSSEoQUB
z4>H@}$&}(N9+|FZ{z|sOUHRqF{3+b{|Gn3q~m7O{s2$FXe%;CEDu
z2~zSU?e9WDT6(^+BK!O5q)Ar&rXeXI4;t
zofK|ng;?cVMPGa$(+(y4v29aDV?AfUbyTz#3sXo14
z+)npa+-J)78`@T});tB}tbxxNq<67W8tKZ=7||2fHx#|(m?Y#wfyQbT=q&D&<$Dj^
z&%nJ|zTZOkD{%j~d|yrXn{Zzu-4kxZ%x(3rBI_LNky?x1r`~E!W&iae9`oMCtG`nH-y(aN3_M}X#v(LQ94~!
z$6v}^gS3a<;>SPJeW%?x
z5^y?lWM=$Hnz=wtZiMu)_{%Yl@i^NCo~%s=
zvXioho5ouHGFclCYf@Fa*0(9UkAM7og~jPlLy7IKB*=8!O}!G)ms>T2WFrg95e}=N
z4L%$ZL1yd^EI<}~1&i6F&hv6F9=~h2>9F(H4yPaIpLfrD_ke{l&3ROe8podYPcVJb
zVX?Zr+yvWl59pNrBGDya%$t-+9I;6`?IX6$!65615)=v43)wY6FGSUO?%@ie7`M`_
z|4S6BvAa;!OZ1wkg~}^Y*bVw&3QJ5#G9Q#;WXR=4#GJavq&N#dA-`_#^D{;R_zK^H-D%?8|fk|J`ZttxShXq%W
z6#rroaXxI@VhM9CdpQRfv}=_e_c|5r>aSiti6?z1ORammzHf8$eo(UUFV$@}sQu55
zC>MNvMJ`KkQ4&v?=2GwJ*y8)1APBLGX@EzaPDuICo~&cY{z%rxLEGb&8Rt#*3(2e(
z(sBl}%u+Tw$_s7S63f{7PB0mzU8chIS^vyLwBiGv!l7%{X-{UT4uvS3Fm$)FaGe}Q
z;*m5Cb*w>P9`^{~|6F&K86vu)+1E>y_O{1aI!iJ`o19h3XRNtbQC(qsqMxHaZIiNt
zkcU*!(m+k)<2Y^8(Zhmvb$?f6_nl_}c`PChYnTFdBu>z(Y5bkE58vd!>#t#(uCU`b
zJ+P^8-5cIO_lWiIQ({T#wEwwDSqJN4Dw}bsfJH2Tg1uD23h{`xOI+E;Au@%X#A9!!e
z^Db*~S#VuZbiozFL=ic;GL0*)?g}(uK{K%f(Xzr&H!EAb@?$YxDjx|ytBn?JD5Gi|n}#ck&BX1eVBF?BGiq&5sMv
zlSjac_}XxKdTHaO4Pwzb=5(95^_;4xtp*f;OcQMYH=`P5^cGHk-#Mt8TXj&Oooeo-
z67W#Si+7SuHb8^=voB#~B;VPMT4*i{)|t1x9faISP6vD#v{UX)r0h2EJ}q2y;BMnR
zN1d8vmi&h3+-2k3>F-Qf7lka{qj+!E)6ImlDdNxUJW;sHSR>WkW2t+Jos}+~)2&1q
z7DrzN*K{9SE(~JC5ecl0Pe3Hu4;v6&qby@QXZ$F=^f6`altc~dXHtrY%2_Jw$gX|E}9HQGmpc%4K%m6YrW6&T>9v=?^nG0H0;_`
zp!GfXB2t=4Ea(P3s%Fv+;#RdP%5=IFd>@0H@PK<_$yrtOEZK`~8~C_111r8l{M-^2
zU*WofEtjuL7;z&a3vEC)G_s8=6-&YGb$$5yc;bBZF;6M&t(>5(iBvn@jt|kmR85+3odeGNGw~94H{S`a1u4N2(
z?!uG|d8Z?tv(H`&KH-}UN?ry?ctd+s2W!nN`4I1d2XS5_#WHd!krVFh$0ED)6rOzh
zO`cql0G++~bC@K104AyXb*cW$5$;qaW1W9iRe-&ll?ea8>DA4XSur9OtAcm}ZdaQM
z(LT?eonm?t824#e!xzaTLIOW#d6)fyS9|if=sUzyk(_W>{*N1W4hJ-9s`SkL+;Lhy|zXO
zV|EJD8bMnD5)1liO*Il@nRb|!awKIm{E(8L9?f6k*@2^p4+*KgJHJi#9fs6x7;#5u
zpCPFm$=v)ly6Nc!A4E%4W0KKvqR3Cx!to+?plR1Xl(18-%P
zI}!y<@@;;I{gZ9;KxHYBD9HNyo!U{i`ZRVuZR@8d?m6@G)CAEIJHG9=TmTKh_o~g`
z$kYS=M@A60*YH?Kg916TPKzNuO!^F)G5r*>)GqJmO{aeax*<4_2Ub=?{pec#^KFEO
z>YgnH$63jGJ4(L?;Q`*k)qbBW;~`3?RBv7ZJ2_B}VnHR7StHNWULi%6i2Y6Yhaw4%
z#0rCtd?@aaTCZu`-b8P$mH9RHBeD!u|8THezFc_wbh>|)!-Ik_^DU#~8q0(^{aiXp
zY8C%t+9|&N&Mwt&3czc$4zvaeZqoy|B@S6z2ha7wA(y%Nu}rR>POB%eTDro7EUU8X
zGIGZkbSt9rN5{4pycsu^pp}-9HxtrMUpMLBY@AhLqXik{wQ^_3V9ZdUxaG|Rg
z__6VY543N`1&!7uO^IPA1j9N|MbMV$X^OFR8nR_IBjyoajAcX@U6(N8R=VzH#1gvZ
z!frWv)Rm2=>rS7<-eqL`hI1Y)(FrE05y^}m_Q{MOjW0zk0v`CH6z~9NTE<#iJ$XcF
z!N=}ZpX?~lCp*GbmL27h?1(dw?C3bjj&LvGo@7V3FKk~+vZFKPt*A(j)cUZCEO0|g
z(eGiQuj#vy)Yr&t{j})!$nn7;KE37ChN4fm{+_hV&u`p{UptpBhxG&fBFW_Qh@?$-
z9AJH`{z)c1&1NVD{dEO#wj-ZTdK)oHO^8C}YSdFKcUiwu+WVApLZv%^)$doZIWQQa
zpg_w0fXpL)WR)tFxbqaj7IJn4CRRE`L;^X09L3-X>k{u0LyBaMP>DxEb1@^FcnYG8
zV^V0vyoHu$6-c&(BiO_|1{;I1khZ`oS@XNaN<8?#_C7+;HG=rPmKZhZt!TYx*ZJ1?
z#$&1QgI8Tk!+}R`g8Ce@&=TEj=~534T7@!6U#+
z9BdSWKuL3_j$qE~!d{|23~ax@*WSVmv$rF<4D>Gt=)#GiYQ%G`UfH91*EJ&bO+krD
zLB0a%b=T6;Tcca8_0*FeN<-{bMX&ALjPUZ#ZJ5ZD{tW&Tdli;5#Q}#Q?Su%x#NU6gdY|;9(#Q7
z_y?`C5x*6=8FkuN=jK7$=BIXgEnmReZ8v&Mk$$m4L!B#EF=nSQ)G5?E9Y?N~S=~jP
z|Cy@&pZ^)_)M&w_QjL~r+NqGJ
zfWM`hi`mEXzAXMN@9p^Zl-KfdE&T5#r)CAC3xcFRPqxWTWd5RPKcr`^C*q%dQ<^DD
z%C^Kjd>r)N%6;`z2AI}*DF8W3@jGY<8k9b7pBX=3tpD+9J
z5#i(C}>og1~hXgxLL&s~MDbUE%0{xWCZDjoo
zUSRSFC4&e}F2P!ByJsGthAO=Yayw=`s3$dtNFgdjGH1kKT-$RQSeN2zU=SCSl)^>(
zu>2;^Q=D7PP7{dF@NvygE?zmmfb0*&&6Ox!#7&Unsz87C6sU)1myyQoDbN&8f~I&9
z7K&luN}huCJ-g|c54t@{dy?Q3t}*cb|7&k5?O{+7RKruE3x8YjSAxH7_$$R9^hW*I
zzqV4r{``A>p7XzcOMQ87823yxgdgP$6$-z}62CdI4E*N)mT90JcK9UkGM7m^MsB?{
z|0!Sp^pk~-8%qCT81%2KR}U-{(xZ9?a{iG<8GF>Vj8yiPx(wLElDOhcJ>d?;vhHE<
z0>BY6)(w7Dmel~`#2wZnS1*K!oA!S`%zxqG>dG0S;5qyqXfJKce
z5Ox#Bqn?r_G$1L{ds~9t{I$$e;JP7V3cIN*sq)5tfGB?fxOsJ>_E%_b{!8qbbM
z^+71auc3(86dTo};!c>Dq{*O2BuEe=&+E6&OmBic2G^%b)jK02naLU^sMu$N2(5fp
zFQS$UOt|noY0-fxT
zACdTcqxaUutjd8TjA%x~UldrFJ!}AW?wbDT{02pK9`}h-a`&I2Q-ibe1oK%$brt$<
z*o4I^ZC0NTC7q>Vec1}k5;{OjDLH+bATw8JsaZr@`RS?M1L-Llz6pIqPrc)#r($j^
z7yR^;Vto+49FP*!)F4~l7cK#?_ch^Jtogdhh~c@;M(^N3{D!yX#qX}Cgag`!FVFiT
zk|#cve+F?xEQvGZuXYMg`|AO`&AavM(yx`T{S<~W_OnmI*BHCC*bCgh^+$H|xfF?7
zC)9D~g*az6I`tVZ8?a8wz9woXV@5y!DbvTnL?16R%O_Qi{?|{5n70UV3F~B;D(AKA
zk59-2wGj(!TnMQumji!5mlpfY@xY?dHtxvnh;23Xs&D4&{CFe(tb#Wn^ZtT!Lz90P
z-gvTI!&&g9->w0DwygvltPtkBdX=mG8uIJtRKyNLRLw~lEb>L;BqT5*l2zXvgIa0iZX8|VHt6n`hk
zO*~gF^r$jx6^l<~^@S{jQMnpO=2@|2kd1i9(Wf72^|qYeZdD;$t1i$nVy`s^LrFO0&z<>toGvN
z9XdId9lHU$l%7N)i>lKT4}C-THmA_=hPb19n^>sEPHo+0O6r@DsCRL)YR
zEoYXsaURFcQqGi=%bR@XDOblEU-!nO`~{p_HnsoRE65(ph`R3Vov?u(U7wIU!A22~
zY1B?z!yB;cXer%BP}1toj{3!k7T77C20d|s`m#3kgf$nyk8vS+
z3D8p=GDT=x=<0_5yF2EB5p60pv}vdYU(Ip&Ey=&R#f{k^TF&E#JehnM
zwtd=@d(amRvS}jfU`u1nzAg4OexHAuBd5lV{(xerW{gWQ$JfyK#kRWmzIY+L0)dO6+g>GrXb^hj@S#6|Gu#@9yQ?xg>8w
zl%@H`z{narc(p~nuw$?c**&Wc+^;(47%!REdIm_oiA&;=5r3rR^j3sq246S%`DrB~
z_JLNYwDaNllt)tV^d?Y4WrYv?wmIB5qc-xCisH3rTTur$y9D*5L(=?l$=reVg!qoW
zN}M$cI@V=ud9GT`C9gtElbigN1+cQEv@pb;P(r+o5C*Lb=a1`LnvRImU3VOtUnAnn
zoSK2Yc#03HO#j|%{>n}I0{oAZ@%`SjR!GBk*4ZdxURmO5-)te?3)iqh?akiNf;c7F
zcQg&0JM!U_=kH5U#)A>z&!>A0)D?Iw8)5HJq;9ICK5_Lc)CHK|&R0A?5QV`ttVHd#
zhs_)x=fgwy6P8ut`cdq%0tciMvEJ-Obs=SRzA57<_(eWP_E&J`Q-rf_Il>uo5*Z6>
zD6*teSSCM>{1mgU{q=mJ%gq)cS~utdo*R%Ow0)9!t#F%j5HgBOsXL>jYYuav=Qf2J
zh4xCly1*(qSZnetY}0At-|e7C+zqEO_a9ych2oogMD61!6VB;$v6Q?IOPgTfIUdpO
zhf%FM!H!re$qNa>#>u{C!3*gbG8nQtVcbHeX4!%Q2jLtgE?#R{U|hUb
zMBHmFv$~hak!Ks_
zD1P;bw0|v<-mczg%L2EJ@93#Li=I8RQF%ghqF|e5pI2ilGQQGkAZp($^xu(Y7zL{y
zIXWIP@ZcId3YG-9-RcF^R_PBcXZQ>0*BO#{Kl>zBdi*E9
zRC8CzgFS(8#D5m1yA;Yi_YIkUDa)QkIg2RIgAxPHUv9@+h&35anZJmNZ~;oej`B4N
z_-!UEI^BE`mhv+OKejqD{iLI~2JveLpN<0co;c2GS|Q^(g3i@>y`b(rPf!fSkXik4
zttqB;k>2Xw!*dNUs5f=8v#jndYU^K3OvMK>Y#Zv5WjOioPis6qQ&jI%CA3UyIz3y?
zc8X|Jdsvw#qKu{_RhHqM6h~apUc}r%glYVOjW_(c^vR;SNVddQB6^&D+}dVRZ(UfO
ze;Kmuw5O9!)TpZSd-O>{O6uluvc(bTZh@sFUX&dWj9onOsj948w_
zIfJao0vj<($C(kuC$p?3h`oGm1nob{0;kK85Qic&2D1waUPu}I`|6$ucq~SL8vT2C
z&(x6@*MbdUxSOnDx{%*uBd%e`@&43%H~RtWKb>ajqLT}0G>F*~<8U_s@{reu(1ktT
z-XP~-_3?nP1W;(xa~pipx$MFxAe{ph1AXgyMLOr_<{%-Fv19D|XgxUl5sE~vj`wD#
zJRDR9=r{t<_gzMx02;K8S1co+-mR=+{3btdC4CCsO5WL?VA|P!zDn8E@gpB=BH0nw
zyb}0l&TE82WdHL4I7Anm3tJaC?p(_ptJOV>b@IE_vu)*Ex4P62eG+sdII5|2km<3o
z_)}Y9<%%3OYO8w^;VE1V;GxxO$nw;X*`4;r)cp_g!|=9mxLHfou)}6UGIM6p2?iAG
zq@ID_`Vz4MKrcCMJzwg0+dglMWj-R_e+k_HKR{A;$tNjO`6OjGwK9;RSah>`Zcv7d
zqE8EdZ=GjQLvnoiTEsIO4nfyf1YHeQw2m^DkfsI{MHgb>trXZ~SxfW0EYTnxji0X|
zJY4or@I?`0A?|@Vl0cc#MB~LD`RhgYTnATw?zxGEC`jCFYMB>Nk;H8ZN!-fz3-e*4
z@|^cpZp3POe!!V_3i*rRueV6s+KWAQ{^lMdZ(2Ir=sjshep)uC?orPGy%l%J)qR~{
zO4jIlSRX)76PL${^c
zWF=fOqLrWxQK#TF77(3Cy->J2*Kn*`UR>W#$&S*SN@uQ4Gg~|=*nrDkt0U=LAz#$0
z;pXShGn<4S=x5gIVKq7h5s?PS?8<}GpbWlPX9Z77J%PLk#)v*?*~S9l(ktn8)MI8|
z4zh{Tud?602VbX0>Z6R2SFgjGwkoZk4xD$$o1Hy`>{!iK^>EiGfd1>M+7V+Ir$NnI
zo3F}v#gFCXQ(>79OuBNezLoRVy?BMNzBPUjLwXa!`_KbIkCn7+3M*@cOXJzCk4>{}
zJpvoO@qRkRJe&`!Au2i#dU;=NSFmSs3d>PkUPb|UjO5g8X
z{C4|)t9AJv-|yY{4W2`$4eHfSL>yDJ*HjzfT+%^O8_&yFSeGXOdjq$_l397W6PidF
zujhdiL7(WUAE&p%_rG!>#i+etLa*djK=;V8dr6O})IhpSfArofH=o*lPl2ytn>&ya
zlx;>Zcbxk$=KB-OwTJQ6O+6c8=kPS4M3MLSDOs8^F*=_8QM}wDH8T*C679L;_)Tdb
z_B-T;zqyAbV%(e=oT-(2o$#H-GgyI?Su^}uC=RObmNP4)&+_3sWbmHQM7XUV7
z#(Q0s`;kWzyy8?!^o%+Sp~MF(I6y5RkK|sY0rBN7m20U=qH_v8izPqNM
zwz{uiN7#uI&hcn|e44rB3f5Z}{a1xHY|s5MFT7PxT(C7Qp9Kc_06wwE)^lrX^7$=}
zY$o2g`6X_41#6vs1@)Hh3bD`I_Q(LY{T
z)vbD>-xb)x8QVF?zrY=c(Xc^*7GXPV^rqa*Z__X127esXJ06nl3o?g{|H?^f{txNd
z_xde*sG<0Pxf1v=SxmHZMwdD
z8G<3^aN#yb&Eyg0?P*cy-G{ufqGoFrhgHr&^5aOS>+b{@T;Jsy(2gRR>V&wW7Sr@c=y*FdWL7C>Zy{j^B
z&<4pE6p^lxJ-W;)9bv(@PABh8VA*)+^*<39Ct|;pYy@o|#v^ats`ZnJT7k?=+gMR%
zH66h28mA`cgoy4N$@0r_q9R6nuX?Hz6pi*oTMSV(&UtD?9y=E!7Qr$=?n#o`q7PY1
zG=R7k9?O4?<-mbuTZG@f#~N}T*jtPCHP!2`s+9f-3r51L{%RQ{2_+uJFV{**0c87)
zwKABAbd!Z)JgfnL`?~Hrf9{{&j614j*jJc1u9N3KccBDq#OHD-ZEbX8KdV(-eLJY?
zc0k`bm+1M=@8~=B{q(-u_(de}B5V{JgY>XoD9m0Ir2pxXH~u9<-JL?cs|Rs6Y!!cq
zGCr5l@`6IuHXQPEF)_oz#VGK(ZXg#!Epf52brb6zOFy{s%0_6VGHSp3KWL>2!{!ap
zN)?8U=+{aSO{Y+F>)s^_%pb91Zlk$KfZZ19qx8HtWB*GywOT$DyWOMH=)ombk?lg=
zx5pLiAO8mUBsp%av>JSpJlk220JuSuV3uQ`p+vSDZ{2Ie_uoR3P}Vf^rYBDit|1i`
z3cF#wpk`!!RC_E_4(e5m>{iM8ryy`ac*fyv#bIj3
zQ9@o%iVl`ECNd^Dael^VXiL`Jsx2uD(?ne)ikWQ0WnD>tHhSc8#RbC9;5V8E;%d#K2&Fn4-=7+gDci
zE9~U^uGLh
z32ze3*UyLQgev4u@syL1NpNQ&WIMA{v3GoWOSv$clh73pPH)o>wf=&Cwv(R7UMj!4;0r%rzhD`{WcwH
zWD0_Y+Q4!1mvEHJ%3C+y3A{6wtCT{W?ZcRNk@*m#6P)?N4~JcWwi0CTXs8R8qEFM_
zw+SdU1e!$IA9h?>64_jwUT}OwIzc$Z8T=;Dx$ek09U|9%`*6M2@PeePme&RN*8ioPCg`*Bu;#h@r}9Cdj>(N_oyAr(7^@5b;8
zefT6JaU$>uz1<_EEBHhyaqjn&dyA+viaSAB2>YotY8yChKBQ%@3d8rU^INdp=eT#>
zn+~kWNJ!0CemL+?o+33PTQ=A?VoylJouRvoOru|6UU}<<)KSBal8TEao#ZfU}Xhd
zEkC8dciKz%q^!v@bw!X0wgeU~Fj7G&-A@7~5DS}dSiNtj`&8T;l>1k4552yfEZNSA
zJLpcWsi?~@>15LdJntF@q6xPUg>uaFLUjse<8tC!q?HasY
z13ms4k`@NY!wSoO6?KMInJ~mJ>FANAX|S?tq{X#mDLW;0I&rY#X1)~pvEh-^`y$!?
zDzJOcSAg9wDzICD+XTUH!tNIVvG?^fT21w^&IT@8Qu4KRUM_5%aCTm3S8dv;c!!Z~
zXXMk9K_81TeNDm*yf6Mmf7+BlFQ~%o-videCb1vZkGs{gW&i2+00{s0pN8-^
zt!)Y|gUEsbx=?xlswYGP=fxc=KH`t)1C1zO2k74t8V&iq8<}*A8956@MqxN~p&1!3
z$tR^;NC>2l{1%>b8+~VT?DBeV#*p@^TsbB~VT>LUST0yHzv5xQpWM_&5dXEPk5)l}
zB9Pgt%*$Z~4{PjA$(uS4CX@eBIjp)}z1NWw%M`OZisW}AQmX}*?0sZj)~hkM_iDWR
z)7=EUtbkrN%eAQYi>ivEQ>(k-7m9pgjv|+;x;vItY}}Mn;n_LjF*1@qznM%E_2wCR$Q)s
zjRZXodE~P!MMw+l2qqc{=Y&T*f>P8S3QDO|nfID}f<{{SnvRxzO`Y~;H~ee_vH0HY
z3pPSW&5K(!rAb-wthiZIO4ObYI{jH`!=1&+aa!De=H|f`WIJ6Y*o5Hfi_=1K6LAOK
zLr;k~E%JS#8=2(N*qfdvzHD(jkLTgC_5XR|CDs{c+e;4;q1^
ze`HxCUCtk1cIJSJXGF~bCdW{btTmQcY>1?NFs<{INjEsu3i@|A>;NA{B+0OYL;5|?
zjYOaLTFifNRSorkmm)#4!xG>HSb{K}+k_vK`*Yj9`)54%V6Cf$c=i0>am|s;0Yu`4
zWyt>VeIfS4MFX>1Q7kiCOf(%Ao(26C@>&p-%O0oLz4h-*+KXI+z??xw
z2y+PRYdvm2?eIgq5zzW;+0p`0L*(&S#vd+$*N8Xe<$c(TDbwFx4WAWSN!rWTYIH37
zo;YFR4A%u&7VIWDgcuh-Q;f}-DURMWQ;ZpPzc_xz4D%*oo{x`)lqqJAShkk|FRkHI
zy(zW-0WS^PPT3D&|9GDtfcvvZ%m8#$_uqtS#}TJW5*ThaqP@zzv@ah_X?hd!x0s)E
z;Hwe$NcZQfT+&ly*J)s33y&2ei;iK)N`zRki23nue#s$dz*OaUUK7bsPFM21vWR2*
z=2%UwDyJ)tY1?>^Vu2;#32LCeK(=xpWk03dDpxdBh~DD37r9m7M+``ZyIXRr0IrE6
z`qDXkjeT*>!>H=T;Vd&aXe=`>p6Duqd~GIJQl`sv)poibBwu@6Sr+sbuA^A7(6f+}
zX7t0gg@9EH0im9dtqT_dKBWUbrTZ)<7g|BVagYs|J9~#B6cc1-jSo8-dM(QDyho5*
z()Zi+J8h%?w>7?oM1pSDa3UoLKJpZuGONdH10=cqh!*(o29JX6U@>Q-q-bHv1vc@lD{8!@H67bCHe+J7P7j&u|N%|of
zy&OuEy00u{f~0bbl?ZI|Q%SD%d5R#m1<@o_z<66SR|0!&(FyJf@BnzaTNQHbXY0jV
z(&dFJekN2)yWp=AU;ol-DsiL98W|jeh1OGTlzOO+7O80n!qZH7VV3wk3cN9Rfir
zz{=I;;B$lFSuL1_bD^aV+2Of!yljeOMhw^AN}YwCuL#c92#rA_%jo|Ff$n9fKUs$Q
zJ(_NTW68;7ktC(i%HsCO3|qX$6Yp5^`n$
zvffWn+6`HNBHP|2C{|5~lDUv#ePA^s`W6OPBO$?6O6IJ^-#9?=9Q3^wC<{9oBdO8h<_DG&nJM3?Ukfim#>K
zh?OJ*c&_VMw?Zi-nPbN$g_bjpS>+ba_$y{KpOhKFT4zmQ4h1Eh`zvFeHI4Z)
zsQRnFq7{QIDbgCtExLcNg%l=&Ew^MsF0T7`5bHd-mKAd{nevF%IKfmR+drAB@!~GKcu;uh5n;iTRSRJ{Q3{gK`j&nLAZDbRb_|^bhdbZmsF8+=%w>jFo2U@1(22O#*&lP#7|2)a
z)Q)%|+FUQ-H-r3{5e(>BM)znIle|G^y7#iEKFACbbSIWF4{y{-(&cjX8D^bE*Pg|!
zL)%Wbbj8_t;xe5`kw4Cq^OqP^BP%5aIaMsX(=?XR8qZm@DaiNpsGH#hvX{5c%0U#F
zP4L*?$#TX6EH~>Q%iVt*k!H@Y)`u>!x*?3(^#QP`we##KgLQ5=%gtq3t6?ImJM|Ky
z2~B!-0xJgLo4KRdyinczmze7BCa~o}$5~CN^Yax<(zBnl*10oSG58>>dvzE?U(q+^
zxaa0RjBo5~{a=ZLj-%{ie0j6fAS$&ypk`64)chy8=5p;pHZMr``3p?-S50i5Mz;{Z
z&Ns3e{Cb{AT8dx1ZXwEMHn5r?-NOH6lAdg0HJonYN+!wt0U~?oK7W}>%5t-LLy(ne
z2thY!u!ay#sr%FAA-ezl?-1apAcnYRGq-G?CrTM>gS127UGK
zQyXcfKbCfyrZwhBzhSgepGDgsmgjtgQ~DkB=|*O9D3e&-+sGE!+X?`M
z)t5H36OCe7|B%ebd6^Y;|k5b#wed2$GoLXHNTY6oybG&4Y+F9Gi$`0
z2AuvjNXbBnnkF+}LfZ#E6x3lFgR`|^CU(D5W0OyiwtXp+l(&>|&dZ04nJYZu`Eo3s<6hI?OB&+a6iiAOPA|dyE`%HUdZgGQxg}7PB9qle+{$5#!ACWy7D1}wu@d{Sp7e&H*?vP@?1
zp-mq-1;8`lbNXtW>HT6r7DUPXm+fwXB|m>h~09&JF@
z`}cFJg$6)O8)mDL(f!+o-#m6nC1x`VEh!_{o^Z2CHaF``!@5RN7BEgntB0uum9x`ABP+LT
zk>~9hwPSuCLr_vXKmV4o$ecIuw@!Wb5^1l-9P}o#%PG;_Je|*M(uc(0+D=l2-H*gY{gacr4j=5{KBaG{;ESjAbsK
z!MDb4>ZfIdBIh#9*;)Uj0X~T-9h0d?ke|&B(z6W@M_?>-gAB^AvIl4Ro-q$bw#l;m
zFJb$TQZ|X&%ud1AtHCplMD|p9qvSzTpncOVpF~QO%rbA~Odip8nV>O=SLLfQ1cnMpEih)=M*u
z>Ut1$MIH5xd8#+&;jGho-}|X&jPw?A9cWOf5B}%$9j$Z3QCW*U9`igjQr=PZ9|qN7
z7I|g$GA%lukMNd_KP+qUV;+7MyKES=g8IUjeEUo9joCDhm2BXdT$p#KZH!)dQ!x#F
z2?8Y>21+&zlx*0;!0j&VG}vw4$u;J|#$=~4DXmw}J9IsLL&DuQp|hmsI*W*>yi|>h
z&&M~4xxMN&I2S!P2!BUO&^M`kV;E;O=BZh!`b34^wl3#ulEhXb1B|HdRrAt)Ht4>j
zi?up@Nw}&+GIw}Xk=R?{9LFeSIb*)s>F&F60pIkY6(7GK!Ulo^cb46*=G^U^&1C*n
zyDG~N^}tyU
z_D5c_??KD?+Q=(0R;it%%ys3VeR!rFb|t1*)-eZac;Wv&?9BK4Qp6S3Xs#+JO;mLc
z^QJH}GHZFMv&i#>!&cgkKGNdCEAq8TIY%6CMblV=+9j8zpk2&!NY*WkgN-1rPyvy|-TA%A1+j_n^r&l$^<
zYc?^{>cL|nG6$ep%gbLxol{l-{@bL5m*<~mpY}RuyhpVxS&tl)1&g}EQZ@3rl?Y{T_MGb1DhKBF`CB{s7u55fh
zS%O#PQk#Gv*C`4DGG4`8(gi{a+cn?&AG|R;jWhi4<9n<}*vaoE{~r!Pfa#O%p)YKw!!weVkEv_t&3lr>T=DS7_nG7V$ss~5j}
zQ%|Kxma5eM)@RBu9bW;7>o~~=rM{v4JkB)D_FUnMUCP*Pc(1(0v35(tSTDbn4?MMN
zJj0$#DdX2z#`tP+w^A*TCUDOT*u8w4zfInQEC;^Ql7~tYY@2``=##_7>NG7pBprLq
zTiXz~p-*%A{!Q+;ZENze1B=}XEYF+~zTGq-5BmW5y=f}kv6`w4jkatS`n_q_qy2vB01kaL0PFp=SzaFht)F^5;F
zhK?8dYnTz9kjH0^uD4;0{Jrq%!}KC!V@OAe^-SsbU$kPQ{$V#=dsDBpP0wr+J*C}L
zuIa0X=H>hTw}=3i#xwi!r{PP2VdAUj>+n6K;r{P`RHF3!`|y?Q3oMb4PrQe3W&b(B
zCg!&T3Pyq=D9@)@_S3rqOB45tk>ocU&7NLHZgpMnyE#Ts(Oo+(1(xIl@X4AoeqWwb
z$Wjw#!Z(PVK`n{vJa6Y1@5MKZu;==F8&JEeU8#L-@86Z$YrpxKlD>YFJ9_skCGWU!
zYf1Zn9+&6z?o&#>eE!yww~TFlZ?9hR>Q{
zbD|Yl5=OVA~
zBzi*U!r3d_*mPb#86~}Im6A7V{UsH6V!sJby!wonX~eL5$Rn6Sumteq?t$g|;Sb8c
zs6d~Cu#n>+VFNv!(s9=>lwU>V%H^_Dcg&qXU$*Rpfn_sbaS;dy_XhO4<9|0vq7MA1
z&@x>NN6&|$H!A$eBdCk>e@QeLzhpw5@~s*$6fvN)_evrtdHPNVD@%CD?|)qq!)%C$
za1OQ5n94@?p9p2vHU+fKJWcJ$lHT^LKT+bliTp3f@Z
zR{FjTdv4&jfuphf#{Vs%^!=9l3R>jpf#n0wndP3F<=Z{?$>&BNw(J+m-`!tc_>Hgp
z(t+g%^yjXd<=vI{`1)fWSbji%#>?~Eo}WZ@)3@kK`$XXs692p`p@mR0l_t)dc@w_x47g*vcaQ@g~C_N<-C$D@+UxGL6(p+WNo%@Z#
zS12X;$=)znW02it*K-~Hdyse%q92KJ;H7=J4Mu1IRl(TB=Jg(6%uQY^cu&ZWNMAIh
zFLq*Ch|$|od;Nehvklxr*BhTwU7HQcj*|IqS!QAYCtZ)oBINCAckIi}Id*{JS#-T|
zQYo)WR=!BE%k^EUvSnVfO3mw`i-7{cx8FQ5bmr>@C*;CIFY(4H_y+*a
zp*?-z{LZdRu=AM{@?Q6SHCm3VWzzui;&$LeuAj2
z2pAF(FC>vg1_yoDeFNuC=}pCe-gLlMY?P13G8Uj;g|F@K_p1wem;yNnrzT82kOyI4
zYXXU-%E$NS$=|<{EVlsr>cVf|^4FCJTEJfy?V&ewiJzEV2d>8M=O-{biCuqA$lYVp
z&W{)oWy1Gc{2Z)oIj?WIQyBw#qM}{z<7E;HS60~)aHVZZKg@#a_R
zz^@Wl1b+39-N_GwZSXM2Gw#|zHFN>{_xG80{e;{qo3+tup8B#IO^8#`r!%9L-tby6%gB|@I6pe$~Rpj`@gyM
z9O88Up%3K?Iys|SmXvr4SFe#Z%w5mzrtkb`&Re)W$H{l7Rv$kl$M%UkG$B{hSe1*2
zYWkxR>bX=2+3g;i0talDy_VAJkUS$!5#+;(`?D07aMzB&Iur68v!t!W>1m*;%E9{c
z_lL|iZ#&7DH}K%T9xC<2Bg__P6LT@x1
z8)~P40w_ZkOvSoyLay~uBW%D3Ru-;OX8+ihz!@QE#~FF1K!JAWD;eGnKKV~d*&#)N
zWtG+RCN3(MW9xO@wYmSTvX1@mT3(NbvA>AZPF#fZf%O9&;NKgome2i&@;;Gngy3R`
zw9jr{+!tzdB-j;+@RE-!+p<#_iNL=vE-b*!BLp^5)j80Ww
z_}*rSo->Pq2Q)M7kSvW;qvpCDdyLm)nV#!xOb9pB^#BP>IB
z-hR|uxZdrD2+Z>S83YuwO#Sa?hyg&kU?|&y=A(V~1iK5k!I_);zPE7j-@i2^Z|(g#^C0|w$XWB
zOZ3M-7$7fc$!DnNcl@_swnx6Ria0ZC*gtPXZ$EjvC
zr)ImF(M$WXxw=6Xjcn<~JaO;^R@SWW|32
z>p6-jRb~A1XS)t#%$DaPtf;^v1T*G8_sRWZldYA5Zt2m)3s#hxYl|{zi=|QH
z2^v~XSC2arXP2Mnoib{-NTaNkvoTY=W{oT4sM0$+YZ-F~&W#FL{b+WyC9yMnW7@jp
zN@sNN)$Pz15dCqXk7~6EgbfR77A!wp$1j`v`GmYGyF$GNhwZA*Yut0l?`;KmtAnrB
zP>c?AfYnW_`&s8TnPOIE+&A7t9nJTTM)%uuw8q#~meM_Up5Ze;Gd(Kfz%gOo#Fh}s
zzod-#hrN)68g(}K
zjIt{@Js|JMcrDfn89ir~|`
zb8Vt!73T(CBPv*SgNOQ-8OS
zXqDQ3{s-Iyoi?KVCgj>lLZoN@SNZabcly6n-WMqEm;2t=^uL$$NXh5G4sVoZjv$BT
zqq&UtcDg5Z@JiF0WR)w9Yyy0KOS~wP8$&toL
zhwY9MPmE3C+|969gd_~7=**|y{fo9Akj!`VU|r(!Fp9*CKlRgjZzj`d?0}0`RLEXb
zGdk~enQ}dL>8MPX`p)VfZ|$Saqx5mt&7So9FZRzGn=$0zXvlPk`rUZ(y?~x(F2{Sz
zvYs4ch1}Dg7+$hcPxC#hi?aNVB^sYW*48}dxd_@tiFME1+EZ(MGSl#H@BTXqF{X$f
zhDLO%*5Ci*0eue6`hWNNttY*fIeki>?Q)+V`ZBQ3W0vB5&;P$ZTb}rFpM&K-f06ss
zeVzh8v&ed^v%3EGz?R(H6AILNq!m1h-R$s$hD(SW{g*zbf8A~AUdwCWtU`4BR5f6$
z-7^>(%RlrD;sD#Bck_4#6BgYhW6=s@+c!2t6mr#%#o1VY5pj^o1CT8ryb0cZl=07w
znD&l6@ZCqGiaddM2JyBtz@p0-S0!{p`NC&oVJG6*C5Ezyn|=xMCin@ABpm<7rwQxE
z7^`!4!*ZQks1}NlgJB8uYaUe+UqtPlpKJTrCdS4hYtM79Vr~L31;Ii3O4-Y84|y$5
ze?Ics>&Ec11B9Quo_mEg9t5s#lOep4^M3Y8g6y1>iE(0f&Ul8oFn7*e^(VW!_QUA$N=XhiIU;AhBoaD6(ZeM)G8DV2+-;u@M+&qFV9XRvU
ziy_W|z25vd^_#1&=P>ib&N2s3AMC5uo$Dce)j}J$R$wZW{%>TBr)qeEx8qph7-qlW@8Cv
z*S`aICk@j}diT-FE8g`M``cb-sAYKFwP*=WAt
zVQ4=V%lonT19^5jc3i{imIbWOU8wKrJvdt2aFMzQ(pEkht|jq9ib$Nc2M;Pj1+a=TXt7LmCc3c&_Txl%5^++q8~31
z-td3rxx*Il)iJy8E35D;`pWxp|5p^vPdNpC<4#Lr3x?o!=_#PORw)=1Jyt
zEAq!9Hz-kMGAtNDztxC>P4kw^h+16TOH}3ZbrO3elB^48Hg7_V!rIRh>~?4+Tj1NF
zoco3`;#y>QwtV~kT-#xqkA{92q0mYJ;|soZd`E#T@4=bqQYHBGKp15fGQhx^jr2g~
zaQYpA-_Qcx-UoUQ)CROh@V(Gf*_1KPDOJWeDR7LEfl)Qdqx?UNYSHloJ6TBdk1BJ7
zGOG0llu^}wbnB=nlb!}A9
z*?}d)8`JVbW0iMT5$E2mBTJeZmaJ&5Y(#|2p?omrR^2)L$`4l9MfqqH)sh?&%sT;-Sc+pc&MEfGJaO-HA1PFF4X&w~n$dN*jkknis{g&);QzcwZbU+a@rrm^N_
z->My^JK5D~orlhMRcnf1nX+_f)VicJw?4$t8RYU>-5OnWyIWu2=*)3>9r(6dxC(#O
zG`6$*`|mjS9^ZVylBJ+`=<)ZoDR;7&wK6PNBXqr9LvWb<%{8AZTpQQOGh>pKJ)-_3
zNfQTO+I_HC#MqnNoVoZyShW7Q8xbhD(OXD1WYK#&rk@}wVF*#`kgIxQ_CG8#_ppQY
zkkzjf`5q?96prYQQ!heZ7=D#`#8%D^V!VlA>L5L=?P9XiovYLq>C0og~
z?D!i!AuFN27%>#yu>p8|^W(}nP1o-Y=uO!SNcWENnNCEP7}?*SSqbYLkdV#MLq?YU
zue0ziNQ`-LmfU*bLvrh{35Szwf($cGQIAsQ%FlKShjH@dj62#b@uLu%3=+hp9LDRe
zsNto~k_)}u;Rr_j6|mwEmN7GfRKWkCS3`sJ=1_hF)wDlZuIX<={id1-SrWjxk+oYM
zV>#@BxCY$W91&wiIc=F7q(yfP)9-AAMG`!xmNKe3?nE3zvAnFacB}q4%ZhvzT!We+
zYk5%BDWUK}GYo5nrBwf36IGMYZsD_U)u!qT8h^0{X_RC~E&JR#wb6zH?R+NXQ%v+p
z$1w}{RM|;_Lvuhhx1%^->1B3l3uu%?=E?r`BHN~MHPQOLM+WYMu!&Xcw2vEqqK@%iJ)kSi
z5q&B?lTKB|L2t_)pVCTbi{eKGo(1I;6qv||fFQb!2Q507U^Kq}!Gp7>K*W1?PWT9W
z|Be3`jYk7#Izk$awI$lQe>Hij9QSf-SaThZotd3}fOcNsUhPuv$=5cxx3bc-I<7I6
zu{MxYBNw*k4{oqFOk%jE6|f>d#FI@oJUyBKyAaR8+PH+_K1h{!^vs|qG`lop2af$L
zRi9tV*l0h#IuaC`(raTe^*Vj`e~cr05Kom+q-y75XupAKg6&-Adf~f%zN52P_>Sav
zW5Zxgr<#V`FtRnB3i9W#J0tmT1MTTnzsC-Yo-Wh$_3JQhzTwz}T!jxESMHNm?TOq5
zI(X2!h+Q^N>S0|A9=`Cg{3~SvdoC)tGh)gO&K*0lM2fR%Bl=>9leQ&e?xMWerP~of
zcH}sTGQ`;gIg_%zJKD@m5kRwQuM9Fr1grVXgQnn{`^vJKWFVMrKrMVM?ufkI5GIA(4(Agv^
zC)oh*Q}!TkGnv2b1&<-BS;(r-K(9wq>SJ#}uNVT)XD$c&u95Hz-$b6_*`r?Qd?ohA
zfAkce+n+If6}%H>wPM%Irrl^W}#vAAoQ
zZvLi5&6y0$_GI(-#2#mHVDUetX%ApX$6l_6EuARrCLo9B13?^Vgc)
zLO%7QTV0PrUSMljcz5n>+ZYqYwvhXO-c?B!XZh#7br1Db<%S|=EW}8
zy>m(D?UQ~~H~IVNkO6bj{my(re`VXG4<_CJ8UCM?FrpnN-8zBEIC+Hj1#tM1HI`A$
zicF7-FtU_8;Le)Jzmsew*K9TBGO)@vMZyCCuz-in?|5JB`c!FHUC~3SbqANGx_N2q
zv8}MSQeqP*vOb%M^Z-hftd?xrOEItjxM@8Y6Ej_w=$$q_js8JhHtny|T>~*0}h>`sGRz3AV+~d)o)NegDBMZEJm{{e}Lj(9n)(GpX
z%UlEa^^}x2IiiX_><`=+L@kZU7$eVUx$v
za_sRVGY-9;$VOaQs2SldCF%d6e~~0S@A$pu*LA(R{Y+_2zcBH{L^JwwcwT89tsEu|
zY_MZzF=KHlPS7uZt=CdqW2^@!)qeE-bQ6i-0`OH9^4ND1{!>r!hk!EUk}fh2B%H~R
zm@P6W_yhy*6O7?Qgdyc|_L&Dz~a@Vl#E_OBLvQPJaIzBUMoQPQE`S0O3W)#*=
zS5p+8%(S|irCBq5c3AI%UbO8aUtcMXAk@A_cuJUrBp}_A%-g*OJ(L@NFV(~4$OsRq
zE=lz`n!x=c0wM7BjQXA6FdWeTk(6+bu!YBcEznr7j@W85&;xED6atwOK5U;A*qyHC
zW_}WE%CNG$*87`ZOf*+HXv-!ZP|<;b8mxTD7o?vCAGw2$R9Hb^?|)gyZicL5RsnDs
zOoB=?l?l$iS7Q;`gXJHF&03H+dz0lc?9S?Gr<^x3Gi-6}uwoNYkAs3@$rh^{y#@QF
zias38Cer&5h$Q2!zZzOPs
z>@OhY>ThQ5kd*f;Lc
z>%9u1dD1_=Wv)A-nULyW6gSn_XQ2>sUti6unxxbhxuiGV5F#wu1+4|1_Jx8`4{boY
zmATd$nEZMjTLpbMM%%uXUnUv**7J~_1|?}qF@A)I@v<;qG)ArAArT_!4I-Tx4Qmh^
zUc(!MHT>g+u=)54X?=@)Gji+D?=8;
zrCP+N;vO$Ft_bF#+x{~+LeuaI6Ybz%V`o7M{WiN3YgXX3pVq1KW%F(ItWoU#{y1N5
zAyrY#^Leo&`Y5LlWgn^Rnpm#K$Ry@%b_~uYi+BZpv8sf#`MjKb&C5Kst-QzX2puvS6JhLT>p
zE05}&BsTKhbNWh>qXaVjl49e^Ru+8BhKSBKik*srj2v(ztCu;etjxw@!VphCL?
z_8mKxxa=e6OF`T1BdbR*r?Gqxh++3^QF+(kAO8ACKsU%my>@81Gv;b+97$kTFXxP|
zpO`Txlm&ESS3OnXB*)rqz<<-q^Q-$123T3^5GS=-1mBEMyIr
zm02y61dnuuXh_mY^LoH#z9OSnXlG=n!PqZbFh+Bbuh3gnd?lD&tvsdK(l_xkY&ML2H{tu6_+dIw$@sxl>gx2J
zx;p7v?gtl*6^g8G7XWkVcFH*S=RH&7r>&i)eX1>O&cwQjmPhtH5AA23m%B!%i@bt=KTXKE{-M=gpHj`)I
z8Pcwe_->uew+t)fE6i3mk%d_Dify%t%1Vi+Q@d*LzopC#iI8cuEcS-~Y|2@9KW28Ga-Y((y6N_2Sf7>by(X>a0vR
z@5z5~*{(eO)nCH{x)C!s+h5WFvFQ4)nE~DLpInX)yAms@AN5l46Ob75p5})+yR*jV#vxGdziA%IlgeZe~8_ZBQgEP0W9P{
z!yYo~o(EP=|C@7`>NTd?7;%~Z-Wq3h<@O4q{bbC(&9L|Wk~jAKl5cX4Ikeh3`dBh{
zgP)}_;3T4z9pZEMp5HPA!S|w&Y0xKQ?ngH8#y;}}
z*cS~;bjZEL-c-*K4~UjuEV7}hAHJc%H#CqB2)nHMs6^Hom3YjktI)XiMBxPZTi39D
z#+c^?;{f~(LQI|rPGjs-p)qQ4jr>vr%U}Ipt&hQaW3Wcpt{IsmtxTzy6Xv|UzBB6U
zf(0v_Uq}xHLpoQdjU%t{5pS*Qo_7mASO5
zfZzQL4nC>OxM~h?>MWe|nHhtPu3Qcy9Nw-4S`ca=2i0rjwji`JsDydQsG(&BeeM$0{ocz?veE~1lX
z%4jym+4YDMdBz-=b)&{5GAh62_(ij#i6UD;q7HD`x|RQ-+9hINXqneS`$_yhvO6fn
zDy8Ol?M^kvcKhm7C08Tmy1k643Af6)=O>pK%g<{G_tPns&V0nTyBy7bhIMAPv$7=h
zFF_;~puS10CT>syejs?kSEJmbNY-%k~C=R
zrW{kh>UfN}Tf8
zcLP6oPo0k+?NB_6uGV6GYf*4PbqoH}_sNr*=1jaD
z7^H|Mb(zgfr3fuUII?IA%=)f?XzSU7pdx{&lmR~tXOSQ6u#7^xCECk+e{josk{Qe#*Xslz>2p;mb6|Fo`ze?xB^L9d3e2(uv
z+3I2=jcn*mT34+7B4P2@7a9-UhzYa`@g$E+wG+RuJ2z7OKCG}lz5T1R?j;$g8`SQ~
z8Im-mnriKO3S2v8?ZsF+jnk=o#=gX5wrVdY_)54v4*75O%v0Y4x@_mki-1NsDfb{B
zQe9c>k=po>PhmN9t%)V2*Yin^CY~gX6qCrcEEuQrI=k8qIv0jKAUzb&Wd+fEaIWcy
zHAYMa7mQZ*!Fip|iS4J9Z>?slCq8bEo2Z=Hb?1hpL>LM|L!!8a
zEG8-v-ENYLBy3L1$!?A?2bk{3-~%|b0_V49r&{9Zk?B#-yVp=3Y<(x*PVc8AZZOfC
z!FcnvX%WABllDOMUF8>KU|Lwy$M5SweeJHt`kirV9Wvggk_MxsnnwwvHR8OwE6|>B
zdyUj`sWj|Ay;|9#NZKXkt`c}%QC_!#l(Mar>eOOZ@5IYW+q&wXuFj8D
zf0T;ntjH!+EXj&VDGboeh&!UzwWOfbzN$H~n#y@CWtaK&A*z%~
zeYYxqRqX3J%?Oe)lFWwck2x17Vx0-C81BHD7bX9I*^!G?+fmCxYHCe0@s*??A2Y^E
z(65YhRC!}kRyBuKOsX&z(|a>hmhZ1EQ`4qa7-O}!r}-yUY^VrT>bc6dZhXIrXg__8
ze9mK1N^?1Dk)O~(WQUiHacmfWv@B--;NlG_bGtU|J3US`%WJ&s)IO?b-o==d4dY`f
zW~Rt4pW5b9=d
z0=FIW#XdAM=HP~uLt#`Zp@umJr0gUeWgeXV$;j9-bYLV?;<=mO}To%M?={mpa@|
zGhy8$uD`X1`(KFa8dX5l713-PR>@9T{TDA>A7kGzzQM~XD$3lss9~=5^$p`{EJBr*
z+j&^36w=Pz&ww&#LAsj
zEV*^-C~<;I5?A_zq|O85#uUz*6;|nO-#QA?-IY~96`T;HtqV+jW{<%^dzs_UzgT9D
zhr9x1wV9G?eY~gL#|yx?QavQ}+SkU&avRPr?QEuXOrg9GbZ(_NVhn0$6MWP5@0uF=
z2<@cssjQ$}qDa0`gpDF2T0%E<{8XZG<9o)f(u?qkZYNnH#;s)nQ&M+GFDTddyRUiO
z*HzLBfvJ1n-(^*)sF53Brdk_~?Xy5Xy18YlOmflu0p?qH+;JxZ>=Qlt)DN#FYR|Es?1I+MQM!IBmxaK_?;EUC@P=?;j8r>2f{%WwKvV}V^;3oPy@E92}yg84Qk
zwP^nY(-Jq@dqJ&9Vr5Dhtt4l>#Bs-;7@jk-T3ZJ%n3l6m!;d985|4Pqt?1nfZlpzS
zZDcCS`k1vxDve7kNjurHxGuU%tu58_-P7uRN4-xJ9$E#;97fa{L-8-NFjK;T4t{V|
zgWb$o=Cz!?7Lz8|NIb1w_~uba>s!X2Rd5tq&ep4|7g6j`%MP>NVPO3#Y(9zXNIU6V
z+c!nYqr(BfOJph`!k<(S{k!((rs&FtCoaRSK-~-tX*sODA+vyK2jI0
zCj;i6sC@RjSL+BxWc#5*2aZ+O?fa(uh0}AsdF9l|$_I~?Iz9QdEa|~wwyJ@fh?$CW
zZ#lSFD5RwakJ%?yy!>pAXyGPjPvRyS{sC=t$onH)dBH8ez^WPCUO)~DWj_>l#&kw{
zq~a9U_3Pm;9P7-N*M#z$tx1|UQaH15rGxD)#vU)&C;E$gzf!r`6K8w<14FO>0(NNe=h>#R?^b_jNcRjUPFP_uNAv=2Mr4f?+
z(ojy19R9G2zv5o>M_#<<$^r7i4;%ZFeFaWY;^)idu+N|=1{T9~L>rv+ewNexMb<|f
zsFx545WK*7*j52kS&S7#jU4QaBK}^M=&BR^G2UOq$(?vC~6d@eGhh?flk
z8fHkXq2JtJFP3d~Tq;A1-7T)~98Aum`T*&T)pEh2*!$An%|OPhR}knZeUohq{-5#Y
ziIBW`%_?qZ^3^fx0Quyir#a%MJ`$BVxIO4MPKe|9mO3i
zI9lMUbs+auR)I1pH*m|!s9e21ULB24w5(|(q$b=H&kDOqo^VV_r#5Z3Kjm>+Yg6=R
z9h~bd>b*j(He}2Lu8n{Pp(o3OF
zOY>Tsl=8|P&`b8@?9}Xu`d+=d>11a>F6edFt7|&@X7=?+pQO;KY{s$7<(tmSukU5{
zRHBtNDe-oqmH++hB{~u(`8WEm(f7DXDP{h5dj0x8)6sK#{w*DagN|P6rlWAs(N77G
z|ACIAZaUI*MCGRzdKFrU>9`?k^pR0)(K=7wHYN)py!^_;gFVt#CSUk1mYd=-3}l`a
zz=R6z@Z%`(mf4|=!s7dIiCQhX$Ino~JBgZBc=A9^99lK+VSSQViIw2}J_=QZgo3L63aVP(HgXD4
z)nBPacMw%|bajBLzWg7k%H|u$oX4wdL__VI939GB?>In1p5_~h^wOy7Vq))x-Fopp
zHowS~H;Tzx<@=E1fVM9E*30G_s$hZIsv?0_xfytqRX`V)wV^DgLa#Bi?DzEFNst*@
zIeM~BO72Z`=0lz;Zx}`^p3PTBi$}Tg!;&&u4Zmr*Df&UfnWvzUi+fk0D~uJ5(=mI|
z7q(-Apew1eZ|?2+`39sJ_u$K(pX;IV8Oy#`Rs*?jC?l#e#!~&CDa)IjxqH>*xx2Gd
zhkjvCjr<}nRs7JCfO8CRAZHSBF&%q>w(gzS?7Cw7+Uo=M9(O^
zTvU{AjPSDM)|VHehSQBJ8`(N*ifD|J*apPnl2}OH_PEz|LC}(iK>|6yNIm;Sh&!QO
zYGwDDdrpCz)vyk=51Nqb3aVn_c#i{om(yvurrGc)mud$;pb4_g7y>S$is4Lsxmqi8
zl6JKHfuE9FfB6Nc<9h-uHuH}$J%qXhCePZ=%Wp(+Ypg|w5Iqem?hxh~4cypj$iCLp
zn@*3P>>ZPHsjNuR3XxCdm^JslXKpXe9c>Ru79aAjDY?-%b*Aa`zM}noQ`h(!78)bY
zgBx=sInz_`hc_k5xF%Y&%Q_eCm0a4YF5|$~8$xYDRXn
zBi)p8YTT*)r^ZF>kMXHJe5U@O_ajGzSN^q)pSEvm#mmrtZl7)(Sal;wTaR~rtY*Bf
zB4S_PYRJUc7`JgyOZkdxhy$T@6Tg
z92rxXq(t}P6iqXH;&D3D+pA%%1C3-QxLF`AYzF$Lu@C95A(!Y|1${{^Ru|RM=3Y?*
zuSA@0TxHK`8Qv0IDoxKG0?GU;Ix~|*CX8e;EnSBR>w-Atu4^if{M>cpfZeEB)eZ38
zzv1tKFnu-)%U2Nu)$@7$p`Mx5eHI@G`d&fvWBO6s3_EDm!`o~5_@fmw;Vy0y3
z<;ne^B?;m@u&fIKmrlHi^PN_$)7QFPZgVqHav~?9%d}l(nFe~R!)q&8e|b`A0)9so_P9NfzH^q4Ara71J`0}-R;xxGD7h7*dM
zK{@yQ{AC&Z9~BvoJv?yk>~CM62MW=v#>zOkB!q#x)z0|B#PtZ+EVB?bNO1Fd3&}Y}{
zwNH+BTG}CX*rTOcLmuAUQLS^F)7zOl7>KrcY3B`ZgHC!K(in!@c>jz=_H&A$cCE&ef1(Ob~$JX@}gg|DN?
zPdy?4%SMhWfi$>;^9OlvY#86zEy+-Kmeh8P&bhHoTop>)TU*v6Q&Z_l^?onS8=eQN
zsg`$t18OFi9e%8-`#4{yPlp}8FMzBTatwtIxJZ`71{!60<7~#
zP4)GCq+tQDio!3gKm_gA`X284NQc>r7%Z+f?KM}Eh4np*ye5~H&ARVfoLi@!`jdAw
zi%kyV2u-#?pCOq}Azk~PUMh}0wO=pIiaO;Bv#vXQT`SEr2gRQ6Pp$`fE=l*1A
zEY7+KBd+a-;&s>uz`mB2uH0XDUaCqsX$y!Jf7Kq$q`Ad)2JUVwp
z(wr!+=D61o)JLDIJpepoe&#-xUAy$OIoX0}s8N>-9-H%J!Rab5A{_54Gjqjw7W+8C`LRB_;G0&Q0FEND-6=T%YC0W!WTY_YBH7{g{
zlCuQqiqt!BuHnB(>fDR)jKgU*Qz>r6?$CEVraLZf#`T#!zkZ#0P<@(lJ?3b4zVk8N
zX(iWZR;g(v?J?cIeAi;S?HEhGkE!T>+B&oQm#=l^QLo`tB}UFPv(_aQ|7Hwo<*9ZQ
zv5q*fVa&Zy;Z-b4+}-o~aF8i;#$Axo#Xb`--TlqcGI#p*E|3*+o|9+Pv`61wSGjGYZZ7xUp
z)3Uae{bI_tqPHBXG%6A{nZt9lEv3pTC=4B1L3;?3c9~RcS>ooXU%3ca!2lOSdyKDk
zD;$__uickzq3EWxehNeFd-;8VmUI8v#|l{*Bx?b-YO?x`&gsL@;&(g9+ne+i*h5;9
zXTJbFk60YYdJJe3HG-Skzf>AYSJ*6!48%S^-95dNA~m0+=Yd#mx_W*73B8!5!Sg57
z=d%;ld#)$_F-QuK|M|z<;tjlS7S(&MC;d^*vdR3IIdE>OJkm=2W&Eh*6S`s~cM@I{
zGr4Dzl&7)3L9yaB`vZ)d`-{o2K(TvG#9CpxROik>9!E+4;Dg|6;0Myk)D%ZQTH$0)
zbu{+p_QUs;hC+(I`rgteY1r{SLoaKbe$p&S4sC7
z*NoSW&UR~1ve?j-8Ts;xePXh>m|e{O
zGT*q_8+7SyeTJ1?EK|#L4D5L~mp${lcUc3y`#s)ei+kQZgLfTx7Zw7T0VxrjV!M0x
zs@f)BG$M-w1DEkJ;~_l~{Q31aRH@vZRdNm_D!f)hUj@H!Sb5lh-9?DcjXHUF`SAnC
zXO45_f-3+A;BsrZuM4nxz-9?nFU-~27EZCi#
z1SoHE=zzngtRcw;&4A{0;bsKKjbiOnQ7j#eMz`_g|Y*B#P-X}?qLYRR7Vg(Gtgy>dX9VehhM=p6|<
z;7SFXyWBYO!TR(Kxi|ENj%1x2+7yZ?tvWdhe#+^UUAFp4QP#BwDJ8xwy-8_U&rR@$
z?Qgdl3$AK1H`}aLUD#^{`FTY4bF_CkM<>TPt50SPaC+*RfDNzrMX`E@
zq+y+g5N~o!yjy_&VWTrCz1^g@ws(n6IYNq}+8K0yzUdlJ0d;avo7R?|(HY^ioMX80NzDf^?Rv#=H$dwTWLs#WWWN#iC@vG00nFm%1=`awn_6hdp9
zCCc+4^+asto*FpVMyCfgKw0e4e)v&!!ESMBvreAX4rDqRBNS%!zuVkq^PLy>eyj9@
zLz*)ioJTA#BWeU%&g1#jV5>e9vFza8F0X0Ebt`ix&?@M&2=x+V775G%jRm|DW|7sl
z5iuIvPV~L=krz1fx19vEjIK?`g~?xc$#B))kJu+=&V(IL*W}|s
z&PQz*hS;nZyFUBzPC{CMeI4-2d3|1UmkVCY7$v#Bmp|giYp%#;O!Y@xX(GG_y*OP5
zjIVd~4@AR1Z?oMf3hX-_{`-?+UOtU2Ai
zV6z6ZA|RwhvuymolkKg)*&m;9jdrh`w-8drmhjI0PeuFRU3O)M(%v|GmDj(l`ILX)
zk3Ze2W$|sb46LCVfggPFU|J>-_ID*O7k^G`aUgzb8zu>AE<{|W0Vx%f0nw9%Snfs0=?yc)cAcKSQx7k
z8O?*yIKS%cC%HIS82@EQ{2I_6B4?;_7+Tu~^vH*j$woMsylZckoG^NTl~Um+sFaRK
zp;kG&m4{DcPAiXd;YQfg-dusIlF+^_(Z#R?-P7asb?fQuk%T!+dR6_x+Hk@jg$)-h
zV9T{VGA;8xc>i;C)v~Y0d12QovwAm_?ye0Ua`T*^Gli>Vk@U%yDnhP>@|K*}piV2U
zhRTH+jY4mB=`Q7(+kJI(Uzc`Y^Q60|Csg|j>J37g&OWRnD#+Ka@&{9^ylO9J3^ky)
zv3d-%TZC#aFZZouM!UrCko?i@H?mV_mw^M@l9(6WurYOkcMGC06BZOn@8x&gJoyJs
zV*^CY&sFd$#j_za-s$Z_ZDx}%j!BoA}p~TAY|Iqx4T3bhdwYCWZ@=)6nKH`v4XK3MsY9Al{
zeRs`W%{Q>ytt-vBw-yoCpbeoqZ{db2S_c8Y6|NKU#CmE!$$neym%#GtR_$?jTkUOE
zS?g{>#ngjaAZ?*P(EO8HH=j!KL^#$&Wxn9
z0C8UAc{ZhbcwT6V2)~_1Cco6im*$b@*n_#B=Ok$wS<PsNzFK&p&Z8_q)xfw|{f!)Ump{6T|n7TqfH^?BU?0d)uDUveF_?
zPA%x?SZ;joU2Fma>LB3y6+FE&s}-AfnqS-
zDwj&=x;z*qO#4IXyDecT;l)3sjtxXMaA_`h$J#K*YQnH(=1Qzc`E+twND2>53OkMWpNe@^LiYK-0$C8eDV2KF?cp~K_f(?t_>q{(0k{6
z5nk8{_ZQ8{;0+qu27p{-t>jA0*`VQuml@>a|@K(Hfuo
zm!M%mQ;tnJLcA?7RvUL&T#jh8Mtw2{>5IQl%;7HT^NP6ai8fy}laKz&|6=vzC8rp5
z4|0gJqmQ#A(vBXHcJzoDsYlGnK8P9F$CjAV=U%iVrq7saS1`xV_o8g6=tl5uWtW|n
z`-?hC|Ln%?-yHj`JW%XS=?8B_-=6<#xsRHDXV>rYpPElKmmc_C>e;$yE>ddR?@|}n
znj0wfso$jzI+>=F@bd3c%TA0^N?6o&d##`Q@_|cKLecN?b{!wAl(3`g_8Px?EDR;|
z)O8~D=TWiYkR!xrShve^tCt5I(Fb1)k8ZH{n!h(O$GqF9)51%2^6mli>-OEQ0sW?Y
z*D`sDs4LAIT4kGt(Oi?1M-;Flnz=?
z#?+`!(I4-Z=Is7AUwE!`cI(YAIIW!QNDvXD`>Og4(RvVT!5_ads6_onBx1hZ{*8CH
zsp<68z&d<_2bNvxr68&%-DmHmWbDbywq_b!+6Kl!B8fGj!F(wwHQ3@dqu1>s5NMWP8r&#UM&o=19NifW
zEKc*xa&b0!l|nv;vI1WTNTnF*fe|sziNMew2?f}MeS;(j=jYjcl^mT5
zM&=X+Y`**W%il&@+~DtA_Svt+p%q6?y$rmzi1&I@3ty$wztqp~a2f3I5iltB2a~=2
z-@Mms)+q3#T4tZK8S%aKpq$H5ohvd6==()Kt1_eNmp)%>tIp+$s$B*L-iIXyqygaU
zfesBkXp6tO`j-KgZu!z2XOu5isIKPnEdD#{TGThxFGk}$W00(k@$N%&%shJ+dKer
zf()Ji?dBVyX!$~b1q*sXT)=|05wJZ~zLq0>
z`;8ezH03U6
zE##g$n`zkMY-UeE&P_h<@1w}9g!UML&}LC)h7P(ZWmN4|GW6c+Z*wKa
z@?*i5%Axj=?eQ<9{$f%QK(M}?olbHdM2>%h!&(km77&1)SJ}&6TY4k2Sr&l%gmki>
z>_Xr8)^NcVIovl;Hb^*&<)UGqBmXjxv&dAKeUGHg*OnIULU2jm;Y1
z0+H42@~iA&;0-sjV2jN%ic50PISd}moG<3KQeW})?~I~nVP8OD>l~aCM~bCnRs+YND=NmZ5IxTbU~5pPei`mBWmN1~#}#79?oTFjKIK
z?t)x+>^A=(vFS7G7J(3X8d$z$)ZiCN!OjsQKOwPft5F=n>7Rm!DxPe?@148-LBZGU
zR-^VR``Sx+AGWIB+yWU(gw=)`8gXV4Ff+E$6*-*oDD5k7hSn{>!r5dqisyl#a+Ptr
zyX$zjKScbF>U^tqJ+%gZvECmeo~C+G9jSx{kNRHYojA3A^ZWOxrI4Sm^Y;`F8xT`8ZphvD=CQHGwQ6q>6>sU8XI)fbIqqWSiW_!G1%POMQeIA~nmSg~zeEBnjNR`4No^7XB@
zS<|^r!mleNP|#j1BFGj^4XR&NX!(SLhh{{u?ORWc0qA=oPuHiDPT?4ccpn;
zW42|01xVZ&nY_cL_MUR7j7M((YprJSxo64_KfUl0@|bE_th4R%$ZxTt@-x7!=?QsTtSb!b~%4rg~}X`za_(i+_|V3*fQmPf}tJehK(t#Rd)85EyTM3ud1f&
zh&`3K7g#W4E0Gjxx;}EJW5v&M|82IiJ8wEM8T%R8a*>A&J+t|&Z;sAebsUlAY6g9-
zv*>CxD_FdnESv>08hm|Fl~D&u1g=E3
zHM`O)b=4no&#bu3|FY(6wJZHRb`v?fnFj}T&FO{p)1TX~QE4i&FO??FHkakWOM_%3
z+GB=k(0&cs`j?@E(G#1w!!|t|p1TuFwi!9#!pz!aiRnl`0~$%lG{~>);gjKUof(xR
zwVLJ^;CIlXD0xm3FRv}(KXS-dYGK{w+$}vsYr6>l%Z(RdXK>0cQ5hWt72YxSGu}P+
zquy+D=Jd;Diy|>L7hoYboj3sVi}T6{9U{6RdPxpuI&Uxwia+uA5u%~&RKwHA)$51n
zGow4AskR&65r#lEf8`?
z8;$)o&nk=!Y#SesG0A;ed8|w2W&esX0p--(Z70{g7U3-EZ}loD>*Zy8=Uxs5-MJRR
zcJyK^tVq3R#qdI49psY@Usc)El#?l?OQB8GB{{00OMkf_Sztl7`lU=bWoPm~{2Gt8
z&UA4_l2l_V`d&USi8W~+?KM-RdDmL`Pc`sag%x^&r+N?n`C56umbY!6z(tt%xK|Z;
z98!urv4vs%J4NUapS$(jBo>Am0wz{;|L5d&lKkA6<
zy5pIAtE+-0M%ZLo~gVH&G?5gtH}}*GrPHj2Y0K?Z7~`9
zMfunb>Rsb#%p0=ZqSfOg=|0*m$S32~y3+g!N@Q2nCxa}_$^KmR%Lv5I4V2KMFK0hUZS+XBrpzdB
z5DU6oAh%y*9>;bQ5E7&o({Q(pC}1=*M!Pd37v&3I=X3g*h&mq*>)uhH-3N`uGFWWj
zo1F$x%*@A5{xvtjwtaGUS`tdiEWq=i4ugE585WD%HMaVECSQ|8*gEs#|G@)8A9U@M
zC{i0T^B*pwH;tP=WO9eZ(Kkhr<}jt8XRkX1VS5;7E5Wx_JRqsf0Wa%foSt2fgcqd||$<(QCA&OFq++5Rea$i;`Auf>T?+sfOj
zKI8=JR!*Mp)e0B^nRg7dhw2y9hKJnoqT&y;Imh4I+#xSoCJ5WYIDuM%p7V%}CQs{h
zPHy+IU?5nea~|=W2~WAC^kl(*yzvL6G|{068L%dWnTpE%V(1S~PJosc_~}Wt$-svj?(XUCvFgPf8ABK_l(o+s7%AutDB9%g71b
zLG;`}XitWQvKN*XHOlKkf}UQssCbt%%{zSg!7^d!B+fQ{ITMCWVx@&iwW9?1jR@lk
zX>FBX|EJnc$FHo;PSUlppTt>`77XPk?DJn+{;M!di++3$Jv)?>|F)MUiDC*p^@zo$
z2@{j1j}rW~+phWV2)X9()$99sa9Jvy&b}TfpVx?;#&z#rWAUH4Bx$WFDft}R*Zq83
zhjY!3ra<{UKRug!(CZ%%+O$BSeg9jf=Yzk9ZXhj6siT|b+xnShL^V}teyh}0>%F9)
zApFZ7lOn$jZ{PCc=P-kIaNZDnc-J!m}?F#PCs;fK6Tj2AD6%psQ%PN1F
zWr9Cq?BoxZrmjvCp2}v6j>_Sh(3z%WWwrA-l2bYg@H>d)WH!t0?lr{m&1kor)?KR|
z(oZpu!IIrgv*}3_Q5H1l`{3nTE%i#$CZ}9pffYpA@#~oEy2#64CJ1Wn#EYoiN!V&B
zt6k%TK>5ctS*ClB%xPBUbfq~dd9k=#%+SM0t%rq=0zZ
z)=r#NZ-JLXdjm~u8?!xI1#hGqy!$zDc^?;i<5_ycqz}K*<@{&RLm^|sA9~B-;rFM=
zAvhslzM%_Kq>I9{v)SA-VTQ!nW5N3R>eC#h>iQkStc)hlebG_);g25
z4<$K#ocv@4?^*hbiCXlQBXYn0>W!;m){&_XD$=K<+yk7yrutXU()}rv^fwpO1M*&H#JXdr0UFM|w
zTe`W*#`5Su-xMR$a;~6`uKb@tUsHRcHBlss)+_x|up8>;pCy}OTY3pgx^jvqP9*~?
zX+7|)+EM4DUPL42>bJ9`Yg>Uamn3DF65UA)fu)rj#C`6TXI;?9
zbFMM@Z$2hB`}i>Pj<45LeCCz=N}T`iZ8v0~YjynZutMa{Z}f}ztHzGYF%<;PtrPo)K_mmRXqWp-nq%V>EOEdJ>#su9i7
zhjPX!y59yb0J@qv#5^+qA*AJOBV;N4TGJuMJ_419`Vu7Bezg1alHFrS>~0^j-zEgD~5ghyz;;*^?WX*4`nt;Q4!m`52)m7
zBTpkN#9Ow)<9^27O|n}GB6_Ym?6Cm1%F)KlSG~P#kUf#)z-|WrxTjh54{_I`hp8+ueohwT8ZJPX^ks%?aV8P`%)Ep_W=E2V_DKQ&|lvmw#y-!7e)DJ?`iW(;*ESSXYNctTGpBF
zf3^K8#fVyU({4N)7KL3ksvk3*ddQD?cphI)>y|KNNMU{&cj4AKg-$7i(;}~TYiww%
zfO;>n9C9l-&XHHy#-ELS8kE+mBbEw$3A)#C%Ydo~+$-QxuIe7ccMr<_Msey07Je_s
zz&zOmH0A$cylTDbcp1R4LZ-UBkLb~su+!sK`IcKk%q6B^%Mu4P`N~trvOhizQ=Zc3
zPE=Z^*Q74hN1GX~$Vn39Kvo~y;qw}@_)_<3$yP71B8$_T+*e*-4?l|1oK?P1Yls=3
z7qC}`1)C1`NI+oj%O1`%vaLGUf#~9jjM`xAB=8zl?y*+C(+p{*24{f1PQ((^-G1h7
z{jKNRtQVOE(o)^SztY!X3+PrQ6cfwUdW69yhHAoDWJqcwAZ>zm8jG|Jus|}3(??6V
zJC%0f)PLxsQ(2N@2sd+l9@VyLNDAue8=|vS_tnK0sn#%5M`QL?oxCiUiJFI(>J6!|
zIS|nL%z9&1j&9YDf2`NumfP#CoR`m)Xi_3z^Mly31~W!Ow7-tCh3@*V$r3lrrImEH
zbV-$pv@g8w0&<%(-SMD5s>cSFWLNR~ux<{c({A|_u7x?wd0)=lY@Z@0I`3Mj;nd%Y
z8(a%hS)NZny^_NT^?dMB?f}(~a8^jdJm}J`J=12jb8ZWIB6s^MlTz|+M%Z@Stc6^@
zZHw}28-5wXS|P2C(g_E&I=ulHp|wq>NojS?&u>f&Px^@4vu~?6;eZxn5>_
z(hRN`t+FRD=aZ2Az)#5jQfEI;Yb57d3Z27r!(bcGXIvsnpmo?|k4zy+gKKGq@+>rM
z(@Q%f`KQP`TtT`7mpwAUQyVEX{LRxC$x%M|uf*D{+qh1%>l(bwuS9a4RyvuTc6+Oie#p;1#)HJ4J60H_Vytjn&&OFsC`A*k;|$EqY6llk~n3zFG3Ll2@iP
zJp-lJa@$}9SH-zRQ?LjA2rm0l$akeac{VD6`pq^)8LSZsf8b
z)fY5&xfY%cFY?*ndstgwsD-I1o9dwcqVMkcQJN0RFEik7ozuiJ__=g1f@lvs6P0b`C=XWU$(
zqw<$Onk=!EIREGWRr_T=yi(vR!Y&gs;P+bC3m*s0^;hd2Rcx7$!wL}PARhIj@_Ou;
z_-))GO~L!aVjhJxHJ+2S%m7N)YqmaQOGwpekL4YQ3`#e-jqZT0t$QK0kIK0_Na9R;
zAIY%{X?Q32&WR-dwcVM=gs1Z~gjvyyz(9X2x`-F4}=h+NF
z_1TnLe`6g6n#D<8hl0NvvIcftsB==}2iR*{yF48`*wMY@O&0Pcm7|wtvk=2YZH!Wu
zkNw}2mGt*g*0A@cjOM2j#jCA*Z12Iksv+4fNtxhRyRB!Oa*Bg9W|jj9BrWFD%#$0+
zVOa;Hcsb0Z?SpwY{Sv!N~?zH+03$o%dOwUxG;qK?(&2H|!l{J3k*60JvuIzE
z!x~w%RStq)%PQ*|v67;^`Xlw1%9ek7Mv*Y8WlMu?773CR@<^t#Ta|C)1m3%qhu#|g
zLa;>v7FB2Z%>B?je5FX75)xK+ro$ec4-`N1b71N{|5S7yBNnefuKJ7MZ(_dvvRgL_
znL}dsbOwYJUCKsC`$^%?usD|IHXW7z!r1{d$J%9>WRd+brQZdQZKF&o@syLP3|
zxE8kdsHK-p`qP>GN#9;9L&;4_$!$F)Tl-SU(7WC&m+aZ+7OcCi?8QE{Y)6FCfV>|_
z(8;T%QtK}j%>4FpxBL}#*0l2Z-5R3GY&oP=vGgSw9b~Yd%ma%5yuC4|*56cqciUpb
z0sKxmRXU}&zEW-WyJI7y4yV54+ZU-W`>T9^TZI^>A
zZ8rLeUsJI$pEsjS=(`sGvRUz*jL%g$fU+w%abHvYAGF^k=6;mRrEW@9?3;8SbjAdQ
z)H+f{O&qL@{84Legz69#x@B>zdj6ub7jYt`Icg6K{WEcgTG(v{KDnnxV!kkhb?heDAIwHIj~QI^@d&>RY6)FB~C{9ypL{rrS(S)S}Wn45Z?oyr+jfk
zkN2A2aP@|fiG+Ou|Fc#;CapBr0DA!-sd5{}+fmvAeu={@8g#g85UPYLQg9
zl_|ZiyL3#jnE89Hr4FZ|Db}U6cM(Fu=|{HtRByJ?l}p?s&6}a~;S`&au>HWtgv|u(
zoz^zP6J!+p+?eSXQxZ<=G@~vZ?3cFatj)X)x_19R_FRYeofVouc+tjSXA4R@Jzj0!
z_A7P~`$|kP;=)Z`P$liD20q}8n&%R%@l3xh;DqeO-QR)ou
zu`(EYfztC*e;wLxzF%6m9nuc?bZ7OuS(`b2
z=&5*Ksf#M}AD5=qhk7vI21^7)f>bFJPcX-Yv_h;kGT))`M;6@>EDO-{vw53&I#2c|
zHmjN6ES||v*(aJ2`|raE2Og-6nPAim5p2_6TmkWJ*y{72(Aiz^6pQ@L=Dc@
zx5}H>@|@o*0o}x5z`khaBM?gwcAvVxtQ3#ZD5^acU>jSgO>uVUQ+QzSTVLd9q_!x(
z-{5KH6DNg}#v%KQdi#Clupe7WHFe?lV9c2KeJ%|XJeoot=SqdsO8Y0BYC6-CG({}*
zz!q^U54!~3c$bFog!m2SO`0X{B(aFO6|ec(M*_u*Z^YTvyKUbFir?-0-OAE(wr)$o
zwj24@%t-nB5-rV9l~btP39BCXlC^eetAmahb(Q?IBP0h$j74R?GuotGF%x##H|O?H
zjinsm;Wy_nQC{~fW)GjE6-w0s(O!x879VV|!gdk%EAF9W4cGYh|97Zf*t_6aLf(q<
z+akMD><#T1BsH)!AW8JyBH8Qp7qQOWy(Fs-u8r_zR;`#YLwmJqyHVyEO8RcH42C5h
z_96Sw_taD7wrzppvn{vMx0QCMZw(Yb7bv=w|HJO|Ey#a~R;;|6&t`w5KAXK6)LY#3
zquQ66VrcPtD;jm(@)cw;;M;5*cwVD-IEsz^>1ut)7)4iUgRu`?eMNW5b
zny1l;-K6-r(?E@@fV>WTi)ty@32*=1+e!=dqDkke-Nw`Y5O;*i>-nb2qh&aDiq1l4
ztZK~+`Ulg|E4$3mjcVCLb3rR#(N}x8n19zga}K_Ll5*XuLtLs_iw>?~C^-vT(eq>X-~L?=_H-)h
zL)?*%^3+yYU$>h>DoYT>C7{bJ0xqHMnRRlXQG}bU+v^5BLLve#mTy(g1hnF*ekQi`
z^Fb~|uK*4&PU1$x)ga)@AqH)jdq4xNt-I2QcOgD4!a}>vGpHZ
z2T|OQz3b`Sp4FJjo~PURwrZnG62`cbJvA+PDf?zk&#a)D?#-76i~=%rKsO*i`XE+?
z@Yc{<=Q=vg1wOgdQfiO1^s)!ofBzHzTgr9|maClnRu#`##qqA7sl01?vMFT3&Meo$
zh0HVK8oW@mfA$!zFp@BcqBDIbBiVtx07yZSzrUd~(z491wqoW-cOO;T;mXT_U8&j+
z=!5MxNHHnjHfc(_8&&gp^Qj-dw}}$(%zj44t)GRZFOQ!
z5wOYcz9#oC#J)#s-0IXkGs(oxUbN%%h|=3`e^#hGTYTo0yo@9YDwnR}si-rj&Q>|C+^a=oDXq)@c{BPe%z_dECzPIo#WagS4B(g1mWjDWLkDE&
z0o{j<`P7n@K__;Xb);_Vwii+`rG=G2gbC8>JU(UyJ@_1$*d=7T>e_T!Dt-9ECf
z1)>{|7|5UA@`C4xvv*jgYZW{1Pd;wR
z2k(8aRX!gtbgx18JF61R*+*?YF*x5TFRf>hmQ5nO1=;Ck&`kl0(N<5~4IxY6
zC-bb)mxTKBK`GAYA4lRWpv;23_pdh`|5YS)FYfWw^U)^yL8yFx16
zsSi{_&P{c?c_Tk)PJ$-ohaq7cI{mNU-h`ok+u6|dI
z*hsxeEmI^SnD;d6j~=j_W+uit*bt@+wHbK62l~okt&Ut;-Ma*QmNW1wQLU-Q6Pe6SD{+1
z*npHO4YnMLiu}IUOd{Cb_x-%@=kxxdb7z>j=RRE5bzkS}B1qH=wXh(6U~fKh02jM?d0EZo*^p`~;qlAt
z4#;@<@!kyqW>Lor!e&8yHJ`~9IKVFDvoXduguTMNCLp(@#RyMIitP^cjl4?UlRR)G
z`^yLWrn;-t`^m2Y%--A7OMwFsn#FUA$?u$2;)z4_UH^t*Kl^)z|0Li0_~g5>Mc~oi
zMpVE}@M!PDrfJqNpH(ynVm4_&UT(zcu$pqUaPYxzfj>kWG!YGEzd!$;vSN-%q7d!h
zaK1LxqK#fhy{e(eW{zWCD-ON^Yo*Pc49TktHkCK)bySNYB?~l?sLKt?Ac$3{Ey4+t
z{Vv@F+@wjzu|7At)~BEJhVTj^G`iO0VwE2=m=7_yn1}Mu81Hgvyor}tF_3x7nw?0WJrU3@p5;#Qe?dQ7;N^b>hQ%|D!@sv+R_RYIit>LC*AbFxwAZiYz=?7{@EC>I$
zgE7XcRVNQA9<);`HQ@Egf0pbE!Tqlw&Xmij!aT1dDth0l)P=X1p-#g;Zb#j!vrV-l
z@&p#|xHe{zrRNwi`#Lx%iY2IE_zcv-L#qMRH=2q2+Pb{THVJjMUUI5ZT#~xbwTufe
z<9Bm{TBYRPaJ=L4)o(A%f`(bkBot;X~Fw0oHrXw^PndKXbqtU=CeW)?7G1
zReJVPc7;c7GrOcGEYN&Z+a@6;lN1wuYg%b%+ozgUzc3%H~QI=iT`QZ
z@_C6sRcQ!k|2PiSF=fw_9as^ZHL|x!DPWoYjvXQ|6ksJ~SeY^A_a{ak>pgB{CH4&T
z0H<{Hq1s(iKWP9~^_e47EePi|GqcP#Ig5F4^x&W;VeCt?tMs5#{9L&*2lxu^CCqMlfZq_J}v(O>#A*5?K~LbTHP9k
zBd+@}dKpz|z_0C6fiuwb(shrV`%OD+f<&1Hc=UkxiwK9d99MQ}^I=*cl04eO5)N4{
z6YPg*_oA0yD@+7-Lh7id)4znGsu<3a%rxTk
zFK~$S530d~_hHSV=u`9a4Pn}2;$MGJ#f}l*{3qnjROnr{oT2=1RL$h!~g
z3D}D(AB14N@hf@d^2MI!C~95Vg}Lcl9zqO2glOR7XbqBs(ys!g;wEhmR530$_S(Vp
zv&(DMbalN{+EF+LplhcEd3D$OsXMgBGA
zFvgV9^GlupyvKy_!|C6sYc{G_ygNrldqMT5Ku__cg6&y2&FBv830-MV=xPFOC%k?p
z|JuROI?a6BzfRXg6zbRCrt#q0vzB+zxBW5vk9!Xi$4K0jXBb)1gz0*4RFNj9#WuA*
ztRPErC9Wn}Ok8zABQ|`h7Ps(f!l?w)pmMk7Z}(8OIZ85%wHH+259`+hN_?u84Mt71
zDhGQp6dJaZ*N0j{`>|ctdt;3iO*J?=(Rx9a+ZB18u=J3{-?Qr80*kqrek~{_jve>j
zzi^kZbwQCbUdmj8yd{uZ%{Y+>g1ISk82E!>Ctf~^Tq8Y#^BM2*d4jxj&T;7Uf?w;>
zBkce!%T%T6+S9hp*ALf?Xpi@I4(w1M?&M8ad1G7D%CAKM@|$BV*=8dm;lNd459l1s
z!nse^9dth8et$$B;R?Ck$hFXVH?1gU&9jRX>Xlu;Gd<}V(Z3i=j#;6AQMVOd)c#2>
z=^dEJdSn%TOb5wI2b{ydN7@muro7+y?Pk;?Mz2icce#Q;zU8N2zjYJryCix$yH*+J
zDd2ItJWfDS9P|hBNa;!=rN7Wfag|5f4$F&C17FdmV#!$yoxAGdA+j1|99C8`|NkPb
z;l8Z<`Z}f&F@|X>F%EfMs<8f5bC5Z>KVo-G@D}XzVY{%PBGw$(x~QZlRpssM{GLu9WQNDR^qxhmt-AgQB@*zP}F*&8a1C}x+b5O)h1}E=)|;D
z&%r*>HA~^YAQ8(vc6BKO{W9*?qGlOg)hyM`mMcdk($&NoAEoOY*4T%xS*-CfHTuF?
zN%T>xR$(WOv6juyb0MOy*(!we8H$cJm+mv!bp?*d3s(S_$(1D4DV3`GotRKQ<;e8I
zDXTDtW4VGshn0$M3AdV|fnrWp+Af(G+r|D2_YGDJtCx~B9kgl+!HVaN^rx_1(C+Av
zP4Qa0hQoe|i-z&yU#9Y6!)-NDW-)gjU-;=TmNI+0JQveKYr>|7JU3nO@aH7X0=>)h
zA_nu~)T#&S_JUu{usdl?O`~!ZX@>M??`EjRQr&CPrzre!h&zrH4meYsLoDLL{OI`K
zL%$rJ67Mn0m;49roPuP78?(ay;ia5`fy
zJ3*zknIG6`nk%xwlNa*?_i6653y8IT;65lCQLaEKdXnwUH2&lxyZ-t^>GtmQS?*C6Atd#as@
z$BAUn4!lL*b(z{sk-}i-$SiR|8zVZ@ko09(%c}?dg7k6PR%X&=ki6d%yGF_GSp
zc1b?#u}6rumFdb8YZ6LyW@OX`Y?inrKScu*m5Fo`PDidS0B=owo%ZwQ$;EW<5ukQK%<;-%rMOknn$PgVDf)i`^>EaW|IDCPr36v
zPCs#88=zW(R2Nu>FEFC+6Q+>=B#r8CV-9B)?@@64S!iSxU1`W80QLQrwM5}O_S+wd
zAC7g`?Y`&|oThfF3`QCwZFK}P>0=$Wx(0tpo6?<%pU#$}!q;A@FL1`Ub|PZ2{2#e=
zPBo3VO?nk--Mx+a_6%xDzen`8fm(UZ$ot}?6PhvRc5AN-wSimfL+ydA(Sx?dX|f7j
z_4P2`l>qH|c^8J-Q73e&aU-Jj?VxrJHJ!d&qu$oj7p7wL_1Z9FLR(O88{z?oqfj!T
zDLbjHw3-$DAI9E<6Sb*#Ah85mR=!0e?`P9nzW}Dxd46N2`o3L?))RZLZok?fAnsoc
zT?k;*r0%7Cg#q+&7uS%!)JwY3=<%z`t^nDq=`yOuhOAG-LG!a0H_f;i)QdKKd1Ewi
zkIr3!IPm|DmN4;qXhXN~3}@0Xy3*kvfFEAdq6t9}!8>P)V;aC2G~d$?=SLJ|@pE&!
zYlYX2`uR#wD=gvsM-I!aS9dia2EG~kQ}IU+6NKl_h;z#EalU$JPmPXx71?e=nF}FD
z-K6gvl69&0T6EhloGF<(B=cvQQ(Sp0lMY(peyx>tJK$SOmJL8>!b*H2v6Zn}-mo+f
zbVo>&$b_n_&Ft22&bN#KB;Txu
zW<{+wze&_*SeAhOIceZqgESZ@b6)@ntT^Sw(R7}Zcr1ZK#fl#
z-Qf_+GhOy3K*a!tPCrANqjUI;JXap{)=x2R&04ivi`=t>AvLXP8A@)_skTl%#Im^_
z(4uZubLGENU_&wiHl&vVHDCM-5feD)k>dm7{~d$eAZi6F_MQk)`2+XqJY{)Qa@k~q
zgG2sJNNf4(_x178D{}Z%LGX?pZ5+s=mK)%8huUWT
z1hDwTU9Y-7&w`hc;j!%3U-qii>XSj5aNjCX1FMAm<@v9YRe}#$CDadCC7SN8a|$sb
zt3=aVpr7E5cXqc)DAo?Lvj$J&IgT(7dWMh5B07zCo(SUX+w~g58^~cQbMkMk0X2w#
z1vL&lHtZDJWcvg`*Os94k-S@hu1)U*`OKynunqwFyhQi2kCG+b9h=2a<_QJ1LQp2d
z*SXLtgicu+A+7#|a*8V%{^X@pewZ1NHEsC9#ENKLv`z_?Fyf*p(zOcA0CukP3kb=gOhblxIuMk}y3intY7PJs*q9$4Yq7kRp9Tu4e$IE{E2
zH}i+Pa5iwhIl4r@an&bb2PDYn6KC$F)ulcZPmV~7;>&U3xH5CvwUD=lvXTRz8k|M^
z49!&@@wYT$+J_TYfJb4lubF$ms?^%auY#2vJ_=;Z4`B{!12}Px%YLh*A9%c4?4t|r
zk>kmrMZ78Ef({mO;IyWTo3hHh)QKzo;J@L-*Y=bU|3%*&S4DPk9c;D6aA-~e+x?`V
z)F}y4-^tn0uzJ#DqJLr=e?P_Hu
z9R10jxEmam%u%zjn!>WEGlQq@n|p(_Z2PigkB6plWh|n@)`7Y!{ANT&vOU-;R-V}M
zBOjD;XvHZqaz&%Fjx6NFnSrwb>~vXSsdklO`CN-=96-dsl=)gZ6ex-~Jk-1kbHtvY
zWmHRy7ys^CVb=!!)lWl^I68(j-o%UU%Sv$`kjmgYG!b6e{YnFCPoGT5+9m0y#r7O+
z3Dg`1U#ma}W$szL_Vnq|vWGnRn&^MWk4U^uxRnIRRq!fM;Vy!{ECw7YXb@!%Qr@O_
zJMStql57OZ(@{QpvY~kRQnDX;Qb@yI@X%lvJnz2^Y1v;qf554)EPxdsvnnjW|9cLk
zI7Mb|By2{BcbJp#9%zStWf+$S%F(WZB^V78ShQ_c@%iVqs
zkDRSf%;3|&p28aDPaoDII18v-4
zKKSgO%{;KGQ&T8IH@CzF`-;dWD)8&~WNSiG#2N!6QjCPf+Y_&RF0atUjzZ;{xHq)6Ni6h*1%wy0
z4>uj5(M7mqSg6mvr`60THsKL-<1wNS=1ZCqpMHphkkdv;i{Y
zM#zxRcdH6M*!3ND4PJ#G_HprRK&sPNN
zN@tvT@dVk>C!E^1DjxV~2rsxGnO*6Ge?y&tnlJAF18X+j7WI>LCyA>EPjiM7dy$1N
zgmI(ZGXUcv1#y-`;}TYxw!uqI#;&&^GtsI~JXssWshZ2RgfF66$DpbVxO{@QKA+n>
z@K8c^hB(sqbfh*6#A+KogLKe5;7tWSZ$g7jJ2>JlG!Qa&?WME3=5o_#6wUM~;nsdZ
z~Xncxp=X%@fBS05rv^rIz$|IwDaq&vb%Q}bm&
zzD`VBL;Gn4UA+85UJ&x<8CPM{MuxCyylZArg^-Z$SG6=PEmm+OvMRXuHJ96Ir113O
zsOF5wwjm2&nunT+LId?76F{_Lj14?bHVKYO*b>sf{C
zgPlj_sRwS5zb^aL<{Wp!XO*4|>3vpa${w{fBfcoedhM25b2w9wl%4Ei04uo`@FMml{0BK&x0jPZcU71tNBF(Ji%29j~
zYesy6StPW;HoBLvx9RFXlPGEjJ<0dMDarfM6xGR^hi_HhZT}bPcWCrV9?C9haYDKB
zt@$pREBX167qN7ldfc=ZJtB_r-))7o6FcRvfAkA$zECt6-o<#nV1IgSF=a8}z
z<=3*2D>G2jyCB(4<1=Q%rc`rz`=Ai~@7@ht9_CXsVplfV@_tc%UH-r}bvN|6Zay70
zs}{rr!6R1{IP>OtH($XdSqwO{17|k=%grY!zo7B`;vC@ttxcc&?E7nqU5%IJ;kUZa
z6j}w0{O-hjF^;gVamboEf_ixjqc*VSMriFZ
zUN=S{Q&-tG*z|nOmEb&;z8!z<-nS(8{pH$!@0+!h$USda$C_K@o@cy+p1~K9)r3~?
zqf2DZ3t93=cLM2cm2CG~0KK5RqWSankZ6Wj%!i@JA|7xxG+MHi^CGmCrO<>)uCqs>
z)sp48ZLXd7fOv}
z+^JxUo0?TJ&vxdeLi%R1L?;8X_o@P!qw?sREUZ!v@;-xA3L34Z)&K0$5A=gRE2RBb
zG!qlbv*mMI?A*Z&0cEem8{TA=O2@4C=?i$CgGtI!V9=?U4I*8xMnSWD1Enq?>9
z>zaxp+86n+EOI9h=|$hv*18C#hEs3h!Kvn6CnSM2CPski1PY68t|2}-&(ubc^SY^S$L
zLW#T^J7G~U@GnrMK={W5G8Y}P30CN$Utq>Dkh>t6DC4Mqf+TH{y2wL_Djnfz=zwU2
z6v$7mbU_N`=aLS0C}P3)L&HPaW1oV2-0wsnGf<~Mh{
zbO3U^(AvPeWI=%MzB9fTalYZn*fH1=D1L}+<0*s-#|yA~t1DwkPZ8b{wmjYDb28S`
z279SW;a)piNlVkXQPI$J=dG+VXZ845I@O>n2y6eDxZ@;2Ikj^9!v$IsqY8dlndA4+
zij0Gtc4Z@U!z8OUy;8Sbnn2d3nwv)+$Vuag<$+w^-bw^;MH@#a
zI&_N4d8mKjo2UN&{pN}b4}Oy{C3FHJ2Mx^@dSK-2!s>9a3V7u!&5nN4?C46fqbtph
zt~5KkN{rR)r509<)`sQ^nz9|bf%{PbeX8k1SLUt6-4R@q4pP?r&w&n7UI*cha*923
zEO?4J>NTM=E626dPbV32Iz^Dj9C>lL+v3A^`$ArvicTpLykB6ia*FM`oI`ranwuL)
z%eM;@YR|@@X0l;G6PdaAqtMwT$Y+!60a0`LRETmZ=M1fu;sHQhVYWrK`v2I<#AC$p
z2WZlxPI-)v6J#w~uWHyTfJvs9)4{+0NOjCX-9c{*b{`<%<&p1{ZI8Ad~
zf_DF!)ud$vZQ62FGF5T3}y4zX2J)I*(Sh43=t#PVfbAbVY)JEc+?EEnx6s%(f`Y>ZHgz~BsYB5y*jn*
zpJeO}pN4_yJq@{Yn2cQGV=c(i=Im+g)e?@?V-Q&=^RWtt7FlQbTWgfEgY#>9X;K|N
zc;0Cvbb|Qabx`^Z;-9}~xO~(k
z8>3~!Y^s=ovoH!zs{QZ#?qY;dRB5B-%6lbs#r#~VFYLtlDKd=KBanIe9p(E23%(wk
zlEsx(gR@t8ybP*I%8*rm$yP3;U__g*!}4ilkPjZ*&Zxs(aLEhCmGvpGsv$3gLO~T<
z<%Cm|#Hi3^2
zb38pc*js@Qck5LZYP#gSW
zup{u1^9QPLFSq#Ls=A#s&)?8`8~&ZhxfZlPU&C)pEj*6>H>-cKStc?5@98=R_AhLn@$QVLg@v|i=j!Pg(~}pTx+P`U(r+>GTB@<*z@E7sgBXIW(&ucL
z!6nI?rKY+#nW(797<1q?f$?m!8MBm@(WZt?nA&RG^{!M}M!I5*Mv1PI7_WSV#nX{ZH{GdLZBPiTZAD*-|lB$g|
z6Y>Zi+as*zxd&7E;Vfk3SU{L0od;~_(f_LU;{E2O2g&w9)@O=kn{X<=2XI%t<1_4w
zyqo*YVt5-_YE;cBoWLVzSV2~WS*)o?R4MH*==S;hd)u321KOvKBL&isMrEHm%WT3e
ztkrgp?V>gu8C9X(-E2-g2_1BK?0dst&C19PoEdASr`_>$nUU*^(f#$X2a@eN0#@H}
z$lpEMkbPJUA2`IX*=66nCE1s{Ly7_=ew&W+`5#{M5%RGAhk5ni^Z$NcqkR89ujL23
z=C$IVUGs8aUeE9R5A!^ArSh~W-(y7{v`
zktXqfcEC%HGea|%$oB^{_3w(o`O|dx!9r_B`>_id|FjYQjY0>!m#?EnTtAzTg#G+#
zoiQ^j0`-oH<%lzR@04dzS%n#5ZY(hHNfZaOUF^v}%9+tdEf0Fv%d(79yFt6la~Rn3
z2_v~~`3YYn*XE-Jeh9(O`>0XZi|*}r!Q;SO3b;Ct`;mvm80Eep{5pB)ScJZ4=oLg_pH}xEO1iI~>
z2w$Q??c8{C(rAk^!n#og>2-|bPHDnPn^2-kmN-iiqt6wRJaYb!0lBC~+BfsRX~)LF
z2kOcql(I@qHb>
zuUqgkYHZ~Fg-HedcRPNAYRdKc4O(zp5p*h%EZY`AXEM&nn6_};T&sBykMq?b36*)q
z%yxJQ62>`?yW6u4ANZt)&2pt!o3M;Ca>P+S`NgLblP9g8q?y*5J};vx!!q{MvB~4sk7Lbq
zL1%2j@D$~o_Ok6MpLNn`4SX(VEtcc&wTC&sRNsuaAGP0F-)yTibN=k`W`k=oYb%?J
z2s}he+!Mj^(AeFpWXeEMkG^$~YqO9&JxCdRL>aCTWkCEiC<9@=50rth-3Q8mEB50(
z>V*|@TzP)Z_dC#lYbu+=q|gA=36g1mZw^bi2pxlfkkL!r$r07l5>?T|f1FqwJ;5x=4<2uIabXigJ
zpp=34`K&`7#;|Rw$C>|zXWpT0{y4t2GS3MN#CZ=-YwYYe)p;cn#l(0uIo#vHc$7Jy
z6z)eB!h4>+mBmzUqzE)n3l`sFW{g7|+QgBSGbW8Z0Xc&+K16@(!FlCtf6f?%-xSM&
z)$KiLBq-VMIC=iUB#!1wqvfVHB-*A_B)WZC)>R}#(>zcy`%!Mn?nF>Il`#Upr=~y3
zP1QYWOgO6og~RU!kAm8%j6F*z{teGNAH}zz+1Rro!E#A5NP3*G`cBYh&THGKH`?xm
z@5F5HM1Z4GaWiUJNt?Rb!37R)dWRGGbDnz8Vu$Z%iq+H)3m;+JbR(?51NJ_l(Ba^W
zn{R|6T8cGjQq)IsXybiqH=q;WXnw96zT)Hw6rv&@oipH$)eOzV;cuL~=`BX#
z4c)*DFMgq?mF?g=(^-SGfDtppBZwwWg01-Y4O%k;bdjJwc!uEJ>AL81^XqU1+yG^#
zzYYR-=ya7Fb@P-D!u37P)wqcwP}C~pX1exQ8Q;ehYYQ4dk+Mtr-1BFKe?{H_-Nzd6
zot3G9F~-c|MCHg!Ah6`+J2StcT!zLq`mk$Y8JlIOTSI7d%#j_(EM=xk?(6iY7pzOs_-MIKOn$c=nq$Xs
z;EmiGcm*Q9N^HCUNlggjgkfxCJ)TwjbA0!B#2AXmW~uxo9x{~QpzTzCX_;$?ID+ga
z_bsTDzRO`jiZwsb^W6)K;q~e$F${6X)bG1g^J!%!^*uT!#i1#;S>gc&gC+3hfofH-
zzYY&i9DiBFNc(^>wqrOu9bugO{s#Dgq4qT7S`|D-nKEL{;qQNA#6B8Me1vq0
z@pR{JuOs%_r%Dv^zTF|+(p8bQaV&8Y*w-|mo<=|UgoTops-l(^_wc3faqT*lS2VD*S
zMn~}XyyhT`X{({t>dSd>=D%0pSDEFCFT1Z(g^Z_-MO`y4S9gs#kfqGnaSlYgFXhI!
zd9+FLjG?IsEGaGujaYd<8#Dg&{`<6l7;mP+U#d6Jdns9$$8cq(&~mJlwH);8y!^|^
zBHk91YsG=?@u~tfRhIClSfXKL~^6YG@7cHY|2hnz~{8zLQ^BerDQ4M|%zd~Oc^={Xf
zP{)twSyu4Kz65rbw@}8pKAS^3Ls~|~ldjAXiKx;rAj_W>Vf6(h?QX|1j11Pknwhh2919yCaR5J&?*(k>?8Yl|)_
zUxW6y>C48@x3**|dlKDrAS)rk5_|;&hTc)ej_%?
z(Y&)FAD|}C`(?jzaX+lxWcMXqIijqbHpq;aS!0n}>3IjFz0$q~S$RHW{A+r7)d4f$
z`I@rEk(Ey9utZc5LA=mKw|0q2zplBj@^!0_A;a;>PeRzD;7J9l7QeA{`Y}cCNqRE!
zq8jW9e)p#$Rk|=;`WzVW#Qy&*K`P_wpVfU_S2GWohX}J<49*^i9RXH-9xH&GS(wiZ
z61GETuj^~`P3=XonX>LnLblOaPkf~l{Qt=Rg@aV&iS&@6-;TXujyIY8F>wq-v_#b_Ii_9w%uXgL4yH#NFDqA*sRc*aE
zi<%)AeH^8gY8p_nVVS;+xTvx^|J(l$Q?PvzMVQo{2eaXcL&o
z(=8jZHoe?@X+pAu2$Ei~n>R{ocXM;pAhmzP?+`~$qa7cNt)+-FW#?~gyoRrl^?k|_
zB{JZ}QsktD2lSIy_nTPLnj&GmvlgulK~Z;_>((U@|2(U4V=m!-UB1SH
z6+piKKMfK>d+u~y=tLY$I8Is23HrTRRJYr}S0*Iq20q@nkMwzkkVz*<(9HMZ03}wF
zVg4}i%k{lzMEG|0QyrW|hdhGV+ols|4;A4Ic$acmY&Q7~Ew?{|oi@2r>AiG1q=E#+
zhMsY3pL2-GdV@2Wk!Q}ZO#M*IiFDHhX*?q>(GDhtAPiDXQsSn((RZ;%cah<%DY$P&I`$+y>&jr%K
znPV{LiB~UHm}45YO9{d8@N+Sq4Khucc%@Z=$_G!H$OlfE=kFkoHjh!B4V@W*ecjKD
zex*qk_-jkbY|Rru*+0IsF2@}FJsy0?kFpQ=#EwAMdxIsb5D)3ppv{kgRL8l@ZM($x
zF36eTFF%*#`&3%#khK0>g};AoX+}wWJ62QYOyi)-sk)@`^(#w0dg|MAmoI(o)kBXe
z>{})3+BA@cRP9)~42M;)T4F4@W^uhwEoNyLubyOh)I7OiGfx8LpTh(uZoaYC%r;P*
zF$ar;_+~Y%FVHGXJXHUAT8e3dDLlP(+Pvvi(=9Kt=5*+1kgY#L(juZoEm{0M4&L5x
zM#k%@wTKBh{uj%1`B=fBm*?${d!Pn#KBOSKp2m{Qukb
z3qKz`}=>la5W&eRuAYd)~=~JX!ghQKUmFfM2f)2
z!9?RceSvy&syC>e+RAksw8svUzRrz(Ie6HcH3#{dh%OtX-^p>dq{|sxPLZ{=htRO%
zTFQ9k>m;hX18VJRq`f#`rkGorpB%MIS)UNI3vCT++=zdhpvl@mZ!cwIg#-)Pu1J?_
z;AeAzkN?sT3yutwMw*=Z=brfeJ>ZGG1z&kJ^rx^)F{~PM!tegjnq5_ms
z{jTVXjAe0jCrJfOwMHi(-w8d>8hg?eBS^p%Ux)r3*HZ9mx74yNYXRySzpGV~O?Bkg
ziY@h)DsroW%hGuTp9TyHOf25yPvp<*4#B>K+VWvN1Hau|Rv`J+{P}FNvk+Q#c?ME4
z{_^qI%VkB=mXiK-`}tkxD$jK3P;Hg53|GlB)^sro*0qYcK^i+J+>o%4NnPEa<%Ecc
zT*Mx!z|hLyi@Arkt8Qq`Z){>=sCf?y4s
z(wXU-$iLk-^>H?|sx8ob(VcPZV_{w`H2;qfPC~!dlVwP^hVh;yJsVf8eiWKIXxV0r
zdr>k*v#OEjp+i-v&Up#4NW&M{0LSjuCjHC9oh}^f3mJh=Cg43!$P|Iu5JQ&8PYOkfs)YmH>@#{u49qigtSgQpj}1w7-@qZXXUYP
z*BwiXDSIInJG0Ta9W>fbn)e5EZL^-t>8@)7T#&A9)|S%$q-j_5?1~Of8}`B>BNGu(
zcaZe#!+ETvWX+&E7Y{-I^0Dja0Mf;MtUsDp^eesFtbp?c$TGBAzbT=0;sFyzrU4Y9
zo$;>>M{Xo#t(28eG;f@ytQTqD
zYMF*2w{`&Y#!`h>^qtN^||LVDrs23BMf9zm0s;x#?Tta#2}_!U?j6Kq6E2a
z<|FqNT^-0VQ-Z%+n8+gu=8<;&`kj4kW(%Sv_u~|s2QQcX$V_AhW|kmVuIMgD=D69&
zX*ilau%4U3vf{ETIg1uIB}r)~oMph9Aj%R~=()U+gwX?2NSp4CpM$!!Hq!LV8hu}1
z(xc-9vbQqg&1y!>MTO~sLeG(G@?V{lv}33Zyr#krg|kn{Cg8z330_UA$f&ZUg7dBNDPId}(~nJUZ2H#fd*$54$B-
zHWKSv!=PcsDJ{-wLkk`hue516SSu6!;`~+(2agGzu9q%3540WpM~Q_6?6APbEp^6z
zyRlxk06$i@=Q-ReH
z{Pe`^i(QhJVzslCX~4CRr;NeAQ{f<+kKv0a4<#HW+kT$lceXTvmyu&*$P18sAYMG7
z$PsgPaBvwgLjDQTsapWBVU1$VyBlc-i2hy&T
z!ut!ld79(Mb?{PRkbfUA@$Mug8bp~NC-h?cH*0U_SVVZx$sQKyW1B@>RUN(AQehI;
zRYNK
zv`gE8akMM6BgVB_tR?N4aivz?4}zlYGFPGOtn!9pAJrkZMs*ZC1LP5rPlTbZ9`>AG
zvQA4GA9)+#{jKm4X&O}$n*C;Z_BlnKGTFZVUqOE0gTTa(HuCKx3Bji)4%sCpE;={)
ztn$==7nG;Ub_OOspEvD7Qqg`>OpzjI)w@{pW=o8~L9!6_Rj9E{dD~?PBEC-6s*|-B
z-ua(}^goG9?WeY%_)pc#|B47ziS<-qWX=WSg7_%8D%&#=GtLf%#aDrCt2tca_6SU1
z>o<+$T?TC4`Uklc78cmL@uqwatvffkbnve5lVUT(@b-tem-;gzqkqxOf5;X^pgte!
z`z2Ve=Y}I&${$W4+MF|lySAiGzpZk+R?nh*r>Wt$RW9Kl+gwGj_eN9*ujfMV&^PZ?
zf-W=g5fn@~>HMvtF${4bQ>jFX;7u(2t<_a@gE*X=HbNp}*$ThkDIBO&%Be^nYwK
zXc;y9Tq6u`BrqZ%!mwZvtkB@<|B=Cn`f%_nJ(#+qHlZ1JBOvhvpZ-TL<>`efpzaFK
zR=4UgeC?4E+jtY}ZX3_!;;pl6=nZjWJ+!7Zz_i=I|K6nOX{m>;SDiu<{`ecVN)uVR
z-@QGU=9S|TS84k{@cz5?{pI%`z1@$WTLBI7ecRf^&P{s(UoAMlU`y71!WLv1*~zRI
zQ4U^q0IXuGB={0VHzk?Ek6$CqsBm)R1BuDhq%LY`Ct`9~63s>n<_+g99U;s6eHXr@))S
z4+XP{Yl{=(_&CYJ;c1&kog(I5iWB=xi9NY799}NQwaqEud{JwrmUa5L$>4|9_Bq{}
zHqTULvZQ~So}95hLo@cLm;N;4+>B>u9+=6R2jD!>A9VEhZ~EaE{lWRYM}xQO&z2nJ
zW~f@@3Go3DA0c;pVKdhMXk1m*sXzv~}q>q~0`
z%lpAkx%8Z
zm|}LEA+jlIX_1@%O%k9wZN;}w0Q0{|65k)l+l1pu;)WtzZzPH9^Lg2SP~V{%F2JM3
zbE7Y8=Sd<5d+sJj68QBd57+gV{3J2V!x}exl34TdgRHr%$Y73@D>Rr7O8VjY0Y#qr
zjtZkgyKHX}D=avq6Q&)4U**rew382taaEKF=vx8Kkev4#5sQ4-6}ir`F5ua
zIg)H~A;^obmgV}#3$n-)P=Oz^!zeKH2RCP_g?;uD`1_SY7u%mGp=zIpBwE5bVuV@QDw>LKdyS_n$!NqXNe0gOF!TY)Ur%0y(t~cEmQFSce_5Ok&rgYNRoy5wh45
zGOQc;nSkz%Z*%Z@()$`Ry?i6!ah=>YY8v6YO7eMAl(n3LoH@ki#XU~g!S04cY1E?a
zsqJgCd;&b7EYSx38TM(9m+nt3WsSP=kOdp5|CQc|nW%fOR#6?)DfUabM5De!C6~R(
zar6azC<|Dk$*K02MqAAbu?BB$n6j~O)r`>#CHLLiQGr>{uQ$ATC(6GrqKSpv=jKfe
zQAB-5`lpJno;2ZHX)F`pK)REP$8DDMlwRsWwG$_nY%h8Dx++N!J@snhfQRtlxh^Q2
zgbWp%v@hmumH*Bto+tyW31v=Jy(npKO6-Fz7v
ziP(wZ*n_b@@a9FbX7hj@**NX+jo=jjuevrR%N8;PWU5cn*AUC0D^n%gDNE?aZ2g5E
zJ%?KS8~S%fj03m2_M=RrMtwh9Cq->gCErZ=oyOOZ9&qQILA%6O{k_c=SblI9Ht9E&
zzm~lbNc-sP>^bqZcvfBecekSyb&_DUahP_Xs1UmO5#NYQNco)xs#|k)1D9{fVm3k%fGo4n8n(LS{k(
zEVq22l*K5$4ww^2d$R1+Xx(o^&`5E6qhpl6mi-C5PTJyft6W`4VnWrGZlQXR_8|Gp
zq@@*B=c|SY%Jb$w1HPj4x%GWlW-8B&q?%4?sgqk&9(iX6%-b&z_PSzQ`YP{8GZv>s
z9b#eINU)Sx^kZ5wC9VGJI^;g_!H3e?ig3n{mHoh`fab=o{Rfa+l@B5{~GQO`^77_CA2;Fj9GL)
zm&uLy%B`Kai{24ak9x;=6TQprGJ5ll(N6a-;68en+jY2)-W_zmg+}m;7j0zr5HK^L
zB~yQ_CG%O2erhWNE$(|XFE*IBcW4&H4;N(7lS3Wi&*ktjGic%&y{|S?UyY~)Xnm{i
z5r39@+KiL4&{407ufmCbc`$YAwi^Y0C|50zFy&wsVe
zDwr*LUvs8AZWyBU+IU?)#^-b0+vRG0n&tLb%#}+^K?=4UXJHBR6Py
z7V->cij-b_4u25!R9hkSUI5>Ip)*GFsmJ?JD>4Yx;dfov-uA%#Fo%D|HN^
zAMV)hAW5CGP(Lx+1M7|NRHJ5LHO5)px&Ixn{0p*3c|Cp^*U;bE@T;x!z^68GRE>k~M-jDZu_d4P(+$Jj>d4xLEE>FGE*P7;gd27HO;miFyyXOg^93fPf
zR9V5HSzew6{)`q}mX=J{6uH-p_4f$R=7f#5xXN+2%7eXsYKxkD+xxo1I>hBS4NnE=9#Hn)oDUz7Zl~x_WNI4p*TUVkAVhPqjUp)+7d;Yv?
zdBg^t6{ngq=7G2$95Z|`t)`?5XNEzuRL&kD!7@DR8*#mfqdQaq3zAx8KfA0sY3g&~
zK@OOBUcY-%M?ZTo;`(26i)nPbDw$}UdMBQihMvM|*neL+^4QZDG5Y>tsJWkgJFUT~
zh@RlY<}j)|MzsMD$~zH1nCKk9eUC
z1|08s*Rov-i+^+bMaPQtN$0zO8m8AH{LM3jU2`0c%tfiMl}4BVaM>=
zBX<9**D;?S(a(T#W0ZfarrA6KjKe5L+Mkv_%l2ybt0HKn05vqK#HG6`3$jj?50&;g
zqr-MdBt2IiODTUE89GOuA8L+9jw-C(KM7Kq=pi^0TxIQT2T#3h2Q|1kz
z%+JMewltQrJ)6YYo*%+-&yVJ86JFrB39~uwxuu+KjFscYApb2du}#|dXS
zn{bV@nQn1x2Al3GV0!a9@oM<9qAFZ%42w~D!j0dZ)Aze_|RFE_n~Vl*auYJs2mmbYD+`!&z;4nN-(PZ7}Yk63Zs}{
z4UTFyM)d+lH5#KDf>9-5L@^wf!E)9NNU34VUy{ZyPY{vZ(F6GfcIcHZUr}aImRUK$
zGxAi41@y}TiWaS}YGG(yB6{j40)z1j5bFlT96y`0jlIQj<5<^o$Ovw{nn@kM2N~dYu-y0_OzO$)EPRI0?vM6I@KC4r@9@k=uu4(eg!}st6+-Pv
zxW5mPA=I9OwilKzYA?exAFy7zorU`!z(btwuS0t$yu_)!1JCSajXbqK!Tnv3kEvaX
z`@0|~Q~Nyb=fi89+O@c!&lqXme<$oAWMCvPhSi8z_Wd&3C-FDU@#8TzQ>IouALz
z(RvHD4)a;}H?VvpzR48c_>eWcg!bltFsXm}kab_`h5P?t3V(p~HXZHFZ!oC~3t0EX
z1l)gvDQwuy8m6JWc^Q+sU^gpe8a6Ls3Tt6?Iunh%uQG)-TUph3_rDCxyW<~?EcAQv
z>-|W3gkfePle*{-Ygpb9wSD};!w=)G;jOz^iLUzx#xFe55BJ?a{q(^7BjXpA4yF5@
zoe$hUH-2IHv((Ru2k(D3e&Mkf>G^y29(aCX<)6lP%ryM3a(Cg0{~2$1_2($}FTX@B
zPh5D)@b_P$WGy1Ndh%2tE=~4J0B_*FdpF8`=S~z!tnS;lqex5VZf}n=ywM&-{wMCH
zrYQH%KS%jv4_zSI_Oi2e;=D;!lPuFdot8X({dCPstz+kns~Tq+|LJ%gXr1BGtBf6M
zmB!jR!=?XW3jNO!d|V>E>D1Rs|OKAtD|m`?C9f#730!3SD+m*4~Mh8d<4
ze2gLZm`?D47H^miSeR=jsJKK>VIioPPEcVXsJKK>ArMqtS_Y^Gj?DvwM}SCz+P%kLi=rCFSY03`L}_+)CTO0vjKalorU&0z+P&v!!z#yd#Swx
z_tyY>sr?D=uL1T_yA_!BeiK4-)4EMp*QWK#PTZ*n`js9tb`WrB3d>>Z(wV^gY6E5
z|6g{GIA6kaG46F%3a7JV?&rL1^5=AVy2?D@G-N4gWA(jf3KgCD^U$d)(q}(-Dv}==
zd9jw50&5?6TR$1v8MXhBb@#fcRn)JRFljyk4@Mdv-HM4y3%FK@Vx;FBFPqDFM
zkh{_FHDoZCk2kxbR%+{B75J*OOA;{*gnSGL`uA_sn{ap*oB`685<#
zRojylUyTQkn&P2)i;!ij7gJ434)xygh1AY+);ghNrFBe+=<>yy3xA?s3!^$!|7+8`
zr}RzLzN|`p8@;~zGyCX!?x`I6EZ56(1bxj%Uw^~38hz`>#G0Q)TTAV!v1TbutUbn1
zr1w|vEGj}?F+_(fUVGzvSQXb%mBl`tOQ925y!Lp#8=7bF8y|f3CGzHO>Vx&0F|V@Kq-LPVETY^^SNy_|4^$5zvSVMtF)eC(l8%U~*Yn
zO@(3Krxm{ab(-sszzOx&OzN<&v5x+n`S*Sg=%A6umqSw3Tz`0Q7D??g4BXY7oG~uN
z!JD1FyfrgU7!Jlm)1&0><;_=QUqGrDLmrMpsn%sv@ui`Nz%fDMH8C-ou6(aFZXRno
zZE47}=F}hTp-Tiq0`+i0k@h))xBcU{_N33viueDS;b!7D(;6hr*}Fpzi~koyx*ttY!RDIcei{B>Ccg`0kKKL~V8Es5_?W%RVu&bse$(O)dA<^Zdz@*BjR49UW~g5k}94e`3>u
zH3>(PtlQuf%10#}jj;kVUoT@4j_RyVto*A60;3us*#VGe29a}#-2H8a6
zpHI+#wN0j?r}Cieq5m(oqarX{?Pjhy`V_lSz)J66*&7z_A15GY%p>a?fO5Y
zy?I;{SNA_YlVq|G)L_6sr4@;wQg^DY*4hAB0GFb57b`kNYd7WT_V{Ui1d;(mRIpJa
zl~(G8(nSl8=ILTt1FncxTv}9Y#HFZefs>K&+GI312QvrJNMjk&pr3t
zbIv^i$Tyc5!a21c<&Qd@c0US!C}d2}Tq%_l>)1vKMH?Qa)l|%_(%$*l`{Q<;K-_gz
zUCMo;OAcNecQh_~vXeTz;%HU0#sTd~?KF3{>$njy!yrez>(NW275O@zUaqm@8IgNT
z*ew!G2=e3(#*kLF0lW_Il*F7|9CFF~wq*DGdofO;4~eq8CeNxPw({#gDKWf;aqF=o
zU@!Sy|L2=>HUT%Zq4bjP2!)XSHs6QhgNQ}20e7kHLzLkmh|5A~4mD9(HJR(^#i$^dUEqcFgY=u?d
zhNE?Lu)OurxSaS%@2mHucfXloNHgLjDE-4Wt3g}H`@^)HIT2LBu7Ye~=)YB%6~IdR
zj8^i@V<>&y$p$CiqcZ``oPpr%OwL~52s1>W`ht!zBI85w(*DVNh?|PGT6!#!v*69G^nOz4}
zN`$&*nWs(+o%$e;w;my1?iG?xQw@$H>9uosVR#m)2RQreUSR7@0gI`n1bWY9cOugw
z@QJJvAy@l4`mvGr+!024{YHiBO%mI(ypcbvk=!2awgo;-W)x&km|r%hsQU;ACK$2VvHcUN9)DB
zC@U%Lxq7AEO)KuQZM~oc-e;L?8E5@5$GjzxvMcly1qdUd#UnTUC?~Db+iigqtzR7C
zp4#h{+CLCCN#!s{g~t7!FSv?1yAsEP&;nW
z;6q1c_s=@}rfH*AcGdQZQI}YhBcvl?Q|Pblm(f)lIap07HCk%KN#=yr+5rJwwS9W3
zwc+E{+OXMb?SQlZX*-@kuaLk$MMmUvw#C$4J#9KX
zX!|NR=H~l#8cpmLy>n+X;7@=4t8pA1ulA=Tjswu+EPHd6x)Y^}g67X`BHC~GLdbrV
z#Yzw768$#$f1y1bZ?@x+x|LG*XIb}hvh!vgjT3K_QA$m>09){|fYLn|DckDE0Hx!7
z)wjz}yxcc4+SrYL!m&Jah~ujj!yNyrS}9vgyMx;9nxiC?I7&~M`&uY*-)c${Z`SH*
z^FRx2hI(?Jt#0WAT#5CM+|M#^ERW2h$Jx5=QYkfaRW?&a%+Oq$@w1qK&bu78ZfgRD
z=GqZsew3s1#(BE*gUQs+-0vK=H4!SMqe1oUifEIX{?k#q*hxiypr)g1|DbH2rUsNA
zJVm|jD9!qSzP$G;jQJUYCGT3`O@!B8eunM)fSBBb*u@v{E)#knxUByuuUCmK3UByq+UCmEd
z1c)(W=6*2&;{J4ixqpRfFlZX%BxY}$pyA-h2-XexQpMvXj9$6>lcn8q2bfDT
zf8>T`1@Ll$w8jc=3^J=&oKF$y-IIRj3(i!cOD-2Avq@mDkrc1zX1
ziV3GC{{sHCjeK2-h+f}s<#>+Tew#D&QGw#Yx$wQ^P(A$zt^ZLM&JECirth3^d)n*M
zf1W-cusU{vKDf;b_kiOrs7pJQH6^n$|H1)^lp45=eTktiLbvVtcA1L&zI5PnFi9!f
z8f6)KGAKdq7bCU%Wk~vNs5EgB+dm~EIor0{H~BIHTVhUL4ptZkU_Q;-JO1$HV8YdV
zZ0>)`ejE{(Ub}VIX1c8}J&sce+ohk_r4nkHDl&`YKJ?GQC*ikK_$KTP$@>!5qE@Rj
zLx0v;GR4=*=Bj=?M29Z98Rn|5oimm0&P>bY;68wH$!Bgk)55ovineNfZ8e->^Ccpo
zhh5gO(-~1e)k1hPqut9WeK}8cfMT}xQweRC?Vfq>H#--^IUXyVJ>oH99mww3ctpa1g8TlV3~8VpK2U(EcjP6`2SbCX`BKMute_T
z5N9?VcmE)|f6Ia^$+{uNmB!t+;qevmJ>#wf28~l^*RL$S8@h{
zGY#Mvj2^LhdUC(LHJciho$pe&!MpnU7D}BhYqv9ae&b)1{XGqJt06x(V?Ud%p;>Mo
zk!j0llk)gc%C>VdZo;+wC>=?g*w=ofY(f8&oQR2@a-3#tIDwLK(%t;3o@OMLwSBOb
z?%5^6b9$LYzMFHMN#*67KqKQ>Jp
z)-wpOK)QgZMPxvrwpT`=Hhg8EcEDh@wqJ}|8wF0+Q^5`9(w-?}8^q=dCycTksiT_p0Mzad_y{B)>01;sZdrd90l2
z+@e@U_d%&8xh&0eP73HpUqqkQuVDQc|I7U7zgRQdr4O(sq>cVO(SAIHS|+!xp4T%n
ztB;&WQth^}t`dVfM}L1pRy^iWdrrc^esZ$X4Rplp9mAh!_RM&!O_&sK7S>ch18S&`&shT2RI&mmdILr@a>BxyTU3K^I*sT__-RNIfwKe
z)qY<7w!Pd``t>WMUbL+?$qLkofV<`LtDUK{yf09Iq)LN|Jliy!`Hn12b9P8
zw@|}No7{fPWxp%|I^+~Hm+JwanyCg2F4#b%$g#Wor$Jg!L0V90d&LAm>c&W6cI5P-
zAX%s&SwMmq3<=_mTHkElUqhajA_C9T{L@8@n9aqfDlnea2tXKeW&e9w3bQp$!TbN!`F5B)5Mz&AJk?7nG~=
zG?iWKbe7hG{@{-X3Jd@R27m$sK!GYypehLTVCSl7K-bjXyyzs_YFhF~e=i?-sUhv~
zAZh~#h+768H=M#*FHiLgj!kM9g#BeTy%nRI+mMg(Cw%9nBjZmFLJ!b#%fO>C4gIKb
zLjIqIob(F{*g*hV8b&4LgEyz6lj&q{6k0|y40Zjt-;cUTVtz}~s7ULvA1m;$&EE$ccQLwgWh68Ti9c=Q!+7NS_vb-{547Bn2f~
zJhfy!Y%L|bIC7IPp&aZOv8V8)D+>f|#Cm6t%MK0(JEow8WaMrWtXXHsBgKuI(^i5**W3EAsT{yD2=SI&19%%_#`E*H!q&lwgghKYgymFxx16
zNiFd#ywl=9TXrsD2N{zd+s}Gyh(HbNzYx-zxAWuml`pONYxHrOTB?%y%Y~W@TeWh%
z4CB3vKyPQt8R5HY3)VyUpAs94>pp0`)+im&rfx!gn;cHSkzKTr*eFq=K)J2vye>et
zQf65U$XgK
zPt!}SoQYj|J5Yez^?|4U$Ku&W2h#0a^ZUZr<_|EQyM%9>-y;~yy$+1=b!NzpNLq$;=>__MGxzlbP;mTJW=w=9*5@1~&TAT+=*F+fT$8_xb2=
zI`Fx!!aGK(NIi5c#<<0siuZ*d=KE5)sc7Y>zZ@gN2ymsoj9Kt&$&_bJUEtLr>s8uz
zK_uKb6Vfp&%N&>vAgi_piPyPL@mC(5ztNgkAmD2-k#kP`;6@~AgYix&C(Xg5y
zt(BInx)C`>E8zJe!^m?do^ti0&%#11D_vQ8G=2CA<*_WBJ-FB2xG(fRHG%a0r31d+
zr^cgyh~IJA*T2!I&-S2yiRfPq&%1>2N%SmSXZ59SP5}M7c;3aQ;(g)w*}ha4Y93hC
z$@nHE^bzk1f8myU@!D(x6cs!V5?pQHqw~Tw0`2AhM;?Z9h`;(A!N!8`ec0fhMSq>bEU6v#|1wLOhk!R$
z{NHBDq3s=KD?ZPh2&`y}(u9aI0*9)G=Lp8i5nt{J`*Xd#8n|B*kN-2)$oBx3tK;#1
z-D>#($Sq-=*Au&0oL)99`Bx53y>OS`LggQVkDviHpE50;LhM4h-*B3UGe_EV%B0zf
z9hLl|@!lkI{%Wg{Ww5{3P;BZk#5r&~oc#GAV?sna(<#JU^PYt){BQ+{rlh4d;k@-h
zG$ow1!eR;$o7OGkQ$JxCQJRZLR9&*4)gNR>QDMf^QjLm~B-rF^OssnQ3jGNj5#
z>YXe;RgP5ogH#1l6(qGg$EW%s)z6o@QMrlIDtWJmmKR%wANHMa2Bd8`6=jL1>W*if
z+49T2lV4j!<(~Qhhj^Vkc!6TC!f-$7?TM!+j+^%5v;bhw4#|@-@vQ?g-%(W{i2{R_VMxke)%B3=1VheKmh8vb=WV}==ilB!UD!Ooq)5`E&mD|^C
z@w+dVE0bDju8X^1NjtOER&_N)F1NkRfBB@fT`i$*BFDs?6o;K$i>`@Zh%+A&Q7c92Rk^hJ(2@4aE*sX1tFN|`|G&0}OE#>x&H7Luqvyo#
z0`uLUbIsdw#o|pbQ7gOH?85_WABO~#R{o8$AKgZkR)0*HH+B)3HympJ?BgvT+tj@R
zY=Q5pN~_+bI;EFZnW@h{)_y%pMESX&x_;+I?%ym=4MVEgn8$`3^OA5eY)U%vFs>vXB;E2{MF7&`hrJYW72xhGWqR`Aqv_LFymM27R9
z{o}K6`;oQX))ucB=lIN_RwyLy9$n7c8&*(SdKYDH=nT6z{7%BVnEc{hM1IYbmLb1l
z*sbBWVJW4RkzYCN(#UtbE66Y2<>Y%7wGsZ#S|xdw(q}WZe#a>LR^f>0_{ytAXv?TyW%W^hO1Cd|hrJI>~v;ei{~Nu)I;fLM+jU1sbtDTS_c(
zsAI6etASPBTuLkLMr-9L<+lrQ7LFm(3EJs=gA(_u(7@kJW$u-s5%-PJnETQiaa2V&
zb5uq*@zXKg%umzZ#QiFQ%>6Qg#QkG}%>C)05X?P7Z#${6--jDY#Syfv@*1JH2?D(>
zX}5Ds)8f+boI3MAESU-Cb35%Oe1E_Sf#<{0JlM`qB4s_lJO9*qe{p<Vw$#1y++ygY)M}nWIKUV
z44HeCtQ}H{NUj)B<4L)59rxIiw-8Ut^Vj|1g|SrONm+Mo3)bhQ0Z6|Zo+VcRjzQ4t
z{)p)760`BJWQb{lY?s4qJS!1?ukgQ4V;A_pNFi??7ll^&)+e$$scHHb=)!wJ7v2lI
zSa~_4mP1nkUXc!ax9b!|EAbz&!5`yuQ>lx$xu|wZ*V1S?Ob#u~nbKm;FKa2Dmh39d
z3Ksiik(8y-*1T8(&j@%#$f3n4`)7v9u?139R^;cXT|{iamB)^gn&ANgy@|OWCq-VlUkui8vb&j_zdwc|V
z>|z8mOeyjgq%nqQc?)dEq#4Q+{0Qb3!E=QYT~v*z8CLB{nQ@A|@vB2psw!^k|=)AQKodq6S@EV
zb3D&DV3$(Cd4%Tq^OyF2fz=f$dm9FyQ0-jVn9&k!ca02g!|9}HIZ3GU!|B=Kd
zBt7qrCtw5f>cidGmB`7g`{f6M4csDuC_3HoOz^Q1&ojOU74%S%86e<^4MKbZYSNE&w8M&e&Gs*ZS?Z236|<$)0qJeNfI@yaT~Kc1zP
zaneWl2e?P@r_!FrQU+t{+Ldl=;ORP__=JT8KSGJ#(LR2kjOEOitIv1!TV|7
zp1PW076S1jbi(_P5ne)~Q=-Q>rOKf5jY=2nI2+Jo!};{Z8fAmPF?r}I$c-t_Zz8bA
z<7wSS0rt;D7@rM*Sgzt{Cy~>Zls-1C3{Sn>BJ6=GigwRHmYqRG~of#y3m;AZrBl4Xf{KdXCkc7
zsid?72yccQPs*Tx5(DnAK#bco6N%x<$Ef-HF$!^&5zd7*AE#(jo`Ewsup6*vozG+~
zPLb97R+GstcT&r}Z*$YxEGH%8i_H8E+6K}hXGME{S9LURMMErZh)t>0vmJBA3d=j>qF+>$Ac*TJRv1%K#4KjctEES^8Le;()1y${0yFydK#^#B=ziQotsM=
z1+RJoE#x=+W5L3tA+%w^!n_yYC(r15k$tvi712;uKj&GPH%(rSShYAG*Fjpwe8~yc
z!O#d}v1Om54ZqnJ#H(`yYn{7_i>=xAtX;*WxM5ElE~Ao
z%}^;`PyRtk(rFbA^dBf?uh@_sE#-8BO_*t-(yUsF
zefhX#DCRD!FQQ6iMY>U|gjyorCYbB)^y26(!rQ}Fd%^}yAoKIgHDZH_`>*w|zZ|qf
ztWAfURbkErc!S<8vD3{`C6c
zw-1SGJcD$9Lxcp_cNAMRoA0zER_Xx2bD1JqM{lh8(Z9p8Kls*D;>`(^fTPq`F@7J<
zyyV3%i_r-zw#FRvz9)K8QeGCGU86lIg%cc~V0?0NW(T~X!IRqWb=I*CUu;j$9tT|S
z2oFMJj7eBIT4ejOCT9`+Qxkc+Bm6PZ8er7S9Ec7;$r;sum93eTydJSjSZ(5vE!YJWtKQnrXzzA5y|
zHc9g-df930%LLZ?z$j}3=8zAYZyYmkNuVY}%59O6o~DqK!IWPdHq)2sZ1y~U-riZG
zoWV!iPMNW$csZZGIta3Qi_E&5U?`gTC*-d37y(Dr-(q|?YP(Cl4jkbomK5Fd3C;=J
zmE8iwu9p-}p`V+RJSo55P+WrM6n89vyKKhj#iV-kF)x9Vj=r^%Gr6f-_l2^CVXe;L
zY0}falPhw%0^>vmv&)BbFtGvD*v@|Ni7)~@DVZU5cOUuO>u$cMU>Iu7Z
z)%%u%h{a*uVWEUuZ~62I+%b%z@{6bg1L~kd5=swJ7Dw$Fu6)^x-aRX(6HJZp;=7Tj9e(q8-MX-!Yi0pd*Xe3FSLeh6n=#Q$f(poK5{zH=t>
zeO9&bT{Xe?-DTwS3)cK^CDrgH#DY6`q2i8Uf&
z#h3lu80X;UKy!@sg7Cz|3i0EGvYTVjb69Nei4{^)Q-*=l+KvRB71C1y*_j<)`Jq9(
zLB@M@5FVMC9IZM#W2CVLLR-73*dmUwQo`GvjZt_@fMppC&2#sS#azH20`#H;
z4cf+e`A0nbTUP2XIkA#kuajDF^R+65stAnfyOqQ)5gQq3mO09dU!PClgIZEaEldWf
zW!47eGm??w$;hojZu}~TNk@{1!+Xm}bP3-)5zc^LsT0*KH|?^roo-0cAL$K=)fA8r
zqtDQ@A<#a6)6h7>fOgtZY$-7zdR7s5PyPjofTiXEpvQHOQnF~q)zO5SeYohpD#|L}
z?8C+LcDszyMOoZG72Sr`OSh;jAmJeCGkr^rK1*)-(+QgC=#AfR?>q2o&-v~BPNN;)
z6K*_ul6!{rrhU?Rr!CP8-e9R~gm)RE~Dk*Z7
za=mDhvn&reGf2)JdA^)Wav6ntjP>r&GGDu|FA(_VZ&5FJ+uc9*7V28$YgJ6@YPX@T
zjijzwHeX$3IYM2o-M+etU-$Ch$S1vZDHCqNwpzfRD?*6LPh<{qi^cSE%%3bo#pY+*
z<_OI>;6d_gtOLJx%ek@OUzQEl$Q(^RzALsxI=&qURWQAL0U#ewa9ZIur7-;{PjJ-)QlQ~YJ?6w~e47|-qW_nLWi09(S
z7;#??-VRnzXpCJFLeYkuha|Ycn8+i--LEAU=C}BmQCTF_lQiR}WZg5mU_EWvfy0c*G_3Bz<51oGw`(sEd|1>ENqX&9)w=LiHt%YeZ7&J6vy9W*0{h0%hUI07=64oK28r_MLavgWGs-dsj^j~jQdnud`WQsx_yzJ*s!!c$)5p3`4e^17F>rXd@Qi>H1W+xSXe
ztoBPOq7k)yy
z7^lrTFDXePyCfep9qsN&sQCgguh7BE3myw$)Klh21)^c^6%)$!!rM=Q
zJLUFDwBd-fi(f=XegLty7jFKFyhM4zb}UvixD7sR&|*(md3QvolireO`{j!S8cXB^
zx}2GoRYPnf1WTvMKTkjL%CR9etb_?e-9`42C?I$PY^Sw|F=i8tBc>8=mRP~F|&kz4M{m6TU)U#v!xK@TgM$
zj$NLUqKGV3%+Ery@5Y?L?!Ui_pMmA@+ZE=Zsy_7@U2<};k6ZKuw-8lJrj~ESf83Mx
zVD5!hPp!s$LrgvNKWv8q@V=U1)Jj)L2rniYAZ;Xk{2)IOT&~}PnFxPEK}PGe7xRr$
zn389*%g*w>R?ec~Q*!X!!P%o5A6EX>fB
z9&2oU6`}X0u$Eik^er;sH-sYdj$oAW`VtUcM%F!0+XcqZ>h#qujAT;4dkt<*a-TC5
zlrx4~&cPKUV>qmIpVx-YoH~o;;pF(2#}KNMuOhavxURa`y5HM_;qImDLIjj4u|
zm!#ZxFHq7L8qcnm1)~SgF^0Wc!Oe1Izxl=nTx>!F(S0zv&}2pVTr4@frWBkM;dMs<7vg{&Z+^{(g)~KlC?BlI;FO(gLXMvR?tg
z)3o7HIiASy7_TUS7pEtqeD8;Q^qtNiY;SZ8HpMC
zhbewgFsRlp>w_7QBa4JJI%bI~1bssv7IypZvmmLPFbh&r2LAziP@}dLGSpFzzlB{N
z;Bs^x^~WPTo|VcvCnvFHS!Y5ay3y|)Mw_qQdeBS2lP!C~2S4!H=|NrpVWsEilaa?K
z`zStzQQ4sce2Rxh<#BoqjThvFlvq+r`m9H5(UNsul_c}13emS667=+AnTk*(>=#rI
z)750|tN8qM-SuW@fv;WsBS2!F=fI*rvOXS{{XVT|8HO^985}XX_)+CAtDK~z*C
zJ!8dIQEyV1x8-jMYbnuo_-dr6PA;5SuOTPa(w?6iXvEgMVN|bqmSVd!^Jkq-oIIvV
zR@QcuSrAtElm;g#xR2>cWl|f~fmF$eHQI0~b)~(*3EN>l?LzmSMw_wCs0?nCT5E7#
zjChK$_nFjY)P`?`_WI^;OiRHzBasd3{f&ba&TD=5zcvubDRTmH^A2M(4#D~6Y
z#255vc0ux~TI7F)q$-JA`bxT}G3nF&YAY`*$pmgeQaV*NLOvw4Pie?Vg*{_`D3z=M
zkeo7!)KfSE_@71~;A@7g=ARRQJ!sj(@5)JP3{v_?o#sL!XBfi^}(
zO-_W~i{Bxs!jzvwsv@T>4h!&Zv3!%bM`OLWSKN1g^IF855N;KVvS`IJshTrUL@OCK
zJmil8ohF-L-SkUfT>TWzRO+Zj%!9V}*4)r4NH6}^B?Y>~RpnLe{9a-Whx#HSzFekT
z2?;)Bhyx|zoAC46IQE@$RC-m%83vJP=IDj|soR$6$XOAQbXGFV>;+-v1Ke4P+skxw
z^uF&TC!~!NLb~p0a)RbNF(KNEYrUyG*CMI%ckoMWuLPK72Lr2;s~lN`&T96H`^cyR
zvF1J|DleA36eMH0e@QjK1YjJcWW_08o5b7Rr#Xm!+NLYTj*NXm8t9{U_hRWS%?h;C
z`R!@~g*c)!Mc@$kl~DqYE>xNOnke(Yag=zwjEWZH&W*24RB7fdy7XBsy~a^0cE^;8
z_UK9nO{Jov5uqykcue%tf9XoI=jo#5!8-Pxn-pEhX3F5VC4+Cbi4uC&%U((iq)D4(
ztksH3Kah4yolUekTtbyvM$zIZ8Ez3W_fk;iC=*VU%5}?gOBn-QYF7`W%s%V_oYrpKu
zXuqzMXu~ei+OYe`*O~ricYW;V2sb-5_CzJQS2fv0r~|g$JmnA#5uqw~%imf~?G7}#
z9XHM;o7}68pUc=iHSR>^-ZC=x1$n$f=Osln5OIWDtPY8U*V@+>JCo!WYZ;ZZD`$kw
zqg!_{bZT12sC@MzMZ2pUmLrT_3=1PyH8_e3)*|^8?kA+}8)=E;p1#!iDs2nAqeC7_
zf3(*gZ4}uj>!2C6Kq{zTqK3spsl=hnFwyZN4`>HSm;mfHs6CPcx_WK6gzQ$N9^HpE
z48EccJb&++oTU{@qthvX83F
zMf<376X_$?%n!`ad%#u}XXOQ0BMQn%Dcm}N+;`*h_wyyUkdpT_A64Cr<@VEv#ye4J
z-Opyt6T6pxaLYG8*0aQF77*mKwY1iUF;A$=?WXOOAL6P?g#DmNwT
z*gvlO3mAQUspdnpqx^k_1HX3L7t@(UdMnB6&DnI_-|nxc=Aw7?b3!K)D#@=xPv^u>
z6c_nX=ebf%F{KRJEIFC04EjQ%ExZkk*UvC-QR04b=t(CYog5rj>O9WJpHYU~j-7N(
zfHhz%^uK)DPfrxu{(XYENQrp*B}t7_h>Zi`SGYOPbVny}vd!Gpgwki*C}l`ntWvX0
zHz!dvt;3#n1aD0%)Tn$(sB!;Tf|a+N1#y~>2*#Iv)MzS*Bj3&v?K9u{=rKZG<><})
zx-+guz}?;t2^Pp%H{sxfcSl(r?*d1bS0QB)iXf|zKyAWU75yy~v=>@cpmTx#6yTnF
zMVkLXyMBJgowb_x@g$8*3yyW*34DIxvRDqW%1a$ZJpK;mYI|Lhz;_&P#gc-`;7U-g
ziPV!(TcEoe$9c%Jb^lr&G#XZ0ECiIl_eCJx-DnKbv
z_NjJ4tEpuqB{+^V;hx8bpe%m=n=&uF&rh&80J%Nq^*J;Z&W*?F-!jr&kaJ)7nwW~+
zo~r(N4e+6sY)U1x-!ek;9^M#c9wb`d^L)&d;T_+1JV$6&s%S
zYfn~l3G`N+MEno}%be%w#eo5P(34*X_gWl?80%;u^(K$Cjj|*%SH5x627;~SRYLu>
zPpysndtAW&wQ;NBd}E&PCS(5BHt4)=95jTR8_Eje$lT!J3TsOwb76SeZKjTP+jDFNm$YVjOpp%WV`1T2p3)@h7@^~*7ev1&z<
zA8WlWHE*k>>MZOs1$N+iv7|h?ym4aao`R{N^*`uCtAB`3-g9@%zs4jV2tHu$t)y6+
zL!y;dQ!JCEST&W{GP3!-8LUc>yCH?AyF2y9EuX#hwO37_k+@I`}6lY_F%*_@apI}V~&i89Xo*w
z=XYadBrytwcd3Gj`Bhr!CVp(K7ksP3keUHFJ6`|O5aR~Jx6VdGW5ubR%WKI>F0G5T
zu>NvNEl!s{Q8Q#5+xhJWns8rf-|vr0wS9uc*7%L0U|C80NDBVW?U-LU^(8YsoVS8n
zlr|3XfI0}W0B#rSSUn?;46zR2Wr81Vkh{kZuOOPqbSdQaq$o?!!KkIDv!`bt%SuG7
z1IfvaB1VecV#|VCeEo>(_3u&DeY
zS%f)gx$!u6WaX01B;pd;nWq1P{$uJyfdg*2Zqr;K9KQC3Zd+~WL~E@egXlgYREV2g
zp9+mzr6U}bU795q%FGQdh!taP#wuRP><0&vwfW3U(l$S#xlIM_EId$m15dL;1MZ!h?s*=5<14lYY%H~7s8yskU2
z{FVT%Of7K##bxO_#ly3yZ(HD7k8ojE8<~+~odgDRQEeA1znYL!H3D1th}BNQ*B3eI
zX7cNez{qo2NvBX9qWnCN5kd)e%5j$7GVrTVT?ZwChkOxomXszZHDpJ-DD5>WN$xKv
zd{tB<+T)?VtdBJWRSeP72XO0`6z6xQ2}ZVa#|e#(9(})8r5z-(B8c%?(VG*cK8COi|z`TM%*DDgGF~bdcL4#{W>x>
z;s{RUOTR#eRtPz3?-o=L%`lO#AFT6jgkzI6o|BQ)UN~dc7DC?VYd5vxl>btze{s%`
z9Pe7;!I?aw4tjarp2dMmjYXm~{jQJZ9Eion7?rDwr2+e)JO8qHmEF+`-aLq}hi`*J
z(r!8coq2O=bwP}EzXCQcXSNluQm$SlA?ZR|bEPk>$JR&F;4^%Uqy?bdtS$eR)`GO!
zPDoq7sdyFJ#Sik}ZZS
z>2y_vHtZsLeUsO#2%|dhM1CzST?y^=Y-;eV^D@99j0U&uEQxrk
zq6U$ZmJ%I@^YH~uFW&IY3uf=bxi@b)i_=(XO^F5Cm!}s`QUBcBFhg1ue^!f$IVJogL%vOT9P8}ePMq=Twul23ZE1*Z_R&_LOQf$Ldn`H
z(iV7NZE!_0#&M{N&0wTLd$m=8aU>P@2dvE4N3fO$spj2SPWo=8hL@%1R-5}ssa0|2
znz_>Db$M}|Q7e{8v4=Y3Yd_B`1$`7NNI}E64hVeXAl}MQi(k$#x+SmO6)-dRJMq_2
z$~=If#99NzF0G^4^UwgmR+=-8bw;mvP3Qif&g~?RDz;P_9P`NApoG2Bo3jNI9#TYX73ttU8NaR~7lbIfIkk@wcdy7q(pclvsWamG1($UGV
zBu+an2^`DrK~Ht{lVN8rTDc_$>o?w#xnbTHmm4?baQuf{{D%Ro=d>~V=rqt4{XX{+0roz
zQS=76L>UeTP@38PA=e2aio|V7*=?rLs0%=)tK8j#ojWmUHuz-D+^-PPK%Uw|VX61nUU3
z!azk?pbe$!-)0WRPZa1wEvwBVGcqua%*cIQ1GJQcPlytft2aq_yJTwNJRdZ^nVh{`
z<(!MaS73hfsq>P3^W*Vdg6|#~
za-R~B_(}W|pUnSujW8Qc77OZz{*_{Yy*7z@^|O?RN{TY}y|O{ZdZbg!@$8Pp-bNOxgtP##l-`rIW}Ud60@)^>)@VVo@+CPf7lFZ{ifV
z(X7*Qkvnk2ojDVQhzhV9~c>D%qOW6N8E?RD2
zvv*M|4Xk6Agk5n?GUzY^Y@HK5ZfoJA#XpWbH-3EXbB8ZI=w6L+uE;a2CO0@7>g0C
zG@A@k1?->}5j7Y~ku0?5$hSxj{2pPGJ|e!*8#X*I^$Lm5-|o
zhyEbwAnz!)YseiPvHfWYPtzepiQm3W*iCjCy)sdexKu|QaXVLi`+=Dam8Lm*wp=Dnjwic!
zXxpiUq}HvZM)vhqRVCi*JwB(@*|DI5G#B>$bPMMBMle$t_ScPE^ESgE`?HBO%1
zLXH=IChv&hvASYsR1Mxw4lxLLaj*HnL;9g^>rM5qy0wnUt!%f|w8E6gFeTyCOf;RkC
zEu;|7l@e8oK<~fr-C*h(Kg77$1g!!r^xAdwm>Vh^Osq
zS)loC@DWmHXx!KtA_p}9@}arFv@FSXI>=d7igAir#>Z5MCJZWkBTw!5D=
ze%~(38Wp`0QnOULxS*m`-b|5QsCGjT-x|DqWkVdRs!mi9eGFL%L^aoXCk;XyrcS2i
zHr&hmKx%f#h!od*(r#Oat_RliH=Z_XzPV8%;8%JlFE)R5pRSGqpzZDo8{Tg=N8)URP8~*5pGQ=H5RIug_D+`S7IgEcE4Y`->tqESDvyM~o
zl}D>I{CXg}@m*GMocrzC`{Ip8Dn7P!#a!rvkBOtjTPRjO4>hvp8Y&M^tuAAiU!v^91ss$})F8ip5j40OdKUdchOh!v~
z^0!1los3+ItU
zpXY0Z=k#5*pI;Rtj?}l?WfJcil6}4edrG12ZTAnv
zMsv7z(Oe`cy75V`gU<&KPtMd
zFCA1X?k#B_T+3$5M9?#|^f&=qoTl})zS&7MNU&ex&$yef`7q%7C73O{oRN6TdF4Uc
zwklH3`k#t(45!oyx7wo@4X0y5B6-Z;Im6D)7l|YNps`A9hm8oN)Ws`ey5amO?D;BE
z+nEaq4|EsAiiD)Bt2pKKuJQGdoi@w^>Xm|W@fWV41FLpre{+eEPK~qG)){wk%(xM2zum7ixr}yc8)g4{
z8&&a1v>5gjoSYh#T`K!YM{d`x=vMJb>C*GMUD<|XY&Iid?=(vvt#xe$sq;sU)Jp0+
z)ut^hqj)HaW&EC6yGiC^m2#0&Mx~PxhhDWZGo6)o7IJ+qtMp-)FST7(&i`(cmHWQ4
zlFsNy*#rJ!mvPkMDajSVu4GpzHkb`279GieRLpxzD^wArfy&5Jg$-ZGlvN
zt^I>QD&qpA%T2IGZtF#H_|l77?zZxhCe92>`4mk8MQmGarZ!!E)t=Z)hrLaY6My>$
zdMd-CMk>LOJv)2HcaF8Dkg7c<5pr0t>#%=dp;mebmSMm3wf!&ZkE;F@xP|
zZqx5s(BjtL-FqRu2^QX3Q4GCY&$@flpXzx}#%rXMnlA-CNR!gCk1u62`%0zXAr|e7
z!BhYJJ;wMAZ`-bW!^;1LrP#Tcvt*{1zsT`l3Rxi~Wri1lX8MrR!jhcoW#Ep>qkr2G{&1deQG#P9Z2q`DG%qS
zjaKCLw4_fi(RI`yeA7+p_(tpu$=yigT!Zl9uqo~*Iq$7`zH-tUg^BIlEMZfNMC=pr
z-e_sRMx(_ux719z$QzU3r_JHyEhCCH^ew~=pJ|pXMmwa}7~PgLpmy;88)~NBTY{^9
zGK#$2!Y-rzPX)3}YE?_T6D7tQSR*U-)SjX>Aq&kpD|*BHWl&@H)0pnLIh2Xqmx1f&Yktv^qo
zoAp}l>5{65CX~e7K#o6(D7yyh&?Imk
z*iejG?e9u*`O+8Ef4Fl&eRro*mM%hsH1KIcPYderlw_v&G`usE83d_BMgEi82sS)T
zPZ#;dSA6{Q?sl0@q?ttRgKc7l5dCBGmdteQNymd*jnB-+(^x!>B~PTh;K6IwGZbzE
zln@_r0q4wpLLV=-iVYGf-1{x!F2>~w`GT=M<^4TLq!A)9S;=`xOJNu(SJwOoZspU+
zXiD7M6cc__dMxtDi0Z{trk)BuHPs;62Tc(*VvpFw&`xKy1X8ySHyBf5QxH9>27EdD9^hARE+5PDEP5I`g-ZHzj?@
zM`COV>(P(@UZ@hA^z?EQft*#fNqzk?c);<_ldrxn+#eWYx6s2LhrGZ0BRQ)9bF8ay
zdJdfmxQErq1|3I?vMbbP=W?UF>+u^Kl~*Vi=y*v(1(hIB;S7=q{}upu@Ct`!>;
zr~{)?I>dMjvqSI}k1!QymsnU^b7wZjDGf5=$)6qP6k(p4@$`}twpVOsvmfSpRZ9NMmIUwEmkiTHo_@vLUq6TBcoEizql+Yc1t+
zZp8mfNDDe`2E}BQZA987C*A>H5S@XiPDh|oqMt+_`m|7Ym|~h!cv}DEOz+c+U!~!;
zI(AJfr8+qAAeoO=ll#-w`>Mke4oX^freH;n3b
zu*{co=^b~MRksPvkd&0bgJm{DuZ`n4Mgjjywfl+u`-|Z7EwtD-%|%kRLTX_ENsVz1
zO$$Gm!$lzqM7o4Yl^$|55jlWT2=W}!%{9giH;yPDRVjR_?M%Kvl4m~0tp40IqFNh@
z`{=_)XW1D_;>QW)%bzYT=Teze;jO7NVx#i)3-9UjFL4G$+7sTxL|;;Vd=8Il-QC-|
z*Y(l3Ei9TT)OEs)_-hE8?hEjku)A%H8~+f5MUn>)ibmDgWhyaX47>t=#O`+=hB3Y8
z!!Q;~9)(eN|4|s5+B#sIarJ)(W8rlHM%f(#QP4v$&b#e{u_w6*
zFofy1AB8aN`lAq*|Iq>A^A{h7kVMPs2YxHyeapVAIsx}7zirWzHv3TCu~4yjo223?
zwCHowqDgE}n_%5y~_4zlT0u<
z=MBbNb_5&TCK+zDGd)F+&s6Kq`R4TW`VaAES?gQddt6GvD?L*U@
zjy@Pj`t<+S2kOY9eJF2ZKi(t~PsyM;G76eDoVI;V(+0!~ri9oek79CjG(2S{J_<$p
zwGJqnN%{l=1)&4PGMPlU4L5Y(o+H&+bzAn;)d*3^=QIw;(RPJTvzVqt)mkaxJ~6~1
zc-+1$g&?g`c`vgQ3vmOEw+__YGA2+y9*;y>qW#C3Urli}BD_7|}8e@HptRrD($R?4}4zGj?xsv16Y0yggO_5*c}
z9ASX(xN&CR8m@T~<5$4a?PjFoY|&blJ(GReZUMaEIhM%*;}8+Koy(um5dmu|coS_c
zSro?dL?tD7XWA5n^7>_I_dFNspI`sH>V?iJ^QNAgYM!=l8u>9q+f|~qMdhvY$($1L
z{doBsX!)Xuah6ndeqCfve(m~fL>Fv`C5l}#Iba~Smq=6eWl`nZzim+&tvRXxtUMVg1zL&e!8svOJb=9y}Zr7Jr{oe-i)
zhmL~KgcvY=YpQt!cMo@HG^O$0)WZ2j^dD=yZHdX+OZ|bj#ZLA`32bW%Cg>?@O#Z>!`&@zmapcKEm-SE50BE3ESoiXXf@)v1MOS7EUBAaKADiQw~&ri3!33*X*ws&UJi#ay4n8*CQ+nX!lF(+V=
z?0Dsy9MSXuIiiwsZ7MONM3G}TWqzBZnOel%KU35i;7!}fE512u%5LeD=3`yUZ7R12
z<+>5QT$+P)+?Yypu-N^o9ru!HPa=L0^R2;FFO9FnjjDYVI4TO7Y0He9Zm|)xZWKj3bdAc
zL)1q0f0GL|ucMP1m;G1qg%VkT8D2`gbhPGCwC6;SdMIMUQ;wGwiIx(aU!^@K7VTT`
zdK&Lt({`+;##a`n`E-{}=x2d>C~hdd{lOYJd1N$TZI)n_{6$PI@zsN};h77tt5Jy&
z-V)8janDr?JWKH;s@1J2jYinvrevGF^;3OwAQh?fQK;r&7|)kV?SYWBwFVq(FSQRf
zqg=ov?L$GuP&Od{w`rAHW#b*3R$$lY8;kA3Nv1?T2^uqKG{8m4_4c8UV)e_c=~Wzb
zz0{hW!UXZ)HJJ`Rjjh27-#&vHOJ>0q9Xgxr)Chj6O&8G4-SpCwX3TMRx(WK)bgvQe
z=3VHeL@Fnf&$N+-)XDYt&L@i(>%UGu_3ZK8w%9z1xxCmsjEgv{YIyqOjAOEc2K4Bo
zmQrbt(A)Puf*k_4@Wj2(flY|!*dJqX9QCD?<`NCl+t)k-kBqZQR4%^++2>Mxpt#(4
z(3gY|o&1{2N5x#qEnYs(ei`%quhLwG5rZEQ6HB})+xr7wrYuhN&34ogyeBV9-H#ji
znAG=E{b$`ydNuiC^0Ys&y9T!Bjg}>;-Iak-I|BubzlX5Pr4009Z;gQZc9rHb{CaWd
zJ&f3n+2V|^r<&X}cUt9il>X=o!VVXny|}Ifer%)Cgi+i3l&*oMeYjykYJs=(DU?3;
z87qCtTN)mD+D?|xh>{fI(LSX!AHaH@keM3nCW|}Njkf%Bl8rV!Kk_Ns;Kk7>j7#>o
z(p=)2^!BrQF{MNWK8bUhgU#TOz(3{S9(Rpz4fF$_gl|40}F`Qv@moYbVfR2TbZ^4H03Dy*gig{z}uAks%N
zSOI{wM}Kc*O@Q@M?5xz{K4tCxkUpdAbZ^<0MwI3bM?1n%mXEzxmb_z>#H6JT-&>kj
zn#)^)&E(@czec~IR5*@!!`CB}LQ@DlAfxxt&1W19KS+17PeO0SKujs*wTf(1Hiif*95Uly@l|
zTz>jKf}w4YV2lW5E!hri`&SOlIIK1SWylEh%uCIhHNdwaNvX>J_2van#)VB!RaUU~
zOeNkQnwHA{uQlB_;@e?ABeYSQb%7YYw4sXp?R1LB4y6^usK}9+d!rZC0{S$_lzMZI
zRq2Bfbye4I4_2@txHR{18gWpbWijH+68KO`0RPqB4A~W)B`i|1wnWKw{plO92*0>-
zZfEt4MA?FfdsveRxSoN7Q}=xCEe9In889SuPoMfT;kRF^zrRa)N=eeWh24mUc!ZTu
z!qY*CCLwkB=d?>v4))#7;fC^t_$PlaUfX5jKv)wk9gLeB+>Z4&7sdR*}xo_TjDE|NhQevmL1h
zo;_#&j`8O{MtnSQZp6g}Oj%3MC+x&oZ@iUL8Jh6NDR^*~Y-YkAr{D*=WMQUwoPsBt
zv_jX*pBKjC3=CbUsBr}^7LblG)6^v`rKeAjwGZ24pFbP}ADrdRu}++9Zi6cr(82XU
z8WfQ#oAqnb+~m`UGy?gnWJQ5kk-3Z$`zfz!mH(Zletvhf3V)oM%HFLIj0sII|9*$)
z4E8VXn;V3ukvQF5!Q1aY(@s>=AfIssH=F5DTNt&r+b#ZZMA8xgr^S8q<6?J?aSnLJ
zc^Au9PRuPz=W&l0-Cp|DiCT(NHTTl1=ifL-XGA(Ho;&DTCa5PuV{Ivb=D@pL-aMy33~Kj9G_^vB3|Cc$H_Mvc-Rti
zGVx6ZuSp9E#TtKT{#|{6$octeg?gDNS~W`fW-1+gO(wo&<+U)L*Q5u9Y6UGP{@sE1
zY^Au?4}5yIK;Ql3N{hI*nG+9xtf_Fk&b_gA;^7(2iFu_?*Nn~tF|kZD$)xRigm?g1
zocd$VudYJaWe{uI2lVwUx;|Mo<<}SHX58ayPv?$0+}ikR-XybK(S1PMHHG7kX@xRb
z(_(8E)%#(kwoAj0`=)7`wF7OGb-3f~*9_vDc0M2d$_i;Za`kSUuo-$$qH#0sP#X;u
zQJWFHy=>BW*VxU)m9IJ~RIg+1Ir)W3QSPV68tig(_f9;T^7?(?yI02M53bC5P<$(ohi56}*23<)J%f9O
zXq~rv5nG4aGy`L;43uOJO!tj6-@dfvo?v=!fBuee%Ox}_D8A;{l?PX96^#n9wvHQR
z6Q5IYknKWa@M-%|`}peCwjY0vu!xhDYF#)kIo0&Fwf@y#XcbK|oi7ZN%P#q<
zT;HFw>Zft!S+})u_c>p#*0z|RTDfDVa93nvU`>33q+deKoP^q!}o~>yhkNeXrdxpH4cQo(DUb!B<(oaF0
z*>j-8KVBY*Uj2BE#(l2oS5qtZQ4QZBJl^1#ZoqaKI@s4j!G+aFO-O2BdUpw~WkzeX^FPDCM^up=0
z=f2kdL(T7Yeo`>1V4rRO%84rv=8JxsAlE;B=ymyX&_Q^F()xoweBF;Lp6Xh9X`og}fpoDYNGl-f)Y7hj$|RStNF_ed_28z^x7DN7
z^Ku!K*`0HZi=lDR-YZtOfUXqiU1ALaW`dJAy9_<
z8T1hvDe#&m&dde{X@uXlXvA7;fF^x~%8n@S;_4kirA1O(f`}%isOBb3v}w{KL&Z=(
z3G)g5MBE_xZ-XBtUim=QtT?~$1fq3YF}5FC;^ueD;*z>iqafGuSGm6LTRFTh=$4f_
z5P3+hxeybXFgOY7p0WDLdD4yKyS{e%Z04Hm53P0jk{`y`Q
zD3`O2Mz2hE1aJ8q`3<9YPB!hpTnC?YWpA8qrGbq|gm2WE{%Q#e82rb0xG)~LP2^^s
z{NBu4T)3+hlj>Cy9a>yxPHSc~
zaCTKqr3<4388tW0_VEFYIe3F+Mo4JpfvmwzM!#Q(!Zz=9sa{fr1wa$9ZJuqro5g{F
zes!+6{u-yvg_bJtvD~3CH)ksa&AE_JdV2lWvyjig&)(jfgDH
z(PUUG0p7!OmvFj+3kWx6Xt0yF3m*yPF
zGN^3Rl*YUJ98zgZ&!8`hH?LX-FGv_`*>QLN#s71zb(J}mZ{3n~q=9m6#)x*{*N&N3
zq-uKb&acT18mW9s$cD{dH*JRgC2+}V5r8)|I!zlJI$c5+#Zr=6YXz>!UfW6YExKyq
z3#7@v>lgC)-&{$fLUQN-{n{l2aa9LqEzUhxdS=JzqxC0Foc`+E(Tj(_tNp(E+QA<^
zZ+sU6dFm*e#uBsv-p8hn&7-Jl{FI&-a;EZ0B%8@eavGziYWtVST>UxOkWy$T0W(BR
zmr87IQMiPWGSRWCAcJi3YFEM?9g33FWjhfsj^kDuj=OlM=WX^6n;s6
zjN%hbxka5#ciMl(ExEPf_8N0UZWCgxxKtjM$Tj#k{dVn+OJxv5b;D?s7Q}}@#gdM=
zk*)xwC;Tu{R_u)AU3DScj@$1yqF{
zv?-6yP1;Q;}gDHF>l55j!EXz
zX2b+(`xo@3cNa~p-d!A#n`6m5FgIxyYD=o5nwM0LcYbKO0vp7+I1hAz?*E;;vTb;d|d+xy91F_e0Csz01M|1TKWiQKPGCFstVN@{)FSNmI}Z4gf+YJ0k6o669(*a
z@{2kR6HiRU+I=B=Zc=8YYw1JWnwDR3D;yJeXW=+tDknc%Y4;PI-CR@8tlkLF(U8#b
z@CLVg<(JMhw_OldHXtRvm*T8PScsyJufE|vkt;s8ZXmV5*|N_`qwM_O3g`bA_7x8;
zv8zPq1(cc5TWZPwmgbhAQJyC&M8w$>Cxy$=qp968ad0=}$;mTytK+eHb1dU3<|fha
z;0m18G~Lo%>q_EzXh>t7B`>wmPW`lfUy43;eX43!XVSdnbIIl@`=;opuAi!!_Unt8pz%%F{&&kQU%tP!
z(EskKO5d8(6t^3aX~jL)Ev>kbD$v-*rnZ(7)Ve0Wu6CEOTGjM$*9l;%Vy>l0C7f@X
z+IXfr9ckxa=dbNLgZ@5o5AXPj^4!>5(C0rbY`eU}T9@dEsS)yW&}he%H+WE^VnTM+no32E0ridR4IZhnm|`$jipsgj-yv-cdg
zc;ZD!bx)5vGxps0^OG)_zauElx~T!AIe7WEU!jRd`i0{bQ;yi&(E&YasuSbSPrOKZ
z5e=s8;SIkUSdOvh-VC@uZT5O!8ne+P|1AG*r-^u;9G!=9jKznljGI>;U5f}k$yhUa
z{&zyA5RX6QPSNii-IXRiIko6#JgxjfU_AWm)5SG5M5CUYdOCH|tb5jz%o7T;jda0c
zL|osWlXR`2VJH4QQl4Mq%%+$Ev)i=(IDdaoz`Obf_10L#zwO5jbVAU?wc^GC?p4b1
zp)wR^mSqBZXYxe%#@Y>iYJIf^4Y<>rm
z|BK?fz7dI_vscpEqW1KpFFCvJ(ZC~WLu<+9t3~n9linc=>Pf#)c_ntvg&S^&F8X-l
zORIqfRUXbBUx5A^#49`fi!i^4VWg#aMLlV)B@h1#>ol|jb|niQh3}Lr^qs7QU=L6-
zaL=;TUoq<>eP=!sl$cSS-o#(gBc?^4oC`nMayZOjH7of37Wm=Xe2o*c1=+K?qyf9U
zh$LQm`^Ur6DxGx{1!j3s4Y7K5EfW5V&
zs-uPn9tll|FqfOc5;s|Lj{RytA05lmq+jS6Hvf@x+|YYDFa5`yICaYiF6p(^=!aB=
zCXiN})hzH~iO@bPy2jms-5;xA)0A&3heM0eSCdwmefwKU^G$VvY>HSEh~cS&kF&LI
zyA|VHVTjG6eqMH=pZzp%bW8WZ#B{A*>JlxlPZksiT>DTAH~P2CA`grQOmrxZ~E-_OucAU<@ow
zxDVe3U*U~UmU!EHgW5}Fdsm=rP{-Y5d(`k4+u$30%IEjRF2XH)Oy4#RbT+NnkyTc5Zp1XP3*YX7yp0*c{Pyh%1z*$d1(wVN1GBarQe5NjXwN(=8g})vLgE6*Xj@M-s=bTg7B;V
z5yAvk*QuDm<5UmTA{J8(o6?LJK#ffM_^w
zwj{b>J5O{$e=z45qYUpES+ugpO|70v57CC#&pu8ox9#?Rg@IX@nSO7r=Mqj86L?j*t0C2(eLtFu6U=-@VqEb$F0Lb*SKg>-iRLp7C7_*8?TfJ~uZNhV
zJI+$<6h&IqYDE#=5fg1I`)=9_%J@E_Zz!5JoVopRCAG{6-;-l_T?9`3kxI^3v)fLs
zXiOe_gHp+!Cc=KY=zL<_vS{!c(L6@v(;URz+8#OP5B)`T!sf^fqZabOkg?bi^|^<-
zLn>-pWV&z#sC-3Bi!6W8Ifc?vf%C@sN#s$fyYSLM^`zE%!yMZCB)cQeQ~#QbnGy|b
zt;f{Tc*2h8%N2=vkhEn#$|wiTCdCf%`A77ajGzPx-dd;N<-=__^`7hP2+_uea4wkM
ztu*31q5_tG(5Z;6#p$)}{VV0Bm|S{#z6G%^uEQU2+w+YWd;DI!EarTuV(Wrn*^J=H
zWt4aPcS>{77-=jw>(|}Wnl#N>*mm*zSZMXXNItIG_J8BcXMaC=-IYp~^VcNAx|l_I
z_gAueX5W{-Som@oVIgnIX=NCu{1x*MruL8wKMuNxptX|zKjCeRZ8~Y@doHg>u-#@h
zyHUBg1-YeFh0EEjH|MhN%~ssd-R4WCOBj4{6~W=5RZZgGx?eX!nR8hriVv6|K%>{`gWBD5mi(@e3|jfZW|)3c>dKJ>Y*GyRdh9+8Q@`jp9wdbp?8K{X^2C{=;%`Qv$sC)rRm&OOCN=?X|m}M6J@OgwESz
zuNZmU2e*0*Z@l6ehSZYM9M2um*adj511B(c?brbwx48ehxeg>UXvwARsx>H
zAs*I;MNzL9(B{{M8CyN!ul+$4>RZ9yEYGG<7@kHrOSnjS4}JIY$6;wUJoWQB>xUL@
zXsu}VQ@HYyl(Bg;>^*7ld(8!eTdSQa-q;i5`ZS2EP^>n{w>Q2iqy@z5s^w=>}aJf+$gk`
zJ@rqTxw6N=Jt#Zwygl_aIGn!NAS<2*-5#>mh_MYby{RTmfjzwJ1j>Z}YH`-VroHUs
z(NQMw07E)phe4^pL(l9EqCU(Xf;ZRD$a>!G>VO4^{xs2l-+d9rT!_uq+@|8XmN4-bc@62CJ%^}|EeiJQNIk91`$JoW(h
zYFjzO+nX)oz;@Lrvv|ZIE4GM=cG`~)I~0C6$6r<8w%M;;HarzG$%Vgt59^3}?y-of
zc7=G{!EGTJvJWlmOwgsegW2(1z7|~axuw9=Of~}
z2hL}@otAGax0`OdH=C}wUtCO4mSUZ|opxx5aKes*q#rg45zF`6aQCo$-0@N7QnReS
zCq2gYnp$>7HxRe=1IbqArfj;oz!Ip0My*UY;BkKIfT8@@(=zNDyI0Z7RMyf-=$+~b
zha+uEu5Z}+R!Vs)eOM5R{
z$F%!O7V~W%+~JPU`X;J$4~lX03ImH_7&4qr{LZ-kI`ZzY`6oK5EjG1!3OAw$HH)R)
z_{VjWR@_7$9yky9@bs|5rFMhI1U-SWAirHPwq<9%drAN_Cdj6)kF0>kZ@10o``Wi2
z=2pk%m*)c;eidsJ{jABE{Nq!hcc1qlSK*f@hux)Tp(_U7KgV+zo%dq$LA{+cuxKrW<+Q)O4okmhQo|TmmTCUg@;KPH&9*QzXCH(2U-bq)c9u46he_&QC^z
zJn3a#3|K1@|K!K%`YHPOEMuMtX$@w?bT0qwrgmV^JH$
z-P7mD16R4NSdSYM{~Ug(MN?0$Y1-U^XzyC#
zWlpS#mggkdlS4G%4m3agE>;bf@34zs<4!1TvN||6#{zn+dYRi^f>;!KyHHiBF^#t5
z4;n3q$9HqC^fc(7-ZsXq+s(}?(4^fq+WoRBNd|TD(4(M;<Wp;@v@>Tr>@xfZud7x`$8BNy51&S*t<&sw3r-)zczH
zInF{!KDiR}xb?KXd=|;MvYw|_tu>3McEhUlu`m3vOT%xYc~c@uTd3xI%SQd0Lv}yA
z!c_TTx(IF%9F#>&+{tyPPqfqOWfqGHlOX})e@$!Hv7968%~R5m%oLs4CZk5x1=$H2-l4l8?>ryf5~dN@xg|w
z^a*FO%%|
zM9|y;*->x*X3*QR*_W_J%X+^djQQZ3EXY;vNs|aW3D0>GEnCcI3n!cn^)OC`C>?KsFC@3p;xvEj_Oq-p
z*SNFN&O%zj?3*E@EV*b;kX4-RkfBt&Pijl&NMbmlLvP+#%
zd<@ZGSGVqwIP8*#KW8UjU#p(FQB%3F>?!xcvWLIm0}=fQ(gm{3Xf1ha9riwX2gjF`
zTY6?hm@4*lf|ndppl#^lE0k@9iZOdR<(#oa``1yeWv31rRGuQH9sR-186m@S0&DZ;TPip!zQPAf)Hu0=WA=jJZ`^ztX<;#U7eh4{SnaV
zduzmisH6&B9N?$;#2LZ3@wTU06jPtJZ!lakxa`#&(Z1Ejig;**;pR;XA=}`&L{l;vrT180UZzORQc$5#?+n=YT;?bqp8MybJ*e4)zGNA
zqeWd}o}VIYD)mM275ZYxIT>o~%PD6VrW)18WBd@q$wvP^man*(L7WS2X;
zaTLzf(|fXJU8u~MeBQIkQ+>#I*i<v$f?(I4vltHKi;fn=^b=RKaD;0)
z=E(^Q!5P@i%@`p)to9?S4GB_x$8jd$)lyW}Ik;%Te{cC-F;Lld$%#HC@3Y
zax!w$J!+V7s?i^ER)gUzT9spBwc4|Z&VY}yx*Q2j=i!A?d`{pFL;HqVr<-n3e^35M
zfB$ubdd*gM2qaPP`?e}9ac1HL=!lj@PWXCxHvL-lLOAZH{POqJzE*sc-snlZ)&M_V
zcy`yl#>&pm(*<>LZdF;Ne1};op&48I+Tf$~Mo;3kI>?C4QVCtKFK6z3Idl8u%w;*z
zQwFp4zMQpva@Mk(ki5}8N1QOb{W9gyNc?z%q-^jjfZlM~T1!ihZi7HxmpGc?$~H+d
z*Y?3pqG_-?8VH@C-*KLv(FzCS!7-HDztoL!&>_<+$4d1$8d9nw89O?5JQr)n&C|rZ|9Ez%F?dFTXk-S
zd<^^<&k6y3*2Q+cwy^D~%QPP39S8PcN&E;{@(d_IJJ8}_qT)K2@R}4gLGoM?5(Vs0
z+W)eU3z$mf#zn$XTEV_?I4i6mZ3TIS*Qw(ir3lf2NVQM%SsKPxCuG8mk!|(CLZBE+Zku)X%iSvNv+F
zp(BQk7duU5fR1gl$QuM+nIDXG`em+PE86A7knLuMAyJbT1{j{$@3>MK1V2QV5~cYW
z(KQ3Nz1_6Ck?e!0Nk|B-UdIbziR+9-IFrHl{Wc(DN0s~D2vF|{*HyJ_rnXHDGZg>y_%Om?Hpj}T
zG{=h`Ap)VlGx8Ha$^oF?U3%*d0vfDoYywt7475LD#T$jQeN>h-H>=&qLSO;SM?K{czGx1H&3flz3LsGLEiBR!}#=f3nTpC
z`${o!t-qr0j(W;Mkm&`O{c;l+QwVp^;%zpmSGN^zjB`jFEi7UE2L-Hn@frHqYT
zSE%1Ea9|rdWHb^9khipip0dQj!zA4==bv#(tDbq!r5r;o-IeqkXt@BIvS>7GXS0Uw
zyxVih5~2zoXs`qB6dq6}IW2L6Kj%behgxiL%f$7{el&{m9l4>JvF0H0Pn`p_s@0D(
zD0YGMRvA2|q`)k0K0DxEUX@9FxD%4?MI%|>8cZk$rDg>iXk*Si9_7oi0`(y964i6R-*gwJWen6h6r}
z@tI5_7CH@9g3fm=t`;HS9m&72cR%ZyZYg!-7d3}pvJ^Lg?>GbN(V*_|9d@nK$R$1E
z+Z*09%Aof}>zJ%rLj15g{gVF68ts(gJ%QIipz4jTb!%9z1OWNi$u%x-CTt*
zTJBwczr^R4MY{4V+==(UESB$1f>%a=wKY1A|7?mlLr`xxwBecIfZzvNjc!;smoZyB
zDkx~}Shoug6h&jlcUXSNuX7kln(6c4!fbZRr+m52GzUD&7uM(`Dj(Ag&QkM$ZUla#
zkAXt_am|G~{qO1-kVjghlewzjp0z(7`>}-iv=%5w_e$N4A~idK+_MKNpJJLrG*o{u
zUO9m)k|ejbD-qQ+yYdSP<>y1I=EnoKdO|`cYvP3oO+&iKpPRE?5mxWCgw?OX|1J36
z7enpew${I2!!SzutyTe?+z_dp9!sD!3gg+FYDE8&RW-o|6DQ7)V0=|J
zf8AO?-W^|e_bBb2E=NnUR%rR?{4ur@3X{%%O;0+VFje}E^8WhXhYC~U-Iw+kjinuR
z$5@oz6ZX|-wW)`T039^qgtuKMioomW@`Mwgk8mS@$Y``qu`LPp?FsXM>(q@`PR4Iz
zgi8qKl%_a%wxagvwg{7}mI9|1g&hW+bS!--D>&n@x|&8tO5Z7%rQhw|->v`lyT$wd
zFTs1;MSBkPh!_pREmthKUfhvPD>tPkoqtZ7+tIs5IjU$w!&eQ|U+l3@1s+zKz0Xmi
zq8j)3xrz;!!NbU)hou0&A=4qE27FCo|6!7&dvpcyd_h+-QtbK8lc15oY|Tb(V{3N%
zKI{Y!y9TT-DoYPaW;zQ7J)LN)PfvLxoMbz$4=
zPZI*6G01rM&s4R65#@$>rGZP}x0KRJ#K8He8{;RF_HBt^D?)ZSFqT7Pjhqp7xk1tz%^Z2~N;rM#w(b+SnLR{2_)Gn_EfBWK@hQ0Dyt9TzEV
z<=3j1)KivJgfhUZe|hWqFoA!(1Y-|RrsU<5aZ%*)FV^NHxr%~~xUztaxP1%m6&0Hd
zYktc1kW7Vk8Q*Sj$&h`h!yN`Mmx!HJMbcLqr4WgN)_oL~cm$CwXtdaOT9d%b-5V0M
zrjFia1uML1_im1CyEYi^k7D-piLB%hoQkkFY(A14@(7+Zf3X(f*OmWBG2i;1shTTY
zKxE2^jw*|5hJ!0UxJ4N2aLusbX^r$0jVC9bl-9sQuuM?gHsmM4OWV~vPTT++7;upn
z?a*N4Ja6WQI8}!emltm^Ovk>gs(mt?^`d3-;gi5+PU7Wp!iHZ~iKi!S9&$n4ZZB->
zZDS*zws~M>;gj_*MVzPs2W*Iohoy-HlDoAnhE0i??uoV=(oGF>T4!o)hkKuKnDDH0Gm0^f;I5;shS{`aR
z0Wa?rDrk>}G=TTshqtiAFb}ow-U%#1@*FJw&8ZNFKz~UUFo4x!5?L)ZYch2Noo<}O
zhuRVOLib7gUDV=?PDoyx?U`1o`^0uvS2CKT75O0nwLsS@5%o%EojTnEMqZ~K&Fg|9d0p^Y&@Kh{xI&*BVTUGJee$_qahG@R
zu8(nr|FWY0H-o~9@
zEnC5mkf;ft-aX1F3)|0f%#fP2J@p%t>dfwjB(PbYmdW+^+6mLTR@JV*TGovR&END-H!4D5J>?k^%c(28@i|CIsy`yCK!tEHi#sbac
zJXfln6MGzJVWSU!O$-BtlK{Ljb^3In`%$=*75cdeaK*<4A=khfTBWha@K|x
z4$*7@iSuV8Tw`E)Yu-xGC$HsgbW5n_FM2$
zkplYAHpNej8@T#s$Wln#j2ron-FCm@gx}P@hyRDLmSzd_QFgQP-|?4bf>yTvAnUbu
zmaoSny{pDFmbF9q>Xi`$@!hM`V}my}b2LkhTJZV^=GnLUHT2kFV?BPon`YOy{vKy}
zx6fY|sb3o=@k5%L=&e3Ji0>oMCqLiR2ZnLV=@{v))RTlG@>!YO8jJOL6X$xfdm!$c
zXE`xPMX1L!u!zy4M_4`0e;yJ^Qu^5!sKxc(RMT*ls{HfN$Rf-UbgAdOhZYz2X>p@B
zuU*gb+B0s(vu(GI#0W}vXS~eG(~Phgt>zFN!2G
z4`J)Wv|&%gEH@-;Z6BQ2?Rc?g9r<`+{NF^tUHP%(X99f(3JsB8W=;;8oMP-}WNF){
zK*#6i%#@&%l&SruN)j>&Ml(ssJe94q`X%3%j6OU~`rpuV{e{MqC`Q!ND1T#=nY}5W
zrkcv3vGDNE-gG0Y_oy0v^eb;^UdfQ@Z^?dLHUjmLUbFK`lPN^)RQI&eb1(>up
zg(1v9w_M<(172G6HGV%A_
zI}7ml;XAM6Z{_dMLus4+`x5-^y}b;7Ke(NRzfaxP!kz-@@X5T0%HubM;N8+H!|5Hr
z272$(Dqo`auHh(k8Mma5k_^7>sZO`BCUQgK;HFE7o1rB~GXFIg!_N|nLeLvW-B?X^
zi_!0Ata>kHZoba?*E|Z)u9P|m3ot^G7hyN>p2ojqififBUgGTQ1KFt9udz}!uus4I
zEq0_O?E~44MC)q9>?iX{UR=_j<=)=Ja&J!nH-DBW14*Fv%)^L}8CwL&CG7V&CiTMF
zv+5zQzNV7t^bKloW-_)0efwFmhgzkye1=#g4|gupRcEhPf?XxWnbU9mWdBPT6i-MT0|DD#Ue1^WBAOPLfn_{aMyh?f`5j@<*tKWIftx~l04C*M1yH4<;g$e19WAdZZ(Z-AlN0AJ2#x~Z<
zn}tY$4Q%JYo2#G+&>$aPr$Wsh&A6l`zM7xyQ*-VQtme$GSk2qV09y{Rp46cy0iHkV
z)khBmQ@yklPb6N6Y&#ULsH@!`+i7$e9)24Ma?aq}@cJ6Z-Tv551E
zh5=^=YUjsu@wmg&?P?j|QmNFpp0Ap(UD4G$)Ec)`;NyfMnRS<0!1(ZPB}UCIw7KjZ
z11q{d165T8#HBlA5yFDP7YlD){Nm4_{dtSEqD$bZZQTWIw67N)FZ|*=`EWD$|2M`v
zhOw4M?PD#6jJ)mLkJ(sQ0`42*i0D9IP{9A&7@K1l-0fuy?sj-S>)m+|?tNn%(G@_D
zrO~w&$>Pq~WK}PN?*V2gCSS=C
zMq3_L=ZAb(dqT1bl2+#H_kaaWtxq5lrhg
zi(0p>2zQ8z00~Ywd^jP7g+c-C^Txu@@uZf%8xTe2cPR?T$#^HqML9#|`XixMz2D&c
zy-M%-pg9m4N}ks1lmhD{q_J8v1E81r1H}m0gMFrPC~K24o2AwSKp)^HqIRgi#r^0@
z`XZ%tzW#4-*@t}hg~VY!)=DEvJRSP1AP#^yxz@(ZH^;as;z$nQw+&?wlz(Rs5KIGU
zMk$SpU}>heS(>E#ZhlxveE!;@-fK?!(PZiD3`P8ycVb
z*(W(93o}{?KCL?95VgvYhFIG^`xYthyVt`EGYuOKg&D%CHYH|MK^OTKqJB&dhvg6G
zoBvuEq)r)#kQ#=(PyO6Cuc~%a0{B?NKD*SDN4q`+wAOodv-A{S`XgQCNQZ_VtBWLz
zq)|)1AusrM5MHC~d
zK&fq_?T9$8s-`t&jim!V
zR3+cN8yoIIf6L;sS2Yba=bJmYI0yMN(cvb%skjbl9RB@>boIS-<$N}0mhCQ8(H87+
z8+5B1INf{jc4W@9=yLGvYJq&$&q6oU;@@^6vX4)na&hqxWnA=LN!FJi+-%S~s+#hl
z-<)6P=ElIgnPDI_&18?0pRebx8Mz9|;9%RWX%
zHPbCVQcB%wIn}WTDO0?-}k
z+-hsIVqC&9thOh?bAwORs?~;N
z1=>s{?pd}0n(>LaC7Ild1-b}8i8ewaq~va5#6xJrr7vzZhjY*o8d>RGf{14-OKWLa
z!8EC~Jjy1)lG+qWux(FZrg(2F@x?mK_5^RLxOJYZ_~AUSiwqh^U*hf_#&fmw96x}2
zx#HFjNLPE)tDmU2^$OmRM^E{ypNL;2=PGU;hPE+#XYlT&v+|#@^j!)om5-NmcPf5(
z1-B_dRx7^6bsh#51#ofm1|dFa^>XbuP?czWaBQt@e^an&~ZlC?@ZPo-dQ)yv%u4!-WPRuOmg;ws&aY8oMX
zMdv)wpcxpWGd9Tl?6l6MRk`b`4Y)LNj(1f`xHHnav)W$K9nZUkkzB>~ZfLEH{tx;H
z%vJ~rqtMx4cH2*%z*>fWmXQ6S1>Sr(x^oT*jB)BByH-$K_nRE((m<^P-nT&EwhC9c
zj;{D1Po#YT^iNi}92Z7nB$vC#dLl198!uFO*WII7cb8y&uZwMmN1OTpVE1yg*$U|k
z(GAG%bTRbBmgAhK%~h3k6Rpa|JXsU&(VAhDLxD2fEs54(-nwu@jM{|v6fQ?}5}*@Q
zhZ}TOq5*2G>zMXj>rO?=66sV08d%bv;y#BxX=iOVAn{&mu^u^hbY|NvmpsTl?&e0R
zO}pBkaECkz>6ow@H&NrQJBB?1R^PHxx&Y)?q%xv1!aF@m$XLbj$vXP`Phy#gME64TVB#gIR
z9Z$FfgGM)^Yq=Bi5nqLK%L=zpFN3CGBEGJ$Mmy|8Z5dU^7aPr6R~vLQLssz6ZuB5`_7;NLhG^cou*n{+E5-k9%F$N61!K$g^n~=Rau=Z=
z5e>^-xsJ#Ft?h%jaBFm}o=G>*du2x!j|4&Kw2F-d1NNsma9qC11+mJcO8BBntk4%pc*>us%i@`AA&G*74}
zfNxQVFAIKli`cZ&e>!4e#f7+GKfc?>_;}@;Avg~~Zv6UK+o(KP5y2Rl;Wmvs;WuHo
z9Joz5tyKfJ-@XOh=J_REZsaJ1&aG~numbw$-Qe_dpWgHxl@m
zo_qb6n>^h@E%_2QLQ?&6(6h3Wze6G~z1Pg`o0rlC!t=-HT+;*YU*+jZT+^TG+T`gA
zIPyEldXhPxm294M!OcMu<%wL8s2O7l%L*p$imVW_q0tR3Uv~Zzz4gpqShld84`g4r
z&+)>Ttvb9Yz>h_HL`G`X;N3Q?BSprUnW^^qJt3f-;WP1ky-;Z)d$XBmv3cE5PgM~3?#L>$jE5u2S1o$P?}sV(TEg|^ugdKkbZ@&V?C8=
z3t``+c1U092hkVs$12JfjXjL=EedA&zTN13527CE?RZD)TMZ?Vi*W0-hvLf_47yP!
zm9n)grl1Is@1WuUvQ
zeIb6;FBV!YdvF(h^%W^a#or=1*d(P})hjG1n1x8p+q@}UwyU-iF^BIGmlNLpie|53
zLTh;2JAF^SFD~A3kSvJFs`%MUGcG=V{?F&;o|$+0)%rI;<7v$b5ugTlBnlJW72$nH
zof4H$gG%7*Zkw2^{BL*q51-S|*f;dF^kr
zkrEQ+Uf;X+Os!K{thW<3wU#{C^NGV6r3mZEig8qQ?B&TDZbfqx@nK=s7-JZC#m4cu
zU*DTnN75p83Dx{SlaT_51B|J-+LcIQz?0
z@3dw=|6Oaz``0is;TV1Jd}-j#wuME&({2%B9=USojbAb8t4UNx>uUcNA58h9wlG)T
zoq>SY>Vp@THI0wgJj`LfFSM3CeQGj`hpEUo?>Inr>Nr=6}Pf|*X1ns_>BxuHBwC`EW
z)BQEYNPR+DeJbX|Ta%5|6hk%DKP`P{ee%^LrIbx4X!q45L8}I|MN=?O_t!K+>J!pN
z0;0{=r}w2kji8!FPL{s2KE3bllavx5LA$Re37YYJw9klN4Z?Ri
z#SC(>K5dNqyM>SY(E{pd48goVN$^nDKd^RjHmF$eUq~4pf_1YI_!p1SrP`K(R@_d<
zX=fHFU!*s+Z5*X$Ib8)k@8)cjPOyV!8m=tW=5`IN$Z{j+r#$+ocR9Oyao419EnV76
z`=?cJ)8AaG#n*~E>*0}q6L^5N`V7O+*Vg=n?baEo;2DXdZ?SM0XE3&6{0&ap%LO$k
z(p;;)TCC_Ci?dHIuZul1mvVqlxh19H`6kh=xf!Vvv@@xx6`gwIeTz>$L*E1$!Bj+a
z(>@uIVK}}q!()v;o`6%#@4DC?!{&%o)OGxQ*EKVj>e&)QXI%?Ui~iJ-Oq#a7d%_?)mwc`~2zWC%sVqLPW-U8L}6Dokm_i$Vw1gO^|Ot
zZhF5xm+i-nBlb++j;wVy7cFdi*nzy^+&g%(!fGS@rGG4Jdv|#to;-hF*mgO`4^QEE
zdMbxFRgRB~?~o*vJt3NPEt3)gA5g~BmRsl~Ili{Jm*nWs&VmJaoDy~|$WJK=ffXnv
zSsw>?O`;M!yocOhhWuY?XLTgRnQ%ssZn=n4VBRR=lu-%5m+X3!huk0bQQv=GLZHHl0Ud7+j_|}piZ?h4Yf0yxY
z7h76OV$S2-BA=wpV*G)A8@Q?JaLiZ<&6or;S}_znL;!Jcx?xwt<#?}=?lsw)aVR7V
z*(Q?Hg4hPb6qD?crEOLo1e!31AwEmg;ZY-B7qq-8%6|JjZy}-WJeIRk$*)fM&OZ+QAC+1Wwjf*egdR9S8!~k0H|1tM2P)%KF
z-}pH>NlqXr)Cj0UTTBqtvDPtGoPHLAl0;D}w%!L@G)1PJTD4Pet&C_$0!Ba^6}(l7
z7p%3mV@A{VZ7V1cq~41_9jmqo)XwV!TOpz#|KD>?A~@~zoA>*#^{vmfFz4*Eug~85
z+0TBiDU|jcf52itDj%(VLbW)@8({8FF3d4{oqbM;P$~Z{&WH
zs~Ljw-S*)(G&}y3NTR01U1^TC&LfU=!xb({KHnT=nD5))1$G^)^wiEWW4
zk5hv`FIx;;l{YtM{0Rro^p1OIuhCk$JT{%UF{|71WNFY=0am(voc3+hywK6RQ7jQxu1$Sw+2`_>yk10MMiu*SAoqPY5DC^aZXjzje6SF5W8{09
z)R3yv-32-EUf6^@;+<1mZBjK>TZqHz#SICZ@W|_^IYGdcSm}`>WXjC~mqNgy32MYc
zD1344VPiOMagf)Q`tn#|CBD+G_a=A>S7-RYrun|6;%ojw@oV1w!+Nod#cDqSSzzI!
z4u47mQZ`3<3a7ODQ}j0b5ex1zPu}yV>_y7b2zU^=>rato*^i|5@f3RQ_)}7mGQGE_
z@T}LLQjQdTh^O$wR)5NXZ2OU?g5dqM#h+q93Y{{GZu?UjkV2=-l%M=5`gN9Uy#FYU
zpkW=#-}0YHmUX`J&Hj`Dc3*jqKcyTgbhbVDPk&14da;`@MHKy5U>H+7{oP}&mow-Gor2(zvOuPVovKM&;_
z%md(}4?G5cYB^FrtVa!MF<1Ep`;jBV0H5zjQ$S3!Y?RGgR5;~ZT6cBh@*CSvYKj`)
zshcT06*q3Hn<6|NY}`@s2jS_%#%=vJk=-D<;NI%s0HqyoC1C4KgY!p&IXxxI-Na4AdavS>#
z&%1?^;`4_>NsW;HK0WhMzWjJLiqE@+^k5H7UUy50iA$N2yGY{k$Znte&tbysQ*iva&Z%7XVFK~=`zm?Jc`2_Q{>=x;3
z1#44N8OT4mr8z~ilR3&Ge;g7hbF@6wd@@I~$F+=mVIUJUj@#>A_Pd@vd;Yk2y&k7Q
zhI!U_#(t!H7V_+KEi(^AOCR#fRpv@&**n~TGmLpaF5~>mS&{;eF%Qf|TiVo%?7wMc
zziV00I7c5X!|gRLukf|ttNj3aph4}2Y|FP5aC<8u8O}oQ&xkee&k}0>xBWkezRmih
z*#G5!RpcuCwR10I`TKuJY{7hpU-7%1-P-u+KWwAWwIXO-&z|V}iZ1Bv_t#$JS|LKm
zw&MQ~I(w*o5jyS_{{BCJ{R$B}{K{@U|4*T_-?f5!z7o(e?>Dae9oLiFwmD1hxTDB0
zPye1#K2<(TkRTo?Ucu2yI%Hev$SP;XI=BHRFu!I-`xg;H+(5H13+3JC_o;5H=%8zb
zVw_|1D2ChbUO9BLLa$n($Pnw7!Ct5sUlAqi&7qqo>HFxlD=HaPYs;9YKy_2r6BvLm=O44ut;?=m5M){`A#XqAw?2dbaMlni8^IM3-=N3mEQ-fswu92n=j@^clrCvlQ{FK5>jzQ5ml+;JLA7T7y+m
zC3CiHW>4loa?EmHH8SRJDj55wa4veCs;`#O2E4432RO51SXa;X&RF=obmZP&t?Jn`
zBbJM7Pgl9PYn)4Qy|bf_OA^6=c0HHg#}&+woyzU>(AZ!m$g$}e#+muIc&pTzlg|v7
zYnNHs$+>Iw+Q~VRg}HC*XB?;T_v@iepUY|&o@P|(J=$rnIve)l_U>BD)kHJgqg9Og
zqMT9n8_8T)r?pn;)QJQ?f*#keilMp=uTyP#is_O2Tp4{ahr;$MacBh>%`et2TgE!|
z>m-S2V<)sJPBYrK7O)b-VVU#GbrNm6g*~j-{^?cL`R12QFN3zsBH50XG(Kkmpfa)XI<6`7&t=TLuv#2axQRYr27qS>j$XY
z_GfO>LS|@ydGlnk?v*FO^EfHg{RE?3`La;I7IDj{?)*rq+g!bm`Q`dmTSwpvwE^90
z-Q-+(fM$sMb*(jqHTT}fm=>;HLM3;ySAMRjkB{~xqv_#d?;4-jUn8w_nr{?l>U%l_?J
z*u1A}EevrBs~)qnMAdgB_TWkELI0dlTQpO?Is3Qs^&hr1(7o7PBWJilw#BMVBbm_k
za;Y=Z#+bM4Va%IfVz?~{%ptk+FJH6T`xR`BO#9ju*1RQ(asIRvC*f<1w%)`f%I)R0
zNaqR_>wJ9%g8$(IrJ^_MNJ#I#YR}qNeQ9@hc_suPnIy%B9!p
z9M<^n%@-S)d@r~%wiw-@1XVtEy?|Re;8m`sLcpV1y+z^(9m#CWfrXZY+XZ|H46E7#
zOeznH_v4Q4nAY4Ir3q&O2hu%|aHn|yzs!$09gk}T?Ck2%&UF07UJ%X^E_LQD(wPe?
zvB#FO)?hzo<@!`I+9`RGMDR$Du#Zc4SP60QULe}GY!#u#f@;QUE&zY$?*NwgmzL0i
z*pl%-YH7j$c}r@4OYY_W$(Rhk+LEd_jY%62C5#CahHysFdYznW-t-ah|bvu(A&}lJrQ#M5ndgPI%#zdaxeR3ylM_LV6GlM2k8vt!lECXga093jm8~F
zz^le({}=J9x_H^LgvNv!6DlT*Ox%|kHqkoq_2lo8pPPGp?f~FbR0;dq%%EC8EcHVmHQm!In)$r-e(N*-92-Z
z#^QunaE+mFCx<*CY)KyS;6BZPM?u;}OY>Y(rWrK{5$`PiPw9Q3M;g-6J2o(c&2Izl
z&whDR-$KuZMd!c^RSwcSo6?9^8|X<|yoyrD`jF%uV%o5`AaM|Kfy+CPa*+gDD&&G^
z8zH56g*hfc`K*Ox%jMpOIo6_YT<{2GEmC;;kwDu(C6f~$@v}ML-IWqQ{5u(*#=f
z4K#?4BA39;X4YoFuZC{&F@Jla_S$i@H%2Hy?J-RJBl+%jXyK==APYzp-+~x(P3ruL
z_LJr(>LstA|G&#bVSD!x}J_wb_+Sk$)g1_pXameqjge^D)FxBE3!
zSSEYKE%wu}7-JK3(x6*g)Vi2-=HtO(Jz$A9ie<~+f@fTpSeE}2<}{@3CzZS~#9?7O
zRF?Q3z#acE-hj7um4&_M*|6?V`~vbRV(oZjyrr;o=1zD3>z;evLCPC%5OW`R-!b!c
zyrTxx17FSbu;w3HGPptLc2BT&5tMD`l8MCYRp|)yhkBu;Cf494Q~|
zuzmZ3%ChDj%b06ou$JLFV~b{EEi*JAy|V8Z)K1Oq(R~b
zSq&sXf(|vFvHlZ%G6bm$bLI591W5<-%xfV1rlCGb2>8;XGy$-K%%LUk=2dgFbUr=5
zBlnjox0=5GJL6n`Fy0i{gHg?Wl#v}Xowv$<*iqlF$NfeNYY^9n{za^>&GV=InDon$
z-o#u3UhF?_(FV`k_0k^ge(&AC92Jh%{H@nFE^;ZFug1Sdekl4H*aVdVmbut@jd8dXSYLfn%VjZ$Fbrw5nQ?mI=NLD$(|N0|nqzG9oZfIi!kYrk
zGd#Ni*Cxydz2jR`t?-RtVH041XpteH5dja|Jo{c*ioZ0XsWbgD!SR~ahl#&?YxN^y
zA5AJnGbi*duQON`Ec8uL)heeP*3ZS|73OZdXb30OS0QBaY=iJt#l-h~FBT
zc0giD^7yHOe(EDH)4EMY{P@ndlXbEDt^SbXcv>I}hZku{#4J|t$Sm#YfDT+lUBoQ1
zi-!K}@@C}XuYH{tQRhk8@F?vDXvahT(|u3K^rAEY
zc~lo9GJ=d9&&iYU6q$T#bV6HR4@j4mtG><~UA8J2_|PYtTy+`t%C(zxs%0&lOIF(X
z*>fGCs&E+#jNg7f@3RZoQ(-Ro7-nhSO+o+kb{Mx`3Xdn|=qwp5GTNbQKBP_xiC~!T
zExKCBVUAY#zYnDEnPDwClc8sLJ#3TiV*{{3`_#OTE4Y}G)Y|shv
zFmA+i(8J)i@okVAj<~>~1yJy%j!+8=9*vwCb2Hbc?Ts(chi7grCEH_eUzSYN?O2%$
zE$@SsQYyJHcS5elmyg@0kO|-R)3?kp!4ie6P@<~CHt0qeNDe%@0yrY9gRBCg_JqMV
zb5`>B-@$e?xsuKfzn_qQT@|s2J}&AONEyoOxwhyQt&6rNFmrhitqb3pzq~6aaa#+%PeW&-vL8jSJS)7+`8J46{FBDPea^r>~LSYOWpyg%C?M@qUsnKUD*)FHfqH>|08lhSY8g^>j4HRa
z6WBcZx?r%?$@^K!^0J!E>`s4}Dj
zOR&(41a&0m7}Osvo)p^U*#9K4hdiF}3)uw$r<6DwE3oUUkzUq6_I{@){W1Ci2{cj?
z`eVIiI2v1nHG}Crv+G?bfxXe%3J6xKf$`PQ@@Jflu#@n;e-6zQIbcR#%ObURF#FNc
z{`3qxD$+Y3X|}An^9FnX_~q)LGOr3+or0XbjAY30G|i8OO^ffm5%Y@p)giadyOr1R
zcfw;F@GGnru9CJu!SRBzpe`d_z$9&XJC5%di@g|f9#1G&oH?(J&ZuJPd~R>TeAqzD
zdxw8a7H`qY_DV`^vC`(N>AmNXeME|Kvp3R{vF_XaCgLR69uZ{riwA$>$rya@vjh=W
zwB_|BiE`xEd7qWRase6%Y`eHVk6?Xj_Tg0BC+abf?uXNhJ$L|V#hIjIk%7BNC95~S)(uzrQdREO&aHYMt`gG9BH8h(o{XeTY**+FWbTgxX4DUi
z)WtDlRKcCFfQqe!T|3X~gmyt=;xx?d+3b>pMAA9~oT7P!mg~vl1cVJ)D>NpTGZ*t5
zVRRni)M>3DtE@<`g3h&XF@OH^Zze;};{4nqI1i+=4<|#UZQeVIclc79(}oz(b&7ar
za|ZH;rvMke@EGDS^y&XVW2Vnfy3$)XkxOs=<&oE7x#p`5->I1XxJ$x}0oNfI+>vJR
zmV?FqzNgzfj@slEj<78BZidjyZ*m>sS+L2&tq|vQSARk82)(4fJDa=@&PD1k7v<}3
zlx^N)Qh$HrGwF_}8Iqr3mD$5HBTcWjNG!6?vtO9_{s&fVnRWORkLcXov0zBJ-y?r_|M
z3XoP{bjaFZkJrj=lP|>0M@)0cq{s;`vI$kbRCu&TomfkyINP|6u(n)Pz73ioqU>yG
zUXiG0t%w*a+Rlmj)BD<8X+tP4+4|7wfOQag8y4kLJ~GFYDFTdwetL9NK=OFg`s++A
zAB5HXFlO$;#EPGNBl?%30Kaf%WafgZ*D4OLKVUzU(?t=_IXC~*E0vz+CqIC%m!uSp
z3+vCk&o(bs-VE8s9_Ci=^zM2izzIu*cQFs<9Qko79;{8l$U|rzRlo%;eq8W`QNRb-
z*F98od&Fyde882$LZ$gC+4KR!vwe=sCIlop0zhkFR+Kxvkxt9bcxUEL*7VlOM@;64
zDu=xJaaFPGnzMKd;|OG~*|#<5?3-H0){sBG<`3VceqRg635Gt0L^>`<=maX-uOB4f
z8$VVfe1loSJ^;P})_aV9u&!*{Wec$W%2Mp%O_8SWiv#wF^=}vIho249&x>okd;OR#
zUrWN873l2*P+zE9{-ACvamX}7{)W0MBDF`0S(PD-QSNl>>^sYJ^#wuA|BiNk%_7EB
zj?1aZsoxaz&u@=8+%26QHf=F9f9|$G_H$!w!{>m|YJd6`UwY%%@*^F~!F62_w^{j=
zZ1ilSxwy2aX@Mw{+A(qQO#9K95%ad4&wZm77$(^6GKR?idN&>s`z4)}*t;SZFC`i9&beNs**
zlf!H6bTk2bN4Lq*qhO*UEJpMiUT;oDih4~-oB;S9X^xrDzl~smr))d{A|%*{wK2#W)dt@NdFw$HT#Ywv9*=uk#u`1X
z2+Nf8&~%mmjz%X`{IkIKYPZ}`6UsQe`1^5fCu|HEab00W{(L@kH+?S3s}y+L)^UY;^zE#y0Uz(yxv!
zrwJaEFt+TbNi;6_(7~wsB$8%Ekua`^Dm}(^?6d#J#x>zi!mo~NT~nMeE^AYq8RMc+
zz0DUS4$!*-+sHz+`RlwLRhX|2xfskQ)?i1!S;pp>uAs6``$!Qt-L8d&f3VDelY3s<
zHYMRO=+2NXQx^^X4AJ1w%;EMK1-)2@9M&$&Yd{4et=QHdr^o$RW%E^{*O?OJg|^Ne
z_|hs17HRll8{kXmtBn}M=3abkab_G6<<9&$#^vm9-F>_)o^R}Us6{J+7e
z3mS3&V`#^%g+=QMhpoLc?zoF*&UJ*xl{xs<&PR+}4Qmn{_V^!SA7vurD$;+`(U*&!
zEJvOYvfzE&_@n%MZXzEm9}TTkf%mGu32ZS5SS3g1lJU%OIc|sO4Rjrbd?O|Pn7tyu
zh#Qb2g&yS=$O&`p6@QmV}>cWd@1=+&V?;t(sSshaM*YfoZ*Fepw%!QN0@2iE(_N!P$J
z5b`$;&K+zsO_SjkAk)2G!cpnv-Z709Nb5?b=3(XN{3WP7wc+{h*V~Xh`=Axcj}~g>
z?A5L|s0GI|cqFiuG1SI+QP(;0n-sz;s+DbA$5Lf@qr5k~k+g86Q9%^4_C_?g1~F`J
zV?U|tr}ou1bEmIo+`Wy%Inv#tacb+~`ywihnP#*|-_@f`$@HA@Zk4o0%G4l}{cqrl
z1YsqtXL>lDuHGzZwfpw?r)DC?f&-EXBC-aGY@6OWqtGDiGA?2@C$Qv&f-xs
z=x(fxbtezZ+`!X|UC?HGb>^^{uxAEOf8b2*iaO>~ndo
zgZ;JTEE)Dfx7vpIYdgK<)w#pwKB#T(uhuryUt5pYxoEkfTYZtIU-$Lyb@Kqdf{T_Z
z{B?2zWQt#{RgJR3h;#63?Otn?zt+>JwH&oty47m=^;)C-wf6Wk`Wn!!uLJ$HPX06c
z8i2kAbn9!tul9AYzt$YoYVBU@5Pz+wQENGBwREf1^6Rw@_1D_t4fHjzTVEqjzrhW}
ztPhwBnf3TUE?No7&br@#J
z5_zrqV)R$fo+S>=bEjW$&o56rKjX_eCl{Q!JU-k-TCQoQx!F8UWiR})@GSR-7{)xu
z$Xu@UoLhAGvMx5iIS4d(aLe|~C7OMR9x|(RnFDt_qQH05?U)t+>L5_mv3zq7PVqYM
zPy)$|0{YmD+7OH4b|APRO1k^W5<$rxybbAOW}vzD+oq1$f{n_a+kwE=@S1Zw2&IE$
z;7g*E@GRJT2+x^HXOoSk(jHx8Eaekqij?O6PWB<<_opsTf{l9+*>GPzh5RE}X6qzX
z5TkHOLl`=%q=Am*?ZITzjr%yL58TI5Z{hE79}grLKtdBpJdU!!2I8y4puf>&fu-ip
zw`roQ15N*k;Z1MeW1QjJ*ti|a(Ltj-BI>t{zUSa0I*Eg(;zN3x7JKF2S;8-pB(LGL
zXYtwlXf>$xCF-?yIeHp-J&1#36t+D>uA}X1h~y!TshoNfgf^8vix+%l2Ci{YYucc8
z9kmyKjAoNyt&&DC$`R7h1n*LUTOf@J^+kb0hUlFPcuXOTFs6OtnB0L5xjRtg<=FzE
z;~c0`_UB5?&ulL^uIY12q6%acMcGt;Y(NO4$bgj%R2uww01FEqZm$b%*x`%Qqf2>=
z+UZt5-bm8h0InaPw$BH(ebs@Qkb8`&;Vu)PtPgwTUbqu0Ps8oAjAxB11NWUTg4{KRA8k?8Z>qe9Nb6h8`%8PSF^1Q{dzWJ1kJI%k
ztBtW&+%8gXsg#hU+#+|hv&rOrD65a>-wQnlyOYwrPR0
z?@o9n@ls;q#7`#P7JihHM(1u>`PpDZ69(&1{d*HD@*mHi_i^^WwGyHS(x9E}kP8V!+%*8zdanEKP>oVbOk9Jr`pgBf~`Rx%XLrmA1
zoVnJ`&j?Fg4TwBFlG_;Y|r7d@vd}zzVmqMNLGQw?2>o-*Y
zNU(b_OF_wB{_k+3DDR-T!QK-%1+{5ywEMs(AX!wCAd7+w=Y7bO>LZe{$3ouyhhJKj
zTuE(3Jdae}drip`UGm$IUbN&Te+dtH%`SX{_5@@fh{=|=6wnmykyOi3E1vx_d&pGW
zUG<#4>bZ8dsnn&(phzil=o-K$KX^Rum*Y0aKN3I@A5-Rd^4-KEHx3tg$&uUSdaS&v7V>Tds6zH{`d7LpRx?2
zddTii^a9k~OIhr12#R)P>06}>RQX0G-u^j!1$6v|A~h||BTR-hH{>3zIVE@s&Co^x
zKdKFRRJGyoZiTdvCA2OFQl5#*smmM|czdh0G3jAX^SAOA<}F<|H!mGhVmGrSug3x^
z(b4%eQdAfQy>UoK`N8*q)0Ba+@P!a7e;g66QA1zy?{o`a2}|MzIU4yQDW5$E?c$W3
z7(_ZRcrKw_8udNkUuDoB{dr?;ad
zPK_^F>_E9@C_USiWFz?ZKv;ysTHH=rFZY1`hrFePrFA0m2HIV=RF*MiA|6Kpk8?jE
zknDsfyE&Xvko5%O&NVeXd@N5piu4gcPefi1G+FZlP4Dn%L5gum11&tAWVCZ>Y_|h(
zryKTB0-azT{Tz4ig8OGnt$!!*4lXS?kz@-zi$B~i8){i}uJg0C8THA<_f2MAZpyBOevD9lT}4p+M)`dzU)o@=XjO|fINh~k>2UAU
zC*ciNWj1bq;+Qzjrr+B0y;7^#KU-6%BRrH5dbk%cy>tzC>Sq_<@%N*&;Xyxoc}MO&
z23vjj;$G9JtgKMm$Db*p7L|tkMNVE7@3hMC*D4{cT`I524`-b23d!+&r_n3+Cd4~D
z^g$i=ii&^jZHRZ+BfjsY4NH#s=Qp~)1F^Q?GwNUFnEca-C#UF}hPcTzMo4KNGjEAu
zxO|@BHXETgng+d58#6M0aK3p(>=a0MCETVae0Sr!ku^KgpfT-c&AUM9
z?y|Awx0_gVK{0E7hnH~g#IRgJjD*{qCgB`LNzvxVwm5AwnERWZ@Q2Y>jtZ^v0`JjAD9Z=VUu({lt#la$rmT`{Q1~#Kz
z9dCTvT4XJPyNByV`EBt5tj$EQ2rUM&{G{Hznpvh$gb|;H8cp#n@-s)Uy=y
zzf5Wh9Kk8wc6EK?jl1=K$iHi^Mx8U4y6m-fP&Pl$U*B&;M{FoguNeJO^UO62*XLc>
z$doc9xw0(4KHxfDcjU?2q0z&Ao!3vng?$SN;7rC9*50XIaffw4vL1V%W3+#~!yJ~G
z!&w%0Kk)dao#c(v0l!(XT)W^EF;Px>Fp$cSrAjIMc7k6sIrlrBq@JV;0ey$T<>2DW
z-r{D&v*xgQEEm3pZa?jGv!9#0O>Pc
zTNQ4_6VGZ_L#CS63F$%0oB6;k4y(0YTv2KF5R2GAD=M2e8F@+l_EurPL#p82T&@Xm
zGmjqsIZZ(x5$gZoZhzWp(bvD-+TP|e=PR)$e~UFY5o_*G(B8K*2l5Z)AI?9Tzu7?h
zRukf7<_fW;)QGX;qd?3!e=;00c?e*<%hBY195{C^aHrYwk}7KiXn2x%ASGIAcJXYa
zh{^Z%bToz`y?QP1u=#)XSGLxXIn6@6OF_Q@HDs=JwJ?!WNw0#=f~N)GA;Sh*H$
zTn|Fq>RYgm5w#E;t&O0Ns@0%#)`CL{>W4V1!-xx3*tE7_whMfDF^y3`s`_=GSz7Q&
z`_ys8#w_6ZU}%_TnfDsA>_=tOl}A$-3O2+kV-Dif3W~+4v}PI3qG-AcB?P`Jj|D#z
zkRkt`h~0WS5b@vUuSjx1W7A>bGnVFUUVvD&$EWA5I0tQqUf3TKRPyLaH*>)=jjHa&
z#gz3TTknN=7+v)BUVy7AHhcmj*mn=SjrW8evEJs+XLwN4;mzRGg%g!9m|B+x#M7O0
z;B83Yag!B1ZV-)4+N?-XIhtZ2yP!IxDu*}b24*S%x$$16c;GXP%Fe?%D##N3oHCi(DPs3^^Ei8CL5hG0@?ng@Jrr$52J)rrJ
zuM&Pg@cnM*tNxu;9py9E#+)*(=ZA{VwleY5L1daxl(M2wTP3n_Yo>(n1>TgEmslpnPYHhy&jAyTl}`Ko4_n8Xtn$YkeN;>`
zQ<2ZrGG%~I}^v`!p
znZb-^Lm+FODPzoi1^|2N8Se2^Mg_b{a#6nB{FsH=rWmep-nqlLyd0Al46Mnx5MkuI
zp4!!&cw)vl@84%)NhdkRy0l}dDz}9rtoJqOXg5oE78+EYPWXcruqv<{VO1wqBxyW~
zxRfMsgzZEv$<{Z_)6t(8!&~OC0mRi5>iZ^#3)jPvqnwq!woMK#k9Ko-D)`wI>}lvm
zm_sd0YzzFlLW1xz_}f)H;+Vj1a5zhQ277yqD&N8qZOntV7v};|bO*QkuxexR0b4hG
zYTy-J_%vyefOKrosq4X
zOtY=6T+3Oe&}<->AJENdEnMP`}8
zj{n+a4wqrp2H?!Y%!Q>g<}eF${AbwvUDujtS>#^>{)ISpeZeP3)=aKHbH-breC3|D
zvdGt$&Bq+J)=pYaUA?xr$P=5=sMOfc%68L;wDQ(?t>SwfY?dT;tWu}V8;|_s??|35
z@UOuq#8U16u@q{&;S%b82qKTT$Upf33!--lw7%X+x5l$Ig1-85vHZ84W2NcgE*bF+
z7OtPWzVL$oF8Xje86sDDQl@+r3krSo^Sz|1H>A*;_m<3EANiHPgn%n-#hGg}W-qbU
z6jkrLP<8IinG2_=4BbLWyC8fVZXDchRNio_NM&2j
z5L_R?y5=_V${eoy3y)+Q>sfE}!)27=wa
zYCkp-P2mMiAxK?Kkg~yF3+z|sKd{>9;@lLrsuz9K3HuAG1yqU8b7dFz1z1b)mI?Yq
zjdOfR#JINY5hp}VnBExpe>A^*`moCp(B5F;8Hn?0P
zmX$rbDCNn*?qB_18YZK@ce-oXnxhilG!G~0JAJ1$CDvGm?4
z*#BEzO<0`pMuK?e!)L%!L}{OgvJ=ESsYyf!EZWp%lO#XGCeT`kU(DCTPht-Tyq8p(
zpsdKwD6%A4WK#5JV}0LE_q%L!WLV?4(btwB%C&7Hx6i#1GJEnF^0wH<06=F-F2Mlv
zFa(;SfUZl%3?biSJB~xv;hV1(I$fj}!N>S_{ziS{nvC&gy9U5pkAUeK=soMOt}8|M
zER8DICThra*NOAngTP*76mZr1Sy|L4?qF7yukMN5p7B=m!7Lm1K~|RegYj1GfWm5i
z4}bXO-pB7ALlE~~g~XE*ye1&E{~uv>IYSCvZta~OtUb2JT&?#Yb0b$d^58)Gk?m1p
ztrmkPY0Q1q@_U^9Xy8=)Q|m@6kItSaev?h~B&}{wv^rXPGrm4d@+7@@?^i4|gi%}O
z!a^hI>K&Iwq87_FB;wsm*gP81NMlD}FT_Z#7+;2?thF1
z>jZ4ddZy15bdif{du}q~NlIFmOCJV+UeWlQ(f|FzMDrR-8}X;C1K}J{Z?$j_jc>S
z8&>30=;K2(1oxQzwMq02>DKCJ^h+O<6?(UwYO0&EG_UTg=cBV{59_8
zUHwM%gDj?$5A!4)yDX-N+*Qdb$r-f3w#tWRuF;$7sD+Ugo}@QV95x)VAgTxWmZmRl
zl2wXPiuVlE+LYqg4d3YxSj8Gse~eq_fC%;nq@!)rKG!G9M%uEo^**h
z^uI&<)&3ldKKk(V$|cX9ae)gUVt@&1L;($i-P_`4E$Zs7XwCD>794-2L|zkp0qdfQ
zD~8wEVtCF4)=&jxKjv8B<&>k+hA5wMCpcR0d^Bx{{ir(uIBu@p6*E`E^ksK50j!37
zkJ-)MU^J3XnB9_-jE4J~+0C^PXXG^SPLC&kmwyV>!TSIHT{wPKL9Y(a{}S)^KaB{-
zuS)sbr}94~zR7_B{S%8UuUI@uoo>56n^|D7Z_1W?k{)-jPnZvkr7S*@U_ZKdq4MZ}
zsqj3Niv3o8D&Yl-@@S|OKBba&m7PmipD@Rw9NCx*?7AA?Pk`%^^!SPT(1d%OWkO(h
zHQJNzx#LNCr8z`5P3O@C{xoC$1Y_#}A#0dgPQ<^O--zQzaln;H@Bul5t+{@?vXxc?(Ug!}uCif|v?vwz|~0q(0m
zvg@}ps?0LL9`O873HVRa&9_*70rtl}2|wdWtsmHG(w+b%H|;f1HO9FV~runo0nf^RXNNZqsllD{YN
z@9^iRUEa@vU2db?Sq7BPJYeI{2kfEX-9inKi4WJHhYjtq0T>3;-1>F@EG)-3LkIv)x%-GX8H3p
z;O%Z%|Bi*npiNbXXtv^6c^~s<_2)_L#CVU__mcgXdJK}t!qvCLTn%lQ53@g4`CZ_)
zlKODjKj$9v6przTc~V=jzSsEk=vy&oU(`p)en>qgo|Kq{9<5T$f?KUSB^uJW0Xbo~QVrwU_ZE!T+Cs
zUO1YUyxVlfqvu%nm1EcF;|-q0>()_g)iYHyTbKZQ%eLuxb+sQEm9gcc95eLHylt?0
zbAM#S7&sMp3E<1Zg6?nbzZtQVR>43&zx^%%{QKZwue9#7Ju8~zcbGE~o^
z?`Z_;GK?XhRYH63m2-nL5lKO$4{;VuX;j8aN7IU2WBk<0Vs=fu*{hyh2p++$B{d
z&s`REO9dgApg)bjclfG~41o2RlW)`=?GvAYd&$$BFp(x6o;^mv2pY
z#j<8H;8WMX(9*-ieahP>ePUFe+L}PP_~}D~t&NuXc)IIccdM_Lv
zLJ`OL5Z=!fK_{?&XFhqE6rf%1RrZ^Jef#9u@G?3z%e>HKXK*ghQdI*y<_4kK&Q^j(UWFWTqQl*UCZajRf!x@
zt`F_4gn1W?bgv|8_6oRM86sDB@a>cf
zu=q)s=L*Z{JOKHs_ZYZvI`B^Mh0>23sl;L41uam4kBoHch04p995zx9#k^$uL4I^r
zE>Ty@YiKO1lEWdxhY!)eC=`&)j);Q|Yc|PXxwwja#OwgS^Ph2*qZy1vcr*Sp?iBia
z2K~LfBDu)uw>a9kpooV(Vl%bA>hh{&wA?PV49U!@%YJ&UI}D{MV#~#Ebiq)X(gj0l
zN_QCYeY(T2_;Pm`8ZY}{xcV#HF954wfMKKvLuty-V2CeN>Sr)SI_@DU55W*=-C^jD
z>qn3rHOrC72It2T%+mS;XDlr!88wSL1Rm0EBV*ogBTsXTDmy;d9?MV9){CQe&kwXv
zbic#dub1>YZYUdDf!M8XU=4elbkwXJI^2~?X>Py6YG4qR7#6g3u+(5i%@QrUmgXJD
zmodVukFKL=3+sKDH1$j1k3xdHNcj<^(Ea<~llcD5!{28w5!Yz($+&aklkH?&bu!kc
z_!e_At`2MAlKAGXjJu4ra7BDetNfxQLh;3M@r|$iqAXeQMTPiQ?Ea#1wBif@esF(r
zDqL7~F-fZwija5p)|xNQ1YSVwVb|M6HD+%^R1xI&U*}1TU*`=s&c{>xr3=RSMlp3P
zQePKRKf7`?DOFg{M1czHImr*%;*?wFxU$icXkGIYu$s{#S=9Pgv+$O7%)gqieu$e(
zp{ETuy22?XnD?o%{57BLN+emS47{C0sq+L*OaHX4lrG*2<-tmtn!b#5?bGvwTjRj%
zLOH~}UXA^cA)KYYy1@4dfqtSWO-ovp%h#F$r|8#U=LxK1>~yg0+B
zk|(i34=BP6Bq^uh3HAulFjM~N-(!}v*-K#cw1qVOoB6m32Yi&rRr==PBkUsVUU4t;
zN8`?6HvMv(55-;NgVTp`b-+@-nJzw5R4vXJKO%kFW_{e{feK)>E7lr6pS7myQsoth
z-_=!EzuSd-xiJ>^a%jb**_Z-%$yXU)W#Gom2jmMhpJl>Iy4NZ;jZ+(M<&NcJ<(
zq{G&SQQdKOX4^&A}seAD|$MQDTWS_|;
zC&>axm#sW6`P^7q3!5$&O_@fverL?R?wsG6M8m|R6KTJ|no;-Sm2X`umpC9pj4Sia
z`Nr;hqiKUU<1tTU>*G!-6ss6@b@YWeL@|{BN1bgaI%zn;LOnGhnqaXDut*VL0XeK&
zL$T%wbCLI1@tthy#dkm|Dn3o*eP9VGa^^5IxpR@^D<
zZQo9B`b*q7UmpWkp^pmCAF#Q*cGzgjwV`*bFNnQMwR&_{KWo)3NEm?L4W!;F{Cy+L
zEcR^I={8@__M&H3Kk?@$evywK#kWeuUfGs*UsEwQu@`9!dT=URze=Dag6lYFb(p8G
zK~Fjl`rw2WI_7WUJyL{1>S~Yfai^FfaK4V?lp0+}31wu;X~#*60gr!ub-c=9lKayMU;$rKDSc
zy66kXZ(?HQh$tFnPKbi772(>|&``uqMGnLRzw=(b>u3pfmOR949KpsS+8}oF9q5A>
zHimF96&avB5UG!75S)6^tr>Ku&bL8EpTU3sw&3qcC69bwyyIK`D$bT=g(swNT&nBQ
zCGQ&JN(3x(9RDkc*%i^j7L03OXdJURbA#!6IX&b0Hyt{Z{
zBY2G{O@l@3Q1aYSrYT+85$;^(VkAcJ(EA8BX~LI;C_o?*x{JJ!roJB4%K$$az*NKY
zZ;G~SNW;k=h0`PB+hxF1k;3}`6*NZ)>!;Iv47?ttHgeI@0m`S>jT)Q3Fjt63JMebY
zVbJzvQT9&)X0PKHZr^ApDBnhXWv259WT}j`;YA(cmjaNG1*IWefydB8{~-+=$6RagoQU8
z`*3R+s8V3z4gm|({7#xRO!r2DZ|}aKdP}MB=z?+cB3vy*dx;Wj0X9Z0^o)pg!c$ok
zz5@anA6mh8-!r}oPl9)zjtBiC?N@(ay}vZ37k8ufF8gbbKR0pa0Vkm>#pv;RwST$?
z4}&k62=?!$Iq%&gjoW|x19W2`ry2T&Nkx$xUnc(-Wx_MT-uc5_l$mC7@PV8u&8r}p
z8={n${P9iIf!bG)$^=38%X4nZxmdm;Dq@_YHJsV`ovJaMb+mf#hnygtuHGj;fou}|4dIU6
zFd4i9-J(m5MxO0`;`44_^pohz**cL!5q&(d1QtkDUG<*+#d>2AjTIV6Ssib5^cHBI
zsM}fej+h;?j5xvTm@g$ZpaSaw9(nNY+0bbba_QSB&Y@5Oa-yhB!V~7wL#Y3K0=rr}Bm~kN(4f
z`A~Vi_cxWm(-2co^2zocB`(YtDC3ZV6AzE2;VEH$N>tFoDJc0IIlq3O--i=Z(%KvH
zn@q?Hiaol-%&)>jOXe9(=BALBji$GodJ^um6{jtI9s=T8!Z|
z`WR#CSIb*Mkh9NMTf$4~ZH@n|-^~AWJme{ZHyy}4{kd=4k=Q>6#ODG1AM{Ljc0bWU
zV&vBuRV1ULXhbwy-21ShLlh13`!@W#72F;^fP2pv5TBt$ghsxe%iuI$=rA|CLRmJ8T{cH5Js
zgcGpqE}7k%*du3sw+OYlqBm$Krk!juevsoydW*C;3u{T!6knzE^$vagCw*1;znUvX
zFm>Zpfp=FI!LARQqOJ19U*}ez;M`FRW;Qz@V<@k^YhZ;qY-vWe?nM6b_LIA_`RB~;
zm)Na{`hE7Y+5HBaeU@UVoA=rJbM6E-e;M*v}OMw;E3>`r$q&KfR8t~R?97_#qa
zUA;6fd%+>%#AOJ4z{plL)vQ_1PwLW+P$#~fD8sq2sQJYvhFQAAVvGZAmJyU#DtD{P
zqfeZFV01T
zeBoQ|P2R!Thpk^!549$T(Ee5Nwx{;$2Znr61Et$G~H^Fe5xCquq`2Q
zLhI}Wb86-o{xAVBc-z`z^5G>!GAhGTuIq|&hho7Oy4sto6>f#hlMRXdx6sT2>GIUwZsb%FzbVGYJ5SMM}NTrNcfq*WzC9Vqji
z(K+%Xrk63I?1C{z9&}DKbOgNGy~JUbWUzvjLFZi7yJS_RW2raT6cV6Lhli#U8GY*1
zMsT!Oc7)EV9&TJ!1_@U%eC5eY*+h$oJIbE$EZ+6m0b8OaqSCV=uXLX+9CHI+_!G)=
z;eF^n9x>jB-!Et~;0Xp&PtUNcRkM;pk|vFxHYs9KFL^&$O;66tm2OcY25S#&H+8#
zemr+#1fz`08lr_i!pG!q%e4z?SojB)kk3BYBHh)jEyH~LjnSB;n2%~kvw07rv0i8L
zS74tPC?aWWyRA~;SL2XIYWAf?Vupih{F?plNQxD%IpB)a9OV0BWd-8~8L276JQne4
z$1>#EQ>(`OkJjufRs(mTOp{u30N)St>QUnt>okX;9p%GHnuG30$1?a|djpW)BJbzF
zN3Kfv^;_ht8s*4u%;bL5z3*qFaXB+Sw|HW`_n>j|b-
zX~CB+zPYm@&$Nl}m7EZZv?w?D^TCeWX#X+3C*>+T5utk~E&inBMxs4faw90c}HCl`Kjo!{4b}d9a?nuD>pi!Ys2STz$vuI
zeC=C~o*X1|spQR2fu?lJCt|KXM!Q|Chd9Bs0Gfl7T7it&{TWoiNL(1r!)z@{-%xVefs4<`V
z=%WFyotfI=eE39b8oQ6+lT8$Z5Sji%Ud??7JbMUumi~6*c|U#!@*%O%M+6SeAfBm+
zX^Jn*TP9$02G|^_>0uVVfYI?@Js1e5-+O>azUf1iPdnm>~0R&T$;x0mWH#M0G{0)
z0F180cjQ^J+##28>ESDLRbJo>d4}{{E#g8(m^_U{vzp+ch3q@;%wDfKWSdX-e7Xz!
z@49}jg#T7c?~qPptiDb+aKX0o=RAju7vJl4KkvqQc-FelLVOG03Ea^|?Zd;f6D?zB
zL(eed*!vD+EBw=?=WhI5T*I4LaV`ewee~>KL0$a#?aB0PH
zZa;;4EB6&}1{tZq8H84{_|;G0-pYNAzAF4*Irj*x(DY@36eJHTVlnhFPE?O03YTPE
zw{m3*hQec!JcCL+pl|nxTAY#zemzb|i~jjwU$3KmeYQIOk;B%ZR_ICy{D!^zY4hvI&kW8}Ry=hav6_eBeF=!SwDW5^<(_{U{!
zIk7xsQm}9OCTEV!#g_!9=O9{K(b2568389+!{%DQ+CI7@-FpV-Ot(bK*GjbXyS!Gi(O~+C?0sN+
zoX^9D3J5|PhBAiImm^)u9+FSb%jM^8pPOek-eyjMEh0WjO1i_ZvH@-Ra&0>fcXUe|_t4bpiA+&RId&4m?NAWB%
zN3t(R43jM6XnBysHiL4&Yj_N(FyfWMJMV+~r_r~+8j_zk?YPKTpkZVRtzj&w9iiXk
zO!|sOWHC55A7$zTYVJGA;p;Q!rVsKlQ|&0p?KLXkvw?e1-xPl;=))2I)U;6?>xSm(vFv_~mr2d`&n-CW)?cWUdKUpW@1-
zh?o6nCG3eRAgjOD5AkUSXZ9_XCG;rd+)|=W?leJ43Z3F>bM7ugL|ID3D*V2Q`BA5~
z%ul$GK(}6K;a!_^M?0dBx#=Ps1NoWgD&j+^&>tWwouOoXYTW1
zHvKa=uPoZ9G7!bDP+ZkRVq@L2jZ(1`*Lw1QbL^Kmn2Q
zHjFxq!#Jp@sEkBKR7CQ;|M^ct<*iz^YSpUiuBu&C8xoFeX!zxg
zFKX&{ei~MHm0FFN%K-F%GNWj*%T=`@CPR?boe}j)5r`q=Ucof%Y-b{=n7bLG@f)Z9g7p
zeBes)`70dNYo>0@^Lz9O#5G+(M^s(s1h%XP^?z0;EG`eCPR*K>EF^u*bBcR@OE#T>NL7p6l{s(w-CSkQ<6Qa5_#hIQ$^;>TcpYB}A%%6f$l
zLt3boQaUio8AEkQhjKfrTfTDBr%v|HA|b&k4gXQqs`+`6!N(pvif>rxDOA$(ezkQg
zpIN^8wGN?K%sexzof@h+MrS6iNFH*D=Pl*ypI(g%zR)mW*@cF0UX3;yQsvY|nXjz-
zHFDFcRJvaL2Zu>s{*!YVvHQLy2%$^k+Qj>>F)=gZ|y6cze$@ds_=Br->
ztNbcnXn1??qJzOX1xw$q8%y=^h}pFn+9xkHrkO9j?knBkoIQ18P_yR08fDzmY7@&h
z?s);Js{0~!?Xga{>HPilX@{nzMy4Lv@Zf#qL)7GZzDQl!`ETi;o_oFF!kMcFqOPvXfj3ZCuk1eY(+bzRf;0eTUyL2LuL-vmRnUo7meQl^LD3BrcN$WFOTX*nl^q
z_jFF%vmbgNk7CJ7zDVs*9fh-k9Ws)Rt&9o^eDTjOptcQIZtfUt*z>~cJau%x^DDKZ
zjy-uipr4WL38l7QBub8#&lH_`&W}N=9?jAGUFU#BM%tI*Uv2JF_W(aRqVgKk+Ko+a
zy&-kakXgD9SFG%MIepJPMLM(hM_(xh=S)Q3Re)T(yu;ie%B`qbp6v;oj2yeXoyu+V
z?<=>DU%wQc{oKETv){hQUuxkesMI#?3m!Ldshv@Y4S$SEtc;h~lxDFnKpmMx@joI;
zY&S2lww?)&3m`o0j|uugMX`o_@C+F^$S#vIi>vpi`SAhZv{kchxj~1vg=b-r|4TbGZ&CA8MeO`<$X#*+Np~;T
z6NkBDh+*qeY8iO8H8eijuQu~97tY*$?`hQI_T#;FQa%1?^_YG9L{dZe8(Xq>
zXFd438spZbW0%^4`_wHVz6R4n-;GW-^iDI+y{zw5U!>EGwH<^`XFmGtGJN~vqhEIO
z_A&S#9eNn_C^#==U_JMZTJhjP$|KsR>px-F4|x=o`NHy|wCJ>?0
zd!GNCt({M8@blEQM?10=p({J>OE-V^p}yt*N7YnC^ZHQzc08l-Tx>9{*;#9Qe_Hm(
zf6H!C6C6)cuQ%=>>Ot_}WAqHfJCW79v%VX>XX(T=a}|1h$*9wfu^t??e8RylN2AlS
z)4HwhFsLJD8frWNj~}LS5JqcQ9}SE?eAk5kdfTSAXqO7wZyn}Z4Wrg~`55c5ht!b<
z#jX19<{aH0Z_2Uya9X=(?uj|F8)v;oagG^ln{tp0+$_}a$b)LS=qa@p2fJ2w{=sl6
zV`ayEhWFCmd+qq)y3x^i8`Fvnufz8~-$-lM=hbIw*FN8o#T=orPU|ku8~W7-#EwBu
z_PEk3=1C@YyX(hnucN&vSeLrIxaM@GoRvK2M?6!$VBJ}+`SR~jkPcxGpj8aNu(d~V*J9@@hSM3zA;Z!-45J<`x6b_VJ-8wM
z_J0;^qVhhSIzvf8&!eYPx7N*AN~u9wI&U+y-aIVhgL^(%zH>#)s??0}2j$f9|BB2w
z{86OwFCVT;Km1`Y$)cmW6=kHqY5P!zKCIZc74O^!?Hh&q*5;^M_8JiD{5%TeEH
z3cgYigSi%szNtP(rj{hpzhcvlOiNwT
zdlg%YrNxzJ_q5u=j=%QFy3?q4BE;#`(;1ZB)2UlV6HeY&@mHLn|Cb2y=z*X2
z1)_Yq9PJ!LYy5rw>}**08Qh11L8X$zYD7C{!!xgUIm+7?S|Zw5gg7sS-W+o*>Pbvj
z(VHCW@-c-#txqGKX@~1RotF0N-;R$KJ;PewGrZ6HfsMRpkkh7R{QCX32kX%G5AJ8o
z5N<%r)v?;KLGmh?bue3C4BM5EP_d#
zgg@=rEs8aSbz}1w7OC(%!wPjI+kHiNraLQ3ON;H!^djN@|I=S>KJaw!#exF94Hckf
zGl&rp!svMRBF|X>|EHn>Id5S22pA0g3*!G;`LGoe|NQwXByHRqBsUDv$7}&!1lEAT
z4O0p;6=pn4HVn#HAAp}h`2{xn1^vda)&J!$_<#5}An0;qYVhU8ehMbQuDX*zBSSRu
z57(Fxu%B%s%oX5Ain-MKa--@dJJHE~T4P>md%2NG>MxFds>6@VBAWix0x}pBdK&+s
z&0g~p4C(xbHhj&G{3R;;|KVRmpUaKL*c+Qs;Aw7tE6mOMliZu-JvKn_J_C$TxZKzY
zrU)h%CS7q4LVmveOJn1o1E{kUzmyheFE2l}VfV=`Ba)xk@qVvMV}^}<;-c}_wvQ)0
zykXTl!3UQWzD<{!RMj#+QM=Wr+8B=0r0;7i5-_QRto0{C1W0NwY92
z{j4UOO8c+{n(9aR-x2>;8OT%Up(5F%jh7p@fqp%634UaV_j=|8{8}>C}AoskR!{cKCZR^XcM
zM_&E_n9}Em*)b_72E{Qk9B
zKm2_AmjQW0$0c=3_&Iy-;wd8zdKUgOuVZDY1J5LwM_{(W)F^JEkE*=fC^s`<^RJ~5
z&w{F(GtK3-XU5ua-B(~P%!GdJ-a(C|-b!C#d{I1%w1oAI21`zIJR
z-s7-W!Q2be59VnYRYnZ#n-Sk`4NZ-o==Qtt{8->evOfS?$_-34{KydR^~_fIwPdcx
z|9j~9zY#adYAJ4_{hoNP$4l|wOg|XB;c}y6{f*5~@H98S73OCBN$$<^>K_xlU)5tw
zj~|A9yx(dC4221U35RJ1(*dRXwL>L-FcHecm
z@$;R+L~86rOM2SxcllYgdBr~kn4{RYfc^@2f6J(G+z1ClR;eb=8}V}e{^-|_+(8IW
z=v9#HJNGu_A=>o}#XqZA{3Qx)nnKT4WS;;IM*Q1>svpHa5qy_4ab8yJME6g^ge{@j
z55>XQV26%npVP61F?u$oL|=1Y6?YG`SgQtlz4Hna7#riTd8Le;G16R{w_LJTSsh-<
z=(YjdP}N{l^9rX+h2CPf*XAgb#$}C`yv3f`0|pF$cSUI#yG{LNxNTmWx!5jcRzqTz
z+gTyyIGrxl`?lMJynZ+R6Z}PpO^Wr93g+2TUX|5dYIn|+%;i?|Y^z1^jI&la-Seb0
zyWMFn_FAQ^Vw>G+86ag;y4{o>yS3CSd2I8olFcKK5ghIIhIyL7I{j95i4Mw;lA!uf&1GTBrSt-2mH3uQjp~&-8IGx^d)HlJ-jFsMb!(%b+pWcJ$>p4DbxY3DQjc0k+@;8Wo5|*IReDV&^G)XRVu!0D8BKW2wvA!h$R$>0G`I%|0$ApX7E5_p(Y>x7+ECN1KO&;A)Y_Q|X~>~yR}ITlx~y|=x}3xB~jp0vq~zhwA+zR)lFGP*$fum9wcCy%jQIPiuxjz
z+sev$zG`Ubr#VUGPIpyyp4+v9W854_Z?
zDh#|ODg~~zIkoti7cHEmmZGMqMD$}7s5Yuo)N7AdA|ff(tlYWY&8kL=Jd}&^YG9@Q
z#Y5==dYV*NEw*B+VIog>ebDqEl(EQbp1%dnxC^`vbZe!>m3HwkN~n%a7+Q^I5XX@M
zAT~{@;&{p>P%OM(h^@q94b9LqFcBq%uGiv;rzWlB9c;)N$DB&5nfh3+T!l1(TFWSD
z1TQV%T${yPKB`S9ktJ!kuQ7R@lxeood2K>P!48)k*14j8mf{qhskEtM<3bQvptDp$
zd-ldli35`crZizr;k^%ILZs6nA%)d=?S;dilVkF
z>}F&DL!443^&mZSonFaS;j&vRX!tSD>h0OHCm6(Ytdgn(^F=c}wvxgMk;2g=E*~S0
z&Zmz*?rT)l>fx~VACw?b^!?)1_KjVI9SwpB&+Y!mto3&yxjhQ%~@
z!861>o6Qq;&3dn!hN+4u<@fV$G7O6AADoR`F{>D+#fLl!lat%nGrGI6_<@
z?htQCRY-Nn{E!79cZbx3EDos+SsJn|WJSoTkb6Vcggg+kE@XYk#*ob+TS6WQsSnv2
zvMpqL$c~VmAy0=q6S50Z@XcA6DwsQAYGCSMR>0f`vkqnx%p)*=fY|}F7lz)$CiT$C
zs2*(iV4X~LhHwIKVw_H{RFK}^)+gv>dWZW#vQExYFc)~Tk4|;~M*u5;`c$1f4rsqs
zCyxe}+^&jn&E2K@i%3QN48X7+`jPojehE
zuD4Du2X=*<<})+lE+%@sPNoG_!b!lCemXe^xDk350G9#_fmizKWE*fStthcP-i6R01mlXbuskWW*9FL&3;^A&Ug8&Y&KRk+eYI{Bhb{5uzL
z<9}9mg2n468On9hIAlK5P#@?DPHnv-tVY+UUud`*_-pW$)(hJF63*)^o(>~XLnYKb
znzJA(mTyI+RR#vbLC?Vy*{&skC(~Vw&LfK&AGI-cw8_U9d@_x2Qemapj6oo*Y%~UZ
zG%i%f8x)U6ctgMq=2Qqwt+KqtVX{`C)28`Q2~Ftu;zMqp|Dj3Iuz-M8^x8iF-x|{C
z1F-HCoF7~tT#dhEqknPuml|9jR!@Hw_sn1mx4VLCfc2c0wh#mu0)tuwhlI9n6W-SU
zRzkdPkb1`S>K)sMh20vf;q22o?0USn24S;_%W06i0juuQ$#;ff{mZM97XW8g>EsR)
z>Q{+D?g$LeH^`lUmzEghF2MM^402bZ-))d@0X_hffYoM$+!Hv|Vvu8i#tNOB0L)pc
zlaqii06SpM${CkVjs(Wf(a9Zw6CFCaKjNLWTqg%cG8VJ~?G*f-YzBEE@EhO+k~7;N
zPXhh~tN^}HWRTO-v+2ju2c`3^7U@INvxlaqQ1fH3a|@6WAEyzw2*U~7O1xko|06RD
za`luTISlWT_U9Vp8rXwjFLfE@op
z@L=}|JL$8xW+Ue6l(0IsX0buu0{#%ltVVvS_DIMSVRdZ1&mPF^t8{Wb_=CXT$tMTz
zxHMrCW*X!j;E4jyv|_)#0p%E75+u`ZmopxnPySCD``%ePdB3910=wTHUaN-Hu}?Ji
zrFA;_5cmTTS9zX6k*{Nxay5T+>^$shS}0G|U)MrE&r*$D_5ZKLEz^SJZ8iEB16F_a
z5PTMO7%H<>s9QSVb|9{iWZNorGVK-m2zB28?1VNE2pq7`AO`{8wHxGCz^_*7FnXCzjsR9eUOV6?NPlZ6
zmO2mNfSc#*asd)Q2Q@5ApxBey|pT)Cx^>6Dsbd13Mvi8hTVsfDu!_d!N
zt&W#46sGZ}L}OW(70Vsy(HeHLM%H!$Ur(p9YHa)htrzlV1j(n7*E+1kBRV$mDT9n|
zg?$sKM?GO|J}?M)3`lGCOM%$>#_k0lZGT&{8hH&I{v7fesJ|C^49xli@)#Hw1UX34
zhmS%o_T42*V*g!=f_Vz&D|jbRtG`r=1yzp}hso=3nsL!+7GrK-`dad*X+pJN5uq{P
z;;V&C#ZWvdANTf1%9DiFANZ^a<1;q~ypp4`q6E(}%o~f{WgdDykd8MQhst-|IB0%x
zGqN;%HbQ_S2rk6&ekp?Q!x
z|AI`v3h?7$iNa@nAfPYK*+BKO9qWt=xinTU_k}Kpdg$eTz#5i!#eBbYTzTC^l}FL4|KuCUf`vUsL!a_XM5{qJ#YXp0C=RA
zUN!(100V(F;K!A}Y%%1w0-OUQclmabQQ@$ZafAFbFyKCA8d*r`O`C!2;9Qyi3y5-
zHU$7ZksheTnVy(LUcwGfdU~cO4i+>pkt}+^a$X2c&sO{t0zGWgbJBSP5tblXMmg#6
zCXU7>mN$_vz}@d5eHafc_zUtY7=7NK^>RDVOMo4K$4==Z
zAUxb(Ez-*-;LNY|GB%^Lboj>sgMe)je#A+=+ynUGaXlY@Y=2kJ$3qEl-vauM*OC8_
zcgBhQ2Oe;sT!FifpmNhC0KUB+
z{?Nnm8uANrKYCR!cLDwEmwLG?`6Hg&fbQLTIR%&tcRa9n719s9bXYGB04@dpKwvyD
z0r>PGy_^i31^=1QZ~k3+ITP-zb9z2*Tt8dS$Bpajpl1|gmk%Nz(BTig2l)V;@j3DV
z_|0c1PvFjvksm;|9eM)wXOIuTr~ifY0teSX4sh2}qzCwl3+V-J{Rrs=h62NZIsZWZ
z1LL07%k6Pd_4%i#m@9%m!7P$0pdbtm<
z^aIpC;Ck@K0nfgVeh7FG`t$>i-G*`jZUH?W=v|2N0PejTmZ2|PZfM@YLixD}a&k5HEX9stAshR%2&;$v>U=#P`yYdS*F0fgN<7e+<_&Ma
z{>Z(;z8vcB%`SId1A
z>b_bZwl4SU|K2jcy;H59|HKls4ag^brl1Z`*w!f3j-+n|>Clf4wI)eLt
zy{v?;C~$q>mcVn*h#mW`F;4jUOo-}F<^Ep
z_7K>kto}N@@j<`6V2{WXYHKIw`t5e;N%LdsLuR5MRqc@)djt9qwJz;i;7{*IHa}ek
zox)N*d|3%gZQ=Yb(O->+eZ{kS`8;^Y-u@ZA{F9Fs~eB%5A|5{s^5OpHu;MUhCm)&=uO~tAHcNK+B+Ta>?a{gDnlk5Jyx!cG7IhWTr
z=ThfaqzhJj_|I<_HuWz&nV$c!&ct;UieZhYRal!Kn5OBWl&h%-Ws$5q{#CQRYy_La
zXl;%~(F!LEteZ3P$tAU`*T3{;(Ur!i$1h$uIiuvZ$gp=l_;xzG_4MldmzwTx_3xiz
z+dckB&B?wQcVB(&QK!7Ur*UJ5OX?W=)sHVa>rO1J+xgPN&!3(5DErgVTlS|vyzBFa
z2Zd+r0^a<`uNR+gcmKr;FFyYBmrpE-pArAchVM=W?2=ZVT;B2Bd!xO*6aIbQtC{Ai
zX&nou9Ne5_uK2p2b6M{bg`1vu^AK(gLAn+XOK?qQW
zyEX7-xZ42N0K2?PBG)x#w6ij>s)_h^Ev^B_A
zVR$|~$|Tx1%6~Hr?59?#`gBZTlW2K4Ih!6&u%~1T1PvDQB0~D0Y&ICY$(RR&KPf>8
zkY1R`XUIe&e&Dclh)T~+Nq2ydOb+~p;V-d(oL#8Qv*7}NvIro;a^6G)qA(OUAx)^0
z1`XnNh)d%7Kvqf)-nS-kCwN7eq~vr)F%lQ;%umlw=6r~fE0Ufq=KthQN=f802V?1g
z76FE&=OiZ5QUc-}lAe^4#8ZI!hjc?t#D?_2HyH|0Vo5g9XoUg!NXrZ?86JpRY-NSWd>%f9v$142Ayd#4L{(r)_LGiO42)_`
zl9Il`yr5BL5J9yEs_?u^MwCO~Mi8ze)>FtoDF?!oVquhz6#rmkIN=bKeH<|C&LFup
z@caTXMmml;0lC-B4dUysuDfXc9(@Ne7|8AplF{5*R5iW32xi+bo}#fgH7+_ULiWH2
zj0({($Q~T2XB+1P@i95|X~Yxl4w6H$z)k*S+C;QshrshPOuLBh*?aIOp7siz#`7H_
zeqyIVBmPK5&RMvzEX`#SPp1eG7x8q~(4#c;E*c%WYIL|op_2~L5e9ZhiL0B2-d#iQ
zp^+nLQphKr`$qfoq+hf@Px>1I*naTR9BqImu7R4k
z5;0;?^Dr6jm(DA34MNYh4PnV|uqNIins|q5WDZm8IS4;I;#YQ2k#l=QC|jn;N!Rda
zXml`Y=$RUNmWDoBL#N88)`2k^{l_c(R}gnW#JB8>5^teee-LhhM&?9~%t;E}fV`45
zJd-s%Q#ACc8oDV`UO!pBSAO2B8SSg0`)3d$t$l?cI2+q*sG!&
z@gNiRd9G5{!O*ihI)p_4sSeE3=r&)Y+nokcpQ+9)zyOo#B=O&+@E?KuZpBXYg_?R^
zqoFU-&=)fylj_D2yrLo9$WCKlDwmhx)+=_BueR$P=wMKEI}SRHQ;2^Z=rji;JLMaV
zSIAEJLt_=yjwy!E9*(+7ycBm^=f~INrylz{>1@F=b+%W
zEDmAGPHVozL-`*ZEU^@Y9-^^_;-wt%l4*^_^q~q*Sg^kw+XQ!Esh~q$Mq_i5N&GZE
zSLM^Xu}W_TIix%BwAa`>goU$gMNVXJAfvWLJRR`@kNU%WxH~C!imS7trwn?OBA?RR
zB`lgvQ{;3FYtJlXM_J#ZhJ`&^!{1Gl#_quZjONf3Zx4ls!b+-cu=m7EKk8?Q9)pF`
zC`EoRg`etPZ!EA=-6J`-2H(o;iakz~-o6Sy@$^&dR2H`>Jd{WA8hd|@o&%8olqVE+
zpc2-Fun9^Uy|5=DEmWt7CkZb)YG9{)OV-d+peOaa#4|{v+Z~Eb3ZJ9cDP7|<>B`mA
zy}aN8woHjDUt=!{%V%pSUgXt;uspU=u}_3P^@@FxCO_$cN%e%v-lR$Ioxz1HKzTmu
zB1GMww9uSDtyckfh9;oyQ(9;gQm~ysG)aO`aO!b3!WWDMbEAp
z-EPtFM{DGCQ~Ejz+e5=6DfVp0x-BY%QJdg(Nuy_fjeS5=C_AU{4AjsQqWZ9WCGE)?
zdWxpcza4pAr0ATg=zP`{B&S8UW-{nAVbY^xm<8yC$x!-p(%FcK@&eGvo*9+JYGEfm
z10q9NltMRX($y+5l0_@@5QR>CU29Ewg(-BZt8LV>K;5Ic8r27?hix@|dqiYM)?1O;
zE;5+KlN~%djU2tI1Ly&ocmtLECmn(m`qQYltuTh6{$Vfd>R66=XdX*CP#f24o>?@X
zRqLwyyr4Q93jKG0m-J~T`TODalHd=6UkALXiiAJ$M1}>jNQJ+nreAVtp1E^SMiO{P
zz8mrKAHveJjA-;6tEMsl)&Q~O!pAc-p5^HTQe3q7vkLxbuAENKGosUbcU~qy3Lgff
z=N&!Ewg4$giU(6w-hZ_R(s;N7A^b7BWKRP-0;zp<0#cjntYDNv?+PS2w*V=xQLPx2
zc{c^S1F3(MfK;b?0*?S=fNuhO0p9}-0EPkSoZ@L<0+7;?2%vbAfH}ZqAhnScg+53@
zI;=(VhY})RhXEpZi2}V3rUgyxxsJwLO7pc51!cFCM1xV#(06#4$Q2MC62&udxfK*>OOM$oDJa)4BRRQ^+`pS%5U>
zcLA}!z&G42?QW1uyBXwFw;1G-uGm9_#X(9_hi>g7s1E2PyqCnj6g}|J27?>`bif@5
z{OS?xYXNRvYLGD$VD@F$&jO5If&DE&<8thG0S<-#AmE#;uqO!EbqCfafUYO8mk1bK
zk3Bv>3*@y0u17o(Koei_(16z^Su
zsjcze6S!iXLG}XUfv5taa}!4!VC#9hALg{J{U1@adsPPyO}#)z39PG3xZvxqsW%|BIi`p4w;#xLLcJS+Xa
z(8F)OXx(-4*wfw9O8O26_vY)TycT=sihffYg4&FBx*one;_ddgzMqr#!Mud>!IgKN
z{ddi*HAA+}sM>jS;mBtn|Ex>#uj3Z%YyHh1?}+)~3s0|}#{)ku{pTLpW}evgvBU>E
zw;CSTG-q_w1^ItEcDvufv+N%lH|5~7emBoh>O#biJN5TBaWeLx))#i_0`cR_z#!fg
z`Y7w$^7>~}r{UoyzD$>=Wd{Ej6iEA<>nfiqj~jh^V!vL|9ccs2CzbV2
zos4?#od;GvbkM%*KBoKh(#WdGdlp8$D!+5-!Ue?l$|bvf_;UfFQ@V7iSqWLXS^GEH
zKI)vc@UNa(e<#^Gb5PR#ALgH*FsER&h%0_=!A|?3qO2v<_0Vt6kBwJ8nfHCYM>rXK
z?5RalUq4?HtGb!~jhc3+c8&A7S>V0Bf8O?z-_63FnA!Vp8aIpH(&t63oAvqor%l`}
zV{TJ7Ti(pAt6{rBW?p#l*NFCyp0yqL<4=c%zG}@2T6d+(N3(93p1WhQ>)+?jyZ3Z_
zt?{WBMjLfc$G&m--n6bg|NPfBj;np-50lzTPd;3`F>uREF{{j99R1jH?AhK^?*(A|I*Uqfi-sxbDmkA5ZpSftzH)t7#b4ZhP5&T
zlz8p4DUYHeZ6BUGJ1F#)1sC4r{fhXrko=x|G3)U8kM>_3lhE7!)R#}R{i0^eXI%n&
zTFCFe`rQ=CyrL*@Rig-5$xkIU_uDvdMf&~5A#>jO<`ohTvzi)l!*y#J8
zcz?Y4L{M4ZzL9mI`)(cD^OgZuD&og=Xfw31$P;RPDRfrVfHz)UR2T1l;IVTDx870O
zb%$%^9k2djy#4hq=N|Y=@1RW|)C~&1=&GL;(dqEEF2VL8-E-z<-}?N^yHfUqMGqUh
z^Hgr$i7ivVcMd53X7PPqr}^>f$m-*@!TQ%%;iiQ(U)%Gy{rHEUU-_ZQVY9-OIW8Ra+vZM0U|%vP3;
zbN91V2l7`rTg5^OappdReo`(@AOcB(cb-c*yZw95z5g~pKQ_Q(6B8^UA+gB`9z>~}
zX|y?Tn$TvET*Y)45+`}+KpuWh7f%1;d=72Yv|0p_PP=8%2_y+8*{$#$AjxC$`Eds+
z))kNKl?b97{L0D8NXwD(iqas9?kXUeg*ZB7#kCCiZkrS5iswnn?FAt9f>D0yICRk_
z^ro*vXvRp|i^GPJ*>0ng=S#|QV`;d{>9NrXvurC4meZvX!*MiGN>^@+!1-Kp
z&qM}4`dEphd$ciJ1;zo!}`h1BcaI?nG1rk%|FQCOL4Z)-3L~u+LKj
zh%lU&$EC>g5nR4=y$(8h>$&m4UW?7+vKOOf2xgq@^=-iBq3Hyz!qepRZsOqo%voQ4
za0vMVOsNKr#E;*t(I2%VLmbld5D_UOC=`{7@*cSL8n>W)){d-KD%&A2ll0Gd0$3nLb=XKWB+&
zKDu%@g5nle!6*kRQ;%*R>(>yZCXhi93XJx=m8$^IEGx|3rF`VNEMYh4O4<+
zhRt-z#R*vD387xV;EUUr$8&9^HVN0Lp!-8T&}6kgujrB$9uX>u(x3X|`21SPV_x1(
zlI4)JSGzztaq3Z%f0f98$fRops9N%CgVNCjDF;@3@wUWQ(j@)rwH>6Pkftps2M*7x
ziM}TH`7wQe`di3Q4GWzD@jnV*PTtzuo4*)m$d0+f<6pYPctkQqBeWbZeQ93Cj2HRLR>ElJbj_i$5L`taqz+wZG7FS<@gi^P55SfZl|+?BDhX^
zi&TGKI(hM9VCRz~2-o&CM4xXfE3x{kQIjx=pF`=R{M83HplS1>iH9#5fBe^LyL3l@
z(&zf(_4OB&i%qJ2b9uy|2B)IInYn_j{Ir6!yurrVa!KOsI8wYX_rjmvsr$RveLa5v
zBg&d?!|e%)Ny#aL1`ioJthmIC3yp}=PfJVBFlJ_P8t!5mTumcS%wZ&nP0T7Zr4<%t
z78DIHm3oepawp{EkY81)$3)}m0a#KjWZRc7ZsT@Cl;B;r4`=6To!+>St^Q6M{2pRc;wjYQvsD>pVwDcVsFVi`Q6v
z`be{_bo~an?e3|ZW%_{9N(U;W@~bY;@iJPmT$GhczjBXouks2^RZ#WcRVC=17Bvm0
z`u|>hTG8Y8hWpR*docsH^Ls)^jpUO=XK9?r>#j88YPb?w<22ziE^A-LFYM7|bX+CY
z43d*f-o9uRyiSgi{4~*uaT`;WiL9D%6`nGm3rmxznnkGksQ<`)Q6rUWg8GjFs~E6M
zwfPH+Pqaq(1EE~$a#lP_(CfvKZ(qjiykIeA7G_K(>huAinktHEodscdR5sq2@NV}B
z>`8)I@GRZ^pyOFN4Q{f~S6hDXZ)!$fu2hhjF&&*UxXI@p!JqJPu!4*LyWt_K!ONe>D=l{#U?
zF_nf5u#;*iNwdl3o}=Cx<(Wzj*SLv1Ttl|BvvQl|XKbSqqq%0cY
z`!c>(TC7-mv^mg8o9(lu5hJ9b=(?_rEjcSIAwi9;sSJ$aY>sQhB(@|cD=UK(
zZ%K~3C0&vdu2qI>q7i}&YpM@d#a-%jXj7Hgf+Psx3aRQek%J7OJASW8SIcq|5};O#
za@@F>*Xz`(a&w8&rio-|CEQG6wBfzgc(U`<&`O%WsBb1M7%-skFcsyQ?#P@Rhi7L&
z=D56~Oin}xD)pD}WJHfD>L0o|(`@TJ>hmy?vRJE?XMNK$g0HK5o&z%~)VHL;*OqZ2
zuO|MAf-=5A{l>t=U%%5bk|nwc+D+pp8qn}w7kv(1UvPsysb?H5$+}H=C1s)6Y9A>(
zEyt9WkzgtsGcL2hls=}2k5sS6mw1zWNjJrpo{@V~eAIxOGWLusvpT5T^d}@&Mt^TA
zkWI#MX{O9^`9+hJ)ZB>xMxy(x}5yFdm_i$TXPl4>o-^fppE!
z0{%dv8n8!deIP%lIuS_cQ%?eefV+WoSI7V$re(Ot+RImrJa}QF-uoFZ;l>=SNz&Ei
zG=@;$Dbp3L!+EzdHMVlPWX7aUGAGjClDX;xPvymnLR`cx20giKaB-4qtD9@Nj3pqTPxtPB|MVCS(hR)06#^}X^_ef-~uvBmd*|AQoUQEg`IVjU{GQHG;xk9DM?kHCHxptDI(A^c)Wffe`HT0JGOYq@=7WiGWEm-9xeVWQC
zwwSNw_qsiEO;}23f!|Wx0zdTkIz8ldjeK`?No8pZa=cCHZ9+wPNm$5iQhi9GQkclY
z8~8P;wnB4FI8Bvq=4W@RHJS2(Yw8P!LTTcu)dgu*+Q_xxP}UGzWp>g`aSo~~T9Q8@
zye=sIHe}lM{5=+IZJ?0NBH-c8;#sbaHr@Xe(wq)1T`^;S9
zbckq)%SYn{SCD1OH=+>(3)2PWOyg#X_btwIfl=jopn8V`RU12a$
zFcM6>Vp4$n;eQC`ILx~+r(n*&oP%kA834(-{KF&sEfOEJDXYZ3i=O%F>l{l7u5-p$
zCuk!=rQ0gL{D6+sB7A6#p$SdY|6=+~1-dnCt`ZisPg8}p*dcm2&IBIpa42@0%l*52
z3h)^Z+JQv-mniWC8Gh#khqW5Fn$yl3^IWAh<=~Q4huO_Db|8p4Y~HXJ+28w@bkAjd|h98i!52Iz3yUsNyRZdwwJv+-uEWh
z)|`Mx7iWP|)KSt>qmYU9LAPm8AZOiKfIP?!m91h7wpvp*-bpHEibUW)$o(
zsHV4G_&f={C*d!@kOqFwHWs2mr`ICruHD#FV4({{$cr+gDGiN{r?
z{AB9Rdv?CFv(r=4pW61+*H0xqJ@5ZRY5IRU!!^n+UlttMu3fvx&6~PJ#>B)#KDD!7
zWO8zHsIH5RNg7u}BW?7jyN798(l3p4!bo-f*oX}D
zxxU92;)E0(@JGIDcnYo{grPK$Ats8uISo7R
z|Ho)H#61Uwx_6~_XX4urc(zH}PG8J9s0Rl-=0^Amn7dT6(6_{t`H1qo)P$ewbkA02
zSIVa}@Hq<#kB5QEuHlD3g(}5ie5Bk;LW?5aYTq{}@cn^eho=JZgG68d@M1#%$y9mh
z>k|B~)9WybXMoQWTLPdP=7IEbm%e*N-%b!R==q`H!)^asKKedZi+qlzeDtjh;=>4-
zTj-BZEaEKY-@)KoL2rsv`R0I|f1|9p5<4-~J6i>>cp2xyt4%*ELSkbiZBx_+5d3C4
zib(mcl}~ny0aRUld3a-Xh9@Y!`Nhsi7wlr}B=({Z2_K8%yJ&G1iawX+XT1S0y?x}b
zmKlw*G(osq+33_Go
zT4vgBYQhI+D9wEDDeN>z^P)v7ekxrh3%a+u%8F1t%v?KmutN_}utQPx=b6yNUt|mO
zy38gno5HE_iYHl9Z==-h$g;|1l`D=
zJm5bcZ}dH0+O3EAH;yMz7%SfcE-5=KsD<6@n(_E(em-|46;V?@g{H2^U^5V=#5k`>AYq2Y>yLyN4p_+p9egy~
z5)&?@AKtOLpgr>BgZ3)?
z5s`(LEj|*1xBf(>{sK!SrMTOiJn@YUN)K=A;_2xS9fdO2;{6DJs&cwV`No=PmwtNr
zb?7QTEny6oELCO230P?$7flec!U;-Z6N+f9S{~7#Xqcdyr4*+WEM*BMOp+8yWr+gcJ9*QQW-XElwg^Q6cu)#wE|N3>Wv4>
zlxXI31cN4s>L-KPoiSJir3RM}gHJxXurj(!qWXQk$}w9y&OXm_GqW6aq9LuZQ+E0Pi8DYZ0l)4CD5LB&^b;VW7Wt3tw>
zF0JR{43b6yO;UxE>Q0Q?A1H<@
zBzI8KX-uYRCpb)kce7T^&EIqVRq|ZBNJ%2_IaQVh1FZ^40_wcOVDpF*Voi
z*HAl(r!8fWLWi2-C3;t>ysHp>Cyqskz7zc#z4znA!PJGjYk9a2XHpmRuI1rAoQE&;
zA%CvrAs-PJxcQ3TwLFRs*otJaDA*DY`H-Znyn>8OQ(hL$4x90z`H8qhKZh}zI%rcm
zOr?LLo>Evb=o7sUp4rt{rBe>h(V8|5Db$`aF)>l6=r4`So{u2@c_;cWI(i41vhFS>FG2*v
z_CjiU9(*~OVUe+tf9bKJnB?Mpi&%7x#lQ~!#a`?qi}m!S^be#ArjG9C2YW)qF)aOltEn(gId61)p_nLwa?<>O=YN@Q2YHZ<6Y
zb>SVU!z#sbnrAMKAfY4S0iE~=Hxj9Q+fy^yQ!*Om;hW5;;9rS1rY7o$4zSyKIR+ED{0z+-~ezls;c~!NV%x+a#O5S-rm}EQMBa;X5`ldL!9OVr~3sdH%
zks?V=V-PI^v+!p0W^o~16z*oDK|WkF=T=kLk{8b_QTnL2e1^`~5t`52n`{-dM>
zi>-{B9CiRE(5|2BZ9PgD;@?I^{US9HTCedTrZGff5H#ClvGX-7F(;B-m1Z{$sl^6H
zJhe4%5XDdwi#^H9P{`DV0P~EgDrJggS
z9+$8G`Fc>bALdl`gPxdk^0lnefo}6agh8VgZ+|Ks{v+cwHlg7iWeCP-)y~;s$OtQT
zNvU=*-o=qm79$3{7+H()E-ZYw%l%v~9Fi!tR3O-Z#8S)v;I?=?9^vMrPLUp3KNHEp
zx9#a1ET55EFq5a^pgs@%BaOK*#KO9n?|b$re~XK+Rq$Czf)vN=C3*vXeKK}M`o>dM
zldoiPIv}seRG3+WM3y$8i-&@`cSPgI>xZ^3V}CKW)6u5M>sR9}`uTPPHr@N?D#lKJ
zoP51e8%WRu*2c}x7$RUxTPtZ_rDlsJ+KgB~rIOcF4?foM`ykgxPEA~pv>wLAkfu{oFADuNJ2S~AKJJB`*kXvl^)R}P&~B$+HyRq5059|?ja(Ml!Re}
z{c%{zMkXiSL`>8VBql1~J8mIOs?YyzToP5Sky8^EBu+=^JNRZ8{>s>aXSjHGOh*jS
znfXTtq?>PDTBr$WMN35j;IoW@(WOmu{$mR8mNL1H}L@1aQnKTh_iNlE1x@rP8rufp$h(4{o278&V##I*LMt~HUHuZt<`X5`i=j5UHXoOBTD
zW5SPicwkKATS)Y?`2B6zi=o`wfbUwXBFJB?sa`+4y5`zac%RZp9LZ|oA?1(E&(q{t
zs%7B%YS*+io{D_U7|HKRel2<^aq@LFSIKOXvMxsaJ{s2D$gMmTSnIZ-;UR7C^)KcA
zwzOqzXV=C?W3rB4F8|hrtEUfatSU;1fNUI>ce=3(f=>g|ZhBa7HwsqN(8npGJSO2i
zqQM!#62LxlFzjt{z906fID})kkihLpQ^o5q&U+v05{K_b2D2JA6nr{dZUwt;XwP7V
z`{JY&vInHIuqa`V>k9ushA;189~my@f}JJkBxaN#lkB+Req=Ajjw{VZ^-=6efrdy-
zn+^9#ZQ^c2xJQ$_WVelsGz?f52|M&^%hD3z&+XW52Oa~`A`wEZp^17Hkzsr{m`N-Z
z?-b9b;(9nH;oF#ztWE0iipUJEH%|kl8+^KWTgm0fDAuP6oW*>E;=*Qgp*_3A^;n6p&d|`ITO<~9FWFlM#jW8qmVmHnYr*Rbg*hhh+(^SV@+Uje;IktQWWUflDQ-LDUTDqzdp;>-oq5jq;k><&
zx6c^iJpg&YYM|>+klQu@y0d`3{{}C&BaYWpJJb2;h|f=FeGe%-lut+l!mh8Tw7i9D
zHQ^WhmN8;YTfJr32e|g|YuMoq{;M%!9llwbuqBSgyz39&w{5owg%sYLs@;zSj{I!$-q*1xg>uEnRpLA6rWTcc@F$kMv$2d
zK3=zZJc5?gKs0K%I+pZ3**knQh4jCSPow;Zu&`5Dk+u%;V}3=tIK6`?GlVm=ZI85|
zO!0kKgy;M`E%za8>wkY0j_<$@W;FrS&QrqB<^yZ=arowI@O_jA2#4>y8eo??aEy%W
zNPdt>IzpnNYV*i?(2a52YCnD|Nj0r2mUt){u^^3V0G{z)3hOM
z()&ZggmD6$VbkOxtmy3_VZu0p&aj!_lbiDujbP*69??da`M~*Y?B-Ey#{SfBGSl}j
z;fB)=fCe-D0BA5R(JWJqY~rr$2r?6Pt>tDKZrd$<)Y-o9(MNq|LO}r=x6#>7n2o@V
z?WRwj%!T1mE;XFY
zAdD~nMBY*UO;%_*JYNOfI&mVtl{vqS*36tViH+a0By#+oJw9VmX!#ntjcB`E{M{@a&RsR|{#IO=a1v+-AqdUK6hi
zc_6>BHiFC~#ZbMM-$T9U2KD|uQ67^}9%QI2eC4ql4a$5Y;+Qak$nY>4qaATQxEv(YgdSOzyY%Ye(;PVU~F_`DB;{>hC!tBtVFkKcFb3=8lM@4oktyx^u
zn>imE(@JYrPq>whuDi9>c*P8>8`SE7iG5l2x_*HZU;W;~m)dSH;&uzJjV9)sBlBe8^Br-Yd+?z;5YacL8O!_C(a
zCgB21?6d|^oO&vt>(%^D?5US%%Y+w)PMUZ_jvBzU|^9v+nVm&d+_WR-dDm{rPzL|8aCzd{T
z-{PGkE!<7Q@6+?e-hinX{mvW|h?xMR@6`P(?ZH9y>wvcp`s`V}{W){HaKD3f8T#c9
z6L;iZScos%LB=6P&QA+BiC>pa6Tf)m*??C^tSP`*ikU(3CEP834)zq-mxkfnu!TW#
zHtbtKkAz)@J-ZFQ(+%{(oPd2M=(VsP2T#rFAbAxL5t&AbA_?
zQZcTELpfvh=M=s)`U4Fd)*c+YlruYdZ>JT5T|3k`ink+x5{tM=hVd
z(>v{~k8yX{PD~1nkd7D;Y3*&KTTy15X+f>FXYHV1P+IY^Lez0=6cOzn2XJ^uE3)TS
zC4jGaeEaS9?d~_>tJJ-x?mhRM|DO9g_l9}`c~8UrGF%TjsdsL}y%nyReo$Y(0Uh8v
z3F$|`T?f}60^u3lm%;Td*wxSBo()&pBftdizl5t8!ewwj4Og}jWQTh*T(^LKaxh__
z-Axe%uMvi(2%Xw&z;{zL{$3m}hP8xIqSo~n7!={mWTtQY?39dRx%>vYbC{2x{gp)CmTzEUJeTX6~F`H!qg&uZ=-giWect~1U19IlZAm@g#ZW%iZopaF4
zRma8+DyAba-C&4AP~Cbvk71azq&Z1t?g8O(rahvoQ=MyQs;kj*iFmyQt3N
zyP!;Rjo@UqlJ&vu-}foCd9@&fVU5{r<*6dQGU3#kO(vlOq$;WmN?xgAnCAQy=?-TG
zZQ{Z`2)G9lY!qrkDn3xdL*$8$YXt9L~m8
z6tbn60-5A4VM{%Y;(b6*=;QJ@V_c@0#s5`>Kq}~UIa?#*8G%O4+f!;>5tvxuF4sd(XLAd#
zI(!^rw%znd95S8hE}rFHX+uM>RsBe!#yFP?Hjz3Us1b`KYUQ?6mv+`&LW(u!s3^*m
zEI?T_l;QM%D^<~epJRFhuBpKp=gtd2v(nsb<@?_!;wy--S&yNWN0~l
zUrZ8c)8npz>l|N{KZG!%9)
z(Q;HSiSt~a1lj}g&^p4-08U(RK1NI@X|~*~47z_(OK6^5_qY_s`j6bL
zeW(%l1xT6yRLW6Tak?Gu2Yu4%&H(34kFaz=^&27x1D|x^*btY{-u=W*w>fMA5v-{a
zu|Au2ny!xZVm;EWNGLIIWV903Q-Enou{uY|!
zM30l`j!$;`%nQ(NC|y+9~xi@=>~XO`_KSO(4_-w^}0*TJa~jd2Lx@{lP(KrHkxL^k+k$VT@dyQc@){2pZUUE|iM
zuWPPNtNoQV)@nAC*jAxXBYh+7%8binZJO;(=)wmURxewHqF{6I7L#-~t;#9inlv?u
zN()VjwQ>OlLO6mV(lVSpwRjreghs6+^pRje=SDR&KbWrOm(IL2Gi7ecT=l%jCDN!s
zS6hq;GK*m^`96xZlJ4UZE$n5IGCa`5hqj>-cBwwy9-mNvu;pRt(ymOajkT57Mp{E*
z&a?{AH#FCdTA`%%S}0kQQO(2XwYUjweJ^dhg|&jLnkprtxoU
zL0)+RLFmU7s3;xX71Gq)ZE0xjD2N*V4~)SYik6HAs52-1dDzQ6~~^qZ827mJX@OQLC^>M5vQh7Ig>`o8{bD}
zgPM;{!V%$87I>mSen;}
zoRuBjEsprSJ22ADb=mIX^dD!H?r2A|9OK<{1&upZu;_uu=F-b~$l2N&n4eubW-F>W
zF4lrl(QImzofG#
zTwoWkH8nc`v+Z&jYn4+9Jo7EhWM%c;F^_ot3E_D;PfRGbj&3j;LXE2sw3oMVZz{>D
z+Q4|_97;GtI}vsM7PH43%${?6%G^XrXUS^F(fmn^)
z1?&x^`>d~Y4`RA_{nZyp*Y7Fmnp0jR-58KgLA+SHUqALqm-81%cfJ~0Ge}qQ0_nJ=
zM*}vlNxLwuI&$@i)#}TdOEb>Su9|mxk$Y(cU0ZA&X^qQv`VT}Z|K>oI5@s&pP9-9{
z!Y!3!2+OGo6rZ_8$8BP%(hXyX+$JZCa&|{C!*w>2&RKFo!z;8WRwivH8tQ+R{W!P)
zw@CHOZ8OQa4^o$=T}n%tQZhyT7H*Z6%Ao{jVr8Wph7#tc(#+rJfXhR$-dU|k!;eec
zv+_MxY36d7hELBfopqQzV7A9wDl1SiGgY7rke{VcmcRxbseih!&|FHp(1bo8VPS{L
zEqb{e_fJt^uThE?WMRk1WvLQ1AS3Zy8*;{hxug*sKMH0BTN~!|uYw*d9
zWqr0klFE2rV_}y;8Tx0+SPNy$e5#E1hrFnaAAZxf46Ki{gCP%@1%*)tkmQ`2Eiqoa
zEi+mP+2rkn%z)cl6l`Ft)=}iAfi3Ww$&Dv+SR8VCGSI>gop~8V+~uU&wh-Lo@CNQ~
zF06S&kg7cfh2Cow(R14PD%Nd%t@gaei&EF8!T)K!84dk6e48fFRk+9LKOZ@
z%|E<#RHxDJ&_9@)#?z@wKyFx#<+lQl3XtbA5k=&XM}&SxZWr`U#@j$^C897FqJ_+H
z!5U3WD<@@>Lr9#~ECl1Ua+z@`(8iFyw9&$>592N$5|+|-7iU)>j-f!av6tg&&4yf|
zkj77c=TeOw2&*Tb)HwBhS5xy3?h~mn_f5@r4Ovroc3;)CGCaP=Wl6nM)#+;YrHYK|
z+LMcJEWN(s+Phc&sdns^@wTr3;|u8OUFi7;i*Y+)Nt289WM`e<`;(l-ALX!ZAz}}V
zab&qWd87EbMLB)NeVvzyD8-Cm9%Ppf6~Fl{L;G{07>B-$mpM$s~v=
zs(|J|;pc-8HPxA=T+FSQpdbwGx)u6by)pG@swQnm8a?H~{G|&nEl62dvM{`gt|
zRX<4C>I9d>9^n>qOyI2k@}IKKIa|;v=yRQ6TVS4?R2^?!oy`4XHtA%>pq5>$pq)DH
z0R>=-#n1{0IoV!W8n4c{!5@5G{gHZ?IzLe;ZPXJteXA7`n7;AMtP~ioT^eP7gKLtd~4(Wjp3?|R|7dh0kadyX6e)i
zbC=G$G%sa-$$a&KZ41bS*nXi!60+1~B7!y+_g1T2YH0J0rqyj079)8Z#oH$&wYJF1dbw#gP~g#EOq3xf
z%ho81X0|F5qWz>&w72E3dWRC^@(37@CvqXuDpf2U^5GJ}oAHcnPvTLz-Rs9x7iPB;5vjgmfa{ciFe{BMcO@
zIwCmjv{r%S>ESaf;x|SUBe#s@zvSs^^;u2TH23V2W369WOSXW_*NSbLj6z9%5BP20
znVnI({1}?Sj~+UW$4|gkYkj;+Qq^hO(xeiwWr!Zix=;Qy3VjCSgyiA-N!>RWu~p!j
z2tVQx0Jy6@F_*0b=sOUPXW3J$uI`zzRmGZ%Pcn0r;u;y@~h4
z*(;v?&%QM8!lG)t&P%&u(fg$M)t0!dqgms(d?m^es;$nLAdXEXR_>m&s8JQryU#mq{2gCKLHyS#smA3TEix+rgiztZXwW=d{6Sddk&@
zrU#lH(~^TrR~~`>k#=M6p*<_sn%h`nRcsn*J2TPQQPIui=i#0Je7rv2ppxwbj;+A4
zMp!+url+K=S-6y%o>CwVC5Z9um55-2_bVs2nX=q%CZ36BuITEiD^IX*UYe`YwYXJ}
zbjMZ1T0adWP+o*=Y@?~}m&IU7EyVHo5<{WU%#O?;*g`&x2j4hFX_6CTtujLkkvl=d
zOX(LEgZ1!u_KxR;8`r#;tEouh8ad&4u6rY*0#_zL;xYNp*!1&x@l=3a#UnXj5%
ziB#)p+1qy2?3HLBGkOcGFX^`(z3EDHgh6c6YpSkf+$g-h?^<>3NE>y^%!a|9gNlhs
zIb=}LqhzHS0;xQGN5>7>Pmj$DU{$n^IXK#=5$yP1&IGW7D3>95Q
zy@evFJ!5g71HPWRZ$1n*=ADv{bwXD-8J&u!?l~zPH4J?m(av()ib%|N1WMy`Vb805
z`ihygGmUeP&Q(B-@=X1|SGH4z`$CRO$oS&E%FxzLuz*b*7YbTJY?CRgvcZ&S-@~eY
z7K$h{C-XxI_Acn>I|92pDCVYXWJWRciDv}(ttaf^;41|#16=qAsQ7wWoPuZg>gT;^
zxZ_I;7o7D*a)Ow+BEMVq2@>wfn-EbMG2;qN#vvu4Bqk8QLH|g6M}9|=)A0rp0f*8F
z;ui!3yZHnhTz{iGqI-jk)WOxfmC(@_VAg)uB!k22{~eyqFXTD&e?rc_JWv05-ASMB
z0K^;J1wC@M5*HXr_mHRYe4Zx(c*^_Y`7)j(h|lGp%PABwEo8t`b@V*XKT}7&a{74Q
zHG!OnNc?N+{b@P7dvy2ljF<-X-WSi4K0MzbpR*+}AF#n*TN3fy+g*kb30IJh=Uvn5
z=&5@D3wVlhhGOQpj(T}+CGN_6b=0K8|7i`OFNTonCLJV(PuZ(DJg`rAkQfdbjOpQG
zcohyWmhy_}7x&4#xKG~2VZC`5_u=z?pY-qdp_}^THTBX@d*%EODEG8iPAM#l}shtJ&7Cv!`eo
z0`CjiQ{+>#O&eViu5oiZB*oBMV_y>F;9d>*rDE6IRH)<
ztf!mf->pJX`&iZP6rAs>WA{lX^tAavw2|y8ntykISJU4y9hgDy_k-)7TfktjJ3_u_TXv7c=8ho!4!Rt-Lw@whfh)@0^77*U~}Yr{7sFtVg3TlDkvV!&)4Quj{ih8n0_Ld_Hh`T6UK-AXCFglO+KIe``*V$)!b9g9>tFFaiNscO;aEX9zF#lRY$R2T?zMv!91;e8
zUJvuHG1|PHFjHh!eYJyI;*mQU9bJ04m4wqnOsTb%#8&Uyv5LlA7E4?T0uNf=a}CFo
ziY`IqKi41#?zMM;=i0A!)UWkC7TWjTgP8tkUj4F;_Fm4-)WVl*ydJRpD)Qzt8j~J>
zuI>&A8dDyB(3tS}fyRLzB(+Lxlc2ZEVkK0YBTOR+?+blY?(@bE_QuahqD@;78fn`j9fO7M{go
zs_--xO9Tn~PM3D?x35ff<+9xFRun%gmpmrWR4yAotBuSN6lSxK59gckZg-#h59_J_
zO;G;_eP|%LxBh7l?L`A{05tqO@)w|?@W=rTAIqA$(ZFf0^g2
z|59jP%FyPNb+A_)Eu}SGbZNDtrSOHDf{HN(;M&(RB(|92=Pa{a+L%@(^3^RDf*Z8a
z)B3~uu8eX)TURxp;m2|7CK|Lg15~5&8K#gn=nI37U@D|uXH!6GlS1%?8jcac*z)OW
z+zy&9eDiVmeGAxrILoc-Kw&ZRu_~shztYeFd#Sk2wab^1z@gxri@1k-yWNwrgrZ>w
z%HMd_mkuZ
z0y!G-Nh&rNc9BAI8hs^29^$qa0V3y)DOijVx1$mHFl;M*S_&+|$1K;ctv`3ahy?q*
zSwwwk!?f35AIxde14d+E%=1_774
zd6LBA$cSWuI-*^RM)?89BO`(n7wB-$c}5swXh@LcyC*1M51_H9Mk$*iJ|FfApha(O
zZ0)V*Q2BugiGokoP$Af`FhQ!D$^q-1k~|?OnFu~2PQTFaN0aKAaisb`;F2i+`@UhS
zFMj&RpZmp_0q@=U{S68!|M!XcH;Mj+!2e4G@b6^))aU>D^HmqnJ45%Ncd(Az$HQ+H
z4#IB(ivRp2{l3Nb4L%8!{11~-;Xg9G^z-MQ!#|*ayydR$?lSlljj!K3T|%ng_#M3Q
z=&(%vzS2jP{DMDL!2b(UpkVlybUmLpnKd!kDJb6M@Z)^(1CN6~XC!G6!gtK6Y$h=b
zdjsy;NOdz@=x~J`zcUtoZ{PF5!4V0h8ef=*^M-go1H?~IkoOj3g6G&Dc^H1wRe-Y5
z&mepneFgCXv9`D1F$n%c2YLwa
z9Kb711`QTtciA3U@a_5#>i=B)Z&>wWh3kV9|M0sQWN5P;d`o~KzPe95
zy8G7FpJp|dzHQ@v5fw#R2mQ2o$qy#Hy}v=5`shqmz@UE^(PgOr=uXSR&yT)(_^a6I
z-`?xLd&;6YL(lFJ=6;dcU6;OAGx^x5KVIEmai}IIm`Dj2SMzz^$HOi^*!5Z0vgLI4
x@EuPI*G&E6!;$a&w%@!Tg$`?5%T!1I`tJwax$xT&*FhTi{D4$<
+#include 
+
+int main(void)
+{
+    rt_kprintf("Hello, RISC-V!\n");
+
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/bl808/m0/board/Kconfig b/bsp/bouffalo_lab/bl808/m0/board/Kconfig
new file mode 100755
index 0000000000..d9ec26766e
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/Kconfig
@@ -0,0 +1,16 @@
+config BSP_USING_BL808
+    bool
+    select RT_USING_COMPONENTS_INIT
+    select RT_USING_USER_MAIN
+    select ARCH_RISCV32
+    select ARCH_RISCV_FPU_S
+    select BL808_CORE_M0
+    default y
+
+config BL808_CORE_M0
+    bool
+    default y
+
+config BSP_USING_PSRAM
+    bool "Enable PSRAM"
+    default n
diff --git a/bsp/bouffalo_lab/bl808/m0/board/SConscript b/bsp/bouffalo_lab/bl808/m0/board/SConscript
new file mode 100755
index 0000000000..c0653a14cc
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/SConscript
@@ -0,0 +1,9 @@
+from building import *
+
+cwd     = GetCurrentDir()
+src     = Glob('*.c') + Glob('*.cpp') + Glob('*.S')
+CPPPATH = [cwd]
+
+group = DefineGroup('Applications', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/bl808/m0/board/board.c b/bsp/bouffalo_lab/bl808/m0/board/board.c
new file mode 100644
index 0000000000..5494c69eaf
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/board.c
@@ -0,0 +1,221 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ * 2023/01/17     chushicheng  add pin and i2c
+ * 2023/03/15     flyingcys    update bsp file structure
+ */
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+#ifdef BSP_USING_SDH_SDCARD
+#include "sdh_sdcard.h"
+#endif
+
+static void system_clock_init(void)
+{
+    /* wifipll/audiopll */
+    GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL |
+                                                    GLB_PLL_CPUPLL |
+                                                    GLB_PLL_UHSPLL |
+                                                    GLB_PLL_MIPIPLL);
+
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_WIFIPLL_320M);
+    GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_CPUPLL_400M);
+    GLB_Config_CPU_PLL(GLB_XTAL_40M, cpuPllCfg_480M);
+
+    CPU_Set_MTimer_CLK(ENABLE, CPU_Get_MTimer_Source_Clock() / 1000 / 1000 - 1);
+}
+
+static void peripheral_clock_init(void)
+{
+    PERIPHERAL_CLOCK_ADC_DAC_ENABLE();
+    PERIPHERAL_CLOCK_SEC_ENABLE();
+    PERIPHERAL_CLOCK_DMA0_ENABLE();
+    PERIPHERAL_CLOCK_UART0_ENABLE();
+    PERIPHERAL_CLOCK_UART1_ENABLE();
+    PERIPHERAL_CLOCK_SPI0_1_ENABLE();
+    PERIPHERAL_CLOCK_I2C0_ENABLE();
+    PERIPHERAL_CLOCK_PWM0_ENABLE();
+    PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE();
+    PERIPHERAL_CLOCK_IR_ENABLE();
+    PERIPHERAL_CLOCK_I2S_ENABLE();
+    PERIPHERAL_CLOCK_USB_ENABLE();
+    PERIPHERAL_CLOCK_CAN_UART2_ENABLE();
+
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 4);
+    GLB_Set_UART_CLK(ENABLE, HBN_UART_CLK_XCLK, 0);
+    GLB_Set_DSP_UART0_CLK(ENABLE, GLB_DSP_UART_CLK_DSP_XCLK, 0);
+    GLB_Set_SPI_CLK(ENABLE, GLB_SPI_CLK_MCU_MUXPLL_160M, 0);
+    GLB_Set_I2C_CLK(ENABLE, GLB_I2C_CLK_XCLK, 0);
+    GLB_Set_IR_CLK(ENABLE, GLB_IR_CLK_SRC_XCLK, 19);
+    GLB_Set_ADC_CLK(ENABLE, GLB_ADC_CLK_XCLK, 1);
+    GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_XCLK);
+    GLB_Set_DIG_512K_CLK(ENABLE, ENABLE, 0x4E);
+    GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_DIFF_END);
+    GLB_Set_CAM_CLK(ENABLE, GLB_CAM_CLK_WIFIPLL_96M, 3);
+
+    GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_MCU_MUXPLL_160M);
+
+#ifdef BSP_USING_SDH_SDCARD
+    PERIPHERAL_CLOCK_SDH_ENABLE();
+    uint32_t tmp_val;
+    tmp_val = BL_RD_REG(PDS_BASE, PDS_CTL5);
+    uint32_t tmp_val2 = BL_GET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN);
+    tmp_val2 &= ~(1 << 0);
+    tmp_val = BL_SET_REG_BITS_VAL(tmp_val, PDS_CR_PDS_GPIO_KEEP_EN, tmp_val2);
+    BL_WR_REG(PDS_BASE, PDS_CTL5, tmp_val);
+    GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_SDH);
+#endif
+
+#ifdef BSP_USING_CSI
+    GLB_CSI_Config_MIPIPLL(2, 0x21000);
+    GLB_CSI_Power_Up_MIPIPLL();
+    GLB_Set_DSP_CLK(ENABLE, GLB_DSP_CLK_MUXPLL_160M, 1);
+#endif
+    GLB_Set_USB_CLK_From_WIFIPLL(1);
+}
+
+#ifdef BSP_USING_PSRAM
+#define WB_4MB_PSRAM   (1)
+#define UHS_32MB_PSRAM (2)
+#define UHS_64MB_PSRAM (3)
+#define WB_32MB_PSRAM  (4)
+#define NONE_UHS_PSRAM (-1)
+
+int uhs_psram_init(void)
+{
+    PSRAM_UHS_Cfg_Type psramDefaultCfg = {
+        2000,
+        PSRAM_MEM_SIZE_32MB,
+        PSRAM_PAGE_SIZE_2KB,
+        PSRAM_UHS_NORMAL_TEMP,
+    };
+
+    bflb_efuse_device_info_type chip_info;
+    bflb_ef_ctrl_get_device_info(&chip_info);
+    if (chip_info.psramInfo == UHS_32MB_PSRAM) {
+        psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_32MB;
+    } else if (chip_info.psramInfo == UHS_64MB_PSRAM) {
+        psramDefaultCfg.psramMemSize = PSRAM_MEM_SIZE_64MB;
+    } else {
+        return -1;
+    }
+
+    //init uhs PLL; Must open uhs pll first, and then initialize uhs psram
+    GLB_Config_UHS_PLL(GLB_XTAL_40M, uhsPllCfg_2000M);
+    //init uhs psram ;
+    // Psram_UHS_x16_Init(Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_PSRAMA) / 1000000);
+    Psram_UHS_x16_Init_Override(&psramDefaultCfg);
+    Tzc_Sec_PSRAMA_Access_Release();
+
+    // example: 2000Mbps typical cal values
+    uhs_phy_cal_res->rl = 39;
+    uhs_phy_cal_res->rdqs = 3;
+    uhs_phy_cal_res->rdq = 0;
+    uhs_phy_cal_res->wl = 13;
+    uhs_phy_cal_res->wdqs = 4;
+    uhs_phy_cal_res->wdq = 5;
+    uhs_phy_cal_res->ck = 9;
+    /* TODO: use uhs psram trim update */
+    set_uhs_latency_r(uhs_phy_cal_res->rl);
+    cfg_dqs_rx(uhs_phy_cal_res->rdqs);
+    cfg_dq_rx(uhs_phy_cal_res->rdq);
+    set_uhs_latency_w(uhs_phy_cal_res->wl);
+    cfg_dq_drv(uhs_phy_cal_res->wdq);
+    cfg_ck_cen_drv(uhs_phy_cal_res->wdq + 4, uhs_phy_cal_res->wdq + 1);
+    cfg_dqs_drv(uhs_phy_cal_res->wdqs);
+    // set_odt_en();
+    mr_read_back();
+    return 0;
+}
+#endif
+
+/* This is the timer interrupt service routine. */
+static void systick_isr(void)
+{
+    rt_tick_increase();
+}
+
+void rt_hw_board_init(void)
+{
+    GLB_Halt_CPU(GLB_CORE_ID_D0);
+    GLB_Halt_CPU(GLB_CORE_ID_LP);
+
+    bflb_flash_init();
+
+    system_clock_init();
+    peripheral_clock_init();
+    bflb_irq_initialize();
+
+    bflb_mtimer_config(CPU_Get_MTimer_Clock() / RT_TICK_PER_SECOND, systick_isr);
+
+#ifdef RT_USING_HEAP
+    /* initialize memory system */
+    rt_kprintf("RT_HW_HEAP_BEGIN:%x RT_HW_HEAP_END:%x size: %d\r\n", RT_HW_HEAP_BEGIN, RT_HW_HEAP_END, RT_HW_HEAP_END - RT_HW_HEAP_BEGIN);
+    rt_system_heap_init(RT_HW_HEAP_BEGIN, RT_HW_HEAP_END);
+#endif
+
+    /* UART driver initialization is open by default */
+#ifdef RT_USING_SERIAL
+    rt_hw_uart_init();
+#endif
+
+#ifdef BSP_USING_PSRAM
+    if (uhs_psram_init() < 0)
+    {
+        rt_kprintf("uhs_psram_init failed!\n");
+    }
+#endif
+
+    /* GPIO driver initialization is open by default */
+#ifdef BSP_USING_PIN
+    rt_hw_pin_init();
+#endif
+
+    /* I2C driver initialization is open by default */
+#ifdef BSP_USING_I2C
+    rt_hw_i2c_init();
+#endif
+
+    /* Set the shell console output device */
+#if defined(RT_USING_CONSOLE) && defined(RT_USING_DEVICE)
+    rt_console_set_device(RT_CONSOLE_DEVICE_NAME);
+#endif
+
+#ifdef RT_USING_COMPONENTS_INIT
+    rt_components_board_init();
+#endif
+
+    /* set CPU D0 boot XIP address and flash address */
+    Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_D0, 1);
+    /* D0 boot from 0x58000000 */
+    GLB_Set_CPU_Reset_Address(GLB_CORE_ID_D0, 0x58000000);
+    /* D0 image offset on flash is CONFIG_D0_FLASH_ADDR+0x1000(header) */
+    bflb_sf_ctrl_set_flash_image_offset(CONFIG_D0_FLASH_ADDR + 0x1000, 1, SF_CTRL_FLASH_BANK0);
+
+    Tzc_Sec_Set_CPU_Group(GLB_CORE_ID_LP, 0);
+    /* LP boot from 0x580C0000 */
+    GLB_Set_CPU_Reset_Address(GLB_CORE_ID_LP, 0x580C0000);
+
+    GLB_Release_CPU(GLB_CORE_ID_D0);
+    GLB_Release_CPU(GLB_CORE_ID_LP);
+
+    /* release d0 and then do can run */
+    BL_WR_WORD(IPC_SYNC_ADDR1, IPC_SYNC_FLAG);
+    BL_WR_WORD(IPC_SYNC_ADDR2, IPC_SYNC_FLAG);
+    L1C_DCache_Clean_By_Addr(IPC_SYNC_ADDR1, 8);
+}
+
+void rt_hw_cpu_reset(void)
+{
+    GLB_SW_POR_Reset();
+}
+MSH_CMD_EXPORT_ALIAS(rt_hw_cpu_reset, reboot, reset machine);
diff --git a/bsp/bouffalo_lab/bl808/m0/board/board.h b/bsp/bouffalo_lab/bl808/m0/board/board.h
new file mode 100644
index 0000000000..87b65931e7
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/board.h
@@ -0,0 +1,38 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2022/12/25     flyingcys    first version
+ * 2023/03/15     flyingcys    update bsp file structure
+ */
+
+#ifndef BOARD_H__
+#define BOARD_H__
+
+#include 
+
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
+#include "bflb_clock.h"
+#include "bflb_rtc.h"
+#include "bflb_flash.h"
+#include "bl808_glb.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_tzc_sec.h"
+#include "bl808_ef_cfg.h"
+#include "bl808_uhs_phy.h"
+
+#define CONFIG_D0_FLASH_ADDR             0x100000
+
+extern uint8_t __HeapBase;
+extern uint8_t __HeapLimit;
+
+#define RT_HW_HEAP_BEGIN    (void*)&__HeapBase
+#define RT_HW_HEAP_END      (void*)&__HeapLimit
+
+void rt_hw_board_init(void);
+
+#endif
diff --git a/bsp/bouffalo_lab/bl808/m0/board/fw_header.c b/bsp/bouffalo_lab/bl808/m0/board/fw_header.c
new file mode 100644
index 0000000000..73f7948497
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/fw_header.c
@@ -0,0 +1,208 @@
+#include "fw_header.h"
+
+__attribute__((section(".fw_header"))) struct bootheader_t fw_header = {
+    .magiccode = 0x504e4642,
+    .rivison = 0x00000001,
+    /*flash config */
+    .flash_cfg.magiccode = 0x47464346,
+    .flash_cfg.cfg.ioMode = 0x11,               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    .flash_cfg.cfg.cReadSupport = 0x00,         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    .flash_cfg.cfg.clkDelay = 0x01,             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    .flash_cfg.cfg.clkInvert = 0x01,            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    .flash_cfg.cfg.resetEnCmd = 0x66,           /*!< Flash enable reset command */
+    .flash_cfg.cfg.resetCmd = 0x99,             /*!< Flash reset command */
+    .flash_cfg.cfg.resetCreadCmd = 0xff,        /*!< Flash reset continuous read command */
+    .flash_cfg.cfg.resetCreadCmdSize = 0x03,    /*!< Flash reset continuous read command size */
+    .flash_cfg.cfg.jedecIdCmd = 0x9f,           /*!< JEDEC ID command */
+    .flash_cfg.cfg.jedecIdCmdDmyClk = 0x00,     /*!< JEDEC ID command dummy clock */
+    .flash_cfg.cfg.enter32BitsAddrCmd = 0xb7,   /*!< Enter 32-bits addr command */
+    .flash_cfg.cfg.exit32BitsAddrCmd = 0xe9,    /*!< Exit 32-bits addr command */
+    .flash_cfg.cfg.sectorSize = 0x04,           /*!< *1024bytes */
+    .flash_cfg.cfg.mid = 0x00,                  /*!< Manufacturer ID */
+    .flash_cfg.cfg.pageSize = 0x100,            /*!< Page size */
+    .flash_cfg.cfg.chipEraseCmd = 0xc7,         /*!< Chip erase cmd */
+    .flash_cfg.cfg.sectorEraseCmd = 0x20,       /*!< Sector erase command */
+    .flash_cfg.cfg.blk32EraseCmd = 0x52,        /*!< Block 32K erase command,some Micron not support */
+    .flash_cfg.cfg.blk64EraseCmd = 0xd8,        /*!< Block 64K erase command */
+    .flash_cfg.cfg.writeEnableCmd = 0x06,       /*!< Need before every erase or program */
+    .flash_cfg.cfg.pageProgramCmd = 0x02,       /*!< Page program cmd */
+    .flash_cfg.cfg.qpageProgramCmd = 0x32,      /*!< QIO page program cmd */
+    .flash_cfg.cfg.qppAddrMode = 0x00,          /*!< QIO page program address mode */
+    .flash_cfg.cfg.fastReadCmd = 0x0b,          /*!< Fast read command */
+    .flash_cfg.cfg.frDmyClk = 0x01,             /*!< Fast read command dummy clock */
+    .flash_cfg.cfg.qpiFastReadCmd = 0x0b,       /*!< QPI fast read command */
+    .flash_cfg.cfg.qpiFrDmyClk = 0x01,          /*!< QPI fast read command dummy clock */
+    .flash_cfg.cfg.fastReadDoCmd = 0x3b,        /*!< Fast read dual output command */
+    .flash_cfg.cfg.frDoDmyClk = 0x01,           /*!< Fast read dual output command dummy clock */
+    .flash_cfg.cfg.fastReadDioCmd = 0xbb,       /*!< Fast read dual io comamnd */
+    .flash_cfg.cfg.frDioDmyClk = 0x00,          /*!< Fast read dual io command dummy clock */
+    .flash_cfg.cfg.fastReadQoCmd = 0x6b,        /*!< Fast read quad output comamnd */
+    .flash_cfg.cfg.frQoDmyClk = 0x01,           /*!< Fast read quad output comamnd dummy clock */
+    .flash_cfg.cfg.fastReadQioCmd = 0xeb,       /*!< Fast read quad io comamnd */
+    .flash_cfg.cfg.frQioDmyClk = 0x02,          /*!< Fast read quad io comamnd dummy clock */
+    .flash_cfg.cfg.qpiFastReadQioCmd = 0xeb,    /*!< QPI fast read quad io comamnd */
+    .flash_cfg.cfg.qpiFrQioDmyClk = 0x02,       /*!< QPI fast read QIO dummy clock */
+    .flash_cfg.cfg.qpiPageProgramCmd = 0x02,    /*!< QPI program command */
+    .flash_cfg.cfg.writeVregEnableCmd = 0x50,   /*!< Enable write reg */
+    .flash_cfg.cfg.wrEnableIndex = 0x00,        /*!< Write enable register index */
+    .flash_cfg.cfg.qeIndex = 0x01,              /*!< Quad mode enable register index */
+    .flash_cfg.cfg.busyIndex = 0x00,            /*!< Busy status register index */
+    .flash_cfg.cfg.wrEnableBit = 0x01,          /*!< Write enable bit pos */
+    .flash_cfg.cfg.qeBit = 0x01,                /*!< Quad enable bit pos */
+    .flash_cfg.cfg.busyBit = 0x00,              /*!< Busy status bit pos */
+    .flash_cfg.cfg.wrEnableWriteRegLen = 0x02,  /*!< Register length of write enable */
+    .flash_cfg.cfg.wrEnableReadRegLen = 0x01,   /*!< Register length of write enable status */
+    .flash_cfg.cfg.qeWriteRegLen = 0x02,        /*!< Register length of contain quad enable */
+    .flash_cfg.cfg.qeReadRegLen = 0x01,         /*!< Register length of contain quad enable status */
+    .flash_cfg.cfg.releasePowerDown = 0xab,     /*!< Release power down command */
+    .flash_cfg.cfg.busyReadRegLen = 0x01,       /*!< Register length of contain busy status */
+    .flash_cfg.cfg.readRegCmd[0] = 0x05,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[1] = 0x35,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[2] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.readRegCmd[3] = 0x00,        /*!< Read register command buffer */
+    .flash_cfg.cfg.writeRegCmd[0] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[1] = 0x01,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[2] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.writeRegCmd[3] = 0x00,       /*!< Write register command buffer */
+    .flash_cfg.cfg.enterQpi = 0x38,             /*!< Enter qpi command */
+    .flash_cfg.cfg.exitQpi = 0xff,              /*!< Exit qpi command */
+    .flash_cfg.cfg.cReadMode = 0x20,            /*!< Config data for continuous read mode */
+    .flash_cfg.cfg.cRExit = 0xf0,               /*!< Config data for exit continuous read mode */
+    .flash_cfg.cfg.burstWrapCmd = 0x77,         /*!< Enable burst wrap command */
+    .flash_cfg.cfg.burstWrapCmdDmyClk = 0x03,   /*!< Enable burst wrap command dummy clock */
+    .flash_cfg.cfg.burstWrapDataMode = 0x02,    /*!< Data and address mode for this command */
+    .flash_cfg.cfg.burstWrapData = 0x40,        /*!< Data to enable burst wrap */
+    .flash_cfg.cfg.deBurstWrapCmd = 0x77,       /*!< Disable burst wrap command */
+    .flash_cfg.cfg.deBurstWrapCmdDmyClk = 0x03, /*!< Disable burst wrap command dummy clock */
+    .flash_cfg.cfg.deBurstWrapDataMode = 0x02,  /*!< Data and address mode for this command */
+    .flash_cfg.cfg.deBurstWrapData = 0xf0,      /*!< Data to disable burst wrap */
+    .flash_cfg.cfg.timeEsector = 300,           /*!< 4K erase time */
+    .flash_cfg.cfg.timeE32k = 1200,             /*!< 32K erase time */
+    .flash_cfg.cfg.timeE64k = 1200,             /*!< 64K erase time */
+    .flash_cfg.cfg.timePagePgm = 50,            /*!< Page program time */
+    .flash_cfg.cfg.timeCe = 30000,              /*!< Chip erase time in ms */
+    .flash_cfg.cfg.pdDelay = 20,                /*!< Release power down command delay time for wake up */
+    .flash_cfg.cfg.qeData = 0,                  /*!< QE set data */
+    .flash_cfg.crc32 = 0xdeadbeef,
+    /* clock cfg */
+    .clk_cfg.magiccode = 0x47464350,
+    .clk_cfg.cfg.xtal_type = 0x07, /*!<  0:None,1:24M,2:32M,3:38.4M,4:40M,5:26M,6:RC32M  */
+    .clk_cfg.cfg.mcu_clk = 0x04,   /*!< mcu_clk 0:RC32M,1:Xtal,2:cpupll 400M,3:wifipll 192M,4:wifipll 320M */
+    .clk_cfg.cfg.mcu_clk_div = 0x00,
+    .clk_cfg.cfg.mcu_bclk_div = 0x00,
+
+    .clk_cfg.cfg.mcu_pbclk_div = 0x03,
+    .clk_cfg.cfg.lp_div = 0x01,
+    .clk_cfg.cfg.dsp_clk = 0x03, /* 0:RC32M,1:Xtal,2:wifipll 240M,3:wifipll 320M,4:cpupll 400M */
+    .clk_cfg.cfg.dsp_clk_div = 0x00,
+
+    .clk_cfg.cfg.dsp_bclk_div = 0x01,
+    .clk_cfg.cfg.dsp_pbclk = 0x02, /* 0:RC32M,1:Xtal,2:wifipll 160M,3:cpupll 160M,4:wifipll 240M */
+    .clk_cfg.cfg.dsp_pbclk_div = 0x00,
+    .clk_cfg.cfg.emi_clk = 0x02, /*!<  0:mcu pbclk,1:cpupll 200M,2:wifipll 320M,3:cpupll 400M */
+
+    .clk_cfg.cfg.emi_clk_div = 0x01,
+    .clk_cfg.cfg.flash_clk_type = 0x01, /*!< 0:wifipll 120M,1:xtal,2:cpupll 100M,3:wifipll 80M,4:bclk,5:wifipll 96M */
+    .clk_cfg.cfg.flash_clk_div = 0x00,
+    .clk_cfg.cfg.wifipll_pu = 0x01,
+
+    .clk_cfg.cfg.aupll_pu = 0x01,
+    .clk_cfg.cfg.cpupll_pu = 0x01,
+    .clk_cfg.cfg.mipipll_pu = 0x01,
+    .clk_cfg.cfg.uhspll_pu = 0x01,
+
+    .clk_cfg.crc32 = 0xdeadbeef,
+
+    /* basic cfg */
+    .basic_cfg.sign_type = 0x0,          /* [1: 0]   for sign */
+    .basic_cfg.encrypt_type = 0x0,       /* [3: 2]   for encrypt */
+    .basic_cfg.key_sel = 0x0,            /* [5: 4]   key slot */
+    .basic_cfg.xts_mode = 0x0,           /* [6]      for xts mode */
+    .basic_cfg.aes_region_lock = 0x0,    /* [7]      rsvd */
+    .basic_cfg.no_segment = 0x1,         /* [8]      no segment info */
+    .basic_cfg.rsvd_0 = 0x0,             /* [9]      boot2 enable(rsvd_0) */
+    .basic_cfg.rsvd_1 = 0x0,             /* [10]     boot2 rollback(rsvd_1) */
+    .basic_cfg.cpu_master_id = 0x0,      /* [14: 11] master id */
+    .basic_cfg.notload_in_bootrom = 0x0, /* [15]     notload in bootrom */
+    .basic_cfg.crc_ignore = 0x1,         /* [16]     ignore crc */
+    .basic_cfg.hash_ignore = 0x1,        /* [17]     hash ignore */
+    .basic_cfg.power_on_mm = 0x1,        /* [18]     power on mm */
+    .basic_cfg.em_sel = 0x1,             /* [21: 19] em_sel */
+    .basic_cfg.cmds_en = 0x1,            /* [22]     command spliter enable */
+#if 0
+# 0 : cmds bypass wrap commands to macro, original mode;
+# 1 : cmds handle wrap commands, original mode;
+# 2 : cmds bypass wrap commands to macro, cmds force wrap16 * 4 splitted into two wrap8 * 4;
+# 3 : cmds handle wrap commands, cmds force wrap16 * 4 splitted into two wrap8 * 4
+#endif
+    .basic_cfg.cmds_wrap_mode = 0x1, /* [24: 23] cmds wrap mode */
+#if 0
+# 0 : SF_CTRL_WRAP_LEN_8, 1 : SF_CTRL_WRAP_LEN_16, 2 : SF_CTRL_WRAP_LEN_32,
+# 3 : SF_CTRL_WRAP_LEN_64, 9 : SF_CTRL_WRAP_LEN_4096
+#endif
+    .basic_cfg.cmds_wrap_len = 0x9,  /* [28: 25] cmds wrap len */
+    .basic_cfg.icache_invalid = 0x1, /* [29] icache invalid */
+    .basic_cfg.dcache_invalid = 0x1, /* [30] dcache invalid */
+    .basic_cfg.rsvd_3 = 0x0,         /* [31] rsvd_3 */
+
+#ifdef BFLB_BOOT2
+    .basic_cfg.group_image_offset = 0x00002000, /* flash controller offset */
+#else
+    .basic_cfg.group_image_offset = 0x00001000, /* flash controller offset */
+#endif
+    .basic_cfg.aes_region_len = 0x00000000,     /* aes region length */
+
+    .basic_cfg.img_len_cnt = 0x00010000, /* image length or segment count */
+    .basic_cfg.hash = { 0xdeadbeef },    /* hash of the image */
+
+    /* cpu cfg */
+    .cpu_cfg[0].config_enable = 0x01, /* coinfig this cpu */
+    .cpu_cfg[0].halt_cpu = 0x0,       /* halt this cpu */
+    .cpu_cfg[0].cache_enable = 0x0,   /* cache setting :only for BL Cache */
+    .cpu_cfg[0].cache_wa = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wb = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_wt = 0x0,       /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].cache_way_dis = 0x0,  /* cache setting :only for BL Cache*/
+    .cpu_cfg[0].rsvd = 0x0,
+
+    .cpu_cfg[0].cache_range_h = 0x00000000,
+    .cpu_cfg[0].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[0].image_address_offset = 0x0,
+    .cpu_cfg[0].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[0].msp_val = 0x00000000, /* msp value */
+
+    /* cpu cfg */
+    .cpu_cfg[1].config_enable = 0x0, /* coinfig this cpu */
+    .cpu_cfg[1].halt_cpu = 0x0,      /* halt this cpu */
+    .cpu_cfg[1].cache_enable = 0x0,  /* cache setting :only for BL Cache */
+    .cpu_cfg[1].cache_wa = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wb = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_wt = 0x0,      /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].cache_way_dis = 0x0, /* cache setting :only for BL Cache*/
+    .cpu_cfg[1].rsvd = 0x0,
+
+    .cpu_cfg[1].cache_range_h = 0x00000000,
+    .cpu_cfg[1].cache_range_l = 0x00000000,
+    /* image_address_offset */
+    .cpu_cfg[1].image_address_offset = 0x0,
+    .cpu_cfg[1].rsvd0 = 0x58000000,   /* rsvd0 */
+    .cpu_cfg[1].msp_val = 0x00000000, /* msp value */
+
+    /* address of partition table 0 */ /* 4 */
+    .boot2_pt_table_0_rsvd = 0x00000000,
+    /* address of partition table 1 */ /* 4 */
+    .boot2_pt_table_1_rsvd = 0x00000000,
+
+    /* address of flashcfg table list */ /* 4 */
+    .flash_cfg_table_addr = 0x00000000,
+    /* flashcfg table list len */ /* 4 */
+    .flash_cfg_table_len = 0x00000000,
+
+    .rsvd1[0] = 0x20000320,
+    .rsvd1[1] = 0x00000000,
+    .rsvd1[2] = 0x2000F038,
+    .rsvd1[3] = 0x18000000,
+
+    .crc32 = 0xdeadbeef /* 4 */
+};
diff --git a/bsp/bouffalo_lab/bl808/m0/board/fw_header.h b/bsp/bouffalo_lab/bl808/m0/board/fw_header.h
new file mode 100644
index 0000000000..85fc1db38f
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/fw_header.h
@@ -0,0 +1,213 @@
+#ifndef __FW_HEADER_H__
+#define __FW_HEADER_H__
+
+#include "stdint.h"
+#include "stdio.h"
+
+struct __attribute__((packed, aligned(4))) spi_flash_cfg_t {
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
+    uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t resetEnCmd;           /*!< Flash enable reset command */
+    uint8_t resetCmd;             /*!< Flash reset command */
+    uint8_t resetCreadCmd;        /*!< Flash reset continuous read command */
+    uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
+    uint8_t jedecIdCmd;           /*!< JEDEC ID command */
+    uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
+    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
+    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t sectorSize;           /*!< *1024bytes */
+    uint8_t mid;                  /*!< Manufacturer ID */
+    uint16_t pageSize;            /*!< Page size */
+    uint8_t chipEraseCmd;         /*!< Chip erase cmd */
+    uint8_t sectorEraseCmd;       /*!< Sector erase command */
+    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
+    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t pageProgramCmd;       /*!< Page program cmd */
+    uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
+    uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t fastReadCmd;          /*!< Fast read command */
+    uint8_t frDmyClk;             /*!< Fast read command dummy clock */
+    uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
+    uint8_t qpiFrDmyClk;          /*!< QPI fast read command dummy clock */
+    uint8_t fastReadDoCmd;        /*!< Fast read dual output command */
+    uint8_t frDoDmyClk;           /*!< Fast read dual output command dummy clock */
+    uint8_t fastReadDioCmd;       /*!< Fast read dual io comamnd */
+    uint8_t frDioDmyClk;          /*!< Fast read dual io command dummy clock */
+    uint8_t fastReadQoCmd;        /*!< Fast read quad output comamnd */
+    uint8_t frQoDmyClk;           /*!< Fast read quad output comamnd dummy clock */
+    uint8_t fastReadQioCmd;       /*!< Fast read quad io comamnd */
+    uint8_t frQioDmyClk;          /*!< Fast read quad io comamnd dummy clock */
+    uint8_t qpiFastReadQioCmd;    /*!< QPI fast read quad io comamnd */
+    uint8_t qpiFrQioDmyClk;       /*!< QPI fast read QIO dummy clock */
+    uint8_t qpiPageProgramCmd;    /*!< QPI program command */
+    uint8_t writeVregEnableCmd;   /*!< Enable write reg */
+    uint8_t wrEnableIndex;        /*!< Write enable register index */
+    uint8_t qeIndex;              /*!< Quad mode enable register index */
+    uint8_t busyIndex;            /*!< Busy status register index */
+    uint8_t wrEnableBit;          /*!< Write enable bit pos */
+    uint8_t qeBit;                /*!< Quad enable bit pos */
+    uint8_t busyBit;              /*!< Busy status bit pos */
+    uint8_t wrEnableWriteRegLen;  /*!< Register length of write enable */
+    uint8_t wrEnableReadRegLen;   /*!< Register length of write enable status */
+    uint8_t qeWriteRegLen;        /*!< Register length of contain quad enable */
+    uint8_t qeReadRegLen;         /*!< Register length of contain quad enable status */
+    uint8_t releasePowerDown;     /*!< Release power down command */
+    uint8_t busyReadRegLen;       /*!< Register length of contain busy status */
+    uint8_t readRegCmd[4];        /*!< Read register command buffer */
+    uint8_t writeRegCmd[4];       /*!< Write register command buffer */
+    uint8_t enterQpi;             /*!< Enter qpi command */
+    uint8_t exitQpi;              /*!< Exit qpi command */
+    uint8_t cReadMode;            /*!< Config data for continuous read mode */
+    uint8_t cRExit;               /*!< Config data for exit continuous read mode */
+    uint8_t burstWrapCmd;         /*!< Enable burst wrap command */
+    uint8_t burstWrapCmdDmyClk;   /*!< Enable burst wrap command dummy clock */
+    uint8_t burstWrapDataMode;    /*!< Data and address mode for this command */
+    uint8_t burstWrapData;        /*!< Data to enable burst wrap */
+    uint8_t deBurstWrapCmd;       /*!< Disable burst wrap command */
+    uint8_t deBurstWrapCmdDmyClk; /*!< Disable burst wrap command dummy clock */
+    uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
+    uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
+    uint16_t timeEsector;         /*!< 4K erase time */
+    uint16_t timeE32k;            /*!< 32K erase time */
+    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timePagePgm;         /*!< Page program time */
+    uint16_t timeCe;              /*!< Chip erase time in ms */
+    uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
+    uint8_t qeData;               /*!< QE set data */
+};
+
+struct __attribute__((packed, aligned(4))) boot_flash_cfg_t {
+    uint32_t magiccode;
+    struct spi_flash_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sys_clk_cfg_t {
+    uint8_t xtal_type;
+    uint8_t mcu_clk;
+    uint8_t mcu_clk_div;
+    uint8_t mcu_bclk_div;
+
+    uint8_t mcu_pbclk_div;
+    uint8_t lp_div;
+    uint8_t dsp_clk;
+    uint8_t dsp_clk_div;
+
+    uint8_t dsp_bclk_div;
+    uint8_t dsp_pbclk;
+    uint8_t dsp_pbclk_div;
+    uint8_t emi_clk;
+
+    uint8_t emi_clk_div;
+    uint8_t flash_clk_type;
+    uint8_t flash_clk_div;
+    uint8_t wifipll_pu;
+
+    uint8_t aupll_pu;
+    uint8_t cpupll_pu;
+    uint8_t mipipll_pu;
+    uint8_t uhspll_pu;
+};
+
+struct __attribute__((packed, aligned(4))) boot_clk_cfg_t {
+    uint32_t magiccode;
+    struct sys_clk_cfg_t cfg;
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) boot_basic_cfg_t {
+    uint32_t sign_type          : 2; /* [1: 0]   for sign */
+    uint32_t encrypt_type       : 2; /* [3: 2]   for encrypt */
+    uint32_t key_sel            : 2; /* [5: 4]   key slot */
+    uint32_t xts_mode           : 1; /* [6]      for xts mode */
+    uint32_t aes_region_lock    : 1; /* [7]      rsvd */
+    uint32_t no_segment         : 1; /* [8]      no segment info */
+    uint32_t rsvd_0             : 1; /* [9]      boot2 enable(rsvd_0) */
+    uint32_t rsvd_1             : 1; /* [10]     boot2 rollback(rsvd_1) */
+    uint32_t cpu_master_id      : 4; /* [14: 11] master id */
+    uint32_t notload_in_bootrom : 1; /* [15]     notload in bootrom */
+    uint32_t crc_ignore         : 1; /* [16]     ignore crc */
+    uint32_t hash_ignore        : 1; /* [17]     hash ignore */
+    uint32_t power_on_mm        : 1; /* [18]     power on mm */
+    uint32_t em_sel             : 3; /* [21: 19] em_sel */
+    uint32_t cmds_en            : 1; /* [22]     command spliter enable */
+    uint32_t cmds_wrap_mode     : 2; /* [24: 23] cmds wrap mode */
+    uint32_t cmds_wrap_len      : 4; /* [28: 25] cmds wrap len */
+    uint32_t icache_invalid     : 1; /* [29] icache invalid */
+    uint32_t dcache_invalid     : 1; /* [30] dcache invalid */
+    uint32_t rsvd_3             : 1; /* [31] rsvd_3 */
+
+    uint32_t group_image_offset; /* flash controller offset */
+    uint32_t aes_region_len;     /* aes region length */
+
+    uint32_t img_len_cnt;  /* image length or segment count */
+    uint32_t hash[32 / 4]; /* hash of the image */
+};
+
+struct __attribute__((packed, aligned(4))) boot_cpu_cfg_t {
+    uint8_t config_enable;     /* coinfig this cpu */
+    uint8_t halt_cpu;          /* halt this cpu */
+    uint8_t cache_enable  : 1; /* cache setting */
+    uint8_t cache_wa      : 1; /* cache setting */
+    uint8_t cache_wb      : 1; /* cache setting */
+    uint8_t cache_wt      : 1; /* cache setting */
+    uint8_t cache_way_dis : 4; /* cache setting */
+    uint8_t rsvd;
+
+    uint32_t cache_range_h; /* cache range high */
+    uint32_t cache_range_l; /* cache range low */
+
+    uint32_t image_address_offset; /* image_address_offset */
+    uint32_t rsvd0;                /* rsvd0 */
+    uint32_t msp_val;              /* msp value */
+};
+
+struct __attribute__((packed, aligned(4))) aesiv_cfg_t {
+    uint8_t aesiv[16];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) pkey_cfg_t {
+    uint8_t eckeyx[32]; /* ec key in boot header */
+    uint8_t eckeyy[32]; /* ec key in boot header */
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) sign_cfg_t {
+    uint32_t sig_len;
+    uint8_t signature[32];
+    uint32_t crc32;
+};
+
+struct __attribute__((packed, aligned(4))) bootheader_t {
+    uint32_t magiccode; /* 4 */
+    uint32_t rivison;   /* 4 */
+
+    struct boot_flash_cfg_t flash_cfg; /* 4 + 84 + 4 */
+    struct boot_clk_cfg_t clk_cfg;     /* 4 + 20 + 4 */
+
+    struct boot_basic_cfg_t basic_cfg; /* 4 + 4 + 4 + 4 + 4*8 */
+
+    struct boot_cpu_cfg_t cpu_cfg[3]; /*24*3 */
+
+    uint32_t boot2_pt_table_0_rsvd; /* address of partition table 0 */ /* 4 */
+    uint32_t boot2_pt_table_1_rsvd; /* address of partition table 1 */ /* 4 */
+
+    uint32_t flash_cfg_table_addr; /* address of flashcfg table list */ /* 4 */
+    uint32_t flash_cfg_table_len; /* flashcfg table list len */         /* 4 */
+
+    uint32_t rsvd0[8]; /* rsvd */
+    uint32_t rsvd1[8]; /* rsvd */
+
+    uint32_t rsvd3[5]; /* 20 */
+
+    uint32_t crc32; /* 4 */
+};
+
+#define BFLB_FW_LENGTH_OFFSET 140
+#define BFLB_FW_HASH_OFFSET   144
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash.ld b/bsp/bouffalo_lab/bl808/m0/board/linker_scripts/bl808_flash_m0.ld
old mode 100644
new mode 100755
similarity index 79%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash.ld
rename to bsp/bouffalo_lab/bl808/m0/board/linker_scripts/bl808_flash_m0.ld
index 6090dd6f1a..2dc1f8fa37
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/bl808_flash.ld
+++ b/bsp/bouffalo_lab/bl808/m0/board/linker_scripts/bl808_flash_m0.ld
@@ -15,52 +15,69 @@ INPUT(-lc)
 /* link with the standard GCC library */
 INPUT(-lgcc)
 /* configure the entry point */
-ENTRY(Reset_Handler)
+ENTRY(__start)
 
 StackSize    = 0x0400; /*  1KB */
 HeapMinSize  = 0x1000; /*  4KB */
 
 MEMORY
 {
+    fw_header_memory  (rx)  : ORIGIN = 0x58000000 - 0x1000, LENGTH = 4K
     xip_memory  (rx)  : ORIGIN = 0x58000000, LENGTH = 32M
-    itcm_memory (rx)  : ORIGIN = 0x62028000, LENGTH = 28K
-    dtcm_memory (rx)  : ORIGIN = 0x6202F000, LENGTH = 4K
-    nocache_ram_memory (!rx) : ORIGIN = 0x22030000, LENGTH = 0K
-    ram_memory  (!rx) : ORIGIN = 0x62030000, LENGTH = 160K
+    itcm_memory (rx)  : ORIGIN = 0x62020000, LENGTH = 20K
+    dtcm_memory (rx)  : ORIGIN = 0x62025000, LENGTH = 4K
+    nocache_ram_memory (!rx) : ORIGIN = 0x22026000, LENGTH = 40K
+    ram_memory  (!rx) : ORIGIN = 0x62030000, LENGTH = 160K + 64K - 20K - 4K - 40K
     xram_memory  (!rx) : ORIGIN = 0x40000000, LENGTH = 16K
 }
 
 SECTIONS
 {
+    .fw_header :
+    {
+        KEEP(*(.fw_header))
+    } > fw_header_memory
 
     .text :
     {
         . = ALIGN(4);
         __text_code_start__ = .;
-        KEEP(*startup*.*o(*.text*))
-        KEEP (*(SORT_NONE(_start)))
-        KEEP (*(SORT_NONE(Reset_Handler)))
+
+        KEEP (*(SORT_NONE(.init)))
+        KEEP (*(SORT_NONE(.vector)))
 
         *(.text)
         *(.text.*)
 
-        /* section information for shell */
+        /* section information for finsh shell */
         . = ALIGN(4);
         __fsymtab_start = .;
         KEEP(*(FSymTab))
         __fsymtab_end = .;
-
         . = ALIGN(4);
         __vsymtab_start = .;
         KEEP(*(VSymTab))
         __vsymtab_end = .;
+        . = ALIGN(4);
 
-        /* section information for usb desc */
+        /* section information for modules */
         . = ALIGN(4);
-        _usb_desc_start = .;
-        KEEP(*(usb_desc))
+        __rtmsymtab_start = .;
+        KEEP(*(RTMSymTab))
+        __rtmsymtab_end = .;
+
+        /* section information for initialization */
         . = ALIGN(4);
-        _usb_desc_end = .;
+        __rt_init_start = .;
+        KEEP(*(SORT(.rti_fn*)))
+        __rt_init_end = .;
+
+        /* section information for usb usbh_class_info */
+        . = ALIGN(4);
+        __usbh_class_info_start__ = .;
+        KEEP(*(.usbh_class_info))
+        . = ALIGN(4);
+        __usbh_class_info_end__ = .;
 
         /*put .rodata**/
         *(EXCLUDE_FILE( *bl808_glb*.o* \
@@ -145,6 +162,7 @@ SECTIONS
      * size of stack_dummy section */
     __StackTop = ORIGIN(dtcm_memory) + LENGTH(dtcm_memory);
     PROVIDE( __freertos_irq_stack_top = __StackTop);
+    PROVIDE( __rt_rvstack = . );
     __StackLimit = __StackTop - SIZEOF(.stack_dummy);
 
     /* Check if data + heap + stack exceeds RAM limit */
@@ -152,7 +170,7 @@ SECTIONS
     /*************************************************************************/
     __nocache_ram_load_addr = __dtcm_load_addr + SIZEOF(.dtcm_region);
 
-    .nocache_ram_region (NOLOAD) : AT (__nocache_ram_load_addr)
+    .nocache_ram_region  : AT (__nocache_ram_load_addr)
     {
         . = ALIGN(4);
         __nocache_ram_data_start__ = .;
@@ -163,28 +181,7 @@ SECTIONS
         __nocache_ram_data_end__ = .;
     } > nocache_ram_memory
 
-    __system_ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
-
-    .system_ram_data_region : AT (__system_ram_load_addr)
-    {
-        . = ALIGN(4);
-        __system_ram_data_start__ = .;
-
-        *(.system_ram)
-
-        . = ALIGN(4);
-        __system_ram_data_end__ = .;
-    } > ram_memory
-
-    .system_ram_noinit_data_region (NOLOAD) :
-    {
-        . = ALIGN(4);
-        *(.system_ram_noinit)
-
-        . = ALIGN(4);
-    } > ram_memory
-
-    __ram_load_addr = __system_ram_load_addr + SIZEOF(.system_ram_data_region);
+    __ram_load_addr = __nocache_ram_load_addr + SIZEOF(.nocache_ram_region);
 
     /* Data section */
     RAM_DATA : AT (__ram_load_addr)
@@ -202,6 +199,10 @@ SECTIONS
         *(.sdata2.*)
 
         . = ALIGN(4);
+        __bflog_tags_start__ = .;
+        *(.bflog_tags_array)
+        . = ALIGN(4);
+        __bflog_tags_end__ = .;
         __ram_data_end__ = .;
     } > ram_memory
 
@@ -232,17 +233,18 @@ SECTIONS
         __noinit_data_end__ = .;
     } > ram_memory
 
-    .nocache_noinit_ram_region (NOLOAD) : 
+    .nocache_noinit_ram_region (NOLOAD) :
     {
         . = ALIGN(4);
-        __nocache_ram_data_start__ = .;
+        __nocache_noinit_ram_data_start__ = .;
 
         *(.nocache_noinit_ram)
+        *(.noncacheable)
 
         . = ALIGN(4);
-        __nocache_ram_data_end__ = .;
+        __nocache_noinit_ram_data_end__ = .;
     } > nocache_ram_memory
-    
+
     .heap (NOLOAD):
     {
         . = ALIGN(4);
diff --git a/bsp/bouffalo_lab/bl808/m0/board/trap_gcc.S b/bsp/bouffalo_lab/bl808/m0/board/trap_gcc.S
new file mode 100755
index 0000000000..a255ed7d09
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/board/trap_gcc.S
@@ -0,0 +1,17 @@
+#include "cpuport.h"
+
+	.globl rt_hw_do_after_save_above
+	.type rt_hw_do_after_save_above,@function
+rt_hw_do_after_save_above:
+    addi  sp, sp,  -4
+    STORE ra,  0 * REGBYTES(sp)
+
+	csrr    t1, mcause
+    andi    t1, t1, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+    
+    LOAD  ra,  0 * REGBYTES(sp)
+    addi  sp, sp,  4
+    ret
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl808/m0/combine.sh b/bsp/bouffalo_lab/bl808/m0/combine.sh
new file mode 100755
index 0000000000..ee1436b881
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/combine.sh
@@ -0,0 +1,39 @@
+#/bin/sh
+CHIPNAME=$1
+BIN_FILE=$2
+
+set -e
+
+SYSTEM=`uname -s`
+echo "system: $SYSTEM"
+
+CONFIG=../config
+TOOL_DIR=../../libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-macos
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_NAME=bflb_fw_post_proc-ubuntu
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc-ubuntu
+else
+    TOOL_NAME=bflb_fw_post_proc.exe
+    TOOL_ADDR=https://raw.githubusercontent.com/bouffalolab/bl_mcu_sdk/master/tools/bflb_tools/bflb_fw_post_proc/bflb_fw_post_proc.exe
+fi
+
+if [ -f "$TOOL_DIR/$TOOL_NAME" ]
+then
+    echo "bflb_fw_post_proc exist"
+else
+    echo "bflb_fw_post_proc not exist, try download... url:$TOOL_ADDR"
+    curl $TOOL_ADDR -o $TOOL_DIR/$TOOL_NAME
+    if [ $SYSTEM = "Darwin" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    elif [ $SYSTEM = "Linux" ]; then
+        chmod +x $TOOL_DIR/$TOOL_NAME
+    fi
+fi
+
+./$TOOL_DIR/$TOOL_NAME --chipname=$CHIPNAME --brdcfgdir=$CONFIG --imgfile=$BIN_FILE
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bl808/m0/flash_prog_cfg.ini b/bsp/bouffalo_lab/bl808/m0/flash_prog_cfg.ini
new file mode 100755
index 0000000000..090dc7a363
--- /dev/null
+++ b/bsp/bouffalo_lab/bl808/m0/flash_prog_cfg.ini
@@ -0,0 +1,12 @@
+[cfg]
+# 0: no erase, 1:programmed section erase, 2: chip erase
+erase = 1
+# skip mode set first para is skip addr, second para is skip len, multi-segment region with ; separated
+skip_mode = 0x0, 0x0
+# 0: not use isp mode, #1: isp mode
+boot2_isp_mode = 0
+
+[FW]
+filedir = ./rtthread_m0.bin
+# since D0 is boot by M0，this address should consistent with m0's board_init in board.c
+address = 0x000000
\ No newline at end of file
diff --git a/bsp/bl808/m0/rtconfig.h b/bsp/bouffalo_lab/bl808/m0/rtconfig.h
similarity index 92%
rename from bsp/bl808/m0/rtconfig.h
rename to bsp/bouffalo_lab/bl808/m0/rtconfig.h
index c8d155b675..7d7e932214 100644
--- a/bsp/bl808/m0/rtconfig.h
+++ b/bsp/bouffalo_lab/bl808/m0/rtconfig.h
@@ -19,7 +19,7 @@
 #define IDLE_THREAD_STACK_SIZE 1024
 #define RT_USING_TIMER_SOFT
 #define RT_TIMER_THREAD_PRIO 4
-#define RT_TIMER_THREAD_STACK_SIZE 1024
+#define RT_TIMER_THREAD_STACK_SIZE 512
 
 /* kservice optimization */
 
@@ -36,9 +36,10 @@
 
 /* Memory Management */
 
+#define RT_PAGE_MAX_ORDER 11
+#define RT_USING_MEMPOOL
 #define RT_USING_SMALL_MEM
 #define RT_USING_SMALL_MEM_AS_HEAP
-#define RT_USING_MEMTRACE
 #define RT_USING_HEAP
 
 /* Kernel Device Object */
@@ -48,8 +49,10 @@
 #define RT_CONSOLEBUF_SIZE 128
 #define RT_CONSOLE_DEVICE_NAME "uart0"
 #define RT_VER_NUM 0x50000
+#define ARCH_RISCV
 #define ARCH_RISCV_FPU
 #define ARCH_RISCV_FPU_S
+#define ARCH_RISCV32
 
 /* RT-Thread Components */
 
@@ -216,21 +219,22 @@
 
 /* Other */
 
+
 /* Signal IO */
 
 
 /* Uncategorized */
 
-/* BL808_M0 Hardware Drivers Config */
+#define BSP_USING_BL808
+#define BL808_CORE_M0
 
-#define SOC_BL808
+/* General Drivers Configuration */
 
-/* On-chip Peripheral Drivers */
 
-#define BSP_USING_GPIO
-#define BSP_USING_UART
+/* General Purpose UARTs */
+
 #define BSP_USING_UART0
-#define BSP_UART0_TXD_PIN 14
-#define BSP_UART0_RXD_PIN 15
+#define UART0_TX_USING_GPIO14
+#define UART0_RX_USING_GPIO15
 
 #endif
diff --git a/bsp/bl808/m0/rtconfig.py b/bsp/bouffalo_lab/bl808/m0/rtconfig.py
old mode 100644
new mode 100755
similarity index 55%
rename from bsp/bl808/m0/rtconfig.py
rename to bsp/bouffalo_lab/bl808/m0/rtconfig.py
index a9c7ad4d54..f8d18aa968
--- a/bsp/bl808/m0/rtconfig.py
+++ b/bsp/bouffalo_lab/bl808/m0/rtconfig.py
@@ -2,14 +2,13 @@ import os
 
 # toolchains options
 ARCH        ='risc-v'
-VENDOR      ='t-head'
 CPU         ='e9xx'
 CROSS_TOOL  ='gcc'
 
 if os.getenv('RTT_ROOT'):
     RTT_ROOT = os.getenv('RTT_ROOT')
 else:
-    RTT_ROOT = r'../../..'
+    RTT_ROOT = r'../../../..'
 
 if os.getenv('RTT_CC'):
     CROSS_TOOL = os.getenv('RTT_CC')
@@ -39,23 +38,20 @@ if PLATFORM == 'gcc':
     OBJDUMP = PREFIX + 'objdump'
     OBJCPY  = PREFIX + 'objcopy'
 
-    DEVICE  = ' -march=rv32imafcxthead -mabi=ilp32f -mtune=e907 -mcmodel=medany'
-    CFLAGS  = DEVICE + ' -Wall -Wno-error=unused-function -Wno-error=unused-but-set-variable -Wno-error=unused-variable -Wno-error=deprecated-declarations -Wextra -Wno-unused-parameter -Wno-sign-compare'
-    CFLAGS += ' -Wno-old-style-declaration -ffunction-sections -fdata-sections -fstrict-volatile-bitfields -fshort-enums -fcommon -ffreestanding -fno-strict-aliasing -fno-jump-tables -save-temps=obj'
+    DEVICE  = ' -march=rv32imafcpzpsfoperand_xtheade -mabi=ilp32f -mtune=e907'
+    CFLAGS  = DEVICE + ' -std=gnu99 -fno-jump-tables -fno-common -fms-extensions -ffunction-sections -fdata-sections -fmessage-length=0 -Wall -Wchar-subscripts -Wformat -Wundef -Wuninitialized -Winit-self -Wignored-qualifiers'
+    CFLAGS += ' -fstrict-volatile-bitfields -fshort-enums -Wno-error=unused-variable -Wno-error=format= -Wno-error=unused-function -Wno-error=implicit-function-declaration -Wno-error=deprecated-declarations -Wno-format'
 
-    LINKER_SCRIPTS_PATH = r'libraries/platform/soc/bl808/startup_bl808/evb/ld/'
-    LINKER_SCRIPTS = 'bl808_flash.ld'
-
-    CFLAGS += ' -DCFG_COMPONENT_BLOG_ENABLE=0 -DARCH_RISCV -DBFLB_USE_HAL_DRIVER -DCPU_M0 -DBL808'
+    LINKER_SCRIPTS = r'board/linker_scripts/bl808_flash_m0.ld'
 
     AFLAGS  = ' -c' + DEVICE + ' -x assembler-with-cpp'
-    LFLAGS  = DEVICE + ' -nostartfiles -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS_PATH + LINKER_SCRIPTS
+    LFLAGS  = DEVICE + ' -nostartfiles -ufw_header -fms-extensions -ffunction-sections -fdata-sections -Wl,--gc-sections,-Map=rtthread.map,-cref,-u,_start -T ' + LINKER_SCRIPTS
     CPATH   = ''
     LPATH   = ''
 
     if BUILD == 'debug':
-        CFLAGS += ' -O0 -gdwarf'
-        AFLAGS += ' -gdwarf'
+        CFLAGS += ' -O2 -g3'
+        AFLAGS += ' -g3'
     else:
         CFLAGS += ' -O3'
 
@@ -63,3 +59,4 @@ if PLATFORM == 'gcc':
 
 DUMP_ACTION = OBJDUMP + ' -D -S $TARGET > rtt.asm\n'
 POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread_m0.bin\n' + SIZE + ' $TARGET \n'
+POST_ACTION += 'sh combine.sh bl808 ./rtthread_m0.bin\n'
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/bouffalo_flash_cube.sh b/bsp/bouffalo_lab/bouffalo_flash_cube.sh
new file mode 100755
index 0000000000..07c7974681
--- /dev/null
+++ b/bsp/bouffalo_lab/bouffalo_flash_cube.sh
@@ -0,0 +1,42 @@
+#/bin/sh
+CHIPNAME=$1
+PORT=$2
+
+set -e
+
+SYSTEM=`uname -s`
+TOOL_SUFFIX=-ubuntu
+echo "system: $SYSTEM"
+
+if [ $SYSTEM = "Darwin" ]
+then
+    TOOL_SUFFIX=-macos
+elif [ $SYSTEM = "Linux" ]
+then
+    TOOL_SUFFIX=-ubuntu
+else
+    TOOL_SUFFIX=.exe
+fi
+
+CONFIG_DIR=./bl60x
+if [ $CHIPNAME = 'bl602' ]
+then
+    CONFIG_DIR=./bl60x
+elif [ $CHIPNAME = 'bl616' ]
+then
+    CONFIG_DIR=./bl61x
+elif [ $CHIPNAME = 'bl702' ]
+then
+    CONFIG_DIR=./bl70x
+elif [ $CHIPNAME = 'bl808' ]
+then
+    CONFIG_DIR=./bl808
+else
+    echo "chip name error"
+fi
+
+TOOL_DIR=./libraries/bl_mcu_sdk/tools/bflb_tools/bouffalo_flash_cube
+TOOL_NAME='BLFlashCommand'$TOOL_SUFFIX
+CONFIG_FILE=$CONFIG_DIR'/flash_prog_cfg.ini'
+
+./$TOOL_DIR/$TOOL_NAME --interface=uart --baudrate=2000000 --chipname=$CHIPNAME --config=$CONFIG_FILE --port=$PORT
diff --git a/bsp/bouffalo_lab/figures/bouffalo_flash_cube.jpg b/bsp/bouffalo_lab/figures/bouffalo_flash_cube.jpg
new file mode 100755
index 0000000000000000000000000000000000000000..ddaeaa5e75dedf5f8eaeaf35b133bceaa8a7af4e
GIT binary patch
literal 75105
zcmeFa2Ut{Dmo{2t5fn)ZB9sCO5+!F!K(c@!IZMttig*+h6v+q(3P_TSnwa7YF%c0lH5oYx1?@#B9qq+Smo77MFkPl+W4LsQ
zS>QU`4K7|@UMQ20m>{<(2M;gzw})U65)u*<5mTKxL&bgN(iQIi@*m7c2k-
z+ZVhK!6n5byTT=bPp*28fZmyc`*B3_DF(^HI!d+f4MrXl7eB(&=PyuEU%YyaiTOGU
zFCV{vppdZCEom89IeCS<>Kd9_+B&+XX66=_R@OGIZtfnQUf%cppF9l+eD*vjGU{b?
zOzf+;_>|PN^miGVS=mL!C8cHM6_r)>4UJ9BEv;>zdV2f%2L^|}A||J%XJ+T-7Z#T`
zx3+h7_x2ACkG|1`1;P1F)*qDpLKi7W7d9>~4lcnry0EZ4!50oGF5VR`d@>1Df_u*7
z^xTh6QAkE47uFFn@ThH2nz(eIKF`QId3Ey}X}?kS?-Azr-=gdf!hX<&fDq$gfy~1p
zg}@-Y!tZ(v$8D6-7i~{f$PMVMG2ymg7hZ9B>o>D%$IOty==?gG)9=c*+i;#i;ODH7
zl2%|b2pKUwlpTnHJdR(>6QEjfQuTXT$_msAOaVt!ykSW4b_}GA_m}s4Lt3!2#kq#I
zh^GmOu_goj7o3NcocWH^0=Z;axtp&TJ6(lfPcwSt8`+A_8x;kb!qB8}at!24T^cZv
zXoQwe{pEe$sRw%Id!)|pmlhceM)lIpf01`*ICahH#Y%{x{h@kP@O5|Gnc$)7P2~{F
z8EQ^}7G6ccm{W;XJ=czlS{F{YP}f}i&OV9x*=87$;UN=EIE~TN|5Ri9*zeIiWr3t_{^+x5kn=drE(`%{X0~?Zs3Ab?!RH
z)A=>KJn^qCx0Q)iEpB>pa8ps4<8f6`Tz+J=SG-2|i8dHGkU^?oAX4}d7>J)YaCj~3
z*AL40U=#}ov56A+hpl{?b|R|hLzUqQs#;b;7FvW$-)?aW*lNWH4bVA-=G8Mcg~
zst-O{M(yXG(J{Ka8=nq06Dc>&l04P2t9R}oRX)CRZsxNnt9^M#&{U7M
z#bGEpsc@kE=V<-wBOf!{a8)r7LYXL3!rr*BZ>?j*jBlh-iTA6~;@06ghvDsM2agBi
zp7CP2$AO^mKz|XI?7_YGwa1nm$$+bA=2yw|`D6B+;SbD095`~5AE_CgoCLcR79YU!
z8m4HOj%CK%w=PaiF(ZUNhHR6}f
z21BJ{aL=6*B1ooadl!lzWQrRQOjTQ3aiYB0cCEMsvSGcNal0v_H{Di%z2EN=1Jpw)
z1Ovf-w_J!SwJUktwHNZK;W7sDPBD(LtMHcjQ9=G7UwemBrnrNe+|1^g9b4ynsR;Js
z;AD7>*VTK=g(eS3vIzQ40})f>N4N_~2mGKEMdajWU+m0|=Z|-!8}kVpYdS53Kf1Oh
zSC~l?r?oD)B<*}`y)WYXM1;yv_64v&o&roDjLC)UaAyU!m=b3g2I8Yr42DJ}-0iP)pep%W1BVw&qZ&0My?jeLKG7|2SkS~N`yf|gW(
zc-o(S9(TXl=82(jw}ad38s!0_l40E@Z?*tJ6ASvUkL;KqB-BN}+(CSjH)xOgKG?Hg
z<}dp*^2t#ey~%x3y^QcuB}ub!%ADINT87^0opOhI;UZ9la@n#Zr#*_}OX+z#&8xYb
zt4irx8F2;T2Q&H;C613Pux|=Mf`cDNyzVD>VR|fLeZOLQC6=CA1;zcEH0h&INLW$d
zZoh(qbKh(p9-$S5s=1_Ls$SPe;|=;bAVloH9K*DtE2$CucAatTxA#_%(L+
zdxb@QJ)_tXxV98Fu&3(AB&}LZl$oy^@wYKe2Q6YCB`X-n
zd^uVesIOSQuAr%Cn(rTM>aov02+Qy?>>O{bDywugHD%xZjA*xYpT&=7Zu+1~IVPj^
zGU}0Yz&?E`@Z$ktt0J(&RSYCFX(QMB>d-Jks4?2wl>tUZEC?3qKz<*y}@?1mBHn5NgA`x#8#en}^$V_=_Q#>T4{X+)2?m_iV%P
zl$g6`DiXQaE)DkfJ&$;Dyq-mSp72EY(
z=D53B&dO#-@i-y-tcv{p$0yt=%sOwQgR
zp|6EFQUr&;(Ttl=M}Q^r%?-v4o}KYiw!(Jy9`CKiX71PZCHv{Mjq2!j=)D^A#;MhE
zJvSs$76uY70{sh`)Ha%vyx&>9Bih6smG^XaS;h^xWyJ4&^)yv>)T0SYoOC-4mB0A8
z3nCZx70qXXb8e}u4)tN7AY+rc?Lfvx>>8}xtA1%_`}}J=_TJvlF9U%_`X&s-H>pLc
zNrI1tNXJfFY&D_JwK0RW!nX}yZk+}`9pv9Y`r^#>&y$4SuFmX@)A>YP2yWp?Y|by5
zWBbLkg|U^ZLiwS7g%32|DdjA@Fh4DFzNW-;YnH1ZgoDBJ%46Jf*)5mnLxq}be2d1>
z_rs27Fp#HEyK+z_Q_+X8N$oAg!uKVCu5{}%UiqSeF}9**djjjc@5LGvmIB7y+pMXI
zAM`LUIVVZ9@R?4Iy3F6Xo~?Zt!rJ;er58|Qg8*;K62)xi4jVhRG4A~#*B6>Zdt
z8oot-RUP@2+u5&jvBZbA4x<+1o7Rg)v5W7XW%}EHm3`)T!t(W
z)msiop*;P?qx7o9{QLpk-4D{~VPvJB>*Wdc1+W4h?%hzIzeK(O`+=A2FzATpGck}_
zl>^l_j=I$=BXgW3qqn@`;yXKmVtoS%XCY5NMWNHUcr%)GE(+&woRfVy62T=}D~t&I
zs~LwcRXw<07U7+tpwQw@)Tr%l@G&^dd7u(Swx=W|Q(Ex`ui|=cM3_HD8
z`vc|597UnLQUh)2St6l)yvD0Tp*k`f5Q2jS0m0c2d)atSbyK|
z;1~$0Y%CLUrwpWI90PflpXiRd=IR1leESz)N=*Rd0~yfqr|GBdLgUdg-{9`fyT~89BXdeBMIKS1&g_{uC
z6O$#9lcHN(dM_V7pxyh&~ON^H5+htwvYTrx&5C3Q~et+DL&Sz2>9abQDPCXvArVN-&!Y{D}$+n+uJS|x}W>b{Sw
znj@WUEvVIhkU#8^wPRZ2B%ILDr!H{6Gd81n%Wz54qc!rB!MlVztkEMBkzV#`m)z?<
zJC~tJ`eu50+d0KnG)gKo7n&tV4Wx-=a&O+NET$K{_XWWObIY6S*{#UUvmo}I$7P|GLl1H)`}tdViB6kfpUlp=jR
z7#<2toLR7rxfmUggQJo$Hf$)FSJ39j(wbawmOE|RPjEk9xT`+4D|rO**`8R-<-l-Q
zF;s_IxlOWz@pitPeu>$%|Ks4PvJWDr-n6^BsExi4UsHq5xf7Ig-y;ru`q<+sYH}u0
zz6%1;R`Y!_6**EW@XUTPQDw(Aw(x0?N+z=k{dodns+bYUL~6h2y9tf<_T|dy#^qTS
zj`mM`i|Id_8?4kxgF#u`E~o_
zSRV-FN5xNf*39Fjxq(eu*DY3QSf$J*hmd8?T>9S^b+
z&PGfb2@;sdJ)SLxD;GAwY@Gl@)l7#;8s0+*WEfxr^|uyT%1XQ
zfj}fg-#?_W=#lW2m~8}bcB#C;NSDT__%H_Xxk{1kMPW$C!lu9{d4!hGG=p{P;%nW2
zD4+Z`A7}B%O(`dY8@shfH;=HCTaQ8`D|hq|iYKZxK-m1coREoI(y*}6p5aiH%%%ya
z80d-R77|83Y`=8%i~LI_k-nU1Ke-tWj~zh=;~o>miXNeMk)rHOCf8!@+|;uiUf)+lZ{K)O7}am+i_muk+q4a%N%9zI}FnDaN}frMsrrQ=JTWF
zNXSfs!z^RGaM)@B=P}Q*%CSP%F%13i!|qn?-Z=b?@0#%LR1#gXBkx{!1HD4|4c<+;
z$SayR??!aWiPW{?-j9e#lo^yAU?{4stnx!EHe?f3dov^suPOw5r60lXCbV;qOoQN0
z5uHmCV)vWi2`4SyB|76z}I^5FX4F;2YIp-gf8Oa;CuE9L1H
z8u^jxJnKBh!q3heulESzm74j@tf8lKD)-2$YxRkF9wd81-HeB=;{*4UUr)BNjb7DI`b$SrZBC~zDpVMBKDKi}~Q-qkO8WdC~KTpO2h-s#FsD)zvRhG-DD?AF-oBz%W2gpxCSA!Xc
z-ICcz%N+yC^|
zMH%*xx7atQ(ldKgfe%1}>XkS#tt|{>x%>BPZ{}P4ITZ~g{AkDG`(=q4t1_w|;6&F@
zf4>L^K^)9>jlj*g_cFg#LhZ~*$)zMRzhaBf6(C;mhwkHz;ez5}j0Fo__2JQPE16fA^o9aOQr*8N>0s}##
zz?A@{>|nuor$5T@Gi<&=gt%=94sI|S2LFDo0JC^Hx&p{!BMfA`1Ou4@bDdA4Q-Q8h
z3qo38i~Y-yYy&wqu{D)-fL~X$`vY
zNJY?e(SQcXRmnnYlnNJQSH4{fgHigwe-fYZ%>RYWo-aI2UYbHPqAS6>{=kB@G%4tGfuo7>ql>DyJb}SmWM2UTZFTEz_!z7+?O#5Z
zAu}b&_=1ad^5xn%;I+4isX
zQ`UBopFiECi2q$EFN7V9JB*%8U1v#nXQR!S~6oIe|p%V))H*HRM=8oo9ZCZN7CaRdXI
zPC_a{hwgxTf}>q%p>He=T@q03;+O=1>-C*H}P;3{8gRY>1=aCqP+
zQGaXoZMgofIdEu2&s^&=vS;u4h!nj~jgVPK6Vg>&%P6n*Tf<94c+EYpU5ThLheZG@PcQyo&&j+A;U~nbFXY}W{T;Thq=nIFbU&D~k!SW*`
z(8Q&+c5Fn)R8HD+cQpWCq1Jwg*}-GQRptm@;*R6Jt;wxn5Bp}>@fN-osR`QqP~wC8
z{k&<4IX+4{j@a$z#Lc?7rK76n811R&A;i;^D|W=N5$$In9tTEHfFVp&Qr0
zaI1u^1zA&vfdB*tgLDj2vKBOxme6D~aHg#V
z9eR&ty3h|Nz_2tGX$2Z;&|p=-))z34i}S*#%lTu;yc(3?+S~SLo{n&fPd0prnUxXV
zVgTAlv{)UJmvl8Vu8zh$+Zxv!8#k=^S}CnKWVSsfqHfaE=NLn;5p7BwJo4uJDy+l~
z+&5n%IX;3lhpp1U4v+oO=&;SVXG!jC81(0T@QB%S%wiRq6#zLhCpxjPr>dpG8jl~MUD}IAK2a}K%t=1
zvU?#(NYpprWDmX&uxBj9KM}tcpjDJ0`ug~FoI||3twX
zW1f4%*|8^n*^NrI1l@!aFy4*k#qxBg`9E~`Y;m$R0?8$tDKU5I4fhSfdrLeEJ_AqW
zFOf2;(x+KrXJ>wdcwlE^AXZ;NJ2nE{-vL6Pi1U_c!*49}M_S>0-sL=G74}5Ayv9Hz
zGMcaNeXUIAUtF^~yv41^&$rE>j1`2pxQ
zB%sL0OrZ0YMKXzlUhi!f`eqd9U{jaXVF|tqup%Ck!%Y|x-)P2-_wR<{^|cAyeqTed
zCvy*6R)7zE)Q$`d2%3ja3T@1zaDgq{Z!T-&&4DZ04|a&H0{Yv$J81X)x9HXm*nA_n
z;-Lm2zI5yF|1uRcdD2CHLs9Lg%s{!3)a99=H&
zGHmx&g?*HcMGwZ<4?0Ib$vBVaIgM|GVj$*VVgpQMy6>rQqP4vf4M(>3AJhfU!$R&8
zC)`D?FWCACYs3_8a%z;r13RDF_t&qRAC@)q)X}}G;3}CKF~}b-TlL=A5f8l5sQ$#J
z?sGF~m`I7~HH5Wq`kX8(4g=A+fPq|t9os{{Che*MTc#LD*&vtDaI$U9NcnCvM-kOIO!u}?kbL1%NK
zZv%UX1z-{%44ZJ^TcW>Zy#2jg(T~Ru>AvNSv-;2)U`v@CtlSB{y#*YwJnsT5fPQJP
zmn;lDEW2lkQa3`r!a!C_zknE=0Yf1IV8$Cv*Ta5#=G`o04%l834meB#^Wc0pG{_Ut
z9T-UV3k)O*iYg0R={m}UAA(7(VOtQ)lca!&@Dq;}&$xT2g~q##9tE>tU2R~Hnaw2j
z-vmkBS2<(rJ@T{!s`@Dyu7Sa5ow~Bm4_sg;;L3mEMbi)<_j0j?g#Jq7mKz(ve$6tt
z5%AP{lH>>%nCXBc4a|kf{fmRXfo@GaO~U7{3BnaIKmLPj-6tn{p9IOOatinYM$^|o
z5t;(mZYLk6QXKnjZXnP$U@9aDT;SEIhl&3gW?z6wT`wv0W9T6dCkAps_LoQRx%|$>
zQf8nFT#-y<%O?E^8y8?3d7@V^kegx1IB<*MMJk#y;|Xj5jPawuaDLOxN9em;K@l%u
z^I(I=h6Y2|pUBk?^guK592n`#qHni@n6MW-3!CpGa;V~%ba@*@acM_;9DfGiG3dK@J`zj$KB_<
zuum1f`1Qkz2XVPNI?bl#0r{mvkOMUgWmb@NFT>o(U(z}^T
z`u-kG6+K;H_iy>HijBwr)BIQEdm5niHE5c^+&`afdcJM*_|~;0*g6wBM7Nz1Nq7Wn
zUH=4|xhI8m#z1-^u02n&=3WqXi?sGoVL&u?e0F$J$igk(qFaM{oCG$pcBn!@Cx2J4hTMe8tc{&#<$$(dug58MKCirn$Oq%Rqx}gwJ=fVdSzP=j2s`P>E
zwkD;ZrBjdsvnbh69j-gU={MK6SksG$HJQj)=dIg4`}cWa1-y<&xI@4MH}DiXbWs3>
zZ3o++hSe9(ZFU8`t%?~_(ml6vcukTrh~*QOEF1o4pbPR4A;2Nm+NqS$c&oOLmcCGq
zO-o&g-J;q%C1Td04wnsUvcdw_*x_r0R=Z-+jiXN1!`c1fcj%AZ@CEXF;Ig$1O#v8N
zjqeZ^fM&xC6sio%X&A})()oe&RgsFWZaulD3u_s-wkuyw<2}^GDlUmOCcHerk+Dh2
zR;pw&KtplNZD$3rzD~s?yp{+1i
z)H9=Vzi>=uZ(Ax`B}0N(VV_K&>Ji)0v-Cp$s5+eBL}|B+9;uc&iyKBm`d6EBm#c)x
zlc8Vy>j=Un@Z+B{6-j#KDvY@teI%`?|(*511z-6dXq*@Y=-pU5<7OR-Du;{Lc*&3_Np!D=D_5@Wnm`dQ5}d)A(&FI
z*w-0=O?UwZeHX^h*_A8{4$KX>=E$Uu6Z|`4_AHEvc9$BFT+3q|
zx76ruLM|45RmH}SGF``W!7e+80b`e$5Y3l!0(J3z&u)5N_VH4v~#w;7~At5K}ThVz>A&P!4eeR=!fMOIhE|s8|XtKJ9pC~FLf7wR33k9`{d2}RJ>|AeuG=_ZkK{BnDZN|DsnG|z!8zaHsFi)v*WD=dD-$R)EHlDYMC
zDAbdK@)dc_4RP~UG<`4Gm=N-i_G(4q0M{il5z&I@#LpcM7J0PeG9ESxJ1Zp}aV_)Q;wXv433v{|gB@8z=%
z@ay!ZuBSftflQ|O^5qN9<8DR^8O0Hi#CabEm<_nYR$fr8JxCJp9W5;z9d@3-9pTVP
zqIB5uz%;bPCBJSrXuK1>XA0EgqySyH&;z3XMDueB=-h#p8w|X7pmX?d*7XTAmJv%8iB#{4pvRRsI#3
z9`lV#_BmGZKGvQ#M^VucGl=s;hup0c1&ku-#ej3+!jat7X;q*gn^SD*8`>Si5-n7&
zw>Mug*y6cNez?68yx$xamOnhmz
zlGWC^P_2uJxM)Q(;pP
zP}54Zf;9e{YEhiEeBUEv*0*;0)3%EYX_8I8fZVXe*NZa_9`*S$a;>>;n|WCSd?J=*
zi6RE#8l~REipGnf#>^ri?N6rf<~D!SA`_eGd6>
zxAodcJ^$7V{KIJN)lbkkjUpkeiq^5~-BH?63Ia)s5eng-67NPo9|gC6rfnR@l3irx
zKILnlJNqvu(XswBtE_(EWVu`WZeO0E8`mTUlmCnb1J|eSqz~DyFNLP5JBf(7DrNs=
zg)KoP{R?Ftyes{O0=_B#DWm`s_9v~5ffB_Z$h-Wt>bUc&{^4BPe}2j@QA=O<|JjK;
z4~`Lc+vVxH7nMfYG9&g1jb|UNqz>eKJusE7u0F>fXXbAz#A;9Hb=i|{w{IEPIvs^N
zz(98Ra%F6~!^yiK`6qu%`DN|BaF00Cn2|Ld-GIXmGyBeG2c-2z
ziNKsrYD8SW;+5xG4l_axW;k!?UjBi;Thhkk1?cuX2^t5SM58LmV7kX(kmdv~S4Ck+
zX=(dSk_N5&l1l~S%65tBe$+}Ym*-noG}JEN&KKBxClpB#2)5N`!Y54*
zR9d&eJj>gy+B#JFoV|T5xM9gD)G{`{wQ@XM(QG~6QhQ0yd)8+^WTGMzp=fPyt{BFD
zli2183**(tt@UpnIe(e>!(e&-jL$FF>gvi=W-OP5xo7Bm7q+n0T{biGO1m2%D}xms
zm<-t>kz_$H{SopAff}?!a<~o76APUE6bsFJJS)wCDCIJcmy#2FCATgS@2MJyFXd$k
zAQjfWRaSv}+1Flh{O)vJoV;9R5|^mX#+szaT#m4dqryG%(aiW|f-#mC6EeQ_2EXNV
z)63EA4vLQCN`9U@=_#;Z{A~k_UCHZB>KMSPlB3h)|Vdo5kMn#q4y{xRQsVlE?n8h8ujx#mNg|Kc?Gh(x{^iGAw
z2|S@6a3E!0H!rEE3T^nzzSX$m@AlZ~@hd#MNA3LhDwI7%BZ@UyHMC{R?+-<4qDwCf
zEPY!-fa#c@r4#y-@M`Hm-w|T5PF2?EY9Au)A|7F?&_GKE5$MN>4OtX
zLHm12f|~oaOWT}OKl~MXqkgc(vI)%4T=mnFCC}e1sNHB9$eBG
zssanFy3w(3fmR{~uqurizC)R(uyY+aEB~kjN}B#W$FOfiUMJQEuMFK**4B3$xIMM)1=N3?%)QL)a#dRBd;j
zBOjr7ovT<$tV|zk$1Qn=WMd6+$BK@d)DSW+-2NQk*+n))KrvBugJrq|MUP=?$ZRW=
zX;yHCwAfL|cbxgM+13$fgT1M8VGLou9rf#mL1FFd3=wl}BCQ$G#})UY28E{590RIS
zt>Qah@3q4Y;;aWqz2h85yX>;7okLa2P%C~s`$~4{YQuDbj_u?>)*l-3V=28vPOd7B)2ppz1kk7+YgB
zmb|7(i%pqOD}ZG~ZYXh|p`a|z{e{R^*^bv^{P6uQ{BsGa)W2_B8O*%SymB
zO$|&f;FGV3holQ(9CNFN^Z%~465
zLB$}Je9X7f46<>Th}LK%7+C_^sHkSGrVQxgapJalbk?P(;_iu4?}`r}@ltN!{bII2zb=&ZkCiB{P=hrut*U;!r)
zx{Bmz9f}TMHL=(Fw27A(Ju|<`Up#VHUAz8rBY(v7&EeNhui5uO
zewB{P{C=4gy==T(>F6juJNrRPO|N<4R^h2gH#!qMLK;ULjyu6D
zl^S6Uh8N)7mc4XKbA+|+=TjnuOP*AMM#YT5+u}IWweoq}(x@%Y+XYdfy!X!@2xQn2
z;(X*}?{U1||5#F%A)JtUVW@$aw2m^PssPDu>X~+MSE1MO3HDs)fQaP{IRhG#r^JLB
zqL0pUH9L25yYJt@tT>iIg
z;^zOjn(n`tO?-o(MJ;&===OdtiL&F0sj~6XcXW
zq%xTspnv#&+w#>2lCK|DC@TA|&f5Y5L7Yd}o$ry;0j9rdXjed1JI5gGTEHY;KWx4x
z2^o?!4EVzP0M9iP2I7#oyTGgABlyZko=$$!o=CHJljKRRF2d9{1qJ^cy=wNtDoT)T
z1)GPg&ZAlXOuGLKQG2hzk5%vTz|3!Kgcx{;mObjl%9v@v*O_S#LL8$#}Zs
z`u4z~UCC-S)k-}^(H^Z^%w=-Hhle!Mn<+`+i*2`(1e4o!rBVyZKhk(HuUWh!gaL24
zY#%}g{SU>1c@H!^v#mYu+mBq()ZAMs*Lsh`aBG|YrndgMTMZQpHX`rOj6qL#y_I4l
zlLh8cRkK6QvPt}l$TY0Ntv3G89Uc)>B6W<`XCAT8G(czMo*k1M@4r
z{(v=O(N-)Y$#K#rfqJOgo<}a6r9i~Bn2TSTr*&ela4L*I-&VI{Up3cN!pEF8c=1}Q
zt6gDsNrtnW+y%(mXJ4RUmQP#9`02BR@a;jD+eRSB*owAnuC5n
z*r#L6i&ZUXY+bQuzC_qy;HhH@kAaByW;S7LC!Ut=xuUQrqKc^PYvZrg_9gpfHYLY(
zsMwROO(PXw<J_O?)EILE
z6{yj-o~zUvp_ArW70MgI)nVDWE!t$PFewR8M{d{YzSP{mZx}0<+_P4~>Ps5GINTL-
z=XR|VOSSgXmk(YUG$zIIBS!`P4%KV>ptK;;XPjwNR*qMd2i0OcqMsD<(#ft3h@}ZS
z7QgQ>aGry{Ts=%J-`Fd3%(X7GE41fs*QoBR?cNI{hb5LnnWAS`X>_Nl$6Uw-sXrpn
zjj&F6`EMcn$zg4}r;^-!zn
zNYL`NZhB;Ueq@Pqd=uZmr{ph4RFof6BiE8!`E^V4|
z8P+xYEX3|9#4WR_@GOVmC^OinpBsw<%jAiAVZ#~HoC>722~4P-K-t~@ToErtu6$E@y|6ROiQuJp^)^KaMG
z+L65WIVqU`nO?{YH{8{+Mw1o=O$ptVawBW~m>jLyqs^WAhO9FKcc)9d@;>|tpOVbB
zT7|rw0iT3;nKMHXcdO+z%`nZg)g;x#1Ewga$X2vlHk2)!;u^o-qxpF|
zE4Ix8Th;zG&d4?OeopB|>`%=;k=bP%x1VThcxA
zGBjMruz_XCqx`&0Q)1uKk?vW-I%AI;BGk_PFa1AmOQ+gglroZ?(f4v0mR5XBJ#vvR
zL02-anTsV{z=I()<8N8kxr8vxxLTH;XQL{C*NyJl%Cid|d|cb^(#xUH2%Wb?cr*_~
zMz>wCCRa`Dh4>6)wTo*t``vMzu@Tla-Og0=yan4LMX!7|9X=7A)w1WeIm}NjQ12Z|%^pfQFx-#MMLE52_5hPR+Gl=20*yi&yctlJaIXG$hvuDcD!?Tn)FPZ>q2B
zHM5sf?`MWv4^pTjbj(JiXxlzselsn(-01tb7Yw~)i=ALt>c99n4=9*}qPKNX@-qUc^|c2nv>#oc1#X2tXGZ=ECy_5;1|+?j>q
zFK~PL+^!DwV!xNTwx?G~hOmA|Z3oene^p$0n$V7!>A)uuT>XNI!HGQ92f(H#4JZOE
zOA#N0e(NdwR}6O7U9*n{eKi)?1vi6t$Td!klv>e;*HlvQ!uw_GQFP
zPVPLD)tqXJJ_Z)f=ndy2h9GmEr6cs(P2>oo!ew`J;3tRC9SDAt9}!L1B>6f1b>^rJ
zaPp??9w-=Hr7hpOteP}MBUfy}qYC>*_2EHCA>S#nyAoULwe1;0Bc&r~!*PMn8mRVb
zGsaHCMI=;WBvgHW0#I49aEayW<SuHQo}ELo92f-PsFh
zztSunFsuEj-mVP-mPG;2K!T2wijGP}(5)
zd%@o)ca&ronk-LpiB?gqI0=YE-@-Y#d3T#o;&ODC!gNcYdf!!q7Lt0^Y3-tR++bSC
zoWEAFhlA?sdzt$+l+(a4Y?pg^e19DSDOW`mV<2}qYCyXKcBH$TqH>_KNYw=(YZsVb
zN6W*u#3F+>;j2kUaqjEK`(XK8CK`+!vSJOvHWL6<6}GAk=B=mvQ7T|=4hC$2Z4D7C
zFSSB25U{hSul+qR4o8p5?scJVSM8&Y!7{!+z^3I8pnxv<8Xbb~BUO-LW+@*Wk1f&f
z41CbwqIGWxRt7AY55m{S!4+)ku_mnj0IY+%y95gEI5HBL@wxh!6hIM$Xrm^Aqa-af
zNYM=Fs2GOY8W@bjLvwHL5R>fW!B+KDk!rv=xZpm$k@TmO6=l7WbU?y`_%iCF-{!5t
zej{yd98m@zi$Wve2dbzXThtY)*M5O9AfdM9ar7R*n7VER)Kmcv)SVW7zhbanj(LHS5ZHK6_zQzi
zu>NR9>5y*q1PIVSpwW8r=j`|Wh6i-1$?@>;JNG?KKoIr=8P
zCowo7AL5l~$Ad_AP0Eo-FlWSsmaRSsf$R@xC?{bj>Hh^9{Xj=hObYeT4}ssLWEB1f
z2B6e|otzZ^7GIKoASyz8V}7cvWazS3r7=nJR@ZKR6MTRPd=kr69zo+pi?Cd!%n^en
zt)h0q=fUC34%sf+t*-mdhS|TD%$aWoCo@);@2_}Yk`Ks|sS!6@ZKKMt$e)VzP*GE0
zPN^ZE|9?Bll@8|XE7QRQdz#S^B=2J97ubw`54h>m!-;}uhFB{eIPb{v^Pr|O4wB};
zo_QROLkz73yrRrN#hHSkT{w6g3U)!3UIe1KZ(%!Uq&=k+R?G$_Y@o*z
zswcjZx-2e}^uIz-)gALD%POAU3o$(#s?GdSkTq=1CfO)nvydmbon|B;C~}N1esAnT
zXNw690WC$+A{fmN4M4X$RgTdZ2vS3RnOQ{pm8z>&<#TB;)nKX(bP2)MK}QdsH*?~R
z22{u3#ZmE^iK-rO^5@W>-sl+kFLnL(gVcS^JxFrI=dMzgqeAXsAfhv%Qv~B0FxmR^
z+g&h&lY9K?rRMk^Um$Wj3Y;x?<_@Lo&+i7n%0F;cT4K{lhve_Ua3u*Hth){?%yn{#
z#2Gs5bUuuq5Ve?7!8H_GYA1#5Bl-!j2FMWLVKtAr28Wiuhc+hAPADc78|CG07^qkah47EES6sXKh<{cPH)PT^
zXz}jznJO2Ni>xo`L@Fu<9`M;ZCL7Ay=dMRsRCpDckggFYn+YC&YVkOW1>q94v@trz
zu_}7Ij9lejx^*#cyFK7-%a|e?s!Aj?Y@i|M9#QVl+XyAv(d!}UWNnaehC)?SPF0!$0=cLi9iWjeeQ${fVw)`N{upffrg1#p
zflum#(a^U;L1e!j3Iflu(Rz`oYb|UmLA%E+;+*i`HnzqZu+aZJ6M%6M3<1s
zdSRrS48>tN5Li21Z*$
z(s=C8RB$vpjz%RkIILDg7VQEQwz?b%fa9K?fvir6&$SQ}{8RaAQ`4U`uwK0yXT3c8
ziX^(YO?qDVZ26y#RcWh2)s}aVz&lFQ%1^ea;!caqY}r3}9Pyw?eU)@XW{e?dZ>U$eFu1{Kwnb%(WBI2;rGpg}kQe{A
z+`ieHOMt8x2FAg#<83{FT6|
zd59q01bGl-YyJ5n4!*I>|b?;5y+7Cj_z)OeIMs|Om4
z5SSeL-NE|d1@P}pcekHkrBMBU*n97|sFH1MxD}NgM35XL2ofddsDOw>$x#K#IU`^r
z2q=;fkSsap90U<0=bS;Jga*l>q5TTS8F9`%bMCok?)#m4@BG29>D{|(*REPswN|aQ
zo=2zo1ty{jdIZu4e2f#%iIMBz$SbOzEh)7%mpD{2Rhv!$}c$-#C~}3WFa+m
zH>J*m+c8@(w+N51^q%FDcx(PE%OO$FIcywF%=_XcbuPOEgG{+O4(J(5S6{N+f0F%i
zVOPOhPV%X(HJcxd6NWad;QL{$rs!Td@#FM$6%>>ygS)vE`gG5lP>xMq^HE21otv5)
zw`6Qtb7pQz5f>dkzGD;07K`|@zmqD*ZmsHGM=hwFRCuKdm|Wbp@z|Sz*|Y9i4P`La
zU@z&2E%<^OTnqIc(t%`ml+1B$wM~;*A0xW>mpEVFQdxb4l8A-HL8I*@4UN0mAZBm|
z1EX>^ez00gjI)&QdjAuEqWH_)1@reD6j(uO;804ZZcid>)6~hz_L1MksI*Wh6X&z5
zv@at#!aU{Vv=S+U`E9TFq@x6Ku0HdEKhH>H>NCjzb%N!y;=o97!J@8dId
zHZ$E_5>6S85qTLOAo7fm`=~Z+sIZkG*>I{&Y@vc_QQ9#c%>y07-v|i_IW|CYFkL6a
zJwWsG#7R`hO#LQ6JiAvRm>0%KC8$;h~QR@k!^9LWVsd}vsZhO%wEGMq0;X&89NdevJ_9f8E`PP;3XIFMRT;7bNKQo
z6XP{cZd9g)MO9?8m(-UpUi7;<=~-GjV})ZzJeZwVXoewY@wU3$KFqELH|o60n{!Tx
z&xH&S0pGR?s$#CX3%9PPGA;J2RY@mT1U-#%B4trBG9l-?Rpq0w-cjw$H@4#FIf?vy
zCyFy0H|RnyWgssVfn|_g(M@q*1A+4%)>$=J>Y-ilEyyh`?mcdAPwdkICjjEZC%}Gw
z%f-jaiqX?iw6VROUXH_kl?!#zg3@~eb*o95#@2b+XZ*~qI>bt-uW}n#5~uF;STrhe
z+s-kDJ~f;P$hu4{g5Ha*Dw8CT4$5=AXGRZ;8xz
zkCl(q$g5KTegmIs%aYDVeIIei9bo~h+#keh?#eocbB>&KWjW6qHc
zZmNJH0c2V&%D6hp&tmi2{a4egE45-?syZrru9G}OQ5kDP=t|EyLY-|qk&yx`<7J5_
z=hTy39{RRwxloIvgwl55g`$#j*rEvTF2AJdrw(06WpBGYuVL`~a_OW^X%LAIcRu9V
z*3SI=`4j>tW;-iJxsI^OPVPaoT*PCnshg$!oNGCg{2xd+g<+~Cdrktz`
z=7O~Z5K_0LJb9$}%5w53QYS|G2&I?QGNd#C8L+qx-U++P3Ywspbfk-EQDm_%+L?+_
zlG()bB&p%lM3s}4v)<3
zYPl<-dF^=BlTSgl=MatD8oK
zzqm|PAO*d|n`pB8z6WE$KuI;TF8!l-0dWt*4gFJciKK`c&Zm(2M+0pZWj$;UyU;ys
zUl%&&?w64cPWq-e<4U(k`;FQ?SnRL(^?6S
zB46#s$f_w8l@!ZVaxRoj;&IznRXba9=l;k#p3K1mOPj{Dw#sGjHvH{CnEGmn^
z#iu~&4#8bIX@Tx==1XGg+Rb4JqB>rC906$48^*@Mw+(pq;Zw132`mK7vk6DQj2fNK
zdjcFUsbFiq{)88MA4Bf|C@!f<)6Z+L)10;L75lF3Iq`b~0Xul(9-^c=(eY$U3bQ<4
zOug{<=D5DagRv$HCg%LNh3Cg{S;xdKw2Xg&-y+AmF2A7bC1JlMIaD}r*S25T!TMaV
z>`PAJ^rJb^pjM2Y1v<$WAV8UAM&*TqSSwP6Deaec`y-UaK}yBZ6HU|R<#qiL&X(7W
zwuvngUuP3AIj%FX-@L?_o|M2qz`;ufKvKP9&8&pBC&uE)cA6!uE3;xsQ1
z^1kQe%?taWOL6MUva2Ee(uY>PiYk5qWu|yJH+$AQ7M607m
zwCahy1E%aZuSowdaX+?dr!JFW-`C3KqZgt{`!#O&nX(+E@KBif!Ct?XF2noqF&1Ty
z(sK%^EGex8YZ#cDjJMJZ?Esa3!*cpab-=FcT
z_vfttK^6EGEr92xqo;<#>g~$aebw!ShkmnUG1&Br=Wtr}5qXTp$-whL5=674ce}r?
za7RW+uyd*Pg4pBOynfC&T}dJl4mLxYQ0Yg~bkRZZKX%Uj12@oj!m5GOu1g;n;+2V*
zX3g+x=>2TcjfhXv`&m#}%AbLGrN%X9b$G>rVm}N3*5%rl%B?qzD-}ibt&6auk}S$L
z8exXCEM?$xy35wDyOQsA+EdCob?kHVAF
zV}Oa#m$mgIoR)_nx(q?M3;aC+*sv24gy#^&0d4}oMEfUd&8lTBdAg6dZ96~RsRptG
zf`ALa7;5!-dgp2ZNOO1%py5QycdU-k)uA(Yp#esJ0M|h9aW7~JENXnVR*PURdNc!9
z0O#4l6yrxcCl_->zR-#^6$8J<--C~MH4B&8fXH^t-XhnH0R`Wb^H9d*yH3ZF7KrA%t#8)*aIhL3arIpc^y4Kr=kA
z>PC1G%by%m9P1eTgh=rd&;{#by+eJ_PKuJYy7+tq5;o$_FjzOw6sGv++Lt`4hEPA*
zIQANQtk-=ytiE7a&A`~{fB_T>phF-!=gmg(81LkvQ84tJJ@%1t=^(A&~5W
zA&wAn1#^5aN^N@(j5pZ&T8Y81{yZYd2;5bXBMcLf{V&i>hmhY_1G?)BkcqM@!&gW<
z1@M0cyWYz_1pDd?*yiU0puce%B
z{nrMZysd7l8HhM}KLg@P-2sNkA+_Gw_p^uoG*U%BNejhK0{>lfuua0DLVCxSD2_vb
zPI&gEM1D6u8b6o+otzit9~Z)>50U?p#J?o*bf*0!i9c<^{|nbdyV+HC6vSwsZ$*e5
zI9DIEAGTMPP|Q|;D2aRoc6^0DS`#yxuaG65F0&!HF1O3$ep!DKPwD{fiYC|{&ff
© COPYRIGHT(c) 2022 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#ifndef _BFLB_SDIO2_H
+#define _BFLB_SDIO2_H
+
+//#define BFLB_SDIO2_ENUM 1
+
+#ifndef BFLB_SDIO2_ENUM
+#include "bflb_core.h"
+#else
+#include "stdio.h"
+#include "stdint.h"
+struct bflb_device_s {
+    const char *name;
+    uint32_t reg_base;
+    uint8_t irq_num;
+    uint8_t idx;
+    uint8_t sub_idx;
+    uint8_t dev_type;
+    void *user_data;
+};
+#endif
+
+/* SDIO2 buffer size */
+#define SDIO2_BYTE_PER_BUF (1024 * 2)
+#define SDIO2_MAX_PORT_NUM 16
+#define SDIO2_MAX_FUNC     1
+
+int bflb_sdio2_init(struct bflb_device_s *dev);
+int bflb_sdio2_check_host_ready(struct bflb_device_s *dev);
+uint32_t bflb_sdio2_get_block_size(struct bflb_device_s *dev);
+int bflb_sdio2_tx_rx_queue_init(struct bflb_device_s *dev);
+int bflb_sdio2_send_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int len);
+int bflb_sdio2_recv_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int *len);
+void bflb_sdio2_isr(int irq, void *arg);
+
+#endif /* _BFLB_SDIO3_H */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_aes.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_aes.h
new file mode 100755
index 0000000000..6ff8e01422
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_aes.h
@@ -0,0 +1,247 @@
+#ifndef _BFLB_SEC_AES_H
+#define _BFLB_SEC_AES_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup SEC_AES
+  * @{
+  */
+
+/** @defgroup AES_MODE aes mode definition
+  * @{
+  */
+#define AES_MODE_ECB 0
+#define AES_MODE_CTR 1
+#define AES_MODE_CBC 2
+#define AES_MODE_XTS 3
+/**
+  * @}
+  */
+
+/** @defgroup AES_LINK_KEYBITS aes link mode keybits definition
+  * @{
+  */
+#define AES_LINK_KEY_128BITS        0
+#define AES_LINK_KEY_192BITS        2
+#define AES_LINK_KEY_256BITS        1
+#define AES_LINK_KEY_DOUBLE_128BITS 3
+/**
+  * @}
+  */
+
+#define AES_LINK_XTS_MODE1 0
+#define AES_LINK_XTS_MODE2 1
+
+struct bflb_aes_link_s {
+    uint32_t                : 3;  /*!< [2:0]Reserved */
+    uint32_t aes_key        : 2;  /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */
+    uint32_t aes_dec_en     : 1;  /*!< [5]Encode or decode */
+    uint32_t aes_newkey_dis : 1;  /*!< [6]Use new key or use same key as last one */
+    uint32_t aes_hwkey_en   : 1;  /*!< [7]Enable or disable using hardware hey */
+    uint32_t                : 1;  /*!< [8]Reserved */
+    uint32_t aes_intclr     : 1;  /*!< [9]Clear interrupt */
+    uint32_t aes_intset     : 1;  /*!< [10]Set interrupt */
+    uint32_t                : 1;  /*!< [11]Reserved */
+    uint32_t aes_mode       : 2;  /*!< [13:12]ECB/CTR/CBC mode select */
+    uint32_t aes_newiv_dis  : 1;  /*!< [14]Use new iv or use same iv as last one */
+    uint32_t aes_xts        : 1;  /*!< [15]XTS mode select */
+    uint32_t aes_msglen     : 16; /*!< [31:16]Number of 128-bit block */
+    uint32_t aes_srcaddr;         /*!< Message source address */
+    uint32_t aes_dstaddr;         /*!< Message destination address */
+    uint32_t aes_iv0;             /*!< Big endian initial vector(MSB) */
+    uint32_t aes_iv1;             /*!< Big endian initial vector */
+    uint32_t aes_iv2;             /*!< Big endian initial vector */
+    uint32_t aes_iv3;             /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */
+    uint32_t aes_key0;            /*!< Big endian aes key(aes-128/256 key MSB) */
+    uint32_t aes_key1;            /*!< Big endian aes key */
+    uint32_t aes_key2;            /*!< Big endian aes key */
+    uint32_t aes_key3;            /*!< Big endian aes key(aes-128 key LSB) */
+    uint32_t aes_key4;            /*!< Big endian aes key */
+    uint32_t aes_key5;            /*!< Big endian aes key */
+    uint32_t aes_key6;            /*!< Big endian aes key */
+    uint32_t aes_key7;            /*!< Big endian aes key(aes-256 key LSB) */
+} __attribute__((aligned(4)));
+
+struct bflb_aes_xts_link_s {
+    uint32_t                : 3;  /*!< [2:0]Reserved */
+    uint32_t aes_key        : 2;  /*!< [4:3]128-bit/256-bit/192-bit/128-bit-double key mode select */
+    uint32_t aes_dec_en     : 1;  /*!< [5]Encode or decode */
+    uint32_t aes_newkey_dis : 1;  /*!< [6]Use new key or use same key as last one */
+    uint32_t aes_hwkey_en   : 1;  /*!< [7]Enable or disable using hardware hey */
+    uint32_t                : 1;  /*!< [8]Reserved */
+    uint32_t aes_intclr     : 1;  /*!< [9]Clear interrupt */
+    uint32_t aes_intset     : 1;  /*!< [10]Set interrupt */
+    uint32_t                : 1;  /*!< [11]Reserved */
+    uint32_t aes_mode       : 2;  /*!< [13:12]ECB/CTR/CBC mode select */
+    uint32_t aes_newiv_dis  : 1;  /*!< [14]Use new iv or use same iv as last one */
+    uint32_t aes_xts        : 1;  /*!< [15]XTS mode select */
+    uint32_t aes_msglen     : 16; /*!< [31:16]Number of 128-bit block */
+    uint32_t aes_srcaddr;         /*!< Message source address */
+    uint32_t aes_dstaddr;         /*!< Message destination address */
+    uint32_t aes_iv0;             /*!< Big endian initial vector(MSB) */
+    uint32_t aes_iv1;             /*!< Big endian initial vector */
+    uint32_t aes_iv2;             /*!< Big endian initial vector */
+    uint32_t aes_iv3;             /*!< Big endian initial vector(LSB)(CTR mode:counter initial value) */
+    uint32_t aes_key10;           /*!< Big endian aes key(aes-128/256 key MSB) */
+    uint32_t aes_key11;           /*!< Big endian aes key1 */
+    uint32_t aes_key12;           /*!< Big endian aes key1 */
+    uint32_t aes_key13;           /*!< Big endian aes key1(aes-128 key LSB) */
+    uint32_t aes_key14;           /*!< Big endian aes key1 */
+    uint32_t aes_key15;           /*!< Big endian aes key1 */
+    uint32_t aes_key16;           /*!< Big endian aes key1 */
+    uint32_t aes_key17;           /*!< Big endian aes key1(aes-256 key LSB) */
+    uint32_t             : 16;    /*!< [15:0]Reserved */
+    uint32_t aes_unitlen : 16;    /*!< [31:16]Big endian aes unit len */
+    uint32_t aes_key20;           /*!< Big endian aes key2(aes-128/256 key MSB) */
+    uint32_t aes_key21;           /*!< Big endian aes key2 */
+    uint32_t aes_key22;           /*!< Big endian aes key2 */
+    uint32_t aes_key23;           /*!< Big endian aes key2(aes-128 key LSB) */
+    uint32_t aes_key24;           /*!< Big endian aes key2 */
+    uint32_t aes_key25;           /*!< Big endian aes key2 */
+    uint32_t aes_key26;           /*!< Big endian aes key2 */
+    uint32_t aes_key27;           /*!< Big endian aes key2(aes-256 key LSB) */
+} __attribute__((aligned(4)));
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Enable aes.
+ *
+ * @param [in] dev
+ */
+void bflb_aes_init(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable aes.
+ *
+ * @param [in] dev
+ */
+void bflb_aes_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Set aes hardware key.
+ *
+ * @param [in] keysel hardware key mode in efuse table
+ */
+void bflb_aes_set_hwkey(uint8_t keysel);
+
+/**
+ * @brief Set aes hardware key source.
+ *
+ * @param [in] dev device handle
+ * @param [in] source hardware key source
+ */
+void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source);
+
+/**
+ * @brief Set aes mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] mode aes mode, use @ref AES_MODE
+ */
+void bflb_aes_set_mode(struct bflb_device_s *dev, uint8_t mode);
+
+/**
+ * @brief Set aes key.
+ *
+ * @param [in] dev device handle
+ * @param [in] key pointer to aes key, if NULL, means use hardware key
+ * @param [in] keybits aes keybits, can be 128/192/256
+ */
+void bflb_aes_setkey(struct bflb_device_s *dev, const uint8_t *key, uint16_t keybits);
+
+/**
+ * @brief Perform aes encrypt.
+ *
+ * @param [in] dev device handle
+ * @param [in] input pointer to plaintext
+ * @param [in] iv input iv, if NULL, means use last iv.
+ * @param [in] output pointer to ciphertext
+ * @param [in] len encrypt length, muse be multiple of 16
+ * @return A negated errno value on failure.
+ */
+int bflb_aes_encrypt(struct bflb_device_s *dev,
+                     const uint8_t *input,
+                     const uint8_t *iv,
+                     uint8_t *output,
+                     uint32_t len);
+
+/**
+ * @brief Perform aes decrypt.
+ *
+ * @param [in] dev device handle
+ * @param [in] input pointer to ciphertext
+ * @param [in] iv input iv, if NULL, means use last iv.
+ * @param [in] output pointer to plaintext
+ * @param [in] len decrypt length, muse be multiple of 16
+ * @return A negated errno value on failure.
+ */
+int bflb_aes_decrypt(struct bflb_device_s *dev,
+                     const uint8_t *input,
+                     const uint8_t *iv,
+                     uint8_t *output,
+                     uint32_t len);
+
+/**
+ * @brief Enable aes link mode.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_aes_link_init(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable aes link mode.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_aes_link_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Perform encrypt or decrypt with link mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] link_addr link struct pointer address, must be located in 0x2xxxxxxx
+ * @param [in] input pointer to plaintext or ciphertext
+ * @param [in] output pointer to plaintext or ciphertext
+ * @param [in] len update length, muse be multiple of 16
+ * @return A negated errno value on failure.
+ */
+int bflb_aes_link_update(struct bflb_device_s *dev,
+                         uint32_t link_addr,
+                         const uint8_t *input,
+                         uint8_t *output,
+                         uint32_t len);
+
+/**
+ * @brief Enable aes in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_request_aes_access(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable aes in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_release_aes_access(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_dsa.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_dsa.h
new file mode 100755
index 0000000000..ccce397bf6
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_dsa.h
@@ -0,0 +1,82 @@
+#ifndef _BFLB_SEC_DSA_H
+#define _BFLB_SEC_DSA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup SEC_DSA
+  * @{
+  */
+
+struct bflb_dsa_crt_s {
+    uint32_t *dP;
+    uint32_t *dQ;
+    uint32_t *qInv;
+    uint32_t *p;
+    uint32_t *invR_p;
+    uint32_t *primeN_p;
+    uint32_t *q;
+    uint32_t *invR_q;
+    uint32_t *primeN_q;
+};
+
+struct bflb_dsa_s {
+    uint32_t size;
+    uint32_t crtSize;
+    uint32_t *n;
+    uint32_t *e;
+    uint32_t *d;
+    struct bflb_dsa_crt_s crtCfg;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] size
+ * @return int
+ */
+int bflb_sec_dsa_init(struct bflb_dsa_s *handle, uint32_t size);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] hash
+ * @param [in] hashLenInWord
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_dsa_sign(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *s);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] hash
+ * @param [in] hashLenInWord
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_dsa_verify(struct bflb_dsa_s *handle, const uint32_t *hash, uint32_t hashLenInWord, const uint32_t *s);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_ecdsa.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_ecdsa.h
new file mode 100755
index 0000000000..d1cd6d4e27
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_ecdsa.h
@@ -0,0 +1,158 @@
+#ifndef _BFLB_SEC_ECDSA_H
+#define _BFLB_SEC_ECDSA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup SEC_ECDSA
+  * @{
+  */
+
+#define ECP_SECP256R1 0
+#define ECP_SECP256K1 1
+
+struct bflb_ecdsa_s {
+    uint8_t ecpId;
+    uint8_t pad[3];
+    uint32_t *privateKey;
+    uint32_t *publicKeyx;
+    uint32_t *publicKeyy;
+};
+
+struct bflb_ecdh_s {
+    uint8_t ecpId;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] id
+ * @return int
+ */
+int bflb_sec_ecdsa_init(struct bflb_ecdsa_s *handle, uint8_t id);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @return int
+ */
+int bflb_sec_ecdsa_deinit(struct bflb_ecdsa_s *handle);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] random_k
+ * @param [in] hash
+ * @param [in] hashLenInWord
+ * @param [in] r
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_ecdsa_sign(struct bflb_ecdsa_s *handle, const uint32_t *random_k, const uint32_t *hash, uint32_t hashLenInWord, uint32_t *r, uint32_t *s);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] hash
+ * @param [in] hashLen
+ * @param [in] r
+ * @param [in] s
+ * @return int
+ */
+int bflb_sec_ecdsa_verify(struct bflb_ecdsa_s *handle, const uint32_t *hash, uint32_t hashLen, const uint32_t *r, const uint32_t *s);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] private_key
+ * @return int
+ */
+int bflb_sec_ecdsa_get_private_key(struct bflb_ecdsa_s *handle, uint32_t *private_key);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] private_key
+ * @param [in] pRx
+ * @param [in] pRy
+ * @return int
+ */
+int bflb_sec_ecdsa_get_public_key(struct bflb_ecdsa_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] id
+ * @return int
+ */
+int bflb_sec_ecdh_init(struct bflb_ecdh_s *handle, uint8_t id);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @return int
+ */
+int bflb_sec_ecdh_deinit(struct bflb_ecdh_s *handle);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] pkX
+ * @param [in] pkY
+ * @param [in] private_key
+ * @param [in] pRx
+ * @param [in] pRy
+ * @return int
+ */
+int bflb_sec_ecdh_get_encrypt_key(struct bflb_ecdh_s *handle, const uint32_t *pkX, const uint32_t *pkY, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+
+/**
+ * @brief
+ *
+ * @param [in] handle
+ * @param [in] private_key
+ * @param [in] pRx
+ * @param [in] pRy
+ * @return int
+ */
+int bflb_sec_ecdh_get_public_key(struct bflb_ecdh_s *handle, const uint32_t *private_key, const uint32_t *pRx, const uint32_t *pRy);
+
+/**
+ * @brief
+ *
+ * @param [in] data
+ * @param [in] max_ref
+ * @param [in] size
+ * @return int
+ */
+int bflb_sec_ecc_get_random_value(uint32_t *data, uint32_t *max_ref, uint32_t size);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_irq.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_irq.h
new file mode 100755
index 0000000000..52cdabc714
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_irq.h
@@ -0,0 +1,53 @@
+#ifndef _BFLB_SEC_IRQ_H
+#define _BFLB_SEC_IRQ_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup SEC_IRQ
+  * @{
+  */
+
+#define BFLB_SEC_ENG_IRQ_TYPE_AES  0
+#define BFLB_SEC_ENG_IRQ_TYPE_SHA  1
+#define BFLB_SEC_ENG_IRQ_TYPE_PKA  2
+#define BFLB_SEC_ENG_IRQ_TYPE_TRNG 3
+#define BFLB_SEC_ENG_IRQ_TYPE_GMAC 4
+#define BFLB_SEC_ENG_IRQ_TYPE_CDET 5
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] sec_type
+ * @param [in] callback
+ * @param [in] arg
+ */
+void bflb_sec_irq_attach(uint8_t sec_type, void (*callback)(void *arg), void *arg);
+
+/**
+ * @brief
+ *
+ * @param [in] sec_type
+ */
+void bflb_sec_irq_detach(uint8_t sec_type);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_pka.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_pka.h
new file mode 100755
index 0000000000..26f4681f35
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_pka.h
@@ -0,0 +1,285 @@
+#ifndef _BFLB_SEC_PKA_H
+#define _BFLB_SEC_PKA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup SEC_PKA
+  * @{
+  */
+
+#define SEC_ENG_PKA_REG_SIZE_8   1
+#define SEC_ENG_PKA_REG_SIZE_16  2
+#define SEC_ENG_PKA_REG_SIZE_32  3
+#define SEC_ENG_PKA_REG_SIZE_64  4
+#define SEC_ENG_PKA_REG_SIZE_96  5
+#define SEC_ENG_PKA_REG_SIZE_128 6
+#define SEC_ENG_PKA_REG_SIZE_192 7
+#define SEC_ENG_PKA_REG_SIZE_256 8
+#define SEC_ENG_PKA_REG_SIZE_384 9
+#define SEC_ENG_PKA_REG_SIZE_512 10
+
+#define SEC_ENG_PKA_OP_PPSEL         0x00
+#define SEC_ENG_PKA_OP_LMOD2N        0x11
+#define SEC_ENG_PKA_OP_LDIV2N        0x12
+#define SEC_ENG_PKA_OP_LMUL2N        0x13
+#define SEC_ENG_PKA_OP_LDIV          0x14
+#define SEC_ENG_PKA_OP_LSQR          0x15
+#define SEC_ENG_PKA_OP_LMUL          0x16
+#define SEC_ENG_PKA_OP_LSUB          0x17
+#define SEC_ENG_PKA_OP_LADD          0x18
+#define SEC_ENG_PKA_OP_LCMP          0x19
+#define SEC_ENG_PKA_OP_MDIV2         0x21
+#define SEC_ENG_PKA_OP_MINV          0x22
+#define SEC_ENG_PKA_OP_MEXP          0x23
+#define SEC_ENG_PKA_OP_MSQR          0x24
+#define SEC_ENG_PKA_OP_MMUL          0x25
+#define SEC_ENG_PKA_OP_MREM          0x26
+#define SEC_ENG_PKA_OP_MSUB          0x27
+#define SEC_ENG_PKA_OP_MADD          0x28
+#define SEC_ENG_PKA_OP_RESIZE        0x31
+#define SEC_ENG_PKA_OP_MOVDAT        0x32
+#define SEC_ENG_PKA_OP_NLIR          0x33
+#define SEC_ENG_PKA_OP_SLIR          0x34
+#define SEC_ENG_PKA_OP_CLIR          0x35
+#define SEC_ENG_PKA_OP_CFLIRI_BUFFER 0x36
+#define SEC_ENG_PKA_OP_CTLIRI_PLD    0x37
+#define SEC_ENG_PKA_OP_CFLIR_BUFFER  0x38
+#define SEC_ENG_PKA_OP_CTLIR_PLD     0x39
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void bflb_pka_init(struct bflb_device_s *dev);
+void bflb_pka_deinit(struct bflb_device_s *dev);
+
+void bflb_pka_lmod2n(struct bflb_device_s *dev,
+                     uint8_t s0_regindex,
+                     uint8_t s0_regsize,
+                     uint8_t d0_regindex,
+                     uint8_t d0_regsize,
+                     uint16_t bit_shift,
+                     uint8_t lastop);
+
+void bflb_pka_ldiv2n(struct bflb_device_s *dev,
+                     uint8_t s0_regindex,
+                     uint8_t s0_regsize,
+                     uint8_t d0_regindex,
+                     uint8_t d0_regsize,
+                     uint16_t bit_shift,
+                     uint8_t lastop);
+
+void bflb_pka_lmul2n(struct bflb_device_s *dev,
+                     uint8_t s0_regindex,
+                     uint8_t s0_regsize,
+                     uint8_t d0_regindex,
+                     uint8_t d0_regsize,
+                     uint16_t bit_shift,
+                     uint8_t lastop);
+
+void bflb_pka_ldiv(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_lsqr(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_lmul(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s1_regindex,
+                   uint8_t s1_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_lsub(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s1_regindex,
+                   uint8_t s1_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_ladd(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s1_regindex,
+                   uint8_t s1_regsize,
+                   uint8_t lastop);
+
+uint8_t bflb_pka_lcmp(struct bflb_device_s *dev,
+                      uint8_t s0_regindex,
+                      uint8_t s0_regsize,
+                      uint8_t s1_regindex,
+                      uint8_t s1_regsize);
+
+void bflb_pka_minv(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_mexp(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s1_regindex,
+                   uint8_t s1_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_msqr(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_mmul(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s1_regindex,
+                   uint8_t s1_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_mrem(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_msub(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s1_regindex,
+                   uint8_t s1_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_madd(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t s1_regindex,
+                   uint8_t s1_regsize,
+                   uint8_t s2_regindex,
+                   uint8_t s2_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_regsize(struct bflb_device_s *dev,
+                      uint8_t s0_regindex,
+                      uint8_t s0_regsize,
+                      uint8_t d0_regindex,
+                      uint8_t d0_regsize,
+                      uint8_t lastop);
+
+void bflb_pka_movdat(struct bflb_device_s *dev,
+                     uint8_t s0_regindex,
+                     uint8_t s0_regsize,
+                     uint8_t d0_regindex,
+                     uint8_t d0_regsize,
+                     uint8_t lastop);
+
+void bflb_pka_nlir(struct bflb_device_s *dev,
+                   uint8_t s0_regindex,
+                   uint8_t s0_regsize,
+                   uint8_t d0_regindex,
+                   uint8_t d0_regsize,
+                   uint8_t lastop);
+
+void bflb_pka_slir(struct bflb_device_s *dev,
+                   uint8_t regindex,
+                   uint8_t regsize,
+                   uint32_t data,
+                   uint8_t lastop);
+
+void bflb_pka_clir(struct bflb_device_s *dev,
+                   uint8_t regindex,
+                   uint8_t regsize,
+                   uint16_t size,
+                   uint8_t lastop);
+
+void bflb_pka_write(struct bflb_device_s *dev,
+                    uint8_t regindex,
+                    uint8_t regsize,
+                    const uint32_t *data,
+                    uint16_t size,
+                    uint8_t lastop);
+
+void bflb_pka_read(struct bflb_device_s *dev,
+                   uint8_t regindex,
+                   uint8_t regsize,
+                   uint32_t *data,
+                   uint16_t size);
+
+void bflb_pka_gf2mont(struct bflb_device_s *dev,
+                      uint8_t s_regindex,
+                      uint8_t s_regsize,
+                      uint8_t d_regindex,
+                      uint8_t d_regsize,
+                      uint8_t t_regindex,
+                      uint8_t t_regsize,
+                      uint8_t p_regindex,
+                      uint8_t p_regsize,
+                      uint32_t size);
+
+void bflb_pka_mont2gf(struct bflb_device_s *dev,
+                      uint8_t s_regindex,
+                      uint8_t s_regsize,
+                      uint8_t d_regindex,
+                      uint8_t d_regsize,
+                      uint8_t invt_regindex,
+                      uint8_t invt_regsize,
+                      uint8_t t_regindex,
+                      uint8_t t_regsize,
+                      uint8_t p_regindex,
+                      uint8_t p_regsize);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_sha.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_sha.h
new file mode 100755
index 0000000000..3053de586a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_sha.h
@@ -0,0 +1,318 @@
+#ifndef _BFLB_SEC_SHA_H
+#define _BFLB_SEC_SHA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup SEC_SHA
+  * @{
+  */
+
+#define SHA_MODE_SHA256     0
+#define SHA_MODE_SHA224     1
+#define SHA_MODE_SHA1       2
+#define SHA_MODE_SHA512     4
+#define SHA_MODE_SHA384     5
+#define SHA_MODE_SHA512T224 6
+#define SHA_MODE_SHA512T256 7
+
+struct bflb_sha1_ctx_s {
+    uint32_t total[2];                                    /*!< Number of bytes processed */
+    __attribute__((aligned(32))) uint8_t sha_buf[64];     /*!< Data not processed but in this temp buffer */
+    __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+    uint8_t sha_feed;                                     /*!< Sha has feed data */
+};
+
+struct bflb_sha256_ctx_s {
+    uint32_t total[2];                                    /*!< Number of bytes processed */
+    __attribute__((aligned(32))) uint8_t sha_buf[64];     /*!< Data not processed but in this temp buffer */
+    __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+    uint8_t sha_feed;                                     /*!< Sha has feed data */
+};
+
+struct bflb_sha512_ctx_s {
+    uint64_t total[2];                                     /*!< Number of bytes processed */
+    __attribute__((aligned(32))) uint8_t sha_buf[128];     /*!< Data not processed but in this temp buffer */
+    __attribute__((aligned(32))) uint8_t sha_padding[128]; /*!< Padding data */
+    uint8_t sha_feed;                                      /*!< Sha has feed data */
+};
+
+struct bflb_sha1_link_ctx_s {
+    uint32_t total[2];                                    /*!< Number of bytes processed */
+    __attribute__((aligned(32))) uint8_t sha_buf[64];     /*!< Data not processed but in this temp buffer */
+    __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+    uint32_t link_addr;                                   /*!< Link configure address */
+};
+
+struct bflb_sha256_link_ctx_s {
+    uint32_t total[2];                                    /*!< Number of bytes processed */
+    __attribute__((aligned(32))) uint8_t sha_buf[64];     /*!< Data not processed but in this temp buffer */
+    __attribute__((aligned(32))) uint8_t sha_padding[64]; /*!< Padding data */
+    uint32_t link_addr;                                   /*!< Link configure address */
+};
+
+struct bflb_sha512_link_ctx_s {
+    uint64_t total[2];                                     /*!< Number of bytes processed */
+    __attribute__((aligned(32))) uint8_t sha_buf[128];     /*!< Data not processed but in this temp buffer */
+    __attribute__((aligned(32))) uint8_t sha_padding[128]; /*!< Padding data */
+    uint32_t link_addr;                                    /*!< Link configure address */
+};
+
+struct bflb_sha_link_s {
+    uint32_t                 : 2;  /*!< [1:0]Reserved */
+    uint32_t sha_mode        : 3;  /*!< [4:2]Sha-256/sha-224/sha-1/sha-1/sha-512/sha-384/sha-512T224/sha-512T256 */
+    uint32_t                 : 1;  /*!< [5]Reserved */
+    uint32_t sha_newhash_dis : 1;  /*!< [6]New hash or accumulate last hash */
+    uint32_t                 : 2;  /*!< [8:7]Reserved */
+    uint32_t sha_intclr      : 1;  /*!< [9]Clear interrupt */
+    uint32_t sha_intset      : 1;  /*!< [10]Set interrupt */
+    uint32_t                 : 1;  /*!< [11]Reserved */
+    uint32_t sha_mode_ext    : 2;  /*!< [13:12]Extention,0:sha 1:md5 2:crc16 3:crc32 */
+    uint32_t                 : 2;  /*!< [15:14]Reserved */
+    uint32_t sha_msglen      : 16; /*!< [31:16]Number of 512-bit block */
+    uint32_t sha_srcaddr;          /*!< Message source address */
+    uint32_t result[16];           /*!< Result of SHA */
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mode
+ */
+void bflb_sha_init(struct bflb_device_s *dev, uint8_t mode);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ */
+void bflb_sha1_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ */
+void bflb_sha256_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ */
+void bflb_sha512_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, const uint8_t *input, uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, const uint8_t *input, uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint64_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_sha_link_init(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_sha_link_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] link
+ */
+void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_link_ctx_s *ctx, struct bflb_sha_link_s *link);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] link
+ */
+void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_link_ctx_s *ctx, struct bflb_sha_link_s *link);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] link
+ */
+void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_link_ctx_s *ctx, struct bflb_sha_link_s *link);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha1_link_update(struct bflb_device_s *dev,
+                          struct bflb_sha1_link_ctx_s *ctx,
+                          const uint8_t *input,
+                          uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha256_link_update(struct bflb_device_s *dev,
+                            struct bflb_sha256_link_ctx_s *ctx,
+                            const uint8_t *input,
+                            uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] input
+ * @param [in] len
+ * @return int
+ */
+int bflb_sha512_link_update(struct bflb_device_s *dev,
+                            struct bflb_sha512_link_ctx_s *ctx,
+                            const uint8_t *input,
+                            uint64_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha1_link_finish(struct bflb_device_s *dev,
+                           struct bflb_sha1_link_ctx_s *ctx,
+                           uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha256_link_finish(struct bflb_device_s *dev,
+                             struct bflb_sha256_link_ctx_s *ctx,
+                             uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] ctx
+ * @param [in] output
+ */
+void bflb_sha512_link_finish(struct bflb_device_s *dev,
+                             struct bflb_sha512_link_ctx_s *ctx,
+                             uint8_t *output);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_group0_request_sha_access(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_group0_release_sha_access(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_trng.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_trng.h
new file mode 100755
index 0000000000..a710703018
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sec_trng.h
@@ -0,0 +1,69 @@
+#ifndef _BFLB_SEC_TRNG_H
+#define _BFLB_SEC_TRNG_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup TRNG
+  * @{
+  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Read trng data.
+ *
+ * @param [in] dev device handle
+ * @param [in] data pointer to trng data
+ * @return A negated errno value on failure.
+ */
+int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32]);
+
+/**
+ * @brief Read trng data with custom length.
+ *
+ * @param [in] data pointer to trng data
+ * @param [in] len length to read
+ * @return A negated errno value on failure.
+ */
+int bflb_trng_readlen(uint8_t *data, uint32_t len);
+
+/**
+ * @brief Get trng data.
+ *
+ * @return trng data with word
+ */
+long random(void);
+
+/**
+ * @brief Enable trng in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_request_trng_access(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable trng in group0.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_group0_release_trng_access(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h
new file mode 100755
index 0000000000..237fbd6f9a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi.h
@@ -0,0 +1,273 @@
+#ifndef _BFLB_SPI_H
+#define _BFLB_SPI_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */
+
+#if defined(BL602) || defined(BL702)
+#define SPI_FIFO_WORD_NUM_MAX           4
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 0
+#elif defined(BL606P) || defined(BL808)
+#define SPI_FIFO_BYTE_NUM_MAX           32
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 1
+#elif defined(BL616) || defined(BL628)
+#define SPI_FIFO_BYTE_NUM_MAX           32
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 1
+#elif defined(BL702L)
+#define SPI_FIFO_BYTE_NUM_MAX           16
+#define SPI_FIFO_WIDTH_VARIABLE_SUPPORT 1
+#else
+#error "unknown device"
+#endif
+
+/** @defgroup SPI_ROLE spi role definition
+  * @{
+  */
+#define SPI_ROLE_MASTER      0
+#define SPI_ROLE_SLAVE       1
+/**
+  * @}
+  */
+
+/** @defgroup SPI_MODE spi mode definition
+  * @{
+  */
+#define SPI_MODE0            0 /* CPOL=0 CHPHA=0 */
+#define SPI_MODE1            1 /* CPOL=0 CHPHA=1 */
+#define SPI_MODE2            2 /* CPOL=1 CHPHA=0 */
+#define SPI_MODE3            3 /* CPOL=1 CHPHA=1 */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_DATA_WIDTH spi data width definition
+  * @{
+  */
+#define SPI_DATA_WIDTH_8BIT  1
+#define SPI_DATA_WIDTH_16BIT 2
+#define SPI_DATA_WIDTH_24BIT 3
+#define SPI_DATA_WIDTH_32BIT 4
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BIT_ORDER spi bit order definition
+  * @{
+  */
+#define SPI_BIT_LSB          1
+#define SPI_BIT_MSB          0
+/**
+  * @}
+  */
+
+/** @defgroup SPI_BYTE_ORDER spi byte order definition
+  * @{
+  */
+#define SPI_BYTE_LSB         0
+#if !defined(BL602) && !defined(BL702)
+#define SPI_BYTE_MSB 1
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup SPI_INTSTS spi interrupt status definition
+  * @{
+  */
+#define SPI_INTSTS_TC                (1 << 0)
+#define SPI_INTSTS_TX_FIFO           (1 << 1)
+#define SPI_INTSTS_RX_FIFO           (1 << 2)
+#define SPI_INTSTS_SLAVE_TIMEOUT     (1 << 3)
+#define SPI_INTSTS_SLAVE_TX_UNDERRUN (1 << 4)
+#define SPI_INTSTS_FIFO_ERR          (1 << 5)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_INTCLR spi interrupt clear definition
+  * @{
+  */
+#define SPI_INTCLR_TC                (1 << 16)
+#define SPI_INTCLR_SLAVE_TIMEOUT     (1 << 19)
+#define SPI_INTCLR_SLAVE_TX_UNDERRUN (1 << 20)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CMD spi feature control cmd definition
+  * @{
+  */
+#define SPI_CMD_SET_DATA_WIDTH       (0x01)
+#define SPI_CMD_GET_DATA_WIDTH       (0x02)
+#define SPI_CMD_CLEAR_TX_FIFO        (0x03)
+#define SPI_CMD_CLEAR_RX_FIFO        (0x04)
+#define SPI_CMD_SET_CS_INTERVAL      (0x05)
+#define SPI_CMD_RX_IGNORE            (0x06)
+/**
+  * @}
+  */
+
+/**
+ * @brief SPI configuration structure
+ *
+ * @param freq                SPI frequence, should be less than spi_clk/2
+ * @param role                SPI role, use @ref SPI_ROLE
+ * @param mode                SPI mode, use @ref SPI_MODE
+ * @param data_width          SPI data width, use @ref SPI_DATA_WIDTH
+ * @param bit_order           SPI bit order, use @ref SPI_BIT_ORDER
+ * @param byte_order          SPI byte order, use @ref SPI_BYTE_ORDER
+ * @param tx_fifo_threshold   SPI tx fifo threshold, should be less than 4
+ * @param rx_fifo_threshold   SPI rx fifo threshold, should be less than 4
+ */
+struct bflb_spi_config_s {
+    uint32_t freq;
+    uint8_t role;
+    uint8_t mode;
+    uint8_t data_width;
+    uint8_t bit_order;
+    uint8_t byte_order;
+    uint8_t tx_fifo_threshold;
+    uint8_t rx_fifo_threshold;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize spi.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save spi config
+ */
+void bflb_spi_init(struct bflb_device_s *dev, const struct bflb_spi_config_s *config);
+
+/**
+ * @brief Deinitialize spi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_spi_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable spi tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_spi_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable spi rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_spi_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Send and receive one data on spi.
+ *
+ * @param [in] dev device handle
+ * @param [in] data data to send
+ * @return receive data
+ */
+uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t data);
+
+/**
+ * @brief Send and receive a block of data on spi.
+ *
+ * @param [in] dev device handle
+ * @param [in] txbuffer pointer to send buffer
+ * @param [in] rxbuffer pointer to receive buffer
+ * @param [in] nbytes bytes to send
+ * @return A negated errno value on failure.
+ */
+int bflb_spi_poll_exchange(struct bflb_device_s *dev, const void *txbuffer, void *rxbuffer, size_t nbytes);
+
+/**
+ * @brief Check if spi is busy.
+ *
+ * @param [in] dev device handle
+ * @return true means busy, otherwise not.
+ */
+bool bflb_spi_isbusy(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable spi rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable spi rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable spi transfer done interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable spi error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get spi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref SPI_INTSTS
+ */
+uint32_t bflb_spi_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear spi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref SPI_INTCLR
+ */
+void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Control spi feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref SPI_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi_psram.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi_psram.h
new file mode 100755
index 0000000000..33969d8459
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_spi_psram.h
@@ -0,0 +1,152 @@
+/**
+  ******************************************************************************
+  * @file    bflb_spi_psram.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BFLB_SPI_PSRAM_H__
+#define __BFLB_SPI_PSRAM_H__
+
+#include "sf_ctrl_reg.h"
+#include "bflb_common.h"
+#include "bflb_sf_ctrl.h"
+
+/** @addtogroup  BFLB_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PSRAM
+ *  @{
+ */
+
+/** @defgroup  PSRAM_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Psram drive strength type definition
+ */
+
+#define PSRAM_DRIVE_STRENGTH_50_OHMS      0  /*!< Drive strength 50 ohms(default) */
+#define PSRAM_DRIVE_STRENGTH_100_OHMS     1  /*!< Drive strength 100 ohms */
+#define PSRAM_DRIVE_STRENGTH_200_OHMS     2  /*!< Drive strength 200 ohms */
+
+/**
+ *  @brief Psram burst length size type definition
+ */
+#define PSRAM_BURST_LENGTH_16_BYTES       0  /*!< Burst Length 16 bytes */
+#define PSRAM_BURST_LENGTH_32_BYTES       1  /*!< Burst Length 32 bytes */
+#define PSRAM_BURST_LENGTH_64_BYTES       2  /*!< Burst Length 64 bytes */
+#define PSRAM_BURST_LENGTH_512_BYTES      3 /*!< Burst Length 512 bytes(default) */
+
+/**
+ *  @brief Psram ctrl mode type definition
+ */
+#define PSRAM_SPI_CTRL_MODE               0  /*!< Psram SPI ctrl mode */
+#define PSRAM_QPI_CTRL_MODE               1  /*!< Psram QPI ctrl mode */
+
+/**
+ *  @brief Psram ctrl configuration structure type definition
+ */
+struct spi_psram_cfg_type {
+    uint8_t read_id_cmd;                  /*!< Read ID command */
+    uint8_t read_id_dmy_clk;              /*!< Read ID command dummy clock */
+    uint8_t burst_toggle_cmd;             /*!< Burst toggle length command */
+    uint8_t reset_enable_cmd;             /*!< Psram reset enable command */
+    uint8_t reset_cmd;                    /*!< Psram reset command */
+    uint8_t enter_quad_mode_cmd;          /*!< Psram enter quad mode command */
+    uint8_t exit_quad_mode_cmd;           /*!< Psram exit quad mode command */
+    uint8_t read_reg_cmd;                 /*!< Read register command */
+    uint8_t read_reg_dmy_clk;             /*!< Read register command dummy clock */
+    uint8_t write_reg_cmd;                /*!< Write register command */
+    uint8_t read_cmd;                     /*!< Psram read command */
+    uint8_t read_dmy_clk;                 /*!< Psram read command dummy clock */
+    uint8_t f_read_cmd;                   /*!< Psram fast read command */
+    uint8_t f_read_dmy_clk;               /*!< Psram fast read command dummy clock */
+    uint8_t f_read_quad_cmd;              /*!< Psram fast read quad command */
+    uint8_t f_read_quad_dmy_clk;          /*!< Psram fast read quad command dummy clock */
+    uint8_t write_cmd;                    /*!< Psram write command */
+    uint8_t quad_write_cmd;               /*!< Psram quad write command */
+    uint16_t page_size;                   /*!< Psram page size */
+#if defined(BL702L)
+    uint8_t burst_toggle_en;              /*!< Psram burst toggle mode enable */
+#endif
+    uint8_t ctrl_mode;                    /*!< Psram ctrl mode */
+    uint8_t drive_strength;               /*!< Psram drive strength */
+    uint8_t burst_length;                 /*!< Psram burst length size */
+};
+
+/*@} end of group PSRAM_Public_Types */
+
+/** @defgroup  PSRAM_Public_Constants
+ *  @{
+ */
+
+/*@} end of group PSRAM_Public_Constants */
+
+/** @defgroup  PSRAM_Public_Macros
+ *  @{
+ */
+
+/*@} end of group PSRAM_Public_Macros */
+
+/** @defgroup  PSRAM_Public_Functions
+ *  @{
+ */
+
+/**
+ *  @brief PSRAM Functions
+ */
+void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg,
+                     struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg);
+void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
+void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value);
+int bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg);
+int bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg);
+void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data);
+int bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg);
+int bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg);
+int bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
+int bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode);
+int bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint32_t len);
+int bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint8_t wt_en,
+                               uint8_t wb_en, uint8_t wa_en);
+int bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
+int bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
+
+/*@} end of group PSRAM_Public_Functions */
+
+/*@} end of group PSRAM */
+
+/*@} end of group BFLB_Peripheral_Driver */
+
+#endif /* __BFLB_SPI_PSRAM_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_timer.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_timer.h
new file mode 100755
index 0000000000..43a09d2e4e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_timer.h
@@ -0,0 +1,204 @@
+#ifndef _BFLB_TIMER_H
+#define _BFLB_TIMER_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup TIMER
+  * @{
+  */
+
+/** @defgroup TIMER_CLK_SOURCE timer clock source definition
+  * @{
+  */
+#if !defined(BL702L)
+#define TIMER_CLKSRC_BCLK 0
+#endif
+#define TIMER_CLKSRC_32K  1
+#define TIMER_CLKSRC_1K   2
+#define TIMER_CLKSRC_XTAL 3
+#if !defined(BL702) && !defined(BL602)
+#define TIMER_CLKSRC_GPIO 4
+#endif
+#define TIMER_CLKSRC_NO   5
+/**
+  * @}
+  */
+
+/** @defgroup TIMER_COUNTER_MODE timer counter mode definition
+  * @{
+  */
+#define TIMER_COUNTER_MODE_PROLOAD 0
+#define TIMER_COUNTER_MODE_UP      1
+/**
+  * @}
+  */
+
+/** @defgroup TIMER_COMP_ID timer compare id definition
+  * @{
+  */
+#define TIMER_COMP_ID_0 0
+#define TIMER_COMP_ID_1 1
+#define TIMER_COMP_ID_2 2
+#define TIMER_COMP_NONE 3
+/**
+  * @}
+  */
+
+/** @defgroup TIMER_CAPTURE_POLARITY timer capture polarity definition
+  * @{
+  */
+#define TIMER_CAPTURE_POLARITY_POSITIVE 0
+#define TIMER_CAPTURE_POLARITY_NEGATIVE 1
+/**
+  * @}
+  */
+
+/**
+ * @brief TIMER configuration structure
+ *
+ * @param counter_mode      Timer counter mode, use @ref TIMER_COUNTER_MODE
+ * @param clock_source      Timer clock source, use @ref TIMER_CLK_SOURCE
+ * @param clock_div         Timer clock divison value, from 0 to 255
+ * @param trigger_comp_id   Timer count register preload trigger source slelect, use @ref TIMER_COMP_ID
+ * @param comp0_val         Timer compare 0 value
+ * @param comp1_val         Timer compare 1 value
+ * @param comp2_val         Timer compare 2 value
+ * @param preload_val       Timer preload value
+ */
+struct bflb_timer_config_s {
+    uint8_t counter_mode;
+    uint8_t clock_source;
+    uint8_t clock_div;
+    uint8_t trigger_comp_id;
+    uint32_t comp0_val;
+    uint32_t comp1_val;
+    uint32_t comp2_val;
+    uint32_t preload_val;
+};
+
+/**
+ * @brief TIMER capture configuration structure
+ *
+ * @param pin      Timer capture pin
+ * @param polarity Timer capture polarity, use @ref TIMER_CAPTURE_POLARITY
+ */
+struct bflb_timer_capture_config_s {
+    uint8_t pin;
+    uint8_t polarity;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize timer.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save timer config
+ */
+void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s *config);
+
+/**
+ * @brief Deinitialize timer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_timer_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Start timer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_timer_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop timer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_timer_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Set timer preload value.
+ *
+ * @param [in] dev device handle
+ * @param [in] val preload value
+ */
+void bflb_timer_set_preloadvalue(struct bflb_device_s *dev, uint32_t val);
+
+/**
+ * @brief Set compare value of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @param [in] val compare value
+ */
+void bflb_timer_set_compvalue(struct bflb_device_s *dev, uint8_t cmp_no, uint32_t val);
+
+/**
+ * @brief Get compare value of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @return uint32_t
+ */
+uint32_t bflb_timer_get_compvalue(struct bflb_device_s *dev, uint8_t cmp_no);
+
+/**
+ * @brief Get timer counter value.
+ *
+ * @param [in] dev device handle
+ * @return counter value
+ */
+uint32_t bflb_timer_get_countervalue(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable timer interrupt of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_timer_compint_mask(struct bflb_device_s *dev, uint8_t cmp_no, bool mask);
+
+/**
+ * @brief Get timer interrupt status of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ * @return true mean yes, otherwise no.
+ */
+bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no);
+
+/**
+ * @brief Clear timer interrupt status of corresponding compare id.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmp_no compare id, use @ref TIMER_COMP_ID
+ */
+void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no);
+
+#if !defined(BL702) || !defined(BL602)
+void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config);
+uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev);
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h
new file mode 100755
index 0000000000..555ef6ecfa
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_uart.h
@@ -0,0 +1,368 @@
+#ifndef _BFLB_UART_H
+#define _BFLB_UART_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup UART
+  * @{
+  */
+
+/** @defgroup UART_DIRECTION uart direction enable definition
+  * @{
+  */
+#define UART_DIRECTION_TX   (1 << 0)
+#define UART_DIRECTION_RX   (1 << 1)
+#define UART_DIRECTION_TXRX (UART_DIRECTION_TX | UART_DIRECTION_RX)
+#define UART_DIRECTION_MASK UART_DIRECTION_TXRX
+/**
+  * @}
+  */
+
+/** @defgroup UART_DATABITS uart data bits definition
+  * @{
+  */
+#define UART_DATA_BITS_5 0
+#define UART_DATA_BITS_6 1
+#define UART_DATA_BITS_7 2
+#define UART_DATA_BITS_8 3
+/**
+  * @}
+  */
+
+/** @defgroup UART_STOPBITS uart stop bits definition
+  * @{
+  */
+#define UART_STOP_BITS_0_5 0
+#define UART_STOP_BITS_1   1
+#define UART_STOP_BITS_1_5 2
+#define UART_STOP_BITS_2   3
+/**
+  * @}
+  */
+
+/** @defgroup UART_PARITY uart parity definition
+  * @{
+  */
+#define UART_PARITY_NONE  0
+#define UART_PARITY_ODD   1
+#define UART_PARITY_EVEN  2
+#define UART_PARITY_MARK  3
+#define UART_PARITY_SPACE 4
+/**
+  * @}
+  */
+
+/** @defgroup UART_BITORDER uart bitorder definition
+  * @{
+  */
+#define UART_LSB_FIRST 0
+#define UART_MSB_FIRST 1
+/**
+  * @}
+  */
+
+/** @defgroup UART_FLOWCTRL uart flow ctrl definition
+  * @{
+  */
+#define UART_FLOWCTRL_NONE    0
+#define UART_FLOWCTRL_RTS     (1 << 0)
+#define UART_FLOWCTRL_CTS     (1 << 1)
+#define UART_FLOWCTRL_RTS_CTS (UART_FLOWCTRL_RTS | UART_FLOWCTRL_CTS)
+/**
+  * @}
+  */
+
+/** @defgroup UART_INTSTS uart interrupt status definition
+  * @{
+  */
+#define UART_INTSTS_TX_END  (1 << 0)
+#define UART_INTSTS_RX_END  (1 << 1)
+#define UART_INTSTS_TX_FIFO (1 << 2)
+#define UART_INTSTS_RX_FIFO (1 << 3)
+#define UART_INTSTS_RTO     (1 << 4)
+#define UART_INTSTS_PCE     (1 << 5)
+#define UART_INTSTS_TX_FER  (1 << 6)
+#define UART_INTSTS_RX_FER  (1 << 7)
+#if !defined(BL602)
+#define UART_INTSTS_RX_LSE (1 << 8)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_INTSTS_RX_BCR (1 << 9)
+#define UART_INTSTS_RX_ADS (1 << 10)
+#define UART_INTSTS_RX_AD5 (1 << 11)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup UART_INTCLR uart interrupt clear definition
+  * @{
+  */
+#define UART_INTCLR_TX_END (1 << 0)
+#define UART_INTCLR_RX_END (1 << 1)
+#define UART_INTCLR_RTO    (1 << 4)
+#define UART_INTCLR_PCE    (1 << 5)
+#if !defined(BL602)
+#define UART_INTCLR_RX_LSE (1 << 8)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_INTCLR_RX_BCR (1 << 9)
+#define UART_INTCLR_RX_ADS (1 << 10)
+#define UART_INTCLR_RX_AD5 (1 << 11)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup UART_CMD uart feature control cmd definition
+  * @{
+  */
+#define UART_CMD_SET_BAUD_RATE           (0x01)
+#define UART_CMD_SET_DATA_BITS           (0x02)
+#define UART_CMD_SET_STOP_BITS           (0x03)
+#define UART_CMD_SET_PARITY_BITS         (0x04)
+#define UART_CMD_CLR_TX_FIFO             (0x05)
+#define UART_CMD_CLR_RX_FIFO             (0x06)
+#define UART_CMD_SET_RTO_VALUE           (0x07)
+#define UART_CMD_SET_RTS_VALUE           (0x08)
+#define UART_CMD_GET_TX_FIFO_CNT         (0x09)
+#define UART_CMD_GET_RX_FIFO_CNT         (0x0a)
+#define UART_CMD_SET_AUTO_BAUD           (0x0b)
+#define UART_CMD_GET_AUTO_BAUD           (0x0c)
+#define UART_CMD_SET_BREAK_VALUE         (0x0d)
+#define UART_CMD_SET_TX_LIN_VALUE        (0x0e)
+#define UART_CMD_SET_RX_LIN_VALUE        (0x0f)
+#define UART_CMD_SET_TX_RX_EN            (0x10)
+#define UART_CMD_SET_TX_RS485_EN         (0x11)
+#define UART_CMD_SET_TX_RS485_POLARITY   (0x12)
+#define UART_CMD_SET_ABR_ALLOWABLE_ERROR (0x13)
+#define UART_CMD_SET_SW_RTS_CONTROL      (0x14)
+#define UART_CMD_IR_CONFIG               (0x15)
+#define UART_CMD_SET_TX_FREERUN          (0x16)
+#define UART_CMD_SET_TX_END_INTERRUPT    (0x17)
+#define UART_CMD_SET_RX_END_INTERRUPT    (0x18)
+#define UART_CMD_SET_TX_TRANSFER_LEN     (0x19)
+#define UART_CMD_SET_RX_TRANSFER_LEN     (0x20)
+#define UART_CMD_SET_TX_EN               (0x21)
+#define UART_CMD_SET_BCR_END_INTERRUPT   (0x22)
+#define UART_CMD_GET_BCR_COUNT           (0x23)
+/**
+  * @}
+  */
+
+#define UART_AUTO_BAUD_START 0
+#define UART_AUTO_BAUD_0X55  1
+
+struct bflb_uart_ir_config_s {
+    bool tx_en;
+    bool rx_en;
+    bool tx_inverse;
+    bool rx_inverse;
+    uint16_t tx_pluse_start;
+    uint16_t tx_pluse_stop;
+    uint16_t rx_pluse_start;
+};
+
+/**
+ * @brief UART configuration structure
+ *
+ * @param baudrate          UART baudrate setting in bps,should be less than uart_clk/2
+ * @param direction         UART direction, use @ref UART_DIRECTION
+ * @param data_bits         UART data bits, use @ref UART_DATABITS
+ * @param stop_bits         UART stop bits, use @ref UART_STOPBITS
+ * @param parity            UART parity bit, use @ref UART_PARITY
+ * @param bit_order         UART bit first, use @ref UART_BITORDER
+ * @param flow_ctrl         UART flow control setting, use @ref UART_FLOWCTRL
+ * @param tx_fifo_threshold UART tx fifo threshold, should be less than 32.
+ * @param rx_fifo_threshold UART rx fifo threshold, should be less than 32.
+ */
+struct bflb_uart_config_s {
+    uint32_t baudrate;
+    uint8_t direction;
+    uint8_t data_bits;
+    uint8_t stop_bits;
+    uint8_t parity;
+    uint8_t bit_order;
+    uint8_t flow_ctrl;
+    uint8_t tx_fifo_threshold;
+    uint8_t rx_fifo_threshold;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize uart.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save uart config
+ */
+void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *config);
+
+/**
+ * @brief Deinitialize uart.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_uart_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable uart.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_uart_enable(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable uart.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_uart_disable(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable uart tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable uart rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Put one char on uart.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch char
+ * @return A negated errno value on failure.
+ */
+int bflb_uart_putchar(struct bflb_device_s *dev, int ch);
+
+/**
+ * @brief Get char from uart.
+ *
+ * @param [in] dev device handle
+ * @return A negated errno value on failure, otherwise received char.
+ */
+int bflb_uart_getchar(struct bflb_device_s *dev);
+
+/**
+ * @brief Put a block of data on uart.This is a poll api.
+ *
+ * @param [in] dev device handle
+ * @param [in] data pointer to save send data
+ * @param [in] len length to send
+ * @return A negated errno value on failure.
+ */
+int bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Get a block of data from uart. This is a asynchronous api.
+ *
+ * @param [in] dev device handle
+ * @param [in] data pointer to save received data
+ * @param [in] len max length wants to receive
+ * @return actual received length
+ */
+int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Check if there is free space in tx fifo.
+ *
+ * @param [in] dev device handle
+ * @return Return true if the tranmsit hardware is ready to send another byte
+ */
+bool bflb_uart_txready(struct bflb_device_s *dev);
+
+/**
+ * @brief Check if there is no data in tx fifo.
+ *
+ * @param [in] dev device handle
+ * @return Return true if all characters have been sent
+ */
+bool bflb_uart_txempty(struct bflb_device_s *dev);
+
+/**
+ * @brief Check if there is data in rx fifo.
+ *
+ * @param [in] dev device handle
+ * @return true means yes.Otherwise there is no data in rx fifo
+ */
+bool bflb_uart_rxavailable(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable uart tx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable uart rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable uart error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get uart interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref UART_INTSTS
+ */
+uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear uart interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref UART_INTCLR
+ */
+void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+
+/**
+ * @brief Control uart feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref UART_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_wdg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_wdg.h
new file mode 100755
index 0000000000..0110d503c4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_wdg.h
@@ -0,0 +1,117 @@
+#ifndef _BFLB_WDG_H
+#define _BFLB_WDG_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup WDG
+  * @{
+  */
+
+#if !defined(BL702L)
+#define WDG_CLKSRC_BCLK 0
+#endif
+#define WDG_CLKSRC_32K  1
+#define WDG_CLKSRC_1K   2
+#define WDG_CLKSRC_XTAL 3
+#if !defined(BL702) && !defined(BL602)
+#define WDG_CLKSRC_GPIO 4
+#endif
+#define WDG_CLKSRC_NO   5
+
+/** @defgroup WDG_MODE Watch-dog reset/interrupt mode definition
+  * @{
+  */
+#define WDG_MODE_INTERRUPT 0
+#define WDG_MODE_RESET     1
+/**
+  * @}
+  */
+
+/**
+ * @brief WDG configuration structure
+ *
+ * @param clock_source      Wdg clock source, use BFLB_SYSTEM_* definition
+ * @param clock_div         Wdg clock divison value, from 0 to 255
+ * @param comp_val          Wdg compare value
+ * @param mode              Wdg reset/interrupt mode
+ */
+struct bflb_wdg_config_s {
+    uint8_t clock_source;
+    uint8_t clock_div;
+    uint16_t comp_val;
+    uint8_t mode;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize watchdog.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save watchdog config
+ */
+void bflb_wdg_init(struct bflb_device_s *dev, const struct bflb_wdg_config_s *config);
+
+/**
+ * @brief Start watchdog.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop watchdog.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Get watchdog counter value.
+ *
+ * @param [in] dev device handle
+ * @return counter value
+ */
+uint16_t bflb_wdg_get_countervalue(struct bflb_device_s *dev);
+
+/**
+ * @brief Set watchdog counter value.
+ *
+ * @param [in] dev device handle
+ * @param [in] counter value
+ */
+void bflb_wdg_set_countervalue(struct bflb_device_s *dev, uint16_t value);
+
+/**
+ * @brief Reset watchdog counter value.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_reset_countervalue(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear watchdog compare interrupt status.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_wdg_compint_clear(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_gcc.h
old mode 100644
new mode 100755
similarity index 52%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_gcc.h
index b1147c4089..82ff6b499b
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/misc/compiler/gcc.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_gcc.h
@@ -1,40 +1,12 @@
-#ifndef __GCC_H
-#define __GCC_H
+#ifndef __COMPILER_GCC_H
+#define __COMPILER_GCC_H
 
-#ifndef __ORDER_BIG_ENDIAN__
-#define __ORDER_BIG_ENDIAN__ (1)
-#endif
-
-#ifndef __ORDER_LITTLE_ENDIAN__
-#define __ORDER_LITTLE_ENDIAN__ (2)
-#endif
-
-#define __BYTE_ORDER__ __ORDER_LITTLE_ENDIAN__
-
-/* CPP header guards */
-#ifdef __cplusplus
-#define EXTERN_C_BEGIN extern "C" {
-#define EXTERN_C_END   }
-#else
-#define EXTERN_C_BEGIN
-#define EXTERN_C_END
-#endif
-
-#define __MACRO_BEGIN do {
-#define __MACRO_END \
-    }               \
-    while (0)
-
-#if defined(__GNUC__)
 #ifndef __ASM
 #define __ASM __asm
 #endif
 #ifndef __INLINE
 #define __INLINE inline
 #endif
-#ifndef __INLINE__
-#define __INLINE__ inline
-#endif
 #ifndef __ALWAYS_INLINE
 #define __ALWAYS_INLINE inline __attribute__((always_inline))
 #endif
@@ -50,21 +22,15 @@
 #ifndef __USED
 #define __USED __attribute__((used))
 #endif
-#ifndef __UNUSED__
-#define __UNUSED__ __attribute__((__unused__))
+#ifndef __UNUSED
+#define __UNUSED __attribute__((unused))
 #endif
 #ifndef __WEAK
 #define __WEAK __attribute__((weak))
 #endif
-#ifndef __WEAK__
-#define __WEAK__ __attribute__((weak))
-#endif
 #ifndef __PACKED
 #define __PACKED __attribute__((packed, aligned(1)))
 #endif
-#ifndef __PACKED__
-#define __PACKED__ __attribute__((packed))
-#endif
 #ifndef __PACKED_STRUCT
 #define __PACKED_STRUCT struct __attribute__((packed, aligned(1)))
 #endif
@@ -80,11 +46,11 @@
 #ifndef ALIGN4
 #define ALIGN4 __attribute((aligned(4)))
 #endif
-#ifndef PACK_START
-#define PACK_START
+#ifndef __PACK_START
+#define __PACK_START
 #endif
-#ifndef PACK_END
-#define PACK_END __attribute__((packed))
+#ifndef __PACK_END
+#define __PACK_END __attribute__((packed))
 #endif
 #ifndef likely
 #define likely(x) __builtin_expect(!!(x), 1)
@@ -92,21 +58,11 @@
 #ifndef unlikely
 #define unlikely(x) __builtin_expect(!!(x), 0)
 #endif
-#ifndef __ALIGNED__
-#define __ALIGNED__(x) __attribute__((aligned(x)))
+#ifndef __ALIGNED
+#define __ALIGNED(x) __attribute__((aligned(x)))
 #endif
 #ifndef SECTION
 #define SECTION(x) __attribute__((section(x)))
 #endif
-#ifndef __CONST__
-#define __CONST__ __attribute__((__const__))
-#endif
-#ifndef __NAKED__
-#define __NAKED__ __attribute__((naked))
-#endif
-#ifndef __deprecated
-#define __deprecated __attribute__((deprecated))
-#endif
-#endif
 
-#endif
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h
new file mode 100755
index 0000000000..0ff7dd9890
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/compiler/compiler_ld.h
@@ -0,0 +1,20 @@
+#ifndef __COMPILER_LD_H
+#define __COMPILER_LD_H
+
+#define ATTR_STRINGIFY(x)               #x
+#define ATTR_TOSTRING(x)                ATTR_STRINGIFY(x)
+#define ATTR_UNI_SYMBOL                 __FILE__ ATTR_TOSTRING(__LINE__)
+#define ATTR_CLOCK_SECTION              __attribute__((section(".sclock_rlt_code." ATTR_UNI_SYMBOL)))
+#define ATTR_CLOCK_CONST_SECTION        __attribute__((section(".sclock_rlt_const." ATTR_UNI_SYMBOL)))
+#define ATTR_TCM_SECTION                __attribute__((section(".tcm_code." ATTR_UNI_SYMBOL)))
+#define ATTR_TCM_CONST_SECTION          __attribute__((section(".tcm_const." ATTR_UNI_SYMBOL)))
+#define ATTR_DTCM_SECTION               __attribute__((section(".tcm_data")))
+#define ATTR_HSRAM_SECTION              __attribute__((section(".hsram_code")))
+#define ATTR_DMA_RAM_SECTION            __attribute__((section(".system_ram")))
+#define ATTR_NOCACHE_RAM_SECTION        __attribute__((section(".nocache_ram")))
+#define ATTR_NOCACHE_NOINIT_RAM_SECTION __attribute__((section(".nocache_noinit_ram")))
+#define ATTR_HBN_RAM_SECTION            __attribute__((section(".hbn_ram_code")))
+#define ATTR_HBN_RAM_CONST_SECTION      __attribute__((section(".hbn_ram_data")))
+#define ATTR_FALLTHROUGH()              __attribute__((fallthrough))
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/adc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/adc_reg.h
new file mode 100755
index 0000000000..3bdc362306
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/adc_reg.h
@@ -0,0 +1,268 @@
+/**
+  ******************************************************************************
+  * @file    adc_reg.h
+  * @version V1.0
+  * @date    2022-08-05
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_ADC_H__
+#define __HARDWARE_ADC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+/* gpip base */
+#define GPIP_GPADC_CONFIG_OFFSET    (0x0) /* gpadc_config */
+#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4) /* gpadc_dma_rdata */
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define GPIP_GPADC_PIR_TRAIN_OFFSET (0x20) /* gpadc_pir_train */
+#endif
+/* aon base */
+#define AON_GPADC_REG_CMD_OFFSET        (0x90C) /* gpadc_reg_cmd */
+#define AON_GPADC_REG_CONFIG1_OFFSET    (0x910) /* gpadc_reg_config1 */
+#define AON_GPADC_REG_CONFIG2_OFFSET    (0x914) /* gpadc_reg_config2 */
+#define AON_GPADC_REG_SCN_POS1_OFFSET   (0x918) /* adc converation sequence 1 */
+#define AON_GPADC_REG_SCN_POS2_OFFSET   (0x91C) /* adc converation sequence 2 */
+#define AON_GPADC_REG_SCN_NEG1_OFFSET   (0x920) /* adc converation sequence 3 */
+#define AON_GPADC_REG_SCN_NEG2_OFFSET   (0x924) /* adc converation sequence 4 */
+#define AON_GPADC_REG_STATUS_OFFSET     (0x928) /* gpadc_reg_status */
+#define AON_GPADC_REG_ISR_OFFSET        (0x92C) /* gpadc_reg_isr */
+#define AON_GPADC_REG_RESULT_OFFSET     (0x930) /* gpadc_reg_result */
+#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934) /* gpadc_reg_raw_result */
+#define AON_GPADC_REG_DEFINE_OFFSET     (0x938) /* gpadc_reg_define */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : gpadc_config */
+#define GPIP_GPADC_DMA_EN        (1 << 0U)
+#define GPIP_GPADC_FIFO_CLR      (1 << 1U)
+#define GPIP_GPADC_FIFO_NE       (1 << 2U)
+#define GPIP_GPADC_FIFO_FULL     (1 << 3U)
+#define GPIP_GPADC_RDY           (1 << 4U)
+#define GPIP_GPADC_FIFO_OVERRUN  (1 << 5U)
+#define GPIP_GPADC_FIFO_UNDERRUN (1 << 6U)
+#if defined(BL702) || defined(BL702L)
+#define GPIP_GPADC_FIFO_RDY (1 << 7U)
+#endif
+#define GPIP_GPADC_RDY_CLR            (1 << 8U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR   (1 << 9U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR  (1 << 10U)
+#define GPIP_GPADC_RDY_MASK           (1 << 12U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK  (1 << 13U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK (1 << 14U)
+#if defined(BL702) || defined(BL702L)
+#define GPIP_GPADC_FIFO_RDY_MASK (1 << 15U)
+#endif
+#define GPIP_GPADC_FIFO_DATA_COUNT_SHIFT (16U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_MASK  (0x3f << GPIP_GPADC_FIFO_DATA_COUNT_SHIFT)
+#define GPIP_GPADC_FIFO_THL_SHIFT        (22U)
+#define GPIP_GPADC_FIFO_THL_MASK         (0x3 << GPIP_GPADC_FIFO_THL_SHIFT)
+
+/* 0x4 : gpadc_dma_rdata */
+#define GPIP_GPADC_DMA_RDATA_SHIFT (0U)
+#define GPIP_GPADC_DMA_RDATA_MASK  (0x3ffffff << GPIP_GPADC_DMA_RDATA_SHIFT)
+
+/* 0x20 : gpadc_pir_train */
+#define GPIP_PIR_EXTEND_SHIFT (0U)
+#define GPIP_PIR_EXTEND_MASK  (0x1f << GPIP_PIR_EXTEND_SHIFT)
+#define GPIP_PIR_CNT_V_SHIFT  (8U)
+#define GPIP_PIR_CNT_V_MASK   (0x1f << GPIP_PIR_CNT_V_SHIFT)
+#define GPIP_PIR_TRAIN        (1 << 16U)
+#define GPIP_PIR_STOP         (1 << 17U)
+
+/* 0x90C : gpadc_reg_cmd */
+#define AON_GPADC_GLOBAL_EN     (1 << 0U)
+#define AON_GPADC_CONV_START    (1 << 1U)
+#define AON_GPADC_SOFT_RST      (1 << 2U)
+#define AON_GPADC_NEG_SEL_SHIFT (3U)
+#define AON_GPADC_NEG_SEL_MASK  (0x1f << AON_GPADC_NEG_SEL_SHIFT)
+#define AON_GPADC_POS_SEL_SHIFT (8U)
+#define AON_GPADC_POS_SEL_MASK  (0x1f << AON_GPADC_POS_SEL_SHIFT)
+#define AON_GPADC_NEG_GND       (1 << 13U)
+#define AON_GPADC_MICBIAS_EN    (1 << 14U)
+#define AON_GPADC_MICPGA_EN     (1 << 15U)
+#define AON_GPADC_BYP_MICBOOST  (1 << 16U)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define AON_GPADC_RCAL_EN (1 << 17U)
+#endif
+#define AON_GPADC_DWA_EN              (1 << 18U)
+#define AON_GPADC_MIC2_DIFF           (1 << 19U)
+#define AON_GPADC_MIC1_DIFF           (1 << 20U)
+#define AON_GPADC_MIC_PGA2_GAIN_SHIFT (21U)
+#define AON_GPADC_MIC_PGA2_GAIN_MASK  (0x3 << AON_GPADC_MIC_PGA2_GAIN_SHIFT)
+#define AON_GPADC_MICBOOST_32DB_EN    (1 << 23U)
+#define AON_GPADC_CHIP_SEN_PU         (1 << 27U)
+#define AON_GPADC_SEN_SEL_SHIFT       (28U)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define AON_GPADC_SEN_SEL_MASK (0x7 << AON_GPADC_SEN_SEL_SHIFT)
+#define AON_GPADC_SEN_TEST_EN  (1 << 31U)
+#elif defined(BL702) || defined(BL602) || defined(BL702L)
+#define AON_GPADC_SEN_SEL_MASK (0x3 << AON_GPADC_SEN_SEL_SHIFT)
+#define AON_GPADC_SEN_TEST_EN  (1 << 30U)
+#endif
+
+/* 0x910 : gpadc_reg_config1 */
+#define AON_GPADC_CAL_OS_EN     (1 << 0U)
+#define AON_GPADC_CONT_CONV_EN  (1 << 1U)
+#define AON_GPADC_RES_SEL_SHIFT (2U)
+#define AON_GPADC_RES_SEL_MASK  (0x7 << AON_GPADC_RES_SEL_SHIFT)
+#define AON_GPADC_VCM_SEL_EN    (1 << 8U)
+#define AON_GPADC_VCM_HYST_SEL  (1 << 9U)
+#define AON_GPADC_LOWV_DET_EN   (1 << 10U)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define AON_GPADC_PWM_TRG_EN        (1 << 11U)
+#define AON_GPADC_CLK_ANA_DLY_SHIFT (12U)
+#define AON_GPADC_CLK_ANA_DLY_MASK  (0xf << AON_GPADC_CLK_ANA_DLY_SHIFT)
+#define AON_GPADC_CLK_ANA_DLY_EN    (1 << 16U)
+#endif
+#define AON_GPADC_CLK_ANA_INV         (1 << 17U)
+#define AON_GPADC_CLK_DIV_RATIO_SHIFT (18U)
+#define AON_GPADC_CLK_DIV_RATIO_MASK  (0x7 << AON_GPADC_CLK_DIV_RATIO_SHIFT)
+#define AON_GPADC_SCAN_LENGTH_SHIFT   (21U)
+#define AON_GPADC_SCAN_LENGTH_MASK    (0xf << AON_GPADC_SCAN_LENGTH_SHIFT)
+#define AON_GPADC_SCAN_EN             (1 << 25U)
+#define AON_GPADC_DITHER_EN           (1 << 26U)
+#define AON_GPADC_V11_SEL_SHIFT       (27U)
+#define AON_GPADC_V11_SEL_MASK        (0x3 << AON_GPADC_V11_SEL_SHIFT)
+#define AON_GPADC_V18_SEL_SHIFT       (29U)
+#define AON_GPADC_V18_SEL_MASK        (0x3 << AON_GPADC_V18_SEL_SHIFT)
+
+/* 0x914 : gpadc_reg_config2 */
+#define AON_GPADC_DIFF_MODE        (1 << 2U)
+#define AON_GPADC_VREF_SEL         (1 << 3U)
+#define AON_GPADC_VBAT_EN          (1 << 4U)
+#define AON_GPADC_TSEXT_SEL        (1 << 5U)
+#define AON_GPADC_TS_EN            (1 << 6U)
+#define AON_GPADC_PGA_VCM_SHIFT    (7U)
+#define AON_GPADC_PGA_VCM_MASK     (0x3 << AON_GPADC_PGA_VCM_SHIFT)
+#define AON_GPADC_PGA_OS_CAL_SHIFT (9U)
+#define AON_GPADC_PGA_OS_CAL_MASK  (0xf << AON_GPADC_PGA_OS_CAL_SHIFT)
+#define AON_GPADC_PGA_EN           (1 << 13U)
+#define AON_GPADC_PGA_VCMI_EN      (1 << 14U)
+#define AON_GPADC_CHOP_MODE_SHIFT  (15U)
+#define AON_GPADC_CHOP_MODE_MASK   (0x3 << AON_GPADC_CHOP_MODE_SHIFT)
+#define AON_GPADC_BIAS_SEL         (1 << 17U)
+#define AON_GPADC_TEST_EN          (1 << 18U)
+#define AON_GPADC_TEST_SEL_SHIFT   (19U)
+#define AON_GPADC_TEST_SEL_MASK    (0x7 << AON_GPADC_TEST_SEL_SHIFT)
+#define AON_GPADC_PGA2_GAIN_SHIFT  (22U)
+#define AON_GPADC_PGA2_GAIN_MASK   (0x7 << AON_GPADC_PGA2_GAIN_SHIFT)
+#define AON_GPADC_PGA1_GAIN_SHIFT  (25U)
+#define AON_GPADC_PGA1_GAIN_MASK   (0x7 << AON_GPADC_PGA1_GAIN_SHIFT)
+#define AON_GPADC_DLY_SEL_SHIFT    (28U)
+#define AON_GPADC_DLY_SEL_MASK     (0x7 << AON_GPADC_DLY_SEL_SHIFT)
+#define AON_GPADC_TSVBE_LOW        (1 << 31U)
+
+/* 0x918 : adc converation sequence 1 */
+#define AON_GPADC_SCAN_POS_0_SHIFT (0U)
+#define AON_GPADC_SCAN_POS_0_MASK  (0x1f << AON_GPADC_SCAN_POS_0_SHIFT)
+#define AON_GPADC_SCAN_POS_1_SHIFT (5U)
+#define AON_GPADC_SCAN_POS_1_MASK  (0x1f << AON_GPADC_SCAN_POS_1_SHIFT)
+#define AON_GPADC_SCAN_POS_2_SHIFT (10U)
+#define AON_GPADC_SCAN_POS_2_MASK  (0x1f << AON_GPADC_SCAN_POS_2_SHIFT)
+#define AON_GPADC_SCAN_POS_3_SHIFT (15U)
+#define AON_GPADC_SCAN_POS_3_MASK  (0x1f << AON_GPADC_SCAN_POS_3_SHIFT)
+#define AON_GPADC_SCAN_POS_4_SHIFT (20U)
+#define AON_GPADC_SCAN_POS_4_MASK  (0x1f << AON_GPADC_SCAN_POS_4_SHIFT)
+#define AON_GPADC_SCAN_POS_5_SHIFT (25U)
+#define AON_GPADC_SCAN_POS_5_MASK  (0x1f << AON_GPADC_SCAN_POS_5_SHIFT)
+
+/* 0x91C : adc converation sequence 2 */
+#define AON_GPADC_SCAN_POS_6_SHIFT  (0U)
+#define AON_GPADC_SCAN_POS_6_MASK   (0x1f << AON_GPADC_SCAN_POS_6_SHIFT)
+#define AON_GPADC_SCAN_POS_7_SHIFT  (5U)
+#define AON_GPADC_SCAN_POS_7_MASK   (0x1f << AON_GPADC_SCAN_POS_7_SHIFT)
+#define AON_GPADC_SCAN_POS_8_SHIFT  (10U)
+#define AON_GPADC_SCAN_POS_8_MASK   (0x1f << AON_GPADC_SCAN_POS_8_SHIFT)
+#define AON_GPADC_SCAN_POS_9_SHIFT  (15U)
+#define AON_GPADC_SCAN_POS_9_MASK   (0x1f << AON_GPADC_SCAN_POS_9_SHIFT)
+#define AON_GPADC_SCAN_POS_10_SHIFT (20U)
+#define AON_GPADC_SCAN_POS_10_MASK  (0x1f << AON_GPADC_SCAN_POS_10_SHIFT)
+#define AON_GPADC_SCAN_POS_11_SHIFT (25U)
+#define AON_GPADC_SCAN_POS_11_MASK  (0x1f << AON_GPADC_SCAN_POS_11_SHIFT)
+
+/* 0x920 : adc converation sequence 3 */
+#define AON_GPADC_SCAN_NEG_0_SHIFT (0U)
+#define AON_GPADC_SCAN_NEG_0_MASK  (0x1f << AON_GPADC_SCAN_NEG_0_SHIFT)
+#define AON_GPADC_SCAN_NEG_1_SHIFT (5U)
+#define AON_GPADC_SCAN_NEG_1_MASK  (0x1f << AON_GPADC_SCAN_NEG_1_SHIFT)
+#define AON_GPADC_SCAN_NEG_2_SHIFT (10U)
+#define AON_GPADC_SCAN_NEG_2_MASK  (0x1f << AON_GPADC_SCAN_NEG_2_SHIFT)
+#define AON_GPADC_SCAN_NEG_3_SHIFT (15U)
+#define AON_GPADC_SCAN_NEG_3_MASK  (0x1f << AON_GPADC_SCAN_NEG_3_SHIFT)
+#define AON_GPADC_SCAN_NEG_4_SHIFT (20U)
+#define AON_GPADC_SCAN_NEG_4_MASK  (0x1f << AON_GPADC_SCAN_NEG_4_SHIFT)
+#define AON_GPADC_SCAN_NEG_5_SHIFT (25U)
+#define AON_GPADC_SCAN_NEG_5_MASK  (0x1f << AON_GPADC_SCAN_NEG_5_SHIFT)
+
+/* 0x924 : adc converation sequence 4 */
+#define AON_GPADC_SCAN_NEG_6_SHIFT  (0U)
+#define AON_GPADC_SCAN_NEG_6_MASK   (0x1f << AON_GPADC_SCAN_NEG_6_SHIFT)
+#define AON_GPADC_SCAN_NEG_7_SHIFT  (5U)
+#define AON_GPADC_SCAN_NEG_7_MASK   (0x1f << AON_GPADC_SCAN_NEG_7_SHIFT)
+#define AON_GPADC_SCAN_NEG_8_SHIFT  (10U)
+#define AON_GPADC_SCAN_NEG_8_MASK   (0x1f << AON_GPADC_SCAN_NEG_8_SHIFT)
+#define AON_GPADC_SCAN_NEG_9_SHIFT  (15U)
+#define AON_GPADC_SCAN_NEG_9_MASK   (0x1f << AON_GPADC_SCAN_NEG_9_SHIFT)
+#define AON_GPADC_SCAN_NEG_10_SHIFT (20U)
+#define AON_GPADC_SCAN_NEG_10_MASK  (0x1f << AON_GPADC_SCAN_NEG_10_SHIFT)
+#define AON_GPADC_SCAN_NEG_11_SHIFT (25U)
+#define AON_GPADC_SCAN_NEG_11_MASK  (0x1f << AON_GPADC_SCAN_NEG_11_SHIFT)
+
+/* 0x928 : gpadc_reg_status */
+#define AON_GPADC_DATA_RDY       (1 << 0U)
+#define AON_GPADC_RESERVED_SHIFT (16U)
+#define AON_GPADC_RESERVED_MASK  (0xffff << AON_GPADC_RESERVED_SHIFT)
+
+/* 0x92C : gpadc_reg_isr */
+#define AON_GPADC_NEG_SATUR      (1 << 0U)
+#define AON_GPADC_POS_SATUR      (1 << 1U)
+#define AON_GPADC_NEG_SATUR_CLR  (1 << 4U)
+#define AON_GPADC_POS_SATUR_CLR  (1 << 5U)
+#define AON_GPADC_NEG_SATUR_MASK (1 << 8U)
+#define AON_GPADC_POS_SATUR_MASK (1 << 9U)
+
+/* 0x930 : gpadc_reg_result */
+#define AON_GPADC_DATA_OUT_SHIFT (0U)
+#define AON_GPADC_DATA_OUT_MASK  (0x3ffffff << AON_GPADC_DATA_OUT_SHIFT)
+
+/* 0x934 : gpadc_reg_raw_result */
+#define AON_GPADC_RAW_DATA_SHIFT (0U)
+#define AON_GPADC_RAW_DATA_MASK  (0xfff << AON_GPADC_RAW_DATA_SHIFT)
+
+/* 0x938 : gpadc_reg_define */
+#define AON_GPADC_OS_CAL_DATA_SHIFT (0U)
+#define AON_GPADC_OS_CAL_DATA_MASK  (0xffff << AON_GPADC_OS_CAL_DATA_SHIFT)
+
+#endif /* __HARDWARE_ADC_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/auadc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/auadc_reg.h
new file mode 100755
index 0000000000..19f352654b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/auadc_reg.h
@@ -0,0 +1,193 @@
+/**
+  ******************************************************************************
+  * @file    auadc_reg.h
+  * @version V1.0
+  * @date    2022-12-03
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __AUADC_REG_H__
+#define __AUADC_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define AUADC_AUDPDM_TOP_OFFSET            (0x00) /* audpdm_top */
+#define AUADC_AUDPDM_ITF_OFFSET            (0x04) /* audpdm_itf */
+#define AUADC_PDM_ADC_0_OFFSET             (0x08) /* pdm_adc_0 */
+#define AUADC_PDM_ADC_1_OFFSET             (0x0C) /* pdm_adc_1 */
+#define AUADC_PDM_DAC_0_OFFSET             (0x10) /* pdm_dac_0 */
+#define AUADC_PDM_PDM_0_OFFSET             (0x1C) /* pdm_pdm_0 */
+#define AUADC_PDM_ADC_S0_OFFSET            (0x38) /* pdm_adc_s0 */
+#define AUADC_AUDADC_ANA_CFG1_OFFSET       (0x60) /* audadc_ana_cfg1 */
+#define AUADC_AUDADC_ANA_CFG2_OFFSET       (0x64) /* audadc_ana_cfg2 */
+#define AUADC_AUDADC_CMD_OFFSET            (0x68) /* audadc_cmd */
+#define AUADC_AUDADC_DATA_OFFSET           (0x6C) /* audadc_data */
+#define AUADC_AUDADC_RX_FIFO_CTRL_OFFSET   (0x80) /* audadc_rx_fifo_ctrl */
+#define AUADC_AUDADC_RX_FIFO_STATUS_OFFSET (0x84) /* audadc_rx_fifo_status */
+#define AUADC_AUDADC_RX_FIFO_DATA_OFFSET   (0x88) /* audadc_rx_fifo_data */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0xC00 : audpdm_top */
+#define AUADC_AUDIO_CKG_EN                 (1 << 0U)
+#define AUADC_ADC_ITF_INV_SEL              (1 << 2U)
+#define AUADC_PDM_ITF_INV_SEL              (1 << 3U)
+#define AUADC_ADC_RATE_SHIFT               (28U)
+#define AUADC_ADC_RATE_MASK                (0xf << AUADC_ADC_RATE_SHIFT)
+
+/* 0xC04 : audpdm_itf */
+#define AUADC_ADC_0_EN                     (1 << 0U)
+#define AUADC_ADC_ITF_EN                   (1 << 30U)
+
+/* 0xC08 : pdm_adc_0 */
+#define AUADC_ADC_0_FIR_MODE               (1 << 0U)
+
+/* 0xC0C : pdm_adc_1 */
+#define AUADC_ADC_0_K1_SHIFT               (0U)
+#define AUADC_ADC_0_K1_MASK                (0xf << AUADC_ADC_0_K1_SHIFT)
+#define AUADC_ADC_0_K1_EN                  (1 << 4U)
+#define AUADC_ADC_0_K2_SHIFT               (5U)
+#define AUADC_ADC_0_K2_MASK                (0xf << AUADC_ADC_0_K2_SHIFT)
+#define AUADC_ADC_0_K2_EN                  (1 << 9U)
+
+/* 0xC10 : pdm_dac_0 */
+#define AUADC_ADC_PDM_H_SHIFT              (0U)
+#define AUADC_ADC_PDM_H_MASK               (0xf << AUADC_ADC_PDM_H_SHIFT)
+#define AUADC_ADC_PDM_L_SHIFT              (6U)
+#define AUADC_ADC_PDM_L_MASK               (0xf << AUADC_ADC_PDM_L_SHIFT)
+#define AUADC_ADC_0_SRC                    (1 << 12U)
+
+/* 0xC1C : pdm_pdm_0 */
+#define AUADC_PDM_0_EN                     (1 << 0U)
+#define AUADC_ADC_0_PDM_SEL_SHIFT          (3U)
+#define AUADC_ADC_0_PDM_SEL_MASK           (0x7 << AUADC_ADC_0_PDM_SEL_SHIFT)
+
+/* 0xC38 : pdm_adc_s0 */
+#define AUADC_ADC_S0_VOLUME_SHIFT          (0U)
+#define AUADC_ADC_S0_VOLUME_MASK           (0x1ff << AUADC_ADC_S0_VOLUME_SHIFT)
+
+/* 0xC60 : audadc_ana_cfg1 */
+#define AUADC_AUDADC_PGA_CHOP_CKSEL        (1 << 0U)
+#define AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT   (1U)
+#define AUADC_AUDADC_PGA_CHOP_FREQ_MASK    (0x7 << AUADC_AUDADC_PGA_CHOP_FREQ_SHIFT)
+#define AUADC_AUDADC_PGA_CHOP_EN           (1 << 4U)
+#define AUADC_AUDADC_PGA_CHOP_CFG_SHIFT    (5U)
+#define AUADC_AUDADC_PGA_CHOP_CFG_MASK     (0x3 << AUADC_AUDADC_PGA_CHOP_CFG_SHIFT)
+#define AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT   (8U)
+#define AUADC_AUDADC_PGA_RHPAS_SEL_MASK    (0x3 << AUADC_AUDADC_PGA_RHPAS_SEL_SHIFT)
+#define AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT   (12U)
+#define AUADC_AUDADC_PGA_NOIS_CTRL_MASK    (0x3 << AUADC_AUDADC_PGA_NOIS_CTRL_SHIFT)
+#define AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT   (16U)
+#define AUADC_AUDADC_ICTRL_PGA_AAF_MASK    (0x3 << AUADC_AUDADC_ICTRL_PGA_AAF_SHIFT)
+#define AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT   (20U)
+#define AUADC_AUDADC_ICTRL_PGA_MIC_MASK    (0x3 << AUADC_AUDADC_ICTRL_PGA_MIC_SHIFT)
+#define AUADC_AUDADC_PGA_LP_EN             (1 << 24U)
+#define AUADC_AUDADC_CKB_EN                (1 << 28U)
+#define AUADC_AUDADC_SEL_EDGE              (1 << 29U)
+
+/* 0xC64 : audadc_ana_cfg2 */
+#define AUADC_AUDADC_DITHER_ORDER          (1 << 0U)
+#define AUADC_AUDADC_DITHER_SEL_SHIFT      (1U)
+#define AUADC_AUDADC_DITHER_SEL_MASK       (0x3 << AUADC_AUDADC_DITHER_SEL_SHIFT)
+#define AUADC_AUDADC_DITHER_ENA            (1 << 3U)
+#define AUADC_AUDADC_QUAN_GAIN_SHIFT       (4U)
+#define AUADC_AUDADC_QUAN_GAIN_MASK        (0x3 << AUADC_AUDADC_QUAN_GAIN_SHIFT)
+#define AUADC_AUDADC_DEM_EN                (1 << 8U)
+#define AUADC_AUDADC_NCTRL_ADC2_SHIFT      (12U)
+#define AUADC_AUDADC_NCTRL_ADC2_MASK       (0x3 << AUADC_AUDADC_NCTRL_ADC2_SHIFT)
+#define AUADC_AUDADC_NCTRL_ADC1_SHIFT      (16U)
+#define AUADC_AUDADC_NCTRL_ADC1_MASK       (0x7 << AUADC_AUDADC_NCTRL_ADC1_SHIFT)
+#define AUADC_AUDADC_ICTRL_ADC_SHIFT       (20U)
+#define AUADC_AUDADC_ICTRL_ADC_MASK        (0x3 << AUADC_AUDADC_ICTRL_ADC_SHIFT)
+#define AUADC_AUDADC_SDM_LP_EN             (1 << 24U)
+#define AUADC_AUDADC_RESERVED_SHIFT        (28U)
+#define AUADC_AUDADC_RESERVED_MASK         (0x3 << AUADC_AUDADC_RESERVED_SHIFT)
+
+/* 0xC68 : audadc_cmd */
+#define AUADC_AUDADC_MEAS_ODR_SEL_SHIFT    (0U)
+#define AUADC_AUDADC_MEAS_ODR_SEL_MASK     (0xf << AUADC_AUDADC_MEAS_ODR_SEL_SHIFT)
+#define AUADC_AUDADC_MEAS_FILTER_TYPE      (1 << 4U)
+#define AUADC_AUDADC_MEAS_FILTER_EN        (1 << 5U)
+#define AUADC_AUDADC_AUDIO_OSR_SEL         (1 << 6U)
+#define AUADC_AUDADC_PGA_GAIN_SHIFT        (8U)
+#define AUADC_AUDADC_PGA_GAIN_MASK         (0xf << AUADC_AUDADC_PGA_GAIN_SHIFT)
+#define AUADC_AUDADC_PGA_MODE_SHIFT        (12U)
+#define AUADC_AUDADC_PGA_MODE_MASK         (0x3 << AUADC_AUDADC_PGA_MODE_SHIFT)
+#define AUADC_AUDADC_CHANNEL_SELN_SHIFT    (16U)
+#define AUADC_AUDADC_CHANNEL_SELN_MASK     (0x7 << AUADC_AUDADC_CHANNEL_SELN_SHIFT)
+#define AUADC_AUDADC_CHANNEL_SELP_SHIFT    (20U)
+#define AUADC_AUDADC_CHANNEL_SELP_MASK     (0x7 << AUADC_AUDADC_CHANNEL_SELP_SHIFT)
+#define AUADC_AUDADC_CHANNEL_EN_SHIFT      (24U)
+#define AUADC_AUDADC_CHANNEL_EN_MASK       (0x3 << AUADC_AUDADC_CHANNEL_EN_SHIFT)
+#define AUADC_AUDADC_CONV                  (1 << 28U)
+#define AUADC_AUDADC_SDM_PU                (1 << 29U)
+#define AUADC_AUDADC_PGA_PU                (1 << 30U)
+
+/* 0xC6C : audadc_data */
+#define AUADC_AUDADC_RAW_DATA_SHIFT        (0U)
+#define AUADC_AUDADC_RAW_DATA_MASK         (0xffffff << AUADC_AUDADC_RAW_DATA_SHIFT)
+#define AUADC_AUDADC_DATA_RDY              (1 << 24U)
+#define AUADC_AUDADC_SOFT_RST              (1 << 29U)
+#define AUADC_AUDADC_VALID_4S_VAL          (1 << 30U)
+#define AUADC_AUDADC_VALID_4S_EN           (1 << 31U)
+
+/* 0xC80 : audadc_rx_fifo_ctrl */
+#define AUADC_RX_FIFO_FLUSH                (1 << 0U)
+#define AUADC_RXO_INT_EN                   (1 << 1U)
+#define AUADC_RXU_INT_EN                   (1 << 2U)
+#define AUADC_RXA_INT_EN                   (1 << 3U)
+#define AUADC_RX_DRQ_EN                    (1 << 4U)
+#define AUADC_RX_DATA_RES_SHIFT            (5U)
+#define AUADC_RX_DATA_RES_MASK             (0x3 << AUADC_RX_DATA_RES_SHIFT)
+#define AUADC_RX_CH_EN                     (1 << 8U)
+#define AUADC_RX_DRQ_CNT_SHIFT             (14U)
+#define AUADC_RX_DRQ_CNT_MASK              (0x3 << AUADC_RX_DRQ_CNT_SHIFT)
+#define AUADC_RX_TRG_LEVEL_SHIFT           (16U)
+#define AUADC_RX_TRG_LEVEL_MASK            (0xf << AUADC_RX_TRG_LEVEL_SHIFT)
+#define AUADC_RX_DATA_MODE_SHIFT           (24U)
+#define AUADC_RX_DATA_MODE_MASK            (0x3 << AUADC_RX_DATA_MODE_SHIFT)
+
+/* 0xC84 : audadc_rx_fifo_status */
+#define AUADC_RXO_INT                      (1 << 1U)
+#define AUADC_RXU_INT                      (1 << 2U)
+#define AUADC_RXA_INT                      (1 << 4U)
+#define AUADC_RXA_CNT_SHIFT                (16U)
+#define AUADC_RXA_CNT_MASK                 (0xf << AUADC_RXA_CNT_SHIFT)
+#define AUADC_RXA                          (1 << 24U)
+
+/* 0xC88 : audadc_rx_fifo_data */
+#define AUADC_RX_DATA_SHIFT                (0U)
+#define AUADC_RX_DATA_MASK                 (0xffffffff << AUADC_RX_DATA_SHIFT)
+
+#endif /* __AUADC_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/audac_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/audac_reg.h
new file mode 100755
index 0000000000..a98de5f717
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/audac_reg.h
@@ -0,0 +1,167 @@
+/**
+  ******************************************************************************
+  * @file    audac_reg.h
+  * @version V1.0
+  * @date    2022-12-03
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __AUDAC_REG_H__
+#define __AUDAC_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define AUDAC_0_OFFSET           (0x000) /* audac_0 */
+#define AUDAC_STATUS_OFFSET      (0x4)   /* audac_status */
+#define AUDAC_S0_OFFSET          (0x8)   /* audac_s0 */
+#define AUDAC_S0_MISC_OFFSET     (0xC)   /* audac_s0_misc */
+#define AUDAC_ZD_0_OFFSET        (0x10)  /* audac_zd_0 */
+#define AUDAC_1_OFFSET           (0x14)  /* audac_1 */
+#define AUDAC_RSVD_OFFSET        (0x18)  /* audac_rsvd */
+#define AUDAC_TEST_0_OFFSET      (0x1C)  /* audac_test_0 */
+#define AUDAC_TEST_1_OFFSET      (0x20)  /* audac_test_1 */
+#define AUDAC_TEST_2_OFFSET      (0x24)  /* audac_test_2 */
+#define AUDAC_TEST_3_OFFSET      (0x28)  /* audac_test_3 */
+#define AUDAC_FIFO_CTRL_OFFSET   (0x8C)  /* audac_fifo_ctrl */
+#define AUDAC_FIFO_STATUS_OFFSET (0x90)  /* audac_fifo_status */
+#define AUDAC_FIFO_DATA_OFFSET   (0x94)  /* audac_fifo_data */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x000 : audac_0 */
+#define AUDAC_DAC_0_EN          (1 << 0U)
+#define AUDAC_DAC_ITF_EN        (1 << 1U)
+#define AUDAC_CKG_ENA           (1 << 27U)
+#define AUDAC_AU_PWM_MODE_SHIFT (28U)
+#define AUDAC_AU_PWM_MODE_MASK  (0xf << AUDAC_AU_PWM_MODE_SHIFT)
+
+/* 0x4 : audac_status */
+#define AUDAC_DAC_H0_BUSY      (1 << 12U)
+#define AUDAC_DAC_H0_MUTE_DONE (1 << 13U)
+#define AUDAC_DAC_S0_INT       (1 << 16U)
+#define AUDAC_DAC_S0_INT_CLR   (1 << 17U)
+#define AUDAC_ZD_AMUTE         (1 << 23U)
+#define AUDAC_AUDIO_INT_ALL    (1 << 24U)
+
+/* 0x8 : audac_s0 */
+#define AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT   (2U)
+#define AUDAC_DAC_S0_CTRL_RMP_RATE_MASK    (0xf << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT)
+#define AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT   (6U)
+#define AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK    (0xf << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT)
+#define AUDAC_DAC_S0_CTRL_MODE_SHIFT       (10U)
+#define AUDAC_DAC_S0_CTRL_MODE_MASK        (0x3 << AUDAC_DAC_S0_CTRL_MODE_SHIFT)
+#define AUDAC_DAC_S0_VOLUME_UPDATE         (1 << 12U)
+#define AUDAC_DAC_S0_VOLUME_SHIFT          (13U)
+#define AUDAC_DAC_S0_VOLUME_MASK           (0x1ff << AUDAC_DAC_S0_VOLUME_SHIFT)
+#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT (22U)
+#define AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK  (0xf << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT)
+#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT (26U)
+#define AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK  (0xf << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT)
+#define AUDAC_DAC_S0_MUTE_SOFTMODE         (1 << 30U)
+#define AUDAC_DAC_S0_MUTE                  (1 << 31U)
+
+/* 0xC : audac_s0_misc */
+#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT (28U)
+#define AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_MASK  (0xf << AUDAC_DAC_S0_CTRL_ZCD_TIMEOUT_SHIFT)
+
+/* 0x10 : audac_zd_0 */
+#define AUDAC_ZD_TIME_SHIFT (0U)
+#define AUDAC_ZD_TIME_MASK  (0x7fff << AUDAC_ZD_TIME_SHIFT)
+#define AUDAC_ZD_EN         (1 << 16U)
+
+/* 0x14 : audac_1 */
+#define AUDAC_DAC_MIX_SEL_SHIFT              (0U)
+#define AUDAC_DAC_MIX_SEL_MASK               (0x3 << AUDAC_DAC_MIX_SEL_SHIFT)
+#define AUDAC_DAC_DSM_OUT_FMT                (1 << 4U)
+#define AUDAC_DAC_DSM_ORDER_SHIFT            (5U)
+#define AUDAC_DAC_DSM_ORDER_MASK             (0x3 << AUDAC_DAC_DSM_ORDER_SHIFT)
+#define AUDAC_DAC_DSM_SCALING_MODE_SHIFT     (7U)
+#define AUDAC_DAC_DSM_SCALING_MODE_MASK      (0x3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT)
+#define AUDAC_DAC_DSM_SCALING_EN             (1 << 10U)
+#define AUDAC_DAC_DSM_DITHER_AMP_SHIFT       (11U)
+#define AUDAC_DAC_DSM_DITHER_AMP_MASK        (0x7 << AUDAC_DAC_DSM_DITHER_AMP_SHIFT)
+#define AUDAC_DAC_DSM_DITHER_EN              (1 << 14U)
+#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT (15U)
+#define AUDAC_DAC_DSM_DITHER_PRBS_MODE_MASK  (0x3 << AUDAC_DAC_DSM_DITHER_PRBS_MODE_SHIFT)
+
+/* 0x18 : audac_rsvd */
+#define AUDAC_AU_PWM_RESERVED_SHIFT (0U)
+#define AUDAC_AU_PWM_RESERVED_MASK  (0xffffffff << AUDAC_AU_PWM_RESERVED_SHIFT)
+
+/* 0x1C : audac_test_0 */
+#define AUDAC_DAC_IN_0_SHIFT   (0U)
+#define AUDAC_DAC_IN_0_MASK    (0xffff << AUDAC_DAC_IN_0_SHIFT)
+#define AUDAC_DAC_DPGA_0_SHIFT (16U)
+#define AUDAC_DAC_DPGA_0_MASK  (0xffff << AUDAC_DAC_DPGA_0_SHIFT)
+
+/* 0x20 : audac_test_1 */
+#define AUDAC_DAC_FIR_0_SHIFT (0U)
+#define AUDAC_DAC_FIR_0_MASK  (0x1ffff << AUDAC_DAC_FIR_0_SHIFT)
+
+/* 0x24 : audac_test_2 */
+#define AUDAC_DAC_SINC_0_SHIFT (0U)
+#define AUDAC_DAC_SINC_0_MASK  (0xffff << AUDAC_DAC_SINC_0_SHIFT)
+
+/* 0x28 : audac_test_3 */
+#define AUDAC_AU_PWM_TEST_READ_SHIFT (0U)
+#define AUDAC_AU_PWM_TEST_READ_MASK  (0xffffffff << AUDAC_AU_PWM_TEST_READ_SHIFT)
+
+/* 0x8C : audac_fifo_ctrl */
+#define AUDAC_TX_FIFO_FLUSH      (1 << 0U)
+#define AUDAC_TXO_INT_EN         (1 << 1U)
+#define AUDAC_TXU_INT_EN         (1 << 2U)
+#define AUDAC_TXA_INT_EN         (1 << 3U)
+#define AUDAC_TX_DRQ_EN          (1 << 4U)
+#define AUDAC_TX_CH_EN_SHIFT     (8U)
+#define AUDAC_TX_CH_EN_MASK      (0x3 << AUDAC_TX_CH_EN_SHIFT)
+#define AUDAC_TX_DRQ_CNT_SHIFT   (14U)
+#define AUDAC_TX_DRQ_CNT_MASK    (0x3 << AUDAC_TX_DRQ_CNT_SHIFT)
+#define AUDAC_TX_TRG_LEVEL_SHIFT (16U)
+#define AUDAC_TX_TRG_LEVEL_MASK  (0x1f << AUDAC_TX_TRG_LEVEL_SHIFT)
+#define AUDAC_TX_DATA_MODE_SHIFT (24U)
+#define AUDAC_TX_DATA_MODE_MASK  (0x3 << AUDAC_TX_DATA_MODE_SHIFT)
+
+/* 0x90 : audac_fifo_status */
+#define AUDAC_TXO_INT       (1 << 1U)
+#define AUDAC_TXU_INT       (1 << 2U)
+#define AUDAC_TXA_INT       (1 << 4U)
+#define AUDAC_TXA_CNT_SHIFT (16U)
+#define AUDAC_TXA_CNT_MASK  (0x1f << AUDAC_TXA_CNT_SHIFT)
+#define AUDAC_TXA           (1 << 24U)
+
+/* 0x94 : audac_fifo_data */
+#define AUDAC_TX_DATA_SHIFT (0U)
+#define AUDAC_TX_DATA_MASK  (0xffffffff << AUDAC_TX_DATA_SHIFT)
+
+#endif /* __AUDAC_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/cam_front_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/cam_front_reg.h
new file mode 100755
index 0000000000..7d337347f4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/cam_front_reg.h
@@ -0,0 +1,185 @@
+/**
+  ******************************************************************************
+  * @file    cam_front_reg.h
+  * @version V1.0
+  * @date    2022-12-03
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __HARDWARE_CAM_FRONT_H__
+#define  __HARDWARE_CAM_FRONT_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CAM_FRONT_CONFIG_OFFSET                                 (0x0)/* config */
+#define CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET                      (0x8)/* dvp2bus_src_sel_1 */
+#if defined(BL616)
+#define CAM_FRONT_SNSR_CTRL_OFFSET                              (0xC)/* snsr_ctrl */
+#define CAM_FRONT_EMI_MISC_OFFSET                               (0x10)/* emi_misc */
+#define CAM_FRONT_ISP_ID_YUV_OFFSET                             (0x14)/* isp_id_yuv */
+#endif
+#if defined(BL808)
+#define CAM_FRONT_PIX_DATA_CTRL_OFFSET                          (0x4)/* pix_data_ctrl */
+#define CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET                      (0x14)/* dvp2bus_src_sel_2 */
+#define CAM_FRONT_ISP_ID_YUV_OFFSET                             (0x28)/* isp_id_yuv */
+#define CAM_FRONT_ADJA_CTRL_2_OFFSET                            (0x108)/* adjA_ctrl_2 */
+#define CAM_FRONT_Y2RA_CONFIG_0_OFFSET                          (0x160)/* y2rA_config_0 */
+#define CAM_FRONT_Y2RA_CONFIG_1_OFFSET                          (0x164)/* y2rA_config_1 */
+#define CAM_FRONT_Y2RA_CONFIG_2_OFFSET                          (0x168)/* y2rA_config_2 */
+#define CAM_FRONT_Y2RA_CONFIG_3_OFFSET                          (0x16C)/* y2rA_config_3 */
+#define CAM_FRONT_Y2RA_CONFIG_4_OFFSET                          (0x170)/* y2rA_config_4 */
+#define CAM_FRONT_Y2RA_CONFIG_5_OFFSET                          (0x174)/* y2rA_config_5 */
+#define CAM_FRONT_Y2RA_CONFIG_6_OFFSET                          (0x178)/* y2rA_config_6 */
+#define CAM_FRONT_Y2RA_CONFIG_7_OFFSET                          (0x17C)/* y2rA_config_7 */
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : config */
+#define CAM_FRONT_RG_DVPAS_ENABLE                               (1<<0U)
+#define CAM_FRONT_RG_DVPAS_HS_INV                               (1<<1U)
+#define CAM_FRONT_RG_DVPAS_VS_INV                               (1<<2U)
+#define CAM_FRONT_RG_DVPAS_DA_ORDER                             (1<<3U)
+#define CAM_FRONT_RG_DVPAS_FIFO_TH_SHIFT                        (16U)
+#define CAM_FRONT_RG_DVPAS_FIFO_TH_MASK                         (0x7ff<
© COPYRIGHT(c) 2020 Bouffalo Lab
q&u$>Nz@huktN+iHt2ljEA>z+&*q3K9uhB?fQR{C=Yzwn~Zr_}r$i?&1
zPWz8GnJik2+i?@8J1h%(+oPQHKWRr)hX1X8-t{Cf
z_>3$BeQ|`=`Lj$a|D*(%#$OZ2INiDF1k>(zeOLRQ4VUN#9mI^xlX|i!Tt4c9TA7IK
zkO4Ik2?Sp;B>n@LmwlwW`Ax6zJ_#;6okAkVAyBw0&_v&^Q5*pKc~tS_9njHw9I=nF
zfzvR{_h-A{cT1AeLL-z3O0h+@m2h~dwtlM5>mjE4pq~Yh5kNiL11Ti`MC+7oXGJ1J
zf(|eKU#$&=ay4R}{O$C4Y=n^dQ?|jK_5{?adW#HA8AcaZ{lLeMtXG^NM=I05Q=@(!
zqRcqKdx`X#3@hVxTigw5ZN_TePfc?_rk6Yc$~7DGciFVMQz$Sc5@$7Y#oLz&Xg*0o
zNC*93&$SynCnh4S-NMHxcmi`_TO(5pcf)q#HtsW9X0L8ZcW`
z$1GA&7yeKU)7PuWlP5K9(N4`_-g)VmaT-j#9`OwjULXZ30agRrKG@!NaH>Hw!M9DW
zwWpd;8z_Td31SwZl28cdyl`*&UXu}c(m!8;vMVvgHVpZ%;(vbEfhe~R@4kSTmamXW
zAVQzPnM?E@>$hPi|2Bd`0oaFoUT}SmQ)v@??#9*oqNS>?`NaNIxWJL^DI-MY8YJEt
z0+FSJIFfX-eGdlQNS2J_dSX-BO-B;+@zI$2%Szj+;bSNji0~`t6+7c^{)-dhS5Amu
z;$%!rXud_p$cU2bryrDSC%mu497uUL>6EdmI5sK0K)FrD-j-_PkA?37A!ig{oqaTF
zs&>`R;7KSnQzQf$Ebxfm7$)GhWH4uP2q2VUxG0e$p_2tW7-KCwVi6l<$@+
zKs*)mBwX#|*vU}k%t6G54`bb$8Z1Pr%PEfjw<#{XY3f5ldKMdwWa}U59Mq`BEiA%~9HB
z{BhbY-GOY@;~T-zh7q_42Y1|BYlrt(3(Z@$_N=C3^#zJI{2kNV87*0i_jo_Mxn!H@
zqV;i+X*P|St;R^kdhtod(i>jH8^?ZKCO(8aq@V
zb)DwAO(hSh!-Li8*y|IJ#obInXO^?JuX?0u|7@M42YhK;N|
zF1c}jpz8cBgWsW&OMpzNX?9vUBw%ojyT>GnuuqhG(Va7!@exE0SEOM3h9r#Bf>)|Ut@T&*se6pXi;*a%H7B#fl=zb%Uz
zU@pz}#>B-_d4zJOX^Cl?vcVwKnjfPYCa>DN&P7IVT0B{R=-Ap|p?cL71XGhonxSGK
z%X${c@br;g#Y3@^^lbNhI5J$-eR}*f8E}kTSL9ukZmSyxL9KQ)0^(HZt=Ei*?uS~BN1hKlxIF`B5h<~%D-j;vn})GY
zx=cBR&##Xcw*hovc#U}zU(-gk2iuy1kd}Hye@Svyw{bIEzN4nxkCk7(Xp#ms_;U*n
zV}v>Vp+{41xDcIB>5b9^v}NMd4^72Wqql6RnotzFp1pvC+Jvo`MtzCBTyL@`Bze@f
zKHc>dBJ0~`LbDw!%{}wEb-M+>3-5tH%V10HD|8Zf4!N>|;-L1@(wEn~d9IH6K@`J6
zts$$TSAiP|^83H}1cWe)$TuFbv|j>*)#6+j<2WyyZ?OOW=Hn+KN{yXQ{%F*GR8
zaA=d9*aO<1DfttOUPWwg{QGkcf8zK&!$Agi6CE6x$0rUC71Mz}1LT%J^gEHy?Z70z
z8y>&9mj5Sw_97~vRnXKQ+>4^WfVgm$gnk2VNqu|Xk3Q{h7>h%5{3|8`^Emn`y-pZq
z;7_23TR}i&NxEPYS(Jp?2P-rgKcg@1#*MCMC841gs905JveaIOe+8<$U
z8NMI0O<0qpfMCA={p9&~{ti@s
zZIMZlzLbpSqfdxsL^v%a^=t1DdD%%Qn&1H9;CSUO{do~Cky;V{|9xLAcTE&-T$tZE
zQXV*E4*%2S;oepl&CGUdJ=g755_GR?frZ$c+y>$nKKGpOm0n=2JJ~VbikwCqaY9Oz
zTx2%BLfnZ3Q}=;eKLEmv7q0{dI<;ib4Rt=hDt;VX2GWPoysxmiAGaK-FNiE$-!n#+xsRQW&Tt%
zF_KPuqUS0CGt$wxgZMZH`+vBf-|&B<4<<<7x*trCKd~mBX@=C92L8;Nc%~J}XWQ31sl5O)XpcqG0GzlQ0fD4D7ygD@
z4EoE6New5@wHL~mHA_N4iQikDdh&N#JvhShu&Uf|c1k%KRYA~JvOavk-xFoVldn^u
z5WuWvu0%$=zupksv(&FJ@Vte~JN|mxagBusBf~tiWMN59{JJLy=ULX7zFPDnosgBGXIUWGktB0
z_%R42PKs55E>74+SWSN{3Q~gAzW-g4kTpHR?037Bv&hQ*xv&uG8gi<|dQPYDB8k-z
zSf7iywCPwLXL3Au(e-%@qTrVx{~G(7s?PLFdotl=n3cmj?y*m7wKwuY$ZXl!QCnub
z4u(>#13*ZD(LrP*8}x%rqDj=dfSNdQp+24?CM4^VEw>u|bOo0kTSq*Vu6|fVoh2N5
z>>*q)a><3HIjWdPloNZ#-LU~Winj-hj)GDFIY~DtGG2Q
z@MEk|e0VFyoyNi`qgBcELN+C`{1e7eY?;m7i|sF3D*Y*{JiLRF&))%Y==ZzSu6tU3vWBlB+Da4efwj9-wU?gB`Nh1-Rn?t^$XqVbg%*VA>tElPXnd}H
zhwbX;0#O=BorsX$i(1LPJVOu#if-1+^+_=4t)Fa813dfM%i>-~A6~ROZo>r30Rl4Z
zI^u&YIe8B&%iY!@2(SXYygYdYJw?z$rITLHO4Hmn(K0aYIOkYzj(y*oj@;u&4Le8A
zi&=_yU2zW8?Q1?o4Uje(q6Uwzg!V2yvC(6(ZMzp{Djf9PUsh
zxO5~bji1y0K)QOru6Cj(0zvcnZr>8cwdn>S6^jsmfaV6^_&>FtHG_;52l@MwqsW(r5(uAv-Oxy7FXR(
z+lC0;<`$^#lx0(n_LifPY#7{Fa4e*$wVoHyWDM-zKs#uKO&zWqnJlWQ=WAD8C(MZG
zjWk#Ez`vbkyVNd3!?$LVZmU_KD1k2yOnQ%h*FPqcX5wgY)Ib1^ctgvaRB3&Q{SuBI
zeT5w14%M#AH{QQfr!tXKEn~1mn6Gx4rSpX(4qa)`azn>H?!IiGs}740
znPeE(U}xm(^Ci|D8-(SfRAq~{)z2n)DPz3q`*N$t^L-|O*8m59itUkOsh=laNcklk
zA`cOJOX1RWt&B-ga>m(i^c9YSYF$48fegwJ&iP)$;y%qq8HXUqE0^0Z$uiU~6d3Aa
zN%F@)M}~)>_`<`NLR>R)n@ShknHO?`JB{OY1xNC!1;{Z|f@r%Xlt)8lpCABUAhO>9
zQo~qUh|QN3yEIeozSjeD1EX^xj@M`!Lygw2QL<;gXOcM=D!m6ABtL~0i~)FqU?qh}
zgW$k_bfLJ^>rHOmYB{21(8)nzP)@%b*ela;YL#2Fx0MfwB>m{~?`%K&myc4nZSSBo
zBNJsZaDJZNpjcAAQ~MAx_w==kFFfE#saF(rkz$=^S?Ue6Vmg%>@0{)miq%8)JW3;p
zP(INvVFTdr5sDH!W`Kf#BAdFqn)K%c8%~-|=(n-=Np@0`Jg#(zOjz{={q^f#z452Y
z#$^MHamNDQZq6hB@67ND=kZ&SnNU6}2TRS;H$c11f=;t_=aglg?lQACLaPMZE8L<5S&IY4ZvAWiuJ`D?}*oTT*X;Hlnp|
z2Lzkf<(@jb&KAyGN&
z)lk`pA
za$-7BU#;hBhH_)*
zl>4XmxdBB76@PFjKXZclHG8|6ogwpECKz#O=nFhjf;o&)qSXP@EXL~{aXgM8%Xn&}
z2!3P9O0uTth~j0;%P}wl(c6V>F$2{Mg_uo!8Ts4zkOEpCCMXVuCdA^mm4BdV>z)nQZ;gSo!jWLm2ZtPc
zL8UGfP@?g8j^(b2O`V{B>{9xWd3Ejiaw}tTN|GN#E1EbGr>P4j)eZ8u1(zbi5Sq8Z
zi99&$?fG~caaCEE#uOkUs{bt%iB?k0Tpz<3c#$6{C0a=yfBoyPws+Vo>Mm}O5t3IK$)D>iioCE(P|7`ic%
zycUtL4Z}Wx`|1sbvfQfo1i=aUMUX8x?NU%SdXS6aBx
z^9@Vx&d87k2=BND)~7CMavu+V>>^EQcZtaUn&O^}{NbK2;>2%h`Xlzm<)Zjji4Rj^
z=J4wi9(PlGE@aRV@)1&KKCbguT7Ze03{%P(9m-FCpbT-$-?UWKw&fE#>Oq$JtrFo@
z6A+-&0}iVTwFiXRu~W2Hn2iJQ6d7kpg6BE7dje4~(uKZAa(KFa{(Q7zT0A9sm3c3f
z{fq2k(d((kN2ne?akAHF$m!t9SfEkO(fb8WsJTbjy#|yUsd@W{%R*L
zmV0fnaqT(9F98tYgui+)@{)r~Q)5j*PK7qbSBUuC$w_r$lcuz~Z(xEnx$g!WwC0T5
zu|Flr4p?TK;y`lI0JAa3fh6Pn_bVQMcp;x9y8GTRg65#A|Kn!8PpHx#DnQZy)Qu%(p0AW5xxdtAC?94(Z?%0tZp!L)r(>r
zB0I`wK=$7aSmslgZ|c1?Ecdz-fslvA1n92xweixFY{%1o;N!u~YR5C=G@QsL-x7b|
z4jVj1nq$3uP_5T9^KLN3^HR^)ku&V=3)F?c%}?!DB`Mi6T9j&b#zo0n{}YDd-Q?K3nA9ed}C+;_FO|LZpxaEa{o}yX
z5pGkCVU&u-3uPpv2iI)8S|~F=I&vzulGk^$ECF=@t-4{_0M2417__#r2CFrO*ILCb
z8WBw|x=l~Q%1PCv(@bR3g*rl4)b{(eZyLI0oeR=~}EYn~U2f#mxt|zNd_zv_SOUNINT%JBL
z@`p8L>~XA-PbJtr@@q!)yhH5Pog9grLU$6>O_hVe0bzW8$s^qbu20-M{TM0W;`?x5
zIP3!p06-cU>jLP#X~YQy0P5BkuK%k!fA!8^vh&*<{eM5Rvc`Omy)5fiUx7?SWs$Rs
z$GwR47326D#AJcoWg{)T$I{>Dbn_^w-mP7cBh=j7!Dl2TN{o3ttoH_kVCX@2>Ndg<
zT)C#UuK}DcaiPEYXg=6*LQWEGmI+R_piMvSi7ZUe*RztZBss7gyItj-mlsevSYHv1
zkv8<`eMnrj$BaD}qcOMqL#V-`s^5`e{JnC9Mz5_IN6O2w@Wn8=_*@?=d>%j%fi;Ib
z1UgN3Z2ZfTWK-uE-A35yUFaJtJM^sX6=2)z@YXZ~b{s=5SYpU{>T
zWJHpornk-#LuR-nC%!c*LJ!k)j7S?yb*iqYaJfU9X47;Df(B7Mz;YdA{k2Cpp~l)z
zz^>(%u=(q<=ssYX^ILEHN52ntrBCRkY9V^S;ZK_W=k#OK3_`-(jQ-bJmEKQ6LRE>s
z`&t>;zK0X(AoB@5YfAZ5t#KcG9=Lgz_C4fixC$Pd)msvXIcqgzpo*kmGaLQ6`z!FUQ*3#gX-K8!OpQoO7SJqK4j*s&-
zn`ZBgcYoUz)4+C_0k>HCHZS|3o64?4d)Po+IpfKC7W=9CX?jbR`aijEYL;dZhEy)x
zCq!Pf6kT^Wm0`Yer~k3EIcGJa2K9>%0T-*Tskd9vqmZ)9YLT(q4P~8_ZGYPfm+KC)
zgnx86d6T=>c>lUNILy~~|KD{>&WZY>fYlM~)LW{0wo6+LqvwobdxL$gQQj;OuFGd;
zc@t$`@8!rvz8Xd%fv0BD_#^h}zW^zQ){<<^bPmH=L^Iki>CW+K%+lxW`|!E#O!~Jd
ze|`O{H~xPYhVa3(Lpkeo-b~{p4=ia2BL}%(mU_Z_#WFw@Pzls%Yy`g9UEV?D6KlX}
z!075=H;_x;*0P)~$sRD;4m+hPfNnH^6djVsz$h|HfP>77Pdbt-JgQLj5UA?2Ke|P6
z_a*Y+TU+>}YKVs7uSWcrdqQj?1v&6`x9nzkcRv+SqN4J+9|EsY9?0aPR*|fU4Sf_r&cK|^
z;76ZV9DF8{`W7@V0Z|R~n8av?YhRMG+{~%Z2B`v9yvT{Q)d?njl0e;R5~_J!UJm0`
zc^sKNc)N@&wo(n8<`rJihaLt?`uu0LDk2U5M@S9dF10HfQ7Bj?Tx}c4bAyI``RJ`D
zdlE`mIKk!P@sLW!e$xIh_lqPB{Kc8-%qto(;}7lES_+8NTyHAOU+j`bYioRh^Msg0
zsX(n-@?9CGVdDDhw#sLBCeXLH{LkCEstMU8YS$cfY>v^zIpnBoGkIhfc~YB8(+T0F
zR3OJ!kZxmk1!ai%?!wsY8(rqT6tC_}-ah$M5i+kVH{;eu;@CqZ$%Fldv9@7Brz>9Q
z?g!=Yxp!p_e$e8Uc81{4dDaM*Pet!7RzrnM!#7^;m@zZJ75KeNdPYTy+X_1T$2FWN
zR|lK8mq?1(G;EjISp9REa~-7~6-YU7r6@il=De2t$~N$v6&qS8FPyN+8qID@H7LVW
z_hND2_&pixc;fgW%A)JzQ7pLERdwIcB(m195LGa-55&G1P@JAvDJxKKun*b`uXtZ3
zV@sBYj*%f}ZF`Qd3v%%#8Y)J~5c8500m>fFbTEiV-o$GyL)L=elOX0EpeJn&^+cD10gCZDU4RM1=)J3M&hxZOZwCb5C4;EH3_n%
zGU(;^E0xwLrtqiUvc2}l98tig3CApZ9%^)p=jD!Zf(&|w*4?UD*u|WXd;WRv*=R_&
z*b|+*JK6*WR`X11B@<}&BZfLN7)ncQC#0&BL_b+K@*R2{N|X9u2~oe1z9O4BZfYbK
zb-Svk${8c%F!bfq9ID9tUSZeh}SXAQ-0S{A66lP+EW7jDaSr
z^Sb(DJNgBlgz$>x@Xl*njWD^?2j!WDRuPf>#Wt^3MSyAVPw4gS?sfMkWxXU
zVx)ZF-snb>&XyKamVv}vXk`n<&83Ma!~aldXyX&0$S+is`V0zWqSC1xeeMuE-O|NH
zj-@qxdduxCXBH}n?fN<+Bbm?{fX&}f>i&&V3C|{voS*jVz-fwFg>qr9YaLQy*%zZPAt+Nk(FzVV)bXh^X7nS5g-LQ3YU9hCS64oJxR#FCF5^34!
zdlMu>HP+pRo#S3{L_ClVquGv2eyae%JEzx(V6N7osDBb4#4%oIfoU~g7>yGw3At5NP|5tA1dY81dA#03EF=|eM-9Q#A@eY2hHfrl6SRo
zbGYiAHguOGJIqh^YCr@p7$gS_WGrrJZmy&jN+Ojn5G##E=r}k
z@%8QGnhvXKok-4ZP3^72-MYzXB0k~MFyTX*@Nh2Ol!kq@FrK0)>9O3^$VrKn%G4og
zec*`kk^@5add{iS;||TUKnSVAr9}|dbs8^)3(Ojc)2J?%zkeZT(qNJCyP2Rfsc}@<
z;W)iJ{uN?in&EcGF9C@jM7k}LTmNhEmC9l%k4DBIG*}Fp0sK7h=EFf;qOd_IE8^Yv
z4}L$0rNORVJAf6J{QfDI4+=+zUXxyg_Vd+k^h3Sn1zp2i>3XzVSLz}GnX3Qy&#(?~=wJt(24*mtVE2&`
z&&iS1m*jY|hER9!j`-|D=1kz?n`jb=?V8vVnCXy@yuktTp`#&<*>Q7pwDqs5Uq(J|f1S}Jw>E^Iif^Ee
z82mxZCsL~REB{|+@BLlp@ZG4$GuMJ(08Q^#PQWaC#a(CLA;Z64fz;qEg+`R!*+*xb
zeOkH%h1v^u!^hoct4%(8dsZBtyY98W8UdO8ul0oI$|~#;B~{3I;aTk0d
zCy{CvbSjP-J6!K@G$-2~hn`O`1nWu~;xgTH!XH7_#!Sq%GBHl;aF3hs6I%4!Ld|#J
z>D!Gc*_180$_O>2dg$WdaKRwI`^uC#MppAfS}nAvN@|YsYBK@0v-{!!{j!5g(yWFr
zYKCpJX&^Tj3=LHyu7&xKbhkCoAu-GHJksF~@9OjWGAW=roYprst79@ZpxU79EmtoN#{d0lAE;F
z&J)rPtJ24^bw9cixN7emF}6Fjk29I{7z(}LNI3GPoLeZ^9JJm{X)1G`}
zCrYaDuh$nBuHs+7d@s^KpAd-NrNz4^d2u#
zXqxDybtl~3P|*<~tM@)gGeYQVTZfr@^hHx9VVHoGi)IcpBZ&Qb*1A0srQ64k)Xj&r*d3)t6z2DWUsD@)$EDmo(SeR
z?d06#iW*OyrOz0;^Ez`p{#S^?D;5Ysrwi_-m5)(0%3s#QyleKV?m&{o@{zI>;wSPdNj3fNIY^+FHMQg~7VGF8Ji!!OpTWK&9a+Eqx|*p7cXZpDBw}~&Qoq`u
z{c5fzGoz}{m{uL3jKL=1RdLS;ZL|;MvJuOIt|Qs)>cWBuh2Bjh%E@?5x(&@8lPa(eqdN7>(n@Py=15qt|PoWYOhkHKBaGl
zhf8oSc7oGePKySc)wuiN#9oF_n9yCnZRmk?X^a)I3&Bxfr?7?Anq$5Rp4!zM?zxso
z!iXD1YN3sm-R&iYWwjJK0?W~P3I1Bknx&oI8B86w>E9=XHimhOOBI~Y1Y)jDtR{qf
z7vv*d1nLMtCm3u?PldJ!L8rsMLT+){)*M=POA1f|*a3`xCWE_sux=38Gv6X-y!B4M
ze2b#VZmzM*T{#j7BHp++qS`DKxHU^t8jw=)LL26M{2?{OF|IN2QlHIKRYrRR!8RYG
zRJ7w3c->jfuMpf7Cry!8$KplFBV(MaY2q!!-0IYP!Td8-)!4e+!I-uPmj1_3Ph$5m
zy@_Tt&07vOShLfn@kRl!S~^2TjY7(HnBD{UH2mWDNJ)nHGNb%nU9nl1kV@NJ~Hz@SSTBcR(v_ZZp4xYzpa
zX2lYEY(S&+Bx-lv?oj>O9->NnBP0K6KZ5EYLg>8At1`GsS86(PzhH%`P&qnZxq(>8
zVV-SKIIM>r`6VYzU$?j9os?y|or}BE?5DK$n}N*p7a=7N5h{jgSxC5k5C~SuyDY|0
zj#1-$X6R+-^0i=zz2_mxgDgoAj3zJ=#fV9~n`2(~7F3o3A<8@`5F%#Pk^qNww_7vS
z2du&)4%v*^W|d>teLHZDKi?Dc%g(mC;2#uKSWo!0_sZJn@)7j-c_cVy+14D%aTh^|
z%Yc(py~A8{HCn5HxYr^+o__Q>0jEgn0HEPN_xFu%zsW@a$F?Nqci%E^t^p42jKHK8PMhboK*Oho*7F
z3G0EX+#8!L)?b_gb`I7<2cy%s4vc-_Jn}$0`IUjmGT}D{rZf=E)-v$NzeE1}epcSq
zkt3s!svTIrD(TrZCG+y?O>}$-Cec
zN32v)`e6y~-FYkyf4|WErf9NAFN00>YPe)*A*!l6UZGoXqUhSk7uuu`cAKyu+|Xh$
ziiex0*&Q-~Wz=x_D`b1l0<0pD$Bgm5ABlYuOl(|dbEzSGin(h_fk$1~jb9s+y*-FPy
z;191#|3L`8@Fl}u3H;CT|LQ@LNpIbhNLR{tBoIaF!6*`2fnu@iz;=Ki@i
z2-$I@n4~rxvXl;FW@br!cOu!u
z2t)a32wm{PMc5z)!FJDLhrIDLE{?uR0aPBnFsr0HwS7m=gP7Nb8FKb%TWN#=Qx+SE
zC{kE69e09Q?|l52Q=d7pnab_*;PGq5Dssx#n%mBOM!wsV^y=E=Yd{;(4HJQhtc{Dn
zun&*62s+`_PZ1pbf$w;erTb=jOIpmCr%Z5#8e0Xu=R=}iaTJs1bVv&?m1^+dczJO?
z_zJ1HA>5CAycdLkdTDabWamGJb@mgT5YDT>Dh}|R{y~r$s@I&
zg{s!NBK#I>`zekQb%+b)2R}V0=n?$w-fA(wCSx@G9(4N%AoSr*&qt5q|9m~dfW-vC8)3FNh-DRKw6ed9ks2+eF)&j9stX0_md`kvAiXjq>^W?Km
z;3=lh6O`#*_wM;&k~M}PiMxv<`V?SnOoT+7T(9R
z(YE|^cCi=9qjK*u%1{dwg?9y|>FPyBjT==rQ*?g!)Uveq9;=Ksl(!^0O)+-~cEGZ~%6(_f67m7+D9@~2Bh?j>P&Xv!8
zm)N?zCHp_5V=|l(u<{$Z_qmhh+o!*(baCROQy7&B%yP5m)3(sx~)2!^Of<1XTN
zgE{e=xSyRSgY&F8??2P$K>-+7{657#DBTp4fN-6FPJ=7N!uga(9ax@!f97HTCrbaO
z+h&OqdSdhkKk?$gfodw;yveURkjcwE8g80pLc{sDI&Rrby8bRME)dJW3ZfKf&DV1T
zG?dU6LZy`DnIr8;F&5sffTxL=NGnQRc}2{=Bys
zEL_!KClzTb;$i_|DfiD_3Oal5`9Cb}@ed0dEE<-FTTD{NCSI<2p`%h*&wxT>R3_;z
zq55|piPW_N2*{qK*1fdY&E~a-V(QSo{xZ>;(oR!2ad-3it$BVbDr#&FOD!6V`QyQ0
zVVsr75WUo;J%{Rv&rp4r2Q{G@Ecv%rMG_bVML)$owW<-Facs^7rvam2MVzcVIiUb_
zG(Y-@^W0*{G5a9cNmaF8X*ehkQZc4`Mc3(ey+-irj1N6!|@+0DcY!zMv7pnca(H|R*oe(>qPosQRi5A
zm`en=w$6qn&PwoTF%C*wVkhVqJl51=y?|F-Xc;3)xY|wr@+8>^EZdGCQD6t`He=k-
z?R_h-DM%gkASWzSU~`#alWMNoPK=Tmm&V;!c&ui-DDWl(=Uh3-v-|NjpJi>?4;Xd6
z1O_tixo0iPV@@v1?`cV|D-?Iryrqk%oVayS*eD{|`hme%n-I|7|K59{#p9P$^t(|c
zsp~W^OpL3GVYF6|kdnLIAkB$$~aW^4V-&irV^ZrA?2HnrTOh0In=#W+A@3hsIPOR0ej4R
z?lrDmi8*cAf{fIAy8H|F{DvuIFZX0}HFjMBCW4vvh93Lhz6`JQ7fmW!hlJwj7u0jz
zy}L*IacmKWKacz|dU}*~W^ng{3yV1yDs!Xbmx&RbEJpk-16}33p*HC{2EO_S4B^cI
zyQ_K_D;%0D5kqux1%07Y_+>9pHI2P06{IjOSwqGyYb|tl(2XUXgb5Y-ZH?4u%w8D4
z*vO!XX!zKfoLg8fD(KS5;^I*qf855>flzkT
zm9Q2@8QO)PC=D^+b&42TmGav@xdD4#Yw|E6fa+RJ5=nNREn7&>{-9zcdnIlVV}YWs
z13?hivy3ZTxz7s8X)SOrOwl~%8#|=&P=mx*7fD_r;)~S7;d-@!ynN+#nWu$rgNloR
z2Y-p|1xtk{C%1G;gIM^Z^s(FdM$|*}`B#T(^z-UxBKlJk+AA#1w=4Q=O&MKbF%0C!
zI&9}astEBn$nV?_+>4n#QL@4jeq~(NE9;bJdUbYorjx&!^m4X)1Lb@KDIdWrCT}
zV1Yq3rzy)o;$o5NlKUjmL;=UZ_R?(=e*?@8TZY&^$43elI^-dW6S&N&)ET#qv%6rz
z*Gz{r<2#}Ew#+pJrfKI&Ly6M4S7^5dEANa15WOd&v*x3;UlkOALbIH?yA=i^MlJJl
z-S)H|)SoYycx&0()mORS$ztDMV9Pn!H7`L3xuAet`U{}81O8I{i|I26+YWe;|L(7k
zy3S8)dqB=LK`7R8Emg^ykDs&DO;a459~uzmAeDM=re(4hs`+7qh^d7zZr*`t%~Wr#
zo%L`Yx-kb0U`~G2hJCbH*OoS|VJEy;lU<0s_c-!+OJskut|{opeKt?x>JqY@^W+OP
zwOt%H6W9$KB;a9fZt3wtQep?1{SK~k2&WZW~y5X0ZKyvf~%=BchyFdzuvj8?dYBpe2TX|pgiEYaP
zU_^eusP_ED;N#TV0jyMnqQ(-o4
zyEmafj;%CP36`yQH*WXV{H?6POyMKNW`k}W&QBxGN*GmHCm&hy;Ed7bAu&pG$r^SaNy{+K^z
zUcc{ezRPF(ewO!#b5W7<)!bROHbio7uFsjS+yHn}0CKdNH(>GZ8|QBZRHg2tkEJ|<
zq91(7JZw)^sJRUCxSGrC>^t88Z}F8fPY$?ru3;U_0fmo3d>3M6?|;Mu;u
zS!ywr8+4ciEXtS6!>U;tLV;>I0lQd5bT=h>tu|Y#du2E9BpR2z{SZSN<q%NCKmXo*r)>9!lmrY}^qEja1RS?mxHr{q3^UK{I`
zDdP&9Y#QTme;~WgmjeUE!K)C@pPAVO`fJQw3q4`kcOr{F&sfl&#qQ>DHr71KXC`fm
zpAv=rr2!&db^cl_0nk#Eqib2ug69)G2BZ-ObQ%Y}j0~6LI@Qj^@E3mO`uqI6MN^(_
zsBck>;+hu#cP(KPVID&2+|om-HeuhmRf1JM4k0qnvLnO{B562od%2cx^peG8$|hG@
zueR(Ia5))$wvOw66fRG@T1)IA@+kd+FQl!}Y^3kjE>~I+Ic!BNsvBqZjHY2?IbPFk
zxESwdOY(tjl7X%WMTAqSIy16@Klo0T{ZOJCiC3=6L$r-PeK(p($gTwTJN*@K1Cl^5
zGDAsc-@Z03q}SG(`Lw<&n?nDvd9g?4S&!muLip2CJR9JV|`OCnbQ$V3_-GIZV-*li#*@l_N?fNPi6xnhR4AuSVY
zlBlI_;4Df3?I`2g30${MgKjz)l3WDf*Axxfe`}!OVeb-9Uq1Pmypo@Ecf?vpDzDNCjVc_J(@Rx44HJfKz}~o
z>il}Y!e_)J%9QO{&plhx%JrixGv$$OU@n*llW@pw(-tkI81-Z2M
zG_Tg{r_95r4Fk4HE-f}tE1O?RwPZvbXM^MoSK9S(T@y@n8tiKP)@oN`*JGS%7^x9l
zTKr%M`;+&tAR?Ce*I;BbKGeWgflFE+NI(T8?mf`(Z%CEwksr6FYkqE2aPH@Pp@4IN
zy0;@*9?N5VDj;mI<8#;1<~VeF7aDhz#Hbe-rN;jy`8o2O$-D5DmIl7MLfO=~nD$Z-
zqG1wXFX_C;KT=^3(ZE=Aw)r&&HDvQK)z__~glrT`
zRw$d$owzqI^{`D%4dn@z5FeV?@*`>T+u_^Hs{RpVjbVs2lh4eJLL-V2)KrbEj;*Q|
z>HRuVRq@YD-(1ZM>8Q)pRkxP2lRP3pUNEJ#vxa892bgpVS+g~pSTnQlqb+#Rqih7T
zQ-g=>BQ|>mxszzLk&A56Mwzz^zwq4BZ_QH9tgAnAc%XWc!=C0kpXQUVh3sUiDxTyc
zPp4~@;5^02bI;%X^y2tg5I_rU^<%kkmz@lm7apizI4kS!Dp~v$N_|=~7giL}7;|`T
zz_ah0sP)K=`R1p!_8-K>`6F7@hL3gV4#JDwzFSoYdQRq@3xUU6@i%q8-OO~G@gNN)
z;~O|j;Vet%yovIN*9qHW7+SHwW86IX1D~Q5$q%vk(6~}Z#6`qSoR4-L;ip-fUYhpc
z?>p(BAX*e)VCboEyeJg3XXoJcZEDvWOb*fPmrQgF>8WO$+DbhUV{hWG7_u-|{wE5T
zgzv`Ca}#EqzOT*L%P6TO8gzknWGe;$oXu&e>=#27uP})^~#>&*a0(1XhV5B3hDA#|hs4Dkn0CH&CcE4PS?ynC0g#i8YX
zgkEPFck^s>u1@nM#oVfHUTeCN#=~-l`6w-;=IqezZrFuFosw%?@!~2-Ce3
zq~ZW0BZI^WyYn>qaww~`C?7?p5LrQD)cPH!nl1YV#wa*cYne7@lUd_@G)3)@d}LVr
zdDlj7g-dE`SI3s&MHZ1atD7T3Z9gn<^UOD>j821wAhNmNp}I?#s{1Gj>p>(uBV&Cx
zzco)zBT^nhO>5bljLCNQ@AV88WN^DHNdG?ly>w>i0IuHc$6I-Lw7QUR=+&=}XWBcu
z=A_TP95B%Ra>calTPHF-@H%ht!ZTwfq^LcS52>-SS2
zV=kO@5-U4=lU?AbToD9&R3e2bwJmBG%)2&^63|vrt2(EedJnCoPd^kBgR8C7%nNf)
zgM$P?tjOFEle_N0(Zjk;LoJToaVrzvde1aWSlTQ61bwApmk-9OA{lf9Vi?C9C@Mpn
z-zFqIRPg#L_r16jb70W&vT1Lu6>PwIm5Rel-r}dIlOm5ycur_LXdk$Giu#ZndE9EZ
z`sm3HhSbW?fx#;o{htT)GNNp4nd|9H;Ik4SK<(0fZ
zLURJdit9TDc)yBlA-ThEy+!6x?H}tUWU7C?vfeCu9Vqn^;yI(YBt_v+OzXKX9~)=q
zZNW1|gh+`to*4}hzkhKlIPmw(Gp*r5L
zGs#5{%!8tGLs^3jkGjY~C%rsOx}{W?eh>djEcd86^HHnUfe3EOLkAJp`fsOvZ_}0(
z6T=(=sS5+L7fMNOJ?BVG1^&pc+7De-D~EtSLTG9D76}DvUTMHf09>?fNS0O1gP^q?
z$QG`-a-^BuaI1ALq=m_&Gz3&fGll;i+Nm!Q}qhkIN?=929Bf+7FIad2Y)3e?!i$VrS#UHM|!H
z(imrJtF%jrN7~oY%)IF>H~oyv)R8WBI%JL|_ffS(nOTD4sML#+>@P6Y3OsGUUyF)&
zn6c5)p~(~ust@nvpX*yg*djnN`H3Cy@Sh7tA-_Qg*&=$9k3W-uzMp-nU9RO);K*1`
z1QEIc<}4`P*^GDX(p~7WtZC2!X%gGaGdmN!_p9gmu5AbdRwU)}#w5sm%|dS}fxS0?
z5nUsIy)3G}EAli6%;~eg%bb3xHK@aA`_|(|w(M^>p_iR8d#06~x4KQt|_4f3>iFMaQ9S-PD!n>P^p;03!E|F^UK
z%Sp-ZAJpGHsFzuB4YojcVb>J%r1l=t4oNw($7}S5#Ew2M+ziZY3lFzReXycZL~smJ
z26P3=NWv1+w;@fMJv&9@=x3S(eN-cOyfx~Z+ACKJuIPi2zE*P_5=-7+m%EwgXYSFf
zU9_^Xcwm%Jqn@oquVooWkIJb06)>zWT0b_i-%+i`a9v#=^?Gnn)gh~1H#8FxlEPOD
z^AkVETF+E*?{c7F@wDLzRRxHUh60pMC$B_6uqKM@AyT
zRRx;H9CV{|J0iJWak0eMt{r*`6iyH=;Sg#uSMax#R3@?A#EGZBBqvR*#9YJ!<8Q{I1+^f%&*JVP9)q&4=Daz&s4
z;r=9Yt_=;McM7`WZ0$DWKm>tTd3Gy`NM?gx7=sZEpnKm3=D>zKNm#-U#O@x$O?vkU
zJ9*p)m~c%b#%?lBDL+vd2H!v(;a0|@9x
zI`__duO5au4p5c@zmjzI+TCr)o^h}OQQNJ9I_R$#(S8
z(7VP!cWrA)b^9xH$N32oNdZ8Jf7-LAp|vY>KhW*}@
z5`B=4c0!ehe}I$gNqw5Dq}Ob|Roc|rwNw0j)=8mH(~|vegiVEBw&Uqx(8}WBX=3Sm
zC0T9p1}n4+(c!PQa~iE5#qY3|ZOjdq1gA18N`n&}ZqVyESG+_wR;8o+QVq8tIl?kD
z!Q$6J9dO?D%zvf={Ez-DFMXZoF^P4&2Gsxg8In)g41HaqqZ)w9!V=TYfhIt3ly`Ku
z2K+uE?yvj(F97%M+3U+g9oVs3U9g!>K_WzpDZyXy^sAR3Z~a0yg9aS(@BG}^DB2oT
zS+uD@n{h=sTV)KX9-TW@+Ixw|&VlAIt5qYvw508bfz-%EkZAUsvEI^L`A$}~Z_2)0
zpXnyu!>PzkSdM=Xo_2UAw1&r@_Cl#u6uiZ>lvW0eM2j;H1s^sF^SMYhbqk&9$@{vb
z+bJw-BMYzj$w^mb@NPV(JnX{zmb*xX@2bAup~4+T4yoj!C7sTR{v8$x96e6B^Qv_G
z@KrB`cGO0kbbFA~kYB3jn=>t0msY2F^A{C!Q_Po#8nUKunFTm|DKI}urxa>%Q5P!G
zU2OC$-PELhG{JsH3Zap^aR-mq@3hI!7fGKA4|<&w&Yw0PCB#
zgb`hI-DoQblnVx!5jdfXp~S>lTs2-1_vZV;=kfW8(;^|_u1U0VJN2vo?oSSi&Z||5
zRJ{#Zd-l9sCxH_m<4W`b`3Dzx{yV#syZPuLo}%QOfO#byZBk@;em-1`bJjl(TtNVC1+EkIJzH$X5w|`
zIeRoHv48NHz+=hXExJEqXJhyGYM)B>`D0%){NIv^$MvsvHdYKSHGT{WIZAiA^Ar5I
NmKK#%S^M_De*k`{rojLJ

literal 0
HcmV?d00001

diff --git a/bsp/bl808/figures/bl808.jpg b/bsp/bouffalo_lab/figures/rt-thread.jpg
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/figures/bl808.jpg
rename to bsp/bouffalo_lab/figures/rt-thread.jpg
diff --git a/bsp/bouffalo_lab/libraries/Kconfig b/bsp/bouffalo_lab/libraries/Kconfig
new file mode 100755
index 0000000000..f9c6d3e44c
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/Kconfig
@@ -0,0 +1,2 @@
+source "$BSP_DIR/$LIBRARIES_DIR/rt_drivers/Kconfig"
+
diff --git a/bsp/bl808/m0/libraries/.ignore_format.yml b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/.ignore_format.yml
old mode 100644
new mode 100755
similarity index 90%
rename from bsp/bl808/m0/libraries/.ignore_format.yml
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/.ignore_format.yml
index 526edb3898..5ed52d4c4f
--- a/bsp/bl808/m0/libraries/.ignore_format.yml
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/.ignore_format.yml
@@ -3,6 +3,5 @@
 # If you need to exclude a file, add the path to the file in file_path.
 
 dir_path:
-- platform
-- stage
-- utils
\ No newline at end of file
+- drivers
+- tools
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/SConscript
new file mode 100755
index 0000000000..4c815c49b8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/SConscript
new file mode 100755
index 0000000000..4c815c49b8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/Doxyfile b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/Doxyfile
new file mode 100755
index 0000000000..40709eb270
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/Doxyfile
@@ -0,0 +1,2768 @@
+# Doxyfile 1.9.5
+
+# This file describes the settings to be used by the documentation system
+# doxygen (www.doxygen.org) for a project.
+#
+# All text after a double hash (##) is considered a comment and is placed in
+# front of the TAG it is preceding.
+#
+# All text after a single hash (#) is considered a comment and will be ignored.
+# The format is:
+# TAG = value [value, ...]
+# For lists, items can also be appended using:
+# TAG += value [value, ...]
+# Values that contain spaces should be placed between quotes (\" \").
+#
+# Note:
+#
+# Use doxygen to compare the used configuration file with the template
+# configuration file:
+# doxygen -x [configFile]
+# Use doxygen to compare the used configuration file with the template
+# configuration file without replacing the environment variables or CMake type
+# replacement variables:
+# doxygen -x_noenv [configFile]
+
+#---------------------------------------------------------------------------
+# Project related configuration options
+#---------------------------------------------------------------------------
+
+# This tag specifies the encoding used for all characters in the configuration
+# file that follow. The default is UTF-8 which is also the encoding used for all
+# text before the first occurrence of this tag. Doxygen uses libiconv (or the
+# iconv built into libc) for the transcoding. See
+# https://www.gnu.org/software/libiconv/ for the list of possible encodings.
+# The default value is: UTF-8.
+
+DOXYFILE_ENCODING      = UTF-8
+
+# The PROJECT_NAME tag is a single word (or a sequence of words surrounded by
+# double-quotes, unless you are using Doxywizard) that should identify the
+# project for which the documentation is generated. This name is used in the
+# title of most generated pages and in a few other places.
+# The default value is: My Project.
+
+PROJECT_NAME           = "LHAL Driver"
+
+# The PROJECT_NUMBER tag can be used to enter a project or revision number. This
+# could be handy for archiving the generated documentation or if some version
+# control system is used.
+
+PROJECT_NUMBER         = 1.0
+
+# Using the PROJECT_BRIEF tag one can provide an optional one line description
+# for a project that appears at the top of each page and should give viewer a
+# quick idea about the purpose of the project. Keep the description short.
+
+PROJECT_BRIEF          = "LHAL Drivers for bouffalolab Series MicroController"
+
+# With the PROJECT_LOGO tag one can specify a logo or an icon that is included
+# in the documentation. The maximum height of the logo should not exceed 55
+# pixels and the maximum width should not exceed 200 pixels. Doxygen will copy
+# the logo to the output directory.
+
+PROJECT_LOGO           =
+
+# The OUTPUT_DIRECTORY tag is used to specify the (relative or absolute) path
+# into which the generated documentation will be written. If a relative path is
+# entered, it will be relative to the location where doxygen was started. If
+# left blank the current directory will be used.
+
+OUTPUT_DIRECTORY       = doc
+
+# If the CREATE_SUBDIRS tag is set to YES then doxygen will create up to 4096
+# sub-directories (in 2 levels) under the output directory of each output format
+# and will distribute the generated files over these directories. Enabling this
+# option can be useful when feeding doxygen a huge amount of source files, where
+# putting all generated files in the same directory would otherwise causes
+# performance problems for the file system. Adapt CREATE_SUBDIRS_LEVEL to
+# control the number of sub-directories.
+# The default value is: NO.
+
+CREATE_SUBDIRS         = NO
+
+# Controls the number of sub-directories that will be created when
+# CREATE_SUBDIRS tag is set to YES. Level 0 represents 16 directories, and every
+# level increment doubles the number of directories, resulting in 4096
+# directories at level 8 which is the default and also the maximum value. The
+# sub-directories are organized in 2 levels, the first level always has a fixed
+# numer of 16 directories.
+# Minimum value: 0, maximum value: 8, default value: 8.
+# This tag requires that the tag CREATE_SUBDIRS is set to YES.
+
+CREATE_SUBDIRS_LEVEL   = 8
+
+# If the ALLOW_UNICODE_NAMES tag is set to YES, doxygen will allow non-ASCII
+# characters to appear in the names of generated files. If set to NO, non-ASCII
+# characters will be escaped, for example _xE3_x81_x84 will be used for Unicode
+# U+3044.
+# The default value is: NO.
+
+ALLOW_UNICODE_NAMES    = NO
+
+# The OUTPUT_LANGUAGE tag is used to specify the language in which all
+# documentation generated by doxygen is written. Doxygen will use this
+# information to generate all constant output in the proper language.
+# Possible values are: Afrikaans, Arabic, Armenian, Brazilian, Bulgarian,
+# Catalan, Chinese, Chinese-Traditional, Croatian, Czech, Danish, Dutch, English
+# (United States), Esperanto, Farsi (Persian), Finnish, French, German, Greek,
+# Hindi, Hungarian, Indonesian, Italian, Japanese, Japanese-en (Japanese with
+# English messages), Korean, Korean-en (Korean with English messages), Latvian,
+# Lithuanian, Macedonian, Norwegian, Persian (Farsi), Polish, Portuguese,
+# Romanian, Russian, Serbian, Serbian-Cyrillic, Slovak, Slovene, Spanish,
+# Swedish, Turkish, Ukrainian and Vietnamese.
+# The default value is: English.
+
+OUTPUT_LANGUAGE        = Chinese
+
+# If the BRIEF_MEMBER_DESC tag is set to YES, doxygen will include brief member
+# descriptions after the members that are listed in the file and class
+# documentation (similar to Javadoc). Set to NO to disable this.
+# The default value is: YES.
+
+BRIEF_MEMBER_DESC      = YES
+
+# If the REPEAT_BRIEF tag is set to YES, doxygen will prepend the brief
+# description of a member or function before the detailed description
+#
+# Note: If both HIDE_UNDOC_MEMBERS and BRIEF_MEMBER_DESC are set to NO, the
+# brief descriptions will be completely suppressed.
+# The default value is: YES.
+
+REPEAT_BRIEF           = YES
+
+# This tag implements a quasi-intelligent brief description abbreviator that is
+# used to form the text in various listings. Each string in this list, if found
+# as the leading text of the brief description, will be stripped from the text
+# and the result, after processing the whole list, is used as the annotated
+# text. Otherwise, the brief description is used as-is. If left blank, the
+# following values are used ($name is automatically replaced with the name of
+# the entity):The $name class, The $name widget, The $name file, is, provides,
+# specifies, contains, represents, a, an and the.
+
+ABBREVIATE_BRIEF       = "The $name class" \
+                         "The $name widget" \
+                         "The $name file" \
+                         is \
+                         provides \
+                         specifies \
+                         contains \
+                         represents \
+                         a \
+                         an \
+                         the
+
+# If the ALWAYS_DETAILED_SEC and REPEAT_BRIEF tags are both set to YES then
+# doxygen will generate a detailed section even if there is only a brief
+# description.
+# The default value is: NO.
+
+ALWAYS_DETAILED_SEC    = NO
+
+# If the INLINE_INHERITED_MEMB tag is set to YES, doxygen will show all
+# inherited members of a class in the documentation of that class as if those
+# members were ordinary class members. Constructors, destructors and assignment
+# operators of the base classes will not be shown.
+# The default value is: NO.
+
+INLINE_INHERITED_MEMB  = NO
+
+# If the FULL_PATH_NAMES tag is set to YES, doxygen will prepend the full path
+# before files name in the file list and in the header files. If set to NO the
+# shortest path that makes the file name unique will be used
+# The default value is: YES.
+
+FULL_PATH_NAMES        = YES
+
+# The STRIP_FROM_PATH tag can be used to strip a user-defined part of the path.
+# Stripping is only done if one of the specified strings matches the left-hand
+# part of the path. The tag can be used to show relative paths in the file list.
+# If left blank the directory from which doxygen is run is used as the path to
+# strip.
+#
+# Note that you can specify absolute paths here, but also relative paths, which
+# will be relative from the directory where doxygen is started.
+# This tag requires that the tag FULL_PATH_NAMES is set to YES.
+
+STRIP_FROM_PATH        =
+
+# The STRIP_FROM_INC_PATH tag can be used to strip a user-defined part of the
+# path mentioned in the documentation of a class, which tells the reader which
+# header file to include in order to use a class. If left blank only the name of
+# the header file containing the class definition is used. Otherwise one should
+# specify the list of include paths that are normally passed to the compiler
+# using the -I flag.
+
+STRIP_FROM_INC_PATH    =
+
+# If the SHORT_NAMES tag is set to YES, doxygen will generate much shorter (but
+# less readable) file names. This can be useful is your file systems doesn't
+# support long names like on DOS, Mac, or CD-ROM.
+# The default value is: NO.
+
+SHORT_NAMES            = NO
+
+# If the JAVADOC_AUTOBRIEF tag is set to YES then doxygen will interpret the
+# first line (until the first dot) of a Javadoc-style comment as the brief
+# description. If set to NO, the Javadoc-style will behave just like regular Qt-
+# style comments (thus requiring an explicit @brief command for a brief
+# description.)
+# The default value is: NO.
+
+JAVADOC_AUTOBRIEF      = NO
+
+# If the JAVADOC_BANNER tag is set to YES then doxygen will interpret a line
+# such as
+# /***************
+# as being the beginning of a Javadoc-style comment "banner". If set to NO, the
+# Javadoc-style will behave just like regular comments and it will not be
+# interpreted by doxygen.
+# The default value is: NO.
+
+JAVADOC_BANNER         = NO
+
+# If the QT_AUTOBRIEF tag is set to YES then doxygen will interpret the first
+# line (until the first dot) of a Qt-style comment as the brief description. If
+# set to NO, the Qt-style will behave just like regular Qt-style comments (thus
+# requiring an explicit \brief command for a brief description.)
+# The default value is: NO.
+
+QT_AUTOBRIEF           = NO
+
+# The MULTILINE_CPP_IS_BRIEF tag can be set to YES to make doxygen treat a
+# multi-line C++ special comment block (i.e. a block of //! or /// comments) as
+# a brief description. This used to be the default behavior. The new default is
+# to treat a multi-line C++ comment block as a detailed description. Set this
+# tag to YES if you prefer the old behavior instead.
+#
+# Note that setting this tag to YES also means that rational rose comments are
+# not recognized any more.
+# The default value is: NO.
+
+MULTILINE_CPP_IS_BRIEF = NO
+
+# By default Python docstrings are displayed as preformatted text and doxygen's
+# special commands cannot be used. By setting PYTHON_DOCSTRING to NO the
+# doxygen's special commands can be used and the contents of the docstring
+# documentation blocks is shown as doxygen documentation.
+# The default value is: YES.
+
+PYTHON_DOCSTRING       = YES
+
+# If the INHERIT_DOCS tag is set to YES then an undocumented member inherits the
+# documentation from any documented member that it re-implements.
+# The default value is: YES.
+
+INHERIT_DOCS           = YES
+
+# If the SEPARATE_MEMBER_PAGES tag is set to YES then doxygen will produce a new
+# page for each member. If set to NO, the documentation of a member will be part
+# of the file/class/namespace that contains it.
+# The default value is: NO.
+
+SEPARATE_MEMBER_PAGES  = NO
+
+# The TAB_SIZE tag can be used to set the number of spaces in a tab. Doxygen
+# uses this value to replace tabs by spaces in code fragments.
+# Minimum value: 1, maximum value: 16, default value: 4.
+
+TAB_SIZE               = 4
+
+# This tag can be used to specify a number of aliases that act as commands in
+# the documentation. An alias has the form:
+# name=value
+# For example adding
+# "sideeffect=@par Side Effects:^^"
+# will allow you to put the command \sideeffect (or @sideeffect) in the
+# documentation, which will result in a user-defined paragraph with heading
+# "Side Effects:". Note that you cannot put \n's in the value part of an alias
+# to insert newlines (in the resulting output). You can put ^^ in the value part
+# of an alias to insert a newline as if a physical newline was in the original
+# file. When you need a literal { or } or , in the value part of an alias you
+# have to escape them by means of a backslash (\), this can lead to conflicts
+# with the commands \{ and \} for these it is advised to use the version @{ and
+# @} or use a double escape (\\{ and \\})
+
+ALIASES                =
+
+# Set the OPTIMIZE_OUTPUT_FOR_C tag to YES if your project consists of C sources
+# only. Doxygen will then generate output that is more tailored for C. For
+# instance, some of the names that are used will be different. The list of all
+# members will be omitted, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_FOR_C  = YES
+
+# Set the OPTIMIZE_OUTPUT_JAVA tag to YES if your project consists of Java or
+# Python sources only. Doxygen will then generate output that is more tailored
+# for that language. For instance, namespaces will be presented as packages,
+# qualified scopes will look different, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_JAVA   = NO
+
+# Set the OPTIMIZE_FOR_FORTRAN tag to YES if your project consists of Fortran
+# sources. Doxygen will then generate output that is tailored for Fortran.
+# The default value is: NO.
+
+OPTIMIZE_FOR_FORTRAN   = NO
+
+# Set the OPTIMIZE_OUTPUT_VHDL tag to YES if your project consists of VHDL
+# sources. Doxygen will then generate output that is tailored for VHDL.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_VHDL   = NO
+
+# Set the OPTIMIZE_OUTPUT_SLICE tag to YES if your project consists of Slice
+# sources only. Doxygen will then generate output that is more tailored for that
+# language. For instance, namespaces will be presented as modules, types will be
+# separated into more groups, etc.
+# The default value is: NO.
+
+OPTIMIZE_OUTPUT_SLICE  = NO
+
+# Doxygen selects the parser to use depending on the extension of the files it
+# parses. With this tag you can assign which parser to use for a given
+# extension. Doxygen has a built-in mapping, but you can override or extend it
+# using this tag. The format is ext=language, where ext is a file extension, and
+# language is one of the parsers supported by doxygen: IDL, Java, JavaScript,
+# Csharp (C#), C, C++, Lex, D, PHP, md (Markdown), Objective-C, Python, Slice,
+# VHDL, Fortran (fixed format Fortran: FortranFixed, free formatted Fortran:
+# FortranFree, unknown formatted Fortran: Fortran. In the later case the parser
+# tries to guess whether the code is fixed or free formatted code, this is the
+# default for Fortran type files). For instance to make doxygen treat .inc files
+# as Fortran files (default is PHP), and .f files as C (default is Fortran),
+# use: inc=Fortran f=C.
+#
+# Note: For files without extension you can use no_extension as a placeholder.
+#
+# Note that for custom extensions you also need to set FILE_PATTERNS otherwise
+# the files are not read by doxygen. When specifying no_extension you should add
+# * to the FILE_PATTERNS.
+#
+# Note see also the list of default file extension mappings.
+
+EXTENSION_MAPPING      =
+
+# If the MARKDOWN_SUPPORT tag is enabled then doxygen pre-processes all comments
+# according to the Markdown format, which allows for more readable
+# documentation. See https://daringfireball.net/projects/markdown/ for details.
+# The output of markdown processing is further processed by doxygen, so you can
+# mix doxygen, HTML, and XML commands with Markdown formatting. Disable only in
+# case of backward compatibilities issues.
+# The default value is: YES.
+
+MARKDOWN_SUPPORT       = YES
+
+# When the TOC_INCLUDE_HEADINGS tag is set to a non-zero value, all headings up
+# to that level are automatically included in the table of contents, even if
+# they do not have an id attribute.
+# Note: This feature currently applies only to Markdown headings.
+# Minimum value: 0, maximum value: 99, default value: 5.
+# This tag requires that the tag MARKDOWN_SUPPORT is set to YES.
+
+TOC_INCLUDE_HEADINGS   = 5
+
+# When enabled doxygen tries to link words that correspond to documented
+# classes, or namespaces to their corresponding documentation. Such a link can
+# be prevented in individual cases by putting a % sign in front of the word or
+# globally by setting AUTOLINK_SUPPORT to NO.
+# The default value is: YES.
+
+AUTOLINK_SUPPORT       = YES
+
+# If you use STL classes (i.e. std::string, std::vector, etc.) but do not want
+# to include (a tag file for) the STL sources as input, then you should set this
+# tag to YES in order to let doxygen match functions declarations and
+# definitions whose arguments contain STL classes (e.g. func(std::string);
+# versus func(std::string) {}). This also make the inheritance and collaboration
+# diagrams that involve STL classes more complete and accurate.
+# The default value is: NO.
+
+BUILTIN_STL_SUPPORT    = NO
+
+# If you use Microsoft's C++/CLI language, you should set this option to YES to
+# enable parsing support.
+# The default value is: NO.
+
+CPP_CLI_SUPPORT        = NO
+
+# Set the SIP_SUPPORT tag to YES if your project consists of sip (see:
+# https://www.riverbankcomputing.com/software/sip/intro) sources only. Doxygen
+# will parse them like normal C++ but will assume all classes use public instead
+# of private inheritance when no explicit protection keyword is present.
+# The default value is: NO.
+
+SIP_SUPPORT            = NO
+
+# For Microsoft's IDL there are propget and propput attributes to indicate
+# getter and setter methods for a property. Setting this option to YES will make
+# doxygen to replace the get and set methods by a property in the documentation.
+# This will only work if the methods are indeed getting or setting a simple
+# type. If this is not the case, or you want to show the methods anyway, you
+# should set this option to NO.
+# The default value is: YES.
+
+IDL_PROPERTY_SUPPORT   = YES
+
+# If member grouping is used in the documentation and the DISTRIBUTE_GROUP_DOC
+# tag is set to YES then doxygen will reuse the documentation of the first
+# member in the group (if any) for the other members of the group. By default
+# all members of a group must be documented explicitly.
+# The default value is: NO.
+
+DISTRIBUTE_GROUP_DOC   = NO
+
+# If one adds a struct or class to a group and this option is enabled, then also
+# any nested class or struct is added to the same group. By default this option
+# is disabled and one has to add nested compounds explicitly via \ingroup.
+# The default value is: NO.
+
+GROUP_NESTED_COMPOUNDS = NO
+
+# Set the SUBGROUPING tag to YES to allow class member groups of the same type
+# (for instance a group of public functions) to be put as a subgroup of that
+# type (e.g. under the Public Functions section). Set it to NO to prevent
+# subgrouping. Alternatively, this can be done per class using the
+# \nosubgrouping command.
+# The default value is: YES.
+
+SUBGROUPING            = YES
+
+# When the INLINE_GROUPED_CLASSES tag is set to YES, classes, structs and unions
+# are shown inside the group in which they are included (e.g. using \ingroup)
+# instead of on a separate page (for HTML and Man pages) or section (for LaTeX
+# and RTF).
+#
+# Note that this feature does not work in combination with
+# SEPARATE_MEMBER_PAGES.
+# The default value is: NO.
+
+INLINE_GROUPED_CLASSES = NO
+
+# When the INLINE_SIMPLE_STRUCTS tag is set to YES, structs, classes, and unions
+# with only public data fields or simple typedef fields will be shown inline in
+# the documentation of the scope in which they are defined (i.e. file,
+# namespace, or group documentation), provided this scope is documented. If set
+# to NO, structs, classes, and unions are shown on a separate page (for HTML and
+# Man pages) or section (for LaTeX and RTF).
+# The default value is: NO.
+
+INLINE_SIMPLE_STRUCTS  = NO
+
+# When TYPEDEF_HIDES_STRUCT tag is enabled, a typedef of a struct, union, or
+# enum is documented as struct, union, or enum with the name of the typedef. So
+# typedef struct TypeS {} TypeT, will appear in the documentation as a struct
+# with name TypeT. When disabled the typedef will appear as a member of a file,
+# namespace, or class. And the struct will be named TypeS. This can typically be
+# useful for C code in case the coding convention dictates that all compound
+# types are typedef'ed and only the typedef is referenced, never the tag name.
+# The default value is: NO.
+
+TYPEDEF_HIDES_STRUCT   = NO
+
+# The size of the symbol lookup cache can be set using LOOKUP_CACHE_SIZE. This
+# cache is used to resolve symbols given their name and scope. Since this can be
+# an expensive process and often the same symbol appears multiple times in the
+# code, doxygen keeps a cache of pre-resolved symbols. If the cache is too small
+# doxygen will become slower. If the cache is too large, memory is wasted. The
+# cache size is given by this formula: 2^(16+LOOKUP_CACHE_SIZE). The valid range
+# is 0..9, the default is 0, corresponding to a cache size of 2^16=65536
+# symbols. At the end of a run doxygen will report the cache usage and suggest
+# the optimal cache size from a speed point of view.
+# Minimum value: 0, maximum value: 9, default value: 0.
+
+LOOKUP_CACHE_SIZE      = 0
+
+# The NUM_PROC_THREADS specifies the number of threads doxygen is allowed to use
+# during processing. When set to 0 doxygen will based this on the number of
+# cores available in the system. You can set it explicitly to a value larger
+# than 0 to get more control over the balance between CPU load and processing
+# speed. At this moment only the input processing can be done using multiple
+# threads. Since this is still an experimental feature the default is set to 1,
+# which effectively disables parallel processing. Please report any issues you
+# encounter. Generating dot graphs in parallel is controlled by the
+# DOT_NUM_THREADS setting.
+# Minimum value: 0, maximum value: 32, default value: 1.
+
+NUM_PROC_THREADS       = 1
+
+#---------------------------------------------------------------------------
+# Build related configuration options
+#---------------------------------------------------------------------------
+
+# If the EXTRACT_ALL tag is set to YES, doxygen will assume all entities in
+# documentation are documented, even if no documentation was available. Private
+# class members and static file members will be hidden unless the
+# EXTRACT_PRIVATE respectively EXTRACT_STATIC tags are set to YES.
+# Note: This will also disable the warnings about undocumented members that are
+# normally produced when WARNINGS is set to YES.
+# The default value is: NO.
+
+EXTRACT_ALL            = YES
+
+# If the EXTRACT_PRIVATE tag is set to YES, all private members of a class will
+# be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIVATE        = YES
+
+# If the EXTRACT_PRIV_VIRTUAL tag is set to YES, documented private virtual
+# methods of a class will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PRIV_VIRTUAL   = YES
+
+# If the EXTRACT_PACKAGE tag is set to YES, all members with package or internal
+# scope will be included in the documentation.
+# The default value is: NO.
+
+EXTRACT_PACKAGE        = YES
+
+# If the EXTRACT_STATIC tag is set to YES, all static members of a file will be
+# included in the documentation.
+# The default value is: NO.
+
+EXTRACT_STATIC         = YES
+
+# If the EXTRACT_LOCAL_CLASSES tag is set to YES, classes (and structs) defined
+# locally in source files will be included in the documentation. If set to NO,
+# only classes defined in header files are included. Does not have any effect
+# for Java sources.
+# The default value is: YES.
+
+EXTRACT_LOCAL_CLASSES  = YES
+
+# This flag is only useful for Objective-C code. If set to YES, local methods,
+# which are defined in the implementation section but not in the interface are
+# included in the documentation. If set to NO, only methods in the interface are
+# included.
+# The default value is: NO.
+
+EXTRACT_LOCAL_METHODS  = NO
+
+# If this flag is set to YES, the members of anonymous namespaces will be
+# extracted and appear in the documentation as a namespace called
+# 'anonymous_namespace{file}', where file will be replaced with the base name of
+# the file that contains the anonymous namespace. By default anonymous namespace
+# are hidden.
+# The default value is: NO.
+
+EXTRACT_ANON_NSPACES   = NO
+
+# If this flag is set to YES, the name of an unnamed parameter in a declaration
+# will be determined by the corresponding definition. By default unnamed
+# parameters remain unnamed in the output.
+# The default value is: YES.
+
+RESOLVE_UNNAMED_PARAMS = YES
+
+# If the HIDE_UNDOC_MEMBERS tag is set to YES, doxygen will hide all
+# undocumented members inside documented classes or files. If set to NO these
+# members will be included in the various overviews, but no documentation
+# section is generated. This option has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_MEMBERS     = NO
+
+# If the HIDE_UNDOC_CLASSES tag is set to YES, doxygen will hide all
+# undocumented classes that are normally visible in the class hierarchy. If set
+# to NO, these classes will be included in the various overviews. This option
+# has no effect if EXTRACT_ALL is enabled.
+# The default value is: NO.
+
+HIDE_UNDOC_CLASSES     = NO
+
+# If the HIDE_FRIEND_COMPOUNDS tag is set to YES, doxygen will hide all friend
+# declarations. If set to NO, these declarations will be included in the
+# documentation.
+# The default value is: NO.
+
+HIDE_FRIEND_COMPOUNDS  = NO
+
+# If the HIDE_IN_BODY_DOCS tag is set to YES, doxygen will hide any
+# documentation blocks found inside the body of a function. If set to NO, these
+# blocks will be appended to the function's detailed documentation block.
+# The default value is: NO.
+
+HIDE_IN_BODY_DOCS      = NO
+
+# The INTERNAL_DOCS tag determines if documentation that is typed after a
+# \internal command is included. If the tag is set to NO then the documentation
+# will be excluded. Set it to YES to include the internal documentation.
+# The default value is: NO.
+
+INTERNAL_DOCS          = NO
+
+# With the correct setting of option CASE_SENSE_NAMES doxygen will better be
+# able to match the capabilities of the underlying filesystem. In case the
+# filesystem is case sensitive (i.e. it supports files in the same directory
+# whose names only differ in casing), the option must be set to YES to properly
+# deal with such files in case they appear in the input. For filesystems that
+# are not case sensitive the option should be set to NO to properly deal with
+# output files written for symbols that only differ in casing, such as for two
+# classes, one named CLASS and the other named Class, and to also support
+# references to files without having to specify the exact matching casing. On
+# Windows (including Cygwin) and MacOS, users should typically set this option
+# to NO, whereas on Linux or other Unix flavors it should typically be set to
+# YES.
+# Possible values are: SYSTEM, NO and YES.
+# The default value is: SYSTEM.
+
+CASE_SENSE_NAMES       = NO
+
+# If the HIDE_SCOPE_NAMES tag is set to NO then doxygen will show members with
+# their full class and namespace scopes in the documentation. If set to YES, the
+# scope will be hidden.
+# The default value is: NO.
+
+HIDE_SCOPE_NAMES       = YES
+
+# If the HIDE_COMPOUND_REFERENCE tag is set to NO (default) then doxygen will
+# append additional text to a page's title, such as Class Reference. If set to
+# YES the compound reference will be hidden.
+# The default value is: NO.
+
+HIDE_COMPOUND_REFERENCE= NO
+
+# If the SHOW_HEADERFILE tag is set to YES then the documentation for a class
+# will show which file needs to be included to use the class.
+# The default value is: YES.
+
+SHOW_HEADERFILE        = YES
+
+# If the SHOW_INCLUDE_FILES tag is set to YES then doxygen will put a list of
+# the files that are included by a file in the documentation of that file.
+# The default value is: YES.
+
+SHOW_INCLUDE_FILES     = YES
+
+# If the SHOW_GROUPED_MEMB_INC tag is set to YES then Doxygen will add for each
+# grouped member an include statement to the documentation, telling the reader
+# which file to include in order to use the member.
+# The default value is: NO.
+
+SHOW_GROUPED_MEMB_INC  = NO
+
+# If the FORCE_LOCAL_INCLUDES tag is set to YES then doxygen will list include
+# files with double quotes in the documentation rather than with sharp brackets.
+# The default value is: NO.
+
+FORCE_LOCAL_INCLUDES   = NO
+
+# If the INLINE_INFO tag is set to YES then a tag [inline] is inserted in the
+# documentation for inline members.
+# The default value is: YES.
+
+INLINE_INFO            = YES
+
+# If the SORT_MEMBER_DOCS tag is set to YES then doxygen will sort the
+# (detailed) documentation of file and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order.
+# The default value is: YES.
+
+SORT_MEMBER_DOCS       = YES
+
+# If the SORT_BRIEF_DOCS tag is set to YES then doxygen will sort the brief
+# descriptions of file, namespace and class members alphabetically by member
+# name. If set to NO, the members will appear in declaration order. Note that
+# this will also influence the order of the classes in the class list.
+# The default value is: NO.
+
+SORT_BRIEF_DOCS        = NO
+
+# If the SORT_MEMBERS_CTORS_1ST tag is set to YES then doxygen will sort the
+# (brief and detailed) documentation of class members so that constructors and
+# destructors are listed first. If set to NO the constructors will appear in the
+# respective orders defined by SORT_BRIEF_DOCS and SORT_MEMBER_DOCS.
+# Note: If SORT_BRIEF_DOCS is set to NO this option is ignored for sorting brief
+# member documentation.
+# Note: If SORT_MEMBER_DOCS is set to NO this option is ignored for sorting
+# detailed member documentation.
+# The default value is: NO.
+
+SORT_MEMBERS_CTORS_1ST = NO
+
+# If the SORT_GROUP_NAMES tag is set to YES then doxygen will sort the hierarchy
+# of group names into alphabetical order. If set to NO the group names will
+# appear in their defined order.
+# The default value is: NO.
+
+SORT_GROUP_NAMES       = NO
+
+# If the SORT_BY_SCOPE_NAME tag is set to YES, the class list will be sorted by
+# fully-qualified names, including namespaces. If set to NO, the class list will
+# be sorted only by class name, not including the namespace part.
+# Note: This option is not very useful if HIDE_SCOPE_NAMES is set to YES.
+# Note: This option applies only to the class list, not to the alphabetical
+# list.
+# The default value is: NO.
+
+SORT_BY_SCOPE_NAME     = NO
+
+# If the STRICT_PROTO_MATCHING option is enabled and doxygen fails to do proper
+# type resolution of all parameters of a function it will reject a match between
+# the prototype and the implementation of a member function even if there is
+# only one candidate or it is obvious which candidate to choose by doing a
+# simple string match. By disabling STRICT_PROTO_MATCHING doxygen will still
+# accept a match between prototype and implementation in such cases.
+# The default value is: NO.
+
+STRICT_PROTO_MATCHING  = NO
+
+# The GENERATE_TODOLIST tag can be used to enable (YES) or disable (NO) the todo
+# list. This list is created by putting \todo commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TODOLIST      = YES
+
+# The GENERATE_TESTLIST tag can be used to enable (YES) or disable (NO) the test
+# list. This list is created by putting \test commands in the documentation.
+# The default value is: YES.
+
+GENERATE_TESTLIST      = YES
+
+# The GENERATE_BUGLIST tag can be used to enable (YES) or disable (NO) the bug
+# list. This list is created by putting \bug commands in the documentation.
+# The default value is: YES.
+
+GENERATE_BUGLIST       = YES
+
+# The GENERATE_DEPRECATEDLIST tag can be used to enable (YES) or disable (NO)
+# the deprecated list. This list is created by putting \deprecated commands in
+# the documentation.
+# The default value is: YES.
+
+GENERATE_DEPRECATEDLIST= YES
+
+# The ENABLED_SECTIONS tag can be used to enable conditional documentation
+# sections, marked by \if  ... \endif and \cond 
+# ... \endcond blocks.
+
+ENABLED_SECTIONS       =
+
+# The MAX_INITIALIZER_LINES tag determines the maximum number of lines that the
+# initial value of a variable or macro / define can have for it to appear in the
+# documentation. If the initializer consists of more lines than specified here
+# it will be hidden. Use a value of 0 to hide initializers completely. The
+# appearance of the value of individual variables and macros / defines can be
+# controlled using \showinitializer or \hideinitializer command in the
+# documentation regardless of this setting.
+# Minimum value: 0, maximum value: 10000, default value: 30.
+
+MAX_INITIALIZER_LINES  = 30
+
+# Set the SHOW_USED_FILES tag to NO to disable the list of files generated at
+# the bottom of the documentation of classes and structs. If set to YES, the
+# list will mention the files that were used to generate the documentation.
+# The default value is: YES.
+
+SHOW_USED_FILES        = YES
+
+# Set the SHOW_FILES tag to NO to disable the generation of the Files page. This
+# will remove the Files entry from the Quick Index and from the Folder Tree View
+# (if specified).
+# The default value is: YES.
+
+SHOW_FILES             = YES
+
+# Set the SHOW_NAMESPACES tag to NO to disable the generation of the Namespaces
+# page. This will remove the Namespaces entry from the Quick Index and from the
+# Folder Tree View (if specified).
+# The default value is: YES.
+
+SHOW_NAMESPACES        = YES
+
+# The FILE_VERSION_FILTER tag can be used to specify a program or script that
+# doxygen should invoke to get the current version for each file (typically from
+# the version control system). Doxygen will invoke the program by executing (via
+# popen()) the command command input-file, where command is the value of the
+# FILE_VERSION_FILTER tag, and input-file is the name of an input file provided
+# by doxygen. Whatever the program writes to standard output is used as the file
+# version. For an example see the documentation.
+
+FILE_VERSION_FILTER    =
+
+# The LAYOUT_FILE tag can be used to specify a layout file which will be parsed
+# by doxygen. The layout file controls the global structure of the generated
+# output files in an output format independent way. To create the layout file
+# that represents doxygen's defaults, run doxygen with the -l option. You can
+# optionally specify a file name after the option, if omitted DoxygenLayout.xml
+# will be used as the name of the layout file. See also section "Changing the
+# layout of pages" for information.
+#
+# Note that if you run doxygen from a directory containing a file called
+# DoxygenLayout.xml, doxygen will parse it automatically even if the LAYOUT_FILE
+# tag is left empty.
+
+LAYOUT_FILE            =
+
+# The CITE_BIB_FILES tag can be used to specify one or more bib files containing
+# the reference definitions. This must be a list of .bib files. The .bib
+# extension is automatically appended if omitted. This requires the bibtex tool
+# to be installed. See also https://en.wikipedia.org/wiki/BibTeX for more info.
+# For LaTeX the style of the bibliography can be controlled using
+# LATEX_BIB_STYLE. To use this feature you need bibtex and perl available in the
+# search path. See also \cite for info how to create references.
+
+CITE_BIB_FILES         =
+
+#---------------------------------------------------------------------------
+# Configuration options related to warning and progress messages
+#---------------------------------------------------------------------------
+
+# The QUIET tag can be used to turn on/off the messages that are generated to
+# standard output by doxygen. If QUIET is set to YES this implies that the
+# messages are off.
+# The default value is: NO.
+
+QUIET                  = NO
+
+# The WARNINGS tag can be used to turn on/off the warning messages that are
+# generated to standard error (stderr) by doxygen. If WARNINGS is set to YES
+# this implies that the warnings are on.
+#
+# Tip: Turn warnings on while writing the documentation.
+# The default value is: YES.
+
+WARNINGS               = YES
+
+# If the WARN_IF_UNDOCUMENTED tag is set to YES then doxygen will generate
+# warnings for undocumented members. If EXTRACT_ALL is set to YES then this flag
+# will automatically be disabled.
+# The default value is: YES.
+
+WARN_IF_UNDOCUMENTED   = YES
+
+# If the WARN_IF_DOC_ERROR tag is set to YES, doxygen will generate warnings for
+# potential errors in the documentation, such as documenting some parameters in
+# a documented function twice, or documenting parameters that don't exist or
+# using markup commands wrongly.
+# The default value is: YES.
+
+WARN_IF_DOC_ERROR      = YES
+
+# If WARN_IF_INCOMPLETE_DOC is set to YES, doxygen will warn about incomplete
+# function parameter documentation. If set to NO, doxygen will accept that some
+# parameters have no documentation without warning.
+# The default value is: YES.
+
+WARN_IF_INCOMPLETE_DOC = YES
+
+# This WARN_NO_PARAMDOC option can be enabled to get warnings for functions that
+# are documented, but have no documentation for their parameters or return
+# value. If set to NO, doxygen will only warn about wrong parameter
+# documentation, but not about the absence of documentation. If EXTRACT_ALL is
+# set to YES then this flag will automatically be disabled. See also
+# WARN_IF_INCOMPLETE_DOC
+# The default value is: NO.
+
+WARN_NO_PARAMDOC       = NO
+
+# If the WARN_AS_ERROR tag is set to YES then doxygen will immediately stop when
+# a warning is encountered. If the WARN_AS_ERROR tag is set to FAIL_ON_WARNINGS
+# then doxygen will continue running as if WARN_AS_ERROR tag is set to NO, but
+# at the end of the doxygen process doxygen will return with a non-zero status.
+# Possible values are: NO, YES and FAIL_ON_WARNINGS.
+# The default value is: NO.
+
+WARN_AS_ERROR          = NO
+
+# The WARN_FORMAT tag determines the format of the warning messages that doxygen
+# can produce. The string should contain the $file, $line, and $text tags, which
+# will be replaced by the file and line number from which the warning originated
+# and the warning text. Optionally the format may contain $version, which will
+# be replaced by the version of the file (if it could be obtained via
+# FILE_VERSION_FILTER)
+# See also: WARN_LINE_FORMAT
+# The default value is: $file:$line: $text.
+
+WARN_FORMAT            = "$file:$line: $text"
+
+# In the $text part of the WARN_FORMAT command it is possible that a reference
+# to a more specific place is given. To make it easier to jump to this place
+# (outside of doxygen) the user can define a custom "cut" / "paste" string.
+# Example:
+# WARN_LINE_FORMAT = "'vi $file +$line'"
+# See also: WARN_FORMAT
+# The default value is: at line $line of file $file.
+
+WARN_LINE_FORMAT       = "at line $line of file $file"
+
+# The WARN_LOGFILE tag can be used to specify a file to which warning and error
+# messages should be written. If left blank the output is written to standard
+# error (stderr). In case the file specified cannot be opened for writing the
+# warning and error messages are written to standard error. When as file - is
+# specified the warning and error messages are written to standard output
+# (stdout).
+
+WARN_LOGFILE           =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the input files
+#---------------------------------------------------------------------------
+
+# The INPUT tag is used to specify the files and/or directories that contain
+# documented source files. You may enter file names like myfile.cpp or
+# directories like /usr/src/myproject. Separate the files or directories with
+# spaces. See also FILE_PATTERNS and EXTENSION_MAPPING
+# Note: If this tag is empty the current directory is searched.
+
+INPUT                  = include
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses. Internally doxygen uses the UTF-8 encoding. Doxygen uses
+# libiconv (or the iconv built into libc) for the transcoding. See the libiconv
+# documentation (see:
+# https://www.gnu.org/software/libiconv/) for the list of possible encodings.
+# See also: INPUT_FILE_ENCODING
+# The default value is: UTF-8.
+
+INPUT_ENCODING         = UTF-8
+
+# This tag can be used to specify the character encoding of the source files
+# that doxygen parses The INPUT_FILE_ENCODING tag can be used to specify
+# character encoding on a per file pattern basis. Doxygen will compare the file
+# name with each pattern and apply the encoding instead of the default
+# INPUT_ENCODING) if there is a match. The character encodings are a list of the
+# form: pattern=encoding (like *.php=ISO-8859-1). See cfg_input_encoding
+# "INPUT_ENCODING" for further information on supported encodings.
+
+INPUT_FILE_ENCODING    =
+
+# If the value of the INPUT tag contains directories, you can use the
+# FILE_PATTERNS tag to specify one or more wildcard patterns (like *.cpp and
+# *.h) to filter out the source-files in the directories.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# read by doxygen.
+#
+# Note the list of default checked file patterns might differ from the list of
+# default file extension mappings.
+#
+# If left blank the following patterns are tested:*.c, *.cc, *.cxx, *.cpp,
+# *.c++, *.java, *.ii, *.ixx, *.ipp, *.i++, *.inl, *.idl, *.ddl, *.odl, *.h,
+# *.hh, *.hxx, *.hpp, *.h++, *.l, *.cs, *.d, *.php, *.php4, *.php5, *.phtml,
+# *.inc, *.m, *.markdown, *.md, *.mm, *.dox (to be provided as doxygen C
+# comment), *.py, *.pyw, *.f90, *.f95, *.f03, *.f08, *.f18, *.f, *.for, *.vhd,
+# *.vhdl, *.ucf, *.qsf and *.ice.
+
+FILE_PATTERNS          = *.c \
+                         *.cc \
+                         *.cxx \
+                         *.cpp \
+                         *.c++ \
+                         *.java \
+                         *.ii \
+                         *.ixx \
+                         *.ipp \
+                         *.i++ \
+                         *.inl \
+                         *.idl \
+                         *.ddl \
+                         *.odl \
+                         *.h \
+                         *.hh \
+                         *.hxx \
+                         *.hpp \
+                         *.h++ \
+                         *.cs \
+                         *.d \
+                         *.php \
+                         *.php4 \
+                         *.php5 \
+                         *.phtml \
+                         *.inc \
+                         *.m \
+                         *.markdown \
+                         *.md \
+                         *.mm \
+                         *.dox \
+                         *.py \
+                         *.pyw \
+                         *.f90 \
+                         *.f95 \
+                         *.f03 \
+                         *.f08 \
+                         *.f18 \
+                         *.f \
+                         *.for \
+                         *.vhd \
+                         *.vhdl \
+                         *.ucf \
+                         *.qsf \
+                         *.ice
+
+# The RECURSIVE tag can be used to specify whether or not subdirectories should
+# be searched for input files as well.
+# The default value is: NO.
+
+RECURSIVE              = NO
+
+# The EXCLUDE tag can be used to specify files and/or directories that should be
+# excluded from the INPUT source files. This way you can easily exclude a
+# subdirectory from a directory tree whose root is specified with the INPUT tag.
+#
+# Note that relative paths are relative to the directory from which doxygen is
+# run.
+
+EXCLUDE                =
+
+# The EXCLUDE_SYMLINKS tag can be used to select whether or not files or
+# directories that are symbolic links (a Unix file system feature) are excluded
+# from the input.
+# The default value is: NO.
+
+EXCLUDE_SYMLINKS       = NO
+
+# If the value of the INPUT tag contains directories, you can use the
+# EXCLUDE_PATTERNS tag to specify one or more wildcard patterns to exclude
+# certain files from those directories.
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories for example use the pattern */test/*
+
+EXCLUDE_PATTERNS       =
+
+# The EXCLUDE_SYMBOLS tag can be used to specify one or more symbol names
+# (namespaces, classes, functions, etc.) that should be excluded from the
+# output. The symbol name can be a fully qualified name, a word, or if the
+# wildcard * is used, a substring. Examples: ANamespace, AClass,
+# ANamespace::AClass, ANamespace::*Test
+#
+# Note that the wildcards are matched against the file with absolute path, so to
+# exclude all test directories use the pattern */test/*
+
+EXCLUDE_SYMBOLS        =
+
+# The EXAMPLE_PATH tag can be used to specify one or more files or directories
+# that contain example code fragments that are included (see the \include
+# command).
+
+EXAMPLE_PATH           =
+
+# If the value of the EXAMPLE_PATH tag contains directories, you can use the
+# EXAMPLE_PATTERNS tag to specify one or more wildcard pattern (like *.cpp and
+# *.h) to filter out the source-files in the directories. If left blank all
+# files are included.
+
+EXAMPLE_PATTERNS       = *
+
+# If the EXAMPLE_RECURSIVE tag is set to YES then subdirectories will be
+# searched for input files to be used with the \include or \dontinclude commands
+# irrespective of the value of the RECURSIVE tag.
+# The default value is: NO.
+
+EXAMPLE_RECURSIVE      = NO
+
+# The IMAGE_PATH tag can be used to specify one or more files or directories
+# that contain images that are to be included in the documentation (see the
+# \image command).
+
+IMAGE_PATH             =
+
+# The INPUT_FILTER tag can be used to specify a program that doxygen should
+# invoke to filter for each input file. Doxygen will invoke the filter program
+# by executing (via popen()) the command:
+#
+#  
+#
+# where  is the value of the INPUT_FILTER tag, and  is the
+# name of an input file. Doxygen will then use the output that the filter
+# program writes to standard output. If FILTER_PATTERNS is specified, this tag
+# will be ignored.
+#
+# Note that the filter must not add or remove lines; it is applied before the
+# code is scanned, but not when the output code is generated. If lines are added
+# or removed, the anchors will not be placed correctly.
+#
+# Note that doxygen will use the data processed and written to standard output
+# for further processing, therefore nothing else, like debug statements or used
+# commands (so in case of a Windows batch file always use @echo OFF), should be
+# written to standard output.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+INPUT_FILTER           =
+
+# The FILTER_PATTERNS tag can be used to specify filters on a per file pattern
+# basis. Doxygen will compare the file name with each pattern and apply the
+# filter if there is a match. The filters are a list of the form: pattern=filter
+# (like *.cpp=my_cpp_filter). See INPUT_FILTER for further information on how
+# filters are used. If the FILTER_PATTERNS tag is empty or if none of the
+# patterns match the file name, INPUT_FILTER is applied.
+#
+# Note that for custom extensions or not directly supported extensions you also
+# need to set EXTENSION_MAPPING for the extension otherwise the files are not
+# properly processed by doxygen.
+
+FILTER_PATTERNS        =
+
+# If the FILTER_SOURCE_FILES tag is set to YES, the input filter (if set using
+# INPUT_FILTER) will also be used to filter the input files that are used for
+# producing the source files to browse (i.e. when SOURCE_BROWSER is set to YES).
+# The default value is: NO.
+
+FILTER_SOURCE_FILES    = NO
+
+# The FILTER_SOURCE_PATTERNS tag can be used to specify source filters per file
+# pattern. A pattern will override the setting for FILTER_PATTERN (if any) and
+# it is also possible to disable source filtering for a specific pattern using
+# *.ext= (so without naming a filter).
+# This tag requires that the tag FILTER_SOURCE_FILES is set to YES.
+
+FILTER_SOURCE_PATTERNS =
+
+# If the USE_MDFILE_AS_MAINPAGE tag refers to the name of a markdown file that
+# is part of the input, its contents will be placed on the main page
+# (index.html). This can be useful if you have a project on for instance GitHub
+# and want to reuse the introduction page also for the doxygen output.
+
+USE_MDFILE_AS_MAINPAGE =
+
+# The Fortran standard specifies that for fixed formatted Fortran code all
+# characters from position 72 are to be considered as comment. A common
+# extension is to allow longer lines before the automatic comment starts. The
+# setting FORTRAN_COMMENT_AFTER will also make it possible that longer lines can
+# be processed before the automatic comment starts.
+# Minimum value: 7, maximum value: 10000, default value: 72.
+
+FORTRAN_COMMENT_AFTER  = 72
+
+#---------------------------------------------------------------------------
+# Configuration options related to source browsing
+#---------------------------------------------------------------------------
+
+# If the SOURCE_BROWSER tag is set to YES then a list of source files will be
+# generated. Documented entities will be cross-referenced with these sources.
+#
+# Note: To get rid of all source code in the generated output, make sure that
+# also VERBATIM_HEADERS is set to NO.
+# The default value is: NO.
+
+SOURCE_BROWSER         = YES
+
+# Setting the INLINE_SOURCES tag to YES will include the body of functions,
+# classes and enums directly into the documentation.
+# The default value is: NO.
+
+INLINE_SOURCES         = NO
+
+# Setting the STRIP_CODE_COMMENTS tag to YES will instruct doxygen to hide any
+# special comment blocks from generated source code fragments. Normal C, C++ and
+# Fortran comments will always remain visible.
+# The default value is: YES.
+
+STRIP_CODE_COMMENTS    = YES
+
+# If the REFERENCED_BY_RELATION tag is set to YES then for each documented
+# entity all documented functions referencing it will be listed.
+# The default value is: NO.
+
+REFERENCED_BY_RELATION = NO
+
+# If the REFERENCES_RELATION tag is set to YES then for each documented function
+# all documented entities called/used by that function will be listed.
+# The default value is: NO.
+
+REFERENCES_RELATION    = NO
+
+# If the REFERENCES_LINK_SOURCE tag is set to YES and SOURCE_BROWSER tag is set
+# to YES then the hyperlinks from functions in REFERENCES_RELATION and
+# REFERENCED_BY_RELATION lists will link to the source code. Otherwise they will
+# link to the documentation.
+# The default value is: YES.
+
+REFERENCES_LINK_SOURCE = YES
+
+# If SOURCE_TOOLTIPS is enabled (the default) then hovering a hyperlink in the
+# source code will show a tooltip with additional information such as prototype,
+# brief description and links to the definition and documentation. Since this
+# will make the HTML file larger and loading of large files a bit slower, you
+# can opt to disable this feature.
+# The default value is: YES.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+SOURCE_TOOLTIPS        = YES
+
+# If the USE_HTAGS tag is set to YES then the references to source code will
+# point to the HTML generated by the htags(1) tool instead of doxygen built-in
+# source browser. The htags tool is part of GNU's global source tagging system
+# (see https://www.gnu.org/software/global/global.html). You will need version
+# 4.8.6 or higher.
+#
+# To use it do the following:
+# - Install the latest version of global
+# - Enable SOURCE_BROWSER and USE_HTAGS in the configuration file
+# - Make sure the INPUT points to the root of the source tree
+# - Run doxygen as normal
+#
+# Doxygen will invoke htags (and that will in turn invoke gtags), so these
+# tools must be available from the command line (i.e. in the search path).
+#
+# The result: instead of the source browser generated by doxygen, the links to
+# source code will now point to the output of htags.
+# The default value is: NO.
+# This tag requires that the tag SOURCE_BROWSER is set to YES.
+
+USE_HTAGS              = NO
+
+# If the VERBATIM_HEADERS tag is set the YES then doxygen will generate a
+# verbatim copy of the header file for each class for which an include is
+# specified. Set to NO to disable this.
+# See also: Section \class.
+# The default value is: YES.
+
+VERBATIM_HEADERS       = YES
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES then doxygen will use the
+# clang parser (see:
+# http://clang.llvm.org/) for more accurate parsing at the cost of reduced
+# performance. This can be particularly helpful with template rich C++ code for
+# which doxygen's built-in parser lacks the necessary type information.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse_libclang=ON option for CMake.
+# The default value is: NO.
+
+CLANG_ASSISTED_PARSING = NO
+
+# If the CLANG_ASSISTED_PARSING tag is set to YES and the CLANG_ADD_INC_PATHS
+# tag is set to YES then doxygen will add the directory of each input to the
+# include path.
+# The default value is: YES.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_ADD_INC_PATHS    = YES
+
+# If clang assisted parsing is enabled you can provide the compiler with command
+# line options that you would normally use when invoking the compiler. Note that
+# the include paths will already be set by doxygen for the files and directories
+# specified with INPUT and INCLUDE_PATH.
+# This tag requires that the tag CLANG_ASSISTED_PARSING is set to YES.
+
+CLANG_OPTIONS          =
+
+# If clang assisted parsing is enabled you can provide the clang parser with the
+# path to the directory containing a file called compile_commands.json. This
+# file is the compilation database (see:
+# http://clang.llvm.org/docs/HowToSetupToolingForLLVM.html) containing the
+# options used when the source files were built. This is equivalent to
+# specifying the -p option to a clang tool, such as clang-check. These options
+# will then be passed to the parser. Any options specified with CLANG_OPTIONS
+# will be added as well.
+# Note: The availability of this option depends on whether or not doxygen was
+# generated with the -Duse_libclang=ON option for CMake.
+
+CLANG_DATABASE_PATH    =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the alphabetical class index
+#---------------------------------------------------------------------------
+
+# If the ALPHABETICAL_INDEX tag is set to YES, an alphabetical index of all
+# compounds will be generated. Enable this if the project contains a lot of
+# classes, structs, unions or interfaces.
+# The default value is: YES.
+
+ALPHABETICAL_INDEX     = YES
+
+# In case all classes in a project start with a common prefix, all classes will
+# be put under the same header in the alphabetical index. The IGNORE_PREFIX tag
+# can be used to specify a prefix (or a list of prefixes) that should be ignored
+# while generating the index headers.
+# This tag requires that the tag ALPHABETICAL_INDEX is set to YES.
+
+IGNORE_PREFIX          =
+
+#---------------------------------------------------------------------------
+# Configuration options related to the HTML output
+#---------------------------------------------------------------------------
+
+# If the GENERATE_HTML tag is set to YES, doxygen will generate HTML output
+# The default value is: YES.
+
+GENERATE_HTML          = YES
+
+# The HTML_OUTPUT tag is used to specify where the HTML docs will be put. If a
+# relative path is entered the value of OUTPUT_DIRECTORY will be put in front of
+# it.
+# The default directory is: html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_OUTPUT            = html
+
+# The HTML_FILE_EXTENSION tag can be used to specify the file extension for each
+# generated HTML page (for example: .htm, .php, .asp).
+# The default value is: .html.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FILE_EXTENSION    = .html
+
+# The HTML_HEADER tag can be used to specify a user-defined HTML header file for
+# each generated HTML page. If the tag is left blank doxygen will generate a
+# standard header.
+#
+# To get valid HTML the header file that includes any scripts and style sheets
+# that doxygen needs, which is dependent on the configuration options used (e.g.
+# the setting GENERATE_TREEVIEW). It is highly recommended to start with a
+# default header using
+# doxygen -w html new_header.html new_footer.html new_stylesheet.css
+# YourConfigFile
+# and then modify the file new_header.html. See also section "Doxygen usage"
+# for information on how to generate the default header that doxygen normally
+# uses.
+# Note: The header is subject to change so you typically have to regenerate the
+# default header when upgrading to a newer version of doxygen. For a description
+# of the possible markers and block names see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_HEADER            =
+
+# The HTML_FOOTER tag can be used to specify a user-defined HTML footer for each
+# generated HTML page. If the tag is left blank doxygen will generate a standard
+# footer. See HTML_HEADER for more information on how to generate a default
+# footer and what special commands can be used inside the footer. See also
+# section "Doxygen usage" for information on how to generate the default footer
+# that doxygen normally uses.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FOOTER            =
+
+# The HTML_STYLESHEET tag can be used to specify a user-defined cascading style
+# sheet that is used by each HTML page. It can be used to fine-tune the look of
+# the HTML output. If left blank doxygen will generate a default style sheet.
+# See also section "Doxygen usage" for information on how to generate the style
+# sheet that doxygen normally uses.
+# Note: It is recommended to use HTML_EXTRA_STYLESHEET instead of this tag, as
+# it is more robust and this tag (HTML_STYLESHEET) will in the future become
+# obsolete.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_STYLESHEET        =
+
+# The HTML_EXTRA_STYLESHEET tag can be used to specify additional user-defined
+# cascading style sheets that are included after the standard style sheets
+# created by doxygen. Using this option one can overrule certain style aspects.
+# This is preferred over using HTML_STYLESHEET since it does not replace the
+# standard style sheet and is therefore more robust against future updates.
+# Doxygen will copy the style sheet files to the output directory.
+# Note: The order of the extra style sheet files is of importance (e.g. the last
+# style sheet in the list overrules the setting of the previous ones in the
+# list). For an example see the documentation.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_STYLESHEET  =
+
+# The HTML_EXTRA_FILES tag can be used to specify one or more extra images or
+# other source files which should be copied to the HTML output directory. Note
+# that these files will be copied to the base HTML output directory. Use the
+# $relpath^ marker in the HTML_HEADER and/or HTML_FOOTER files to load these
+# files. In the HTML_STYLESHEET file, use the file name only. Also note that the
+# files will be copied as-is; there are no commands or markers available.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_EXTRA_FILES       =
+
+# The HTML_COLORSTYLE tag can be used to specify if the generated HTML output
+# should be rendered with a dark or light theme. Default setting AUTO_LIGHT
+# enables light output unless the user preference is dark output. Other options
+# are DARK to always use dark mode, LIGHT to always use light mode, AUTO_DARK to
+# default to dark mode unless the user prefers light mode, and TOGGLE to let the
+# user toggle between dark and light mode via a button.
+# Possible values are: LIGHT Always generate light output., DARK Always generate
+# dark output., AUTO_LIGHT Automatically set the mode according to the user
+# preference, use light mode if no preference is set (the default)., AUTO_DARK
+# Automatically set the mode according to the user preference, use dark mode if
+# no preference is set. and TOGGLE Allow to user to switch between light and
+# dark mode via a button..
+# The default value is: AUTO_LIGHT.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE        = AUTO_LIGHT
+
+# The HTML_COLORSTYLE_HUE tag controls the color of the HTML output. Doxygen
+# will adjust the colors in the style sheet and background images according to
+# this color. Hue is specified as an angle on a color-wheel, see
+# https://en.wikipedia.org/wiki/Hue for more information. For instance the value
+# 0 represents red, 60 is yellow, 120 is green, 180 is cyan, 240 is blue, 300
+# purple, and 360 is red again.
+# Minimum value: 0, maximum value: 359, default value: 220.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_HUE    = 234
+
+# The HTML_COLORSTYLE_SAT tag controls the purity (or saturation) of the colors
+# in the HTML output. For a value of 0 the output will use gray-scales only. A
+# value of 255 will produce the most vivid colors.
+# Minimum value: 0, maximum value: 255, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_SAT    = 35
+
+# The HTML_COLORSTYLE_GAMMA tag controls the gamma correction applied to the
+# luminance component of the colors in the HTML output. Values below 100
+# gradually make the output lighter, whereas values above 100 make the output
+# darker. The value divided by 100 is the actual gamma applied, so 80 represents
+# a gamma of 0.8, The value 220 represents a gamma of 2.2, and 100 does not
+# change the gamma.
+# Minimum value: 40, maximum value: 240, default value: 80.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_COLORSTYLE_GAMMA  = 110
+
+# If the HTML_TIMESTAMP tag is set to YES then the footer of each generated HTML
+# page will contain the date and time when the page was generated. Setting this
+# to YES can help to show when doxygen was last run and thus if the
+# documentation is up to date.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_TIMESTAMP         = NO
+
+# If the HTML_DYNAMIC_MENUS tag is set to YES then the generated HTML
+# documentation will contain a main index with vertical navigation menus that
+# are dynamically created via JavaScript. If disabled, the navigation index will
+# consists of multiple levels of tabs that are statically embedded in every HTML
+# page. Disable this option to support browsers that do not have JavaScript,
+# like the Qt help browser.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_MENUS     = YES
+
+# If the HTML_DYNAMIC_SECTIONS tag is set to YES then the generated HTML
+# documentation will contain sections that can be hidden and shown after the
+# page has loaded.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_DYNAMIC_SECTIONS  = NO
+
+# With HTML_INDEX_NUM_ENTRIES one can control the preferred number of entries
+# shown in the various tree structured indices initially; the user can expand
+# and collapse entries dynamically later on. Doxygen will expand the tree to
+# such a level that at most the specified number of entries are visible (unless
+# a fully collapsed tree already exceeds this amount). So setting the number of
+# entries 1 will produce a full collapsed tree by default. 0 is a special value
+# representing an infinite number of entries and will result in a full expanded
+# tree by default.
+# Minimum value: 0, maximum value: 9999, default value: 100.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_INDEX_NUM_ENTRIES = 100
+
+# If the GENERATE_DOCSET tag is set to YES, additional index files will be
+# generated that can be used as input for Apple's Xcode 3 integrated development
+# environment (see:
+# https://developer.apple.com/xcode/), introduced with OSX 10.5 (Leopard). To
+# create a documentation set, doxygen will generate a Makefile in the HTML
+# output directory. Running make will produce the docset in that directory and
+# running make install will install the docset in
+# ~/Library/Developer/Shared/Documentation/DocSets so that Xcode will find it at
+# startup. See https://developer.apple.com/library/archive/featuredarticles/Doxy
+# genXcode/_index.html for more information.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_DOCSET        = NO
+
+# This tag determines the name of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# The default value is: Doxygen generated docs.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDNAME        = "Doxygen generated docs"
+
+# This tag determines the URL of the docset feed. A documentation feed provides
+# an umbrella under which multiple documentation sets from a single provider
+# (such as a company or product suite) can be grouped.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_FEEDURL         =
+
+# This tag specifies a string that should uniquely identify the documentation
+# set bundle. This should be a reverse domain-name style string, e.g.
+# com.mycompany.MyDocSet. Doxygen will append .docset to the name.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_BUNDLE_ID       = org.doxygen.Project
+
+# The DOCSET_PUBLISHER_ID tag specifies a string that should uniquely identify
+# the documentation publisher. This should be a reverse domain-name style
+# string, e.g. com.mycompany.MyDocSet.documentation.
+# The default value is: org.doxygen.Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_ID    = org.doxygen.Publisher
+
+# The DOCSET_PUBLISHER_NAME tag identifies the documentation publisher.
+# The default value is: Publisher.
+# This tag requires that the tag GENERATE_DOCSET is set to YES.
+
+DOCSET_PUBLISHER_NAME  = Publisher
+
+# If the GENERATE_HTMLHELP tag is set to YES then doxygen generates three
+# additional HTML index files: index.hhp, index.hhc, and index.hhk. The
+# index.hhp is a project file that can be read by Microsoft's HTML Help Workshop
+# on Windows. In the beginning of 2021 Microsoft took the original page, with
+# a.o. the download links, offline the HTML help workshop was already many years
+# in maintenance mode). You can download the HTML help workshop from the web
+# archives at Installation executable (see:
+# http://web.archive.org/web/20160201063255/http://download.microsoft.com/downlo
+# ad/0/A/9/0A939EF6-E31C-430F-A3DF-DFAE7960D564/htmlhelp.exe).
+#
+# The HTML Help Workshop contains a compiler that can convert all HTML output
+# generated by doxygen into a single compiled HTML file (.chm). Compiled HTML
+# files are now used as the Windows 98 help format, and will replace the old
+# Windows help format (.hlp) on all Windows platforms in the future. Compressed
+# HTML files also contain an index, a table of contents, and you can search for
+# words in the documentation. The HTML workshop also contains a viewer for
+# compressed HTML files.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_HTMLHELP      = NO
+
+# The CHM_FILE tag can be used to specify the file name of the resulting .chm
+# file. You can add a path in front of the file if the result should not be
+# written to the html output directory.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_FILE               =
+
+# The HHC_LOCATION tag can be used to specify the location (absolute path
+# including file name) of the HTML help compiler (hhc.exe). If non-empty,
+# doxygen will try to run the HTML help compiler on the generated index.hhp.
+# The file has to be specified with full path.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+HHC_LOCATION           =
+
+# The GENERATE_CHI flag controls if a separate .chi index file is generated
+# (YES) or that it should be included in the main .chm file (NO).
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+GENERATE_CHI           = NO
+
+# The CHM_INDEX_ENCODING is used to encode HtmlHelp index (hhk), content (hhc)
+# and project file content.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+CHM_INDEX_ENCODING     =
+
+# The BINARY_TOC flag controls whether a binary table of contents is generated
+# (YES) or a normal table of contents (NO) in the .chm file. Furthermore it
+# enables the Previous and Next buttons.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+BINARY_TOC             = NO
+
+# The TOC_EXPAND flag can be set to YES to add extra items for group members to
+# the table of contents of the HTML help documentation and to the tree view.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTMLHELP is set to YES.
+
+TOC_EXPAND             = NO
+
+# If the GENERATE_QHP tag is set to YES and both QHP_NAMESPACE and
+# QHP_VIRTUAL_FOLDER are set, an additional index file will be generated that
+# can be used as input for Qt's qhelpgenerator to generate a Qt Compressed Help
+# (.qch) of the generated HTML documentation.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_QHP           = NO
+
+# If the QHG_LOCATION tag is specified, the QCH_FILE tag can be used to specify
+# the file name of the resulting .qch file. The path specified is relative to
+# the HTML output folder.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QCH_FILE               =
+
+# The QHP_NAMESPACE tag specifies the namespace to use when generating Qt Help
+# Project output. For more information please see Qt Help Project / Namespace
+# (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#namespace).
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_NAMESPACE          = org.doxygen.Project
+
+# The QHP_VIRTUAL_FOLDER tag specifies the namespace to use when generating Qt
+# Help Project output. For more information please see Qt Help Project / Virtual
+# Folders (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#virtual-folders).
+# The default value is: doc.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_VIRTUAL_FOLDER     = doc
+
+# If the QHP_CUST_FILTER_NAME tag is set, it specifies the name of a custom
+# filter to add. For more information please see Qt Help Project / Custom
+# Filters (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_NAME   =
+
+# The QHP_CUST_FILTER_ATTRS tag specifies the list of the attributes of the
+# custom filter to add. For more information please see Qt Help Project / Custom
+# Filters (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#custom-filters).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_CUST_FILTER_ATTRS  =
+
+# The QHP_SECT_FILTER_ATTRS tag specifies the list of the attributes this
+# project's filter section matches. Qt Help Project / Filter Attributes (see:
+# https://doc.qt.io/archives/qt-4.8/qthelpproject.html#filter-attributes).
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHP_SECT_FILTER_ATTRS  =
+
+# The QHG_LOCATION tag can be used to specify the location (absolute path
+# including file name) of Qt's qhelpgenerator. If non-empty doxygen will try to
+# run qhelpgenerator on the generated .qhp file.
+# This tag requires that the tag GENERATE_QHP is set to YES.
+
+QHG_LOCATION           =
+
+# If the GENERATE_ECLIPSEHELP tag is set to YES, additional index files will be
+# generated, together with the HTML files, they form an Eclipse help plugin. To
+# install this plugin and make it available under the help contents menu in
+# Eclipse, the contents of the directory containing the HTML and XML files needs
+# to be copied into the plugins directory of eclipse. The name of the directory
+# within the plugins directory should be the same as the ECLIPSE_DOC_ID value.
+# After copying Eclipse needs to be restarted before the help appears.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_ECLIPSEHELP   = NO
+
+# A unique identifier for the Eclipse help plugin. When installing the plugin
+# the directory name containing the HTML and XML files should also have this
+# name. Each documentation set should have its own identifier.
+# The default value is: org.doxygen.Project.
+# This tag requires that the tag GENERATE_ECLIPSEHELP is set to YES.
+
+ECLIPSE_DOC_ID         = org.doxygen.Project
+
+# If you want full control over the layout of the generated HTML pages it might
+# be necessary to disable the index and replace it with your own. The
+# DISABLE_INDEX tag can be used to turn on/off the condensed index (tabs) at top
+# of each HTML page. A value of NO enables the index and the value YES disables
+# it. Since the tabs in the index contain the same information as the navigation
+# tree, you can set this option to YES if you also set GENERATE_TREEVIEW to YES.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+DISABLE_INDEX          = NO
+
+# The GENERATE_TREEVIEW tag is used to specify whether a tree-like index
+# structure should be generated to display hierarchical information. If the tag
+# value is set to YES, a side panel will be generated containing a tree-like
+# index structure (just like the one that is generated for HTML Help). For this
+# to work a browser that supports JavaScript, DHTML, CSS and frames is required
+# (i.e. any modern browser). Windows users are probably better off using the
+# HTML help feature. Via custom style sheets (see HTML_EXTRA_STYLESHEET) one can
+# further fine tune the look of the index (see "Fine-tuning the output"). As an
+# example, the default style sheet generated by doxygen has an example that
+# shows how to put an image at the root of the tree instead of the PROJECT_NAME.
+# Since the tree basically has the same information as the tab index, you could
+# consider setting DISABLE_INDEX to YES when enabling this option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+GENERATE_TREEVIEW      = YES
+
+# When both GENERATE_TREEVIEW and DISABLE_INDEX are set to YES, then the
+# FULL_SIDEBAR option determines if the side bar is limited to only the treeview
+# area (value NO) or if it should extend to the full height of the window (value
+# YES). Setting this to YES gives a layout similar to
+# https://docs.readthedocs.io with more room for contents, but less room for the
+# project logo, title, and description. If either GENERATE_TREEVIEW or
+# DISABLE_INDEX is set to NO, this option has no effect.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FULL_SIDEBAR           = NO
+
+# The ENUM_VALUES_PER_LINE tag can be used to set the number of enum values that
+# doxygen will group on one line in the generated HTML documentation.
+#
+# Note that a value of 0 will completely suppress the enum values from appearing
+# in the overview section.
+# Minimum value: 0, maximum value: 20, default value: 4.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+ENUM_VALUES_PER_LINE   = 4
+
+# If the treeview is enabled (see GENERATE_TREEVIEW) then this tag can be used
+# to set the initial width (in pixels) of the frame in which the tree is shown.
+# Minimum value: 0, maximum value: 1500, default value: 250.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+TREEVIEW_WIDTH         = 250
+
+# If the EXT_LINKS_IN_WINDOW option is set to YES, doxygen will open links to
+# external symbols imported via tag files in a separate window.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+EXT_LINKS_IN_WINDOW    = NO
+
+# If the OBFUSCATE_EMAILS tag is set to YES, doxygen will obfuscate email
+# addresses.
+# The default value is: YES.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+OBFUSCATE_EMAILS       = YES
+
+# If the HTML_FORMULA_FORMAT option is set to svg, doxygen will use the pdf2svg
+# tool (see https://github.com/dawbarton/pdf2svg) or inkscape (see
+# https://inkscape.org) to generate formulas as SVG images instead of PNGs for
+# the HTML output. These images will generally look nicer at scaled resolutions.
+# Possible values are: png (the default) and svg (looks nicer but requires the
+# pdf2svg or inkscape tool).
+# The default value is: png.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+HTML_FORMULA_FORMAT    = png
+
+# Use this tag to change the font size of LaTeX formulas included as images in
+# the HTML documentation. When you change the font size after a successful
+# doxygen run you need to manually remove any form_*.png images from the HTML
+# output directory to force them to be regenerated.
+# Minimum value: 8, maximum value: 50, default value: 10.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+FORMULA_FONTSIZE       = 10
+
+# The FORMULA_MACROFILE can contain LaTeX \newcommand and \renewcommand commands
+# to create new LaTeX commands to be used in formulas as building blocks. See
+# the section "Including formulas" for details.
+
+FORMULA_MACROFILE      =
+
+# Enable the USE_MATHJAX option to render LaTeX formulas using MathJax (see
+# https://www.mathjax.org) which uses client side JavaScript for the rendering
+# instead of using pre-rendered bitmaps. Use this if you do not have LaTeX
+# installed or if you want to formulas look prettier in the HTML output. When
+# enabled you may also need to install MathJax separately and configure the path
+# to it using the MATHJAX_RELPATH option.
+# The default value is: NO.
+# This tag requires that the tag GENERATE_HTML is set to YES.
+
+USE_MATHJAX            = NO
+
+# With MATHJAX_VERSION it is possible to specify the MathJax version to be used.
+# Note that the different versions of MathJax have different requirements with
+# regards to the different settings, so it is possible that also other MathJax
+# settings have to be changed when switching between the different MathJax
+# versions.
+# Possible values are: MathJax_2 and MathJax_3.
+# The default value is: MathJax_2.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_VERSION        = MathJax_2
+
+# When MathJax is enabled you can set the default output format to be used for
+# the MathJax output. For more details about the output format see MathJax
+# version 2 (see:
+# http://docs.mathjax.org/en/v2.7-latest/output.html) and MathJax version 3
+# (see:
+# http://docs.mathjax.org/en/latest/web/components/output.html).
+# Possible values are: HTML-CSS (which is slower, but has the best
+# compatibility. This is the name for Mathjax version 2, for MathJax version 3
+# this will be translated into chtml), NativeMML (i.e. MathML. Only supported
+# for NathJax 2. For MathJax version 3 chtml will be used instead.), chtml (This
+# is the name for Mathjax version 3, for MathJax version 2 this will be
+# translated into HTML-CSS) and SVG.
+# The default value is: HTML-CSS.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_FORMAT         = HTML-CSS
+
+# When MathJax is enabled you need to specify the location relative to the HTML
+# output directory using the MATHJAX_RELPATH option. The destination directory
+# should contain the MathJax.js script. For instance, if the mathjax directory
+# is located at the same level as the HTML output directory, then
+# MATHJAX_RELPATH should be ../mathjax. The default value points to the MathJax
+# Content Delivery Network so you can quickly see the result without installing
+# MathJax. However, it is strongly recommended to install a local copy of
+# MathJax from https://www.mathjax.org before deployment. The default value is:
+# - in case of MathJax version 2: https://cdn.jsdelivr.net/npm/mathjax@2
+# - in case of MathJax version 3: https://cdn.jsdelivr.net/npm/mathjax@3
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_RELPATH        = https://cdn.jsdelivr.net/npm/mathjax@2
+
+# The MATHJAX_EXTENSIONS tag can be used to specify one or more MathJax
+# extension names that should be enabled during MathJax rendering. For example
+# for MathJax version 2 (see
+# https://docs.mathjax.org/en/v2.7-latest/tex.html#tex-and-latex-extensions):
+# MATHJAX_EXTENSIONS = TeX/AMSmath TeX/AMSsymbols
+# For example for MathJax version 3 (see
+# http://docs.mathjax.org/en/latest/input/tex/extensions/index.html):
+# MATHJAX_EXTENSIONS = ams
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_EXTENSIONS     =
+
+# The MATHJAX_CODEFILE tag can be used to specify a file with javascript pieces
+# of code that will be used on startup of the MathJax code. See the MathJax site
+# (see:
+# http://docs.mathjax.org/en/v2.7-latest/output.html) for more details. For an
+# example see the documentation.
+# This tag requires that the tag USE_MATHJAX is set to YES.
+
+MATHJAX_CODEFILE       =
+
+# When the SEARCHENGINE tag is enabled doxygen will generate a search box for
+# the HTML output. The underlying search engine uses javascript and DHTML and
+# should work on any modern browser. Note that when using HTML help
+# (GENERATE_HTMLHELP), Qt help (GENERATE_QHP), or docsets (GENERATE_DOCSET)
+# there is already a search function so this one should typically be disabled.
+# For large projects the javascript based search engine can be slow, then
+# enabling SERVER_BASED_SEARCH may provide a better solution. It is possible to
+# search using the keyboard; to jump to the search box use  + S
+# (what the  is depends on the OS and browser, but it is typically
+# , /Node,
+# Edge and Graph Attributes specification You need to make sure dot is able
+# to find the font, which can be done by putting it in a standard location or by
+# setting the DOTFONTPATH environment variable or by setting DOT_FONTPATH to the
+# directory containing the font. Default graphviz fontsize is 14.
+# The default value is: fontname=Helvetica,fontsize=10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_COMMON_ATTR        = "fontname=Helvetica,fontsize=10"
+
+# DOT_EDGE_ATTR is concatenated with DOT_COMMON_ATTR. For elegant style you can
+# add 'arrowhead=open, arrowtail=open, arrowsize=0.5'. Complete documentation about
+# arrows shapes.
+# The default value is: labelfontname=Helvetica,labelfontsize=10.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_EDGE_ATTR          = "labelfontname=Helvetica,labelfontsize=10"
+
+# DOT_NODE_ATTR is concatenated with DOT_COMMON_ATTR. For view without boxes
+# around nodes set 'shape=plain' or 'shape=plaintext' Shapes specification
+# The default value is: shape=box,height=0.2,width=0.4.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_NODE_ATTR          = "shape=box,height=0.2,width=0.4"
+
+# You can set the path where dot can find font specified with fontname in
+# DOT_COMMON_ATTR and others dot attributes.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_FONTPATH           =
+
+# If the CLASS_GRAPH tag is set to YES (or GRAPH) then doxygen will generate a
+# graph for each documented class showing the direct and indirect inheritance
+# relations. In case HAVE_DOT is set as well dot will be used to draw the graph,
+# otherwise the built-in generator will be used. If the CLASS_GRAPH tag is set
+# to TEXT the direct and indirect inheritance relations will be shown as texts /
+# links.
+# Possible values are: NO, YES, TEXT and GRAPH.
+# The default value is: YES.
+
+CLASS_GRAPH            = YES
+
+# If the COLLABORATION_GRAPH tag is set to YES then doxygen will generate a
+# graph for each documented class showing the direct and indirect implementation
+# dependencies (inheritance, containment, and class references variables) of the
+# class with other documented classes.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+COLLABORATION_GRAPH    = YES
+
+# If the GROUP_GRAPHS tag is set to YES then doxygen will generate a graph for
+# groups, showing the direct groups dependencies. See also the chapter Grouping
+# in the manual.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GROUP_GRAPHS           = YES
+
+# If the UML_LOOK tag is set to YES, doxygen will generate inheritance and
+# collaboration diagrams in a style similar to the OMG's Unified Modeling
+# Language.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+UML_LOOK               = YES
+
+# If the UML_LOOK tag is enabled, the fields and methods are shown inside the
+# class node. If there are many fields or methods and many nodes the graph may
+# become too big to be useful. The UML_LIMIT_NUM_FIELDS threshold limits the
+# number of items for each type to make the size more manageable. Set this to 0
+# for no limit. Note that the threshold may be exceeded by 50% before the limit
+# is enforced. So when you set the threshold to 10, up to 15 fields may appear,
+# but if the number exceeds 15, the total amount of fields shown is limited to
+# 10.
+# Minimum value: 0, maximum value: 100, default value: 10.
+# This tag requires that the tag UML_LOOK is set to YES.
+
+UML_LIMIT_NUM_FIELDS   = 10
+
+# If the DOT_UML_DETAILS tag is set to NO, doxygen will show attributes and
+# methods without types and arguments in the UML graphs. If the DOT_UML_DETAILS
+# tag is set to YES, doxygen will add type and arguments for attributes and
+# methods in the UML graphs. If the DOT_UML_DETAILS tag is set to NONE, doxygen
+# will not generate fields with class member information in the UML graphs. The
+# class diagrams will look similar to the default class diagrams but using UML
+# notation for the relationships.
+# Possible values are: NO, YES and NONE.
+# The default value is: NO.
+# This tag requires that the tag UML_LOOK is set to YES.
+
+DOT_UML_DETAILS        = NO
+
+# The DOT_WRAP_THRESHOLD tag can be used to set the maximum number of characters
+# to display on a single line. If the actual line length exceeds this threshold
+# significantly it will wrapped across multiple lines. Some heuristics are apply
+# to avoid ugly line breaks.
+# Minimum value: 0, maximum value: 1000, default value: 17.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_WRAP_THRESHOLD     = 17
+
+# If the TEMPLATE_RELATIONS tag is set to YES then the inheritance and
+# collaboration graphs will show the relations between templates and their
+# instances.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+TEMPLATE_RELATIONS     = NO
+
+# If the INCLUDE_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are set to
+# YES then doxygen will generate a graph for each documented file showing the
+# direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDE_GRAPH          = YES
+
+# If the INCLUDED_BY_GRAPH, ENABLE_PREPROCESSING and SEARCH_INCLUDES tags are
+# set to YES then doxygen will generate a graph for each documented file showing
+# the direct and indirect include dependencies of the file with other documented
+# files.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INCLUDED_BY_GRAPH      = YES
+
+# If the CALL_GRAPH tag is set to YES then doxygen will generate a call
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable call graphs for selected
+# functions only using the \callgraph command. Disabling a call graph can be
+# accomplished by means of the command \hidecallgraph.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALL_GRAPH             = YES
+
+# If the CALLER_GRAPH tag is set to YES then doxygen will generate a caller
+# dependency graph for every global function or class method.
+#
+# Note that enabling this option will significantly increase the time of a run.
+# So in most cases it will be better to enable caller graphs for selected
+# functions only using the \callergraph command. Disabling a caller graph can be
+# accomplished by means of the command \hidecallergraph.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+CALLER_GRAPH           = YES
+
+# If the GRAPHICAL_HIERARCHY tag is set to YES then doxygen will graphical
+# hierarchy of all classes instead of a textual one.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GRAPHICAL_HIERARCHY    = YES
+
+# If the DIRECTORY_GRAPH tag is set to YES then doxygen will show the
+# dependencies a directory has on other directories in a graphical way. The
+# dependency relations are determined by the #include relations between the
+# files in the directories.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DIRECTORY_GRAPH        = YES
+
+# The DIR_GRAPH_MAX_DEPTH tag can be used to limit the maximum number of levels
+# of child directories generated in directory dependency graphs by dot.
+# Minimum value: 1, maximum value: 25, default value: 1.
+# This tag requires that the tag DIRECTORY_GRAPH is set to YES.
+
+DIR_GRAPH_MAX_DEPTH    = 1
+
+# The DOT_IMAGE_FORMAT tag can be used to set the image format of the images
+# generated by dot. For an explanation of the image formats see the section
+# output formats in the documentation of the dot tool (Graphviz (see:
+# http://www.graphviz.org/)).
+# Note: If you choose svg you need to set HTML_FILE_EXTENSION to xhtml in order
+# to make the SVG files visible in IE 9+ (other browsers do not have this
+# requirement).
+# Possible values are: png, jpg, gif, svg, png:gd, png:gd:gd, png:cairo,
+# png:cairo:gd, png:cairo:cairo, png:cairo:gdiplus, png:gdiplus and
+# png:gdiplus:gdiplus.
+# The default value is: png.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_IMAGE_FORMAT       = png
+
+# If DOT_IMAGE_FORMAT is set to svg, then this option can be set to YES to
+# enable generation of interactive SVG images that allow zooming and panning.
+#
+# Note that this requires a modern browser other than Internet Explorer. Tested
+# and working are Firefox, Chrome, Safari, and Opera.
+# Note: For IE 9+ you need to set HTML_FILE_EXTENSION to xhtml in order to make
+# the SVG files visible. Older versions of IE do not have SVG support.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+INTERACTIVE_SVG        = NO
+
+# The DOT_PATH tag can be used to specify the path where the dot tool can be
+# found. If left blank, it is assumed the dot tool can be found in the path.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_PATH               = "C:\Program Files\Graphviz\bin"
+
+# The DOTFILE_DIRS tag can be used to specify one or more directories that
+# contain dot files that are included in the documentation (see the \dotfile
+# command).
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOTFILE_DIRS           =
+
+# The MSCFILE_DIRS tag can be used to specify one or more directories that
+# contain msc files that are included in the documentation (see the \mscfile
+# command).
+
+MSCFILE_DIRS           =
+
+# The DIAFILE_DIRS tag can be used to specify one or more directories that
+# contain dia files that are included in the documentation (see the \diafile
+# command).
+
+DIAFILE_DIRS           =
+
+# When using plantuml, the PLANTUML_JAR_PATH tag should be used to specify the
+# path where java can find the plantuml.jar file or to the filename of jar file
+# to be used. If left blank, it is assumed PlantUML is not used or called during
+# a preprocessing step. Doxygen will generate a warning when it encounters a
+# \startuml command in this case and will not generate output for the diagram.
+
+PLANTUML_JAR_PATH      =
+
+# When using plantuml, the PLANTUML_CFG_FILE tag can be used to specify a
+# configuration file for plantuml.
+
+PLANTUML_CFG_FILE      =
+
+# When using plantuml, the specified paths are searched for files specified by
+# the !include statement in a plantuml block.
+
+PLANTUML_INCLUDE_PATH  =
+
+# The DOT_GRAPH_MAX_NODES tag can be used to set the maximum number of nodes
+# that will be shown in the graph. If the number of nodes in a graph becomes
+# larger than this value, doxygen will truncate the graph, which is visualized
+# by representing a node as a red box. Note that doxygen if the number of direct
+# children of the root node in a graph is already larger than
+# DOT_GRAPH_MAX_NODES then the graph will not be shown at all. Also note that
+# the size of a graph can be further restricted by MAX_DOT_GRAPH_DEPTH.
+# Minimum value: 0, maximum value: 10000, default value: 50.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_GRAPH_MAX_NODES    = 50
+
+# The MAX_DOT_GRAPH_DEPTH tag can be used to set the maximum depth of the graphs
+# generated by dot. A depth value of 3 means that only nodes reachable from the
+# root by following a path via at most 3 edges will be shown. Nodes that lay
+# further from the root node will be omitted. Note that setting this option to 1
+# or 2 may greatly reduce the computation time needed for large code bases. Also
+# note that the size of a graph can be further restricted by
+# DOT_GRAPH_MAX_NODES. Using a depth of 0 means no depth restriction.
+# Minimum value: 0, maximum value: 1000, default value: 0.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+MAX_DOT_GRAPH_DEPTH    = 0
+
+# Set the DOT_MULTI_TARGETS tag to YES to allow dot to generate multiple output
+# files in one run (i.e. multiple -o and -T options on the command line). This
+# makes dot run faster, but since only newer versions of dot (>1.8.10) support
+# this, this feature is disabled by default.
+# The default value is: NO.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+DOT_MULTI_TARGETS      = NO
+
+# If the GENERATE_LEGEND tag is set to YES doxygen will generate a legend page
+# explaining the meaning of the various boxes and arrows in the dot generated
+# graphs.
+# Note: This tag requires that UML_LOOK isn't set, i.e. the doxygen internal
+# graphical representation for inheritance and collaboration diagrams is used.
+# The default value is: YES.
+# This tag requires that the tag HAVE_DOT is set to YES.
+
+GENERATE_LEGEND        = YES
+
+# If the DOT_CLEANUP tag is set to YES, doxygen will remove the intermediate
+# files that are used to generate the various graphs.
+#
+# Note: This setting is not only used for dot files but also for msc temporary
+# files.
+# The default value is: YES.
+
+DOT_CLEANUP            = YES
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/SConscript
new file mode 100755
index 0000000000..9eacf7f39f
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/SConscript
@@ -0,0 +1,123 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+
+CPPPATH = [cwd + r'/include',
+        cwd + r'/include/arch',
+        cwd + r'/include/arch/risc-v/t-head',
+        cwd + r'/include/arch/risc-v/t-head/Core/Include',
+        cwd + r'/src/flash']
+
+src     = Split("""
+    src/bflb_adc.c
+    src/bflb_cks.c
+    src/bflb_ef_ctrl.c
+    src/bflb_gpio.c
+    src/bflb_i2c.c
+    src/bflb_dma.c
+    src/bflb_rtc.c
+    src/bflb_sec_aes.c
+    src/bflb_sec_sha.c
+    src/bflb_sec_trng.c
+    src/bflb_spi.c
+    src/bflb_timer.c
+    src/bflb_uart.c
+    src/bflb_wdg.c
+    src/bflb_flash.c
+    src/flash/bflb_sf_cfg.c
+    src/flash/bflb_xip_sflash.c
+    src/flash/bflb_sflash.c
+    src/flash/bflb_sf_ctrl.c
+    src/bflb_irq.c
+    src/bflb_l1c.c
+    src/bflb_mtimer.c
+""")
+
+if not GetDepend('BSP_USING_ROMAPI'):
+    src += ['src/bflb_common.c']
+else:
+    if not GetDepend('BSP_USING_BL60X') and not GetDepend('BSP_USING_BL70X'):
+        src += ['src/bflb_common.c']
+
+if GetDepend('BSP_USING_BL61X'):
+    src += Split("""
+        src/bflb_dac.c
+        src/bflb_emac.c
+        src/bflb_ir.c
+        src/bflb_mjpeg.c
+        src/bflb_pwm_v2.c
+        src/bflb_cam.c
+        src/bflb_iso11898.c
+        src/bflb_i2s.c
+        src/bflb_common.c
+        include/arch/risc-v/t-head/rv_hart.c
+        include/arch/risc-v/t-head/rv_pmp.c
+    """)
+    src += ['config/bl616/device_table.c']
+    CPPPATH += [cwd + r'/config/bl616']
+    
+elif GetDepend('BSP_USING_BL60X'):
+    src += Split("""
+        src/bflb_dac.c
+        src/bflb_ir.c
+        src/bflb_pwm_v1.c
+    """)
+    src += ['config/bl602/device_table.c']
+    CPPPATH += [cwd + r'/config/bl602']
+
+elif GetDepend('BSP_USING_BL70X'):
+    src += Split("""
+        src/bflb_dac.c
+        src/bflb_emac.c
+        src/bflb_ir.c
+        src/bflb_pwm_v1.c
+        src/bflb_cam.c
+        src/bflb_spi_psram.c
+    """)
+    src += ['config/bl702/device_table.c']
+    CPPPATH += [cwd + r'/config/bl702']
+
+elif GetDepend('BSP_USING_BL702L'):
+    src += Split("""
+        src/bflb_pwm_v1.c
+        src/bflb_pwm_v2.c
+        src/bflb_spi_psram.c
+    """)
+
+elif GetDepend('BSP_USING_BL628'):
+    src += Split("""
+        src/bflb_dac.c
+        src/bflb_emac.c
+        src/bflb_clock.c
+        src/bflb_pwm_v2.c
+        src/bflb_iso11898.c
+        include/arch/risc-v/t-head/rv_hart.c
+        include/arch/risc-v/t-head/rv_pmp.c
+   """)
+
+elif GetDepend('BSP_USING_BL808'):
+    src += Split("""
+        src/bflb_dac.c
+        src/bflb_emac.c
+        src/bflb_ir.c
+        src/bflb_mjpeg.c
+        src/bflb_pwm_v2.c
+        src/bflb_cam.c
+        src/bflb_iso11898.c
+        src/bflb_csi.c
+        src/bflb_i2s.c
+        include/arch/risc-v/t-head/rv_hart.c
+        include/arch/risc-v/t-head/rv_pmp.c
+    """)
+    src += ['config/bl808/device_table.c']
+    CPPPATH += [cwd + r'/config/bl808']
+    
+LOCAL_CFLAGS = ' -DARCH_RISCV'
+
+group = DefineGroup('bl_lhal', src, depend = [''], CPPPATH = CPPPATH, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+objs = [group]
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/bl602_irq.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/bl602_irq.h
new file mode 100755
index 0000000000..9a72f12bb8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/bl602_irq.h
@@ -0,0 +1,84 @@
+#ifndef __BL602_IRQ_H
+#define __BL602_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BL602_IRQ_NUM_BASE 16
+
+#define BL602_IRQ_MSOFT          3
+#define BL602_IRQ_MTIME          7
+#define BL602_IRQ_MEXT           11
+#define BL602_IRQ_CLIC_SOFT_PEND 12
+
+#define BL602_IRQ_BMX_MCU_BUS_ERR      (BL602_IRQ_NUM_BASE + 0)
+#define BL602_IRQ_BMX_MCU_TO           (BL602_IRQ_NUM_BASE + 1)
+#define BL602_IRQ_L1C_BMX_ERR          (BL602_IRQ_NUM_BASE + 2)
+#define BL602_IRQ_L1C_BMX_TO           (BL602_IRQ_NUM_BASE + 3)
+#define BL602_IRQ_SEC_BMX_ERR          (BL602_IRQ_NUM_BASE + 4)
+#define BL602_IRQ_RF_TOP_INT0          (BL602_IRQ_NUM_BASE + 5)
+#define BL602_IRQ_RF_TOP_INT1          (BL602_IRQ_NUM_BASE + 6)
+#define BL602_IRQ_SDIO                 (BL602_IRQ_NUM_BASE + 7)
+#define BL602_IRQ_DMA_BMX_ERR          (BL602_IRQ_NUM_BASE + 8)
+#define BL602_IRQ_SEC_GMAC             (BL602_IRQ_NUM_BASE + 9)
+#define BL602_IRQ_SEC_CDET             (BL602_IRQ_NUM_BASE + 10)
+#define BL602_IRQ_SEC_PKA              (BL602_IRQ_NUM_BASE + 11)
+#define BL602_IRQ_SEC_TRNG             (BL602_IRQ_NUM_BASE + 12)
+#define BL602_IRQ_SEC_AES              (BL602_IRQ_NUM_BASE + 13)
+#define BL602_IRQ_SEC_SHA              (BL602_IRQ_NUM_BASE + 14)
+#define BL602_IRQ_DMA0_ALL             (BL602_IRQ_NUM_BASE + 15)
+#define BL602_IRQ_RESERVED0            (BL602_IRQ_NUM_BASE + 16)
+#define BL602_IRQ_RESERVED1            (BL602_IRQ_NUM_BASE + 17)
+#define BL602_IRQ_RESERVED2            (BL602_IRQ_NUM_BASE + 18)
+#define BL602_IRQ_IRTX                 (BL602_IRQ_NUM_BASE + 19)
+#define BL602_IRQ_IRRX                 (BL602_IRQ_NUM_BASE + 20)
+#define BL602_IRQ_RESERVED3            (BL602_IRQ_NUM_BASE + 21)
+#define BL602_IRQ_RESERVED4            (BL602_IRQ_NUM_BASE + 22)
+#define BL602_IRQ_SF_CTRL              (BL602_IRQ_NUM_BASE + 23)
+#define BL602_IRQ_RESERVED5            (BL602_IRQ_NUM_BASE + 24)
+#define BL602_IRQ_GPADC_DMA            (BL602_IRQ_NUM_BASE + 25)
+#define BL602_IRQ_EFUSE                (BL602_IRQ_NUM_BASE + 26)
+#define BL602_IRQ_SPI0                 (BL602_IRQ_NUM_BASE + 27)
+#define BL602_IRQ_RESERVED6            (BL602_IRQ_NUM_BASE + 28)
+#define BL602_IRQ_UART0                (BL602_IRQ_NUM_BASE + 29)
+#define BL602_IRQ_UART1                (BL602_IRQ_NUM_BASE + 30)
+#define BL602_IRQ_RESERVED7            (BL602_IRQ_NUM_BASE + 31)
+#define BL602_IRQ_I2C0                 (BL602_IRQ_NUM_BASE + 32)
+#define BL602_IRQ_RESERVED8            (BL602_IRQ_NUM_BASE + 33)
+#define BL602_IRQ_PWM                  (BL602_IRQ_NUM_BASE + 34)
+#define BL602_IRQ_RESERVED9            (BL602_IRQ_NUM_BASE + 35)
+#define BL602_IRQ_TIMER0               (BL602_IRQ_NUM_BASE + 36)
+#define BL602_IRQ_TIMER1               (BL602_IRQ_NUM_BASE + 37)
+#define BL602_IRQ_WDT                  (BL602_IRQ_NUM_BASE + 38)
+#define BL602_IRQ_RESERVED10           (BL602_IRQ_NUM_BASE + 39)
+#define BL602_IRQ_RESERVED11           (BL602_IRQ_NUM_BASE + 40)
+#define BL602_IRQ_RESERVED12           (BL602_IRQ_NUM_BASE + 41)
+#define BL602_IRQ_RESERVED13           (BL602_IRQ_NUM_BASE + 42)
+#define BL602_IRQ_RESERVED14           (BL602_IRQ_NUM_BASE + 43)
+#define BL602_IRQ_GPIO_INT0            (BL602_IRQ_NUM_BASE + 44)
+#define BL602_IRQ_RESERVED15           (BL602_IRQ_NUM_BASE + 45)
+#define BL602_IRQ_RESERVED16           (BL602_IRQ_NUM_BASE + 46)
+#define BL602_IRQ_RESERVED17           (BL602_IRQ_NUM_BASE + 47)
+#define BL602_IRQ_RESERVED18           (BL602_IRQ_NUM_BASE + 48)
+#define BL602_IRQ_RESERVED19           (BL602_IRQ_NUM_BASE + 49)
+#define BL602_IRQ_PDS_WAKEUP           (BL602_IRQ_NUM_BASE + 50)
+#define BL602_IRQ_HBN_OUT0             (BL602_IRQ_NUM_BASE + 51)
+#define BL602_IRQ_HBN_OUT1             (BL602_IRQ_NUM_BASE + 52)
+#define BL602_IRQ_BOR                  (BL602_IRQ_NUM_BASE + 53)
+#define BL602_IRQ_WIFI                 (BL602_IRQ_NUM_BASE + 54)
+#define BL616_IRQ_BZ_PHY_INT           (BL602_IRQ_NUM_BASE + 55)
+#define BL602_IRQ_BLE                  (BL602_IRQ_NUM_BASE + 56)
+#define BL602_IRQ_MAC_INT_TIMER        (BL602_IRQ_NUM_BASE + 57)
+#define BL602_IRQ_MAC_INT_MISC         (BL602_IRQ_NUM_BASE + 58)
+#define BL602_IRQ_MAC_INT_RX_TRIGGER   (BL602_IRQ_NUM_BASE + 59)
+#define BL602_IRQ_MAC_INT_TX_TRIGGER   (BL602_IRQ_NUM_BASE + 60)
+#define BL602_IRQ_MAC_INT_GEN          (BL602_IRQ_NUM_BASE + 61)
+#define BL602_IRQ_MAC_INT_PROT_TRIGGER (BL602_IRQ_NUM_BASE + 62)
+#define BL602_IRQ_WIFI_IPC             (BL602_IRQ_NUM_BASE + 63)
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/bl602_memorymap.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/bl602_memorymap.h
new file mode 100755
index 0000000000..4e846b55c2
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/bl602_memorymap.h
@@ -0,0 +1,67 @@
+#ifndef __BL702_MEMORYMAP_H
+#define __BL702_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define BL602_FLASH_XIP_BASE        0x23000000
+#define BL602_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL602_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL602_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL602_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)
+
+#define BL602_WRAM_BASE        0x42020000
+#define BL602_WRAM_END         (0x42020000 + 176 * 1024)
+#define BL602_WRAM_REMAP0_BASE 0x22020000
+#define BL602_WRAM_REMAP0_END  (0x22020000 + 176 * 1024)
+#define BL602_WRAM_REMAP1_BASE 0x32020000
+#define BL602_WRAM_REMAP1_END  (0x32020000 + 176 * 1024)
+#define BL602_WRAM_REMAP2_BASE 0x52020000
+#define BL602_WRAM_REMAP2_END  (0x52020000 + 176 * 1024)
+
+#define BL602_TCM_BASE        0x22008000
+#define BL602_TCM_END         (0x22008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP0_BASE 0x32008000
+#define BL602_TCM_REMAP0_END  (0x32008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP1_BASE 0x42008000
+#define BL602_TCM_REMAP1_END  (0x42008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP2_BASE 0x52008000
+#define BL602_TCM_REMAP2_END  (0x52008000 + (96 + 176) * 1024)
+/*@} end of group Memory_Map_Section */
+
+/* BL602 peripherals base address */
+#define GLB_BASE         ((uint32_t)0x40000000)
+#define RF_BASE          ((uint32_t)0x40001000)
+#define GPIP_BASE        ((uint32_t)0x40002000) /*!< AUX module base address */
+#define SEC_DBG_BASE     ((uint32_t)0x40003000) /*!< Security Debug module base address */
+#define SEC_ENG_BASE     ((uint32_t)0x40004000) /*!< Security Engine module base address */
+#define TZC_SEC_BASE     ((uint32_t)0x40005000) /*!< Trustzone control security base address */
+#define TZC_NSEC_BASE    ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
+#define EF_DATA_BASE     ((uint32_t)0x40007000)
+#define EF_CTRL_BASE     ((uint32_t)0x40007000)
+#define CCI_BASE         ((uint32_t)0x40008000)
+#define L1C_BASE         ((uint32_t)0x40009000) /*!< L1 cache config base address */
+#define UART0_BASE       ((uint32_t)0x4000A000)
+#define UART1_BASE       ((uint32_t)0x4000A100)
+#define SPI_BASE         ((uint32_t)0x4000A200)
+#define I2C_BASE         ((uint32_t)0x4000A300)
+#define PWM_BASE         ((uint32_t)0x4000A400)
+#define TIMER_BASE       ((uint32_t)0x4000A500)
+#define IR_BASE          ((uint32_t)0x4000A600)
+#define SF_CTRL_BASE     ((uint32_t)0x4000B000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#define DMA_BASE         ((uint32_t)0x4000C000)
+#define SDU_BASE         ((uint32_t)0x4000D000)
+#define PDS_BASE         ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
+#define HBN_BASE         ((uint32_t)0x4000F000) /*!< Hibernate module base address */
+#define AON_BASE         ((uint32_t)0x4000F000) /*!< Always on module base address */
+#define HBN_RAM_BASE     ((uint32_t)0x40010000)
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/device_table.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/device_table.c
new file mode 100755
index 0000000000..38fa6e46e1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl602/device_table.c
@@ -0,0 +1,225 @@
+#include "bflb_core.h"
+#include "bl602_irq.h"
+#include "bl602_memorymap.h"
+
+#define DMA_CHANNEL_OFFSET 0x100
+
+struct bflb_device_s bl602_device_table[] = {
+    { .name = "adc",
+      .reg_base = AON_BASE,
+      .irq_num = BL602_IRQ_GPADC_DMA,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ADC,
+      .user_data = NULL },
+    { .name = "dac",
+      .reg_base = GLB_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DAC,
+      .user_data = NULL },
+    { .name = "ef_ctrl",
+      .reg_base = EF_CTRL_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_EF_CTRL,
+      .user_data = NULL },
+    { .name = "gpio",
+      .reg_base = GLB_BASE,
+      .irq_num = BL602_IRQ_GPIO_INT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_GPIO,
+      .user_data = NULL },
+    { .name = "uart0",
+      .reg_base = UART0_BASE,
+      .irq_num = BL602_IRQ_UART0,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart1",
+      .reg_base = UART1_BASE,
+      .irq_num = BL602_IRQ_UART1,
+      .idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "spi0",
+      .reg_base = SPI_BASE,
+      .irq_num = BL602_IRQ_SPI0,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SPI,
+      .user_data = NULL },
+    { .name = "pwm0",
+      .reg_base = PWM_BASE,
+      .irq_num = BL602_IRQ_PWM,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PWM,
+      .user_data = NULL },
+    { .name = "dma0_ch0",
+      .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch1",
+      .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch2",
+      .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 2,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch3",
+      .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 3,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch4",
+      .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 4,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch5",
+      .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 5,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch6",
+      .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 6,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch7",
+      .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL602_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 7,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "i2c0",
+      .reg_base = I2C_BASE,
+      .irq_num = BL602_IRQ_I2C0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_I2C,
+      .user_data = NULL },
+    { .name = "timer0",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL602_IRQ_TIMER0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "timer1",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL602_IRQ_TIMER1,
+      .idx = 1,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "rtc",
+      .reg_base = HBN_BASE,
+      .irq_num = BL602_IRQ_HBN_OUT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_RTC,
+      .user_data = NULL },
+    { .name = "aes",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_AES,
+      .user_data = NULL },
+    { .name = "sha",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SHA,
+      .user_data = NULL },
+    { .name = "trng",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TRNG,
+      .user_data = NULL },
+    { .name = "pka",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PKA,
+      .user_data = NULL },
+    { .name = "watchdog",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL602_IRQ_WDT,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "irtx",
+      .reg_base = IR_BASE,
+      .irq_num = BL602_IRQ_IRTX,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_IR,
+      .user_data = NULL },
+    { .name = "irrx",
+      .reg_base = IR_BASE,
+      .irq_num = BL602_IRQ_IRRX,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_IR,
+      .user_data = NULL },
+    { .name = "sdio2",
+      .reg_base = SDU_BASE,
+      .irq_num = BL602_IRQ_SDIO,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SDIO2,
+      .user_data = NULL },
+};
+
+struct bflb_device_s *bflb_device_get_by_name(const char *name)
+{
+    for (uint8_t i = 0; i < sizeof(bl602_device_table) / sizeof(bl602_device_table[0]); i++) {
+        if (strcmp(bl602_device_table[i].name, name) == 0) {
+            return &bl602_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx)
+{
+    for (uint8_t i = 0; i < sizeof(bl602_device_table) / sizeof(bl602_device_table[0]); i++) {
+        if ((bl602_device_table[i].dev_type == type) && (bl602_device_table[i].idx = idx)) {
+            return &bl602_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data)
+{
+    device->user_data = user_data;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_irq.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_irq.h
new file mode 100755
index 0000000000..869a2fd128
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_irq.h
@@ -0,0 +1,90 @@
+#ifndef __BL616_IRQ_H
+#define __BL616_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BL616_IRQ_NUM_BASE       16
+
+#define BL616_IRQ_SSOFT          1
+#define BL616_IRQ_MSOFT          3
+#define BL616_IRQ_STIME          5
+#define BL616_IRQ_MTIME          7
+#define BL616_IRQ_SEXT           9
+#define BL616_IRQ_MEXT           11
+#define BL616_IRQ_CLIC_SOFT_PEND 12
+#if (__riscv_xlen == 64)
+#define BL616_IRQ_HPM_OVF 17
+#endif
+
+#define BL616_IRQ_BMX_MCU_BUS_ERR                   (BL616_IRQ_NUM_BASE + 0)
+#define BL616_IRQ_BMX_MCU_TO                        (BL616_IRQ_NUM_BASE + 1)
+#define BL616_IRQ_DBI                               (BL616_IRQ_NUM_BASE + 2)
+#define BL616_IRQ_SDU_SOFT_RST                      (BL616_IRQ_NUM_BASE + 3)
+#define BL616_IRQ_AUDAC                             (BL616_IRQ_NUM_BASE + 4)
+#define BL616_IRQ_RF_TOP_INT0                       (BL616_IRQ_NUM_BASE + 5)
+#define BL616_IRQ_RF_TOP_INT1                       (BL616_IRQ_NUM_BASE + 6)
+#define BL616_IRQ_SDIO                              (BL616_IRQ_NUM_BASE + 7)
+#define BL616_IRQ_WIFI_TBTT_SLEEP                   (BL616_IRQ_NUM_BASE + 8)
+#define BL616_IRQ_SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC (BL616_IRQ_NUM_BASE + 9)
+#define BL616_IRQ_SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC (BL616_IRQ_NUM_BASE + 10)
+#define BL616_IRQ_SEC_ENG_ID1_CDET                  (BL616_IRQ_NUM_BASE + 11)
+#define BL616_IRQ_SEC_ENG_ID0_CDET                  (BL616_IRQ_NUM_BASE + 12)
+#define BL616_IRQ_SF_CTRL_ID1                       (BL616_IRQ_NUM_BASE + 13)
+#define BL616_IRQ_SF_CTRL_ID0                       (BL616_IRQ_NUM_BASE + 14)
+#define BL616_IRQ_DMA0_ALL                          (BL616_IRQ_NUM_BASE + 15)
+#define BL616_IRQ_DVP2BUS_INT0                      (BL616_IRQ_NUM_BASE + 16)
+#define BL616_IRQ_SDH                               (BL616_IRQ_NUM_BASE + 17)
+#define BL616_IRQ_DVP2BUS_INT1                      (BL616_IRQ_NUM_BASE + 18)
+#define BL616_IRQ_WIFI_TBTT_WAKEUP                  (BL616_IRQ_NUM_BASE + 19)
+#define BL616_IRQ_IRRX                              (BL616_IRQ_NUM_BASE + 20)
+#define BL616_IRQ_USB                               (BL616_IRQ_NUM_BASE + 21)
+#define BL616_IRQ_AUADC                             (BL616_IRQ_NUM_BASE + 22)
+#define BL616_IRQ_MJPEG                             (BL616_IRQ_NUM_BASE + 23)
+#define BL616_IRQ_EMAC                              (BL616_IRQ_NUM_BASE + 24)
+#define BL616_IRQ_GPADC_DMA                         (BL616_IRQ_NUM_BASE + 25)
+#define BL616_IRQ_EFUSE                             (BL616_IRQ_NUM_BASE + 26)
+#define BL616_IRQ_SPI0                              (BL616_IRQ_NUM_BASE + 27)
+#define BL616_IRQ_UART0                             (BL616_IRQ_NUM_BASE + 28)
+#define BL616_IRQ_UART1                             (BL616_IRQ_NUM_BASE + 29)
+#define BL616_IRQ_ISO11898                          (BL616_IRQ_NUM_BASE + 30)
+#define BL616_IRQ_GPIO_DMA                          (BL616_IRQ_NUM_BASE + 31)
+#define BL616_IRQ_I2C0                              (BL616_IRQ_NUM_BASE + 32)
+#define BL616_IRQ_PWM                               (BL616_IRQ_NUM_BASE + 33)
+#define BL616_IRQ_RESERVED0                         (BL616_IRQ_NUM_BASE + 34)
+#define BL616_IRQ_RESERVED1                         (BL616_IRQ_NUM_BASE + 35)
+#define BL616_IRQ_TIMER0                            (BL616_IRQ_NUM_BASE + 36)
+#define BL616_IRQ_TIMER1                            (BL616_IRQ_NUM_BASE + 37)
+#define BL616_IRQ_WDG                               (BL616_IRQ_NUM_BASE + 38)
+#define BL616_IRQ_I2C1                              (BL616_IRQ_NUM_BASE + 39)
+#define BL616_IRQ_I2S                               (BL616_IRQ_NUM_BASE + 40)
+#define BL616_IRQ_ANA_OCP_OUT_TO_CPU_0              (BL616_IRQ_NUM_BASE + 41)
+#define BL616_IRQ_ANA_OCP_OUT_TO_CPU_1              (BL616_IRQ_NUM_BASE + 42)
+#define BL616_IRQ_XTAL_RDY_SCAN                     (BL616_IRQ_NUM_BASE + 43)
+#define BL616_IRQ_GPIO_INT0                         (BL616_IRQ_NUM_BASE + 44)
+#define BL616_IRQ_DM                                (BL616_IRQ_NUM_BASE + 45)
+#define BL616_IRQ_BT                                (BL616_IRQ_NUM_BASE + 46)
+#define BL616_IRQ_M154_REQ_ACK                      (BL616_IRQ_NUM_BASE + 47)
+#define BL616_IRQ_M154                              (BL616_IRQ_NUM_BASE + 48)
+#define BL616_IRQ_M154_AES                          (BL616_IRQ_NUM_BASE + 49)
+#define BL616_IRQ_PDS_WAKEUP                        (BL616_IRQ_NUM_BASE + 50)
+#define BL616_IRQ_HBN_OUT0                          (BL616_IRQ_NUM_BASE + 51)
+#define BL616_IRQ_HBN_OUT1                          (BL616_IRQ_NUM_BASE + 52)
+#define BL616_IRQ_BOD                               (BL616_IRQ_NUM_BASE + 53)
+#define BL616_IRQ_WIFI                              (BL616_IRQ_NUM_BASE + 54)
+#define BL616_IRQ_BZ_PHY_INT                        (BL616_IRQ_NUM_BASE + 55)
+#define BL616_IRQ_BLE                               (BL616_IRQ_NUM_BASE + 56)
+#define BL616_IRQ_MAC_INT_TIMER                     (BL616_IRQ_NUM_BASE + 57)
+#define BL616_IRQ_MAC_INT_MISC                      (BL616_IRQ_NUM_BASE + 58)
+#define BL616_IRQ_MAC_INT_RX_TRIGGER                (BL616_IRQ_NUM_BASE + 59)
+#define BL616_IRQ_MAC_INT_TX_TRIGGER                (BL616_IRQ_NUM_BASE + 60)
+#define BL616_IRQ_MAC_INT_GEN                       (BL616_IRQ_NUM_BASE + 61)
+#define BL616_IRQ_MAC_INT_PROT_TRIGGER              (BL616_IRQ_NUM_BASE + 62)
+#define BL616_IRQ_WIFI_IPC                          (BL616_IRQ_NUM_BASE + 63)
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_memorymap.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_memorymap.h
new file mode 100755
index 0000000000..d22c1b6cad
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/bl616_memorymap.h
@@ -0,0 +1,108 @@
+#ifndef __BL616_MEMORYMAP_H
+#define __BL616_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define BL616_OCRAM_BASE                     (0x20FC0000)
+#define BL616_OCRAM_END                      (0x20FC0000 + 320 * 1024)
+#define BL616_OCRAM_CACHEABLE_BASE           (0x60FC0000)
+#define BL616_OCRAM_CACHEABLE_END            (0x60FC0000 + 320 * 1024)
+#define BL616_OCRAM_BUSREMAP_BASE            (0x22FC0000)
+#define BL616_OCRAM_BUSREMAP_END             (0x22FC0000 + 320 * 1024)
+#define BL616_OCRAM_BUSREMAP_CACHEABLE_BASE  (0x62FC0000)
+#define BL616_OCRAM_BUSREMAP_CACHEABLE_END   (0x62FC0000 + 320 * 1024)
+
+#define BL616_WRAM_BASE                      (0x21010000)
+#define BL616_WRAM_END                       (0x21010000 + 160 * 1024)
+#define BL616_WRAM_CACHEABLE_BASE            (0x61010000)
+#define BL616_WRAM_CACHEABLE_END             (0x61010000 + 160 * 1024)
+#define BL616_WRAM_BUSREMAP_BASE             (0x23010000)
+#define BL616_WRAM_BUSREMAP_END              (0x23010000 + 160 * 1024)
+#define BL616_WRAM_BUSREMAP_CACHEABLE_BASE   (0x63010000)
+#define BL616_WRAM_BUSREMAP_CACHEABLE_END    (0x63010000 + 160 * 1024)
+
+#define BL616_FLASH_XIP_BASE                 (0xA0000000)
+#define BL616_FLASH_XIP_END                  (0xA0000000 + 64 * 1024 * 1024)
+#define BL616_FLASH_XIP_REMAP0_BASE          (0xD0000000)
+#define BL616_FLASH_XIP_REMAP0_END           (0xD0000000 + 64 * 1024 * 1024)
+#define BL616_FLASH_XIP_BUSREMAP_BASE        (0xA0000000)
+#define BL616_FLASH_XIP_BUSREMAP_END         (0xA0000000 + 64 * 1024 * 1024)
+
+#define BL616_FLASH2_XIP_BASE                (0x84000000)
+#define BL616_FLASH2_XIP_END                 (0x84000000 + 64 * 1024 * 1024)
+#define BL616_FLASH2_XIP_REMAP0_BASE         (0xD4000000)
+#define BL616_FLASH2_XIP_REMAP0_END          (0xD4000000 + 64 * 1024 * 1024)
+#define BL616_FLASH2_XIP_BUSREMAP_BASE       (0xA4000000)
+#define BL616_FLASH2_XIP_BUSREMAP_END        (0xA4000000 + 64 * 1024 * 1024)
+
+#define BL616_PSRAM_BASE                     (0x88000000)
+#define BL616_PSRAM_END                      (0x88000000 + 128 * 1024 * 1024)
+#define BL616_PSRAM_REMAP0_BASE              (0xD8000000)
+#define BL616_PSRAM_REMAP0_END               (0xD8000000 + 128 * 1024 * 1024)
+#define BL616_PSRAM_BUSREMAP_BASE            (0xA8000000)
+#define BL616_PSRAM_BUSREMAP_END             (0xA8000000 + 128 * 1024 * 1024)
+
+#define BL616_ALLRAM_BASE                    (0x20FC0000)
+#define BL616_ALLRAM_END                     (0x20FC0000 + 320 * 1024 + 160 * 1024)
+#define BL616_ALLRAM_CACHEABLE_BASE          (0x60FC0000)
+#define BL616_ALLRAM_CACHEABLE_END           (0x60FC0000 + 320 * 1024 + 160 * 1024)
+#define BL616_ALLRAM_BUSREMAP_BASE           (0x22FC0000)
+#define BL616_ALLRAM_BUSREMAP_END            (0x22FC0000 + 320 * 1024 + 160 * 1024)
+#define BL616_ALLRAM_BUSREMAP_CACHEABLE_BASE (0x62FC0000)
+#define BL616_ALLRAM_BUSREMAP_CACHEABLE_END  (0x62FC0000 + 320 * 1024 + 160 * 1024)
+
+#define GLB_BASE                             ((uint32_t)0x20000000)
+#define MIX_BASE                             ((uint32_t)0x20001000)
+#define GPIP_BASE                            ((uint32_t)0x20002000)
+#define PHY_BASE                             ((uint32_t)0x20002800)
+#define AGC_BASE                             ((uint32_t)0x20002c00)
+#define SEC_DBG_BASE                         ((uint32_t)0x20003000)
+#define SEC_ENG_BASE                         ((uint32_t)0x20004000)
+#define TZ1_BASE                             ((uint32_t)0x20005000)
+#define TZC_SEC_BASE                         ((uint32_t)0x20005000)
+#define TZ2_BASE                             ((uint32_t)0x20006000)
+#define TZC_NSEC_BASE                        ((uint32_t)0x20006000)
+#define CCI_BASE                             ((uint32_t)0x20008000)
+#define MCU_MISC_BASE                        ((uint32_t)0x20009000)
+#define L1C_BASE                             ((uint32_t)0x20009000)
+#define UART0_BASE                           ((uint32_t)0x2000a000)
+#define UART1_BASE                           ((uint32_t)0x2000a100)
+#define SPI_BASE                             ((uint32_t)0x2000a200)
+#define I2C0_BASE                            ((uint32_t)0x2000a300)
+#define PWM_BASE                             ((uint32_t)0x2000a400)
+#define TIMER_BASE                           ((uint32_t)0x2000a500)
+#define IR_BASE                              ((uint32_t)0x2000a600)
+#define CKS_BASE                             ((uint32_t)0x2000a700)
+#define DBI_BASE                             ((uint32_t)0x2000a800)
+#define I2C1_BASE                            ((uint32_t)0x2000a900)
+#define ISO11898_BASE                        ((uint32_t)0x2000aa00)
+#define I2S_BASE                             ((uint32_t)0x2000ab00)
+#define AUADC_BASE                           ((uint32_t)0x2000ac00)
+#define QSPI_BASE                            ((uint32_t)0x2000b000)
+#define SF_CTRL_BASE                         ((uint32_t)0x2000b000)
+#define SF_CTRL_BUF_BASE                     ((uint32_t)0x2000b600)
+#define DMA_BASE                             ((uint32_t)0x2000c000)
+#define SDU_BASE                             ((uint32_t)0x2000d000)
+#define PDS_BASE                             ((uint32_t)0x2000e000)
+#define HBN_BASE                             ((uint32_t)0x2000f000)
+#define AON_BASE                             ((uint32_t)0x2000f000)
+#define MM_MISC_BASE                         ((uint32_t)0x20050000)
+#define PSRAM_CTRL_BASE                      ((uint32_t)0x20052000)
+#define AUDAC_BASE                           ((uint32_t)0x20055000)
+#define EFUSE_BASE                           ((uint32_t)0x20056000)
+#define EF_DATA_BASE                         ((uint32_t)0x20056000)
+#define EF_CTRL_BASE                         ((uint32_t)0x20056000)
+#define DVP2AXI0_BASE                        ((uint32_t)0x20057000)
+#define DVP2AXI1_BASE                        ((uint32_t)0x20058000)
+#define MJPEG_BASE                           ((uint32_t)0x20059000)
+#define SDH_BASE                             ((uint32_t)0x20060000)
+#define EMAC_BASE                            ((uint32_t)0x20070000)
+#define USB_BASE                             ((uint32_t)0x20072000)
+#define HBN_RAM_BASE                         ((uint32_t)0x20010000)
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/device_table.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/device_table.c
new file mode 100755
index 0000000000..c972011ae7
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl616/device_table.c
@@ -0,0 +1,288 @@
+#include "bflb_core.h"
+#include "bl616_memorymap.h"
+#include "bl616_irq.h"
+
+#define DMA_CHANNEL_OFFSET 0x100
+
+struct bflb_device_s bl616_device_table[] = {
+    { .name = "adc",
+      .reg_base = AON_BASE,
+      .irq_num = BL616_IRQ_GPADC_DMA,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ADC,
+      .user_data = NULL },
+    { .name = "dac",
+      .reg_base = GLB_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DAC,
+      .user_data = NULL },
+    { .name = "ef_ctrl",
+      .reg_base = EF_CTRL_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_EF_CTRL,
+      .user_data = NULL },
+    { .name = "gpio",
+      .reg_base = GLB_BASE,
+      .irq_num = BL616_IRQ_GPIO_INT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_GPIO,
+      .user_data = NULL },
+    { .name = "uart0",
+      .reg_base = UART0_BASE,
+      .irq_num = BL616_IRQ_UART0,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart1",
+      .reg_base = UART1_BASE,
+      .irq_num = BL616_IRQ_UART1,
+      .idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "iso11898",
+      .reg_base = ISO11898_BASE,
+      .irq_num = BL616_IRQ_ISO11898,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ISO11898,
+      .user_data = NULL },
+    { .name = "spi0",
+      .reg_base = SPI_BASE,
+      .irq_num = BL616_IRQ_SPI0,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SPI,
+      .user_data = NULL },
+    { .name = "pwm_v2_0",
+      .reg_base = PWM_BASE,
+      .irq_num = BL616_IRQ_PWM,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PWM,
+      .user_data = NULL },
+    { .name = "dma0_ch0",
+      .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch1",
+      .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch2",
+      .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 2,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch3",
+      .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 3,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch4",
+      .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 4,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch5",
+      .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 5,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch6",
+      .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 6,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch7",
+      .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL616_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 7,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "i2c0",
+      .reg_base = I2C0_BASE,
+      .irq_num = BL616_IRQ_I2C0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_I2C,
+      .user_data = NULL },
+    { .name = "i2s0",
+      .reg_base = I2S_BASE,
+      .irq_num = BL616_IRQ_I2S,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_I2S,
+      .user_data = NULL },
+    { .name = "timer0",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL616_IRQ_TIMER0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "timer1",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL616_IRQ_TIMER1,
+      .idx = 1,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "rtc",
+      .reg_base = HBN_BASE,
+      .irq_num = BL616_IRQ_HBN_OUT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_RTC,
+      .user_data = NULL },
+    { .name = "aes",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_AES,
+      .user_data = NULL },
+    { .name = "sha",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SHA,
+      .user_data = NULL },
+    { .name = "trng",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TRNG,
+      .user_data = NULL },
+    { .name = "pka",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PKA,
+      .user_data = NULL },
+    { .name = "emac0",
+      .reg_base = EMAC_BASE,
+      .irq_num = BL616_IRQ_EMAC,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ETH,
+      .user_data = NULL },
+    { .name = "watchdog",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL616_IRQ_WDG,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "cks",
+      .reg_base = CKS_BASE,
+      .irq_num = 0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CKS,
+      .user_data = NULL },
+    { .name = "mjpeg",
+      .reg_base = MJPEG_BASE,
+      .irq_num = BL616_IRQ_MJPEG,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_MJPEG,
+      .user_data = NULL },
+    { .name = "irrx",
+      .reg_base = IR_BASE,
+      .irq_num = BL616_IRQ_IRRX,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_IR,
+      .user_data = NULL },
+    { .name = "cam0",
+      .reg_base = DVP2AXI0_BASE,
+      .irq_num = BL616_IRQ_DVP2BUS_INT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam1",
+      .reg_base = DVP2AXI1_BASE,
+      .irq_num = BL616_IRQ_DVP2BUS_INT1,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "auadc",
+      .reg_base = AUADC_BASE,
+      .irq_num = BL616_IRQ_AUADC,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_AUDIOADC,
+      .user_data = NULL },
+    { .name = "audac",
+      .reg_base = AUDAC_BASE,
+      .irq_num = BL616_IRQ_AUDAC,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_AUDIODAC,
+      .user_data = NULL },
+    { .name = "sdio2",
+      .reg_base = SDU_BASE,
+      .irq_num = BL616_IRQ_SDIO,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SDIO2,
+      .user_data = NULL },
+    { .name = "dbi",
+      .reg_base = DBI_BASE,
+      .irq_num = BL616_IRQ_DBI,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DBI,
+      .user_data = NULL },
+};
+
+struct bflb_device_s *bflb_device_get_by_name(const char *name)
+{
+    for (uint8_t i = 0; i < sizeof(bl616_device_table) / sizeof(bl616_device_table[0]); i++) {
+        if (strcmp(bl616_device_table[i].name, name) == 0) {
+            return &bl616_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx)
+{
+    for (uint8_t i = 0; i < sizeof(bl616_device_table) / sizeof(bl616_device_table[0]); i++) {
+        if ((bl616_device_table[i].dev_type == type) && (bl616_device_table[i].idx = idx)) {
+            return &bl616_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data)
+{
+    device->user_data = user_data;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/bl702_irq.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/bl702_irq.h
new file mode 100755
index 0000000000..e92fa4074e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/bl702_irq.h
@@ -0,0 +1,84 @@
+#ifndef __BL702_IRQ_H
+#define __BL702_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BL702_IRQ_NUM_BASE 16
+
+#define BL702_IRQ_MSOFT          3
+#define BL702_IRQ_MTIME          7
+#define BL702_IRQ_MEXT           11
+#define BL702_IRQ_CLIC_SOFT_PEND 12
+
+#define BL702_IRQ_BMX_MCU_BUS_ERR      (BL702_IRQ_NUM_BASE + 0)
+#define BL702_IRQ_BMX_MCU_TO           (BL702_IRQ_NUM_BASE + 1)
+#define BL702_IRQ_L1C_BMX_ERR          (BL702_IRQ_NUM_BASE + 2)
+#define BL702_IRQ_L1C_BMX_TO           (BL702_IRQ_NUM_BASE + 3)
+#define BL702_IRQ_SEC_BMX_ERR          (BL702_IRQ_NUM_BASE + 4)
+#define BL702_IRQ_RF_TOP_INT0          (BL702_IRQ_NUM_BASE + 5)
+#define BL702_IRQ_RF_TOP_INT1          (BL702_IRQ_NUM_BASE + 6)
+#define BL702_IRQ_RESERVED0            (BL702_IRQ_NUM_BASE + 7)
+#define BL702_IRQ_DMA_BMX_ERR          (BL702_IRQ_NUM_BASE + 8)
+#define BL702_IRQ_SEC_GMAC             (BL702_IRQ_NUM_BASE + 9)
+#define BL702_IRQ_SEC_CDET             (BL702_IRQ_NUM_BASE + 10)
+#define BL702_IRQ_SEC_PKA              (BL702_IRQ_NUM_BASE + 11)
+#define BL702_IRQ_SEC_TRNG             (BL702_IRQ_NUM_BASE + 12)
+#define BL702_IRQ_SEC_AES              (BL702_IRQ_NUM_BASE + 13)
+#define BL702_IRQ_SEC_SHA              (BL702_IRQ_NUM_BASE + 14)
+#define BL702_IRQ_DMA0_ALL             (BL702_IRQ_NUM_BASE + 15)
+#define BL702_IRQ_MJPEG                (BL702_IRQ_NUM_BASE + 16)
+#define BL702_IRQ_CAM                  (BL702_IRQ_NUM_BASE + 17)
+#define BL702_IRQ_I2S                  (BL702_IRQ_NUM_BASE + 18)
+#define BL702_IRQ_IRTX                 (BL702_IRQ_NUM_BASE + 19)
+#define BL702_IRQ_IRRX                 (BL702_IRQ_NUM_BASE + 20)
+#define BL702_IRQ_USB                  (BL702_IRQ_NUM_BASE + 21)
+#define BL702_IRQ_EMAC                 (BL702_IRQ_NUM_BASE + 22)
+#define BL702_IRQ_SF_CTRL              (BL702_IRQ_NUM_BASE + 23)
+#define BL702_IRQ_RESERVED1            (BL702_IRQ_NUM_BASE + 24)
+#define BL702_IRQ_GPADC_DMA            (BL702_IRQ_NUM_BASE + 25)
+#define BL702_IRQ_EFUSE                (BL702_IRQ_NUM_BASE + 26)
+#define BL702_IRQ_SPI0                 (BL702_IRQ_NUM_BASE + 27)
+#define BL702_IRQ_RESERVED2            (BL702_IRQ_NUM_BASE + 28)
+#define BL702_IRQ_UART0                (BL702_IRQ_NUM_BASE + 29)
+#define BL702_IRQ_UART1                (BL702_IRQ_NUM_BASE + 30)
+#define BL702_IRQ_RESERVED3            (BL702_IRQ_NUM_BASE + 31)
+#define BL702_IRQ_I2C0                 (BL702_IRQ_NUM_BASE + 32)
+#define BL702_IRQ_RESERVED4            (BL702_IRQ_NUM_BASE + 33)
+#define BL702_IRQ_PWM                  (BL702_IRQ_NUM_BASE + 34)
+#define BL702_IRQ_RESERVED5            (BL702_IRQ_NUM_BASE + 35)
+#define BL702_IRQ_TIMER0               (BL702_IRQ_NUM_BASE + 36)
+#define BL702_IRQ_TIMER1               (BL702_IRQ_NUM_BASE + 37)
+#define BL702_IRQ_WDT                  (BL702_IRQ_NUM_BASE + 38)
+#define BL702_IRQ_KYS                  (BL702_IRQ_NUM_BASE + 39)
+#define BL702_IRQ_QDEC0                (BL702_IRQ_NUM_BASE + 40)
+#define BL702_IRQ_QDEC1                (BL702_IRQ_NUM_BASE + 41)
+#define BL702_IRQ_QDEC2                (BL702_IRQ_NUM_BASE + 42)
+#define BL702_IRQ_RESERVED6            (BL702_IRQ_NUM_BASE + 43)
+#define BL702_IRQ_GPIO_INT0            (BL702_IRQ_NUM_BASE + 44)
+#define BL702_IRQ_TOUCH                (BL702_IRQ_NUM_BASE + 45)
+#define BL702_IRQ_RESERVED7            (BL702_IRQ_NUM_BASE + 46)
+#define BL702_IRQ_M154_REQ_ENH_ACK     (BL702_IRQ_NUM_BASE + 47)
+#define BL702_IRQ_M154                 (BL702_IRQ_NUM_BASE + 48)
+#define BL702_IRQ_M154_AES             (BL702_IRQ_NUM_BASE + 49)
+#define BL702_IRQ_PDS_WAKEUP           (BL702_IRQ_NUM_BASE + 50)
+#define BL702_IRQ_HBN_OUT0             (BL702_IRQ_NUM_BASE + 51)
+#define BL702_IRQ_HBN_OUT1             (BL702_IRQ_NUM_BASE + 52)
+#define BL702_IRQ_BOR                  (BL702_IRQ_NUM_BASE + 53)
+#define BL702_IRQ_WIFI                 (BL702_IRQ_NUM_BASE + 54)
+#define BL616_IRQ_BZ_PHY_INT           (BL702_IRQ_NUM_BASE + 55)
+#define BL702_IRQ_BLE                  (BL702_IRQ_NUM_BASE + 56)
+#define BL702_IRQ_MAC_INT_TIMER        (BL702_IRQ_NUM_BASE + 57)
+#define BL702_IRQ_MAC_INT_MISC         (BL702_IRQ_NUM_BASE + 58)
+#define BL702_IRQ_MAC_INT_RX_TRIGGER   (BL702_IRQ_NUM_BASE + 59)
+#define BL702_IRQ_MAC_INT_TX_TRIGGER   (BL702_IRQ_NUM_BASE + 60)
+#define BL702_IRQ_MAC_INT_GEN          (BL702_IRQ_NUM_BASE + 61)
+#define BL702_IRQ_MAC_INT_PROT_TRIGGER (BL702_IRQ_NUM_BASE + 62)
+#define BL702_IRQ_WIFI_IPC             (BL702_IRQ_NUM_BASE + 63)
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/bl702_memorymap.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/bl702_memorymap.h
new file mode 100755
index 0000000000..821a346af3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/bl702_memorymap.h
@@ -0,0 +1,89 @@
+#ifndef __BL702_MEMORYMAP_H
+#define __BL702_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define BL702_FLASH_XIP_BASE        0x23000000
+#define BL702_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL702_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL702_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL702_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)
+
+#define BL702_PSRAM_XIP_BASE        0x24000000
+#define BL702_PSRAM_XIP_END         (0x24000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP0_BASE 0x34000000
+#define BL702_PSRAM_XIP_REMAP0_END  (0x34000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP1_BASE 0x44000000
+#define BL702_PSRAM_XIP_REMAP1_END  (0x44000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP2_BASE 0x54000000
+#define BL702_PSRAM_XIP_REMAP2_END  (0x54000000 + 16 * 1024 * 1024)
+
+#define BL702_WRAM_BASE        0x42020000
+#define BL702_WRAM_END         (0x42020000 + 56 * 1024)
+#define BL702_WRAM_REMAP0_BASE 0x22020000
+#define BL702_WRAM_REMAP0_END  (0x22020000 + 56 * 1024)
+#define BL702_WRAM_REMAP1_BASE 0x32020000
+#define BL702_WRAM_REMAP1_END  (0x32020000 + 56 * 1024)
+#define BL702_WRAM_REMAP2_BASE 0x52020000
+#define BL702_WRAM_REMAP2_END  (0x52020000 + 56 * 1024)
+
+#define BL702_TCM_BASE        0x22010000
+#define BL702_TCM_END         (0x22010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP0_BASE 0x32010000
+#define BL702_TCM_REMAP0_END  (0x32010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP1_BASE 0x42010000
+#define BL702_TCM_REMAP1_END  (0x42010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP2_BASE 0x52010000
+#define BL702_TCM_REMAP2_END  (0x52010000 + (16 + 48) * 1024)
+/*@} end of group Memory_Map_Section */
+
+/* BL702 peripherals base address */
+#define GLB_BASE         ((uint32_t)0x40000000)
+#define RF_BASE          ((uint32_t)0x40001000)
+#define BZ_PHY_BASE      ((uint32_t)0x40001000)
+#define BZ_PHY_AGC_BASE  ((uint32_t)0x40001000)
+#define GPIP_BASE        ((uint32_t)0x40002000) /*!< AUX module base address */
+#define SEC_DBG_BASE     ((uint32_t)0x40003000) /*!< Security Debug module base address */
+#define SEC_ENG_BASE     ((uint32_t)0x40004000) /*!< Security Engine module base address */
+#define TZC_SEC_BASE     ((uint32_t)0x40005000) /*!< Trustzone control security base address */
+#define TZC_NSEC_BASE    ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
+#define EF_DATA_BASE     ((uint32_t)0x40007000)
+#define EF_CTRL_BASE     ((uint32_t)0x40007000)
+#define CCI_BASE         ((uint32_t)0x40008000)
+#define L1C_BASE         ((uint32_t)0x40009000) /*!< L1 cache config base address */
+#define UART0_BASE       ((uint32_t)0x4000A000)
+#define UART1_BASE       ((uint32_t)0x4000A100)
+#define SPI_BASE         ((uint32_t)0x4000A200)
+#define I2C_BASE         ((uint32_t)0x4000A300)
+#define PWM_BASE         ((uint32_t)0x4000A400)
+#define TIMER_BASE       ((uint32_t)0x4000A500)
+#define IR_BASE          ((uint32_t)0x4000A600)
+#define CKS_BASE         ((uint32_t)0x4000A700)
+#define QDEC0_BASE       ((uint32_t)0x4000A800)
+#define QDEC1_BASE       ((uint32_t)0x4000A840)
+#define QDEC2_BASE       ((uint32_t)0x4000A880)
+#define KYS_BASE         ((uint32_t)0x4000A900)
+#define I2S_BASE         ((uint32_t)0x4000AA00)
+#define CAM_BASE         ((uint32_t)0x4000AD00)
+#define MJPEG_BASE       ((uint32_t)0x4000AE00)
+#define SF_CTRL_BASE     ((uint32_t)0x4000B000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#define DMA_BASE         ((uint32_t)0x4000C000)
+#define EMAC_BASE        ((uint32_t)0x4000D000)
+#define USB_BASE         ((uint32_t)0x4000D800)
+#define PDS_BASE         ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
+#define HBN_BASE         ((uint32_t)0x4000F000) /*!< Hibernate module base address */
+#define AON_BASE         ((uint32_t)0x4000F000) /*!< Always on module base address */
+#define MAC154_BASE      ((uint32_t)0x4C000000) /*!< MAC154 module base address */
+
+#define HBN_RAM_BASE ((uint32_t)0x40010000)
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/device_table.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/device_table.c
new file mode 100755
index 0000000000..44a8ae77ca
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl702/device_table.c
@@ -0,0 +1,239 @@
+#include "bflb_core.h"
+#include "bl702_irq.h"
+#include "bl702_memorymap.h"
+
+#define DMA_CHANNEL_OFFSET 0x100
+
+struct bflb_device_s bl702_device_table[] = {
+    { .name = "adc",
+      .reg_base = AON_BASE,
+      .irq_num = BL702_IRQ_GPADC_DMA,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ADC,
+      .user_data = NULL },
+    { .name = "dac",
+      .reg_base = GLB_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DAC,
+      .user_data = NULL },
+    { .name = "ef_ctrl",
+      .reg_base = EF_CTRL_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_EF_CTRL,
+      .user_data = NULL },
+    { .name = "gpio",
+      .reg_base = GLB_BASE,
+      .irq_num = BL702_IRQ_GPIO_INT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_GPIO,
+      .user_data = NULL },
+    { .name = "uart0",
+      .reg_base = UART0_BASE,
+      .irq_num = BL702_IRQ_UART0,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart1",
+      .reg_base = UART1_BASE,
+      .irq_num = BL702_IRQ_UART1,
+      .idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "spi0",
+      .reg_base = SPI_BASE,
+      .irq_num = BL702_IRQ_SPI0,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SPI,
+      .user_data = NULL },
+    { .name = "pwm_v1",
+      .reg_base = PWM_BASE,
+      .irq_num = BL702_IRQ_PWM,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PWM,
+      .user_data = NULL },
+    { .name = "dma0_ch0",
+      .reg_base = DMA_BASE + 1 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch1",
+      .reg_base = DMA_BASE + 2 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch2",
+      .reg_base = DMA_BASE + 3 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 2,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch3",
+      .reg_base = DMA_BASE + 4 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 3,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch4",
+      .reg_base = DMA_BASE + 5 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 4,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch5",
+      .reg_base = DMA_BASE + 6 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 5,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch6",
+      .reg_base = DMA_BASE + 7 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 6,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch7",
+      .reg_base = DMA_BASE + 8 * DMA_CHANNEL_OFFSET,
+      .irq_num = BL702_IRQ_DMA0_ALL,
+      .idx = 0,
+      .sub_idx = 7,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "i2c0",
+      .reg_base = I2C_BASE,
+      .irq_num = BL702_IRQ_I2C0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_I2C,
+      .user_data = NULL },
+    { .name = "timer0",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL702_IRQ_TIMER0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "timer1",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL702_IRQ_TIMER1,
+      .idx = 1,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "rtc",
+      .reg_base = HBN_BASE,
+      .irq_num = BL702_IRQ_HBN_OUT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_RTC,
+      .user_data = NULL },
+    { .name = "aes",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_AES,
+      .user_data = NULL },
+    { .name = "sha",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SHA,
+      .user_data = NULL },
+    { .name = "trng",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TRNG,
+      .user_data = NULL },
+    { .name = "pka",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PKA,
+      .user_data = NULL },
+    { .name = "emac0",
+      .reg_base = EMAC_BASE,
+      .irq_num = BL702_IRQ_EMAC,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ETH,
+      .user_data = NULL },
+    { .name = "watchdog",
+      .reg_base = TIMER_BASE,
+      .irq_num = BL702_IRQ_WDT,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "irtx",
+      .reg_base = IR_BASE,
+      .irq_num = BL702_IRQ_IRTX,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_IR,
+      .user_data = NULL },
+    { .name = "irrx",
+      .reg_base = IR_BASE,
+      .irq_num = BL702_IRQ_IRRX,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_IR,
+      .user_data = NULL },
+    { .name = "kys0",
+      .reg_base = KYS_BASE,
+      .irq_num = BL702_IRQ_KYS,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_KYS,
+      .user_data = NULL },
+    { .name = "cam0",
+      .reg_base = CAM_BASE,
+      .irq_num = BL702_IRQ_CAM,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+};
+
+struct bflb_device_s *bflb_device_get_by_name(const char *name)
+{
+    for (uint8_t i = 0; i < sizeof(bl702_device_table) / sizeof(bl702_device_table[0]); i++) {
+        if (strcmp(bl702_device_table[i].name, name) == 0) {
+            return &bl702_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx)
+{
+    for (uint8_t i = 0; i < sizeof(bl702_device_table) / sizeof(bl702_device_table[0]); i++) {
+        if ((bl702_device_table[i].dev_type == type) && (bl702_device_table[i].idx = idx)) {
+            return &bl702_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data)
+{
+    device->user_data = user_data;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_irq.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_irq.h
new file mode 100755
index 0000000000..406b8ae5f0
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_irq.h
@@ -0,0 +1,160 @@
+#ifndef __BL808_IRQ_H
+#define __BL808_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+#define BL808_IRQ_NUM_BASE       16
+
+#define BL808_IRQ_SSOFT          1
+#define BL808_IRQ_MSOFT          3
+#define BL808_IRQ_STIME          5
+#define BL808_IRQ_MTIME          7
+#define BL808_IRQ_SEXT           9
+#define BL808_IRQ_MEXT           11
+#define BL808_IRQ_CLIC_SOFT_PEND 12
+#if (__riscv_xlen == 64)
+#define BL808_IRQ_HPM_OVF 17
+#endif
+
+#if defined(CPU_M0) || defined(CPU_LP)
+#define BL808_IRQ_BMX_MCU_BUS_ERR                   (BL808_IRQ_NUM_BASE + 0)
+#define BL808_IRQ_BMX_MCU_TO                        (BL808_IRQ_NUM_BASE + 1)
+#define BL808_IRQ_M0_RESERVED2                      (BL808_IRQ_NUM_BASE + 2)
+#define BL808_IRQ_IPC_M0                            (BL808_IRQ_NUM_BASE + 3)
+#define BL808_IRQ_AUDIO                             (BL808_IRQ_NUM_BASE + 4)
+#define BL808_IRQ_RF_TOP_INT0                       (BL808_IRQ_NUM_BASE + 5)
+#define BL808_IRQ_RF_TOP_INT1                       (BL808_IRQ_NUM_BASE + 6)
+#define BL808_IRQ_LZ4D                              (BL808_IRQ_NUM_BASE + 7)
+#define BL808_IRQ_GAUGE_ITF                         (BL808_IRQ_NUM_BASE + 8)
+#define BL808_IRQ_SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC (BL808_IRQ_NUM_BASE + 9)
+#define BL808_IRQ_SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC (BL808_IRQ_NUM_BASE + 10)
+#define BL808_IRQ_SEC_ENG_ID1_CDET                  (BL808_IRQ_NUM_BASE + 11)
+#define BL808_IRQ_SEC_ENG_ID0_CDET                  (BL808_IRQ_NUM_BASE + 12)
+#define BL808_IRQ_SF_CTRL_ID1                       (BL808_IRQ_NUM_BASE + 13)
+#define BL808_IRQ_SF_CTRL_ID0                       (BL808_IRQ_NUM_BASE + 14)
+#define BL808_IRQ_DMA0_ALL                          (BL808_IRQ_NUM_BASE + 15)
+#define BL808_IRQ_DMA1_ALL                          (BL808_IRQ_NUM_BASE + 16)
+#define BL808_IRQ_SDH                               (BL808_IRQ_NUM_BASE + 17)
+#define BL808_IRQ_MM_ALL                            (BL808_IRQ_NUM_BASE + 18)
+#define BL808_IRQ_IRTX                              (BL808_IRQ_NUM_BASE + 19)
+#define BL808_IRQ_IRRX                              (BL808_IRQ_NUM_BASE + 20)
+#define BL808_IRQ_USB                               (BL808_IRQ_NUM_BASE + 21)
+#define BL808_IRQ_AUPDM_TOUCH                       (BL808_IRQ_NUM_BASE + 22)
+#define BL808_IRQ_M0_RESERVED23                     (BL808_IRQ_NUM_BASE + 23)
+#define BL808_IRQ_EMAC                              (BL808_IRQ_NUM_BASE + 24)
+#define BL808_IRQ_GPADC_DMA                         (BL808_IRQ_NUM_BASE + 25)
+#define BL808_IRQ_EFUSE                             (BL808_IRQ_NUM_BASE + 26)
+#define BL808_IRQ_SPI0                              (BL808_IRQ_NUM_BASE + 27)
+#define BL808_IRQ_UART0                             (BL808_IRQ_NUM_BASE + 28)
+#define BL808_IRQ_UART1                             (BL808_IRQ_NUM_BASE + 29)
+#define BL808_IRQ_UART2                             (BL808_IRQ_NUM_BASE + 30)
+#define BL808_IRQ_GPIO_DMA                          (BL808_IRQ_NUM_BASE + 31)
+#define BL808_IRQ_I2C0                              (BL808_IRQ_NUM_BASE + 32)
+#define BL808_IRQ_PWM                               (BL808_IRQ_NUM_BASE + 33)
+#define BL808_IRQ_IPC_RSVD                          (BL808_IRQ_NUM_BASE + 34)
+#define BL808_IRQ_IPC_LP                            (BL808_IRQ_NUM_BASE + 35)
+#define BL808_IRQ_TIMER0                            (BL808_IRQ_NUM_BASE + 36)
+#define BL808_IRQ_TIMER1                            (BL808_IRQ_NUM_BASE + 37)
+#define BL808_IRQ_WDT                               (BL808_IRQ_NUM_BASE + 38)
+#define BL808_IRQ_I2C1                              (BL808_IRQ_NUM_BASE + 39)
+#define BL808_IRQ_I2S                               (BL808_IRQ_NUM_BASE + 40)
+#define BL808_IRQ_ANA_OCP_OUT_TO_CPU_0              (BL808_IRQ_NUM_BASE + 41)
+#define BL808_IRQ_ANA_OCP_OUT_TO_CPU_1              (BL808_IRQ_NUM_BASE + 42)
+#define BL808_IRQ_ANA_OCP_OUT_TO_CPU_2              (BL808_IRQ_NUM_BASE + 43)
+#define BL808_IRQ_GPIO_INT0                         (BL808_IRQ_NUM_BASE + 44)
+#define BL808_IRQ_DM                                (BL808_IRQ_NUM_BASE + 45)
+#define BL808_IRQ_BT                                (BL808_IRQ_NUM_BASE + 46)
+#define BL808_IRQ_M154_REQ_ACK                      (BL808_IRQ_NUM_BASE + 47)
+#define BL808_IRQ_M154                              (BL808_IRQ_NUM_BASE + 48)
+#define BL808_IRQ_M154_AES                          (BL808_IRQ_NUM_BASE + 49)
+#define BL808_IRQ_PDS_WAKEUP                        (BL808_IRQ_NUM_BASE + 50)
+#define BL808_IRQ_HBN_OUT0                          (BL808_IRQ_NUM_BASE + 51)
+#define BL808_IRQ_HBN_OUT1                          (BL808_IRQ_NUM_BASE + 52)
+#define BL808_IRQ_BOD                               (BL808_IRQ_NUM_BASE + 53)
+#define BL808_IRQ_WIFI                              (BL808_IRQ_NUM_BASE + 54)
+#define BL808_IRQ_BZ_PHY_INT                        (BL808_IRQ_NUM_BASE + 55)
+#define BL808_IRQ_BLE                               (BL808_IRQ_NUM_BASE + 56)
+#define BL808_IRQ_MAC_INT_TIMER                     (BL808_IRQ_NUM_BASE + 57)
+#define BL808_IRQ_MAC_INT_MISC                      (BL808_IRQ_NUM_BASE + 58)
+#define BL808_IRQ_MAC_INT_RX_TRIGGER                (BL808_IRQ_NUM_BASE + 59)
+#define BL808_IRQ_MAC_INT_TX_TRIGGER                (BL808_IRQ_NUM_BASE + 60)
+#define BL808_IRQ_MAC_INT_GEN                       (BL808_IRQ_NUM_BASE + 61)
+#define BL808_IRQ_MAC_INT_PROT_TRIGGER              (BL808_IRQ_NUM_BASE + 62)
+#define BL808_IRQ_WIFI_IPC                          (BL808_IRQ_NUM_BASE + 63)
+#else
+#define BL808_IRQ_BMX_DSP_BUS_ERR (BL808_IRQ_NUM_BASE + 0)
+#define BL808_IRQ_D0_RESERVED1    (BL808_IRQ_NUM_BASE + 1)
+#define BL808_IRQ_D0_RESERVED2    (BL808_IRQ_NUM_BASE + 2)
+#define BL808_IRQ_D0_RESERVED3    (BL808_IRQ_NUM_BASE + 3)
+#define BL808_IRQ_UART3           (BL808_IRQ_NUM_BASE + 4)
+#define BL808_IRQ_I2C2            (BL808_IRQ_NUM_BASE + 5)
+#define BL808_IRQ_I2C3            (BL808_IRQ_NUM_BASE + 6)
+#define BL808_IRQ_SPI1            (BL808_IRQ_NUM_BASE + 7)
+#define BL808_IRQ_D0_RESERVED4    (BL808_IRQ_NUM_BASE + 8)
+#define BL808_IRQ_D0_RESERVED5    (BL808_IRQ_NUM_BASE + 9)
+#define BL808_IRQ_SEOF_INT0       (BL808_IRQ_NUM_BASE + 10)
+#define BL808_IRQ_SEOF_INT1       (BL808_IRQ_NUM_BASE + 11)
+#define BL808_IRQ_SEOF_INT2       (BL808_IRQ_NUM_BASE + 12)
+#define BL808_IRQ_DVP2BUS_INT0    (BL808_IRQ_NUM_BASE + 13)
+#define BL808_IRQ_DVP2BUS_INT1    (BL808_IRQ_NUM_BASE + 14)
+#define BL808_IRQ_DVP2BUS_INT2    (BL808_IRQ_NUM_BASE + 15)
+#define BL808_IRQ_DVP2BUS_INT3    (BL808_IRQ_NUM_BASE + 16)
+#define BL808_IRQ_H264_BS         (BL808_IRQ_NUM_BASE + 17)
+#define BL808_IRQ_H264_FRAME      (BL808_IRQ_NUM_BASE + 18)
+#define BL808_IRQ_H264_SEQ_DONE   (BL808_IRQ_NUM_BASE + 19)
+#define BL808_IRQ_MJPEG           (BL808_IRQ_NUM_BASE + 20)
+#define BL808_IRQ_H264_S_BS       (BL808_IRQ_NUM_BASE + 21)
+#define BL808_IRQ_H264_S_FRAME    (BL808_IRQ_NUM_BASE + 22)
+#define BL808_IRQ_H264_S_SEQ_DONE (BL808_IRQ_NUM_BASE + 23)
+#define BL808_IRQ_DMA2_INT0       (BL808_IRQ_NUM_BASE + 24)
+#define BL808_IRQ_DMA2_INT1       (BL808_IRQ_NUM_BASE + 25)
+#define BL808_IRQ_DMA2_INT2       (BL808_IRQ_NUM_BASE + 26)
+#define BL808_IRQ_DMA2_INT3       (BL808_IRQ_NUM_BASE + 27)
+#define BL808_IRQ_DMA2_INT4       (BL808_IRQ_NUM_BASE + 28)
+#define BL808_IRQ_DMA2_INT5       (BL808_IRQ_NUM_BASE + 29)
+#define BL808_IRQ_DMA2_INT6       (BL808_IRQ_NUM_BASE + 30)
+#define BL808_IRQ_DMA2_INT7       (BL808_IRQ_NUM_BASE + 31)
+#define BL808_IRQ_D0_RESERVED6    (BL808_IRQ_NUM_BASE + 32)
+#define BL808_IRQ_D0_RESERVED7    (BL808_IRQ_NUM_BASE + 33)
+#define BL808_IRQ_D0_RESERVED8    (BL808_IRQ_NUM_BASE + 34)
+#define BL808_IRQ_D0_RESERVED9    (BL808_IRQ_NUM_BASE + 35)
+#define BL808_IRQ_D0_RESERVED10   (BL808_IRQ_NUM_BASE + 36)
+#define BL808_IRQ_MIPI_CSI        (BL808_IRQ_NUM_BASE + 37)
+#define BL808_IRQ_IPC_D0          (BL808_IRQ_NUM_BASE + 38)
+#define BL808_IRQ_D0_RESERVED11   (BL808_IRQ_NUM_BASE + 39)
+#define BL808_IRQ_MJDEC           (BL808_IRQ_NUM_BASE + 40)
+#define BL808_IRQ_DVP2BUS_INT4    (BL808_IRQ_NUM_BASE + 41)
+#define BL808_IRQ_DVP2BUS_INT5    (BL808_IRQ_NUM_BASE + 42)
+#define BL808_IRQ_DVP2BUS_INT6    (BL808_IRQ_NUM_BASE + 43)
+#define BL808_IRQ_DVP2BUS_INT7    (BL808_IRQ_NUM_BASE + 44)
+#define BL808_IRQ_DMA2D_INT0      (BL808_IRQ_NUM_BASE + 45)
+#define BL808_IRQ_DMA2D_INT1      (BL808_IRQ_NUM_BASE + 46)
+#define BL808_IRQ_DISPLAY         (BL808_IRQ_NUM_BASE + 47)
+#define BL808_IRQ_PWM             (BL808_IRQ_NUM_BASE + 48)
+#define BL808_IRQ_SEOF_INT3       (BL808_IRQ_NUM_BASE + 49)
+#define BL808_IRQ_D0_RESERVED12   (BL808_IRQ_NUM_BASE + 50)
+#define BL808_IRQ_D0_RESERVED13   (BL808_IRQ_NUM_BASE + 51)
+#define BL808_IRQ_OSD             (BL808_IRQ_NUM_BASE + 52)
+#define BL808_IRQ_DBI             (BL808_IRQ_NUM_BASE + 53)
+#define BL808_IRQ_D0_RESERVED14   (BL808_IRQ_NUM_BASE + 54)
+#define BL808_IRQ_OSDA_BUS_DRAIN  (BL808_IRQ_NUM_BASE + 55)
+#define BL808_IRQ_OSDB_BUS_DRAIN  (BL808_IRQ_NUM_BASE + 56)
+#define BL808_IRQ_OSD_PB          (BL808_IRQ_NUM_BASE + 57)
+#define BL808_IRQ_D0_RESERVED15   (BL808_IRQ_NUM_BASE + 58)
+#define BL808_IRQ_MIPI_DSI        (BL808_IRQ_NUM_BASE + 59)
+#define BL808_IRQ_D0_RESERVED16   (BL808_IRQ_NUM_BASE + 60)
+#define BL808_IRQ_TIMER0          (BL808_IRQ_NUM_BASE + 61)
+#define BL808_IRQ_TIMER1          (BL808_IRQ_NUM_BASE + 62)
+#define BL808_IRQ_WDT             (BL808_IRQ_NUM_BASE + 63)
+#define BL808_IRQ_AUDIO           (BL808_IRQ_NUM_BASE + 64)
+#define BL808_IRQ_WL_ALL          (BL808_IRQ_NUM_BASE + 65)
+#define BL808_IRQ_PDS             (BL808_IRQ_NUM_BASE + 66)
+#endif
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_memorymap.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_memorymap.h
new file mode 100755
index 0000000000..03585b85bd
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/bl808_memorymap.h
@@ -0,0 +1,161 @@
+#ifndef __BL808_MEMORYMAP_H
+#define __BL808_MEMORYMAP_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+#define BL808_OCRAM_BASE           (0x22020000)
+#define BL808_OCRAM_END            (0x22020000 + 64 * 1024)
+#define BL808_OCRAM_CACHEABLE_BASE (0x62020000)
+#define BL808_OCRAM_CACHEABLE_END  (0x62020000 + 64 * 1024)
+
+#define BL808_WRAM_BASE           (0x22030000)
+#define BL808_WRAM_END            (0x22030000 + 160 * 1024)
+#define BL808_WRAM_CACHEABLE_BASE (0x62030000)
+#define BL808_WRAM_CACHEABLE_END  (0x62030000 + 160 * 1024)
+
+#define BL808_MCU_ALLRAM_BASE           (0x22020000)
+#define BL808_MCU_ALLRAM_END            (0x22020000 + 64 * 1024 + 160 * 1024)
+#define BL808_MCU_ALLRAM_CACHEABLE_BASE (0x62020000)
+#define BL808_MCU_ALLRAM_CACHEABLE_END  (0x62020000 + 64 * 1024 + 160 * 1024)
+
+#define BL808_DRAM_BASE           (0x3EF80000)
+#define BL808_DRAM_END            (0x3EF80000 + 512 * 1024)
+#define BL808_DRAM_CACHEABLE_BASE (0x7EF80000)
+#define BL808_DRAM_CACHEABLE_END  (0x7EF80000 + 512 * 1024)
+
+#define BL808_VRAM_BASE           (0x3F000000)
+#define BL808_VRAM_END            (0x3F000000 + 32 * 1024)
+#define BL808_VRAM_CACHEABLE_BASE (0x7F000000)
+#define BL808_VRAM_CACHEABLE_END  (0x7F000000 + 32 * 1024)
+
+#define BL808_MM_ALLRAM_BASE           (0x3EF80000)
+#define BL808_MM_ALLRAM_END            (0x3EF80000 + 512 * 1024 + 32 * 1024)
+#define BL808_MM_ALLRAM_CACHEABLE_BASE (0x7EF80000)
+#define BL808_MM_ALLRAM_CACHEABLE_END  (0x7EF80000 + 512 * 1024 + 32 * 1024)
+
+#define BL808_FLASH_XIP_BASE         (0x58000000)
+#define BL808_FLASH_XIP_END          (0x58000000 + 64 * 1024 * 1024)
+#define BL808_FLASH2_XIP_BASE        (0x5C000000)
+#define BL808_FLASH2_XIP_END         (0x5C000000 + 64 * 1024 * 1024)
+#define BL808_FLASH_XIP_REMAP0_BASE  (0xD8000000)
+#define BL808_FLASH_XIP_REMAP0_END   (0xD8000000 + 64 * 1024 * 1024)
+#define BL808_FLASH2_XIP_REMAP0_BASE (0xDC000000)
+#define BL808_FLASH2_XIP_REMAP0_END  (0xDC000000 + 64 * 1024 * 1024)
+
+#define BL808_MM_WHOLERAM_BASE           (0x3EF80000)
+#define BL808_MM_WHOLERAM_END            (0x3EF80000 + 512 * 1024 + 96 * 1024)
+#define BL808_MM_WHOLERAM_CACHEABLE_BASE (0x7EF80000)
+#define BL808_MM_WHOLERAM_CACHEABLE_END  (0x7EF80000 + 512 * 1024 + 96 * 1024)
+
+/*@} end of group Memory_Map_Section */
+
+/* BL808 peripherals base address */
+/* WLSYS */
+#define GLB_BASE         ((uint32_t)0x20000000)
+#define MIX_BASE         ((uint32_t)0x20001000)
+#define GPIP_BASE        ((uint32_t)0x20002000)
+#define PHY_BASE         ((uint32_t)0x20002800)
+#define AGC_BASE         ((uint32_t)0x20002c00)
+#define SEC_DBG_BASE     ((uint32_t)0x20003000)
+#define SEC_ENG_BASE     ((uint32_t)0x20004000)
+#define TZ1_BASE         ((uint32_t)0x20005000)
+#define TZC_SEC_BASE     ((uint32_t)0x20005000)
+#define TZ2_BASE         ((uint32_t)0x20006000)
+#define TZC_NSEC_BASE    ((uint32_t)0x20006000)
+#define EFUSE_BASE       ((uint32_t)0x20056000)
+#define EF_DATA_BASE     ((uint32_t)0x20056000)
+#define EF_CTRL_BASE     ((uint32_t)0x20056000)
+#define CCI_BASE         ((uint32_t)0x20008000)
+#define MCU_MISC_BASE    ((uint32_t)0x20009000)
+#define L1C_BASE         ((uint32_t)0x20009000)
+#define UART0_BASE       ((uint32_t)0x2000a000)
+#define UART1_BASE       ((uint32_t)0x2000a100)
+#define SPI0_BASE        ((uint32_t)0x2000a200)
+#define I2C0_BASE        ((uint32_t)0x2000a300)
+#define PWM_BASE         ((uint32_t)0x2000a400)
+#define TIMER0_BASE      ((uint32_t)0x2000a500)
+#define IR_BASE          ((uint32_t)0x2000a600)
+#define CKS_BASE         ((uint32_t)0x2000a700)
+#define IPC0_BASE        ((uint32_t)0x2000a800)
+#define IPC1_BASE        ((uint32_t)0x2000a840)
+#define I2C1_BASE        ((uint32_t)0x2000a900)
+#define UART2_BASE       ((uint32_t)0x2000aa00)
+#define ISO11898_BASE    ((uint32_t)0x2000aa00)
+#define I2S_BASE         ((uint32_t)0x2000ab00)
+#define PDM0_BASE        ((uint32_t)0x2000a000)
+#define LZ4D_BASE        ((uint32_t)0x2000ad00)
+#define QSPI_BASE        ((uint32_t)0x2000b000)
+#define SF_CTRL_BASE     ((uint32_t)0x2000b000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x2000b600)
+#define DMA0_BASE        ((uint32_t)0x2000c000)
+#define PDS_BASE         ((uint32_t)0x2000e000)
+#define HBN_BASE         ((uint32_t)0x2000f000)
+#define AON_BASE         ((uint32_t)0x2000f000)
+#define EMI_MISC_BASE    ((uint32_t)0x20050000)
+#define PSRAM_CTRL_BASE  ((uint32_t)0x20052000)
+#define USB_BASE         ((uint32_t)0x20072000)
+#define AUDIO_BASE       ((uint32_t)0x20055000)
+#define SDH_BASE         ((uint32_t)0x20060000)
+#define EMAC_BASE        ((uint32_t)0x20070000)
+#define DMA1_BASE        ((uint32_t)0x20071000)
+
+/* MMSYS */
+#define MM_MISC_BASE     ((uint32_t)0x30000000)
+#define DMA2_BASE        ((uint32_t)0x30001000)
+#define UART3_BASE       ((uint32_t)0x30002000)
+#define I2C2_BASE        ((uint32_t)0x30003000)
+#define I2C3_BASE        ((uint32_t)0x30004000)
+#define IPC2_BASE        ((uint32_t)0x30005000)
+#define DMA2D_BASE       ((uint32_t)0x30006000)
+#define CLKRST_CTRL_BASE ((uint32_t)0x30007000)
+#define MM_GLB_BASE      ((uint32_t)0x30007000)
+#define SPI1_BASE        ((uint32_t)0x30008000)
+#define TIMER1_BASE      ((uint32_t)0x30009000)
+#define PSRAM_UHS_BASE   ((uint32_t)0x3000f000)
+
+/* MM_SUBSYS */
+#define CAM_FRONT_BASE       ((uint32_t)0x30010000)
+#define MM_SUBSYS_BASE       ((uint32_t)0x30011000)
+#define DVP0_BASE            ((uint32_t)0x30012000)
+#define DVP1_BASE            ((uint32_t)0x30012100)
+#define DVP2_BASE            ((uint32_t)0x30012200)
+#define DVP3_BASE            ((uint32_t)0x30012300)
+#define DVP4_BASE            ((uint32_t)0x30012400)
+#define DVP5_BASE            ((uint32_t)0x30012500)
+#define DVP6_BASE            ((uint32_t)0x30012600)
+#define DVP7_BASE            ((uint32_t)0x30012700)
+#define DVP_TSRC0_BASE       ((uint32_t)0x30012800)
+#define DVP_TSRC1_BASE       ((uint32_t)0x30012900)
+#define AXI_CTRL_NR3D_BASE   ((uint32_t)0x30012a00)
+#define OSD_PROBE_BASE       ((uint32_t)0x30012b00)
+#define OSD_A_BASE           ((uint32_t)0x30013000)
+#define OSD_B_BASE           ((uint32_t)0x30014000)
+#define OSD_DP_BASE          ((uint32_t)0x30015000)
+#define OSD_BLEND0_OFFSET    (0x000)
+#define OSD_BLEND1_OFFSET    (0x100)
+#define OSD_BLEND2_OFFSET    (0x200)
+#define OSD_BLEND3_OFFSET    (0x300)
+#define OSD_DRAW_LOW_OFFSET  (0x400)
+#define OSD_DRAW_HIGH_OFFSET (0x504)
+#define MIPI_BASE            ((uint32_t)0x3001a000)
+#define DBI_BASE             ((uint32_t)0x3001b000)
+#define DSI_BASE             ((uint32_t)0x3001a100)
+#define CSI_BASE             ((uint32_t)0x3001a000)
+
+/* CODEC_SUBSYS */
+#define CODEC_MISC_BASE ((uint32_t)0x30020000)
+#define MJPEG_BASE      ((uint32_t)0x30021000)
+#define VIDEO_BASE      ((uint32_t)0x30022000)
+#define MJPEG_DEC_BASE  ((uint32_t)0x30023000)
+#define BL_CNN_BASE     ((uint32_t)0x30024000)
+
+#define HBN_RAM_BASE ((uint32_t)0x20010000)
+
+#define RF_BASE ((uint32_t)0x20001000)
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/device_table.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/device_table.c
new file mode 100755
index 0000000000..af4e863cbb
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/config/bl808/device_table.c
@@ -0,0 +1,530 @@
+#include "bflb_core.h"
+#include "bl808_memorymap.h"
+#include "bl808_irq.h"
+
+#define DMA_CHANNEL_OFFSET 0x100
+
+#ifndef BFLB_BOOT2
+struct bflb_device_s bl808_device_table[] = {
+    { .name = "adc",
+      .reg_base = AON_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_GPADC_DMA,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ADC,
+      .user_data = NULL },
+    { .name = "dac",
+      .reg_base = GLB_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DAC,
+      .user_data = NULL },
+    { .name = "ef_ctrl",
+      .reg_base = EF_CTRL_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_EF_CTRL,
+      .user_data = NULL },
+    { .name = "gpio",
+      .reg_base = GLB_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_GPIO_INT0,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_GPIO,
+      .user_data = NULL },
+    { .name = "uart0",
+      .reg_base = UART0_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_UART0,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart1",
+      .reg_base = UART1_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_UART1,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart2",
+      .reg_base = UART2_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_UART2,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 2,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart3",
+      .reg_base = UART3_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = 0xff,
+#else
+      .irq_num = BL808_IRQ_UART3,
+#endif
+      .idx = 3,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "spi0",
+      .reg_base = SPI0_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_SPI0,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SPI,
+      .user_data = NULL },
+    { .name = "pwm_v2_0",
+      .reg_base = PWM_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_PWM,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PWM,
+      .user_data = NULL },
+    { .name = "dma0_ch0",
+      .reg_base = DMA0_BASE + 1 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch1",
+      .reg_base = DMA0_BASE + 2 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch2",
+      .reg_base = DMA0_BASE + 3 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 2,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch3",
+      .reg_base = DMA0_BASE + 4 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 3,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch4",
+      .reg_base = DMA0_BASE + 5 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 4,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch5",
+      .reg_base = DMA0_BASE + 6 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 5,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch6",
+      .reg_base = DMA0_BASE + 7 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 6,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "dma0_ch7",
+      .reg_base = DMA0_BASE + 8 * DMA_CHANNEL_OFFSET,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_DMA0_ALL,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 7,
+      .dev_type = BFLB_DEVICE_TYPE_DMA,
+      .user_data = NULL },
+    { .name = "i2c0",
+      .reg_base = I2C0_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_I2C0,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_I2C,
+      .user_data = NULL },
+    { .name = "timer0",
+      .reg_base = TIMER0_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_TIMER0,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "timer1",
+      .reg_base = TIMER1_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_TIMER1,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 1,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "rtc",
+      .reg_base = HBN_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_HBN_OUT0,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_RTC,
+      .user_data = NULL },
+    { .name = "aes",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_AES,
+      .user_data = NULL },
+    { .name = "sha",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SHA,
+      .user_data = NULL },
+    { .name = "trng",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TRNG,
+      .user_data = NULL },
+    { .name = "pka",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PKA,
+      .user_data = NULL },
+    { .name = "emac0",
+      .reg_base = EMAC_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_EMAC,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_ETH,
+      .user_data = NULL },
+    { .name = "irtx",
+      .reg_base = IR_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_IRTX,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_IR,
+      .user_data = NULL },
+    { .name = "irrx",
+      .reg_base = IR_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_IRRX,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_IR,
+      .user_data = NULL },
+    { .name = "cks",
+      .reg_base = CKS_BASE,
+      .irq_num = 0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CKS,
+      .user_data = NULL },
+    { .name = "mjpeg",
+      .reg_base = MJPEG_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = 0xff,
+#else
+      .irq_num = BL808_IRQ_MJPEG,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_MJPEG,
+      .user_data = NULL },
+    { .name = "watchdog",
+      .reg_base = TIMER0_BASE,
+#if defined(CPU_M0) || defined(CPU_LP)
+      .irq_num = BL808_IRQ_WDT,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "cam0",
+      .reg_base = DVP0_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT0,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam1",
+      .reg_base = DVP1_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT1,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 1,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam2",
+      .reg_base = DVP2_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT2,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 2,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam3",
+      .reg_base = DVP3_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT3,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 3,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam4",
+      .reg_base = DVP4_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT4,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 4,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam5",
+      .reg_base = DVP5_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT5,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 5,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam6",
+      .reg_base = DVP6_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT6,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 6,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "cam7",
+      .reg_base = DVP7_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_DVP2BUS_INT7,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 7,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CAMERA,
+      .user_data = NULL },
+    { .name = "csi",
+      .reg_base = CSI_BASE,
+#if defined(CPU_D0)
+      .irq_num = BL808_IRQ_MIPI_CSI,
+#else
+      .irq_num = 0xff,
+#endif
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_CSI,
+      .user_data = NULL },
+};
+#else
+struct bflb_device_s bl808_device_table[] = {
+    { .name = "ef_ctrl",
+      .reg_base = EF_CTRL_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_EF_CTRL,
+      .user_data = NULL },
+    { .name = "gpio",
+      .reg_base = GLB_BASE,
+      .irq_num = BL808_IRQ_GPIO_INT0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_GPIO,
+      .user_data = NULL },
+    { .name = "uart0",
+      .reg_base = UART0_BASE,
+      .irq_num = BL808_IRQ_UART0,
+      .idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart1",
+      .reg_base = UART1_BASE,
+      .irq_num = BL808_IRQ_UART1,
+      .idx = 1,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+    { .name = "uart2",
+      .reg_base = UART2_BASE,
+      .irq_num = BL808_IRQ_UART2,
+      .idx = 2,
+      .dev_type = BFLB_DEVICE_TYPE_UART,
+      .user_data = NULL },
+      { .name = "timer0",
+      .reg_base = TIMER0_BASE,
+      .irq_num = BL808_IRQ_TIMER0,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "timer1",
+      .reg_base = TIMER1_BASE,
+      .irq_num = BL808_IRQ_TIMER1,
+      .idx = 1,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TIMER,
+      .user_data = NULL },
+    { .name = "aes",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_AES,
+      .user_data = NULL },
+    { .name = "sha",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_SHA,
+      .user_data = NULL },
+    { .name = "trng",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_TRNG,
+      .user_data = NULL },
+    { .name = "pka",
+      .reg_base = SEC_ENG_BASE,
+      .irq_num = 0xff,
+      .idx = 0,
+      .sub_idx = 0,
+      .dev_type = BFLB_DEVICE_TYPE_PKA,
+      .user_data = NULL },
+};
+#endif
+
+struct bflb_device_s *bflb_device_get_by_name(const char *name)
+{
+    for (uint8_t i = 0; i < sizeof(bl808_device_table) / sizeof(bl808_device_table[0]); i++) {
+        if (strcmp(bl808_device_table[i].name, name) == 0) {
+            return &bl808_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx)
+{
+    for (uint8_t i = 0; i < sizeof(bl808_device_table) / sizeof(bl808_device_table[0]); i++) {
+        if ((bl808_device_table[i].dev_type == type) && (bl808_device_table[i].idx = idx)) {
+            return &bl808_device_table[i];
+        }
+    }
+    return NULL;
+}
+
+void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data)
+{
+    device->user_data = user_data;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/csr.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/csr.h
new file mode 100755
index 0000000000..3b2b462777
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/csr.h
@@ -0,0 +1,364 @@
+/****************************************************************************
+ * arch/risc-v/include/csr.h
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directly but, rather, only indirectly
+ * through nuttx/irq.h
+ */
+
+#ifndef __ARCH_RISCV_INCLUDE_CSR_H
+#define __ARCH_RISCV_INCLUDE_CSR_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* User Trap Registers */
+
+#define CSR_USTATUS         0x000
+#define CSR_UIE             0x004
+#define CSR_UTVEC           0x005
+
+/* User Trap Handling Registers */
+
+#define CSR_USCRATCH        0x040
+#define CSR_UEPC            0x041
+#define CSR_UCAUSE          0x042
+#define CSR_UTVAL           0x043
+#define CSR_UIP             0x044
+
+/* User Floating-Point Registers */
+
+#define CSR_FFLAGS          0x001
+#define CSR_FRM             0x002
+#define CSR_FCSR            0x003
+
+/* User Counter/Times Registers */
+
+#define CSR_CYCLE           0xC00
+#define CSR_TIME            0xC01
+#define CSR_INSTRET         0xC02
+#define CSR_HPCOUNTER3      0xC03
+#define CSR_HPCOUNTER4      0xC04
+#define CSR_HPCOUNTER5      0xC05
+#define CSR_HPCOUNTER6      0xC06
+#define CSR_HPCOUNTER7      0xC07
+#define CSR_HPCOUNTER8      0xC08
+#define CSR_HPCOUNTER9      0xC09
+#define CSR_HPCOUNTER10     0xC0A
+#define CSR_HPCOUNTER11     0xC0B
+#define CSR_HPCOUNTER12     0xC0C
+#define CSR_HPCOUNTER13     0xC0D
+#define CSR_HPCOUNTER14     0xC0E
+#define CSR_HPCOUNTER15     0xC0F
+#define CSR_HPCOUNTER16     0xC10
+#define CSR_HPCOUNTER17     0xC11
+#define CSR_HPCOUNTER18     0xC12
+#define CSR_HPCOUNTER19     0xC13
+#define CSR_HPCOUNTER20     0xC14
+#define CSR_HPCOUNTER21     0xC15
+#define CSR_HPCOUNTER22     0xC16
+#define CSR_HPCOUNTER24     0xC17
+#define CSR_HPCOUNTER25     0xC18
+#define CSR_HPCOUNTER26     0xC19
+#define CSR_HPCOUNTER27     0xC1A
+#define CSR_HPCOUNTER28     0xC1B
+#define CSR_HPCOUNTER29     0xC1C
+#define CSR_HPCOUNTER30     0xC1D
+#define CSR_HPCOUNTER31     0xC1F
+#define CSR_CYCLEH          0xC80
+#define CSR_TIMEH           0xC81
+#define CSR_INSTRETH        0xC82
+#define CSR_HPCOUNTER3H     0xC83
+#define CSR_HPCOUNTER4H     0xC84
+#define CSR_HPCOUNTER5H     0xC85
+#define CSR_HPCOUNTER6H     0xC86
+#define CSR_HPCOUNTER7H     0xC87
+#define CSR_HPCOUNTER8H     0xC88
+#define CSR_HPCOUNTER9H     0xC89
+#define CSR_HPCOUNTER10H    0xC8A
+#define CSR_HPCOUNTER11H    0xC8B
+#define CSR_HPCOUNTER12H    0xC8C
+#define CSR_HPCOUNTER13H    0xC8D
+#define CSR_HPCOUNTER14H    0xC8E
+#define CSR_HPCOUNTER15H    0xC8F
+#define CSR_HPCOUNTER16H    0xC90
+#define CSR_HPCOUNTER17H    0xC91
+#define CSR_HPCOUNTER18H    0xC92
+#define CSR_HPCOUNTER19H    0xC93
+#define CSR_HPCOUNTER20H    0xC94
+#define CSR_HPCOUNTER21H    0xC95
+#define CSR_HPCOUNTER22H    0xC96
+#define CSR_HPCOUNTER24H    0xC97
+#define CSR_HPCOUNTER25H    0xC98
+#define CSR_HPCOUNTER26H    0xC99
+#define CSR_HPCOUNTER27H    0xC9A
+#define CSR_HPCOUNTER28H    0xC9B
+#define CSR_HPCOUNTER29H    0xC9C
+#define CSR_HPCOUNTER30H    0xC9D
+#define CSR_HPCOUNTER31H    0xC9F
+
+/* Supervisor Trap Setup Registers */
+
+#define CSR_SSTATUS         0x100
+#define CSR_SEDELEG         0x102
+#define CSR_SIDELEG         0x103
+#define CSR_SIE             0x104
+#define CSR_STVEC           0x105
+#define CSR_SCOUNTEREN      0x106
+
+/* Supervisor Trap Handling Registers */
+
+#define CSR_SSCRATCH        0x140
+#define CSR_SEPC            0x141
+#define CSR_SCAUSE          0x142
+#define CSR_STVAL           0x143
+#define CSR_SIP             0x144
+
+/* Supervisor Protection and Translation Registers */
+
+#define CSR_SATP            0x180
+
+/* Machine Information Registers */
+
+#define CSR_MVENDORID       0xF11
+#define CSR_MARCHID         0xF12
+#define CSR_MIMPID          0xF13
+#define CSR_MHARTID         0xF14
+
+/* Machine Trap Registers */
+
+#define CSR_MSTATUS         0x300
+#define CSR_MISA            0x301
+#define CSR_MEDELEG         0x302
+#define CSR_MIDELEG         0x303
+#define CSR_MIE             0x304
+#define CSR_MTVEC           0x305
+#define CSR_MCOUNTEREN      0x306
+
+/* Machine Trap Handling */
+
+#define CSR_MSCRATCH        0x340
+#define CSR_MEPC            0x341
+#define CSR_MCAUSE          0x342
+#define CSR_MTVAL           0x343
+#define CSR_MIP             0x344
+
+/* Machine Protection and Translation */
+
+#define CSR_PMPCFG0         0x3A0
+#define CSR_PMPCFG1         0x3A1
+#define CSR_PMPCFG2         0x3A2
+#define CSR_PMPCFG3         0x3A3
+#define CSR_PMPADDR0        0x3B0
+#define CSR_PMPADDR1        0x3B1
+#define CSR_PMPADDR2        0x3B2
+#define CSR_PMPADDR3        0x3B3
+#define CSR_PMPADDR4        0x3B4
+#define CSR_PMPADDR5        0x3B5
+#define CSR_PMPADDR6        0x3B6
+#define CSR_PMPADDR7        0x3B7
+#define CSR_PMPADDR8        0x3B8
+#define CSR_PMPADDR9        0x3B9
+#define CSR_PMPADDR10       0x3BA
+#define CSR_PMPADDR11       0x3BB
+#define CSR_PMPADDR12       0x3BC
+#define CSR_PMPADDR13       0x3BD
+#define CSR_PMPADDR14       0x3BE
+#define CSR_PMPADDR15       0x3BF
+
+/* Machine Timers and Counters */
+
+#define CSR_MCYCLE          0xB00
+#define CSR_MINSTRET        0xB02
+#define CSR_MHPMCOUNTER3    0xB03
+#define CSR_MHPMCOUNTER4    0xB04
+#define CSR_MHPMCOUNTER5    0xB05
+#define CSR_MHPMCOUNTER6    0xB06
+#define CSR_MHPMCOUNTER7    0xB07
+#define CSR_MHPMCOUNTER8    0xB08
+#define CSR_MHPMCOUNTER9    0xB09
+#define CSR_MHPMCOUNTER10   0xB0A
+#define CSR_MHPMCOUNTER11   0xB0B
+#define CSR_MHPMCOUNTER12   0xB0C
+#define CSR_MHPMCOUNTER13   0xB0D
+#define CSR_MHPMCOUNTER14   0xB0E
+#define CSR_MHPMCOUNTER15   0xB0F
+#define CSR_MHPMCOUNTER16   0xB10
+#define CSR_MHPMCOUNTER17   0xB11
+#define CSR_MHPMCOUNTER18   0xB12
+#define CSR_MHPMCOUNTER19   0xB13
+#define CSR_MHPMCOUNTER20   0xB14
+#define CSR_MHPMCOUNTER21   0xB15
+#define CSR_MHPMCOUNTER22   0xB16
+#define CSR_MHPMCOUNTER23   0xB17
+#define CSR_MHPMCOUNTER24   0xB18
+#define CSR_MHPMCOUNTER25   0xB19
+#define CSR_MHPMCOUNTER26   0xB1A
+#define CSR_MHPMCOUNTER27   0xB1B
+#define CSR_MHPMCOUNTER28   0xB1C
+#define CSR_MHPMCOUNTER29   0xB1D
+#define CSR_MHPMCOUNTER30   0xB1E
+#define CSR_MHPMCOUNTER31   0xB1F
+#define CSR_MCYCLEH         0xB80
+#define CSR_MINSTRETH       0xB82
+#define CSR_MHPMCOUNTER3H   0xB83
+#define CSR_MHPMCOUNTER4H   0xB84
+#define CSR_MHPMCOUNTER5H   0xB85
+#define CSR_MHPMCOUNTER6H   0xB86
+#define CSR_MHPMCOUNTER7H   0xB87
+#define CSR_MHPMCOUNTER8H   0xB88
+#define CSR_MHPMCOUNTER9H   0xB89
+#define CSR_MHPMCOUNTER10H  0xB8A
+#define CSR_MHPMCOUNTER11H  0xB8B
+#define CSR_MHPMCOUNTER12H  0xB8C
+#define CSR_MHPMCOUNTER13H  0xB8D
+#define CSR_MHPMCOUNTER14H  0xB8E
+#define CSR_MHPMCOUNTER15H  0xB8F
+#define CSR_MHPMCOUNTER16H  0xB90
+#define CSR_MHPMCOUNTER17H  0xB91
+#define CSR_MHPMCOUNTER18H  0xB92
+#define CSR_MHPMCOUNTER19H  0xB93
+#define CSR_MHPMCOUNTER20H  0xB94
+#define CSR_MHPMCOUNTER21H  0xB95
+#define CSR_MHPMCOUNTER22H  0xB96
+#define CSR_MHPMCOUNTER23H  0xB97
+#define CSR_MHPMCOUNTER24H  0xB98
+#define CSR_MHPMCOUNTER25H  0xB99
+#define CSR_MHPMCOUNTER26H  0xB9A
+#define CSR_MHPMCOUNTER27H  0xB9B
+#define CSR_MHPMCOUNTER28H  0xB9C
+#define CSR_MHPMCOUNTER29H  0xB9D
+#define CSR_MHPMCOUNTER30H  0xB9E
+#define CSR_MHPMCOUNTER31H  0xB9F
+
+/* Machine Counter Setup */
+
+#define CSR_MPHEVENT3       0x323
+#define CSR_MPHEVENT4       0x324
+#define CSR_MPHEVENT5       0x325
+#define CSR_MPHEVENT6       0x326
+#define CSR_MPHEVENT7       0x327
+#define CSR_MPHEVENT8       0x328
+#define CSR_MPHEVENT9       0x329
+#define CSR_MPHEVENT10      0x32A
+#define CSR_MPHEVENT11      0x32B
+#define CSR_MPHEVENT12      0x32C
+#define CSR_MPHEVENT13      0x32D
+#define CSR_MPHEVENT14      0x32E
+#define CSR_MPHEVENT15      0x32F
+#define CSR_MPHEVENT16      0x330
+#define CSR_MPHEVENT17      0x331
+#define CSR_MPHEVENT18      0x332
+#define CSR_MPHEVENT19      0x333
+#define CSR_MPHEVENT20      0x334
+#define CSR_MPHEVENT21      0x335
+#define CSR_MPHEVENT22      0x336
+#define CSR_MPHEVENT23      0x337
+#define CSR_MPHEVENT24      0x338
+#define CSR_MPHEVENT25      0x339
+#define CSR_MPHEVENT26      0x33A
+#define CSR_MPHEVENT27      0x33B
+#define CSR_MPHEVENT28      0x33C
+#define CSR_MPHEVENT29      0x33D
+#define CSR_MPHEVENT30      0x33E
+#define CSR_MPHEVENT31      0x33F
+
+/* Debug/Trace Registers */
+
+#define CSR_TSELECT         0x7A0
+#define CSR_TDATA1          0x7A1
+#define CSR_TDATA2          0x7A2
+#define CSR_TDATA3          0x7A3
+
+/* Debug interface CSRs */
+
+#define CSR_DCSR            0x7B0
+#define CSR_DPC             0x7B1
+#define CSR_DSCRATCH        0x7B2
+
+/* In mstatus register */
+#define MSTATUS_SIE       (0x1 << 1)  /* Superior Interrupt Enable */
+#define MSTATUS_MIE       (0x1 << 3)  /* Machine Interrupt Enable */
+#define MSTATUS_MPIE      (0x1 << 7)  /* Machine Previous Interrupt Enable */
+#define MSTATUS_MPPM      (0x3 << 11) /* Machine Previous Privilege (m-mode) */
+#define MSTATUS_FS        (0x3 << 13) /* Machine Floating-point Status */
+#define MSTATUS_FS_INIT   (0x1 << 13)
+#define MSTATUS_FS_CLEAN  (0x2 << 13)
+#define MSTATUS_FS_DIRTY  (0x3 << 13)
+
+/* In mie (machine interrupt enable) register */
+
+#define MIE_MSIE      (0x1 << 3)  /* Machine Software Interrupt Enable */
+#define MIE_MTIE      (0x1 << 7)  /* Machine Timer Interrupt Enable */
+#define MIE_MEIE      (0x1 << 11) /* Machine External Interrupt Enable */
+
+/* In mip (machine interrupt pending) register */
+
+#define MIP_MTIP      (0x1 << 7)
+
+#define CSR_STR(csr) #csr
+
+#define READ_CSR(reg) \
+  ({ \
+     unsigned long tmp; \
+     asm volatile("csrr %0, " CSR_STR(reg) : "=r"(tmp)); \
+     tmp; \
+  })
+
+#define WRITE_CSR(reg, val) \
+  ({ \
+     asm volatile("csrw " CSR_STR(reg) ", %0" :: "rK"(val)); \
+  })
+
+#define SET_CSR(reg, bits) \
+  ({ \
+     asm volatile("csrs " CSR_STR(reg) ", %0" :: "rK"(bits)); \
+  })
+
+#define CLEAR_CSR(reg, bits) \
+  ({ \
+     asm volatile("csrc " CSR_STR(reg) ", %0" :: "rK"(bits)); \
+  })
+
+/* In pmpcfg (PMP configuration) register */
+
+#define PMPCFG_R        (1 << 0)  /* readable ? */
+#define PMPCFG_W        (1 << 1)  /* writeable ? */
+#define PMPCFG_X        (1 << 2)  /* excutable ? */
+#define PMPCFG_A_OFF    (0 << 3)  /* null region (disabled) */
+#define PMPCFG_A_TOR    (1 << 3)  /* top of range */
+#define PMPCFG_A_NA4    (2 << 3)  /* naturally aligned four-byte region */
+#define PMPCFG_A_NAPOT  (3 << 3)  /* naturally aligned power-of-two region */
+#define PMPCFG_A_MASK   (3 << 3)  /* address-matching mode mask */
+#define PMPCFG_L        (1 << 7)  /* locked ? */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#endif /* __ARCH_RISCV_INCLUDE_CSR_H */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/e24/clic.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/e24/clic.h
new file mode 100755
index 0000000000..403d31a422
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/e24/clic.h
@@ -0,0 +1,17 @@
+// See LICENSE for license details.
+
+#ifndef _SIFIVE_CLIC_H
+#define _SIFIVE_CLIC_H
+
+#define CLIC_CTRL_BASE  0x02000000UL
+#define CLIC_HART0_BASE 0x02800000UL
+
+#define CLIC_MSIP_OFFSET     0x0000
+#define CLIC_MTIMECMP_OFFSET 0x4000
+#define CLIC_MTIME_OFFSET    0xBFF8
+#define CLIC_INTIP_OFFSET    0x000
+#define CLIC_INTIE_OFFSET    0x400
+#define CLIC_INTCFG_OFFSET   0x800
+#define CLIC_CFG_OFFSET      0xc00
+
+#endif /* _SIFIVE_CLIC_H */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/riscv_arch.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/riscv_arch.h
new file mode 100755
index 0000000000..35a901b2f8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/riscv_arch.h
@@ -0,0 +1,14 @@
+#ifndef _RISCV_ARCH_H
+#define _RISCV_ARCH_H
+
+#define getreg8(a)                         (*(volatile uint8_t *)(uintptr_t)(a))
+#define putreg8(v, a)                      (*(volatile uint8_t *)(uintptr_t)(a) = (v))
+#define getreg16(a)                        (*(volatile uint16_t *)(uintptr_t)(a))
+#define putreg16(v, a)                     (*(volatile uint16_t *)(uintptr_t)(a) = (v))
+#define getreg32(a)                        (*(volatile uint32_t *)(uintptr_t)(a))
+#define putreg32(v, a)                     (*(volatile uint32_t *)(uintptr_t)(a) = (v))
+// #define getreg64(a)                        (*(volatile uint64_t *)(a))
+// #define putreg64(v, a)                     (*(volatile uint64_t *)(a) = (v))
+// #define modifyreg32(a, clearbits, setbits) putreg32((getreg32(a) & (~clearbits)) | setbits, a)
+
+#endif
\ No newline at end of file
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/core_rv32.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/core_rv32.h
old mode 100644
new mode 100755
similarity index 90%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/core_rv32.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/core_rv32.h
index e4b3d57251..bb577e72bb
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/core_rv32.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/core_rv32.h
@@ -101,8 +101,8 @@ extern "C" {
 
 /* following defines should be used for structure members */
 #define __IM  volatile const /*! Defines 'read only' structure member permissions */
-#define __OM  volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+#define __OM  volatile       /*! Defines 'write only' structure member permissions */
+#define __IOM volatile       /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group RV32 */
 
@@ -154,34 +154,34 @@ typedef struct
 #define CLIC_INFO_CLICINTCTLBITS_Pos 21U
 #define CLIC_INFO_CLICINTCTLBITS_Msk (0xFUL << CLIC_INFO_CLICINTCTLBITS_Pos)
 
-#define CLIC_INTIP_IP_Pos 0U /*!< CLIC INTIP: IP Position */
+#define CLIC_INTIP_IP_Pos 0U                           /*!< CLIC INTIP: IP Position */
 #define CLIC_INTIP_IP_Msk (0x1UL << CLIC_INTIP_IP_Pos) /*!< CLIC INTIP: IP Mask */
 
-#define CLIC_INTIE_IE_Pos 0U /*!< CLIC INTIE: IE Position */
+#define CLIC_INTIE_IE_Pos 0U                           /*!< CLIC INTIE: IE Position */
 #define CLIC_INTIE_IE_Msk (0x1UL << CLIC_INTIE_IE_Pos) /*!< CLIC INTIE: IE Mask */
 
-#define CLIC_INTIE_T_Pos 7U /*!< CLIC INTIE: T Position */
+#define CLIC_INTIE_T_Pos 7U                          /*!< CLIC INTIE: T Position */
 #define CLIC_INTIE_T_Msk (0x1UL << CLIC_INTIE_T_Pos) /*!< CLIC INTIE: T Mask */
 
-#define CLIC_INTATTR_TRIG_Pos 1U /*!< CLIC INTATTR: TRIG Position */
+#define CLIC_INTATTR_TRIG_Pos 1U                               /*!< CLIC INTATTR: TRIG Position */
 #define CLIC_INTATTR_TRIG_Msk (0x3UL << CLIC_INTATTR_TRIG_Pos) /*!< CLIC INTATTR: TRIG Mask */
 
-#define CLIC_INTATTR_SHV_Pos 0U /*!< CLIC INTATTR: SHV Position */
+#define CLIC_INTATTR_SHV_Pos 0U                              /*!< CLIC INTATTR: SHV Position */
 #define CLIC_INTATTR_SHV_Msk (0x1UL << CLIC_INTATTR_SHV_Pos) /*!< CLIC INTATTR: SHV Mask */
 
-#define CLIC_INTCFG_NVBIT_Pos 5U /*!< CLIC INTCFG: NVBIT Position */
+#define CLIC_INTCFG_NVBIT_Pos 5U                               /*!< CLIC INTCFG: NVBIT Position */
 #define CLIC_INTCFG_NVBIT_Msk (0x1UL << CLIC_INTCFG_NVBIT_Pos) /*!< CLIC INTCFG: NVBIT Mask */
 
-#define CLIC_INTCFG_PRIO_Pos 4U /*!< CLIC INTCFG: INTCFG Position */
+#define CLIC_INTCFG_PRIO_Pos 4U                              /*!< CLIC INTCFG: INTCFG Position */
 #define CLIC_INTCFG_PRIO_Msk (0xFUL << CLIC_INTCFG_PRIO_Pos) /*!< CLIC INTCFG: INTCFG Mask */
 
-#define CLIC_CLICCFG_NVBIT_Pos 0U /*!< CLIC CLICCFG: NVBIT Position */
+#define CLIC_CLICCFG_NVBIT_Pos 0U                                /*!< CLIC CLICCFG: NVBIT Position */
 #define CLIC_CLICCFG_NVBIT_Msk (0x1UL << CLIC_CLICCFG_NVBIT_Pos) /*!< CLIC CLICCFG: NVBIT Mask */
 
-#define CLIC_CLICCFG_NLBIT_Pos 1U /*!< CLIC CLICCFG: NLBIT Position */
+#define CLIC_CLICCFG_NLBIT_Pos 1U                                /*!< CLIC CLICCFG: NLBIT Position */
 #define CLIC_CLICCFG_NLBIT_Msk (0xFUL << CLIC_CLICCFG_NLBIT_Pos) /*!< CLIC CLICCFG: NLBIT Mask */
 
-#define CLIC_CLICCFG_NMBIT_Pos 5U /*!< CLIC CLICCFG: NMBIT Position */
+#define CLIC_CLICCFG_NMBIT_Pos 5U                                /*!< CLIC CLICCFG: NMBIT Position */
 #define CLIC_CLICCFG_NMBIT_Msk (0x3UL << CLIC_CLICCFG_NMBIT_Pos) /*!< CLIC CLICCFG: NMBIT Mask */
 
 /*@} end of group CSI_CLIC */
@@ -193,19 +193,19 @@ typedef struct
   @{
  */
 
-#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */
+#define PMP_PMPCFG_R_Pos 0U                          /*!< PMP PMPCFG: R Position */
 #define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */
 
-#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */
+#define PMP_PMPCFG_W_Pos 1U                          /*!< PMP PMPCFG: W Position */
 #define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */
 
-#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */
+#define PMP_PMPCFG_X_Pos 2U                          /*!< PMP PMPCFG: X Position */
 #define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */
 
-#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */
+#define PMP_PMPCFG_A_Pos 3U                          /*!< PMP PMPCFG: A Position */
 #define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */
 
-#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */
+#define PMP_PMPCFG_L_Pos 7U                          /*!< PMP PMPCFG: L Position */
 #define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */
 
 typedef enum {
@@ -262,25 +262,25 @@ typedef struct
 /*@} end of group CSI_PMP */
 
 /* CACHE Register Definitions */
-#define CACHE_MHCR_L0BTB_Pos 12U /*!< CACHE MHCR: L0BTB Position */
+#define CACHE_MHCR_L0BTB_Pos 12U                             /*!< CACHE MHCR: L0BTB Position */
 #define CACHE_MHCR_L0BTB_Msk (0x1UL << CACHE_MHCR_L0BTB_Pos) /*!< CACHE MHCR: WA Mask */
 
-#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */
+#define CACHE_MHCR_BPE_Pos 5U                            /*!< CACHE MHCR: BPE Position */
 #define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */
 
-#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */
+#define CACHE_MHCR_RS_Pos 4U                           /*!< CACHE MHCR: RS Position */
 #define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */
 
-#define CACHE_MHCR_WA_Pos 3U /*!< CACHE MHCR: WA Position */
+#define CACHE_MHCR_WA_Pos 3U                           /*!< CACHE MHCR: WA Position */
 #define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */
 
-#define CACHE_MHCR_WB_Pos 2U /*!< CACHE MHCR: WB Position */
+#define CACHE_MHCR_WB_Pos 2U                           /*!< CACHE MHCR: WB Position */
 #define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */
 
-#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */
+#define CACHE_MHCR_DE_Pos 1U                           /*!< CACHE MHCR: DE Position */
 #define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */
 
-#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */
+#define CACHE_MHCR_IE_Pos 0U                           /*!< CACHE MHCR: IE Position */
 #define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */
 
 #define CACHE_INV_ADDR_Pos 5U
@@ -295,13 +295,13 @@ typedef struct
   @{
  */
 
-#define SYSMAP_SYSMAPCFG_B_Pos 0U /*!< SYSMAP SYSMAPCFG: B Position */
+#define SYSMAP_SYSMAPCFG_B_Pos 0U                                /*!< SYSMAP SYSMAPCFG: B Position */
 #define SYSMAP_SYSMAPCFG_B_Msk (0x1UL << SYSMAP_SYSMAPCFG_B_Pos) /*!< SYSMAP SYSMAPCFG: B Mask */
 
-#define SYSMAP_SYSMAPCFG_C_Pos 1U /*!< SYSMAP SYSMAPCFG: C Position */
+#define SYSMAP_SYSMAPCFG_C_Pos 1U                                /*!< SYSMAP SYSMAPCFG: C Position */
 #define SYSMAP_SYSMAPCFG_C_Msk (0x1UL << SYSMAP_SYSMAPCFG_C_Pos) /*!< SYSMAP SYSMAPCFG: C Mask */
 
-#define SYSMAP_SYSMAPCFG_SO_Pos 2U /*!< SYSMAP SYSMAPCFG: SO Position */
+#define SYSMAP_SYSMAPCFG_SO_Pos 2U                                 /*!< SYSMAP SYSMAPCFG: SO Position */
 #define SYSMAP_SYSMAPCFG_SO_Msk (0x1UL << SYSMAP_SYSMAPCFG_SO_Pos) /*!< SYSMAP SYSMAPCFG: SO Mask */
 
 /**
@@ -374,16 +374,16 @@ typedef struct
 
 } DCC_Type;
 
-#define DCC_HCR_JW_Pos 18U /*!< DCC HCR: jw_int_en Position */
+#define DCC_HCR_JW_Pos 18U                     /*!< DCC HCR: jw_int_en Position */
 #define DCC_HCR_JW_Msk (1UL << DCC_HCR_JW_Pos) /*!< DCC HCR: jw_int_en Mask */
 
-#define DCC_HCR_JR_Pos 19U /*!< DCC HCR: jr_int_en Position */
+#define DCC_HCR_JR_Pos 19U                     /*!< DCC HCR: jr_int_en Position */
 #define DCC_HCR_JR_Msk (1UL << DCC_HCR_JR_Pos) /*!< DCC HCR: jr_int_en Mask */
 
-#define DCC_EHSR_JW_Pos 1U /*!< DCC EHSR: jw_vld Position */
+#define DCC_EHSR_JW_Pos 1U                       /*!< DCC EHSR: jw_vld Position */
 #define DCC_EHSR_JW_Msk (1UL << DCC_EHSR_JW_Pos) /*!< DCC EHSR: jw_vld Mask */
 
-#define DCC_EHSR_JR_Pos 2U /*!< DCC EHSR: jr_vld Position */
+#define DCC_EHSR_JR_Pos 2U                       /*!< DCC EHSR: jr_vld Position */
 #define DCC_EHSR_JR_Msk (1UL << DCC_EHSR_JR_Pos) /*!< DCC EHSR: jr_vld Mask */
 
 /*@} end of group CSI_DCC */
@@ -421,18 +421,18 @@ typedef struct
  */
 
 /* Memory mapping of THEAD CPU */
-#define TCIP_BASE   (0xE000E000UL) /*!< Titly Coupled IP Base Address */
-#define CORET_BASE  (0xE0004000UL) /*!< CORET Base Address */
-#define CLIC_BASE   (0xE0800000UL) /*!< CLIC Base Address */
-#define SYSMAP_BASE (0xEFFFF000UL) /*!< SYSMAP Base Address */
-#define DCC_BASE    (0xE4010000UL) /*!< DCC Base Address */
+#define TCIP_BASE   (0xE000E000UL)         /*!< Titly Coupled IP Base Address */
+#define CORET_BASE  (0xE0004000UL)         /*!< CORET Base Address */
+#define CLIC_BASE   (0xE0800000UL)         /*!< CLIC Base Address */
+#define SYSMAP_BASE (0xEFFFF000UL)         /*!< SYSMAP Base Address */
+#define DCC_BASE    (0xE4010000UL)         /*!< DCC Base Address */
 #define CACHE_BASE  (TCIP_BASE + 0x1000UL) /*!< CACHE Base Address */
 
-#define CORET  ((CORET_Type *)CORET_BASE) /*!< SysTick configuration struct */
-#define CLIC   ((CLIC_Type *)CLIC_BASE) /*!< CLIC configuration struct */
-#define DCC    ((DCC_Type *)DCC_BASE) /*!< DCC configuration struct */
+#define CORET  ((CORET_Type *)CORET_BASE)   /*!< SysTick configuration struct */
+#define CLIC   ((CLIC_Type *)CLIC_BASE)     /*!< CLIC configuration struct */
+#define DCC    ((DCC_Type *)DCC_BASE)       /*!< DCC configuration struct */
 #define SYSMAP ((SYSMAP_Type *)SYSMAP_BASE) /*!< SYSMAP configuration struct */
-#define CACHE  ((CACHE_Type *)CACHE_BASE) /*!< cache configuration struct */
+#define CACHE  ((CACHE_Type *)CACHE_BASE)   /*!< cache configuration struct */
 
 /*@} */
 
@@ -1198,7 +1198,7 @@ __STATIC_INLINE void csi_dcache_clean_invalid(void)
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
-__STATIC_INLINE void csi_dcache_invalid_range(uint32_t *addr, int32_t dsize)
+__STATIC_INLINE void csi_dcache_invalid_range(void *addr, int32_t dsize)
 {
 #if (__DCACHE_PRESENT == 1U)
     int32_t op_size = dsize + (uint32_t)addr % 32;
@@ -1223,7 +1223,7 @@ __STATIC_INLINE void csi_dcache_invalid_range(uint32_t *addr, int32_t dsize)
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
-__STATIC_INLINE void csi_dcache_clean_range(uint32_t *addr, int32_t dsize)
+__STATIC_INLINE void csi_dcache_clean_range(void *addr, int32_t dsize)
 {
 #if (__DCACHE_PRESENT == 1U)
     int32_t op_size = dsize + (uint32_t)addr % 32;
@@ -1248,7 +1248,7 @@ __STATIC_INLINE void csi_dcache_clean_range(uint32_t *addr, int32_t dsize)
   \param[in]   addr    address (aligned to 16-byte boundary)
   \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
 */
-__STATIC_INLINE void csi_dcache_clean_invalid_range(uint32_t *addr, int32_t dsize)
+__STATIC_INLINE void csi_dcache_clean_invalid_range(void *addr, int32_t dsize)
 {
 #if (__DCACHE_PRESENT == 1U)
     int32_t op_size = dsize + (uint32_t)addr % 32;
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/core_rv64.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/core_rv64.h
old mode 100644
new mode 100755
similarity index 93%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/core_rv64.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/core_rv64.h
index f9036fab13..07257e8996
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/core_rv64.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/core_rv64.h
@@ -9,8 +9,8 @@
  * @date     01. Sep 2018
  ******************************************************************************/
 
-#ifndef __CORE_RV32_H_GENERIC
-#define __CORE_RV32_H_GENERIC
+#ifndef __CORE_RV64_H_GENERIC
+#define __CORE_RV64_H_GENERIC
 
 #include 
 
@@ -105,8 +105,8 @@ extern "C" {
 
 /* following defines should be used for structure members */
 #define __IM  volatile const /*! Defines 'read only' structure member permissions */
-#define __OM  volatile /*! Defines 'write only' structure member permissions */
-#define __IOM volatile /*! Defines 'read / write' structure member permissions */
+#define __OM  volatile       /*! Defines 'write only' structure member permissions */
+#define __IOM volatile       /*! Defines 'read / write' structure member permissions */
 
 /*@} end of group C910 */
 
@@ -191,19 +191,19 @@ typedef struct
   @{
  */
 
-#define PMP_PMPCFG_R_Pos 0U /*!< PMP PMPCFG: R Position */
+#define PMP_PMPCFG_R_Pos 0U                          /*!< PMP PMPCFG: R Position */
 #define PMP_PMPCFG_R_Msk (0x1UL << PMP_PMPCFG_R_Pos) /*!< PMP PMPCFG: R Mask */
 
-#define PMP_PMPCFG_W_Pos 1U /*!< PMP PMPCFG: W Position */
+#define PMP_PMPCFG_W_Pos 1U                          /*!< PMP PMPCFG: W Position */
 #define PMP_PMPCFG_W_Msk (0x1UL << PMP_PMPCFG_W_Pos) /*!< PMP PMPCFG: W Mask */
 
-#define PMP_PMPCFG_X_Pos 2U /*!< PMP PMPCFG: X Position */
+#define PMP_PMPCFG_X_Pos 2U                          /*!< PMP PMPCFG: X Position */
 #define PMP_PMPCFG_X_Msk (0x1UL << PMP_PMPCFG_X_Pos) /*!< PMP PMPCFG: X Mask */
 
-#define PMP_PMPCFG_A_Pos 3U /*!< PMP PMPCFG: A Position */
+#define PMP_PMPCFG_A_Pos 3U                          /*!< PMP PMPCFG: A Position */
 #define PMP_PMPCFG_A_Msk (0x3UL << PMP_PMPCFG_A_Pos) /*!< PMP PMPCFG: A Mask */
 
-#define PMP_PMPCFG_L_Pos 7U /*!< PMP PMPCFG: L Position */
+#define PMP_PMPCFG_L_Pos 7U                          /*!< PMP PMPCFG: L Position */
 #define PMP_PMPCFG_L_Msk (0x1UL << PMP_PMPCFG_L_Pos) /*!< PMP PMPCFG: L Mask */
 
 typedef enum {
@@ -260,25 +260,25 @@ typedef struct
 /*@} end of group CSI_PMP */
 
 /* CACHE Register Definitions */
-#define CACHE_MHCR_L0BTB_Pos 6U /*!< CACHE MHCR: L0BTB Position */
+#define CACHE_MHCR_L0BTB_Pos 6U                              /*!< CACHE MHCR: L0BTB Position */
 #define CACHE_MHCR_L0BTB_Msk (0x1UL << CACHE_MHCR_L0BTB_Pos) /*!< CACHE MHCR: WA Mask */
 
-#define CACHE_MHCR_BPE_Pos 5U /*!< CACHE MHCR: BPE Position */
+#define CACHE_MHCR_BPE_Pos 5U                            /*!< CACHE MHCR: BPE Position */
 #define CACHE_MHCR_BPE_Msk (0x1UL << CACHE_MHCR_BPE_Pos) /*!< CACHE MHCR: BPE Mask */
 
-#define CACHE_MHCR_RS_Pos 4U /*!< CACHE MHCR: RS Position */
+#define CACHE_MHCR_RS_Pos 4U                           /*!< CACHE MHCR: RS Position */
 #define CACHE_MHCR_RS_Msk (0x1UL << CACHE_MHCR_RS_Pos) /*!< CACHE MHCR: RS Mask */
 
-#define CACHE_MHCR_WB_Pos 3U /*!< CACHE MHCR: WB Position */
+#define CACHE_MHCR_WB_Pos 3U                           /*!< CACHE MHCR: WB Position */
 #define CACHE_MHCR_WB_Msk (0x1UL << CACHE_MHCR_WB_Pos) /*!< CACHE MHCR: WB Mask */
 
-#define CACHE_MHCR_WA_Pos 2U /*!< CACHE MHCR: WA Position */
+#define CACHE_MHCR_WA_Pos 2U                           /*!< CACHE MHCR: WA Position */
 #define CACHE_MHCR_WA_Msk (0x1UL << CACHE_MHCR_WA_Pos) /*!< CACHE MHCR: WA Mask */
 
-#define CACHE_MHCR_DE_Pos 1U /*!< CACHE MHCR: DE Position */
+#define CACHE_MHCR_DE_Pos 1U                           /*!< CACHE MHCR: DE Position */
 #define CACHE_MHCR_DE_Msk (0x1UL << CACHE_MHCR_DE_Pos) /*!< CACHE MHCR: DE Mask */
 
-#define CACHE_MHCR_IE_Pos 0U /*!< CACHE MHCR: IE Position */
+#define CACHE_MHCR_IE_Pos 0U                           /*!< CACHE MHCR: IE Position */
 #define CACHE_MHCR_IE_Msk (0x1UL << CACHE_MHCR_IE_Pos) /*!< CACHE MHCR: IE Mask */
 
 #define CACHE_INV_ADDR_Pos 6U
@@ -360,12 +360,12 @@ typedef struct
   @{
  */
 #define CORET_BASE (PLIC_BASE + 0x4000000UL) /*!< CORET Base Address */
-#define PLIC_BASE  (0x00E0000000UL) /*!< PLIC Base Address */
+#define PLIC_BASE  (0x00E0000000UL)          /*!< PLIC Base Address */
 //#define PLIC_BASE           (0x4000000000UL)                          /*!< PLIC Base Address */
 
 #define CORET ((CORET_Type *)CORET_BASE) /*!< SysTick configuration struct */
 #define CLINT ((CORET_Type *)CORET_BASE) /*!< CLINT configuration struct */
-#define PLIC  ((PLIC_Type *)PLIC_BASE) /*!< PLIC configuration struct */
+#define PLIC  ((PLIC_Type *)PLIC_BASE)   /*!< PLIC configuration struct */
 
 /*@} */
 
@@ -694,21 +694,21 @@ __STATIC_INLINE uint32_t csi_coret_config(uint32_t ticks, int32_t IRQn)
 
 #if 0
 
-    if(value)
-    {
-        value = value + (uint64_t)ticks;
-        CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
-        CORET->MTIMECMPL0 = (uint32_t)value;
-    }
-    else
-    {
-        uint64_t result;
-        __ASM volatile("csrr %0, 0xc01" : "=r"(result));
+	if(value)
+	{
+		value = value + (uint64_t)ticks;
+		CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
+		CORET->MTIMECMPL0 = (uint32_t)value;
+	}
+	else
+	{
+		uint64_t result;
+		__ASM volatile("csrr %0, 0xc01" : "=r"(result));
 
-        value = result + (uint64_t)ticks;
-        CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
-        CORET->MTIMECMPL0 = (uint32_t)value;
-    }
+		value = result + (uint64_t)ticks;
+		CORET->MTIMECMPH0 = (uint32_t)(value >> 32);
+		CORET->MTIMECMPL0 = (uint32_t)value;
+	}
 
 #else
     value = value + (uint64_t)ticks;
@@ -987,7 +987,7 @@ __STATIC_INLINE void csi_l2cache_clean_invalid(void)
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
-__STATIC_INLINE void csi_dcache_invalid_range(uint64_t *addr, int64_t dsize)
+__STATIC_INLINE void csi_dcache_invalid_range(void *addr, int64_t dsize)
 {
 #if (__DCACHE_PRESENT == 1U)
     int64_t op_size = dsize + (uint64_t)addr % 64;
@@ -1012,7 +1012,7 @@ __STATIC_INLINE void csi_dcache_invalid_range(uint64_t *addr, int64_t dsize)
   \param[in]   addr    address (aligned to 32-byte boundary)
   \param[in]   dsize   size of memory block (in number of bytes)
 */
-__STATIC_INLINE void csi_dcache_clean_range(uint64_t *addr, int64_t dsize)
+__STATIC_INLINE void csi_dcache_clean_range(void *addr, int64_t dsize)
 {
 #if (__DCACHE_PRESENT == 1)
     int64_t op_size = dsize + (uint64_t)addr % 64;
@@ -1037,7 +1037,7 @@ __STATIC_INLINE void csi_dcache_clean_range(uint64_t *addr, int64_t dsize)
   \param[in]   addr    address (aligned to 16-byte boundary)
   \param[in]   dsize   size of memory block (aligned to 16-byte boundary)
 */
-__STATIC_INLINE void csi_dcache_clean_invalid_range(uint64_t *addr, int64_t dsize)
+__STATIC_INLINE void csi_dcache_clean_invalid_range(void *addr, int64_t dsize)
 {
 #if (__DCACHE_PRESENT == 1U)
     int64_t op_size = dsize + (uint64_t)addr % 64;
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_core.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_core.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_core.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_core.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_rv32_gcc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_rv32_gcc.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_rv32_gcc.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_rv32_gcc.h
index 595bdd5b10..d4fc8cb3eb
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_rv32_gcc.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_rv32_gcc.h
@@ -2006,23 +2006,23 @@ __ALWAYS_STATIC_INLINE uint32_t __USAD8(uint32_t x, uint32_t y)
                  sum = absdiff1 + absdiff2 + absdiff3 + absdiff4 \n
                  res[31:0] = sum[31:0] + val3[31:0]
  */
-__ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum)
-{
-    int32_t r, s, t, u;
+// __ALWAYS_STATIC_INLINE uint32_t __USADA8(uint32_t x, uint32_t y, uint32_t sum)
+// {
+//     int32_t r, s, t, u;
 
-#ifdef __cplusplus
-    r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
-    s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
-    t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
-    u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF;
-#else
-    r = (abs((int32_t)(((x << 24) >> 24) - ((y << 24) >> 24)))) & 0x000000FF;
-    s = (abs((int32_t)(((x << 16) >> 24) - ((y << 16) >> 24)))) & 0x000000FF;
-    t = (abs((int32_t)(((x << 8) >> 24) - ((y << 8) >> 24)))) & 0x000000FF;
-    u = (abs((int32_t)(((x) >> 24) - ((y) >> 24)))) & 0x000000FF;
-#endif
-    return (u + t + s + r + sum);
-}
+// #ifdef __cplusplus
+//     r = (abs((long long)((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
+//     s = (abs((long long)((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
+//     t = (abs((long long)((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
+//     u = (abs((long long)((x) >> 24) - ((y) >> 24))) & 0x000000FF;
+// #else
+//     r = (abs(((x << 24) >> 24) - ((y << 24) >> 24))) & 0x000000FF;
+//     s = (abs(((x << 16) >> 24) - ((y << 16) >> 24))) & 0x000000FF;
+//     t = (abs(((x << 8) >> 24) - ((y << 8) >> 24))) & 0x000000FF;
+//     u = (abs(((x) >> 24) - ((y) >> 24))) & 0x000000FF;
+// #endif
+//     return (u + t + s + r + sum);
+// }
 
 /**
   \brief   Dual 16-bit saturating addition.
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_rv64_gcc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_rv64_gcc.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_rv64_gcc.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_rv64_gcc.h
index 5f75cd42e1..a1cf6f874b
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/Core/Include/csi_rv64_gcc.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/Core/Include/csi_rv64_gcc.h
@@ -9,8 +9,8 @@
  * @date     01. Sep 2018
  ******************************************************************************/
 
-#ifndef _CSI_RV32_GCC_H_
-#define _CSI_RV32_GCC_H_
+#ifndef _CSI_RV64_GCC_H_
+#define _CSI_RV64_GCC_H_
 
 #include 
 
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_common_tables.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_common_tables.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_common_tables.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_common_tables.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_const_structs.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_const_structs.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_const_structs.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_const_structs.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_instance.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_instance.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_instance.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_instance.h
index 3de1a3a86a..88cdece3c9
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_instance.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_instance.h
@@ -44,8 +44,8 @@ extern "C"
 #include 
 #endif
 
-#define LOW_OPTIMIZATION_ENTER
-#define LOW_OPTIMIZATION_EXIT
+#define	LOW_OPTIMIZATION_ENTER
+#define	LOW_OPTIMIZATION_EXIT
 
 #define F64_MAX   ((float64_t)DBL_MAX)
 #define F32_MAX   ((float32_t)FLT_MAX)
@@ -396,9 +396,9 @@ __STATIC_FORCEINLINE uint32_t __USAT(int32_t val, uint32_t sat)
 * @brief definition to pack four 8 bit values.
 */
 #define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) | \
-                                      (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
-                                      (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
-                                      (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+									  (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) | \
+									  (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) | \
+									  (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
 
 /**
  * @brief Clips Q63 to Q31 values.
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_math.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_math.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_math.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_math.h
index 9ee04631a5..78e0bb24c5
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/csi_dsp/include/csi_math.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/csi_dsp/include/csi_math.h
@@ -4038,7 +4038,7 @@ csi_status csi_sqrt_q15(
                    - \ref CSI_MATH_SUCCESS        : input value is positive
                    - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
  */
-#ifdef __riscv
+#ifdef __riscv 
 __STATIC_FORCEINLINE csi_status csi_sqrt_f32(
     float32_t in,
     float32_t * pOut)
@@ -4075,12 +4075,12 @@ csi_status csi_sqrt_f32(
 
 
 /**
-  @brief         Q31 square root function.
-  @param[in]     in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
-  @param[out]    pOut  points to square root of input value
-  @return        execution status
-                   - \ref CSI_MATH_SUCCESS      : input value is positive
-                   - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
+  @brief		 Q31 square root function.
+  @param[in]	 in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF
+  @param[out]	 pOut  points to square root of input value
+  @return		 execution status
+				   - \ref CSI_MATH_SUCCESS		: input value is positive
+				   - \ref CSI_MATH_ARGUMENT_ERROR : input value is negative; *pOut is set to 0
  */
 csi_status csi_sqrt_q31(
     q31_t in,
@@ -4102,19 +4102,19 @@ void csi_vsqrt_f32(
     uint16_t len);
 
  void csi_vsqrt_q15(
-    q15_t *     pIn,
-    q15_t *     pOut,
-    uint16_t    len);
+    q15_t * 	pIn,
+    q15_t * 	pOut,
+    uint16_t	len);
 
 void csi_vsqrt_q31(
-    q31_t *     pIn,
-    q31_t *     pOut,
-    uint16_t    len);
+    q31_t * 	pIn,
+    q31_t * 	pOut,
+    uint16_t	len);
 
 void csi_vsqrt_q7(
-    q7_t *  pIn,
-    q7_t *  pOut,
-    uint16_t    len);
+    q7_t * 	pIn,
+    q7_t * 	pOut,
+    uint16_t	len);
 
 
 #else
@@ -4129,9 +4129,9 @@ __STATIC_FORCEINLINE void csi_vsqrt_f32(
 }
 
 __STATIC_FORCEINLINE void csi_vsqrt_q15(
-    q15_t *     pIn,
-    q15_t *     pOut,
-    uint16_t    len
+    q15_t * 	pIn,
+    q15_t * 	pOut,
+    uint16_t	len
 )
 {
     for (int i = 0; i < len; i++) {
@@ -4139,9 +4139,9 @@ __STATIC_FORCEINLINE void csi_vsqrt_q15(
     }
 }
 __STATIC_FORCEINLINE void csi_vsqrt_q31(
-    q31_t *     pIn,
-    q31_t *     pOut,
-    uint16_t    len
+    q31_t * 	pIn,
+    q31_t * 	pOut,
+    uint16_t	len
 )
 {
     for (int i = 0; i < len; i++) {
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_Sv39.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.c
old mode 100644
new mode 100755
similarity index 94%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_Sv39.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.c
index 1ea15afbed..c2a61d68dd
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_Sv39.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.c
@@ -68,15 +68,13 @@ RV_Sv39_alloc_PageTable_buf(void)
  *
 *******************************************************************************/
 
-BL_Err_Type RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index, volatile uintptr_t *ttb0)
+int RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index, volatile uintptr_t *ttb0)
 {
     uintptr_t smeh, smel, smcir;
     uintptr_t t0;
     volatile uint64_t *ttb1 = NULL;
     volatile uint64_t *ttb2 = NULL;
 
-    /* TODO: check parameters */
-
     if (Sv39_PTE_LOC_JTLB == cfg->where) {
         t0 = cfg->va;
         smeh = ((t0 >> 12) << SMEH_VPN_OFFSET) | cfg->size | cfg->asid;
@@ -108,7 +106,7 @@ BL_Err_Type RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index
 
         *tlb_index = t0;
 
-        return (t0 & (SMCIR_PF | SMCIR_TF)) ? ERROR : SUCCESS;
+        return (t0 & (SMCIR_PF | SMCIR_TF)) ? -1 : 0;
     } else {
         /* top level: 1GB */
         t0 = SV39_VPN2(cfg->va);
@@ -119,12 +117,12 @@ BL_Err_Type RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index
                 /* finish map for top level */
                 ttb0[t0] = (SV39_PA2PPN(cfg->pa) << PTE_PPN_OFFSET) |
                            (cfg->flags);
-                return SUCCESS;
+                return 0;
             } else {
                 ttb1 = RV_Sv39_alloc_PageTable_buf();
 
                 if (NULL == ttb1) {
-                    return NORESC;
+                    return -1;
                 }
 
                 __COMPILE_BARRIER();
@@ -145,12 +143,12 @@ BL_Err_Type RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index
             if (Sv39_PAGESIZE_2MB == cfg->size) {
                 ttb1[t0] = (SV39_PA2PPN(cfg->pa) << PTE_PPN_OFFSET) |
                            (cfg->flags);
-                return SUCCESS;
+                return 0;
             } else {
                 ttb2 = RV_Sv39_alloc_PageTable_buf();
 
                 if (NULL == ttb2) {
-                    return NORESC;
+                    return -1;
                 }
 
                 ttb1[t0] = (SV39_PA2PPN((uint64_t)ttb2) << PTE_PPN_OFFSET) |
@@ -170,7 +168,7 @@ BL_Err_Type RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index
 
     /* flush the D cache */
 
-    return SUCCESS;
+    return 0;
 }
 
 /*@} end of group SV39_Public_Functions */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_Sv39.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.h
old mode 100644
new mode 100755
similarity index 97%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_Sv39.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.h
index 9ca9803170..11dbe95f58
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_Sv39.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_Sv39.h
@@ -2,7 +2,8 @@
 #define __RV_SV39_H__
 
 #include 
-#include "bl808_common.h"
+#include 
+#include 
 
 #define SV39_VPN2(va) (((va) >> (9 + 9 + 12)) & 0x1FF)
 #define SV39_VPN1(va) (((va) >> (0 + 9 + 12)) & 0x1FF)
@@ -222,6 +223,6 @@ __ALWAYS_STATIC_INLINE void RV_Sv39_Set_SATP(uintptr_t asid, uintptr_t *ppn)
 }
 
 /* cache config into jTLB, return tlb index if success */
-BL_Err_Type RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index, volatile uint64_t *ttb0);
+int RV_Sv39_Create_PageMapping(Sv39_PTE_cfg_t *cfg, uintptr_t *tlb_index, volatile uintptr_t *ttb0);
 
 #endif /* __RV_SV39_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hart.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hart.c
old mode 100644
new mode 100755
similarity index 81%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hart.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hart.c
index 1c1ed1d711..60ef44f086
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hart.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hart.c
@@ -1,6 +1,11 @@
 #include "csi_core.h"
 #include "rv_hart.h"
-#include "riscv_encoding.h"
+#include 
+
+#define PRV_U 0
+#define PRV_S 1
+#define PRV_H 2
+#define PRV_M 3
 
 #define INSERT_FIELD(val, which, fieldval) \
     (((val) & ~(which)) | ((fieldval) * ((which) & ~((which)-1))))
@@ -17,7 +22,7 @@ void __attribute__((noreturn)) rv_hart_hang(void)
 /* determine CPU extension, return non-zero support */
 int rv_hart_misa_ext_chk(char ext)
 {
-    unsigned long misa = read_csr(misa);
+    unsigned long misa = READ_CSR(misa);
 
     if (misa) {
         if ('A' <= ext && ext <= 'Z') {
@@ -98,24 +103,24 @@ rv_hart_switch_mode_from_M(uintptr_t arg0, uintptr_t arg1,
             rv_hart_hang();
     }
 
-    val = read_csr(mstatus);
-    val = INSERT_FIELD(val, MSTATUS_MPP, next_mode);
+    val = READ_CSR(mstatus);
+    val = INSERT_FIELD(val, MSTATUS_MPPM, next_mode);
     val = INSERT_FIELD(val, MSTATUS_MPIE, 0);
 
-    write_csr(mstatus, val);
-    write_csr(mepc, next_addr);
+    WRITE_CSR(mstatus, val);
+    WRITE_CSR(mepc, next_addr);
 
     if (next_mode == PRV_S) {
-        write_csr(stvec, next_addr);
-        write_csr(sscratch, 0);
-        write_csr(sie, 0);
-        write_csr(satp, 0);
+        WRITE_CSR(stvec, next_addr);
+        WRITE_CSR(sscratch, 0);
+        WRITE_CSR(sie, 0);
+        WRITE_CSR(satp, 0);
     } else if (next_mode == PRV_U) {
         /* un-implemented
-                write_csr(utvec, next_addr);
-                write_csr(uscratch, 0);
-                write_csr(uie, 0);
-        */
+		        WRITE_CSR(utvec, next_addr);
+		        WRITE_CSR(uscratch, 0);
+		        WRITE_CSR(uie, 0);
+		*/
     }
 
     register unsigned long a0 __asm("a0") = arg0;
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hart.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hart.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hart.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hart.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hpm.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h
old mode 100644
new mode 100755
similarity index 91%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hpm.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h
index b4466058b2..78311671e0
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_hpm.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_hpm.h
@@ -5,7 +5,7 @@
 
 #if (__riscv_xlen == 32)
 
-#define RV_HPM_SET_CPUNTER(name, val)                      \
+#define RV_HPM_SET_COUNTER(name, val)                      \
     do {                                                   \
         uint32_t value = (uint32_t)val;                    \
         __asm volatile("csrw " #name ", %0"                \
@@ -46,7 +46,7 @@
 
 #else
 
-#define RV_HPM_SET_CPUNTER(name, val)       \
+#define RV_HPM_SET_COUNTER(name, val)       \
     do {                                    \
         uint64_t value = val;               \
         __asm volatile("csrw " #name ", %0" \
@@ -114,8 +114,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_ICache_Miss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter3, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter4, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter3, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter4, 0);
 }
 
 /* M-mode: L1 ICache Miss rate measure end              */
@@ -142,8 +142,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_BrPredict_Miss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter8, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter9, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter8, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter9, 0);
 #endif
 #ifdef CPU_D0
     __asm volatile("csrw mhpmevent9, 6"
@@ -154,8 +154,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_BrPredict_Miss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter9, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter10, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter9, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter10, 0);
 #endif
 }
 
@@ -187,8 +187,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_RdMiss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter14, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter15, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter14, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter15, 0);
 #endif
 #ifdef CPU_D0
     __asm volatile("csrw mhpmevent5, 12"
@@ -199,8 +199,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_RdMiss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter5, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter6, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter5, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter6, 0);
 #endif
 }
 
@@ -232,8 +232,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_WrMiss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter16, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter17, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter16, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter17, 0);
 #endif
 #ifdef CPU_D0
     __asm volatile("csrw mhpmevent7, 14"
@@ -244,8 +244,8 @@ inline __attribute__((always_inline)) void RV_HPM_L1_DCache_WrMiss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter7, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter8, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter7, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter8, 0);
 #endif
 }
 
@@ -280,9 +280,9 @@ inline __attribute__((always_inline)) void RV_HPM_TLB_Miss_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter5, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter6, 0);
-    RV_HPM_SET_CPUNTER(mhpmcounter7, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter5, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter6, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter7, 0);
 }
 
 /* M-mode: TLB miss count measure end      */
@@ -307,7 +307,7 @@ inline __attribute__((always_inline)) void RV_HPM_Store_Insn_Init_M(void)
                    :
                    :
                    : "memory");
-    RV_HPM_SET_CPUNTER(mhpmcounter13, 0);
+    RV_HPM_SET_COUNTER(mhpmcounter13, 0);
 }
 
 /* M-mode: Store Instruction counter measure end      */
@@ -323,7 +323,7 @@ inline __attribute__((always_inline)) void RV_HPM_Store_Insn_Stop_M(uint64_t *sc
 /* M-Mode: Set cycle counter */
 inline __attribute__((always_inline)) void RV_HPM_Cycle_Init_M(void)
 {
-    RV_HPM_SET_CPUNTER(mcycle, 0);
+    RV_HPM_SET_COUNTER(mcycle, 0);
 }
 
 /* M-Mode: Get cycle counter */
@@ -338,7 +338,7 @@ inline __attribute__((always_inline)) void RV_HPM_Cycle_Get_M(uint64_t *cycle)
 /* M-Mode: Set minstret counter */
 inline __attribute__((always_inline)) void RV_HPM_Instret_Init_M(void)
 {
-    RV_HPM_SET_CPUNTER(minstret, 0);
+    RV_HPM_SET_COUNTER(minstret, 0);
 }
 
 /* M-Mode: Get minstret counter */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c
index b099df57c6..0e9b3f77ea
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_pmp.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.c
@@ -274,6 +274,8 @@ pmp_status_type_e rvpmp_fill_entry(const pmp_config_entry_t *entry, uintptr_t i,
     am = entry->entry_flag & ENTRY_FLAG_ADDR_MASK;
 
     switch (am) {
+        case ENTRY_FLAG_ADDR_OFF:
+            break;
         case ENTRY_FLAG_ADDR_TOR:
             pa >>= 2;
             break;
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h
new file mode 100755
index 0000000000..851db5ce57
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_pmp.h
@@ -0,0 +1,75 @@
+#ifndef _RV_PMP_H_
+#define _RV_PMP_H_
+
+#include "stdint.h"
+
+#define RV_PMP_ENTRY          (8)
+
+#define ENTRY_FLAG_PERM_R     (1 << 0)
+#define ENTRY_FLAG_PERM_W     (1 << 1)
+#define ENTRY_FLAG_PERM_X     (1 << 2)
+#define ENTRY_FLAG_ADDR_OFF   (0 << 3)
+#define ENTRY_FLAG_ADDR_TOR   (1 << 3)
+#define ENTRY_FLAG_ADDR_NAPOT (3 << 3)
+#define ENTRY_FLAG_ADDR_MASK  (3 << 3)
+#define ENTRY_FLAG_M_MODE_L   (1 << 7)
+
+#define ENTRY_FLAG_SIZE       (8)
+#define ENTRY_FLAG_MASK       (0xFF)
+
+#define ENTRY_IN_CFG_REG      (__riscv_xlen / ENTRY_FLAG_SIZE)
+
+/* E907: the smallest granularity is 128B */
+/* C906: the smallest granularity is 4K */
+#define PMP_REG_SZ_128B       (1 << 7)
+#define PMP_REG_SZ_256B       (1 << 8)
+#define PMP_REG_SZ_512B       (1 << 9)
+#define PMP_REG_SZ_1K         (1 << 10)
+#define PMP_REG_SZ_2K         (1 << 11)
+#define PMP_REG_SZ_4K         (1 << 12)
+#define PMP_REG_SZ_8K         (1 << 13)
+#define PMP_REG_SZ_16K        (1 << 14)
+#define PMP_REG_SZ_32K        (1 << 15)
+#define PMP_REG_SZ_64K        (1 << 16)
+#define PMP_REG_SZ_128K       (1 << 17)
+#define PMP_REG_SZ_256K       (1 << 18)
+#define PMP_REG_SZ_512K       (1 << 19)
+#define PMP_REG_SZ_1M         (1 << 20)
+#define PMP_REG_SZ_2M         (1 << 21)
+#define PMP_REG_SZ_4M         (1 << 22)
+#define PMP_REG_SZ_8M         (1 << 23)
+#define PMP_REG_SZ_16M        (1 << 24)
+#define PMP_REG_SZ_32M        (1 << 25)
+#define PMP_REG_SZ_64M        (1 << 26)
+#define PMP_REG_SZ_128M       (1 << 27)
+#define PMP_REG_SZ_256M       (1 << 28)
+#define PMP_REG_SZ_512M       (1 << 29)
+#define PMP_REG_SZ_1G         (1 << 30)
+#define PMP_REG_SZ_1024M      (PMP_REG_SZ_1G)
+
+typedef enum _pmp_status_type_ {
+    PMP_STATUS_OK = 0,
+    PMP_STATUS_BUSY,
+    PMP_STATUS_DENIED,
+    PMP_STATUS_INVALID,
+    PMP_STATUS_UNSUPPORTED,
+    PMP_STATUS_MAX = 0x7FFFFFFF
+} pmp_status_type_e;
+
+typedef enum _addr_match_type_ {
+    PMP_ADDR_MATCH_OFF = 0,
+    PMP_ADDR_MATCH_TOR,
+    PMP_ADDR_MATCH_NA4,
+    PMP_ADDR_MATCH_NAPOT
+} pmp_addr_match_type_e;
+
+typedef struct _pmp_config_entry {
+    uintptr_t entry_pa_base;
+    uintptr_t entry_pa_length;
+    uintptr_t entry_flag;
+} pmp_config_entry_t;
+
+pmp_status_type_e rvpmp_fill_entry(const pmp_config_entry_t *entry, uintptr_t i, uintptr_t force);
+pmp_status_type_e rvpmp_init(const pmp_config_entry_t *entry, uintptr_t n);
+
+#endif /* _RV_PMP_H_ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_syscall.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_syscall.h
old mode 100644
new mode 100755
similarity index 98%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_syscall.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_syscall.h
index a8c843956c..27da9a83c9
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/risc-v/rv_syscall.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/arch/risc-v/t-head/rv_syscall.h
@@ -2,7 +2,6 @@
 #define _RV_SYSCALL_H_
 
 #include 
-#include 
 
 #define RV_SYSCALL_BACK_TO_MACHINE 0
 #define RV_SYSCALL_WFI             1
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_adc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_adc.h
new file mode 100755
index 0000000000..5ea85a0a95
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_adc.h
@@ -0,0 +1,303 @@
+#ifndef _BFLB_ADC_H
+#define _BFLB_ADC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */
+
+/** @defgroup ADC_CHANNEL adc channel definition
+  * @{
+  */
+#define ADC_CHANNEL_0         0
+#define ADC_CHANNEL_1         1
+#define ADC_CHANNEL_2         2
+#define ADC_CHANNEL_3         3
+#define ADC_CHANNEL_4         4
+#define ADC_CHANNEL_5         5
+#define ADC_CHANNEL_6         6
+#define ADC_CHANNEL_7         7
+#define ADC_CHANNEL_8         8
+#define ADC_CHANNEL_9         9
+#define ADC_CHANNEL_10        10
+#define ADC_CHANNEL_11        11
+#define ADC_CHANNEL_DACA      12
+#define ADC_CHANNEL_DACB      13
+#define ADC_CHANNEL_TSEN_P    14
+#define ADC_CHANNEL_TSEN_N    15
+#define ADC_CHANNEL_VREF      16
+#define ADC_CHANNEL_VABT_HALF 18
+#define ADC_CHANNEL_GND       23
+/**
+  * @}
+  */
+
+/** @defgroup ADC_CLK_DIV adc clock divison definition
+  * @{
+  */
+#define ADC_CLK_DIV_4  1
+#define ADC_CLK_DIV_8  2
+#define ADC_CLK_DIV_12 3
+#define ADC_CLK_DIV_16 4
+#define ADC_CLK_DIV_20 5
+#define ADC_CLK_DIV_24 6
+#define ADC_CLK_DIV_32 7
+/**
+  * @}
+  */
+
+/** @defgroup ADC_RESOLUTION adc resolution definition
+  * @{
+  */
+#define ADC_RESOLUTION_12B 0
+#define ADC_RESOLUTION_14B 2
+#define ADC_RESOLUTION_16B 4
+/**
+  * @}
+  */
+
+/** @defgroup ADC_VREF adc reference select definition
+  * @{
+  */
+#define ADC_VREF_3P2V 0
+#define ADC_VREF_2P0V 1
+/**
+  * @}
+  */
+
+/** @defgroup ADC_TSEN_MOD adc tsen mode definition
+  * @{
+  */
+#define ADC_TSEN_MOD_INTERNAL_DIODE 0
+#define ADC_TSEN_MOD_EXTERNAL_DIODE 1
+/**
+  * @}
+  */
+
+/** @defgroup ADC_INTSTS adc interrupt status definition
+  * @{
+  */
+#define ADC_INTSTS_NEG_SATURATION (1 << 0)
+#define ADC_INTSTS_POS_SATURATION (1 << 1)
+#define ADC_INTSTS_FIFO_UNDERRUN  (1 << 2)
+#define ADC_INTSTS_FIFO_OVERRUN   (1 << 3)
+#define ADC_INTSTS_ADC_READY      (1 << 4)
+/**
+  * @}
+  */
+
+/** @defgroup ADC_INTCLR adc interrupt clear definition
+  * @{
+  */
+#define ADC_INTCLR_NEG_SATURATION (1 << 0)
+#define ADC_INTCLR_POS_SATURATION (1 << 1)
+#define ADC_INTCLR_FIFO_UNDERRUN  (1 << 2)
+#define ADC_INTCLR_FIFO_OVERRUN   (1 << 3)
+#define ADC_INTCLR_ADC_READY      (1 << 4)
+/**
+  * @}
+  */
+
+/**
+ * @brief ADC configuration structure
+ *
+ * @param clk_div                ADC clock divison, use @ref ADC_CLK_DIV
+ * @param scan_conv_mode         ADC scan mode enable
+ * @param continuous_conv_mode   ADC continuous conversion enable
+ * @param differential_mode      ADC differential mode enable
+ * @param resolution             ADC resolution, use @ref ADC_RESOLUTION
+ * @param vref                   ADC reference select, use @ref ADC_VREF
+ */
+struct bflb_adc_config_s {
+    uint8_t clk_div;
+    uint8_t scan_conv_mode;
+    uint8_t continuous_conv_mode;
+    uint8_t differential_mode;
+    uint8_t resolution;
+    uint8_t vref;
+};
+
+/**
+ * @brief ADC channel select
+ *
+ * @param pos_chan         Select ADC positive input in none-scan mode
+ * @param neg_chan         Select ADC negative input in none-scan mode
+ */
+struct bflb_adc_channel_s {
+    uint8_t pos_chan;
+    uint8_t neg_chan;
+};
+
+/**
+ * @brief ADC result select
+ *
+ * @param pos_chan         ADC positive channel
+ * @param neg_chan         ADC negative channel
+ * @param value            ADC value
+ * @param millivolt        ADC voltage result
+ */
+struct bflb_adc_result_s {
+    int8_t pos_chan;
+    int8_t neg_chan;
+    int32_t value;
+    int32_t millivolt;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize adc.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save adc configuration
+ */
+void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *config);
+
+/**
+ * @brief Deinitialize adc.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable adc rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_adc_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Config adc channels to sample.
+ *
+ * @param [in] dev device handle
+ * @param [in] chan pointer to the channel configurations.
+ * @param [in] channels pair number of channels
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_adc_channel_config(struct bflb_device_s *dev, struct bflb_adc_channel_s *chan, uint8_t channels);
+
+/**
+ * @brief Start adc conversion
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_start_conversion(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop adc conversion
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_stop_conversion(struct bflb_device_s *dev);
+
+/**
+ * @brief Get adc number of completed conversions
+ *
+ * @param [in] dev device handle
+ * @return number of completed conversions
+ */
+uint8_t bflb_adc_get_count(struct bflb_device_s *dev);
+
+/**
+ * @brief Read adc conversion value
+ *
+ * @param [in] dev device handle
+ * @return conversion value
+ */
+uint32_t bflb_adc_read_raw(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable or disable adc conversion completion interrupt.
+ * Triggerring when a channel conversion is completed.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_adc_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable adc error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_adc_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get adc interrupt instatus.
+ *
+ * @param [in] dev device handle
+ * @return interrupt instatus value, use @ref ADC_INTSTS
+ */
+uint32_t bflb_adc_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear adc interrupt instatus.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear interrupt clear value, use @ref ADC_INTCLR
+ */
+void bflb_adc_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Parse adc conversion value into millivolt and actual numerical value.
+ *
+ * @param [in] dev device handle
+ * @param [in] buffer pointer to adc original value from bflb_adc_read_raw api
+ * @param [out] result pointer to save parse result
+ * @param [in] count count to parse
+ */
+void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct bflb_adc_result_s *result, uint16_t count);
+
+/**
+ * @brief Initialize adc temperature sensor
+ *
+ * @param [in] dev device handle
+ * @param [in] tsen_mod temperature sensor mode, use @ref ADC_TSEN_MOD
+ */
+void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod);
+
+/**
+ * @brief Get adc temperature
+ *
+ * @param [in] dev device handle
+ * @return temperature
+ */
+float bflb_adc_tsen_get_temp(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable adc vbat power.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_vbat_enable(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable adc vbat power.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_adc_vbat_disable(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_auadc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_auadc.h
new file mode 100755
index 0000000000..6e4785fc60
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_auadc.h
@@ -0,0 +1,182 @@
+#ifndef _BFLB_AUADC_H
+#define _BFLB_AUADC_H
+
+#include "bflb_core.h"
+
+/**
+ *  @defgroup AUADC_SAMPLING_RATE auadc sampling rate
+ */
+#define AUADC_SAMPLING_RATE_8K           0  /* audio mode */
+#define AUADC_SAMPLING_RATE_16K          1  /* audio mode */
+#define AUADC_SAMPLING_RATE_24K          2  /* audio mode, same as 22.02K, adjust the AUPLL clock */
+#define AUADC_SAMPLING_RATE_32K          3  /* audio mode */
+#define AUADC_SAMPLING_RATE_48K          4  /* audio mode, same as 44.1K, adjust the AUPLL clock */
+#define AUADC_SAMPLING_RATE_MEASURE_128K 8  /* only used in ADC measurement mode */
+#define AUADC_SAMPLING_RATE_MEASURE_256K 9  /* only used in ADC measurement mode */
+#define AUADC_SAMPLING_RATE_MEASURE_512K 10 /* only used in ADC measurement mode */
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUADC_INPUT_MODE auadc input mode
+ */
+#define AUADC_INPUT_MODE_ADC             0 /* Analog ADC */
+#define AUADC_INPUT_MODE_PDM_L           1 /* PDM left channel */
+#define AUADC_INPUT_MODE_PDM_R           2 /* PDM right channel */
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUADC_DATA_FORMAT auadc data format
+ */
+#define AUADC_DATA_FORMAT_16BIT          3
+#define AUADC_DATA_FORMAT_20BIT          2
+#define AUADC_DATA_FORMAT_24BIT          1
+#define AUADC_DATA_FORMAT_32BIT          0
+/**
+  * @}
+  */
+
+/**
+ *  @brief AUADC_ADC_ANALOG_CH auadc adc input ch
+ */
+#define AUADC_ADC_ANALOG_CH_0            0
+#define AUADC_ADC_ANALOG_CH_1            1
+#define AUADC_ADC_ANALOG_CH_2            2
+#define AUADC_ADC_ANALOG_CH_3            3
+#define AUADC_ADC_ANALOG_CH_4            4
+#define AUADC_ADC_ANALOG_CH_5            5
+#define AUADC_ADC_ANALOG_CH_6            6
+#define AUADC_ADC_ANALOG_CH_7            7
+/**
+  * @}
+  */
+
+/**
+ *  @brief AUADC_ADC_MEASURE_RATE auadc adc Sampling rate in measurement mode, @ AUADC_SAMPLING_RATE_MEASURE_256K
+ */
+
+#define AUADC_ADC_MEASURE_RATE_SPS_2_5   0
+#define AUADC_ADC_MEASURE_RATE_SPS_5     1
+#define AUADC_ADC_MEASURE_RATE_SPS_10    2
+#define AUADC_ADC_MEASURE_RATE_SPS_20    3
+#define AUADC_ADC_MEASURE_RATE_SPS_25    4
+#define AUADC_ADC_MEASURE_RATE_SPS_50    5
+#define AUADC_ADC_MEASURE_RATE_SPS_100   6
+#define AUADC_ADC_MEASURE_RATE_SPS_200   7
+#define AUADC_ADC_MEASURE_RATE_SPS_400   8
+#define AUADC_ADC_MEASURE_RATE_SPS_800   9
+#define AUADC_ADC_MEASURE_RATE_SPS_1000  10
+#define AUADC_ADC_MEASURE_RATE_SPS_2000  11
+#define AUADC_ADC_MEASURE_RATE_SPS_4000  12
+
+/**
+  * @}
+  */
+
+/**
+ *  @brief AUADC_ADC_MODE auadc adc mode
+ */
+#define AUADC_ADC_MODE_AUDIO             0
+#define AUADC_ADC_MODE_MEASURE           1
+/**
+  * @}
+  */
+
+/**
+ *  @brief AUADC_ADC_PGA_MODE auadc adc mode, Ac or DC, differential or single
+ */
+#define AUADC_ADC_PGA_MODE_AC_DIFFER     0
+#define AUADC_ADC_PGA_MODE_AC_SINGLE     1
+#define AUADC_ADC_PGA_MODE_DC_DIFFER     2
+#define AUADC_ADC_PGA_MODE_DC_SINGLE     3
+/**
+  * @}
+  */
+
+/** @defgroup AUADC_INTMASK auadc interrupt status definition
+  * @{
+  */
+#define AUADC_INTMASK_FIFO_OVER          (1 << 1)
+#define AUADC_INTMASK_FIFO_UNDER         (1 << 2)
+#define AUADC_INTMASK_FIFO_AVAILABLE     (1 << 3)
+/**
+  * @}
+  */
+
+/** @defgroup AUADC_INTSTS auadc interrupt status definition
+  * @{
+  */
+#define AUADC_INTSTS_FIFO_OVER           (1 << 1)
+#define AUADC_INTSTS_FIFO_UNDER          (1 << 2)
+#define AUADC_INTSTS_FIFO_AVAILABLE      (1 << 4)
+/**
+  * @}
+  */
+
+/** @defgroup AUADC_CMD auadc feature control cmd definition
+  * @{
+  */
+#define AUADC_CMD_RECORD_START           (0x01)
+#define AUADC_CMD_RECORD_STOP            (0x02)
+#define AUADC_CMD_SET_VOLUME_VAL         (0x03)
+#define AUADC_CMD_SET_PGA_GAIN_VAL       (0x04)
+#define AUADC_CMD_CLEAR_RX_FIFO          (0x05)
+#define AUADC_CMD_GET_RX_FIFO_CNT        (0x06)
+/**
+  * @}
+  */
+
+/**
+ * @brief auadc initialization configuration structure
+ *
+ * @param sampling_rate         auadc sampling rate, use @ref AUADC_SAMPLING_RATE
+ * @param input_mode            auadc mode, use @ref AUADC_INPUT_MODE
+ * @param data_format           auadc fifo data format, use @ref AUADC_DATA_FORMAT
+ * @param fifo_threshold        auadc tx fifo threshold, 0 ~ 7
+ */
+struct bflb_auadc_init_config_s {
+    uint8_t sampling_rate;
+    uint8_t input_mode;
+    uint8_t data_format;
+    uint8_t fifo_threshold;
+};
+
+/**
+ * @brief auadc adc analog initialization configuration structure
+ *
+ * @param analog_adc_en         auadc sampling rate, use true or false
+ * @param adc_mode              auadc adc work pattern, use @ref AUADC_ADC_MODE
+ * @param adc_pga_mode          auadc adc PGA mode, use @ref AUADC_ADC_PGA_MODE
+ * @param adc_pga_posi_ch       auadc adc positive channel selection, use @ref AUADC_ADC_ANALOG_CH
+ * @param adc_pga_nega_ch       auadc adc negative channel selection, This channel is valid only when adc_pga_mode is differential, use @ref AUADC_ADC_ANALOG_CH
+ * @param adc_pga_gain          auadc adc PGA Gain control, 6dB ~ 42dB, step by 3db
+ * @param adc_measure_rate      auadc adc sampling rate in measurement mode @ AUADC_SAMPLING_RATE_MEASURE_256K, use @ref AUADC_ADC_MEASURE_RATE
+ */
+struct bflb_auadc_adc_init_config_s {
+    uint8_t auadc_analog_en;
+    uint8_t adc_mode;
+    uint8_t adc_pga_mode;
+    uint8_t adc_pga_posi_ch;
+    uint8_t adc_pga_nega_ch;
+    uint8_t adc_pga_gain;
+    uint8_t adc_measure_rate;
+};
+
+int bflb_auadc_init(struct bflb_device_s *dev, const struct bflb_auadc_init_config_s *config);
+
+int bflb_auadc_adc_init(struct bflb_device_s *dev, const struct bflb_auadc_adc_init_config_s *config);
+
+int bflb_auadc_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+int bflb_auadc_int_mask(struct bflb_device_s *dev, uint32_t int_sts);
+
+int bflb_auadc_int_unmask(struct bflb_device_s *dev, uint32_t int_sts);
+
+int bflb_auadc_get_intstatus(struct bflb_device_s *dev);
+
+int bflb_auadc_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_audac.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_audac.h
new file mode 100755
index 0000000000..5bf695ee59
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_audac.h
@@ -0,0 +1,165 @@
+#ifndef _BFLB_AUDAC_H
+#define _BFLB_AUDAC_H
+
+#include "bflb_core.h"
+
+/**
+ *  @defgroup AUDAC_SAMPLING_RATE audac sampling rate
+ */
+#define AUDAC_SAMPLING_RATE_8K                      0
+#define AUDAC_SAMPLING_RATE_16K                     1
+#define AUDAC_SAMPLING_RATE_22P05K                  5
+#define AUDAC_SAMPLING_RATE_24K                     3
+#define AUDAC_SAMPLING_RATE_32K                     2
+#define AUDAC_SAMPLING_RATE_44P1K                   6
+#define AUDAC_SAMPLING_RATE_48K                     4
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUDAC_OUTPUT_MODE audac output mode
+ */
+#define AUDAC_OUTPUT_MODE_PWM                       0
+#define AUDAC_OUTPUT_MODE_GPDAC_CH_A                1
+#define AUDAC_OUTPUT_MODE_GPDAC_CH_B                2
+#define AUDAC_OUTPUT_MODE_GPDAC_CH_A_B              3
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUDAC_SOURCE_CHANNEL source channels num
+ */
+#define AUDAC_SOURCE_CHANNEL_SINGLE                 0x01
+#define AUDAC_SOURCE_CHANNEL_DUAL                   0x03
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUDAC_MIXER_MODE audac mixer mode, this parameter is valid only in AUDAC_SOURCE_CHANNEL_DUAL mode
+ */
+#define AUDAC_MIXER_MODE_ONLY_L                     0
+#define AUDAC_MIXER_MODE_ONLY_R                     1
+#define AUDAC_MIXER_MODE_SUM                        2
+#define AUDAC_MIXER_MODE_AVERAGE                    3
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUDAC_DATA_FORMAT audac data format
+ */
+#define AUDAC_DATA_FORMAT_16BIT                     3
+#define AUDAC_DATA_FORMAT_20BIT                     2
+#define AUDAC_DATA_FORMAT_24BIT                     1
+#define AUDAC_DATA_FORMAT_32BIT                     0
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUDAC_RAMP_RATE audac volume ramp rate
+ */
+#define AUDAC_RAMP_RATE_FS_2                        0
+#define AUDAC_RAMP_RATE_FS_4                        1
+#define AUDAC_RAMP_RATE_FS_8                        2
+#define AUDAC_RAMP_RATE_FS_16                       3
+#define AUDAC_RAMP_RATE_FS_32                       4
+#define AUDAC_RAMP_RATE_FS_64                       5
+#define AUDAC_RAMP_RATE_FS_128                      6
+#define AUDAC_RAMP_RATE_FS_256                      7
+#define AUDAC_RAMP_RATE_FS_512                      8
+#define AUDAC_RAMP_RATE_FS_1024                     9
+#define AUDAC_RAMP_RATE_FS_2048                     10
+/**
+  * @}
+  */
+
+/**
+ *  @defgroup AUDAC_VOLUME_UPDATE_MODE audac volume ramp rate
+ */
+#define AUDAC_VOLUME_UPDATE_MODE_FORCE              0
+#define AUDAC_VOLUME_UPDATE_MODE_RAMP               1
+#define AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING 2
+/**
+  * @}
+  */
+
+/** @defgroup AUDAC_INTSTS audac interrupt status definition
+  * @{
+  */
+#define AUDAC_INTSTS_VOLUME_RAMP                    (1 << 0)
+#define AUDAC_INTSTS_FIFO_OVER                      (1 << 1)
+#define AUDAC_INTSTS_FIFO_UNDER                     (1 << 2)
+#define AUDAC_INTSTS_FIFO_AVAILABLE                 (1 << 3)
+
+/** @defgroup AUDAC_CMD audac feature control cmd definition
+  * @{
+  */
+#define AUDAC_CMD_PLAY_START                        (0x01)
+#define AUDAC_CMD_PLAY_STOP                         (0x02)
+#define AUDAC_CMD_SET_MUTE                          (0x03)
+#define AUDAC_CMD_SET_VOLUME_VAL                    (0x04)
+#define AUDAC_CMD_CLEAR_TX_FIFO                     (0x05)
+#define AUDAC_CMD_GET_TX_FIFO_CNT                   (0x06)
+
+/**
+  * @}
+  */
+
+/**
+ * @brief AUDAC initialization configuration structure
+ *
+ * @param sampling_rate         AUDAC sampling rate, use @ref AUDAC_SAMPLING_RATE
+ * @param output_mode           AUDAC mode, use @ref AUDAC_OUTPUT_MODE
+ * @param source_channels_num   AUDAC source channels num, use @ref AUDAC_SOURCE_CHANNEL
+ * @param mixer_mode            AUDAC mixer mode, valid only in AUDAC_SOURCE_CHANNEL_DUAL mode, use @ref AUDAC_MIXER_MODE
+ * @param data_format           AUDAC audac data format, use @ref AUDAC_DATA_FORMAT
+ * @param fifo_threshold        AUDAC tx fifo threshold, 0 ~ 7
+ * @param dma_enable            AUDAC dma mode enable, use true or false
+ */
+struct bflb_audac_init_config_s {
+    uint8_t sampling_rate;
+    uint8_t output_mode;
+    uint8_t source_channels_num;
+    uint8_t mixer_mode;
+    uint8_t data_format;
+    uint8_t fifo_threshold;
+};
+
+/**
+ * @brief AUDAC volume configuration structure
+ *
+ * @param mute_ramp_en              AUDAC mute mode en, use true or false
+ * @param mute_up_ramp_rate         AUDAC mute up ramp rate, valid when mute_ramp_en is true, use @ref AUDAC_RAMP_RATE
+ * @param mute_down_ramp_rate       AUDAC mute down ramp rate, valid when mute_ramp_en is true, use @ref AUDAC_RAMP_RATE
+ * @param volume_update_mode        AUDAC volume update mode, use @ref AUDAC_VOLUME_UPDATE_MODE
+ * @param volume_ramp_rate          AUDAC volume ramp rate, valid when volume_update_mode is not AUDAC_VOLUME_UPDATE_MODE_FORCE, use @ref AUDAC_RAMP_RATE
+ * @param volume_zero_cross_timeout AUDAC volume update zero cross timeout period, valid only in AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING mode
+ */
+struct bflb_audac_volume_config_s {
+    bool mute_ramp_en;
+    uint8_t mute_up_ramp_rate;
+    uint8_t mute_down_ramp_rate;
+    uint8_t volume_update_mode;
+    uint8_t volume_ramp_rate;
+    uint8_t volume_zero_cross_timeout;
+};
+
+int bflb_audac_init(struct bflb_device_s *dev, const struct bflb_audac_init_config_s *config);
+
+int bflb_audac_volume_init(struct bflb_device_s *dev, const struct bflb_audac_volume_config_s *vol_cfg);
+
+int bflb_audac_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+int bflb_audac_int_mask(struct bflb_device_s *dev, uint32_t mask);
+
+int bflb_audac_get_intstatus(struct bflb_device_s *dev);
+
+int bflb_audac_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+int bflb_audac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cam.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cam.h
new file mode 100755
index 0000000000..44db5401b1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cam.h
@@ -0,0 +1,325 @@
+#ifndef _BFLB_CAM_H
+#define _BFLB_CAM_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup CAM
+  * @{
+  */
+
+/** @defgroup CAM_INPUT_FORMAT CAMERA input format definition
+  * @{
+  */
+#define CAM_INPUT_FORMAT_YUV422_YUYV 0
+#define CAM_INPUT_FORMAT_YUV422_YVYU 1
+#define CAM_INPUT_FORMAT_YUV422_UYVY 2
+#define CAM_INPUT_FORMAT_YUV422_VYUY 3
+#define CAM_INPUT_FORMAT_GRAY        4
+#define CAM_INPUT_FORMAT_RGB565      5
+#define CAM_INPUT_FORMAT_BGR565      6
+#define CAM_INPUT_FORMAT_RGB888      7
+#define CAM_INPUT_FORMAT_BGR888      8
+/**
+  * @}
+  */
+
+/** @defgroup CAM_OUTPUT_FORMAT CAMERA output format definition
+  * @{
+  */
+#define CAM_OUTPUT_FORMAT_AUTO             0
+#define CAM_OUTPUT_FORMAT_YUV422           1
+#define CAM_OUTPUT_FORMAT_GRAY             2
+#define CAM_OUTPUT_FORMAT_YUV422_UV        3
+#define CAM_OUTPUT_FORMAT_YUV420_UV        4
+#define CAM_OUTPUT_FORMAT_RGB565_OR_BGR565 5
+#define CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 6
+#if !defined(BL702)
+#define CAM_OUTPUT_FORMAT_RGB888_TO_RGB565   7
+#define CAM_OUTPUT_FORMAT_RGB888_TO_BGR565   8
+#define CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888 9
+#endif
+
+/**
+  * @}
+  */
+
+/** @defgroup CAM_INTSTS CAMERA interrupt status definition
+  * @{
+  */
+#if defined(BL702)
+#define CAM_INTSTS_NORMAL           (1 << 0)
+#define CAM_INTSTS_MEMORY_OVERWRITE (1 << 2)
+#define CAM_INTSTS_FRAME_OVERWRITE  (1 << 4)
+#define CAM_INTSTS_FIFO_OVERWRITE   (1 << 6)
+#define CAM_INTSTS_HSYNC_MISMATCH   (1 << 8)
+#define CAM_INTSTS_VSYNC_MISMATCH   (1 << 9)
+#else
+#define CAM_INTSTS_NORMAL           (1 << 12)
+#define CAM_INTSTS_MEMORY_OVERWRITE (1 << 13)
+#define CAM_INTSTS_FRAME_OVERWRITE  (1 << 14)
+#define CAM_INTSTS_FIFO_OVERWRITE   (1 << 15)
+#define CAM_INTSTS_HSYNC_MISMATCH   (1 << 21)
+#define CAM_INTSTS_VSYNC_MISMATCH   (1 << 22)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup CAM_INTMASK CAMERA interrupt mask definition
+  * @{
+  */
+#if defined(BL702)
+#define CAM_INTMASK_NORMAL           (1 << 0)
+#define CAM_INTMASK_MEMORY_OVERWRITE (1 << 2)
+#define CAM_INTMASK_FRAME_OVERWRITE  (1 << 3)
+#define CAM_INTMASK_FIFO_OVERWRITE   (1 << 4)
+#define CAM_INTMASK_HSYNC_MISMATCH   (1 << 5)
+#define CAM_INTMASK_VSYNC_MISMATCH   (1 << 6)
+#else
+#define CAM_INTMASK_NORMAL           (1 << 8)
+#define CAM_INTMASK_MEMORY_OVERWRITE (1 << 9)
+#define CAM_INTMASK_FRAME_OVERWRITE  (1 << 10)
+#define CAM_INTMASK_FIFO_OVERWRITE   (1 << 11)
+#define CAM_INTMASK_HSYNC_MISMATCH   (1 << 6)
+#define CAM_INTMASK_VSYNC_MISMATCH   (1 << 7)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup CAM_INTCLR CAMERA interrupt clear definition
+  * @{
+  */
+#define CAM_INTCLR_NORMAL           (1 << 4)
+#define CAM_INTCLR_MEMORY_OVERWRITE (1 << 5)
+#define CAM_INTCLR_FRAME_OVERWRITE  (1 << 6)
+#define CAM_INTCLR_FIFO_OVERWRITE   (1 << 7)
+#define CAM_INTCLR_HSYNC_MISMATCH   (1 << 8)
+#define CAM_INTCLR_VSYNC_MISMATCH   (1 << 9)
+/**
+  * @}
+  */
+
+/** @defgroup CAM_POLARITY CAMERA hsync/vsync polarity active level definition
+  * @{
+  */
+#define CAM_POLARITY_ACTIVE_LOW  0
+#define CAM_POLARITY_ACTIVE_HIGH 1
+/**
+  * @}
+  */
+
+/** @defgroup CAM_INPUT_SOURCE CAMERA input source definition
+  * @{
+  */
+#define CAM_INPUT_SOURCE_DVP 0
+#if defined(BL808)
+#define CAM_INPUT_SOURCE_CSI 1
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup CAM_BURST CAMERA burst length definition
+  * @{
+  */
+#define CAM_BURST_INCR1  0
+#define CAM_BURST_INCR4  1
+#define CAM_BURST_INCR8  2
+#define CAM_BURST_INCR16 3
+#if !defined(BL702)
+#define CAM_BURST_INCR32 5
+#define CAM_BURST_INCR64 6
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup CAM_CMD CAMERA feature control cmd definition
+  * @{
+  */
+#define CAM_CMD_SET_VSYNC_POLARITY 1
+#define CAM_CMD_SET_HSYNC_POLARITY 2
+#define CAM_CMD_SET_BURST          3
+#if !defined(BL702)
+#define CAM_CMD_SET_RGBA8888_ALPHA 4
+#define CAM_CMD_GET_FRAME_ID       5
+#endif
+#define CAM_CMD_WRAP_MODE                6
+#define CAM_CMD_COUNT_TRIGGER_NORMAL_INT 7
+#if !defined(BL702)
+#define CAM_CMD_FRAME_ID_RESET         8
+#define CAM_CMD_INVERSE_VSYNC_POLARITY 9
+#define CAM_CMD_INVERSE_HSYNC_POLARITY 10
+#endif
+
+/**
+  * @}
+  */
+
+/**
+ * @brief CAM configuration structure
+ *
+ * @param input_format   CAM input format, use @ref CAM_INPUT_FORMAT
+ * @param resolution_x   CAM resolution x
+ * @param resolution_y   CAM resolution y
+ * @param h_blank        CAM Hsync blank
+ * @param pixel_clock    CAM pixel clock
+ * @param with_mjpeg     CAM with mjpeg or not
+ * @param input_source   CAM input source, use @ref CAM_INPUT_SOURCE
+ * @param output_format  CAM output format, use @ref CAM_OUTPUT_FORMAT
+ * @param output_bufaddr CAM output buffer address , must be align 16
+ * @param output_bufsize CAM output buffer size, should not be less than one frame size
+ */
+struct bflb_cam_config_s {
+    uint8_t input_format;
+    uint16_t resolution_x;
+    uint16_t resolution_y;
+    uint16_t h_blank;
+    uint32_t pixel_clock;
+    bool with_mjpeg;
+    uint8_t input_source;
+    uint8_t output_format;
+    uint32_t output_bufaddr;
+    uint32_t output_bufsize;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize cam.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to cam configure structure
+ */
+void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config);
+
+/**
+ * @brief Enable cam.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cam_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable cam.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cam_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Mask or unmask cam interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type cam interrupt mask type, use @ref CAM_INTMASK
+ * @param [in] mask mask or unmask
+ */
+void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
+
+/**
+ * @brief Clear cam interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type int_type cam interrupt clear type, use @ref CAM_INTCLR
+ */
+void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type);
+
+/**
+ * @brief Crop vsync.
+ *
+ * @param [in] dev device handle
+ * @param [in] start_line start line of window
+ * @param [in] end_line end line of window, not include
+ */
+void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line);
+
+/**
+ * @brief Crop hsync.
+ *
+ * @param [in] dev device handle
+ * @param [in] start_pixel start pixel of each line
+ * @param [in] end_pixel end pixel of each line, not include
+ */
+void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel);
+
+/**
+ * @brief Pop one frame.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cam_pop_one_frame(struct bflb_device_s *dev);
+
+#if !defined(BL702)
+/**
+ * @brief Swap input order of y and uv.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Set frame filter, if frame_count = 3, frame_valid = 101b, second frame will be dropped every 3 frames.
+ *
+ * @param [in] dev device handle
+ * @param [in] frame_count frame filter period
+ * @param [in] frame_valid frame valid
+ */
+void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid);
+#endif
+
+/**
+ * @brief Get frame count.
+ *
+ * @param [in] dev device handle
+ * @return Frame count
+ */
+uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev);
+
+/**
+ * @brief Get frame information.
+ *
+ * @param [in] dev device handle
+ * @param [out] pic pointer to frame start address
+ * @return Size of frame
+ */
+uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
+
+/**
+ * @brief Get interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Interrupt status
+ */
+uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control cam feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure
+ */
+int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cks.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cks.h
new file mode 100755
index 0000000000..eb68b49e7e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_cks.h
@@ -0,0 +1,64 @@
+#ifndef _BFLB_CKS_H
+#define _BFLB_CKS_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup CKS
+  * @{
+  */
+
+/** @defgroup CKS_ENDIAN cks endian definition
+  * @{
+  */
+#define CKS_LITTLE_ENDIAN 0
+#define CKS_BIG_ENDIAN    1
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Reset checksum module.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_cks_reset(struct bflb_device_s *dev);
+
+/**
+ * @brief Set checksum bitorder.
+ *
+ * @param [in] dev device handle
+ * @param [in] endian cks endian, use @ref CKS_ENDIAN
+ */
+void bflb_cks_set_endian(struct bflb_device_s *dev, uint8_t endian);
+
+/**
+ * @brief Compute data with checksum.
+ *
+ * @param [in] dev device handle
+ * @param [in] data input data buffer
+ * @param [in] length data length
+ * @return checksum value
+ */
+uint16_t bflb_cks_compute(struct bflb_device_s *dev, uint8_t *data, uint32_t length);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_clock.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_clock.h
new file mode 100755
index 0000000000..30564c7623
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_clock.h
@@ -0,0 +1,246 @@
+#ifndef _BFLB_CLOCK_H
+#define _BFLB_CLOCK_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup CLOCK
+  * @{
+  */
+
+/** @defgroup BFLB_SYSTEM_CLOCK system clock definition
+  * @{
+  */
+#define BFLB_SYSTEM_ROOT_CLOCK 0
+#define BFLB_SYSTEM_CPU_CLK    1
+#define BFLB_SYSTEM_PBCLK      2
+#define BFLB_SYSTEM_XCLK       3
+#define BFLB_SYSTEM_32K_CLK    4
+/**
+  * @}
+  */
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define BFLB_GLB_CGEN1_BASE (0x40000000 + 0x24)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define BFLB_GLB_CGEN1_BASE (0x20000000 + 0x584)
+#define BFLB_GLB_CGEN2_BASE (0x20000000 + 0x588)
+#endif
+
+#define PERIPHERAL_CLOCK_ADC_DAC_ENABLE()                         \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 2);                                       \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#define PERIPHERAL_CLOCK_SEC_ENABLE()                             \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 4);                                       \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#define PERIPHERAL_CLOCK_DMA0_ENABLE()                            \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 12);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_DMA1_ENABLE()
+#define PERIPHERAL_CLOCK_DMA2_ENABLE()
+#endif
+
+#define PERIPHERAL_CLOCK_UART0_ENABLE()                           \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 16);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#define PERIPHERAL_CLOCK_UART1_ENABLE()                           \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 17);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_UART2_ENABLE()
+#endif
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_SPI0_1_ENABLE()                          \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 18);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+#else
+#define PERIPHERAL_CLOCK_SPI0_ENABLE()                            \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 18);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+#endif
+
+#define PERIPHERAL_CLOCK_I2C0_ENABLE()                            \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 19);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_I2C1_ENABLE()                            \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 25);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#endif
+
+#define PERIPHERAL_CLOCK_PWM0_ENABLE()                            \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 20);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#define PERIPHERAL_CLOCK_TIMER0_1_WDG_ENABLE()                    \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 21);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#define PERIPHERAL_CLOCK_IR_ENABLE()                              \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 22);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#if defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_CAN_UART2_ENABLE()                       \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 26);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+#elif defined(BL616) || defined(BL628)
+#define PERIPHERAL_CLOCK_CAN_ENABLE()                             \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 26);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+#endif
+
+#if defined(BL702)
+#define PERIPHERAL_CLOCK_USB_ENABLE()                             \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 28);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#define PERIPHERAL_CLOCK_I2S_ENABLE()                             \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 26);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#elif defined(BL616) || defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_USB_ENABLE()                             \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 13);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#define PERIPHERAL_CLOCK_I2S_ENABLE()                             \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 27);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+
+#endif
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define PERIPHERAL_CLOCK_SDH_ENABLE()                             \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
+        regval |= (1 << 22);                                      \
+        putreg32(regval, BFLB_GLB_CGEN2_BASE);                    \
+    } while (0)
+#endif
+
+#if defined(BL702)
+#define PERIPHERAL_CLOCK_EMAC_ENABLE()                            \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN1_BASE); \
+        regval |= (1 << 13);                                      \
+        putreg32(regval, BFLB_GLB_CGEN1_BASE);                    \
+    } while (0)
+#elif defined(BL616) || defined(BL606P) || defined(BL808)
+#define PERIPHERAL_CLOCK_EMAC_ENABLE()                            \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
+        regval |= (1 << 23);                                      \
+        putreg32(regval, BFLB_GLB_CGEN2_BASE);                    \
+    } while (0)
+#endif
+
+#if defined(BL616)
+#define PERIPHERAL_CLOCK_AUDIO_ENABLE()                           \
+    do {                                                          \
+        volatile uint32_t regval = getreg32(BFLB_GLB_CGEN2_BASE); \
+        regval |= (1 << 21);                                      \
+        putreg32(regval, BFLB_GLB_CGEN2_BASE);                    \
+    } while (0)
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get system clock frequence
+ *
+ * @param [in] type system clock type
+ * @return frequence
+ */
+uint32_t bflb_clk_get_system_clock(uint8_t type);
+
+/**
+ * @brief Get peripheral clock frequence
+ *
+ * @param [in] type peripheral type
+ * @param [in] idx peripheral index
+ * @return frequence
+ */
+uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_common.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_common.h
new file mode 100755
index 0000000000..7bd1441e09
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_common.h
@@ -0,0 +1,106 @@
+#ifndef _BFLB_COMMON_H
+#define _BFLB_COMMON_H
+
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dst
+ * @param [in] src
+ * @param [in] n
+ * @return void*
+ */
+void *arch_memcpy(void *dst, const void *src, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] s
+ * @param [in] c
+ * @param [in] n
+ * @return void*
+ */
+void *arch_memset(void *s, uint8_t c, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] s1
+ * @param [in] s2
+ * @param [in] n
+ * @return int
+ */
+int arch_memcmp(const void *s1, const void *s2, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] dst
+ * @param [in] src
+ * @param [in] n
+ * @return uint32_t*
+ */
+uint32_t *arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] pdst
+ * @param [in] psrc
+ * @param [in] n
+ * @return void*
+ */
+void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] dst
+ * @param [in] val
+ * @param [in] n
+ * @return uint32_t*
+ */
+uint32_t *arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n);
+
+/**
+ * @brief
+ *
+ * @param [in] cnt
+ */
+void arch_delay_us(uint32_t cnt);
+
+/**
+ * @brief
+ *
+ * @param [in] cnt
+ */
+void arch_delay_ms(uint32_t cnt);
+
+/**
+ * @brief
+ * 
+ * @param [in] in
+ * @param [in] len
+ * @return [in] uint16_t
+ */
+uint16_t bflb_soft_crc16(void *in, uint32_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] in
+ * @param [in] len
+ * @return [in] uint32_t
+ */
+uint32_t bflb_soft_crc32(void *in, uint32_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h
new file mode 100755
index 0000000000..7c7da5536b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_core.h
@@ -0,0 +1,143 @@
+#ifndef _BFLB_CORE_H
+#define _BFLB_CORE_H
+
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include 
+#include "bflb_list.h"
+#include "bflb_mtimer.h"
+#include "bflb_irq.h"
+#include "bflb_common.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup CORE
+  * @{
+  */
+
+#if !defined(BL602) && !defined(BL702) && !defined(BL702L) && \
+    !defined(BL616) && !defined(BL606P) && !defined(BL808) && !defined(BL628)
+#error please define a supported chip
+#endif
+
+#ifdef CONFIG_PARAM_ASSERT
+#define ASSERT_PARAM(expr) ((expr) ? (void)0 : assert_func(__FILE__, __LINE__, __FUNCTION__, #expr))
+void assert_func(uint8_t *file, uint32_t line, uint8_t *function, uint8_t *string);
+#else
+#define ASSERT_PARAM(expr) ((void)0U)
+#endif
+
+#if defined(BL702)
+#define BFLB_PSRAM_BASE 0x26000000
+#elif defined(BL616)
+#define BFLB_PSRAM_BASE 0xA8000000
+#elif defined(BL808)
+#define BFLB_PSRAM_BASE 0x50000000
+#elif defined(BL606P)
+#define BFLB_PSRAM_BASE 0x54000000
+#endif
+
+#define BFLB_DEVICE_TYPE_ADC      0
+#define BFLB_DEVICE_TYPE_DAC      1
+#define BFLB_DEVICE_TYPE_AUDIOADC 2
+#define BFLB_DEVICE_TYPE_AUDIODAC 3
+#define BFLB_DEVICE_TYPE_GPIO     4
+#define BFLB_DEVICE_TYPE_UART     5
+#define BFLB_DEVICE_TYPE_SPI      6
+#define BFLB_DEVICE_TYPE_I2C      7
+#define BFLB_DEVICE_TYPE_DMA      8
+#define BFLB_DEVICE_TYPE_I2S      9
+#define BFLB_DEVICE_TYPE_IR       10
+#define BFLB_DEVICE_TYPE_TIMER    11
+#define BFLB_DEVICE_TYPE_PWM      12
+#define BFLB_DEVICE_TYPE_ISO11898 13
+#define BFLB_DEVICE_TYPE_CAMERA   14
+#define BFLB_DEVICE_TYPE_FLASH    15
+#define BFLB_DEVICE_TYPE_QSPI     16
+#define BFLB_DEVICE_TYPE_SDH      17
+#define BFLB_DEVICE_TYPE_SDU      18
+#define BFLB_DEVICE_TYPE_ETH      19
+#define BFLB_DEVICE_TYPE_RTC      20
+#define BFLB_DEVICE_TYPE_CRC      21
+#define BFLB_DEVICE_TYPE_RNG      22
+#define BFLB_DEVICE_TYPE_MIPI     23
+#define BFLB_DEVICE_TYPE_DPI      24
+#define BFLB_DEVICE_TYPE_DSI      25
+#define BFLB_DEVICE_TYPE_CSI      26
+#define BFLB_DEVICE_TYPE_USB      27
+#define BFLB_DEVICE_TYPE_AES      28
+#define BFLB_DEVICE_TYPE_SHA      29
+#define BFLB_DEVICE_TYPE_MD5      30
+#define BFLB_DEVICE_TYPE_TRNG     31
+#define BFLB_DEVICE_TYPE_PKA      32
+#define BFLB_DEVICE_TYPE_CKS      33
+#define BFLB_DEVICE_TYPE_MJPEG    34
+#define BFLB_DEVICE_TYPE_KYS      35
+#define BFLB_DEVICE_TYPE_DBI      36
+#define BFLB_DEVICE_TYPE_PEC      37
+#define BFLB_DEVICE_TYPE_WDT      38
+#define BFLB_DEVICE_TYPE_EF_CTRL  39
+#define BFLB_DEVICE_TYPE_SDIO3    40
+#define BFLB_DEVICE_TYPE_SDIO2    41
+
+struct bflb_device_s {
+    const char *name;
+    uint32_t reg_base;
+    uint8_t irq_num;
+    uint8_t idx;
+    uint8_t sub_idx;
+    uint8_t dev_type;
+    void *user_data;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Get device handle by name.
+ *
+ * @param [in] name device name
+ * @return device handle
+ */
+struct bflb_device_s *bflb_device_get_by_name(const char *name);
+
+/**
+ * @brief Get device handle by type and index.
+ *
+ * @param [in] type device type
+ * @param [in] idx device index
+ * @return device handle
+ */
+struct bflb_device_s *bflb_device_get_by_id(uint8_t type, uint8_t idx);
+
+/**
+ * @brief Set user data into device handle.
+ *
+ * @param [in] device device handle
+ * @param [in] user_data pointer to user data
+ */
+void bflb_device_set_userdata(struct bflb_device_s *device, void *user_data);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_csi.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_csi.h
new file mode 100755
index 0000000000..d430a4e381
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_csi.h
@@ -0,0 +1,158 @@
+#ifndef _BFLB_CSI_H
+#define _BFLB_CSI_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup CSI
+  * @{
+  */
+
+/** @defgroup CSI_LANE_NUMBER CSI lane number definition
+  * @{
+  */
+#define CSI_LANE_NUMBER_1 0
+#define CSI_LANE_NUMBER_2 1
+/**
+  * @}
+  */
+
+/** @defgroup CSI_INTSTS CSI interrupt status definition
+  * @{
+  */
+#define CSI_INTSTS_GENERIC_PACKET        (1 << 0)
+#define CSI_INTSTS_LANE_MERGE_ERROR      (1 << 1)
+#define CSI_INTSTS_ECC_ERROR             (1 << 2)
+#define CSI_INTSTS_CRC_ERROR             (1 << 3)
+#define CSI_INTSTS_PHY_HS_SOT_ERROR      (1 << 4)
+#define CSI_INTSTS_PHY_HS_SOT_SYNC_ERROR (1 << 5)
+/**
+  * @}
+  */
+
+/** @defgroup CSI_INTMASK CSI interrupt mask definition
+  * @{
+  */
+#define CSI_INTMASK_GENERIC_PACKET        (1 << 0)
+#define CSI_INTMASK_LANE_MERGE_ERROR      (1 << 1)
+#define CSI_INTMASK_ECC_ERROR             (1 << 2)
+#define CSI_INTMASK_CRC_ERROR             (1 << 3)
+#define CSI_INTMASK_PHY_HS_SOT_ERROR      (1 << 4)
+#define CSI_INTMASK_PHY_HS_SOT_SYNC_ERROR (1 << 5)
+/**
+  * @}
+  */
+
+/** @defgroup CSI_INTCLR CSI interrupt clear definition
+  * @{
+  */
+#define CSI_INTCLR_GENERIC_PACKET        (1 << 0)
+#define CSI_INTCLR_LANE_MERGE_ERROR      (1 << 1)
+#define CSI_INTCLR_ECC_ERROR             (1 << 2)
+#define CSI_INTCLR_CRC_ERROR             (1 << 3)
+#define CSI_INTCLR_PHY_HS_SOT_ERROR      (1 << 4)
+#define CSI_INTCLR_PHY_HS_SOT_SYNC_ERROR (1 << 5)
+/**
+  * @}
+  */
+
+/**
+ * @brief CSI configuration structure
+ *
+ * @param lane_number   CSI lane number, use @ref CSI_LANE_NUMBER
+ * @param tx_clk_escape CSI tx clock in escape mode
+ * @param data_rate     CSI data rate
+ */
+struct bflb_csi_config_s {
+    uint8_t lane_number;
+    uint32_t tx_clk_escape;
+    uint32_t data_rate;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize csi.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to csi configure structure
+ */
+void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config);
+
+/**
+ * @brief Enable csi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_csi_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Disable csi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_csi_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Set threshold of line buffer, data will be sent to following module when threshold reached.
+ *
+ * @param [in] dev device handle
+ * @param [in] resolution_x number of columns
+ * @param [in] pixel_clock pixel clock
+ * @param [in] dsp_clock dsp clock
+ */
+void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock);
+
+/**
+ * @brief Mask or unmask csi interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type csi interrupt mask type, use @ref CSI_INTMASK
+ * @param [in] mask mask or unmask
+ */
+void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
+
+/**
+ * @brief Clear csi interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type csi interrupt clear type, use @ref CSI_INTCLR
+ */
+void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type);
+
+/**
+ * @brief Get csi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Interrupt status
+ */
+uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control csi feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure
+ */
+int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dac.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dac.h
new file mode 100755
index 0000000000..39892a5120
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dac.h
@@ -0,0 +1,98 @@
+#ifndef _BFLB_DAC_H
+#define _BFLB_DAC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/** @defgroup DAC_CLK_DIV dac clock div definition
+  * @{
+  */
+#define DAC_CLK_DIV_16 0
+#define DAC_CLK_DIV_32 1
+#define DAC_CLK_DIV_64 3
+#define DAC_CLK_DIV_1  4
+/**
+  * @}
+  */
+
+/** @defgroup DAC_CHANNEL dac channel select
+  * @{
+  */
+#define DAC_CHANNEL_A (1 << 0)
+#define DAC_CHANNEL_B (1 << 1)
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize dac frequence.
+ *
+ * @param [in] dev device handle
+ * @param [in] frequence dac clock div, use @ref DAC_CLK_DIV
+ */
+void bflb_dac_init(struct bflb_device_s *dev, uint8_t clk_div);
+
+/**
+ * @brief Deinitialize dac.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dac_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable dac tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_dac_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable dac channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_dac_channel_enable(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Disable dac channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_dac_channel_disable(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Set dac output value
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] value output value
+ */
+void bflb_dac_set_value(struct bflb_device_s *dev, uint8_t ch, uint16_t value);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dbi.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dbi.h
new file mode 100755
index 0000000000..5c40688c0e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dbi.h
@@ -0,0 +1,295 @@
+#ifndef _BFLB_DBI_H
+#define _BFLB_DBI_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup DBI
+  * @{
+  */
+
+#if defined(BL616)
+#define DBI_QSPI_SUPPORT        1
+#define DBI_YUV_SUPPORT         1
+#define DBI_WRITE_DATA_BYTE_MAX 256
+#define DBI_READ_DATA_BYTE_MAX  8
+#define SPI_FIFO_NUM_MAX        8
+#elif defined(BL606P) || defined(BL808)
+#define DBI_QSPI_SUPPORT        0
+#define DBI_YUV_SUPPORT         0
+#define DBI_WRITE_DATA_BYTE_MAX 4
+#define DBI_READ_DATA_BYTE_MAX  4
+#define SPI_FIFO_NUM_MAX        8
+#else
+#error "unknown device"
+#endif
+
+#define DBI_WRITE_PIXEL_CNT_MAX 0x00FFFFFF
+
+/** @defgroup DBI_MODE dbi working mode definition
+  * @{
+  */
+#define DBI_MODE_TYPE_B         0 /* mipi-dbi typeB 8-wire-data mode */
+#define DBI_MODE_TYPE_C_4_WIRE  1 /* mipi-dbi typeC 4-wire mode */
+#define DBI_MODE_TYPE_C_3_WIRE  2 /* mipi-dbi typeC 3-wire mode */
+#if (DBI_QSPI_SUPPORT)
+#define DBI_MODE_EX_QSPI 3 /* Not the mipi standard. Extra support for QSPI mode */
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup DBI_PIXEL_INPUT_FORMAT dbi fifo input pixel format, the FIFO are filled in 32-bits width definition
+  * @{
+  */
+#define DBI_PIXEL_INPUT_FORMAT_NBGR_8888 0 /* 32-bit/pixel, memory byte: [0]->pixel[0][R], [1]->pixel[0][G], [2]->pixel[0][B], [3]->invalid, [4]->pixel[1][R], ... */
+#define DBI_PIXEL_INPUT_FORMAT_NRGB_8888 1 /* 32-bit/pixel, memory byte: [0]->pixel[0][B], [1]->pixel[0][G], [2]->pixel[0][R], [3]->invalid, [4]->pixel[1][B], ... */
+#define DBI_PIXEL_INPUT_FORMAT_BGRN_8888 2 /* 32-bit/pixel, memory byte: [0]->invalid, [1]->pixel[0][R], [2]->pixel[0][G], [3]->pixel[0][B], [4]->invalid, [5]->pixel[1][R], ... */
+#define DBI_PIXEL_INPUT_FORMAT_RGBN_8888 3 /* 32-bit/pixel, memory byte: [0]->invalid, [1]->pixel[0][B], [2]->pixel[0][G], [3]->pixel[0][R], [4]->invalid, [5]->pixel[1][B], ... */
+#define DBI_PIXEL_INPUT_FORMAT_RGB_888   4 /* 24-bit/pixel, memory byte: [0]->pixel[0][R], [1]->pixel[0][G], [2]->pixel[0][B], [3]->pixel[1][R], [4]->pixel[1][G], ... */
+#define DBI_PIXEL_INPUT_FORMAT_BGR_888   5 /* 24-bit/pixel, memory byte: [0]->pixel[0][B], [1]->pixel[0][G], [2]->pixel[0][R], [3]->pixel[1][B], [4]->pixel[1][G], ... */
+#define DBI_PIXEL_INPUT_FORMAT_BGR_565   6 /* 16-bit/pixel, */
+#define DBI_PIXEL_INPUT_FORMAT_RGB_565   7 /* 16-bit/pixel, */
+/**
+  * @}
+  */
+
+/** @defgroup DBI_PIXEL_OUTPUT_FORMAT dbi output pixel format definition
+  * @{
+  */
+#define DBI_PIXEL_OUTPUT_FORMAT_RGB_565  0 /* 16-bit/pixel */
+#define DBI_PIXEL_OUTPUT_FORMAT_RGB_888  1 /* 24-bit/pixel, Compatible with RGB666 format */
+/**
+  * @}
+  */
+
+/** @defgroup DBI_CLOCK_MODE dbi clock phase and polarity definition
+  * @{
+  */
+#define DBI_CLOCK_MODE_0                 0 /* CPOL=0 CHPHA=0 */
+#define DBI_CLOCK_MODE_1                 1 /* CPOL=0 CHPHA=1 */
+#define DBI_CLOCK_MODE_2                 2 /* CPOL=1 CHPHA=0 */
+#define DBI_CLOCK_MODE_3                 3 /* CPOL=1 CHPHA=1 */
+/**
+  * @}
+  */
+
+/** @defgroup DBI_QSPI_WIRE_NUM dbi qspi wire num definition
+  * @{
+  */
+#define DBI_QSPI_WIRE_NUM_1              0 /* 1-wire mode */
+#define DBI_QSPI_WIRE_NUM_4              1 /* 4-wire mode */
+/**
+  * @}
+  */
+
+/** @defgroup SPI_INTSTS dbi interrupt status definition
+  * @{
+  */
+#define DBI_INTSTS_TC                    (1 << 0)
+#define SPI_INTSTS_TX_FIFO               (1 << 1)
+#define SPI_INTSTS_FIFO_ERR              (1 << 2)
+/**
+  * @}
+  */
+
+/** @defgroup DBI_INTCLR dbi interrupt clear definition
+  * @{
+  */
+#define DBI_INTCLR_TC                    (1 << 0)
+/**
+  * @}
+  */
+
+/** @defgroup DBI_CMD dbi feature control cmd definition
+  * @{
+  */
+#define DBI_CMD_CLEAR_TX_FIFO            (0x01)
+#define DBI_CMD_GET_TX_FIFO_CNT          (0x02)
+#define DBI_CMD_MASK_CMD_PHASE           (0x03)
+#define DBI_CMD_CS_CONTINUE              (0x04)
+#define DBI_CMD_SET_DUMMY_CNT            (0x05)
+#define DBI_CMD_GET_SIZE_OF_PIXEL_CNT    (0x06)
+#define DBI_CMD_INPUT_PIXEL_FORMAT       (0x07)
+#define DBI_CMD_OUTPUT_PIXEL_FORMAT      (0x08)
+#if (DBI_QSPI_SUPPORT)
+#define DBI_CMD_YUV_TO_RGB_ENABLE (0x10)
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+ * @brief DBI configuration structure
+ *
+ * @param dbi_mode              DBI working mode, use @ref DBI_MODE
+ * @param pixel_input_format    DBI input pixel_format, use @ref DBI_PIXEL_INPUT_FORMAT
+ * @param pixel_output_format   DBI output pixel_format, use @ref DBI_PIXEL_OUTPUT_FORMAT
+ * @param clk_mode              DBI clock phase and polarity, use @ref DBI_CLOCK_MODE
+ * @param clk_freq_hz           DBI clock frequency
+ * @param tx_fifo_threshold     DBI tx fifo threshold, should be less than 16
+ * @param cmd_wire_mode         DBI qspi mode, number of wire in the command phase, use @ref DBI_QSPI_WIRE_NUM
+ * @param addr_wire_mode        DBI qspi mode, number of wire in the address phase, use @ref DBI_QSPI_WIRE_NUM
+ * @param data_wire_mode        DBI qspi mode, number of wire in the data phase, use @ref DBI_QSPI_WIRE_NUM
+ */
+struct bflb_dbi_config_s {
+    uint8_t dbi_mode;
+    uint8_t pixel_input_format;
+    uint8_t pixel_output_format;
+    uint8_t clk_mode;
+    uint32_t clk_freq_hz;
+    uint8_t tx_fifo_threshold;
+#if (DBI_QSPI_SUPPORT)
+    uint8_t cmd_wire_mode;
+    uint8_t addr_wire_mode;
+    uint8_t data_wire_mode;
+#endif
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize dbi.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save dbi config
+ */
+void bflb_dbi_init(struct bflb_device_s *dev, const struct bflb_dbi_config_s *config);
+
+/**
+ * @brief Deinitialize dbi.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dbi_deinit(struct bflb_device_s *dev);
+
+#if DBI_QSPI_SUPPORT
+/**
+ * @brief Set the address value and address length of the QSPI
+ *
+ * @param [in] dev device handle
+ * @param [in] addr_byte_size address size(byte), range 1 ~ 4
+ * @param [in] addr_val address value: [0:7]->addr[0], [8:15]->addr[1], [16:23]->addr[2], [24:31]->addr[3].
+ */
+void bflb_dbi_qspi_set_addr(struct bflb_device_s *dev, uint8_t addr_byte_size, uint32_t addr_val);
+
+#endif
+
+/**
+ * @brief Send cmd with pixel data, send cmd -> send address(only QSPI mode) -> send parameter_data.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd command
+ * @param [in] data_len Parameter length (byte), The maximum is DBI_WRITE_DATA_BYTE_MAX
+ * @param [in] data_buff Parameter buffer, Cannot be null
+ * @return
+ */
+int bflb_dbi_send_cmd_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff);
+
+/**
+ * @brief To read the data after sending the command, send cmd -> send address(only QSPI mode) -> read parameter_data.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd command
+ * @param [in] data_len Length of data to be read (byte), The maximum is DBI_READ_DATA_BYTE_MAX
+ * @param [in] data_buff Buff of data to be read, discard data if null
+ * @return
+ */
+int bflb_dbi_send_cmd_read_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff);
+
+/**
+ * @brief Send cmd with pixel data, send cmd -> send address(only QSPI mode) -> send pixel_data,
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd command
+ * @param [in] pixel_cnt Number of pixels,The maximum is DBI_WRITE_PIXEL_CNT_MAX
+ * @param [in] pixel_buff Pixels buffer, NULL when using DMA, in which case data needs to be transferred by DMA later, and wait for the transfer to complete
+ * @return
+ */
+int bflb_dbi_send_cmd_pixel(struct bflb_device_s *dev, uint8_t cmd, uint32_t pixel_cnt, void *pixel_buff);
+
+/**
+ * @brief Enable dbi tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_dbi_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable or disable dbi rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dbi_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable dbi transfer completion interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dbi_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable dbi error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dbi_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get dbi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref DBI_INTSTS
+ */
+uint32_t bflb_dbi_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear dbi interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref SPI_INTCLR
+ */
+void bflb_dbi_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Control dbi feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref DBI_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_dbi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h
new file mode 100755
index 0000000000..fb7aeed185
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_dma.h
@@ -0,0 +1,506 @@
+#ifndef _BFLB_DMA_H
+#define _BFLB_DMA_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/** @defgroup DMA_DIRECTION dma transfer direction definition
+  * @{
+  */
+#define DMA_MEMORY_TO_MEMORY       0
+#define DMA_MEMORY_TO_PERIPH       1
+#define DMA_PERIPH_TO_MEMORY       2
+#define DMA_PERIPH_TO_PERIPH       3
+/**
+  * @}
+  */
+
+/** @defgroup DMA_ADDR_INCREMENT dma source and destination address increment definition
+  * @{
+  */
+#define DMA_ADDR_INCREMENT_DISABLE 0
+#define DMA_ADDR_INCREMENT_ENABLE  1
+/**
+  * @}
+  */
+
+/** @defgroup DMA_DATA_WIDTH dma data width definition
+  * @{
+  */
+#define DMA_DATA_WIDTH_8BIT        0
+#define DMA_DATA_WIDTH_16BIT       1
+#define DMA_DATA_WIDTH_32BIT       2
+/**
+  * @}
+  */
+
+/** @defgroup DMA_BURST_COUNT dma burst increment count definition
+  * @{
+  */
+#define DMA_BURST_INCR1            0
+#define DMA_BURST_INCR4            1
+#define DMA_BURST_INCR8            2
+#define DMA_BURST_INCR16           3
+/**
+  * @}
+  */
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+  * @{
+  */
+#define DMA_ADDR_UART0_TDR (0x4000A000 + 0x88)
+#define DMA_ADDR_UART0_RDR (0x4000A000 + 0x8C)
+#if !defined(BL702L)
+#define DMA_ADDR_UART1_TDR (0x4000A100 + 0x88)
+#define DMA_ADDR_UART1_RDR (0x4000A100 + 0x8C)
+#endif
+#define DMA_ADDR_I2C0_TDR (0x4000A300 + 0x88)
+#define DMA_ADDR_I2C0_RDR (0x4000A300 + 0x8C)
+#define DMA_ADDR_SPI0_TDR (0x4000A200 + 0x88)
+#define DMA_ADDR_SPI0_RDR (0x4000A200 + 0x8C)
+#if !defined(BL702L)
+#define DMA_ADDR_I2S_TDR (0x4000AA00 + 0x88)
+#define DMA_ADDR_I2S_RDR (0x4000AA00 + 0x8C)
+#endif
+#define DMA_ADDR_ADC_RDR (0x40002000 + 0x04)
+#if !defined(BL702L)
+#define DMA_ADDR_DAC_TDR (0x40002000 + 0x48)
+#endif
+#if defined(BL702L)
+#define DMA_ADDR_IR_TDR    (0x4000A600 + 0x88)
+#define DMA_ADDR_AUADC_RDR (0x4000AD00 + 0x88)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+  * @{
+  */
+#define DMA_REQUEST_NONE     0x00000000
+#define DMA_REQUEST_UART0_RX 0x00000000
+#define DMA_REQUEST_UART0_TX 0x00000001
+#if !defined(BL702L)
+#define DMA_REQUEST_UART1_RX 0x00000002
+#define DMA_REQUEST_UART1_TX 0x00000003
+#endif
+#define DMA_REQUEST_I2C0_RX 0x00000006
+#define DMA_REQUEST_I2C0_TX 0x00000007
+#if defined(BL702L)
+#define DMA_REQUEST_IR_TX 0x00000008
+#endif
+#define DMA_REQUEST_SPI0_RX 0x0000000A
+#define DMA_REQUEST_SPI0_TX 0x0000000B
+#if defined(BL702L)
+#define DMA_REQUEST_AUADC_RX 0x0000000D
+#endif
+#if !defined(BL702L)
+#define DMA_REQUEST_I2S_RX 0x00000014
+#define DMA_REQUEST_I2S_TX 0x00000015
+#endif
+#define DMA_REQUEST_ADC 0x00000016
+#if !defined(BL702L)
+#define DMA_REQUEST_DAC 0x00000017
+#endif
+/**
+  * @}
+  */
+
+#elif defined(BL616)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+  * @{
+  */
+#define DMA_ADDR_UART0_TDR      (0x2000A000 + 0x88)
+#define DMA_ADDR_UART0_RDR      (0x2000A000 + 0x8C)
+#define DMA_ADDR_UART1_TDR      (0x2000A100 + 0x88)
+#define DMA_ADDR_UART1_RDR      (0x2000A100 + 0x8C)
+#define DMA_ADDR_I2C0_TDR       (0x2000A300 + 0x88)
+#define DMA_ADDR_I2C0_RDR       (0x2000A300 + 0x8C)
+#define DMA_ADDR_SPI0_TDR       (0x2000A200 + 0x88)
+#define DMA_ADDR_SPI0_RDR       (0x2000A200 + 0x8C)
+#define DMA_ADDR_I2S_TDR        (0x2000AB00 + 0x88)
+#define DMA_ADDR_I2S_RDR        (0x2000AB00 + 0x8C)
+#define DMA_ADDR_ADC_RDR        (0x20002000 + 0x04)
+#define DMA_ADDR_DAC_TDR        (0x20002000 + 0x48)
+#define DMA_ADDR_DBI_TDR        (0x2000A800 + 0x88)
+#define DMA_ADDR_AUDAC_TDR      (0x20055000 + 0x94)
+#define DMA_ADDR_AUADC_RDR      (0x2000A000 + 0xC88)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+  * @{
+  */
+#define DMA_REQUEST_NONE        0x00000000
+#define DMA_REQUEST_UART0_RX    0x00000000
+#define DMA_REQUEST_UART0_TX    0x00000001
+#define DMA_REQUEST_UART1_RX    0x00000002
+#define DMA_REQUEST_UART1_TX    0x00000003
+#define DMA_REQUEST_I2C0_RX     0x00000006
+#define DMA_REQUEST_I2C0_TX     0x00000007
+#define DMA_REQUEST_SPI0_RX     0x0000000A
+#define DMA_REQUEST_SPI0_TX     0x0000000B
+#define DMA_REQUEST_DBI_TX      0x00000014
+#define DMA_REQUEST_AUADC_RX    0x00000015
+#define DMA_REQUEST_AUDAC_TX    0x0000000D
+#define DMA_REQUEST_I2S_RX      0x00000010
+#define DMA_REQUEST_I2S_TX      0x00000011
+#define DMA_REQUEST_ADC         0x00000016
+#define DMA_REQUEST_DAC         0x00000017
+#define DMA_REQUEST_PEC0_SM0_RX 0x00000018
+#define DMA_REQUEST_PEC0_SM1_RX 0x00000019
+#define DMA_REQUEST_PEC0_SM2_RX 0x0000001A
+#define DMA_REQUEST_PEC0_SM3_RX 0x0000001B
+#define DMA_REQUEST_PEC0_SM0_TX 0x0000001C
+#define DMA_REQUEST_PEC0_SM1_TX 0x0000001D
+#define DMA_REQUEST_PEC0_SM2_TX 0x0000001E
+#define DMA_REQUEST_PEC0_SM3_TX 0x0000001F
+
+/**
+  * @}
+  */
+
+#elif defined(BL808) || defined(BL606P)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+  * @{
+  */
+#define DMA_ADDR_UART0_TDR   (0x2000A000 + 0x88)
+#define DMA_ADDR_UART0_RDR   (0x2000A000 + 0x8C)
+#define DMA_ADDR_UART1_TDR   (0x2000A100 + 0x88)
+#define DMA_ADDR_UART1_RDR   (0x2000A100 + 0x8C)
+#define DMA_ADDR_UART2_TDR   (0x2000AA00 + 0x88)
+#define DMA_ADDR_UART2_RDR   (0x2000AA00 + 0x8C)
+#define DMA_ADDR_UART3_TDR   (0x30002000 + 0x88)
+#define DMA_ADDR_UART3_RDR   (0x30002000 + 0x8C)
+#define DMA_ADDR_I2C0_TDR    (0x2000A300 + 0x88)
+#define DMA_ADDR_I2C0_RDR    (0x2000A300 + 0x8C)
+#define DMA_ADDR_I2C1_TDR    (0x2000A900 + 0x88)
+#define DMA_ADDR_I2C1_RDR    (0x2000A900 + 0x8C)
+#define DMA_ADDR_I2C2_TDR    (0x30003000 + 0x88)
+#define DMA_ADDR_I2C2_RDR    (0x30003000 + 0x8C)
+#define DMA_ADDR_I2C3_TDR    (0x30004000 + 0x88)
+#define DMA_ADDR_I2C3_RDR    (0x30004000 + 0x8C)
+#define DMA_ADDR_SPI0_TDR    (0x2000A200 + 0x88)
+#define DMA_ADDR_SPI0_RDR    (0x2000A200 + 0x8C)
+#define DMA_ADDR_SPI1_TDR    (0x30008000 + 0x88)
+#define DMA_ADDR_SPI1_RDR    (0x30008000 + 0x8C)
+#define DMA_ADDR_I2S_TDR     (0x2000AB00 + 0x88)
+#define DMA_ADDR_I2S_RDR     (0x2000AB00 + 0x8C)
+#define DMA_ADDR_ADC_RDR     (0x20002000 + 0x04)
+#define DMA_ADDR_DAC_TDR     (0x20002000 + 0x48)
+#define DMA_ADDR_IR_TDR      (0x2000A600 + 0x88)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+  * @{
+  */
+#define DMA_REQUEST_NONE     0x00000000
+#define DMA_REQUEST_UART0_RX 0x00000000
+#define DMA_REQUEST_UART0_TX 0x00000001
+#define DMA_REQUEST_UART1_RX 0x00000002
+#define DMA_REQUEST_UART1_TX 0x00000003
+#define DMA_REQUEST_UART2_RX 0x00000004
+#define DMA_REQUEST_UART2_TX 0x00000005
+#define DMA_REQUEST_I2C0_RX  0x00000006
+#define DMA_REQUEST_I2C0_TX  0x00000007
+#define DMA_REQUEST_IR_TX    0x00000008
+#define DMA_REQUEST_SPI0_RX  0x0000000A
+#define DMA_REQUEST_SPI0_TX  0x0000000B
+#define DMA_REQUEST_AUDIO_RX 0x0000000C
+#define DMA_REQUEST_AUDIO_TX 0x0000000D
+#define DMA_REQUEST_I2C1_RX  0x0000000E
+#define DMA_REQUEST_I2C1_TX  0x0000000F
+#define DMA_REQUEST_I2S_RX   0x00000010
+#define DMA_REQUEST_I2S_TX   0x00000011
+#define DMA_REQUEST_ADC      0x00000016
+#define DMA_REQUEST_DAC      0x00000017
+
+/* Only support dma2 */
+#define DMA_REQUEST_UART3_RX 0x00000000
+#define DMA_REQUEST_UART3_TX 0x00000001
+#define DMA_REQUEST_SPI1_RX  0x00000002
+#define DMA_REQUEST_SPI1_TX  0x00000003
+#define DMA_REQUEST_I2C2_RX  0x00000006
+#define DMA_REQUEST_I2C2_TX  0x00000007
+#define DMA_REQUEST_I2C3_RX  0x00000008
+#define DMA_REQUEST_I2C3_TX  0x00000009
+/**
+  * @}
+  */
+
+#elif defined(BL628)
+/** @defgroup DMA_PERIPHERAL_REGBASE dma peripheral data register address definition
+  * @{
+  */
+#define DMA_ADDR_UART0_TDR   (0x20010000 + 0x88)
+#define DMA_ADDR_UART0_RDR   (0x20010000 + 0x8C)
+#define DMA_ADDR_UART1_TDR   (0x20011000 + 0x88)
+#define DMA_ADDR_UART1_RDR   (0x20011000 + 0x8C)
+#define DMA_ADDR_UART2_TDR   (0x20012000 + 0x88)
+#define DMA_ADDR_UART2_RDR   (0x20012000 + 0x8C)
+#define DMA_ADDR_I2C0_TDR    (0x20014000 + 0x88)
+#define DMA_ADDR_I2C0_RDR    (0x20014000 + 0x8C)
+#define DMA_ADDR_I2C1_TDR    (0x20015000 + 0x88)
+#define DMA_ADDR_I2C1_RDR    (0x20015000 + 0x8C)
+#define DMA_ADDR_SPI0_TDR    (0x20018000 + 0x88)
+#define DMA_ADDR_SPI0_RDR    (0x20018000 + 0x8C)
+#define DMA_ADDR_I2S_TDR     (0x2001E000 + 0x88)
+#define DMA_ADDR_I2S_RDR     (0x2001E000 + 0x8C)
+#define DMA_ADDR_ADC_RDR     (0x20002000 + 0x04)
+#define DMA_ADDR_DAC_TDR     (0x20002000 + 0x48)
+/**
+  * @}
+  */
+
+/** @defgroup DMA_PERIPHERAL_REQUEST dma peripheral request definition
+  * @{
+  */
+#define DMA_REQUEST_NONE     0x00000000
+#define DMA_REQUEST_UART0_RX 0x00000000
+#define DMA_REQUEST_UART0_TX 0x00000001
+#define DMA_REQUEST_UART1_RX 0x00000002
+#define DMA_REQUEST_UART1_TX 0x00000003
+#define DMA_REQUEST_UART2_RX 0x00000004
+#define DMA_REQUEST_UART2_TX 0x00000005
+#define DMA_REQUEST_I2C0_RX  0x00000006
+#define DMA_REQUEST_I2C0_TX  0x00000007
+#define DMA_REQUEST_I2C1_RX  0x00000008
+#define DMA_REQUEST_I2C1_TX  0x00000009
+#define DMA_REQUEST_SPI0_RX  0x0000000A
+#define DMA_REQUEST_SPI0_TX  0x0000000B
+#define DMA_REQUEST_I2S_RX   0x00000010
+#define DMA_REQUEST_I2S_TX   0x00000011
+#define DMA_REQUEST_ADC      0x00000016
+#define DMA_REQUEST_DAC      0x00000017
+/**
+  * @}
+  */
+
+#endif
+
+/** @defgroup DMA_CMD dma feature control cmd definition
+  * @{
+  */
+#define DMA_CMD_SET_SRCADDR_INCREMENT (0x01)
+#define DMA_CMD_SET_DSTADDR_INCREMENT (0x02)
+#define DMA_CMD_SET_ADD_MODE          (0x03)
+#define DMA_CMD_SET_REDUCE_MODE       (0x04)
+#define DMA_CMD_SET_LLI_CONFIG        (0x05)
+#define DMA_CMD_GET_LLI_CONTROL       (0x06)
+/**
+  * @}
+  */
+
+union bflb_dma_lli_control_s {
+    struct
+    {
+        uint32_t TransferSize : 12; /* [11: 0],        r/w,        0x0 */
+        uint32_t SBSize       : 2;  /* [13:12],        r/w,        0x1 */
+        uint32_t dst_min_mode : 1;  /* [   14],        r/w,        0x0 */
+        uint32_t DBSize       : 2;  /* [16:15],        r/w,        0x1 */
+        uint32_t dst_add_mode : 1;  /* [   17],        r/w,        0x0 */
+        uint32_t SWidth       : 2;  /* [19:18],        r/w,        0x2 */
+        uint32_t reserved_20  : 1;  /* [   20],       rsvd,        0x0 */
+        uint32_t DWidth       : 2;  /* [22:21],        r/w,        0x2 */
+        uint32_t fix_cnt      : 2;  /* [24:23],        r/w,        0x0 */
+        uint32_t SLargerD     : 1;  /* [   25],        r/w,        0x0 */
+        uint32_t SI           : 1;  /* [   26],        r/w,        0x1 */
+        uint32_t DI           : 1;  /* [   27],        r/w,        0x1 */
+        uint32_t Prot         : 3;  /* [30:28],        r/w,        0x0 */
+        uint32_t I            : 1;  /* [   31],        r/w,        0x0 */
+    } bits;
+    uint32_t WORD;
+};
+
+/**
+ * @brief DMA channel lli pool structure
+ *
+ * @param src_addr        DMA source address
+ * @param dst_addr        DMA destination address
+ * @param nextlli         DMA next lli address
+ * @param control         DMA lli config
+ */
+struct bflb_dma_channel_lli_pool_s {
+    uint32_t src_addr;
+    uint32_t dst_addr;
+    uint32_t nextlli;
+    union bflb_dma_lli_control_s control;
+};
+
+/**
+ * @brief DMA channel lli transfer structure
+ *
+ * @param src_addr        DMA source address
+ * @param dst_addr        DMA destination address
+ * @param nbytes          How many bytes should be transferred
+ */
+struct bflb_dma_channel_lli_transfer_s {
+    uint32_t src_addr;
+    uint32_t dst_addr;
+    uint32_t nbytes;
+};
+
+/**
+ * @brief DMA configuration structure
+ *
+ * @param direction        DMA transfer direction, use @ref DMA_DIRECTION
+ * @param src_req          DMA source request, use @ref DMA_PERIPHERAL_REQUEST
+ * @param dst_req          DMA destination request, use @ref DMA_PERIPHERAL_REQUEST
+ * @param src_addr_inc     DMA source address increment, use @ref DMA_ADDR_INCREMENT
+ * @param dst_addr_inc     DMA destination address increment, use @ref DMA_ADDR_INCREMENT
+ * @param src_burst_count  DMA source burst count, use @ref DMA_BURST_COUNT
+ * @param dst_burst_count  DMA destination burst count, use @ref DMA_BURST_COUNT
+ * @param src_width        DMA source data width, use @ref DMA_DATA_WIDTH
+ * @param dst_width        DMA destination data width, use @ref DMA_DATA_WIDTH
+ */
+struct bflb_dma_channel_config_s {
+    uint8_t direction;
+    uint32_t src_req;
+    uint32_t dst_req;
+    uint8_t src_addr_inc;
+    uint8_t dst_addr_inc;
+    uint8_t src_burst_count;
+    uint8_t dst_burst_count;
+    uint8_t src_width;
+    uint8_t dst_width;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize dma channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save dma channel configuration
+ */
+void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_channel_config_s *config);
+
+/**
+ * @brief Deinitialize dma channel.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Start dma channel transfer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop dma channel transfer.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Check if dma channel is in busy.
+ *
+ * @param [in] dev device handle
+ * @return true means dma channel does not transfer completely, otherwise transfers completely.
+ */
+bool bflb_dma_channel_isbusy(struct bflb_device_s *dev);
+
+/**
+ * @brief Register dma channel transmission completion interrupt callback.
+ *
+ * @param [in] dev device handle
+ * @param [in] callback interrupt callback
+ * @param [in] arg user data
+ */
+void bflb_dma_channel_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg), void *arg);
+
+/**
+ * @brief Unregister dma channel transmission completion interrupt callback.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_irq_detach(struct bflb_device_s *dev);
+
+/**
+ * @brief Config dma channel lli.
+ *
+ * @param [in] dev device handle
+ * @param [in] lli_pool pointer to lli pool
+ * @param [in] max_lli_count lli pool size
+ * @param [in] transfer pointer to transfer structure
+ * @param [in] count transfer count.
+ * @return A negated errno value on failure, otherwise means number of used lli.
+ */
+int bflb_dma_channel_lli_reload(struct bflb_device_s *dev,
+                                struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count,
+                                struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count);
+
+/**
+ * @brief Enable lli continueous mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] lli_pool pointer to lli pool
+ * @param [in] used_lli_count number of used lli.
+ */
+void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
+                                    struct bflb_dma_channel_lli_pool_s *lli_pool,
+                                    uint32_t used_lli_count);
+
+/**
+ * @brief Control dma feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command. use @ref DMA_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+/**
+ * @brief Enable or disable dma channel transmission completion interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Check if dma channel transfers completely.
+ *
+ * @param [in] dev device handle
+ * @return true means yes, false means no.
+ */
+bool bflb_dma_channel_get_tcint_status(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear dma channel transmission completion interrupt status.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ef_ctrl.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ef_ctrl.h
new file mode 100755
index 0000000000..f945b849a6
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ef_ctrl.h
@@ -0,0 +1,139 @@
+#ifndef _BFLB_EF_CTRL_H
+#define _BFLB_EF_CTRL_H
+
+#include "bflb_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup EF_CTRL
+  * @{
+  */
+
+/**
+ *  @brief Efuse common trim config definition
+ */
+typedef struct
+{
+    char *name;           /*!< trim anme */
+    uint16_t en_addr;     /*!< enable address */
+    uint16_t parity_addr; /*!< parity address */
+    uint16_t value_addr;  /*!< value address */
+    uint16_t value_len;   /*!< value length */
+} bflb_ef_ctrl_com_trim_cfg_t;
+
+/**
+ *  @brief Efuse common trim type definition
+ */
+typedef struct
+{
+    uint8_t en;     /*!< Enable status */
+    uint8_t parity; /*!< Trim parity */
+    uint8_t empty;  /*!< Trim empty */
+    uint8_t len;    /*!< Trim value len in bit */
+    uint32_t value; /*!< Trim value */
+} bflb_ef_ctrl_com_trim_t;
+
+/**
+ * @brief Get efuse control common trim list.
+ *
+ * @param [in] trim_list pointer to save trim list
+ * @return trim list length
+ */
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @return int
+ */
+int bflb_ef_ctrl_autoload_done(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] offset
+ * @param [in] pword
+ * @param [in] count
+ * @param [in] program
+ */
+void bflb_ef_ctrl_write_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t program);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] offset
+ * @param [in] pword
+ * @param [in] count
+ * @param [in] reload
+ */
+void bflb_ef_ctrl_read_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t reload);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] name
+ * @param [in] trim
+ * @param [in] reload
+ */
+void bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_t *trim, uint8_t reload);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] name
+ * @param [in] value
+ * @param [in] program
+ */
+void bflb_ef_ctrl_write_common_trim(struct bflb_device_s *dev, char *name, uint32_t value, uint8_t program);
+
+/**
+ * @brief
+ *
+ * @param [in] val
+ * @param [in] start
+ * @param [in] len
+ * @return uint8_t
+ */
+uint8_t bflb_ef_ctrl_is_all_bits_zero(uint32_t val, uint8_t start, uint8_t len);
+
+/**
+ * @brief
+ *
+ * @param [in] val
+ * @return uint32_t
+ */
+uint32_t bflb_ef_ctrl_get_byte_zero_cnt(uint8_t val);
+
+/**
+ * @brief
+ *
+ * @param [in] val
+ * @param [in] len
+ * @return uint8_t
+ */
+uint8_t bflb_ef_ctrl_get_trim_parity(uint32_t val, uint8_t len);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_efuse.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_efuse.h
new file mode 100755
index 0000000000..845cdccceb
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_efuse.h
@@ -0,0 +1,30 @@
+#ifndef _BFLB_EFUSE_H
+#define _BFLB_EFUSE_H
+
+#include "bflb_core.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+void bflb_efuse_get_chipid(uint8_t chipid[8]);
+
+uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload);
+int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program);
+int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+
+float bflb_efuse_get_adc_trim(void);
+uint32_t bflb_efuse_get_adc_tsen_trim(void);
+
+void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes);
+void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len);
+void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len);
+
+void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program);
+void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_emac.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_emac.h
new file mode 100755
index 0000000000..7e28fd6abe
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_emac.h
@@ -0,0 +1,343 @@
+#ifndef _BFLB_EMAC_H
+#define _BFLB_EMAC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup EMAC
+  * @{
+  */
+
+#define EMAC_DO_FLUSH_DATA (1)
+
+/* EMAC clock use external or use internal; 0: used external 1: used internal */
+#define EMAC_CLK_USE_EXTERNAL (0)
+#define EMAC_CLK_USE_INTERNAL (1)
+
+/** @defgroup EMAC_CMD emac feature control cmd definition
+  * @{
+  */
+#define EMAC_CMD_NO_PREAMBLE_MODE (0x01)
+#define EMAC_CMD_EN_PROMISCUOUS   (0x02)
+#define EMAC_CMD_FRAME_GAP_CHECK  (0x03)
+#define EMAC_CMD_FULL_DUPLEX      (0x04)
+#define EMAC_CMD_EN_TX_CRC_FIELD  (0x05)
+#define EMAC_CMD_RECV_HUGE_FRAMES (0x06)
+#define EMAC_CMD_EN_AUTO_PADDING  (0x07)
+#define EMAC_CMD_RECV_SMALL_FRAME (0x08)
+#define EMAC_CMD_SET_PHY_ADDRESS  (0x09)
+#define EMAC_CMD_SET_MAC_ADDRESS  (0x0A)
+#define EMAC_CMD_SET_PACKET_GAP   (0x0B)
+#define EMAC_CMD_SET_MIN_FRAME    (0x0C)
+#define EMAC_CMD_SET_MAX_FRAME    (0x0D)
+#define EMAC_CMD_SET_MAXRET       (0x0E)
+#define EMAC_CMD_SET_COLLVALID    (0x0F)
+/**
+  * @}
+  */
+
+/** @defgroup PHY_STATE phy state definition
+  * @{
+  */
+#define PHY_STATE_DOWN    (0) /* PHY is not usable */
+#define PHY_STATE_READY   (1) /* PHY is OK, wait for controller */
+#define PHY_STATE_UP      (2) /* Network is ready for TX/RX */
+#define PHY_STATE_RUNNING (3) /* working */
+#define PHY_STATE_NOLINK  (4) /* no cable connected */
+#define PHY_STATE_STOPPED (5) /* PHY has been stopped */
+#define PHY_STATE_TESTING (6) /* in test mode */
+/**
+  * @}
+  */
+
+/* EMAC PACKET */
+#define EMAC_NORMAL_PACKET   (uint32_t)(0)
+#define EMAC_FRAGMENT_PACKET (uint32_t)(0x01)
+#define EMAC_NOCOPY_PACKET   (uint32_t)(0x02)
+
+/* ETH packet size */
+/* ETH     | Header | Extra | VLAN tag | Payload   | CRC | */
+/* Size    | 14     | 2     | 4        | 46 ~ 1500 | 4   | */
+#define ETH_MAX_PACKET_SIZE          ((uint32_t)1524U) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
+#define ETH_HEADER_SZIE              ((uint32_t)14U)   /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
+#define ETH_CRC_SIZE                 ((uint32_t)4U)    /*!< Ethernet CRC */
+#define ETH_EXTRA_SIZE               ((uint32_t)2U)    /*!< Extra bytes in some cases */
+#define ETH_VLAN_TAG_SIZE            ((uint32_t)4U)    /*!< optional 802.1q VLAN Tag */
+#define ETH_MIN_ETH_PAYLOAD_SIZE     ((uint32_t)46U)   /*!< Minimum Ethernet payload size */
+#define ETH_MAX_ETH_PAYLOAD_SIZE     ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
+#define ETH_JUMBO_FRAME_PAYLOAD_SIZE ((uint32_t)9000U) /*!< Jumbo frame payload size */
+
+/* ETH tx & rx buffer size */
+#ifndef ETH_TX_BUFFER_SIZE
+#define ETH_TX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
+#endif
+#ifndef ETH_RX_BUFFER_SIZE
+#define ETH_RX_BUFFER_SIZE (ETH_MAX_PACKET_SIZE)
+#endif
+
+/* emac interrupt UNMASK/MASK define */
+#define EMAC_INT_EN_TX_DONE  (1 << 0)
+#define EMAC_INT_EN_TX_ERROR (1 << 1)
+#define EMAC_INT_EN_RX_DONE  (1 << 2)
+#define EMAC_INT_EN_RX_ERROR (1 << 3)
+#define EMAC_INT_EN_RX_BUSY  (1 << 4)
+#define EMAC_INT_EN_TX_CTRL  (1 << 5)
+#define EMAC_INT_EN_RX_CTRL  (1 << 6)
+#define EMAC_INT_EN_ALL      (0x7f << 0)
+
+/* emac interrupt status define */
+#define EMAC_INT_STS_TX_DONE  (1 << 0)
+#define EMAC_INT_STS_TX_ERROR (1 << 1)
+#define EMAC_INT_STS_RX_DONE  (1 << 2)
+#define EMAC_INT_STS_RX_ERROR (1 << 3)
+#define EMAC_INT_STS_RX_BUSY  (1 << 4)
+#define EMAC_INT_STS_TX_CTRL  (1 << 5)
+#define EMAC_INT_STS_RX_CTRL  (1 << 6)
+#define EMAC_INT_STS_ALL      (0x7f << 0)
+
+/* emac buffer descriptors type define */
+#define EMAC_BD_TYPE_INVLAID (0)
+#define EMAC_BD_TYPE_TX      (1)
+#define EMAC_BD_TYPE_RX      (2)
+#define EMAC_BD_TYPE_NONE    (3)
+#define EMAC_BD_TYPE_MAX     (0x7FFFFFFF)
+
+/**
+ * @brief EMAC configuration structure
+ *
+ * @param mac_addr  EMAC mac addr
+ * @param inside_clk EMAC select inside or external @ref EMAC_CLK_USE_EXTERNAL or EMAC_CLK_USE_INTERNAL
+ * @param mii_clk_div mii clock div
+ * @param min_frame_len min frame len
+ * @param max_frame_len max frame len
+ *
+ */
+struct bflb_emac_config_s {
+    uint8_t mac_addr[6];
+    uint8_t inside_clk;
+    uint8_t mii_clk_div;
+    uint16_t min_frame_len;
+    uint16_t max_frame_len;
+};
+
+/**
+ * @brief EMAC phy configuration structure
+ *
+ * @param auto_negotiation EMAC phy speed and mode auto negotiation
+ * @param full_duplex      EMAC phy duplex mode
+ * @param phy_state        EMAC phy down,ready,up,running,nolink,halted, @ref PHY_STATE
+ * @param use_irq          EMAC phy interrupt enable 0: no IRQ used
+ * @param speed            EMAC phy speed mode
+ * @param phy_address      EMAC phy address
+ * @param phy_id           EMAC phy read phy id
+ */
+struct bflb_emac_phy_cfg_s {
+    uint8_t auto_negotiation;
+    uint8_t full_duplex;
+    uint8_t phy_state;
+    uint8_t use_irq;
+    uint16_t speed;
+    uint16_t phy_address;
+    uint32_t phy_id;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] config
+ */
+void bflb_emac_init(struct bflb_device_s *dev, const struct bflb_emac_config_s *config);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_start(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_start_tx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_stop_tx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_start_rx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_emac_stop_rx(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] eth_tx_buff
+ * @param [in] tx_buf_count
+ * @param [in] eth_rx_buff
+ * @param [in] rx_buf_count
+ */
+void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] bdt
+ * @return uint32_t
+ */
+uint32_t bflb_emac_bd_get_cur_active(struct bflb_device_s *dev, uint8_t bdt);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_rx_enqueue(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_rx_on_err(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_tx_dequeue(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] index
+ */
+void bflb_emac_bd_tx_on_err(uint32_t index);
+
+/**
+ * @brief
+ *
+ * @param [in] flags
+ * @param [in] len
+ * @param [in] data_in
+ * @return int
+ */
+int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in);
+
+/**
+ * @brief
+ *
+ * @param [in] flags
+ * @param [in] len
+ * @param [in] data_out
+ * @return int
+ */
+int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out);
+
+/**
+ * @brief
+ *
+ * @return int
+ */
+int emac_bd_fragment_support(void);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] flag
+ * @param [in] enable
+ */
+void bflb_emac_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] flag
+ */
+void bflb_emac_int_clear(struct bflb_device_s *dev, uint32_t flag);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint32_t
+ */
+uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] cmd
+ * @param [in] arg
+ * @return int
+ */
+int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] phy_reg
+ * @param [in] phy_reg_val
+ * @return int
+ */
+int bflb_emac_phy_reg_read(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t *phy_reg_val);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] phy_reg
+ * @param [in] phy_reg_val
+ * @return int
+ */
+int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t phy_reg_val);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_flash.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_flash.h
new file mode 100755
index 0000000000..8ad92374be
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_flash.h
@@ -0,0 +1,177 @@
+#ifndef _BFLB_FLASH_H
+#define _BFLB_FLASH_H
+
+#include "bflb_core.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */
+
+/** @defgroup FLASH_IOMODE flash iomode definition
+  * @{
+  */
+#define FLASH_IOMODE_NIO 0 /*!< Normal IO mode define */
+#define FLASH_IOMODE_DO  1 /*!< Dual Output mode define */
+#define FLASH_IOMODE_QO  2 /*!< Quad Output mode define */
+#define FLASH_IOMODE_DIO 3 /*!< Dual IO mode define */
+#define FLASH_IOMODE_QIO 4 /*!< Quad IO mode define */
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_AES_KEY_TYPE flash aes key type definition
+  * @{
+  */
+#define FLASH_AES_KEY_128BITS        0
+#define FLASH_AES_KEY_192BITS        2
+#define FLASH_AES_KEY_256BITS        1
+#define FLASH_AES_KEY_DOUBLE_128BITS 3
+/**
+  * @}
+  */
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define FLASH_XIP_BASE (0x23000000)
+#elif defined(BL616) || defined(BL628)
+#define FLASH_XIP_BASE (0xA0000000)
+#elif defined(BL808) || defined(BL606P)
+#define FLASH_XIP_BASE (0x58000000)
+#endif
+
+struct bflb_flash_aes_config_s {
+    uint8_t region;
+    uint8_t region_enable;
+    uint8_t lock_enable;
+    const uint8_t *key;
+    uint8_t keybits;
+    uint8_t *iv;
+    uint32_t start_addr;
+    uint32_t end_addr;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize flash.
+ *
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_init(void);
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+/**
+ * @brief flash_set_cmds
+ *
+ * @return None
+ */
+void bflb_flash_set_cmds(spi_flash_cfg_type *p_flash_cfg);
+#endif
+
+/**
+ * @brief Get flash jedec id.
+ *
+ * @return uint32_t
+ */
+uint32_t bflb_flash_get_jedec_id(void);
+
+/**
+ * @brief Get flash config.
+ *
+ * @param [out] cfg_addr pointer to save config
+ * @param [in] len flash config size
+ */
+void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len);
+
+/**
+ * @brief Set flash iomode.
+ *
+ * @param [in] iomode flash iomode, use @ref FLASH_IOMODE
+ */
+void bflb_flash_set_iomode(uint8_t iomode);
+
+/**
+ * @brief Get flash image offset.
+ *
+ * @return flash image offset
+ */
+uint32_t bflb_flash_get_image_offset(void);
+
+/**
+ * @brief Erase flash with sectors.
+ *
+ * @param [in] addr
+ * @param [in] len
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_erase(uint32_t addr, uint32_t len);
+
+/**
+ * @brief Write data into flash.
+ *
+ * @param [in] addr flash physical address
+ * @param [in] data pointer to data buffer
+ * @param [in] len length of data
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Read data from flash.
+ *
+ * @param [in] addr flash physical address
+ * @param [out] data pointer to data buffer
+ * @param [in] len length of data
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len);
+
+/**
+ * @brief Config flash cache.
+ *
+ * @param [in] cont_read enable or not continuous read mode.
+ * @param [in] cache_enable enable cache or not
+ * @param [in] cache_way_disable ways of cache to disable
+ * @param [in] flash_offset flash image offset
+ * @return Zero on success; a negated errno value on failure
+ */
+int bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset);
+
+/**
+ * @brief Initialize flash aes controller.
+ *
+ * @param [in] config pointer to flash aes config.
+ */
+void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config);
+
+/**
+ * @brief Enable flash decrypt with aes.
+ *
+ */
+void bflb_flash_aes_enable(void);
+
+/**
+ * @brief Disable flash decrypt with aes.
+ *
+ */
+void bflb_flash_aes_disable(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h
new file mode 100755
index 0000000000..e4f410d83b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_gpio.h
@@ -0,0 +1,409 @@
+#ifndef _BFLB_GPIO_H
+#define _BFLB_GPIO_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */
+
+/**
+ * @brief Gpio pin definitions
+ *
+ * BL602  : GPIO0/1/2/7/8/14/15/20/21/22
+ * BL604  : GPIO0 ~ GPIO5, GPIO7/8/11/12/14/16/17/20/21/22
+ * BL606  : GPIO0 ~ GPIO22
+ * BL702  : GPIO0/1/2/7/8/9/14/15/17/23/24/25/26/27/28
+ * BL704  : GPIO0 ~ GPIO3, GPIO7 ~ GPIO11, GPIO14/15, GPIO17 ~ GPIO28,
+ * BL706  : GPIO0 ~ GPIO31
+ * BL606P : GPIO0 ~ GPIO5, GPIO11 ~ GPIO12, GPIO16 ~ GPIO21, GPIO24 ~ GPIO28, GPIO34 ~ GPIO41
+ * BL616  : GPIO0 ~ GPIO3, GPIO10 ~ GPIO17, GPIO20 ~ GPIO22, GPIO27 ~ GPIO30
+ * BL618  : GPIO0 ~ GPIO34
+ * BL808C : GPIO0 ~ GPIO23, GPIO34 ~ GPIO45
+ * BL808D : GPIO0 ~ GPIO8, GPIO11 ~ GPIO41
+ *
+ */
+
+/** @defgroup GPIO_PIN gpio pin definition
+  * @{
+  */
+#define GPIO_PIN_0      0
+#define GPIO_PIN_1      1
+#define GPIO_PIN_2      2
+#define GPIO_PIN_3      3
+#define GPIO_PIN_4      4
+#define GPIO_PIN_5      5
+#define GPIO_PIN_6      6
+#define GPIO_PIN_7      7
+#define GPIO_PIN_8      8
+#define GPIO_PIN_9      9
+#define GPIO_PIN_10     10
+#define GPIO_PIN_11     11
+#define GPIO_PIN_12     12
+#define GPIO_PIN_13     13
+#define GPIO_PIN_14     14
+#define GPIO_PIN_15     15
+#define GPIO_PIN_16     16
+#define GPIO_PIN_17     17
+#define GPIO_PIN_18     18
+#define GPIO_PIN_19     19
+#define GPIO_PIN_20     20
+#define GPIO_PIN_21     21
+#define GPIO_PIN_22     22
+#define GPIO_PIN_23     23
+#define GPIO_PIN_24     24
+#define GPIO_PIN_25     25
+#define GPIO_PIN_26     26
+#define GPIO_PIN_27     27
+#define GPIO_PIN_28     28
+#define GPIO_PIN_29     29
+#define GPIO_PIN_30     30
+#define GPIO_PIN_31     31
+#define GPIO_PIN_32     32
+#define GPIO_PIN_33     33
+#define GPIO_PIN_34     34
+#define GPIO_PIN_35     35
+#define GPIO_PIN_36     36
+#define GPIO_PIN_37     37
+#define GPIO_PIN_38     38
+#define GPIO_PIN_39     39
+#define GPIO_PIN_40     40
+#define GPIO_PIN_41     41
+#define GPIO_PIN_42     42
+#define GPIO_PIN_43     43
+#define GPIO_PIN_44     44
+#define GPIO_PIN_45     45
+/**
+  * @}
+  */
+
+/* cfgset list */
+#define GPIO_FUNC_SHIFT (0) /* Bits 0-4: GPIO function */
+#define GPIO_FUNC_MASK  (0x1f << GPIO_FUNC_SHIFT)
+#if defined(BL602)
+#define GPIO_FUNC_SDIO (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0 (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0 (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0 (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG (14 << GPIO_FUNC_SHIFT)
+#elif defined(BL702)
+#define GPIO_FUNC_CLK_OUT  (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S      (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0     (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0     (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0     (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM      (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG     (14 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC     (19 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM_MCLK (23 << GPIO_FUNC_SHIFT)
+#elif defined(BL702L)
+#define GPIO_FUNC_SPI0    (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0    (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0    (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_KEYSCAN (13 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG    (14 << GPIO_FUNC_SHIFT)
+#elif defined(BL616)
+#define GPIO_FUNC_SDH       (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0      (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S       (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PDM       (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0      (5 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C1      (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC      (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM       (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SDU       (12 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0      (16 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_B     (22 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_C     (23 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_QSPI  (24 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_AUDAC_PWM (25 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG      (26 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PEC       (27 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CLKOUT    (31 << GPIO_FUNC_SHIFT)
+#elif defined(BL606P) || defined(BL808)
+#define GPIO_FUNC_SDH     (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0    (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S     (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PDM     (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0    (5 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C1    (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC    (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM     (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SDU     (12 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0    (16 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM1    (17 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI1    (18 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C2    (19 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C3    (20 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C3    (20 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_B   (22 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_C   (23 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG_LP (25 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG_M0 (26 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_JTAG_D0 (27 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CLKOUT  (31 << GPIO_FUNC_SHIFT)
+#elif defined(BL628)
+#define GPIO_FUNC_SDH    (0 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SPI0   (1 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2S    (3 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PDM    (4 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C0   (5 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_I2C1   (6 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_UART   (7 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_EMAC   (8 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CAM    (9 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_SDU    (12 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PWM0   (16 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_B  (22 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_DBI_C  (23 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_PEC    (27 << GPIO_FUNC_SHIFT)
+#define GPIO_FUNC_CLKOUT (31 << GPIO_FUNC_SHIFT)
+#endif
+
+#define GPIO_MODE_SHIFT                      (5) /* Bits 5-6: Port Mode */
+#define GPIO_MODE_MASK                       (3 << GPIO_MODE_SHIFT)
+#define GPIO_INPUT                           (0 << GPIO_MODE_SHIFT) /* Input Enable */
+#define GPIO_OUTPUT                          (1 << GPIO_MODE_SHIFT) /* Output Enable */
+#define GPIO_ANALOG                          (2 << GPIO_MODE_SHIFT) /* Analog Enable */
+#define GPIO_ALTERNATE                       (3 << GPIO_MODE_SHIFT) /* Alternate Enable */
+
+#define GPIO_PUPD_SHIFT                      (7) /* Bits 7-8: Pull-up/down */
+#define GPIO_PUPD_MASK                       (3 << GPIO_PUPD_SHIFT)
+#define GPIO_FLOAT                           (0 << GPIO_PUPD_SHIFT) /* No pull-up, pull-down */
+#define GPIO_PULLUP                          (1 << GPIO_PUPD_SHIFT) /* Pull-up */
+#define GPIO_PULLDOWN                        (2 << GPIO_PUPD_SHIFT) /* Pull-down */
+
+#define GPIO_SMT_SHIFT                       (9) /* Bits 9: SMT Enable */
+#define GPIO_SMT_MASK                        (1 << GPIO_SMT_SHIFT)
+#define GPIO_SMT_DIS                         (0 << GPIO_SMT_SHIFT)
+#define GPIO_SMT_EN                          (1 << GPIO_SMT_SHIFT)
+
+#define GPIO_DRV_SHIFT                       (10) /* Bits 10-11: Drive */
+#define GPIO_DRV_MASK                        (3 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_0                           (0 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_1                           (1 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_2                           (2 << GPIO_DRV_SHIFT)
+#define GPIO_DRV_3                           (3 << GPIO_DRV_SHIFT)
+
+/** @defgroup GPIO_INT_TRIG_MODE gpio interrupt trigger mode definition
+  * @{
+  */
+#define GPIO_INT_TRIG_MODE_SYNC_FALLING_EDGE 0
+#define GPIO_INT_TRIG_MODE_SYNC_RISING_EDGE  1
+#define GPIO_INT_TRIG_MODE_SYNC_LOW_LEVEL    2
+#define GPIO_INT_TRIG_MODE_SYNC_HIGH_LEVEL   3
+#if defined(BL602) || defined(BL702)
+#define GPIO_INT_TRIG_MODE_ASYNC_FALLING_EDGE 4
+#define GPIO_INT_TRIG_MODE_ASYNC_RISING_EDGE  5
+#define GPIO_INT_TRIG_MODE_ASYNC_LOW_LEVEL    6
+#define GPIO_INT_TRIG_MODE_ASYNC_HIGH_LEVEL   7
+#else
+#define GPIO_INT_TRIG_MODE_SYNC_FALLING_RISING_EDGE 4
+#define GPIO_INT_TRIG_MODE_ASYNC_FALLING_EDGE       8
+#define GPIO_INT_TRIG_MODE_ASYNC_RISING_EDGE        9
+#define GPIO_INT_TRIG_MODE_ASYNC_LOW_LEVEL          10
+#define GPIO_INT_TRIG_MODE_ASYNC_HIGH_LEVEL         11
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_UART_FUNC gpio uart function definition
+  * @{
+  */
+#define GPIO_UART_FUNC_UART0_RTS 0
+#define GPIO_UART_FUNC_UART0_CTS 1
+#define GPIO_UART_FUNC_UART0_TX  2
+#define GPIO_UART_FUNC_UART0_RX  3
+#define GPIO_UART_FUNC_UART1_RTS 4
+#define GPIO_UART_FUNC_UART1_CTS 5
+#define GPIO_UART_FUNC_UART1_TX  6
+#define GPIO_UART_FUNC_UART1_RX  7
+#if defined(BL808) || defined(BL606P)
+#define GPIO_UART_FUNC_UART2_RTS 8
+#define GPIO_UART_FUNC_UART2_CTS 9
+#define GPIO_UART_FUNC_UART2_TX  10
+#define GPIO_UART_FUNC_UART2_RX  11
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_ISO11898_FUNC gpio iso11898 function definition
+  * @{
+  */
+#if defined(BL808) || defined(BL606P)|| defined(BL616)|| defined(BL628)
+#define GPIO_ISO11898_FUNC_TX 10
+#define GPIO_ISO11898_FUNC_RX 11
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_CMD gpio feature control cmd definition
+  * @{
+  */
+#define GPIO_CMD_GET_GPIO_FUN (0x01)
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize gpio pin.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] cfgset gpio config mask
+ */
+void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset);
+
+/**
+ * @brief Deinitialize gpio pin with input float.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Write gpio pin with high level.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Write gpio pin with low level.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Read level from gpio pin.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @return true means high level, otherwise low level
+ */
+bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Write gpio pin 0~31.
+ *
+ * @param [in] dev device handle
+ * @param [in] val gpio pin 0~31 value
+ */
+void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val);
+
+/**
+ * @brief Write gpio pin 32~63.
+ *
+ * @param [in] dev device handle
+ * @param [in] val gpio pin 32~63 value
+ */
+void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val);
+
+/**
+ * @brief Read level from gpio pin 0~31.
+ *
+ * @param [in] dev device handle
+ * @return level of gpio pin 0~31
+ */
+uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev);
+
+/**
+ * @brief Read level from gpio pin 32~63.
+ *
+ * @param [in] dev device handle
+ * @return level of gpio pin32~63
+ */
+uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev);
+
+/**
+ * @brief Config gpio pin interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] trig_mode mode to trigger interrupt
+ */
+void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode);
+
+/**
+ * @brief Enable or disable gpio pin interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask);
+
+/**
+ * @brief Get gpio pin interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @return true means yes, false means no
+ */
+bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Clear gpio pin interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ */
+void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin);
+
+/**
+ * @brief Config gpio pin with uart function.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] uart_func uart function, use @ref GPIO_UART_FUNC
+ */
+void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func);
+
+/**
+ * @brief Config gpio pin with iso11898 function.
+ *
+ * @param [in] dev device handle
+ * @param [in] pin gpio pin, use @ref GPIO_PIN
+ * @param [in] iso11898_func iso11898 function, use @ref GPIO_ISO11898_FUNC
+ */
+void bflb_gpio_iso11898_init(struct bflb_device_s *dev, uint8_t pin, uint8_t iso11898_func);
+
+/**
+ * @brief Control gpio feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref GPIO_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+
+int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2c.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2c.h
new file mode 100755
index 0000000000..3395e833a1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2c.h
@@ -0,0 +1,194 @@
+#ifndef _BFLB_I2C_H
+#define _BFLB_I2C_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Bit definitions for the flags field in struct bflb_i2c_msg_s
+ *
+ * START/STOP Rules:
+ *
+ * 1. The lower half I2C driver will always issue the START condition at the
+ *    beginning of a message unless I2C_M_NOSTART flag is set in the
+ *    message.
+ *
+ * 2. The lower half I2C driver will always issue the STOP condition at the
+ *    end of the messages unless:
+ *
+ *    a. The I2C_M_NOSTOP flag is set in the message, OR
+ *    b. The following message has the I2C_M_NOSTART flag set (meaning
+ *       that following message is simply a continuation of the transfer).
+ *
+ * A proper I2C repeated start would then have I2C_M_NOSTOP set on msg[n]
+ * and I2C_M_NOSTART *not* set on msg[n+1].  See the following table:
+ *
+ *   msg[n].flags  msg[n+1].flags Behavior
+ *   ------------ --------------- -----------------------------------------
+ *   0            0                Two normal, separate messages with STOP
+ *                                 on msg[n] then START on msg[n+1]
+ *   0*           I2C_M_NOSTART    Continuation of the same transfer (must
+ *                                 be the same direction).  See NOTE below.
+ *   NO_STOP      0                No STOP on msg[n]; repeated START on
+ *                                 msg[n+1].
+ *
+ * * NOTE: NO_STOP is implied in this case and may or not be explicitly
+ *   included in the msg[n] flags
+ */
+
+#define I2C_M_READ    0x0001 /* Read data, from slave to master */
+#define I2C_M_TEN     0x0002 /* Ten bit address */
+#define I2C_M_DMA     0x0004 /* Enable dma mode */
+#define I2C_M_NOSTOP  0x0040 /* Message should not end with a STOP */
+#define I2C_M_NOSTART 0x0080 /* Message should not begin with a START */
+
+/** @defgroup I2C_INTSTS i2c interrupt status definition
+  * @{
+  */
+#define I2C_INTSTS_END     (1 << 0) /* Transfer end interrupt */
+#define I2C_INTSTS_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */
+#define I2C_INTSTS_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */
+#define I2C_INTSTS_NACK    (1 << 3) /* NACK interrupt */
+#define I2C_INTSTS_ARB     (1 << 4) /* Arbitration lost interrupt */
+#define I2C_INTSTS_FER     (1 << 5) /* TX/RX FIFO error interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_INTCLR i2c interrupt clear definition
+  * @{
+  */
+#define I2C_INTCLR_END  (1 << 0) /* Transfer end interrupt */
+#define I2C_INTCLR_NACK (1 << 3) /* NACK interrupt */
+#define I2C_INTCLR_ARB  (1 << 4) /* Arbitration lost interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup I2C_INTEN i2c interrupt enable definition
+  * @{
+  */
+#define I2C_INTEN_END     (1 << 0) /* Transfer end interrupt */
+#define I2C_INTEN_TX_FIFO (1 << 1) /* TX FIFO ready interrupt */
+#define I2C_INTEN_RX_FIFO (1 << 2) /* RX FIFO ready interrupt */
+#define I2C_INTEN_NACK    (1 << 3) /* NACK interrupt */
+#define I2C_INTEN_ARB     (1 << 4) /* Arbitration lost interrupt */
+#define I2C_INTEN_FER     (1 << 5) /* TX/RX FIFO error interrupt */
+/**
+ * @}
+ */
+
+/**
+ * @brief I2C message structure
+ *
+ * @param addr          Slave address (7- or 10-bit)
+ * @param flags         See I2C_M_* definitions
+ * @param buffer        Buffer to be transferred
+ * @param length        Length of the buffer in bytes, should be less than 256.
+ */
+struct bflb_i2c_msg_s {
+    uint16_t addr;
+    uint16_t flags;
+    uint8_t *buffer;
+    uint16_t length;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize i2c.
+ *
+ * @param [in] dev device handle
+ * @param [in] frequency i2c frequency, range from 305Hz to 400KHz
+ */
+void bflb_i2c_init(struct bflb_device_s *dev, uint32_t frequency);
+
+/**
+ * @brief Deinitialize i2c.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_i2c_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable i2c tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2c_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable i2c rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2c_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Start transferring i2c message.
+ *
+ * @param [in] dev device handle
+ * @param [in] msgs pointer to i2c message
+ * @param [in] count message count
+ * @return A negated errno value on failure.
+ */
+int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, int count);
+
+/**
+ * @brief Enable or disable i2c interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type interrupt type ,use @ref I2C_INTEN
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2c_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask);
+
+/**
+ * @brief Clear i2c interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref I2C_INTCLR
+ */
+void bflb_i2c_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Get i2c interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status value, use @ref I2C_INTSTS
+ */
+uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control i2c feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2s.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2s.h
new file mode 100755
index 0000000000..e006116d28
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_i2s.h
@@ -0,0 +1,207 @@
+#ifndef _BFLB_I2S_H
+#define _BFLB_I2S_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup I2S
+  * @{
+  */
+
+/** @defgroup I2S_ROLE i2s role definition
+  * @{
+  */
+#define I2S_ROLE_MASTER 0
+#define I2S_ROLE_SLAVE  1
+/**
+  * @}
+  */
+
+/** @defgroup I2S_FORMAT_MODE i2s mode definition
+  * @{
+  */
+#define I2S_MODE_LEFT_JUSTIFIED       0 /* left-justified or Phillips standard */
+#define I2S_MODE_RIGHT_JUSTIFIED      1 /* right-justified */
+#define I2S_MODE_DSP_SHORT_FRAME_SYNC 2 /* dsp modeA/B short frame sync */
+#define I2S_MODE_DSP_LONG_FRAME_SYNC  3 /* dsp modeA/B long frame sync */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_CHANNEL_MODE i2s mode definition
+  * @{
+  */
+#define I2S_CHANNEL_MODE_NUM_1 0
+#define I2S_CHANNEL_MODE_NUM_2 1
+#define I2S_CHANNEL_MODE_NUM_3 2 /* only DSP mode, frame_size must equal data_size */
+#define I2S_CHANNEL_MODE_NUM_4 3 /* only DSP mode, frame_size must equal data_size */
+#define I2S_CHANNEL_MODE_NUM_6 4 /* only DSP mode, frame_size must equal data_size */
+/**
+  * @}
+  */
+
+/** @defgroup I2S_SLOT_WIDTH i2s slot width definition
+  * @{
+  */
+#define I2S_SLOT_WIDTH_8  0
+#define I2S_SLOT_WIDTH_16 1
+#define I2S_SLOT_WIDTH_24 2
+#define I2S_SLOT_WIDTH_32 3
+/**
+  * @}
+  */
+
+/** @defgroup I2S_INTSTS i2s interrupt status definition
+  * @{
+  */
+#define I2S_INTSTS_TX_FIFO  (1 << 1)
+#define I2S_INTSTS_RX_FIFO  (1 << 2)
+#define I2S_INTSTS_FIFO_ERR (1 << 3)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_CMD i2s feature control cmd definition
+  * @{
+  */
+#define I2S_CMD_CLEAR_TX_FIFO    (0x01)
+#define I2S_CMD_CLEAR_RX_FIFO    (0x02)
+#define I2S_CMD_RX_DEGLITCH      (0x03)
+#define I2S_CMD_DATA_ENABLE      (0x04)
+#define I2S_CMD_CHANNEL_LR_MERGE (0x05)
+#define I2S_CMD_CHANNEL_LR_EXCHG (0x06)
+#define I2S_CMD_MUTE             (0x07)
+#define I2S_CMD_BIT_REVERSE      (0x08)
+/**
+  * @}
+  */
+
+/** @defgroup I2S_CMD_DATA_ENABLE_TYPE i2s data enable type
+  * @{
+  */
+#define I2S_CMD_DATA_ENABLE_TX (1 << 1)
+#define I2S_CMD_DATA_ENABLE_RX (1 << 2)
+
+/**
+  * @}
+  */
+
+/**
+ * @brief I2S configuration structure
+ *
+ * @param bclk_freq_hz        I2S bit frequence, Sampling_rate = bclk_freq_hz / frame_width / channel_num.
+ * @param role                I2S role, use @ref I2S_ROLE
+ * @param format_mode         I2S mode, use @ref I2S_FORMAT_MODE
+ * @param channel_mode        I2S channel num, Only DSP mode supports more than 2 channels, use @ref I2S_CHANNEL_MODE
+ * @param frame_width         I2S frame width, use @ref I2S_SLOT_WIDTH
+ * @param data_width          I2S data order, frame_size must equal data_size in 3/4/6-channel mode, use @ref I2S_SLOT_WIDTH
+ * @param fs_offset_cycle     I2S first bit offset of the data
+ * @param tx_fifo_threshold   I2S tx fifo threshold, should be less than 16
+ * @param rx_fifo_threshold   I2S rx fifo threshold, should be less than 16
+ */
+struct bflb_i2s_config_s {
+    uint32_t bclk_freq_hz;
+    uint8_t role;
+    uint8_t format_mode;
+    uint8_t channel_mode;
+    uint8_t frame_width;
+    uint8_t data_width;
+    uint8_t fs_offset_cycle;
+
+    uint8_t tx_fifo_threshold;
+    uint8_t rx_fifo_threshold;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize i2s.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save i2s config
+ */
+void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config);
+
+/**
+ * @brief Deinitialize i2s.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_i2s_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Enable i2s tx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable i2s rx dma.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Enable or disable i2s rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable i2s rx fifo threhold interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable i2s error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get i2s interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref I2S_INTSTS
+ */
+uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Control i2s feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref I2S_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ir.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ir.h
new file mode 100755
index 0000000000..821f57666b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_ir.h
@@ -0,0 +1,375 @@
+#ifndef _BFLB_IR_H
+#define _BFLB_IR_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup IR
+  * @{
+  */
+
+#if !defined(BL616)
+/** @defgroup IR_TX_MODE ir tx mode definition
+  * @{
+  */
+#define IR_TX_NEC       0
+#define IR_TX_RC5       1
+#define IR_TX_SWM       2
+#define IR_TX_CUSTOMIZE 3
+/**
+  * @}
+  */
+
+/** @defgroup IR_TX_FIFO_WIDTH ir tx fifo width valid width definition
+  * @{
+  */
+#if !defined(BL602) && !defined(BL702)
+#define IR_TX_FIFO_WIDTH_8BIT  0
+#define IR_TX_FIFO_WIDTH_16BIT 1
+#define IR_TX_FIFO_WIDTH_24BIT 2
+#endif
+#define IR_TX_FIFO_WIDTH_32BIT 3
+/**
+  * @}
+  */
+
+/** @defgroup IR_TX_INTEN ir tx interrupt enable definition
+  * @{
+  */
+#define IR_TX_INTEN_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_TX_INTEN_FIFO (1 << 1)
+#define IR_TX_INTEN_FER  (1 << 2)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup IR_TX_INTSTS ir tx interrupt status definition
+  * @{
+  */
+#define IR_TX_INTSTS_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_TX_INTSTS_FIFO (1 << 1)
+#define IR_TX_INTSTS_FER  (1 << 2)
+#endif
+/**
+  * @}
+  */
+
+#endif
+
+#if !defined(BL702L)
+/** @defgroup IR_RX_MODE ir rx mode definition
+  * @{
+  */
+#define IR_RX_NEC 0
+#define IR_RX_RC5 1
+#define IR_RX_SWM 2
+/**
+  * @}
+  */
+
+/** @defgroup IR_RX_INTEN ir rx interrupt enable definition
+  * @{
+  */
+#define IR_RX_INTEN_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_RX_INTEN_FIFO (1 << 1)
+#define IR_RX_INTEN_FER  (1 << 2)
+#endif
+/**
+  * @}
+  */
+
+/** @defgroup IR_RX_INTSTS ir rx interrupt status definition
+  * @{
+  */
+#define IR_RX_INTSTS_END (1 << 0)
+#if !defined(BL602) && !defined(BL702)
+#define IR_RX_INTSTS_FIFO (1 << 1)
+#define IR_RX_INTSTS_FER  (1 << 2)
+#endif
+/**
+  * @}
+  */
+#endif
+
+#if !defined(BL616)
+/**
+ * @brief IR TX configuration structure
+ *
+ * @param tx_mode              TX mode select, use @ref IR_TX_MODE
+ * @param data_bits            Bit count of data phase (don't care if tx freerun mode is enabled)
+ * @param tail_inverse         Enable or disable signal of tail pulse inverse (don't care if SWM is enabled)
+ * @param tail_enable          Enable or disable signal of tail pulse (don't care if SWM is enabled)
+ * @param head_inverse         Enable or disable signal of head pulse inverse (don't care if SWM is enabled)
+ * @param head_enable          Enable or disable signal of head pulse (don't care if SWM is enabled)
+ * @param logic1_inverse       Enable or disable signal of logic 1 pulse inverse (don't care if SWM is enabled)
+ * @param logic0_inverse       Enable or disable signal of logic 0 pulse inverse (don't care if SWM is enabled)
+ * @param data_enable          Enable or disable signal of data pulse (don't care if SWM is enabled)
+ * @param swm_enable           Enable or disable software mode(SWM)
+ * @param output_modulation    Enable or disable signal of output modulation
+ * @param output_inverse       Enable or disable signal of output inverse,0:output stays at low during idle state,1:stay at high
+ * @param freerun_enable       Enable or disable tx freerun mode (don't care if SWM is enabled)
+ * @param continue_enable      Disable:idle time between frames = (tailPulseWidth_0+tailPulseWidth_1)*pulseWidthUnit,Enable:no idle time between frames
+ * @param fifo_width           IR frame size(also the valid width for each fifo entry), use @ref IR_TX_FIFO_WIDTH
+ * @param fifo_threshold       TX FIFO threshold
+ * @param logic0_pulse_width_1 Pulse width of logic 0 pulse phase 1 (don't care if SWM is enabled)
+ * @param logic0_pulse_width_0 Pulse width of logic 0 pulse phase 0 (don't care if SWM is enabled)
+ * @param logic1_pulse_width_1 Pulse width of logic 1 pulse phase 1 (don't care if SWM is enabled)
+ * @param logic1_pulse_width_0 Pulse width of logic 1 pulse phase 0 (don't care if SWM is enabled)
+ * @param head_pulse_width_1   Pulse width of head pulse phase 1 (don't care if SWM is enabled)
+ * @param head_pulse_width_0   Pulse width of head pulse phase 0 (don't care if SWM is enabled)
+ * @param tail_pulse_width_1   Pulse width of tail pulse phase 1 (don't care if SWM is enabled)
+ * @param tail_pulse_width_0   Pulse width of tail pulse phase 0 (don't care if SWM is enabled)
+ * @param modu_width_1         Modulation phase 1 width
+ * @param modu_width_0         Modulation phase 0 width
+ * @param pulse_width_unit     Pulse width unit
+ */
+struct bflb_ir_tx_config_s {
+    uint8_t tx_mode;
+    uint8_t data_bits;
+    uint8_t tail_inverse;
+    uint8_t tail_enable;
+    uint8_t head_inverse;
+    uint8_t head_enable;
+    uint8_t logic1_inverse;
+    uint8_t logic0_inverse;
+    uint8_t data_enable;
+    uint8_t swm_enable;
+    uint8_t output_modulation;
+    uint8_t output_inverse;
+    uint8_t freerun_enable;
+    uint8_t continue_enable;
+    uint8_t fifo_width;
+    uint8_t fifo_threshold;
+    uint8_t logic0_pulse_width_1;
+    uint8_t logic0_pulse_width_0;
+    uint8_t logic1_pulse_width_1;
+    uint8_t logic1_pulse_width_0;
+    uint8_t head_pulse_width_1;
+    uint8_t head_pulse_width_0;
+    uint8_t tail_pulse_width_1;
+    uint8_t tail_pulse_width_0;
+    uint8_t modu_width_1;
+    uint8_t modu_width_0;
+    uint16_t pulse_width_unit;
+};
+#endif
+
+#if !defined(BL702L)
+/**
+ * @brief IR RX configuration structure
+ *
+ * @param rx_mode         RX mode select, use @ref IR_RX_MODE
+ * @param input_inverse   Enable or disable signal of input inverse
+ * @param deglitch_enable Enable or disable signal of rx input de-glitch function
+ * @param deglitch_cnt    De-glitch function cycle count
+ * @param  data_threshold Pulse width threshold for logic 0/1 detection (don't care if SWM is enabled)
+ * @param  end_threshold  Pulse width threshold to trigger end condition
+ * @param  fifo_threshold RX FIFO threshold
+ */
+struct bflb_ir_rx_config_s {
+    uint8_t rx_mode;
+    uint8_t input_inverse;
+    uint8_t deglitch_enable;
+    uint8_t deglitch_cnt;
+    uint16_t data_threshold;
+    uint16_t end_threshold;
+    uint16_t fifo_threshold;
+};
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#if !defined(BL616)
+/**
+ * @brief Initialize ir tx.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to ir tx configure structure
+ */
+void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config);
+
+/**
+ * @brief Send data in NEC/RC5/customize mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] data data buffer to send
+ * @param [in] length length of data buffer
+ */
+void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length);
+
+/**
+ * @brief Send data in software mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] data data data buffer to send
+ * @param [in] length length of data buffer
+ */
+void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
+
+/**
+ * @brief Enable or disable ir tx.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Mask or unmask ir tx interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type ir tx interrupt type, use @ref IR_TX_INTEN
+ * @param [in] mask mask or unmask
+ */
+void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
+
+/**
+ * @brief Get ir tx interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Ir tx interrupt status
+ */
+uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir tx interrupt.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_txint_clear(struct bflb_device_s *dev);
+
+#if !defined(BL602) && !defined(BL702)
+/**
+ * @brief Enable or disable ir tx dma mode.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Get ir tx fifo available count.
+ *
+ * @param [in] dev device handle
+ * @return Ir tx fifo available count
+ */
+uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir tx fifo.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_txfifo_clear(struct bflb_device_s *dev);
+#endif
+#endif
+
+#if !defined(BL702L)
+/**
+ * @brief Initialize ir rx.
+ *
+ * @param [in] dev device handle
+ * @param [in] config config pointer to ir rx configure structure
+ */
+void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config);
+
+/**
+ * @brief Receive data in NEC/RC5/customize mode.
+ *
+ * @param [in] dev device handle
+ * @param [out] data data received
+ * @return Bit count of data received
+ */
+uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data);
+
+/**
+ * @brief Receive data in software mode.
+ *
+ * @param [in] dev device handle
+ * @param [out] data data buffer to receive
+ * @param [in] length of data buffer
+ * @return Length of data received
+ */
+uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length);
+
+/**
+ * @brief Enable or disable ir rx.
+ *
+ * @param [in] dev device handle
+ * @param [in] enable enable or disable
+ */
+void bflb_ir_rx_enable(struct bflb_device_s *dev, bool enable);
+
+/**
+ * @brief Get ir rx fifo available count.
+ *
+ * @param [in] dev device handle
+ * @return Ir rx fifo available count
+ */
+uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir rx fifo.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_rxfifo_clear(struct bflb_device_s *dev);
+
+/**
+ * @brief Mask ir rx interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_type ir rx interrupt type, use @ref IR_RX_INTEN
+ * @param [in] mask mask or unmask
+ */
+void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask);
+
+/**
+ * @brief Get ir rx interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return Ir rx interrupt status
+ */
+uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear ir rx interrupt.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_ir_rxint_clear(struct bflb_device_s *dev);
+
+#endif
+
+/**
+ * @brief Control ir feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure
+ */
+int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_irq.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_irq.h
new file mode 100755
index 0000000000..c56a723508
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_irq.h
@@ -0,0 +1,125 @@
+#ifndef _BFLB_IRQ_H
+#define _BFLB_IRQ_H
+
+#include "stdint.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup IRQ
+  * @{
+  */
+
+typedef void (*irq_callback)(int irq, void *arg);
+
+/**
+ * @brief IRQ configuration structure
+ *
+ * @param handler      Address of the interrupt handler
+ * @param arg          The argument provided to the interrupt handler
+ */
+struct bflb_irq_info_s {
+    irq_callback handler;
+    void *arg;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Interrupt initialize.
+ *
+ */
+void bflb_irq_initialize(void);
+
+/**
+ * @brief Disable global irq and save the previous status.
+ *
+ * @return last status
+ */
+uintptr_t bflb_irq_save(void);
+
+/**
+ * @brief Enable global irq by the previous status.
+ *
+ * @param [in] flags previous status by bflb_irq_save
+ */
+void bflb_irq_restore(uintptr_t flags);
+
+/**
+ * @brief Attach interrupt with callback.
+ *
+ * @param [in] irq irq number
+ * @param [in] isr interrupt callback
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_irq_attach(int irq, irq_callback isr, void *arg);
+
+/**
+ * @brief Detach interrupt, reset interrupt callback.
+ *
+ * @param [in] irq irq number
+ * @return A negated errno value on failure.
+ */
+int bflb_irq_detach(int irq);
+
+/**
+ * @brief Enable interrupt.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_enable(int irq);
+
+/**
+ * @brief Disable interrupt.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_disable(int irq);
+
+/**
+ * @brief Set interrupt with pending.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_set_pending(int irq);
+
+/**
+ * @brief Clear interrupt pending status.
+ *
+ * @param [in] irq irq number
+ */
+void bflb_irq_clear_pending(int irq);
+
+/**
+ * @brief Set interrupt group.
+ *
+ * @param [in] nlbits
+ */
+void bflb_irq_set_nlbits(uint8_t nlbits);
+
+/**
+ * @brief Set interrupt priority.
+ *
+ * @param [in] irq irq number
+ * @param [in] preemptprio preempt priority
+ * @param [in] subprio sub priority
+ */
+void bflb_irq_set_priority(int irq, uint8_t preemptprio, uint8_t subprio);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h
new file mode 100755
index 0000000000..2d7b683aaf
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_iso11898.h
@@ -0,0 +1,249 @@
+#ifndef _BFLB_ISO11898_H
+#define _BFLB_ISO11898_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup ISO11898
+  * @{
+  */
+
+#define ISO11898_TIMEOUT (320 * 1000 * 1000)
+
+#define ISO11898_MODE_NORMAL          0 /*!< normal mode */
+#define ISO11898_MODE_LOOPBACK        1 /*!< loopback mode */
+#define ISO11898_MODE_SILENT          2 /*!< silent mode */
+#define ISO11898_MODE_SILENT_LOOPBACK 3 /*!< loopback combined with silent mode */
+
+#define ISO11898_SAMPLE_SINGLE 0 /*!< the bus is sampled three times, recommended for low/medium speed buses */
+#define ISO11898_SAMPLE_TRIPLE 1 /*!< the bus is sampled once, recommended for high speed buses */
+
+#define ISO11898_SJW_1TQ 0 /*!< 1 time quantum */
+#define ISO11898_SJW_2TQ 1 /*!< 2 time quantum */
+#define ISO11898_SJW_3TQ 2 /*!< 3 time quantum */
+#define ISO11898_SJW_4TQ 3 /*!< 4 time quantum */
+
+#define ISO11898_BS1_1TQ  0  /*!< 1 time quantum */
+#define ISO11898_BS1_2TQ  1  /*!< 2 time quantum */
+#define ISO11898_BS1_3TQ  2  /*!< 3 time quantum */
+#define ISO11898_BS1_4TQ  3  /*!< 4 time quantum */
+#define ISO11898_BS1_5TQ  4  /*!< 5 time quantum */
+#define ISO11898_BS1_6TQ  5  /*!< 6 time quantum */
+#define ISO11898_BS1_7TQ  6  /*!< 7 time quantum */
+#define ISO11898_BS1_8TQ  7  /*!< 8 time quantum */
+#define ISO11898_BS1_9TQ  8  /*!< 9 time quantum */
+#define ISO11898_BS1_10TQ 9  /*!< 10 time quantum */
+#define ISO11898_BS1_11TQ 10 /*!< 11 time quantum */
+#define ISO11898_BS1_12TQ 11 /*!< 12 time quantum */
+#define ISO11898_BS1_13TQ 12 /*!< 13 time quantum */
+#define ISO11898_BS1_14TQ 13 /*!< 14 time quantum */
+#define ISO11898_BS1_15TQ 14 /*!< 15 time quantum */
+#define ISO11898_BS1_16TQ 15 /*!< 16 time quantum */
+
+#define ISO11898_BS2_1TQ 0 /*!< 1 time quantum */
+#define ISO11898_BS2_2TQ 1 /*!< 2 time quantum */
+#define ISO11898_BS2_3TQ 2 /*!< 3 time quantum */
+#define ISO11898_BS2_4TQ 3 /*!< 4 time quantum */
+#define ISO11898_BS2_5TQ 4 /*!< 5 time quantum */
+#define ISO11898_BS2_6TQ 5 /*!< 6 time quantum */
+#define ISO11898_BS2_7TQ 6 /*!< 7 time quantum */
+#define ISO11898_BS2_8TQ 7 /*!< 8 time quantum */
+
+#define ISO11898_ID_STANDARD 0 /*!< standard ID */
+#define ISO11898_ID_EXTENDED 1 /*!< extended ID */
+
+#define ISO11898_RTR_DATA   0 /*!< data frame */
+#define ISO11898_RTR_REMOTE 1 /*!< remote frame */
+
+/** @defgroup ISO11898_INTSTS iso11898 interrupt status definition
+  * @{
+  */
+#define ISO11898_INTSTS_RX               (1 << 0)
+#define ISO11898_INTSTS_TX               (1 << 1)
+#define ISO11898_INTSTS_ERROR_WARNING    (1 << 2)
+#define ISO11898_INTSTS_DATA_OVERRUN     (1 << 3)
+#define ISO11898_INTSTS_ERROR_PASSIVE    (1 << 5)
+#define ISO11898_INTSTS_ARBITRATION_LOST (1 << 6)
+#define ISO11898_INTSTS_BUS_ERROR        (1 << 7)
+/**
+  * @}
+  */
+
+#define ISO11898_STATUS_RX_NOT_EMPTY  (1 << 0)
+#define ISO11898_STATUS_RX_OVERRUN    (1 << 1)
+#define ISO11898_STATUS_TX_AVAILABLE  (1 << 2)
+#define ISO11898_STATUS_TX_COMPLETE   (1 << 3)
+#define ISO11898_STATUS_RX_RECEIVING  (1 << 4)
+#define ISO11898_STATUS_TX_SENDING    (1 << 5)
+#define ISO11898_STATUS_ERROR_COUNTER (1 << 6)
+#define ISO11898_STATUS_BUS_OFF       (1 << 7)
+
+#define ISO11898_FILTER_TYPE_SINGLE 0
+#define ISO11898_FILTER_TYPE_DUAL   1
+
+struct bflb_iso11898_config_s {
+    uint8_t prescaler; /*!< specifies the length of a time quantum, ranges from 1 to 63, tq=tclk*2*(prescaler+1) */
+    uint8_t mode;      /*!< specifies the CAN operating mode. @ref ISO11898_MODE_XXX */
+    uint8_t sample;    /*!< specifies the number of sample times. @ref ISO11898_SAMPLE_XXX */
+    uint8_t sjw;       /*!< specifies the maximum number of time quanta the ISO11898 hardware is allowed to lengthen or shorten a bit to perform resynchronization. @ref ISO11898_SJW_XXX */
+    uint8_t bs1;       /*!< specifies the number of time quanta in Bit Segment 1. @ref ISO11898_BS1_XXX */
+    uint8_t bs2;       /*!< specifies the number of time quanta in Bit Segment 2. @ref ISO11898_BS2_XXX */
+};
+
+struct bflb_iso11898_msg_s {
+    uint32_t std_id; /*!< specifies the standard identifier, this parameter can be a value between 0 to 0x7FF */
+    uint32_t ext_id; /*!< specifies the extended identifier, this parameter can be a value between 0 to 0x1FFFFFFF */
+    uint8_t id_type; /*!< specifies the type of identifier for the message that will be send or received. @ref ISO11898_ID_XXX */
+    uint8_t rtr;     /*!< specifies the type of frame for the message that will be send or received, @ref ISO11898_RTR_XXX */
+    uint8_t dlc;     /*!< specifies the length of the frame that will be send or received, this parameter can be a value between 0 to 8 */
+    uint8_t data[8]; /*!< contains the data to be send or received, it ranges from 0 to 0xFF */
+};
+
+struct bflb_iso11898_filter_s {
+    uint8_t filter_type;
+    uint8_t code0;
+    uint8_t code1;
+    uint8_t code2;
+    uint8_t code3;
+    uint8_t mask0;
+    uint8_t mask1;
+    uint8_t mask2;
+    uint8_t mask3;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] config
+ */
+void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_iso11898_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ */
+void bflb_iso11898_abort_send(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] msg
+ * @param [in] timeout
+ * @return int8_t
+ */
+int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] msg
+ * @param [in] timeout
+ * @return int8_t
+ */
+int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mode
+ */
+void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint8_t
+ */
+uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint8_t
+ */
+uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] filter
+ */
+void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mask
+ */
+void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mask
+ */
+void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] mask
+ */
+void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @return uint32_t
+ */
+uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev);
+
+/**
+ * @brief
+ *
+ * @param [in] dev
+ * @param [in] cmd
+ * @param [in] arg
+ * @return int
+ */
+int bflb_iso11898_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_kys.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_kys.h
new file mode 100755
index 0000000000..677aff3364
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_kys.h
@@ -0,0 +1,53 @@
+#ifndef _BFLB_KYS_H
+#define _BFLB_KYS_H
+
+#include "bflb_core.h"
+
+struct bflb_kys_config_s {
+    uint8_t col;           /* Col of keyboard,max:8 */
+    uint8_t row;           /* Row of keyboard,max:8 */
+    uint8_t deglitch_en;   /* Disable deglitch function */
+    uint8_t deglitch_cnt;  /* Deglitch count */
+    uint8_t idle_duration; /* Idle duration between column scans */
+    uint8_t ghost_en;      /* Disable ghost key event detection */
+};
+
+/* keyscan interrupt enable define */
+#if defined(BL702)
+#define KEYSCAN_INT_EN (0x1 << 0)
+#else
+#define KEYSCAN_INT_EN_DONE          (0x1 << 7)
+#define KEYSCAN_INT_EN_FIFOFULL      (0x1 << 8)
+#define KEYSCAN_INT_EN_FIFOHALF      (0x1 << 9)
+#define KEYSCAN_INT_EN_FIFOQUARTER   (0x1 << 10)
+#define KEYSCAN_INT_EN_FIFO_NONEMPTY (0x1 << 11)
+#define KEYSCAN_INT_EN_GHOST         (0x1 << 12)
+#endif
+
+/* keyscan interrupt clear */
+#if defined(BL702L)
+#define KEYSCAN_INT_CLR_DONE  (0x1 << 7)
+#define KEYSCAN_INT_CLR_FIFO  (0x1 << 8)
+#define KEYSCAN_INT_CLR_GHOST (0x1 << 12)
+#endif
+
+#if defined(BL702)
+/* keyscan keycode status and clear */
+#define KEYSCAN_STS_KEYCODE0 (0x1 << 0)
+#define KEYSCAN_STS_KEYCODE1 (0x1 << 1)
+#define KEYSCAN_STS_KEYCODE2 (0x1 << 2)
+#define KEYSCAN_STS_KEYCODE3 (0x1 << 3)
+#endif
+
+void bflb_kys_init(struct bflb_device_s *dev, const struct bflb_kys_config_s *config);
+void bflb_kys_enable(struct bflb_device_s *dev);
+void bflb_kys_disable(struct bflb_device_s *dev);
+void bflb_kys_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable);
+void bflb_kys_int_clear(struct bflb_device_s *dev, uint32_t flag);
+uint32_t bflb_kys_get_int_status(struct bflb_device_s *dev);
+#if defined(BL702L)
+void bflb_kys_get_fifo_info(struct bflb_device_s *dev, uint8_t *fifo_head, uint8_t *fifo_tail, uint8_t *fifo_valid_cnt);
+#endif
+uint8_t bflb_kys_read_keyvalue(struct bflb_device_s *dev, uint8_t index);
+
+#endif // _BFLB_KYS_H
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_l1c.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_l1c.h
new file mode 100755
index 0000000000..7d15367ff1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_l1c.h
@@ -0,0 +1,98 @@
+#ifndef _BFLB_L1C_H
+#define _BFLB_L1C_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup L1C
+  * @{
+  */
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_icache_enable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_icache_disable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_icache_invalid_all(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_enable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_disable(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_clean_all(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_invalidate_all(void);
+
+/**
+ * @brief
+ *
+ */
+void bflb_l1c_dcache_clean_invalidate_all(void);
+
+/**
+ * @brief
+ *
+ * @param [in] addr
+ * @param [in] size
+ */
+void bflb_l1c_dcache_clean_range(void *addr, uint32_t size);
+
+/**
+ * @brief
+ *
+ * @param [in] addr
+ * @param [in] size
+ */
+void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size);
+
+/**
+ * @brief
+ *
+ * @param [in] addr
+ * @param [in] size
+ */
+void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size);
+
+void bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high);
+uint32_t bflb_l1c_miss_count_get(void);
+void bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en);
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_list.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_list.h
new file mode 100755
index 0000000000..7ad2245a78
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_list.h
@@ -0,0 +1,270 @@
+/**
+ * @file bflb_list.h
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#ifndef _BFLB_LIST_H
+#define _BFLB_LIST_H
+
+#include "string.h"
+#include "stdint.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * container_of - return the member address of ptr, if the type of ptr is the
+ * struct type.
+ */
+#define bflb_container_of(ptr, type, member) \
+    ((type *)((char *)(ptr) - (unsigned long)(&((type *)0)->member)))
+
+/**
+ * Double List structure
+ */
+struct bflb_dlist_node {
+    struct bflb_dlist_node *next; /**< point to next node. */
+    struct bflb_dlist_node *prev; /**< point to prev node. */
+};
+typedef struct bflb_dlist_node bflb_dlist_t; /**< Type for lists. */
+
+/**
+ * @brief initialize a list
+ *
+ * @param l list to be initialized
+ */
+static inline void bflb_dlist_init(bflb_dlist_t *l)
+{
+    l->next = l->prev = l;
+}
+
+/**
+ * @brief insert a node after a list
+ *
+ * @param l list to insert it
+ * @param n new node to be inserted
+ */
+static inline void bflb_dlist_insert_after(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+    l->next->prev = n;
+    n->next = l->next;
+
+    l->next = n;
+    n->prev = l;
+}
+
+/**
+ * @brief insert a node before a list
+ *
+ * @param n new node to be inserted
+ * @param l list to insert it
+ */
+static inline void bflb_dlist_insert_before(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+    l->prev->next = n;
+    n->prev = l->prev;
+
+    l->prev = n;
+    n->next = l;
+}
+
+/**
+ * @brief remove node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void bflb_dlist_remove(bflb_dlist_t *n)
+{
+    n->next->prev = n->prev;
+    n->prev->next = n->next;
+
+    n->next = n->prev = n;
+}
+
+/**
+ * @brief move node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void bflb_dlist_move_head(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+    bflb_dlist_remove(n);
+    bflb_dlist_insert_after(l, n);
+}
+
+/**
+ * @brief move node from list.
+ * @param n the node to remove from the list.
+ */
+static inline void bflb_dlist_move_tail(bflb_dlist_t *l, bflb_dlist_t *n)
+{
+    bflb_dlist_remove(n);
+    bflb_dlist_insert_before(l, n);
+}
+
+/**
+ * @brief tests whether a list is empty
+ * @param l the list to test.
+ */
+static inline int bflb_dlist_isempty(const bflb_dlist_t *l)
+{
+    return l->next == l;
+}
+
+/**
+ * @brief get the list length
+ * @param l the list to get.
+ */
+static inline unsigned int bflb_dlist_len(const bflb_dlist_t *l)
+{
+    unsigned int len = 0;
+    const bflb_dlist_t *p = l;
+
+    while (p->next != l) {
+        p = p->next;
+        len++;
+    }
+
+    return len;
+}
+
+/**
+ * @brief initialize a dlist object
+ */
+#define DLIST_OBJECT_INIT(object) \
+    {                             \
+        &(object), &(object)      \
+    }
+/**
+ * @brief initialize a dlist object
+ */
+#define DLIST_DEFINE(list) \
+    bflb_dlist_t list = { &(list), &(list) }
+
+/**
+ * @brief get the struct for this entry
+ * @param node the entry point
+ * @param type the type of structure
+ * @param member the name of list in structure
+ */
+#define bflb_dlist_entry(node, type, member) \
+    bflb_container_of(node, type, member)
+
+/**
+ * dlist_first_entry - get the first element from a list
+ * @ptr:    the list head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define bflb_dlist_first_entry(ptr, type, member) \
+    bflb_dlist_entry((ptr)->next, type, member)
+/**
+ * dlist_first_entry_or_null - get the first element from a list
+ * @ptr:    the list head to take the element from.
+ * @type:   the type of the struct this is embedded in.
+ * @member: the name of the list_struct within the struct.
+ *
+ * Note, that list is expected to be not empty.
+ */
+#define bflb_dlist_first_entry_or_null(ptr, type, member) \
+    (bflb_dlist_isempty(ptr) ? NULL : bflb_dlist_first_entry(ptr, type, member))
+
+/**
+ * dlist_for_each - iterate over a list
+ * @pos:    the dlist_t * to use as a loop cursor.
+ * @head:   the head for your list.
+ */
+#define bflb_dlist_for_each(pos, head) \
+    for (pos = (head)->next; pos != (head); pos = pos->next)
+
+/**
+ * dlist_for_each_prev - iterate over a list
+ * @pos:    the dlist_t * to use as a loop cursor.
+ * @head:   the head for your list.
+ */
+#define bflb_dlist_for_each_prev(pos, head) \
+    for (pos = (head)->prev; pos != (head); pos = pos->prev)
+
+/**
+ * dlist_for_each_safe - iterate over a list safe against removal of list entry
+ * @pos:    the dlist_t * to use as a loop cursor.
+ * @n:      another dlist_t * to use as temporary storage
+ * @head:   the head for your list.
+ */
+#define bflb_dlist_for_each_safe(pos, n, head)                  \
+    for (pos = (head)->next, n = pos->next; pos != (head); \
+         pos = n, n = pos->next)
+
+#define bflb_dlist_for_each_prev_safe(pos, n, head)             \
+    for (pos = (head)->prev, n = pos->prev; pos != (head); \
+         pos = n, n = pos->prev)
+/**
+ * dlist_for_each_entry  -   iterate over list of given type
+ * @pos:    the type * to use as a loop cursor.
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry(pos, head, member)                 \
+    for (pos = bflb_dlist_entry((head)->next, typeof(*pos), member); \
+         &pos->member != (head);                                \
+         pos = bflb_dlist_entry(pos->member.next, typeof(*pos), member))
+
+/**
+ * dlist_for_each_entry_reverse  -   iterate over list of given type
+ * @pos:    the type * to use as a loop cursor.
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry_reverse(pos, head, member)         \
+    for (pos = bflb_dlist_entry((head)->prev, typeof(*pos), member); \
+         &pos->member != (head);                                \
+         pos = bflb_dlist_entry(pos->member.prev, typeof(*pos), member))
+
+/**
+ * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos:    the type * to use as a loop cursor.
+ * @n:      another type * to use as temporary storage
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry_safe(pos, n, head, member)          \
+    for (pos = bflb_dlist_entry((head)->next, typeof(*pos), member),  \
+        n = bflb_dlist_entry(pos->member.next, typeof(*pos), member); \
+         &pos->member != (head);                                 \
+         pos = n, n = bflb_dlist_entry(n->member.next, typeof(*n), member))
+
+/**
+ * dlist_for_each_entry_safe - iterate over list of given type safe against removal of list entry
+ * @pos:    the type * to use as a loop cursor.
+ * @n:      another type * to use as temporary storage
+ * @head:   the head for your list.
+ * @member: the name of the list_struct within the struct.
+ */
+#define bflb_dlist_for_each_entry_safe_reverse(pos, n, head, member)  \
+    for (pos = bflb_dlist_entry((head)->prev, typeof(*pos), field),   \
+        n = bflb_dlist_entry(pos->member.prev, typeof(*pos), member); \
+         &pos->member != (head);                                 \
+         pos = n, n = bflb_dlist_entry(pos->member.prev, typeof(*pos), member))
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h
new file mode 100755
index 0000000000..7cde648d49
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mjpeg.h
@@ -0,0 +1,251 @@
+#ifndef _BFLB_MJPEG_H
+#define _BFLB_MJPEG_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup MJPEG
+  * @{
+  */
+
+/** @defgroup MJPEG_FORMAT mjpeg format definition
+  * @{
+  */
+#define MJPEG_FORMAT_YUV422_YUYV   0
+#define MJPEG_FORMAT_YUV422_YVYU   1
+#define MJPEG_FORMAT_YUV422_UYVY   2
+#define MJPEG_FORMAT_YUV422_VYUY   3
+#define MJPEG_FORMAT_YUV422SP_NV16 4
+#define MJPEG_FORMAT_YUV422SP_NV61 5
+#define MJPEG_FORMAT_YUV420SP_NV12 6
+#define MJPEG_FORMAT_YUV420SP_NV21 7
+#define MJPEG_FORMAT_GRAY          8
+/**
+  * @}
+  */
+
+/** @defgroup MJPEG_INTSTS mjpeg interrupt status definition
+  * @{
+  */
+#define MJPEG_INTSTS_ONE_FRAME     (1 << 4)
+/**
+  * @}
+  */
+
+/** @defgroup MJPEG_INTCLR mjpeg interrupt clear definition
+  * @{
+  */
+#define MJPEG_INTCLR_ONE_FRAME     (1 << 8)
+/**
+  * @}
+  */
+
+/** @defgroup MJPEG_CMD mjpeg feature control cmd definition
+  * @{
+  */
+#define MJPEG_CMD_SET_INPUTADDR0   0x00
+#define MJPEG_CMD_SET_INPUTADDR1   0x01
+/**
+  * @}
+  */
+
+#define MJPEG_MAX_FRAME_COUNT      4
+
+/**
+ * @brief MJPEG configuration structure
+ *
+ * @param format            MJPEG format, use @ref MJPEG_FORMAT
+ * @param resolution_x      MJPEG width, must be a multiple of 8 or a multiple of 16
+ * @param resolution_y      MJPEG higth, must be a multiple of 8 or a multiple of 16
+ * @param input_bufaddr0    MJPEG input buffer address 0 for yy , must be align 16
+ * @param input_bufaddr1    MJPEG input buffer address 0 for yy , must be align 16
+ * @param output_bufaddr    MJPEG output buffer address , must be align 16
+ * @param output_bufsize    MJPEG output buffer size, must be larger than resolution_x*resolution_y*2*MJPEG_MAX_FRAME_COUNT
+ */
+struct bflb_mjpeg_config_s {
+    uint8_t format;
+    uint8_t quality;
+    uint16_t rows;
+    uint16_t resolution_x;
+    uint16_t resolution_y;
+    uint32_t input_bufaddr0;
+    uint32_t input_bufaddr1;
+    uint32_t output_bufaddr;
+    uint32_t output_bufsize;
+    uint16_t *input_yy_table;
+    uint16_t *input_uv_table;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize mjpeg.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save mjpeg config
+ */
+void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s *config);
+
+/**
+ * @brief Start mjpeg compression with camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop mjpeg compression with camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Start mjpeg compression without camera.
+ *
+ * @param [in] dev device handle
+ * @param [in] frame_count frame count to compress
+ */
+void bflb_mjpeg_sw_run(struct bflb_device_s *dev, uint8_t frame_count);
+
+/**
+ * @brief Start mjpeg kick mode compression without camera.
+ *
+ * @param [in] dev device handle
+ * @param [in] kick_count kick block horizontal count to compress
+ */
+void bflb_mjpeg_kick_run(struct bflb_device_s *dev, uint16_t kick_count);
+
+/**
+ * @brief Stop mjpeg kick mode compression without camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_kick_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief kick one times compression without camera.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_kick(struct bflb_device_s *dev);
+/**
+ * @brief Enable or disable mjpeg one frame compression completion interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_mjpeg_tcint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Enable or disable mjpeg error interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] mask true means disable, false means enable
+ */
+void bflb_mjpeg_errint_mask(struct bflb_device_s *dev, bool mask);
+
+/**
+ * @brief Get mjpeg interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status
+ */
+uint32_t bflb_mjpeg_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear mjpeg interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value
+ */
+void bflb_mjpeg_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Get number of frame count that has compressed.
+ *
+ * @param [in] dev device handle
+ * @return compressed frame count
+ */
+uint8_t bflb_mjpeg_get_frame_count(struct bflb_device_s *dev);
+
+/**
+ * @brief Drop one frame that has compressed.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_mjpeg_pop_one_frame(struct bflb_device_s *dev);
+
+/**
+ * @brief Get one frame information.
+ *
+ * @param [in] dev device handle
+ * @param [in] pic pointer to save frame address.
+ * @return frame length
+ */
+uint32_t bflb_mjpeg_get_frame_info(struct bflb_device_s *dev, uint8_t **pic);
+
+/**
+ * @brief Calculate jpeg quantize table.
+ *
+ * @param [in] quality image quality
+ * @param [in] input_table pointer to save input table
+ * @param [in] output_table pointer to save output table
+ */
+void bflb_mjpeg_calculate_quantize_table(uint8_t quality, uint16_t *input_table, uint16_t *output_table);
+
+/**
+ * @brief Fill quantize table into mjpeg register.
+ *
+ * @param [in] dev device handle
+ * @param [in] input_yy yy quantize table
+ * @param [in] input_uv uv quantize table
+ */
+void bflb_mjpeg_fill_quantize_table(struct bflb_device_s *dev, uint16_t *input_yy, uint16_t *input_uv);
+
+/**
+ * @brief Fill jpeg header into mjpeg register and enable hardware auto adding jpeg tail.
+ *
+ * @param [in] dev device handle
+ * @param [in] header pointer to jpeg header
+ * @param [in] header_len jpeg header length
+ */
+void bflb_mjpeg_fill_jpeg_header_tail(struct bflb_device_s *dev, uint8_t *header, uint32_t header_len);
+
+/**
+ * @brief Set mjpeg input when uses camera with yuv402sp.
+ *
+ * @param [in] dev device handle
+ * @param [in] yy camera id for yy
+ * @param [in] uv camera id for uv
+ */
+void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, uint8_t uv);
+
+/**
+ * @brief Control mjpeg feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_mjpeg_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mtimer.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mtimer.h
new file mode 100755
index 0000000000..447820d6f9
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_mtimer.h
@@ -0,0 +1,74 @@
+#ifndef _BFLB_MTIMER_H
+#define _BFLB_MTIMER_H
+
+#include "stdint.h"
+#include "stdio.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup MTIMER
+  * @{
+  */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Config mtimer interrupt.
+ *
+ * @param [in] ticks ticks to invoke interrupt.
+ * @param [in] interruptfun interrupt callback
+ */
+void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void));
+
+/**
+ * @brief Get mtimer current frequence.
+ *
+ * @return frequence
+ */
+uint32_t bflb_mtimer_get_freq(void);
+
+/**
+ * @brief Mtimer delay with ms.
+ *
+ * @param [in] time delay time
+ */
+void bflb_mtimer_delay_ms(uint32_t time);
+
+/**
+ * @brief Mtimer delay with us.
+ *
+ * @param [in] time delay time
+ */
+void bflb_mtimer_delay_us(uint32_t time);
+
+/**
+ * @brief Get current mtimer time with us.
+ *
+ * @return time with us
+ */
+uint64_t bflb_mtimer_get_time_us();
+
+/**
+ * @brief Get current mtimer time with ms.
+ *
+ * @return time with ms
+ */
+uint64_t bflb_mtimer_get_time_ms();
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h
new file mode 100755
index 0000000000..fcf1768df9
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pec_ip.h
@@ -0,0 +1,189 @@
+#ifndef __BFLB_PEC_IP_H__
+#define __BFLB_PEC_IP_H__
+
+#include "bflb_core.h"
+
+#define PEC0                    0
+#define PEC_MAX                 1
+
+#define PEC_SM0                 0
+#define PEC_SM1                 1
+#define PEC_SM2                 2
+#define PEC_SM3                 3
+#define PEC_SM_MAX              4
+
+#define PEC_FLAG_0              (1 << 0)
+#define PEC_FLAG_1              (1 << 1)
+#define PEC_FLAG_2              (1 << 2)
+#define PEC_FLAG_3              (1 << 3)
+#define PEC_FLAG_4              (1 << 4)
+#define PEC_FLAG_5              (1 << 5)
+#define PEC_FLAG_6              (1 << 6)
+#define PEC_FLAG_7              (1 << 7)
+
+#define PEC_IP_NULL             0
+#define PEC_IP_PWM              1
+#define PEC_IP_UART_TX          2
+#define PEC_IP_UART_RX          3
+#define PEC_IP_SPI              4
+#define PEC_IP_I2C              5
+#define PEC_IP_WS2812           6
+#define PEC_IP_JTAG             7
+#define PEC_IP_DPI              8
+#define PEC_IP_LA               9
+#define PEC_IP_SEG              10
+#define PEC_IP_DBI_B            11
+#define PEC_IP_4xI2S            12
+
+#define PEC_ERR_OK              0
+#define PEC_ERR_NOT_SUPPORT     1
+#define PEC_ERR_PIN_CONFLICT    2
+#define PEC_ERR_SM_LACK         3
+#define PEC_ERR_CODE_SPACE_LACK 4
+#define PEC_ERR_FLAG_LACK       5
+
+extern uint32_t bflb_pec_get_tx_fifo_addr(uint8_t pec_id, uint8_t sm_id);
+extern uint32_t bflb_pec_get_rx_fifo_addr(uint8_t pec_id, uint8_t sm_id);
+extern void bflb_pec_dma_tx_enable(uint8_t pec_id, uint8_t sm_id, uint8_t enable);
+extern void bflb_pec_dma_rx_enable(uint8_t pec_id, uint8_t sm_id, uint8_t enable);
+
+struct bflb_pec_pwm_s {
+    uint32_t high_cnt; /*!< high level count */
+    uint32_t low_cnt;  /*!< low level count */
+    uint16_t div;      /*!< divisor */
+    uint8_t pin;       /*!< PWM output assert pin index */
+    uint8_t pec;
+    uint8_t sm;
+    uint8_t addr;
+};
+
+int bflb_pec_pwm_init(struct bflb_pec_pwm_s *pwm);
+void bflb_pec_pwm_start(struct bflb_pec_pwm_s *pwm);
+void bflb_pec_pwm_stop(struct bflb_pec_pwm_s *pwm);
+
+struct bflb_pec_jtag_s {
+    uint8_t pin_tck;
+    uint8_t pin_tms;
+    uint8_t pin_tdo;
+    uint8_t pin_tdi;
+    uint8_t pec;
+    uint8_t sm;
+    uint8_t addr;
+};
+
+int bflb_pec_jtag_init(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_set_tck(struct bflb_pec_jtag_s *jtag, uint8_t value);
+void bflb_pec_jtag_set_tms(struct bflb_pec_jtag_s *jtag, uint8_t value);
+void bflb_pec_jtag_set_tdi(struct bflb_pec_jtag_s *jtag, uint8_t value);
+int bflb_pec_jtag_get_tdo(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_set_path(struct bflb_pec_jtag_s *jtag, uint32_t path, uint32_t bits);
+void bflb_pec_jtag_select_ir(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_exit_ir(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_select_dr(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_exit_dr(struct bflb_pec_jtag_s *jtag);
+void bflb_pec_jtag_scan_ir(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out, uint8_t *ir_in);
+void bflb_pec_jtag_scan_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_out, uint8_t *dr_in);
+void bflb_pec_jtag_scan(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out, uint8_t *ir_in, uint8_t dr_bits, uint8_t *dr_out, uint8_t *dr_in);
+void bflb_pec_jtag_write_ir(struct bflb_pec_jtag_s *jtag, uint8_t ir_bits, uint8_t *ir_out);
+void bflb_pec_jtag_write_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_out);
+void bflb_pec_jtag_read_dr(struct bflb_pec_jtag_s *jtag, uint8_t dr_bits, uint8_t *dr_in);
+
+/* pixel format */
+#define PEC_DBI_B_PIXEL_FORMAT_NRGB8888 1 /* 32-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_NBGR8888 2 /* 32-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_RGB888   3 /* 24-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_BGR888   4 /* 24-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_RGB565   5 /* 16-bit */
+#define PEC_DBI_B_PIXEL_FORMAT_BGR565   6 /* 16-bit */
+
+/* transmit mode */
+#define PEC_DBI_TRANSMIT_MODE_CMD       0
+#define PEC_DBI_TRANSMIT_MODE_PIXEL     1
+
+struct bflb_pec_dbi_b_s {
+    uint32_t clk_src;
+    uint32_t clk;
+    uint8_t pixel_format;
+    uint8_t pin_dc;
+    uint8_t pin_wr;
+    uint8_t pin_data;
+    uint8_t pec;
+    uint8_t sm;
+    uint8_t addr;
+    uint8_t fifo_threshold;
+};
+
+int bflb_pec_dbi_b_init(struct bflb_pec_dbi_b_s *dbi_b);
+uint32_t bflb_pec_dbi_b_build_head(struct bflb_pec_dbi_b_s *dbi_b, uint8_t transmit_mode, uint8_t cmd, size_t data_num);
+uint32_t bflb_pec_dbi_b_get_fifo_address(struct bflb_pec_dbi_b_s *dbi_b);
+int bflb_pec_dbi_b_get_fifo_cnt(struct bflb_pec_dbi_b_s *dbi_b);
+int bflb_pec_dbi_b_dma_enable(struct bflb_pec_dbi_b_s *dbi_b, bool en);
+
+/* Signal polarity selection */
+#define V_SYNC_SINGLE_POL 0
+#define H_SYNC_SINGLE_POL 0
+#define DE_SINGLE_POL     1
+
+struct bflb_pec_dpi_s {
+    uint16_t width;
+    uint16_t height;
+
+    uint16_t hsw;
+    uint16_t hbp;
+    uint16_t hfp;
+
+    uint16_t vsw;
+    uint16_t vbp;
+    uint16_t vfp;
+
+    bool data_latch_mode;
+    bool de_sig_enable;
+    bool de_sig_polarity;
+    bool v_sync_sig_polarity;
+    bool h_sync_sig_polarity;
+
+    uint32_t *invalid_row_para;
+
+    uint16_t frame_rate;
+    uint16_t data_format;
+
+    uint8_t pin_clk;
+    uint8_t pin_hs;
+    uint8_t pin_data;
+    uint8_t pec;
+    uint8_t sm;
+};
+
+int bflb_pec_dpi_init(struct bflb_pec_dpi_s *dpi);
+
+#define PEC_I2S_SAMPLE_RATE_24KHZ      1
+#define PEC_I2S_SAMPLE_RATE_48KHZ      2
+#define PEC_I2S_SAMPLE_RATE_96KHZ      3
+
+#define PEC_I2S_DATA_FORMAT_BIT24IN32R 0
+#define PEC_I2S_DATA_FORMAT_BIT16      1
+#define PEC_I2S_DATA_FORMAT_BIT32      2
+
+struct bflb_pec_i2sx4_s {
+    uint8_t sample_rate;
+    uint8_t data_format;
+    uint8_t pin_bck;
+    uint8_t pin_ws;
+    uint8_t pin_d0;
+    uint8_t pin_d1;
+    uint8_t pin_d2;
+    uint8_t pin_d3;
+    uint8_t pec;
+    // uint8_t sm;
+    // uint8_t addr;
+    uint8_t flag;
+};
+
+int bflb_pec_i2sx4_init(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_enable(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_disable(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_rx_start(struct bflb_pec_i2sx4_s *i2s);
+void bflb_pec_i2sx4_rx_stop(struct bflb_pec_i2sx4_s *i2s);
+uint8_t bflb_pec_i2sx4_get_data(struct bflb_pec_i2sx4_s *i2s, uint8_t ch, uint32_t *data);
+
+#endif /* __BFLB_PEC_IP_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v1.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v1.h
new file mode 100755
index 0000000000..d5ee6ed63e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v1.h
@@ -0,0 +1,189 @@
+#ifndef _BFLB_PWM_V1_H
+#define _BFLB_PWM_V2_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup PWM_V1
+  * @{
+  */
+
+/** @defgroup PWM_CHANNEL pwm channel definition
+  * @{
+  */
+#define PWM_CH0       0
+#define PWM_CH1       1
+#define PWM_CH2       2
+#define PWM_CH3       3
+#define PWM_CH4       4
+#define PWM_V1_CH_MAX 5
+/**
+  * @}
+  */
+
+/** @defgroup PWM_INTSTS pwm interrupt status definition
+  * @{
+  */
+#define PWM_INTSTS_REPT_CH0 (1 << 0)
+#define PWM_INTSTS_REPT_CH1 (1 << 1)
+#define PWM_INTSTS_REPT_CH2 (1 << 2)
+#define PWM_INTSTS_REPT_CH3 (1 << 3)
+#define PWM_INTSTS_REPT_CH4 (1 << 4)
+/**
+  * @}
+  */
+
+/** @defgroup PWM_INTCLR pwm interrupt clear definition
+  * @{
+  */
+#define PWM_INTCLR_REPT_CH0 (1 << 8)
+#define PWM_INTCLR_REPT_CH1 (1 << 9)
+#define PWM_INTCLR_REPT_CH2 (1 << 10)
+#define PWM_INTCLR_REPT_CH3 (1 << 11)
+#define PWM_INTCLR_REPT_CH4 (1 << 12)
+/**
+  * @}
+  */
+
+/** @defgroup PWM_CMD pwm feature control cmd definition
+  * @{
+  */
+#define PWM_CMD_SET_STOP_MODE      (0x01)
+#define PWM_CMD_SET_OUT_INVERT     (0x02)
+#define PWM_CMD_SET_SW_MODE        (0x03)
+#define PWM_CMD_SET_SW_FORCE_VALUE (0x04)
+#define PWM_CMD_SET_REPT_COUNT     (0x05)
+/**
+  * @}
+  */
+
+/** @defgroup PWM_STOP_MODE pwm stop mode definition
+  * @{
+  */
+#define PWM_STOP_MODE_ABRUPT   0
+#define PWM_STOP_MODE_GRACEFUL 1
+/**
+  * @}
+  */
+
+/**
+ * @brief PWM configuration structure
+ *
+ * @param clk_source PWM clock source, use @ref BFLB_SYSTEM_CLOCK
+ * @param clk_div    PWM clock dividor, should be in 1~65535
+ * @param period     PWM period count, should be in 2~65535
+ */
+struct bflb_pwm_v1_channel_config_s {
+    uint8_t clk_source;
+    uint16_t clk_div;
+    uint16_t period;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize pwm channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] config pointer to save pwm channel config
+ */
+void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struct bflb_pwm_v1_channel_config_s *config);
+
+/**
+ * @brief Deinitialize pwm channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v1_channel_deinit(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Start pwm channel output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Stop pwm channel output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Set pwm channel period to change pwm frequence. Frequcence(hz) = pwm source clock /div/period.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] period pwm period
+ */
+void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t period);
+
+/**
+ * @brief Set pwm dutycycle. Dutycycle(%) = (high_threhold - low_threhold)/period * 100%.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] low_threhold pwm low threhold
+ * @param [in] high_threhold pwm high threhold
+ */
+void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
+
+/**
+ * @brief Enable pwm interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] enable true means enable, otherwise disable.
+ */
+void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable);
+
+/**
+ * @brief Get pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref PWM_INTSTS
+ */
+uint32_t bflb_pwm_v1_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref PWM_INTCLR
+ */
+void bflb_pwm_v1_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] cmd feature command, use @ref PWM_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v2.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v2.h
new file mode 100755
index 0000000000..88ebe74620
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_pwm_v2.h
@@ -0,0 +1,309 @@
+#ifndef _BFLB_PWM_V2_H
+#define _BFLB_PWM_V2_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup PWM_V2
+  * @{
+  */
+
+/** @defgroup PWM_CHANNEL pwm channel definition
+  * @{
+  */
+#define PWM_CH0       0
+#define PWM_CH1       1
+#define PWM_CH2       2
+#define PWM_CH3       3
+#define PWM_V2_CH_MAX 4
+/**
+  * @}
+  */
+
+/** @defgroup PWM_POLARITY pwm polarity definition
+  * @{
+  */
+#define PWM_POLARITY_ACTIVE_LOW  0
+#define PWM_POLARITY_ACTIVE_HIGH 1
+/**
+  * @}
+  */
+
+/** @defgroup PWM_STATE pwm state definition
+  * @{
+  */
+#define PWM_STATE_INACTIVE 0
+#define PWM_STATE_ACTIVE   1
+/**
+  * @}
+  */
+
+/** @defgroup PWM_TRIG_SDC_SRC pwm trigger adc source definition
+  * @{
+  */
+#define PWM_TRIG_ADC_SRC_CH0_L  0
+#define PWM_TRIG_ADC_SRC_CH0_H  1
+#define PWM_TRIG_ADC_SRC_CH1_L  2
+#define PWM_TRIG_ADC_SRC_CH1_H  3
+#define PWM_TRIG_ADC_SRC_CH2_L  4
+#define PWM_TRIG_ADC_SRC_CH2_H  5
+#define PWM_TRIG_ADC_SRC_CH3_L  6
+#define PWM_TRIG_ADC_SRC_CH3_H  7
+#define PWM_TRIG_ADC_SRC_PERIOD 8
+#define PWM_TRIG_ADC_SRC_NONE   0xF
+/**
+  * @}
+  */
+
+/** @defgroup PWM_INTEN pwm interrupt enable definition
+  * @{
+  */
+#define PWM_INTEN_CH0_L  (1 << 0)
+#define PWM_INTEN_CH0_H  (1 << 1)
+#define PWM_INTEN_CH1_L  (1 << 2)
+#define PWM_INTEN_CH1_H  (1 << 3)
+#define PWM_INTEN_CH2_L  (1 << 4)
+#define PWM_INTEN_CH2_H  (1 << 5)
+#define PWM_INTEN_CH3_L  (1 << 6)
+#define PWM_INTEN_CH3_H  (1 << 7)
+#define PWM_INTEN_PERIOD (1 << 8)
+#define PWM_INTEN_BRAKE  (1 << 9)
+#define PWM_INTEN_REPT   (1 << 10)
+/**
+  * @}
+  */
+
+/** @defgroup PWM_INTSTS pwm interrupt status definition
+  * @{
+  */
+#define PWM_INTSTS_CH0_L  (1 << 0)
+#define PWM_INTSTS_CH0_H  (1 << 1)
+#define PWM_INTSTS_CH1_L  (1 << 2)
+#define PWM_INTSTS_CH1_H  (1 << 3)
+#define PWM_INTSTS_CH2_L  (1 << 4)
+#define PWM_INTSTS_CH2_H  (1 << 5)
+#define PWM_INTSTS_CH3_L  (1 << 6)
+#define PWM_INTSTS_CH3_H  (1 << 7)
+#define PWM_INTSTS_PERIOD (1 << 8)
+#define PWM_INTSTS_BRAKE  (1 << 9)
+#define PWM_INTSTS_REPT   (1 << 10)
+/**
+  * @}
+  */
+
+/** @defgroup PWM_INTCLR pwm interrupt clear definition
+  * @{
+  */
+#define PWM_INTCLR_CH0_L  (1 << 0)
+#define PWM_INTCLR_CH0_H  (1 << 1)
+#define PWM_INTCLR_CH1_L  (1 << 2)
+#define PWM_INTCLR_CH1_H  (1 << 3)
+#define PWM_INTCLR_CH2_L  (1 << 4)
+#define PWM_INTCLR_CH2_H  (1 << 5)
+#define PWM_INTCLR_CH3_L  (1 << 6)
+#define PWM_INTCLR_CH3_H  (1 << 7)
+#define PWM_INTCLR_PERIOD (1 << 8)
+#define PWM_INTCLR_BRAKE  (1 << 9)
+#define PWM_INTCLR_REPT   (1 << 10)
+/**
+  * @}
+  */
+
+/** @defgroup PWM_CMD pwm feature control cmd definition
+  * @{
+  */
+#define PWM_CMD_SET_TRIG_ADC_SRC       (0x01)
+#define PWM_CMD_SET_EXT_BRAKE_POLARITY (0x02)
+#define PWM_CMD_SET_EXT_BRAKE_ENABLE   (0x03)
+#define PWM_CMD_SET_SW_BRAKE_ENABLE    (0x04)
+#define PWM_CMD_SET_STOP_ON_REPT       (0x05)
+#define PWM_CMD_SET_REPT_COUNT         (0x06)
+/**
+  * @}
+  */
+
+/**
+ * @brief PWM channel configuration structure
+ *
+ * @param positive_polarity    PWM posotive channel polarity, use @ref PWM_POLARITY
+ * @param negative_polarity    PWM negative channel polarity, use @ref PWM_POLARITY
+ * @param positive_stop_state  PWM posotive channel state when stop, use @ref PWM_STATE
+ * @param negative_stop_state  PWM negative channel state when stop, use @ref PWM_STATE
+ * @param positive_brake_state PWM posotive channel state when brake, use @ref PWM_STATE
+ * @param negative_brake_state PWM negative channel state when brake, use @ref PWM_STATE
+ * @param dead_time            PWM channel dead time
+ */
+struct bflb_pwm_v2_channel_config_s {
+    uint8_t positive_polarity;
+    uint8_t negative_polarity;
+    uint8_t positive_stop_state;
+    uint8_t negative_stop_state;
+    uint8_t positive_brake_state;
+    uint8_t negative_brake_state;
+    uint8_t dead_time;
+};
+
+/**
+ * @brief PWM configuration structure
+ *
+ * @param clk_source PWM clock source, use @ref BFLB_SYSTEM_CLOCK
+ * @param clk_div    PWM clock dividor, should be in 1~65535
+ * @param period     PWM period count, should be in 2~65535
+ */
+struct bflb_pwm_v2_config_s {
+    uint8_t clk_source;
+    uint16_t clk_div;
+    uint16_t period;
+};
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Initialize pwm.
+ *
+ * @param [in] dev device handle
+ * @param [in] config pointer to save pwm config
+ */
+void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config_s *config);
+
+/**
+ * @brief Deinitialize pwm.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_pwm_v2_deinit(struct bflb_device_s *dev);
+
+/**
+ * @brief Start pwm output.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_pwm_v2_start(struct bflb_device_s *dev);
+
+/**
+ * @brief Stop pwm output.
+ *
+ * @param [in] dev device handle
+ */
+void bflb_pwm_v2_stop(struct bflb_device_s *dev);
+
+/**
+ * @brief Set pwm period to change pwm frequence. Frequcence(hz) = pwm source clock /div/period.
+ *
+ * @param [in] dev device handle
+ * @param [in] period pwm period
+ */
+void bflb_pwm_v2_set_period(struct bflb_device_s *dev, uint16_t period);
+
+/**
+ * @brief Get pwm frequcency.
+ *
+ * @param [in] dev device handle
+ * @return frequcency
+ */
+float bflb_pwm_v2_get_frequency(struct bflb_device_s *dev);
+
+/**
+ * @brief Config pwm channel.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] config pointer to save pwm channel config
+ */
+void bflb_pwm_v2_channel_init(struct bflb_device_s *dev, uint8_t ch, struct bflb_pwm_v2_channel_config_s *config);
+
+/**
+ * @brief Set pwm dutycycle. Dutycycle(%) = (high_threhold - low_threhold)/period * 100%.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ * @param [in] low_threhold pwm low threhold
+ * @param [in] high_threhold pwm high threhold
+ */
+void bflb_pwm_v2_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold);
+
+/**
+ * @brief Start pwm positive output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_positive_start(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Start pwm negative output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_negative_start(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Stop pwm positive output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_positive_stop(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Stop pwm negative output.
+ *
+ * @param [in] dev device handle
+ * @param [in] ch channel number
+ */
+void bflb_pwm_v2_channel_negative_stop(struct bflb_device_s *dev, uint8_t ch);
+
+/**
+ * @brief Enable pwm interrupt.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_en interrupt type
+ * @param [in] enable true means enable, otherwise disable
+ */
+void bflb_pwm_v2_int_enable(struct bflb_device_s *dev, uint32_t int_en, bool enable);
+
+/**
+ * @brief Get pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @return interrupt status, use @ref PWM_INTSTS
+ */
+uint32_t bflb_pwm_v2_get_intstatus(struct bflb_device_s *dev);
+
+/**
+ * @brief Clear pwm interrupt status.
+ *
+ * @param [in] dev device handle
+ * @param [in] int_clear clear value, use @ref PWM_INTCLR
+ */
+void bflb_pwm_v2_int_clear(struct bflb_device_s *dev, uint32_t int_clear);
+
+/**
+ * @brief Control pwm feature.
+ *
+ * @param [in] dev device handle
+ * @param [in] cmd feature command, use @ref PWM_CMD
+ * @param [in] arg user data
+ * @return A negated errno value on failure.
+ */
+int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h
new file mode 100755
index 0000000000..a8fa56d74b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_rtc.h
@@ -0,0 +1,49 @@
+#ifndef _BFLB_RTC_H
+#define _BFLB_RTC_H
+
+#include "bflb_core.h"
+
+/** @addtogroup LHAL
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */
+
+#define BFLB_RTC_SEC2TIME(s)    (s * 32768)
+#define BFLB_RTC_TIME2SEC(time) (time / 32768)
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * @brief Set rtc alarming time.
+ *
+ * @param [in] dev device handle
+ * @param [in] time alarming time, unit is (1/32768 s)
+ */
+void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time);
+
+/**
+ * @brief Get rtc current time.
+ *
+ * @param [in] dev device handle
+ * @return current rtc running time
+ */
+uint64_t bflb_rtc_get_time(struct bflb_device_s *dev);
+
+#ifdef __cplusplus
+}
+#endif
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sdio2.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sdio2.h
new file mode 100755
index 0000000000..e5cfc65b56
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/bflb_sdio2.h
@@ -0,0 +1,71 @@
+/**
+  ******************************************************************************
+  * @file    bflb_sdio2.h
+  * @version V1.0
+  * @date    2022-09-27
+  * @brief   This file is the low hardware abstraction layer file
+  ******************************************************************************
+  * @attention
+  *
+  * 

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __HARDWARE_CAM_H__
+#define  __HARDWARE_CAM_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CAM_DVP2AXI_CONFIGUE_OFFSET     (0x0)/* dvp2axi_configue */
+#define CAM_DVP2AXI_ADDR_START_OFFSET   (0x4)/* dvp2axi_addr_start */
+#define CAM_DVP2AXI_MEM_BCNT_OFFSET     (0x8)/* dvp2axi_mem_bcnt */
+#define CAM_DVP2AXI_HSYNC_CROP_OFFSET   (0x30)/* dvp2axi_hsync_crop */
+#define CAM_DVP2AXI_VSYNC_CROP_OFFSET   (0x34)/* dvp2axi_vsync_crop */
+#define CAM_DVP2AXI_FRAM_EXM_OFFSET     (0x38)/* dvp2axi_fram_exm */
+#define CAM_FRAME_START_ADDR0_OFFSET    (0x40)/* frame_start_addr0 */
+#define CAM_FRAME_START_ADDR1_OFFSET    (0x48)/* frame_start_addr1 */
+#define CAM_FRAME_START_ADDR2_OFFSET    (0x50)/* frame_start_addr2 */
+#define CAM_FRAME_START_ADDR3_OFFSET    (0x58)/* frame_start_addr3 */
+#if defined(BL702)
+#define CAM_DVP2AXI_FRAME_BCNT_0_OFFSET (0xC)/* dvp2axi_frame_bcnt_0 */
+#define CAM_DVP2AXI_ADDR_START_1_OFFSET (0x10)/* dvp2axi_addr_start_1 */
+#define CAM_DVP2AXI_MEM_BCNT_1_OFFSET   (0x14)/* dvp2axi_mem_bcnt_1 */
+#define CAM_DVP2AXI_FRAME_BCNT_1_OFFSET (0x18)/* dvp2axi_frame_bcnt_1 */
+#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0x1C)/* dvp_status_and_error */
+#define CAM_DVP_FRAME_FIFO_POP_OFFSET   (0x20)/* dvp_frame_fifo_pop */
+#define CAM_SNSR_CONTROL_OFFSET         (0x24)/* snsr_control */
+#define CAM_INT_CONTROL_OFFSET          (0x28)/* int_control */
+#define CAM_FRAME_BYTE_CNT0_0_OFFSET    (0x44)/* frame_byte_cnt0_0 */
+#define CAM_FRAME_BYTE_CNT0_1_OFFSET    (0x4C)/* frame_byte_cnt0_1 */
+#define CAM_FRAME_BYTE_CNT0_2_OFFSET    (0x54)/* frame_byte_cnt0_2 */
+#define CAM_FRAME_BYTE_CNT0_3_OFFSET    (0x5C)/* frame_byte_cnt0_3 */
+#define CAM_FRAME_START_ADDR0_4_OFFSET  (0x60)/* frame_start_addr0_4 */
+#define CAM_FRAME_BYTE_CNT0_4_OFFSET    (0x64)/* frame_byte_cnt0_4 */
+#define CAM_FRAME_START_ADDR0_5_OFFSET  (0x68)/* frame_start_addr0_5 */
+#define CAM_FRAME_BYTE_CNT0_5_OFFSET    (0x6C)/* frame_byte_cnt0_5 */
+#define CAM_FRAME_START_ADDR0_6_OFFSET  (0x70)/* frame_start_addr0_6 */
+#define CAM_FRAME_BYTE_CNT0_6_OFFSET    (0x74)/* frame_byte_cnt0_6 */
+#define CAM_FRAME_START_ADDR0_7_OFFSET  (0x78)/* frame_start_addr0_7 */
+#define CAM_FRAME_BYTE_CNT0_7_OFFSET    (0x7C)/* frame_byte_cnt0_7 */
+#define CAM_FRAME_START_ADDR1_0_OFFSET  (0x80)/* frame_start_addr1_0 */
+#define CAM_FRAME_BYTE_CNT1_0_OFFSET    (0x84)/* frame_byte_cnt1_0 */
+#define CAM_FRAME_START_ADDR1_1_OFFSET  (0x88)/* frame_start_addr1_1 */
+#define CAM_FRAME_BYTE_CNT1_1_OFFSET    (0x8C)/* frame_byte_cnt1_1 */
+#define CAM_FRAME_START_ADDR1_2_OFFSET  (0x90)/* frame_start_addr1_2 */
+#define CAM_FRAME_BYTE_CNT1_2_OFFSET    (0x94)/* frame_byte_cnt1_2 */
+#define CAM_FRAME_START_ADDR1_3_OFFSET  (0x98)/* frame_start_addr1_3 */
+#define CAM_FRAME_BYTE_CNT1_3_OFFSET    (0x9C)/* frame_byte_cnt1_3 */
+#define CAM_FRAME_START_ADDR1_4_OFFSET  (0xA0)/* frame_start_addr1_4 */
+#define CAM_FRAME_BYTE_CNT1_4_OFFSET    (0xA4)/* frame_byte_cnt1_4 */
+#define CAM_FRAME_START_ADDR1_5_OFFSET  (0xA8)/* frame_start_addr1_5 */
+#define CAM_FRAME_BYTE_CNT1_5_OFFSET    (0xAC)/* frame_byte_cnt1_5 */
+#define CAM_FRAME_START_ADDR1_6_OFFSET  (0xB0)/* frame_start_addr1_6 */
+#define CAM_FRAME_BYTE_CNT1_6_OFFSET    (0xB4)/* frame_byte_cnt1_6 */
+#define CAM_FRAME_START_ADDR1_7_OFFSET  (0xB8)/* frame_start_addr1_7 */
+#define CAM_FRAME_BYTE_CNT1_7_OFFSET    (0xBC)/* frame_byte_cnt1_7 */
+#define CAM_DVP_DEBUG_OFFSET            (0xFF0)/* dvp_debug */
+#define CAM_DVP_DUMMY_REG_OFFSET        (0xFFC)/* dvp_dummy_reg */
+#else
+#define CAM_DVP_STATUS_AND_ERROR_OFFSET (0xC)/* dvp_status_and_error */
+#define CAM_DVP2AXI_FRAME_BCNT_OFFSET   (0x10)/* dvp2axi_frame_bcnt */
+#define CAM_DVP_FRAME_FIFO_POP_OFFSET   (0x14)/* dvp_frame_fifo_pop */
+#define CAM_DVP2AXI_FRAME_VLD_OFFSET    (0x18)/* dvp2axi_frame_vld */
+#define CAM_DVP2AXI_FRAME_PERIOD_OFFSET (0x1C)/* dvp2axi_frame_period */
+#define CAM_DVP2AXI_MISC_OFFSET         (0x20)/* dvp2axi_misc */
+#define CAM_FRAME_ID_STS01_OFFSET       (0x60)/* frame_id_sts01 */
+#define CAM_FRAME_ID_STS23_OFFSET       (0x64)/* frame_id_sts23 */
+#define CAM_DVP_DEBUG_OFFSET            (0xF0)/* dvp_debug */
+#define CAM_DVP_DUMMY_REG_OFFSET        (0xFC)/* dvp_dummy_reg */
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : dvp2axi_configue */
+#define CAM_REG_DVP_ENABLE           (1<<0U)
+#define CAM_REG_SW_MODE              (1<<1U)
+#define CAM_REG_FRAM_VLD_POL         (1<<2U)
+#define CAM_REG_LINE_VLD_POL         (1<<3U)
+#define CAM_REG_XLEN_SHIFT           (4U)
+#if defined(BL702)
+#define CAM_REG_XLEN_MASK            (0x3<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __CKS_REG_H__
+#define  __CKS_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CKS_CONFIG_OFFSET                                       (0x0)/* cks_config */
+#define CKS_DATA_IN_OFFSET                                      (0x4)/* data_in */
+#define CKS_OUT_OFFSET                                          (0x8)/* cks_out */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : cks_config */
+#define CKS_CR_CKS_CLR                                          (1<<0U)
+#define CKS_CR_CKS_BYTE_SWAP                                    (1<<1U)
+
+/* 0x4 : data_in */
+#define CKS_DATA_IN_SHIFT                                       (0U)
+#define CKS_DATA_IN_MASK                                        (0xff<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __HARDWARE_CSI_H__
+#define  __HARDWARE_CSI_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define CSI_MIPI_CONFIG_OFFSET    (0x0)/* mipi_config */
+#define CSI_INT_STATUS_OFFSET     (0x10)/* csi_int_status */
+#define CSI_INT_MASK_OFFSET       (0x14)/* csi_int_mask */
+#define CSI_INT_CLEAR_OFFSET      (0x18)/* csi_int_clear */
+#define CSI_INT_ENABLE_OFFSET     (0x1C)/* csi_int_enable */
+#define CSI_GNR_BUF_STATUS_OFFSET (0x20)/* gnr_buf_status */
+#define CSI_GNR_BUF_RDATA_OFFSET  (0x24)/* gnr_buf_rdata */
+#define CSI_DPHY_CONFIG_0_OFFSET  (0x80)/* dphy_config_0 */
+#define CSI_DPHY_CONFIG_1_OFFSET  (0x84)/* dphy_config_1 */
+#define CSI_DPHY_CONFIG_2_OFFSET  (0x88)/* dphy_config_2 */
+#define CSI_DPHY_CONFIG_3_OFFSET  (0x8C)/* dphy_config_3 */
+#define CSI_DPHY_CONFIG_4_OFFSET  (0x90)/* dphy_config_4 */
+#define CSI_DPHY_CONFIG_5_OFFSET  (0x94)/* dphy_config_5 */
+#define CSI_DUMMY_REG_OFFSET      (0xFC)/* dummy_reg */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : mipi_config */
+#define CSI_CR_CSI_EN        (1<<0U)
+#define CSI_CR_LANE_NUM      (1<<1U)
+#define CSI_CR_LANE_INV      (1<<3U)
+#define CSI_CR_DATA_BIT_INV  (1<<4U)
+#define CSI_CR_SYNC_SP_EN    (1<<5U)
+#define CSI_CR_UNPACK_EN     (1<<6U)
+#define CSI_CR_VC_DVP0_SHIFT (12U)
+#define CSI_CR_VC_DVP0_MASK  (0x3<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_DAC_H__
+#define __HARDWARE_DAC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+/* gpip base */
+#define GPIP_GPDAC_CONFIG_OFFSET         (0x40) /* gpdac_config */
+#define GPIP_GPDAC_DMA_CONFIG_OFFSET     (0x44) /* gpdac_dma_config */
+#define GPIP_GPDAC_DMA_WDATA_OFFSET      (0x48) /* gpdac_dma_wdata */
+#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C) /* gpdac_tx_fifo_status */
+/* glb base */
+#if defined(BL702)
+#define GLB_GPDAC_CTRL_OFFSET  (0x308) /* gpdac_ctrl */
+#define GLB_GPDAC_ACTRL_OFFSET (0x30C) /* gpdac_actrl */
+#define GLB_GPDAC_BCTRL_OFFSET (0x310) /* gpdac_bctrl */
+#define GLB_GPDAC_DATA_OFFSET  (0x314) /* gpdac_data */
+#else
+#define GLB_GPDAC_CTRL_OFFSET  (0x120) /* gpdac_ctrl */
+#define GLB_GPDAC_ACTRL_OFFSET (0x124) /* gpdac_actrl */
+#define GLB_GPDAC_BCTRL_OFFSET (0x128) /* gpdac_bctrl */
+#define GLB_GPDAC_DATA_OFFSET  (0x12C) /* gpdac_data */
+#endif
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x40 : gpdac_config */
+#define GPIP_GPDAC_EN (1 << 0U)
+#if defined(BL702)
+#define GPIP_GPDAC_EN2      (1 << 1U)
+#define GPIP_DSM_MODE_SHIFT (4U)
+#define GPIP_DSM_MODE_MASK  (0x3 << GPIP_DSM_MODE_SHIFT)
+#endif
+#define GPIP_GPDAC_MODE_SHIFT     (8U)
+#define GPIP_GPDAC_MODE_MASK      (0x7 << GPIP_GPDAC_MODE_SHIFT)
+#define GPIP_GPDAC_CH_A_SEL_SHIFT (16U)
+#define GPIP_GPDAC_CH_A_SEL_MASK  (0xf << GPIP_GPDAC_CH_A_SEL_SHIFT)
+#define GPIP_GPDAC_CH_B_SEL_SHIFT (20U)
+#define GPIP_GPDAC_CH_B_SEL_MASK  (0xf << GPIP_GPDAC_CH_B_SEL_SHIFT)
+
+/* 0x44 : gpdac_dma_config */
+#define GPIP_GPDAC_DMA_TX_EN (1 << 0U)
+#if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808)
+#define GPIP_GPDAC_DMA_INV_MSB (1 << 1U)
+#endif
+#define GPIP_GPDAC_DMA_FORMAT_SHIFT (4U)
+#define GPIP_GPDAC_DMA_FORMAT_MASK  (0x3 << GPIP_GPDAC_DMA_FORMAT_SHIFT)
+
+/* 0x48 : gpdac_dma_wdata */
+#define GPIP_GPDAC_DMA_WDATA_SHIFT (0U)
+#define GPIP_GPDAC_DMA_WDATA_MASK  (0xffffffff << GPIP_GPDAC_DMA_WDATA_SHIFT)
+
+/* 0x4C : gpdac_tx_fifo_status */
+#define GPIP_TX_FIFO_EMPTY     (1 << 0U)
+#define GPIP_TX_FIFO_FULL      (1 << 1U)
+#define GPIP_TX_CS_SHIFT       (2U)
+#define GPIP_TX_CS_MASK        (0x3 << GPIP_TX_CS_SHIFT)
+#define GPIP_TXFIFORDPTR_SHIFT (4U)
+#define GPIP_TXFIFORDPTR_MASK  (0x7 << GPIP_TXFIFORDPTR_SHIFT)
+#define GPIP_TXFIFOWRPTR_SHIFT (8U)
+#define GPIP_TXFIFOWRPTR_MASK  (0x3 << GPIP_TXFIFOWRPTR_SHIFT)
+
+/* 0x308 : gpdac_ctrl */
+#define GLB_GPDACA_RSTN_ANA      (1 << 0U)
+#define GLB_GPDACB_RSTN_ANA      (1 << 1U)
+#define GLB_GPDAC_TEST_EN        (1 << 7U)
+#define GLB_GPDAC_REF_SEL        (1 << 8U)
+#define GLB_GPDAC_TEST_SEL_SHIFT (9U)
+#define GLB_GPDAC_TEST_SEL_MASK  (0x7 << GLB_GPDAC_TEST_SEL_SHIFT)
+#if defined(BL616) || defined(BL628) || defined(BL606P) || defined(BL808)
+#define GLB_GPDAC_ANA_CLK_SEL (1 << 12U)
+#define GLB_GPDAC_DAT_CHA_SEL (1 << 13U)
+#define GLB_GPDAC_DAT_CHB_SEL (1 << 14U)
+#endif
+#define GLB_GPDAC_RESERVED_SHIFT (24U)
+#define GLB_GPDAC_RESERVED_MASK  (0xff << GLB_GPDAC_RESERVED_SHIFT)
+
+/* 0x30C : gpdac_actrl */
+#define GLB_GPDAC_A_EN           (1 << 0U)
+#define GLB_GPDAC_IOA_EN         (1 << 1U)
+#define GLB_GPDAC_A_RNG_SHIFT    (18U)
+#define GLB_GPDAC_A_RNG_MASK     (0x3 << GLB_GPDAC_A_RNG_SHIFT)
+#define GLB_GPDAC_A_OUTMUX_SHIFT (20U)
+#define GLB_GPDAC_A_OUTMUX_MASK  (0x7 << GLB_GPDAC_A_OUTMUX_SHIFT)
+
+/* 0x310 : gpdac_bctrl */
+#define GLB_GPDAC_B_EN           (1 << 0U)
+#define GLB_GPDAC_IOB_EN         (1 << 1U)
+#define GLB_GPDAC_B_RNG_SHIFT    (18U)
+#define GLB_GPDAC_B_RNG_MASK     (0x3 << GLB_GPDAC_B_RNG_SHIFT)
+#define GLB_GPDAC_B_OUTMUX_SHIFT (20U)
+#define GLB_GPDAC_B_OUTMUX_MASK  (0x7 << GLB_GPDAC_B_OUTMUX_SHIFT)
+
+/* 0x314 : gpdac_data */
+#if defined(BL702) || defined(BL602) || defined(BL606P) || defined(BL808)
+#define GLB_GPDAC_B_DATA_SHIFT (0U)
+#define GLB_GPDAC_B_DATA_MASK  (0x3ff << GLB_GPDAC_B_DATA_SHIFT)
+#define GLB_GPDAC_A_DATA_SHIFT (16U)
+#define GLB_GPDAC_A_DATA_MASK  (0x3ff << GLB_GPDAC_A_DATA_SHIFT)
+#elif defined(BL616) || defined(BL628)
+#define GLB_GPDAC_B_DATA_SHIFT (0U)
+#define GLB_GPDAC_B_DATA_MASK  (0x1fff << GLB_GPDAC_B_DATA_SHIFT)
+#define GLB_GPDAC_A_DATA_SHIFT (16U)
+#define GLB_GPDAC_A_DATA_MASK  (0x1fff << GLB_GPDAC_A_DATA_SHIFT)
+#endif
+
+#endif /* __HARDWARE_DAC_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dbi_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dbi_reg.h
new file mode 100755
index 0000000000..9ae0a18d80
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dbi_reg.h
@@ -0,0 +1,201 @@
+/**
+  ******************************************************************************
+  * @file    dbi_reg.h
+  * @version V1.0
+  * @date    2023-02-08
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __DBI_REG_H__
+#define __DBI_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define DBI_CONFIG_OFFSET           (0x0)  /* dbi_config */
+#define DBI_QSPI_CONFIG_OFFSET      (0x4)  /* qspi_config */
+#define DBI_PIX_CNT_OFFSET          (0x8)  /* dbi_pix_cnt */
+#define DBI_PRD_OFFSET              (0xC)  /* dbi_prd */
+#define DBI_CMD_OFFSET              (0x10) /* dbi_cmd */
+#define DBI_QSPI_ADR_OFFSET         (0x14) /* dbi_qspi_adr */
+#define DBI_RDATA_0_OFFSET          (0x18) /* dbi_rdata_0 */
+#define DBI_RDATA_1_OFFSET          (0x1C) /* dbi_rdata_1 */
+#define DBI_INT_STS_OFFSET          (0x30) /* dbi_int_sts */
+#define DBI_YUV_RGB_CONFIG_0_OFFSET (0x60) /* dbi_yuv_rgb_config_0 */
+#define DBI_YUV_RGB_CONFIG_1_OFFSET (0x64) /* dbi_yuv_rgb_config_1 */
+#define DBI_YUV_RGB_CONFIG_2_OFFSET (0x68) /* dbi_yuv_rgb_config_2 */
+#define DBI_YUV_RGB_CONFIG_3_OFFSET (0x6C) /* dbi_yuv_rgb_config_3 */
+#define DBI_YUV_RGB_CONFIG_4_OFFSET (0x70) /* dbi_yuv_rgb_config_4 */
+#define DBI_YUV_RGB_CONFIG_5_OFFSET (0x74) /* dbi_yuv_rgb_config_5 */
+#define DBI_FIFO_CONFIG_0_OFFSET    (0x80) /* dbi_fifo_config_0 */
+#define DBI_FIFO_CONFIG_1_OFFSET    (0x84) /* dbi_fifo_config_1 */
+#define DBI_FIFO_WDATA_OFFSET       (0x88) /* dbi_fifo_wdata */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : dbi_config */
+#define DBI_CR_DBI_EN               (1 << 0U)
+#define DBI_CR_DBI_SEL_SHIFT        (1U)
+#define DBI_CR_DBI_SEL_MASK         (0x3 << DBI_CR_DBI_SEL_SHIFT)
+#define DBI_CR_DBI_CMD_EN           (1 << 4U)
+#define DBI_CR_DBI_DAT_EN           (1 << 5U)
+#define DBI_CR_DBI_DAT_WR           (1 << 6U)
+#define DBI_CR_DBI_DAT_TP           (1 << 7U)
+#define DBI_CR_DBI_DAT_BC_SHIFT     (8U)
+#define DBI_CR_DBI_DAT_BC_MASK      (0xff << DBI_CR_DBI_DAT_BC_SHIFT)
+#define DBI_CR_DBI_SCL_POL          (1 << 16U)
+#define DBI_CR_DBI_SCL_PH           (1 << 17U)
+#define DBI_CR_DBI_CONT_EN          (1 << 18U)
+#define DBI_CR_DBI_DMY_EN           (1 << 19U)
+#define DBI_CR_DBI_DMY_CNT_SHIFT    (20U)
+#define DBI_CR_DBI_DMY_CNT_MASK     (0xf << DBI_CR_DBI_DMY_CNT_SHIFT)
+#define DBI_CR_DBI_CS_STRETCH       (1 << 24U)
+#define DBI_STS_DBI_BUS_BUSY        (1 << 31U)
+
+/* 0x4 : qspi_config */
+#define DBI_CR_QSPI_CMD_4B          (1 << 0U)
+#define DBI_CR_QSPI_ADR_4B          (1 << 1U)
+#define DBI_CR_QSPI_DAT_4B          (1 << 2U)
+#define DBI_CR_QSPI_ADR_BC_SHIFT    (4U)
+#define DBI_CR_QSPI_ADR_BC_MASK     (0x3 << DBI_CR_QSPI_ADR_BC_SHIFT)
+
+/* 0x8 : dbi_pix_cnt */
+#define DBI_CR_DBI_PIX_CNT_SHIFT    (0U)
+#define DBI_CR_DBI_PIX_CNT_MASK     (0xffffff << DBI_CR_DBI_PIX_CNT_SHIFT)
+#define DBI_CR_DBI_PIX_FORMAT       (1 << 31U)
+
+/* 0xC : dbi_prd */
+#define DBI_CR_DBI_PRD_S_SHIFT      (0U)
+#define DBI_CR_DBI_PRD_S_MASK       (0xff << DBI_CR_DBI_PRD_S_SHIFT)
+#define DBI_CR_DBI_PRD_I_SHIFT      (8U)
+#define DBI_CR_DBI_PRD_I_MASK       (0xff << DBI_CR_DBI_PRD_I_SHIFT)
+#define DBI_CR_DBI_PRD_D_PH_0_SHIFT (16U)
+#define DBI_CR_DBI_PRD_D_PH_0_MASK  (0xff << DBI_CR_DBI_PRD_D_PH_0_SHIFT)
+#define DBI_CR_DBI_PRD_D_PH_1_SHIFT (24U)
+#define DBI_CR_DBI_PRD_D_PH_1_MASK  (0xff << DBI_CR_DBI_PRD_D_PH_1_SHIFT)
+
+/* 0x10 : dbi_cmd */
+#define DBI_CR_DBI_CMD_SHIFT        (0U)
+#define DBI_CR_DBI_CMD_MASK         (0xff << DBI_CR_DBI_CMD_SHIFT)
+
+/* 0x14 : dbi_qspi_adr */
+#define DBI_CR_QSPI_ADR_SHIFT       (0U)
+#define DBI_CR_QSPI_ADR_MASK        (0xffffffff << DBI_CR_QSPI_ADR_SHIFT)
+
+/* 0x18 : dbi_rdata_0 */
+#define DBI_STS_DBI_RDATA_0_SHIFT   (0U)
+#define DBI_STS_DBI_RDATA_0_MASK    (0xffffffff << DBI_STS_DBI_RDATA_0_SHIFT)
+
+/* 0x1C : dbi_rdata_1 */
+#define DBI_STS_DBI_RDATA_1_SHIFT   (0U)
+#define DBI_STS_DBI_RDATA_1_MASK    (0xffffffff << DBI_STS_DBI_RDATA_1_SHIFT)
+
+/* 0x30 : dbi_int_sts */
+#define DBI_END_INT                 (1 << 0U)
+#define DBI_TXF_INT                 (1 << 1U)
+#define DBI_FER_INT                 (1 << 2U)
+#define DBI_CR_DBI_END_MASK         (1 << 8U)
+#define DBI_CR_DBI_TXF_MASK         (1 << 9U)
+#define DBI_CR_DBI_FER_MASK         (1 << 10U)
+#define DBI_CR_DBI_END_CLR          (1 << 16U)
+#define DBI_CR_DBI_END_EN           (1 << 24U)
+#define DBI_CR_DBI_TXF_EN           (1 << 25U)
+#define DBI_CR_DBI_FER_EN           (1 << 26U)
+
+/* 0x60 : dbi_yuv_rgb_config_0 */
+#define DBI_CR_Y2R_PRE_0_SHIFT      (0U)
+#define DBI_CR_Y2R_PRE_0_MASK       (0x1ff << DBI_CR_Y2R_PRE_0_SHIFT)
+#define DBI_CR_Y2R_PRE_1_SHIFT      (10U)
+#define DBI_CR_Y2R_PRE_1_MASK       (0x1ff << DBI_CR_Y2R_PRE_1_SHIFT)
+#define DBI_CR_Y2R_PRE_2_SHIFT      (20U)
+#define DBI_CR_Y2R_PRE_2_MASK       (0x1ff << DBI_CR_Y2R_PRE_2_SHIFT)
+#define DBI_CR_Y2R_EN               (1 << 31U)
+
+/* 0x64 : dbi_yuv_rgb_config_1 */
+#define DBI_CR_Y2R_POS_0_SHIFT      (0U)
+#define DBI_CR_Y2R_POS_0_MASK       (0x1ff << DBI_CR_Y2R_POS_0_SHIFT)
+#define DBI_CR_Y2R_POS_1_SHIFT      (10U)
+#define DBI_CR_Y2R_POS_1_MASK       (0x1ff << DBI_CR_Y2R_POS_1_SHIFT)
+#define DBI_CR_Y2R_POS_2_SHIFT      (20U)
+#define DBI_CR_Y2R_POS_2_MASK       (0x1ff << DBI_CR_Y2R_POS_2_SHIFT)
+
+/* 0x68 : dbi_yuv_rgb_config_2 */
+#define DBI_CR_Y2R_MTX_00_SHIFT     (0U)
+#define DBI_CR_Y2R_MTX_00_MASK      (0xfff << DBI_CR_Y2R_MTX_00_SHIFT)
+#define DBI_CR_Y2R_MTX_01_SHIFT     (12U)
+#define DBI_CR_Y2R_MTX_01_MASK      (0xfff << DBI_CR_Y2R_MTX_01_SHIFT)
+#define DBI_CR_Y2R_MTX_02_L_SHIFT   (24U)
+#define DBI_CR_Y2R_MTX_02_L_MASK    (0xff << DBI_CR_Y2R_MTX_02_L_SHIFT)
+
+/* 0x6C : dbi_yuv_rgb_config_3 */
+#define DBI_CR_Y2R_MTX_02_U_SHIFT   (0U)
+#define DBI_CR_Y2R_MTX_02_U_MASK    (0xf << DBI_CR_Y2R_MTX_02_U_SHIFT)
+#define DBI_CR_Y2R_MTX_10_SHIFT     (4U)
+#define DBI_CR_Y2R_MTX_10_MASK      (0xfff << DBI_CR_Y2R_MTX_10_SHIFT)
+#define DBI_CR_Y2R_MTX_11_SHIFT     (16U)
+#define DBI_CR_Y2R_MTX_11_MASK      (0xfff << DBI_CR_Y2R_MTX_11_SHIFT)
+#define DBI_CR_Y2R_MTX_12_L_SHIFT   (28U)
+#define DBI_CR_Y2R_MTX_12_L_MASK    (0xf << DBI_CR_Y2R_MTX_12_L_SHIFT)
+
+/* 0x70 : dbi_yuv_rgb_config_4 */
+#define DBI_CR_Y2R_MTX_12_U_SHIFT   (0U)
+#define DBI_CR_Y2R_MTX_12_U_MASK    (0xff << DBI_CR_Y2R_MTX_12_U_SHIFT)
+#define DBI_CR_Y2R_MTX_20_SHIFT     (8U)
+#define DBI_CR_Y2R_MTX_20_MASK      (0xfff << DBI_CR_Y2R_MTX_20_SHIFT)
+#define DBI_CR_Y2R_MTX_21_SHIFT     (20U)
+#define DBI_CR_Y2R_MTX_21_MASK      (0xfff << DBI_CR_Y2R_MTX_21_SHIFT)
+
+/* 0x74 : dbi_yuv_rgb_config_5 */
+#define DBI_CR_Y2R_MTX_22_SHIFT     (0U)
+#define DBI_CR_Y2R_MTX_22_MASK      (0xfff << DBI_CR_Y2R_MTX_22_SHIFT)
+
+/* 0x80 : dbi_fifo_config_0 */
+#define DBI_DMA_TX_EN               (1 << 0U)
+#define DBI_TX_FIFO_CLR             (1 << 2U)
+#define DBI_TX_FIFO_OVERFLOW        (1 << 4U)
+#define DBI_TX_FIFO_UNDERFLOW       (1 << 5U)
+#define DBI_FIFO_YUV_MODE           (1 << 28U)
+#define DBI_FIFO_FORMAT_SHIFT       (29U)
+#define DBI_FIFO_FORMAT_MASK        (0x7 << DBI_FIFO_FORMAT_SHIFT)
+
+/* 0x84 : dbi_fifo_config_1 */
+#define DBI_TX_FIFO_CNT_SHIFT       (0U)
+#define DBI_TX_FIFO_CNT_MASK        (0xf << DBI_TX_FIFO_CNT_SHIFT)
+#define DBI_TX_FIFO_TH_SHIFT        (16U)
+#define DBI_TX_FIFO_TH_MASK         (0x7 << DBI_TX_FIFO_TH_SHIFT)
+
+/* 0x88 : dbi_fifo_wdata */
+#define DBI_FIFO_WDATA_SHIFT        (0U)
+#define DBI_FIFO_WDATA_MASK         (0xffffffff << DBI_FIFO_WDATA_SHIFT)
+
+#endif /* __DBI_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dma_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dma_reg.h
new file mode 100755
index 0000000000..83b0d5c1dc
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dma_reg.h
@@ -0,0 +1,190 @@
+/**
+  ******************************************************************************
+  * @file    dma_reg.h
+  * @version V1.0
+  * @date    2022-06-20
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_DMA_H__
+#define __HARDWARE_DMA_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define DMA_INTSTATUS_OFFSET         (0x0)  /* DMA_IntStatus */
+#define DMA_INTTCSTATUS_OFFSET       (0x4)  /* DMA_IntTCStatus */
+#define DMA_INTTCCLEAR_OFFSET        (0x8)  /* DMA_IntTCClear */
+#define DMA_INTERRORSTATUS_OFFSET    (0xC)  /* DMA_IntErrorStatus */
+#define DMA_INTERRCLR_OFFSET         (0x10) /* DMA_IntErrClr */
+#define DMA_RAWINTTCSTATUS_OFFSET    (0x14) /* DMA_RawIntTCStatus */
+#define DMA_RAWINTERRORSTATUS_OFFSET (0x18) /* DMA_RawIntErrorStatus */
+#define DMA_ENBLDCHNS_OFFSET         (0x1C) /* DMA_EnbldChns */
+#define DMA_SOFTBREQ_OFFSET          (0x20) /* DMA_SoftBReq */
+#define DMA_SOFTSREQ_OFFSET          (0x24) /* DMA_SoftSReq */
+#define DMA_SOFTLBREQ_OFFSET         (0x28) /* DMA_SoftLBReq */
+#define DMA_SOFTLSREQ_OFFSET         (0x2C) /* DMA_SoftLSReq */
+#define DMA_TOP_CONFIG_OFFSET        (0x30) /* DMA_Top_Config */
+#define DMA_SYNC_OFFSET              (0x34) /* DMA_Sync */
+
+#define DMA_CxSRCADDR_OFFSET (0x00) /* DMA_CxSrcAddr */
+#define DMA_CxDSTADDR_OFFSET (0x04) /* DMA_CxDstAddr */
+#define DMA_CxLLI_OFFSET     (0x08) /* DMA_CxLLI */
+#define DMA_CxCONTROL_OFFSET (0x0C) /* DMA_CxControl */
+#define DMA_CxCONFIG_OFFSET  (0x10) /* DMA_CxConfig */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : DMA_IntStatus */
+#define DMA_INTSTATUS_SHIFT (0U)
+#define DMA_INTSTATUS_MASK  (0xff << DMA_INTSTATUS_SHIFT)
+
+/* 0x4 : DMA_IntTCStatus */
+#define DMA_INTTCSTATUS_SHIFT (0U)
+#define DMA_INTTCSTATUS_MASK  (0xff << DMA_INTTCSTATUS_SHIFT)
+
+/* 0x8 : DMA_IntTCClear */
+#define DMA_INTTCCLEAR_SHIFT (0U)
+#define DMA_INTTCCLEAR_MASK  (0xff << DMA_INTTCCLEAR_SHIFT)
+
+/* 0xC : DMA_IntErrorStatus */
+#define DMA_INTERRORSTATUS_SHIFT (0U)
+#define DMA_INTERRORSTATUS_MASK  (0xff << DMA_INTERRORSTATUS_SHIFT)
+
+/* 0x10 : DMA_IntErrClr */
+#define DMA_INTERRCLR_SHIFT (0U)
+#define DMA_INTERRCLR_MASK  (0xff << DMA_INTERRCLR_SHIFT)
+
+/* 0x14 : DMA_RawIntTCStatus */
+#define DMA_RAWINTTCSTATUS_SHIFT (0U)
+#define DMA_RAWINTTCSTATUS_MASK  (0xff << DMA_RAWINTTCSTATUS_SHIFT)
+
+/* 0x18 : DMA_RawIntErrorStatus */
+#define DMA_RAWINTERRORSTATUS_SHIFT (0U)
+#define DMA_RAWINTERRORSTATUS_MASK  (0xff << DMA_RAWINTERRORSTATUS_SHIFT)
+
+/* 0x1C : DMA_EnbldChns */
+#define DMA_ENABLEDCHANNELS_SHIFT (0U)
+#define DMA_ENABLEDCHANNELS_MASK  (0xff << DMA_ENABLEDCHANNELS_SHIFT)
+
+/* 0x20 : DMA_SoftBReq */
+#define DMA_SOFTBREQ_SHIFT (0U)
+#define DMA_SOFTBREQ_MASK  (0xffffffff << DMA_SOFTBREQ_SHIFT)
+
+/* 0x24 : DMA_SoftSReq */
+#define DMA_SOFTSREQ_SHIFT (0U)
+#define DMA_SOFTSREQ_MASK  (0xffffffff << DMA_SOFTSREQ_SHIFT)
+
+/* 0x28 : DMA_SoftLBReq */
+#define DMA_SOFTLBREQ_SHIFT (0U)
+#define DMA_SOFTLBREQ_MASK  (0xffffffff << DMA_SOFTLBREQ_SHIFT)
+
+/* 0x2C : DMA_SoftLSReq */
+#define DMA_SOFTLSREQ_SHIFT (0U)
+#define DMA_SOFTLSREQ_MASK  (0xffffffff << DMA_SOFTLSREQ_SHIFT)
+
+/* 0x30 : DMA_Top_Config */
+#define DMA_E (1 << 0U)
+#define DMA_M (1 << 1U)
+
+/* 0x34 : DMA_Sync */
+#define DMA_SYNC_SHIFT (0U)
+#define DMA_SYNC_MASK  (0xffffffff << DMA_SYNC_SHIFT)
+
+/* 0x100 : DMA_CxSrcAddr */
+#define DMA_SRCADDR_SHIFT (0U)
+#define DMA_SRCADDR_MASK  (0xffffffff << DMA_SRCADDR_SHIFT)
+
+/* 0x104 : DMA_CxDstAddr */
+#define DMA_DSTADDR_SHIFT (0U)
+#define DMA_DSTADDR_MASK  (0xffffffff << DMA_DSTADDR_SHIFT)
+
+/* 0x108 : DMA_CxLLI */
+#define DMA_LLI_SHIFT (0U)
+#define DMA_LLI_MASK  (0xffffffff << DMA_LLI_SHIFT)
+
+/* 0x10C : DMA_CxControl */
+#define DMA_TRANSFERSIZE_SHIFT (0U)
+#define DMA_TRANSFERSIZE_MASK  (0xfff << DMA_TRANSFERSIZE_SHIFT)
+#define DMA_SBSIZE_SHIFT       (12U)
+#if defined(BL602)
+#define DMA_SBSIZE_MASK        (0x7 << DMA_SBSIZE_SHIFT)
+#else
+#define DMA_SBSIZE_MASK        (0x3 << DMA_SBSIZE_SHIFT)
+#define DMA_DST_MIN_MODE       (1 << 14U)
+#endif
+#define DMA_DBSIZE_SHIFT       (15U)
+#if defined(BL602)
+#define DMA_DBSIZE_MASK        (0x7 << DMA_DBSIZE_SHIFT)
+#else
+#define DMA_DBSIZE_MASK        (0x3 << DMA_DBSIZE_SHIFT)
+#define DMA_DST_ADD_MODE       (1 << 17U)
+#endif
+#define DMA_SWIDTH_SHIFT       (18U)
+#if defined(BL602)
+#define DMA_SWIDTH_MASK        (0x7 << DMA_SWIDTH_SHIFT)
+#else
+#define DMA_SWIDTH_MASK        (0x3 << DMA_SWIDTH_SHIFT)
+#endif
+#define DMA_DWIDTH_SHIFT       (21U)
+#if defined(BL602)
+#define DMA_DWIDTH_MASK        (0x7 << DMA_DWIDTH_SHIFT)
+#define DMA_SLARGERD           (1 << 24U)
+#else
+#define DMA_DWIDTH_MASK        (0x3 << DMA_DWIDTH_SHIFT)
+#define DMA_FIX_CNT_SHIFT      (23U)
+#define DMA_FIX_CNT_MASK       (0x7 << DMA_FIX_CNT_SHIFT)
+#endif
+#define DMA_SI                 (1 << 26U)
+#define DMA_DI                 (1 << 27U)
+#define DMA_PROT_SHIFT         (28U)
+#define DMA_PROT_MASK          (0x7 << DMA_PROT_SHIFT)
+#define DMA_I                  (1 << 31U)
+
+/* 0x110 : DMA_CxConfig */
+#define DMA_E                   (1 << 0U)
+#define DMA_SRCPERIPHERAL_SHIFT (1U)
+#define DMA_SRCPERIPHERAL_MASK  (0x1f << DMA_SRCPERIPHERAL_SHIFT)
+#define DMA_DSTPERIPHERAL_SHIFT (6U)
+#define DMA_DSTPERIPHERAL_MASK  (0x1f << DMA_DSTPERIPHERAL_SHIFT)
+#define DMA_FLOWCNTRL_SHIFT     (11U)
+#define DMA_FLOWCNTRL_MASK      (0x7 << DMA_FLOWCNTRL_SHIFT)
+#define DMA_IE                  (1 << 14U)
+#define DMA_ITC                 (1 << 15U)
+#define DMA_L                   (1 << 16U)
+#define DMA_A                   (1 << 17U)
+#define DMA_H                   (1 << 18U)
+#define DMA_LLICOUNTER_SHIFT    (20U)
+#define DMA_LLICOUNTER_MASK     (0x3ff << DMA_LLICOUNTER_SHIFT)
+
+#endif /* __HARDWARE_DMA_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dtsrc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dtsrc_reg.h
new file mode 100755
index 0000000000..1c3a21c79c
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/dtsrc_reg.h
@@ -0,0 +1,168 @@
+/**
+  ******************************************************************************
+  * @file    dtsrc_reg.h
+  * @version V1.0
+  * @date    2022-12-15
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __HARDWARE_DTSRC_H__
+#define  __HARDWARE_DTSRC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define DTSRC_CONFIG_OFFSET                                     (0x0)/* config */
+#define DTSRC_FRAME_SIZE_H_OFFSET                               (0x4)/* frame_size_h */
+#define DTSRC_FRAME_SIZE_V_OFFSET                               (0x8)/* frame_size_v */
+#define DTSRC_FRAME_SIZE_CEA_861_OFFSET                         (0xC)/* frame_size_cea_861 */
+#define DTSRC_PIX_DATA_RANGE_OFFSET                             (0x10)/* pix_data_range */
+#define DTSRC_PIX_DATA_STEP_OFFSET                              (0x14)/* pix_data_step */
+#define DTSRC_AXI2DVP_SETTING_OFFSET                            (0x20)/* axi2dvp_setting */
+#define DTSRC_AXI2DVP_START_ADDR_BY_OFFSET                      (0x24)/* axi2dvp_start_addr_by */
+#define DTSRC_AXI2DVP_BURST_CNT_OFFSET                          (0x28)/* axi2dvp_burst_cnt */
+#define DTSRC_AXI2DVP_STATUS_OFFSET                             (0x2C)/* axi2dvp_status */
+#define DTSRC_AXI2DVP_SWAP_ADDR_BY_OFFSET                       (0x30)/* axi2dvp_swap_addr_by */
+#define DTSRC_AXI2DVP_PREFETCH_OFFSET                           (0x34)/* axi2dvp_prefetch */
+#define DTSRC_SNSR2DVP_WAIT_POS_OFFSET                          (0x38)/* snsr2dvp_wait_pos */
+#define DTSRC_AXI2DVP_START_ADDR_UV_OFFSET                      (0x40)/* axi2dvp_start_addr_uv */
+#define DTSRC_AXI2DVP_SWAP_ADDR_UV_OFFSET                       (0x44)/* axi2dvp_swap_addr_uv */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : config */
+#define DTSRC_CR_ENABLE                                         (1<<0U)
+#define DTSRC_CR_AXI_EN                                         (1<<1U)
+#define DTSRC_CR_MODE_CEA_861                                   (1<<2U)
+#define DTSRC_CR_SNSR_EN                                        (1<<3U)
+#define DTSRC_CR_SNSR_HSYNC_INV                                 (1<<4U)
+#define DTSRC_CR_SNSR_VSYNC_INV                                 (1<<5U)
+#define DTSRC_CR_AXI_SWAP_MODE                                  (1<<7U)
+#define DTSRC_CR_AXI_SWAP_IDX_SEL_SHIFT                         (8U)
+#define DTSRC_CR_AXI_SWAP_IDX_SEL_MASK                          (0xf<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_EF_CTRL_H__
+#define __HARDWARE_EF_CTRL_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define EF_CTRL_EF_IF_CTRL_0_OFFSET   (0x800) /* efuse control */
+#define EF_CTRL_EF_IF_CYC_0_OFFSET    (0x804) /* efuse cycle config 0 */
+#define EF_CTRL_EF_IF_CYC_1_OFFSET    (0x808) /* efuse cycle config 1 */
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET (0x80C) /* efuse manual config 1 */
+#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810) /* efuse status */
+#define EF_CTRL_EF_IF_CFG_0_OFFSET    (0x814) /* efuse config 0 */
+
+/* 0x800 :efuse control */
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE       EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS   (0U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN   (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MASK  (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMASK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE          EF_CTRL_EF_IF_0_AUTOLOAD_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS      (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN      (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK     (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMASK    (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
+//#define EF_CTRL_EF_IF_0_BUSY                   EF_CTRL_EF_IF_0_BUSY
+#define EF_CTRL_EF_IF_0_BUSY_POS               (2U)
+#define EF_CTRL_EF_IF_0_BUSY_LEN               (1U)
+#define EF_CTRL_EF_IF_0_BUSY_MASK              (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
+#define EF_CTRL_EF_IF_0_BUSY_UMASK             (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
+#define EF_CTRL_EF_IF_0_RW                     EF_CTRL_EF_IF_0_RW
+#define EF_CTRL_EF_IF_0_RW_POS                 (3U)
+#define EF_CTRL_EF_IF_0_RW_LEN                 (1U)
+#define EF_CTRL_EF_IF_0_RW_MASK                (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
+#define EF_CTRL_EF_IF_0_RW_UMASK               (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
+#define EF_CTRL_EF_IF_0_TRIG                   EF_CTRL_EF_IF_0_TRIG
+#define EF_CTRL_EF_IF_0_TRIG_POS               (4U)
+#define EF_CTRL_EF_IF_0_TRIG_LEN               (1U)
+#define EF_CTRL_EF_IF_0_TRIG_MASK              (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
+#define EF_CTRL_EF_IF_0_TRIG_UMASK             (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
+#define EF_CTRL_EF_IF_0_MANUAL_EN              EF_CTRL_EF_IF_0_MANUAL_EN
+#define EF_CTRL_EF_IF_0_MANUAL_EN_POS          (5U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN          (1U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_MASK         (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_UMASK        (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_0_CYC_MODIFY             EF_CTRL_EF_IF_0_CYC_MODIFY
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS         (6U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN         (1U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_MASK        (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMASK       (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL       EF_CTRL_EF_CLK_SAHB_DATA_SEL
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS   (7U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN   (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MASK  (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMASK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
+#endif
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL       EF_CTRL_EF_IF_PROT_CODE_CTRL
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS   (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN   (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MASK  (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMASK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
+#define EF_CTRL_EF_IF_POR_DIG              EF_CTRL_EF_IF_POR_DIG
+#define EF_CTRL_EF_IF_POR_DIG_POS          (16U)
+#define EF_CTRL_EF_IF_POR_DIG_LEN          (1U)
+#define EF_CTRL_EF_IF_POR_DIG_MASK         (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
+#define EF_CTRL_EF_IF_POR_DIG_UMASK        (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE       EF_CTRL_EF_CLK_SAHB_DATA_GATE
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS   (17U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN   (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MASK  (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMASK (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
+#else
+#define EF_CTRL_EF_PCLK_FORCE_ON       EF_CTRL_EF_PCLK_FORCE_ON
+#define EF_CTRL_EF_PCLK_FORCE_ON_POS   (17U)
+#define EF_CTRL_EF_PCLK_FORCE_ON_LEN   (1U)
+#define EF_CTRL_EF_PCLK_FORCE_ON_MASK  (((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS)
+#define EF_CTRL_EF_PCLK_FORCE_ON_UMASK (~(((1U << EF_CTRL_EF_PCLK_FORCE_ON_LEN) - 1) << EF_CTRL_EF_PCLK_FORCE_ON_POS))
+#endif
+#define EF_CTRL_EF_IF_AUTO_RD_EN            EF_CTRL_EF_IF_AUTO_RD_EN
+#define EF_CTRL_EF_IF_AUTO_RD_EN_POS        (18U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN        (1U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_MASK       (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_UMASK      (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK       EF_CTRL_EF_IF_CYC_MODIFY_LOCK
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS   (19U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN   (1U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MASK  (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMASK (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
+#define EF_CTRL_EF_IF_0_INT                 EF_CTRL_EF_IF_0_INT
+#define EF_CTRL_EF_IF_0_INT_POS             (20U)
+#define EF_CTRL_EF_IF_0_INT_LEN             (1U)
+#define EF_CTRL_EF_IF_0_INT_MASK            (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
+#define EF_CTRL_EF_IF_0_INT_UMASK           (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
+#define EF_CTRL_EF_IF_0_INT_CLR             EF_CTRL_EF_IF_0_INT_CLR
+#define EF_CTRL_EF_IF_0_INT_CLR_POS         (21U)
+#define EF_CTRL_EF_IF_0_INT_CLR_LEN         (1U)
+#define EF_CTRL_EF_IF_0_INT_CLR_MASK        (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
+#define EF_CTRL_EF_IF_0_INT_CLR_UMASK       (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
+#define EF_CTRL_EF_IF_0_INT_SET             EF_CTRL_EF_IF_0_INT_SET
+#define EF_CTRL_EF_IF_0_INT_SET_POS         (22U)
+#define EF_CTRL_EF_IF_0_INT_SET_LEN         (1U)
+#define EF_CTRL_EF_IF_0_INT_SET_MASK        (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
+#define EF_CTRL_EF_IF_0_INT_SET_UMASK       (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CYC         EF_CTRL_EF_IF_PROT_CODE_CYC
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS     (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN     (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_MASK    (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMASK   (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
+
+/* 0x80C : ef_if_0_manual, 606P and 808 manual config is the same but not need witch clock */
+#if defined(BL702) || defined(BL602) || defined(BL702L) || defined(BL606P) || defined(BL808)
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET        (0x80C)
+#define EF_CTRL_EF_IF_A                      EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS                  (0U)
+#define EF_CTRL_EF_IF_A_LEN                  (10U)
+#define EF_CTRL_EF_IF_A_MASK                 (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMASK                (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD                     EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS                 (10U)
+#define EF_CTRL_EF_IF_PD_LEN                 (1U)
+#define EF_CTRL_EF_IF_PD_MASK                (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMASK               (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS                     EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS                 (11U)
+#define EF_CTRL_EF_IF_PS_LEN                 (1U)
+#define EF_CTRL_EF_IF_PS_MASK                (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMASK               (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE                 EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS             (12U)
+#define EF_CTRL_EF_IF_STROBE_LEN             (1U)
+#define EF_CTRL_EF_IF_STROBE_MASK            (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMASK           (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB                  EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS              (13U)
+#define EF_CTRL_EF_IF_PGENB_LEN              (1U)
+#define EF_CTRL_EF_IF_PGENB_MASK             (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMASK            (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD                   EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS               (14U)
+#define EF_CTRL_EF_IF_LOAD_LEN               (1U)
+#define EF_CTRL_EF_IF_LOAD_MASK              (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMASK             (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB                    EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS                (15U)
+#define EF_CTRL_EF_IF_CSB_LEN                (1U)
+#define EF_CTRL_EF_IF_CSB_MASK               (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMASK              (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_0_Q                    EF_CTRL_EF_IF_0_Q
+#define EF_CTRL_EF_IF_0_Q_POS                (16U)
+#define EF_CTRL_EF_IF_0_Q_LEN                (8U)
+#define EF_CTRL_EF_IF_0_Q_MASK               (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
+#define EF_CTRL_EF_IF_0_Q_UMASK              (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL       EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS   (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN   (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MASK  (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMASK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+#else
+/* 0x80C : ef_if_0_manual_0 */
+#define EF_CTRL_EF_IF_0_MANUAL_0_OFFSET      (0x80C)
+#define EF_CTRL_EF_IF_A                      EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS                  (0U)
+#define EF_CTRL_EF_IF_A_LEN                  (12U)
+#define EF_CTRL_EF_IF_A_MASK                 (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMASK                (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD                     EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS                 (18U)
+#define EF_CTRL_EF_IF_PD_LEN                 (1U)
+#define EF_CTRL_EF_IF_PD_MASK                (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMASK               (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS                     EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS                 (19U)
+#define EF_CTRL_EF_IF_PS_LEN                 (1U)
+#define EF_CTRL_EF_IF_PS_MASK                (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMASK               (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE                 EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS             (20U)
+#define EF_CTRL_EF_IF_STROBE_LEN             (1U)
+#define EF_CTRL_EF_IF_STROBE_MASK            (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMASK           (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB                  EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS              (21U)
+#define EF_CTRL_EF_IF_PGENB_LEN              (1U)
+#define EF_CTRL_EF_IF_PGENB_MASK             (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMASK            (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD                   EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS               (22U)
+#define EF_CTRL_EF_IF_LOAD_LEN               (1U)
+#define EF_CTRL_EF_IF_LOAD_MASK              (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMASK             (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB                    EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS                (23U)
+#define EF_CTRL_EF_IF_CSB_LEN                (1U)
+#define EF_CTRL_EF_IF_CSB_MASK               (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMASK              (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL       EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS   (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN   (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MASK  (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMASK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+#endif
+
+#if defined(BL606P) || defined(BL808)
+/* 0x900 : ef_if_ctrl_1 */
+#define EF_CTRL_EF_IF_CTRL_1_OFFSET      (0x900)
+#define EF_CTRL_EF_IF_1_BUSY             EF_CTRL_EF_IF_1_BUSY
+#define EF_CTRL_EF_IF_1_BUSY_POS         (2U)
+#define EF_CTRL_EF_IF_1_BUSY_LEN         (1U)
+#define EF_CTRL_EF_IF_1_BUSY_MASK        (((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS)
+#define EF_CTRL_EF_IF_1_BUSY_UMASK       (~(((1U << EF_CTRL_EF_IF_1_BUSY_LEN) - 1) << EF_CTRL_EF_IF_1_BUSY_POS))
+#define EF_CTRL_EF_IF_1_RW               EF_CTRL_EF_IF_1_RW
+#define EF_CTRL_EF_IF_1_RW_POS           (3U)
+#define EF_CTRL_EF_IF_1_RW_LEN           (1U)
+#define EF_CTRL_EF_IF_1_RW_MASK          (((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS)
+#define EF_CTRL_EF_IF_1_RW_UMASK         (~(((1U << EF_CTRL_EF_IF_1_RW_LEN) - 1) << EF_CTRL_EF_IF_1_RW_POS))
+#define EF_CTRL_EF_IF_1_TRIG             EF_CTRL_EF_IF_1_TRIG
+#define EF_CTRL_EF_IF_1_TRIG_POS         (4U)
+#define EF_CTRL_EF_IF_1_TRIG_LEN         (1U)
+#define EF_CTRL_EF_IF_1_TRIG_MASK        (((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS)
+#define EF_CTRL_EF_IF_1_TRIG_UMASK       (~(((1U << EF_CTRL_EF_IF_1_TRIG_LEN) - 1) << EF_CTRL_EF_IF_1_TRIG_POS))
+#define EF_CTRL_EF_IF_1_MANUAL_EN        EF_CTRL_EF_IF_1_MANUAL_EN
+#define EF_CTRL_EF_IF_1_MANUAL_EN_POS    (5U)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_LEN    (1U)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_MASK   (((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_1_MANUAL_EN_UMASK  (~(((1U << EF_CTRL_EF_IF_1_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_1_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_1_CYC_MODIFY       EF_CTRL_EF_IF_1_CYC_MODIFY
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_POS   (6U)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_LEN   (1U)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_MASK  (((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_1_CYC_MODIFY_UMASK (~(((1U << EF_CTRL_EF_IF_1_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_1_CYC_MODIFY_POS))
+#define EF_CTRL_EF_IF_1_INT              EF_CTRL_EF_IF_1_INT
+#define EF_CTRL_EF_IF_1_INT_POS          (20U)
+#define EF_CTRL_EF_IF_1_INT_LEN          (1U)
+#define EF_CTRL_EF_IF_1_INT_MASK         (((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS)
+#define EF_CTRL_EF_IF_1_INT_UMASK        (~(((1U << EF_CTRL_EF_IF_1_INT_LEN) - 1) << EF_CTRL_EF_IF_1_INT_POS))
+#define EF_CTRL_EF_IF_1_INT_CLR          EF_CTRL_EF_IF_1_INT_CLR
+#define EF_CTRL_EF_IF_1_INT_CLR_POS      (21U)
+#define EF_CTRL_EF_IF_1_INT_CLR_LEN      (1U)
+#define EF_CTRL_EF_IF_1_INT_CLR_MASK     (((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS)
+#define EF_CTRL_EF_IF_1_INT_CLR_UMASK    (~(((1U << EF_CTRL_EF_IF_1_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_1_INT_CLR_POS))
+#define EF_CTRL_EF_IF_1_INT_SET          EF_CTRL_EF_IF_1_INT_SET
+#define EF_CTRL_EF_IF_1_INT_SET_POS      (22U)
+#define EF_CTRL_EF_IF_1_INT_SET_LEN      (1U)
+#define EF_CTRL_EF_IF_1_INT_SET_MASK     (((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS)
+#define EF_CTRL_EF_IF_1_INT_SET_UMASK    (~(((1U << EF_CTRL_EF_IF_1_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_1_INT_SET_POS))
+
+/* 0x904 : ef_if_1_manual */
+#define EF_CTRL_EF_IF_1_MANUAL_OFFSET (0x904)
+#define EF_CTRL_EF_IF_1_Q             EF_CTRL_EF_IF_1_Q
+#define EF_CTRL_EF_IF_1_Q_POS         (16U)
+#define EF_CTRL_EF_IF_1_Q_LEN         (8U)
+#define EF_CTRL_EF_IF_1_Q_MASK        (((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS)
+#define EF_CTRL_EF_IF_1_Q_UMASK       (~(((1U << EF_CTRL_EF_IF_1_Q_LEN) - 1) << EF_CTRL_EF_IF_1_Q_POS))
+
+/* 0x908 : ef_if_1_status */
+#define EF_CTRL_EF_IF_1_STATUS_OFFSET (0x908)
+#define EF_CTRL_EF_IF_1_STATUS        EF_CTRL_EF_IF_1_STATUS
+#define EF_CTRL_EF_IF_1_STATUS_POS    (0U)
+#define EF_CTRL_EF_IF_1_STATUS_LEN    (32U)
+#define EF_CTRL_EF_IF_1_STATUS_MASK   (((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS)
+#define EF_CTRL_EF_IF_1_STATUS_UMASK  (~(((1U << EF_CTRL_EF_IF_1_STATUS_LEN) - 1) << EF_CTRL_EF_IF_1_STATUS_POS))
+#endif
+
+#endif /* __HARDWARE_EF_CTRL_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/emac_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/emac_reg.h
new file mode 100755
index 0000000000..d41765cbaa
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/emac_reg.h
@@ -0,0 +1,237 @@
+/**
+  ******************************************************************************
+  * @file    emac_reg.h
+  * @version V1.0
+  * @date    2022-09-27
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2022 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_EMAC_H__
+#define __HARDWARE_EMAC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#define EMAC_MODE_OFFSET       (0x0)
+#define EMAC_INT_SOURCE_OFFSET (0x4)
+#define EMAC_INT_MASK_OFFSET   (0x8)
+#define EMAC_IPGT_OFFSET       (0xC)
+#define EMAC_PACKETLEN_OFFSET  (0x18)
+#define EMAC_COLLCONFIG_OFFSET (0x1C)
+#define EMAC_TX_BD_NUM_OFFSET  (0x20)
+#define EMAC_MIIMODE_OFFSET    (0x28)
+#define EMAC_MIICOMMAND_OFFSET (0x2C)
+#define EMAC_MIIADDRESS_OFFSET (0x30)
+#define EMAC_MIITX_DATA_OFFSET (0x34)
+#define EMAC_MIIRX_DATA_OFFSET (0x38)
+#define EMAC_MIISTATUS_OFFSET  (0x3C)
+#define EMAC_MAC_ADDR0_OFFSET  (0x40)
+#define EMAC_MAC_ADDR1_OFFSET  (0x44)
+#define EMAC_HASH0_ADDR_OFFSET (0x48)
+#define EMAC_HASH1_ADDR_OFFSET (0x4C)
+#define EMAC_TXCTRL_OFFSET     (0x50)
+#define EMAC_DMA_DESC_OFFSET   (0x400)
+
+/* 0x0 : EMAC MODE config */
+#define EMAC_RX_EN    (1 << 0U)
+#define EMAC_TX_EN    (1 << 1U)
+#define EMAC_NOPRE    (1 << 2U)
+#define EMAC_BRO      (1 << 3U)
+#define EMAC_PRO      (1 << 5U)
+#define EMAC_IFG      (1 << 6U)
+#define EMAC_FULLD    (1 << 10U)
+#define EMAC_CRCEN    (1 << 13U)
+#define EMAC_HUGEN    (1 << 14U)
+#define EMAC_PAD      (1 << 15U)
+#define EMAC_RECSMALL (1 << 16U)
+#define EMAC_RMII_EN  (1 << 17U)
+
+/* 0x4 : INT_SOURCE */
+#define EMAC_TXB  (1 << 0U)
+#define EMAC_TXE  (1 << 1U)
+#define EMAC_RXB  (1 << 2U)
+#define EMAC_RXE  (1 << 3U)
+#define EMAC_BUSY (1 << 4U)
+#define EMAC_TXC  (1 << 5U)
+#define EMAC_RXC  (1 << 6U)
+
+/* 0x8 : INT_MASK */
+#define EMAC_TXB_M  (1 << 0U)
+#define EMAC_TXE_M  (1 << 1U)
+#define EMAC_RXB_M  (1 << 2U)
+#define EMAC_RXE_M  (1 << 3U)
+#define EMAC_BUSY_M (1 << 4U)
+#define EMAC_TXC_M  (1 << 5U)
+#define EMAC_RXC_M  (1 << 6U)
+
+/* 0xC : IPGT */
+#define EMAC_IPGT_SHIFT (0U)
+#define EMAC_IPGT_MASK  (0x7f << EMAC_IPGT_SHIFT)
+
+/* 0x18 : PACKETLEN */
+#define EMAC_MAXFL_SHIFT (0U)
+#define EMAC_MAXFL_MASK  (0xffff << EMAC_MAXFL_SHIFT)
+#define EMAC_MINFL_SHIFT (16U)
+#define EMAC_MINFL_MASK  (0xffff << EMAC_MINFL_SHIFT)
+
+/* 0x1C : COLLCONFIG */
+#define EMAC_COLLVALID_SHIFT (0U)
+#define EMAC_COLLVALID_MASK  (0x3F << EMAC_COLLVALID_SHIFT)
+#define EMAC_MAXRET_SHIFT    (16U)
+#define EMAC_MAXRET_MASK     (0xF << EMAC_MAXRET_SHIFT)
+
+/* 0x20 : TX_BD_NUM */
+#define EMAC_TXBDNUM_SHIFT (0U)
+#define EMAC_TXBDNUM_MASK  (0xff << EMAC_TXBDNUM_SHIFT)
+#define EMAC_TXBDPTR_SHIFT (16U)
+#define EMAC_TXBDPTR_MASK  (0x7f << EMAC_TXBDPTR_SHIFT)
+#define EMAC_RXBDPTR_SHIFT (24U)
+#define EMAC_RXBDPTR_MASK  (0x7f << EMAC_RXBDPTR_SHIFT)
+
+/* 0x28 : MIIMODE */
+#define EMAC_CLKDIV_SHIFT (0U)
+#define EMAC_CLKDIV_MASK  (0xff << EMAC_CLKDIV_SHIFT)
+#define EMAC_MIINOPRE     (1 << 8U)
+
+/* 0x2C : MIICOMMAND */
+#define EMAC_SCANSTAT  (1 << 0U)
+#define EMAC_RSTAT     (1 << 1U)
+#define EMAC_WCTRLDATA (1 << 2U)
+
+/* 0x30 : MIIADDRESS */
+#define EMAC_FIAD_SHIFT (0U)
+#define EMAC_FIAD_MASK  (0x1f << EMAC_FIAD_SHIFT)
+#define EMAC_RGAD_SHIFT (8U)
+#define EMAC_RGAD_MASK  (0x1f << EMAC_RGAD_SHIFT)
+
+/* 0x34 : MIITX_DATA */
+#define EMAC_CTRLDATA_SHIFT (0U)
+#define EMAC_CTRLDATA_MASK  (0xffff << EMAC_CTRLDATA_SHIFT)
+
+/* 0x38 : MIIRX_DATA */
+#define EMAC_PRSD_SHIFT (0U)
+#define EMAC_PRSD_MASK  (0xffff << EMAC_PRSD_SHIFT)
+
+/* 0x3C : MIISTATUS */
+#define EMAC_MIIM_LINKFAIL (1 << 0U)
+#define EMAC_MIIM_BUSY     (1 << 1U)
+
+/* 0x40 : MAC_ADDR0 */
+#define EMAC_MAC_B5_SHIFT (0U)
+#define EMAC_MAC_B5_MASK  (0xff << EMAC_MAC_B5_SHIFT)
+#define EMAC_MAC_B4_SHIFT (8U)
+#define EMAC_MAC_B4_MASK  (0xff << EMAC_MAC_B4_SHIFT)
+#define EMAC_MAC_B3_SHIFT (16U)
+#define EMAC_MAC_B3_MASK  (0xff << EMAC_MAC_B3_SHIFT)
+#define EMAC_MAC_B2_SHIFT (24U)
+#define EMAC_MAC_B2_MASK  (0xff << EMAC_MAC_B2_SHIFT)
+
+/* 0x44 : MAC_ADDR1 */
+#define EMAC_MAC_B1_SHIFT (0U)
+#define EMAC_MAC_B1_MASK  (0xff << EMAC_MAC_B1_SHIFT)
+#define EMAC_MAC_B0_SHIFT (8U)
+#define EMAC_MAC_B0_MASK  (0xff << EMAC_MAC_B0_SHIFT)
+
+/* 0x48 : HASH0_ADDR */
+#define EMAC_HASH0_SHIFT (0U)
+#define EMAC_HASH0_MASK  (0xffffffff << EMAC_HASH0_SHIFT)
+
+/* 0x4C : HASH1_ADDR */
+#define EMAC_HASH1_SHIFT (0U)
+#define EMAC_HASH1_MASK  (0xffffffff << EMAC_HASH1_SHIFT)
+
+/* 0x50 : TXCTRL */
+#define EMAC_TXPAUSETV_SHIFT (0U)
+#define EMAC_TXPAUSETV_MASK  (0xffff << EMAC_TXPAUSETV_SHIFT)
+#define EMAC_TXPAUSERQ_SHIFT (16U)
+#define EMAC_TXPAUSERQ_MASK  (0x1 << EMAC_TXPAUSETV_SHIFT)
+
+/* 0x400 ：EAMC DMA BD DESC */
+/* EMAC TX BD DESC BASE: (TX_BD_NUM * 8) */
+#define EMAC_BD_TX_CS_SHIFT   (0) /*!< Carrier Sense Lost */
+#define EMAC_BD_TX_CS_MASK    (1 << EMAC_BD_TX_CS_SHIFT)
+#define EMAC_BD_TX_DF_SHIFT   (1) /*!< Defer Indication */
+#define EMAC_BD_TX_DF_MASK    (1 << EMAC_BD_TX_DF_SHIFT)
+#define EMAC_BD_TX_LC_SHIFT   (2) /*!< Late Collision */
+#define EMAC_BD_TX_LC_MASK    (1 << EMAC_BD_TX_LC_SHIFT)
+#define EMAC_BD_TX_RL_SHIFT   (3) /*!< Retransmission Limit */
+#define EMAC_BD_TX_RL_MASK    (1 << EMAC_BD_TX_RL_SHIFT)
+#define EMAC_BD_TX_RTRY_SHIFT (4) /*!< Retry Count */
+#define EMAC_BD_TX_RTRY_MASK  (4 << EMAC_BD_TX_RTRY_SHIFT)
+#define EMAC_BD_TX_UR_SHIFT   (8) /*!< Underrun */
+#define EMAC_BD_TX_UR_MASK    (1 << EMAC_BD_TX_UR_SHIFT)
+#define EMAC_BD_TX_EOF_SHIFT  (10) /*!< EOF */
+#define EMAC_BD_TX_EOF_MASK   (1 << EMAC_BD_TX_EOF_SHIFT)
+#define EMAC_BD_TX_CRC_SHIFT  (11) /*!< CRC Enable */
+#define EMAC_BD_TX_CRC_MASK   (1 << EMAC_BD_TX_CRC_SHIFT)
+#define EMAC_BD_TX_PAD_SHIFT  (12) /*!< PAD enable */
+#define EMAC_BD_TX_PAD_MASK   (1 << EMAC_BD_TX_PAD_SHIFT)
+#define EMAC_BD_TX_WR_SHIFT   (13) /*!< Wrap */
+#define EMAC_BD_TX_WR_MASK    (1 << EMAC_BD_TX_WR_SHIFT)
+#define EMAC_BD_TX_IRQ_SHIFT  (14) /*!< Interrupt Request Enable */
+#define EMAC_BD_TX_IRQ_MASK   (1 << EMAC_BD_TX_IRQ_SHIFT)
+#define EMAC_BD_TX_RD_SHIFT   (15) /*!< The data buffer is ready for transmission or is currently being transmitted. You are not allowed to change it */
+#define EMAC_BD_TX_RD_MASK    (1 << EMAC_BD_TX_RD_SHIFT)
+#define EMAC_BD_TX_LEN_SHIFT  (16) /*!< TX Data buffer length */
+#define EMAC_BD_TX_LEN_MASK   (0xffff << EMAC_BD_TX_LEN_SHIFT)
+
+/* RX BD DESC BASE: ((TX_BD_NUM + RX_BD_NUM) * 8) */
+#define EMAC_BD_RX_LC_SHIFT  (0) /*!< Late Collision */
+#define EMAC_BD_RX_LC_MASK   (1 << EMAC_BD_RX_LC_SHIFT)
+#define EMAC_BD_RX_CRC_SHIFT (1) /*!< RX CRC Error */
+#define EMAC_BD_RX_CRC_MASK  (1 << EMAC_BD_RX_CRC_SHIFT)
+#define EMAC_BD_RX_SF_SHIFT  (2) /*!< Short Frame */
+#define EMAC_BD_RX_SF_MASK   (1 << EMAC_BD_RX_SF_SHIFT)
+#define EMAC_BD_RX_TL_SHIFT  (3) /*!< Too Long */
+#define EMAC_BD_RX_TL_MASK   (1 << EMAC_BD_RX_TL_SHIFT)
+#define EMAC_BD_RX_DN_SHIFT  (4) /*!< Dribble Nibble */
+#define EMAC_BD_RX_DN_MASK   (1 << EMAC_BD_RX_DN_SHIFT)
+#define EMAC_BD_RX_RE_SHIFT  (5) /*!< Receive Error */
+#define EMAC_BD_RX_RE_MASK   (1 << EMAC_BD_RX_RE_SHIFT)
+#define EMAC_BD_RX_OR_SHIFT  (6) /*!< Overrun */
+#define EMAC_BD_RX_OR_MASK   (1 << EMAC_BD_RX_OR_SHIFT)
+#define EMAC_BD_RX_M_SHIFT   (7) /*!< Miss */
+#define EMAC_BD_RX_M_MASK    (1 << EMAC_BD_RX_M_SHIFT)
+#define EMAC_BD_RX_CF_SHIFT  (8) /*!< Control Frame Received */
+#define EMAC_BD_RX_CF_MASK   (1 << EMAC_BD_RX_CF_SHIFT)
+#define EMAC_BD_RX_WR_SHIFT  (13) /*!< Wrap */
+#define EMAC_BD_RX_WR_MASK   (1 << EMAC_BD_RX_WR_SHIFT)
+#define EMAC_BD_RX_IRQ_SHIFT (14) /*!< Interrupt Request Enable */
+#define EMAC_BD_RX_IRQ_MASK  (1 << EMAC_BD_RX_IRQ_SHIFT)
+#define EMAC_BD_RX_E_SHIFT   (15) /*!< The data buffer is empty (and ready for receiving data) or currently receiving data */
+#define EMAC_BD_RX_E_MASK    (1 << EMAC_BD_RX_E_SHIFT)
+#define EMAC_BD_RX_LEN_SHIFT (16) /*!< RX Data buffer length */
+#define EMAC_BD_RX_LEN_MASK  (0xffff << EMAC_BD_RX_LEN_SHIFT)
+
+/* MAX BD DESC 0x7FF */
+
+#endif /* __HARDWARE_EMAC_H__ */
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/gpio_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/gpio_reg.h
new file mode 100755
index 0000000000..bfba6cd840
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/gpio_reg.h
@@ -0,0 +1,2042 @@
+/**
+  ******************************************************************************
+  * @file    gpio_reg.h
+  * @version V1.0
+  * @date    2022-08-03
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __HARDWARE_GPIO_H__
+#define  __HARDWARE_GPIO_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#if defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+#define GLB_GPIO_CFG0_OFFSET                                    (0x8C4)/* gpio_cfg0 */
+#define GLB_GPIO_CFG1_OFFSET                                    (0x8C8)/* gpio_cfg1 */
+#define GLB_GPIO_CFG2_OFFSET                                    (0x8CC)/* gpio_cfg2 */
+#define GLB_GPIO_CFG3_OFFSET                                    (0x8D0)/* gpio_cfg3 */
+#define GLB_GPIO_CFG4_OFFSET                                    (0x8D4)/* gpio_cfg4 */
+#define GLB_GPIO_CFG5_OFFSET                                    (0x8D8)/* gpio_cfg5 */
+#define GLB_GPIO_CFG6_OFFSET                                    (0x8DC)/* gpio_cfg6 */
+#define GLB_GPIO_CFG7_OFFSET                                    (0x8E0)/* gpio_cfg7 */
+#define GLB_GPIO_CFG8_OFFSET                                    (0x8E4)/* gpio_cfg8 */
+#define GLB_GPIO_CFG9_OFFSET                                    (0x8E8)/* gpio_cfg9 */
+#define GLB_GPIO_CFG10_OFFSET                                   (0x8EC)/* gpio_cfg10 */
+#define GLB_GPIO_CFG11_OFFSET                                   (0x8F0)/* gpio_cfg11 */
+#define GLB_GPIO_CFG12_OFFSET                                   (0x8F4)/* gpio_cfg12 */
+#define GLB_GPIO_CFG13_OFFSET                                   (0x8F8)/* gpio_cfg13 */
+#define GLB_GPIO_CFG14_OFFSET                                   (0x8FC)/* gpio_cfg14 */
+#define GLB_GPIO_CFG15_OFFSET                                   (0x900)/* gpio_cfg15 */
+#define GLB_GPIO_CFG16_OFFSET                                   (0x904)/* gpio_cfg16 */
+#define GLB_GPIO_CFG17_OFFSET                                   (0x908)/* gpio_cfg17 */
+#define GLB_GPIO_CFG18_OFFSET                                   (0x90C)/* gpio_cfg18 */
+#define GLB_GPIO_CFG19_OFFSET                                   (0x910)/* gpio_cfg19 */
+#define GLB_GPIO_CFG20_OFFSET                                   (0x914)/* gpio_cfg20 */
+#define GLB_GPIO_CFG21_OFFSET                                   (0x918)/* gpio_cfg21 */
+#define GLB_GPIO_CFG22_OFFSET                                   (0x91C)/* gpio_cfg22 */
+#define GLB_GPIO_CFG23_OFFSET                                   (0x920)/* gpio_cfg23 */
+#define GLB_GPIO_CFG24_OFFSET                                   (0x924)/* gpio_cfg24 */
+#define GLB_GPIO_CFG25_OFFSET                                   (0x928)/* gpio_cfg25 */
+#define GLB_GPIO_CFG26_OFFSET                                   (0x92C)/* gpio_cfg26 */
+#define GLB_GPIO_CFG27_OFFSET                                   (0x930)/* gpio_cfg27 */
+#define GLB_GPIO_CFG28_OFFSET                                   (0x934)/* gpio_cfg28 */
+#define GLB_GPIO_CFG29_OFFSET                                   (0x938)/* gpio_cfg29 */
+#define GLB_GPIO_CFG30_OFFSET                                   (0x93C)/* gpio_cfg30 */
+#define GLB_GPIO_CFG31_OFFSET                                   (0x940)/* gpio_cfg31 */
+#define GLB_GPIO_CFG32_OFFSET                                   (0x944)/* gpio_cfg32 */
+#define GLB_GPIO_CFG33_OFFSET                                   (0x948)/* gpio_cfg33 */
+#define GLB_GPIO_CFG34_OFFSET                                   (0x94C)/* gpio_cfg34 */
+#define GLB_GPIO_CFG35_OFFSET                                   (0x950)/* gpio_cfg35 */
+#define GLB_GPIO_CFG36_OFFSET                                   (0x954)/* gpio_cfg36 */
+#define GLB_GPIO_CFG37_OFFSET                                   (0x958)/* gpio_cfg37 */
+#define GLB_GPIO_CFG38_OFFSET                                   (0x95C)/* gpio_cfg38 */
+#define GLB_GPIO_CFG39_OFFSET                                   (0x960)/* gpio_cfg39 */
+#define GLB_GPIO_CFG40_OFFSET                                   (0x964)/* gpio_cfg40 */
+#define GLB_GPIO_CFG41_OFFSET                                   (0x968)/* gpio_cfg41 */
+#define GLB_GPIO_CFG42_OFFSET                                   (0x96C)/* gpio_cfg42 */
+#define GLB_GPIO_CFG43_OFFSET                                   (0x970)/* gpio_cfg43 */
+#define GLB_GPIO_CFG44_OFFSET                                   (0x974)/* gpio_cfg44 */
+#define GLB_GPIO_CFG45_OFFSET                                   (0x978)/* gpio_cfg45 */
+#define GLB_GPIO_CFG46_OFFSET                                   (0x97C)/* gpio_cfg46 */
+#define GLB_GPIO_CFG47_OFFSET                                   (0x980)/* gpio_cfg47 */
+#define GLB_GPIO_CFG48_OFFSET                                   (0x984)/* gpio_cfg48 */
+#define GLB_GPIO_CFG49_OFFSET                                   (0x988)/* gpio_cfg49 */
+#define GLB_GPIO_CFG50_OFFSET                                   (0x98C)/* gpio_cfg50 */
+#define GLB_GPIO_CFG51_OFFSET                                   (0x990)/* gpio_cfg51 */
+#define GLB_GPIO_CFG52_OFFSET                                   (0x994)/* gpio_cfg52 */
+#define GLB_GPIO_CFG53_OFFSET                                   (0x998)/* gpio_cfg53 */
+#define GLB_GPIO_CFG54_OFFSET                                   (0x99C)/* gpio_cfg54 */
+#define GLB_GPIO_CFG55_OFFSET                                   (0x9A0)/* gpio_cfg55 */
+#define GLB_GPIO_CFG56_OFFSET                                   (0x9A4)/* gpio_cfg56 */
+#define GLB_GPIO_CFG57_OFFSET                                   (0x9A8)/* gpio_cfg57 */
+#define GLB_GPIO_CFG58_OFFSET                                   (0x9AC)/* gpio_cfg58 */
+#define GLB_GPIO_CFG59_OFFSET                                   (0x9B0)/* gpio_cfg59 */
+#define GLB_GPIO_CFG60_OFFSET                                   (0x9B4)/* gpio_cfg60 */
+#define GLB_GPIO_CFG61_OFFSET                                   (0x9B8)/* gpio_cfg61 */
+#define GLB_GPIO_CFG62_OFFSET                                   (0x9BC)/* gpio_cfg62 */
+#define GLB_GPIO_CFG63_OFFSET                                   (0x9C0)/* gpio_cfg63 */
+#define GLB_GPIO_CFG128_OFFSET                                  (0xAC4)/* gpio_cfg128 */
+#define GLB_GPIO_CFG129_OFFSET                                  (0xAC8)/* gpio_cfg129 */
+#define GLB_GPIO_CFG136_OFFSET                                  (0xAE4)/* gpio_cfg136 */
+#define GLB_GPIO_CFG137_OFFSET                                  (0xAE8)/* gpio_cfg137 */
+#define GLB_GPIO_CFG138_OFFSET                                  (0xAEC)/* gpio_cfg138 */
+#define GLB_GPIO_CFG139_OFFSET                                  (0xAF0)/* gpio_cfg139 */
+#define GLB_GPIO_CFG140_OFFSET                                  (0xAF4)/* gpio_cfg140 */
+#define GLB_GPIO_CFG141_OFFSET                                  (0xAF8)/* gpio_cfg141 */
+#define GLB_GPIO_CFG142_OFFSET                                  (0xAFC)/* gpio_cfg142 */
+#define GLB_GPIO_CFG143_OFFSET                                  (0xB00)/* gpio_cfg143 */
+#define GLB_GPIO_CFG144_OFFSET                                  (0xB04)/* gpio_cfg144 */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x8C4 : gpio_cfg0 */
+#define GLB_REG_GPIO_0_IE                                       (1<<0U)
+#define GLB_REG_GPIO_0_SMT                                      (1<<1U)
+#define GLB_REG_GPIO_0_DRV_SHIFT                                (2U)
+#define GLB_REG_GPIO_0_DRV_MASK                                 (0x3<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_I2C_H__
+#define __HARDWARE_I2C_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define I2C_CONFIG_OFFSET        (0x0)  /* i2c_config */
+#define I2C_INT_STS_OFFSET       (0x4)  /* i2c_int_sts */
+#define I2C_SUB_ADDR_OFFSET      (0x8)  /* i2c_sub_addr */
+#define I2C_BUS_BUSY_OFFSET      (0xC)  /* i2c_bus_busy */
+#define I2C_PRD_START_OFFSET     (0x10) /* i2c_prd_start */
+#define I2C_PRD_STOP_OFFSET      (0x14) /* i2c_prd_stop */
+#define I2C_PRD_DATA_OFFSET      (0x18) /* i2c_prd_data */
+#define I2C_FIFO_CONFIG_0_OFFSET (0x80) /* i2c_fifo_config_0 */
+#define I2C_FIFO_CONFIG_1_OFFSET (0x84) /* i2c_fifo_config_1 */
+#define I2C_FIFO_WDATA_OFFSET    (0x88) /* i2c_fifo_wdata */
+#define I2C_FIFO_RDATA_OFFSET    (0x8C) /* i2c_fifo_rdata */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : i2c_config */
+#define I2C_CR_I2C_M_EN              (1 << 0U)
+#define I2C_CR_I2C_PKT_DIR           (1 << 1U)
+#define I2C_CR_I2C_DEG_EN            (1 << 2U)
+#define I2C_CR_I2C_SCL_SYNC_EN       (1 << 3U)
+#define I2C_CR_I2C_SUB_ADDR_EN       (1 << 4U)
+#define I2C_CR_I2C_SUB_ADDR_BC_SHIFT (5U)
+#define I2C_CR_I2C_SUB_ADDR_BC_MASK  (0x3 << I2C_CR_I2C_SUB_ADDR_BC_SHIFT)
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628) || defined(BL702L)
+#define I2C_CR_I2C_10B_ADDR_EN    (1 << 7U)
+#define I2C_CR_I2C_SLV_ADDR_SHIFT (8U)
+#define I2C_CR_I2C_SLV_ADDR_MASK  (0x3ff << I2C_CR_I2C_SLV_ADDR_SHIFT)
+#define I2C_CR_I2C_PKT_LEN_SHIFT  (20U)
+#define I2C_CR_I2C_PKT_LEN_MASK   (0xff << I2C_CR_I2C_PKT_LEN_SHIFT)
+#else
+#define I2C_CR_I2C_SLV_ADDR_SHIFT (8U)
+#define I2C_CR_I2C_SLV_ADDR_MASK  (0x7f << I2C_CR_I2C_SLV_ADDR_SHIFT)
+#define I2C_CR_I2C_PKT_LEN_SHIFT  (16U)
+#define I2C_CR_I2C_PKT_LEN_MASK   (0xff << I2C_CR_I2C_PKT_LEN_SHIFT)
+#endif
+
+#define I2C_CR_I2C_DEG_CNT_SHIFT (28U)
+#define I2C_CR_I2C_DEG_CNT_MASK  (0xf << I2C_CR_I2C_DEG_CNT_SHIFT)
+
+/* 0x4 : i2c_int_sts */
+#define I2C_END_INT         (1 << 0U)
+#define I2C_TXF_INT         (1 << 1U)
+#define I2C_RXF_INT         (1 << 2U)
+#define I2C_NAK_INT         (1 << 3U)
+#define I2C_ARB_INT         (1 << 4U)
+#define I2C_FER_INT         (1 << 5U)
+#define I2C_CR_I2C_END_MASK (1 << 8U)
+#define I2C_CR_I2C_TXF_MASK (1 << 9U)
+#define I2C_CR_I2C_RXF_MASK (1 << 10U)
+#define I2C_CR_I2C_NAK_MASK (1 << 11U)
+#define I2C_CR_I2C_ARB_MASK (1 << 12U)
+#define I2C_CR_I2C_FER_MASK (1 << 13U)
+#define I2C_CR_I2C_END_CLR  (1 << 16U)
+#define I2C_CR_I2C_NAK_CLR  (1 << 19U)
+#define I2C_CR_I2C_ARB_CLR  (1 << 20U)
+#define I2C_CR_I2C_END_EN   (1 << 24U)
+#define I2C_CR_I2C_TXF_EN   (1 << 25U)
+#define I2C_CR_I2C_RXF_EN   (1 << 26U)
+#define I2C_CR_I2C_NAK_EN   (1 << 27U)
+#define I2C_CR_I2C_ARB_EN   (1 << 28U)
+#define I2C_CR_I2C_FER_EN   (1 << 29U)
+
+/* 0x8 : i2c_sub_addr */
+#define I2C_CR_I2C_SUB_ADDR_B0_SHIFT (0U)
+#define I2C_CR_I2C_SUB_ADDR_B0_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B0_SHIFT)
+#define I2C_CR_I2C_SUB_ADDR_B1_SHIFT (8U)
+#define I2C_CR_I2C_SUB_ADDR_B1_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B1_SHIFT)
+#define I2C_CR_I2C_SUB_ADDR_B2_SHIFT (16U)
+#define I2C_CR_I2C_SUB_ADDR_B2_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B2_SHIFT)
+#define I2C_CR_I2C_SUB_ADDR_B3_SHIFT (24U)
+#define I2C_CR_I2C_SUB_ADDR_B3_MASK  (0xff << I2C_CR_I2C_SUB_ADDR_B3_SHIFT)
+
+/* 0xC : i2c_bus_busy */
+#define I2C_STS_I2C_BUS_BUSY    (1 << 0U)
+#define I2C_CR_I2C_BUS_BUSY_CLR (1 << 1U)
+
+/* 0x10 : i2c_prd_start */
+#define I2C_CR_I2C_PRD_S_PH_0_SHIFT (0U)
+#define I2C_CR_I2C_PRD_S_PH_0_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_0_SHIFT)
+#define I2C_CR_I2C_PRD_S_PH_1_SHIFT (8U)
+#define I2C_CR_I2C_PRD_S_PH_1_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_1_SHIFT)
+#define I2C_CR_I2C_PRD_S_PH_2_SHIFT (16U)
+#define I2C_CR_I2C_PRD_S_PH_2_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_2_SHIFT)
+#define I2C_CR_I2C_PRD_S_PH_3_SHIFT (24U)
+#define I2C_CR_I2C_PRD_S_PH_3_MASK  (0xff << I2C_CR_I2C_PRD_S_PH_3_SHIFT)
+
+/* 0x14 : i2c_prd_stop */
+#define I2C_CR_I2C_PRD_P_PH_0_SHIFT (0U)
+#define I2C_CR_I2C_PRD_P_PH_0_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_0_SHIFT)
+#define I2C_CR_I2C_PRD_P_PH_1_SHIFT (8U)
+#define I2C_CR_I2C_PRD_P_PH_1_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_1_SHIFT)
+#define I2C_CR_I2C_PRD_P_PH_2_SHIFT (16U)
+#define I2C_CR_I2C_PRD_P_PH_2_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_2_SHIFT)
+#define I2C_CR_I2C_PRD_P_PH_3_SHIFT (24U)
+#define I2C_CR_I2C_PRD_P_PH_3_MASK  (0xff << I2C_CR_I2C_PRD_P_PH_3_SHIFT)
+
+/* 0x18 : i2c_prd_data */
+#define I2C_CR_I2C_PRD_D_PH_0_SHIFT (0U)
+#define I2C_CR_I2C_PRD_D_PH_0_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_0_SHIFT)
+#define I2C_CR_I2C_PRD_D_PH_1_SHIFT (8U)
+#define I2C_CR_I2C_PRD_D_PH_1_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_1_SHIFT)
+#define I2C_CR_I2C_PRD_D_PH_2_SHIFT (16U)
+#define I2C_CR_I2C_PRD_D_PH_2_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_2_SHIFT)
+#define I2C_CR_I2C_PRD_D_PH_3_SHIFT (24U)
+#define I2C_CR_I2C_PRD_D_PH_3_MASK  (0xff << I2C_CR_I2C_PRD_D_PH_3_SHIFT)
+
+/* 0x80 : i2c_fifo_config_0 */
+#define I2C_DMA_TX_EN         (1 << 0U)
+#define I2C_DMA_RX_EN         (1 << 1U)
+#define I2C_TX_FIFO_CLR       (1 << 2U)
+#define I2C_RX_FIFO_CLR       (1 << 3U)
+#define I2C_TX_FIFO_OVERFLOW  (1 << 4U)
+#define I2C_TX_FIFO_UNDERFLOW (1 << 5U)
+#define I2C_RX_FIFO_OVERFLOW  (1 << 6U)
+#define I2C_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x84 : i2c_fifo_config_1 */
+#define I2C_TX_FIFO_CNT_SHIFT (0U)
+#define I2C_TX_FIFO_CNT_MASK  (0x3 << I2C_TX_FIFO_CNT_SHIFT)
+#define I2C_RX_FIFO_CNT_SHIFT (8U)
+#define I2C_RX_FIFO_CNT_MASK  (0x3 << I2C_RX_FIFO_CNT_SHIFT)
+#define I2C_TX_FIFO_TH        (1 << 16U)
+#define I2C_RX_FIFO_TH        (1 << 24U)
+
+/* 0x88 : i2c_fifo_wdata */
+#define I2C_FIFO_WDATA_SHIFT (0U)
+#define I2C_FIFO_WDATA_MASK  (0xffffffff << I2C_FIFO_WDATA_SHIFT)
+
+/* 0x8C : i2c_fifo_rdata */
+#define I2C_FIFO_RDATA_SHIFT (0U)
+#define I2C_FIFO_RDATA_MASK  (0xffffffff << I2C_FIFO_RDATA_SHIFT)
+
+#endif /* __HARDWARE_I2C_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/i2s_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/i2s_reg.h
new file mode 100755
index 0000000000..e5bc85c158
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/i2s_reg.h
@@ -0,0 +1,135 @@
+/**
+  ******************************************************************************
+  * @file    i2s_reg.h
+  * @version V1.0
+  * @date    2023-01-03
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __I2S_REG_H__
+#define __I2S_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define I2S_CONFIG_OFFSET        (0x0)  /* i2s_config */
+#define I2S_INT_STS_OFFSET       (0x4)  /* i2s_int_sts */
+#define I2S_BCLK_CONFIG_OFFSET   (0x10) /* i2s_bclk_config */
+#define I2S_FIFO_CONFIG_0_OFFSET (0x80) /* i2s_fifo_config_0 */
+#define I2S_FIFO_CONFIG_1_OFFSET (0x84) /* i2s_fifo_config_1 */
+#define I2S_FIFO_WDATA_OFFSET    (0x88) /* i2s_fifo_wdata */
+#define I2S_FIFO_RDATA_OFFSET    (0x8C) /* i2s_fifo_rdata */
+#define I2S_IO_CONFIG_OFFSET     (0xFC) /* i2s_io_config */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : i2s_config */
+#define I2S_CR_I2S_M_EN         (1 << 0U)
+#define I2S_CR_I2S_S_EN         (1 << 1U)
+#define I2S_CR_I2S_TXD_EN       (1 << 2U)
+#define I2S_CR_I2S_RXD_EN       (1 << 3U)
+#define I2S_CR_MONO_MODE        (1 << 4U)
+#define I2S_CR_MUTE_MODE        (1 << 5U)
+#define I2S_CR_FS_1T_MODE       (1 << 6U)
+#define I2S_CR_FS_CH_CNT_SHIFT  (7U)
+#define I2S_CR_FS_CH_CNT_MASK   (0x3 << I2S_CR_FS_CH_CNT_SHIFT)
+#define I2S_CR_FRAME_SIZE_SHIFT (12U)
+#define I2S_CR_FRAME_SIZE_MASK  (0x3 << I2S_CR_FRAME_SIZE_SHIFT)
+#define I2S_CR_DATA_SIZE_SHIFT  (14U)
+#define I2S_CR_DATA_SIZE_MASK   (0x3 << I2S_CR_DATA_SIZE_SHIFT)
+#define I2S_CR_I2S_MODE_SHIFT   (16U)
+#define I2S_CR_I2S_MODE_MASK    (0x3 << I2S_CR_I2S_MODE_SHIFT)
+#define I2S_CR_ENDIAN           (1 << 18U)
+#define I2S_CR_MONO_RX_CH       (1 << 19U)
+#define I2S_CR_OFS_CNT_SHIFT    (20U)
+#define I2S_CR_OFS_CNT_MASK     (0x1f << I2S_CR_OFS_CNT_SHIFT)
+#define I2S_CR_OFS_EN           (1 << 25U)
+
+/* 0x4 : i2s_int_sts */
+#define I2S_TXF_INT         (1 << 0U)
+#define I2S_RXF_INT         (1 << 1U)
+#define I2S_FER_INT         (1 << 2U)
+#define I2S_CR_I2S_TXF_MASK (1 << 8U)
+#define I2S_CR_I2S_RXF_MASK (1 << 9U)
+#define I2S_CR_I2S_FER_MASK (1 << 10U)
+#define I2S_CR_I2S_TXF_EN   (1 << 24U)
+#define I2S_CR_I2S_RXF_EN   (1 << 25U)
+#define I2S_CR_I2S_FER_EN   (1 << 26U)
+
+/* 0x10 : i2s_bclk_config */
+#define I2S_CR_BCLK_DIV_L_SHIFT (0U)
+#define I2S_CR_BCLK_DIV_L_MASK  (0xfff << I2S_CR_BCLK_DIV_L_SHIFT)
+#define I2S_CR_BCLK_DIV_H_SHIFT (16U)
+#define I2S_CR_BCLK_DIV_H_MASK  (0xfff << I2S_CR_BCLK_DIV_H_SHIFT)
+
+/* 0x80 : i2s_fifo_config_0 */
+#define I2S_DMA_TX_EN         (1 << 0U)
+#define I2S_DMA_RX_EN         (1 << 1U)
+#define I2S_TX_FIFO_CLR       (1 << 2U)
+#define I2S_RX_FIFO_CLR       (1 << 3U)
+#define I2S_TX_FIFO_OVERFLOW  (1 << 4U)
+#define I2S_TX_FIFO_UNDERFLOW (1 << 5U)
+#define I2S_RX_FIFO_OVERFLOW  (1 << 6U)
+#define I2S_RX_FIFO_UNDERFLOW (1 << 7U)
+#define I2S_CR_FIFO_LR_MERGE  (1 << 8U)
+#define I2S_CR_FIFO_LR_EXCHG  (1 << 9U)
+#define I2S_CR_FIFO_24B_LJ    (1 << 10U)
+
+/* 0x84 : i2s_fifo_config_1 */
+#define I2S_TX_FIFO_CNT_SHIFT (0U)
+#define I2S_TX_FIFO_CNT_MASK  (0x1f << I2S_TX_FIFO_CNT_SHIFT)
+#define I2S_RX_FIFO_CNT_SHIFT (8U)
+#define I2S_RX_FIFO_CNT_MASK  (0x1f << I2S_RX_FIFO_CNT_SHIFT)
+#define I2S_TX_FIFO_TH_SHIFT  (16U)
+#define I2S_TX_FIFO_TH_MASK   (0xf << I2S_TX_FIFO_TH_SHIFT)
+#define I2S_RX_FIFO_TH_SHIFT  (24U)
+#define I2S_RX_FIFO_TH_MASK   (0xf << I2S_RX_FIFO_TH_SHIFT)
+
+/* 0x88 : i2s_fifo_wdata */
+#define I2S_FIFO_WDATA_SHIFT (0U)
+#define I2S_FIFO_WDATA_MASK  (0xffffffff << I2S_FIFO_WDATA_SHIFT)
+
+/* 0x8C : i2s_fifo_rdata */
+#define I2S_FIFO_RDATA_SHIFT (0U)
+#define I2S_FIFO_RDATA_MASK  (0xffffffff << I2S_FIFO_RDATA_SHIFT)
+
+/* 0xFC : i2s_io_config */
+#define I2S_CR_I2S_TXD_INV   (1 << 0U)
+#define I2S_CR_I2S_RXD_INV   (1 << 1U)
+#define I2S_CR_I2S_FS_INV    (1 << 2U)
+#define I2S_CR_I2S_BCLK_INV  (1 << 3U)
+#define I2S_CR_DEG_CNT_SHIFT (4U)
+#define I2S_CR_DEG_CNT_MASK  (0x7 << I2S_CR_DEG_CNT_SHIFT)
+#define I2S_CR_DEG_EN        (1 << 7U)
+
+#endif /* __I2S_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/ir_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/ir_reg.h
new file mode 100755
index 0000000000..1ae989454b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/ir_reg.h
@@ -0,0 +1,338 @@
+/**
+  ******************************************************************************
+  * @file    ir_reg.h
+  * @version V1.0
+  * @date    2022-09-28
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_IR_H__
+#define __HARDWARE_IR_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#if !defined(BL616)
+#define IRTX_CONFIG_OFFSET      (0x0)  /* irtx_config */
+#define IRTX_INT_STS_OFFSET     (0x4)  /* irtx_int_sts */
+#if defined(BL602) || defined(BL702)
+#define IRTX_DATA_WORD0_OFFSET  (0x8)  /* irtx_data_word0 */
+#define IRTX_DATA_WORD1_OFFSET  (0xC)  /* irtx_data_word1 */
+#endif
+#define IRTX_PULSE_WIDTH_OFFSET (0x10) /* irtx_pulse_width */
+#if defined(BL602) || defined(BL702)
+#define IRTX_PW_OFFSET          (0x14) /* irtx_pw */
+#define IRTX_SWM_PW_0_OFFSET    (0x40) /* irtx_swm_pw_0 */
+#define IRTX_SWM_PW_1_OFFSET    (0x44) /* irtx_swm_pw_1 */
+#define IRTX_SWM_PW_2_OFFSET    (0x48) /* irtx_swm_pw_2 */
+#define IRTX_SWM_PW_3_OFFSET    (0x4C) /* irtx_swm_pw_3 */
+#define IRTX_SWM_PW_4_OFFSET    (0x50) /* irtx_swm_pw_4 */
+#define IRTX_SWM_PW_5_OFFSET    (0x54) /* irtx_swm_pw_5 */
+#define IRTX_SWM_PW_6_OFFSET    (0x58) /* irtx_swm_pw_6 */
+#define IRTX_SWM_PW_7_OFFSET    (0x5C) /* irtx_swm_pw_7 */
+#else
+#define IRTX_PW_0_OFFSET        (0x14) /* irtx_pw_0 */
+#define IRTX_PW_1_OFFSET        (0x18) /* irtx_pw_1 */
+#endif
+#endif
+#if !defined(BL702L)
+#if defined(BL602) || defined(BL702)
+#define IRRX_CONFIG_OFFSET      (0x80) /* irrx_config */
+#define IRRX_INT_STS_OFFSET     (0x84) /* irrx_int_sts */
+#define IRRX_PW_CONFIG_OFFSET   (0x88) /* irrx_pw_config */
+#define IRRX_DATA_COUNT_OFFSET  (0x90) /* irrx_data_count */
+#define IRRX_DATA_WORD0_OFFSET  (0x94) /* irrx_data_word0 */
+#define IRRX_DATA_WORD1_OFFSET  (0x98) /* irrx_data_word1 */
+#else
+#define IRRX_CONFIG_OFFSET      (0x40) /* irrx_config */
+#define IRRX_INT_STS_OFFSET     (0x44) /* irrx_int_sts */
+#define IRRX_PW_CONFIG_OFFSET   (0x48) /* irrx_pw_config */
+#define IRRX_DATA_COUNT_OFFSET  (0x50) /* irrx_data_count */
+#define IRRX_DATA_WORD0_OFFSET  (0x54) /* irrx_data_word0 */
+#define IRRX_DATA_WORD1_OFFSET  (0x58) /* irrx_data_word1 */
+#endif
+#endif
+#if defined(BL602) || defined(BL702)
+#define IRRX_SWM_FIFO_CONFIG_0_OFFSET (0xC0) /* irrx_swm_fifo_config_0 */
+#define IRRX_SWM_FIFO_RDATA_OFFSET    (0xC4) /* irrx_swm_fifo_rdata */
+#else
+#define IR_FIFO_CONFIG_0_OFFSET (0x80) /* ir_fifo_config_0 */
+#define IR_FIFO_CONFIG_1_OFFSET (0x84) /* ir_fifo_config_1 */
+#define IR_FIFO_WDATA_OFFSET    (0x88) /* ir_fifo_wdata */
+#if !defined(BL702L)
+#define IR_FIFO_RDATA_OFFSET    (0x8C) /* ir_fifo_rdata */
+#endif
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+#if !defined(BL616)
+/* 0x0 : irtx_config */
+#define IR_CR_IRTX_EN                   (1 << 0U)
+#define IR_CR_IRTX_OUT_INV              (1 << 1U)
+#define IR_CR_IRTX_MOD_EN               (1 << 2U)
+#define IR_CR_IRTX_SWM_EN               (1 << 3U)
+#define IR_CR_IRTX_DATA_EN              (1 << 4U)
+#define IR_CR_IRTX_LOGIC0_HL_INV        (1 << 5U)
+#define IR_CR_IRTX_LOGIC1_HL_INV        (1 << 6U)
+#define IR_CR_IRTX_HEAD_EN              (1 << 8U)
+#define IR_CR_IRTX_HEAD_HL_INV          (1 << 9U)
+#define IR_CR_IRTX_TAIL_EN              (1 << 10U)
+#define IR_CR_IRTX_TAIL_HL_INV          (1 << 11U)
+#if defined(BL602) || defined(BL702)
+#define IR_CR_IRTX_DATA_NUM_SHIFT       (12U)
+#define IR_CR_IRTX_DATA_NUM_MASK        (0x3f << IR_CR_IRTX_DATA_NUM_SHIFT)
+#else
+#define IR_CR_IRTX_FRM_EN               (1 << 12U)
+#define IR_CR_IRTX_FRM_CONT_EN          (1 << 13U)
+#define IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT (14U)
+#define IR_CR_IRTX_FRM_FRAME_SIZE_MASK  (0x3 << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT)
+#define IR_CR_IRTX_DATA_NUM_SHIFT       (16U)
+#define IR_CR_IRTX_DATA_NUM_MASK        (0x7f << IR_CR_IRTX_DATA_NUM_SHIFT)
+#endif
+
+/* 0x4 : irtx_int_sts */
+#define IRTX_END_INT         (1 << 0U)
+#if !defined(BL602) && !defined(BL702)
+#define IRTX_FRDY_INT        (1 << 1U)
+#define IRTX_FER_INT         (1 << 2U)
+#endif
+#define IR_CR_IRTX_END_MASK  (1 << 8U)
+#if !defined(BL602) && !defined(BL702)
+#define IR_CR_IRTX_FRDY_MASK (1 << 9U)
+#define IR_CR_IRTX_FER_MASK  (1 << 10U)
+#endif
+#define IR_CR_IRTX_END_CLR   (1 << 16U)
+#define IR_CR_IRTX_END_EN    (1 << 24U)
+#if !defined(BL602) && !defined(BL702)
+#define IR_CR_IRTX_FRDY_EN   (1 << 25U)
+#define IR_CR_IRTX_FER_EN    (1 << 26U)
+#else
+/* 0x8 : irtx_data_word0 */
+#define IR_CR_IRTX_DATA_WORD0_SHIFT (0U)
+#define IR_CR_IRTX_DATA_WORD0_MASK  (0xffffffff<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __ISO11898_REG_H__
+#define  __ISO11898_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define ISO11898_MODE_OFFSET                                    (0x0)/* mode */
+#define ISO11898_COMMAND_OFFSET                                 (0x4)/* command */
+#define ISO11898_STATUS_OFFSET                                  (0x8)/* status */
+#define ISO11898_INTERRUPT_OFFSET                               (0xc)/* interrupt */
+#define ISO11898_INTERRUPT_ENABLE_OFFSET                        (0x10)/* interrupt_enable */
+#define ISO11898_BUS_TIMING_0_OFFSET                            (0x18)/* bus_timing_0 */
+#define ISO11898_BUS_TIMING_1_OFFSET                            (0x1c)/* bus_timing_1 */
+#define ISO11898_ARB_LOST_CAPTURE_OFFSET                        (0x2c)/* arb_lost_capture */
+#define ISO11898_ERROR_CODE_CAPTURE_OFFSET                      (0x30)/* error_code_capture */
+#define ISO11898_ERROR_WARNING_LIMIT_OFFSET                     (0x34)/* error_warning_limit */
+#define ISO11898_RX_ERR_COUNT_OFFSET                            (0x38)/* rx_err_count */
+#define ISO11898_TX_ERR_COUNT_OFFSET                            (0x3c)/* tx_err_count */
+#define ISO11898_FRAME_INFORMATION_OFFSET                       (0x40)/* frame_information */
+#define ISO11898_ACCEPTANCE_CODE_0_OFFSET                       (0x40)/* acceptance_code_0 */
+#define ISO11898_SFF_ID1_OFFSET                                 (0x44)/* sff_id1 */
+#define ISO11898_EFF_ID1_OFFSET                                 (0x44)/* eff_id1 */
+#define ISO11898_ACCEPTANCE_CODE_1_OFFSET                       (0x44)/* acceptance_code_1 */
+#define ISO11898_SFF_ID2_OFFSET                                 (0x48)/* sff_id2 */
+#define ISO11898_EFF_ID2_OFFSET                                 (0x48)/* eff_id2 */
+#define ISO11898_ACCEPTANCE_CODE_2_OFFSET                       (0x48)/* acceptance_code_2 */
+#define ISO11898_SFF_DATA1_OFFSET                               (0x4c)/* sff_data1 */
+#define ISO11898_EFF_ID3_OFFSET                                 (0x4c)/* eff_id3 */
+#define ISO11898_ACCEPTANCE_CODE_3_OFFSET                       (0x4c)/* acceptance_code_3 */
+#define ISO11898_SFF_DATA2_OFFSET                               (0x50)/* sff_data2 */
+#define ISO11898_EFF_ID4_OFFSET                                 (0x50)/* eff_id4 */
+#define ISO11898_ACCEPTANCE_MASK_0_OFFSET                       (0x50)/* acceptance_mask_0 */
+#define ISO11898_SFF_DATA3_OFFSET                               (0x54)/* sff_data3 */
+#define ISO11898_EFF_DATA1_OFFSET                               (0x54)/* eff_data1 */
+#define ISO11898_ACCEPTANCE_MASK_1_OFFSET                       (0x54)/* acceptance_mask_1 */
+#define ISO11898_SFF_DATA4_OFFSET                               (0x58)/* sff_data4 */
+#define ISO11898_EFF_DATA2_OFFSET                               (0x58)/* eff_data2 */
+#define ISO11898_ACCEPTANCE_MASK_2_OFFSET                       (0x58)/* acceptance_mask_2 */
+#define ISO11898_SFF_DATA5_OFFSET                               (0x5c)/* sff_data5 */
+#define ISO11898_EFF_DATA3_OFFSET                               (0x5c)/* eff_data3 */
+#define ISO11898_ACCEPTANCE_MASK_3_OFFSET                       (0x5c)/* acceptance_mask_3 */
+#define ISO11898_SFF_DATA6_OFFSET                               (0x60)/* sff_data6 */
+#define ISO11898_EFF_DATA4_OFFSET                               (0x60)/* eff_data4 */
+#define ISO11898_SFF_DATA7_OFFSET                               (0x64)/* sff_data7 */
+#define ISO11898_EFF_DATA5_OFFSET                               (0x64)/* eff_data5 */
+#define ISO11898_SFF_DATA8_OFFSET                               (0x68)/* sff_data8 */
+#define ISO11898_EFF_DATA6_OFFSET                               (0x68)/* eff_data6 */
+#define ISO11898_EFF_DATA7_OFFSET                               (0x6c)/* eff_data7 */
+#define ISO11898_EFF_DATA8_OFFSET                               (0x70)/* eff_data8 */
+#define ISO11898_RX_MESSAGE_COUNT_OFFSET                        (0x74)/* rx_message_count */
+#define ISO11898_CLOCK_DIVIDER_OFFSET                           (0x7c)/* clock_divider */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : mode */
+#define ISO11898_RESET_REQUEST                                  (1<<0U)
+#define ISO11898_LISTEN_ONLY                                    (1<<1U)
+#define ISO11898_SELF_TEST                                      (1<<2U)
+#define ISO11898_FILTER_TYPE                                    (1<<3U)
+
+/* 0x4 : command */
+#define ISO11898_TRANSMIT_REQUEST                               (1<<0U)
+#define ISO11898_ABORT_TRANSMISSION                             (1<<1U)
+#define ISO11898_RELEASE_RECEIVE_BUFFER                         (1<<2U)
+#define ISO11898_CLEAR_DATA_OVERRUN                             (1<<3U)
+#define ISO11898_SELF_REQUEST                                   (1<<4U)
+
+/* 0x8 : status */
+#define ISO11898_RECEIVE_BUFFER_STS                             (1<<0U)
+#define ISO11898_DATA_OVERRUN_STS                               (1<<1U)
+#define ISO11898_TRANSMIT_BUFFER_STS                            (1<<2U)
+#define ISO11898_TRANSMIT_COMPLETE_STS                          (1<<3U)
+#define ISO11898_RECEIVE_STS                                    (1<<4U)
+#define ISO11898_TRANSMIT_STS                                   (1<<5U)
+#define ISO11898_ERROR_STS                                      (1<<6U)
+#define ISO11898_BUS_STS                                        (1<<7U)
+
+/* 0xc : interrupt */
+#define ISO11898_RECEIVE_INT                                    (1<<0U)
+#define ISO11898_TRANSMIT_INT                                   (1<<1U)
+#define ISO11898_ERROR_INT                                      (1<<2U)
+#define ISO11898_DATA_OVERRUN_INT                               (1<<3U)
+#define ISO11898_ERROR_PASSIVE_INT                              (1<<5U)
+#define ISO11898_ARB_LOST_INT                                   (1<<6U)
+#define ISO11898_BUS_ERROR_INT                                  (1<<7U)
+
+/* 0x10 : interrupt_enable */
+#define ISO11898_RECEIVE_INT_EN                                 (1<<0U)
+#define ISO11898_TRANSMIT_INT_EN                                (1<<1U)
+#define ISO11898_ERROR_INT_EN                                   (1<<2U)
+#define ISO11898_DATA_OVERRUN_INT_EN                            (1<<3U)
+#define ISO11898_ERROR_PASSIVE_INT_EN                           (1<<5U)
+#define ISO11898_ARB_LOST_INT_EN                                (1<<6U)
+#define ISO11898_BUS_ERROR_INT_EN                               (1<<7U)
+
+/* 0x18 : bus_timing_0 */
+#define ISO11898_BAUD_RATE_PRESCALER_SHIFT                      (0U)
+#define ISO11898_BAUD_RATE_PRESCALER_MASK                       (0x3f<
© COPYRIGHT(c) 2022 Bouffalo Lab

+ *
+ * Redistribution and use in source and binary forms, with or without
+ *modification, are permitted provided that the following conditions are met:
+ *   1. Redistributions of source code must retain the above copyright notice,
+ *      this list of conditions and the following disclaimer.
+ *   2. Redistributions in binary form must reproduce the above copyright
+ *notice, this list of conditions and the following disclaimer in the
+ *documentation and/or other materials provided with the distribution.
+ *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+ *      may be used to endorse or promote products derived from this software
+ *      without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
+ *ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
+ *LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
+ *CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
+ *SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
+ *INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
+ *CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
+ *ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ *POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#ifndef __HARDWARE_KYS_H__
+#define __HARDWARE_KYS_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#define KYS_KS_CTRL_OFFSET     (0x0)
+#define KYS_KS_INT_EN_OFFSET   (0x10)
+#define KYS_KS_INT_STS_OFFSET  (0x14)
+#define KYS_KEYCODE_CLR_OFFSET (0x18)
+#if defined(bl702)
+#define KYS_KEYFIFO_VALUE_OFFSET (0x1C)
+#else
+#define KYS_KEYFIFO_IDX_OFFSET   (0x30)
+#define KYS_KEYFIFO_VALUE_OFFSET (0x34)
+#endif
+
+/* 0x0 : ks_ctrl */
+#define KYS_KS_EN_SHIFT    (0U)
+#define KYS_KS_EN_MASK     (0x1 << KYS_KS_EN_SHIFT)
+#define KYS_GHOST_EN_SHIFT (2U)
+#define KYS_GHOST_EN_MASK  (0x1 << KYS_GHOST_EN_SHIFT)
+#define KYS_DEG_EN_SHIFT   (3U)
+#define KYS_DEG_EN_MASK    (0x1 << KYS_DEG_EN_SHIFT)
+#define KYS_DEG_CNT_SHIFT  (4U)
+#define KYS_DEG_CNT_MASK   (0xf << KYS_DEG_CNT_SHIFT)
+#define KYS_RC_EXT_SHIFT   (8U)
+#define KYS_RC_EXT_MASK    (0x3 << KYS_RC_EXT_SHIFT)
+#define KYS_ROW_NUM_SHIFT  (16U)
+#define KYS_ROW_NUM_MASK   (0x7 << KYS_ROW_NUM_SHIFT)
+#if defined(bl702)
+#define KYS_COL_NUM_SHIFT (20U)
+#define KYS_COL_NUM_MASK  (0x7 << KYS_COL_NUM_SHIFT)
+#else
+#define KYS_FIFO_MODE_SHIFT (1U)
+#define KYS_FIFO_MODE_MASK  (0x1 << KYS_FIFO_MODE_SHIFT)
+#define KYS_COL_NUM_SHIFT   (20U)
+#define KYS_COL_NUM_MASK    (0x1f << KYS_COL_NUM_SHIFT)
+#endif
+
+/* 0x10 : ks_int_en */
+#if defined(bl702)
+#define KYS_KS_INT_EN_SHIFT (0U)
+#define KYS_KS_INT_EN_MASK  (0x1 << KYS_KS_INT_EN_SHIFT)
+#else
+#define KYS_KS_DONE_INT_EN_SHIFT          (7U)
+#define KYS_KS_DONE_INT_EN_MASK           (0x1 << KYS_KS_DONE_INT_EN_SHIFT)
+#define KYS_KEYFIFO_FULL_INT_EN_SHIFT     (8U)
+#define KYS_KEYFIFO_FULL_INT_EN_MASK      (0x1 << KYS_KEYFIFO_FULL_INT_EN_SHIFT)
+#define KYS_KEYFIFO_HALF_INT_EN_SHIFT     (9U)
+#define KYS_KEYFIFO_HALF_INT_EN_MASK      (0x1 << KYS_KEYFIFO_HALF_INT_EN_SHIFT)
+#define KYS_KEYFIFO_QUARTER_INT_EN_SHIFT  (10U)
+#define KYS_KEYFIFO_QUARTER_INT_EN_MASK   (0x1 << KYS_KEYFIFO_QUARTER_INT_EN_SHIFT)
+#define KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT (11U)
+#define KYS_KEYFIFO_NONEMPTY_INT_EN_MASK  (0x1 << KYS_KEYFIFO_NONEMPTY_INT_EN_SHIFT)
+#define KYS_GHOST_INT_EN_SHIFT            (12U)
+#define KYS_GHOST_INT_EN_MASK             (0x1 << KYS_GHOST_INT_EN_SHIFT)
+#endif
+
+/* 0x14 : ks_int_sts */
+#if defined(bl702)
+#define KYS_KEYCODE_VALID_SHIFT (0U)
+#define KYS_KEYCODE_VALID_MASK  (0xf << KYS_KEYCODE_VALID_SHIFT)
+#else
+#define KYS_KEYCODE_DONE_SHIFT     (7U)
+#define KYS_KEYCODE_DONE_MASK      (0x1 << KYS_KEYCODE_DONE_SHIFT)
+#define KYS_KEYFIFO_FULL_SHIFT     (8U)
+#define KYS_KEYFIFO_FULL_MASK      (0x1 << KYS_KEYFIFO_FULL_SHIFT)
+#define KYS_KEYFIFO_HALF_SHIFT     (9U)
+#define KYS_KEYFIFO_HALF_MSK       (0x1 << KYS_KEYFIFO_HALF_SHIFT)
+#define KYS_KEYFIFO_QUARTER_SHIFT  (10U)
+#define KYS_KEYFIFO_QUARTER_MSK    (0x1 << KYS_KEYFIFO_QUARTER_SHIFT)
+#define KYS_KEYFIFO_NONEMPTY_SHIFT (11U)
+#define KYS_KEYFIFO_NONEMPTY_MSK   (0x1 << KYS_KEYFIFO_NONEMPTY_SHIFT)
+#define KYS_GHOST_DET_SHIFT        (12U)
+#define KYS_GHOST_DET_MASK         (0x1 << KYS_GHOST_DET_SHIFT)
+#endif
+
+/* 0x18 : keycode_clr */
+#if defined(bl702)
+#define KYS_KEYCODE_CLR_SHIFT (0U)
+#define KYS_KEYCODE_CLR_MASK  (0xf << KYS_KEYCODE_CLR_SHIFT)
+#else
+#define KYS_KS_DONE_CLR_SHIFT      (7U)
+#define KYS_KS_DONE_CLR_MASK       (0x1 << KYS_KS_DONE_CLR_SHIFT)
+#define KYS_KEYFIFO_FULL_CLR_SHIFT (8U)
+#define KYS_KEYFIFO_FULL_CLR_MASK  (0x1 << KYS_KEYFIFO_FULL_CLR_SHIFT)
+#define KYS_GHOST_CLR_SHIFT        (12U)
+#define KYS_GHOST_CLR_MASK         (0x1 << KYS_GHOST_CLR_SHIFT)
+#endif
+
+#if defined(bl702)
+/* 0x1c : keycode value */
+#define KYS_KEYCODE0_SHIFT (0U)
+#define KYS_KEYCODE0_MASK  (0xff << KYS_KEYCODE0_SHIFT)
+#define KYS_KEYCODE1_SHIFT (8U)
+#define KYS_KEYCODE1_MASK  (0xff << KYS_KEYCODE1_SHIFT)
+#define KYS_KEYCODE2_SHIFT (16U)
+#define KYS_KEYCODE2_MASK  (0xff << KYS_KEYCODE2_SHIFT)
+#define KYS_KEYCODE3_SHIFT (24U)
+#define KYS_KEYCODE3_MASK  (0xff << KYS_KEYCODE3_SHIFT)
+#endif
+
+#if defined(bl702l)
+/* 0x30 : keyfifo_idx */
+#define KYS_KEYFIFO_HEAD_SHIFT (0U)
+#define KYS_KEYFIFO_HEAD_MASK  (0x7 << KYS_KEYFIFO_HEAD_SHIFT)
+#define KYS_KEYFIFO_TAIL_SHIFT (8U)
+#define KYS_KEYFIFO_TAIL_MASK  (0x7 << KYS_KEYFIFO_TAIL_SHIFT)
+
+/* 0x34 : keyfifo_value */
+#define KYS_KEYFIFO_VALUE_SHIFT (0U)
+#define KYS_KEYFIFO_VALUE_MASK  (0xff << KYS_KEYFIFO_VALUE_SHIFT)
+#endif
+
+#endif /* __HARDWARE_KYS_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/mjpeg_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/mjpeg_reg.h
new file mode 100755
index 0000000000..1fbd4f6941
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/mjpeg_reg.h
@@ -0,0 +1,319 @@
+/**
+  ******************************************************************************
+  * @file    mjpeg_reg.h
+  * @version V1.0
+  * @date    2022-11-01
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __HARDWARE_MJPEG_REG_H__
+#define  __HARDWARE_MJPEG_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define MJPEG_CONTROL_1_OFFSET                                  (0x0)/* mjpeg_control_1 */
+#define MJPEG_CONTROL_2_OFFSET                                  (0x4)/* mjpeg_control_2 */
+#define MJPEG_YY_FRAME_ADDR_OFFSET                              (0x08)/* mjpeg_yy_frame_addr */
+#define MJPEG_UV_FRAME_ADDR_OFFSET                              (0x0C)/* mjpeg_uv_frame_addr */
+#define MJPEG_YUV_MEM_OFFSET                                    (0x10)/* mjpeg_yuv_mem */
+#define MJPEG_JPEG_FRAME_ADDR_OFFSET                            (0x14)/* jpeg_frame_addr */
+#define MJPEG_JPEG_STORE_MEMORY_OFFSET                          (0x18)/* jpeg_store_memory */
+#define MJPEG_CONTROL_3_OFFSET                                  (0x1C)/* mjpeg_control_3 */
+#define MJPEG_FRAME_FIFO_POP_OFFSET                             (0x20)/* mjpeg_frame_fifo_pop */
+#define MJPEG_FRAME_SIZE_OFFSET                                 (0x24)/* mjpeg_frame_size */
+#define MJPEG_HEADER_BYTE_OFFSET                                (0x28)/* mjpeg_header_byte */
+#define MJPEG_SWAP_MODE_OFFSET                                  (0x30)/* mjpeg_swap_mode */
+#define MJPEG_SWAP_BIT_CNT_OFFSET                               (0x34)/* mjpeg_swap_bit_cnt */
+#define MJPEG_YUV_MEM_SW_OFFSET                                 (0x38)/* mjpeg_yuv_mem_sw */
+#define MJPEG_Y_FRAME_READ_STATUS_1_OFFSET                      (0x40)/* mjpeg_Y_frame_read_status_1 */
+#define MJPEG_Y_FRAME_READ_STATUS_2_OFFSET                      (0x44)/* mjpeg_Y_frame_read_status_2 */
+#define MJPEG_Y_FRAME_WRITE_STATUS_OFFSET                       (0x48)/* mjpeg_Y_frame_write_status */
+#define MJPEG_UV_FRAME_READ_STATUS_1_OFFSET                     (0x4C)/* mjpeg_UV_frame_read_status_1 */
+#define MJPEG_UV_FRAME_READ_STATUS_2_OFFSET                     (0x50)/* mjpeg_UV_frame_read_status_2 */
+#define MJPEG_UV_FRAME_WRITE_STATUS_OFFSET                      (0x54)/* mjpeg_UV_frame_write_status */
+#define MJPEG_FRAME_W_HBLK_STATUS_OFFSET                        (0x58)/* mjpeg_frame_w_hblk_status */
+#define MJPEG_START_ADDR0_OFFSET                                (0x80)/* mjpeg_start_addr0 */
+#define MJPEG_BIT_CNT0_OFFSET                                   (0x84)/* mjpeg_bit_cnt0 */
+#define MJPEG_START_ADDR1_OFFSET                                (0x88)/* mjpeg_start_addr1 */
+#define MJPEG_BIT_CNT1_OFFSET                                   (0x8C)/* mjpeg_bit_cnt1 */
+#define MJPEG_START_ADDR2_OFFSET                                (0x90)/* mjpeg_start_addr2 */
+#define MJPEG_BIT_CNT2_OFFSET                                   (0x94)/* mjpeg_bit_cnt2 */
+#define MJPEG_START_ADDR3_OFFSET                                (0x98)/* mjpeg_start_addr3 */
+#define MJPEG_BIT_CNT3_OFFSET                                   (0x9C)/* mjpeg_bit_cnt3 */
+#define MJPEG_Q_ENC_OFFSET                                      (0x100)/* mjpeg_q_enc */
+#define MJPEG_FRAME_ID_10_OFFSET                                (0x110)/* mjpeg_frame_id_10 */
+#define MJPEG_FRAME_ID_32_OFFSET                                (0x114)/* mjpeg_frame_id_32 */
+#define MJPEG_DEBUG_OFFSET                                      (0x1F0)/* mjpeg_debug */
+#define MJPEG_DUMMY_REG_OFFSET                                  (0x1FC)/* mjpeg_dummy_reg */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : mjpeg_control_1 */
+#define MJPEG_REG_MJPEG_ENABLE                                  (1<<0U)
+#define MJPEG_REG_MJPEG_BIT_ORDER                               (1<<1U)
+#define MJPEG_REG_ORDER_U_EVEN                                  (1<<2U)
+#define MJPEG_REG_HW_MODE_SWEN                                  (1<<3U)
+#define MJPEG_REG_LAST_HF_WBLK_DMY                              (1<<4U)
+#define MJPEG_REG_LAST_HF_HBLK_DMY                              (1<<5U)
+#define MJPEG_REG_REFLECT_DMY                                   (1<<6U)
+#define MJPEG_REG_READ_FWRAP                                    (1<<7U)
+#define MJPEG_REG_W_XLEN_SHIFT                                  (8U)
+#define MJPEG_REG_W_XLEN_MASK                                   (0x7<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PWM_REG_H__
+#define __PWM_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+#if defined(BL702L)
+#define PWM_INT_CONFIG_OFFSET (-0x20) /* pwm_int_config */
+#else
+#define PWM_INT_CONFIG_OFFSET (0x0) /* pwm_int_config */
+#endif
+#define PWM0_CLKDIV_OFFSET    (0x20) /* pwm0_clkdiv */
+#define PWM0_THRE1_OFFSET     (0x24) /* pwm0_thre1 */
+#define PWM0_THRE2_OFFSET     (0x28) /* pwm0_thre2 */
+#define PWM0_PERIOD_OFFSET    (0x2C) /* pwm0_period */
+#define PWM0_CONFIG_OFFSET    (0x30) /* pwm0_config */
+#define PWM0_INTERRUPT_OFFSET (0x34) /* pwm0_interrupt */
+#define PWM1_CLKDIV_OFFSET    (0x40) /* pwm1_clkdiv */
+#define PWM1_THRE1_OFFSET     (0x44) /* pwm1_thre1 */
+#define PWM1_THRE2_OFFSET     (0x48) /* pwm1_thre2 */
+#define PWM1_PERIOD_OFFSET    (0x4C) /* pwm1_period */
+#define PWM1_CONFIG_OFFSET    (0x50) /* pwm1_config */
+#define PWM1_INTERRUPT_OFFSET (0x54) /* pwm1_interrupt */
+#define PWM2_CLKDIV_OFFSET    (0x60) /* pwm2_clkdiv */
+#define PWM2_THRE1_OFFSET     (0x64) /* pwm2_thre1 */
+#define PWM2_THRE2_OFFSET     (0x68) /* pwm2_thre2 */
+#define PWM2_PERIOD_OFFSET    (0x6C) /* pwm2_period */
+#define PWM2_CONFIG_OFFSET    (0x70) /* pwm2_config */
+#define PWM2_INTERRUPT_OFFSET (0x74) /* pwm2_interrupt */
+#define PWM3_CLKDIV_OFFSET    (0x80) /* pwm3_clkdiv */
+#define PWM3_THRE1_OFFSET     (0x84) /* pwm3_thre1 */
+#define PWM3_THRE2_OFFSET     (0x88) /* pwm3_thre2 */
+#define PWM3_PERIOD_OFFSET    (0x8C) /* pwm3_period */
+#define PWM3_CONFIG_OFFSET    (0x90) /* pwm3_config */
+#define PWM3_INTERRUPT_OFFSET (0x94) /* pwm3_interrupt */
+#define PWM4_CLKDIV_OFFSET    (0xA0) /* pwm4_clkdiv */
+#define PWM4_THRE1_OFFSET     (0xA4) /* pwm4_thre1 */
+#define PWM4_THRE2_OFFSET     (0xA8) /* pwm4_thre2 */
+#define PWM4_PERIOD_OFFSET    (0xAC) /* pwm4_period */
+#define PWM4_CONFIG_OFFSET    (0xB0) /* pwm4_config */
+#define PWM4_INTERRUPT_OFFSET (0xB4) /* pwm4_interrupt */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : pwm_int_config */
+#define PWM_INTERRUPT_STS_SHIFT (0U)
+#define PWM_INTERRUPT_STS_MASK  (0x3f << PWM_INTERRUPT_STS_SHIFT)
+#define PWM_INT_CLEAR_SHIFT     (8U)
+#define PWM_INT_CLEAR_MASK      (0x3f << PWM_INT_CLEAR_SHIFT)
+
+/* 0x20 : pwm0_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK  (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x24 : pwm0_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK  (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x28 : pwm0_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK  (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x2C : pwm0_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK  (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x30 : pwm0_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK  (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV           (1 << 2U)
+#define PWM_STOP_MODE         (1 << 3U)
+#define PWM_SW_FORCE_VAL      (1 << 4U)
+#define PWM_SW_MODE           (1 << 5U)
+#define PWM_STOP_EN           (1 << 6U)
+#define PWM_STS_TOP           (1 << 7U)
+
+/* 0x34 : pwm0_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK  (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE           (1 << 16U)
+
+/* 0x40 : pwm1_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK  (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x44 : pwm1_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK  (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x48 : pwm1_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK  (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x4C : pwm1_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK  (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x50 : pwm1_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK  (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV           (1 << 2U)
+#define PWM_STOP_MODE         (1 << 3U)
+#define PWM_SW_FORCE_VAL      (1 << 4U)
+#define PWM_SW_MODE           (1 << 5U)
+#define PWM_STOP_EN           (1 << 6U)
+#define PWM_STS_TOP           (1 << 7U)
+
+/* 0x54 : pwm1_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK  (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE           (1 << 16U)
+
+/* 0x60 : pwm2_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK  (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x64 : pwm2_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK  (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x68 : pwm2_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK  (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x6C : pwm2_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK  (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x70 : pwm2_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK  (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV           (1 << 2U)
+#define PWM_STOP_MODE         (1 << 3U)
+#define PWM_SW_FORCE_VAL      (1 << 4U)
+#define PWM_SW_MODE           (1 << 5U)
+#define PWM_STOP_EN           (1 << 6U)
+#define PWM_STS_TOP           (1 << 7U)
+
+/* 0x74 : pwm2_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK  (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE           (1 << 16U)
+
+/* 0x80 : pwm3_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK  (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0x84 : pwm3_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK  (0xffff << PWM_THRE1_SHIFT)
+
+/* 0x88 : pwm3_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK  (0xffff << PWM_THRE2_SHIFT)
+
+/* 0x8C : pwm3_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK  (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0x90 : pwm3_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK  (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV           (1 << 2U)
+#define PWM_STOP_MODE         (1 << 3U)
+#define PWM_SW_FORCE_VAL      (1 << 4U)
+#define PWM_SW_MODE           (1 << 5U)
+#define PWM_STOP_EN           (1 << 6U)
+#define PWM_STS_TOP           (1 << 7U)
+
+/* 0x94 : pwm3_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK  (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE           (1 << 16U)
+
+/* 0xA0 : pwm4_clkdiv */
+#define PWM_CLK_DIV_SHIFT (0U)
+#define PWM_CLK_DIV_MASK  (0xffff << PWM_CLK_DIV_SHIFT)
+
+/* 0xA4 : pwm4_thre1 */
+#define PWM_THRE1_SHIFT (0U)
+#define PWM_THRE1_MASK  (0xffff << PWM_THRE1_SHIFT)
+
+/* 0xA8 : pwm4_thre2 */
+#define PWM_THRE2_SHIFT (0U)
+#define PWM_THRE2_MASK  (0xffff << PWM_THRE2_SHIFT)
+
+/* 0xAC : pwm4_period */
+#define PWM_PERIOD_SHIFT (0U)
+#define PWM_PERIOD_MASK  (0xffff << PWM_PERIOD_SHIFT)
+
+/* 0xB0 : pwm4_config */
+#define PWM_REG_CLK_SEL_SHIFT (0U)
+#define PWM_REG_CLK_SEL_MASK  (0x3 << PWM_REG_CLK_SEL_SHIFT)
+#define PWM_OUT_INV           (1 << 2U)
+#define PWM_STOP_MODE         (1 << 3U)
+#define PWM_SW_FORCE_VAL      (1 << 4U)
+#define PWM_SW_MODE           (1 << 5U)
+#define PWM_STOP_EN           (1 << 6U)
+#define PWM_STS_TOP           (1 << 7U)
+
+/* 0xB4 : pwm4_interrupt */
+#define PWM_INT_PERIOD_CNT_SHIFT (0U)
+#define PWM_INT_PERIOD_CNT_MASK  (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+#define PWM_INT_ENABLE           (1 << 16U)
+
+#endif /* __PWM_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/pwm_v2_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/pwm_v2_reg.h
new file mode 100755
index 0000000000..b69b385ef1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/pwm_v2_reg.h
@@ -0,0 +1,208 @@
+/**
+  ******************************************************************************
+  * @file    pwm_reg.h
+  * @version V1.0
+  * @date    2022-08-15
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_PWM_V2_H__
+#define __HARDWARE_PWM_V2_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define PWM_INT_CONFIG_OFFSET    (0x0)  /* pwm_int_config */
+#define PWM_MC0_CONFIG0_OFFSET   (0x40) /* pwm_mc0_config0 */
+#define PWM_MC0_CONFIG1_OFFSET   (0x44) /* pwm_mc0_config1 */
+#define PWM_MC0_PERIOD_OFFSET    (0x48) /* pwm_mc0_period */
+#define PWM_MC0_DEAD_TIME_OFFSET (0x4C) /* pwm_mc0_dead_time */
+#define PWM_MC0_CH0_THRE_OFFSET  (0x50) /* pwm_mc0_ch0_thre */
+#define PWM_MC0_CH1_THRE_OFFSET  (0x54) /* pwm_mc0_ch1_thre */
+#define PWM_MC0_CH2_THRE_OFFSET  (0x58) /* pwm_mc0_ch2_thre */
+#define PWM_MC0_CH3_THRE_OFFSET  (0x5C) /* pwm_mc0_ch3_thre */
+#define PWM_MC0_INT_STS_OFFSET   (0x60) /* pwm_mc0_int_sts */
+#define PWM_MC0_INT_MASK_OFFSET  (0x64) /* pwm_mc0_int_mask */
+#define PWM_MC0_INT_CLEAR_OFFSET (0x68) /* pwm_mc0_int_clear */
+#define PWM_MC0_INT_EN_OFFSET    (0x6C) /* pwm_mc0_int_en */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : pwm_int_config */
+#define PWM0_INT_STS (1 << 0U)
+#define PWM1_INT_STS (1 << 1U)
+#define PWM0_INT_CLR (1 << 8U)
+#define PWM1_INT_CLR (1 << 9U)
+
+/* 0x40 : pwm_mc0_config0 */
+#define PWM_CLK_DIV_SHIFT     (0U)
+#define PWM_CLK_DIV_MASK      (0xffff << PWM_CLK_DIV_SHIFT)
+#define PWM_STOP_ON_REPT      (1 << 19U)
+#define PWM_ADC_TRG_SRC_SHIFT (20U)
+#define PWM_ADC_TRG_SRC_MASK  (0xf << PWM_ADC_TRG_SRC_SHIFT)
+#define PWM_SW_BREAK_EN       (1 << 24U)
+#define PWM_EXT_BREAK_EN      (1 << 25U)
+#define PWM_EXT_BREAK_PL      (1 << 26U)
+#define PWM_STOP_EN           (1 << 27U)
+#define PWM_STOP_MODE         (1 << 28U)
+#define PWM_STS_STOP          (1 << 29U)
+#define PWM_REG_CLK_SEL_SHIFT (30U)
+#define PWM_REG_CLK_SEL_MASK  (0x3 << PWM_REG_CLK_SEL_SHIFT)
+
+/* 0x44 : pwm_mc0_config1 */
+#define PWM_CH0_PEN (1 << 0U)
+#define PWM_CH0_PSI (1 << 1U)
+#define PWM_CH0_NEN (1 << 2U)
+#define PWM_CH0_NSI (1 << 3U)
+#define PWM_CH1_PEN (1 << 4U)
+#define PWM_CH1_PSI (1 << 5U)
+#define PWM_CH1_NEN (1 << 6U)
+#define PWM_CH1_NSI (1 << 7U)
+#define PWM_CH2_PEN (1 << 8U)
+#define PWM_CH2_PSI (1 << 9U)
+#define PWM_CH2_NEN (1 << 10U)
+#define PWM_CH2_NSI (1 << 11U)
+#define PWM_CH3_PEN (1 << 12U)
+#define PWM_CH3_PSI (1 << 13U)
+#define PWM_CH3_NEN (1 << 14U)
+#define PWM_CH3_NSI (1 << 15U)
+#define PWM_CH0_PPL (1 << 16U)
+#define PWM_CH0_NPL (1 << 17U)
+#define PWM_CH1_PPL (1 << 18U)
+#define PWM_CH1_NPL (1 << 19U)
+#define PWM_CH2_PPL (1 << 20U)
+#define PWM_CH2_NPL (1 << 21U)
+#define PWM_CH3_PPL (1 << 22U)
+#define PWM_CH3_NPL (1 << 23U)
+#define PWM_CH0_PBS (1 << 24U)
+#define PWM_CH0_NBS (1 << 25U)
+#define PWM_CH1_PBS (1 << 26U)
+#define PWM_CH1_NBS (1 << 27U)
+#define PWM_CH2_PBS (1 << 28U)
+#define PWM_CH2_NBS (1 << 29U)
+#define PWM_CH3_PBS (1 << 30U)
+#define PWM_CH3_NBS (1 << 31U)
+
+/* 0x48 : pwm_mc0_period */
+#define PWM_PERIOD_SHIFT         (0U)
+#define PWM_PERIOD_MASK          (0xffff << PWM_PERIOD_SHIFT)
+#define PWM_INT_PERIOD_CNT_SHIFT (16U)
+#define PWM_INT_PERIOD_CNT_MASK  (0xffff << PWM_INT_PERIOD_CNT_SHIFT)
+
+/* 0x4C : pwm_mc0_dead_time */
+#define PWM_CH0_DTG_SHIFT (0U)
+#define PWM_CH0_DTG_MASK  (0xff << PWM_CH0_DTG_SHIFT)
+#define PWM_CH1_DTG_SHIFT (8U)
+#define PWM_CH1_DTG_MASK  (0xff << PWM_CH1_DTG_SHIFT)
+#define PWM_CH2_DTG_SHIFT (16U)
+#define PWM_CH2_DTG_MASK  (0xff << PWM_CH2_DTG_SHIFT)
+#define PWM_CH3_DTG_SHIFT (24U)
+#define PWM_CH3_DTG_MASK  (0xff << PWM_CH3_DTG_SHIFT)
+
+/* 0x50 : pwm_mc0_ch0_thre */
+#define PWM_CH0_THREL_SHIFT (0U)
+#define PWM_CH0_THREL_MASK  (0xffff << PWM_CH0_THREL_SHIFT)
+#define PWM_CH0_THREH_SHIFT (16U)
+#define PWM_CH0_THREH_MASK  (0xffff << PWM_CH0_THREH_SHIFT)
+
+/* 0x54 : pwm_mc0_ch1_thre */
+#define PWM_CH1_THREL_SHIFT (0U)
+#define PWM_CH1_THREL_MASK  (0xffff << PWM_CH1_THREL_SHIFT)
+#define PWM_CH1_THREH_SHIFT (16U)
+#define PWM_CH1_THREH_MASK  (0xffff << PWM_CH1_THREH_SHIFT)
+
+/* 0x58 : pwm_mc0_ch2_thre */
+#define PWM_CH2_THREL_SHIFT (0U)
+#define PWM_CH2_THREL_MASK  (0xffff << PWM_CH2_THREL_SHIFT)
+#define PWM_CH2_THREH_SHIFT (16U)
+#define PWM_CH2_THREH_MASK  (0xffff << PWM_CH2_THREH_SHIFT)
+
+/* 0x5C : pwm_mc0_ch3_thre */
+#define PWM_CH3_THREL_SHIFT (0U)
+#define PWM_CH3_THREL_MASK  (0xffff << PWM_CH3_THREL_SHIFT)
+#define PWM_CH3_THREH_SHIFT (16U)
+#define PWM_CH3_THREH_MASK  (0xffff << PWM_CH3_THREH_SHIFT)
+
+/* 0x60 : pwm_mc0_int_sts */
+#define PWM_CH0L_INT (1 << 0U)
+#define PWM_CH0H_INT (1 << 1U)
+#define PWM_CH1L_INT (1 << 2U)
+#define PWM_CH1H_INT (1 << 3U)
+#define PWM_CH2L_INT (1 << 4U)
+#define PWM_CH2H_INT (1 << 5U)
+#define PWM_CH3L_INT (1 << 6U)
+#define PWM_CH3H_INT (1 << 7U)
+#define PWM_PRDE_INT (1 << 8U)
+#define PWM_BRK_INT  (1 << 9U)
+#define PWM_REPT_INT (1 << 10U)
+
+/* 0x64 : pwm_mc0_int_mask */
+#define PWM_CR_PWM_CH0L_MASK (1 << 0U)
+#define PWM_CR_PWM_CH0H_MASK (1 << 1U)
+#define PWM_CR_PWM_CH1L_MASK (1 << 2U)
+#define PWM_CR_PWM_CH1H_MASK (1 << 3U)
+#define PWM_CR_PWM_CH2L_MASK (1 << 4U)
+#define PWM_CR_PWM_CH2H_MASK (1 << 5U)
+#define PWM_CR_PWM_CH3L_MASK (1 << 6U)
+#define PWM_CR_PWM_CH3H_MASK (1 << 7U)
+#define PWM_CR_PWM_PRDE_MASK (1 << 8U)
+#define PWM_CR_PWM_BRK_MASK  (1 << 9U)
+#define PWM_CR_PWM_REPT_MASK (1 << 10U)
+
+/* 0x68 : pwm_mc0_int_clear */
+#define PWM_CR_PWM_CH0L_CLR (1 << 0U)
+#define PWM_CR_PWM_CH0H_CLR (1 << 1U)
+#define PWM_CR_PWM_CH1L_CLR (1 << 2U)
+#define PWM_CR_PWM_CH1H_CLR (1 << 3U)
+#define PWM_CR_PWM_CH2L_CLR (1 << 4U)
+#define PWM_CR_PWM_CH2H_CLR (1 << 5U)
+#define PWM_CR_PWM_CH3L_CLR (1 << 6U)
+#define PWM_CR_PWM_CH3H_CLR (1 << 7U)
+#define PWM_CR_PWM_PRDE_CLR (1 << 8U)
+#define PWM_CR_PWM_BRK_CLR  (1 << 9U)
+#define PWM_CR_PWM_REPT_CLR (1 << 10U)
+
+/* 0x6C : pwm_mc0_int_en */
+#define PWM_CR_PWM_CH0L_EN (1 << 0U)
+#define PWM_CR_PWM_CH0H_EN (1 << 1U)
+#define PWM_CR_PWM_CH1L_EN (1 << 2U)
+#define PWM_CR_PWM_CH1H_EN (1 << 3U)
+#define PWM_CR_PWM_CH2L_EN (1 << 4U)
+#define PWM_CR_PWM_CH2H_EN (1 << 5U)
+#define PWM_CR_PWM_CH3L_EN (1 << 6U)
+#define PWM_CR_PWM_CH3H_EN (1 << 7U)
+#define PWM_CR_PWM_PRDE_EN (1 << 8U)
+#define PWM_CR_PWM_BRK_EN  (1 << 9U)
+#define PWM_CR_PWM_REPT_EN (1 << 10U)
+
+#endif /* __HARDWARE_PWM_V2_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h
new file mode 100755
index 0000000000..dee3bfee8e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/rtc_reg.h
@@ -0,0 +1,92 @@
+/**
+  ******************************************************************************
+  * @file    rtc_reg.h
+  * @version V1.0
+  * @date    2022-08-05
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_RTC_H__
+#define __HARDWARE_RTC_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define HBN_CTL_OFFSET        (0x0)  /* HBN_CTL */
+#define HBN_TIME_L_OFFSET     (0x4)  /* HBN_TIME_L */
+#define HBN_TIME_H_OFFSET     (0x8)  /* HBN_TIME_H */
+#define HBN_RTC_TIME_L_OFFSET (0xC)  /* RTC_TIME_L */
+#define HBN_RTC_TIME_H_OFFSET (0x10) /* RTC_TIME_H */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : HBN_CTL */
+#define HBN_RTC_CTL_SHIFT            (0U)
+#define HBN_RTC_CTL_MASK             (0x7f << HBN_RTC_CTL_SHIFT)
+#define HBN_MODE                     (1 << 7U)
+#define HBN_TRAP_MODE                (1 << 8U)
+#define HBN_PWRDN_HBN_CORE           (1 << 9U)
+#define HBN_PWRDN_HBN_RTC            (1 << 11U)
+#define HBN_SW_RST                   (1 << 12U)
+#define HBN_DIS_PWR_OFF_LDO11        (1 << 13U)
+#define HBN_DIS_PWR_OFF_LDO11_RT     (1 << 14U)
+#define HBN_LDO11_RT_VOUT_SEL_SHIFT  (15U)
+#define HBN_LDO11_RT_VOUT_SEL_MASK   (0xf << HBN_LDO11_RT_VOUT_SEL_SHIFT)
+#define HBN_LDO11_AON_VOUT_SEL_SHIFT (19U)
+#define HBN_LDO11_AON_VOUT_SEL_MASK  (0xf << HBN_LDO11_AON_VOUT_SEL_SHIFT)
+#define HBN_PU_DCDC18_AON            (1 << 23U)
+#define HBN_RTC_DLY_OPTION           (1 << 24U)
+#define HBN_PWR_ON_OPTION            (1 << 25U)
+#define HBN_SRAM_SLP_OPTION          (1 << 26U)
+#define HBN_SRAM_SLP                 (1 << 27U)
+#define HBN_STATE_SHIFT              (28U)
+#define HBN_STATE_MASK               (0xf << HBN_STATE_SHIFT)
+
+/* 0x4 : HBN_TIME_L */
+#define HBN_TIME_L_SHIFT (0U)
+#define HBN_TIME_L_MASK  (0xffffffff << HBN_TIME_L_SHIFT)
+
+/* 0x8 : HBN_TIME_H */
+#define HBN_TIME_H_SHIFT (0U)
+#define HBN_TIME_H_MASK  (0xff << HBN_TIME_H_SHIFT)
+
+/* 0xC : RTC_TIME_L */
+#define HBN_RTC_TIME_LATCH_L_SHIFT (0U)
+#define HBN_RTC_TIME_LATCH_L_MASK  (0xffffffff << HBN_RTC_TIME_LATCH_L_SHIFT)
+
+/* 0x10 : RTC_TIME_H */
+#define HBN_RTC_TIME_LATCH_H_SHIFT (0U)
+#define HBN_RTC_TIME_LATCH_H_MASK  (0xff << HBN_RTC_TIME_LATCH_H_SHIFT)
+#define HBN_RTC_TIME_LATCH         (1 << 31U)
+
+#endif /* __HARDWARE_RTC_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sdio2_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sdio2_reg.h
new file mode 100755
index 0000000000..9862a41ef3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sdio2_reg.h
@@ -0,0 +1,139 @@
+/**
+  ******************************************************************************
+  * @file    sdio2.h
+  * @version V1.0
+  * @date    2022-08-03
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_SDIO2_H__
+#define __HARDWARE_SDIO2_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SDIO2_IO_ENABLE_OFFSET          (0x0002) /* SDIO I/O Enable */
+#define SDIO2_FN1_BLK_SIZE_0_OFFSET     (0x0028) /* SDIO block size infor */
+#define SDIO2_FN1_BLK_SIZE_1_OFFSET     (0x0029) /* SDIO block size infor */
+#define SDIO2_DEV_SLEEP_OFFSET          (0x0092) /* SDIO Device Sleep */
+#define SDIO2_CCR_FUNC_OFFSET           (0x0100) /* Address offset of CCR between two functions */
+#define SDIO2_HOST_TO_CARD_EVENT_OFFSET (0x0100)
+#define SDIO2_HOST_INT_CAUSE_OFFSET     (0x0101)
+#define SDIO2_HOST_INT_MASK_OFFSET      (0x0102)
+#define SDIO2_HOST_INT_STATUS_OFFSET    (0x0103)
+#define SDIO2_RD_BIT_MAP_OFFSET         (0x0104)
+#define SDIO2_WR_BIT_MAP_OFFSET         (0x0106)
+#define SDIO2_RD_LEN_OFFSET             (0x0108)
+#define SDIO2_HOST_TRANS_STATUS_OFFSET  (0x0128)
+#define SDIO2_CARD_TO_HOST_EVENT_OFFSET (0x0130)
+#define SDIO2_CARD_INT_MASK_OFFSET      (0x0134)
+#define SDIO2_CARD_INT_STATUS_OFFSET    (0x0138)
+#define SDIO2_CARD_INT_MODE_OFFSET      (0x013C)
+#define SDIO2_SQ_READ_BASE_OFFSET       (0x0140)
+#define SDIO2_SQ_WRITE_BASE_OFFSET      (0x0144)
+#define SDIO2_READ_INDEX_OFFSET         (0x0148)
+#define SDIO2_WRITE_INDEX_OFFSET        (0x0149)
+#define SDIO2_DNLD_QUEUE_WRPTR_OFFSET   (0x014A)
+#define SDIO2_UPLD_QUEUE_WRPTR_OFFSET   (0x014B)
+#define SDIO2_DNLD_QUEUE_OFFSET         (0x014C)
+#define SDIO2_UPLD_QUEUE_OFFSET         (0x0154)
+#define SDIO2_CHIP_VERSION_OFFSET       (0x015C)
+#define SDIO2_IP_VERSION0_OFFSET        (0x015E)
+#define SDIO2_IP_VERSION1_OFFSET        (0x015F)
+#define SDIO2_SCRATCH2_OFFSET           (0x0164)
+#define SDIO2_SCRATCH1_OFFSET           (0x0166)
+#define SDIO2_OCR0_OFFSET               (0x0168)
+#define SDIO2_OCR1_OFFSET               (0x0169)
+#define SDIO2_OCR2_OFFSET               (0x016A)
+#define SDIO2_CONFIG_OFFSET             (0x016B)
+#define SDIO2_CONFIG2_OFFSET            (0x016C)
+#define SDIO2_DEBUG_OFFSET              (0x0170)
+#define SDIO2_DMA_ADDR_OFFSET           (0x0174)
+#define SDIO2_IO_PORT_OFFSET            (0x0178)
+
+
+// Bit Def. Scratch register 0
+#define SDIO2_SCRATCH_OFFSET           (0x0160)
+
+// Bit Def. Block size 1 mask (Offset 0x29)
+#define SDIO2_FN1_BLK_SIZE_1_MASK 0x01
+
+// Bit Def. Host To Card Interrupt Event (Offset 0x100/200)
+#define SDIO2_HCR_CONFIG_HostPwrUp (1 << 1)
+
+// Bit Def. Host Transfer Status (Offset 0x128/228)
+#define SDIO2_CCR_HOST_INT_DnLdReStart (1 << 0)
+#define SDIO2_CCR_HOST_INT_UpLdReStart (1 << 1)
+#define SDIO2_CCR_HOST_INT_DnLdCRC_err (1 << 2)
+
+// Bit Def. Card To Host Interrupt Event (Offset 0x130/230)
+#define SDIO2_CCR_CS_DnLdRdy    (1 << 0)
+#define SDIO2_CCR_CS_UpLdRdy    (1 << 1)
+#define SDIO2_CCR_CS_ReadCISRdy (1 << 2)
+#define SDIO2_CCR_CS_IORdy      (1 << 3)
+
+// Bit Def. Card Interrupt Mask (Offset 0x134/234)
+#define SDIO2_CCR_CIM_DnLdOvr (1 << 0)
+#define SDIO2_CCR_CIM_UpLdOvr (1 << 1)
+#define SDIO2_CCR_CIM_Abort   (1 << 2)
+#define SDIO2_CCR_CIM_PwrDn   (1 << 3)
+#define SDIO2_CCR_CIM_PwrUp   (1 << 4)
+
+#define SDIO2_CCR_CIM_MASK 0x0007
+
+// Bit Def. Card Interrupt Status (Offset 0x138/238)
+#define SDIO2_CCR_CIC_DnLdOvr (1 << 0)
+#define SDIO2_CCR_CIC_UpLdOvr (1 << 1)
+#define SDIO2_CCR_CIC_Abort   (1 << 2)
+#define SDIO2_CCR_CIC_PwrDn   (1 << 3)
+#define SDIO2_CCR_CIC_PwrUp   (1 << 4)
+
+#define SDIO2_CCR_CIC_MASK 0x001F
+
+// Bit Def. Card Interrupt RSR (Offset 0x13C/23C)
+#define SDIO2_CCR_CIO_DnLdOvr (1 << 0)
+#define SDIO2_CCR_CIO_UpLdOvr (1 << 1)
+#define SDIO2_CCR_CIO_Abort   (1 << 2)
+#define SDIO2_CCR_CIO_PwrDn   (1 << 3)
+#define SDIO2_CCR_CIO_PwrUp   (1 << 4)
+#define SDIO2_CCR_CIO_MASK    0x001F
+
+//Config2 register mask
+#define SDIO2_CONFIG2_MSK 0x00000C00
+
+//CardIntMode register mask
+
+#define SDIO2_CARD_INT_MODE_MSK 0x00000003
+#define SDIO2_HOST_INT_MSK      0x00000002
+
+#endif /* __HARDWARE_SDIO2_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sec_eng_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sec_eng_reg.h
new file mode 100755
index 0000000000..54e99c4a46
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sec_eng_reg.h
@@ -0,0 +1,558 @@
+/**
+  ******************************************************************************
+  * @file    sec_eng_reg.h
+  * @version V1.0
+  * @date    2022-08-15
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_SEC_ENG_H__
+#define __HARDWARE_SEC_ENG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SEC_ENG_SE_SHA_0_CTRL_OFFSET        (0x0)   /* se_sha_0_ctrl */
+#define SEC_ENG_SE_SHA_0_MSA_OFFSET         (0x4)   /* se_sha_0_msa */
+#define SEC_ENG_SE_SHA_0_STATUS_OFFSET      (0x8)   /* se_sha_0_status */
+#define SEC_ENG_SE_SHA_0_ENDIAN_OFFSET      (0xC)   /* se_sha_0_endian */
+#define SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET    (0x10)  /* se_sha_0_hash_l_0 */
+#define SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET    (0x14)  /* se_sha_0_hash_l_1 */
+#define SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET    (0x18)  /* se_sha_0_hash_l_2 */
+#define SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET    (0x1C)  /* se_sha_0_hash_l_3 */
+#define SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET    (0x20)  /* se_sha_0_hash_l_4 */
+#define SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET    (0x24)  /* se_sha_0_hash_l_5 */
+#define SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET    (0x28)  /* se_sha_0_hash_l_6 */
+#define SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET    (0x2C)  /* se_sha_0_hash_l_7 */
+#define SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET    (0x30)  /* se_sha_0_hash_h_0 */
+#define SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET    (0x34)  /* se_sha_0_hash_h_1 */
+#define SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET    (0x38)  /* se_sha_0_hash_h_2 */
+#define SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET    (0x3C)  /* se_sha_0_hash_h_3 */
+#define SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET    (0x40)  /* se_sha_0_hash_h_4 */
+#define SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET    (0x44)  /* se_sha_0_hash_h_5 */
+#define SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET    (0x48)  /* se_sha_0_hash_h_6 */
+#define SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET    (0x4C)  /* se_sha_0_hash_h_7 */
+#define SEC_ENG_SE_SHA_0_LINK_OFFSET        (0x50)  /* se_sha_0_link */
+#define SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET   (0xFC)  /* se_sha_0_ctrl_prot */
+#define SEC_ENG_SE_AES_0_CTRL_OFFSET        (0x100) /* se_aes_0_ctrl */
+#define SEC_ENG_SE_AES_0_MSA_OFFSET         (0x104) /* se_aes_0_msa */
+#define SEC_ENG_SE_AES_0_MDA_OFFSET         (0x108) /* se_aes_0_mda */
+#define SEC_ENG_SE_AES_0_STATUS_OFFSET      (0x10C) /* se_aes_0_status */
+#define SEC_ENG_SE_AES_0_IV_0_OFFSET        (0x110) /* se_aes_0_iv_0 */
+#define SEC_ENG_SE_AES_0_IV_1_OFFSET        (0x114) /* se_aes_0_iv_1 */
+#define SEC_ENG_SE_AES_0_IV_2_OFFSET        (0x118) /* se_aes_0_iv_2 */
+#define SEC_ENG_SE_AES_0_IV_3_OFFSET        (0x11C) /* se_aes_0_iv_3 */
+#define SEC_ENG_SE_AES_0_KEY_0_OFFSET       (0x120) /* se_aes_0_key_0 */
+#define SEC_ENG_SE_AES_0_KEY_1_OFFSET       (0x124) /* se_aes_0_key_1 */
+#define SEC_ENG_SE_AES_0_KEY_2_OFFSET       (0x128) /* se_aes_0_key_2 */
+#define SEC_ENG_SE_AES_0_KEY_3_OFFSET       (0x12C) /* se_aes_0_key_3 */
+#define SEC_ENG_SE_AES_0_KEY_4_OFFSET       (0x130) /* se_aes_0_key_4 */
+#define SEC_ENG_SE_AES_0_KEY_5_OFFSET       (0x134) /* se_aes_0_key_5 */
+#define SEC_ENG_SE_AES_0_KEY_6_OFFSET       (0x138) /* se_aes_0_key_6 */
+#define SEC_ENG_SE_AES_0_KEY_7_OFFSET       (0x13C) /* se_aes_0_key_7 */
+#define SEC_ENG_SE_AES_0_KEY_SEL_OFFSET     (0x140) /* se_aes_0_key_sel */
+#define SEC_ENG_SE_AES_1_KEY_SEL_OFFSET     (0x144) /* se_aes_1_key_sel */
+#define SEC_ENG_SE_AES_0_ENDIAN_OFFSET      (0x148) /* se_aes_0_endian */
+#define SEC_ENG_SE_AES_0_SBOOT_OFFSET       (0x14C) /* se_aes_0_sboot */
+#define SEC_ENG_SE_AES_0_LINK_OFFSET        (0x150) /* se_aes_0_link */
+#define SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET   (0x1FC) /* se_aes_0_ctrl_prot */
+#define SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET     (0x200) /* se_trng_0_ctrl_0 */
+#define SEC_ENG_SE_TRNG_0_STATUS_OFFSET     (0x204) /* se_trng_0_status */
+#define SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET     (0x208) /* se_trng_0_dout_0 */
+#define SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET     (0x20C) /* se_trng_0_dout_1 */
+#define SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET     (0x210) /* se_trng_0_dout_2 */
+#define SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET     (0x214) /* se_trng_0_dout_3 */
+#define SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET     (0x218) /* se_trng_0_dout_4 */
+#define SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET     (0x21C) /* se_trng_0_dout_5 */
+#define SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET     (0x220) /* se_trng_0_dout_6 */
+#define SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET     (0x224) /* se_trng_0_dout_7 */
+#define SEC_ENG_SE_TRNG_0_TEST_OFFSET       (0x228) /* se_trng_0_test */
+#define SEC_ENG_SE_TRNG_0_CTRL_1_OFFSET     (0x22C) /* se_trng_0_ctrl_1 */
+#define SEC_ENG_SE_TRNG_0_CTRL_2_OFFSET     (0x230) /* se_trng_0_ctrl_2 */
+#define SEC_ENG_SE_TRNG_0_CTRL_3_OFFSET     (0x234) /* se_trng_0_ctrl_3 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_OFFSET (0x240) /* se_trng_0_test_out_0 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_OFFSET (0x244) /* se_trng_0_test_out_1 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_OFFSET (0x248) /* se_trng_0_test_out_2 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_OFFSET (0x24C) /* se_trng_0_test_out_3 */
+#define SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET  (0x2FC) /* se_trng_0_ctrl_prot */
+#define SEC_ENG_SE_PKA_0_CTRL_0_OFFSET      (0x300) /* se_pka_0_ctrl_0 */
+#define SEC_ENG_SE_PKA_0_SEED_OFFSET        (0x30C) /* se_pka_0_seed */
+#define SEC_ENG_SE_PKA_0_CTRL_1_OFFSET      (0x310) /* se_pka_0_ctrl_1 */
+#define SEC_ENG_SE_PKA_0_RW_OFFSET          (0x340) /* se_pka_0_rw */
+#define SEC_ENG_SE_PKA_0_RW_BURST_OFFSET    (0x360) /* se_pka_0_rw_burst */
+#define SEC_ENG_SE_PKA_0_CTRL_PROT_OFFSET   (0x3FC) /* se_pka_0_ctrl_prot */
+#define SEC_ENG_SE_CDET_0_CTRL_0_OFFSET     (0x400) /* se_cdet_0_ctrl_0 */
+#define SEC_ENG_SE_CDET_0_CTRL_1_OFFSET     (0x404) /* se_cdet_0_ctrl_1 */
+#define SEC_ENG_SE_CDET_0_CTRL_2_OFFSET     (0x408) /* se_cdet_0_ctrl_2 */
+#define SEC_ENG_SE_CDET_0_CTRL_3_OFFSET     (0x40C) /* se_cdet_0_ctrl_3 */
+#define SEC_ENG_SE_CDET_0_CTRL_PROT_OFFSET  (0x4FC) /* se_cdet_0_ctrl_prot */
+#define SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET     (0x500) /* se_gmac_0_ctrl_0 */
+#define SEC_ENG_SE_GMAC_0_LCA_OFFSET        (0x504) /* se_gmac_0_lca */
+#define SEC_ENG_SE_GMAC_0_STATUS_OFFSET     (0x508) /* se_gmac_0_status */
+#define SEC_ENG_SE_GMAC_0_CTRL_PROT_OFFSET  (0x5FC) /* se_gmac_0_ctrl_prot */
+#define SEC_ENG_SE_CTRL_PROT_RD_OFFSET      (0xF00) /* se_ctrl_prot_rd */
+#define SEC_ENG_SE_CTRL_RESERVED_0_OFFSET   (0xF04) /* se_ctrl_reserved_0 */
+#define SEC_ENG_SE_CTRL_RESERVED_1_OFFSET   (0xF08) /* se_ctrl_reserved_1 */
+#define SEC_ENG_SE_CTRL_RESERVED_2_OFFSET   (0xF0C) /* se_ctrl_reserved_2 */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : se_sha_0_ctrl */
+#define SEC_ENG_SE_SHA_0_BUSY           (1 << 0U)
+#define SEC_ENG_SE_SHA_0_TRIG_1T        (1 << 1U)
+#define SEC_ENG_SE_SHA_0_MODE_SHIFT     (2U)
+#define SEC_ENG_SE_SHA_0_MODE_MASK      (0x7 << SEC_ENG_SE_SHA_0_MODE_SHIFT)
+#define SEC_ENG_SE_SHA_0_EN             (1 << 5U)
+#define SEC_ENG_SE_SHA_0_HASH_SEL       (1 << 6U)
+#define SEC_ENG_SE_SHA_0_INT            (1 << 8U)
+#define SEC_ENG_SE_SHA_0_INT_CLR_1T     (1 << 9U)
+#define SEC_ENG_SE_SHA_0_INT_SET_1T     (1 << 10U)
+#define SEC_ENG_SE_SHA_0_INT_MASK       (1 << 11U)
+#define SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT (12U)
+#define SEC_ENG_SE_SHA_0_MODE_EXT_MASK  (0x3 << SEC_ENG_SE_SHA_0_MODE_EXT_SHIFT)
+#define SEC_ENG_SE_SHA_0_LINK_MODE      (1 << 15U)
+#define SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT  (16U)
+#define SEC_ENG_SE_SHA_0_MSG_LEN_MASK   (0xffff << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT)
+
+/* 0x4 : se_sha_0_msa */
+#define SEC_ENG_SE_SHA_0_MSA_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_MSA_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_MSA_SHIFT)
+
+/* 0x8 : se_sha_0_status */
+#define SEC_ENG_SE_SHA_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_STATUS_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_STATUS_SHIFT)
+
+/* 0xC : se_sha_0_endian */
+#define SEC_ENG_SE_SHA_0_DOUT_ENDIAN (1 << 0U)
+
+/* 0x10 : se_sha_0_hash_l_0 */
+#define SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_0_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_0_SHIFT)
+
+/* 0x14 : se_sha_0_hash_l_1 */
+#define SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_1_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_1_SHIFT)
+
+/* 0x18 : se_sha_0_hash_l_2 */
+#define SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_2_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_2_SHIFT)
+
+/* 0x1C : se_sha_0_hash_l_3 */
+#define SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_3_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_3_SHIFT)
+
+/* 0x20 : se_sha_0_hash_l_4 */
+#define SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_4_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_4_SHIFT)
+
+/* 0x24 : se_sha_0_hash_l_5 */
+#define SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_5_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_5_SHIFT)
+
+/* 0x28 : se_sha_0_hash_l_6 */
+#define SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_6_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_6_SHIFT)
+
+/* 0x2C : se_sha_0_hash_l_7 */
+#define SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_L_7_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_L_7_SHIFT)
+
+/* 0x30 : se_sha_0_hash_h_0 */
+#define SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_0_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_0_SHIFT)
+
+/* 0x34 : se_sha_0_hash_h_1 */
+#define SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_1_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_1_SHIFT)
+
+/* 0x38 : se_sha_0_hash_h_2 */
+#define SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_2_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_2_SHIFT)
+
+/* 0x3C : se_sha_0_hash_h_3 */
+#define SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_3_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_3_SHIFT)
+
+/* 0x40 : se_sha_0_hash_h_4 */
+#define SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_4_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_4_SHIFT)
+
+/* 0x44 : se_sha_0_hash_h_5 */
+#define SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_5_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_5_SHIFT)
+
+/* 0x48 : se_sha_0_hash_h_6 */
+#define SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_6_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_6_SHIFT)
+
+/* 0x4C : se_sha_0_hash_h_7 */
+#define SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_HASH_H_7_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_HASH_H_7_SHIFT)
+
+/* 0x50 : se_sha_0_link */
+#define SEC_ENG_SE_SHA_0_LCA_SHIFT (0U)
+#define SEC_ENG_SE_SHA_0_LCA_MASK  (0xffffffff << SEC_ENG_SE_SHA_0_LCA_SHIFT)
+
+/* 0xFC : se_sha_0_ctrl_prot */
+#define SEC_ENG_SE_SHA_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_SHA_ID1_EN (1 << 2U)
+
+/* 0x100 : se_aes_0_ctrl */
+#define SEC_ENG_SE_AES_0_BUSY             (1 << 0U)
+#define SEC_ENG_SE_AES_0_TRIG_1T          (1 << 1U)
+#define SEC_ENG_SE_AES_0_EN               (1 << 2U)
+#define SEC_ENG_SE_AES_0_MODE_SHIFT       (3U)
+#define SEC_ENG_SE_AES_0_MODE_MASK        (0x3 << SEC_ENG_SE_AES_0_MODE_SHIFT)
+#define SEC_ENG_SE_AES_0_DEC_EN           (1 << 5U)
+#define SEC_ENG_SE_AES_0_DEC_KEY_SEL      (1 << 6U)
+#define SEC_ENG_SE_AES_0_HW_KEY_EN        (1 << 7U)
+#define SEC_ENG_SE_AES_0_INT              (1 << 8U)
+#define SEC_ENG_SE_AES_0_INT_CLR_1T       (1 << 9U)
+#define SEC_ENG_SE_AES_0_INT_SET_1T       (1 << 10U)
+#define SEC_ENG_SE_AES_0_INT_MASK         (1 << 11U)
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT (12U)
+#define SEC_ENG_SE_AES_0_BLOCK_MODE_MASK  (0x3 << SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT)
+#define SEC_ENG_SE_AES_0_IV_SEL           (1 << 14U)
+#define SEC_ENG_SE_AES_0_LINK_MODE        (1 << 15U)
+#define SEC_ENG_SE_AES_0_MSG_LEN_SHIFT    (16U)
+#define SEC_ENG_SE_AES_0_MSG_LEN_MASK     (0xffff << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT)
+
+/* 0x104 : se_aes_0_msa */
+#define SEC_ENG_SE_AES_0_MSA_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_MSA_MASK  (0xffffffff << SEC_ENG_SE_AES_0_MSA_SHIFT)
+
+/* 0x108 : se_aes_0_mda */
+#define SEC_ENG_SE_AES_0_MDA_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_MDA_MASK  (0xffffffff << SEC_ENG_SE_AES_0_MDA_SHIFT)
+
+/* 0x10C : se_aes_0_status */
+#define SEC_ENG_SE_AES_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_STATUS_MASK  (0xffffffff << SEC_ENG_SE_AES_0_STATUS_SHIFT)
+
+/* 0x110 : se_aes_0_iv_0 */
+#define SEC_ENG_SE_AES_0_IV_0_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_0_MASK  (0xffffffff << SEC_ENG_SE_AES_0_IV_0_SHIFT)
+
+/* 0x114 : se_aes_0_iv_1 */
+#define SEC_ENG_SE_AES_0_IV_1_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_1_MASK  (0xffffffff << SEC_ENG_SE_AES_0_IV_1_SHIFT)
+
+/* 0x118 : se_aes_0_iv_2 */
+#define SEC_ENG_SE_AES_0_IV_2_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_2_MASK  (0xffffffff << SEC_ENG_SE_AES_0_IV_2_SHIFT)
+
+/* 0x11C : se_aes_0_iv_3 */
+#define SEC_ENG_SE_AES_0_IV_3_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_IV_3_MASK  (0xffffffff << SEC_ENG_SE_AES_0_IV_3_SHIFT)
+
+/* 0x120 : se_aes_0_key_0 */
+#define SEC_ENG_SE_AES_0_KEY_0_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_0_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_0_SHIFT)
+
+/* 0x124 : se_aes_0_key_1 */
+#define SEC_ENG_SE_AES_0_KEY_1_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_1_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_1_SHIFT)
+
+/* 0x128 : se_aes_0_key_2 */
+#define SEC_ENG_SE_AES_0_KEY_2_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_2_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_2_SHIFT)
+
+/* 0x12C : se_aes_0_key_3 */
+#define SEC_ENG_SE_AES_0_KEY_3_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_3_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_3_SHIFT)
+
+/* 0x130 : se_aes_0_key_4 */
+#define SEC_ENG_SE_AES_0_KEY_4_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_4_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_4_SHIFT)
+
+/* 0x134 : se_aes_0_key_5 */
+#define SEC_ENG_SE_AES_0_KEY_5_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_5_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_5_SHIFT)
+
+/* 0x138 : se_aes_0_key_6 */
+#define SEC_ENG_SE_AES_0_KEY_6_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_6_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_6_SHIFT)
+
+/* 0x13C : se_aes_0_key_7 */
+#define SEC_ENG_SE_AES_0_KEY_7_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_7_MASK  (0xffffffff << SEC_ENG_SE_AES_0_KEY_7_SHIFT)
+
+/* 0x140 : se_aes_0_key_sel */
+#define SEC_ENG_SE_AES_0_KEY_SEL_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_KEY_SEL_MASK  (0x3 << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT)
+
+/* 0x144 : se_aes_1_key_sel */
+#define SEC_ENG_SE_AES_1_KEY_SEL_SHIFT (0U)
+#define SEC_ENG_SE_AES_1_KEY_SEL_MASK  (0x3 << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT)
+
+/* 0x148 : se_aes_0_endian */
+#define SEC_ENG_SE_AES_0_DOUT_ENDIAN   (1 << 0U)
+#define SEC_ENG_SE_AES_0_DIN_ENDIAN    (1 << 1U)
+#define SEC_ENG_SE_AES_0_KEY_ENDIAN    (1 << 2U)
+#define SEC_ENG_SE_AES_0_IV_ENDIAN     (1 << 3U)
+#define SEC_ENG_SE_AES_0_TWK_ENDIAN    (1 << 4U)
+#define SEC_ENG_SE_AES_0_CTR_LEN_SHIFT (30U)
+#define SEC_ENG_SE_AES_0_CTR_LEN_MASK  (0x3 << SEC_ENG_SE_AES_0_CTR_LEN_SHIFT)
+
+/* 0x14C : se_aes_sboot */
+#define SEC_ENG_SE_AES_0_SBOOT_KEY_SEL (1 << 0U)
+#define SEC_ENG_SE_AES_0_XTS_MODE      (1 << 15U)
+#define SEC_ENG_SE_AES_0_UNI_LEN_SHIFT (16U)
+#define SEC_ENG_SE_AES_0_UNI_LEN_MASK  (0xffff << SEC_ENG_SE_AES_0_UNI_LEN_SHIFT)
+
+/* 0x150 : se_aes_0_link */
+#define SEC_ENG_SE_AES_0_LCA_SHIFT (0U)
+#define SEC_ENG_SE_AES_0_LCA_MASK  (0xffffffff << SEC_ENG_SE_AES_0_LCA_SHIFT)
+
+/* 0x1FC : se_aes_0_ctrl_prot */
+#define SEC_ENG_SE_AES_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_AES_ID1_EN (1 << 2U)
+
+/* 0x200 : se_trng_0_ctrl_0 */
+#define SEC_ENG_SE_TRNG_0_BUSY           (1 << 0U)
+#define SEC_ENG_SE_TRNG_0_TRIG_1T        (1 << 1U)
+#define SEC_ENG_SE_TRNG_0_EN             (1 << 2U)
+#define SEC_ENG_SE_TRNG_0_DOUT_CLR_1T    (1 << 3U)
+#define SEC_ENG_SE_TRNG_0_HT_ERROR       (1 << 4U)
+#define SEC_ENG_SE_TRNG_0_INT            (1 << 8U)
+#define SEC_ENG_SE_TRNG_0_INT_CLR_1T     (1 << 9U)
+#define SEC_ENG_SE_TRNG_0_INT_SET_1T     (1 << 10U)
+#define SEC_ENG_SE_TRNG_0_INT_MASK       (1 << 11U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_FUN_SEL (1 << 13U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_RESEED  (1 << 14U)
+#define SEC_ENG_SE_TRNG_0_MANUAL_EN      (1 << 15U)
+
+/* 0x204 : se_trng_0_status */
+#define SEC_ENG_SE_TRNG_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_STATUS_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_STATUS_SHIFT)
+
+/* 0x208 : se_trng_0_dout_0 */
+#define SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_0_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_0_SHIFT)
+
+/* 0x20C : se_trng_0_dout_1 */
+#define SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_1_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_1_SHIFT)
+
+/* 0x210 : se_trng_0_dout_2 */
+#define SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_2_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_2_SHIFT)
+
+/* 0x214 : se_trng_0_dout_3 */
+#define SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_3_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_3_SHIFT)
+
+/* 0x218 : se_trng_0_dout_4 */
+#define SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_4_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_4_SHIFT)
+
+/* 0x21C : se_trng_0_dout_5 */
+#define SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_5_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_5_SHIFT)
+
+/* 0x220 : se_trng_0_dout_6 */
+#define SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_6_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_6_SHIFT)
+
+/* 0x224 : se_trng_0_dout_7 */
+#define SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_DOUT_7_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_DOUT_7_SHIFT)
+
+/* 0x228 : se_trng_0_test */
+#define SEC_ENG_SE_TRNG_0_TEST_EN          (1 << 0U)
+#define SEC_ENG_SE_TRNG_0_CP_TEST_EN       (1 << 1U)
+#define SEC_ENG_SE_TRNG_0_CP_BYPASS        (1 << 2U)
+#define SEC_ENG_SE_TRNG_0_HT_DIS           (1 << 3U)
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT (4U)
+#define SEC_ENG_SE_TRNG_0_HT_ALARM_N_MASK  (0xff << SEC_ENG_SE_TRNG_0_HT_ALARM_N_SHIFT)
+
+/* 0x22C : se_trng_0_ctrl_1 */
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_LSB_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_RESEED_N_LSB_SHIFT)
+
+/* 0x230 : se_trng_0_ctrl_2 */
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_RESEED_N_MSB_MASK  (0xffff << SEC_ENG_SE_TRNG_0_RESEED_N_MSB_SHIFT)
+
+/* 0x234 : se_trng_0_ctrl_3 */
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_CP_RATIO_MASK  (0xff << SEC_ENG_SE_TRNG_0_CP_RATIO_SHIFT)
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT (8U)
+#define SEC_ENG_SE_TRNG_0_HT_RCT_C_MASK  (0xff << SEC_ENG_SE_TRNG_0_HT_RCT_C_SHIFT)
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT (16U)
+#define SEC_ENG_SE_TRNG_0_HT_APT_C_MASK  (0x3ff << SEC_ENG_SE_TRNG_0_HT_APT_C_SHIFT)
+#define SEC_ENG_SE_TRNG_0_HT_OD_EN       (1 << 26U)
+#define SEC_ENG_SE_TRNG_0_ROSC_EN        (1 << 31U)
+
+/* 0x240 : se_trng_0_test_out_0 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_0_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_0_SHIFT)
+
+/* 0x244 : se_trng_0_test_out_1 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_1_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_1_SHIFT)
+
+/* 0x248 : se_trng_0_test_out_2 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_2_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_2_SHIFT)
+
+/* 0x24C : se_trng_0_test_out_3 */
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT (0U)
+#define SEC_ENG_SE_TRNG_0_TEST_OUT_3_MASK  (0xffffffff << SEC_ENG_SE_TRNG_0_TEST_OUT_3_SHIFT)
+
+/* 0x2FC : se_trng_0_ctrl_prot */
+#define SEC_ENG_SE_TRNG_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_TRNG_ID1_EN (1 << 2U)
+
+/* 0x300 : se_pka_0_ctrl_0 */
+#define SEC_ENG_SE_PKA_0_DONE          (1 << 0U)
+#define SEC_ENG_SE_PKA_0_DONE_CLR_1T   (1 << 1U)
+#define SEC_ENG_SE_PKA_0_BUSY          (1 << 2U)
+#define SEC_ENG_SE_PKA_0_EN            (1 << 3U)
+#define SEC_ENG_SE_PKA_0_PROT_MD_SHIFT (4U)
+#define SEC_ENG_SE_PKA_0_PROT_MD_MASK  (0xf << SEC_ENG_SE_PKA_0_PROT_MD_SHIFT)
+#define SEC_ENG_SE_PKA_0_INT           (1 << 8U)
+#define SEC_ENG_SE_PKA_0_INT_CLR_1T    (1 << 9U)
+#define SEC_ENG_SE_PKA_0_INT_SET       (1 << 10U)
+#define SEC_ENG_SE_PKA_0_INT_MASK      (1 << 11U)
+#define SEC_ENG_SE_PKA_0_ENDIAN        (1 << 12U)
+#define SEC_ENG_SE_PKA_0_RAM_CLR_MD    (1 << 13U)
+#define SEC_ENG_SE_PKA_0_STATUS_CLR_1T (1 << 15U)
+#define SEC_ENG_SE_PKA_0_STATUS_SHIFT  (16U)
+#define SEC_ENG_SE_PKA_0_STATUS_MASK   (0xffff << SEC_ENG_SE_PKA_0_STATUS_SHIFT)
+
+/* 0x30C : se_pka_0_seed */
+#define SEC_ENG_SE_PKA_0_SEED_SHIFT (0U)
+#define SEC_ENG_SE_PKA_0_SEED_MASK  (0xffffffff << SEC_ENG_SE_PKA_0_SEED_SHIFT)
+
+/* 0x310 : se_pka_0_ctrl_1 */
+#define SEC_ENG_SE_PKA_0_HBURST_SHIFT (0U)
+#define SEC_ENG_SE_PKA_0_HBURST_MASK  (0x7 << SEC_ENG_SE_PKA_0_HBURST_SHIFT)
+#define SEC_ENG_SE_PKA_0_HBYPASS      (1 << 3U)
+
+/* 0x340 : se_pka_0_rw */
+
+/* 0x360 : se_pka_0_rw_burst */
+
+/* 0x3FC : se_pka_0_ctrl_prot */
+#define SEC_ENG_SE_PKA_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_PKA_ID1_EN (1 << 2U)
+
+/* 0x400 : se_cdet_0_ctrl_0 */
+#define SEC_ENG_SE_CDET_0_EN           (1 << 0U)
+#define SEC_ENG_SE_CDET_0_BUSY         (1 << 1U)
+#define SEC_ENG_SE_CDET_0_STATUS_SHIFT (3U)
+#define SEC_ENG_SE_CDET_0_STATUS_MASK  (0x1f << SEC_ENG_SE_CDET_0_STATUS_SHIFT)
+#define SEC_ENG_SE_CDET_0_INT          (1 << 8U)
+#define SEC_ENG_SE_CDET_0_INT_CLR      (1 << 9U)
+#define SEC_ENG_SE_CDET_0_INT_SET      (1 << 10U)
+#define SEC_ENG_SE_CDET_0_INT_MASK     (1 << 11U)
+#define SEC_ENG_SE_CDET_0_MODE         (1 << 12U)
+
+/* 0x404 : se_cdet_0_ctrl_1 */
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT (0U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MAX_MASK  (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MAX_SHIFT)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT (16U)
+#define SEC_ENG_SE_CDET_0_G_LOOP_MIN_MASK  (0xffff << SEC_ENG_SE_CDET_0_G_LOOP_MIN_SHIFT)
+
+/* 0x408 : se_cdet_0_ctrl_2 */
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT (0U)
+#define SEC_ENG_SE_CDET_0_T_LOOP_N_MASK  (0xffff << SEC_ENG_SE_CDET_0_T_LOOP_N_SHIFT)
+#define SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT  (16U)
+#define SEC_ENG_SE_CDET_0_T_DLY_N_MASK   (0xff << SEC_ENG_SE_CDET_0_T_DLY_N_SHIFT)
+#define SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT  (24U)
+#define SEC_ENG_SE_CDET_0_G_SLP_N_MASK   (0xff << SEC_ENG_SE_CDET_0_G_SLP_N_SHIFT)
+
+/* 0x40C : se_cdet_0_ctrl_3 */
+#define SEC_ENG_SE_CDET_0_T_COUNT_SHIFT (0U)
+#define SEC_ENG_SE_CDET_0_T_COUNT_MASK  (0xffff << SEC_ENG_SE_CDET_0_T_COUNT_SHIFT)
+#define SEC_ENG_SE_CDET_0_G_COUNT_SHIFT (16U)
+#define SEC_ENG_SE_CDET_0_G_COUNT_MASK  (0xffff << SEC_ENG_SE_CDET_0_G_COUNT_SHIFT)
+
+/* 0x4FC : se_cdet_0_ctrl_prot */
+#define SEC_ENG_SE_CDET_PROT_EN (1 << 0U)
+#define SEC_ENG_SE_CDET_ID0_EN  (1 << 1U)
+#define SEC_ENG_SE_CDET_ID1_EN  (1 << 2U)
+
+/* 0x500 : se_gmac_0_ctrl_0 */
+#define SEC_ENG_SE_GMAC_0_BUSY       (1 << 0U)
+#define SEC_ENG_SE_GMAC_0_TRIG_1T    (1 << 1U)
+#define SEC_ENG_SE_GMAC_0_EN         (1 << 2U)
+#define SEC_ENG_SE_GMAC_0_INT        (1 << 8U)
+#define SEC_ENG_SE_GMAC_0_INT_CLR_1T (1 << 9U)
+#define SEC_ENG_SE_GMAC_0_INT_SET_1T (1 << 10U)
+#define SEC_ENG_SE_GMAC_0_INT_MASK   (1 << 11U)
+#define SEC_ENG_SE_GMAC_0_T_ENDIAN   (1 << 12U)
+#define SEC_ENG_SE_GMAC_0_H_ENDIAN   (1 << 13U)
+#define SEC_ENG_SE_GMAC_0_X_ENDIAN   (1 << 14U)
+
+/* 0x504 : se_gmac_0_lca */
+#define SEC_ENG_SE_GMAC_0_LCA_SHIFT (0U)
+#define SEC_ENG_SE_GMAC_0_LCA_MASK  (0xffffffff << SEC_ENG_SE_GMAC_0_LCA_SHIFT)
+
+/* 0x508 : se_gmac_0_status */
+#define SEC_ENG_SE_GMAC_0_STATUS_SHIFT (0U)
+#define SEC_ENG_SE_GMAC_0_STATUS_MASK  (0xffffffff << SEC_ENG_SE_GMAC_0_STATUS_SHIFT)
+
+/* 0x5FC : se_gmac_0_ctrl_prot */
+#define SEC_ENG_SE_GMAC_ID0_EN (1 << 1U)
+#define SEC_ENG_SE_GMAC_ID1_EN (1 << 2U)
+
+/* 0xF00 : se_ctrl_prot_rd */
+#define SEC_ENG_SE_SHA_ID0_EN_RD  (1 << 0U)
+#define SEC_ENG_SE_SHA_ID1_EN_RD  (1 << 1U)
+#define SEC_ENG_SE_AES_ID0_EN_RD  (1 << 2U)
+#define SEC_ENG_SE_AES_ID1_EN_RD  (1 << 3U)
+#define SEC_ENG_SE_TRNG_ID0_EN_RD (1 << 4U)
+#define SEC_ENG_SE_TRNG_ID1_EN_RD (1 << 5U)
+#define SEC_ENG_SE_PKA_ID0_EN_RD  (1 << 6U)
+#define SEC_ENG_SE_PKA_ID1_EN_RD  (1 << 7U)
+#define SEC_ENG_SE_CDET_ID0_EN_RD (1 << 8U)
+#define SEC_ENG_SE_CDET_ID1_EN_RD (1 << 9U)
+#define SEC_ENG_SE_GMAC_ID0_EN_RD (1 << 10U)
+#define SEC_ENG_SE_GMAC_ID1_EN_RD (1 << 11U)
+#define SEC_ENG_SE_DBG_DIS        (1 << 31U)
+
+/* 0xF04 : se_ctrl_reserved_0 */
+#define SEC_ENG_SE_CTRL_RESERVED_0_SHIFT (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_0_MASK  (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_0_SHIFT)
+
+/* 0xF08 : se_ctrl_reserved_1 */
+#define SEC_ENG_SE_CTRL_RESERVED_1_SHIFT (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_1_MASK  (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_1_SHIFT)
+
+/* 0xF0C : se_ctrl_reserved_2 */
+#define SEC_ENG_SE_CTRL_RESERVED_2_SHIFT (0U)
+#define SEC_ENG_SE_CTRL_RESERVED_2_MASK  (0xffffffff << SEC_ENG_SE_CTRL_RESERVED_2_SHIFT)
+
+#endif /* __HARDWARE_SEC_ENG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sf_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sf_ctrl_reg.h
new file mode 100755
index 0000000000..2f1b5ee4e5
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/sf_ctrl_reg.h
@@ -0,0 +1,983 @@
+/**
+  ******************************************************************************
+  * @file    sf_ctrl_reg.h
+  * @version V1.0
+  * @date    2022-10-20
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __SF_CTRL_REG_H__
+#define  __SF_CTRL_REG_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SF_CTRL_0_OFFSET                                        (0x0)/* sf_ctrl_0 */
+#define SF_CTRL_1_OFFSET                                        (0x4)/* sf_ctrl_1 */
+#define SF_CTRL_SF_IF_SAHB_0_OFFSET                             (0x8)/* sf_if_sahb_0 */
+#define SF_CTRL_SF_IF_SAHB_1_OFFSET                             (0xC)/* sf_if_sahb_1 */
+#define SF_CTRL_SF_IF_SAHB_2_OFFSET                             (0x10)/* sf_if_sahb_2 */
+#define SF_CTRL_SF_IF_IAHB_0_OFFSET                             (0x14)/* sf_if_iahb_0 */
+#define SF_CTRL_SF_IF_IAHB_1_OFFSET                             (0x18)/* sf_if_iahb_1 */
+#define SF_CTRL_SF_IF_IAHB_2_OFFSET                             (0x1C)/* sf_if_iahb_2 */
+#define SF_CTRL_SF_IF_STATUS_0_OFFSET                           (0x20)/* sf_if_status_0 */
+#define SF_CTRL_SF_IF_STATUS_1_OFFSET                           (0x24)/* sf_if_status_1 */
+#define SF_CTRL_SF_AES_OFFSET                                   (0x28)/* sf_aes */
+#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET                        (0x2C)/* sf_ahb2sif_status */
+#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET                           (0x30)/* sf_if_io_dly_0 */
+#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET                           (0x34)/* sf_if_io_dly_1 */
+#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET                           (0x38)/* sf_if_io_dly_2 */
+#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET                           (0x3C)/* sf_if_io_dly_3 */
+#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET                           (0x40)/* sf_if_io_dly_4 */
+#define SF_CTRL_SF_RESERVED_OFFSET                              (0x44)/* sf_reserved */
+#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET                          (0x48)/* sf2_if_io_dly_0 */
+#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET                          (0x4C)/* sf2_if_io_dly_1 */
+#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET                          (0x50)/* sf2_if_io_dly_2 */
+#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET                          (0x54)/* sf2_if_io_dly_3 */
+#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET                          (0x58)/* sf2_if_io_dly_4 */
+#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET                          (0x5C)/* sf3_if_io_dly_0 */
+#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET                          (0x60)/* sf3_if_io_dly_1 */
+#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET                          (0x64)/* sf3_if_io_dly_2 */
+#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET                          (0x68)/* sf3_if_io_dly_3 */
+#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET                          (0x6C)/* sf3_if_io_dly_4 */
+#define SF_CTRL_2_OFFSET                                        (0x70)/* sf_ctrl_2 */
+#define SF_CTRL_3_OFFSET                                        (0x74)/* sf_ctrl_3 */
+#define SF_CTRL_SF_IF_IAHB_3_OFFSET                             (0x78)/* sf_if_iahb_3 */
+#define SF_CTRL_SF_IF_IAHB_4_OFFSET                             (0x7C)/* sf_if_iahb_4 */
+#define SF_CTRL_SF_IF_IAHB_5_OFFSET                             (0x80)/* sf_if_iahb_5 */
+#define SF_CTRL_SF_IF_IAHB_6_OFFSET                             (0x84)/* sf_if_iahb_6 */
+#define SF_CTRL_SF_IF_IAHB_7_OFFSET                             (0x88)/* sf_if_iahb_7 */
+#define SF_CTRL_SF_IF_IAHB_8_OFFSET                             (0x8C)/* sf_if_iahb_8 */
+#define SF_CTRL_SF_IF_IAHB_9_OFFSET                             (0x90)/* sf_if_iahb_9 */
+#define SF_CTRL_SF_IF_IAHB_10_OFFSET                            (0x94)/* sf_if_iahb_10 */
+#define SF_CTRL_SF_IF_IAHB_11_OFFSET                            (0x98)/* sf_if_iahb_11 */
+#define SF_CTRL_SF_IF_IAHB_12_OFFSET                            (0x9C)/* sf_if_iahb_12 */
+#define SF_CTRL_SF_ID0_OFFSET_OFFSET                            (0xA0)/* sf_id0_offset */
+#define SF_CTRL_SF_ID1_OFFSET_OFFSET                            (0xA4)/* sf_id1_offset */
+#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET                        (0xA8)/* sf_bk2_id0_offset */
+#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET                        (0xAC)/* sf_bk2_id1_offset */
+#define SF_CTRL_SF_DBG_OFFSET                                   (0xB0)/* sf_dbg */
+#define SF_CTRL_SF_IF2_CTRL_0_OFFSET                            (0xC0)/* sf_if2_ctrl_0 */
+#define SF_CTRL_SF_IF2_CTRL_1_OFFSET                            (0xC4)/* sf_if2_ctrl_1 */
+#define SF_CTRL_SF_IF2_SAHB_0_OFFSET                            (0xC8)/* sf_if2_sahb_0 */
+#define SF_CTRL_SF_IF2_SAHB_1_OFFSET                            (0xCC)/* sf_if2_sahb_1 */
+#define SF_CTRL_SF_IF2_SAHB_2_OFFSET                            (0xD0)/* sf_if2_sahb_2 */
+#define SF_CTRL_PROT_EN_RD_OFFSET                               (0x100)/* sf_ctrl_prot_en_rd */
+#define SF_CTRL_PROT_EN_OFFSET                                  (0x104)/* sf_ctrl_prot_en */
+#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET                          (0x200)/* sf_aes_key_r0_0 */
+#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET                          (0x204)/* sf_aes_key_r0_1 */
+#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET                          (0x208)/* sf_aes_key_r0_2 */
+#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET                          (0x20C)/* sf_aes_key_r0_3 */
+#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET                          (0x210)/* sf_aes_key_r0_4 */
+#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET                          (0x214)/* sf_aes_key_r0_5 */
+#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET                          (0x218)/* sf_aes_key_r0_6 */
+#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET                          (0x21C)/* sf_aes_key_r0_7 */
+#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET                          (0x220)/* sf_aes_iv_r0_w0 */
+#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET                          (0x224)/* sf_aes_iv_r0_w1 */
+#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET                          (0x228)/* sf_aes_iv_r0_w2 */
+#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET                          (0x22C)/* sf_aes_iv_r0_w3 */
+#define SF_CTRL_SF_AES_R0_START_OFFSET                          (0x230)/* sf_aes_r0_start */
+#define SF_CTRL_SF_AES_R0_END_OFFSET                            (0x234)/* sf_aes_r0_end */
+#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET                          (0x280)/* sf_aes_key_r1_0 */
+#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET                          (0x284)/* sf_aes_key_r1_1 */
+#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET                          (0x288)/* sf_aes_key_r1_2 */
+#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET                          (0x28C)/* sf_aes_key_r1_3 */
+#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET                          (0x290)/* sf_aes_key_r1_4 */
+#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET                          (0x294)/* sf_aes_key_r1_5 */
+#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET                          (0x298)/* sf_aes_key_r1_6 */
+#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET                          (0x29C)/* sf_aes_key_r1_7 */
+#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET                          (0x2A0)/* sf_aes_iv_r1_w0 */
+#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET                          (0x2A4)/* sf_aes_iv_r1_w1 */
+#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET                          (0x2A8)/* sf_aes_iv_r1_w2 */
+#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET                          (0x2AC)/* sf_aes_iv_r1_w3 */
+#define SF_CTRL_SF_AES_R1_START_OFFSET                          (0x2B0)/* sf_aes_r1_start */
+#define SF_CTRL_SF_AES_R1_END_OFFSET                            (0x2B4)/* sf_aes_r1_end */
+#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET                          (0x300)/* sf_aes_key_r2_0 */
+#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET                          (0x304)/* sf_aes_key_r2_1 */
+#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET                          (0x308)/* sf_aes_key_r2_2 */
+#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET                          (0x30C)/* sf_aes_key_r2_3 */
+#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET                          (0x310)/* sf_aes_key_r2_4 */
+#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET                          (0x314)/* sf_aes_key_r2_5 */
+#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET                          (0x318)/* sf_aes_key_r2_6 */
+#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET                          (0x31C)/* sf_aes_key_r2_7 */
+#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET                          (0x320)/* sf_aes_iv_r2_w0 */
+#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET                          (0x324)/* sf_aes_iv_r2_w1 */
+#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET                          (0x328)/* sf_aes_iv_r2_w2 */
+#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET                          (0x32C)/* sf_aes_iv_r2_w3 */
+#define SF_CTRL_SF_AES_R2_START_OFFSET                          (0x330)/* sf_aes_r2_start */
+#define SF_CTRL_SF_AES_R2_END_OFFSET                            (0x334)/* sf_aes_r2_end */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : sf_ctrl_0 */
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL                            (1<<2U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN                              (1<<3U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL                              (1<<4U)
+#define SF_CTRL_SF_IF_READ_DLY_N_SHIFT                          (8U)
+#define SF_CTRL_SF_IF_READ_DLY_N_MASK                           (0x7<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_SPI_H__
+#define __HARDWARE_SPI_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define SPI_CONFIG_OFFSET        (0x0)  /* spi_config */
+#define SPI_INT_STS_OFFSET       (0x4)  /* spi_int_sts */
+#define SPI_BUS_BUSY_OFFSET      (0x8)  /* spi_bus_busy */
+#define SPI_PRD_0_OFFSET         (0x10) /* spi_prd_0 */
+#define SPI_PRD_1_OFFSET         (0x14) /* spi_prd_1 */
+#define SPI_RXD_IGNR_OFFSET      (0x18) /* spi_rxd_ignr */
+#define SPI_STO_VALUE_OFFSET     (0x1C) /* spi_sto_value */
+#define SPI_FIFO_CONFIG_0_OFFSET (0x80) /* spi_fifo_config_0 */
+#define SPI_FIFO_CONFIG_1_OFFSET (0x84) /* spi_fifo_config_1 */
+#define SPI_FIFO_WDATA_OFFSET    (0x88) /* spi_fifo_wdata */
+#define SPI_FIFO_RDATA_OFFSET    (0x8C) /* spi_fifo_rdata */
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_BACKUP_IO_EN_OFFSET (0xFC) /* backup_io_en */
+#endif
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : spi_config */
+#define SPI_CR_SPI_M_EN             (1 << 0U)
+#define SPI_CR_SPI_S_EN             (1 << 1U)
+#define SPI_CR_SPI_FRAME_SIZE_SHIFT (2U)
+#define SPI_CR_SPI_FRAME_SIZE_MASK  (0x3 << SPI_CR_SPI_FRAME_SIZE_SHIFT)
+#define SPI_CR_SPI_SCLK_POL         (1 << 4U)
+#define SPI_CR_SPI_SCLK_PH          (1 << 5U)
+#define SPI_CR_SPI_BIT_INV          (1 << 6U)
+#define SPI_CR_SPI_BYTE_INV         (1 << 7U)
+#define SPI_CR_SPI_RXD_IGNR_EN      (1 << 8U)
+#define SPI_CR_SPI_M_CONT_EN        (1 << 9U)
+#define SPI_CR_SPI_S_3PIN_MODE      (1 << 10U)
+#define SPI_CR_SPI_DEG_EN           (1 << 11U)
+#define SPI_CR_SPI_DEG_CNT_SHIFT    (12U)
+#define SPI_CR_SPI_DEG_CNT_MASK     (0xf << SPI_CR_SPI_DEG_CNT_SHIFT)
+
+/* 0x4 : spi_int_sts */
+#define SPI_END_INT         (1 << 0U)
+#define SPI_TXF_INT         (1 << 1U)
+#define SPI_RXF_INT         (1 << 2U)
+#define SPI_STO_INT         (1 << 3U)
+#define SPI_TXU_INT         (1 << 4U)
+#define SPI_FER_INT         (1 << 5U)
+#define SPI_CR_SPI_END_MASK (1 << 8U)
+#define SPI_CR_SPI_TXF_MASK (1 << 9U)
+#define SPI_CR_SPI_RXF_MASK (1 << 10U)
+#define SPI_CR_SPI_STO_MASK (1 << 11U)
+#define SPI_CR_SPI_TXU_MASK (1 << 12U)
+#define SPI_CR_SPI_FER_MASK (1 << 13U)
+#define SPI_CR_SPI_END_CLR  (1 << 16U)
+#define SPI_CR_SPI_STO_CLR  (1 << 19U)
+#define SPI_CR_SPI_TXU_CLR  (1 << 20U)
+#define SPI_CR_SPI_END_EN   (1 << 24U)
+#define SPI_CR_SPI_TXF_EN   (1 << 25U)
+#define SPI_CR_SPI_RXF_EN   (1 << 26U)
+#define SPI_CR_SPI_STO_EN   (1 << 27U)
+#define SPI_CR_SPI_TXU_EN   (1 << 28U)
+#define SPI_CR_SPI_FER_EN   (1 << 29U)
+
+/* 0x8 : spi_bus_busy */
+#define SPI_STS_SPI_BUS_BUSY (1 << 0U)
+
+/* 0x10 : spi_prd_0 */
+#define SPI_CR_SPI_PRD_S_SHIFT      (0U)
+#define SPI_CR_SPI_PRD_S_MASK       (0xff << SPI_CR_SPI_PRD_S_SHIFT)
+#define SPI_CR_SPI_PRD_P_SHIFT      (8U)
+#define SPI_CR_SPI_PRD_P_MASK       (0xff << SPI_CR_SPI_PRD_P_SHIFT)
+#define SPI_CR_SPI_PRD_D_PH_0_SHIFT (16U)
+#define SPI_CR_SPI_PRD_D_PH_0_MASK  (0xff << SPI_CR_SPI_PRD_D_PH_0_SHIFT)
+#define SPI_CR_SPI_PRD_D_PH_1_SHIFT (24U)
+#define SPI_CR_SPI_PRD_D_PH_1_MASK  (0xff << SPI_CR_SPI_PRD_D_PH_1_SHIFT)
+
+/* 0x14 : spi_prd_1 */
+#define SPI_CR_SPI_PRD_I_SHIFT (0U)
+#define SPI_CR_SPI_PRD_I_MASK  (0xff << SPI_CR_SPI_PRD_I_SHIFT)
+
+/* 0x18 : spi_rxd_ignr */
+#define SPI_CR_SPI_RXD_IGNR_P_SHIFT (0U)
+#define SPI_CR_SPI_RXD_IGNR_P_MASK  (0x1f << SPI_CR_SPI_RXD_IGNR_P_SHIFT)
+#define SPI_CR_SPI_RXD_IGNR_S_SHIFT (16U)
+#define SPI_CR_SPI_RXD_IGNR_S_MASK  (0x1f << SPI_CR_SPI_RXD_IGNR_S_SHIFT)
+
+/* 0x1C : spi_sto_value */
+#define SPI_CR_SPI_STO_VALUE_SHIFT (0U)
+#define SPI_CR_SPI_STO_VALUE_MASK  (0xfff << SPI_CR_SPI_STO_VALUE_SHIFT)
+
+/* 0x80 : spi_fifo_config_0 */
+#define SPI_DMA_TX_EN         (1 << 0U)
+#define SPI_DMA_RX_EN         (1 << 1U)
+#define SPI_TX_FIFO_CLR       (1 << 2U)
+#define SPI_RX_FIFO_CLR       (1 << 3U)
+#define SPI_TX_FIFO_OVERFLOW  (1 << 4U)
+#define SPI_TX_FIFO_UNDERFLOW (1 << 5U)
+#define SPI_RX_FIFO_OVERFLOW  (1 << 6U)
+#define SPI_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x84 : spi_fifo_config_1 */
+#define SPI_TX_FIFO_CNT_SHIFT (0U)
+#if defined(BL702) || defined(BL602)
+#define SPI_TX_FIFO_CNT_MASK (0x7 << SPI_TX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define SPI_TX_FIFO_CNT_MASK (0x1f << SPI_TX_FIFO_CNT_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_TX_FIFO_CNT_MASK (0x3f << SPI_TX_FIFO_CNT_SHIFT)
+#endif
+#define SPI_RX_FIFO_CNT_SHIFT (8U)
+#if defined(BL702) || defined(BL602)
+#define SPI_RX_FIFO_CNT_MASK (0x7 << SPI_RX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define SPI_RX_FIFO_CNT_MASK (0x1f << SPI_RX_FIFO_CNT_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_RX_FIFO_CNT_MASK (0x3f << SPI_RX_FIFO_CNT_SHIFT)
+#endif
+#define SPI_TX_FIFO_TH_SHIFT (16U)
+#if defined(BL702) || defined(BL602)
+#define SPI_TX_FIFO_TH_MASK (0x3 << SPI_TX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define SPI_TX_FIFO_TH_MASK (0xf << SPI_TX_FIFO_TH_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_TX_FIFO_TH_MASK (0x1f << SPI_TX_FIFO_TH_SHIFT)
+#endif
+#define SPI_RX_FIFO_TH_SHIFT (24U)
+#if defined(BL702) || defined(BL602)
+#define SPI_RX_FIFO_TH_MASK (0x3 << SPI_RX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define SPI_RX_FIFO_TH_MASK (0xf << SPI_RX_FIFO_TH_SHIFT)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define SPI_RX_FIFO_TH_MASK (0x1f << SPI_RX_FIFO_TH_SHIFT)
+#endif
+
+/* 0x88 : spi_fifo_wdata */
+#define SPI_FIFO_WDATA_SHIFT (0U)
+#define SPI_FIFO_WDATA_MASK  (0xffffffff << SPI_FIFO_WDATA_SHIFT)
+
+/* 0x8C : spi_fifo_rdata */
+#define SPI_FIFO_RDATA_SHIFT (0U)
+#define SPI_FIFO_RDATA_MASK  (0xffffffff << SPI_FIFO_RDATA_SHIFT)
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+/* 0xFC : backup_io_en */
+#define SPI_BACKUP_IO_EN (1 << 0U)
+#endif
+
+#endif /* __HARDWARE_SPI_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/timer_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/timer_reg.h
new file mode 100755
index 0000000000..6af022d5b4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/timer_reg.h
@@ -0,0 +1,285 @@
+/**
+  ******************************************************************************
+  * @file    timer_reg.h
+  * @version V1.0
+  * @date    2022-08-03
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_TIMER_H__
+#define __HARDWARE_TIMER_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define TIMER_TCCR_OFFSET    (0x0)  /* Timer Clock Source */
+#define TIMER_TMR0_0_OFFSET  (0x10) /* Timer0 Match Value 0 */
+#define TIMER_TMR0_1_OFFSET  (0x14) /* Timer0 Match Value 1 */
+#define TIMER_TMR0_2_OFFSET  (0x18) /* Timer0 Match Value 2 */
+#define TIMER_TMR1_0_OFFSET  (0x1C) /* Timer1 Match Value 0 */
+#define TIMER_TMR1_1_OFFSET  (0x20) /* Timer1 Match Value 1 */
+#define TIMER_TMR1_2_OFFSET  (0x24) /* Timer1 Match Value 2 */
+#define TIMER_TCR0_OFFSET    (0x2C) /* Timer0 Counter Value */
+#define TIMER_TCR1_OFFSET    (0x30) /* Timer1 Counter Value */
+#define TIMER_TSR0_OFFSET    (0x38) /* Timer0 Match Status */
+#define TIMER_TSR1_OFFSET    (0x3C) /* Timer1 Match Status */
+#define TIMER_TIER0_OFFSET   (0x44) /* Timer0 Match Interrupt Enable */
+#define TIMER_TIER1_OFFSET   (0x48) /* Timer1 Match Interrupt Enable */
+#define TIMER_TPLVR0_OFFSET  (0x50) /* Timer0 Pre-Load Value */
+#define TIMER_TPLVR1_OFFSET  (0x54) /* Timer1 Pre-Load Value */
+#define TIMER_TPLCR0_OFFSET  (0x5C) /* Timer0 Pre-Load Control */
+#define TIMER_TPLCR1_OFFSET  (0x60) /* Timer1 Pre-Load Control */
+#define TIMER_WMER_OFFSET    (0x64) /* Watch-dog reset/interrupt Mode */
+#define TIMER_WMR_OFFSET     (0x68) /* Watch-dog Match Value */
+#define TIMER_WVR_OFFSET     (0x6C) /* Watch-dog Counter Value */
+#define TIMER_WSR_OFFSET     (0x70) /* Watch-dog Reset Status */
+#define TIMER_TICR0_OFFSET   (0x78) /* Timer0 Interrupt Clear */
+#define TIMER_TICR1_OFFSET   (0x7C) /* Timer1 Interrupt Clear */
+#define TIMER_WICR_OFFSET    (0x80) /* WDT Interrupt Clear */
+#define TIMER_TCER_OFFSET    (0x84) /* Timer Counter Enable/Clear */
+#define TIMER_TCMR_OFFSET    (0x88) /* Timer Counter Mode */
+#define TIMER_TILR0_OFFSET   (0x90) /* Timer0 Match Interrupt Mode */
+#define TIMER_TILR1_OFFSET   (0x94) /* Timer1 Match Interrupt Mode */
+#define TIMER_WCR_OFFSET     (0x98) /* WDT Counter Reset */
+#define TIMER_WFAR_OFFSET    (0x9C) /* WDT Access Key1 */
+#define TIMER_WSAR_OFFSET    (0xA0) /* WDT Access Key2 */
+#define TIMER_TCVWR0_OFFSET  (0xA8) /* Timer0 Counter Latch Value */
+#define TIMER_TCVWR1_OFFSET  (0xAC) /* Timer1 Counter Latch Value */
+#define TIMER_TCVSYN0_OFFSET (0xB4) /* Timer0 Counter Sync Value */
+#define TIMER_TCVSYN1_OFFSET (0xB8) /* Timer1 Counter Sync Value */
+#define TIMER_TCDR_OFFSET    (0xBC) /* Timer Division */
+#if !defined(BL702) || !defined(BL602)
+#define TIMER_GPIO_OFFSET       (0xC0) /* GPIO Mode */
+#define TIMER_GPIO_LAT1_OFFSET  (0xC4) /* GPIO Latch Value1 */
+#define TIMER_GPIO_LAT2_OFFSET  (0xC8) /* GPIO Latch Value2 */
+#define TIMER_TCDR_FORCE_OFFSET (0xCC) /* Timer Division Force */
+#endif
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : Timer Clock Source */
+#if defined(BL702) || defined(BL602)
+#define TIMER_CS_0_SHIFT   (2U)
+#define TIMER_CS_0_MASK    (0x3 << TIMER_CS_0_SHIFT)
+#define TIMER_CS_1_SHIFT   (5U)
+#define TIMER_CS_1_MASK    (0x3 << TIMER_CS_1_SHIFT)
+#define TIMER_CS_WDT_SHIFT (8U)
+#define TIMER_CS_WDT_MASK  (0x3 << TIMER_CS_WDT_SHIFT)
+#else
+#define TIMER_CS_0_SHIFT   (0U)
+#define TIMER_CS_0_MASK    (0xf << TIMER_CS_0_SHIFT)
+#define TIMER_CS_1_SHIFT   (4U)
+#define TIMER_CS_1_MASK    (0xf << TIMER_CS_1_SHIFT)
+#define TIMER_CS_WDT_SHIFT (8U)
+#define TIMER_CS_WDT_MASK  (0xf << TIMER_CS_WDT_SHIFT)
+#define TIMER_ID_SHIFT     (24U)
+#define TIMER_ID_MASK      (0xff << TIMER_ID_SHIFT)
+#endif
+
+/* 0x10 : Timer0 Match Value 0 */
+#define TIMER_TMR0_0_SHIFT (0U)
+#define TIMER_TMR0_0_MASK  (0xffffffff << TIMER_TMR0_0_SHIFT)
+
+/* 0x14 : Timer0 Match Value 1 */
+#define TIMER_TMR0_1_SHIFT (0U)
+#define TIMER_TMR0_1_MASK  (0xffffffff << TIMER_TMR0_1_SHIFT)
+
+/* 0x18 : Timer0 Match Value 2 */
+#define TIMER_TMR0_2_SHIFT (0U)
+#define TIMER_TMR0_2_MASK  (0xffffffff << TIMER_TMR0_2_SHIFT)
+
+/* 0x1C : Timer1 Match Value 0 */
+#define TIMER_TMR1_0_SHIFT (0U)
+#define TIMER_TMR1_0_MASK  (0xffffffff << TIMER_TMR1_0_SHIFT)
+
+/* 0x20 : Timer1 Match Value 1 */
+#define TIMER_TMR1_1_SHIFT (0U)
+#define TIMER_TMR1_1_MASK  (0xffffffff << TIMER_TMR1_1_SHIFT)
+
+/* 0x24 : Timer1 Match Value 2 */
+#define TIMER_TMR1_2_SHIFT (0U)
+#define TIMER_TMR1_2_MASK  (0xffffffff << TIMER_TMR1_2_SHIFT)
+
+/* 0x2C : Timer0 Counter Value */
+#define TIMER_TCR0_CNT_SHIFT (0U)
+#define TIMER_TCR0_CNT_MASK  (0xffffffff << TIMER_TCR0_CNT_SHIFT)
+
+/* 0x30 : Timer1 Counter Value */
+#define TIMER_TCR1_CNT_SHIFT (0U)
+#define TIMER_TCR1_CNT_MASK  (0xffffffff << TIMER_TCR1_CNT_SHIFT)
+
+/* 0x38 : Timer0 Match Status */
+#define TIMER_TSR0_0 (1 << 0U)
+#define TIMER_TSR0_1 (1 << 1U)
+#define TIMER_TSR0_2 (1 << 2U)
+
+/* 0x3C : Timer1 Match Status */
+#define TIMER_TSR1_0 (1 << 0U)
+#define TIMER_TSR1_1 (1 << 1U)
+#define TIMER_TSR1_2 (1 << 2U)
+
+/* 0x44 : Timer0 Match Interrupt Enable */
+#define TIMER_TIER0_0 (1 << 0U)
+#define TIMER_TIER0_1 (1 << 1U)
+#define TIMER_TIER0_2 (1 << 2U)
+
+/* 0x48 : Timer1 Match Interrupt Enable */
+#define TIMER_TIER1_0 (1 << 0U)
+#define TIMER_TIER1_1 (1 << 1U)
+#define TIMER_TIER1_2 (1 << 2U)
+
+/* 0x50 : Timer0 Pre-Load Value */
+#define TIMER_TPLVR0_SHIFT (0U)
+#define TIMER_TPLVR0_MASK  (0xffffffff << TIMER_TPLVR0_SHIFT)
+
+/* 0x54 : Timer1 Pre-Load Value */
+#define TIMER_TPLVR1_SHIFT (0U)
+#define TIMER_TPLVR1_MASK  (0xffffffff << TIMER_TPLVR1_SHIFT)
+
+/* 0x5C : Timer0 Pre-Load Control */
+#define TIMER_TPLCR0_SHIFT (0U)
+#define TIMER_TPLCR0_MASK  (0x3 << TIMER_TPLCR0_SHIFT)
+
+/* 0x60 : Timer1 Pre-Load Control */
+#define TIMER_TPLCR1_SHIFT (0U)
+#define TIMER_TPLCR1_MASK  (0x3 << TIMER_TPLCR1_SHIFT)
+
+/* 0x64 : Watch-dog reset/interrupt Mode */
+#define TIMER_WE   (1 << 0U)
+#define TIMER_WRIE (1 << 1U)
+
+/* 0x68 : Watch-dog Match Value */
+#define TIMER_WMR_SHIFT (0U)
+#define TIMER_WMR_MASK  (0xffff << TIMER_WMR_SHIFT)
+#define TIMER_WDT_ALIGN (1 << 16U)
+
+/* 0x6C : Watch-dog Counter Value */
+#define TIMER_WDT_CNT_SHIFT (0U)
+#define TIMER_WDT_CNT_MASK  (0xffff << TIMER_WDT_CNT_SHIFT)
+
+/* 0x70 : Watch-dog Reset Status */
+#define TIMER_WTS (1 << 0U)
+
+/* 0x78 : Timer0 Interrupt Clear */
+#define TIMER_TCLR0_0 (1 << 0U)
+#define TIMER_TCLR0_1 (1 << 1U)
+#define TIMER_TCLR0_2 (1 << 2U)
+
+/* 0x7C : Timer1 Interrupt Clear */
+#define TIMER_TCLR1_0 (1 << 0U)
+#define TIMER_TCLR1_1 (1 << 1U)
+#define TIMER_TCLR1_2 (1 << 2U)
+
+/* 0x80 : WDT Interrupt Clear */
+#define TIMER_WICLR (1 << 0U)
+
+/* 0x84 : Timer Counter Enable/Clear */
+#define TIMER0_EN          (1 << 1U)
+#define TIMER1_EN          (1 << 2U)
+#define TIMER_TCR0_CNT_CLR (1 << 5U)
+#define TIMER_TCR1_CNT_CLR (1 << 6U)
+
+/* 0x88 : Timer Counter Mode */
+#define TIMER0_MODE  (1 << 1U)
+#define TIMER1_MODE  (1 << 2U)
+#define TIMER0_ALIGN (1 << 5U)
+#define TIMER1_ALIGN (1 << 6U)
+
+/* 0x90 : Timer0 Match Interrupt Mode */
+#define TIMER_TILR0_0 (1 << 0U)
+#define TIMER_TILR0_1 (1 << 1U)
+#define TIMER_TILR0_2 (1 << 2U)
+
+/* 0x94 : Timer1 Match Interrupt Mode */
+#define TIMER_TILR1_0 (1 << 0U)
+#define TIMER_TILR1_1 (1 << 1U)
+#define TIMER_TILR1_2 (1 << 2U)
+
+/* 0x98 : WDT Counter Reset */
+#define TIMER_WCR (1 << 0U)
+
+/* 0x9C : WDT Access Key1 */
+#define TIMER_WFAR_SHIFT (0U)
+#define TIMER_WFAR_MASK  (0xffff << TIMER_WFAR_SHIFT)
+
+/* 0xA0 : WDT Access Key2 */
+#define TIMER_WSAR_SHIFT (0U)
+#define TIMER_WSAR_MASK  (0xffff << TIMER_WSAR_SHIFT)
+
+/* 0xA8 : Timer0 Counter Latch Value */
+#define TIMER_TCR0_CNT_LAT_SHIFT (0U)
+#define TIMER_TCR0_CNT_LAT_MASK  (0xffffffff << TIMER_TCR0_CNT_LAT_SHIFT)
+
+/* 0xAC : Timer1 Counter Latch Value */
+#define TIMER_TCR1_CNT_LAT_SHIFT (0U)
+#define TIMER_TCR1_CNT_LAT_MASK  (0xffffffff << TIMER_TCR1_CNT_LAT_SHIFT)
+
+/* 0xB4 : Timer0 Counter Sync Value */
+#define TIMER_TCR0_CNT_SYNC_SHIFT (0U)
+#define TIMER_TCR0_CNT_SYNC_MASK  (0xffffffff << TIMER_TCR0_CNT_SYNC_SHIFT)
+
+/* 0xB8 : Timer1 Counter Sync Value */
+#define TIMER_TCR1_CNT_SYNC_SHIFT (0U)
+#define TIMER_TCR1_CNT_SYNC_MASK  (0xffffffff << TIMER_TCR1_CNT_SYNC_SHIFT)
+
+/* 0xBC : Timer Division */
+#define TIMER_TCDR0_SHIFT (8U)
+#define TIMER_TCDR0_MASK  (0xff << TIMER_TCDR0_SHIFT)
+#define TIMER_TCDR1_SHIFT (16U)
+#define TIMER_TCDR1_MASK  (0xff << TIMER_TCDR1_SHIFT)
+#define TIMER_WCDR_SHIFT  (24U)
+#define TIMER_WCDR_MASK   (0xff << TIMER_WCDR_SHIFT)
+
+#if !defined(BL702) || !defined(BL602)
+/* 0xC0 : GPIO Mode */
+#define TIMER0_GPIO_EN     (1 << 1U)
+#define TIMER0_GPIO_INV    (1 << 5U)
+#define TIMER1_GPIO_INV    (1 << 6U)
+#define TIMER_WDT_GPIO_INV (1 << 7U)
+#define TIMER_GPIO_LAT_OK  (1 << 31U)
+
+/* 0xC4 : GPIO Latch Value1 */
+#define TIMER_GPIO_LAT1_SHIFT (0U)
+#define TIMER_GPIO_LAT1_MASK  (0xffffffff << TIMER_GPIO_LAT1_SHIFT)
+
+/* 0xC8 : GPIO Latch Value2 */
+#define TIMER_GPIO_LAT2_SHIFT (0U)
+#define TIMER_GPIO_LAT2_MASK  (0xffffffff << TIMER_GPIO_LAT2_SHIFT)
+
+/* 0xCC : Timer Division Force */
+#define TIMER_TCDR0_FORCE (1 << 1U)
+#define TIMER_TCDR1_FORCE (1 << 2U)
+#define TIMER_WCDR_FORCE  (1 << 4U)
+#endif
+
+#endif /* __HARDWARE_TIMER_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/uart_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/uart_reg.h
new file mode 100755
index 0000000000..39e2f9ecf0
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/uart_reg.h
@@ -0,0 +1,370 @@
+/**
+  ******************************************************************************
+  * @file    uart_reg.h
+  * @version V1.0
+  * @date    2022-06-10
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_UART_H__
+#define __HARDWARE_UART_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define UART_UTX_CONFIG_OFFSET  (0x0) /* utx_config */
+#define UART_URX_CONFIG_OFFSET  (0x4) /* urx_config */
+#define UART_BIT_PRD_OFFSET     (0x8) /* uart_bit_prd */
+#define UART_DATA_CONFIG_OFFSET (0xC) /* data_config */
+#if !defined(BL702L)
+#define UART_UTX_IR_POSITION_OFFSET (0x10) /* utx_ir_position */
+#define UART_URX_IR_POSITION_OFFSET (0x14) /* urx_ir_position */
+#endif
+#define UART_URX_RTO_TIMER_OFFSET (0x18) /* urx_rto_timer */
+#if !defined(BL602)
+#define UART_SW_MODE_OFFSET (0x1C) /* uart_sw_mode */
+#endif
+#define UART_INT_STS_OFFSET         (0x20) /* UART interrupt status */
+#define UART_INT_MASK_OFFSET        (0x24) /* UART interrupt mask */
+#define UART_INT_CLEAR_OFFSET       (0x28) /* UART interrupt clear */
+#define UART_INT_EN_OFFSET          (0x2C) /* UART interrupt enable */
+#define UART_STATUS_OFFSET          (0x30) /* uart_status */
+#define UART_STS_URX_ABR_PRD_OFFSET (0x34) /* sts_urx_abr_prd */
+#if !defined(BL602) && !defined(BL702)
+#define UART_URX_ABR_PRD_B01_OFFSET (0x38) /* urx_abr_prd_b01 */
+#define UART_URX_ABR_PRD_B23_OFFSET (0x3C) /* urx_abr_prd_b23 */
+#define UART_URX_ABR_PRD_B45_OFFSET (0x40) /* urx_abr_prd_b45 */
+#define UART_URX_ABR_PRD_B67_OFFSET (0x44) /* urx_abr_prd_b67 */
+#define UART_URX_ABR_PW_TOL_OFFSET  (0x48) /* urx_abr_pw_tol */
+#define UART_URX_BCR_INT_CFG_OFFSET (0x50) /* urx_bcr_int_cfg */
+#define UART_UTX_RS485_CFG_OFFSET   (0x54) /* utx_rs485_cfg */
+#endif
+#define UART_FIFO_CONFIG_0_OFFSET (0x80) /* uart_fifo_config_0 */
+#define UART_FIFO_CONFIG_1_OFFSET (0x84) /* uart_fifo_config_1 */
+#define UART_FIFO_WDATA_OFFSET    (0x88) /* uart_fifo_wdata */
+#define UART_FIFO_RDATA_OFFSET    (0x8C) /* uart_fifo_rdata */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : utx_config */
+#define UART_CR_UTX_EN     (1 << 0U)
+#define UART_CR_UTX_CTS_EN (1 << 1U)
+#define UART_CR_UTX_FRM_EN (1 << 2U)
+#if !defined(BL602)
+#define UART_CR_UTX_LIN_EN (1 << 3U)
+#endif
+#define UART_CR_UTX_PRT_EN  (1 << 4U)
+#define UART_CR_UTX_PRT_SEL (1 << 5U)
+#if !defined(BL702L)
+#define UART_CR_UTX_IR_EN  (1 << 6U)
+#define UART_CR_UTX_IR_INV (1 << 7U)
+#endif
+#define UART_CR_UTX_BIT_CNT_D_SHIFT (8U)
+#define UART_CR_UTX_BIT_CNT_D_MASK  (0x7 << UART_CR_UTX_BIT_CNT_D_SHIFT)
+#if defined(BL602)
+#define UART_CR_UTX_BIT_CNT_P_SHIFT (12U)
+#else
+#define UART_CR_UTX_BIT_CNT_P_SHIFT (11U)
+#endif
+#define UART_CR_UTX_BIT_CNT_P_MASK (0x3 << UART_CR_UTX_BIT_CNT_P_SHIFT)
+#if !defined(BL602)
+#define UART_CR_UTX_BIT_CNT_B_SHIFT (13U)
+#define UART_CR_UTX_BIT_CNT_B_MASK  (0x7 << UART_CR_UTX_BIT_CNT_B_SHIFT)
+#endif
+#define UART_CR_UTX_LEN_SHIFT (16U)
+#define UART_CR_UTX_LEN_MASK  (0xffff << UART_CR_UTX_LEN_SHIFT)
+
+/* 0x4 : urx_config */
+#define UART_CR_URX_EN (1 << 0U)
+#if defined(BL602)
+#define UART_CR_URX_RTS_SW_MODE (1 << 1U)
+#define UART_CR_URX_RTS_SW_VAL  (1 << 2U)
+#define UART_CR_URX_ABR_EN      (1 << 3U)
+#else
+#define UART_CR_URX_ABR_EN (1 << 1U)
+#define UART_CR_URX_LIN_EN (1 << 3U)
+#endif
+#define UART_CR_URX_PRT_EN  (1 << 4U)
+#define UART_CR_URX_PRT_SEL (1 << 5U)
+#if !defined(BL702L)
+#define UART_CR_URX_IR_EN  (1 << 6U)
+#define UART_CR_URX_IR_INV (1 << 7U)
+#endif
+#define UART_CR_URX_BIT_CNT_D_SHIFT (8U)
+#define UART_CR_URX_BIT_CNT_D_MASK  (0x7 << UART_CR_URX_BIT_CNT_D_SHIFT)
+#define UART_CR_URX_DEG_EN          (1 << 11U)
+#define UART_CR_URX_DEG_CNT_SHIFT   (12U)
+#define UART_CR_URX_DEG_CNT_MASK    (0xf << UART_CR_URX_DEG_CNT_SHIFT)
+#define UART_CR_URX_LEN_SHIFT       (16U)
+#define UART_CR_URX_LEN_MASK        (0xffff << UART_CR_URX_LEN_SHIFT)
+
+/* 0x8 : uart_bit_prd */
+#define UART_CR_UTX_BIT_PRD_SHIFT (0U)
+#define UART_CR_UTX_BIT_PRD_MASK  (0xffff << UART_CR_UTX_BIT_PRD_SHIFT)
+#define UART_CR_URX_BIT_PRD_SHIFT (16U)
+#define UART_CR_URX_BIT_PRD_MASK  (0xffff << UART_CR_URX_BIT_PRD_SHIFT)
+
+/* 0xC : data_config */
+#define UART_CR_UART_BIT_INV (1 << 0U)
+
+#if !defined(BL702L)
+/* 0x10 : utx_ir_position */
+#define UART_CR_UTX_IR_POS_S_SHIFT (0U)
+#define UART_CR_UTX_IR_POS_S_MASK  (0xffff << UART_CR_UTX_IR_POS_S_SHIFT)
+#define UART_CR_UTX_IR_POS_P_SHIFT (16U)
+#define UART_CR_UTX_IR_POS_P_MASK  (0xffff << UART_CR_UTX_IR_POS_P_SHIFT)
+
+/* 0x14 : urx_ir_position */
+#define UART_CR_URX_IR_POS_S_SHIFT (0U)
+#define UART_CR_URX_IR_POS_S_MASK  (0xffff << UART_CR_URX_IR_POS_S_SHIFT)
+#endif
+
+/* 0x18 : urx_rto_timer */
+#define UART_CR_URX_RTO_VALUE_SHIFT (0U)
+#define UART_CR_URX_RTO_VALUE_MASK  (0xff << UART_CR_URX_RTO_VALUE_SHIFT)
+
+#if !defined(BL602)
+/* 0x1C : uart_sw_mode */
+#define UART_CR_UTX_TXD_SW_MODE (1 << 0U)
+#define UART_CR_UTX_TXD_SW_VAL  (1 << 1U)
+#define UART_CR_URX_RTS_SW_MODE (1 << 2U)
+#define UART_CR_URX_RTS_SW_VAL  (1 << 3U)
+#endif
+
+/* 0x20 : UART interrupt status */
+#define UART_UTX_END_INT  (1 << 0U)
+#define UART_URX_END_INT  (1 << 1U)
+#define UART_UTX_FIFO_INT (1 << 2U)
+#define UART_URX_FIFO_INT (1 << 3U)
+#define UART_URX_RTO_INT  (1 << 4U)
+#define UART_URX_PCE_INT  (1 << 5U)
+#define UART_UTX_FER_INT  (1 << 6U)
+#define UART_URX_FER_INT  (1 << 7U)
+#if !defined(BL602)
+#define UART_URX_LSE_INT (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_URX_BCR_INT (1 << 9U)
+#define UART_URX_ADS_INT (1 << 10U)
+#define UART_URX_AD5_INT (1 << 11U)
+#endif
+
+/* 0x24 : UART interrupt mask */
+#define UART_CR_UTX_END_MASK  (1 << 0U)
+#define UART_CR_URX_END_MASK  (1 << 1U)
+#define UART_CR_UTX_FIFO_MASK (1 << 2U)
+#define UART_CR_URX_FIFO_MASK (1 << 3U)
+#define UART_CR_URX_RTO_MASK  (1 << 4U)
+#define UART_CR_URX_PCE_MASK  (1 << 5U)
+#define UART_CR_UTX_FER_MASK  (1 << 6U)
+#define UART_CR_URX_FER_MASK  (1 << 7U)
+#if !defined(BL602)
+#define UART_CR_URX_LSE_MASK (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_CR_URX_BCR_MASK (1 << 9U)
+#define UART_CR_URX_ADS_MASK (1 << 10U)
+#define UART_CR_URX_AD5_MASK (1 << 11U)
+#endif
+
+/* 0x28 : UART interrupt clear */
+#define UART_CR_UTX_END_CLR (1 << 0U)
+#define UART_CR_URX_END_CLR (1 << 1U)
+#define UART_CR_URX_RTO_CLR (1 << 4U)
+#define UART_CR_URX_PCE_CLR (1 << 5U)
+#if !defined(BL602)
+#define UART_CR_URX_LSE_CLR (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_CR_URX_BCR_CLR (1 << 9U)
+#define UART_CR_URX_ADS_CLR (1 << 10U)
+#define UART_CR_URX_AD5_CLR (1 << 11U)
+#endif
+
+/* 0x2C : UART interrupt enable */
+#define UART_CR_UTX_END_EN  (1 << 0U)
+#define UART_CR_URX_END_EN  (1 << 1U)
+#define UART_CR_UTX_FIFO_EN (1 << 2U)
+#define UART_CR_URX_FIFO_EN (1 << 3U)
+#define UART_CR_URX_RTO_EN  (1 << 4U)
+#define UART_CR_URX_PCE_EN  (1 << 5U)
+#define UART_CR_UTX_FER_EN  (1 << 6U)
+#define UART_CR_URX_FER_EN  (1 << 7U)
+#if !defined(BL602)
+#define UART_CR_URX_LSE_EN (1 << 8U)
+#endif
+#if !defined(BL602) && !defined(BL702)
+#define UART_CR_URX_BCR_EN (1 << 9U)
+#define UART_CR_URX_ADS_EN (1 << 10U)
+#define UART_CR_URX_AD5_EN (1 << 11U)
+#endif
+
+/* 0x30 : uart_status */
+#define UART_STS_UTX_BUS_BUSY (1 << 0U)
+#define UART_STS_URX_BUS_BUSY (1 << 1U)
+
+/* 0x34 : sts_urx_abr_prd */
+#define UART_STS_URX_ABR_PRD_START_SHIFT (0U)
+#define UART_STS_URX_ABR_PRD_START_MASK  (0xffff << UART_STS_URX_ABR_PRD_START_SHIFT)
+#define UART_STS_URX_ABR_PRD_0X55_SHIFT  (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_0X55_MASK (0x3ff << UART_STS_URX_ABR_PRD_0X55_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_0X55_MASK (0xffff << UART_STS_URX_ABR_PRD_0X55_SHIFT)
+#endif
+
+#if !defined(BL602) && !defined(BL702)
+/* 0x38 : urx_abr_prd_b01 */
+#define UART_STS_URX_ABR_PRD_BIT0_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT0_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT0_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT0_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT0_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT1_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT1_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT1_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT1_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT1_SHIFT)
+#endif
+
+/* 0x3C : urx_abr_prd_b23 */
+#define UART_STS_URX_ABR_PRD_BIT2_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT2_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT2_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT2_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT2_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT3_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT3_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT3_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT3_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT3_SHIFT)
+#endif
+
+/* 0x40 : urx_abr_prd_b45 */
+#define UART_STS_URX_ABR_PRD_BIT4_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT4_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT4_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT4_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT4_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT5_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT5_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT5_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT5_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT5_SHIFT)
+#endif
+
+/* 0x44 : urx_abr_prd_b67 */
+#define UART_STS_URX_ABR_PRD_BIT6_SHIFT (0U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT6_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT6_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT6_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT6_SHIFT)
+#endif
+#define UART_STS_URX_ABR_PRD_BIT7_SHIFT (16U)
+#if defined(BL702L)
+#define UART_STS_URX_ABR_PRD_BIT7_MASK (0x3ff << UART_STS_URX_ABR_PRD_BIT7_SHIFT)
+#else
+#define UART_STS_URX_ABR_PRD_BIT7_MASK (0xffff << UART_STS_URX_ABR_PRD_BIT7_SHIFT)
+#endif
+
+/* 0x48 : urx_abr_pw_tol */
+#define UART_CR_URX_ABR_PW_TOL_SHIFT (0U)
+#define UART_CR_URX_ABR_PW_TOL_MASK  (0xff << UART_CR_URX_ABR_PW_TOL_SHIFT)
+
+/* 0x50 : urx_bcr_int_cfg */
+#define UART_CR_URX_BCR_VALUE_SHIFT  (0U)
+#define UART_CR_URX_BCR_VALUE_MASK   (0xffff << UART_CR_URX_BCR_VALUE_SHIFT)
+#define UART_STS_URX_BCR_COUNT_SHIFT (16U)
+#define UART_STS_URX_BCR_COUNT_MASK  (0xffff << UART_STS_URX_BCR_COUNT_SHIFT)
+
+/* 0x54 : utx_rs485_cfg */
+#define UART_CR_UTX_RS485_EN  (1 << 0U)
+#define UART_CR_UTX_RS485_POL (1 << 1U)
+#endif
+
+/* 0x80 : uart_fifo_config_0 */
+#define UART_DMA_TX_EN         (1 << 0U)
+#define UART_DMA_RX_EN         (1 << 1U)
+#define UART_TX_FIFO_CLR       (1 << 2U)
+#define UART_RX_FIFO_CLR       (1 << 3U)
+#define UART_TX_FIFO_OVERFLOW  (1 << 4U)
+#define UART_TX_FIFO_UNDERFLOW (1 << 5U)
+#define UART_RX_FIFO_OVERFLOW  (1 << 6U)
+#define UART_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x84 : uart_fifo_config_1 */
+#define UART_TX_FIFO_CNT_SHIFT (0U)
+#if defined(BL702)
+#define UART_TX_FIFO_CNT_MASK (0xff << UART_TX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define UART_TX_FIFO_CNT_MASK (0x1f << UART_TX_FIFO_CNT_SHIFT)
+#else
+#define UART_TX_FIFO_CNT_MASK (0x3f << UART_TX_FIFO_CNT_SHIFT)
+#endif
+#define UART_RX_FIFO_CNT_SHIFT (8U)
+#if defined(BL702)
+#define UART_RX_FIFO_CNT_MASK (0xff << UART_RX_FIFO_CNT_SHIFT)
+#elif defined(BL702L)
+#define UART_RX_FIFO_CNT_MASK (0x1f << UART_RX_FIFO_CNT_SHIFT)
+#else
+#define UART_RX_FIFO_CNT_MASK (0x3f << UART_RX_FIFO_CNT_SHIFT)
+#endif
+#define UART_TX_FIFO_TH_SHIFT (16U)
+#if defined(BL702)
+#define UART_TX_FIFO_TH_MASK (0x7f << UART_TX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define UART_TX_FIFO_TH_MASK (0xf << UART_TX_FIFO_TH_SHIFT)
+#else
+#define UART_TX_FIFO_TH_MASK (0x1f << UART_TX_FIFO_TH_SHIFT)
+#endif
+#define UART_RX_FIFO_TH_SHIFT (24U)
+#if defined(BL702)
+#define UART_RX_FIFO_TH_MASK (0x7f << UART_RX_FIFO_TH_SHIFT)
+#elif defined(BL702L)
+#define UART_RX_FIFO_TH_MASK (0xf << UART_RX_FIFO_TH_SHIFT)
+#else
+#define UART_RX_FIFO_TH_MASK (0x1f << UART_RX_FIFO_TH_SHIFT)
+#endif
+
+/* 0x88 : uart_fifo_wdata */
+#define UART_FIFO_WDATA_SHIFT (0U)
+#define UART_FIFO_WDATA_MASK  (0xff << UART_FIFO_WDATA_SHIFT)
+
+/* 0x8C : uart_fifo_rdata */
+#define UART_FIFO_RDATA_SHIFT (0U)
+#define UART_FIFO_RDATA_MASK  (0xff << UART_FIFO_RDATA_SHIFT)
+
+#endif /* __HARDWARE_UART_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v1_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v1_reg.h
new file mode 100755
index 0000000000..57cc404eb4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v1_reg.h
@@ -0,0 +1,618 @@
+/**
+  ******************************************************************************
+  * @file    usb_v1_reg.h
+  * @version V1.0
+  * @date    2022-08-15
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_USB_V1_H__
+#define __HARDWARE_USB_V1_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define USB_CONFIG_OFFSET            (0x0)   /* usb_config */
+#define USB_LPM_CONFIG_OFFSET        (0x4)   /* usb_lpm_config */
+#define USB_RESUME_CONFIG_OFFSET     (0x8)   /* usb_resume_config */
+#define USB_SETUP_DATA_0_OFFSET      (0x10)  /* usb_setup_data_0 */
+#define USB_SETUP_DATA_1_OFFSET      (0x14)  /* usb_setup_data_1 */
+#define USB_FRAME_NO_OFFSET          (0x18)  /* usb_frame_no */
+#define USB_ERROR_OFFSET             (0x1C)  /* usb_error */
+#define USB_INT_EN_OFFSET            (0x20)  /* USB interrupt enable */
+#define USB_INT_STS_OFFSET           (0x24)  /* USB interrupt status */
+#define USB_INT_MASK_OFFSET          (0x28)  /* USB interrupt mask */
+#define USB_INT_CLEAR_OFFSET         (0x2C)  /* USB interrupt clear */
+#define USB_EP1_CONFIG_OFFSET        (0x40)  /* ep1_config */
+#define USB_EP2_CONFIG_OFFSET        (0x44)  /* ep2_config */
+#define USB_EP3_CONFIG_OFFSET        (0x48)  /* ep3_config */
+#define USB_EP4_CONFIG_OFFSET        (0x4C)  /* ep4_config */
+#define USB_EP5_CONFIG_OFFSET        (0x50)  /* ep5_config */
+#define USB_EP6_CONFIG_OFFSET        (0x54)  /* ep6_config */
+#define USB_EP7_CONFIG_OFFSET        (0x58)  /* ep7_config */
+#define USB_EP0_FIFO_CONFIG_OFFSET   (0x100) /* ep0_fifo_config */
+#define USB_EP0_FIFO_STATUS_OFFSET   (0x104) /* ep0_fifo_status */
+#define USB_EP0_TX_FIFO_WDATA_OFFSET (0x108) /* ep0_tx_fifo_wdata */
+#define USB_EP0_RX_FIFO_RDATA_OFFSET (0x10C) /* ep0_rx_fifo_rdata */
+#define USB_EP1_FIFO_CONFIG_OFFSET   (0x110) /* ep1_fifo_config */
+#define USB_EP1_FIFO_STATUS_OFFSET   (0x114) /* ep1_fifo_status */
+#define USB_EP1_TX_FIFO_WDATA_OFFSET (0x118) /* ep1_tx_fifo_wdata */
+#define USB_EP1_RX_FIFO_RDATA_OFFSET (0x11C) /* ep1_rx_fifo_rdata */
+#define USB_EP2_FIFO_CONFIG_OFFSET   (0x120) /* ep2_fifo_config */
+#define USB_EP2_FIFO_STATUS_OFFSET   (0x124) /* ep2_fifo_status */
+#define USB_EP2_TX_FIFO_WDATA_OFFSET (0x128) /* ep2_tx_fifo_wdata */
+#define USB_EP2_RX_FIFO_RDATA_OFFSET (0x12C) /* ep2_rx_fifo_rdata */
+#define USB_EP3_FIFO_CONFIG_OFFSET   (0x130) /* ep3_fifo_config */
+#define USB_EP3_FIFO_STATUS_OFFSET   (0x134) /* ep3_fifo_status */
+#define USB_EP3_TX_FIFO_WDATA_OFFSET (0x138) /* ep3_tx_fifo_wdata */
+#define USB_EP3_RX_FIFO_RDATA_OFFSET (0x13C) /* ep3_rx_fifo_rdata */
+#define USB_EP4_FIFO_CONFIG_OFFSET   (0x140) /* ep4_fifo_config */
+#define USB_EP4_FIFO_STATUS_OFFSET   (0x144) /* ep4_fifo_status */
+#define USB_EP4_TX_FIFO_WDATA_OFFSET (0x148) /* ep4_tx_fifo_wdata */
+#define USB_EP4_RX_FIFO_RDATA_OFFSET (0x14C) /* ep4_rx_fifo_rdata */
+#define USB_EP5_FIFO_CONFIG_OFFSET   (0x150) /* ep5_fifo_config */
+#define USB_EP5_FIFO_STATUS_OFFSET   (0x154) /* ep5_fifo_status */
+#define USB_EP5_TX_FIFO_WDATA_OFFSET (0x158) /* ep5_tx_fifo_wdata */
+#define USB_EP5_RX_FIFO_RDATA_OFFSET (0x15C) /* ep5_rx_fifo_rdata */
+#define USB_EP6_FIFO_CONFIG_OFFSET   (0x160) /* ep6_fifo_config */
+#define USB_EP6_FIFO_STATUS_OFFSET   (0x164) /* ep6_fifo_status */
+#define USB_EP6_TX_FIFO_WDATA_OFFSET (0x168) /* ep6_tx_fifo_wdata */
+#define USB_EP6_RX_FIFO_RDATA_OFFSET (0x16C) /* ep6_rx_fifo_rdata */
+#define USB_EP7_FIFO_CONFIG_OFFSET   (0x170) /* ep7_fifo_config */
+#define USB_EP7_FIFO_STATUS_OFFSET   (0x174) /* ep7_fifo_status */
+#define USB_EP7_TX_FIFO_WDATA_OFFSET (0x178) /* ep7_tx_fifo_wdata */
+#define USB_EP7_RX_FIFO_RDATA_OFFSET (0x17C) /* ep7_rx_fifo_rdata */
+#define USB_RSVD_0_OFFSET            (0x1F0) /* rsvd_0 */
+#define USB_RSVD_1_OFFSET            (0x1F4) /* rsvd_1 */
+#define USB_XCVR_IF_CONFIG_OFFSET    (0x1FC) /* xcvr_if_config */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : usb_config */
+#define USB_CR_USB_EN                (1 << 0U)
+#define USB_CR_USB_ROM_DCT_EN        (1 << 4U)
+#define USB_CR_USB_EP0_SW_CTRL       (1 << 8U)
+#define USB_CR_USB_EP0_SW_ADDR_SHIFT (9U)
+#define USB_CR_USB_EP0_SW_ADDR_MASK  (0x7f << USB_CR_USB_EP0_SW_ADDR_SHIFT)
+#define USB_CR_USB_EP0_SW_SIZE_SHIFT (16U)
+#define USB_CR_USB_EP0_SW_SIZE_MASK  (0xff << USB_CR_USB_EP0_SW_SIZE_SHIFT)
+#define USB_CR_USB_EP0_SW_STALL      (1 << 24U)
+#define USB_CR_USB_EP0_SW_NACK_IN    (1 << 25U)
+#define USB_CR_USB_EP0_SW_NACK_OUT   (1 << 26U)
+#define USB_CR_USB_EP0_SW_RDY        (1 << 27U)
+#define USB_STS_USB_EP0_SW_RDY       (1 << 28U)
+
+/* 0x4 : usb_lpm_config */
+#define USB_CR_LPM_EN          (1 << 0U)
+#define USB_CR_LPM_RESP_UPD    (1 << 1U)
+#define USB_CR_LPM_RESP_SHIFT  (2U)
+#define USB_CR_LPM_RESP_MASK   (0x3 << USB_CR_LPM_RESP_SHIFT)
+#define USB_STS_LPM_ATTR_SHIFT (20U)
+#define USB_STS_LPM_ATTR_MASK  (0x7ff << USB_STS_LPM_ATTR_SHIFT)
+#define USB_STS_LPM            (1 << 31U)
+
+/* 0x8 : usb_resume_config */
+#define USB_CR_RES_WIDTH_SHIFT (0U)
+#define USB_CR_RES_WIDTH_MASK  (0x7ff << USB_CR_RES_WIDTH_SHIFT)
+#define USB_CR_RES_TRIG        (1 << 12U)
+#define USB_CR_RES_FORCE       (1 << 31U)
+
+/* 0x10 : usb_setup_data_0 */
+#define USB_STS_SETUP_DATA_B0_SHIFT (0U)
+#define USB_STS_SETUP_DATA_B0_MASK  (0xff << USB_STS_SETUP_DATA_B0_SHIFT)
+#define USB_STS_SETUP_DATA_B1_SHIFT (8U)
+#define USB_STS_SETUP_DATA_B1_MASK  (0xff << USB_STS_SETUP_DATA_B1_SHIFT)
+#define USB_STS_SETUP_DATA_B2_SHIFT (16U)
+#define USB_STS_SETUP_DATA_B2_MASK  (0xff << USB_STS_SETUP_DATA_B2_SHIFT)
+#define USB_STS_SETUP_DATA_B3_SHIFT (24U)
+#define USB_STS_SETUP_DATA_B3_MASK  (0xff << USB_STS_SETUP_DATA_B3_SHIFT)
+
+/* 0x14 : usb_setup_data_1 */
+#define USB_STS_SETUP_DATA_B4_SHIFT (0U)
+#define USB_STS_SETUP_DATA_B4_MASK  (0xff << USB_STS_SETUP_DATA_B4_SHIFT)
+#define USB_STS_SETUP_DATA_B5_SHIFT (8U)
+#define USB_STS_SETUP_DATA_B5_MASK  (0xff << USB_STS_SETUP_DATA_B5_SHIFT)
+#define USB_STS_SETUP_DATA_B6_SHIFT (16U)
+#define USB_STS_SETUP_DATA_B6_MASK  (0xff << USB_STS_SETUP_DATA_B6_SHIFT)
+#define USB_STS_SETUP_DATA_B7_SHIFT (24U)
+#define USB_STS_SETUP_DATA_B7_MASK  (0xff << USB_STS_SETUP_DATA_B7_SHIFT)
+
+/* 0x18 : usb_frame_no */
+#define USB_STS_FRAME_NO_SHIFT (0U)
+#define USB_STS_FRAME_NO_MASK  (0x7ff << USB_STS_FRAME_NO_SHIFT)
+#define USB_STS_PID_SHIFT      (12U)
+#define USB_STS_PID_MASK       (0xf << USB_STS_PID_SHIFT)
+#define USB_STS_EP_NO_SHIFT    (16U)
+#define USB_STS_EP_NO_MASK     (0xf << USB_STS_EP_NO_SHIFT)
+
+/* 0x1C : usb_error */
+#define USB_UTMI_RX_ERR (1 << 0U)
+#define USB_XFER_TO_ERR (1 << 1U)
+#define USB_IVLD_EP_ERR (1 << 2U)
+#define USB_PID_SEQ_ERR (1 << 3U)
+#define USB_PID_CKS_ERR (1 << 4U)
+#define USB_CRC5_ERR    (1 << 5U)
+#define USB_CRC16_ERR   (1 << 6U)
+
+/* 0x20 : USB interrupt enable */
+#define USB_CR_SOF_EN            (1 << 0U)
+#define USB_CR_USB_RESET_EN      (1 << 1U)
+#define USB_CR_VBUS_TGL_EN       (1 << 2U)
+#define USB_CR_GET_DCT_CMD_EN    (1 << 3U)
+#define USB_CR_EP0_SETUP_CMD_EN  (1 << 4U)
+#define USB_CR_EP0_SETUP_DONE_EN (1 << 5U)
+#define USB_CR_EP0_IN_CMD_EN     (1 << 6U)
+#define USB_CR_EP0_IN_DONE_EN    (1 << 7U)
+#define USB_CR_EP0_OUT_CMD_EN    (1 << 8U)
+#define USB_CR_EP0_OUT_DONE_EN   (1 << 9U)
+#define USB_CR_EP1_CMD_EN        (1 << 10U)
+#define USB_CR_EP1_DONE_EN       (1 << 11U)
+#define USB_CR_EP2_CMD_EN        (1 << 12U)
+#define USB_CR_EP2_DONE_EN       (1 << 13U)
+#define USB_CR_EP3_CMD_EN        (1 << 14U)
+#define USB_CR_EP3_DONE_EN       (1 << 15U)
+#define USB_CR_EP4_CMD_EN        (1 << 16U)
+#define USB_CR_EP4_DONE_EN       (1 << 17U)
+#define USB_CR_EP5_CMD_EN        (1 << 18U)
+#define USB_CR_EP5_DONE_EN       (1 << 19U)
+#define USB_CR_EP6_CMD_EN        (1 << 20U)
+#define USB_CR_EP6_DONE_EN       (1 << 21U)
+#define USB_CR_EP7_CMD_EN        (1 << 22U)
+#define USB_CR_EP7_DONE_EN       (1 << 23U)
+#define USB_CR_USB_REND_EN       (1 << 27U)
+#define USB_CR_LPM_WKUP_EN       (1 << 28U)
+#define USB_CR_LPM_PKT_EN        (1 << 29U)
+#define USB_CR_SOF_3MS_EN        (1 << 30U)
+#define USB_CR_USB_ERR_EN        (1 << 31U)
+
+/* 0x24 : USB interrupt status */
+#define USB_SOF_INT            (1 << 0U)
+#define USB_RESET_INT          (1 << 1U)
+#define USB_VBUS_TGL_INT       (1 << 2U)
+#define USB_GET_DCT_CMD_INT    (1 << 3U)
+#define USB_EP0_SETUP_CMD_INT  (1 << 4U)
+#define USB_EP0_SETUP_DONE_INT (1 << 5U)
+#define USB_EP0_IN_CMD_INT     (1 << 6U)
+#define USB_EP0_IN_DONE_INT    (1 << 7U)
+#define USB_EP0_OUT_CMD_INT    (1 << 8U)
+#define USB_EP0_OUT_DONE_INT   (1 << 9U)
+#define USB_EP1_CMD_INT        (1 << 10U)
+#define USB_EP1_DONE_INT       (1 << 11U)
+#define USB_EP2_CMD_INT        (1 << 12U)
+#define USB_EP2_DONE_INT       (1 << 13U)
+#define USB_EP3_CMD_INT        (1 << 14U)
+#define USB_EP3_DONE_INT       (1 << 15U)
+#define USB_EP4_CMD_INT        (1 << 16U)
+#define USB_EP4_DONE_INT       (1 << 17U)
+#define USB_EP5_CMD_INT        (1 << 18U)
+#define USB_EP5_DONE_INT       (1 << 19U)
+#define USB_EP6_CMD_INT        (1 << 20U)
+#define USB_EP6_DONE_INT       (1 << 21U)
+#define USB_EP7_CMD_INT        (1 << 22U)
+#define USB_EP7_DONE_INT       (1 << 23U)
+#define USB_REND_INT           (1 << 27U)
+#define USB_LPM_WKUP_INT       (1 << 28U)
+#define USB_LPM_PKT_INT        (1 << 29U)
+#define USB_SOF_3MS_INT        (1 << 30U)
+#define USB_ERR_INT            (1 << 31U)
+
+/* 0x28 : USB interrupt mask */
+#define USB_CR_SOF_MASK            (1 << 0U)
+#define USB_CR_USB_RESET_MASK      (1 << 1U)
+#define USB_CR_VBUS_TGL_MASK       (1 << 2U)
+#define USB_CR_GET_DCT_CMD_MASK    (1 << 3U)
+#define USB_CR_EP0_SETUP_CMD_MASK  (1 << 4U)
+#define USB_CR_EP0_SETUP_DONE_MASK (1 << 5U)
+#define USB_CR_EP0_IN_CMD_MASK     (1 << 6U)
+#define USB_CR_EP0_IN_DONE_MASK    (1 << 7U)
+#define USB_CR_EP0_OUT_CMD_MASK    (1 << 8U)
+#define USB_CR_EP0_OUT_DONE_MASK   (1 << 9U)
+#define USB_CR_EP1_CMD_MASK        (1 << 10U)
+#define USB_CR_EP1_DONE_MASK       (1 << 11U)
+#define USB_CR_EP2_CMD_MASK        (1 << 12U)
+#define USB_CR_EP2_DONE_MASK       (1 << 13U)
+#define USB_CR_EP3_CMD_MASK        (1 << 14U)
+#define USB_CR_EP3_DONE_MASK       (1 << 15U)
+#define USB_CR_EP4_CMD_MASK        (1 << 16U)
+#define USB_CR_EP4_DONE_MASK       (1 << 17U)
+#define USB_CR_EP5_CMD_MASK        (1 << 18U)
+#define USB_CR_EP5_DONE_MASK       (1 << 19U)
+#define USB_CR_EP6_CMD_MASK        (1 << 20U)
+#define USB_CR_EP6_DONE_MASK       (1 << 21U)
+#define USB_CR_EP7_CMD_MASK        (1 << 22U)
+#define USB_CR_EP7_DONE_MASK       (1 << 23U)
+#define USB_CR_USB_REND_MASK       (1 << 27U)
+#define USB_CR_LPM_WKUP_MASK       (1 << 28U)
+#define USB_CR_LPM_PKT_MASK        (1 << 29U)
+#define USB_CR_SOF_3MS_MASK        (1 << 30U)
+#define USB_CR_USB_ERR_MASK        (1 << 31U)
+
+/* 0x2C : USB interrupt clear */
+#define USB_CR_SOF_CLR            (1 << 0U)
+#define USB_CR_USB_RESET_CLR      (1 << 1U)
+#define USB_CR_VBUS_TGL_CLR       (1 << 2U)
+#define USB_CR_GET_DCT_CMD_CLR    (1 << 3U)
+#define USB_CR_EP0_SETUP_CMD_CLR  (1 << 4U)
+#define USB_CR_EP0_SETUP_DONE_CLR (1 << 5U)
+#define USB_CR_EP0_IN_CMD_CLR     (1 << 6U)
+#define USB_CR_EP0_IN_DONE_CLR    (1 << 7U)
+#define USB_CR_EP0_OUT_CMD_CLR    (1 << 8U)
+#define USB_CR_EP0_OUT_DONE_CLR   (1 << 9U)
+#define USB_CR_EP1_CMD_CLR        (1 << 10U)
+#define USB_CR_EP1_DONE_CLR       (1 << 11U)
+#define USB_CR_EP2_CMD_CLR        (1 << 12U)
+#define USB_CR_EP2_DONE_CLR       (1 << 13U)
+#define USB_CR_EP3_CMD_CLR        (1 << 14U)
+#define USB_CR_EP3_DONE_CLR       (1 << 15U)
+#define USB_CR_EP4_CMD_CLR        (1 << 16U)
+#define USB_CR_EP4_DONE_CLR       (1 << 17U)
+#define USB_CR_EP5_CMD_CLR        (1 << 18U)
+#define USB_CR_EP5_DONE_CLR       (1 << 19U)
+#define USB_CR_EP6_CMD_CLR        (1 << 20U)
+#define USB_CR_EP6_DONE_CLR       (1 << 21U)
+#define USB_CR_EP7_CMD_CLR        (1 << 22U)
+#define USB_CR_EP7_DONE_CLR       (1 << 23U)
+#define USB_CR_USB_REND_CLR       (1 << 27U)
+#define USB_CR_LPM_WKUP_CLR       (1 << 28U)
+#define USB_CR_LPM_PKT_CLR        (1 << 29U)
+#define USB_CR_SOF_3MS_CLR        (1 << 30U)
+#define USB_CR_USB_ERR_CLR        (1 << 31U)
+
+/* 0x40 : ep1_config */
+#define USB_CR_EP1_SIZE_SHIFT (0U)
+#define USB_CR_EP1_SIZE_MASK  (0x7ff << USB_CR_EP1_SIZE_SHIFT)
+#define USB_CR_EP1_DIR_SHIFT  (11U)
+#define USB_CR_EP1_DIR_MASK   (0x3 << USB_CR_EP1_DIR_SHIFT)
+#define USB_CR_EP1_TYPE_SHIFT (13U)
+#define USB_CR_EP1_TYPE_MASK  (0x7 << USB_CR_EP1_TYPE_SHIFT)
+#define USB_CR_EP1_STALL      (1 << 16U)
+#define USB_CR_EP1_NACK       (1 << 17U)
+#define USB_CR_EP1_RDY        (1 << 18U)
+#define USB_STS_EP1_RDY       (1 << 19U)
+
+/* 0x44 : ep2_config */
+#define USB_CR_EP2_SIZE_SHIFT (0U)
+#define USB_CR_EP2_SIZE_MASK  (0x7ff << USB_CR_EP2_SIZE_SHIFT)
+#define USB_CR_EP2_DIR_SHIFT  (11U)
+#define USB_CR_EP2_DIR_MASK   (0x3 << USB_CR_EP2_DIR_SHIFT)
+#define USB_CR_EP2_TYPE_SHIFT (13U)
+#define USB_CR_EP2_TYPE_MASK  (0x7 << USB_CR_EP2_TYPE_SHIFT)
+#define USB_CR_EP2_STALL      (1 << 16U)
+#define USB_CR_EP2_NACK       (1 << 17U)
+#define USB_CR_EP2_RDY        (1 << 18U)
+#define USB_STS_EP2_RDY       (1 << 19U)
+
+/* 0x48 : ep3_config */
+#define USB_CR_EP3_SIZE_SHIFT (0U)
+#define USB_CR_EP3_SIZE_MASK  (0x7ff << USB_CR_EP3_SIZE_SHIFT)
+#define USB_CR_EP3_DIR_SHIFT  (11U)
+#define USB_CR_EP3_DIR_MASK   (0x3 << USB_CR_EP3_DIR_SHIFT)
+#define USB_CR_EP3_TYPE_SHIFT (13U)
+#define USB_CR_EP3_TYPE_MASK  (0x7 << USB_CR_EP3_TYPE_SHIFT)
+#define USB_CR_EP3_STALL      (1 << 16U)
+#define USB_CR_EP3_NACK       (1 << 17U)
+#define USB_CR_EP3_RDY        (1 << 18U)
+#define USB_STS_EP3_RDY       (1 << 19U)
+
+/* 0x4C : ep4_config */
+#define USB_CR_EP4_SIZE_SHIFT (0U)
+#define USB_CR_EP4_SIZE_MASK  (0x7ff << USB_CR_EP4_SIZE_SHIFT)
+#define USB_CR_EP4_DIR_SHIFT  (11U)
+#define USB_CR_EP4_DIR_MASK   (0x3 << USB_CR_EP4_DIR_SHIFT)
+#define USB_CR_EP4_TYPE_SHIFT (13U)
+#define USB_CR_EP4_TYPE_MASK  (0x7 << USB_CR_EP4_TYPE_SHIFT)
+#define USB_CR_EP4_STALL      (1 << 16U)
+#define USB_CR_EP4_NACK       (1 << 17U)
+#define USB_CR_EP4_RDY        (1 << 18U)
+#define USB_STS_EP4_RDY       (1 << 19U)
+
+/* 0x50 : ep5_config */
+#define USB_CR_EP5_SIZE_SHIFT (0U)
+#define USB_CR_EP5_SIZE_MASK  (0x7ff << USB_CR_EP5_SIZE_SHIFT)
+#define USB_CR_EP5_DIR_SHIFT  (11U)
+#define USB_CR_EP5_DIR_MASK   (0x3 << USB_CR_EP5_DIR_SHIFT)
+#define USB_CR_EP5_TYPE_SHIFT (13U)
+#define USB_CR_EP5_TYPE_MASK  (0x7 << USB_CR_EP5_TYPE_SHIFT)
+#define USB_CR_EP5_STALL      (1 << 16U)
+#define USB_CR_EP5_NACK       (1 << 17U)
+#define USB_CR_EP5_RDY        (1 << 18U)
+#define USB_STS_EP5_RDY       (1 << 19U)
+
+/* 0x54 : ep6_config */
+#define USB_CR_EP6_SIZE_SHIFT (0U)
+#define USB_CR_EP6_SIZE_MASK  (0x7ff << USB_CR_EP6_SIZE_SHIFT)
+#define USB_CR_EP6_DIR_SHIFT  (11U)
+#define USB_CR_EP6_DIR_MASK   (0x3 << USB_CR_EP6_DIR_SHIFT)
+#define USB_CR_EP6_TYPE_SHIFT (13U)
+#define USB_CR_EP6_TYPE_MASK  (0x7 << USB_CR_EP6_TYPE_SHIFT)
+#define USB_CR_EP6_STALL      (1 << 16U)
+#define USB_CR_EP6_NACK       (1 << 17U)
+#define USB_CR_EP6_RDY        (1 << 18U)
+#define USB_STS_EP6_RDY       (1 << 19U)
+
+/* 0x58 : ep7_config */
+#define USB_CR_EP7_SIZE_SHIFT (0U)
+#define USB_CR_EP7_SIZE_MASK  (0x7ff << USB_CR_EP7_SIZE_SHIFT)
+#define USB_CR_EP7_DIR_SHIFT  (11U)
+#define USB_CR_EP7_DIR_MASK   (0x3 << USB_CR_EP7_DIR_SHIFT)
+#define USB_CR_EP7_TYPE_SHIFT (13U)
+#define USB_CR_EP7_TYPE_MASK  (0x7 << USB_CR_EP7_TYPE_SHIFT)
+#define USB_CR_EP7_STALL      (1 << 16U)
+#define USB_CR_EP7_NACK       (1 << 17U)
+#define USB_CR_EP7_RDY        (1 << 18U)
+#define USB_STS_EP7_RDY       (1 << 19U)
+
+/* 0x100 : ep0_fifo_config */
+#define USB_EP0_DMA_TX_EN         (1 << 0U)
+#define USB_EP0_DMA_RX_EN         (1 << 1U)
+#define USB_EP0_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP0_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP0_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP0_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP0_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP0_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x104 : ep0_fifo_status */
+#define USB_EP0_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP0_TX_FIFO_CNT_MASK  (0x7f << USB_EP0_TX_FIFO_CNT_SHIFT)
+#define USB_EP0_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP0_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP0_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP0_RX_FIFO_CNT_MASK  (0x7f << USB_EP0_RX_FIFO_CNT_SHIFT)
+#define USB_EP0_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP0_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x108 : ep0_tx_fifo_wdata */
+#define USB_EP0_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP0_TX_FIFO_WDATA_MASK  (0xff << USB_EP0_TX_FIFO_WDATA_SHIFT)
+
+/* 0x10C : ep0_rx_fifo_rdata */
+#define USB_EP0_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP0_RX_FIFO_RDATA_MASK  (0xff << USB_EP0_RX_FIFO_RDATA_SHIFT)
+
+/* 0x110 : ep1_fifo_config */
+#define USB_EP1_DMA_TX_EN         (1 << 0U)
+#define USB_EP1_DMA_RX_EN         (1 << 1U)
+#define USB_EP1_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP1_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP1_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP1_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP1_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP1_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x114 : ep1_fifo_status */
+#define USB_EP1_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP1_TX_FIFO_CNT_MASK  (0x7f << USB_EP1_TX_FIFO_CNT_SHIFT)
+#define USB_EP1_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP1_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP1_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP1_RX_FIFO_CNT_MASK  (0x7f << USB_EP1_RX_FIFO_CNT_SHIFT)
+#define USB_EP1_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP1_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x118 : ep1_tx_fifo_wdata */
+#define USB_EP1_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP1_TX_FIFO_WDATA_MASK  (0xff << USB_EP1_TX_FIFO_WDATA_SHIFT)
+
+/* 0x11C : ep1_rx_fifo_rdata */
+#define USB_EP1_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP1_RX_FIFO_RDATA_MASK  (0xff << USB_EP1_RX_FIFO_RDATA_SHIFT)
+
+/* 0x120 : ep2_fifo_config */
+#define USB_EP2_DMA_TX_EN         (1 << 0U)
+#define USB_EP2_DMA_RX_EN         (1 << 1U)
+#define USB_EP2_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP2_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP2_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP2_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP2_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP2_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x124 : ep2_fifo_status */
+#define USB_EP2_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP2_TX_FIFO_CNT_MASK  (0x7f << USB_EP2_TX_FIFO_CNT_SHIFT)
+#define USB_EP2_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP2_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP2_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP2_RX_FIFO_CNT_MASK  (0x7f << USB_EP2_RX_FIFO_CNT_SHIFT)
+#define USB_EP2_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP2_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x128 : ep2_tx_fifo_wdata */
+#define USB_EP2_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP2_TX_FIFO_WDATA_MASK  (0xff << USB_EP2_TX_FIFO_WDATA_SHIFT)
+
+/* 0x12C : ep2_rx_fifo_rdata */
+#define USB_EP2_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP2_RX_FIFO_RDATA_MASK  (0xff << USB_EP2_RX_FIFO_RDATA_SHIFT)
+
+/* 0x130 : ep3_fifo_config */
+#define USB_EP3_DMA_TX_EN         (1 << 0U)
+#define USB_EP3_DMA_RX_EN         (1 << 1U)
+#define USB_EP3_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP3_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP3_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP3_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP3_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP3_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x134 : ep3_fifo_status */
+#define USB_EP3_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP3_TX_FIFO_CNT_MASK  (0x7f << USB_EP3_TX_FIFO_CNT_SHIFT)
+#define USB_EP3_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP3_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP3_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP3_RX_FIFO_CNT_MASK  (0x7f << USB_EP3_RX_FIFO_CNT_SHIFT)
+#define USB_EP3_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP3_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x138 : ep3_tx_fifo_wdata */
+#define USB_EP3_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP3_TX_FIFO_WDATA_MASK  (0xff << USB_EP3_TX_FIFO_WDATA_SHIFT)
+
+/* 0x13C : ep3_rx_fifo_rdata */
+#define USB_EP3_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP3_RX_FIFO_RDATA_MASK  (0xff << USB_EP3_RX_FIFO_RDATA_SHIFT)
+
+/* 0x140 : ep4_fifo_config */
+#define USB_EP4_DMA_TX_EN         (1 << 0U)
+#define USB_EP4_DMA_RX_EN         (1 << 1U)
+#define USB_EP4_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP4_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP4_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP4_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP4_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP4_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x144 : ep4_fifo_status */
+#define USB_EP4_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP4_TX_FIFO_CNT_MASK  (0x7f << USB_EP4_TX_FIFO_CNT_SHIFT)
+#define USB_EP4_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP4_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP4_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP4_RX_FIFO_CNT_MASK  (0x7f << USB_EP4_RX_FIFO_CNT_SHIFT)
+#define USB_EP4_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP4_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x148 : ep4_tx_fifo_wdata */
+#define USB_EP4_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP4_TX_FIFO_WDATA_MASK  (0xff << USB_EP4_TX_FIFO_WDATA_SHIFT)
+
+/* 0x14C : ep4_rx_fifo_rdata */
+#define USB_EP4_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP4_RX_FIFO_RDATA_MASK  (0xff << USB_EP4_RX_FIFO_RDATA_SHIFT)
+
+/* 0x150 : ep5_fifo_config */
+#define USB_EP5_DMA_TX_EN         (1 << 0U)
+#define USB_EP5_DMA_RX_EN         (1 << 1U)
+#define USB_EP5_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP5_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP5_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP5_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP5_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP5_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x154 : ep5_fifo_status */
+#define USB_EP5_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP5_TX_FIFO_CNT_MASK  (0x7f << USB_EP5_TX_FIFO_CNT_SHIFT)
+#define USB_EP5_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP5_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP5_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP5_RX_FIFO_CNT_MASK  (0x7f << USB_EP5_RX_FIFO_CNT_SHIFT)
+#define USB_EP5_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP5_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x158 : ep5_tx_fifo_wdata */
+#define USB_EP5_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP5_TX_FIFO_WDATA_MASK  (0xff << USB_EP5_TX_FIFO_WDATA_SHIFT)
+
+/* 0x15C : ep5_rx_fifo_rdata */
+#define USB_EP5_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP5_RX_FIFO_RDATA_MASK  (0xff << USB_EP5_RX_FIFO_RDATA_SHIFT)
+
+/* 0x160 : ep6_fifo_config */
+#define USB_EP6_DMA_TX_EN         (1 << 0U)
+#define USB_EP6_DMA_RX_EN         (1 << 1U)
+#define USB_EP6_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP6_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP6_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP6_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP6_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP6_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x164 : ep6_fifo_status */
+#define USB_EP6_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP6_TX_FIFO_CNT_MASK  (0x7f << USB_EP6_TX_FIFO_CNT_SHIFT)
+#define USB_EP6_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP6_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP6_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP6_RX_FIFO_CNT_MASK  (0x7f << USB_EP6_RX_FIFO_CNT_SHIFT)
+#define USB_EP6_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP6_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x168 : ep6_tx_fifo_wdata */
+#define USB_EP6_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP6_TX_FIFO_WDATA_MASK  (0xff << USB_EP6_TX_FIFO_WDATA_SHIFT)
+
+/* 0x16C : ep6_rx_fifo_rdata */
+#define USB_EP6_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP6_RX_FIFO_RDATA_MASK  (0xff << USB_EP6_RX_FIFO_RDATA_SHIFT)
+
+/* 0x170 : ep7_fifo_config */
+#define USB_EP7_DMA_TX_EN         (1 << 0U)
+#define USB_EP7_DMA_RX_EN         (1 << 1U)
+#define USB_EP7_TX_FIFO_CLR       (1 << 2U)
+#define USB_EP7_RX_FIFO_CLR       (1 << 3U)
+#define USB_EP7_TX_FIFO_OVERFLOW  (1 << 4U)
+#define USB_EP7_TX_FIFO_UNDERFLOW (1 << 5U)
+#define USB_EP7_RX_FIFO_OVERFLOW  (1 << 6U)
+#define USB_EP7_RX_FIFO_UNDERFLOW (1 << 7U)
+
+/* 0x174 : ep7_fifo_status */
+#define USB_EP7_TX_FIFO_CNT_SHIFT (0U)
+#define USB_EP7_TX_FIFO_CNT_MASK  (0x7f << USB_EP7_TX_FIFO_CNT_SHIFT)
+#define USB_EP7_TX_FIFO_EMPTY     (1 << 14U)
+#define USB_EP7_TX_FIFO_FULL      (1 << 15U)
+#define USB_EP7_RX_FIFO_CNT_SHIFT (16U)
+#define USB_EP7_RX_FIFO_CNT_MASK  (0x7f << USB_EP7_RX_FIFO_CNT_SHIFT)
+#define USB_EP7_RX_FIFO_EMPTY     (1 << 30U)
+#define USB_EP7_RX_FIFO_FULL      (1 << 31U)
+
+/* 0x178 : ep7_tx_fifo_wdata */
+#define USB_EP7_TX_FIFO_WDATA_SHIFT (0U)
+#define USB_EP7_TX_FIFO_WDATA_MASK  (0xff << USB_EP7_TX_FIFO_WDATA_SHIFT)
+
+/* 0x17C : ep7_rx_fifo_rdata */
+#define USB_EP7_RX_FIFO_RDATA_SHIFT (0U)
+#define USB_EP7_RX_FIFO_RDATA_MASK  (0xff << USB_EP7_RX_FIFO_RDATA_SHIFT)
+
+/* 0x1F0 : rsvd_0 */
+
+/* 0x1F4 : rsvd_1 */
+
+/* 0x1FC : xcvr_if_config */
+#define USB_CR_XCVR_FORCE_TX_EN (1 << 0U)
+#define USB_CR_XCVR_FORCE_TX_OE (1 << 1U)
+#define USB_CR_XCVR_FORCE_TX_DP (1 << 2U)
+#define USB_CR_XCVR_FORCE_TX_DN (1 << 3U)
+#define USB_CR_XCVR_FORCE_RX_EN (1 << 4U)
+#define USB_CR_XCVR_FORCE_RX_D  (1 << 5U)
+#define USB_CR_XCVR_FORCE_RX_DP (1 << 6U)
+#define USB_CR_XCVR_FORCE_RX_DN (1 << 7U)
+#define USB_CR_XCVR_OM_RX_SEL   (1 << 8U)
+#define USB_CR_XCVR_OM_RX_D     (1 << 9U)
+#define USB_CR_XCVR_OM_RX_DP    (1 << 10U)
+#define USB_CR_XCVR_OM_RX_DN    (1 << 11U)
+#define USB_STS_VBUS_DET        (1 << 31U)
+
+#endif /* __HARDWARE_USB_V1_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v2_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v2_reg.h
new file mode 100755
index 0000000000..a126038cdc
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/include/hardware/usb_v2_reg.h
@@ -0,0 +1,734 @@
+/**
+  ******************************************************************************
+  * @file    usb_v2_reg.h
+  * @version V1.0
+  * @date    2022-08-15
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HARDWARE_USB_V2_H__
+#define __HARDWARE_USB_V2_H__
+
+/****************************************************************************
+ * Pre-processor Definitions
+****************************************************************************/
+
+/* Register offsets *********************************************************/
+
+#define USB_HCCAP_OFFSET            (0x0)   /* HCCAP */
+#define USB_HCSPARAMS_OFFSET        (0x4)   /* HCSPARAMS */
+#define USB_HCCPARAMS_OFFSET        (0x8)   /* HCCPARAMS */
+#define USBCMD_OFFSET               (0x10)  /* USBCMD */
+#define USBSTS_OFFSET               (0x14)  /* USBSTS */
+#define USBINTR_OFFSET              (0x18)  /* USBINTR */
+#define USB_FRINDEX_OFFSET          (0x1C)  /* FRINDEX */
+#define USB_PERIODICLISTBASE_OFFSET (0x24)  /* PERIODICLISTBASE */
+#define USB_ASYNCLISTADDR_OFFSET    (0x28)  /* ASYNCLISTADDR */
+#define USB_PORTSC_OFFSET           (0x30)  /* PORTSC */
+#define USB_HCMISC_OFFSET           (0x40)  /* HCMISC */
+#define USB_FS_EOF_OFFSET           (0x44)  /* FS_EOF */
+#define USB_HS_EOF_OFFSET           (0x48)  /* HS_EOF */
+#define USB_OTG_CSR_OFFSET          (0x80)  /* OTG_CSR */
+#define USB_OTG_ISR_OFFSET          (0x84)  /* OTG_ISR */
+#define USB_OTG_IER_OFFSET          (0x88)  /* OTG_IER */
+#define USB_GLB_ISR_OFFSET          (0xC0)  /* GLB_ISR */
+#define USB_GLB_INT_OFFSET          (0xC4)  /* GLB_INT */
+#define USB_REVISION_OFFSET         (0xE0)  /* REVISION */
+#define USB_FEATURE_OFFSET          (0xE4)  /* FEATURE */
+#define USB_AXI_CR_OFFSET           (0xE8)  /* AXI_CR */
+#define USB_DEV_CTL_OFFSET          (0x100) /* DEV_CTL */
+#define USB_DEV_ADR_OFFSET          (0x104) /* DEV_ADR */
+#define USB_DEV_TST_OFFSET          (0x108) /* DEV_TST */
+#define USB_DEV_SFN_OFFSET          (0x10C) /* DEV_SFN */
+#define USB_DEV_SMT_OFFSET          (0x110) /* DEV_SMT */
+#define USB_PHY_TST_OFFSET          (0x114) /* PHY_TST */
+#define USB_DEV_VCTL_OFFSET         (0x118) /* DEV_VCTL */
+#define USB_DEV_CXCFG_OFFSET        (0x11C) /* DEV_CXCFG */
+#define USB_DEV_CXCFE_OFFSET        (0x120) /* DEV_CXCFE */
+#define USB_DEV_ICR_OFFSET          (0x124) /* DEV_ICR */
+#define USB_DEV_MIGR_OFFSET         (0x130) /* DEV_MIGR */
+#define USB_DEV_MISG0_OFFSET        (0x134) /* DEV_MISG0 */
+#define USB_DEV_MISG1_OFFSET        (0x138) /* DEV_MISG1 */
+#define USB_DEV_MISG2_OFFSET        (0x13C) /* DEV_MISG2 */
+#define USB_DEV_IGR_OFFSET          (0x140) /* DEV_IGR */
+#define USB_DEV_ISG0_OFFSET         (0x144) /* DEV_ISG0 */
+#define USB_DEV_ISG1_OFFSET         (0x148) /* DEV_ISG1 */
+#define USB_DEV_ISG2_OFFSET         (0x14C) /* DEV_ISG2 */
+#define USB_DEV_RXZ_OFFSET          (0x150) /* DEV_RXZ */
+#define USB_DEV_TXZ_OFFSET          (0x154) /* DEV_TXZ */
+#define USB_DEV_ISE_OFFSET          (0x158) /* DEV_ISE */
+#define USB_DEV_INMPS1_OFFSET       (0x160) /* DEV_INMPS1 */
+#define USB_DEV_INMPS2_OFFSET       (0x164) /* DEV_INMPS2 */
+#define USB_DEV_INMPS3_OFFSET       (0x168) /* DEV_INMPS3 */
+#define USB_DEV_INMPS4_OFFSET       (0x16C) /* DEV_INMPS4 */
+#define USB_DEV_INMPS5_OFFSET       (0x170) /* DEV_INMPS5 */
+#define USB_DEV_INMPS6_OFFSET       (0x174) /* DEV_INMPS6 */
+#define USB_DEV_INMPS7_OFFSET       (0x178) /* DEV_INMPS7 */
+#define USB_DEV_INMPS8_OFFSET       (0x17C) /* DEV_INMPS8 */
+#define USB_DEV_OUTMPS1_OFFSET      (0x180) /* DEV_OUTMPS1 */
+#define USB_DEV_OUTMPS2_OFFSET      (0x184) /* DEV_OUTMPS2 */
+#define USB_DEV_OUTMPS3_OFFSET      (0x188) /* DEV_OUTMPS3 */
+#define USB_DEV_OUTMPS4_OFFSET      (0x18C) /* DEV_OUTMPS4 */
+#define USB_DEV_OUTMPS5_OFFSET      (0x190) /* DEV_OUTMPS5 */
+#define USB_DEV_OUTMPS6_OFFSET      (0x194) /* DEV_OUTMPS6 */
+#define USB_DEV_OUTMPS7_OFFSET      (0x198) /* DEV_OUTMPS7 */
+#define USB_DEV_OUTMPS8_OFFSET      (0x19C) /* DEV_OUTMPS8 */
+#define USB_DEV_EPMAP0_OFFSET       (0x1A0) /* DEV_EPMAP0 */
+#define USB_DEV_EPMAP1_OFFSET       (0x1A4) /* DEV_EPMAP1 */
+#define USB_DEV_FMAP_OFFSET         (0x1A8) /* DEV_FMAP */
+#define USB_DEV_FCFG_OFFSET         (0x1AC) /* DEV_FCFG */
+#define USB_DEV_FIBC0_OFFSET        (0x1B0) /* DEV_FIBC0 */
+#define USB_DEV_FIBC1_OFFSET        (0x1B4) /* DEV_FIBC1 */
+#define USB_DEV_FIBC2_OFFSET        (0x1B8) /* DEV_FIBC2 */
+#define USB_DEV_FIBC3_OFFSET        (0x1BC) /* DEV_FIBC3 */
+#define USB_DMA_TFN_OFFSET          (0x1C0) /* DMA_TFN */
+#define USB_DMA_CPS0_OFFSET         (0x1C4) /* DMA_CPS0 */
+#define USB_DMA_CPS1_OFFSET         (0x1C8) /* DMA_CPS1 */
+#define USB_DMA_CPS2_OFFSET         (0x1CC) /* DMA_CPS2 */
+#define USB_DMA_CPS3_OFFSET         (0x1D0) /* DMA_CPS3 */
+#define USB_DMA_CPS4_OFFSET         (0x1D4) /* DMA_CPS4 */
+#define USB_DEV_FMAP2_OFFSET        (0x1D8) /* DEV_FMAP2 */
+#define USB_DEV_FCFG2_OFFSET        (0x1DC) /* DEV_FCFG2 */
+#define USB_DEV_FMAP3_OFFSET        (0x1E0) /* DEV_FMAP3 */
+#define USB_DEV_FCFG3_OFFSET        (0x1E4) /* DEV_FCFG3 */
+#define USB_DEV_FMAP4_OFFSET        (0x1E8) /* DEV_FMAP4 */
+#define USB_DEV_FCFG4_OFFSET        (0x1EC) /* DEV_FCFG4 */
+#define USB_DEV_FIBC4_OFFSET        (0x1F0) /* DEV_FIBC4 */
+#define USB_DEV_FIBC5_OFFSET        (0x1F4) /* DEV_FIBC5 */
+#define USB_DEV_FIBC6_OFFSET        (0x1F8) /* DEV_FIBC6 */
+#define USB_DEV_FIBC7_OFFSET        (0x1FC) /* DEV_FIBC7 */
+#define USB_VDMA_CXFPS1_OFFSET      (0x300) /* VDMA_CXFPS1 */
+#define USB_VDMA_CXFPS2_OFFSET      (0x304) /* VDMA_CXFPS2 */
+#define USB_VDMA_F0PS1_OFFSET       (0x308) /* VDMA_F0PS1 */
+#define USB_VDMA_F0PS2_OFFSET       (0x30C) /* VDMA_F0PS2 */
+#define USB_VDMA_F1PS1_OFFSET       (0x310) /* VDMA_F1PS1 */
+#define USB_VDMA_F1PS2_OFFSET       (0x314) /* VDMA_F1PS2 */
+#define USB_VDMA_F2PS1_OFFSET       (0x318) /* VDMA_F2PS1 */
+#define USB_VDMA_F2PS2_OFFSET       (0x31C) /* VDMA_F2PS2 */
+#define USB_VDMA_F3PS1_OFFSET       (0x320) /* VDMA_F3PS1 */
+#define USB_VDMA_F3PS2_OFFSET       (0x324) /* VDMA_F3PS2 */
+#define USB_DEV_ISG3_OFFSET         (0x328) /* DEV_ISG3 */
+#define USB_DEV_MISG3_OFFSET        (0x32C) /* DEV_MISG3 */
+#define USB_VDMA_CTRL_OFFSET        (0x330) /* VDMA_CTRL */
+#define USB_LPM_CAP_OFFSET          (0x334) /* LPM_CAP */
+#define USB_DEV_ISG4_OFFSET         (0x338) /* DEV_ISG4 */
+#define USB_DEV_MISG4_OFFSET        (0x33C) /* DEV_MISG4 */
+#define USB_VDMA_FNPS1_OFFSET       (0x350) /* VDMA_FNPS1 */
+#define USB_VDMA_FNPS2_OFFSET       (0x354) /* VDMA_FNPS2 */
+
+/* Register Bitfield definitions *****************************************************/
+
+/* 0x0 : HCCAP */
+#define USB_CAPLENGTH_SHIFT  (0U)
+#define USB_CAPLENGTH_MASK   (0xff << USB_CAPLENGTH_SHIFT)
+#define USB_HCIVERSION_SHIFT (16U)
+#define USB_HCIVERSION_MASK  (0xffff << USB_HCIVERSION_SHIFT)
+
+/* 0x4 : HCSPARAMS */
+#define USB_N_PORTS_SHIFT (0U)
+#define USB_N_PORTS_MASK  (0xf << USB_N_PORTS_SHIFT)
+
+/* 0x8 : HCCPARAMS */
+#define USB_PROG_FR_LIST_FLAG (1 << 1U)
+#define USB_ASYN_SCH_PARK_CAP (1 << 2U)
+
+/* 0x10 : USBCMD */
+#define USB_RS                (1 << 0U)
+#define USB_HC_RESET          (1 << 1U)
+#define USB_FRL_SIZE_SHIFT    (2U)
+#define USB_FRL_SIZE_MASK     (0x3 << USB_FRL_SIZE_SHIFT)
+#define USB_PSCH_EN           (1 << 4U)
+#define USB_ASCH_EN           (1 << 5U)
+#define USB_INT_OAAD          (1 << 6U)
+#define USB_ASYN_PK_CNT_SHIFT (8U)
+#define USB_ASYN_PK_CNT_MASK  (0x3 << USB_ASYN_PK_CNT_SHIFT)
+#define USB_ASYN_PK_EN        (1 << 11U)
+#define USB_INT_THRC_SHIFT    (16U)
+#define USB_INT_THRC_MASK     (0xff << USB_INT_THRC_SHIFT)
+
+/* 0x14 : USBSTS */
+#define USB_INT         (1 << 0U)
+#define USBERR_INT      (1 << 1U)
+#define USB_PO_CHG_DET  (1 << 2U)
+#define USB_FRL_ROL     (1 << 3U)
+#define USB_H_SYSERR    (1 << 4U)
+#define USB_INT_OAA     (1 << 5U)
+#define USB_HCHALTED    (1 << 12U)
+#define USB_RECLAMATION (1 << 13U)
+#define USB_PSCH_STS    (1 << 14U)
+#define USB_ASCH_STS    (1 << 15U)
+
+/* 0x18 : USBINTR */
+#define USB_INT_EN        (1 << 0U)
+#define USBERR_INT_EN     (1 << 1U)
+#define USB_PO_CHG_INT_EN (1 << 2U)
+#define USB_FRL_ROL_EN    (1 << 3U)
+#define USB_H_SYSERR_EN   (1 << 4U)
+#define USB_INT_OAA_EN    (1 << 5U)
+
+/* 0x1C : FRINDEX */
+#define USB_FRINDEX_SHIFT (0U)
+#define USB_FRINDEX_MASK  (0x3fff << USB_FRINDEX_SHIFT)
+
+/* 0x24 : PERIODICLISTBASE */
+#define USB_PERI_BASADR_SHIFT (12U)
+#define USB_PERI_BASADR_MASK  (0xfffff << USB_PERI_BASADR_SHIFT)
+
+/* 0x28 : ASYNCLISTADDR */
+#define USB_ASYNC_LADR_SHIFT (5U)
+#define USB_ASYNC_LADR_MASK  (0x7fffff << USB_ASYNC_LADR_SHIFT)
+
+/* 0x30 : PORTSC */
+#define USB_CONN_STS        (1 << 0U)
+#define USB_CONN_CHG        (1 << 1U)
+#define USB_PO_EN           (1 << 2U)
+#define USB_PO_EN_CHG       (1 << 3U)
+#define USB_F_PO_RESM       (1 << 6U)
+#define USB_PO_SUSP         (1 << 7U)
+#define USB_PO_RESET        (1 << 8U)
+#define USB_LINE_STS_SHIFT  (10U)
+#define USB_LINE_STS_MASK   (0x3 << USB_LINE_STS_SHIFT)
+#define USB_PORT_TEST_SHIFT (16U)
+#define USB_PORT_TEST_MASK  (0xf << USB_PORT_TEST_SHIFT)
+#define USB_HC_TST_PKDONE   (1 << 20U)
+
+/* 0x40 : HCMISC */
+#define USB_ASYN_SCH_SLPT_SHIFT (0U)
+#define USB_ASYN_SCH_SLPT_MASK  (0x3 << USB_ASYN_SCH_SLPT_SHIFT)
+#define USB_EOF1_TIME_SHIFT     (2U)
+#define USB_EOF1_TIME_MASK      (0x3 << USB_EOF1_TIME_SHIFT)
+#define USB_EOF2_TIME_SHIFT     (4U)
+#define USB_EOF2_TIME_MASK      (0x3 << USB_EOF2_TIME_SHIFT)
+#define USB_HOSTPHY_SUSPEND     (1 << 6U)
+#define USB_HC_WKP_DET_EN       (1 << 8U)
+#define USB_HC_CONN_DET_EN      (1 << 9U)
+
+/* 0x44 : FS_EOF */
+#define USB_FS_EOF1_TIME_SHIFT       (0U)
+#define USB_FS_EOF1_TIME_MASK        (0xfff << USB_FS_EOF1_TIME_SHIFT)
+#define USB_FS_EOF1_TIME_125US_SHIFT (12U)
+#define USB_FS_EOF1_TIME_125US_MASK  (0x7 << USB_FS_EOF1_TIME_125US_SHIFT)
+#define USB_ITDDMASM_SHIFT           (16U)
+#define USB_ITDDMASM_MASK            (0xf << USB_ITDDMASM_SHIFT)
+#define USB_ITDTRAVSM_SHIFT          (20U)
+#define USB_ITDTRAVSM_MASK           (0x3 << USB_ITDTRAVSM_SHIFT)
+#define USB_DMADMSM_SHIFT            (22U)
+#define USB_DMADMSM_MASK             (0xf << USB_DMADMSM_SHIFT)
+#define USB_QHTTRSM_SHIFT            (26U)
+#define USB_QHTTRSM_MASK             (0x7 << USB_QHTTRSM_SHIFT)
+#define USB_QHTRAVSM_SHIFT           (29U)
+#define USB_QHTRAVSM_MASK            (0x7 << USB_QHTRAVSM_SHIFT)
+
+/* 0x48 : HS_EOF */
+#define USB_HS_EOF1_TIME_SHIFT       (0U)
+#define USB_HS_EOF1_TIME_MASK        (0xfff << USB_HS_EOF1_TIME_SHIFT)
+#define USB_FS_EOF1_TIME_125US_SHIFT (12U)
+#define USB_FS_EOF1_TIME_125US_MASK  (0x7 << USB_FS_EOF1_TIME_125US_SHIFT)
+#define USB_SITDDMASM_SHIFT          (16U)
+#define USB_SITDDMASM_MASK           (0xf << USB_SITDDMASM_SHIFT)
+#define USB_SITDTRAVSM_SHIFT         (20U)
+#define USB_SITDTRAVSM_MASK          (0x3 << USB_SITDTRAVSM_SHIFT)
+
+/* 0x80 : OTG_CSR */
+#define USB_B_BUS_REQ             (1 << 0U)
+#define USB_B_HNP_EN              (1 << 1U)
+#define USB_B_DSCHRG_VBUS         (1 << 2U)
+#define USB_A_BUS_REQ_HOV         (1 << 4U)
+#define USB_A_BUS_DROP_HOV        (1 << 5U)
+#define USB_A_SET_B_HNP_EN        (1 << 6U)
+#define USB_A_SRP_DET_EN          (1 << 7U)
+#define USB_A_SRP_RESP_TYP        (1 << 8U)
+#define USB_ID_FLT_SEL            (1 << 9U)
+#define USB_VBUS_FLT_SEL_HOV_POV  (1 << 10U)
+#define USB_HDISCON_FLT_SEL_HOV   (1 << 11U)
+#define USB_IDPULUP_HOV_POV       (1 << 13U)
+#define USB_B_SESS_END_POV        (1 << 16U)
+#define USB_B_SESS_VLD_POV        (1 << 17U)
+#define USB_A_SESS_VLD            (1 << 18U)
+#define USB_VBUS_VLD_HOV          (1 << 19U)
+#define USB_CROLE_HOV_POV         (1 << 20U)
+#define USB_ID_HOV_POV            (1 << 21U)
+#define USB_SPD_TYP_HOV_POV_SHIFT (22U)
+#define USB_SPD_TYP_HOV_POV_MASK  (0x3 << USB_SPD_TYP_HOV_POV_SHIFT)
+
+/* 0x84 : OTG_ISR */
+#define USB_B_SRP_DN           (1 << 0U)
+#define USB_A_SRP_DET          (1 << 4U)
+#define USB_A_VBUS_ERR_HOV     (1 << 5U)
+#define USB_B_SESS_END_INT_POV (1 << 6U)
+#define USB_RLCHG              (1 << 8U)
+#define USB_IDCHG              (1 << 9U)
+#define USB_OVC_HOV            (1 << 10U)
+#define USB_A_WAIT_CON_HOV     (1 << 11U)
+#define USB_APLGRMV            (1 << 12U)
+
+/* 0x88 : OTG_IER */
+#define USB_B_SRP_DN_EN       (1 << 0U)
+#define USB_A_SRP_DET_INT_EN  (1 << 4U)
+#define USB_A_VBUS_ERR_EN_HOV (1 << 5U)
+#define USB_B_SESS_END_EN_POV (1 << 6U)
+#define USB_RLCHG_EN          (1 << 8U)
+#define USB_IDCHG_EN          (1 << 9U)
+#define USB_OVC_EN_HOV        (1 << 10U)
+#define USB_A_WAIT_CON_EN_HOV (1 << 11U)
+#define USB_APLGRMV_EN        (1 << 12U)
+
+/* 0xC0 : GLB_ISR */
+#define USB_DEV_INT (1 << 0U)
+#define USB_OTG_INT (1 << 1U)
+#define USB_HC_INT  (1 << 2U)
+
+/* 0xC4 : GLB_INT */
+#define USB_MDEV_INT (1 << 0U)
+#define USB_MOTG_INT (1 << 1U)
+#define USB_MHC_INT  (1 << 2U)
+
+/* 0xE0 : REVISION */
+#define USB_REVISION_SHIFT (0U)
+#define USB_REVISION_MASK  (0xffffffff << USB_REVISION_SHIFT)
+
+/* 0xE4 : FEATURE */
+#define USB_DMABUFSIZE_SHIFT (0U)
+#define USB_DMABUFSIZE_MASK  (0x1f << USB_DMABUFSIZE_SHIFT)
+#define USB_FIFO_NUM_SHIFT   (5U)
+#define USB_FIFO_NUM_MASK    (0x1f << USB_FIFO_NUM_SHIFT)
+#define USB_EP_NUM_SHIFT     (10U)
+#define USB_EP_NUM_MASK      (0x1f << USB_EP_NUM_SHIFT)
+#define USB_DEV_ONLY         (1 << 15U)
+#define USB_HOST_ONLY        (1 << 16U)
+
+/* 0xE8 : AXI_CR */
+#define USB_AXI_SGLBST (1 << 0U)
+
+/* 0x100 : DEV_CTL */
+#define USB_CAP_RMWAKUP        (1 << 0U)
+#define USB_HALF_SPEED_HOV     (1 << 1U)
+#define USB_GLINT_EN_HOV       (1 << 2U)
+#define USB_GOSUSP             (1 << 3U)
+#define USB_SFRST_HOV          (1 << 4U)
+#define USB_CHIP_EN_HOV        (1 << 5U)
+#define USB_HS_EN_HOV          (1 << 6U)
+#define USB_SYSBUS_WIDTH_HOV   (1 << 7U)
+#define USB_FORCE_FS           (1 << 9U)
+#define USB_IDLE_DEGLITCH_HOV  (1 << 10U)
+#define USB_LPM_BESL_MAX_SHIFT (12U)
+#define USB_LPM_BESL_MAX_MASK  (0xf << USB_LPM_BESL_MAX_SHIFT)
+#define USB_LPM_BESL_MIN_SHIFT (16U)
+#define USB_LPM_BESL_MIN_MASK  (0xf << USB_LPM_BESL_MIN_SHIFT)
+#define USB_LPM_BESL_SHIFT     (20U)
+#define USB_LPM_BESL_MASK      (0xf << USB_LPM_BESL_SHIFT)
+#define USB_LPM_EN             (1 << 25U)
+#define USB_LPM_ACCEPT         (1 << 26U)
+
+/* 0x104 : DEV_ADR */
+#define USB_DEVADR_SHIFT (0U)
+#define USB_DEVADR_MASK  (0x7f << USB_DEVADR_SHIFT)
+#define USB_AFT_CONF     (1 << 7U)
+
+/* 0x108 : DEV_TST */
+#define USB_TST_CLRFF_HOV   (1 << 0U)
+#define USB_TST_LPCX        (1 << 1U)
+#define USB_TST_CLREA       (1 << 2U)
+#define USB_TST_DISTO_HOV   (1 << 4U)
+#define USB_TST_MOD_HOV     (1 << 5U)
+#define USB_DISGENSOF       (1 << 6U)
+#define USB_TST_MOD_TYP_HOV (1 << 7U)
+
+/* 0x10C : DEV_SFN */
+#define USB_SOFN_SHIFT  (0U)
+#define USB_SOFN_MASK   (0x7ff << USB_SOFN_SHIFT)
+#define USB_USOFN_SHIFT (11U)
+#define USB_USOFN_MASK  (0x7 << USB_USOFN_SHIFT)
+
+/* 0x110 : DEV_SMT */
+#define USB_SOFMT_SHIFT (0U)
+#define USB_SOFMT_MASK  (0xffff << USB_SOFMT_SHIFT)
+
+/* 0x114 : PHY_TST */
+#define USB_UNPLUG     (1 << 0U)
+#define USB_TST_JSTA   (1 << 1U)
+#define USB_TST_KSTA   (1 << 2U)
+#define USB_TST_SE0NAK (1 << 3U)
+#define USB_TST_PKT    (1 << 4U)
+
+/* 0x11C : DEV_CXCFG */
+#define USB_VSTA_HOV_SHIFT (0U)
+#define USB_VSTA_HOV_MASK  (0xff << USB_VSTA_HOV_SHIFT)
+
+/* 0x120 : DEV_CXCFE */
+#define USB_CX_DONE    (1 << 0U)
+#define USB_TST_PKDONE (1 << 1U)
+#define USB_CX_STL     (1 << 2U)
+#define USB_CX_CLR     (1 << 3U)
+#define USB_CX_FUL     (1 << 4U)
+#define USB_CX_EMP     (1 << 5U)
+#define USB_F0_EMP     (1 << 8U)
+#define USB_F1_EMP     (1 << 9U)
+#define USB_F2_EMP     (1 << 10U)
+#define USB_F3_EMP     (1 << 11U)
+
+/* 0x124 : DEV_ICR */
+#define USB_IDLE_CNT_SHIFT (0U)
+#define USB_IDLE_CNT_MASK  (0x7 << USB_IDLE_CNT_SHIFT)
+
+/* 0x130 : DEV_MIGR */
+#define USB_MINT_G0 (1 << 0U)
+#define USB_MINT_G1 (1 << 1U)
+#define USB_MINT_G2 (1 << 2U)
+#define USB_MINT_G3 (1 << 3U)
+#define USB_MINT_G4 (1 << 4U)
+
+/* 0x134 : DEV_MISG0 */
+#define USB_MCX_SETUP_INT    (1 << 0U)
+#define USB_MCX_IN_INT       (1 << 1U)
+#define USB_MCX_OUT_INT      (1 << 2U)
+#define USB_MCX_COMFAIL_INT  (1 << 4U)
+#define USB_MCX_COMABORT_INT (1 << 5U)
+
+/* 0x138 : DEV_MISG1 */
+#define USB_MF0_OUT_INT (1 << 0U)
+#define USB_MF0_SPK_INT (1 << 1U)
+#define USB_MF1_OUT_INT (1 << 2U)
+#define USB_MF1_SPK_INT (1 << 3U)
+#define USB_MF2_OUT_INT (1 << 4U)
+#define USB_MF2_SPK_INT (1 << 5U)
+#define USB_MF3_OUT_INT (1 << 6U)
+#define USB_MF3_SPK_INT (1 << 7U)
+#define USB_MF0_IN_INT  (1 << 16U)
+#define USB_MF1_IN_INT  (1 << 17U)
+#define USB_MF2_IN_INT  (1 << 18U)
+#define USB_MF3_IN_INT  (1 << 19U)
+
+/* 0x13C : DEV_MISG2 */
+#define USB_MUSBRST_INT        (1 << 0U)
+#define USB_MSUSP_INT          (1 << 1U)
+#define USB_MRESM_INT          (1 << 2U)
+#define USB_MSEQ_ERR_INT       (1 << 3U)
+#define USB_MSEQ_ABORT_INT     (1 << 4U)
+#define USB_MTX0BYTE_INT       (1 << 5U)
+#define USB_MRX0BYTE_INT       (1 << 6U)
+#define USB_MDMA_CMPLT_HOV     (1 << 7U)
+#define USB_MDMA_ERROR_HOV     (1 << 8U)
+#define USB_MDEV_IDLE_HOV      (1 << 9U)
+#define USB_MDEV_WAKEUP_BYVBUS (1 << 10U)
+
+/* 0x140 : DEV_IGR */
+#define USB_INT_G0 (1 << 0U)
+#define USB_INT_G1 (1 << 1U)
+#define USB_INT_G2 (1 << 2U)
+#define USB_INT_G3 (1 << 3U)
+#define USB_INT_G4 (1 << 4U)
+
+/* 0x144 : DEV_ISG0 */
+#define USB_CX_SETUP_INT   (1 << 0U)
+#define USB_CX_IN_INT      (1 << 1U)
+#define USB_CX_OUT_INT     (1 << 2U)
+#define USB_CX_COMFAIL_INT (1 << 4U)
+#define USB_CX_COMABT_INT  (1 << 5U)
+
+/* 0x148 : DEV_ISG1 */
+#define USB_F0_OUT_INT (1 << 0U)
+#define USB_F0_SPK_INT (1 << 1U)
+#define USB_F1_OUT_INT (1 << 2U)
+#define USB_F1_SPK_INT (1 << 3U)
+#define USB_F2_OUT_INT (1 << 4U)
+#define USB_F2_SPK_INT (1 << 5U)
+#define USB_F3_OUT_INT (1 << 6U)
+#define USB_F3_SPK_INT (1 << 7U)
+#define USB_F0_IN_INT  (1 << 16U)
+#define USB_F1_IN_INT  (1 << 17U)
+#define USB_F2_IN_INT  (1 << 18U)
+#define USB_F3_IN_INT  (1 << 19U)
+
+/* 0x14C : DEV_ISG2 */
+#define USBRST_INT            (1 << 0U)
+#define USB_SUSP_INT          (1 << 1U)
+#define USB_RESM_INT          (1 << 2U)
+#define USB_ISO_SEQ_ERR_INT   (1 << 3U)
+#define USB_ISO_SEQ_ABORT_INT (1 << 4U)
+#define USB_TX0BYTE_INT       (1 << 5U)
+#define USB_RX0BYTE_INT       (1 << 6U)
+#define USB_DMA_CMPLT_HOV     (1 << 7U)
+#define USB_DMA_ERROR_HOV     (1 << 8U)
+#define USB_DEV_IDLE_HOV      (1 << 9U)
+#define USB_DEV_WAKEUP_BYVBUS (1 << 10U)
+
+/* 0x150 : DEV_RXZ */
+#define USB_RX0BYTE_EP1 (1 << 0U)
+#define USB_RX0BYTE_EP2 (1 << 1U)
+#define USB_RX0BYTE_EP3 (1 << 2U)
+#define USB_RX0BYTE_EP4 (1 << 3U)
+
+/* 0x154 : DEV_TXZ */
+#define USB_TX0BYTE_EP1 (1 << 0U)
+#define USB_TX0BYTE_EP2 (1 << 1U)
+#define USB_TX0BYTE_EP3 (1 << 2U)
+#define USB_TX0BYTE_EP4 (1 << 3U)
+
+/* 0x158 : DEV_ISE */
+#define USB_ISO_ABT_ERR_EP1 (1 << 0U)
+#define USB_ISO_ABT_ERR_EP2 (1 << 1U)
+#define USB_ISO_ABT_ERR_EP3 (1 << 2U)
+#define USB_ISO_ABT_ERR_EP4 (1 << 3U)
+#define USB_ISO_SEQ_ERR_EP1 (1 << 16U)
+#define USB_ISO_SEQ_ERR_EP2 (1 << 17U)
+#define USB_ISO_SEQ_ERR_EP3 (1 << 18U)
+#define USB_ISO_SEQ_ERR_EP4 (1 << 19U)
+
+/* 0x160 : DEV_INMPS1 */
+#define USB_MAXPS_IEP1_SHIFT      (0U)
+#define USB_MAXPS_IEP1_MASK       (0x7ff << USB_MAXPS_IEP1_SHIFT)
+#define USB_STL_IEP1              (1 << 11U)
+#define USB_RSTG_IEP1             (1 << 12U)
+#define USB_TX_NUM_HBW_IEP1_SHIFT (13U)
+#define USB_TX_NUM_HBW_IEP1_MASK  (0x3 << USB_TX_NUM_HBW_IEP1_SHIFT)
+#define USB_TX0BYTE_IEP1          (1 << 15U)
+
+/* 0x164 : DEV_INMPS2 */
+/* 0x168 : DEV_INMPS3 */
+/* 0x16C : DEV_INMPS4 */
+/* 0x170 : DEV_INMPS5 */
+/* 0x174 : DEV_INMPS6 */
+/* 0x178 : DEV_INMPS7 */
+/* 0x17C : DEV_INMPS8 */
+
+/* 0x180 : DEV_OUTMPS1 */
+#define USB_MAXPS_OEP1_SHIFT (0U)
+#define USB_MAXPS_OEP1_MASK  (0x7ff << USB_MAXPS_OEP1_SHIFT)
+#define USB_STL_OEP1         (1 << 11U)
+#define USB_RSTG_OEP1        (1 << 12U)
+
+/* 0x184 : DEV_OUTMPS2 */
+/* 0x188 : DEV_OUTMPS3 */
+/* 0x18C : DEV_OUTMPS4 */
+/* 0x190 : DEV_OUTMPS5 */
+/* 0x194 : DEV_OUTMPS6 */
+/* 0x198 : DEV_OUTMPS7 */
+/* 0x19C : DEV_OUTMPS8 */
+
+/* 0x1A0 : DEV_EPMAP0 */
+#define USB_FNO_IEP1_SHIFT (0U)
+#define USB_FNO_IEP1_MASK  (0xf << USB_FNO_IEP1_SHIFT)
+#define USB_FNO_OEP1_SHIFT (4U)
+#define USB_FNO_OEP1_MASK  (0xf << USB_FNO_OEP1_SHIFT)
+#define USB_FNO_IEP2_SHIFT (8U)
+#define USB_FNO_IEP2_MASK  (0xf << USB_FNO_IEP2_SHIFT)
+#define USB_FNO_OEP2_SHIFT (12U)
+#define USB_FNO_OEP2_MASK  (0xf << USB_FNO_OEP2_SHIFT)
+#define USB_FNO_IEP3_SHIFT (16U)
+#define USB_FNO_IEP3_MASK  (0xf << USB_FNO_IEP3_SHIFT)
+#define USB_FNO_OEP3_SHIFT (20U)
+#define USB_FNO_OEP3_MASK  (0xf << USB_FNO_OEP3_SHIFT)
+#define USB_FNO_IEP4_SHIFT (24U)
+#define USB_FNO_IEP4_MASK  (0xf << USB_FNO_IEP4_SHIFT)
+#define USB_FNO_OEP4_SHIFT (28U)
+#define USB_FNO_OEP4_MASK  (0xf << USB_FNO_OEP4_SHIFT)
+
+/* 0x1A4 : DEV_EPMAP1 */
+
+/* 0x1A8 : DEV_FMAP */
+#define USB_EPNO_FIFO0_SHIFT (0U)
+#define USB_EPNO_FIFO0_MASK  (0xf << USB_EPNO_FIFO0_SHIFT)
+#define USB_DIR_FIFO0_SHIFT  (4U)
+#define USB_DIR_FIFO0_MASK   (0x3 << USB_DIR_FIFO0_SHIFT)
+#define USB_EPNO_FIFO1_SHIFT (8U)
+#define USB_EPNO_FIFO1_MASK  (0xf << USB_EPNO_FIFO1_SHIFT)
+#define USB_DIR_FIFO1_SHIFT  (12U)
+#define USB_DIR_FIFO1_MASK   (0x3 << USB_DIR_FIFO1_SHIFT)
+#define USB_EPNO_FIFO2_SHIFT (16U)
+#define USB_EPNO_FIFO2_MASK  (0xf << USB_EPNO_FIFO2_SHIFT)
+#define USB_DIR_FIFO2_SHIFT  (20U)
+#define USB_DIR_FIFO2_MASK   (0x3 << USB_DIR_FIFO2_SHIFT)
+#define USB_EPNO_FIFO3_SHIFT (24U)
+#define USB_EPNO_FIFO3_MASK  (0xf << USB_EPNO_FIFO3_SHIFT)
+#define USB_DIR_FIFO3_SHIFT  (28U)
+#define USB_DIR_FIFO3_MASK   (0x3 << USB_DIR_FIFO3_SHIFT)
+
+/* 0x1AC : DEV_FCFG */
+#define USB_BLK_TYP_F0_SHIFT (0U)
+#define USB_BLK_TYP_F0_MASK  (0x3 << USB_BLK_TYP_F0_SHIFT)
+#define USB_BLKNO_F0_SHIFT   (2U)
+#define USB_BLKNO_F0_MASK    (0x3 << USB_BLKNO_F0_SHIFT)
+#define USB_BLKSZ_F0         (1 << 4U)
+#define USB_EN_F0            (1 << 5U)
+#define USB_BLK_TYP_F1_SHIFT (8U)
+#define USB_BLK_TYP_F1_MASK  (0x3 << USB_BLK_TYP_F1_SHIFT)
+#define USB_BLKNO_F1_SHIFT   (10U)
+#define USB_BLKNO_F1_MASK    (0x3 << USB_BLKNO_F1_SHIFT)
+#define USB_BLKSZ_F1         (1 << 12U)
+#define USB_EN_F1            (1 << 13U)
+#define USB_BLK_TYP_F2_SHIFT (16U)
+#define USB_BLK_TYP_F2_MASK  (0x3 << USB_BLK_TYP_F2_SHIFT)
+#define USB_BLKNO_F2_SHIFT   (18U)
+#define USB_BLKNO_F2_MASK    (0x3 << USB_BLKNO_F2_SHIFT)
+#define USB_BLKSZ_F2         (1 << 20U)
+#define USB_EN_F2            (1 << 21U)
+#define USB_BLK_TYP_F3_SHIFT (24U)
+#define USB_BLK_TYP_F3_MASK  (0x3 << USB_BLK_TYP_F3_SHIFT)
+#define USB_BLKNO_F3_SHIFT   (26U)
+#define USB_BLKNO_F3_MASK    (0x3 << USB_BLKNO_F3_SHIFT)
+#define USB_BLKSZ_F3         (1 << 28U)
+#define USB_EN_F3            (1 << 29U)
+
+/* 0x1B0 : DEV_FIBC0 */
+#define USB_BC_F0_SHIFT (0U)
+#define USB_BC_F0_MASK  (0x7ff << USB_BC_F0_SHIFT)
+#define USB_FFRST0_HOV  (1 << 12U)
+
+/* 0x1B4 : DEV_FIBC1 */
+/* 0x1B8 : DEV_FIBC2 */
+/* 0x1BC : DEV_FIBC3 */
+
+/* 0x1C0 : DMA_TFN */
+#define USB_ACC_F0_HOV  (1 << 0U)
+#define USB_ACC_F1_HOV  (1 << 1U)
+#define USB_ACC_F2_HOV  (1 << 2U)
+#define USB_ACC_F3_HOV  (1 << 3U)
+#define USB_ACC_CXF_HOV (1 << 4U)
+
+/* 0x1C4 : DMA_CPS0 */
+#define USB_AWCHACHE_HOV_SHIFT (0U)
+#define USB_AWCHACHE_HOV_MASK  (0xf << USB_AWCHACHE_HOV_SHIFT)
+#define USB_AWPORT_HOV_SHIFT   (4U)
+#define USB_AWPORT_HOV_MASK    (0x7 << USB_AWPORT_HOV_SHIFT)
+#define USB_AWLOCK_HOV_SHIFT   (7U)
+#define USB_AWLOCK_HOV_MASK    (0x3 << USB_AWLOCK_HOV_SHIFT)
+#define USB_ARCACHE_HOV_SHIFT  (9U)
+#define USB_ARCACHE_HOV_MASK   (0xf << USB_ARCACHE_HOV_SHIFT)
+#define USB_ARPORT_HOV_SHIFT   (13U)
+#define USB_ARPORT_HOV_MASK    (0x7 << USB_ARPORT_HOV_SHIFT)
+#define USB_ARLOCK_HOV_SHIFT   (16U)
+#define USB_ARLOCK_HOV_MASK    (0x3 << USB_ARLOCK_HOV_SHIFT)
+#define USB_BUF_LD_EN_HOV      (1 << 18U)
+#define USB_DST_WD_HOV         (1 << 19U)
+
+/* 0x1C8 : DMA_CPS1 */
+#define USB_DMA_START_HOV        (1 << 0U)
+#define USB_DMA_TYPE_HOV         (1 << 1U)
+#define USB_DMA_IO_HOV           (1 << 2U)
+#define USB_DMA_ABORT_HOV        (1 << 3U)
+#define USB_CLRFIFO_DMAABORT_HOV (1 << 4U)
+#define USB_DMA_LEN_HOV_SHIFT    (8U)
+#define USB_DMA_LEN_HOV_MASK     (0x1ffff << USB_DMA_LEN_HOV_SHIFT)
+#define USB_R_HPORT_HOV_SHIFT    (25U)
+#define USB_R_HPORT_HOV_MASK     (0xf << USB_R_HPORT_HOV_SHIFT)
+#define USB_UNDEF_LEN_BURST_HOV  (1 << 29U)
+#define USB_L1_WAKEUP            (1 << 30U)
+#define USB_DEVPHY_SUSPEND_HOV   (1 << 31U)
+
+/* 0x1CC : DMA_CPS2 */
+#define USB_DMA_MADDR_HOV_SHIFT (0U)
+#define USB_DMA_MADDR_HOV_MASK  (0xffffffff << USB_DMA_MADDR_HOV_SHIFT)
+
+/* 0x1D0 : DMA_CPS3 */
+#define USB_SETUP_CMD_RPORT_SHIFT (0U)
+#define USB_SETUP_CMD_RPORT_MASK  (0xffffffff << USB_SETUP_CMD_RPORT_SHIFT)
+
+/* 0x1D4 : DMA_CPS4 */
+/* 0x1D8 : DEV_FMAP2 */
+/* 0x1DC : DEV_FCFG2 */
+/* 0x1E0 : DEV_FMAP3 */
+/* 0x1E4 : DEV_FCFG3 */
+/* 0x1E8 : DEV_FMAP4 */
+/* 0x1EC : DEV_FCFG4 */
+/* 0x1F0 : DEV_FIBC4 */
+/* 0x1F4 : DEV_FIBC5 */
+/* 0x1F8 : DEV_FIBC6 */
+/* 0x1FC : DEV_FIBC7 */
+
+/* 0x300 : VDMA_CXFPS1 */
+#define USB_VDMA_START_CXF     (1 << 0U)
+#define USB_VDMA_TYPE_CXF      (1 << 1U)
+#define USB_VDMA_IO_CXF        (1 << 2U)
+#define USB_VDMA_LEN_CXF_SHIFT (8U)
+#define USB_VDMA_LEN_CXF_MASK  (0x1ffff << USB_VDMA_LEN_CXF_SHIFT)
+
+/* 0x304 : VDMA_CXFPS2 */
+#define USB_VDMA_MADDR_CXF_SHIFT (8U)
+#define USB_VDMA_MADDR_CXF_MASK  (0x1ffff << USB_VDMA_MADDR_CXF_SHIFT)
+
+/* 0x308 : VDMA_F0PS1 */
+#define USB_VDMA_START_F0     (1 << 0U)
+#define USB_VDMA_TYPE_F0      (1 << 1U)
+#define USB_VDMA_IO_F0        (1 << 2U)
+#define USB_VDMA_LEN_F0_SHIFT (8U)
+#define USB_VDMA_LEN_F0_MASK  (0x1ffff << USB_VDMA_LEN_F0_SHIFT)
+
+/* 0x30c : VDMA_F0PS2 */
+#define USB_VDMA_MADDR_F0_SHIFT (8U)
+#define USB_VDMA_MADDR_F0_MASK  (0x1ffff << USB_VDMA_MADDR_F0_SHIFT)
+
+/* 0x310 : VDMA_F1PS1 */
+/* 0x314 : VDMA_F1PS2 */
+/* 0x318 : VDMA_F2PS1 */
+/* 0x31C : VDMA_F2PS2 */
+/* 0x320 : VDMA_F3PS1 */
+/* 0x324 : VDMA_F3PS2 */
+
+/* 0x328 : DEV_ISG3 */
+#define USB_VDMA_CMPLT_CXF (1 << 0U)
+#define USB_VDMA_CMPLT_F0  (1 << 1U)
+#define USB_VDMA_CMPLT_F1  (1 << 2U)
+#define USB_VDMA_CMPLT_F2  (1 << 3U)
+#define USB_VDMA_CMPLT_F3  (1 << 4U)
+#define USB_VDMA_ERROR_CXF (1 << 16U)
+#define USB_VDMA_ERROR_F0  (1 << 17U)
+#define USB_VDMA_ERROR_F1  (1 << 18U)
+#define USB_VDMA_ERROR_F2  (1 << 19U)
+#define USB_VDMA_ERROR_F3  (1 << 20U)
+
+/* 0x32C : DEV_MISG3 */
+#define USB_MVDMA_CMPLT_CXF (1 << 0U)
+#define USB_MVDMA_CMPLT_F0  (1 << 1U)
+#define USB_MVDMA_CMPLT_F1  (1 << 2U)
+#define USB_MVDMA_CMPLT_F2  (1 << 3U)
+#define USB_MVDMA_CMPLT_F3  (1 << 4U)
+#define USB_MVDMA_ERROR_CXF (1 << 16U)
+#define USB_MVDMA_ERROR_F0  (1 << 17U)
+#define USB_MVDMA_ERROR_F1  (1 << 18U)
+#define USB_MVDMA_ERROR_F2  (1 << 19U)
+#define USB_MVDMA_ERROR_F3  (1 << 20U)
+
+/* 0x330 : VDMA_CTRL */
+#define USB_VDMA_EN (1 << 0U)
+
+/* 0x334 : LPM_CAP */
+#define USB_LPM_WAKEUP_EN (1 << 0U)
+
+/* 0x338 : DEV_ISG4 */
+#define USB_L1_INT (1 << 0U)
+
+/* 0x33C : DEV_MISG4 */
+#define USB_ML1_INT (1 << 0U)
+
+/* 0x350 : VDMA_FnPS1 */
+/* 0x354 : VDMA_FnPS2 */
+
+#endif /* __HARDWARE_USB_V2_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_adc.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_adc.c
new file mode 100755
index 0000000000..2d231c79c2
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_adc.c
@@ -0,0 +1,646 @@
+#include "bflb_adc.h"
+#include "bflb_efuse.h"
+#include "hardware/adc_reg.h"
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define ADC_GPIP_BASE ((uint32_t)0x40002000)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define ADC_GPIP_BASE ((uint32_t)0x20002000)
+#endif
+
+volatile float coe = 1.0;
+volatile uint32_t tsen_offset;
+
+void bflb_adc_init(struct bflb_device_s *dev, const struct bflb_adc_config_s *config)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    /* adc disable */
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval &= ~AON_GPADC_GLOBAL_EN;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval |= AON_GPADC_GLOBAL_EN;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    /* adc reset */
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval |= AON_GPADC_SOFT_RST;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval &= ~AON_GPADC_SOFT_RST;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    /* disable int and clear status */
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    regval |= (GPIP_GPADC_FIFO_UNDERRUN_MASK | GPIP_GPADC_FIFO_OVERRUN_MASK | GPIP_GPADC_RDY_MASK |
+               GPIP_GPADC_FIFO_UNDERRUN_CLR | GPIP_GPADC_FIFO_OVERRUN_CLR | GPIP_GPADC_RDY_CLR);
+
+#if defined(BL702) || defined(BL702L)
+    regval |= (GPIP_GPADC_FIFO_RDY_MASK | GPIP_GPADC_FIFO_RDY);
+#endif
+    regval |= GPIP_GPADC_FIFO_CLR;
+    regval &= ~GPIP_GPADC_FIFO_THL_MASK;
+    regval &= ~GPIP_GPADC_DMA_EN;
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+    bflb_adc_start_conversion(dev);
+    bflb_mtimer_delay_ms(1);
+    bflb_adc_stop_conversion(dev);
+
+    regval = 0;
+    regval |= (2 << AON_GPADC_V18_SEL_SHIFT);                     /* V18 select 1.82V */
+    regval |= (1 << AON_GPADC_V11_SEL_SHIFT);                     /* V11 select 1.1V */
+    regval |= (config->clk_div << AON_GPADC_CLK_DIV_RATIO_SHIFT); /* clock div */
+    regval |= (config->resolution << AON_GPADC_RES_SEL_SHIFT);    /* resolution */
+    if (config->scan_conv_mode) {
+        regval |= AON_GPADC_SCAN_EN;
+        regval |= AON_GPADC_CLK_ANA_INV;
+    }
+    if (config->continuous_conv_mode) {
+        regval |= AON_GPADC_CONT_CONV_EN;
+    }
+
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+
+    regval = 0;
+    regval |= (2 << AON_GPADC_DLY_SEL_SHIFT);
+    regval |= (2 << AON_GPADC_CHOP_MODE_SHIFT); /* Vref AZ and PGA chop on */
+    regval |= (1 << AON_GPADC_PGA1_GAIN_SHIFT); /* gain 1 */
+    regval |= (1 << AON_GPADC_PGA2_GAIN_SHIFT); /* gain 1 */
+    regval |= AON_GPADC_PGA_EN;
+    regval |= (8 << AON_GPADC_PGA_OS_CAL_SHIFT);
+    regval |= (1 << AON_GPADC_PGA_VCM_SHIFT); /* PGA output common mode control 1.4V */
+
+    if (config->vref == ADC_VREF_2P0V) {
+        regval |= AON_GPADC_VREF_SEL;
+    }
+
+    if (config->differential_mode) {
+        regval |= AON_GPADC_DIFF_MODE;
+    }
+
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval |= AON_GPADC_MIC2_DIFF; /* mic2 diff enable */
+    if (config->differential_mode) {
+        regval &= ~AON_GPADC_NEG_GND;
+    } else {
+        regval |= AON_GPADC_NEG_GND;
+    }
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    /* calibration offset */
+    regval = getreg32(reg_base + AON_GPADC_REG_DEFINE_OFFSET);
+    regval &= ~AON_GPADC_OS_CAL_DATA_MASK;
+    putreg32(regval, reg_base + AON_GPADC_REG_DEFINE_OFFSET);
+
+    /* disable int and clear status */
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    regval |= (GPIP_GPADC_FIFO_UNDERRUN_MASK | GPIP_GPADC_FIFO_OVERRUN_MASK | GPIP_GPADC_RDY_MASK |
+               GPIP_GPADC_FIFO_UNDERRUN_CLR | GPIP_GPADC_FIFO_OVERRUN_CLR | GPIP_GPADC_RDY_CLR);
+
+#if defined(BL702) || defined(BL702L)
+    regval |= (GPIP_GPADC_FIFO_RDY_MASK | GPIP_GPADC_FIFO_RDY);
+#endif
+    regval |= GPIP_GPADC_FIFO_CLR;
+    regval &= ~GPIP_GPADC_FIFO_THL_MASK;
+    regval &= ~GPIP_GPADC_DMA_EN;
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    regval &= ~(GPIP_GPADC_FIFO_UNDERRUN_CLR |
+                GPIP_GPADC_FIFO_OVERRUN_CLR |
+                GPIP_GPADC_RDY_CLR |
+                GPIP_GPADC_FIFO_CLR);
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+    regval |= AON_GPADC_NEG_SATUR_MASK;
+    regval |= AON_GPADC_POS_SATUR_MASK;
+    putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+    coe = bflb_efuse_get_adc_trim();              /* read from efuse */
+    tsen_offset = bflb_efuse_get_adc_tsen_trim(); /* read from efuse */
+}
+
+void bflb_adc_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    /* adc disable */
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval &= ~AON_GPADC_GLOBAL_EN;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    /* adc reset */
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval |= AON_GPADC_SOFT_RST;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval &= ~AON_GPADC_SOFT_RST;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    putreg32(0, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+    putreg32(0, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+}
+
+void bflb_adc_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t regval;
+
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    if (enable) {
+        regval |= GPIP_GPADC_DMA_EN;
+    } else {
+        regval &= ~GPIP_GPADC_DMA_EN;
+    }
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+}
+
+int bflb_adc_channel_config(struct bflb_device_s *dev, struct bflb_adc_channel_s *chan, uint8_t channels)
+{
+    uint32_t regval;
+    uint32_t regval2;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    if (!(getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET) & AON_GPADC_SCAN_EN)) {
+        if (channels > 1) {
+            return -EINVAL;
+        }
+
+        regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+        regval &= ~AON_GPADC_POS_SEL_MASK;
+        regval &= ~AON_GPADC_NEG_SEL_MASK;
+        regval |= (chan->pos_chan << AON_GPADC_POS_SEL_SHIFT);
+        regval |= (chan->neg_chan << AON_GPADC_NEG_SEL_SHIFT);
+        putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+    } else {
+        if (channels < 6) {
+            regval = 0;
+            regval2 = 0;
+            for (uint8_t i = 0; i < channels; i++) {
+                regval |= (chan[i].pos_chan << (i * 5));
+                regval2 |= (chan[i].neg_chan << (i * 5));
+            }
+            putreg32(regval, reg_base + AON_GPADC_REG_SCN_POS1_OFFSET);
+            putreg32(regval2, reg_base + AON_GPADC_REG_SCN_NEG1_OFFSET);
+        } else {
+            regval = 0;
+            regval2 = 0;
+            for (uint8_t i = 0; i < 6; i++) {
+                regval |= (chan[i].pos_chan << (i * 5));
+                regval2 |= (chan[i].neg_chan << (i * 5));
+            }
+            putreg32(regval, reg_base + AON_GPADC_REG_SCN_POS1_OFFSET);
+            putreg32(regval2, reg_base + AON_GPADC_REG_SCN_NEG1_OFFSET);
+
+            regval = 0;
+            regval2 = 0;
+            for (uint8_t i = 0; i < (channels - 6); i++) {
+                regval |= (chan[i + 6].pos_chan << (i * 5));
+                regval2 |= (chan[i + 6].neg_chan << (i * 5));
+            }
+            putreg32(regval, reg_base + AON_GPADC_REG_SCN_POS2_OFFSET);
+            putreg32(regval2, reg_base + AON_GPADC_REG_SCN_NEG2_OFFSET);
+        }
+
+        regval = getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+        regval &= ~AON_GPADC_SCAN_LENGTH_MASK;
+        regval |= ((channels - 1) << AON_GPADC_SCAN_LENGTH_SHIFT);
+        putreg32(regval, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+    }
+    return 0;
+}
+
+void bflb_adc_start_conversion(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval &= ~AON_GPADC_CONV_START;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    bflb_mtimer_delay_us(100);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval |= AON_GPADC_CONV_START;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+}
+
+void bflb_adc_stop_conversion(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval &= ~AON_GPADC_CONV_START;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+}
+
+uint8_t bflb_adc_get_count(struct bflb_device_s *dev)
+{
+    return ((getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_FIFO_DATA_COUNT_MASK) >> GPIP_GPADC_FIFO_DATA_COUNT_SHIFT);
+}
+
+uint32_t bflb_adc_read_raw(struct bflb_device_s *dev)
+{
+    return getreg32(ADC_GPIP_BASE + GPIP_GPADC_DMA_RDATA_OFFSET) & GPIP_GPADC_DMA_RDATA_MASK;
+}
+
+void bflb_adc_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    if (mask) {
+        regval |= GPIP_GPADC_RDY_MASK;
+    } else {
+        regval &= ~GPIP_GPADC_RDY_MASK;
+    }
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+}
+
+void bflb_adc_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t regval2;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+    regval2 = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+    if (mask) {
+        regval |= AON_GPADC_POS_SATUR_MASK;
+        regval |= AON_GPADC_NEG_SATUR_MASK;
+        regval2 |= GPIP_GPADC_FIFO_UNDERRUN_MASK;
+        regval2 |= GPIP_GPADC_FIFO_OVERRUN_MASK;
+    } else {
+        regval &= ~AON_GPADC_POS_SATUR_MASK;
+        regval &= ~AON_GPADC_NEG_SATUR_MASK;
+        regval2 &= ~GPIP_GPADC_FIFO_UNDERRUN_MASK;
+        regval2 &= ~GPIP_GPADC_FIFO_OVERRUN_MASK;
+    }
+    putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+    putreg32(regval2, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+}
+
+uint32_t bflb_adc_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval = 0;
+
+    reg_base = dev->reg_base;
+
+    if (getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET) & AON_GPADC_NEG_SATUR) {
+        regval |= ADC_INTSTS_NEG_SATURATION;
+    }
+    if (getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET) & AON_GPADC_POS_SATUR) {
+        regval |= ADC_INTSTS_POS_SATURATION;
+    }
+    if (getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_FIFO_UNDERRUN) {
+        regval |= ADC_INTSTS_FIFO_UNDERRUN;
+    }
+    if (getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_FIFO_OVERRUN) {
+        regval |= ADC_INTSTS_FIFO_OVERRUN;
+    }
+    if (getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET) & GPIP_GPADC_RDY) {
+        regval |= ADC_INTSTS_ADC_READY;
+    }
+    return regval;
+}
+
+void bflb_adc_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    if (int_clear & ADC_INTCLR_NEG_SATURATION) {
+        regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+        regval &= ~AON_GPADC_NEG_SATUR_CLR;
+        putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+        regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+        regval |= AON_GPADC_NEG_SATUR_CLR;
+        putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+        regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+        regval &= ~AON_GPADC_NEG_SATUR_CLR;
+        putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+    }
+    if (int_clear & ADC_INTCLR_POS_SATURATION) {
+        regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+        regval &= ~AON_GPADC_POS_SATUR_CLR;
+        putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+        regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+        regval |= AON_GPADC_POS_SATUR_CLR;
+        putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+
+        regval = getreg32(reg_base + AON_GPADC_REG_ISR_OFFSET);
+        regval &= ~AON_GPADC_POS_SATUR_CLR;
+        putreg32(regval, reg_base + AON_GPADC_REG_ISR_OFFSET);
+    }
+    if (int_clear & ADC_INTCLR_FIFO_UNDERRUN) {
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval &= ~GPIP_GPADC_FIFO_UNDERRUN_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval |= GPIP_GPADC_FIFO_UNDERRUN_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval &= ~GPIP_GPADC_FIFO_UNDERRUN_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    }
+    if (int_clear & ADC_INTCLR_FIFO_OVERRUN) {
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval &= ~GPIP_GPADC_FIFO_OVERRUN_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval |= GPIP_GPADC_FIFO_OVERRUN_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval &= ~GPIP_GPADC_FIFO_OVERRUN_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    }
+    if (int_clear & ADC_INTCLR_ADC_READY) {
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval &= ~GPIP_GPADC_RDY_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval |= GPIP_GPADC_RDY_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+        regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+        regval &= ~GPIP_GPADC_RDY_CLR;
+        putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    }
+}
+
+void bflb_adc_parse_result(struct bflb_device_s *dev, uint32_t *buffer, struct bflb_adc_result_s *result, uint16_t count)
+{
+    uint32_t reg_base;
+    uint8_t resolution;
+    uint8_t diff_mode;
+    uint8_t vref;
+    uint32_t conv_result = 0;
+    uint16_t ref = 3200;
+    uint8_t neg = 0;
+    uint32_t tmp;
+
+    reg_base = dev->reg_base;
+
+    resolution = (getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET) & AON_GPADC_RES_SEL_MASK) >> AON_GPADC_RES_SEL_SHIFT;
+    diff_mode = (getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET) & AON_GPADC_DIFF_MODE) >> 2;
+    vref = (getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET) & AON_GPADC_VREF_SEL) >> 3;
+
+    if (vref == ADC_VREF_2P0V) {
+        ref = 2000;
+    }
+
+    /* single mode */
+    if (diff_mode == 0) {
+        for (uint16_t i = 0; i < count; i++) {
+            result[i].pos_chan = buffer[i] >> 21;
+            result[i].neg_chan = -1;
+
+            if (resolution == ADC_RESOLUTION_12B) {
+                conv_result = (uint32_t)(((buffer[i] & 0xffff) >> 4) / coe);
+                if (conv_result > 4095) {
+                    conv_result = 4095;
+                }
+                result[i].value = conv_result;
+                result[i].millivolt = (float)result[i].value / 4096 * ref;
+            } else if (resolution == ADC_RESOLUTION_14B) {
+                conv_result = (uint32_t)(((buffer[i] & 0xffff) >> 2) / coe);
+                if (conv_result > 16383) {
+                    conv_result = 16383;
+                }
+                result[i].value = conv_result;
+                result[i].millivolt = (float)result[i].value / 16384 * ref;
+            } else if (resolution == ADC_RESOLUTION_16B) {
+                conv_result = (uint32_t)((buffer[i] & 0xffff) / coe);
+                if (conv_result > 65535) {
+                    conv_result = 65535;
+                }
+                result[i].value = conv_result;
+                result[i].millivolt = (int32_t)result[i].value / 65536.0 * ref;
+            } else {
+            }
+        }
+    } else {
+        for (uint16_t i = 0; i < count; i++) {
+            result[i].pos_chan = buffer[i] >> 21;
+            result[i].neg_chan = (buffer[i] >> 16) & 0x1F;
+
+            tmp = buffer[i];
+
+            if (tmp & 0x8000) {
+                tmp = ~tmp;
+                tmp += 1;
+                neg = 1;
+            }
+
+            if (resolution == ADC_RESOLUTION_12B) {
+                conv_result = (uint32_t)(((tmp & 0xffff) >> 4) / coe);
+                if (conv_result > 2047) {
+                    conv_result = 2047;
+                }
+                result[i].value = conv_result;
+                result[i].millivolt = (float)result[i].value / 2048 * ref;
+            } else if (resolution == ADC_RESOLUTION_14B) {
+                conv_result = (uint32_t)(((tmp & 0xffff) >> 2) / coe);
+                if (conv_result > 8191) {
+                    conv_result = 8191;
+                }
+                result[i].value = conv_result;
+                result[i].millivolt = (float)result[i].value / 8192 * ref;
+            } else if (resolution == ADC_RESOLUTION_16B) {
+                conv_result = (uint32_t)((tmp & 0xffff) / coe);
+                if (conv_result > 32767) {
+                    conv_result = 32767;
+                }
+                result[i].value = conv_result;
+                result[i].millivolt = (float)result[i].value / 32768 * ref;
+            } else {
+            }
+
+            if (neg) {
+                result[i].value = -result[i].value;
+                result[i].millivolt = -result[i].millivolt;
+            }
+        }
+    }
+}
+
+void bflb_adc_tsen_init(struct bflb_device_s *dev, uint8_t tsen_mod)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval &= ~AON_GPADC_SEN_TEST_EN;
+    regval |= (0 << AON_GPADC_SEN_SEL_SHIFT);
+    regval &= ~AON_GPADC_CHIP_SEN_PU;
+    regval |= AON_GPADC_DWA_EN;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+    regval &= ~AON_GPADC_TSVBE_LOW;
+    regval |= (2 << AON_GPADC_DLY_SEL_SHIFT);
+    regval |= (0 << AON_GPADC_TEST_SEL_SHIFT);
+    regval &= ~AON_GPADC_TEST_EN;
+    regval |= AON_GPADC_TS_EN;
+    if (tsen_mod) {
+        regval |= AON_GPADC_TSEXT_SEL;
+    } else {
+        regval &= ~AON_GPADC_TSEXT_SEL;
+    }
+    regval |= (2 << AON_GPADC_PGA_VCM_SHIFT);
+    regval &= ~AON_GPADC_PGA_VCMI_EN;
+    regval |= (0 << AON_GPADC_PGA_OS_CAL_SHIFT);
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+    regval |= AON_GPADC_DITHER_EN;
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG1_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CMD_OFFSET);
+    regval |= AON_GPADC_MIC2_DIFF;
+    putreg32(regval, reg_base + AON_GPADC_REG_CMD_OFFSET);
+}
+
+float bflb_adc_tsen_get_temp(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    struct bflb_adc_result_s result;
+    uint32_t v0 = 0, v1 = 0;
+    float temp = 0;
+    uint32_t raw_data;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    regval |= (0 << 22);
+    regval |= GPIP_GPADC_FIFO_CLR;
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+    regval &= ~AON_GPADC_TSVBE_LOW;
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+    bflb_adc_start_conversion(dev);
+    start_time = bflb_mtimer_get_time_ms();
+    while (bflb_adc_get_count(dev) == 0) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    raw_data = bflb_adc_read_raw(dev);
+    bflb_adc_parse_result(dev, &raw_data, &result, 1);
+    v0 = result.value;
+    regval = getreg32(ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+    regval |= GPIP_GPADC_FIFO_CLR;
+    putreg32(regval, ADC_GPIP_BASE + GPIP_GPADC_CONFIG_OFFSET);
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+    regval |= AON_GPADC_TSVBE_LOW;
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+
+    bflb_adc_start_conversion(dev);
+    start_time = bflb_mtimer_get_time_ms();
+    while (bflb_adc_get_count(dev) == 0) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    raw_data = bflb_adc_read_raw(dev);
+    bflb_adc_parse_result(dev, &raw_data, &result, 1);
+    v1 = result.value;
+    if (v0 > v1) {
+        temp = (((float)v0 - (float)v1) - (float)tsen_offset) / 7.753;
+    } else {
+        temp = (((float)v1 - (float)v0) - (float)tsen_offset) / 7.753;
+    }
+
+    return temp;
+}
+
+void bflb_adc_vbat_enable(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+    regval |= AON_GPADC_VBAT_EN;
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+}
+
+void bflb_adc_vbat_disable(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+    regval &= ~AON_GPADC_VBAT_EN;
+    putreg32(regval, reg_base + AON_GPADC_REG_CONFIG2_OFFSET);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_auadc.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_auadc.c
new file mode 100755
index 0000000000..8f813b5094
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_auadc.c
@@ -0,0 +1,291 @@
+#include "bflb_auadc.h"
+#include "hardware/auadc_reg.h"
+
+int bflb_auadc_init(struct bflb_device_s *dev, const struct bflb_auadc_init_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AUADC_AUDPDM_TOP_OFFSET);
+    /* enable clk */
+    regval |= AUADC_AUDIO_CKG_EN;
+    /* sampling rate */
+    regval &= ~AUADC_ADC_RATE_MASK;
+    regval |= config->sampling_rate << AUADC_ADC_RATE_SHIFT;
+    putreg32(regval, reg_base + AUADC_AUDPDM_TOP_OFFSET);
+
+    /* disable ch0 and enable dma interface */
+    regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET);
+    regval &= ~AUADC_ADC_0_EN;
+    regval |= AUADC_ADC_ITF_EN;
+    putreg32(regval, reg_base + AUADC_AUDPDM_ITF_OFFSET);
+
+    /* pdm or adc input */
+    regval = getreg32(reg_base + AUADC_PDM_DAC_0_OFFSET);
+    if (config->input_mode == AUADC_INPUT_MODE_ADC) {
+        regval &= ~AUADC_ADC_0_SRC;
+    } else {
+        regval |= AUADC_ADC_0_SRC;
+    }
+    putreg32(regval, reg_base + AUADC_PDM_DAC_0_OFFSET);
+
+    /* pdm cfg */
+    regval = getreg32(reg_base + AUADC_PDM_PDM_0_OFFSET);
+    if (config->input_mode == AUADC_INPUT_MODE_PDM_L || config->input_mode == AUADC_INPUT_MODE_PDM_R) {
+        /* enable pdm */
+        regval |= AUADC_PDM_0_EN;
+        /* pdm_l or pdm_r input */
+        regval &= ~AUADC_ADC_0_PDM_SEL_MASK;
+        if (config->input_mode == AUADC_INPUT_MODE_PDM_L) {
+            regval |= 0 << AUADC_ADC_0_PDM_SEL_SHIFT;
+        } else if (config->input_mode == AUADC_INPUT_MODE_PDM_R) {
+            regval |= 1 << AUADC_ADC_0_PDM_SEL_SHIFT;
+        }
+    } else {
+        /* disable pdm */
+        regval &= ~AUADC_PDM_0_EN;
+    }
+    putreg32(regval, reg_base + AUADC_PDM_PDM_0_OFFSET);
+
+    regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+    /* audio osr configuration */
+    if (config->input_mode != AUADC_INPUT_MODE_ADC && (config->sampling_rate == AUADC_SAMPLING_RATE_32K || config->sampling_rate == AUADC_SAMPLING_RATE_48K)) {
+        /* osr 64 */
+        regval |= AUADC_AUDADC_AUDIO_OSR_SEL;
+    } else {
+        /* osr 128 */
+        regval &= ~AUADC_AUDADC_AUDIO_OSR_SEL;
+    }
+    putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+    /* fifo configuration */
+    regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+    /* data format */
+    regval &= ~AUADC_RX_DATA_MODE_MASK;
+    regval |= config->data_format << AUADC_RX_DATA_MODE_SHIFT;
+
+    /* fifo threshold */
+    regval &= ~AUADC_RX_TRG_LEVEL_MASK;
+    regval |= config->fifo_threshold << AUADC_RX_TRG_LEVEL_SHIFT;
+    regval &= ~AUADC_RX_DRQ_CNT_MASK;
+
+    /* disable record */
+    regval &= ~AUADC_RX_CH_EN;
+
+    /* 24bit sample */
+    regval &= ~AUADC_RX_DATA_RES_MASK;
+    regval |= 2 << AUADC_RX_DATA_RES_SHIFT;
+
+    /* disable fifo dma and int */
+    regval &= ~AUADC_RX_DRQ_EN;
+    regval &= ~AUADC_RXA_INT_EN;
+    regval &= ~AUADC_RXU_INT_EN;
+    regval &= ~AUADC_RXO_INT_EN;
+
+    /* clear fifo */
+    regval |= AUADC_RX_FIFO_FLUSH;
+    putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+    /* enable ch0 */
+    regval = getreg32(reg_base + AUADC_AUDPDM_ITF_OFFSET);
+    regval |= AUADC_ADC_0_EN;
+    putreg32(regval, reg_base + AUADC_AUDPDM_ITF_OFFSET);
+
+    return 0;
+}
+
+int bflb_auadc_adc_init(struct bflb_device_s *dev, const struct bflb_auadc_adc_init_config_s *adc_analog_cfg)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    if (adc_analog_cfg->auadc_analog_en == false) {
+        /* disable analog and channel */
+        regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+        regval &= ~AUADC_AUDADC_PGA_PU;
+        regval &= ~AUADC_AUDADC_SDM_PU;
+        regval &= ~AUADC_AUDADC_CHANNEL_EN_MASK;
+        putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+        return 0;
+    }
+
+    /* power up, and SDM reset */
+    regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+    regval |= AUADC_AUDADC_PGA_PU;
+    regval |= AUADC_AUDADC_SDM_PU;
+    regval &= ~AUADC_AUDADC_CONV;
+    putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+    /* select analog channel */
+    regval &= ~AUADC_AUDADC_CHANNEL_SELP_MASK;
+    regval &= ~AUADC_AUDADC_CHANNEL_SELN_MASK;
+    regval |= adc_analog_cfg->adc_pga_posi_ch << AUADC_AUDADC_CHANNEL_SELP_SHIFT;
+    regval |= adc_analog_cfg->adc_pga_nega_ch << AUADC_AUDADC_CHANNEL_SELN_SHIFT;
+
+    /* PGA mode */
+    regval &= ~AUADC_AUDADC_PGA_MODE_MASK;
+    regval |= adc_analog_cfg->adc_pga_mode << AUADC_AUDADC_PGA_MODE_SHIFT;
+
+    /* PGA gain */
+    regval &= ~AUADC_AUDADC_PGA_GAIN_MASK;
+    regval |= (adc_analog_cfg->adc_pga_gain / 3) << AUADC_AUDADC_PGA_GAIN_SHIFT;
+
+    /* adc mode */
+    if (adc_analog_cfg->adc_mode == AUADC_ADC_MODE_AUDIO) {
+        regval &= ~AUADC_AUDADC_MEAS_FILTER_EN;
+    } else {
+        regval |= AUADC_AUDADC_MEAS_FILTER_EN;
+    }
+
+    /* measuring mode rate */
+    regval &= ~AUADC_AUDADC_MEAS_ODR_SEL_MASK;
+    regval |= adc_analog_cfg->adc_measure_rate << AUADC_AUDADC_MEAS_ODR_SEL_SHIFT;
+
+    /* enable analog channel */
+    regval &= ~AUADC_AUDADC_CHANNEL_EN_MASK;
+    if (adc_analog_cfg->adc_pga_mode == AUADC_ADC_PGA_MODE_AC_DIFFER || adc_analog_cfg->adc_pga_mode == AUADC_ADC_PGA_MODE_DC_DIFFER) {
+        regval |= 0x03 << AUADC_AUDADC_CHANNEL_EN_SHIFT;
+    } else {
+        regval |= 0x02 << AUADC_AUDADC_CHANNEL_EN_SHIFT;
+    }
+    putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+    /* SDM conversion start */
+    regval |= AUADC_AUDADC_CONV;
+    putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+
+    return 0;
+}
+
+int bflb_auadc_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+    if (enable) {
+        regval |= AUADC_RX_DRQ_EN;
+    } else {
+        regval &= ~AUADC_RX_DRQ_EN;
+    }
+    putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+    return 0;
+}
+
+int bflb_auadc_int_mask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* fifo int */
+    regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+    regval &= ~int_sts;
+    putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+    return 0;
+}
+
+int bflb_auadc_int_unmask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* fifo int */
+    regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+    regval |= int_sts;
+    putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+
+    return 0;
+}
+
+int bflb_auadc_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    int32_t int_sts;
+
+    reg_base = dev->reg_base;
+    int_sts = 0;
+
+    regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_STATUS_OFFSET);
+    if (regval & AUADC_RXO_INT) {
+        int_sts |= AUADC_INTSTS_FIFO_OVER;
+    }
+    if (regval & AUADC_RXU_INT) {
+        int_sts |= AUADC_INTSTS_FIFO_UNDER;
+    }
+    if (regval & AUADC_RXA_INT) {
+        int_sts |= AUADC_INTSTS_FIFO_AVAILABLE;
+    }
+
+    return int_sts;
+}
+
+int bflb_auadc_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+    int16_t volume_val;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case AUADC_CMD_RECORD_START:
+            /* record start */
+            regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+            regval |= AUADC_RX_CH_EN;
+            putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+            break;
+
+        case AUADC_CMD_RECORD_STOP:
+            /* record stop */
+            regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+            regval &= ~AUADC_RX_CH_EN;
+            putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+            break;
+
+        case AUADC_CMD_SET_VOLUME_VAL:
+            /* set volume value dB, arg range -191 to + 36, 0.5dB step, range -95.5dB to +18dB*/
+            volume_val = (uint16_t)((int16_t)arg * 2);
+            regval = getreg32(reg_base + AUADC_PDM_ADC_S0_OFFSET);
+            regval &= ~AUADC_ADC_S0_VOLUME_MASK;
+            regval |= (volume_val << AUADC_ADC_S0_VOLUME_SHIFT) & AUADC_ADC_S0_VOLUME_MASK;
+            putreg32(regval, reg_base + AUADC_PDM_ADC_S0_OFFSET);
+            break;
+
+        case AUADC_CMD_SET_PGA_GAIN_VAL:
+            /* set adc pga gain, range 6dB ~ 42dB, step by 3db */
+            volume_val = arg / 3;
+            regval = getreg32(reg_base + AUADC_AUDADC_CMD_OFFSET);
+            regval &= ~AUADC_AUDADC_PGA_GAIN_MASK;
+            regval |= (volume_val << AUADC_AUDADC_PGA_GAIN_SHIFT) & AUADC_AUDADC_PGA_GAIN_MASK;
+            putreg32(regval, reg_base + AUADC_AUDADC_CMD_OFFSET);
+            break;
+
+        case AUADC_CMD_CLEAR_RX_FIFO:
+            /* get rx fifo cnt */
+            regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+            regval |= AUADC_RX_FIFO_FLUSH;
+            putreg32(regval, reg_base + AUADC_AUDADC_RX_FIFO_CTRL_OFFSET);
+            break;
+
+        case AUADC_CMD_GET_RX_FIFO_CNT:
+            /* get rx fifo cnt */
+            regval = getreg32(reg_base + AUADC_AUDADC_RX_FIFO_STATUS_OFFSET);
+            ret = (regval & AUADC_RXA_CNT_MASK) >> AUADC_RXA_CNT_SHIFT;
+    }
+
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_audac.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_audac.c
new file mode 100755
index 0000000000..75202f4ee1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_audac.c
@@ -0,0 +1,360 @@
+#include "bflb_audac.h"
+#include "hardware/audac_reg.h"
+#include "hardware/dac_reg.h"
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define GLB_BASE ((uint32_t)0x20000000)
+#endif
+
+static volatile uint32_t g_audac_channel_mode = 0;
+
+int bflb_audac_init(struct bflb_device_s *dev, const struct bflb_audac_init_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* enable clk, enable dma interface, disable ch0 */
+    regval = getreg32(reg_base + AUDAC_0_OFFSET);
+    regval |= AUDAC_CKG_ENA;
+    regval |= AUDAC_DAC_ITF_EN;
+    regval |= AUDAC_DAC_0_EN;
+
+    /* set output mode and sampling rate */
+    regval &= ~AUDAC_AU_PWM_MODE_MASK;
+    if (config->output_mode != AUDAC_OUTPUT_MODE_PWM) {
+        regval |= (config->sampling_rate + 8) << AUDAC_AU_PWM_MODE_SHIFT;
+    } else {
+        regval |= config->sampling_rate << AUDAC_AU_PWM_MODE_SHIFT;
+    }
+    putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+    regval = getreg32(reg_base + AUDAC_1_OFFSET);
+    /* set dsm dither, scaling, and order */
+    regval &= ~AUDAC_DAC_DSM_SCALING_MODE_MASK;
+    regval |= 3 << AUDAC_DAC_DSM_SCALING_MODE_SHIFT;
+    regval &= ~AUDAC_DAC_DSM_ORDER_MASK;
+    regval |= 1 << AUDAC_DAC_DSM_ORDER_SHIFT;
+
+    /* set mixer */
+    regval &= ~AUDAC_DAC_MIX_SEL_MASK;
+    if (config->source_channels_num == AUDAC_SOURCE_CHANNEL_DUAL) {
+        regval |= config->mixer_mode << AUDAC_DAC_MIX_SEL_SHIFT;
+    }
+    putreg32(regval, reg_base + AUDAC_1_OFFSET);
+
+    regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+    /* data format */
+    regval &= ~AUDAC_TX_DATA_MODE_MASK;
+    regval |= config->data_format;
+
+    /* fifo threshold */
+    regval &= ~AUDAC_TX_TRG_LEVEL_MASK;
+    regval |= (config->fifo_threshold << AUDAC_TX_TRG_LEVEL_SHIFT) & AUDAC_TX_TRG_LEVEL_MASK;
+    regval &= ~AUDAC_TX_DRQ_CNT_MASK;
+
+    /* dma disable */
+    regval &= ~AUDAC_TX_DRQ_EN;
+
+    /* source channels num */
+    regval &= ~AUDAC_TX_CH_EN_MASK;
+    g_audac_channel_mode = config->source_channels_num;
+
+    /* disable fifo int */
+    regval &= ~AUDAC_TXO_INT_EN;
+    regval &= ~AUDAC_TXU_INT_EN;
+    regval &= ~AUDAC_TXA_INT_EN;
+
+    /* clear fifo */
+    regval &= ~AUDAC_TX_FIFO_FLUSH;
+    putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+
+    /* enable zero delete */
+    regval = getreg32(reg_base + AUDAC_ZD_0_OFFSET);
+    regval |= AUDAC_ZD_EN;
+    regval &= ~AUDAC_ZD_TIME_MASK;
+    regval |= 512 << AUDAC_ZD_TIME_SHIFT;
+    putreg32(regval, reg_base + AUDAC_ZD_0_OFFSET);
+
+    /* disable volume interrupt */
+    regval = getreg32(reg_base + AUDAC_STATUS_OFFSET);
+    regval |= AUDAC_DAC_S0_INT_CLR;
+    putreg32(regval, reg_base + AUDAC_STATUS_OFFSET);
+
+    /* gpdac config */
+    reg_base = GLB_BASE;
+    if (config->output_mode != AUDAC_OUTPUT_MODE_PWM) {
+        /* Select Internal reference */
+        regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+        regval |= (GLB_GPDACA_RSTN_ANA | GLB_GPDACB_RSTN_ANA);
+        regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+        regval &= ~GLB_GPDAC_REF_SEL;
+
+        /* Select the clock and data from aupdac */
+        regval |= GLB_GPDAC_ANA_CLK_SEL;
+        if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_A) {
+            regval |= GLB_GPDAC_DAT_CHA_SEL;
+        }
+        if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_B) {
+            regval |= GLB_GPDAC_DAT_CHB_SEL;
+        }
+        putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+        if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_A) {
+            /* gpdac enable ch-A */
+            regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+            regval |= (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+            putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+        }
+
+        if (config->output_mode & AUDAC_OUTPUT_MODE_GPDAC_CH_B) {
+            /* gpdac enable ch-A */
+            regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET);
+            regval |= (GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN);
+            putreg32(regval, reg_base + GLB_GPDAC_BCTRL_OFFSET);
+        }
+    }
+
+    return 0;
+}
+
+int bflb_audac_volume_init(struct bflb_device_s *dev, const struct bflb_audac_volume_config_s *vol_cfg)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* enable volume update */
+    regval = getreg32(reg_base + AUDAC_S0_OFFSET);
+    regval |= AUDAC_DAC_S0_VOLUME_UPDATE;
+
+    if (vol_cfg->mute_ramp_en) {
+        /* mute ramp mode */
+        regval |= AUDAC_DAC_S0_MUTE_SOFTMODE;
+        regval &= ~AUDAC_DAC_S0_MUTE_RMPDN_RATE_MASK;
+        regval |= vol_cfg->mute_down_ramp_rate << AUDAC_DAC_S0_MUTE_RMPDN_RATE_SHIFT;
+        regval &= ~AUDAC_DAC_S0_MUTE_RMPUP_RATE_MASK;
+        regval |= vol_cfg->mute_up_ramp_rate << AUDAC_DAC_S0_MUTE_RMPUP_RATE_SHIFT;
+
+    } else {
+        /* mute directly mode */
+        regval &= ~AUDAC_DAC_S0_MUTE_SOFTMODE;
+    }
+
+    regval &= ~AUDAC_DAC_S0_CTRL_MODE_MASK;
+    if (vol_cfg->volume_update_mode == AUDAC_VOLUME_UPDATE_MODE_RAMP) {
+        /* ramp mode */
+        regval |= 2 << AUDAC_DAC_S0_CTRL_MODE_SHIFT;
+        regval &= ~AUDAC_DAC_S0_CTRL_RMP_RATE_MASK;
+        regval |= vol_cfg->volume_ramp_rate << AUDAC_DAC_S0_CTRL_RMP_RATE_SHIFT;
+    } else if (vol_cfg->volume_update_mode == AUDAC_VOLUME_UPDATE_MODE_RAMP_ZERO_CROSSING) {
+        /* ramp and zero crossing mode */
+        regval |= 1 << AUDAC_DAC_S0_CTRL_MODE_SHIFT;
+        regval &= ~AUDAC_DAC_S0_CTRL_ZCD_RATE_MASK;
+        regval |= vol_cfg->volume_ramp_rate << AUDAC_DAC_S0_CTRL_ZCD_RATE_SHIFT;
+    }
+    putreg32(regval, reg_base + AUDAC_S0_OFFSET);
+
+    return 0;
+}
+
+int bflb_audac_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+    if (enable) {
+        regval |= AUDAC_TX_DRQ_EN;
+    } else {
+        regval &= ~AUDAC_TX_DRQ_EN;
+    }
+    putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+
+    return 0;
+}
+
+int bflb_audac_int_mask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    if (int_sts & AUDAC_INTSTS_VOLUME_RAMP) {
+        /* volume ramp done int */
+        regval = getreg32(reg_base + AUDAC_0_OFFSET);
+        regval &= ~(0x01 << 17);
+        putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+        int_sts &= ~AUDAC_INTSTS_VOLUME_RAMP;
+    }
+
+    if (int_sts) {
+        /* fifo int */
+        regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+        regval &= ~int_sts;
+        putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+    }
+
+    return 0;
+}
+
+int bflb_audac_int_unmask(struct bflb_device_s *dev, uint32_t int_sts)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    if (int_sts & AUDAC_INTSTS_VOLUME_RAMP) {
+        /* volume ramp done int */
+        regval = getreg32(reg_base + AUDAC_0_OFFSET);
+        regval |= (0x01 << 17);
+        putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+        int_sts &= ~AUDAC_INTSTS_VOLUME_RAMP;
+    }
+
+    if (int_sts) {
+        /* fifo int */
+        regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+        regval |= int_sts;
+        putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+    }
+
+    return 0;
+}
+
+int bflb_audac_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    int32_t int_sts;
+
+    reg_base = dev->reg_base;
+    int_sts = 0;
+
+    /* volume ramp done int */
+    regval = getreg32(reg_base + AUDAC_0_OFFSET);
+    if (regval & (0x01 << 17)) {
+        int_sts |= AUDAC_INTSTS_VOLUME_RAMP;
+    }
+
+    /* fifo int */
+    regval = getreg32(reg_base + AUDAC_FIFO_STATUS_OFFSET);
+    if (regval & AUDAC_TXO_INT) {
+        int_sts |= AUDAC_INTSTS_FIFO_OVER;
+    }
+    if (regval & AUDAC_TXU_INT) {
+        int_sts |= AUDAC_INTSTS_FIFO_UNDER;
+    }
+    if (regval & AUDAC_TXA_INT) {
+        int_sts |= AUDAC_INTSTS_FIFO_AVAILABLE;
+    }
+
+    return int_sts;
+}
+
+int bflb_audac_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint8_t ramp_int_en;
+
+    reg_base = dev->reg_base;
+
+    if (int_clear & AUDAC_INTSTS_VOLUME_RAMP) {
+        /* volume ramp done int */
+        regval = getreg32(reg_base + AUDAC_0_OFFSET);
+
+        if (regval & (0x01 << 17)) {
+            ramp_int_en = 0;
+        } else {
+            ramp_int_en = 1;
+        }
+
+        regval |= (0x01 << 17);
+        putreg32(regval, reg_base + AUDAC_0_OFFSET);
+
+        if (ramp_int_en) {
+            regval &= ~(0x01 << 17);
+        }
+        putreg32(regval, reg_base + AUDAC_0_OFFSET);
+    }
+
+    return 0;
+}
+
+int bflb_audac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+    int16_t volume_val;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case AUDAC_CMD_PLAY_START:
+            /* play start */
+            regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+            regval &= ~AUDAC_TX_CH_EN_MASK;
+            regval |= g_audac_channel_mode << AUDAC_TX_CH_EN_SHIFT;
+            putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+            g_audac_channel_mode = 0;
+            break;
+
+        case AUDAC_CMD_PLAY_STOP:
+            /* play stop */
+            regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+            if (g_audac_channel_mode == 0) {
+                g_audac_channel_mode = (regval & AUDAC_TX_CH_EN_MASK) >> AUDAC_TX_CH_EN_SHIFT;
+            }
+            regval &= ~AUDAC_TX_CH_EN_MASK;
+            putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+            break;
+
+        case AUDAC_CMD_SET_MUTE:
+            /* set mute, arg use true or false */
+            regval = getreg32(reg_base + AUDAC_S0_OFFSET);
+            if (arg) {
+                regval |= AUDAC_DAC_S0_MUTE;
+            } else {
+                regval &= ~AUDAC_DAC_S0_MUTE;
+            }
+            putreg32(regval, reg_base + AUDAC_S0_OFFSET);
+            break;
+
+        case AUDAC_CMD_SET_VOLUME_VAL:
+            /* set volume value dB, arg range -191 to + 36, 0.5dB step, range -95.5dB to +18dB*/
+            volume_val = (uint16_t)((int16_t)arg * 2);
+            regval = getreg32(reg_base + AUDAC_S0_OFFSET);
+            regval &= ~AUDAC_DAC_S0_VOLUME_MASK;
+            regval |= (volume_val << AUDAC_DAC_S0_VOLUME_SHIFT) & AUDAC_DAC_S0_VOLUME_MASK;
+            putreg32(regval, reg_base + AUDAC_S0_OFFSET);
+            break;
+
+        case AUDAC_CMD_CLEAR_TX_FIFO:
+            /* get tx fifo cnt */
+            regval = getreg32(reg_base + AUDAC_FIFO_CTRL_OFFSET);
+            regval |= AUDAC_TX_FIFO_FLUSH;
+            putreg32(regval, reg_base + AUDAC_FIFO_CTRL_OFFSET);
+            break;
+
+        case AUDAC_CMD_GET_TX_FIFO_CNT:
+            /* get tx fifo cnt */
+            regval = getreg32(reg_base + AUDAC_FIFO_STATUS_OFFSET);
+            ret = (regval & AUDAC_TXA_CNT_MASK) >> AUDAC_TXA_CNT_SHIFT;
+            break;
+
+        default:
+            break;
+    }
+
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cam.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cam.c
new file mode 100755
index 0000000000..3120831233
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cam.c
@@ -0,0 +1,624 @@
+#include "bflb_cam.h"
+#include "hardware/cam_reg.h"
+#if !defined(BL702)
+#include "hardware/cam_front_reg.h"
+#include "bflb_clock.h"
+#endif
+
+#if defined(BL616)
+#define CAM_FRONT_BASE 0x20050000
+#endif
+#if defined(BL808)
+#define CAM_FRONT_BASE 0x30010000
+#endif
+
+void bflb_cam_init(struct bflb_device_s *dev, const struct bflb_cam_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint8_t data_mode = 0;
+    uint16_t resolution_x, resolution_y;
+    uint32_t frame_size;
+#if !defined(BL702)
+    uint32_t threshold;
+#endif
+#if defined(BL808)
+    uint32_t tmpval;
+
+    if (config->input_source) {
+        tmpval = 0x15;
+        regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+        regval |= CAM_FRONT_REG_ISP_DTSRC_SRC;
+        putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+
+        regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_ADJA_CTRL_2_OFFSET);
+        regval |= 1;
+        putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_ADJA_CTRL_2_OFFSET);
+    } else {
+        tmpval = 0x24;
+        regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+        regval &= ~CAM_FRONT_REG_ISP_DTSRC_SRC;
+        putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_PIX_DATA_CTRL_OFFSET);
+    }
+#endif
+
+    reg_base = dev->reg_base;
+    putreg32(config->output_bufaddr, reg_base + CAM_DVP2AXI_ADDR_START_OFFSET);
+    putreg32(config->resolution_y << 16 | config->resolution_x, reg_base + CAM_DVP2AXI_FRAM_EXM_OFFSET);
+    putreg32(data_mode, reg_base + CAM_DVP_DEBUG_OFFSET);
+
+    regval = getreg32(reg_base + CAM_DVP2AXI_HSYNC_CROP_OFFSET);
+#if defined(BL702)
+    if ((regval & 0xffff) > 2 * config->resolution_x) {
+        resolution_x = config->resolution_x;
+    } else {
+        resolution_x = ((regval & 0xffff) - (regval >> 16 & 0xffff)) / 2;
+    }
+#else
+    if ((regval & 0xffff) > config->resolution_x) {
+        resolution_x = config->resolution_x;
+    } else {
+        resolution_x = (regval & 0xffff) - (regval >> 16 & 0xffff);
+    }
+#endif
+    regval = getreg32(reg_base + CAM_DVP2AXI_VSYNC_CROP_OFFSET);
+    if ((regval & 0xffff) > config->resolution_y) {
+        resolution_y = config->resolution_y;
+    } else {
+        resolution_y = (regval & 0xffff) - (regval >> 16 & 0xffff);
+    }
+
+#if defined(BL616)
+    putreg32(0, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+#endif
+
+#if !defined(BL702)
+#if defined(BL808)
+    if (config->input_source != CAM_INPUT_SOURCE_CSI) {
+#endif
+        regval = bflb_clk_get_system_clock(BFLB_SYSTEM_PBCLK);
+        if (regval == 0) {
+            regval = 80;
+        }
+        threshold = (config->h_blank + 4 * config->resolution_x - 2 * config->resolution_x * (config->pixel_clock / 1000000) / regval) / 4;
+
+        regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+        regval &= ~CAM_FRONT_RG_DVPAS_FIFO_TH_MASK;
+        regval |= threshold << CAM_FRONT_RG_DVPAS_FIFO_TH_SHIFT;
+        putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+#if defined(BL808)
+    }
+#endif
+#endif
+
+    /* Set output format */
+    frame_size = resolution_x * resolution_y * 2;
+    regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+    if (config->with_mjpeg) {
+        regval &= ~CAM_REG_SW_MODE;
+    } else {
+        regval |= CAM_REG_SW_MODE;
+    }
+#if defined(BL702)
+    regval |= CAM_REG_INTERLV_MODE;
+    regval &= ~(CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN | CAM_REG_SUBSAMPLE_EVEN);
+#else
+    regval &= ~(CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_DVP_DATA_MODE_MASK | CAM_REG_DVP_DATA_BSEL | CAM_REG_V_SUBSAMPLE_EN | CAM_REG_V_SUBSAMPLE_POL);
+#endif
+    switch (config->input_format) {
+        case CAM_INPUT_FORMAT_YUV422_YUYV:
+#if defined(BL808)
+            if (config->output_format >= CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 && config->output_format <= CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+                tmpval = 0x23;
+                if (config->input_source) {
+                    putreg32(0x18000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+                } else {
+                    putreg32(0xa8000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+                }
+                putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_1_OFFSET);
+                putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_2_OFFSET);
+                putreg32(0x200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_3_OFFSET);
+                putreg32(0x20002ce, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_4_OFFSET);
+                putreg32(0xfe92ff50, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_5_OFFSET);
+                putreg32(0x38b0200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_6_OFFSET);
+                putreg32(0, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_7_OFFSET);
+
+                if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
+                    data_mode = 1;
+                    frame_size = resolution_x * resolution_y * 3;
+                    break;
+                } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
+                    data_mode = 2;
+                    frame_size = resolution_x * resolution_y * 2;
+                    putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+                    break;
+                } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
+                    data_mode = 2;
+                    frame_size = resolution_x * resolution_y * 2;
+                    putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+                    break;
+                } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+                    data_mode = 3;
+                    frame_size = resolution_x * resolution_y * 4;
+                    break;
+                }
+            }
+#endif
+        case CAM_INPUT_FORMAT_YUV422_YVYU:
+            if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_YUV422) {
+                data_mode = 0;
+                frame_size = resolution_x * resolution_y * 2;
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
+#if defined(BL702)
+                regval |= CAM_REG_DROP_EN;
+#endif
+                data_mode = 4;
+                frame_size = resolution_x * resolution_y;
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV422_UV) {
+#if defined(BL702)
+                regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN;
+#else
+                regval |= CAM_REG_DVP_DATA_BSEL;
+#endif
+                data_mode = 4;
+                frame_size = resolution_x * resolution_y;
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV420_UV) {
+#if defined(BL702)
+                regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN;
+#else
+                regval |= CAM_REG_DVP_DATA_BSEL | CAM_REG_V_SUBSAMPLE_EN | CAM_REG_V_SUBSAMPLE_POL;
+#endif
+                data_mode = 4;
+                frame_size = resolution_x * resolution_y / 2;
+#if defined(BL616)
+                putreg32(1, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+#endif
+            }
+            break;
+
+        case CAM_INPUT_FORMAT_YUV422_UYVY:
+#if defined(BL808)
+            if (config->output_format >= CAM_OUTPUT_FORMAT_RGB888_OR_BGR888 && config->output_format <= CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+                bflb_cam_swap_input_yu_order(dev, true);
+                tmpval = 0x23;
+                if (config->input_source) {
+                    putreg32(0x18000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+                } else {
+                    putreg32(0xa8000000, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_0_OFFSET);
+                }
+                putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_1_OFFSET);
+                putreg32(0xff80, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_2_OFFSET);
+                putreg32(0x200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_3_OFFSET);
+                putreg32(0x20002ce, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_4_OFFSET);
+                putreg32(0xfe92ff50, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_5_OFFSET);
+                putreg32(0x38b0200, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_6_OFFSET);
+                putreg32(0, CAM_FRONT_BASE + CAM_FRONT_Y2RA_CONFIG_7_OFFSET);
+
+                if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
+                    data_mode = 1;
+                    frame_size = resolution_x * resolution_y * 3;
+                    break;
+                } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
+                    data_mode = 2;
+                    frame_size = resolution_x * resolution_y * 2;
+                    putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+                    break;
+                } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
+                    data_mode = 2;
+                    frame_size = resolution_x * resolution_y * 2;
+                    putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+                    break;
+                } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+                    data_mode = 3;
+                    frame_size = resolution_x * resolution_y * 4;
+                    break;
+                }
+            }
+#endif
+        case CAM_INPUT_FORMAT_YUV422_VYUY:
+            if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_YUV422) {
+                data_mode = 0;
+                frame_size = resolution_x * resolution_y * 2;
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
+#if defined(BL702)
+                regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN;
+#else
+                regval |= CAM_REG_DVP_DATA_BSEL;
+#endif
+                data_mode = 4;
+                frame_size = resolution_x * resolution_y;
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV422_UV) {
+#if defined(BL702)
+                regval |= CAM_REG_DROP_EN;
+#endif
+                data_mode = 4;
+                frame_size = resolution_x * resolution_y;
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_YUV420_UV) {
+#if defined(BL702)
+                regval |= CAM_REG_DROP_EN | CAM_REG_DROP_EVEN | CAM_REG_SUBSAMPLE_EN | CAM_REG_SUBSAMPLE_EVEN;
+#else
+                regval |= CAM_REG_V_SUBSAMPLE_EN;
+#endif
+                data_mode = 4;
+                frame_size = resolution_x * resolution_y / 2;
+#if defined(BL616)
+                putreg32(1, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+#endif
+            }
+            break;
+
+        case CAM_INPUT_FORMAT_GRAY:
+            if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_GRAY) {
+                data_mode = 0;
+                frame_size = resolution_x * resolution_y;
+            }
+            break;
+
+        case CAM_INPUT_FORMAT_RGB565:
+            /* Same as CAM_INPUT_FORMAT_BGR565 */
+        case CAM_INPUT_FORMAT_BGR565:
+            if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_RGB565_OR_BGR565) {
+                data_mode = 0;
+                frame_size = resolution_x * resolution_y * 2;
+            }
+            break;
+
+        case CAM_INPUT_FORMAT_RGB888:
+            /* Same as CAM_INPUT_FORMAT_BGR888 */
+        case CAM_INPUT_FORMAT_BGR888:
+            if (config->output_format == CAM_OUTPUT_FORMAT_AUTO || config->output_format == CAM_OUTPUT_FORMAT_RGB888_OR_BGR888) {
+                data_mode = 1;
+                frame_size = resolution_x * resolution_y * 3;
+#if !defined(BL702)
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGB565) {
+                data_mode = 2;
+                frame_size = resolution_x * resolution_y * 2;
+                putreg32(5 << CAM_REG_FORMAT_565_SHIFT, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_BGR565) {
+                data_mode = 2;
+                frame_size = resolution_x * resolution_y * 2;
+                putreg32(0, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+            } else if (config->output_format == CAM_OUTPUT_FORMAT_RGB888_TO_RGBA8888) {
+                /* Default A = 0 */
+                data_mode = 3;
+                frame_size = resolution_x * resolution_y * 4;
+#endif
+            }
+            break;
+
+        default:
+            break;
+    }
+#if !defined(BL702)
+    putreg32(frame_size, reg_base + CAM_DVP2AXI_FRAME_BCNT_OFFSET);
+    regval |= data_mode << CAM_REG_DVP_DATA_MODE_SHIFT;
+#endif
+    putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+
+    /* Set output buffer burst count */
+    regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+    regval = (regval & CAM_REG_XLEN_MASK) >> CAM_REG_XLEN_SHIFT;
+    switch (regval) {
+        case CAM_BURST_INCR1:
+#if defined(BL702)
+            regval = config->output_bufsize >> 2;
+            frame_size = frame_size >> 2;
+#else
+            regval = config->output_bufsize >> 3;
+#endif
+            break;
+
+        case CAM_BURST_INCR4:
+#if defined(BL702)
+            regval = config->output_bufsize >> 4;
+            frame_size = frame_size >> 4;
+#else
+            regval = config->output_bufsize >> 5;
+#endif
+            break;
+
+        case CAM_BURST_INCR8:
+#if defined(BL702)
+            regval = config->output_bufsize >> 5;
+            frame_size = frame_size >> 5;
+#else
+            regval = config->output_bufsize >> 6;
+#endif
+            break;
+
+        case CAM_BURST_INCR16:
+#if defined(BL702)
+            regval = config->output_bufsize >> 6;
+            frame_size = frame_size >> 6;
+#else
+            regval = config->output_bufsize >> 7;
+#endif
+            break;
+
+#if !defined(BL702)
+        case CAM_BURST_INCR32:
+            regval = config->output_bufsize >> 8;
+            break;
+
+        case CAM_BURST_INCR64:
+            regval = config->output_bufsize >> 9;
+            break;
+#endif
+
+        default:
+            regval = config->output_bufsize >> 7;
+            frame_size = frame_size >> 6;
+            break;
+    }
+    putreg32(regval, reg_base + CAM_DVP2AXI_MEM_BCNT_OFFSET);
+
+#if defined(BL702)
+    putreg32(frame_size, reg_base + CAM_DVP2AXI_FRAME_BCNT_0_OFFSET);
+#endif
+
+#if defined(BL808)
+    if (dev->idx < 4) {
+        regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+        regval &= ~(0x3f << (dev->idx * 8));
+        regval |= tmpval << (dev->idx * 8);
+        putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_1_OFFSET);
+    } else {
+        regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET);
+        regval &= ~(0x3f << ((dev->idx - 4) * 8));
+        regval |= tmpval << ((dev->idx - 4) * 8);
+        putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_DVP2BUS_SRC_SEL_2_OFFSET);
+    }
+#endif
+
+#if !defined(BL702)
+#if defined(BL808)
+    if (config->input_source == 0) {
+        regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+        regval |= CAM_FRONT_RG_DVPAS_ENABLE;
+        putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+    }
+#else
+    regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+    regval |= CAM_FRONT_RG_DVPAS_ENABLE;
+    putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+#endif
+#endif
+}
+
+void bflb_cam_start(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+    regval |= CAM_REG_DVP_ENABLE;
+    putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+}
+
+void bflb_cam_stop(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+    regval &= ~CAM_REG_DVP_ENABLE;
+    putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+}
+
+void bflb_cam_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+#if defined(BL702)
+    regval = getreg32(reg_base + CAM_INT_CONTROL_OFFSET);
+#else
+    regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+#endif
+    if (mask) {
+        regval &= ~int_type;
+    } else {
+        regval |= int_type;
+    }
+#if defined(BL702)
+    putreg32(regval, reg_base + CAM_INT_CONTROL_OFFSET);
+#else
+    putreg32(regval, reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+#endif
+}
+
+void bflb_cam_int_clear(struct bflb_device_s *dev, uint32_t int_type)
+{
+    putreg32(int_type, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
+}
+
+void bflb_cam_crop_vsync(struct bflb_device_s *dev, uint16_t start_line, uint16_t end_line)
+{
+    /* Get start_line ~ (end_line - 1), not include end_line */
+    putreg32(start_line << 16 | end_line, dev->reg_base + CAM_DVP2AXI_VSYNC_CROP_OFFSET);
+}
+
+void bflb_cam_crop_hsync(struct bflb_device_s *dev, uint16_t start_pixel, uint16_t end_pixel)
+{
+#if defined(BL702)
+    start_pixel = start_pixel * 2;
+    end_pixel = end_pixel * 2;
+#endif
+    /* Get start_pixel ~ (end_pixel - 1), not include end_pixel */
+    putreg32(start_pixel << 16 | end_pixel, dev->reg_base + CAM_DVP2AXI_HSYNC_CROP_OFFSET);
+}
+
+void bflb_cam_pop_one_frame(struct bflb_device_s *dev)
+{
+#if defined(BL702)
+    putreg32(3, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
+#else
+    putreg32(1, dev->reg_base + CAM_DVP_FRAME_FIFO_POP_OFFSET);
+#endif
+}
+
+#if !defined(BL702)
+void bflb_cam_swap_input_yu_order(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t regval;
+
+    /* If image sensor output format is YUYV, it will be changed to UYVY */
+    regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+    if (enable) {
+        regval |= CAM_FRONT_RG_DVPAS_DA_ORDER;
+    } else {
+        regval &= ~CAM_FRONT_RG_DVPAS_DA_ORDER;
+    }
+    putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+}
+
+void bflb_cam_filter_frame_period(struct bflb_device_s *dev, uint8_t frame_count, uint32_t frame_valid)
+{
+    /* For example: frame_count is 4, frame_valid is 0x14 (10100b). Third/fifth frame will be retained,
+       First/second/fourth frame will be dropped in every (4 + 1) frames */
+    putreg32(frame_count, dev->reg_base + CAM_DVP2AXI_FRAME_PERIOD_OFFSET);
+    putreg32(frame_valid, dev->reg_base + CAM_DVP2AXI_FRAME_VLD_OFFSET);
+}
+#endif
+
+uint8_t bflb_cam_get_frame_count(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+    regval &= CAM_FRAME_VALID_CNT_MASK;
+    return (regval >> CAM_FRAME_VALID_CNT_SHIFT);
+}
+
+uint32_t bflb_cam_get_frame_info(struct bflb_device_s *dev, uint8_t **pic)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    *pic = (uint8_t *)getreg32(reg_base + CAM_FRAME_START_ADDR0_OFFSET);
+#if defined(BL702)
+    return (getreg32(reg_base + CAM_FRAME_BYTE_CNT0_0_OFFSET));
+#else
+    return (getreg32(reg_base + CAM_DVP2AXI_FRAME_BCNT_OFFSET));
+#endif
+}
+
+uint32_t bflb_cam_get_intstatus(struct bflb_device_s *dev)
+{
+    return (getreg32(dev->reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET));
+}
+
+int bflb_cam_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case CAM_CMD_SET_VSYNC_POLARITY:
+            /* Set vsync polarity, arg use @ref CAM_POLARITY */
+            regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            if (arg) {
+                regval |= CAM_REG_FRAM_VLD_POL;
+            } else {
+                regval &= ~CAM_REG_FRAM_VLD_POL;
+            }
+            putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            break;
+
+        case CAM_CMD_SET_HSYNC_POLARITY:
+            /* Set hsync polarity, arg use @ref CAM_POLARITY */
+            regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            if (arg) {
+                regval |= CAM_REG_LINE_VLD_POL;
+            } else {
+                regval &= ~CAM_REG_LINE_VLD_POL;
+            }
+            putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            break;
+
+        case CAM_CMD_SET_BURST:
+            /* Set burst length, arg use @ref CAM_BURST */
+            regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            regval &= ~CAM_REG_XLEN_MASK;
+            regval |= (arg << CAM_REG_XLEN_SHIFT) & CAM_REG_XLEN_MASK;
+            putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            break;
+
+#if !defined(BL702)
+        case CAM_CMD_SET_RGBA8888_ALPHA:
+            /* Set alpha value of RGBA8888 output, arg is alpha */
+            regval = getreg32(reg_base + CAM_DVP2AXI_MISC_OFFSET);
+            regval &= ~CAM_REG_ALPHA_MASK;
+            regval |= arg & CAM_REG_ALPHA_MASK;
+            putreg32(regval, reg_base + CAM_DVP2AXI_MISC_OFFSET);
+            break;
+
+        case CAM_CMD_GET_FRAME_ID:
+            /* Get frame id */
+            *(uint16_t *)arg = getreg32(reg_base + CAM_FRAME_ID_STS01_OFFSET) & 0xffff;
+            break;
+#endif
+
+        case CAM_CMD_WRAP_MODE:
+            /* Wrap to output buffer start address, only effective in mjpeg mode, arg use ENABLE or DISABLE */
+            regval = getreg32(reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            if (arg) {
+                regval |= CAM_REG_HW_MODE_FWRAP;
+            } else {
+                regval &= ~CAM_REG_HW_MODE_FWRAP;
+            }
+            putreg32(regval, reg_base + CAM_DVP2AXI_CONFIGUE_OFFSET);
+            break;
+
+        case CAM_CMD_COUNT_TRIGGER_NORMAL_INT:
+            /* Set frame count to trigger normal interrupt, arg is frame count */
+#if defined(BL702)
+            regval = getreg32(reg_base + CAM_INT_CONTROL_OFFSET);
+            regval &= ~CAM_REG_FRAME_CNT_TRGR_INT_MASK;
+            regval |= arg << CAM_REG_FRAME_CNT_TRGR_INT_SHIFT;
+            putreg32(regval, reg_base + CAM_INT_CONTROL_OFFSET);
+#else
+            regval = getreg32(reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+            regval &= ~CAM_REG_FRAME_CNT_TRGR_INT_MASK;
+            regval |= arg & CAM_REG_FRAME_CNT_TRGR_INT_MASK;
+            putreg32(regval, reg_base + CAM_DVP_STATUS_AND_ERROR_OFFSET);
+#endif
+            break;
+
+#if !defined(BL702)
+        case CAM_CMD_FRAME_ID_RESET:
+            /* Reset frame id */
+            regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_ISP_ID_YUV_OFFSET);
+            regval |= CAM_FRONT_REG_YUV_IDGEN_RST;
+            putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_ISP_ID_YUV_OFFSET);
+            break;
+
+        case CAM_CMD_INVERSE_VSYNC_POLARITY:
+            /* Inverse vsync polarity */
+            regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+            regval |= CAM_FRONT_RG_DVPAS_VS_INV;
+            putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+            break;
+
+        case CAM_CMD_INVERSE_HSYNC_POLARITY:
+            /* Inverse hsync polarity */
+            regval = getreg32(CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+            regval |= CAM_FRONT_RG_DVPAS_HS_INV;
+            putreg32(regval, CAM_FRONT_BASE + CAM_FRONT_CONFIG_OFFSET);
+            break;
+#endif
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cks.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cks.c
new file mode 100755
index 0000000000..830702ae82
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_cks.c
@@ -0,0 +1,34 @@
+#include "bflb_cks.h"
+#include "hardware/cks_reg.h"
+
+void bflb_cks_reset(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + CKS_CONFIG_OFFSET);
+    regval |= CKS_CR_CKS_CLR;
+    putreg32(regval, reg_base + CKS_CONFIG_OFFSET);
+}
+
+void bflb_cks_set_endian(struct bflb_device_s *dev, uint8_t endian)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    putreg32(endian << 1, reg_base + CKS_CONFIG_OFFSET);
+}
+
+uint16_t bflb_cks_compute(struct bflb_device_s *dev, uint8_t *data, uint32_t length)
+{
+    uint32_t reg_base;
+    uint32_t i;
+
+    reg_base = dev->reg_base;
+    for (i = 0; i < length; i++) {
+        putreg32(data[i], reg_base + CKS_DATA_IN_OFFSET);
+    }
+
+    return ((uint16_t)(getreg32(reg_base + CKS_OUT_OFFSET) & 0xffff));
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c
new file mode 100755
index 0000000000..e46bfd7858
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_clock.c
@@ -0,0 +1,93 @@
+#include "bflb_clock.h"
+#if defined(BL702)
+#include "bl702_clock.h"
+#elif defined(BL702L)
+#include "bl702l_clock.h"
+#elif defined(BL606P)
+#include "bl606p_clock.h"
+#elif defined(BL808)
+#include "bl808_clock.h"
+#elif defined(BL616)
+#include "bl616_clock.h"
+#elif defined(WB03)
+#include "wb03_clock.h"
+#elif defined(BL628)
+#include "bl628_clock.h"
+#endif
+
+/****************************************************************************/ /**
+ * @brief  get system clock
+ *
+ * @param  type: BFLB_SYSTEM_XXX
+ *
+ * @return NONE
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION bflb_clk_get_system_clock(uint8_t type)
+{
+    switch (type) {
+        case BFLB_SYSTEM_ROOT_CLOCK:
+            return bflb_clock_get_root();
+        case BFLB_SYSTEM_CPU_CLK:
+            return bflb_clock_get_fclk();
+        case BFLB_SYSTEM_PBCLK:
+            return bflb_clock_get_bclk();
+        case BFLB_SYSTEM_XCLK:
+            return bflb_clock_get_xclk();
+        case BFLB_SYSTEM_32K_CLK:
+            return bflb_clock_get_f32k();
+        default:
+            return 0;
+    }
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  get peripheral clock
+ *
+ * @param  type: BFLB_DEVICE_TYPE_XXX
+ * @param  idx: peripheral index
+ *
+ * @return NONE
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
+{
+    switch (type) {
+        case BFLB_DEVICE_TYPE_ADC:
+            return bflb_clock_get_adc();
+        case BFLB_DEVICE_TYPE_DAC:
+            return bflb_clock_get_dac();
+        case BFLB_DEVICE_TYPE_UART:
+            return bflb_clock_get_uart();
+        case BFLB_DEVICE_TYPE_SPI:
+            return bflb_clock_get_spi();
+        case BFLB_DEVICE_TYPE_I2C:
+            return bflb_clock_get_i2c();
+        case BFLB_DEVICE_TYPE_PWM:
+            return bflb_clock_get_pwm();
+        case BFLB_DEVICE_TYPE_TIMER:
+            return bflb_clock_get_timer(idx);
+        case BFLB_DEVICE_TYPE_WDT:
+            return bflb_clock_get_wdt();
+        case BFLB_DEVICE_TYPE_FLASH:
+            return bflb_clock_get_flash();
+        case BFLB_DEVICE_TYPE_IR:
+            return bflb_clock_get_ir();
+        case BFLB_DEVICE_TYPE_PKA:
+            return bflb_clock_get_pka();
+        case BFLB_DEVICE_TYPE_SDH:
+            return bflb_clock_get_sdh();
+        case BFLB_DEVICE_TYPE_CAMERA:
+            return bflb_clock_get_cam();
+        case BFLB_DEVICE_TYPE_DBI:
+            return bflb_clock_get_dbi();
+        case BFLB_DEVICE_TYPE_PEC:
+            return bflb_clock_get_pec();
+        case BFLB_DEVICE_TYPE_I2S:
+            return bflb_clock_get_i2s();
+        default:
+            return 0;
+    }
+    return 0;
+}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_common.c
old mode 100644
new mode 100755
similarity index 76%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_common.c
index d8380bf752..17db99b7df
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/common/soft_crc/softcrc.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_common.c
@@ -1,27 +1,92 @@
-/**
- * @file softcrc.c
- * @brief
- *
- * Copyright (c) 2021 Bouffalolab team
- *
- * Licensed to the Apache Software Foundation (ASF) under one or more
- * contributor license agreements.  See the NOTICE file distributed with
- * this work for additional information regarding copyright ownership.  The
- * ASF licenses this file to you under the Apache License, Version 2.0 (the
- * "License"); you may not use this file except in compliance with the
- * License.  You may obtain a copy of the License at
- *
- *   http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
- * License for the specific language governing permissions and limitations
- * under the License.
- *
- */
-#include "softcrc.h"
-#include "misc.h"
+#include "bflb_common.h"
+#include "bflb_core.h"
+
+void *ATTR_TCM_SECTION arch_memcpy(void *dst, const void *src, uint32_t n)
+{
+    const uint8_t *p = src;
+    uint8_t *q = dst;
+
+    while (n--) {
+        *q++ = *p++;
+    }
+
+    return dst;
+}
+
+uint32_t *ATTR_TCM_SECTION arch_memcpy4(uint32_t *dst, const uint32_t *src, uint32_t n)
+{
+    const uint32_t *p = src;
+    uint32_t *q = dst;
+
+    while (n--) {
+        *q++ = *p++;
+    }
+
+    return dst;
+}
+
+void *ATTR_TCM_SECTION arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n)
+{
+    uint32_t left, done, i = 0;
+    uint8_t *dst = (uint8_t *)pdst;
+    uint8_t *src = (uint8_t *)psrc;
+
+    if (((uint32_t)(uintptr_t)dst & 0x3) == 0 && ((uint32_t)(uintptr_t)src & 0x3) == 0) {
+        arch_memcpy4((uint32_t *)dst, (const uint32_t *)src, n >> 2);
+        left = n % 4;
+        done = n - left;
+
+        while (i < left) {
+            dst[done + i] = src[done + i];
+            i++;
+        }
+    } else {
+        arch_memcpy(dst, src, n);
+    }
+
+    return dst;
+}
+
+void *ATTR_TCM_SECTION arch_memset(void *s, uint8_t c, uint32_t n)
+{
+    uint8_t *p = (uint8_t *)s;
+
+    while (n > 0) {
+        *p++ = (uint8_t)c;
+        --n;
+    }
+
+    return s;
+}
+
+uint32_t *ATTR_TCM_SECTION arch_memset4(uint32_t *dst, const uint32_t val, uint32_t n)
+{
+    uint32_t *q = dst;
+
+    while (n--) {
+        *q++ = val;
+    }
+
+    return dst;
+}
+
+int ATTR_TCM_SECTION arch_memcmp(const void *s1, const void *s2, uint32_t n)
+{
+    const unsigned char *c1 = s1, *c2 = s2;
+    int d = 0;
+
+    while (n--) {
+        d = (int)*c1++ - (int)*c2++;
+
+        if (d) {
+            break;
+        }
+    }
+
+    return d;
+}
+
+
 // ---------------- POPULAR POLYNOMIALS ----------------
 // CCITT:      x^16 + x^12 + x^5 + x^0                 (0x1021,init 0x0000)
 // CRC-16:     x^16 + x^15 + x^2 + x^0                 (0x8005,init 0xFFFF)
@@ -77,12 +142,12 @@ const uint8_t chCRCLTalbe[] = {
     0x41, 0x81, 0x80, 0x40
 };
 
-uint16_t BFLB_Soft_CRC16(void *dataIn, uint32_t len)
+uint16_t bflb_soft_crc16(void *in, uint32_t len)
 {
     uint8_t chCRCHi = 0xFF;
     uint8_t chCRCLo = 0xFF;
     uint16_t wIndex;
-    uint8_t *data = (uint8_t *)dataIn;
+    uint8_t *data = (uint8_t *)in;
 
     while (len--) {
         wIndex = chCRCLo ^ *data++;
@@ -142,10 +207,10 @@ const uint32_t crc32Tab[256] = {
     0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d
 };
 
-uint32_t BFLB_Soft_CRC32_Table(void *dataIn, uint32_t len)
+uint32_t bflb_soft_crc32_table(void *in, uint32_t len)
 {
     uint32_t crc = 0;
-    uint8_t *data = (uint8_t *)dataIn;
+    uint8_t *data = (uint8_t *)in;
 
     crc = crc ^ 0xffffffff;
 
@@ -166,18 +231,18 @@ uint32_t BFLB_Soft_CRC32_Table(void *dataIn, uint32_t len)
 * Alias:   CRC_32/ADCCP
 * Use:     WinRAR,ect.
 *****************************************************************************/
-uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uint32_t len)
+uint32_t ATTR_TCM_SECTION bflb_soft_crc32_ex(uint32_t initial, void *in, uint32_t len)
 {
     uint8_t i;
-    uint32_t crc = ~initial;        // Initial value
-    uint8_t *data=(uint8_t *)dataIn;
+    uint32_t crc = ~initial; // Initial value
+    uint8_t *data = (uint8_t *)in;
 
-    while(len--){
-        crc ^= *data++;                // crc ^= *data; data++;
-        for (i = 0; i < 8; ++i){
-            if (crc & 1){
-                crc = (crc >> 1) ^ 0xEDB88320;// 0xEDB88320= reverse 0x04C11DB7
-            }else{
+    while (len--) {
+        crc ^= *data++; // crc ^= *data; data++;
+        for (i = 0; i < 8; ++i) {
+            if (crc & 1) {
+                crc = (crc >> 1) ^ 0xEDB88320; // 0xEDB88320= reverse 0x04C11DB7
+            } else {
                 crc = (crc >> 1);
             }
         }
@@ -185,10 +250,9 @@ uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32_Ex(uint32_t initial, void *dataIn, uin
     return ~crc;
 }
 
-#ifndef BFLB_USE_ROM_DRIVER
-__WEAK__
-uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len)
+#if !defined(BL602) && !defined(BL702)
+uint32_t ATTR_TCM_SECTION bflb_soft_crc32(void *in, uint32_t len)
 {
-    return BFLB_Soft_CRC32_Ex(0,dataIn,len);
+    return bflb_soft_crc32_ex(0, in, len);
 }
-#endif
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_csi.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_csi.c
new file mode 100755
index 0000000000..7237e2c3d5
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_csi.c
@@ -0,0 +1,143 @@
+#include "bflb_csi.h"
+#include "hardware/csi_reg.h"
+#include "hardware/dtsrc_reg.h"
+
+#define DTSRC_BASE 0x30012800
+
+static void bflb_csi_phy_config(struct bflb_device_s *dev, uint32_t tx_clk_escape, uint32_t data_rate)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    
+    /* Unit: ns */
+    float TD_TERM_EN_MAX = 35 + 4 * (1e3) / data_rate; 
+    uint32_t TD_TERM_EN = (TD_TERM_EN_MAX * data_rate / 2 / (1e3)) - 1;
+    float THS_SETTLE_MAX = 145 + 10 * (1e3) / data_rate;
+    /* THS_SETTLE = reg_time_hs_settle + reg_time_hs_term_en */
+    uint32_t THS_SETTLE = ((THS_SETTLE_MAX - TD_TERM_EN * 2 * (1e3) / data_rate) * data_rate / 2 / (1e3)) - 1;
+    uint32_t TCLK_TERM_EN_MAX = 38;
+    uint32_t TCLK_TERM_EN = (tx_clk_escape * TCLK_TERM_EN_MAX) / (1e3);
+    uint32_t TCLK_SETTLE_MAX = 300;
+    /* TCLK_SETTLE = reg_time_ck_settle + reg_time_ck_term_en */
+    uint32_t TCLK_SETTLE = ((TCLK_SETTLE_MAX - TCLK_TERM_EN * (1e3) / tx_clk_escape) * tx_clk_escape / (1e3)) - 1;
+
+    uint32_t ANA_TERM_EN = 0x8;
+    
+    reg_base = dev->reg_base;
+    regval = TD_TERM_EN  << CSI_REG_TIME_HS_TERM_EN_SHIFT & CSI_REG_TIME_HS_TERM_EN_MASK;
+    regval |= THS_SETTLE << CSI_REG_TIME_HS_SETTLE_SHIFT & CSI_REG_TIME_HS_SETTLE_MASK;
+    regval |= TCLK_TERM_EN << CSI_REG_TIME_CK_TERM_EN_SHIFT & CSI_REG_TIME_CK_TERM_EN_MASK;
+    regval |= TCLK_SETTLE << CSI_REG_TIME_CK_SETTLE_SHIFT & CSI_REG_TIME_CK_SETTLE_MASK;
+    putreg32(regval, reg_base + CSI_DPHY_CONFIG_1_OFFSET);
+    
+    regval = getreg32(DTSRC_BASE + CSI_DPHY_CONFIG_2_OFFSET);
+    regval &= ~CSI_REG_ANA_TERM_EN_MASK;
+    regval |= ANA_TERM_EN << CSI_REG_ANA_TERM_EN_SHIFT & CSI_REG_ANA_TERM_EN_MASK;
+    putreg32(regval, reg_base + CSI_DPHY_CONFIG_2_OFFSET);
+}
+
+void bflb_csi_init(struct bflb_device_s *dev, const struct bflb_csi_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+    regval |= DTSRC_CR_SNSR_EN;
+    putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+    
+    regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+    regval &= ~(CSI_DL0_ENABLE | CSI_DL1_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE | CSI_DL1_FORCERXMODE | CSI_RESET_N);
+    putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+    regval |= CSI_RESET_N;
+    putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+    
+    regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
+    if (config->lane_number) {
+        regval |= CSI_CR_LANE_NUM;
+    } else {
+        regval &= ~CSI_CR_LANE_NUM;
+    }
+    regval |= CSI_CR_UNPACK_EN | CSI_CR_SYNC_SP_EN;
+    putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
+    
+    bflb_csi_phy_config(dev, config->tx_clk_escape / 1000000, config->data_rate / 1000000);
+    
+    regval = getreg32(reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+    regval |= CSI_DL0_ENABLE | CSI_CL_ENABLE | CSI_DL0_FORCERXMODE;
+    if (config->lane_number) {
+        regval |= CSI_DL1_ENABLE | CSI_DL1_FORCERXMODE;
+    }
+    putreg32(regval, reg_base + CSI_DPHY_CONFIG_0_OFFSET);
+    
+    regval = getreg32(DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+    regval |= DTSRC_CR_ENABLE;
+    putreg32(regval, DTSRC_BASE + DTSRC_CONFIG_OFFSET);
+}
+
+void bflb_csi_start(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
+    regval |= CSI_CR_CSI_EN;
+    putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
+}
+
+void bflb_csi_stop(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + CSI_MIPI_CONFIG_OFFSET);
+    regval &= ~CSI_CR_CSI_EN;
+    putreg32(regval, reg_base + CSI_MIPI_CONFIG_OFFSET);
+}
+
+void bflb_csi_set_line_threshold(struct bflb_device_s *dev, uint16_t resolution_x, uint32_t pixel_clock, uint32_t dsp_clock)
+{
+    uint32_t threshold;
+    
+    threshold = (dsp_clock - pixel_clock) / 1000 * resolution_x / (dsp_clock / 1000) + 10;
+    putreg32(threshold, DTSRC_BASE + DTSRC_SNSR2DVP_WAIT_POS_OFFSET);
+}
+
+void bflb_csi_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + CSI_INT_MASK_OFFSET);
+    if (mask) {
+        regval |= int_type;
+    } else {
+        regval &= ~int_type;
+    }
+    putreg32(regval, reg_base + CSI_INT_MASK_OFFSET);
+}
+
+void bflb_csi_int_clear(struct bflb_device_s *dev, uint32_t int_type)
+{
+    putreg32(int_type, dev->reg_base + CSI_INT_CLEAR_OFFSET);
+}
+
+uint32_t bflb_csi_get_intstatus(struct bflb_device_s *dev)
+{
+    return(getreg32(dev->reg_base + CSI_INT_STATUS_OFFSET));
+}
+
+int bflb_csi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+
+    switch (cmd) {
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dac.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dac.c
new file mode 100755
index 0000000000..5cdfa034b5
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dac.c
@@ -0,0 +1,160 @@
+#include "bflb_dac.h"
+#include "hardware/dac_reg.h"
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define DAC_GPIP_BASE ((uint32_t)0x40002000)
+#elif defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)
+#define DAC_GPIP_BASE ((uint32_t)0x20002000)
+#endif
+
+void bflb_dac_init(struct bflb_device_s *dev, uint8_t clk_div)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    /* dac reset */
+    regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+    regval &= ~GLB_GPDACA_RSTN_ANA;
+    putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+
+    regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+    regval &= ~GLB_GPDACB_RSTN_ANA;
+    putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+    __asm volatile("nop");
+
+    regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+    regval |= (GLB_GPDACA_RSTN_ANA | GLB_GPDACB_RSTN_ANA);
+    putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+    regval = getreg32(reg_base + GLB_GPDAC_CTRL_OFFSET);
+    regval &= ~GLB_GPDAC_REF_SEL;
+    putreg32(regval, reg_base + GLB_GPDAC_CTRL_OFFSET);
+
+    regval = 0;
+    regval |= GPIP_GPDAC_EN;
+#ifdef GPIP_GPDAC_EN2
+    regval |= GPIP_GPDAC_EN2;
+#endif
+    regval |= (clk_div << GPIP_GPDAC_MODE_SHIFT);
+    putreg32(regval, DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET);
+
+    regval = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+    regval &= ~GPIP_GPDAC_DMA_TX_EN;
+    putreg32(regval, DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+}
+
+void bflb_dac_channel_enable(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    if (ch & DAC_CHANNEL_A) {
+        regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+        regval |= (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+        putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+    }
+
+    if (ch & DAC_CHANNEL_B) {
+        regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET);
+        regval |= (GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN);
+        putreg32(regval, reg_base + GLB_GPDAC_BCTRL_OFFSET);
+#ifdef GPIP_GPDAC_EN2
+        regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+        regval |= (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+        putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+#endif
+    }
+}
+
+void bflb_dac_channel_disable(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    if (ch & DAC_CHANNEL_A) {
+        regval = getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET);
+        regval &= ~(GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN);
+        putreg32(regval, reg_base + GLB_GPDAC_ACTRL_OFFSET);
+    }
+
+    if (ch & DAC_CHANNEL_B) {
+        regval = getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET);
+        regval &= ~(GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN);
+        putreg32(regval, reg_base + GLB_GPDAC_BCTRL_OFFSET);
+    }
+}
+
+void bflb_dac_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t regval1;
+    uint32_t regval2;
+    uint32_t reg_base;
+    uint8_t flag = 0;
+
+    reg_base = dev->reg_base;
+
+    regval1 = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET);
+    regval1 &= ~GPIP_GPDAC_CH_A_SEL_MASK;
+    regval1 &= ~GPIP_GPDAC_CH_B_SEL_MASK;
+
+    regval2 = getreg32(DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+    if (enable) {
+        if (getreg32(reg_base + GLB_GPDAC_ACTRL_OFFSET) & (GLB_GPDAC_A_EN | GLB_GPDAC_IOA_EN)) {
+            regval1 |= (1 << GPIP_GPDAC_CH_A_SEL_SHIFT);
+            flag++;
+        }
+
+        if (getreg32(reg_base + GLB_GPDAC_BCTRL_OFFSET) & (GLB_GPDAC_B_EN | GLB_GPDAC_IOB_EN)) {
+            regval1 |= (1 << GPIP_GPDAC_CH_B_SEL_SHIFT);
+            flag++;
+        }
+
+        if (flag == 1) {
+            regval2 |= (0 << GPIP_GPDAC_DMA_FORMAT_SHIFT);
+        } else {
+            regval2 |= (1 << GPIP_GPDAC_DMA_FORMAT_SHIFT);
+        }
+        regval2 |= GPIP_GPDAC_DMA_TX_EN;
+    } else {
+        regval2 &= ~GPIP_GPDAC_DMA_TX_EN;
+    }
+    putreg32(regval2, DAC_GPIP_BASE + GPIP_GPDAC_DMA_CONFIG_OFFSET);
+    putreg32(regval1, DAC_GPIP_BASE + GPIP_GPDAC_CONFIG_OFFSET);
+}
+
+void bflb_dac_set_value(struct bflb_device_s *dev, uint8_t ch, uint16_t value)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + GLB_GPDAC_DATA_OFFSET);
+
+    if (ch & DAC_CHANNEL_A) {
+        regval &= ~GLB_GPDAC_A_DATA_MASK;
+        regval |= (value << GLB_GPDAC_A_DATA_SHIFT);
+    }
+
+    if (ch & DAC_CHANNEL_B) {
+        regval &= ~GLB_GPDAC_B_DATA_MASK;
+        regval |= (value << GLB_GPDAC_B_DATA_SHIFT);
+    }
+
+    putreg32(regval, reg_base + GLB_GPDAC_DATA_OFFSET);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dbi.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dbi.c
new file mode 100755
index 0000000000..c102f40ede
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dbi.c
@@ -0,0 +1,799 @@
+#include "bflb_dbi.h"
+#include "bflb_clock.h"
+#include "hardware/dbi_reg.h"
+
+#if (DBI_YUV_SUPPORT)
+/* YUV to RGB parameter list, do not modify. */
+
+#define YUV_PRE_OFFSET_0  0
+#define YUV_PRE_OFFSET_1  0x180
+#define YUV_PRE_OFFSET_2  0x180
+
+#define YUV_POST_OFFSET_0 0
+#define YUV_POST_OFFSET_1 0
+#define YUV_POST_OFFSET_2 0
+
+#define YUV_MATRIX00      0x200
+#define YUV_MATRIX01      0
+#define YUV_MATRIX02      0x2ce
+
+#define YUV_MATRIX10      0x200
+#define YUV_MATRIX11      0xf50
+#define YUV_MATRIX12      0xe92
+
+#define YUV_MATRIX20      0x200
+#define YUV_MATRIX21      0x38b
+#define YUV_MATRIX22      0
+
+#endif
+
+void bflb_dbi_init(struct bflb_device_s *dev, const struct bflb_dbi_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t div;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+
+    /* disable DBI transaction */
+    regval &= ~DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* dbi work mode select */
+    regval &= ~DBI_CR_DBI_SEL_MASK;
+    regval |= config->dbi_mode << DBI_CR_DBI_SEL_SHIFT;
+
+    /* clock phase and polarity cfg */
+    switch (config->clk_mode) {
+        case DBI_CLOCK_MODE_0:
+            /* CPOL=0 CHPHA=0 */
+            regval &= ~DBI_CR_DBI_SCL_POL;
+            regval |= DBI_CR_DBI_SCL_PH;
+            break;
+        case DBI_CLOCK_MODE_1:
+            /* CPOL=0 CHPHA=1 */
+            regval &= ~DBI_CR_DBI_SCL_POL;
+            regval &= ~DBI_CR_DBI_SCL_PH;
+            break;
+        case DBI_CLOCK_MODE_2:
+            /* CPOL=1 CHPHA=0 */
+            regval |= DBI_CR_DBI_SCL_POL;
+            regval |= DBI_CR_DBI_SCL_PH;
+            break;
+        case DBI_CLOCK_MODE_3:
+            /* CPOL=1 CHPHA=1 */
+            regval |= DBI_CR_DBI_SCL_POL;
+            regval &= ~DBI_CR_DBI_SCL_PH;
+            break;
+        default:
+            break;
+    }
+
+    /* disable pixel data continuous transfer mode (CS) */
+    regval &= ~DBI_CR_DBI_CONT_EN;
+
+    /* disable dummy between command phase and data phase */
+    regval &= ~DBI_CR_DBI_DMY_EN;
+
+    /* CS will stay asserted before FIFO is empty */
+#if (DBI_QSPI_SUPPORT)
+    if (config->dbi_mode == DBI_MODE_EX_QSPI) {
+        /* The CS of the qspi must be asserted in a single transaction */
+        regval |= DBI_CR_DBI_CS_STRETCH;
+    } else
+#endif
+    {
+        /* Other modes don't care */
+        regval &= ~DBI_CR_DBI_CS_STRETCH;
+    }
+
+    /* enable command phase */
+    regval |= DBI_CR_DBI_CMD_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* clock cfg */
+    /* integer frequency segmentation by rounding */
+    div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_DBI, dev->idx) / 2 * 10 / config->clk_freq_hz + 5) / 10;
+    div = (div) ? (div - 1) : 0;
+    div = (div > 0xff) ? 0xff : div;
+    regval = 0;
+    regval |= div << DBI_CR_DBI_PRD_S_SHIFT;
+    regval |= div << DBI_CR_DBI_PRD_I_SHIFT;
+    regval |= div << DBI_CR_DBI_PRD_D_PH_0_SHIFT;
+    regval |= div << DBI_CR_DBI_PRD_D_PH_1_SHIFT;
+    putreg32(regval, reg_base + DBI_PRD_OFFSET);
+
+    /* dbi output pixel format cfg */
+    regval = getreg32(reg_base + DBI_PIX_CNT_OFFSET);
+    if (config->pixel_output_format == DBI_PIXEL_OUTPUT_FORMAT_RGB_565) {
+        regval &= ~DBI_CR_DBI_PIX_FORMAT;
+    } else {
+        regval |= DBI_CR_DBI_PIX_FORMAT;
+    }
+    putreg32(regval, reg_base + DBI_PIX_CNT_OFFSET);
+
+    /* dbi input pixel format */
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+    regval &= ~DBI_FIFO_FORMAT_MASK;
+    regval |= config->pixel_input_format << DBI_FIFO_FORMAT_SHIFT;
+
+    /* clear fifo */
+    regval |= DBI_TX_FIFO_CLR;
+
+    /* disable YUV mode */
+    regval &= ~DBI_FIFO_YUV_MODE;
+
+    /* disable dma mode */
+    regval &= ~DBI_DMA_TX_EN;
+    putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+    /* tx fifo threshold cfg */
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+    regval &= ~DBI_TX_FIFO_TH_MASK;
+    regval |= (config->tx_fifo_threshold << DBI_TX_FIFO_TH_SHIFT) & DBI_TX_FIFO_TH_MASK;
+    putreg32(regval, reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+
+#if (DBI_QSPI_SUPPORT)
+    regval = getreg32(reg_base + DBI_QSPI_CONFIG_OFFSET);
+
+    /* cmd wire */
+    if (config->cmd_wire_mode) {
+        regval |= DBI_CR_QSPI_CMD_4B;
+    } else {
+        regval &= ~DBI_CR_QSPI_CMD_4B;
+    }
+
+    /* address wire */
+    if (config->addr_wire_mode) {
+        regval |= DBI_CR_QSPI_ADR_4B;
+    } else {
+        regval &= ~DBI_CR_QSPI_ADR_4B;
+    }
+
+    /* data/pixel wire */
+    if (config->data_wire_mode) {
+        regval |= DBI_CR_QSPI_DAT_4B;
+    } else {
+        regval &= ~DBI_CR_QSPI_DAT_4B;
+    }
+
+    putreg32(regval, reg_base + DBI_QSPI_CONFIG_OFFSET);
+#endif
+
+#if (DBI_YUV_SUPPORT)
+    /* YUV to RGB parameter list. */
+    regval = 0;
+    regval |= (YUV_PRE_OFFSET_0 << DBI_CR_Y2R_PRE_0_SHIFT) & DBI_CR_Y2R_PRE_0_MASK;
+    regval |= (YUV_PRE_OFFSET_1 << DBI_CR_Y2R_PRE_1_SHIFT) & DBI_CR_Y2R_PRE_1_MASK;
+    regval |= (YUV_PRE_OFFSET_2 << DBI_CR_Y2R_PRE_2_SHIFT) & DBI_CR_Y2R_PRE_2_MASK;
+    regval |= DBI_CR_Y2R_EN;
+    putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_0_OFFSET);
+
+    regval = 0;
+    regval |= (YUV_POST_OFFSET_0 << DBI_CR_Y2R_POS_0_SHIFT) & DBI_CR_Y2R_POS_0_MASK;
+    regval |= (YUV_POST_OFFSET_1 << DBI_CR_Y2R_POS_1_SHIFT) & DBI_CR_Y2R_POS_1_MASK;
+    regval |= (YUV_POST_OFFSET_2 << DBI_CR_Y2R_POS_2_SHIFT) & DBI_CR_Y2R_POS_2_MASK;
+    putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_1_OFFSET);
+
+    regval = 0;
+    regval |= (YUV_MATRIX00 << DBI_CR_Y2R_MTX_00_SHIFT) & DBI_CR_Y2R_MTX_00_MASK;
+    regval |= (YUV_MATRIX01 << DBI_CR_Y2R_MTX_01_SHIFT) & DBI_CR_Y2R_MTX_01_MASK;
+    regval |= ((YUV_MATRIX02 & 0x0ff) << DBI_CR_Y2R_MTX_02_L_SHIFT) & DBI_CR_Y2R_MTX_02_L_MASK;
+    putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_2_OFFSET);
+
+    regval = 0;
+    regval |= (((YUV_MATRIX02 & 0xf00) >> 8) << DBI_CR_Y2R_MTX_02_U_SHIFT) & DBI_CR_Y2R_MTX_02_U_MASK;
+    regval |= (YUV_MATRIX10 << DBI_CR_Y2R_MTX_10_SHIFT) & DBI_CR_Y2R_MTX_10_MASK;
+    regval |= (YUV_MATRIX11 << DBI_CR_Y2R_MTX_11_SHIFT) & DBI_CR_Y2R_MTX_11_MASK;
+    regval |= ((YUV_MATRIX12 & 0x00f) << DBI_CR_Y2R_MTX_12_L_SHIFT) & DBI_CR_Y2R_MTX_12_L_MASK;
+    putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_3_OFFSET);
+
+    regval = 0;
+    regval |= (((YUV_MATRIX12 & 0xff0) >> 4) << DBI_CR_Y2R_MTX_12_U_SHIFT) & DBI_CR_Y2R_MTX_12_U_MASK;
+    regval |= (YUV_MATRIX20 << DBI_CR_Y2R_MTX_20_SHIFT) & DBI_CR_Y2R_MTX_20_MASK;
+    regval |= (YUV_MATRIX21 << DBI_CR_Y2R_MTX_21_SHIFT) & DBI_CR_Y2R_MTX_21_MASK;
+    putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_4_OFFSET);
+
+    regval = 0;
+    regval |= (YUV_MATRIX22 << DBI_CR_Y2R_MTX_22_SHIFT) & DBI_CR_Y2R_MTX_22_MASK;
+    putreg32(regval, reg_base + DBI_YUV_RGB_CONFIG_5_OFFSET);
+#endif
+}
+
+void bflb_dbi_deinit(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* disable DBI transaction */
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+    regval &= ~DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* clear fifo */
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+    regval |= DBI_TX_FIFO_CLR;
+    putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+}
+
+#if DBI_QSPI_SUPPORT
+void bflb_dbi_qspi_set_addr(struct bflb_device_s *dev, uint8_t addr_byte_size, uint32_t addr_val)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    addr_byte_size = addr_byte_size ? (addr_byte_size - 1) : addr_byte_size;
+
+    /* set address size */
+    regval = getreg32(reg_base + DBI_QSPI_CONFIG_OFFSET);
+    regval &= ~DBI_CR_QSPI_ADR_BC_MASK;
+    regval |= (addr_byte_size << DBI_CR_QSPI_ADR_BC_SHIFT) & DBI_CR_QSPI_ADR_BC_MASK;
+    putreg32(regval, reg_base + DBI_QSPI_CONFIG_OFFSET);
+
+    /* set address value */
+    putreg32(addr_val, reg_base + DBI_QSPI_ADR_OFFSET);
+}
+#endif
+
+static void bflb_dbi_fill_fifo(struct bflb_device_s *dev, uint32_t words_cnt, uint32_t *data_buff)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t fifo_cnt;
+
+    reg_base = dev->reg_base;
+
+    for (; words_cnt > 0;) {
+        /* get fifo available count */
+        regval = getreg32(reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+        fifo_cnt = (regval & DBI_TX_FIFO_CNT_MASK) >> DBI_TX_FIFO_CNT_SHIFT;
+
+        if (fifo_cnt) {
+            fifo_cnt = (fifo_cnt > words_cnt) ? words_cnt : fifo_cnt;
+            words_cnt -= fifo_cnt;
+        } else {
+            continue;
+        }
+
+        /* fill fifo */
+        for (; fifo_cnt > 0; fifo_cnt--, data_buff++) {
+            putreg32(*data_buff, reg_base + DBI_FIFO_WDATA_OFFSET);
+        }
+    }
+}
+
+static uint32_t bflb_dbi_get_words_cnt_form_pixel(struct bflb_device_s *dev, uint32_t pixle_cnt)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t words_cnt;
+    uint8_t pixel_input_format;
+
+    reg_base = dev->reg_base;
+
+    /* get fifo input pixel_format */
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+    pixel_input_format = (regval & DBI_FIFO_FORMAT_MASK) >> DBI_FIFO_FORMAT_SHIFT;
+
+    switch (pixel_input_format) {
+        /* 32-bit/pixel format list */
+        case DBI_PIXEL_INPUT_FORMAT_NBGR_8888:
+        case DBI_PIXEL_INPUT_FORMAT_NRGB_8888:
+        case DBI_PIXEL_INPUT_FORMAT_BGRN_8888:
+        case DBI_PIXEL_INPUT_FORMAT_RGBN_8888:
+            words_cnt = pixle_cnt;
+            break;
+
+        /* 24-bit/pixel format list */
+        case DBI_PIXEL_INPUT_FORMAT_RGB_888:
+        case DBI_PIXEL_INPUT_FORMAT_BGR_888:
+            words_cnt = (pixle_cnt * 3 + 3) / 4;
+            break;
+
+        /* 16-bit/pixel format list */
+        case DBI_PIXEL_INPUT_FORMAT_BGR_565:
+        case DBI_PIXEL_INPUT_FORMAT_RGB_565:
+            words_cnt = (pixle_cnt + 1) / 2;
+            break;
+
+        default:
+            words_cnt = 0;
+            break;
+    }
+
+    return words_cnt;
+}
+
+int bflb_dbi_send_cmd_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* null */
+    if (data_len && data_buff == NULL) {
+        return 0;
+    }
+
+    /* disable DBI transaction */
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+    regval &= ~DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    if (((regval & DBI_CR_DBI_CMD_EN) == 0) && (data_len == 0)) {
+        /* There is no data or command phase, nothing to do */
+        return 0;
+    }
+
+    /* normal data mode  */
+    regval &= ~DBI_CR_DBI_DAT_TP;
+
+    /* write mode  */
+    regval |= DBI_CR_DBI_DAT_WR;
+
+    /* set data len */
+    if (data_len) {
+        regval |= DBI_CR_DBI_DAT_EN;
+        regval &= ~DBI_CR_DBI_DAT_BC_MASK;
+        regval |= ((data_len - 1) << DBI_CR_DBI_DAT_BC_SHIFT) & DBI_CR_DBI_DAT_BC_MASK;
+    } else {
+        regval &= ~DBI_CR_DBI_DAT_EN;
+    }
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* set cmd */
+    if (regval & DBI_CR_DBI_CMD_EN) {
+        regval = getreg32(reg_base + DBI_CMD_OFFSET);
+        regval &= ~DBI_CR_DBI_CMD_MASK;
+        regval |= cmd << DBI_CR_DBI_CMD_SHIFT;
+        putreg32(regval, reg_base + DBI_CMD_OFFSET);
+    }
+
+    /* clear fifo */
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+    regval |= DBI_TX_FIFO_CLR;
+    putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+    /* clear complete interrupt  */
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    regval |= DBI_CR_DBI_END_CLR;
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+    /* first fill some data into the fifo */
+    if (data_len) {
+        if (data_len <= SPI_FIFO_NUM_MAX * 4) {
+            bflb_dbi_fill_fifo(dev, (data_len + 3) / 4, (uint32_t *)data_buff);
+            data_len = 0;
+        } else {
+            bflb_dbi_fill_fifo(dev, SPI_FIFO_NUM_MAX, (uint32_t *)data_buff);
+            data_len -= SPI_FIFO_NUM_MAX * 4;
+        }
+    }
+
+    /* trigger the transaction */
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+    regval |= DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* Fill the rest of the data into the fifo */
+    if (data_len) {
+        bflb_dbi_fill_fifo(dev, (data_len + 3) / 4, (uint32_t *)data_buff);
+    }
+
+    /* Wait transfer complete */
+    do {
+        regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    } while ((regval & DBI_END_INT) == 0);
+
+    /* clear end int */
+    regval |= DBI_CR_DBI_END_CLR;
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+    return 0;
+}
+
+int bflb_dbi_send_cmd_read_data(struct bflb_device_s *dev, uint8_t cmd, uint8_t data_len, uint8_t *data_buff)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* disable DBI transaction */
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+    regval &= ~DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    if (((regval & DBI_CR_DBI_CMD_EN) == 0) && (data_len == 0)) {
+        /* There is no data or command phase, nothing to do */
+        return 0;
+    }
+
+    /* normal data mode  */
+    regval &= ~DBI_CR_DBI_DAT_TP;
+
+    /* read mode  */
+    regval &= ~DBI_CR_DBI_DAT_WR;
+
+    /* set data len */
+    if (data_len) {
+        regval |= DBI_CR_DBI_DAT_EN;
+        regval &= ~DBI_CR_DBI_DAT_BC_MASK;
+        regval |= ((data_len - 1) << DBI_CR_DBI_DAT_BC_SHIFT) & DBI_CR_DBI_DAT_BC_MASK;
+    } else {
+        regval &= ~DBI_CR_DBI_DAT_EN;
+    }
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* set cmd */
+    if (regval & DBI_CR_DBI_CMD_EN) {
+        regval = getreg32(reg_base + DBI_CMD_OFFSET);
+        regval &= ~DBI_CR_DBI_CMD_MASK;
+        regval |= cmd << DBI_CR_DBI_CMD_SHIFT;
+        putreg32(regval, reg_base + DBI_CMD_OFFSET);
+    }
+
+    /* clear fifo */
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+    regval |= DBI_TX_FIFO_CLR;
+    putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+    /* clear complete interrupt  */
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    regval |= DBI_CR_DBI_END_CLR;
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+    /* trigger the transaction */
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+    regval |= DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* Wait transfer complete */
+    do {
+        regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    } while ((regval & DBI_END_INT) == 0);
+
+    /* clear end int */
+    regval |= DBI_CR_DBI_END_CLR;
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+    /* Null pointer error */
+    if (data_buff == NULL) {
+        return 0;
+    }
+
+    /* copy data to buff */
+    regval = getreg32(reg_base + DBI_RDATA_0_OFFSET);
+    for (uint8_t i = 0; (data_len > 0) && (i < 4); i++, data_len--) {
+        *data_buff = (uint8_t)regval;
+        data_buff++;
+        regval >>= 8;
+    }
+    regval = getreg32(reg_base + DBI_RDATA_1_OFFSET);
+    for (uint8_t i = 0; (data_len > 0) && (i < 4); i++, data_len--) {
+        *data_buff = (uint8_t)regval;
+        data_buff++;
+        regval >>= 8;
+    }
+
+    return 0;
+}
+
+int bflb_dbi_send_cmd_pixel(struct bflb_device_s *dev, uint8_t cmd, uint32_t pixel_cnt, void *pixel_buff)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* disable DBI transaction */
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+    regval &= ~DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    if (((regval & DBI_CR_DBI_CMD_EN) == 0) && (pixel_cnt == 0)) {
+        /* There is no data or command phase, nothing to do */
+        return 0;
+    }
+
+    /* pixel mode  */
+    regval |= DBI_CR_DBI_DAT_TP;
+
+    /* write mode  */
+    regval |= DBI_CR_DBI_DAT_WR;
+
+    /* pixle data phase enable */
+    if (pixel_cnt) {
+        regval |= DBI_CR_DBI_DAT_EN;
+    } else {
+        regval &= ~DBI_CR_DBI_DAT_EN;
+    }
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* set cmd  */
+    if (regval & DBI_CR_DBI_CMD_EN) {
+        regval = getreg32(reg_base + DBI_CMD_OFFSET);
+        regval &= ~DBI_CR_DBI_CMD_MASK;
+        regval |= cmd << DBI_CR_DBI_CMD_SHIFT;
+        putreg32(regval, reg_base + DBI_CMD_OFFSET);
+    }
+
+    /* pixel cnt */
+    if (pixel_cnt) {
+        regval = getreg32(reg_base + DBI_PIX_CNT_OFFSET);
+        regval &= ~DBI_CR_DBI_PIX_CNT_MASK;
+        regval |= ((pixel_cnt - 1) << DBI_CR_DBI_PIX_CNT_SHIFT) & DBI_CR_DBI_PIX_CNT_MASK;
+        putreg32(regval, reg_base + DBI_PIX_CNT_OFFSET);
+    }
+
+    /* clear fifo */
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+    regval |= DBI_TX_FIFO_CLR;
+    putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+
+    /* clear complete interrupt  */
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    regval |= DBI_CR_DBI_END_CLR;
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+    /* trigger the transaction */
+    regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+    regval |= DBI_CR_DBI_EN;
+    putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+
+    /* No need to fill in fifo, for DMA mode */
+    if (pixel_buff == NULL) {
+        return 0;
+    }
+
+    /* fill the data into the fifo, can only be used in non-DMA mode */
+    bflb_dbi_fill_fifo(dev, bflb_dbi_get_words_cnt_form_pixel(dev, pixel_cnt), (uint32_t *)pixel_buff);
+
+    /* Wait transfer complete */
+    do {
+        regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    } while ((regval & DBI_END_INT) == 0);
+
+    /* clear end int */
+    regval |= DBI_CR_DBI_END_CLR;
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+
+    return 0;
+}
+
+void bflb_dbi_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= DBI_DMA_TX_EN;
+    } else {
+        regval &= ~DBI_DMA_TX_EN;
+    }
+    putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_dbi_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    if (mask) {
+        regval |= DBI_CR_DBI_TXF_MASK;
+    } else {
+        regval &= ~DBI_CR_DBI_TXF_MASK;
+    }
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+void bflb_dbi_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    if (mask) {
+        regval |= DBI_CR_DBI_END_MASK;
+    } else {
+        regval &= ~DBI_CR_DBI_END_MASK;
+    }
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+void bflb_dbi_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+    if (mask) {
+        regval |= DBI_CR_DBI_FER_MASK;
+    } else {
+        regval &= ~DBI_CR_DBI_FER_MASK;
+    }
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+uint32_t bflb_dbi_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t int_sts;
+
+    reg_base = dev->reg_base;
+    int_sts = 0;
+
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+
+    /* transfer completion interrupt */
+    if (regval & DBI_END_INT) {
+        int_sts |= DBI_INTSTS_TC;
+    }
+
+    /* fifo threshold interrupt */
+    if (regval & DBI_TXF_INT) {
+        int_sts |= SPI_INTSTS_TX_FIFO;
+    }
+
+    /* fifo error (underflow or overflow) interrupt */
+    if (regval & DBI_FER_INT) {
+        int_sts |= SPI_INTSTS_FIFO_ERR;
+    }
+
+    return int_sts;
+}
+
+void bflb_dbi_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + DBI_INT_STS_OFFSET);
+
+    /* transfer completion interrupt */
+    if (int_clear & DBI_INTCLR_TC) {
+        regval |= DBI_CR_DBI_END_CLR;
+    }
+
+    putreg32(regval, reg_base + DBI_INT_STS_OFFSET);
+}
+
+int bflb_dbi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case DBI_CMD_CLEAR_TX_FIFO:
+            /* clear fifo */
+            regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+            regval |= DBI_TX_FIFO_CLR;
+            putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case DBI_CMD_GET_TX_FIFO_CNT:
+            /* get fifo available count */
+            regval = getreg32(reg_base + DBI_FIFO_CONFIG_1_OFFSET);
+            ret = (regval & DBI_TX_FIFO_CNT_MASK) >> DBI_TX_FIFO_CNT_SHIFT;
+            break;
+
+        case DBI_CMD_MASK_CMD_PHASE:
+            /* mask command phase, arg use true or false,
+               true: no command phase, false: command will be sent
+               don't-care if QSPI mode is selected (command always sent)
+            */
+            regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+#if (DBI_QSPI_SUPPORT)
+            /* the setting is not valid for the qspi mode */
+            if ((regval & DBI_CR_DBI_SEL_MASK) >> DBI_CR_DBI_SEL_SHIFT == DBI_MODE_EX_QSPI) {
+                break;
+            }
+#endif
+            if (arg) {
+                regval &= ~DBI_CR_DBI_CMD_EN;
+            } else {
+                regval |= DBI_CR_DBI_CMD_EN;
+            }
+            putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+            break;
+
+        case DBI_CMD_CS_CONTINUE:
+            /* set CS continue mode, arg use true or false */
+            regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+            if (arg) {
+                regval |= DBI_CR_DBI_CONT_EN;
+            } else {
+                regval &= ~DBI_CR_DBI_CONT_EN;
+            }
+            putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+            break;
+
+        case DBI_CMD_SET_DUMMY_CNT:
+            /* set dummy cycle(s) between command phase and data phase
+               arg range: 0 ~ 16,
+               don't-care if QSPI mode is selected (no dummy cycle)
+             */
+            regval = getreg32(reg_base + DBI_CONFIG_OFFSET);
+#if (DBI_QSPI_SUPPORT)
+            /* the setting is not valid for the qspi mode */
+            if ((regval & DBI_CR_DBI_SEL_MASK) >> DBI_CR_DBI_SEL_SHIFT == DBI_MODE_EX_QSPI) {
+                break;
+            }
+#endif
+            if (arg) {
+                regval |= DBI_CR_DBI_DMY_EN;
+                regval &= ~DBI_CR_DBI_DMY_CNT_MASK;
+                regval |= ((arg - 1) << DBI_CR_DBI_DMY_CNT_SHIFT) & DBI_CR_DBI_DMY_CNT_MASK;
+            } else {
+                regval &= ~DBI_CR_DBI_DMY_EN;
+            }
+            putreg32(regval, reg_base + DBI_CONFIG_OFFSET);
+            break;
+
+        case DBI_CMD_GET_SIZE_OF_PIXEL_CNT:
+            /* gets the pixel_data size(byte), arg: pixel number */
+            ret = bflb_dbi_get_words_cnt_form_pixel(dev, arg) * 4;
+            break;
+
+        case DBI_CMD_INPUT_PIXEL_FORMAT:
+            /* dbi input pixel format, arg use @ref DBI_PIXEL_INPUT_FORMAT */
+            regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+            regval &= ~DBI_FIFO_FORMAT_MASK;
+            regval |= (arg << DBI_FIFO_FORMAT_SHIFT) & DBI_FIFO_FORMAT_MASK;
+            putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case DBI_CMD_OUTPUT_PIXEL_FORMAT:
+            /* dbi output pixel format, arg use @ref DBI_PIXEL_OUTPUT_FORMAT */
+            regval = getreg32(reg_base + DBI_PIX_CNT_OFFSET);
+            if (arg == DBI_PIXEL_OUTPUT_FORMAT_RGB_565) {
+                regval &= ~DBI_CR_DBI_PIX_FORMAT;
+            } else if (arg == DBI_PIXEL_OUTPUT_FORMAT_RGB_888) {
+                regval |= DBI_CR_DBI_PIX_FORMAT;
+            }
+            putreg32(regval, reg_base + DBI_PIX_CNT_OFFSET);
+            break;
+
+#if (DBI_YUV_SUPPORT)
+        case DBI_CMD_YUV_TO_RGB_ENABLE:
+            /* yuv to rgb cfg, arg use true or false */
+            regval = getreg32(reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+            if (arg) {
+                regval |= DBI_FIFO_YUV_MODE;
+            } else {
+                regval &= ~DBI_FIFO_YUV_MODE;
+            }
+            putreg32(regval, reg_base + DBI_FIFO_CONFIG_0_OFFSET);
+            break;
+#endif
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+
+    return ret;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dma.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dma.c
new file mode 100755
index 0000000000..25a2532731
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_dma.c
@@ -0,0 +1,455 @@
+#include "bflb_dma.h"
+#include "bflb_l1c.h"
+#include "hardware/dma_reg.h"
+
+struct bflb_dma_irq_callback {
+    void (*handler)(void *arg);
+    void *arg;
+};
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+const uint32_t dma_base[] = { 0x4000C000 };
+struct bflb_dma_irq_callback dma_callback[1][8];
+#elif defined(BL616)
+const uint32_t dma_base[] = { 0x2000C000 };
+struct bflb_dma_irq_callback dma_callback[1][4];
+#elif defined(BL606P) || defined(BL808)
+const uint32_t dma_base[] = { 0x2000C000, 0x20071000, 0x30001000 };
+struct bflb_dma_irq_callback dma_callback[3][8];
+#elif defined(BL628)
+const uint32_t dma_base[] = { 0x20081000 };
+struct bflb_dma_irq_callback dma_callback[1][8];
+#endif
+
+void dma0_isr(int irq, void *arg)
+{
+    uint32_t regval;
+
+    regval = getreg32(dma_base[0] + DMA_INTTCSTATUS_OFFSET);
+    putreg32(regval, dma_base[0] + DMA_INTTCCLEAR_OFFSET);
+
+    for (uint8_t i = 0; i < 8; i++) {
+        if (regval & (1 << i)) {
+            dma_callback[0][i].handler(dma_callback[0][i].arg);
+        }
+    }
+}
+
+#if defined(BL606P) || defined(BL808)
+void dma1_isr(int irq, void *arg)
+{
+    uint32_t regval;
+
+    regval = getreg32(dma_base[1] + DMA_INTTCSTATUS_OFFSET);
+    putreg32(regval, dma_base[1] + DMA_INTTCCLEAR_OFFSET);
+
+    for (uint8_t i = 0; i < 8; i++) {
+        if (regval & (1 << i)) {
+            dma_callback[1][i].handler(dma_callback[1][i].arg);
+        }
+    }
+}
+
+void dma2_isr(int irq, void *arg)
+{
+    uint32_t regval;
+
+    regval = getreg32(dma_base[2] + DMA_INTTCSTATUS_OFFSET);
+    putreg32(regval, dma_base[2] + DMA_INTTCCLEAR_OFFSET);
+
+    for (uint8_t i = 0; i < 8; i++) {
+        if (regval & (1 << i)) {
+            dma_callback[1][i].handler(dma_callback[2][i].arg);
+        }
+    }
+}
+#endif
+
+void bflb_dma_channel_init(struct bflb_device_s *dev, const struct bflb_dma_channel_config_s *config)
+{
+    uint32_t regval;
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    /* dma global enable */
+    regval = getreg32(dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
+    regval |= DMA_E;
+    putreg32(regval, dma_base[dev->idx] + DMA_TOP_CONFIG_OFFSET);
+
+    /* dma channel disable */
+    regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+    regval &= ~DMA_E;
+    putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+#if defined(BL602)
+    regval = 0;
+#else
+    regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+    regval &= DMA_DST_ADD_MODE | DMA_DST_MIN_MODE | DMA_FIX_CNT_MASK;
+#endif
+
+    if (config->src_addr_inc) {
+        regval |= DMA_SI;
+    }
+    if (config->dst_addr_inc) {
+        regval |= DMA_DI;
+    }
+
+    regval |= (config->src_width << DMA_SWIDTH_SHIFT);
+    regval |= (config->dst_width << DMA_DWIDTH_SHIFT);
+    regval |= (config->src_burst_count << DMA_SBSIZE_SHIFT);
+    regval |= (config->dst_burst_count << DMA_DBSIZE_SHIFT);
+    putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+
+    regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+    regval &= ~DMA_SRCPERIPHERAL_MASK;
+    regval &= ~DMA_DSTPERIPHERAL_MASK;
+    regval &= ~DMA_FLOWCNTRL_MASK;
+    regval &= ~DMA_LLICOUNTER_MASK;
+    regval |= (config->src_req << DMA_SRCPERIPHERAL_SHIFT);
+    regval |= (config->dst_req << DMA_DSTPERIPHERAL_SHIFT);
+    regval |= (config->direction << DMA_FLOWCNTRL_SHIFT);
+    putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+    /* enable dma error and tc interrupt */
+    regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+    regval |= (DMA_ITC | DMA_IE);
+    putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+    regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+    regval &= ~DMA_I;
+    putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+
+    /* clear irq status */
+    putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTTCCLEAR_OFFSET);
+    putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTERRCLR_OFFSET);
+
+#if (defined(BL606P) || defined(BL808)) && (defined(CPU_M0) || defined(CPU_LP))
+    bflb_irq_attach(31, dma0_isr, NULL);
+    bflb_irq_attach(32, dma1_isr, NULL);
+    bflb_irq_enable(31);
+    bflb_irq_enable(32);
+#elif (defined(BL606P) || defined(BL808)) && defined(CPU_D0)
+    bflb_irq_attach(40, dma2_isr, NULL);
+    bflb_irq_attach(41, dma2_isr, NULL);
+    bflb_irq_attach(42, dma2_isr, NULL);
+    bflb_irq_attach(43, dma2_isr, NULL);
+    bflb_irq_attach(44, dma2_isr, NULL);
+    bflb_irq_attach(45, dma2_isr, NULL);
+    bflb_irq_attach(46, dma2_isr, NULL);
+    bflb_irq_attach(47, dma2_isr, NULL);
+    bflb_irq_enable(40);
+    bflb_irq_enable(41);
+    bflb_irq_enable(42);
+    bflb_irq_enable(43);
+    bflb_irq_enable(44);
+    bflb_irq_enable(45);
+    bflb_irq_enable(46);
+    bflb_irq_enable(47);
+#else
+    bflb_irq_attach(dev->irq_num, dma0_isr, NULL);
+    bflb_irq_enable(dev->irq_num);
+#endif
+}
+
+void bflb_dma_lli_config(struct bflb_device_s *dev, struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t lli_count, uint32_t src_addr, uint32_t dst_addr, uint32_t transfer_offset, uint32_t last_transfer_len)
+{
+    uint32_t channel_base;
+    union bflb_dma_lli_control_s dma_ctrl_cfg;
+
+    channel_base = dev->reg_base;
+
+    dma_ctrl_cfg = (union bflb_dma_lli_control_s)getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+
+    dma_ctrl_cfg.bits.TransferSize = 4064;
+    dma_ctrl_cfg.bits.I = 0;
+
+    /* nbytes will be integer multiple of 4064*n or 4064*2*n or 4064*4*n,(n>0) */
+    for (uint32_t i = 0; i < lli_count; i++) {
+        lli_pool[i].src_addr = src_addr;
+        lli_pool[i].dst_addr = dst_addr;
+        lli_pool[i].nextlli = 0;
+
+        if (dma_ctrl_cfg.bits.SI) {
+            src_addr += transfer_offset;
+        }
+
+        if (dma_ctrl_cfg.bits.DI) {
+            dst_addr += transfer_offset;
+        }
+
+        if (i == lli_count - 1) {
+            dma_ctrl_cfg.bits.TransferSize = last_transfer_len;
+            dma_ctrl_cfg.bits.I = 1;
+        }
+
+        if (i) {
+            lli_pool[i - 1].nextlli = (uint32_t)(uintptr_t)&lli_pool[i];
+        }
+
+        lli_pool[i].control = dma_ctrl_cfg;
+    }
+}
+
+int bflb_dma_channel_lli_reload(struct bflb_device_s *dev, struct bflb_dma_channel_lli_pool_s *lli_pool, uint32_t max_lli_count, struct bflb_dma_channel_lli_transfer_s *transfer, uint32_t count)
+{
+    uint32_t channel_base;
+    uint32_t actual_transfer_offset = 0;
+    uint32_t actual_transfer_len = 0;
+    uint32_t last_transfer_len = 0;
+    uint32_t current_lli_count = 0;
+    uint32_t lli_count_used_offset = 0;
+    union bflb_dma_lli_control_s dma_ctrl_cfg;
+
+    channel_base = dev->reg_base;
+
+    dma_ctrl_cfg = (union bflb_dma_lli_control_s)getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+
+    switch (dma_ctrl_cfg.bits.SWidth) {
+        case DMA_DATA_WIDTH_8BIT:
+            actual_transfer_offset = 4064;
+            break;
+        case DMA_DATA_WIDTH_16BIT:
+            actual_transfer_offset = 4064 << 1;
+            break;
+        case DMA_DATA_WIDTH_32BIT:
+            actual_transfer_offset = 4064 << 2;
+            break;
+        default:
+            break;
+    }
+
+    for (size_t i = 0; i < count; i++) {
+        switch (dma_ctrl_cfg.bits.SWidth) {
+            case DMA_DATA_WIDTH_8BIT:
+                actual_transfer_len = transfer[i].nbytes;
+                break;
+            case DMA_DATA_WIDTH_16BIT:
+                if (transfer[i].nbytes % 2) {
+                    return -1;
+                }
+                actual_transfer_len = transfer[i].nbytes >> 1;
+                break;
+            case DMA_DATA_WIDTH_32BIT:
+                if (transfer[i].nbytes % 4) {
+                    return -1;
+                }
+                actual_transfer_len = transfer[i].nbytes >> 2;
+                break;
+
+            default:
+                break;
+        }
+
+        current_lli_count = actual_transfer_len / 4064 + 1;
+        last_transfer_len = actual_transfer_len % 4064;
+
+        /* The maximum transfer capacity of the last node is 4095 */
+        if (current_lli_count > 1 && last_transfer_len < (4095 - 4064)) {
+            current_lli_count--;
+            last_transfer_len += 4064;
+        }
+
+        bflb_dma_lli_config(dev, &lli_pool[lli_count_used_offset], current_lli_count, transfer[i].src_addr, transfer[i].dst_addr, actual_transfer_offset, last_transfer_len);
+        if (i) {
+            lli_pool[lli_count_used_offset - 1].nextlli = (uint32_t)(uintptr_t)&lli_pool[lli_count_used_offset];
+        }
+        lli_count_used_offset += current_lli_count;
+
+        if (lli_count_used_offset > max_lli_count) {
+            return -ENOMEM;
+        }
+    }
+
+    putreg32(lli_pool[0].src_addr, channel_base + DMA_CxSRCADDR_OFFSET);
+    putreg32(lli_pool[0].dst_addr, channel_base + DMA_CxDSTADDR_OFFSET);
+    putreg32(lli_pool[0].nextlli, channel_base + DMA_CxLLI_OFFSET);
+    putreg32(lli_pool[0].control.WORD, channel_base + DMA_CxCONTROL_OFFSET);
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+    /* clean cache, DMA does not pass through the cache */
+    bflb_l1c_dcache_clean_range((uint32_t *)(uintptr_t)lli_pool, sizeof(struct bflb_dma_channel_lli_pool_s) * lli_count_used_offset);
+#endif
+    return lli_count_used_offset;
+}
+
+void bflb_dma_channel_lli_link_head(struct bflb_device_s *dev,
+                                    struct bflb_dma_channel_lli_pool_s *lli_pool,
+                                    uint32_t used_lli_count)
+{
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    lli_pool[used_lli_count - 1].nextlli = (uint32_t)(uintptr_t)&lli_pool[0];
+
+    putreg32(lli_pool[0].nextlli, channel_base + DMA_CxLLI_OFFSET);
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+    /* clean cache, DMA does not pass through the cache */
+    bflb_l1c_dcache_clean_range((uint32_t *)lli_pool, sizeof(struct bflb_dma_channel_lli_pool_s) * used_lli_count);
+#endif
+}
+
+void bflb_dma_channel_start(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    /* dma channel enable */
+    regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+    regval |= DMA_E;
+    putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+}
+
+void bflb_dma_channel_stop(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    /* dma channel disable */
+    regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+    regval &= ~DMA_E;
+    putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+}
+
+bool bflb_dma_channel_isbusy(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+    if (regval & (1 << 0)) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+void bflb_dma_channel_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    if (mask) {
+        regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+        regval |= DMA_ITC;
+        putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+        regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+        regval &= ~DMA_I;
+        putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+    } else {
+        regval = getreg32(channel_base + DMA_CxCONFIG_OFFSET);
+        regval &= ~DMA_ITC;
+        putreg32(regval, channel_base + DMA_CxCONFIG_OFFSET);
+
+        regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+        regval |= DMA_I;
+        putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+    }
+}
+
+void bflb_dma_channel_irq_attach(struct bflb_device_s *dev, void (*callback)(void *arg), void *arg)
+{
+    dma_callback[dev->idx][dev->sub_idx].handler = callback;
+    dma_callback[dev->idx][dev->sub_idx].arg = arg;
+
+    bflb_dma_channel_tcint_mask(dev, false);
+}
+
+void bflb_dma_channel_irq_detach(struct bflb_device_s *dev)
+{
+    dma_callback[dev->idx][dev->sub_idx].handler = NULL;
+    dma_callback[dev->idx][dev->sub_idx].arg = NULL;
+
+    bflb_dma_channel_tcint_mask(dev, true);
+}
+
+bool bflb_dma_channel_get_tcint_status(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+
+    regval = getreg32(dma_base[dev->idx] + DMA_INTTCSTATUS_OFFSET);
+    if (regval & (1 << dev->sub_idx)) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+void bflb_dma_channel_tcint_clear(struct bflb_device_s *dev)
+{
+    putreg32(1 << dev->sub_idx, dma_base[dev->idx] + DMA_INTTCCLEAR_OFFSET);
+}
+
+int bflb_dma_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t regval;
+    uint32_t channel_base;
+
+    channel_base = dev->reg_base;
+
+    switch (cmd) {
+        case DMA_CMD_SET_SRCADDR_INCREMENT:
+            regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+            if (arg) {
+                regval |= DMA_SI;
+            } else {
+                regval &= ~DMA_SI;
+            }
+            putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+            break;
+
+        case DMA_CMD_SET_DSTADDR_INCREMENT:
+            regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+            if (arg) {
+                regval |= DMA_DI;
+            } else {
+                regval &= ~DMA_DI;
+            }
+            putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+            break;
+
+#if !defined(BL602)
+        case DMA_CMD_SET_ADD_MODE:
+            regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+            if (arg) {
+                regval |= DMA_DST_ADD_MODE;
+            } else {
+                regval &= ~DMA_DST_ADD_MODE;
+            }
+            putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+            break;
+
+        case DMA_CMD_SET_REDUCE_MODE:
+            regval = getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+            if (arg) {
+                regval |= DMA_DST_MIN_MODE;
+                regval &= ~DMA_FIX_CNT_MASK;
+                regval |= (arg & 0x7) << DMA_FIX_CNT_SHIFT;
+            } else {
+                regval &= ~DMA_DST_MIN_MODE;
+            }
+            putreg32(regval, channel_base + DMA_CxCONTROL_OFFSET);
+            break;
+#endif
+        case DMA_CMD_SET_LLI_CONFIG:
+            arch_memcpy4((uint32_t *)(channel_base + DMA_CxSRCADDR_OFFSET), (uint32_t *)arg, 4);
+            break;
+        case DMA_CMD_GET_LLI_CONTROL:
+            return getreg32(channel_base + DMA_CxCONTROL_OFFSET);
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ef_ctrl.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ef_ctrl.c
new file mode 100755
index 0000000000..3e858abcdd
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ef_ctrl.c
@@ -0,0 +1,932 @@
+#include "bflb_ef_ctrl.h"
+#include "hardware/ef_ctrl_reg.h"
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_EF_CTRL_BASE ((uint32_t)0x40007000)
+#elif defined(BL616) || defined(BL808) || defined(BL606P)
+#define BFLB_EF_CTRL_BASE ((uint32_t)0x20056000)
+#elif defined(BL628)
+#define BFLB_EF_CTRL_BASE ((uint32_t)0x2000C000)
+#endif
+
+#define EF_CTRL_EFUSE_CYCLE_PROTECT (0xbf << 24)
+#define EF_CTRL_EFUSE_CTRL_PROTECT  (0xbf << 8)
+#define EF_CTRL_OP_MODE_AUTO        0
+#define EF_CTRL_PARA_DFT            0
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EF_CLK   0
+#define EF_CTRL_SAHB_CLK 1
+#endif
+#define EF_CTRL_DFT_TIMEOUT_VAL (160 * 1000)
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define EF_CTRL_EFUSE_R0_SIZE 128
+#elif defined(BL606P) || defined(BL808)
+#define EF_CTRL_EFUSE_R0_SIZE 128
+#define EF_CTRL_EFUSE_R1_SIZE 128
+#elif defined(BL616) || defined(BL628)
+#define EF_CTRL_EFUSE_R0_SIZE 512
+#else
+#define EF_CTRL_EFUSE_R0_SIZE 128
+#endif
+
+#ifndef BOOTROM
+#define EF_CTRL_LOAD_BEFORE_READ_R0 bflb_ef_ctrl_load_efuse_r0(dev)
+#define EF_CTRL_LOAD_BEFORE_READ_R1 bflb_ef_ctrl_load_efuse_r1(dev)
+#else
+#define EF_CTRL_LOAD_BEFORE_READ_R0
+#define EF_CTRL_LOAD_BEFORE_READ_R1
+#endif
+#define EF_CTRL_DATA0_CLEAR bflb_ef_ctrl_clear_data_reg0(dev)
+#define EF_CTRL_DATA1_CLEAR bflb_ef_ctrl_clear_data_reg1(dev)
+
+static int ATTR_TCM_SECTION bflb_ef_ctrl_busy(struct bflb_device_s *dev);
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+extern void bflb_efuse_switch_cpu_clock_save(void);
+extern void bflb_efuse_switch_cpu_clock_restore(void);
+#endif
+
+
+/****************************************************************************/ /**
+ * @brief  Switch efuse region 0 control to AHB clock
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_switch_ahb_clk_r0(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+    uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+    while (bflb_ef_ctrl_busy(dev) == 1) {
+        timeout--;
+        if (timeout == 0) {
+            break;
+        }
+    }
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+              (EF_CTRL_SAHB_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    /* Add delay for CLK to be stable */
+    arch_delay_us(4);
+}
+
+/****************************************************************************/ /**
+ * @brief  Switch efuse region 1 control to AHB clock
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_switch_ahb_clk_r1(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+    uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+    while (bflb_ef_ctrl_busy(dev) == 1) {
+        timeout--;
+        if (timeout == 0) {
+            break;
+        }
+    }
+
+    /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+	   so we select it(them) in ef_if_ctrl_0 */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_1_RW_POS) |
+              (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+    /* Add delay for CLK to be stable */
+    arch_delay_us(4);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Program efuse region 0
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r0(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    /* Select auto mode and select ef clock */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+              (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    /* Program */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+              (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (1 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (1 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    /* Add delay for POR to be stable */
+    arch_delay_us(4);
+
+    /* Trigger */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+              (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (1 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (1 << EF_CTRL_EF_IF_0_RW_POS) |
+              (1 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Program efuse region 1
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_program_efuse_r1(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    /* Select auto mode and select ef clock */
+    /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+	   so we select it(them) in ef_if_ctrl_0 */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_1_RW_POS) |
+              (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+    /* Program */
+    /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+	so we select it(them) in ef_if_ctrl_0 */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (1 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    /* Add delay for POR to be stable */
+    arch_delay_us(4);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+              (1 << EF_CTRL_EF_IF_1_RW_POS) |
+              (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+              (1 << EF_CTRL_EF_IF_1_RW_POS) |
+              (1 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Clear efuse region 0 data register
+ *
+ * @param  dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_clear_data_reg0(struct bflb_device_s *dev)
+{
+    uint32_t *pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + 0x00);
+    uint32_t i = 0;
+
+    /* Switch to AHB clock */
+    bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+
+    /* Clear data */
+    for (i = 0; i < EF_CTRL_EFUSE_R0_SIZE / 4; i++) {
+        pefuse_start[i] = 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear efuse region 1 data register
+ *
+ * @param  dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_clear_data_reg1(struct bflb_device_s *dev)
+{
+    uint32_t *pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + EF_CTRL_EFUSE_R0_SIZE);
+    uint32_t i = 0;
+
+    /* Switch to AHB clock */
+    bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+
+    /* Clear data */
+    for (i = 0; i < EF_CTRL_EFUSE_R1_SIZE / 4; i++) {
+        pefuse_start[i] = 0;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Load efuse region 0
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r0(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+    uint32_t timeout = EF_CTRL_DFT_TIMEOUT_VAL;
+
+    EF_CTRL_DATA0_CLEAR;
+
+    /* Trigger read */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+              (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+              (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (1 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    arch_delay_us(10);
+
+    /* Wait for efuse control idle */
+    do {
+        reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+        timeout--;
+
+        if (timeout == 0) {
+            break;
+        }
+    } while ((reg_val & EF_CTRL_EF_IF_0_BUSY_MASK) || (!(reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK)));
+
+    /* Switch to AHB clock */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+              (EF_CTRL_EF_CLK << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS) |
+#endif
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Load efuse region 0
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+static void ATTR_TCM_SECTION bflb_ef_ctrl_load_efuse_r1(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    EF_CTRL_DATA1_CLEAR;
+
+    /* Trigger read */
+    /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+	so we select it(them) in ef_if_ctrl_0 */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_1_RW_POS) |
+              (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_1_RW_POS) |
+              (1 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+
+    arch_delay_us(10);
+
+    /* Wait for efuse control idle */
+    do {
+        reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+    } while (reg_val & EF_CTRL_EF_IF_1_BUSY_MASK);
+
+    do {
+        reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+    } while (!(reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK));
+
+    /* Switch to AHB clock since often read efuse data after load */
+    /* Note:ef_if_ctrl_1 has no EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS bit as ef_if_ctrl_0,
+	   so we select it(them) in ef_if_ctrl_0 */
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_0_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_0_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_AUTO_RD_EN_POS) |
+              (0 << EF_CTRL_EF_IF_POR_DIG_POS) |
+              (1 << EF_CTRL_EF_IF_0_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_0_RW_POS) |
+              (0 << EF_CTRL_EF_IF_0_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    reg_val = (EF_CTRL_EFUSE_CTRL_PROTECT) |
+              (EF_CTRL_OP_MODE_AUTO << EF_CTRL_EF_IF_1_MANUAL_EN_POS) |
+              (EF_CTRL_PARA_DFT << EF_CTRL_EF_IF_1_CYC_MODIFY_POS) |
+              (1 << EF_CTRL_EF_IF_1_INT_CLR_POS) |
+              (0 << EF_CTRL_EF_IF_1_RW_POS) |
+              (0 << EF_CTRL_EF_IF_1_TRIG_POS);
+
+    putreg32(reg_val, BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_1_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Check efuse busy status
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return 1 for busy 0 for not
+ *
+*******************************************************************************/
+static int ATTR_TCM_SECTION bflb_ef_ctrl_busy(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    if (reg_val & EF_CTRL_EF_IF_0_BUSY_MASK) {
+        return 1;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Check efuse auto load done
+ *
+ * @param dev  ef control device pointer
+ *
+ * @return 1 for auto load done 0 for not
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_ef_ctrl_autoload_done(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    // if (dev == NULL) {
+    //     dev = bflb_device_get_by_name("ef_ctrl");
+    // }
+
+    /* Switch to AHB clock */
+    bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+
+    reg_val = getreg32(BFLB_EF_CTRL_BASE + EF_CTRL_EF_IF_CTRL_0_OFFSET);
+
+    if (reg_val & EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MASK) {
+        return 1;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  write data to efuse
+ *
+ * @param dev  ef control device pointer
+ * @param  offset: offset of efuse address to write
+ * @param  pword: data pointer to buffer which is aligned to word
+ * @param  count: count of data in words to write
+ * @param  program: 1 for program to efuse,0 for not program now
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_write_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t program)
+{
+    uint32_t *pefuse_start = NULL;
+    uint32_t region0_count = 0, region1_count = 0;
+    uint32_t total_size = EF_CTRL_EFUSE_R0_SIZE;
+    uintptr_t irq_stat;
+
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+    total_size += EF_CTRL_EFUSE_R1_SIZE;
+#else
+    (void)region1_count;
+#endif
+
+    if (offset > total_size || (offset + count * 4) > total_size || pword == NULL) {
+        return;
+    }
+
+    if (offset < EF_CTRL_EFUSE_R0_SIZE) {
+        if (offset + count * 4 <= EF_CTRL_EFUSE_R0_SIZE) {
+            region0_count = count;
+        } else {
+            region0_count = (EF_CTRL_EFUSE_R0_SIZE - offset) / 4;
+            region1_count = (offset + count * 4 - EF_CTRL_EFUSE_R0_SIZE) / 4;
+        }
+    } else {
+        region1_count = count;
+    }
+
+    // if (dev == NULL) {
+    //     dev = bflb_device_get_by_name("ef_ctrl");
+    // }
+    pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + offset);
+
+    irq_stat = bflb_irq_save();
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    bflb_efuse_switch_cpu_clock_save();
+#endif
+    if (region0_count > 0) {
+        /* Switch to AHB clock */
+        bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+
+        arch_memcpy4(pefuse_start, pword, region0_count);
+        pefuse_start += region0_count;
+        pword += region0_count;
+
+        if (program) {
+            bflb_ef_ctrl_program_efuse_r0(dev);
+            arch_delay_us(100);
+        }
+    }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+    if (region1_count > 0) {
+        /* Switch to AHB clock */
+        bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+
+        /* Add delay for CLK to be stable */
+        arch_delay_us(4);
+
+        arch_memcpy4(pefuse_start, pword, region1_count);
+
+        if (program) {
+            bflb_ef_ctrl_program_efuse_r1(dev);
+            arch_delay_us(100);
+        }
+    }
+#endif
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    bflb_efuse_switch_cpu_clock_restore();
+#endif
+
+    bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from efuse
+ *
+ * @param dev  ef control device pointer
+ * @param  offset: offset of efuse address to read
+ * @param  pword: data pointer to buffer which is aligned to word
+ * @param  count: count of data in words to read
+ * @param  reload: 1 for reload before read,0 for not
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_read_direct(struct bflb_device_s *dev, uint32_t offset, uint32_t *pword, uint32_t count, uint8_t reload)
+{
+    uint32_t *pefuse_start = NULL;
+    uint32_t region0_count = 0, region1_count = 0;
+    uint32_t total_size = EF_CTRL_EFUSE_R0_SIZE;
+    uintptr_t irq_stat;
+
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+    total_size += EF_CTRL_EFUSE_R1_SIZE;
+#else
+    (void)region1_count;
+#endif
+
+    if (offset > total_size || (offset + count * 4) > total_size || pword == NULL) {
+        return;
+    }
+
+    if (offset < EF_CTRL_EFUSE_R0_SIZE) {
+        if (offset + count * 4 <= EF_CTRL_EFUSE_R0_SIZE) {
+            region0_count = count;
+        } else {
+            region0_count = (EF_CTRL_EFUSE_R0_SIZE - offset) / 4;
+            region1_count = (offset + count * 4 - EF_CTRL_EFUSE_R0_SIZE) / 4;
+        }
+    } else {
+        region1_count = count;
+    }
+
+    // if (dev == NULL) {
+    //     dev = bflb_device_get_by_name("ef_ctrl");
+    // }
+    pefuse_start = (uint32_t *)(BFLB_EF_CTRL_BASE + offset);
+
+    irq_stat = bflb_irq_save();
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    bflb_efuse_switch_cpu_clock_save();
+#endif
+    if (region0_count > 0) {
+        if (reload) {
+            bflb_ef_ctrl_load_efuse_r0(dev);
+        } else {
+            bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+        }
+        arch_memcpy4(pword, pefuse_start, region0_count);
+        pword += region0_count;
+        pefuse_start += region0_count;
+    }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+    if (region1_count > 0) {
+        if (reload) {
+            bflb_ef_ctrl_load_efuse_r1(dev);
+        } else {
+            bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+        }
+        arch_memcpy4(pword, pefuse_start, region0_count);
+    }
+#endif
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    bflb_efuse_switch_cpu_clock_restore();
+#endif
+
+    bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read common trim value
+ *
+ * @param dev  ef control device pointer
+ * @param  name: Trim name
+ * @param  trim: Trim data pointer
+ * @param  reload: Reload efuse data before read
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_read_common_trim(struct bflb_device_s *dev, char *name, bflb_ef_ctrl_com_trim_t *trim, uint8_t reload)
+{
+    uint32_t reg_val;
+    uint32_t i = 0;
+    const bflb_ef_ctrl_com_trim_cfg_t *trim_list = NULL;
+    uint32_t trim_list_len;
+    uintptr_t irq_stat;
+
+    // if (dev == NULL) {
+    //     dev = bflb_device_get_by_name("ef_ctrl");
+    // }
+
+    irq_stat = bflb_irq_save();
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    bflb_efuse_switch_cpu_clock_save();
+#endif
+    if (reload) {
+        /* Trigger read data from efuse */
+        bflb_ef_ctrl_load_efuse_r0(dev);
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+        bflb_ef_ctrl_load_efuse_r1(dev);
+#endif
+    }
+
+    trim->en = 0;
+    trim->parity = 0;
+    trim->empty = 1;
+    trim->len = 0;
+
+    trim_list_len = bflb_ef_ctrl_get_common_trim_list(&trim_list);
+
+    for (i = 0; i < trim_list_len; i++) {
+        if (arch_memcmp(name, trim_list[i].name, strlen(name)) == 0) {
+            /* switch clock */
+            if (trim_list[i].en_addr <= EF_CTRL_EFUSE_R0_SIZE) {
+                /* Switch to AHB clock */
+                bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+            }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+            if (trim_list[i].en_addr > EF_CTRL_EFUSE_R0_SIZE) {
+                /* Switch to AHB clock */
+                bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+            }
+#endif
+            trim->len = trim_list[i].value_len;
+            reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4);
+            if (reg_val & (1 << (trim_list[i].en_addr % 32))) {
+                trim->en = 1;
+            }
+            reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4);
+            if (reg_val & (1 << (trim_list[i].parity_addr % 32))) {
+                trim->parity = 1;
+            }
+
+            if (((trim_list[i].value_addr % 32) + trim_list[i].value_len) > 32) {
+                uint64_t tmpval64 = (uint64_t)getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+                tmpval64 |= (((uint64_t)getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4 + 4)) << 32);
+                tmpval64 = tmpval64 >> (trim_list[i].value_addr % 32);
+                trim->value = (uint32_t)(tmpval64 & (((uint64_t)1 << trim_list[i].value_len) - 1));
+            } else {
+                reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+                reg_val = reg_val >> (trim_list[i].value_addr % 32);
+                trim->value = reg_val & ((1 << trim_list[i].value_len) - 1);
+            }
+
+            if (trim->en == 0 && trim->parity == 0 && trim->value == 0) {
+                trim->empty = 1;
+            } else {
+                trim->empty = 0;
+            }
+
+            break;
+        }
+    }
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    bflb_efuse_switch_cpu_clock_restore();
+#endif
+    bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse write common trim value
+ *
+ * @param dev  ef control device pointer
+ * @param  name: Trim name
+ * @param  trim: Trim data pointer
+ * @param  program: program to efuse entity or not
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_ef_ctrl_write_common_trim(struct bflb_device_s *dev, char *name, uint32_t value, uint8_t program)
+{
+    uint32_t reg_val;
+    uint32_t i = 0;
+    uint8_t parity = 0;
+    const bflb_ef_ctrl_com_trim_cfg_t *trim_list = NULL;
+    uint32_t trim_list_len;
+    uintptr_t irq_stat;
+
+    // if (dev == NULL) {
+    //     dev = bflb_device_get_by_name("ef_ctrl");
+    // }
+
+    trim_list_len = bflb_ef_ctrl_get_common_trim_list(&trim_list);
+
+    irq_stat = bflb_irq_save();
+    for (i = 0; i < trim_list_len; i++) {
+        if (memcmp(name, trim_list[i].name, strlen(name)) == 0) {
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+            bflb_efuse_switch_cpu_clock_save();
+#endif
+            /* switch clock */
+            if (trim_list[i].en_addr <= EF_CTRL_EFUSE_R0_SIZE) {
+                /* Switch to AHB clock */
+                bflb_ef_ctrl_switch_ahb_clk_r0(dev);
+            }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+            if (trim_list[i].en_addr > EF_CTRL_EFUSE_R0_SIZE) {
+                /* Switch to AHB clock */
+                bflb_ef_ctrl_switch_ahb_clk_r1(dev);
+            }
+#endif
+            reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4);
+            reg_val |= (1 << (trim_list[i].en_addr % 32));
+            putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].en_addr / 32) * 4, reg_val);
+
+            parity = bflb_ef_ctrl_get_trim_parity(value, trim_list[i].value_len);
+            if (parity) {
+                reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4);
+                reg_val |= (1 << (trim_list[i].parity_addr % 32));
+                putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].parity_addr / 32) * 4, reg_val);
+            }
+
+            if (((trim_list[i].value_addr % 32) + trim_list[i].value_len) > 32) {
+                reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+                reg_val |= (value << (trim_list[i].value_addr % 32));
+                putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4, reg_val);
+
+                reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4) + 4;
+                reg_val |= (value >> (32 - (trim_list[i].value_addr % 32)));
+                putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4 + 4, reg_val);
+            } else {
+                reg_val = getreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4);
+                reg_val |= (value << (trim_list[i].value_addr % 32));
+                putreg32(BFLB_EF_CTRL_BASE + (trim_list[i].value_addr / 32) * 4, reg_val);
+            }
+
+            if (program) {
+                /* program */
+                if (trim_list[i].en_addr <= EF_CTRL_EFUSE_R0_SIZE) {
+                    bflb_ef_ctrl_program_efuse_r0(dev);
+                }
+#ifdef EF_CTRL_EFUSE_R1_SIZE
+                if (trim_list[i].en_addr > EF_CTRL_EFUSE_R0_SIZE) {
+                    bflb_ef_ctrl_program_efuse_r1(dev);
+                }
+#endif
+            }
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+            bflb_efuse_switch_cpu_clock_restore();
+#endif
+            break;
+        }
+    }
+    bflb_irq_restore(irq_stat);
+}
+
+/****************************************************************************/ /**
+ * @brief  Whether a value bits is all zero
+ *
+ * @param  val: value to check
+ * @param  start: start bit
+ * @param  len: total length of bits to check
+ *
+ * @return 1 for all bits zero 0 for others
+ *
+*******************************************************************************/
+uint8_t ATTR_TCM_SECTION bflb_ef_ctrl_is_all_bits_zero(uint32_t val, uint8_t start, uint8_t len)
+{
+    uint32_t mask = 0;
+
+    val = (val >> start);
+
+    if (len >= 32) {
+        mask = 0xffffffff;
+    } else {
+        mask = (1 << len) - 1;
+    }
+
+    if ((val & mask) == 0) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse Ctrl get zero bit count
+ *
+ * @param  val: Value to count
+ *
+ * @return Zero bit count
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION bflb_ef_ctrl_get_byte_zero_cnt(uint8_t val)
+{
+    uint32_t cnt = 0;
+    uint32_t i = 0;
+
+    for (i = 0; i < 8; i++) {
+        if ((val & (1 << i)) == 0) {
+            cnt += 1;
+        }
+    }
+
+    return cnt;
+}
+
+/****************************************************************************/ /**
+ * @brief  Analog Trim parity calculate
+ *
+ * @param  val: Value of efuse trim data
+ * @param  len: Length of bit to calculate
+ *
+ * @return Parity bit value
+ *
+*******************************************************************************/
+uint8_t ATTR_CLOCK_SECTION bflb_ef_ctrl_get_trim_parity(uint32_t val, uint8_t len)
+{
+    uint8_t cnt = 0;
+    uint8_t i = 0;
+
+    for (i = 0; i < len; i++) {
+        if (val & (1 << i)) {
+            cnt++;
+        }
+    }
+
+    return cnt & 0x01;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_emac.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_emac.c
new file mode 100755
index 0000000000..f4d6809ab8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_emac.c
@@ -0,0 +1,879 @@
+/**
+  ******************************************************************************
+  * @file    bflb_emac.c
+  * @version V1.0
+  * @date    2022-09-27
+  * @brief   This file is the low hardware abstraction layer file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2022 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "bflb_emac.h"
+#include "bflb_clock.h"
+#include "bflb_l1c.h"
+#include "hardware/emac_reg.h"
+
+/* private definition */
+// #define TAG                   "EMAC_BD: "
+#define EMAC_TX_COMMON_FLAGS (EMAC_BD_TX_RD_MASK | EMAC_BD_TX_IRQ_MASK | EMAC_BD_TX_PAD_MASK | EMAC_BD_TX_CRC_MASK | EMAC_BD_TX_EOF_MASK)
+#define EMAC_RX_COMMON_FLAGS ((ETH_MAX_PACKET_SIZE << 16) | EMAC_BD_RX_IRQ_MASK)
+
+/**
+ *  @brief Note: Always write DWORD1 (buffer addr) first then DWORD0 for racing concern.
+ */
+struct bflb_emac_bd_desc_s {
+    uint32_t C_S_L;  /*!< Buffer Descriptors(BD) control,status,length */
+    uint32_t Buffer; /*!< BD buffer address */
+};
+
+/**
+ * @brief emac handle type definition
+ * @param bd             Tx descriptor header pointer
+ * @param tx_index_emac  TX index: EMAC
+ * @param tx_index_cpu   TX index: CPU/SW
+ * @param tx_buff_limit  TX index max
+ * @param rsv0           rsv0
+ * @param rx_index_emac  RX index: EMAC
+ * @param rx_index_cpu   RX index: CPU/SW
+ * @param rx_buff_limit  RX index max
+ * @param rsv1           rsv1
+ *
+ */
+struct bflb_emac_handle_s {
+    struct bflb_emac_bd_desc_s *bd;
+    uint8_t tx_index_emac;
+    uint8_t tx_index_cpu;
+    uint8_t tx_buff_limit;
+    uint8_t rsv0;
+    uint8_t rx_index_emac;
+    uint8_t rx_index_cpu;
+    uint8_t rx_buff_limit;
+    uint8_t rsv1;
+};
+
+static struct bflb_emac_handle_s eth_handle;
+static struct bflb_emac_handle_s *thiz = NULL;
+
+/**
+ *
+ * @brief get emac current active buffer describe index
+ * @param dev
+ * @param bdt @ref emac buffer descriptors type define
+ * @return uint32_t
+ *
+ */
+uint32_t bflb_emac_bd_get_cur_active(struct bflb_device_s *dev, uint8_t bdt)
+{
+    uint32_t bd = 0;
+    uint32_t reg_base;
+    reg_base = dev->reg_base;
+
+    bd = getreg32(reg_base + EMAC_TX_BD_NUM_OFFSET);
+
+    if (bdt == EMAC_BD_TYPE_TX) {
+        bd &= EMAC_TXBDPTR_MASK;
+        bd >>= EMAC_TXBDPTR_SHIFT;
+    }
+
+    if (bdt == EMAC_BD_TYPE_RX) {
+        bd &= EMAC_RXBDPTR_MASK;
+        bd >>= EMAC_RXBDPTR_SHIFT;
+    }
+
+    return bd;
+}
+/**
+ * @brief
+ *
+ * @param index
+ *
+ */
+void bflb_emac_bd_rx_enqueue(uint32_t index)
+{
+    thiz->rx_index_emac = index;
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ *
+ */
+void bflb_emac_bd_rx_on_err(uint32_t index)
+{
+    /* handle error */
+    if (thiz->bd[index].C_S_L & EMAC_BD_RX_OR_MASK) {
+        printf("EMAC RX OR Error at %s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_RX_RE_MASK) {
+        printf("MAC RX RE Error at %s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_RX_DN_MASK) {
+        printf("MAC RX DN Error at %s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_RX_TL_MASK) {
+        printf("MAC RX TL Error at %s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_RX_CRC_MASK) {
+        printf("MAC RX CRC Error at %s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_RX_LC_MASK) {
+        printf("MAC RX LC Error at %s:%d\r\n", __func__, __LINE__);
+    }
+
+    thiz->bd[index].C_S_L &= ~0xff;
+    /* RX BD is ready for RX */
+    thiz->bd[index].C_S_L |= EMAC_BD_RX_E_MASK;
+}
+
+/**
+ * @brief this func will be called in ISR
+ *
+ * @param index
+ *
+ */
+void bflb_emac_bd_tx_dequeue(uint32_t index)
+{
+    struct bflb_emac_bd_desc_s *DMADesc;
+
+    thiz->tx_index_emac = index;
+    DMADesc = &thiz->bd[thiz->tx_index_emac];
+    /* release this tx BD to SW (HW will do this) */
+    DMADesc->C_S_L &= ~EMAC_BD_TX_RD_MASK;
+}
+
+/**
+ * @brief
+ *
+ * @param index
+ * @return int
+ */
+void bflb_emac_bd_tx_on_err(uint32_t index)
+{
+    /* handle error */
+    if (thiz->bd[index].C_S_L & EMAC_BD_TX_UR_MASK) {
+        printf("%s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_TX_RTRY_MASK) {
+        printf("%s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_TX_RL_MASK) {
+        printf("%s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_TX_LC_MASK) {
+        printf("%s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_TX_DF_MASK) {
+        printf("%s:%d\r\n", __func__, __LINE__);
+    }
+
+    if (thiz->bd[index].C_S_L & EMAC_BD_TX_CS_MASK) {
+        printf("%s:%d\r\n", __func__, __LINE__);
+    }
+
+    thiz->bd[index].C_S_L &= ~0xff;
+}
+/**
+ * @brief
+ *
+ * @param none
+ * @return int
+ */
+int emac_bd_fragment_support(void)
+{
+#if defined(BL616) || defined(BL808)
+    return 1;
+#elif defined(BL702)
+    return 0;
+#elif defined(BL628)
+    return 1;
+#endif
+}
+/**
+ * @brief
+ *
+ * @param flags
+ * @param len
+ * @param data_in
+ * @return int
+ */
+int bflb_emac_bd_tx_enqueue(uint32_t flags, uint32_t len, const uint8_t *data_in)
+{
+    uint32_t err = 0;
+    struct bflb_emac_bd_desc_s *DMADesc;
+    uint32_t tx_flags = EMAC_TX_COMMON_FLAGS;
+    DMADesc = &thiz->bd[thiz->tx_index_cpu];
+
+    if (flags & EMAC_FRAGMENT_PACKET) {
+        /* Fragment packet, clear EOF */
+        tx_flags &= ~EMAC_BD_TX_EOF_MASK;
+    }
+
+    if (DMADesc->C_S_L & EMAC_BD_TX_RD_MASK) {
+        /* no free BD, lost sync with DMA TX? */
+        err = 4;
+        //printf(TAG"%s:%d\n", __func__, __LINE__);
+    } else {
+#if defined(BL616)
+        __ASM volatile("fence");
+#endif
+        // printf("tx q flags:%d,len:%d,data:0x%x\r\n", flags, len, data_in);
+        if (flags & EMAC_NOCOPY_PACKET) {
+            DMADesc->Buffer = (uint32_t)(uintptr_t)data_in;
+        } else {
+            // memcpy((void *)(uintptr_t)(DMADesc->Buffer), data_in, len);
+            arch_memcpy_fast((void *)(uintptr_t)(DMADesc->Buffer), data_in, len);
+        }
+
+#ifdef EMAC_DO_FLUSH_DATA
+#if defined(BL616)
+        bflb_l1c_dcache_invalidate_range((void *)DMADesc->Buffer, len);
+#endif
+#endif
+        DMADesc->C_S_L = tx_flags | (len << EMAC_BD_TX_LEN_SHIFT);
+
+        /* move to next TX BD */
+        if ((++thiz->tx_index_cpu) > thiz->tx_buff_limit) {
+            /* the last BD */
+            DMADesc->C_S_L |= EMAC_BD_TX_WR_MASK;
+            /* wrap back */
+            thiz->tx_index_cpu = 0;
+        }
+    }
+
+    return err;
+}
+
+/**
+ * @brief
+ *
+ * @param flags
+ * @param len
+ * @param data_out
+ * @return int
+ */
+int bflb_emac_bd_rx_dequeue(uint32_t flags, uint32_t *len, uint8_t *data_out)
+{
+    uint32_t err = 0;
+    struct bflb_emac_bd_desc_s *DMADesc;
+
+    DMADesc = &thiz->bd[thiz->rx_index_cpu];
+
+    if (DMADesc->C_S_L & EMAC_BD_RX_E_MASK) {
+        /* current RX BD is empty */
+        err = 4;
+        *len = 0;
+    } else {
+        *len = (thiz->bd[thiz->rx_index_cpu].C_S_L & EMAC_BD_RX_LEN_MASK) >> EMAC_BD_RX_LEN_SHIFT;
+#ifdef EMAC_DO_FLUSH_DATA
+#if defined(BL616)
+        bflb_l1c_dcache_invalidate_range((void *)DMADesc->Buffer, *len);
+#endif
+#endif
+        if (data_out) {
+            // memcpy(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len);
+            arch_memcpy_fast(data_out, (const void *)(uintptr_t)DMADesc->Buffer, *len);
+        }
+
+        /* RX BD can be used for another receive */
+        DMADesc->C_S_L |= EMAC_BD_RX_E_MASK;
+
+        /* move to next RX BD */
+        if ((++thiz->rx_index_cpu) > thiz->rx_buff_limit) {
+            /* the last BD */
+            DMADesc->C_S_L |= EMAC_BD_RX_WR_MASK;
+            /* wrap back */
+            thiz->rx_index_cpu = thiz->tx_buff_limit + 1;
+        }
+    }
+
+    return err;
+}
+
+/**
+ * @brief bflb emac init
+ *
+ * @param dev
+ * @param config
+ *
+ */
+void bflb_emac_init(struct bflb_device_s *dev, const struct bflb_emac_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t reg_val;
+
+#if defined(BL616) || defined(BL808)
+#define GLB_EMAC_CLK_OUT_ADDRESS (0x20000390)
+#define GLB_UNGATE_CFG2_ADDRESS  (0x20000588)
+
+    /* GLB select inside clock or Not */
+    reg_val = getreg32(GLB_EMAC_CLK_OUT_ADDRESS);
+    if (config->inside_clk == EMAC_CLK_USE_INTERNAL) {
+        reg_val |= (1 << 5);
+        reg_val |= (1 << 6);
+        reg_val &= ~(1 << 7);
+        reg_val |= (1 << 10);
+    } else {
+        reg_val &= ~(1 << 5);
+        reg_val &= ~(1 << 6);
+        reg_val &= ~(1 << 7);
+    }
+    putreg32(reg_val, GLB_EMAC_CLK_OUT_ADDRESS);
+
+    /* ungate emac clock */
+    reg_val = getreg32(GLB_UNGATE_CFG2_ADDRESS);
+    reg_val |= (1 << 23);
+    putreg32(reg_val, GLB_UNGATE_CFG2_ADDRESS);
+#elif defined(BL702)
+    /* enable audio clock and GLB select inside clock or Not */
+// #define PDS_AUDIO_PLL_EN_ADDRESS (0x4000E41C)
+#define GLB_UNGATE_CFG1_ADDRESS (0x40000024)
+#define GLB_CLOCK_CFG3_ADDRESS  (0x4000000C)
+
+    // reg_val = getreg32(PDS_AUDIO_PLL_EN_ADDRESS);
+    // reg_val |= (1 << 7);
+    // putreg32(reg_val, PDS_AUDIO_PLL_EN_ADDRESS);
+
+    reg_val = getreg32(GLB_CLOCK_CFG3_ADDRESS);
+    if (config->inside_clk == EMAC_CLK_USE_INTERNAL) {
+        reg_val |= (1 << 5);
+    } else {
+        reg_val &= ~(1 << 5);
+    }
+    putreg32(reg_val, GLB_CLOCK_CFG3_ADDRESS);
+
+    /* ungate emac clock */
+    reg_val = getreg32(GLB_UNGATE_CFG1_ADDRESS);
+    reg_val |= (1 << 0x0d);
+    putreg32(reg_val, GLB_UNGATE_CFG1_ADDRESS);
+#endif
+
+    reg_base = dev->reg_base;
+    /* set mac defualt config , enable rmii and other*/
+    reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+    reg_val |= (EMAC_RMII_EN);
+    reg_val |= (EMAC_PRO);
+    reg_val |= (EMAC_BRO);
+    reg_val &= ~(EMAC_NOPRE);
+    reg_val |= (EMAC_PAD);
+    reg_val |= (EMAC_CRCEN);
+    reg_val &= ~(EMAC_HUGEN);
+    reg_val |= (EMAC_RECSMALL);
+    reg_val |= (EMAC_IFG);
+    putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+
+    /* set inter frame gap defualt value */
+    reg_val = getreg32(reg_base + EMAC_IPGT_OFFSET);
+    reg_val &= ~(EMAC_IPGT_MASK);
+    reg_val |= (0x18) << EMAC_IPGT_SHIFT;
+    putreg32(reg_val, reg_base + EMAC_IPGT_OFFSET);
+
+    /* set MII interface */
+    reg_val = getreg32(reg_base + EMAC_MIIMODE_OFFSET);
+    reg_val |= EMAC_MIINOPRE;
+    reg_val &= ~(EMAC_CLKDIV_MASK);
+    reg_val |= (config->mii_clk_div) << EMAC_CLKDIV_SHIFT;
+    putreg32(reg_val, reg_base + EMAC_MIIMODE_OFFSET);
+
+    /* set collision */
+    reg_val = getreg32(reg_base + EMAC_COLLCONFIG_OFFSET);
+    reg_val &= ~(EMAC_MAXFL_MASK | EMAC_COLLVALID_MASK);
+    reg_val |= (0xf) << EMAC_MAXFL_SHIFT;
+    reg_val |= (0x10) << EMAC_COLLVALID_SHIFT;
+    putreg32(reg_val, reg_base + EMAC_COLLCONFIG_OFFSET);
+
+    /* set frame length */
+    reg_val = getreg32(reg_base + EMAC_PACKETLEN_OFFSET);
+    reg_val &= ~(EMAC_MINFL_MASK | EMAC_MAXFL_MASK);
+    reg_val |= (config->min_frame_len) << EMAC_MINFL_SHIFT;
+    reg_val |= (config->max_frame_len) << EMAC_MAXFL_SHIFT;
+    putreg32(reg_val, reg_base + EMAC_PACKETLEN_OFFSET);
+
+    /* set emac address */
+    reg_val = getreg32(reg_base + EMAC_MAC_ADDR0_OFFSET);
+    reg_val &= ~(EMAC_MAC_B2_MASK | EMAC_MAC_B3_MASK | EMAC_MAC_B4_MASK | EMAC_MAC_B5_MASK);
+    reg_val |= (config->mac_addr[5]) << EMAC_MAC_B5_SHIFT;
+    reg_val |= (config->mac_addr[4]) << EMAC_MAC_B4_SHIFT;
+    reg_val |= (config->mac_addr[3]) << EMAC_MAC_B3_SHIFT;
+    reg_val |= (config->mac_addr[2]) << EMAC_MAC_B2_SHIFT;
+    putreg32(reg_val, reg_base + EMAC_MAC_ADDR0_OFFSET);
+    reg_val = getreg32(reg_base + EMAC_MAC_ADDR1_OFFSET);
+    reg_val &= ~(EMAC_MAC_B0_MASK | EMAC_MAC_B1_MASK);
+    reg_val |= (config->mac_addr[1]) << EMAC_MAC_B1_SHIFT;
+    reg_val |= (config->mac_addr[0]) << EMAC_MAC_B0_SHIFT;
+    putreg32(reg_val, reg_base + EMAC_MAC_ADDR1_OFFSET);
+}
+
+/**
+ * @brief bflb emac deinit
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_deinit(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t reg_val;
+
+    reg_base = dev->reg_base;
+
+    reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+    reg_val &= ~(EMAC_TX_EN | EMAC_RX_EN);
+    putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac interrupt enable
+ *
+ * @param dev
+ * @param flag
+ * @param enable
+ *
+ */
+void bflb_emac_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t reg_val_mask; // reg_val_en;
+
+    reg_base = dev->reg_base;
+    reg_val_mask = getreg32(reg_base + EMAC_INT_MASK_OFFSET);
+    if (enable) {
+        reg_val_mask &= ~(flag);
+    } else {
+        reg_val_mask |= (flag);
+    }
+    putreg32(reg_val_mask, reg_base + EMAC_INT_MASK_OFFSET);
+};
+
+/**
+ * @brief bflb emac interrupt clear
+ *
+ * @param dev
+ * @param flag
+ *
+ */
+void bflb_emac_int_clear(struct bflb_device_s *dev, uint32_t flag)
+{
+    putreg32(flag, dev->reg_base + EMAC_INT_SOURCE_OFFSET);
+}
+
+/**
+ * @brief bflb emac get interrupt status
+ *
+ * @param dev
+ * @return uint32_t
+ */
+uint32_t bflb_emac_get_int_status(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t reg_sts_val, reg_mask_val;
+
+    reg_base = dev->reg_base;
+    reg_sts_val = getreg32(reg_base + EMAC_INT_SOURCE_OFFSET);
+    reg_mask_val = getreg32(reg_base + EMAC_INT_MASK_OFFSET);
+
+    return (reg_sts_val & (~reg_mask_val));
+}
+
+/**
+ * @brief emac dma description list init
+ *
+ * @param reg_base
+ * @param handle
+ * @param tx_buff
+ * @param tx_buff_cnt
+ * @param rx_buff
+ * @param rx_buff_cnt
+ *
+ */
+static void emac_dma_desc_list_init(uint32_t reg_base, struct bflb_emac_handle_s *handle, uint8_t *tx_buff, uint32_t tx_buff_cnt, uint8_t *rx_buff, uint32_t rx_buff_cnt)
+{
+    uint32_t i = 0;
+
+    /* Set the Ethernet handler env */
+    handle->bd = (struct bflb_emac_bd_desc_s *)(uintptr_t)(reg_base + EMAC_DMA_DESC_OFFSET);
+    handle->tx_index_emac = 0;
+    handle->tx_index_cpu = 0;
+    handle->tx_buff_limit = tx_buff_cnt - 1;
+    /* The receive descriptors' address starts right after the last transmit BD. */
+    handle->rx_index_emac = tx_buff_cnt;
+    handle->rx_index_cpu = tx_buff_cnt;
+    handle->rx_buff_limit = tx_buff_cnt + rx_buff_cnt - 1;
+
+    /* Fill each DMARxDesc descriptor with the right values */
+    for (i = 0; i < tx_buff_cnt; i++) {
+        /* Get the pointer on the ith member of the Tx Desc list */
+        handle->bd[i].Buffer = (NULL == tx_buff) ? 0 : (uint32_t)(uintptr_t)(tx_buff + (ETH_MAX_PACKET_SIZE * i));
+        handle->bd[i].C_S_L = 0;
+    }
+
+    /* For the last TX DMA Descriptor, it should be wrap back */
+    handle->bd[handle->tx_buff_limit].C_S_L |= EMAC_BD_TX_WR_MASK;
+
+    for (i = tx_buff_cnt; i < (tx_buff_cnt + rx_buff_cnt); i++) {
+        /* Get the pointer on the ith member of the Rx Desc list */
+        handle->bd[i].Buffer = (NULL == rx_buff) ? 0 : (uint32_t)(uintptr_t)(rx_buff + (ETH_MAX_PACKET_SIZE * (i - tx_buff_cnt)));
+        handle->bd[i].C_S_L = (ETH_MAX_PACKET_SIZE << 16) | EMAC_BD_RX_IRQ_MASK | EMAC_BD_RX_E_MASK;
+    }
+
+    /* For the last RX DMA Descriptor, it should be wrap back */
+    handle->bd[handle->rx_buff_limit].C_S_L |= EMAC_BD_RX_WR_MASK;
+
+    /* For the TX DMA Descriptor, it will wrap to 0 according to EMAC_TX_BD_NUM*/
+    putreg32(tx_buff_cnt, reg_base + EMAC_TX_BD_NUM_OFFSET);
+}
+
+/**
+ * @brief emac buffer description init
+ *
+ * @param eth_tx_buff
+ * @param tx_buf_count
+ * @param eth_rx_buff
+ * @param rx_buf_count
+ *
+ */
+void bflb_emac_bd_init(struct bflb_device_s *dev, uint8_t *eth_tx_buff, uint8_t tx_buf_count, uint8_t *eth_rx_buff, uint8_t rx_buf_count)
+{
+    thiz = ð_handle;
+    uint32_t reg_base;
+    reg_base = dev->reg_base;
+    /* init the BDs in emac with buffer address */
+    emac_dma_desc_list_init(reg_base, thiz, (uint8_t *)eth_tx_buff, tx_buf_count, (uint8_t *)eth_rx_buff, rx_buf_count);
+}
+
+/**
+ * @brief bflb emac phy register read
+ *
+ * @param dev
+ * @param phy_reg
+ * @param phy_reg_val
+ * @return int
+ *
+ */
+int bflb_emac_phy_reg_read(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t *phy_reg_val)
+{
+    uint32_t reg_val;
+
+    /* Set Register Address */
+    reg_val = getreg32(dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+    reg_val &= ~(EMAC_RGAD_MASK);
+    reg_val |= ((uint32_t)phy_reg << EMAC_RGAD_SHIFT);
+    putreg32(reg_val, dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+
+    /* Trigger read */
+    reg_val = getreg32(dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+    reg_val |= (EMAC_RSTAT);
+    putreg32(reg_val, dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+
+    do {
+        reg_val = getreg32(dev->reg_base + EMAC_MIISTATUS_OFFSET);
+        bflb_mtimer_delay_us(16);
+    } while ((reg_val & (EMAC_MIIM_BUSY)) != 0);
+
+    *phy_reg_val = getreg32(dev->reg_base + EMAC_MIIRX_DATA_OFFSET);
+
+    return 0;
+}
+
+/**
+ * @brief bflb emac phy register write
+ *
+ * @param dev
+ * @param phy_reg
+ * @param phy_reg_val
+ * @return int
+ *
+ */
+int bflb_emac_phy_reg_write(struct bflb_device_s *dev, uint16_t phy_reg, uint16_t phy_reg_val)
+{
+    uint32_t reg_val;
+
+    /* Set Register Address */
+    reg_val = getreg32(dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+    reg_val &= ~(EMAC_RGAD_MASK);
+    reg_val |= ((uint32_t)phy_reg << EMAC_RGAD_SHIFT);
+    putreg32(reg_val, dev->reg_base + EMAC_MIIADDRESS_OFFSET);
+
+    /* Set Write data */
+    putreg32(phy_reg_val, dev->reg_base + EMAC_MIITX_DATA_OFFSET);
+
+    /* Trigger write */
+    reg_val = getreg32(dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+    reg_val |= (EMAC_WCTRLDATA);
+    putreg32(reg_val, dev->reg_base + EMAC_MIICOMMAND_OFFSET);
+
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+
+    do {
+        reg_val = getreg32(dev->reg_base + EMAC_MIISTATUS_OFFSET);
+        bflb_mtimer_delay_us(16);
+    } while ((reg_val & (EMAC_MIIM_BUSY)) != 0);
+
+    return 0;
+}
+
+/**
+ * @brief bflb emac feature control
+ *
+ * @param dev
+ * @param cmd
+ * @param arg
+ * @return int
+ *
+ */
+int bflb_emac_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_val;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    switch (cmd) {
+        case EMAC_CMD_NO_PREAMBLE_MODE:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_NOPRE;
+            } else {
+                reg_val &= ~(EMAC_NOPRE);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_EN_PROMISCUOUS:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_PRO;
+            } else {
+                reg_val &= ~(EMAC_PRO);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_FRAME_GAP_CHECK:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_IFG;
+            } else {
+                reg_val &= ~(EMAC_IFG);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_FULL_DUPLEX:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_FULLD;
+            } else {
+                reg_val &= ~(EMAC_FULLD);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_EN_TX_CRC_FIELD:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_CRCEN;
+            } else {
+                reg_val &= ~(EMAC_CRCEN);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_RECV_HUGE_FRAMES:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_HUGEN;
+            } else {
+                reg_val &= ~(EMAC_HUGEN);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_EN_AUTO_PADDING:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_PAD;
+            } else {
+                reg_val &= ~(EMAC_PAD);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_RECV_SMALL_FRAME:
+            reg_val = getreg32(reg_base + EMAC_MODE_OFFSET);
+            if (arg) {
+                reg_val |= EMAC_RECSMALL;
+            } else {
+                reg_val &= ~(EMAC_RECSMALL);
+            }
+            putreg32(reg_val, reg_base + EMAC_MODE_OFFSET);
+            break;
+
+        case EMAC_CMD_SET_PHY_ADDRESS:
+            reg_val = getreg32(reg_base + EMAC_MIIADDRESS_OFFSET);
+            reg_val &= ~(EMAC_FIAD_MASK);
+            reg_val |= (uint32_t)(arg << EMAC_FIAD_SHIFT);
+            putreg32(reg_val, reg_base + EMAC_MIIADDRESS_OFFSET);
+            break;
+
+        case EMAC_CMD_SET_MAXRET:
+            reg_val = getreg32(reg_base + EMAC_COLLCONFIG_OFFSET);
+            reg_val &= ~(EMAC_MAXFL_MASK);
+            reg_val |= (arg) << EMAC_MAXFL_SHIFT;
+            putreg32(reg_val, reg_base + EMAC_COLLCONFIG_OFFSET);
+            break;
+
+        case EMAC_CMD_SET_COLLVALID:
+            reg_val = getreg32(reg_base + EMAC_COLLCONFIG_OFFSET);
+            reg_val &= ~(EMAC_COLLVALID_MASK);
+            reg_val |= (arg) << EMAC_COLLVALID_SHIFT;
+            putreg32(reg_val, reg_base + EMAC_COLLCONFIG_OFFSET);
+            break;
+
+        case EMAC_CMD_SET_PACKET_GAP:
+            reg_val = getreg32(reg_base + EMAC_IPGT_OFFSET);
+            reg_val &= ~(EMAC_IPGT_MASK);
+            reg_val |= (arg) << EMAC_IPGT_SHIFT;
+            putreg32(reg_val, reg_base + EMAC_IPGT_OFFSET);
+            break;
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
+
+/**
+ * @brief bflb emac stop
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_stop(struct bflb_device_s *dev)
+{
+    /* disable emac */
+    uint32_t reg_val;
+
+    reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+    reg_val &= ~(EMAC_TX_EN | EMAC_RX_EN);
+    putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac start
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_start(struct bflb_device_s *dev)
+{
+    /* enable emac */
+    uint32_t reg_val;
+
+    reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+    reg_val |= (EMAC_TX_EN | EMAC_RX_EN);
+    putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac start tx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_start_tx(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+    reg_val |= (EMAC_TX_EN);
+    putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac stop tx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_stop_tx(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+    reg_val &= ~(EMAC_TX_EN);
+    putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac start rx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_start_rx(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+    reg_val |= (EMAC_RX_EN);
+    putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
+
+/**
+ * @brief bflb emac stop rx
+ *
+ * @param dev
+ *
+ */
+void bflb_emac_stop_rx(struct bflb_device_s *dev)
+{
+    uint32_t reg_val;
+
+    reg_val = getreg32(dev->reg_base + EMAC_MODE_OFFSET);
+    reg_val &= ~(EMAC_RX_EN);
+    putreg32(reg_val, dev->reg_base + EMAC_MODE_OFFSET);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_flash.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_flash.c
new file mode 100755
index 0000000000..6229cfeb9a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_flash.c
@@ -0,0 +1,809 @@
+
+#if defined(BL616)
+#include "bl616_memorymap.h"
+#include "bl616_glb.h"
+#include "bl616_ef_cfg.h"
+#elif defined(BL606P)
+#include "bl606p_memorymap.h"
+#include "bl606p_glb.h"
+#elif defined(BL808)
+#include "bl808_memorymap.h"
+#include "bl808_glb.h"
+#elif defined(BL702L)
+#include "bl702l_glb.h"
+#include "bl702l_ef_ctrl.h"
+#elif defined(BL602)
+#include "bl602_glb.h"
+#include "bl602_sflash_ext.h"
+#include "bl602_xip_sflash_ext.h"
+#include "bl602_sf_cfg_ext.h"
+#elif defined(BL702)
+#include "bl702_glb.h"
+#include "bl702_xip_sflash_ext.h"
+#include "bl702_sf_cfg_ext.h"
+#endif
+#include "bflb_xip_sflash.h"
+#include "bflb_sf_cfg.h"
+#include "bflb_flash.h"
+#include "hardware/sf_ctrl_reg.h"
+
+#if defined(BL616)
+static uint32_t flash1_size = 4 * 1024 * 1024;
+static uint32_t flash2_size = 2 * 1024 * 1024;
+static uint32_t g_jedec_id2 = 0;
+#endif
+static uint32_t g_jedec_id = 0;
+static spi_flash_cfg_type g_flash_cfg = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = 0x11,
+    .clk_delay = 0,
+    .clk_invert = 0x03,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+#if defined(BL616)
+static spi_flash_cfg_type g_flash2_cfg = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = 0x10,
+    .clk_delay = 0,
+    .clk_invert = 0x03,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static bflb_efuse_device_info_type deviceInfo;
+#endif
+
+#if defined(BL616)
+uint32_t bflb_flash2_get_jedec_id(void)
+{
+    uint32_t jid = 0;
+
+    jid = ((g_jedec_id2 & 0xff) << 16) + (g_jedec_id2 & 0xff00) + ((g_jedec_id2 & 0xff0000) >> 16);
+    return jid;
+}
+#endif
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL702L)
+static int flash_get_clock_delay(spi_flash_cfg_type *cfg)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+    /* bit0-3 for clk delay */
+    if (regval & SF_CTRL_SF_IF_READ_DLY_EN) {
+        cfg->clk_delay = ((regval & SF_CTRL_SF_IF_READ_DLY_N_MASK) >> SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1;
+    } else {
+        cfg->clk_delay = 0;
+    }
+    cfg->clk_invert = 0;
+    /* bit0 for clk invert */
+    cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_OUT_INV_SEL) ? 1 : 0) << 0);
+    /* bit1 for rx clk invert */
+    cfg->clk_invert |= (((regval & SF_CTRL_SF_CLK_SF_RX_INV_SEL) ? 1 : 0) << 1);
+
+    regval = getreg32(reg_base + SF_CTRL_SF_IF_IO_DLY_1_OFFSET);
+    /* bit4-6 for do delay */
+    cfg->clk_delay |= (((regval & SF_CTRL_SF_IO_0_DO_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DO_DLY_SEL_SHIFT) << 4);
+    /* bit2-4 for di delay */
+    cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_DI_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_DI_DLY_SEL_SHIFT) << 2);
+    /* bit5-7 for oe delay */
+    cfg->clk_invert |= (((regval & SF_CTRL_SF_IO_0_OE_DLY_SEL_MASK) >> SF_CTRL_SF_IO_0_OE_DLY_SEL_SHIFT) << 5);
+
+    return 0;
+}
+#endif
+
+static void ATTR_TCM_SECTION flash_set_qspi_enable(spi_flash_cfg_type *p_flash_cfg)
+{
+    if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
+        bflb_sflash_qspi_enable(p_flash_cfg);
+    }
+}
+
+static void ATTR_TCM_SECTION flash_set_l1c_wrap(spi_flash_cfg_type *p_flash_cfg)
+{
+    if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
+        L1C_Set_Wrap(ENABLE);
+        bflb_sflash_set_burst_wrap(p_flash_cfg);
+    } else {
+        L1C_Set_Wrap(DISABLE);
+        bflb_sflash_disable_burst_wrap(p_flash_cfg);
+    }
+}
+
+/**
+ * @brief flash_config_init
+ *
+ * @return int
+ */
+static int ATTR_TCM_SECTION flash_config_init(spi_flash_cfg_type *p_flash_cfg, uint8_t *jedec_id)
+{
+    int ret = -1;
+    uint8_t is_aes_enable = 0;
+    uint32_t jid = 0;
+    uint32_t offset = 0;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    bflb_xip_sflash_opt_enter(&is_aes_enable);
+    bflb_xip_sflash_state_save(p_flash_cfg, &offset, 0, 0);
+    bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jid);
+    arch_memcpy(jedec_id, (uint8_t *)&jid, 3);
+    jid &= 0xFFFFFF;
+    g_jedec_id = jid;
+    ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jid, p_flash_cfg, 0, 0);
+    if (ret == 0) {
+        p_flash_cfg->mid = (jid & 0xff);
+    }
+
+    // p_flash_cfg->io_mode = 0x11;
+    // p_flash_cfg->c_read_support = 0x00;
+
+    /* Set flash controler from p_flash_cfg */
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+    bflb_flash_set_cmds(p_flash_cfg);
+#endif
+    flash_set_qspi_enable(p_flash_cfg);
+    flash_set_l1c_wrap(p_flash_cfg);
+#if defined(BL602)
+    bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, 0, 0);
+#else
+    bflb_xip_sflash_state_restore(p_flash_cfg, offset, 0, 0);
+#endif
+    bflb_xip_sflash_opt_exit(is_aes_enable);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+#if defined(BL616)
+/**
+ * @brief flash2 init
+ *
+ * @return int
+ */
+static int ATTR_TCM_SECTION flash2_init(void)
+{
+    int stat = -1;
+    uint32_t ret = 0;
+    uint32_t jid = 0;
+
+    struct sf_ctrl_bank2_cfg sf_bank2_cfg;
+    struct sf_ctrl_cmds_cfg cmds_cfg;
+
+    sf_bank2_cfg.sbus2_select = 1;
+    sf_bank2_cfg.bank2_rx_clk_invert_src = 0;
+    sf_bank2_cfg.bank2_rx_clk_invert_sel = 0;
+    sf_bank2_cfg.bank2_delay_src = 0;
+    sf_bank2_cfg.bank2_clk_delay = 1;
+    sf_bank2_cfg.do_delay = 0;
+    sf_bank2_cfg.di_delay = 0;
+    sf_bank2_cfg.oe_delay = 0;
+    sf_bank2_cfg.remap = SF_CTRL_REMAP_4MB;
+    sf_bank2_cfg.remap_lock = 1;
+
+    cmds_cfg.ack_latency = 1;
+    cmds_cfg.cmds_core_en = 1;
+    cmds_cfg.cmds_en = 1;
+    cmds_cfg.cmds_wrap_mode = 1;
+    cmds_cfg.cmds_wrap_len = SF_CTRL_WRAP_LEN_4096;
+
+    if (deviceInfo.memoryInfo == 0) {
+        /* memoryInfo==0, external flash */
+        flash1_size = 64 * 1024 * 1024;
+        flash2_size = 0;
+    } else if (deviceInfo.memoryInfo == 1) {
+        flash1_size = 2 * 1024 * 1024;
+        flash2_size = 0;
+    } else if (deviceInfo.memoryInfo == 2) {
+        flash1_size = 4 * 1024 * 1024;
+        flash2_size = 0;
+    } else if (deviceInfo.memoryInfo == 3) {
+        /* memoryInfo==3, embedded 4MB+2MB flash */
+        flash1_size = 4 * 1024 * 1024;
+        flash2_size = 2 * 1024 * 1024;
+    } else {
+        flash1_size = 8 * 1024 * 1024;
+        flash2_size = 0;
+    }
+
+    if (flash2_size > 0) {
+        bflb_sf_cfg_sbus2_flash_init(SF_IO_EMB_SWAP_IO3IO0_AND_SF2, &sf_bank2_cfg);
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        ret = bflb_sf_cfg_flash_identify_ext(0, SF_IO_EMB_SWAP_IO3IO0_AND_SF2, 0, &g_flash2_cfg, 0, SF_CTRL_FLASH_BANK1);
+        if ((ret & BFLB_FLASH_ID_VALID_FLAG) == 0) {
+            return -1;
+        }
+        g_flash2_cfg.io_mode = 0x11;
+        g_flash2_cfg.c_read_support = 0;
+        g_flash2_cfg.c_read_mode = 0xff;
+        bflb_sflash_get_jedecid(&g_flash2_cfg, (uint8_t *)&jid);
+        jid &= 0xFFFFFF;
+        g_jedec_id2 = jid;
+
+        bflb_sf_ctrl_cmds_set(&cmds_cfg, SF_CTRL_FLASH_BANK1);
+        stat = bflb_sflash_xip_read_enable(&g_flash2_cfg, (g_flash2_cfg.io_mode & 0xf), 0, SF_CTRL_FLASH_BANK1);
+        if (0 != stat) {
+            return -1;
+        }
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    }
+
+    return 0;
+}
+#endif
+
+/**
+ * @brief multi flash adapter
+ *
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_init(void)
+{
+    int ret = -1;
+    uint32_t jedec_id = 0;
+#if defined(BL602) || defined(BL702)
+    uint8_t clk_delay = 1;
+    uint8_t clk_invert = 1;
+    uintptr_t flag;
+#endif
+
+#if defined(BL616)
+    bflb_ef_ctrl_get_device_info(&deviceInfo);
+#endif
+
+#if defined(BL602) || defined(BL702)
+    flag = bflb_irq_save();
+#if defined(BL602)
+    bflb_sflash_cache_flush();
+#else
+    L1C_Cache_Flush();
+#endif
+    bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
+#if defined(BL602)
+    bflb_sflash_cache_flush();
+#else
+    L1C_Cache_Flush();
+#endif
+    bflb_irq_restore(flag);
+    if (g_flash_cfg.mid != 0xff && g_flash_cfg.mid != 0x00) {
+        return 0;
+    }
+    clk_delay = g_flash_cfg.clk_delay;
+    clk_invert = g_flash_cfg.clk_invert;
+    g_flash_cfg.io_mode &= 0x0f;
+
+    ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
+
+    g_flash_cfg.clk_delay = clk_delay;
+    g_flash_cfg.clk_invert = clk_invert;
+#else
+    jedec_id = GLB_Get_Flash_Id_Value();
+    if (jedec_id != 0) {
+        ret = bflb_sf_cfg_get_flash_cfg_need_lock_ext(jedec_id, &g_flash_cfg, 0, 0);
+        if (ret == 0) {
+            g_jedec_id = jedec_id;
+            g_flash_cfg.io_mode &= 0x0f;
+            flash_get_clock_delay(&g_flash_cfg);
+#if defined(BL616)
+            flash2_init();
+#endif
+            return 0;
+        }
+    }
+
+    g_flash_cfg.io_mode &= 0x0f;
+    ret = flash_config_init(&g_flash_cfg, (uint8_t *)&jedec_id);
+
+    g_flash_cfg.io_mode &= 0x0f;
+    flash_get_clock_delay(&g_flash_cfg);
+    GLB_Set_Flash_Id_Value(g_jedec_id);
+#endif
+
+#if defined(BL616)
+    flash2_init();
+#endif
+
+    return ret;
+}
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+void ATTR_TCM_SECTION bflb_flash_set_cmds(spi_flash_cfg_type *p_flash_cfg)
+{
+    struct sf_ctrl_cmds_cfg cmds_cfg;
+
+    cmds_cfg.ack_latency = 1;
+    cmds_cfg.cmds_core_en = 1;
+    cmds_cfg.cmds_en = 1;
+    cmds_cfg.cmds_wrap_mode = 1;
+    cmds_cfg.cmds_wrap_len = 9;
+
+    if ((p_flash_cfg->io_mode & 0x1f) == SF_CTRL_QIO_MODE) {
+        cmds_cfg.cmds_wrap_mode = 2;
+        cmds_cfg.cmds_wrap_len = 2;
+    }
+    bflb_sf_ctrl_cmds_set(&cmds_cfg, 0);
+}
+#endif
+
+uint32_t bflb_flash_get_jedec_id(void)
+{
+    uint32_t jid = 0;
+
+    jid = ((g_jedec_id & 0xff) << 16) + (g_jedec_id & 0xff00) + ((g_jedec_id & 0xff0000) >> 16);
+    return jid;
+}
+
+void bflb_flash_get_cfg(uint8_t **cfg_addr, uint32_t *len)
+{
+    *cfg_addr = (uint8_t *)&g_flash_cfg;
+    *len = sizeof(spi_flash_cfg_type);
+}
+
+void ATTR_TCM_SECTION bflb_flash_set_iomode(uint8_t iomode)
+{
+    uintptr_t flag = 0;
+    uint8_t is_aes_enable = 0;
+    uint32_t offset = 0;
+
+    flag = bflb_irq_save();
+    bflb_xip_sflash_opt_enter(&is_aes_enable);
+    bflb_xip_sflash_state_save(&g_flash_cfg, &offset, 0, 0);
+
+    g_flash_cfg.io_mode &= ~0x1f;
+    if (iomode&4) {
+        g_flash_cfg.io_mode |= iomode;
+    } else {
+        g_flash_cfg.io_mode |= 0x10;
+        g_flash_cfg.io_mode |= iomode;
+    }
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+    bflb_flash_set_cmds(&g_flash_cfg);
+#endif
+    flash_set_qspi_enable(&g_flash_cfg);
+    flash_set_l1c_wrap(&g_flash_cfg);
+#if defined(BL602)
+    bflb_xip_sflash_state_restore_ext(&g_flash_cfg, offset, 0, 0);
+#else
+    bflb_xip_sflash_state_restore(&g_flash_cfg, offset, 0, 0);
+#endif
+    bflb_xip_sflash_opt_exit(is_aes_enable);
+    bflb_irq_restore(flag);
+}
+
+ATTR_TCM_SECTION uint32_t bflb_flash_get_image_offset(void)
+{
+    return bflb_sf_ctrl_get_flash_image_offset(0, 0);
+}
+
+/**
+ * @brief erase flash via sbus
+ *
+ * @param flash absolute startaddr
+ * @param flash absolute endaddr
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_erase(uint32_t startaddr, uint32_t len)
+{
+    int stat = -1;
+    uintptr_t flag;
+
+#if defined(BL616)
+    if ((startaddr + len) > (flash1_size + flash2_size)) {
+        return -ENOMEM;
+    } else if ((startaddr + len) <= flash1_size) {
+        flag = bflb_irq_save();
+        stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
+        bflb_irq_restore(flag);
+    } else if (startaddr >= flash1_size) {
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        stat = bflb_sflash_erase(&g_flash2_cfg, startaddr, startaddr + len - 1);
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    } else {
+        flag = bflb_irq_save();
+        stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, flash1_size - startaddr, 0, 0);
+        bflb_irq_restore(flag);
+        if (stat != 0) {
+            return stat;
+        }
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        stat = bflb_sflash_erase(&g_flash2_cfg, flash1_size, startaddr + len - flash1_size - 1);
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    }
+#else
+    if (startaddr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
+        return -ENOMEM;
+    }
+
+    flag = bflb_irq_save();
+#if defined(BL602)
+    stat = bflb_xip_sflash_erase_need_lock_ext(&g_flash_cfg, startaddr, startaddr+len-1, 0, 0);
+#elif defined(BL702)
+    uint8_t aes_enabled = 0;
+    bflb_xip_sflash_opt_enter(&aes_enabled);
+    stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
+    bflb_xip_sflash_opt_exit(aes_enabled);
+#else
+    stat = bflb_xip_sflash_erase_need_lock(&g_flash_cfg, startaddr, len, 0, 0);
+#endif
+    bflb_irq_restore(flag);
+#endif
+
+    return stat;
+}
+
+/**
+ * @brief write flash data via sbus
+ *
+ * @param flash absolute addr
+ * @param data
+ * @param len
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_write(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    int stat = -1;
+    uintptr_t flag;
+
+#if defined(BL616)
+    if ((addr + len) > (flash1_size + flash2_size)) {
+        return -ENOMEM;
+    } else if ((addr + len) <= flash1_size) {
+        flag = bflb_irq_save();
+        stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+        bflb_irq_restore(flag);
+    } else if (addr >= flash1_size) {
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, addr, data, len);
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    } else {
+        flag = bflb_irq_save();
+        stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
+        bflb_irq_restore(flag);
+        if (stat != 0) {
+            return stat;
+        }
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        stat = bflb_sflash_program(&g_flash2_cfg, SF_CTRL_DO_MODE, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    }
+#else
+    if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
+        return -ENOMEM;
+    }
+
+    flag = bflb_irq_save();
+#if defined(BL602)
+    stat = bflb_xip_sflash_write_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
+#elif defined(BL702)
+    uint8_t aes_enabled = 0;
+    bflb_xip_sflash_opt_enter(&aes_enabled);
+    stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+    bflb_xip_sflash_opt_exit(aes_enabled);
+#else
+    stat = bflb_xip_sflash_write_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+#endif
+    bflb_irq_restore(flag);
+#endif
+
+    return stat;
+}
+
+/**
+ * @brief read flash data via sbus
+ *
+ * @param flash absolute addr
+ * @param data
+ * @param len
+ * @return int
+ */
+int ATTR_TCM_SECTION bflb_flash_read(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    int stat = -1;
+    uintptr_t flag;
+
+#if defined(BL616)
+    if ((addr + len) > (flash1_size + flash2_size)) {
+        return -ENOMEM;
+    } else if ((addr + len) <= flash1_size) {
+        flag = bflb_irq_save();
+        stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+        bflb_irq_restore(flag);
+    } else if (addr >= flash1_size) {
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, addr, data, len);
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    } else {
+        flag = bflb_irq_save();
+        stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, flash1_size - addr, 0, 0);
+        bflb_irq_restore(flag);
+        if (stat != 0) {
+            return stat;
+        }
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        stat = bflb_sflash_read(&g_flash2_cfg, SF_CTRL_DO_MODE, 0, flash1_size, data + (flash1_size - addr), addr + len - flash1_size);
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    }
+#else
+    if (addr >= BFLB_FLASH_XIP_END - BFLB_FLASH_XIP_BASE) {
+        return -ENOMEM;
+    }
+
+    flag = bflb_irq_save();
+#if defined(BL602)
+    stat = bflb_xip_sflash_read_need_lock_ext(&g_flash_cfg, addr, data, len, 0, 0);
+#elif defined(BL702)
+    uint8_t aes_enabled = 0;
+    bflb_xip_sflash_opt_enter(&aes_enabled);
+    stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+    bflb_xip_sflash_opt_exit(aes_enabled);
+#else
+    stat = bflb_xip_sflash_read_need_lock(&g_flash_cfg, addr, data, len, 0, 0);
+#endif
+    bflb_irq_restore(flag);
+#endif
+
+    return stat;
+}
+
+int ATTR_TCM_SECTION bflb_flash_set_cache(uint8_t cont_read, uint8_t cache_enable, uint8_t cache_way_disable, uint32_t flash_offset)
+{
+    uint8_t is_aes_enable = 0;
+    uint32_t tmp[1];
+    int stat;
+
+    bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+
+    bflb_xip_sflash_opt_enter(&is_aes_enable);
+    /* To make it simple, exit cont read anyway */
+    bflb_sflash_reset_continue_read(&g_flash_cfg);
+
+    if (g_flash_cfg.c_read_support == 0) {
+        cont_read = 0;
+    }
+
+    if (cont_read == 1) {
+        stat = bflb_sflash_read(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+
+        if (0 != stat) {
+            bflb_xip_sflash_opt_exit(is_aes_enable);
+            return -1;
+        }
+    }
+
+#if defined(BL602) || defined(BL702)
+#if defined(BL602)
+    bflb_sflash_cache_enable_set(0xf);
+#else
+    L1C_Cache_Enable_Set(0xf);
+#endif
+
+    if (cache_enable) {
+        bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
+        bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
+    }
+#if defined(BL602)
+    bflb_sflash_cache_enable_set(cache_way_disable);
+#else
+    L1C_Cache_Enable_Set(cache_way_disable);
+#endif
+#else
+    bflb_sf_ctrl_set_flash_image_offset(flash_offset, 0, 0);
+    bflb_sflash_xip_read_enable(&g_flash_cfg, g_flash_cfg.io_mode & 0xf, cont_read, 0);
+#endif
+
+    bflb_xip_sflash_opt_exit(is_aes_enable);
+
+    return 0;
+}
+
+void bflb_flash_aes_init(struct bflb_flash_aes_config_s *config)
+{
+    uint8_t hw_key_enable = 0;
+
+    if (config->key == NULL) {
+        hw_key_enable = 1;
+    }
+
+    bflb_sf_ctrl_aes_set_key_be(config->region, (uint8_t *)config->key, config->keybits);
+    bflb_sf_ctrl_aes_set_iv_be(config->region, (uint8_t *)config->iv, config->start_addr);
+    bflb_sf_ctrl_aes_set_region(config->region, config->region_enable, hw_key_enable, config->start_addr, config->end_addr - 1, config->lock_enable);
+}
+
+void bflb_flash_aes_enable(void)
+{
+    bflb_sf_ctrl_aes_enable();
+}
+
+void bflb_flash_aes_disable(void)
+{
+    bflb_sf_ctrl_aes_disable();
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c
new file mode 100755
index 0000000000..cd8f5282c6
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_gpio.c
@@ -0,0 +1,447 @@
+#include "bflb_gpio.h"
+#include "hardware/gpio_reg.h"
+
+void bflb_gpio_init(struct bflb_device_s *dev, uint8_t pin, uint32_t cfgset)
+{
+    uint32_t cfg = 0;
+    uint32_t reg_base;
+    uint32_t cfg_address;
+    uint8_t drive;
+    uint8_t function;
+    uint16_t mode;
+
+    reg_base = dev->reg_base;
+
+    function = (cfgset & GPIO_FUNC_MASK) >> GPIO_FUNC_SHIFT;
+    mode = (cfgset & GPIO_MODE_MASK);
+    drive = (cfgset & GPIO_DRV_MASK) >> GPIO_DRV_SHIFT;
+
+#if defined(BL616)
+    /* disable muxed to be xtal32k */
+    if (pin == GPIO_PIN_16) {
+        *(volatile uint32_t *)(0x2000f000 + 0x38) &= ~(1 << 20);
+    } else if (pin == GPIO_PIN_17) {
+        *(volatile uint32_t *)(0x2000f000 + 0x38) &= ~(1 << 21);
+    }
+#endif
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    uint32_t regval;
+    uint8_t is_odd = 0;
+
+    regval = getreg32(reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+    regval &= ~(1 << (pin & 0x1f));
+    putreg32(regval, reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+
+    is_odd = (pin % 2);
+
+    cfg_address = reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4);
+    cfg = getreg32(cfg_address);
+    cfg &= ~(0xffff << (16 * is_odd));
+
+    regval = getreg32(reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+    if (mode == GPIO_INPUT) {
+        cfg |= (1 << (is_odd * 16 + 0));
+        regval &= ~(1 << (pin & 0x1f));
+        function = 11;
+    } else if (mode == GPIO_OUTPUT) {
+        regval |= (1 << (pin & 0x1f));
+        function = 11;
+#if defined(BL702L)
+        if (function == 22) {
+            regval &= ~(1 << (pin & 0x1f));
+        }
+#endif
+    } else if (mode == GPIO_ANALOG) {
+        regval &= ~(1 << (pin & 0x1f));
+        function = 10;
+    } else if (mode == GPIO_ALTERNATE) {
+        cfg |= (1 << (is_odd * 16 + 0));
+#if defined(BL702L)
+        if (function == 22) {
+            cfg &= ~(1 << (is_odd * 16 + 0));
+        }
+#endif
+        regval &= ~(1 << (pin & 0x1f));
+    } else {
+    }
+    putreg32(regval, reg_base + GLB_GPIO_CFGCTL34_OFFSET + ((pin >> 5) << 2));
+
+    if (cfgset & GPIO_PULLUP) {
+        cfg |= (1 << (is_odd * 16 + 4));
+    } else if (cfgset & GPIO_PULLDOWN) {
+        cfg |= (1 << (is_odd * 16 + 5));
+    } else {
+    }
+
+    if (cfgset & GPIO_SMT_EN) {
+        cfg |= (1 << (is_odd * 16 + 1));
+    }
+
+    cfg |= (drive << (is_odd * 16 + 2));
+    cfg |= (function << (is_odd * 16 + 8));
+#if defined(BL702L)
+    /* configure output mode:set and clr mode */
+    if ((function != 22) || (function != 21)) {
+        cfg |= (1 << (is_odd * 16 + 15));
+    }
+#endif
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+    cfg = 0;
+    cfg |= GLB_REG_GPIO_0_INT_MASK;
+
+    if (mode == GPIO_INPUT) {
+        cfg |= GLB_REG_GPIO_0_IE;
+        function = 11;
+    } else if (mode == GPIO_OUTPUT) {
+        cfg |= GLB_REG_GPIO_0_OE;
+        function = 11;
+    } else if (mode == GPIO_ANALOG) {
+        function = 10;
+    } else if (mode == GPIO_ALTERNATE) {
+        cfg |= GLB_REG_GPIO_0_IE;
+    } else {
+    }
+
+    if (cfgset & GPIO_PULLUP) {
+        cfg |= GLB_REG_GPIO_0_PU;
+    } else if (cfgset & GPIO_PULLDOWN) {
+        cfg |= GLB_REG_GPIO_0_PD;
+    } else {
+    }
+
+    if (cfgset & GPIO_SMT_EN) {
+        cfg |= GLB_REG_GPIO_0_SMT;
+    }
+
+    cfg |= (drive << GLB_REG_GPIO_0_DRV_SHIFT);
+    cfg |= (function << GLB_REG_GPIO_0_FUNC_SEL_SHIFT);
+
+    /* configure output mode:set and clr mode */
+    cfg |= 0x1 << GLB_REG_GPIO_0_MODE_SHIFT;
+#endif
+    putreg32(cfg, cfg_address);
+}
+
+void bflb_gpio_deinit(struct bflb_device_s *dev, uint8_t pin)
+{
+    bflb_gpio_init(dev, pin, GPIO_INPUT | GPIO_FLOAT);
+}
+
+void bflb_gpio_set(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602)
+    uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+    putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+#elif defined(BL702L)
+    uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
+    putreg32(regval | 1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFGCTL35_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG138_OFFSET + ((pin >> 5) << 2));
+#endif
+}
+
+void bflb_gpio_reset(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602)
+    uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+    putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+#elif defined(BL702L)
+    uint32_t regval = getreg32(dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
+    putreg32(regval & ~(1 << (pin & 0x1f)), dev->reg_base + GLB_GPIO_CFGCTL36_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    putreg32(1 << (pin & 0x1f), dev->reg_base + GLB_GPIO_CFG140_OFFSET + ((pin >> 5) << 2));
+#endif
+}
+
+bool bflb_gpio_read(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET) & (1 << pin));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_REG_GPIO_0_I);
+#endif
+}
+
+void bflb_gpio_pin0_31_write(struct bflb_device_s *dev, uint32_t val)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL32_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    putreg32(val, dev->reg_base + GLB_GPIO_CFG136_OFFSET);
+#endif
+}
+
+void bflb_gpio_pin32_63_write(struct bflb_device_s *dev, uint32_t val)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    putreg32(val, dev->reg_base + GLB_GPIO_CFGCTL33_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    putreg32(val, dev->reg_base + GLB_GPIO_CFG137_OFFSET);
+#endif
+}
+
+uint32_t bflb_gpio_pin0_31_read(struct bflb_device_s *dev)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL30_OFFSET));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    return (getreg32(dev->reg_base + GLB_GPIO_CFG128_OFFSET));
+#endif
+}
+
+uint32_t bflb_gpio_pin32_63_read(struct bflb_device_s *dev)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    return (getreg32(dev->reg_base + GLB_GPIO_CFGCTL31_OFFSET));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    return (getreg32(dev->reg_base + GLB_GPIO_CFG129_OFFSET));
+#endif
+}
+
+void bflb_gpio_int_init(struct bflb_device_s *dev, uint8_t pin, uint8_t trig_mode)
+{
+    uint32_t reg_base;
+    uint32_t cfg_address;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    bflb_gpio_init(dev, pin, GPIO_INPUT | GPIO_FLOAT);
+
+    bflb_gpio_int_mask(dev, pin, true);
+    bflb_gpio_int_clear(dev, pin);
+
+#if defined(BL702) || defined(BL602)
+    cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 10) << 2);
+    regval = getreg32(cfg_address);
+    regval &= ~(0x07 << ((pin % 10) * 3));
+    regval |= (trig_mode << ((pin % 10) * 3));
+#elif defined(BL702L)
+    cfg_address = reg_base + GLB_GPIO_INT_MODE_SET1_OFFSET + ((pin / 8) << 2);
+    regval = getreg32(cfg_address);
+    regval &= ~(0x0f << ((pin % 8) * 4));
+    regval |= (trig_mode << ((pin % 8) * 4));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+    regval = getreg32(cfg_address);
+    regval &= ~GLB_REG_GPIO_0_INT_MODE_SET_MASK;
+    regval |= (trig_mode << GLB_REG_GPIO_0_INT_MODE_SET_SHIFT);
+#endif
+    putreg32(regval, cfg_address);
+}
+
+void bflb_gpio_int_mask(struct bflb_device_s *dev, uint8_t pin, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t cfg_address;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    cfg_address = reg_base + GLB_GPIO_INT_MASK1_OFFSET;
+
+    regval = getreg32(cfg_address);
+    if (mask) {
+        regval |= (1 << pin);
+    } else {
+        regval &= ~(1 << pin);
+    }
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+
+    regval = getreg32(cfg_address);
+    if (mask) {
+        regval |= GLB_REG_GPIO_0_INT_MASK;
+    } else {
+        regval &= ~GLB_REG_GPIO_0_INT_MASK;
+    }
+#endif
+    putreg32(regval, cfg_address);
+}
+
+bool bflb_gpio_get_intstatus(struct bflb_device_s *dev, uint8_t pin)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    return (getreg32(dev->reg_base + GLB_GPIO_INT_STAT1_OFFSET) & (1 << pin));
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    return (getreg32(dev->reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_GPIO_0_INT_STAT);
+#endif
+}
+
+void bflb_gpio_int_clear(struct bflb_device_s *dev, uint8_t pin)
+{
+    uint32_t reg_base;
+    uint32_t cfg_address;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    cfg_address = reg_base + GLB_GPIO_INT_CLR1_OFFSET;
+
+    regval = getreg32(cfg_address);
+    regval |= (1 << pin);
+    putreg32(regval, cfg_address);
+    regval &= ~(1 << pin);
+    putreg32(regval, cfg_address);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+    cfg_address = reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2);
+
+    regval = getreg32(cfg_address);
+    regval |= GLB_REG_GPIO_0_INT_CLR;
+    putreg32(regval, cfg_address);
+    regval &= ~GLB_REG_GPIO_0_INT_CLR;
+    putreg32(regval, cfg_address);
+#endif
+}
+
+void bflb_gpio_uart_init(struct bflb_device_s *dev, uint8_t pin, uint8_t uart_func)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint8_t sig;
+    uint8_t sig_pos;
+
+    reg_base = dev->reg_base;
+#if defined(BL702) || defined(BL602)
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+    regval = getreg32(reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+
+    sig = pin % 8;
+    sig_pos = sig << 2;
+
+    regval &= (~(0x0f << sig_pos));
+    regval |= (uart_func << sig_pos);
+
+    for (uint8_t i = 0; i < 8; i++) {
+        /* reset other sigs which are the same with uart_func */
+        sig_pos = i << 2;
+        if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+            regval &= (~(0x0f << sig_pos));
+            regval |= (0x0f << sig_pos);
+        }
+    }
+
+    putreg32(regval, reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+#elif defined(BL702L)
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+    regval = getreg32(reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+
+    sig = pin % 4;
+    sig_pos = sig << 2;
+
+    regval &= (~(0x0f << sig_pos));
+    regval |= (uart_func << sig_pos);
+
+    for (uint8_t i = 0; i < 4; i++) {
+        /* reset other sigs which are the same with uart_func */
+        sig_pos = i << 2;
+        if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+            regval &= (~(0x0f << sig_pos));
+            regval |= (0x0f << sig_pos);
+        }
+    }
+
+    putreg32(regval, reg_base + GLB_UART_SIG_SEL_0_OFFSET);
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+#define GLB_UART_CFG1_OFFSET (0x154)
+#define GLB_UART_CFG2_OFFSET (0x158)
+    uint32_t regval2;
+    sig = pin % 12;
+
+    if (sig < 8) {
+        sig_pos = sig << 2;
+
+        regval = getreg32(reg_base + GLB_UART_CFG1_OFFSET);
+        regval &= (~(0x0f << sig_pos));
+        regval |= (uart_func << sig_pos);
+
+        for (uint8_t i = 0; i < 8; i++) {
+            /* reset other sigs which are the same with uart_func */
+            sig_pos = i << 2;
+            if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+                regval &= (~(0x0f << sig_pos));
+                regval |= (0x0f << sig_pos);
+            }
+        }
+        regval2 = getreg32(reg_base + GLB_UART_CFG2_OFFSET);
+
+        for (uint8_t i = 8; i < 12; i++) {
+            /* reset other sigs which are the same with uart_func */
+            sig_pos = (i - 8) << 2;
+            if (((regval2 & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+                regval2 &= (~(0x0f << sig_pos));
+                regval2 |= (0x0f << sig_pos);
+            }
+        }
+        putreg32(regval, reg_base + GLB_UART_CFG1_OFFSET);
+        putreg32(regval2, reg_base + GLB_UART_CFG2_OFFSET);
+    } else {
+        sig_pos = (sig - 8) << 2;
+
+        regval = getreg32(reg_base + GLB_UART_CFG2_OFFSET);
+        regval &= (~(0x0f << sig_pos));
+        regval |= (uart_func << sig_pos);
+
+        for (uint8_t i = 8; i < 12; i++) {
+            /* reset other sigs which are the same with uart_func */
+            sig_pos = (i - 8) << 2;
+            if (((regval & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+                regval &= (~(0x0f << sig_pos));
+                regval |= (0x0f << sig_pos);
+            }
+        }
+        regval2 = getreg32(reg_base + GLB_UART_CFG1_OFFSET);
+
+        for (uint8_t i = 0; i < 8; i++) {
+            /* reset other sigs which are the same with uart_func */
+            sig_pos = i << 2;
+            if (((regval2 & (0x0f << sig_pos)) == (uart_func << sig_pos)) && (i != sig) && (uart_func != 0x0f)) {
+                regval2 &= (~(0x0f << sig_pos));
+                regval2 |= (0x0f << sig_pos);
+            }
+        }
+        putreg32(regval, reg_base + GLB_UART_CFG2_OFFSET);
+        putreg32(regval2, reg_base + GLB_UART_CFG1_OFFSET);
+    }
+#endif
+    bflb_gpio_init(dev, pin, (7 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+}
+
+#if defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+void bflb_gpio_iso11898_init(struct bflb_device_s *dev, uint8_t pin, uint8_t iso11898_func)
+{
+    bflb_gpio_uart_init(dev, pin, iso11898_func);
+}
+#endif
+
+int bflb_gpio_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+    uint8_t pin = arg;
+
+    reg_base = dev->reg_base;
+    switch (cmd) {
+        case GPIO_CMD_GET_GPIO_FUN:
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+            if ((pin % 2)) {
+                regval = getreg32(reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4)) & GLB_REG_GPIO_0_FUNC_SEL_MASK;
+                regval >>= GLB_REG_GPIO_0_FUNC_SEL_SHIFT;
+            } else {
+                regval = getreg32(reg_base + GLB_GPIO_CFGCTL0_OFFSET + (pin / 2 * 4)) & GLB_REG_GPIO_1_FUNC_SEL_MASK;
+                regval >>= GLB_REG_GPIO_1_FUNC_SEL_SHIFT;
+            }
+#elif defined(BL616) || defined(BL808) || defined(BL606P) || defined(BL628)
+            regval = getreg32(reg_base + GLB_GPIO_CFG0_OFFSET + (pin << 2)) & GLB_REG_GPIO_0_FUNC_SEL_MASK;
+            regval >>= GLB_REG_GPIO_0_FUNC_SEL_SHIFT;
+#endif
+            return regval;
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c
new file mode 100755
index 0000000000..a82ef5fdb5
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2c.c
@@ -0,0 +1,456 @@
+#include "bflb_i2c.h"
+#include "bflb_clock.h"
+#include "hardware/i2c_reg.h"
+
+#define PUT_UINT32_LE(field, value)            \
+    do {                                       \
+        (field)[0] = (uint8_t)((value) >> 0);  \
+        (field)[1] = (uint8_t)((value) >> 8);  \
+        (field)[2] = (uint8_t)((value) >> 16); \
+        (field)[3] = (uint8_t)((value) >> 24); \
+    } while (0)
+
+static void bflb_i2c_addr_config(struct bflb_device_s *dev, uint16_t slaveaddr, uint16_t subaddr, uint8_t subaddr_size, bool is_addr_10bit)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+
+    if (subaddr_size > 0) {
+        regval |= I2C_CR_I2C_SUB_ADDR_EN;
+        regval &= ~I2C_CR_I2C_SUB_ADDR_BC_MASK;
+        regval |= ((subaddr_size - 1) << I2C_CR_I2C_SUB_ADDR_BC_SHIFT);
+    } else {
+        regval &= ~I2C_CR_I2C_SUB_ADDR_EN;
+    }
+
+    regval &= ~I2C_CR_I2C_SLV_ADDR_MASK;
+    regval |= (slaveaddr << I2C_CR_I2C_SLV_ADDR_SHIFT);
+#if !defined(BL602) && !defined(BL702)
+    if (is_addr_10bit) {
+        regval |= I2C_CR_I2C_10B_ADDR_EN;
+    } else {
+        regval &= ~I2C_CR_I2C_10B_ADDR_EN;
+    }
+#endif
+    regval &= ~I2C_CR_I2C_SCL_SYNC_EN;
+    putreg32(subaddr, reg_base + I2C_SUB_ADDR_OFFSET);
+    putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static inline void bflb_i2c_set_dir(struct bflb_device_s *dev, bool is_in)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+
+    if (is_in) {
+        regval |= I2C_CR_I2C_PKT_DIR;
+    } else {
+        regval &= ~I2C_CR_I2C_PKT_DIR;
+    }
+    putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static inline void bflb_i2c_set_datalen(struct bflb_device_s *dev, uint16_t data_len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+    regval &= ~I2C_CR_I2C_PKT_LEN_MASK;
+    regval |= ((data_len - 1) << I2C_CR_I2C_PKT_LEN_SHIFT) & I2C_CR_I2C_PKT_LEN_MASK;
+    putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static void bflb_i2c_set_frequence(struct bflb_device_s *dev, uint32_t freq)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint32_t phase;
+
+    reg_base = dev->reg_base;
+
+    phase = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2C, dev->idx) / (freq * 4) - 1;
+
+    regval = phase << I2C_CR_I2C_PRD_S_PH_0_SHIFT;
+    regval |= phase << I2C_CR_I2C_PRD_S_PH_1_SHIFT;
+    regval |= phase << I2C_CR_I2C_PRD_S_PH_2_SHIFT;
+    regval |= phase << I2C_CR_I2C_PRD_S_PH_3_SHIFT;
+
+    putreg32(regval, reg_base + I2C_PRD_START_OFFSET);
+    putreg32(regval, reg_base + I2C_PRD_STOP_OFFSET);
+    putreg32(regval, reg_base + I2C_PRD_DATA_OFFSET);
+}
+
+static inline bool bflb_i2c_isbusy(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_BUS_BUSY_OFFSET);
+
+    if (regval & I2C_STS_I2C_BUS_BUSY) {
+        return true;
+    }
+
+    return false;
+}
+
+static inline bool bflb_i2c_isend(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+
+    if (regval & I2C_END_INT) {
+        return true;
+    }
+
+    return false;
+}
+
+static inline void bflb_i2c_enable(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+    regval |= I2C_CR_I2C_M_EN;
+    putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+}
+
+static inline void bflb_i2c_disable(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+    regval &= ~I2C_CR_I2C_M_EN;
+    putreg32(regval, reg_base + I2C_CONFIG_OFFSET);
+    /* Clear I2C fifo */
+    regval = getreg32(reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+    regval |= I2C_TX_FIFO_CLR;
+    regval |= I2C_RX_FIFO_CLR;
+    putreg32(regval, reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+    /* Clear I2C interrupt status */
+    regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+    regval |= I2C_CR_I2C_END_CLR;
+    regval |= I2C_CR_I2C_NAK_CLR;
+    regval |= I2C_CR_I2C_ARB_CLR;
+    putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+static inline bool bflb_i2c_isenable(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2C_CONFIG_OFFSET);
+    if (regval & I2C_CR_I2C_M_EN) {
+        return true;
+    }
+
+    return false;
+}
+
+static int bflb_i2c_write_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+    uint32_t reg_base;
+    uint32_t temp = 0;
+    uint8_t *tmp_buf;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    tmp_buf = data;
+    while (len >= 4) {
+        for (uint8_t i = 0; i < 4; i++) {
+            temp += (tmp_buf[i] << ((i % 4) * 8));
+        }
+        tmp_buf += 4;
+        len -= 4;
+        start_time = bflb_mtimer_get_time_ms();
+        while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_TX_FIFO_CNT_MASK) == 0) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+        putreg32(temp, reg_base + I2C_FIFO_WDATA_OFFSET);
+        if (!bflb_i2c_isenable(dev)) {
+            bflb_i2c_enable(dev);
+        }
+        temp = 0;
+    }
+
+    if (len > 0) {
+        for (uint8_t i = 0; i < len; i++) {
+            temp += (tmp_buf[i] << ((i % 4) * 8));
+        }
+        start_time = bflb_mtimer_get_time_ms();
+        while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_TX_FIFO_CNT_MASK) == 0) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+        putreg32(temp, reg_base + I2C_FIFO_WDATA_OFFSET);
+        if (!bflb_i2c_isenable(dev)) {
+            bflb_i2c_enable(dev);
+        }
+    }
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev)) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    bflb_i2c_disable(dev);
+
+    return 0;
+}
+
+static int bflb_i2c_read_bytes(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+    uint32_t reg_base;
+    uint32_t temp = 0;
+    uint8_t *tmp_buf;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    tmp_buf = data;
+
+    bflb_i2c_enable(dev);
+
+    while (len >= 4) {
+        start_time = bflb_mtimer_get_time_ms();
+        while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_RX_FIFO_CNT_MASK) == 0) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+        temp = getreg32(reg_base + I2C_FIFO_RDATA_OFFSET);
+        PUT_UINT32_LE(tmp_buf, temp);
+        tmp_buf += 4;
+        len -= 4;
+    }
+
+    if (len > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while ((getreg32(reg_base + I2C_FIFO_CONFIG_1_OFFSET) & I2C_RX_FIFO_CNT_MASK) == 0) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+        temp = getreg32(reg_base + I2C_FIFO_RDATA_OFFSET);
+
+        for (uint8_t i = 0; i < len; i++) {
+            tmp_buf[i] = (temp >> (i * 8)) & 0xff;
+        }
+    }
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (bflb_i2c_isbusy(dev) || !bflb_i2c_isend(dev)) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    bflb_i2c_disable(dev);
+
+    return 0;
+}
+
+void bflb_i2c_init(struct bflb_device_s *dev, uint32_t frequency)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    bflb_i2c_disable(dev);
+
+    regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+
+    regval |= (I2C_CR_I2C_END_MASK |
+               I2C_CR_I2C_TXF_MASK |
+               I2C_CR_I2C_RXF_MASK |
+               I2C_CR_I2C_NAK_MASK |
+               I2C_CR_I2C_ARB_MASK |
+               I2C_CR_I2C_FER_MASK);
+
+    putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+
+    bflb_i2c_set_frequence(dev, frequency);
+}
+
+void bflb_i2c_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    bflb_i2c_disable(dev);
+
+    regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+
+    regval |= (I2C_CR_I2C_END_MASK |
+               I2C_CR_I2C_TXF_MASK |
+               I2C_CR_I2C_RXF_MASK |
+               I2C_CR_I2C_NAK_MASK |
+               I2C_CR_I2C_ARB_MASK |
+               I2C_CR_I2C_FER_MASK);
+
+    putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+void bflb_i2c_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= I2C_DMA_TX_EN;
+    } else {
+        regval &= ~I2C_DMA_TX_EN;
+    }
+    putreg32(regval, reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_i2c_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= I2C_DMA_RX_EN;
+    } else {
+        regval &= ~I2C_DMA_RX_EN;
+    }
+    putreg32(regval, reg_base + I2C_FIFO_CONFIG_0_OFFSET);
+}
+
+int bflb_i2c_transfer(struct bflb_device_s *dev, struct bflb_i2c_msg_s *msgs, int count)
+{
+    uint16_t subaddr = 0;
+    uint16_t subaddr_size = 0;
+    bool is_addr_10bit = false;
+    int ret = 0;
+
+    bflb_i2c_disable(dev);
+
+    for (uint16_t i = 0; i < count; i++) {
+        if (msgs[i].flags & I2C_M_TEN) {
+            is_addr_10bit = true;
+        } else {
+            is_addr_10bit = false;
+        }
+        if (msgs[i].flags & I2C_M_NOSTOP) {
+            subaddr = 0;
+            for (uint8_t j = 0; j < msgs[i].length; j++) {
+                subaddr += msgs[i].buffer[j] << (j * 8);
+            }
+            subaddr_size = msgs[i].length;
+            bflb_i2c_addr_config(dev, msgs[i].addr, subaddr, subaddr_size, is_addr_10bit);
+            i++;
+        } else {
+            subaddr = 0;
+            subaddr_size = 0;
+            bflb_i2c_addr_config(dev, msgs[i].addr, subaddr, subaddr_size, is_addr_10bit);
+        }
+
+        if (msgs[i].length > 256) {
+            return -EINVAL;
+        }
+        bflb_i2c_set_datalen(dev, msgs[i].length);
+        if (msgs[i].flags & I2C_M_READ) {
+            bflb_i2c_set_dir(dev, 1);
+            if ((msgs[i].flags & I2C_M_DMA) == 0) {
+                ret = bflb_i2c_read_bytes(dev, msgs[i].buffer, msgs[i].length);
+                if (ret < 0) {
+                    return ret;
+                }
+            } else {
+                bflb_i2c_enable(dev);
+            }
+        } else {
+            bflb_i2c_set_dir(dev, 0);
+            if ((msgs[i].flags & I2C_M_DMA) == 0) {
+                ret = bflb_i2c_write_bytes(dev, msgs[i].buffer, msgs[i].length);
+                if (ret < 0) {
+                    return ret;
+                }
+            } else {
+                bflb_i2c_enable(dev);
+            }
+        }
+    }
+
+    return 0;
+}
+
+void bflb_i2c_int_mask(struct bflb_device_s *dev, uint32_t int_type, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+    regval &= ~((int_type & 0xff) << 8);
+    if (mask) {
+        regval |= (int_type & 0xff) << 8;
+    }
+    putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+void bflb_i2c_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + I2C_INT_STS_OFFSET);
+    regval |= (int_clear & 0xff) << 16;
+    putreg32(regval, reg_base + I2C_INT_STS_OFFSET);
+}
+
+uint32_t bflb_i2c_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    return (getreg32(reg_base + I2C_INT_STS_OFFSET) & 0xff);
+}
+
+int bflb_i2c_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    switch (cmd) {
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2s.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2s.c
new file mode 100755
index 0000000000..95b1074a61
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_i2s.c
@@ -0,0 +1,341 @@
+#include "bflb_i2s.h"
+#include "bflb_clock.h"
+#include "hardware/i2s_reg.h"
+
+void bflb_i2s_init(struct bflb_device_s *dev, const struct bflb_i2s_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t div;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+    /* disable I2S */
+    regval &= ~I2S_CR_I2S_M_EN;
+    regval &= ~I2S_CR_I2S_S_EN;
+    regval &= ~I2S_CR_I2S_TXD_EN;
+    regval &= ~I2S_CR_I2S_TXD_EN;
+    putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+
+    if (config->channel_mode == I2S_CHANNEL_MODE_NUM_1) {
+        /* Mono mode */
+        regval |= I2S_CR_MONO_MODE;
+        regval &= ~I2S_CR_FS_CH_CNT_MASK;
+    } else {
+        regval &= ~I2S_CR_MONO_MODE;
+        regval &= ~I2S_CR_FS_CH_CNT_MASK;
+        regval |= (config->channel_mode - 1) << I2S_CR_FS_CH_CNT_SHIFT;
+    }
+
+    /* disable mute */
+    regval &= ~I2S_CR_MUTE_MODE;
+
+    if (config->format_mode == I2S_MODE_DSP_SHORT_FRAME_SYNC) {
+        /* dsp modeA/B short frame sync, there is only one bclk cycle */
+        regval |= I2S_CR_FS_1T_MODE;
+    } else {
+        regval &= ~I2S_CR_FS_1T_MODE;
+    }
+
+    /* frame/data width */
+    regval &= ~I2S_CR_FRAME_SIZE_MASK;
+    regval &= ~I2S_CR_DATA_SIZE_MASK;
+    regval |= config->frame_width << I2S_CR_FRAME_SIZE_SHIFT;
+    regval |= config->data_width << I2S_CR_DATA_SIZE_SHIFT;
+
+    if (config->format_mode == I2S_MODE_LEFT_JUSTIFIED) {
+        /* left justified*/
+        regval &= ~I2S_CR_I2S_MODE_MASK;
+    } else if (config->format_mode == I2S_MODE_RIGHT_JUSTIFIED) {
+        /* right justified*/
+        regval &= ~I2S_CR_I2S_MODE_MASK;
+        regval |= 1 << I2S_CR_I2S_MODE_SHIFT;
+    } else {
+        /* dsp mode */
+        regval &= ~I2S_CR_I2S_MODE_MASK;
+        regval |= 2 << I2S_CR_I2S_MODE_SHIFT;
+    }
+
+    /* fs_offset_cycle */
+    if (config->fs_offset_cycle) {
+        regval |= I2S_CR_OFS_EN;
+        regval &= ~I2S_CR_OFS_CNT_MASK;
+        regval |= ((config->fs_offset_cycle - 1) << I2S_CR_OFS_CNT_SHIFT) & I2S_CR_OFS_CNT_MASK;
+    } else {
+        regval &= ~I2S_CR_OFS_EN;
+    }
+
+    /* rx mono mode L-channel */
+    regval &= ~I2S_CR_MONO_RX_CH;
+    /* MSB */
+    regval &= ~I2S_CR_ENDIAN;
+
+    putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+
+    /* integer frequency segmentation by rounding */
+    div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_I2S, dev->idx) / 2 * 10 / config->bclk_freq_hz + 5) / 10;
+    div = (div) ? (div - 1) : 0;
+    div = (div > 0xfff) ? 0xfff : div;
+
+    /* bclk timing config */
+    regval = getreg32(reg_base + I2S_BCLK_CONFIG_OFFSET);
+    regval &= ~I2S_CR_BCLK_DIV_L_MASK;
+    regval &= ~I2S_CR_BCLK_DIV_H_MASK;
+    regval |= div << I2S_CR_BCLK_DIV_L_SHIFT;
+    regval |= div << I2S_CR_BCLK_DIV_H_SHIFT;
+    putreg32(regval, reg_base + I2S_BCLK_CONFIG_OFFSET);
+
+    /* fifo threshold config */
+    regval = getreg32(reg_base + I2S_FIFO_CONFIG_1_OFFSET);
+    regval &= ~I2S_TX_FIFO_TH_MASK;
+    regval &= ~I2S_RX_FIFO_TH_MASK;
+    regval |= (config->tx_fifo_threshold << I2S_TX_FIFO_TH_SHIFT) & I2S_TX_FIFO_TH_MASK;
+    regval |= (config->tx_fifo_threshold << I2S_RX_FIFO_TH_SHIFT) & I2S_RX_FIFO_TH_MASK;
+    putreg32(regval, reg_base + I2S_FIFO_CONFIG_1_OFFSET);
+
+    regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+    /* 32bit to 24bit */
+    regval &= ~I2S_CR_FIFO_24B_LJ;
+    /* Exchange L/R channel data */
+    regval &= ~I2S_CR_FIFO_LR_EXCHG;
+    /* Each FIFO entry contains both L/R channel data */
+    regval &= ~I2S_CR_FIFO_LR_MERGE;
+    /* disable dma */
+    regval &= ~I2S_DMA_TX_EN;
+    regval &= ~I2S_DMA_RX_EN;
+    /* clean fifo */
+    regval |= I2S_TX_FIFO_CLR;
+    regval |= I2S_RX_FIFO_CLR;
+    putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+
+    regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
+    /* disable deglitch */
+    regval &= ~I2S_CR_DEG_EN;
+    /* disable inverse signal */
+    regval &= ~I2S_CR_I2S_BCLK_INV;
+    regval &= ~I2S_CR_I2S_FS_INV;
+    regval &= ~I2S_CR_I2S_RXD_INV;
+    regval &= ~I2S_CR_I2S_TXD_INV;
+    putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
+
+    /* enable I2S, but disable tx and rx */
+    regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+    if (config->role == I2S_ROLE_MASTER) {
+        regval |= I2S_CR_I2S_M_EN;
+    } else {
+        regval |= I2S_CR_I2S_S_EN;
+    }
+    putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+}
+
+void bflb_i2s_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    /* disable I2S */
+    regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+    regval &= ~I2S_CR_I2S_S_EN;
+    regval &= ~I2S_CR_I2S_M_EN;
+    putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+}
+
+void bflb_i2s_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= I2S_DMA_TX_EN;
+    } else {
+        regval &= ~I2S_DMA_TX_EN;
+    }
+    putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_i2s_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= I2S_DMA_RX_EN;
+    } else {
+        regval &= ~I2S_DMA_RX_EN;
+    }
+    putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_i2s_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
+    if (mask) {
+        regval |= I2S_CR_I2S_TXF_MASK;
+    } else {
+        regval &= ~I2S_CR_I2S_TXF_MASK;
+    }
+    putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
+}
+
+void bflb_i2s_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
+    if (mask) {
+        regval |= I2S_CR_I2S_RXF_MASK;
+    } else {
+        regval &= ~I2S_CR_I2S_RXF_MASK;
+    }
+    putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
+}
+
+void bflb_i2s_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + I2S_INT_STS_OFFSET);
+    if (mask) {
+        regval |= I2S_CR_I2S_FER_MASK;
+    } else {
+        regval &= ~I2S_CR_I2S_FER_MASK;
+    }
+    putreg32(regval, reg_base + I2S_INT_STS_OFFSET);
+}
+
+uint32_t bflb_i2s_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t int_status;
+    uint32_t int_mask;
+
+    reg_base = dev->reg_base;
+
+    int_status = getreg32(reg_base + I2S_INT_STS_OFFSET) & 0x1f;
+
+    int_mask = (getreg32(reg_base + I2S_INT_STS_OFFSET) >> 8) & 0x1f;
+
+    return (int_status & ~int_mask);
+}
+
+int bflb_i2s_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case I2S_CMD_CLEAR_TX_FIFO:
+            /* clear tx fifo */
+            regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            regval |= I2S_TX_FIFO_CLR;
+            putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case I2S_CMD_CLEAR_RX_FIFO:
+            /* clear rx fifo */
+            regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            regval |= I2S_RX_FIFO_CLR;
+            putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case I2S_CMD_RX_DEGLITCH:
+            /* set rx deglitch, arg: deglitch cycle count (unit: cycle of I2S kernel clock) */
+            regval = getreg32(reg_base + I2S_IO_CONFIG_OFFSET);
+            if (arg) {
+                regval |= I2S_CR_DEG_EN;
+                regval &= ~I2S_CR_DEG_CNT_MASK;
+                regval |= (arg << I2S_CR_DEG_CNT_SHIFT) & I2S_CR_DEG_CNT_MASK;
+            } else {
+                regval &= ~I2S_CR_DEG_EN;
+            }
+            putreg32(regval, reg_base + I2S_IO_CONFIG_OFFSET);
+            break;
+
+        case I2S_CMD_DATA_ENABLE:
+            /* data enable, arg: use @ref I2S_CMD_DATA_ENABLE_TYPE */
+            regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+            /* enable tx data signal */
+            if (arg & I2S_CMD_DATA_ENABLE_TX) {
+                regval |= I2S_CR_I2S_TXD_EN;
+            } else {
+                regval &= ~I2S_CR_I2S_TXD_EN;
+            }
+            /* enable rx data signal */
+            if (arg & I2S_CMD_DATA_ENABLE_RX) {
+                regval |= I2S_CR_I2S_RXD_EN;
+            } else {
+                regval &= ~I2S_CR_I2S_RXD_EN;
+            }
+            putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+            break;
+
+        case I2S_CMD_CHANNEL_LR_MERGE:
+            /* Each FIFO entry contains both L/R channel data ,
+            can only be enabled if data size is 8 or 16 bits,
+            arg use true or false */
+            regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            if (arg) {
+                regval |= I2S_CR_FIFO_LR_MERGE;
+            } else {
+                regval &= ~I2S_CR_FIFO_LR_MERGE;
+            }
+            putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case I2S_CMD_CHANNEL_LR_EXCHG:
+            /* The position of L/R channel data within each entry is exchanged,
+            can only be enabled if data size is 8 or 16 bits and I2S_CMD_CHANNEL_LR_MERGE is enabled,
+            arg use true or false */
+            regval = getreg32(reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            if (arg) {
+                regval |= I2S_CR_FIFO_LR_EXCHG;
+            } else {
+                regval &= ~I2S_CR_FIFO_LR_EXCHG;
+            }
+            putreg32(regval, reg_base + I2S_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case I2S_CMD_MUTE:
+            /* Enable mute, arg use true or false */
+            regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+            if (arg) {
+                regval |= I2S_CR_MUTE_MODE;
+            } else {
+                regval &= ~I2S_CR_MUTE_MODE;
+            }
+            putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+            break;
+
+        case I2S_CMD_BIT_REVERSE:
+            /* Data endian (bit reverse), arg use true or false, true: MSB goes out first, false: LSB goes out first*/
+            regval = getreg32(reg_base + I2S_CONFIG_OFFSET);
+            if (arg) {
+                regval |= I2S_CR_MUTE_MODE;
+            } else {
+                regval &= ~I2S_CR_MUTE_MODE;
+            }
+            putreg32(regval, reg_base + I2S_CONFIG_OFFSET);
+            break;
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ir.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ir.c
new file mode 100755
index 0000000000..345adb8571
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_ir.c
@@ -0,0 +1,637 @@
+#include "bflb_ir.h"
+#include "bflb_clock.h"
+#include "hardware/ir_reg.h"
+
+#define DIVIDE_ROUND(a, b) ((2 * a + b) / (2 * b))
+
+#if !defined(BL616)
+void bflb_ir_tx_init(struct bflb_device_s *dev, const struct bflb_ir_tx_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t ir_clock;
+    struct bflb_ir_tx_config_s *tx_config = (struct bflb_ir_tx_config_s *)config;
+
+#if defined(BL602) || defined(BL702)
+    *(uint32_t *)0x40000224 |= 1 << 31;
+#else
+    *(uint32_t *)0x20000144 |= 1 << 31;
+#endif
+
+    if (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0)) {
+        ir_clock = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0);
+    } else {
+        ir_clock = 2000000;
+    }
+
+    if (tx_config->tx_mode == IR_TX_NEC) {
+        tx_config->data_bits = 32;
+        tx_config->tail_inverse = 0;
+        tx_config->tail_enable = 1;
+        tx_config->head_inverse = 0;
+        tx_config->head_enable = 1;
+        tx_config->logic1_inverse = 0;
+        tx_config->logic0_inverse = 0;
+        tx_config->data_enable = 1;
+        tx_config->swm_enable = 0;
+        tx_config->output_modulation = 1;
+        tx_config->output_inverse = 0;
+        tx_config->freerun_enable = 0;
+        tx_config->continue_enable = 0;
+        tx_config->fifo_width = IR_TX_FIFO_WIDTH_32BIT;
+        tx_config->fifo_threshold = 0;
+        tx_config->logic0_pulse_width_1 = 0;
+        tx_config->logic0_pulse_width_0 = 0;
+        tx_config->logic1_pulse_width_1 = 2;
+        tx_config->logic1_pulse_width_0 = 0;
+        tx_config->head_pulse_width_1 = 7;
+        tx_config->head_pulse_width_0 = 15;
+        tx_config->tail_pulse_width_1 = 0;
+        tx_config->tail_pulse_width_0 = 0;
+        tx_config->pulse_width_unit = (ir_clock * 10 / 17777 - 1) & 0xfff;
+    } else if (tx_config->tx_mode == IR_TX_RC5) {
+        tx_config->data_bits = 13;
+        tx_config->tail_inverse = 0;
+        tx_config->tail_enable = 0;
+        tx_config->head_inverse = 1;
+        tx_config->head_enable = 1;
+        tx_config->logic1_inverse = 1;
+        tx_config->logic0_inverse = 0;
+        tx_config->data_enable = 1;
+        tx_config->swm_enable = 0;
+        tx_config->output_modulation = 1;
+        tx_config->output_inverse = 0;
+        tx_config->freerun_enable = 0;
+        tx_config->continue_enable = 0;
+        tx_config->fifo_width = IR_TX_FIFO_WIDTH_32BIT;
+        tx_config->fifo_threshold = 0;
+        tx_config->logic0_pulse_width_1 = 0;
+        tx_config->logic0_pulse_width_0 = 0;
+        tx_config->logic1_pulse_width_1 = 0;
+        tx_config->logic1_pulse_width_0 = 0;
+        tx_config->head_pulse_width_1 = 0;
+        tx_config->head_pulse_width_0 = 0;
+        tx_config->tail_pulse_width_1 = 0;
+        tx_config->tail_pulse_width_0 = 0;
+        tx_config->pulse_width_unit = (ir_clock * 10 / 11248 - 1) & 0xfff;
+    } else if (tx_config->tx_mode == IR_TX_SWM) {
+        tx_config->swm_enable = 1;
+        tx_config->output_modulation = 1;
+        tx_config->output_inverse = 0;
+        tx_config->fifo_width = IR_TX_FIFO_WIDTH_32BIT;
+        tx_config->fifo_threshold = 0;
+    }
+
+    if (tx_config->tx_mode != IR_TX_CUSTOMIZE) {
+        tx_config->modu_width_1 = ((ir_clock / 11310 + 5) / 10 - 1) & 0xff;
+        tx_config->modu_width_0 = ((ir_clock / 5655 + 5) / 10 - 1) & 0xff;
+    } else {
+        if (tx_config->output_modulation != 0 && tx_config->freerun_enable != 0) {
+            tx_config->continue_enable = 0;
+            if (tx_config->tail_pulse_width_1 < 5) {
+                tx_config->tail_pulse_width_1 = 5;
+            }
+            if (tx_config->tail_pulse_width_0 < 5) {
+                tx_config->tail_pulse_width_0 = 5;
+            }
+        }
+    }
+
+    reg_base = dev->reg_base;
+    regval = (tx_config->pulse_width_unit & 0xfff) | tx_config->modu_width_1 << 16 | tx_config->modu_width_0 << 24;
+    putreg32(regval, reg_base + IRTX_PULSE_WIDTH_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+    regval = getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET);
+    regval &= ~IR_TX_FIFO_TH_MASK;
+    regval |= tx_config->fifo_threshold << IR_TX_FIFO_TH_SHIFT;
+    putreg32(regval, reg_base + IR_FIFO_CONFIG_1_OFFSET);
+#endif
+
+    regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+#if defined(BL602) || defined(BL702)
+    regval &= ~(IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV);
+#else
+    regval &= ~(IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV | IR_CR_IRTX_FRM_FRAME_SIZE_MASK);
+#endif
+    if (tx_config->swm_enable) {
+        regval |= IR_CR_IRTX_SWM_EN;
+    }
+    if (tx_config->output_modulation) {
+        regval |= IR_CR_IRTX_MOD_EN;
+    }
+    if (tx_config->output_inverse) {
+        regval |= IR_CR_IRTX_OUT_INV;
+    }
+#if !defined(BL602) && !defined(BL702)
+    regval |= (tx_config->fifo_width & 0x3) << IR_CR_IRTX_FRM_FRAME_SIZE_SHIFT;
+#endif
+    if (tx_config->tx_mode == IR_TX_SWM) {
+        putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+        return;
+    }
+#if defined(BL602) || defined(BL702)
+    regval &= IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV;
+#else
+    regval &= IR_CR_IRTX_SWM_EN | IR_CR_IRTX_MOD_EN | IR_CR_IRTX_OUT_INV | IR_CR_IRTX_FRM_FRAME_SIZE_MASK;
+#endif
+    regval |= (tx_config->data_bits - 1) << IR_CR_IRTX_DATA_NUM_SHIFT;
+    if (tx_config->tail_inverse) {
+        regval |= IR_CR_IRTX_TAIL_HL_INV;
+    }
+    if (tx_config->tail_enable) {
+        regval |= IR_CR_IRTX_TAIL_EN;
+    }
+    if (tx_config->head_inverse) {
+        regval |= IR_CR_IRTX_HEAD_HL_INV;
+    }
+    if (tx_config->head_enable) {
+        regval |= IR_CR_IRTX_HEAD_EN;
+    }
+    if (tx_config->logic1_inverse) {
+        regval |= IR_CR_IRTX_LOGIC1_HL_INV;
+    }
+    if (tx_config->logic0_inverse) {
+        regval |= IR_CR_IRTX_LOGIC0_HL_INV;
+    }
+    if (tx_config->data_enable) {
+        regval |= IR_CR_IRTX_DATA_EN;
+    }
+#if !defined(BL602) && !defined(BL702)
+    if (tx_config->freerun_enable) {
+        regval |= IR_CR_IRTX_FRM_EN;
+    }
+    if (tx_config->continue_enable) {
+        regval |= IR_CR_IRTX_FRM_CONT_EN;
+    }
+#endif
+    putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+#if defined(BL602) || defined(BL702)
+    regval = (tx_config->tail_pulse_width_1 & 0xf) << 28 | \
+             (tx_config->tail_pulse_width_0 & 0xf) << 24 | \
+             (tx_config->head_pulse_width_1 & 0xf) << 20 | \
+             (tx_config->head_pulse_width_0 & 0xf) << 16 | \
+             (tx_config->logic1_pulse_width_1 & 0xf) << 12 | \
+             (tx_config->logic1_pulse_width_0 & 0xf) << 8 | \
+             (tx_config->logic0_pulse_width_1 & 0xf) << 4 | \
+             (tx_config->logic0_pulse_width_0 & 0xf);
+    putreg32(regval, reg_base + IRTX_PW_OFFSET);
+#else
+    regval = tx_config->logic0_pulse_width_0 | tx_config->logic0_pulse_width_1 << 8 | \
+             tx_config->logic1_pulse_width_0 << 16 | tx_config->logic1_pulse_width_1 << 24;
+    putreg32(regval, reg_base + IRTX_PW_0_OFFSET);
+
+    regval = tx_config->head_pulse_width_0 | tx_config->head_pulse_width_1 << 8 | \
+             tx_config->tail_pulse_width_0 << 16 | tx_config->tail_pulse_width_1 << 24;
+    putreg32(regval, reg_base + IRTX_PW_1_OFFSET);
+#endif
+}
+
+void bflb_ir_send(struct bflb_device_s *dev, uint32_t *data, uint32_t length)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+#if !defined(BL602) && !defined(BL702)
+    uint32_t i = 0;
+#endif
+
+    bflb_ir_txint_clear(dev);
+
+    reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+    putreg32(data[0], reg_base + IRTX_DATA_WORD0_OFFSET);
+    if (length > 1) {
+        putreg32(data[1], reg_base + IRTX_DATA_WORD1_OFFSET);
+    }
+#endif
+
+    regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+    regval |= IR_CR_IRTX_EN;
+    putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+    if ((regval & IR_CR_IRTX_FRM_EN) == 0) {
+        length = length < 4 ? length : 4;
+    }
+    while(i < length){
+        if (bflb_ir_get_txfifo_cnt(dev) > 0) {
+            putreg32(data[i], reg_base + IR_FIFO_WDATA_OFFSET);
+            i++;
+        }
+    }
+
+    if ((getreg32(reg_base + IRTX_CONFIG_OFFSET) & IR_CR_IRTX_FRM_EN) == 0) {
+        while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
+            /* Waiting for sending */
+        }
+    } else {
+        while(bflb_ir_get_txfifo_cnt(dev) < 4){
+            /* Waiting for sending */
+        }
+    }
+#else
+    while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
+        /* Waiting for sending */
+    }
+#endif
+
+    regval &= ~IR_CR_IRTX_EN;
+    putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+    bflb_ir_txint_clear(dev);
+}
+
+void bflb_ir_swm_send(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint16_t min_data = data[0];
+#if defined(BL602) || defined(BL702)
+    uint32_t count = (length + 7) / 8;
+#else
+    uint32_t count = (length + 3) / 4;
+#endif
+    uint32_t pwval = 0;
+    uint32_t i, j;
+
+    if (length > 128) {
+        length = 128;
+    }
+
+    bflb_ir_txint_clear(dev);
+
+    /* Search for min value */
+    for (i = 1; i < length; i++) {
+        if (min_data > data[i] && data[i] != 0) {
+            min_data = data[i];
+        }
+    }
+
+    /* Set min value as pulse width unit */
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRTX_PULSE_WIDTH_OFFSET);
+    regval &= ~IR_CR_IRTX_PW_UNIT_MASK;
+    regval |= min_data << IR_CR_IRTX_PW_UNIT_SHIFT;
+    putreg32(regval, reg_base + IRTX_PULSE_WIDTH_OFFSET);
+
+#if defined(BL602) || defined(BL702)
+    /* Set tx SWM pulse width data as multiples of pulse width unit */
+    for (i = 0; i < count; i++) {
+        pwval = 0;
+
+        if (i < count - 1) {
+            for (j = 0; j < 8; j++) {
+                regval = ((2 * data[j + i * 8] + min_data) / (2 * min_data) - 1) & 0xf;
+                pwval |= regval << (4 * j);
+            }
+
+            putreg32(pwval, reg_base + IRTX_SWM_PW_0_OFFSET + i * 4);
+        } else {
+            for (j = 0; j < length % 8; j++) {
+                regval = ((2 * data[j + i * 8] + min_data) / (2 * min_data) - 1) & 0xf;
+                pwval |= regval << (4 * j);
+            }
+
+            putreg32(pwval, reg_base + IRTX_SWM_PW_0_OFFSET + i * 4);
+        }
+    }
+#endif
+
+    regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+    regval &= ~IR_CR_IRTX_DATA_NUM_MASK;
+    regval |= (length - 1) << IR_CR_IRTX_DATA_NUM_SHIFT;
+    regval |= IR_CR_IRTX_EN;
+    putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+    /* Calculate tx SWM pulse width data as multiples of pulse width unit */
+    for (i = 0; i < count; i++) {
+        pwval = 0;
+
+        if (i < count - 1) {
+            /* Put every four pulse width together as a 32-bit value to tx fifo */
+            for (j = 0; j < 4; j++) {
+                /* Every pulse width divided by pulse width unit */
+                regval = (DIVIDE_ROUND(data[j + i * 4], min_data) - 1) & 0xff;
+                /* Tx fifo 32-bit value: pwval[7:0]:first pulse width, pwval[15:8]:second pulse width... */
+                pwval |= regval << (8 * j);
+            }
+        } else {
+            /* Deal with pulse width data remained which is less than 4 */
+            for (j = 0; j < length % 4; j++) {
+                regval = (DIVIDE_ROUND(data[j + i * 4], min_data) - 1) & 0xff;
+                pwval |= regval << (8 * j);
+            }
+        }
+
+        /* Write to tx fifo */
+        while(bflb_ir_get_txfifo_cnt(dev) == 0){}
+        putreg32(pwval, reg_base + IR_FIFO_WDATA_OFFSET);
+    }
+#endif
+
+    while((bflb_ir_get_txint_status(dev) & IR_TX_INTSTS_END) == 0){
+        /* Waiting for sending */
+    }
+
+    regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+    regval &= ~IR_CR_IRTX_EN;
+    putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+
+    bflb_ir_txint_clear(dev);
+}
+
+void bflb_ir_tx_enable(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRTX_CONFIG_OFFSET);
+    if (enable) {
+        regval |= IR_CR_IRTX_EN;
+    } else {
+        regval &= ~IR_CR_IRTX_EN;
+    }
+    putreg32(regval, reg_base + IRTX_CONFIG_OFFSET);
+}
+
+void bflb_ir_txint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRTX_INT_STS_OFFSET);
+    if (mask) {
+        regval |= (int_type & 0x7) << 8;
+    } else {
+        regval &= ~((int_type & 0x7) << 8);
+    }
+    putreg32(regval, reg_base + IRTX_INT_STS_OFFSET);
+}
+
+void bflb_ir_txint_clear(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRTX_INT_STS_OFFSET);
+    regval |= IR_CR_IRTX_END_CLR;
+    putreg32(regval, reg_base + IRTX_INT_STS_OFFSET);
+}
+
+uint32_t bflb_ir_get_txint_status(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    return (getreg32(reg_base + IRTX_INT_STS_OFFSET) & 0x7);
+}
+
+#if !defined(BL602) && !defined(BL702)
+void bflb_ir_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IR_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= IRTX_DMA_EN;
+    } else {
+        regval &= ~IRTX_DMA_EN;
+    }
+    putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
+}
+
+uint8_t bflb_ir_get_txfifo_cnt(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    return ((getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET) & IR_TX_FIFO_CNT_MASK) >> IR_TX_FIFO_CNT_SHIFT);
+}
+
+void bflb_ir_txfifo_clear(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IR_FIFO_CONFIG_0_OFFSET);
+    regval |= IR_TX_FIFO_CLR;
+    putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
+}
+#endif
+#endif
+
+#if !defined(BL702L)
+void bflb_ir_rx_init(struct bflb_device_s *dev, const struct bflb_ir_rx_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t ir_clock;
+    uint16_t data_threshold, end_threshold;
+
+    if (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0)) {
+        ir_clock = bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_IR, 0);
+    } else {
+        ir_clock = 2000000;
+    }
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+    regval &= ~IR_CR_IRRX_MODE_MASK;
+    regval |= (config->rx_mode & 0x3) << IR_CR_IRRX_MODE_SHIFT;
+    if (config->input_inverse) {
+        regval |= IR_CR_IRRX_IN_INV;
+    } else {
+        regval &= ~IR_CR_IRRX_IN_INV;
+    }
+    if (!config->deglitch_enable) {
+        regval &= ~IR_CR_IRRX_DEG_EN;
+    } else {
+        regval |= IR_CR_IRRX_DEG_EN;
+        regval &= ~IR_CR_IRRX_DEG_CNT_MASK;
+        regval |= config->deglitch_cnt << IR_CR_IRRX_DEG_CNT_SHIFT;
+    }
+    putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+    if (config->rx_mode == IR_RX_NEC) {
+        data_threshold = (ir_clock / 588 - 1) & 0xffff;
+        end_threshold = (ir_clock / 222 - 1) & 0xffff;
+    } else if (config->rx_mode == IR_RX_RC5) {
+        data_threshold = (ir_clock / 750 - 1) & 0xffff;
+        end_threshold = (ir_clock / 400 - 1) & 0xffff;
+    } else {
+        data_threshold = config->data_threshold;
+        end_threshold = config->end_threshold;
+    }
+    regval = getreg32(reg_base + IRRX_PW_CONFIG_OFFSET);
+    regval = end_threshold << IR_CR_IRRX_END_TH_SHIFT | data_threshold;
+    putreg32(regval, reg_base + IRRX_PW_CONFIG_OFFSET);
+
+#if !defined(BL602) && !defined(BL702)
+    regval = getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET);
+    regval &= ~IR_RX_FIFO_TH_MASK;
+    regval |= config->fifo_threshold << IR_RX_FIFO_TH_SHIFT;
+    putreg32(regval, reg_base + IR_FIFO_CONFIG_1_OFFSET);
+#endif
+}
+
+uint8_t bflb_ir_receive(struct bflb_device_s *dev, uint64_t *data)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    bflb_ir_rxint_clear(dev);
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+    regval |= IR_CR_IRRX_EN;
+    putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+    while((bflb_ir_get_rxint_status(dev) & IR_RX_INTSTS_END) == 0){
+        /* Waiting for receiving */
+    }
+
+    regval &= ~IR_CR_IRRX_EN;
+    putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+    bflb_ir_rxint_clear(dev);
+
+    regval = getreg32(reg_base + IRRX_DATA_COUNT_OFFSET) & IR_STS_IRRX_DATA_CNT_MASK;
+    if (regval <= 32) {
+        *data = getreg32(reg_base + IRRX_DATA_WORD0_OFFSET);
+    } else {
+        *data = getreg32(reg_base + IRRX_DATA_WORD0_OFFSET) | (uint64_t)getreg32(reg_base + IRRX_DATA_WORD1_OFFSET) << 32;
+    }
+
+    return regval;
+}
+
+uint8_t bflb_ir_swm_receive(struct bflb_device_s *dev, uint16_t *data, uint8_t length)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t i = 0;
+
+    bflb_ir_rxint_clear(dev);
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+    regval |= IR_CR_IRRX_EN;
+    putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+    while((bflb_ir_get_rxint_status(dev) & IR_RX_INTSTS_END) == 0){
+        if (bflb_ir_get_rxfifo_cnt(dev) != 0 && i < length) {
+#if defined(BL602) || defined(BL702)
+            data[i] = getreg32(reg_base + IRRX_SWM_FIFO_RDATA_OFFSET);
+#else
+            data[i] = getreg32(reg_base + IR_FIFO_RDATA_OFFSET);
+#endif
+            i++;
+        }
+    }
+
+    regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+    regval &= ~IR_CR_IRRX_EN;
+    putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+
+    bflb_ir_rxint_clear(dev);
+
+    return(getreg32(reg_base + IRRX_DATA_COUNT_OFFSET) & IR_STS_IRRX_DATA_CNT_MASK);
+}
+
+void bflb_ir_rx_enable(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRRX_CONFIG_OFFSET);
+    if (enable) {
+        regval |= IR_CR_IRRX_EN;
+    } else {
+        regval &= ~IR_CR_IRRX_EN;
+    }
+    putreg32(regval, reg_base + IRRX_CONFIG_OFFSET);
+}
+
+void bflb_ir_rxint_mask(struct bflb_device_s *dev, uint8_t int_type, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRRX_INT_STS_OFFSET);
+    if (mask) {
+        regval |= (int_type & 0x7) << 8;
+    } else {
+        regval &= ~((int_type & 0x7) << 8);
+    }
+    putreg32(regval, reg_base + IRRX_INT_STS_OFFSET);
+}
+
+void bflb_ir_rxint_clear(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + IRRX_INT_STS_OFFSET);
+    regval |= IR_CR_IRRX_END_CLR;
+    putreg32(regval, reg_base + IRRX_INT_STS_OFFSET);
+}
+
+uint32_t bflb_ir_get_rxint_status(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    return (getreg32(reg_base + IRRX_INT_STS_OFFSET) & 0x7);
+}
+
+uint8_t bflb_ir_get_rxfifo_cnt(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+    return ((getreg32(reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET) & IR_RX_FIFO_CNT_MASK) >> IR_RX_FIFO_CNT_SHIFT);
+#else
+    return ((getreg32(reg_base + IR_FIFO_CONFIG_1_OFFSET) & IR_RX_FIFO_CNT_MASK) >> IR_RX_FIFO_CNT_SHIFT);
+#endif
+}
+
+void bflb_ir_rxfifo_clear(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+#if defined(BL602) || defined(BL702)
+    regval = getreg32(reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET);
+    regval |= IR_RX_FIFO_CLR;
+    putreg32(regval, reg_base + IRRX_SWM_FIFO_CONFIG_0_OFFSET);
+#else
+    regval = getreg32(reg_base + IR_FIFO_CONFIG_0_OFFSET);
+    regval |= IR_RX_FIFO_CLR;
+    putreg32(regval, reg_base + IR_FIFO_CONFIG_0_OFFSET);
+#endif
+}
+#endif
+
+int bflb_ir_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    switch (cmd) {
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_irq.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_irq.c
new file mode 100755
index 0000000000..7e423b362c
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_irq.c
@@ -0,0 +1,130 @@
+#include "bflb_irq.h"
+#include "bflb_core.h"
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#include 
+#else
+#include 
+#endif
+
+extern struct bflb_irq_info_s g_irqvector[];
+
+static void irq_unexpected_isr(int irq, void *arg)
+{
+    printf("irq :%d unregistered\r\n", irq);
+}
+
+void bflb_irq_initialize(void)
+{
+    int i;
+
+    /* Point all interrupt vectors to the unexpected interrupt */
+    for (i = 0; i < CONFIG_IRQ_NUM; i++) {
+        g_irqvector[i].handler = irq_unexpected_isr;
+        g_irqvector[i].arg = NULL;
+    }
+}
+
+ATTR_TCM_SECTION uintptr_t bflb_irq_save(void)
+{
+    uintptr_t oldstat;
+
+    /* Read mstatus & clear machine interrupt enable (MIE) in mstatus */
+
+    asm volatile("csrrc %0, mstatus, %1"
+                 : "=r"(oldstat)
+                 : "r"(MSTATUS_MIE));
+    return oldstat;
+}
+
+ATTR_TCM_SECTION void bflb_irq_restore(uintptr_t flags)
+{
+    /* Write flags to mstatus */
+
+    asm volatile("csrw mstatus, %0"
+                 : /* no output */
+                 : "r"(flags));
+}
+
+int bflb_irq_attach(int irq, irq_callback isr, void *arg)
+{
+    if (irq > CONFIG_IRQ_NUM) {
+        return -EINVAL;
+    }
+    g_irqvector[irq].handler = isr;
+    g_irqvector[irq].arg = arg;
+    return 0;
+}
+
+int bflb_irq_detach(int irq)
+{
+    if (irq > CONFIG_IRQ_NUM) {
+        return -EINVAL;
+    }
+    g_irqvector[irq].handler = irq_unexpected_isr;
+    g_irqvector[irq].arg = NULL;
+    return 0;
+}
+
+void bflb_irq_enable(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    putreg8(1, CLIC_HART0_BASE + CLIC_INTIE_OFFSET + irq);
+#else
+#if (defined(BL808) || defined(BL606P)) && defined(CPU_D0)
+    if (csi_vic_get_prio(irq) == 0) {
+        csi_vic_set_prio(irq, 1);
+    }
+#endif
+    csi_vic_enable_irq(irq);
+#endif
+}
+
+void bflb_irq_disable(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    putreg8(0, CLIC_HART0_BASE + CLIC_INTIE_OFFSET + irq);
+#else
+    csi_vic_disable_irq(irq);
+#endif
+}
+
+void bflb_irq_set_pending(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    putreg8(1, CLIC_HART0_BASE + CLIC_INTIP_OFFSET + irq);
+#else
+    csi_vic_set_pending_irq(irq);
+#endif
+}
+
+void bflb_irq_clear_pending(int irq)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    putreg8(0, CLIC_HART0_BASE + CLIC_INTIP_OFFSET + irq);
+#else
+    csi_vic_clear_pending_irq(irq);
+#endif
+}
+
+void bflb_irq_set_nlbits(uint8_t nlbits)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    uint8_t clicCfg = getreg8(CLIC_HART0_BASE + CLIC_CFG_OFFSET);
+    putreg8((clicCfg & 0xe1) | ((nlbits & 0xf) << 1), CLIC_HART0_BASE + CLIC_CFG_OFFSET);
+#else
+#if !defined(CPU_D0)
+    CLIC->CLICCFG = ((nlbits & 0xf) << 1) | 1;
+#endif
+#endif
+}
+
+void bflb_irq_set_priority(int irq, uint8_t preemptprio, uint8_t subprio)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    uint8_t nlbits = getreg8(CLIC_HART0_BASE + CLIC_CFG_OFFSET) >> 1 & 0xf;
+    uint8_t clicIntCfg = getreg8(CLIC_HART0_BASE + CLIC_INTCFG_OFFSET + irq);
+    putreg8((clicIntCfg & 0xf) | (preemptprio << (8 - nlbits)) | ((subprio & (0xf >> nlbits)) << 4), CLIC_HART0_BASE + CLIC_INTCFG_OFFSET + irq);
+#else
+    csi_vic_set_prio(irq, preemptprio);
+#endif
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c
new file mode 100755
index 0000000000..f926516540
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_iso11898.c
@@ -0,0 +1,366 @@
+#include "bflb_iso11898.h"
+#include "hardware/iso11898_reg.h"
+
+void bflb_iso11898_init(struct bflb_device_s *dev, struct bflb_iso11898_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    /* first enter reset mode */
+    regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+    regval |= ISO11898_RESET_REQUEST;
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+    /* force using PeliISO11898 not BasicISO11898 */
+    regval = getreg32(reg_base + ISO11898_CLOCK_DIVIDER_OFFSET);
+    regval |= ISO11898_CAN_MODE;
+    putreg32(regval, reg_base + ISO11898_CLOCK_DIVIDER_OFFSET);
+
+    /* config prescale and synchronisation_jump_width */
+    regval = getreg32(reg_base + ISO11898_BUS_TIMING_0_OFFSET);
+    regval &= ~ISO11898_BAUD_RATE_PRESCALER_MASK;
+    regval |= (config->prescaler << ISO11898_BAUD_RATE_PRESCALER_SHIFT);
+    regval &= ~ISO11898_SYNC_JUMP_WIDTH_MASK;
+    regval |= (config->sjw << ISO11898_SYNC_JUMP_WIDTH_SHIFT);
+    putreg32(regval, reg_base + ISO11898_BUS_TIMING_0_OFFSET);
+
+    /* config samping and bit_segment_1/2 */
+    regval = getreg32(reg_base + ISO11898_BUS_TIMING_1_OFFSET);
+    if (config->sample == ISO11898_SAMPLE_SINGLE) {
+        regval &= ~ISO11898_SAMPLING;
+    } else {
+        regval |= ISO11898_SAMPLING;
+    }
+    regval &= ~ISO11898_TIME_SEGMENT_1_MASK;
+    regval |= (config->bs1 << ISO11898_TIME_SEGMENT_1_SHIFT);
+    regval &= ~ISO11898_TIME_SEGMENT_2_MASK;
+    regval |= (config->bs2 << ISO11898_TIME_SEGMENT_2_SHIFT);
+    putreg32(regval, reg_base + ISO11898_BUS_TIMING_1_OFFSET);
+
+    /* config mode */
+    regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+    if (config->mode == ISO11898_MODE_NORMAL) {
+        regval &= ~ISO11898_LISTEN_ONLY;
+        regval &= ~ISO11898_SELF_TEST;
+    } else if (config->mode == ISO11898_MODE_LOOPBACK) {
+        regval &= ~ISO11898_LISTEN_ONLY;
+        regval |= ISO11898_SELF_TEST;
+    } else if (config->mode == ISO11898_MODE_SILENT) {
+        regval |= ISO11898_LISTEN_ONLY;
+        regval &= ~ISO11898_SELF_TEST;
+    } else if (config->mode == ISO11898_MODE_SILENT_LOOPBACK) {
+        regval |= ISO11898_LISTEN_ONLY;
+        regval |= ISO11898_SELF_TEST;
+    } else {
+    }
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+    /* last leave reset mode */
+    regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+    regval &= ~ISO11898_RESET_REQUEST;
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+}
+
+void bflb_iso11898_deinit(struct bflb_device_s *dev)
+{
+}
+
+void bflb_iso11898_abort_send(struct bflb_device_s *dev)
+{
+    putreg32(ISO11898_ABORT_TRANSMISSION, dev->reg_base + ISO11898_COMMAND_OFFSET);
+}
+
+int8_t bflb_iso11898_send(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t data_base_addr;
+    uint8_t mode;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_TX_AVAILABLE)) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > timeout) {
+            return -ETIMEDOUT;
+        }
+    }
+
+    /* config frame information register */
+    regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
+    regval &= ~ISO11898_FRAME_INFORMATION_DLC_MASK;
+    regval |= (msg->dlc << ISO11898_FRAME_INFORMATION_DLC_SHIFT);
+    if (msg->id_type == ISO11898_ID_STANDARD) {
+        regval &= ~ISO11898_FRAME_INFORMATION_FF;
+    } else {
+        regval |= ISO11898_FRAME_INFORMATION_FF;
+    }
+    if (msg->rtr == ISO11898_RTR_DATA) {
+        regval &= ~ISO11898_FRAME_INFORMATION_RTR;
+    } else {
+        regval |= ISO11898_FRAME_INFORMATION_RTR;
+    }
+    putreg32(regval, reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
+
+    /* config id */
+    if (msg->id_type == ISO11898_ID_STANDARD) {
+        putreg32(msg->std_id >> (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT), reg_base + ISO11898_SFF_ID1_OFFSET);
+        putreg32(msg->std_id << ISO11898_SFF_ID2_BIT20_18_SHIFT, reg_base + ISO11898_SFF_ID2_OFFSET);
+        data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET;
+    } else {
+        putreg32(msg->ext_id >> 21, reg_base + ISO11898_EFF_ID1_OFFSET);
+        putreg32(msg->ext_id >> 13, reg_base + ISO11898_EFF_ID2_OFFSET);
+        putreg32(msg->ext_id >> 5, reg_base + ISO11898_EFF_ID3_OFFSET);
+        putreg32(msg->ext_id << ISO11898_EFF_ID4_BIT4_0_SHIFT, reg_base + ISO11898_EFF_ID4_OFFSET);
+        data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET;
+    }
+
+    /* move data from user buff to registers */
+    for (uint32_t i = 0; i < msg->dlc; i++) {
+        *((uint32_t *)data_base_addr + i) = msg->data[i];
+    }
+
+    /* trig a request for transmit */
+    mode = bflb_iso11898_get_mode(dev);
+    if (mode == ISO11898_MODE_SILENT_LOOPBACK || mode == ISO11898_MODE_LOOPBACK) {
+        putreg32(ISO11898_SELF_REQUEST, reg_base + ISO11898_COMMAND_OFFSET);
+    } else if (mode == ISO11898_MODE_NORMAL) {
+        putreg32(ISO11898_TRANSMIT_REQUEST, reg_base + ISO11898_COMMAND_OFFSET);
+    } else {
+        return -2;
+    }
+    return 0;
+}
+
+int8_t bflb_iso11898_recv(struct bflb_device_s *dev, struct bflb_iso11898_msg_s *msg, uint32_t timeout)
+{
+    uint32_t reg_base;
+    uint32_t regval, regval2, regval3, regval4;
+    uint32_t data_base_addr;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (!(bflb_iso11898_get_status(dev) & ISO11898_STATUS_RX_NOT_EMPTY)) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > timeout) {
+            return -ETIMEDOUT;
+        }
+    }
+
+    /* read information register */
+    regval = getreg32(reg_base + ISO11898_FRAME_INFORMATION_OFFSET);
+    msg->dlc = (uint8_t)((regval & ISO11898_FRAME_INFORMATION_DLC_MASK) >> ISO11898_FRAME_INFORMATION_DLC_SHIFT);
+    if (regval & ISO11898_FRAME_INFORMATION_FF) {
+        msg->id_type = ISO11898_ID_EXTENDED;
+    } else {
+        msg->id_type = ISO11898_ID_STANDARD;
+    }
+    if (regval & ISO11898_FRAME_INFORMATION_RTR) {
+        msg->rtr = ISO11898_RTR_REMOTE;
+    } else {
+        msg->rtr = ISO11898_RTR_DATA;
+    }
+
+    /* receive with 11 or 29 bits ID */
+    if (msg->id_type == ISO11898_ID_STANDARD) {
+        regval = getreg32(reg_base + ISO11898_SFF_ID1_OFFSET);
+        regval &= ISO11898_SFF_ID1_BIT28_21_MASK;
+        regval <<= (8 - ISO11898_SFF_ID2_BIT20_18_SHIFT);
+        regval2 = getreg32(reg_base + ISO11898_SFF_ID2_OFFSET);
+        regval2 &= ISO11898_SFF_ID2_BIT20_18_MASK;
+        regval2 >>= ISO11898_SFF_ID2_BIT20_18_SHIFT;
+        msg->std_id = regval | regval2;
+        data_base_addr = reg_base + ISO11898_SFF_DATA1_OFFSET;
+    } else {
+        regval = getreg32(reg_base + ISO11898_EFF_ID1_OFFSET);
+        regval &= ISO11898_EFF_ID1_BIT28_21_MASK;
+        regval <<= 21;
+        regval2 = getreg32(reg_base + ISO11898_EFF_ID2_OFFSET);
+        regval2 &= ISO11898_EFF_ID2_BIT20_13_MASK;
+        regval2 <<= 13;
+        regval3 = getreg32(reg_base + ISO11898_EFF_ID3_OFFSET);
+        regval3 &= ISO11898_EFF_ID3_BIT12_5_MASK;
+        regval3 <<= 5;
+        regval4 = getreg32(reg_base + ISO11898_EFF_ID4_OFFSET);
+        regval4 &= ISO11898_EFF_ID4_BIT4_0_MASK;
+        regval4 >>= ISO11898_EFF_ID4_BIT4_0_SHIFT;
+        msg->ext_id = regval | regval2 | regval3 | regval4;
+        data_base_addr = reg_base + ISO11898_EFF_DATA1_OFFSET;
+    }
+
+    /* move data from registers to user buff */
+    for (uint32_t i = 0; i < msg->dlc; i++) {
+        msg->data[i] = (uint8_t)(*((uint32_t *)data_base_addr + i));
+    }
+    putreg32(ISO11898_RELEASE_RECEIVE_BUFFER, reg_base + ISO11898_COMMAND_OFFSET);
+    return 0;
+}
+
+uint8_t bflb_iso11898_get_status(struct bflb_device_s *dev)
+{
+    return getreg32(dev->reg_base + ISO11898_STATUS_OFFSET) & 0xff;
+}
+
+void bflb_iso11898_set_mode(struct bflb_device_s *dev, uint8_t mode)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    /* first enter reset mode */
+    regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+    regval |= ISO11898_RESET_REQUEST;
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+    /* config mode */
+    regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+    if (mode == ISO11898_MODE_NORMAL) {
+        regval &= ~ISO11898_LISTEN_ONLY;
+        regval &= ~ISO11898_SELF_TEST;
+    } else if (mode == ISO11898_MODE_LOOPBACK) {
+        regval &= ~ISO11898_LISTEN_ONLY;
+        regval |= ISO11898_SELF_TEST;
+    } else if (mode == ISO11898_MODE_SILENT) {
+        regval |= ISO11898_LISTEN_ONLY;
+        regval &= ~ISO11898_SELF_TEST;
+    } else if (mode == ISO11898_MODE_SILENT_LOOPBACK) {
+        regval |= ISO11898_LISTEN_ONLY;
+        regval |= ISO11898_SELF_TEST;
+    } else {
+    }
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+    /* last leave reset mode */
+    regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+    regval &= ~ISO11898_RESET_REQUEST;
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+}
+
+uint8_t bflb_iso11898_get_mode(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint8_t silent, loopback;
+
+    regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET);
+    if (regval & ISO11898_SELF_TEST) {
+        loopback = 1;
+    } else {
+        loopback = 0;
+    }
+    if (regval & ISO11898_LISTEN_ONLY) {
+        silent = 1;
+    } else {
+        silent = 0;
+    }
+    if (loopback && silent) {
+        return ISO11898_MODE_SILENT_LOOPBACK;
+    } else if (!loopback && silent) {
+        return ISO11898_MODE_SILENT;
+    } else if (loopback && !silent) {
+        return ISO11898_MODE_LOOPBACK;
+    } else {
+        return ISO11898_MODE_NORMAL;
+    }
+}
+
+void bflb_iso11898_set_filter(struct bflb_device_s *dev, struct bflb_iso11898_filter_s *filter)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint8_t mode;
+
+    reg_base = dev->reg_base;
+    /* first save mode */
+    mode = bflb_iso11898_get_mode(dev);
+
+    /* enter reset mode */
+    regval = getreg32(reg_base + ISO11898_MODE_OFFSET);
+    regval |= ISO11898_RESET_REQUEST;
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+    /* config filter type */
+    regval = getreg32(dev->reg_base + ISO11898_MODE_OFFSET);
+    if (filter->filter_type == ISO11898_FILTER_TYPE_SINGLE) {
+        regval |= ISO11898_FILTER_TYPE;
+    } else {
+        regval &= ~ISO11898_FILTER_TYPE;
+    }
+    putreg32(regval, reg_base + ISO11898_MODE_OFFSET);
+
+    /* config filter code and mask */
+    putreg32(filter->code0, reg_base + ISO11898_ACCEPTANCE_CODE_0_OFFSET);
+    putreg32(filter->code1, reg_base + ISO11898_ACCEPTANCE_CODE_1_OFFSET);
+    putreg32(filter->code2, reg_base + ISO11898_ACCEPTANCE_CODE_2_OFFSET);
+    putreg32(filter->code3, reg_base + ISO11898_ACCEPTANCE_CODE_3_OFFSET);
+    putreg32(filter->mask0, reg_base + ISO11898_ACCEPTANCE_MASK_0_OFFSET);
+    putreg32(filter->mask1, reg_base + ISO11898_ACCEPTANCE_MASK_1_OFFSET);
+    putreg32(filter->mask2, reg_base + ISO11898_ACCEPTANCE_MASK_2_OFFSET);
+    putreg32(filter->mask3, reg_base + ISO11898_ACCEPTANCE_MASK_3_OFFSET);
+
+    /* restore saved mode */
+    bflb_iso11898_set_mode(dev, mode);
+}
+
+void bflb_iso11898_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+    if (mask) {
+        regval &= ~ISO11898_TRANSMIT_INT_EN;
+    } else {
+        regval |= ISO11898_TRANSMIT_INT_EN;
+    }
+
+    putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+}
+
+void bflb_iso11898_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+    if (mask) {
+        regval &= ~ISO11898_RECEIVE_INT_EN;
+    } else {
+        regval |= ISO11898_RECEIVE_INT_EN;
+    }
+
+    putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+}
+
+void bflb_iso11898_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+    if (mask) {
+        regval &= ~ISO11898_ERROR_INT_EN;
+        regval &= ~ISO11898_DATA_OVERRUN_INT_EN;
+        regval &= ~ISO11898_ERROR_PASSIVE_INT_EN;
+        regval &= ~ISO11898_ARB_LOST_INT_EN;
+        regval &= ~ISO11898_BUS_ERROR_INT_EN;
+    } else {
+        regval |= ISO11898_ERROR_INT_EN;
+        regval |= ISO11898_DATA_OVERRUN_INT_EN;
+        regval |= ISO11898_ERROR_PASSIVE_INT_EN;
+        regval |= ISO11898_ARB_LOST_INT_EN;
+        regval |= ISO11898_BUS_ERROR_INT_EN;
+    }
+
+    putreg32(regval, reg_base + ISO11898_INTERRUPT_ENABLE_OFFSET);
+}
+
+uint32_t bflb_iso11898_get_int_status(struct bflb_device_s *dev)
+{
+    return getreg32(dev->reg_base + ISO11898_INTERRUPT_OFFSET);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_kys.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_kys.c
new file mode 100755
index 0000000000..95fa963764
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_kys.c
@@ -0,0 +1,217 @@
+/**
+  ******************************************************************************
+  * @file    bflb_kys.c
+  * @version V1.0
+  * @date    2022-11-17
+  * @brief   This file is the low hardware abstraction layer file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2022 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "bflb_core.h"
+#include "bflb_kys.h"
+#include "bflb_clock.h"
+#include "bflb_l1c.h"
+#include "hardware/kys_reg.h"
+
+/**
+ * @brief keyscan init
+ *
+ * @param dev
+ * @param config
+ */
+void bflb_kys_init(struct bflb_device_s *dev, const struct bflb_kys_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t reg_val;
+
+    reg_base = dev->reg_base;
+    /* disable kys */
+    reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+    reg_val &= ~(KYS_KS_EN_MASK);
+    putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+
+    /* mask all interrupt before init */
+    reg_val = getreg32(reg_base + KYS_KS_INT_EN_OFFSET);
+#if defined(BL702)
+    reg_val &= ~(KYS_KS_INT_EN_MASK);
+#else
+    reg_val &= ~(KYS_KS_DONE_INT_EN_MASK |
+                 KYS_KEYFIFO_FULL_INT_EN_MASK |
+                 KYS_KEYFIFO_HALF_INT_EN_MASK |
+                 KYS_KEYFIFO_QUARTER_INT_EN_MASK |
+                 KYS_KEYFIFO_NONEMPTY_INT_EN_MASK |
+                 KYS_GHOST_INT_EN_MASK);
+#endif
+
+    /* kys init */
+    reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+
+    reg_val &= ~(KYS_COL_NUM_MASK |
+                 KYS_ROW_NUM_MASK |
+#if defined(BL702L)
+                 KYS_FIFO_MODE_MASK |
+#endif
+                 KYS_RC_EXT_MASK |
+                 KYS_GHOST_EN_MASK |
+                 KYS_DEG_EN_MASK |
+                 KYS_DEG_CNT_MASK);
+    reg_val |= ((config->col - 1) << KYS_COL_NUM_SHIFT);
+    reg_val |= ((config->row - 1) << KYS_ROW_NUM_SHIFT);
+    reg_val |= ((config->idle_duration) << KYS_RC_EXT_SHIFT);
+    reg_val |= (config->ghost_en << KYS_GHOST_EN_SHIFT);
+    reg_val |= (config->deglitch_en << KYS_DEG_EN_SHIFT);
+    reg_val |= (config->deglitch_cnt << KYS_DEG_CNT_SHIFT);
+#if defined(BL702L)
+    reg_val |= (0x1 << KYS_FIFO_MODE_SHIFT);
+#endif
+    putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+}
+
+/**
+ * @brief keyscan enable
+ *
+ */
+void bflb_kys_enable(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t reg_val;
+
+    reg_base = dev->reg_base;
+    reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+    reg_val |= (0x1 << KYS_KS_EN_SHIFT);
+    putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+}
+
+/**
+ * @brief keyscan disable
+ *
+ */
+void bflb_kys_disable(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t reg_val;
+
+    reg_base = dev->reg_base;
+
+    reg_val = getreg32(reg_base + KYS_KS_CTRL_OFFSET);
+    reg_val &= ~(KYS_KS_EN_MASK);
+    putreg32(reg_val, reg_base + KYS_KS_CTRL_OFFSET);
+}
+
+/**
+ * @brief keyscan interrupt enable
+ *
+ * @param dev
+ * @param flag interrupt flag @KEYSCAN_INT_EN define
+ * @param enable enable or disable interrupt
+ */
+void bflb_kys_int_enable(struct bflb_device_s *dev, uint32_t flag, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t reg_val_en;
+
+    reg_base = dev->reg_base;
+    reg_val_en = getreg32(reg_base + KYS_KS_INT_EN_OFFSET);
+
+    if (enable) {
+        reg_val_en |= (flag);
+    } else {
+        reg_val_en &= ~(flag);
+    }
+    putreg32(reg_val_en, reg_base + KYS_KS_INT_EN_OFFSET);
+}
+
+/**
+ * @brief keyscan interrupt clear flag
+ *
+ * @param dev
+ * @param flag
+ */
+void bflb_kys_int_clear(struct bflb_device_s *dev, uint32_t flag)
+{
+    putreg32(flag, dev->reg_base + KYS_KEYCODE_CLR_OFFSET);
+}
+/**
+ * @brief keyscan get interrupt status
+ *
+ * @param dev
+ * @return uint32_t
+ */
+uint32_t bflb_kys_get_int_status(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t reg_sts_val, reg_mask_val;
+
+    reg_base = dev->reg_base;
+    reg_sts_val = getreg32(reg_base + KYS_KS_INT_STS_OFFSET);
+    reg_mask_val = getreg32(reg_base + KYS_KS_INT_EN_OFFSET);
+
+    return (reg_sts_val & (reg_mask_val));
+}
+
+#if defined(BL702L)
+/**
+ * @brief get keyscan keycode index in fifo
+ *
+ * @param dev
+ * @param fifo_head
+ * @param fifo_tail
+ * @param fifo_valid_cnt
+ *
+ */
+void bflb_kys_get_fifo_info(struct bflb_device_s *dev, uint8_t *fifo_head, uint8_t *fifo_tail, uint8_t *fifo_valid_cnt)
+{
+    uint32_t reg_base;
+    uint32_t reg_val;
+
+    reg_base = dev->reg_base;
+    reg_val = getreg32(reg_base + KYS_KEYFIFO_IDX_OFFSET);
+
+    *fifo_head = (uint8_t)(reg_val & 0x7);
+    *fifo_tail = (uint8_t)((reg_val & 0x700) >> 8);
+    *fifo_valid_cnt = (uint8_t)((reg_val & 0xf0000) >> 16);
+}
+
+#endif
+/**
+ * @brief get keyscan keycode value
+ *
+ * @param dev
+ * @param index
+ * @return uint8_t
+ */
+uint8_t bflb_kys_read_keyvalue(struct bflb_device_s *dev, uint8_t index)
+{
+#if defined(BL702L)
+    return (uint8_t)(getreg32(dev->reg_base + KYS_KEYFIFO_VALUE_OFFSET) & 0xff);
+#endif
+#if defined(BL702)
+    return (uint8_t)((getreg32(dev->reg_base + KYS_KEYFIFO_VALUE_OFFSET) >> (index * 8)) & 0xff);
+#endif
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_l1c.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_l1c.c
new file mode 100755
index 0000000000..4e377e9f8a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_l1c.c
@@ -0,0 +1,188 @@
+#include "bflb_l1c.h"
+
+#if (defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL628)) && !defined(CPU_LP)
+#include "csi_core.h"
+void bflb_l1c_icache_enable(void)
+{
+    csi_icache_enable();
+}
+
+void bflb_l1c_icache_disable(void)
+{
+    csi_icache_disable();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_icache_invalid_all(void)
+{
+    csi_icache_invalid();
+}
+
+void bflb_l1c_dcache_enable(void)
+{
+    csi_dcache_enable();
+}
+
+void bflb_l1c_dcache_disable(void)
+{
+    csi_dcache_disable();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_all(void)
+{
+    csi_dcache_clean();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_all(void)
+{
+    csi_dcache_invalid();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_invalidate_all(void)
+{
+    csi_dcache_clean_invalid();
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
+{
+    csi_dcache_clean_range(addr, size);
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size)
+{
+    csi_dcache_invalid_range(addr, size);
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_clean_invalidate_range(void *addr, uint32_t size)
+{
+    csi_dcache_clean_invalid_range(addr, size);
+}
+#else
+
+#if defined(BL702) || defined(BL702L)
+extern void L1C_Cache_Enable_Set(uint8_t wayDisable);
+extern void L1C_Cache_Flush(void);
+#endif
+
+void bflb_l1c_icache_enable(void)
+{
+}
+
+void bflb_l1c_icache_disable(void)
+{
+#if defined(BL702) || defined(BL702L)
+    L1C_Cache_Enable_Set(0x0f);
+#endif
+}
+
+void bflb_l1c_icache_invalid_all(void)
+{
+}
+
+void bflb_l1c_dcache_enable(void)
+{
+}
+
+void bflb_l1c_dcache_disable(void)
+{
+}
+
+void bflb_l1c_dcache_clean_all(void)
+{
+}
+
+void bflb_l1c_dcache_invalidate_all(void)
+{
+#if defined(BL702) || defined(BL702L)
+    L1C_Cache_Flush();
+#endif
+}
+
+void bflb_l1c_dcache_clean_invalidate_all(void)
+{
+#if defined(BL702) || defined(BL702L)
+    L1C_Cache_Flush();
+#endif
+}
+
+void bflb_l1c_dcache_clean_range(void *addr, uint32_t size)
+{
+}
+
+ATTR_TCM_SECTION void bflb_l1c_dcache_invalidate_range(void *addr, uint32_t size)
+{
+#if defined(BL702) || defined(BL702L)
+    L1C_Cache_Flush();
+#endif
+}
+
+#if defined(BL702) || defined(BL702L)
+/****************************************************************************/ /**
+ * @brief  L1C cache write set
+ *
+ * @param  wt_en: L1C write through enable
+ * @param  wb_en: L1C write back enable
+ * @param  wa_en: L1C write allocate enable
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
+{
+    uint32_t regval = 0;
+
+    regval = getreg32(0x40009000 + 0x0);
+
+    if (wt_en) {
+        regval |= (1<<4);
+    } else {
+        regval &= ~(1<<4);
+    }
+
+    if (wb_en) {
+        regval |= (1<<5);
+    } else {
+        regval &= ~(1<<5);
+    }
+
+    if (wa_en) {
+        regval |= (1<<6);
+    } else {
+        regval &= ~(1<<6);
+    }
+
+    putreg32(regval, 0x40009000+0x0);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get hit count
+ *
+ * @param  hit_count_low: hit count low 32 bits pointer
+ * @param  hit_count_high: hit count high 32 bits pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high)
+{
+    *hit_count_low = getreg32(0x40009000 + 0x4);
+    *hit_count_high = getreg32(0x40009000 + 0x8);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get miss count
+ *
+ * @param  None
+ *
+ * @return Miss count
+ *
+*******************************************************************************/
+__WEAK
+uint32_t ATTR_TCM_SECTION bflb_l1c_miss_count_get(void)
+{
+    return getreg32(0x40009000 + 0xC);
+}
+
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c
new file mode 100755
index 0000000000..0414102e5b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mjpeg.c
@@ -0,0 +1,569 @@
+#include "bflb_mjpeg.h"
+#include "hardware/mjpeg_reg.h"
+
+static void bflb_mjpeg_set_yuv422_interleave_order(struct bflb_device_s *dev, uint8_t y0, uint8_t u0, uint8_t y1, uint8_t v0)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
+    regval &= ~MJPEG_REG_Y0_ORDER_MASK;
+    regval &= ~MJPEG_REG_U0_ORDER_MASK;
+    regval &= ~MJPEG_REG_Y1_ORDER_MASK;
+    regval &= ~MJPEG_REG_V0_ORDER_MASK;
+
+    regval |= (y0 << MJPEG_REG_Y0_ORDER_SHIFT);
+    regval |= (u0 << MJPEG_REG_U0_ORDER_SHIFT);
+    regval |= (y1 << MJPEG_REG_Y1_ORDER_SHIFT);
+    regval |= (v0 << MJPEG_REG_V0_ORDER_SHIFT);
+
+    putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
+}
+
+static void bflb_mjpeg_set_framesize(struct bflb_device_s *dev, uint16_t x, uint16_t y)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = 0;
+    regval |= (x << MJPEG_REG_FRAME_WBLK_SHIFT);
+    regval |= (y << MJPEG_REG_FRAME_HBLK_SHIFT);
+    putreg32(regval, reg_base + MJPEG_FRAME_SIZE_OFFSET);
+}
+
+void bflb_mjpeg_init(struct bflb_device_s *dev, const struct bflb_mjpeg_config_s *config)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint16_t blocks;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_ENABLE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+
+    regval = 0;
+    regval |= (3 << MJPEG_REG_W_XLEN_SHIFT); /* burst count 16 increment */
+    regval |= MJPEG_REG_READ_FWRAP;
+    regval |= MJPEG_REG_MJPEG_BIT_ORDER;
+
+    switch (config->format) {
+        case MJPEG_FORMAT_YUV422_YUYV:
+            regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+            bflb_mjpeg_set_yuv422_interleave_order(dev, 0, 1, 2, 3);
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+            break;
+        case MJPEG_FORMAT_YUV422_YVYU:
+            regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+            bflb_mjpeg_set_yuv422_interleave_order(dev, 0, 3, 2, 1);
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+            break;
+        case MJPEG_FORMAT_YUV422_UYVY:
+            regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+            bflb_mjpeg_set_yuv422_interleave_order(dev, 1, 0, 3, 2);
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+            break;
+        case MJPEG_FORMAT_YUV422_VYUY:
+            regval |= (3 << MJPEG_REG_YUV_MODE_SHIFT);
+            bflb_mjpeg_set_yuv422_interleave_order(dev, 1, 2, 3, 0);
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+            break;
+        case MJPEG_FORMAT_YUV422SP_NV16:
+            regval |= (2 << MJPEG_REG_YUV_MODE_SHIFT);
+            regval |= MJPEG_REG_ORDER_U_EVEN;
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+            break;
+        case MJPEG_FORMAT_YUV422SP_NV61:
+            regval |= (2 << MJPEG_REG_YUV_MODE_SHIFT);
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 7) >> 3);
+            break;
+        case MJPEG_FORMAT_YUV420SP_NV12:
+            regval |= (0 << MJPEG_REG_YUV_MODE_SHIFT);
+            regval |= MJPEG_REG_ORDER_U_EVEN;
+
+            if (config->resolution_x % 16) {
+                regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
+            }
+
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 15) >> 4);
+            break;
+        case MJPEG_FORMAT_YUV420SP_NV21:
+            regval |= (0 << MJPEG_REG_YUV_MODE_SHIFT);
+
+            if (config->resolution_x % 16) {
+                regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
+            }
+
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 15) >> 4, (config->resolution_y + 15) >> 3);
+            break;
+        case MJPEG_FORMAT_GRAY:
+            regval |= (1 << MJPEG_REG_YUV_MODE_SHIFT);
+
+            if (config->resolution_x % 16) {
+                regval |= MJPEG_REG_LAST_HF_WBLK_DMY;
+            }
+
+            if (config->resolution_y % 16) {
+                regval |= MJPEG_REG_LAST_HF_HBLK_DMY;
+            }
+
+            bflb_mjpeg_set_framesize(dev, (config->resolution_x + 7) >> 3, (config->resolution_y + 7) >> 3);
+            break;
+
+        default:
+            break;
+    }
+
+    putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_WAIT_CYCLE_MASK;
+    regval |= (0x100 << MJPEG_REG_MJPEG_WAIT_CYCLE_SHIFT);
+    regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_SWAP_MODE_OFFSET);
+    regval &= ~MJPEG_REG_W_SWAP_MODE;
+    putreg32(regval, reg_base + MJPEG_SWAP_MODE_OFFSET);
+
+    putreg32(config->input_bufaddr0, reg_base + MJPEG_YY_FRAME_ADDR_OFFSET);
+    putreg32(config->input_bufaddr1, reg_base + MJPEG_UV_FRAME_ADDR_OFFSET);
+
+    blocks = config->rows / 8;
+
+    switch (config->format) {
+        case MJPEG_FORMAT_YUV422_YUYV:
+        case MJPEG_FORMAT_YUV422_YVYU:
+        case MJPEG_FORMAT_YUV422_UYVY:
+        case MJPEG_FORMAT_YUV422_VYUY:
+            putreg32((0 << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET); /* uv << 16 + yy */
+            break;
+        case MJPEG_FORMAT_YUV422SP_NV16:
+        case MJPEG_FORMAT_YUV422SP_NV61:
+            putreg32((blocks << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET);
+            break;
+        case MJPEG_FORMAT_YUV420SP_NV12:
+        case MJPEG_FORMAT_YUV420SP_NV21:
+            putreg32((blocks << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET);
+            break;
+        case MJPEG_FORMAT_GRAY:
+            putreg32((0 << 16) + blocks, reg_base + MJPEG_YUV_MEM_OFFSET);
+            break;
+
+        default:
+            break;
+    }
+
+    putreg32(config->output_bufaddr, reg_base + MJPEG_JPEG_FRAME_ADDR_OFFSET);
+    putreg32(config->output_bufsize / 128, reg_base + MJPEG_JPEG_STORE_MEMORY_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+    regval &= ~MJPEG_REG_INT_NORMAL_EN;
+    regval &= ~MJPEG_REG_INT_CAM_EN;
+    regval &= ~MJPEG_REG_INT_MEM_EN;
+    regval &= ~MJPEG_REG_INT_FRAME_EN;
+    regval &= ~MJPEG_REG_INT_IDLE_EN;
+    regval &= ~MJPEG_REG_INT_SWAP_EN;
+    regval &= ~MJPEG_REG_FRAME_CNT_TRGR_INT_MASK;
+    regval |= (1 << MJPEG_REG_FRAME_CNT_TRGR_INT_SHIFT); /* trigger int with one frame */
+    putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
+    regval &= ~MJPEG_REG_HEAD_BYTE_MASK;
+    regval &= ~MJPEG_REG_TAIL_EXP;
+    putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
+
+    /* Clear interrupt */
+    putreg32(0x3F00, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
+
+    static uint16_t q_table_50_y[64] = {
+        16, 11, 10, 16, 24, 40, 51, 61,
+        12, 12, 14, 19, 26, 58, 60, 55,
+        14, 13, 16, 24, 40, 57, 69, 56,
+        14, 17, 22, 29, 51, 87, 80, 62,
+        18, 22, 37, 56, 68, 109, 103, 77,
+        24, 35, 55, 64, 81, 104, 113, 92,
+        49, 64, 78, 87, 103, 121, 120, 101,
+        72, 92, 95, 98, 112, 100, 103, 99
+    };
+
+    static uint16_t q_table_50_uv[64] = {
+        17, 18, 24, 47, 99, 99, 99, 99,
+        18, 21, 26, 66, 99, 99, 99, 99,
+        24, 26, 56, 99, 99, 99, 99, 99,
+        47, 66, 99, 99, 99, 99, 99, 99,
+        99, 99, 99, 99, 99, 99, 99, 99,
+        99, 99, 99, 99, 99, 99, 99, 99,
+        99, 99, 99, 99, 99, 99, 99, 99,
+        99, 99, 99, 99, 99, 99, 99, 99
+    };
+
+    uint16_t tmp_table_y[64] = { 0 };
+    uint16_t tmp_table_uv[64] = { 0 };
+
+    if (config->input_yy_table) {
+        bflb_mjpeg_calculate_quantize_table(config->quality, config->input_yy_table, tmp_table_y);
+    } else {
+        bflb_mjpeg_calculate_quantize_table(config->quality, q_table_50_y, tmp_table_y);
+    }
+    if (config->input_uv_table) {
+        bflb_mjpeg_calculate_quantize_table(config->quality, config->input_uv_table, tmp_table_uv);
+    } else {
+        bflb_mjpeg_calculate_quantize_table(config->quality, q_table_50_uv, tmp_table_uv);
+    }
+
+    bflb_mjpeg_fill_quantize_table(dev, tmp_table_y, tmp_table_uv);
+}
+
+void bflb_mjpeg_start(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
+    regval |= MJPEG_REG_MJPEG_ENABLE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+}
+
+void bflb_mjpeg_stop(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_1_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_ENABLE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_1_OFFSET);
+}
+
+void bflb_mjpeg_sw_run(struct bflb_device_s *dev, uint8_t frame_count)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_SW_KICK_MODE;
+    regval &= ~MJPEG_REG_SW_FRAME_MASK;
+    regval |= (frame_count << MJPEG_REG_SW_FRAME_SHIFT);
+    regval |= MJPEG_REG_MJPEG_SW_MODE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval |= MJPEG_REG_MJPEG_SW_RUN;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_SW_RUN;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_kick_run(struct bflb_device_s *dev, uint16_t kick_count)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval |= MJPEG_REG_SW_KICK_MODE;
+    regval &= ~MJPEG_REG_SW_FRAME_MASK;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval |= MJPEG_REG_MJPEG_SW_MODE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_YUV_MEM_SW_OFFSET);
+    regval &= ~MJPEG_REG_SW_KICK_HBLK_MASK;
+    regval |= (kick_count << MJPEG_REG_SW_KICK_HBLK_SHIFT);
+    putreg32(regval, reg_base + MJPEG_YUV_MEM_SW_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval |= MJPEG_REG_MJPEG_SW_RUN;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_SW_RUN;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_kick_stop(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_SW_KICK_MODE;
+    regval &= ~MJPEG_REG_SW_FRAME_MASK;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval |= MJPEG_REG_MJPEG_SW_MODE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_MJPEG_SW_MODE;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_kick(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval |= MJPEG_REG_SW_KICK;
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+void bflb_mjpeg_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+
+    if (mask) {
+        regval &= ~MJPEG_REG_INT_NORMAL_EN;
+    } else {
+        regval |= MJPEG_REG_INT_NORMAL_EN;
+    }
+
+    putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
+}
+
+void bflb_mjpeg_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+
+    if (mask) {
+        regval &= ~MJPEG_REG_INT_CAM_EN;
+        regval &= ~MJPEG_REG_INT_MEM_EN;
+        regval &= ~MJPEG_REG_INT_FRAME_EN;
+        regval &= ~MJPEG_REG_INT_IDLE_EN;
+        regval &= ~MJPEG_REG_INT_SWAP_EN;
+    } else {
+        regval |= MJPEG_REG_INT_CAM_EN;
+        regval |= MJPEG_REG_INT_MEM_EN;
+        regval |= MJPEG_REG_INT_FRAME_EN;
+        regval |= MJPEG_REG_INT_IDLE_EN;
+        regval |= MJPEG_REG_INT_SWAP_EN;
+    }
+
+    putreg32(regval, reg_base + MJPEG_CONTROL_3_OFFSET);
+}
+
+uint32_t bflb_mjpeg_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_3_OFFSET);
+    regval &= 0xf0;
+
+    return regval;
+}
+
+void bflb_mjpeg_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg32(int_clear, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
+}
+
+uint8_t bflb_mjpeg_get_frame_count(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    return ((getreg32(reg_base + MJPEG_CONTROL_3_OFFSET) & MJPEG_FRAME_VALID_CNT_MASK) >> MJPEG_FRAME_VALID_CNT_SHIFT);
+}
+
+void bflb_mjpeg_pop_one_frame(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg32(1, reg_base + MJPEG_FRAME_FIFO_POP_OFFSET);
+}
+
+uint32_t bflb_mjpeg_get_frame_info(struct bflb_device_s *dev, uint8_t **pic)
+{
+    uint32_t bytes;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    *pic = (uint8_t *)getreg32(reg_base + MJPEG_START_ADDR0_OFFSET);
+    bytes = (getreg32(reg_base + MJPEG_BIT_CNT0_OFFSET) + 7) >> 3;
+
+    return bytes;
+}
+
+void bflb_mjpeg_calculate_quantize_table(uint8_t quality, uint16_t *input_table, uint16_t *output_table)
+{
+    uint32_t scale_factor, i;
+
+    if (quality == 0) {
+        quality = 1;
+    } else if (quality > 100) {
+        quality = 100;
+    }
+
+    if (quality < 50) {
+        scale_factor = 5000000 / quality;
+    } else {
+        scale_factor = 200000 - quality * 2000;
+    }
+
+    for (i = 0; i < 64; i++) {
+        output_table[i] = (input_table[i] * scale_factor + 50000) / 100000;
+
+        if (output_table[i] == 0) {
+            output_table[i] = 1;
+        } else if (output_table[i] > 0xff) {
+            output_table[i] = 0xff;
+        }
+    }
+}
+
+void bflb_mjpeg_fill_quantize_table(struct bflb_device_s *dev, uint16_t *input_yy, uint16_t *input_uv)
+{
+#define MJPEG_Q_PARAM_00_OFFSET (0x400)
+#define MJPEG_Q_PARAM_40_OFFSET (0x480)
+
+    uint8_t i, j;
+    uint16_t tmp1;
+    uint16_t tmp2;
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    for (i = 0; i < 8; i++) {
+        for (j = 0; j < 4; j++) {
+            tmp1 = 2048 / input_yy[16 * j + i];
+            tmp2 = 2048 / input_yy[16 * j + i + 8];
+
+            if (20480 / input_yy[16 * j + i] % 10 > 4) {
+                tmp1++;
+            }
+
+            if (20480 / input_yy[16 * j + i + 8] % 10 > 4) {
+                tmp2++;
+            }
+
+            putreg32(tmp1 | tmp2 << 16, reg_base + MJPEG_Q_PARAM_00_OFFSET + (i * 4 + j) * 4);
+        }
+    }
+
+    for (i = 0; i < 8; i++) {
+        for (j = 0; j < 4; j++) {
+            tmp1 = 2048 / input_uv[16 * j + i];
+            tmp2 = 2048 / input_uv[16 * j + i + 8];
+
+            if (20480 / input_uv[16 * j + i] % 10 > 4) {
+                tmp1++;
+            }
+
+            if (20480 / input_uv[16 * j + i + 8] % 10 > 4) {
+                tmp2++;
+            }
+
+            putreg32(tmp1 | tmp2 << 16, reg_base + MJPEG_Q_PARAM_40_OFFSET + (i * 4 + j) * 4);
+        }
+    }
+
+    regval = getreg32(reg_base + MJPEG_Q_ENC_OFFSET);
+    regval |= MJPEG_REG_Q_SRAM_SW;
+    putreg32(regval, reg_base + MJPEG_Q_ENC_OFFSET);
+}
+
+void bflb_mjpeg_fill_jpeg_header_tail(struct bflb_device_s *dev, uint8_t *header, uint32_t header_len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    arch_memcpy_fast((void *)(reg_base + 0x800), header, header_len);
+
+    regval = getreg32(reg_base + MJPEG_HEADER_BYTE_OFFSET);
+    regval &= ~MJPEG_REG_HEAD_BYTE_MASK;
+    regval |= (header_len << MJPEG_REG_HEAD_BYTE_SHIFT);
+    regval |= MJPEG_REG_TAIL_EXP;
+    putreg32(regval, reg_base + MJPEG_HEADER_BYTE_OFFSET);
+}
+
+void bflb_mjpeg_set_yuv420sp_cam_input(struct bflb_device_s *dev, uint8_t yy, uint8_t uv)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + MJPEG_CONTROL_2_OFFSET);
+    regval &= ~MJPEG_REG_YY_DVP2AXI_SEL_MASK;
+    regval &= ~MJPEG_REG_UV_DVP2AXI_SEL_MASK;
+    regval |= (yy << MJPEG_REG_YY_DVP2AXI_SEL_SHIFT);
+    regval |= (uv << MJPEG_REG_UV_DVP2AXI_SEL_SHIFT);
+    putreg32(regval, reg_base + MJPEG_CONTROL_2_OFFSET);
+}
+
+int bflb_mjpeg_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case MJPEG_CMD_SET_INPUTADDR0:
+            putreg32(arg, reg_base + MJPEG_YY_FRAME_ADDR_OFFSET);
+            break;
+        case MJPEG_CMD_SET_INPUTADDR1:
+            putreg32(arg, reg_base + MJPEG_UV_FRAME_ADDR_OFFSET);
+            break;
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mtimer.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mtimer.c
new file mode 100755
index 0000000000..27b09d5b71
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_mtimer.c
@@ -0,0 +1,123 @@
+#include "bflb_mtimer.h"
+#include "bflb_core.h"
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#include 
+#else
+#include 
+#endif
+
+static void (*systick_callback)(void);
+static uint64_t current_set_ticks = 0;
+
+static void systick_isr(int irq, void *arg)
+{
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    *(volatile uint64_t *)(CLIC_CTRL_BASE + CLIC_MTIMECMP_OFFSET) += current_set_ticks;
+#else
+    csi_coret_config(current_set_ticks, 7);
+#endif
+    systick_callback();
+}
+
+void bflb_mtimer_config(uint64_t ticks, void (*interruptfun)(void))
+{
+    bflb_irq_disable(7);
+
+    current_set_ticks = ticks;
+    systick_callback = interruptfun;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    *(volatile uint64_t *)(CLIC_CTRL_BASE + CLIC_MTIMECMP_OFFSET) = (*(volatile uint64_t *)(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET)) + ticks;
+#else
+    csi_coret_config_use(ticks, 7);
+#endif
+
+    bflb_irq_attach(7, systick_isr, NULL);
+    bflb_irq_enable(7);
+}
+
+__WEAK uint32_t ATTR_TCM_SECTION bflb_mtimer_get_freq(void)
+{
+    return 1 * 1000 * 1000;
+}
+
+uint64_t ATTR_TCM_SECTION bflb_mtimer_get_time_us()
+{
+    volatile uint64_t tmp_low, tmp_high, tmp_low1, tmp_high1;
+
+    do {
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+        tmp_high = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET + 4);
+        tmp_low = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET);
+        tmp_low1 = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET);
+        tmp_high1 = getreg32(CLIC_CTRL_BASE + CLIC_MTIME_OFFSET + 4);
+#else
+        tmp_high = (uint64_t)csi_coret_get_valueh();
+        tmp_low = (uint64_t)csi_coret_get_value();
+        tmp_low1 = (uint64_t)csi_coret_get_value();
+        tmp_high1 = (uint64_t)csi_coret_get_valueh();
+#endif
+    } while (tmp_low > tmp_low1 || tmp_high != tmp_high1);
+#ifdef CONFIG_MTIMER_CUSTOM_FREQUENCE
+    return ((uint64_t)(((tmp_high1 << 32) + tmp_low1)) * ((uint64_t)(1 * 1000 * 1000)) / bflb_mtimer_get_freq());
+#else
+    return (uint64_t)(((tmp_high1 << 32) + tmp_low1));
+#endif
+}
+
+uint32_t ATTR_TCM_SECTION __attribute__((weak)) __div64_32(uint64_t *n, uint32_t base)
+{
+    uint64_t rem = *n;
+    uint64_t b = base;
+    uint64_t res, d = 1;
+    uint32_t high = rem >> 32;
+
+    res = 0;
+    if (high >= base) {
+        high /= base;
+        res = (uint64_t) high << 32;
+        rem -= (uint64_t) (high*base) << 32;
+    }
+    while ((int64_t)b > 0 && b < rem) {
+        b = b+b;
+        d = d+d;
+    }
+
+    do {
+        if (rem >= b) {
+            rem -= b;
+            res += d;
+        }
+        b >>= 1;
+        d >>= 1;
+    } while (d);
+
+    *n = res;
+    return rem;
+}
+
+uint64_t ATTR_TCM_SECTION bflb_mtimer_get_time_ms()
+{
+#ifdef BFLB_BOOT2
+    uint64_t ret = bflb_mtimer_get_time_us();
+    __div64_32(&ret, 1000);
+    return ret;
+#else
+    return bflb_mtimer_get_time_us() / 1000;
+#endif
+}
+
+void ATTR_TCM_SECTION bflb_mtimer_delay_us(uint32_t time)
+{
+    uint64_t start_time = bflb_mtimer_get_time_us();
+
+    while (bflb_mtimer_get_time_us() - start_time < time) {
+    }
+}
+
+void ATTR_TCM_SECTION bflb_mtimer_delay_ms(uint32_t time)
+{
+    uint64_t start_time = bflb_mtimer_get_time_ms();
+
+    while (bflb_mtimer_get_time_ms() - start_time < time) {
+    }
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v1.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v1.c
new file mode 100755
index 0000000000..766c6e9265
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v1.c
@@ -0,0 +1,278 @@
+#include "bflb_pwm_v1.h"
+#include "bflb_clock.h"
+#include "hardware/pwm_v1_reg.h"
+
+void bflb_pwm_v1_channel_init(struct bflb_device_s *dev, uint8_t ch, const struct bflb_pwm_v1_channel_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    /* stop pwm */
+    regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+    regval |= PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+        regval &= PWM_STS_TOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval == 0);
+
+    /* config clock source and dividor */
+    regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+    regval &= ~PWM_REG_CLK_SEL_MASK;
+    if (config->clk_source == BFLB_SYSTEM_XCLK) {
+        regval |= (0 << PWM_REG_CLK_SEL_SHIFT);
+    } else if (config->clk_source == BFLB_SYSTEM_PBCLK) {
+        regval |= (1 << PWM_REG_CLK_SEL_SHIFT);
+    } else if (config->clk_source == BFLB_SYSTEM_32K_CLK) {
+        regval |= (2 << PWM_REG_CLK_SEL_SHIFT);
+    } else {
+    }
+    putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+    regval = getreg32(reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20);
+    regval &= ~PWM_CLK_DIV_MASK;
+    regval |= (uint32_t)config->clk_div << PWM_CLK_DIV_SHIFT;
+    putreg32(regval, reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20);
+
+    /* config pwm period */
+    regval = getreg32(reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+    regval &= ~PWM_PERIOD_MASK;
+    regval |= (uint32_t)config->period << PWM_PERIOD_SHIFT;
+    putreg32(regval, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+}
+
+void bflb_pwm_v1_channel_deinit(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    /* stop pwmx */
+    regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+    regval |= PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+        regval &= PWM_STS_TOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval == 0);
+
+    /* restore pwmx_clkdiv register with default value */
+    putreg32(0, reg_base + PWM0_CLKDIV_OFFSET + ch * 0x20);
+
+    /* restore pwmx_thre1 register with default value */
+    putreg32(0, reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
+
+    /* restore pwmx_thre2 register with default value */
+    putreg32(0, reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
+
+    /* restore pwmx_period register with default value */
+    putreg32(0, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+
+    /* restore pwmx_config register with default value */
+    regval = PWM_STOP_MODE;
+    putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+    /* restore pwmx_interrupt register with default value */
+    putreg32(0, reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+
+    /* clear all interrupt */
+    putreg32(0xFFFFFFFF, reg_base + PWM_INT_CONFIG_OFFSET);
+}
+
+void bflb_pwm_v1_start(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t start_time;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+    regval &= ~PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+        regval &= PWM_STS_TOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval != 0);
+}
+
+void bflb_pwm_v1_stop(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t start_time;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+    regval |= PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+        regval &= PWM_STS_TOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval == 0);
+}
+
+void bflb_pwm_v1_set_period(struct bflb_device_s *dev, uint8_t ch, uint16_t period)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+    regval &= ~PWM_PERIOD_MASK;
+    regval |= (uint32_t)period << PWM_PERIOD_SHIFT;
+    putreg32(regval, reg_base + PWM0_PERIOD_OFFSET + ch * 0x20);
+}
+
+void bflb_pwm_v1_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
+    regval &= ~PWM_THRE1_MASK;
+    regval |= low_threhold;
+    putreg32(regval, reg_base + PWM0_THRE1_OFFSET + ch * 0x20);
+
+    regval = getreg32(reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
+    regval &= ~PWM_THRE2_MASK;
+    regval |= high_threhold;
+    putreg32(regval, reg_base + PWM0_THRE2_OFFSET + ch * 0x20);
+}
+
+void bflb_pwm_v1_int_enable(struct bflb_device_s *dev, uint8_t ch, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+    if (enable) {
+        regval |= PWM_INT_ENABLE;
+    } else {
+        regval &= ~PWM_INT_ENABLE;
+    }
+    putreg32(regval, reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+}
+
+uint32_t bflb_pwm_v1_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET);
+    return (regval);
+}
+
+void bflb_pwm_v1_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t timeout_count = 160 * 1000;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET);
+    regval |= int_clear;
+    putreg32(regval, dev->reg_base + PWM_INT_CONFIG_OFFSET);
+    do {
+        regval = getreg32(reg_base + PWM_INT_CONFIG_OFFSET);
+        timeout_count--;
+        if (timeout_count == 0) {
+            break;
+        }
+    } while (regval & (int_clear >> PWM_INT_CLEAR_SHIFT));
+
+    regval &= ~int_clear;
+    putreg32(regval, dev->reg_base + PWM_INT_CONFIG_OFFSET);
+}
+
+int bflb_pwm_v1_feature_control(struct bflb_device_s *dev, uint8_t ch, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    switch (cmd) {
+        case PWM_CMD_SET_STOP_MODE:
+            regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            if (arg == PWM_STOP_MODE_ABRUPT) {
+                regval &= ~PWM_STOP_MODE;
+            } else {
+                regval |= PWM_STOP_MODE;
+            }
+            putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            break;
+
+        case PWM_CMD_SET_OUT_INVERT:
+            regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            if (arg) {
+                regval |= PWM_OUT_INV;
+            } else {
+                regval &= ~PWM_OUT_INV;
+            }
+            putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            break;
+
+        case PWM_CMD_SET_SW_MODE:
+            regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            if (arg) {
+                regval |= PWM_SW_MODE;
+            } else {
+                regval &= ~PWM_SW_MODE;
+            }
+            putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            break;
+
+        case PWM_CMD_SET_SW_FORCE_VALUE:
+            regval = getreg32(reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            if (arg) {
+                regval |= PWM_SW_FORCE_VAL;
+            } else {
+                regval &= ~PWM_SW_FORCE_VAL;
+            }
+            putreg32(regval, reg_base + PWM0_CONFIG_OFFSET + ch * 0x20);
+            break;
+
+        case PWM_CMD_SET_REPT_COUNT:
+            regval = getreg32(reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+            regval &= ~(PWM_INT_PERIOD_CNT_MASK);
+            regval |= (arg << PWM_INT_PERIOD_CNT_SHIFT);
+            putreg32(regval, reg_base + PWM0_INTERRUPT_OFFSET + ch * 0x20);
+            break;
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v2.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v2.c
new file mode 100755
index 0000000000..c70164da5d
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_pwm_v2.c
@@ -0,0 +1,388 @@
+#include "bflb_pwm_v2.h"
+#include "bflb_clock.h"
+#include "hardware/pwm_v2_reg.h"
+
+void bflb_pwm_v2_init(struct bflb_device_s *dev, const struct bflb_pwm_v2_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    /* stop pwm */
+    regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+    regval |= PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+        regval &= PWM_STS_STOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval == 0);
+
+    /* config clock source and dividor */
+    regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+    regval &= ~PWM_REG_CLK_SEL_MASK;
+    if (config->clk_source == BFLB_SYSTEM_XCLK) {
+        regval |= (0 << PWM_REG_CLK_SEL_SHIFT);
+    } else if (config->clk_source == BFLB_SYSTEM_PBCLK) {
+        regval |= (1 << PWM_REG_CLK_SEL_SHIFT);
+    } else if (config->clk_source == BFLB_SYSTEM_32K_CLK) {
+        regval |= (2 << PWM_REG_CLK_SEL_SHIFT);
+    } else {
+    }
+    regval &= ~PWM_CLK_DIV_MASK;
+    regval |= (uint32_t)config->clk_div << PWM_CLK_DIV_SHIFT;
+    putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+    /* config pwm period */
+    regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+    regval &= ~PWM_PERIOD_MASK;
+    regval |= (uint32_t)config->period << PWM_PERIOD_SHIFT;
+    putreg32(regval, reg_base + PWM_MC0_PERIOD_OFFSET);
+}
+
+void bflb_pwm_v2_deinit(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    /* stop pwm */
+    regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+    regval |= PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+        regval &= PWM_STS_STOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval == 0);
+
+    /* restore pwm_mc0_config0 register with default value */
+    regval = PWM_STS_STOP | PWM_STOP_MODE | PWM_STOP_EN | PWM_ADC_TRG_SRC_MASK;
+    putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+    /* restore pwm_mc0_config1 register with default value */
+    regval = PWM_CH3_NPL | PWM_CH3_PPL | PWM_CH2_NPL | PWM_CH2_PPL;
+    regval |= PWM_CH1_NPL | PWM_CH1_PPL | PWM_CH0_NPL | PWM_CH0_PPL;
+    regval |= PWM_CH3_NSI | PWM_CH2_NSI | PWM_CH1_NSI | PWM_CH0_NSI;
+    putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+
+    /* restore pwm_mc0_period register with default value */
+    putreg32(0, reg_base + PWM_MC0_PERIOD_OFFSET);
+
+    /* restore pwm_mc0_dead_time register with default value */
+    putreg32(0, reg_base + PWM_MC0_DEAD_TIME_OFFSET);
+
+    /* restore pwm_mc0_chx_thre(x=0...3) register with default value */
+    putreg32(0, reg_base + PWM_MC0_CH0_THRE_OFFSET);
+    putreg32(1, reg_base + PWM_MC0_CH1_THRE_OFFSET);
+    putreg32(2, reg_base + PWM_MC0_CH2_THRE_OFFSET);
+    putreg32(3, reg_base + PWM_MC0_CH3_THRE_OFFSET);
+
+    /* restore pwm_mc0_int_mask register with default value */
+    putreg32(0xFFFFFFFF, reg_base + PWM_MC0_INT_MASK_OFFSET);
+    /* clear all interrupt */
+    putreg32(0xFFFFFFFF, reg_base + PWM_MC0_INT_CLEAR_OFFSET);
+    /* restore pwm_mc0_int_en register with default value */
+    putreg32(0xFFFFFFFF, reg_base + PWM_MC0_INT_EN_OFFSET);
+}
+
+void bflb_pwm_v2_set_period(struct bflb_device_s *dev, uint16_t period)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+    regval &= ~PWM_PERIOD_MASK;
+    regval |= (uint32_t)period << PWM_PERIOD_SHIFT;
+    putreg32(regval, reg_base + PWM_MC0_PERIOD_OFFSET);
+}
+
+void bflb_pwm_v2_start(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+    regval &= ~PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+        regval &= PWM_STS_STOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval != 0);
+}
+
+void bflb_pwm_v2_stop(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+    regval |= PWM_STOP_EN;
+    putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+
+    start_time = bflb_mtimer_get_time_ms();
+    do {
+        regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+        regval &= PWM_STS_STOP;
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return;
+        }
+    } while (regval == 0);
+}
+
+float bflb_pwm_v2_get_frequency(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t tmp;
+    float src, div, period;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+    /* get clock source frequency */
+    tmp = (regval & PWM_REG_CLK_SEL_MASK) >> PWM_REG_CLK_SEL_SHIFT;
+    switch (tmp) {
+        case 0:
+            src = (float)bflb_clk_get_system_clock(0); /* TODO: because this function has not been implemented */
+            break;
+        case 1:
+            src = (float)bflb_clk_get_system_clock(1); /* TODO: because this function has not been implemented */
+            break;
+        case 2:
+            src = (float)bflb_clk_get_system_clock(2); /* TODO: because this function has not been implemented */
+            break;
+        default:
+            src = 0.0f;
+            break;
+    }
+    /* get clock dividor */
+    tmp = (regval & PWM_CLK_DIV_MASK) >> PWM_CLK_DIV_SHIFT;
+    div = tmp ? (float)tmp : 1.0f;
+    /* get pwm period count */
+    regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+    tmp = (regval & PWM_PERIOD_MASK) >> PWM_PERIOD_SHIFT;
+    period = (float)tmp;
+    /* calculate freaueny */
+    return (src / div / period);
+}
+
+void bflb_pwm_v2_channel_init(struct bflb_device_s *dev, uint8_t ch, struct bflb_pwm_v2_channel_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+    if (config->positive_polarity == PWM_POLARITY_ACTIVE_LOW) {
+        regval &= ~(PWM_CH0_PPL << ch * 2);
+    } else {
+        regval |= (PWM_CH0_PPL << ch * 2);
+    }
+    if (config->negative_polarity == PWM_POLARITY_ACTIVE_LOW) {
+        regval &= ~(PWM_CH0_NPL << ch * 2);
+    } else {
+        regval |= (PWM_CH0_NPL << ch * 2);
+    }
+    if (config->positive_stop_state == PWM_STATE_ACTIVE) {
+        regval |= (PWM_CH0_PSI << ch * 4);
+    } else {
+        regval &= ~(PWM_CH0_PSI << ch * 4);
+    }
+    if (config->negative_stop_state == PWM_STATE_INACTIVE) {
+        regval &= ~(PWM_CH0_NSI << ch * 4);
+    } else {
+        regval |= (PWM_CH0_NSI << ch * 4);
+    }
+    if (config->positive_brake_state == PWM_STATE_ACTIVE) {
+        regval |= (PWM_CH0_PBS << ch * 2);
+    } else {
+        regval &= ~(PWM_CH0_PBS << ch * 2);
+    }
+    if (config->negative_brake_state == PWM_STATE_ACTIVE) {
+        regval |= (PWM_CH0_NBS << ch * 2);
+    } else {
+        regval &= ~(PWM_CH0_NBS << ch * 2);
+    }
+    putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+    regval = getreg32(reg_base + PWM_MC0_DEAD_TIME_OFFSET);
+    regval &= ~(PWM_CH0_DTG_MASK << ch * 8);
+    regval |= ((uint32_t)config->dead_time << ch * 8);
+    putreg32(regval, reg_base + PWM_MC0_DEAD_TIME_OFFSET);
+}
+
+void bflb_pwm_v2_channel_set_threshold(struct bflb_device_s *dev, uint8_t ch, uint16_t low_threhold, uint16_t high_threhold)
+{
+    uint32_t regval;
+
+    regval = ((uint32_t)high_threhold << 16) | low_threhold;
+    putreg32(regval, dev->reg_base + PWM_MC0_CH0_THRE_OFFSET + ch * 4);
+}
+
+void bflb_pwm_v2_channel_positive_start(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+    regval |= (PWM_CH0_PEN << 4 * ch);
+    putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_channel_negative_start(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+    regval |= (PWM_CH0_NEN << 4 * ch);
+    putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_channel_positive_stop(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+    regval &= ~(PWM_CH0_PEN << 4 * ch);
+    putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_channel_negative_stop(struct bflb_device_s *dev, uint8_t ch)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + PWM_MC0_CONFIG1_OFFSET);
+    regval &= ~(PWM_CH0_NEN << 4 * ch);
+    putreg32(regval, reg_base + PWM_MC0_CONFIG1_OFFSET);
+}
+
+void bflb_pwm_v2_int_enable(struct bflb_device_s *dev, uint32_t int_en, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval_mask, regval_en;
+
+    reg_base = dev->reg_base;
+    regval_mask = getreg32(reg_base + PWM_MC0_INT_MASK_OFFSET);
+    regval_en = getreg32(reg_base + PWM_MC0_INT_EN_OFFSET);
+    if (enable) {
+        regval_mask &= ~int_en;
+        regval_en |= int_en;
+    } else {
+        regval_mask |= int_en;
+        regval_en &= ~int_en;
+    }
+    putreg32(regval_mask, reg_base + PWM_MC0_INT_MASK_OFFSET);
+    putreg32(regval_en, reg_base + PWM_MC0_INT_EN_OFFSET);
+}
+
+void bflb_pwm_v2_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    putreg32(int_clear, dev->reg_base + PWM_MC0_INT_CLEAR_OFFSET);
+}
+
+uint32_t bflb_pwm_v2_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval_sts, regval_mask, regval_en;
+
+    reg_base = dev->reg_base;
+    regval_sts = getreg32(reg_base + PWM_MC0_INT_STS_OFFSET);
+    regval_mask = getreg32(reg_base + PWM_MC0_INT_MASK_OFFSET);
+    regval_en = getreg32(reg_base + PWM_MC0_INT_EN_OFFSET);
+    return (regval_sts & ~regval_mask & regval_en);
+}
+
+int bflb_pwm_v2_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    switch (cmd) {
+        case PWM_CMD_SET_EXT_BRAKE_POLARITY:
+            regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+            if (arg == PWM_POLARITY_ACTIVE_HIGH) {
+                regval |= PWM_EXT_BREAK_PL;
+            } else {
+                regval &= ~PWM_EXT_BREAK_PL;
+            }
+            putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+            break;
+
+        case PWM_CMD_SET_EXT_BRAKE_ENABLE:
+            regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+            if (arg == true) {
+                regval |= PWM_EXT_BREAK_EN;
+            } else {
+                regval &= ~PWM_EXT_BREAK_EN;
+            }
+            putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+            break;
+
+        case PWM_CMD_SET_SW_BRAKE_ENABLE:
+            regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+            if (arg == true) {
+                regval |= PWM_SW_BREAK_EN;
+            } else {
+                regval &= ~PWM_SW_BREAK_EN;
+            }
+            putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+            break;
+
+        case PWM_CMD_SET_STOP_ON_REPT:
+            regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+            if (arg == true) {
+                regval |= PWM_STOP_ON_REPT;
+            } else {
+                regval &= ~PWM_STOP_ON_REPT;
+            }
+            putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+            break;
+
+        case PWM_CMD_SET_REPT_COUNT:
+            regval = getreg32(reg_base + PWM_MC0_PERIOD_OFFSET);
+            regval &= ~(PWM_INT_PERIOD_CNT_MASK);
+            regval |= (arg << PWM_INT_PERIOD_CNT_SHIFT);
+            putreg32(regval, reg_base + PWM_MC0_PERIOD_OFFSET);
+            break;
+
+        case PWM_CMD_SET_TRIG_ADC_SRC:
+            regval = getreg32(reg_base + PWM_MC0_CONFIG0_OFFSET);
+            regval &= ~(PWM_ADC_TRG_SRC_MASK);
+            regval |= (arg << PWM_ADC_TRG_SRC_SHIFT);
+            putreg32(regval, reg_base + PWM_MC0_CONFIG0_OFFSET);
+            break;
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c
new file mode 100755
index 0000000000..6287a8a7d8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_rtc.c
@@ -0,0 +1,76 @@
+#include "bflb_rtc.h"
+#include "hardware/rtc_reg.h"
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_RTC_BASE 0x4000F000
+#elif defined(BL808) || defined(BL606P) || defined(BL616)
+#define BFLB_RTC_BASE 0x2000F000
+#elif defined(BL628)
+#define BFLB_RTC_BASE 0x2008F000
+#endif
+
+void bflb_rtc_set_time(struct bflb_device_s *dev, uint64_t time)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t comp_l, comp_h;
+
+    reg_base = BFLB_RTC_BASE;
+
+    /* Clear & Disable RTC counter */
+    regval = getreg32(reg_base + HBN_CTL_OFFSET);
+    regval &= ~HBN_RTC_CTL_MASK;
+    putreg32(regval, reg_base + HBN_CTL_OFFSET);
+
+    /* Tigger RTC val read */
+    regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET);
+    regval |= HBN_RTC_TIME_LATCH;
+    putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+    regval &= ~HBN_RTC_TIME_LATCH;
+    putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+
+    /* Read RTC val */
+    comp_l = getreg32(reg_base + HBN_RTC_TIME_L_OFFSET);
+    comp_h = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff;
+
+    /* calculate RTC Comp time */
+    comp_l += (uint32_t)(time & 0xFFFFFFFF);
+    comp_h += (uint32_t)((time >> 32) & 0xFFFFFFFF);
+
+    /* Set RTC Comp time  */
+    putreg32(comp_l, reg_base + HBN_TIME_L_OFFSET);
+    putreg32(comp_h, reg_base + HBN_TIME_H_OFFSET);
+
+    regval = getreg32(reg_base + HBN_CTL_OFFSET);
+    regval |= HBN_RTC_DLY_OPTION;
+    regval |= (0x01 << 1);
+    putreg32(regval, reg_base + HBN_CTL_OFFSET);
+
+    /* Enable RTC Counter */
+    regval = getreg32(reg_base + HBN_CTL_OFFSET);
+    regval |= (1 << 0);
+    putreg32(regval, reg_base + HBN_CTL_OFFSET);
+}
+
+uint64_t bflb_rtc_get_time(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint64_t time_l;
+    uint64_t time_h;
+
+    reg_base = BFLB_RTC_BASE;
+
+    /* Tigger RTC val read */
+    regval = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET);
+    regval |= HBN_RTC_TIME_LATCH;
+    putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+    regval &= ~HBN_RTC_TIME_LATCH;
+    putreg32(regval, reg_base + HBN_RTC_TIME_H_OFFSET);
+
+    /* Read RTC val */
+    time_l = getreg32(reg_base + HBN_RTC_TIME_L_OFFSET);
+    time_h = getreg32(reg_base + HBN_RTC_TIME_H_OFFSET) & 0xff;
+
+    return (((uint64_t)time_h << 32) | (uint64_t)time_l);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sdio2.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sdio2.c
new file mode 100755
index 0000000000..114023a5e1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sdio2.c
@@ -0,0 +1,296 @@
+/**
+  ******************************************************************************
+  * @file    bflb_sdio2.c
+  * @version V1.0
+  * @date    2022-10-12
+  * @brief   This file is the low hardware abstraction layer file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2022 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "../include/bflb_sdio2.h"
+#include "../include/hardware/sdio2_reg.h"
+
+//#define SDIO2_DRV_DBG(a, ...) printf(a, ##__VA_ARGS__)
+#define SDIO2_DRV_DBG(a, ...)
+#ifndef BOOTROM
+#define SDIO2_DRV_ERR(a, ...) printf("[Error]:" a, ##__VA_ARGS__)
+#else
+extern void bflb_bootrom_printf(char *fmt, ...);
+#define SDIO2_DRV_ERR(a, ...) bflb_bootrom_printf("[Error]:" a, ##__VA_ARGS__)
+#endif
+#define SDU_INT_HOST 0
+
+static uintptr_t local_tx_buf[SDIO2_MAX_PORT_NUM][SDIO2_BYTE_PER_BUF / sizeof(uintptr_t)] ATTR_NOCACHE_RAM_SECTION;
+static uintptr_t local_rx_buf[SDIO2_MAX_PORT_NUM][SDIO2_BYTE_PER_BUF / sizeof(uintptr_t)] ATTR_NOCACHE_RAM_SECTION;
+
+/****************************************************************************/ /**
+ * @brief  Get sdio2 block size
+ *
+ * @param  dev  SDIO device pointer
+ *
+ * @return Block size
+ *
+*******************************************************************************/
+uint32_t bflb_sdio2_get_block_size(struct bflb_device_s *dev)
+{
+    uint16_t blk_size = 0;
+    uint32_t reg_base = dev->reg_base;
+
+    blk_size = getreg8(reg_base + SDIO2_FN1_BLK_SIZE_0_OFFSET);
+    blk_size |= ((getreg8(reg_base + SDIO2_FN1_BLK_SIZE_1_OFFSET) & SDIO2_FN1_BLK_SIZE_1_MASK) << 8);
+
+    return blk_size;
+}
+
+/****************************************************************************/ /**
+ * @brief  sdio2 init
+ *
+ * @param  dev: SDIO device pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_init(struct bflb_device_s *dev)
+{
+    uint32_t reg_base = dev->reg_base;
+    uint32_t regval = 0;
+
+    putreg16(0, reg_base + SDIO2_RD_BIT_MAP_OFFSET);
+    putreg16(0, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+
+    /* toggle SDIO_CCR_CIC_DnLdOvr on WL_SDIO_CCR_CARD_INT_CAUSE */
+    putreg8(SDIO2_CCR_CIC_DnLdOvr, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+    putreg8(0, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+
+    if (1) {
+        /* multiport */
+        regval = getreg32(reg_base + SDIO2_CONFIG2_OFFSET);
+        putreg32(regval | SDIO2_CONFIG2_MSK, reg_base + SDIO2_CONFIG2_OFFSET);
+        regval = getreg8(reg_base + SDIO2_CONFIG_OFFSET);
+        putreg8(regval | 0x00000010, reg_base + SDIO2_CONFIG_OFFSET);
+    }
+
+    /* unmask the interrupts */
+    putreg8(SDIO2_CCR_CIM_MASK, reg_base + SDIO2_CARD_INT_MASK_OFFSET);
+    /* select interrupt reset mode */
+    putreg8(0, reg_base + SDIO2_CARD_INT_MODE_OFFSET);
+
+    bflb_sdio2_tx_rx_queue_init(dev);
+
+    bflb_irq_attach(dev->irq_num, bflb_sdio2_isr, dev);
+    bflb_irq_enable(dev->irq_num);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDIO2 tx and rx queue init
+ *
+ * @param  dev: SDIO device pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_tx_rx_queue_init(struct bflb_device_s *dev)
+{
+    uint32_t reg_base = dev->reg_base;
+    uint16_t wr_bit_map = getreg16(reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+
+    for (uint8_t i = 0; i < SDIO2_MAX_PORT_NUM; i++) {
+        if (!(wr_bit_map & (1 << i))) {
+            /* attach new buffer */
+            putreg8(i, reg_base + SDIO2_WRITE_INDEX_OFFSET);
+            putreg32((uint32_t)&local_rx_buf[i][0], reg_base + SDIO2_SQ_WRITE_BASE_OFFSET);
+            putreg16(1 << i, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+#if SDU_INT_HOST
+            putreg8((SDIO2_CCR_CS_ReadCISRdy | SDIO2_CCR_CS_DnLdRdy | SDIO2_CCR_CS_IORdy),
+                    reg_base + SDIO2_CARD_TO_HOST_EVENT_OFFSET);
+#endif
+        }
+    }
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDIO2 check host ready
+ *
+ * @param  dev:   SDIO device pointer
+ *
+ * @return 1 for host ready, 0 for not
+ *
+*******************************************************************************/
+int bflb_sdio2_check_host_ready(struct bflb_device_s *dev)
+{
+    uint32_t reg_base = dev->reg_base;
+    uint32_t regval = 0;
+
+    regval = getreg8(reg_base + SDIO2_SCRATCH_OFFSET);
+
+    if (regval != 0) {
+        return 1;
+
+    } else {
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  SDIO2 send data,this function can be in user app context
+ *
+ * @param  dev:   SDIO device pointer
+ * @param  qos:   qos number for this data buffer to send
+ * @param  buff:  data buffer pointer
+ * @param  len:   data length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_send_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int len)
+{
+    uint32_t reg_base = dev->reg_base;
+    uint16_t rd_bit_map = getreg16(reg_base + SDIO2_RD_BIT_MAP_OFFSET);
+    static uint8_t curr_upld_port = 0; 
+
+    if (rd_bit_map & (1 << curr_upld_port)) {
+        return -1;
+    }
+    arch_memcpy_fast(local_tx_buf[curr_upld_port], buff, len);
+    SDIO2_DRV_DBG("Copy port=%d,index=%d\r\n",curr_upld_port,local_tx_buf[curr_upld_port][0]);
+    putreg8(curr_upld_port, reg_base + SDIO2_READ_INDEX_OFFSET);
+    putreg16(SDIO2_BYTE_PER_BUF, reg_base + SDIO2_RD_LEN_OFFSET + curr_upld_port * 2);
+    putreg32((uint32_t)&local_tx_buf[curr_upld_port][0], reg_base + SDIO2_SQ_READ_BASE_OFFSET);
+    putreg16(1 << curr_upld_port, reg_base + SDIO2_RD_BIT_MAP_OFFSET);
+#if SDU_INT_HOST
+    putreg8(SDIO2_CCR_CS_UpLdRdy, reg_base + SDIO2_CARD_TO_HOST_EVENT_OFFSET);
+#endif     
+    curr_upld_port++;
+    if(curr_upld_port == SDIO2_MAX_PORT_NUM){
+        curr_upld_port = 0;
+    }
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDIO2 receive data,this function can be in user app context
+ *
+ * @param  dev:   SDIO device pointer
+ * @param  qos:   qos number for this data buffer to receive
+ * @param  buff:  data buffer pointer
+ * @param  len:   data length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int bflb_sdio2_recv_data(struct bflb_device_s *dev, int qos, uintptr_t *buff, int *len)
+{
+    static uint16_t curr_dnld_port = 0;
+    uint32_t reg_base = dev->reg_base;
+    uint16_t wr_bit_map = getreg16(reg_base + SDIO2_WR_BIT_MAP_OFFSET);    
+    uint8_t crcerror = 0;
+#if 0
+    uint8_t card_status = 0;
+
+    /* get card status */
+    card_status = getreg8(reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+#endif
+
+    /* get erro */
+    crcerror = getreg8(reg_base + SDIO2_HOST_TRANS_STATUS_OFFSET);
+
+#if 0
+    if (!(card_status & SDIO2_CCR_CIC_DnLdOvr)){
+        SDIO2_DRV_DBG("No data come from host\r\n");
+        return -1;
+    }
+#endif
+    if (crcerror & SDIO2_CCR_HOST_INT_DnLdCRC_err) {
+        SDIO2_DRV_ERR("RX CRC error\r\n");
+    }
+
+    if (!(wr_bit_map & (1 << curr_dnld_port))) {
+        arch_memcpy_fast(buff, local_rx_buf[curr_dnld_port], SDIO2_BYTE_PER_BUF);
+        SDIO2_DRV_DBG("Copy port=%d,index=%d\r\n",curr_dnld_port,buff[0]);
+        *len = SDIO2_BYTE_PER_BUF;
+        /* attach new buffer */
+        putreg8(curr_dnld_port, reg_base + SDIO2_WRITE_INDEX_OFFSET);
+        putreg32((uint32_t)&local_rx_buf[curr_dnld_port][0], reg_base + SDIO2_SQ_WRITE_BASE_OFFSET);
+        putreg16(1 << curr_dnld_port, reg_base + SDIO2_WR_BIT_MAP_OFFSET);
+#if SDU_INT_HOST
+        putreg8((SDIO2_CCR_CS_ReadCISRdy | SDIO2_CCR_CS_DnLdRdy | SDIO2_CCR_CS_IORdy),
+                reg_base + SDIO2_CARD_TO_HOST_EVENT_OFFSET);
+#endif
+        /* go to next */
+        curr_dnld_port++;
+        if (curr_dnld_port == SDIO2_MAX_PORT_NUM) {
+            curr_dnld_port = 0;
+        }
+        return 0;
+    }else{
+        return -1;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  sdio2 irq handler
+ *
+ * @param  irq: sdio3 interrupt type
+ * @param  arg: arg for callback
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_sdio2_isr(int irq, void *arg)
+{
+    struct bflb_device_s *dev = (struct bflb_device_s *)arg;
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+    uint8_t crcerror = 0;
+
+    reg_base = dev->reg_base;
+    regval = getreg8(reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+
+    /* clear interrupt */
+    putreg8(~regval | SDIO2_CCR_CIC_PwrUp, reg_base + SDIO2_CARD_INT_STATUS_OFFSET);
+    /* get erro */
+    crcerror = getreg8(reg_base + SDIO2_HOST_TRANS_STATUS_OFFSET);
+
+    if ((regval & SDIO2_CCR_CIC_UpLdOvr)) {
+        SDIO2_DRV_DBG("TX interrupt come\r\n");
+    }
+
+    if ((regval & SDIO2_CCR_CIC_DnLdOvr) &&
+        !(crcerror & SDIO2_CCR_HOST_INT_DnLdCRC_err)) {
+        SDIO2_DRV_DBG("RX interrupt come\r\n");
+    }
+
+    if (crcerror & SDIO2_CCR_HOST_INT_DnLdCRC_err) {
+        SDIO2_DRV_ERR("RX CRC error\r\n");
+    }
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_aes.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_aes.c
new file mode 100755
index 0000000000..ca2117e324
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_aes.c
@@ -0,0 +1,392 @@
+#include "bflb_sec_aes.h"
+#include "hardware/sec_eng_reg.h"
+
+#define CONFIG_BFLB_AES_USE_BE
+
+#define BFLB_PUT_LE32(p) ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+#define BFLB_PUT_BE32(p) ((p[0] << 24) | (p[1] << 16) | (p[2] << 8) | (p[3]))
+
+volatile uint8_t hw_key_sel = 1;
+
+void bflb_aes_init(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+#ifdef CONFIG_BFLB_AES_USE_BE
+    putreg32(0x1f, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#else
+    putreg32(0x10, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#endif
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_AES_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_AES_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_set_hwkey(uint8_t keysel)
+{
+    hw_key_sel = keysel;
+}
+
+void bflb_aes_set_mode(struct bflb_device_s *dev, uint8_t mode)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_AES_0_BLOCK_MODE_MASK;
+    regval |= (mode << SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT);
+
+    if (mode == AES_MODE_CTR) {
+        regval |= SEC_ENG_SE_AES_0_DEC_KEY_SEL;
+    } else {
+        regval &= ~SEC_ENG_SE_AES_0_DEC_KEY_SEL; /* clear key to set new key */
+    }
+
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_setkey(struct bflb_device_s *dev, const uint8_t *key, uint16_t keybits)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint8_t mode;
+    uint8_t *temp_key = (uint8_t *)key;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
+
+    regval &= ~SEC_ENG_SE_AES_0_MODE_MASK;
+    regval &= ~SEC_ENG_SE_AES_0_HW_KEY_EN;
+    if (key == NULL) {
+        regval |= SEC_ENG_SE_AES_0_HW_KEY_EN;
+    }
+
+    if (keybits == 128) {
+        regval |= (0 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+    } else if (keybits == 192) {
+        regval |= (2 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+    } else if (keybits == 256) {
+        regval |= (1 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+    } else {
+        regval |= (3 << SEC_ENG_SE_AES_0_MODE_SHIFT);
+    }
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+    if (key == NULL) {
+        regval = getreg32(reg_base + SEC_ENG_SE_AES_0_KEY_SEL_OFFSET);
+        regval &= ~SEC_ENG_SE_AES_0_KEY_SEL_MASK;
+        regval |= (hw_key_sel << SEC_ENG_SE_AES_0_KEY_SEL_SHIFT);
+        putreg32(regval, reg_base + SEC_ENG_SE_AES_0_KEY_SEL_OFFSET);
+
+        regval = getreg32(reg_base + SEC_ENG_SE_AES_1_KEY_SEL_OFFSET);
+        regval &= ~SEC_ENG_SE_AES_1_KEY_SEL_MASK;
+        regval |= (hw_key_sel << SEC_ENG_SE_AES_1_KEY_SEL_SHIFT);
+        putreg32(regval, reg_base + SEC_ENG_SE_AES_1_KEY_SEL_OFFSET);
+    } else {
+        putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_0_OFFSET);
+        temp_key += 4;
+        putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_1_OFFSET);
+        temp_key += 4;
+        putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_2_OFFSET);
+        temp_key += 4;
+        putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_3_OFFSET);
+        temp_key += 4;
+
+        if (keybits == 192) {
+            putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_4_OFFSET);
+            temp_key += 4;
+            putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_5_OFFSET);
+            temp_key += 4;
+        } else if ((keybits == 256) || (mode == AES_MODE_XTS)) {
+            putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_4_OFFSET);
+            temp_key += 4;
+            putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_5_OFFSET);
+            temp_key += 4;
+            putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_6_OFFSET);
+            temp_key += 4;
+            putreg32(BFLB_PUT_LE32(temp_key), reg_base + SEC_ENG_SE_AES_0_KEY_7_OFFSET);
+            temp_key += 4;
+        }
+    }
+}
+
+int bflb_aes_encrypt(struct bflb_device_s *dev,
+                     const uint8_t *input,
+                     const uint8_t *iv,
+                     uint8_t *output,
+                     uint32_t len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint64_t start_time;
+    uint8_t mode;
+    uint8_t *temp_iv = (uint8_t *)iv;
+
+    reg_base = dev->reg_base;
+
+    if (len % 16) {
+        return -EINVAL;
+    }
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
+    if (temp_iv) {
+        regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
+    } else {
+        regval |= SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select last iv */
+    }
+    regval &= ~SEC_ENG_SE_AES_0_DEC_EN; /* Set AES encryption */
+    regval &= ~SEC_ENG_SE_AES_0_MSG_LEN_MASK;
+    regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
+    regval |= ((len / 16) << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT);
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+    mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
+
+    if (temp_iv) {
+        if (mode == AES_MODE_XTS) {
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+            temp_iv += 4;
+        } else {
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+            temp_iv += 4;
+        }
+    }
+
+    /* Set input and output address */
+    putreg32((uint32_t)input, reg_base + SEC_ENG_SE_AES_0_MSA_OFFSET);
+    putreg32((uint32_t)output, reg_base + SEC_ENG_SE_AES_0_MDA_OFFSET);
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_AES_0_TRIG_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    return 0;
+}
+
+int bflb_aes_decrypt(struct bflb_device_s *dev,
+                     const uint8_t *input,
+                     const uint8_t *iv,
+                     uint8_t *output,
+                     uint32_t len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint64_t start_time;
+    uint8_t mode;
+    uint8_t *temp_iv = (uint8_t *)iv;
+
+    reg_base = dev->reg_base;
+
+    if (len % 16) {
+        return -EINVAL;
+    }
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
+    if (temp_iv) {
+        regval &= ~SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select new iv */
+    } else {
+        regval |= SEC_ENG_SE_AES_0_IV_SEL; /* Clear aes iv sel to select last iv */
+    }
+    regval |= SEC_ENG_SE_AES_0_DEC_EN; /* Set AES decryption */
+    regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
+    regval &= ~SEC_ENG_SE_AES_0_MSG_LEN_MASK;
+    regval |= ((len / 16) << SEC_ENG_SE_AES_0_MSG_LEN_SHIFT);
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+    mode = (regval & SEC_ENG_SE_AES_0_BLOCK_MODE_MASK) >> SEC_ENG_SE_AES_0_BLOCK_MODE_SHIFT;
+
+    if (temp_iv) {
+        if (mode == AES_MODE_XTS) {
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_BE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+            temp_iv += 4;
+        } else {
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_0_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_1_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_2_OFFSET);
+            temp_iv += 4;
+            putreg32(BFLB_PUT_LE32(temp_iv), reg_base + SEC_ENG_SE_AES_0_IV_3_OFFSET);
+            temp_iv += 4;
+        }
+    }
+
+    /* Set input and output address */
+    putreg32((uint32_t)input, reg_base + SEC_ENG_SE_AES_0_MSA_OFFSET);
+    putreg32((uint32_t)output, reg_base + SEC_ENG_SE_AES_0_MDA_OFFSET);
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_AES_0_TRIG_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    return 0;
+}
+
+void bflb_aes_link_init(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+#ifdef CONFIG_BFLB_AES_USE_BE
+    putreg32(0x1f, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#else
+    putreg32(0x10, reg_base + SEC_ENG_SE_AES_0_ENDIAN_OFFSET);
+#endif
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_AES_0_LINK_MODE;
+    regval |= SEC_ENG_SE_AES_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+void bflb_aes_link_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_AES_0_LINK_MODE;
+    regval &= ~SEC_ENG_SE_AES_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+}
+
+int bflb_aes_link_update(struct bflb_device_s *dev,
+                         uint32_t link_addr,
+                         const uint8_t *input,
+                         uint8_t *output,
+                         uint32_t len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint64_t start_time;
+
+    reg_base = dev->reg_base;
+
+    if ((len % 16) || ((link_addr & 0x03))) {
+        return -EINVAL;
+    }
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_AES_0_TRIG_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+    /* Set link address */
+    putreg32(link_addr, reg_base + SEC_ENG_SE_AES_0_LINK_OFFSET);
+
+    /* Change source buffer address and destination buffer address */
+    *(uint32_t *)(uintptr_t)(link_addr + 4) = (uint32_t)(uintptr_t)input;
+    *(uint32_t *)(uintptr_t)(link_addr + 8) = (uint32_t)(uintptr_t)output;
+
+    /* Set data length */
+    *((uint16_t *)(uintptr_t)link_addr + 1) = len / 16;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_AES_0_TRIG_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+
+    __asm volatile("nop");
+    __asm volatile("nop");
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_AES_0_CTRL_OFFSET) & SEC_ENG_SE_AES_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+
+    return 0;
+}
+
+void bflb_group0_request_aes_access(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+    if (((regval >> 2) & 0x03) == 0x03) {
+        putreg32(0x02, reg_base + SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET);
+
+        regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+        if (((regval >> 2) & 0x03) == 0x01) {
+        }
+    }
+}
+
+void bflb_group0_release_aes_access(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg32(0x06, reg_base + SEC_ENG_SE_AES_0_CTRL_PROT_OFFSET);
+}
+
+void bflb_aes_set_hwkey_source(struct bflb_device_s *dev, uint8_t source)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_AES_0_SBOOT_OFFSET);
+    regval |= (source << 0);
+    putreg32(0x02, reg_base + SEC_ENG_SE_AES_0_SBOOT_OFFSET);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_irq.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_irq.c
new file mode 100755
index 0000000000..99f2d296a4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_irq.c
@@ -0,0 +1,176 @@
+#include "bflb_sec_irq.h"
+#include "hardware/sec_eng_reg.h"
+
+struct bflb_sec_irq_callback {
+    void (*handler)(void *arg);
+    void *arg;
+};
+
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+#define BFLB_SEC_ENG_BASE ((uint32_t)0x40004000)
+#elif defined(BL616) || defined(BL606P) || defined(BL808)
+#define BFLB_SEC_ENG_BASE ((uint32_t)0x20004000)
+#elif defined(BL628)
+#define BFLB_SEC_ENG_BASE ((uint32_t)0x20080000)
+#endif
+
+struct bflb_sec_irq_callback sec_eng_callback[6];
+
+void sec_eng_isr(int irq, void *arg)
+{
+    uint32_t regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+    if (regval & SEC_ENG_SE_AES_0_INT) {
+        regval |= SEC_ENG_SE_AES_0_INT_CLR_1T;
+        putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+        if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].handler) {
+            sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_AES].arg);
+        }
+    }
+
+    regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    if (regval & SEC_ENG_SE_SHA_0_INT) {
+        regval |= SEC_ENG_SE_SHA_0_INT_CLR_1T;
+        putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+        if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].handler) {
+            sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_SHA].arg);
+        }
+    }
+
+    regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+    if (regval & SEC_ENG_SE_PKA_0_INT) {
+        regval |= SEC_ENG_SE_PKA_0_INT_CLR_1T;
+        putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+        if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].handler) {
+            sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_PKA].arg);
+        }
+    }
+
+    regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    if (regval & SEC_ENG_SE_TRNG_0_INT) {
+        regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+        putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+        if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].handler) {
+            sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_TRNG].arg);
+        }
+    }
+
+    regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+    if (regval & SEC_ENG_SE_GMAC_0_INT) {
+        regval |= SEC_ENG_SE_GMAC_0_INT_CLR_1T;
+        putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+        if (sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].handler) {
+            sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].handler(sec_eng_callback[BFLB_SEC_ENG_IRQ_TYPE_GMAC].arg);
+        }
+    }
+}
+
+void bflb_sec_int_mask(uint8_t sec_type, bool mask)
+{
+    uint32_t regval;
+
+    switch (sec_type) {
+        case BFLB_SEC_ENG_IRQ_TYPE_AES:
+            regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+            if (mask) {
+                regval |= SEC_ENG_SE_AES_0_INT_MASK;
+            } else {
+                regval &= ~SEC_ENG_SE_AES_0_INT_MASK;
+            }
+            putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_AES_0_CTRL_OFFSET);
+            break;
+        case BFLB_SEC_ENG_IRQ_TYPE_SHA:
+            regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+            if (mask) {
+                regval |= SEC_ENG_SE_SHA_0_INT_MASK;
+            } else {
+                regval &= ~SEC_ENG_SE_SHA_0_INT_MASK;
+            }
+            putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+            break;
+        case BFLB_SEC_ENG_IRQ_TYPE_PKA:
+            regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+            if (mask) {
+                regval |= SEC_ENG_SE_PKA_0_INT_MASK;
+            } else {
+                regval &= ~SEC_ENG_SE_PKA_0_INT_MASK;
+            }
+            putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_PKA_0_CTRL_0_OFFSET);
+            break;
+        case BFLB_SEC_ENG_IRQ_TYPE_TRNG:
+            regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+            if (mask) {
+                regval |= SEC_ENG_SE_TRNG_0_INT_MASK;
+            } else {
+                regval &= ~SEC_ENG_SE_TRNG_0_INT_MASK;
+            }
+            putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+            break;
+        case BFLB_SEC_ENG_IRQ_TYPE_GMAC:
+            regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+            if (mask) {
+                regval |= SEC_ENG_SE_GMAC_0_INT_MASK;
+            } else {
+                regval &= ~SEC_ENG_SE_GMAC_0_INT_MASK;
+            }
+            putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_GMAC_0_CTRL_0_OFFSET);
+            break;
+        case BFLB_SEC_ENG_IRQ_TYPE_CDET:
+            regval = getreg32(BFLB_SEC_ENG_BASE + SEC_ENG_SE_CDET_0_CTRL_0_OFFSET);
+            if (mask) {
+                regval |= SEC_ENG_SE_CDET_0_INT_MASK;
+            } else {
+                regval &= ~SEC_ENG_SE_CDET_0_INT_MASK;
+            }
+            putreg32(regval, BFLB_SEC_ENG_BASE + SEC_ENG_SE_CDET_0_CTRL_0_OFFSET);
+            break;
+
+        default:
+            break;
+    }
+}
+
+void bflb_sec_irq_attach(uint8_t sec_type, void (*callback)(void *arg), void *arg)
+{
+    sec_eng_callback[sec_type].handler = callback;
+    sec_eng_callback[sec_type].arg = arg;
+#if defined(BL702) || defined(BL602) || defined(BL702L)
+    bflb_irq_attach(25, sec_eng_isr, NULL);
+    bflb_irq_attach(26, sec_eng_isr, NULL);
+    bflb_irq_attach(27, sec_eng_isr, NULL);
+    bflb_irq_attach(28, sec_eng_isr, NULL);
+    bflb_irq_attach(29, sec_eng_isr, NULL);
+    bflb_irq_attach(30, sec_eng_isr, NULL);
+    bflb_irq_enable(25);
+    bflb_irq_enable(26);
+    bflb_irq_enable(27);
+    bflb_irq_enable(28);
+    bflb_irq_enable(29);
+    bflb_irq_enable(30);
+#elif (defined(BL606P) || defined(BL808)) && (defined(CPU_M0) || defined(CPU_LP))
+    bflb_irq_attach(25, sec_eng_isr, NULL);
+    bflb_irq_attach(26, sec_eng_isr, NULL);
+    bflb_irq_attach(27, sec_eng_isr, NULL);
+    bflb_irq_attach(28, sec_eng_isr, NULL);
+    bflb_irq_enable(25);
+    bflb_irq_enable(26);
+    bflb_irq_enable(27);
+    bflb_irq_enable(28);
+#elif defined(BL616) || defined(BL628)
+    bflb_irq_attach(25, sec_eng_isr, NULL);
+    bflb_irq_attach(26, sec_eng_isr, NULL);
+    bflb_irq_attach(27, sec_eng_isr, NULL);
+    bflb_irq_attach(28, sec_eng_isr, NULL);
+    bflb_irq_enable(25);
+    bflb_irq_enable(26);
+    bflb_irq_enable(27);
+    bflb_irq_enable(28);
+#endif
+    bflb_sec_int_mask(sec_type, false);
+}
+
+void bflb_sec_irq_detach(uint8_t sec_type)
+{
+    sec_eng_callback[sec_type].handler = NULL;
+    sec_eng_callback[sec_type].arg = NULL;
+    bflb_sec_int_mask(sec_type, true);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_sha.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_sha.c
new file mode 100755
index 0000000000..8fd8f83b45
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_sha.c
@@ -0,0 +1,880 @@
+#include "bflb_sec_sha.h"
+#include "hardware/sec_eng_reg.h"
+
+#define PUT_UINT32_BE(n, b, i)               \
+    {                                        \
+        (b)[(i)] = (uint8_t)((n) >> 24);     \
+        (b)[(i) + 1] = (uint8_t)((n) >> 16); \
+        (b)[(i) + 2] = (uint8_t)((n) >> 8);  \
+        (b)[(i) + 3] = (uint8_t)((n));       \
+    }
+#define PUT_UINT32(n, b, i)                  \
+    {                                        \
+        (b)[(i) + 3] = (uint8_t)((n) >> 24); \
+        (b)[(i) + 2] = (uint8_t)((n) >> 16); \
+        (b)[(i) + 1] = (uint8_t)((n) >> 8);  \
+        (b)[(i) + 0] = (uint8_t)((n));       \
+    }
+#define PUT_UINT64_BE(n, b, i)               \
+    {                                        \
+        (b)[(i)] = (uint8_t)((n) >> 56);     \
+        (b)[(i) + 1] = (uint8_t)((n) >> 48); \
+        (b)[(i) + 2] = (uint8_t)((n) >> 40); \
+        (b)[(i) + 3] = (uint8_t)((n) >> 32); \
+        (b)[(i) + 4] = (uint8_t)((n) >> 24); \
+        (b)[(i) + 5] = (uint8_t)((n) >> 16); \
+        (b)[(i) + 6] = (uint8_t)((n) >> 8);  \
+        (b)[(i) + 7] = (uint8_t)((n));       \
+    }
+
+void bflb_sha_init(struct bflb_device_s *dev, uint8_t mode)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_SHA_0_MODE_EXT_MASK;
+    regval &= ~SEC_ENG_SE_SHA_0_MODE_MASK;
+    regval |= (mode << SEC_ENG_SE_SHA_0_MODE_SHIFT);
+    putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha1_start(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    arch_memset(ctx, 0, sizeof(struct bflb_sha1_ctx_s));
+    ctx->sha_padding[0] = 0x80;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_SHA_0_EN;
+    regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+    putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha256_start(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx)
+{
+    return bflb_sha1_start(dev, (struct bflb_sha1_ctx_s *)ctx);
+}
+
+void bflb_sha512_start(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    arch_memset(ctx, 0, sizeof(struct bflb_sha512_ctx_s));
+    ctx->sha_padding[0] = 0x80;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_SHA_0_EN;
+    regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+    putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+int bflb_sha1_update(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, const uint8_t *input, uint32_t len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint32_t fill;
+    uint32_t left;
+    uint64_t start_time;
+
+    if (len == 0) {
+        return 0;
+    }
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+    if (ctx->sha_feed) {
+        regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+    } else {
+        regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+    }
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += len;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if (ctx->total[0] < len) {
+        ctx->total[1]++;
+    }
+
+    if (left && len >= fill) {
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+        putreg32((uint32_t)ctx->sha_buf, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+        regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+        regval |= (1 << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        ctx->sha_feed = 1;
+        input += fill;
+        len -= fill;
+        left = 0;
+    }
+
+    fill = len / 64;
+    len = len % 64;
+
+    if (fill > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* SHA need set se_sha_sel to 1 to keep the last sha state */
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+        if (ctx->sha_feed) {
+            regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+        } else {
+            regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+        }
+        /* Fill data */
+        putreg32((uintptr_t)input, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+        regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+        regval |= (fill << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        input += (fill * 64);
+        ctx->sha_feed = 1;
+    }
+
+    if (len > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* Copy left data into temp buffer */
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+    }
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    return 0;
+}
+
+int bflb_sha256_update(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, const uint8_t *input, uint32_t len)
+{
+    return bflb_sha1_update(dev, (struct bflb_sha1_ctx_s *)ctx, input, len);
+}
+
+int bflb_sha512_update(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, const uint8_t *input, uint64_t len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint32_t fill;
+    uint32_t left;
+    uint64_t start_time;
+
+    if (len == 0) {
+        return 0;
+    }
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+    if (ctx->sha_feed) {
+        regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+    } else {
+        regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+    }
+
+    left = ctx->total[0] & 0x7F;
+    fill = 128 - left;
+
+    ctx->total[0] += (uint64_t)len;
+
+    if (ctx->total[0] < (uint64_t)len) {
+        ctx->total[1]++;
+    }
+
+    if (left && len >= fill) {
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+        putreg32((uint32_t)ctx->sha_buf, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+        regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+        regval |= (1 << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        ctx->sha_feed = 1;
+        input += fill;
+        len -= fill;
+        left = 0;
+    }
+
+    fill = len / 128;
+    len = len % 128;
+
+    if (fill > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* SHA need set se_sha_sel to 1 to keep the last sha state */
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+        if (ctx->sha_feed) {
+            regval |= SEC_ENG_SE_SHA_0_HASH_SEL;
+        } else {
+            regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+        }
+        /* Fill data */
+        putreg32((uintptr_t)input, reg_base + SEC_ENG_SE_SHA_0_MSA_OFFSET);
+
+        regval &= ~SEC_ENG_SE_SHA_0_MSG_LEN_MASK;
+        regval |= (fill << SEC_ENG_SE_SHA_0_MSG_LEN_SHIFT);
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        input += (fill * 128);
+        ctx->sha_feed = 1;
+    }
+
+    if (len > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* Copy left data into temp buffer */
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+    }
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    return 0;
+}
+
+void bflb_sha1_finish(struct bflb_device_s *dev, struct bflb_sha1_ctx_s *ctx, uint8_t *output)
+{
+    uint32_t last, padn;
+    uint32_t high, low;
+    uint8_t msgLen[8];
+    uint32_t regval;
+    uint32_t reg_base;
+    uint8_t mode;
+    uint8_t *p = (uint8_t *)output;
+
+    reg_base = dev->reg_base;
+
+    high = (ctx->total[0] >> 29) | (ctx->total[1] << 3);
+    low = (ctx->total[0] << 3);
+
+    PUT_UINT32_BE(high, msgLen, 0);
+    PUT_UINT32_BE(low, msgLen, 4);
+
+    last = ctx->total[0] & 0x3F;
+    padn = (last < 56) ? (56 - last) : (120 - last);
+
+    bflb_sha1_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+    arch_memcpy_fast(ctx->sha_padding, msgLen, 8);
+    bflb_sha1_update(dev, ctx, (uint8_t *)ctx->sha_padding, 8);
+
+    /* Copy SHA value */
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+
+    mode = (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_MODE_MASK) >> SEC_ENG_SE_SHA_0_MODE_SHIFT;
+
+    if ((mode == SHA_MODE_SHA224) || (mode == SHA_MODE_SHA256)) {
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET);
+        *p++ = (regval & 0xff);
+        *p++ = ((regval >> 8) & 0xff);
+        *p++ = ((regval >> 16) & 0xff);
+        *p++ = ((regval >> 24) & 0xff);
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET);
+        *p++ = (regval & 0xff);
+        *p++ = ((regval >> 8) & 0xff);
+        *p++ = ((regval >> 16) & 0xff);
+        *p++ = ((regval >> 24) & 0xff);
+
+        if (mode == SHA_MODE_SHA256) {
+            regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET);
+            *p++ = (regval & 0xff);
+            *p++ = ((regval >> 8) & 0xff);
+            *p++ = ((regval >> 16) & 0xff);
+            *p++ = ((regval >> 24) & 0xff);
+        }
+    }
+
+    /* Disable SHA engine*/
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+    regval &= ~SEC_ENG_SE_SHA_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha256_finish(struct bflb_device_s *dev, struct bflb_sha256_ctx_s *ctx, uint8_t *output)
+{
+    return bflb_sha1_finish(dev, (struct bflb_sha1_ctx_s *)ctx, output);
+}
+
+void bflb_sha512_finish(struct bflb_device_s *dev, struct bflb_sha512_ctx_s *ctx, uint8_t *output)
+{
+    uint64_t last, padn;
+    uint64_t high, low;
+    uint8_t msgLen[16];
+    uint8_t mode;
+    uint32_t regval;
+    uint32_t reg_base;
+    uint8_t *p = (uint8_t *)output;
+
+    reg_base = dev->reg_base;
+
+    high = (ctx->total[0] >> 61) | (ctx->total[1] << 3);
+    low = (ctx->total[0] << 3);
+
+    PUT_UINT64_BE(high, msgLen, 0);
+    PUT_UINT64_BE(low, msgLen, 8);
+
+    last = ctx->total[0] & 0x7F;
+    padn = (last < 112) ? (112 - last) : (240 - last);
+
+    bflb_sha512_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+    arch_memcpy_fast(ctx->sha_padding, msgLen, 16);
+    bflb_sha512_update(dev, ctx, (uint8_t *)ctx->sha_padding, 16);
+
+    /* Copy SHA value */
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_0_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_0_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_1_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_1_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_2_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_2_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_3_OFFSET);
+    *p++ = (regval & 0xff);
+    *p++ = ((regval >> 8) & 0xff);
+    *p++ = ((regval >> 16) & 0xff);
+    *p++ = ((regval >> 24) & 0xff);
+
+    mode = (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_MODE_MASK) >> SEC_ENG_SE_SHA_0_MODE_SHIFT;
+
+    if ((mode == SHA_MODE_SHA512) || (mode == SHA_MODE_SHA384) || (mode == SHA_MODE_SHA512T256)) {
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_3_OFFSET);
+        *p++ = (regval & 0xff);
+        *p++ = ((regval >> 8) & 0xff);
+        *p++ = ((regval >> 16) & 0xff);
+        *p++ = ((regval >> 24) & 0xff);
+
+        if ((mode == SHA_MODE_SHA512) || (mode == SHA_MODE_SHA384)) {
+            regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_4_OFFSET);
+            *p++ = (regval & 0xff);
+            *p++ = ((regval >> 8) & 0xff);
+            *p++ = ((regval >> 16) & 0xff);
+            *p++ = ((regval >> 24) & 0xff);
+            regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_4_OFFSET);
+            *p++ = (regval & 0xff);
+            *p++ = ((regval >> 8) & 0xff);
+            *p++ = ((regval >> 16) & 0xff);
+            *p++ = ((regval >> 24) & 0xff);
+            regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_5_OFFSET);
+            *p++ = (regval & 0xff);
+            *p++ = ((regval >> 8) & 0xff);
+            *p++ = ((regval >> 16) & 0xff);
+            *p++ = ((regval >> 24) & 0xff);
+            regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_5_OFFSET);
+            *p++ = (regval & 0xff);
+            *p++ = ((regval >> 8) & 0xff);
+            *p++ = ((regval >> 16) & 0xff);
+            *p++ = ((regval >> 24) & 0xff);
+
+            if (mode == SHA_MODE_SHA512) {
+                regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_6_OFFSET);
+                *p++ = (regval & 0xff);
+                *p++ = ((regval >> 8) & 0xff);
+                *p++ = ((regval >> 16) & 0xff);
+                *p++ = ((regval >> 24) & 0xff);
+                regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_6_OFFSET);
+                *p++ = (regval & 0xff);
+                *p++ = ((regval >> 8) & 0xff);
+                *p++ = ((regval >> 16) & 0xff);
+                *p++ = ((regval >> 24) & 0xff);
+                regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_H_7_OFFSET);
+                *p++ = (regval & 0xff);
+                *p++ = ((regval >> 8) & 0xff);
+                *p++ = ((regval >> 16) & 0xff);
+                *p++ = ((regval >> 24) & 0xff);
+                regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_HASH_L_7_OFFSET);
+                *p++ = (regval & 0xff);
+                *p++ = ((regval >> 8) & 0xff);
+                *p++ = ((regval >> 16) & 0xff);
+                *p++ = ((regval >> 24) & 0xff);
+            }
+        }
+    }
+
+    /* Disable SHA engine*/
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_SHA_0_HASH_SEL;
+    regval &= ~SEC_ENG_SE_SHA_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha_link_init(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    regval |= SEC_ENG_SE_SHA_0_EN;
+    regval |= SEC_ENG_SE_SHA_0_LINK_MODE;
+    putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha_link_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+    regval &= ~SEC_ENG_SE_SHA_0_EN;
+    regval &= ~SEC_ENG_SE_SHA_0_LINK_MODE;
+    putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+}
+
+void bflb_sha1_link_start(struct bflb_device_s *dev, struct bflb_sha1_link_ctx_s *ctx, struct bflb_sha_link_s *link)
+{
+    arch_memset(ctx, 0, sizeof(struct bflb_sha1_link_ctx_s));
+    ctx->sha_padding[0] = 0x80;
+    ctx->link_addr = (uint32_t)(uintptr_t)link;
+}
+
+void bflb_sha256_link_start(struct bflb_device_s *dev, struct bflb_sha256_link_ctx_s *ctx, struct bflb_sha_link_s *link)
+{
+    return bflb_sha1_link_start(dev, (struct bflb_sha1_link_ctx_s *)ctx, link);
+}
+
+void bflb_sha512_link_start(struct bflb_device_s *dev, struct bflb_sha512_link_ctx_s *ctx, struct bflb_sha_link_s *link)
+{
+    arch_memset(ctx, 0, sizeof(struct bflb_sha512_link_ctx_s));
+    ctx->sha_padding[0] = 0x80;
+    ctx->link_addr = (uint32_t)(uintptr_t)link;
+}
+
+int bflb_sha1_link_update(struct bflb_device_s *dev,
+                          struct bflb_sha1_link_ctx_s *ctx,
+                          const uint8_t *input,
+                          uint32_t len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint32_t fill;
+    uint32_t left;
+    uint64_t start_time;
+
+    if (len == 0) {
+        return 0;
+    }
+
+    reg_base = dev->reg_base;
+
+    /* Set link address */
+    putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+    left = ctx->total[0] & 0x3F;
+    fill = 64 - left;
+
+    ctx->total[0] += len;
+    ctx->total[0] &= 0xFFFFFFFF;
+
+    if (ctx->total[0] < len) {
+        ctx->total[1]++;
+    }
+
+    if (left && len >= fill) {
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+        /* Set data source address */
+        *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
+
+        /* Set data length */
+        *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = 1;
+
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        /* Choose accumulating last hash in the next time */
+        *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+        input += fill;
+        len -= fill;
+        left = 0;
+    }
+
+    fill = len / 64;
+    len = len % 64;
+
+    if (fill > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* Fill data */
+        *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)input;
+        *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = fill;
+
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        input += (fill * 64);
+        /* Choose accumulating last hash in the next time */
+        *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+    }
+
+    if (len > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* Copy left data into temp buffer */
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+    }
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    return 0;
+}
+
+int bflb_sha256_link_update(struct bflb_device_s *dev,
+                            struct bflb_sha256_link_ctx_s *ctx,
+                            const uint8_t *input,
+                            uint32_t len)
+{
+    return bflb_sha1_link_update(dev, (struct bflb_sha1_link_ctx_s *)ctx, input, len);
+}
+
+int bflb_sha512_link_update(struct bflb_device_s *dev,
+                            struct bflb_sha512_link_ctx_s *ctx,
+                            const uint8_t *input,
+                            uint64_t len)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint32_t fill;
+    uint32_t left;
+    uint64_t start_time;
+
+    if (len == 0) {
+        return 0;
+    }
+
+    reg_base = dev->reg_base;
+
+    /* Set link address */
+    putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+    left = ctx->total[0] & 0x7F;
+    fill = 128 - left;
+
+    ctx->total[0] += len;
+
+    if (ctx->total[0] < len) {
+        ctx->total[1]++;
+    }
+
+    if (left && len >= fill) {
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, fill);
+        /* Set data source address */
+        *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)ctx->sha_buf;
+
+        /* Set data length */
+        *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = 1;
+
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        /* Choose accumulating last hash in the next time */
+        *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+        input += fill;
+        len -= fill;
+        left = 0;
+    }
+
+    fill = len / 128;
+    len = len % 128;
+
+    if (fill > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* Fill data */
+        *(uint32_t *)(uintptr_t)(ctx->link_addr + 4) = (uint32_t)(uintptr_t)input;
+        *((uint16_t *)(uintptr_t)ctx->link_addr + 1) = fill;
+
+        regval = getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+        regval |= SEC_ENG_SE_SHA_0_TRIG_1T;
+        putreg32(regval, reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET);
+
+        input += (fill * 128);
+        /* Choose accumulating last hash in the next time */
+        *((uint32_t *)(uintptr_t)ctx->link_addr) |= 0x40;
+    }
+
+    if (len > 0) {
+        start_time = bflb_mtimer_get_time_ms();
+        while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+            if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+                return -ETIMEDOUT;
+            }
+        }
+
+        /* Copy left data into temp buffer */
+        arch_memcpy_fast((void *)((uint8_t *)ctx->sha_buf + left), input, len);
+    }
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_SHA_0_CTRL_OFFSET) & SEC_ENG_SE_SHA_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    return 0;
+}
+
+void bflb_sha1_link_finish(struct bflb_device_s *dev,
+                           struct bflb_sha1_link_ctx_s *ctx,
+                           uint8_t *output)
+{
+    uint32_t last, padn;
+    uint32_t high, low;
+    uint8_t msgLen[8];
+
+    uint32_t reg_base;
+    uint32_t sha_mode = (*(uint32_t *)(uintptr_t)ctx->link_addr) >> 2 & 0x7;
+
+    reg_base = dev->reg_base;
+
+    /* Set link address */
+    putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+    high = (ctx->total[0] >> 29) | (ctx->total[1] << 3);
+    low = (ctx->total[0] << 3);
+
+    PUT_UINT32_BE(high, msgLen, 0);
+    PUT_UINT32_BE(low, msgLen, 4);
+
+    last = ctx->total[0] & 0x3F;
+    padn = (last < 56) ? (56 - last) : (120 - last);
+
+    bflb_sha1_link_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+    bflb_sha1_link_update(dev, ctx, msgLen, 8);
+
+    /* Get result according to SHA mode,result is placed in (link address + offset:8) */
+    switch (sha_mode) {
+        case 0:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 32);
+            break;
+
+        case 1:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 28);
+            break;
+
+        case 2:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 20);
+            break;
+
+        case 3:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 20);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Choose new hash in the next time */
+    *((uint32_t *)(uintptr_t)ctx->link_addr) &= ~0x40;
+}
+
+void bflb_sha256_link_finish(struct bflb_device_s *dev,
+                             struct bflb_sha256_link_ctx_s *ctx,
+                             uint8_t *output)
+{
+    return bflb_sha1_link_finish(dev, (struct bflb_sha1_link_ctx_s *)ctx, output);
+}
+
+void bflb_sha512_link_finish(struct bflb_device_s *dev,
+                             struct bflb_sha512_link_ctx_s *ctx,
+                             uint8_t *output)
+{
+    uint64_t last, padn;
+    uint64_t high, low;
+    uint8_t msgLen[16];
+
+    uint32_t reg_base;
+    uint32_t sha_mode = (*(uint32_t *)(uintptr_t)ctx->link_addr) >> 2 & 0x7;
+
+    reg_base = dev->reg_base;
+
+    /* Set link address */
+    putreg32(ctx->link_addr, reg_base + SEC_ENG_SE_SHA_0_LINK_OFFSET);
+
+    high = (ctx->total[0] >> 61) | (ctx->total[1] << 3);
+    low = (ctx->total[0] << 3);
+
+    PUT_UINT64_BE(high, msgLen, 0);
+    PUT_UINT64_BE(low, msgLen, 8);
+
+    last = ctx->total[0] & 0x7F;
+    padn = (last < 112) ? (112 - last) : (240 - last);
+
+    bflb_sha512_link_update(dev, ctx, (uint8_t *)ctx->sha_padding, padn);
+    bflb_sha512_link_update(dev, ctx, msgLen, 16);
+
+    /* Get result according to SHA mode,result is placed in (link address + offset:8) */
+    switch (sha_mode) {
+        case 4:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 64);
+            break;
+
+        case 5:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 48);
+            break;
+
+        case 6:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 28);
+            break;
+
+        case 7:
+            arch_memcpy_fast(output, (uint8_t *)(uintptr_t)(ctx->link_addr + 8), 32);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Choose new hash in the next time */
+    *((uint32_t *)(uintptr_t)ctx->link_addr) &= ~0x40;
+}
+
+void bflb_group0_request_sha_access(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+    if ((regval & 0x03) == 0x03) {
+        putreg32(0x02, reg_base + SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET);
+
+        regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+        if ((regval & 0x03) == 0x01) {
+        }
+    }
+}
+
+void bflb_group0_release_sha_access(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg32(0x06, reg_base + SEC_ENG_SE_SHA_0_CTRL_PROT_OFFSET);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c
new file mode 100755
index 0000000000..5358485705
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_sec_trng.c
@@ -0,0 +1,172 @@
+#include "bflb_sec_trng.h"
+#include "hardware/sec_eng_reg.h"
+
+#define BFLB_PUT_LE32TOBYTES(p, val) \
+    {                                \
+        p[0] = val & 0xff;           \
+        p[1] = (val >> 8) & 0xff;    \
+        p[2] = (val >> 16) & 0xff;   \
+        p[3] = (val >> 24) & 0xff;   \
+    }
+
+int bflb_trng_read(struct bflb_device_s *dev, uint8_t data[32])
+{
+    uint32_t regval;
+    uint32_t reg_base;
+    uint64_t start_time;
+    uint8_t *p = (uint8_t *)data;
+
+    reg_base = dev->reg_base;
+
+    /* enable trng */
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval |= SEC_ENG_SE_TRNG_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    /* busy will be set to 1 after trigger, the gap is 1T */
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET) & SEC_ENG_SE_TRNG_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval |= SEC_ENG_SE_TRNG_0_TRIG_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    /* busy will be set to 1 after trigger, the gap is 1T */
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+    __ASM volatile("nop");
+
+    start_time = bflb_mtimer_get_time_ms();
+    while (getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET) & SEC_ENG_SE_TRNG_0_BUSY) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+
+    /* copy trng value */
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_0_OFFSET));
+    p += 4;
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_1_OFFSET));
+    p += 4;
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_2_OFFSET));
+    p += 4;
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_3_OFFSET));
+    p += 4;
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_4_OFFSET));
+    p += 4;
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_5_OFFSET));
+    p += 4;
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_6_OFFSET));
+    p += 4;
+    BFLB_PUT_LE32TOBYTES(p, getreg32(reg_base + SEC_ENG_SE_TRNG_0_DOUT_7_OFFSET));
+    p += 4;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval &= ~SEC_ENG_SE_TRNG_0_TRIG_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval |= SEC_ENG_SE_TRNG_0_DOUT_CLR_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval &= ~SEC_ENG_SE_TRNG_0_DOUT_CLR_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    /* disable trng */
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval &= ~SEC_ENG_SE_TRNG_0_EN;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    regval = getreg32(reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+    regval |= SEC_ENG_SE_TRNG_0_INT_CLR_1T;
+    putreg32(regval, reg_base + SEC_ENG_SE_TRNG_0_CTRL_0_OFFSET);
+
+    return 0;
+}
+
+int bflb_trng_readlen(uint8_t *data, uint32_t len)
+{
+    struct bflb_device_s *trng;
+
+    uint8_t tmp_buf[32];
+    uint32_t readlen = 0;
+    uint32_t i = 0, cnt = 0;
+
+    trng = bflb_device_get_by_name("trng");
+
+    while (readlen < len) {
+        if (bflb_trng_read(trng, tmp_buf) != 0) {
+            return -ETIMEDOUT;
+        }
+
+        cnt = len - readlen;
+
+        if (cnt > sizeof(tmp_buf)) {
+            cnt = sizeof(tmp_buf);
+        }
+
+        for (i = 0; i < cnt; i++) {
+            data[readlen + i] = tmp_buf[i];
+        }
+
+        readlen += cnt;
+    }
+
+    return 0;
+}
+
+long random(void)
+{
+    uint32_t data[8];
+    struct bflb_device_s *trng;
+
+    trng = bflb_device_get_by_name("trng");
+    bflb_trng_read(trng, (uint8_t *)data);
+
+    return data[0];
+}
+
+void bflb_group0_request_trng_access(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+    if (((regval >> 4) & 0x03) == 0x03) {
+        putreg32(0x04, reg_base + SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET);
+
+        regval = getreg32(reg_base + SEC_ENG_SE_CTRL_PROT_RD_OFFSET);
+        if (((regval >> 4) & 0x03) == 0x01) {
+        }
+    }
+}
+
+void bflb_group0_release_trng_access(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg32(0x06, reg_base + SEC_ENG_SE_TRNG_0_CTRL_PROT_OFFSET);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c
new file mode 100755
index 0000000000..de9da2599d
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi.c
@@ -0,0 +1,587 @@
+#include "bflb_spi.h"
+#include "bflb_clock.h"
+#include "hardware/spi_reg.h"
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define GLB_SPI_MODE_ADDRESS 0x40000080
+#elif defined(BL606P) || defined(BL808) || defined(BL616) || defined(BL628)
+#define GLB_SPI_MODE_ADDRESS 0x20000510
+#endif
+
+void bflb_spi_init(struct bflb_device_s *dev, const struct bflb_spi_config_s *config)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+    uint32_t div;
+
+    /* GLB select master or slave mode */
+    regval = getreg32(GLB_SPI_MODE_ADDRESS);
+    if (config->role == SPI_ROLE_MASTER) {
+        regval |= 1 << 12;
+    } else {
+        regval &= ~(1 << 12);
+    }
+    putreg32(regval, GLB_SPI_MODE_ADDRESS);
+
+    reg_base = dev->reg_base;
+    /* integer frequency segmentation by rounding */
+    div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_SPI, dev->idx) / 2 * 10 / config->freq + 5) / 10;
+    div = (div) ? (div - 1) : 0;
+    div = (div > 0xff) ? 0xff : div;
+
+    regval = 0;
+    regval |= div << SPI_CR_SPI_PRD_D_PH_0_SHIFT;
+    regval |= div << SPI_CR_SPI_PRD_D_PH_1_SHIFT;
+    regval |= div << SPI_CR_SPI_PRD_S_SHIFT;
+    regval |= div << SPI_CR_SPI_PRD_P_SHIFT;
+    putreg32(regval, reg_base + SPI_PRD_0_OFFSET);
+
+    regval = getreg32(reg_base + SPI_PRD_1_OFFSET);
+    regval &= ~SPI_CR_SPI_PRD_I_MASK;
+    regval |= (div) << SPI_CR_SPI_PRD_I_SHIFT;
+    putreg32(regval, reg_base + SPI_PRD_1_OFFSET);
+
+    /* Disable deglitch and disenable continue function */
+    regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+    regval &= ~SPI_CR_SPI_DEG_EN;
+    regval &= ~SPI_CR_SPI_DEG_CNT_MASK;
+    regval &= ~SPI_CR_SPI_M_CONT_EN;
+    regval &= ~SPI_CR_SPI_RXD_IGNR_EN;
+
+    /* Byte-inverse and Bit-inverse */
+    if (config->byte_order == SPI_BYTE_LSB) {
+        regval &= ~SPI_CR_SPI_BYTE_INV;
+    } else {
+        regval |= SPI_CR_SPI_BYTE_INV;
+    }
+    if (config->bit_order == SPI_BIT_LSB) {
+        regval |= SPI_CR_SPI_BIT_INV;
+    } else {
+        regval &= ~SPI_CR_SPI_BIT_INV;
+    }
+
+    /* clk phase and polarity cfg */
+    switch (config->mode) {
+        case SPI_MODE0:
+            /* CPOL=0 CHPHA=0 */
+            regval &= ~SPI_CR_SPI_SCLK_POL;
+            regval |= SPI_CR_SPI_SCLK_PH;
+            break;
+        case SPI_MODE1:
+            /* CPOL=0 CHPHA=1 */
+            regval &= ~SPI_CR_SPI_SCLK_POL;
+            regval &= ~SPI_CR_SPI_SCLK_PH;
+            break;
+        case SPI_MODE2:
+            /* CPOL=1 CHPHA=0 */
+            regval |= SPI_CR_SPI_SCLK_POL;
+            regval |= SPI_CR_SPI_SCLK_PH;
+            break;
+        case SPI_MODE3:
+            /* CPOL=1 CHPHA=1 */
+            regval |= SPI_CR_SPI_SCLK_POL;
+            regval &= ~SPI_CR_SPI_SCLK_PH;
+            break;
+        default:
+            break;
+    }
+
+    /* data frame size cfg */
+    regval &= ~SPI_CR_SPI_FRAME_SIZE_MASK;
+    regval |= (config->data_width - 1) << SPI_CR_SPI_FRAME_SIZE_SHIFT;
+
+    /* disable SPI */
+    regval &= ~SPI_CR_SPI_S_EN;
+    regval &= ~SPI_CR_SPI_M_EN;
+
+    putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+
+    /* clear fifo and close dma */
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+    regval |= SPI_TX_FIFO_CLR;
+    regval |= SPI_RX_FIFO_CLR;
+    regval &= ~SPI_DMA_TX_EN;
+    regval &= ~SPI_DMA_RX_EN;
+    putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+    /* fifo threshold cfg */
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+    regval &= ~SPI_TX_FIFO_TH_MASK;
+    regval &= ~SPI_RX_FIFO_TH_MASK;
+    regval |= (config->tx_fifo_threshold << SPI_TX_FIFO_TH_SHIFT) & SPI_TX_FIFO_TH_MASK;
+    regval |= (config->rx_fifo_threshold << SPI_RX_FIFO_TH_SHIFT) & SPI_RX_FIFO_TH_MASK;
+    putreg32(regval, reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+
+    /* enable spi */
+    regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+    if (config->role == SPI_ROLE_MASTER) {
+        regval |= SPI_CR_SPI_M_EN;
+        regval &= ~SPI_CR_SPI_S_EN;
+    } else {
+        regval |= SPI_CR_SPI_S_EN;
+        regval &= ~SPI_CR_SPI_M_EN;
+    }
+    putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+}
+
+void bflb_spi_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    /* disable SPI */
+    regval = getreg32(dev->reg_base + SPI_CONFIG_OFFSET);
+    regval &= ~SPI_CR_SPI_S_EN;
+    regval &= ~SPI_CR_SPI_M_EN;
+    putreg32(regval, dev->reg_base + SPI_CONFIG_OFFSET);
+}
+
+void bflb_spi_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= SPI_DMA_TX_EN;
+    } else {
+        regval &= ~SPI_DMA_TX_EN;
+    }
+    putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_spi_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= SPI_DMA_RX_EN;
+    } else {
+        regval &= ~SPI_DMA_RX_EN;
+    }
+    putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+}
+
+/* Read and write a frame of data */
+ATTR_TCM_SECTION uint32_t bflb_spi_poll_send(struct bflb_device_s *dev, uint32_t data)
+{
+    uint32_t reg_base = dev->reg_base;
+    uint32_t regval;
+    uint8_t fifo_cnt;
+
+#if 0
+    /* Wait for tx FIFO to be empty */
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+    do {
+        regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+        fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+    } while (fifo_cnt < SPI_FIFO_BYTE_NUM_MAX);
+#else
+    do {
+        regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+        fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+    } while (fifo_cnt < SPI_FIFO_WORD_NUM_MAX);
+#endif
+
+    /* Wait for SPI to idle */
+    do {
+        regval = getreg32(reg_base + SPI_BUS_BUSY_OFFSET);
+    } while (regval);
+
+    /* clear fifo */
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+    regval |= SPI_TX_FIFO_CLR;
+    regval |= SPI_RX_FIFO_CLR;
+    putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+#endif
+
+    /* wtire data to fifo */
+    putreg32(data, reg_base + SPI_FIFO_WDATA_OFFSET);
+
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+
+    /* get frame size */
+    regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+    uint8_t frame_size = ((regval & SPI_CR_SPI_FRAME_SIZE_MASK) >> SPI_CR_SPI_FRAME_SIZE_SHIFT) + 1;
+    if (frame_size == 3) {
+        frame_size = 4;
+    }
+
+    /* Wait for rx data */
+    do {
+        regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+        fifo_cnt = (regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT;
+    } while (fifo_cnt < frame_size);
+#else
+
+    /* Wait for rx data */
+    do {
+        regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+        fifo_cnt = (regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT;
+    } while (fifo_cnt == 0);
+#endif
+
+    regval = getreg32(reg_base + SPI_FIFO_RDATA_OFFSET);
+
+    return regval;
+}
+
+/* read and write data */
+ATTR_TCM_SECTION int bflb_spi_poll_exchange(struct bflb_device_s *dev, const void *txbuffer, void *rxbuffer, size_t nbytes)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+    uint32_t tx_cnt;
+    uint8_t fifo_cnt, frame_size;
+
+    /* get frame size */
+    regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+    frame_size = ((regval & SPI_CR_SPI_FRAME_SIZE_MASK) >> SPI_CR_SPI_FRAME_SIZE_SHIFT) + 1;
+    if (frame_size == 3) {
+        frame_size = 4;
+    }
+
+    nbytes /= frame_size;
+    tx_cnt = nbytes;
+
+#if 0
+    /* Wait for tx FIFO to be empty */
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+    do {
+        regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+        fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+    } while (fifo_cnt < SPI_FIFO_BYTE_NUM_MAX);
+#else
+    do {
+        regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+        fifo_cnt = (regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT;
+    } while (fifo_cnt < SPI_FIFO_WORD_NUM_MAX);
+#endif
+
+    /* Wait for SPI to idle */
+    do {
+        regval = getreg32(reg_base + SPI_BUS_BUSY_OFFSET);
+    } while (regval);
+
+    /* clear fifo */
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+    regval |= SPI_TX_FIFO_CLR;
+    regval |= SPI_RX_FIFO_CLR;
+    putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+#endif
+
+    /* clear fifo */
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+    regval |= SPI_TX_FIFO_CLR;
+    regval |= SPI_RX_FIFO_CLR;
+    putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+    /* get tx fifo cnt */
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+    fifo_cnt = ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT) / frame_size;
+#else
+    fifo_cnt = ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT);
+#endif
+
+    /* first fill tx fifo */
+    fifo_cnt = fifo_cnt > nbytes ? nbytes : fifo_cnt;
+    tx_cnt -= fifo_cnt;
+    if (txbuffer != NULL) {
+        /* Send valid data */
+        for (; fifo_cnt > 0; fifo_cnt--) {
+            switch (frame_size) {
+                case 1:
+                    regval = *(uint8_t *)txbuffer;
+                    putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+                    txbuffer += 1;
+                    break;
+                case 2:
+                    regval = *(uint16_t *)txbuffer;
+                    putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+                    txbuffer += 2;
+                    break;
+                case 3:
+                case 4:
+                    regval = *(uint32_t *)txbuffer;
+                    putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+                    txbuffer += 4;
+                    break;
+                default:
+                    break;
+            }
+        }
+    } else {
+        /* Send idle Data */
+        for (; fifo_cnt > 0; fifo_cnt--) {
+            putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+        }
+    }
+
+    /* read and write rest of the data */
+    for (; nbytes > 0;) {
+        /* get rx fifo cnt */
+        regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+        fifo_cnt = ((regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT) / frame_size;
+#else
+        fifo_cnt = ((regval & SPI_RX_FIFO_CNT_MASK) >> SPI_RX_FIFO_CNT_SHIFT);
+#endif
+        if (fifo_cnt) {
+            fifo_cnt = fifo_cnt > nbytes ? nbytes : fifo_cnt;
+            nbytes -= fifo_cnt;
+        } else {
+        }
+
+        /* read and write data */
+        for (; fifo_cnt > 0; fifo_cnt--) {
+            regval = getreg32(reg_base + SPI_FIFO_RDATA_OFFSET);
+            switch (frame_size) {
+                case 1:
+                    if (rxbuffer) {
+                        *((uint8_t *)rxbuffer) = (uint8_t)regval;
+                        rxbuffer += 1;
+                    }
+                    if (tx_cnt) {
+                        if (txbuffer) {
+                            regval = *(uint8_t *)txbuffer;
+                            putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+                            txbuffer++;
+                        } else {
+                            putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+                        }
+                        tx_cnt--;
+                    }
+                    break;
+                case 2:
+                    if (rxbuffer) {
+                        *((uint16_t *)rxbuffer) = (uint16_t)regval;
+                        rxbuffer += 2;
+                    }
+                    if (tx_cnt) {
+                        if (txbuffer) {
+                            regval = *(uint16_t *)txbuffer;
+                            putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+                            txbuffer += 2;
+                        } else {
+                            putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+                        }
+                        tx_cnt--;
+                    }
+                    break;
+                case 3:
+                    /* discard the high 8 bits of data when 24bit-frame */
+                case 4:
+                    if (rxbuffer) {
+                        *((uint32_t *)rxbuffer) = (uint32_t)regval;
+                        rxbuffer += 4;
+                    }
+                    if (tx_cnt) {
+                        if (txbuffer) {
+                            regval = *(uint32_t *)txbuffer;
+                            putreg32(regval, reg_base + SPI_FIFO_WDATA_OFFSET);
+                            txbuffer += 4;
+                        } else {
+                            putreg32(0xFFFFFFFF, reg_base + SPI_FIFO_WDATA_OFFSET);
+                        }
+                        tx_cnt--;
+                    }
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+    return 0;
+}
+
+void bflb_spi_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+    if (mask) {
+        regval |= SPI_CR_SPI_TXF_MASK;
+    } else {
+        regval &= ~SPI_CR_SPI_TXF_MASK;
+    }
+    putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+void bflb_spi_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+    if (mask) {
+        regval |= SPI_CR_SPI_RXF_MASK;
+    } else {
+        regval &= ~SPI_CR_SPI_RXF_MASK;
+    }
+    putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+void bflb_spi_tcint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+    if (mask) {
+        regval |= SPI_CR_SPI_END_MASK;
+    } else {
+        regval &= ~SPI_CR_SPI_END_MASK;
+    }
+    putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+void bflb_spi_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+    if (mask) {
+        regval |= SPI_CR_SPI_STO_MASK;
+        regval |= SPI_CR_SPI_TXU_MASK;
+        regval |= SPI_CR_SPI_FER_MASK;
+    } else {
+        regval &= ~SPI_CR_SPI_STO_MASK;
+        regval &= ~SPI_CR_SPI_TXU_MASK;
+        regval &= ~SPI_CR_SPI_FER_MASK;
+    }
+    putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+uint32_t bflb_spi_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t int_status;
+    uint32_t int_mask;
+
+    reg_base = dev->reg_base;
+    int_status = getreg32(reg_base + SPI_INT_STS_OFFSET) & 0x1f;
+    int_mask = getreg32(reg_base + SPI_INT_STS_OFFSET) >> 8 & 0x1f;
+    return (int_status & ~int_mask);
+}
+
+void bflb_spi_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + SPI_INT_STS_OFFSET);
+    regval |= int_clear;
+    putreg32(regval, reg_base + SPI_INT_STS_OFFSET);
+}
+
+bool bflb_spi_isbusy(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    /* check tx fifo */
+    regval = getreg32(reg_base + SPI_FIFO_CONFIG_1_OFFSET);
+#if (SPI_FIFO_WIDTH_VARIABLE_SUPPORT)
+    if ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT < SPI_FIFO_BYTE_NUM_MAX) {
+        return true;
+    }
+#else
+    if ((regval & SPI_TX_FIFO_CNT_MASK) >> SPI_TX_FIFO_CNT_SHIFT < SPI_FIFO_WORD_NUM_MAX) {
+        return true;
+    }
+#endif
+
+    /* check busy bit */
+    regval = getreg32(reg_base + SPI_BUS_BUSY_OFFSET);
+    if (regval) {
+        return true;
+    }
+
+    return false;
+}
+
+int bflb_spi_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case SPI_CMD_SET_DATA_WIDTH:
+            /* set data width, arg use @ref SPI_DATA_WIDTH, must clear fifo */
+            regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+            regval |= SPI_TX_FIFO_CLR;
+            regval |= SPI_RX_FIFO_CLR;
+            putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+
+            regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+            regval &= ~SPI_CR_SPI_FRAME_SIZE_MASK;
+            regval |= (arg - 1) << SPI_CR_SPI_FRAME_SIZE_SHIFT;
+            putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+            break;
+
+        case SPI_CMD_GET_DATA_WIDTH:
+            /* set data width, arg use @ref SPI_DATA_WIDTH */
+            regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+            regval &= SPI_CR_SPI_FRAME_SIZE_MASK;
+            regval >>= SPI_CR_SPI_FRAME_SIZE_SHIFT;
+            *(uint32_t *)arg = regval;
+            break;
+
+        case SPI_CMD_CLEAR_TX_FIFO:
+            /* clear tx fifo */
+            regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+            regval |= SPI_TX_FIFO_CLR;
+            putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case SPI_CMD_CLEAR_RX_FIFO:
+            /* clear rx fifo */
+            regval = getreg32(reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+            regval |= SPI_RX_FIFO_CLR;
+            putreg32(regval, reg_base + SPI_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case SPI_CMD_SET_CS_INTERVAL:
+            /* set CS continue mode, arg use true or false */
+            regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+            if (arg) {
+                regval |= SPI_CR_SPI_M_CONT_EN;
+            } else {
+                regval &= ~SPI_CR_SPI_M_CONT_EN;
+            }
+            putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+            break;
+
+        case SPI_CMD_RX_IGNORE:
+            /* set rx ignore, start: arg[20:16], stop: arg[4:0] */
+            regval = getreg32(reg_base + SPI_CONFIG_OFFSET);
+            if (arg) {
+                regval |= SPI_CR_SPI_RXD_IGNR_EN;
+                putreg32(arg, reg_base + SPI_RXD_IGNR_OFFSET);
+            } else {
+                regval &= ~SPI_CR_SPI_RXD_IGNR_EN;
+            }
+            putreg32(regval, reg_base + SPI_CONFIG_OFFSET);
+            break;
+
+        default:
+            ret = -EPERM;
+            break;
+    }
+
+    return ret;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi_psram.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi_psram.c
new file mode 100755
index 0000000000..566663aec3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_spi_psram.c
@@ -0,0 +1,774 @@
+/**
+  ******************************************************************************
+  * @file    bflb_spi_psram.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bflb_spi_psram.h"
+#include "bflb_l1c.h"
+
+/** @addtogroup  BFLB_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PSRAM
+ *  @{
+ */
+
+/** @defgroup  PSRAM_Private_Macros
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Macros */
+
+/** @defgroup  PSRAM_Private_Types
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Types */
+
+/** @defgroup  PSRAM_Private_Variables
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Variables */
+
+/** @defgroup  PSRAM_Global_Variables
+ *  @{
+ */
+
+/*@} end of group PSRAM_Global_Variables */
+
+/** @defgroup  PSRAM_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Fun_Declaration */
+
+/** @defgroup  PSRAM_Private_Functions
+ *  @{
+ */
+
+/*@} end of group PSRAM_Private_Functions */
+
+/** @defgroup  PSRAM_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Init serial psram control interface
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  cmds_cfg: Serial Serial Flash controller configuration pointer
+ * @param  sf_ctrl_psram_cfg: Serial psram controller configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg,
+                                 struct sf_ctrl_psram_cfg *sf_ctrl_psram_cfg)
+{
+    bflb_sf_ctrl_psram_init(sf_ctrl_psram_cfg);
+    bflb_sf_ctrl_cmds_set(cmds_cfg, 0);
+
+#if defined(BL702L)
+    bflb_sf_ctrl_burst_toggle_set(psram_cfg->burst_toggle_en, psram_cfg->ctrl_mode);
+#endif
+    bflb_psram_setdrivestrength(psram_cfg);
+    bflb_psram_setburstwrap(psram_cfg);
+}
+
+/****************************************************************************/ /**
+ * @brief  Read psram register
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  reg_value: Register value pointer to store data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
+{
+    uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+        psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+    }
+
+    psram_cmd.cmd_buf[0] = (psram_cfg->read_reg_cmd) << 24;
+    psram_cmd.rw_flag = SF_CTRL_READ;
+    psram_cmd.addr_size = 3;
+    psram_cmd.dummy_clks = psram_cfg->read_reg_dmy_clk;
+    psram_cmd.nb_data = 1;
+
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return;
+        }
+    }
+
+    arch_memcpy(reg_value, psram_ctrl_buf, 1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Write psram register
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  reg_value: Register value pointer storing data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
+{
+    uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    arch_memcpy(psram_ctrl_buf, reg_value, 1);
+
+    if (psram_cfg->ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+        psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+    }
+
+    psram_cmd.cmd_buf[0] = (psram_cfg->write_reg_cmd) << 24;
+    psram_cmd.rw_flag = SF_CTRL_WRITE;
+    psram_cmd.addr_size = 3;
+    psram_cmd.nb_data = 1;
+
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set psram driver strength
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg)
+{
+    uint32_t stat = 0;
+
+    bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+    if ((stat & 0x3) == psram_cfg->drive_strength) {
+        return 0;
+    }
+
+    stat &= (~0x3);
+    stat |= psram_cfg->drive_strength;
+
+    bflb_psram_writereg(psram_cfg, (uint8_t *)&stat);
+    /* Wait for write done */
+
+    bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+    if ((stat & 0x3) == psram_cfg->drive_strength) {
+        return 0;
+    }
+
+    return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set psram burst wrap size
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg)
+{
+    uint32_t stat = 0;
+
+    bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+    if (((stat >> 5) & 0x3) == psram_cfg->burst_length) {
+        return 0;
+    }
+
+    stat &= (~(0x3 << 5));
+    stat |= (psram_cfg->burst_length << 5);
+
+    bflb_psram_writereg(psram_cfg, (uint8_t *)&stat);
+    /* Wait for write done */
+
+    bflb_psram_readreg(psram_cfg, (uint8_t *)&stat);
+
+    if (((stat >> 5) & 0x3) == psram_cfg->burst_length) {
+        return 0;
+    }
+
+    return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get psram ID
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  data: Data pointer to store read data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data)
+{
+    uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    psram_cmd.cmd_buf[0] = (psram_cfg->read_id_cmd) << 24;
+    psram_cmd.rw_flag = SF_CTRL_READ;
+    psram_cmd.addr_size = 3;
+    psram_cmd.dummy_clks = psram_cfg->read_id_dmy_clk;
+    psram_cmd.nb_data = 8;
+
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return;
+        }
+    }
+
+    arch_memcpy(data, psram_ctrl_buf, 8);
+}
+
+/****************************************************************************/ /**
+ * @brief  Psram enter quad mode
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg)
+{
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+    uint32_t timeout = 0;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    psram_cmd.cmd_buf[0] = (psram_cfg->enter_quad_mode_cmd) << 24;
+    psram_cmd.rw_flag = SF_CTRL_READ;
+
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return -2;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Psram exit quad mode
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg)
+{
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+    uint32_t timeout = 0;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+    psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+    psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+
+    psram_cmd.cmd_buf[0] = (psram_cfg->exit_quad_mode_cmd) << 24;
+    psram_cmd.rw_flag = SF_CTRL_READ;
+
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return -2;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Psram toggle burst length
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  ctrl_mode: Psram ctrl mode type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
+{
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+    uint32_t timeout = 0;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    if (ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+        psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+    }
+
+    psram_cmd.cmd_buf[0] = (psram_cfg->burst_toggle_cmd) << 24;
+    psram_cmd.rw_flag = SF_CTRL_READ;
+
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return -2;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Psram software reset
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  ctrl_mode: Psram ctrl mode type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
+{
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+    uint32_t timeout = 0;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    if (ctrl_mode == PSRAM_QPI_CTRL_MODE) {
+        psram_cmd.cmd_mode = SF_CTRL_CMD_4_LINES;
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+    }
+
+    /* Reset enable */
+    psram_cmd.cmd_buf[0] = (psram_cfg->reset_enable_cmd) << 24;
+    /* rw_flag don't care */
+    psram_cmd.rw_flag = SF_CTRL_READ;
+    /* Wait for write done */
+
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return -2;
+        }
+    }
+
+    /* Reset */
+    psram_cmd.cmd_buf[0] = (psram_cfg->reset_cmd) << 24;
+    /* rw_flag don't care */
+    psram_cmd.rw_flag = SF_CTRL_READ;
+    bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return -2;
+        }
+    }
+
+    arch_delay_us(50);
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Psram set IDbus config
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  io_mode: Psram ctrl mode type
+ * @param  addr: Address to read/write
+ * @param  len: Data length to read/write
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg,
+                                                 uint8_t io_mode, uint32_t addr, uint32_t len)
+{
+    uint8_t cmd, dummy_clks;
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+    uint8_t cmd_valid = 1;
+
+    bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB);
+
+    /* read mode cache set */
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == io_mode) {
+        cmd = psram_cfg->f_read_cmd;
+        dummy_clks = psram_cfg->f_read_dmy_clk;
+    } else if (SF_CTRL_QIO_MODE == io_mode) {
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = psram_cfg->f_read_quad_cmd;
+        dummy_clks = psram_cfg->f_read_quad_dmy_clk;
+    } else {
+        return -1;
+    }
+
+    /* prepare command */
+    psram_cmd.rw_flag = SF_CTRL_READ;
+    psram_cmd.addr_size = 3;
+    psram_cmd.cmd_buf[0] = (cmd << 24) | addr;
+    psram_cmd.dummy_clks = dummy_clks;
+    psram_cmd.nb_data = len;
+    bflb_sf_ctrl_psram_read_set(&psram_cmd, cmd_valid);
+
+    /* write mode cache set */
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == io_mode) {
+        cmd = psram_cfg->write_cmd;
+    } else if (SF_CTRL_QIO_MODE == io_mode) {
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = psram_cfg->quad_write_cmd;
+    } else {
+        return -1;
+    }
+
+    dummy_clks = 0;
+
+    /* prepare command */
+    psram_cmd.rw_flag = SF_CTRL_WRITE;
+    psram_cmd.addr_size = 3;
+    psram_cmd.cmd_buf[0] = (cmd << 24) | addr;
+    psram_cmd.dummy_clks = dummy_clks;
+    psram_cmd.nb_data = len;
+    bflb_sf_ctrl_psram_write_set(&psram_cmd, cmd_valid);
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set cache write to psram with cache
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  io_mode: Psram controller interface mode
+ * @param  wt_en: Psram cache write through enable
+ * @param  wb_en: Psram cache write back enable
+ * @param  wa_en: Psram cache write allocate enable
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
+                                                uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
+{
+    int stat = -1;
+
+    /* Cache now only support 32 bytes read */
+    stat = bflb_psram_set_idbus_cfg(psram_cfg, io_mode, 0, 32);
+
+    if (0 != stat) {
+        return stat;
+    }
+
+    bflb_l1c_cache_write_set(wt_en, wb_en, wa_en);
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Write psram one region
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  io_mode: Write mode: SPI mode or QPI mode
+ * @param  addr: Start address to be write
+ * @param  data: Data pointer to be write
+ * @param  len: Data length to be write
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_write(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
+                                      uint32_t addr, uint8_t *data, uint32_t len)
+{
+    uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+    uint32_t i = 0, cur_len = 0;
+    uint32_t burst_len = 512;
+    uint8_t cmd;
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == io_mode) {
+        cmd = psram_cfg->write_cmd;
+    } else if (SF_CTRL_QIO_MODE == io_mode) {
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = psram_cfg->quad_write_cmd;
+    } else {
+        return -1;
+    }
+
+    /* Prepare command */
+    psram_cmd.rw_flag = SF_CTRL_WRITE;
+    psram_cmd.addr_size = 3;
+
+    if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) {
+        burst_len = 16;
+    } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) {
+        burst_len = 32;
+    } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) {
+        burst_len = 64;
+    } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) {
+        burst_len = 512;
+    }
+
+    for (i = 0; i < len;) {
+        /* Get current programmed length within page size */
+        cur_len = burst_len - addr % burst_len;
+
+        if (cur_len > len - i) {
+            cur_len = len - i;
+        }
+
+        /* Prepare command */
+        arch_memcpy_fast(psram_ctrl_buf, data, cur_len);
+        psram_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+        psram_cmd.nb_data = cur_len;
+
+        bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+        /* Adjust address and programmed length */
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+
+        /* Wait for write done */
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from psram
+ *
+ * @param  psram_cfg: Serial psram parameter configuration pointer
+ * @param  io_mode: IoMode: psram controller interface mode
+ * @param  addr: Psram read start address
+ * @param  data: Data pointer to store data read from psram
+ * @param  len: Data length to read
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_psram_read(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
+                                     uint32_t addr, uint8_t *data, uint32_t len)
+{
+    uint8_t *const psram_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BASE;
+    uint32_t cur_len, i;
+    uint32_t burst_len = 512;
+    uint32_t timeout = 0;
+    uint8_t cmd, dummy_clks;
+    struct sf_ctrl_cmd_cfg_type psram_cmd;
+
+    if (((uint32_t)&psram_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&psram_cmd, 0, sizeof(psram_cmd) / 4);
+    } else {
+        arch_memset(&psram_cmd, 0, sizeof(psram_cmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == io_mode) {
+        cmd = psram_cfg->f_read_cmd;
+        dummy_clks = psram_cfg->f_read_dmy_clk;
+    } else if (SF_CTRL_QIO_MODE == io_mode) {
+        psram_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        psram_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = psram_cfg->f_read_quad_cmd;
+        dummy_clks = psram_cfg->f_read_quad_dmy_clk;
+    } else {
+        return -1;
+    }
+
+    /* Prepare command */
+    psram_cmd.rw_flag = SF_CTRL_READ;
+    psram_cmd.addr_size = 3;
+    psram_cmd.dummy_clks = dummy_clks;
+
+    if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_16_BYTES) {
+        burst_len = 16;
+    } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_32_BYTES) {
+        burst_len = 32;
+    } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_64_BYTES) {
+        burst_len = 64;
+    } else if (psram_cfg->burst_length == PSRAM_BURST_LENGTH_512_BYTES) {
+        burst_len = 512;
+    }
+
+    /* Read data */
+    for (i = 0; i < len;) {
+        /* Prepare command */
+        psram_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+        cur_len = burst_len - addr % burst_len;
+
+        if (cur_len > len - i) {
+            cur_len = len - i;
+        }
+
+        if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
+            cur_len = NOR_FLASH_CTRL_BUF_SIZE;
+            psram_cmd.nb_data = cur_len;
+        } else {
+            /* Make sf_ctrl word read */
+            psram_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
+        }
+
+        bflb_sf_ctrl_sendcmd(&psram_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+
+        arch_memcpy_fast(data, psram_ctrl_buf, cur_len);
+
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+    }
+
+    return 0;
+}
+
+/*@} end of group PSRAM_Public_Functions */
+
+/*@} end of group PSRAM */
+
+/*@} end of group BFLB_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_timer.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_timer.c
new file mode 100755
index 0000000000..7e93a146b3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_timer.c
@@ -0,0 +1,292 @@
+#include "bflb_timer.h"
+#include "bflb_gpio.h"
+#include "hardware/timer_reg.h"
+
+void bflb_timer_init(struct bflb_device_s *dev, const struct bflb_timer_config_s *config)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    /* Disable timer */
+    regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+    regval &= ~(1 << (dev->idx + 1));
+    putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+
+    /* Timer interrupr clear */
+    bflb_timer_compint_clear(dev, TIMER_COMP_ID_0);
+    bflb_timer_compint_clear(dev, TIMER_COMP_ID_1);
+    bflb_timer_compint_clear(dev, TIMER_COMP_ID_2);
+
+    /* Configure clock source */
+    regval = getreg32(reg_base + TIMER_TCCR_OFFSET);
+    if (dev->idx == 0) {
+        regval &= ~TIMER_CS_0_MASK;
+        regval |= (config->clock_source << TIMER_CS_0_SHIFT);
+    } else {
+        regval &= ~TIMER_CS_1_MASK;
+        regval |= (config->clock_source << TIMER_CS_1_SHIFT);
+    }
+    putreg32(regval, reg_base + TIMER_TCCR_OFFSET);
+
+    /* Configure clock div */
+    regval = getreg32(reg_base + TIMER_TCDR_OFFSET);
+    regval &= ~(0xff << (TIMER_TCDR0_SHIFT + 8 * dev->idx));
+    regval |= (config->clock_div << (TIMER_TCDR0_SHIFT + 8 * dev->idx));
+    putreg32(regval, reg_base + TIMER_TCDR_OFFSET);
+
+    /* Configure counter mode */
+    regval = getreg32(reg_base + TIMER_TCMR_OFFSET);
+    if (config->counter_mode == TIMER_COUNTER_MODE_PROLOAD) {
+        regval &= ~(1 << (1 + dev->idx));
+    } else {
+        regval |= (1 << (1 + dev->idx));
+    }
+    putreg32(regval, reg_base + TIMER_TCMR_OFFSET);
+
+    /* Configure preload trigger source */
+    regval = getreg32(reg_base + TIMER_TPLCR0_OFFSET + 4 * dev->idx);
+    regval &= ~TIMER_TPLCR0_MASK;
+    if (config->trigger_comp_id != TIMER_COMP_NONE) {
+        regval |= ((config->trigger_comp_id + 1) << TIMER_TPLCR0_SHIFT);
+    }
+    putreg32(regval, reg_base + TIMER_TPLCR0_OFFSET + 4 * dev->idx);
+
+    if (config->counter_mode == TIMER_COUNTER_MODE_PROLOAD) {
+        bflb_timer_set_preloadvalue(dev, config->preload_val);
+    }
+
+    if (config->trigger_comp_id < TIMER_COMP_ID_1) {
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, false);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, true);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, true);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, 0xffffffff);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff);
+    } else if (config->trigger_comp_id < TIMER_COMP_ID_2) {
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, false);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, false);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, true);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, config->comp1_val - 2);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff);
+    } else if (config->trigger_comp_id < TIMER_COMP_NONE) {
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, false);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, false);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, false);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, config->comp0_val - 2);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, config->comp1_val - 2);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, config->comp2_val - 2);
+    } else {
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_0, true);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_1, true);
+        bflb_timer_compint_mask(dev, TIMER_COMP_ID_2, true);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_0, 0xffffffff);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_1, 0xffffffff);
+        bflb_timer_set_compvalue(dev, TIMER_COMP_ID_2, 0xffffffff);
+    }
+}
+
+void bflb_timer_deinit(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+    regval &= ~(1 << (dev->idx + 1));
+    putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+}
+
+void bflb_timer_start(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+    regval |= (1 << (dev->idx + 1));
+    putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+}
+
+void bflb_timer_stop(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    regval = getreg32(reg_base + TIMER_TCER_OFFSET);
+    regval &= ~(1 << (dev->idx + 1));
+    putreg32(regval, reg_base + TIMER_TCER_OFFSET);
+}
+
+void bflb_timer_set_preloadvalue(struct bflb_device_s *dev, uint32_t val)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg32(val, reg_base + TIMER_TPLVR0_OFFSET + 4 * dev->idx);
+}
+
+void bflb_timer_set_compvalue(struct bflb_device_s *dev, uint8_t cmp_no, uint32_t val)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg32(val, reg_base + TIMER_TMR0_0_OFFSET + 0x0c * dev->idx + 4 * cmp_no);
+}
+
+uint32_t bflb_timer_get_compvalue(struct bflb_device_s *dev, uint8_t cmp_no)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    return getreg32(reg_base + TIMER_TMR0_0_OFFSET + 0x0c * dev->idx + 4 * cmp_no);
+}
+
+uint32_t bflb_timer_get_countervalue(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    return getreg32(reg_base + TIMER_TCR0_OFFSET + 4 * dev->idx);
+}
+
+void bflb_timer_compint_mask(struct bflb_device_s *dev, uint8_t cmp_no, bool mask)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + TIMER_TIER0_OFFSET + 4 * dev->idx);
+    if (mask) {
+        regval &= ~(1 << cmp_no);
+    } else {
+        regval |= (1 << cmp_no);
+    }
+    putreg32(regval, reg_base + TIMER_TIER0_OFFSET + 4 * dev->idx);
+}
+
+bool bflb_timer_get_compint_status(struct bflb_device_s *dev, uint8_t cmp_no)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + TIMER_TSR0_OFFSET + 4 * dev->idx);
+
+    if (regval & (1 << cmp_no)) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+void bflb_timer_compint_clear(struct bflb_device_s *dev, uint8_t cmp_no)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx);
+    regval |= (1 << cmp_no);
+    putreg32(regval, reg_base + TIMER_TICR0_OFFSET + 4 * dev->idx);
+}
+
+#if !defined(BL702) && !defined(BL602)
+void bflb_timer_capture_init(struct bflb_device_s *dev, const struct bflb_timer_capture_config_s *config)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+#if defined(BL702L)
+    regval = getreg32(0x20000000 + 0xc);
+    regval &= ~(0x3 << 14);
+    switch (config->pin & 0x03) {
+        case 0:
+            regval &= ~(1 << 10);
+            regval |= (0 << 14);
+            break;
+        case 1:
+            regval &= ~(1 << 11);
+            regval |= (1 << 14);
+            break;
+        case 2:
+            regval &= ~(1 << 12);
+            regval |= (2 << 14);
+            break;
+        case 3:
+            regval &= ~(1 << 13);
+            regval |= (3 << 14);
+            break;
+
+        default:
+            break;
+    }
+    putreg32(regval, 0x20000000 + 0xc);
+    struct bflb_device_s *gpio = bflb_device_get_by_name("gpio");
+    bflb_gpio_init(gpio, config->pin, (0 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1);
+#else
+    regval = getreg32(0x20000000 + 0x258);
+    regval &= ~(3 << 12);
+    switch (config->pin & 0x03) {
+        case 0:
+            regval &= ~(1 << 8);
+            regval |= (0 << 12);
+            break;
+        case 1:
+            regval &= ~(1 << 9);
+            regval |= (1 << 12);
+            break;
+        case 2:
+            regval &= ~(1 << 10);
+            regval |= (2 << 12);
+            break;
+        case 3:
+            regval &= ~(1 << 11);
+            regval |= (3 << 12);
+            break;
+
+        default:
+            break;
+    }
+    putreg32(regval, 0x20000000 + 0x258);
+    struct bflb_device_s *gpio = bflb_device_get_by_name("gpio");
+    bflb_gpio_init(gpio, config->pin, (31 << GPIO_FUNC_SHIFT) | GPIO_ALTERNATE | GPIO_FLOAT | GPIO_SMT_EN | GPIO_DRV_1);
+#endif
+
+    regval = getreg32(reg_base + TIMER_GPIO_OFFSET);
+    /* polarity: 1->neg, 0->pos */
+    if (config->polarity == TIMER_CAPTURE_POLARITY_NEGATIVE) {
+        regval |= (1 << (5 + dev->idx));
+    } else {
+        regval &= ~(1 << (5 + dev->idx));
+    }
+    regval |= TIMER0_GPIO_EN;
+    putreg32(regval, reg_base + TIMER_GPIO_OFFSET);
+}
+
+uint32_t bflb_timer_capture_get_pulsewidth(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t lat1 = 0;
+    uint32_t lat2 = 0;
+    reg_base = dev->reg_base;
+
+    do {
+        lat1 = getreg32(reg_base + TIMER_GPIO_LAT1_OFFSET);
+        lat2 = getreg32(reg_base + TIMER_GPIO_LAT2_OFFSET);
+    } while (!(getreg32(reg_base + TIMER_GPIO_OFFSET) & TIMER_GPIO_LAT_OK) || (lat1 >= lat2));
+
+    return (lat2 - lat1);
+}
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c
new file mode 100755
index 0000000000..acd93c1e08
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_uart.c
@@ -0,0 +1,719 @@
+#include "bflb_uart.h"
+#include "bflb_clock.h"
+#include "hardware/uart_reg.h"
+
+void bflb_uart_init(struct bflb_device_s *dev, const struct bflb_uart_config_s *config)
+{
+    uint32_t div = 0;
+    uint32_t tx_cfg;
+    uint32_t rx_cfg;
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    /* Cal the baud rate divisor */
+    div = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_UART, dev->idx) * 10 / config->baudrate + 5) / 10;
+
+    tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+    rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+    tx_cfg &= ~UART_CR_UTX_EN;
+    rx_cfg &= ~UART_CR_URX_EN;
+    putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+    putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+
+    putreg32(((div - 1) << 0x10) | ((div - 1) & 0xFFFF), reg_base + UART_BIT_PRD_OFFSET);
+
+    /* configure parity type */
+
+    tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+    rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+    switch (config->parity) {
+        case UART_PARITY_NONE:
+            tx_cfg &= ~UART_CR_UTX_PRT_EN;
+            rx_cfg &= ~UART_CR_URX_PRT_EN;
+            break;
+        case UART_PARITY_ODD:
+            tx_cfg |= UART_CR_UTX_PRT_EN;
+            tx_cfg |= UART_CR_UTX_PRT_SEL;
+            rx_cfg |= UART_CR_URX_PRT_EN;
+            rx_cfg |= UART_CR_URX_PRT_SEL;
+            break;
+        case UART_PARITY_EVEN:
+            tx_cfg |= UART_CR_UTX_PRT_EN;
+            tx_cfg &= ~UART_CR_UTX_PRT_SEL;
+            rx_cfg |= UART_CR_URX_PRT_EN;
+            rx_cfg &= ~UART_CR_URX_PRT_SEL;
+            break;
+        default:
+            break;
+    }
+
+    /* Configure data bits */
+    tx_cfg &= ~UART_CR_UTX_BIT_CNT_D_MASK;
+    tx_cfg |= (config->data_bits + 4) << UART_CR_UTX_BIT_CNT_D_SHIFT;
+    rx_cfg &= ~UART_CR_URX_BIT_CNT_D_MASK;
+    rx_cfg |= (config->data_bits + 4) << UART_CR_URX_BIT_CNT_D_SHIFT;
+
+    /* Configure tx stop bits */
+    tx_cfg &= ~UART_CR_UTX_BIT_CNT_P_MASK;
+    tx_cfg |= config->stop_bits << UART_CR_UTX_BIT_CNT_P_SHIFT;
+
+    /* Configure tx cts flow control function */
+    if (config->flow_ctrl & UART_FLOWCTRL_CTS) {
+        tx_cfg |= UART_CR_UTX_CTS_EN;
+    } else {
+        tx_cfg &= ~UART_CR_UTX_CTS_EN;
+    }
+
+    rx_cfg &= ~UART_CR_URX_DEG_EN;
+
+    /* Write back */
+    putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+    putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+#if defined(BL602)
+    regval = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+    regval &= ~UART_CR_URX_RTS_SW_MODE;
+    putreg32(regval, reg_base + UART_URX_CONFIG_OFFSET);
+
+#else
+    regval = getreg32(reg_base + UART_SW_MODE_OFFSET);
+    regval &= ~UART_CR_URX_RTS_SW_MODE;
+    putreg32(regval, reg_base + UART_SW_MODE_OFFSET);
+#endif
+    regval = getreg32(reg_base + UART_DATA_CONFIG_OFFSET);
+    regval &= ~UART_CR_UART_BIT_INV;
+    putreg32(regval, reg_base + UART_DATA_CONFIG_OFFSET);
+
+    /* Enable tx free run mode */
+    regval = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+    regval |= UART_CR_UTX_FRM_EN;
+    putreg32(regval, reg_base + UART_UTX_CONFIG_OFFSET);
+
+    /* Configure FIFO thresholds */
+    regval = getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET);
+    regval &= ~UART_TX_FIFO_TH_MASK;
+    regval &= ~UART_RX_FIFO_TH_MASK;
+    regval |= (config->tx_fifo_threshold << UART_TX_FIFO_TH_SHIFT) & UART_TX_FIFO_TH_MASK;
+    regval |= (config->rx_fifo_threshold << UART_RX_FIFO_TH_SHIFT) & UART_RX_FIFO_TH_MASK;
+    putreg32(regval, reg_base + UART_FIFO_CONFIG_1_OFFSET);
+
+    /* Clear FIFO */
+    regval = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+    regval |= UART_TX_FIFO_CLR;
+    regval |= UART_RX_FIFO_CLR;
+    regval &= ~UART_DMA_TX_EN;
+    regval &= ~UART_DMA_RX_EN;
+    putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+
+    putreg32(0xFFFFFFFF, reg_base + UART_INT_MASK_OFFSET);
+
+    /* Enable UART tx rx unit */
+    tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+    rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+    tx_cfg |= UART_CR_UTX_EN;
+    rx_cfg |= UART_CR_URX_EN;
+    putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+    putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_deinit(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t tx_cfg;
+    uint32_t rx_cfg;
+
+    reg_base = dev->reg_base;
+    tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+    rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+    tx_cfg &= ~UART_CR_UTX_EN;
+    rx_cfg &= ~UART_CR_URX_EN;
+    putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+    putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_enable(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t tx_cfg;
+    uint32_t rx_cfg;
+
+    reg_base = dev->reg_base;
+    tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+    rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+    tx_cfg |= UART_CR_UTX_EN;
+    rx_cfg |= UART_CR_URX_EN;
+    putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+    putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_disable(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t tx_cfg;
+    uint32_t rx_cfg;
+
+    reg_base = dev->reg_base;
+    tx_cfg = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+    rx_cfg = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+    tx_cfg &= ~UART_CR_UTX_EN;
+    rx_cfg &= ~UART_CR_URX_EN;
+    putreg32(tx_cfg, reg_base + UART_UTX_CONFIG_OFFSET);
+    putreg32(rx_cfg, reg_base + UART_URX_CONFIG_OFFSET);
+}
+
+void bflb_uart_link_txdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= UART_DMA_TX_EN;
+    } else {
+        regval &= ~UART_DMA_TX_EN;
+    }
+    putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+}
+
+void bflb_uart_link_rxdma(struct bflb_device_s *dev, bool enable)
+{
+    uint32_t reg_base;
+    uint32_t regval;
+
+    reg_base = dev->reg_base;
+    regval = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+    if (enable) {
+        regval |= UART_DMA_RX_EN;
+    } else {
+        regval &= ~UART_DMA_RX_EN;
+    }
+    putreg32(regval, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+}
+
+ATTR_TCM_SECTION int bflb_uart_putchar(struct bflb_device_s *dev, int ch)
+{
+    uint64_t start_time;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    start_time = bflb_mtimer_get_time_ms();
+    while ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == 0) {
+        if ((bflb_mtimer_get_time_ms() - start_time) > 100) {
+            return -ETIMEDOUT;
+        }
+    }
+    putreg8(ch, reg_base + UART_FIFO_WDATA_OFFSET);
+    return 0;
+}
+
+ATTR_TCM_SECTION int bflb_uart_getchar(struct bflb_device_s *dev)
+{
+    int ch = -1;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0) {
+        ch = getreg8(reg_base + UART_FIFO_RDATA_OFFSET);
+    }
+
+    return ch;
+}
+
+ATTR_TCM_SECTION int bflb_uart_put(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+    int ret;
+    for (uint32_t i = 0; i < len; i++) {
+        ret = bflb_uart_putchar(dev, data[i]);
+        if (ret < 0) {
+            return ret;
+        }
+    }
+    return 0;
+}
+
+ATTR_TCM_SECTION int bflb_uart_get(struct bflb_device_s *dev, uint8_t *data, uint32_t len)
+{
+    int ch = -1;
+    uint32_t count = 0;
+
+    while (count < len) {
+        if ((ch = bflb_uart_getchar(dev)) < 0) {
+            break;
+        }
+        data[count] = ch;
+        count++;
+    }
+    return count;
+}
+
+bool bflb_uart_txready(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) != 0) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+bool bflb_uart_txempty(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    if ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) == (UART_TX_FIFO_CNT_MASK >> 1) + 1) {
+        return true;
+    } else {
+        return false;
+    }
+}
+
+bool bflb_uart_rxavailable(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    return ((getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) != 0);
+}
+
+void bflb_uart_txint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t int_mask;
+
+    reg_base = dev->reg_base;
+    int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+    if (mask) {
+        int_mask |= UART_CR_UTX_FIFO_MASK;
+    } else {
+        int_mask &= ~UART_CR_UTX_FIFO_MASK;
+    }
+    putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+}
+
+void bflb_uart_rxint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t int_mask;
+
+    reg_base = dev->reg_base;
+    int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+    if (mask) {
+        int_mask |= UART_CR_URX_FIFO_MASK;
+        int_mask |= UART_CR_URX_RTO_MASK;
+    } else {
+        int_mask &= ~UART_CR_URX_FIFO_MASK;
+        int_mask &= ~UART_CR_URX_RTO_MASK;
+    }
+    putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+}
+
+void bflb_uart_errint_mask(struct bflb_device_s *dev, bool mask)
+{
+    uint32_t reg_base;
+    uint32_t int_mask;
+
+    reg_base = dev->reg_base;
+    int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+    if (mask) {
+        int_mask |= UART_CR_URX_PCE_MASK;
+        int_mask |= UART_CR_UTX_FER_MASK;
+        int_mask |= UART_CR_URX_FER_MASK;
+#if !defined(BL602)
+        int_mask |= UART_CR_URX_LSE_MASK;
+#endif
+    } else {
+        int_mask &= ~UART_CR_URX_PCE_MASK;
+        int_mask &= ~UART_CR_UTX_FER_MASK;
+        int_mask &= ~UART_CR_URX_FER_MASK;
+#if !defined(BL602)
+        int_mask &= ~UART_CR_URX_LSE_MASK;
+#endif
+    }
+    putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+}
+
+uint32_t bflb_uart_get_intstatus(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+    uint32_t int_status;
+    uint32_t int_mask;
+
+    reg_base = dev->reg_base;
+    int_status = getreg32(reg_base + UART_INT_STS_OFFSET);
+    int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+    return (int_status & ~int_mask);
+}
+
+void bflb_uart_int_clear(struct bflb_device_s *dev, uint32_t int_clear)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+    putreg32(int_clear, reg_base + UART_INT_CLEAR_OFFSET);
+}
+
+int bflb_uart_feature_control(struct bflb_device_s *dev, int cmd, size_t arg)
+{
+    int ret = 0;
+    uint32_t reg_base;
+    uint32_t tmp;
+    uint32_t tx_tmp;
+    uint32_t rx_tmp;
+    uint32_t int_mask;
+
+    reg_base = dev->reg_base;
+
+    switch (cmd) {
+        case UART_CMD_SET_BAUD_RATE:
+            /* Cal the baud rate divisor */
+            tmp = (bflb_clk_get_peripheral_clock(BFLB_DEVICE_TYPE_UART, dev->idx) * 10 / arg + 5) / 10;
+
+            putreg32(((tmp - 1) << 0x10) | ((tmp - 1) & 0xFFFF), reg_base + UART_BIT_PRD_OFFSET);
+            break;
+
+        case UART_CMD_SET_DATA_BITS:
+            /* Set data bits */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+            rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+            tx_tmp &= ~UART_CR_UTX_BIT_CNT_D_MASK;
+            tx_tmp |= (arg + 4) << UART_CR_UTX_BIT_CNT_D_SHIFT;
+
+            rx_tmp &= ~UART_CR_URX_BIT_CNT_D_MASK;
+            rx_tmp |= (arg + 4) << UART_CR_URX_BIT_CNT_D_SHIFT;
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            break;
+
+        case UART_CMD_SET_STOP_BITS:
+            /* Set stop bits */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+            tx_tmp &= ~UART_CR_UTX_BIT_CNT_P_MASK;
+            tx_tmp |= arg << UART_CR_UTX_BIT_CNT_P_SHIFT;
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            break;
+
+        case UART_CMD_SET_PARITY_BITS:
+            /* Set parity mode */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+            rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+            if (arg == UART_PARITY_NONE) {
+                tx_tmp &= ~UART_CR_UTX_PRT_EN;
+                rx_tmp &= ~UART_CR_URX_PRT_EN;
+            } else if (arg == UART_PARITY_ODD) {
+                tx_tmp |= UART_CR_UTX_PRT_EN;
+                tx_tmp |= UART_CR_UTX_PRT_SEL;
+                rx_tmp |= UART_CR_URX_PRT_EN;
+                rx_tmp |= UART_CR_URX_PRT_SEL;
+            } else if (arg == UART_PARITY_EVEN) {
+                tx_tmp |= UART_CR_UTX_PRT_EN;
+                tx_tmp &= ~UART_CR_UTX_PRT_SEL;
+                rx_tmp |= UART_CR_URX_PRT_EN;
+                rx_tmp &= ~UART_CR_URX_PRT_SEL;
+            }
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            break;
+
+        case UART_CMD_CLR_TX_FIFO:
+            /* Clear tx fifo */
+            tmp = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+            tmp |= UART_TX_FIFO_CLR;
+            putreg32(tmp, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case UART_CMD_CLR_RX_FIFO:
+            /* Clear rx fifo */
+            tmp = getreg32(reg_base + UART_FIFO_CONFIG_0_OFFSET);
+            tmp |= UART_RX_FIFO_CLR;
+            putreg32(tmp, reg_base + UART_FIFO_CONFIG_0_OFFSET);
+            break;
+
+        case UART_CMD_SET_RTO_VALUE:
+            /* Set rx time-out value */
+            putreg32(arg, reg_base + UART_URX_RTO_TIMER_OFFSET);
+            break;
+
+        case UART_CMD_SET_RTS_VALUE:
+#if defined(BL602)
+#else
+            /* Set rx rts output software control value */
+            tmp = getreg32(reg_base + UART_SW_MODE_OFFSET);
+            tmp &= ~UART_CR_URX_RTS_SW_VAL;
+            if (arg) {
+                tmp |= UART_CR_URX_RTS_SW_VAL;
+            }
+            putreg32(tmp, reg_base + UART_SW_MODE_OFFSET);
+#endif
+            break;
+
+        case UART_CMD_GET_TX_FIFO_CNT:
+            /* Get tx fifo count */
+            return (getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_TX_FIFO_CNT_MASK) >> UART_TX_FIFO_CNT_SHIFT;
+
+        case UART_CMD_GET_RX_FIFO_CNT:
+            /* Get rx fifo count */
+            return (getreg32(reg_base + UART_FIFO_CONFIG_1_OFFSET) & UART_RX_FIFO_CNT_MASK) >> UART_RX_FIFO_CNT_SHIFT;
+
+        case UART_CMD_SET_AUTO_BAUD:
+            /* Set auto baudrate detection  */
+            tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+            rx_tmp = getreg32(reg_base + UART_INT_MASK_OFFSET);
+            tmp &= ~UART_CR_URX_ABR_EN;
+            if (arg == UART_AUTO_BAUD_0X55) {
+                tmp |= UART_CR_URX_ABR_EN;
+#if !defined(BL602) && !defined(BL702)
+                rx_tmp &= ~UART_CR_URX_AD5_MASK;
+#endif
+            } else {
+                tmp |= UART_CR_URX_ABR_EN;
+#if !defined(BL602) && !defined(BL702)
+                rx_tmp &= ~UART_CR_URX_ADS_MASK;
+#endif
+            }
+
+            putreg32(tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            putreg32(rx_tmp, reg_base + UART_INT_MASK_OFFSET);
+            break;
+
+        case UART_CMD_GET_AUTO_BAUD:
+            /* Get auto baudrate detection count value */
+            tmp = getreg32(reg_base + UART_STS_URX_ABR_PRD_OFFSET);
+            if (arg == UART_AUTO_BAUD_START) {
+                return (tmp & UART_STS_URX_ABR_PRD_START_MASK);
+            } else {
+                return ((tmp & UART_STS_URX_ABR_PRD_0X55_MASK) >> UART_STS_URX_ABR_PRD_0X55_SHIFT);
+            }
+#if !defined(BL602)
+        case UART_CMD_SET_BREAK_VALUE:
+            /* Set lin mode break value */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+            tx_tmp &= ~UART_CR_UTX_BIT_CNT_B_MASK;
+            tx_tmp |= arg << UART_CR_UTX_BIT_CNT_B_SHIFT;
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            break;
+
+        case UART_CMD_SET_TX_LIN_VALUE:
+            /* Set tx lin mode */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+            tx_tmp &= ~UART_CR_UTX_LIN_EN;
+            if (arg) {
+                tx_tmp |= UART_CR_UTX_LIN_EN;
+            }
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            break;
+
+        case UART_CMD_SET_RX_LIN_VALUE:
+            /* Set rx lin mode */
+            rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+            rx_tmp &= ~UART_CR_URX_LIN_EN;
+            if (arg) {
+                rx_tmp |= UART_CR_URX_LIN_EN;
+            }
+
+            putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            break;
+#endif
+        case UART_CMD_SET_TX_RX_EN:
+            /* Set tx and rx enable */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+            rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+            tx_tmp &= ~UART_CR_UTX_EN;
+            rx_tmp &= ~UART_CR_URX_EN;
+            if (arg) {
+                tx_tmp |= UART_CR_UTX_EN;
+                rx_tmp |= UART_CR_URX_EN;
+            }
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            break;
+#if !defined(BL602) && !defined(BL702)
+        case UART_CMD_SET_TX_RS485_EN:
+            /* Set tx rs485 transceiver enable */
+            tx_tmp = getreg32(reg_base + UART_UTX_RS485_CFG_OFFSET);
+            tx_tmp &= ~UART_CR_UTX_RS485_EN;
+
+            if (arg) {
+                tx_tmp |= UART_CR_UTX_RS485_EN;
+            }
+
+            putreg32(tx_tmp, reg_base + UART_UTX_RS485_CFG_OFFSET);
+            break;
+
+        case UART_CMD_SET_TX_RS485_POLARITY:
+            /* Set tx rs485 de pin polarity */
+            tx_tmp = getreg32(reg_base + UART_UTX_RS485_CFG_OFFSET);
+            tx_tmp &= ~UART_CR_UTX_RS485_POL;
+
+            if (arg) {
+                tx_tmp |= UART_CR_UTX_RS485_POL;
+            }
+
+            putreg32(tx_tmp, reg_base + UART_UTX_RS485_CFG_OFFSET);
+            break;
+
+        case UART_CMD_SET_ABR_ALLOWABLE_ERROR:
+            /* Set auto baudrate detection mode pulse-width tolerance value for codeword 0x55 */
+            rx_tmp = getreg32(reg_base + UART_URX_ABR_PW_TOL_OFFSET);
+            rx_tmp &= ~UART_CR_URX_ABR_PW_TOL_MASK;
+            rx_tmp |= arg << UART_CR_URX_ABR_PW_TOL_SHIFT;
+
+            putreg32(rx_tmp, reg_base + UART_URX_ABR_PW_TOL_OFFSET);
+            break;
+#endif
+        case UART_CMD_SET_SW_RTS_CONTROL:
+#if defined(BL602)
+            if (arg) {
+                rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+                rx_tmp |= UART_CR_URX_RTS_SW_MODE;
+                putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            } else {
+                rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+                rx_tmp &= ~UART_CR_URX_RTS_SW_MODE;
+                putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            }
+#else
+            if (arg) {
+                rx_tmp = getreg32(reg_base + UART_SW_MODE_OFFSET);
+                rx_tmp |= UART_CR_URX_RTS_SW_MODE;
+                putreg32(rx_tmp, reg_base + UART_SW_MODE_OFFSET);
+
+            } else {
+                rx_tmp = getreg32(reg_base + UART_SW_MODE_OFFSET);
+                rx_tmp &= ~UART_CR_URX_RTS_SW_MODE;
+                putreg32(rx_tmp, reg_base + UART_SW_MODE_OFFSET);
+            }
+#endif
+            break;
+#if !defined(BL702L)
+        case UART_CMD_IR_CONFIG: {
+            struct bflb_uart_ir_config_s *ir_config = (struct bflb_uart_ir_config_s *)arg;
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+            if (ir_config->tx_en) {
+                tx_tmp |= UART_CR_UTX_IR_EN;
+            } else {
+                tx_tmp &= ~UART_CR_UTX_IR_EN;
+            }
+            if (ir_config->tx_inverse) {
+                tx_tmp |= UART_CR_UTX_IR_INV;
+            } else {
+                tx_tmp &= ~UART_CR_UTX_IR_INV;
+            }
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+
+            rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+            if (ir_config->rx_en) {
+                rx_tmp |= UART_CR_URX_IR_EN;
+            } else {
+                rx_tmp &= ~UART_CR_URX_IR_EN;
+            }
+            if (ir_config->rx_inverse) {
+                rx_tmp |= UART_CR_URX_IR_INV;
+            } else {
+                rx_tmp &= ~UART_CR_URX_IR_INV;
+            }
+            putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            /* Configure tx ir pulse start and stop position */
+            putreg32((ir_config->tx_pluse_stop << 16) | ir_config->tx_pluse_start, reg_base + UART_UTX_IR_POSITION_OFFSET);
+            /* Configure rx ir pulse start position */
+            putreg32(ir_config->rx_pluse_start, reg_base + UART_URX_IR_POSITION_OFFSET);
+        } break;
+#endif
+        case UART_CMD_SET_TX_FREERUN:
+            /* Set tx freerun */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+            if (arg) {
+                tx_tmp |= UART_CR_UTX_FRM_EN;
+            } else {
+                tx_tmp &= ~UART_CR_UTX_FRM_EN;
+            }
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            break;
+        case UART_CMD_SET_TX_END_INTERRUPT:
+            /* Set tx end interrupt */
+            int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+            if (arg) {
+                int_mask &= ~UART_CR_UTX_END_MASK;
+            } else {
+                int_mask |= UART_CR_UTX_END_MASK;
+            }
+            putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+            break;
+        case UART_CMD_SET_RX_END_INTERRUPT:
+            /* Set rx end interrupt */
+            int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+            if (arg) {
+                int_mask &= ~UART_CR_URX_END_MASK;
+            } else {
+                int_mask |= UART_CR_URX_END_MASK;
+            }
+            putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+            break;
+        case UART_CMD_SET_TX_TRANSFER_LEN:
+            /* Set tx transfer length */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+            tx_tmp |= ((arg - 1) << UART_CR_UTX_LEN_SHIFT);
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            break;
+        case UART_CMD_SET_RX_TRANSFER_LEN:
+            /* Set rx transfer length */
+            rx_tmp = getreg32(reg_base + UART_URX_CONFIG_OFFSET);
+
+            rx_tmp |= ((arg - 1) << UART_CR_URX_LEN_SHIFT);
+
+            putreg32(rx_tmp, reg_base + UART_URX_CONFIG_OFFSET);
+            break;
+        case UART_CMD_SET_TX_EN:
+            /* Set tx enable */
+            tx_tmp = getreg32(reg_base + UART_UTX_CONFIG_OFFSET);
+
+            if (arg) {
+                tx_tmp |= UART_CR_UTX_EN;
+            } else {
+                tx_tmp &= ~UART_CR_UTX_EN;
+            }
+
+            putreg32(tx_tmp, reg_base + UART_UTX_CONFIG_OFFSET);
+            break;
+#if !defined(BL602) && !defined(BL702)
+        case UART_CMD_SET_BCR_END_INTERRUPT:
+            /* Set bcr value */
+            int_mask = getreg32(reg_base + UART_INT_MASK_OFFSET);
+            int_mask &= ~UART_CR_URX_BCR_MASK;
+            putreg32(int_mask, reg_base + UART_INT_MASK_OFFSET);
+
+            rx_tmp = getreg32(reg_base + UART_URX_BCR_INT_CFG_OFFSET);
+            rx_tmp &= ~UART_CR_URX_BCR_VALUE_MASK;
+            rx_tmp |= (arg << UART_CR_URX_BCR_VALUE_SHIFT);
+            putreg32(rx_tmp, reg_base + UART_URX_BCR_INT_CFG_OFFSET);
+            break;
+        case UART_CMD_GET_BCR_COUNT:
+            /* Get bcr value */
+            rx_tmp = getreg32(reg_base + UART_URX_BCR_INT_CFG_OFFSET);
+            return ((rx_tmp & UART_STS_URX_BCR_COUNT_MASK) >> UART_STS_URX_BCR_COUNT_SHIFT);
+            break;
+#endif
+        default:
+            ret = -EPERM;
+            break;
+    }
+    return ret;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c
new file mode 100755
index 0000000000..88d90c9d95
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v1.c
@@ -0,0 +1,584 @@
+#include "bflb_core.h"
+#include "bflb_gpio.h"
+#include "usbd_core.h"
+#include "hardware/usb_v1_reg.h"
+
+#define BL702_USB_BASE ((uint32_t)0x4000D800)
+#define BL702_GLB_BASE ((uint32_t)0x40000000)
+
+#define GLB_USB_XCVR_OFFSET        (0x228) /* usb_xcvr */
+#define GLB_USB_XCVR_CONFIG_OFFSET (0x22C) /* usb_xcvr_config */
+
+/* 0x228 : usb_xcvr */
+#define GLB_USB_LDO_VFB_SHIFT   (0U)
+#define GLB_USB_LDO_VFB_MASK    (0x7 << GLB_USB_LDO_VFB_SHIFT)
+#define GLB_PU_USB_LDO          (1 << 3U)
+#define GLB_USB_ROUT_NMOS_SHIFT (4U)
+#define GLB_USB_ROUT_NMOS_MASK  (0x7 << GLB_USB_ROUT_NMOS_SHIFT)
+#define GLB_USB_ROUT_PMOS_SHIFT (8U)
+#define GLB_USB_ROUT_PMOS_MASK  (0x7 << GLB_USB_ROUT_PMOS_SHIFT)
+#define GLB_USB_OEB_SEL         (1 << 12U)
+#define GLB_USB_OEB_REG         (1 << 13U)
+#define GLB_USB_OEB             (1 << 14U)
+#define GLB_USB_DATA_CONVERT    (1 << 16U)
+#define GLB_USB_ENUM            (1 << 20U)
+#define GLB_USB_SPD             (1 << 21U)
+#define GLB_USB_SUS             (1 << 22U)
+#define GLB_PU_USB              (1 << 23U)
+#define GLB_USB_BD              (1 << 24U)
+#define GLB_USB_VIM             (1 << 25U)
+#define GLB_USB_VIP             (1 << 26U)
+#define GLB_USB_RCV             (1 << 27U)
+
+/* 0x22C : usb_xcvr_config */
+#define GLB_USB_V_HYS_M_SHIFT         (0U)
+#define GLB_USB_V_HYS_M_MASK          (0x3 << GLB_USB_V_HYS_M_SHIFT)
+#define GLB_USB_V_HYS_P_SHIFT         (2U)
+#define GLB_USB_V_HYS_P_MASK          (0x3 << GLB_USB_V_HYS_P_SHIFT)
+#define GLB_USB_BD_VTH_SHIFT          (4U)
+#define GLB_USB_BD_VTH_MASK           (0x7 << GLB_USB_BD_VTH_SHIFT)
+#define GLB_REG_USB_USE_XCVR          (1 << 7U)
+#define GLB_USB_STR_DRV_SHIFT         (8U)
+#define GLB_USB_STR_DRV_MASK          (0x7 << GLB_USB_STR_DRV_SHIFT)
+#define GLB_REG_USB_USE_CTRL          (1 << 11U)
+#define GLB_USB_RES_PULLUP_TUNE_SHIFT (12U)
+#define GLB_USB_RES_PULLUP_TUNE_MASK  (0x7 << GLB_USB_RES_PULLUP_TUNE_SHIFT)
+#define GLB_USB_SLEWRATE_M_FALL_SHIFT (16U)
+#define GLB_USB_SLEWRATE_M_FALL_MASK  (0x7 << GLB_USB_SLEWRATE_M_FALL_SHIFT)
+#define GLB_USB_SLEWRATE_M_RISE_SHIFT (20U)
+#define GLB_USB_SLEWRATE_M_RISE_MASK  (0x7 << GLB_USB_SLEWRATE_M_RISE_SHIFT)
+#define GLB_USB_SLEWRATE_P_FALL_SHIFT (24U)
+#define GLB_USB_SLEWRATE_P_FALL_MASK  (0x7 << GLB_USB_SLEWRATE_P_FALL_SHIFT)
+#define GLB_USB_SLEWRATE_P_RISE_SHIFT (28U)
+#define GLB_USB_SLEWRATE_P_RISE_MASK  (0x7 << GLB_USB_SLEWRATE_P_RISE_SHIFT)
+
+#define USB_NUM_BIDIR_ENDPOINTS 9
+
+/* Endpoint state */
+struct bl_ep_state {
+    uint16_t ep_mps;    /* Endpoint max packet size */
+    uint8_t ep_type;    /* Endpoint type */
+    uint8_t ep_stalled; /* Endpoint stall flag */
+    uint8_t ep_enable;  /* Endpoint enable */
+    uint8_t *xfer_buf;
+    uint32_t xfer_len;
+    uint32_t actual_xfer_len;
+};
+
+struct bl_udc {
+    struct usb_setup_packet setup;
+    struct bl_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS];  /*!< IN endpoint parameters             */
+    struct bl_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters            */
+} g_bl_udc;
+
+void USBD_IRQHandler(int irq, void *arg);
+
+static void bflb_usb_mem2fifo(uint8_t ep_idx, uint8_t *data, uint32_t length)
+{
+    uint32_t fifo_addr = BL702_USB_BASE + USB_EP0_TX_FIFO_WDATA_OFFSET + ep_idx * 0x10;
+
+    uint8_t *p = (uint8_t *)fifo_addr;
+    uint8_t *q = data;
+
+    while (length--) {
+        *p = *q++;
+    }
+}
+
+static void bflb_usb_fifo2mem(uint8_t ep_idx, uint8_t *data, uint32_t length)
+{
+    uint32_t fifo_addr = BL702_USB_BASE + USB_EP0_RX_FIFO_RDATA_OFFSET + ep_idx * 0x10;
+
+    uint8_t *p = (uint8_t *)fifo_addr;
+    uint8_t *q = data;
+
+    while (length--) {
+        *q++ = *p;
+    }
+}
+
+static void bflb_usb_xcvr_config(void)
+{
+    uint32_t regval;
+
+    regval = getreg32(BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+    regval |= GLB_PU_USB;
+    putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+
+    regval = getreg32(BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+    regval &= ~GLB_USB_SUS;
+    regval |= GLB_USB_SPD; /* 0 for 1.1 ls,1 for 1.1 fs */
+    regval &= ~GLB_USB_DATA_CONVERT;
+    regval &= ~GLB_USB_OEB_SEL;
+    regval &= ~GLB_USB_ROUT_PMOS_MASK;
+    regval &= ~GLB_USB_ROUT_NMOS_MASK;
+    regval |= (3 << GLB_USB_ROUT_PMOS_SHIFT);
+    regval |= (3 << GLB_USB_ROUT_NMOS_SHIFT);
+    putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+
+    regval = 0;
+    regval |= (2 << GLB_USB_V_HYS_M_SHIFT);
+    regval |= (2 << GLB_USB_V_HYS_P_SHIFT);
+    regval |= (7 << GLB_USB_BD_VTH_SHIFT);
+    regval |= GLB_REG_USB_USE_XCVR;
+    regval |= GLB_REG_USB_USE_CTRL;
+    regval |= (0 << GLB_USB_STR_DRV_SHIFT);
+    regval |= (5 << GLB_USB_RES_PULLUP_TUNE_SHIFT);
+    regval |= (2 << GLB_USB_SLEWRATE_M_FALL_SHIFT);
+    regval |= (2 << GLB_USB_SLEWRATE_M_RISE_SHIFT);
+    regval |= (2 << GLB_USB_SLEWRATE_P_FALL_SHIFT);
+    regval |= (2 << GLB_USB_SLEWRATE_P_RISE_SHIFT);
+    putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_CONFIG_OFFSET);
+
+    regval = getreg32(BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+    regval |= GLB_USB_ENUM;
+    putreg32(regval, BL702_GLB_BASE + GLB_USB_XCVR_OFFSET);
+}
+
+static void bflb_usb_ep0_size(uint8_t ep_mps)
+{
+    uint32_t regval;
+
+    regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+    regval &= ~USB_CR_USB_EP0_SW_SIZE_MASK;
+    regval |= (ep_mps << USB_CR_USB_EP0_SW_SIZE_SHIFT);
+    putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+}
+
+static void bflb_usb_ep_config(uint8_t ep_idx, uint8_t ep_type, uint8_t dir, uint16_t ep_mps)
+{
+    uint32_t regval;
+
+    regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+    regval &= ~USB_CR_EP1_SIZE_MASK;
+    regval &= ~USB_CR_EP1_TYPE_MASK;
+    regval &= ~USB_CR_EP1_DIR_MASK;
+    regval |= (ep_mps << USB_CR_EP1_SIZE_SHIFT);
+    regval |= (dir << USB_CR_EP1_DIR_SHIFT);
+    regval |= (ep_type << USB_CR_EP1_TYPE_SHIFT);
+    putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+}
+
+static void bflb_usb_ep_set_nak(uint8_t ep_idx)
+{
+    uint32_t regval;
+
+    if (ep_idx == 0) {
+        regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+        regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+        regval |= USB_CR_USB_EP0_SW_NACK_IN;
+        putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+    } else {
+        regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+        regval |= USB_CR_EP1_NACK;
+        regval &= ~USB_CR_EP1_STALL;
+        putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+    }
+}
+
+static void bflb_usb_ep_set_ready(uint8_t ep_idx)
+{
+    uint32_t regval;
+
+    if (ep_idx == 0) {
+        regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+        regval |= USB_CR_USB_EP0_SW_RDY;
+        regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+        regval |= USB_CR_USB_EP0_SW_NACK_IN;
+        regval &= ~USB_CR_USB_EP0_SW_STALL;
+        putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+    } else {
+        regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+        regval |= USB_CR_EP1_RDY;
+        regval |= USB_CR_EP1_NACK;
+        regval &= ~USB_CR_EP1_STALL;
+        putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+    }
+}
+
+static uint16_t bflb_usb_get_rxcount(uint8_t ep_idx)
+{
+    return (getreg32(BL702_USB_BASE + USB_EP0_FIFO_STATUS_OFFSET + 0x10 * ep_idx) & USB_EP0_RX_FIFO_CNT_MASK) >> USB_EP0_RX_FIFO_CNT_SHIFT;
+}
+
+// static uint16_t bflb_usb_get_txcount(uint8_t ep_idx)
+// {
+//     return (getreg32(BL702_USB_BASE + USB_EP0_FIFO_STATUS_OFFSET + 0x10 * ep_idx) & USB_EP0_TX_FIFO_CNT_MASK) >> USB_EP0_TX_FIFO_CNT_SHIFT;
+// }
+
+static bool bflb_usb_ep_isbusy(uint8_t ep_idx)
+{
+    uint32_t regval;
+
+    if (ep_idx == 0) {
+        regval = (getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET) & USB_STS_USB_EP0_SW_RDY);
+    } else {
+        regval = (getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1)) & USB_STS_EP1_RDY);
+    }
+    return regval ? true : false;
+}
+
+static uint32_t bflb_usb_get_intstatus(void)
+{
+    uint32_t regval;
+
+    regval = getreg32(BL702_USB_BASE + USB_INT_STS_OFFSET);
+    regval &= ~getreg32(BL702_USB_BASE + USB_INT_MASK_OFFSET);
+    regval &= getreg32(BL702_USB_BASE + USB_INT_EN_OFFSET);
+    return regval;
+}
+
+static void bflb_usb_int_clear(uint32_t int_clear)
+{
+    uint32_t regval;
+    regval = getreg32(BL702_USB_BASE + USB_INT_CLEAR_OFFSET);
+    regval |= int_clear;
+    putreg32(regval, BL702_USB_BASE + USB_INT_CLEAR_OFFSET);
+}
+
+int usb_dc_init(void)
+{
+    uint32_t regval;
+
+    struct bflb_device_s *gpio;
+
+    gpio = bflb_device_get_by_name("gpio");
+    bflb_gpio_init(gpio, GPIO_PIN_7, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+    bflb_gpio_init(gpio, GPIO_PIN_8, GPIO_ANALOG | GPIO_SMT_EN | GPIO_DRV_0);
+
+    bflb_usb_xcvr_config();
+
+    /* disable USB first */
+    regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+    regval &= ~USB_CR_USB_EN;
+    putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+    /* USB ep0 config */
+    regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+    regval |= USB_CR_USB_EP0_SW_CTRL;
+    regval &= ~USB_CR_USB_EP0_SW_ADDR_MASK;
+    regval &= ~USB_CR_USB_EP0_SW_SIZE_MASK;
+    regval |= (64 << USB_CR_USB_EP0_SW_SIZE_SHIFT);
+    regval |= USB_CR_USB_EP0_SW_NACK_IN;
+    regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+    regval &= ~USB_CR_USB_ROM_DCT_EN;
+    putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+    regval = 0;
+    regval |= USB_CR_USB_RESET_EN;
+    regval |= USB_CR_EP0_SETUP_DONE_EN;
+    regval |= USB_CR_EP0_IN_DONE_EN;
+    regval |= USB_CR_EP0_OUT_DONE_EN;
+    regval |= USB_CR_USB_REND_EN;
+    putreg32(regval, BL702_USB_BASE + USB_INT_EN_OFFSET);
+
+    regval = 0xffffffff;
+    regval &= ~USB_CR_USB_RESET_MASK;
+    regval &= ~USB_CR_EP0_SETUP_DONE_MASK;
+    regval &= ~USB_CR_EP0_IN_DONE_MASK;
+    regval &= ~USB_CR_EP0_OUT_DONE_MASK;
+    regval &= ~USB_CR_USB_REND_MASK;
+    putreg32(regval, BL702_USB_BASE + USB_INT_MASK_OFFSET);
+
+    putreg32(0xffffffff, BL702_USB_BASE + USB_INT_CLEAR_OFFSET);
+
+    bflb_irq_attach(37, USBD_IRQHandler, NULL);
+    bflb_irq_enable(37);
+
+    /* enable usb */
+    regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+    regval |= USB_CR_USB_EN;
+    putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+    return 0;
+}
+
+int usbd_set_address(const uint8_t addr)
+{
+    uint32_t regval;
+
+    regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+    regval &= ~USB_CR_USB_EP0_SW_ADDR_MASK;
+    regval |= (addr << USB_CR_USB_EP0_SW_ADDR_SHIFT);
+    putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+    return 0;
+}
+
+uint8_t usbd_get_port_speed(const uint8_t port)
+{
+    return USB_SPEED_FULL;
+}
+
+int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
+{
+    uint8_t ep;
+    uint8_t ep_type;
+    uint8_t dir;
+    uint32_t regval;
+
+    ep = ep_cfg->ep_addr;
+
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (ep_idx > USB_NUM_BIDIR_ENDPOINTS) {
+        return -1;
+    }
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        g_bl_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+        g_bl_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
+        g_bl_udc.out_ep[ep_idx].ep_enable = 1U;
+        dir = 2;
+    } else {
+        g_bl_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+        g_bl_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
+        g_bl_udc.in_ep[ep_idx].ep_enable = 1U;
+        dir = 1;
+    }
+
+    if (ep_idx != 0) {
+        switch (ep_cfg->ep_type) {
+            case 1:
+                ep_type = 2;
+                break;
+            case 2:
+                ep_type = 4;
+                break;
+            case 3:
+                ep_type = 0;
+                break;
+
+            default:
+                ep_type = 4;
+                break;
+        }
+        bflb_usb_ep_config(ep_idx, ep_type, dir, ep_cfg->ep_mps);
+
+        regval = getreg32(BL702_USB_BASE + USB_INT_EN_OFFSET);
+        regval |= (1 << (9 + ep_idx * 2));
+        putreg32(regval, BL702_USB_BASE + USB_INT_EN_OFFSET);
+
+        regval = getreg32(BL702_USB_BASE + USB_INT_MASK_OFFSET);
+        regval &= ~(1 << (9 + ep_idx * 2));
+        putreg32(regval, BL702_USB_BASE + USB_INT_MASK_OFFSET);
+
+        bflb_usb_ep_set_nak(ep_idx);
+    }
+    return 0;
+}
+
+int usbd_ep_close(const uint8_t ep)
+{
+    return 0;
+}
+
+int usbd_ep_set_stall(const uint8_t ep)
+{
+    uint32_t regval;
+
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (ep_idx == 0) {
+        regval = getreg32(BL702_USB_BASE + USB_CONFIG_OFFSET);
+        regval |= USB_CR_USB_EP0_SW_RDY;
+        regval |= USB_CR_USB_EP0_SW_NACK_OUT;
+        regval |= USB_CR_USB_EP0_SW_NACK_IN;
+        regval |= USB_CR_USB_EP0_SW_STALL;
+        putreg32(regval, BL702_USB_BASE + USB_CONFIG_OFFSET);
+
+    } else {
+        regval = getreg32(BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+        regval |= USB_CR_EP1_STALL;
+        putreg32(regval, BL702_USB_BASE + USB_EP1_CONFIG_OFFSET + 4 * (ep_idx - 1));
+    }
+
+    return 0;
+}
+
+int usbd_ep_clear_stall(const uint8_t ep)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (ep_idx == 0) {
+    } else {
+        bflb_usb_ep_set_ready(ep_idx);
+    }
+
+    return 0;
+}
+
+int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
+{
+    return 0;
+}
+
+int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (!data && data_len) {
+        return -1;
+    }
+
+    if (!g_bl_udc.in_ep[ep_idx].ep_enable) {
+        return -2;
+    }
+
+    g_bl_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
+    g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+    g_bl_udc.in_ep[ep_idx].actual_xfer_len = 0;
+
+    data_len = MIN(data_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+
+    if (ep_idx == 0) {
+        if (data_len == 1) {
+            bflb_usb_ep0_size(1);
+        } else {
+            bflb_usb_ep0_size(g_bl_udc.in_ep[ep_idx].ep_mps);
+        }
+    }
+
+    bflb_usb_mem2fifo(ep_idx, g_bl_udc.in_ep[ep_idx].xfer_buf, data_len);
+    bflb_usb_ep_set_ready(ep_idx);
+
+    return 0;
+}
+
+int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (!data && data_len) {
+        return -1;
+    }
+
+    if (!g_bl_udc.out_ep[ep_idx].ep_enable) {
+        return -2;
+    }
+
+    g_bl_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data;
+    g_bl_udc.out_ep[ep_idx].xfer_len = data_len;
+    g_bl_udc.out_ep[ep_idx].actual_xfer_len = 0;
+    bflb_usb_ep_set_ready(ep_idx);
+
+    return 0;
+}
+
+void USBD_IRQHandler(int irq, void *arg)
+{
+    uint32_t regval;
+    uint32_t intstatus;
+    uint16_t rx_count;
+    uint16_t tx_count;
+
+    intstatus = bflb_usb_get_intstatus();
+    bflb_usb_int_clear(intstatus);
+
+    for (uint8_t ep_idx = 1; ep_idx < USB_NUM_BIDIR_ENDPOINTS; ep_idx++) {
+        if (intstatus & (1 << (9 + 2 * ep_idx))) {
+            if (g_bl_udc.in_ep[ep_idx].ep_enable) {
+                tx_count = MIN(g_bl_udc.in_ep[ep_idx].xfer_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+                g_bl_udc.in_ep[ep_idx].xfer_buf += tx_count;
+                g_bl_udc.in_ep[ep_idx].xfer_len -= tx_count;
+                g_bl_udc.in_ep[ep_idx].actual_xfer_len += tx_count;
+
+                if (g_bl_udc.in_ep[ep_idx].xfer_len == 0) {
+                    usbd_event_ep_in_complete_handler(ep_idx | 0x80, g_bl_udc.in_ep[ep_idx].actual_xfer_len);
+                } else {
+                    tx_count = MIN(g_bl_udc.in_ep[ep_idx].xfer_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+                    bflb_usb_mem2fifo(ep_idx, g_bl_udc.in_ep[ep_idx].xfer_buf, tx_count);
+                    bflb_usb_ep_set_ready(ep_idx);
+                }
+            } else {
+                while (bflb_usb_ep_isbusy(ep_idx)) {
+                }
+
+                rx_count = bflb_usb_get_rxcount(ep_idx);
+                bflb_usb_fifo2mem(ep_idx, g_bl_udc.out_ep[ep_idx].xfer_buf, rx_count);
+
+                g_bl_udc.out_ep[ep_idx].xfer_buf += rx_count;
+                g_bl_udc.out_ep[ep_idx].xfer_len -= rx_count;
+                g_bl_udc.out_ep[ep_idx].actual_xfer_len += rx_count;
+
+                if ((rx_count < g_bl_udc.out_ep[ep_idx].ep_mps) ||
+                    (g_bl_udc.out_ep[ep_idx].xfer_len == 0)) {
+                    usbd_event_ep_out_complete_handler(ep_idx, g_bl_udc.out_ep[ep_idx].actual_xfer_len);
+                } else {
+                    bflb_usb_ep_set_ready(ep_idx);
+                }
+            }
+        }
+    }
+
+    if (intstatus & USB_EP0_SETUP_DONE_INT) {
+        while (bflb_usb_ep_isbusy(0)) {
+        }
+
+        rx_count = bflb_usb_get_rxcount(0);
+        if (rx_count != 8) {
+            printf("setup fail\r\n");
+            return;
+        }
+        bflb_usb_fifo2mem(0, (uint8_t *)&g_bl_udc.setup, 8);
+        usbd_event_ep0_setup_complete_handler((uint8_t *)&g_bl_udc.setup);
+    }
+    if (intstatus & USB_EP0_IN_DONE_INT) {
+        tx_count = MIN(g_bl_udc.in_ep[0].xfer_len, g_bl_udc.in_ep[0].ep_mps);
+        g_bl_udc.in_ep[0].xfer_buf += tx_count;
+        g_bl_udc.in_ep[0].xfer_len -= tx_count;
+        g_bl_udc.in_ep[0].actual_xfer_len += tx_count;
+
+        usbd_event_ep_in_complete_handler(0 | 0x80, g_bl_udc.in_ep[0].actual_xfer_len);
+
+        if (g_bl_udc.setup.wLength == 0) {
+            /* In status, start reading setup */
+            bflb_usb_ep_set_ready(0);
+        } else if (g_bl_udc.setup.wLength && ((g_bl_udc.setup.bmRequestType & USB_REQUEST_DIR_MASK) == USB_REQUEST_DIR_OUT)) {
+            /* In status, start reading setup */
+            bflb_usb_ep_set_ready(0);
+        }
+    }
+    if (intstatus & USB_EP0_OUT_DONE_INT) {
+        while (bflb_usb_ep_isbusy(0)) {
+        }
+
+        rx_count = bflb_usb_get_rxcount(0);
+
+        bflb_usb_fifo2mem(0, g_bl_udc.out_ep[0].xfer_buf, rx_count);
+        g_bl_udc.out_ep[0].xfer_buf += rx_count;
+        g_bl_udc.out_ep[0].xfer_len -= rx_count;
+        g_bl_udc.out_ep[0].actual_xfer_len += rx_count;
+
+        usbd_event_ep_out_complete_handler(0, g_bl_udc.out_ep[0].actual_xfer_len);
+
+        if (rx_count == 0) {
+            /* Out status, start reading setup */
+            bflb_usb_ep_set_ready(0);
+        }
+    }
+
+    if (intstatus & USB_RESET_INT) {
+        memset(&g_bl_udc, 0, sizeof(g_bl_udc));
+
+        regval = 0;
+        regval |= USB_CR_EP0_SETUP_DONE_EN;
+        regval |= USB_CR_EP0_IN_DONE_EN;
+        regval |= USB_CR_EP0_OUT_DONE_EN;
+        regval |= USB_CR_USB_REND_EN;
+        putreg32(regval, BL702_USB_BASE + USB_INT_EN_OFFSET);
+
+        regval = 0xffffffff;
+        regval &= ~USB_CR_USB_RESET_MASK;
+        regval &= ~USB_CR_EP0_SETUP_DONE_MASK;
+        regval &= ~USB_CR_EP0_IN_DONE_MASK;
+        regval &= ~USB_CR_EP0_OUT_DONE_MASK;
+        regval &= ~USB_CR_USB_REND_MASK;
+        putreg32(regval, BL702_USB_BASE + USB_INT_MASK_OFFSET);
+
+        usbd_event_reset_handler();
+    }
+    if (intstatus & USB_REND_INT) {
+        bflb_usb_ep_set_ready(0);
+    }
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c
new file mode 100755
index 0000000000..497f928fbe
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_usb_v2.c
@@ -0,0 +1,1073 @@
+#include "bflb_core.h"
+#include "usbd_core.h"
+#include "usbh_core.h"
+#include "hardware/usb_v2_reg.h"
+
+// #define CONFIG_USB_PINGPONG_ENABLE
+
+#define BLFB_USB_BASE ((uint32_t)0x20072000)
+#define BFLB_PDS_BASE ((uint32_t)0x2000e000)
+
+#define PDS_USB_CTL_OFFSET      (0x500) /* usb_ctl */
+#define PDS_USB_PHY_CTRL_OFFSET (0x504) /* usb_phy_ctrl */
+
+/* 0x500 : usb_ctl */
+#define PDS_REG_USB_SW_RST_N   (1 << 0U)
+#define PDS_REG_USB_EXT_SUSP_N (1 << 1U)
+#define PDS_REG_USB_WAKEUP     (1 << 2U)
+#define PDS_REG_USB_L1_WAKEUP  (1 << 3U)
+#define PDS_REG_USB_DRVBUS_POL (1 << 4U)
+#define PDS_REG_USB_IDDIG      (1 << 5U)
+
+/* 0x504 : usb_phy_ctrl */
+#define PDS_REG_USB_PHY_PONRST       (1 << 0U)
+#define PDS_REG_USB_PHY_OSCOUTEN     (1 << 1U)
+#define PDS_REG_USB_PHY_XTLSEL_SHIFT (2U)
+#define PDS_REG_USB_PHY_XTLSEL_MASK  (0x3 << PDS_REG_USB_PHY_XTLSEL_SHIFT)
+#define PDS_REG_USB_PHY_OUTCLKSEL    (1 << 4U)
+#define PDS_REG_USB_PHY_PLLALIV      (1 << 5U)
+#define PDS_REG_PU_USB20_PSW         (1 << 6U)
+
+#define USB_SOF_TIMER_MASK_AFTER_RESET_HS (0x44C)
+#define USB_SOF_TIMER_MASK_AFTER_RESET_FS (0x2710)
+
+void USBD_IRQHandler(int irq, void *arg);
+
+extern void USBH_IRQHandler();
+
+static void bflb_usb_phy_init(void)
+{
+    uint32_t regval;
+
+    /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0                             */
+    /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
+    /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1        */
+    /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0               */
+    /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1             */
+    /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1               */
+    /* #1.2ms; wait UCLK                                                  */
+    /* wait(soc616_b0.usb_uclk);                                          */
+
+    regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+    regval &= ~PDS_REG_USB_PHY_XTLSEL_MASK;
+    putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+
+    regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+    regval |= PDS_REG_PU_USB20_PSW;
+    putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+
+    regval = getreg32(BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+    regval |= PDS_REG_USB_PHY_PONRST;
+    putreg32(regval, BFLB_PDS_BASE + PDS_USB_PHY_CTRL_OFFSET);
+
+    /* greater than 5T */
+    bflb_mtimer_delay_us(1);
+
+    regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+    regval &= ~PDS_REG_USB_SW_RST_N;
+    putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+    /* greater than 5T */
+    bflb_mtimer_delay_us(1);
+
+    regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+    regval |= PDS_REG_USB_EXT_SUSP_N;
+    putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+    /* wait UCLK 1.2ms */
+    bflb_mtimer_delay_ms(3);
+
+    regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+    regval |= PDS_REG_USB_SW_RST_N;
+    putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+    bflb_mtimer_delay_ms(2);
+}
+
+void usb_hc_low_level_init(void)
+{
+    uint32_t regval;
+
+    bflb_usb_phy_init();
+
+    bflb_irq_attach(37, USBH_IRQHandler, NULL);
+    bflb_irq_enable(37);
+
+    /* enable device-A for host */
+    regval = getreg32(BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+    regval &= ~PDS_REG_USB_IDDIG;
+    putreg32(regval, BFLB_PDS_BASE + PDS_USB_CTL_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+    regval |= USB_A_BUS_DROP_HOV;
+    regval &= ~USB_A_BUS_REQ_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+
+    bflb_mtimer_delay_ms(10);
+
+    /* enable vbus and bus control */
+    regval = getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+    regval &= ~USB_A_BUS_DROP_HOV;
+    regval |= USB_A_BUS_REQ_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_OTG_CSR_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+    regval |= USB_MDEV_INT;
+    regval |= USB_MOTG_INT;
+    regval &= ~USB_MHC_INT;
+    putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+}
+
+uint8_t usbh_get_port_speed(const uint8_t port)
+{
+    uint8_t speed = 3;
+
+    speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
+
+    if (speed == 0) {
+        return USB_SPEED_FULL;
+    } else if (speed == 1) {
+        return USB_SPEED_LOW;
+    } else if (speed == 2) {
+        return USB_SPEED_HIGH;
+    }
+    return USB_SPEED_HIGH;
+}
+
+#define USB_FIFO_F0  0
+#define USB_FIFO_F1  1
+#define USB_FIFO_F2  2
+#define USB_FIFO_F3  3
+#define USB_FIFO_CXF 0xff
+
+#define USB_FIFO_DIR_OUT 0
+#define USB_FIFO_DIR_IN  1
+#define USB_FIFO_DIR_BID 2
+
+#define USB_VDMA_DIR_FIFO2MEM 0
+#define USB_VDMA_DIR_MEM2FIFO 1
+
+#define USB_NUM_BIDIR_ENDPOINTS 5
+
+/* Endpoint state */
+struct bl_ep_state {
+    uint16_t ep_mps;    /* Endpoint max packet size */
+    uint8_t ep_type;    /* Endpoint type */
+    uint8_t ep_stalled; /* Endpoint stall flag */
+    uint8_t ep_enable;  /* Endpoint enable */
+    bool ep_active;
+    uint8_t *xfer_buf;
+    uint32_t xfer_len;
+    uint32_t actual_xfer_len;
+};
+
+struct bl_udc {
+    struct bl_ep_state in_ep[USB_NUM_BIDIR_ENDPOINTS];  /*!< IN endpoint parameters             */
+    struct bl_ep_state out_ep[USB_NUM_BIDIR_ENDPOINTS]; /*!< OUT endpoint parameters            */
+} g_bl_udc;
+
+static void bflb_usb_reset_fifo(uint8_t fifo)
+{
+    uint32_t regval;
+
+    if (fifo == USB_FIFO_CXF) {
+        regval = getreg32(BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+        regval |= USB_CX_CLR;
+        putreg32(regval, BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+    } else {
+        regval = getreg32(BLFB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo);
+        regval |= USB_FFRST0_HOV;
+        putreg32(regval, BLFB_USB_BASE + USB_DEV_FIBC0_OFFSET + 4 * fifo);
+    }
+}
+
+static void bflb_usb_get_setup_packet(uint32_t setup[2])
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+    regval |= USB_ACC_CXF_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+
+    setup[0] = getreg32(BLFB_USB_BASE + USB_DMA_CPS3_OFFSET);
+    setup[1] = getreg32(BLFB_USB_BASE + USB_DMA_CPS3_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+    regval &= ~USB_ACC_CXF_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_DMA_TFN_OFFSET);
+}
+
+static void bflb_usb_set_ep_fifomap(uint8_t ep_idx, uint8_t fifo)
+{
+    uint32_t regval;
+
+    if (ep_idx < 5) {
+        regval = getreg32(BLFB_USB_BASE + USB_DEV_EPMAP0_OFFSET);
+        regval &= ~(0xff << ((ep_idx - 1) * 8));
+        regval |= (fifo << ((ep_idx - 1) * 8));
+        regval |= (fifo << ((ep_idx - 1) * 8 + 4));
+        putreg32(regval, BLFB_USB_BASE + USB_DEV_EPMAP0_OFFSET);
+    } else {
+        regval = getreg32(BLFB_USB_BASE + USB_DEV_EPMAP1_OFFSET);
+        regval &= ~(0xff << ((ep_idx - 4 - 1) * 8));
+        regval |= (fifo << ((ep_idx - 4 - 1) * 8));
+        regval |= (fifo << ((ep_idx - 4 - 1) * 8 + 4));
+        putreg32(regval, BLFB_USB_BASE + USB_DEV_EPMAP1_OFFSET);
+    }
+}
+
+static void bflb_usb_set_fifo_epmap(uint8_t fifo, uint8_t ep_idx, uint8_t dir)
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_FMAP_OFFSET);
+    regval &= ~(0x3f << (fifo * 8));
+    regval |= (ep_idx << (fifo * 8));
+    regval |= (dir << (fifo * 8 + 4));
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_FMAP_OFFSET);
+}
+
+static void bflb_usb_set_outep_mps(uint8_t ep_idx, uint16_t ep_mps)
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+    regval &= ~USB_MAXPS_OEP1_MASK;
+    regval |= ep_mps;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static void bflb_usb_set_inep_mps(uint8_t ep_idx, uint16_t ep_mps)
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+    regval &= ~USB_MAXPS_IEP1_MASK;
+    regval |= ep_mps;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static uint8_t bflb_usb_get_fifo_ep(uint8_t fifo)
+{
+    uint32_t regval;
+
+    regval = (getreg32(BLFB_USB_BASE + USB_DEV_FMAP_OFFSET) & (0xf << (fifo * 8)));
+    regval >>= (fifo * 8);
+    return regval;
+}
+
+static void bflb_usb_fifo_config(uint8_t fifo, uint8_t ep_type, uint16_t block_size, uint8_t block_num, bool fifo_en)
+{
+    uint32_t regval;
+
+    if (fifo < 4) {
+        regval = getreg32(BLFB_USB_BASE + USB_DEV_FCFG_OFFSET);
+        regval &= ~(0x3f << (fifo * 8));
+        regval |= (ep_type << (fifo * 8 + 0));
+        regval |= ((block_num - 1) << (fifo * 8 + 2));
+        if (block_size == 1024) {
+            regval |= (1 << (fifo * 8 + 4));
+        }
+
+        if (fifo_en) {
+            regval |= (1 << (fifo * 8 + 5));
+        }
+        putreg32(regval, BLFB_USB_BASE + USB_DEV_FCFG_OFFSET);
+    }
+}
+
+static void bflb_usb_vdma_start_write(uint8_t fifo, const uint8_t *data, uint32_t len)
+{
+    uint32_t regval;
+
+    if (fifo == USB_FIFO_CXF) {
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+        regval &= ~USB_VDMA_LEN_CXF_MASK;
+        regval &= ~USB_VDMA_IO_CXF;
+        regval |= USB_VDMA_TYPE_CXF;
+        regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+
+        putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_CXFPS2_OFFSET);
+
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+        regval |= USB_VDMA_START_CXF;
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+    } else {
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+        regval &= ~USB_VDMA_LEN_CXF_MASK;
+        regval &= ~USB_VDMA_IO_CXF;
+        regval |= USB_VDMA_TYPE_CXF;
+        regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+
+        putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8);
+
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+        regval |= USB_VDMA_START_CXF;
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+    }
+}
+
+static void bflb_usb_vdma_start_read(uint8_t fifo, uint8_t *data, uint32_t len)
+{
+    uint32_t regval;
+
+    if (fifo == USB_FIFO_CXF) {
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+        regval &= ~USB_VDMA_LEN_CXF_MASK;
+        regval &= ~USB_VDMA_IO_CXF;
+        regval &= ~USB_VDMA_TYPE_CXF;
+        regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+
+        putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_CXFPS2_OFFSET);
+
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+        regval |= USB_VDMA_START_CXF;
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET);
+    } else {
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+        regval &= ~USB_VDMA_LEN_CXF_MASK;
+        regval &= ~USB_VDMA_IO_CXF;
+        regval &= ~USB_VDMA_TYPE_CXF;
+        regval |= (len << USB_VDMA_LEN_CXF_SHIFT);
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+
+        putreg32((uint32_t)data, BLFB_USB_BASE + USB_VDMA_F0PS2_OFFSET + fifo * 8);
+
+        regval = getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+        regval |= USB_VDMA_START_CXF;
+        putreg32(regval, BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8);
+    }
+}
+
+static uint32_t bflb_usb_vdma_get_remain_size(uint8_t fifo)
+{
+    uint32_t regval;
+
+    if (fifo == USB_FIFO_CXF) {
+        regval = (getreg32(BLFB_USB_BASE + USB_VDMA_CXFPS1_OFFSET) & USB_VDMA_LEN_CXF_MASK);
+        regval >>= USB_VDMA_LEN_CXF_SHIFT;
+
+    } else {
+        regval = (getreg32(BLFB_USB_BASE + USB_VDMA_F0PS1_OFFSET + fifo * 8) & USB_VDMA_LEN_CXF_MASK);
+        regval >>= USB_VDMA_LEN_CXF_SHIFT;
+    }
+
+    return regval;
+}
+
+static inline void bflb_usb_control_transfer_done(void)
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+    regval |= USB_CX_DONE;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+}
+
+static inline void bflb_usb_set_mult(uint8_t ep_idx, uint8_t mult)
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+    regval &= ~USB_TX_NUM_HBW_IEP1_MASK;
+    regval |= (mult << USB_TX_NUM_HBW_IEP1_SHIFT);
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static inline void bflb_usb_send_zlp(uint8_t ep_idx)
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+    regval |= USB_TX0BYTE_IEP1;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+}
+
+static inline uint32_t bflb_usb_get_tx_zlp_intstatus(void)
+{
+    return getreg32(BLFB_USB_BASE + USB_DEV_TXZ_OFFSET);
+}
+
+static inline uint32_t bflb_usb_get_rx_zlp_intstatus(void)
+{
+    return getreg32(BLFB_USB_BASE + USB_DEV_RXZ_OFFSET);
+}
+
+static inline void bflb_usb_clear_tx_zlp_intstatus(uint8_t ep_idx)
+{
+    putreg32((1 << (ep_idx - 1)), BLFB_USB_BASE + USB_DEV_TXZ_OFFSET);
+}
+
+static inline void bflb_usb_clear_rx_zlp_intstatus(uint8_t ep_idx)
+{
+    putreg32((1 << (ep_idx - 1)), BLFB_USB_BASE + USB_DEV_RXZ_OFFSET);
+}
+
+static uint32_t bflb_usb_get_source_group_intstatus(uint8_t group)
+{
+    switch (group) {
+        case 0:
+            return (getreg32(BLFB_USB_BASE + USB_DEV_ISG0_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG0_OFFSET));
+        case 1:
+            return (getreg32(BLFB_USB_BASE + USB_DEV_ISG1_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG1_OFFSET));
+        case 2:
+            return (getreg32(BLFB_USB_BASE + USB_DEV_ISG2_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG2_OFFSET));
+        case 3:
+            return (getreg32(BLFB_USB_BASE + USB_DEV_ISG3_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG3_OFFSET));
+        case 4:
+            return (getreg32(BLFB_USB_BASE + USB_DEV_ISG4_OFFSET) & ~getreg32(BLFB_USB_BASE + USB_DEV_MISG4_OFFSET));
+        default:
+            break;
+    }
+    return 0;
+}
+
+static void bflb_usb_source_group_int_clear(uint8_t group, uint32_t int_clear)
+{
+    switch (group) {
+        case 0:
+            putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG0_OFFSET);
+            break;
+        case 1:
+            putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG1_OFFSET);
+            break;
+        case 2:
+            putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG2_OFFSET);
+            break;
+        case 3:
+            putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG3_OFFSET);
+            break;
+        case 4:
+            putreg32(int_clear, BLFB_USB_BASE + USB_DEV_ISG4_OFFSET);
+            break;
+
+        default:
+            break;
+    }
+}
+
+static uint8_t usb_get_transfer_fifo(uint8_t ep_idx)
+{
+    uint8_t target_fifo_id;
+
+    if ((g_bl_udc.out_ep[ep_idx].ep_mps > 512) || (g_bl_udc.in_ep[ep_idx].ep_mps > 512)) {
+#ifdef CONFIG_USB_PINGPONG_ENABLE
+        target_fifo_id = 0;
+#else
+        target_fifo_id = ((2 * ep_idx - 1) - 1);
+#endif
+    } else {
+#ifdef CONFIG_USB_PINGPONG_ENABLE
+        target_fifo_id = ((2 * ep_idx - 1) - 1);
+#else
+        target_fifo_id = (ep_idx - 1);
+#endif
+    }
+
+    return target_fifo_id;
+}
+
+int usb_dc_init(void)
+{
+    uint32_t regval;
+
+    bflb_usb_phy_init();
+
+    bflb_irq_attach(37, USBD_IRQHandler, NULL);
+    bflb_irq_enable(37);
+
+    /* disable global irq */
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+    regval &= ~USB_GLINT_EN_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+    regval |= USB_UNPLUG;
+    putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+    regval &= ~USB_CAP_RMWAKUP;
+    regval |= USB_CHIP_EN_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+    regval |= USB_SFRST_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+    while (getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET) & USB_SFRST_HOV) {
+    }
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+    regval &= ~USB_AFT_CONF;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+    regval &= ~USB_SOFMT_MASK;
+#ifdef CONFIG_USB_HS
+    regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS;
+#else
+    regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS;
+#endif
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+
+    /* enable setup irq in source group0 */
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_MISG0_OFFSET);
+    regval &= ~USB_MCX_SETUP_INT;
+    regval |= USB_MCX_IN_INT;
+    regval |= (1 << 3);
+    regval |= USB_MCX_OUT_INT;
+    regval |= USB_MCX_IN_INT;
+    regval |= USB_MCX_COMFAIL_INT;
+    regval |= USB_MCX_COMABORT_INT;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_MISG0_OFFSET);
+
+    /* disable all fifo irq in source group1 */
+    putreg32(0xffffffff, BLFB_USB_BASE + USB_DEV_MISG1_OFFSET);
+
+    /* enable rst/tx0/rx0 irq in source group2 */
+    regval = 0xffffffff;
+    regval &= ~USB_MUSBRST_INT;
+    regval &= ~USB_MSUSP_INT;
+    regval &= ~USB_MRESM_INT;
+    regval &= ~USB_MTX0BYTE_INT;
+    regval &= ~USB_MRX0BYTE_INT;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_MISG2_OFFSET);
+
+    /* enable vdma cmplt and error irq in source group3 */
+    regval = 0xffffffff;
+    regval &= ~(USB_MVDMA_CMPLT_CXF |
+                USB_MVDMA_CMPLT_F0 |
+                USB_MVDMA_CMPLT_F1 |
+                USB_MVDMA_CMPLT_F2 |
+                USB_MVDMA_CMPLT_F3);
+    // regval &= ~(USB_MVDMA_ERROR_CXF |
+    //             USB_MVDMA_ERROR_F0 |
+    //             USB_MVDMA_ERROR_F1 |
+    //             USB_MVDMA_ERROR_F2 |
+    //             USB_MVDMA_ERROR_F3);
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_MISG3_OFFSET);
+
+    /* enable group irq */
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_MIGR_OFFSET);
+    regval &= ~USB_MINT_G0;
+    regval &= ~USB_MINT_G1;
+    regval &= ~USB_MINT_G2;
+    regval &= ~USB_MINT_G3;
+    regval &= ~USB_MINT_G4;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_MIGR_OFFSET);
+
+    /* enable device irq */
+    regval = getreg32(BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+    regval |= USB_MHC_INT;
+    regval |= USB_MOTG_INT;
+    regval &= ~USB_MDEV_INT;
+    putreg32(regval, BLFB_USB_BASE + USB_GLB_INT_OFFSET);
+
+    bflb_usb_source_group_int_clear(2, 0x3ff);
+    bflb_usb_source_group_int_clear(3, 0xffffffff);
+
+    for (uint8_t i = 1; i < 9; i++) {
+        bflb_usb_set_ep_fifomap(i, 15);
+        bflb_usb_set_fifo_epmap(i, 15, 0);
+    }
+
+    /* enable vdma */
+    regval = getreg32(BLFB_USB_BASE + USB_VDMA_CTRL_OFFSET);
+    regval |= USB_VDMA_EN;
+    putreg32(regval, BLFB_USB_BASE + USB_VDMA_CTRL_OFFSET);
+
+    regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+    regval &= ~USB_UNPLUG;
+    putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+    /* enable global irq */
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+    regval |= USB_GLINT_EN_HOV;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_CTL_OFFSET);
+
+    return 0;
+}
+
+int usb_dc_deinit(void)
+{
+    return 0;
+}
+
+int usbd_set_address(const uint8_t addr)
+{
+    uint32_t regval;
+
+    regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+    regval &= ~USB_DEVADR_MASK;
+    regval |= addr;
+    putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+
+    return 0;
+}
+
+uint8_t usbd_get_port_speed(const uint8_t port)
+{
+    uint8_t speed = 3;
+
+    speed = (getreg32(BLFB_USB_BASE + USB_OTG_CSR_OFFSET) & USB_SPD_TYP_HOV_POV_MASK) >> USB_SPD_TYP_HOV_POV_SHIFT;
+
+    if (speed == 0) {
+        return USB_SPEED_FULL;
+    } else if (speed == 1) {
+        return USB_SPEED_LOW;
+    } else if (speed == 2) {
+        return USB_SPEED_HIGH;
+    }
+    return USB_SPEED_HIGH;
+}
+
+int usbd_ep_open(const struct usbd_endpoint_cfg *ep_cfg)
+{
+    uint8_t ep;
+    uint32_t regval;
+
+    ep = ep_cfg->ep_addr;
+
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if ((ep_idx > 4) && (ep_idx < 9)) {
+        return 0;
+    }
+
+    if (USB_EP_DIR_IS_OUT(ep)) {
+        g_bl_udc.out_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+        g_bl_udc.out_ep[ep_idx].ep_type = ep_cfg->ep_type;
+        g_bl_udc.out_ep[ep_idx].ep_enable = 1U;
+        bflb_usb_set_outep_mps(ep_idx, ep_cfg->ep_mps);
+    } else {
+        g_bl_udc.in_ep[ep_idx].ep_mps = ep_cfg->ep_mps;
+        g_bl_udc.in_ep[ep_idx].ep_type = ep_cfg->ep_type;
+        g_bl_udc.in_ep[ep_idx].ep_enable = 1U;
+        bflb_usb_set_inep_mps(ep_idx, ep_cfg->ep_mps);
+        bflb_usb_set_mult(ep_idx, 0);
+    }
+
+    if (ep_idx != 0) {
+#ifndef CONFIG_USB_PINGPONG_ENABLE
+        if (ep_cfg->ep_mps > 512) {
+            bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+            bflb_usb_set_ep_fifomap(2, USB_FIFO_F2);
+
+            bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID);
+
+            if (ep_idx == 1) {
+                bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 1024, 1, true);
+                bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 1024, 1, false);
+            } else if (ep_idx == 2) {
+                bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 1024, 1, true);
+                bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 1024, 1, false);
+            } else {
+                return -1;
+            }
+        } else {
+            bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+            bflb_usb_set_ep_fifomap(2, USB_FIFO_F1);
+            bflb_usb_set_ep_fifomap(3, USB_FIFO_F2);
+            bflb_usb_set_ep_fifomap(4, USB_FIFO_F3);
+
+            bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F1, 2, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F2, 3, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F3, 4, USB_FIFO_DIR_BID);
+
+            if (ep_idx == 1) {
+                bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 512, 1, true);
+            } else if (ep_idx == 2) {
+                bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 512, 1, true);
+            } else if (ep_idx == 3) {
+                bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 512, 1, true);
+            } else if (ep_idx == 4) {
+                bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 512, 1, true);
+            } else {
+                return -1;
+            }
+        }
+#else
+        if (ep_cfg->ep_mps > 512) {
+            bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+
+            bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F2, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F3, 1, USB_FIFO_DIR_BID);
+
+            if (ep_idx == 1) {
+                bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 1024, 2, true);
+                bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 1024, 2, false);
+                bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 1024, 2, false);
+                bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 1024, 2, false);
+            } else {
+                return -1;
+            }
+        } else {
+            bflb_usb_set_ep_fifomap(1, USB_FIFO_F0);
+            bflb_usb_set_ep_fifomap(2, USB_FIFO_F2);
+
+            bflb_usb_set_fifo_epmap(USB_FIFO_F0, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F1, 1, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F2, 2, USB_FIFO_DIR_BID);
+            bflb_usb_set_fifo_epmap(USB_FIFO_F3, 2, USB_FIFO_DIR_BID);
+
+            if (ep_idx == 1) {
+                bflb_usb_fifo_config(USB_FIFO_F0, ep_cfg->ep_type, 512, 2, true);
+                bflb_usb_fifo_config(USB_FIFO_F1, ep_cfg->ep_type, 512, 2, false);
+            } else if (ep_idx == 2) {
+                bflb_usb_fifo_config(USB_FIFO_F2, ep_cfg->ep_type, 512, 2, true);
+                bflb_usb_fifo_config(USB_FIFO_F3, ep_cfg->ep_type, 512, 2, false);
+            } else {
+                return -1;
+            }
+        }
+#endif
+        regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+        regval |= USB_AFT_CONF;
+        putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+    }
+    return 0;
+}
+
+int usbd_ep_close(const uint8_t ep)
+{
+    return 0;
+}
+
+int usbd_ep_set_stall(const uint8_t ep)
+{
+    uint32_t regval;
+
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (ep_idx == 0) {
+        regval = getreg32(BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+        regval |= USB_CX_STL;
+        putreg32(regval, BLFB_USB_BASE + USB_DEV_ADR_OFFSET);
+    } else {
+        if (USB_EP_DIR_IS_OUT(ep)) {
+            regval = getreg32(BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+            regval |= USB_STL_OEP1;
+            //regval |= USB_RSTG_OEP1;
+            putreg32(regval, BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+        } else {
+            regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+            regval |= USB_STL_IEP1;
+            //regval |= USB_RSTG_IEP1;
+            putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+        }
+    }
+
+    return 0;
+}
+
+int usbd_ep_clear_stall(const uint8_t ep)
+{
+    uint32_t regval;
+
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (ep_idx == 0) {
+    } else {
+        if (USB_EP_DIR_IS_OUT(ep)) {
+            regval = getreg32(BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+            //regval &= ~USB_RSTG_OEP1;
+            regval &= ~USB_STL_OEP1;
+            putreg32(regval, BLFB_USB_BASE + USB_DEV_OUTMPS1_OFFSET + (ep_idx - 1) * 4);
+        } else {
+            regval = getreg32(BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+            //regval &= ~USB_RSTG_IEP1;
+            regval &= ~USB_STL_IEP1;
+            putreg32(regval, BLFB_USB_BASE + USB_DEV_INMPS1_OFFSET + (ep_idx - 1) * 4);
+        }
+    }
+
+    return 0;
+}
+
+int usbd_ep_is_stalled(const uint8_t ep, uint8_t *stalled)
+{
+    return 0;
+}
+
+int usbd_ep_start_write(const uint8_t ep, const uint8_t *data, uint32_t data_len)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (!data && data_len) {
+        return -1;
+    }
+
+    if (!g_bl_udc.in_ep[ep_idx].ep_enable) {
+        return -2;
+    }
+
+    g_bl_udc.in_ep[ep_idx].xfer_buf = (uint8_t *)data;
+    g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+    g_bl_udc.in_ep[ep_idx].actual_xfer_len = 0;
+    g_bl_udc.in_ep[ep_idx].ep_active = true;
+
+    if (ep_idx == 0) {
+        if (data_len == 0) {
+            g_bl_udc.in_ep[ep_idx].ep_active = false;
+            bflb_usb_control_transfer_done();
+        } else {
+            data_len = MIN(data_len, g_bl_udc.in_ep[ep_idx].ep_mps);
+            g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+            bflb_usb_vdma_start_write(USB_FIFO_CXF, data, data_len);
+        }
+    } else {
+        if (data_len == 0) {
+            bflb_usb_send_zlp(ep_idx);
+        } else {
+            bflb_usb_vdma_start_write(usb_get_transfer_fifo(ep_idx), data, data_len);
+        }
+    }
+
+    return 0;
+}
+
+int usbd_ep_start_read(const uint8_t ep, uint8_t *data, uint32_t data_len)
+{
+    uint8_t ep_idx = USB_EP_GET_IDX(ep);
+
+    if (!data && data_len) {
+        return -1;
+    }
+
+    if (!g_bl_udc.out_ep[ep_idx].ep_enable) {
+        return -2;
+    }
+
+    g_bl_udc.out_ep[ep_idx].xfer_buf = (uint8_t *)data;
+    g_bl_udc.out_ep[ep_idx].xfer_len = data_len;
+    g_bl_udc.out_ep[ep_idx].actual_xfer_len = 0;
+    g_bl_udc.out_ep[ep_idx].ep_active = true;
+
+    if (ep_idx == 0) {
+        if (data_len == 0) {
+            g_bl_udc.out_ep[ep_idx].ep_active = false;
+        } else {
+            data_len = MIN(data_len, g_bl_udc.out_ep[ep_idx].ep_mps);
+            g_bl_udc.in_ep[ep_idx].xfer_len = data_len;
+            bflb_usb_vdma_start_read(USB_FIFO_CXF, data, data_len);
+        }
+    } else {
+        if (data_len == 0) {
+        } else {
+            bflb_usb_vdma_start_read(usb_get_transfer_fifo(ep_idx), data, data_len);
+        }
+    }
+    return 0;
+}
+
+void USBD_IRQHandler(int irq, void *arg)
+{
+    uint32_t glb_intstatus;
+    uint32_t dev_intstatus;
+    uint32_t subgroup_intstatus;
+    uint32_t regval;
+    uint8_t ep_idx;
+
+    glb_intstatus = getreg32(BLFB_USB_BASE + USB_GLB_ISR_OFFSET);
+
+    if (glb_intstatus & USB_DEV_INT) {
+        dev_intstatus = getreg32(BLFB_USB_BASE + USB_DEV_IGR_OFFSET);
+        if (dev_intstatus & USB_INT_G0) {
+            subgroup_intstatus = bflb_usb_get_source_group_intstatus(0);
+
+            if (subgroup_intstatus & USB_CX_SETUP_INT) {
+                uint32_t setup[2];
+                bflb_usb_get_setup_packet(setup);
+                usbd_event_ep0_setup_complete_handler((uint8_t *)setup);
+            }
+        }
+        if (dev_intstatus & USB_INT_G1) {
+        }
+        if (dev_intstatus & USB_INT_G2) {
+            subgroup_intstatus = bflb_usb_get_source_group_intstatus(2);
+
+            if (subgroup_intstatus & USB_SUSP_INT) {
+                bflb_usb_source_group_int_clear(2, USB_SUSP_INT);
+                usbd_event_suspend_handler();
+            }
+            if (subgroup_intstatus & USB_RESM_INT) {
+                bflb_usb_source_group_int_clear(2, USB_RESM_INT);
+                usbd_event_resume_handler();
+            }
+            if (subgroup_intstatus & USB_TX0BYTE_INT) {
+                for (uint8_t i = 1; i < 5; i++) {
+                    if (bflb_usb_get_tx_zlp_intstatus() & (1 << (i - 1))) {
+                        bflb_usb_clear_tx_zlp_intstatus(i);
+                        usbd_event_ep_in_complete_handler(i | 0x80, 0);
+                    }
+                }
+                bflb_usb_source_group_int_clear(2, USB_TX0BYTE_INT);
+            }
+            if (subgroup_intstatus & USB_RX0BYTE_INT) {
+                for (uint8_t i = 1; i < 5; i++) {
+                    if (bflb_usb_get_rx_zlp_intstatus() & (1 << (i - 1))) {
+                        bflb_usb_clear_rx_zlp_intstatus(i);
+                        usbd_event_ep_out_complete_handler(i, 0);
+                    }
+                }
+
+                bflb_usb_source_group_int_clear(2, USB_RX0BYTE_INT);
+            }
+            if (subgroup_intstatus & USBRST_INT) {
+                bflb_usb_source_group_int_clear(2, USBRST_INT);
+
+                bflb_usb_reset_fifo(USB_FIFO_F0);
+                bflb_usb_reset_fifo(USB_FIFO_F1);
+                bflb_usb_reset_fifo(USB_FIFO_F2);
+                bflb_usb_reset_fifo(USB_FIFO_F3);
+                bflb_usb_reset_fifo(USB_FIFO_CXF);
+
+                regval = getreg32(BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+                regval &= ~USB_SOFMT_MASK;
+#ifdef CONFIG_USB_HS
+                regval |= USB_SOF_TIMER_MASK_AFTER_RESET_HS;
+#else
+                regval |= USB_SOF_TIMER_MASK_AFTER_RESET_FS;
+#endif
+                putreg32(regval, BLFB_USB_BASE + USB_DEV_SMT_OFFSET);
+
+                memset(&g_bl_udc, 0, sizeof(g_bl_udc));
+
+                usbd_event_reset_handler();
+            }
+        }
+        if (dev_intstatus & USB_INT_G3) {
+            subgroup_intstatus = bflb_usb_get_source_group_intstatus(3);
+            bflb_usb_source_group_int_clear(3, subgroup_intstatus);
+            if (subgroup_intstatus & USB_VDMA_CMPLT_CXF) {
+                if (g_bl_udc.in_ep[0].ep_active) {
+                    g_bl_udc.in_ep[0].ep_active = false;
+                    g_bl_udc.in_ep[0].actual_xfer_len = g_bl_udc.in_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF);
+                    if (g_bl_udc.in_ep[0].actual_xfer_len < g_bl_udc.in_ep[0].ep_mps) {
+                        bflb_usb_control_transfer_done();
+                    }
+                    usbd_event_ep_in_complete_handler(0x80, g_bl_udc.in_ep[0].actual_xfer_len);
+                } else {
+                    g_bl_udc.out_ep[0].ep_active = false;
+                    g_bl_udc.out_ep[0].actual_xfer_len = g_bl_udc.out_ep[0].xfer_len - bflb_usb_vdma_get_remain_size(USB_FIFO_CXF);
+                    usbd_event_ep_out_complete_handler(0x00, g_bl_udc.out_ep[0].actual_xfer_len);
+                }
+            }
+
+            for (uint8_t i = 0; i < 4; i++) {
+                if (subgroup_intstatus & (1 << (i + 1))) {
+                    ep_idx = bflb_usb_get_fifo_ep(i);
+                    if (g_bl_udc.in_ep[ep_idx].ep_active) {
+                        g_bl_udc.in_ep[ep_idx].ep_active = 0;
+                        g_bl_udc.in_ep[ep_idx].actual_xfer_len = g_bl_udc.in_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i);
+                        usbd_event_ep_in_complete_handler(ep_idx | 0x80, g_bl_udc.in_ep[ep_idx].actual_xfer_len);
+                    } else {
+                        g_bl_udc.out_ep[ep_idx].ep_active = 0;
+                        g_bl_udc.out_ep[ep_idx].actual_xfer_len = g_bl_udc.out_ep[ep_idx].xfer_len - bflb_usb_vdma_get_remain_size(i);
+                        usbd_event_ep_out_complete_handler(ep_idx & 0x7f, g_bl_udc.out_ep[ep_idx].actual_xfer_len);
+                    }
+                }
+            }
+        }
+        if (dev_intstatus & USB_INT_G4) {
+        }
+    }
+}
+
+#ifdef CONFIG_USBDEV_TEST_MODE
+void usbd_execute_test_mode(struct usb_setup_packet *setup)
+{
+    uint32_t regval;
+    uint8_t index = setup->wIndex >> 8;
+
+    switch (index) {
+        case 1: // Test_J
+        {
+            regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+            regval |= USB_TST_JSTA;
+            putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+            bflb_usb_control_transfer_done();
+        } break;
+        case 2: // Test_K
+        {
+            regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+            regval |= USB_TST_KSTA;
+            putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+            bflb_usb_control_transfer_done();
+        } break;
+        case 3: // TEST_SE0_NAK
+        {
+            regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+            regval |= USB_TST_SE0NAK;
+            putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+            bflb_usb_control_transfer_done();
+        } break;
+        case 4: // Test_Packet
+        {
+            bflb_usb_control_transfer_done();
+            regval = getreg32(BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+            regval |= USB_TST_PKT;
+            putreg32(regval, BLFB_USB_BASE + USB_PHY_TST_OFFSET);
+
+            __attribute__((aligned(32))) uint8_t temp[53];
+            uint8_t *pp;
+            uint8_t i;
+            pp = temp;
+
+            for (i = 0; i < 9; i++) /*JKJKJKJK x 9*/
+                *pp++ = 0x00;
+
+            for (i = 0; i < 8; i++) /* 8*AA */
+                *pp++ = 0xAA;
+
+            for (i = 0; i < 8; i++) /* 8*EE */
+                *pp++ = 0xEE;
+
+            *pp++ = 0xFE;
+
+            for (i = 0; i < 11; i++) /* 11*FF */
+                *pp++ = 0xFF;
+
+            *pp++ = 0x7F;
+            *pp++ = 0xBF;
+            *pp++ = 0xDF;
+            *pp++ = 0xEF;
+            *pp++ = 0xF7;
+            *pp++ = 0xFB;
+            *pp++ = 0xFD;
+            *pp++ = 0xFC;
+            *pp++ = 0x7E;
+            *pp++ = 0xBF;
+            *pp++ = 0xDF;
+            *pp++ = 0xEF;
+            *pp++ = 0xF7;
+            *pp++ = 0xFB;
+            *pp++ = 0xFD;
+            *pp++ = 0x7E;
+
+            bflb_usb_vdma_start_write(USB_FIFO_CXF, temp, 53);
+
+            regval = getreg32(BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+            regval |= USB_TST_PKDONE;
+            putreg32(regval, BLFB_USB_BASE + USB_DEV_CXCFE_OFFSET);
+
+        } break;
+        case 5: // Test_Force_Enable
+            break;
+
+        default:
+            break;
+    }
+}
+#endif
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_wdg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_wdg.c
new file mode 100755
index 0000000000..e6905728bc
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/bflb_wdg.c
@@ -0,0 +1,119 @@
+#include "bflb_wdg.h"
+#include "bflb_clock.h"
+#include "hardware/timer_reg.h"
+
+void bflb_wdg_init(struct bflb_device_s *dev, const struct bflb_wdg_config_s *config)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+    putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+    regval = getreg32(reg_base + TIMER_WMER_OFFSET);
+    regval &= ~TIMER_WE;
+    if (config->mode == WDG_MODE_INTERRUPT) {
+        regval &= ~TIMER_WRIE;
+    } else {
+        regval |= TIMER_WRIE;
+    }
+    putreg32(regval, reg_base + TIMER_WMER_OFFSET);
+
+    /* Configure clock source */
+    regval = getreg32(reg_base + TIMER_TCCR_OFFSET);
+    regval &= ~TIMER_CS_WDT_MASK;
+    regval |= (config->clock_source << TIMER_CS_WDT_SHIFT);
+    putreg32(regval, reg_base + TIMER_TCCR_OFFSET);
+
+    /* Configure clock div */
+    regval = getreg32(reg_base + TIMER_TCDR_OFFSET);
+    regval &= ~TIMER_WCDR_MASK;
+    regval |= (config->clock_div << TIMER_WCDR_SHIFT);
+    putreg32(regval, reg_base + TIMER_TCDR_OFFSET);
+
+    putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+    putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+    putreg16(config->comp_val, reg_base + TIMER_WMR_OFFSET);
+}
+
+void bflb_wdg_start(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+    putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+    regval = getreg32(reg_base + TIMER_WMER_OFFSET);
+    regval |= TIMER_WE;
+    putreg32(regval, reg_base + TIMER_WMER_OFFSET);
+}
+
+void bflb_wdg_stop(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+    putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+    regval = getreg32(reg_base + TIMER_WMER_OFFSET);
+    regval &= ~TIMER_WE;
+    putreg32(regval, reg_base + TIMER_WMER_OFFSET);
+}
+
+uint16_t bflb_wdg_get_countervalue(struct bflb_device_s *dev)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    return getreg16(reg_base + TIMER_WVR_OFFSET);
+}
+
+void bflb_wdg_set_countervalue(struct bflb_device_s *dev, uint16_t value)
+{
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+    putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+    putreg16(value, reg_base + TIMER_WMR_OFFSET);
+}
+
+void bflb_wdg_reset_countervalue(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+    putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+    regval = getreg32(reg_base + TIMER_WCR_OFFSET);
+    regval |= TIMER_WCR;
+    putreg32(regval, reg_base + TIMER_WCR_OFFSET);
+}
+
+void bflb_wdg_compint_clear(struct bflb_device_s *dev)
+{
+    uint32_t regval;
+    uint32_t reg_base;
+
+    reg_base = dev->reg_base;
+
+    putreg16(0xBABA, reg_base + TIMER_WFAR_OFFSET);
+    putreg16(0xEB10, reg_base + TIMER_WSAR_OFFSET);
+
+    regval = getreg32(reg_base + TIMER_WICR_OFFSET);
+    regval |= TIMER_WICLR;
+    putreg32(regval, reg_base + TIMER_WICR_OFFSET);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.c
new file mode 100755
index 0000000000..994528d194
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.c
@@ -0,0 +1,3703 @@
+/**
+  ******************************************************************************
+  * @file    bflb_sf_cfg.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
+#include "bflb_xip_sflash.h"
+
+/** @addtogroup  BL628_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_Private_Macros
+ *  @{
+ */
+#define BFLB_FLASH_CFG_MAGIC   "FCFG"
+
+/*@} end of group SF_CFG_Private_Macros */
+
+/** @defgroup  SF_CFG_Private_Types
+ *  @{
+ */
+typedef struct
+{
+    uint32_t jedec_id;
+    char *name;
+    const spi_flash_cfg_type *cfg;
+}flash_info_t;
+
+/*@} end of group SF_CFG_Private_Types */
+
+/** @defgroup  SF_CFG_Private_Variables
+ *  @{
+ */
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_80dv = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0xFF,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3d,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_16jv = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3d,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_80ew_16fw_32jw_32fw_32fv = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xa0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 400,
+    .time_e_32k = 1600,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_128jw_128jv = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0xFF,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 400,
+    .time_e_32k = 1600,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_issi = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x9d,
+
+    .de_burst_wrap_cmd = 0xC0,
+    .de_burst_wrap_cmd_dmy_clk = 0x00,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .de_burst_wrap_data = 0x00,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0,
+    .qe_bit = 0x06,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA0,
+
+    .burst_wrap_cmd = 0xC0,
+    .burst_wrap_cmd_dmy_clk = 0x00,
+    .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .burst_wrap_data = 0x06,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 5,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_md_40d = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x51,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0xA0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_DO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_lq08c_le16c_lq32d_wq32e = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_q80e_q16e = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_wq80e_wq16e = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 32 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 8 / 8,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0x12,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_gd_q32e_q128e = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xC2,
+
+    .de_burst_wrap_cmd = 0xC0,
+    .de_burst_wrap_cmd_dmy_clk = 0x00,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .de_burst_wrap_data = 0x10,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0,
+    .qe_bit = 0x06,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA5,
+
+    .burst_wrap_cmd = 0xC0,
+    .burst_wrap_cmd_dmy_clk = 0x00,
+    .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .burst_wrap_data = 0x02,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x38,
+    .qpp_addr_mode = SF_CTRL_ADDR_4_LINES,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 45,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic_1635f = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xC2,
+
+    .de_burst_wrap_cmd = 0xC0,
+    .de_burst_wrap_cmd_dmy_clk = 0x00,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .de_burst_wrap_data = 0x10,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0,
+    .qe_bit = 0x06,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA5,
+
+    .burst_wrap_cmd = 0xC0,
+    .burst_wrap_cmd_dmy_clk = 0x00,
+    .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .burst_wrap_data = 0x02,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x38,
+    .qpp_addr_mode = SF_CTRL_ADDR_4_LINES,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 45,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mxic_25l256 = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc2,
+
+    .de_burst_wrap_cmd = 0xC0,
+    .de_burst_wrap_cmd_dmy_clk = 0x00,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .de_burst_wrap_data = 0x10,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0,
+    .qe_bit = 0x06,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x15,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA5,
+
+    .burst_wrap_cmd = 0xC0,
+    .burst_wrap_cmd_dmy_clk = 0x00,
+    .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .burst_wrap_data = 0x02,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x38,
+    .qpp_addr_mode = SF_CTRL_ADDR_4_LINES,
+
+    .io_mode = (SF_CTRL_QIO_MODE | 0x20),
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 400,
+    .time_e_32k = 1000,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_xtx = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x0B,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0x01,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 6000,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_puya_q80l_q80h_q16h = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x85,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0x01,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3d,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 8,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_puya_q32h = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x85,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0x01,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 8,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_boya40 = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x68,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0xA0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_DO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_boya = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x68,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0x01,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_mx_kh25 = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc2,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x00,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x00,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = (SF_CTRL_DO_MODE | 0x10),
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_winb_256fv= {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xa0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = 0x24,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 400,
+    .time_e_32k = 1600,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_xtx_q80b_f16b = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x85,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0x01,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xa0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = 0x14,
+    .clk_delay = 1,
+    .clk_invert = 0x01,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+#else
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+#endif
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[] = {
+    {
+        .jedec_id = 0x1440ef,
+        //.name="winb_80dv_08_33",
+        .cfg = &flash_cfg_winb_80dv,
+    },
+    {
+        .jedec_id = 0x1540ef,
+        //.name="winb_16dv_16_33",
+        .cfg = &flash_cfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x1570ef,
+        //.name="wb_16jv_16_33",
+        .cfg = &flash_cfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x1640ef,
+        //.name="winb_32fv_32_33",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x1740ef,
+        //.name="wb_64jv_64_33",
+        .cfg = &flash_cfg_winb_128jw_128jv,
+    },
+    {
+        .jedec_id = 0x1840ef,
+        //.name="winb_128jv_128_33",
+        .cfg = &flash_cfg_winb_128jw_128jv,
+    },
+    {
+        .jedec_id = 0x1870ef,
+        //.name="winb_128jv_128_33",
+        .cfg = &flash_cfg_winb_128jw_128jv,
+    },
+    {
+        .jedec_id = 0x1940ef,
+        //.name="wb_256fv_256_33",
+        .cfg = &flash_cfg_winb_256fv,
+    },
+    {
+        .jedec_id = 0x1460ef,
+        //.name="winb_80ew_08_18",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x1560ef,
+        //.name="winb_16fw_16_18",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x1660ef,
+        //.name="winb_32fw_32_18",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x1760ef,
+        //.name="wb_64jw_64_18",
+        .cfg = &flash_cfg_winb_128jw_128jv,
+    },
+    {
+        .jedec_id = 0x1860ef,
+        //.name="winb_128jw_128_18",
+        .cfg = &flash_cfg_winb_128jw_128jv,
+    },
+    {
+        .jedec_id = 0x1680ef,
+        //.name="winb_32jw_32_18",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x1880ef,
+        //.name="winb_128jw_128_18",
+        .cfg = &flash_cfg_winb_128jw_128jv,
+    },
+    {
+        .jedec_id = 0x134051,
+        //.name="gd_md04d_04_33",
+        .cfg = &flash_cfg_gd_md_40d,
+    },
+    {
+        .jedec_id = 0x1440c8,
+        //.name="gd_q08e_08_33",
+        .cfg = &flash_cfg_gd_q80e_q16e,
+    },
+    {
+        .jedec_id = 0x1540c8,
+        //.name="gd_q16e_16_33",
+        .cfg = &flash_cfg_gd_q80e_q16e,
+    },
+    {
+        .jedec_id = 0x1640c8,
+        //.name="gd_q32c_32_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x1740c8,
+        //.name="gd_64e_64_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x1840c8,
+        //.name="gd_q128e_128_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x1460c8,
+        //.name="gd_lq08c_08_18",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x1560c8,
+        //.name="gd_le16c_16_18",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x1660c8,
+        //.name="gd_lq32d_32_18",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x1760c8,
+        //.name="gd_lq64e_64_18",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x1860c8,
+        //.name="gd_lq128e_128_18",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x1465c8,
+        //.name="gd_wq80e_80_33",
+        .cfg = &flash_cfg_gd_wq80e_wq16e,
+    },
+    {
+        .jedec_id = 0x1565c8,
+        //.name="gd_wq16e_16_33",
+        .cfg = &flash_cfg_gd_wq80e_wq16e,
+    },
+    {
+        .jedec_id = 0x1665c8,
+        //.name="gd_wq32e_32_33",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x1320c2,
+        //.name="mx_kh40_04_33",
+        .cfg = &flash_cfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x1420c2,
+        //.name="mx_kh80_08_33",
+        .cfg = &flash_cfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x1520c2,
+        //.name="mx_kh16_16_33",
+        .cfg = &flash_cfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x3425c2,
+        //.name="mx_25v80_08_18",
+        .cfg = &flash_cfg_mxic,
+    },
+    {
+        .jedec_id = 0x3525c2,
+        //.name="mx_25u16_35_18",
+        .cfg = &flash_cfg_mxic_1635f,
+    },
+    {
+        .jedec_id = 0x3625c2,
+        //.name="mx_25v32_32_18",
+        .cfg = &flash_cfg_mxic,
+    },
+    {
+        .jedec_id = 0x3925c2,
+        //.name="mx_u25643g_256_18",
+        .cfg = &flash_cfg_mxic_25l256,
+    },
+    {
+        .jedec_id = 0x1820c2,
+        //.name="mx_25l128_128_33",
+        .cfg = &flash_cfg_mxic_1635f,
+    },
+    {
+        .jedec_id = 0x1920c2,
+        //.name="mx_25l256_256_33",
+        .cfg = &flash_cfg_mxic_25l256,
+    },
+    {
+        .jedec_id = 0x13400b,
+        //.name="xt_25f04d_04_33",
+        .cfg = &flash_cfg_xtx,
+    },
+    {
+        .jedec_id = 0x15400b,
+        //.name="xt_25f16b_16_33",
+        .cfg = &flashcfg_xtx_q80b_f16b,
+    },
+    {
+        .jedec_id = 0x16400b,
+        //.name="xt_25f32b_32_33",
+        .cfg = &flash_cfg_xtx,
+    },
+    {
+        .jedec_id = 0x17400b,
+        //.name="xt_f64b_64_33",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x18400b,
+        //.name="xt_25f128b_128_33",
+        .cfg = &flash_cfg_xtx,
+    },
+    {
+        .jedec_id = 0x14600b,
+        //.name="xt_25q80b_08_18",
+        .cfg = &flashcfg_xtx_q80b_f16b,
+    },
+    {
+        .jedec_id = 0x16600b,
+        //.name="xt_25q32b_32_18",
+        .cfg = &flash_cfg_xtx,
+    },
+    {
+        .jedec_id = 0x134068,
+        //.name="boya_q04b_04_33",
+        .cfg = &flash_cfg_boya40,
+    },
+    {
+        .jedec_id = 0x144068,
+        //.name="boya_q08b_08_33",
+        .cfg = &flash_cfg_boya,
+    },
+    {
+        .jedec_id = 0x154068,
+        //.name="boya_q16b_16_33",
+        .cfg = &flash_cfg_boya,
+    },
+    {
+        .jedec_id = 0x164068,
+        //.name="boya_q32b_32_33",
+        .cfg = &flash_cfg_boya,
+    },
+    {
+        .jedec_id = 0x174068,
+        //.name="boya_q64a_64_33",
+        .cfg = &flash_cfg_boya,
+    },
+    {
+        .jedec_id = 0x184068,
+        //.name="boya_q128a_128_33",
+        .cfg = &flash_cfg_boya,
+    },
+    {
+        .jedec_id = 0x13325e,
+        //.name="zbit_04_33",
+        .cfg = &flash_cfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x14325e,
+        //.name="zbit_08_33",
+        .cfg = &flash_cfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x15345e,
+        //.name="zb_wq16a_16_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x13605e,
+        //.name="zbit_04_33",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x14605e,
+        //.name="zbit_08_33",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x15605e,
+        //.name="zb_vq16_16_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x15405e,
+        //.name="zb_16b_16_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x16405e,
+        //.name="zb_32b_32_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x17405e,
+        //.name="zb_vq64_64_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x18405e,
+        //.name="zb_vq128_128_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x144020,
+        //.name="xm_qh80_08_33",
+        .cfg = &flash_cfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x154020,
+        //.name="xm_qh16_16_33",
+        .cfg = &flash_cfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x164020,
+        //.name="xm_qh32_32_33",
+        .cfg = &flash_cfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x174020,
+        //.name="xm_qh64_64_33",
+        .cfg = &flash_cfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x184020,
+        //.name="xm_qh128_128_33",
+        .cfg = &flash_cfg_gd_q32e_q128e,
+    },
+    {
+        .jedec_id = 0x174220,
+        //.name="xm_qw64_64_1833",
+        .cfg = &flash_cfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x1440a1,
+        //.name="fm25q80_80_33",
+        .cfg = &flash_cfg_gd_q80e_q16e,
+    },
+    {
+        .jedec_id = 0x1740a1,
+        //.name="fm25q64_64_33",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x1840a1,
+        //.name="fm25q128_128_33",
+        .cfg = &flash_cfg_winb_80ew_16fw_32jw_32fw_32fv,
+    },
+    {
+        .jedec_id = 0x146085,
+        //.name="puya_q80l/h_08_18/33",
+        .cfg = &flash_cfg_puya_q80l_q80h_q16h,
+    },
+    {
+        .jedec_id = 0x156085,
+        //.name="puya_q16h_16_33",
+        .cfg = &flash_cfg_puya_q80l_q80h_q16h,
+    },
+    {
+        .jedec_id = 0x166085,
+        //.name="puya_q32h_32_33",
+        .cfg = &flash_cfg_puya_q32h,
+    },
+    {
+        .jedec_id = 0x176085,
+        //.name="puya_q64h_64_33",
+        .cfg = &flash_cfg_puya_q32h,
+    },
+    {
+        .jedec_id = 0x186085,
+        //.name="puya_q128h_128_33",
+        .cfg = &flash_cfg_puya_q32h,
+    },
+    {
+        .jedec_id = 0x14609d,
+        //.name="issi_08_33",
+        .cfg = &flash_cfg_issi,
+    },
+    {
+        .jedec_id = 0x15609d,
+        //.name="issi_16_33",
+        .cfg = &flash_cfg_issi,
+    },
+    {
+        .jedec_id = 0x16609d,
+        //.name="issi_32_33",
+        .cfg = &flash_cfg_issi,
+    },
+    {
+        .jedec_id = 0x14709d,
+        //.name="issi_08_18",
+        .cfg = &flash_cfg_issi,
+    },
+    {
+        .jedec_id = 0x15709d,
+        //.name="issi_16_18",
+        .cfg = &flash_cfg_issi,
+    },
+    {
+        .jedec_id = 0x16709d,
+        //.name="issi_32_18",
+        .cfg = &flash_cfg_issi,
+    },
+    {
+        .jedec_id = 0x1460cd,
+        //.name="th25q80_80_33",
+        .cfg = &flash_cfg_gd_lq08c_le16c_lq32d_wq32e,
+    },
+    {
+        .jedec_id = 0x1560eb,
+        //.name="th25q16_16_33",
+        .cfg = &flash_cfg_gd_q80e_q16e,
+    },
+    {
+        .jedec_id = 0x1560ba,
+        //.name="zd25a16_16_33",
+        .cfg = &flashcfg_xtx_q80b_f16b,
+    },
+};
+
+/*@} end of group SF_CFG_Private_Variables */
+
+/** @defgroup  SF_CFG_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SF_CFG_Global_Variables */
+
+/** @defgroup  SF_CFG_Private_Fun_Declaration
+ *  @{
+ */
+
+#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)\
+ || defined(BL602) || defined(BL702) || defined(BL702L)
+/**
+ * @brief Error type definition
+ */
+typedef enum {
+    SUCCESS = 0,
+    ERROR = 1,
+    TIMEOUT = 2,
+    INVALID = 3, /* invalid arguments */
+    NORESC = 4   /* no resource or resource temperary unavailable */
+} BL_Err_Type;
+#endif
+#if defined(BL808) || defined(BL606P)
+extern BL_Err_Type GLB_Set_Flash_IO_PARM(uint8_t sel_embedded, uint8_t swap);
+#elif defined(BL616)
+extern BL_Err_Type GLB_Set_SFlash_IO_PARM(uint8_t sel_embedded, uint8_t swapIo3Io0, uint8_t swapIo2Cs);
+extern BL_Err_Type GLB_Set_SFlash2_IO_PARM(uint8_t swapIo3Io0);
+#elif defined(BL702L)
+extern BL_Err_Type GLB_Set_Embedded_FLash_IO_PARM(uint8_t reverse, uint8_t swapIo3Io0, uint8_t swapIo2Cs);
+#elif defined(BL628)
+extern void bflb_glb_set_sflash_io_parm(uint8_t sel_embedded, uint8_t swap_io3_io0, uint8_t swap_io2_cs);
+extern void bflb_glb_set_sflash2_io_parm(uint8_t swap_io3_io0);
+#elif defined(BL602)
+extern BL_Err_Type GLB_Select_Internal_Flash(void);
+extern BL_Err_Type GLB_Select_External_Flash(void);
+extern BL_Err_Type GLB_Deswap_Flash_Pin(void);
+extern BL_Err_Type GLB_Swap_Flash_Pin(void);
+#endif
+
+/*@} end of group SF_CFG_Private_Fun_Declaration */
+
+/** @defgroup  SF_CFG_Private_Functions
+ *  @{
+ */
+
+#if defined(BL702L)
+/****************************************************************************/ /**
+ * @brief  Embedded flash set input function enable
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void)
+{
+#define GLB_BASE_ADDR           0x40000000
+#define GLB_GPIO_OFFSET_ADDR    0x100
+    uint32_t regval;
+    uint32_t gpio_pin;
+    uint32_t pin_offset;
+
+    for (gpio_pin = 32; gpio_pin < 38; gpio_pin++) {
+        pin_offset = (gpio_pin >> 1) << 2;
+        regval = *(uint32_t *)(GLB_BASE_ADDR + GLB_GPIO_OFFSET_ADDR + pin_offset);
+        if (gpio_pin % 2 == 0) {
+            /* [0] is ie */
+            regval |= (1 << 0);
+        } else {
+            /* [16] is ie */
+            regval |= (1 << 16);
+        }
+        *(uint32_t *)(GLB_BASE_ADDR + GLB_GPIO_OFFSET_ADDR + pin_offset) = regval;
+    }
+}
+#elif defined(BL702) || defined(BL602)
+/****************************************************************************/ /**
+ * @brief  Init internal flash GPIO
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void)
+{
+    struct bflb_device_s *gpio;
+    uint8_t gpio_pins[6];
+    uint8_t i = 0;
+
+    gpio = bflb_device_get_by_name("gpio");
+    for (i = 0; i < sizeof(gpio_pins); i++) {
+        gpio_pins[i] = 23+i;
+        bflb_gpio_init(gpio, gpio_pins[i],
+                       BFLB_GPIO_FUNC_SF | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+    }
+}
+#endif
+
+#if defined(BL602)
+/****************************************************************************/ /**
+ * @brief  Restore GPIO17 function
+ *
+ * @param  fun: GPIO17 function
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_cfg_restore_gpio17_fun(uint8_t fun)
+{
+    struct bflb_device_s *gpio;
+
+    gpio = bflb_device_get_by_name("gpio");
+    bflb_gpio_init(gpio, GPIO_PIN_17,
+                   fun | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Init external flash GPIO according to flash GPIO config
+ *
+ * @param  ext_flash_pin: Flash GPIO config
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+    struct bflb_device_s *gpio;
+    uint8_t gpio_pins[6];
+    uint8_t i = 0;
+
+    gpio = bflb_device_get_by_name("gpio");
+    if (ext_flash_pin == 0) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK0_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS0_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA00_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA10_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA20_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA30_GPIO;
+#if defined(BL628) || defined(BL616)
+    } else if (ext_flash_pin == 1) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#elif defined(BL702)
+    } else if (ext_flash_pin == 1) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+    } else if (ext_flash_pin == 2) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK2_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS2_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA02_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA12_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA22_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA32_GPIO;
+#elif defined(BL602)
+    } else if (ext_flash_pin == 1) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#endif
+    } else {
+        return -1;
+    }
+
+    for (i = 0; i < sizeof(gpio_pins); i++) {
+        bflb_gpio_init(gpio, gpio_pins[i],
+                       BFLB_GPIO_FUNC_SF | GPIO_ALTERNATE | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_2);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Deinit external flash GPIO according to flash GPIO config
+ *
+ * @param  ext_flash_pin: Flash GPIO config
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+    struct bflb_device_s *gpio;
+    uint8_t gpio_pins[6];
+    uint8_t i = 0;
+
+    gpio = bflb_device_get_by_name("gpio");
+    if (ext_flash_pin == 0) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK0_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS0_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA00_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA10_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA20_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA30_GPIO;
+#if defined(BL628) || defined(BL616)
+    } else if (ext_flash_pin == 1) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#elif defined(BL702)
+    } else if (ext_flash_pin == 1) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+    } else if (ext_flash_pin == 2) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK2_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS2_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA02_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA12_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA22_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA32_GPIO;
+#elif defined(BL602)
+    } else if (ext_flash_pin == 1) {
+        gpio_pins[0] = BFLB_EXTFLASH_CLK1_GPIO;
+        gpio_pins[1] = BFLB_EXTFLASH_CS1_GPIO;
+        gpio_pins[2] = BFLB_EXTFLASH_DATA01_GPIO;
+        gpio_pins[3] = BFLB_EXTFLASH_DATA11_GPIO;
+        gpio_pins[4] = BFLB_EXTFLASH_DATA21_GPIO;
+        gpio_pins[5] = BFLB_EXTFLASH_DATA31_GPIO;
+#endif
+    } else {
+        return -1;
+    }
+
+    for (i = 0; i < sizeof(gpio_pins); i++) {
+        bflb_gpio_init(gpio, gpio_pins[i], GPIO_INPUT | GPIO_PULLUP | GPIO_SMT_EN | GPIO_DRV_1);
+    }
+
+    return 0;
+}
+
+/*@} end of group SF_CFG_Private_Functions */
+
+/** @defgroup  SF_CFG_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Get flash config according to flash ID
+ *
+ * @param  flash_id: Flash ID
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                                         uint8_t group, uint8_t bank)
+{
+    uint32_t i = 0;
+    uint8_t buf[sizeof(spi_flash_cfg_type) + 8];
+    uint32_t crc = 0, *p_crc;
+    uint32_t xip_offset = 0;
+
+    if (flash_id == 0) {
+        xip_offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+        bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+        bflb_xip_sflash_read_via_cache_need_lock(8 + BFLB_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank);
+        bflb_sf_ctrl_set_flash_image_offset(xip_offset, group, bank);
+
+        if (arch_memcmp(buf, BFLB_FLASH_CFG_MAGIC, 4) == 0) {
+            crc = bflb_soft_crc32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+            p_crc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type));
+
+            if (*p_crc == crc) {
+                arch_memcpy_fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+                return 0;
+            }
+        }
+    } else {
+        for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+            if (flash_infos[i].jedec_id == flash_id) {
+                arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+                return 0;
+            }
+        }
+    }
+
+    return -1;
+}
+
+#if defined(BL616) || defined(BL606P) || defined(BL808) || defined(BL702L)
+/****************************************************************************/ /**
+ * @brief  Get flash config according to flash ID patch
+ *
+ * @param  flash_id: Flash ID
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                                             uint8_t group, uint8_t bank)
+{
+    return bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Init flash GPIO according to flash Pin config
+ *
+ * @param  flash_pin_cfg: Specify flash Pin config
+ * @param  restore_default: Wether to restore default setting
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+#if defined(BL628) || defined(BL616)
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+    uint8_t sel_embedded = 0;
+    uint8_t swap_io2_cs = 0;
+    uint8_t swap_io3_io0 = 0;
+
+    if (restore_default) {
+        /* Set Default first */
+#if defined(BL628)
+        bflb_glb_set_sflash_io_parm(1, 1, 0);
+#else
+        GLB_Set_SFlash_IO_PARM(1, 1, 0);
+#endif
+        bflb_sf_ctrl_select_pad(SF_IO_EMB_SWAP_IO3IO0);
+
+        /* Default is set, so return */
+        if (flash_pin_cfg == SF_IO_EMB_SWAP_IO3IO0) {
+            return 0;
+        }
+    }
+
+    if (flash_pin_cfg & (1 << 2)) {
+        /* Init sf2 gpio */
+        bflb_sf_cfg_init_flash2_gpio(!((flash_pin_cfg >> 5) & 1));
+        sel_embedded = 0;
+    } else if (flash_pin_cfg & (1 << 3)) {
+        /* Init sf3 gpio */
+        bflb_sf_cfg_init_ext_flash_gpio(1);
+        sel_embedded = 0;
+    } else {
+        sel_embedded = 1;
+    }
+    /* if pin select dual flash, embedded is default */
+    if ((flash_pin_cfg & (1 << 4))) {
+        sel_embedded = 1;
+    }
+
+    swap_io3_io0 = ((flash_pin_cfg >> 1) & 1);
+    swap_io3_io0 = (!swap_io3_io0);
+    swap_io2_cs = ((flash_pin_cfg >> 0) & 1);
+#if defined(BL628)
+    bflb_glb_set_sflash_io_parm(sel_embedded, swap_io3_io0, swap_io2_cs);
+#else
+    GLB_Set_SFlash_IO_PARM(sel_embedded, swap_io3_io0, swap_io2_cs);
+#endif
+    bflb_sf_ctrl_select_pad(flash_pin_cfg);
+
+    return 0;
+}
+#elif defined(BL808) || defined(BL606P)
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+    uint8_t sel_embedded = 0;
+    uint8_t swap = 0;
+
+    if ((flash_pin_cfg&(1<<3)) > 0) {
+        return ERROR;
+    }
+
+    if (restore_default) {
+        /* Set Default first */
+        GLB_Set_Flash_IO_PARM(1, 1);
+        bflb_sf_ctrl_select_pad(SF_IO_EMB_SWAP_IO0_IO3);
+
+        /* Default is set, so return */
+        if (flash_pin_cfg == SF_IO_EMB_SWAP_IO0_IO3) {
+            return SUCCESS;
+        }
+    }
+
+    if (flash_pin_cfg & (1 << 2)) {
+        /* Init sf2 gpio */
+        bflb_sf_cfg_init_ext_flash_gpio(0);
+        sel_embedded = 0;
+    } else {
+        sel_embedded = 1;
+    }
+    /* if pin select dual flash, embedded is default */
+    if ((flash_pin_cfg & (1 << 4))) {
+        sel_embedded = 1;
+    }
+
+    swap = ((flash_pin_cfg >> 1) & 1);
+    swap = (!swap);
+    GLB_Set_Flash_IO_PARM(sel_embedded, swap);
+    bflb_sf_ctrl_select_pad(flash_pin_cfg);
+
+    return SUCCESS;
+}
+#elif defined(BL702L)
+/****************************************************************************/ /**
+ * @brief  Init flash GPIO according to flash Pin config
+ *
+ * @param  flash_pin_cfg: Specify flash Pin config
+ * @param  restore_default: Wether to restore default setting
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+    if (restore_default) {
+        GLB_Set_Embedded_FLash_IO_PARM(0, 0, 0);
+
+        bflb_sf_cfg_init_internal_flash_gpio();
+        bflb_sf_ctrl_select_pad(SF_CTRL_PAD1);
+
+        /* Default is set, so return */
+        if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) {
+            return 0;
+        }
+    }
+
+    if (flash_pin_cfg == SF_CTRL_SEL_EXTERNAL_FLASH) {
+        bflb_sf_cfg_init_ext_flash_gpio(0);
+        bflb_sf_ctrl_select_pad(SF_CTRL_PAD2);
+    } else {
+        if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) {
+            GLB_Set_Embedded_FLash_IO_PARM(0, 0, 0);
+        } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) {
+            GLB_Set_Embedded_FLash_IO_PARM(0, 0, 1);
+        } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) {
+            GLB_Set_Embedded_FLash_IO_PARM(0, 1, 0);
+        } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) {
+            GLB_Set_Embedded_FLash_IO_PARM(0, 1, 1);
+        } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) {
+            GLB_Set_Embedded_FLash_IO_PARM(1, 0, 0);
+        } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) {
+            GLB_Set_Embedded_FLash_IO_PARM(1, 0, 1);
+        } else if (flash_pin_cfg == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) {
+            GLB_Set_Embedded_FLash_IO_PARM(1, 1, 0);
+        } else {
+            GLB_Set_Embedded_FLash_IO_PARM(1, 1, 1);
+        }
+
+        bflb_sf_cfg_init_internal_flash_gpio();
+        bflb_sf_ctrl_select_pad(SF_CTRL_PAD1);
+    }
+
+    return 0;
+}
+#elif defined(BL702)
+/****************************************************************************/ /**
+ * @brief  Init flash GPIO according to flash Pin config
+ *
+ * @param  flash_pin_cfg: Specify flash Pin config
+ * @param  restore_default: Wether to restore default setting
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+#define GLB_BASE_ADDR                         0x40000000
+#define GLB_PARM_OFFSET_ADDR                  0x80
+#define GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR    0x88
+    uint8_t flash_cfg;
+    uint8_t swap_cfg;
+    uint32_t regval;
+
+    flash_cfg = (flash_pin_cfg >> 2) & 0x03;
+    swap_cfg = flash_pin_cfg & 0x03;
+
+    if (restore_default) {
+        /* Set Default first */
+        regval = getreg32(GLB_BASE_ADDR + GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR);
+
+        /* Bit0~5 is sf io select */
+        if ((regval&0x3F) == 0x00) {
+            bflb_sf_cfg_init_ext_flash_gpio(1);
+        }
+
+        regval = getreg32(GLB_BASE_ADDR + GLB_PARM_OFFSET_ADDR);
+        /* Bit9 is flash2 swap cs with io2 */
+        regval &= ~(1 << 9);
+        /* Bit8 is flash2 swap io0 with io3 */
+        regval &= ~(1 << 8);
+        putreg32(regval, GLB_BASE_ADDR+GLB_PARM_OFFSET_ADDR);
+
+        bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF2);
+
+        /* Default is set, so return */
+        if (flash_cfg == BFLB_FLASH_CFG_SF2_EXT_23_28 && swap_cfg == BFLB_SF2_SWAP_NONE) {
+            return 0;
+        }
+    }
+
+    if (flash_cfg == BFLB_FLASH_CFG_SF1_EXT_17_22) {
+        bflb_sf_cfg_init_ext_flash_gpio(0);
+        bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF1);
+    } else {
+        regval = getreg32(GLB_BASE_ADDR + GLB_GPIO_USE_PSRAM__IO_OFFSET_ADDR);
+
+        /* Bit0~5 is sf io select */
+        if ((regval&0x3F) == 0x00) {
+            bflb_sf_cfg_init_ext_flash_gpio(1);
+        }
+
+        regval = getreg32(GLB_BASE_ADDR + GLB_PARM_OFFSET_ADDR);
+        if (swap_cfg == BFLB_SF2_SWAP_NONE) {
+            /* Bit9 is flash2 swap cs with io2 */
+            regval &= ~(1 << 9);
+            /* Bit8 is flash2 swap io0 with io3 */
+            regval &= ~(1 << 8);
+        } else if (swap_cfg == BFLB_SF2_SWAP_CS_IO2) {
+            /* Bit9 is flash2 swap cs with io2 */
+            regval |= (1 << 9);
+            /* Bit8 is flash2 swap io0 with io3 */
+            regval &= ~(1 << 8);
+        } else if (swap_cfg == BFLB_SF2_SWAP_IO0_IO3) {
+            /* Bit9 is flash2 swap cs with io2 */
+            regval &= ~(1 << 9);
+            /* Bit8 is flash2 swap io0 with io3 */
+            regval |= (1 << 8);
+        } else {
+            /* Bit9 is flash2 swap cs with io2 */
+            regval |= (1 << 9);
+            /* Bit8 is flash2 swap io0 with io3 */
+            regval |= (1 << 8);
+        }
+        putreg32(regval, GLB_BASE_ADDR+GLB_PARM_OFFSET_ADDR);
+
+        bflb_sf_ctrl_select_pad(SF_CTRL_SEL_SF2);
+    }
+
+    return 0;
+}
+#elif defined(BL602)
+/****************************************************************************/ /**
+ * @brief  Init flash GPIO according to flash Pin config
+ *
+ * @param  flash_pin_cfg: Specify flash Pin config
+ * @param  restore_default: Wether to restore default setting
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+    if (restore_default) {
+        /* Set Default first */
+        bflb_sf_ctrl_select_pad(SF_CTRL_EMBEDDED_SEL);
+        GLB_Select_Internal_Flash();
+        GLB_Swap_Flash_Pin();
+        //SF_Cfg_Deinit_Ext_Flash_Gpio(0);
+        bflb_sf_cfg_deinit_ext_flash_gpio(1);
+        bflb_sf_cfg_init_internal_flash_gpio();
+    }
+
+    if (flash_pin_cfg > 0) {
+        /*01: deswap flash PIN
+            10: use ext flash 1(GPIO17-22)
+            11: use ext flash 0(GPIO0-2, 20-22)
+        */
+        if (flash_pin_cfg == BFLB_FLASH_CFG_DESWAP) {
+            bflb_sf_ctrl_select_pad(SF_CTRL_EMBEDDED_SEL);
+            /*DONOT Swap flash PIN*/
+            GLB_Deswap_Flash_Pin();
+        } else {
+            bflb_sf_ctrl_select_pad(flash_pin_cfg - 1);
+            GLB_Select_External_Flash();
+            bflb_sf_cfg_init_ext_flash_gpio(flash_pin_cfg - BFLB_FLASH_CFG_EXT0_17_22);
+        }
+    }
+
+    return 0;
+}
+#endif
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+/****************************************************************************/ /**
+ * @brief  Init flash2 GPIO
+ *
+ * @param  swap: Select embedded flash2 swap io3 with io0
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash2_gpio(uint8_t swap)
+{
+    bflb_sf_cfg_init_ext_flash_gpio(0);
+#if defined(BL628)
+    bflb_glb_set_sflash2_io_parm(swap);
+#elif defined(BL616)
+    GLB_Set_SFlash2_IO_PARM(swap);
+#endif
+
+    return 0;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Identify one flash
+ *
+ * @param  call_from_flash: code run at flash or ram
+ * @param  flash_pin_cfg: Bit 7: auto_scan, Bit6-0: flash GPIO config
+ * @param  restore_default: Wether restore default flash GPIO config
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+__WEAK
+uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
+                                                     spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    uint8_t auto_scan = 0;
+    uint8_t flash_pin = 0;
+    uint32_t jedec_id = 0;
+    uint32_t i = 0;
+    uint32_t offset = 0;
+    uint8_t stat = 0;
+#if defined(BL602)
+    uint8_t gpio17_fun = 0;
+#endif
+
+    auto_scan = ((flash_pin_cfg >> 7) & 1);
+    flash_pin = (flash_pin_cfg & 0x7F);
+
+    arch_memcpy_fast(p_flash_cfg, &flash_cfg_winb_16jv, sizeof(spi_flash_cfg_type));
+
+    if (call_from_flash == 1) {
+        stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+        if (stat != 0) {
+            bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB);
+            return 0;
+        }
+    }
+
+    if (auto_scan) {
+        flash_pin = 0;
+        do {
+#if defined(BL628) || defined(BL616)
+            if (!IS_SF_CTRL_PIN_SELECT(flash_pin)) {
+                flash_pin++;
+                continue;
+            }
+            if (bank == SF_CTRL_FLASH_BANK1) {
+                if (flash_pin > SF_IO_EMB_SWAP_IO2CS_AND_SF2) {
+                    jedec_id = 0;
+                    break;
+                }
+                if (flash_pin < SF_IO_EXT_SF3) {
+                    flash_pin = SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0;
+                }
+                if (flash_pin == SF_IO_EXT_SF2) {
+                    flash_pin++;
+                }
+                bflb_sf_cfg_init_flash2_gpio(!((flash_pin >> 5) & 1));
+            } else {
+                if (flash_pin > SF_IO_EXT_SF2) {
+                    jedec_id = 0;
+                    break;
+                }
+                if (flash_pin > SF_IO_EXT_SF3) {
+                    flash_pin = SF_IO_EXT_SF2;
+                }
+                bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+            }
+#elif defined(BL808) || defined(BL606P)
+            if (flash_pin > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+                jedec_id = 0;
+                break;
+            }
+            if (!IS_SF_CTRL_PIN_SELECT(flash_pin) || (flash_pin&(1<<3)) > 0) {
+                flash_pin++;
+                continue;
+            }
+            bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#elif defined(BL702L)
+            if (flash_pin > SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH) {
+                jedec_id = 0;
+                break;
+            }
+            bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#elif defined(BL702)
+            if (flash_pin > 0x0f) {
+                jedec_id = 0;
+                break;
+            }
+            bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#elif defined(BL602)
+#define GLB_BASE_ADDR             0x40000000
+#define GLB_GPIO17_OFFSET_ADDR    0x120
+            if (flash_pin > BFLB_FLASH_CFG_EXT1_0_2_20_22) {
+                jedec_id = 0;
+                break;
+            }
+
+            if (flash_pin > BFLB_FLASH_CFG_EXT0_17_22) {
+                /*flash_pin=2 has make gpio17 into jtag,but not success*/
+                bflb_sf_cfg_restore_gpio17_fun(gpio17_fun);
+            }
+
+            /* select media gpio */
+            if (flash_pin == BFLB_FLASH_CFG_EXT0_17_22) {
+                gpio17_fun = ((getreg32(GLB_BASE_ADDR + GLB_GPIO17_OFFSET_ADDR)>>24) & 0xf);
+            }
+
+            bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#endif
+            bflb_sflash_release_powerdown(p_flash_cfg);
+            bflb_sflash_reset_continue_read(p_flash_cfg);
+            bflb_sflash_disable_burst_wrap(p_flash_cfg);
+            jedec_id = 0;
+            bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id);
+            bflb_sflash_disable_burst_wrap(p_flash_cfg);
+            jedec_id = jedec_id & 0xffffff;
+            flash_pin++;
+        } while ((jedec_id & 0x00ffff) == 0 || (jedec_id & 0xffff00) == 0 || (jedec_id & 0x00ffff) == 0xffff || (jedec_id & 0xffff00) == 0xffff00);
+    } else {
+        /* select media gpio */
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+        if (bank == SF_CTRL_FLASH_BANK1) {
+            bflb_sf_cfg_init_flash2_gpio(!((flash_pin >> 5) & 1));
+        } else {
+            bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+        }
+#else
+        bflb_sf_cfg_init_flash_gpio(flash_pin, restore_default);
+#endif
+        bflb_sflash_release_powerdown(p_flash_cfg);
+        bflb_sflash_reset_continue_read(p_flash_cfg);
+        bflb_sflash_disable_burst_wrap(p_flash_cfg);
+        bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id);
+        bflb_sflash_disable_burst_wrap(p_flash_cfg);
+        jedec_id = jedec_id & 0xffffff;
+    }
+
+    for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+        if (flash_infos[i].jedec_id == jedec_id) {
+            arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+            break;
+        }
+    }
+
+    if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) {
+        if (call_from_flash == 1) {
+            bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+        }
+
+        return jedec_id;
+    } else {
+        if (call_from_flash == 1) {
+            bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+        }
+
+        return (jedec_id | BFLB_FLASH_ID_VALID_FLAG);
+    }
+}
+
+#if defined(BL616) || defined(BL606P) || defined(BL808)
+/****************************************************************************/ /**
+ * @brief  Identify one flash patch
+ *
+ * @param  call_from_flash: code run at flash or ram
+ * @param  flash_pin_cfg: Bit 7: auto_scan, Bit6-0: flash GPIO config
+ * @param  restore_default: Wether restore default flash GPIO config
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+__WEAK
+uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg,
+                  uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    return bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank);
+}
+#endif
+
+#if defined(BL628) || defined(BL616)
+/****************************************************************************/ /**
+ * @brief  SF Cfg flash init
+ *
+ * @param  sel: SF pin select
+ * @param  p_sf_ctrl_cfg: Serial flash controller configuration pointer
+ * @param  p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg,
+                                                const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+    uint8_t sel_embedded = 0;
+    uint8_t swap_io2_cs = 0;
+    uint8_t swap_io3_io0 = 0;
+
+    if (sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) {
+        return -1;
+    }
+
+    if (sel & (1 << 2)) {
+        bflb_sf_cfg_init_flash2_gpio(!((sel >> 5) & 1));
+        sel_embedded = 0;
+    } else if (sel & (1 << 3)) {
+        bflb_sf_cfg_init_ext_flash_gpio(1);
+        sel_embedded = 0;
+    } else {
+        sel_embedded = 1;
+    }
+    /* If pin select dual flash, embedded is default */
+    if ((sel & (1 << 4))) {
+        sel_embedded = 1;
+    }
+
+    swap_io3_io0 = ((sel >> 1) & 1);
+    swap_io3_io0 = (!swap_io3_io0);
+    swap_io2_cs = ((sel >> 0) & 1);
+#if defined(BL628)
+    bflb_glb_set_sflash_io_parm(sel_embedded, swap_io3_io0, swap_io2_cs);
+#else
+    GLB_Set_SFlash_IO_PARM(sel_embedded, swap_io3_io0, swap_io2_cs);
+#endif
+    bflb_sf_ctrl_select_pad(sel);
+
+    if (sel <= SF_IO_EMB_SWAP_IO2CS) {
+        /* Embedded pad1 io delay set */
+        if (p_sf_ctrl_cfg != NULL) {
+            bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+        }
+    } else if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) {
+        /* Pad2 or pad3 io delay set */
+        if (p_sf_ctrl_cfg != NULL) {
+            bflb_sf_ctrl_set_io_delay(((sel&0xf) >> 2), p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+        }
+    } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+             ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+        /* Dual flash mode, embedded pad1 and pad2 io delay set */
+        if (p_sf_ctrl_cfg != NULL) {
+            bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+        }
+        if (p_bank2_cfg != NULL) {
+            bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+        }
+    }
+
+    if (p_bank2_cfg != NULL) {
+        if (p_bank2_cfg->sbus2_select) {
+            if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+              ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+                /* Default sbus2 replace opt flash2 */
+                bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+            }
+        }
+    }
+
+    bflb_sflash_init(p_sf_ctrl_cfg, p_bank2_cfg);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Cfg system bus 2 flash init
+ *
+ * @param  sel: SF pin select
+ * @param  p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+    if (sel < SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 || sel > SF_IO_EMB_SWAP_IO2CS_AND_SF2) {
+        return -1;
+    }
+
+    /* Init flash2 gpio */
+    if (sel & (1 << 2)) {
+        bflb_sf_cfg_init_flash2_gpio(!((sel >> 5) & 1));
+    }
+
+    /* Set remap for flash2 xip mode */
+    bflb_sf_ctrl_remap_set(p_bank2_cfg->remap, p_bank2_cfg->remap_lock);
+
+    if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+      ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+        /* Dual flash mode, pad2 io delay set */
+        bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+    }
+    if (p_bank2_cfg->sbus2_select) {
+        if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+          ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+            /* Default sbus2 replace opt flash2 */
+            bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+        }
+    }
+
+    bflb_sflash_init(NULL, p_bank2_cfg);
+
+    return 0;
+}
+#elif defined(BL808) || defined(BL606P)
+/****************************************************************************/ /**
+ * @brief  SF Cfg flash init
+ *
+ * @param  sel: SF pin select
+ * @param  p_sf_ctrl_cfg: Serial flash controller configuration pointer
+ * @param  p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg,
+                                                const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+    uint8_t sel_embedded = 0;
+    uint8_t swap = 0;
+
+    if ((sel&(1<<3)) > 0) {
+        return ERROR;
+    }
+
+    if (sel & (1 << 2)) {
+        bflb_sf_cfg_init_ext_flash_gpio(0);
+        sel_embedded = 0;
+    } else {
+        sel_embedded = 1;
+    }
+    /* If pin select dual flash, embedded is default */
+    if ((sel & (1 << 4))) {
+        sel_embedded = 1;
+    }
+
+    swap = ((sel >> 1) & 1);
+    swap = (!swap);
+    GLB_Set_Flash_IO_PARM(sel_embedded, swap);
+    bflb_sf_ctrl_select_pad(sel);
+
+    if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) {
+        /* Embedded pad1 io delay set */
+        bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+    } else if (sel <= SF_IO_EXT_SF2) {
+        /* Pad2 or pad3 io delay set */
+        bflb_sf_ctrl_set_io_delay((sel >> 2), p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+    } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+        /* Dual flash mode, embedded pad1 and pad2 io delay set */
+        bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD1, p_sf_ctrl_cfg->do_delay, p_sf_ctrl_cfg->di_delay, p_sf_ctrl_cfg->oe_delay);
+        bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+    }
+
+    if (p_bank2_cfg != NULL) {
+        if (p_bank2_cfg->sbus2_select) {
+            if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+                /* Default sbus2 replace opt flash2 */
+                bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+            }
+        }
+    }
+
+    bflb_sflash_init(p_sf_ctrl_cfg, p_bank2_cfg);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Cfg system bus 2 flash init
+ *
+ * @param  sel: SF pin select
+ * @param  p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+    if (sel < SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 || sel > SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+        return ERROR;
+    }
+
+    /* Init flash2 gpio */
+    if (sel & (1 << 2)) {
+        bflb_sf_cfg_init_ext_flash_gpio(0);
+    }
+
+    /* Set remap for flash2 xip mode */
+    bflb_sf_ctrl_remap_set(p_bank2_cfg->remap, p_bank2_cfg->remap_lock);
+
+    /* Dual flash mode, pad2 io delay set */
+    bflb_sf_ctrl_set_io_delay(SF_CTRL_PAD2, p_bank2_cfg->do_delay, p_bank2_cfg->di_delay, p_bank2_cfg->oe_delay);
+
+    if (p_bank2_cfg->sbus2_select) {
+        /* Default sbus2 replace opt flash2 */
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+    }
+
+    bflb_sflash_init(NULL, p_bank2_cfg);
+
+    return SUCCESS;
+}
+#endif
+
+/*@} end of group SF_CFG_Public_Functions */
+
+/*@} end of group SF_CFG */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.h
new file mode 100755
index 0000000000..7b984cf0a4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_cfg.h
@@ -0,0 +1,215 @@
+/**
+  ******************************************************************************
+  * @file    bflb_sf_cfg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL628_SF_CFG_H__
+#define __BL628_SF_CFG_H__
+
+#include "bflb_gpio.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup  BL628_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_Public_Types
+ *  @{
+ */
+
+/*@} end of group SF_CFG_Public_Types */
+
+/** @defgroup  SF_CFG_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SF_CFG_Public_Constants */
+
+/** @defgroup  SF_CFG_Public_Macros
+ *  @{
+ */
+#define BFLB_GPIO_FUNC_SF             2
+#if defined(BL628) || defined(BL616)
+/* Flash option sf2 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO       GPIO_PIN_8
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO        GPIO_PIN_4
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO     GPIO_PIN_7
+#define BFLB_EXTFLASH_DATA10_GPIO     GPIO_PIN_5
+#define BFLB_EXTFLASH_DATA20_GPIO     GPIO_PIN_6
+#define BFLB_EXTFLASH_DATA30_GPIO     GPIO_PIN_9
+/* Flash option sf3 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK1_GPIO       GPIO_PIN_15
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS1_GPIO        GPIO_PIN_20
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA01_GPIO     GPIO_PIN_16
+#define BFLB_EXTFLASH_DATA11_GPIO     GPIO_PIN_19
+#define BFLB_EXTFLASH_DATA21_GPIO     GPIO_PIN_18
+#define BFLB_EXTFLASH_DATA31_GPIO     GPIO_PIN_14
+#elif defined(BL808) || defined(BL606P)
+/* Flash option sf2 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO       GPIO_PIN_34
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO        GPIO_PIN_35
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO     GPIO_PIN_36
+#define BFLB_EXTFLASH_DATA10_GPIO     GPIO_PIN_37
+#define BFLB_EXTFLASH_DATA20_GPIO     GPIO_PIN_38
+#define BFLB_EXTFLASH_DATA30_GPIO     GPIO_PIN_39
+#elif defined(BL702L)
+/* Flash option */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO       GPIO_PIN_27
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO        GPIO_PIN_26
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO     GPIO_PIN_23
+#define BFLB_EXTFLASH_DATA10_GPIO     GPIO_PIN_25
+#define BFLB_EXTFLASH_DATA20_GPIO     GPIO_PIN_24
+#define BFLB_EXTFLASH_DATA30_GPIO     GPIO_PIN_28
+#elif defined(BL702)
+/* Flash option 0 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK0_GPIO       GPIO_PIN_21
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS0_GPIO        GPIO_PIN_19
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA00_GPIO     GPIO_PIN_17
+#define BFLB_EXTFLASH_DATA10_GPIO     GPIO_PIN_18
+#define BFLB_EXTFLASH_DATA20_GPIO     GPIO_PIN_22
+#define BFLB_EXTFLASH_DATA30_GPIO     GPIO_PIN_20
+/* Flash option 1 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK1_GPIO       GPIO_PIN_27
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS1_GPIO        GPIO_PIN_25
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA01_GPIO     GPIO_PIN_28
+#define BFLB_EXTFLASH_DATA11_GPIO     GPIO_PIN_24
+#define BFLB_EXTFLASH_DATA21_GPIO     GPIO_PIN_23
+#define BFLB_EXTFLASH_DATA31_GPIO     GPIO_PIN_26
+/* Flash option 2 */
+/* Flash CLK */
+#define BFLB_EXTFLASH_CLK2_GPIO       GPIO_PIN_36
+/* FLASH CS */
+#define BFLB_EXTFLASH_CS2_GPIO        GPIO_PIN_35
+/* FLASH DATA */
+#define BFLB_EXTFLASH_DATA02_GPIO     GPIO_PIN_32
+#define BFLB_EXTFLASH_DATA12_GPIO     GPIO_PIN_34
+#define BFLB_EXTFLASH_DATA22_GPIO     GPIO_PIN_33
+#define BFLB_EXTFLASH_DATA32_GPIO     GPIO_PIN_37
+#define BFLB_FLASH_CFG_SF2_EXT_23_28  0
+#define BFLB_FLASH_CFG_SF2_INT_512K   1
+#define BFLB_FLASH_CFG_SF2_INT_1M     2
+#define BFLB_FLASH_CFG_SF1_EXT_17_22  3
+#define BFLB_SF2_SWAP_NONE            0
+#define BFLB_SF2_SWAP_CS_IO2          1
+#define BFLB_SF2_SWAP_IO0_IO3         2
+#define BFLB_SF2_SWAP_BOTH            3
+#elif defined(BL602)
+/*Flash option 0*/
+/*Flash CLK*/
+#define BFLB_EXTFLASH_CLK0_GPIO       GPIO_PIN_22
+/*FLASH CS*/
+#define BFLB_EXTFLASH_CS0_GPIO        GPIO_PIN_21
+/*FLASH DATA*/
+#define BFLB_EXTFLASH_DATA00_GPIO     GPIO_PIN_20
+#define BFLB_EXTFLASH_DATA10_GPIO     GPIO_PIN_19
+#define BFLB_EXTFLASH_DATA20_GPIO     GPIO_PIN_18
+#define BFLB_EXTFLASH_DATA30_GPIO     GPIO_PIN_17
+/*Flash option 1*/
+/*Flash CLK*/
+#define BFLB_EXTFLASH_CLK1_GPIO       GPIO_PIN_22
+/*FLASH CS*/
+#define BFLB_EXTFLASH_CS1_GPIO        GPIO_PIN_21
+/*FLASH DATA*/
+#define BFLB_EXTFLASH_DATA01_GPIO     GPIO_PIN_20
+#define BFLB_EXTFLASH_DATA11_GPIO     GPIO_PIN_0
+#define BFLB_EXTFLASH_DATA21_GPIO     GPIO_PIN_1
+#define BFLB_EXTFLASH_DATA31_GPIO     GPIO_PIN_2
+#define BFLB_FLASH_CFG_DESWAP         1
+#define BFLB_FLASH_CFG_EXT0_17_22     2
+#define BFLB_FLASH_CFG_EXT1_0_2_20_22 3
+#endif
+#define BFLB_FLASH_ID_VALID_FLAG      0x80000000
+#define BFLB_FLASH_ID_VALID_MASK      0x7FFFFFFF
+
+/*@} end of group SF_CFG_Public_Macros */
+
+/** @defgroup  SF_CFG_Public_Functions
+ *  @{
+ */
+int bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                        uint8_t group, uint8_t bank);
+int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                            uint8_t group, uint8_t bank);
+#if defined(BL702L) || defined(BL702)
+void bflb_sf_cfg_init_internal_flash_gpio(void);
+#endif
+#if defined(BL602)
+void bflb_sf_cfg_restore_gpio17_fun(uint8_t fun);
+#endif
+int bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+int bflb_sf_cfg_init_flash2_gpio(uint8_t swap);
+#endif
+int bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin);
+int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin);
+uint32_t bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
+                                    spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
+uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t callfromflash, uint8_t flash_pin_cfg, uint8_t restore_default,
+                                        spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg,
+                               const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
+int bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
+#else
+int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sfctrl_cfg);
+#endif
+
+/*@} end of group SF_CFG_Public_Functions */
+
+/*@} end of group SF_CFG */
+
+/*@} end of group BL628_Peripheral_Driver */
+
+#endif /* __BL628_SF_CFG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.c
new file mode 100755
index 0000000000..2996a65695
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.c
@@ -0,0 +1,2244 @@
+/**
+  ******************************************************************************
+  * @file    bl628_sf_ctrl.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bflb_sf_ctrl.h"
+#include "hardware/sf_ctrl_reg.h"
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#include 
+#else
+#include 
+#endif
+
+/** @addtogroup  BL628_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CTRL
+ *  @{
+ */
+
+/** @defgroup  SF_CTRL_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Macros */
+
+/** @defgroup  SF_CTRL_Private_Types
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Types */
+
+/** @defgroup  SF_CTRL_Private_Variables
+ *  @{
+ */
+
+#if defined(BL702) || defined(BL702L)
+#define bflb_sf_ctrl_get_aes_region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x100)
+#else
+#define bflb_sf_ctrl_get_aes_region(addr, r) (addr + SF_CTRL_AES_REGION_OFFSET + (r)*0x80)
+#endif
+#define BL_RDWD_FRM_BYTEP(p)                 ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+
+/*@} end of group SF_CTRL_Private_Variables */
+
+/** @defgroup  SF_CTRL_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Global_Variables */
+
+/** @defgroup  SF_CTRL_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Fun_Declaration */
+
+/** @defgroup  SF_CTRL_Private_Functions
+ *  @{
+ */
+
+/*@} end of group SF_CTRL_Private_Functions */
+
+/** @defgroup  SF_CTRL_Public_Functions
+ *  @{
+ */
+
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+    //return __builtin_bswap32(value);
+    uint32_t res = 0;
+
+    res = (value << 24) | (value >> 24);
+    res &= 0xFF0000FF; /* only for sure */
+    res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
+
+    return res;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable serail flash controller
+ *
+ * @param  cfg: serial flash controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+    uint32_t time_out = 0;
+
+    if (cfg == NULL) {
+        return;
+    }
+
+    reg_base = BFLB_SF_CTRL_BASE;
+    time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        time_out--;
+
+        if (time_out == 0) {
+            return;
+        }
+    }
+
+    regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+    if (cfg->en32b_addr) {
+        regval |= SF_CTRL_SF_IF_32B_ADR_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_32B_ADR_EN;
+    }
+#endif
+
+    if (cfg->clk_delay > 0) {
+        regval |= SF_CTRL_SF_IF_READ_DLY_EN;
+        regval &= ~SF_CTRL_SF_IF_READ_DLY_N_MASK;
+        regval |= ((cfg->clk_delay-1) << SF_CTRL_SF_IF_READ_DLY_N_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_READ_DLY_EN;
+    }
+
+    /* Serail out inverted, so sf ctrl send on negative edge */
+    if (cfg->clk_invert) {
+        regval |= SF_CTRL_SF_CLK_OUT_INV_SEL;
+    } else {
+        regval &= ~SF_CTRL_SF_CLK_OUT_INV_SEL;
+    }
+    if (cfg->rx_clk_invert) {
+        regval |= SF_CTRL_SF_CLK_SF_RX_INV_SEL;
+    } else {
+        regval &= ~SF_CTRL_SF_CLK_SF_RX_INV_SEL;
+    }
+    putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+
+#if defined(BL602) ||defined(BL702) || defined(BL702L)
+    bflb_sf_ctrl_set_io_delay(0, cfg->do_delay, cfg->di_delay, cfg->oe_delay);
+    bflb_sf_ctrl_set_io_delay(1, cfg->do_delay, cfg->di_delay, cfg->oe_delay);
+    bflb_sf_ctrl_set_io_delay(2, cfg->do_delay, cfg->di_delay, cfg->oe_delay);
+#endif
+
+    /* Enable AHB access sram buffer and enable sf interface */
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    regval |= SF_CTRL_SF_AHB2SRAM_EN;
+    regval |= SF_CTRL_SF_IF_EN;
+    putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+
+    bflb_sf_ctrl_set_owner(cfg->owner);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl set io delay
+ *
+ * @param  pad: Pad select
+ * @param  do_delay: DO delay select
+ * @param  di_delay: DI delay select
+ * @param  oe_delay: OE delay select
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t do_delay, uint8_t di_delay, uint8_t oe_delay)
+{
+    uint32_t offset = 0;
+    uint32_t regval = 0;
+
+    if (pad == SF_CTRL_PAD1) {
+        offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_1_OFFSET;
+    } else if (pad == SF_CTRL_PAD2) {
+        offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_2_OFFSET;
+    } else {
+        offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF_IO_DLY_3_OFFSET;
+    }
+
+    /* Set do di and oe delay */
+    regval = getreg32(offset + SF_CTRL_IO_DLY_1_OFFSET);
+    regval &= ~SF_CTRL_IO_0_DO_DLY_SEL_MASK;
+    regval |= (do_delay << SF_CTRL_IO_0_DO_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_0_DI_DLY_SEL_MASK;
+    regval |= (di_delay << SF_CTRL_IO_0_DI_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_0_OE_DLY_SEL_MASK;
+    regval |= (oe_delay << SF_CTRL_IO_0_OE_DLY_SEL_SHIFT);
+    putreg32(regval, offset + SF_CTRL_IO_DLY_1_OFFSET);
+
+    regval = getreg32(offset + SF_CTRL_IO_DLY_2_OFFSET);
+    regval &= ~SF_CTRL_IO_1_DO_DLY_SEL_MASK;
+    regval |= (do_delay << SF_CTRL_IO_1_DO_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_1_DI_DLY_SEL_MASK;
+    regval |= (di_delay << SF_CTRL_IO_1_DI_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_1_OE_DLY_SEL_MASK;
+    regval |= (oe_delay << SF_CTRL_IO_1_OE_DLY_SEL_SHIFT);
+    putreg32(regval, offset + SF_CTRL_IO_DLY_2_OFFSET);
+
+    regval = getreg32(offset + SF_CTRL_IO_DLY_3_OFFSET);
+    regval &= ~SF_CTRL_IO_2_DO_DLY_SEL_MASK;
+    regval |= (do_delay << SF_CTRL_IO_2_DO_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_2_DI_DLY_SEL_MASK;
+    regval |= (di_delay << SF_CTRL_IO_2_DI_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_2_OE_DLY_SEL_MASK;
+    regval |= (oe_delay << SF_CTRL_IO_2_OE_DLY_SEL_SHIFT);
+    putreg32(regval, offset + SF_CTRL_IO_DLY_3_OFFSET);
+
+    regval = getreg32(offset + SF_CTRL_IO_DLY_4_OFFSET);
+    regval &= ~SF_CTRL_IO_3_DO_DLY_SEL_MASK;
+    regval |= (do_delay << SF_CTRL_IO_3_DO_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_3_DI_DLY_SEL_MASK;
+    regval |= (di_delay << SF_CTRL_IO_3_DI_DLY_SEL_SHIFT);
+    regval &= ~SF_CTRL_IO_3_OE_DLY_SEL_MASK;
+    regval |= (oe_delay << SF_CTRL_IO_3_OE_DLY_SEL_SHIFT);
+    putreg32(regval, offset + SF_CTRL_IO_DLY_4_OFFSET);
+}
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+/****************************************************************************/ /**
+ * @brief  Enable serail bank2 controller
+ *
+ * @param  bank2_cfg: serial bank2 controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2_cfg)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    if (bank2_cfg == NULL) {
+        return;
+    }
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    /* Select if1 bank2 clock delay */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_12_OFFSET);
+    if (bank2_cfg->bank2_rx_clk_invert_src) {
+        regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+
+        if (bank2_cfg->bank2_rx_clk_invert_sel) {
+            regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+        } else {
+            regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+        }
+    } else {
+        regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+    }
+
+    if (bank2_cfg->bank2_delay_src) {
+        regval |= SF_CTRL_SF2_IF_READ_DLY_SRC;
+
+        if (bank2_cfg->bank2_clk_delay > 0) {
+            regval |= SF_CTRL_SF2_IF_READ_DLY_EN;
+            regval &= ~SF_CTRL_SF2_IF_READ_DLY_N_MASK;
+            regval |= ((bank2_cfg->bank2_clk_delay - 1) << SF_CTRL_SF2_IF_READ_DLY_N_SHIFT);
+        } else {
+            regval &= ~SF_CTRL_SF2_IF_READ_DLY_EN;
+        }
+    } else {
+        regval &= ~SF_CTRL_SF2_IF_READ_DLY_SRC;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_12_OFFSET);
+
+    /* Select sbus2 clock delay */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+    if (bank2_cfg->bank2_rx_clk_invert_sel) {
+        regval |= SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+    } else {
+        regval &= ~SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+    }
+
+    if (bank2_cfg->bank2_clk_delay > 0) {
+        regval |= SF_CTRL_SF_IF2_READ_DLY_EN;
+        regval &= ~SF_CTRL_SF_IF2_READ_DLY_N_MASK;
+        regval |= ((bank2_cfg->bank2_clk_delay - 1) << SF_CTRL_SF_IF2_READ_DLY_N_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF2_READ_DLY_EN;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+
+    /* Dual flash mode, enable bank2, select pad1 and pad2 */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+    regval |= SF_CTRL_SF_IF_BK2_EN;
+    regval |= SF_CTRL_SF_IF_BK2_MODE;
+    regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+    putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Flash controller sbus2 hold sram
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_hold_sram(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    /* Sbus2 hold sram */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+    regval |= SF_CTRL_SF_IF2_FN_SEL;
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Flash controller sbus2 release sram
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_release_sram(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    /* Sbus2 release sram */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+    regval &= ~SF_CTRL_SF_IF2_FN_SEL;
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get flash controller sbus2 status
+ *
+ * @param  None
+ *
+ * @return Wether if2 is enable
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_is_sbus2_enable(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+    if (regval & SF_CTRL_SF_IF2_EN) {
+        if (regval & SF_CTRL_SF_IF2_FN_SEL) {
+            return 1;
+        } else {
+            return 0;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl set sbus2 repalce
+ *
+ * @param  pad: SF pad to replace
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_replace(uint8_t pad)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    /* Sbus2 enable */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+    regval |= SF_CTRL_SF_IF2_EN;
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+
+    bflb_sf_ctrl_sbus2_hold_sram();
+
+    /* Sbus2 repalce pad */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+    regval &= ~SF_CTRL_SF_IF2_REPLACE_SF1;
+    regval &= ~SF_CTRL_SF_IF2_REPLACE_SF2;
+    regval &= ~SF_CTRL_SF_IF2_REPLACE_SF3;
+
+    if (pad == SF_CTRL_PAD1) {
+        regval |= SF_CTRL_SF_IF2_REPLACE_SF1;
+    } else if (pad == SF_CTRL_PAD2) {
+        regval |= SF_CTRL_SF_IF2_REPLACE_SF2;
+    } else {
+        regval |= SF_CTRL_SF_IF2_REPLACE_SF3;
+    }
+
+    regval &= ~SF_CTRL_SF_IF2_PAD_SEL_MASK;
+    regval |= (pad << SF_CTRL_SF_IF2_PAD_SEL_SHIFT);
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl sbus2 revoke replace
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_revoke_replace(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    bflb_sf_ctrl_sbus2_release_sram();
+
+    /* Sbus2 clear repalce pad */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+    regval &= ~SF_CTRL_SF_IF2_REPLACE_SF1;
+    regval &= ~SF_CTRL_SF_IF2_REPLACE_SF2;
+    regval &= ~SF_CTRL_SF_IF2_REPLACE_SF3;
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+
+    /* Sbus2 disable */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+    regval &= ~SF_CTRL_SF_IF2_EN;
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl set sbus2 clock delay
+ *
+ * @param  clk_delay: Sbus2 clock delay
+ * @param  rx_clk_invert: Sbus2 rx clock invert
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+
+    if (clk_delay > 0) {
+        regval |= SF_CTRL_SF_IF2_READ_DLY_EN;
+        regval &= ~SF_CTRL_SF_IF2_READ_DLY_N_MASK;
+        regval |= ((clk_delay-1) << SF_CTRL_SF_IF2_READ_DLY_N_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF2_READ_DLY_EN;
+    }
+
+    if (rx_clk_invert) {
+        regval |= SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+    } else {
+        regval &= ~SF_CTRL_SF_CLK_SF_IF2_RX_INV_SEL;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF2_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl dual flash memory remap set
+ *
+ * @param  remap: Memory remap set type
+ * @param  lock: Memory remap lock
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+    regval &= ~SF_CTRL_SF_AHB2SIF_REMAP_MASK;
+    regval |= (remap << SF_CTRL_SF_AHB2SIF_REMAP_SHIFT);
+    putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+
+    regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+    if (lock) {
+        regval |= SF_CTRL_SF_AHB2SIF_REMAP_LOCK;
+    } else {
+        regval &= ~SF_CTRL_SF_AHB2SIF_REMAP_LOCK;
+    }
+    putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+#endif
+
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+/****************************************************************************/ /**
+ * @brief  Get flash controller clock delay value
+ *
+ * @param  en32_bits_addr: Serial flash enable or disable 32-bits addr
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_32bits_addr_en(uint8_t en32_bits_addr)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+    if (en32_bits_addr) {
+        regval |= SF_CTRL_SF_IF_32B_ADR_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_32B_ADR_EN;
+    }
+    putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+#endif
+
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+/****************************************************************************/ /**
+ * @brief  Enable serail psram controller
+ *
+ * @param  psram_cfg: serial psram controller config
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+#if defined(BL702L)
+    /* Enable psram dual bank mode */
+    regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+    regval |= SF_CTRL_SF_IF_BK2_EN;
+    regval |= SF_CTRL_SF_IF_BK2_MODE;
+    putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+#endif
+
+    /* Select psram clock delay */
+    regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_12_OFFSET);
+    if (psram_cfg->psram_rx_clk_invert_src) {
+        regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+
+        if (psram_cfg->psram_rx_clk_invert_sel) {
+            regval |= SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+        } else {
+            regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SEL;
+        }
+    } else {
+        regval &= ~SF_CTRL_SF2_CLK_SF_RX_INV_SRC;
+    }
+
+    if (psram_cfg->psram_delay_src) {
+        regval |= SF_CTRL_SF2_IF_READ_DLY_SRC;
+
+        if (psram_cfg->psram_clk_delay > 0) {
+            regval |= SF_CTRL_SF2_IF_READ_DLY_EN;
+            regval &= ~SF_CTRL_SF2_IF_READ_DLY_N_MASK;
+            regval |= ((psram_cfg->psram_clk_delay - 1) << SF_CTRL_SF2_IF_READ_DLY_N_SHIFT);
+        } else {
+            regval &= ~SF_CTRL_SF2_IF_READ_DLY_EN;
+        }
+    } else {
+        regval &= ~SF_CTRL_SF2_IF_READ_DLY_SRC;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_12_OFFSET);
+
+    /* Enable AHB access sram buffer and enable sf interface */
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    regval |= SF_CTRL_SF_AHB2SRAM_EN;
+    regval |= SF_CTRL_SF_IF_EN;
+    putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+
+    bflb_sf_ctrl_set_owner(psram_cfg->owner);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get flash controller clock delay value
+ *
+ * @param  None
+ *
+ * @return Clock delay value
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_clock_delay(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+    if ((regval&SF_CTRL_SF_IF_READ_DLY_EN) == 0) {
+        return 0;
+    }
+
+    return ((regval&SF_CTRL_SF_IF_READ_DLY_N_MASK)>>SF_CTRL_SF_IF_READ_DLY_N_SHIFT) + 1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set flash controller clock delay value
+ *
+ * @param  delay: Clock delay value
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_clock_delay(uint8_t delay)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+    if (delay > 0) {
+        regval |= SF_CTRL_SF_IF_READ_DLY_EN;
+        regval &= ~SF_CTRL_SF_IF_READ_DLY_N_MASK;
+        regval |= ((delay-1) << SF_CTRL_SF_IF_READ_DLY_N_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_READ_DLY_EN;
+    }
+    putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl get wrap queue value
+ *
+ * @param  None
+ *
+ * @return Wrap queue value
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_wrap_queue_value(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+    return (regval&SF_CTRL_SF_CMDS_2_WRAP_Q) ? 1:0;
+}
+
+#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)
+/****************************************************************************/ /**
+ * @brief  SF Ctrl set cmds config
+ *
+ * @param  cmds_cfg: SF Ctrl cmds config
+ * @param  bank: bank select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t bank)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+    regval &= ~SF_CTRL_SF_IF_1_ACK_LAT_MASK;
+    regval |= ((cmds_cfg->ack_latency) << SF_CTRL_SF_IF_1_ACK_LAT_SHIFT);
+
+    if (cmds_cfg->cmds_core_en) {
+        regval |= SF_CTRL_SF_CMDS_CORE_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_CMDS_CORE_EN;
+    }
+
+    if (bank == SF_CTRL_FLASH_BANK1) {
+        if (cmds_cfg->cmds_en) {
+            regval |= SF_CTRL_SF_CMDS_2_EN;
+        } else {
+            regval &= ~SF_CTRL_SF_CMDS_2_EN;
+        }
+
+        regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT);
+        regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT);
+    } else {
+        if (cmds_cfg->cmds_en) {
+            regval |= SF_CTRL_SF_CMDS_1_EN;
+        } else {
+            regval &= ~SF_CTRL_SF_CMDS_1_EN;
+        }
+
+        regval &= ~SF_CTRL_SF_CMDS_1_WRAP_MODE_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT);
+        regval &= ~SF_CTRL_SF_CMDS_1_WRAP_LEN_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT);
+    }
+    putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+}
+#elif defined(BL702L)
+/****************************************************************************/ /**
+ * @brief  SF Ctrl set cmds config
+ *
+ * @param  cmds_cfg: SF Ctrl cmds config
+ * @param  sel: select set flash or psram cmds
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+    if (sel == SF_CTRL_SEL_FLASH) {
+        if (cmds_cfg->cmds_en) {
+            regval |= SF_CTRL_SF_CMDS_1_EN;
+        } else {
+            regval &= ~SF_CTRL_SF_CMDS_1_EN;
+        }
+        regval &= ~SF_CTRL_SF_CMDS_1_WRAP_MODE_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_1_WRAP_MODE_SHIFT);
+        regval &= ~SF_CTRL_SF_CMDS_1_WRAP_LEN_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_1_WRAP_LEN_SHIFT);
+    } else {
+        if (cmds_cfg->cmds_en) {
+            regval |= SF_CTRL_SF_CMDS_2_EN;
+        } else {
+            regval &= ~SF_CTRL_SF_CMDS_2_EN;
+        }
+        regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_mode) << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT);
+        regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK;
+        regval |= ((cmds_cfg->cmds_wrap_len) << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT);
+    }
+    putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl burst toggle select
+ *
+ * @param  burst_toggle_en: burst toggle enable or not
+ * @param  mode: SPI or QPI mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+    if (burst_toggle_en) {
+        regval |= SF_CTRL_SF_CMDS_2_BT_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_CMDS_2_BT_EN;
+    }
+    putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+
+    regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_6_OFFSET);
+    if (mode) {
+        regval |= SF_CTRL_SF_IF_3_QPI_MODE_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_3_QPI_MODE_EN;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_6_OFFSET);
+}
+#elif defined(BL702) || defined(BL602)
+/****************************************************************************/ /**
+ * @brief  SF Ctrl set cmds config
+ *
+ * @param  cmds_cfg: SF Ctrl cmds config
+ * @param  sel: select bank0 or bank1
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_3_OFFSET);
+
+    if (cmds_cfg->cmds_en) {
+        regval |= SF_CTRL_SF_CMDS_2_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_CMDS_2_EN;
+    }
+
+#if defined(BL702)
+    if (cmds_cfg->burst_toggle_en) {
+        regval |= SF_CTRL_SF_CMDS_2_BT_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_CMDS_2_BT_EN;
+    }
+#endif
+
+    regval &= ~SF_CTRL_SF_CMDS_2_WRAP_MODE_MASK;
+    regval |= (cmds_cfg->cmds_wrap_mode << SF_CTRL_SF_CMDS_2_WRAP_MODE_SHIFT);
+
+    regval &= ~SF_CTRL_SF_CMDS_2_WRAP_LEN_MASK;
+    regval |= (cmds_cfg->cmds_wrap_len << SF_CTRL_SF_CMDS_2_WRAP_LEN_SHIFT);
+    putreg32(regval, reg_base+SF_CTRL_3_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl pad select
+ *
+ * @param  sel: Pin select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_select_pad(uint8_t sel)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+#if defined(BL628) || defined(BL616)
+    if (sel <= SF_IO_EXT_SF3 || sel == SF_IO_EXT_SF2) {
+        /* Single flash mode, disable bank2 */
+        regval &= ~SF_CTRL_SF_IF_BK2_EN;
+
+        if (sel <= SF_IO_EMB_SWAP_IO2CS) {
+            /* Select embedded pad1 */
+            regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+        } else {
+            /* Select pad2 or pad3 */
+            regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+            regval |= (((sel&0xf) >> 2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+        }
+    } else if ((sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0)
+             ||(sel >= SF_IO_EMB_SWAP_IO3IO0_AND_SF2 && sel <= SF_IO_EMB_SWAP_IO2CS_AND_SF2)) {
+        /* Dual flash mode, enable bank2, select pad1 and pad2 */
+        regval |= SF_CTRL_SF_IF_BK2_EN;
+        regval |= SF_CTRL_SF_IF_BK2_MODE;
+        regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+    }
+#elif defined(BL808) || defined(BL606P)
+    if (sel <= SF_IO_EXT_SF2) {
+        /* Single flash mode, disable bank2 */
+        regval &= ~SF_CTRL_SF_IF_BK2_EN;
+
+        if (sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0) {
+            /* Select embedded pad1 */
+            regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+        } else {
+            /* Select pad2 or pad3 */
+            regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+            regval |= (((sel&0xf) >> 2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+        }
+    } else if (sel >= SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2 && sel <= SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2) {
+        /* Dual flash mode, enable bank2, select pad1 and pad2 */
+        regval |= SF_CTRL_SF_IF_BK2_EN;
+        regval |= SF_CTRL_SF_IF_BK2_MODE;
+        regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+    }
+#elif defined(BL702)
+    if (sel <= SF_CTRL_SEL_SF3) {
+        regval &= ~SF_CTRL_SF_IF_BK2_EN;
+        regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+        regval |= (sel << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+    } else if (sel >= SF_CTRL_SEL_DUAL_BANK_SF1_SF2 && sel <= SF_CTRL_SEL_DUAL_BANK_SF3_SF1) {
+        regval |= SF_CTRL_SF_IF_BK2_EN;
+        regval |= SF_CTRL_SF_IF_BK2_MODE;
+        regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+        regval |= ((sel - SF_CTRL_SEL_DUAL_BANK_SF1_SF2) << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+    } else if (sel == SF_CTRL_SEL_DUAL_CS_SF2) {
+        regval |= SF_CTRL_SF_IF_BK2_EN;
+        regval &= ~SF_CTRL_SF_IF_BK2_MODE;
+        regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+        regval |= (1 << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+    } else if (sel == SF_CTRL_SEL_DUAL_CS_SF3) {
+        regval |= SF_CTRL_SF_IF_BK2_EN;
+        regval &= ~SF_CTRL_SF_IF_BK2_MODE;
+        regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+        regval |= (2 << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+    }
+#else
+    regval &= ~SF_CTRL_SF_IF_PAD_SEL_MASK;
+    regval |= (sel << SF_CTRL_SF_IF_PAD_SEL_SHIFT);
+#endif
+    putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl select bank on system bus
+ *
+ * @param  bank: bank select type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_sbus_select_bank(uint8_t bank)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_2_OFFSET);
+    if (bank) {
+        regval |= SF_CTRL_SF_IF_0_BK_SEL;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_0_BK_SEL;
+    }
+    putreg32(regval, reg_base+SF_CTRL_2_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set flash controller owner:I/D AHB or system AHB
+ *
+ * @param  owner: owner type
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_owner(uint8_t owner)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+    uint32_t time_out = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+    time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        time_out--;
+
+        if (time_out == 0) {
+            return;
+        }
+    }
+
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    /* Set owner */
+    if (owner) {
+        regval |= SF_CTRL_SF_IF_FN_SEL;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_FN_SEL;
+    }
+
+    /* Set iahb to flash interface */
+    if (owner == SF_CTRL_OWNER_IAHB) {
+        regval |= SF_CTRL_SF_AHB2SIF_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_AHB2SIF_EN;
+    }
+    putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable flash controller
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_disable(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    regval &= ~SF_CTRL_SF_IF_EN;
+    putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable flash controller AES with big indian
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_be(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+    regval |= SF_CTRL_SF_AES_KEY_ENDIAN;
+    regval |= SF_CTRL_SF_AES_IV_ENDIAN;
+    regval |= SF_CTRL_SF_AES_DIN_ENDIAN;
+    regval |= SF_CTRL_SF_AES_DOUT_ENDIAN;
+    putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable flash controller AES with little indian
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_le(void)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_0_OFFSET);
+    regval &= ~SF_CTRL_SF_AES_KEY_ENDIAN;
+    regval &= ~SF_CTRL_SF_AES_IV_ENDIAN;
+    regval &= ~SF_CTRL_SF_AES_DIN_ENDIAN;
+    regval &= ~SF_CTRL_SF_AES_DOUT_ENDIAN;
+    putreg32(regval, reg_base+SF_CTRL_0_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Serial flash controller set AES region
+ *
+ * @param  region: region number
+ * @param  enable: enable or not
+ * @param  hw_key: hardware key or software key
+ * @param  start_addr: region start address
+ * @param  end_addr: region end address
+ * @param  locked: lock this region or not
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+#if defined (BL702) || defined(BL602)
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hw_key,
+                                          uint32_t start_addr, uint32_t end_addr, uint8_t locked)
+{
+    /* 0x30 : sf_aes_cfg */
+    #define SF_CTRL_SF_AES_REGION_CFG_END_SHIFT   (0U)
+    #define SF_CTRL_SF_AES_REGION_CFG_END_MASK    (0x3fff<cmd_buf[0], cmd_offset+SF_CTRL_IF_SAHB_1_OFFSET);
+    putreg32(cfg->cmd_buf[1], cmd_offset+SF_CTRL_IF_SAHB_2_OFFSET);
+
+    regval = getreg32(cmd_offset + SF_CTRL_IF_SAHB_0_OFFSET);
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+        regval &= ~SF_CTRL_IF_0_QPI_MODE_EN;
+    } else {
+        regval |= SF_CTRL_IF_0_QPI_MODE_EN;
+    }
+
+    regval &= ~SF_CTRL_IF_0_SPI_MODE_MASK;
+    if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+            regval |= (SF_CTRL_NIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_DO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_QO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_DIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_QIO_MODE << SF_CTRL_IF_0_SPI_MODE_SHIFT);
+    }
+
+    /* Configure cmd */
+    regval |= SF_CTRL_IF_0_CMD_EN;
+    regval &= ~SF_CTRL_IF_0_CMD_BYTE_MASK;
+
+    /* Configure address */
+    regval &= ~SF_CTRL_IF_0_ADR_BYTE_MASK;
+    if (cfg->addr_size != 0) {
+        regval |= SF_CTRL_IF_0_ADR_EN;
+        regval |= ((cfg->addr_size-1) << SF_CTRL_IF_0_ADR_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_IF_0_ADR_EN;
+    }
+
+    /* Configure dummy */
+    regval &= ~SF_CTRL_IF_0_DMY_BYTE_MASK;
+    if (cfg->dummy_clks != 0) {
+        regval |= SF_CTRL_IF_0_DMY_EN;
+        regval |= ((cfg->dummy_clks-1) << SF_CTRL_IF_0_DMY_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_IF_0_DMY_EN;
+    }
+
+    /* Configure data */
+    regval &= ~SF_CTRL_IF_0_DAT_BYTE_MASK;
+    if (cfg->nb_data != 0) {
+        regval |= SF_CTRL_IF_0_DAT_EN;
+        regval |= ((cfg->nb_data-1) << SF_CTRL_IF_0_DAT_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_IF_0_DAT_EN;
+    }
+
+    /* Set read write flag */
+    if (cfg->rw_flag) {
+        regval |= SF_CTRL_IF_0_DAT_RW;
+    } else {
+        regval &= ~SF_CTRL_IF_0_DAT_RW;
+    }
+    putreg32(regval, cmd_offset+SF_CTRL_IF_SAHB_0_OFFSET);
+
+    //switch sf_clk_sahb_sram_sel = 0
+    bflb_sf_ctrl_select_clock(1);
+
+    /* Trigger */
+    regval |= SF_CTRL_IF_0_TRIG;
+    putreg32(regval, cmd_offset+SF_CTRL_IF_SAHB_0_OFFSET);
+
+    time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+    while (bflb_sf_ctrl_get_busy_state()) {
+        time_out--;
+
+        if (time_out == 0) {
+            bflb_sf_ctrl_select_clock(0);
+            return;
+        }
+    }
+
+    //switch sf_clk_sahb_sram_sel = 0
+    bflb_sf_ctrl_select_clock(0);
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Ctrl disable iahb to flash wrap access for XTS mode
+ *
+ * @param  disable: Disable for 1 and enable for 0
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_disable_wrap_access(uint8_t disable)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    if (disable) {
+        regval &= ~SF_CTRL_SF_AHB2SIF_DISWRAP;
+    } else {
+        regval |= SF_CTRL_SF_AHB2SIF_DISWRAP;
+    }
+    putreg32(regval, reg_base+SF_CTRL_1_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Config SF controller for xip read
+ *
+ * @param  cfg: Serial flash controller command configuration pointer
+ * @param  cmd_valid: command valid or not, for continous read, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+    uint32_t time_out = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+    time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        time_out--;
+
+        if (time_out == 0) {
+            return;
+        }
+    }
+
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) {
+        return;
+    }
+
+    /* Copy command buffer */
+    putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_1_OFFSET);
+    putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_2_OFFSET);
+
+    regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_0_OFFSET);
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+        regval &= ~SF_CTRL_SF_IF_1_QPI_MODE_EN;
+    } else {
+        regval |= SF_CTRL_SF_IF_1_QPI_MODE_EN;
+    }
+
+    regval &= ~SF_CTRL_SF_IF_1_SPI_MODE_MASK;
+    if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+            regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_1_SPI_MODE_SHIFT);
+    }
+
+    regval &= ~SF_CTRL_SF_IF_1_CMD_BYTE_MASK;
+    if (cmd_valid) {
+        regval |= SF_CTRL_SF_IF_1_CMD_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_1_CMD_EN;
+    }
+
+    /* Configure address */
+    regval &= ~SF_CTRL_SF_IF_1_ADR_BYTE_MASK;
+    if (cfg->addr_size != 0) {
+        regval |= SF_CTRL_SF_IF_1_ADR_EN;
+        regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_1_ADR_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_1_ADR_EN;
+    }
+
+    /* configure dummy */
+    regval &= ~SF_CTRL_SF_IF_1_DMY_BYTE_MASK;
+    if (cfg->dummy_clks != 0) {
+        regval |= SF_CTRL_SF_IF_1_DMY_EN;
+        regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_1_DMY_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_1_DMY_EN;
+    }
+
+    /* Configure data */
+    if (cfg->nb_data != 0) {
+        regval |= SF_CTRL_SF_IF_1_DAT_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_1_DAT_EN;
+    }
+
+    /* Set read write flag */
+    if (cfg->rw_flag) {
+        regval |= SF_CTRL_SF_IF_1_DAT_RW;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_1_DAT_RW;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_0_OFFSET);
+}
+
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+/****************************************************************************/ /**
+ * @brief  Config psram controller for psram I/D cache write
+ *
+ * @param  cfg: Serial flash controller command configuration pointer
+ * @param  cmd_valid: command valid or not, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+    uint32_t time_out = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+    time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        time_out--;
+
+        if (time_out == 0) {
+            return;
+        }
+    }
+
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) {
+        return;
+    }
+
+    /* Copy command buffer */
+    putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_4_OFFSET);
+    putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_5_OFFSET);
+
+    getreg32(reg_base + SF_CTRL_SF_IF_IAHB_3_OFFSET);
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+        regval &= ~SF_CTRL_SF_IF_2_QPI_MODE_EN;
+    } else {
+        regval |= SF_CTRL_SF_IF_2_QPI_MODE_EN;
+    }
+
+    regval &= ~SF_CTRL_SF_IF_2_SPI_MODE_MASK;
+    if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+            regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_2_SPI_MODE_SHIFT);
+    }
+
+    regval &= ~SF_CTRL_SF_IF_2_CMD_BYTE_MASK;
+    if (cmd_valid) {
+        regval |= SF_CTRL_SF_IF_2_CMD_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_2_CMD_EN;
+    }
+
+    /* Configure address */
+    regval &= ~SF_CTRL_SF_IF_2_ADR_BYTE_MASK;
+    if (cfg->addr_size != 0) {
+        regval |= SF_CTRL_SF_IF_2_ADR_EN;
+        regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_2_ADR_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_2_ADR_EN;
+    }
+
+    /* configure dummy */
+    regval &= ~SF_CTRL_SF_IF_2_DMY_BYTE_MASK;
+    if (cfg->dummy_clks != 0) {
+        regval |= SF_CTRL_SF_IF_2_DMY_EN;
+        regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_2_DMY_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_2_DMY_EN;
+    }
+
+    /* Configure data */
+    if (cfg->nb_data != 0) {
+        regval |= SF_CTRL_SF_IF_2_DAT_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_2_DAT_EN;
+    }
+
+    /* Set read write flag */
+    if (cfg->rw_flag) {
+        regval |= SF_CTRL_SF_IF_2_DAT_RW;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_2_DAT_RW;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_3_OFFSET);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Config bank2 controller for flash2 I/D cache read
+ *
+ * @param  cfg: Serial flash controller command configuration pointer
+ * @param  cmd_valid: command valid or not, for continous read, cache may need no command
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+void ATTR_TCM_SECTION bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+#else
+void ATTR_TCM_SECTION bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+#endif
+{
+    uint32_t reg_base = 0;
+    uint32_t regval = 0;
+    uint32_t time_out = 0;
+
+    reg_base = BFLB_SF_CTRL_BASE;
+    time_out = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        time_out--;
+
+        if (time_out == 0) {
+            return;
+        }
+    }
+
+    regval = getreg32(reg_base + SF_CTRL_1_OFFSET);
+    if ((regval & SF_CTRL_SF_IF_FN_SEL) == 0) {
+        return;
+    }
+
+    /* Copy command buffer */
+    putreg32(cfg->cmd_buf[0], reg_base+SF_CTRL_SF_IF_IAHB_10_OFFSET);
+    putreg32(cfg->cmd_buf[1], reg_base+SF_CTRL_SF_IF_IAHB_11_OFFSET);
+
+    regval = getreg32(reg_base + SF_CTRL_SF_IF_IAHB_9_OFFSET);
+    /* Configure SPI and IO mode*/
+    if (SF_CTRL_CMD_1_LINE == cfg->cmd_mode) {
+        regval &= ~SF_CTRL_SF_IF_4_QPI_MODE_EN;
+    } else {
+        regval |= SF_CTRL_SF_IF_4_QPI_MODE_EN;
+    }
+
+    regval &= ~SF_CTRL_SF_IF_4_SPI_MODE_MASK;
+    if (SF_CTRL_ADDR_1_LINE == cfg->addr_mode) {
+        if (SF_CTRL_DATA_1_LINE == cfg->data_mode) {
+            regval |= (SF_CTRL_NIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_2_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_DO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+        } else if (SF_CTRL_DATA_4_LINES == cfg->data_mode) {
+            regval |= (SF_CTRL_QO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+        }
+    } else if (SF_CTRL_ADDR_2_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_DIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+    } else if (SF_CTRL_ADDR_4_LINES == cfg->addr_mode) {
+        regval |= (SF_CTRL_QIO_MODE << SF_CTRL_SF_IF_4_SPI_MODE_SHIFT);
+    }
+
+    regval &= ~SF_CTRL_SF_IF_4_CMD_BYTE_MASK;
+    if (cmd_valid) {
+        regval |= SF_CTRL_SF_IF_4_CMD_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_4_CMD_EN;
+    }
+
+    /* Configure address */
+    regval &= ~SF_CTRL_SF_IF_4_ADR_BYTE_MASK;
+    if (cfg->addr_size != 0) {
+        regval |= SF_CTRL_SF_IF_4_ADR_EN;
+        regval |= ((cfg->addr_size-1) << SF_CTRL_SF_IF_4_ADR_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_4_ADR_EN;
+    }
+
+    /* configure dummy */
+    regval &= ~SF_CTRL_SF_IF_4_DMY_BYTE_MASK;
+    if (cfg->dummy_clks != 0) {
+        regval |= SF_CTRL_SF_IF_4_DMY_EN;
+        regval |= ((cfg->dummy_clks-1) << SF_CTRL_SF_IF_4_DMY_BYTE_SHIFT);
+    } else {
+        regval &= ~SF_CTRL_SF_IF_4_DMY_EN;
+    }
+
+    /* Configure data */
+    if (cfg->nb_data != 0) {
+        regval |= SF_CTRL_SF_IF_4_DAT_EN;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_4_DAT_EN;
+    }
+
+    /* Set read write flag */
+    if (cfg->rw_flag) {
+        regval |= SF_CTRL_SF_IF_4_DAT_RW;
+    } else {
+        regval &= ~SF_CTRL_SF_IF_4_DAT_RW;
+    }
+    putreg32(regval, reg_base+SF_CTRL_SF_IF_IAHB_9_OFFSET);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get SF Ctrl busy state
+ *
+ * @param  None
+ *
+ * @return 1 means SF ctrl busy or 0 means SF ctrl not busy
+ *
+*******************************************************************************/
+__WEAK
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_busy_state(void)
+{
+    uint32_t regval = 0;
+    uint32_t cmd_offset = 0;
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+    if (bflb_sf_ctrl_is_sbus2_enable() == 0) {
+        cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET;
+    } else {
+        cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF2_SAHB_OFFSET;
+    }
+#else
+    cmd_offset = BFLB_SF_CTRL_BASE + SF_CTRL_IF1_SAHB_OFFSET;
+#endif
+
+    regval = getreg32(cmd_offset + SF_CTRL_IF_SAHB_0_OFFSET);
+    if (regval & SF_CTRL_IF_BUSY) {
+        return 1;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  SF Controller interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_sf_ctrl_irqhandler(void)
+{
+    /* TODO: Not implemented */
+}
+
+/*@} end of group SF_CTRL_Public_Functions */
+
+/*@} end of group SF_CTRL */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h
new file mode 100755
index 0000000000..de58709eac
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sf_ctrl.h
@@ -0,0 +1,482 @@
+/**
+  ******************************************************************************
+  * @file    bflb_sf_ctrl.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL628_SF_CTRL_H__
+#define __BL628_SF_CTRL_H__
+
+#include "bflb_core.h"
+
+/** @addtogroup  BL628_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CTRL
+ *  @{
+ */
+
+/** @defgroup  SF_CTRL_Public_Types
+ *  @{
+ */
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_SF_CTRL_BASE      ((uint32_t)0x4000B000)
+#elif defined(BL606P) || defined(BL808) || defined(BL616)
+#define BFLB_SF_CTRL_BASE      ((uint32_t)0x2000b000)
+#elif defined(BL628)
+#define BFLB_SF_CTRL_BASE      ((uint32_t)0x20082000)
+#endif
+
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define BFLB_FLASH_XIP_BASE    (0x23000000)
+#define BFLB_FLASH_XIP_END     (0x23000000 + 16 * 1024 * 1024)
+#elif defined(BL606P) || defined(BL808)
+#define BFLB_FLASH_XIP_BASE    (0x58000000)
+#define BFLB_FLASH_XIP_END     (0x58000000 + 64 * 1024 * 1024)
+#elif defined(BL616)
+#define BFLB_FLASH_XIP_BASE    (0xA0000000)
+#define BFLB_FLASH_XIP_END     (0xA0000000 + 64 * 1024 * 1024)
+#elif defined(BL628)
+#define BFLB_FLASH_XIP_BASE    (0x80000000)
+#define BFLB_FLASH_XIP_END     (0x80000000 + 64 * 1024 * 1024)
+#endif
+
+#if defined(BL628) || defined(BL616) || defined(BL808) || defined(BL606P)
+#define BFLB_SF_CTRL_SBUS2_ENABLE
+#define BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+#define BFLB_SF_CTRL_AES_XTS_ENABLE
+#endif
+#if defined(BL702) || defined(BL702L)
+#define BFLB_SF_CTRL_PSRAM_ENABLE
+#endif
+
+/**
+ *  @brief Serial flash pad type definition
+ */
+#define SF_CTRL_PAD1                                    0    /*!< SF Ctrl pad 1 */
+#define SF_CTRL_PAD2                                    1    /*!< SF Ctrl pad 2 */
+#define SF_CTRL_PAD3                                    2    /*!< SF Ctrl pad 3 */
+
+/**
+ *  @brief Serial flash config pin select type definition
+ */
+#if defined(BL628) || defined(BL616)
+#define SF_IO_EMB_SWAP_IO3IO0                           0x0  /*!< SF select embedded flash swap io3 with io0 */
+#define SF_IO_EMB_SWAP_IO3IO0_IO2CS                     0x1  /*!< SF select embedded flash swap io3 with io0 and io2 with cs */
+#define SF_IO_EMB_SWAP_NONE                             0x2  /*!< SF select embedded flash no swap */
+#define SF_IO_EMB_SWAP_IO2CS                            0x3  /*!< SF select embedded flash swap io2 with cs */
+#define SF_IO_EXT_SF2_SWAP_IO3IO0                       0x4  /*!< SF select external flash SF2 use gpio4-9 and SF2 swap io3 with io0 */
+#define SF_IO_EXT_SF3                                   0x8  /*!< SF select external flash SF3 use gpio10-15 */
+#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0       0x14 /*!< SF select embedded flash swap io3 with io0 and SF2 swap io3 with io0*/
+#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0 0x15 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 swap io3 with io0 */
+#define SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0         0x16 /*!< SF select embedded flash no swap and SF2 swap io3 with io0 */
+#define SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0        0x17 /*!< SF select embedded flash swap io2 with cs, and SF2 swap io3 with io0 */
+#define SF_IO_EXT_SF2                                   0x24 /*!< SF select external flash SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_IO3IO0_AND_SF2                   0x34 /*!< SF select embedded flash swap io3 with io0 and SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2             0x35 /*!< SF select embedded flash swap io3 with io0、io2 with cs and SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_NONE_AND_SF2                     0x36 /*!< SF select embedded flash no swap and SF2 use gpio4-9 */
+#define SF_IO_EMB_SWAP_IO2CS_AND_SF2                    0x37 /*!< SF select embedded flash swap io2 with cs and SF2 use gpio4-9 */
+#elif defined(BL808) || defined(BL606P)
+#define SF_IO_EMB_SWAP_IO0_IO3                          0x0  /*!< SF select embedded flash swap io0 with io3 */
+#define SF_IO_EMB_SWAP_DUAL_IO0_IO3                     0x1  /*!< SF select embedded flash swap dual io0 with io3 */
+#define SF_IO_EMB_SWAP_NONE                             0x2  /*!< SF select embedded flash no swap */
+#define SF_IO_EMB_SWAP_NONE_DUAL_IO0                    0x3  /*!< SF select embedded flash no swap and use dual io0 */
+#define SF_IO_EXT_SF2                                   0x4  /*!< SF select external flash SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2              0x14 /*!< SF select embedded flash swap io0 with io3 and external SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2         0x15 /*!< SF select embedded flash swap dual io0 with io3 and external SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_NONE_AND_EXT_SF2                 0x16 /*!< SF select embedded flash no swap and external SF2 use gpio34-39 */
+#define SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2        0x17 /*!< SF select embedded flash no swap, use dual io0 and external SF2 use gpio34-39 */
+#elif defined(BL702L)
+#define SF_CTRL_SEL_EXTERNAL_FLASH                      0x0  /*!< SF select sf2, flash use GPIO 23-28, external flash */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE            0x1  /*!< SF select sf1, embedded flash do not swap */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2           0x2  /*!< SF select sf1, embedded flash swap cs/io2 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3          0x3  /*!< SF select sf1, embedded flash swap io0/io3 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH            0x4  /*!< SF select sf1, embedded flash swap cs/io2 and io0/io3 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE    0x5  /*!< SF select sf1, embedded flash interface reverse and do not swap */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2   0x6  /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3  0x7  /*!< SF select sf1, embedded flash interface reverse and swap io0/io3 */
+#define SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH    0x8  /*!< SF select sf1, embedded flash interface reverse and swap cs/io2 and io0/io3 */
+#elif defined(BL702)
+#define SF_CTRL_SEL_SF1                                 0x0  /*!< SF Ctrl select sf1, flash use GPIO 17-22, no psram */
+#define SF_CTRL_SEL_SF2                                 0x1  /*!< SF Ctrl select sf2, flash use GPIO 23-28, no psram, embedded flash */
+#define SF_CTRL_SEL_SF3                                 0x2  /*!< SF Ctrl select sf3, flash use GPIO 32-37, no psram */
+#define SF_CTRL_SEL_DUAL_BANK_SF1_SF2                   0x3  /*!< SF Ctrl select sf1 and sf2, flash use GPIO 17-22, psram use GPIO 23-28 */
+#define SF_CTRL_SEL_DUAL_BANK_SF2_SF3                   0x4  /*!< SF Ctrl select sf2 and sf3, flash use GPIO 23-28, psram use GPIO 32-37 */
+#define SF_CTRL_SEL_DUAL_BANK_SF3_SF1                   0x5  /*!< SF Ctrl select sf3 and sf1, flash use GPIO 32-37, psram use GPIO 17-22 */
+#define SF_CTRL_SEL_DUAL_CS_SF2                         0x6  /*!< SF Ctrl select sf2, flash/psram use GPIO 23-28, psram use GPIO 17 as CS2 */
+#define SF_CTRL_SEL_DUAL_CS_SF3                         0x7  /*!< SF Ctrl select sf3, flash/psram use GPIO 32-37, psram use GPIO 23 as CS2 */
+#elif defined(BL602)
+#define SF_CTRL_EMBEDDED_SEL                            0x0  /*!< Embedded flash select */
+#define SF_CTRL_EXTERNAL_17TO22_SEL                     0x1  /*!< External flash select gpio 17-22 */
+#define SF_CTRL_EXTERNAL_0TO2_20TO22_SEL                0x2  /*!< External flash select gpio 0-2 and 20-22 */
+#endif
+
+
+/**
+ *  @brief Serial flash select bank control type definition
+ */
+#if defined(BL702) || defined(BL702L)
+#define SF_CTRL_SEL_FLASH                               0    /*!< SF Ctrl system bus control flash */
+#define SF_CTRL_SEL_PSRAM                               1    /*!< SF Ctrl system bus control psram */
+#else
+#define SF_CTRL_FLASH_BANK0                             0    /*!< SF Ctrl select flash bank0 */
+#define SF_CTRL_FLASH_BANK1                             1    /*!< SF Ctrl select flash bank1 */
+#endif
+
+/**
+ *  @brief Serial flash controller wrap mode type definition
+ */
+#define SF_CTRL_WRAP_MODE_0                             0    /*!< Cmds bypass wrap commands to macro, original mode */
+#define SF_CTRL_WRAP_MODE_1                             1    /*!< Cmds handle wrap commands, original mode */
+#define SF_CTRL_WRAP_MODE_2                             2    /*!< Cmds bypass wrap commands to macro, cmds force wrap16*4 splitted into two wrap8*4 */
+#define SF_CTRL_WRAP_MODE_3                             3    /*!< Cmds handle wrap commands, cmds force wrap16*4 splitted into two wrap8*4 */
+
+/**
+ *  @brief Serail flash controller wrap mode len type definition
+ */
+#define SF_CTRL_WRAP_LEN_8                              0    /*!< SF Ctrl wrap length: 8 */
+#define SF_CTRL_WRAP_LEN_16                             1    /*!< SF Ctrl wrap length: 16 */
+#define SF_CTRL_WRAP_LEN_32                             2    /*!< SF Ctrl wrap length: 32 */
+#define SF_CTRL_WRAP_LEN_64                             3    /*!< SF Ctrl wrap length: 64 */
+#define SF_CTRL_WRAP_LEN_128                            4    /*!< SF Ctrl wrap length: 128 */
+#define SF_CTRL_WRAP_LEN_256                            5    /*!< SF Ctrl wrap length: 256 */
+#define SF_CTRL_WRAP_LEN_512                            6    /*!< SF Ctrl wrap length: 512 */
+#define SF_CTRL_WRAP_LEN_1024                           7    /*!< SF Ctrl wrap length: 1024 */
+#define SF_CTRL_WRAP_LEN_2048                           8    /*!< SF Ctrl wrap length: 2048 */
+#define SF_CTRL_WRAP_LEN_4096                           9    /*!< SF Ctrl wrap length: 4096 */
+
+/**
+ *  @brief Serail flash controller memory remap type define
+ */
+#define SF_CTRL_ORIGINAL_MEMORY_MAP                     0    /*!< Remap none, use two addr map when use dual flash */
+#define SF_CTRL_REMAP_16MB                              1    /*!< Remap HADDR>16MB region to psram port HADDR[24] -> HADDR[28] */
+#define SF_CTRL_REMAP_8MB                               2    /*!< Remap HADDR>8MB region to psram port HADDR[23] -> HADDR[28] */
+#define SF_CTRL_REMAP_4MB                               3    /*!< Remap HADDR>4MB region to psram port HADDR[22] -> HADDR[28] */
+
+/**
+ *  @brief Serial flash controller select clock type definition
+ */
+#define SF_CTRL_OWNER_SAHB                              0    /*!< System AHB bus control serial flash controller */
+#define SF_CTRL_OWNER_IAHB                              1    /*!< I-Code AHB bus control serial flash controller */
+
+/**
+ *  @brief Serial flash controller select clock type definition
+ */
+#define SF_CTRL_SAHB_CLOCK                              0    /*!< Serial flash controller select default sahb clock */
+#define SF_CTRL_FLASH_CLOCK                             1    /*!< Serial flash controller select flash clock */
+
+/**
+ *  @brief Read and write type definition
+ */
+#define SF_CTRL_READ                                    0    /*!< Serail flash read command flag */
+#define SF_CTRL_WRITE                                   1    /*!< Serail flash write command flag */
+
+/**
+ *  @brief Serail flash interface IO type definition
+ */
+#define SF_CTRL_NIO_MODE                                0    /*!< Normal IO mode define */
+#define SF_CTRL_DO_MODE                                 1    /*!< Dual Output mode define */
+#define SF_CTRL_QO_MODE                                 2    /*!< Quad Output mode define */
+#define SF_CTRL_DIO_MODE                                3    /*!< Dual IO mode define */
+#define SF_CTRL_QIO_MODE                                4    /*!< Quad IO mode define */
+
+/**
+ *  @brief Serail flash controller interface mode type definition
+ */
+#define SF_CTRL_SPI_MODE                                0    /*!< SPI mode define */
+#define SF_CTRL_QPI_MODE                                1    /*!< QPI mode define */
+
+/**
+ *  @brief Serail flash controller command mode type definition
+ */
+#define SF_CTRL_CMD_1_LINE                              0    /*!< Command in one line mode */
+#define SF_CTRL_CMD_4_LINES                             1   /*!< Command in four lines mode */
+
+/**
+ *  @brief Serail flash controller address mode type definition
+ */
+#define SF_CTRL_ADDR_1_LINE                             0    /*!< Address in one line mode */
+#define SF_CTRL_ADDR_2_LINES                            1    /*!< Address in two lines mode */
+#define SF_CTRL_ADDR_4_LINES                            2    /*!< Address in four lines mode */
+
+/**
+ *  @brief Serail flash controller dummy mode type definition
+ */
+#define SF_CTRL_DUMMY_1_LINE                            0    /*!< Dummy in one line mode */
+#define SF_CTRL_DUMMY_2_LINES                           1    /*!< Dummy in two lines mode */
+#define SF_CTRL_DUMMY_4_LINES                           2    /*!< Dummy in four lines mode */
+
+/**
+ *  @brief Serail flash controller data mode type definition
+ */
+#define SF_CTRL_DATA_1_LINE                             0    /*!< Data in one line mode */
+#define SF_CTRL_DATA_2_LINES                            1    /*!< Data in two lines mode */
+#define SF_CTRL_DATA_4_LINES                            2    /*!< Data in four lines mode */
+
+/**
+ *  @brief Serail flash controller AES mode type definition
+ */
+#define SF_CTRL_AES_CTR_MODE                            0    /*!< Serail flash AES CTR mode */
+#define SF_CTRL_AES_XTS_MODE                            1    /*!< Serail flash AES XTS mode */
+
+/**
+ *  @brief Serail flash controller AES key len type definition
+ */
+#define SF_CTRL_AES_128BITS                             0    /*!< Serail flash AES key 128 bits length */
+#define SF_CTRL_AES_256BITS                             1    /*!< Serail flash AES key 256 bits length */
+#define SF_CTRL_AES_192BITS                             2    /*!< Serail flash AES key 192 bits length */
+#define SF_CTRL_AES_128BITS_DOUBLE_KEY                  3    /*!< Serail flash AES key 128 bits length double key */
+
+/**
+ *  @brief Serail flash controller configuration structure type definition
+ */
+struct sf_ctrl_cfg_type {
+    uint8_t owner;                       /*!< Sflash interface bus owner */
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+    uint8_t en32b_addr;                  /*!< Sflash enable 32-bits address */
+#endif
+    uint8_t clk_delay;                   /*!< Clock count for read due to pad delay */
+    uint8_t clk_invert;                  /*!< Clock invert */
+    uint8_t rx_clk_invert;               /*!< RX clock invert */
+    uint8_t do_delay;                    /*!< Data out delay */
+    uint8_t di_delay;                    /*!< Data in delay */
+    uint8_t oe_delay;                    /*!< Output enable delay */
+};
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+/**
+ *  @brief SF Ctrl bank2 controller configuration structure type definition
+ */
+struct sf_ctrl_bank2_cfg {
+    uint8_t sbus2_select;                /*!< Select sbus2 as 2nd flash controller */
+    uint8_t bank2_rx_clk_invert_src;     /*!< Select bank2 rx clock invert source */
+    uint8_t bank2_rx_clk_invert_sel;     /*!< Select inveted bank2 rx clock */
+    uint8_t bank2_delay_src;             /*!< Select bank2 read delay source */
+    uint8_t bank2_clk_delay;             /*!< Bank2 read delay cycle = n + 1 */
+    uint8_t do_delay;                    /*!< Data out delay */
+    uint8_t di_delay;                    /*!< Data in delay */
+    uint8_t oe_delay;                    /*!< Output enable delay */
+    uint8_t remap;                       /*!< Select dual flash memory remap set */
+    uint8_t remap_lock;                  /*!< Select memory remap lock */
+};
+#endif
+
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+/**
+ *  @brief SF Ctrl psram controller configuration structure type definition
+ */
+struct sf_ctrl_psram_cfg {
+    uint8_t owner;                   /*!< Psram interface bus owner */
+    uint8_t pad_sel;                 /*!< SF Ctrl pad select */
+    uint8_t bank_sel;                /*!< SF Ctrl bank select */
+    uint8_t psram_rx_clk_invert_src; /*!< Select psram rx clock invert source */
+    uint8_t psram_rx_clk_invert_sel; /*!< Select inveted psram rx clock */
+    uint8_t psram_delay_src;         /*!< Select psram read delay source */
+    uint8_t psram_clk_delay;         /*!< Psram read delay cycle = n + 1 */
+} ;
+#endif
+
+/**
+ *  @brief SF Ctrl cmds configuration structure type definition
+ */
+struct sf_ctrl_cmds_cfg {
+    uint8_t ack_latency;                 /*!< SF Ctrl ack latency cycles */
+    uint8_t cmds_core_en;                /*!< SF Ctrl cmds core enable */
+#if defined(BL702)
+    uint8_t burst_toggle_en;             /*!< SF Ctrl burst toggle mode enable */
+#endif
+    uint8_t cmds_en;                     /*!< SF Ctrl cmds enable */
+    uint8_t cmds_wrap_mode;              /*!< SF Ctrl cmds wrap mode */
+    uint8_t cmds_wrap_len;               /*!< SF Ctrl cmds wrap length */
+};
+
+/**
+ *  @brief Serail flash command configuration structure type definition
+ */
+struct sf_ctrl_cmd_cfg_type {
+    uint8_t rw_flag;                     /*!< Read write flag */
+    uint8_t cmd_mode;                    /*!< Command mode */
+    uint8_t addr_mode;                   /*!< Address mode */
+    uint8_t addr_size;                   /*!< Address size */
+    uint8_t dummy_clks;                  /*!< Dummy clocks */
+    uint8_t dummy_mode;                  /*!< Dummy mode */
+    uint8_t data_mode;                   /*!< Data mode */
+    uint8_t rsv[1];                      /*!< Reserved */
+    uint32_t nb_data;                    /*!< Transfer number of bytes */
+    uint32_t cmd_buf[2];                 /*!< Command buffer */
+};
+
+/*@} end of group SF_CTRL_Public_Types */
+
+/** @defgroup  SF_CTRL_Public_Macros
+ *  @{
+ */
+#if defined(BL602) || defined(BL702) || defined(BL702L)
+#define SF_CTRL_BUSY_STATE_TIMEOUT  (5 * 160 * 1000)
+#else
+#define SF_CTRL_BUSY_STATE_TIMEOUT  (5 * 320 * 1000)
+#endif
+#define SF_CTRL_NO_ADDRESS          0xFFFFFFFF
+#define NOR_FLASH_CTRL_BUF_SIZE     256
+#define NAND_FLASH_CTRL_BUF_SIZE    512
+
+#if defined(BL628) || defined(BL616)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO3IO0) ||                           \
+                                     ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS) ||                     \
+                                     ((type) == SF_IO_EMB_SWAP_NONE) ||                             \
+                                     ((type) == SF_IO_EMB_SWAP_IO2CS) ||                            \
+                                     ((type) == SF_IO_EXT_SF2_SWAP_IO3IO0) ||                       \
+                                     ((type) == SF_IO_EXT_SF3) ||                                   \
+                                     ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2_SWAP_IO3IO0) ||       \
+                                     ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2_SWAP_IO3IO0) || \
+                                     ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2_SWAP_IO3IO0) ||         \
+                                     ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2_SWAP_IO3IO0) ||        \
+                                     ((type) == SF_IO_EXT_SF2) ||                                   \
+                                     ((type) == SF_IO_EMB_SWAP_IO3IO0_AND_SF2) ||                   \
+                                     ((type) == SF_IO_EMB_SWAP_IO3IO0_IO2CS_AND_SF2) ||             \
+                                     ((type) == SF_IO_EMB_SWAP_NONE_AND_SF2) ||                     \
+                                     ((type) == SF_IO_EMB_SWAP_IO2CS_AND_SF2))
+#elif defined(BL808) || defined(BL606P)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_IO_EMB_SWAP_IO0_IO3) ||                  \
+                                     ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3) ||             \
+                                     ((type) == SF_IO_EMB_SWAP_NONE) ||                     \
+                                     ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0) ||            \
+                                     ((type) == SF_IO_EXT_SF2) ||                           \
+                                     ((type) == SF_IO_EMB_SWAP_IO0_IO3_AND_EXT_SF2) ||      \
+                                     ((type) == SF_IO_EMB_SWAP_DUAL_IO0_IO3_AND_EXT_SF2) || \
+                                     ((type) == SF_IO_EMB_SWAP_NONE_AND_EXT_SF2) ||         \
+                                     ((type) == SF_IO_EMB_SWAP_NONE_DUAL_IO0_AND_EXT_SF2))
+#elif defined(BL702L)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_EXTERNAL_FLASH) ||                     \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_NONE) ||           \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_CSIO2) ||          \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_IO0IO3) ||         \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_SWAP_BOTH) ||           \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_NONE) ||   \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_CSIO2) ||  \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_IO0IO3) || \
+                                     ((type) == SF_CTRL_SEL_INTERNAL_FLASH_REVERSE_SWAP_BOTH))
+#elif defined(BL702)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_SEL_SF1) ||               \
+                                     ((type) == SF_CTRL_SEL_SF2) ||               \
+                                     ((type) == SF_CTRL_SEL_SF3) ||               \
+                                     ((type) == SF_CTRL_SEL_DUAL_BANK_SF1_SF2) || \
+                                     ((type) == SF_CTRL_SEL_DUAL_BANK_SF2_SF3) || \
+                                     ((type) == SF_CTRL_SEL_DUAL_BANK_SF3_SF1) || \
+                                     ((type) == SF_CTRL_SEL_DUAL_CS_SF2) ||       \
+                                     ((type) == SF_CTRL_SEL_DUAL_CS_SF3))
+#elif defined(BL602)
+#define IS_SF_CTRL_PIN_SELECT(type) (((type) == SF_CTRL_EMBEDDED_SEL) ||         \
+                                     ((type) == SF_CTRL_EXTERNAL_17TO22_SEL) ||  \
+                                     ((type) == SF_CTRL_EXTERNAL_0TO2_20TO22_SEL))
+#endif
+
+/*@} end of group SF_CTRL_Public_Macros */
+
+/** @defgroup  SF_CTRL_Public_Functions
+ *  @{
+ */
+void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg);
+void bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t dodelay, uint8_t didelay, uint8_t oedelay);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2cfg);
+void bflb_sf_ctrl_sbus2_hold_sram(void);
+void bflb_sf_ctrl_sbus2_release_sram(void);
+uint8_t sf_ctrl_is_sbus2_enable(void);
+void bflb_sf_ctrl_sbus2_replace(uint8_t pad);
+void bflb_sf_ctrl_sbus2_revoke_replace(void);
+void bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert);
+void bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock);
+#endif
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+void bflb_sf_ctrl_32bits_addr_en(uint8_t en_32bit_saddr);
+#endif
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg);
+#endif
+uint8_t bflb_sf_ctrl_get_clock_delay(void);
+void bflb_sf_ctrl_set_clock_delay(uint8_t delay);
+uint8_t bflb_sf_ctrl_get_wrap_queue_value(void);
+void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel);
+#if defined(BL702L)
+void bflb_sf_ctrl_burst_toggle_set(uint8_t burst_toggle_en, uint8_t mode);
+#endif
+void bflb_sf_ctrl_select_pad(uint8_t sel);
+void bflb_sf_ctrl_sbus_select_bank(uint8_t bank);
+void bflb_sf_ctrl_set_owner(uint8_t owner);
+void bflb_sf_ctrl_disable(void);
+void bflb_sf_ctrl_aes_enable_be(void);
+void bflb_sf_ctrl_aes_enable_le(void);
+void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwkey,
+                                 uint32_t start_addr, uint32_t end_addr, uint8_t locked);
+void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+#ifdef BFLB_SF_CTRL_AES_XTS_ENABLE
+void bflb_sf_ctrl_aes_xts_set_key(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_xts_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type);
+void bflb_sf_ctrl_aes_xts_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+void bflb_sf_ctrl_aes_xts_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset);
+#endif
+void bflb_sf_ctrl_aes_set_mode(uint8_t mode);
+void bflb_sf_ctrl_aes_enable(void);
+void bflb_sf_ctrl_aes_disable(void);
+uint8_t bflb_sf_ctrl_is_aes_enable(void);
+void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank);
+uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank);
+void bflb_sf_ctrl_lock_flash_image_offset(uint8_t lock);
+void bflb_sf_ctrl_select_clock(uint8_t sahb_sram_sel);
+void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg);
+void bflb_sf_ctrl_disable_wrap_access(uint8_t disable);
+void bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+#endif
+#ifdef BFLB_SF_CTRL_PSRAM_ENABLE
+void bflb_sf_ctrl_psram_write_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+void bflb_sf_ctrl_psram_read_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid);
+#endif
+uint8_t bflb_sf_ctrl_get_busy_state(void);
+#ifndef BFLB_USE_HAL_DRIVER
+void bflb_sf_ctrl_irqhandler(void);
+#endif
+
+/*@} end of group SF_CTRL_Public_Functions */
+
+/*@} end of group SF_CTRL */
+
+/*@} end of group BL628_Peripheral_Driver */
+
+#endif /* __BL628_SF_CTRL_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.c
new file mode 100755
index 0000000000..a97f9de4d1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.c
@@ -0,0 +1,2182 @@
+/**
+  ******************************************************************************
+  * @file    bflb_sflash.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "bflb_sf_ctrl.h"
+#include "bflb_sflash.h"
+//#include "bl628_l1c.h"
+
+/** @addtogroup  BL628_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLASH
+ *  @{
+ */
+
+/** @defgroup  SFLASH_Private_Macros
+ *  @{
+ */
+
+#if defined(BL602) || defined(BL702)
+#define BFLB_SF_CTRL_BUF_BASE    ((uint32_t)0x4000B700)
+#elif defined(BL702L)
+#define BFLB_SF_CTRL_BUF_BASE    ((uint32_t)0x4000B600)
+#elif defined(BL606P) || defined(BL808) || defined(BL616)
+#define BFLB_SF_CTRL_BUF_BASE    ((uint32_t)0x2000b600)
+#elif defined(BL628)
+#define BFLB_SF_CTRL_BUF_BASE    ((uint32_t)0x20082600)
+#endif
+
+/*@} end of group SFLASH_Private_Macros */
+
+/** @defgroup  SFLASH_Private_Types
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Types */
+
+/** @defgroup  SFLASH_Private_Variables
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Variables */
+
+/** @defgroup  SFLASH_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SFLASH_Global_Variables */
+
+/** @defgroup  SFLASH_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Fun_Declaration */
+
+/** @defgroup  SFLASH_Private_Functions
+ *  @{
+ */
+
+/*@} end of group SFLASH_Private_Functions */
+
+/** @defgroup  SFLASH_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Init serial flash control interface
+ *
+ * @param  p_sf_ctrl_cfg: Serial flash controller configuration pointer
+ * @param  p_bank2_cfg: Serial flash2 controller configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg,
+                                       const struct sf_ctrl_bank2_cfg *p_bank2_cfg)
+{
+    uint8_t clk_delay = 0;
+    uint8_t rx_clk_invert = 0;
+
+    if (p_bank2_cfg != NULL) {
+        if (p_bank2_cfg->sbus2_select) {
+            if (p_bank2_cfg->bank2_delay_src) {
+                clk_delay = p_bank2_cfg->bank2_clk_delay;
+            } else {
+                if (p_sf_ctrl_cfg != NULL) {
+                    clk_delay = p_sf_ctrl_cfg->clk_delay;
+                } else {
+                    clk_delay = 1;
+                }
+            }
+
+            if (p_bank2_cfg->bank2_rx_clk_invert_src) {
+                rx_clk_invert = p_bank2_cfg->bank2_rx_clk_invert_sel;
+            } else {
+                if (p_sf_ctrl_cfg != NULL) {
+                    rx_clk_invert = p_sf_ctrl_cfg->rx_clk_invert;
+                } else {
+                    rx_clk_invert = 0;
+                }
+            }
+
+            bflb_sf_ctrl_sbus2_set_delay(clk_delay, rx_clk_invert);
+        } else {
+            bflb_sf_ctrl_sbus2_revoke_replace();
+        }
+
+        bflb_sf_ctrl_bank2_enable(p_bank2_cfg);
+    } else {
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    }
+#else
+void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg)
+{
+#endif
+
+    if (p_sf_ctrl_cfg != NULL) {
+        bflb_sf_ctrl_enable(p_sf_ctrl_cfg);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Set serial flash control interface SPI or QPI mode
+ *
+ * @param  mode: Serial flash interface mode
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_set_spi_mode(uint8_t mode)
+{
+    int stat = 0;
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read flash register
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  reg_index: register index
+ * @param  reg_value: register value pointer to store data
+ * @param  reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index,
+                                              uint8_t *reg_value, uint8_t reg_len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint32_t cnt = 0;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.cmd_buf[0] = (flash_cfg->read_reg_cmd[reg_index]) << 24;
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.nb_data = reg_len;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        arch_delay_us(1);
+        cnt++;
+
+        if (cnt > 1000) {
+            return -1;
+        }
+    }
+
+    arch_memcpy(reg_value, flash_ctrl_buf, reg_len);
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Write flash register
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  reg_index: register index
+ * @param  reg_value: register value pointer storing data
+ * @param  reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index,
+                                               uint8_t *reg_value, uint8_t reg_len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint32_t cnt = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    arch_memcpy(flash_ctrl_buf, reg_value, reg_len);
+
+    flash_cmd.cmd_buf[0] = (flash_cfg->write_reg_cmd[reg_index]) << 24;
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.nb_data = reg_len;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    /* take 40ms for tw(write status register) as default */
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(100);
+        cnt++;
+
+        if (cnt > 400) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read flash register with read command
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  read_reg_cmd: read command
+ * @param  reg_value: register value pointer to store data
+ * @param  reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg,
+                           uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint32_t cnt = 0;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.cmd_buf[0] = read_reg_cmd << 24;
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.nb_data = reg_len;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        arch_delay_us(1);
+        cnt++;
+
+        if (cnt > 1000) {
+            return -1;
+        }
+    }
+
+    arch_memcpy(reg_value, flash_ctrl_buf, reg_len);
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Write flash register with write command
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  write_reg_cmd: write command
+ * @param  reg_value: register value pointer storing data
+ * @param  reg_len: register value length
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg,
+                           uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint32_t cnt = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    arch_memcpy(flash_ctrl_buf, reg_value, reg_len);
+
+    flash_cmd.cmd_buf[0] = write_reg_cmd << 24;
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.nb_data = reg_len;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    /* take 40ms for tw(write status register) as default */
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(100);
+        cnt++;
+
+        if (cnt > 400) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Check flash busy status
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return 1 means busy or 0 means not busy
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_busy(spi_flash_cfg_type *flash_cfg)
+{
+    uint32_t stat = 0;
+    bflb_sflash_read_reg(flash_cfg, flash_cfg->busy_index, (uint8_t *)&stat, flash_cfg->busy_read_reg_len);
+
+    if ((stat & (1 << flash_cfg->busy_bit)) == 0) {
+        return 0;
+    }
+
+    return 1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable flash write function
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+    uint32_t stat = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    /* Write enable*/
+    flash_cmd.cmd_buf[0] = (flash_cfg->write_enable_cmd) << 24;
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    bflb_sflash_read_reg(flash_cfg, flash_cfg->wr_enable_index, (uint8_t *)&stat, flash_cfg->wr_enable_read_reg_len);
+
+    if ((stat & (1 << flash_cfg->wr_enable_bit)) != 0) {
+        return 0;
+    }
+
+    return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable flash flash controller QSPI interface
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg)
+{
+    uint32_t stat = 0, ret = 0;
+
+    if (flash_cfg->qe_read_reg_len == 0) {
+        ret = bflb_sflash_write_enable(flash_cfg);
+
+        if (0 != ret) {
+            return -1;
+        }
+
+        bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+        return 0;
+    }
+
+    bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+    if (flash_cfg->qe_data == 0) {
+        if ((stat & (1 << flash_cfg->qe_bit)) != 0) {
+            return 0;
+        }
+    } else {
+        if (((stat >> (flash_cfg->qe_bit & 0x08)) & 0xff) == flash_cfg->qe_data) {
+            return 0;
+        }
+    }
+
+    if (flash_cfg->qe_write_reg_len != 1) {
+        /* This is  read r0,read r1 write r0,r1 case*/
+        bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1);
+        bflb_sflash_read_reg(flash_cfg, 1, ((uint8_t *)&stat) + 1, 1);
+
+        if (flash_cfg->qe_data == 0) {
+            stat |= (1 << (flash_cfg->qe_bit + 8 * flash_cfg->qe_index));
+        } else {
+            stat = stat & (~(0xff << (8 * flash_cfg->qe_index)));
+            stat |= (flash_cfg->qe_data << (8 * flash_cfg->qe_index));
+        }
+    } else {
+        if (flash_cfg->qe_data == 0) {
+            stat |= (1 << (flash_cfg->qe_bit % 8));
+        } else {
+            stat = flash_cfg->qe_data;
+        }
+    }
+
+    ret = bflb_sflash_write_enable(flash_cfg);
+
+    if (0 != ret) {
+        return -1;
+    }
+
+    bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+    bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+    if (flash_cfg->qe_data == 0) {
+        if ((stat & (1 << flash_cfg->qe_bit)) != 0) {
+            return 0;
+        }
+    } else {
+        if (((stat >> (flash_cfg->qe_bit & 0x08)) & 0xff) == flash_cfg->qe_data) {
+            return 0;
+        }
+    }
+
+    return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable flash flash controller QSPI interface
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg)
+{
+    uint32_t stat = 0, ret = 0;
+
+    if (flash_cfg->qe_read_reg_len == 0) {
+        ret = bflb_sflash_write_enable(flash_cfg);
+
+        if (0 != ret) {
+            return -1;
+        }
+
+        bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+        return 0;
+    }
+
+    bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+    if ((stat & (1 << flash_cfg->qe_bit)) == 0) {
+        return 0;
+    }
+
+    if (flash_cfg->qe_write_reg_len != 1) {
+        /* This is  read r0,read r1 write r0,r1 case*/
+        bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1);
+        bflb_sflash_read_reg(flash_cfg, 1, ((uint8_t *)&stat) + 1, 1);
+        stat &= (~(1 << (flash_cfg->qe_bit + 8 * flash_cfg->qe_index)));
+    } else {
+        stat &= (~(1 << (flash_cfg->qe_bit % 8)));
+    }
+
+    ret = bflb_sflash_write_enable(flash_cfg);
+
+    if (0 != ret) {
+        return -1;
+    }
+
+    bflb_sflash_write_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_write_reg_len);
+    bflb_sflash_read_reg(flash_cfg, flash_cfg->qe_index, (uint8_t *)&stat, flash_cfg->qe_read_reg_len);
+
+    if ((stat & (1 << flash_cfg->qe_bit)) == 0) {
+        return 0;
+    }
+
+    return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable flash volatile register write enable
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.cmd_buf[0] = (flash_cfg->write_vreg_enable_cmd) << 24;
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash whole chip
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg)
+{
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint32_t cnt = 0;
+    uint32_t timeout = 0;
+    int stat = bflb_sflash_write_enable(flash_cfg);
+
+    if (stat != 0) {
+        return stat;
+    }
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.cmd_buf[0] = (flash_cfg->chip_erase_cmd) << 24;
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    timeout = flash_cfg->time_ce;
+
+    if ((timeout >> 15) > 0) {
+        timeout = (timeout & 0x7FFF) * 1000;
+    }
+
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > timeout * 3) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one sector
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  sector_num: flash sector number
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num)
+{
+    uint32_t cnt = 0;
+    uint8_t is_32bits_addr = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    int stat = bflb_sflash_write_enable(flash_cfg);
+
+    if (stat != 0) {
+        return stat;
+    }
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    is_32bits_addr = (flash_cfg->io_mode & 0x20);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    if (is_32bits_addr > 0) {
+        flash_cmd.addr_size++;
+        flash_cmd.cmd_buf[0] = (flash_cfg->sector_erase_cmd << 24) | ((flash_cfg->sector_size * 1024 * sector_num) >> 8);
+        flash_cmd.cmd_buf[1] = ((flash_cfg->sector_size * 1024 * sector_num) << 24);
+    } else {
+        flash_cmd.cmd_buf[0] = (flash_cfg->sector_erase_cmd << 24) | (flash_cfg->sector_size * 1024 * sector_num);
+    }
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > flash_cfg->time_e_sector * 3) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one 32K block
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  blk_num: flash 32K block number
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
+{
+    uint32_t cnt = 0;
+    uint8_t is_32bits_addr = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    int stat = bflb_sflash_write_enable(flash_cfg);
+
+    if (stat != 0) {
+        return stat;
+    }
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    is_32bits_addr = (flash_cfg->io_mode & 0x20);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    if (is_32bits_addr > 0) {
+        flash_cmd.addr_size++;
+        flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) >> 8);
+        flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) << 24);
+    } else {
+        flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blk_num);
+    }
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > flash_cfg->time_e_32k * 3) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one 64K block
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  blk_num: flash 64K block number
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
+{
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint32_t cnt = 0;
+    uint8_t is_32bits_addr = 0;
+    int stat = bflb_sflash_write_enable(flash_cfg);
+
+    if (stat != 0) {
+        return stat;
+    }
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    is_32bits_addr = (flash_cfg->io_mode & 0x20);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    if (is_32bits_addr > 0) {
+        flash_cmd.addr_size++;
+        flash_cmd.cmd_buf[0] = (flash_cfg->blk64_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK64K_SIZE * blk_num) >> 8);
+        flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK64K_SIZE * blk_num) << 24);
+    } else {
+        flash_cmd.cmd_buf[0] = (flash_cfg->blk64_erase_cmd << 24) | (BFLB_SPIFLASH_BLK64K_SIZE * blk_num);
+    }
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > flash_cfg->time_e_64k * 3) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one region
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  start_addr: start address to erase
+ * @param  end_addr: end address(include this address) to erase
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr)
+{
+    uint32_t len = 0;
+    uint32_t erase_len = 0;
+    uint8_t ret = 0;
+
+    if (start_addr > end_addr) {
+        return -1;
+    }
+
+    while (start_addr <= end_addr) {
+        len = end_addr - start_addr + 1;
+
+        if (flash_cfg->blk64_erase_cmd != BFLB_SPIFLASH_CMD_INVALID &&
+            (start_addr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 &&
+            len > (BFLB_SPIFLASH_BLK64K_SIZE - flash_cfg->sector_size * 1024)) {
+            /* 64K margin address,and length > 64K-sector size, erase one first */
+            ret = bflb_sflash_blk64_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK64K_SIZE);
+            erase_len = BFLB_SPIFLASH_BLK64K_SIZE;
+        } else if (flash_cfg->blk32_erase_cmd != BFLB_SPIFLASH_CMD_INVALID &&
+                   (start_addr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 &&
+                   len > (BFLB_SPIFLASH_BLK32K_SIZE - flash_cfg->sector_size * 1024)) {
+            /* 32K margin address,and length > 32K-sector size, erase one first */
+            ret = bflb_sflash_blk32_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK32K_SIZE);
+            erase_len = BFLB_SPIFLASH_BLK32K_SIZE;
+        } else {
+            /* Sector erase */
+            start_addr = ((start_addr) & (~(flash_cfg->sector_size * 1024 - 1)));
+            ret = bflb_sflash_sector_erase(flash_cfg, start_addr / flash_cfg->sector_size / 1024);
+            erase_len = flash_cfg->sector_size * 1024;
+        }
+
+        start_addr += erase_len;
+
+        if (ret != 0) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get flash unique ID
+ *
+ * @param  data: data pointer to store read data
+ * @param  id_len: unique ID len
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint8_t cmd = 0, dummy_clks = 0;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    dummy_clks = 4;
+    cmd = 0x4B;
+    flash_cmd.cmd_buf[0] = (cmd << 24);
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.dummy_clks = dummy_clks;
+    flash_cmd.nb_data = id_len;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return;
+        }
+    }
+
+    arch_memcpy(data, flash_ctrl_buf, id_len);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get flash jedec ID
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  data: data pointer to store read data
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint8_t cmd = 0, dummy_clks = 0;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    dummy_clks = flash_cfg->jedec_id_cmd_dmy_clk;
+    cmd = flash_cfg->jedec_id_cmd;
+    flash_cmd.cmd_buf[0] = (cmd << 24);
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.dummy_clks = dummy_clks;
+    flash_cmd.nb_data = 3;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return;
+        }
+    }
+
+    arch_memcpy(data, flash_ctrl_buf, 3);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get flash device ID
+ *
+ * @param  data: data pointer to store read data
+ * @param  is_32bits_addr: Is flash addr mode in 32-bits
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint8_t cmd = 0, dummy_clks = 0;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint32_t addr = 0x00000001;
+    uint8_t read_mode = 0xFF;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+    flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+    dummy_clks = 2;
+    cmd = 0x94;
+    flash_cmd.addr_size = 4;
+
+    if (is_32bits_addr) {
+        flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+        flash_cmd.cmd_buf[1] = (addr << 24) | (read_mode << 16);
+        flash_cmd.addr_size++;
+    } else {
+        flash_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+        flash_cmd.cmd_buf[1] = (read_mode << 24);
+    }
+
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.dummy_clks = dummy_clks;
+    flash_cmd.nb_data = 2;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return;
+        }
+    }
+
+    arch_memcpy(data, flash_ctrl_buf, 2);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set flash power down
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_powerdown(void)
+{
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint8_t cmd = 0;
+    uint32_t timeout = 0;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    cmd = 0xB9;
+    flash_cmd.cmd_buf[0] = (cmd << 24);
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return;
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Release flash power down for wake up
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg)
+{
+    uint8_t cmd = 0;
+    uint32_t timeout = 0;
+
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    cmd = flash_cfg->release_powerdown;
+    flash_cmd.cmd_buf[0] = (cmd << 24);
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+    while (bflb_sf_ctrl_get_busy_state()) {
+        timeout--;
+
+        if (timeout == 0) {
+            return;
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Sflash restore from power down
+ *
+ * @param  flash_cfg: Flash configuration pointer
+ * @param  flash_cont_read: Whether enable continuous read
+ * @param  bank: bank select type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg,
+                                                    uint8_t flash_cont_read, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t jedecid = 0;
+    uint8_t tmp[8];
+    uint8_t io_mode = flash_cfg->io_mode & 0xf;
+
+    /* Wake flash up from power down */
+    bflb_sflash_release_powerdown(flash_cfg);
+    arch_delay_us(120);
+
+    bflb_sflash_get_jedecid(flash_cfg, (uint8_t *)&jedecid);
+
+    if (SF_CTRL_QO_MODE == io_mode || SF_CTRL_QIO_MODE == io_mode) {
+        bflb_sflash_qspi_enable(flash_cfg);
+    }
+
+    if (((flash_cfg->io_mode >> 4) & 0x01) == 1) {
+        /* unwrap */
+        //L1C_Set_Wrap(0);
+    } else {
+        /* burst wrap */
+        //L1C_Set_Wrap(1);
+        /* For command that is setting register instead of send command, we need write enable */
+        bflb_sflash_write_enable(flash_cfg);
+        bflb_sflash_set_burst_wrap(flash_cfg);
+    }
+
+    if (flash_cont_read) {
+        stat = bflb_sflash_read(flash_cfg, io_mode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+        stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, 0, 0, 32, bank);
+    }
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set flash burst wrap config
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint8_t cmd = 0, dummy_clks = 0;
+    uint32_t wrap_data = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((flash_cfg->io_mode >> 4) & 0x01) == 1) {
+        /* Disable burst wrap ,just return */
+        return;
+    }
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.addr_mode = flash_cfg->burst_wrap_data_mode;
+    flash_cmd.data_mode = flash_cfg->burst_wrap_data_mode;
+    dummy_clks = flash_cfg->burst_wrap_cmd_dmy_clk;
+    cmd = flash_cfg->burst_wrap_cmd;
+    wrap_data = flash_cfg->burst_wrap_data;
+    arch_memcpy4((uint32_t *)flash_ctrl_buf, &wrap_data, 4);
+    flash_cmd.cmd_buf[0] = (cmd << 24);
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.dummy_clks = dummy_clks;
+    flash_cmd.nb_data = 1;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable flash burst wrap config
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint8_t cmd = 0, dummy_clks = 0;
+    uint32_t wrap_data = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.addr_mode = flash_cfg->de_burst_wrap_data_mode;
+    flash_cmd.data_mode = flash_cfg->de_burst_wrap_data_mode;
+    dummy_clks = flash_cfg->de_burst_wrap_cmd_dmy_clk;
+    cmd = flash_cfg->de_burst_wrap_cmd;
+    wrap_data = flash_cfg->de_burst_wrap_data;
+    arch_memcpy4((uint32_t *)flash_ctrl_buf, &wrap_data, 4);
+    flash_cmd.cmd_buf[0] = (cmd << 24);
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.dummy_clks = dummy_clks;
+    flash_cmd.nb_data = 1;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+/****************************************************************************/ /**
+ * @brief  Set flash 24-bits or 32-bits addr mode
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  en_32bits_addr: Serial flash enable or disable 32-bits addr
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg,
+                                                          uint8_t en_32bits_addr)
+{
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint8_t cmd = 0;
+
+    if ((flash_cfg->io_mode & 0x20) == 0) {
+        return -1;
+    }
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    bflb_sf_ctrl_32bits_addr_en(en_32bits_addr);
+
+    if (en_32bits_addr) {
+        cmd = flash_cfg->enter_32bits_addr_cmd;
+    } else {
+        cmd = flash_cfg->exit_32bits_addr_cmd;
+    }
+
+    flash_cmd.cmd_buf[0] = (cmd << 24);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    return 0;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software reset flash
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg)
+{
+    uint16_t cnt = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    /* Reset enable */
+    flash_cmd.cmd_buf[0] = (flash_cfg->reset_en_cmd) << 24;
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+
+    /* Wait for write done */
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(100);
+        cnt++;
+
+        if (cnt > 20) {
+            return -1;
+        }
+    }
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    /* Reset */
+    flash_cmd.cmd_buf[0] = (flash_cfg->reset_cmd) << 24;
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    arch_delay_us(50);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Reset flash continous read mode
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg)
+{
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    /* Reset continous read */
+    arch_memset(&flash_cmd.cmd_buf[0], flash_cfg->reset_c_read_cmd, 4);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = flash_cfg->reset_c_read_cmd_size;
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set xip read flash configuration in flash controller
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  io_mode: flash controller interface mode
+ * @param  cont_read: Wether enable cont read mode
+ * @param  addr: address to read/write
+ * @param  len: data length to read/write
+ * @param  bank: bank select type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode,
+                                     uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank)
+{
+    uint8_t cmd = 0, dummy_clks = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint8_t cmd_valid = 1;
+    uint8_t no_read_mode_cfg = 0;
+    uint8_t c_read_support = 0;
+    uint8_t is_32bits_addr = 0;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_IAHB);
+
+    if (SF_CTRL_NIO_MODE == io_mode) {
+        cmd = flash_cfg->fast_read_cmd;
+        dummy_clks = flash_cfg->fr_dmy_clk;
+    } else if (SF_CTRL_DO_MODE == io_mode) {
+        flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+        cmd = flash_cfg->fast_read_do_cmd;
+        dummy_clks = flash_cfg->fr_do_dmy_clk;
+    } else if (SF_CTRL_DIO_MODE == io_mode) {
+        flash_cmd.addr_mode = SF_CTRL_ADDR_2_LINES;
+        flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+        cmd = flash_cfg->fast_read_dio_cmd;
+        dummy_clks = flash_cfg->fr_dio_dmy_clk;
+    } else if (SF_CTRL_QO_MODE == io_mode) {
+        flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = flash_cfg->fast_read_qo_cmd;
+        dummy_clks = flash_cfg->fr_qo_dmy_clk;
+    } else if (SF_CTRL_QIO_MODE == io_mode) {
+        flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = flash_cfg->fast_read_qio_cmd;
+        dummy_clks = flash_cfg->fr_qio_dmy_clk;
+    } else {
+        return -1;
+    }
+
+    is_32bits_addr = (flash_cfg->io_mode & 0x20);
+    /*prepare command**/
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    if (is_32bits_addr > 0) {
+        flash_cmd.addr_size++;
+        flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+        flash_cmd.cmd_buf[1] = (addr << 24);
+    } else {
+        flash_cmd.cmd_buf[0] = (cmd << 24) | addr;
+    }
+
+    if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) {
+        no_read_mode_cfg = flash_cfg->c_read_support & 0x02;
+        c_read_support = flash_cfg->c_read_support & 0x01;
+
+        if (no_read_mode_cfg == 0) {
+            /* Read mode must be set*/
+            if (c_read_support == 0) {
+                /* Not support cont read,but we still need set read mode(winbond 80dv)*/
+                if (is_32bits_addr > 0) {
+                    flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16);
+                } else {
+                    flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+                }
+            } else {
+                /* Flash support cont read, setting depend on user parameter */
+                if (cont_read) {
+                    if (is_32bits_addr > 0) {
+                        flash_cmd.cmd_buf[0] = addr;
+                        flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+                    } else {
+                        flash_cmd.cmd_buf[0] = (addr << 8) | flash_cfg->c_read_mode;
+                    }
+
+                    cmd_valid = 0;
+                } else {
+                    if (is_32bits_addr > 0) {
+                        flash_cmd.cmd_buf[1] |= ((!flash_cfg->c_read_mode) << 16);
+                    } else {
+                        flash_cmd.cmd_buf[1] = ((!flash_cfg->c_read_mode) << 24);
+                    }
+                }
+            }
+
+            flash_cmd.addr_size++;
+        }
+    }
+
+    flash_cmd.dummy_clks = dummy_clks;
+    flash_cmd.nb_data = len;
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+    if (bank == SF_CTRL_FLASH_BANK0) {
+        bflb_sf_ctrl_xip_set(&flash_cmd, cmd_valid);
+    } else {
+        bflb_sf_ctrl_xip2_set(&flash_cmd, cmd_valid);
+    }
+#else
+    bflb_sf_ctrl_xip_set(&flash_cmd, cmd_valid);
+#endif
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable xip read from flash
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  io_mode: flash controller interface mode
+ * @param  cont_read: Wether enable cont read mode
+ * @param  bank: bank select type
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg,
+                                    uint8_t io_mode, uint8_t cont_read, uint8_t bank)
+{
+    int stat = 0;
+
+    stat = bflb_sflash_set_xip_cfg(flash_cfg, io_mode, cont_read, 0, 32, bank);
+    if (0 != stat) {
+        return stat;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable read from flash with xip
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_sflash_xip_read_disable(void)
+{
+
+}
+
+/****************************************************************************/ /**
+ * @brief  Sflash enable RCV mode to recovery for erase while power drop
+ *
+ * @param  flash_cfg: Flash configuration pointer
+ * @param  r_cmd: Read RCV register cmd
+ * @param  w_cmd: Write RCV register cmd
+ * @param  bit_pos: RCV register bit pos
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd,
+                                                uint8_t w_cmd, uint8_t bit_pos)
+{
+    int stat = 0;
+    uint32_t cnt = 0;
+    uint32_t temp_val = 0;
+
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > 20000 * 3) {
+            return -1;
+        }
+    }
+
+    stat = bflb_sflash_read_reg_with_cmd(flash_cfg, r_cmd, (uint8_t *)&temp_val, 1);
+    if (0 != stat) {
+        stat = -1;
+    }
+
+    if (((temp_val >> bit_pos) & 0x01) > 0) {
+        return 0;
+    }
+
+    temp_val |= (uint32_t)(1 << bit_pos);
+    stat = bflb_sflash_write_enable(flash_cfg);
+    if (0 != stat) {
+        stat = -1;
+    }
+
+    stat = bflb_sflash_write_reg_with_cmd(flash_cfg, w_cmd, (uint8_t *)&temp_val, 1);
+    if (0 != stat) {
+        return stat;
+    }
+
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > 20000 * 3) {
+            return -1;
+        }
+    }
+
+    stat = bflb_sflash_read_reg_with_cmd(flash_cfg, r_cmd, (uint8_t *)&temp_val, 1);
+    if (0 != stat) {
+        stat = -1;
+    }
+
+    if (((temp_val >> bit_pos) & 0x01) <= 0) {
+        return -1;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash security register one block
+ *
+ * @param  flash_cfg: Flash configuration pointer
+ * @param  p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg,
+                                                  struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+    int stat = 0;
+    uint32_t cnt = 0;
+    uint8_t cmd = 0;
+    uint8_t sec_opt_mode = 0;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+        sec_opt_mode = 1;
+
+        if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+            arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+    }
+
+    stat = bflb_sflash_write_enable(flash_cfg);
+    if (stat != 0) {
+        return stat;
+    }
+
+    if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    cmd = p_sec_reg_cfg->erase_cmd;
+    flash_cmd.cmd_buf[0] = (cmd << 24) | (p_sec_reg_cfg->block_num << 12);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > flash_cfg->time_e_sector * 3) {
+            return -1;
+        }
+    }
+
+    if (sec_opt_mode > 0) {
+        if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+            arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Program flash security register one block
+ *
+ * @param  flash_cfg: Flash configuration pointer
+ * @param  p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg,
+                                                    struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint32_t i = 0, cur_len = 0;
+    uint32_t cnt = 0;
+    int stat = 0;
+    uint8_t cmd = 0;
+    uint8_t sec_opt_mode = 0;
+    uint8_t *data = p_sec_reg_cfg->data;
+    uint32_t addr = p_sec_reg_cfg->addr;
+    uint32_t len = p_sec_reg_cfg->len;
+    uint32_t current_addr = 0;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+        sec_opt_mode = 1;
+
+        if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+            arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+    }
+
+    if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    /* Prepare command */
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.addr_size = 3;
+    cmd = p_sec_reg_cfg->program_cmd;
+
+    for (i = 0; i < len;) {
+        /* Write enable is needed for every program */
+        stat = bflb_sflash_write_enable(flash_cfg);
+
+        if (stat != 0) {
+            return stat;
+        }
+
+        /* Get current programmed length within page size */
+        cur_len = 256 - addr % 256;
+
+        if (cur_len > len - i) {
+            cur_len = len - i;
+        }
+
+        current_addr = (p_sec_reg_cfg->block_num << 12) | addr;
+
+        /* Prepare command */
+        arch_memcpy_fast(flash_ctrl_buf, data, cur_len);
+        flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr);
+        flash_cmd.nb_data = cur_len;
+
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        /* Adjust address and programmed length */
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+
+        /* Wait for write done */
+        cnt = 0;
+
+        while (bflb_sflash_busy(flash_cfg)) {
+            arch_delay_us(100);
+            cnt++;
+
+            if (cnt > flash_cfg->time_page_pgm * 20) {
+                return -1;
+            }
+        }
+    }
+
+    if (sec_opt_mode > 0) {
+        if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+            arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash security register one block
+ *
+ * @param  p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint32_t cur_len = 0, i = 0;
+    uint8_t cmd = 0;
+    uint8_t sec_opt_mode = 0;
+    uint8_t *data = p_sec_reg_cfg->data;
+    uint32_t addr = p_sec_reg_cfg->addr;
+    uint32_t len = p_sec_reg_cfg->len;
+    uint32_t current_addr = 0;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+        sec_opt_mode = 1;
+
+        if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+            arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+    }
+
+    if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    /* Prepare command */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+    flash_cmd.dummy_clks = 1;
+    cmd = p_sec_reg_cfg->read_cmd;
+
+    /* Read data */
+    for (i = 0; i < len;) {
+        current_addr = (p_sec_reg_cfg->block_num << 12) | addr;
+        /* Prepare command */
+        flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr);
+        cur_len = len - i;
+
+        if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
+            cur_len = NOR_FLASH_CTRL_BUF_SIZE;
+            flash_cmd.nb_data = cur_len;
+        } else {
+            /* Make sf_ctrl word read */
+            flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
+        }
+
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+
+        arch_memcpy_fast(data, flash_ctrl_buf, cur_len);
+
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+    }
+
+    if (sec_opt_mode > 0) {
+        if (((uint32_t)(uintptr_t)&flash_cmd) % 4 == 0) {
+            arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register
+ *
+ * @param  flash_cfg: Flash configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg)
+{
+    uint32_t ret = 0;
+    uint32_t qe_value = 0;
+    uint32_t reg_value = 0;
+    uint32_t read_value = 0;
+    uint8_t read_reg_value0 = 0;
+    uint8_t read_reg_value1 = 0;
+
+    if ((flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE) {
+        qe_value = 1;
+    }
+
+    bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&read_reg_value0, 1);
+    bflb_sflash_read_reg(flash_cfg, 1, (uint8_t *)&read_reg_value1, 1);
+    read_value = (read_reg_value0|(read_reg_value1<<8));
+    if ((read_value & (~((1<<(flash_cfg->qe_index*8+flash_cfg->qe_bit)) |
+                         (1<<(flash_cfg->busy_index*8+flash_cfg->busy_bit)) |
+                         (1<<(flash_cfg->wr_enable_index*8+flash_cfg->wr_enable_bit))))) == 0) {
+        return 0;
+    }
+
+    ret = bflb_sflash_write_enable(flash_cfg);
+    if (0 != ret) {
+        return ret;
+    }
+    if (flash_cfg->qe_write_reg_len == 2) {
+        reg_value = (qe_value<<(flash_cfg->qe_index*8+flash_cfg->qe_bit));
+        bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 2);
+    } else {
+        if (flash_cfg->qe_index == 0) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 1);
+        ret = bflb_sflash_write_enable(flash_cfg);
+        if (0 != ret) {
+            return ret;
+        }
+        if (flash_cfg->qe_index == 1) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(flash_cfg, 1, (uint8_t *)®_value, 1);
+    }
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  io_mode: flash controller interface mode
+ * @param  cont_read: Wether enable cont read mode
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode,
+                           uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint32_t cur_len = 0, i = 0;
+    uint8_t cmd = 0, dummy_clks = 0;
+    uint32_t timeout = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint8_t no_read_mode_cfg = 0;
+    uint8_t c_read_support = 0;
+    uint8_t is_32bits_addr = 0;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == io_mode) {
+        cmd = flash_cfg->fast_read_cmd;
+        dummy_clks = flash_cfg->fr_dmy_clk;
+    } else if (SF_CTRL_DO_MODE == io_mode) {
+        flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+        cmd = flash_cfg->fast_read_do_cmd;
+        dummy_clks = flash_cfg->fr_do_dmy_clk;
+    } else if (SF_CTRL_DIO_MODE == io_mode) {
+        flash_cmd.addr_mode = SF_CTRL_ADDR_2_LINES;
+        flash_cmd.data_mode = SF_CTRL_DATA_2_LINES;
+        cmd = flash_cfg->fast_read_dio_cmd;
+        dummy_clks = flash_cfg->fr_dio_dmy_clk;
+    } else if (SF_CTRL_QO_MODE == io_mode) {
+        flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = flash_cfg->fast_read_qo_cmd;
+        dummy_clks = flash_cfg->fr_qo_dmy_clk;
+    } else if (SF_CTRL_QIO_MODE == io_mode) {
+        flash_cmd.addr_mode = SF_CTRL_ADDR_4_LINES;
+        flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = flash_cfg->fast_read_qio_cmd;
+        dummy_clks = flash_cfg->fr_qio_dmy_clk;
+    } else {
+        return -1;
+    }
+
+    is_32bits_addr = (flash_cfg->io_mode & 0x20);
+    /* Prepare command */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    if (is_32bits_addr > 0) {
+        flash_cmd.addr_size++;
+    }
+
+    if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) {
+        no_read_mode_cfg = flash_cfg->c_read_support & 0x02;
+        c_read_support = flash_cfg->c_read_support & 0x01;
+
+        if (no_read_mode_cfg == 0) {
+            /* Read mode must be set*/
+            if (c_read_support == 0) {
+                /* Not support cont read,but we still need set read mode(winbond 80dv)*/
+                if (is_32bits_addr > 0) {
+                    flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16);
+                } else {
+                    flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+                }
+            } else {
+                /* Flash support cont read, setting depend on user parameter */
+                if (cont_read) {
+                    if (is_32bits_addr > 0) {
+                        flash_cmd.cmd_buf[1] |= (flash_cfg->c_read_mode << 16);
+                    } else {
+                        flash_cmd.cmd_buf[1] = (flash_cfg->c_read_mode << 24);
+                    }
+                } else {
+                    if (is_32bits_addr > 0) {
+                        flash_cmd.cmd_buf[1] |= ((!flash_cfg->c_read_mode) << 16);
+                    } else {
+                        flash_cmd.cmd_buf[1] = ((!flash_cfg->c_read_mode) << 24);
+                    }
+                }
+            }
+
+            flash_cmd.addr_size++;
+        }
+    }
+
+    flash_cmd.dummy_clks = dummy_clks;
+
+    /* Read data */
+    for (i = 0; i < len;) {
+        /* Prepare command */
+        if (is_32bits_addr > 0) {
+            flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+            flash_cmd.cmd_buf[1] |= (addr << 24);
+        } else {
+            flash_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+        }
+
+        cur_len = len - i;
+
+        if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
+            cur_len = NOR_FLASH_CTRL_BUF_SIZE;
+            flash_cmd.nb_data = cur_len;
+        } else {
+            /* Make sf_ctrl word read */
+            flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
+        }
+
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        timeout = SF_CTRL_BUSY_STATE_TIMEOUT;
+
+        while (bflb_sf_ctrl_get_busy_state()) {
+            timeout--;
+
+            if (timeout == 0) {
+                return -2;
+            }
+        }
+
+        arch_memcpy_fast(data, flash_ctrl_buf, cur_len);
+
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Program flash one region
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  io_mode: progran mode:SPI mode or QPI mode
+ * @param  addr: start address to be programed
+ * @param  data: data pointer to be programed
+ * @param  len: data length to be programed
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode,
+                                                 uint32_t addr, uint8_t *data, uint32_t len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)BFLB_SF_CTRL_BUF_BASE;
+    uint32_t i = 0, cur_len = 0;
+    uint32_t cnt = 0;
+    int stat = 0;
+    uint8_t is_32bits_addr = 0;
+    uint8_t cmd = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        arch_memset4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        arch_memset(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    if (SF_CTRL_NIO_MODE == io_mode || SF_CTRL_DO_MODE == io_mode || SF_CTRL_DIO_MODE == io_mode) {
+        cmd = flash_cfg->page_program_cmd;
+    } else if (SF_CTRL_QIO_MODE == io_mode || SF_CTRL_QO_MODE == io_mode) {
+        flash_cmd.addr_mode = flash_cfg->qpp_addr_mode;
+        flash_cmd.data_mode = SF_CTRL_DATA_4_LINES;
+        cmd = flash_cfg->qpage_program_cmd;
+    } else {
+        return -1;
+    }
+
+    is_32bits_addr = (flash_cfg->io_mode & 0x20);
+    /* Prepare command */
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.addr_size = 3;
+
+    if (is_32bits_addr > 0) {
+        flash_cmd.addr_size++;
+    }
+
+    for (i = 0; i < len;) {
+        /* Write enable is needed for every program */
+        stat = bflb_sflash_write_enable(flash_cfg);
+
+        if (stat != 0) {
+            return stat;
+        }
+
+        /* Get current programmed length within page size */
+        cur_len = flash_cfg->page_size - addr % flash_cfg->page_size;
+
+        if (cur_len > len - i) {
+            cur_len = len - i;
+        }
+
+        /* Prepare command */
+        arch_memcpy_fast(flash_ctrl_buf, data, cur_len);
+
+        if (is_32bits_addr > 0) {
+            flash_cmd.cmd_buf[0] = (cmd << 24) | (addr >> 8);
+            flash_cmd.cmd_buf[1] = (addr << 24);
+        } else {
+            flash_cmd.cmd_buf[0] = (cmd << 24) | (addr);
+        }
+
+        flash_cmd.nb_data = cur_len;
+
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        /* Adjust address and programmed length */
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+
+        /* Wait for write done */
+        cnt = 0;
+
+        while (bflb_sflash_busy(flash_cfg)) {
+            arch_delay_us(100);
+            cnt++;
+
+            if (cnt > flash_cfg->time_page_pgm * 20) {
+                return -1;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/*@} end of group SFLASH_Public_Functions */
+
+/*@} end of group SFLASH */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.h
new file mode 100755
index 0000000000..339f37900d
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_sflash.h
@@ -0,0 +1,226 @@
+/**
+  ******************************************************************************
+  * @file    bl628_sflah.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL628_SFLAH_H__
+#define __BL628_SFLAH_H__
+
+#include "bflb_sf_ctrl.h"
+
+/** @addtogroup  BL628_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLAH
+ *  @{
+ */
+
+/** @defgroup  SFLAH_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Serial flash configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t  io_mode;                   /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */
+    uint8_t  c_read_support;            /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
+    uint8_t  clk_delay;                 /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
+    uint8_t  clk_invert;                /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
+    uint8_t  reset_en_cmd;              /*!< Flash enable reset command */
+    uint8_t  reset_cmd;                 /*!< Flash reset command */
+    uint8_t  reset_c_read_cmd;          /*!< Flash reset continuous read command */
+    uint8_t  reset_c_read_cmd_size;     /*!< Flash reset continuous read command size */
+    uint8_t  jedec_id_cmd;              /*!< JEDEC ID command */
+    uint8_t  jedec_id_cmd_dmy_clk;      /*!< JEDEC ID command dummy clock */
+#if defined(BL702L) || defined(BL702) || defined(BL602)
+    uint8_t  qpi_jedec_id_cmd;          /*!< QPI JEDEC ID comamnd */
+    uint8_t  qpi_jedec_id_cmd_dmy_clk;  /*!< QPI JEDEC ID command dummy clock */
+#else
+    uint8_t  enter_32bits_addr_cmd;     /*!< Enter 32-bits addr command */
+    uint8_t  exit_32bits_addr_cmd;      /*!< Exit 32-bits addr command */
+#endif
+    uint8_t  sector_size;               /*!< *1024bytes */
+    uint8_t  mid;                       /*!< Manufacturer ID */
+    uint16_t page_size;                 /*!< Page size */
+    uint8_t  chip_erase_cmd;            /*!< Chip erase cmd */
+    uint8_t  sector_erase_cmd;          /*!< Sector erase command */
+    uint8_t  blk32_erase_cmd;           /*!< Block 32K erase command,some Micron not support */
+    uint8_t  blk64_erase_cmd;           /*!< Block 64K erase command */
+    uint8_t  write_enable_cmd;          /*!< Need before every erase or program */
+    uint8_t  page_program_cmd;          /*!< Page program cmd */
+    uint8_t  qpage_program_cmd;         /*!< QIO page program cmd */
+    uint8_t  qpp_addr_mode;             /*!< QIO page program address mode */
+    uint8_t  fast_read_cmd;             /*!< Fast read command */
+    uint8_t  fr_dmy_clk;                /*!< Fast read command dummy clock */
+    uint8_t  qpi_fast_read_cmd;         /*!< QPI fast read command */
+    uint8_t  qpi_fr_dmy_clk;            /*!< QPI fast read command dummy clock */
+    uint8_t  fast_read_do_cmd;          /*!< Fast read dual output command */
+    uint8_t  fr_do_dmy_clk;             /*!< Fast read dual output command dummy clock */
+    uint8_t  fast_read_dio_cmd;         /*!< Fast read dual io comamnd */
+    uint8_t  fr_dio_dmy_clk;            /*!< Fast read dual io command dummy clock */
+    uint8_t  fast_read_qo_cmd;          /*!< Fast read quad output comamnd */
+    uint8_t  fr_qo_dmy_clk;             /*!< Fast read quad output comamnd dummy clock */
+    uint8_t  fast_read_qio_cmd;         /*!< Fast read quad io comamnd */
+    uint8_t  fr_qio_dmy_clk;            /*!< Fast read quad io comamnd dummy clock */
+    uint8_t  qpi_fast_read_qio_cmd;     /*!< QPI fast read quad io comamnd */
+    uint8_t  qpi_fr_qio_dmy_clk;        /*!< QPI fast read QIO dummy clock */
+    uint8_t  qpi_page_program_cmd;      /*!< QPI program command */
+    uint8_t  write_vreg_enable_cmd;     /*!< Enable write reg */
+    uint8_t  wr_enable_index;           /*!< Write enable register index */
+    uint8_t  qe_index;                  /*!< Quad mode enable register index */
+    uint8_t  busy_index;                /*!< Busy status register index */
+    uint8_t  wr_enable_bit;             /*!< Write enable bit pos */
+    uint8_t  qe_bit;                    /*!< Quad enable bit pos */
+    uint8_t  busy_bit;                  /*!< Busy status bit pos */
+    uint8_t  wr_enable_write_reg_len;   /*!< Register length of write enable */
+    uint8_t  wr_enable_read_reg_len;    /*!< Register length of write enable status */
+    uint8_t  qe_write_reg_len;          /*!< Register length of contain quad enable */
+    uint8_t  qe_read_reg_len;           /*!< Register length of contain quad enable status */
+    uint8_t  release_powerdown;         /*!< Release power down command */
+    uint8_t  busy_read_reg_len;         /*!< Register length of contain busy status */
+    uint8_t  read_reg_cmd[4];           /*!< Read register command buffer */
+    uint8_t  write_reg_cmd[4];          /*!< Write register command buffer */
+    uint8_t  enter_qpi;                 /*!< Enter qpi command */
+    uint8_t  exit_qpi;                  /*!< Exit qpi command */
+    uint8_t  c_read_mode;               /*!< Config data for continuous read mode */
+    uint8_t  c_rexit;                   /*!< Config data for exit continuous read mode */
+    uint8_t  burst_wrap_cmd;            /*!< Enable burst wrap command */
+    uint8_t  burst_wrap_cmd_dmy_clk;    /*!< Enable burst wrap command dummy clock */
+    uint8_t  burst_wrap_data_mode;      /*!< Data and address mode for this command */
+    uint8_t  burst_wrap_data;           /*!< Data to enable burst wrap */
+    uint8_t  de_burst_wrap_cmd;         /*!< Disable burst wrap command */
+    uint8_t  de_burst_wrap_cmd_dmy_clk; /*!< Disable burst wrap command dummy clock */
+    uint8_t  de_burst_wrap_data_mode;   /*!< Data and address mode for this command */
+    uint8_t  de_burst_wrap_data;        /*!< Data to disable burst wrap */
+    uint16_t time_e_sector;             /*!< 4K erase time */
+    uint16_t time_e_32k;                /*!< 32K erase time */
+    uint16_t time_e_64k;                /*!< 64K erase time */
+    uint16_t time_page_pgm;             /*!< Page program time */
+    uint16_t time_ce;                   /*!< Chip erase time in ms */
+    uint8_t  pd_delay;                  /*!< Release power down command delay time for wake up */
+    uint8_t  qe_data;                   /*!< QE set data */
+} __attribute__((packed)) spi_flash_cfg_type;
+
+/**
+ *  @brief Serial flash security register configuration
+ */
+struct sflash_sec_reg_cfg
+{
+    uint8_t  erase_cmd;         /*!< Erase security register command */
+    uint8_t  program_cmd;       /*!< Program security register command */
+    uint8_t  read_cmd;          /*!< Read security register command */
+    uint8_t  enter_sec_opt_cmd; /*!< Enter security register option mode command */
+    uint8_t  exit_sec_opt_cmd;  /*!< Exit security register option mode command */
+    uint8_t  block_num;         /*!< Security register block number */
+    uint8_t  *data;             /*!< Data pointer to be program/read */
+    uint32_t addr;              /*!< Start address to be program/read */
+    uint32_t len;               /*!< Data length to be program/read */
+};
+/*@} end of group SFLAH_Public_Types */
+
+/** @defgroup  SFLAH_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SFLAH_Public_Constants */
+
+/** @defgroup  SFLAH_Public_Macros
+ *  @{
+ */
+#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
+#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
+#define BFLB_SPIFLASH_CMD_INVALID 0xff
+
+/*@} end of group SFLAH_Public_Macros */
+
+/** @defgroup  SFLAH_Public_Functions
+ *  @{
+ */
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg);
+#else
+void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg);
+#endif
+int bflb_sflash_set_spi_mode(uint8_t mode);
+int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len);
+int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len);
+int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value,
+                                      uint8_t reg_len);
+int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value,
+                                       uint8_t reg_len);
+int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg);
+void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sector_num);
+int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num);
+int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num);
+int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr);
+void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len);
+void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data);
+void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr);
+void bflb_sflash_powerdown(void);
+void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, uint8_t flash_cont_read, uint8_t bank);
+void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg);
+void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg);
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+int bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, uint8_t en_32bits_addr);
+#endif
+int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg);
+void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr,
+                            uint32_t len, uint8_t bank);
+int bflb_sflash_xip_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank);
+void bflb_sflash_xip_read_disable(void);
+int bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos);
+int bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_clear_status_register(spi_flash_cfg_type *flash_cfg);
+int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data,
+                         uint32_t len);
+int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len);
+
+/*@} end of group SFLAH_Public_Functions */
+
+/*@} end of group SFLAH */
+
+/*@} end of group BL628_Peripheral_Driver */
+
+#endif /* __BL628_SFLAH_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.c
new file mode 100755
index 0000000000..4d4a5943b3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.c
@@ -0,0 +1,495 @@
+/**
+  ******************************************************************************
+  * @file    bflb_xip_sflash.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bflb_common.h"
+#include "bflb_xip_sflash.h"
+
+/** @addtogroup  BL628_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_Private_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Macros */
+
+/** @defgroup  XIP_SFLASH_Private_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Types */
+
+/** @defgroup  XIP_SFLASH_Private_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Variables */
+
+/** @defgroup  XIP_SFLASH_Global_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Global_Variables */
+
+/** @defgroup  XIP_SFLASH_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_Private_Fun_Declaration */
+
+/** @defgroup  XIP_SFLASH_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Save flash controller state
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  offset: CPU XIP flash offset pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset,
+                                                    uint8_t group, uint8_t bank)
+{
+    /* XIP_SFlash_Delay */
+    volatile uint32_t i = 32 * 2;
+
+    while (i--)
+        ;
+
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+    if (bank == SF_CTRL_FLASH_BANK1) {
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+    }
+#endif
+    bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+    /* Exit form continous read for accepting command */
+    bflb_sflash_reset_continue_read(p_flash_cfg);
+    /* For disable command that is setting register instaed of send command, we need write enable */
+    bflb_sflash_disable_burst_wrap(p_flash_cfg);
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+    /* Enable 32Bits addr mode again in case reset command make it reset */
+    bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1);
+#endif
+    if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
+        /* Enable QE again in case reset command make it reset */
+        bflb_sflash_qspi_enable(p_flash_cfg);
+    }
+    /* Deburst again to make sure */
+    bflb_sflash_disable_burst_wrap(p_flash_cfg);
+
+    /* Clear offset setting*/
+    *offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+    bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Restore flash controller state
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  offset: CPU XIP flash offset
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset,
+                                                       uint8_t group, uint8_t bank)
+{
+    uint32_t tmp[1];
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
+
+    if(((p_flash_cfg->io_mode>>4)&0x01) == 0) {
+        if((p_flash_cfg->io_mode&0x0f)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0x0f)==SF_CTRL_QIO_MODE) {
+            bflb_sflash_set_burst_wrap(p_flash_cfg);
+        }
+    }
+#ifdef BFLB_SF_CTRL_32BITS_ADDR_ENABLE
+    bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1);
+#endif
+    bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
+    bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+#ifdef BFLB_SF_CTRL_SBUS2_ENABLE
+    if (bank == SF_CTRL_FLASH_BANK1) {
+        bflb_sf_ctrl_sbus2_revoke_replace();
+    }
+#endif
+
+    return 0;
+}
+
+/*@} end of group XIP_SFLASH_Private_Functions */
+
+/** @defgroup  XIP_SFLASH_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one region
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  start_addr: start address to erase
+ * @param  len: data length to erase
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr,
+                                                         int len, uint8_t group, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t offset = 0;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_erase(p_flash_cfg, start_addr, start_addr + len - 1);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Program flash one region
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: start address to be programed
+ * @param  data: data pointer to be programed
+ * @param  len: data length to be programed
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+                                                         uint32_t len, uint8_t group, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t offset = 0;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_program(p_flash_cfg, io_mode, addr, data, len);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+                                                        uint32_t len, uint8_t group, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t offset = 0;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_read(p_flash_cfg, io_mode, 0, addr, data, len);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Jedec ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  data: data pointer to store Jedec ID Read from flash
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                                               uint8_t group, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t offset = 0;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_jedecid(p_flash_cfg, data);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Device ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  is_32bits_addr: Is flash addr mode in 32-bits
+ * @param  data: data pointer to store Device ID Read from flash
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
+                                                                uint8_t *data, uint8_t group, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t offset = 0;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_deviceid(data, is_32bits_addr);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Unique ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  data: data pointer to store Device ID Read from flash
+ * @param  id_len: Unique id len
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                                                uint8_t id_len, uint8_t group, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t offset = 0;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_uniqueid(data, id_len);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register need lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg,
+                                                                     uint8_t group, uint8_t bank)
+{
+    int stat = 0;
+    uint32_t offset = 0;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_clear_status_register(p_flash_cfg);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash via XIP
+ *
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len,
+                                                                  uint8_t group, uint8_t bank)
+{
+    uint32_t offset = 0;
+
+    addr = addr & (BFLB_FLASH_XIP_END-BFLB_FLASH_XIP_BASE-1);
+    addr |= BFLB_FLASH_XIP_BASE;
+
+    offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+    bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+    /* Flash read */
+    arch_memcpy_fast(data, (void *)(uintptr_t)(addr - bflb_sf_ctrl_get_flash_image_offset(group, bank)), len);
+    bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  XIP SFlash option save
+ *
+ * @param  aes_enable: AES enable status pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable)
+{
+    *aes_enable = bflb_sf_ctrl_is_aes_enable();
+
+    if (*aes_enable) {
+        bflb_sf_ctrl_aes_disable();
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  XIP SFlash option restore
+ *
+ * @param  aes_enable: AES enable status
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable)
+{
+    if (aes_enable) {
+        bflb_sf_ctrl_aes_enable();
+    }
+}
+
+/*@} end of group XIP_SFLASH_Public_Functions */
+
+/*@} end of group XIP_SFLASH */
+
+/*@} end of group BL628_Peripheral_Driver */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.h
old mode 100644
new mode 100755
similarity index 55%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.h
index fe9918e4cf..ab4cf7d777
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_xip_sflash.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/lhal/src/flash/bflb_xip_sflash.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_xip_sflash.h
+  * @file    bflb_xip_sflash.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,13 +33,12 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_XIP_SFLASH_H__
-#define __BL808_XIP_SFLASH_H__
+#ifndef __BL628_XIP_SFLASH_H__
+#define __BL628_XIP_SFLASH_H__
 
-#include "bl808_common.h"
-#include "bl808_sflash.h"
+#include "bflb_sflash.h"
 
-/** @addtogroup  BL808_Peripheral_Driver
+/** @addtogroup  BL628_Peripheral_Driver
  *  @{
  */
 
@@ -68,31 +67,33 @@
 /** @defgroup  XIP_SFLASH_Public_Functions
  *  @{
  */
-BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset,
-                                  uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset,
-                                     uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr,
-                                       int len, uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr,
-                                       uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr,
-                                      uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data,
-                                            uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg,
-                                             BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data,
-                                             uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank);
-BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len,
-                                                uint8_t group, SF_Ctrl_Bank_Select bank);
-void XIP_SFlash_Opt_Enter(uint8_t *aesEnable);
-void XIP_SFlash_Opt_Exit(uint8_t aesEnable);
+int bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset,
+                                   uint8_t group, uint8_t bank);
+int bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset,
+                                      uint8_t group, uint8_t bank);
+int bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr,
+                                        int len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
+                                        uint8_t *data, uint32_t len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
+                                       uint8_t *data, uint32_t len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                              uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
+                                               uint8_t *data, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                               uint8_t idlen, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_Flash_Cfg,
+                                                        uint8_t group, uint8_t bank);
+int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len,
+                                                 uint8_t group, uint8_t bank);
+void bflb_xip_sflash_opt_enter(uint8_t *aes_enable);
+void bflb_xip_sflash_opt_exit(uint8_t aes_enable);
 
 /*@} end of group XIP_SFLASH_Public_Functions */
 
 /*@} end of group XIP_SFLASH */
 
-/*@} end of group BL808_Peripheral_Driver */
+/*@} end of group BL628_Peripheral_Driver */
 
-#endif /* __BL808_XIP_SFLASH_H__ */
+#endif /* __BL628_XIP_SFLASH_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/SConscript
new file mode 100755
index 0000000000..4c815c49b8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/SConscript
@@ -0,0 +1,15 @@
+# RT-Thread building script for bridge
+
+import os
+from building import *
+
+cwd = GetCurrentDir()
+objs = []
+list = os.listdir(cwd)
+
+for d in list:
+    path = os.path.join(cwd, d)
+    if os.path.isfile(os.path.join(path, 'SConscript')):
+        objs = objs + SConscript(os.path.join(d, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/SConscript
new file mode 100755
index 0000000000..6471757956
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/SConscript
@@ -0,0 +1,48 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = []
+
+CPPPATH = [cwd]
+CPPDEFINES = []
+
+src += Split("""
+    std/startup/start.S
+    std/startup/start_load.c
+    std/startup/system_bl602.c
+    std/startup/interrupt.c
+""")
+
+src += Split("""
+    std/src/bl602_aon.c
+    std/src/bl602_common.c
+    std/src/bl602_clock.c
+    std/src/bl602_ef_cfg.c
+    std/src/bl602_glb.c
+    std/src/bl602_hbn.c
+    std/src/bl602_l1c.c
+    std/src/bl602_pds.c 
+    std/src/bl602_tzc_sec.c
+    std/src/bl602_sflash_ext.c
+    std/src/bl602_xip_sflash_ext.c
+    std/src/bl602_sf_cfg_ext.c
+""")
+src += ['std/port/bl602_clock.c']
+
+CPPPATH += [cwd + r'/std/include',
+        cwd + r'/std/include/hardware']
+
+if GetDepend('BSP_USING_ROMAPI'):
+    src += Split("""
+        std/src/bl602_romapi.c
+    """)
+    CPPDEFINES += ['BFLB_USE_ROM_DRIVER']
+
+CPPDEFINES += ['CONFIG_IRQ_NUM=80', 'BFLB_USE_HAL_DRIVER', 'BL602', 'default_interrupt_handler=SW_handler']
+LOCAL_CFLAGS = ' -DARCH_RISCV'
+
+group = DefineGroup('bl602', src, depend = ['BSP_USING_BL60X'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_aon.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_aon.h
new file mode 100755
index 0000000000..92c54f06e3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_aon.h
@@ -0,0 +1,107 @@
+/**
+  ******************************************************************************
+  * @file    bl602_aon.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_AON_H__
+#define __BL602_AON_H__
+
+#include "aon_reg.h"
+#include "glb_reg.h"
+#include "hbn_reg.h"
+#include "pds_reg.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Public_Types
+ *  @{
+ */
+
+/*@} end of group AON_Public_Types */
+
+/** @defgroup  AON_Public_Constants
+ *  @{
+ */
+
+/*@} end of group AON_Public_Constants */
+
+/** @defgroup  AON_Public_Macros
+ *  @{
+ */
+
+/*@} end of group AON_Public_Macros */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+/*----------*/
+BL_Err_Type AON_Power_On_MBG(void);
+BL_Err_Type AON_Power_Off_MBG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_XTAL(void);
+BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut);
+uint8_t AON_Get_Xtal_CapCode(void);
+BL_Err_Type AON_Power_Off_XTAL(void);
+/*----------*/
+BL_Err_Type AON_Power_On_BG(void);
+BL_Err_Type AON_Power_Off_BG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO11_SOC(void);
+BL_Err_Type AON_Power_Off_LDO11_SOC(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO15_RF(void);
+BL_Err_Type AON_Power_Off_LDO15_RF(void);
+/*----------*/
+BL_Err_Type AON_Power_On_SFReg(void);
+BL_Err_Type AON_Power_Off_SFReg(void);
+/*----------*/
+BL_Err_Type AON_LowPower_Enter_PDS0(void);
+BL_Err_Type AON_LowPower_Exit_PDS0(void);
+/*----------*/
+BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay);
+/*----------*/;
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_AON_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_clock.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_clock.h
new file mode 100755
index 0000000000..07e2f93e4a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_clock.h
@@ -0,0 +1,128 @@
+/**
+  ******************************************************************************
+  * @file    bl602_clock.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_CLOCK_H__
+#define __BL602_CLOCK_H__
+
+#include "glb_reg.h"
+#include "bl602_hbn.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief System clock type definition
+ */
+typedef enum {
+    BL_SYSTEM_CLOCK_ROOT, /*!< ROOT clock */
+    BL_SYSTEM_CLOCK_FCLK, /*!< Fast clock/CPU clock */
+    BL_SYSTEM_CLOCK_BCLK, /*!< BUS clock */
+    BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */
+    BL_SYSTEM_CLOCK_XCLK, /*!< XCLK:RC32M or XTAL */
+    BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */
+    BL_SYSTEM_CLOCK_MAX,  /*!< MAX type of system clock */
+} BL_System_Clock_Type;
+
+typedef enum {
+    BL_PERIPHERAL_CLOCK_UART0,   /*!< UART0 clock */
+    BL_PERIPHERAL_CLOCK_UART1,   /*!< UART1 clock */
+    BL_PERIPHERAL_CLOCK_SPI0,    /*!< SPI0 clock */
+    BL_PERIPHERAL_CLOCK_I2C0,    /*!< I2C0 clock */
+    BL_PERIPHERAL_CLOCK_GPADC,   /*!< GPADC clock */
+    BL_PERIPHERAL_CLOCK_GPDAC,   /*!< GPDAC clock */
+    BL_PERIPHERAL_CLOCK_PWM,     /*!< PWM clock */
+    BL_PERIPHERAL_CLOCK_IR,      /*!< IR clock */
+    BL_PERIPHERAL_CLOCK_FLASH,   /*!< FLASH clock */
+    BL_PERIPHERAL_CLOCK_MAX,
+} BL_Peripheral_Type;
+
+/**
+ *  @brief SOC clock config type
+ */
+typedef struct
+{
+    uint16_t systemClock[BL_SYSTEM_CLOCK_MAX];   /*!< System lock value */
+    uint16_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */
+    uint32_t i2sClock;                           /*!< I2S clock */
+} Clock_Cfg_Type;
+
+/*@} end of group CLOCK_Public_Types */
+
+/** @defgroup  CLOCK_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  BL_SYSTEM_CLOCK_TYPE
+ *  @{
+ */
+#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_ROOT) || \
+                                       ((type) == BL_SYSTEM_CLOCK_FCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_BCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_F32K) || \
+                                       ((type) == BL_SYSTEM_CLOCK_XCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_XTAL) || \
+                                       ((type) == BL_SYSTEM_CLOCK_MAX))
+
+/*@} end of group CLOCK_Public_Constants */
+
+/** @defgroup  CLOCK_Public_Macros
+ *  @{
+ */
+
+/*@} end of group CLOCK_Public_Macros */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type);
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type);
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_CLOCK_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_common.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_common.h
new file mode 100755
index 0000000000..b60b815697
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_common.h
@@ -0,0 +1,215 @@
+#ifndef __BL602_COMMON_H__
+#define __BL602_COMMON_H__
+
+#include "bl602.h"
+#include "bflb_core.h"
+
+/**
+ * @brief Memory access macro
+ */
+#define BL_RD_WORD(addr)       (*((volatile uint32_t *)(uintptr_t)(addr)))
+#define BL_WR_WORD(addr, val)  ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_SHORT(addr)      (*((volatile uint16_t *)(uintptr_t)(addr)))
+#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_BYTE(addr)       (*((volatile uint8_t *)(uintptr_t)(addr)))
+#define BL_WR_BYTE(addr, val)  ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val))
+#define BL_RDWD_FRM_BYTEP(p)   ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+
+#define BL_WRWD_TO_BYTEP(p, val)   \
+    {                              \
+        p[0] = val & 0xff;         \
+        p[1] = (val >> 8) & 0xff;  \
+        p[2] = (val >> 16) & 0xff; \
+        p[3] = (val >> 24) & 0xff; \
+    }
+/**
+ * @brief Register access macro
+ */
+#define BL_RD_REG16(addr, regname)                BL_RD_SHORT(addr + regname##_OFFSET)
+#define BL_WR_REG16(addr, regname, val)           BL_WR_SHORT(addr + regname##_OFFSET, val)
+#define BL_RD_REG(addr, regname)                  BL_RD_WORD(addr + regname##_OFFSET)
+#define BL_WR_REG(addr, regname, val)             BL_WR_WORD(addr + regname##_OFFSET, val)
+#define BL_SET_REG_BIT(val, bitname)              ((val) | (1U << bitname##_POS))
+#define BL_CLR_REG_BIT(val, bitname)              ((val)&bitname##_UMSK)
+#define BL_GET_REG_BITS_VAL(val, bitname)         (((val)&bitname##_MSK) >> bitname##_POS)
+#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
+#define BL_IS_REG_BIT_SET(val, bitname)           (((val) & (1U << (bitname##_POS))) != 0)
+#define BL_DRV_DUMMY           \
+    {                          \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+    }
+
+/** @defgroup  COMMON_Public_Types
+ *  @{
+ */
+#ifdef BIT
+#undef BIT
+#define BIT(n) (1UL << (n))
+#else
+#define BIT(n) (1UL << (n))
+#endif
+
+/**
+ * @brief Null Type definition
+ */
+#ifndef NULL
+#define NULL 0
+#endif
+
+/**
+ * @brief Error type definition
+ */
+typedef enum {
+    SUCCESS = 0,
+    ERROR = 1,
+    TIMEOUT = 2,
+    INVALID = 3, /* invalid arguments */
+    NORESC = 4   /* no resource or resource temperary unavailable */
+} BL_Err_Type;
+
+/**
+ * @brief Functional type definition
+ */
+typedef enum {
+    DISABLE = 0,
+    ENABLE = 1,
+} BL_Fun_Type;
+
+/**
+ * @brief Status type definition
+ */
+typedef enum {
+    RESET = 0,
+    SET = 1,
+} BL_Sts_Type;
+
+/**
+ * @brief Mask type definition
+ */
+typedef enum {
+    UNMASK = 0,
+    MASK = 1
+} BL_Mask_Type;
+
+/**
+ * @brief Logical status Type definition
+ */
+typedef enum {
+    LOGIC_LO = 0,
+    LOGIC_HI = !LOGIC_LO
+} LogicalStatus;
+
+/**
+ * @brief Active status Type definition
+ */
+typedef enum {
+    DEACTIVE = 0,
+    ACTIVE = !DEACTIVE
+} ActiveStatus;
+
+/**
+ *  @brief Interrupt callback function type
+ */
+typedef void(intCallback_Type)(void);
+typedef void (*pFunc)(void);
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr) ((void)0)
+#endif /* DEBUG */
+
+#ifndef __NOP
+#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */
+#endif
+#ifndef __WFI
+#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */
+#endif
+#ifndef __WFE
+#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */
+#endif
+#ifndef __SEV
+#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */
+#endif
+#ifndef __set_MSP
+#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
+#endif
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+    //return __builtin_bswap32(value);
+    uint32_t res = 0;
+
+    res = (value << 24) | (value >> 24);
+    res &= 0xFF0000FF; /* only for sure */
+    res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
+
+    return res;
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    return __builtin_bswap16(value);
+}
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by setting the IE-bit in the PSR.
+           Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile("csrs mstatus, 8");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
+  Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile("csrc mstatus, 8");
+}
+
+/** @defgroup  COMMON_Public_Constants
+ *  @{
+ */
+
+/** @defgroup DRIVER_INT_PERIPH
+ *  @{
+ */
+#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
+
+/*@} end of group DRIVER_INT_PERIPH */
+
+/** @defgroup DRIVER_INT_MASK
+ *  @{
+ */
+#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
+
+/*@} end of group COMMON_Public_Constants */
+
+/*@} end of group DRIVER_Public_Macro */
+#define BL602_MemCpy      arch_memcpy
+#define BL602_MemSet      arch_memset
+#define BL602_MemCmp      arch_memcmp
+#define BL602_MemCpy4     arch_memcpy4
+#define BL602_MemCpy_Fast arch_memcpy_fast
+#define BL602_MemSet4     arch_memset4
+
+#define BL602_Delay_US arch_delay_us
+#define BL602_Delay_MS arch_delay_ms
+
+#define BFLB_Soft_CRC32 bflb_soft_crc32
+#define CPU_Interrupt_Enable(irq)
+#define CPU_Interrupt_Disable(irq)
+#define Interrupt_Handler_Register(irq, callback)
+
+void BL602_Delay_US(uint32_t cnt);
+void BL602_Delay_MS(uint32_t cnt);
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_cfg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_cfg.h
new file mode 100755
index 0000000000..c639fff967
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_cfg.h
@@ -0,0 +1,97 @@
+/**
+  ******************************************************************************
+  * @file    bl602_ef_cfg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_EF_CFG_H__
+#define __BL602_EF_CFG_H__
+
+#include "bl602_common.h"
+#include "bflb_ef_ctrl.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Efuse Ctrl key slot type definition
+ */
+typedef struct {
+    uint32_t rsvd_18_0  : 19; /*!< Reserved */
+    uint32_t chip_ver   : 3;  /*!< chip revision */
+    uint32_t rsvd_23_22 : 2;  /*!< Reserved */
+    uint32_t extInfo    : 3;  /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E, 4:POS/AT */
+    uint32_t memoryInfo : 2;  /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash, 3:4MB flash */
+    uint32_t rsvd_29    : 1;  /*!< Efuse reserved */
+    uint32_t mcuInfo    : 1;  /*!< Efuse mcu info 0:wifi, 1:mcu */
+    uint32_t pinInfo    : 1;  /*!< Efuse pin info 0:QFN32, 1:QFN40 */
+} bflb_efuse_device_info_type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
+ *  @{
+ */
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup  EF_CTRL_Public_Macros
+ *  @{
+ */
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup  EF_CTRL_Public_Functions
+ *  @{
+ */
+
+void bflb_efuse_switch_cpu_clock_save(void);
+void bflb_efuse_switch_cpu_clock_restore(void);
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo);
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_EF_CFG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_ctrl.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_ctrl.h
new file mode 100755
index 0000000000..5e8d1fd603
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_ef_ctrl.h
@@ -0,0 +1,352 @@
+/**
+  ******************************************************************************
+  * @file    bl602_ef_ctrl.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_EF_CTRL_H__
+#define __BL602_EF_CTRL_H__
+
+#include "ef_ctrl_reg.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Efuse Ctrl key slot type definition
+ */
+typedef enum {
+    EF_CTRL_KEY_SLOT0, /*!< key slot 0 */
+    EF_CTRL_KEY_SLOT1, /*!< key slot 1 */
+    EF_CTRL_KEY_SLOT2, /*!< key slot 2 */
+    EF_CTRL_KEY_SLOT3, /*!< key slot 3 */
+    EF_CTRL_KEY_SLOT4, /*!< key slot 4 */
+    EF_CTRL_KEY_SLOT5, /*!< key slot 5 */
+    EF_CTRL_KEY_MAX,   /*!<  */
+} EF_Ctrl_Key_Type;
+
+/**
+ *  @brief Efuse Ctrl sign type definition
+ */
+typedef enum {
+    EF_CTRL_SIGN_NONE, /*!< no sign */
+    EF_CTRL_SIGN_RSA,  /*!< use RSA to sign */
+    EF_CTRL_SIGN_ECC,  /*!< use ECC to sign */
+} EF_Ctrl_Sign_Type;
+
+/**
+ *  @brief Efuse Ctrl flash AES type definition
+ */
+typedef enum {
+    EF_CTRL_SF_AES_NONE, /*!< No AES */
+    EF_CTRL_SF_AES_128,  /*!< AES 128 */
+    EF_CTRL_SF_AES_192,  /*!< AES 192 */
+    EF_CTRL_SF_AES_256,  /*!< AES 256 */
+} EF_Ctrl_SF_AES_Type;
+
+/**
+ *  @brief Efuse Ctrl Dbg type definition
+ */
+typedef enum {
+    EF_CTRL_DBG_OPEN = 0,  /*!< Open debug */
+    EF_CTRL_DBG_PASSWORD,  /*!< Open debug with password */
+    EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */
+} EF_Ctrl_Dbg_Mode_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_EF_CLK,   /*!< Select efuse clock */
+    EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */
+} EF_Ctrl_CLK_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_PARA_DFT,    /*!< Select default cyc parameter */
+    EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */
+} EF_Ctrl_CYC_PARA_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_OP_MODE_AUTO,   /*!< Select efuse program auto mode */
+    EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */
+} EF_Ctrl_OP_MODE_Type;
+
+/**
+ *  @brief Efuse Ctrl secure configuration structure type definition
+ */
+typedef struct
+{
+    EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */
+    uint8_t ef_dbg_jtag_0_dis;         /*!< Jtag debug disable config value */
+    uint8_t ef_sboot_en;               /*!< Secure boot enable config value */
+    uint8_t ef_no_hd_boot_en;          /*!< No header boot enable */
+} EF_Ctrl_Sec_Param_Type;
+
+/**
+ *  @brief Efuse analog RC32M trim type definition
+ */
+typedef struct
+{
+    uint32_t trimRc32mCodeFrExt       : 8;  /*!< Efuse analog trim:trim_rc32m_code_fr_ext */
+    uint32_t trimRc32mCodeFrExtParity : 1;  /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */
+    uint32_t trimRc32mExtCodeEn       : 1;  /*!< Efuse analog trim:trim_rc32m_ext_code_en */
+    uint32_t reserved                 : 22; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32M_Trim_Type;
+
+/**
+ *  @brief Efuse analog RC32K trim type definition
+ */
+typedef struct
+{
+    uint32_t trimRc32kCodeFrExt       : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */
+    uint32_t trimRc32kCodeFrExtParity : 1;  /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */
+    uint32_t trimRc32kExtCodeEn       : 1;  /*!< Efuse analog trim:trim_rc32k_ext_code_en */
+    uint32_t reserved                 : 20; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32K_Trim_Type;
+
+/**
+ *  @brief Efuse analog TSEN trim type definition
+ */
+typedef struct
+{
+    uint32_t tsenRefcodeCorner        : 12; /*!< TSEN refcode */
+    uint32_t tsenRefcodeCornerParity  : 1;  /*!< TSEN refcode parity */
+    uint32_t tsenRefcodeCornerEn      : 1;  /*!< TSEN refcode enable */
+    uint32_t tsenRefcodeCornerVersion : 1;  /*!< TSEN refcode version */
+    uint32_t reserved                 : 17; /*!< TSEN analog trim:reserved */
+} Efuse_TSEN_Refcode_Corner_Type;
+
+/**
+ *  @brief Efuse analog ADC Gain trim type definition
+ */
+typedef struct
+{
+    uint32_t adcGainCoeff       : 12; /*!< ADC gain coeff */
+    uint32_t adcGainCoeffParity : 1;  /*!< ADC gain coeff parity */
+    uint32_t adcGainCoeffEn     : 1;  /*!< ADC gain coeff enable */
+    uint32_t reserved           : 18; /*!< ADC gain coeff:reserved */
+} Efuse_ADC_Gain_Coeff_Type;
+
+/**
+ *  @brief Efuse analog device info type definition
+ */
+typedef struct
+{
+    uint32_t rsvd       : 19; /*!< Reserved */
+    uint32_t chip_ver   : 3;  /*!< chip revision */
+    uint32_t customerID : 2;  /*!< Efuse customer ID information */
+    uint32_t rsvd_info  : 3;  /*!< Efuse device info extension: 1:BL602C, 2:BL602L, 3:BL602E */
+    uint32_t memoryInfo : 2;  /*!< Efuse memory info 0:no memory, 1:1MB flash, 2:2MB flash */
+    uint32_t coreInfo   : 1;  /*!< Efuse reserved */
+    uint32_t mcuInfo    : 1;  /*!< Efuse mcu info 0:wifi, 1:mcu */
+    uint32_t pinInfo    : 1;  /*!< Efuse pin info 0:QFN32, 1:QFN40 */
+} Efuse_Device_Info_Type;
+
+/**
+ *  @brief Efuse Capcode type definition
+ */
+typedef struct
+{
+    uint32_t capCode : 6;  /*!< Cap code value */
+    uint32_t parity  : 1;  /*!< Parity of capcode */
+    uint32_t en      : 1;  /*!< Enable status */
+    uint32_t rsvd    : 24; /*!< Reserved */
+} Efuse_Capcode_Info_Type;
+
+/**
+ *  @brief Efuse Ldo11 Vout Sel Trim definition
+ */
+typedef struct {
+    uint32_t sel_value : 4;  /*!< value trim */
+    uint32_t parity    : 1;  /*!< Parity of capcode */
+    uint32_t en        : 1;  /*!< Enable status */
+    uint32_t rsvd      : 26; /*!< Reserved */
+} Efuse_Ldo11VoutSelTrim_Info_Type;
+
+/**
+ *  @brief Efuse Tx Power definition
+ */
+typedef struct {
+    uint32_t txpower : 5;  /*!< txpower value  */
+    uint32_t parity  : 1;  /*!< Parity of capcode */
+    uint32_t en      : 1;  /*!< Enable status */
+    uint32_t rsvd    : 25; /*!< Reserved */
+} Efuse_TxPower_Info_Type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_KEY_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \
+                                   ((type) == EF_CTRL_KEY_SLOT1) || \
+                                   ((type) == EF_CTRL_KEY_SLOT2) || \
+                                   ((type) == EF_CTRL_KEY_SLOT3) || \
+                                   ((type) == EF_CTRL_KEY_SLOT4) || \
+                                   ((type) == EF_CTRL_KEY_SLOT5) || \
+                                   ((type) == EF_CTRL_KEY_MAX))
+
+/** @defgroup  EF_CTRL_SIGN_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \
+                                    ((type) == EF_CTRL_SIGN_RSA) ||  \
+                                    ((type) == EF_CTRL_SIGN_ECC))
+
+/** @defgroup  EF_CTRL_SF_AES_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \
+                                      ((type) == EF_CTRL_SF_AES_128) ||  \
+                                      ((type) == EF_CTRL_SF_AES_192) ||  \
+                                      ((type) == EF_CTRL_SF_AES_256))
+
+/** @defgroup  EF_CTRL_DBG_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) ||     \
+                                        ((type) == EF_CTRL_DBG_PASSWORD) || \
+                                        ((type) == EF_CTRL_DBG_CLOSE))
+
+/** @defgroup  EF_CTRL_CLK_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \
+                                   ((type) == EF_CTRL_SAHB_CLK))
+
+/** @defgroup  EF_CTRL_CYC_PARA_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \
+                                        ((type) == EF_CTRL_PARA_MANUAL))
+
+/** @defgroup  EF_CTRL_OP_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \
+                                       ((type) == EF_CTRL_OP_MODE_MANUAL))
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup  EF_CTRL_Public_Macros
+ *  @{
+ */
+#define EF_CTRL_EFUSE_R0_SIZE 128
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup  EF_CTRL_Public_Functions
+ *  @{
+ */
+void EF_Ctrl_Load_Efuse_R0(void);
+void EF_Ctrl_Program_Efuse_0(void);
+BL_Sts_Type EF_Ctrl_Busy(void);
+BL_Sts_Type EF_Ctrl_AutoLoad_Done(void);
+void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program);
+void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh);
+void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program);
+void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg);
+void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program);
+void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]);
+void EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled, uint8_t *npDisabled, uint8_t *npCpuType);
+uint8_t EF_Ctrl_Get_Trim_Enable(void);
+uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len);
+void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program);
+void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim);
+void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim);
+void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim);
+void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim);
+void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim);
+void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program);
+void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage);
+void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program);
+void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
+void EF_Ctrl_Writelock_MAC_Address(uint8_t program);
+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
+void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo);
+void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program);
+void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
+void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Clear(uint32_t index, uint32_t len);
+void EF_Ctrl_Crc_Enable(void);
+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
+void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue);
+BL_Err_Type EF_Ctrl_Crc_Result(void);
+void EF_Ctrl_Sw_AHB_Clk_0(void);
+uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+uint8_t EF_Ctrl_Is_CapCode_Slot_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program);
+BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload);
+uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[3], uint8_t reload);
+void EF_Ctrl_Write_R0(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Read_R0(uint32_t index, uint32_t *data, uint32_t len);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_EF_CTRL_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_glb.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_glb.h
new file mode 100755
index 0000000000..8ba8c8914b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_glb.h
@@ -0,0 +1,666 @@
+/**
+  ******************************************************************************
+  * @file    bl602_glb.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_GLB_H__
+#define __BL602_GLB_H__
+
+#include "glb_reg.h"
+#include "pds_reg.h"
+#include "bl602_gpio.h"
+#include "bl602_l1c.h"
+#include "bl602_hbn.h"
+#include "bl602_aon.h"
+#include "bl602_pds.h"
+#include "bl602_common.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief GLB root clock type definition
+ */
+typedef enum {
+    GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */
+    GLB_ROOT_CLK_XTAL,  /*!< root clock select XTAL */
+    GLB_ROOT_CLK_PLL,   /*!< root clock select PLL others */
+} GLB_ROOT_CLK_Type;
+
+/**
+ *  @brief GLB system clock type definition
+ */
+typedef enum {
+    GLB_SYS_CLK_RC32M,   /*!< use RC32M as system clock frequency */
+    GLB_SYS_CLK_XTAL,    /*!< use XTAL as system clock */
+    GLB_SYS_CLK_PLL48M,  /*!< use PLL output 48M as system clock */
+    GLB_SYS_CLK_PLL120M, /*!< use PLL output 120M as system clock */
+    GLB_SYS_CLK_PLL160M, /*!< use PLL output 160M as system clock */
+    GLB_SYS_CLK_PLL192M, /*!< use PLL output 192M as system clock */
+} GLB_SYS_CLK_Type;
+
+/**
+ *  @brief GLB DMA clock ID type definition
+ */
+typedef enum {
+    GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */
+    GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */
+    GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */
+    GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */
+} GLB_DMA_CLK_ID_Type;
+
+/**
+ *  @brief GLB clock source type definition
+ */
+typedef enum {
+    GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */
+} GLB_IR_CLK_SRC_Type;
+
+/**
+ *  @brief GLB flash clock type definition
+ */
+typedef enum {
+    GLB_SFLASH_CLK_120M, /*!< Select 120M as flash clock */
+    GLB_SFLASH_CLK_XTAL, /*!< Select XTAL as flash clock */
+    GLB_SFLASH_CLK_48M,  /*!< Select 48M as flash clock */
+    GLB_SFLASH_CLK_80M,  /*!< Select 80M as flash clock */
+    GLB_SFLASH_CLK_BCLK, /*!< Select BCLK as flash clock */
+    GLB_SFLASH_CLK_96M,  /*!< Select 96M as flash clock */
+} GLB_SFLASH_CLK_Type;
+
+/**
+ *  @brief GLB SPI pad action type definition
+ */
+typedef enum {
+    GLB_SPI_PAD_ACT_AS_SLAVE,  /*!< SPI pad act as slave */
+    GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */
+} GLB_SPI_PAD_ACT_AS_Type;
+
+/**
+ *  @brief GLB PKA clock type definition
+ */
+typedef enum {
+    GLB_PKA_CLK_HCLK,    /*!< Select HCLK as PKA clock */
+    GLB_PKA_CLK_PLL120M, /*!< Select PLL 120M as PKA clock */
+} GLB_PKA_CLK_Type;
+
+/**
+ *  @brief BMX arb mode type definition
+ */
+typedef enum {
+    BMX_ARB_FIX,         /*!< 0->fix */
+    BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
+    BMX_ARB_RANDOM,      /*!< 3->random */
+} BMX_ARB_Type;
+
+/**
+ *  @brief BMX configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t timeoutEn;   /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+    BL_Fun_Type errEn;   /*!< Bus error response enable */
+    BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+} BMX_Cfg_Type;
+
+/**
+ *  @brief BMX bus err type definition
+ */
+typedef enum {
+    BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+    BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
+} BMX_BUS_ERR_Type;
+
+/**
+ *  @brief BMX bus err interrupt type definition
+ */
+typedef enum {
+    BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */
+    BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */
+} BMX_ERR_INT_Type;
+
+/**
+ *  @brief BMX time out interrupt type definition
+ */
+typedef enum {
+    BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */
+    BMX_TO_INT_ALL,     /*!< BMX timeout interrupt max num */
+} BMX_TO_INT_Type;
+
+/**
+ *  @brief GLB EM type definition
+ */
+typedef enum {
+    GLB_EM_0KB = 0x0,  /*!< 0x0 --> 0KB */
+    GLB_EM_8KB = 0x3,  /*!< 0x3 --> 8KB */
+    GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */
+} GLB_EM_Type;
+
+/**
+ *  @brief GLB RTC clock type definition
+ */
+typedef enum {
+    GLB_MTIMER_CLK_BCLK, /*!< BUS clock */
+    GLB_MTIMER_CLK_32K,  /*!< 32KHz */
+} GLB_MTIMER_CLK_Type;
+
+/**
+ *  @brief GLB ADC clock type definition
+ */
+typedef enum {
+    GLB_ADC_CLK_96M,  /*!< use 96M as ADC clock */
+    GLB_ADC_CLK_XCLK, /*!< use XCLK as ADC clock */
+} GLB_ADC_CLK_Type;
+
+/**
+ *  @brief GLB DAC clock type definition
+ */
+typedef enum {
+    GLB_DAC_CLK_32M,  /*!< use 32M as DAC clock */
+    GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */
+} GLB_DAC_CLK_Type;
+
+/**
+ *  @brief GLB DIG clock source select type definition
+ */
+typedef enum {
+    GLB_DIG_CLK_PLL_32M, /*!< select PLL 32M as DIG clock source */
+    GLB_DIG_CLK_XCLK,    /*!< select XCLK as DIG clock source */
+} GLB_DIG_CLK_Type;
+
+/**
+ *  @brief GLB 512K clock out select type definition
+ */
+typedef enum {
+    GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */
+    GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */
+    GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */
+} GLB_512K_CLK_OUT_Type;
+
+/**
+ *  @brief GLB BT bandwidth type definition
+ */
+typedef enum {
+    GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */
+    GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */
+} GLB_BT_BANDWIDTH_Type;
+
+/**
+ *  @brief GLB UART signal type definition
+ */
+typedef enum {
+    GLB_UART_SIG_0, /*!< UART signal 0 */
+    GLB_UART_SIG_1, /*!< UART signal 1 */
+    GLB_UART_SIG_2, /*!< UART signal 2 */
+    GLB_UART_SIG_3, /*!< UART signal 3 */
+    GLB_UART_SIG_4, /*!< UART signal 4 */
+    GLB_UART_SIG_5, /*!< UART signal 5 */
+    GLB_UART_SIG_6, /*!< UART signal 6 */
+    GLB_UART_SIG_7, /*!< UART signal 7 */
+} GLB_UART_SIG_Type;
+
+/**
+ *  @brief GLB UART signal  function type definition
+ */
+typedef enum {
+    GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */
+    GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */
+    GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */
+    GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */
+    GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */
+    GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */
+    GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */
+    GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */
+} GLB_UART_SIG_FUN_Type;
+
+/**
+ *  @brief GLB GPIO real mode type definition
+ */
+typedef enum {
+    GLB_GPIO_REAL_MODE_REG,        /*!< GPIO real function is reg_gpio_x_func_sel */
+    GLB_GPIO_REAL_MODE_SDIO = 0x1, /*!< GPIO real function is SDIO */
+    GLB_GPIO_REAL_MODE_RF = 0xC,   /*!< GPIO real function is RF */
+    GLB_GPIO_REAL_MODE_JTAG = 0xE, /*!< GPIO real function is JTAG */
+    GLB_GPIO_REAL_MODE_CCI = 0xF,  /*!< GPIO real function is CCI */
+} GLB_GPIO_REAL_MODE_Type;
+
+/**
+ *  @brief GLB GPIO interrupt trigger mode type definition
+ */
+typedef enum {
+    GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */
+    GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */
+    GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */
+    GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */
+} GLB_GPIO_INT_TRIG_Type;
+
+/**
+ *  @brief GLB GPIO interrupt control mode type definition
+ */
+typedef enum {
+    GLB_GPIO_INT_CONTROL_SYNC,  /*!< GPIO interrupt sync mode */
+    GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */
+} GLB_GPIO_INT_CONTROL_Type;
+
+/**
+ *  @brief PLL XTAL type definition
+ */
+typedef enum {
+    GLB_PLL_XTAL_NONE,  /*!< XTAL is none */
+    GLB_PLL_XTAL_24M,   /*!< XTAL is 24M */
+    GLB_PLL_XTAL_32M,   /*!< XTAL is 32M */
+    GLB_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */
+    GLB_PLL_XTAL_40M,   /*!< XTAL is 40M */
+    GLB_PLL_XTAL_26M,   /*!< XTAL is 26M */
+    GLB_PLL_XTAL_RC32M, /*!< XTAL is RC32M */
+} GLB_PLL_XTAL_Type;
+
+/**
+ *  @brief PLL output clock type definition
+ */
+typedef enum {
+    GLB_PLL_CLK_480M, /*!< PLL output clock:480M */
+    GLB_PLL_CLK_240M, /*!< PLL output clock:240M */
+    GLB_PLL_CLK_192M, /*!< PLL output clock:192M */
+    GLB_PLL_CLK_160M, /*!< PLL output clock:160M */
+    GLB_PLL_CLK_120M, /*!< PLL output clock:120M */
+    GLB_PLL_CLK_96M,  /*!< PLL output clock:96M */
+    GLB_PLL_CLK_80M,  /*!< PLL output clock:80M */
+    GLB_PLL_CLK_48M,  /*!< PLL output clock:48M */
+    GLB_PLL_CLK_32M,  /*!< PLL output clock:32M */
+} GLB_PLL_CLK_Type;
+
+/**
+ *  @brief PLL configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t clkpllIcp1u;        /*!< int mode:0, frac mode:1 */
+    uint8_t clkpllIcp5u;        /*!< int mode:2, frac mode:0 */
+    uint8_t clkpllIntFracSw;    /*!< 0:int mode, 1:frac mode */
+    uint8_t clkpllC3;           /*!< int:3, frac:2 */
+    uint8_t clkpllCz;           /*!< int:1, frac:2 */
+    uint8_t clkpllRz;           /*!< int:1, frac:5 */
+    uint8_t clkpllR4;           /*!< int:2, frac:2 */
+    uint8_t clkpllR4Short;      /*!< int:1, frac:0 */
+    uint8_t clkpllRefdivRatio;  /*!< ref divider ratio */
+    uint8_t clkpllPostdiv;      /*!< >=8 and should be even number */
+    uint32_t clkpllSdmin;       /*!< sdmin */
+    uint8_t clkpllSelFbClk;     /*!< 0:mod1, 1:mod2, 2:mod3 */
+    uint8_t clkpllSelSampleClk; /*!< 0:[16,63)mod3, 1:[32:127)mod4, 2:[64,255)mod5 */
+} GLB_PLL_Cfg_Type;
+
+/*@} end of group GLB_Public_Types */
+
+/** @defgroup  GLB_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  GLB_ROOT_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \
+                                    ((type) == GLB_ROOT_CLK_XTAL) ||  \
+                                    ((type) == GLB_ROOT_CLK_PLL))
+
+/** @defgroup  GLB_SYS_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) ||   \
+                                   ((type) == GLB_SYS_CLK_XTAL) ||    \
+                                   ((type) == GLB_SYS_CLK_PLL48M) ||  \
+                                   ((type) == GLB_SYS_CLK_PLL120M) || \
+                                   ((type) == GLB_SYS_CLK_PLL160M) || \
+                                   ((type) == GLB_SYS_CLK_PLL192M))
+
+/** @defgroup  GLB_DMA_CLK_ID_TYPE
+ *  @{
+ */
+#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH1) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH2) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH3))
+
+/** @defgroup  GLB_IR_CLK_SRC_TYPE
+ *  @{
+ */
+#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK))
+
+/** @defgroup  GLB_SFLASH_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_120M) || \
+                                      ((type) == GLB_SFLASH_CLK_XTAL) || \
+                                      ((type) == GLB_SFLASH_CLK_48M) ||  \
+                                      ((type) == GLB_SFLASH_CLK_80M) ||  \
+                                      ((type) == GLB_SFLASH_CLK_BCLK) || \
+                                      ((type) == GLB_SFLASH_CLK_96M))
+
+/** @defgroup  GLB_SPI_PAD_ACT_AS_TYPE
+ *  @{
+ */
+#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \
+                                          ((type) == GLB_SPI_PAD_ACT_AS_MASTER))
+
+/** @defgroup  GLB_PKA_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \
+                                   ((type) == GLB_PKA_CLK_PLL120M))
+
+/** @defgroup  BMX_ARB_TYPE
+ *  @{
+ */
+#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) ||         \
+                               ((type) == BMX_ARB_ROUND_ROBIN) || \
+                               ((type) == BMX_ARB_RANDOM))
+
+/** @defgroup  BMX_BUS_ERR_TYPE
+ *  @{
+ */
+#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+                                   ((type) == BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup  BMX_ERR_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \
+                                   ((type) == BMX_ERR_INT_ALL))
+
+/** @defgroup  BMX_TO_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \
+                                  ((type) == BMX_TO_INT_ALL))
+
+/** @defgroup  GLB_EM_TYPE
+ *  @{
+ */
+#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \
+                              ((type) == GLB_EM_8KB) || \
+                              ((type) == GLB_EM_16KB))
+
+/** @defgroup  GLB_MTIMER_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \
+                                      ((type) == GLB_MTIMER_CLK_32K))
+
+/** @defgroup  GLB_ADC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_96M) || \
+                                   ((type) == GLB_ADC_CLK_XCLK))
+
+/** @defgroup  GLB_DAC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \
+                                   ((type) == GLB_DAC_CLK_XCLK))
+
+/** @defgroup  GLB_DIG_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \
+                                   ((type) == GLB_DIG_CLK_XCLK))
+
+/** @defgroup  GLB_512K_CLK_OUT_TYPE
+ *  @{
+ */
+#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \
+                                        ((type) == GLB_512K_CLK_OUT_256K) || \
+                                        ((type) == GLB_512K_CLK_OUT_128K))
+
+/** @defgroup  GLB_BT_BANDWIDTH_TYPE
+ *  @{
+ */
+#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \
+                                        ((type) == GLB_BT_BANDWIDTH_2M))
+
+/** @defgroup  GLB_UART_SIG_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \
+                                    ((type) == GLB_UART_SIG_1) || \
+                                    ((type) == GLB_UART_SIG_2) || \
+                                    ((type) == GLB_UART_SIG_3) || \
+                                    ((type) == GLB_UART_SIG_4) || \
+                                    ((type) == GLB_UART_SIG_5) || \
+                                    ((type) == GLB_UART_SIG_6) || \
+                                    ((type) == GLB_UART_SIG_7))
+
+/** @defgroup  GLB_UART_SIG_FUN_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RXD))
+
+/** @defgroup  GLB_GPIO_REAL_MODE_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_REAL_MODE_TYPE(type) (((type) == GLB_GPIO_REAL_MODE_REG) ||  \
+                                          ((type) == GLB_GPIO_REAL_MODE_SDIO) || \
+                                          ((type) == GLB_GPIO_REAL_MODE_RF) ||   \
+                                          ((type) == GLB_GPIO_REAL_MODE_JTAG) || \
+                                          ((type) == GLB_GPIO_REAL_MODE_CCI))
+
+/** @defgroup  GLB_GPIO_INT_TRIG_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL))
+
+/** @defgroup  GLB_GPIO_INT_CONTROL_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \
+                                            ((type) == GLB_GPIO_INT_CONTROL_ASYNC))
+
+/** @defgroup  GLB_PLL_XTAL_TYPE
+ *  @{
+ */
+#define IS_GLB_PLL_XTAL_TYPE(type) (((type) == GLB_PLL_XTAL_NONE) ||  \
+                                    ((type) == GLB_PLL_XTAL_24M) ||   \
+                                    ((type) == GLB_PLL_XTAL_32M) ||   \
+                                    ((type) == GLB_PLL_XTAL_38P4M) || \
+                                    ((type) == GLB_PLL_XTAL_40M) ||   \
+                                    ((type) == GLB_PLL_XTAL_26M) ||   \
+                                    ((type) == GLB_PLL_XTAL_RC32M))
+
+/** @defgroup  GLB_PLL_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_PLL_CLK_TYPE(type) (((type) == GLB_PLL_CLK_480M) || \
+                                   ((type) == GLB_PLL_CLK_240M) || \
+                                   ((type) == GLB_PLL_CLK_192M) || \
+                                   ((type) == GLB_PLL_CLK_160M) || \
+                                   ((type) == GLB_PLL_CLK_120M) || \
+                                   ((type) == GLB_PLL_CLK_96M) ||  \
+                                   ((type) == GLB_PLL_CLK_80M) ||  \
+                                   ((type) == GLB_PLL_CLK_48M) ||  \
+                                   ((type) == GLB_PLL_CLK_32M))
+
+/*@} end of group GLB_Public_Constants */
+
+/** @defgroup  GLB_Public_Macros
+ *  @{
+ */
+#define UART_SIG_SWAP_GPIO0_GPIO7   0x01 /* GPIO0-7   uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_GPIO8_GPIO15  0x02 /* GPIO8-15  uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_NONE          0x00 /* GPIO0-22  uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */
+#define JTAG_SIG_SWAP_GPIO0_GPIO3   0x01 /* GPIO0-3   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO4_GPIO7   0x02 /* GPIO4-7   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO8_GPIO11  0x04 /* GPIO8-11  E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_NONE          0x00 /* GPIO0-22  E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+
+/*@} end of group GLB_Public_Macros */
+
+/** @defgroup  GLB_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_ERR_IRQHandler(void);
+void BMX_TO_IRQHandler(void);
+void GPIO_INT0_IRQHandler(void);
+#endif
+/*----------*/
+GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void);
+BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv);
+uint8_t GLB_Get_BCLK_Div(void);
+uint8_t GLB_Get_HCLK_Div(void);
+BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType);
+BL_Err_Type GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq);
+BL_Err_Type System_Core_Clock_Update_From_RC32M(void);
+/*----------*/
+BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv);
+BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv);
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk);
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div);
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel);
+BL_Err_Type GLB_SW_System_Reset(void);
+BL_Err_Type GLB_SW_CPU_Reset(void);
+BL_Err_Type GLB_SW_POR_Reset(void);
+BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1);
+BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1);
+/*----------*/
+BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg);
+BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void);
+BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void);
+BL_Err_Type GLB_BMX_BusErrResponse_Enable(void);
+BL_Err_Type GLB_BMX_BusErrResponse_Disable(void);
+BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType);
+uint32_t GLB_BMX_Get_Err_Addr(void);
+BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type GLB_Set_OCRAM_Idle(void);
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value);
+uint32_t GLB_Get_SRAM_RET(void);
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value);
+uint32_t GLB_Get_SRAM_SLP(void);
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value);
+uint32_t GLB_Get_SRAM_PARM(void);
+/*----------*/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType);
+/*----------*/
+BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel);
+BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel);
+BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState);
+BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod);
+BL_Err_Type GLB_Select_Internal_Flash(void);
+BL_Err_Type GLB_Select_External_Flash(void);
+BL_Err_Type GLB_Deswap_Flash_Pin(void);
+BL_Err_Type GLB_Swap_Flash_Pin(void);
+/*----------*/
+BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div);
+/*----------*/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Platform_Wakeup_Enable(void);
+BL_Err_Type GLB_Platform_Wakeup_Disable(void);
+/*----------*/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel);
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div);
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div);
+/*----------*/
+BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth,
+                                   uint8_t pti, uint8_t channel);
+/*----------*/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun);
+/*----------*/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio);
+BL_Err_Type GLB_IR_LED_Driver_Enable(void);
+BL_Err_Type GLB_IR_LED_Driver_Disable(void);
+BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias);
+/*----------*/
+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg);
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt);
+BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
+uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
+GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val);
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
+BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear);
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod,
+                                GLB_GPIO_INT_TRIG_Type intTrgMod);
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void);
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_GLB_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_gpio.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_gpio.h
new file mode 100755
index 0000000000..7cc1446cf1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_gpio.h
@@ -0,0 +1,444 @@
+/**
+
+  ******************************************************************************
+
+  * @file    bl602_gpio.h
+
+  * @version V1.2
+
+  * @date    2019-12-14
+
+  * @brief   This file is the description of.IP register
+
+  ******************************************************************************
+
+  * @attention
+
+  *
+
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+
+  *
+
+  * Redistribution and use in source and binary forms, with or without modification,
+
+  * are permitted provided that the following conditions are met:
+
+  *   1. Redistributions of source code must retain the above copyright notice,
+
+  *      this list of conditions and the following disclaimer.
+
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+
+  *      this list of conditions and the following disclaimer in the documentation
+
+  *      and/or other materials provided with the distribution.
+
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+
+  *      may be used to endorse or promote products derived from this software
+
+  *      without specific prior written permission.
+
+  *
+
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  *
+
+  ******************************************************************************
+
+  */
+
+#ifndef __BL602_GPIO_H__
+#define __BL602_GPIO_H__
+
+typedef enum {
+    GLB_GPIO_PIN_0 = 0,
+    GLB_GPIO_PIN_1,
+    GLB_GPIO_PIN_2,
+    GLB_GPIO_PIN_3,
+    GLB_GPIO_PIN_4,
+    GLB_GPIO_PIN_5,
+    GLB_GPIO_PIN_6,
+    GLB_GPIO_PIN_7,
+    GLB_GPIO_PIN_8,
+    GLB_GPIO_PIN_9,
+    GLB_GPIO_PIN_10,
+    GLB_GPIO_PIN_11,
+    GLB_GPIO_PIN_12,
+    GLB_GPIO_PIN_13,
+    GLB_GPIO_PIN_14,
+    GLB_GPIO_PIN_15,
+    GLB_GPIO_PIN_16,
+    GLB_GPIO_PIN_17,
+    GLB_GPIO_PIN_18,
+    GLB_GPIO_PIN_19,
+    GLB_GPIO_PIN_20,
+    GLB_GPIO_PIN_21,
+    GLB_GPIO_PIN_22,
+    GLB_GPIO_PIN_MAX,
+} GLB_GPIO_Type;
+
+#define GPIO_MODE_INPUT  ((uint32_t)0x00000000U) /*!< Input Floating Mode                   */
+#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode                 */
+#define GPIO_MODE_AF     ((uint32_t)0x00000002U) /*!< Alternate function                    */
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function                       */
+#define GPIO_PULL_UP     ((uint32_t)0x00000000U) /*!< GPIO pull up                          */
+#define GPIO_PULL_DOWN   ((uint32_t)0x00000001U) /*!< GPIO pull down                        */
+#define GPIO_PULL_NONE   ((uint32_t)0x00000002U) /*!< GPIO no pull up or down               */
+
+typedef enum {
+    GPIO_FUN_SDIO = 1,
+    GPIO_FUN_FLASH = 2,
+    GPIO_FUN_SPI = 4,
+    GPIO_FUN_I2C = 6,
+    GPIO_FUN_UART = 7,
+    GPIO_FUN_PWM = 8,
+    GPIO_FUN_EXT_PA = 9,
+    GPIO_FUN_ANALOG = 10,
+    GPIO_FUN_SWGPIO = 11,
+    GPIO_FUN_GPIO = 11,
+    GPIO_FUN_JTAG = 14,
+    GPIO_FUN_UART0_RTS = 0x70,
+    GPIO_FUN_UART0_CTS = 0x71,
+    GPIO_FUN_UART0_TX = 0x72,
+    GPIO_FUN_UART0_RX = 0x73,
+    GPIO_FUN_UART1_RTS = 0x74,
+    GPIO_FUN_UART1_CTS = 0x75,
+    GPIO_FUN_UART1_TX = 0x76,
+    GPIO_FUN_UART1_RX = 0x77,
+    GPIO_FUN_GPIO_OUTPUT = 0x80,
+    GPIO_FUN_GPIO_INPUT = 0x81,
+    GPIO_FUN_UNUSED = 255,
+} GLB_GPIO_FUNC_Type;
+
+typedef struct
+{
+    uint8_t gpioPin;
+    uint8_t gpioFun;
+    uint8_t gpioMode;
+    uint8_t pullType;
+    uint8_t drive;
+    uint8_t smtCtrl;
+} GLB_GPIO_Cfg_Type;
+
+/* GPIO0 function definition */
+#define GPIO0_FUN_SDIO_CLK          1
+#define GPIO0_FUN_SF_D1             2
+#define GPIO0_FUN_UNUSED3           3
+#define GPIO0_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO0_FUN_UNUSED5           5
+#define GPIO0_FUN_I2C_SCL           6
+#define GPIO0_FUN_UART_SIG0         7
+#define GPIO0_FUN_PWM_CH0           8
+#define GPIO0_FUN_FEM_GPIO_0        9
+#define GPIO0_FUN_ATEST_IN          10
+#define GPIO0_FUN_SWGPIO_0          11
+#define GPIO0_FUN_E21_TMS           14
+/* GPIO1 function definition */
+#define GPIO1_FUN_SDIO_CMD          1
+#define GPIO1_FUN_SF_D2             2
+#define GPIO1_FUN_UNUSED3           3
+#define GPIO1_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO1_FUN_UNUSED5           5
+#define GPIO1_FUN_I2C_SDA           6
+#define GPIO1_FUN_UART_SIG1         7
+#define GPIO1_FUN_PWM_CH1           8
+#define GPIO1_FUN_FEM_GPIO_1        9
+#define GPIO1_FUN_ATEST_IP          10
+#define GPIO1_FUN_SWGPIO_1          11
+#define GPIO1_FUN_E21_TDI           14
+/* GPIO2 function definition */
+#define GPIO2_FUN_SDIO_DAT0  1
+#define GPIO2_FUN_SF_D3      2
+#define GPIO2_FUN_UNUSED3    3
+#define GPIO2_FUN_SPI_SS     4
+#define GPIO2_FUN_UNUSED5    5
+#define GPIO2_FUN_I2C_SCL    6
+#define GPIO2_FUN_UART_SIG2  7
+#define GPIO2_FUN_PWM_CH2    8
+#define GPIO2_FUN_FEM_GPIO_2 9
+#define GPIO2_FUN_ATEST_QN   10
+#define GPIO2_FUN_SWGPIO_2   11
+#define GPIO2_FUN_E21_TCK    14
+/* GPIO3 function definition */
+#define GPIO3_FUN_SDIO_DAT1  1
+#define GPIO3_FUN_UNUSED2    2
+#define GPIO3_FUN_UNUSED3    3
+#define GPIO3_FUN_SPI_SCLK   4
+#define GPIO3_FUN_UNUSED5    5
+#define GPIO3_FUN_I2C_SDA    6
+#define GPIO3_FUN_UART_SIG3  7
+#define GPIO3_FUN_PWM_CH3    8
+#define GPIO3_FUN_FEM_GPIO_3 9
+#define GPIO3_FUN_ATEST_QP   10
+#define GPIO3_FUN_SWGPIO_3   11
+#define GPIO3_FUN_E21_TDO    14
+/* GPIO4 function definition */
+#define GPIO4_FUN_SDIO_DAT2         1
+#define GPIO4_FUN_UNUSED2           2
+#define GPIO4_FUN_UNUSED3           3
+#define GPIO4_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO4_FUN_UNUSED5           5
+#define GPIO4_FUN_I2C_SCL           6
+#define GPIO4_FUN_UART_SIG4         7
+#define GPIO4_FUN_PWM_CH4           8
+#define GPIO4_FUN_FEM_GPIO_0        9
+#define GPIO4_FUN_GPIP_CH1          10
+#define GPIO4_FUN_SWGPIO_4          11
+#define GPIO4_FUN_E21_TMS           14
+/* GPIO5 function definition */
+#define GPIO5_FUN_SDIO_DAT3         1
+#define GPIO5_FUN_UNUSED2           2
+#define GPIO5_FUN_UNUSED3           3
+#define GPIO5_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO5_FUN_UNUSED5           5
+#define GPIO5_FUN_I2C_SDA           6
+#define GPIO5_FUN_UART_SIG5         7
+#define GPIO5_FUN_PWM_CH0           8
+#define GPIO5_FUN_FEM_GPIO_1        9
+#define GPIO5_FUN_GPIP_CH4          10
+#define GPIO5_FUN_SWGPIO_5          11
+#define GPIO5_FUN_E21_TDI           14
+/* GPIO6 function definition */
+#define GPIO6_FUN_UNUSED1    1
+#define GPIO6_FUN_UNUSED2    2
+#define GPIO6_FUN_UNUSED3    3
+#define GPIO6_FUN_SPI_SS     4
+#define GPIO6_FUN_UNUSED5    5
+#define GPIO6_FUN_I2C_SCL    6
+#define GPIO6_FUN_UART_SIG6  7
+#define GPIO6_FUN_PWM_CH1    8
+#define GPIO6_FUN_FEM_GPIO_2 9
+#define GPIO6_FUN_GPIP_CH5   10
+#define GPIO6_FUN_SWGPIO_6   11
+#define GPIO6_FUN_E21_TCK    14
+/* GPIO7 function definition */
+#define GPIO7_FUN_UNUSED1    1
+#define GPIO7_FUN_UNUSED2    2
+#define GPIO7_FUN_UNUSED3    3
+#define GPIO7_FUN_SPI_SCLK   4
+#define GPIO7_FUN_UNUSED5    5
+#define GPIO7_FUN_I2C_SDA    6
+#define GPIO7_FUN_UART_SIG7  7
+#define GPIO7_FUN_PWM_CH2    8
+#define GPIO7_FUN_FEM_GPIO_3 9
+#define GPIO7_FUN_UNUSED10   10
+#define GPIO7_FUN_SWGPIO_7   11
+#define GPIO7_FUN_E21_TDO    14
+/* GPIO8 function definition */
+#define GPIO8_FUN_UNUSED1           1
+#define GPIO8_FUN_UNUSED2           2
+#define GPIO8_FUN_UNUSED3           3
+#define GPIO8_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO8_FUN_UNUSED5           5
+#define GPIO8_FUN_I2C_SCL           6
+#define GPIO8_FUN_UART_SIG0         7
+#define GPIO8_FUN_PWM_CH3           8
+#define GPIO8_FUN_FEM_GPIO_0        9
+#define GPIO8_FUN_UNUSED10          10
+#define GPIO8_FUN_SWGPIO_8          11
+#define GPIO8_FUN_E21_TMS           14
+/* GPIO9 function definition */
+#define GPIO9_FUN_UNUSED1           1
+#define GPIO9_FUN_UNUSED2           2
+#define GPIO9_FUN_UNUSED3           3
+#define GPIO9_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO9_FUN_UNUSED5           5
+#define GPIO9_FUN_I2C_SDA           6
+#define GPIO9_FUN_UART_SIG1         7
+#define GPIO9_FUN_PWM_CH4           8
+#define GPIO9_FUN_FEM_GPIO_1        9
+#define GPIO9_FUN_GPIP_CH6_GPIP_CH7 10
+#define GPIO9_FUN_SWGPIO_9          11
+#define GPIO9_FUN_E21_TDI           14
+/* GPIO10 function definition */
+#define GPIO10_FUN_UNUSED1                   1
+#define GPIO10_FUN_UNUSED2                   2
+#define GPIO10_FUN_UNUSED3                   3
+#define GPIO10_FUN_SPI_SS                    4
+#define GPIO10_FUN_UNUSED5                   5
+#define GPIO10_FUN_I2C_SCL                   6
+#define GPIO10_FUN_UART_SIG2                 7
+#define GPIO10_FUN_PWM_CH0                   8
+#define GPIO10_FUN_FEM_GPIO_2                9
+#define GPIO10_FUN_MICBIAS_GPIP_CH8_GPIP_CH9 10
+#define GPIO10_FUN_SWGPIO_10                 11
+#define GPIO10_FUN_E21_TCK                   14
+/* GPIO11 function definition */
+#define GPIO11_FUN_UNUSED1             1
+#define GPIO11_FUN_UNUSED2             2
+#define GPIO11_FUN_UNUSED3             3
+#define GPIO11_FUN_SPI_SCLK            4
+#define GPIO11_FUN_UNUSED5             5
+#define GPIO11_FUN_I2C_SDA             6
+#define GPIO11_FUN_UART_SIG3           7
+#define GPIO11_FUN_PWM_CH1             8
+#define GPIO11_FUN_FEM_GPIO_3          9
+#define GPIO11_FUN_IRLED_OUT_GPIP_CH10 10
+#define GPIO11_FUN_SWGPIO_11           11
+#define GPIO11_FUN_E21_TDO             14
+/* GPIO12 function definition */
+#define GPIO12_FUN_UNUSED1                 1
+#define GPIO12_FUN_UNUSED2                 2
+#define GPIO12_FUN_UNUSED3                 3
+#define GPIO12_FUN_SPI_MOSI_SPI_MISO       4
+#define GPIO12_FUN_UNUSED5                 5
+#define GPIO12_FUN_I2C_SCL                 6
+#define GPIO12_FUN_UART_SIG4               7
+#define GPIO12_FUN_PWM_CH2                 8
+#define GPIO12_FUN_FEM_GPIO_0              9
+#define GPIO12_FUN_GPIP_CH0_GPADC_VREF_EXT 10
+#define GPIO12_FUN_SWGPIO_12               11
+#define GPIO12_FUN_E21_TMS                 14
+/* GPIO13 function definition */
+#define GPIO13_FUN_UNUSED1           1
+#define GPIO13_FUN_UNUSED2           2
+#define GPIO13_FUN_UNUSED3           3
+#define GPIO13_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO13_FUN_UNUSED5           5
+#define GPIO13_FUN_I2C_SDA           6
+#define GPIO13_FUN_UART_SIG5         7
+#define GPIO13_FUN_PWM_CH3           8
+#define GPIO13_FUN_FEM_GPIO_1        9
+#define GPIO13_FUN_GPIP_CH3          10
+#define GPIO13_FUN_SWGPIO_13         11
+#define GPIO13_FUN_E21_TDI           14
+/* GPIO14 function definition */
+#define GPIO14_FUN_UNUSED1    1
+#define GPIO14_FUN_UNUSED2    2
+#define GPIO14_FUN_UNUSED3    3
+#define GPIO14_FUN_SPI_SS     4
+#define GPIO14_FUN_UNUSED5    5
+#define GPIO14_FUN_I2C_SCL    6
+#define GPIO14_FUN_UART_SIG6  7
+#define GPIO14_FUN_PWM_CH4    8
+#define GPIO14_FUN_FEM_GPIO_2 9
+#define GPIO14_FUN_GPIP_CH2   10
+#define GPIO14_FUN_SWGPIO_14  11
+#define GPIO14_FUN_E21_TCK    14
+/* GPIO15 function definition */
+#define GPIO15_FUN_UNUSED1                 1
+#define GPIO15_FUN_UNUSED2                 2
+#define GPIO15_FUN_UNUSED3                 3
+#define GPIO15_FUN_SPI_SCLK                4
+#define GPIO15_FUN_UNUSED5                 5
+#define GPIO15_FUN_I2C_SDA                 6
+#define GPIO15_FUN_UART_SIG7               7
+#define GPIO15_FUN_PWM_CH0                 8
+#define GPIO15_FUN_FEM_GPIO_3              9
+#define GPIO15_FUN_PSW_IRRCV_OUT_GPIP_CH11 10
+#define GPIO15_FUN_SWGPIO_15               11
+#define GPIO15_FUN_E21_TDO                 14
+/* GPIO16 function definition */
+#define GPIO16_FUN_UNUSED1           1
+#define GPIO16_FUN_UNUSED2           2
+#define GPIO16_FUN_UNUSED3           3
+#define GPIO16_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO16_FUN_UNUSED5           5
+#define GPIO16_FUN_I2C_SCL           6
+#define GPIO16_FUN_UART_SIG0         7
+#define GPIO16_FUN_PWM_CH1           8
+#define GPIO16_FUN_FEM_GPIO_0        9
+#define GPIO16_FUN_UNUSED10          10
+#define GPIO16_FUN_SWGPIO_16         11
+#define GPIO16_FUN_E21_TMS           14
+/* GPIO17 function definition */
+#define GPIO17_FUN_UNUSED1           1
+#define GPIO17_FUN_SF_D3             2
+#define GPIO17_FUN_UNUSED3           3
+#define GPIO17_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO17_FUN_UNUSED5           5
+#define GPIO17_FUN_I2C_SDA           6
+#define GPIO17_FUN_UART_SIG1         7
+#define GPIO17_FUN_PWM_CH2           8
+#define GPIO17_FUN_FEM_GPIO_1        9
+#define GPIO17_FUN_PMIP_DC_TP_OUT    10
+#define GPIO17_FUN_SWGPIO_17         11
+#define GPIO17_FUN_E21_TDI           14
+/* GPIO18 function definition */
+#define GPIO18_FUN_UNUSED1    1
+#define GPIO18_FUN_SF_D2      2
+#define GPIO18_FUN_UNUSED3    3
+#define GPIO18_FUN_SPI_SS     4
+#define GPIO18_FUN_UNUSED5    5
+#define GPIO18_FUN_I2C_SCL    6
+#define GPIO18_FUN_UART_SIG2  7
+#define GPIO18_FUN_PWM_CH3    8
+#define GPIO18_FUN_FEM_GPIO_2 9
+#define GPIO18_FUN_UNUSED10   10
+#define GPIO18_FUN_SWGPIO_18  11
+#define GPIO18_FUN_E21_TCK    14
+/* GPIO19 function definition */
+#define GPIO19_FUN_UNUSED1    1
+#define GPIO19_FUN_SF_D1      2
+#define GPIO19_FUN_UNUSED3    3
+#define GPIO19_FUN_SPI_SCLK   4
+#define GPIO19_FUN_UNUSED5    5
+#define GPIO19_FUN_I2C_SDA    6
+#define GPIO19_FUN_UART_SIG3  7
+#define GPIO19_FUN_PWM_CH4    8
+#define GPIO19_FUN_FEM_GPIO_3 9
+#define GPIO19_FUN_UNUSED10   10
+#define GPIO19_FUN_SWGPIO_19  11
+#define GPIO19_FUN_E21_TDO    14
+/* GPIO20 function definition */
+#define GPIO20_FUN_UNUSED1           1
+#define GPIO20_FUN_SF_D0             2
+#define GPIO20_FUN_UNUSED3           3
+#define GPIO20_FUN_SPI_MOSI_SPI_MISO 4
+#define GPIO20_FUN_UNUSED5           5
+#define GPIO20_FUN_I2C_SCL           6
+#define GPIO20_FUN_UART_SIG4         7
+#define GPIO20_FUN_PWM_CH0           8
+#define GPIO20_FUN_FEM_GPIO_0        9
+#define GPIO20_FUN_UNUSED10          10
+#define GPIO20_FUN_SWGPIO_20         11
+#define GPIO20_FUN_E21_TMS           14
+/* GPIO21 function definition */
+#define GPIO21_FUN_UNUSED1           1
+#define GPIO21_FUN_SF_CS             2
+#define GPIO21_FUN_UNUSED3           3
+#define GPIO21_FUN_SPI_MISO_SPI_MOSI 4
+#define GPIO21_FUN_UNUSED5           5
+#define GPIO21_FUN_I2C_SDA           6
+#define GPIO21_FUN_UART_SIG5         7
+#define GPIO21_FUN_PWM_CH1           8
+#define GPIO21_FUN_FEM_GPIO_1        9
+#define GPIO21_FUN_UNUSED10          10
+#define GPIO21_FUN_SWGPIO_21         11
+#define GPIO21_FUN_E21_TDI           14
+/* GPIO22 function definition */
+#define GPIO22_FUN_UNUSED1    1
+#define GPIO22_FUN_SF_CLK_OUT 2
+#define GPIO22_FUN_UNUSED3    3
+#define GPIO22_FUN_SPI_SS     4
+#define GPIO22_FUN_UNUSED5    5
+#define GPIO22_FUN_I2C_SCL    6
+#define GPIO22_FUN_UART_SIG6  7
+#define GPIO22_FUN_PWM_CH2    8
+#define GPIO22_FUN_FEM_GPIO_2 9
+#define GPIO22_FUN_UNUSED10   10
+#define GPIO22_FUN_SWGPIO_22  11
+#define GPIO22_FUN_E21_TCK    14
+
+#endif /*__BL602_GPIO_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_hbn.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_hbn.h
new file mode 100755
index 0000000000..07e6874274
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_hbn.h
@@ -0,0 +1,497 @@
+/**
+  ******************************************************************************
+  * @file    bl602_hbn.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_HBN_H__
+#define __BL602_HBN_H__
+
+#include "hbn_reg.h"
+#include "bl602_aon.h"
+#include "bflb_sflash.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief HBN PIR interrupt configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type lowIntEn;  /*!< Low will trigger interrupt */
+    BL_Fun_Type highIntEn; /*!< High will trigger interrupt */
+} HBN_PIR_INT_CFG_Type;
+
+/**
+ *  @brief HBN PIR low pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */
+    HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */
+} HBN_PIR_LPF_Type;
+
+/**
+ *  @brief HBN PIR high pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */
+    HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */
+    HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */
+} HBN_PIR_HPF_Type;
+
+/**
+ *  @brief HBN BOR threshold type definition
+ */
+typedef enum {
+    HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */
+    HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */
+} HBN_BOR_THRES_Type;
+
+/**
+ *  @brief HBN BOR mode type definition
+ */
+typedef enum {
+    HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */
+    HBN_BOR_MODE_POR_RELEVANT,    /*!< POR is relevant to BOR */
+} HBN_BOR_MODE_Type;
+
+/**
+ *  @brief HBN 32K clock type definition
+ */
+typedef enum {
+    HBN_32K_RC = 0,  /*!< HBN use rc 32k */
+    HBN_32K_XTAL,    /*!< HBN use xtal 32k */
+    HBN_32K_DIG = 3, /*!< HBN use dig 32k */
+} HBN_32K_CLK_Type;
+
+/**
+ *  @brief HBN xclk clock type definition
+ */
+typedef enum {
+    HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */
+    HBN_XCLK_CLK_XTAL,  /*!< use XTAL as xclk clock */
+} HBN_XCLK_CLK_Type;
+
+/**
+ *  @brief HBN root clock type definition
+ */
+typedef enum {
+    HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */
+    HBN_ROOT_CLK_XTAL,  /*!< use XTAL as root clock */
+    HBN_ROOT_CLK_PLL,   /*!< use PLL as root clock */
+} HBN_ROOT_CLK_Type;
+
+/**
+ *  @brief HBN UART clock type definition
+ */
+typedef enum {
+    HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */
+    HBN_UART_CLK_160M,     /*!< Select 160M as UART clock */
+} HBN_UART_CLK_Type;
+
+/**
+ *  @brief HBN RTC interrupt delay type definition
+ */
+typedef enum {
+    HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */
+    HBN_RTC_INT_DELAY_0T = 1,  /*!< HBN RTC interrupt delay 0T */
+} HBN_RTC_INT_Delay_Type;
+
+/**
+ *  @brief HBN interrupt type definition
+ */
+typedef enum {
+    HBN_INT_GPIO7 = 0,   /*!< HBN interrupt type: GPIO7 */
+    HBN_INT_GPIO8 = 1,   /*!< HBN interrupt type: GPIO8 */
+    HBN_INT_RTC = 16,    /*!< HBN interrupt type: RTC */
+    HBN_INT_PIR = 17,    /*!< HBN interrupt type: PIR */
+    HBN_INT_BOR = 18,    /*!< HBN interrupt type: BOR */
+    HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */
+    HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */
+} HBN_INT_Type;
+
+/**
+ *  @brief HBN acomp interrupt type definition
+ */
+typedef enum {
+    HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */
+    HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */
+} HBN_ACOMP_INT_EDGE_Type;
+
+/**
+ *  @brief HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< HBN GPIO INT trigger type: sync falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< HBN GPIO INT trigger type: sync rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< HBN GPIO INT trigger type: sync low level trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< HBN GPIO INT trigger type: sync high level trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< HBN GPIO INT trigger type: async rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< HBN GPIO INT trigger type: async low level trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< HBN GPIO INT trigger type: async high level trigger */
+} HBN_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT0_INT_GPIO7 = 0, /*!< HBN out 0 interrupt type: GPIO7 */
+    HBN_OUT0_INT_GPIO8,     /*!< HBN out 0 interrupt type: GPIO8 */
+    HBN_OUT0_INT_RTC,       /*!< HBN out 0 interrupt type: RTC */
+} HBN_OUT0_INT_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT1_INT_PIR,    /*!< HBN out 1 interrupt type: PIR */
+    HBN_OUT1_INT_BOR,    /*!< HBN out 1 interrupt type: BOR */
+    HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */
+    HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */
+} HBN_OUT1_INT_Type;
+
+/**
+ *  @brief HBN LDO level type definition
+ */
+typedef enum {
+    HBN_LDO_LEVEL_0P60V = 0,  /*!< HBN LDO voltage 0.60V */
+    HBN_LDO_LEVEL_0P65V = 1,  /*!< HBN LDO voltage 0.65V */
+    HBN_LDO_LEVEL_0P70V = 2,  /*!< HBN LDO voltage 0.70V */
+    HBN_LDO_LEVEL_0P75V = 3,  /*!< HBN LDO voltage 0.75V */
+    HBN_LDO_LEVEL_0P80V = 4,  /*!< HBN LDO voltage 0.80V */
+    HBN_LDO_LEVEL_0P85V = 5,  /*!< HBN LDO voltage 0.85V */
+    HBN_LDO_LEVEL_0P90V = 6,  /*!< HBN LDO voltage 0.90V */
+    HBN_LDO_LEVEL_0P95V = 7,  /*!< HBN LDO voltage 0.95V */
+    HBN_LDO_LEVEL_1P00V = 8,  /*!< HBN LDO voltage 1.00V */
+    HBN_LDO_LEVEL_1P05V = 9,  /*!< HBN LDO voltage 1.05V */
+    HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */
+    HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */
+    HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */
+    HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */
+    HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */
+    HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */
+} HBN_LDO_LEVEL_Type;
+
+/**
+ *  @brief HBN level type definition
+ */
+typedef enum {
+    HBN_LEVEL_0, /*!< HBN pd_core */
+    HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */
+    HBN_LEVEL_2, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */
+    HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */
+} HBN_LEVEL_Type;
+
+/**
+ *  @brief HBN BOR configuration type definition
+ */
+typedef struct
+{
+    uint8_t enableBor;      /*!< Enable BOR or not */
+    uint8_t enableBorInt;   /*!< Enable BOR interrupt or not */
+    uint8_t borThreshold;   /*!< BOR threshold */
+    uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */
+} HBN_BOR_CFG_Type;
+
+/**
+ *  @brief HBN APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t useXtal32k;                     /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint32_t sleepTime;                     /*!< HBN sleep time */
+    uint8_t gpioWakeupSrc;                  /*!< GPIO Wakeup source */
+    HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
+    spi_flash_cfg_type *flashCfg;           /*!< Flash config pointer, used when power down flash */
+    HBN_LEVEL_Type hbnLevel;                /*!< HBN level */
+    HBN_LDO_LEVEL_Type ldoLevel;            /*!< LDO level */
+} HBN_APP_CFG_Type;
+
+/*@} end of group HBN_Public_Types */
+
+/** @defgroup  HBN_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  HBN_PIR_LPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \
+                                   ((type) == HBN_PIR_LPF_DIV2))
+
+/** @defgroup  HBN_PIR_HPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \
+                                   ((type) == HBN_PIR_HPF_METHOD1) || \
+                                   ((type) == HBN_PIR_HPF_METHOD2))
+
+/** @defgroup  HBN_BOR_THRES_TYPE
+ *  @{
+ */
+#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \
+                                     ((type) == HBN_BOR_THRES_2P4V))
+
+/** @defgroup  HBN_BOR_MODE_TYPE
+ *  @{
+ */
+#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \
+                                    ((type) == HBN_BOR_MODE_POR_RELEVANT))
+
+/** @defgroup  HBN_32K_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) ||   \
+                                   ((type) == HBN_32K_XTAL) || \
+                                   ((type) == HBN_32K_DIG))
+
+/** @defgroup  HBN_XCLK_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \
+                                    ((type) == HBN_XCLK_CLK_XTAL))
+
+/** @defgroup  HBN_ROOT_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \
+                                    ((type) == HBN_ROOT_CLK_XTAL) ||  \
+                                    ((type) == HBN_ROOT_CLK_PLL))
+
+/** @defgroup  HBN_UART_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \
+                                    ((type) == HBN_UART_CLK_160M))
+
+/** @defgroup  HBN_RTC_INT_DELAY_TYPE
+ *  @{
+ */
+#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \
+                                         ((type) == HBN_RTC_INT_DELAY_0T))
+
+/** @defgroup  HBN_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO7) ||  \
+                               ((type) == HBN_INT_GPIO8) ||  \
+                               ((type) == HBN_INT_RTC) ||    \
+                               ((type) == HBN_INT_PIR) ||    \
+                               ((type) == HBN_INT_BOR) ||    \
+                               ((type) == HBN_INT_ACOMP0) || \
+                               ((type) == HBN_INT_ACOMP1))
+
+/** @defgroup  HBN_ACOMP_INT_EDGE_TYPE
+ *  @{
+ */
+#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \
+                                          ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE))
+
+/** @defgroup  HBN_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  HBN_OUT0_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO7) || \
+                                    ((type) == HBN_OUT0_INT_GPIO8) || \
+                                    ((type) == HBN_OUT0_INT_RTC))
+
+/** @defgroup  HBN_OUT1_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) ||    \
+                                    ((type) == HBN_OUT1_INT_BOR) ||    \
+                                    ((type) == HBN_OUT1_INT_ACOMP0) || \
+                                    ((type) == HBN_OUT1_INT_ACOMP1))
+
+/** @defgroup  HBN_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P65V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P70V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P75V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P80V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P85V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P90V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P95V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P00V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P05V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P10V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P15V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P20V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P25V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P30V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P35V))
+
+/** @defgroup  HBN_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \
+                                 ((type) == HBN_LEVEL_1) || \
+                                 ((type) == HBN_LEVEL_2) || \
+                                 ((type) == HBN_LEVEL_3))
+
+/*@} end of group HBN_Public_Constants */
+
+/** @defgroup  HBN_Public_Macros
+ *  @{
+ */
+#define HBN_RAM_SIZE           (4 * 1024)
+#define HBN_RTC_COMP_BIT0_39   0x01
+#define HBN_RTC_COMP_BIT0_23   0x02
+#define HBN_RTC_COMP_BIT13_39  0x04
+#define HBN_STATUS_ENTER_FLAG  0x4e424845
+#define HBN_STATUS_WAKEUP_FLAG 0x4e424857
+#define HBN_WAKEUP_GPIO_NONE   0x00
+#define HBN_WAKEUP_GPIO_7      0x01
+#define HBN_WAKEUP_GPIO_8      0x02
+#define HBN_WAKEUP_GPIO_ALL    0x03
+
+/*@} end of group HBN_Public_Macros */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void);
+void HBN_OUT1_IRQHandler(void);
+#endif
+/*----------*/
+void HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg);
+void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg);
+void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
+BL_Err_Type HBN_Reset(void);
+BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv);
+BL_Err_Type HBN_Disable(void);
+/*----------*/
+BL_Err_Type HBN_PIR_Enable(void);
+BL_Err_Type HBN_PIR_Disable(void);
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg);
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf);
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf);
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold);
+uint16_t HBN_Get_PIR_Threshold(void);
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval);
+uint16_t HBN_Get_PIR_Interval(void);
+/*----------*/
+BL_Sts_Type HBN_Get_BOR_OUT_State(void);
+BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode);
+/*----------*/
+BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+/*----------*/
+BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
+BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk);
+HBN_ROOT_CLK_Type HBN_Get_Root_CLK_Sel(void);
+BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk);
+/*----------*/
+BL_Err_Type HBN_Set_HRAM_slp(void);
+BL_Err_Type HBN_Set_HRAM_Ret(void);
+/*----------*/
+uint32_t HBN_Get_Status_Flag(void);
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag);
+uint32_t HBN_Get_Wakeup_Addr(void);
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr);
+/*----------*/
+BL_Err_Type HBN_Clear_RTC_Counter(void);
+BL_Err_Type HBN_Enable_RTC_Counter(void);
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode);
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh);
+BL_Err_Type HBN_Clear_RTC_INT(void);
+/*----------*/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType);
+BL_Err_Type HBN_GPIO_INT_Disable(void);
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType);
+uint8_t HBN_Get_Pin_Wakeup_Mode(void);
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType);
+BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable);
+BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg);
+BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal);
+/*----------*/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+/*----------*/
+BL_Err_Type HBN_Enable_BOR_IRQ(void);
+BL_Err_Type HBN_Disable_BOR_IRQ(void);
+/*----------*/
+BL_Err_Type HBN_Out0_IRQHandler_Install(void);
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type HBN_Out1_IRQHandler_Install(void);
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn,
+                                   BL_Fun_Type dlyEn, uint8_t dlySec);
+/*----------*/
+BL_Err_Type HBN_Power_On_Xtal_32K(void);
+BL_Err_Type HBN_Power_Off_Xtal_32K(void);
+BL_Err_Type HBN_Power_On_RC32K(void);
+BL_Err_Type HBN_Power_Off_RC32K(void);
+BL_Err_Type HBN_Trim_RC32K(void);
+BL_Err_Type HBN_Set_Embedded_Flash_Pullup(uint8_t enable);
+BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg);
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_HBN_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_l1c.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_l1c.h
new file mode 100755
index 0000000000..e8fccde77e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_l1c.h
@@ -0,0 +1,189 @@
+/**
+  ******************************************************************************
+  * @file    bl602_l1c.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_L1C_H__
+#define __BL602_L1C_H__
+
+#include "l1c_reg.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  L1C
+ *  @{
+ */
+
+/** @defgroup  L1C_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief L1C configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type wrapDis;  /*!< wrap disable */
+    BL_Fun_Type bypassEn; /*!< bypass cache enable */
+    uint8_t wayDis;       /*!< Disable part of cache ways & used as ITCM */
+    BL_Fun_Type cntEn;    /*!< l1c count enable */
+} L1C_CACHE_Cfg_Type;
+
+/**
+ *  @brief L1C BMX arb mode type definition
+ */
+typedef enum {
+    L1C_BMX_ARB_FIX,         /*!< 0->fix */
+    L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
+    L1C_BMX_ARB_RANDOM,      /*!< 3->random */
+} L1C_BMX_ARB_Type;
+
+/**
+ *  @brief L1C BMX configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t timeoutEn;       /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+    BL_Fun_Type errEn;       /*!< Bus error response enable */
+    L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+} L1C_BMX_Cfg_Type;
+
+/**
+ *  @brief L1C BMX bus err type definition
+ */
+typedef enum {
+    L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+    L1C_BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
+} L1C_BMX_BUS_ERR_Type;
+
+/**
+ *  @brief L1C BMX bus err interrupt type definition
+ */
+typedef enum {
+    L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */
+    L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */
+} L1C_BMX_ERR_INT_Type;
+
+/**
+ *  @brief L1C BMX time out interrupt type definition
+ */
+typedef enum {
+    L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */
+    L1C_BMX_TO_INT_ALL,     /*!< L1C_BMX timeout interrupt max num */
+} L1C_BMX_TO_INT_Type;
+
+/*@} end of group L1C_Public_Types */
+
+/** @defgroup  L1C_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  L1C_BMX_ARB_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) ||         \
+                                   ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \
+                                   ((type) == L1C_BMX_ARB_RANDOM))
+
+/** @defgroup  L1C_BMX_BUS_ERR_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+                                       ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup  L1C_BMX_ERR_INT_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \
+                                       ((type) == L1C_BMX_ERR_INT_ALL))
+
+/** @defgroup  L1C_BMX_TO_INT_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \
+                                      ((type) == L1C_BMX_TO_INT_ALL))
+
+/*@} end of group L1C_Public_Constants */
+
+/** @defgroup  L1C_Public_Macros
+ *  @{
+ */
+#if 1
+/*NP config address */
+#define L1C_CONF_REG_NP        (L1C_BASE + 0x00)
+#define L1C_HIT_CNT_LSB_REG_NP (L1C_BASE + 0x04)
+#define L1C_HIT_CNT_MSB_REG_NP (L1C_BASE + 0x08)
+#define L1C_MISS_CNT_REG_NP    (L1C_BASE + 0x0C)
+/* Get miss and hit count */
+#define L1C_Get_Miss_Cnt_NP()    BL602_REG_RD(L1C_MISS_CNT_REG_NP)
+#define L1C_Get_Hit_Cnt_LSB_NP() BL602_REG_RD(L1C_HIT_CNT_LSB_REG_NP)
+#define L1C_Get_Hit_Cnt_MSB_NP() BL602_REG_RD(L1C_HIT_CNT_MSB_REG_NP)
+#endif
+
+/*@} end of group L1C_Public_Macros */
+
+/** @defgroup  L1C_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_ERR_IRQHandler(void);
+void L1C_BMX_TO_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap);
+BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal);
+BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable);
+/*----------*/
+BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg);
+BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void);
+BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void);
+BL_Err_Type L1C_BMX_BusErrResponse_Enable(void);
+BL_Err_Type L1C_BMX_BusErrResponse_Disable(void);
+BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType);
+uint32_t L1C_BMX_Get_Err_Addr(void);
+BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,
+                                                 intCallback_Type *cbFun);
+/*----------*/;
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_L1C_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pds.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pds.h
new file mode 100755
index 0000000000..6217f6f62b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_pds.h
@@ -0,0 +1,501 @@
+/**
+  ******************************************************************************
+  * @file    bl602_pds.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_PDS_H__
+#define __BL602_PDS_H__
+
+#include "pds_reg.h"
+#include "bl602_aon.h"
+#include "bl602_hbn.h"
+#include "bl602_common.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief PDS LDO level type definition
+ */
+typedef enum {
+    PDS_LDO_LEVEL_0P60V = 0,  /*!< PDS LDO voltage 0.60V */
+    PDS_LDO_LEVEL_0P65V = 1,  /*!< PDS LDO voltage 0.65V */
+    PDS_LDO_LEVEL_0P70V = 2,  /*!< PDS LDO voltage 0.70V */
+    PDS_LDO_LEVEL_0P75V = 3,  /*!< PDS LDO voltage 0.75V */
+    PDS_LDO_LEVEL_0P80V = 4,  /*!< PDS LDO voltage 0.80V */
+    PDS_LDO_LEVEL_0P85V = 5,  /*!< PDS LDO voltage 0.85V */
+    PDS_LDO_LEVEL_0P90V = 6,  /*!< PDS LDO voltage 0.90V */
+    PDS_LDO_LEVEL_0P95V = 7,  /*!< PDS LDO voltage 0.95V */
+    PDS_LDO_LEVEL_1P00V = 8,  /*!< PDS LDO voltage 1.00V */
+    PDS_LDO_LEVEL_1P05V = 9,  /*!< PDS LDO voltage 1.05V */
+    PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */
+    PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */
+    PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */
+    PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */
+    PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */
+    PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */
+} PDS_LDO_LEVEL_Type;
+
+/**
+ *  @brief PDS configuration type definition
+ */
+typedef struct
+{
+    uint32_t pdsStart      : 1; /*!< [0]PDS Start */
+    uint32_t sleepForever  : 1; /*!< [1]PDS sleep forever */
+    uint32_t xtalForceOff  : 1; /*!< [2]Power off xtal force */
+    uint32_t saveWiFiState : 1; /*!< [3]Save WIFI State Before Enter PDS */
+    uint32_t dcdc18Off     : 1; /*!< [4]power down dcdc18 during PDS */
+    uint32_t bgSysOff      : 1; /*!< [5]power down bg_sys during PDS */
+    uint32_t rsv6_7        : 2; /*!< [7:6]reserve */
+    uint32_t clkOff        : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
+    uint32_t memStby       : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
+    uint32_t rsv10         : 1; /*!< [10]reserve */
+    uint32_t isolation     : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
+    uint32_t waitXtalRdy   : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
+    uint32_t pdsPwrOff     : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
+    uint32_t xtalOff       : 1; /*!< [14]xtal power down during PDS */
+    uint32_t socEnbForceOn : 1; /*!< [15]pds_soc_enb always active */
+    uint32_t pdsRstSocEn   : 1; /*!< [16]pds_rst controlled by PDS */
+    uint32_t pdsRC32mOn    : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
+    uint32_t pdsLdoVselEn  : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
+    uint32_t rsv19_20      : 2; /*!< [20:19]reserve */
+    uint32_t wfiMask       : 1; /*!< [21]pds start condition mask np_wfi */
+    uint32_t ldo11Off      : 1; /*!< [22]power down ldo11 during PDS */
+    uint32_t rsv23         : 1; /*!< [23]reserve */
+    uint32_t pdsLdoVol     : 4; /*!< [27:24]LDO voltage value in PDS mode */
+    uint32_t pdsCtlRfSel   : 2; /*!< [29:28]select the way RF controlled by PDS */
+    uint32_t pdsCtlPllSel  : 2; /*!< [31:30]select the way PLL controlled by PDS */
+} PDS_CTL_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t cpuPwrOff   : 1; /*!< [0] */
+    uint32_t cpuRst      : 1; /*!< [1] */
+    uint32_t cpuMemStby  : 1; /*!< [2] */
+    uint32_t cpuGateClk  : 1; /*!< [3] */
+    uint32_t rsv4_11     : 8; /*!< [11:4]reserve */
+    uint32_t WbPwrOff    : 1; /*!< [12] */
+    uint32_t WbRst       : 1; /*!< [13] */
+    uint32_t WbMemStby   : 1; /*!< [14] */
+    uint32_t WbGateClk   : 1; /*!< [15] */
+    uint32_t rsv16_23    : 8; /*!< [23:16]reserve */
+    uint32_t MiscPwrOff  : 1; /*!< [24] */
+    uint32_t MiscRst     : 1; /*!< [25] */
+    uint32_t MiscMemStby : 1; /*!< [26] */
+    uint32_t MiscGateClk : 1; /*!< [27] */
+    uint32_t rsv28_31    : 4; /*!< [31:28]reserve */
+} PDS_CTL4_Type;
+
+/**
+ *  @brief PDS interrupt type definition
+ */
+typedef enum {
+    PDS_INT_WAKEUP = 0,                 /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */
+    PDS_INT_HBN_GPIO_IRRX_BLE_WIFI = 1, /*!< PDS in interrupt source HBN_Wakeup_Source/All_GPIO_Wakeup/IRRX/BLE_Wakeup_Eveent/WIFI_Wakeup_Event */
+    PDS_INT_RF_DONE = 2,                /*!< PDS RF done interrupt */
+    PDS_INT_PLL_DONE = 3,               /*!< PDS PLL done interrupt */
+    PDS_INT_MAX = 4,                    /*!< PDS int max number */
+} PDS_INT_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t forceCpuPwrOff    : 1;  /*!< [0]manual force NP power off */
+    uint32_t rsv1              : 1;  /*!< [1]reserve */
+    uint32_t forceWbPwrOff     : 1;  /*!< [2]manual force WB power off */
+    uint32_t rsv3              : 1;  /*!< [3]reserve */
+    uint32_t forceCpuIsoPwrOff : 1;  /*!< [4]manual force NP isolation */
+    uint32_t rsv5              : 1;  /*!< [5]reserve */
+    uint32_t forceWbIsoPwrOff  : 1;  /*!< [6]manual force WB isolation */
+    uint32_t rsv7              : 1;  /*!< [7]reserve */
+    uint32_t forceCpuPdsRst    : 1;  /*!< [8]manual force NP pds reset */
+    uint32_t rsv9              : 1;  /*!< [9]reserve */
+    uint32_t forceWbPdsRst     : 1;  /*!< [10]manual force WB pds reset */
+    uint32_t rsv11             : 1;  /*!< [11]reserve */
+    uint32_t forceCpuMemStby   : 1;  /*!< [12]manual force NP memory sleep */
+    uint32_t rsv13             : 1;  /*!< [13]reserve */
+    uint32_t forceWbMemStby    : 1;  /*!< [14]manual force WB memory sleep */
+    uint32_t rsv15             : 1;  /*!< [15]reserve */
+    uint32_t forceCpuGateClk   : 1;  /*!< [16]manual force NP clock gated */
+    uint32_t rsv17             : 1;  /*!< [17]reserve */
+    uint32_t forceWbGateClk    : 1;  /*!< [18]manual force WB clock gated */
+    uint32_t rsv19_31          : 12; /*!< [31:19]reserve */
+} PDS_CTL2_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t rsv0             : 1;  /*!< [0]reserve */
+    uint32_t forceMiscPwrOff  : 1;  /*!< [1]manual force MISC pwr_off */
+    uint32_t rsv2_3           : 2;  /*!< [3:2]reserve */
+    uint32_t forceMiscIsoEn   : 1;  /*!< [4]manual force MISC iso_en */
+    uint32_t rsv5_6           : 2;  /*!< [6:5]reserve */
+    uint32_t forceMiscPdsRst  : 1;  /*!< [7]manual force MISC pds_rst */
+    uint32_t rsv8_9           : 2;  /*!< [9:8]reserve */
+    uint32_t forceMiscMemStby : 1;  /*!< [10]manual force MISC mem_stby */
+    uint32_t rsv11_12         : 2;  /*!< [12:11]reserve */
+    uint32_t forceMiscGateClk : 1;  /*!< [13]manual force MISC gate_clk */
+    uint32_t rsv14_23         : 10; /*!< [23:14]reserve */
+    uint32_t CpuIsoEn         : 1;  /*!< [24]make NP isolated at PDS Sleep state */
+    uint32_t rsv25_26         : 2;  /*!< [26:25]reserve */
+    uint32_t WbIsoEn          : 1;  /*!< [27]make WB isolated at PDS Sleep state */
+    uint32_t rsv28_29         : 2;  /*!< [29:28]reserve */
+    uint32_t MiscIsoEn        : 1;  /*!< [30]make misc isolated at PDS Sleep state */
+    uint32_t rsv31            : 1;  /*!< [31]reserve */
+} PDS_CTL3_Type;
+
+/**
+ *  @brief PDS default level configuration type definition
+ */
+typedef struct
+{
+    PDS_CTL_Type pdsCtl;   /*!< PDS_CTL configuration */
+    PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */
+    PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */
+    PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */
+} PDS_DEFAULT_LV_CFG_Type;
+
+/**
+ *  @brief PDS PLL status type definition
+ */
+typedef enum {
+    PDS_PLL_STS_OFF = 0,   /*!< 2'b00 */
+    PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */
+    PDS_PLL_STS_PU = 2,    /*!< 2'b10 */
+    PDS_PLL_STS_RDY = 3,   /*!< 2'b11 */
+} PDS_PLL_STS_Type;
+
+/**
+ *  @brief PDS RF status type definition
+ */
+typedef enum {
+    PDS_RF_STS_OFF = 0,        /*!< 4'b0000 */
+    PDS_RF_STS_PU_MBG = 1,     /*!< 4'b0001 */
+    PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */
+    PDS_RF_STS_PU_SFREG = 7,   /*!< 4'b0111 */
+    PDS_RF_STS_WB_EN_AON = 15, /*!< 4'b1111 */
+} PDS_RF_STS_Type;
+
+/**
+ *  @brief PDS status type definition
+ */
+typedef enum {
+    PDS_STS_IDLE = 0,            /*!< 4'b0000 */
+    PDS_STS_ECG = 8,             /*!< 4'b1000 */
+    PDS_STS_ERST = 12,           /*!< 4'b1100 */
+    PDS_STS_EISO = 15,           /*!< 4'b1111 */
+    PDS_STS_POFF = 7,            /*!< 4'b0111 */
+    PDS_STS_PRE_BGON = 3,        /*!< 4'b0011 */
+    PDS_STS_PRE_BGON1 = 1,       /*!< 4'b0001 */
+    PDS_STS_BGON = 5,            /*!< 4'b0101 */
+    PDS_STS_CLK_SW_32M = 4,      /*!< 4'b0100 */
+    PDS_STS_PON_DCDC = 6,        /*!< 4'b0110 */
+    PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */
+    PDS_STS_PON = 10,            /*!< 4'b1010 */
+    PDS_STS_DISO = 2,            /*!< 4'b0010 */
+    PDS_STS_DCG = 13,            /*!< 4'b1101 */
+    PDS_STS_DRST = 11,           /*!< 4'b1011 */
+    PDS_STS_WAIT_EFUSE = 9,      /*!< 4'b1001 */
+} PDS_STS_Type;
+
+/**
+ *  @brief PDS RAM configuration type definition
+ */
+typedef struct
+{
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET  : 1;  /*!< [0]   0~16KB cpu_ram RET */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET : 1;  /*!< [1]   16~32KB cpu_ram RET */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET : 1;  /*!< [2]   32~48KB cpu_ram RET */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET : 1;  /*!< [3]   48~64KB cpu_ram RET */
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_SLP  : 1;  /*!< [4]   0~16KB cpu_ram SLP */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_SLP : 1;  /*!< [5]   16~32KB cpu_ram SLP */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_SLP : 1;  /*!< [6]   32~48KB cpu_ram SLP */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_SLP : 1;  /*!< [7]   48~64KB cpu_ram SLP */
+    uint32_t PDS_RAM_CFG_RSV                   : 24; /*!< [31:8]reserve */
+} PDS_RAM_CFG_Type;
+
+/**
+ *  @brief PLL XTAL type definition
+ */
+typedef enum {
+    PDS_PLL_XTAL_NONE,  /*!< XTAL is none */
+    PDS_PLL_XTAL_24M,   /*!< XTAL is 24M */
+    PDS_PLL_XTAL_32M,   /*!< XTAL is 32M */
+    PDS_PLL_XTAL_38P4M, /*!< XTAL is 38.4M */
+    PDS_PLL_XTAL_40M,   /*!< XTAL is 40M */
+    PDS_PLL_XTAL_26M,   /*!< XTAL is 26M */
+    PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */
+} PDS_PLL_XTAL_Type;
+
+/**
+ *  @brief PLL output clock type definition
+ */
+typedef enum {
+    PDS_PLL_CLK_480M, /*!< PLL output clock:480M */
+    PDS_PLL_CLK_240M, /*!< PLL output clock:240M */
+    PDS_PLL_CLK_192M, /*!< PLL output clock:192M */
+    PDS_PLL_CLK_160M, /*!< PLL output clock:160M */
+    PDS_PLL_CLK_120M, /*!< PLL output clock:120M */
+    PDS_PLL_CLK_96M,  /*!< PLL output clock:96M */
+    PDS_PLL_CLK_80M,  /*!< PLL output clock:80M */
+    PDS_PLL_CLK_48M,  /*!< PLL output clock:48M */
+    PDS_PLL_CLK_32M,  /*!< PLL output clock:32M */
+} PDS_PLL_CLK_Type;
+
+/**
+ *  @brief PDS level 0/1/2/3 mode HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync high level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async high level trigger */
+} PDS_AON_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief PDS APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t pdsLevel;                                 /*!< PDS level */
+    uint8_t turnOffRF;                                /*!< Wheather turn off RF */
+    uint8_t useXtal32k;                               /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint8_t pdsAonGpioWakeupSrc;                      /*!< PDS level 0/1/2/3 mode always on GPIO Wakeup source(HBN wakeup pin) */
+    PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0/1/2/3 mode always on GPIO Triger type(HBN wakeup pin) */
+    uint8_t powerDownFlash;                           /*!< Whether power down flash */
+    uint8_t turnOffFlashPad;                          /*!< Whether turn off embedded flash pad */
+    uint8_t ocramRetetion;                            /*!< Whether OCRAM Retention */
+    uint8_t turnoffPLL;                               /*!< Whether trun off PLL */
+    uint8_t xtalType;                                 /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
+    uint8_t flashContRead;                            /*!< Whether enable flash continue read */
+    uint32_t sleepTime;                               /*!< PDS sleep time */
+    spi_flash_cfg_type *flashCfg;                     /*!< Flash config pointer, used when power down flash */
+    PDS_LDO_LEVEL_Type ldoLevel;                      /*!< LDO level */
+    void (*preCbFun)(void);                           /*!< Pre callback function */
+    void (*postCbFun)(void);                          /*!< Post callback function */
+} PDS_APP_CFG_Type;
+
+/*@} end of group PDS_Public_Types */
+
+/** @defgroup  PDS_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  PDS_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P65V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P70V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P75V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P80V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P85V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P90V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P95V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P00V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P05V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P10V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P15V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P20V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P25V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P30V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P35V))
+
+/** @defgroup  PDS_INT_TYPE
+ *  @{
+ */
+#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) ||                 \
+                               ((type) == PDS_INT_HBN_GPIO_IRRX_BLE_WIFI) || \
+                               ((type) == PDS_INT_RF_DONE) ||                \
+                               ((type) == PDS_INT_PLL_DONE) ||               \
+                               ((type) == PDS_INT_MAX))
+
+/** @defgroup  PDS_PLL_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) ||   \
+                                   ((type) == PDS_PLL_STS_SFREG) || \
+                                   ((type) == PDS_PLL_STS_PU) ||    \
+                                   ((type) == PDS_PLL_STS_RDY))
+
+/** @defgroup  PDS_RF_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) ||        \
+                                  ((type) == PDS_RF_STS_PU_MBG) ||     \
+                                  ((type) == PDS_RF_STS_PU_LDO15RF) || \
+                                  ((type) == PDS_RF_STS_PU_SFREG) ||   \
+                                  ((type) == PDS_RF_STS_WB_EN_AON))
+
+/** @defgroup  PDS_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) ||           \
+                               ((type) == PDS_STS_ECG) ||            \
+                               ((type) == PDS_STS_ERST) ||           \
+                               ((type) == PDS_STS_EISO) ||           \
+                               ((type) == PDS_STS_POFF) ||           \
+                               ((type) == PDS_STS_PRE_BGON) ||       \
+                               ((type) == PDS_STS_PRE_BGON1) ||      \
+                               ((type) == PDS_STS_BGON) ||           \
+                               ((type) == PDS_STS_CLK_SW_32M) ||     \
+                               ((type) == PDS_STS_PON_DCDC) ||       \
+                               ((type) == PDS_STS_PON_LDO11_MISC) || \
+                               ((type) == PDS_STS_PON) ||            \
+                               ((type) == PDS_STS_DISO) ||           \
+                               ((type) == PDS_STS_DCG) ||            \
+                               ((type) == PDS_STS_DRST) ||           \
+                               ((type) == PDS_STS_WAIT_EFUSE))
+
+/** @defgroup  PDS_PLL_XTAL_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) ||  \
+                                    ((type) == PDS_PLL_XTAL_24M) ||   \
+                                    ((type) == PDS_PLL_XTAL_32M) ||   \
+                                    ((type) == PDS_PLL_XTAL_38P4M) || \
+                                    ((type) == PDS_PLL_XTAL_40M) ||   \
+                                    ((type) == PDS_PLL_XTAL_26M) ||   \
+                                    ((type) == PDS_PLL_XTAL_RC32M))
+
+/** @defgroup  PDS_PLL_CLK_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \
+                                   ((type) == PDS_PLL_CLK_240M) || \
+                                   ((type) == PDS_PLL_CLK_192M) || \
+                                   ((type) == PDS_PLL_CLK_160M) || \
+                                   ((type) == PDS_PLL_CLK_120M) || \
+                                   ((type) == PDS_PLL_CLK_96M) ||  \
+                                   ((type) == PDS_PLL_CLK_80M) ||  \
+                                   ((type) == PDS_PLL_CLK_48M) ||  \
+                                   ((type) == PDS_PLL_CLK_32M))
+
+/** @defgroup  PDS_AON_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/*@} end of group PDS_Public_Constants */
+
+/** @defgroup  PDS_Public_Macros
+ *  @{
+ */
+#define PDS_LDO_MIN_PU_CNT        (25) /* LDO need 25 cycles to power up */
+#define PDS_WARMUP_LATENCY_CNT    (38) /* LDO hw warmup compensation latency cycles */
+#define PDS_FORCE_PWR_OFF_OFFSET  (0)
+#define PDS_FORCE_ISO_EN_OFFSET   (4)
+#define PDS_FORCE_PDS_RST_OFFSET  (8)
+#define PDS_FORCE_MEM_STBY_OFFSET (12)
+#define PDS_FORCE_GATE_CLK_OFFSET (16)
+#define PDS_INT_MASK_BIT_OFFSET   (8)
+#define PDS_AON_WAKEUP_GPIO_NONE  (0x00)
+#define PDS_AON_WAKEUP_GPIO_7     (0x01)
+#define PDS_AON_WAKEUP_GPIO_8     (0x02)
+#define PDS_AON_WAKEUP_GPIO_ALL   (0x03)
+
+/*@} end of group PDS_Public_Macros */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type PDS_Reset(void);
+BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt);
+BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3);
+BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg);
+/*----------*/
+BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg,
+                                     PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt);
+/*----------*/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask);
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType);
+BL_Err_Type PDS_IntClear(void);
+PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void);
+PDS_RF_STS_Type PDS_Get_PdsRfStstus(void);
+PDS_STS_Type PDS_Get_PdsStstus(void);
+BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void);
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type PDS_Trim_RC32M(void);
+BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void);
+BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void);
+BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType);
+BL_Err_Type PDS_Fix_Xtal_Settig(void);
+BL_Err_Type PDS_Enable_PLL_All_Clks(void);
+BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
+BL_Err_Type PDS_Disable_PLL_All_Clks(void);
+BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
+BL_Err_Type PDS_Power_Off_PLL(void);
+/*----------*/;
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_PDS_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_romdriver.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_romdriver.h
new file mode 100755
index 0000000000..5b263a2fe9
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_romdriver.h
@@ -0,0 +1,799 @@
+/**
+  ******************************************************************************
+  * @file    bl602_romdriver.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_ROMDRIVER_H__
+#define __BL602_ROMDRIVER_H__
+
+#include "bl602_common.h"
+#include "bl602_aon.h"
+#include "bl602_glb.h"
+#include "bl602_hbn.h"
+#include "bl602_ef_ctrl.h"
+// #include "bl602_sec_eng.h"
+#include "bflb_xip_sflash.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_ctrl.h"
+// #include "softcrc.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  ROMDRIVER
+ *  @{
+ */
+
+/** @defgroup  ROMDRIVER_Public_Types
+ *  @{
+ */
+
+#define ROMAPI_INDEX_SECT_SIZE (0x800)
+#define ROMAPI_INDEX_MAX       (ROMAPI_INDEX_SECT_SIZE / 4 - 1)
+
+typedef enum {
+    ROM_API_INDEX_VERSION = 0,
+    ROM_API_INDEX_RSVD_0,
+    ROM_API_INDEX_RSVD_1,
+    ROM_API_INDEX_RSVD_LAST,
+
+    ROM_API_INDEX_AON_Power_On_MBG,
+    ROM_API_INDEX_AON_Power_Off_MBG,
+    ROM_API_INDEX_AON_Power_On_XTAL,
+    ROM_API_INDEX_AON_Set_Xtal_CapCode,
+    ROM_API_INDEX_AON_Get_Xtal_CapCode,
+    ROM_API_INDEX_AON_Power_Off_XTAL,
+    ROM_API_INDEX_AON_Power_On_BG,
+    ROM_API_INDEX_AON_Power_Off_BG,
+    ROM_API_INDEX_AON_Power_On_LDO11_SOC,
+    ROM_API_INDEX_AON_Power_Off_LDO11_SOC,
+    ROM_API_INDEX_AON_Power_On_LDO15_RF,
+    ROM_API_INDEX_AON_Power_Off_LDO15_RF,
+    ROM_API_INDEX_AON_Power_On_SFReg,
+    ROM_API_INDEX_AON_Power_Off_SFReg,
+    ROM_API_INDEX_AON_LowPower_Enter_PDS0,
+    ROM_API_INDEX_AON_LowPower_Exit_PDS0,
+
+    ROM_API_INDEX_ASM_Delay_Us,
+
+    ROM_API_INDEX_BL602_Delay_US,
+    ROM_API_INDEX_BL602_Delay_MS,
+    ROM_API_INDEX_BL602_MemCpy,
+    ROM_API_INDEX_BL602_MemCpy4,
+    ROM_API_INDEX_BL602_MemCpy_Fast,
+    ROM_API_INDEX_BL602_MemSet,
+    ROM_API_INDEX_BL602_MemSet4,
+    ROM_API_INDEX_BL602_MemCmp,
+
+    ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0,
+    ROM_API_INDEX_EF_Ctrl_Program_Efuse_0,
+    ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0,
+    ROM_API_INDEX_EF_Ctrl_Busy,
+    ROM_API_INDEX_EF_Ctrl_AutoLoad_Done,
+    ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity,
+    ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim,
+    ROM_API_INDEX_EF_Ctrl_Clear,
+
+    ROM_API_INDEX_GLB_Get_Root_CLK_Sel,
+    ROM_API_INDEX_GLB_Set_System_CLK_Div,
+    ROM_API_INDEX_GLB_Get_BCLK_Div,
+    ROM_API_INDEX_GLB_Get_HCLK_Div,
+
+    ROM_API_INDEX_Update_SystemCoreClockWith_XTAL,
+
+    ROM_API_INDEX_GLB_Set_System_CLK,
+
+    ROM_API_INDEX_System_Core_Clock_Update_From_RC32M,
+
+    ROM_API_INDEX_GLB_Set_SF_CLK,
+    ROM_API_INDEX_GLB_Set_PKA_CLK_Sel,
+    ROM_API_INDEX_GLB_SW_System_Reset,
+    ROM_API_INDEX_GLB_SW_CPU_Reset,
+    ROM_API_INDEX_GLB_SW_POR_Reset,
+    ROM_API_INDEX_GLB_Select_Internal_Flash,
+    ROM_API_INDEX_GLB_Select_External_Flash,
+    ROM_API_INDEX_GLB_Deswap_Flash_Pin,
+    ROM_API_INDEX_GLB_Swap_Flash_Pin,
+    ROM_API_INDEX_GLB_GPIO_Init,
+    ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable,
+    ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable,
+    ROM_API_INDEX_GLB_GPIO_Set_HZ,
+    ROM_API_INDEX_GLB_GPIO_Get_Fun,
+
+    ROM_API_INDEX_HBN_Mode_Enter,
+    ROM_API_INDEX_HBN_Power_Down_Flash,
+    ROM_API_INDEX_HBN_Enable,
+    ROM_API_INDEX_HBN_Reset,
+    ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout,
+    ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout,
+    ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout,
+    ROM_API_INDEX_HBN_32K_Sel,
+    ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel,
+    ROM_API_INDEX_HBN_Power_On_Xtal_32K,
+    ROM_API_INDEX_HBN_Power_Off_Xtal_32K,
+    ROM_API_INDEX_HBN_Power_On_RC32K,
+    ROM_API_INDEX_HBN_Power_Off_RC32K,
+    ROM_API_INDEX_HBN_Trim_RC32K,
+    ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg,
+    ROM_API_INDEX_HBN_Pin_WakeUp_Mask,
+    ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg,
+    ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup,
+
+    ROM_API_INDEX_L1C_Set_Wrap,
+    ROM_API_INDEX_L1C_Set_Way_Disable,
+    ROM_API_INDEX_L1C_IROM_2T_Access_Set,
+
+    ROM_API_INDEX_PDS_Reset,
+    ROM_API_INDEX_PDS_Enable,
+    ROM_API_INDEX_PDS_Force_Config,
+    ROM_API_INDEX_PDS_RAM_Config,
+    ROM_API_INDEX_PDS_Default_Level_Config,
+    ROM_API_INDEX_PDS_Trim_RC32M,
+    ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref,
+    ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref,
+    ROM_API_INDEX_PDS_Power_On_PLL,
+    ROM_API_INDEX_PDS_Enable_PLL_All_Clks,
+    ROM_API_INDEX_PDS_Disable_PLL_All_Clks,
+    ROM_API_INDEX_PDS_Enable_PLL_Clk,
+    ROM_API_INDEX_PDS_Disable_PLL_Clk,
+    ROM_API_INDEX_PDS_Power_Off_PLL,
+
+    ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring,
+    ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring,
+
+    ROM_API_INDEX_SFlash_Init,
+    ROM_API_INDEX_SFlash_SetSPIMode,
+    ROM_API_INDEX_SFlash_Read_Reg,
+    ROM_API_INDEX_SFlash_Write_Reg,
+    ROM_API_INDEX_SFlash_Busy,
+    ROM_API_INDEX_SFlash_Write_Enable,
+    ROM_API_INDEX_SFlash_Qspi_Enable,
+    ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable,
+    ROM_API_INDEX_SFlash_Chip_Erase,
+    ROM_API_INDEX_SFlash_Sector_Erase,
+    ROM_API_INDEX_SFlash_Blk32_Erase,
+    ROM_API_INDEX_SFlash_Blk64_Erase,
+    ROM_API_INDEX_SFlash_Erase,
+    ROM_API_INDEX_SFlash_Program,
+    ROM_API_INDEX_SFlash_GetUniqueId,
+    ROM_API_INDEX_SFlash_GetJedecId,
+    ROM_API_INDEX_SFlash_GetDeviceId,
+    ROM_API_INDEX_SFlash_Powerdown,
+    ROM_API_INDEX_SFlash_Releae_Powerdown,
+    ROM_API_INDEX_SFlash_SetBurstWrap,
+    ROM_API_INDEX_SFlash_DisableBurstWrap,
+    ROM_API_INDEX_SFlash_Software_Reset,
+    ROM_API_INDEX_SFlash_Reset_Continue_Read,
+    ROM_API_INDEX_SFlash_Set_IDbus_Cfg,
+    ROM_API_INDEX_SFlash_IDbus_Read_Enable,
+    ROM_API_INDEX_SFlash_Cache_Enable_Set,
+    ROM_API_INDEX_SFlash_Cache_Flush,
+    ROM_API_INDEX_SFlash_Cache_Read_Enable,
+    ROM_API_INDEX_SFlash_Cache_Hit_Count_Get,
+    ROM_API_INDEX_SFlash_Cache_Miss_Count_Get,
+    ROM_API_INDEX_SFlash_Cache_Read_Disable,
+    ROM_API_INDEX_SFlash_Read,
+    ROM_API_INDEX_SFlash_Read_Reg_With_Cmd,
+    ROM_API_INDEX_SFlash_Write_Reg_With_Cmd,
+    ROM_API_INDEX_SFlash_Restore_From_Powerdown,
+
+    ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun,
+    ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock,
+    ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Flash_Identify,
+    ROM_API_INDEX_SF_Ctrl_Enable,
+    ROM_API_INDEX_SF_Ctrl_Select_Pad,
+    ROM_API_INDEX_SF_Ctrl_Set_Owner,
+    ROM_API_INDEX_SF_Ctrl_Disable,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable_LE,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Region,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Key,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_IV,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable,
+    ROM_API_INDEX_SF_Ctrl_AES_Disable,
+    ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset,
+    ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset,
+    ROM_API_INDEX_SF_Ctrl_Select_Clock,
+    ROM_API_INDEX_SF_Ctrl_SendCmd,
+    ROM_API_INDEX_SF_Ctrl_Icache_Set,
+    ROM_API_INDEX_SF_Ctrl_Icache2_Set,
+    ROM_API_INDEX_SF_Ctrl_GetBusyState,
+    ROM_API_INDEX_SF_Ctrl_Is_AES_Enable,
+    ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay,
+    ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay,
+
+    ROM_API_INDEX_XIP_SFlash_State_Save,
+    ROM_API_INDEX_XIP_SFlash_State_Restore,
+    ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Write_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_With_Lock,
+    ROM_API_INDEX_XIP_SFlash_Write_With_Lock,
+    ROM_API_INDEX_XIP_SFlash_Erase_With_Lock,
+    ROM_API_INDEX_XIP_SFlash_Opt_Enter,
+    ROM_API_INDEX_XIP_SFlash_Opt_Exit,
+
+    ROM_API_INDEX_BFLB_Soft_CRC32,
+
+    ROM_API_INDEX_FUNC_EMPTY_START,
+
+    ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX
+
+} ROM_API_INDEX_e;
+
+/*@} end of group ROMDRIVER_Public_Types */
+
+/** @defgroup  ROMDRIVER_Public_Constants
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Constants */
+
+/** @defgroup  ROMDRIVER_Public_Macros
+ *  @{
+ */
+
+#define ROM_APITABLE ((uint32_t *)0x21010800)
+
+#define RomDriver_AON_Power_On_MBG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG])
+
+#define RomDriver_AON_Power_Off_MBG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG])
+
+#define RomDriver_AON_Power_On_XTAL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL])
+
+#define RomDriver_AON_Set_Xtal_CapCode \
+    ((BL_Err_Type(*)(uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode])
+
+#define RomDriver_AON_Get_Xtal_CapCode \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode])
+
+#define RomDriver_AON_Power_Off_XTAL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL])
+
+#define RomDriver_AON_Power_On_BG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_BG])
+
+#define RomDriver_AON_Power_Off_BG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG])
+
+#define RomDriver_AON_Power_On_LDO11_SOC \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO11_SOC])
+
+#define RomDriver_AON_Power_Off_LDO11_SOC \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO11_SOC])
+
+#define RomDriver_AON_Power_On_LDO15_RF \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_LDO15_RF])
+
+#define RomDriver_AON_Power_Off_LDO15_RF \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_LDO15_RF])
+
+#define RomDriver_AON_Power_On_SFReg \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_SFReg])
+
+#define RomDriver_AON_Power_Off_SFReg \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_SFReg])
+
+#define RomDriver_AON_LowPower_Enter_PDS0 \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Enter_PDS0])
+
+#define RomDriver_AON_LowPower_Exit_PDS0 \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Exit_PDS0])
+
+#define RomDriver_ASM_Delay_Us \
+    ((void (*)(uint32_t core, uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us])
+
+#define RomDriver_BL602_Delay_US \
+    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_US])
+
+#define RomDriver_BL602_Delay_MS \
+    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL602_Delay_MS])
+
+#define RomDriver_BL602_MemCpy \
+    ((void *(*)(void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy])
+
+#define RomDriver_BL602_MemCpy4 \
+    ((uint32_t * (*)(uint32_t * dst, const uint32_t *src, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy4])
+
+#define RomDriver_BL602_MemCpy_Fast \
+    ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCpy_Fast])
+
+#define RomDriver_BL602_MemSet \
+    ((void *(*)(void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemSet])
+
+#define RomDriver_BL602_MemSet4 \
+    ((uint32_t * (*)(uint32_t * dst, const uint32_t val, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL602_MemSet4])
+
+#define RomDriver_BL602_MemCmp \
+    ((int (*)(const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL602_MemCmp])
+
+#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0])
+
+#define RomDriver_EF_Ctrl_Program_Efuse_0 \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0])
+
+#define RomDriver_EF_Ctrl_Load_Efuse_R0 \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0])
+
+#define RomDriver_EF_Ctrl_Busy \
+    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy])
+
+#define RomDriver_EF_Ctrl_AutoLoad_Done \
+    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_AutoLoad_Done])
+
+#define RomDriver_EF_Ctrl_Get_Trim_Parity \
+    ((uint8_t(*)(uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity])
+
+#define RomDriver_EF_Ctrl_Read_RC32M_Trim \
+    ((void (*)(Efuse_Ana_RC32M_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim])
+
+#define RomDriver_EF_Ctrl_Read_RC32K_Trim \
+    ((void (*)(Efuse_Ana_RC32K_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim])
+
+#define RomDriver_EF_Ctrl_Clear \
+    ((void (*)(uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])
+
+#define RomDriver_GLB_Get_Root_CLK_Sel \
+    ((GLB_ROOT_CLK_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel])
+
+#define RomDriver_GLB_Set_System_CLK_Div \
+    ((BL_Err_Type(*)(uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div])
+
+#define RomDriver_GLB_Get_BCLK_Div \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div])
+
+#define RomDriver_GLB_Get_HCLK_Div \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div])
+
+#define RomDriver_Update_SystemCoreClockWith_XTAL \
+    ((BL_Err_Type(*)(GLB_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL])
+
+#define RomDriver_GLB_Set_System_CLK \
+    ((BL_Err_Type(*)(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK])
+
+#define RomDriver_System_Core_Clock_Update_From_RC32M \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M])
+
+#define RomDriver_GLB_Set_SF_CLK \
+    ((BL_Err_Type(*)(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK])
+
+#define RomDriver_GLB_Set_PKA_CLK_Sel \
+    ((BL_Err_Type(*)(GLB_PKA_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel])
+
+#define RomDriver_GLB_SW_System_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset])
+
+#define RomDriver_GLB_SW_CPU_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset])
+
+#define RomDriver_GLB_SW_POR_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset])
+
+#define RomDriver_GLB_Select_Internal_Flash \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash])
+
+#define RomDriver_GLB_Select_External_Flash \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash])
+
+#define RomDriver_GLB_Deswap_Flash_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin])
+
+#define RomDriver_GLB_Swap_Flash_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin])
+
+#define RomDriver_GLB_GPIO_Init \
+    ((BL_Err_Type(*)(GLB_GPIO_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init])
+
+#define RomDriver_GLB_GPIO_OUTPUT_Enable \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable])
+
+#define RomDriver_GLB_GPIO_OUTPUT_Disable \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable])
+
+#define RomDriver_GLB_GPIO_Set_HZ \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ])
+
+#define RomDriver_GLB_GPIO_Get_Fun \
+    ((uint8_t(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun])
+
+#define RomDriver_HBN_Mode_Enter \
+    ((void (*)(HBN_APP_CFG_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter])
+
+#define RomDriver_HBN_Power_Down_Flash \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
+
+#define RomDriver_HBN_Enable \
+    ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])
+
+#define RomDriver_HBN_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset])
+
+#define RomDriver_HBN_Set_Ldo11_Aon_Vout \
+    ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout])
+
+#define RomDriver_HBN_Set_Ldo11_Rt_Vout \
+    ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout])
+
+#define RomDriver_HBN_Set_Ldo11_Soc_Vout \
+    ((BL_Err_Type(*)(HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout])
+
+#define RomDriver_HBN_32K_Sel \
+    ((BL_Err_Type(*)(HBN_32K_CLK_Type clkType))ROM_APITABLE[ROM_API_INDEX_HBN_32K_Sel])
+
+#define RomDriver_HBN_Set_ROOT_CLK_Sel \
+    ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel])
+
+#define RomDriver_HBN_Power_On_Xtal_32K \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K])
+
+#define RomDriver_HBN_Power_Off_Xtal_32K \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K])
+
+#define RomDriver_HBN_Power_On_RC32K \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K])
+
+#define RomDriver_HBN_Power_Off_RC32K \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_RC32K])
+
+#define RomDriver_HBN_Trim_RC32K \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K])
+
+#define RomDriver_HBN_Hw_Pu_Pd_Cfg \
+    ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg])
+
+#define RomDriver_HBN_Pin_WakeUp_Mask \
+    ((BL_Err_Type(*)(uint8_t maskVal))ROM_APITABLE[ROM_API_INDEX_HBN_Pin_WakeUp_Mask])
+
+#define RomDriver_HBN_GPIO7_Dbg_Pull_Cfg \
+    ((BL_Err_Type(*)(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg])
+
+#define RomDriver_HBN_Set_Embedded_Flash_Pullup \
+    ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup])
+
+#define RomDriver_L1C_Set_Wrap \
+    ((BL_Err_Type(*)(BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap])
+
+#define RomDriver_L1C_Set_Way_Disable \
+    ((BL_Err_Type(*)(uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable])
+
+#define RomDriver_L1C_IROM_2T_Access_Set \
+    ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set])
+
+#define RomDriver_PDS_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset])
+
+#define RomDriver_PDS_Enable \
+    ((BL_Err_Type(*)(PDS_CTL_Type * cfg, PDS_CTL4_Type * cfg4, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Enable])
+
+#define RomDriver_PDS_Force_Config \
+    ((BL_Err_Type(*)(PDS_CTL2_Type * cfg2, PDS_CTL3_Type * cfg3)) ROM_APITABLE[ROM_API_INDEX_PDS_Force_Config])
+
+#define RomDriver_PDS_RAM_Config \
+    ((BL_Err_Type(*)(PDS_RAM_CFG_Type * ramCfg)) ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config])
+
+#define RomDriver_PDS_Default_Level_Config \
+    ((BL_Err_Type(*)(PDS_DEFAULT_LV_CFG_Type * defaultLvCfg, PDS_RAM_CFG_Type * ramCfg, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config])
+
+#define RomDriver_PDS_Trim_RC32M \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M])
+
+#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref])
+
+#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref])
+
+#define RomDriver_PDS_Power_On_PLL \
+    ((BL_Err_Type(*)(PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL])
+
+#define RomDriver_PDS_Enable_PLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks])
+
+#define RomDriver_PDS_Disable_PLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks])
+
+#define RomDriver_PDS_Enable_PLL_Clk \
+    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk])
+
+#define RomDriver_PDS_Disable_PLL_Clk \
+    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk])
+
+#define RomDriver_PDS_Power_Off_PLL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL])
+
+#define RomDriver_SEC_Eng_Turn_On_Sec_Ring \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring])
+
+#define RomDriver_SEC_Eng_Turn_Off_Sec_Ring \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring])
+
+#define RomDriver_SFlash_Init \
+    ((void (*)(const struct sf_ctrl_cfg_type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
+
+#define RomDriver_SFlash_SetSPIMode \
+    ((int(*)(uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
+
+#define RomDriver_SFlash_Read_Reg \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
+
+#define RomDriver_SFlash_Write_Reg \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
+
+#define RomDriver_SFlash_Busy \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
+
+#define RomDriver_SFlash_Write_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
+
+#define RomDriver_SFlash_Qspi_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
+
+#define RomDriver_SFlash_Volatile_Reg_Write_Enable \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
+
+#define RomDriver_SFlash_Chip_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
+
+#define RomDriver_SFlash_Sector_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
+
+#define RomDriver_SFlash_Blk32_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
+
+#define RomDriver_SFlash_Blk64_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
+
+#define RomDriver_SFlash_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
+
+#define RomDriver_SFlash_Program \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
+
+#define RomDriver_SFlash_GetUniqueId \
+    ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
+
+#define RomDriver_SFlash_GetJedecId \
+    ((void (*)(spi_flash_cfg_type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
+
+#define RomDriver_SFlash_GetDeviceId \
+    ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
+
+#define RomDriver_SFlash_Powerdown \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
+
+#define RomDriver_SFlash_Releae_Powerdown \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown])
+
+#define RomDriver_SFlash_SetBurstWrap \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
+
+#define RomDriver_SFlash_DisableBurstWrap \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
+
+#define RomDriver_SFlash_Software_Reset \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
+
+#define RomDriver_SFlash_Reset_Continue_Read \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
+
+#define RomDriver_SFlash_Set_IDbus_Cfg \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
+
+#define RomDriver_SFlash_IDbus_Read_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
+
+#define RomDriver_SFlash_Cache_Enable_Set \
+    ((int(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Enable_Set])
+
+#define RomDriver_SFlash_Cache_Flush \
+    ((int(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Flush])
+
+#define RomDriver_SFlash_Cache_Read_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable])
+
+#define RomDriver_SFlash_Cache_Hit_Count_Get \
+    ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Hit_Count_Get])
+
+#define RomDriver_SFlash_Cache_Miss_Count_Get \
+    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Miss_Count_Get])
+
+#define RomDriver_SFlash_Cache_Read_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable])
+
+#define RomDriver_SFlash_Read \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
+
+#define RomDriver_SFlash_Read_Reg_With_Cmd \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
+
+#define RomDriver_SFlash_Write_Reg_With_Cmd \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
+
+#define RomDriver_SFlash_Restore_From_Powerdown \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t flashContRead)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
+
+#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \
+    ((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
+
+#define RomDriver_SF_Cfg_Init_Internal_Flash_Gpio \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio])
+
+#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \
+    ((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
+
+#define RomDriver_SF_Cfg_Restore_GPIO17_Fun \
+    ((void (*)(uint8_t fun))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun])
+
+#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \
+    ((int(*)(uint32_t flashID, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
+
+#define RomDriver_SF_Cfg_Init_Flash_Gpio \
+    ((int (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
+
+#define RomDriver_SF_Cfg_Flash_Identify \
+    ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
+
+#define RomDriver_SF_Ctrl_Enable \
+    ((void (*)(const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
+
+#define RomDriver_SF_Ctrl_Select_Pad \
+    ((void (*)(uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
+
+#define RomDriver_SF_Ctrl_Set_Owner \
+    ((void (*)(uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
+
+#define RomDriver_SF_Ctrl_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
+
+#define RomDriver_SF_Ctrl_AES_Enable_BE \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE])
+
+#define RomDriver_SF_Ctrl_AES_Enable_LE \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE])
+
+#define RomDriver_SF_Ctrl_AES_Set_Region \
+    ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
+
+#define RomDriver_SF_Ctrl_AES_Set_Key \
+    ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
+
+#define RomDriver_SF_Ctrl_AES_Set_Key_BE \
+    ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
+
+#define RomDriver_SF_Ctrl_AES_Set_IV \
+    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV])
+
+#define RomDriver_SF_Ctrl_AES_Set_IV_BE \
+    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])
+
+#define RomDriver_SF_Ctrl_AES_Enable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable])
+
+#define RomDriver_SF_Ctrl_AES_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable])
+
+#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \
+    ((void (*)(uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
+
+#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \
+    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
+
+#define RomDriver_SF_Ctrl_Select_Clock \
+    ((void (*)(uint8_t sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock])
+
+#define RomDriver_SF_Ctrl_SendCmd \
+    ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
+
+#define RomDriver_SF_Ctrl_Icache_Set \
+    ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache_Set])
+
+#define RomDriver_SF_Ctrl_Icache2_Set \
+    ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Icache2_Set])
+
+#define RomDriver_SF_Ctrl_GetBusyState \
+    ((int(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
+
+#define RomDriver_SF_Ctrl_Is_AES_Enable \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
+
+#define RomDriver_SF_Ctrl_Get_Clock_Delay \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])
+
+#define RomDriver_SF_Ctrl_Set_Clock_Delay \
+    ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
+
+#define RomDriver_XIP_SFlash_State_Save \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
+
+#define RomDriver_XIP_SFlash_State_Restore \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
+
+#define RomDriver_XIP_SFlash_Erase_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
+
+#define RomDriver_XIP_SFlash_Write_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
+
+#define RomDriver_XIP_SFlash_Read_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
+
+#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
+
+#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
+
+#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
+
+#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \
+    ((int(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
+
+#define RomDriver_XIP_SFlash_Opt_Enter \
+    ((void (*)(uint8_t * aesEnable)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter])
+
+#define RomDriver_XIP_SFlash_Opt_Exit \
+    ((void (*)(uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit])
+
+#define RomDriver_BFLB_Soft_CRC32 \
+    ((uint32_t(*)(void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32])
+
+/*@} end of group ROMDRIVER_Public_Macros */
+
+/** @defgroup  ROMDRIVER_Public_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Functions */
+
+/*@} end of group ROMDRIVER */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_ROMDRIVER_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sdu.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sdu.h
new file mode 100755
index 0000000000..25fb979ae7
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sdu.h
@@ -0,0 +1,184 @@
+#ifndef __BL602_SDU_H__
+#define __BL602_SDU_H__
+
+#include "bl602.h"
+#include "bl602_common.h"
+
+#define NUM_FUNC  1
+#define FUNC_WIFI 0
+
+// SDIO I/O Enable
+#define BL_SDIO_IO_ENABLE SDU_BASE + 0x00000002
+//CCCR (Fn0) Registers
+
+// SDIO Device Sleep
+#define BL_SDIO_DEV_SLEEP SDU_BASE + 0x00000092
+
+// Start Address of CCR
+#define BL_SDIO_CCR_BASE SDU_BASE + 0x00000100
+// Address offset of CCR between two functions
+#define BL_SDIO_CCR_FUNC_OFFSET 0x00000100
+
+// Address for sdio block size information
+#define SDIO_FN1_BLK_SIZE_0      (SDU_BASE + 0x00000028)
+#define SDIO_FN1_BLK_SIZE_1      (SDU_BASE + 0x00000029)
+#define SDIO_FN1_BLK_SIZE_1_MASK 0x01
+
+#define BL_FUNC_SCRATCH_BASE SDU_BASE + 0x00000160
+
+typedef struct
+{
+    uint8_t HostToCardEvent;    // 0x100/200
+    uint8_t HostIntCause;       // 0x101/201
+    uint8_t HostIntMask;        // 0x102/202
+    uint8_t HostIntStatus;      // 0x103/203
+    uint16_t RdBitMap;          // 0x104/204
+    uint16_t WrBitMap;          // 0x106/206
+    uint16_t RdLen[16];         // 0x108/208
+    uint8_t HostTransferStatus; // 0x128/228
+    uint8_t reserved1[0x130 - 0x128 - 1];
+    uint8_t CardToHostEvent; // 0x130/230
+    uint8_t reserved2[3];
+    uint8_t CardIntMask; // 0x134/234
+    uint8_t reserved3[3];
+    uint8_t CardIntStatus; // 0x138/238
+    uint8_t reserved4[3];
+    uint8_t CardIntMode; // 0x13C/23C
+    uint8_t reserved5[3];
+    uint32_t SqReadBase;    // 0x140/240
+    uint32_t SqWriteBase;   // 0x144/244
+    uint8_t RdIdx;          // 0x148/248
+    uint8_t WrIdx;          // 0x149/249
+    uint8_t DnldQueueWrPtr; // 0x14A/24A
+    uint8_t UpldQueueWrPtr; // 0x14B/24B
+    uint8_t DnldQueue[8];   // 0x14C/24C
+    uint8_t UpldQueue[8];   // 0x154/254
+    uint8_t ChipRev;        // 0x15C      //RO
+    uint8_t reserved6;      // 0x15D      //NOT_DEFINE
+    uint8_t IPRev0;         // 0x15E      //RO
+    uint8_t IPRev1;         // 0x15F      //RO
+    uint8_t reserved7[4];   // 0x160/260
+    uint16_t Scratch2;      // 0x164/264
+    uint16_t Scratch1;      // 0x166/266
+    uint8_t Ocr0;           // 0x168/268
+    uint8_t Ocr1;           // 0x169/269
+    uint8_t Ocr2;           // 0x16A/26A
+    uint8_t Config;         // 0x16B/26B
+    uint32_t Config2;       // 0x16C/26C
+    uint32_t Debug;         // 0x170/270
+    uint32_t DmaAddr;       // 0x174/274
+    uint8_t IoPort[3];      // 0x178/278
+} __attribute__((packed)) HidSdio_RegMap_t, *pHidSdio_RegMap_t;
+
+// Common I/O Area Registers (CIA) Offset
+//
+// Bit Def. Host To Card Interrupt Event (Offset 0x100/200)
+#define SDIO_HCR_CONFIG_HostPwrUp (1 << 1)
+
+// Bit Def. Host Transfer Status (Offset 0x128/228)
+#define SDIO_CCR_HOST_INT_DnLdReStart (1 << 0)
+#define SDIO_CCR_HOST_INT_UpLdReStart (1 << 1)
+#define SDIO_CCR_HOST_INT_DnLdCRC_err (1 << 2)
+
+// Bit Def. Card To Host Interrupt Event (Offset 0x130/230)
+#define SDIO_CCR_CS_DnLdRdy    (1 << 0)
+#define SDIO_CCR_CS_UpLdRdy    (1 << 1)
+#define SDIO_CCR_CS_ReadCISRdy (1 << 2)
+#define SDIO_CCR_CS_IORdy      (1 << 3)
+
+// Bit Def. Card Interrupt Mask (Offset 0x134/234)
+#define SDIO_CCR_CIM_DnLdOvr (1 << 0)
+#define SDIO_CCR_CIM_UpLdOvr (1 << 1)
+#define SDIO_CCR_CIM_Abort   (1 << 2)
+#define SDIO_CCR_CIM_PwrDn   (1 << 3)
+#define SDIO_CCR_CIM_PwrUp   (1 << 4)
+
+#define SDIO_CCR_CIM_MASK 0x0007
+
+// Bit Def. Card Interrupt Status (Offset 0x138/238)
+#define SDIO_CCR_CIC_DnLdOvr (1 << 0)
+#define SDIO_CCR_CIC_UpLdOvr (1 << 1)
+#define SDIO_CCR_CIC_Abort   (1 << 2)
+#define SDIO_CCR_CIC_PwrDn   (1 << 3)
+#define SDIO_CCR_CIC_PwrUp   (1 << 4)
+
+#define SDIO_CCR_CIC_MASK 0x001F
+
+// Bit Def. Card Interrupt RSR (Offset 0x13C/23C)
+#define SDIO_CCR_CIO_DnLdOvr (1 << 0)
+#define SDIO_CCR_CIO_UpLdOvr (1 << 1)
+#define SDIO_CCR_CIO_Abort   (1 << 2)
+#define SDIO_CCR_CIO_PwrDn   (1 << 3)
+#define SDIO_CCR_CIO_PwrUp   (1 << 4)
+#define SDIO_CCR_CIO_MASK    0x001F
+
+//Config2 register mask
+#define CONFIG2_MSK 0x00000C00
+
+//CardIntMode register mask
+
+#define CARD_INT_MODE_MSK 0x00000003
+#define HOST_INT_MSK      0x00000002
+
+//=============================================================================
+//                                PUBLIC MACROS
+//=============================================================================
+
+#define BL_REGS8(x)  (*(volatile unsigned char *)(x))
+#define BL_REGS16(x) (*(volatile unsigned short *)(x))
+#define BL_REGS32(x) (*(volatile unsigned long *)(x))
+
+#define BL_READ_REGS8(reg, val)  ((val) = BL_REGS8(reg))
+#define BL_READ_REGS16(reg, val) ((val) = BL_REGS16(reg))
+#define BL_READ_REGS32(reg, val) ((val) = BL_REGS32(reg))
+#define BL_READ_BYTE(reg, val)   ((val) = BL_REGS8(reg))
+#define BL_READ_HWORD(reg, val)  ((val) = BL_REGS16(reg)) /*half word; */
+#define BL_READ_WORD(reg, val)   ((val) = BL_REGS32(reg)) /*32 bits */
+
+#define BL_WRITE_REGS8(reg, val)  (BL_REGS8(reg) = (val))
+#define BL_WRITE_REGS16(reg, val) (BL_REGS16(reg) = (val))
+#define BL_WRITE_REGS32(reg, val) (BL_REGS32(reg) = (val))
+#define BL_WRITE_BYTE(reg, val)   (BL_REGS8(reg) = (val))
+#define BL_WRITE_HWORD(reg, val)  (BL_REGS16(reg) = (val)) /*half word; */
+#define BL_WRITE_WORD(reg, val)   (BL_REGS32(reg) = (val)) /*32 bits */
+// Write uint32 to a low 16-bit register and a high 16-bit register
+#define WRITE2REGS(lo, hi, u32)                   \
+    BL_WRITE_HWORD(lo, (uint16_t)((u32)&0xffff)); \
+    BL_WRITE_HWORD(hi, (uint16_t)(((u32) >> 16) & 0xffff))
+
+#define BL_REGS8_SETBITS(reg, val)  (BL_REGS8(reg) |= (uint8)(val))
+#define BL_REGS16_SETBITS(reg, val) (BL_REGS16(reg) |= (uint16)(val))
+#define BL_REGS32_SETBITS(reg, val) (BL_REGS32(reg) |= (val))
+#define BL_REGS8_CLRBITS(reg, val)  (BL_REGS8(reg) = (uint8)(BL_REGS8(reg) & ~(val)))
+#define BL_REGS16_CLRBITS(reg, val) (BL_REGS16(reg) = (uint16)(BL_REGS16(reg) & ~(val)))
+#define BL_REGS32_CLRBITS(reg, val) (BL_REGS32(reg) = (BL_REGS32(reg) & ~(val)))
+
+//=============================================================================
+//                                ENUM TYPE DEFINITION
+//=============================================================================
+
+/******************************************************************/
+/*!
+ *  \enum SDIO_CMD_TYPE
+ *
+ *******************************************************************/
+typedef enum {
+    IOCTL_GET_CONFIG = 0, /*!< Get configuration info */
+
+    /* HID IOCTLs*/
+    IOCTL_HID_GET_BLOCK_SIZE, /*!< Get Block size */
+
+} SDIO_CMD_TYPE;
+
+//=============================================================================
+//                                FUNCTION DECLARATION
+//=============================================================================
+extern void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value);
+extern uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg);
+
+//=============================================================================
+//                                Variable DECLARATION
+//=============================================================================
+extern volatile pHidSdio_RegMap_t SdioFuncReg[];
+extern uint8_t flag_mport[];
+#endif /* __BL602_SDU_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h
old mode 100644
new mode 100755
similarity index 79%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h
index 187024d224..b2090baa9b
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sf_cfg_ext.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sf_cfg_ext.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_sf_cfg_ext.h
+  * @file    bl602_sf_cfg_ext.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,14 +33,14 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_SF_CFG_EXT_H__
-#define __BL808_SF_CFG_EXT_H__
+#ifndef __BL602_SF_CFG_EXT_H__
+#define __BL602_SF_CFG_EXT_H__
 
 #include "string.h"
-#include "bl808_sflash.h"
-#include "bl808_sf_ctrl.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_ctrl.h"
 
-/** @addtogroup  BL808_Peripheral_Driver
+/** @addtogroup  BL602_Peripheral_Driver
  *  @{
  */
 
@@ -69,14 +69,15 @@
 /** @defgroup  SF_CFG_EXT_Public_Functions
  *  @{
  */
-BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg);
-uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,
-                                   SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);
+int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                            uint8_t group, uint8_t bank);
+uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
+                                        spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
 
 /*@} end of group SF_CFG_EXT_Public_Functions */
 
 /*@} end of group SF_CFG_EXT */
 
-/*@} end of group BL808_Peripheral_Driver */
+/*@} end of group BL602_Peripheral_Driver */
 
-#endif /* __BL808_SF_CFG_EXT_H__ */
+#endif /* __BL602_SF_CFG_EXT_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sflash_ext.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sflash_ext.h
new file mode 100755
index 0000000000..a706e06d42
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_sflash_ext.h
@@ -0,0 +1,87 @@
+/**
+  ******************************************************************************
+  * @file    bl602_sflah_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_SFLAH_EXT_H__
+#define __BL602_SFLAH_EXT_H__
+
+#include "bflb_sflash.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLAH_EXT
+ *  @{
+ */
+
+/** @defgroup  SFLAH_EXT_Public_Types
+ *  @{
+ */
+
+/*@} end of group SFLAH_EXT_Public_Types */
+
+/** @defgroup  SFLAH_EXT_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SFLAH_EXT_Public_Constants */
+
+/** @defgroup  SFLAH_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group SFLAH_EXT_Public_Macros */
+
+/** @defgroup  SFLAH_EXT_Public_Functions
+ *  @{
+ */
+int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flash_cont_read, uint8_t bank);
+int bflb_sflash_rcv_enable(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos);
+int bflb_sflash_erase_security_register(spi_flash_cfg_type *p_flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_program_security_register(spi_flash_cfg_type *p_flash_cfg,
+                                          struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg);
+int bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg);
+int bflb_sflash_cache_enable_set(uint8_t way_disable);
+int bflb_sflash_cache_flush(void);
+
+/*@} end of group SFLAH_EXT_Public_Functions */
+
+/*@} end of group SFLAH_EXT */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_SFLAH_EXT_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_tzc_sec.h
old mode 100644
new mode 100755
similarity index 68%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_tzc_sec.h
index 099764d134..832c587fe5
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sec_dbg.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_tzc_sec.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_sec_dbg.h
+  * @file    bl602_tzc_sec.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,51 +33,52 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_SEC_DBG_H__
-#define __BL808_SEC_DBG_H__
+#ifndef __BL602_TZC_SEC_H__
+#define __BL602_TZC_SEC_H__
 
-#include "sec_dbg_reg.h"
-#include "bl808_common.h"
+#include "tzc_sec_reg.h"
+#include "bl602_common.h"
 
-/** @addtogroup  BL808_Peripheral_Driver
+/** @addtogroup  BL602_Peripheral_Driver
  *  @{
  */
 
-/** @addtogroup  SEC_DBG
+/** @addtogroup  TZC_SEC
  *  @{
  */
 
-/** @defgroup  SEC_DBG_Public_Types
+/** @defgroup  TZC_SEC_Public_Types
  *  @{
  */
 
-/*@} end of group SEC_DBG_Public_Types */
+/*@} end of group TZC_SEC_Public_Types */
 
-/** @defgroup  SEC_DBG_Public_Constants
+/** @defgroup  TZC_SEC_Public_Constants
  *  @{
  */
 
-/*@} end of group SEC_DBG_Public_Constants */
+/*@} end of group TZC_SEC_Public_Constants */
 
-/** @defgroup  SEC_DBG_Public_Macros
+/** @defgroup  TZC_SEC_Public_Macros
  *  @{
  */
 
-/*@} end of group SEC_DBG_Public_Macros */
+/*@} end of group TZC_SEC_Public_Macros */
 
-/** @defgroup  SEC_DBG_Public_Functions
+/** @defgroup  TZC_SEC_Public_Functions
  *  @{
  */
-void Sec_Dbg_Read_Chip_ID(uint8_t id[8]);
-void Sec_Dbg_Set_Dbg_Pwd(const uint32_t pwd[4]);
-uint32_t Sec_Dbg_Read_Dbg_Mode(void);
-uint32_t Sec_Dbg_Read_Dbg_Enable(void);
-void Sec_Dbg_Set_Dbg_Trigger(void);
 
-/*@} end of group SEC_DBG_Public_Functions */
+void TZC_Sboot_Set(uint8_t Val);
+void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t length);
+void TZC_Set_Rom0_R1_Protect(uint32_t start, uint32_t length);
+void TZC_Set_Rom1_R0_Protect(uint32_t start, uint32_t length);
+void TZC_Set_Rom1_R1_Protect(uint32_t start, uint32_t length);
 
-/*@} end of group SEC_DBG */
+/*@} end of group TZC_SEC_Public_Functions */
 
-/*@} end of group BL808_Peripheral_Driver */
+/*@} end of group TZC_SEC */
 
-#endif /* __BL808_SEC_DBG_H__ */
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_TZC_SEC_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h
new file mode 100755
index 0000000000..1bf26e49f4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/bl602_xip_sflash_ext.h
@@ -0,0 +1,97 @@
+/**
+  ******************************************************************************
+  * @file    bl602_xip_sflash_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL602_XIP_SFLASH_EXT_H__
+#define __BL602_XIP_SFLASH_EXT_H__
+
+#include "bl602_common.h"
+#include "bl602_sflash_ext.h"
+#include "bflb_sflash.h"
+#include "bflb_xip_sflash.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH_EXT
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Types */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Constants
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Constants */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Macros */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Functions
+ *  @{
+ */
+int bflb_xip_sflash_state_restore_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_erase_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr,
+                                        uint32_t endaddr, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_write_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+                                        uint32_t len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_read_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+                                        uint32_t len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_jedecid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                              uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_deviceid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr,
+                                               uint8_t *data, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_get_uniqueid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint8_t *data,
+                                               uint8_t idLen, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_rcv_enable_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t rCmd, uint8_t wCmd,
+                                         uint8_t bitPos, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_init(spi_flash_cfg_type *p_flash_cfg);
+
+/*@} end of group XIP_SFLASH_EXT_Public_Functions */
+
+/*@} end of group XIP_SFLASH_EXT */
+
+/*@} end of group BL602_Peripheral_Driver */
+
+#endif /* __BL602_XIP_SFLASH_EXT_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/aon_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/aon_reg.h
new file mode 100755
index 0000000000..993e06043c
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/aon_reg.h
@@ -0,0 +1,1560 @@
+/**
+  ******************************************************************************
+  * @file    aon_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __AON_REG_H__
+#define __AON_REG_H__
+
+#include "bl602.h"
+
+/* 0x800 : aon */
+#define AON_OFFSET                     (0x800)
+#define AON_RESV                       AON_RESV
+#define AON_RESV_POS                   (0U)
+#define AON_RESV_LEN                   (8U)
+#define AON_RESV_MSK                   (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)
+#define AON_RESV_UMSK                  (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS))
+#define AON_PU_AON_DC_TBUF             AON_PU_AON_DC_TBUF
+#define AON_PU_AON_DC_TBUF_POS         (12U)
+#define AON_PU_AON_DC_TBUF_LEN         (1U)
+#define AON_PU_AON_DC_TBUF_MSK         (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)
+#define AON_PU_AON_DC_TBUF_UMSK        (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS))
+#define AON_LDO11_RT_PULLDOWN          AON_LDO11_RT_PULLDOWN
+#define AON_LDO11_RT_PULLDOWN_POS      (20U)
+#define AON_LDO11_RT_PULLDOWN_LEN      (1U)
+#define AON_LDO11_RT_PULLDOWN_MSK      (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)
+#define AON_LDO11_RT_PULLDOWN_UMSK     (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS))
+#define AON_LDO11_RT_PULLDOWN_SEL      AON_LDO11_RT_PULLDOWN_SEL
+#define AON_LDO11_RT_PULLDOWN_SEL_POS  (21U)
+#define AON_LDO11_RT_PULLDOWN_SEL_LEN  (1U)
+#define AON_LDO11_RT_PULLDOWN_SEL_MSK  (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)
+#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS))
+#define AON_SW_PU_LDO11_RT             AON_SW_PU_LDO11_RT
+#define AON_SW_PU_LDO11_RT_POS         (22U)
+#define AON_SW_PU_LDO11_RT_LEN         (1U)
+#define AON_SW_PU_LDO11_RT_MSK         (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)
+#define AON_SW_PU_LDO11_RT_UMSK        (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS))
+
+/* 0x804 : aon_common */
+#define AON_COMMON_OFFSET         (0x804)
+#define AON_TMUX_AON              AON_TMUX_AON
+#define AON_TMUX_AON_POS          (0U)
+#define AON_TMUX_AON_LEN          (3U)
+#define AON_TMUX_AON_MSK          (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)
+#define AON_TMUX_AON_UMSK         (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS))
+#define AON_TEN_AON               AON_TEN_AON
+#define AON_TEN_AON_POS           (4U)
+#define AON_TEN_AON_LEN           (1U)
+#define AON_TEN_AON_MSK           (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)
+#define AON_TEN_AON_UMSK          (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS))
+#define AON_DTEN_XTAL32K          AON_DTEN_XTAL32K
+#define AON_DTEN_XTAL32K_POS      (5U)
+#define AON_DTEN_XTAL32K_LEN      (1U)
+#define AON_DTEN_XTAL32K_MSK      (((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS)
+#define AON_DTEN_XTAL32K_UMSK     (~(((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS))
+#define AON_TEN_XTAL32K           AON_TEN_XTAL32K
+#define AON_TEN_XTAL32K_POS       (6U)
+#define AON_TEN_XTAL32K_LEN       (1U)
+#define AON_TEN_XTAL32K_MSK       (((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS)
+#define AON_TEN_XTAL32K_UMSK      (~(((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS))
+#define AON_TEN_VDDCORE_AON       AON_TEN_VDDCORE_AON
+#define AON_TEN_VDDCORE_AON_POS   (8U)
+#define AON_TEN_VDDCORE_AON_LEN   (1U)
+#define AON_TEN_VDDCORE_AON_MSK   (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)
+#define AON_TEN_VDDCORE_AON_UMSK  (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS))
+#define AON_TEN_LDO11SOC_AON      AON_TEN_LDO11SOC_AON
+#define AON_TEN_LDO11SOC_AON_POS  (9U)
+#define AON_TEN_LDO11SOC_AON_LEN  (1U)
+#define AON_TEN_LDO11SOC_AON_MSK  (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)
+#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS))
+#define AON_TEN_DCDC18_0_AON      AON_TEN_DCDC18_0_AON
+#define AON_TEN_DCDC18_0_AON_POS  (10U)
+#define AON_TEN_DCDC18_0_AON_LEN  (1U)
+#define AON_TEN_DCDC18_0_AON_MSK  (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)
+#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS))
+#define AON_TEN_DCDC18_1_AON      AON_TEN_DCDC18_1_AON
+#define AON_TEN_DCDC18_1_AON_POS  (11U)
+#define AON_TEN_DCDC18_1_AON_LEN  (1U)
+#define AON_TEN_DCDC18_1_AON_MSK  (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)
+#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS))
+#define AON_TEN_BG_SYS_AON        AON_TEN_BG_SYS_AON
+#define AON_TEN_BG_SYS_AON_POS    (12U)
+#define AON_TEN_BG_SYS_AON_LEN    (1U)
+#define AON_TEN_BG_SYS_AON_MSK    (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)
+#define AON_TEN_BG_SYS_AON_UMSK   (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS))
+#define AON_TEN_LDO15RF_AON       AON_TEN_LDO15RF_AON
+#define AON_TEN_LDO15RF_AON_POS   (16U)
+#define AON_TEN_LDO15RF_AON_LEN   (1U)
+#define AON_TEN_LDO15RF_AON_MSK   (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)
+#define AON_TEN_LDO15RF_AON_UMSK  (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS))
+#define AON_TEN_XTAL_AON          AON_TEN_XTAL_AON
+#define AON_TEN_XTAL_AON_POS      (17U)
+#define AON_TEN_XTAL_AON_LEN      (1U)
+#define AON_TEN_XTAL_AON_MSK      (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)
+#define AON_TEN_XTAL_AON_UMSK     (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS))
+#define AON_DTEN_XTAL_AON         AON_DTEN_XTAL_AON
+#define AON_DTEN_XTAL_AON_POS     (18U)
+#define AON_DTEN_XTAL_AON_LEN     (1U)
+#define AON_DTEN_XTAL_AON_MSK     (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)
+#define AON_DTEN_XTAL_AON_UMSK    (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS))
+#define AON_TEN_MBG_AON           AON_TEN_MBG_AON
+#define AON_TEN_MBG_AON_POS       (19U)
+#define AON_TEN_MBG_AON_LEN       (1U)
+#define AON_TEN_MBG_AON_MSK       (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)
+#define AON_TEN_MBG_AON_UMSK      (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS))
+#define AON_TEN_CIP_MISC_AON      AON_TEN_CIP_MISC_AON
+#define AON_TEN_CIP_MISC_AON_POS  (20U)
+#define AON_TEN_CIP_MISC_AON_LEN  (1U)
+#define AON_TEN_CIP_MISC_AON_MSK  (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)
+#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS))
+
+/* 0x808 : aon_misc */
+#define AON_MISC_OFFSET        (0x808)
+#define AON_SW_SOC_EN_AON      AON_SW_SOC_EN_AON
+#define AON_SW_SOC_EN_AON_POS  (0U)
+#define AON_SW_SOC_EN_AON_LEN  (1U)
+#define AON_SW_SOC_EN_AON_MSK  (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)
+#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS))
+#define AON_SW_WB_EN_AON       AON_SW_WB_EN_AON
+#define AON_SW_WB_EN_AON_POS   (1U)
+#define AON_SW_WB_EN_AON_LEN   (1U)
+#define AON_SW_WB_EN_AON_MSK   (((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS)
+#define AON_SW_WB_EN_AON_UMSK  (~(((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS))
+
+/* 0x810 : bg_sys_top */
+#define AON_BG_SYS_TOP_OFFSET          (0x810)
+#define AON_PMIP_RESV                  AON_PMIP_RESV
+#define AON_PMIP_RESV_POS              (0U)
+#define AON_PMIP_RESV_LEN              (8U)
+#define AON_PMIP_RESV_MSK              (((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS)
+#define AON_PMIP_RESV_UMSK             (~(((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS))
+#define AON_PU_BG_SYS_AON              AON_PU_BG_SYS_AON
+#define AON_PU_BG_SYS_AON_POS          (8U)
+#define AON_PU_BG_SYS_AON_LEN          (1U)
+#define AON_PU_BG_SYS_AON_MSK          (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)
+#define AON_PU_BG_SYS_AON_UMSK         (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS))
+#define AON_BG_SYS_START_CTRL_AON      AON_BG_SYS_START_CTRL_AON
+#define AON_BG_SYS_START_CTRL_AON_POS  (12U)
+#define AON_BG_SYS_START_CTRL_AON_LEN  (1U)
+#define AON_BG_SYS_START_CTRL_AON_MSK  (((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS)
+#define AON_BG_SYS_START_CTRL_AON_UMSK (~(((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS))
+
+/* 0x814 : dcdc18_top_0 */
+#define AON_DCDC18_TOP_0_OFFSET            (0x814)
+#define AON_DCDC18_VOUT_SEL_AON            AON_DCDC18_VOUT_SEL_AON
+#define AON_DCDC18_VOUT_SEL_AON_POS        (1U)
+#define AON_DCDC18_VOUT_SEL_AON_LEN        (5U)
+#define AON_DCDC18_VOUT_SEL_AON_MSK        (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)
+#define AON_DCDC18_VOUT_SEL_AON_UMSK       (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS))
+#define AON_DCDC18_VPFM_AON                AON_DCDC18_VPFM_AON
+#define AON_DCDC18_VPFM_AON_POS            (8U)
+#define AON_DCDC18_VPFM_AON_LEN            (4U)
+#define AON_DCDC18_VPFM_AON_MSK            (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)
+#define AON_DCDC18_VPFM_AON_UMSK           (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS))
+#define AON_DCDC18_OSC_2M_MODE_AON         AON_DCDC18_OSC_2M_MODE_AON
+#define AON_DCDC18_OSC_2M_MODE_AON_POS     (12U)
+#define AON_DCDC18_OSC_2M_MODE_AON_LEN     (1U)
+#define AON_DCDC18_OSC_2M_MODE_AON_MSK     (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)
+#define AON_DCDC18_OSC_2M_MODE_AON_UMSK    (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS))
+#define AON_DCDC18_OSC_FREQ_TRIM_AON       AON_DCDC18_OSC_FREQ_TRIM_AON
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS   (16U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN   (4U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK   (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK  (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS))
+#define AON_DCDC18_SLOPE_CURR_SEL_AON      AON_DCDC18_SLOPE_CURR_SEL_AON
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS  (20U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN  (5U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK  (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS))
+#define AON_DCDC18_STOP_OSC_AON            AON_DCDC18_STOP_OSC_AON
+#define AON_DCDC18_STOP_OSC_AON_POS        (25U)
+#define AON_DCDC18_STOP_OSC_AON_LEN        (1U)
+#define AON_DCDC18_STOP_OSC_AON_MSK        (((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS)
+#define AON_DCDC18_STOP_OSC_AON_UMSK       (~(((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS))
+#define AON_DCDC18_SLOW_OSC_AON            AON_DCDC18_SLOW_OSC_AON
+#define AON_DCDC18_SLOW_OSC_AON_POS        (26U)
+#define AON_DCDC18_SLOW_OSC_AON_LEN        (1U)
+#define AON_DCDC18_SLOW_OSC_AON_MSK        (((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS)
+#define AON_DCDC18_SLOW_OSC_AON_UMSK       (~(((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS))
+#define AON_DCDC18_OSC_INHIBIT_T2_AON      AON_DCDC18_OSC_INHIBIT_T2_AON
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_POS  (27U)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_LEN  (1U)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_MSK  (((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS))
+#define AON_DCDC18_SSTART_TIME_AON         AON_DCDC18_SSTART_TIME_AON
+#define AON_DCDC18_SSTART_TIME_AON_POS     (28U)
+#define AON_DCDC18_SSTART_TIME_AON_LEN     (2U)
+#define AON_DCDC18_SSTART_TIME_AON_MSK     (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)
+#define AON_DCDC18_SSTART_TIME_AON_UMSK    (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS))
+#define AON_DCDC18_RDY_AON                 AON_DCDC18_RDY_AON
+#define AON_DCDC18_RDY_AON_POS             (31U)
+#define AON_DCDC18_RDY_AON_LEN             (1U)
+#define AON_DCDC18_RDY_AON_MSK             (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)
+#define AON_DCDC18_RDY_AON_UMSK            (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS))
+
+/* 0x818 : dcdc18_top_1 */
+#define AON_DCDC18_TOP_1_OFFSET           (0x818)
+#define AON_DCDC18_FORCE_CS_ZVS_AON       AON_DCDC18_FORCE_CS_ZVS_AON
+#define AON_DCDC18_FORCE_CS_ZVS_AON_POS   (0U)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_LEN   (1U)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_MSK   (((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_UMSK  (~(((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS))
+#define AON_DCDC18_CS_DELAY_AON           AON_DCDC18_CS_DELAY_AON
+#define AON_DCDC18_CS_DELAY_AON_POS       (1U)
+#define AON_DCDC18_CS_DELAY_AON_LEN       (3U)
+#define AON_DCDC18_CS_DELAY_AON_MSK       (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)
+#define AON_DCDC18_CS_DELAY_AON_UMSK      (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS))
+#define AON_DCDC18_ZVS_TD_OPT_AON         AON_DCDC18_ZVS_TD_OPT_AON
+#define AON_DCDC18_ZVS_TD_OPT_AON_POS     (4U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_LEN     (3U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_MSK     (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)
+#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK    (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS))
+#define AON_DCDC18_NONOVERLAP_TD_AON      AON_DCDC18_NONOVERLAP_TD_AON
+#define AON_DCDC18_NONOVERLAP_TD_AON_POS  (8U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_LEN  (5U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_MSK  (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)
+#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS))
+#define AON_DCDC18_RC_SEL_AON             AON_DCDC18_RC_SEL_AON
+#define AON_DCDC18_RC_SEL_AON_POS         (16U)
+#define AON_DCDC18_RC_SEL_AON_LEN         (4U)
+#define AON_DCDC18_RC_SEL_AON_MSK         (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)
+#define AON_DCDC18_RC_SEL_AON_UMSK        (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS))
+#define AON_DCDC18_CHF_SEL_AON            AON_DCDC18_CHF_SEL_AON
+#define AON_DCDC18_CHF_SEL_AON_POS        (20U)
+#define AON_DCDC18_CHF_SEL_AON_LEN        (4U)
+#define AON_DCDC18_CHF_SEL_AON_MSK        (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)
+#define AON_DCDC18_CHF_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS))
+#define AON_DCDC18_CFB_SEL_AON            AON_DCDC18_CFB_SEL_AON
+#define AON_DCDC18_CFB_SEL_AON_POS        (24U)
+#define AON_DCDC18_CFB_SEL_AON_LEN        (4U)
+#define AON_DCDC18_CFB_SEL_AON_MSK        (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)
+#define AON_DCDC18_CFB_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS))
+#define AON_DCDC18_EN_ANTIRING_AON        AON_DCDC18_EN_ANTIRING_AON
+#define AON_DCDC18_EN_ANTIRING_AON_POS    (28U)
+#define AON_DCDC18_EN_ANTIRING_AON_LEN    (1U)
+#define AON_DCDC18_EN_ANTIRING_AON_MSK    (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)
+#define AON_DCDC18_EN_ANTIRING_AON_UMSK   (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS))
+#define AON_DCDC18_PULLDOWN_AON           AON_DCDC18_PULLDOWN_AON
+#define AON_DCDC18_PULLDOWN_AON_POS       (29U)
+#define AON_DCDC18_PULLDOWN_AON_LEN       (1U)
+#define AON_DCDC18_PULLDOWN_AON_MSK       (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)
+#define AON_DCDC18_PULLDOWN_AON_UMSK      (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS))
+
+/* 0x81C : ldo11soc_and_dctest */
+#define AON_LDO11SOC_AND_DCTEST_OFFSET     (0x81C)
+#define AON_PU_LDO11SOC_AON                AON_PU_LDO11SOC_AON
+#define AON_PU_LDO11SOC_AON_POS            (0U)
+#define AON_PU_LDO11SOC_AON_LEN            (1U)
+#define AON_PU_LDO11SOC_AON_MSK            (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)
+#define AON_PU_LDO11SOC_AON_UMSK           (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS))
+#define AON_LDO11SOC_SSTART_SEL_AON        AON_LDO11SOC_SSTART_SEL_AON
+#define AON_LDO11SOC_SSTART_SEL_AON_POS    (4U)
+#define AON_LDO11SOC_SSTART_SEL_AON_LEN    (1U)
+#define AON_LDO11SOC_SSTART_SEL_AON_MSK    (((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS)
+#define AON_LDO11SOC_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS))
+#define AON_LDO11SOC_SSTART_DELAY_AON      AON_LDO11SOC_SSTART_DELAY_AON
+#define AON_LDO11SOC_SSTART_DELAY_AON_POS  (8U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_MSK  (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)
+#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_AON          AON_LDO11SOC_PULLDOWN_AON
+#define AON_LDO11SOC_PULLDOWN_AON_POS      (10U)
+#define AON_LDO11SOC_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO11SOC_PULLDOWN_AON_MSK      (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_SEL_AON      AON_LDO11SOC_PULLDOWN_SEL_AON
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS  (11U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS))
+#define AON_LDO11SOC_VTH_SEL_AON           AON_LDO11SOC_VTH_SEL_AON
+#define AON_LDO11SOC_VTH_SEL_AON_POS       (12U)
+#define AON_LDO11SOC_VTH_SEL_AON_LEN       (2U)
+#define AON_LDO11SOC_VTH_SEL_AON_MSK       (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)
+#define AON_LDO11SOC_VTH_SEL_AON_UMSK      (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS))
+#define AON_LDO11SOC_CC_AON                AON_LDO11SOC_CC_AON
+#define AON_LDO11SOC_CC_AON_POS            (24U)
+#define AON_LDO11SOC_CC_AON_LEN            (2U)
+#define AON_LDO11SOC_CC_AON_MSK            (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)
+#define AON_LDO11SOC_CC_AON_UMSK           (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS))
+#define AON_LDO11SOC_RDY_AON               AON_LDO11SOC_RDY_AON
+#define AON_LDO11SOC_RDY_AON_POS           (28U)
+#define AON_LDO11SOC_RDY_AON_LEN           (1U)
+#define AON_LDO11SOC_RDY_AON_MSK           (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)
+#define AON_LDO11SOC_RDY_AON_UMSK          (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS))
+#define AON_LDO11SOC_POWER_GOOD_AON        AON_LDO11SOC_POWER_GOOD_AON
+#define AON_LDO11SOC_POWER_GOOD_AON_POS    (29U)
+#define AON_LDO11SOC_POWER_GOOD_AON_LEN    (1U)
+#define AON_LDO11SOC_POWER_GOOD_AON_MSK    (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)
+#define AON_LDO11SOC_POWER_GOOD_AON_UMSK   (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS))
+#define AON_PU_VDDCORE_MISC_AON            AON_PU_VDDCORE_MISC_AON
+#define AON_PU_VDDCORE_MISC_AON_POS        (30U)
+#define AON_PU_VDDCORE_MISC_AON_LEN        (1U)
+#define AON_PU_VDDCORE_MISC_AON_MSK        (((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS)
+#define AON_PU_VDDCORE_MISC_AON_UMSK       (~(((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS))
+#define AON_PMIP_DC_TP_OUT_EN_AON          AON_PMIP_DC_TP_OUT_EN_AON
+#define AON_PMIP_DC_TP_OUT_EN_AON_POS      (31U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_LEN      (1U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_MSK      (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)
+#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK     (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS))
+
+/* 0x820 : psw_irrcv */
+#define AON_PSW_IRRCV_OFFSET   (0x820)
+#define AON_PU_IR_PSW_AON      AON_PU_IR_PSW_AON
+#define AON_PU_IR_PSW_AON_POS  (0U)
+#define AON_PU_IR_PSW_AON_LEN  (1U)
+#define AON_PU_IR_PSW_AON_MSK  (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)
+#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS))
+
+/* 0x880 : rf_top_aon */
+#define AON_RF_TOP_AON_OFFSET             (0x880)
+#define AON_PU_MBG_AON                    AON_PU_MBG_AON
+#define AON_PU_MBG_AON_POS                (0U)
+#define AON_PU_MBG_AON_LEN                (1U)
+#define AON_PU_MBG_AON_MSK                (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)
+#define AON_PU_MBG_AON_UMSK               (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS))
+#define AON_PU_LDO15RF_AON                AON_PU_LDO15RF_AON
+#define AON_PU_LDO15RF_AON_POS            (1U)
+#define AON_PU_LDO15RF_AON_LEN            (1U)
+#define AON_PU_LDO15RF_AON_MSK            (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)
+#define AON_PU_LDO15RF_AON_UMSK           (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS))
+#define AON_PU_SFREG_AON                  AON_PU_SFREG_AON
+#define AON_PU_SFREG_AON_POS              (2U)
+#define AON_PU_SFREG_AON_LEN              (1U)
+#define AON_PU_SFREG_AON_MSK              (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)
+#define AON_PU_SFREG_AON_UMSK             (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS))
+#define AON_PU_XTAL_BUF_AON               AON_PU_XTAL_BUF_AON
+#define AON_PU_XTAL_BUF_AON_POS           (4U)
+#define AON_PU_XTAL_BUF_AON_LEN           (1U)
+#define AON_PU_XTAL_BUF_AON_MSK           (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)
+#define AON_PU_XTAL_BUF_AON_UMSK          (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS))
+#define AON_PU_XTAL_AON                   AON_PU_XTAL_AON
+#define AON_PU_XTAL_AON_POS               (5U)
+#define AON_PU_XTAL_AON_LEN               (1U)
+#define AON_PU_XTAL_AON_MSK               (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)
+#define AON_PU_XTAL_AON_UMSK              (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS))
+#define AON_LDO15RF_SSTART_SEL_AON        AON_LDO15RF_SSTART_SEL_AON
+#define AON_LDO15RF_SSTART_SEL_AON_POS    (8U)
+#define AON_LDO15RF_SSTART_SEL_AON_LEN    (1U)
+#define AON_LDO15RF_SSTART_SEL_AON_MSK    (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)
+#define AON_LDO15RF_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS))
+#define AON_LDO15RF_SSTART_DELAY_AON      AON_LDO15RF_SSTART_DELAY_AON
+#define AON_LDO15RF_SSTART_DELAY_AON_POS  (9U)
+#define AON_LDO15RF_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO15RF_SSTART_DELAY_AON_MSK  (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)
+#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS))
+#define AON_LDO15RF_PULLDOWN_AON          AON_LDO15RF_PULLDOWN_AON
+#define AON_LDO15RF_PULLDOWN_AON_POS      (12U)
+#define AON_LDO15RF_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO15RF_PULLDOWN_AON_MSK      (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)
+#define AON_LDO15RF_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS))
+#define AON_LDO15RF_PULLDOWN_SEL_AON      AON_LDO15RF_PULLDOWN_SEL_AON
+#define AON_LDO15RF_PULLDOWN_SEL_AON_POS  (13U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS))
+#define AON_LDO15RF_VOUT_SEL_AON          AON_LDO15RF_VOUT_SEL_AON
+#define AON_LDO15RF_VOUT_SEL_AON_POS      (16U)
+#define AON_LDO15RF_VOUT_SEL_AON_LEN      (3U)
+#define AON_LDO15RF_VOUT_SEL_AON_MSK      (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)
+#define AON_LDO15RF_VOUT_SEL_AON_UMSK     (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS))
+#define AON_LDO15RF_CC_AON                AON_LDO15RF_CC_AON
+#define AON_LDO15RF_CC_AON_POS            (24U)
+#define AON_LDO15RF_CC_AON_LEN            (2U)
+#define AON_LDO15RF_CC_AON_MSK            (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)
+#define AON_LDO15RF_CC_AON_UMSK           (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS))
+#define AON_LDO15RF_BYPASS_AON            AON_LDO15RF_BYPASS_AON
+#define AON_LDO15RF_BYPASS_AON_POS        (28U)
+#define AON_LDO15RF_BYPASS_AON_LEN        (1U)
+#define AON_LDO15RF_BYPASS_AON_MSK        (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)
+#define AON_LDO15RF_BYPASS_AON_UMSK       (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS))
+
+/* 0x884 : xtal_cfg */
+#define AON_XTAL_CFG_OFFSET             (0x884)
+#define AON_XTAL_BK_AON                 AON_XTAL_BK_AON
+#define AON_XTAL_BK_AON_POS             (0U)
+#define AON_XTAL_BK_AON_LEN             (2U)
+#define AON_XTAL_BK_AON_MSK             (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)
+#define AON_XTAL_BK_AON_UMSK            (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS))
+#define AON_XTAL_CAPCODE_EXTRA_AON      AON_XTAL_CAPCODE_EXTRA_AON
+#define AON_XTAL_CAPCODE_EXTRA_AON_POS  (2U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_LEN  (1U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_MSK  (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)
+#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS))
+#define AON_XTAL_EXT_SEL_AON            AON_XTAL_EXT_SEL_AON
+#define AON_XTAL_EXT_SEL_AON_POS        (3U)
+#define AON_XTAL_EXT_SEL_AON_LEN        (1U)
+#define AON_XTAL_EXT_SEL_AON_MSK        (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)
+#define AON_XTAL_EXT_SEL_AON_UMSK       (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS))
+#define AON_XTAL_BUF_EN_AON             AON_XTAL_BUF_EN_AON
+#define AON_XTAL_BUF_EN_AON_POS         (4U)
+#define AON_XTAL_BUF_EN_AON_LEN         (4U)
+#define AON_XTAL_BUF_EN_AON_MSK         (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)
+#define AON_XTAL_BUF_EN_AON_UMSK        (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS))
+#define AON_XTAL_BUF_HP_AON             AON_XTAL_BUF_HP_AON
+#define AON_XTAL_BUF_HP_AON_POS         (8U)
+#define AON_XTAL_BUF_HP_AON_LEN         (4U)
+#define AON_XTAL_BUF_HP_AON_MSK         (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)
+#define AON_XTAL_BUF_HP_AON_UMSK        (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS))
+#define AON_XTAL_FAST_STARTUP_AON       AON_XTAL_FAST_STARTUP_AON
+#define AON_XTAL_FAST_STARTUP_AON_POS   (12U)
+#define AON_XTAL_FAST_STARTUP_AON_LEN   (1U)
+#define AON_XTAL_FAST_STARTUP_AON_MSK   (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)
+#define AON_XTAL_FAST_STARTUP_AON_UMSK  (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS))
+#define AON_XTAL_SLEEP_AON              AON_XTAL_SLEEP_AON
+#define AON_XTAL_SLEEP_AON_POS          (13U)
+#define AON_XTAL_SLEEP_AON_LEN          (1U)
+#define AON_XTAL_SLEEP_AON_MSK          (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)
+#define AON_XTAL_SLEEP_AON_UMSK         (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS))
+#define AON_XTAL_AMP_CTRL_AON           AON_XTAL_AMP_CTRL_AON
+#define AON_XTAL_AMP_CTRL_AON_POS       (14U)
+#define AON_XTAL_AMP_CTRL_AON_LEN       (2U)
+#define AON_XTAL_AMP_CTRL_AON_MSK       (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)
+#define AON_XTAL_AMP_CTRL_AON_UMSK      (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS))
+#define AON_XTAL_CAPCODE_OUT_AON        AON_XTAL_CAPCODE_OUT_AON
+#define AON_XTAL_CAPCODE_OUT_AON_POS    (16U)
+#define AON_XTAL_CAPCODE_OUT_AON_LEN    (6U)
+#define AON_XTAL_CAPCODE_OUT_AON_MSK    (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)
+#define AON_XTAL_CAPCODE_OUT_AON_UMSK   (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS))
+#define AON_XTAL_CAPCODE_IN_AON         AON_XTAL_CAPCODE_IN_AON
+#define AON_XTAL_CAPCODE_IN_AON_POS     (22U)
+#define AON_XTAL_CAPCODE_IN_AON_LEN     (6U)
+#define AON_XTAL_CAPCODE_IN_AON_MSK     (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)
+#define AON_XTAL_CAPCODE_IN_AON_UMSK    (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS))
+#define AON_XTAL_GM_BOOST_AON           AON_XTAL_GM_BOOST_AON
+#define AON_XTAL_GM_BOOST_AON_POS       (28U)
+#define AON_XTAL_GM_BOOST_AON_LEN       (2U)
+#define AON_XTAL_GM_BOOST_AON_MSK       (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)
+#define AON_XTAL_GM_BOOST_AON_UMSK      (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS))
+#define AON_XTAL_RDY_SEL_AON            AON_XTAL_RDY_SEL_AON
+#define AON_XTAL_RDY_SEL_AON_POS        (30U)
+#define AON_XTAL_RDY_SEL_AON_LEN        (2U)
+#define AON_XTAL_RDY_SEL_AON_MSK        (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)
+#define AON_XTAL_RDY_SEL_AON_UMSK       (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS))
+
+/* 0x888 : tsen */
+#define AON_TSEN_OFFSET               (0x888)
+#define AON_TSEN_REFCODE_CORNER       AON_TSEN_REFCODE_CORNER
+#define AON_TSEN_REFCODE_CORNER_POS   (0U)
+#define AON_TSEN_REFCODE_CORNER_LEN   (12U)
+#define AON_TSEN_REFCODE_CORNER_MSK   (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)
+#define AON_TSEN_REFCODE_CORNER_UMSK  (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS))
+#define AON_TSEN_REFCODE_RFCAL        AON_TSEN_REFCODE_RFCAL
+#define AON_TSEN_REFCODE_RFCAL_POS    (16U)
+#define AON_TSEN_REFCODE_RFCAL_LEN    (12U)
+#define AON_TSEN_REFCODE_RFCAL_MSK    (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)
+#define AON_TSEN_REFCODE_RFCAL_UMSK   (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS))
+#define AON_XTAL_RDY                  AON_XTAL_RDY
+#define AON_XTAL_RDY_POS              (28U)
+#define AON_XTAL_RDY_LEN              (1U)
+#define AON_XTAL_RDY_MSK              (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)
+#define AON_XTAL_RDY_UMSK             (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS))
+#define AON_XTAL_INN_CFG_EN_AON       AON_XTAL_INN_CFG_EN_AON
+#define AON_XTAL_INN_CFG_EN_AON_POS   (29U)
+#define AON_XTAL_INN_CFG_EN_AON_LEN   (1U)
+#define AON_XTAL_INN_CFG_EN_AON_MSK   (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)
+#define AON_XTAL_INN_CFG_EN_AON_UMSK  (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS))
+#define AON_XTAL_RDY_INT_SEL_AON      AON_XTAL_RDY_INT_SEL_AON
+#define AON_XTAL_RDY_INT_SEL_AON_POS  (30U)
+#define AON_XTAL_RDY_INT_SEL_AON_LEN  (2U)
+#define AON_XTAL_RDY_INT_SEL_AON_MSK  (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)
+#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS))
+
+/* 0x900 : acomp0_ctrl */
+#define AON_ACOMP0_CTRL_OFFSET    (0x900)
+#define AON_ACOMP0_EN             AON_ACOMP0_EN
+#define AON_ACOMP0_EN_POS         (0U)
+#define AON_ACOMP0_EN_LEN         (1U)
+#define AON_ACOMP0_EN_MSK         (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)
+#define AON_ACOMP0_EN_UMSK        (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS))
+#define AON_ACOMP0_HYST_SELN      AON_ACOMP0_HYST_SELN
+#define AON_ACOMP0_HYST_SELN_POS  (4U)
+#define AON_ACOMP0_HYST_SELN_LEN  (3U)
+#define AON_ACOMP0_HYST_SELN_MSK  (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)
+#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS))
+#define AON_ACOMP0_HYST_SELP      AON_ACOMP0_HYST_SELP
+#define AON_ACOMP0_HYST_SELP_POS  (7U)
+#define AON_ACOMP0_HYST_SELP_LEN  (3U)
+#define AON_ACOMP0_HYST_SELP_MSK  (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)
+#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS))
+#define AON_ACOMP0_BIAS_PROG      AON_ACOMP0_BIAS_PROG
+#define AON_ACOMP0_BIAS_PROG_POS  (10U)
+#define AON_ACOMP0_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP0_BIAS_PROG_MSK  (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)
+#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS))
+#define AON_ACOMP0_LEVEL_SEL      AON_ACOMP0_LEVEL_SEL
+#define AON_ACOMP0_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP0_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP0_LEVEL_SEL_MSK  (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)
+#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS))
+#define AON_ACOMP0_NEG_SEL        AON_ACOMP0_NEG_SEL
+#define AON_ACOMP0_NEG_SEL_POS    (18U)
+#define AON_ACOMP0_NEG_SEL_LEN    (4U)
+#define AON_ACOMP0_NEG_SEL_MSK    (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)
+#define AON_ACOMP0_NEG_SEL_UMSK   (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS))
+#define AON_ACOMP0_POS_SEL        AON_ACOMP0_POS_SEL
+#define AON_ACOMP0_POS_SEL_POS    (22U)
+#define AON_ACOMP0_POS_SEL_LEN    (4U)
+#define AON_ACOMP0_POS_SEL_MSK    (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)
+#define AON_ACOMP0_POS_SEL_UMSK   (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS))
+#define AON_ACOMP0_MUXEN          AON_ACOMP0_MUXEN
+#define AON_ACOMP0_MUXEN_POS      (26U)
+#define AON_ACOMP0_MUXEN_LEN      (1U)
+#define AON_ACOMP0_MUXEN_MSK      (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)
+#define AON_ACOMP0_MUXEN_UMSK     (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS))
+
+/* 0x904 : acomp1_ctrl */
+#define AON_ACOMP1_CTRL_OFFSET    (0x904)
+#define AON_ACOMP1_EN             AON_ACOMP1_EN
+#define AON_ACOMP1_EN_POS         (0U)
+#define AON_ACOMP1_EN_LEN         (1U)
+#define AON_ACOMP1_EN_MSK         (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)
+#define AON_ACOMP1_EN_UMSK        (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS))
+#define AON_ACOMP1_HYST_SELN      AON_ACOMP1_HYST_SELN
+#define AON_ACOMP1_HYST_SELN_POS  (4U)
+#define AON_ACOMP1_HYST_SELN_LEN  (3U)
+#define AON_ACOMP1_HYST_SELN_MSK  (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)
+#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS))
+#define AON_ACOMP1_HYST_SELP      AON_ACOMP1_HYST_SELP
+#define AON_ACOMP1_HYST_SELP_POS  (7U)
+#define AON_ACOMP1_HYST_SELP_LEN  (3U)
+#define AON_ACOMP1_HYST_SELP_MSK  (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)
+#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS))
+#define AON_ACOMP1_BIAS_PROG      AON_ACOMP1_BIAS_PROG
+#define AON_ACOMP1_BIAS_PROG_POS  (10U)
+#define AON_ACOMP1_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP1_BIAS_PROG_MSK  (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)
+#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS))
+#define AON_ACOMP1_LEVEL_SEL      AON_ACOMP1_LEVEL_SEL
+#define AON_ACOMP1_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP1_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP1_LEVEL_SEL_MSK  (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)
+#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS))
+#define AON_ACOMP1_NEG_SEL        AON_ACOMP1_NEG_SEL
+#define AON_ACOMP1_NEG_SEL_POS    (18U)
+#define AON_ACOMP1_NEG_SEL_LEN    (4U)
+#define AON_ACOMP1_NEG_SEL_MSK    (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)
+#define AON_ACOMP1_NEG_SEL_UMSK   (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS))
+#define AON_ACOMP1_POS_SEL        AON_ACOMP1_POS_SEL
+#define AON_ACOMP1_POS_SEL_POS    (22U)
+#define AON_ACOMP1_POS_SEL_LEN    (4U)
+#define AON_ACOMP1_POS_SEL_MSK    (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)
+#define AON_ACOMP1_POS_SEL_UMSK   (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS))
+#define AON_ACOMP1_MUXEN          AON_ACOMP1_MUXEN
+#define AON_ACOMP1_MUXEN_POS      (26U)
+#define AON_ACOMP1_MUXEN_LEN      (1U)
+#define AON_ACOMP1_MUXEN_MSK      (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)
+#define AON_ACOMP1_MUXEN_UMSK     (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS))
+
+/* 0x908 : acomp_ctrl */
+#define AON_ACOMP_CTRL_OFFSET    (0x908)
+#define AON_ACOMP1_RSTN_ANA      AON_ACOMP1_RSTN_ANA
+#define AON_ACOMP1_RSTN_ANA_POS  (0U)
+#define AON_ACOMP1_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP1_RSTN_ANA_MSK  (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)
+#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS))
+#define AON_ACOMP0_RSTN_ANA      AON_ACOMP0_RSTN_ANA
+#define AON_ACOMP0_RSTN_ANA_POS  (1U)
+#define AON_ACOMP0_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP0_RSTN_ANA_MSK  (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)
+#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS))
+#define AON_ACOMP1_TEST_EN       AON_ACOMP1_TEST_EN
+#define AON_ACOMP1_TEST_EN_POS   (8U)
+#define AON_ACOMP1_TEST_EN_LEN   (1U)
+#define AON_ACOMP1_TEST_EN_MSK   (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)
+#define AON_ACOMP1_TEST_EN_UMSK  (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS))
+#define AON_ACOMP0_TEST_EN       AON_ACOMP0_TEST_EN
+#define AON_ACOMP0_TEST_EN_POS   (9U)
+#define AON_ACOMP0_TEST_EN_LEN   (1U)
+#define AON_ACOMP0_TEST_EN_MSK   (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)
+#define AON_ACOMP0_TEST_EN_UMSK  (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS))
+#define AON_ACOMP1_TEST_SEL      AON_ACOMP1_TEST_SEL
+#define AON_ACOMP1_TEST_SEL_POS  (10U)
+#define AON_ACOMP1_TEST_SEL_LEN  (2U)
+#define AON_ACOMP1_TEST_SEL_MSK  (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)
+#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS))
+#define AON_ACOMP0_TEST_SEL      AON_ACOMP0_TEST_SEL
+#define AON_ACOMP0_TEST_SEL_POS  (12U)
+#define AON_ACOMP0_TEST_SEL_LEN  (2U)
+#define AON_ACOMP0_TEST_SEL_MSK  (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)
+#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS))
+#define AON_ACOMP1_OUT_RAW       AON_ACOMP1_OUT_RAW
+#define AON_ACOMP1_OUT_RAW_POS   (17U)
+#define AON_ACOMP1_OUT_RAW_LEN   (1U)
+#define AON_ACOMP1_OUT_RAW_MSK   (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)
+#define AON_ACOMP1_OUT_RAW_UMSK  (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS))
+#define AON_ACOMP0_OUT_RAW       AON_ACOMP0_OUT_RAW
+#define AON_ACOMP0_OUT_RAW_POS   (19U)
+#define AON_ACOMP0_OUT_RAW_LEN   (1U)
+#define AON_ACOMP0_OUT_RAW_MSK   (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)
+#define AON_ACOMP0_OUT_RAW_UMSK  (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS))
+#define AON_ACOMP_RESERVED       AON_ACOMP_RESERVED
+#define AON_ACOMP_RESERVED_POS   (24U)
+#define AON_ACOMP_RESERVED_LEN   (8U)
+#define AON_ACOMP_RESERVED_MSK   (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)
+#define AON_ACOMP_RESERVED_UMSK  (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS))
+
+/* 0x90C : gpadc_reg_cmd */
+#define AON_GPADC_REG_CMD_OFFSET        (0x90C)
+#define AON_GPADC_GLOBAL_EN             AON_GPADC_GLOBAL_EN
+#define AON_GPADC_GLOBAL_EN_POS         (0U)
+#define AON_GPADC_GLOBAL_EN_LEN         (1U)
+#define AON_GPADC_GLOBAL_EN_MSK         (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)
+#define AON_GPADC_GLOBAL_EN_UMSK        (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS))
+#define AON_GPADC_CONV_START            AON_GPADC_CONV_START
+#define AON_GPADC_CONV_START_POS        (1U)
+#define AON_GPADC_CONV_START_LEN        (1U)
+#define AON_GPADC_CONV_START_MSK        (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)
+#define AON_GPADC_CONV_START_UMSK       (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS))
+#define AON_GPADC_SOFT_RST              AON_GPADC_SOFT_RST
+#define AON_GPADC_SOFT_RST_POS          (2U)
+#define AON_GPADC_SOFT_RST_LEN          (1U)
+#define AON_GPADC_SOFT_RST_MSK          (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)
+#define AON_GPADC_SOFT_RST_UMSK         (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS))
+#define AON_GPADC_NEG_SEL               AON_GPADC_NEG_SEL
+#define AON_GPADC_NEG_SEL_POS           (3U)
+#define AON_GPADC_NEG_SEL_LEN           (5U)
+#define AON_GPADC_NEG_SEL_MSK           (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)
+#define AON_GPADC_NEG_SEL_UMSK          (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS))
+#define AON_GPADC_POS_SEL               AON_GPADC_POS_SEL
+#define AON_GPADC_POS_SEL_POS           (8U)
+#define AON_GPADC_POS_SEL_LEN           (5U)
+#define AON_GPADC_POS_SEL_MSK           (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)
+#define AON_GPADC_POS_SEL_UMSK          (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS))
+#define AON_GPADC_NEG_GND               AON_GPADC_NEG_GND
+#define AON_GPADC_NEG_GND_POS           (13U)
+#define AON_GPADC_NEG_GND_LEN           (1U)
+#define AON_GPADC_NEG_GND_MSK           (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)
+#define AON_GPADC_NEG_GND_UMSK          (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS))
+#define AON_GPADC_MICBIAS_EN            AON_GPADC_MICBIAS_EN
+#define AON_GPADC_MICBIAS_EN_POS        (14U)
+#define AON_GPADC_MICBIAS_EN_LEN        (1U)
+#define AON_GPADC_MICBIAS_EN_MSK        (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)
+#define AON_GPADC_MICBIAS_EN_UMSK       (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS))
+#define AON_GPADC_MICPGA_EN             AON_GPADC_MICPGA_EN
+#define AON_GPADC_MICPGA_EN_POS         (15U)
+#define AON_GPADC_MICPGA_EN_LEN         (1U)
+#define AON_GPADC_MICPGA_EN_MSK         (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)
+#define AON_GPADC_MICPGA_EN_UMSK        (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS))
+#define AON_GPADC_BYP_MICBOOST          AON_GPADC_BYP_MICBOOST
+#define AON_GPADC_BYP_MICBOOST_POS      (16U)
+#define AON_GPADC_BYP_MICBOOST_LEN      (1U)
+#define AON_GPADC_BYP_MICBOOST_MSK      (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)
+#define AON_GPADC_BYP_MICBOOST_UMSK     (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS))
+#define AON_GPADC_DWA_EN                AON_GPADC_DWA_EN
+#define AON_GPADC_DWA_EN_POS            (18U)
+#define AON_GPADC_DWA_EN_LEN            (1U)
+#define AON_GPADC_DWA_EN_MSK            (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)
+#define AON_GPADC_DWA_EN_UMSK           (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS))
+#define AON_GPADC_MIC2_DIFF             AON_GPADC_MIC2_DIFF
+#define AON_GPADC_MIC2_DIFF_POS         (19U)
+#define AON_GPADC_MIC2_DIFF_LEN         (1U)
+#define AON_GPADC_MIC2_DIFF_MSK         (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)
+#define AON_GPADC_MIC2_DIFF_UMSK        (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS))
+#define AON_GPADC_MIC1_DIFF             AON_GPADC_MIC1_DIFF
+#define AON_GPADC_MIC1_DIFF_POS         (20U)
+#define AON_GPADC_MIC1_DIFF_LEN         (1U)
+#define AON_GPADC_MIC1_DIFF_MSK         (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)
+#define AON_GPADC_MIC1_DIFF_UMSK        (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS))
+#define AON_GPADC_MIC_PGA2_GAIN         AON_GPADC_MIC_PGA2_GAIN
+#define AON_GPADC_MIC_PGA2_GAIN_POS     (21U)
+#define AON_GPADC_MIC_PGA2_GAIN_LEN     (2U)
+#define AON_GPADC_MIC_PGA2_GAIN_MSK     (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)
+#define AON_GPADC_MIC_PGA2_GAIN_UMSK    (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS))
+#define AON_GPADC_MICBOOST_32DB_EN      AON_GPADC_MICBOOST_32DB_EN
+#define AON_GPADC_MICBOOST_32DB_EN_POS  (23U)
+#define AON_GPADC_MICBOOST_32DB_EN_LEN  (1U)
+#define AON_GPADC_MICBOOST_32DB_EN_MSK  (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)
+#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS))
+#define AON_GPADC_CHIP_SEN_PU           AON_GPADC_CHIP_SEN_PU
+#define AON_GPADC_CHIP_SEN_PU_POS       (27U)
+#define AON_GPADC_CHIP_SEN_PU_LEN       (1U)
+#define AON_GPADC_CHIP_SEN_PU_MSK       (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)
+#define AON_GPADC_CHIP_SEN_PU_UMSK      (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS))
+#define AON_GPADC_SEN_SEL               AON_GPADC_SEN_SEL
+#define AON_GPADC_SEN_SEL_POS           (28U)
+#define AON_GPADC_SEN_SEL_LEN           (2U)
+#define AON_GPADC_SEN_SEL_MSK           (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)
+#define AON_GPADC_SEN_SEL_UMSK          (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS))
+#define AON_GPADC_SEN_TEST_EN           AON_GPADC_SEN_TEST_EN
+#define AON_GPADC_SEN_TEST_EN_POS       (30U)
+#define AON_GPADC_SEN_TEST_EN_LEN       (1U)
+#define AON_GPADC_SEN_TEST_EN_MSK       (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)
+#define AON_GPADC_SEN_TEST_EN_UMSK      (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS))
+
+/* 0x910 : gpadc_reg_config1 */
+#define AON_GPADC_REG_CONFIG1_OFFSET (0x910)
+#define AON_GPADC_CAL_OS_EN          AON_GPADC_CAL_OS_EN
+#define AON_GPADC_CAL_OS_EN_POS      (0U)
+#define AON_GPADC_CAL_OS_EN_LEN      (1U)
+#define AON_GPADC_CAL_OS_EN_MSK      (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)
+#define AON_GPADC_CAL_OS_EN_UMSK     (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS))
+#define AON_GPADC_CONT_CONV_EN       AON_GPADC_CONT_CONV_EN
+#define AON_GPADC_CONT_CONV_EN_POS   (1U)
+#define AON_GPADC_CONT_CONV_EN_LEN   (1U)
+#define AON_GPADC_CONT_CONV_EN_MSK   (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)
+#define AON_GPADC_CONT_CONV_EN_UMSK  (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS))
+#define AON_GPADC_RES_SEL            AON_GPADC_RES_SEL
+#define AON_GPADC_RES_SEL_POS        (2U)
+#define AON_GPADC_RES_SEL_LEN        (3U)
+#define AON_GPADC_RES_SEL_MSK        (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)
+#define AON_GPADC_RES_SEL_UMSK       (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS))
+#define AON_GPADC_CLK_ANA_INV        AON_GPADC_CLK_ANA_INV
+#define AON_GPADC_CLK_ANA_INV_POS    (17U)
+#define AON_GPADC_CLK_ANA_INV_LEN    (1U)
+#define AON_GPADC_CLK_ANA_INV_MSK    (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)
+#define AON_GPADC_CLK_ANA_INV_UMSK   (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS))
+#define AON_GPADC_CLK_DIV_RATIO      AON_GPADC_CLK_DIV_RATIO
+#define AON_GPADC_CLK_DIV_RATIO_POS  (18U)
+#define AON_GPADC_CLK_DIV_RATIO_LEN  (3U)
+#define AON_GPADC_CLK_DIV_RATIO_MSK  (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)
+#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS))
+#define AON_GPADC_SCAN_LENGTH        AON_GPADC_SCAN_LENGTH
+#define AON_GPADC_SCAN_LENGTH_POS    (21U)
+#define AON_GPADC_SCAN_LENGTH_LEN    (4U)
+#define AON_GPADC_SCAN_LENGTH_MSK    (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)
+#define AON_GPADC_SCAN_LENGTH_UMSK   (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS))
+#define AON_GPADC_SCAN_EN            AON_GPADC_SCAN_EN
+#define AON_GPADC_SCAN_EN_POS        (25U)
+#define AON_GPADC_SCAN_EN_LEN        (1U)
+#define AON_GPADC_SCAN_EN_MSK        (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)
+#define AON_GPADC_SCAN_EN_UMSK       (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS))
+#define AON_GPADC_DITHER_EN          AON_GPADC_DITHER_EN
+#define AON_GPADC_DITHER_EN_POS      (26U)
+#define AON_GPADC_DITHER_EN_LEN      (1U)
+#define AON_GPADC_DITHER_EN_MSK      (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)
+#define AON_GPADC_DITHER_EN_UMSK     (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS))
+#define AON_GPADC_V11_SEL            AON_GPADC_V11_SEL
+#define AON_GPADC_V11_SEL_POS        (27U)
+#define AON_GPADC_V11_SEL_LEN        (2U)
+#define AON_GPADC_V11_SEL_MSK        (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)
+#define AON_GPADC_V11_SEL_UMSK       (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS))
+#define AON_GPADC_V18_SEL            AON_GPADC_V18_SEL
+#define AON_GPADC_V18_SEL_POS        (29U)
+#define AON_GPADC_V18_SEL_LEN        (2U)
+#define AON_GPADC_V18_SEL_MSK        (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)
+#define AON_GPADC_V18_SEL_UMSK       (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS))
+
+/* 0x914 : gpadc_reg_config2 */
+#define AON_GPADC_REG_CONFIG2_OFFSET (0x914)
+#define AON_GPADC_DIFF_MODE          AON_GPADC_DIFF_MODE
+#define AON_GPADC_DIFF_MODE_POS      (2U)
+#define AON_GPADC_DIFF_MODE_LEN      (1U)
+#define AON_GPADC_DIFF_MODE_MSK      (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)
+#define AON_GPADC_DIFF_MODE_UMSK     (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS))
+#define AON_GPADC_VREF_SEL           AON_GPADC_VREF_SEL
+#define AON_GPADC_VREF_SEL_POS       (3U)
+#define AON_GPADC_VREF_SEL_LEN       (1U)
+#define AON_GPADC_VREF_SEL_MSK       (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)
+#define AON_GPADC_VREF_SEL_UMSK      (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS))
+#define AON_GPADC_VBAT_EN            AON_GPADC_VBAT_EN
+#define AON_GPADC_VBAT_EN_POS        (4U)
+#define AON_GPADC_VBAT_EN_LEN        (1U)
+#define AON_GPADC_VBAT_EN_MSK        (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)
+#define AON_GPADC_VBAT_EN_UMSK       (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS))
+#define AON_GPADC_TSEXT_SEL          AON_GPADC_TSEXT_SEL
+#define AON_GPADC_TSEXT_SEL_POS      (5U)
+#define AON_GPADC_TSEXT_SEL_LEN      (1U)
+#define AON_GPADC_TSEXT_SEL_MSK      (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)
+#define AON_GPADC_TSEXT_SEL_UMSK     (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS))
+#define AON_GPADC_TS_EN              AON_GPADC_TS_EN
+#define AON_GPADC_TS_EN_POS          (6U)
+#define AON_GPADC_TS_EN_LEN          (1U)
+#define AON_GPADC_TS_EN_MSK          (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)
+#define AON_GPADC_TS_EN_UMSK         (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS))
+#define AON_GPADC_PGA_VCM            AON_GPADC_PGA_VCM
+#define AON_GPADC_PGA_VCM_POS        (7U)
+#define AON_GPADC_PGA_VCM_LEN        (2U)
+#define AON_GPADC_PGA_VCM_MSK        (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)
+#define AON_GPADC_PGA_VCM_UMSK       (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS))
+#define AON_GPADC_PGA_OS_CAL         AON_GPADC_PGA_OS_CAL
+#define AON_GPADC_PGA_OS_CAL_POS     (9U)
+#define AON_GPADC_PGA_OS_CAL_LEN     (4U)
+#define AON_GPADC_PGA_OS_CAL_MSK     (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)
+#define AON_GPADC_PGA_OS_CAL_UMSK    (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS))
+#define AON_GPADC_PGA_EN             AON_GPADC_PGA_EN
+#define AON_GPADC_PGA_EN_POS         (13U)
+#define AON_GPADC_PGA_EN_LEN         (1U)
+#define AON_GPADC_PGA_EN_MSK         (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)
+#define AON_GPADC_PGA_EN_UMSK        (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS))
+#define AON_GPADC_PGA_VCMI_EN        AON_GPADC_PGA_VCMI_EN
+#define AON_GPADC_PGA_VCMI_EN_POS    (14U)
+#define AON_GPADC_PGA_VCMI_EN_LEN    (1U)
+#define AON_GPADC_PGA_VCMI_EN_MSK    (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)
+#define AON_GPADC_PGA_VCMI_EN_UMSK   (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS))
+#define AON_GPADC_CHOP_MODE          AON_GPADC_CHOP_MODE
+#define AON_GPADC_CHOP_MODE_POS      (15U)
+#define AON_GPADC_CHOP_MODE_LEN      (2U)
+#define AON_GPADC_CHOP_MODE_MSK      (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)
+#define AON_GPADC_CHOP_MODE_UMSK     (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS))
+#define AON_GPADC_BIAS_SEL           AON_GPADC_BIAS_SEL
+#define AON_GPADC_BIAS_SEL_POS       (17U)
+#define AON_GPADC_BIAS_SEL_LEN       (1U)
+#define AON_GPADC_BIAS_SEL_MSK       (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)
+#define AON_GPADC_BIAS_SEL_UMSK      (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS))
+#define AON_GPADC_TEST_EN            AON_GPADC_TEST_EN
+#define AON_GPADC_TEST_EN_POS        (18U)
+#define AON_GPADC_TEST_EN_LEN        (1U)
+#define AON_GPADC_TEST_EN_MSK        (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)
+#define AON_GPADC_TEST_EN_UMSK       (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS))
+#define AON_GPADC_TEST_SEL           AON_GPADC_TEST_SEL
+#define AON_GPADC_TEST_SEL_POS       (19U)
+#define AON_GPADC_TEST_SEL_LEN       (3U)
+#define AON_GPADC_TEST_SEL_MSK       (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)
+#define AON_GPADC_TEST_SEL_UMSK      (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS))
+#define AON_GPADC_PGA2_GAIN          AON_GPADC_PGA2_GAIN
+#define AON_GPADC_PGA2_GAIN_POS      (22U)
+#define AON_GPADC_PGA2_GAIN_LEN      (3U)
+#define AON_GPADC_PGA2_GAIN_MSK      (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)
+#define AON_GPADC_PGA2_GAIN_UMSK     (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS))
+#define AON_GPADC_PGA1_GAIN          AON_GPADC_PGA1_GAIN
+#define AON_GPADC_PGA1_GAIN_POS      (25U)
+#define AON_GPADC_PGA1_GAIN_LEN      (3U)
+#define AON_GPADC_PGA1_GAIN_MSK      (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)
+#define AON_GPADC_PGA1_GAIN_UMSK     (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS))
+#define AON_GPADC_DLY_SEL            AON_GPADC_DLY_SEL
+#define AON_GPADC_DLY_SEL_POS        (28U)
+#define AON_GPADC_DLY_SEL_LEN        (3U)
+#define AON_GPADC_DLY_SEL_MSK        (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)
+#define AON_GPADC_DLY_SEL_UMSK       (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS))
+#define AON_GPADC_TSVBE_LOW          AON_GPADC_TSVBE_LOW
+#define AON_GPADC_TSVBE_LOW_POS      (31U)
+#define AON_GPADC_TSVBE_LOW_LEN      (1U)
+#define AON_GPADC_TSVBE_LOW_MSK      (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)
+#define AON_GPADC_TSVBE_LOW_UMSK     (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS))
+
+/* 0x918 : adc converation sequence 1 */
+#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918)
+#define AON_GPADC_SCAN_POS_0          AON_GPADC_SCAN_POS_0
+#define AON_GPADC_SCAN_POS_0_POS      (0U)
+#define AON_GPADC_SCAN_POS_0_LEN      (5U)
+#define AON_GPADC_SCAN_POS_0_MSK      (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)
+#define AON_GPADC_SCAN_POS_0_UMSK     (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS))
+#define AON_GPADC_SCAN_POS_1          AON_GPADC_SCAN_POS_1
+#define AON_GPADC_SCAN_POS_1_POS      (5U)
+#define AON_GPADC_SCAN_POS_1_LEN      (5U)
+#define AON_GPADC_SCAN_POS_1_MSK      (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)
+#define AON_GPADC_SCAN_POS_1_UMSK     (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS))
+#define AON_GPADC_SCAN_POS_2          AON_GPADC_SCAN_POS_2
+#define AON_GPADC_SCAN_POS_2_POS      (10U)
+#define AON_GPADC_SCAN_POS_2_LEN      (5U)
+#define AON_GPADC_SCAN_POS_2_MSK      (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)
+#define AON_GPADC_SCAN_POS_2_UMSK     (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS))
+#define AON_GPADC_SCAN_POS_3          AON_GPADC_SCAN_POS_3
+#define AON_GPADC_SCAN_POS_3_POS      (15U)
+#define AON_GPADC_SCAN_POS_3_LEN      (5U)
+#define AON_GPADC_SCAN_POS_3_MSK      (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)
+#define AON_GPADC_SCAN_POS_3_UMSK     (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS))
+#define AON_GPADC_SCAN_POS_4          AON_GPADC_SCAN_POS_4
+#define AON_GPADC_SCAN_POS_4_POS      (20U)
+#define AON_GPADC_SCAN_POS_4_LEN      (5U)
+#define AON_GPADC_SCAN_POS_4_MSK      (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)
+#define AON_GPADC_SCAN_POS_4_UMSK     (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS))
+#define AON_GPADC_SCAN_POS_5          AON_GPADC_SCAN_POS_5
+#define AON_GPADC_SCAN_POS_5_POS      (25U)
+#define AON_GPADC_SCAN_POS_5_LEN      (5U)
+#define AON_GPADC_SCAN_POS_5_MSK      (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)
+#define AON_GPADC_SCAN_POS_5_UMSK     (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS))
+
+/* 0x91C : adc converation sequence 2 */
+#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C)
+#define AON_GPADC_SCAN_POS_6          AON_GPADC_SCAN_POS_6
+#define AON_GPADC_SCAN_POS_6_POS      (0U)
+#define AON_GPADC_SCAN_POS_6_LEN      (5U)
+#define AON_GPADC_SCAN_POS_6_MSK      (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)
+#define AON_GPADC_SCAN_POS_6_UMSK     (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS))
+#define AON_GPADC_SCAN_POS_7          AON_GPADC_SCAN_POS_7
+#define AON_GPADC_SCAN_POS_7_POS      (5U)
+#define AON_GPADC_SCAN_POS_7_LEN      (5U)
+#define AON_GPADC_SCAN_POS_7_MSK      (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)
+#define AON_GPADC_SCAN_POS_7_UMSK     (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS))
+#define AON_GPADC_SCAN_POS_8          AON_GPADC_SCAN_POS_8
+#define AON_GPADC_SCAN_POS_8_POS      (10U)
+#define AON_GPADC_SCAN_POS_8_LEN      (5U)
+#define AON_GPADC_SCAN_POS_8_MSK      (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)
+#define AON_GPADC_SCAN_POS_8_UMSK     (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS))
+#define AON_GPADC_SCAN_POS_9          AON_GPADC_SCAN_POS_9
+#define AON_GPADC_SCAN_POS_9_POS      (15U)
+#define AON_GPADC_SCAN_POS_9_LEN      (5U)
+#define AON_GPADC_SCAN_POS_9_MSK      (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)
+#define AON_GPADC_SCAN_POS_9_UMSK     (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS))
+#define AON_GPADC_SCAN_POS_10         AON_GPADC_SCAN_POS_10
+#define AON_GPADC_SCAN_POS_10_POS     (20U)
+#define AON_GPADC_SCAN_POS_10_LEN     (5U)
+#define AON_GPADC_SCAN_POS_10_MSK     (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)
+#define AON_GPADC_SCAN_POS_10_UMSK    (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS))
+#define AON_GPADC_SCAN_POS_11         AON_GPADC_SCAN_POS_11
+#define AON_GPADC_SCAN_POS_11_POS     (25U)
+#define AON_GPADC_SCAN_POS_11_LEN     (5U)
+#define AON_GPADC_SCAN_POS_11_MSK     (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)
+#define AON_GPADC_SCAN_POS_11_UMSK    (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS))
+
+/* 0x920 : adc converation sequence 3 */
+#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920)
+#define AON_GPADC_SCAN_NEG_0          AON_GPADC_SCAN_NEG_0
+#define AON_GPADC_SCAN_NEG_0_POS      (0U)
+#define AON_GPADC_SCAN_NEG_0_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_0_MSK      (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)
+#define AON_GPADC_SCAN_NEG_0_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS))
+#define AON_GPADC_SCAN_NEG_1          AON_GPADC_SCAN_NEG_1
+#define AON_GPADC_SCAN_NEG_1_POS      (5U)
+#define AON_GPADC_SCAN_NEG_1_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_1_MSK      (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)
+#define AON_GPADC_SCAN_NEG_1_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS))
+#define AON_GPADC_SCAN_NEG_2          AON_GPADC_SCAN_NEG_2
+#define AON_GPADC_SCAN_NEG_2_POS      (10U)
+#define AON_GPADC_SCAN_NEG_2_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_2_MSK      (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)
+#define AON_GPADC_SCAN_NEG_2_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS))
+#define AON_GPADC_SCAN_NEG_3          AON_GPADC_SCAN_NEG_3
+#define AON_GPADC_SCAN_NEG_3_POS      (15U)
+#define AON_GPADC_SCAN_NEG_3_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_3_MSK      (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)
+#define AON_GPADC_SCAN_NEG_3_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS))
+#define AON_GPADC_SCAN_NEG_4          AON_GPADC_SCAN_NEG_4
+#define AON_GPADC_SCAN_NEG_4_POS      (20U)
+#define AON_GPADC_SCAN_NEG_4_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_4_MSK      (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)
+#define AON_GPADC_SCAN_NEG_4_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS))
+#define AON_GPADC_SCAN_NEG_5          AON_GPADC_SCAN_NEG_5
+#define AON_GPADC_SCAN_NEG_5_POS      (25U)
+#define AON_GPADC_SCAN_NEG_5_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_5_MSK      (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)
+#define AON_GPADC_SCAN_NEG_5_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS))
+
+/* 0x924 : adc converation sequence 4 */
+#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924)
+#define AON_GPADC_SCAN_NEG_6          AON_GPADC_SCAN_NEG_6
+#define AON_GPADC_SCAN_NEG_6_POS      (0U)
+#define AON_GPADC_SCAN_NEG_6_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_6_MSK      (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)
+#define AON_GPADC_SCAN_NEG_6_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS))
+#define AON_GPADC_SCAN_NEG_7          AON_GPADC_SCAN_NEG_7
+#define AON_GPADC_SCAN_NEG_7_POS      (5U)
+#define AON_GPADC_SCAN_NEG_7_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_7_MSK      (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)
+#define AON_GPADC_SCAN_NEG_7_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS))
+#define AON_GPADC_SCAN_NEG_8          AON_GPADC_SCAN_NEG_8
+#define AON_GPADC_SCAN_NEG_8_POS      (10U)
+#define AON_GPADC_SCAN_NEG_8_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_8_MSK      (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)
+#define AON_GPADC_SCAN_NEG_8_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS))
+#define AON_GPADC_SCAN_NEG_9          AON_GPADC_SCAN_NEG_9
+#define AON_GPADC_SCAN_NEG_9_POS      (15U)
+#define AON_GPADC_SCAN_NEG_9_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_9_MSK      (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)
+#define AON_GPADC_SCAN_NEG_9_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS))
+#define AON_GPADC_SCAN_NEG_10         AON_GPADC_SCAN_NEG_10
+#define AON_GPADC_SCAN_NEG_10_POS     (20U)
+#define AON_GPADC_SCAN_NEG_10_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_10_MSK     (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)
+#define AON_GPADC_SCAN_NEG_10_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS))
+#define AON_GPADC_SCAN_NEG_11         AON_GPADC_SCAN_NEG_11
+#define AON_GPADC_SCAN_NEG_11_POS     (25U)
+#define AON_GPADC_SCAN_NEG_11_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_11_MSK     (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)
+#define AON_GPADC_SCAN_NEG_11_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS))
+
+/* 0x928 : gpadc_reg_status */
+#define AON_GPADC_REG_STATUS_OFFSET (0x928)
+#define AON_GPADC_DATA_RDY          AON_GPADC_DATA_RDY
+#define AON_GPADC_DATA_RDY_POS      (0U)
+#define AON_GPADC_DATA_RDY_LEN      (1U)
+#define AON_GPADC_DATA_RDY_MSK      (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)
+#define AON_GPADC_DATA_RDY_UMSK     (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS))
+#define AON_GPADC_RESERVED          AON_GPADC_RESERVED
+#define AON_GPADC_RESERVED_POS      (16U)
+#define AON_GPADC_RESERVED_LEN      (16U)
+#define AON_GPADC_RESERVED_MSK      (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)
+#define AON_GPADC_RESERVED_UMSK     (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS))
+
+/* 0x92C : gpadc_reg_isr */
+#define AON_GPADC_REG_ISR_OFFSET      (0x92C)
+#define AON_GPADC_NEG_SATUR           AON_GPADC_NEG_SATUR
+#define AON_GPADC_NEG_SATUR_POS       (0U)
+#define AON_GPADC_NEG_SATUR_LEN       (1U)
+#define AON_GPADC_NEG_SATUR_MSK       (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)
+#define AON_GPADC_NEG_SATUR_UMSK      (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS))
+#define AON_GPADC_POS_SATUR           AON_GPADC_POS_SATUR
+#define AON_GPADC_POS_SATUR_POS       (1U)
+#define AON_GPADC_POS_SATUR_LEN       (1U)
+#define AON_GPADC_POS_SATUR_MSK       (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)
+#define AON_GPADC_POS_SATUR_UMSK      (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS))
+#define AON_GPADC_NEG_SATUR_CLR       AON_GPADC_NEG_SATUR_CLR
+#define AON_GPADC_NEG_SATUR_CLR_POS   (4U)
+#define AON_GPADC_NEG_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_NEG_SATUR_CLR_MSK   (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)
+#define AON_GPADC_NEG_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS))
+#define AON_GPADC_POS_SATUR_CLR       AON_GPADC_POS_SATUR_CLR
+#define AON_GPADC_POS_SATUR_CLR_POS   (5U)
+#define AON_GPADC_POS_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_POS_SATUR_CLR_MSK   (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)
+#define AON_GPADC_POS_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS))
+#define AON_GPADC_NEG_SATUR_MASK      AON_GPADC_NEG_SATUR_MASK
+#define AON_GPADC_NEG_SATUR_MASK_POS  (8U)
+#define AON_GPADC_NEG_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_NEG_SATUR_MASK_MSK  (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)
+#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS))
+#define AON_GPADC_POS_SATUR_MASK      AON_GPADC_POS_SATUR_MASK
+#define AON_GPADC_POS_SATUR_MASK_POS  (9U)
+#define AON_GPADC_POS_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_POS_SATUR_MASK_MSK  (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)
+#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS))
+
+/* 0x930 : gpadc_reg_result */
+#define AON_GPADC_REG_RESULT_OFFSET (0x930)
+#define AON_GPADC_DATA_OUT          AON_GPADC_DATA_OUT
+#define AON_GPADC_DATA_OUT_POS      (0U)
+#define AON_GPADC_DATA_OUT_LEN      (26U)
+#define AON_GPADC_DATA_OUT_MSK      (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)
+#define AON_GPADC_DATA_OUT_UMSK     (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS))
+
+/* 0x934 : gpadc_reg_raw_result */
+#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934)
+#define AON_GPADC_RAW_DATA              AON_GPADC_RAW_DATA
+#define AON_GPADC_RAW_DATA_POS          (0U)
+#define AON_GPADC_RAW_DATA_LEN          (12U)
+#define AON_GPADC_RAW_DATA_MSK          (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)
+#define AON_GPADC_RAW_DATA_UMSK         (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS))
+
+/* 0x938 : gpadc_reg_define */
+#define AON_GPADC_REG_DEFINE_OFFSET (0x938)
+#define AON_GPADC_OS_CAL_DATA       AON_GPADC_OS_CAL_DATA
+#define AON_GPADC_OS_CAL_DATA_POS   (0U)
+#define AON_GPADC_OS_CAL_DATA_LEN   (16U)
+#define AON_GPADC_OS_CAL_DATA_MSK   (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)
+#define AON_GPADC_OS_CAL_DATA_UMSK  (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS))
+
+/* 0x93C : hbncore_resv0 */
+#define AON_HBNCORE_RESV0_OFFSET    (0x93C)
+#define AON_HBNCORE_RESV0_DATA      AON_HBNCORE_RESV0_DATA
+#define AON_HBNCORE_RESV0_DATA_POS  (0U)
+#define AON_HBNCORE_RESV0_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV0_DATA_MSK  (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)
+#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS))
+
+/* 0x940 : hbncore_resv1 */
+#define AON_HBNCORE_RESV1_OFFSET    (0x940)
+#define AON_HBNCORE_RESV1_DATA      AON_HBNCORE_RESV1_DATA
+#define AON_HBNCORE_RESV1_DATA_POS  (0U)
+#define AON_HBNCORE_RESV1_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV1_DATA_MSK  (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)
+#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS))
+
+struct aon_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[2048];
+
+    /* 0x800 : aon */
+    union {
+        struct
+        {
+            uint32_t aon_resv              : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t pu_aon_dc_tbuf        : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_19        : 7; /* [19:13],       rsvd,        0x0 */
+            uint32_t ldo11_rt_pulldown     : 1; /* [   20],        r/w,        0x0 */
+            uint32_t ldo11_rt_pulldown_sel : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sw_pu_ldo11_rt        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23_31        : 9; /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon;
+
+    /* 0x804 : aon_common */
+    union {
+        struct
+        {
+            uint32_t tmux_aon         : 3;  /* [ 2: 0],        r/w,        0x0 */
+            uint32_t reserved_3       : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t ten_aon          : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t dten_xtal32k     : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t ten_xtal32k      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7       : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t ten_vddcore_aon  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t ten_ldo11soc_aon : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t ten_dcdc18_0_aon : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ten_dcdc18_1_aon : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t ten_bg_sys_aon   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15   : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t ten_ldo15rf_aon  : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t ten_xtal_aon     : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t dten_xtal_aon    : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t ten_mbg_aon      : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t ten_cip_misc_aon : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31   : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_common;
+
+    /* 0x808 : aon_misc */
+    union {
+        struct
+        {
+            uint32_t sw_soc_en_aon : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t sw_wb_en_aon  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_misc;
+
+    /* 0x80c  reserved */
+    uint8_t RESERVED0x80c[4];
+
+    /* 0x810 : bg_sys_top */
+    union {
+        struct
+        {
+            uint32_t pmip_resv             : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t pu_bg_sys_aon         : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_11         : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t bg_sys_start_ctrl_aon : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t reserved_13_31        : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bg_sys_top;
+
+    /* 0x814 : dcdc18_top_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0                : 1; /* [    0],       rsvd,        0x0 */
+            uint32_t dcdc18_vout_sel_aon       : 5; /* [ 5: 1],        r/w,       0x1b */
+            uint32_t reserved_6_7              : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t dcdc18_vpfm_aon           : 4; /* [11: 8],        r/w,        0x7 */
+            uint32_t dcdc18_osc_2m_mode_aon    : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15            : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc18_osc_freq_trim_aon  : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc18_slope_curr_sel_aon : 5; /* [24:20],        r/w,        0x5 */
+            uint32_t dcdc18_stop_osc_aon       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t dcdc18_slow_osc_aon       : 1; /* [   26],        r/w,        0x0 */
+            uint32_t dcdc18_osc_inhibit_t2_aon : 1; /* [   27],        r/w,        0x1 */
+            uint32_t dcdc18_sstart_time_aon    : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t reserved_30               : 1; /* [   30],       rsvd,        0x0 */
+            uint32_t dcdc18_rdy_aon            : 1; /* [   31],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } dcdc18_top_0;
+
+    /* 0x818 : dcdc18_top_1 */
+    union {
+        struct
+        {
+            uint32_t dcdc18_force_cs_zvs_aon  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t dcdc18_cs_delay_aon      : 3; /* [ 3: 1],        r/w,        0x4 */
+            uint32_t dcdc18_zvs_td_opt_aon    : 3; /* [ 6: 4],        r/w,        0x4 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t dcdc18_nonoverlap_td_aon : 5; /* [12: 8],        r/w,        0x0 */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc18_rc_sel_aon        : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc18_chf_sel_aon       : 4; /* [23:20],        r/w,        0x1 */
+            uint32_t dcdc18_cfb_sel_aon       : 4; /* [27:24],        r/w,        0x8 */
+            uint32_t dcdc18_en_antiring_aon   : 1; /* [   28],        r/w,        0x1 */
+            uint32_t dcdc18_pulldown_aon      : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31           : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dcdc18_top_1;
+
+    /* 0x81C : ldo11soc_and_dctest */
+    union {
+        struct
+        {
+            uint32_t pu_ldo11soc_aon           : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3              : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t ldo11soc_sstart_sel_aon   : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_7              : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t ldo11soc_sstart_delay_aon : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_aon     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_sel_aon : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t ldo11soc_vth_sel_aon      : 2;  /* [13:12],        r/w,        0x1 */
+            uint32_t reserved_14_23            : 10; /* [23:14],       rsvd,        0x0 */
+            uint32_t ldo11soc_cc_aon           : 2;  /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27            : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t ldo11soc_rdy_aon          : 1;  /* [   28],          r,        0x1 */
+            uint32_t ldo11soc_power_good_aon   : 1;  /* [   29],          r,        0x1 */
+            uint32_t pu_vddcore_misc_aon       : 1;  /* [   30],        r/w,        0x1 */
+            uint32_t pmip_dc_tp_out_en_aon     : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ldo11soc_and_dctest;
+
+    /* 0x820 : psw_irrcv */
+    union {
+        struct
+        {
+            uint32_t pu_ir_psw_aon : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psw_irrcv;
+
+    /* 0x824  reserved */
+    uint8_t RESERVED0x824[92];
+
+    /* 0x880 : rf_top_aon */
+    union {
+        struct
+        {
+            uint32_t pu_mbg_aon               : 1; /* [    0],        r/w,        0x1 */
+            uint32_t pu_ldo15rf_aon           : 1; /* [    1],        r/w,        0x1 */
+            uint32_t pu_sfreg_aon             : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3               : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t pu_xtal_buf_aon          : 1; /* [    4],        r/w,        0x1 */
+            uint32_t pu_xtal_aon              : 1; /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7             : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t ldo15rf_sstart_sel_aon   : 1; /* [    8],        r/w,        0x1 */
+            uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t ldo15rf_pulldown_aon     : 1; /* [   12],        r/w,        0x0 */
+            uint32_t ldo15rf_pulldown_sel_aon : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t ldo15rf_vout_sel_aon     : 3; /* [18:16],        r/w,        0x2 */
+            uint32_t reserved_19_23           : 5; /* [23:19],       rsvd,        0x0 */
+            uint32_t ldo15rf_cc_aon           : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27           : 2; /* [27:26],       rsvd,        0x0 */
+            uint32_t ldo15rf_bypass_aon       : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29_31           : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rf_top_aon;
+
+    /* 0x884 : xtal_cfg */
+    union {
+        struct
+        {
+            uint32_t xtal_bk_aon            : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t xtal_capcode_extra_aon : 1; /* [    2],        r/w,        0x0 */
+            uint32_t xtal_ext_sel_aon       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t xtal_buf_en_aon        : 4; /* [ 7: 4],        r/w,        0xf */
+            uint32_t xtal_buf_hp_aon        : 4; /* [11: 8],        r/w,        0x0 */
+            uint32_t xtal_fast_startup_aon  : 1; /* [   12],        r/w,        0x1 */
+            uint32_t xtal_sleep_aon         : 1; /* [   13],        r/w,        0x1 */
+            uint32_t xtal_amp_ctrl_aon      : 2; /* [15:14],        r/w,        0x3 */
+            uint32_t xtal_capcode_out_aon   : 6; /* [21:16],        r/w,       0x10 */
+            uint32_t xtal_capcode_in_aon    : 6; /* [27:22],        r/w,       0x10 */
+            uint32_t xtal_gm_boost_aon      : 2; /* [29:28],        r/w,        0x3 */
+            uint32_t xtal_rdy_sel_aon       : 2; /* [31:30],        r/w,        0x2 */
+        } BF;
+        uint32_t WORD;
+    } xtal_cfg;
+
+    /* 0x888 : tsen */
+    union {
+        struct
+        {
+            uint32_t tsen_refcode_corner  : 12; /* [11: 0],        r/w,      0x8ff */
+            uint32_t reserved_12_15       : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t tsen_refcode_rfcal   : 12; /* [27:16],        r/w,      0x8ff */
+            uint32_t xtal_rdy             : 1;  /* [   28],          r,        0x1 */
+            uint32_t xtal_inn_cfg_en_aon  : 1;  /* [   29],        r/w,        0x1 */
+            uint32_t xtal_rdy_int_sel_aon : 2;  /* [31:30],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } tsen;
+
+    /* 0x88c  reserved */
+    uint8_t RESERVED0x88c[116];
+
+    /* 0x900 : acomp0_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp0_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp0_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp0_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp0_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp0_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp0_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp0_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp0_ctrl;
+
+    /* 0x904 : acomp1_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp1_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp1_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp1_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp1_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp1_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp1_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp1_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp1_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp1_ctrl;
+
+    /* 0x908 : acomp_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp1_rstn_ana : 1; /* [    0],        r/w,        0x1 */
+            uint32_t acomp0_rstn_ana : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_7    : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t acomp1_test_en  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t acomp0_test_en  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t acomp1_test_sel : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_test_sel : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t reserved_14_16  : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t acomp1_out_raw  : 1; /* [   17],          r,        0x0 */
+            uint32_t reserved_18     : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t acomp0_out_raw  : 1; /* [   19],          r,        0x0 */
+            uint32_t reserved_20_23  : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t acomp_reserved  : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp_ctrl;
+
+    /* 0x90C : gpadc_reg_cmd */
+    union {
+        struct
+        {
+            uint32_t gpadc_global_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_conv_start       : 1; /* [    1],        r/w,        0x0 */
+            uint32_t gpadc_soft_rst         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_neg_sel          : 5; /* [ 7: 3],        r/w,        0xf */
+            uint32_t gpadc_pos_sel          : 5; /* [12: 8],        r/w,        0xf */
+            uint32_t gpadc_neg_gnd          : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_micbias_en       : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_micpga_en        : 1; /* [   15],        r/w,        0x0 */
+            uint32_t gpadc_byp_micboost     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17            : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t gpadc_dwa_en           : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_mic2_diff        : 1; /* [   19],        r/w,        0x0 */
+            uint32_t gpadc_mic1_diff        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpadc_mic_pga2_gain    : 2; /* [22:21],        r/w,        0x0 */
+            uint32_t gpadc_micboost_32db_en : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_26         : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t gpadc_chip_sen_pu      : 1; /* [   27],        r/w,        0x0 */
+            uint32_t gpadc_sen_sel          : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t gpadc_sen_test_en      : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reserved_31            : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_cmd;
+
+    /* 0x910 : gpadc_reg_config1 */
+    union {
+        struct
+        {
+            uint32_t gpadc_cal_os_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_cont_conv_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t gpadc_res_sel       : 3;  /* [ 4: 2],        r/w,        0x0 */
+            uint32_t reserved_5_16       : 12; /* [16: 5],       rsvd,        0x0 */
+            uint32_t gpadc_clk_ana_inv   : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_clk_div_ratio : 3;  /* [20:18],        r/w,        0x3 */
+            uint32_t gpadc_scan_length   : 4;  /* [24:21],        r/w,        0x0 */
+            uint32_t gpadc_scan_en       : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t gpadc_dither_en     : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t gpadc_v11_sel       : 2;  /* [28:27],        r/w,        0x0 */
+            uint32_t gpadc_v18_sel       : 2;  /* [30:29],        r/w,        0x0 */
+            uint32_t reserved_31         : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config1;
+
+    /* 0x914 : gpadc_reg_config2 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1      : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t gpadc_diff_mode   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_vref_sel    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t gpadc_vbat_en     : 1; /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_tsext_sel   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t gpadc_ts_en       : 1; /* [    6],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcm     : 2; /* [ 8: 7],        r/w,        0x2 */
+            uint32_t gpadc_pga_os_cal  : 4; /* [12: 9],        r/w,        0x8 */
+            uint32_t gpadc_pga_en      : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcmi_en : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_chop_mode   : 2; /* [16:15],        r/w,        0x3 */
+            uint32_t gpadc_bias_sel    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_test_en     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_test_sel    : 3; /* [21:19],        r/w,        0x0 */
+            uint32_t gpadc_pga2_gain   : 3; /* [24:22],        r/w,        0x0 */
+            uint32_t gpadc_pga1_gain   : 3; /* [27:25],        r/w,        0x0 */
+            uint32_t gpadc_dly_sel     : 3; /* [30:28],        r/w,        0x0 */
+            uint32_t gpadc_tsvbe_low   : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config2;
+
+    /* 0x918 : adc converation sequence 1 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos1;
+
+    /* 0x91C : adc converation sequence 2 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_pos_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos2;
+
+    /* 0x920 : adc converation sequence 3 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg1;
+
+    /* 0x924 : adc converation sequence 4 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_neg_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg2;
+
+    /* 0x928 : gpadc_reg_status */
+    union {
+        struct
+        {
+            uint32_t gpadc_data_rdy : 1;  /* [    0],          r,        0x0 */
+            uint32_t reserved_1_15  : 15; /* [15: 1],       rsvd,        0x0 */
+            uint32_t gpadc_reserved : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_status;
+
+    /* 0x92C : gpadc_reg_isr */
+    union {
+        struct
+        {
+            uint32_t gpadc_neg_satur      : 1;  /* [    0],          r,        0x0 */
+            uint32_t gpadc_pos_satur      : 1;  /* [    1],          r,        0x0 */
+            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_clr  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_clr  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_mask : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_mask : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31       : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_isr;
+
+    /* 0x930 : gpadc_reg_result */
+    union {
+        struct
+        {
+            uint32_t gpadc_data_out : 26; /* [25: 0],          r,  0x1ef0000 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_result;
+
+    /* 0x934 : gpadc_reg_raw_result */
+    union {
+        struct
+        {
+            uint32_t gpadc_raw_data : 12; /* [11: 0],          r,        0x0 */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_raw_result;
+
+    /* 0x938 : gpadc_reg_define */
+    union {
+        struct
+        {
+            uint32_t gpadc_os_cal_data : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31    : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_define;
+
+    /* 0x93C : hbncore_resv0 */
+    union {
+        struct
+        {
+            uint32_t hbncore_resv0_data : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv0;
+
+    /* 0x940 : hbncore_resv1 */
+    union {
+        struct
+        {
+            uint32_t hbncore_resv1_data : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv1;
+};
+
+typedef volatile struct aon_reg aon_reg_t;
+
+#endif /* __AON_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/bl602.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/bl602.h
new file mode 100755
index 0000000000..db35c11858
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/bl602.h
@@ -0,0 +1,250 @@
+#ifndef __BL602_H__
+#define __BL602_H__
+
+/** @addtogroup Configuration_section_for_RISCV
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Processor and Core Peripherals
+   */
+#define SystemCoreClockSet(val) BL_WR_WORD(0x4000F108, val)
+#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108)
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+#ifdef ARCH_ARM
+#define IRQ_NUM_BASE 0
+#endif
+
+#ifdef ARCH_RISCV
+#define IRQ_NUM_BASE 16
+#endif
+/**
+ * @brief BL602 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum {
+#ifdef ARCH_ARM
+    /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+    NonMaskableInt_IRQn = -14,   /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+    HardFault_IRQn = -13,        /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+    BusFault_IRQn = -11,         /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+    UsageFault_IRQn = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+    SVCall_IRQn = -5,            /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+    DebugMonitor_IRQn = -4,      /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+    PendSV_IRQn = -2,            /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+    SysTick_IRQn = -1,           /*!< 15 Cortex-M4 System Tick Interrupt                                */
+#endif
+#ifdef ARCH_RISCV
+    MSOFT_IRQn = 3,           /*!< 3 RISCV machine software Interrupt                                */
+    MTIME_IRQn = 7,           /*!< 7 RISCV machine time Interrupt                                    */
+    MEXT_IRQn = 11,           /*!< 11 RISCV external  Interrupt                                      */
+    CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending  Interrupt                         */
+#endif
+    /******  BL602 specific Interrupt Numbers **********************************************************************/
+    BMX_ERR_IRQn = IRQ_NUM_BASE + 0,          /*!< BMX Error Interrupt                                               */
+    BMX_TO_IRQn = IRQ_NUM_BASE + 1,           /*!< BMX Timeout Interrupt                                             */
+    L1C_BMX_ERR_IRQn = IRQ_NUM_BASE + 2,      /*!< L1C BMX Error Interrupt                                           */
+    L1C_BMX_TO_IRQn = IRQ_NUM_BASE + 3,       /*!< L1C BMX Timeout Interrupt                                         */
+    SEC_BMX_ERR_IRQn = IRQ_NUM_BASE + 4,      /*!< SEC BMX Error Interrupt                                           */
+    RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5,      /*!< RF_TOP_INT0 Interrupt                                             */
+    RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6,      /*!< RF_TOP_INT1 Interrupt                                             */
+    SDIO_IRQn = IRQ_NUM_BASE + 7,             /*!< SDIO Interrupt                                                    */
+    DMA_BMX_ERR_IRQn = IRQ_NUM_BASE + 8,      /*!< DMA BMX Error Interrupt                                           */
+    SEC_GMAC_IRQn = IRQ_NUM_BASE + 9,         /*!< SEC_ENG_GMAC_INT Interrupt                                        */
+    SEC_CDET_IRQn = IRQ_NUM_BASE + 10,        /*!< SEC_ENG_CDET_INT Interrupt                                        */
+    SEC_PKA_IRQn = IRQ_NUM_BASE + 11,         /*!< SEC_ENG_PKA_INT  Interrupt                                        */
+    SEC_TRNG_IRQn = IRQ_NUM_BASE + 12,        /*!< SEC_ENG_TRNG_INT Interrupt                                        */
+    SEC_AES_IRQn = IRQ_NUM_BASE + 13,         /*!< SEC_ENG_AES_INT  Interrupt                                        */
+    SEC_SHA_IRQn = IRQ_NUM_BASE + 14,         /*!< SEC_ENG_SHA_INT  Interrupt                                        */
+    DMA_ALL_IRQn = IRQ_NUM_BASE + 15,         /*!< DMA ALL Interrupt                                                 */
+    RESERVED0 = IRQ_NUM_BASE + 16,            /*!< RESERVED Interrupt                                                */
+    RESERVED1 = IRQ_NUM_BASE + 17,            /*!< RESERVED Interrupt                                                */
+    RESERVED2 = IRQ_NUM_BASE + 18,            /*!< RESERVED Interrupt                                                */
+    IRTX_IRQn = IRQ_NUM_BASE + 19,            /*!< IR TX Interrupt                                                   */
+    IRRX_IRQn = IRQ_NUM_BASE + 20,            /*!< IR RX Interrupt                                                   */
+    RESERVED3 = IRQ_NUM_BASE + 21,            /*!< RESERVED  Interrupt                                               */
+    RESERVED4 = IRQ_NUM_BASE + 22,            /*!< RESERVED  Interrupt                                               */
+    SF_CTRL_IRQn = IRQ_NUM_BASE + 23,         /*!< SF_CTRL   Interrupt                                               */
+    RESERVED5 = IRQ_NUM_BASE + 24,            /*!< RESERVED  Interrupt                                               */
+    GPADC_DMA_IRQn = IRQ_NUM_BASE + 25,       /*!< GPADC_DMA Interrupt                                               */
+    EFUSE_IRQn = IRQ_NUM_BASE + 26,           /*!< Efuse Interrupt                                                   */
+    SPI_IRQn = IRQ_NUM_BASE + 27,             /*!< SPI   Interrupt                                                   */
+    RESERVED6 = IRQ_NUM_BASE + 28,            /*!< RESERVED Interrupt                                                */
+    UART0_IRQn = IRQ_NUM_BASE + 29,           /*!< UART  Interrupt                                                   */
+    UART1_IRQn = IRQ_NUM_BASE + 30,           /*!< UART1 Interrupt                                                   */
+    RESERVED7 = IRQ_NUM_BASE + 31,            /*!< RESERVED Interrupt                                                */
+    I2C_IRQn = IRQ_NUM_BASE + 32,             /*!< I2C   Interrupt                                                   */
+    RESERVED8 = IRQ_NUM_BASE + 33,            /*!< RESERVED Interrupt                                                */
+    PWM_IRQn = IRQ_NUM_BASE + 34,             /*!< PWM   Interrupt                                                   */
+    RESERVED9 = IRQ_NUM_BASE + 35,            /*!< RESERVED Interrupt                                                */
+    TIMER_CH0_IRQn = IRQ_NUM_BASE + 36,       /*!< Timer Channel 0 Interrupt                                         */
+    TIMER_CH1_IRQn = IRQ_NUM_BASE + 37,       /*!< Timer Channel 1 Interrupt                                         */
+    TIMER_WDT_IRQn = IRQ_NUM_BASE + 38,       /*!< Timer Watch Dog Interrupt                                         */
+    RESERVED10 = IRQ_NUM_BASE + 39,           /*!< RESERVED Interrupt                                                */
+    RESERVED11 = IRQ_NUM_BASE + 40,           /*!< RESERVED Interrupt                                                */
+    RESERVED12 = IRQ_NUM_BASE + 41,           /*!< RESERVED Interrupt                                                */
+    RESERVED13 = IRQ_NUM_BASE + 42,           /*!< RESERVED Interrupt                                                */
+    RESERVED14 = IRQ_NUM_BASE + 43,           /*!< RESERVED Interrupt                                                */
+    GPIO_INT0_IRQn = IRQ_NUM_BASE + 44,       /*!< RESERVED Interrupt                                                */
+    RESERVED16 = IRQ_NUM_BASE + 45,           /*!< RESERVED Interrupt                                                */
+    RESERVED17 = IRQ_NUM_BASE + 46,           /*!< RESERVED Interrupt                                                */
+    RESERVED18 = IRQ_NUM_BASE + 47,           /*!< RESERVED Interrupt                                                */
+    RESERVED19 = IRQ_NUM_BASE + 48,           /*!< RESERVED Interrupt                                                */
+    RESERVED20 = IRQ_NUM_BASE + 49,           /*!< RESERVED Interrupt                                                */
+    PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50,      /*!< PDS Wakeup Interrupt                                              */
+    HBN_OUT0_IRQn = IRQ_NUM_BASE + 51,        /*!< Hibernate out 0 Interrupt                                         */
+    HBN_OUT1_IRQn = IRQ_NUM_BASE + 52,        /*!< Hibernate out 1 Interrupt                                         */
+    BOR_IRQn = IRQ_NUM_BASE + 53,             /*!< BOR Interrupt                                                     */
+    WIFI_IRQn = IRQ_NUM_BASE + 54,            /*!< WIFI To CPU Interrupt                                             */
+    BZ_PHY_IRQn = IRQ_NUM_BASE + 55,          /*!< RESERVED Interrupt                                                */
+    BLE_IRQn = IRQ_NUM_BASE + 56,             /*!< RESERVED Interrupt                                                */
+    MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE + 57,  /*!< mac_int_tx_rx_timer Interrupt                                     */
+    MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE + 58,   /*!< mac_int_tx_rx_misc Interrupt                                      */
+    MAC_RX_TRG_IRQn = IRQ_NUM_BASE + 59,      /*!< mac_int_rx_trigger Interrupt                                      */
+    MAC_TX_TRG_IRQn = IRQ_NUM_BASE + 60,      /*!< mac_int_tx_trigger Interrupt                                      */
+    MAC_GEN_IRQn = IRQ_NUM_BASE + 61,         /*!< mac_int_gen Interrupt                                             */
+    MAC_PORT_TRG_IRQn = IRQ_NUM_BASE + 62,    /*!< mac_int_port_trigger Interrupt                                    */
+    WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE + 63, /*!< wifi IPC public Interrupt                                         */
+    IRQn_LAST,
+} IRQn_Type;
+
+/**
+ * @brief BL602 Memory Map Definitions
+ */
+#define BL602_FLASH_XIP_BASE        0x23000000
+#define BL602_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL602_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL602_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
+#define BL602_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL602_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)
+
+#define BL602_WRAM_BASE        0x42020000
+#define BL602_WRAM_END         (0x42020000 + 176 * 1024)
+#define BL602_WRAM_REMAP0_BASE 0x22020000
+#define BL602_WRAM_REMAP0_END  (0x22020000 + 176 * 1024)
+#define BL602_WRAM_REMAP1_BASE 0x32020000
+#define BL602_WRAM_REMAP1_END  (0x32020000 + 176 * 1024)
+#define BL602_WRAM_REMAP2_BASE 0x52020000
+#define BL602_WRAM_REMAP2_END  (0x52020000 + 176 * 1024)
+
+#define BL602_TCM_BASE        0x22008000
+#define BL602_TCM_END         (0x22008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP0_BASE 0x32008000
+#define BL602_TCM_REMAP0_END  (0x32008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP1_BASE 0x42008000
+#define BL602_TCM_REMAP1_END  (0x42008000 + (96 + 176) * 1024)
+#define BL602_TCM_REMAP2_BASE 0x52008000
+#define BL602_TCM_REMAP2_END  (0x52008000 + (96 + 176) * 1024)
+/*@} end of group Memory_Map_Section */
+
+/* BL602 peripherals base address */
+#define GLB_BASE         ((uint32_t)0x40000000)
+#define RF_BASE          ((uint32_t)0x40001000)
+#define GPIP_BASE        ((uint32_t)0x40002000) /*!< AUX module base address */
+#define SEC_DBG_BASE     ((uint32_t)0x40003000) /*!< Security Debug module base address */
+#define SEC_ENG_BASE     ((uint32_t)0x40004000) /*!< Security Engine module base address */
+#define TZC_SEC_BASE     ((uint32_t)0x40005000) /*!< Trustzone control security base address */
+#define TZC_NSEC_BASE    ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
+#define EF_DATA_BASE     ((uint32_t)0x40007000)
+#define EF_CTRL_BASE     ((uint32_t)0x40007000)
+#define CCI_BASE         ((uint32_t)0x40008000)
+#define L1C_BASE         ((uint32_t)0x40009000) /*!< L1 cache config base address */
+#define UART0_BASE       ((uint32_t)0x4000A000)
+#define UART1_BASE       ((uint32_t)0x4000A100)
+#define SPI_BASE         ((uint32_t)0x4000A200)
+#define I2C_BASE         ((uint32_t)0x4000A300)
+#define PWM_BASE         ((uint32_t)0x4000A400)
+#define TIMER_BASE       ((uint32_t)0x4000A500)
+#define IR_BASE          ((uint32_t)0x4000A600)
+#define SF_CTRL_BASE     ((uint32_t)0x4000B000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#define DMA_BASE         ((uint32_t)0x4000C000)
+#define SDU_BASE         ((uint32_t)0x4000D000)
+#define PDS_BASE         ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
+#define HBN_BASE         ((uint32_t)0x4000F000) /*!< Hibernate module base address */
+#define AON_BASE         ((uint32_t)0x4000F000) /*!< Always on module base address */
+#define HBN_RAM_BASE     ((uint32_t)0x40010000)
+
+typedef enum {
+    BL_AHB_SLAVE1_GLB = 0x00,
+    BL_AHB_SLAVE1_RF = 0x01,
+    BL_AHB_SLAVE1_GPIP_PHY_AGC = 0x02,
+    BL_AHB_SLAVE1_SEC_DBG = 0x03,
+    BL_AHB_SLAVE1_SEC = 0x04,
+    BL_AHB_SLAVE1_TZ1 = 0x05,
+    BL_AHB_SLAVE1_TZ2 = 0x06,
+    BL_AHB_SLAVE1_EFUSE = 0x07,
+    BL_AHB_SLAVE1_CCI = 0x08,
+    BL_AHB_SLAVE1_L1C = 0x09,
+    BL_AHB_SLAVE1_RSVD0A = 0x0A,
+    BL_AHB_SLAVE1_SFC = 0x0B,
+    BL_AHB_SLAVE1_DMA = 0x0C,
+    BL_AHB_SLAVE1_SDU = 0x0D,
+    BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E,
+    BL_AHB_SLAVE1_RSVD0F = 0x0F,
+    BL_AHB_SLAVE1_UART0 = 0x10,
+    BL_AHB_SLAVE1_UART1 = 0x11,
+    BL_AHB_SLAVE1_SPI = 0x12,
+    BL_AHB_SLAVE1_I2C = 0x13,
+    BL_AHB_SLAVE1_PWM = 0x14,
+    BL_AHB_SLAVE1_TMR = 0x15,
+    BL_AHB_SLAVE1_IRR = 0x16,
+    BL_AHB_SLAVE1_CKS = 0x17,
+    BL_AHB_SLAVE1_MAX = 0x18,
+} BL_AHB_Slave1_Type;
+
+typedef enum {
+    BL_AHB_SEC_ENG_AES0 = 0,
+    BL_AHB_SEC_ENG_AES1,
+    BL_AHB_SEC_ENG_SHA0,
+    BL_AHB_SEC_ENG_SHA1,
+} BL_AHB_Sec_Eng_Type;
+
+typedef enum {
+    BL_AHB_DMA0_CH0 = 0,
+    BL_AHB_DMA0_CH1,
+    BL_AHB_DMA0_CH2,
+    BL_AHB_DMA0_CH3,
+    BL_AHB_DMA0_CH4,
+} BL_AHB_DMA0_CHNL_Type;
+
+typedef enum {
+    BL_CORE_MASTER_IBUS_CPU = 0,
+    BL_CORE_MASTER_DBUS_CPU,
+    BL_CORE_MASTER_BUS_S2F,
+    BL_CORE_MASTER_MAX,
+} BL_Core_Master_Type;
+
+typedef enum {
+    BL_CORE_SLAVE0_DTCM_CPU = 0,
+    BL_CORE_SLAVE0_MAX,
+} BL_Core_Slave0_Type;
+
+typedef enum {
+    BL_CORE_SLAVE1_XIP_CPU = 0,
+    BL_CORE_SLAVE1_ITCM_CPU,
+    BL_CORE_SLAVE1_ROM,
+    BL_CORE_SLAVE1_MAX,
+} BL_Core_Slave1_Type;
+
+typedef enum {
+    BL_CORE_SLAVE2_F2S = 0,
+    BL_CORE_SLAVE2_MAX,
+} BL_Core_Slave2_Type;
+
+/**
+  * @}
+  */
+#include 
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_ctrl_reg.h
new file mode 100755
index 0000000000..772c9030c1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_ctrl_reg.h
@@ -0,0 +1,812 @@
+/**
+  ******************************************************************************
+  * @file    ef_ctrl_reg.h
+  * @version V1.2
+  * @date    2019-11-22
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __EF_CTRL_REG_H__
+#define __EF_CTRL_REG_H__
+
+#include "bl602.h"
+
+/* 0x800 : ef_if_ctrl_0 */
+#define EF_CTRL_EF_IF_CTRL_0_OFFSET           (0x800)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE      EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS  (0U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN  (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK  (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE         EF_CTRL_EF_IF_0_AUTOLOAD_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS     (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN     (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK     (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK    (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
+#define EF_CTRL_EF_IF_0_BUSY                  EF_CTRL_EF_IF_0_BUSY
+#define EF_CTRL_EF_IF_0_BUSY_POS              (2U)
+#define EF_CTRL_EF_IF_0_BUSY_LEN              (1U)
+#define EF_CTRL_EF_IF_0_BUSY_MSK              (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
+#define EF_CTRL_EF_IF_0_BUSY_UMSK             (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
+#define EF_CTRL_EF_IF_0_RW                    EF_CTRL_EF_IF_0_RW
+#define EF_CTRL_EF_IF_0_RW_POS                (3U)
+#define EF_CTRL_EF_IF_0_RW_LEN                (1U)
+#define EF_CTRL_EF_IF_0_RW_MSK                (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
+#define EF_CTRL_EF_IF_0_RW_UMSK               (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
+#define EF_CTRL_EF_IF_0_TRIG                  EF_CTRL_EF_IF_0_TRIG
+#define EF_CTRL_EF_IF_0_TRIG_POS              (4U)
+#define EF_CTRL_EF_IF_0_TRIG_LEN              (1U)
+#define EF_CTRL_EF_IF_0_TRIG_MSK              (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
+#define EF_CTRL_EF_IF_0_TRIG_UMSK             (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
+#define EF_CTRL_EF_IF_0_MANUAL_EN             EF_CTRL_EF_IF_0_MANUAL_EN
+#define EF_CTRL_EF_IF_0_MANUAL_EN_POS         (5U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN         (1U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK         (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_0_CYC_MODIFY            EF_CTRL_EF_IF_0_CYC_MODIFY
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS        (6U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN        (1U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK        (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK       (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL          EF_CTRL_EF_CLK_SAHB_DATA_SEL
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS      (7U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN      (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK      (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK     (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL          EF_CTRL_EF_IF_PROT_CODE_CTRL
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS      (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN      (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK      (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK     (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
+#define EF_CTRL_EF_IF_POR_DIG                 EF_CTRL_EF_IF_POR_DIG
+#define EF_CTRL_EF_IF_POR_DIG_POS             (16U)
+#define EF_CTRL_EF_IF_POR_DIG_LEN             (1U)
+#define EF_CTRL_EF_IF_POR_DIG_MSK             (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
+#define EF_CTRL_EF_IF_POR_DIG_UMSK            (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE         EF_CTRL_EF_CLK_SAHB_DATA_GATE
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS     (17U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN     (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK     (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK    (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
+#define EF_CTRL_EF_IF_AUTO_RD_EN              EF_CTRL_EF_IF_AUTO_RD_EN
+#define EF_CTRL_EF_IF_AUTO_RD_EN_POS          (18U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN          (1U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK          (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK         (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK         EF_CTRL_EF_IF_CYC_MODIFY_LOCK
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS     (19U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN     (1U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK     (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK    (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
+#define EF_CTRL_EF_IF_0_INT                   EF_CTRL_EF_IF_0_INT
+#define EF_CTRL_EF_IF_0_INT_POS               (20U)
+#define EF_CTRL_EF_IF_0_INT_LEN               (1U)
+#define EF_CTRL_EF_IF_0_INT_MSK               (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
+#define EF_CTRL_EF_IF_0_INT_UMSK              (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
+#define EF_CTRL_EF_IF_0_INT_CLR               EF_CTRL_EF_IF_0_INT_CLR
+#define EF_CTRL_EF_IF_0_INT_CLR_POS           (21U)
+#define EF_CTRL_EF_IF_0_INT_CLR_LEN           (1U)
+#define EF_CTRL_EF_IF_0_INT_CLR_MSK           (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
+#define EF_CTRL_EF_IF_0_INT_CLR_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
+#define EF_CTRL_EF_IF_0_INT_SET               EF_CTRL_EF_IF_0_INT_SET
+#define EF_CTRL_EF_IF_0_INT_SET_POS           (22U)
+#define EF_CTRL_EF_IF_0_INT_SET_LEN           (1U)
+#define EF_CTRL_EF_IF_0_INT_SET_MSK           (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
+#define EF_CTRL_EF_IF_0_INT_SET_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CYC           EF_CTRL_EF_IF_PROT_CODE_CYC
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS       (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN       (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK       (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK      (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
+
+/* 0x804 : ef_if_cyc_0 */
+#define EF_CTRL_EF_IF_CYC_0_OFFSET     (0x804)
+#define EF_CTRL_EF_IF_CYC_RD_DMY       EF_CTRL_EF_IF_CYC_RD_DMY
+#define EF_CTRL_EF_IF_CYC_RD_DMY_POS   (0U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS))
+#define EF_CTRL_EF_IF_CYC_RD_DAT       EF_CTRL_EF_IF_CYC_RD_DAT
+#define EF_CTRL_EF_IF_CYC_RD_DAT_POS   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS))
+#define EF_CTRL_EF_IF_CYC_RD_ADR       EF_CTRL_EF_IF_CYC_RD_ADR
+#define EF_CTRL_EF_IF_CYC_RD_ADR_POS   (12U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_CS           EF_CTRL_EF_IF_CYC_CS
+#define EF_CTRL_EF_IF_CYC_CS_POS       (18U)
+#define EF_CTRL_EF_IF_CYC_CS_LEN       (6U)
+#define EF_CTRL_EF_IF_CYC_CS_MSK       (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)
+#define EF_CTRL_EF_IF_CYC_CS_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_S      EF_CTRL_EF_IF_CYC_PD_CS_S
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS  (24U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN  (8U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS))
+
+/* 0x808 : ef_if_cyc_1 */
+#define EF_CTRL_EF_IF_CYC_1_OFFSET     (0x808)
+#define EF_CTRL_EF_IF_CYC_PI           EF_CTRL_EF_IF_CYC_PI
+#define EF_CTRL_EF_IF_CYC_PI_POS       (0U)
+#define EF_CTRL_EF_IF_CYC_PI_LEN       (6U)
+#define EF_CTRL_EF_IF_CYC_PI_MSK       (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)
+#define EF_CTRL_EF_IF_CYC_PI_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS))
+#define EF_CTRL_EF_IF_CYC_PP           EF_CTRL_EF_IF_CYC_PP
+#define EF_CTRL_EF_IF_CYC_PP_POS       (6U)
+#define EF_CTRL_EF_IF_CYC_PP_LEN       (8U)
+#define EF_CTRL_EF_IF_CYC_PP_MSK       (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)
+#define EF_CTRL_EF_IF_CYC_PP_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS))
+#define EF_CTRL_EF_IF_CYC_WR_ADR       EF_CTRL_EF_IF_CYC_WR_ADR
+#define EF_CTRL_EF_IF_CYC_WR_ADR_POS   (14U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_PS_CS        EF_CTRL_EF_IF_CYC_PS_CS
+#define EF_CTRL_EF_IF_CYC_PS_CS_POS    (20U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_LEN    (6U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_MSK    (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)
+#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK   (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_H      EF_CTRL_EF_IF_CYC_PD_CS_H
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS  (26U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN  (6U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS))
+
+/* 0x80C : ef_if_0_manual */
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET       (0x80C)
+#define EF_CTRL_EF_IF_A                     EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS                 (0U)
+#define EF_CTRL_EF_IF_A_LEN                 (10U)
+#define EF_CTRL_EF_IF_A_MSK                 (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMSK                (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD                    EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS                (10U)
+#define EF_CTRL_EF_IF_PD_LEN                (1U)
+#define EF_CTRL_EF_IF_PD_MSK                (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMSK               (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS                    EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS                (11U)
+#define EF_CTRL_EF_IF_PS_LEN                (1U)
+#define EF_CTRL_EF_IF_PS_MSK                (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMSK               (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE                EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS            (12U)
+#define EF_CTRL_EF_IF_STROBE_LEN            (1U)
+#define EF_CTRL_EF_IF_STROBE_MSK            (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMSK           (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB                 EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS             (13U)
+#define EF_CTRL_EF_IF_PGENB_LEN             (1U)
+#define EF_CTRL_EF_IF_PGENB_MSK             (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMSK            (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD                  EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS              (14U)
+#define EF_CTRL_EF_IF_LOAD_LEN              (1U)
+#define EF_CTRL_EF_IF_LOAD_MSK              (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMSK             (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB                   EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS               (15U)
+#define EF_CTRL_EF_IF_CSB_LEN               (1U)
+#define EF_CTRL_EF_IF_CSB_MSK               (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMSK              (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_0_Q                   EF_CTRL_EF_IF_0_Q
+#define EF_CTRL_EF_IF_0_Q_POS               (16U)
+#define EF_CTRL_EF_IF_0_Q_LEN               (8U)
+#define EF_CTRL_EF_IF_0_Q_MSK               (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
+#define EF_CTRL_EF_IF_0_Q_UMSK              (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL      EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS  (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN  (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK  (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+
+/* 0x810 : ef_if_0_status */
+#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
+#define EF_CTRL_EF_IF_0_STATUS        EF_CTRL_EF_IF_0_STATUS
+#define EF_CTRL_EF_IF_0_STATUS_POS    (0U)
+#define EF_CTRL_EF_IF_0_STATUS_LEN    (32U)
+#define EF_CTRL_EF_IF_0_STATUS_MSK    (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)
+#define EF_CTRL_EF_IF_0_STATUS_UMSK   (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS))
+
+/* 0x814 : ef_if_cfg_0 */
+#define EF_CTRL_EF_IF_CFG_0_OFFSET         (0x814)
+#define EF_CTRL_EF_IF_SF_AES_MODE          EF_CTRL_EF_IF_SF_AES_MODE
+#define EF_CTRL_EF_IF_SF_AES_MODE_POS      (0U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_LEN      (2U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)
+#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS))
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE      EF_CTRL_EF_IF_SBOOT_SIGN_MODE
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS))
+#define EF_CTRL_EF_IF_SBOOT_EN             EF_CTRL_EF_IF_SBOOT_EN
+#define EF_CTRL_EF_IF_SBOOT_EN_POS         (4U)
+#define EF_CTRL_EF_IF_SBOOT_EN_LEN         (2U)
+#define EF_CTRL_EF_IF_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)
+#define EF_CTRL_EF_IF_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS))
+#define EF_CTRL_EF_IF_CPU1_ENC_EN          EF_CTRL_EF_IF_CPU1_ENC_EN
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS      (6U)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS))
+#define EF_CTRL_EF_IF_CPU0_ENC_EN          EF_CTRL_EF_IF_CPU0_ENC_EN
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS      (7U)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS))
+#define EF_CTRL_EF_IF_BOOT_SEL             EF_CTRL_EF_IF_BOOT_SEL
+#define EF_CTRL_EF_IF_BOOT_SEL_POS         (8U)
+#define EF_CTRL_EF_IF_BOOT_SEL_LEN         (4U)
+#define EF_CTRL_EF_IF_BOOT_SEL_MSK         (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)
+#define EF_CTRL_EF_IF_BOOT_SEL_UMSK        (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS))
+#define EF_CTRL_EF_IF_SW_USAGE_1           EF_CTRL_EF_IF_SW_USAGE_1
+#define EF_CTRL_EF_IF_SW_USAGE_1_POS       (12U)
+#define EF_CTRL_EF_IF_SW_USAGE_1_LEN       (2U)
+#define EF_CTRL_EF_IF_SW_USAGE_1_MSK       (((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS)
+#define EF_CTRL_EF_IF_SW_USAGE_1_UMSK      (~(((1U << EF_CTRL_EF_IF_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_1_POS))
+#define EF_CTRL_EF_IF_SDU_DIS              EF_CTRL_EF_IF_SDU_DIS
+#define EF_CTRL_EF_IF_SDU_DIS_POS          (14U)
+#define EF_CTRL_EF_IF_SDU_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_SDU_DIS_MSK          (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)
+#define EF_CTRL_EF_IF_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS))
+#define EF_CTRL_EF_IF_BLE_DIS              EF_CTRL_EF_IF_BLE_DIS
+#define EF_CTRL_EF_IF_BLE_DIS_POS          (15U)
+#define EF_CTRL_EF_IF_BLE_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_BLE_DIS_MSK          (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)
+#define EF_CTRL_EF_IF_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS))
+#define EF_CTRL_EF_IF_WIFI_DIS             EF_CTRL_EF_IF_WIFI_DIS
+#define EF_CTRL_EF_IF_WIFI_DIS_POS         (16U)
+#define EF_CTRL_EF_IF_WIFI_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)
+#define EF_CTRL_EF_IF_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS))
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN         EF_CTRL_EF_IF_0_KEY_ENC_EN
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS     (17U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN     (1U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_IF_CAM_DIS              EF_CTRL_EF_IF_CAM_DIS
+#define EF_CTRL_EF_IF_CAM_DIS_POS          (18U)
+#define EF_CTRL_EF_IF_CAM_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_CAM_DIS_MSK          (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)
+#define EF_CTRL_EF_IF_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS))
+#define EF_CTRL_EF_IF_SF_DIS               EF_CTRL_EF_IF_SF_DIS
+#define EF_CTRL_EF_IF_SF_DIS_POS           (19U)
+#define EF_CTRL_EF_IF_SF_DIS_LEN           (1U)
+#define EF_CTRL_EF_IF_SF_DIS_MSK           (((1U << EF_CTRL_EF_IF_SF_DIS_LEN) - 1) << EF_CTRL_EF_IF_SF_DIS_POS)
+#define EF_CTRL_EF_IF_SF_DIS_UMSK          (~(((1U << EF_CTRL_EF_IF_SF_DIS_LEN) - 1) << EF_CTRL_EF_IF_SF_DIS_POS))
+#define EF_CTRL_EF_IF_CPU1_DIS             EF_CTRL_EF_IF_CPU1_DIS
+#define EF_CTRL_EF_IF_CPU1_DIS_POS         (20U)
+#define EF_CTRL_EF_IF_CPU1_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)
+#define EF_CTRL_EF_IF_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS))
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS      EF_CTRL_EF_IF_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS  (21U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN  (1U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_SE_DBG_DIS           EF_CTRL_EF_IF_SE_DBG_DIS
+#define EF_CTRL_EF_IF_SE_DBG_DIS_POS       (22U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN       (1U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS        EF_CTRL_EF_IF_EFUSE_DBG_DIS
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS    (23U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN    (1U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS       EF_CTRL_EF_IF_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS   (24U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN   (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS       EF_CTRL_EF_IF_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_MODE             EF_CTRL_EF_IF_DBG_MODE
+#define EF_CTRL_EF_IF_DBG_MODE_POS         (28U)
+#define EF_CTRL_EF_IF_DBG_MODE_LEN         (4U)
+#define EF_CTRL_EF_IF_DBG_MODE_MSK         (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)
+#define EF_CTRL_EF_IF_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS))
+
+/* 0x818 : ef_sw_cfg_0 */
+#define EF_CTRL_EF_SW_CFG_0_OFFSET         (0x818)
+#define EF_CTRL_EF_SW_SF_AES_MODE          EF_CTRL_EF_SW_SF_AES_MODE
+#define EF_CTRL_EF_SW_SF_AES_MODE_POS      (0U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_LEN      (2U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)
+#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS))
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE      EF_CTRL_EF_SW_SBOOT_SIGN_MODE
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS))
+#define EF_CTRL_EF_SW_SBOOT_EN             EF_CTRL_EF_SW_SBOOT_EN
+#define EF_CTRL_EF_SW_SBOOT_EN_POS         (4U)
+#define EF_CTRL_EF_SW_SBOOT_EN_LEN         (2U)
+#define EF_CTRL_EF_SW_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)
+#define EF_CTRL_EF_SW_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS))
+#define EF_CTRL_EF_SW_CPU1_ENC_EN          EF_CTRL_EF_SW_CPU1_ENC_EN
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS      (6U)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS))
+#define EF_CTRL_EF_SW_CPU0_ENC_EN          EF_CTRL_EF_SW_CPU0_ENC_EN
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS      (7U)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS))
+#define EF_CTRL_EF_SW_SW_USAGE_1           EF_CTRL_EF_SW_SW_USAGE_1
+#define EF_CTRL_EF_SW_SW_USAGE_1_POS       (12U)
+#define EF_CTRL_EF_SW_SW_USAGE_1_LEN       (2U)
+#define EF_CTRL_EF_SW_SW_USAGE_1_MSK       (((1U << EF_CTRL_EF_SW_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_SW_SW_USAGE_1_POS)
+#define EF_CTRL_EF_SW_SW_USAGE_1_UMSK      (~(((1U << EF_CTRL_EF_SW_SW_USAGE_1_LEN) - 1) << EF_CTRL_EF_SW_SW_USAGE_1_POS))
+#define EF_CTRL_EF_SW_SDU_DIS              EF_CTRL_EF_SW_SDU_DIS
+#define EF_CTRL_EF_SW_SDU_DIS_POS          (14U)
+#define EF_CTRL_EF_SW_SDU_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_SDU_DIS_MSK          (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)
+#define EF_CTRL_EF_SW_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS))
+#define EF_CTRL_EF_SW_BLE_DIS              EF_CTRL_EF_SW_BLE_DIS
+#define EF_CTRL_EF_SW_BLE_DIS_POS          (15U)
+#define EF_CTRL_EF_SW_BLE_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_BLE_DIS_MSK          (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)
+#define EF_CTRL_EF_SW_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS))
+#define EF_CTRL_EF_SW_WIFI_DIS             EF_CTRL_EF_SW_WIFI_DIS
+#define EF_CTRL_EF_SW_WIFI_DIS_POS         (16U)
+#define EF_CTRL_EF_SW_WIFI_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)
+#define EF_CTRL_EF_SW_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS))
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN         EF_CTRL_EF_SW_0_KEY_ENC_EN
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS     (17U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN     (1U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_SW_CAM_DIS              EF_CTRL_EF_SW_CAM_DIS
+#define EF_CTRL_EF_SW_CAM_DIS_POS          (18U)
+#define EF_CTRL_EF_SW_CAM_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_CAM_DIS_MSK          (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)
+#define EF_CTRL_EF_SW_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS))
+#define EF_CTRL_EF_SW_SF_DIS               EF_CTRL_EF_SW_SF_DIS
+#define EF_CTRL_EF_SW_SF_DIS_POS           (19U)
+#define EF_CTRL_EF_SW_SF_DIS_LEN           (1U)
+#define EF_CTRL_EF_SW_SF_DIS_MSK           (((1U << EF_CTRL_EF_SW_SF_DIS_LEN) - 1) << EF_CTRL_EF_SW_SF_DIS_POS)
+#define EF_CTRL_EF_SW_SF_DIS_UMSK          (~(((1U << EF_CTRL_EF_SW_SF_DIS_LEN) - 1) << EF_CTRL_EF_SW_SF_DIS_POS))
+#define EF_CTRL_EF_SW_CPU1_DIS             EF_CTRL_EF_SW_CPU1_DIS
+#define EF_CTRL_EF_SW_CPU1_DIS_POS         (20U)
+#define EF_CTRL_EF_SW_CPU1_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)
+#define EF_CTRL_EF_SW_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS))
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS      EF_CTRL_EF_SW_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS  (21U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN  (1U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_SE_DBG_DIS           EF_CTRL_EF_SW_SE_DBG_DIS
+#define EF_CTRL_EF_SW_SE_DBG_DIS_POS       (22U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN       (1U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS        EF_CTRL_EF_SW_EFUSE_DBG_DIS
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS    (23U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN    (1U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS       EF_CTRL_EF_SW_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS   (24U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN   (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS       EF_CTRL_EF_SW_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_MODE             EF_CTRL_EF_SW_DBG_MODE
+#define EF_CTRL_EF_SW_DBG_MODE_POS         (28U)
+#define EF_CTRL_EF_SW_DBG_MODE_LEN         (4U)
+#define EF_CTRL_EF_SW_DBG_MODE_MSK         (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)
+#define EF_CTRL_EF_SW_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS))
+
+/* 0x81C : ef_reserved */
+#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
+#define EF_CTRL_EF_RESERVED        EF_CTRL_EF_RESERVED
+#define EF_CTRL_EF_RESERVED_POS    (0U)
+#define EF_CTRL_EF_RESERVED_LEN    (32U)
+#define EF_CTRL_EF_RESERVED_MSK    (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)
+#define EF_CTRL_EF_RESERVED_UMSK   (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS))
+
+/* 0x820 : ef_if_ana_trim_0 */
+#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820)
+#define EF_CTRL_EF_IF_ANA_TRIM_0        EF_CTRL_EF_IF_ANA_TRIM_0
+#define EF_CTRL_EF_IF_ANA_TRIM_0_POS    (0U)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN    (32U)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK    (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK   (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS))
+
+/* 0x824 : ef_if_sw_usage_0 */
+#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824)
+#define EF_CTRL_EF_IF_SW_USAGE_0        EF_CTRL_EF_IF_SW_USAGE_0
+#define EF_CTRL_EF_IF_SW_USAGE_0_POS    (0U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_LEN    (32U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_MSK    (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)
+#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK   (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS))
+
+/* 0xA00 : ef_crc_ctrl_0 */
+#define EF_CTRL_EF_CRC_CTRL_0_OFFSET    (0xA00)
+#define EF_CTRL_EF_CRC_BUSY             EF_CTRL_EF_CRC_BUSY
+#define EF_CTRL_EF_CRC_BUSY_POS         (0U)
+#define EF_CTRL_EF_CRC_BUSY_LEN         (1U)
+#define EF_CTRL_EF_CRC_BUSY_MSK         (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)
+#define EF_CTRL_EF_CRC_BUSY_UMSK        (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS))
+#define EF_CTRL_EF_CRC_TRIG             EF_CTRL_EF_CRC_TRIG
+#define EF_CTRL_EF_CRC_TRIG_POS         (1U)
+#define EF_CTRL_EF_CRC_TRIG_LEN         (1U)
+#define EF_CTRL_EF_CRC_TRIG_MSK         (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)
+#define EF_CTRL_EF_CRC_TRIG_UMSK        (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS))
+#define EF_CTRL_EF_CRC_EN               EF_CTRL_EF_CRC_EN
+#define EF_CTRL_EF_CRC_EN_POS           (2U)
+#define EF_CTRL_EF_CRC_EN_LEN           (1U)
+#define EF_CTRL_EF_CRC_EN_MSK           (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)
+#define EF_CTRL_EF_CRC_EN_UMSK          (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS))
+#define EF_CTRL_EF_CRC_MODE             EF_CTRL_EF_CRC_MODE
+#define EF_CTRL_EF_CRC_MODE_POS         (3U)
+#define EF_CTRL_EF_CRC_MODE_LEN         (1U)
+#define EF_CTRL_EF_CRC_MODE_MSK         (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)
+#define EF_CTRL_EF_CRC_MODE_UMSK        (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS))
+#define EF_CTRL_EF_CRC_ERROR            EF_CTRL_EF_CRC_ERROR
+#define EF_CTRL_EF_CRC_ERROR_POS        (4U)
+#define EF_CTRL_EF_CRC_ERROR_LEN        (1U)
+#define EF_CTRL_EF_CRC_ERROR_MSK        (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)
+#define EF_CTRL_EF_CRC_ERROR_UMSK       (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS))
+#define EF_CTRL_EF_CRC_DOUT_INV_EN      EF_CTRL_EF_CRC_DOUT_INV_EN
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS  (5U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN  (1U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN      EF_CTRL_EF_CRC_DOUT_ENDIAN
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS  (6U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN  (1U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_DIN_ENDIAN       EF_CTRL_EF_CRC_DIN_ENDIAN
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS   (7U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN   (1U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK   (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK  (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_INT              EF_CTRL_EF_CRC_INT
+#define EF_CTRL_EF_CRC_INT_POS          (8U)
+#define EF_CTRL_EF_CRC_INT_LEN          (1U)
+#define EF_CTRL_EF_CRC_INT_MSK          (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)
+#define EF_CTRL_EF_CRC_INT_UMSK         (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS))
+#define EF_CTRL_EF_CRC_INT_CLR          EF_CTRL_EF_CRC_INT_CLR
+#define EF_CTRL_EF_CRC_INT_CLR_POS      (9U)
+#define EF_CTRL_EF_CRC_INT_CLR_LEN      (1U)
+#define EF_CTRL_EF_CRC_INT_CLR_MSK      (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)
+#define EF_CTRL_EF_CRC_INT_CLR_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS))
+#define EF_CTRL_EF_CRC_INT_SET          EF_CTRL_EF_CRC_INT_SET
+#define EF_CTRL_EF_CRC_INT_SET_POS      (10U)
+#define EF_CTRL_EF_CRC_INT_SET_LEN      (1U)
+#define EF_CTRL_EF_CRC_INT_SET_MSK      (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)
+#define EF_CTRL_EF_CRC_INT_SET_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS))
+#define EF_CTRL_EF_CRC_LOCK             EF_CTRL_EF_CRC_LOCK
+#define EF_CTRL_EF_CRC_LOCK_POS         (11U)
+#define EF_CTRL_EF_CRC_LOCK_LEN         (1U)
+#define EF_CTRL_EF_CRC_LOCK_MSK         (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)
+#define EF_CTRL_EF_CRC_LOCK_UMSK        (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS))
+#define EF_CTRL_EF_CRC_SLP_N            EF_CTRL_EF_CRC_SLP_N
+#define EF_CTRL_EF_CRC_SLP_N_POS        (16U)
+#define EF_CTRL_EF_CRC_SLP_N_LEN        (16U)
+#define EF_CTRL_EF_CRC_SLP_N_MSK        (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)
+#define EF_CTRL_EF_CRC_SLP_N_UMSK       (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS))
+
+/* 0xA04 : ef_crc_ctrl_1 */
+#define EF_CTRL_EF_CRC_CTRL_1_OFFSET  (0xA04)
+#define EF_CTRL_EF_CRC_DATA_0_EN      EF_CTRL_EF_CRC_DATA_0_EN
+#define EF_CTRL_EF_CRC_DATA_0_EN_POS  (0U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_LEN  (32U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS))
+
+/* 0xA08 : ef_crc_ctrl_2 */
+#define EF_CTRL_EF_CRC_CTRL_2_OFFSET  (0xA08)
+#define EF_CTRL_EF_CRC_DATA_1_EN      EF_CTRL_EF_CRC_DATA_1_EN
+#define EF_CTRL_EF_CRC_DATA_1_EN_POS  (0U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_LEN  (32U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS))
+
+/* 0xA0C : ef_crc_ctrl_3 */
+#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
+#define EF_CTRL_EF_CRC_IV            EF_CTRL_EF_CRC_IV
+#define EF_CTRL_EF_CRC_IV_POS        (0U)
+#define EF_CTRL_EF_CRC_IV_LEN        (32U)
+#define EF_CTRL_EF_CRC_IV_MSK        (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)
+#define EF_CTRL_EF_CRC_IV_UMSK       (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS))
+
+/* 0xA10 : ef_crc_ctrl_4 */
+#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
+#define EF_CTRL_EF_CRC_GOLDEN        EF_CTRL_EF_CRC_GOLDEN
+#define EF_CTRL_EF_CRC_GOLDEN_POS    (0U)
+#define EF_CTRL_EF_CRC_GOLDEN_LEN    (32U)
+#define EF_CTRL_EF_CRC_GOLDEN_MSK    (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)
+#define EF_CTRL_EF_CRC_GOLDEN_UMSK   (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS))
+
+/* 0xA14 : ef_crc_ctrl_5 */
+#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
+#define EF_CTRL_EF_CRC_DOUT          EF_CTRL_EF_CRC_DOUT
+#define EF_CTRL_EF_CRC_DOUT_POS      (0U)
+#define EF_CTRL_EF_CRC_DOUT_LEN      (32U)
+#define EF_CTRL_EF_CRC_DOUT_MSK      (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)
+#define EF_CTRL_EF_CRC_DOUT_UMSK     (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS))
+
+struct ef_ctrl_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[2048];
+
+    /* 0x800 : ef_if_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_0_autoload_p1_done : 1; /* [    0],          r,        0x1 */
+            uint32_t ef_if_0_autoload_done    : 1; /* [    1],          r,        0x1 */
+            uint32_t ef_if_0_busy             : 1; /* [    2],          r,        0x0 */
+            uint32_t ef_if_0_rw               : 1; /* [    3],        r/w,        0x0 */
+            uint32_t ef_if_0_trig             : 1; /* [    4],        r/w,        0x0 */
+            uint32_t ef_if_0_manual_en        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t ef_if_0_cyc_modify       : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_clk_sahb_data_sel     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t ef_if_prot_code_ctrl     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t ef_if_por_dig            : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_clk_sahb_data_gate    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t ef_if_auto_rd_en         : 1; /* [   18],        r/w,        0x1 */
+            uint32_t ef_if_cyc_modify_lock    : 1; /* [   19],        r/w,        0x0 */
+            uint32_t ef_if_0_int              : 1; /* [   20],          r,        0x0 */
+            uint32_t ef_if_0_int_clr          : 1; /* [   21],        r/w,        0x1 */
+            uint32_t ef_if_0_int_set          : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t ef_if_prot_code_cyc      : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_ctrl_0;
+
+    /* 0x804 : ef_if_cyc_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_cyc_rd_dmy  : 6; /* [ 5: 0],        r/w,        0x0 */
+            uint32_t ef_if_cyc_rd_dat  : 6; /* [11: 6],        r/w,        0x1 */
+            uint32_t ef_if_cyc_rd_adr  : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t ef_if_cyc_cs      : 6; /* [23:18],        r/w,        0x0 */
+            uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24],        r/w,       0x16 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cyc_0;
+
+    /* 0x808 : ef_if_cyc_1 */
+    union {
+        struct
+        {
+            uint32_t ef_if_cyc_pi      : 6; /* [ 5: 0],        r/w,        0x9 */
+            uint32_t ef_if_cyc_pp      : 8; /* [13: 6],        r/w,       0x98 */
+            uint32_t ef_if_cyc_wr_adr  : 6; /* [19:14],        r/w,        0x1 */
+            uint32_t ef_if_cyc_ps_cs   : 6; /* [25:20],        r/w,        0x2 */
+            uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cyc_1;
+
+    /* 0x80C : ef_if_0_manual */
+    union {
+        struct
+        {
+            uint32_t ef_if_a                : 10; /* [ 9: 0],        r/w,        0x0 */
+            uint32_t ef_if_pd               : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t ef_if_ps               : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t ef_if_strobe           : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t ef_if_pgenb            : 1;  /* [   13],        r/w,        0x1 */
+            uint32_t ef_if_load             : 1;  /* [   14],        r/w,        0x1 */
+            uint32_t ef_if_csb              : 1;  /* [   15],        r/w,        0x1 */
+            uint32_t ef_if_0_q              : 8;  /* [23:16],          r,        0x0 */
+            uint32_t ef_if_prot_code_manual : 8;  /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_0_manual;
+
+    /* 0x810 : ef_if_0_status */
+    union {
+        struct
+        {
+            uint32_t ef_if_0_status : 32; /* [31: 0],          r,     0xe400 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_0_status;
+
+    /* 0x814 : ef_if_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_sf_aes_mode     : 2; /* [ 1: 0],          r,        0x0 */
+            uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2],          r,        0x0 */
+            uint32_t ef_if_sboot_en        : 2; /* [ 5: 4],          r,        0x0 */
+            uint32_t ef_if_cpu1_enc_en     : 1; /* [    6],          r,        0x0 */
+            uint32_t ef_if_cpu0_enc_en     : 1; /* [    7],          r,        0x0 */
+            uint32_t ef_if_boot_sel        : 4; /* [11: 8],          r,        0x0 */
+            uint32_t ef_if_sw_usage_1      : 2; /* [13:12],          r,        0x0 */
+            uint32_t ef_if_sdu_dis         : 1; /* [   14],          r,        0x0 */
+            uint32_t ef_if_ble_dis         : 1; /* [   15],          r,        0x0 */
+            uint32_t ef_if_wifi_dis        : 1; /* [   16],          r,        0x0 */
+            uint32_t ef_if_0_key_enc_en    : 1; /* [   17],          r,        0x0 */
+            uint32_t ef_if_cam_dis         : 1; /* [   18],          r,        0x0 */
+            uint32_t ef_if_sf_dis          : 1; /* [   19],          r,        0x0 */
+            uint32_t ef_if_cpu1_dis        : 1; /* [   20],          r,        0x0 */
+            uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [   21],          r,        0x0 */
+            uint32_t ef_if_se_dbg_dis      : 1; /* [   22],          r,        0x0 */
+            uint32_t ef_if_efuse_dbg_dis   : 1; /* [   23],          r,        0x0 */
+            uint32_t ef_if_dbg_jtag_1_dis  : 2; /* [25:24],          r,        0x0 */
+            uint32_t ef_if_dbg_jtag_0_dis  : 2; /* [27:26],          r,        0x0 */
+            uint32_t ef_if_dbg_mode        : 4; /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cfg_0;
+
+    /* 0x818 : ef_sw_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sw_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t ef_sw_sboot_en        : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t ef_sw_cpu1_enc_en     : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_sw_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t ef_sw_sw_usage_1      : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t ef_sw_sdu_dis         : 1; /* [   14],        r/w,        0x0 */
+            uint32_t ef_sw_ble_dis         : 1; /* [   15],        r/w,        0x0 */
+            uint32_t ef_sw_wifi_dis        : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_sw_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t ef_sw_cam_dis         : 1; /* [   18],        r/w,        0x0 */
+            uint32_t ef_sw_sf_dis          : 1; /* [   19],        r/w,        0x0 */
+            uint32_t ef_sw_cpu1_dis        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [   21],        r/w,        0x0 */
+            uint32_t ef_sw_se_dbg_dis      : 1; /* [   22],        r/w,        0x0 */
+            uint32_t ef_sw_efuse_dbg_dis   : 1; /* [   23],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_jtag_1_dis  : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_sw_cfg_0;
+
+    /* 0x81C : ef_reserved */
+    union {
+        struct
+        {
+            uint32_t ef_reserved : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } ef_reserved;
+
+    /* 0x820 : ef_if_ana_trim_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_ana_trim_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_ana_trim_0;
+
+    /* 0x824 : ef_if_sw_usage_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_sw_usage_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_sw_usage_0;
+
+    /* 0x828  reserved */
+    uint8_t RESERVED0x828[472];
+
+    /* 0xA00 : ef_crc_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_busy        : 1;  /* [    0],          r,        0x0 */
+            uint32_t ef_crc_trig        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ef_crc_en          : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t ef_crc_mode        : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t ef_crc_error       : 1;  /* [    4],          r,        0x0 */
+            uint32_t ef_crc_dout_inv_en : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t ef_crc_dout_endian : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t ef_crc_din_endian  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t ef_crc_int         : 1;  /* [    8],          r,        0x0 */
+            uint32_t ef_crc_int_clr     : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t ef_crc_int_set     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ef_crc_lock        : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15     : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t ef_crc_slp_n       : 16; /* [31:16],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_0;
+
+    /* 0xA04 : ef_crc_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_data_0_en : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_1;
+
+    /* 0xA08 : ef_crc_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_data_1_en : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_2;
+
+    /* 0xA0C : ef_crc_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_iv : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_3;
+
+    /* 0xA10 : ef_crc_ctrl_4 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_golden : 32; /* [31: 0],        r/w, 0xc2a8fa9dL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_4;
+
+    /* 0xA14 : ef_crc_ctrl_5 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_dout : 32; /* [31: 0],          r, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_5;
+};
+
+typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t;
+
+#endif /* __EF_CTRL_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_data_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_data_reg.h
new file mode 100755
index 0000000000..5e0d45dc4e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/ef_data_reg.h
@@ -0,0 +1,762 @@
+/**
+  ******************************************************************************
+  * @file    EF_DATA_reg.h
+  * @version V1.2
+  * @date    2019-11-22
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __EF_DATA_REG_H__
+#define __EF_DATA_REG_H__
+
+#include "bl602.h"
+
+/* 0x0 : ef_cfg_0 */
+#define EF_DATA_EF_CFG_0_OFFSET         (0x0)
+#define EF_DATA_EF_SF_AES_MODE          EF_DATA_EF_SF_AES_MODE
+#define EF_DATA_EF_SF_AES_MODE_POS      (0U)
+#define EF_DATA_EF_SF_AES_MODE_LEN      (2U)
+#define EF_DATA_EF_SF_AES_MODE_MSK      (((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS)
+#define EF_DATA_EF_SF_AES_MODE_UMSK     (~(((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS))
+#define EF_DATA_EF_SBOOT_SIGN_MODE      EF_DATA_EF_SBOOT_SIGN_MODE
+#define EF_DATA_EF_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_DATA_EF_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_DATA_EF_SBOOT_SIGN_MODE_MSK  (((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS)
+#define EF_DATA_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS))
+#define EF_DATA_EF_SBOOT_EN             EF_DATA_EF_SBOOT_EN
+#define EF_DATA_EF_SBOOT_EN_POS         (4U)
+#define EF_DATA_EF_SBOOT_EN_LEN         (2U)
+#define EF_DATA_EF_SBOOT_EN_MSK         (((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS)
+#define EF_DATA_EF_SBOOT_EN_UMSK        (~(((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS))
+#define EF_DATA_EF_CPU0_ENC_EN          EF_DATA_EF_CPU0_ENC_EN
+#define EF_DATA_EF_CPU0_ENC_EN_POS      (7U)
+#define EF_DATA_EF_CPU0_ENC_EN_LEN      (1U)
+#define EF_DATA_EF_CPU0_ENC_EN_MSK      (((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS)
+#define EF_DATA_EF_CPU0_ENC_EN_UMSK     (~(((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS))
+#define EF_DATA_EF_TRIM_EN              EF_DATA_EF_TRIM_EN
+#define EF_DATA_EF_TRIM_EN_POS          (12U)
+#define EF_DATA_EF_TRIM_EN_LEN          (1U)
+#define EF_DATA_EF_TRIM_EN_MSK          (((1U << EF_DATA_EF_TRIM_EN_LEN) - 1) << EF_DATA_EF_TRIM_EN_POS)
+#define EF_DATA_EF_TRIM_EN_UMSK         (~(((1U << EF_DATA_EF_TRIM_EN_LEN) - 1) << EF_DATA_EF_TRIM_EN_POS))
+#define EF_DATA_EF_NO_HD_BOOT_EN        EF_DATA_EF_NO_HD_BOOT_EN
+#define EF_DATA_EF_NO_HD_BOOT_EN_POS    (13U)
+#define EF_DATA_EF_NO_HD_BOOT_EN_LEN    (1U)
+#define EF_DATA_EF_NO_HD_BOOT_EN_MSK    (((1U << EF_DATA_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_EF_NO_HD_BOOT_EN_POS)
+#define EF_DATA_EF_NO_HD_BOOT_EN_UMSK   (~(((1U << EF_DATA_EF_NO_HD_BOOT_EN_LEN) - 1) << EF_DATA_EF_NO_HD_BOOT_EN_POS))
+#define EF_DATA_EF_0_KEY_ENC_EN         EF_DATA_EF_0_KEY_ENC_EN
+#define EF_DATA_EF_0_KEY_ENC_EN_POS     (17U)
+#define EF_DATA_EF_0_KEY_ENC_EN_LEN     (1U)
+#define EF_DATA_EF_0_KEY_ENC_EN_MSK     (((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS)
+#define EF_DATA_EF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS))
+#define EF_DATA_EF_DBG_JTAG_0_DIS       EF_DATA_EF_DBG_JTAG_0_DIS
+#define EF_DATA_EF_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_DATA_EF_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_DATA_EF_DBG_JTAG_0_DIS_MSK   (((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS)
+#define EF_DATA_EF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS))
+#define EF_DATA_EF_DBG_MODE             EF_DATA_EF_DBG_MODE
+#define EF_DATA_EF_DBG_MODE_POS         (28U)
+#define EF_DATA_EF_DBG_MODE_LEN         (4U)
+#define EF_DATA_EF_DBG_MODE_MSK         (((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS)
+#define EF_DATA_EF_DBG_MODE_UMSK        (~(((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS))
+
+/* 0x4 : ef_dbg_pwd_low */
+#define EF_DATA_EF_DBG_PWD_LOW_OFFSET (0x4)
+#define EF_DATA_EF_DBG_PWD_LOW        EF_DATA_EF_DBG_PWD_LOW
+#define EF_DATA_EF_DBG_PWD_LOW_POS    (0U)
+#define EF_DATA_EF_DBG_PWD_LOW_LEN    (32U)
+#define EF_DATA_EF_DBG_PWD_LOW_MSK    (((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS)
+#define EF_DATA_EF_DBG_PWD_LOW_UMSK   (~(((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS))
+
+/* 0x8 : ef_dbg_pwd_high */
+#define EF_DATA_EF_DBG_PWD_HIGH_OFFSET (0x8)
+#define EF_DATA_EF_DBG_PWD_HIGH        EF_DATA_EF_DBG_PWD_HIGH
+#define EF_DATA_EF_DBG_PWD_HIGH_POS    (0U)
+#define EF_DATA_EF_DBG_PWD_HIGH_LEN    (32U)
+#define EF_DATA_EF_DBG_PWD_HIGH_MSK    (((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS)
+#define EF_DATA_EF_DBG_PWD_HIGH_UMSK   (~(((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS))
+
+/* 0xC : ef_ana_trim_0 */
+#define EF_DATA_EF_ANA_TRIM_0_OFFSET (0xC)
+#define EF_DATA_EF_ANA_TRIM_0        EF_DATA_EF_ANA_TRIM_0
+#define EF_DATA_EF_ANA_TRIM_0_POS    (0U)
+#define EF_DATA_EF_ANA_TRIM_0_LEN    (32U)
+#define EF_DATA_EF_ANA_TRIM_0_MSK    (((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS)
+#define EF_DATA_EF_ANA_TRIM_0_UMSK   (~(((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS))
+
+/* 0x10 : ef_sw_usage_0 */
+#define EF_DATA_EF_SW_USAGE_0_OFFSET (0x10)
+#define EF_DATA_EF_SW_USAGE_0        EF_DATA_EF_SW_USAGE_0
+#define EF_DATA_EF_SW_USAGE_0_POS    (0U)
+#define EF_DATA_EF_SW_USAGE_0_LEN    (32U)
+#define EF_DATA_EF_SW_USAGE_0_MSK    (((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS)
+#define EF_DATA_EF_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS))
+
+/* 0x14 : ef_wifi_mac_low */
+#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
+#define EF_DATA_EF_WIFI_MAC_LOW        EF_DATA_EF_WIFI_MAC_LOW
+#define EF_DATA_EF_WIFI_MAC_LOW_POS    (0U)
+#define EF_DATA_EF_WIFI_MAC_LOW_LEN    (32U)
+#define EF_DATA_EF_WIFI_MAC_LOW_MSK    (((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS)
+#define EF_DATA_EF_WIFI_MAC_LOW_UMSK   (~(((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS))
+
+/* 0x18 : ef_wifi_mac_high */
+#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
+#define EF_DATA_EF_WIFI_MAC_HIGH        EF_DATA_EF_WIFI_MAC_HIGH
+#define EF_DATA_EF_WIFI_MAC_HIGH_POS    (0U)
+#define EF_DATA_EF_WIFI_MAC_HIGH_LEN    (32U)
+#define EF_DATA_EF_WIFI_MAC_HIGH_MSK    (((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS)
+#define EF_DATA_EF_WIFI_MAC_HIGH_UMSK   (~(((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS))
+
+/* 0x1C : ef_key_slot_0_w0 */
+#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
+#define EF_DATA_EF_KEY_SLOT_0_W0        EF_DATA_EF_KEY_SLOT_0_W0
+#define EF_DATA_EF_KEY_SLOT_0_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS))
+
+/* 0x20 : ef_key_slot_0_w1 */
+#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
+#define EF_DATA_EF_KEY_SLOT_0_W1        EF_DATA_EF_KEY_SLOT_0_W1
+#define EF_DATA_EF_KEY_SLOT_0_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS))
+
+/* 0x24 : ef_key_slot_0_w2 */
+#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
+#define EF_DATA_EF_KEY_SLOT_0_W2        EF_DATA_EF_KEY_SLOT_0_W2
+#define EF_DATA_EF_KEY_SLOT_0_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS))
+
+/* 0x28 : ef_key_slot_0_w3 */
+#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
+#define EF_DATA_EF_KEY_SLOT_0_W3        EF_DATA_EF_KEY_SLOT_0_W3
+#define EF_DATA_EF_KEY_SLOT_0_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS))
+
+/* 0x2C : ef_key_slot_1_w0 */
+#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
+#define EF_DATA_EF_KEY_SLOT_1_W0        EF_DATA_EF_KEY_SLOT_1_W0
+#define EF_DATA_EF_KEY_SLOT_1_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS))
+
+/* 0x30 : ef_key_slot_1_w1 */
+#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
+#define EF_DATA_EF_KEY_SLOT_1_W1        EF_DATA_EF_KEY_SLOT_1_W1
+#define EF_DATA_EF_KEY_SLOT_1_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS))
+
+/* 0x34 : ef_key_slot_1_w2 */
+#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
+#define EF_DATA_EF_KEY_SLOT_1_W2        EF_DATA_EF_KEY_SLOT_1_W2
+#define EF_DATA_EF_KEY_SLOT_1_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS))
+
+/* 0x38 : ef_key_slot_1_w3 */
+#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
+#define EF_DATA_EF_KEY_SLOT_1_W3        EF_DATA_EF_KEY_SLOT_1_W3
+#define EF_DATA_EF_KEY_SLOT_1_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS))
+
+/* 0x3C : ef_key_slot_2_w0 */
+#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
+#define EF_DATA_EF_KEY_SLOT_2_W0        EF_DATA_EF_KEY_SLOT_2_W0
+#define EF_DATA_EF_KEY_SLOT_2_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS))
+
+/* 0x40 : ef_key_slot_2_w1 */
+#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
+#define EF_DATA_EF_KEY_SLOT_2_W1        EF_DATA_EF_KEY_SLOT_2_W1
+#define EF_DATA_EF_KEY_SLOT_2_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS))
+
+/* 0x44 : ef_key_slot_2_w2 */
+#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
+#define EF_DATA_EF_KEY_SLOT_2_W2        EF_DATA_EF_KEY_SLOT_2_W2
+#define EF_DATA_EF_KEY_SLOT_2_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS))
+
+/* 0x48 : ef_key_slot_2_w3 */
+#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
+#define EF_DATA_EF_KEY_SLOT_2_W3        EF_DATA_EF_KEY_SLOT_2_W3
+#define EF_DATA_EF_KEY_SLOT_2_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS))
+
+/* 0x4C : ef_key_slot_3_w0 */
+#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
+#define EF_DATA_EF_KEY_SLOT_3_W0        EF_DATA_EF_KEY_SLOT_3_W0
+#define EF_DATA_EF_KEY_SLOT_3_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS))
+
+/* 0x50 : ef_key_slot_3_w1 */
+#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
+#define EF_DATA_EF_KEY_SLOT_3_W1        EF_DATA_EF_KEY_SLOT_3_W1
+#define EF_DATA_EF_KEY_SLOT_3_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS))
+
+/* 0x54 : ef_key_slot_3_w2 */
+#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
+#define EF_DATA_EF_KEY_SLOT_3_W2        EF_DATA_EF_KEY_SLOT_3_W2
+#define EF_DATA_EF_KEY_SLOT_3_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS))
+
+/* 0x58 : ef_key_slot_3_w3 */
+#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
+#define EF_DATA_EF_KEY_SLOT_3_W3        EF_DATA_EF_KEY_SLOT_3_W3
+#define EF_DATA_EF_KEY_SLOT_3_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS))
+
+/* 0x5C : ef_key_slot_4_w0 */
+#define EF_DATA_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
+#define EF_DATA_EF_KEY_SLOT_4_W0        EF_DATA_EF_KEY_SLOT_4_W0
+#define EF_DATA_EF_KEY_SLOT_4_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS))
+
+/* 0x60 : ef_key_slot_4_w1 */
+#define EF_DATA_EF_KEY_SLOT_4_W1_OFFSET (0x60)
+#define EF_DATA_EF_KEY_SLOT_4_W1        EF_DATA_EF_KEY_SLOT_4_W1
+#define EF_DATA_EF_KEY_SLOT_4_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS))
+
+/* 0x64 : ef_key_slot_4_w2 */
+#define EF_DATA_EF_KEY_SLOT_4_W2_OFFSET (0x64)
+#define EF_DATA_EF_KEY_SLOT_4_W2        EF_DATA_EF_KEY_SLOT_4_W2
+#define EF_DATA_EF_KEY_SLOT_4_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS))
+
+/* 0x68 : ef_key_slot_4_w3 */
+#define EF_DATA_EF_KEY_SLOT_4_W3_OFFSET (0x68)
+#define EF_DATA_EF_KEY_SLOT_4_W3        EF_DATA_EF_KEY_SLOT_4_W3
+#define EF_DATA_EF_KEY_SLOT_4_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS))
+
+/* 0x6C : ef_key_slot_5_w0 */
+#define EF_DATA_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
+#define EF_DATA_EF_KEY_SLOT_5_W0        EF_DATA_EF_KEY_SLOT_5_W0
+#define EF_DATA_EF_KEY_SLOT_5_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS))
+
+/* 0x70 : ef_key_slot_5_w1 */
+#define EF_DATA_EF_KEY_SLOT_5_W1_OFFSET (0x70)
+#define EF_DATA_EF_KEY_SLOT_5_W1        EF_DATA_EF_KEY_SLOT_5_W1
+#define EF_DATA_EF_KEY_SLOT_5_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS))
+
+/* 0x74 : ef_key_slot_5_w2 */
+#define EF_DATA_EF_KEY_SLOT_5_W2_OFFSET (0x74)
+#define EF_DATA_EF_KEY_SLOT_5_W2        EF_DATA_EF_KEY_SLOT_5_W2
+#define EF_DATA_EF_KEY_SLOT_5_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS))
+
+/* 0x78 : ef_key_slot_5_w3 */
+#define EF_DATA_EF_KEY_SLOT_5_W3_OFFSET (0x78)
+#define EF_DATA_EF_KEY_SLOT_5_W3        EF_DATA_EF_KEY_SLOT_5_W3
+#define EF_DATA_EF_KEY_SLOT_5_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS))
+
+/* 0x7C : EF_DATA_lock */
+#define EF_DATA_LOCK_OFFSET               (0x7C)
+#define EF_DATA_EF_ANA_TRIM_1             EF_DATA_EF_ANA_TRIM_1
+#define EF_DATA_EF_ANA_TRIM_1_POS         (0U)
+#define EF_DATA_EF_ANA_TRIM_1_LEN         (13U)
+#define EF_DATA_EF_ANA_TRIM_1_MSK         (((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS)
+#define EF_DATA_EF_ANA_TRIM_1_UMSK        (~(((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L      EF_DATA_WR_LOCK_KEY_SLOT_4_L
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS  (13U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L      EF_DATA_WR_LOCK_KEY_SLOT_5_L
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS  (14U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS))
+#define EF_DATA_WR_LOCK_BOOT_MODE         EF_DATA_WR_LOCK_BOOT_MODE
+#define EF_DATA_WR_LOCK_BOOT_MODE_POS     (15U)
+#define EF_DATA_WR_LOCK_BOOT_MODE_LEN     (1U)
+#define EF_DATA_WR_LOCK_BOOT_MODE_MSK     (((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS)
+#define EF_DATA_WR_LOCK_BOOT_MODE_UMSK    (~(((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS))
+#define EF_DATA_WR_LOCK_DBG_PWD           EF_DATA_WR_LOCK_DBG_PWD
+#define EF_DATA_WR_LOCK_DBG_PWD_POS       (16U)
+#define EF_DATA_WR_LOCK_DBG_PWD_LEN       (1U)
+#define EF_DATA_WR_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS)
+#define EF_DATA_WR_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS))
+#define EF_DATA_WR_LOCK_SW_USAGE_0        EF_DATA_WR_LOCK_SW_USAGE_0
+#define EF_DATA_WR_LOCK_SW_USAGE_0_POS    (17U)
+#define EF_DATA_WR_LOCK_SW_USAGE_0_LEN    (1U)
+#define EF_DATA_WR_LOCK_SW_USAGE_0_MSK    (((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS)
+#define EF_DATA_WR_LOCK_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS))
+#define EF_DATA_WR_LOCK_WIFI_MAC          EF_DATA_WR_LOCK_WIFI_MAC
+#define EF_DATA_WR_LOCK_WIFI_MAC_POS      (18U)
+#define EF_DATA_WR_LOCK_WIFI_MAC_LEN      (1U)
+#define EF_DATA_WR_LOCK_WIFI_MAC_MSK      (((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS)
+#define EF_DATA_WR_LOCK_WIFI_MAC_UMSK     (~(((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_0        EF_DATA_WR_LOCK_KEY_SLOT_0
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_POS    (19U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_1        EF_DATA_WR_LOCK_KEY_SLOT_1
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_POS    (20U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_2        EF_DATA_WR_LOCK_KEY_SLOT_2
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_POS    (21U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_3        EF_DATA_WR_LOCK_KEY_SLOT_3
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_POS    (22U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H      EF_DATA_WR_LOCK_KEY_SLOT_4_H
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS  (23U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H      EF_DATA_WR_LOCK_KEY_SLOT_5_H
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS  (24U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS))
+#define EF_DATA_RD_LOCK_DBG_PWD           EF_DATA_RD_LOCK_DBG_PWD
+#define EF_DATA_RD_LOCK_DBG_PWD_POS       (25U)
+#define EF_DATA_RD_LOCK_DBG_PWD_LEN       (1U)
+#define EF_DATA_RD_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS)
+#define EF_DATA_RD_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_0        EF_DATA_RD_LOCK_KEY_SLOT_0
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_POS    (26U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_1        EF_DATA_RD_LOCK_KEY_SLOT_1
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_POS    (27U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_2        EF_DATA_RD_LOCK_KEY_SLOT_2
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_POS    (28U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_3        EF_DATA_RD_LOCK_KEY_SLOT_3
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_POS    (29U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_4        EF_DATA_RD_LOCK_KEY_SLOT_4
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_POS    (30U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_5        EF_DATA_RD_LOCK_KEY_SLOT_5
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_POS    (31U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS))
+
+struct EF_DATA_reg {
+    /* 0x0 : ef_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t ef_sboot_en        : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6         : 1; /* [    6],       rsvd,        0x0 */
+            uint32_t ef_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_11      : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t ef_sw_usage_1      : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t rsvd0              : 1; /* [   14],        r/w,        0x0 */
+            uint32_t rsvd1              : 1; /* [   15],        r/w,        0x0 */
+            uint32_t rsvd2              : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reserved_18        : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t rsvd3              : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20        : 1; /* [   20],       rsvd,        0x0 */
+            uint32_t rsvd4              : 1; /* [   21],        r/w,        0x0 */
+            uint32_t rsvd5              : 1; /* [   22],        r/w,        0x0 */
+            uint32_t rsvd6              : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_25     : 2; /* [25:24],       rsvd,        0x0 */
+            uint32_t ef_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
+            uint32_t ef_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_cfg_0;
+
+    /* 0x4 : ef_dbg_pwd_low */
+    union {
+        struct
+        {
+            uint32_t ef_dbg_pwd_low : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_dbg_pwd_low;
+
+    /* 0x8 : ef_dbg_pwd_high */
+    union {
+        struct
+        {
+            uint32_t ef_dbg_pwd_high : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_dbg_pwd_high;
+
+    /* 0xC : ef_ana_trim_0 */
+    union {
+        struct
+        {
+            uint32_t ef_ana_trim_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_ana_trim_0;
+
+    /* 0x10 : ef_sw_usage_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sw_usage_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_sw_usage_0;
+
+    /* 0x14 : ef_wifi_mac_low */
+    union {
+        struct
+        {
+            uint32_t ef_wifi_mac_low : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_wifi_mac_low;
+
+    /* 0x18 : ef_wifi_mac_high */
+    union {
+        struct
+        {
+            uint32_t ef_wifi_mac_high : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_wifi_mac_high;
+
+    /* 0x1C : ef_key_slot_0_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w0;
+
+    /* 0x20 : ef_key_slot_0_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w1;
+
+    /* 0x24 : ef_key_slot_0_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w2;
+
+    /* 0x28 : ef_key_slot_0_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w3;
+
+    /* 0x2C : ef_key_slot_1_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w0;
+
+    /* 0x30 : ef_key_slot_1_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w1;
+
+    /* 0x34 : ef_key_slot_1_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w2;
+
+    /* 0x38 : ef_key_slot_1_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w3;
+
+    /* 0x3C : ef_key_slot_2_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w0;
+
+    /* 0x40 : ef_key_slot_2_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w1;
+
+    /* 0x44 : ef_key_slot_2_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w2;
+
+    /* 0x48 : ef_key_slot_2_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w3;
+
+    /* 0x4C : ef_key_slot_3_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w0;
+
+    /* 0x50 : ef_key_slot_3_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w1;
+
+    /* 0x54 : ef_key_slot_3_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w2;
+
+    /* 0x58 : ef_key_slot_3_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w3;
+
+    /* 0x5C : ef_key_slot_4_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w0;
+
+    /* 0x60 : ef_key_slot_4_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w1;
+
+    /* 0x64 : ef_key_slot_4_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w2;
+
+    /* 0x68 : ef_key_slot_4_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w3;
+
+    /* 0x6C : ef_key_slot_5_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w0;
+
+    /* 0x70 : ef_key_slot_5_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w1;
+
+    /* 0x74 : ef_key_slot_5_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w2;
+
+    /* 0x78 : ef_key_slot_5_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w3;
+
+    /* 0x7C : EF_DATA_lock */
+    union {
+        struct
+        {
+            uint32_t ef_ana_trim_1        : 13; /* [12: 0],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_4_l : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_5_l : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t wr_lock_boot_mode    : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t wr_lock_dbg_pwd      : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t wr_lock_sw_usage_0   : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t wr_lock_wifi_mac     : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_0   : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_1   : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_2   : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_3   : 1;  /* [   22],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_4_h : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_5_h : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t rd_lock_dbg_pwd      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_0   : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_1   : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_2   : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_3   : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_4   : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_5   : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } EF_DATA_lock;
+};
+
+typedef volatile struct EF_DATA_reg EF_DATA_reg_t;
+
+#endif /* __EF_DATA_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/glb_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/glb_reg.h
new file mode 100755
index 0000000000..f60cab6401
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/glb_reg.h
@@ -0,0 +1,4094 @@
+/**
+  ******************************************************************************
+  * @file    glb_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __GLB_REG_H__
+#define __GLB_REG_H__
+
+#include "bl602.h"
+
+/* 0x0 : clk_cfg0 */
+#define GLB_CLK_CFG0_OFFSET       (0x0)
+#define GLB_REG_PLL_EN            GLB_REG_PLL_EN
+#define GLB_REG_PLL_EN_POS        (0U)
+#define GLB_REG_PLL_EN_LEN        (1U)
+#define GLB_REG_PLL_EN_MSK        (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
+#define GLB_REG_PLL_EN_UMSK       (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
+#define GLB_REG_FCLK_EN           GLB_REG_FCLK_EN
+#define GLB_REG_FCLK_EN_POS       (1U)
+#define GLB_REG_FCLK_EN_LEN       (1U)
+#define GLB_REG_FCLK_EN_MSK       (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
+#define GLB_REG_FCLK_EN_UMSK      (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
+#define GLB_REG_HCLK_EN           GLB_REG_HCLK_EN
+#define GLB_REG_HCLK_EN_POS       (2U)
+#define GLB_REG_HCLK_EN_LEN       (1U)
+#define GLB_REG_HCLK_EN_MSK       (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
+#define GLB_REG_HCLK_EN_UMSK      (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
+#define GLB_REG_BCLK_EN           GLB_REG_BCLK_EN
+#define GLB_REG_BCLK_EN_POS       (3U)
+#define GLB_REG_BCLK_EN_LEN       (1U)
+#define GLB_REG_BCLK_EN_MSK       (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
+#define GLB_REG_BCLK_EN_UMSK      (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
+#define GLB_REG_PLL_SEL           GLB_REG_PLL_SEL
+#define GLB_REG_PLL_SEL_POS       (4U)
+#define GLB_REG_PLL_SEL_LEN       (2U)
+#define GLB_REG_PLL_SEL_MSK       (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
+#define GLB_REG_PLL_SEL_UMSK      (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
+#define GLB_HBN_ROOT_CLK_SEL      GLB_HBN_ROOT_CLK_SEL
+#define GLB_HBN_ROOT_CLK_SEL_POS  (6U)
+#define GLB_HBN_ROOT_CLK_SEL_LEN  (2U)
+#define GLB_HBN_ROOT_CLK_SEL_MSK  (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
+#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
+#define GLB_REG_HCLK_DIV          GLB_REG_HCLK_DIV
+#define GLB_REG_HCLK_DIV_POS      (8U)
+#define GLB_REG_HCLK_DIV_LEN      (8U)
+#define GLB_REG_HCLK_DIV_MSK      (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
+#define GLB_REG_HCLK_DIV_UMSK     (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
+#define GLB_REG_BCLK_DIV          GLB_REG_BCLK_DIV
+#define GLB_REG_BCLK_DIV_POS      (16U)
+#define GLB_REG_BCLK_DIV_LEN      (8U)
+#define GLB_REG_BCLK_DIV_MSK      (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
+#define GLB_REG_BCLK_DIV_UMSK     (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
+#define GLB_FCLK_SW_STATE         GLB_FCLK_SW_STATE
+#define GLB_FCLK_SW_STATE_POS     (24U)
+#define GLB_FCLK_SW_STATE_LEN     (3U)
+#define GLB_FCLK_SW_STATE_MSK     (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
+#define GLB_FCLK_SW_STATE_UMSK    (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
+#define GLB_CHIP_RDY              GLB_CHIP_RDY
+#define GLB_CHIP_RDY_POS          (27U)
+#define GLB_CHIP_RDY_LEN          (1U)
+#define GLB_CHIP_RDY_MSK          (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
+#define GLB_CHIP_RDY_UMSK         (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
+#define GLB_ID                    GLB_ID
+#define GLB_ID_POS                (28U)
+#define GLB_ID_LEN                (4U)
+#define GLB_ID_MSK                (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
+#define GLB_ID_UMSK               (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))
+
+/* 0x4 : clk_cfg1 */
+#define GLB_CLK_CFG1_OFFSET        (0x4)
+#define GLB_WIFI_MAC_CORE_DIV      GLB_WIFI_MAC_CORE_DIV
+#define GLB_WIFI_MAC_CORE_DIV_POS  (0U)
+#define GLB_WIFI_MAC_CORE_DIV_LEN  (4U)
+#define GLB_WIFI_MAC_CORE_DIV_MSK  (((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS)
+#define GLB_WIFI_MAC_CORE_DIV_UMSK (~(((1U << GLB_WIFI_MAC_CORE_DIV_LEN) - 1) << GLB_WIFI_MAC_CORE_DIV_POS))
+#define GLB_WIFI_MAC_WT_DIV        GLB_WIFI_MAC_WT_DIV
+#define GLB_WIFI_MAC_WT_DIV_POS    (4U)
+#define GLB_WIFI_MAC_WT_DIV_LEN    (4U)
+#define GLB_WIFI_MAC_WT_DIV_MSK    (((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS)
+#define GLB_WIFI_MAC_WT_DIV_UMSK   (~(((1U << GLB_WIFI_MAC_WT_DIV_LEN) - 1) << GLB_WIFI_MAC_WT_DIV_POS))
+#define GLB_BLE_CLK_SEL            GLB_BLE_CLK_SEL
+#define GLB_BLE_CLK_SEL_POS        (16U)
+#define GLB_BLE_CLK_SEL_LEN        (6U)
+#define GLB_BLE_CLK_SEL_MSK        (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
+#define GLB_BLE_CLK_SEL_UMSK       (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
+#define GLB_BLE_EN                 GLB_BLE_EN
+#define GLB_BLE_EN_POS             (24U)
+#define GLB_BLE_EN_LEN             (1U)
+#define GLB_BLE_EN_MSK             (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
+#define GLB_BLE_EN_UMSK            (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
+
+/* 0x8 : clk_cfg2 */
+#define GLB_CLK_CFG2_OFFSET       (0x8)
+#define GLB_UART_CLK_DIV          GLB_UART_CLK_DIV
+#define GLB_UART_CLK_DIV_POS      (0U)
+#define GLB_UART_CLK_DIV_LEN      (3U)
+#define GLB_UART_CLK_DIV_MSK      (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
+#define GLB_UART_CLK_DIV_UMSK     (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
+#define GLB_UART_CLK_EN           GLB_UART_CLK_EN
+#define GLB_UART_CLK_EN_POS       (4U)
+#define GLB_UART_CLK_EN_LEN       (1U)
+#define GLB_UART_CLK_EN_MSK       (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
+#define GLB_UART_CLK_EN_UMSK      (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
+#define GLB_HBN_UART_CLK_SEL      GLB_HBN_UART_CLK_SEL
+#define GLB_HBN_UART_CLK_SEL_POS  (7U)
+#define GLB_HBN_UART_CLK_SEL_LEN  (1U)
+#define GLB_HBN_UART_CLK_SEL_MSK  (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
+#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
+#define GLB_SF_CLK_DIV            GLB_SF_CLK_DIV
+#define GLB_SF_CLK_DIV_POS        (8U)
+#define GLB_SF_CLK_DIV_LEN        (3U)
+#define GLB_SF_CLK_DIV_MSK        (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
+#define GLB_SF_CLK_DIV_UMSK       (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
+#define GLB_SF_CLK_EN             GLB_SF_CLK_EN
+#define GLB_SF_CLK_EN_POS         (11U)
+#define GLB_SF_CLK_EN_LEN         (1U)
+#define GLB_SF_CLK_EN_MSK         (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
+#define GLB_SF_CLK_EN_UMSK        (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
+#define GLB_SF_CLK_SEL            GLB_SF_CLK_SEL
+#define GLB_SF_CLK_SEL_POS        (12U)
+#define GLB_SF_CLK_SEL_LEN        (2U)
+#define GLB_SF_CLK_SEL_MSK        (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
+#define GLB_SF_CLK_SEL_UMSK       (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
+#define GLB_SF_CLK_SEL2           GLB_SF_CLK_SEL2
+#define GLB_SF_CLK_SEL2_POS       (14U)
+#define GLB_SF_CLK_SEL2_LEN       (2U)
+#define GLB_SF_CLK_SEL2_MSK       (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
+#define GLB_SF_CLK_SEL2_UMSK      (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
+#define GLB_IR_CLK_DIV            GLB_IR_CLK_DIV
+#define GLB_IR_CLK_DIV_POS        (16U)
+#define GLB_IR_CLK_DIV_LEN        (6U)
+#define GLB_IR_CLK_DIV_MSK        (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
+#define GLB_IR_CLK_DIV_UMSK       (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
+#define GLB_IR_CLK_EN             GLB_IR_CLK_EN
+#define GLB_IR_CLK_EN_POS         (23U)
+#define GLB_IR_CLK_EN_LEN         (1U)
+#define GLB_IR_CLK_EN_MSK         (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
+#define GLB_IR_CLK_EN_UMSK        (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
+#define GLB_DMA_CLK_EN            GLB_DMA_CLK_EN
+#define GLB_DMA_CLK_EN_POS        (24U)
+#define GLB_DMA_CLK_EN_LEN        (8U)
+#define GLB_DMA_CLK_EN_MSK        (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
+#define GLB_DMA_CLK_EN_UMSK       (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
+
+/* 0xC : clk_cfg3 */
+#define GLB_CLK_CFG3_OFFSET  (0xC)
+#define GLB_SPI_CLK_DIV      GLB_SPI_CLK_DIV
+#define GLB_SPI_CLK_DIV_POS  (0U)
+#define GLB_SPI_CLK_DIV_LEN  (5U)
+#define GLB_SPI_CLK_DIV_MSK  (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
+#define GLB_SPI_CLK_DIV_UMSK (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
+#define GLB_SPI_CLK_EN       GLB_SPI_CLK_EN
+#define GLB_SPI_CLK_EN_POS   (8U)
+#define GLB_SPI_CLK_EN_LEN   (1U)
+#define GLB_SPI_CLK_EN_MSK   (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
+#define GLB_SPI_CLK_EN_UMSK  (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
+#define GLB_I2C_CLK_DIV      GLB_I2C_CLK_DIV
+#define GLB_I2C_CLK_DIV_POS  (16U)
+#define GLB_I2C_CLK_DIV_LEN  (8U)
+#define GLB_I2C_CLK_DIV_MSK  (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
+#define GLB_I2C_CLK_DIV_UMSK (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
+#define GLB_I2C_CLK_EN       GLB_I2C_CLK_EN
+#define GLB_I2C_CLK_EN_POS   (24U)
+#define GLB_I2C_CLK_EN_LEN   (1U)
+#define GLB_I2C_CLK_EN_MSK   (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
+#define GLB_I2C_CLK_EN_UMSK  (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
+
+/* 0x10 : swrst_cfg0 */
+#define GLB_SWRST_CFG0_OFFSET (0x10)
+#define GLB_SWRST_S00         GLB_SWRST_S00
+#define GLB_SWRST_S00_POS     (0U)
+#define GLB_SWRST_S00_LEN     (1U)
+#define GLB_SWRST_S00_MSK     (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
+#define GLB_SWRST_S00_UMSK    (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
+#define GLB_SWRST_S01         GLB_SWRST_S01
+#define GLB_SWRST_S01_POS     (1U)
+#define GLB_SWRST_S01_LEN     (1U)
+#define GLB_SWRST_S01_MSK     (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
+#define GLB_SWRST_S01_UMSK    (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
+#define GLB_SWRST_S20         GLB_SWRST_S20
+#define GLB_SWRST_S20_POS     (4U)
+#define GLB_SWRST_S20_LEN     (1U)
+#define GLB_SWRST_S20_MSK     (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
+#define GLB_SWRST_S20_UMSK    (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
+#define GLB_SWRST_S30         GLB_SWRST_S30
+#define GLB_SWRST_S30_POS     (8U)
+#define GLB_SWRST_S30_LEN     (1U)
+#define GLB_SWRST_S30_MSK     (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
+#define GLB_SWRST_S30_UMSK    (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
+
+/* 0x14 : swrst_cfg1 */
+#define GLB_SWRST_CFG1_OFFSET (0x14)
+#define GLB_SWRST_S10         GLB_SWRST_S10
+#define GLB_SWRST_S10_POS     (0U)
+#define GLB_SWRST_S10_LEN     (1U)
+#define GLB_SWRST_S10_MSK     (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
+#define GLB_SWRST_S10_UMSK    (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
+#define GLB_SWRST_S11         GLB_SWRST_S11
+#define GLB_SWRST_S11_POS     (1U)
+#define GLB_SWRST_S11_LEN     (1U)
+#define GLB_SWRST_S11_MSK     (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
+#define GLB_SWRST_S11_UMSK    (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
+#define GLB_SWRST_S12         GLB_SWRST_S12
+#define GLB_SWRST_S12_POS     (2U)
+#define GLB_SWRST_S12_LEN     (1U)
+#define GLB_SWRST_S12_MSK     (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
+#define GLB_SWRST_S12_UMSK    (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
+#define GLB_SWRST_S13         GLB_SWRST_S13
+#define GLB_SWRST_S13_POS     (3U)
+#define GLB_SWRST_S13_LEN     (1U)
+#define GLB_SWRST_S13_MSK     (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
+#define GLB_SWRST_S13_UMSK    (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
+#define GLB_SWRST_S14         GLB_SWRST_S14
+#define GLB_SWRST_S14_POS     (4U)
+#define GLB_SWRST_S14_LEN     (1U)
+#define GLB_SWRST_S14_MSK     (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
+#define GLB_SWRST_S14_UMSK    (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
+#define GLB_SWRST_S15         GLB_SWRST_S15
+#define GLB_SWRST_S15_POS     (5U)
+#define GLB_SWRST_S15_LEN     (1U)
+#define GLB_SWRST_S15_MSK     (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
+#define GLB_SWRST_S15_UMSK    (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
+#define GLB_SWRST_S16         GLB_SWRST_S16
+#define GLB_SWRST_S16_POS     (6U)
+#define GLB_SWRST_S16_LEN     (1U)
+#define GLB_SWRST_S16_MSK     (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
+#define GLB_SWRST_S16_UMSK    (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
+#define GLB_SWRST_S17         GLB_SWRST_S17
+#define GLB_SWRST_S17_POS     (7U)
+#define GLB_SWRST_S17_LEN     (1U)
+#define GLB_SWRST_S17_MSK     (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
+#define GLB_SWRST_S17_UMSK    (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
+#define GLB_SWRST_S18         GLB_SWRST_S18
+#define GLB_SWRST_S18_POS     (8U)
+#define GLB_SWRST_S18_LEN     (1U)
+#define GLB_SWRST_S18_MSK     (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
+#define GLB_SWRST_S18_UMSK    (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
+#define GLB_SWRST_S19         GLB_SWRST_S19
+#define GLB_SWRST_S19_POS     (9U)
+#define GLB_SWRST_S19_LEN     (1U)
+#define GLB_SWRST_S19_MSK     (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
+#define GLB_SWRST_S19_UMSK    (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
+#define GLB_SWRST_S1A         GLB_SWRST_S1A
+#define GLB_SWRST_S1A_POS     (10U)
+#define GLB_SWRST_S1A_LEN     (1U)
+#define GLB_SWRST_S1A_MSK     (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
+#define GLB_SWRST_S1A_UMSK    (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
+#define GLB_SWRST_S1B         GLB_SWRST_S1B
+#define GLB_SWRST_S1B_POS     (11U)
+#define GLB_SWRST_S1B_LEN     (1U)
+#define GLB_SWRST_S1B_MSK     (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
+#define GLB_SWRST_S1B_UMSK    (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
+#define GLB_SWRST_S1C         GLB_SWRST_S1C
+#define GLB_SWRST_S1C_POS     (12U)
+#define GLB_SWRST_S1C_LEN     (1U)
+#define GLB_SWRST_S1C_MSK     (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
+#define GLB_SWRST_S1C_UMSK    (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
+#define GLB_SWRST_S1D         GLB_SWRST_S1D
+#define GLB_SWRST_S1D_POS     (13U)
+#define GLB_SWRST_S1D_LEN     (1U)
+#define GLB_SWRST_S1D_MSK     (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
+#define GLB_SWRST_S1D_UMSK    (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
+#define GLB_SWRST_S1E         GLB_SWRST_S1E
+#define GLB_SWRST_S1E_POS     (14U)
+#define GLB_SWRST_S1E_LEN     (1U)
+#define GLB_SWRST_S1E_MSK     (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
+#define GLB_SWRST_S1E_UMSK    (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
+#define GLB_SWRST_S1F         GLB_SWRST_S1F
+#define GLB_SWRST_S1F_POS     (15U)
+#define GLB_SWRST_S1F_LEN     (1U)
+#define GLB_SWRST_S1F_MSK     (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
+#define GLB_SWRST_S1F_UMSK    (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
+#define GLB_SWRST_S1A0        GLB_SWRST_S1A0
+#define GLB_SWRST_S1A0_POS    (16U)
+#define GLB_SWRST_S1A0_LEN    (1U)
+#define GLB_SWRST_S1A0_MSK    (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
+#define GLB_SWRST_S1A0_UMSK   (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
+#define GLB_SWRST_S1A1        GLB_SWRST_S1A1
+#define GLB_SWRST_S1A1_POS    (17U)
+#define GLB_SWRST_S1A1_LEN    (1U)
+#define GLB_SWRST_S1A1_MSK    (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
+#define GLB_SWRST_S1A1_UMSK   (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
+#define GLB_SWRST_S1A2        GLB_SWRST_S1A2
+#define GLB_SWRST_S1A2_POS    (18U)
+#define GLB_SWRST_S1A2_LEN    (1U)
+#define GLB_SWRST_S1A2_MSK    (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
+#define GLB_SWRST_S1A2_UMSK   (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
+#define GLB_SWRST_S1A3        GLB_SWRST_S1A3
+#define GLB_SWRST_S1A3_POS    (19U)
+#define GLB_SWRST_S1A3_LEN    (1U)
+#define GLB_SWRST_S1A3_MSK    (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
+#define GLB_SWRST_S1A3_UMSK   (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
+#define GLB_SWRST_S1A4        GLB_SWRST_S1A4
+#define GLB_SWRST_S1A4_POS    (20U)
+#define GLB_SWRST_S1A4_LEN    (1U)
+#define GLB_SWRST_S1A4_MSK    (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
+#define GLB_SWRST_S1A4_UMSK   (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
+#define GLB_SWRST_S1A5        GLB_SWRST_S1A5
+#define GLB_SWRST_S1A5_POS    (21U)
+#define GLB_SWRST_S1A5_LEN    (1U)
+#define GLB_SWRST_S1A5_MSK    (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
+#define GLB_SWRST_S1A5_UMSK   (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
+#define GLB_SWRST_S1A6        GLB_SWRST_S1A6
+#define GLB_SWRST_S1A6_POS    (22U)
+#define GLB_SWRST_S1A6_LEN    (1U)
+#define GLB_SWRST_S1A6_MSK    (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
+#define GLB_SWRST_S1A6_UMSK   (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
+#define GLB_SWRST_S1A7        GLB_SWRST_S1A7
+#define GLB_SWRST_S1A7_POS    (23U)
+#define GLB_SWRST_S1A7_LEN    (1U)
+#define GLB_SWRST_S1A7_MSK    (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
+#define GLB_SWRST_S1A7_UMSK   (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
+
+/* 0x18 : swrst_cfg2 */
+#define GLB_SWRST_CFG2_OFFSET         (0x18)
+#define GLB_REG_CTRL_PWRON_RST        GLB_REG_CTRL_PWRON_RST
+#define GLB_REG_CTRL_PWRON_RST_POS    (0U)
+#define GLB_REG_CTRL_PWRON_RST_LEN    (1U)
+#define GLB_REG_CTRL_PWRON_RST_MSK    (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
+#define GLB_REG_CTRL_PWRON_RST_UMSK   (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
+#define GLB_REG_CTRL_CPU_RESET        GLB_REG_CTRL_CPU_RESET
+#define GLB_REG_CTRL_CPU_RESET_POS    (1U)
+#define GLB_REG_CTRL_CPU_RESET_LEN    (1U)
+#define GLB_REG_CTRL_CPU_RESET_MSK    (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
+#define GLB_REG_CTRL_CPU_RESET_UMSK   (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
+#define GLB_REG_CTRL_SYS_RESET        GLB_REG_CTRL_SYS_RESET
+#define GLB_REG_CTRL_SYS_RESET_POS    (2U)
+#define GLB_REG_CTRL_SYS_RESET_LEN    (1U)
+#define GLB_REG_CTRL_SYS_RESET_MSK    (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
+#define GLB_REG_CTRL_SYS_RESET_UMSK   (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
+#define GLB_REG_CTRL_RESET_DUMMY      GLB_REG_CTRL_RESET_DUMMY
+#define GLB_REG_CTRL_RESET_DUMMY_POS  (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_LEN  (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_MSK  (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
+#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS))
+#define GLB_PKA_CLK_SEL               GLB_PKA_CLK_SEL
+#define GLB_PKA_CLK_SEL_POS           (24U)
+#define GLB_PKA_CLK_SEL_LEN           (1U)
+#define GLB_PKA_CLK_SEL_MSK           (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
+#define GLB_PKA_CLK_SEL_UMSK          (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
+
+/* 0x1C : swrst_cfg3 */
+#define GLB_SWRST_CFG3_OFFSET (0x1C)
+
+/* 0x20 : cgen_cfg0 */
+#define GLB_CGEN_CFG0_OFFSET (0x20)
+#define GLB_CGEN_M           GLB_CGEN_M
+#define GLB_CGEN_M_POS       (0U)
+#define GLB_CGEN_M_LEN       (8U)
+#define GLB_CGEN_M_MSK       (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
+#define GLB_CGEN_M_UMSK      (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))
+
+/* 0x24 : cgen_cfg1 */
+#define GLB_CGEN_CFG1_OFFSET (0x24)
+#define GLB_CGEN_S1          GLB_CGEN_S1
+#define GLB_CGEN_S1_POS      (0U)
+#define GLB_CGEN_S1_LEN      (16U)
+#define GLB_CGEN_S1_MSK      (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
+#define GLB_CGEN_S1_UMSK     (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
+#define GLB_CGEN_S1A         GLB_CGEN_S1A
+#define GLB_CGEN_S1A_POS     (16U)
+#define GLB_CGEN_S1A_LEN     (8U)
+#define GLB_CGEN_S1A_MSK     (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
+#define GLB_CGEN_S1A_UMSK    (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))
+
+/* 0x28 : cgen_cfg2 */
+#define GLB_CGEN_CFG2_OFFSET (0x28)
+#define GLB_CGEN_S2          GLB_CGEN_S2
+#define GLB_CGEN_S2_POS      (0U)
+#define GLB_CGEN_S2_LEN      (1U)
+#define GLB_CGEN_S2_MSK      (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
+#define GLB_CGEN_S2_UMSK     (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
+#define GLB_CGEN_S3          GLB_CGEN_S3
+#define GLB_CGEN_S3_POS      (4U)
+#define GLB_CGEN_S3_LEN      (1U)
+#define GLB_CGEN_S3_MSK      (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
+#define GLB_CGEN_S3_UMSK     (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))
+
+/* 0x2C : cgen_cfg3 */
+#define GLB_CGEN_CFG3_OFFSET (0x2C)
+
+/* 0x30 : MBIST_CTL */
+#define GLB_MBIST_CTL_OFFSET      (0x30)
+#define GLB_IROM_MBIST_MODE       GLB_IROM_MBIST_MODE
+#define GLB_IROM_MBIST_MODE_POS   (0U)
+#define GLB_IROM_MBIST_MODE_LEN   (1U)
+#define GLB_IROM_MBIST_MODE_MSK   (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
+#define GLB_IROM_MBIST_MODE_UMSK  (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
+#define GLB_HSRAM_MBIST_MODE      GLB_HSRAM_MBIST_MODE
+#define GLB_HSRAM_MBIST_MODE_POS  (1U)
+#define GLB_HSRAM_MBIST_MODE_LEN  (1U)
+#define GLB_HSRAM_MBIST_MODE_MSK  (((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS)
+#define GLB_HSRAM_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MBIST_MODE_POS))
+#define GLB_TAG_MBIST_MODE        GLB_TAG_MBIST_MODE
+#define GLB_TAG_MBIST_MODE_POS    (2U)
+#define GLB_TAG_MBIST_MODE_LEN    (1U)
+#define GLB_TAG_MBIST_MODE_MSK    (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
+#define GLB_TAG_MBIST_MODE_UMSK   (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
+#define GLB_OCRAM_MBIST_MODE      GLB_OCRAM_MBIST_MODE
+#define GLB_OCRAM_MBIST_MODE_POS  (3U)
+#define GLB_OCRAM_MBIST_MODE_LEN  (1U)
+#define GLB_OCRAM_MBIST_MODE_MSK  (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
+#define GLB_OCRAM_MBIST_MODE_UMSK (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
+#define GLB_WIFI_MBIST_MODE       GLB_WIFI_MBIST_MODE
+#define GLB_WIFI_MBIST_MODE_POS   (4U)
+#define GLB_WIFI_MBIST_MODE_LEN   (1U)
+#define GLB_WIFI_MBIST_MODE_MSK   (((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS)
+#define GLB_WIFI_MBIST_MODE_UMSK  (~(((1U << GLB_WIFI_MBIST_MODE_LEN) - 1) << GLB_WIFI_MBIST_MODE_POS))
+#define GLB_REG_MBIST_RST_N       GLB_REG_MBIST_RST_N
+#define GLB_REG_MBIST_RST_N_POS   (31U)
+#define GLB_REG_MBIST_RST_N_LEN   (1U)
+#define GLB_REG_MBIST_RST_N_MSK   (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
+#define GLB_REG_MBIST_RST_N_UMSK  (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))
+
+/* 0x34 : MBIST_STAT */
+#define GLB_MBIST_STAT_OFFSET     (0x34)
+#define GLB_IROM_MBIST_DONE       GLB_IROM_MBIST_DONE
+#define GLB_IROM_MBIST_DONE_POS   (0U)
+#define GLB_IROM_MBIST_DONE_LEN   (1U)
+#define GLB_IROM_MBIST_DONE_MSK   (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
+#define GLB_IROM_MBIST_DONE_UMSK  (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
+#define GLB_HSRAM_MBIST_DONE      GLB_HSRAM_MBIST_DONE
+#define GLB_HSRAM_MBIST_DONE_POS  (1U)
+#define GLB_HSRAM_MBIST_DONE_LEN  (1U)
+#define GLB_HSRAM_MBIST_DONE_MSK  (((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS)
+#define GLB_HSRAM_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MBIST_DONE_POS))
+#define GLB_TAG_MBIST_DONE        GLB_TAG_MBIST_DONE
+#define GLB_TAG_MBIST_DONE_POS    (2U)
+#define GLB_TAG_MBIST_DONE_LEN    (1U)
+#define GLB_TAG_MBIST_DONE_MSK    (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
+#define GLB_TAG_MBIST_DONE_UMSK   (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
+#define GLB_OCRAM_MBIST_DONE      GLB_OCRAM_MBIST_DONE
+#define GLB_OCRAM_MBIST_DONE_POS  (3U)
+#define GLB_OCRAM_MBIST_DONE_LEN  (1U)
+#define GLB_OCRAM_MBIST_DONE_MSK  (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
+#define GLB_OCRAM_MBIST_DONE_UMSK (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
+#define GLB_WIFI_MBIST_DONE       GLB_WIFI_MBIST_DONE
+#define GLB_WIFI_MBIST_DONE_POS   (4U)
+#define GLB_WIFI_MBIST_DONE_LEN   (1U)
+#define GLB_WIFI_MBIST_DONE_MSK   (((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS)
+#define GLB_WIFI_MBIST_DONE_UMSK  (~(((1U << GLB_WIFI_MBIST_DONE_LEN) - 1) << GLB_WIFI_MBIST_DONE_POS))
+#define GLB_IROM_MBIST_FAIL       GLB_IROM_MBIST_FAIL
+#define GLB_IROM_MBIST_FAIL_POS   (16U)
+#define GLB_IROM_MBIST_FAIL_LEN   (1U)
+#define GLB_IROM_MBIST_FAIL_MSK   (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
+#define GLB_IROM_MBIST_FAIL_UMSK  (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
+#define GLB_HSRAM_MBIST_FAIL      GLB_HSRAM_MBIST_FAIL
+#define GLB_HSRAM_MBIST_FAIL_POS  (17U)
+#define GLB_HSRAM_MBIST_FAIL_LEN  (1U)
+#define GLB_HSRAM_MBIST_FAIL_MSK  (((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS)
+#define GLB_HSRAM_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MBIST_FAIL_POS))
+#define GLB_TAG_MBIST_FAIL        GLB_TAG_MBIST_FAIL
+#define GLB_TAG_MBIST_FAIL_POS    (18U)
+#define GLB_TAG_MBIST_FAIL_LEN    (1U)
+#define GLB_TAG_MBIST_FAIL_MSK    (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
+#define GLB_TAG_MBIST_FAIL_UMSK   (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
+#define GLB_OCRAM_MBIST_FAIL      GLB_OCRAM_MBIST_FAIL
+#define GLB_OCRAM_MBIST_FAIL_POS  (19U)
+#define GLB_OCRAM_MBIST_FAIL_LEN  (1U)
+#define GLB_OCRAM_MBIST_FAIL_MSK  (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
+#define GLB_OCRAM_MBIST_FAIL_UMSK (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
+#define GLB_WIFI_MBIST_FAIL       GLB_WIFI_MBIST_FAIL
+#define GLB_WIFI_MBIST_FAIL_POS   (20U)
+#define GLB_WIFI_MBIST_FAIL_LEN   (1U)
+#define GLB_WIFI_MBIST_FAIL_MSK   (((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS)
+#define GLB_WIFI_MBIST_FAIL_UMSK  (~(((1U << GLB_WIFI_MBIST_FAIL_LEN) - 1) << GLB_WIFI_MBIST_FAIL_POS))
+
+/* 0x50 : bmx_cfg1 */
+#define GLB_BMX_CFG1_OFFSET          (0x50)
+#define GLB_BMX_TIMEOUT_EN           GLB_BMX_TIMEOUT_EN
+#define GLB_BMX_TIMEOUT_EN_POS       (0U)
+#define GLB_BMX_TIMEOUT_EN_LEN       (4U)
+#define GLB_BMX_TIMEOUT_EN_MSK       (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
+#define GLB_BMX_TIMEOUT_EN_UMSK      (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
+#define GLB_BMX_ARB_MODE             GLB_BMX_ARB_MODE
+#define GLB_BMX_ARB_MODE_POS         (4U)
+#define GLB_BMX_ARB_MODE_LEN         (2U)
+#define GLB_BMX_ARB_MODE_MSK         (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
+#define GLB_BMX_ARB_MODE_UMSK        (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
+#define GLB_BMX_ERR_EN               GLB_BMX_ERR_EN
+#define GLB_BMX_ERR_EN_POS           (8U)
+#define GLB_BMX_ERR_EN_LEN           (1U)
+#define GLB_BMX_ERR_EN_MSK           (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
+#define GLB_BMX_ERR_EN_UMSK          (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
+#define GLB_BMX_BUSY_OPTION_DIS      GLB_BMX_BUSY_OPTION_DIS
+#define GLB_BMX_BUSY_OPTION_DIS_POS  (9U)
+#define GLB_BMX_BUSY_OPTION_DIS_LEN  (1U)
+#define GLB_BMX_BUSY_OPTION_DIS_MSK  (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
+#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS))
+#define GLB_BMX_GATING_DIS           GLB_BMX_GATING_DIS
+#define GLB_BMX_GATING_DIS_POS       (10U)
+#define GLB_BMX_GATING_DIS_LEN       (1U)
+#define GLB_BMX_GATING_DIS_MSK       (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
+#define GLB_BMX_GATING_DIS_UMSK      (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
+#define GLB_HSEL_OPTION              GLB_HSEL_OPTION
+#define GLB_HSEL_OPTION_POS          (12U)
+#define GLB_HSEL_OPTION_LEN          (4U)
+#define GLB_HSEL_OPTION_MSK          (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
+#define GLB_HSEL_OPTION_UMSK         (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
+#define GLB_PDS_APB_CFG              GLB_PDS_APB_CFG
+#define GLB_PDS_APB_CFG_POS          (16U)
+#define GLB_PDS_APB_CFG_LEN          (8U)
+#define GLB_PDS_APB_CFG_MSK          (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
+#define GLB_PDS_APB_CFG_UMSK         (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
+#define GLB_HBN_APB_CFG              GLB_HBN_APB_CFG
+#define GLB_HBN_APB_CFG_POS          (24U)
+#define GLB_HBN_APB_CFG_LEN          (8U)
+#define GLB_HBN_APB_CFG_MSK          (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
+#define GLB_HBN_APB_CFG_UMSK         (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
+
+/* 0x54 : bmx_cfg2 */
+#define GLB_BMX_CFG2_OFFSET       (0x54)
+#define GLB_BMX_ERR_ADDR_DIS      GLB_BMX_ERR_ADDR_DIS
+#define GLB_BMX_ERR_ADDR_DIS_POS  (0U)
+#define GLB_BMX_ERR_ADDR_DIS_LEN  (1U)
+#define GLB_BMX_ERR_ADDR_DIS_MSK  (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
+#define GLB_BMX_ERR_ADDR_DIS_UMSK (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
+#define GLB_BMX_ERR_DEC           GLB_BMX_ERR_DEC
+#define GLB_BMX_ERR_DEC_POS       (4U)
+#define GLB_BMX_ERR_DEC_LEN       (1U)
+#define GLB_BMX_ERR_DEC_MSK       (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
+#define GLB_BMX_ERR_DEC_UMSK      (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
+#define GLB_BMX_ERR_TZ            GLB_BMX_ERR_TZ
+#define GLB_BMX_ERR_TZ_POS        (5U)
+#define GLB_BMX_ERR_TZ_LEN        (1U)
+#define GLB_BMX_ERR_TZ_MSK        (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
+#define GLB_BMX_ERR_TZ_UMSK       (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
+#define GLB_BMX_DBG_SEL           GLB_BMX_DBG_SEL
+#define GLB_BMX_DBG_SEL_POS       (28U)
+#define GLB_BMX_DBG_SEL_LEN       (4U)
+#define GLB_BMX_DBG_SEL_MSK       (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
+#define GLB_BMX_DBG_SEL_UMSK      (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
+
+/* 0x58 : bmx_err_addr */
+#define GLB_BMX_ERR_ADDR_OFFSET (0x58)
+#define GLB_BMX_ERR_ADDR        GLB_BMX_ERR_ADDR
+#define GLB_BMX_ERR_ADDR_POS    (0U)
+#define GLB_BMX_ERR_ADDR_LEN    (32U)
+#define GLB_BMX_ERR_ADDR_MSK    (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
+#define GLB_BMX_ERR_ADDR_UMSK   (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))
+
+/* 0x5C : bmx_dbg_out */
+#define GLB_BMX_DBG_OUT_OFFSET (0x5C)
+#define GLB_BMX_DBG_OUT        GLB_BMX_DBG_OUT
+#define GLB_BMX_DBG_OUT_POS    (0U)
+#define GLB_BMX_DBG_OUT_LEN    (32U)
+#define GLB_BMX_DBG_OUT_MSK    (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
+#define GLB_BMX_DBG_OUT_UMSK   (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))
+
+/* 0x60 : rsv0 */
+#define GLB_RSV0_OFFSET (0x60)
+
+/* 0x64 : rsv1 */
+#define GLB_RSV1_OFFSET (0x64)
+
+/* 0x68 : rsv2 */
+#define GLB_RSV2_OFFSET (0x68)
+
+/* 0x6C : rsv3 */
+#define GLB_RSV3_OFFSET (0x6C)
+
+/* 0x70 : sram_ret */
+#define GLB_SRAM_RET_OFFSET   (0x70)
+#define GLB_REG_SRAM_RET      GLB_REG_SRAM_RET
+#define GLB_REG_SRAM_RET_POS  (0U)
+#define GLB_REG_SRAM_RET_LEN  (32U)
+#define GLB_REG_SRAM_RET_MSK  (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
+#define GLB_REG_SRAM_RET_UMSK (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))
+
+/* 0x74 : sram_slp */
+#define GLB_SRAM_SLP_OFFSET   (0x74)
+#define GLB_REG_SRAM_SLP      GLB_REG_SRAM_SLP
+#define GLB_REG_SRAM_SLP_POS  (0U)
+#define GLB_REG_SRAM_SLP_LEN  (32U)
+#define GLB_REG_SRAM_SLP_MSK  (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
+#define GLB_REG_SRAM_SLP_UMSK (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))
+
+/* 0x78 : sram_parm */
+#define GLB_SRAM_PARM_OFFSET   (0x78)
+#define GLB_REG_SRAM_PARM      GLB_REG_SRAM_PARM
+#define GLB_REG_SRAM_PARM_POS  (0U)
+#define GLB_REG_SRAM_PARM_LEN  (32U)
+#define GLB_REG_SRAM_PARM_MSK  (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
+#define GLB_REG_SRAM_PARM_UMSK (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))
+
+/* 0x7C : seam_misc */
+#define GLB_SEAM_MISC_OFFSET (0x7C)
+#define GLB_EM_SEL           GLB_EM_SEL
+#define GLB_EM_SEL_POS       (0U)
+#define GLB_EM_SEL_LEN       (4U)
+#define GLB_EM_SEL_MSK       (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
+#define GLB_EM_SEL_UMSK      (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
+
+/* 0x80 : glb_parm */
+#define GLB_PARM_OFFSET                (0x80)
+#define GLB_REG_BD_EN                  GLB_REG_BD_EN
+#define GLB_REG_BD_EN_POS              (0U)
+#define GLB_REG_BD_EN_LEN              (1U)
+#define GLB_REG_BD_EN_MSK              (((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS)
+#define GLB_REG_BD_EN_UMSK             (~(((1U << GLB_REG_BD_EN_LEN) - 1) << GLB_REG_BD_EN_POS))
+#define GLB_REG_EXT_RST_SMT            GLB_REG_EXT_RST_SMT
+#define GLB_REG_EXT_RST_SMT_POS        (1U)
+#define GLB_REG_EXT_RST_SMT_LEN        (1U)
+#define GLB_REG_EXT_RST_SMT_MSK        (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
+#define GLB_REG_EXT_RST_SMT_UMSK       (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
+#define GLB_JTAG_SWAP_SET              GLB_JTAG_SWAP_SET
+#define GLB_JTAG_SWAP_SET_POS          (2U)
+#define GLB_JTAG_SWAP_SET_LEN          (6U)
+#define GLB_JTAG_SWAP_SET_MSK          (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
+#define GLB_JTAG_SWAP_SET_UMSK         (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
+#define GLB_SWAP_SFLASH_IO_3_IO_0      GLB_SWAP_SFLASH_IO_3_IO_0
+#define GLB_SWAP_SFLASH_IO_3_IO_0_POS  (8U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN  (1U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK  (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS))
+#define GLB_SEL_EMBEDDED_SFLASH        GLB_SEL_EMBEDDED_SFLASH
+#define GLB_SEL_EMBEDDED_SFLASH_POS    (9U)
+#define GLB_SEL_EMBEDDED_SFLASH_LEN    (1U)
+#define GLB_SEL_EMBEDDED_SFLASH_MSK    (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)
+#define GLB_SEL_EMBEDDED_SFLASH_UMSK   (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS))
+#define GLB_REG_SPI_0_MASTER_MODE      GLB_REG_SPI_0_MASTER_MODE
+#define GLB_REG_SPI_0_MASTER_MODE_POS  (12U)
+#define GLB_REG_SPI_0_MASTER_MODE_LEN  (1U)
+#define GLB_REG_SPI_0_MASTER_MODE_MSK  (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)
+#define GLB_REG_SPI_0_MASTER_MODE_UMSK (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS))
+#define GLB_REG_SPI_0_SWAP             GLB_REG_SPI_0_SWAP
+#define GLB_REG_SPI_0_SWAP_POS         (13U)
+#define GLB_REG_SPI_0_SWAP_LEN         (1U)
+#define GLB_REG_SPI_0_SWAP_MSK         (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
+#define GLB_REG_SPI_0_SWAP_UMSK        (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
+#define GLB_REG_CCI_USE_JTAG_PIN       GLB_REG_CCI_USE_JTAG_PIN
+#define GLB_REG_CCI_USE_JTAG_PIN_POS   (15U)
+#define GLB_REG_CCI_USE_JTAG_PIN_LEN   (1U)
+#define GLB_REG_CCI_USE_JTAG_PIN_MSK   (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
+#define GLB_REG_CCI_USE_JTAG_PIN_UMSK  (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS))
+#define GLB_REG_CCI_USE_SDIO_PIN       GLB_REG_CCI_USE_SDIO_PIN
+#define GLB_REG_CCI_USE_SDIO_PIN_POS   (16U)
+#define GLB_REG_CCI_USE_SDIO_PIN_LEN   (1U)
+#define GLB_REG_CCI_USE_SDIO_PIN_MSK   (((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS)
+#define GLB_REG_CCI_USE_SDIO_PIN_UMSK  (~(((1U << GLB_REG_CCI_USE_SDIO_PIN_LEN) - 1) << GLB_REG_CCI_USE_SDIO_PIN_POS))
+#define GLB_P1_ADC_TEST_WITH_CCI       GLB_P1_ADC_TEST_WITH_CCI
+#define GLB_P1_ADC_TEST_WITH_CCI_POS   (17U)
+#define GLB_P1_ADC_TEST_WITH_CCI_LEN   (1U)
+#define GLB_P1_ADC_TEST_WITH_CCI_MSK   (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
+#define GLB_P1_ADC_TEST_WITH_CCI_UMSK  (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS))
+#define GLB_P2_DAC_TEST_WITH_CCI       GLB_P2_DAC_TEST_WITH_CCI
+#define GLB_P2_DAC_TEST_WITH_CCI_POS   (18U)
+#define GLB_P2_DAC_TEST_WITH_CCI_LEN   (1U)
+#define GLB_P2_DAC_TEST_WITH_CCI_MSK   (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
+#define GLB_P2_DAC_TEST_WITH_CCI_UMSK  (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS))
+#define GLB_P3_CCI_USE_IO_2_5          GLB_P3_CCI_USE_IO_2_5
+#define GLB_P3_CCI_USE_IO_2_5_POS      (19U)
+#define GLB_P3_CCI_USE_IO_2_5_LEN      (1U)
+#define GLB_P3_CCI_USE_IO_2_5_MSK      (((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS)
+#define GLB_P3_CCI_USE_IO_2_5_UMSK     (~(((1U << GLB_P3_CCI_USE_IO_2_5_LEN) - 1) << GLB_P3_CCI_USE_IO_2_5_POS))
+#define GLB_P4_ADC_TEST_WITH_JTAG      GLB_P4_ADC_TEST_WITH_JTAG
+#define GLB_P4_ADC_TEST_WITH_JTAG_POS  (20U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_LEN  (1U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_MSK  (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)
+#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS))
+#define GLB_P5_DAC_TEST_WITH_JTAG      GLB_P5_DAC_TEST_WITH_JTAG
+#define GLB_P5_DAC_TEST_WITH_JTAG_POS  (21U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_LEN  (1U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_MSK  (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)
+#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS))
+#define GLB_P6_SDIO_USE_IO_0_5         GLB_P6_SDIO_USE_IO_0_5
+#define GLB_P6_SDIO_USE_IO_0_5_POS     (22U)
+#define GLB_P6_SDIO_USE_IO_0_5_LEN     (1U)
+#define GLB_P6_SDIO_USE_IO_0_5_MSK     (((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS)
+#define GLB_P6_SDIO_USE_IO_0_5_UMSK    (~(((1U << GLB_P6_SDIO_USE_IO_0_5_LEN) - 1) << GLB_P6_SDIO_USE_IO_0_5_POS))
+#define GLB_P7_JTAG_USE_IO_2_5         GLB_P7_JTAG_USE_IO_2_5
+#define GLB_P7_JTAG_USE_IO_2_5_POS     (23U)
+#define GLB_P7_JTAG_USE_IO_2_5_LEN     (1U)
+#define GLB_P7_JTAG_USE_IO_2_5_MSK     (((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS)
+#define GLB_P7_JTAG_USE_IO_2_5_UMSK    (~(((1U << GLB_P7_JTAG_USE_IO_2_5_LEN) - 1) << GLB_P7_JTAG_USE_IO_2_5_POS))
+#define GLB_UART_SWAP_SET              GLB_UART_SWAP_SET
+#define GLB_UART_SWAP_SET_POS          (24U)
+#define GLB_UART_SWAP_SET_LEN          (3U)
+#define GLB_UART_SWAP_SET_MSK          (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
+#define GLB_UART_SWAP_SET_UMSK         (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
+
+/* 0x90 : CPU_CLK_CFG */
+#define GLB_CPU_CLK_CFG_OFFSET      (0x90)
+#define GLB_CPU_RTC_DIV             GLB_CPU_RTC_DIV
+#define GLB_CPU_RTC_DIV_POS         (0U)
+#define GLB_CPU_RTC_DIV_LEN         (17U)
+#define GLB_CPU_RTC_DIV_MSK         (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
+#define GLB_CPU_RTC_DIV_UMSK        (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
+#define GLB_CPU_RTC_EN              GLB_CPU_RTC_EN
+#define GLB_CPU_RTC_EN_POS          (18U)
+#define GLB_CPU_RTC_EN_LEN          (1U)
+#define GLB_CPU_RTC_EN_MSK          (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
+#define GLB_CPU_RTC_EN_UMSK         (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
+#define GLB_CPU_RTC_SEL             GLB_CPU_RTC_SEL
+#define GLB_CPU_RTC_SEL_POS         (19U)
+#define GLB_CPU_RTC_SEL_LEN         (1U)
+#define GLB_CPU_RTC_SEL_MSK         (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
+#define GLB_CPU_RTC_SEL_UMSK        (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
+#define GLB_DEBUG_NDRESET_GATE      GLB_DEBUG_NDRESET_GATE
+#define GLB_DEBUG_NDRESET_GATE_POS  (20U)
+#define GLB_DEBUG_NDRESET_GATE_LEN  (1U)
+#define GLB_DEBUG_NDRESET_GATE_MSK  (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
+#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
+
+/* 0xA4 : GPADC_32M_SRC_CTRL */
+#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4)
+#define GLB_GPADC_32M_CLK_DIV         GLB_GPADC_32M_CLK_DIV
+#define GLB_GPADC_32M_CLK_DIV_POS     (0U)
+#define GLB_GPADC_32M_CLK_DIV_LEN     (6U)
+#define GLB_GPADC_32M_CLK_DIV_MSK     (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
+#define GLB_GPADC_32M_CLK_DIV_UMSK    (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
+#define GLB_GPADC_32M_CLK_SEL         GLB_GPADC_32M_CLK_SEL
+#define GLB_GPADC_32M_CLK_SEL_POS     (7U)
+#define GLB_GPADC_32M_CLK_SEL_LEN     (1U)
+#define GLB_GPADC_32M_CLK_SEL_MSK     (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
+#define GLB_GPADC_32M_CLK_SEL_UMSK    (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
+#define GLB_GPADC_32M_DIV_EN          GLB_GPADC_32M_DIV_EN
+#define GLB_GPADC_32M_DIV_EN_POS      (8U)
+#define GLB_GPADC_32M_DIV_EN_LEN      (1U)
+#define GLB_GPADC_32M_DIV_EN_MSK      (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
+#define GLB_GPADC_32M_DIV_EN_UMSK     (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
+
+/* 0xA8 : DIG32K_WAKEUP_CTRL */
+#define GLB_DIG32K_WAKEUP_CTRL_OFFSET   (0xA8)
+#define GLB_DIG_32K_DIV                 GLB_DIG_32K_DIV
+#define GLB_DIG_32K_DIV_POS             (0U)
+#define GLB_DIG_32K_DIV_LEN             (11U)
+#define GLB_DIG_32K_DIV_MSK             (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
+#define GLB_DIG_32K_DIV_UMSK            (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
+#define GLB_DIG_32K_EN                  GLB_DIG_32K_EN
+#define GLB_DIG_32K_EN_POS              (12U)
+#define GLB_DIG_32K_EN_LEN              (1U)
+#define GLB_DIG_32K_EN_MSK              (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
+#define GLB_DIG_32K_EN_UMSK             (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
+#define GLB_DIG_32K_COMP                GLB_DIG_32K_COMP
+#define GLB_DIG_32K_COMP_POS            (13U)
+#define GLB_DIG_32K_COMP_LEN            (1U)
+#define GLB_DIG_32K_COMP_MSK            (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
+#define GLB_DIG_32K_COMP_UMSK           (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
+#define GLB_DIG_512K_DIV                GLB_DIG_512K_DIV
+#define GLB_DIG_512K_DIV_POS            (16U)
+#define GLB_DIG_512K_DIV_LEN            (7U)
+#define GLB_DIG_512K_DIV_MSK            (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
+#define GLB_DIG_512K_DIV_UMSK           (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
+#define GLB_DIG_512K_EN                 GLB_DIG_512K_EN
+#define GLB_DIG_512K_EN_POS             (24U)
+#define GLB_DIG_512K_EN_LEN             (1U)
+#define GLB_DIG_512K_EN_MSK             (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
+#define GLB_DIG_512K_EN_UMSK            (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
+#define GLB_DIG_512K_COMP               GLB_DIG_512K_COMP
+#define GLB_DIG_512K_COMP_POS           (25U)
+#define GLB_DIG_512K_COMP_LEN           (1U)
+#define GLB_DIG_512K_COMP_MSK           (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
+#define GLB_DIG_512K_COMP_UMSK          (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
+#define GLB_DIG_CLK_SRC_SEL             GLB_DIG_CLK_SRC_SEL
+#define GLB_DIG_CLK_SRC_SEL_POS         (28U)
+#define GLB_DIG_CLK_SRC_SEL_LEN         (1U)
+#define GLB_DIG_CLK_SRC_SEL_MSK         (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
+#define GLB_DIG_CLK_SRC_SEL_UMSK        (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
+#define GLB_REG_EN_PLATFORM_WAKEUP      GLB_REG_EN_PLATFORM_WAKEUP
+#define GLB_REG_EN_PLATFORM_WAKEUP_POS  (31U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_LEN  (1U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_MSK  (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)
+#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS))
+
+/* 0xAC : WIFI_BT_COEX_CTRL */
+#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC)
+#define GLB_COEX_BT_CHANNEL          GLB_COEX_BT_CHANNEL
+#define GLB_COEX_BT_CHANNEL_POS      (0U)
+#define GLB_COEX_BT_CHANNEL_LEN      (7U)
+#define GLB_COEX_BT_CHANNEL_MSK      (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
+#define GLB_COEX_BT_CHANNEL_UMSK     (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
+#define GLB_COEX_BT_PTI              GLB_COEX_BT_PTI
+#define GLB_COEX_BT_PTI_POS          (7U)
+#define GLB_COEX_BT_PTI_LEN          (4U)
+#define GLB_COEX_BT_PTI_MSK          (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
+#define GLB_COEX_BT_PTI_UMSK         (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
+#define GLB_COEX_BT_BW               GLB_COEX_BT_BW
+#define GLB_COEX_BT_BW_POS           (11U)
+#define GLB_COEX_BT_BW_LEN           (1U)
+#define GLB_COEX_BT_BW_MSK           (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
+#define GLB_COEX_BT_BW_UMSK          (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
+#define GLB_EN_GPIO_BT_COEX          GLB_EN_GPIO_BT_COEX
+#define GLB_EN_GPIO_BT_COEX_POS      (12U)
+#define GLB_EN_GPIO_BT_COEX_LEN      (1U)
+#define GLB_EN_GPIO_BT_COEX_MSK      (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
+#define GLB_EN_GPIO_BT_COEX_UMSK     (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))
+
+/* 0xC0 : UART_SIG_SEL_0 */
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+#define GLB_UART_SIG_0_SEL        GLB_UART_SIG_0_SEL
+#define GLB_UART_SIG_0_SEL_POS    (0U)
+#define GLB_UART_SIG_0_SEL_LEN    (4U)
+#define GLB_UART_SIG_0_SEL_MSK    (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
+#define GLB_UART_SIG_0_SEL_UMSK   (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
+#define GLB_UART_SIG_1_SEL        GLB_UART_SIG_1_SEL
+#define GLB_UART_SIG_1_SEL_POS    (4U)
+#define GLB_UART_SIG_1_SEL_LEN    (4U)
+#define GLB_UART_SIG_1_SEL_MSK    (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
+#define GLB_UART_SIG_1_SEL_UMSK   (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
+#define GLB_UART_SIG_2_SEL        GLB_UART_SIG_2_SEL
+#define GLB_UART_SIG_2_SEL_POS    (8U)
+#define GLB_UART_SIG_2_SEL_LEN    (4U)
+#define GLB_UART_SIG_2_SEL_MSK    (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
+#define GLB_UART_SIG_2_SEL_UMSK   (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
+#define GLB_UART_SIG_3_SEL        GLB_UART_SIG_3_SEL
+#define GLB_UART_SIG_3_SEL_POS    (12U)
+#define GLB_UART_SIG_3_SEL_LEN    (4U)
+#define GLB_UART_SIG_3_SEL_MSK    (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
+#define GLB_UART_SIG_3_SEL_UMSK   (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
+#define GLB_UART_SIG_4_SEL        GLB_UART_SIG_4_SEL
+#define GLB_UART_SIG_4_SEL_POS    (16U)
+#define GLB_UART_SIG_4_SEL_LEN    (4U)
+#define GLB_UART_SIG_4_SEL_MSK    (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
+#define GLB_UART_SIG_4_SEL_UMSK   (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
+#define GLB_UART_SIG_5_SEL        GLB_UART_SIG_5_SEL
+#define GLB_UART_SIG_5_SEL_POS    (20U)
+#define GLB_UART_SIG_5_SEL_LEN    (4U)
+#define GLB_UART_SIG_5_SEL_MSK    (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
+#define GLB_UART_SIG_5_SEL_UMSK   (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
+#define GLB_UART_SIG_6_SEL        GLB_UART_SIG_6_SEL
+#define GLB_UART_SIG_6_SEL_POS    (24U)
+#define GLB_UART_SIG_6_SEL_LEN    (4U)
+#define GLB_UART_SIG_6_SEL_MSK    (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
+#define GLB_UART_SIG_6_SEL_UMSK   (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
+#define GLB_UART_SIG_7_SEL        GLB_UART_SIG_7_SEL
+#define GLB_UART_SIG_7_SEL_POS    (28U)
+#define GLB_UART_SIG_7_SEL_LEN    (4U)
+#define GLB_UART_SIG_7_SEL_MSK    (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
+#define GLB_UART_SIG_7_SEL_UMSK   (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
+
+/* 0xD0 : DBG_SEL_LL */
+#define GLB_DBG_SEL_LL_OFFSET    (0xD0)
+#define GLB_REG_DBG_LL_CTRL      GLB_REG_DBG_LL_CTRL
+#define GLB_REG_DBG_LL_CTRL_POS  (0U)
+#define GLB_REG_DBG_LL_CTRL_LEN  (32U)
+#define GLB_REG_DBG_LL_CTRL_MSK  (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
+#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
+
+/* 0xD4 : DBG_SEL_LH */
+#define GLB_DBG_SEL_LH_OFFSET    (0xD4)
+#define GLB_REG_DBG_LH_CTRL      GLB_REG_DBG_LH_CTRL
+#define GLB_REG_DBG_LH_CTRL_POS  (0U)
+#define GLB_REG_DBG_LH_CTRL_LEN  (32U)
+#define GLB_REG_DBG_LH_CTRL_MSK  (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
+#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
+
+/* 0xD8 : DBG_SEL_HL */
+#define GLB_DBG_SEL_HL_OFFSET    (0xD8)
+#define GLB_REG_DBG_HL_CTRL      GLB_REG_DBG_HL_CTRL
+#define GLB_REG_DBG_HL_CTRL_POS  (0U)
+#define GLB_REG_DBG_HL_CTRL_LEN  (32U)
+#define GLB_REG_DBG_HL_CTRL_MSK  (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
+#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
+
+/* 0xDC : DBG_SEL_HH */
+#define GLB_DBG_SEL_HH_OFFSET    (0xDC)
+#define GLB_REG_DBG_HH_CTRL      GLB_REG_DBG_HH_CTRL
+#define GLB_REG_DBG_HH_CTRL_POS  (0U)
+#define GLB_REG_DBG_HH_CTRL_LEN  (32U)
+#define GLB_REG_DBG_HH_CTRL_MSK  (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
+#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
+
+/* 0xE0 : debug */
+#define GLB_DEBUG_OFFSET  (0xE0)
+#define GLB_DEBUG_OE      GLB_DEBUG_OE
+#define GLB_DEBUG_OE_POS  (0U)
+#define GLB_DEBUG_OE_LEN  (1U)
+#define GLB_DEBUG_OE_MSK  (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
+#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
+#define GLB_DEBUG_I       GLB_DEBUG_I
+#define GLB_DEBUG_I_POS   (1U)
+#define GLB_DEBUG_I_LEN   (31U)
+#define GLB_DEBUG_I_MSK   (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
+#define GLB_DEBUG_I_UMSK  (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
+
+/* 0x100 : GPIO_CFGCTL0 */
+#define GLB_GPIO_CFGCTL0_OFFSET       (0x100)
+#define GLB_REG_GPIO_0_IE             GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS         (0U)
+#define GLB_REG_GPIO_0_IE_LEN         (1U)
+#define GLB_REG_GPIO_0_IE_MSK         (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK        (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT            GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS        (1U)
+#define GLB_REG_GPIO_0_SMT_LEN        (1U)
+#define GLB_REG_GPIO_0_SMT_MSK        (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK       (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV            GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS        (2U)
+#define GLB_REG_GPIO_0_DRV_LEN        (2U)
+#define GLB_REG_GPIO_0_DRV_MSK        (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK       (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU             GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS         (4U)
+#define GLB_REG_GPIO_0_PU_LEN         (1U)
+#define GLB_REG_GPIO_0_PU_MSK         (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK        (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD             GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS         (5U)
+#define GLB_REG_GPIO_0_PD_LEN         (1U)
+#define GLB_REG_GPIO_0_PD_MSK         (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK        (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL       GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS   (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_0_FUNC_SEL      GLB_REAL_GPIO_0_FUNC_SEL
+#define GLB_REAL_GPIO_0_FUNC_SEL_POS  (12U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE             GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS         (16U)
+#define GLB_REG_GPIO_1_IE_LEN         (1U)
+#define GLB_REG_GPIO_1_IE_MSK         (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK        (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT            GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS        (17U)
+#define GLB_REG_GPIO_1_SMT_LEN        (1U)
+#define GLB_REG_GPIO_1_SMT_MSK        (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK       (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV            GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS        (18U)
+#define GLB_REG_GPIO_1_DRV_LEN        (2U)
+#define GLB_REG_GPIO_1_DRV_MSK        (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK       (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU             GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS         (20U)
+#define GLB_REG_GPIO_1_PU_LEN         (1U)
+#define GLB_REG_GPIO_1_PU_MSK         (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK        (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD             GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS         (21U)
+#define GLB_REG_GPIO_1_PD_LEN         (1U)
+#define GLB_REG_GPIO_1_PD_MSK         (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK        (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL       GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS   (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_1_FUNC_SEL      GLB_REAL_GPIO_1_FUNC_SEL
+#define GLB_REAL_GPIO_1_FUNC_SEL_POS  (28U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS))
+
+/* 0x104 : GPIO_CFGCTL1 */
+#define GLB_GPIO_CFGCTL1_OFFSET       (0x104)
+#define GLB_REG_GPIO_2_IE             GLB_REG_GPIO_2_IE
+#define GLB_REG_GPIO_2_IE_POS         (0U)
+#define GLB_REG_GPIO_2_IE_LEN         (1U)
+#define GLB_REG_GPIO_2_IE_MSK         (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
+#define GLB_REG_GPIO_2_IE_UMSK        (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
+#define GLB_REG_GPIO_2_SMT            GLB_REG_GPIO_2_SMT
+#define GLB_REG_GPIO_2_SMT_POS        (1U)
+#define GLB_REG_GPIO_2_SMT_LEN        (1U)
+#define GLB_REG_GPIO_2_SMT_MSK        (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
+#define GLB_REG_GPIO_2_SMT_UMSK       (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
+#define GLB_REG_GPIO_2_DRV            GLB_REG_GPIO_2_DRV
+#define GLB_REG_GPIO_2_DRV_POS        (2U)
+#define GLB_REG_GPIO_2_DRV_LEN        (2U)
+#define GLB_REG_GPIO_2_DRV_MSK        (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
+#define GLB_REG_GPIO_2_DRV_UMSK       (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
+#define GLB_REG_GPIO_2_PU             GLB_REG_GPIO_2_PU
+#define GLB_REG_GPIO_2_PU_POS         (4U)
+#define GLB_REG_GPIO_2_PU_LEN         (1U)
+#define GLB_REG_GPIO_2_PU_MSK         (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
+#define GLB_REG_GPIO_2_PU_UMSK        (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
+#define GLB_REG_GPIO_2_PD             GLB_REG_GPIO_2_PD
+#define GLB_REG_GPIO_2_PD_POS         (5U)
+#define GLB_REG_GPIO_2_PD_LEN         (1U)
+#define GLB_REG_GPIO_2_PD_MSK         (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
+#define GLB_REG_GPIO_2_PD_UMSK        (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
+#define GLB_REG_GPIO_2_FUNC_SEL       GLB_REG_GPIO_2_FUNC_SEL
+#define GLB_REG_GPIO_2_FUNC_SEL_POS   (8U)
+#define GLB_REG_GPIO_2_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_2_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
+#define GLB_REG_GPIO_2_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_2_FUNC_SEL      GLB_REAL_GPIO_2_FUNC_SEL
+#define GLB_REAL_GPIO_2_FUNC_SEL_POS  (12U)
+#define GLB_REAL_GPIO_2_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_2_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_2_FUNC_SEL_POS))
+#define GLB_REG_GPIO_3_IE             GLB_REG_GPIO_3_IE
+#define GLB_REG_GPIO_3_IE_POS         (16U)
+#define GLB_REG_GPIO_3_IE_LEN         (1U)
+#define GLB_REG_GPIO_3_IE_MSK         (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
+#define GLB_REG_GPIO_3_IE_UMSK        (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
+#define GLB_REG_GPIO_3_SMT            GLB_REG_GPIO_3_SMT
+#define GLB_REG_GPIO_3_SMT_POS        (17U)
+#define GLB_REG_GPIO_3_SMT_LEN        (1U)
+#define GLB_REG_GPIO_3_SMT_MSK        (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
+#define GLB_REG_GPIO_3_SMT_UMSK       (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
+#define GLB_REG_GPIO_3_DRV            GLB_REG_GPIO_3_DRV
+#define GLB_REG_GPIO_3_DRV_POS        (18U)
+#define GLB_REG_GPIO_3_DRV_LEN        (2U)
+#define GLB_REG_GPIO_3_DRV_MSK        (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
+#define GLB_REG_GPIO_3_DRV_UMSK       (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
+#define GLB_REG_GPIO_3_PU             GLB_REG_GPIO_3_PU
+#define GLB_REG_GPIO_3_PU_POS         (20U)
+#define GLB_REG_GPIO_3_PU_LEN         (1U)
+#define GLB_REG_GPIO_3_PU_MSK         (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
+#define GLB_REG_GPIO_3_PU_UMSK        (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
+#define GLB_REG_GPIO_3_PD             GLB_REG_GPIO_3_PD
+#define GLB_REG_GPIO_3_PD_POS         (21U)
+#define GLB_REG_GPIO_3_PD_LEN         (1U)
+#define GLB_REG_GPIO_3_PD_MSK         (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
+#define GLB_REG_GPIO_3_PD_UMSK        (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
+#define GLB_REG_GPIO_3_FUNC_SEL       GLB_REG_GPIO_3_FUNC_SEL
+#define GLB_REG_GPIO_3_FUNC_SEL_POS   (24U)
+#define GLB_REG_GPIO_3_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_3_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
+#define GLB_REG_GPIO_3_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_3_FUNC_SEL      GLB_REAL_GPIO_3_FUNC_SEL
+#define GLB_REAL_GPIO_3_FUNC_SEL_POS  (28U)
+#define GLB_REAL_GPIO_3_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_3_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_3_FUNC_SEL_POS))
+
+/* 0x108 : GPIO_CFGCTL2 */
+#define GLB_GPIO_CFGCTL2_OFFSET       (0x108)
+#define GLB_REG_GPIO_4_IE             GLB_REG_GPIO_4_IE
+#define GLB_REG_GPIO_4_IE_POS         (0U)
+#define GLB_REG_GPIO_4_IE_LEN         (1U)
+#define GLB_REG_GPIO_4_IE_MSK         (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
+#define GLB_REG_GPIO_4_IE_UMSK        (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
+#define GLB_REG_GPIO_4_SMT            GLB_REG_GPIO_4_SMT
+#define GLB_REG_GPIO_4_SMT_POS        (1U)
+#define GLB_REG_GPIO_4_SMT_LEN        (1U)
+#define GLB_REG_GPIO_4_SMT_MSK        (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
+#define GLB_REG_GPIO_4_SMT_UMSK       (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
+#define GLB_REG_GPIO_4_DRV            GLB_REG_GPIO_4_DRV
+#define GLB_REG_GPIO_4_DRV_POS        (2U)
+#define GLB_REG_GPIO_4_DRV_LEN        (2U)
+#define GLB_REG_GPIO_4_DRV_MSK        (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
+#define GLB_REG_GPIO_4_DRV_UMSK       (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
+#define GLB_REG_GPIO_4_PU             GLB_REG_GPIO_4_PU
+#define GLB_REG_GPIO_4_PU_POS         (4U)
+#define GLB_REG_GPIO_4_PU_LEN         (1U)
+#define GLB_REG_GPIO_4_PU_MSK         (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
+#define GLB_REG_GPIO_4_PU_UMSK        (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
+#define GLB_REG_GPIO_4_PD             GLB_REG_GPIO_4_PD
+#define GLB_REG_GPIO_4_PD_POS         (5U)
+#define GLB_REG_GPIO_4_PD_LEN         (1U)
+#define GLB_REG_GPIO_4_PD_MSK         (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
+#define GLB_REG_GPIO_4_PD_UMSK        (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
+#define GLB_REG_GPIO_4_FUNC_SEL       GLB_REG_GPIO_4_FUNC_SEL
+#define GLB_REG_GPIO_4_FUNC_SEL_POS   (8U)
+#define GLB_REG_GPIO_4_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_4_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
+#define GLB_REG_GPIO_4_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_4_FUNC_SEL      GLB_REAL_GPIO_4_FUNC_SEL
+#define GLB_REAL_GPIO_4_FUNC_SEL_POS  (12U)
+#define GLB_REAL_GPIO_4_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_4_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_4_FUNC_SEL_POS))
+#define GLB_REG_GPIO_5_IE             GLB_REG_GPIO_5_IE
+#define GLB_REG_GPIO_5_IE_POS         (16U)
+#define GLB_REG_GPIO_5_IE_LEN         (1U)
+#define GLB_REG_GPIO_5_IE_MSK         (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
+#define GLB_REG_GPIO_5_IE_UMSK        (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
+#define GLB_REG_GPIO_5_SMT            GLB_REG_GPIO_5_SMT
+#define GLB_REG_GPIO_5_SMT_POS        (17U)
+#define GLB_REG_GPIO_5_SMT_LEN        (1U)
+#define GLB_REG_GPIO_5_SMT_MSK        (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
+#define GLB_REG_GPIO_5_SMT_UMSK       (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
+#define GLB_REG_GPIO_5_DRV            GLB_REG_GPIO_5_DRV
+#define GLB_REG_GPIO_5_DRV_POS        (18U)
+#define GLB_REG_GPIO_5_DRV_LEN        (2U)
+#define GLB_REG_GPIO_5_DRV_MSK        (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
+#define GLB_REG_GPIO_5_DRV_UMSK       (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
+#define GLB_REG_GPIO_5_PU             GLB_REG_GPIO_5_PU
+#define GLB_REG_GPIO_5_PU_POS         (20U)
+#define GLB_REG_GPIO_5_PU_LEN         (1U)
+#define GLB_REG_GPIO_5_PU_MSK         (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
+#define GLB_REG_GPIO_5_PU_UMSK        (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
+#define GLB_REG_GPIO_5_PD             GLB_REG_GPIO_5_PD
+#define GLB_REG_GPIO_5_PD_POS         (21U)
+#define GLB_REG_GPIO_5_PD_LEN         (1U)
+#define GLB_REG_GPIO_5_PD_MSK         (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
+#define GLB_REG_GPIO_5_PD_UMSK        (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
+#define GLB_REG_GPIO_5_FUNC_SEL       GLB_REG_GPIO_5_FUNC_SEL
+#define GLB_REG_GPIO_5_FUNC_SEL_POS   (24U)
+#define GLB_REG_GPIO_5_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_5_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
+#define GLB_REG_GPIO_5_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_5_FUNC_SEL      GLB_REAL_GPIO_5_FUNC_SEL
+#define GLB_REAL_GPIO_5_FUNC_SEL_POS  (28U)
+#define GLB_REAL_GPIO_5_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_5_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_5_FUNC_SEL_POS))
+
+/* 0x10C : GPIO_CFGCTL3 */
+#define GLB_GPIO_CFGCTL3_OFFSET      (0x10C)
+#define GLB_REG_GPIO_6_IE            GLB_REG_GPIO_6_IE
+#define GLB_REG_GPIO_6_IE_POS        (0U)
+#define GLB_REG_GPIO_6_IE_LEN        (1U)
+#define GLB_REG_GPIO_6_IE_MSK        (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
+#define GLB_REG_GPIO_6_IE_UMSK       (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
+#define GLB_REG_GPIO_6_SMT           GLB_REG_GPIO_6_SMT
+#define GLB_REG_GPIO_6_SMT_POS       (1U)
+#define GLB_REG_GPIO_6_SMT_LEN       (1U)
+#define GLB_REG_GPIO_6_SMT_MSK       (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
+#define GLB_REG_GPIO_6_SMT_UMSK      (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
+#define GLB_REG_GPIO_6_DRV           GLB_REG_GPIO_6_DRV
+#define GLB_REG_GPIO_6_DRV_POS       (2U)
+#define GLB_REG_GPIO_6_DRV_LEN       (2U)
+#define GLB_REG_GPIO_6_DRV_MSK       (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
+#define GLB_REG_GPIO_6_DRV_UMSK      (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
+#define GLB_REG_GPIO_6_PU            GLB_REG_GPIO_6_PU
+#define GLB_REG_GPIO_6_PU_POS        (4U)
+#define GLB_REG_GPIO_6_PU_LEN        (1U)
+#define GLB_REG_GPIO_6_PU_MSK        (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
+#define GLB_REG_GPIO_6_PU_UMSK       (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
+#define GLB_REG_GPIO_6_PD            GLB_REG_GPIO_6_PD
+#define GLB_REG_GPIO_6_PD_POS        (5U)
+#define GLB_REG_GPIO_6_PD_LEN        (1U)
+#define GLB_REG_GPIO_6_PD_MSK        (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
+#define GLB_REG_GPIO_6_PD_UMSK       (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
+#define GLB_REG_GPIO_6_FUNC_SEL      GLB_REG_GPIO_6_FUNC_SEL
+#define GLB_REG_GPIO_6_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_6_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_6_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
+#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
+#define GLB_REG_GPIO_7_IE            GLB_REG_GPIO_7_IE
+#define GLB_REG_GPIO_7_IE_POS        (16U)
+#define GLB_REG_GPIO_7_IE_LEN        (1U)
+#define GLB_REG_GPIO_7_IE_MSK        (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
+#define GLB_REG_GPIO_7_IE_UMSK       (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
+#define GLB_REG_GPIO_7_SMT           GLB_REG_GPIO_7_SMT
+#define GLB_REG_GPIO_7_SMT_POS       (17U)
+#define GLB_REG_GPIO_7_SMT_LEN       (1U)
+#define GLB_REG_GPIO_7_SMT_MSK       (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
+#define GLB_REG_GPIO_7_SMT_UMSK      (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
+#define GLB_REG_GPIO_7_DRV           GLB_REG_GPIO_7_DRV
+#define GLB_REG_GPIO_7_DRV_POS       (18U)
+#define GLB_REG_GPIO_7_DRV_LEN       (2U)
+#define GLB_REG_GPIO_7_DRV_MSK       (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
+#define GLB_REG_GPIO_7_DRV_UMSK      (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
+#define GLB_REG_GPIO_7_PU            GLB_REG_GPIO_7_PU
+#define GLB_REG_GPIO_7_PU_POS        (20U)
+#define GLB_REG_GPIO_7_PU_LEN        (1U)
+#define GLB_REG_GPIO_7_PU_MSK        (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
+#define GLB_REG_GPIO_7_PU_UMSK       (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
+#define GLB_REG_GPIO_7_PD            GLB_REG_GPIO_7_PD
+#define GLB_REG_GPIO_7_PD_POS        (21U)
+#define GLB_REG_GPIO_7_PD_LEN        (1U)
+#define GLB_REG_GPIO_7_PD_MSK        (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
+#define GLB_REG_GPIO_7_PD_UMSK       (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
+#define GLB_REG_GPIO_7_FUNC_SEL      GLB_REG_GPIO_7_FUNC_SEL
+#define GLB_REG_GPIO_7_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_7_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_7_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
+#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))
+
+/* 0x110 : GPIO_CFGCTL4 */
+#define GLB_GPIO_CFGCTL4_OFFSET      (0x110)
+#define GLB_REG_GPIO_8_IE            GLB_REG_GPIO_8_IE
+#define GLB_REG_GPIO_8_IE_POS        (0U)
+#define GLB_REG_GPIO_8_IE_LEN        (1U)
+#define GLB_REG_GPIO_8_IE_MSK        (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
+#define GLB_REG_GPIO_8_IE_UMSK       (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
+#define GLB_REG_GPIO_8_SMT           GLB_REG_GPIO_8_SMT
+#define GLB_REG_GPIO_8_SMT_POS       (1U)
+#define GLB_REG_GPIO_8_SMT_LEN       (1U)
+#define GLB_REG_GPIO_8_SMT_MSK       (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
+#define GLB_REG_GPIO_8_SMT_UMSK      (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
+#define GLB_REG_GPIO_8_DRV           GLB_REG_GPIO_8_DRV
+#define GLB_REG_GPIO_8_DRV_POS       (2U)
+#define GLB_REG_GPIO_8_DRV_LEN       (2U)
+#define GLB_REG_GPIO_8_DRV_MSK       (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
+#define GLB_REG_GPIO_8_DRV_UMSK      (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
+#define GLB_REG_GPIO_8_PU            GLB_REG_GPIO_8_PU
+#define GLB_REG_GPIO_8_PU_POS        (4U)
+#define GLB_REG_GPIO_8_PU_LEN        (1U)
+#define GLB_REG_GPIO_8_PU_MSK        (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
+#define GLB_REG_GPIO_8_PU_UMSK       (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
+#define GLB_REG_GPIO_8_PD            GLB_REG_GPIO_8_PD
+#define GLB_REG_GPIO_8_PD_POS        (5U)
+#define GLB_REG_GPIO_8_PD_LEN        (1U)
+#define GLB_REG_GPIO_8_PD_MSK        (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
+#define GLB_REG_GPIO_8_PD_UMSK       (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
+#define GLB_REG_GPIO_8_FUNC_SEL      GLB_REG_GPIO_8_FUNC_SEL
+#define GLB_REG_GPIO_8_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_8_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_8_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
+#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
+#define GLB_REG_GPIO_9_IE            GLB_REG_GPIO_9_IE
+#define GLB_REG_GPIO_9_IE_POS        (16U)
+#define GLB_REG_GPIO_9_IE_LEN        (1U)
+#define GLB_REG_GPIO_9_IE_MSK        (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
+#define GLB_REG_GPIO_9_IE_UMSK       (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
+#define GLB_REG_GPIO_9_SMT           GLB_REG_GPIO_9_SMT
+#define GLB_REG_GPIO_9_SMT_POS       (17U)
+#define GLB_REG_GPIO_9_SMT_LEN       (1U)
+#define GLB_REG_GPIO_9_SMT_MSK       (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
+#define GLB_REG_GPIO_9_SMT_UMSK      (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
+#define GLB_REG_GPIO_9_DRV           GLB_REG_GPIO_9_DRV
+#define GLB_REG_GPIO_9_DRV_POS       (18U)
+#define GLB_REG_GPIO_9_DRV_LEN       (2U)
+#define GLB_REG_GPIO_9_DRV_MSK       (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
+#define GLB_REG_GPIO_9_DRV_UMSK      (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
+#define GLB_REG_GPIO_9_PU            GLB_REG_GPIO_9_PU
+#define GLB_REG_GPIO_9_PU_POS        (20U)
+#define GLB_REG_GPIO_9_PU_LEN        (1U)
+#define GLB_REG_GPIO_9_PU_MSK        (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
+#define GLB_REG_GPIO_9_PU_UMSK       (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
+#define GLB_REG_GPIO_9_PD            GLB_REG_GPIO_9_PD
+#define GLB_REG_GPIO_9_PD_POS        (21U)
+#define GLB_REG_GPIO_9_PD_LEN        (1U)
+#define GLB_REG_GPIO_9_PD_MSK        (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
+#define GLB_REG_GPIO_9_PD_UMSK       (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
+#define GLB_REG_GPIO_9_FUNC_SEL      GLB_REG_GPIO_9_FUNC_SEL
+#define GLB_REG_GPIO_9_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_9_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_9_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
+#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))
+
+/* 0x114 : GPIO_CFGCTL5 */
+#define GLB_GPIO_CFGCTL5_OFFSET       (0x114)
+#define GLB_REG_GPIO_10_IE            GLB_REG_GPIO_10_IE
+#define GLB_REG_GPIO_10_IE_POS        (0U)
+#define GLB_REG_GPIO_10_IE_LEN        (1U)
+#define GLB_REG_GPIO_10_IE_MSK        (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
+#define GLB_REG_GPIO_10_IE_UMSK       (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
+#define GLB_REG_GPIO_10_SMT           GLB_REG_GPIO_10_SMT
+#define GLB_REG_GPIO_10_SMT_POS       (1U)
+#define GLB_REG_GPIO_10_SMT_LEN       (1U)
+#define GLB_REG_GPIO_10_SMT_MSK       (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
+#define GLB_REG_GPIO_10_SMT_UMSK      (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
+#define GLB_REG_GPIO_10_DRV           GLB_REG_GPIO_10_DRV
+#define GLB_REG_GPIO_10_DRV_POS       (2U)
+#define GLB_REG_GPIO_10_DRV_LEN       (2U)
+#define GLB_REG_GPIO_10_DRV_MSK       (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
+#define GLB_REG_GPIO_10_DRV_UMSK      (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
+#define GLB_REG_GPIO_10_PU            GLB_REG_GPIO_10_PU
+#define GLB_REG_GPIO_10_PU_POS        (4U)
+#define GLB_REG_GPIO_10_PU_LEN        (1U)
+#define GLB_REG_GPIO_10_PU_MSK        (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
+#define GLB_REG_GPIO_10_PU_UMSK       (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
+#define GLB_REG_GPIO_10_PD            GLB_REG_GPIO_10_PD
+#define GLB_REG_GPIO_10_PD_POS        (5U)
+#define GLB_REG_GPIO_10_PD_LEN        (1U)
+#define GLB_REG_GPIO_10_PD_MSK        (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
+#define GLB_REG_GPIO_10_PD_UMSK       (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
+#define GLB_REG_GPIO_10_FUNC_SEL      GLB_REG_GPIO_10_FUNC_SEL
+#define GLB_REG_GPIO_10_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_10_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_10_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
+#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS))
+#define GLB_REG_GPIO_11_IE            GLB_REG_GPIO_11_IE
+#define GLB_REG_GPIO_11_IE_POS        (16U)
+#define GLB_REG_GPIO_11_IE_LEN        (1U)
+#define GLB_REG_GPIO_11_IE_MSK        (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
+#define GLB_REG_GPIO_11_IE_UMSK       (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
+#define GLB_REG_GPIO_11_SMT           GLB_REG_GPIO_11_SMT
+#define GLB_REG_GPIO_11_SMT_POS       (17U)
+#define GLB_REG_GPIO_11_SMT_LEN       (1U)
+#define GLB_REG_GPIO_11_SMT_MSK       (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
+#define GLB_REG_GPIO_11_SMT_UMSK      (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
+#define GLB_REG_GPIO_11_DRV           GLB_REG_GPIO_11_DRV
+#define GLB_REG_GPIO_11_DRV_POS       (18U)
+#define GLB_REG_GPIO_11_DRV_LEN       (2U)
+#define GLB_REG_GPIO_11_DRV_MSK       (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
+#define GLB_REG_GPIO_11_DRV_UMSK      (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
+#define GLB_REG_GPIO_11_PU            GLB_REG_GPIO_11_PU
+#define GLB_REG_GPIO_11_PU_POS        (20U)
+#define GLB_REG_GPIO_11_PU_LEN        (1U)
+#define GLB_REG_GPIO_11_PU_MSK        (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
+#define GLB_REG_GPIO_11_PU_UMSK       (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
+#define GLB_REG_GPIO_11_PD            GLB_REG_GPIO_11_PD
+#define GLB_REG_GPIO_11_PD_POS        (21U)
+#define GLB_REG_GPIO_11_PD_LEN        (1U)
+#define GLB_REG_GPIO_11_PD_MSK        (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
+#define GLB_REG_GPIO_11_PD_UMSK       (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
+#define GLB_REG_GPIO_11_FUNC_SEL      GLB_REG_GPIO_11_FUNC_SEL
+#define GLB_REG_GPIO_11_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_11_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_11_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
+#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS))
+
+/* 0x118 : GPIO_CFGCTL6 */
+#define GLB_GPIO_CFGCTL6_OFFSET       (0x118)
+#define GLB_REG_GPIO_12_IE            GLB_REG_GPIO_12_IE
+#define GLB_REG_GPIO_12_IE_POS        (0U)
+#define GLB_REG_GPIO_12_IE_LEN        (1U)
+#define GLB_REG_GPIO_12_IE_MSK        (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
+#define GLB_REG_GPIO_12_IE_UMSK       (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
+#define GLB_REG_GPIO_12_SMT           GLB_REG_GPIO_12_SMT
+#define GLB_REG_GPIO_12_SMT_POS       (1U)
+#define GLB_REG_GPIO_12_SMT_LEN       (1U)
+#define GLB_REG_GPIO_12_SMT_MSK       (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
+#define GLB_REG_GPIO_12_SMT_UMSK      (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
+#define GLB_REG_GPIO_12_DRV           GLB_REG_GPIO_12_DRV
+#define GLB_REG_GPIO_12_DRV_POS       (2U)
+#define GLB_REG_GPIO_12_DRV_LEN       (2U)
+#define GLB_REG_GPIO_12_DRV_MSK       (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
+#define GLB_REG_GPIO_12_DRV_UMSK      (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
+#define GLB_REG_GPIO_12_PU            GLB_REG_GPIO_12_PU
+#define GLB_REG_GPIO_12_PU_POS        (4U)
+#define GLB_REG_GPIO_12_PU_LEN        (1U)
+#define GLB_REG_GPIO_12_PU_MSK        (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
+#define GLB_REG_GPIO_12_PU_UMSK       (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
+#define GLB_REG_GPIO_12_PD            GLB_REG_GPIO_12_PD
+#define GLB_REG_GPIO_12_PD_POS        (5U)
+#define GLB_REG_GPIO_12_PD_LEN        (1U)
+#define GLB_REG_GPIO_12_PD_MSK        (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
+#define GLB_REG_GPIO_12_PD_UMSK       (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
+#define GLB_REG_GPIO_12_FUNC_SEL      GLB_REG_GPIO_12_FUNC_SEL
+#define GLB_REG_GPIO_12_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_12_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_12_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
+#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS))
+#define GLB_REG_GPIO_13_IE            GLB_REG_GPIO_13_IE
+#define GLB_REG_GPIO_13_IE_POS        (16U)
+#define GLB_REG_GPIO_13_IE_LEN        (1U)
+#define GLB_REG_GPIO_13_IE_MSK        (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
+#define GLB_REG_GPIO_13_IE_UMSK       (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
+#define GLB_REG_GPIO_13_SMT           GLB_REG_GPIO_13_SMT
+#define GLB_REG_GPIO_13_SMT_POS       (17U)
+#define GLB_REG_GPIO_13_SMT_LEN       (1U)
+#define GLB_REG_GPIO_13_SMT_MSK       (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
+#define GLB_REG_GPIO_13_SMT_UMSK      (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
+#define GLB_REG_GPIO_13_DRV           GLB_REG_GPIO_13_DRV
+#define GLB_REG_GPIO_13_DRV_POS       (18U)
+#define GLB_REG_GPIO_13_DRV_LEN       (2U)
+#define GLB_REG_GPIO_13_DRV_MSK       (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
+#define GLB_REG_GPIO_13_DRV_UMSK      (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
+#define GLB_REG_GPIO_13_PU            GLB_REG_GPIO_13_PU
+#define GLB_REG_GPIO_13_PU_POS        (20U)
+#define GLB_REG_GPIO_13_PU_LEN        (1U)
+#define GLB_REG_GPIO_13_PU_MSK        (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
+#define GLB_REG_GPIO_13_PU_UMSK       (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
+#define GLB_REG_GPIO_13_PD            GLB_REG_GPIO_13_PD
+#define GLB_REG_GPIO_13_PD_POS        (21U)
+#define GLB_REG_GPIO_13_PD_LEN        (1U)
+#define GLB_REG_GPIO_13_PD_MSK        (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
+#define GLB_REG_GPIO_13_PD_UMSK       (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
+#define GLB_REG_GPIO_13_FUNC_SEL      GLB_REG_GPIO_13_FUNC_SEL
+#define GLB_REG_GPIO_13_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_13_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_13_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
+#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS))
+
+/* 0x11C : GPIO_CFGCTL7 */
+#define GLB_GPIO_CFGCTL7_OFFSET       (0x11C)
+#define GLB_REG_GPIO_14_IE            GLB_REG_GPIO_14_IE
+#define GLB_REG_GPIO_14_IE_POS        (0U)
+#define GLB_REG_GPIO_14_IE_LEN        (1U)
+#define GLB_REG_GPIO_14_IE_MSK        (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
+#define GLB_REG_GPIO_14_IE_UMSK       (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
+#define GLB_REG_GPIO_14_SMT           GLB_REG_GPIO_14_SMT
+#define GLB_REG_GPIO_14_SMT_POS       (1U)
+#define GLB_REG_GPIO_14_SMT_LEN       (1U)
+#define GLB_REG_GPIO_14_SMT_MSK       (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
+#define GLB_REG_GPIO_14_SMT_UMSK      (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
+#define GLB_REG_GPIO_14_DRV           GLB_REG_GPIO_14_DRV
+#define GLB_REG_GPIO_14_DRV_POS       (2U)
+#define GLB_REG_GPIO_14_DRV_LEN       (2U)
+#define GLB_REG_GPIO_14_DRV_MSK       (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
+#define GLB_REG_GPIO_14_DRV_UMSK      (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
+#define GLB_REG_GPIO_14_PU            GLB_REG_GPIO_14_PU
+#define GLB_REG_GPIO_14_PU_POS        (4U)
+#define GLB_REG_GPIO_14_PU_LEN        (1U)
+#define GLB_REG_GPIO_14_PU_MSK        (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
+#define GLB_REG_GPIO_14_PU_UMSK       (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
+#define GLB_REG_GPIO_14_PD            GLB_REG_GPIO_14_PD
+#define GLB_REG_GPIO_14_PD_POS        (5U)
+#define GLB_REG_GPIO_14_PD_LEN        (1U)
+#define GLB_REG_GPIO_14_PD_MSK        (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
+#define GLB_REG_GPIO_14_PD_UMSK       (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
+#define GLB_REG_GPIO_14_FUNC_SEL      GLB_REG_GPIO_14_FUNC_SEL
+#define GLB_REG_GPIO_14_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_14_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_14_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
+#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS))
+#define GLB_REG_GPIO_15_IE            GLB_REG_GPIO_15_IE
+#define GLB_REG_GPIO_15_IE_POS        (16U)
+#define GLB_REG_GPIO_15_IE_LEN        (1U)
+#define GLB_REG_GPIO_15_IE_MSK        (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
+#define GLB_REG_GPIO_15_IE_UMSK       (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
+#define GLB_REG_GPIO_15_SMT           GLB_REG_GPIO_15_SMT
+#define GLB_REG_GPIO_15_SMT_POS       (17U)
+#define GLB_REG_GPIO_15_SMT_LEN       (1U)
+#define GLB_REG_GPIO_15_SMT_MSK       (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
+#define GLB_REG_GPIO_15_SMT_UMSK      (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
+#define GLB_REG_GPIO_15_DRV           GLB_REG_GPIO_15_DRV
+#define GLB_REG_GPIO_15_DRV_POS       (18U)
+#define GLB_REG_GPIO_15_DRV_LEN       (2U)
+#define GLB_REG_GPIO_15_DRV_MSK       (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
+#define GLB_REG_GPIO_15_DRV_UMSK      (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
+#define GLB_REG_GPIO_15_PU            GLB_REG_GPIO_15_PU
+#define GLB_REG_GPIO_15_PU_POS        (20U)
+#define GLB_REG_GPIO_15_PU_LEN        (1U)
+#define GLB_REG_GPIO_15_PU_MSK        (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
+#define GLB_REG_GPIO_15_PU_UMSK       (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
+#define GLB_REG_GPIO_15_PD            GLB_REG_GPIO_15_PD
+#define GLB_REG_GPIO_15_PD_POS        (21U)
+#define GLB_REG_GPIO_15_PD_LEN        (1U)
+#define GLB_REG_GPIO_15_PD_MSK        (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
+#define GLB_REG_GPIO_15_PD_UMSK       (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
+#define GLB_REG_GPIO_15_FUNC_SEL      GLB_REG_GPIO_15_FUNC_SEL
+#define GLB_REG_GPIO_15_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_15_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_15_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
+#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS))
+
+/* 0x120 : GPIO_CFGCTL8 */
+#define GLB_GPIO_CFGCTL8_OFFSET       (0x120)
+#define GLB_REG_GPIO_16_IE            GLB_REG_GPIO_16_IE
+#define GLB_REG_GPIO_16_IE_POS        (0U)
+#define GLB_REG_GPIO_16_IE_LEN        (1U)
+#define GLB_REG_GPIO_16_IE_MSK        (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
+#define GLB_REG_GPIO_16_IE_UMSK       (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
+#define GLB_REG_GPIO_16_SMT           GLB_REG_GPIO_16_SMT
+#define GLB_REG_GPIO_16_SMT_POS       (1U)
+#define GLB_REG_GPIO_16_SMT_LEN       (1U)
+#define GLB_REG_GPIO_16_SMT_MSK       (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
+#define GLB_REG_GPIO_16_SMT_UMSK      (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
+#define GLB_REG_GPIO_16_DRV           GLB_REG_GPIO_16_DRV
+#define GLB_REG_GPIO_16_DRV_POS       (2U)
+#define GLB_REG_GPIO_16_DRV_LEN       (2U)
+#define GLB_REG_GPIO_16_DRV_MSK       (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
+#define GLB_REG_GPIO_16_DRV_UMSK      (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
+#define GLB_REG_GPIO_16_PU            GLB_REG_GPIO_16_PU
+#define GLB_REG_GPIO_16_PU_POS        (4U)
+#define GLB_REG_GPIO_16_PU_LEN        (1U)
+#define GLB_REG_GPIO_16_PU_MSK        (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
+#define GLB_REG_GPIO_16_PU_UMSK       (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
+#define GLB_REG_GPIO_16_PD            GLB_REG_GPIO_16_PD
+#define GLB_REG_GPIO_16_PD_POS        (5U)
+#define GLB_REG_GPIO_16_PD_LEN        (1U)
+#define GLB_REG_GPIO_16_PD_MSK        (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
+#define GLB_REG_GPIO_16_PD_UMSK       (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
+#define GLB_REG_GPIO_16_FUNC_SEL      GLB_REG_GPIO_16_FUNC_SEL
+#define GLB_REG_GPIO_16_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_16_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_16_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
+#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS))
+#define GLB_REG_GPIO_17_IE            GLB_REG_GPIO_17_IE
+#define GLB_REG_GPIO_17_IE_POS        (16U)
+#define GLB_REG_GPIO_17_IE_LEN        (1U)
+#define GLB_REG_GPIO_17_IE_MSK        (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
+#define GLB_REG_GPIO_17_IE_UMSK       (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
+#define GLB_REG_GPIO_17_SMT           GLB_REG_GPIO_17_SMT
+#define GLB_REG_GPIO_17_SMT_POS       (17U)
+#define GLB_REG_GPIO_17_SMT_LEN       (1U)
+#define GLB_REG_GPIO_17_SMT_MSK       (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
+#define GLB_REG_GPIO_17_SMT_UMSK      (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
+#define GLB_REG_GPIO_17_DRV           GLB_REG_GPIO_17_DRV
+#define GLB_REG_GPIO_17_DRV_POS       (18U)
+#define GLB_REG_GPIO_17_DRV_LEN       (2U)
+#define GLB_REG_GPIO_17_DRV_MSK       (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
+#define GLB_REG_GPIO_17_DRV_UMSK      (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
+#define GLB_REG_GPIO_17_PU            GLB_REG_GPIO_17_PU
+#define GLB_REG_GPIO_17_PU_POS        (20U)
+#define GLB_REG_GPIO_17_PU_LEN        (1U)
+#define GLB_REG_GPIO_17_PU_MSK        (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
+#define GLB_REG_GPIO_17_PU_UMSK       (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
+#define GLB_REG_GPIO_17_PD            GLB_REG_GPIO_17_PD
+#define GLB_REG_GPIO_17_PD_POS        (21U)
+#define GLB_REG_GPIO_17_PD_LEN        (1U)
+#define GLB_REG_GPIO_17_PD_MSK        (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
+#define GLB_REG_GPIO_17_PD_UMSK       (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
+#define GLB_REG_GPIO_17_FUNC_SEL      GLB_REG_GPIO_17_FUNC_SEL
+#define GLB_REG_GPIO_17_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_17_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_17_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
+#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS))
+
+/* 0x124 : GPIO_CFGCTL9 */
+#define GLB_GPIO_CFGCTL9_OFFSET       (0x124)
+#define GLB_REG_GPIO_18_IE            GLB_REG_GPIO_18_IE
+#define GLB_REG_GPIO_18_IE_POS        (0U)
+#define GLB_REG_GPIO_18_IE_LEN        (1U)
+#define GLB_REG_GPIO_18_IE_MSK        (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
+#define GLB_REG_GPIO_18_IE_UMSK       (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
+#define GLB_REG_GPIO_18_SMT           GLB_REG_GPIO_18_SMT
+#define GLB_REG_GPIO_18_SMT_POS       (1U)
+#define GLB_REG_GPIO_18_SMT_LEN       (1U)
+#define GLB_REG_GPIO_18_SMT_MSK       (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
+#define GLB_REG_GPIO_18_SMT_UMSK      (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
+#define GLB_REG_GPIO_18_DRV           GLB_REG_GPIO_18_DRV
+#define GLB_REG_GPIO_18_DRV_POS       (2U)
+#define GLB_REG_GPIO_18_DRV_LEN       (2U)
+#define GLB_REG_GPIO_18_DRV_MSK       (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
+#define GLB_REG_GPIO_18_DRV_UMSK      (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
+#define GLB_REG_GPIO_18_PU            GLB_REG_GPIO_18_PU
+#define GLB_REG_GPIO_18_PU_POS        (4U)
+#define GLB_REG_GPIO_18_PU_LEN        (1U)
+#define GLB_REG_GPIO_18_PU_MSK        (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
+#define GLB_REG_GPIO_18_PU_UMSK       (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
+#define GLB_REG_GPIO_18_PD            GLB_REG_GPIO_18_PD
+#define GLB_REG_GPIO_18_PD_POS        (5U)
+#define GLB_REG_GPIO_18_PD_LEN        (1U)
+#define GLB_REG_GPIO_18_PD_MSK        (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
+#define GLB_REG_GPIO_18_PD_UMSK       (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
+#define GLB_REG_GPIO_18_FUNC_SEL      GLB_REG_GPIO_18_FUNC_SEL
+#define GLB_REG_GPIO_18_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_18_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_18_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
+#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS))
+#define GLB_REG_GPIO_19_IE            GLB_REG_GPIO_19_IE
+#define GLB_REG_GPIO_19_IE_POS        (16U)
+#define GLB_REG_GPIO_19_IE_LEN        (1U)
+#define GLB_REG_GPIO_19_IE_MSK        (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
+#define GLB_REG_GPIO_19_IE_UMSK       (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
+#define GLB_REG_GPIO_19_SMT           GLB_REG_GPIO_19_SMT
+#define GLB_REG_GPIO_19_SMT_POS       (17U)
+#define GLB_REG_GPIO_19_SMT_LEN       (1U)
+#define GLB_REG_GPIO_19_SMT_MSK       (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
+#define GLB_REG_GPIO_19_SMT_UMSK      (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
+#define GLB_REG_GPIO_19_DRV           GLB_REG_GPIO_19_DRV
+#define GLB_REG_GPIO_19_DRV_POS       (18U)
+#define GLB_REG_GPIO_19_DRV_LEN       (2U)
+#define GLB_REG_GPIO_19_DRV_MSK       (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
+#define GLB_REG_GPIO_19_DRV_UMSK      (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
+#define GLB_REG_GPIO_19_PU            GLB_REG_GPIO_19_PU
+#define GLB_REG_GPIO_19_PU_POS        (20U)
+#define GLB_REG_GPIO_19_PU_LEN        (1U)
+#define GLB_REG_GPIO_19_PU_MSK        (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
+#define GLB_REG_GPIO_19_PU_UMSK       (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
+#define GLB_REG_GPIO_19_PD            GLB_REG_GPIO_19_PD
+#define GLB_REG_GPIO_19_PD_POS        (21U)
+#define GLB_REG_GPIO_19_PD_LEN        (1U)
+#define GLB_REG_GPIO_19_PD_MSK        (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
+#define GLB_REG_GPIO_19_PD_UMSK       (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
+#define GLB_REG_GPIO_19_FUNC_SEL      GLB_REG_GPIO_19_FUNC_SEL
+#define GLB_REG_GPIO_19_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_19_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_19_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
+#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS))
+
+/* 0x128 : GPIO_CFGCTL10 */
+#define GLB_GPIO_CFGCTL10_OFFSET      (0x128)
+#define GLB_REG_GPIO_20_IE            GLB_REG_GPIO_20_IE
+#define GLB_REG_GPIO_20_IE_POS        (0U)
+#define GLB_REG_GPIO_20_IE_LEN        (1U)
+#define GLB_REG_GPIO_20_IE_MSK        (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
+#define GLB_REG_GPIO_20_IE_UMSK       (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
+#define GLB_REG_GPIO_20_SMT           GLB_REG_GPIO_20_SMT
+#define GLB_REG_GPIO_20_SMT_POS       (1U)
+#define GLB_REG_GPIO_20_SMT_LEN       (1U)
+#define GLB_REG_GPIO_20_SMT_MSK       (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
+#define GLB_REG_GPIO_20_SMT_UMSK      (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
+#define GLB_REG_GPIO_20_DRV           GLB_REG_GPIO_20_DRV
+#define GLB_REG_GPIO_20_DRV_POS       (2U)
+#define GLB_REG_GPIO_20_DRV_LEN       (2U)
+#define GLB_REG_GPIO_20_DRV_MSK       (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
+#define GLB_REG_GPIO_20_DRV_UMSK      (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
+#define GLB_REG_GPIO_20_PU            GLB_REG_GPIO_20_PU
+#define GLB_REG_GPIO_20_PU_POS        (4U)
+#define GLB_REG_GPIO_20_PU_LEN        (1U)
+#define GLB_REG_GPIO_20_PU_MSK        (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
+#define GLB_REG_GPIO_20_PU_UMSK       (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
+#define GLB_REG_GPIO_20_PD            GLB_REG_GPIO_20_PD
+#define GLB_REG_GPIO_20_PD_POS        (5U)
+#define GLB_REG_GPIO_20_PD_LEN        (1U)
+#define GLB_REG_GPIO_20_PD_MSK        (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
+#define GLB_REG_GPIO_20_PD_UMSK       (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
+#define GLB_REG_GPIO_20_FUNC_SEL      GLB_REG_GPIO_20_FUNC_SEL
+#define GLB_REG_GPIO_20_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_20_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_20_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
+#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS))
+#define GLB_REG_GPIO_21_IE            GLB_REG_GPIO_21_IE
+#define GLB_REG_GPIO_21_IE_POS        (16U)
+#define GLB_REG_GPIO_21_IE_LEN        (1U)
+#define GLB_REG_GPIO_21_IE_MSK        (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
+#define GLB_REG_GPIO_21_IE_UMSK       (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
+#define GLB_REG_GPIO_21_SMT           GLB_REG_GPIO_21_SMT
+#define GLB_REG_GPIO_21_SMT_POS       (17U)
+#define GLB_REG_GPIO_21_SMT_LEN       (1U)
+#define GLB_REG_GPIO_21_SMT_MSK       (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
+#define GLB_REG_GPIO_21_SMT_UMSK      (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
+#define GLB_REG_GPIO_21_DRV           GLB_REG_GPIO_21_DRV
+#define GLB_REG_GPIO_21_DRV_POS       (18U)
+#define GLB_REG_GPIO_21_DRV_LEN       (2U)
+#define GLB_REG_GPIO_21_DRV_MSK       (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
+#define GLB_REG_GPIO_21_DRV_UMSK      (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
+#define GLB_REG_GPIO_21_PU            GLB_REG_GPIO_21_PU
+#define GLB_REG_GPIO_21_PU_POS        (20U)
+#define GLB_REG_GPIO_21_PU_LEN        (1U)
+#define GLB_REG_GPIO_21_PU_MSK        (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
+#define GLB_REG_GPIO_21_PU_UMSK       (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
+#define GLB_REG_GPIO_21_PD            GLB_REG_GPIO_21_PD
+#define GLB_REG_GPIO_21_PD_POS        (21U)
+#define GLB_REG_GPIO_21_PD_LEN        (1U)
+#define GLB_REG_GPIO_21_PD_MSK        (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
+#define GLB_REG_GPIO_21_PD_UMSK       (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
+#define GLB_REG_GPIO_21_FUNC_SEL      GLB_REG_GPIO_21_FUNC_SEL
+#define GLB_REG_GPIO_21_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_21_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_21_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
+#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS))
+
+/* 0x12C : GPIO_CFGCTL11 */
+#define GLB_GPIO_CFGCTL11_OFFSET      (0x12C)
+#define GLB_REG_GPIO_22_IE            GLB_REG_GPIO_22_IE
+#define GLB_REG_GPIO_22_IE_POS        (0U)
+#define GLB_REG_GPIO_22_IE_LEN        (1U)
+#define GLB_REG_GPIO_22_IE_MSK        (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
+#define GLB_REG_GPIO_22_IE_UMSK       (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
+#define GLB_REG_GPIO_22_SMT           GLB_REG_GPIO_22_SMT
+#define GLB_REG_GPIO_22_SMT_POS       (1U)
+#define GLB_REG_GPIO_22_SMT_LEN       (1U)
+#define GLB_REG_GPIO_22_SMT_MSK       (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
+#define GLB_REG_GPIO_22_SMT_UMSK      (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
+#define GLB_REG_GPIO_22_DRV           GLB_REG_GPIO_22_DRV
+#define GLB_REG_GPIO_22_DRV_POS       (2U)
+#define GLB_REG_GPIO_22_DRV_LEN       (2U)
+#define GLB_REG_GPIO_22_DRV_MSK       (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
+#define GLB_REG_GPIO_22_DRV_UMSK      (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
+#define GLB_REG_GPIO_22_PU            GLB_REG_GPIO_22_PU
+#define GLB_REG_GPIO_22_PU_POS        (4U)
+#define GLB_REG_GPIO_22_PU_LEN        (1U)
+#define GLB_REG_GPIO_22_PU_MSK        (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
+#define GLB_REG_GPIO_22_PU_UMSK       (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
+#define GLB_REG_GPIO_22_PD            GLB_REG_GPIO_22_PD
+#define GLB_REG_GPIO_22_PD_POS        (5U)
+#define GLB_REG_GPIO_22_PD_LEN        (1U)
+#define GLB_REG_GPIO_22_PD_MSK        (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
+#define GLB_REG_GPIO_22_PD_UMSK       (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
+#define GLB_REG_GPIO_22_FUNC_SEL      GLB_REG_GPIO_22_FUNC_SEL
+#define GLB_REG_GPIO_22_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_22_FUNC_SEL_LEN  (4U)
+#define GLB_REG_GPIO_22_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
+#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS))
+#define GLB_REG_GPIO_23_IE            GLB_REG_GPIO_23_IE
+#define GLB_REG_GPIO_23_IE_POS        (16U)
+#define GLB_REG_GPIO_23_IE_LEN        (1U)
+#define GLB_REG_GPIO_23_IE_MSK        (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
+#define GLB_REG_GPIO_23_IE_UMSK       (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
+#define GLB_REG_GPIO_23_SMT           GLB_REG_GPIO_23_SMT
+#define GLB_REG_GPIO_23_SMT_POS       (17U)
+#define GLB_REG_GPIO_23_SMT_LEN       (1U)
+#define GLB_REG_GPIO_23_SMT_MSK       (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
+#define GLB_REG_GPIO_23_SMT_UMSK      (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
+#define GLB_REG_GPIO_23_DRV           GLB_REG_GPIO_23_DRV
+#define GLB_REG_GPIO_23_DRV_POS       (18U)
+#define GLB_REG_GPIO_23_DRV_LEN       (2U)
+#define GLB_REG_GPIO_23_DRV_MSK       (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
+#define GLB_REG_GPIO_23_DRV_UMSK      (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
+#define GLB_REG_GPIO_23_PU            GLB_REG_GPIO_23_PU
+#define GLB_REG_GPIO_23_PU_POS        (20U)
+#define GLB_REG_GPIO_23_PU_LEN        (1U)
+#define GLB_REG_GPIO_23_PU_MSK        (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
+#define GLB_REG_GPIO_23_PU_UMSK       (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
+#define GLB_REG_GPIO_23_PD            GLB_REG_GPIO_23_PD
+#define GLB_REG_GPIO_23_PD_POS        (21U)
+#define GLB_REG_GPIO_23_PD_LEN        (1U)
+#define GLB_REG_GPIO_23_PD_MSK        (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
+#define GLB_REG_GPIO_23_PD_UMSK       (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
+
+/* 0x130 : GPIO_CFGCTL12 */
+#define GLB_GPIO_CFGCTL12_OFFSET (0x130)
+#define GLB_REG_GPIO_24_IE       GLB_REG_GPIO_24_IE
+#define GLB_REG_GPIO_24_IE_POS   (0U)
+#define GLB_REG_GPIO_24_IE_LEN   (1U)
+#define GLB_REG_GPIO_24_IE_MSK   (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
+#define GLB_REG_GPIO_24_IE_UMSK  (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
+#define GLB_REG_GPIO_24_SMT      GLB_REG_GPIO_24_SMT
+#define GLB_REG_GPIO_24_SMT_POS  (1U)
+#define GLB_REG_GPIO_24_SMT_LEN  (1U)
+#define GLB_REG_GPIO_24_SMT_MSK  (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
+#define GLB_REG_GPIO_24_SMT_UMSK (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
+#define GLB_REG_GPIO_24_DRV      GLB_REG_GPIO_24_DRV
+#define GLB_REG_GPIO_24_DRV_POS  (2U)
+#define GLB_REG_GPIO_24_DRV_LEN  (2U)
+#define GLB_REG_GPIO_24_DRV_MSK  (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
+#define GLB_REG_GPIO_24_DRV_UMSK (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
+#define GLB_REG_GPIO_24_PU       GLB_REG_GPIO_24_PU
+#define GLB_REG_GPIO_24_PU_POS   (4U)
+#define GLB_REG_GPIO_24_PU_LEN   (1U)
+#define GLB_REG_GPIO_24_PU_MSK   (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
+#define GLB_REG_GPIO_24_PU_UMSK  (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
+#define GLB_REG_GPIO_24_PD       GLB_REG_GPIO_24_PD
+#define GLB_REG_GPIO_24_PD_POS   (5U)
+#define GLB_REG_GPIO_24_PD_LEN   (1U)
+#define GLB_REG_GPIO_24_PD_MSK   (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
+#define GLB_REG_GPIO_24_PD_UMSK  (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
+#define GLB_REG_GPIO_25_IE       GLB_REG_GPIO_25_IE
+#define GLB_REG_GPIO_25_IE_POS   (16U)
+#define GLB_REG_GPIO_25_IE_LEN   (1U)
+#define GLB_REG_GPIO_25_IE_MSK   (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
+#define GLB_REG_GPIO_25_IE_UMSK  (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
+#define GLB_REG_GPIO_25_SMT      GLB_REG_GPIO_25_SMT
+#define GLB_REG_GPIO_25_SMT_POS  (17U)
+#define GLB_REG_GPIO_25_SMT_LEN  (1U)
+#define GLB_REG_GPIO_25_SMT_MSK  (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
+#define GLB_REG_GPIO_25_SMT_UMSK (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
+#define GLB_REG_GPIO_25_DRV      GLB_REG_GPIO_25_DRV
+#define GLB_REG_GPIO_25_DRV_POS  (18U)
+#define GLB_REG_GPIO_25_DRV_LEN  (2U)
+#define GLB_REG_GPIO_25_DRV_MSK  (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
+#define GLB_REG_GPIO_25_DRV_UMSK (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
+#define GLB_REG_GPIO_25_PU       GLB_REG_GPIO_25_PU
+#define GLB_REG_GPIO_25_PU_POS   (20U)
+#define GLB_REG_GPIO_25_PU_LEN   (1U)
+#define GLB_REG_GPIO_25_PU_MSK   (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
+#define GLB_REG_GPIO_25_PU_UMSK  (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
+#define GLB_REG_GPIO_25_PD       GLB_REG_GPIO_25_PD
+#define GLB_REG_GPIO_25_PD_POS   (21U)
+#define GLB_REG_GPIO_25_PD_LEN   (1U)
+#define GLB_REG_GPIO_25_PD_MSK   (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
+#define GLB_REG_GPIO_25_PD_UMSK  (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
+
+/* 0x134 : GPIO_CFGCTL13 */
+#define GLB_GPIO_CFGCTL13_OFFSET (0x134)
+#define GLB_REG_GPIO_26_IE       GLB_REG_GPIO_26_IE
+#define GLB_REG_GPIO_26_IE_POS   (0U)
+#define GLB_REG_GPIO_26_IE_LEN   (1U)
+#define GLB_REG_GPIO_26_IE_MSK   (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
+#define GLB_REG_GPIO_26_IE_UMSK  (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
+#define GLB_REG_GPIO_26_SMT      GLB_REG_GPIO_26_SMT
+#define GLB_REG_GPIO_26_SMT_POS  (1U)
+#define GLB_REG_GPIO_26_SMT_LEN  (1U)
+#define GLB_REG_GPIO_26_SMT_MSK  (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
+#define GLB_REG_GPIO_26_SMT_UMSK (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
+#define GLB_REG_GPIO_26_DRV      GLB_REG_GPIO_26_DRV
+#define GLB_REG_GPIO_26_DRV_POS  (2U)
+#define GLB_REG_GPIO_26_DRV_LEN  (2U)
+#define GLB_REG_GPIO_26_DRV_MSK  (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
+#define GLB_REG_GPIO_26_DRV_UMSK (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
+#define GLB_REG_GPIO_26_PU       GLB_REG_GPIO_26_PU
+#define GLB_REG_GPIO_26_PU_POS   (4U)
+#define GLB_REG_GPIO_26_PU_LEN   (1U)
+#define GLB_REG_GPIO_26_PU_MSK   (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
+#define GLB_REG_GPIO_26_PU_UMSK  (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
+#define GLB_REG_GPIO_26_PD       GLB_REG_GPIO_26_PD
+#define GLB_REG_GPIO_26_PD_POS   (5U)
+#define GLB_REG_GPIO_26_PD_LEN   (1U)
+#define GLB_REG_GPIO_26_PD_MSK   (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
+#define GLB_REG_GPIO_26_PD_UMSK  (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
+#define GLB_REG_GPIO_27_IE       GLB_REG_GPIO_27_IE
+#define GLB_REG_GPIO_27_IE_POS   (16U)
+#define GLB_REG_GPIO_27_IE_LEN   (1U)
+#define GLB_REG_GPIO_27_IE_MSK   (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
+#define GLB_REG_GPIO_27_IE_UMSK  (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
+#define GLB_REG_GPIO_27_SMT      GLB_REG_GPIO_27_SMT
+#define GLB_REG_GPIO_27_SMT_POS  (17U)
+#define GLB_REG_GPIO_27_SMT_LEN  (1U)
+#define GLB_REG_GPIO_27_SMT_MSK  (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
+#define GLB_REG_GPIO_27_SMT_UMSK (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
+#define GLB_REG_GPIO_27_DRV      GLB_REG_GPIO_27_DRV
+#define GLB_REG_GPIO_27_DRV_POS  (18U)
+#define GLB_REG_GPIO_27_DRV_LEN  (2U)
+#define GLB_REG_GPIO_27_DRV_MSK  (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
+#define GLB_REG_GPIO_27_DRV_UMSK (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
+#define GLB_REG_GPIO_27_PU       GLB_REG_GPIO_27_PU
+#define GLB_REG_GPIO_27_PU_POS   (20U)
+#define GLB_REG_GPIO_27_PU_LEN   (1U)
+#define GLB_REG_GPIO_27_PU_MSK   (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
+#define GLB_REG_GPIO_27_PU_UMSK  (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
+#define GLB_REG_GPIO_27_PD       GLB_REG_GPIO_27_PD
+#define GLB_REG_GPIO_27_PD_POS   (21U)
+#define GLB_REG_GPIO_27_PD_LEN   (1U)
+#define GLB_REG_GPIO_27_PD_MSK   (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
+#define GLB_REG_GPIO_27_PD_UMSK  (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
+
+/* 0x138 : GPIO_CFGCTL14 */
+#define GLB_GPIO_CFGCTL14_OFFSET (0x138)
+#define GLB_REG_GPIO_28_IE       GLB_REG_GPIO_28_IE
+#define GLB_REG_GPIO_28_IE_POS   (0U)
+#define GLB_REG_GPIO_28_IE_LEN   (1U)
+#define GLB_REG_GPIO_28_IE_MSK   (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
+#define GLB_REG_GPIO_28_IE_UMSK  (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
+#define GLB_REG_GPIO_28_SMT      GLB_REG_GPIO_28_SMT
+#define GLB_REG_GPIO_28_SMT_POS  (1U)
+#define GLB_REG_GPIO_28_SMT_LEN  (1U)
+#define GLB_REG_GPIO_28_SMT_MSK  (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
+#define GLB_REG_GPIO_28_SMT_UMSK (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
+#define GLB_REG_GPIO_28_DRV      GLB_REG_GPIO_28_DRV
+#define GLB_REG_GPIO_28_DRV_POS  (2U)
+#define GLB_REG_GPIO_28_DRV_LEN  (2U)
+#define GLB_REG_GPIO_28_DRV_MSK  (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
+#define GLB_REG_GPIO_28_DRV_UMSK (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
+#define GLB_REG_GPIO_28_PU       GLB_REG_GPIO_28_PU
+#define GLB_REG_GPIO_28_PU_POS   (4U)
+#define GLB_REG_GPIO_28_PU_LEN   (1U)
+#define GLB_REG_GPIO_28_PU_MSK   (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
+#define GLB_REG_GPIO_28_PU_UMSK  (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
+#define GLB_REG_GPIO_28_PD       GLB_REG_GPIO_28_PD
+#define GLB_REG_GPIO_28_PD_POS   (5U)
+#define GLB_REG_GPIO_28_PD_LEN   (1U)
+#define GLB_REG_GPIO_28_PD_MSK   (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
+#define GLB_REG_GPIO_28_PD_UMSK  (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
+
+/* 0x180 : GPIO_CFGCTL30 */
+#define GLB_GPIO_CFGCTL30_OFFSET (0x180)
+#define GLB_REG_GPIO_0_I         GLB_REG_GPIO_0_I
+#define GLB_REG_GPIO_0_I_POS     (0U)
+#define GLB_REG_GPIO_0_I_LEN     (1U)
+#define GLB_REG_GPIO_0_I_MSK     (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
+#define GLB_REG_GPIO_0_I_UMSK    (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
+#define GLB_REG_GPIO_1_I         GLB_REG_GPIO_1_I
+#define GLB_REG_GPIO_1_I_POS     (1U)
+#define GLB_REG_GPIO_1_I_LEN     (1U)
+#define GLB_REG_GPIO_1_I_MSK     (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
+#define GLB_REG_GPIO_1_I_UMSK    (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
+#define GLB_REG_GPIO_2_I         GLB_REG_GPIO_2_I
+#define GLB_REG_GPIO_2_I_POS     (2U)
+#define GLB_REG_GPIO_2_I_LEN     (1U)
+#define GLB_REG_GPIO_2_I_MSK     (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
+#define GLB_REG_GPIO_2_I_UMSK    (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
+#define GLB_REG_GPIO_3_I         GLB_REG_GPIO_3_I
+#define GLB_REG_GPIO_3_I_POS     (3U)
+#define GLB_REG_GPIO_3_I_LEN     (1U)
+#define GLB_REG_GPIO_3_I_MSK     (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
+#define GLB_REG_GPIO_3_I_UMSK    (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
+#define GLB_REG_GPIO_4_I         GLB_REG_GPIO_4_I
+#define GLB_REG_GPIO_4_I_POS     (4U)
+#define GLB_REG_GPIO_4_I_LEN     (1U)
+#define GLB_REG_GPIO_4_I_MSK     (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
+#define GLB_REG_GPIO_4_I_UMSK    (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
+#define GLB_REG_GPIO_5_I         GLB_REG_GPIO_5_I
+#define GLB_REG_GPIO_5_I_POS     (5U)
+#define GLB_REG_GPIO_5_I_LEN     (1U)
+#define GLB_REG_GPIO_5_I_MSK     (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
+#define GLB_REG_GPIO_5_I_UMSK    (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
+#define GLB_REG_GPIO_6_I         GLB_REG_GPIO_6_I
+#define GLB_REG_GPIO_6_I_POS     (6U)
+#define GLB_REG_GPIO_6_I_LEN     (1U)
+#define GLB_REG_GPIO_6_I_MSK     (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
+#define GLB_REG_GPIO_6_I_UMSK    (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
+#define GLB_REG_GPIO_7_I         GLB_REG_GPIO_7_I
+#define GLB_REG_GPIO_7_I_POS     (7U)
+#define GLB_REG_GPIO_7_I_LEN     (1U)
+#define GLB_REG_GPIO_7_I_MSK     (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
+#define GLB_REG_GPIO_7_I_UMSK    (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
+#define GLB_REG_GPIO_8_I         GLB_REG_GPIO_8_I
+#define GLB_REG_GPIO_8_I_POS     (8U)
+#define GLB_REG_GPIO_8_I_LEN     (1U)
+#define GLB_REG_GPIO_8_I_MSK     (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
+#define GLB_REG_GPIO_8_I_UMSK    (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
+#define GLB_REG_GPIO_9_I         GLB_REG_GPIO_9_I
+#define GLB_REG_GPIO_9_I_POS     (9U)
+#define GLB_REG_GPIO_9_I_LEN     (1U)
+#define GLB_REG_GPIO_9_I_MSK     (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
+#define GLB_REG_GPIO_9_I_UMSK    (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
+#define GLB_REG_GPIO_10_I        GLB_REG_GPIO_10_I
+#define GLB_REG_GPIO_10_I_POS    (10U)
+#define GLB_REG_GPIO_10_I_LEN    (1U)
+#define GLB_REG_GPIO_10_I_MSK    (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
+#define GLB_REG_GPIO_10_I_UMSK   (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
+#define GLB_REG_GPIO_11_I        GLB_REG_GPIO_11_I
+#define GLB_REG_GPIO_11_I_POS    (11U)
+#define GLB_REG_GPIO_11_I_LEN    (1U)
+#define GLB_REG_GPIO_11_I_MSK    (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
+#define GLB_REG_GPIO_11_I_UMSK   (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
+#define GLB_REG_GPIO_12_I        GLB_REG_GPIO_12_I
+#define GLB_REG_GPIO_12_I_POS    (12U)
+#define GLB_REG_GPIO_12_I_LEN    (1U)
+#define GLB_REG_GPIO_12_I_MSK    (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
+#define GLB_REG_GPIO_12_I_UMSK   (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
+#define GLB_REG_GPIO_13_I        GLB_REG_GPIO_13_I
+#define GLB_REG_GPIO_13_I_POS    (13U)
+#define GLB_REG_GPIO_13_I_LEN    (1U)
+#define GLB_REG_GPIO_13_I_MSK    (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
+#define GLB_REG_GPIO_13_I_UMSK   (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
+#define GLB_REG_GPIO_14_I        GLB_REG_GPIO_14_I
+#define GLB_REG_GPIO_14_I_POS    (14U)
+#define GLB_REG_GPIO_14_I_LEN    (1U)
+#define GLB_REG_GPIO_14_I_MSK    (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
+#define GLB_REG_GPIO_14_I_UMSK   (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
+#define GLB_REG_GPIO_15_I        GLB_REG_GPIO_15_I
+#define GLB_REG_GPIO_15_I_POS    (15U)
+#define GLB_REG_GPIO_15_I_LEN    (1U)
+#define GLB_REG_GPIO_15_I_MSK    (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
+#define GLB_REG_GPIO_15_I_UMSK   (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
+#define GLB_REG_GPIO_16_I        GLB_REG_GPIO_16_I
+#define GLB_REG_GPIO_16_I_POS    (16U)
+#define GLB_REG_GPIO_16_I_LEN    (1U)
+#define GLB_REG_GPIO_16_I_MSK    (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
+#define GLB_REG_GPIO_16_I_UMSK   (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
+#define GLB_REG_GPIO_17_I        GLB_REG_GPIO_17_I
+#define GLB_REG_GPIO_17_I_POS    (17U)
+#define GLB_REG_GPIO_17_I_LEN    (1U)
+#define GLB_REG_GPIO_17_I_MSK    (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
+#define GLB_REG_GPIO_17_I_UMSK   (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
+#define GLB_REG_GPIO_18_I        GLB_REG_GPIO_18_I
+#define GLB_REG_GPIO_18_I_POS    (18U)
+#define GLB_REG_GPIO_18_I_LEN    (1U)
+#define GLB_REG_GPIO_18_I_MSK    (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
+#define GLB_REG_GPIO_18_I_UMSK   (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
+#define GLB_REG_GPIO_19_I        GLB_REG_GPIO_19_I
+#define GLB_REG_GPIO_19_I_POS    (19U)
+#define GLB_REG_GPIO_19_I_LEN    (1U)
+#define GLB_REG_GPIO_19_I_MSK    (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
+#define GLB_REG_GPIO_19_I_UMSK   (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
+#define GLB_REG_GPIO_20_I        GLB_REG_GPIO_20_I
+#define GLB_REG_GPIO_20_I_POS    (20U)
+#define GLB_REG_GPIO_20_I_LEN    (1U)
+#define GLB_REG_GPIO_20_I_MSK    (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
+#define GLB_REG_GPIO_20_I_UMSK   (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
+#define GLB_REG_GPIO_21_I        GLB_REG_GPIO_21_I
+#define GLB_REG_GPIO_21_I_POS    (21U)
+#define GLB_REG_GPIO_21_I_LEN    (1U)
+#define GLB_REG_GPIO_21_I_MSK    (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
+#define GLB_REG_GPIO_21_I_UMSK   (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
+#define GLB_REG_GPIO_22_I        GLB_REG_GPIO_22_I
+#define GLB_REG_GPIO_22_I_POS    (22U)
+#define GLB_REG_GPIO_22_I_LEN    (1U)
+#define GLB_REG_GPIO_22_I_MSK    (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
+#define GLB_REG_GPIO_22_I_UMSK   (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
+
+/* 0x184 : GPIO_CFGCTL31 */
+#define GLB_GPIO_CFGCTL31_OFFSET (0x184)
+
+/* 0x188 : GPIO_CFGCTL32 */
+#define GLB_GPIO_CFGCTL32_OFFSET (0x188)
+#define GLB_REG_GPIO_0_O         GLB_REG_GPIO_0_O
+#define GLB_REG_GPIO_0_O_POS     (0U)
+#define GLB_REG_GPIO_0_O_LEN     (1U)
+#define GLB_REG_GPIO_0_O_MSK     (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
+#define GLB_REG_GPIO_0_O_UMSK    (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
+#define GLB_REG_GPIO_1_O         GLB_REG_GPIO_1_O
+#define GLB_REG_GPIO_1_O_POS     (1U)
+#define GLB_REG_GPIO_1_O_LEN     (1U)
+#define GLB_REG_GPIO_1_O_MSK     (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
+#define GLB_REG_GPIO_1_O_UMSK    (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
+#define GLB_REG_GPIO_2_O         GLB_REG_GPIO_2_O
+#define GLB_REG_GPIO_2_O_POS     (2U)
+#define GLB_REG_GPIO_2_O_LEN     (1U)
+#define GLB_REG_GPIO_2_O_MSK     (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
+#define GLB_REG_GPIO_2_O_UMSK    (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
+#define GLB_REG_GPIO_3_O         GLB_REG_GPIO_3_O
+#define GLB_REG_GPIO_3_O_POS     (3U)
+#define GLB_REG_GPIO_3_O_LEN     (1U)
+#define GLB_REG_GPIO_3_O_MSK     (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
+#define GLB_REG_GPIO_3_O_UMSK    (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
+#define GLB_REG_GPIO_4_O         GLB_REG_GPIO_4_O
+#define GLB_REG_GPIO_4_O_POS     (4U)
+#define GLB_REG_GPIO_4_O_LEN     (1U)
+#define GLB_REG_GPIO_4_O_MSK     (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
+#define GLB_REG_GPIO_4_O_UMSK    (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
+#define GLB_REG_GPIO_5_O         GLB_REG_GPIO_5_O
+#define GLB_REG_GPIO_5_O_POS     (5U)
+#define GLB_REG_GPIO_5_O_LEN     (1U)
+#define GLB_REG_GPIO_5_O_MSK     (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
+#define GLB_REG_GPIO_5_O_UMSK    (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
+#define GLB_REG_GPIO_6_O         GLB_REG_GPIO_6_O
+#define GLB_REG_GPIO_6_O_POS     (6U)
+#define GLB_REG_GPIO_6_O_LEN     (1U)
+#define GLB_REG_GPIO_6_O_MSK     (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
+#define GLB_REG_GPIO_6_O_UMSK    (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
+#define GLB_REG_GPIO_7_O         GLB_REG_GPIO_7_O
+#define GLB_REG_GPIO_7_O_POS     (7U)
+#define GLB_REG_GPIO_7_O_LEN     (1U)
+#define GLB_REG_GPIO_7_O_MSK     (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
+#define GLB_REG_GPIO_7_O_UMSK    (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
+#define GLB_REG_GPIO_8_O         GLB_REG_GPIO_8_O
+#define GLB_REG_GPIO_8_O_POS     (8U)
+#define GLB_REG_GPIO_8_O_LEN     (1U)
+#define GLB_REG_GPIO_8_O_MSK     (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
+#define GLB_REG_GPIO_8_O_UMSK    (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
+#define GLB_REG_GPIO_9_O         GLB_REG_GPIO_9_O
+#define GLB_REG_GPIO_9_O_POS     (9U)
+#define GLB_REG_GPIO_9_O_LEN     (1U)
+#define GLB_REG_GPIO_9_O_MSK     (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
+#define GLB_REG_GPIO_9_O_UMSK    (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
+#define GLB_REG_GPIO_10_O        GLB_REG_GPIO_10_O
+#define GLB_REG_GPIO_10_O_POS    (10U)
+#define GLB_REG_GPIO_10_O_LEN    (1U)
+#define GLB_REG_GPIO_10_O_MSK    (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
+#define GLB_REG_GPIO_10_O_UMSK   (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
+#define GLB_REG_GPIO_11_O        GLB_REG_GPIO_11_O
+#define GLB_REG_GPIO_11_O_POS    (11U)
+#define GLB_REG_GPIO_11_O_LEN    (1U)
+#define GLB_REG_GPIO_11_O_MSK    (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
+#define GLB_REG_GPIO_11_O_UMSK   (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
+#define GLB_REG_GPIO_12_O        GLB_REG_GPIO_12_O
+#define GLB_REG_GPIO_12_O_POS    (12U)
+#define GLB_REG_GPIO_12_O_LEN    (1U)
+#define GLB_REG_GPIO_12_O_MSK    (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
+#define GLB_REG_GPIO_12_O_UMSK   (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
+#define GLB_REG_GPIO_13_O        GLB_REG_GPIO_13_O
+#define GLB_REG_GPIO_13_O_POS    (13U)
+#define GLB_REG_GPIO_13_O_LEN    (1U)
+#define GLB_REG_GPIO_13_O_MSK    (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
+#define GLB_REG_GPIO_13_O_UMSK   (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
+#define GLB_REG_GPIO_14_O        GLB_REG_GPIO_14_O
+#define GLB_REG_GPIO_14_O_POS    (14U)
+#define GLB_REG_GPIO_14_O_LEN    (1U)
+#define GLB_REG_GPIO_14_O_MSK    (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
+#define GLB_REG_GPIO_14_O_UMSK   (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
+#define GLB_REG_GPIO_15_O        GLB_REG_GPIO_15_O
+#define GLB_REG_GPIO_15_O_POS    (15U)
+#define GLB_REG_GPIO_15_O_LEN    (1U)
+#define GLB_REG_GPIO_15_O_MSK    (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
+#define GLB_REG_GPIO_15_O_UMSK   (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
+#define GLB_REG_GPIO_16_O        GLB_REG_GPIO_16_O
+#define GLB_REG_GPIO_16_O_POS    (16U)
+#define GLB_REG_GPIO_16_O_LEN    (1U)
+#define GLB_REG_GPIO_16_O_MSK    (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
+#define GLB_REG_GPIO_16_O_UMSK   (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
+#define GLB_REG_GPIO_17_O        GLB_REG_GPIO_17_O
+#define GLB_REG_GPIO_17_O_POS    (17U)
+#define GLB_REG_GPIO_17_O_LEN    (1U)
+#define GLB_REG_GPIO_17_O_MSK    (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
+#define GLB_REG_GPIO_17_O_UMSK   (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
+#define GLB_REG_GPIO_18_O        GLB_REG_GPIO_18_O
+#define GLB_REG_GPIO_18_O_POS    (18U)
+#define GLB_REG_GPIO_18_O_LEN    (1U)
+#define GLB_REG_GPIO_18_O_MSK    (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
+#define GLB_REG_GPIO_18_O_UMSK   (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
+#define GLB_REG_GPIO_19_O        GLB_REG_GPIO_19_O
+#define GLB_REG_GPIO_19_O_POS    (19U)
+#define GLB_REG_GPIO_19_O_LEN    (1U)
+#define GLB_REG_GPIO_19_O_MSK    (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
+#define GLB_REG_GPIO_19_O_UMSK   (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
+#define GLB_REG_GPIO_20_O        GLB_REG_GPIO_20_O
+#define GLB_REG_GPIO_20_O_POS    (20U)
+#define GLB_REG_GPIO_20_O_LEN    (1U)
+#define GLB_REG_GPIO_20_O_MSK    (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
+#define GLB_REG_GPIO_20_O_UMSK   (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
+#define GLB_REG_GPIO_21_O        GLB_REG_GPIO_21_O
+#define GLB_REG_GPIO_21_O_POS    (21U)
+#define GLB_REG_GPIO_21_O_LEN    (1U)
+#define GLB_REG_GPIO_21_O_MSK    (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
+#define GLB_REG_GPIO_21_O_UMSK   (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
+#define GLB_REG_GPIO_22_O        GLB_REG_GPIO_22_O
+#define GLB_REG_GPIO_22_O_POS    (22U)
+#define GLB_REG_GPIO_22_O_LEN    (1U)
+#define GLB_REG_GPIO_22_O_MSK    (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
+#define GLB_REG_GPIO_22_O_UMSK   (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
+
+/* 0x18C : GPIO_CFGCTL33 */
+#define GLB_GPIO_CFGCTL33_OFFSET (0x18C)
+
+/* 0x190 : GPIO_CFGCTL34 */
+#define GLB_GPIO_CFGCTL34_OFFSET (0x190)
+#define GLB_REG_GPIO_0_OE        GLB_REG_GPIO_0_OE
+#define GLB_REG_GPIO_0_OE_POS    (0U)
+#define GLB_REG_GPIO_0_OE_LEN    (1U)
+#define GLB_REG_GPIO_0_OE_MSK    (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
+#define GLB_REG_GPIO_0_OE_UMSK   (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
+#define GLB_REG_GPIO_1_OE        GLB_REG_GPIO_1_OE
+#define GLB_REG_GPIO_1_OE_POS    (1U)
+#define GLB_REG_GPIO_1_OE_LEN    (1U)
+#define GLB_REG_GPIO_1_OE_MSK    (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
+#define GLB_REG_GPIO_1_OE_UMSK   (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
+#define GLB_REG_GPIO_2_OE        GLB_REG_GPIO_2_OE
+#define GLB_REG_GPIO_2_OE_POS    (2U)
+#define GLB_REG_GPIO_2_OE_LEN    (1U)
+#define GLB_REG_GPIO_2_OE_MSK    (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
+#define GLB_REG_GPIO_2_OE_UMSK   (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
+#define GLB_REG_GPIO_3_OE        GLB_REG_GPIO_3_OE
+#define GLB_REG_GPIO_3_OE_POS    (3U)
+#define GLB_REG_GPIO_3_OE_LEN    (1U)
+#define GLB_REG_GPIO_3_OE_MSK    (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
+#define GLB_REG_GPIO_3_OE_UMSK   (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
+#define GLB_REG_GPIO_4_OE        GLB_REG_GPIO_4_OE
+#define GLB_REG_GPIO_4_OE_POS    (4U)
+#define GLB_REG_GPIO_4_OE_LEN    (1U)
+#define GLB_REG_GPIO_4_OE_MSK    (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
+#define GLB_REG_GPIO_4_OE_UMSK   (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
+#define GLB_REG_GPIO_5_OE        GLB_REG_GPIO_5_OE
+#define GLB_REG_GPIO_5_OE_POS    (5U)
+#define GLB_REG_GPIO_5_OE_LEN    (1U)
+#define GLB_REG_GPIO_5_OE_MSK    (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
+#define GLB_REG_GPIO_5_OE_UMSK   (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
+#define GLB_REG_GPIO_6_OE        GLB_REG_GPIO_6_OE
+#define GLB_REG_GPIO_6_OE_POS    (6U)
+#define GLB_REG_GPIO_6_OE_LEN    (1U)
+#define GLB_REG_GPIO_6_OE_MSK    (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
+#define GLB_REG_GPIO_6_OE_UMSK   (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
+#define GLB_REG_GPIO_7_OE        GLB_REG_GPIO_7_OE
+#define GLB_REG_GPIO_7_OE_POS    (7U)
+#define GLB_REG_GPIO_7_OE_LEN    (1U)
+#define GLB_REG_GPIO_7_OE_MSK    (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
+#define GLB_REG_GPIO_7_OE_UMSK   (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
+#define GLB_REG_GPIO_8_OE        GLB_REG_GPIO_8_OE
+#define GLB_REG_GPIO_8_OE_POS    (8U)
+#define GLB_REG_GPIO_8_OE_LEN    (1U)
+#define GLB_REG_GPIO_8_OE_MSK    (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
+#define GLB_REG_GPIO_8_OE_UMSK   (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
+#define GLB_REG_GPIO_9_OE        GLB_REG_GPIO_9_OE
+#define GLB_REG_GPIO_9_OE_POS    (9U)
+#define GLB_REG_GPIO_9_OE_LEN    (1U)
+#define GLB_REG_GPIO_9_OE_MSK    (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
+#define GLB_REG_GPIO_9_OE_UMSK   (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
+#define GLB_REG_GPIO_10_OE       GLB_REG_GPIO_10_OE
+#define GLB_REG_GPIO_10_OE_POS   (10U)
+#define GLB_REG_GPIO_10_OE_LEN   (1U)
+#define GLB_REG_GPIO_10_OE_MSK   (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
+#define GLB_REG_GPIO_10_OE_UMSK  (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
+#define GLB_REG_GPIO_11_OE       GLB_REG_GPIO_11_OE
+#define GLB_REG_GPIO_11_OE_POS   (11U)
+#define GLB_REG_GPIO_11_OE_LEN   (1U)
+#define GLB_REG_GPIO_11_OE_MSK   (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
+#define GLB_REG_GPIO_11_OE_UMSK  (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
+#define GLB_REG_GPIO_12_OE       GLB_REG_GPIO_12_OE
+#define GLB_REG_GPIO_12_OE_POS   (12U)
+#define GLB_REG_GPIO_12_OE_LEN   (1U)
+#define GLB_REG_GPIO_12_OE_MSK   (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
+#define GLB_REG_GPIO_12_OE_UMSK  (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
+#define GLB_REG_GPIO_13_OE       GLB_REG_GPIO_13_OE
+#define GLB_REG_GPIO_13_OE_POS   (13U)
+#define GLB_REG_GPIO_13_OE_LEN   (1U)
+#define GLB_REG_GPIO_13_OE_MSK   (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
+#define GLB_REG_GPIO_13_OE_UMSK  (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
+#define GLB_REG_GPIO_14_OE       GLB_REG_GPIO_14_OE
+#define GLB_REG_GPIO_14_OE_POS   (14U)
+#define GLB_REG_GPIO_14_OE_LEN   (1U)
+#define GLB_REG_GPIO_14_OE_MSK   (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
+#define GLB_REG_GPIO_14_OE_UMSK  (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
+#define GLB_REG_GPIO_15_OE       GLB_REG_GPIO_15_OE
+#define GLB_REG_GPIO_15_OE_POS   (15U)
+#define GLB_REG_GPIO_15_OE_LEN   (1U)
+#define GLB_REG_GPIO_15_OE_MSK   (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
+#define GLB_REG_GPIO_15_OE_UMSK  (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
+#define GLB_REG_GPIO_16_OE       GLB_REG_GPIO_16_OE
+#define GLB_REG_GPIO_16_OE_POS   (16U)
+#define GLB_REG_GPIO_16_OE_LEN   (1U)
+#define GLB_REG_GPIO_16_OE_MSK   (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
+#define GLB_REG_GPIO_16_OE_UMSK  (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
+#define GLB_REG_GPIO_17_OE       GLB_REG_GPIO_17_OE
+#define GLB_REG_GPIO_17_OE_POS   (17U)
+#define GLB_REG_GPIO_17_OE_LEN   (1U)
+#define GLB_REG_GPIO_17_OE_MSK   (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
+#define GLB_REG_GPIO_17_OE_UMSK  (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
+#define GLB_REG_GPIO_18_OE       GLB_REG_GPIO_18_OE
+#define GLB_REG_GPIO_18_OE_POS   (18U)
+#define GLB_REG_GPIO_18_OE_LEN   (1U)
+#define GLB_REG_GPIO_18_OE_MSK   (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
+#define GLB_REG_GPIO_18_OE_UMSK  (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
+#define GLB_REG_GPIO_19_OE       GLB_REG_GPIO_19_OE
+#define GLB_REG_GPIO_19_OE_POS   (19U)
+#define GLB_REG_GPIO_19_OE_LEN   (1U)
+#define GLB_REG_GPIO_19_OE_MSK   (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
+#define GLB_REG_GPIO_19_OE_UMSK  (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
+#define GLB_REG_GPIO_20_OE       GLB_REG_GPIO_20_OE
+#define GLB_REG_GPIO_20_OE_POS   (20U)
+#define GLB_REG_GPIO_20_OE_LEN   (1U)
+#define GLB_REG_GPIO_20_OE_MSK   (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
+#define GLB_REG_GPIO_20_OE_UMSK  (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
+#define GLB_REG_GPIO_21_OE       GLB_REG_GPIO_21_OE
+#define GLB_REG_GPIO_21_OE_POS   (21U)
+#define GLB_REG_GPIO_21_OE_LEN   (1U)
+#define GLB_REG_GPIO_21_OE_MSK   (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
+#define GLB_REG_GPIO_21_OE_UMSK  (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
+#define GLB_REG_GPIO_22_OE       GLB_REG_GPIO_22_OE
+#define GLB_REG_GPIO_22_OE_POS   (22U)
+#define GLB_REG_GPIO_22_OE_LEN   (1U)
+#define GLB_REG_GPIO_22_OE_MSK   (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
+#define GLB_REG_GPIO_22_OE_UMSK  (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
+
+/* 0x194 : GPIO_CFGCTL35 */
+#define GLB_GPIO_CFGCTL35_OFFSET (0x194)
+
+/* 0x1A0 : GPIO_INT_MASK1 */
+#define GLB_GPIO_INT_MASK1_OFFSET   (0x1A0)
+#define GLB_REG_GPIO_INT_MASK1      GLB_REG_GPIO_INT_MASK1
+#define GLB_REG_GPIO_INT_MASK1_POS  (0U)
+#define GLB_REG_GPIO_INT_MASK1_LEN  (32U)
+#define GLB_REG_GPIO_INT_MASK1_MSK  (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
+#define GLB_REG_GPIO_INT_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))
+
+/* 0x1A8 : GPIO_INT_STAT1 */
+#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)
+#define GLB_GPIO_INT_STAT1        GLB_GPIO_INT_STAT1
+#define GLB_GPIO_INT_STAT1_POS    (0U)
+#define GLB_GPIO_INT_STAT1_LEN    (32U)
+#define GLB_GPIO_INT_STAT1_MSK    (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
+#define GLB_GPIO_INT_STAT1_UMSK   (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))
+
+/* 0x1B0 : GPIO_INT_CLR1 */
+#define GLB_GPIO_INT_CLR1_OFFSET   (0x1B0)
+#define GLB_REG_GPIO_INT_CLR1      GLB_REG_GPIO_INT_CLR1
+#define GLB_REG_GPIO_INT_CLR1_POS  (0U)
+#define GLB_REG_GPIO_INT_CLR1_LEN  (32U)
+#define GLB_REG_GPIO_INT_CLR1_MSK  (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
+#define GLB_REG_GPIO_INT_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))
+
+/* 0x1C0 : GPIO_INT_MODE_SET1 */
+#define GLB_GPIO_INT_MODE_SET1_OFFSET   (0x1C0)
+#define GLB_REG_GPIO_INT_MODE_SET1      GLB_REG_GPIO_INT_MODE_SET1
+#define GLB_REG_GPIO_INT_MODE_SET1_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET1_LEN  (32U)
+#define GLB_REG_GPIO_INT_MODE_SET1_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS)
+#define GLB_REG_GPIO_INT_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS))
+
+/* 0x1C4 : GPIO_INT_MODE_SET2 */
+#define GLB_GPIO_INT_MODE_SET2_OFFSET   (0x1C4)
+#define GLB_REG_GPIO_INT_MODE_SET2      GLB_REG_GPIO_INT_MODE_SET2
+#define GLB_REG_GPIO_INT_MODE_SET2_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET2_LEN  (32U)
+#define GLB_REG_GPIO_INT_MODE_SET2_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS)
+#define GLB_REG_GPIO_INT_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS))
+
+/* 0x1C8 : GPIO_INT_MODE_SET3 */
+#define GLB_GPIO_INT_MODE_SET3_OFFSET   (0x1C8)
+#define GLB_REG_GPIO_INT_MODE_SET3      GLB_REG_GPIO_INT_MODE_SET3
+#define GLB_REG_GPIO_INT_MODE_SET3_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET3_LEN  (32U)
+#define GLB_REG_GPIO_INT_MODE_SET3_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS)
+#define GLB_REG_GPIO_INT_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS))
+
+/* 0x224 : led_driver */
+#define GLB_LED_DRIVER_OFFSET         (0x224)
+#define GLB_LED_DIN_REG               GLB_LED_DIN_REG
+#define GLB_LED_DIN_REG_POS           (0U)
+#define GLB_LED_DIN_REG_LEN           (1U)
+#define GLB_LED_DIN_REG_MSK           (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
+#define GLB_LED_DIN_REG_UMSK          (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
+#define GLB_LED_DIN_SEL               GLB_LED_DIN_SEL
+#define GLB_LED_DIN_SEL_POS           (1U)
+#define GLB_LED_DIN_SEL_LEN           (1U)
+#define GLB_LED_DIN_SEL_MSK           (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
+#define GLB_LED_DIN_SEL_UMSK          (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
+#define GLB_LED_DIN_POLARITY_SEL      GLB_LED_DIN_POLARITY_SEL
+#define GLB_LED_DIN_POLARITY_SEL_POS  (2U)
+#define GLB_LED_DIN_POLARITY_SEL_LEN  (1U)
+#define GLB_LED_DIN_POLARITY_SEL_MSK  (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
+#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS))
+#define GLB_LEDDRV_IBIAS              GLB_LEDDRV_IBIAS
+#define GLB_LEDDRV_IBIAS_POS          (4U)
+#define GLB_LEDDRV_IBIAS_LEN          (4U)
+#define GLB_LEDDRV_IBIAS_MSK          (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
+#define GLB_LEDDRV_IBIAS_UMSK         (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
+#define GLB_IR_RX_GPIO_SEL            GLB_IR_RX_GPIO_SEL
+#define GLB_IR_RX_GPIO_SEL_POS        (8U)
+#define GLB_IR_RX_GPIO_SEL_LEN        (2U)
+#define GLB_IR_RX_GPIO_SEL_MSK        (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
+#define GLB_IR_RX_GPIO_SEL_UMSK       (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
+#define GLB_PU_LEDDRV                 GLB_PU_LEDDRV
+#define GLB_PU_LEDDRV_POS             (31U)
+#define GLB_PU_LEDDRV_LEN             (1U)
+#define GLB_PU_LEDDRV_MSK             (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
+#define GLB_PU_LEDDRV_UMSK            (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
+
+/* 0x308 : gpdac_ctrl */
+#define GLB_GPDAC_CTRL_OFFSET    (0x308)
+#define GLB_GPDACA_RSTN_ANA      GLB_GPDACA_RSTN_ANA
+#define GLB_GPDACA_RSTN_ANA_POS  (0U)
+#define GLB_GPDACA_RSTN_ANA_LEN  (1U)
+#define GLB_GPDACA_RSTN_ANA_MSK  (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
+#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
+#define GLB_GPDACB_RSTN_ANA      GLB_GPDACB_RSTN_ANA
+#define GLB_GPDACB_RSTN_ANA_POS  (1U)
+#define GLB_GPDACB_RSTN_ANA_LEN  (1U)
+#define GLB_GPDACB_RSTN_ANA_MSK  (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
+#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
+#define GLB_GPDAC_TEST_EN        GLB_GPDAC_TEST_EN
+#define GLB_GPDAC_TEST_EN_POS    (7U)
+#define GLB_GPDAC_TEST_EN_LEN    (1U)
+#define GLB_GPDAC_TEST_EN_MSK    (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
+#define GLB_GPDAC_TEST_EN_UMSK   (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
+#define GLB_GPDAC_REF_SEL        GLB_GPDAC_REF_SEL
+#define GLB_GPDAC_REF_SEL_POS    (8U)
+#define GLB_GPDAC_REF_SEL_LEN    (1U)
+#define GLB_GPDAC_REF_SEL_MSK    (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
+#define GLB_GPDAC_REF_SEL_UMSK   (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
+#define GLB_GPDAC_TEST_SEL       GLB_GPDAC_TEST_SEL
+#define GLB_GPDAC_TEST_SEL_POS   (9U)
+#define GLB_GPDAC_TEST_SEL_LEN   (3U)
+#define GLB_GPDAC_TEST_SEL_MSK   (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
+#define GLB_GPDAC_TEST_SEL_UMSK  (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
+#define GLB_GPDAC_RESERVED       GLB_GPDAC_RESERVED
+#define GLB_GPDAC_RESERVED_POS   (24U)
+#define GLB_GPDAC_RESERVED_LEN   (8U)
+#define GLB_GPDAC_RESERVED_MSK   (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
+#define GLB_GPDAC_RESERVED_UMSK  (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
+
+/* 0x30C : gpdac_actrl */
+#define GLB_GPDAC_ACTRL_OFFSET  (0x30C)
+#define GLB_GPDAC_A_EN          GLB_GPDAC_A_EN
+#define GLB_GPDAC_A_EN_POS      (0U)
+#define GLB_GPDAC_A_EN_LEN      (1U)
+#define GLB_GPDAC_A_EN_MSK      (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
+#define GLB_GPDAC_A_EN_UMSK     (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
+#define GLB_GPDAC_IOA_EN        GLB_GPDAC_IOA_EN
+#define GLB_GPDAC_IOA_EN_POS    (1U)
+#define GLB_GPDAC_IOA_EN_LEN    (1U)
+#define GLB_GPDAC_IOA_EN_MSK    (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
+#define GLB_GPDAC_IOA_EN_UMSK   (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
+#define GLB_GPDAC_A_RNG         GLB_GPDAC_A_RNG
+#define GLB_GPDAC_A_RNG_POS     (18U)
+#define GLB_GPDAC_A_RNG_LEN     (2U)
+#define GLB_GPDAC_A_RNG_MSK     (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
+#define GLB_GPDAC_A_RNG_UMSK    (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
+#define GLB_GPDAC_A_OUTMUX      GLB_GPDAC_A_OUTMUX
+#define GLB_GPDAC_A_OUTMUX_POS  (20U)
+#define GLB_GPDAC_A_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_A_OUTMUX_MSK  (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
+#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
+
+/* 0x310 : gpdac_bctrl */
+#define GLB_GPDAC_BCTRL_OFFSET  (0x310)
+#define GLB_GPDAC_B_EN          GLB_GPDAC_B_EN
+#define GLB_GPDAC_B_EN_POS      (0U)
+#define GLB_GPDAC_B_EN_LEN      (1U)
+#define GLB_GPDAC_B_EN_MSK      (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
+#define GLB_GPDAC_B_EN_UMSK     (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
+#define GLB_GPDAC_IOB_EN        GLB_GPDAC_IOB_EN
+#define GLB_GPDAC_IOB_EN_POS    (1U)
+#define GLB_GPDAC_IOB_EN_LEN    (1U)
+#define GLB_GPDAC_IOB_EN_MSK    (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
+#define GLB_GPDAC_IOB_EN_UMSK   (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
+#define GLB_GPDAC_B_RNG         GLB_GPDAC_B_RNG
+#define GLB_GPDAC_B_RNG_POS     (18U)
+#define GLB_GPDAC_B_RNG_LEN     (2U)
+#define GLB_GPDAC_B_RNG_MSK     (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
+#define GLB_GPDAC_B_RNG_UMSK    (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
+#define GLB_GPDAC_B_OUTMUX      GLB_GPDAC_B_OUTMUX
+#define GLB_GPDAC_B_OUTMUX_POS  (20U)
+#define GLB_GPDAC_B_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_B_OUTMUX_MSK  (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
+#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
+
+/* 0x314 : gpdac_data */
+#define GLB_GPDAC_DATA_OFFSET (0x314)
+#define GLB_GPDAC_B_DATA      GLB_GPDAC_B_DATA
+#define GLB_GPDAC_B_DATA_POS  (0U)
+#define GLB_GPDAC_B_DATA_LEN  (10U)
+#define GLB_GPDAC_B_DATA_MSK  (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
+#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
+#define GLB_GPDAC_A_DATA      GLB_GPDAC_A_DATA
+#define GLB_GPDAC_A_DATA_POS  (16U)
+#define GLB_GPDAC_A_DATA_LEN  (10U)
+#define GLB_GPDAC_A_DATA_MSK  (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
+#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
+
+/* 0xF00 : tzc_glb_ctrl_0 */
+#define GLB_TZC_GLB_CTRL_0_OFFSET             (0xF00)
+#define GLB_TZC_GLB_SWRST_S00_LOCK            GLB_TZC_GLB_SWRST_S00_LOCK
+#define GLB_TZC_GLB_SWRST_S00_LOCK_POS        (0U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S01_LOCK            GLB_TZC_GLB_SWRST_S01_LOCK
+#define GLB_TZC_GLB_SWRST_S01_LOCK_POS        (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S30_LOCK            GLB_TZC_GLB_SWRST_S30_LOCK
+#define GLB_TZC_GLB_SWRST_S30_LOCK_POS        (8U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK       GLB_TZC_GLB_CTRL_PWRON_RST_LOCK
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS   (12U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK       GLB_TZC_GLB_CTRL_CPU_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS   (13U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK       GLB_TZC_GLB_CTRL_SYS_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS   (14U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK      GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS  (15U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK  (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS))
+#define GLB_TZC_GLB_MISC_LOCK                 GLB_TZC_GLB_MISC_LOCK
+#define GLB_TZC_GLB_MISC_LOCK_POS             (25U)
+#define GLB_TZC_GLB_MISC_LOCK_LEN             (1U)
+#define GLB_TZC_GLB_MISC_LOCK_MSK             (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
+#define GLB_TZC_GLB_MISC_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
+#define GLB_TZC_GLB_SRAM_LOCK                 GLB_TZC_GLB_SRAM_LOCK
+#define GLB_TZC_GLB_SRAM_LOCK_POS             (26U)
+#define GLB_TZC_GLB_SRAM_LOCK_LEN             (1U)
+#define GLB_TZC_GLB_SRAM_LOCK_MSK             (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
+#define GLB_TZC_GLB_SRAM_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
+#define GLB_TZC_GLB_L2C_LOCK                  GLB_TZC_GLB_L2C_LOCK
+#define GLB_TZC_GLB_L2C_LOCK_POS              (27U)
+#define GLB_TZC_GLB_L2C_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_L2C_LOCK_MSK              (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
+#define GLB_TZC_GLB_L2C_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
+#define GLB_TZC_GLB_BMX_LOCK                  GLB_TZC_GLB_BMX_LOCK
+#define GLB_TZC_GLB_BMX_LOCK_POS              (28U)
+#define GLB_TZC_GLB_BMX_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_BMX_LOCK_MSK              (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
+#define GLB_TZC_GLB_BMX_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
+#define GLB_TZC_GLB_DBG_LOCK                  GLB_TZC_GLB_DBG_LOCK
+#define GLB_TZC_GLB_DBG_LOCK_POS              (29U)
+#define GLB_TZC_GLB_DBG_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_DBG_LOCK_MSK              (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
+#define GLB_TZC_GLB_DBG_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
+#define GLB_TZC_GLB_MBIST_LOCK                GLB_TZC_GLB_MBIST_LOCK
+#define GLB_TZC_GLB_MBIST_LOCK_POS            (30U)
+#define GLB_TZC_GLB_MBIST_LOCK_LEN            (1U)
+#define GLB_TZC_GLB_MBIST_LOCK_MSK            (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
+#define GLB_TZC_GLB_MBIST_LOCK_UMSK           (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
+#define GLB_TZC_GLB_CLK_LOCK                  GLB_TZC_GLB_CLK_LOCK
+#define GLB_TZC_GLB_CLK_LOCK_POS              (31U)
+#define GLB_TZC_GLB_CLK_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_CLK_LOCK_MSK              (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
+#define GLB_TZC_GLB_CLK_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
+
+/* 0xF04 : tzc_glb_ctrl_1 */
+#define GLB_TZC_GLB_CTRL_1_OFFSET       (0xF04)
+#define GLB_TZC_GLB_SWRST_S20_LOCK      GLB_TZC_GLB_SWRST_S20_LOCK
+#define GLB_TZC_GLB_SWRST_S20_LOCK_POS  (0U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S21_LOCK      GLB_TZC_GLB_SWRST_S21_LOCK
+#define GLB_TZC_GLB_SWRST_S21_LOCK_POS  (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S22_LOCK      GLB_TZC_GLB_SWRST_S22_LOCK
+#define GLB_TZC_GLB_SWRST_S22_LOCK_POS  (2U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S23_LOCK      GLB_TZC_GLB_SWRST_S23_LOCK
+#define GLB_TZC_GLB_SWRST_S23_LOCK_POS  (3U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S24_LOCK      GLB_TZC_GLB_SWRST_S24_LOCK
+#define GLB_TZC_GLB_SWRST_S24_LOCK_POS  (4U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S25_LOCK      GLB_TZC_GLB_SWRST_S25_LOCK
+#define GLB_TZC_GLB_SWRST_S25_LOCK_POS  (5U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S26_LOCK      GLB_TZC_GLB_SWRST_S26_LOCK
+#define GLB_TZC_GLB_SWRST_S26_LOCK_POS  (6U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S27_LOCK      GLB_TZC_GLB_SWRST_S27_LOCK
+#define GLB_TZC_GLB_SWRST_S27_LOCK_POS  (7U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S28_LOCK      GLB_TZC_GLB_SWRST_S28_LOCK
+#define GLB_TZC_GLB_SWRST_S28_LOCK_POS  (8U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S29_LOCK      GLB_TZC_GLB_SWRST_S29_LOCK
+#define GLB_TZC_GLB_SWRST_S29_LOCK_POS  (9U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2A_LOCK      GLB_TZC_GLB_SWRST_S2A_LOCK
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS  (10U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2B_LOCK      GLB_TZC_GLB_SWRST_S2B_LOCK
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS  (11U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2C_LOCK      GLB_TZC_GLB_SWRST_S2C_LOCK
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS  (12U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2D_LOCK      GLB_TZC_GLB_SWRST_S2D_LOCK
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS  (13U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2E_LOCK      GLB_TZC_GLB_SWRST_S2E_LOCK
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS  (14U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2F_LOCK      GLB_TZC_GLB_SWRST_S2F_LOCK
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS  (15U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S10_LOCK      GLB_TZC_GLB_SWRST_S10_LOCK
+#define GLB_TZC_GLB_SWRST_S10_LOCK_POS  (16U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S11_LOCK      GLB_TZC_GLB_SWRST_S11_LOCK
+#define GLB_TZC_GLB_SWRST_S11_LOCK_POS  (17U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S12_LOCK      GLB_TZC_GLB_SWRST_S12_LOCK
+#define GLB_TZC_GLB_SWRST_S12_LOCK_POS  (18U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S13_LOCK      GLB_TZC_GLB_SWRST_S13_LOCK
+#define GLB_TZC_GLB_SWRST_S13_LOCK_POS  (19U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S14_LOCK      GLB_TZC_GLB_SWRST_S14_LOCK
+#define GLB_TZC_GLB_SWRST_S14_LOCK_POS  (20U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S15_LOCK      GLB_TZC_GLB_SWRST_S15_LOCK
+#define GLB_TZC_GLB_SWRST_S15_LOCK_POS  (21U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S16_LOCK      GLB_TZC_GLB_SWRST_S16_LOCK
+#define GLB_TZC_GLB_SWRST_S16_LOCK_POS  (22U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S17_LOCK      GLB_TZC_GLB_SWRST_S17_LOCK
+#define GLB_TZC_GLB_SWRST_S17_LOCK_POS  (23U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S18_LOCK      GLB_TZC_GLB_SWRST_S18_LOCK
+#define GLB_TZC_GLB_SWRST_S18_LOCK_POS  (24U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S19_LOCK      GLB_TZC_GLB_SWRST_S19_LOCK
+#define GLB_TZC_GLB_SWRST_S19_LOCK_POS  (25U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1A_LOCK      GLB_TZC_GLB_SWRST_S1A_LOCK
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS  (26U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1B_LOCK      GLB_TZC_GLB_SWRST_S1B_LOCK
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS  (27U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1C_LOCK      GLB_TZC_GLB_SWRST_S1C_LOCK
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS  (28U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1D_LOCK      GLB_TZC_GLB_SWRST_S1D_LOCK
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS  (29U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1E_LOCK      GLB_TZC_GLB_SWRST_S1E_LOCK
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS  (30U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1F_LOCK      GLB_TZC_GLB_SWRST_S1F_LOCK
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS  (31U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS))
+
+/* 0xF08 : tzc_glb_ctrl_2 */
+#define GLB_TZC_GLB_CTRL_2_OFFSET     (0xF08)
+#define GLB_TZC_GLB_GPIO_0_LOCK       GLB_TZC_GLB_GPIO_0_LOCK
+#define GLB_TZC_GLB_GPIO_0_LOCK_POS   (0U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_1_LOCK       GLB_TZC_GLB_GPIO_1_LOCK
+#define GLB_TZC_GLB_GPIO_1_LOCK_POS   (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_2_LOCK       GLB_TZC_GLB_GPIO_2_LOCK
+#define GLB_TZC_GLB_GPIO_2_LOCK_POS   (2U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_3_LOCK       GLB_TZC_GLB_GPIO_3_LOCK
+#define GLB_TZC_GLB_GPIO_3_LOCK_POS   (3U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_4_LOCK       GLB_TZC_GLB_GPIO_4_LOCK
+#define GLB_TZC_GLB_GPIO_4_LOCK_POS   (4U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_5_LOCK       GLB_TZC_GLB_GPIO_5_LOCK
+#define GLB_TZC_GLB_GPIO_5_LOCK_POS   (5U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_6_LOCK       GLB_TZC_GLB_GPIO_6_LOCK
+#define GLB_TZC_GLB_GPIO_6_LOCK_POS   (6U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_7_LOCK       GLB_TZC_GLB_GPIO_7_LOCK
+#define GLB_TZC_GLB_GPIO_7_LOCK_POS   (7U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_8_LOCK       GLB_TZC_GLB_GPIO_8_LOCK
+#define GLB_TZC_GLB_GPIO_8_LOCK_POS   (8U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_9_LOCK       GLB_TZC_GLB_GPIO_9_LOCK
+#define GLB_TZC_GLB_GPIO_9_LOCK_POS   (9U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_10_LOCK      GLB_TZC_GLB_GPIO_10_LOCK
+#define GLB_TZC_GLB_GPIO_10_LOCK_POS  (10U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_11_LOCK      GLB_TZC_GLB_GPIO_11_LOCK
+#define GLB_TZC_GLB_GPIO_11_LOCK_POS  (11U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_12_LOCK      GLB_TZC_GLB_GPIO_12_LOCK
+#define GLB_TZC_GLB_GPIO_12_LOCK_POS  (12U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_13_LOCK      GLB_TZC_GLB_GPIO_13_LOCK
+#define GLB_TZC_GLB_GPIO_13_LOCK_POS  (13U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_14_LOCK      GLB_TZC_GLB_GPIO_14_LOCK
+#define GLB_TZC_GLB_GPIO_14_LOCK_POS  (14U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_15_LOCK      GLB_TZC_GLB_GPIO_15_LOCK
+#define GLB_TZC_GLB_GPIO_15_LOCK_POS  (15U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_16_LOCK      GLB_TZC_GLB_GPIO_16_LOCK
+#define GLB_TZC_GLB_GPIO_16_LOCK_POS  (16U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_17_LOCK      GLB_TZC_GLB_GPIO_17_LOCK
+#define GLB_TZC_GLB_GPIO_17_LOCK_POS  (17U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_18_LOCK      GLB_TZC_GLB_GPIO_18_LOCK
+#define GLB_TZC_GLB_GPIO_18_LOCK_POS  (18U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_19_LOCK      GLB_TZC_GLB_GPIO_19_LOCK
+#define GLB_TZC_GLB_GPIO_19_LOCK_POS  (19U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_20_LOCK      GLB_TZC_GLB_GPIO_20_LOCK
+#define GLB_TZC_GLB_GPIO_20_LOCK_POS  (20U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_21_LOCK      GLB_TZC_GLB_GPIO_21_LOCK
+#define GLB_TZC_GLB_GPIO_21_LOCK_POS  (21U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_22_LOCK      GLB_TZC_GLB_GPIO_22_LOCK
+#define GLB_TZC_GLB_GPIO_22_LOCK_POS  (22U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_23_LOCK      GLB_TZC_GLB_GPIO_23_LOCK
+#define GLB_TZC_GLB_GPIO_23_LOCK_POS  (23U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_24_LOCK      GLB_TZC_GLB_GPIO_24_LOCK
+#define GLB_TZC_GLB_GPIO_24_LOCK_POS  (24U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_25_LOCK      GLB_TZC_GLB_GPIO_25_LOCK
+#define GLB_TZC_GLB_GPIO_25_LOCK_POS  (25U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_26_LOCK      GLB_TZC_GLB_GPIO_26_LOCK
+#define GLB_TZC_GLB_GPIO_26_LOCK_POS  (26U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_27_LOCK      GLB_TZC_GLB_GPIO_27_LOCK
+#define GLB_TZC_GLB_GPIO_27_LOCK_POS  (27U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_28_LOCK      GLB_TZC_GLB_GPIO_28_LOCK
+#define GLB_TZC_GLB_GPIO_28_LOCK_POS  (28U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS))
+
+/* 0xF0C : tzc_glb_ctrl_3 */
+#define GLB_TZC_GLB_CTRL_3_OFFSET (0xF0C)
+
+struct glb_reg {
+    /* 0x0 : clk_cfg0 */
+    union {
+        struct
+        {
+            uint32_t reg_pll_en       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_fclk_en      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_hclk_en      : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reg_bclk_en      : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reg_pll_sel      : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t hbn_root_clk_sel : 2; /* [ 7: 6],          r,        0x0 */
+            uint32_t reg_hclk_div     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_bclk_div     : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t fclk_sw_state    : 3; /* [26:24],          r,        0x0 */
+            uint32_t chip_rdy         : 1; /* [   27],          r,        0x0 */
+            uint32_t glb_id           : 4; /* [31:28],          r,        0x6 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg0;
+
+    /* 0x4 : clk_cfg1 */
+    union {
+        struct
+        {
+            uint32_t wifi_mac_core_div : 4; /* [ 3: 0],        r/w,        0x1 */
+            uint32_t wifi_mac_wt_div   : 4; /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_15     : 8; /* [15: 8],       rsvd,        0x0 */
+            uint32_t ble_clk_sel       : 6; /* [21:16],        r/w,       0x10 */
+            uint32_t reserved_22_23    : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t ble_en            : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_31    : 7; /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg1;
+
+    /* 0x8 : clk_cfg2 */
+    union {
+        struct
+        {
+            uint32_t uart_clk_div     : 3; /* [ 2: 0],        r/w,        0x7 */
+            uint32_t reserved_3       : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t uart_clk_en      : 1; /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_6     : 2; /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t hbn_uart_clk_sel : 1; /* [    7],          r,        0x0 */
+            uint32_t sf_clk_div       : 3; /* [10: 8],        r/w,        0x3 */
+            uint32_t sf_clk_en        : 1; /* [   11],        r/w,        0x1 */
+            uint32_t sf_clk_sel       : 2; /* [13:12],        r/w,        0x2 */
+            uint32_t sf_clk_sel2      : 2; /* [15:14],        r/w,        0x0 */
+            uint32_t ir_clk_div       : 6; /* [21:16],        r/w,        0xf */
+            uint32_t reserved_22      : 1; /* [   22],       rsvd,        0x0 */
+            uint32_t ir_clk_en        : 1; /* [   23],        r/w,        0x1 */
+            uint32_t dma_clk_en       : 8; /* [31:24],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg2;
+
+    /* 0xC : clk_cfg3 */
+    union {
+        struct
+        {
+            uint32_t spi_clk_div    : 5; /* [ 4: 0],        r/w,        0x3 */
+            uint32_t reserved_5_7   : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t spi_clk_en     : 1; /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_15  : 7; /* [15: 9],       rsvd,        0x0 */
+            uint32_t i2c_clk_div    : 8; /* [23:16],        r/w,       0xff */
+            uint32_t i2c_clk_en     : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_31 : 7; /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg3;
+
+    /* 0x10 : swrst_cfg0 */
+    union {
+        struct
+        {
+            uint32_t swrst_s00     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s01     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3  : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t swrst_s20     : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_7  : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t swrst_s30     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg0;
+
+    /* 0x14 : swrst_cfg1 */
+    union {
+        struct
+        {
+            uint32_t swrst_s10      : 1; /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s11      : 1; /* [    1],        r/w,        0x0 */
+            uint32_t swrst_s12      : 1; /* [    2],        r/w,        0x0 */
+            uint32_t swrst_s13      : 1; /* [    3],        r/w,        0x0 */
+            uint32_t swrst_s14      : 1; /* [    4],        r/w,        0x0 */
+            uint32_t swrst_s15      : 1; /* [    5],        r/w,        0x0 */
+            uint32_t swrst_s16      : 1; /* [    6],        r/w,        0x0 */
+            uint32_t swrst_s17      : 1; /* [    7],        r/w,        0x0 */
+            uint32_t swrst_s18      : 1; /* [    8],        r/w,        0x0 */
+            uint32_t swrst_s19      : 1; /* [    9],        r/w,        0x0 */
+            uint32_t swrst_s1a      : 1; /* [   10],        r/w,        0x0 */
+            uint32_t swrst_s1b      : 1; /* [   11],        r/w,        0x0 */
+            uint32_t swrst_s1c      : 1; /* [   12],        r/w,        0x0 */
+            uint32_t swrst_s1d      : 1; /* [   13],        r/w,        0x0 */
+            uint32_t swrst_s1e      : 1; /* [   14],        r/w,        0x0 */
+            uint32_t swrst_s1f      : 1; /* [   15],        r/w,        0x0 */
+            uint32_t swrst_s1a0     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t swrst_s1a1     : 1; /* [   17],        r/w,        0x0 */
+            uint32_t swrst_s1a2     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t swrst_s1a3     : 1; /* [   19],        r/w,        0x0 */
+            uint32_t swrst_s1a4     : 1; /* [   20],        r/w,        0x0 */
+            uint32_t swrst_s1a5     : 1; /* [   21],        r/w,        0x0 */
+            uint32_t swrst_s1a6     : 1; /* [   22],        r/w,        0x0 */
+            uint32_t swrst_s1a7     : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_31 : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg1;
+
+    /* 0x18 : swrst_cfg2 */
+    union {
+        struct
+        {
+            uint32_t reg_ctrl_pwron_rst   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_ctrl_cpu_reset   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_ctrl_sys_reset   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t reg_ctrl_reset_dummy : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_23        : 16; /* [23: 8],       rsvd,        0x0 */
+            uint32_t pka_clk_sel          : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t reserved_25_31       : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg2;
+
+    /* 0x1C : swrst_cfg3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg3;
+
+    /* 0x20 : cgen_cfg0 */
+    union {
+        struct
+        {
+            uint32_t cgen_m        : 8;  /* [ 7: 0],        r/w,       0xff */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg0;
+
+    /* 0x24 : cgen_cfg1 */
+    union {
+        struct
+        {
+            uint32_t cgen_s1        : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t cgen_s1a       : 8;  /* [23:16],        r/w,       0xff */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg1;
+
+    /* 0x28 : cgen_cfg2 */
+    union {
+        struct
+        {
+            uint32_t cgen_s2       : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3  : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t cgen_s3       : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_31 : 27; /* [31: 5],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg2;
+
+    /* 0x2C : cgen_cfg3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg3;
+
+    /* 0x30 : MBIST_CTL */
+    union {
+        struct
+        {
+            uint32_t irom_mbist_mode  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t hsram_mbist_mode : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t tag_mbist_mode   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t ocram_mbist_mode : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t wifi_mbist_mode  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_30    : 26; /* [30: 5],       rsvd,        0x0 */
+            uint32_t reg_mbist_rst_n  : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MBIST_CTL;
+
+    /* 0x34 : MBIST_STAT */
+    union {
+        struct
+        {
+            uint32_t irom_mbist_done  : 1;  /* [    0],          r,        0x0 */
+            uint32_t hsram_mbist_done : 1;  /* [    1],          r,        0x0 */
+            uint32_t tag_mbist_done   : 1;  /* [    2],          r,        0x0 */
+            uint32_t ocram_mbist_done : 1;  /* [    3],          r,        0x0 */
+            uint32_t wifi_mbist_done  : 1;  /* [    4],          r,        0x0 */
+            uint32_t reserved_5_15    : 11; /* [15: 5],       rsvd,        0x0 */
+            uint32_t irom_mbist_fail  : 1;  /* [   16],          r,        0x0 */
+            uint32_t hsram_mbist_fail : 1;  /* [   17],          r,        0x0 */
+            uint32_t tag_mbist_fail   : 1;  /* [   18],          r,        0x0 */
+            uint32_t ocram_mbist_fail : 1;  /* [   19],          r,        0x0 */
+            uint32_t wifi_mbist_fail  : 1;  /* [   20],          r,        0x0 */
+            uint32_t reserved_21_31   : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MBIST_STAT;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[24];
+
+    /* 0x50 : bmx_cfg1 */
+    union {
+        struct
+        {
+            uint32_t bmx_timeout_en      : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t bmx_arb_mode        : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t bmx_err_en          : 1; /* [    8],        r/w,        0x0 */
+            uint32_t bmx_busy_option_dis : 1; /* [    9],        r/w,        0x0 */
+            uint32_t bmx_gating_dis      : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t hsel_option         : 4; /* [15:12],        r/w,        0x0 */
+            uint32_t pds_apb_cfg         : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t hbn_apb_cfg         : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg1;
+
+    /* 0x54 : bmx_cfg2 */
+    union {
+        struct
+        {
+            uint32_t bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
+            uint32_t bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_27    : 22; /* [27: 6],       rsvd,        0x0 */
+            uint32_t bmx_dbg_sel      : 4;  /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg2;
+
+    /* 0x58 : bmx_err_addr */
+    union {
+        struct
+        {
+            uint32_t bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_err_addr;
+
+    /* 0x5C : bmx_dbg_out */
+    union {
+        struct
+        {
+            uint32_t bmx_dbg_out : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_dbg_out;
+
+    /* 0x60 : rsv0 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv0;
+
+    /* 0x64 : rsv1 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv1;
+
+    /* 0x68 : rsv2 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv2;
+
+    /* 0x6C : rsv3 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } rsv3;
+
+    /* 0x70 : sram_ret */
+    union {
+        struct
+        {
+            uint32_t reg_sram_ret : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_ret;
+
+    /* 0x74 : sram_slp */
+    union {
+        struct
+        {
+            uint32_t reg_sram_slp : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_slp;
+
+    /* 0x78 : sram_parm */
+    union {
+        struct
+        {
+            uint32_t reg_sram_parm : 32; /* [31: 0],        r/w,  0xc0c0c0c */
+        } BF;
+        uint32_t WORD;
+    } sram_parm;
+
+    /* 0x7C : seam_misc */
+    union {
+        struct
+        {
+            uint32_t em_sel        : 4;  /* [ 3: 0],        r/w,        0x3 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } seam_misc;
+
+    /* 0x80 : glb_parm */
+    union {
+        struct
+        {
+            uint32_t reg_bd_en             : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_ext_rst_smt       : 1; /* [    1],        r/w,        0x0 */
+            uint32_t jtag_swap_set         : 6; /* [ 7: 2],        r/w,        0x0 */
+            uint32_t swap_sflash_io_3_io_0 : 1; /* [    8],        r/w,        0x1 */
+            uint32_t sel_embedded_sflash   : 1; /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10_11        : 2; /* [11:10],       rsvd,        0x0 */
+            uint32_t reg_spi_0_master_mode : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_spi_0_swap        : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14           : 1; /* [   14],       rsvd,        0x0 */
+            uint32_t reg_cci_use_jtag_pin  : 1; /* [   15],        r/w,        0x1 */
+            uint32_t reg_cci_use_sdio_pin  : 1; /* [   16],        r/w,        0x1 */
+            uint32_t p1_adc_test_with_cci  : 1; /* [   17],        r/w,        0x0 */
+            uint32_t p2_dac_test_with_cci  : 1; /* [   18],        r/w,        0x0 */
+            uint32_t p3_cci_use_io_2_5     : 1; /* [   19],        r/w,        0x0 */
+            uint32_t p4_adc_test_with_jtag : 1; /* [   20],        r/w,        0x0 */
+            uint32_t p5_dac_test_with_jtag : 1; /* [   21],        r/w,        0x0 */
+            uint32_t p6_sdio_use_io_0_5    : 1; /* [   22],        r/w,        0x0 */
+            uint32_t p7_jtag_use_io_2_5    : 1; /* [   23],        r/w,        0x0 */
+            uint32_t uart_swap_set         : 3; /* [26:24],        r/w,        0x0 */
+            uint32_t reserved_27_31        : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } glb_parm;
+
+    /* 0x84  reserved */
+    uint8_t RESERVED0x84[12];
+
+    /* 0x90 : CPU_CLK_CFG */
+    union {
+        struct
+        {
+            uint32_t cpu_rtc_div        : 17; /* [16: 0],        r/w,       0x10 */
+            uint32_t reserved_17        : 1;  /* [   17],       rsvd,        0x0 */
+            uint32_t cpu_rtc_en         : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t cpu_rtc_sel        : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t debug_ndreset_gate : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31     : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } CPU_CLK_CFG;
+
+    /* 0x94  reserved */
+    uint8_t RESERVED0x94[16];
+
+    /* 0xA4 : GPADC_32M_SRC_CTRL */
+    union {
+        struct
+        {
+            uint32_t gpadc_32m_clk_div : 6;  /* [ 5: 0],        r/w,        0x2 */
+            uint32_t reserved_6        : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t gpadc_32m_clk_sel : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_32m_div_en  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31     : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPADC_32M_SRC_CTRL;
+
+    /* 0xA8 : DIG32K_WAKEUP_CTRL */
+    union {
+        struct
+        {
+            uint32_t dig_32k_div            : 11; /* [10: 0],        r/w,      0x3e8 */
+            uint32_t reserved_11            : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t dig_32k_en             : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t dig_32k_comp           : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15         : 2;  /* [15:14],       rsvd,        0x0 */
+            uint32_t dig_512k_div           : 7;  /* [22:16],        r/w,       0x3e */
+            uint32_t reserved_23            : 1;  /* [   23],       rsvd,        0x0 */
+            uint32_t dig_512k_en            : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t dig_512k_comp          : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t reserved_26_27         : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t dig_clk_src_sel        : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29_30         : 2;  /* [30:29],       rsvd,        0x0 */
+            uint32_t reg_en_platform_wakeup : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DIG32K_WAKEUP_CTRL;
+
+    /* 0xAC : WIFI_BT_COEX_CTRL */
+    union {
+        struct
+        {
+            uint32_t coex_bt_channel : 7;  /* [ 6: 0],        r/w,        0x0 */
+            uint32_t coex_bt_pti     : 4;  /* [10: 7],        r/w,        0x0 */
+            uint32_t coex_bt_bw      : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t en_gpio_bt_coex : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_31  : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WIFI_BT_COEX_CTRL;
+
+    /* 0xb0  reserved */
+    uint8_t RESERVED0xb0[16];
+
+    /* 0xC0 : UART_SIG_SEL_0 */
+    union {
+        struct
+        {
+            uint32_t uart_sig_0_sel : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t uart_sig_1_sel : 4; /* [ 7: 4],        r/w,        0x1 */
+            uint32_t uart_sig_2_sel : 4; /* [11: 8],        r/w,        0x2 */
+            uint32_t uart_sig_3_sel : 4; /* [15:12],        r/w,        0x3 */
+            uint32_t uart_sig_4_sel : 4; /* [19:16],        r/w,        0x4 */
+            uint32_t uart_sig_5_sel : 4; /* [23:20],        r/w,        0x5 */
+            uint32_t uart_sig_6_sel : 4; /* [27:24],        r/w,        0x6 */
+            uint32_t uart_sig_7_sel : 4; /* [31:28],        r/w,        0x7 */
+        } BF;
+        uint32_t WORD;
+    } UART_SIG_SEL_0;
+
+    /* 0xc4  reserved */
+    uint8_t RESERVED0xc4[12];
+
+    /* 0xD0 : DBG_SEL_LL */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_LL;
+
+    /* 0xD4 : DBG_SEL_LH */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_LH;
+
+    /* 0xD8 : DBG_SEL_HL */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_HL;
+
+    /* 0xDC : DBG_SEL_HH */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_HH;
+
+    /* 0xE0 : debug */
+    union {
+        struct
+        {
+            uint32_t debug_oe : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t debug_i  : 31; /* [31: 1],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } debug;
+
+    /* 0xe4  reserved */
+    uint8_t RESERVED0xe4[28];
+
+    /* 0x100 : GPIO_CFGCTL0 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_ie        : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_0_smt       : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_0_drv       : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pu        : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pd        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_func_sel  : 4; /* [11: 8],        r/w,        0x1 */
+            uint32_t real_gpio_0_func_sel : 4; /* [15:12],          r,        0x1 */
+            uint32_t reg_gpio_1_ie        : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_1_smt       : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_1_drv       : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pu        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pd        : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_func_sel  : 4; /* [27:24],        r/w,        0x1 */
+            uint32_t real_gpio_1_func_sel : 4; /* [31:28],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL0;
+
+    /* 0x104 : GPIO_CFGCTL1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_2_ie        : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_2_smt       : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_2_drv       : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pu        : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pd        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_func_sel  : 4; /* [11: 8],        r/w,        0x1 */
+            uint32_t real_gpio_2_func_sel : 4; /* [15:12],          r,        0x1 */
+            uint32_t reg_gpio_3_ie        : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_3_smt       : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_3_drv       : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pu        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pd        : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_func_sel  : 4; /* [27:24],        r/w,        0x1 */
+            uint32_t real_gpio_3_func_sel : 4; /* [31:28],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL1;
+
+    /* 0x108 : GPIO_CFGCTL2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_4_ie        : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_4_smt       : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_4_drv       : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pu        : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pd        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_func_sel  : 4; /* [11: 8],        r/w,        0x1 */
+            uint32_t real_gpio_4_func_sel : 4; /* [15:12],          r,        0x1 */
+            uint32_t reg_gpio_5_ie        : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_5_smt       : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_5_drv       : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pu        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pd        : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_func_sel  : 4; /* [27:24],        r/w,        0x1 */
+            uint32_t real_gpio_5_func_sel : 4; /* [31:28],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL2;
+
+    /* 0x10C : GPIO_CFGCTL3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_6_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_6_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_6_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_func_sel : 4; /* [11: 8],        r/w,        0xb */
+            uint32_t reserved_12_15      : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_7_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_7_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_func_sel : 4; /* [27:24],        r/w,        0xb */
+            uint32_t reserved_28_31      : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL3;
+
+    /* 0x110 : GPIO_CFGCTL4 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_8_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_8_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_8_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_func_sel : 4; /* [11: 8],        r/w,        0xb */
+            uint32_t reserved_12_15      : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_9_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_9_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_func_sel : 4; /* [27:24],        r/w,        0xb */
+            uint32_t reserved_28_31      : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL4;
+
+    /* 0x114 : GPIO_CFGCTL5 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_10_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_10_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_10_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_func_sel : 4; /* [11: 8],        r/w,        0xb */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_11_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_11_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_func_sel : 4; /* [27:24],        r/w,        0xe */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL5;
+
+    /* 0x118 : GPIO_CFGCTL6 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_12_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_12_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_12_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_func_sel : 4; /* [11: 8],        r/w,        0xe */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_13_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_13_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_func_sel : 4; /* [27:24],        r/w,        0xb */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL6;
+
+    /* 0x11C : GPIO_CFGCTL7 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_14_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_14_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_14_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_func_sel : 4; /* [11: 8],        r/w,        0xe */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_15_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_15_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_func_sel : 4; /* [27:24],        r/w,        0xb */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL7;
+
+    /* 0x120 : GPIO_CFGCTL8 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_16_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_16_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_16_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_func_sel : 4; /* [11: 8],        r/w,        0xb */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_17_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_17_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_func_sel : 4; /* [27:24],        r/w,        0xe */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL8;
+
+    /* 0x124 : GPIO_CFGCTL9 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_18_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_18_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_18_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_func_sel : 4; /* [11: 8],        r/w,        0xb */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_19_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_19_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_func_sel : 4; /* [27:24],        r/w,        0xb */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL9;
+
+    /* 0x128 : GPIO_CFGCTL10 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_20_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_20_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_20_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_func_sel : 4; /* [11: 8],        r/w,        0xb */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_21_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_21_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_func_sel : 4; /* [27:24],        r/w,        0xb */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL10;
+
+    /* 0x12C : GPIO_CFGCTL11 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_22_ie       : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_22_smt      : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_22_drv      : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pu       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pd       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_func_sel : 4;  /* [11: 8],        r/w,        0xb */
+            uint32_t reserved_12_15       : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_ie       : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_23_smt      : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_23_drv      : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pu       : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pd       : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31       : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL11;
+
+    /* 0x130 : GPIO_CFGCTL12 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_24_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_24_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_24_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pd  : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_25_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_25_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL12;
+
+    /* 0x134 : GPIO_CFGCTL13 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_26_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_26_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_26_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_27_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_27_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL13;
+
+    /* 0x138 : GPIO_CFGCTL14 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_28_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_28_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_28_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL14;
+
+    /* 0x13c  reserved */
+    uint8_t RESERVED0x13c[68];
+
+    /* 0x180 : GPIO_CFGCTL30 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_i   : 1; /* [    0],          r,        0x0 */
+            uint32_t reg_gpio_1_i   : 1; /* [    1],          r,        0x0 */
+            uint32_t reg_gpio_2_i   : 1; /* [    2],          r,        0x0 */
+            uint32_t reg_gpio_3_i   : 1; /* [    3],          r,        0x0 */
+            uint32_t reg_gpio_4_i   : 1; /* [    4],          r,        0x0 */
+            uint32_t reg_gpio_5_i   : 1; /* [    5],          r,        0x0 */
+            uint32_t reg_gpio_6_i   : 1; /* [    6],          r,        0x0 */
+            uint32_t reg_gpio_7_i   : 1; /* [    7],          r,        0x0 */
+            uint32_t reg_gpio_8_i   : 1; /* [    8],          r,        0x0 */
+            uint32_t reg_gpio_9_i   : 1; /* [    9],          r,        0x0 */
+            uint32_t reg_gpio_10_i  : 1; /* [   10],          r,        0x0 */
+            uint32_t reg_gpio_11_i  : 1; /* [   11],          r,        0x0 */
+            uint32_t reg_gpio_12_i  : 1; /* [   12],          r,        0x0 */
+            uint32_t reg_gpio_13_i  : 1; /* [   13],          r,        0x0 */
+            uint32_t reg_gpio_14_i  : 1; /* [   14],          r,        0x0 */
+            uint32_t reg_gpio_15_i  : 1; /* [   15],          r,        0x0 */
+            uint32_t reg_gpio_16_i  : 1; /* [   16],          r,        0x0 */
+            uint32_t reg_gpio_17_i  : 1; /* [   17],          r,        0x0 */
+            uint32_t reg_gpio_18_i  : 1; /* [   18],          r,        0x0 */
+            uint32_t reg_gpio_19_i  : 1; /* [   19],          r,        0x0 */
+            uint32_t reg_gpio_20_i  : 1; /* [   20],          r,        0x0 */
+            uint32_t reg_gpio_21_i  : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_22_i  : 1; /* [   22],          r,        0x0 */
+            uint32_t reserved_23_31 : 9; /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL30;
+
+    /* 0x184 : GPIO_CFGCTL31 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL31;
+
+    /* 0x188 : GPIO_CFGCTL32 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_o   : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_1_o   : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg_gpio_2_o   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg_gpio_3_o   : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg_gpio_4_o   : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_5_o   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_6_o   : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_gpio_7_o   : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_gpio_8_o   : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_gpio_9_o   : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reg_gpio_10_o  : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg_gpio_11_o  : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg_gpio_12_o  : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_gpio_13_o  : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_gpio_14_o  : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg_gpio_15_o  : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg_gpio_16_o  : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_17_o  : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reg_gpio_18_o  : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_o  : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg_gpio_20_o  : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_o  : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reg_gpio_22_o  : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9; /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL32;
+
+    /* 0x18C : GPIO_CFGCTL33 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL33;
+
+    /* 0x190 : GPIO_CFGCTL34 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_oe  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_1_oe  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg_gpio_2_oe  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg_gpio_3_oe  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg_gpio_4_oe  : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_5_oe  : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_6_oe  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_gpio_7_oe  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_gpio_8_oe  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_gpio_9_oe  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reg_gpio_10_oe : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg_gpio_11_oe : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg_gpio_12_oe : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_gpio_13_oe : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_gpio_14_oe : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg_gpio_15_oe : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg_gpio_16_oe : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_17_oe : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reg_gpio_18_oe : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_oe : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg_gpio_20_oe : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_oe : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reg_gpio_22_oe : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9; /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL34;
+
+    /* 0x194 : GPIO_CFGCTL35 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL35;
+
+    /* 0x198  reserved */
+    uint8_t RESERVED0x198[8];
+
+    /* 0x1A0 : GPIO_INT_MASK1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mask1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MASK1;
+
+    /* 0x1a4  reserved */
+    uint8_t RESERVED0x1a4[4];
+
+    /* 0x1A8 : GPIO_INT_STAT1 */
+    union {
+        struct
+        {
+            uint32_t gpio_int_stat1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_STAT1;
+
+    /* 0x1ac  reserved */
+    uint8_t RESERVED0x1ac[4];
+
+    /* 0x1B0 : GPIO_INT_CLR1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_clr1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_CLR1;
+
+    /* 0x1b4  reserved */
+    uint8_t RESERVED0x1b4[12];
+
+    /* 0x1C0 : GPIO_INT_MODE_SET1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET1;
+
+    /* 0x1C4 : GPIO_INT_MODE_SET2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET2;
+
+    /* 0x1C8 : GPIO_INT_MODE_SET3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET3;
+
+    /* 0x1cc  reserved */
+    uint8_t RESERVED0x1cc[88];
+
+    /* 0x224 : led_driver */
+    union {
+        struct
+        {
+            uint32_t led_din_reg          : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t led_din_sel          : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t led_din_polarity_sel : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t leddrv_ibias         : 4;  /* [ 7: 4],        r/w,        0x8 */
+            uint32_t ir_rx_gpio_sel       : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_30       : 21; /* [30:10],       rsvd,        0x0 */
+            uint32_t pu_leddrv            : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } led_driver;
+
+    /* 0x228  reserved */
+    uint8_t RESERVED0x228[224];
+
+    /* 0x308 : gpdac_ctrl */
+    union {
+        struct
+        {
+            uint32_t gpdaca_rstn_ana : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t gpdacb_rstn_ana : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_6    : 5;  /* [ 6: 2],       rsvd,        0x0 */
+            uint32_t gpdac_test_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpdac_ref_sel   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpdac_test_sel  : 3;  /* [11: 9],        r/w,        0x0 */
+            uint32_t reserved_12_23  : 12; /* [23:12],       rsvd,        0x0 */
+            uint32_t gpdac_reserved  : 8;  /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } gpdac_ctrl;
+
+    /* 0x30C : gpdac_actrl */
+    union {
+        struct
+        {
+            uint32_t gpdac_a_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_ioa_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_a_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_a_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_actrl;
+
+    /* 0x310 : gpdac_bctrl */
+    union {
+        struct
+        {
+            uint32_t gpdac_b_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_iob_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_b_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_b_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_bctrl;
+
+    /* 0x314 : gpdac_data */
+    union {
+        struct
+        {
+            uint32_t gpdac_b_data   : 10; /* [ 9: 0],        r/w,        0x0 */
+            uint32_t reserved_10_15 : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t gpdac_a_data   : 10; /* [25:16],        r/w,        0x0 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_data;
+
+    /* 0x318  reserved */
+    uint8_t RESERVED0x318[3048];
+
+    /* 0xF00 : tzc_glb_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_swrst_s00_lock       : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s01_lock       : 1; /* [    1],          r,        0x0 */
+            uint32_t reserved_2_7                 : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t tzc_glb_swrst_s30_lock       : 1; /* [    8],          r,        0x0 */
+            uint32_t reserved_9_11                : 3; /* [11: 9],       rsvd,        0x0 */
+            uint32_t tzc_glb_ctrl_pwron_rst_lock  : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_cpu_reset_lock  : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_sys_reset_lock  : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t reserved_16_24               : 9; /* [24:16],       rsvd,        0x0 */
+            uint32_t tzc_glb_misc_lock            : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_sram_lock            : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_l2c_lock             : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_bmx_lock             : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_dbg_lock             : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_mbist_lock           : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_clk_lock             : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_0;
+
+    /* 0xF04 : tzc_glb_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_swrst_s20_lock : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s21_lock : 1; /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s22_lock : 1; /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s23_lock : 1; /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s24_lock : 1; /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s25_lock : 1; /* [    5],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s26_lock : 1; /* [    6],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s27_lock : 1; /* [    7],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s28_lock : 1; /* [    8],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s29_lock : 1; /* [    9],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2a_lock : 1; /* [   10],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2b_lock : 1; /* [   11],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2c_lock : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2d_lock : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2e_lock : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2f_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s10_lock : 1; /* [   16],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s11_lock : 1; /* [   17],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s12_lock : 1; /* [   18],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s13_lock : 1; /* [   19],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s14_lock : 1; /* [   20],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s15_lock : 1; /* [   21],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s16_lock : 1; /* [   22],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s17_lock : 1; /* [   23],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s18_lock : 1; /* [   24],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s19_lock : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1a_lock : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1b_lock : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1c_lock : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1d_lock : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1e_lock : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1f_lock : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_1;
+
+    /* 0xF08 : tzc_glb_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_gpio_0_lock  : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_gpio_1_lock  : 1; /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_gpio_2_lock  : 1; /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_gpio_3_lock  : 1; /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_gpio_4_lock  : 1; /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_gpio_5_lock  : 1; /* [    5],          r,        0x0 */
+            uint32_t tzc_glb_gpio_6_lock  : 1; /* [    6],          r,        0x0 */
+            uint32_t tzc_glb_gpio_7_lock  : 1; /* [    7],          r,        0x0 */
+            uint32_t tzc_glb_gpio_8_lock  : 1; /* [    8],          r,        0x0 */
+            uint32_t tzc_glb_gpio_9_lock  : 1; /* [    9],          r,        0x0 */
+            uint32_t tzc_glb_gpio_10_lock : 1; /* [   10],          r,        0x0 */
+            uint32_t tzc_glb_gpio_11_lock : 1; /* [   11],          r,        0x0 */
+            uint32_t tzc_glb_gpio_12_lock : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_gpio_13_lock : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_gpio_14_lock : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_gpio_15_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t tzc_glb_gpio_16_lock : 1; /* [   16],          r,        0x0 */
+            uint32_t tzc_glb_gpio_17_lock : 1; /* [   17],          r,        0x0 */
+            uint32_t tzc_glb_gpio_18_lock : 1; /* [   18],          r,        0x0 */
+            uint32_t tzc_glb_gpio_19_lock : 1; /* [   19],          r,        0x0 */
+            uint32_t tzc_glb_gpio_20_lock : 1; /* [   20],          r,        0x0 */
+            uint32_t tzc_glb_gpio_21_lock : 1; /* [   21],          r,        0x0 */
+            uint32_t tzc_glb_gpio_22_lock : 1; /* [   22],          r,        0x0 */
+            uint32_t tzc_glb_gpio_23_lock : 1; /* [   23],          r,        0x0 */
+            uint32_t tzc_glb_gpio_24_lock : 1; /* [   24],          r,        0x0 */
+            uint32_t tzc_glb_gpio_25_lock : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_gpio_26_lock : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_gpio_27_lock : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_gpio_28_lock : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_2;
+
+    /* 0xF0C : tzc_glb_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_3;
+};
+
+typedef volatile struct glb_reg glb_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : GPIO_CFGCTL */
+#define GLB_GPIO_CFGCTL_OFFSET        (0x0)
+#define GLB_REG_GPIO_0_IE             GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS         (0U)
+#define GLB_REG_GPIO_0_IE_LEN         (1U)
+#define GLB_REG_GPIO_0_IE_MSK         (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK        (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT            GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS        (1U)
+#define GLB_REG_GPIO_0_SMT_LEN        (1U)
+#define GLB_REG_GPIO_0_SMT_MSK        (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK       (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV            GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS        (2U)
+#define GLB_REG_GPIO_0_DRV_LEN        (2U)
+#define GLB_REG_GPIO_0_DRV_MSK        (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK       (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU             GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS         (4U)
+#define GLB_REG_GPIO_0_PU_LEN         (1U)
+#define GLB_REG_GPIO_0_PU_MSK         (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK        (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD             GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS         (5U)
+#define GLB_REG_GPIO_0_PD_LEN         (1U)
+#define GLB_REG_GPIO_0_PD_MSK         (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK        (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL       GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS   (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_0_FUNC_SEL      GLB_REAL_GPIO_0_FUNC_SEL
+#define GLB_REAL_GPIO_0_FUNC_SEL_POS  (12U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE             GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS         (16U)
+#define GLB_REG_GPIO_1_IE_LEN         (1U)
+#define GLB_REG_GPIO_1_IE_MSK         (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK        (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT            GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS        (17U)
+#define GLB_REG_GPIO_1_SMT_LEN        (1U)
+#define GLB_REG_GPIO_1_SMT_MSK        (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK       (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV            GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS        (18U)
+#define GLB_REG_GPIO_1_DRV_LEN        (2U)
+#define GLB_REG_GPIO_1_DRV_MSK        (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK       (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU             GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS         (20U)
+#define GLB_REG_GPIO_1_PU_LEN         (1U)
+#define GLB_REG_GPIO_1_PU_MSK         (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK        (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD             GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS         (21U)
+#define GLB_REG_GPIO_1_PD_LEN         (1U)
+#define GLB_REG_GPIO_1_PD_MSK         (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK        (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL       GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS   (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN   (4U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK   (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK  (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+#define GLB_REAL_GPIO_1_FUNC_SEL      GLB_REAL_GPIO_1_FUNC_SEL
+#define GLB_REAL_GPIO_1_FUNC_SEL_POS  (28U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_LEN  (4U)
+#define GLB_REAL_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS)
+#define GLB_REAL_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REAL_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REAL_GPIO_1_FUNC_SEL_POS))
+
+struct glb_gpio_reg {
+    /* 0x0 : GPIO_CFGCTL */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_ie        : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_0_smt       : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_0_drv       : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pu        : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pd        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_func_sel  : 4; /* [11: 8],        r/w,        0x1 */
+            uint32_t real_gpio_0_func_sel : 4; /* [15:12],          r,        0x1 */
+            uint32_t reg_gpio_1_ie        : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_1_smt       : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_1_drv       : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pu        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pd        : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_func_sel  : 4; /* [27:24],        r/w,        0x1 */
+            uint32_t real_gpio_1_func_sel : 4; /* [31:28],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL;
+};
+
+typedef volatile struct glb_gpio_reg glb_gpio_reg_t;
+
+#define GLB_GPIO_OFFSET           0x100
+#define GLB_GPIO_INPUT_OFFSET     0x180
+#define GLB_GPIO_OUTPUT_OFFSET    0x188
+#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190
+
+#endif /* __GLB_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/hbn_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/hbn_reg.h
new file mode 100755
index 0000000000..1aef0ab766
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/hbn_reg.h
@@ -0,0 +1,760 @@
+/**
+  ******************************************************************************
+  * @file    hbn_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HBN_REG_H__
+#define __HBN_REG_H__
+
+#include "bl602.h"
+
+/* 0x0 : HBN_CTL */
+#define HBN_CTL_OFFSET                (0x0)
+#define HBN_RTC_CTL                   HBN_RTC_CTL
+#define HBN_RTC_CTL_POS               (0U)
+#define HBN_RTC_CTL_LEN               (7U)
+#define HBN_RTC_CTL_MSK               (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
+#define HBN_RTC_CTL_UMSK              (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
+#define HBN_MODE                      HBN_MODE
+#define HBN_MODE_POS                  (7U)
+#define HBN_MODE_LEN                  (1U)
+#define HBN_MODE_MSK                  (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
+#define HBN_MODE_UMSK                 (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
+#define HBN_TRAP_MODE                 HBN_TRAP_MODE
+#define HBN_TRAP_MODE_POS             (8U)
+#define HBN_TRAP_MODE_LEN             (1U)
+#define HBN_TRAP_MODE_MSK             (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
+#define HBN_TRAP_MODE_UMSK            (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
+#define HBN_PWRDN_HBN_CORE            HBN_PWRDN_HBN_CORE
+#define HBN_PWRDN_HBN_CORE_POS        (9U)
+#define HBN_PWRDN_HBN_CORE_LEN        (1U)
+#define HBN_PWRDN_HBN_CORE_MSK        (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
+#define HBN_PWRDN_HBN_CORE_UMSK       (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
+#define HBN_PWRDN_HBN_RTC             HBN_PWRDN_HBN_RTC
+#define HBN_PWRDN_HBN_RTC_POS         (11U)
+#define HBN_PWRDN_HBN_RTC_LEN         (1U)
+#define HBN_PWRDN_HBN_RTC_MSK         (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)
+#define HBN_PWRDN_HBN_RTC_UMSK        (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS))
+#define HBN_SW_RST                    HBN_SW_RST
+#define HBN_SW_RST_POS                (12U)
+#define HBN_SW_RST_LEN                (1U)
+#define HBN_SW_RST_MSK                (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
+#define HBN_SW_RST_UMSK               (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
+#define HBN_DIS_PWR_OFF_LDO11         HBN_DIS_PWR_OFF_LDO11
+#define HBN_DIS_PWR_OFF_LDO11_POS     (13U)
+#define HBN_DIS_PWR_OFF_LDO11_LEN     (1U)
+#define HBN_DIS_PWR_OFF_LDO11_MSK     (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
+#define HBN_DIS_PWR_OFF_LDO11_UMSK    (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
+#define HBN_DIS_PWR_OFF_LDO11_RT      HBN_DIS_PWR_OFF_LDO11_RT
+#define HBN_DIS_PWR_OFF_LDO11_RT_POS  (14U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_LEN  (1U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_MSK  (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
+#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
+#define HBN_LDO11_RT_VOUT_SEL         HBN_LDO11_RT_VOUT_SEL
+#define HBN_LDO11_RT_VOUT_SEL_POS     (15U)
+#define HBN_LDO11_RT_VOUT_SEL_LEN     (4U)
+#define HBN_LDO11_RT_VOUT_SEL_MSK     (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
+#define HBN_LDO11_RT_VOUT_SEL_UMSK    (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
+#define HBN_LDO11_AON_VOUT_SEL        HBN_LDO11_AON_VOUT_SEL
+#define HBN_LDO11_AON_VOUT_SEL_POS    (19U)
+#define HBN_LDO11_AON_VOUT_SEL_LEN    (4U)
+#define HBN_LDO11_AON_VOUT_SEL_MSK    (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
+#define HBN_LDO11_AON_VOUT_SEL_UMSK   (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
+#define HBN_PU_DCDC18_AON             HBN_PU_DCDC18_AON
+#define HBN_PU_DCDC18_AON_POS         (23U)
+#define HBN_PU_DCDC18_AON_LEN         (1U)
+#define HBN_PU_DCDC18_AON_MSK         (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
+#define HBN_PU_DCDC18_AON_UMSK        (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
+#define HBN_RTC_DLY_OPTION            HBN_RTC_DLY_OPTION
+#define HBN_RTC_DLY_OPTION_POS        (24U)
+#define HBN_RTC_DLY_OPTION_LEN        (1U)
+#define HBN_RTC_DLY_OPTION_MSK        (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
+#define HBN_RTC_DLY_OPTION_UMSK       (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
+#define HBN_PWR_ON_OPTION             HBN_PWR_ON_OPTION
+#define HBN_PWR_ON_OPTION_POS         (25U)
+#define HBN_PWR_ON_OPTION_LEN         (1U)
+#define HBN_PWR_ON_OPTION_MSK         (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
+#define HBN_PWR_ON_OPTION_UMSK        (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
+#define HBN_SRAM_SLP_OPTION           HBN_SRAM_SLP_OPTION
+#define HBN_SRAM_SLP_OPTION_POS       (26U)
+#define HBN_SRAM_SLP_OPTION_LEN       (1U)
+#define HBN_SRAM_SLP_OPTION_MSK       (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
+#define HBN_SRAM_SLP_OPTION_UMSK      (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
+#define HBN_SRAM_SLP                  HBN_SRAM_SLP
+#define HBN_SRAM_SLP_POS              (27U)
+#define HBN_SRAM_SLP_LEN              (1U)
+#define HBN_SRAM_SLP_MSK              (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
+#define HBN_SRAM_SLP_UMSK             (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
+#define HBN_STATE                     HBN_STATE
+#define HBN_STATE_POS                 (28U)
+#define HBN_STATE_LEN                 (4U)
+#define HBN_STATE_MSK                 (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
+#define HBN_STATE_UMSK                (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
+
+/* 0x4 : HBN_TIME_L */
+#define HBN_TIME_L_OFFSET (0x4)
+#define HBN_TIME_L        HBN_TIME_L
+#define HBN_TIME_L_POS    (0U)
+#define HBN_TIME_L_LEN    (32U)
+#define HBN_TIME_L_MSK    (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
+#define HBN_TIME_L_UMSK   (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
+
+/* 0x8 : HBN_TIME_H */
+#define HBN_TIME_H_OFFSET (0x8)
+#define HBN_TIME_H        HBN_TIME_H
+#define HBN_TIME_H_POS    (0U)
+#define HBN_TIME_H_LEN    (8U)
+#define HBN_TIME_H_MSK    (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
+#define HBN_TIME_H_UMSK   (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
+
+/* 0xC : RTC_TIME_L */
+#define HBN_RTC_TIME_L_OFFSET     (0xC)
+#define HBN_RTC_TIME_LATCH_L      HBN_RTC_TIME_LATCH_L
+#define HBN_RTC_TIME_LATCH_L_POS  (0U)
+#define HBN_RTC_TIME_LATCH_L_LEN  (32U)
+#define HBN_RTC_TIME_LATCH_L_MSK  (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
+#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
+
+/* 0x10 : RTC_TIME_H */
+#define HBN_RTC_TIME_H_OFFSET     (0x10)
+#define HBN_RTC_TIME_LATCH_H      HBN_RTC_TIME_LATCH_H
+#define HBN_RTC_TIME_LATCH_H_POS  (0U)
+#define HBN_RTC_TIME_LATCH_H_LEN  (8U)
+#define HBN_RTC_TIME_LATCH_H_MSK  (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
+#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
+#define HBN_RTC_TIME_LATCH        HBN_RTC_TIME_LATCH
+#define HBN_RTC_TIME_LATCH_POS    (31U)
+#define HBN_RTC_TIME_LATCH_LEN    (1U)
+#define HBN_RTC_TIME_LATCH_MSK    (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
+#define HBN_RTC_TIME_LATCH_UMSK   (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
+
+/* 0x14 : HBN_IRQ_MODE */
+#define HBN_IRQ_MODE_OFFSET         (0x14)
+#define HBN_PIN_WAKEUP_MODE         HBN_PIN_WAKEUP_MODE
+#define HBN_PIN_WAKEUP_MODE_POS     (0U)
+#define HBN_PIN_WAKEUP_MODE_LEN     (3U)
+#define HBN_PIN_WAKEUP_MODE_MSK     (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
+#define HBN_PIN_WAKEUP_MODE_UMSK    (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
+#define HBN_PIN_WAKEUP_MASK         HBN_PIN_WAKEUP_MASK
+#define HBN_PIN_WAKEUP_MASK_POS     (3U)
+#define HBN_PIN_WAKEUP_MASK_LEN     (2U)
+#define HBN_PIN_WAKEUP_MASK_MSK     (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
+#define HBN_PIN_WAKEUP_MASK_UMSK    (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
+#define HBN_REG_AON_PAD_IE_SMT      HBN_REG_AON_PAD_IE_SMT
+#define HBN_REG_AON_PAD_IE_SMT_POS  (8U)
+#define HBN_REG_AON_PAD_IE_SMT_LEN  (1U)
+#define HBN_REG_AON_PAD_IE_SMT_MSK  (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
+#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
+#define HBN_REG_EN_HW_PU_PD         HBN_REG_EN_HW_PU_PD
+#define HBN_REG_EN_HW_PU_PD_POS     (16U)
+#define HBN_REG_EN_HW_PU_PD_LEN     (1U)
+#define HBN_REG_EN_HW_PU_PD_MSK     (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
+#define HBN_REG_EN_HW_PU_PD_UMSK    (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
+#define HBN_IRQ_BOR_EN              HBN_IRQ_BOR_EN
+#define HBN_IRQ_BOR_EN_POS          (18U)
+#define HBN_IRQ_BOR_EN_LEN          (1U)
+#define HBN_IRQ_BOR_EN_MSK          (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
+#define HBN_IRQ_BOR_EN_UMSK         (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
+#define HBN_IRQ_ACOMP0_EN           HBN_IRQ_ACOMP0_EN
+#define HBN_IRQ_ACOMP0_EN_POS       (20U)
+#define HBN_IRQ_ACOMP0_EN_LEN       (2U)
+#define HBN_IRQ_ACOMP0_EN_MSK       (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
+#define HBN_IRQ_ACOMP0_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
+#define HBN_IRQ_ACOMP1_EN           HBN_IRQ_ACOMP1_EN
+#define HBN_IRQ_ACOMP1_EN_POS       (22U)
+#define HBN_IRQ_ACOMP1_EN_LEN       (2U)
+#define HBN_IRQ_ACOMP1_EN_MSK       (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
+#define HBN_IRQ_ACOMP1_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
+#define HBN_PIN_WAKEUP_SEL          HBN_PIN_WAKEUP_SEL
+#define HBN_PIN_WAKEUP_SEL_POS      (24U)
+#define HBN_PIN_WAKEUP_SEL_LEN      (3U)
+#define HBN_PIN_WAKEUP_SEL_MSK      (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
+#define HBN_PIN_WAKEUP_SEL_UMSK     (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
+#define HBN_PIN_WAKEUP_EN           HBN_PIN_WAKEUP_EN
+#define HBN_PIN_WAKEUP_EN_POS       (27U)
+#define HBN_PIN_WAKEUP_EN_LEN       (1U)
+#define HBN_PIN_WAKEUP_EN_MSK       (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
+#define HBN_PIN_WAKEUP_EN_UMSK      (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
+
+/* 0x18 : HBN_IRQ_STAT */
+#define HBN_IRQ_STAT_OFFSET (0x18)
+#define HBN_IRQ_STAT        HBN_IRQ_STAT
+#define HBN_IRQ_STAT_POS    (0U)
+#define HBN_IRQ_STAT_LEN    (32U)
+#define HBN_IRQ_STAT_MSK    (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
+#define HBN_IRQ_STAT_UMSK   (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
+
+/* 0x1C : HBN_IRQ_CLR */
+#define HBN_IRQ_CLR_OFFSET (0x1C)
+#define HBN_IRQ_CLR        HBN_IRQ_CLR
+#define HBN_IRQ_CLR_POS    (0U)
+#define HBN_IRQ_CLR_LEN    (32U)
+#define HBN_IRQ_CLR_MSK    (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
+#define HBN_IRQ_CLR_UMSK   (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
+
+/* 0x20 : HBN_PIR_CFG */
+#define HBN_PIR_CFG_OFFSET    (0x20)
+#define HBN_PIR_HPF_SEL       HBN_PIR_HPF_SEL
+#define HBN_PIR_HPF_SEL_POS   (0U)
+#define HBN_PIR_HPF_SEL_LEN   (2U)
+#define HBN_PIR_HPF_SEL_MSK   (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
+#define HBN_PIR_HPF_SEL_UMSK  (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
+#define HBN_PIR_LPF_SEL       HBN_PIR_LPF_SEL
+#define HBN_PIR_LPF_SEL_POS   (2U)
+#define HBN_PIR_LPF_SEL_LEN   (1U)
+#define HBN_PIR_LPF_SEL_MSK   (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
+#define HBN_PIR_LPF_SEL_UMSK  (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
+#define HBN_PIR_DIS           HBN_PIR_DIS
+#define HBN_PIR_DIS_POS       (4U)
+#define HBN_PIR_DIS_LEN       (2U)
+#define HBN_PIR_DIS_MSK       (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
+#define HBN_PIR_DIS_UMSK      (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
+#define HBN_PIR_EN            HBN_PIR_EN
+#define HBN_PIR_EN_POS        (7U)
+#define HBN_PIR_EN_LEN        (1U)
+#define HBN_PIR_EN_MSK        (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
+#define HBN_PIR_EN_UMSK       (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
+#define HBN_GPADC_CGEN        HBN_GPADC_CGEN
+#define HBN_GPADC_CGEN_POS    (8U)
+#define HBN_GPADC_CGEN_LEN    (1U)
+#define HBN_GPADC_CGEN_MSK    (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)
+#define HBN_GPADC_CGEN_UMSK   (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS))
+#define HBN_GPADC_NOSYNC      HBN_GPADC_NOSYNC
+#define HBN_GPADC_NOSYNC_POS  (9U)
+#define HBN_GPADC_NOSYNC_LEN  (1U)
+#define HBN_GPADC_NOSYNC_MSK  (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)
+#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS))
+
+/* 0x24 : HBN_PIR_VTH */
+#define HBN_PIR_VTH_OFFSET (0x24)
+#define HBN_PIR_VTH        HBN_PIR_VTH
+#define HBN_PIR_VTH_POS    (0U)
+#define HBN_PIR_VTH_LEN    (14U)
+#define HBN_PIR_VTH_MSK    (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
+#define HBN_PIR_VTH_UMSK   (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
+
+/* 0x28 : HBN_PIR_INTERVAL */
+#define HBN_PIR_INTERVAL_OFFSET (0x28)
+#define HBN_PIR_INTERVAL        HBN_PIR_INTERVAL
+#define HBN_PIR_INTERVAL_POS    (0U)
+#define HBN_PIR_INTERVAL_LEN    (12U)
+#define HBN_PIR_INTERVAL_MSK    (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
+#define HBN_PIR_INTERVAL_UMSK   (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
+
+/* 0x2C : HBN_BOR_CFG */
+#define HBN_BOR_CFG_OFFSET (0x2C)
+#define HBN_BOR_SEL        HBN_BOR_SEL
+#define HBN_BOR_SEL_POS    (0U)
+#define HBN_BOR_SEL_LEN    (1U)
+#define HBN_BOR_SEL_MSK    (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)
+#define HBN_BOR_SEL_UMSK   (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS))
+#define HBN_BOR_VTH        HBN_BOR_VTH
+#define HBN_BOR_VTH_POS    (1U)
+#define HBN_BOR_VTH_LEN    (1U)
+#define HBN_BOR_VTH_MSK    (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)
+#define HBN_BOR_VTH_UMSK   (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS))
+#define HBN_PU_BOR         HBN_PU_BOR
+#define HBN_PU_BOR_POS     (2U)
+#define HBN_PU_BOR_LEN     (1U)
+#define HBN_PU_BOR_MSK     (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)
+#define HBN_PU_BOR_UMSK    (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS))
+#define HBN_R_BOR_OUT      HBN_R_BOR_OUT
+#define HBN_R_BOR_OUT_POS  (3U)
+#define HBN_R_BOR_OUT_LEN  (1U)
+#define HBN_R_BOR_OUT_MSK  (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)
+#define HBN_R_BOR_OUT_UMSK (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS))
+
+/* 0x30 : HBN_GLB */
+#define HBN_GLB_OFFSET                    (0x30)
+#define HBN_ROOT_CLK_SEL                  HBN_ROOT_CLK_SEL
+#define HBN_ROOT_CLK_SEL_POS              (0U)
+#define HBN_ROOT_CLK_SEL_LEN              (2U)
+#define HBN_ROOT_CLK_SEL_MSK              (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
+#define HBN_ROOT_CLK_SEL_UMSK             (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
+#define HBN_UART_CLK_SEL                  HBN_UART_CLK_SEL
+#define HBN_UART_CLK_SEL_POS              (2U)
+#define HBN_UART_CLK_SEL_LEN              (1U)
+#define HBN_UART_CLK_SEL_MSK              (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
+#define HBN_UART_CLK_SEL_UMSK             (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
+#define HBN_F32K_SEL                      HBN_F32K_SEL
+#define HBN_F32K_SEL_POS                  (3U)
+#define HBN_F32K_SEL_LEN                  (2U)
+#define HBN_F32K_SEL_MSK                  (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
+#define HBN_F32K_SEL_UMSK                 (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
+#define HBN_PU_RC32K                      HBN_PU_RC32K
+#define HBN_PU_RC32K_POS                  (5U)
+#define HBN_PU_RC32K_LEN                  (1U)
+#define HBN_PU_RC32K_MSK                  (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
+#define HBN_PU_RC32K_UMSK                 (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON      HBN_SW_LDO11SOC_VOUT_SEL_AON
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS  (16U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN  (4U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK  (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
+#define HBN_SW_LDO11_RT_VOUT_SEL          HBN_SW_LDO11_RT_VOUT_SEL
+#define HBN_SW_LDO11_RT_VOUT_SEL_POS      (24U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_LEN      (4U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_MSK      (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
+#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK     (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
+#define HBN_SW_LDO11_AON_VOUT_SEL         HBN_SW_LDO11_AON_VOUT_SEL
+#define HBN_SW_LDO11_AON_VOUT_SEL_POS     (28U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_LEN     (4U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_MSK     (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
+#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK    (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))
+
+/* 0x34 : HBN_SRAM */
+#define HBN_SRAM_OFFSET     (0x34)
+#define HBN_RETRAM_RET      HBN_RETRAM_RET
+#define HBN_RETRAM_RET_POS  (6U)
+#define HBN_RETRAM_RET_LEN  (1U)
+#define HBN_RETRAM_RET_MSK  (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
+#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
+#define HBN_RETRAM_SLP      HBN_RETRAM_SLP
+#define HBN_RETRAM_SLP_POS  (7U)
+#define HBN_RETRAM_SLP_LEN  (1U)
+#define HBN_RETRAM_SLP_MSK  (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
+#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
+
+/* 0x100 : HBN_RSV0 */
+#define HBN_RSV0_OFFSET (0x100)
+#define HBN_RSV0        HBN_RSV0
+#define HBN_RSV0_POS    (0U)
+#define HBN_RSV0_LEN    (32U)
+#define HBN_RSV0_MSK    (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
+#define HBN_RSV0_UMSK   (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
+
+/* 0x104 : HBN_RSV1 */
+#define HBN_RSV1_OFFSET (0x104)
+#define HBN_RSV1        HBN_RSV1
+#define HBN_RSV1_POS    (0U)
+#define HBN_RSV1_LEN    (32U)
+#define HBN_RSV1_MSK    (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
+#define HBN_RSV1_UMSK   (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
+
+/* 0x108 : HBN_RSV2 */
+#define HBN_RSV2_OFFSET (0x108)
+#define HBN_RSV2        HBN_RSV2
+#define HBN_RSV2_POS    (0U)
+#define HBN_RSV2_LEN    (32U)
+#define HBN_RSV2_MSK    (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
+#define HBN_RSV2_UMSK   (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
+
+/* 0x10C : HBN_RSV3 */
+#define HBN_RSV3_OFFSET (0x10C)
+#define HBN_RSV3        HBN_RSV3
+#define HBN_RSV3_POS    (0U)
+#define HBN_RSV3_LEN    (32U)
+#define HBN_RSV3_MSK    (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
+#define HBN_RSV3_UMSK   (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
+
+/* 0x200 : rc32k_ctrl0 */
+#define HBN_RC32K_CTRL0_OFFSET         (0x200)
+#define HBN_RC32K_CAL_DONE             HBN_RC32K_CAL_DONE
+#define HBN_RC32K_CAL_DONE_POS         (0U)
+#define HBN_RC32K_CAL_DONE_LEN         (1U)
+#define HBN_RC32K_CAL_DONE_MSK         (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
+#define HBN_RC32K_CAL_DONE_UMSK        (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
+#define HBN_RC32K_RDY                  HBN_RC32K_RDY
+#define HBN_RC32K_RDY_POS              (1U)
+#define HBN_RC32K_RDY_LEN              (1U)
+#define HBN_RC32K_RDY_MSK              (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
+#define HBN_RC32K_RDY_UMSK             (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
+#define HBN_RC32K_CAL_INPROGRESS       HBN_RC32K_CAL_INPROGRESS
+#define HBN_RC32K_CAL_INPROGRESS_POS   (2U)
+#define HBN_RC32K_CAL_INPROGRESS_LEN   (1U)
+#define HBN_RC32K_CAL_INPROGRESS_MSK   (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
+#define HBN_RC32K_CAL_INPROGRESS_UMSK  (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
+#define HBN_RC32K_CAL_DIV              HBN_RC32K_CAL_DIV
+#define HBN_RC32K_CAL_DIV_POS          (3U)
+#define HBN_RC32K_CAL_DIV_LEN          (2U)
+#define HBN_RC32K_CAL_DIV_MSK          (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
+#define HBN_RC32K_CAL_DIV_UMSK         (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
+#define HBN_RC32K_CAL_PRECHARGE        HBN_RC32K_CAL_PRECHARGE
+#define HBN_RC32K_CAL_PRECHARGE_POS    (5U)
+#define HBN_RC32K_CAL_PRECHARGE_LEN    (1U)
+#define HBN_RC32K_CAL_PRECHARGE_MSK    (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
+#define HBN_RC32K_CAL_PRECHARGE_UMSK   (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
+#define HBN_RC32K_DIG_CODE_FR_CAL      HBN_RC32K_DIG_CODE_FR_CAL
+#define HBN_RC32K_DIG_CODE_FR_CAL_POS  (6U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_LEN  (10U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_MSK  (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
+#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
+#define HBN_RC32K_VREF_DLY             HBN_RC32K_VREF_DLY
+#define HBN_RC32K_VREF_DLY_POS         (16U)
+#define HBN_RC32K_VREF_DLY_LEN         (2U)
+#define HBN_RC32K_VREF_DLY_MSK         (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
+#define HBN_RC32K_VREF_DLY_UMSK        (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
+#define HBN_RC32K_ALLOW_CAL            HBN_RC32K_ALLOW_CAL
+#define HBN_RC32K_ALLOW_CAL_POS        (18U)
+#define HBN_RC32K_ALLOW_CAL_LEN        (1U)
+#define HBN_RC32K_ALLOW_CAL_MSK        (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
+#define HBN_RC32K_ALLOW_CAL_UMSK       (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
+#define HBN_RC32K_EXT_CODE_EN          HBN_RC32K_EXT_CODE_EN
+#define HBN_RC32K_EXT_CODE_EN_POS      (19U)
+#define HBN_RC32K_EXT_CODE_EN_LEN      (1U)
+#define HBN_RC32K_EXT_CODE_EN_MSK      (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
+#define HBN_RC32K_EXT_CODE_EN_UMSK     (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
+#define HBN_RC32K_CAL_EN               HBN_RC32K_CAL_EN
+#define HBN_RC32K_CAL_EN_POS           (20U)
+#define HBN_RC32K_CAL_EN_LEN           (1U)
+#define HBN_RC32K_CAL_EN_MSK           (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
+#define HBN_RC32K_CAL_EN_UMSK          (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
+#define HBN_RC32K_CODE_FR_EXT          HBN_RC32K_CODE_FR_EXT
+#define HBN_RC32K_CODE_FR_EXT_POS      (22U)
+#define HBN_RC32K_CODE_FR_EXT_LEN      (10U)
+#define HBN_RC32K_CODE_FR_EXT_MSK      (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
+#define HBN_RC32K_CODE_FR_EXT_UMSK     (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
+
+/* 0x204 : xtal32k */
+#define HBN_XTAL32K_OFFSET            (0x204)
+#define HBN_XTAL32K_EXT_SEL           HBN_XTAL32K_EXT_SEL
+#define HBN_XTAL32K_EXT_SEL_POS       (2U)
+#define HBN_XTAL32K_EXT_SEL_LEN       (1U)
+#define HBN_XTAL32K_EXT_SEL_MSK       (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
+#define HBN_XTAL32K_EXT_SEL_UMSK      (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
+#define HBN_XTAL32K_AMP_CTRL          HBN_XTAL32K_AMP_CTRL
+#define HBN_XTAL32K_AMP_CTRL_POS      (3U)
+#define HBN_XTAL32K_AMP_CTRL_LEN      (2U)
+#define HBN_XTAL32K_AMP_CTRL_MSK      (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
+#define HBN_XTAL32K_AMP_CTRL_UMSK     (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
+#define HBN_XTAL32K_REG               HBN_XTAL32K_REG
+#define HBN_XTAL32K_REG_POS           (5U)
+#define HBN_XTAL32K_REG_LEN           (2U)
+#define HBN_XTAL32K_REG_MSK           (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
+#define HBN_XTAL32K_REG_UMSK          (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
+#define HBN_XTAL32K_OUTBUF_STRE       HBN_XTAL32K_OUTBUF_STRE
+#define HBN_XTAL32K_OUTBUF_STRE_POS   (7U)
+#define HBN_XTAL32K_OUTBUF_STRE_LEN   (1U)
+#define HBN_XTAL32K_OUTBUF_STRE_MSK   (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
+#define HBN_XTAL32K_OUTBUF_STRE_UMSK  (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
+#define HBN_XTAL32K_OTF_SHORT         HBN_XTAL32K_OTF_SHORT
+#define HBN_XTAL32K_OTF_SHORT_POS     (8U)
+#define HBN_XTAL32K_OTF_SHORT_LEN     (1U)
+#define HBN_XTAL32K_OTF_SHORT_MSK     (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
+#define HBN_XTAL32K_OTF_SHORT_UMSK    (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
+#define HBN_XTAL32K_INV_STRE          HBN_XTAL32K_INV_STRE
+#define HBN_XTAL32K_INV_STRE_POS      (9U)
+#define HBN_XTAL32K_INV_STRE_LEN      (2U)
+#define HBN_XTAL32K_INV_STRE_MSK      (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
+#define HBN_XTAL32K_INV_STRE_UMSK     (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
+#define HBN_XTAL32K_CAPBANK           HBN_XTAL32K_CAPBANK
+#define HBN_XTAL32K_CAPBANK_POS       (11U)
+#define HBN_XTAL32K_CAPBANK_LEN       (6U)
+#define HBN_XTAL32K_CAPBANK_MSK       (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
+#define HBN_XTAL32K_CAPBANK_UMSK      (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
+#define HBN_XTAL32K_AC_CAP_SHORT      HBN_XTAL32K_AC_CAP_SHORT
+#define HBN_XTAL32K_AC_CAP_SHORT_POS  (17U)
+#define HBN_XTAL32K_AC_CAP_SHORT_LEN  (1U)
+#define HBN_XTAL32K_AC_CAP_SHORT_MSK  (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
+#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
+#define HBN_PU_XTAL32K_BUF            HBN_PU_XTAL32K_BUF
+#define HBN_PU_XTAL32K_BUF_POS        (18U)
+#define HBN_PU_XTAL32K_BUF_LEN        (1U)
+#define HBN_PU_XTAL32K_BUF_MSK        (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
+#define HBN_PU_XTAL32K_BUF_UMSK       (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
+#define HBN_PU_XTAL32K                HBN_PU_XTAL32K
+#define HBN_PU_XTAL32K_POS            (19U)
+#define HBN_PU_XTAL32K_LEN            (1U)
+#define HBN_PU_XTAL32K_MSK            (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
+#define HBN_PU_XTAL32K_UMSK           (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
+
+struct hbn_reg {
+    /* 0x0 : HBN_CTL */
+    union {
+        struct
+        {
+            uint32_t rtc_ctl                  : 7; /* [ 6: 0],        r/w,        0x0 */
+            uint32_t hbn_mode                 : 1; /* [    7],          w,        0x0 */
+            uint32_t trap_mode                : 1; /* [    8],          r,        0x0 */
+            uint32_t pwrdn_hbn_core           : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10              : 1; /* [   10],       rsvd,        0x0 */
+            uint32_t pwrdn_hbn_rtc            : 1; /* [   11],        r/w,        0x0 */
+            uint32_t sw_rst                   : 1; /* [   12],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [   14],        r/w,        0x0 */
+            uint32_t hbn_ldo11_rt_vout_sel    : 4; /* [18:15],        r/w,        0xa */
+            uint32_t hbn_ldo11_aon_vout_sel   : 4; /* [22:19],        r/w,        0xa */
+            uint32_t pu_dcdc18_aon            : 1; /* [   23],        r/w,        0x1 */
+            uint32_t rtc_dly_option           : 1; /* [   24],        r/w,        0x0 */
+            uint32_t pwr_on_option            : 1; /* [   25],        r/w,        0x0 */
+            uint32_t sram_slp_option          : 1; /* [   26],        r/w,        0x0 */
+            uint32_t sram_slp                 : 1; /* [   27],          r,        0x0 */
+            uint32_t hbn_state                : 4; /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_CTL;
+
+    /* 0x4 : HBN_TIME_L */
+    union {
+        struct
+        {
+            uint32_t hbn_time_l : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_L;
+
+    /* 0x8 : HBN_TIME_H */
+    union {
+        struct
+        {
+            uint32_t hbn_time_h    : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_H;
+
+    /* 0xC : RTC_TIME_L */
+    union {
+        struct
+        {
+            uint32_t rtc_time_latch_l : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_L;
+
+    /* 0x10 : RTC_TIME_H */
+    union {
+        struct
+        {
+            uint32_t rtc_time_latch_h : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_30    : 23; /* [30: 8],       rsvd,        0x0 */
+            uint32_t rtc_time_latch   : 1;  /* [   31],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_H;
+
+    /* 0x14 : HBN_IRQ_MODE */
+    union {
+        struct
+        {
+            uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0],        r/w,        0x5 */
+            uint32_t hbn_pin_wakeup_mask : 2; /* [ 4: 3],        r/w,        0x0 */
+            uint32_t reserved_5_7        : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t reg_aon_pad_ie_smt  : 1; /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_15       : 7; /* [15: 9],       rsvd,        0x0 */
+            uint32_t reg_en_hw_pu_pd     : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reserved_17         : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t irq_bor_en          : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t irq_acomp0_en       : 2; /* [21:20],        r/w,        0x0 */
+            uint32_t irq_acomp1_en       : 2; /* [23:22],        r/w,        0x0 */
+            uint32_t pin_wakeup_sel      : 3; /* [26:24],        r/w,        0x3 */
+            uint32_t pin_wakeup_en       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reserved_28_31      : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_MODE;
+
+    /* 0x18 : HBN_IRQ_STAT */
+    union {
+        struct
+        {
+            uint32_t irq_stat : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_STAT;
+
+    /* 0x1C : HBN_IRQ_CLR */
+    union {
+        struct
+        {
+            uint32_t irq_clr : 32; /* [31: 0],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_CLR;
+
+    /* 0x20 : HBN_PIR_CFG */
+    union {
+        struct
+        {
+            uint32_t pir_hpf_sel    : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pir_lpf_sel    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3     : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t pir_dis        : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6     : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t pir_en         : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_cgen     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_nosync   : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_CFG;
+
+    /* 0x24 : HBN_PIR_VTH */
+    union {
+        struct
+        {
+            uint32_t pir_vth        : 14; /* [13: 0],        r/w,      0x3ff */
+            uint32_t reserved_14_31 : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_VTH;
+
+    /* 0x28 : HBN_PIR_INTERVAL */
+    union {
+        struct
+        {
+            uint32_t pir_interval   : 12; /* [11: 0],        r/w,      0xa3d */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_INTERVAL;
+
+    /* 0x2C : HBN_BOR_CFG */
+    union {
+        struct
+        {
+            uint32_t bor_sel       : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t bor_vth       : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t pu_bor        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t r_bor_out     : 1;  /* [    3],          r,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_BOR_CFG;
+
+    /* 0x30 : HBN_GLB */
+    union {
+        struct
+        {
+            uint32_t hbn_root_clk_sel         : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t hbn_uart_clk_sel         : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t hbn_f32k_sel             : 2;  /* [ 4: 3],        r/w,        0x0 */
+            uint32_t hbn_pu_rc32k             : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_15            : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t sw_ldo11soc_vout_sel_aon : 4;  /* [19:16],        r/w,        0xa */
+            uint32_t reserved_20_23           : 4;  /* [23:20],       rsvd,        0x0 */
+            uint32_t sw_ldo11_rt_vout_sel     : 4;  /* [27:24],        r/w,        0xa */
+            uint32_t sw_ldo11_aon_vout_sel    : 4;  /* [31:28],        r/w,        0xa */
+        } BF;
+        uint32_t WORD;
+    } HBN_GLB;
+
+    /* 0x34 : HBN_SRAM */
+    union {
+        struct
+        {
+            uint32_t reserved_0_5  : 6;  /* [ 5: 0],       rsvd,        0x0 */
+            uint32_t retram_ret    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t retram_slp    : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_SRAM;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[200];
+
+    /* 0x100 : HBN_RSV0 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV0;
+
+    /* 0x104 : HBN_RSV1 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV1;
+
+    /* 0x108 : HBN_RSV2 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV2;
+
+    /* 0x10C : HBN_RSV3 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV3 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV3;
+
+    /* 0x110  reserved */
+    uint8_t RESERVED0x110[240];
+
+    /* 0x200 : rc32k_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t rc32k_cal_done        : 1;  /* [    0],          r,        0x1 */
+            uint32_t rc32k_rdy             : 1;  /* [    1],          r,        0x1 */
+            uint32_t rc32k_cal_inprogress  : 1;  /* [    2],          r,        0x0 */
+            uint32_t rc32k_cal_div         : 2;  /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32k_cal_precharge   : 1;  /* [    5],          r,        0x0 */
+            uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6],          r,      0x200 */
+            uint32_t rc32k_vref_dly        : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t rc32k_allow_cal       : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t rc32k_ext_code_en     : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t rc32k_cal_en          : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21           : 1;  /* [   21],       rsvd,        0x0 */
+            uint32_t rc32k_code_fr_ext     : 10; /* [31:22],        r/w,      0x140 */
+        } BF;
+        uint32_t WORD;
+    } rc32k_ctrl0;
+
+    /* 0x204 : xtal32k */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1         : 2;  /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t xtal32k_ext_sel      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t xtal32k_amp_ctrl     : 2;  /* [ 4: 3],        r/w,        0x1 */
+            uint32_t xtal32k_reg          : 2;  /* [ 6: 5],        r/w,        0x1 */
+            uint32_t xtal32k_outbuf_stre  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t xtal32k_otf_short    : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t xtal32k_inv_stre     : 2;  /* [10: 9],        r/w,        0x1 */
+            uint32_t xtal32k_capbank      : 6;  /* [16:11],        r/w,       0x20 */
+            uint32_t xtal32k_ac_cap_short : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t pu_xtal32k_buf       : 1;  /* [   18],        r/w,        0x1 */
+            uint32_t pu_xtal32k           : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } xtal32k;
+};
+
+typedef volatile struct hbn_reg hbn_reg_t;
+
+#endif /* __HBN_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/l1c_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/l1c_reg.h
new file mode 100755
index 0000000000..2c618383c8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/l1c_reg.h
@@ -0,0 +1,318 @@
+/**
+  ******************************************************************************
+  * @file    l1c_reg.h
+  * @version V1.2
+  * @date    2019-11-22
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __L1C_REG_H__
+#define __L1C_REG_H__
+
+#include "bl602.h"
+
+/* 0x0 : l1c_config */
+#define L1C_CONFIG_OFFSET            (0x0)
+#define L1C_CACHEABLE                L1C_CACHEABLE
+#define L1C_CACHEABLE_POS            (0U)
+#define L1C_CACHEABLE_LEN            (1U)
+#define L1C_CACHEABLE_MSK            (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)
+#define L1C_CACHEABLE_UMSK           (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS))
+#define L1C_CNT_EN                   L1C_CNT_EN
+#define L1C_CNT_EN_POS               (1U)
+#define L1C_CNT_EN_LEN               (1U)
+#define L1C_CNT_EN_MSK               (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)
+#define L1C_CNT_EN_UMSK              (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS))
+#define L1C_INVALID_EN               L1C_INVALID_EN
+#define L1C_INVALID_EN_POS           (2U)
+#define L1C_INVALID_EN_LEN           (1U)
+#define L1C_INVALID_EN_MSK           (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)
+#define L1C_INVALID_EN_UMSK          (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS))
+#define L1C_INVALID_DONE             L1C_INVALID_DONE
+#define L1C_INVALID_DONE_POS         (3U)
+#define L1C_INVALID_DONE_LEN         (1U)
+#define L1C_INVALID_DONE_MSK         (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)
+#define L1C_INVALID_DONE_UMSK        (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS))
+#define L1C_WAY_DIS                  L1C_WAY_DIS
+#define L1C_WAY_DIS_POS              (8U)
+#define L1C_WAY_DIS_LEN              (4U)
+#define L1C_WAY_DIS_MSK              (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)
+#define L1C_WAY_DIS_UMSK             (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS))
+#define L1C_IROM_2T_ACCESS           L1C_IROM_2T_ACCESS
+#define L1C_IROM_2T_ACCESS_POS       (12U)
+#define L1C_IROM_2T_ACCESS_LEN       (1U)
+#define L1C_IROM_2T_ACCESS_MSK       (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)
+#define L1C_IROM_2T_ACCESS_UMSK      (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS))
+#define L1C_BYPASS                   L1C_BYPASS
+#define L1C_BYPASS_POS               (14U)
+#define L1C_BYPASS_LEN               (1U)
+#define L1C_BYPASS_MSK               (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)
+#define L1C_BYPASS_UMSK              (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS))
+#define L1C_BMX_ERR_EN               L1C_BMX_ERR_EN
+#define L1C_BMX_ERR_EN_POS           (15U)
+#define L1C_BMX_ERR_EN_LEN           (1U)
+#define L1C_BMX_ERR_EN_MSK           (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)
+#define L1C_BMX_ERR_EN_UMSK          (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS))
+#define L1C_BMX_ARB_MODE             L1C_BMX_ARB_MODE
+#define L1C_BMX_ARB_MODE_POS         (16U)
+#define L1C_BMX_ARB_MODE_LEN         (2U)
+#define L1C_BMX_ARB_MODE_MSK         (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)
+#define L1C_BMX_ARB_MODE_UMSK        (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS))
+#define L1C_BMX_TIMEOUT_EN           L1C_BMX_TIMEOUT_EN
+#define L1C_BMX_TIMEOUT_EN_POS       (20U)
+#define L1C_BMX_TIMEOUT_EN_LEN       (4U)
+#define L1C_BMX_TIMEOUT_EN_MSK       (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)
+#define L1C_BMX_TIMEOUT_EN_UMSK      (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS))
+#define L1C_BMX_BUSY_OPTION_DIS      L1C_BMX_BUSY_OPTION_DIS
+#define L1C_BMX_BUSY_OPTION_DIS_POS  (24U)
+#define L1C_BMX_BUSY_OPTION_DIS_LEN  (1U)
+#define L1C_BMX_BUSY_OPTION_DIS_MSK  (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)
+#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS))
+#define L1C_EARLY_RESP_DIS           L1C_EARLY_RESP_DIS
+#define L1C_EARLY_RESP_DIS_POS       (25U)
+#define L1C_EARLY_RESP_DIS_LEN       (1U)
+#define L1C_EARLY_RESP_DIS_MSK       (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)
+#define L1C_EARLY_RESP_DIS_UMSK      (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS))
+#define L1C_WRAP_DIS                 L1C_WRAP_DIS
+#define L1C_WRAP_DIS_POS             (26U)
+#define L1C_WRAP_DIS_LEN             (1U)
+#define L1C_WRAP_DIS_MSK             (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)
+#define L1C_WRAP_DIS_UMSK            (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS))
+
+/* 0x4 : hit_cnt_lsb */
+#define L1C_HIT_CNT_LSB_OFFSET (0x4)
+#define L1C_HIT_CNT_LSB        L1C_HIT_CNT_LSB
+#define L1C_HIT_CNT_LSB_POS    (0U)
+#define L1C_HIT_CNT_LSB_LEN    (32U)
+#define L1C_HIT_CNT_LSB_MSK    (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)
+#define L1C_HIT_CNT_LSB_UMSK   (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS))
+
+/* 0x8 : hit_cnt_msb */
+#define L1C_HIT_CNT_MSB_OFFSET (0x8)
+#define L1C_HIT_CNT_MSB        L1C_HIT_CNT_MSB
+#define L1C_HIT_CNT_MSB_POS    (0U)
+#define L1C_HIT_CNT_MSB_LEN    (32U)
+#define L1C_HIT_CNT_MSB_MSK    (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)
+#define L1C_HIT_CNT_MSB_UMSK   (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS))
+
+/* 0xC : miss_cnt */
+#define L1C_MISS_CNT_OFFSET (0xC)
+#define L1C_MISS_CNT        L1C_MISS_CNT
+#define L1C_MISS_CNT_POS    (0U)
+#define L1C_MISS_CNT_LEN    (32U)
+#define L1C_MISS_CNT_MSK    (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)
+#define L1C_MISS_CNT_UMSK   (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS))
+
+/* 0x10 : l1c_range */
+#define L1C_RANGE_OFFSET (0x10)
+
+/* 0x200 : l1c_bmx_err_addr_en */
+#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200)
+#define L1C_BMX_ERR_ADDR_DIS       L1C_BMX_ERR_ADDR_DIS
+#define L1C_BMX_ERR_ADDR_DIS_POS   (0U)
+#define L1C_BMX_ERR_ADDR_DIS_LEN   (1U)
+#define L1C_BMX_ERR_ADDR_DIS_MSK   (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)
+#define L1C_BMX_ERR_ADDR_DIS_UMSK  (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS))
+#define L1C_BMX_ERR_DEC            L1C_BMX_ERR_DEC
+#define L1C_BMX_ERR_DEC_POS        (4U)
+#define L1C_BMX_ERR_DEC_LEN        (1U)
+#define L1C_BMX_ERR_DEC_MSK        (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)
+#define L1C_BMX_ERR_DEC_UMSK       (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS))
+#define L1C_BMX_ERR_TZ             L1C_BMX_ERR_TZ
+#define L1C_BMX_ERR_TZ_POS         (5U)
+#define L1C_BMX_ERR_TZ_LEN         (1U)
+#define L1C_BMX_ERR_TZ_MSK         (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)
+#define L1C_BMX_ERR_TZ_UMSK        (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS))
+#define L1C_HSEL_OPTION            L1C_HSEL_OPTION
+#define L1C_HSEL_OPTION_POS        (16U)
+#define L1C_HSEL_OPTION_LEN        (4U)
+#define L1C_HSEL_OPTION_MSK        (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)
+#define L1C_HSEL_OPTION_UMSK       (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS))
+
+/* 0x204 : l1c_bmx_err_addr */
+#define L1C_BMX_ERR_ADDR_OFFSET (0x204)
+#define L1C_BMX_ERR_ADDR        L1C_BMX_ERR_ADDR
+#define L1C_BMX_ERR_ADDR_POS    (0U)
+#define L1C_BMX_ERR_ADDR_LEN    (32U)
+#define L1C_BMX_ERR_ADDR_MSK    (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)
+#define L1C_BMX_ERR_ADDR_UMSK   (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS))
+
+/* 0x208 : irom1_misr_dataout_0 */
+#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
+#define L1C_IROM1_MISR_DATAOUT_0        L1C_IROM1_MISR_DATAOUT_0
+#define L1C_IROM1_MISR_DATAOUT_0_POS    (0U)
+#define L1C_IROM1_MISR_DATAOUT_0_LEN    (32U)
+#define L1C_IROM1_MISR_DATAOUT_0_MSK    (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)
+#define L1C_IROM1_MISR_DATAOUT_0_UMSK   (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS))
+
+/* 0x20C : irom1_misr_dataout_1 */
+#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
+
+/* 0x210 : cpu_clk_gate */
+#define L1C_CPU_CLK_GATE_OFFSET       (0x210)
+#define L1C_FORCE_E21_CLOCK_ON_0      L1C_FORCE_E21_CLOCK_ON_0
+#define L1C_FORCE_E21_CLOCK_ON_0_POS  (0U)
+#define L1C_FORCE_E21_CLOCK_ON_0_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_0_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)
+#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS))
+#define L1C_FORCE_E21_CLOCK_ON_1      L1C_FORCE_E21_CLOCK_ON_1
+#define L1C_FORCE_E21_CLOCK_ON_1_POS  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_1_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_1_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)
+#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS))
+#define L1C_FORCE_E21_CLOCK_ON_2      L1C_FORCE_E21_CLOCK_ON_2
+#define L1C_FORCE_E21_CLOCK_ON_2_POS  (2U)
+#define L1C_FORCE_E21_CLOCK_ON_2_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_2_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)
+#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS))
+
+struct l1c_reg {
+    /* 0x0 : l1c_config */
+    union {
+        struct
+        {
+            uint32_t l1c_cacheable           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t l1c_cnt_en              : 1; /* [    1],        r/w,        0x0 */
+            uint32_t l1c_invalid_en          : 1; /* [    2],        r/w,        0x0 */
+            uint32_t l1c_invalid_done        : 1; /* [    3],          r,        0x0 */
+            uint32_t reserved_4_7            : 4; /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t l1c_way_dis             : 4; /* [11: 8],        r/w,        0xf */
+            uint32_t irom_2t_access          : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13             : 1; /* [   13],       rsvd,        0x0 */
+            uint32_t l1c_bypass              : 1; /* [   14],        r/w,        0x0 */
+            uint32_t l1c_bmx_err_en          : 1; /* [   15],        r/w,        0x0 */
+            uint32_t l1c_bmx_arb_mode        : 2; /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_19          : 2; /* [19:18],       rsvd,        0x0 */
+            uint32_t l1c_bmx_timeout_en      : 4; /* [23:20],        r/w,        0x0 */
+            uint32_t l1c_bmx_busy_option_dis : 1; /* [   24],        r/w,        0x0 */
+            uint32_t early_resp_dis          : 1; /* [   25],        r/w,        0x1 */
+            uint32_t wrap_dis                : 1; /* [   26],        r/w,        0x1 */
+            uint32_t reserved_27_31          : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_config;
+
+    /* 0x4 : hit_cnt_lsb */
+    union {
+        struct
+        {
+            uint32_t hit_cnt_lsb : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hit_cnt_lsb;
+
+    /* 0x8 : hit_cnt_msb */
+    union {
+        struct
+        {
+            uint32_t hit_cnt_msb : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hit_cnt_msb;
+
+    /* 0xC : miss_cnt */
+    union {
+        struct
+        {
+            uint32_t miss_cnt : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } miss_cnt;
+
+    /* 0x10 : l1c_range */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_range;
+
+    /* 0x14  reserved */
+    uint8_t RESERVED0x14[492];
+
+    /* 0x200 : l1c_bmx_err_addr_en */
+    union {
+        struct
+        {
+            uint32_t l1c_bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t l1c_bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
+            uint32_t l1c_bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_15        : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t l1c_hsel_option      : 4;  /* [19:16],        r/w,        0x0 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_bmx_err_addr_en;
+
+    /* 0x204 : l1c_bmx_err_addr */
+    union {
+        struct
+        {
+            uint32_t l1c_bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_bmx_err_addr;
+
+    /* 0x208 : irom1_misr_dataout_0 */
+    union {
+        struct
+        {
+            uint32_t irom1_misr_dataout_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_0;
+
+    /* 0x20C : irom1_misr_dataout_1 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_1;
+
+    /* 0x210 : cpu_clk_gate */
+    union {
+        struct
+        {
+            uint32_t force_e21_clock_on_0 : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t force_e21_clock_on_1 : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t force_e21_clock_on_2 : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31        : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cpu_clk_gate;
+};
+
+typedef volatile struct l1c_reg l1c_reg_t;
+
+#endif /* __L1C_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/pds_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/pds_reg.h
new file mode 100755
index 0000000000..5b5ebe6654
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/pds_reg.h
@@ -0,0 +1,1085 @@
+/**
+  ******************************************************************************
+  * @file    pds_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PDS_REG_H__
+#define __PDS_REG_H__
+
+#include "bl602.h"
+
+/* 0x0 : PDS_CTL */
+#define PDS_CTL_OFFSET                   (0x0)
+#define PDS_START_PS                     PDS_START_PS
+#define PDS_START_PS_POS                 (0U)
+#define PDS_START_PS_LEN                 (1U)
+#define PDS_START_PS_MSK                 (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
+#define PDS_START_PS_UMSK                (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
+#define PDS_CR_SLEEP_FOREVER             PDS_CR_SLEEP_FOREVER
+#define PDS_CR_SLEEP_FOREVER_POS         (1U)
+#define PDS_CR_SLEEP_FOREVER_LEN         (1U)
+#define PDS_CR_SLEEP_FOREVER_MSK         (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
+#define PDS_CR_SLEEP_FOREVER_UMSK        (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
+#define PDS_CR_XTAL_FORCE_OFF            PDS_CR_XTAL_FORCE_OFF
+#define PDS_CR_XTAL_FORCE_OFF_POS        (2U)
+#define PDS_CR_XTAL_FORCE_OFF_LEN        (1U)
+#define PDS_CR_XTAL_FORCE_OFF_MSK        (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
+#define PDS_CR_XTAL_FORCE_OFF_UMSK       (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
+#define PDS_CR_WIFI_PDS_SAVE_STATE       PDS_CR_WIFI_PDS_SAVE_STATE
+#define PDS_CR_WIFI_PDS_SAVE_STATE_POS   (3U)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN   (1U)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK   (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK  (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS))
+#define PDS_CR_PDS_PD_DCDC18             PDS_CR_PDS_PD_DCDC18
+#define PDS_CR_PDS_PD_DCDC18_POS         (4U)
+#define PDS_CR_PDS_PD_DCDC18_LEN         (1U)
+#define PDS_CR_PDS_PD_DCDC18_MSK         (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
+#define PDS_CR_PDS_PD_DCDC18_UMSK        (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
+#define PDS_CR_PDS_PD_BG_SYS             PDS_CR_PDS_PD_BG_SYS
+#define PDS_CR_PDS_PD_BG_SYS_POS         (5U)
+#define PDS_CR_PDS_PD_BG_SYS_LEN         (1U)
+#define PDS_CR_PDS_PD_BG_SYS_MSK         (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
+#define PDS_CR_PDS_PD_BG_SYS_UMSK        (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
+#define PDS_CR_PDS_GATE_CLK              PDS_CR_PDS_GATE_CLK
+#define PDS_CR_PDS_GATE_CLK_POS          (8U)
+#define PDS_CR_PDS_GATE_CLK_LEN          (1U)
+#define PDS_CR_PDS_GATE_CLK_MSK          (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
+#define PDS_CR_PDS_GATE_CLK_UMSK         (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
+#define PDS_CR_PDS_MEM_STBY              PDS_CR_PDS_MEM_STBY
+#define PDS_CR_PDS_MEM_STBY_POS          (9U)
+#define PDS_CR_PDS_MEM_STBY_LEN          (1U)
+#define PDS_CR_PDS_MEM_STBY_MSK          (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
+#define PDS_CR_PDS_MEM_STBY_UMSK         (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
+#define PDS_CR_PDS_ISO_EN                PDS_CR_PDS_ISO_EN
+#define PDS_CR_PDS_ISO_EN_POS            (11U)
+#define PDS_CR_PDS_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_ISO_EN_MSK            (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
+#define PDS_CR_PDS_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
+#define PDS_CR_PDS_WAIT_XTAL_RDY         PDS_CR_PDS_WAIT_XTAL_RDY
+#define PDS_CR_PDS_WAIT_XTAL_RDY_POS     (12U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN     (1U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK     (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK    (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
+#define PDS_CR_PDS_PWR_OFF               PDS_CR_PDS_PWR_OFF
+#define PDS_CR_PDS_PWR_OFF_POS           (13U)
+#define PDS_CR_PDS_PWR_OFF_LEN           (1U)
+#define PDS_CR_PDS_PWR_OFF_MSK           (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
+#define PDS_CR_PDS_PWR_OFF_UMSK          (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
+#define PDS_CR_PDS_PD_XTAL               PDS_CR_PDS_PD_XTAL
+#define PDS_CR_PDS_PD_XTAL_POS           (14U)
+#define PDS_CR_PDS_PD_XTAL_LEN           (1U)
+#define PDS_CR_PDS_PD_XTAL_MSK           (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
+#define PDS_CR_PDS_PD_XTAL_UMSK          (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON      PDS_CR_PDS_SOC_ENB_FORCE_ON
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS  (15U)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN  (1U)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK  (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS))
+#define PDS_CR_PDS_RST_SOC_EN            PDS_CR_PDS_RST_SOC_EN
+#define PDS_CR_PDS_RST_SOC_EN_POS        (16U)
+#define PDS_CR_PDS_RST_SOC_EN_LEN        (1U)
+#define PDS_CR_PDS_RST_SOC_EN_MSK        (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)
+#define PDS_CR_PDS_RST_SOC_EN_UMSK       (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS))
+#define PDS_CR_PDS_RC32M_OFF_DIS         PDS_CR_PDS_RC32M_OFF_DIS
+#define PDS_CR_PDS_RC32M_OFF_DIS_POS     (17U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_LEN     (1U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_MSK     (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
+#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK    (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
+#define PDS_CR_PDS_LDO_VSEL_EN           PDS_CR_PDS_LDO_VSEL_EN
+#define PDS_CR_PDS_LDO_VSEL_EN_POS       (18U)
+#define PDS_CR_PDS_LDO_VSEL_EN_LEN       (1U)
+#define PDS_CR_PDS_LDO_VSEL_EN_MSK       (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)
+#define PDS_CR_PDS_LDO_VSEL_EN_UMSK      (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS))
+#define PDS_CR_NP_WFI_MASK               PDS_CR_NP_WFI_MASK
+#define PDS_CR_NP_WFI_MASK_POS           (21U)
+#define PDS_CR_NP_WFI_MASK_LEN           (1U)
+#define PDS_CR_NP_WFI_MASK_MSK           (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
+#define PDS_CR_NP_WFI_MASK_UMSK          (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
+#define PDS_CR_PDS_PD_LDO11              PDS_CR_PDS_PD_LDO11
+#define PDS_CR_PDS_PD_LDO11_POS          (22U)
+#define PDS_CR_PDS_PD_LDO11_LEN          (1U)
+#define PDS_CR_PDS_PD_LDO11_MSK          (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)
+#define PDS_CR_PDS_PD_LDO11_UMSK         (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS))
+#define PDS_CR_PDS_LDO_VOL               PDS_CR_PDS_LDO_VOL
+#define PDS_CR_PDS_LDO_VOL_POS           (24U)
+#define PDS_CR_PDS_LDO_VOL_LEN           (4U)
+#define PDS_CR_PDS_LDO_VOL_MSK           (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)
+#define PDS_CR_PDS_LDO_VOL_UMSK          (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS))
+#define PDS_CR_PDS_CTRL_RF               PDS_CR_PDS_CTRL_RF
+#define PDS_CR_PDS_CTRL_RF_POS           (28U)
+#define PDS_CR_PDS_CTRL_RF_LEN           (2U)
+#define PDS_CR_PDS_CTRL_RF_MSK           (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
+#define PDS_CR_PDS_CTRL_RF_UMSK          (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
+#define PDS_CR_PDS_CTRL_PLL              PDS_CR_PDS_CTRL_PLL
+#define PDS_CR_PDS_CTRL_PLL_POS          (30U)
+#define PDS_CR_PDS_CTRL_PLL_LEN          (2U)
+#define PDS_CR_PDS_CTRL_PLL_MSK          (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)
+#define PDS_CR_PDS_CTRL_PLL_UMSK         (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS))
+
+/* 0x4 : PDS_TIME1 */
+#define PDS_TIME1_OFFSET           (0x4)
+#define PDS_CR_SLEEP_DURATION      PDS_CR_SLEEP_DURATION
+#define PDS_CR_SLEEP_DURATION_POS  (0U)
+#define PDS_CR_SLEEP_DURATION_LEN  (32U)
+#define PDS_CR_SLEEP_DURATION_MSK  (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
+#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))
+
+/* 0xC : PDS_INT */
+#define PDS_INT_OFFSET                    (0xC)
+#define PDS_RO_PDS_WAKE_INT               PDS_RO_PDS_WAKE_INT
+#define PDS_RO_PDS_WAKE_INT_POS           (0U)
+#define PDS_RO_PDS_WAKE_INT_LEN           (1U)
+#define PDS_RO_PDS_WAKE_INT_MSK           (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
+#define PDS_RO_PDS_WAKE_INT_UMSK          (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
+#define PDS_RO_PDS_IRQ_IN                 PDS_RO_PDS_IRQ_IN
+#define PDS_RO_PDS_IRQ_IN_POS             (1U)
+#define PDS_RO_PDS_IRQ_IN_LEN             (1U)
+#define PDS_RO_PDS_IRQ_IN_MSK             (((1U << PDS_RO_PDS_IRQ_IN_LEN) - 1) << PDS_RO_PDS_IRQ_IN_POS)
+#define PDS_RO_PDS_IRQ_IN_UMSK            (~(((1U << PDS_RO_PDS_IRQ_IN_LEN) - 1) << PDS_RO_PDS_IRQ_IN_POS))
+#define PDS_RO_PDS_RF_DONE_INT            PDS_RO_PDS_RF_DONE_INT
+#define PDS_RO_PDS_RF_DONE_INT_POS        (2U)
+#define PDS_RO_PDS_RF_DONE_INT_LEN        (1U)
+#define PDS_RO_PDS_RF_DONE_INT_MSK        (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
+#define PDS_RO_PDS_RF_DONE_INT_UMSK       (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
+#define PDS_RO_PDS_PLL_DONE_INT           PDS_RO_PDS_PLL_DONE_INT
+#define PDS_RO_PDS_PLL_DONE_INT_POS       (3U)
+#define PDS_RO_PDS_PLL_DONE_INT_LEN       (1U)
+#define PDS_RO_PDS_PLL_DONE_INT_MSK       (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)
+#define PDS_RO_PDS_PLL_DONE_INT_UMSK      (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS))
+#define PDS_CR_PDS_WAKE_INT_MASK          PDS_CR_PDS_WAKE_INT_MASK
+#define PDS_CR_PDS_WAKE_INT_MASK_POS      (8U)
+#define PDS_CR_PDS_WAKE_INT_MASK_LEN      (1U)
+#define PDS_CR_PDS_WAKE_INT_MASK_MSK      (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
+#define PDS_CR_PDS_WAKE_INT_MASK_UMSK     (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
+#define PDS_CR_PDS_IRQ_IN_DIS             PDS_CR_PDS_IRQ_IN_DIS
+#define PDS_CR_PDS_IRQ_IN_DIS_POS         (9U)
+#define PDS_CR_PDS_IRQ_IN_DIS_LEN         (1U)
+#define PDS_CR_PDS_IRQ_IN_DIS_MSK         (((1U << PDS_CR_PDS_IRQ_IN_DIS_LEN) - 1) << PDS_CR_PDS_IRQ_IN_DIS_POS)
+#define PDS_CR_PDS_IRQ_IN_DIS_UMSK        (~(((1U << PDS_CR_PDS_IRQ_IN_DIS_LEN) - 1) << PDS_CR_PDS_IRQ_IN_DIS_POS))
+#define PDS_CR_PDS_RF_DONE_INT_MASK       PDS_CR_PDS_RF_DONE_INT_MASK
+#define PDS_CR_PDS_RF_DONE_INT_MASK_POS   (10U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN   (1U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK   (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK  (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_PLL_DONE_INT_MASK      PDS_CR_PDS_PLL_DONE_INT_MASK
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS  (11U)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN  (1U)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK  (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_INT_CLR                PDS_CR_PDS_INT_CLR
+#define PDS_CR_PDS_INT_CLR_POS            (16U)
+#define PDS_CR_PDS_INT_CLR_LEN            (1U)
+#define PDS_CR_PDS_INT_CLR_MSK            (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
+#define PDS_CR_PDS_INT_CLR_UMSK           (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
+
+/* 0x10 : PDS_CTL2 */
+#define PDS_CTL2_OFFSET                   (0x10)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF       PDS_CR_PDS_FORCE_NP_PWR_OFF
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS   (0U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF       PDS_CR_PDS_FORCE_WB_PWR_OFF
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_POS   (2U)
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_NP_ISO_EN        PDS_CR_PDS_FORCE_NP_ISO_EN
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS    (4U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_WB_ISO_EN        PDS_CR_PDS_FORCE_WB_ISO_EN
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_POS    (6U)
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_NP_PDS_RST       PDS_CR_PDS_FORCE_NP_PDS_RST
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS   (8U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_WB_PDS_RST       PDS_CR_PDS_FORCE_WB_PDS_RST
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_POS   (10U)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY      PDS_CR_PDS_FORCE_NP_MEM_STBY
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS  (12U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY      PDS_CR_PDS_FORCE_WB_MEM_STBY
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_POS  (14U)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK      PDS_CR_PDS_FORCE_NP_GATE_CLK
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS  (16U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK      PDS_CR_PDS_FORCE_WB_GATE_CLK
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_POS  (18U)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS))
+
+/* 0x14 : PDS_CTL3 */
+#define PDS_CTL3_OFFSET                     (0x14)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF       PDS_CR_PDS_FORCE_MISC_PWR_OFF
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN        PDS_CR_PDS_FORCE_MISC_ISO_EN
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_POS    (4U)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST       PDS_CR_PDS_FORCE_MISC_PDS_RST
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS   (7U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY      PDS_CR_PDS_FORCE_MISC_MEM_STBY
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS  (10U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK      PDS_CR_PDS_FORCE_MISC_GATE_CLK
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS  (13U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
+#define PDS_CR_PDS_NP_ISO_EN                PDS_CR_PDS_NP_ISO_EN
+#define PDS_CR_PDS_NP_ISO_EN_POS            (24U)
+#define PDS_CR_PDS_NP_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_NP_ISO_EN_MSK            (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)
+#define PDS_CR_PDS_NP_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS))
+#define PDS_CR_PDS_WB_ISO_EN                PDS_CR_PDS_WB_ISO_EN
+#define PDS_CR_PDS_WB_ISO_EN_POS            (27U)
+#define PDS_CR_PDS_WB_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_WB_ISO_EN_MSK            (((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS)
+#define PDS_CR_PDS_WB_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS))
+#define PDS_CR_PDS_MISC_ISO_EN              PDS_CR_PDS_MISC_ISO_EN
+#define PDS_CR_PDS_MISC_ISO_EN_POS          (30U)
+#define PDS_CR_PDS_MISC_ISO_EN_LEN          (1U)
+#define PDS_CR_PDS_MISC_ISO_EN_MSK          (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_MISC_ISO_EN_UMSK         (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))
+
+/* 0x18 : PDS_CTL4 */
+#define PDS_CTL4_OFFSET               (0x18)
+#define PDS_CR_PDS_NP_PWR_OFF         PDS_CR_PDS_NP_PWR_OFF
+#define PDS_CR_PDS_NP_PWR_OFF_POS     (0U)
+#define PDS_CR_PDS_NP_PWR_OFF_LEN     (1U)
+#define PDS_CR_PDS_NP_PWR_OFF_MSK     (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_NP_PWR_OFF_UMSK    (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_NP_RESET           PDS_CR_PDS_NP_RESET
+#define PDS_CR_PDS_NP_RESET_POS       (1U)
+#define PDS_CR_PDS_NP_RESET_LEN       (1U)
+#define PDS_CR_PDS_NP_RESET_MSK       (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
+#define PDS_CR_PDS_NP_RESET_UMSK      (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
+#define PDS_CR_PDS_NP_MEM_STBY        PDS_CR_PDS_NP_MEM_STBY
+#define PDS_CR_PDS_NP_MEM_STBY_POS    (2U)
+#define PDS_CR_PDS_NP_MEM_STBY_LEN    (1U)
+#define PDS_CR_PDS_NP_MEM_STBY_MSK    (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_NP_MEM_STBY_UMSK   (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_NP_GATE_CLK        PDS_CR_PDS_NP_GATE_CLK
+#define PDS_CR_PDS_NP_GATE_CLK_POS    (3U)
+#define PDS_CR_PDS_NP_GATE_CLK_LEN    (1U)
+#define PDS_CR_PDS_NP_GATE_CLK_MSK    (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_NP_GATE_CLK_UMSK   (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_WB_PWR_OFF         PDS_CR_PDS_WB_PWR_OFF
+#define PDS_CR_PDS_WB_PWR_OFF_POS     (12U)
+#define PDS_CR_PDS_WB_PWR_OFF_LEN     (1U)
+#define PDS_CR_PDS_WB_PWR_OFF_MSK     (((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS)
+#define PDS_CR_PDS_WB_PWR_OFF_UMSK    (~(((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS))
+#define PDS_CR_PDS_WB_RESET           PDS_CR_PDS_WB_RESET
+#define PDS_CR_PDS_WB_RESET_POS       (13U)
+#define PDS_CR_PDS_WB_RESET_LEN       (1U)
+#define PDS_CR_PDS_WB_RESET_MSK       (((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS)
+#define PDS_CR_PDS_WB_RESET_UMSK      (~(((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS))
+#define PDS_CR_PDS_WB_MEM_STBY        PDS_CR_PDS_WB_MEM_STBY
+#define PDS_CR_PDS_WB_MEM_STBY_POS    (14U)
+#define PDS_CR_PDS_WB_MEM_STBY_LEN    (1U)
+#define PDS_CR_PDS_WB_MEM_STBY_MSK    (((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS)
+#define PDS_CR_PDS_WB_MEM_STBY_UMSK   (~(((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS))
+#define PDS_CR_PDS_WB_GATE_CLK        PDS_CR_PDS_WB_GATE_CLK
+#define PDS_CR_PDS_WB_GATE_CLK_POS    (15U)
+#define PDS_CR_PDS_WB_GATE_CLK_LEN    (1U)
+#define PDS_CR_PDS_WB_GATE_CLK_MSK    (((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS)
+#define PDS_CR_PDS_WB_GATE_CLK_UMSK   (~(((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS))
+#define PDS_CR_PDS_MISC_PWR_OFF       PDS_CR_PDS_MISC_PWR_OFF
+#define PDS_CR_PDS_MISC_PWR_OFF_POS   (24U)
+#define PDS_CR_PDS_MISC_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_MISC_RESET         PDS_CR_PDS_MISC_RESET
+#define PDS_CR_PDS_MISC_RESET_POS     (25U)
+#define PDS_CR_PDS_MISC_RESET_LEN     (1U)
+#define PDS_CR_PDS_MISC_RESET_MSK     (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
+#define PDS_CR_PDS_MISC_RESET_UMSK    (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
+#define PDS_CR_PDS_MISC_MEM_STBY      PDS_CR_PDS_MISC_MEM_STBY
+#define PDS_CR_PDS_MISC_MEM_STBY_POS  (26U)
+#define PDS_CR_PDS_MISC_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_MISC_GATE_CLK      PDS_CR_PDS_MISC_GATE_CLK
+#define PDS_CR_PDS_MISC_GATE_CLK_POS  (27U)
+#define PDS_CR_PDS_MISC_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))
+
+/* 0x1C : pds_stat */
+#define PDS_STAT_OFFSET           (0x1C)
+#define PDS_RO_PDS_STATE          PDS_RO_PDS_STATE
+#define PDS_RO_PDS_STATE_POS      (0U)
+#define PDS_RO_PDS_STATE_LEN      (4U)
+#define PDS_RO_PDS_STATE_MSK      (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
+#define PDS_RO_PDS_STATE_UMSK     (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
+#define PDS_RO_PDS_RF_STATE       PDS_RO_PDS_RF_STATE
+#define PDS_RO_PDS_RF_STATE_POS   (8U)
+#define PDS_RO_PDS_RF_STATE_LEN   (4U)
+#define PDS_RO_PDS_RF_STATE_MSK   (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
+#define PDS_RO_PDS_RF_STATE_UMSK  (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
+#define PDS_RO_PDS_PLL_STATE      PDS_RO_PDS_PLL_STATE
+#define PDS_RO_PDS_PLL_STATE_POS  (16U)
+#define PDS_RO_PDS_PLL_STATE_LEN  (2U)
+#define PDS_RO_PDS_PLL_STATE_MSK  (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)
+#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS))
+
+/* 0x20 : pds_ram1 */
+#define PDS_RAM1_OFFSET         (0x20)
+#define PDS_CR_NP_SRAM_PWR      PDS_CR_NP_SRAM_PWR
+#define PDS_CR_NP_SRAM_PWR_POS  (0U)
+#define PDS_CR_NP_SRAM_PWR_LEN  (8U)
+#define PDS_CR_NP_SRAM_PWR_MSK  (((1U << PDS_CR_NP_SRAM_PWR_LEN) - 1) << PDS_CR_NP_SRAM_PWR_POS)
+#define PDS_CR_NP_SRAM_PWR_UMSK (~(((1U << PDS_CR_NP_SRAM_PWR_LEN) - 1) << PDS_CR_NP_SRAM_PWR_POS))
+
+/* 0x300 : rc32m_ctrl0 */
+#define PDS_RC32M_CTRL0_OFFSET         (0x300)
+#define PDS_RC32M_CAL_DONE             PDS_RC32M_CAL_DONE
+#define PDS_RC32M_CAL_DONE_POS         (0U)
+#define PDS_RC32M_CAL_DONE_LEN         (1U)
+#define PDS_RC32M_CAL_DONE_MSK         (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
+#define PDS_RC32M_CAL_DONE_UMSK        (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
+#define PDS_RC32M_RDY                  PDS_RC32M_RDY
+#define PDS_RC32M_RDY_POS              (1U)
+#define PDS_RC32M_RDY_LEN              (1U)
+#define PDS_RC32M_RDY_MSK              (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
+#define PDS_RC32M_RDY_UMSK             (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
+#define PDS_RC32M_CAL_INPROGRESS       PDS_RC32M_CAL_INPROGRESS
+#define PDS_RC32M_CAL_INPROGRESS_POS   (2U)
+#define PDS_RC32M_CAL_INPROGRESS_LEN   (1U)
+#define PDS_RC32M_CAL_INPROGRESS_MSK   (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
+#define PDS_RC32M_CAL_INPROGRESS_UMSK  (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
+#define PDS_RC32M_CAL_DIV              PDS_RC32M_CAL_DIV
+#define PDS_RC32M_CAL_DIV_POS          (3U)
+#define PDS_RC32M_CAL_DIV_LEN          (2U)
+#define PDS_RC32M_CAL_DIV_MSK          (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
+#define PDS_RC32M_CAL_DIV_UMSK         (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
+#define PDS_RC32M_CAL_PRECHARGE        PDS_RC32M_CAL_PRECHARGE
+#define PDS_RC32M_CAL_PRECHARGE_POS    (5U)
+#define PDS_RC32M_CAL_PRECHARGE_LEN    (1U)
+#define PDS_RC32M_CAL_PRECHARGE_MSK    (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
+#define PDS_RC32M_CAL_PRECHARGE_UMSK   (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
+#define PDS_RC32M_DIG_CODE_FR_CAL      PDS_RC32M_DIG_CODE_FR_CAL
+#define PDS_RC32M_DIG_CODE_FR_CAL_POS  (6U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_LEN  (8U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_MSK  (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
+#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
+#define PDS_RC32M_ALLOW_CAL            PDS_RC32M_ALLOW_CAL
+#define PDS_RC32M_ALLOW_CAL_POS        (17U)
+#define PDS_RC32M_ALLOW_CAL_LEN        (1U)
+#define PDS_RC32M_ALLOW_CAL_MSK        (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
+#define PDS_RC32M_ALLOW_CAL_UMSK       (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
+#define PDS_RC32M_REFCLK_HALF          PDS_RC32M_REFCLK_HALF
+#define PDS_RC32M_REFCLK_HALF_POS      (18U)
+#define PDS_RC32M_REFCLK_HALF_LEN      (1U)
+#define PDS_RC32M_REFCLK_HALF_MSK      (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
+#define PDS_RC32M_REFCLK_HALF_UMSK     (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
+#define PDS_RC32M_EXT_CODE_EN          PDS_RC32M_EXT_CODE_EN
+#define PDS_RC32M_EXT_CODE_EN_POS      (19U)
+#define PDS_RC32M_EXT_CODE_EN_LEN      (1U)
+#define PDS_RC32M_EXT_CODE_EN_MSK      (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
+#define PDS_RC32M_EXT_CODE_EN_UMSK     (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
+#define PDS_RC32M_CAL_EN               PDS_RC32M_CAL_EN
+#define PDS_RC32M_CAL_EN_POS           (20U)
+#define PDS_RC32M_CAL_EN_LEN           (1U)
+#define PDS_RC32M_CAL_EN_MSK           (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
+#define PDS_RC32M_CAL_EN_UMSK          (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
+#define PDS_RC32M_PD                   PDS_RC32M_PD
+#define PDS_RC32M_PD_POS               (21U)
+#define PDS_RC32M_PD_LEN               (1U)
+#define PDS_RC32M_PD_MSK               (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
+#define PDS_RC32M_PD_UMSK              (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
+#define PDS_RC32M_CODE_FR_EXT          PDS_RC32M_CODE_FR_EXT
+#define PDS_RC32M_CODE_FR_EXT_POS      (22U)
+#define PDS_RC32M_CODE_FR_EXT_LEN      (8U)
+#define PDS_RC32M_CODE_FR_EXT_MSK      (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
+#define PDS_RC32M_CODE_FR_EXT_UMSK     (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))
+
+/* 0x304 : rc32m_ctrl1 */
+#define PDS_RC32M_CTRL1_OFFSET      (0x304)
+#define PDS_RC32M_TEST_EN           PDS_RC32M_TEST_EN
+#define PDS_RC32M_TEST_EN_POS       (0U)
+#define PDS_RC32M_TEST_EN_LEN       (1U)
+#define PDS_RC32M_TEST_EN_MSK       (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
+#define PDS_RC32M_TEST_EN_UMSK      (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
+#define PDS_RC32M_SOFT_RST          PDS_RC32M_SOFT_RST
+#define PDS_RC32M_SOFT_RST_POS      (1U)
+#define PDS_RC32M_SOFT_RST_LEN      (1U)
+#define PDS_RC32M_SOFT_RST_MSK      (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
+#define PDS_RC32M_SOFT_RST_UMSK     (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
+#define PDS_RC32M_CLK_SOFT_RST      PDS_RC32M_CLK_SOFT_RST
+#define PDS_RC32M_CLK_SOFT_RST_POS  (2U)
+#define PDS_RC32M_CLK_SOFT_RST_LEN  (1U)
+#define PDS_RC32M_CLK_SOFT_RST_MSK  (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
+#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
+#define PDS_RC32M_CLK_INV           PDS_RC32M_CLK_INV
+#define PDS_RC32M_CLK_INV_POS       (3U)
+#define PDS_RC32M_CLK_INV_LEN       (1U)
+#define PDS_RC32M_CLK_INV_MSK       (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
+#define PDS_RC32M_CLK_INV_UMSK      (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
+#define PDS_RC32M_CLK_FORCE_ON      PDS_RC32M_CLK_FORCE_ON
+#define PDS_RC32M_CLK_FORCE_ON_POS  (4U)
+#define PDS_RC32M_CLK_FORCE_ON_LEN  (1U)
+#define PDS_RC32M_CLK_FORCE_ON_MSK  (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
+#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
+#define PDS_RC32M_RESERVED          PDS_RC32M_RESERVED
+#define PDS_RC32M_RESERVED_POS      (24U)
+#define PDS_RC32M_RESERVED_LEN      (8U)
+#define PDS_RC32M_RESERVED_MSK      (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
+#define PDS_RC32M_RESERVED_UMSK     (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))
+
+/* 0x400 : pu_rst_clkpll */
+#define PDS_PU_RST_CLKPLL_OFFSET      (0x400)
+#define PDS_CLKPLL_SDM_RESET          PDS_CLKPLL_SDM_RESET
+#define PDS_CLKPLL_SDM_RESET_POS      (0U)
+#define PDS_CLKPLL_SDM_RESET_LEN      (1U)
+#define PDS_CLKPLL_SDM_RESET_MSK      (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)
+#define PDS_CLKPLL_SDM_RESET_UMSK     (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS))
+#define PDS_CLKPLL_RESET_POSTDIV      PDS_CLKPLL_RESET_POSTDIV
+#define PDS_CLKPLL_RESET_POSTDIV_POS  (1U)
+#define PDS_CLKPLL_RESET_POSTDIV_LEN  (1U)
+#define PDS_CLKPLL_RESET_POSTDIV_MSK  (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)
+#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS))
+#define PDS_CLKPLL_RESET_FBDV         PDS_CLKPLL_RESET_FBDV
+#define PDS_CLKPLL_RESET_FBDV_POS     (2U)
+#define PDS_CLKPLL_RESET_FBDV_LEN     (1U)
+#define PDS_CLKPLL_RESET_FBDV_MSK     (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)
+#define PDS_CLKPLL_RESET_FBDV_UMSK    (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS))
+#define PDS_CLKPLL_RESET_REFDIV       PDS_CLKPLL_RESET_REFDIV
+#define PDS_CLKPLL_RESET_REFDIV_POS   (3U)
+#define PDS_CLKPLL_RESET_REFDIV_LEN   (1U)
+#define PDS_CLKPLL_RESET_REFDIV_MSK   (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)
+#define PDS_CLKPLL_RESET_REFDIV_UMSK  (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS))
+#define PDS_CLKPLL_PU_POSTDIV         PDS_CLKPLL_PU_POSTDIV
+#define PDS_CLKPLL_PU_POSTDIV_POS     (4U)
+#define PDS_CLKPLL_PU_POSTDIV_LEN     (1U)
+#define PDS_CLKPLL_PU_POSTDIV_MSK     (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)
+#define PDS_CLKPLL_PU_POSTDIV_UMSK    (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS))
+#define PDS_CLKPLL_PU_FBDV            PDS_CLKPLL_PU_FBDV
+#define PDS_CLKPLL_PU_FBDV_POS        (5U)
+#define PDS_CLKPLL_PU_FBDV_LEN        (1U)
+#define PDS_CLKPLL_PU_FBDV_MSK        (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)
+#define PDS_CLKPLL_PU_FBDV_UMSK       (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS))
+#define PDS_CLKPLL_PU_CLAMP_OP        PDS_CLKPLL_PU_CLAMP_OP
+#define PDS_CLKPLL_PU_CLAMP_OP_POS    (6U)
+#define PDS_CLKPLL_PU_CLAMP_OP_LEN    (1U)
+#define PDS_CLKPLL_PU_CLAMP_OP_MSK    (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)
+#define PDS_CLKPLL_PU_CLAMP_OP_UMSK   (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS))
+#define PDS_CLKPLL_PU_PFD             PDS_CLKPLL_PU_PFD
+#define PDS_CLKPLL_PU_PFD_POS         (7U)
+#define PDS_CLKPLL_PU_PFD_LEN         (1U)
+#define PDS_CLKPLL_PU_PFD_MSK         (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)
+#define PDS_CLKPLL_PU_PFD_UMSK        (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS))
+#define PDS_CLKPLL_PU_CP              PDS_CLKPLL_PU_CP
+#define PDS_CLKPLL_PU_CP_POS          (8U)
+#define PDS_CLKPLL_PU_CP_LEN          (1U)
+#define PDS_CLKPLL_PU_CP_MSK          (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)
+#define PDS_CLKPLL_PU_CP_UMSK         (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS))
+#define PDS_PU_CLKPLL_SFREG           PDS_PU_CLKPLL_SFREG
+#define PDS_PU_CLKPLL_SFREG_POS       (9U)
+#define PDS_PU_CLKPLL_SFREG_LEN       (1U)
+#define PDS_PU_CLKPLL_SFREG_MSK       (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)
+#define PDS_PU_CLKPLL_SFREG_UMSK      (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS))
+#define PDS_PU_CLKPLL                 PDS_PU_CLKPLL
+#define PDS_PU_CLKPLL_POS             (10U)
+#define PDS_PU_CLKPLL_LEN             (1U)
+#define PDS_PU_CLKPLL_MSK             (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)
+#define PDS_PU_CLKPLL_UMSK            (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS))
+
+/* 0x404 : clkpll_top_ctrl */
+#define PDS_CLKPLL_TOP_CTRL_OFFSET     (0x404)
+#define PDS_CLKPLL_POSTDIV             PDS_CLKPLL_POSTDIV
+#define PDS_CLKPLL_POSTDIV_POS         (0U)
+#define PDS_CLKPLL_POSTDIV_LEN         (7U)
+#define PDS_CLKPLL_POSTDIV_MSK         (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)
+#define PDS_CLKPLL_POSTDIV_UMSK        (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS))
+#define PDS_CLKPLL_REFDIV_RATIO        PDS_CLKPLL_REFDIV_RATIO
+#define PDS_CLKPLL_REFDIV_RATIO_POS    (8U)
+#define PDS_CLKPLL_REFDIV_RATIO_LEN    (4U)
+#define PDS_CLKPLL_REFDIV_RATIO_MSK    (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)
+#define PDS_CLKPLL_REFDIV_RATIO_UMSK   (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS))
+#define PDS_CLKPLL_XTAL_RC32M_SEL      PDS_CLKPLL_XTAL_RC32M_SEL
+#define PDS_CLKPLL_XTAL_RC32M_SEL_POS  (12U)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN  (1U)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK  (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS))
+#define PDS_CLKPLL_REFCLK_SEL          PDS_CLKPLL_REFCLK_SEL
+#define PDS_CLKPLL_REFCLK_SEL_POS      (16U)
+#define PDS_CLKPLL_REFCLK_SEL_LEN      (1U)
+#define PDS_CLKPLL_REFCLK_SEL_MSK      (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)
+#define PDS_CLKPLL_REFCLK_SEL_UMSK     (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS))
+#define PDS_CLKPLL_VG11_SEL            PDS_CLKPLL_VG11_SEL
+#define PDS_CLKPLL_VG11_SEL_POS        (20U)
+#define PDS_CLKPLL_VG11_SEL_LEN        (2U)
+#define PDS_CLKPLL_VG11_SEL_MSK        (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)
+#define PDS_CLKPLL_VG11_SEL_UMSK       (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS))
+#define PDS_CLKPLL_VG13_SEL            PDS_CLKPLL_VG13_SEL
+#define PDS_CLKPLL_VG13_SEL_POS        (24U)
+#define PDS_CLKPLL_VG13_SEL_LEN        (2U)
+#define PDS_CLKPLL_VG13_SEL_MSK        (((1U << PDS_CLKPLL_VG13_SEL_LEN) - 1) << PDS_CLKPLL_VG13_SEL_POS)
+#define PDS_CLKPLL_VG13_SEL_UMSK       (~(((1U << PDS_CLKPLL_VG13_SEL_LEN) - 1) << PDS_CLKPLL_VG13_SEL_POS))
+
+/* 0x408 : clkpll_cp */
+#define PDS_CLKPLL_CP_OFFSET          (0x408)
+#define PDS_CLKPLL_SEL_CP_BIAS        PDS_CLKPLL_SEL_CP_BIAS
+#define PDS_CLKPLL_SEL_CP_BIAS_POS    (0U)
+#define PDS_CLKPLL_SEL_CP_BIAS_LEN    (1U)
+#define PDS_CLKPLL_SEL_CP_BIAS_MSK    (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)
+#define PDS_CLKPLL_SEL_CP_BIAS_UMSK   (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS))
+#define PDS_CLKPLL_ICP_5U             PDS_CLKPLL_ICP_5U
+#define PDS_CLKPLL_ICP_5U_POS         (4U)
+#define PDS_CLKPLL_ICP_5U_LEN         (2U)
+#define PDS_CLKPLL_ICP_5U_MSK         (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)
+#define PDS_CLKPLL_ICP_5U_UMSK        (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS))
+#define PDS_CLKPLL_ICP_1U             PDS_CLKPLL_ICP_1U
+#define PDS_CLKPLL_ICP_1U_POS         (6U)
+#define PDS_CLKPLL_ICP_1U_LEN         (2U)
+#define PDS_CLKPLL_ICP_1U_MSK         (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)
+#define PDS_CLKPLL_ICP_1U_UMSK        (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS))
+#define PDS_CLKPLL_INT_FRAC_SW        PDS_CLKPLL_INT_FRAC_SW
+#define PDS_CLKPLL_INT_FRAC_SW_POS    (8U)
+#define PDS_CLKPLL_INT_FRAC_SW_LEN    (1U)
+#define PDS_CLKPLL_INT_FRAC_SW_MSK    (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)
+#define PDS_CLKPLL_INT_FRAC_SW_UMSK   (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS))
+#define PDS_CLKPLL_CP_STARTUP_EN      PDS_CLKPLL_CP_STARTUP_EN
+#define PDS_CLKPLL_CP_STARTUP_EN_POS  (9U)
+#define PDS_CLKPLL_CP_STARTUP_EN_LEN  (1U)
+#define PDS_CLKPLL_CP_STARTUP_EN_MSK  (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)
+#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS))
+#define PDS_CLKPLL_CP_OPAMP_EN        PDS_CLKPLL_CP_OPAMP_EN
+#define PDS_CLKPLL_CP_OPAMP_EN_POS    (10U)
+#define PDS_CLKPLL_CP_OPAMP_EN_LEN    (1U)
+#define PDS_CLKPLL_CP_OPAMP_EN_MSK    (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)
+#define PDS_CLKPLL_CP_OPAMP_EN_UMSK   (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS))
+
+/* 0x40C : clkpll_rz */
+#define PDS_CLKPLL_RZ_OFFSET     (0x40C)
+#define PDS_CLKPLL_C4_EN         PDS_CLKPLL_C4_EN
+#define PDS_CLKPLL_C4_EN_POS     (0U)
+#define PDS_CLKPLL_C4_EN_LEN     (1U)
+#define PDS_CLKPLL_C4_EN_MSK     (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)
+#define PDS_CLKPLL_C4_EN_UMSK    (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS))
+#define PDS_CLKPLL_R4            PDS_CLKPLL_R4
+#define PDS_CLKPLL_R4_POS        (4U)
+#define PDS_CLKPLL_R4_LEN        (2U)
+#define PDS_CLKPLL_R4_MSK        (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)
+#define PDS_CLKPLL_R4_UMSK       (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS))
+#define PDS_CLKPLL_R4_SHORT      PDS_CLKPLL_R4_SHORT
+#define PDS_CLKPLL_R4_SHORT_POS  (8U)
+#define PDS_CLKPLL_R4_SHORT_LEN  (1U)
+#define PDS_CLKPLL_R4_SHORT_MSK  (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)
+#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS))
+#define PDS_CLKPLL_C3            PDS_CLKPLL_C3
+#define PDS_CLKPLL_C3_POS        (12U)
+#define PDS_CLKPLL_C3_LEN        (2U)
+#define PDS_CLKPLL_C3_MSK        (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)
+#define PDS_CLKPLL_C3_UMSK       (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS))
+#define PDS_CLKPLL_CZ            PDS_CLKPLL_CZ
+#define PDS_CLKPLL_CZ_POS        (14U)
+#define PDS_CLKPLL_CZ_LEN        (2U)
+#define PDS_CLKPLL_CZ_MSK        (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)
+#define PDS_CLKPLL_CZ_UMSK       (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS))
+#define PDS_CLKPLL_RZ            PDS_CLKPLL_RZ
+#define PDS_CLKPLL_RZ_POS        (16U)
+#define PDS_CLKPLL_RZ_LEN        (3U)
+#define PDS_CLKPLL_RZ_MSK        (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)
+#define PDS_CLKPLL_RZ_UMSK       (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS))
+
+/* 0x410 : clkpll_fbdv */
+#define PDS_CLKPLL_FBDV_OFFSET         (0x410)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK      PDS_CLKPLL_SEL_SAMPLE_CLK
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS  (0U)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN  (2U)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK  (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS))
+#define PDS_CLKPLL_SEL_FB_CLK          PDS_CLKPLL_SEL_FB_CLK
+#define PDS_CLKPLL_SEL_FB_CLK_POS      (2U)
+#define PDS_CLKPLL_SEL_FB_CLK_LEN      (2U)
+#define PDS_CLKPLL_SEL_FB_CLK_MSK      (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)
+#define PDS_CLKPLL_SEL_FB_CLK_UMSK     (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS))
+
+/* 0x414 : clkpll_vco */
+#define PDS_CLKPLL_VCO_OFFSET     (0x414)
+#define PDS_CLKPLL_VCO_SPEED      PDS_CLKPLL_VCO_SPEED
+#define PDS_CLKPLL_VCO_SPEED_POS  (0U)
+#define PDS_CLKPLL_VCO_SPEED_LEN  (3U)
+#define PDS_CLKPLL_VCO_SPEED_MSK  (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)
+#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS))
+#define PDS_CLKPLL_SHRTR          PDS_CLKPLL_SHRTR
+#define PDS_CLKPLL_SHRTR_POS      (3U)
+#define PDS_CLKPLL_SHRTR_LEN      (1U)
+#define PDS_CLKPLL_SHRTR_MSK      (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)
+#define PDS_CLKPLL_SHRTR_UMSK     (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS))
+
+/* 0x418 : clkpll_sdm */
+#define PDS_CLKPLL_SDM_OFFSET      (0x418)
+#define PDS_CLKPLL_SDMIN           PDS_CLKPLL_SDMIN
+#define PDS_CLKPLL_SDMIN_POS       (0U)
+#define PDS_CLKPLL_SDMIN_LEN       (24U)
+#define PDS_CLKPLL_SDMIN_MSK       (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)
+#define PDS_CLKPLL_SDMIN_UMSK      (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS))
+#define PDS_CLKPLL_DITHER_SEL      PDS_CLKPLL_DITHER_SEL
+#define PDS_CLKPLL_DITHER_SEL_POS  (24U)
+#define PDS_CLKPLL_DITHER_SEL_LEN  (2U)
+#define PDS_CLKPLL_DITHER_SEL_MSK  (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)
+#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS))
+#define PDS_CLKPLL_SDM_FLAG        PDS_CLKPLL_SDM_FLAG
+#define PDS_CLKPLL_SDM_FLAG_POS    (28U)
+#define PDS_CLKPLL_SDM_FLAG_LEN    (1U)
+#define PDS_CLKPLL_SDM_FLAG_MSK    (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)
+#define PDS_CLKPLL_SDM_FLAG_UMSK   (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS))
+#define PDS_CLKPLL_SDM_BYPASS      PDS_CLKPLL_SDM_BYPASS
+#define PDS_CLKPLL_SDM_BYPASS_POS  (29U)
+#define PDS_CLKPLL_SDM_BYPASS_LEN  (1U)
+#define PDS_CLKPLL_SDM_BYPASS_MSK  (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)
+#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS))
+
+/* 0x41C : clkpll_output_en */
+#define PDS_CLKPLL_OUTPUT_EN_OFFSET  (0x41C)
+#define PDS_CLKPLL_EN_480M           PDS_CLKPLL_EN_480M
+#define PDS_CLKPLL_EN_480M_POS       (0U)
+#define PDS_CLKPLL_EN_480M_LEN       (1U)
+#define PDS_CLKPLL_EN_480M_MSK       (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)
+#define PDS_CLKPLL_EN_480M_UMSK      (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS))
+#define PDS_CLKPLL_EN_240M           PDS_CLKPLL_EN_240M
+#define PDS_CLKPLL_EN_240M_POS       (1U)
+#define PDS_CLKPLL_EN_240M_LEN       (1U)
+#define PDS_CLKPLL_EN_240M_MSK       (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)
+#define PDS_CLKPLL_EN_240M_UMSK      (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS))
+#define PDS_CLKPLL_EN_192M           PDS_CLKPLL_EN_192M
+#define PDS_CLKPLL_EN_192M_POS       (2U)
+#define PDS_CLKPLL_EN_192M_LEN       (1U)
+#define PDS_CLKPLL_EN_192M_MSK       (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)
+#define PDS_CLKPLL_EN_192M_UMSK      (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS))
+#define PDS_CLKPLL_EN_160M           PDS_CLKPLL_EN_160M
+#define PDS_CLKPLL_EN_160M_POS       (3U)
+#define PDS_CLKPLL_EN_160M_LEN       (1U)
+#define PDS_CLKPLL_EN_160M_MSK       (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)
+#define PDS_CLKPLL_EN_160M_UMSK      (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS))
+#define PDS_CLKPLL_EN_120M           PDS_CLKPLL_EN_120M
+#define PDS_CLKPLL_EN_120M_POS       (4U)
+#define PDS_CLKPLL_EN_120M_LEN       (1U)
+#define PDS_CLKPLL_EN_120M_MSK       (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)
+#define PDS_CLKPLL_EN_120M_UMSK      (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS))
+#define PDS_CLKPLL_EN_96M            PDS_CLKPLL_EN_96M
+#define PDS_CLKPLL_EN_96M_POS        (5U)
+#define PDS_CLKPLL_EN_96M_LEN        (1U)
+#define PDS_CLKPLL_EN_96M_MSK        (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)
+#define PDS_CLKPLL_EN_96M_UMSK       (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS))
+#define PDS_CLKPLL_EN_80M            PDS_CLKPLL_EN_80M
+#define PDS_CLKPLL_EN_80M_POS        (6U)
+#define PDS_CLKPLL_EN_80M_LEN        (1U)
+#define PDS_CLKPLL_EN_80M_MSK        (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)
+#define PDS_CLKPLL_EN_80M_UMSK       (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS))
+#define PDS_CLKPLL_EN_48M            PDS_CLKPLL_EN_48M
+#define PDS_CLKPLL_EN_48M_POS        (7U)
+#define PDS_CLKPLL_EN_48M_LEN        (1U)
+#define PDS_CLKPLL_EN_48M_MSK        (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)
+#define PDS_CLKPLL_EN_48M_UMSK       (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS))
+#define PDS_CLKPLL_EN_32M            PDS_CLKPLL_EN_32M
+#define PDS_CLKPLL_EN_32M_POS        (8U)
+#define PDS_CLKPLL_EN_32M_LEN        (1U)
+#define PDS_CLKPLL_EN_32M_MSK        (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)
+#define PDS_CLKPLL_EN_32M_UMSK       (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS))
+#define PDS_CLKPLL_EN_DIV2_480M      PDS_CLKPLL_EN_DIV2_480M
+#define PDS_CLKPLL_EN_DIV2_480M_POS  (9U)
+#define PDS_CLKPLL_EN_DIV2_480M_LEN  (1U)
+#define PDS_CLKPLL_EN_DIV2_480M_MSK  (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)
+#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS))
+
+struct pds_reg {
+    /* 0x0 : PDS_CTL */
+    union {
+        struct
+        {
+            uint32_t pds_start_ps            : 1; /* [    0],        w1p,        0x0 */
+            uint32_t cr_sleep_forever        : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_xtal_force_off       : 1; /* [    2],        r/w,        0x0 */
+            uint32_t cr_wifi_pds_save_state  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t cr_pds_pd_dcdc18        : 1; /* [    4],        r/w,        0x0 */
+            uint32_t cr_pds_pd_bg_sys        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7            : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t cr_pds_gate_clk         : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_pds_mem_stby         : 1; /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10             : 1; /* [   10],       rsvd,        0x0 */
+            uint32_t cr_pds_iso_en           : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_pds_wait_xtal_rdy    : 1; /* [   12],        r/w,        0x0 */
+            uint32_t cr_pds_pwr_off          : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_pd_xtal          : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_soc_enb_force_on : 1; /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_rst_soc_en       : 1; /* [   16],        r/w,        0x0 */
+            uint32_t cr_pds_rc32m_off_dis    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t cr_pds_ldo_vsel_en      : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_20          : 2; /* [20:19],       rsvd,        0x0 */
+            uint32_t cr_np_wfi_mask          : 1; /* [   21],        r/w,        0x0 */
+            uint32_t cr_pds_pd_ldo11         : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t cr_pds_ldo_vol          : 4; /* [27:24],        r/w,        0xa */
+            uint32_t cr_pds_ctrl_rf          : 2; /* [29:28],        r/w,        0x1 */
+            uint32_t cr_pds_ctrl_pll         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL;
+
+    /* 0x4 : PDS_TIME1 */
+    union {
+        struct
+        {
+            uint32_t cr_sleep_duration : 32; /* [31: 0],        r/w,      0xca8 */
+        } BF;
+        uint32_t WORD;
+    } PDS_TIME1;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[4];
+
+    /* 0xC : PDS_INT */
+    union {
+        struct
+        {
+            uint32_t ro_pds_wake_int          : 1;  /* [    0],          r,        0x0 */
+            uint32_t ro_pds_irq_in            : 1;  /* [    1],          r,        0x0 */
+            uint32_t ro_pds_rf_done_int       : 1;  /* [    2],          r,        0x0 */
+            uint32_t ro_pds_pll_done_int      : 1;  /* [    3],          r,        0x0 */
+            uint32_t reserved_4_7             : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t cr_pds_wake_int_mask     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_pds_irq_in_dis        : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t cr_pds_rf_done_int_mask  : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_pll_done_int_mask : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15           : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t cr_pds_int_clr           : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31           : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_INT;
+
+    /* 0x10 : PDS_CTL2 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_force_np_pwr_off  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1               : 1;  /* [    1],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_pwr_off  : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3               : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t cr_pds_force_np_iso_en   : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5               : 1;  /* [    5],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_iso_en   : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t cr_pds_force_np_pds_rst  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9               : 1;  /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_pds_rst  : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11              : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t cr_pds_force_np_mem_stby : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13              : 1;  /* [   13],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_mem_stby : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t reserved_15              : 1;  /* [   15],       rsvd,        0x0 */
+            uint32_t cr_pds_force_np_gate_clk : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17              : 1;  /* [   17],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_gate_clk : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19_31           : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL2;
+
+    /* 0x14 : PDS_CTL3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0                 : 1;  /* [    0],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pwr_off  : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3               : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_iso_en   : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_6               : 2;  /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pds_rst  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_9               : 2;  /* [ 9: 8],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_mem_stby : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_12             : 2;  /* [12:11],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_gate_clk : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_23             : 10; /* [23:14],       rsvd,        0x0 */
+            uint32_t cr_pds_np_iso_en           : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_26             : 2;  /* [26:25],       rsvd,        0x0 */
+            uint32_t cr_pds_wb_iso_en           : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t reserved_28_29             : 2;  /* [29:28],       rsvd,        0x0 */
+            uint32_t cr_pds_misc_iso_en         : 1;  /* [   30],        r/w,        0x1 */
+            uint32_t reserved_31                : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL3;
+
+    /* 0x18 : PDS_CTL4 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_np_pwr_off    : 1; /* [    0],        r/w,        0x1 */
+            uint32_t cr_pds_np_reset      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t cr_pds_np_mem_stby   : 1; /* [    2],        r/w,        0x1 */
+            uint32_t cr_pds_np_gate_clk   : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_11        : 8; /* [11: 4],       rsvd,        0x0 */
+            uint32_t cr_pds_wb_pwr_off    : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_pds_wb_reset      : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_wb_mem_stby   : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_wb_gate_clk   : 1; /* [   15],        r/w,        0x1 */
+            uint32_t reserved_16_23       : 8; /* [23:16],       rsvd,        0x0 */
+            uint32_t cr_pds_misc_pwr_off  : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cr_pds_misc_reset    : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cr_pds_misc_mem_stby : 1; /* [   26],        r/w,        0x1 */
+            uint32_t cr_pds_misc_gate_clk : 1; /* [   27],        r/w,        0x1 */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL4;
+
+    /* 0x1C : pds_stat */
+    union {
+        struct
+        {
+            uint32_t ro_pds_state     : 4;  /* [ 3: 0],          r,        0x0 */
+            uint32_t reserved_4_7     : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t ro_pds_rf_state  : 4;  /* [11: 8],          r,        0x0 */
+            uint32_t reserved_12_15   : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t ro_pds_pll_state : 2;  /* [17:16],          r,        0x0 */
+            uint32_t reserved_18_31   : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_stat;
+
+    /* 0x20 : pds_ram1 */
+    union {
+        struct
+        {
+            uint32_t cr_np_sram_pwr : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_31  : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_ram1;
+
+    /* 0x24  reserved */
+    uint8_t RESERVED0x24[732];
+
+    /* 0x300 : rc32m_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t rc32m_cal_done        : 1; /* [    0],          r,        0x0 */
+            uint32_t rc32m_rdy             : 1; /* [    1],          r,        0x0 */
+            uint32_t rc32m_cal_inprogress  : 1; /* [    2],          r,        0x0 */
+            uint32_t rc32m_cal_div         : 2; /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32m_cal_precharge   : 1; /* [    5],          r,        0x0 */
+            uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6],          r,        0x0 */
+            uint32_t reserved_14_16        : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t rc32m_allow_cal       : 1; /* [   17],        r/w,        0x0 */
+            uint32_t rc32m_refclk_half     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t rc32m_ext_code_en     : 1; /* [   19],        r/w,        0x1 */
+            uint32_t rc32m_cal_en          : 1; /* [   20],        r/w,        0x0 */
+            uint32_t rc32m_pd              : 1; /* [   21],        r/w,        0x0 */
+            uint32_t rc32m_code_fr_ext     : 8; /* [29:22],        r/w,       0x60 */
+            uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl0;
+
+    /* 0x304 : rc32m_ctrl1 */
+    union {
+        struct
+        {
+            uint32_t rc32m_test_en      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t rc32m_soft_rst     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rc32m_clk_soft_rst : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t rc32m_clk_inv      : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t rc32m_clk_force_on : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_23      : 19; /* [23: 5],       rsvd,        0x0 */
+            uint32_t rc32m_reserved     : 8;  /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl1;
+
+    /* 0x308  reserved */
+    uint8_t RESERVED0x308[248];
+
+    /* 0x400 : pu_rst_clkpll */
+    union {
+        struct
+        {
+            uint32_t clkpll_sdm_reset     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t clkpll_reset_postdiv : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t clkpll_reset_fbdv    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t clkpll_reset_refdiv  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t clkpll_pu_postdiv    : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t clkpll_pu_fbdv       : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t clkpll_pu_clamp_op   : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t clkpll_pu_pfd        : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t clkpll_pu_cp         : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t pu_clkpll_sfreg      : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t pu_clkpll            : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pu_rst_clkpll;
+
+    /* 0x404 : clkpll_top_ctrl */
+    union {
+        struct
+        {
+            uint32_t clkpll_postdiv        : 7; /* [ 6: 0],        r/w,       0x14 */
+            uint32_t reserved_7            : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t clkpll_refdiv_ratio   : 4; /* [11: 8],        r/w,        0x4 */
+            uint32_t clkpll_xtal_rc32m_sel : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15        : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t clkpll_refclk_sel     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_19        : 3; /* [19:17],       rsvd,        0x0 */
+            uint32_t clkpll_vg11_sel       : 2; /* [21:20],        r/w,        0x1 */
+            uint32_t reserved_22_23        : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t clkpll_vg13_sel       : 2; /* [25:24],        r/w,        0x1 */
+            uint32_t reserved_26_31        : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_top_ctrl;
+
+    /* 0x408 : clkpll_cp */
+    union {
+        struct
+        {
+            uint32_t clkpll_sel_cp_bias   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t clkpll_icp_5u        : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t clkpll_icp_1u        : 2;  /* [ 7: 6],        r/w,        0x1 */
+            uint32_t clkpll_int_frac_sw   : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t clkpll_cp_startup_en : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t clkpll_cp_opamp_en   : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_cp;
+
+    /* 0x40C : clkpll_rz */
+    union {
+        struct
+        {
+            uint32_t clkpll_c4_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3    : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t clkpll_r4       : 2;  /* [ 5: 4],        r/w,        0x2 */
+            uint32_t reserved_6_7    : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t clkpll_r4_short : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_11   : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t clkpll_c3       : 2;  /* [13:12],        r/w,        0x2 */
+            uint32_t clkpll_cz       : 2;  /* [15:14],        r/w,        0x2 */
+            uint32_t clkpll_rz       : 3;  /* [18:16],        r/w,        0x5 */
+            uint32_t reserved_19_31  : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_rz;
+
+    /* 0x410 : clkpll_fbdv */
+    union {
+        struct
+        {
+            uint32_t clkpll_sel_sample_clk : 2;  /* [ 1: 0],        r/w,        0x1 */
+            uint32_t clkpll_sel_fb_clk     : 2;  /* [ 3: 2],        r/w,        0x1 */
+            uint32_t reserved_4_31         : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_fbdv;
+
+    /* 0x414 : clkpll_vco */
+    union {
+        struct
+        {
+            uint32_t clkpll_vco_speed : 3;  /* [ 2: 0],        r/w,        0x7 */
+            uint32_t clkpll_shrtr     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31    : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_vco;
+
+    /* 0x418 : clkpll_sdm */
+    union {
+        struct
+        {
+            uint32_t clkpll_sdmin      : 24; /* [23: 0],        r/w,   0x600000 */
+            uint32_t clkpll_dither_sel : 2;  /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27    : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t clkpll_sdm_flag   : 1;  /* [   28],        r/w,        0x1 */
+            uint32_t clkpll_sdm_bypass : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31    : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_sdm;
+
+    /* 0x41C : clkpll_output_en */
+    union {
+        struct
+        {
+            uint32_t clkpll_en_480m      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t clkpll_en_240m      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t clkpll_en_192m      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t clkpll_en_160m      : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t clkpll_en_120m      : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t clkpll_en_96m       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t clkpll_en_80m       : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t clkpll_en_48m       : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t clkpll_en_32m       : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t clkpll_en_div2_480m : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31      : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_output_en;
+};
+
+typedef volatile struct pds_reg pds_reg_t;
+
+#endif /* __PDS_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/sf_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/sf_ctrl_reg.h
new file mode 100755
index 0000000000..5c36954592
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/sf_ctrl_reg.h
@@ -0,0 +1,2450 @@
+/**
+  ******************************************************************************
+  * @file    sf_ctrl_reg.h
+  * @version V1.2
+  * @date    2019-10-21
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __SF_CTRL_REG_H__
+#define __SF_CTRL_REG_H__
+
+#include "bl602.h"
+
+/* 0x0 : sf_ctrl_0 */
+#define SF_CTRL_0_OFFSET                  (0x0)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL      SF_CTRL_SF_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS  (2U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN  (1U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_GATE_EN        SF_CTRL_SF_CLK_OUT_GATE_EN
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS    (3U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN    (1U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK    (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS))
+#define SF_CTRL_SF_CLK_OUT_INV_SEL        SF_CTRL_SF_CLK_OUT_INV_SEL
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS    (4U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN    (1U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL      SF_CTRL_SF_CLK_SAHB_SRAM_SEL
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS  (5U)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN  (1U)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS))
+#define SF_CTRL_SF_IF_READ_DLY_N          SF_CTRL_SF_IF_READ_DLY_N
+#define SF_CTRL_SF_IF_READ_DLY_N_POS      (8U)
+#define SF_CTRL_SF_IF_READ_DLY_N_LEN      (3U)
+#define SF_CTRL_SF_IF_READ_DLY_N_MSK      (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)
+#define SF_CTRL_SF_IF_READ_DLY_N_UMSK     (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS))
+#define SF_CTRL_SF_IF_READ_DLY_EN         SF_CTRL_SF_IF_READ_DLY_EN
+#define SF_CTRL_SF_IF_READ_DLY_EN_POS     (11U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_LEN     (1U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_MSK     (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)
+#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS))
+#define SF_CTRL_SF_IF_INT                 SF_CTRL_SF_IF_INT
+#define SF_CTRL_SF_IF_INT_POS             (16U)
+#define SF_CTRL_SF_IF_INT_LEN             (1U)
+#define SF_CTRL_SF_IF_INT_MSK             (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)
+#define SF_CTRL_SF_IF_INT_UMSK            (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS))
+#define SF_CTRL_SF_IF_INT_CLR             SF_CTRL_SF_IF_INT_CLR
+#define SF_CTRL_SF_IF_INT_CLR_POS         (17U)
+#define SF_CTRL_SF_IF_INT_CLR_LEN         (1U)
+#define SF_CTRL_SF_IF_INT_CLR_MSK         (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)
+#define SF_CTRL_SF_IF_INT_CLR_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS))
+#define SF_CTRL_SF_IF_INT_SET             SF_CTRL_SF_IF_INT_SET
+#define SF_CTRL_SF_IF_INT_SET_POS         (18U)
+#define SF_CTRL_SF_IF_INT_SET_LEN         (1U)
+#define SF_CTRL_SF_IF_INT_SET_MSK         (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)
+#define SF_CTRL_SF_IF_INT_SET_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS))
+#define SF_CTRL_SF_AES_DLY_MODE           SF_CTRL_SF_AES_DLY_MODE
+#define SF_CTRL_SF_AES_DLY_MODE_POS       (19U)
+#define SF_CTRL_SF_AES_DLY_MODE_LEN       (1U)
+#define SF_CTRL_SF_AES_DLY_MODE_MSK       (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)
+#define SF_CTRL_SF_AES_DLY_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS))
+#define SF_CTRL_SF_AES_DOUT_ENDIAN        SF_CTRL_SF_AES_DOUT_ENDIAN
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS    (20U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN    (1U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK    (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK   (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS))
+#define SF_CTRL_SF_AES_CTR_PLUS_EN        SF_CTRL_SF_AES_CTR_PLUS_EN
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS    (21U)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN    (1U)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK    (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK   (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS))
+#define SF_CTRL_SF_AES_KEY_ENDIAN         SF_CTRL_SF_AES_KEY_ENDIAN
+#define SF_CTRL_SF_AES_KEY_ENDIAN_POS     (22U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN     (1U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK     (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK    (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS))
+#define SF_CTRL_SF_AES_IV_ENDIAN          SF_CTRL_SF_AES_IV_ENDIAN
+#define SF_CTRL_SF_AES_IV_ENDIAN_POS      (23U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_LEN      (1U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_MSK      (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)
+#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK     (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS))
+#define SF_CTRL_SF_ID                     SF_CTRL_SF_ID
+#define SF_CTRL_SF_ID_POS                 (24U)
+#define SF_CTRL_SF_ID_LEN                 (8U)
+#define SF_CTRL_SF_ID_MSK                 (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)
+#define SF_CTRL_SF_ID_UMSK                (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS))
+
+/* 0x4 : sf_ctrl_1 */
+#define SF_CTRL_1_OFFSET                (0x4)
+#define SF_CTRL_SF_IF_SR_PAT_MASK       SF_CTRL_SF_IF_SR_PAT_MASK
+#define SF_CTRL_SF_IF_SR_PAT_MASK_POS   (0U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN   (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK   (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK  (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS))
+#define SF_CTRL_SF_IF_SR_PAT            SF_CTRL_SF_IF_SR_PAT
+#define SF_CTRL_SF_IF_SR_PAT_POS        (8U)
+#define SF_CTRL_SF_IF_SR_PAT_LEN        (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MSK        (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)
+#define SF_CTRL_SF_IF_SR_PAT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS))
+#define SF_CTRL_SF_IF_SR_INT            SF_CTRL_SF_IF_SR_INT
+#define SF_CTRL_SF_IF_SR_INT_POS        (16U)
+#define SF_CTRL_SF_IF_SR_INT_LEN        (1U)
+#define SF_CTRL_SF_IF_SR_INT_MSK        (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)
+#define SF_CTRL_SF_IF_SR_INT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS))
+#define SF_CTRL_SF_IF_SR_INT_EN         SF_CTRL_SF_IF_SR_INT_EN
+#define SF_CTRL_SF_IF_SR_INT_EN_POS     (17U)
+#define SF_CTRL_SF_IF_SR_INT_EN_LEN     (1U)
+#define SF_CTRL_SF_IF_SR_INT_EN_MSK     (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)
+#define SF_CTRL_SF_IF_SR_INT_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS))
+#define SF_CTRL_SF_IF_SR_INT_SET        SF_CTRL_SF_IF_SR_INT_SET
+#define SF_CTRL_SF_IF_SR_INT_SET_POS    (18U)
+#define SF_CTRL_SF_IF_SR_INT_SET_LEN    (1U)
+#define SF_CTRL_SF_IF_SR_INT_SET_MSK    (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)
+#define SF_CTRL_SF_IF_SR_INT_SET_UMSK   (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS))
+#define SF_CTRL_SF_IF_0_ACK_LAT         SF_CTRL_SF_IF_0_ACK_LAT
+#define SF_CTRL_SF_IF_0_ACK_LAT_POS     (20U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_LEN     (3U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS))
+#define SF_CTRL_SF_IF_REG_HOLD          SF_CTRL_SF_IF_REG_HOLD
+#define SF_CTRL_SF_IF_REG_HOLD_POS      (24U)
+#define SF_CTRL_SF_IF_REG_HOLD_LEN      (1U)
+#define SF_CTRL_SF_IF_REG_HOLD_MSK      (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)
+#define SF_CTRL_SF_IF_REG_HOLD_UMSK     (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS))
+#define SF_CTRL_SF_IF_REG_WP            SF_CTRL_SF_IF_REG_WP
+#define SF_CTRL_SF_IF_REG_WP_POS        (25U)
+#define SF_CTRL_SF_IF_REG_WP_LEN        (1U)
+#define SF_CTRL_SF_IF_REG_WP_MSK        (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)
+#define SF_CTRL_SF_IF_REG_WP_UMSK       (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS))
+#define SF_CTRL_SF_AHB2SIF_STOPPED      SF_CTRL_SF_AHB2SIF_STOPPED
+#define SF_CTRL_SF_AHB2SIF_STOPPED_POS  (26U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN  (1U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK  (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS))
+#define SF_CTRL_SF_AHB2SIF_STOP         SF_CTRL_SF_AHB2SIF_STOP
+#define SF_CTRL_SF_AHB2SIF_STOP_POS     (27U)
+#define SF_CTRL_SF_AHB2SIF_STOP_LEN     (1U)
+#define SF_CTRL_SF_AHB2SIF_STOP_MSK     (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)
+#define SF_CTRL_SF_AHB2SIF_STOP_UMSK    (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS))
+#define SF_CTRL_SF_IF_FN_SEL            SF_CTRL_SF_IF_FN_SEL
+#define SF_CTRL_SF_IF_FN_SEL_POS        (28U)
+#define SF_CTRL_SF_IF_FN_SEL_LEN        (1U)
+#define SF_CTRL_SF_IF_FN_SEL_MSK        (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)
+#define SF_CTRL_SF_IF_FN_SEL_UMSK       (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS))
+#define SF_CTRL_SF_IF_EN                SF_CTRL_SF_IF_EN
+#define SF_CTRL_SF_IF_EN_POS            (29U)
+#define SF_CTRL_SF_IF_EN_LEN            (1U)
+#define SF_CTRL_SF_IF_EN_MSK            (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)
+#define SF_CTRL_SF_IF_EN_UMSK           (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS))
+#define SF_CTRL_SF_AHB2SIF_EN           SF_CTRL_SF_AHB2SIF_EN
+#define SF_CTRL_SF_AHB2SIF_EN_POS       (30U)
+#define SF_CTRL_SF_AHB2SIF_EN_LEN       (1U)
+#define SF_CTRL_SF_AHB2SIF_EN_MSK       (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)
+#define SF_CTRL_SF_AHB2SIF_EN_UMSK      (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS))
+#define SF_CTRL_SF_AHB2SRAM_EN          SF_CTRL_SF_AHB2SRAM_EN
+#define SF_CTRL_SF_AHB2SRAM_EN_POS      (31U)
+#define SF_CTRL_SF_AHB2SRAM_EN_LEN      (1U)
+#define SF_CTRL_SF_AHB2SRAM_EN_MSK      (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)
+#define SF_CTRL_SF_AHB2SRAM_EN_UMSK     (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS))
+
+/* 0x8 : sf_if_sahb_0 */
+#define SF_CTRL_SF_IF_SAHB_0_OFFSET      (0x8)
+#define SF_CTRL_SF_IF_BUSY               SF_CTRL_SF_IF_BUSY
+#define SF_CTRL_SF_IF_BUSY_POS           (0U)
+#define SF_CTRL_SF_IF_BUSY_LEN           (1U)
+#define SF_CTRL_SF_IF_BUSY_MSK           (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)
+#define SF_CTRL_SF_IF_BUSY_UMSK          (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS))
+#define SF_CTRL_SF_IF_0_TRIG             SF_CTRL_SF_IF_0_TRIG
+#define SF_CTRL_SF_IF_0_TRIG_POS         (1U)
+#define SF_CTRL_SF_IF_0_TRIG_LEN         (1U)
+#define SF_CTRL_SF_IF_0_TRIG_MSK         (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)
+#define SF_CTRL_SF_IF_0_TRIG_UMSK        (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS))
+#define SF_CTRL_SF_IF_0_DAT_BYTE         SF_CTRL_SF_IF_0_DAT_BYTE
+#define SF_CTRL_SF_IF_0_DAT_BYTE_POS     (2U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN     (10U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DMY_BYTE         SF_CTRL_SF_IF_0_DMY_BYTE
+#define SF_CTRL_SF_IF_0_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_0_ADR_BYTE         SF_CTRL_SF_IF_0_ADR_BYTE
+#define SF_CTRL_SF_IF_0_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_0_CMD_BYTE         SF_CTRL_SF_IF_0_CMD_BYTE
+#define SF_CTRL_SF_IF_0_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DAT_RW           SF_CTRL_SF_IF_0_DAT_RW
+#define SF_CTRL_SF_IF_0_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_0_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)
+#define SF_CTRL_SF_IF_0_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS))
+#define SF_CTRL_SF_IF_0_DAT_EN           SF_CTRL_SF_IF_0_DAT_EN
+#define SF_CTRL_SF_IF_0_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_0_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)
+#define SF_CTRL_SF_IF_0_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS))
+#define SF_CTRL_SF_IF_0_DMY_EN           SF_CTRL_SF_IF_0_DMY_EN
+#define SF_CTRL_SF_IF_0_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_0_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)
+#define SF_CTRL_SF_IF_0_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS))
+#define SF_CTRL_SF_IF_0_ADR_EN           SF_CTRL_SF_IF_0_ADR_EN
+#define SF_CTRL_SF_IF_0_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_0_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)
+#define SF_CTRL_SF_IF_0_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS))
+#define SF_CTRL_SF_IF_0_CMD_EN           SF_CTRL_SF_IF_0_CMD_EN
+#define SF_CTRL_SF_IF_0_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_0_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)
+#define SF_CTRL_SF_IF_0_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS))
+#define SF_CTRL_SF_IF_0_SPI_MODE         SF_CTRL_SF_IF_0_SPI_MODE
+#define SF_CTRL_SF_IF_0_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN      SF_CTRL_SF_IF_0_QPI_MODE_EN
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS))
+
+/* 0xC : sf_if_sahb_1 */
+#define SF_CTRL_SF_IF_SAHB_1_OFFSET    (0xC)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0      SF_CTRL_SF_IF_0_CMD_BUF_0
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS))
+
+/* 0x10 : sf_if_sahb_2 */
+#define SF_CTRL_SF_IF_SAHB_2_OFFSET    (0x10)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1      SF_CTRL_SF_IF_0_CMD_BUF_1
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS))
+
+/* 0x14 : sf_if_iahb_0 */
+#define SF_CTRL_SF_IF_IAHB_0_OFFSET      (0x14)
+#define SF_CTRL_SF_IF_1_DMY_BYTE         SF_CTRL_SF_IF_1_DMY_BYTE
+#define SF_CTRL_SF_IF_1_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_1_ADR_BYTE         SF_CTRL_SF_IF_1_ADR_BYTE
+#define SF_CTRL_SF_IF_1_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_1_CMD_BYTE         SF_CTRL_SF_IF_1_CMD_BYTE
+#define SF_CTRL_SF_IF_1_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_1_DAT_RW           SF_CTRL_SF_IF_1_DAT_RW
+#define SF_CTRL_SF_IF_1_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_1_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)
+#define SF_CTRL_SF_IF_1_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS))
+#define SF_CTRL_SF_IF_1_DAT_EN           SF_CTRL_SF_IF_1_DAT_EN
+#define SF_CTRL_SF_IF_1_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_1_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)
+#define SF_CTRL_SF_IF_1_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS))
+#define SF_CTRL_SF_IF_1_DMY_EN           SF_CTRL_SF_IF_1_DMY_EN
+#define SF_CTRL_SF_IF_1_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_1_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)
+#define SF_CTRL_SF_IF_1_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS))
+#define SF_CTRL_SF_IF_1_ADR_EN           SF_CTRL_SF_IF_1_ADR_EN
+#define SF_CTRL_SF_IF_1_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_1_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)
+#define SF_CTRL_SF_IF_1_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS))
+#define SF_CTRL_SF_IF_1_CMD_EN           SF_CTRL_SF_IF_1_CMD_EN
+#define SF_CTRL_SF_IF_1_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_1_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)
+#define SF_CTRL_SF_IF_1_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS))
+#define SF_CTRL_SF_IF_1_SPI_MODE         SF_CTRL_SF_IF_1_SPI_MODE
+#define SF_CTRL_SF_IF_1_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN      SF_CTRL_SF_IF_1_QPI_MODE_EN
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS))
+
+/* 0x18 : sf_if_iahb_1 */
+#define SF_CTRL_SF_IF_IAHB_1_OFFSET    (0x18)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0      SF_CTRL_SF_IF_1_CMD_BUF_0
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS))
+
+/* 0x1C : sf_if_iahb_2 */
+#define SF_CTRL_SF_IF_IAHB_2_OFFSET    (0x1C)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1      SF_CTRL_SF_IF_1_CMD_BUF_1
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS))
+
+/* 0x20 : sf_if_status_0 */
+#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)
+#define SF_CTRL_SF_IF_STATUS_0        SF_CTRL_SF_IF_STATUS_0
+#define SF_CTRL_SF_IF_STATUS_0_POS    (0U)
+#define SF_CTRL_SF_IF_STATUS_0_LEN    (32U)
+#define SF_CTRL_SF_IF_STATUS_0_MSK    (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)
+#define SF_CTRL_SF_IF_STATUS_0_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS))
+
+/* 0x24 : sf_if_status_1 */
+#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)
+#define SF_CTRL_SF_IF_STATUS_1        SF_CTRL_SF_IF_STATUS_1
+#define SF_CTRL_SF_IF_STATUS_1_POS    (0U)
+#define SF_CTRL_SF_IF_STATUS_1_LEN    (32U)
+#define SF_CTRL_SF_IF_STATUS_1_MSK    (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)
+#define SF_CTRL_SF_IF_STATUS_1_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS))
+
+/* 0x28 : sf_aes */
+#define SF_CTRL_SF_AES_OFFSET         (0x28)
+#define SF_CTRL_SF_AES_EN             SF_CTRL_SF_AES_EN
+#define SF_CTRL_SF_AES_EN_POS         (0U)
+#define SF_CTRL_SF_AES_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_EN_MSK         (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)
+#define SF_CTRL_SF_AES_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS))
+#define SF_CTRL_SF_AES_MODE           SF_CTRL_SF_AES_MODE
+#define SF_CTRL_SF_AES_MODE_POS       (1U)
+#define SF_CTRL_SF_AES_MODE_LEN       (2U)
+#define SF_CTRL_SF_AES_MODE_MSK       (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)
+#define SF_CTRL_SF_AES_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS))
+#define SF_CTRL_SF_AES_PREF_TRIG      SF_CTRL_SF_AES_PREF_TRIG
+#define SF_CTRL_SF_AES_PREF_TRIG_POS  (3U)
+#define SF_CTRL_SF_AES_PREF_TRIG_LEN  (1U)
+#define SF_CTRL_SF_AES_PREF_TRIG_MSK  (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)
+#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS))
+#define SF_CTRL_SF_AES_PREF_BUSY      SF_CTRL_SF_AES_PREF_BUSY
+#define SF_CTRL_SF_AES_PREF_BUSY_POS  (4U)
+#define SF_CTRL_SF_AES_PREF_BUSY_LEN  (1U)
+#define SF_CTRL_SF_AES_PREF_BUSY_MSK  (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)
+#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS))
+#define SF_CTRL_SF_AES_STATUS         SF_CTRL_SF_AES_STATUS
+#define SF_CTRL_SF_AES_STATUS_POS     (5U)
+#define SF_CTRL_SF_AES_STATUS_LEN     (27U)
+#define SF_CTRL_SF_AES_STATUS_MSK     (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)
+#define SF_CTRL_SF_AES_STATUS_UMSK    (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS))
+
+/* 0x2C : sf_ahb2sif_status */
+#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)
+#define SF_CTRL_SF_AHB2SIF_STATUS        SF_CTRL_SF_AHB2SIF_STATUS
+#define SF_CTRL_SF_AHB2SIF_STATUS_POS    (0U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_LEN    (32U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_MSK    (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)
+#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK   (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS))
+
+/* 0x30 : sf_if_io_dly_0 */
+#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET   (0x30)
+#define SF_CTRL_SF_CS_DLY_SEL           SF_CTRL_SF_CS_DLY_SEL
+#define SF_CTRL_SF_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)
+#define SF_CTRL_SF_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL      SF_CTRL_SF_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_OE_DLY_SEL       SF_CTRL_SF_DQS_OE_DLY_SEL
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DI_DLY_SEL       SF_CTRL_SF_DQS_DI_DLY_SEL
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DO_DLY_SEL       SF_CTRL_SF_DQS_DO_DLY_SEL
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS))
+
+/* 0x34 : sf_if_io_dly_1 */
+#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET   (0x34)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL      SF_CTRL_SF_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL      SF_CTRL_SF_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL      SF_CTRL_SF_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS))
+
+/* 0x38 : sf_if_io_dly_2 */
+#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET   (0x38)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL      SF_CTRL_SF_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL      SF_CTRL_SF_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL      SF_CTRL_SF_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS))
+
+/* 0x3C : sf_if_io_dly_3 */
+#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET   (0x3C)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL      SF_CTRL_SF_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL      SF_CTRL_SF_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL      SF_CTRL_SF_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS))
+
+/* 0x40 : sf_if_io_dly_4 */
+#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET   (0x40)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL      SF_CTRL_SF_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL      SF_CTRL_SF_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL      SF_CTRL_SF_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS))
+
+/* 0x44 : sf_reserved */
+#define SF_CTRL_SF_RESERVED_OFFSET (0x44)
+#define SF_CTRL_SF_RESERVED        SF_CTRL_SF_RESERVED
+#define SF_CTRL_SF_RESERVED_POS    (0U)
+#define SF_CTRL_SF_RESERVED_LEN    (32U)
+#define SF_CTRL_SF_RESERVED_MSK    (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)
+#define SF_CTRL_SF_RESERVED_UMSK   (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS))
+
+/* 0x48 : sf2_if_io_dly_0 */
+#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET   (0x48)
+#define SF_CTRL_SF2_CS_DLY_SEL           SF_CTRL_SF2_CS_DLY_SEL
+#define SF_CTRL_SF2_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF2_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF2_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)
+#define SF_CTRL_SF2_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS))
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL      SF_CTRL_SF2_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL       SF_CTRL_SF2_DQS_OE_DLY_SEL
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL       SF_CTRL_SF2_DQS_DI_DLY_SEL
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL       SF_CTRL_SF2_DQS_DO_DLY_SEL
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS))
+
+/* 0x4C : sf2_if_io_dly_1 */
+#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET   (0x4C)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL      SF_CTRL_SF2_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL      SF_CTRL_SF2_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL      SF_CTRL_SF2_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS))
+
+/* 0x50 : sf2_if_io_dly_2 */
+#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET   (0x50)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL      SF_CTRL_SF2_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL      SF_CTRL_SF2_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL      SF_CTRL_SF2_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS))
+
+/* 0x54 : sf2_if_io_dly_3 */
+#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET   (0x54)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL      SF_CTRL_SF2_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL      SF_CTRL_SF2_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL      SF_CTRL_SF2_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS))
+
+/* 0x58 : sf2_if_io_dly_4 */
+#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET   (0x58)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL      SF_CTRL_SF2_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL      SF_CTRL_SF2_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL      SF_CTRL_SF2_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS))
+
+/* 0x5C : sf3_if_io_dly_0 */
+#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET   (0x5C)
+#define SF_CTRL_SF3_CS_DLY_SEL           SF_CTRL_SF3_CS_DLY_SEL
+#define SF_CTRL_SF3_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF3_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF3_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)
+#define SF_CTRL_SF3_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS))
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL      SF_CTRL_SF3_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL       SF_CTRL_SF3_DQS_OE_DLY_SEL
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL       SF_CTRL_SF3_DQS_DI_DLY_SEL
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL       SF_CTRL_SF3_DQS_DO_DLY_SEL
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS))
+
+/* 0x60 : sf3_if_io_dly_1 */
+#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET   (0x60)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL      SF_CTRL_SF3_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL      SF_CTRL_SF3_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL      SF_CTRL_SF3_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS))
+
+/* 0x64 : sf3_if_io_dly_2 */
+#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET   (0x64)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL      SF_CTRL_SF3_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL      SF_CTRL_SF3_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL      SF_CTRL_SF3_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS))
+
+/* 0x68 : sf3_if_io_dly_3 */
+#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET   (0x68)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL      SF_CTRL_SF3_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL      SF_CTRL_SF3_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL      SF_CTRL_SF3_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS))
+
+/* 0x6C : sf3_if_io_dly_4 */
+#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET   (0x6C)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL      SF_CTRL_SF3_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL      SF_CTRL_SF3_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL      SF_CTRL_SF3_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS))
+
+/* 0x70 : sf_ctrl_2 */
+#define SF_CTRL_2_OFFSET                (0x70)
+#define SF_CTRL_SF_IF_PAD_SEL           SF_CTRL_SF_IF_PAD_SEL
+#define SF_CTRL_SF_IF_PAD_SEL_POS       (0U)
+#define SF_CTRL_SF_IF_PAD_SEL_LEN       (2U)
+#define SF_CTRL_SF_IF_PAD_SEL_MSK       (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_UMSK      (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS))
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK      SF_CTRL_SF_IF_PAD_SEL_LOCK
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS  (3U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN  (1U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK  (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS))
+#define SF_CTRL_SF_IF_DTR_EN            SF_CTRL_SF_IF_DTR_EN
+#define SF_CTRL_SF_IF_DTR_EN_POS        (4U)
+#define SF_CTRL_SF_IF_DTR_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_DTR_EN_MSK        (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)
+#define SF_CTRL_SF_IF_DTR_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS))
+#define SF_CTRL_SF_IF_DQS_EN            SF_CTRL_SF_IF_DQS_EN
+#define SF_CTRL_SF_IF_DQS_EN_POS        (5U)
+#define SF_CTRL_SF_IF_DQS_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_DQS_EN_MSK        (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)
+#define SF_CTRL_SF_IF_DQS_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS))
+
+/* 0x74 : sf_ctrl_3 */
+#define SF_CTRL_3_OFFSET                (0x74)
+#define SF_CTRL_SF_CMDS_WRAP_LEN        SF_CTRL_SF_CMDS_WRAP_LEN
+#define SF_CTRL_SF_CMDS_WRAP_LEN_POS    (0U)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN    (4U)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK    (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK   (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS))
+#define SF_CTRL_SF_CMDS_EN              SF_CTRL_SF_CMDS_EN
+#define SF_CTRL_SF_CMDS_EN_POS          (4U)
+#define SF_CTRL_SF_CMDS_EN_LEN          (1U)
+#define SF_CTRL_SF_CMDS_EN_MSK          (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)
+#define SF_CTRL_SF_CMDS_EN_UMSK         (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS))
+#define SF_CTRL_SF_CMDS_BT_DLY          SF_CTRL_SF_CMDS_BT_DLY
+#define SF_CTRL_SF_CMDS_BT_DLY_POS      (5U)
+#define SF_CTRL_SF_CMDS_BT_DLY_LEN      (3U)
+#define SF_CTRL_SF_CMDS_BT_DLY_MSK      (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)
+#define SF_CTRL_SF_CMDS_BT_DLY_UMSK     (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS))
+#define SF_CTRL_SF_CMDS_BT_EN           SF_CTRL_SF_CMDS_BT_EN
+#define SF_CTRL_SF_CMDS_BT_EN_POS       (8U)
+#define SF_CTRL_SF_CMDS_BT_EN_LEN       (1U)
+#define SF_CTRL_SF_CMDS_BT_EN_MSK       (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)
+#define SF_CTRL_SF_CMDS_BT_EN_UMSK      (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS))
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI      SF_CTRL_SF_CMDS_WRAP_Q_INI
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS  (9U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN  (1U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK  (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS))
+#define SF_CTRL_SF_CMDS_WRAP_MODE       SF_CTRL_SF_CMDS_WRAP_MODE
+#define SF_CTRL_SF_CMDS_WRAP_MODE_POS   (10U)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN   (1U)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK   (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK  (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS))
+#define SF_CTRL_SF_IF_1_ACK_LAT         SF_CTRL_SF_IF_1_ACK_LAT
+#define SF_CTRL_SF_IF_1_ACK_LAT_POS     (29U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_LEN     (3U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS))
+
+/* 0x78 : sf_if_iahb_3 */
+#define SF_CTRL_SF_IF_IAHB_3_OFFSET      (0x78)
+#define SF_CTRL_SF_IF_2_DMY_BYTE         SF_CTRL_SF_IF_2_DMY_BYTE
+#define SF_CTRL_SF_IF_2_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_2_ADR_BYTE         SF_CTRL_SF_IF_2_ADR_BYTE
+#define SF_CTRL_SF_IF_2_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_2_CMD_BYTE         SF_CTRL_SF_IF_2_CMD_BYTE
+#define SF_CTRL_SF_IF_2_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_2_DAT_RW           SF_CTRL_SF_IF_2_DAT_RW
+#define SF_CTRL_SF_IF_2_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_2_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)
+#define SF_CTRL_SF_IF_2_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS))
+#define SF_CTRL_SF_IF_2_DAT_EN           SF_CTRL_SF_IF_2_DAT_EN
+#define SF_CTRL_SF_IF_2_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_2_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)
+#define SF_CTRL_SF_IF_2_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS))
+#define SF_CTRL_SF_IF_2_DMY_EN           SF_CTRL_SF_IF_2_DMY_EN
+#define SF_CTRL_SF_IF_2_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_2_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)
+#define SF_CTRL_SF_IF_2_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS))
+#define SF_CTRL_SF_IF_2_ADR_EN           SF_CTRL_SF_IF_2_ADR_EN
+#define SF_CTRL_SF_IF_2_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_2_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)
+#define SF_CTRL_SF_IF_2_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS))
+#define SF_CTRL_SF_IF_2_CMD_EN           SF_CTRL_SF_IF_2_CMD_EN
+#define SF_CTRL_SF_IF_2_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_2_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)
+#define SF_CTRL_SF_IF_2_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS))
+#define SF_CTRL_SF_IF_2_SPI_MODE         SF_CTRL_SF_IF_2_SPI_MODE
+#define SF_CTRL_SF_IF_2_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN      SF_CTRL_SF_IF_2_QPI_MODE_EN
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS))
+
+/* 0x7C : sf_if_iahb_4 */
+#define SF_CTRL_SF_IF_IAHB_4_OFFSET    (0x7C)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0      SF_CTRL_SF_IF_2_CMD_BUF_0
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS))
+
+/* 0x80 : sf_if_iahb_5 */
+#define SF_CTRL_SF_IF_IAHB_5_OFFSET    (0x80)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1      SF_CTRL_SF_IF_2_CMD_BUF_1
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS))
+
+/* 0x84 : sf_if_iahb_6 */
+#define SF_CTRL_SF_IF_IAHB_6_OFFSET      (0x84)
+#define SF_CTRL_SF_IF_3_CMD_BYTE         SF_CTRL_SF_IF_3_CMD_BYTE
+#define SF_CTRL_SF_IF_3_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_3_SPI_MODE         SF_CTRL_SF_IF_3_SPI_MODE
+#define SF_CTRL_SF_IF_3_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN      SF_CTRL_SF_IF_3_QPI_MODE_EN
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS))
+
+/* 0x88 : sf_if_iahb_7 */
+#define SF_CTRL_SF_IF_IAHB_7_OFFSET    (0x88)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0      SF_CTRL_SF_IF_3_CMD_BUF_0
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS))
+
+/* 0x100 : sf_ctrl_prot_en_rd */
+#define SF_CTRL_PROT_EN_RD_OFFSET         (0x100)
+#define SF_CTRL_PROT_EN_RD                SF_CTRL_PROT_EN_RD
+#define SF_CTRL_PROT_EN_RD_POS            (0U)
+#define SF_CTRL_PROT_EN_RD_LEN            (1U)
+#define SF_CTRL_PROT_EN_RD_MSK            (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)
+#define SF_CTRL_PROT_EN_RD_UMSK           (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS))
+#define SF_CTRL_ID0_EN_RD                 SF_CTRL_ID0_EN_RD
+#define SF_CTRL_ID0_EN_RD_POS             (1U)
+#define SF_CTRL_ID0_EN_RD_LEN             (1U)
+#define SF_CTRL_ID0_EN_RD_MSK             (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)
+#define SF_CTRL_ID0_EN_RD_UMSK            (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS))
+#define SF_CTRL_ID1_EN_RD                 SF_CTRL_ID1_EN_RD
+#define SF_CTRL_ID1_EN_RD_POS             (2U)
+#define SF_CTRL_ID1_EN_RD_LEN             (1U)
+#define SF_CTRL_ID1_EN_RD_MSK             (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)
+#define SF_CTRL_ID1_EN_RD_UMSK            (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS))
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK      SF_CTRL_SF_IF_0_TRIG_WR_LOCK
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS  (30U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN  (1U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK  (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS))
+#define SF_CTRL_SF_DBG_DIS                SF_CTRL_SF_DBG_DIS
+#define SF_CTRL_SF_DBG_DIS_POS            (31U)
+#define SF_CTRL_SF_DBG_DIS_LEN            (1U)
+#define SF_CTRL_SF_DBG_DIS_MSK            (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)
+#define SF_CTRL_SF_DBG_DIS_UMSK           (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS))
+
+/* 0x104 : sf_ctrl_prot_en */
+#define SF_CTRL_PROT_EN_OFFSET (0x104)
+#define SF_CTRL_PROT_EN        SF_CTRL_PROT_EN
+#define SF_CTRL_PROT_EN_POS    (0U)
+#define SF_CTRL_PROT_EN_LEN    (1U)
+#define SF_CTRL_PROT_EN_MSK    (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)
+#define SF_CTRL_PROT_EN_UMSK   (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS))
+#define SF_CTRL_ID0_EN         SF_CTRL_ID0_EN
+#define SF_CTRL_ID0_EN_POS     (1U)
+#define SF_CTRL_ID0_EN_LEN     (1U)
+#define SF_CTRL_ID0_EN_MSK     (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)
+#define SF_CTRL_ID0_EN_UMSK    (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS))
+#define SF_CTRL_ID1_EN         SF_CTRL_ID1_EN
+#define SF_CTRL_ID1_EN_POS     (2U)
+#define SF_CTRL_ID1_EN_LEN     (1U)
+#define SF_CTRL_ID1_EN_MSK     (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)
+#define SF_CTRL_ID1_EN_UMSK    (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS))
+
+/* 0x200 : sf_aes_key_r0_0 */
+#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)
+#define SF_CTRL_SF_AES_KEY_R0_0        SF_CTRL_SF_AES_KEY_R0_0
+#define SF_CTRL_SF_AES_KEY_R0_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)
+#define SF_CTRL_SF_AES_KEY_R0_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS))
+
+/* 0x204 : sf_aes_key_r0_1 */
+#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)
+#define SF_CTRL_SF_AES_KEY_R0_1        SF_CTRL_SF_AES_KEY_R0_1
+#define SF_CTRL_SF_AES_KEY_R0_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)
+#define SF_CTRL_SF_AES_KEY_R0_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS))
+
+/* 0x208 : sf_aes_key_r0_2 */
+#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)
+#define SF_CTRL_SF_AES_KEY_R0_2        SF_CTRL_SF_AES_KEY_R0_2
+#define SF_CTRL_SF_AES_KEY_R0_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)
+#define SF_CTRL_SF_AES_KEY_R0_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS))
+
+/* 0x20C : sf_aes_key_r0_3 */
+#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)
+#define SF_CTRL_SF_AES_KEY_R0_3        SF_CTRL_SF_AES_KEY_R0_3
+#define SF_CTRL_SF_AES_KEY_R0_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)
+#define SF_CTRL_SF_AES_KEY_R0_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS))
+
+/* 0x210 : sf_aes_key_r0_4 */
+#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)
+#define SF_CTRL_SF_AES_KEY_R0_4        SF_CTRL_SF_AES_KEY_R0_4
+#define SF_CTRL_SF_AES_KEY_R0_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)
+#define SF_CTRL_SF_AES_KEY_R0_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS))
+
+/* 0x214 : sf_aes_key_r0_5 */
+#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)
+#define SF_CTRL_SF_AES_KEY_R0_5        SF_CTRL_SF_AES_KEY_R0_5
+#define SF_CTRL_SF_AES_KEY_R0_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)
+#define SF_CTRL_SF_AES_KEY_R0_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS))
+
+/* 0x218 : sf_aes_key_r0_6 */
+#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)
+#define SF_CTRL_SF_AES_KEY_R0_6        SF_CTRL_SF_AES_KEY_R0_6
+#define SF_CTRL_SF_AES_KEY_R0_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)
+#define SF_CTRL_SF_AES_KEY_R0_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS))
+
+/* 0x21C : sf_aes_key_r0_7 */
+#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)
+#define SF_CTRL_SF_AES_KEY_R0_7        SF_CTRL_SF_AES_KEY_R0_7
+#define SF_CTRL_SF_AES_KEY_R0_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)
+#define SF_CTRL_SF_AES_KEY_R0_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS))
+
+/* 0x220 : sf_aes_iv_r0_w0 */
+#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)
+#define SF_CTRL_SF_AES_IV_R0_W0        SF_CTRL_SF_AES_IV_R0_W0
+#define SF_CTRL_SF_AES_IV_R0_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)
+#define SF_CTRL_SF_AES_IV_R0_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS))
+
+/* 0x224 : sf_aes_iv_r0_w1 */
+#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)
+#define SF_CTRL_SF_AES_IV_R0_W1        SF_CTRL_SF_AES_IV_R0_W1
+#define SF_CTRL_SF_AES_IV_R0_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)
+#define SF_CTRL_SF_AES_IV_R0_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS))
+
+/* 0x228 : sf_aes_iv_r0_w2 */
+#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)
+#define SF_CTRL_SF_AES_IV_R0_W2        SF_CTRL_SF_AES_IV_R0_W2
+#define SF_CTRL_SF_AES_IV_R0_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)
+#define SF_CTRL_SF_AES_IV_R0_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS))
+
+/* 0x22C : sf_aes_iv_r0_w3 */
+#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)
+#define SF_CTRL_SF_AES_IV_R0_W3        SF_CTRL_SF_AES_IV_R0_W3
+#define SF_CTRL_SF_AES_IV_R0_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)
+#define SF_CTRL_SF_AES_IV_R0_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS))
+
+/* 0x230 : sf_aes_cfg_r0 */
+#define SF_CTRL_SF_AES_CFG_R0_OFFSET            (0x230)
+#define SF_CTRL_SF_AES_REGION_R0_END            SF_CTRL_SF_AES_REGION_R0_END
+#define SF_CTRL_SF_AES_REGION_R0_END_POS        (0U)
+#define SF_CTRL_SF_AES_REGION_R0_END_LEN        (14U)
+#define SF_CTRL_SF_AES_REGION_R0_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)
+#define SF_CTRL_SF_AES_REGION_R0_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS))
+#define SF_CTRL_SF_AES_REGION_R0_START          SF_CTRL_SF_AES_REGION_R0_START
+#define SF_CTRL_SF_AES_REGION_R0_START_POS      (14U)
+#define SF_CTRL_SF_AES_REGION_R0_START_LEN      (14U)
+#define SF_CTRL_SF_AES_REGION_R0_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)
+#define SF_CTRL_SF_AES_REGION_R0_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS))
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN      SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_EN             SF_CTRL_SF_AES_REGION_R0_EN
+#define SF_CTRL_SF_AES_REGION_R0_EN_POS         (30U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_LOCK           SF_CTRL_SF_AES_REGION_R0_LOCK
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS))
+
+/* 0x300 : sf_aes_key_r1_0 */
+#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300)
+#define SF_CTRL_SF_AES_KEY_R1_0        SF_CTRL_SF_AES_KEY_R1_0
+#define SF_CTRL_SF_AES_KEY_R1_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)
+#define SF_CTRL_SF_AES_KEY_R1_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS))
+
+/* 0x304 : sf_aes_key_r1_1 */
+#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304)
+#define SF_CTRL_SF_AES_KEY_R1_1        SF_CTRL_SF_AES_KEY_R1_1
+#define SF_CTRL_SF_AES_KEY_R1_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)
+#define SF_CTRL_SF_AES_KEY_R1_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS))
+
+/* 0x308 : sf_aes_key_r1_2 */
+#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308)
+#define SF_CTRL_SF_AES_KEY_R1_2        SF_CTRL_SF_AES_KEY_R1_2
+#define SF_CTRL_SF_AES_KEY_R1_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)
+#define SF_CTRL_SF_AES_KEY_R1_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS))
+
+/* 0x30C : sf_aes_key_r1_3 */
+#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C)
+#define SF_CTRL_SF_AES_KEY_R1_3        SF_CTRL_SF_AES_KEY_R1_3
+#define SF_CTRL_SF_AES_KEY_R1_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)
+#define SF_CTRL_SF_AES_KEY_R1_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS))
+
+/* 0x310 : sf_aes_key_r1_4 */
+#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310)
+#define SF_CTRL_SF_AES_KEY_R1_4        SF_CTRL_SF_AES_KEY_R1_4
+#define SF_CTRL_SF_AES_KEY_R1_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)
+#define SF_CTRL_SF_AES_KEY_R1_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS))
+
+/* 0x314 : sf_aes_key_r1_5 */
+#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314)
+#define SF_CTRL_SF_AES_KEY_R1_5        SF_CTRL_SF_AES_KEY_R1_5
+#define SF_CTRL_SF_AES_KEY_R1_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)
+#define SF_CTRL_SF_AES_KEY_R1_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS))
+
+/* 0x318 : sf_aes_key_r1_6 */
+#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318)
+#define SF_CTRL_SF_AES_KEY_R1_6        SF_CTRL_SF_AES_KEY_R1_6
+#define SF_CTRL_SF_AES_KEY_R1_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)
+#define SF_CTRL_SF_AES_KEY_R1_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS))
+
+/* 0x31C : sf_aes_key_r1_7 */
+#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C)
+#define SF_CTRL_SF_AES_KEY_R1_7        SF_CTRL_SF_AES_KEY_R1_7
+#define SF_CTRL_SF_AES_KEY_R1_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)
+#define SF_CTRL_SF_AES_KEY_R1_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS))
+
+/* 0x320 : sf_aes_iv_r1_w0 */
+#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320)
+#define SF_CTRL_SF_AES_IV_R1_W0        SF_CTRL_SF_AES_IV_R1_W0
+#define SF_CTRL_SF_AES_IV_R1_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)
+#define SF_CTRL_SF_AES_IV_R1_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS))
+
+/* 0x324 : sf_aes_iv_r1_w1 */
+#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324)
+#define SF_CTRL_SF_AES_IV_R1_W1        SF_CTRL_SF_AES_IV_R1_W1
+#define SF_CTRL_SF_AES_IV_R1_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)
+#define SF_CTRL_SF_AES_IV_R1_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS))
+
+/* 0x328 : sf_aes_iv_r1_w2 */
+#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328)
+#define SF_CTRL_SF_AES_IV_R1_W2        SF_CTRL_SF_AES_IV_R1_W2
+#define SF_CTRL_SF_AES_IV_R1_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)
+#define SF_CTRL_SF_AES_IV_R1_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS))
+
+/* 0x32C : sf_aes_iv_r1_w3 */
+#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C)
+#define SF_CTRL_SF_AES_IV_R1_W3        SF_CTRL_SF_AES_IV_R1_W3
+#define SF_CTRL_SF_AES_IV_R1_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)
+#define SF_CTRL_SF_AES_IV_R1_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS))
+
+/* 0x330 : sf_aes_r1 */
+#define SF_CTRL_SF_AES_R1_OFFSET         (0x330)
+#define SF_CTRL_SF_AES_R1_END            SF_CTRL_SF_AES_R1_END
+#define SF_CTRL_SF_AES_R1_END_POS        (0U)
+#define SF_CTRL_SF_AES_R1_END_LEN        (14U)
+#define SF_CTRL_SF_AES_R1_END_MSK        (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)
+#define SF_CTRL_SF_AES_R1_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS))
+#define SF_CTRL_SF_AES_R1_START          SF_CTRL_SF_AES_R1_START
+#define SF_CTRL_SF_AES_R1_START_POS      (14U)
+#define SF_CTRL_SF_AES_R1_START_LEN      (14U)
+#define SF_CTRL_SF_AES_R1_START_MSK      (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)
+#define SF_CTRL_SF_AES_R1_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS))
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN      SF_CTRL_SF_AES_R1_HW_KEY_EN
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R1_EN             SF_CTRL_SF_AES_R1_EN
+#define SF_CTRL_SF_AES_R1_EN_POS         (30U)
+#define SF_CTRL_SF_AES_R1_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_R1_EN_MSK         (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)
+#define SF_CTRL_SF_AES_R1_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS))
+#define SF_CTRL_SF_AES_R1_LOCK           SF_CTRL_SF_AES_R1_LOCK
+#define SF_CTRL_SF_AES_R1_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_R1_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_R1_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)
+#define SF_CTRL_SF_AES_R1_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS))
+
+/* 0x400 : sf_aes_key_r2_0 */
+#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400)
+#define SF_CTRL_SF_AES_KEY_R2_0        SF_CTRL_SF_AES_KEY_R2_0
+#define SF_CTRL_SF_AES_KEY_R2_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)
+#define SF_CTRL_SF_AES_KEY_R2_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS))
+
+/* 0x404 : sf_aes_key_r2_1 */
+#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404)
+#define SF_CTRL_SF_AES_KEY_R2_1        SF_CTRL_SF_AES_KEY_R2_1
+#define SF_CTRL_SF_AES_KEY_R2_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)
+#define SF_CTRL_SF_AES_KEY_R2_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS))
+
+/* 0x408 : sf_aes_key_r2_2 */
+#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408)
+#define SF_CTRL_SF_AES_KEY_R2_2        SF_CTRL_SF_AES_KEY_R2_2
+#define SF_CTRL_SF_AES_KEY_R2_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)
+#define SF_CTRL_SF_AES_KEY_R2_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS))
+
+/* 0x40C : sf_aes_key_r2_3 */
+#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C)
+#define SF_CTRL_SF_AES_KEY_R2_3        SF_CTRL_SF_AES_KEY_R2_3
+#define SF_CTRL_SF_AES_KEY_R2_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)
+#define SF_CTRL_SF_AES_KEY_R2_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS))
+
+/* 0x410 : sf_aes_key_r2_4 */
+#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410)
+#define SF_CTRL_SF_AES_KEY_R2_4        SF_CTRL_SF_AES_KEY_R2_4
+#define SF_CTRL_SF_AES_KEY_R2_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)
+#define SF_CTRL_SF_AES_KEY_R2_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS))
+
+/* 0x414 : sf_aes_key_r2_5 */
+#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414)
+#define SF_CTRL_SF_AES_KEY_R2_5        SF_CTRL_SF_AES_KEY_R2_5
+#define SF_CTRL_SF_AES_KEY_R2_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)
+#define SF_CTRL_SF_AES_KEY_R2_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS))
+
+/* 0x418 : sf_aes_key_r2_6 */
+#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418)
+#define SF_CTRL_SF_AES_KEY_R2_6        SF_CTRL_SF_AES_KEY_R2_6
+#define SF_CTRL_SF_AES_KEY_R2_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)
+#define SF_CTRL_SF_AES_KEY_R2_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS))
+
+/* 0x41C : sf_aes_key_r2_7 */
+#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C)
+#define SF_CTRL_SF_AES_KEY_R2_7        SF_CTRL_SF_AES_KEY_R2_7
+#define SF_CTRL_SF_AES_KEY_R2_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)
+#define SF_CTRL_SF_AES_KEY_R2_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS))
+
+/* 0x420 : sf_aes_iv_r2_w0 */
+#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420)
+#define SF_CTRL_SF_AES_IV_R2_W0        SF_CTRL_SF_AES_IV_R2_W0
+#define SF_CTRL_SF_AES_IV_R2_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)
+#define SF_CTRL_SF_AES_IV_R2_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS))
+
+/* 0x424 : sf_aes_iv_r2_w1 */
+#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424)
+#define SF_CTRL_SF_AES_IV_R2_W1        SF_CTRL_SF_AES_IV_R2_W1
+#define SF_CTRL_SF_AES_IV_R2_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)
+#define SF_CTRL_SF_AES_IV_R2_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS))
+
+/* 0x428 : sf_aes_iv_r2_w2 */
+#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428)
+#define SF_CTRL_SF_AES_IV_R2_W2        SF_CTRL_SF_AES_IV_R2_W2
+#define SF_CTRL_SF_AES_IV_R2_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)
+#define SF_CTRL_SF_AES_IV_R2_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS))
+
+/* 0x42C : sf_aes_iv_r2_w3 */
+#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C)
+#define SF_CTRL_SF_AES_IV_R2_W3        SF_CTRL_SF_AES_IV_R2_W3
+#define SF_CTRL_SF_AES_IV_R2_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)
+#define SF_CTRL_SF_AES_IV_R2_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS))
+
+/* 0x430 : sf_aes_r2 */
+#define SF_CTRL_SF_AES_R2_OFFSET         (0x430)
+#define SF_CTRL_SF_AES_R2_END            SF_CTRL_SF_AES_R2_END
+#define SF_CTRL_SF_AES_R2_END_POS        (0U)
+#define SF_CTRL_SF_AES_R2_END_LEN        (14U)
+#define SF_CTRL_SF_AES_R2_END_MSK        (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)
+#define SF_CTRL_SF_AES_R2_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS))
+#define SF_CTRL_SF_AES_R2_START          SF_CTRL_SF_AES_R2_START
+#define SF_CTRL_SF_AES_R2_START_POS      (14U)
+#define SF_CTRL_SF_AES_R2_START_LEN      (14U)
+#define SF_CTRL_SF_AES_R2_START_MSK      (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)
+#define SF_CTRL_SF_AES_R2_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS))
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN      SF_CTRL_SF_AES_R2_HW_KEY_EN
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R2_EN             SF_CTRL_SF_AES_R2_EN
+#define SF_CTRL_SF_AES_R2_EN_POS         (30U)
+#define SF_CTRL_SF_AES_R2_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_R2_EN_MSK         (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)
+#define SF_CTRL_SF_AES_R2_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS))
+#define SF_CTRL_SF_AES_R2_LOCK           SF_CTRL_SF_AES_R2_LOCK
+#define SF_CTRL_SF_AES_R2_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_R2_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_R2_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)
+#define SF_CTRL_SF_AES_R2_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS))
+
+/* 0x434 : sf_id0_offset */
+#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434)
+#define SF_CTRL_SF_ID0_OFFSET        SF_CTRL_SF_ID0_OFFSET
+#define SF_CTRL_SF_ID0_OFFSET_POS    (0U)
+#define SF_CTRL_SF_ID0_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_ID0_OFFSET_MSK    (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)
+#define SF_CTRL_SF_ID0_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS))
+
+/* 0x438 : sf_id1_offset */
+#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438)
+#define SF_CTRL_SF_ID1_OFFSET        SF_CTRL_SF_ID1_OFFSET
+#define SF_CTRL_SF_ID1_OFFSET_POS    (0U)
+#define SF_CTRL_SF_ID1_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_ID1_OFFSET_MSK    (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)
+#define SF_CTRL_SF_ID1_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS))
+
+struct sf_ctrl_reg {
+    /* 0x0 : sf_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1         : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t sf_clk_sf_rx_inv_sel : 1; /* [    2],        r/w,        0x1 */
+            uint32_t sf_clk_out_gate_en   : 1; /* [    3],        r/w,        0x1 */
+            uint32_t sf_clk_out_inv_sel   : 1; /* [    4],        r/w,        0x1 */
+            uint32_t sf_clk_sahb_sram_sel : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t sf_if_read_dly_n     : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t sf_if_read_dly_en    : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t sf_if_int            : 1; /* [   16],          r,        0x0 */
+            uint32_t sf_if_int_clr        : 1; /* [   17],        r/w,        0x1 */
+            uint32_t sf_if_int_set        : 1; /* [   18],        r/w,        0x0 */
+            uint32_t sf_aes_dly_mode      : 1; /* [   19],        r/w,        0x0 */
+            uint32_t sf_aes_dout_endian   : 1; /* [   20],        r/w,        0x1 */
+            uint32_t sf_aes_ctr_plus_en   : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sf_aes_key_endian    : 1; /* [   22],        r/w,        0x1 */
+            uint32_t sf_aes_iv_endian     : 1; /* [   23],        r/w,        0x1 */
+            uint32_t sf_id                : 8; /* [31:24],        r/w,       0x1a */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_0;
+
+    /* 0x4 : sf_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_sr_pat_mask  : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t sf_if_sr_pat       : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t sf_if_sr_int       : 1; /* [   16],          r,        0x0 */
+            uint32_t sf_if_sr_int_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t sf_if_sr_int_set   : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19        : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t sf_if_0_ack_lat    : 3; /* [22:20],        r/w,        0x6 */
+            uint32_t reserved_23        : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t sf_if_reg_hold     : 1; /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_reg_wp       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t sf_ahb2sif_stopped : 1; /* [   26],          r,        0x0 */
+            uint32_t sf_ahb2sif_stop    : 1; /* [   27],        r/w,        0x0 */
+            uint32_t sf_if_fn_sel       : 1; /* [   28],        r/w,        0x1 */
+            uint32_t sf_if_en           : 1; /* [   29],        r/w,        0x1 */
+            uint32_t sf_ahb2sif_en      : 1; /* [   30],        r/w,        0x1 */
+            uint32_t sf_ahb2sram_en     : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_1;
+
+    /* 0x8 : sf_if_sahb_0 */
+    union {
+        struct sf_if_sahb {
+            uint32_t sf_if_busy          : 1;  /* [    0],          r,        0x0 */
+            uint32_t sf_if_0_trig        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_byte    : 10; /* [11: 2],        r/w,        0x0 */
+            uint32_t sf_if_0_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_0_adr_byte    : 3;  /* [19:17],        r/w,        0x0 */
+            uint32_t sf_if_0_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_en      : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t sf_if_0_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_0_adr_en      : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t sf_if_0_cmd_en      : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t sf_if_0_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_0_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_0;
+
+    /* 0xC : sf_if_sahb_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_1;
+
+    /* 0x10 : sf_if_sahb_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_2;
+
+    /* 0x14 : sf_if_iahb_0 */
+    union {
+        struct sf_if_iahb {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_1_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_1_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_1_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_1_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_1_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_1_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_1_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_1_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_1_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_1_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_0;
+
+    /* 0x18 : sf_if_iahb_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0],        r/w,  0x3000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_1;
+
+    /* 0x1C : sf_if_iahb_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_2;
+
+    /* 0x20 : sf_if_status_0 */
+    union {
+        struct
+        {
+            uint32_t sf_if_status_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_status_0;
+
+    /* 0x24 : sf_if_status_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_status_1 : 32; /* [31: 0],          r, 0x20000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_status_1;
+
+    /* 0x28 : sf_aes */
+    union {
+        struct
+        {
+            uint32_t sf_aes_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t sf_aes_mode      : 2;  /* [ 2: 1],        r/w,        0x0 */
+            uint32_t sf_aes_pref_trig : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf_aes_pref_busy : 1;  /* [    4],          r,        0x0 */
+            uint32_t sf_aes_status    : 27; /* [31: 5],          r,        0x2 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes;
+
+    /* 0x2C : sf_ahb2sif_status */
+    union {
+        struct
+        {
+            uint32_t sf_ahb2sif_status : 32; /* [31: 0],          r, 0x10000003 */
+        } BF;
+        uint32_t WORD;
+    } sf_ahb2sif_status;
+
+    /* 0x30 : sf_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25     : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_0;
+
+    /* 0x34 : sf_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_1;
+
+    /* 0x38 : sf_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_2;
+
+    /* 0x3C : sf_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_3;
+
+    /* 0x40 : sf_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_4;
+
+    /* 0x44 : sf_reserved */
+    union {
+        struct
+        {
+            uint32_t sf_reserved : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } sf_reserved;
+
+    /* 0x48 : sf2_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf2_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf2_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf2_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf2_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_0;
+
+    /* 0x4C : sf2_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_1;
+
+    /* 0x50 : sf2_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_2;
+
+    /* 0x54 : sf2_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_3;
+
+    /* 0x58 : sf2_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_4;
+
+    /* 0x5C : sf3_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf3_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf3_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf3_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf3_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_0;
+
+    /* 0x60 : sf3_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_1;
+
+    /* 0x64 : sf3_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_2;
+
+    /* 0x68 : sf3_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_3;
+
+    /* 0x6C : sf3_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_4;
+
+    /* 0x70 : sf_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_pad_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2         : 1;  /* [    2],       rsvd,        0x0 */
+            uint32_t sf_if_pad_sel_lock : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf_if_dtr_en       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t sf_if_dqs_en       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31      : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_2;
+
+    /* 0x74 : sf_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t sf_cmds_wrap_len   : 4;  /* [ 3: 0],        r/w,        0x6 */
+            uint32_t sf_cmds_en         : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t sf_cmds_bt_dly     : 3;  /* [ 7: 5],        r/w,        0x2 */
+            uint32_t sf_cmds_bt_en      : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_q_ini : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_mode  : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_28     : 18; /* [28:11],       rsvd,        0x0 */
+            uint32_t sf_if_1_ack_lat    : 3;  /* [31:29],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_3;
+
+    /* 0x78 : sf_if_iahb_3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_2_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_2_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_2_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_2_dat_rw      : 1;  /* [   23],        r/w,        0x1 */
+            uint32_t sf_if_2_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_2_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_2_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_2_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_2_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_2_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_3;
+
+    /* 0x7C : sf_if_iahb_4 */
+    union {
+        struct
+        {
+            uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0],        r/w, 0x38000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_4;
+
+    /* 0x80 : sf_if_iahb_5 */
+    union {
+        struct
+        {
+            uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_5;
+
+    /* 0x84 : sf_if_iahb_6 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_19       : 20; /* [19: 0],       rsvd,        0x0 */
+            uint32_t sf_if_3_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_27      : 5;  /* [27:23],       rsvd,        0x0 */
+            uint32_t sf_if_3_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_3_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_6;
+
+    /* 0x88 : sf_if_iahb_7 */
+    union {
+        struct
+        {
+            uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0],        r/w, 0xc0000000L */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_7;
+
+    /* 0x8c  reserved */
+    uint8_t RESERVED0x8c[116];
+
+    /* 0x100 : sf_ctrl_prot_en_rd */
+    union {
+        struct
+        {
+            uint32_t sf_ctrl_prot_en_rd   : 1;  /* [    0],          r,        0x1 */
+            uint32_t sf_ctrl_id0_en_rd    : 1;  /* [    1],          r,        0x1 */
+            uint32_t sf_ctrl_id1_en_rd    : 1;  /* [    2],          r,        0x1 */
+            uint32_t reserved_3_29        : 27; /* [29: 3],       rsvd,        0x0 */
+            uint32_t sf_if_0_trig_wr_lock : 1;  /* [   30],          r,        0x0 */
+            uint32_t sf_dbg_dis           : 1;  /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_prot_en_rd;
+
+    /* 0x104 : sf_ctrl_prot_en */
+    union {
+        struct
+        {
+            uint32_t sf_ctrl_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t sf_ctrl_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t sf_ctrl_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_prot_en;
+
+    /* 0x108  reserved */
+    uint8_t RESERVED0x108[248];
+
+    /* 0x200 : sf_aes_key_r0_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_0;
+
+    /* 0x204 : sf_aes_key_r0_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_1;
+
+    /* 0x208 : sf_aes_key_r0_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_2;
+
+    /* 0x20C : sf_aes_key_r0_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_3;
+
+    /* 0x210 : sf_aes_key_r0_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_4;
+
+    /* 0x214 : sf_aes_key_r0_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_5;
+
+    /* 0x218 : sf_aes_key_r0_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_6;
+
+    /* 0x21C : sf_aes_key_r0_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_7;
+
+    /* 0x220 : sf_aes_iv_r0_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w0;
+
+    /* 0x224 : sf_aes_iv_r0_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w1;
+
+    /* 0x228 : sf_aes_iv_r0_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w2;
+
+    /* 0x22C : sf_aes_iv_r0_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w3;
+
+    /* 0x230 : sf_aes_cfg_r0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_region_r0_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_region_r0_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28                : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_region_r0_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_region_r0_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_region_r0_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_cfg_r0;
+
+    /* 0x234  reserved */
+    uint8_t RESERVED0x234[204];
+
+    /* 0x300 : sf_aes_key_r1_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_0;
+
+    /* 0x304 : sf_aes_key_r1_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_1;
+
+    /* 0x308 : sf_aes_key_r1_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_2;
+
+    /* 0x30C : sf_aes_key_r1_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_3;
+
+    /* 0x310 : sf_aes_key_r1_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_4;
+
+    /* 0x314 : sf_aes_key_r1_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_5;
+
+    /* 0x318 : sf_aes_key_r1_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_6;
+
+    /* 0x31C : sf_aes_key_r1_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_7;
+
+    /* 0x320 : sf_aes_iv_r1_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w0;
+
+    /* 0x324 : sf_aes_iv_r1_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w1;
+
+    /* 0x328 : sf_aes_iv_r1_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w2;
+
+    /* 0x32C : sf_aes_iv_r1_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w3;
+
+    /* 0x330 : sf_aes_r1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_r1_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_r1_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_r1_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_r1_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_r1_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_r1;
+
+    /* 0x334  reserved */
+    uint8_t RESERVED0x334[204];
+
+    /* 0x400 : sf_aes_key_r2_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_0;
+
+    /* 0x404 : sf_aes_key_r2_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_1;
+
+    /* 0x408 : sf_aes_key_r2_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_2;
+
+    /* 0x40C : sf_aes_key_r2_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_3;
+
+    /* 0x410 : sf_aes_key_r2_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_4;
+
+    /* 0x414 : sf_aes_key_r2_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_5;
+
+    /* 0x418 : sf_aes_key_r2_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_6;
+
+    /* 0x41C : sf_aes_key_r2_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_7;
+
+    /* 0x420 : sf_aes_iv_r2_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w0;
+
+    /* 0x424 : sf_aes_iv_r2_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w1;
+
+    /* 0x428 : sf_aes_iv_r2_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w2;
+
+    /* 0x42C : sf_aes_iv_r2_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w3;
+
+    /* 0x430 : sf_aes_r2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_r2_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_r2_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_r2_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_r2_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_r2_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_r2;
+
+    /* 0x434 : sf_id0_offset */
+    union {
+        struct
+        {
+            uint32_t sf_id0_offset  : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_id0_offset;
+
+    /* 0x438 : sf_id1_offset */
+    union {
+        struct
+        {
+            uint32_t sf_id1_offset  : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_id1_offset;
+};
+
+typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t;
+
+/* 0x0 : sf_aes_key_0 */
+#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0)
+#define SF_CTRL_SF_AES_KEY_0        SF_CTRL_SF_AES_KEY_0
+#define SF_CTRL_SF_AES_KEY_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)
+#define SF_CTRL_SF_AES_KEY_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS))
+
+/* 0x4 : sf_aes_key_1 */
+#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4)
+#define SF_CTRL_SF_AES_KEY_1        SF_CTRL_SF_AES_KEY_1
+#define SF_CTRL_SF_AES_KEY_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)
+#define SF_CTRL_SF_AES_KEY_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS))
+
+/* 0x8 : sf_aes_key_2 */
+#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8)
+#define SF_CTRL_SF_AES_KEY_2        SF_CTRL_SF_AES_KEY_2
+#define SF_CTRL_SF_AES_KEY_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)
+#define SF_CTRL_SF_AES_KEY_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS))
+
+/* 0xc : sf_aes_key_3 */
+#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc)
+#define SF_CTRL_SF_AES_KEY_3        SF_CTRL_SF_AES_KEY_3
+#define SF_CTRL_SF_AES_KEY_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)
+#define SF_CTRL_SF_AES_KEY_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS))
+
+/* 0x10 : sf_aes_key_4 */
+#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10)
+#define SF_CTRL_SF_AES_KEY_4        SF_CTRL_SF_AES_KEY_4
+#define SF_CTRL_SF_AES_KEY_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)
+#define SF_CTRL_SF_AES_KEY_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS))
+
+/* 0x14 : sf_aes_key_5 */
+#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14)
+#define SF_CTRL_SF_AES_KEY_5        SF_CTRL_SF_AES_KEY_5
+#define SF_CTRL_SF_AES_KEY_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)
+#define SF_CTRL_SF_AES_KEY_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS))
+
+/* 0x18 : sf_aes_key_6 */
+#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18)
+#define SF_CTRL_SF_AES_KEY_6        SF_CTRL_SF_AES_KEY_6
+#define SF_CTRL_SF_AES_KEY_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)
+#define SF_CTRL_SF_AES_KEY_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS))
+
+/* 0x1c : sf_aes_key_7 */
+#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c)
+#define SF_CTRL_SF_AES_KEY_7        SF_CTRL_SF_AES_KEY_7
+#define SF_CTRL_SF_AES_KEY_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)
+#define SF_CTRL_SF_AES_KEY_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS))
+
+/* 0x20 : sf_aes_iv_w0 */
+#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20)
+#define SF_CTRL_SF_AES_IV_W0        SF_CTRL_SF_AES_IV_W0
+#define SF_CTRL_SF_AES_IV_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)
+#define SF_CTRL_SF_AES_IV_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS))
+
+/* 0x24 : sf_aes_iv_w1 */
+#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24)
+#define SF_CTRL_SF_AES_IV_W1        SF_CTRL_SF_AES_IV_W1
+#define SF_CTRL_SF_AES_IV_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)
+#define SF_CTRL_SF_AES_IV_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS))
+
+/* 0x28 : sf_aes_iv_w2 */
+#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28)
+#define SF_CTRL_SF_AES_IV_W2        SF_CTRL_SF_AES_IV_W2
+#define SF_CTRL_SF_AES_IV_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)
+#define SF_CTRL_SF_AES_IV_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS))
+
+/* 0x2c : sf_aes_iv_w3 */
+#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c)
+#define SF_CTRL_SF_AES_IV_W3        SF_CTRL_SF_AES_IV_W3
+#define SF_CTRL_SF_AES_IV_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)
+#define SF_CTRL_SF_AES_IV_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS))
+
+/* 0x30 : sf_aes_cfg */
+#define SF_CTRL_SF_AES_CFG_OFFSET            (0x30)
+#define SF_CTRL_SF_AES_REGION_END            SF_CTRL_SF_AES_REGION_END
+#define SF_CTRL_SF_AES_REGION_END_POS        (0U)
+#define SF_CTRL_SF_AES_REGION_END_LEN        (14U)
+#define SF_CTRL_SF_AES_REGION_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)
+#define SF_CTRL_SF_AES_REGION_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS))
+#define SF_CTRL_SF_AES_REGION_START          SF_CTRL_SF_AES_REGION_START
+#define SF_CTRL_SF_AES_REGION_START_POS      (14U)
+#define SF_CTRL_SF_AES_REGION_START_LEN      (14U)
+#define SF_CTRL_SF_AES_REGION_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)
+#define SF_CTRL_SF_AES_REGION_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS))
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN      SF_CTRL_SF_AES_REGION_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_EN             SF_CTRL_SF_AES_REGION_EN
+#define SF_CTRL_SF_AES_REGION_EN_POS         (30U)
+#define SF_CTRL_SF_AES_REGION_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_REGION_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)
+#define SF_CTRL_SF_AES_REGION_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS))
+#define SF_CTRL_SF_AES_REGION_LOCK           SF_CTRL_SF_AES_REGION_LOCK
+#define SF_CTRL_SF_AES_REGION_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_REGION_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_REGION_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS))
+
+struct sf_ctrl_aes_region_reg {
+    /* 0x0 : sf_aes_key_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_0;
+
+    /* 0x4 : sf_aes_key_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_1;
+
+    /* 0x8 : sf_aes_key_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_2;
+
+    /* 0xc : sf_aes_key_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_3;
+
+    /* 0x10 : sf_aes_key_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_4;
+
+    /* 0x14 : sf_aes_key_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_5;
+
+    /* 0x18 : sf_aes_key_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_6;
+
+    /* 0x1c : sf_aes_key_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_7;
+
+    /* 0x20 : sf_aes_iv_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w0;
+
+    /* 0x24 : sf_aes_iv_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w1;
+
+    /* 0x28 : sf_aes_iv_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w2;
+
+    /* 0x2c : sf_aes_iv_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w3;
+
+    /* 0x30 : sf_aes_cfg */
+    union {
+        struct
+        {
+            uint32_t sf_aes_region_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_region_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28             : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_region_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_region_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_region_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_cfg;
+};
+
+typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t;
+
+#define SF_CTRL_AES_REGION_OFFSET 0x200
+
+#endif /* __SF_CTRL_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/tzc_sec_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/tzc_sec_reg.h
new file mode 100755
index 0000000000..8ba37e34d2
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/include/hardware/tzc_sec_reg.h
@@ -0,0 +1,256 @@
+/**
+  ******************************************************************************
+  * @file    tzc_sec_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __TZC_SEC_REG_H__
+#define __TZC_SEC_REG_H__
+
+#include "bl602.h"
+
+/* 0x40 : tzc_rom_ctrl */
+#define TZC_SEC_TZC_ROM_CTRL_OFFSET     (0x40)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN      TZC_SEC_TZC_ROM0_R0_ID0_EN
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS  (0U)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN      TZC_SEC_TZC_ROM0_R1_ID0_EN
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN      TZC_SEC_TZC_ROM1_R0_ID0_EN
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS  (2U)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN      TZC_SEC_TZC_ROM1_R1_ID0_EN
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS  (3U)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN      TZC_SEC_TZC_ROM0_R0_ID1_EN
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS  (8U)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN      TZC_SEC_TZC_ROM0_R1_ID1_EN
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS  (9U)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN      TZC_SEC_TZC_ROM1_R0_ID1_EN
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS  (10U)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN      TZC_SEC_TZC_ROM1_R1_ID1_EN
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS  (11U)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_EN          TZC_SEC_TZC_ROM0_R0_EN
+#define TZC_SEC_TZC_ROM0_R0_EN_POS      (16U)
+#define TZC_SEC_TZC_ROM0_R0_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM0_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_EN          TZC_SEC_TZC_ROM0_R1_EN
+#define TZC_SEC_TZC_ROM0_R1_EN_POS      (17U)
+#define TZC_SEC_TZC_ROM0_R1_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM0_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_EN          TZC_SEC_TZC_ROM1_R0_EN
+#define TZC_SEC_TZC_ROM1_R0_EN_POS      (18U)
+#define TZC_SEC_TZC_ROM1_R0_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM1_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_EN          TZC_SEC_TZC_ROM1_R1_EN
+#define TZC_SEC_TZC_ROM1_R1_EN_POS      (19U)
+#define TZC_SEC_TZC_ROM1_R1_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM1_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_LOCK        TZC_SEC_TZC_ROM0_R0_LOCK
+#define TZC_SEC_TZC_ROM0_R0_LOCK_POS    (24U)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS))
+#define TZC_SEC_TZC_ROM0_R1_LOCK        TZC_SEC_TZC_ROM0_R1_LOCK
+#define TZC_SEC_TZC_ROM0_R1_LOCK_POS    (25U)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS))
+#define TZC_SEC_TZC_ROM1_R0_LOCK        TZC_SEC_TZC_ROM1_R0_LOCK
+#define TZC_SEC_TZC_ROM1_R0_LOCK_POS    (26U)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS))
+#define TZC_SEC_TZC_ROM1_R1_LOCK        TZC_SEC_TZC_ROM1_R1_LOCK
+#define TZC_SEC_TZC_ROM1_R1_LOCK_POS    (27U)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS))
+#define TZC_SEC_TZC_SBOOT_DONE          TZC_SEC_TZC_SBOOT_DONE
+#define TZC_SEC_TZC_SBOOT_DONE_POS      (28U)
+#define TZC_SEC_TZC_SBOOT_DONE_LEN      (4U)
+#define TZC_SEC_TZC_SBOOT_DONE_MSK      (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)
+#define TZC_SEC_TZC_SBOOT_DONE_UMSK     (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS))
+
+/* 0x44 : tzc_rom0_r0 */
+#define TZC_SEC_TZC_ROM0_R0_OFFSET     (0x44)
+#define TZC_SEC_TZC_ROM0_R0_END        TZC_SEC_TZC_ROM0_R0_END
+#define TZC_SEC_TZC_ROM0_R0_END_POS    (0U)
+#define TZC_SEC_TZC_ROM0_R0_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM0_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)
+#define TZC_SEC_TZC_ROM0_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS))
+#define TZC_SEC_TZC_ROM0_R0_START      TZC_SEC_TZC_ROM0_R0_START
+#define TZC_SEC_TZC_ROM0_R0_START_POS  (16U)
+#define TZC_SEC_TZC_ROM0_R0_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM0_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)
+#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS))
+
+/* 0x48 : tzc_rom0_r1 */
+#define TZC_SEC_TZC_ROM0_R1_OFFSET     (0x48)
+#define TZC_SEC_TZC_ROM0_R1_END        TZC_SEC_TZC_ROM0_R1_END
+#define TZC_SEC_TZC_ROM0_R1_END_POS    (0U)
+#define TZC_SEC_TZC_ROM0_R1_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM0_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)
+#define TZC_SEC_TZC_ROM0_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS))
+#define TZC_SEC_TZC_ROM0_R1_START      TZC_SEC_TZC_ROM0_R1_START
+#define TZC_SEC_TZC_ROM0_R1_START_POS  (16U)
+#define TZC_SEC_TZC_ROM0_R1_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM0_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)
+#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS))
+
+/* 0x4C : tzc_rom1_r0 */
+#define TZC_SEC_TZC_ROM1_R0_OFFSET     (0x4C)
+#define TZC_SEC_TZC_ROM1_R0_END        TZC_SEC_TZC_ROM1_R0_END
+#define TZC_SEC_TZC_ROM1_R0_END_POS    (0U)
+#define TZC_SEC_TZC_ROM1_R0_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM1_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)
+#define TZC_SEC_TZC_ROM1_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS))
+#define TZC_SEC_TZC_ROM1_R0_START      TZC_SEC_TZC_ROM1_R0_START
+#define TZC_SEC_TZC_ROM1_R0_START_POS  (16U)
+#define TZC_SEC_TZC_ROM1_R0_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM1_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)
+#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS))
+
+/* 0x50 : tzc_rom1_r1 */
+#define TZC_SEC_TZC_ROM1_R1_OFFSET     (0x50)
+#define TZC_SEC_TZC_ROM1_R1_END        TZC_SEC_TZC_ROM1_R1_END
+#define TZC_SEC_TZC_ROM1_R1_END_POS    (0U)
+#define TZC_SEC_TZC_ROM1_R1_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM1_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)
+#define TZC_SEC_TZC_ROM1_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS))
+#define TZC_SEC_TZC_ROM1_R1_START      TZC_SEC_TZC_ROM1_R1_START
+#define TZC_SEC_TZC_ROM1_R1_START_POS  (16U)
+#define TZC_SEC_TZC_ROM1_R1_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM1_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)
+#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS))
+
+struct tzc_sec_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[64];
+
+    /* 0x40 : tzc_rom_ctrl */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r0_id0_en : 1; /* [    0],        r/w,        0x1 */
+            uint32_t tzc_rom0_r1_id0_en : 1; /* [    1],        r/w,        0x1 */
+            uint32_t tzc_rom1_r0_id0_en : 1; /* [    2],        r/w,        0x1 */
+            uint32_t tzc_rom1_r1_id0_en : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_7       : 4; /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_id1_en : 1; /* [    8],        r/w,        0x1 */
+            uint32_t tzc_rom0_r1_id1_en : 1; /* [    9],        r/w,        0x1 */
+            uint32_t tzc_rom1_r0_id1_en : 1; /* [   10],        r/w,        0x1 */
+            uint32_t tzc_rom1_r1_id1_en : 1; /* [   11],        r/w,        0x1 */
+            uint32_t reserved_12_15     : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_en     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t tzc_rom0_r1_en     : 1; /* [   17],        r/w,        0x0 */
+            uint32_t tzc_rom1_r0_en     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t tzc_rom1_r1_en     : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20_23     : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_lock   : 1; /* [   24],        r/w,        0x0 */
+            uint32_t tzc_rom0_r1_lock   : 1; /* [   25],        r/w,        0x0 */
+            uint32_t tzc_rom1_r0_lock   : 1; /* [   26],        r/w,        0x0 */
+            uint32_t tzc_rom1_r1_lock   : 1; /* [   27],        r/w,        0x0 */
+            uint32_t tzc_sboot_done     : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom_ctrl;
+
+    /* 0x44 : tzc_rom0_r0 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom0_r0_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom0_r0;
+
+    /* 0x48 : tzc_rom0_r1 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom0_r1_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom0_r1;
+
+    /* 0x4C : tzc_rom1_r0 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom1_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom1_r0_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom1_r0;
+
+    /* 0x50 : tzc_rom1_r1 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom1_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom1_r1_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom1_r1;
+};
+
+typedef volatile struct tzc_sec_reg tzc_sec_reg_t;
+
+#endif /* __TZC_SEC_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/port/bl602_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/port/bl602_clock.c
new file mode 100755
index 0000000000..735b931172
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/port/bl602_clock.c
@@ -0,0 +1,19 @@
+#include "bflb_clock.h"
+#include "bl602_clock.h"
+
+uint32_t bflb_clk_get_system_clock(uint8_t type)
+{
+    return 0;
+}
+
+uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
+{
+    if (type == BFLB_DEVICE_TYPE_UART) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0);
+    } else if (type == BFLB_DEVICE_TYPE_SPI) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0);
+    } else if (type == BFLB_DEVICE_TYPE_I2C) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2C0);
+    }
+    return 0;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_aon.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_aon.c
new file mode 100755
index 0000000000..3f148bd447
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_aon.c
@@ -0,0 +1,551 @@
+/**
+  ******************************************************************************
+  * @file    bl602_aon.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_aon.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Private_Macros
+ *  @{
+ */
+#define AON_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group AON_Private_Macros */
+
+/** @defgroup  AON_Private_Types
+ *  @{
+ */
+
+/*@} end of group AON_Private_Types */
+
+/** @defgroup  AON_Private_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Private_Variables */
+
+/** @defgroup  AON_Global_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Global_Variables */
+
+/** @defgroup  AON_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group AON_Private_Fun_Declaration */
+
+/** @defgroup  AON_Private_Functions
+ *  @{
+ */
+
+/*@} end of group AON_Private_Functions */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Power on MXX band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL602_Delay_US(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off MXX band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power OFF */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* Polling for ready */
+    do {
+        BL602_Delay_US(10);
+        timeOut++;
+        tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
+
+    if (timeOut >= 120) {
+        return TIMEOUT;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set XTAL cap code
+ *
+ * @param  capIn: Cap code in
+ * @param  capOut: Cap code out
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    BL602_Delay_US(100);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get XTAL cap code
+ *
+ * @param  None
+ *
+ * @return Cap code
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    BL602_Delay_US(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    BL602_Delay_US(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on LDO11
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    BL602_Delay_US(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off LDO11
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    BL602_Delay_US(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power on */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL602_Delay_US(90);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power off */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power on source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power on sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL602_Delay_US(10);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power off source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off the power can be shut down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* gating Clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpVal = tmpVal & (~(1 << 6));
+    tmpVal = tmpVal & (~(1 << 7));
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL602_Delay_US(20);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL602_Delay_US(60);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL602_Delay_US(20);
+
+    /* power on wb */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    /* ungating Clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpVal = tmpVal | ((1 << 6));
+    tmpVal = tmpVal | ((1 << 7));
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  delay: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((delay <= 0x3));
+
+    /* config ldo11soc_sstart_delay_aon */
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    return SUCCESS;
+}
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_clock.c
new file mode 100755
index 0000000000..6dc62ec4bf
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_clock.c
@@ -0,0 +1,601 @@
+/**
+  ******************************************************************************
+  * @file    bl602_clock.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_clock.h"
+// #include "bl602_pwm.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Private_Macros
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Macros */
+
+/** @defgroup  CLOCK_Private_Types
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Types */
+
+/** @defgroup  CLOCK_Private_Variables
+ *  @{
+ */
+//static inline Clock_Cfg_Type clkCfg;
+
+/*@} end of group CLOCK_Private_Variables */
+
+/** @defgroup  CLOCK_Global_Variables
+ *  @{
+ */
+
+/*@} end of group CLOCK_Global_Variables */
+
+/** @defgroup  CLOCK_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Fun_Declaration */
+
+/** @defgroup  CLOCK_Private_Functions
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Functions */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+
+static inline uint32_t Clock_Xtal_Output(void)
+{
+    uint32_t tmpVal;
+
+    /* get clkpll_sdmin */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN);
+
+    switch (tmpVal) {
+        case 0x500000:
+            /* 24m */
+            return (24 * 1000 * 1000);
+
+        case 0x3C0000:
+            /* 32m */
+            return (32 * 1000 * 1000);
+
+        case 0x320000:
+            /* 38.4m */
+            return (384 * 100 * 1000);
+
+        case 0x300000:
+            /* 40m */
+            return (40 * 1000 * 1000);
+
+        case 0x49D39D:
+            /* 26m */
+            return (26 * 1000 * 1000);
+
+        default:
+            /* 32m */
+            return (32 * 1000 * 1000);
+    }
+}
+
+static inline uint32_t Clock_XClk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* rc32m */
+        return (32 * 1000 * 1000);
+    } else {
+        /* xtal */
+        return Clock_Xtal_Output();
+    }
+}
+
+static inline uint8_t Clock_Get_MCU_XClk_Sel_Val(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL);
+
+    return (tmpVal & 0x1);
+}
+
+static inline uint8_t Clock_Get_MCU_Root_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL);
+
+    return ((tmpVal >> 1) & 0x1);
+}
+
+static inline uint32_t Clock_MCU_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* pll 48m */
+        return (48 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* pll 120m */
+        return (120 * 1000 * 1000);
+    } else if (sel == 2) {
+        /* pll 160m */
+        return (160 * 1000 * 1000);
+    } else if (sel == 3) {
+        /* pll 192m */
+        return (192 * 1000 * 1000);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint32_t Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
+{
+    uint32_t tmpVal;
+
+    if (sel == 0) {
+        /* xclk */
+        return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+    } else if (sel == 1) {
+        /* pll */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL);
+        return Clock_MCU_Clk_Mux_Output(tmpVal);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t Clock_Get_MCU_HClk_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
+}
+
+static inline uint8_t Clock_Get_Peri_BClk_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
+}
+
+static inline uint32_t Clock_F32k_Mux_Output(uint8_t sel)
+{
+    uint32_t tmpVal;
+    uint32_t div = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV);
+
+    if (sel == 0) {
+        /* src32K */
+        return (32 * 1000);
+    } else if (sel == 1) {
+        /* xtal 32K */
+        return (32 * 1000);
+    } else {
+        return Clock_Xtal_Output() / (div + 1);
+    }
+}
+
+static inline uint8_t Clock_Get_F32k_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get System Clock
+ *
+ * @param  type: System clock type
+ *
+ * @return System clock value
+ *
+*******************************************************************************/
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type)
+{
+    uint32_t clock = 0;
+    uint32_t div = 0;
+
+    switch (type) {
+        case BL_SYSTEM_CLOCK_XCLK:
+            /*!< mcu xclk clock */
+            return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+
+        case BL_SYSTEM_CLOCK_ROOT:
+            /*!< mcu root clock */
+            return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+
+        case BL_SYSTEM_CLOCK_FCLK:
+            /*!< mcu fast clock/cpu clock */
+            clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+            div = Clock_Get_MCU_HClk_Div_Val();
+            return clock / (div + 1);
+
+        case BL_SYSTEM_CLOCK_BCLK:
+            /*!< mcu peri bus clock */
+            clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
+            div = Clock_Get_Peri_BClk_Div_Val();
+            return clock / (div + 1);
+
+        case BL_SYSTEM_CLOCK_XTAL:
+            /*!< xtal clock */
+            return Clock_Xtal_Output();
+
+        case BL_SYSTEM_CLOCK_F32K:
+            /*!< f32k clock */
+            return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+
+        default:
+            return 0;
+    }
+}
+
+static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* fclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
+    } else {
+        /* 160m */
+        return (160 * 1000 * 1000);
+    }
+}
+
+static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_UART_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
+}
+
+static inline uint32_t Clock_SPI_Clk_Mux_Output(void)
+{
+    /* pbclk */
+    return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+}
+
+static inline uint8_t Clock_Get_SPI_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
+}
+
+static inline uint32_t Clock_I2C_Clk_Mux_Output()
+{
+    /* pbclk */
+    return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+}
+
+static inline uint8_t Clock_Get_I2C_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_GPADC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* 96m */
+        return (96 * 1000 * 1000);
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
+{
+    uint32_t div = 0;
+
+    if (sel == 1) {
+        /* f32k clk */
+        return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+    } else {
+        div = Clock_Get_GPADC_Div_Val();
+        return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1);
+    }
+}
+
+static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN);
+}
+
+static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* pll 32m */
+        return (32 * 1000 * 1000);
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
+}
+
+static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
+}
+
+// static inline uint32_t Clock_PWM_Clk_Mux_Output(uint8_t sel)
+// {
+//     if (sel == 0) {
+//         /* xclk */
+//         return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+//     } else if (sel == 1) {
+//         /* pbclk */
+//         return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+//     } else {
+//         /* f32k clk */
+//         return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+//     }
+// }
+
+// static inline uint8_t Clock_Get_PWM_Div_Val(void)
+// {
+//     uint32_t tmpVal;
+
+//     tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
+
+//     return tmpVal;
+// }
+
+// static inline uint8_t Clock_Get_PWM_Clk_Sel_Val(void)
+// {
+//     uint32_t tmpVal;
+
+//     tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CONFIG);
+
+//     return BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL);
+// }
+
+static inline uint32_t Clock_IR_Clk_Mux_Output(void)
+{
+    /* xclk */
+    return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+}
+
+static inline uint8_t Clock_Get_IR_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
+}
+
+static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* 120m */
+        return (120 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else {
+        /* 48m */
+        return (48 * 1000 * 1000);
+    }
+}
+
+static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* sf sel2 */
+        return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val());
+    } else if (sel == 1) {
+        /* 80m */
+        return (80 * 1000 * 1000);
+    } else if (sel == 2) {
+        /* pbclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+    } else {
+        /* 96m */
+        return (96 * 1000 * 1000);
+    }
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SF_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Peripheral Clock
+ *
+ * @param  type: Peripheral clock type
+ *
+ * @return Peripheral clock value
+ *
+*******************************************************************************/
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
+{
+    uint32_t clock = 0;
+    uint32_t div = 0;
+
+    switch (type) {
+        /*!< uart0 clock */
+        case BL_PERIPHERAL_CLOCK_UART0:
+            ATTR_FALLTHROUGH();
+
+        /*!< uart1 clock */
+        case BL_PERIPHERAL_CLOCK_UART1:
+            clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val());
+            div = Clock_Get_UART_Div_Val();
+            return clock / (div + 1);
+
+        /*!< FLASH clock */
+        case BL_PERIPHERAL_CLOCK_FLASH:
+            clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val());
+            div = Clock_Get_SF_Div_Val();
+            return clock / (div + 1);
+
+        /*!< spi0 clock */
+        case BL_PERIPHERAL_CLOCK_SPI0:
+            clock = Clock_SPI_Clk_Mux_Output();
+            div = Clock_Get_SPI_Div_Val();
+            return clock / (div + 1);
+
+        /*!< i2c0 clock */
+        case BL_PERIPHERAL_CLOCK_I2C0:
+            clock = Clock_I2C_Clk_Mux_Output();
+            div = Clock_Get_I2C_Div_Val();
+            return clock / (div + 1);
+
+        /*!< GPADC clock */
+        case BL_PERIPHERAL_CLOCK_GPADC:
+            return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val());
+
+        /*!< GPDAC clock */
+        case BL_PERIPHERAL_CLOCK_GPDAC:
+            clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val());
+            div = Clock_Get_GPDAC_Div_Val();
+            return clock / (div + 1);
+
+        /*!< PWM clock */
+        // case BL_PERIPHERAL_CLOCK_PWM:
+        //     clock = Clock_PWM_Clk_Mux_Output(Clock_Get_PWM_Clk_Sel_Val());
+        //     div = Clock_Get_PWM_Div_Val();
+        //     return clock / div;
+
+        /*!< IR clock */
+        case BL_PERIPHERAL_CLOCK_IR:
+            clock = Clock_IR_Clk_Mux_Output();
+            div = Clock_Get_IR_Div_Val();
+            return clock / (div + 1);
+
+        default:
+            return 0;
+    }
+}
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_common.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_common.c
new file mode 100755
index 0000000000..473b30f85e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_common.c
@@ -0,0 +1,162 @@
+#include "l1c_reg.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Periph_Driver
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  core:  systemcoreclock
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+#ifdef ARCH_ARM
+#ifndef __GNUC__
+__WEAK
+__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr
+}
+#else
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    __asm__ __volatile__(
+        "lsr r0,#0x10\n\t"
+        "mul r0,r1,r0\n\t"
+        "mov r2,r0\n\t"
+        "lsr r2,#0x04\n\t"
+        "lsr r2,#0x03\n\t"
+        "cmp r2,#0x01\n\t"
+        "beq end\n\t"
+        "cmp r2,#0x00\n\t"
+        "beq end\n"
+        "loop :"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "sub r2,r2,#0x01\n\t"
+        "cmp r2,#0x00\n\t"
+        "bne loop\n"
+        "end :"
+        "mov r0,r0\n\t");
+}
+#endif
+#endif
+#ifdef ARCH_RISCV
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    uint32_t codeAddress = 0;
+    uint32_t divVal = 40;
+
+    codeAddress = (uint32_t)&ASM_Delay_Us;
+
+    /* 1M=100K*10, so multiple is 10 */
+    /* loop function take 4 instructions, so instructionNum is 4 */
+    /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */
+    /* divVal = multiple*instructionNum*irom2TAccess */
+    if (((codeAddress & (0xF << 24)) >> 24) == 0x01) {
+        /* IROM space */
+        if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) {
+            /* instruction 2T */
+            divVal = 80;
+        }
+    }
+
+    __asm__ __volatile__(
+        ".align 4\n\t"
+        "lw       a4,%1\n\t"
+        "lui   a5,0x18\n\t"
+        "addi  a5,a5,1696\n\t"
+        "divu  a5,a4,a5\n\t"
+        "sw       a5,%1\n\t"
+        "lw       a4,%1\n\t"
+        "lw       a5,%0\n\t"
+        "mul   a5,a4,a5\n\t"
+        "sw       a5,%1\n\t"
+        "lw       a4,%1\n\t"
+        "lw       a5,%2\n\t"
+        "divu  a5,a4,a5\n\t"
+        "sw    a5,%1\n\t"
+        "lw    a5,%1\n\t"
+        "li    a4,0x1\n\t"
+        "beq   a5,zero,end\n\t"
+        "beq   a5,a4,end\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        ".align 4\n\t"
+        "loop  :\n"
+        "addi  a4,a5,-1\n\t"
+        "mv    a5,a4\n\t"
+        "bnez  a5,loop\n\t"
+        "nop\n\t"
+        "end   :\n\t"
+        "nop\n"
+        :                                  /* output */
+        : "m"(cnt), "m"(core), "m"(divVal) /* input */
+        : "t1", "a4", "a5"                 /* destruct description */
+    );
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt)
+{
+    ASM_Delay_Us(SystemCoreClockGet(), cnt);
+}
+
+/****************************************************************************/ /**
+ * @brief      delay ms
+ *
+ * @param[in]  cnt:  delay cnt ms
+ *
+ * @return none
+ *
+ *******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt)
+{
+    uint32_t i = 0;
+    uint32_t count = 0;
+
+    if (cnt >= 1024) {
+        /* delay (n*1024) ms */
+        count = 1024;
+
+        for (i = 0; i < (cnt / 1024); i++) {
+            BL602_Delay_US(1024 * 1000);
+        }
+    }
+
+    if (cnt & 0x3FF) {
+        /* delay (1-1023)ms */
+        count = cnt & 0x3FF;
+        BL602_Delay_US(count * 1000);
+    }
+
+    //BL602_Delay_US((count<<10)-(count<<4)-(count<<3));
+}
+#endif
+
+/*@} end of group DRIVER_Public_Functions */
+
+/*@} end of group DRIVER_COMMON */
+
+/*@} end of group BL602_Periph_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_ef_cfg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_ef_cfg.c
new file mode 100755
index 0000000000..e23972bd39
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_ef_cfg.c
@@ -0,0 +1,413 @@
+/**
+  ******************************************************************************
+  * @file    bl602_ef_cfg.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "bl602_ef_cfg.h"
+#include "bl602_glb.h"
+#include "hardware/ef_data_reg.h"
+
+extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+
+static bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
+    {
+        .name = "rc32m",
+        .en_addr = 0x78 * 8 + 1,
+        .parity_addr = 0x78 * 8 + 0,
+        .value_addr = 0x7C * 8 + 4,
+        .value_len = 8,
+    },
+    {
+        .name = "rc32k",
+        .en_addr = 0xEC * 8 + 19,
+        .parity_addr = 0xEC * 8 + 18,
+        .value_addr = 0xEC * 8 + 8,
+        .value_len = 10,
+    },
+    {
+        .name = "gpadc_gain",
+        .en_addr = 0xF0 * 8 + 27,
+        .parity_addr = 0xF0 * 8 + 26,
+        .value_addr = 0xF0 * 8 + 14,
+        .value_len = 12,
+    },
+    {
+        .name = "tsen",
+        .en_addr = 0xF0 * 8 + 13,
+        .parity_addr = 0xF0 * 8 + 12,
+        .value_addr = 0xF0 * 8 + 0,
+        .value_len = 12,
+    }
+};
+
+static GLB_ROOT_CLK_Type rtClk;
+static uint8_t bdiv, hdiv;
+
+/****************************************************************************/ /**
+ * @brief  Efuse read write switch clock save
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_save(void)
+{
+    /* all API should be place at tcm section */
+    bdiv = GLB_Get_BCLK_Div();
+    hdiv = GLB_Get_HCLK_Div();
+    rtClk = GLB_Get_Root_CLK_Sel();
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
+    GLB_Set_System_CLK_Div(0, 0);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read write switch clock restore
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_restore(void)
+{
+    /* all API should be place at tcm section */
+    GLB_Set_System_CLK_Div(hdiv, bdiv);
+    HBN_Set_ROOT_CLK_Sel(rtClk);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse get trim list
+ *
+ * @param  trim_list: Trim list pointer
+ *
+ * @return Trim list count
+ *
+*******************************************************************************/
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
+{
+    *ptrim_list = &trim_list[0];
+    return sizeof(trim_list) / sizeof(trim_list[0]);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read device info
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
+{
+    uint32_t *p = (uint32_t *)deviceInfo;
+    uint32_t tmpval;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, p, 1, 1);
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+    deviceInfo->chip_ver = (tmpval >> 8) & 0x7;
+}
+
+void bflb_efuse_get_chipid(uint8_t chipid[8])
+{
+    bflb_efuse_read_mac_address_opt(0, chipid, 1);
+    chipid[6] = 0;
+    chipid[7] = 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Whether MAC address slot is empty
+ *
+ * @param  slot: MAC address slot
+ * @param  reload: whether  reload to check
+ *
+ * @return 0 for all slots full,1 for others
+ *
+*******************************************************************************/
+uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
+{
+    uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
+    uint32_t part1Empty = 0, part2Empty = 0;
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmp2, 1, reload);
+    }
+
+    part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
+    part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
+
+    return (part1Empty && part2Empty);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse write optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  program: Whether program
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval;
+    uint32_t i = 0, cnt;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    /* Change to local order */
+    for (i = 0; i < 3; i++) {
+        tmpval = mac[i];
+        mac[i] = mac[5 - i];
+        mac[5 - i] = tmpval;
+    }
+
+    /* The low 32 bits */
+    tmpval = BL_RDWD_FRM_BYTEP(maclow);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, program);
+    }
+
+    /* The high 16 bits */
+    tmpval = machigh[0] + (machigh[1] << 8);
+    cnt = 0;
+
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    tmpval |= ((cnt & 0x3f) << 16);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, program);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  reload: Whether reload
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval = 0;
+    uint32_t i = 0;
+    uint32_t cnt = 0;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, reload);
+    }
+
+    BL_WRWD_TO_BYTEP(maclow, tmpval);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, reload);
+    }
+
+    machigh[0] = tmpval & 0xff;
+    machigh[1] = (tmpval >> 8) & 0xff;
+
+    /* Check parity */
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) {
+        /* Change to network order */
+        for (i = 0; i < 3; i++) {
+            tmpval = mac[i];
+            mac[i] = mac[5 - i];
+            mac[5 - i] = tmpval;
+        }
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+float bflb_efuse_get_adc_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+    uint32_t tmp;
+
+    float coe = 1.0;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
+
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            tmp = trim.value;
+
+            if (tmp & 0x800) {
+                tmp = ~tmp;
+                tmp += 1;
+                tmp = tmp & 0xfff;
+                coe = (1.0 + ((float)tmp / 2048.0));
+            } else {
+                coe = (1.0 - ((float)tmp / 2048.0));
+            }
+        }
+    }
+
+    return coe;
+}
+
+uint32_t bflb_efuse_get_adc_tsen_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            return trim.value;
+        }
+    }
+
+    return 2042;
+}
+
+void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
+{
+    uint32_t tmpval = 0;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+    *sign = ((tmpval & EF_DATA_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_EF_SBOOT_SIGN_MODE_POS) & 0x01;
+    *aes = ((tmpval & EF_DATA_EF_SF_AES_MODE_MSK) >> EF_DATA_EF_SF_AES_MODE_POS);
+}
+
+void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if (index > 5) {
+        return;
+    }
+
+    bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+}
+
+void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if (index > 5) {
+        return;
+    }
+
+    bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+}
+
+void bflb_efuse_lock_aes_key_write(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if (index > 5) {
+        return;
+    }
+    /* write lock */
+    if (index <= 3) {
+        lock |= (1 << (index + 19));
+    } else {
+        lock |= (1 << (index + 19));
+        lock |= (1 << (index - 4 + 13));
+    }
+    bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
+}
+
+void bflb_efuse_lock_aes_key_read(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if (index > 5) {
+        return;
+    }
+    /* read lock */
+    lock |= (1 << (index + 26));
+
+    bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
+}
+
+void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
+{
+    if (index != 0) {
+        return;
+    }
+    bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
+}
+
+void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
+{
+    if (index != 0) {
+        return;
+    }
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_glb.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_glb.c
new file mode 100755
index 0000000000..324f484044
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_glb.c
@@ -0,0 +1,2619 @@
+/**
+  ******************************************************************************
+  * @file    bl602_glb.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_glb.h"
+#include "bl602_hbn.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Private_Macros
+ *  @{
+ */
+#define GLB_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+#define GLB_GPIO_Get_Reg(pin)       (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4)
+#define GLB_GPIO_INT0_NUM           (23)
+#define GLB_REG_BCLK_DIS_TRUE       (*(volatile uint32_t *)(0x40000FFC) = (0x00000001))
+#define GLB_REG_BCLK_DIS_FALSE      (*(volatile uint32_t *)(0x40000FFC) = (0x00000000))
+#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
+
+/*@} end of group GLB_Private_Macros */
+
+/** @defgroup  GLB_Private_Types
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Types */
+
+/** @defgroup  GLB_Private_Variables
+ *  @{
+ */
+static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL };
+static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };
+static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL };
+
+/*@} end of group GLB_Private_Variables */
+
+/** @defgroup  GLB_Global_Variables
+ *  @{
+ */
+
+/*@} end of group GLB_Global_Variables */
+
+/** @defgroup  GLB_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Fun_Declaration */
+
+/** @defgroup  GLB_Private_Functions
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Functions */
+
+/** @defgroup  GLB_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  get root clock selection
+ *
+ * @param  None
+ *
+ * @return root clock selection
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) {
+        case 0:
+            return GLB_ROOT_CLK_RC32M;
+
+        case 1:
+            return GLB_ROOT_CLK_XTAL;
+
+        case 2:
+            return GLB_ROOT_CLK_PLL;
+
+        case 3:
+            return GLB_ROOT_CLK_PLL;
+
+        default:
+            return GLB_ROOT_CLK_RC32M;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set System clock divider
+ *
+ * @param  hclkDiv: HCLK divider
+ * @param  bclkDiv: BCLK divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* recommended: fclk<=160MHz, bclk<=80MHz */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1));
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get Bus clock divider
+ *
+ * @param  None
+ *
+ * @return Clock Divider
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get CPU clock divider
+ *
+ * @param  None
+ *
+ * @return Clock Divider
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  update SystemCoreClock value
+ *
+ * @param  xtalType: XTAL frequency type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType)
+{
+    CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType));
+
+    switch (xtalType) {
+        case GLB_PLL_XTAL_NONE:
+            break;
+
+        case GLB_PLL_XTAL_24M:
+            SystemCoreClockSet(24000000);
+            break;
+
+        case GLB_PLL_XTAL_32M:
+            SystemCoreClockSet(32000000);
+            break;
+
+        case GLB_PLL_XTAL_38P4M:
+            SystemCoreClockSet(38400000);
+            break;
+
+        case GLB_PLL_XTAL_40M:
+            SystemCoreClockSet(40000000);
+            break;
+
+        case GLB_PLL_XTAL_26M:
+            SystemCoreClockSet(26000000);
+            break;
+
+        case GLB_PLL_XTAL_RC32M:
+            SystemCoreClockSet(32000000);
+            break;
+
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set System clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  clkFreq: clock frequency selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_PLL_XTAL_TYPE(xtalType));
+    CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq));
+
+    /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+
+    /* Before config XTAL and PLL ,make sure root clk is from RC32M */
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
+    GLB_Set_System_CLK_Div(0, 0);
+    SystemCoreClockSet(32 * 1000 * 1000);
+
+    /* Select PKA clock from hclk */
+    GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_HCLK);
+
+    if (xtalType == GLB_PLL_XTAL_NONE) {
+        if (clkFreq == GLB_SYS_CLK_RC32M) {
+            return SUCCESS;
+        } else {
+            return ERROR;
+        }
+    }
+
+    if (xtalType != GLB_PLL_XTAL_RC32M) {
+        /* power on xtal first */
+        AON_Power_On_XTAL();
+    }
+
+    /* always power up PLL and enable all PLL clock output */
+    PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType);
+    BL602_Delay_US(55);
+    PDS_Enable_PLL_All_Clks();
+
+    /* reg_pll_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+
+    /* select pll output clock before select root clock */
+    if (clkFreq >= GLB_SYS_CLK_PLL48M) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_PLL48M);
+        BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    }
+
+    /* select root clock */
+    switch (clkFreq) {
+        case GLB_SYS_CLK_RC32M:
+            break;
+
+        case GLB_SYS_CLK_XTAL:
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL);
+            Update_SystemCoreClockWith_XTAL(xtalType);
+            break;
+
+        case GLB_SYS_CLK_PLL48M:
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
+            SystemCoreClockSet(48 * 1000 * 1000);
+            break;
+
+        case GLB_SYS_CLK_PLL120M:
+            GLB_Set_System_CLK_Div(0, 1);
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
+            SystemCoreClockSet(120 * 1000 * 1000);
+            break;
+
+        case GLB_SYS_CLK_PLL160M:
+            L1C_IROM_2T_Access_Set(ENABLE);
+            GLB_Set_System_CLK_Div(0, 1);
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
+            SystemCoreClockSet(160 * 1000 * 1000);
+            break;
+
+        case GLB_SYS_CLK_PLL192M:
+            L1C_IROM_2T_Access_Set(ENABLE);
+            GLB_Set_System_CLK_Div(0, 1);
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_PLL);
+            SystemCoreClockSet(192 * 1000 * 1000);
+            break;
+
+        default:
+            break;
+    }
+
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* select PKA clock from 120M since we power up PLL */
+    GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_PLL120M);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  This is demo for user that use RC32M as default bootup clock instead of PLL,when APP is
+ *         started, this function can be called to set PLL to 160M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void)
+{
+    SF_Ctrl_Cfg_Type sfCtrlCfg = {
+        .owner = SF_CTRL_OWNER_IAHB,
+        .clkDelay = 1,
+        .clkInvert = 1,
+        .rxClkInvert = 1,
+        .doDelay = 0,
+        .diDelay = 0,
+        .oeDelay = 0,
+    };
+    /* Use RC32M as PLL ref source to set up PLL to 160M */
+    GLB_Set_System_CLK(GLB_PLL_XTAL_RC32M, GLB_SYS_CLK_PLL160M);
+    /* Flash controller also need changes since system (bus) clock changed */
+    SF_Ctrl_Enable(&sfCtrlCfg);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set BLE clock
+ *
+ * @param  enable: Enable or disable BLE clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set wifi core clock divider
+ *
+ * @param  clkDiv: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_WiFi_Core_CLK(uint8_t clkDiv)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((clkDiv <= 0x3));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_CORE_DIV, clkDiv);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set wifi encryption clock
+ *
+ * @param  clkDiv: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_WiFi_Encrypt_CLK(uint8_t clkDiv)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((clkDiv <= 0x3));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFI_MAC_WT_DIV, clkDiv);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DMA clock
+ *
+ * @param  enable: Enable or disable BLE clock
+ * @param  clk: DMA clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);
+
+    if (enable) {
+        tmpVal2 |= (1 << clk);
+    } else {
+        tmpVal2 &= (~(1 << clk));
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set IR clock divider
+ *
+ * @param  enable: enable or disable IR clock
+ * @param  clkSel: IR clock type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set sflash clock
+ *
+ * @param  enable: enable or disable sflash clock
+ * @param  clkSel: sflash clock type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+    GLB_PLL_CLK_Type clk;
+
+    CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x7));
+
+    /* disable SFLASH clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Select flash clock, all Flash CLKs are divied by PLL_480M */
+    clk = GLB_PLL_CLK_480M;
+    PDS_Enable_PLL_Clk((PDS_PLL_CLK_Type)clk);
+    /* clock divider */
+    /* Select flash clock, all Flash CLKs are divied by PLL_480M */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);
+
+    switch (clkSel) {
+        case GLB_SFLASH_CLK_120M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);
+            break;
+
+        case GLB_SFLASH_CLK_XTAL:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);
+            break;
+
+        case GLB_SFLASH_CLK_48M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);
+            break;
+
+        case GLB_SFLASH_CLK_80M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);
+            break;
+
+        case GLB_SFLASH_CLK_BCLK:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);
+            break;
+
+        case GLB_SFLASH_CLK_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);
+            break;
+
+        default:
+            break;
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* enable or disable flash clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set UART clock
+ *
+ * @param  enable: Enable or disable UART clock
+ * @param  clkSel: UART clock type
+ * @param  div: UART clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x7));
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    /* disable UART clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Set div */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Select clock source for uart */
+    HBN_Set_UART_CLK_Sel(clkSel);
+
+    /* Set enable or disable */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2C clock
+ *
+ * @param  enable: Enable or disable I2C clock
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set SPI clock
+ *
+ * @param  enable: Enable or disable SPI clock
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select PKA clock source
+ *
+ * @param  clkSel: PKA clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software system reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL602_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software CPU reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL602_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software power on reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL602_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Reset slave 1
+ *
+ * @param  slave1: slave num
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal &= (~(1 << slave1));
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal |= (1 << slave1);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal &= (~(1 << slave1));
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  clock gate
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  slave1: AHB slaveClk type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1)
+{
+    uint32_t tmpVal = 0;
+
+    if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) ||
+        (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) ||
+        (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) {
+        /* not support */
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+
+    if (enable) {
+        /* clear bit means clock gate */
+        tmpVal &= (~(1 << slave1));
+    } else {
+        /* set bit means clock pass */
+        tmpVal |= (1 << slave1);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX init
+ *
+ * @param  BmxCfg: BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler);
+    Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX address monitor enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX address monitor disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX bus error response enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_BusErrResponse_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX bus error response disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_BusErrResponse_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get BMX error status
+ *
+ * @param  errType: BMX error status type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+
+    if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET;
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get BMX error address
+ *
+ * @param  None
+ *
+ * @return NP BMX error address
+ *
+*******************************************************************************/
+uint32_t GLB_BMX_Get_Err_Addr(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR);
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX error interrupt callback install
+ *
+ * @param  intType: BMX error interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType));
+
+    glbBmxErrIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX ERR interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_ERR_IRQHandler(void)
+{
+    BMX_ERR_INT_Type intType;
+
+    for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) {
+        if (glbBmxErrIntCbfArra[intType] != NULL) {
+            glbBmxErrIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        MSG("BMX_ERR_IRQHandler\r\n");
+        BL602_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  BMX timeout interrupt callback install
+ *
+ * @param  intType: BMX timeout interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));
+
+    glbBmxToIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX Time Out interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_TO_IRQHandler(void)
+{
+    BMX_TO_INT_Type intType;
+
+    for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) {
+        if (glbBmxToIntCbfArra[intType] != NULL) {
+            glbBmxToIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        MSG("BMX_TO_IRQHandler\r\n");
+        BL602_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set sram_ret value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_ret value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_RET(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_RET);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_slp value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_slp value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_SLP(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_param value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_parm value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_PARM(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM);
+}
+
+/****************************************************************************/ /**
+ * @brief  select EM type
+ *
+ * @param  emType: EM type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_EM_TYPE(emType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType);
+    BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap UART gpio pins sig function
+ *
+ * @param  swapSel: UART swap set gpio pins selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((swapSel <= 0x7));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap JTAG gpio pins function
+ *
+ * @param  swapSel: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((swapSel <= 0x3F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap SPI0 MOSI with MISO
+ *
+ * @param  newState: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select SPI_0 act mode
+ *
+ * @param  mod: SPI work mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  use internal flash
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  use external flash
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Deswap internal flash IO3 and IO0 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Swap internal flash IO3 and IO0 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set MTimer clock
+ *
+ * @param  enable: enable or disable MTimer clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1FFFF));
+
+    /* disable MTimer clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set ADC clock
+ *
+ * @param  enable: enable frequency divider or not
+ * @param  clkSel: ADC clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));
+
+    /* disable ADC clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DAC clock
+ *
+ * @param  enable: enable frequency divider or not
+ * @param  clkSel: ADC clock selection
+ * @param  div: src divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+
+    if (clkSel == GLB_DAC_CLK_32M) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL);
+    } else {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_CLK_SRC_SEL);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  platform wakeup will becomes one of  pds_wakeup source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Platform_Wakeup_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  platform wakeup will not becomes one of  pds_wakeup source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Platform_Wakeup_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select DIG clock source
+ *
+ * @param  clkSel: DIG clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+    uint32_t dig512kEn;
+    uint32_t dig32kEn;
+
+    /* disable DIG512K and DIG32K clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);
+    dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    /* repristinate DIG512K and DIG32K clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 512K clock
+ *
+ * @param  enable: enable or disable DIG 512K clock
+ * @param  compensation: enable or disable DIG 512K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    if (compensation) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 32K clock
+ *
+ * @param  enable: enable or disable DIG 32K clock
+ * @param  compensation: enable or disable DIG 32K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    if (compensation) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set BT coex signal
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal
+ * @param  bandWidth: BT Bandwidth
+ * @param  pti: BT Packet Traffic Information
+ * @param  channel: BT Channel
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth));
+    CHECK_PARAM((pti <= 0xF));
+    CHECK_PARAM((channel <= 78));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select UART signal function
+ *
+ * @param  sig: UART signal
+ * @param  fun: UART function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)
+{
+    uint32_t sig_pos = 0;
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));
+    CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
+    sig_pos = (sig * 4);
+    /* Clear original val */
+    tmpVal &= (~(0xf << sig_pos));
+    /* Set new value */
+    tmpVal |= (fun << sig_pos);
+    BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select ir rx gpio (gpio11~gpio13)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    /* Select gpio between gpio11 and gpio13 */
+    if (gpio > 10 && gpio < 14) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 10);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    /* Close ir rx */
+    if (gpio == 0) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable ir led driver
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Enable led driver */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable ir led driver
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Disable led driver */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set ir led driver ibias
+ *
+ * @param  ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias)
+{
+    uint32_t tmpVal = 0;
+
+    /* Set driver ibias */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO initialization
+ *
+ * @param  cfg: GPIO configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+    uint8_t gpioPin = cfg->gpioPin;
+    uint32_t *pOut;
+    uint32_t pos;
+    uint32_t tmpOut;
+    uint32_t tmpVal;
+
+    /* drive strength(drive) = 0  <=>  8.0mA  @ 3.3V */
+    /* drive strength(drive) = 1  <=>  9.6mA  @ 3.3V */
+    /* drive strength(drive) = 2  <=>  11.2mA @ 3.3V */
+    /* drive strength(drive) = 3  <=>  12.8mA @ 3.3V */
+
+    pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+    pos = gpioPin % 32;
+    tmpOut = *pOut;
+
+    /* Disable output anyway*/
+    tmpOut &= (~(1 << pos));
+    *pOut = tmpOut;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    if (gpioPin % 2 == 0) {
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            /* Set input or output */
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+                tmpOut |= (1 << pos);
+            } else {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            }
+
+            /* Set pull up or down */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+
+            if (cfg->pullType == GPIO_PULL_UP) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            } else if (cfg->pullType == GPIO_PULL_DOWN) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+            }
+        } else {
+            /* analog mode */
+
+            /* clear ie && oe */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            tmpOut &= ~(1 << pos);
+
+            /* clear pu && pd */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+        }
+
+        /* set drive && smt && func */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
+    } else {
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            /* Set input or output */
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+                tmpOut |= (1 << pos);
+            } else {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+            }
+
+            /* Set pull up or down */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+
+            if (cfg->pullType == GPIO_PULL_UP) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            } else if (cfg->pullType == GPIO_PULL_DOWN) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+            }
+        } else {
+            /* analog mode */
+
+            /* clear ie && oe */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+            tmpOut &= ~(1 << pos);
+
+            /* clear pu && pd */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+        }
+
+        /* set drive && smt && func */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+    *pOut = tmpOut;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  init GPIO function in pin list
+ *
+ * @param  gpioFun: GPIO pin function
+ * @param  pinList: GPIO pin list
+ * @param  cnt: GPIO pin count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_0,
+        .gpioFun = (uint8_t)gpioFun,
+        .gpioMode = GPIO_MODE_AF,
+        .pullType = GPIO_PULL_UP,
+        .drive = 1,
+        .smtCtrl = 1
+    };
+
+    if (gpioFun == GPIO_FUN_ANALOG) {
+        gpioCfg.gpioMode = GPIO_MODE_ANALOG;
+    }
+
+    for (uint8_t i = 0; i < cnt; i++) {
+        gpioCfg.gpioPin = pinList[i];
+        GLB_GPIO_Init(&gpioCfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t pinOffset;
+
+    pinOffset = (gpioPin >> 1) << 2;
+    tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
+
+    if (gpioPin % 2 == 0) {
+        /* [0] is ie */
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    } else {
+        /* [16] is ie */
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+    }
+
+    *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t pinOffset;
+
+    pinOffset = (gpioPin >> 1) << 2;
+    tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
+
+    if (gpioPin % 2 == 0) {
+        /* [0] is ie */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    } else {
+        /* [16] is ie */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+    }
+
+    *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
+    tmpVal = tmpVal | (1 << gpioPin);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
+    tmpVal = tmpVal & ~(1 << gpioPin);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  GPIO set High-Z
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+    uint32_t *pOut;
+    uint32_t pos;
+    uint32_t tmpOut;
+    uint32_t tmpVal;
+
+    pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+    pos = gpioPin % 32;
+    tmpOut = *pOut;
+
+    /* Disable output anyway*/
+    tmpOut &= (~(1 << pos));
+    *pOut = tmpOut;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    /* select GPIO_FUN_GPIO as FUNC_SEL */
+    if (gpioPin % 2 == 0) {
+        tmpVal = (tmpVal & 0xffff0000);
+        tmpVal |= 0x0B00;
+    } else {
+        tmpVal = (tmpVal & 0x0000ffff);
+        tmpVal |= (0x0B00 << 16);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+    /* Disable output anyway*/
+    *pOut = tmpOut;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  GPIO set Pull up
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullUp(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    /* Set Pull up */
+    if (gpioPin % 2 == 0) {
+        tmpVal &= (~(1 << 5));
+        tmpVal |= (1 << 4);
+    } else {
+        tmpVal &= (~(1 << 21));
+        tmpVal |= (1 << 20);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set Pull down
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_PullDown(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    /* Set Pull up */
+    if (gpioPin % 2 == 0) {
+        tmpVal &= (~(1 << 4));
+        tmpVal |= (1 << 5);
+    } else {
+        tmpVal &= (~(1 << 20));
+        tmpVal |= (1 << 21);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GPIO function
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO function
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    if (gpioPin % 2 == 0) {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get GPIO0-GPIO5 real function
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO real function
+ *
+*******************************************************************************/
+GLB_GPIO_REAL_MODE_Type GLB_GPIO_Get_Real_Fun(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((gpioPin <= GLB_GPIO_PIN_5));
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    if (gpioPin % 2 == 0) {
+        return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_0_FUNC_SEL);
+    } else {
+        return (GLB_GPIO_REAL_MODE_Type)BL_GET_REG_BITS_VAL(tmpVal, GLB_REAL_GPIO_1_FUNC_SEL);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Write GPIO
+ *
+ * @param  gpioPin: GPIO type
+ * @param  val: GPIO value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
+{
+    uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2));
+    uint32_t pos = gpioPin % 32;
+    uint32_t tmpOut;
+
+    tmpOut = *pOut;
+
+    if (val > 0) {
+        tmpOut |= (1 << pos);
+    } else {
+        tmpOut &= (~(1 << pos));
+    }
+
+    *pOut = tmpOut;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read GPIO
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO value
+ *
+*******************************************************************************/
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
+{
+    uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2));
+    uint32_t pos = gpioPin % 32;
+
+    if ((*p) & (1 << pos)) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intMask: GPIO interrupt MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1);
+
+        if (intMask == MASK) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intClear: GPIO interrupt clear or unclear
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1);
+
+        if (intClear == SET) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GLB GPIO interrrupt status
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1);
+    }
+
+    return (tmpVal & (1 << gpioPin)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear GLB GPIO interrrupt status
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1);
+        tmpVal = tmpVal | (1 << gpioPin);
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mode
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intCtlMod: GPIO interrupt control mode
+ * @param  intTrgMod: GPIO interrupt trigger mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod)
+{
+    uint32_t tmpVal;
+    uint32_t tmpGpioPin;
+
+    CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
+    CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 ~ GPIO9 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
+        tmpGpioPin = gpioPin;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_20) {
+        /* GPIO10 ~ GPIO19 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal);
+    } else {
+        /* GPIO20 ~ GPIO29 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get GPIO interrupt control mode
+ *
+ * @param  gpioPin: GPIO pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t bitVal;
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 - GPIO9 */
+        bitVal = gpioPin - 0;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
+        /* GPIO10 - GPIO19 */
+        bitVal = gpioPin - 10;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else {
+        /* GPIO20 - GPIO29 */
+        bitVal = gpioPin - 20;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO INT0 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler callback install
+ *
+ * @param  gpioPin: GPIO pin type
+ * @param  cbFun: callback function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
+{
+    if (gpioPin < 32) {
+        glbGpioInt0CbfArra[gpioPin] = cbFun;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_INT0_IRQHandler(void)
+{
+    GLB_GPIO_Type gpioPin;
+    uint32_t timeOut = 0;
+
+    for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_22; gpioPin++) {
+        if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
+            GLB_GPIO_IntClear(gpioPin, SET);
+
+            /* timeout check */
+            timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+
+            do {
+                timeOut--;
+            } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
+
+            if (!timeOut) {
+                MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+            }
+
+            /* if timeOut==0, GPIO interrupt status not cleared */
+            GLB_GPIO_IntClear(gpioPin, RESET);
+
+            if (glbGpioInt0CbfArra[gpioPin] != NULL) {
+                /* Call the callback function */
+                glbGpioInt0CbfArra[gpioPin]();
+            }
+        }
+    }
+}
+#endif
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c
new file mode 100755
index 0000000000..9f64ea3b23
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_hbn.c
@@ -0,0 +1,1799 @@
+/**
+  ******************************************************************************
+  * @file    bl602_hbn.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_hbn.h"
+#include "bl602_glb.h"
+#include "bflb_xip_sflash.h"
+// #include "risc-v/Core/Include/clic.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Private_Macros
+ *  @{
+ */
+#define HBN_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group HBN_Private_Macros */
+
+/** @defgroup  HBN_Private_Types
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Types */
+
+/** @defgroup  HBN_Private_Variables
+ *  @{
+ */
+static intCallback_Type *hbnInt0CbfArra[3] = { NULL, NULL, NULL };
+static intCallback_Type *hbnInt1CbfArra[4] = { NULL, NULL, NULL, NULL };
+
+/*@} end of group HBN_Private_Variables */
+
+/** @defgroup  HBN_Global_Variables
+ *  @{
+ */
+
+/*@} end of group HBN_Global_Variables */
+
+/** @defgroup  HBN_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Fun_Declaration */
+
+/** @defgroup  HBN_Private_Functions
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Functions */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enter HBN
+ *
+ * @param  cfg: HBN APP Config
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Mode_Enter_Ext(HBN_APP_CFG_Type *cfg)
+{
+    uint32_t valLow = 0, valHigh = 0;
+    uint64_t val;
+
+    if (cfg->useXtal32k) {
+        HBN_32K_Sel(HBN_32K_XTAL);
+    } else {
+        HBN_32K_Sel(HBN_32K_RC);
+        HBN_Power_Off_Xtal_32K();
+    }
+
+    /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
+    HBN_Hw_Pu_Pd_Cfg(DISABLE);
+
+    HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));
+
+    if (cfg->gpioWakeupSrc != 0) {
+        HBN_Aon_Pad_IeSmt_Cfg(ENABLE);
+        HBN_GPIO_INT_Enable(cfg->gpioTrigType);
+    } else {
+        HBN_Aon_Pad_IeSmt_Cfg(DISABLE);
+    }
+
+    /* HBN RTC config and enable */
+    if (cfg->sleepTime != 0) {
+        HBN_Clear_RTC_Counter();
+        HBN_Get_RTC_Timer_Val(&valLow, &valHigh);
+        val = valLow + ((uint64_t)valHigh << 32);
+        val += cfg->sleepTime;
+        HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);
+        HBN_Enable_RTC_Counter();
+    }
+
+    HBN_Power_Down_Flash(cfg->flashCfg);
+    HBN_Set_Embedded_Flash_Pullup(ENABLE); /* E_ITEM_06 */
+
+    GLB_Set_System_CLK(GLB_PLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
+
+    HBN_Enable_Ext(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel);
+}
+
+/****************************************************************************/ /**
+ * @brief  power down and switch clock
+ *
+ * @param  flashCfg: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg)
+{
+    SPI_Flash_Cfg_Type bhFlashCfg;
+
+    if (flashCfg == NULL) {
+        SFlash_Cache_Flush();
+        XIP_SFlash_Read_Via_Cache_Need_Lock(BL602_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type));
+        SFlash_Cache_Flush();
+
+        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+        SFlash_Reset_Continue_Read(&bhFlashCfg);
+    } else {
+        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+        SFlash_Reset_Continue_Read(flashCfg);
+    }
+
+    SFlash_Powerdown();
+}
+#endif
+#if 0
+/****************************************************************************/ /**
+ * @brief  Enable HBN mode
+ *
+ * @param  aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to
+ *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param  ldoLevel: LDO volatge level
+ * @param  hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+    CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+    /* Setting from guide */
+    /* RAM Retion */
+    BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24);
+    /* AON GPIO IE */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    if (aGPIOIeCfg) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, 0);
+    }
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    /* HBN mode LDO level */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Select RC32M */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbnLevel) {
+        case HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_2:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_3:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT0_IRQn) = 0;
+    *(volatile uint8_t *)(CLIC_HART0_ADDR + CLIC_INTIP + HBN_OUT1_IRQn) = 0;
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        BL602_Delay_MS(1000);
+    }
+}
+#endif
+/****************************************************************************/ /**
+ * @brief  Reset HBN mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Reset HBN mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  reset HBN by software
+ *
+ * @param  npXtalType: NP clock type
+ * @param  bclkDiv: NP clock div
+ * @param  apXtalType: AP clock type
+ * @param  fclkDiv: AP clock div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv)
+{
+    uint32_t tmp[12];
+
+    tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmp[1] = BL_RD_REG(HBN_BASE, HBN_TIME_L);
+    tmp[2] = BL_RD_REG(HBN_BASE, HBN_TIME_H);
+    tmp[3] = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmp[4] = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmp[5] = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmp[6] = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmp[7] = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmp[9] = BL_RD_REG(HBN_BASE, HBN_RSV0);
+    tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1);
+    tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    /* DO HBN reset */
+    HBN_Reset();
+    /* HBN need 3 32k cyclce to recovery */
+    BL602_Delay_US(100);
+    /* Recover HBN value */
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]);
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]);
+    BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]);
+    BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]);
+    BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Disable HBN mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Config HBN PIR interrupt
+ *
+ * @param  pirIntCfg: HBN PIR interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg)
+{
+    uint32_t tmpVal;
+    uint32_t bit4 = 0;
+    uint32_t bit5 = 0;
+    uint32_t bitVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    /* low trigger interrupt */
+    if (pirIntCfg->lowIntEn == ENABLE) {
+        bit5 = 0;
+    } else {
+        bit5 = 1;
+    }
+
+    /* high trigger interrupt */
+    if (pirIntCfg->highIntEn == ENABLE) {
+        bit4 = 0;
+    } else {
+        bit4 = 1;
+    }
+
+    bitVal = bit4 | (bit5 << 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR low pass filter
+ *
+ * @param  lpf: HBN PIR low pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR high pass filter
+ *
+ * @param  hpf: HBN PIR high pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR threshold value
+ *
+ * @param  threshold: HBN PIR threshold value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((threshold <= 0x3FFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR threshold value
+ *
+ * @param  None
+ *
+ * @return HBN PIR threshold value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Threshold(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR interval value
+ *
+ * @param  interval: HBN PIR interval value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((interval <= 0xFFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR interval value
+ *
+ * @param  None
+ *
+ * @return HBN PIR interval value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Interval(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL);
+}
+
+/****************************************************************************/ /**
+ * @brief  get HBN bor out state
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_BOR_OUT_State(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_BOR_CFG), HBN_R_BOR_OUT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN bor config
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset
+ * @param  threshold: bor threshold
+ * @param  mode: bor work mode with por
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold));
+    CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 0);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, threshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, mode);
+    BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11aon voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11rt voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11soc voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11 all voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN select 32K
+ *
+ * @param  clkType: HBN 32k clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType));
+
+    HBN_Trim_RC32K();
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select uart clock source
+ *
+ * @param  clkSel: uart clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select xclk clock source
+ *
+ * @param  xClk: xclk clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    switch (xClk) {
+        case HBN_XCLK_CLK_RC32M:
+            tmpVal2 &= (~(1 << 0));
+            break;
+
+        case HBN_XCLK_CLK_XTAL:
+            tmpVal2 |= (1 << 0);
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+* @brief  get root clock selection
+*
+* @param  None
+*
+* @return root clock selection
+*
+*******************************************************************************/
+HBN_ROOT_CLK_Type ATTR_CLOCK_SECTION HBN_Get_Root_CLK_Sel(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+    switch (BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL)) {
+        case 0:
+            return HBN_ROOT_CLK_RC32M;
+        case 1:
+            return HBN_ROOT_CLK_XTAL;
+        case 2:
+            return HBN_ROOT_CLK_PLL;
+        case 3:
+            return HBN_ROOT_CLK_PLL;
+        default:
+            return HBN_ROOT_CLK_RC32M;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Select root clk source
+ *
+ * @param  rootClk: root clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    switch (rootClk) {
+        case HBN_ROOT_CLK_RC32M:
+            tmpVal2 = 0x0;
+            break;
+
+        case HBN_ROOT_CLK_XTAL:
+            tmpVal2 = 0x1;
+            break;
+
+        case HBN_ROOT_CLK_PLL:
+            tmpVal2 |= (1 << 1);
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM sleep mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_HRAM_slp(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM retension mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_HRAM_Ret(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    /* Delay >1s */
+    BL602_Delay_US(1100);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    /* Delay >800us */
+    BL602_Delay_US(880);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off RC3K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void)
+{
+    Efuse_Ana_RC32K_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32K_Trim(&trim);
+
+    if (trim.trimRc32kExtCodeEn) {
+        if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) {
+            tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN);
+            BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+            BL602_Delay_US(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get HBN status flag
+ *
+ * @param  None
+ *
+ * @return HBN status flag value
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Status_Flag(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV0);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN status flag
+ *
+ * @param  flag: Status Flag
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV0, flag);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN wakeup address
+ *
+ * @param  None
+ *
+ * @return HBN wakeup address
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Wakeup_Addr(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN wakeup address
+ *
+ * @param  addr: HBN wakeup address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV1, addr);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set RTC timer configuration
+ *
+ * @param  delay: RTC interrupt delay 32 clocks
+ * @param  compValLow: RTC interrupt commpare value low 32 bits
+ * @param  compValHigh: RTC interrupt commpare value high 32 bits
+ * @param  compMode: RTC interrupt commpare
+ *                   mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay));
+
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set interrupt delay option */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay);
+    /* Set RTC compare mode */
+    tmpVal |= (compMode << 1);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get RTC async timer count value
+ *
+ * @param  valLow: RTC count value pointer for low 32 bits
+ * @param  valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+    uint32_t tmpVal;
+
+    /* Tigger RTC val read */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+
+    /* Read RTC val */
+    *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
+    *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get RTC timer count value
+ *
+ * @param  valLow: RTC count value pointer for low 32 bits
+ * @param  valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+    uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
+    uint64_t val, val1;
+
+    do {
+        HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh);
+        val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow);
+        HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1);
+        val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1);
+    } while (val1 < val);
+
+    *valLow = tmpValLow1;
+    *valHigh = tmpValHigh1;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_INT(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable GPIO interrupt
+ *
+ * @param  gpioIntTrigType: HBN GPIO interrupt trigger type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable GPIO interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT);
+
+    if (tmpVal & (1 << irqType)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get pin wakeup mode value
+ *
+ * @param  None
+ *
+ * @return HBN pin wakeup mode value
+ *
+*******************************************************************************/
+uint8_t HBN_Get_Pin_Wakeup_Mode(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE);
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_INT_TYPE(irqType));
+
+    /* set clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal |= (1 << irqType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    /* unset clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal &= (~(1 << irqType));
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN hardware pullup or pulldown configuration
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN Config AON pad input and SMT
+ *
+ * @param  padCfg: AON pad config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, padCfg);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN wakeup pin mask configuration
+ *
+ * @param  maskVal: mask value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP0 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+    tmpVal2 = tmpVal2 | (1 << edge);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP0 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+    tmpVal2 = tmpVal2 & (~(1 << edge));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP1 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+    tmpVal2 = tmpVal2 | (1 << edge);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP1 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+    tmpVal2 = tmpVal2 & (~(1 << edge));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable BOR interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_BOR_IRQ(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable BOR interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_BOR_IRQ(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out0 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out0_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out0 install interrupt callback
+ *
+ * @param  intType: HBN out0 interrupt type
+ * @param  cbFun: HBN out0 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType));
+
+    hbnInt0CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out1 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out1_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out1 install interrupt callback
+ *
+ * @param  intType: HBN out1 interrupt type
+ * @param  cbFun: HBN out1 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType));
+
+    hbnInt1CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN GPIO7 debbug pull config
+ *
+ * @param  pupdEn: Enable or disable GPIO7 pull down and pull up
+ * @param  iesmtEn: Enable or disable GPIO7 IE and SMT
+ * @param  dlyEn: Enable or disable GPIO7 wakeup delay function
+ * @param  dlySec: GPIO7 wakeup delay sec 1 to 7
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, iesmtEn);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set Embedded Flash Pullup enabe or disable
+ *
+ * @param  enable: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+
+    enable = (!enable);
+    tmpVal = ((tmpVal & 0xfffffffe) | (enable & 0x01));
+
+    BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set Embedded Flash Pullup enabe or disable
+ *
+ * @param  cfg: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg)
+{
+    uint32_t tmpVal = 0;
+
+    if (cfg->enableBorInt) {
+        HBN_Enable_BOR_IRQ();
+    } else {
+        HBN_Disable_BOR_IRQ();
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, cfg->borThreshold);
+
+    if (cfg->enablePorInBor) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOR_SEL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOR_SEL);
+    }
+
+    if (cfg->enableBor) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT0 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void)
+{
+    /* GPIO7 GPIO8 and RTC */
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO7)) {
+        /* gpio7 sync/async mode */
+        HBN_Clear_IRQ(HBN_INT_GPIO7);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO7] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO7]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO8)) {
+        /* gpio8 sync/async mode */
+        HBN_Clear_IRQ(HBN_INT_GPIO8);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO8] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO8]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {
+        HBN_Clear_IRQ(HBN_INT_RTC);
+        HBN_Clear_RTC_INT();
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_RTC]();
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT1 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT1_IRQHandler(void)
+{
+    /* PIR */
+    if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
+        HBN_Clear_IRQ(HBN_INT_PIR);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_PIR]();
+        }
+    }
+
+    /* BOR */
+    if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
+        HBN_Clear_IRQ(HBN_INT_BOR);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_BOR]();
+        }
+    }
+
+    /* ACOMP0 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP0);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0]();
+        }
+    }
+
+    /* ACOMP1 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP1);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1]();
+        }
+    }
+}
+#endif
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_l1c.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_l1c.c
new file mode 100755
index 0000000000..b9e065a584
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_l1c.c
@@ -0,0 +1,428 @@
+/**
+  ******************************************************************************
+  * @file    bl602_l1c.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_l1c.h"
+#include "bl602_common.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  L1C
+ *  @{
+ */
+
+/** @defgroup  L1C_Private_Macros
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Macros */
+
+/** @defgroup  L1C_Private_Types
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Types */
+
+/** @defgroup  L1C_Private_Variables
+ *  @{
+ */
+static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL };
+static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL };
+
+/*@} end of group L1C_Private_Variables */
+
+/** @defgroup  L1C_Global_Variables
+ *  @{
+ */
+
+/*@} end of group L1C_Global_Variables */
+
+/** @defgroup  L1C_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Fun_Declaration */
+
+/** @defgroup  L1C_Private_Functions
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Functions */
+
+/** @defgroup  L1C_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  wrap set
+ *
+ * @param  wrap: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
+{
+    uint32_t tmpVal = 0;
+    uint8_t cacheEn = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (wrap == ENABLE) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS);
+    } else {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  cache way disable set
+ *
+ * @param  disableVal: cache way disable value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal)
+{
+    uint32_t tmpVal = 0;
+    uint8_t cacheEn = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set for ROM 2T access if CPU freq >120MHz
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX init
+ *
+ * @param  l1cBmxCfg: L1C BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF);
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler);
+    Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX address monitor enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX address monitor disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX bus error response enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_BusErrResponse_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX bus error response disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_BusErrResponse_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get L1C BMX error status
+ *
+ * @param  errType: L1C BMX error status type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType));
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+
+    if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) {
+        return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET;
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get L1C BMX error address
+ *
+ * @param  None
+ *
+ * @return NP L1C BMX error address
+ *
+*******************************************************************************/
+uint32_t L1C_BMX_Get_Err_Addr(void)
+{
+    return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR);
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX error interrupt callback install
+ *
+ * @param  intType: L1C BMX error interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType));
+
+    l1cBmxErrIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX ERR interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_ERR_IRQHandler(void)
+{
+    L1C_BMX_ERR_INT_Type intType;
+
+    for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) {
+        if (l1cBmxErrIntCbfArra[intType] != NULL) {
+            l1cBmxErrIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        MSG("L1C_BMX_ERR_IRQHandler\r\n");
+        BL602_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX timeout interrupt callback install
+ *
+ * @param  intType: L1C BMX timeout interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType));
+
+    l1cBmxToIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX Time Out interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_TO_IRQHandler(void)
+{
+    L1C_BMX_TO_INT_Type intType;
+
+    for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) {
+        if (l1cBmxToIntCbfArra[intType] != NULL) {
+            l1cBmxToIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        MSG("L1C_BMX_TO_IRQHandler\r\n");
+        BL602_Delay_MS(1000);
+    }
+}
+#endif
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pds.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pds.c
new file mode 100755
index 0000000000..dd3d40fe05
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_pds.c
@@ -0,0 +1,841 @@
+/**
+  ******************************************************************************
+  * @file    bl602_pds.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602.h"
+#include "bl602_pds.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Private_Macros
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Macros */
+
+/** @defgroup  PDS_Private_Types
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Types */
+
+/** @defgroup  PDS_Private_Variables
+ *  @{
+ */
+static intCallback_Type *pdsIntCbfArra[4][1] = { { NULL }, { NULL }, { NULL }, { NULL } };
+
+/*@} end of group PDS_Private_Variables */
+
+/** @defgroup  PDS_Global_Variables
+ *  @{
+ */
+
+/*@} end of group PDS_Global_Variables */
+
+/** @defgroup  PDS_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Fun_Declaration */
+
+/** @defgroup  PDS_Private_Functions
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Functions */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  PDS software reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = *(uint32_t *)0x40000014;
+    tmpVal = tmpVal | (1 << 14);
+    *(uint32_t *)0x40000014 = tmpVal;
+
+    tmpVal = *(uint32_t *)0x40000014;
+    tmpVal = tmpVal & ~(1 << 14);
+    *(uint32_t *)0x40000014 = tmpVal;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable power down sleep
+ *
+ * @param  cfg: power down sleep configuration 1
+ * @param  cfg4: power down sleep configuration 2
+ * @param  pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+// #ifndef BFLB_USE_ROM_DRIVER
+// __WEAK
+BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
+{
+    uint32_t tmpVal = 0;
+
+    /* PDS sleep time 0 <=> sleep forever */
+    /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
+    /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
+    if (!pdsSleepCnt) {
+        cfg->sleepForever = 1;
+    } else if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
+        return ERROR;
+    } else {
+        BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
+    }
+
+    /* PDS_CTL4 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
+
+    /* PDS_CTL config */
+    if (cfg->pdsStart) {
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
+    } else {
+        BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
+    }
+
+    return SUCCESS;
+}
+// #endif
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  cfg2: power down sleep force configuration 1
+ * @param  cfg3: power down sleep force configuration 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3)
+{
+    /* PDS_CTL2 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);
+
+    /* PDS_CTL3 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power down sleep ram configure
+ *
+ * @param  ramCfg: power down sleep force ram configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
+{
+    uint32_t tmpVal = 0;
+
+    if (NULL == ramCfg) {
+        return SUCCESS;
+    }
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL);
+    /* enter bist mode (make ram idle/slp) */
+    //tmpVal = tmpVal&~0x1F;
+    //tmpVal = tmpVal|0x18;
+    /* enter bist mode (make ram ret) */
+    tmpVal = tmpVal | (0x1 << 3);
+    BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal);
+
+    /* PDS_RAM1 config */
+    BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MBIST_CTL);
+    /* exit bist mode (make ram idle/slp) */
+    //tmpVal = tmpVal&~0x1F;
+    /* exit bist mode (make ram ret) */
+    tmpVal = tmpVal & ~(0x1 << 3);
+    BL_WR_REG(GLB_BASE, GLB_MBIST_CTL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  defaultLvCfg: power down sleep default level configuration
+ * @param  ramCfg: ram configuration
+ * @param  pdsSleepCnt: power down sleep time count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+// #ifndef BFLB_USE_ROM_DRIVER
+// __WEAK
+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt)
+{
+    /* RAM config need fix after ECO */
+    PDS_RAM_Config(ramCfg);
+    PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3));
+    PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
+
+    return SUCCESS;
+}
+// #endif
+
+/****************************************************************************/ /**
+ * @brief  power down sleep int mask
+ *
+ * @param  intType: PDS int type
+ * @param  intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+
+    if (intMask != UNMASK) {
+        tmpVal = tmpVal | (1 << (intType + PDS_INT_MASK_BIT_OFFSET));
+    } else {
+        tmpVal = tmpVal & ~(1 << (intType + PDS_INT_MASK_BIT_OFFSET));
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep int status
+ *
+ * @param  intType: PDS int type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
+{
+    return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << intType)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  clear power down sleep int status
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntClear(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep PLL status
+ *
+ * @param  None
+ *
+ * @return PDS PLL status
+ *
+*******************************************************************************/
+PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void)
+{
+    return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep RF status
+ *
+ * @param  None
+ *
+ * @return PDS RF status
+ *
+*******************************************************************************/
+PDS_RF_STS_Type PDS_Get_PdsRfStstus(void)
+{
+    return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep status
+ *
+ * @param  None
+ *
+ * @return PDS status
+ *
+*******************************************************************************/
+PDS_STS_Type PDS_Get_PdsStstus(void)
+{
+    return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  PDS wakeup IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Install PDS interrupt callback function
+ *
+ * @param  intType: PDS int type
+ * @param  cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)
+{
+    pdsIntCbfArra[intType][0] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
+{
+    Efuse_Ana_RC32M_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32M_Trim(&trim);
+
+    if (trim.trimRc32mExtCodeEn) {
+        if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {
+            tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
+            BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
+            BL602_Delay_US(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select RC32M as PLL ref source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_REFCLK_SEL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select XTAL as PLL ref source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_REFCLK_SEL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on PLL
+ *
+ * @param  xtalType: xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType));
+
+    /**************************/
+    /* select PLL XTAL source */
+    /**************************/
+
+    if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) {
+        PDS_Trim_RC32M();
+        PDS_Select_RC32M_As_PLL_Ref();
+    } else {
+        PDS_Select_XTAL_As_PLL_Ref();
+    }
+
+    /*******************************************/
+    /* PLL power down first, not indispensable */
+    /*******************************************/
+    /* power off PLL first, this step is not indispensable */
+    PDS_Power_Off_PLL();
+
+    /********************/
+    /* PLL param config */
+    /********************/
+
+    /* clkpll_icp_1u */
+    /* clkpll_icp_5u */
+    /* clkpll_int_frac_sw */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP);
+
+    if (xtalType == PDS_PLL_XTAL_26M) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal);
+
+    /* clkpll_c3 */
+    /* clkpll_cz */
+    /* clkpll_rz */
+    /* clkpll_r4 */
+    /* clkpll_r4_short */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ);
+
+    if (xtalType == PDS_PLL_XTAL_26M) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 5);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 0);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal);
+
+    /* clkpll_refdiv_ratio */
+    /* clkpll_postdiv */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    /* clkpll_sdmin */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+
+    switch (xtalType) {
+        case PDS_PLL_XTAL_NONE:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
+            break;
+
+        case PDS_PLL_XTAL_24M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x500000);
+            break;
+
+        case PDS_PLL_XTAL_32M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
+            break;
+
+        case PDS_PLL_XTAL_38P4M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x320000);
+            break;
+
+        case PDS_PLL_XTAL_40M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x300000);
+            break;
+
+        case PDS_PLL_XTAL_26M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D39D);
+            break;
+
+        case PDS_PLL_XTAL_RC32M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
+            break;
+
+        default:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
+            break;
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
+
+    /* clkpll_sel_fb_clk */
+    /* clkpll_sel_sample_clk can be 0/1, default is 1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal);
+
+    /*************************/
+    /* PLL power up sequence */
+    /*************************/
+
+    /* pu_clkpll_sfreg=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL602_Delay_US(5);
+
+    /* pu_clkpll=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /* clkpll_pu_cp=1 */
+    /* clkpll_pu_pfd=1 */
+    /* clkpll_pu_fbdv=1 */
+    /* clkpll_pu_postdiv=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL602_Delay_US(5);
+
+    /* clkpll_sdm_reset=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL602_Delay_US(1);
+    /* clkpll_reset_fbdv=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL602_Delay_US(2);
+    /* clkpll_reset_fbdv=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL602_Delay_US(1);
+    /* clkpll_sdm_reset=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Fix XTAL26M Setting
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Fix_Xtal_Settig(void)
+{
+    uint32_t tmpVal;
+
+    /* Fix 26M xtal clkpll_sdmin */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+
+    if (0x49D39D == BL_GET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN)) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x49D89E);
+        BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/** PLL output config **/
+/*
+[8]    1'h0    r/w    clkpll_en_32m
+[7]    1'h0    r/w    clkpll_en_48m
+[6]    1'h0    r/w    clkpll_en_80m
+[5]    1'h0    r/w    clkpll_en_96m
+[4]    1'h0    r/w    clkpll_en_120m
+[3]    1'h0    r/w    clkpll_en_160m
+[2]    1'h0    r/w    clkpll_en_192m
+[1]    1'h0    r/w    clkpll_en_240m
+[0]    1'h0    r/w    clkpll_en_480m
+*/
+
+/****************************************************************************/ /**
+ * @brief  Enable all PLL clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal |= 0x1FF;
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable all PLL clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal &= (~0x1FF);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable PLL clock
+ *
+ * @param  pllClk: PLL clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal |= (1 << pllClk);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable PLL clock
+ *
+ * @param  pllClk: PLL clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal &= (~(1 << pllClk));
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off PLL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* pu_clkpll_sfreg=0 */
+    /* pu_clkpll=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /* clkpll_pu_cp=0 */
+    /* clkpll_pu_pfd=0 */
+    /* clkpll_pu_fbdv=0 */
+    /* clkpll_pu_postdiv=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power down sleep wake up interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void)
+{
+    for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
+        if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) {
+            pdsIntCbfArra[intType][0]();
+        }
+    }
+
+    PDS_IntClear();
+}
+#endif
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romapi.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romapi.c
new file mode 100755
index 0000000000..5680504c8e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romapi.c
@@ -0,0 +1,1035 @@
+#include "bl602_romdriver.h"
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
+{
+    return RomDriver_AON_Power_On_MBG();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
+{
+    return RomDriver_AON_Power_Off_MBG();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
+{
+    return RomDriver_AON_Power_On_XTAL();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+    return RomDriver_AON_Set_Xtal_CapCode(capIn, capOut);
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
+{
+    return RomDriver_AON_Get_Xtal_CapCode();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
+{
+    return RomDriver_AON_Power_Off_XTAL();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
+{
+    return RomDriver_AON_Power_On_BG();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
+{
+    return RomDriver_AON_Power_Off_BG();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
+{
+    return RomDriver_AON_Power_On_LDO11_SOC();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
+{
+    return RomDriver_AON_Power_Off_LDO11_SOC();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
+{
+    return RomDriver_AON_Power_On_LDO15_RF();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
+{
+    return RomDriver_AON_Power_Off_LDO15_RF();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
+{
+    return RomDriver_AON_Power_On_SFReg();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
+{
+    return RomDriver_AON_Power_Off_SFReg();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
+{
+    return RomDriver_AON_LowPower_Enter_PDS0();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
+{
+    return RomDriver_AON_LowPower_Exit_PDS0();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    return RomDriver_ASM_Delay_Us(core, cnt);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION BL602_Delay_US(uint32_t cnt)
+{
+    return RomDriver_BL602_Delay_US(cnt);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION BL602_Delay_MS(uint32_t cnt)
+{
+    return RomDriver_BL602_Delay_MS(cnt);
+}
+
+__ALWAYS_INLINE
+void *ATTR_TCM_SECTION BL602_MemCpy(void *dst, const void *src, uint32_t n)
+{
+    return RomDriver_BL602_MemCpy(dst, src, n);
+}
+
+__ALWAYS_INLINE
+uint32_t *ATTR_TCM_SECTION BL602_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n)
+{
+    return RomDriver_BL602_MemCpy4(dst, src, n);
+}
+
+__ALWAYS_INLINE
+void *ATTR_TCM_SECTION BL602_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n)
+{
+    return RomDriver_BL602_MemCpy_Fast(pdst, psrc, n);
+}
+
+__ALWAYS_INLINE
+void *ATTR_TCM_SECTION BL602_MemSet(void *s, uint8_t c, uint32_t n)
+{
+    return RomDriver_BL602_MemSet(s, c, n);
+}
+
+__ALWAYS_INLINE
+uint32_t *ATTR_TCM_SECTION BL602_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n)
+{
+    return RomDriver_BL602_MemSet4(dst, val, n);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION BL602_MemCmp(const void *s1, const void *s2, uint32_t n)
+{
+    return RomDriver_BL602_MemCmp(s1, s2, n);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION EF_Ctrl_Sw_AHB_Clk_0(void)
+{
+    return RomDriver_EF_Ctrl_Sw_AHB_Clk_0();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION EF_Ctrl_Program_Efuse_0(void)
+{
+    return RomDriver_EF_Ctrl_Program_Efuse_0();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION EF_Ctrl_Load_Efuse_R0(void)
+{
+    return RomDriver_EF_Ctrl_Load_Efuse_R0();
+}
+
+__ALWAYS_INLINE
+BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_Busy(void)
+{
+    return RomDriver_EF_Ctrl_Busy();
+}
+
+__ALWAYS_INLINE
+BL_Sts_Type ATTR_TCM_SECTION EF_Ctrl_AutoLoad_Done(void)
+{
+    return RomDriver_EF_Ctrl_AutoLoad_Done();
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_CLOCK_SECTION EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len)
+{
+    return RomDriver_EF_Ctrl_Get_Trim_Parity(val, len);
+}
+
+__ALWAYS_INLINE
+void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim)
+{
+    return RomDriver_EF_Ctrl_Read_RC32M_Trim(trim);
+}
+
+__ALWAYS_INLINE
+void ATTR_CLOCK_SECTION EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim)
+{
+    return RomDriver_EF_Ctrl_Read_RC32K_Trim(trim);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION EF_Ctrl_Clear(uint32_t index, uint32_t len)
+{
+    return RomDriver_EF_Ctrl_Clear(index, len);
+}
+
+__ALWAYS_INLINE
+GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void)
+{
+    return RomDriver_GLB_Get_Root_CLK_Sel();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
+{
+    return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv);
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void)
+{
+    return RomDriver_GLB_Get_BCLK_Div();
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void)
+{
+    return RomDriver_GLB_Get_HCLK_Div();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_PLL_XTAL_Type xtalType)
+{
+    return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_PLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq)
+{
+    return RomDriver_GLB_Set_System_CLK(xtalType, clkFreq);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void)
+{
+    return RomDriver_System_Core_Clock_Update_From_RC32M();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+    return RomDriver_GLB_Set_SF_CLK(enable, clkSel, div);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)
+{
+    return RomDriver_GLB_Set_PKA_CLK_Sel(clkSel);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)
+{
+    return RomDriver_GLB_SW_System_Reset();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)
+{
+    return RomDriver_GLB_SW_CPU_Reset();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)
+{
+    return RomDriver_GLB_SW_POR_Reset();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void)
+{
+    return RomDriver_GLB_Select_Internal_Flash();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void)
+{
+    return RomDriver_GLB_Select_External_Flash();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void)
+{
+    return RomDriver_GLB_Deswap_Flash_Pin();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void)
+{
+    return RomDriver_GLB_Swap_Flash_Pin();
+}
+
+#if 0
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+	return RomDriver_GLB_GPIO_Init(cfg);
+}
+#endif
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_Set_HZ(gpioPin);
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_Get_Fun(gpioPin);
+}
+
+#if 0
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
+{
+	return RomDriver_HBN_Mode_Enter(cfg);
+}
+#endif
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_HBN_Power_Down_Flash(flash_cfg);
+}
+
+#if 0
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    return RomDriver_HBN_Enable(aGPIOIeCfg, ldoLevel, hbnLevel);
+}
+#endif
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void)
+{
+    return RomDriver_HBN_Reset();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    return RomDriver_HBN_Set_Ldo11_Aon_Vout(ldoLevel);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    return RomDriver_HBN_Set_Ldo11_Rt_Vout(ldoLevel);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    return RomDriver_HBN_Set_Ldo11_Soc_Vout(ldoLevel);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType)
+{
+    return RomDriver_HBN_32K_Sel(clkType);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk)
+{
+    return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)
+{
+    return RomDriver_HBN_Power_On_Xtal_32K();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)
+{
+    return RomDriver_HBN_Power_Off_Xtal_32K();
+}
+
+#if 0
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void)
+{
+	return RomDriver_HBN_Power_On_RC32K();
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void)
+{
+	return RomDriver_HBN_Power_Off_RC32K();
+}
+#endif
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void)
+{
+    return RomDriver_HBN_Trim_RC32K();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable)
+{
+    return RomDriver_HBN_Hw_Pu_Pd_Cfg(enable);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal)
+{
+    return RomDriver_HBN_Pin_WakeUp_Mask(maskVal);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO7_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type iesmtEn, BL_Fun_Type dlyEn, uint8_t dlySec)
+{
+    return RomDriver_HBN_GPIO7_Dbg_Pull_Cfg(pupdEn, iesmtEn, dlyEn, dlySec);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Embedded_Flash_Pullup(uint8_t enable)
+{
+    return RomDriver_HBN_Set_Embedded_Flash_Pullup(enable);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
+{
+    return RomDriver_L1C_Set_Wrap(wrap);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal)
+{
+    return RomDriver_L1C_Set_Way_Disable(disableVal);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
+{
+    return RomDriver_L1C_IROM_2T_Access_Set(enable);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION PDS_Reset(void)
+{
+    return RomDriver_PDS_Reset();
+}
+
+#if 0
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
+{
+    return RomDriver_PDS_Enable(cfg, cfg4, pdsSleepCnt);
+}
+#endif
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3)
+{
+    return RomDriver_PDS_Force_Config(cfg2, cfg3);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
+{
+    return RomDriver_PDS_RAM_Config(ramCfg);
+}
+
+#if 0
+__ALWAYS_INLINE
+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_RAM_CFG_Type *ramCfg, uint32_t pdsSleepCnt)
+{
+    return RomDriver_PDS_Default_Level_Config(defaultLvCfg, ramCfg, pdsSleepCnt);
+}
+#endif
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
+{
+    return RomDriver_PDS_Trim_RC32M();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void)
+{
+    return RomDriver_PDS_Select_RC32M_As_PLL_Ref();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void)
+{
+    return RomDriver_PDS_Select_XTAL_As_PLL_Ref();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
+{
+    return RomDriver_PDS_Power_On_PLL(xtalType);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void)
+{
+    return RomDriver_PDS_Enable_PLL_All_Clks();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void)
+{
+    return RomDriver_PDS_Disable_PLL_All_Clks();
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    return RomDriver_PDS_Enable_PLL_Clk(pllClk);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    return RomDriver_PDS_Disable_PLL_Clk(pllClk);
+}
+
+__ALWAYS_INLINE
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
+{
+    return RomDriver_PDS_Power_Off_PLL();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION SEC_Eng_Turn_On_Sec_Ring(void)
+{
+    return RomDriver_SEC_Eng_Turn_On_Sec_Ring();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION SEC_Eng_Turn_Off_Sec_Ring(void)
+{
+    return RomDriver_SEC_Eng_Turn_Off_Sec_Ring();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg)
+{
+    return RomDriver_SFlash_Init(p_sf_ctrl_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_setspimode(uint8_t mode)
+{
+    return RomDriver_SFlash_SetSPIMode(mode);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Read_Reg(flash_cfg, reg_index, reg_value, reg_len);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Write_Reg(flash_cfg, reg_index, reg_value, reg_len);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_busy(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Busy(flash_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Write_Enable(flash_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Qspi_Enable(flash_cfg);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Chip_Erase(flash_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sec_num)
+{
+    return RomDriver_SFlash_Sector_Erase(flash_cfg, sec_num);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
+{
+    return RomDriver_SFlash_Blk32_Erase(flash_cfg, blk_num);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
+{
+    return RomDriver_SFlash_Blk64_Erase(flash_cfg, blk_num);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t startaddr, uint32_t endaddr)
+{
+    return RomDriver_SFlash_Erase(flash_cfg, startaddr, endaddr);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_SFlash_Program(flash_cfg, io_mode, addr, data, len);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_get_uniqueid(uint8_t *data, uint8_t idLen)
+{
+    return RomDriver_SFlash_GetUniqueId(data, idLen);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data)
+{
+    return RomDriver_SFlash_GetJedecId(flash_cfg, data);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr)
+{
+    return RomDriver_SFlash_GetDeviceId(data);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_powerdown(void)
+{
+    return RomDriver_SFlash_Powerdown();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Releae_Powerdown(flash_cfg);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_SetBurstWrap(flash_cfg);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_DisableBurstWrap(flash_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Software_Reset(flash_cfg);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Reset_Continue_Read(flash_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_set_idbus_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank)
+{
+    return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg, io_mode, cont_read, addr, len);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank)
+{
+    return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg, io_mode, cont_read);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_cache_enable_set(uint8_t way_disable)
+{
+    return RomDriver_SFlash_Cache_Enable_Set(way_disable);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_cache_flush(void)
+{
+    return RomDriver_SFlash_Cache_Flush();
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_cache_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t way_disable)
+{
+    return RomDriver_SFlash_Cache_Read_Enable(flash_cfg, io_mode, cont_read, way_disable);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_l1c_hit_count_get(uint32_t *hit_count_low, uint32_t *hit_count_high)
+{
+    return RomDriver_SFlash_Cache_Hit_Count_Get(hit_count_low, hit_count_high);
+}
+
+__ALWAYS_INLINE
+uint32_t ATTR_TCM_SECTION bflb_l1c_miss_count_get(void)
+{
+    return RomDriver_SFlash_Cache_Miss_Count_Get();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sflash_cache_read_disable(void)
+{
+    return RomDriver_SFlash_Cache_Read_Disable();
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_SFlash_Read(flash_cfg, io_mode, cont_read, addr, data, len);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg, read_reg_cmd, reg_value, reg_len);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg, write_reg_cmd, reg_value, reg_len);
+}
+
+#if 0
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flashContRead)
+{
+	return RomDriver_SFlash_Restore_From_Powerdown(p_flash_cfg, flashContRead);
+}
+#endif
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+    return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_cfg_init_internal_flash_gpio(void)
+{
+    return RomDriver_SF_Cfg_Init_Internal_Flash_Gpio();
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+    return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_cfg_restore_gpio17_fun(uint8_t fun)
+{
+    return RomDriver_SF_Cfg_Restore_GPIO17_Fun(fun);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+    return RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg, restore_default);
+}
+
+__ALWAYS_INLINE
+uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    uint8_t auto_scan = 0;
+    uint8_t flash_pin = 0;
+    auto_scan = ((flash_pin_cfg >> 7) & 1);
+    flash_pin = (flash_pin_cfg & 0x7F);
+    return RomDriver_SF_Cfg_Flash_Identify(call_from_flash, auto_scan, flash_pin, restore_default, p_flash_cfg);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg)
+{
+    return RomDriver_SF_Ctrl_Enable(cfg);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_select_pad(uint8_t sel)
+{
+    return RomDriver_SF_Ctrl_Select_Pad(sel);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_owner(uint8_t owner)
+{
+    return RomDriver_SF_Ctrl_Set_Owner(owner);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_disable(void)
+{
+    return RomDriver_SF_Ctrl_Disable();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_be(void)
+{
+    return RomDriver_SF_Ctrl_AES_Enable_BE();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable_le(void)
+{
+    return RomDriver_SF_Ctrl_AES_Enable_LE();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hw_key, uint32_t start_addr, uint32_t end_addr, uint8_t locked)
+{
+    return RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hw_key, start_addr, end_addr, locked);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t keyType)
+{
+    return RomDriver_SF_Ctrl_AES_Set_Key(region, key, keyType);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t keyType)
+{
+    return RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, keyType);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset)
+{
+    return RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addr_offset);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset)
+{
+    return RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addr_offset);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_enable(void)
+{
+    return RomDriver_SF_Ctrl_AES_Enable();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_aes_disable(void)
+{
+    return RomDriver_SF_Ctrl_AES_Disable();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank)
+{
+    return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset);
+}
+
+__ALWAYS_INLINE
+uint32_t ATTR_TCM_SECTION bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank)
+{
+    return RomDriver_SF_Ctrl_Get_Flash_Image_Offset();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_select_clock(uint8_t sahb_type)
+{
+    return RomDriver_SF_Ctrl_Select_Clock(sahb_type);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg)
+{
+    return RomDriver_SF_Ctrl_SendCmd(cfg);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+    return RomDriver_SF_Ctrl_Icache_Set(cfg, cmd_valid);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_icache2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+    return RomDriver_SF_Ctrl_Icache2_Set(cfg, cmd_valid);
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_busy_state(void)
+{
+    return RomDriver_SF_Ctrl_GetBusyState();
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_is_aes_enable(void)
+{
+    return RomDriver_SF_Ctrl_Is_AES_Enable();
+}
+
+__ALWAYS_INLINE
+uint8_t ATTR_TCM_SECTION bflb_sf_ctrl_get_clock_delay(void)
+{
+    return RomDriver_SF_Ctrl_Get_Clock_Delay();
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_sf_ctrl_set_clock_delay(uint8_t delay)
+{
+    return RomDriver_SF_Ctrl_Set_Clock_Delay(delay);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_State_Save(p_flash_cfg, offset);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_State_Restore(p_flash_cfg, offset);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_Erase_Need_Lock(p_flash_cfg, startaddr, startaddr+len-1);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_Write_Need_Lock(p_flash_cfg, addr, data, len);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_Read_Need_Lock(p_flash_cfg, addr, data, len);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(p_flash_cfg, data);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(p_flash_cfg, data);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t idLen, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(p_flash_cfg, data, idLen);
+}
+
+__ALWAYS_INLINE
+int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable)
+{
+    return RomDriver_XIP_SFlash_Opt_Enter(aes_enable);
+}
+
+__ALWAYS_INLINE
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable)
+{
+    return RomDriver_XIP_SFlash_Opt_Exit(aes_enable);
+}
+
+__ALWAYS_INLINE
+uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len)
+{
+    return RomDriver_BFLB_Soft_CRC32(dataIn, len);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romdriver.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romdriver.c
new file mode 100755
index 0000000000..e14b47724b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_romdriver.c
@@ -0,0 +1,291 @@
+/**
+  ******************************************************************************
+  * @file    bl602_romdriver.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_romdriver.h"
+#include 
+
+/** @addtogroup  BL602_Periph_Driver
+ *  @{
+ */
+
+/** @defgroup ROMDRIVER
+ *  @brief ROMDRIVER common functions
+ *  @{
+ */
+
+/** @defgroup ROMDRIVER_Private_Type
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Type*/
+
+/** @defgroup ROMDRIVER_Private_Defines
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Defines */
+
+/** @defgroup ROMDRIVER_Private_Variables
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Variables */
+
+/** @defgroup ROMDRIVER_Global_Variables
+ *  @{
+ */
+
+uint32_t const romDriverTable[] = {
+    0x06020002,
+    0x00000000,
+    0x00000000,
+    0x00000000,
+
+    [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG,
+    [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG,
+    [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL,
+    [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode,
+    [ROM_API_INDEX_AON_Get_Xtal_CapCode] = (uint32_t)AON_Get_Xtal_CapCode,
+    [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL,
+    [ROM_API_INDEX_AON_Power_On_BG] = (uint32_t)AON_Power_On_BG,
+    [ROM_API_INDEX_AON_Power_Off_BG] = (uint32_t)AON_Power_Off_BG,
+    [ROM_API_INDEX_AON_Power_On_LDO11_SOC] = (uint32_t)AON_Power_On_LDO11_SOC,
+    [ROM_API_INDEX_AON_Power_Off_LDO11_SOC] = (uint32_t)AON_Power_Off_LDO11_SOC,
+    [ROM_API_INDEX_AON_Power_On_LDO15_RF] = (uint32_t)AON_Power_On_LDO15_RF,
+    [ROM_API_INDEX_AON_Power_Off_LDO15_RF] = (uint32_t)AON_Power_Off_LDO15_RF,
+    [ROM_API_INDEX_AON_Power_On_SFReg] = (uint32_t)AON_Power_On_SFReg,
+    [ROM_API_INDEX_AON_Power_Off_SFReg] = (uint32_t)AON_Power_Off_SFReg,
+    [ROM_API_INDEX_AON_LowPower_Enter_PDS0] = (uint32_t)AON_LowPower_Enter_PDS0,
+    [ROM_API_INDEX_AON_LowPower_Exit_PDS0] = (uint32_t)AON_LowPower_Exit_PDS0,
+
+    [ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us,
+
+    [ROM_API_INDEX_BL602_Delay_US] = (uint32_t)BL602_Delay_US,
+    [ROM_API_INDEX_BL602_Delay_MS] = (uint32_t)BL602_Delay_MS,
+    [ROM_API_INDEX_BL602_MemCpy] = (uint32_t)BL602_MemCpy,
+    [ROM_API_INDEX_BL602_MemCpy4] = (uint32_t)BL602_MemCpy4,
+    [ROM_API_INDEX_BL602_MemCpy_Fast] = (uint32_t)BL602_MemCpy_Fast,
+    [ROM_API_INDEX_BL602_MemSet] = (uint32_t)BL602_MemSet,
+    [ROM_API_INDEX_BL602_MemSet4] = (uint32_t)BL602_MemSet4,
+    [ROM_API_INDEX_BL602_MemCmp] = (uint32_t)BL602_MemCmp,
+
+    [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0,
+    [ROM_API_INDEX_EF_Ctrl_Program_Efuse_0] = (uint32_t)EF_Ctrl_Program_Efuse_0,
+    [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0,
+    [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy,
+    [ROM_API_INDEX_EF_Ctrl_AutoLoad_Done] = (uint32_t)EF_Ctrl_AutoLoad_Done,
+    [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity,
+    [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear,
+
+    [ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel,
+    [ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div,
+    [ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div,
+    [ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div,
+
+    [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL] = (uint32_t)Update_SystemCoreClockWith_XTAL,
+
+    [ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK,
+
+    [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M,
+
+    [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK,
+    [ROM_API_INDEX_GLB_Set_PKA_CLK_Sel] = (uint32_t)GLB_Set_PKA_CLK_Sel,
+    [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset,
+    [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset,
+    [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset,
+    [ROM_API_INDEX_GLB_Select_Internal_Flash] = (uint32_t)GLB_Select_Internal_Flash,
+    [ROM_API_INDEX_GLB_Select_External_Flash] = (uint32_t)GLB_Select_External_Flash,
+    [ROM_API_INDEX_GLB_Deswap_Flash_Pin] = (uint32_t)GLB_Deswap_Flash_Pin,
+    [ROM_API_INDEX_GLB_Swap_Flash_Pin] = (uint32_t)GLB_Swap_Flash_Pin,
+    [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init,
+    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable,
+    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable,
+    [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ,
+    [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun,
+
+    [ROM_API_INDEX_HBN_Mode_Enter] = (uint32_t)HBN_Mode_Enter,
+    [ROM_API_INDEX_HBN_Power_Down_Flash] = (uint32_t)HBN_Power_Down_Flash,
+    [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable,
+    [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset,
+    [ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout] = (uint32_t)HBN_Set_Ldo11_Aon_Vout,
+    [ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout] = (uint32_t)HBN_Set_Ldo11_Rt_Vout,
+    [ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout] = (uint32_t)HBN_Set_Ldo11_Soc_Vout,
+    [ROM_API_INDEX_HBN_32K_Sel] = (uint32_t)HBN_32K_Sel,
+    [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel,
+    [ROM_API_INDEX_HBN_Power_On_Xtal_32K] = (uint32_t)HBN_Power_On_Xtal_32K,
+    [ROM_API_INDEX_HBN_Power_Off_Xtal_32K] = (uint32_t)HBN_Power_Off_Xtal_32K,
+    [ROM_API_INDEX_HBN_Power_On_RC32K] = (uint32_t)HBN_Power_On_RC32K,
+    [ROM_API_INDEX_HBN_Power_Off_RC32K] = (uint32_t)HBN_Power_Off_RC32K,
+    [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K,
+    [ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg] = (uint32_t)HBN_Hw_Pu_Pd_Cfg,
+    [ROM_API_INDEX_HBN_Pin_WakeUp_Mask] = (uint32_t)HBN_Pin_WakeUp_Mask,
+    [ROM_API_INDEX_HBN_GPIO7_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO7_Dbg_Pull_Cfg,
+    [ROM_API_INDEX_HBN_Set_Embedded_Flash_Pullup] = (uint32_t)HBN_Set_Embedded_Flash_Pullup,
+
+    [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap,
+    [ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable,
+    [ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set,
+
+    [ROM_API_INDEX_PDS_Reset] = (uint32_t)PDS_Reset,
+    [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable,
+    [ROM_API_INDEX_PDS_Force_Config] = (uint32_t)PDS_Force_Config,
+    [ROM_API_INDEX_PDS_RAM_Config] = (uint32_t)PDS_RAM_Config,
+    [ROM_API_INDEX_PDS_Default_Level_Config] = (uint32_t)PDS_Default_Level_Config,
+    [ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M,
+    [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref,
+    [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref] = (uint32_t)PDS_Select_XTAL_As_PLL_Ref,
+    [ROM_API_INDEX_PDS_Power_On_PLL] = (uint32_t)PDS_Power_On_PLL,
+    [ROM_API_INDEX_PDS_Enable_PLL_All_Clks] = (uint32_t)PDS_Enable_PLL_All_Clks,
+    [ROM_API_INDEX_PDS_Disable_PLL_All_Clks] = (uint32_t)PDS_Disable_PLL_All_Clks,
+    [ROM_API_INDEX_PDS_Enable_PLL_Clk] = (uint32_t)PDS_Enable_PLL_Clk,
+    [ROM_API_INDEX_PDS_Disable_PLL_Clk] = (uint32_t)PDS_Disable_PLL_Clk,
+    [ROM_API_INDEX_PDS_Power_Off_PLL] = (uint32_t)PDS_Power_Off_PLL,
+
+    [ROM_API_INDEX_SEC_Eng_Turn_On_Sec_Ring] = (uint32_t)SEC_Eng_Turn_On_Sec_Ring,
+    [ROM_API_INDEX_SEC_Eng_Turn_Off_Sec_Ring] = (uint32_t)SEC_Eng_Turn_Off_Sec_Ring,
+
+    [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init,
+    [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode,
+    [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg,
+    [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg,
+    [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy,
+    [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable,
+    [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable,
+    [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable,
+    [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase,
+    [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase,
+    [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase,
+    [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase,
+    [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase,
+    [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program,
+    [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId,
+    [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId,
+    [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId,
+    [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown,
+    [ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown,
+    [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap,
+    [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap,
+    [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset,
+    [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read,
+    [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg,
+    [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable,
+    [ROM_API_INDEX_SFlash_Cache_Enable_Set] = (uint32_t)SFlash_Cache_Enable_Set,
+    [ROM_API_INDEX_SFlash_Cache_Flush] = (uint32_t)SFlash_Cache_Flush,
+    [ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable,
+    [ROM_API_INDEX_SFlash_Cache_Hit_Count_Get] = (uint32_t)SFlash_Cache_Hit_Count_Get,
+    [ROM_API_INDEX_SFlash_Cache_Miss_Count_Get] = (uint32_t)SFlash_Cache_Miss_Count_Get,
+    [ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable,
+    [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read,
+    [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd,
+    [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd,
+    [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown,
+
+    [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Init_Internal_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Internal_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Restore_GPIO17_Fun] = (uint32_t)SF_Cfg_Restore_GPIO17_Fun,
+    [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock,
+    [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify,
+    [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable,
+    [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad,
+    [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner,
+    [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable,
+    [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable,
+    [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset,
+    [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset,
+    [ROM_API_INDEX_SF_Ctrl_Select_Clock] = (uint32_t)SF_Ctrl_Select_Clock,
+    [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd,
+    [ROM_API_INDEX_SF_Ctrl_Icache_Set] = (uint32_t)SF_Ctrl_Icache_Set,
+    [ROM_API_INDEX_SF_Ctrl_Icache2_Set] = (uint32_t)SF_Ctrl_Icache2_Set,
+    [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState,
+    [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable,
+    [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay,
+    [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay,
+
+    [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save,
+    [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore,
+    [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Opt_Enter] = (uint32_t)XIP_SFlash_Opt_Enter,
+    [ROM_API_INDEX_XIP_SFlash_Opt_Exit] = (uint32_t)XIP_SFlash_Opt_Exit,
+
+    [ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32,
+
+    [ROM_API_INDEX_FUNC_EMPTY_START... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef,
+};
+
+/*@} end of group ROMDRIVER_Global_Variables */
+
+/** @defgroup ROMDRIVER_Private_FunctionDeclaration
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_FunctionDeclaration */
+
+/** @defgroup ROMDRIVER_Private_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Functions */
+
+/** @defgroup ROMDRIVER_Public_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Functions */
+
+/*@} end of group ROMDRIVER_COMMON */
+
+/*@} end of group BL602_Periph_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c
new file mode 100755
index 0000000000..c8ceab2787
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_sf_cfg_ext.c
@@ -0,0 +1,792 @@
+/**
+  ******************************************************************************
+  * @file    bl602_sf_cfg_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_glb.h"
+#include "bl602_sf_cfg_ext.h"
+#include "bflb_sf_cfg.h"
+#include "bflb_xip_sflash.h"
+#include "bl602_romdriver.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG_EXT
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_EXT_Private_Macros
+ *  @{
+ */
+#define BFLB_FLASH_CFG_MAGIC                    "FCFG"
+
+/*@} end of group SF_CFG_EXT_Private_Macros */
+
+/** @defgroup  SF_CFG_EXT_Private_Types
+ *  @{
+ */
+typedef struct {
+    uint32_t jedec_id;
+    char *name;
+    const spi_flash_cfg_type *cfg;
+}flash_info_t;
+
+/*@} end of group SF_CFG_EXT_Private_Types */
+
+/** @defgroup  SF_CFG_EXT_Private_Variables
+ *  @{
+ */
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_fm_25q08={
+        .reset_c_read_cmd=0xff,
+        .reset_c_read_cmd_size=3,
+        .mid=0xc8,
+
+        .de_burst_wrap_cmd=0x77,
+        .de_burst_wrap_cmd_dmy_clk=0x3,
+        .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .de_burst_wrap_data=0xF0,
+
+        /*reg*/
+        .write_enable_cmd=0x06,
+        .wr_enable_index=0x00,
+        .wr_enable_bit=0x01,
+        .wr_enable_read_reg_len=0x01,
+
+        .qe_index=1,
+        .qe_bit=0x01,
+        .qe_write_reg_len=0x02,
+        .qe_read_reg_len=0x1,
+
+        .busy_index=0,
+        .busy_bit=0x00,
+        .busy_read_reg_len=0x1,
+        .release_powerdown=0xab,
+
+        .read_reg_cmd[0]=0x05,
+        .read_reg_cmd[1]=0x35,
+        .write_reg_cmd[0]=0x01,
+        .write_reg_cmd[1]=0x01,
+
+        .fast_read_qio_cmd=0xeb,
+        .fr_qio_dmy_clk=16/8,
+        .c_read_support=1,
+        .c_read_mode=0xa0,
+
+        .burst_wrap_cmd=0x77,
+        .burst_wrap_cmd_dmy_clk=0x3,
+        .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .burst_wrap_data=0x40,
+         /*erase*/
+        .chip_erase_cmd=0xc7,
+        .sector_erase_cmd=0x20,
+        .blk32_erase_cmd=0x52,
+        .blk64_erase_cmd=0xd8,
+        /*write*/
+        .page_program_cmd=0x02,
+        .qpage_program_cmd=0x32,
+        .qpp_addr_mode=SF_CTRL_ADDR_1_LINE,
+
+        .io_mode=SF_CTRL_QIO_MODE,
+        .clk_delay=1,
+        .clk_invert=0x01,
+
+        .reset_en_cmd=0x66,
+        .reset_cmd=0x99,
+        .c_rexit=0xff,
+        .wr_enable_write_reg_len=0x00,
+
+        /*id*/
+        .jedec_id_cmd=0x9f,
+        .jedec_id_cmd_dmy_clk=0,
+        .qpi_jedec_id_cmd=0x9f,
+        .qpi_jedec_id_cmd_dmy_clk=0x00,
+        .sector_size=4,
+        .page_size=256,
+
+        /*read*/
+        .fast_read_cmd=0x0b,
+        .fr_dmy_clk=8/8,
+        .qpi_fast_read_cmd =0x0b,
+        .qpi_fr_dmy_clk=8/8,
+        .fast_read_do_cmd=0x3b,
+        .fr_do_dmy_clk=8/8,
+        .fast_read_dio_cmd=0xbb,
+        .fr_dio_dmy_clk=0,
+        .fast_read_qo_cmd=0x6b,
+        .fr_qo_dmy_clk=8/8,
+
+        .qpi_fast_read_qio_cmd=0xeb,
+        .qpi_fr_qio_dmy_clk=16/8,
+        .qpi_page_program_cmd=0x02,
+        .write_vreg_enable_cmd=0x50,
+
+        /* qpi mode */
+        .enter_qpi=0x38,
+        .exit_qpi=0xff,
+
+         /*AC*/
+        .time_e_sector=300,
+        .time_e_32k=1200,
+        .time_e_64k=1200,
+        .time_page_pgm=5,
+        .time_ce=33000,
+        .pd_delay=20,
+        .qe_data=0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_gd_md_40d={
+        .reset_c_read_cmd=0xff,
+        .reset_c_read_cmd_size=3,
+        .mid=0x51,
+
+        .de_burst_wrap_cmd=0x77,
+        .de_burst_wrap_cmd_dmy_clk=0x3,
+        .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .de_burst_wrap_data=0xF0,
+
+        /*reg*/
+        .write_enable_cmd=0x06,
+        .wr_enable_index=0x00,
+        .wr_enable_bit=0x01,
+        .wr_enable_read_reg_len=0x01,
+
+        .qe_index=1,
+        .qe_bit=0x01,
+        .qe_write_reg_len=0x02,
+        .qe_read_reg_len=0x1,
+
+        .busy_index=0,
+        .busy_bit=0x00,
+        .busy_read_reg_len=0x1,
+        .release_powerdown=0xab,
+
+        .read_reg_cmd[0]=0x05,
+        .read_reg_cmd[1]=0x35,
+        .write_reg_cmd[0]=0x01,
+        .write_reg_cmd[1]=0x01,
+
+        .fast_read_qio_cmd=0xeb,
+        .fr_qio_dmy_clk=16/8,
+        .c_read_support=0,
+        .c_read_mode=0xA0,
+
+        .burst_wrap_cmd=0x77,
+        .burst_wrap_cmd_dmy_clk=0x3,
+        .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .burst_wrap_data=0x40,
+         /*erase*/
+        .chip_erase_cmd=0xc7,
+        .sector_erase_cmd=0x20,
+        .blk32_erase_cmd=0x52,
+        .blk64_erase_cmd=0xd8,
+        /*write*/
+        .page_program_cmd=0x02,
+        .qpage_program_cmd=0x32,
+        .qpp_addr_mode=SF_CTRL_ADDR_1_LINE,
+
+        .io_mode=0x11,
+        .clk_delay=1,
+        .clk_invert=0x01,
+
+        .reset_en_cmd=0x66,
+        .reset_cmd=0x99,
+        .c_rexit=0xff,
+        .wr_enable_write_reg_len=0x00,
+
+        /*id*/
+        .jedec_id_cmd=0x9f,
+        .jedec_id_cmd_dmy_clk=0,
+        .qpi_jedec_id_cmd=0x9f,
+        .qpi_jedec_id_cmd_dmy_clk=0x00,
+        .sector_size=4,
+        .page_size=256,
+
+        /*read*/
+        .fast_read_cmd=0x0b,
+        .fr_dmy_clk=8/8,
+        .qpi_fast_read_cmd =0x0b,
+        .qpi_fr_dmy_clk=8/8,
+        .fast_read_do_cmd=0x3b,
+        .fr_do_dmy_clk=8/8,
+        .fast_read_dio_cmd=0xbb,
+        .fr_dio_dmy_clk=0,
+        .fast_read_qo_cmd=0x6b,
+        .fr_qo_dmy_clk=8/8,
+
+        .qpi_fast_read_qio_cmd=0xeb,
+        .qpi_fr_qio_dmy_clk=16/8,
+        .qpi_page_program_cmd=0x02,
+        .write_vreg_enable_cmd=0x50,
+
+        /* qpi mode */
+        .enter_qpi=0x38,
+        .exit_qpi=0xff,
+
+         /*AC*/
+        .time_e_sector=300,
+        .time_e_32k=1200,
+        .time_e_64k=1200,
+        .time_page_pgm=5,
+        .time_ce=33000,
+        .pd_delay=20,
+        .qe_data=0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_xm25qh16={
+        .reset_c_read_cmd=0xff,
+        .reset_c_read_cmd_size=3,
+        .mid=0x20,
+
+        .de_burst_wrap_cmd=0x77,
+        .de_burst_wrap_cmd_dmy_clk=0x3,
+        .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .de_burst_wrap_data=0xF0,
+
+        /*reg*/
+        .write_enable_cmd=0x06,
+        .wr_enable_index=0x00,
+        .wr_enable_bit=0x01,
+        .wr_enable_read_reg_len=0x01,
+
+        .qe_index=1,
+        .qe_bit=0x01,
+        .qe_write_reg_len=0x01,
+        .qe_read_reg_len=0x1,
+
+        .busy_index=0,
+        .busy_bit=0x00,
+        .busy_read_reg_len=0x1,
+        .release_powerdown=0xab,
+
+        .read_reg_cmd[0]=0x05,
+        .read_reg_cmd[1]=0x35,
+        .write_reg_cmd[0]=0x01,
+        .write_reg_cmd[1]=0x31,
+
+        .fast_read_qio_cmd=0xeb,
+        .fr_qio_dmy_clk=16/8,
+        .c_read_support=1,
+        .c_read_mode=0x20,
+
+        .burst_wrap_cmd=0x77,
+        .burst_wrap_cmd_dmy_clk=0x3,
+        .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .burst_wrap_data=0x40,
+         /*erase*/
+        .chip_erase_cmd=0xc7,
+        .sector_erase_cmd=0x20,
+        .blk32_erase_cmd=0x52,
+        .blk64_erase_cmd=0xd8,
+        /*write*/
+        .page_program_cmd=0x02,
+        .qpage_program_cmd=0x32,
+        .qpp_addr_mode=SF_CTRL_ADDR_1_LINE,
+
+        .io_mode=SF_CTRL_QIO_MODE,
+        .clk_delay=1,
+        .clk_invert=0x01,
+
+        .reset_en_cmd=0x66,
+        .reset_cmd=0x99,
+        .c_rexit=0xff,
+        .wr_enable_write_reg_len=0x00,
+
+        /*id*/
+        .jedec_id_cmd=0x9f,
+        .jedec_id_cmd_dmy_clk=0,
+        .qpi_jedec_id_cmd=0x9f,
+        .qpi_jedec_id_cmd_dmy_clk=0x00,
+        .sector_size=4,
+        .page_size=256,
+
+        /*read*/
+        .fast_read_cmd=0x0b,
+        .fr_dmy_clk=8/8,
+        .qpi_fast_read_cmd =0x0b,
+        .qpi_fr_dmy_clk=8/8,
+        .fast_read_do_cmd=0x3b,
+        .fr_do_dmy_clk=8/8,
+        .fast_read_dio_cmd=0xbb,
+        .fr_dio_dmy_clk=0,
+        .fast_read_qo_cmd=0x6b,
+        .fr_qo_dmy_clk=8/8,
+
+        .qpi_fast_read_qio_cmd=0xeb,
+        .qpi_fr_qio_dmy_clk=16/8,
+        .qpi_page_program_cmd=0x02,
+        .write_vreg_enable_cmd=0x50,
+
+        /* qpi mode */
+        .enter_qpi=0x38,
+        .exit_qpi=0xff,
+
+         /*AC*/
+        .time_e_sector=400,
+        .time_e_32k=1600,
+        .time_e_64k=2000,
+        .time_page_pgm=5,
+        .time_ce=33000,
+        .pd_delay=3,
+        .qe_data=0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_mx_kh25={
+        .reset_c_read_cmd=0xff,
+        .reset_c_read_cmd_size=3,
+        .mid=0xc2,
+
+        .de_burst_wrap_cmd=0x77,
+        .de_burst_wrap_cmd_dmy_clk=0x3,
+        .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .de_burst_wrap_data=0xF0,
+
+        /*reg*/
+        .write_enable_cmd=0x06,
+        .wr_enable_index=0x00,
+        .wr_enable_bit=0x01,
+        .wr_enable_read_reg_len=0x01,
+
+        .qe_index=1,
+        .qe_bit=0x01,
+        .qe_write_reg_len=0x01,
+        .qe_read_reg_len=0x1,
+
+        .busy_index=0,
+        .busy_bit=0x00,
+        .busy_read_reg_len=0x1,
+        .release_powerdown=0xab,
+
+        .read_reg_cmd[0]=0x05,
+        .read_reg_cmd[1]=0x00,
+        .write_reg_cmd[0]=0x01,
+        .write_reg_cmd[1]=0x00,
+
+        .fast_read_qio_cmd=0xeb,
+        .fr_qio_dmy_clk=16/8,
+        .c_read_support=0,
+        .c_read_mode=0x20,
+
+        .burst_wrap_cmd=0x77,
+        .burst_wrap_cmd_dmy_clk=0x3,
+        .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .burst_wrap_data=0x40,
+         /*erase*/
+        .chip_erase_cmd=0xc7,
+        .sector_erase_cmd=0x20,
+        .blk32_erase_cmd=0x52,
+        .blk64_erase_cmd=0xd8,
+        /*write*/
+        .page_program_cmd=0x02,
+        .qpage_program_cmd=0x32,
+        .qpp_addr_mode=SF_CTRL_ADDR_1_LINE,
+
+        .io_mode=0x11,
+        .clk_delay=1,
+        .clk_invert=0x01,
+
+        .reset_en_cmd=0x66,
+        .reset_cmd=0x99,
+        .c_rexit=0xff,
+        .wr_enable_write_reg_len=0x00,
+
+        /*id*/
+        .jedec_id_cmd=0x9f,
+        .jedec_id_cmd_dmy_clk=0,
+        .qpi_jedec_id_cmd=0x9f,
+        .qpi_jedec_id_cmd_dmy_clk=0x00,
+        .sector_size=4,
+        .page_size=256,
+
+        /*read*/
+        .fast_read_cmd=0x0b,
+        .fr_dmy_clk=8/8,
+        .qpi_fast_read_cmd =0x0b,
+        .qpi_fr_dmy_clk=8/8,
+        .fast_read_do_cmd=0x3b,
+        .fr_do_dmy_clk=8/8,
+        .fast_read_dio_cmd=0xbb,
+        .fr_dio_dmy_clk=0,
+        .fast_read_qo_cmd=0x6b,
+        .fr_qo_dmy_clk=8/8,
+
+        .qpi_fast_read_qio_cmd=0xeb,
+        .qpi_fr_qio_dmy_clk=16/8,
+        .qpi_page_program_cmd=0x02,
+        .write_vreg_enable_cmd=0x50,
+
+        /* qpi mode */
+        .enter_qpi=0x38,
+        .exit_qpi=0xff,
+
+         /*AC*/
+        .time_e_sector=300,
+        .time_e_32k=1200,
+        .time_e_64k=1200,
+        .time_page_pgm=5,
+        .time_ce=33000,
+        .pd_delay=20,
+        .qe_data=0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_zd_25q16b={
+        .reset_c_read_cmd=0xff,
+        .reset_c_read_cmd_size=3,
+        .mid=0xba,
+
+        .de_burst_wrap_cmd=0x77,
+        .de_burst_wrap_cmd_dmy_clk=0x3,
+        .de_burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .de_burst_wrap_data=0xF0,
+
+        /*reg*/
+        .write_enable_cmd=0x06,
+        .wr_enable_index=0x00,
+        .wr_enable_bit=0x01,
+        .wr_enable_read_reg_len=0x01,
+
+        .qe_index=1,
+        .qe_bit=0x01,
+        .qe_write_reg_len=0x02,
+        .qe_read_reg_len=0x1,
+
+        .busy_index=0,
+        .busy_bit=0x00,
+        .busy_read_reg_len=0x1,
+        .release_powerdown=0xab,
+
+        .read_reg_cmd[0]=0x05,
+        .read_reg_cmd[1]=0x35,
+        .write_reg_cmd[0]=0x01,
+        .write_reg_cmd[1]=0x01,
+
+        .fast_read_qio_cmd=0xeb,
+        .fr_qio_dmy_clk=16/8,
+        .c_read_support=1,
+        .c_read_mode=0xa0,
+
+        .burst_wrap_cmd=0x77,
+        .burst_wrap_cmd_dmy_clk=0x3,
+        .burst_wrap_data_mode=SF_CTRL_DATA_4_LINES,
+        .burst_wrap_data=0x40,
+         /*erase*/
+        .chip_erase_cmd=0xc7,
+        .sector_erase_cmd=0x20,
+        .blk32_erase_cmd=0x52,
+        .blk64_erase_cmd=0xd8,
+        /*write*/
+        .page_program_cmd=0x02,
+        .qpage_program_cmd=0x32,
+        .qpp_addr_mode=SF_CTRL_ADDR_1_LINE,
+
+        .io_mode=0x14,
+        .clk_delay=1,
+        .clk_invert=0x01,
+
+        .reset_en_cmd=0x66,
+        .reset_cmd=0x99,
+        .c_rexit=0xff,
+        .wr_enable_write_reg_len=0x00,
+
+        /*id*/
+        .jedec_id_cmd=0x9f,
+        .jedec_id_cmd_dmy_clk=0,
+        .qpi_jedec_id_cmd=0x9f,
+        .qpi_jedec_id_cmd_dmy_clk=0x00,
+        .sector_size=4,
+        .page_size=256,
+
+        /*read*/
+        .fast_read_cmd=0x0b,
+        .fr_dmy_clk=8/8,
+        .qpi_fast_read_cmd =0x0b,
+        .qpi_fr_dmy_clk=8/8,
+        .fast_read_do_cmd=0x3b,
+        .fr_do_dmy_clk=8/8,
+        .fast_read_dio_cmd=0xbb,
+        .fr_dio_dmy_clk=0,
+        .fast_read_qo_cmd=0x6b,
+        .fr_qo_dmy_clk=8/8,
+
+        .qpi_fast_read_qio_cmd=0xeb,
+        .qpi_fr_qio_dmy_clk=16/8,
+        .qpi_page_program_cmd=0x02,
+        .write_vreg_enable_cmd=0x50,
+
+        /* qpi mode */
+        .enter_qpi=0x38,
+        .exit_qpi=0xff,
+
+         /*AC*/
+        .time_e_sector=300,
+        .time_e_32k=1200,
+        .time_e_64k=1200,
+        .time_page_pgm=5,
+        .time_ce=33000,
+        .pd_delay=20,
+        .qe_data=0,
+};
+
+static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[]={
+    {
+        .jedec_id=0x1440A1,
+        //.name="FM_25Q08",
+        .cfg=&flashcfg_fm_25q08,
+    },
+    {
+        .jedec_id=0x134051,
+        //.name="GD_MD04D_04_33",
+        .cfg=&flashcfg_gd_md_40d,
+    },
+    {
+        .jedec_id=0x144020,
+        //.name="XM_25QH80_80_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x154020,
+        //.name="XM_25QH16_16_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x164020,
+        //.name="XM_25QH32_32_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x174020,
+        //.name="XM_25QH64_64_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x1320C2,
+        //.name="MX_KH40_04_33",
+        .cfg=&flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id=0x1420C2,
+        //.name="MX_KH80_08_33",
+        .cfg=&flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id=0x1520C2,
+        //.name="MX_KH16_16_33",
+        .cfg=&flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id=0x13325E,
+        //.name="ZB_D40B_80_33",
+        .cfg=&flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id=0x14325E,
+        //.name="ZB_D80B_80_33",
+        .cfg=&flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id=0x15405E,
+        //.name="ZB_25Q16B_15_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x16405E,
+        //.name="ZB_25Q32B_16_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x17405E,
+        //.name="ZB_25VQ64_64_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x15605E,
+        //.name="ZB_25VQ16_16_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x15345E,
+        //.name="ZB_25WQ16_16_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x1560EB,
+        //.name="TH_25Q16",
+        .cfg=&flashcfg_fm_25q08,
+    },
+    {
+        .jedec_id=0x1740C8,
+        //.name="GD_25Q64E_64_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x1840C8,
+        //.name="GD_25Q127C_128_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x176085,
+        //.name="Puya_P25Q64H_64_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+    {
+        .jedec_id=0x17400B,
+        //.name="XT_25F64B",
+        .cfg=&flashcfg_fm_25q08,
+    },
+    {
+        .jedec_id=0x1560BA,
+        //.name="ZD_25Q16B",
+        .cfg=&flashcfg_zd_25q16b,
+    },
+    {
+        .jedec_id=0x1460CD,
+        //.name="TH_25Q80HB",
+        .cfg=&flashcfg_fm_25q08,
+    },
+    {
+        .jedec_id=0x1870EF,
+        //.name="W25Q128JV_128_33",
+        .cfg=&flashcfg_xm25qh16,
+    },
+};
+
+/*@} end of group SF_CFG_EXT_Private_Variables */
+
+/** @defgroup  SF_CFG_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Global_Variables */
+
+/** @defgroup  SF_CFG_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */
+
+/** @defgroup  SF_CFG_EXT_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************//**
+ * @brief  Get flash config according to flash ID
+ *
+ * @param  flash_id: Flash ID
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type * p_flash_cfg,
+                                                             uint8_t group, uint8_t bank)
+{
+    uint32_t i;
+    uint8_t buf[sizeof(spi_flash_cfg_type)+8];
+    uint32_t crc,*p_crc;
+    char flash_cfg_magic[] = "FCFG";
+
+    if(flash_id==0){
+        bflb_xip_sflash_read_via_cache_need_lock(8+BL602_FLASH_XIP_BASE,buf,sizeof(spi_flash_cfg_type)+8,group,bank);
+        if(BL602_MemCmp(buf,flash_cfg_magic,4)==0){
+            crc=BFLB_Soft_CRC32((uint8_t *)buf+4,sizeof(spi_flash_cfg_type));
+            p_crc=(uint32_t *)(buf+4+sizeof(spi_flash_cfg_type));
+            if(*p_crc==crc){
+                BL602_MemCpy_Fast(p_flash_cfg,(uint8_t *)buf+4,sizeof(spi_flash_cfg_type));
+                return 0 ;
+            }
+        }
+    }else{
+        if(bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank) == 0){
+            return 0;
+        }
+        for(i=0;iio_mode&0xf,1,0,32,bank);
+    }
+    if((ret&BFLB_FLASH_ID_VALID_FLAG)!=0){
+        return ret;
+    }
+
+    jedec_id=(ret&0xffffff);
+    for(i=0;i
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl602_l1c.h"
+#include "bl602_sflash_ext.h"
+#include "bflb_sf_ctrl.h"
+#include "l1c_reg.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLASH_EXT
+ *  @{
+ */
+
+/** @defgroup  SFLASH_EXT_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Macros */
+
+/** @defgroup  SFLASH_EXT_Private_Types
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Types */
+
+/** @defgroup  SFLASH_EXT_Private_Variables
+ *  @{
+ */
+#define SFCTRL_BUSY_STATE_TIMEOUT (5 * 160 * 1000)
+
+#define SFLASH_L1C_BASE_ADDR      (0x40009000)
+#define SFLASH_L1C_CONFIG_OFFSET  (0x0)
+#define SFLASH_L1C_CACHEABLE      (1<<0U)
+#define SFLASH_L1C_CNT_EN         (1<<1U)
+#define SFLASH_L1C_INVALID_EN     (1<<2U)
+#define SFLASH_L1C_INVALID_DONE   (1<<3U)
+#define SFLASH_L1C_WAY_DIS_SHIFT  (8U)
+#define SFLASH_L1C_WAY_DIS_MASK   (0xf<io_mode & 0xf;
+
+    /* Wake flash up from power down */
+    bflb_sflash_release_powerdown(p_flash_cfg);
+    BL602_Delay_US(120);
+
+    bflb_sflash_get_jedecid(p_flash_cfg, (uint8_t *)&jedec_id);
+
+    if (SF_CTRL_QO_MODE == io_mode || SF_CTRL_QIO_MODE == io_mode) {
+        bflb_sflash_qspi_enable(p_flash_cfg);
+    }
+
+    if (((p_flash_cfg->io_mode >> 4) & 0x01) == 1) {
+        /* unwrap */
+        L1C_Set_Wrap(DISABLE);
+    } else {
+        /* burst wrap */
+        L1C_Set_Wrap(ENABLE);
+        /* For command that is setting register instead of send command, we need write enable */
+        bflb_sflash_write_enable(p_flash_cfg);
+        bflb_sflash_set_burst_wrap(p_flash_cfg);
+    }
+
+    if (flash_cont_read) {
+        stat = bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x00000000, (uint8_t *)tmp, sizeof(tmp));
+        stat = bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, 0);
+    } else {
+        stat = bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 0, 0, 32, 0);
+    }
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Sflash enable RCV mode to recovery for erase while power drop
+ *
+ * @param  p_flash_cfg: Flash configuration pointer
+ * @param  r_cmd: Read RCV register cmd
+ * @param  w_cmd: Write RCV register cmd
+ * @param  bit_pos: RCV register bit pos
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_rcv_enable(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos)
+{
+    int stat = -1;
+    uint32_t cnt = 0;
+    uint32_t regval = 0;
+
+    while (SET == bflb_sflash_busy(p_flash_cfg)) {
+        BL602_Delay_US(500);
+        cnt++;
+
+        if (cnt > 20000 * 3) {
+            return -1;
+        }
+    }
+
+    stat = bflb_sflash_read_reg_with_cmd(p_flash_cfg, r_cmd, (uint8_t *)®val, 1);
+
+    if (0 != stat) {
+        stat = -1;
+    }
+
+    if (((regval >> bit_pos) & 0x01) > 0) {
+        return 0;
+    }
+
+    regval |= (uint32_t)(1 << bit_pos);
+    stat = bflb_sflash_write_enable(p_flash_cfg);
+
+    if (0 != stat) {
+        stat = -1;
+    }
+
+    stat = bflb_sflash_write_reg_with_cmd(p_flash_cfg, w_cmd, (uint8_t *)®val, 1);
+
+    if (0 != stat) {
+        return stat;
+    }
+
+    while (SET == bflb_sflash_busy(p_flash_cfg)) {
+        BL602_Delay_US(500);
+        cnt++;
+
+        if (cnt > 20000 * 3) {
+            return -1;
+        }
+    }
+
+    stat = bflb_sflash_read_reg_with_cmd(p_flash_cfg, r_cmd, (uint8_t *)®val, 1);
+
+    if (0 != stat) {
+        stat = -1;
+    }
+
+    if (((regval >> bit_pos) & 0x01) <= 0) {
+        return -1;
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash security register one block
+ *
+ * @param  p_flash_cfg: Flash configuration pointer
+ * @param  p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_erase_security_register(spi_flash_cfg_type *p_flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+    uint32_t cnt = 0;
+    uint8_t cmd = 0;
+    uint8_t sec_opt_mode = 0;
+    uint32_t time_out = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+        sec_opt_mode = 1;
+
+        if (((uint32_t)&flash_cmd) % 4 == 0) {
+            BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        time_out = SFCTRL_BUSY_STATE_TIMEOUT;
+
+        while (SET == bflb_sf_ctrl_get_busy_state()) {
+            time_out--;
+
+            if (time_out == 0) {
+                return -2;
+            }
+        }
+    }
+
+    int stat = bflb_sflash_write_enable(p_flash_cfg);
+
+    if (stat != 0) {
+        return stat;
+    }
+
+    if (((uint32_t)&flash_cmd) % 4 == 0) {
+        BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    cmd = p_sec_reg_cfg->erase_cmd;
+    flash_cmd.cmd_buf[0] = (cmd << 24) | (p_sec_reg_cfg->block_num << 12);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (SET == bflb_sflash_busy(p_flash_cfg)) {
+        BL602_Delay_US(500);
+        cnt++;
+
+        if (cnt > p_flash_cfg->time_e_sector * 3) {
+            return -1;
+        }
+    }
+
+    if (sec_opt_mode > 0) {
+        if (((uint32_t)&flash_cmd) % 4 == 0) {
+            BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        time_out = SFCTRL_BUSY_STATE_TIMEOUT;
+
+        while (SET == bflb_sf_ctrl_get_busy_state()) {
+            time_out--;
+
+            if (time_out == 0) {
+                return -2;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Program flash security register one block
+ *
+ * @param  p_flash_cfg: Flash configuration pointer
+ * @param  p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_program_security_register(spi_flash_cfg_type *p_flash_cfg,
+                                                  struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE;
+    uint32_t i = 0, cur_len = 0;
+    uint32_t cnt = 0;
+    int stat = -1;
+    uint8_t cmd;
+    uint8_t sec_opt_mode = 0;
+    uint8_t *data = p_sec_reg_cfg->data;
+    uint32_t addr = p_sec_reg_cfg->addr;
+    uint32_t len = p_sec_reg_cfg->len;
+    uint32_t current_addr = 0;
+    uint32_t time_out = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+        sec_opt_mode = 1;
+
+        if (((uint32_t)&flash_cmd) % 4 == 0) {
+            BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        time_out = SFCTRL_BUSY_STATE_TIMEOUT;
+
+        while (SET == bflb_sf_ctrl_get_busy_state()) {
+            time_out--;
+
+            if (time_out == 0) {
+                return -2;
+            }
+        }
+    }
+
+    if (((uint32_t)&flash_cmd) % 4 == 0) {
+        BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    /* Prepare command */
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.addr_size = 3;
+    cmd = p_sec_reg_cfg->program_cmd;
+
+    for (i = 0; i < len;) {
+        /* Write enable is needed for every program */
+        stat = bflb_sflash_write_enable(p_flash_cfg);
+
+        if (stat != 0) {
+            return stat;
+        }
+
+        /* Get current programmed length within page size */
+        cur_len = 256 - addr % 256;
+
+        if (cur_len > len - i) {
+            cur_len = len - i;
+        }
+
+        current_addr = (p_sec_reg_cfg->block_num << 12) | addr;
+
+        /* Prepare command */
+        BL602_MemCpy_Fast(flash_ctrl_buf, data, cur_len);
+        flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr);
+        flash_cmd.nb_data = cur_len;
+
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        /* Adjust address and programmed length */
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+
+        /* Wait for write done */
+        cnt = 0;
+
+        while (SET == bflb_sflash_busy(p_flash_cfg)) {
+            BL602_Delay_US(100);
+            cnt++;
+
+            if (cnt > p_flash_cfg->time_page_pgm * 20) {
+                return -1;
+            }
+        }
+    }
+
+    if (sec_opt_mode > 0) {
+        if (((uint32_t)&flash_cmd) % 4 == 0) {
+            BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        time_out = SFCTRL_BUSY_STATE_TIMEOUT;
+
+        while (SET == bflb_sf_ctrl_get_busy_state()) {
+            time_out--;
+
+            if (time_out == 0) {
+                return -2;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash security register one block
+ *
+ * @param  p_sec_reg_cfg: Security register configuration pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE;
+    uint32_t cur_len, i;
+    uint8_t cmd;
+    uint8_t sec_opt_mode = 0;
+    uint8_t *data = p_sec_reg_cfg->data;
+    uint32_t addr = p_sec_reg_cfg->addr;
+    uint32_t len = p_sec_reg_cfg->len;
+    uint32_t current_addr = 0;
+    uint32_t time_out = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (p_sec_reg_cfg->enter_sec_opt_cmd != 0x00) {
+        sec_opt_mode = 1;
+
+        if (((uint32_t)&flash_cmd) % 4 == 0) {
+            BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->enter_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        time_out = SFCTRL_BUSY_STATE_TIMEOUT;
+
+        while (SET == bflb_sf_ctrl_get_busy_state()) {
+            time_out--;
+
+            if (time_out == 0) {
+                return -2;
+            }
+        }
+    }
+
+    if (((uint32_t)&flash_cmd) % 4 == 0) {
+        BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    /* Prepare command */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+    flash_cmd.dummy_clks = 1;
+    cmd = p_sec_reg_cfg->read_cmd;
+
+    /* Read data */
+    for (i = 0; i < len;) {
+        current_addr = (p_sec_reg_cfg->block_num << 12) | addr;
+        /* Prepare command */
+        flash_cmd.cmd_buf[0] = (cmd << 24) | (current_addr);
+        cur_len = len - i;
+
+        if (cur_len >= NOR_FLASH_CTRL_BUF_SIZE) {
+            cur_len = NOR_FLASH_CTRL_BUF_SIZE;
+            flash_cmd.nb_data = cur_len;
+        } else {
+            /* Make sf_ctrl word read */
+            flash_cmd.nb_data = ((cur_len + 3) >> 2) << 2;
+        }
+
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        time_out = SFCTRL_BUSY_STATE_TIMEOUT;
+
+        while (SET == bflb_sf_ctrl_get_busy_state()) {
+            time_out--;
+
+            if (time_out == 0) {
+                return -2;
+            }
+        }
+
+        BL602_MemCpy_Fast(data, flash_ctrl_buf, cur_len);
+
+        addr += cur_len;
+        i += cur_len;
+        data += cur_len;
+    }
+
+    if (sec_opt_mode > 0) {
+        if (((uint32_t)&flash_cmd) % 4 == 0) {
+            BL602_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+        } else {
+            BL602_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+        }
+
+        flash_cmd.cmd_buf[0] = (p_sec_reg_cfg->exit_sec_opt_cmd << 24);
+        flash_cmd.rw_flag = SF_CTRL_WRITE;
+        bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+        time_out = SFCTRL_BUSY_STATE_TIMEOUT;
+
+        while (SET == bflb_sf_ctrl_get_busy_state()) {
+            time_out--;
+
+            if (time_out == 0) {
+                return -2;
+            }
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register
+ *
+ * @param  p_flash_cfg: Flash configuration pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg)
+{
+    uint32_t ret = 0;
+    uint32_t qe_value = 0;
+    uint32_t reg_value = 0;
+    uint32_t read_value = 0;
+    uint8_t read_reg_value0 = 0;
+    uint8_t read_reg_value1 = 0;
+
+    if((p_flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE){
+        qe_value = 1;
+    }
+
+    bflb_sflash_read_reg(p_flash_cfg, 0, (uint8_t *)&read_reg_value0, 1);
+    bflb_sflash_read_reg(p_flash_cfg, 1, (uint8_t *)&read_reg_value1, 1);
+    read_value = (read_reg_value0|(read_reg_value1<<8));
+    if ((read_value & (~((1<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit)) |
+                         (1<<(p_flash_cfg->busy_index*8+p_flash_cfg->busy_bit)) |
+                         (1<<(p_flash_cfg->wr_enable_index*8+p_flash_cfg->wr_enable_bit))))) == 0){
+        return 0;
+    }
+
+    ret = bflb_sflash_write_enable(p_flash_cfg);
+    if (0 != ret) {
+        return -1;
+    }
+    if (p_flash_cfg->qe_write_reg_len == 2) {
+        reg_value = (qe_value<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit));
+        bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 2);
+    } else {
+        if (p_flash_cfg->qe_index == 0) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 1);
+        ret = bflb_sflash_write_enable(p_flash_cfg);
+        if (0 != ret) {
+            return -1;
+        }
+        if (p_flash_cfg->qe_index == 1) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(p_flash_cfg, 1, (uint8_t *)®_value, 1);
+    }
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable cache
+ *
+ * @param  way_disable: cache way disable config
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_cache_enable_set(uint8_t way_disable)
+{
+    uint32_t regval = 0;
+
+    uint32_t cnt = 0;
+
+    /* Set cacheable to 0 */
+    regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET);
+    regval &= ~SFLASH_L1C_CACHEABLE;
+    regval |= SFLASH_L1C_BYPASS;
+    regval &= ~SFLASH_L1C_WAY_DIS_MASK;
+    regval &= ~SFLASH_L1C_CNT_EN;
+    putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET);
+
+    regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET);
+    /*Set Tag RAM to zero */
+    regval &= ~SFLASH_L1C_INVALID_EN;
+    putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    regval|= SFLASH_L1C_INVALID_EN;
+    putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Polling for invalid done */
+    do {
+        BL602_Delay_US(1);
+        cnt++;
+        regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET);
+    } while (!((regval&SFLASH_L1C_INVALID_DONE) > 0 ? 1:0) && cnt < 100);
+
+    regval |= SFLASH_L1C_BYPASS;
+    putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET);
+
+    regval &= ~SFLASH_L1C_BYPASS;
+    regval &= ~SFLASH_L1C_WAY_DIS_MASK;
+    regval |= SFLASH_L1C_CNT_EN;
+    putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET);
+
+    regval &= ~SFLASH_L1C_WAY_DIS_MASK;
+    regval |= (way_disable << SFLASH_L1C_WAY_DIS_SHIFT);
+
+    /* If way disable is 0x0f, cacheable can't be set */
+    if (way_disable != 0x0f) {
+        regval |= SFLASH_L1C_CACHEABLE;
+    } else {
+        regval &= ~SFLASH_L1C_CACHEABLE;
+    }
+
+    putreg32(regval, SFLASH_L1C_BASE_ADDR+SFLASH_L1C_CONFIG_OFFSET);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Flush cache
+ *
+ * @param  None
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_cache_flush(void)
+{
+    uint32_t regval = 0;
+    uint32_t way_disable = 0;
+
+    /* Disable early respone */
+    regval = getreg32(SFLASH_L1C_BASE_ADDR + SFLASH_L1C_CONFIG_OFFSET);
+    way_disable = (regval&SFLASH_L1C_WAY_DIS_MASK) >> SFLASH_L1C_WAY_DIS_SHIFT;
+    bflb_sflash_cache_enable_set(way_disable & 0xf);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    return 0;
+}
+
+/*@} end of group SFLASH_EXT_Public_Functions */
+
+/*@} end of group SFLASH_EXT */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_tzc_sec.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_tzc_sec.c
new file mode 100755
index 0000000000..048bd144e9
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_tzc_sec.c
@@ -0,0 +1,237 @@
+/**
+  ******************************************************************************
+  * @file    bl602_tzc_sec.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "string.h"
+#include "bl602_tzc_sec.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  TZC_SEC
+ *  @{
+ */
+
+/** @defgroup  TZC_SEC_Private_Macros
+ *  @{
+ */
+
+/*@} end of group TZC_SEC_Private_Macros */
+
+/** @defgroup  TZC_SEC_Private_Types
+ *  @{
+ */
+
+/*@} end of group TZC_SEC_Private_Types */
+
+/** @defgroup  TZC_SEC_Private_Variables
+ *  @{
+ */
+
+/*@} end of group TZC_SEC_Private_Variables */
+
+/** @defgroup  TZC_SEC_Global_Variables
+ *  @{
+ */
+
+/*@} end of group TZC_SEC_Global_Variables */
+
+/** @defgroup  TZC_SEC_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group TZC_SEC_Private_Fun_Declaration */
+
+/** @defgroup  TZC_SEC_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  TZC Security boot set
+ *
+ * @param  Val: 0 for security boot start, and 0xf for security boot finished
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TZC_Sboot_Set(uint8_t Val)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, Val);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TZC Set ROM0 R0 protect range
+ *
+ * @param  start: Start address to protect
+ * @param  length: length to protect
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TZC_Set_Rom0_R0_Protect(uint32_t start, uint32_t length)
+{
+    uint32_t tmpVal;
+    uint32_t alignEnd = (start+length+1023)&~0x3FF;
+
+    /* Set Range */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_START, ((start >> 10)&0xffff));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_END, ((alignEnd >> 10)&0xffff)-1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R0, tmpVal);
+
+    /* Enable */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID0_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_ID1_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R0_LOCK, 1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TZC Set ROM0 R1 protect range
+ *
+ * @param  start: Start address to protect
+ * @param  length: length to protect
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TZC_Set_Rom0_R1_Protect(uint32_t start, uint32_t length)
+{
+    uint32_t tmpVal;
+    uint32_t alignEnd = (start+length+1023)&~0x3FF;
+
+    /* Set Range */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_START, ((start >> 10)&0xffff));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_END, ((alignEnd >> 10)&0xffff)-1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM0_R1, tmpVal);
+
+    /* Enable */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID0_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_ID1_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM0_R1_LOCK, 1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TZC Set ROM1 R0 protect range
+ *
+ * @param  start: Start address to protect
+ * @param  length: length to protect
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TZC_Set_Rom1_R0_Protect(uint32_t start, uint32_t length)
+{
+    uint32_t tmpVal;
+    uint32_t alignEnd = (start+length+1023)&~0x3FF;
+
+    /* Set Range */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_START, ((start >> 10)&0xffff));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_END, ((alignEnd >> 10)&0xffff)-1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R0, tmpVal);
+
+    /* Enable */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID0_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_ID1_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R0_LOCK, 1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TZC Set ROM1 R1 protect range
+ *
+ * @param  start: Start address to protect
+ * @param  length: length to protect
+ *
+ * @return None
+ *
+*******************************************************************************/
+void TZC_Set_Rom1_R1_Protect(uint32_t start, uint32_t length)
+{
+    uint32_t tmpVal;
+    uint32_t alignEnd = (start+length+1023)&~0x3FF;
+
+    /* Set Range */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_START, ((start >> 10)&0xffff));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_END, ((alignEnd >> 10)&0xffff)-1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM1_R1, tmpVal);
+
+    /* Enable */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID0_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_ID1_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_ROM1_R1_LOCK, 1);
+
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_CTRL, tmpVal);
+}
+
+/*@} end of group TZC_SEC_Public_Functions */
+
+/*@} end of group TZC_SEC */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c
new file mode 100755
index 0000000000..8a9e8df6cd
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/src/bl602_xip_sflash_ext.c
@@ -0,0 +1,593 @@
+/**
+  ******************************************************************************
+  * @file    bl602_xip_sflash_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "string.h"
+#include "bflb_sf_cfg.h"
+#include "bl602_sf_cfg_ext.h"
+#include "bflb_xip_sflash.h"
+#include "bl602_xip_sflash_ext.h"
+
+/** @addtogroup  BL602_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH_EXT
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Macros */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Types */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Variables
+ *  @{
+ */
+
+static spi_flash_cfg_type flash_cfg;
+static uint8_t aes_enable;
+
+/*@} end of group XIP_SFLASH_EXT_Private_Variables */
+
+/** @defgroup  XIP_SFLASH_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Global_Variables */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Functions
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Functions */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************//**
+ * @brief  Save flash controller state
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  offset: CPU XIP flash offset pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_state_save_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t *offset,
+                                                                         uint8_t group, uint8_t bank)
+{
+    /* XIP_SFlash_Delay */
+    volatile uint32_t i=32*2;
+    while(i--);
+    
+    bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+    /* Exit form continous read for accepting command */
+    bflb_sflash_reset_continue_read(p_flash_cfg);
+    /* Send software reset command(80bv has no this command)to deburst wrap for ISSI like */
+    bflb_sflash_software_reset(p_flash_cfg);
+    /* For disable command that is setting register instaed of send command, we need write enable */
+    bflb_sflash_disable_burst_wrap(p_flash_cfg);
+    if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
+        /* Enable QE again in case reset command make it reset */
+        bflb_sflash_qspi_enable(p_flash_cfg);
+    }
+    /* Deburst again to make sure */
+    bflb_sflash_disable_burst_wrap(p_flash_cfg);
+
+    /* Clear offset setting*/
+    *offset=bflb_sf_ctrl_get_flash_image_offset(group, bank);
+    bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Restore flash controller state
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  offset: CPU XIP flash offset
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_state_restore_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t offset,
+                                                                            uint8_t group, uint8_t bank)
+{
+    uint32_t tmp[1];
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
+
+    if (((p_flash_cfg->io_mode >> 4) & 0x01) == 0) {
+        if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
+            bflb_sflash_set_burst_wrap(p_flash_cfg);
+        }
+    }
+    bflb_sflash_read(p_flash_cfg, io_mode, 1, 0x0, (uint8_t *)tmp, sizeof(tmp));
+    bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+
+    return 0;
+}
+
+/*@} end of group XIP_SFLASH_EXT_Public_Functions */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one region
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  startaddr: start address to erase
+ * @param  endaddr: end address(include this address) to erase
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr,
+                                                               uint32_t endaddr, uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode&0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat=bflb_xip_sflash_state_save(p_flash_cfg,&offset,group,bank);
+    if(stat!=0){
+        bflb_sflash_set_xip_cfg(p_flash_cfg,io_mode,1,0,32,bank);
+    }else{
+        stat=bflb_sflash_erase(p_flash_cfg,startaddr,endaddr);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg,offset,group,bank);
+    }
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Program flash one region
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: start address to be programed
+ * @param  data: data pointer to be programed
+ * @param  len: data length to be programed
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
+                                               uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode&0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat=bflb_xip_sflash_state_save(p_flash_cfg,&offset,group,bank);
+    if(stat!=0){
+        bflb_sflash_set_xip_cfg(p_flash_cfg,io_mode,1,0,32,bank);
+    }else{
+        stat= bflb_sflash_program(p_flash_cfg,io_mode,addr,data,len);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg,offset,group,bank);
+    }
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint32_t addr,
+                                              uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode&0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat=bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+    if(stat!=0){
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    }else{
+        stat=bflb_sflash_read(p_flash_cfg, io_mode,0, addr, data, len);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank);
+    }
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register need lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg,
+                                                                         uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode&0xf;
+
+    stat=bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat=bflb_sflash_clear_status_register(p_flash_cfg);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset,  group, bank);
+    }
+
+    return stat;
+}
+
+/****************************************************************************//**
+ * @brief  Get Flash Jedec ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  data: data pointer to store Jedec ID Read from flash
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_getjedecid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                                                                 uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_jedecid(p_flash_cfg, data);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Device ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  data: data pointer to store Device ID Read from flash
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_deviceid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg,
+                             uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_deviceid(data, is_32bits_addr);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Unique ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  data: data pointer to store Device ID Read from flash
+ * @param  id_len: Unique id len
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_get_uniqueid_need_lock_ext(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                                                uint8_t id_len, uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_uniqueid(data, id_len);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Sflash enable RCV mode to recovery for erase while power drop need lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  r_cmd: Read RCV register cmd
+ * @param  w_cmd: Write RCV register cmd
+ * @param  bit_pos: RCV register bit pos
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_rcv_enable_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd,
+                                                          uint8_t bit_pos, uint8_t group, uint8_t bank)
+{
+    int stat = -1;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32 , bank);
+    } else {
+        stat = bflb_sflash_rcv_enable(p_flash_cfg, r_cmd, w_cmd, bit_pos);
+        bflb_xip_sflash_state_restore_ext(p_flash_cfg, offset, group, bank);
+    }
+
+    return stat;
+}
+
+/****************************************************************************//**
+ * @brief  Read data from flash with lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: flash read start address
+ * @param  dst: data pointer to store data read from flash
+ * @param  len: data length to read
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read_with_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t addr, uint8_t *dst, int len)
+{
+    __disable_irq();
+    bflb_xip_sflash_read_need_lock_ext(p_flash_cfg, addr, dst, len, 0, 0);
+    __enable_irq();
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Program flash one region with lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: Start address to be programed
+ * @param  src: Data pointer to be programed
+ * @param  len: Data length to be programed
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_ip_sflash_write_with_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t addr, uint8_t *src, int len)
+{
+    __disable_irq();
+    bflb_xip_sflash_write_need_lock_ext(p_flash_cfg, addr, src, len, 0, 0);
+    __enable_irq();
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Erase flash one region with lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: Start address to be erased
+ * @param  len: Data length to be erased
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_erase_with_lock_ext(spi_flash_cfg_type *p_flash_cfg,uint32_t addr, int len)
+{
+    __disable_irq();
+    bflb_xip_sflash_erase_need_lock_ext(p_flash_cfg, addr, addr + len - 1, 0, 0);
+    __enable_irq();
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register with lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_clear_status_register_with_lock(spi_flash_cfg_type *p_flash_cfg)
+{
+    __disable_irq();
+    bflb_xip_sflash_clear_status_register_need_lock(p_flash_cfg, 0, 0);
+    __enable_irq();
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Sflash enable RCV mode to recovery for erase while power drop with lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  r_cmd: Read RCV register cmd
+ * @param  w_cmd: Write RCV register cmd
+ * @param  bit_pos: RCV register bit pos
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_rcv_enable_with_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos)
+{
+    __disable_irq();
+    bflb_xip_sflash_rcv_enable_need_lock(p_flash_cfg, r_cmd, w_cmd, bit_pos, 0, 0);
+    __enable_irq();
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Read data from flash with lock
+ *
+ * @param  p_flash_cfg:Flash config pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_init(spi_flash_cfg_type *p_flash_cfg)
+{
+    uint32_t ret;
+
+    if(p_flash_cfg==NULL){
+        /* Get flash config identify */
+        bflb_xip_sflash_opt_enter(&aes_enable);
+        ret=bflb_sf_cfg_flash_identify_ext(1, 0x80, 0, &flash_cfg, 0, 0);
+        bflb_xip_sflash_opt_exit(aes_enable);
+        if((ret&BFLB_FLASH_ID_VALID_FLAG)==0){
+            return -1;
+        }
+    }else{
+        memcpy(&flash_cfg,p_flash_cfg,sizeof(flash_cfg));
+    }
+    
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Read data from flash with lock
+ *
+ * @param  addr: flash read start address
+ * @param  dst: data pointer to store data read from flash
+ * @param  len: data length to read
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read(uint32_t addr, uint8_t *dst, int len)
+{
+    __disable_irq();
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    bflb_xip_sflash_read_need_lock_ext(&flash_cfg, addr, dst, len, 0, 0);
+    bflb_xip_sflash_opt_exit(aes_enable);
+    __enable_irq();
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Program flash one region with lock
+ *
+ * @param  addr: Start address to be programed
+ * @param  src: Data pointer to be programed
+ * @param  len: Data length to be programed
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_write(uint32_t addr, uint8_t *src, int len)
+{
+    __disable_irq();
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    bflb_xip_sflash_write_need_lock_ext(&flash_cfg, addr, src, len, 0, 0);
+    bflb_xip_sflash_opt_exit(aes_enable);
+    __enable_irq();
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Erase flash one region with lock
+ *
+ * @param  addr: Start address to be erased
+ * @param  len: Data length to be erased
+ *
+ * @return 0
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_erase(uint32_t addr, int len)
+{
+    __disable_irq();
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    bflb_xip_sflash_erase_need_lock_ext(&flash_cfg, addr, addr + len - 1, 0, 0);
+    bflb_xip_sflash_opt_exit(aes_enable);
+    __enable_irq();
+    return 0;
+}
+/*@} end of group XIP_SFLASH_EXT_Public_Functions */
+
+/*@} end of group XIP_SFLASH_EXT */
+
+/*@} end of group BL602_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/interrupt.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/interrupt.c
new file mode 100755
index 0000000000..69df558d15
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/interrupt.c
@@ -0,0 +1,204 @@
+/**
+ * @file interrupt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bflb_core.h"
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
+
+extern void default_trap_handler(void);
+extern void default_interrupt_handler(void);
+
+const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /* 3       */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /* 7       */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /* 11      */
+    default_interrupt_handler, /* 12      */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /* 16 +  0 */
+    default_interrupt_handler, /* 16 +  1 */
+    default_interrupt_handler, /* 16 +  2 */
+    default_interrupt_handler, /* 16 +  3 */
+    default_interrupt_handler, /* 16 +  4 */
+    default_interrupt_handler, /* 16 +  5 */
+    default_interrupt_handler, /* 16 +  6 */
+    default_interrupt_handler, /* 16 +  7 */
+    default_interrupt_handler, /* 16 +  8 */
+    default_interrupt_handler, /* 16 +  9 */
+    default_interrupt_handler, /* 16 + 10 */
+    default_interrupt_handler, /* 16 + 11 */
+    default_interrupt_handler, /* 16 + 12 */
+    default_interrupt_handler, /* 16 + 13 */
+    default_interrupt_handler, /* 16 + 14 */
+    default_interrupt_handler, /* 16 + 15 */
+    default_interrupt_handler, /* 16 + 16 */
+    default_interrupt_handler, /* 16 + 17 */
+    default_interrupt_handler, /* 16 + 18 */
+    default_interrupt_handler, /* 16 + 19 */
+    default_interrupt_handler, /* 16 + 20 */
+    default_interrupt_handler, /* 16 + 21 */
+    default_interrupt_handler, /* 16 + 22 */
+    default_interrupt_handler, /* 16 + 23 */
+    default_interrupt_handler, /* 16 + 24 */
+    default_interrupt_handler, /* 16 + 25 */
+    default_interrupt_handler, /* 16 + 26 */
+    default_interrupt_handler, /* 16 + 27 */
+    default_interrupt_handler, /* 16 + 28 */
+    default_interrupt_handler, /* 16 + 29 */
+    default_interrupt_handler, /* 16 + 30 */
+    default_interrupt_handler, /* 16 + 31 */
+    default_interrupt_handler, /* 16 + 32 */
+    default_interrupt_handler, /* 16 + 33 */
+    default_interrupt_handler, /* 16 + 34 */
+    default_interrupt_handler, /* 16 + 35 */
+    default_interrupt_handler, /* 16 + 36 */
+    default_interrupt_handler, /* 16 + 37 */
+    default_interrupt_handler, /* 16 + 38 */
+    default_interrupt_handler, /* 16 + 39 */
+    default_interrupt_handler, /* 16 + 40 */
+    default_interrupt_handler, /* 16 + 41 */
+    default_interrupt_handler, /* 16 + 42 */
+    default_interrupt_handler, /* 16 + 43 */
+    default_interrupt_handler, /* 16 + 44 */
+    default_interrupt_handler, /* 16 + 45 */
+    default_interrupt_handler, /* 16 + 46 */
+    default_interrupt_handler, /* 16 + 47 */
+    default_interrupt_handler, /* 16 + 48 */
+    default_interrupt_handler, /* 16 + 49 */
+    default_interrupt_handler, /* 16 + 50 */
+    default_interrupt_handler, /* 16 + 51 */
+    default_interrupt_handler, /* 16 + 52 */
+    default_interrupt_handler, /* 16 + 53 */
+    default_interrupt_handler, /* 16 + 54 */
+    default_interrupt_handler, /* 16 + 55 */
+    default_interrupt_handler, /* 16 + 56 */
+    default_interrupt_handler, /* 16 + 57 */
+    default_interrupt_handler, /* 16 + 58 */
+    default_interrupt_handler, /* 16 + 59 */
+    default_interrupt_handler, /* 16 + 60 */
+    default_interrupt_handler, /* 16 + 61 */
+    default_interrupt_handler, /* 16 + 62 */
+    default_interrupt_handler, /* 16 + 63 */
+};
+
+void exception_entry(void)
+{
+    unsigned long cause;
+    unsigned long epc;
+    unsigned long tval;
+
+    printf("exception_entry\r\n");
+
+    cause = READ_CSR(CSR_MCAUSE);
+    printf("mcause=%08x\r\n", (int)cause);
+    epc = READ_CSR(CSR_MEPC);
+    printf("mepc:%08x\r\n", (int)epc);
+    tval = READ_CSR(CSR_MTVAL);
+    printf("mtval:%08x\r\n", (int)tval);
+
+    cause = (cause & 0x3ff);
+
+#ifndef CONFIG_TRAP_DUMP_DISABLE
+    const char *mcause_str[] = {
+        "Instruction address misaligned",
+        "Instruction access fault",
+        "Illegal instruction",
+        "Breakpoint",
+        "Load address misaligned",
+        "Load access fault",
+        "Store/AMO address misaligned",
+        "Store/AMO access fault",
+        "Environment call from U-mode",
+        "Environment call from S-mode",
+        "RSVD",
+        "Environment call from M-mode",
+        "Instruction page fault",
+        "Load page fault",
+        "RSVD",
+        "Store/AMO page fault"
+    };
+
+    printf("%s\r\n", mcause_str[cause & 0xf]);
+#endif
+    if ((cause == 8) || (cause == 11)) {
+        epc += 4;
+        WRITE_CSR(CSR_MEPC, epc);
+    } else {
+        while (1) {
+        }
+    }
+}
+
+void interrupt_entry(void)
+{
+    irq_callback handler;
+    void *arg;
+    volatile uint32_t mcause = 0UL;
+    uint32_t irq_num;
+
+    mcause = READ_CSR(CSR_MCAUSE);
+    irq_num = mcause & 0x3FF;
+
+    if (irq_num < CONFIG_IRQ_NUM) {
+        handler = g_irqvector[irq_num].handler;
+        arg = g_irqvector[irq_num].arg;
+        if (handler) {
+            handler(irq_num, arg);
+        } else {
+        }
+    } else {
+    }
+}
+
+__attribute__((interrupt, aligned(64))) void default_trap_handler(void)
+{
+    exception_entry();
+}
+
+__attribute__((interrupt)) __attribute__((weak)) void default_interrupt_handler(void)
+{
+    __asm volatile("addi sp,sp,-8");
+    __asm volatile("csrr a0,mcause");
+    __asm volatile("csrr a1,mepc");
+    __asm volatile("sw a0,4(sp)");
+    __asm volatile("sw a1,0(sp)");
+    __asm volatile("csrsi mstatus,8");
+    interrupt_entry();
+    __asm volatile("csrci mstatus,8");
+    __asm volatile("lw a1,0(sp)");
+    __asm volatile("lw a0,4(sp)");
+    __asm volatile("csrw mepc,a1");
+    __asm volatile("csrw mcause,a0");
+    __asm volatile("addi sp,sp,8");
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S
new file mode 100755
index 0000000000..d1b331cb04
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start.S
@@ -0,0 +1,96 @@
+/* Copyright 2018 SiFive, Inc */
+/* SPDX-License-Identifier: Apache-2.0 */
+#include 
+
+/* This code executes before _start, which is contained inside the C library.
+ * In embedded systems we want to ensure that _enter, which contains the first
+ * code to be executed, can be loaded at a specific address.  To enable this
+ * feature we provide the '.text.metal.init.enter' section, which is
+ * defined to have the first address being where execution should start. */
+    .section .init
+    .global __start
+    .type   __start, %function
+__start:
+    .cfi_startproc
+
+    /* Inform the debugger that there is nowhere to backtrace past _enter. */
+    .cfi_undefined ra
+
+    /* The absolute first thing that must happen is configuring the global
+     * pointer register, which must be done with relaxation disabled because
+     * it's not valid to obtain the address of any symbol without GP
+     * configured.  The C environment might go ahead and do this again, but
+     * that's safe as it's a fixed register. */
+.option push
+.option norelax
+    la gp, __global_pointer$
+.option pop
+
+    /* Disable global interrupt */
+    csrci mstatus,8
+
+    /* Set up a simple trap vector to catch anything that goes wrong early in
+     * the boot process. */
+    la t0, default_trap_handler
+    # /* enable CLIC Vectored mode */
+    ori	t0,t0,3
+    csrw mtvec, t0
+    /* enable chicken bit if core is bullet series*/
+    la t0, __metal_chicken_bit
+    beqz t0, 1f
+    csrwi 0x7C1, 0
+1:
+
+    /* There may be pre-initialization routines inside the MBI code that run in
+     * C, so here we set up a C environment.  First we set up a stack pointer,
+     * which is left as a weak reference in order to allow initialization
+     * routines that do not need a stack to be set up to transparently be
+     * called. */
+    .weak __StackTop
+    la sp, __StackTop
+
+    /* Intial the mtvt, MUST BE 64 bytes aligned*/
+    .weak __Vectors
+    la t0, __Vectors
+    csrw mtvt, t0
+
+#ifdef __riscv_float_abi_single
+    /* deal with FP */
+    /* Is F extension present? */
+    csrr t0, misa
+    andi t0, t0, (1 << ('F' - 'A'))
+    beqz t0, 1f
+    /* If so, enable it */
+    li t0, MSTATUS_FS
+    csrs mstatus, t0
+    fssr x0
+1:
+#endif
+
+    /* Check for an initialization routine and call it if one exists, otherwise
+     * just skip over the call entirely.   Note that __metal_initialize isn't
+     * actually a full C function, as it doesn't end up with the .bss or .data
+     * segments having been initialized.  This is done to avoid putting a
+     * burden on systems that can be initialized without having a C environment
+     * set up. */
+    jal SystemInit
+
+    /* start load code to itcm like. */
+    jal start_load
+
+    jal System_Post_Init
+
+    /* At this point we can enter the C runtime's startup file.  The arguments
+     * to this function are designed to match those provided to the SEE, just
+     * so we don't have to write another ABI. */
+    csrr a0, mhartid
+    li a1, 0
+    li a2, 0
+    jal entry
+
+    csrci mstatus, (1 << 3)
+
+__exit:
+    j __exit
+
+    .cfi_endproc
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/start_load.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start_load.c
old mode 100644
new mode 100755
similarity index 70%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/start_load.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start_load.c
index fea62fabb3..b09830c474
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/start_load.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/start_load.c
@@ -1,6 +1,27 @@
+/**
+ * @file start_load.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
 #include 
-#include "bl808_glb.h"
-#include 
 
 #define __STARTUP_CLEAR_BSS 1
 
@@ -18,8 +39,6 @@ extern uint32_t __tcm_code_start__;
 extern uint32_t __tcm_code_end__;
 extern uint32_t __tcm_data_start__;
 extern uint32_t __tcm_data_end__;
-extern uint32_t __system_ram_data_start__;
-extern uint32_t __system_ram_data_end__;
 extern uint32_t __ram_data_start__;
 extern uint32_t __ram_data_end__;
 extern uint32_t __bss_start__;
@@ -37,10 +56,6 @@ extern uint32_t __HeapLimit;
 //extern uint32_t __zero_table_start__;
 //extern uint32_t __zero_table_end__;
 
-#if defined(DUAL_CORE)
-volatile uintptr_t ATTR_MP_SHARE_DATA_SECTION master_copy_done = 0;
-#endif
-
 void start_load(void)
 {
     uint32_t *pSrc, *pDest;
@@ -62,14 +77,6 @@ void start_load(void)
         *pDest++ = *pSrc++;
     }
 
-    /* BF Add system RAM data copy */
-    pSrc = &__system_ram_load_addr;
-    pDest = &__system_ram_data_start__;
-
-    for (; pDest < &__system_ram_data_end__;) {
-        *pDest++ = *pSrc++;
-    }
-
     /* BF Add OCARAM data copy */
     pSrc = &__ram_load_addr;
     pDest = &__ram_data_start__;
@@ -94,16 +101,4 @@ void start_load(void)
     }
 
 #endif
-
-    csi_dcache_clean();
-
-#if defined(DUAL_CORE)
-    __DSB();
-
-    if (GLB_CORE_ID_D0 == GLB_Get_Core_Type()) {
-        master_copy_done = 0xDEAD5501;
-    }
-
-    __DSB();
-#endif
-}
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/system_bl602.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/system_bl602.c
new file mode 100755
index 0000000000..f6b95a4510
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl602/std/startup/system_bl602.c
@@ -0,0 +1,79 @@
+/**
+ * @file system_bl702.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bl602_glb.h"
+#include 
+
+void SystemInit(void)
+{
+    uint32_t *p;
+    uint8_t i;
+    uint32_t tmpVal = 0;
+
+    /* global IRQ disable */
+    __disable_irq();
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal |= (1 << 8);      /*mask pds wakeup*/
+    tmpVal |= (1 << 10);     /*mask rf done*/
+    tmpVal |= (1 << 11);     /*mask pll done*/
+    tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    /* GLB_Set_EM_Sel(GLB_EM_0KB); */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); //GLB_EM_0KB
+    BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
+
+    /* Restore default setting*/
+    /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, 0x00); //UART_SIG_SWAP_NONE
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    /* CLear all interrupt */
+    p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIE_OFFSET);
+
+    for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+        p[i] = 0;
+    }
+
+    p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET);
+
+    for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+        p[i] = 0;
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff);
+
+    /* init bor for all platform */
+    // HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ };
+    // HBN_Set_BOR_Cfg(&borCfg);
+}
+
+void System_Post_Init(void)
+{
+    PDS_Trim_RC32M();
+    HBN_Trim_RC32K();
+    /* global IRQ enable */
+    __enable_irq();
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/SConscript
new file mode 100755
index 0000000000..f6c702ff1c
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/SConscript
@@ -0,0 +1,54 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = []
+
+CPPPATH = [cwd]
+CPPDEFINES = []
+
+src += Split("""
+    std/startup/start.S
+    std/startup/vector.S
+    std/startup/riscv_fpu.S
+    std/startup/start_load.c
+    std/startup/system_bl616.c
+    std/startup/interrupt.c
+""")
+
+src += Split("""
+    std/src/bl616_common.c
+    std/src/bl616_ef_cfg.c
+    std/src/bl616_sdh.c
+    std/src/bl616_tzc_sec.c
+    std/src/bl616_psram.c
+    std/src/bl616_aon.c
+    std/src/bl616_pm.c
+""")
+src += ['std/port/bl616_clock.c']
+
+CPPPATH += [cwd + r'/std/include',
+        cwd + r'/std/include/hardware']
+
+if GetDepend('BSP_USING_ROMAPI'):
+    src += Split("""
+        std/src/bl616_romapi_e907.c
+        std/src/bl616_romapi_patch.c
+    """)
+    CPPDEFINES += ['BFLB_USE_ROM_DRIVER']
+else:
+    src += Split("""
+        std/src/bl616_clock.c
+        std/src/bl616_glb_gpio.c
+        std/src/bl616_glb.c
+        std/src/bl616_hbn.c
+        std/src/bl616_l1c.c
+        std/src/bl616_pds.c
+    """)
+
+CPPDEFINES += ['CONFIG_IRQ_NUM=80', 'BFLB_USE_HAL_DRIVER', 'BL616', 'default_interrupt_handler=SW_handler']
+LOCAL_CFLAGS = ' -DARCH_RISCV'
+group = DefineGroup('bl616', src, depend = ['BSP_USING_BL61X'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_acomp.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h
old mode 100644
new mode 100755
similarity index 97%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_acomp.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h
index 7f2aa8fd86..f6b87526fa
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_acomp.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_acomp.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_acomp.h
+  * @file    wb03_acomp.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,13 +33,13 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_ACOMP_H__
-#define __BL808_ACOMP_H__
+#ifndef __WB03_ACOMP_H__
+#define __WB03_ACOMP_H__
 
 #include "aon_reg.h"
-#include "bl808_common.h"
+#include "bl616_common.h"
 
-/** @addtogroup  BL808_Peripheral_Driver
+/** @addtogroup  BL606P_Peripheral_Driver
  *  @{
  */
 
@@ -209,6 +209,6 @@ BL_Sts_Type AON_ACOMP_Get_Result(AON_ACOMP_ID_Type acompNo);
 
 /*@} end of group ACOMP */
 
-/*@} end of group BL808_Peripheral_Driver */
+/*@} end of group BL606P_Peripheral_Driver */
 
-#endif /* __BL808_ACOMP_H__ */
+#endif /* __BL606P_ACOMP_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_aon.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_aon.h
new file mode 100755
index 0000000000..f7b35968e0
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_aon.h
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    bl616_aon.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_AON_H__
+#define __BL616_AON_H__
+
+#include "aon_reg.h"
+#include "glb_reg.h"
+#include "hbn_reg.h"
+#include "pds_reg.h"
+#include "bl616_ef_cfg.h"
+#include "bl616_common.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Public_Types
+ *  @{
+ */
+
+/*@} end of group AON_Public_Types */
+
+/** @defgroup  AON_Public_Constants
+ *  @{
+ */
+
+/*@} end of group AON_Public_Constants */
+
+/** @defgroup  AON_Public_Macros
+ *  @{
+ */
+
+/*@} end of group AON_Public_Macros */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+/*----------*/
+BL_Err_Type AON_Power_On_MBG(void);
+BL_Err_Type AON_Power_Off_MBG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_XTAL(void);
+BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut);
+uint8_t AON_Get_Xtal_CapCode(void);
+BL_Err_Type AON_Power_Off_XTAL(void);
+/*----------*/
+BL_Err_Type AON_Power_On_BG(void);
+BL_Err_Type AON_Power_Off_BG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO15_RF(void);
+BL_Err_Type AON_Power_Off_LDO15_RF(void);
+BL_Err_Type AON_Output_Float_LDO15_RF(void);
+BL_Err_Type AON_Output_Pulldown_LDO15_RF(void);
+/*----------*/
+BL_Err_Type AON_Power_On_SFReg(void);
+BL_Err_Type AON_Power_Off_SFReg(void);
+/*----------*/
+BL_Err_Type AON_Power_On_MicBias(void);
+BL_Err_Type AON_Power_Off_MicBias(void);
+/*----------*/
+BL_Err_Type AON_LowPower_Enter_PDS0(void);
+BL_Err_Type AON_LowPower_Exit_PDS0(void);
+/*----------*/
+BL_Err_Type AON_Trim_DcdcDis(void);
+BL_Err_Type AON_Trim_DcdcVoutSel(void);
+BL_Err_Type AON_Trim_DcdcVoutTrim(void);
+BL_Err_Type AON_Trim_Ldo11socVoutTrim(void);
+BL_Err_Type AON_Trim_Usb20RcalCode(void);
+/*----------*/
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_AON_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h
new file mode 100755
index 0000000000..29a70e03db
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_clock.h
@@ -0,0 +1,196 @@
+/**
+  ******************************************************************************
+  * @file    bl616_clock.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_CLOCK_H__
+#define __BL616_CLOCK_H__
+
+#include "glb_reg.h"
+#include "mcu_misc_reg.h"
+#include "pds_reg.h"
+#include "bl616_glb.h"
+#include "bl616_hbn.h"
+#include "bl616_common.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief System clock type definition
+ */
+typedef enum {
+    BL_SYSTEM_CLOCK_MCU_ROOT_CLK, /*!< MCU root clock */
+    BL_SYSTEM_CLOCK_MCU_CLK,      /*!< MCU Fast clock/CPU clock */
+    BL_SYSTEM_CLOCK_MCU_BCLK,     /*!< MCU BUS clock */
+    BL_SYSTEM_CLOCK_MCU_PBCLK,    /*!< MCU peri BUS clock */
+    BL_SYSTEM_CLOCK_F32K,         /*!< F32K clock */
+    BL_SYSTEM_CLOCK_XCLK,         /*!< XCLK:RC32M or XTAL */
+    BL_SYSTEM_CLOCK_XTAL,         /*!< XTAL clock */
+    BL_SYSTEM_CLOCK_MAX,          /*!< MAX type of system clock */
+} BL_System_Clock_Type;
+
+typedef enum {
+    BL_MTIMER_SOURCE_CLOCK_MCU_XCLK,     /*!< MCU xclk clock */
+    BL_MTIMER_SOURCE_CLOCK_MCU_CLK,      /*!< MCU root clock */
+} BL_MTimer_Source_Clock_Type;
+
+/**
+ *  @brief SOC clock config type
+ */
+typedef struct
+{
+    uint32_t magic;                              /*!< Clock config magic */
+    uint32_t systemClock[BL_SYSTEM_CLOCK_MAX];   /*!< System lock value */
+    uint32_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */
+    uint32_t i2sClock;                           /*!< I2S clock */
+} Clock_Cfg_Type;
+
+typedef enum {
+    CLOCK_AUPLL_DIV1,
+    CLOCK_AUPLL_DIV2,
+    CLOCK_AUPLL_DIV2P5,
+    CLOCK_AUPLL_DIV3,
+    CLOCK_AUPLL_DIV4,
+    CLOCK_AUPLL_DIV5,
+    CLOCK_AUPLL_DIV6,
+    CLOCK_AUPLL_DIV10,
+    CLOCK_AUPLL_DIV15,
+} CLOCK_AUPLL_Type;
+/**
+ *  @brief Peripheral clock type definition
+ */
+typedef enum {
+    BL_PERIPHERAL_CLOCK_UART0,       /*!< UART0 clock */
+    BL_PERIPHERAL_CLOCK_UART1,       /*!< UART1 clock */
+    BL_PERIPHERAL_CLOCK_UART2,       /*!< UART2 clock */
+    BL_PERIPHERAL_CLOCK_SPI,         /*!< SPI clock */
+    BL_PERIPHERAL_CLOCK_PEC,         /*!< PEC clock */
+    BL_PERIPHERAL_CLOCK_DBI,         /*!< DBI clock */
+    BL_PERIPHERAL_CLOCK_EMI,         /*!< EMI clock */
+    BL_PERIPHERAL_CLOCK_ISP,         /*!< ISP clock */
+    BL_PERIPHERAL_CLOCK_I2C0,        /*!< I2C0 clock */
+    BL_PERIPHERAL_CLOCK_I2C1,        /*!< I2C1 clock */
+    BL_PERIPHERAL_CLOCK_PSRAMB,      /*!< PSRAMB clock */
+    BL_PERIPHERAL_CLOCK_FLASH,       /*!< FLASH clock */
+    BL_PERIPHERAL_CLOCK_I2S,         /*!< I2S clock */
+    BL_PERIPHERAL_CLOCK_IR,          /*!< IR clock */
+    BL_PERIPHERAL_CLOCK_ADC,         /*!< ADC clock */
+    BL_PERIPHERAL_CLOCK_GPADC,       /*!< GPADC clock */
+    BL_PERIPHERAL_CLOCK_GPDAC,       /*!< GPDAC clock */
+    BL_PERIPHERAL_CLOCK_CAM,         /*!< CAM clock */
+    BL_PERIPHERAL_CLOCK_SDH,         /*!< SDH clock */
+    BL_PERIPHERAL_CLOCK_PKA,         /*!< PKA clock */
+    BL_PERIPHERAL_CLOCK_MAX,
+} BL_Peripheral_Type;
+
+/*@} end of group CLOCK_Public_Types */
+
+/** @defgroup  CLOCK_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  BL_SYSTEM_CLOCK_TYPE
+ *  @{
+ */
+#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_MCU_ROOT_CLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_MCU_CLK) ||      \
+                                       ((type) == BL_SYSTEM_CLOCK_MCU_BCLK) ||     \
+                                       ((type) == BL_SYSTEM_CLOCK_MCU_PBCLK) ||    \
+                                       ((type) == BL_SYSTEM_CLOCK_DSP_ROOT_CLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_DSP_CLK) ||      \
+                                       ((type) == BL_SYSTEM_CLOCK_DSP_BCLK) ||     \
+                                       ((type) == BL_SYSTEM_CLOCK_DSP_PBCLK) ||    \
+                                       ((type) == BL_SYSTEM_CLOCK_LP_CLK) ||       \
+                                       ((type) == BL_SYSTEM_CLOCK_F32K) ||         \
+                                       ((type) == BL_SYSTEM_CLOCK_XCLK) ||         \
+                                       ((type) == BL_SYSTEM_CLOCK_XTAL) ||         \
+                                       ((type) == BL_SYSTEM_CLOCK_MAX))
+
+/*@} end of group CLOCK_Public_Constants */
+
+/** @defgroup  CLOCK_Public_Macros
+ *  @{
+ */
+#define SYS_CLOCK_CFG_MAGIC (0x12345678)
+#define SYS_CLOCK_CFG_ADDR  (0x20010000 + 4 * 1024 - 512)
+
+/*@} end of group CLOCK_Public_Macros */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+/*----------*/
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type);
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type);
+uint32_t Clock_Audio_ADC_Clock_Get(void);
+uint32_t Clock_Audio_DAC_Clock_Get(void);
+/*----------*/
+uint32_t SystemCoreClockGet(void);
+/*----------*/
+BL_Err_Type CPU_Set_MTimer_RST(uint8_t rstEn);
+BL_Err_Type CPU_Reset_MTimer(void);
+BL_Err_Type CPU_Set_MTimer_CLK(uint8_t enable, BL_MTimer_Source_Clock_Type mTimerSourceClockType, uint16_t div);
+uint32_t CPU_Get_MTimer_Source_Clock(void);
+uint32_t CPU_Get_MTimer_Clock(void);
+uint64_t CPU_Get_MTimer_Counter(void);
+uint64_t CPU_Get_CPU_Cycle(void);
+uint64_t CPU_Get_MTimer_US(void);
+uint64_t CPU_Get_MTimer_MS(void);
+BL_Err_Type CPU_MTimer_Delay_US(uint32_t cnt);
+BL_Err_Type CPU_MTimer_Delay_MS(uint32_t cnt);
+uint32_t Clock_Get_EMI_Clk(void);
+uint32_t Clock_Get_ISP_Clk(void);
+uint32_t Clock_Get_BLAI_Clk(void);
+uint32_t Clock_Get_Display_Clk(void);
+uint32_t Clock_Get_PSRAMB_Clk(void);
+uint32_t Clock_Get_PSRAMB_Clk(void);
+uint32_t Clock_Get_H264_Clk(void);
+/*----------*/
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_CLOCK_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_common.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_common.h
new file mode 100755
index 0000000000..f6afff2c61
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_common.h
@@ -0,0 +1,186 @@
+#ifndef __BL616_COMMON_H__
+#define __BL616_COMMON_H__
+
+#include "bl616.h"
+#include "bflb_core.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  COMMON
+ *  @{
+ */
+
+/**
+ * @brief Memory access macro
+ */
+#define BL_RD_WORD(addr)       (*((volatile uint32_t *)(uintptr_t)(addr)))
+#define BL_WR_WORD(addr, val)  ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_SHORT(addr)      (*((volatile uint16_t *)(uintptr_t)(addr)))
+#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_BYTE(addr)       (*((volatile uint8_t *)(uintptr_t)(addr)))
+#define BL_WR_BYTE(addr, val)  ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val))
+#define BL_RDWD_FRM_BYTEP(p)   ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+
+#define BL_WRWD_TO_BYTEP(p, val)   \
+    {                              \
+        p[0] = val & 0xff;         \
+        p[1] = (val >> 8) & 0xff;  \
+        p[2] = (val >> 16) & 0xff; \
+        p[3] = (val >> 24) & 0xff; \
+    }
+/**
+ * @brief Register access macro
+ */
+#define BL_RD_REG16(addr, regname)                BL_RD_SHORT(addr + regname##_OFFSET)
+#define BL_WR_REG16(addr, regname, val)           BL_WR_SHORT(addr + regname##_OFFSET, val)
+#define BL_RD_REG(addr, regname)                  BL_RD_WORD(addr + regname##_OFFSET)
+#define BL_WR_REG(addr, regname, val)             BL_WR_WORD(addr + regname##_OFFSET, val)
+#define BL_SET_REG_BIT(val, bitname)              ((val) | (1U << bitname##_POS))
+#define BL_CLR_REG_BIT(val, bitname)              ((val)&bitname##_UMSK)
+#define BL_GET_REG_BITS_VAL(val, bitname)         (((val)&bitname##_MSK) >> bitname##_POS)
+#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
+#define BL_IS_REG_BIT_SET(val, bitname)           (((val) & (1U << (bitname##_POS))) != 0)
+#define BL_DRV_DUMMY           \
+    {                          \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+    }
+
+/** @defgroup  COMMON_Public_Types
+ *  @{
+ */
+#ifdef BIT
+#undef BIT
+#define BIT(n) (1UL << (n))
+#else
+#define BIT(n) (1UL << (n))
+#endif
+
+/**
+ * @brief Null Type definition
+ */
+#ifndef NULL
+#define NULL 0
+#endif
+
+/**
+ * @brief Error type definition
+ */
+typedef enum {
+    SUCCESS = 0,
+    ERROR = 1,
+    TIMEOUT = 2,
+    INVALID = 3, /* invalid arguments */
+    NORESC = 4   /* no resource or resource temperary unavailable */
+} BL_Err_Type;
+
+/**
+ * @brief Functional type definition
+ */
+typedef enum {
+    DISABLE = 0,
+    ENABLE = 1,
+} BL_Fun_Type;
+
+/**
+ * @brief Status type definition
+ */
+typedef enum {
+    RESET = 0,
+    SET = 1,
+} BL_Sts_Type;
+
+/**
+ * @brief Mask type definition
+ */
+typedef enum {
+    UNMASK = 0,
+    MASK = 1
+} BL_Mask_Type;
+
+/**
+ * @brief Logical status Type definition
+ */
+typedef enum {
+    LOGIC_LO = 0,
+    LOGIC_HI = !LOGIC_LO
+} LogicalStatus;
+
+/**
+ * @brief Active status Type definition
+ */
+typedef enum {
+    DEACTIVE = 0,
+    ACTIVE = !DEACTIVE
+} ActiveStatus;
+
+/**
+ *  @brief Interrupt callback function type
+ */
+typedef void(intCallback_Type)(void);
+typedef void (*pFunc)(void);
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr) ((void)0)
+#endif /* DEBUG */
+
+/*@} end of group COMMON_Public_Types */
+
+/** @defgroup  COMMON_Public_Constants
+ *  @{
+ */
+
+/** @defgroup DRIVER_INT_PERIPH
+ *  @{
+ */
+#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
+
+/*@} end of group DRIVER_INT_PERIPH */
+
+/** @defgroup DRIVER_INT_MASK
+ *  @{
+ */
+#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
+
+#define ARCH_MemCpy      arch_memcpy
+#define ARCH_MemSet      arch_memset
+#define ARCH_MemCmp      arch_memcmp
+#define ARCH_MemCpy4     arch_memcpy4
+#define arch_memcpy_fast arch_memcpy_fast
+#define ARCH_MemSet4     arch_memset4
+#define BFLB_Soft_CRC32  bflb_soft_crc32
+#define CPU_Interrupt_Enable(irq)
+#define CPU_Interrupt_Disable(irq)
+#define Interrupt_Handler_Register(irq, callback)
+/*@} end of group COMMON_Public_Constants */
+
+/** @defgroup DRIVER_Public_FunctionDeclaration
+ *  @brief DRIVER functions declaration
+ *  @{
+ */
+
+// void Interrupt_Handler_Register(IRQn_Type irq, pFunc interruptFun);
+void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT);
+void arch_delay_us(uint32_t cnt);
+void arch_delay_ms(uint32_t cnt);
+
+void *ARCH_MemCpy(void *dst, const void *src, uint32_t n);
+uint32_t *ARCH_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
+void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
+void *ARCH_MemSet(void *s, uint8_t c, uint32_t n);
+uint32_t *ARCH_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n);
+int ARCH_MemCmp(const void *s1, const void *s2, uint32_t n);
+
+void C906_All_Int_Enable(void);
+void C906_All_Int_Disable(void);
+
+/*@} end of group DRIVER_COMMON  */
+
+#endif /* __BL616_COMMON_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_cfg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_cfg.h
new file mode 100755
index 0000000000..34e5681b4d
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_cfg.h
@@ -0,0 +1,88 @@
+/**
+  ******************************************************************************
+  * @file    bl616_ef_cfg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_EF_CFG_H__
+#define __BL616_EF_CFG_H__
+
+#include "bflb_ef_ctrl.h"
+#include "bl616_common.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_Public_Types
+ *  @{
+ */
+
+typedef struct
+{
+    uint32_t rsvd       : 22; /*!< Reserved */
+    uint32_t deviceInfo : 2;  /*!< Efuse device information */
+    uint32_t psramInfo  : 2;  /*!< Efuse psram info 0:no psram, 1:WB 4MB*/
+    uint32_t memoryInfo : 3;  /*!< Efuse memory info 0:no memory, 1:2MB flash, 2:4MB flash, 3:6MB flash, 4:8MB flash */
+    uint32_t chipInfo   : 3;  /*!< Efuse chip revision */
+} bflb_efuse_device_info_type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
+ *  @{
+ */
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup  EF_CTRL_Public_Macros
+ *  @{
+ */
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup  EF_CTRL_Public_Functions
+ *  @{
+ */
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_EF_CFG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_ctrl.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_ctrl.h
new file mode 100755
index 0000000000..ebb32e8f50
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_ef_ctrl.h
@@ -0,0 +1,457 @@
+/**
+  ******************************************************************************
+  * @file    bl616_ef_ctrl.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_EF_CTRL_H__
+#define __BL616_EF_CTRL_H__
+
+#include "ef_ctrl_reg.h"
+#include "bl616_common.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Efuse Ctrl key slot type definition
+ */
+typedef enum {
+    EF_CTRL_KEY_SLOT0, /*!< key slot 0 */
+    EF_CTRL_KEY_SLOT1, /*!< key slot 1 */
+    EF_CTRL_KEY_SLOT2, /*!< key slot 2 */
+    EF_CTRL_KEY_SLOT3, /*!< key slot 3 */
+    EF_CTRL_KEY_SLOT4, /*!< key slot 4 */
+    EF_CTRL_KEY_SLOT5, /*!< key slot 5 */
+    EF_CTRL_KEY_MAX,   /*!<  */
+} EF_Ctrl_Key_Type;
+
+/**
+ *  @brief Efuse Ctrl sign type definition
+ */
+typedef enum {
+    EF_CTRL_SIGN_NONE, /*!< no sign */
+    EF_CTRL_SIGN_RSA,  /*!< use RSA to sign */
+    EF_CTRL_SIGN_ECC,  /*!< use ECC to sign */
+} EF_Ctrl_Sign_Type;
+
+/**
+ *  @brief Efuse Ctrl flash AES type definition
+ */
+typedef enum {
+    EF_CTRL_SF_AES_NONE, /*!< No AES */
+    EF_CTRL_SF_AES_128,  /*!< AES 128 */
+    EF_CTRL_SF_AES_192,  /*!< AES 192 */
+    EF_CTRL_SF_AES_256,  /*!< AES 256 */
+} EF_Ctrl_SF_AES_Type;
+
+/**
+ *  @brief Efuse Ctrl Dbg type definition
+ */
+typedef enum {
+    EF_CTRL_DBG_OPEN = 0,  /*!< Open debug */
+    EF_CTRL_DBG_PASSWORD,  /*!< Open debug with password */
+    EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */
+} EF_Ctrl_Dbg_Mode_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_EF_CLK,   /*!< Select efuse clock */
+    EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */
+} EF_Ctrl_CLK_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_PARA_DFT,    /*!< Select default cyc parameter */
+    EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */
+} EF_Ctrl_CYC_PARA_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_OP_MODE_AUTO,   /*!< Select efuse program auto mode */
+    EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */
+} EF_Ctrl_OP_MODE_Type;
+
+/**
+ *  @brief Efuse Ctrl secure configuration structure type definition
+ */
+typedef struct
+{
+    EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */
+    uint8_t ef_dbg_jtag_0_dis;         /*!< Jtag debug disable config value */
+    uint8_t ef_dbg_jtag_1_dis;         /*!< Jtag debug disable config value */
+    uint8_t ef_sboot_en;               /*!< Secure boot enable config value */
+} EF_Ctrl_Sec_Param_Type;
+
+/**
+ *  @brief Efuse analog DcdcDis type definition
+ */
+typedef struct
+{
+    uint32_t dcdcDisAonEn     : 1;  /*!< Efuse analog dcdc_dis_aon_en */
+    uint32_t dcdcDisAonParity : 1;  /*!< Efuse analog dcdc_dis_aon_parity */
+    uint32_t dcdcDisAon       : 1;  /*!< Efuse analog dcdc_dis_aon */
+    uint32_t reserved         : 29; /*!< Efuse analog reserved */
+} Efuse_Ana_DcdcDis_Type;
+
+/**
+ *  @brief Efuse analog DcdcVoutSel type definition
+ */
+typedef struct
+{
+    uint32_t dcdcVoutSelAonEn     : 1;  /*!< Efuse analog dcdc_vout_sel_aon_en */
+    uint32_t dcdcVoutSelAonParity : 1;  /*!< Efuse analog dcdc_vout_sel_aon_parity */
+    uint32_t dcdcVoutSelAon       : 5;  /*!< Efuse analog dcdc_vout_sel_aon[4:0] */
+    uint32_t reserved             : 25; /*!< Efuse analog reserved */
+} Efuse_Ana_DcdcVoutSel_Type;
+
+/**
+ *  @brief Efuse analog Ldo18ioVoutSel type definition
+ */
+typedef struct
+{
+    uint32_t ldo18ioVoutSelEn     : 1;  /*!< Efuse analog ldo18io_vout_sel_en */
+    uint32_t ldo18ioVoutSelParity : 1;  /*!< Efuse analog ldo18io_vout_sel_parity */
+    uint32_t ldo18ioVoutSelAon    : 4;  /*!< Efuse analog ldo18io_vout_sel_aon[3:0] */
+    uint32_t reserved             : 26; /*!< Efuse analog reserved */
+} Efuse_Ana_Ldo18ioVoutSel_Type;
+
+/**
+ *  @brief Efuse analog Ldo18ioBypass type definition
+ */
+typedef struct
+{
+    uint32_t ldo18ioBypassEn     : 1;  /*!< Efuse analog ldo18io_bypass_en */
+    uint32_t ldo18ioBypassParity : 1;  /*!< Efuse analog ldo18io_bypass_parity */
+    uint32_t ldo18ioBypassAon    : 1;  /*!< Efuse analog ldo18io_bypass_aon */
+    uint32_t reserved            : 29; /*!< Efuse analog reserved */
+} Efuse_Ana_Ldo18ioBypass_Type;
+
+/**
+ *  @brief Efuse analog Ldo33VoutTrim type definition
+ */
+typedef struct
+{
+    uint32_t ldo33VoutTrimAonEn     : 1;  /*!< Efuse analog ldo33_vout_trim_aon_en */
+    uint32_t ldo33VoutTrimAonParity : 1;  /*!< Efuse analog ldo33_vout_trim_aon_parity */
+    uint32_t ldo33VoutTrimAon       : 4;  /*!< Efuse analog ldo33_vout_trim_aon[3:0] */
+    uint32_t reserved               : 26; /*!< Efuse analog reserved */
+} Efuse_Ana_Ldo33VoutTrim_Type;
+
+/**
+ *  @brief Efuse analog Ldo18ioVoutTrim type definition
+ */
+typedef struct
+{
+    uint32_t ldo18ioVoutTrimEn     : 1;  /*!< Efuse analog ldo18io_vout_trim_en */
+    uint32_t ldo18ioVoutTrimParity : 1;  /*!< Efuse analog ldo18io_vout_trim_parity */
+    uint32_t ldo18ioVoutTrimAon    : 4;  /*!< Efuse analog ldo18io_vout_trim_aon[3:0] */
+    uint32_t reserved              : 26; /*!< Efuse analog reserved */
+} Efuse_Ana_Ldo18ioVoutTrim_Type;
+
+/**
+ *  @brief Efuse analog DcdcVoutTrim type definition
+ */
+typedef struct
+{
+    uint32_t dcdcVoutTrimAonEn     : 1;  /*!< Efuse analog dcdc_vout_trim_aon_en */
+    uint32_t dcdcVoutTrimAonParity : 1;  /*!< Efuse analog dcdc_vout_trim_aon_parity */
+    uint32_t dcdcVoutTrimAon       : 4;  /*!< Efuse analog dcdc_vout_trim_aon[3:0] */
+    uint32_t reserved              : 26; /*!< Efuse analog reserved */
+} Efuse_Ana_DcdcVoutTrim_Type;
+
+/**
+ *  @brief Efuse analog Ldo11socVoutTrim type definition
+ */
+typedef struct
+{
+    uint32_t ldo11socVoutTrimAonEn   : 1;  /*!< Efuse analog ldo11soc_vout_trim_aon_en */
+    uint32_t ldo11socVoutTrimAonTrim : 1;  /*!< Efuse analog ldo11soc_vout_trim_aon_trim */
+    uint32_t ldo11socVoutTrimAon     : 4;  /*!< Efuse analog ldo11soc_vout_trim_aon[3:0] */
+    uint32_t reserved                : 26; /*!< Efuse analog reserved */
+} Efuse_Ana_Ldo11socVoutTrim_Type;
+
+/**
+ *  @brief Efuse analog RC32M trim type definition
+ */
+typedef struct
+{
+    uint32_t rc32mCodeFrExt2En     : 1;  /*!< Efuse analog rc32m_code_fr_ext2_en */
+    uint32_t rc32mCodeFrExt2Parity : 1;  /*!< Efuse analog rc32m_code_fr_ext2_parity */
+    uint32_t rc32mCodeFrExt2       : 8;  /*!< Efuse analog rc32m_code_fr_ext2[7:0] */
+    uint32_t reserved              : 22; /*!< Efuse analog reserved */
+} Efuse_Ana_RC32M_Trim_Type;
+
+/**
+ *  @brief Efuse analog RC32K trim type definition
+ */
+typedef struct
+{
+    uint32_t rc32kCodeFrExtEn     : 1;  /*!< Efuse analog rc32k_code_fr_ext_en */
+    uint32_t rc32kCodeFrExtParity : 1;  /*!< Efuse analog rc32k_code_fr_ext_parity */
+    uint32_t rc32kCodeFrExt       : 10; /*!< Efuse analog rc32k_code_fr_ext[9:0] */
+    uint32_t reserved             : 20; /*!< Efuse analog reserved */
+} Efuse_Ana_RC32K_Trim_Type;
+
+/**
+ *  @brief Efuse analog Usb20RcalCode type definition
+ */
+typedef struct
+{
+    uint32_t usb20RcalCodeAonEn     : 1;  /*!< Efuse analog usb20_rcal_code_aon_en */
+    uint32_t usb20RcalCodeAonParity : 1;  /*!< Efuse analog usb20_rcal_code_aon_parity */
+    uint32_t usb20RcalCodeAon       : 6;  /*!< Efuse analog usb20_rcal_code_aon[5:0] */
+    uint32_t reserved               : 24; /*!< Efuse analog reserved */
+} Efuse_Ana_Usb20RcalCode_Type;
+
+/**
+ *  @brief Efuse analog TSEN trim type definition
+ */
+typedef struct
+{
+    uint32_t tsenRefcodeCorner        : 12; /*!< TSEN refcode */
+    uint32_t tsenRefcodeCornerParity  : 1;  /*!< TSEN refcode parity */
+    uint32_t tsenRefcodeCornerEn      : 1;  /*!< TSEN refcode enable */
+    uint32_t tsenRefcodeCornerVersion : 1;  /*!< TSEN refcode version */
+    uint32_t reserved                 : 17; /*!< TSEN analog trim:reserved */
+} Efuse_TSEN_Refcode_Corner_Type;
+
+/**
+ *  @brief Efuse analog ADC Gain trim type definition
+ */
+typedef struct
+{
+    uint32_t adcGainCoeff       : 12; /*!< ADC gain coeff */
+    uint32_t adcGainCoeffParity : 1;  /*!< ADC gain coeff parity */
+    uint32_t adcGainCoeffEn     : 1;  /*!< ADC gain coeff enable */
+    uint32_t reserved           : 18; /*!< ADC gain coeff:reserved */
+} Efuse_ADC_Gain_Coeff_Type;
+
+/**
+ *  @brief Efuse analog device info type definition
+ */
+typedef struct
+{
+    uint32_t rsvd       : 22; /*!< Reserved */
+    uint32_t deviceInfo : 2;  /*!< Efuse device information */
+    uint32_t psramInfo  : 2;  /*!< Efuse psram info 0:no psram, 1:WB 4MB*/
+    uint32_t memoryInfo : 3;  /*!< Efuse memory info 0:no memory, 8:1MB flash */
+    uint32_t chipInfo   : 3;  /*!< Efuse chip revision */
+} Efuse_Device_Info_Type;
+
+/**
+ *  @brief Efuse Capcode type definition
+ */
+typedef struct
+{
+    uint32_t capCode : 6;  /*!< Cap code value */
+    uint32_t parity  : 1;  /*!< Parity of capcode */
+    uint32_t en      : 1;  /*!< Enable status */
+    uint32_t rsvd    : 24; /*!< Reserved */
+} Efuse_Capcode_Info_Type;
+
+/**
+ *  @brief Efuse common trim config definition
+ */
+typedef struct
+{
+    char *name;           /*!< trim anme */
+    uint16_t en_addr;     /*!< enable address */
+    uint16_t parity_addr; /*!< parity address */
+    uint16_t value_addr;  /*!< value address */
+    uint16_t value_len;   /*!< value length */
+} Efuse_Common_Trim_Cfg;
+
+/**
+ *  @brief Efuse common trim type definition
+ */
+typedef struct
+{
+    uint8_t en;     /*!< Enable status */
+    uint8_t parity; /*!< Trim parity */
+    uint8_t empty;  /*!< Trim empty */
+    uint8_t len;    /*!< Trim value len in bit */
+    uint32_t value; /*!< Trim value */
+} Efuse_Common_Trim_Type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_KEY_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \
+                                   ((type) == EF_CTRL_KEY_SLOT1) || \
+                                   ((type) == EF_CTRL_KEY_SLOT2) || \
+                                   ((type) == EF_CTRL_KEY_SLOT3) || \
+                                   ((type) == EF_CTRL_KEY_SLOT4) || \
+                                   ((type) == EF_CTRL_KEY_SLOT5) || \
+                                   ((type) == EF_CTRL_KEY_MAX))
+
+/** @defgroup  EF_CTRL_SIGN_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \
+                                    ((type) == EF_CTRL_SIGN_RSA) ||  \
+                                    ((type) == EF_CTRL_SIGN_ECC))
+
+/** @defgroup  EF_CTRL_SF_AES_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \
+                                      ((type) == EF_CTRL_SF_AES_128) ||  \
+                                      ((type) == EF_CTRL_SF_AES_192) ||  \
+                                      ((type) == EF_CTRL_SF_AES_256))
+
+/** @defgroup  EF_CTRL_DBG_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) ||     \
+                                        ((type) == EF_CTRL_DBG_PASSWORD) || \
+                                        ((type) == EF_CTRL_DBG_CLOSE))
+
+/** @defgroup  EF_CTRL_CLK_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \
+                                   ((type) == EF_CTRL_SAHB_CLK))
+
+/** @defgroup  EF_CTRL_CYC_PARA_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \
+                                        ((type) == EF_CTRL_PARA_MANUAL))
+
+/** @defgroup  EF_CTRL_OP_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \
+                                       ((type) == EF_CTRL_OP_MODE_MANUAL))
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup  EF_CTRL_Public_Macros
+ *  @{
+ */
+#define EF_CTRL_EFUSE_R0_SIZE (128 * 4)
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup  EF_CTRL_Public_Functions
+ *  @{
+ */
+/*----------*/
+BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]);
+/*----------*/
+void EF_Ctrl_Load_Efuse_R0(void);
+void EF_Ctrl_Program_Efuse_0(void);
+BL_Sts_Type EF_Ctrl_Busy(void);
+BL_Sts_Type EF_Ctrl_AutoLoad_Done(void);
+void EF_Ctrl_Write_Dbg_Pwd(uint8_t slot, uint32_t passWdLow, uint32_t passWdHigh, uint8_t program);
+void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh);
+void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program);
+void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg);
+void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program);
+void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_SF_AES_Type aes[2]);
+BL_Fun_Type EF_Ctrl_Read_Bus_Remap(void);
+void EF_Ctrl_Set_sf_key_re_sel(uint8_t ef_sf_key_re_sel);
+/*----------*/
+uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len);
+void EF_Ctrl_Read_DcdcDis_Trim(Efuse_Ana_DcdcDis_Type *trim);
+void EF_Ctrl_Read_DcdcVoutSel_Trim(Efuse_Ana_DcdcVoutSel_Type *trim);
+void EF_Ctrl_Read_Ldo18ioVoutSel_Trim(Efuse_Ana_Ldo18ioVoutSel_Type *trim);
+void EF_Ctrl_Read_Ldo18ioBypass_Trim(Efuse_Ana_Ldo18ioBypass_Type *trim);
+void EF_Ctrl_Read_Ldo33VoutTrim_Trim(Efuse_Ana_Ldo33VoutTrim_Type *trim);
+void EF_Ctrl_Read_Ldo18ioVoutTrim_Trim(Efuse_Ana_Ldo18ioVoutTrim_Type *trim);
+void EF_Ctrl_Read_DcdcVoutTrim_Trim(Efuse_Ana_DcdcVoutTrim_Type *trim);
+void EF_Ctrl_Read_Ldo11socVoutTrim_Trim(Efuse_Ana_Ldo11socVoutTrim_Type *trim);
+void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim);
+void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim);
+void EF_Ctrl_Read_Usb20RcalCode_Trim(Efuse_Ana_Usb20RcalCode_Type *trim);
+/*----------*/
+void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim);
+void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim);
+void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program);
+void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage);
+void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program);
+void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[6]);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
+BL_Err_Type EF_Ctrl_Read_ZiggBee_MAC_Address(uint8_t mac[8]);
+void EF_Ctrl_Writelock_MAC_Address(uint8_t program);
+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
+void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program);
+void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
+void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Program_Direct(uint32_t offset, uint32_t *data, uint32_t len);
+void EF_Ctrl_Read_Direct(uint32_t offset, uint32_t *data, uint32_t len);
+void EF_Ctrl_Clear(uint32_t index, uint32_t len);
+void EF_Ctrl_Crc_Enable(void);
+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
+void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue);
+BL_Err_Type EF_Ctrl_Crc_Result(void);
+void EF_Ctrl_Sw_AHB_Clk_0(void);
+uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len);
+uint8_t EF_Ctrl_Read_FlashDlyCoe(void);
+
+uint32_t EF_Ctrl_Get_Common_Trim_List(Efuse_Common_Trim_Cfg **trim_list);
+void EF_Ctrl_Read_Common_Trim(char *name, Efuse_Common_Trim_Type *trim, uint8_t reload);
+void EF_Ctrl_Write_Common_Trim(char *name, uint32_t value, uint8_t program);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_EF_CTRL_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h
new file mode 100755
index 0000000000..21052332e0
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_glb.h
@@ -0,0 +1,1748 @@
+/**
+  ******************************************************************************
+  * @file    bl616_glb.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_GLB_H__
+#define __BL616_GLB_H__
+
+#include "glb_reg.h"
+#include "cci_reg.h"
+#include "mm_glb_reg.h"
+#include "pds_reg.h"
+#include "bl616_gpio.h"
+#include "bl616_hbn.h"
+#include "bl616_aon.h"
+#include "bl616_pds.h"
+#include "bl616_common.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief GLB core ID type definition
+ */
+typedef enum {
+    GLB_CORE_ID_M0,      /*!< M0 */
+    GLB_CORE_ID_MAX,     /*!< ID max */
+    GLB_CORE_ID_INVALID, /*!< ID invalid */
+} GLB_CORE_ID_Type;
+
+/**
+ *  @brief cci ID type definition
+ */
+typedef enum {
+    CCI0_ID,    /*!< CCI0 port define */
+    CCI_ID_MAX, /*!< CCI MAX ID define */
+} CCI_ID_Type;
+
+/**
+ *  @brief GLB MCU all interrupt type definition
+ */
+typedef enum {
+    GLB_MCU_ALL_INT_BMX_ERR_INT = 0,                       /*!< bmx_err_intmcu_dec_err_int */
+    GLB_MCU_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT = 1,   /*!< bmx_timeout_intmcu_timeout_int */
+    GLB_MCU_ALL_INT_IPC0_NP2AP_IRQ = 2,                    /*!< ipc0_np2ap_irq */
+    GLB_MCU_ALL_INT_IPC0_AP2NP_IRQ = 3,                    /*!< ipc0_ap2np_irq */
+    GLB_MCU_ALL_INT_AUDIO_INT = 4,                         /*!< audio_int */
+    GLB_MCU_ALL_INT_RF_TOP_INT_0 = 5,                      /*!< rf_top_int[0] */
+    GLB_MCU_ALL_INT_RF_TOP_INT_1 = 6,                      /*!< rf_top_int[1] */
+    GLB_MCU_ALL_INT_LZ4_INT = 7,                           /*!< lz4_int */
+    GLB_MCU_ALL_INT_RSV8 = 8,                              /*!< rsv8 */
+    GLB_MCU_ALL_INT_SEC_ENG_ID0_GMAC_INT = 9,              /*!< sec_eng_id0_gmac_int */
+    GLB_MCU_ALL_INT_SEC_ENG_ID0_CDET_INT = 10,             /*!< sec_eng_id0_cdet_int */
+    GLB_MCU_ALL_INT_SEC_ENG_ID0_PKA_INT = 11,              /*!< sec_eng_id0_pka_int */
+    GLB_MCU_ALL_INT_SEC_ENG_ID0_TRNG_INT = 12,             /*!< sec_eng_id0_trng_int */
+    GLB_MCU_ALL_INT_SEC_ENG_ID0_AES_INT = 13,              /*!< sec_eng_id0_aes_int */
+    GLB_MCU_ALL_INT_SEC_ENG_ID0_SHA_INT = 14,              /*!< sec_eng_id0_sha_int */
+    GLB_MCU_ALL_INT_DMA_INTR_ALL = 15,                     /*!< DMA_INTR_ALL */
+    GLB_MCU_ALL_INT_DMA2_INTR_ALL = 16,                    /*!< DMA2_INTR_ALL */
+    GLB_MCU_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1 = 17, /*!< sdh_mmc1_intsdh2pmu_wakeup_int1 */
+    GLB_MCU_ALL_INT_MM_IRQ_ALL = 18,                       /*!< mm_irq_all */
+    GLB_MCU_ALL_INT_IRTX_INT = 19,                         /*!< irtx_int */
+    GLB_MCU_ALL_INT_IRRX_INT = 20,                         /*!< irrx_int */
+    GLB_MCU_ALL_INT_USB_INT = 21,                          /*!< usb_int */
+    GLB_MCU_ALL_INT_AUPDM_INT = 22,                        /*!< aupdm_int */
+    GLB_MCU_ALL_INT_SF_CTRL_ID0_INT = 23,                  /*!< sf_ctrl_id0_int */
+    GLB_MCU_ALL_INT_EMAC_INT = 24,                         /*!< emac_int */
+    GLB_MCU_ALL_INT_GPADC_DMA_INT = 25,                    /*!< gpadc_dma_int */
+    GLB_MCU_ALL_INT_EFUSE_INT = 26,                        /*!< efuse_int */
+    GLB_MCU_ALL_INT_SPI_0_INT = 27,                        /*!< spi_0_int */
+    GLB_MCU_ALL_INT_UART_IRQ = 28,                         /*!< uart_irq */
+    GLB_MCU_ALL_INT_UART1_IRQ = 29,                        /*!< uart1_irq */
+    GLB_MCU_ALL_INT_UART2_IRQ = 30,                        /*!< uart2_irq */
+    GLB_MCU_ALL_INT_GPIO_DMA_INT = 31,                     /*!< gpio_dma_int */
+    GLB_MCU_ALL_INT_I2C_0_INT = 32,                        /*!< i2c_0_int */
+    GLB_MCU_ALL_INT_PWM_INT = 33,                          /*!< pwm_int */
+    GLB_MCU_ALL_INT_IPC1_NP2AP_IRQ = 34,                   /*!< ipc1_np2ap_irq */
+    GLB_MCU_ALL_INT_IPC1_AP2NP_IRQ = 35,                   /*!< ipc1_ap2np_irq */
+    GLB_MCU_ALL_INT_TIMER0_2_IRQ = 36,                     /*!< timer0_2_irq */
+    GLB_MCU_ALL_INT_TIMER0_3_IRQ = 37,                     /*!< timer0_3_irq */
+    GLB_MCU_ALL_INT_WDT0_IRQ = 38,                         /*!< wdt0_irq */
+    GLB_MCU_ALL_INT_I2C_1_INT = 39,                        /*!< i2c_1_int */
+    GLB_MCU_ALL_INT_I2S0_INT = 40,                         /*!< i2s0_int */
+    GLB_MCU_ALL_INT_RSV41 = 41,                            /*!< rsv41 */
+    GLB_MCU_ALL_INT_RSV42 = 42,                            /*!< rsv42 */
+    GLB_MCU_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ = 43,           /*!< ana_ocp_out_to_cpu_irq[2:0] */
+    GLB_MCU_ALL_INT_GPIO_IRQ = 44,                         /*!< gpio_irq */
+    GLB_MCU_ALL_INT_DM_IRQ = 45,                           /*!< dm_irq */
+    GLB_MCU_ALL_INT_BT_IRQ = 46,                           /*!< bt_irq */
+    GLB_MCU_ALL_INT_M154_REQ_ENH_ACK_INT = 47,             /*!< m154_req_enh_ack_int */
+    GLB_MCU_ALL_INT_M154_INT = 48,                         /*!< m154_int */
+    GLB_MCU_ALL_INT_M154_AES_INT = 49,                     /*!< m154_aes_int */
+    GLB_MCU_ALL_INT_PDS_INT = 50,                          /*!< pds_int */
+    GLB_MCU_ALL_INT_HBN_IRQ_OUT_0 = 51,                    /*!< hbn_irq_out[0] */
+    GLB_MCU_ALL_INT_HBN_IRQ_OUT_1 = 52,                    /*!< hbn_irq_out[1] */
+    GLB_MCU_ALL_INT_BOR_OUT = 53,                          /*!< bor_out */
+    GLB_MCU_ALL_INT_WIFI_TO_CPU_IRQ_N = 54,                /*!< wifi_to_cpu_irq_n */
+    GLB_MCU_ALL_INT_BZ_PHY_INT = 55,                       /*!< bz_phy_int */
+    GLB_MCU_ALL_INT_BLE_INT = 56,                          /*!< ble_int */
+    GLB_MCU_ALL_INT_MAC_INT_TX_RX_TIMER = 57,              /*!< mac_int_tx_rx_timer */
+    GLB_MCU_ALL_INT_MAC_INT_TX_RX_MISC = 58,               /*!< mac_int_tx_rx_misc */
+    GLB_MCU_ALL_INT_MAC_INT_RX_TRIGGER = 59,               /*!< mac_int_rx_trigger */
+    GLB_MCU_ALL_INT_MAC_INT_TX_TRIGGER = 60,               /*!< mac_int_tx_trigger */
+    GLB_MCU_ALL_INT_MAC_INT_GEN = 61,                      /*!< mac_int_gen */
+    GLB_MCU_ALL_INT_MAC_INT_PROT_TRIGGER = 62,             /*!< mac_int_prot_trigger */
+    GLB_MCU_ALL_INT_WIFI_IPC = 63,                         /*!< wifi_ipc */
+} GLB_MCU_ALL_INT_Type;
+
+/**
+ *  @brief GLB mcu muxpll 160M clock type definition
+ */
+typedef enum {
+    GLB_MCU_MUXPLL_SEL_WIFIPLL_160M,    /*!< mcu muxpll select wifipll 160M */
+    GLB_MCU_MUXPLL_SEL_AUPLL_DIV3,      /*!< mcu muxpll select aupll div3 */
+    GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV2,  /*!< mcu muxpll select top aupll div2 */
+    GLB_MCU_MUXPLL_SEL_AUPLL_DIV2P5,    /*!< mcu muxpll select aupll div2p5 */
+} GLB_MCU_MUXPLL_160M_CLK_SEL_Type;
+
+/**
+ *  @brief GLB mcu muxpll 80M clock type definition
+ */
+typedef enum {
+    GLB_MCU_MUXPLL_SEL_WIFIPLL_80M,    /*!< mcu muxpll select wifipll 80M */
+    GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV5, /*!< mcu muxpll select top aupll div5 */
+    GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV6, /*!< mcu muxpll select top aupll div6 */
+} GLB_MCU_MUXPLL_80M_CLK_SEL_Type;
+
+/**
+ *  @brief GLB isp muxpll 80M clock type definition
+ */
+typedef enum {
+    GLB_ISP_MUXPLL_SEL_WIFIPLL_80M,    /*!< isp muxpll select wifipll 80M */
+    GLB_ISP_MUXPLL_SEL_AUPLL_DIV5,     /*!< isp muxpll select aupll div5 */
+    GLB_ISP_MUXPLL_SEL_AUPLL_DIV6,     /*!< isp muxpll select aupll div6 */
+} GLB_ISP_MUXPLL_80M_CLK_SEL_Type;
+
+/**
+ *  @brief GLB pll clock gate type definition
+ */
+typedef enum {
+    GLB_PLL_CGEN_ISP_WIFIPLL_80M     =  2,  /*!< CGEN for WIFIPLL 80M to ISP       */
+    GLB_PLL_CGEN_ISP_AUPLL_DIV5      =  3,  /*!< CGEN for AUPLL DIV5 to ISP        */
+    GLB_PLL_CGEN_ISP_AUPLL_DIV6      =  4,  /*!< CGEN for AUPLL DIV6 to ISP        */
+    GLB_PLL_CGEN_TOP_AUPLL_DIV5      =  5,  /*!< CGEN for AUPLL DIV5 to TOP        */
+    GLB_PLL_CGEN_TOP_AUPLL_DIV6      =  6,  /*!< CGEN for AUPLL DIV6 to TOP        */
+    GLB_PLL_CGEN_PSRAMB_WIFIPLL_320M =  7,  /*!< CGEN for WIFIPLL 320MHz to psramB */
+    GLB_PLL_CGEN_PSRAMB_AUPLL_DIV1   =  8,  /*!< CGEN for AUPLL_DIV1 to psramB     */
+    GLB_PLL_CGEN_TOP_WIFIPLL_240M    = 13,  /*!< CGEN for WIFIPLL 240MHz to TOP    */
+    GLB_PLL_CGEN_TOP_WIFIPLL_320M    = 14,  /*!< CGEN for WIFIPLL 320MHz to TOP    */
+    GLB_PLL_CGEN_TOP_AUPLL_DIV2      = 15,  /*!< CGEN for AUPLL_DIV2 to TOP        */
+    GLB_PLL_CGEN_TOP_AUPLL_DIV1      = 16,  /*!< CGEN for AUPLL_DIV1 to TOP        */
+} GLB_PLL_CGEN_Type;
+
+/**
+ *  @brief GLB mcu system clock type definition
+ */
+typedef enum {
+    GLB_MCU_SYS_CLK_RC32M,              /*!< use RC32M as system clock frequency */
+    GLB_MCU_SYS_CLK_XTAL,               /*!< use XTAL as system clock */
+    GLB_MCU_SYS_CLK_TOP_AUPLL_DIV2,     /*!< use TOP_AUPLL_DIV2 output as system clock */
+    GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1,     /*!< use TOP_AUPLL_DIV1 output as system clock */
+    GLB_MCU_SYS_CLK_TOP_WIFIPLL_240M,   /*!< use TOP_WIFIPLL_240M output as system clock */
+    GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M,   /*!< use TOP_WIFIPLL_320M output as system clock */
+} GLB_MCU_SYS_CLK_Type;
+
+/**
+ *  @brief GLB dsp system clock type definition
+ */
+typedef enum {
+    GLB_PLL_REFCLK_XTAL = 0,  /*!< use XTAL as pll ref clock */
+    GLB_PLL_REFCLK_RC32M = 3, /*!< use RC32M as pll ref clock */
+} GLB_PLL_REF_CLK_Type;
+
+typedef struct {
+    uint8_t clkpllRefdivRatio;  /*!< xxx pll_refdiv_ratio */
+    uint8_t clkpllIntFracSw;    /*!< xxx pll_int_frac_sw */
+    uint8_t clkpllIcp1u;        /*!< xxx pll_icp_1u */
+    uint8_t clkpllIcp5u;        /*!< xxx pll_icp_5u */
+    uint8_t clkpllRz;           /*!< xxx pll_rz */
+    uint8_t clkpllCz;           /*!< xxx pll_cz */
+    uint8_t clkpllC3;           /*!< xxx pll_c3 */
+    uint8_t clkpllR4Short;      /*!< xxx pll_r4_short */
+    uint8_t clkpllC4En;         /*!< xxx pll_r4_en */
+    uint8_t clkpllSelSampleClk; /*!< xxx pll_sel_sample_clk */
+    uint8_t clkpllVcoSpeed;     /*!< xxx pll_vco_speed */
+    uint8_t clkpllSdmCtrlHw;    /*!< xxx pll_sdm_ctrl_hw */
+    uint8_t clkpllSdmBypass;    /*!< xxx pll_sdm_bypass */
+} GLB_WA_PLL_CFG_BASIC_Type;
+
+typedef struct {
+    const GLB_WA_PLL_CFG_BASIC_Type *const basicCfg;  /*!< pll basic configuration */
+    uint32_t clkpllSdmin;                             /*!< pll sdmin value */
+    uint8_t clkpllPostDiv;                            /*!< aupll aupll_postdiv value */
+} GLB_WA_PLL_Cfg_Type;
+
+/**
+ *  @brief GLB CAM clock type definition
+ */
+typedef enum {
+    GLB_CAM_CLK_XCLK,           /*!< Select XCLK as CAM clock */
+    GLB_CAM_CLK_WIFIPLL_96M,    /*!< Select WIFIPLL_96M as CAM clock */
+    GLB_CAM_CLK_TOP_AUPLL_DIV5, /*!< Select TOP_AUPLL_DIV5 as CAM clock */
+} GLB_CAM_CLK_Type;
+
+/**
+ *  @brief GLB SDH clock type definition
+ */
+typedef enum {
+    GLB_SDH_CLK_WIFIPLL_96M,    /*!< Select WIFIPLL_96M as SDH clock */
+    GLB_SDH_CLK_TOP_AUPLL_DIV5, /*!< Select TOP_AUPLL_DIV5 as SDH clock */
+} GLB_SDH_CLK_Type;
+
+/**
+ *  @brief GLB UART sig swap group type definition
+ */
+typedef enum {
+    GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11,  /*!< SWAP UART SIG GROUP GPIO0  -  GPIO11 */
+    GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, /*!< SWAP UART SIG GROUP GPIO12 -  GPIO23 */
+    GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35, /*!< SWAP UART SIG GROUP GPIO24 -  GPIO35 */
+    GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, /*!< SWAP UART SIG GROUP GPIO36 -  GPIO45 */
+} GLB_UART_SIG_SWAP_GRP_Type;
+
+/**
+ *  @brief GLB I2S output ref clock type definition
+ */
+typedef enum {
+    GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */
+    GLB_I2S_OUT_REF_CLK_SRC,  /*!< output reference clock on I2S_0 ref_clock port */
+} GLB_I2S_OUT_REF_CLK_Type;
+
+/**
+ *  @brief GLB DMA clock ID type definition
+ */
+typedef enum {
+    GLB_DMA0_CLK_CH0, /*!< DMA0 clock ID:channel 0 */
+    GLB_DMA0_CLK_CH1, /*!< DMA0 clock ID:channel 1 */
+    GLB_DMA0_CLK_CH2, /*!< DMA0 clock ID:channel 2 */
+    GLB_DMA0_CLK_CH3, /*!< DMA0 clock ID:channel 3 */
+} GLB_DMA_CLK_ID_Type;
+
+/**
+ *  @brief GLB peripheral DMA type definition
+ */
+typedef enum {
+    GLB_PERI_DMA_UART0_RX =  0, /*!< uart_rx  */
+    GLB_PERI_DMA_UART0_TX =  1, /*!< uart_tx  */
+    GLB_PERI_DMA_UART1_RX =  2, /*!< uart1_rx */
+    GLB_PERI_DMA_UART1_TX =  3, /*!< uart1_tx */
+    GLB_PERI_DMA_UART2_RX =  4, /*!< uart2_rx */
+    GLB_PERI_DMA_UART2_TX =  5, /*!< uart2_tx */
+    GLB_PERI_DMA_I2C_0_RX =  6, /*!< i2c_0_rx */
+    GLB_PERI_DMA_I2C_0_TX =  7, /*!< i2c_0_tx */
+    GLB_PERI_DMA_IRTX_TX  =  8, /*!< irtx_tx  */
+    GLB_PERI_DMA_GPIO_TX  =  9, /*!< gpio_tx  */
+    GLB_PERI_DMA_SPI_RX   = 10, /*!< spi_rx   */
+    GLB_PERI_DMA_SPI_TX   = 11, /*!< spi_tx   */
+    GLB_PERI_DMA_AUDIO_RX = 12, /*!< audio_rx */
+    GLB_PERI_DMA_AUDIO_TX = 13, /*!< audio_tx */
+    GLB_PERI_DMA_I2C_1_RX = 14, /*!< i2c_1_rx */
+    GLB_PERI_DMA_I2C_1_TX = 15, /*!< i2c_1_tx */
+    GLB_PERI_DMA_I2S_0_RX = 16, /*!< i2s_0_rx */
+    GLB_PERI_DMA_I2S_0_TX = 17, /*!< i2s_0_tx */
+    GLB_PERI_DMA_PDM_RX   = 18, /*!< pdm_rx   */
+    GLB_PERI_DMA_PADC     = 19, /*!< padc     */
+    GLB_PERI_DMA_GAUGE    = 20, /*!< gauge    */
+    GLB_PERI_DMA_GPADC    = 22, /*!< gpadc    */
+    GLB_PERI_DMA_GPDAC_TX = 23, /*!< gpdac_tx */
+    GLB_PERI_DMA_PEC_RX0  = 24, /*!< pec_rx0  */
+    GLB_PERI_DMA_PEC_RX1  = 25, /*!< pec_rx1  */
+    GLB_PERI_DMA_PEC_RX2  = 26, /*!< pec_rx2  */
+    GLB_PERI_DMA_PEC_RX3  = 27, /*!< pec_rx3  */
+    GLB_PERI_DMA_PEC_TX0  = 28, /*!< pec_tx0  */
+    GLB_PERI_DMA_PEC_TX1  = 29, /*!< pec_tx1  */
+    GLB_PERI_DMA_PEC_TX2  = 30, /*!< pec_tx2  */
+    GLB_PERI_DMA_PEC_TX3  = 31, /*!< pec_tx3  */
+} GLB_PERI_DMA_Type;
+
+/**
+ *  @brief GLB DMA CN selection type definition
+ */
+typedef enum {
+    GLB_PERI_DMA_CN_SEL_DMA0 = 0, /*!< peripheral DMA channel select DMA0 */
+} GLB_PERI_DMA_CN_SEL_Type;
+
+/**
+ *  @brief GLB clock source type definition
+ */
+typedef enum {
+    GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */
+} GLB_IR_CLK_SRC_Type;
+
+/**
+ *  @brief GLB flash clock type definition
+ */
+typedef enum {
+    GLB_SFLASH_CLK_WIFIPLL_120M,    /*!< Select WIFIPLL 120M as flash clock */
+    GLB_SFLASH_CLK_XTAL,            /*!< Select XTAL as flash clock */
+    GLB_SFLASH_CLK_TOP_AUPLL_DIV5,  /*!< Select AUPLL DIV5 as flash clock */
+    GLB_SFLASH_CLK_MUXPLL_80M,      /*!< Select MUXPLL 80M as flash clock */
+    GLB_SFLASH_CLK_BCLK,            /*!< Select BCLK as flash clock */
+    GLB_SFLASH_CLK_WIFIPLL_96M,     /*!< Select WIFIPLL 96M as flash clock */
+} GLB_SFLASH_CLK_Type;
+
+/**
+ *  @brief GLB I2C clock type definition
+ */
+typedef enum {
+    GLB_I2C_CLK_BCLK,       /*!< Select bus clk as I2C clock */
+    GLB_I2C_CLK_XCLK,       /*!< Select xclk as I2C clock */
+} GLB_I2C_CLK_Type;
+
+/**
+ *  @brief GLB SPI clock type definition
+ */
+typedef enum {
+    GLB_SPI_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as SPI clock */
+    GLB_SPI_CLK_XCLK,            /*!< Select xclk as SPI clock */
+} GLB_SPI_CLK_Type;
+
+/**
+ *  @brief GLB PEC clock type definition
+ */
+typedef enum {
+    GLB_PEC_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as PEC clock */
+    GLB_PEC_CLK_XCLK,            /*!< Select xclk as PEC clock */
+} GLB_PEC_CLK_Type;
+
+/**
+ *  @brief GLB PWM1 io type definition
+ */
+typedef enum {
+    GLB_PWM1_IO_SINGLE_END, /*!< Select pwm1 io single end */
+    GLB_PWM1_IO_DIFF_END,   /*!< Select pwm1 io differential end for BLDC */
+} GLB_PWM1_IO_SEL_Type;
+
+/**
+ *  @brief GLB PDM io type definition
+ */
+typedef enum {
+    GLB_PDM_IO_SEL_AUDIO_TOP, /*!< Select audio_top PDM */
+    GLB_PDM_IO_SEL_AUPDM_TOP, /*!< Select aupdm_top PDM */
+} GLB_PDM_IO_SEL_Type;
+
+/**
+ *  @brief GLB DBI clock type definition
+ */
+typedef enum {
+    GLB_DBI_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as DBI clock */
+    GLB_DBI_CLK_XCLK,            /*!< Select xclk as DBI clock */
+} GLB_DBI_CLK_Type;
+
+/**
+ *  @brief GLB Audio auto clock type definition
+ */
+typedef enum {
+    GLB_AUDIO_AUTO_AUPLL,   /*!< Select aupll as audio auto clock */
+} GLB_AUDIO_AUTO_CLK_Type;
+
+/**
+ *  @brief GLB Audio ADC clock type definition
+ */
+typedef enum {
+    GLB_AUDIO_ADC_AUPLL,    /*!< Select aupll as audio adc clock */
+} GLB_AUDIO_ADC_CLK_Type;
+
+/**
+ *  @brief GLB Audio solo clock type definition
+ */
+typedef enum {
+    GLB_AUDIO_SOLO_AUPLL,   /*!< Select aupll as audio solo clock */
+} GLB_AUDIO_SOLO_CLK_Type;
+
+/**
+ *  @brief GLB SPI pad action type definition
+ */
+typedef enum {
+    GLB_SPI_PAD_ACT_AS_SLAVE,  /*!< SPI pad act as slave */
+    GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */
+} GLB_SPI_PAD_ACT_AS_Type;
+
+/**
+ *  @brief GLB reset recorder type definition
+ */
+typedef struct {
+    uint8_t reset_recorder_ana_powb         : 1; /* reset record bit [0] */
+    uint8_t reset_recorder_ext_rst_n        : 1; /* reset record bit [1] */
+    uint8_t reset_recorder_pds_reset        : 1; /* reset record bit [2] */
+    uint8_t reset_recorder_wdt_rst_n        : 1; /* reset record bit [3] */
+    uint8_t reset_recorder_cpu_porst_n      : 1; /* reset record bit [4] */
+    uint8_t reset_recorder_sys_reset_n      : 1; /* reset record bit [5] */
+    uint8_t reset_recorder_cpu_sys_rstreq_n : 1; /* reset record bit [6] */
+    uint8_t reset_recorder_rsvd             : 1; /* reset record bit [7] */
+} GLB_RESET_RECORD_Type ;
+
+/**
+ *  @brief GLB AHB software type definition
+ */
+typedef enum {
+    GLB_AHB_MCU_SW_RSV0 = 0,
+    GLB_AHB_MCU_SW_RSV1 = 1,
+    GLB_AHB_MCU_SW_WIFI = 4,
+    GLB_AHB_MCU_SW_BTDM = 8,
+    GLB_AHB_MCU_SW_ZIGBEE = 9,
+    GLB_AHB_MCU_SW_BLE2 = 10,
+    GLB_AHB_MCU_SW_ZIGBEE2 = 11,
+    GLB_AHB_MCU_SW_EMI_MISC = 16,
+    GLB_AHB_MCU_SW_MM_MISC = 17,
+    GLB_AHB_MCU_SW_PSRAM1_CTRL = 18,
+    GLB_AHB_MCU_SW_EXT_USB = 19,
+    GLB_AHB_MCU_SW_EXT_AUPWM = 21,
+    GLB_AHB_MCU_SW_EXT_SDH = 22,
+    GLB_AHB_MCU_SW_EXT_EMAC = 23,
+    GLB_AHB_MCU_SW_D2XA = 25,
+    GLB_AHB_MCU_SW_D2XB = 26,
+    GLB_AHB_MCU_SW_JENC = 27,
+    GLB_AHB_MCU_SW_EXT_PEC = 28,
+    GLB_AHB_MCU_SW_GLB = 32,
+    GLB_AHB_MCU_SW_MIX = 33,
+    GLB_AHB_MCU_SW_GPIP = 34,
+    GLB_AHB_MCU_SW_SEC_DBG = 35,
+    GLB_AHB_MCU_SW_SEC_ENG = 36,
+    GLB_AHB_MCU_SW_TZ1 = 37,
+    GLB_AHB_MCU_SW_RSV38 = 38,
+    GLB_AHB_MCU_SW_EFUSE = 39,
+    GLB_AHB_MCU_SW_RSV40 = 40,
+    GLB_AHB_MCU_SW_PERI = 41,
+    GLB_AHB_MCU_SW_RSV42 = 42,
+    GLB_AHB_MCU_SW_SF = 43,
+    GLB_AHB_MCU_SW_DMA = 44,
+    GLB_AHB_MCU_SW_SDU = 45,
+    GLB_AHB_MCU_SW_PDS = 46,
+    GLB_AHB_MCU_SW_RSV47 = 47,
+    GLB_AHB_MCU_SW_UART0 = 48,
+    GLB_AHB_MCU_SW_UART1 = 49,
+    GLB_AHB_MCU_SW_SPI = 50,
+    GLB_AHB_MCU_SW_I2C0 = 51,
+    GLB_AHB_MCU_SW_PWM = 52,
+    GLB_AHB_MCU_SW_TIMER = 53,
+    GLB_AHB_MCU_SW_IR_REMOTE = 54,
+    GLB_AHB_MCU_SW_CHECKSUM = 55,
+    GLB_AHB_MCU_SW_DBI = 56,
+    GLB_AHB_MCU_SW_I2C1 = 57,
+    GLB_AHB_MCU_SW_ISO11898 = 58,
+    GLB_AHB_MCU_SW_I2S = 59,
+    GLB_AHB_MCU_SW_AUSOLO = 60,
+    GLB_AHB_MCU_SW_RSV61 = 61,
+    GLB_AHB_MCU_SW_RSV62 = 62,
+    GLB_AHB_MCU_SW_RSV63 = 63,
+    GLB_AHB_MCU_SW_PWRON_RST = 64,
+    GLB_AHB_MCU_SW_CPU_RESET = 65,
+    GLB_AHB_MCU_SW_SYS_RESET = 66,
+    GLB_AHB_MCU_SW_CHIP_RESET = 69,
+} GLB_AHB_MCU_SW_Type;
+
+/**
+ *  @brief GLB dis reset type definition
+ */
+typedef enum {
+    GLB_DISRST_GPIP = 2,
+    GLB_DISRST_SEC_ENG = 4,
+    GLB_DISRST_CCI = 8,
+    GLB_DISRST_SF = 11,
+    GLB_DISRST_UART0 = 16,
+    GLB_DISRST_UART1 = 17,
+    GLB_DISRST_SPI = 18,
+    GLB_DISRST_I2C0 = 19,
+    GLB_DISRST_PWM = 20,
+    GLB_DISRST_TIMER = 21,
+    GLB_DISRST_IR_REMOTE = 22,
+    GLB_DISRST_CHECKSUM = 23,
+    GLB_DISRST_DBI = 24,
+    GLB_DISRST_I2C1 = 25,
+    GLB_DISRST_ISO11898 = 26,
+} GLB_DISRST_Type;
+
+/**
+ *  @brief GLB PKA clock type definition
+ */
+typedef enum {
+    GLB_PKA_CLK_MCU_BCLK,        /*!< Select MCU_BCLK as PKA clock */
+    GLB_PKA_CLK_MCU_MUXPLL_160M, /*!< Select MCU MUXPLL 160M as PKA clock */
+} GLB_PKA_CLK_Type;
+
+/**
+ *  @brief GLB MCU software system reset type definition
+ */
+typedef enum {
+    GLB_MCU_SW_SYSTEM_CTRL_MCU = 1, /*!< mcu reset */
+} GLB_MCU_SW_SYSTEM_Type;
+
+/**
+ *  @brief BMX arb mode type definition
+ */
+typedef enum {
+    BMX_ARB_ROUND_ROBIN = 0, /*!< 0->round-robin */
+    BMX_ARB_FIX = 1,         /*!< 1->fix */
+} BMX_ARB_Type;
+
+/**
+ *  @brief BMX latch type definition
+ */
+typedef enum {
+    BMX_LATCH_FIRST_ERROR = 0, /*!< 0->Latch first error */
+    BMX_LATCH_LAST_ERROR = 1,  /*!< 1->Latch last error */
+} BMX_LATCH_Type;
+
+/**
+ *  @brief BMX configuration structure type definition
+ */
+typedef struct {
+    BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+    uint8_t timeoutEn;   /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+} BMX_TO_Cfg_Type;
+
+/**
+ *  @brief BMX bus err type definition
+ */
+typedef enum {
+    BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+    BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
+} BMX_BUS_ERR_Type;
+
+/**
+ *  @brief BMX bus err interrupt type definition
+ */
+typedef enum {
+    BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */
+    BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */
+} BMX_ERR_INT_Type;
+
+/**
+ *  @brief BMX time out interrupt type definition
+ */
+typedef enum {
+    BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */
+    BMX_TO_INT_ALL,     /*!< BMX timeout interrupt max num */
+} BMX_TO_INT_Type;
+
+/**
+ *  @brief GLB eth ref clock out type definition
+ */
+typedef enum {
+    GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */
+    GLB_ETH_REF_CLK_OUT_INSIDE_50M,  /*!< select inside 50MHz RMII ref clock */
+} GLB_ETH_REF_CLK_OUT_Type;
+
+/**
+ *  @brief GLB EM type definition
+ */
+typedef enum {
+    GLB_WRAM160KB_EM0KB,    /*!< WRAM_160KB EM_0KB */
+    GLB_WRAM128KB_EM32KB,   /*!< WRAM_128KB EM_32KB */
+    GLB_WRAM96KB_EM64KB,    /*!< WRAM_96KB EM_64KB */
+} GLB_EM_Type;
+
+/**
+ *  @brief GLB ADC clock type definition
+ */
+typedef enum {
+    GLB_ADC_CLK_AUPLL, /*!< use AUPLL as ADC clock */
+    GLB_ADC_CLK_XCLK,  /*!< use XCLK as ADC clock */
+} GLB_ADC_CLK_Type;
+
+/**
+ *  @brief GLB DAC clock type definition
+ */
+typedef enum {
+    GLB_DAC_CLK_32M,  /*!< use 32M as DAC clock */
+    GLB_DAC_CLK_XCLK, /*!< use XCLK as DAC clock */
+} GLB_DAC_CLK_Type;
+
+/**
+ *  @brief GLB chip clock input output type definition
+ */
+
+/**
+ *  @brief GLB chip clock out 0 type definition
+ */
+typedef enum {
+    GLB_CHIP_CLK_OUT_0_CAM_REF_CLK = 0,   /*!< cam_ref_clk */
+    GLB_CHIP_CLK_OUT_0_I2S_REF_CLK = 1,   /*!< i2s_ref_clk out */
+    GLB_CHIP_CLK_OUT_0_NONE = 2,          /*!< no clock out */
+    GLB_CHIP_CLK_OUT_0_SOLO_IN_128FS = 3, /*!< clk_solo_in_128fs */
+} GLB_CHIP_CLK_OUT_0_Type;
+
+/**
+ *  @brief GLB chip clock out 1 type definition
+ */
+typedef enum {
+    GLB_CHIP_CLK_OUT_1_CAM_REF_CLK = 0,   /*!< no chip clock out */
+    GLB_CHIP_CLK_OUT_1_I2S_REF_CLK = 1,   /*!< i2s_ref_clk out */
+    GLB_CHIP_CLK_OUT_1_NONE = 2,          /*!< no clock out */
+    GLB_CHIP_CLK_OUT_1_SOLO_IN_128FS = 3, /*!< clk_solo_in_128fs */
+} GLB_CHIP_CLK_OUT_1_Type;
+
+/**
+ *  @brief GLB chip clock out 2 type definition
+ */
+typedef enum {
+    GLB_CHIP_CLK_OUT_2_CAM_REF_CLK = 0,  /*!< cam_ref_clk */
+    GLB_CHIP_CLK_OUT_2_I2S_REF_CLK = 1,  /*!< i2s_ref_clk */
+    GLB_CHIP_CLK_OUT_2_ANA_XTAL_CLK = 2, /*!< ana_xtal_clk */
+    GLB_CHIP_CLK_OUT_2_WIFIPLL_32M = 3,  /*!< wifipll_32m_clk */
+} GLB_CHIP_CLK_OUT_2_Type;
+
+/**
+ *  @brief GLB chip clock out 3 type definition
+ */
+typedef enum {
+    GLB_CHIP_CLK_OUT_3_CAM_REF_CLK = 0, /*!< no chip clock out */
+    GLB_CHIP_CLK_OUT_3_I2S_REF_CLK = 1, /*!< i2s_ref_clk out */
+    GLB_CHIP_CLK_OUT_3_NONE = 2,        /*!< no clock out */
+    GLB_CHIP_CLK_OUT_3_WIFIPLL_48M = 3, /*!< wifipll_48m_clk */
+} GLB_CHIP_CLK_OUT_3_Type;
+
+/**
+ *  @brief GLB DIG clock source select type definition
+ */
+typedef enum {
+    GLB_DIG_CLK_WIFIPLL_32M, /*!< select WIFIPLL 32M as DIG clock source */
+    GLB_DIG_CLK_XCLK,        /*!< select XCLK as DIG clock source */
+    GLB_DIG_CLK_AUPLL,       /*!< select AUPLL as DIG clock source */
+} GLB_DIG_CLK_Type;
+
+/**
+ *  @brief GLB 512K clock out select type definition
+ */
+typedef enum {
+    GLB_512K_CLK_OUT_512K, /*!< select 512K clock out */
+    GLB_512K_CLK_OUT_256K, /*!< select 256K clock out */
+    GLB_512K_CLK_OUT_128K, /*!< select 128K clock out */
+} GLB_512K_CLK_OUT_Type;
+
+/**
+ *  @brief GLB BT bandwidth type definition
+ */
+typedef enum {
+    GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */
+    GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */
+} GLB_BT_BANDWIDTH_Type;
+
+/**
+ *  @brief GLB UART signal type definition
+ */
+typedef enum {
+    GLB_UART_SIG_0,  /*!< UART signal 0 */
+    GLB_UART_SIG_1,  /*!< UART signal 1 */
+    GLB_UART_SIG_2,  /*!< UART signal 2 */
+    GLB_UART_SIG_3,  /*!< UART signal 3 */
+    GLB_UART_SIG_4,  /*!< UART signal 4 */
+    GLB_UART_SIG_5,  /*!< UART signal 5 */
+    GLB_UART_SIG_6,  /*!< UART signal 6 */
+    GLB_UART_SIG_7,  /*!< UART signal 7 */
+    GLB_UART_SIG_8,  /*!< UART signal 8 */
+    GLB_UART_SIG_9,  /*!< UART signal 9 */
+    GLB_UART_SIG_10, /*!< UART signal 10 */
+    GLB_UART_SIG_11, /*!< UART signal 11 */
+} GLB_UART_SIG_Type;
+
+/**
+ *  @brief GLB UART signal  function type definition
+ */
+typedef enum {
+    GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */
+    GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */
+    GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */
+    GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */
+    GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */
+    GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */
+    GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */
+    GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */
+    GLB_UART_SIG_FUN_N_ISO11898_TXD, /*!< UART funtion: UART 2 RTS */
+    GLB_UART_SIG_FUN_RESERVED,  /*!< UART funtion: UART 2 CTS */
+    GLB_UART_SIG_FUN_ISO11898_TXD,   /*!< UART funtion: UART 2 TXD */
+    GLB_UART_SIG_FUN_ISO11898_RXD,   /*!< UART funtion: UART 2 RXD */
+} GLB_UART_SIG_FUN_Type;
+
+/**
+ *  @brief XTAL type definition
+ */
+typedef enum {
+    GLB_XTAL_NONE,  /*!< XTAL is none */
+    GLB_XTAL_24M,   /*!< XTAL is 24M */
+    GLB_XTAL_32M,   /*!< XTAL is 32M */
+    GLB_XTAL_38P4M, /*!< XTAL is 38.4M */
+    GLB_XTAL_40M,   /*!< XTAL is 40M */
+    GLB_XTAL_26M,   /*!< XTAL is 26M */
+    GLB_XTAL_RC32M, /*!< XTAL is RC32M */
+    GLB_XTAL_MAX,   /*!< type max num */
+} GLB_XTAL_Type;
+
+/**
+ *  @brief PLL power on type definition
+ */
+typedef enum {
+    GLB_PLL_NONE = 0,    /*!< power on xtal and pll */
+    GLB_PLL_WIFIPLL = 1, /*!< power on WIFIPLL */
+    GLB_PLL_AUPLL = 2,   /*!< power on AUPLL */
+} GLB_PLL_Type;
+
+/**
+ *  @brief WA PLL XTAL type definition
+ */
+typedef enum {
+    GLB_WA_PLL_WIFIPLL, /*!< wifi pll */
+    GLB_WA_PLL_AUPLL,   /*!< audio pll */
+} GLB_WA_PLL_Type;
+
+/**
+ *  @brief PSRAMB PLL type definition
+ */
+typedef enum {
+    GLB_PSRAMB_EMI_WIFIPLL_320M, /*!< emi_wifipll_320m_clk */
+    GLB_PSRAMB_EMI_AUPLL_DIV1,   /*!< emi_aupll_div1_clk */
+} GLB_PSRAMB_PLL_Type;
+
+/**
+ *  @brief GLB UART clock type definition
+ */
+typedef enum {
+    GLB_UART_CLK_BCLK,     /*!< Select bclk clock as UART clock */
+    GLB_UART_CLK_PLL_160M, /*!< Select PLL 160M as UART clock */
+} GLB_UART_CLK_Type;
+
+/**
+ *  @brief GLB I2S di ref clock type definition
+ */
+typedef enum {
+    GLB_I2S_DI_SEL_I2S_DI_INPUT,   /*!< Select i2s_di input */
+    GLB_I2S_DI_SEL_I2S_REF_OUTPUT, /*!< Select i2s_ref_clk output */
+} GLB_I2S_DI_REF_CLK_Type;
+
+/**
+ *  @brief GLB SPI sig swap group type definition
+ */
+typedef enum {
+    GLB_SPI_SIG_SWAP_GRP_GPIO0_GPIO11,  /*!< SWAP SPI SIG GROUP GPIO0  -  GPIO11 */
+    GLB_SPI_SIG_SWAP_GRP_GPIO12_GPIO23, /*!< SWAP SPI SIG GROUP GPIO12 -  GPIO23 */
+    GLB_SPI_SIG_SWAP_GRP_GPIO24_GPIO35, /*!< SWAP SPI SIG GROUP GPIO24 -  GPIO35 */
+    GLB_SPI_SIG_SWAP_GRP_GPIO36_GPIO45, /*!< SWAP SPI SIG GROUP GPIO36 -  GPIO45 */
+} GLB_SPI_SIG_SWAP_GRP_Type;
+
+/**
+ *  @brief GLB I2S do ref clock type definition
+ */
+typedef enum {
+    GLB_I2S_DO_SEL_I2S_DO_OUTPT,   /*!< Select i2s_do output */
+    GLB_I2S_DO_SEL_I2S_REF_OUTPUT, /*!< Select i2s_ref_clk output */
+} GLB_I2S_DO_REF_CLK_Type;
+
+/**
+ *  @brief GLB AHB clock IP type definition
+ */
+typedef enum {
+    GLB_AHB_CLOCK_IP_CPU,
+    GLB_AHB_CLOCK_IP_RSVD,
+    GLB_AHB_CLOCK_IP_SEC,
+    GLB_AHB_CLOCK_IP_DMA_0,
+    GLB_AHB_CLOCK_IP_DMA_1,
+    GLB_AHB_CLOCK_IP_DMA_2,
+    GLB_AHB_CLOCK_IP_CCI,
+    GLB_AHB_CLOCK_IP_RF_TOP,
+    GLB_AHB_CLOCK_IP_GPIP,
+    GLB_AHB_CLOCK_IP_TZC,
+    GLB_AHB_CLOCK_IP_EF_CTRL,
+    GLB_AHB_CLOCK_IP_SF_CTRL,
+    GLB_AHB_CLOCK_IP_EMAC,
+    GLB_AHB_CLOCK_IP_UART0,
+    GLB_AHB_CLOCK_IP_UART1,
+    GLB_AHB_CLOCK_IP_UART2,
+    GLB_AHB_CLOCK_IP_UART3,
+    GLB_AHB_CLOCK_IP_UART4,
+    GLB_AHB_CLOCK_IP_SPI,
+    GLB_AHB_CLOCK_IP_I2C,
+    GLB_AHB_CLOCK_IP_PWM,
+    GLB_AHB_CLOCK_IP_TIMER,
+    GLB_AHB_CLOCK_IP_IR,
+    GLB_AHB_CLOCK_IP_CHECKSUM,
+    GLB_AHB_CLOCK_IP_QDEC,
+    GLB_AHB_CLOCK_IP_KYS,
+    GLB_AHB_CLOCK_IP_I2S,
+    GLB_AHB_CLOCK_IP_USB11,
+    GLB_AHB_CLOCK_IP_CAM,
+    GLB_AHB_CLOCK_IP_MJPEG,
+    GLB_AHB_CLOCK_IP_BT_BLE_NORMAL,
+    GLB_AHB_CLOCK_IP_BT_BLE_LP,
+    GLB_AHB_CLOCK_IP_ZB_NORMAL,
+    GLB_AHB_CLOCK_IP_ZB_LP,
+    GLB_AHB_CLOCK_IP_WIFI_NORMAL,
+    GLB_AHB_CLOCK_IP_WIFI_LP,
+    GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL,
+    GLB_AHB_CLOCK_IP_BT_BLE_2_LP,
+    GLB_AHB_CLOCK_IP_EMI_MISC,
+    GLB_AHB_CLOCK_IP_PSRAM0_CTRL,
+    GLB_AHB_CLOCK_IP_PSRAM1_CTRL,
+    GLB_AHB_CLOCK_IP_USB20_SDU,
+    GLB_AHB_CLOCK_IP_MIX2,
+    GLB_AHB_CLOCK_IP_AUDIO,
+    GLB_AHB_CLOCK_IP_SDH,
+    GLB_AHB_CLOCK_IP_ZB2_NORMAL,
+    GLB_AHB_CLOCK_IP_ZB2_LP,
+    GLB_AHB_CLOCK_IP_I2C1,
+    GLB_AHB_CLOCK_IP_WIFI_PHY,
+    GLB_AHB_CLOCK_IP_WIFI_MAC_PHY,
+    GLB_AHB_CLOCK_IP_WIFI_PLATFORM,
+    GLB_AHB_CLOCK_IP_LZ4,
+    GLB_AHB_CLOCK_IP_AUPDM,
+    GLB_AHB_CLOCK_IP_GAUGE,
+    GLB_AHB_CLOCK_IP_DBI,
+    GLB_AHB_CLOCK_IP_PEC,
+    GLB_AHB_CLOCK_IP_ISO11898,
+    GLB_AHB_CLOCK_IP_AUSOLO_TOP,
+    GLB_AHB_CLOCK_IP_DMA_GPIO,
+    GLB_AHB_CLOCK_IP_MM_MISC,
+} GLB_AHB_CLOCK_IP_Type;
+
+typedef enum {
+    GLB_SLAVE_GRP_0_ADC,
+    GLB_SLAVE_GRP_0_IR,
+    GLB_SLAVE_GRP_0_I2C,
+    GLB_SLAVE_GRP_0_SPI,
+    GLB_SLAVE_GRP_0_PEC,
+    GLB_SLAVE_GRP_0_DBI,
+    GLB_SLAVE_GRP_0_AUDIO_AUTO,
+    GLB_SLAVE_GRP_0_AUDIO_ADC,
+    GLB_SLAVE_GRP_0_AUDIO_SOLO,
+    GLB_SLAVE_GRP_0_CAM,
+    GLB_SLAVE_GRP_0_SDH,
+    GLB_SLAVE_GRP_0_PSRAMB,
+    GLB_SLAVE_GRP_0_MAX,
+} GLB_SLAVE_GRP_0_Type;
+
+typedef struct {
+    uint32_t clkOffSetAddr;
+    uint8_t clkEnPos;
+    uint8_t clkSelPos;
+    uint8_t clkDivPos;
+    uint8_t clkEnLen;
+    uint8_t clkSelLen;
+    uint8_t clkDivLen;
+} GLB_SLAVE_GRP_0_TBL_Type;
+
+typedef union {
+        GLB_ADC_CLK_Type        adcClkSel;
+        GLB_IR_CLK_SRC_Type     irClkSel;
+        GLB_I2C_CLK_Type        i2cClkSel;
+        GLB_SPI_CLK_Type        spiClkSel;
+        GLB_PEC_CLK_Type        pecClkSel;
+        GLB_DBI_CLK_Type        dbiClkSel;
+        GLB_AUDIO_AUTO_CLK_Type audioAutoClkSel;
+        GLB_AUDIO_ADC_CLK_Type  audioAdcClkSel;
+        GLB_AUDIO_SOLO_CLK_Type audioSoloClkSel;
+        GLB_CAM_CLK_Type        camClkSel;
+        GLB_SDH_CLK_Type        sdhClkSel;
+        GLB_PSRAMB_PLL_Type     psrambClkSel;
+        uint32_t                clkSel;
+} GLB_SLAVE_GRP_0_CLK_SEL_Type;
+
+/*@} end of group GLB_Public_Types */
+
+/** @defgroup  GLB_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  GLB_CORE_ID_TYPE
+ *  @{
+ */
+#define IS_GLB_CORE_ID_TYPE(type) (((type) == GLB_CORE_ID_M0) ||  \
+                                   ((type) == GLB_CORE_ID_MAX) || \
+                                   ((type) == GLB_CORE_ID_INVALID))
+
+/** @defgroup  CCI_ID_TYPE
+ *  @{
+ */
+#define IS_CCI_ID_TYPE(type) (((type) == CCI0_ID) || \
+                              ((type) == CCI_ID_MAX))
+
+/** @defgroup  GLB_MCU_ALL_INT_TYPE
+ *  @{
+ */
+#define IS_GLB_MCU_ALL_INT_TYPE(type) (((type) == GLB_MCU_ALL_INT_BMX_ERR_INT) ||                      \
+                                       ((type) == GLB_MCU_ALL_INT_BMX_TIMEOUT_INT_MCU_TIMEOUT_INT) ||  \
+                                       ((type) == GLB_MCU_ALL_INT_IPC0_NP2AP_IRQ) ||                   \
+                                       ((type) == GLB_MCU_ALL_INT_IPC0_AP2NP_IRQ) ||                   \
+                                       ((type) == GLB_MCU_ALL_INT_AUDIO_INT) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_RF_TOP_INT_0) ||                     \
+                                       ((type) == GLB_MCU_ALL_INT_RF_TOP_INT_1) ||                     \
+                                       ((type) == GLB_MCU_ALL_INT_LZ4_INT) ||                          \
+                                       ((type) == GLB_MCU_ALL_INT_RSV8) ||                             \
+                                       ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_GMAC_INT) ||             \
+                                       ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_CDET_INT) ||             \
+                                       ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_PKA_INT) ||              \
+                                       ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_TRNG_INT) ||             \
+                                       ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_AES_INT) ||              \
+                                       ((type) == GLB_MCU_ALL_INT_SEC_ENG_ID0_SHA_INT) ||              \
+                                       ((type) == GLB_MCU_ALL_INT_DMA_INTR_ALL) ||                     \
+                                       ((type) == GLB_MCU_ALL_INT_DMA2_INTR_ALL) ||                    \
+                                       ((type) == GLB_MCU_ALL_INT_SDH_MMC1_INT_SDH2PMU_WAKEUP_INT1) || \
+                                       ((type) == GLB_MCU_ALL_INT_MM_IRQ_ALL) ||                       \
+                                       ((type) == GLB_MCU_ALL_INT_IRTX_INT) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_IRRX_INT) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_USB_INT) ||                          \
+                                       ((type) == GLB_MCU_ALL_INT_AUPDM_INT) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_SF_CTRL_ID0_INT) ||                  \
+                                       ((type) == GLB_MCU_ALL_INT_EMAC_INT) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_GPADC_DMA_INT) ||                    \
+                                       ((type) == GLB_MCU_ALL_INT_EFUSE_INT) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_SPI_0_INT) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_UART_IRQ) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_UART1_IRQ) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_UART2_IRQ) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_GPIO_DMA_INT) ||                     \
+                                       ((type) == GLB_MCU_ALL_INT_I2C_0_INT) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_PWM_INT) ||                          \
+                                       ((type) == GLB_MCU_ALL_INT_IPC1_NP2AP_IRQ) ||                   \
+                                       ((type) == GLB_MCU_ALL_INT_IPC1_AP2NP_IRQ) ||                   \
+                                       ((type) == GLB_MCU_ALL_INT_TIMER0_2_IRQ) ||                     \
+                                       ((type) == GLB_MCU_ALL_INT_TIMER0_3_IRQ) ||                     \
+                                       ((type) == GLB_MCU_ALL_INT_WDT0_IRQ) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_I2C_1_INT) ||                        \
+                                       ((type) == GLB_MCU_ALL_INT_I2S0_INT) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_RSV41) ||                            \
+                                       ((type) == GLB_MCU_ALL_INT_RSV42) ||                            \
+                                       ((type) == GLB_MCU_ALL_INT_ANA_OCP_OUT_TO_CPU_IRQ) ||           \
+                                       ((type) == GLB_MCU_ALL_INT_GPIO_IRQ) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_DM_IRQ) ||                           \
+                                       ((type) == GLB_MCU_ALL_INT_BT_IRQ) ||                           \
+                                       ((type) == GLB_MCU_ALL_INT_M154_REQ_ENH_ACK_INT) ||             \
+                                       ((type) == GLB_MCU_ALL_INT_M154_INT) ||                         \
+                                       ((type) == GLB_MCU_ALL_INT_M154_AES_INT) ||                     \
+                                       ((type) == GLB_MCU_ALL_INT_PDS_INT) ||                          \
+                                       ((type) == GLB_MCU_ALL_INT_HBN_IRQ_OUT_0) ||                    \
+                                       ((type) == GLB_MCU_ALL_INT_HBN_IRQ_OUT_1) ||                    \
+                                       ((type) == GLB_MCU_ALL_INT_BOR_OUT) ||                          \
+                                       ((type) == GLB_MCU_ALL_INT_WIFI_TO_CPU_IRQ_N) ||                \
+                                       ((type) == GLB_MCU_ALL_INT_BZ_PHY_INT) ||                       \
+                                       ((type) == GLB_MCU_ALL_INT_BLE_INT) ||                          \
+                                       ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_RX_TIMER) ||              \
+                                       ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_RX_MISC) ||               \
+                                       ((type) == GLB_MCU_ALL_INT_MAC_INT_RX_TRIGGER) ||               \
+                                       ((type) == GLB_MCU_ALL_INT_MAC_INT_TX_TRIGGER) ||               \
+                                       ((type) == GLB_MCU_ALL_INT_MAC_INT_GEN) ||                      \
+                                       ((type) == GLB_MCU_ALL_INT_MAC_INT_PROT_TRIGGER) ||             \
+                                       ((type) == GLB_MCU_ALL_INT_WIFI_IPC))
+
+/** @defgroup  GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(type) (((type) == GLB_MCU_MUXPLL_SEL_WIFIPLL_160M) ||    \
+                                                   ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV3) ||      \
+                                                   ((type) == GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV2) ||  \
+                                                   ((type) == GLB_MCU_MUXPLL_SEL_AUPLL_DIV2P5))
+
+/** @defgroup  GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(type) (((type) == GLB_MCU_MUXPLL_SEL_WIFIPLL_80M) ||    \
+                                                  ((type) == GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV5) || \
+                                                  ((type) == GLB_MCU_MUXPLL_SEL_TOP_AUPLL_DIV6))
+
+/** @defgroup  GLB_ISP_MUXPLL_80M_CLK_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_ISP_MUXPLL_80M_CLK_SEL_TYPE(type) (((type) == GLB_ISP_MUXPLL_SEL_WIFIPLL_80M) ||    \
+                                                  ((type) == GLB_ISP_MUXPLL_SEL_AUPLL_DIV5) ||     \
+                                                  ((type) == GLB_ISP_MUXPLL_SEL_AUPLL_DIV6))
+
+/** @defgroup  GLB_PLL_CGEN_TYPE
+ *  @{
+ */
+#define IS_GLB_PLL_CGEN_TYPE(type) (((type) == GLB_PLL_CGEN_ISP_WIFIPLL_80M) ||     \
+                                    ((type) == GLB_PLL_CGEN_ISP_AUPLL_DIV5) ||      \
+                                    ((type) == GLB_PLL_CGEN_ISP_AUPLL_DIV6) ||      \
+                                    ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV5) ||      \
+                                    ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV6) ||      \
+                                    ((type) == GLB_PLL_CGEN_PSRAMB_WIFIPLL_320M) || \
+                                    ((type) == GLB_PLL_CGEN_PSRAMB_AUPLL_DIV1) ||   \
+                                    ((type) == GLB_PLL_CGEN_TOP_WIFIPLL_240M) ||    \
+                                    ((type) == GLB_PLL_CGEN_TOP_WIFIPLL_320M) ||    \
+                                    ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV2) ||      \
+                                    ((type) == GLB_PLL_CGEN_TOP_AUPLL_DIV1))
+
+/** @defgroup  GLB_MCU_SYS_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_MCU_SYS_CLK_TYPE(type) (((type) == GLB_MCU_SYS_CLK_RC32M) ||            \
+                                       ((type) == GLB_MCU_SYS_CLK_XTAL) ||             \
+                                       ((type) == GLB_MCU_SYS_CLK_TOP_AUPLL_DIV2) ||   \
+                                       ((type) == GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1) ||   \
+                                       ((type) == GLB_MCU_SYS_CLK_TOP_WIFIPLL_240M) || \
+                                       ((type) == GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M))
+
+/** @defgroup  GLB_PLL_REF_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_PLL_REF_CLK_TYPE(type) (((type) == GLB_PLL_REFCLK_XTAL) || \
+                                       ((type) == GLB_PLL_REFCLK_RC32M))
+
+/** @defgroup  GLB_WIFIPLL_REF_CLK_Type
+ *  @{
+ */
+#define IS_GLB_WIFIPLL_REF_CLK_TYPE(type) (((type) == GLB_WIFIPLL_REF_XTAL_SOC_CLK) || \
+                                           ((type) == GLB_WIFIPLL_REF_XTAL_CLK) ||     \
+                                           ((type) == GLB_WIFIPLL_REF_XTAL_LO_CLK) ||  \
+                                           ((type) == GLB_WIFIPLL_REF_RC32M_CLK))
+
+/** @defgroup  GLB_AUPLL_REF_CLK_Type
+ *  @{
+ */
+#define IS_GLB_AUPLL_REF_CLK_TYPE(type) (((type) == GLB_AUPLL_REF_XTAL_SOC_CLK) || \
+                                         ((type) == GLB_AUPLL_REF_RC32M_CLK))
+
+/** @defgroup  GLB_CPUPLL_REF_CLK_Type
+ *  @{
+ */
+#define IS_GLB_CPUPLL_REF_CLK_TYPE(type) (((type) == GLB_CPUPLL_REF_XTAL_SOC_CLK) || \
+                                          ((type) == GLB_CPUPLL_REF_RC32M_CLK))
+
+/** @defgroup  GLB_UHSPLL_REF_CLK_Type
+ *  @{
+ */
+#define IS_GLB_UHSPLL_REF_CLK_TYPE(type) (((type) == GLB_UHSPLL_REF_XTAL_SOC_CLK) || \
+                                          ((type) == GLB_UHSPLL_REF_RC32M_CLK))
+
+/** @defgroup  GLB_CAM_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) ||         \
+                                   ((type) == GLB_CAM_CLK_WIFIPLL_96M) ||  \
+                                   ((type) == GLB_CAM_CLK_TOP_AUPLL_DIV5))
+
+/** @defgroup  GLB_SDH_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SDH_CLK_TYPE(type) (((type) == GLB_SDH_CLK_WIFIPLL_96M) ||  \
+                                   ((type) == GLB_SDH_CLK_TOP_AUPLL_DIV5))
+
+/** @defgroup  GLB_GLB_UART_SIG_SWAP_SET_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_SWAP_GRP_TYPE(type) (((type) == GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11) ||  \
+                                             ((type) == GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23) || \
+                                             ((type) == GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35) || \
+                                             ((type) == GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45))
+
+/** @defgroup  GLB_I2S_OUT_REF_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \
+                                           ((type) == GLB_I2S_OUT_REF_CLK_SRC))
+
+/** @defgroup  GLB_DMA_CLK_ID_TYPE
+ *  @{
+ */
+#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA0_CLK_CH0) || \
+                                      ((type) == GLB_DMA0_CLK_CH1) || \
+                                      ((type) == GLB_DMA0_CLK_CH2) || \
+                                      ((type) == GLB_DMA0_CLK_CH3))
+
+/** @defgroup  GLB_PERI_DMA_TYPE
+ *  @{
+ */
+#define IS_GLB_PERI_DMA_TYPE(type) (((type) == GLB_PERI_DMA_UART0_RX) || \
+                                    ((type) == GLB_PERI_DMA_UART0_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_UART1_RX) ||  \
+                                    ((type) == GLB_PERI_DMA_UART1_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_UART2_RX) ||  \
+                                    ((type) == GLB_PERI_DMA_UART2_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_I2C_0_RX) ||  \
+                                    ((type) == GLB_PERI_DMA_I2C_0_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_IRTX_TX) ||   \
+                                    ((type) == GLB_PERI_DMA_GPIO_TX) ||   \
+                                    ((type) == GLB_PERI_DMA_SPI_RX) ||    \
+                                    ((type) == GLB_PERI_DMA_SPI_TX) ||    \
+                                    ((type) == GLB_PERI_DMA_AUDIO_RX) ||  \
+                                    ((type) == GLB_PERI_DMA_AUDIO_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_I2C_1_RX) ||  \
+                                    ((type) == GLB_PERI_DMA_I2C_1_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_I2S_0_RX) ||  \
+                                    ((type) == GLB_PERI_DMA_I2S_0_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_PDM_RX) ||    \
+                                    ((type) == GLB_PERI_DMA_PADC) ||      \
+                                    ((type) == GLB_PERI_DMA_GAUGE) ||     \
+                                    ((type) == GLB_PERI_DMA_GPADC) ||     \
+                                    ((type) == GLB_PERI_DMA_GPDAC_TX) ||  \
+                                    ((type) == GLB_PERI_DMA_PEC_RX0) ||   \
+                                    ((type) == GLB_PERI_DMA_PEC_RX1) ||   \
+                                    ((type) == GLB_PERI_DMA_PEC_RX2) ||   \
+                                    ((type) == GLB_PERI_DMA_PEC_RX3) ||   \
+                                    ((type) == GLB_PERI_DMA_PEC_TX0) ||   \
+                                    ((type) == GLB_PERI_DMA_PEC_TX1) ||   \
+                                    ((type) == GLB_PERI_DMA_PEC_TX2) ||   \
+                                    ((type) == GLB_PERI_DMA_PEC_TX3))
+
+/** @defgroup  GLB_PERI_DMA_CN_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_PERI_DMA_CN_SEL_TYPE(type) (((type) == GLB_PERI_DMA_CN_SEL_DMA0))
+
+/** @defgroup  GLB_IR_CLK_SRC_TYPE
+ *  @{
+ */
+#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK))
+
+/** @defgroup  GLB_SFLASH_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_WIFIPLL_120M) ||   \
+                                      ((type) == GLB_SFLASH_CLK_XTAL) ||           \
+                                      ((type) == GLB_SFLASH_CLK_TOP_AUPLL_DIV5) || \
+                                      ((type) == GLB_SFLASH_CLK_MUXPLL_80M) ||     \
+                                      ((type) == GLB_SFLASH_CLK_BCLK) ||           \
+                                      ((type) == GLB_SFLASH_CLK_WIFIPLL_96M))
+
+/** @defgroup  GLB_I2C_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_I2C_CLK_TYPE(type) (((type) == GLB_I2C_CLK_BCLK) || \
+                                   ((type) == GLB_I2C_CLK_XCLK))
+
+/** @defgroup  GLB_SPI_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SPI_CLK_TYPE(type) (((type) == GLB_SPI_CLK_PLL160M) || \
+                                   ((type) == GLB_SPI_CLK_XCLK))
+
+/** @defgroup  GLB_PEC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_PEC_CLK_TYPE(type) (((type) == GLB_PEC_CLK_PLL160M) || \
+                                   ((type) == GLB_PEC_CLK_XCLK))
+
+/** @defgroup  GLB_PWM1_IO_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_PWM1_IO_SEL_TYPE(type) (((type) == GLB_PWM1_IO_SINGLE_END) || \
+                                       ((type) == GLB_PWM1_IO_DIFF_END))
+
+/** @defgroup  GLB_PWM2_IO_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_PWM2_IO_SEL_TYPE(type) (((type) == GLB_PWM2_IO_SINGLE_END) || \
+                                       ((type) == GLB_PWM2_IO_SINGLE_END_BLDC))
+
+/** @defgroup  GLB_PDM_IO_SEL_TYPE
+ *  @{
+ */
+#define IS_GLB_PDM_IO_SEL_TYPE(type) (((type) == GLB_PDM_IO_SEL_AUDIO_TOP) || \
+                                      ((type) == GLB_PDM_IO_SEL_AUPDM_TOP))
+
+/** @defgroup  GLB_DBI_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DBI_CLK_TYPE(type) (((type) == GLB_DBI_CLK_PLL160M) || \
+                                   ((type) == GLB_DBI_CLK_XCLK))
+
+/** @defgroup  GLB_AUDIO_AUTO_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_AUDIO_AUTO_CLK_TYPE(type) (((type) == GLB_AUDIO_AUTO_AUPLL))
+
+/** @defgroup  GLB_AUDIO_ADC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_AUDIO_ADC_CLK_TYPE(type) (((type) == GLB_AUDIO_ADC_AUPLL))
+
+/** @defgroup  GLB_AUDIO_SOLO_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_AUDIO_SOLO_CLK_TYPE(type) (((type) == GLB_AUDIO_SOLO_AUPLL))
+
+/** @defgroup  GLB_SPI_PAD_ACT_AS_TYPE
+ *  @{
+ */
+#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \
+                                          ((type) == GLB_SPI_PAD_ACT_AS_MASTER))
+
+/** @defgroup  GLB_AHB_SW_TYPE
+ *  @{
+ */
+#define IS_GLB_AHB_MCU_SW_TYPE(type) (((type) == GLB_AHB_MCU_SW_RSV0) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_RSV1) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_WIFI) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_BTDM) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_ZIGBEE) ||      \
+                                      ((type) == GLB_AHB_MCU_SW_BLE2) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_ZIGBEE2) ||     \
+                                      ((type) == GLB_AHB_MCU_SW_EMI_MISC) ||    \
+                                      ((type) == GLB_AHB_MCU_SW_MM_MISC) ||     \
+                                      ((type) == GLB_AHB_MCU_SW_PSRAM1_CTRL) || \
+                                      ((type) == GLB_AHB_MCU_SW_EXT_USB) ||     \
+                                      ((type) == GLB_AHB_MCU_SW_EXT_AUPWM) ||   \
+                                      ((type) == GLB_AHB_MCU_SW_EXT_SDH) ||     \
+                                      ((type) == GLB_AHB_MCU_SW_EXT_EMAC) ||    \
+                                      ((type) == GLB_AHB_MCU_SW_D2XA) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_D2XB) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_JENC) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_EXT_PEC) ||     \
+                                      ((type) == GLB_AHB_MCU_SW_GLB) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_MIX) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_GPIP) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_SEC_DBG) ||     \
+                                      ((type) == GLB_AHB_MCU_SW_SEC_ENG) ||     \
+                                      ((type) == GLB_AHB_MCU_SW_TZ1) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_RSV38) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_EFUSE) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_RSV40) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_PERI) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_RSV42) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_SF) ||          \
+                                      ((type) == GLB_AHB_MCU_SW_DMA) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_SDU) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_PDS) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_RSV47) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_UART0) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_UART1) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_SPI) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_I2C0) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_PWM) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_TIMER) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_IR_REMOTE) ||   \
+                                      ((type) == GLB_AHB_MCU_SW_CHECKSUM) ||    \
+                                      ((type) == GLB_AHB_MCU_SW_DBI) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_I2C1) ||        \
+                                      ((type) == GLB_AHB_MCU_SW_ISO11898) ||    \
+                                      ((type) == GLB_AHB_MCU_SW_I2S) ||         \
+                                      ((type) == GLB_AHB_MCU_SW_AUSOLO) ||      \
+                                      ((type) == GLB_AHB_MCU_SW_RSV61) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_RSV62) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_RSV63) ||       \
+                                      ((type) == GLB_AHB_MCU_SW_PWRON_RST) ||   \
+                                      ((type) == GLB_AHB_MCU_SW_CPU_RESET) ||   \
+                                      ((type) == GLB_AHB_MCU_SW_SYS_RESET) ||   \
+                                      ((type) == GLB_AHB_MCU_SW_CHIP_RESET))
+
+/** @defgroup  GLB DISRST_TYPE
+ *  @{
+ */
+#define IS_GLB_DISRST_TYPE(type) (((type) == GLB_DISRST_GPIP) ||      \
+                                  ((type) == GLB_DISRST_SEC_ENG) ||   \
+                                  ((type) == GLB_DISRST_CCI) ||       \
+                                  ((type) == GLB_DISRST_SF) ||        \
+                                  ((type) == GLB_DISRST_UART0) ||     \
+                                  ((type) == GLB_DISRST_UART1) ||     \
+                                  ((type) == GLB_DISRST_SPI) ||       \
+                                  ((type) == GLB_DISRST_I2C0) ||      \
+                                  ((type) == GLB_DISRST_PWM) ||       \
+                                  ((type) == GLB_DISRST_TIMER) ||     \
+                                  ((type) == GLB_DISRST_IR_REMOTE) || \
+                                  ((type) == GLB_DISRST_CHECKSUM) ||  \
+                                  ((type) == GLB_DISRST_DBI) ||       \
+                                  ((type) == GLB_DISRST_I2C1) ||      \
+                                  ((type) == GLB_DISRST_ISO11898))
+
+/** @defgroup  GLB_PKA_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_MCU_BCLK) || \
+                                   ((type) == GLB_PKA_CLK_MCU_MUXPLL_160M))
+
+/** @defgroup  GLB_MCU_SW_SYSTEM_TYPE
+ *  @{
+ */
+#define IS_GLB_MCU_SW_SYSTEM_TYPE(type) (((type) == GLB_MCU_SW_SYSTEM_CTRL_MCU))
+
+/** @defgroup  BMX_ARB_TYPE
+ *  @{
+ */
+#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_ROUND_ROBIN) || \
+                               ((type) == BMX_ARB_FIX))
+
+/** @defgroup  BMX_LATCH_TYPE
+ *  @{
+ */
+#define IS_BMX_LATCH_TYPE(type) (((type) == BMX_LATCH_FIRST_ERROR) || \
+                                 ((type) == BMX_LATCH_LAST_ERROR))
+
+/** @defgroup  BMX_BUS_ERR_TYPE
+ *  @{
+ */
+#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+                                   ((type) == BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup  BMX_ERR_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \
+                                   ((type) == BMX_ERR_INT_ALL))
+
+/** @defgroup  BMX_TO_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \
+                                  ((type) == BMX_TO_INT_ALL))
+
+/** @defgroup  GLB_ETH_REF_CLK_OUT_TYPE
+ *  @{
+ */
+#define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \
+                                           ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M))
+
+/** @defgroup  GLB_EM_TYPE
+ *  @{
+ */
+#define IS_GLB_EM_TYPE(type) (((type) == GLB_WRAM160KB_EM0KB) ||  \
+                              ((type) == GLB_WRAM128KB_EM32KB) || \
+                              ((type) == GLB_WRAM96KB_EM64KB))
+
+/** @defgroup  GLB_ADC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUPLL) || \
+                                   ((type) == GLB_ADC_CLK_XCLK))
+
+/** @defgroup  GLB_DAC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_32M) || \
+                                   ((type) == GLB_DAC_CLK_XCLK))
+
+/** @defgroup  GLB_CHIP_CLK_INOUT_TYPE
+ *  @{
+ */
+#define IS_GLB_CHIP_CLK_INOUT_TYPE(type) (((type) == GLB_CHIP_CLK_INOUT_INPUT) || \
+                                          ((type) == GLB_CHIP_CLK_INOUT_OUTPUT))
+
+/** @defgroup  GLB_CHIP_CLK_OUT_0_TYPE
+ *  @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_0_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_0_CAM_REF_CLK) || \
+                                          ((type) == GLB_CHIP_CLK_OUT_0_I2S_REF_CLK) || \
+                                          ((type) == GLB_CHIP_CLK_OUT_0_NONE) ||        \
+                                          ((type) == GLB_CHIP_CLK_OUT_0_SOLO_IN_128FS))
+
+/** @defgroup  GLB_CHIP_CLK_OUT_1_TYPE
+ *  @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_1_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_1_CAM_REF_CLK) || \
+                                          ((type) == GLB_CHIP_CLK_OUT_1_I2S_REF_CLK) || \
+                                          ((type) == GLB_CHIP_CLK_OUT_1_NONE) ||        \
+                                          ((type) == GLB_CHIP_CLK_OUT_1_SOLO_IN_128FS))
+
+/** @defgroup  GLB_CHIP_CLK_OUT_2_TYPE
+ *  @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_2_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_2_CAM_REF_CLK) ||  \
+                                          ((type) == GLB_CHIP_CLK_OUT_2_I2S_REF_CLK) ||  \
+                                          ((type) == GLB_CHIP_CLK_OUT_2_ANA_XTAL_CLK) || \
+                                          ((type) == GLB_CHIP_CLK_OUT_2_WIFIPLL_32M))
+
+/** @defgroup  GLB_CHIP_CLK_OUT_3_TYPE
+ *  @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_3_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_3_CAM_REF_CLK) || \
+                                          ((type) == GLB_CHIP_CLK_OUT_3_I2S_REF_CLK) || \
+                                          ((type) == GLB_CHIP_CLK_OUT_3_NONE) ||        \
+                                          ((type) == GLB_CHIP_CLK_OUT_3_WIFIPLL_48M))
+
+/** @defgroup  GLB_DIG_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_WIFIPLL_32M) || \
+                                   ((type) == GLB_DIG_CLK_XCLK) ||        \
+                                   ((type) == GLB_DIG_CLK_AUPLL))
+
+/** @defgroup  GLB_512K_CLK_OUT_TYPE
+ *  @{
+ */
+#define IS_GLB_512K_CLK_OUT_TYPE(type) (((type) == GLB_512K_CLK_OUT_512K) || \
+                                        ((type) == GLB_512K_CLK_OUT_256K) || \
+                                        ((type) == GLB_512K_CLK_OUT_128K))
+
+/** @defgroup  GLB_BT_BANDWIDTH_TYPE
+ *  @{
+ */
+#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \
+                                        ((type) == GLB_BT_BANDWIDTH_2M))
+
+/** @defgroup  GLB_UART_SIG_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) ||  \
+                                    ((type) == GLB_UART_SIG_1) ||  \
+                                    ((type) == GLB_UART_SIG_2) ||  \
+                                    ((type) == GLB_UART_SIG_3) ||  \
+                                    ((type) == GLB_UART_SIG_4) ||  \
+                                    ((type) == GLB_UART_SIG_5) ||  \
+                                    ((type) == GLB_UART_SIG_6) ||  \
+                                    ((type) == GLB_UART_SIG_7) ||  \
+                                    ((type) == GLB_UART_SIG_8) ||  \
+                                    ((type) == GLB_UART_SIG_9) ||  \
+                                    ((type) == GLB_UART_SIG_10) || \
+                                    ((type) == GLB_UART_SIG_11))
+
+/** @defgroup  GLB_UART_SIG_FUN_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_N_ISO11898_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_RESERVED)  || \
+                                        ((type) == GLB_UART_SIG_FUN_ISO11898_TXD)   || \
+                                        ((type) == GLB_UART_SIG_FUN_ISO11898_RXD))
+
+/** @defgroup  GLB_XTAL_TYPE
+ *  @{
+ */
+#define IS_GLB_XTAL_TYPE(type) (((type) == GLB_XTAL_NONE) ||  \
+                                ((type) == GLB_XTAL_24M) ||   \
+                                ((type) == GLB_XTAL_32M) ||   \
+                                ((type) == GLB_XTAL_38P4M) || \
+                                ((type) == GLB_XTAL_40M) ||   \
+                                ((type) == GLB_XTAL_26M) ||   \
+                                ((type) == GLB_XTAL_RC32M) || \
+                                ((type) == GLB_XTAL_MAX))
+
+/** @defgroup  GLB_PLL_TYPE
+ *  @{
+ */
+#define IS_GLB_PLL_TYPE(type) (((type) == GLB_PLL_NONE) ||    \
+                               ((type) == GLB_PLL_WIFIPLL) || \
+                               ((type) == GLB_PLL_AUPLL))
+
+/** @defgroup  GLB_WA_PLL_TYPE
+ *  @{
+ */
+#define IS_GLB_WA_PLL_TYPE(type) (((type) == GLB_WA_PLL_WIFIPLL) || \
+                                   ((type) == GLB_WA_PLL_AUPLL))
+
+/** @defgroup  GLB_PSRAMB_PLL_TYPE
+ *  @{
+ */
+#define IS_GLB_PSRAMB_PLL_TYPE(type) (((type) == GLB_PSRAMB_EMI_WIFIPLL_320M) ||  \
+                                      ((type) == GLB_PSRAMB_EMI_AUPLL_DIV1))
+
+/** @defgroup  GLB_UART_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_CLK_TYPE(type) (((type) == GLB_UART_CLK_BCLK) || \
+                                    ((type) == GLB_UART_CLK_PLL_160M))
+
+/** @defgroup  GLB_I2S_DI_REF_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_I2S_DI_REF_CLK_TYPE(type) (((type) == GLB_I2S_DI_SEL_I2S_DI_INPUT) || \
+                                          ((type) == GLB_I2S_DI_SEL_I2S_REF_OUTPUT))
+
+/** @defgroup  GLB_SPI_SIG_SWAP_GRP_TYPE
+ *  @{
+ */
+#define IS_GLB_SPI_SIG_SWAP_GRP_TYPE(type) (((type) == GLB_SPI_SIG_SWAP_GRP_GPIO0_GPIO11) ||  \
+                                            ((type) == GLB_SPI_SIG_SWAP_GRP_GPIO12_GPIO23) || \
+                                            ((type) == GLB_SPI_SIG_SWAP_GRP_GPIO24_GPIO35) || \
+                                            ((type) == GLB_SPI_SIG_SWAP_GRP_GPIO36_GPIO45))
+
+/** @defgroup  GLB_I2S_DO_REF_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_I2S_DO_REF_CLK_TYPE(type) (((type) == GLB_I2S_DO_SEL_I2S_DO_OUTPT) || \
+                                          ((type) == GLB_I2S_DO_SEL_I2S_REF_OUTPUT))
+
+#define IS_GLB_SLAVE_GRP_0_TYPE(type) (((type) == GLB_SLAVE_GRP_0_ADC) || \
+                                       ((type) == GLB_SLAVE_GRP_0_IR) || \
+                                       ((type) == GLB_SLAVE_GRP_0_I2C) || \
+                                       ((type) == GLB_SLAVE_GRP_0_SPI) || \
+                                       ((type) == GLB_SLAVE_GRP_0_PEC) || \
+                                       ((type) == GLB_SLAVE_GRP_0_DBI) || \
+                                       ((type) == GLB_SLAVE_GRP_0_AUDIO_AUTO) || \
+                                       ((type) == GLB_SLAVE_GRP_0_AUDIO_ADC) || \
+                                       ((type) == GLB_SLAVE_GRP_0_AUDIO_SOLO) || \
+                                       ((type) == GLB_SLAVE_GRP_0_CAM) || \
+                                       ((type) == GLB_SLAVE_GRP_0_SDH) || \
+                                       ((type) == GLB_SLAVE_GRP_0_PSRAMB) || \
+                                       ((type) == GLB_SLAVE_GRP_0_MAX))
+
+/*@} end of group GLB_Public_Constants */
+
+/** @defgroup  GLB_Public_Macros
+ *  @{
+ */
+#define UART_SIG_SWAP_NONE          (0x00) /* uart_sig[0:11] -> uart_sig[0:11] */
+#define UART_SIG_SWAP_GPIO0_GPIO11  (0x01) /* GPIO0-11  uart_sig[ 0:11] -> uart_sig[ 6:11], uart_sig[ 0: 5] */
+#define UART_SIG_SWAP_GPIO12_GPIO23 (0x02) /* GPIO12-23 uart_sig[12:23] -> uart_sig[18:23], uart_sig[12:17] */
+#define UART_SIG_SWAP_GPIO24_GPIO35 (0x04) /* GPIO24-35 uart_sig[24:35] -> uart_sig[30:35], uart_sig[24:29] */
+#define UART_SIG_SWAP_GPIO36_GPIO47 (0x08) /* GPIO36-47 uart_sig[36:47] -> uart_sig[42:47], uart_sig[36:41] */
+
+#define JTAG_SIG_SWAP_NONE 0x00 /* GPIO0-22  E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+
+#define GLB_AHB_CLOCK_CPU               (1ULL<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_GLB_GPIO_H__
+#define __BL616_GLB_GPIO_H__
+
+#include "glb_reg.h"
+#include "mm_glb_reg.h"
+#include "pds_reg.h"
+#include "bl616_gpio.h"
+#include "bl616_hbn.h"
+#include "bl616_aon.h"
+#include "bl616_pds.h"
+#include "bl616_common.h"
+#include "bflb_sf_ctrl.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB_GPIO
+ *  @{
+ */
+
+/** @defgroup  GLB_GPIO_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief GLB GPIO interrupt control mode type definition
+ */
+typedef enum {
+    GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE = 0,        /*!< GPIO interrupt sync mode, GPIO falling edge trigger interrupt */
+    GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE = 1,         /*!< GPIO interrupt sync mode, GPIO rising edge trigger interrupt */
+    GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL = 2,           /*!< GPIO interrupt sync mode, GPIO low level trigger interrupt (32k 3T) */
+    GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL = 3,          /*!< GPIO interrupt sync mode, GPIO high level trigger interrupt (32k 3T) */
+    GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE = 4, /*!< GPIO interrupt sync mode, GPIO falling and rising edge trigger interrupt */
+    GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE = 8,       /*!< GPIO interrupt async mode, GPIO falling edge trigger interrupt */
+    GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE = 9,        /*!< GPIO interrupt async mode, GPIO rising edge trigger interrupt */
+    GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL = 10,         /*!< GPIO interrupt async mode, GPIO low level trigger interrupt (32k 3T) */
+    GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL = 11,        /*!< GPIO interrupt async mode, GPIO high level trigger interrupt (32k 3T) */
+} GLB_GPIO_INT_TRIG_Type;
+
+/**
+ *  @brief GLB GPIO FIFO interrupt type definition
+ */
+typedef enum {
+    GLB_GPIO_FIFO_INT_FER,  /*!< GLB GPIO FIFO Underflow or Overflow interrupt */
+    GLB_GPIO_FIFO_INT_FIFO, /*!< GLB GPIO FIFO ready (tx_fifo_cnt > tx_fifo_th) interrupt */
+    GLB_GPIO_FIFO_INT_END,  /*!< GLB GPIO FIFO Empty interrupt */
+    GLB_GPIO_FIFO_INT_ALL,  /*!< All the interrupt */
+} GLB_GPIO_FIFO_INT_Type;
+
+/**
+ *  @brief GLB GPIO FIFO Timing Phase type definition
+ */
+typedef enum {
+    GPIO_FIFO_PHASE_FIRST_HIGH, /*!< GPIO first send high level */
+    GPIO_FIFO_PHASE_FIRST_LOW,  /*!< GPIO first send low level */
+} GLB_GPIO_FIFO_PHASE_Type;
+
+/**
+ *  @brief GLB GPIO FIFO Idle State type definition
+ */
+typedef enum {
+    GPIO_FIFO_IDLE_LOW,
+    GPIO_FIFO_IDLE_HIGH,
+} GLB_GPIO_FIFO_IDLE_Type;
+
+/**
+ *  @brief GLB GPIO FIFO Latch Mode type definition
+ */
+typedef enum {
+    GPIO_FIFO_LATCH_WRITE,    /*!< GPIO FIFO direct write I/O */
+    GPIO_FIFO_LATCH_SETCLEAR, /*!< GPIO FIFO set/clr I/O */
+} GLB_GPIO_FIFO_LATCH_Type;
+
+/**
+ *  @brief GPIO interrupt configuration structure type definition
+ */
+typedef struct
+{
+    GLB_GPIO_Type gpioPin;       /*!< GPIO pin num */
+    GLB_GPIO_INT_TRIG_Type trig; /*!< GPIO interrupt trig mode */
+    BL_Mask_Type intMask;        /*!< GPIO interrupt mask config */
+} GLB_GPIO_INT_Cfg_Type;
+
+/**
+ *  @brief UART configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t code0FirstTime;              /*!< The clock num of code0 first send */
+    uint8_t code1FirstTime;              /*!< The clock num of code1 first send */
+    uint16_t codeTotalTime;              /*!< The total clock num of code0/1(high + low */
+    GLB_GPIO_FIFO_PHASE_Type code0Phase; /*!< low or high level of code0 first send */
+    GLB_GPIO_FIFO_PHASE_Type code1Phase; /*!< low or high level of code1 first send */
+    GLB_GPIO_FIFO_IDLE_Type idle;        /*!< the I/O idle level */
+    uint8_t fifoDmaThreshold;            /*!< FIFO threshold */
+    BL_Fun_Type fifoDmaEnable;           /*!< Enable or disable DMA of GPIO */
+    GLB_GPIO_FIFO_LATCH_Type latch;      /*!< Write or set/clr GPIO level */
+} GLB_GPIO_FIFO_CFG_Type;
+
+/*@} end of group GLB_GPIO_Public_Types */
+
+/** @defgroup  GLB_GPIO_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  GLB_GPIO_INT_TRIG_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_SYNC_FALLING_EDGE) ||         \
+                                         ((type) == GLB_GPIO_INT_TRIG_SYNC_RISING_EDGE) ||          \
+                                         ((type) == GLB_GPIO_INT_TRIG_SYNC_LOW_LEVEL) ||            \
+                                         ((type) == GLB_GPIO_INT_TRIG_SYNC_HIGH_LEVEL) ||           \
+                                         ((type) == GLB_GPIO_INT_TRIG_SYNC_FALLING_RISING_EDGE) ||  \
+                                         ((type) == GLB_GPIO_INT_TRIG_ASYNC_FALLING_EDGE) ||        \
+                                         ((type) == GLB_GPIO_INT_TRIG_ASYNC_RISING_EDGE) ||         \
+                                         ((type) == GLB_GPIO_INT_TRIG_ASYNC_LOW_LEVEL) ||           \
+                                         ((type) == GLB_GPIO_INT_TRIG_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  GLB_GPIO_INT_TRIG_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_FIFO_INT_TYPE(type) (((type) == GLB_GPIO_FIFO_INT_FER) ||  \
+                                         ((type) == GLB_GPIO_FIFO_INT_FIFO) || \
+                                         ((type) == GLB_GPIO_FIFO_INT_END) ||  \
+                                         ((type) == GLB_GPIO_FIFO_INT_ALL))
+
+/** @defgroup  GLB_GPIO_FIFO_PHASE_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_FIFO_PHASE_TYPE(type) (((type) == GPIO_FIFO_PHASE_FIRST_HIGH) || \
+                                           ((type) == GPIO_FIFO_PHASE_FIRST_LOW))
+
+/** @defgroup  GLB_GPIO_FIFO_PHASE_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_FIFO_LATCH_TYPE(type) (((type) == GPIO_FIFO_LATCH_WRITE) || \
+                                           ((type) == GPIO_FIFO_LATCH_SETCLEAR))
+
+/*@} end of group GLB_GPIO_Public_Constants */
+
+/** @defgroup  GLB_GPIO_Public_Macros
+ *  @{
+ */
+
+/*@} end of group GLB_GPIO_Public_Macros */
+
+/** @defgroup  GLB_GPIO_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_INT0_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg);
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt);
+BL_Err_Type GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Embedded_Flash_Pad_Enable(uint8_t swapIo2Cs);
+BL_Err_Type GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
+uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val);
+BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg);
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void);
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
+
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_FIFO_IRQHandler(void);
+#endif
+BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type GLB_GPIO_Fifo_IRQHandler_Install(void);
+BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg);
+BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len);
+uint32_t GLB_GPIO_Fifo_GetCount(void);
+BL_Err_Type GLB_GPIO_Fifo_Clear(void);
+BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask);
+BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType);
+BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType);
+BL_Err_Type GLB_GPIO_Fifo_Enable(void);
+BL_Err_Type GLB_GPIO_Fifo_Disable(void);
+
+/*@} end of group GLB_GPIO_Public_Functions */
+
+/*@} end of group GLB_GPIO */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_GLB_GPIO_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_gpio.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_gpio.h
new file mode 100755
index 0000000000..e687b278c4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_gpio.h
@@ -0,0 +1,148 @@
+/**
+  ******************************************************************************
+  * @file    bl616_gpio.h
+  * @version V1.0
+  * @date    2020-11-06
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_GPIO_H__
+#define __BL616_GPIO_H__
+
+typedef enum {
+    GLB_GPIO_PIN_0 = 0,
+    GLB_GPIO_PIN_1,
+    GLB_GPIO_PIN_2,
+    GLB_GPIO_PIN_3,
+    GLB_GPIO_PIN_4,
+    GLB_GPIO_PIN_5,
+    GLB_GPIO_PIN_6,
+    GLB_GPIO_PIN_7,
+    GLB_GPIO_PIN_8,
+    GLB_GPIO_PIN_9,
+    GLB_GPIO_PIN_10,
+    GLB_GPIO_PIN_11,
+    GLB_GPIO_PIN_12,
+    GLB_GPIO_PIN_13,
+    GLB_GPIO_PIN_14,
+    GLB_GPIO_PIN_15,
+    GLB_GPIO_PIN_16,
+    GLB_GPIO_PIN_17,
+    GLB_GPIO_PIN_18,
+    GLB_GPIO_PIN_19,
+    GLB_GPIO_PIN_20,
+    GLB_GPIO_PIN_21,
+    GLB_GPIO_PIN_22,
+    GLB_GPIO_PIN_23,
+    GLB_GPIO_PIN_24,
+    GLB_GPIO_PIN_25,
+    GLB_GPIO_PIN_26,
+    GLB_GPIO_PIN_27,
+    GLB_GPIO_PIN_28,
+    GLB_GPIO_PIN_29,
+    GLB_GPIO_PIN_30,
+    GLB_GPIO_PIN_31,
+    GLB_GPIO_PIN_32,
+    GLB_GPIO_PIN_33,
+    GLB_GPIO_PIN_34,
+    GLB_GPIO_PIN_MAX,
+} GLB_GPIO_Type;
+
+#define GPIO_MODE_INPUT            ((uint32_t)0x00000000U) /*!< Input Floating Mode                   */
+#define GPIO_MODE_OUTPUT           ((uint32_t)0x00000001U) /*!< Output Push Pull Mode                 */
+#define GPIO_MODE_AF               ((uint32_t)0x00000002U) /*!< Alternate function                    */
+#define GPIO_MODE_ANALOG           ((uint32_t)0x00000003U) /*!< Analog function                       */
+#define GPIO_PULL_UP               ((uint32_t)0x00000000U) /*!< GPIO pull up                          */
+#define GPIO_PULL_DOWN             ((uint32_t)0x00000001U) /*!< GPIO pull down                        */
+#define GPIO_PULL_NONE             ((uint32_t)0x00000002U) /*!< GPIO no pull up or down               */
+#define GPIO_OUTPUT_VALUE_MODE     ((uint8_t)0x00U)        /*!< GPIO Output by reg_gpio_x_o Value                             */
+#define GPIO_SET_CLR_MODE          ((uint8_t)0x01U)        /*!< GPIO Output set by reg_gpio_x_set and clear by reg_gpio_x_clr */
+#define GPIO_DMA_OUTPUT_VALUE_MODE ((uint8_t)0x02U)        /*!< GPIO Output value by gpio_dma_o                               */
+#define GPIO_DMA_SET_CLR_MODE      ((uint8_t)0x03U)        /*!< GPIO Outout value by gpio_dma_set/gpio_dma_clr                */
+
+typedef enum {
+    GPIO_FUN_SDH = 0,
+    GPIO_FUN_SPI = 1,
+    GPIO_FUN_FLASH = 2,
+    GPIO_FUN_I2S = 3,
+    GPIO_FUN_PDM = 4,
+    GPIO_FUN_I2C0 = 5,
+    GPIO_FUN_I2C1 = 6,
+    GPIO_FUN_UART = 7,
+    GPIO_FUN_ETHER_MAC = 8,
+    GPIO_FUN_CAM = 9,
+    GPIO_FUN_ANALOG = 10,
+    GPIO_FUN_GPIO = 11,
+    GPIO_FUN_SDIO = 12,
+    GPIO_FUN_PWM0 = 16,
+    GPIO_FUN_MD_JTAG = 17,
+    GPIO_FUN_MD_UART = 18,
+    GPIO_FUN_MD_PWM = 19,
+    GPIO_FUN_MD_SPI = 20,
+    GPIO_FUN_MD_I2S = 21,
+    GPIO_FUN_DBI_B = 22,
+    GPIO_FUN_DBI_C = 23,
+    GPIO_FUN_DISP_QSPI = 24,
+    GPIO_FUN_AUDAC_PWM = 25,
+    GPIO_FUN_JTAG = 26,
+    GPIO_FUN_CLOCK_OUT = 31,
+
+    GPIO_FUN_CLOCK_OUT_X_CAM_REF_CLK = 0xE0,
+    GPIO_FUN_CLOCK_OUT_X_I2S_REF_CLK = 0xE1,
+    GPIO_FUN_CLOCK_OUT_0_1_3_NONE = 0xE2,
+    GPIO_FUN_CLOCK_OUT_0_1_SOLO_128FS_CLK = 0xE3,
+    GPIO_FUN_CLOCK_OUT_2_ANA_XTAL_CLK = 0xE3,
+    GPIO_FUN_CLOCK_OUT_2_WIFI_32M_CLK = 0xE3,
+    GPIO_FUN_CLOCK_OUT_3_WIFI_48M_CLK = 0xE3,
+
+    GPIO_FUN_UART0_RTS = 0xF0,
+    GPIO_FUN_UART0_CTS = 0xF1,
+    GPIO_FUN_UART0_TX = 0xF2,
+    GPIO_FUN_UART0_RX = 0xF3,
+    GPIO_FUN_UART1_RTS = 0xF4,
+    GPIO_FUN_UART1_CTS = 0xF5,
+    GPIO_FUN_UART1_TX = 0xF6,
+    GPIO_FUN_UART1_RX = 0xF7,
+
+    GPIO_FUN_UNUSED = 0xFF,
+} GLB_GPIO_FUNC_Type;
+
+typedef struct
+{
+    uint8_t gpioPin;
+    uint8_t gpioFun;
+    uint8_t gpioMode;
+    uint8_t pullType;
+    uint8_t drive;
+    uint8_t smtCtrl;
+    uint8_t outputMode;
+} GLB_GPIO_Cfg_Type;
+
+#endif /*__BL616_GPIO_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_hbn.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_hbn.h
new file mode 100755
index 0000000000..e40187375a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_hbn.h
@@ -0,0 +1,687 @@
+/**
+  ******************************************************************************
+  * @file    bl616_hbn.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_HBN_H__
+#define __BL616_HBN_H__
+
+#include "hbn_reg.h"
+#include "bl616_aon.h"
+#include "bl616_l1c.h"
+#include "bl616_common.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief HBN PIR interrupt configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type lowIntEn;  /*!< Low will trigger interrupt */
+    BL_Fun_Type highIntEn; /*!< High will trigger interrupt */
+} HBN_PIR_INT_CFG_Type;
+
+/**
+ *  @brief HBN PIR low pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */
+    HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */
+} HBN_PIR_LPF_Type;
+
+/**
+ *  @brief HBN PIR high pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */
+    HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */
+    HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */
+} HBN_PIR_HPF_Type;
+
+/**
+ *  @brief HBN flash pad pu pd type
+ */
+typedef enum {
+    HBN_FLASH_PAD_PULL_NONE, /*!< flash pad pull none when Flash at Deep Power Down Mode */
+    HBN_FLASH_PAD_PULL_UP,   /*!< flash pad pull up when Flash at Deep Power Down Mode */
+    HBN_FLASH_PAD_PULL_DOWN, /*!< flash pad pull down when Flash at Deep Power Down Mode */
+} HBN_FLASH_PAD_PULL_Type;
+
+/**
+ *  @brief HBN BOD threshold type definition
+ */
+typedef enum {
+    HBN_BOD_THRES_2P05V, /*!< BOD threshold 2.05V */
+    HBN_BOD_THRES_2P10V, /*!< BOD threshold 2.10V */
+    HBN_BOD_THRES_2P15V, /*!< BOD threshold 2.15V */
+    HBN_BOD_THRES_2P20V, /*!< BOD threshold 2.20V */
+    HBN_BOD_THRES_2P25V, /*!< BOD threshold 2.25V */
+    HBN_BOD_THRES_2P30V, /*!< BOD threshold 2.30V */
+    HBN_BOD_THRES_2P35V, /*!< BOD threshold 2.35V */
+    HBN_BOD_THRES_2P40V, /*!< BOD threshold 2.40V */
+} HBN_BOD_THRES_Type;
+
+/**
+ *  @brief HBN BOD mode type definition
+ */
+typedef enum {
+    HBN_BOD_MODE_POR_INDEPENDENT, /*!< POR is independent of BOD */
+    HBN_BOD_MODE_POR_RELEVANT,    /*!< POR is relevant to BOD */
+} HBN_BOD_MODE_Type;
+
+/**
+ *  @brief HBN 32K clock type definition
+ */
+typedef enum {
+    HBN_32K_RC = 0,  /*!< HBN use rc 32k */
+    HBN_32K_XTAL,    /*!< HBN use xtal 32k */
+    HBN_32K_DIG = 3, /*!< HBN use dig 32k */
+} HBN_32K_CLK_Type;
+
+/**
+ *  @brief HBN xclk clock type definition
+ */
+typedef enum {
+    HBN_MCU_XCLK_RC32M, /*!< use RC32M as xclk clock */
+    HBN_MCU_XCLK_XTAL,  /*!< use XTAL as xclk clock */
+} HBN_MCU_XCLK_Type;
+
+/**
+ *  @brief HBN GPADC clock type definition
+ */
+typedef enum {
+    HBN_GPADC_CLK_32M,  /*!< use gpadc_32m_clk as clock */
+    HBN_GPADC_CLK_F32K, /*!< use f32k_clk as clock */
+} HBN_GPADC_CLK_Type;
+
+/**
+ *  @brief HBN root clock type definition
+ */
+typedef enum {
+    HBN_MCU_ROOT_CLK_XCLK, /*!< use XCLK as root clock */
+    HBN_MCU_ROOT_CLK_PLL,  /*!< use PLL as root clock */
+} HBN_MCU_ROOT_CLK_Type;
+
+/**
+ *  @brief HBN UART clock type definition
+ */
+typedef enum {
+    HBN_UART_CLK_MCU_BCLK = 0, /*!< Select mcu_pbclk as UART clock */
+    HBN_UART_CLK_MUXPLL_160M,  /*!< Select MUXPLL 160M as UART clock */
+    HBN_UART_CLK_XCLK,         /*!< Select XCLK as UART clock */
+} HBN_UART_CLK_Type;
+
+/**
+ *  @brief HBN RTC interrupt delay type definition
+ */
+typedef enum {
+    HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */
+    HBN_RTC_INT_DELAY_0T = 1,  /*!< HBN RTC interrupt delay 0T */
+} HBN_RTC_INT_Delay_Type;
+
+/**
+ *  @brief HBN interrupt type definition
+ */
+typedef enum {
+    HBN_INT_GPIO16 = 0,  /*!< HBN interrupt type: GPIO16 */
+    HBN_INT_GPIO17 = 1,  /*!< HBN interrupt type: GPIO17 */
+    HBN_INT_GPIO18 = 2,  /*!< HBN interrupt type: GPIO18 */
+    HBN_INT_GPIO19 = 3,  /*!< HBN interrupt type: GPIO19 */
+    HBN_INT_RTC = 16,    /*!< HBN interrupt type: RTC */
+    HBN_INT_PIR = 17,    /*!< HBN interrupt type: PIR */
+    HBN_INT_BOD = 18,    /*!< HBN interrupt type: BOD */
+    HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */
+    HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */
+} HBN_INT_Type;
+
+/**
+ *  @brief HBN aon pad type definition
+ */
+typedef enum {
+    HBN_AON_PAD_GPIO16 = 0, /*!< HBN aon pad type: GPIO16 */
+    HBN_AON_PAD_GPIO17 = 1, /*!< HBN aon pad type: GPIO17 */
+    HBN_AON_PAD_GPIO18 = 2, /*!< HBN aon pad type: GPIO18 */
+    HBN_AON_PAD_GPIO19 = 3, /*!< HBN aon pad type: GPIO19 */
+} HBN_AON_PAD_Type;
+
+/**
+ *  @brief HBN AON PAD configuration type definition
+ */
+typedef struct
+{
+    uint8_t ctrlEn;   /*!< AON PAD Control by AON HW */
+    uint8_t ie;       /*!< Always on PAD IE/SMT (if corresponding  AON GPIO controlled by AON HW) */
+    uint8_t oe;       /*!< Always on PAD OE (if corresponding  AON GPIO controlled by AON HW)     */
+    uint8_t pullUp;   /*!< Always on PAD PU (if corresponding  AON GPIO controlled by AON HW)     */
+    uint8_t pullDown; /*!< Always on PAD PD (if corresponding  AON GPIO controlled by AON HW)     */
+} HBN_AON_PAD_CFG_Type;
+
+/**
+ *  @brief HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE = 0x0,        /*!< HBN GPIO INT trigger type: sync falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE = 0x1,         /*!< HBN GPIO INT trigger type: sync rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL = 0x2,           /*!< HBN GPIO INT trigger type: sync low level trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL = 0x3,          /*!< HBN GPIO INT trigger type: sync high level trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_RISING_FALLING_EDGE = 0x4, /*!< HBN GPIO INT trigger type: sync rising falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE = 0x8,       /*!< HBN GPIO INT trigger type: async falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE = 0x9,        /*!< HBN GPIO INT trigger type: async rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL = 0xA,          /*!< HBN GPIO INT trigger type: async low level trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL = 0xB,         /*!< HBN GPIO INT trigger type: async high level trigger */
+} HBN_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT0_INT_GPIO16 = 0, /*!< HBN out 0 interrupt type: GPIO16 */
+    HBN_OUT0_INT_GPIO17 = 1, /*!< HBN out 0 interrupt type: GPIO17 */
+    HBN_OUT0_INT_GPIO18 = 2, /*!< HBN out 0 interrupt type: GPIO18 */
+    HBN_OUT0_INT_GPIO19 = 3, /*!< HBN out 0 interrupt type: GPIO19 */
+    HBN_OUT0_INT_RTC,        /*!< HBN out 0 interrupt type: RTC */
+    HBN_OUT0_INT_MAX,        /*!< MAX */
+} HBN_OUT0_INT_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT1_INT_PIR,    /*!< HBN out 1 interrupt type: PIR */
+    HBN_OUT1_INT_BOD,    /*!< HBN out 1 interrupt type: BOD */
+    HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */
+    HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */
+    HBN_OUT1_INT_MAX,    /*!< MAX */
+} HBN_OUT1_INT_Type;
+
+/**
+ *  @brief HBN acomp interrupt type definition
+ */
+typedef enum {
+    HBN_ACOMP_INT_EDGE_POSEDGE = 1,         /*!< HBN acomp interrupt edge posedge */
+    HBN_ACOMP_INT_EDGE_NEGEDGE = 2,         /*!< HBN acomp interrupt edge negedge */
+    HBN_ACOMP_INT_EDGE_POSEDGE_NEGEDGE = 3, /*!< HBN acomp interrupt edge posedge and negedge */
+} HBN_ACOMP_INT_EDGE_Type;
+
+/**
+ *  @brief HBN LDO level type definition
+ */
+typedef enum {
+    HBN_LDO_LEVEL_0P70V = 2,  /*!< HBN LDO voltage 0.70V */
+    HBN_LDO_LEVEL_0P75V = 3,  /*!< HBN LDO voltage 0.75V */
+    HBN_LDO_LEVEL_0P80V = 4,  /*!< HBN LDO voltage 0.80V */
+    HBN_LDO_LEVEL_0P85V = 5,  /*!< HBN LDO voltage 0.85V */
+    HBN_LDO_LEVEL_0P90V = 6,  /*!< HBN LDO voltage 0.90V */
+    HBN_LDO_LEVEL_0P95V = 7,  /*!< HBN LDO voltage 0.95V */
+    HBN_LDO_LEVEL_1P00V = 8,  /*!< HBN LDO voltage 1.00V */
+    HBN_LDO_LEVEL_1P05V = 9,  /*!< HBN LDO voltage 1.05V */
+    HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */
+    HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */
+    HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */
+    HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */
+    HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */
+    HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */
+} HBN_LDO_LEVEL_Type;
+
+/**
+ *  @brief HBN level type definition
+ */
+typedef enum {
+    HBN_LEVEL_0, /*!< HBN pd_core */
+    HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */
+} HBN_LEVEL_Type;
+
+/**
+ *  @brief HBN BOD configuration type definition
+ */
+typedef struct
+{
+    uint8_t enableBod;      /*!< Enable BOD or not */
+    uint8_t enableBodInt;   /*!< Enable BOD interrupt or not */
+    uint8_t bodThreshold;   /*!< BOD threshold */
+    uint8_t enablePorInBod; /*!< Enable POR when BOD occure or not */
+} HBN_BOD_CFG_Type;
+
+/**
+ *  @brief HBN APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t useXtal32k;                     /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint32_t sleepTime;                     /*!< HBN sleep time */
+    uint8_t gpioWakeupSrc;                  /*!< GPIO Wakeup source */
+    HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
+    spi_flash_cfg_type *flashCfg;           /*!< Flash config pointer, used when power down flash */
+    HBN_LEVEL_Type hbnLevel;                /*!< HBN level */
+    HBN_LDO_LEVEL_Type ldoLevel;            /*!< LDO level */
+    uint8_t dcdcPuSeq;                      /*!< power on dcdc sequence */
+} HBN_APP_CFG_Type;
+
+/*@} end of group HBN_Public_Types */
+
+/** @defgroup  HBN_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  HBN_PIR_LPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \
+                                   ((type) == HBN_PIR_LPF_DIV2))
+
+/** @defgroup  HBN_PIR_HPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \
+                                   ((type) == HBN_PIR_HPF_METHOD1) || \
+                                   ((type) == HBN_PIR_HPF_METHOD2))
+
+/** @defgroup  HBN_FLASH_PAD_PULL_TYPE
+ *  @{
+ */
+#define IS_HBN_FLASH_PAD_PULL_TYPE(type) (((type) == HBN_FLASH_PAD_PULL_NONE) || \
+                                          ((type) == HBN_FLASH_PAD_PULL_UP) ||   \
+                                          ((type) == HBN_FLASH_PAD_PULL_DOWN))
+
+/** @defgroup  HBN_BOD_THRES_TYPE
+ *  @{
+ */
+#define IS_HBN_BOD_THRES_TYPE(type) (((type) == HBN_BOD_THRES_2P05V) || \
+                                     ((type) == HBN_BOD_THRES_2P10V) || \
+                                     ((type) == HBN_BOD_THRES_2P15V) || \
+                                     ((type) == HBN_BOD_THRES_2P20V) || \
+                                     ((type) == HBN_BOD_THRES_2P25V) || \
+                                     ((type) == HBN_BOD_THRES_2P30V) || \
+                                     ((type) == HBN_BOD_THRES_2P35V) || \
+                                     ((type) == HBN_BOD_THRES_2P40V))
+
+/** @defgroup  HBN_BOD_MODE_TYPE
+ *  @{
+ */
+#define IS_HBN_BOD_MODE_TYPE(type) (((type) == HBN_BOD_MODE_POR_INDEPENDENT) || \
+                                    ((type) == HBN_BOD_MODE_POR_RELEVANT))
+
+/** @defgroup  HBN_32K_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) ||   \
+                                   ((type) == HBN_32K_XTAL) || \
+                                   ((type) == HBN_32K_DIG))
+
+/** @defgroup  HBN_MCU_XCLK_TYPE
+ *  @{
+ */
+#define IS_HBN_MCU_XCLK_TYPE(type) (((type) == HBN_MCU_XCLK_RC32M) || \
+                                    ((type) == HBN_MCU_XCLK_XTAL))
+
+/** @defgroup  HBN_GPADC_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_GPADC_CLK_TYPE(type) (((type) == HBN_GPADC_CLK_32M) || \
+                                     ((type) == HBN_GPADC_CLK_F32K))
+
+/** @defgroup  HBN_MCU_ROOT_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_MCU_ROOT_CLK_TYPE(type) (((type) == HBN_MCU_ROOT_CLK_XCLK) || \
+                                        ((type) == HBN_MCU_ROOT_CLK_PLL))
+
+/** @defgroup  HBN_UART_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_MCU_BCLK) ||    \
+                                    ((type) == HBN_UART_CLK_MUXPLL_160M) || \
+                                    ((type) == HBN_UART_CLK_XCLK))
+
+/** @defgroup  HBN_RTC_INT_DELAY_TYPE
+ *  @{
+ */
+#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \
+                                         ((type) == HBN_RTC_INT_DELAY_0T))
+
+/** @defgroup  HBN_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) ||  \
+                               ((type) == HBN_INT_GPIO10) || \
+                               ((type) == HBN_INT_GPIO11) || \
+                               ((type) == HBN_INT_GPIO12) || \
+                               ((type) == HBN_INT_GPIO13) || \
+                               ((type) == HBN_INT_GPIO14) || \
+                               ((type) == HBN_INT_GPIO15) || \
+                               ((type) == HBN_INT_GPIO40) || \
+                               ((type) == HBN_INT_GPIO41) || \
+                               ((type) == HBN_INT_RTC) ||    \
+                               ((type) == HBN_INT_PIR) ||    \
+                               ((type) == HBN_INT_BOD) ||    \
+                               ((type) == HBN_INT_ACOMP0) || \
+                               ((type) == HBN_INT_ACOMP1))
+
+/** @defgroup  HBN_AON_PAD_TYPE
+ *  @{
+ */
+#define IS_HBN_AON_PAD_TYPE(type) (((type) == HBN_AON_PAD_GPIO16) || \
+                                   ((type) == HBN_AON_PAD_GPIO17) || \
+                                   ((type) == HBN_AON_PAD_GPIO18) || \
+                                   ((type) == HBN_AON_PAD_GPIO19))
+
+/** @defgroup  HBN_ACOMP_INT_EDGE_TYPE
+ *  @{
+ */
+#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \
+                                          ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE) || \
+                                          ((type) == HBN_ACOMP_INT_EDGE_POSEDGE_NEGEDGE))
+
+/** @defgroup  HBN_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||        \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||         \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||           \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||          \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_FALLING_EDGE) || \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) ||       \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||        \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||          \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  HBN_OUT0_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) ||  \
+                                    ((type) == HBN_OUT0_INT_GPIO10) || \
+                                    ((type) == HBN_OUT0_INT_GPIO11) || \
+                                    ((type) == HBN_OUT0_INT_GPIO12) || \
+                                    ((type) == HBN_OUT0_INT_GPIO13) || \
+                                    ((type) == HBN_OUT0_INT_GPIO14) || \
+                                    ((type) == HBN_OUT0_INT_GPIO15) || \
+                                    ((type) == HBN_OUT0_INT_GPIO40) || \
+                                    ((type) == HBN_OUT0_INT_GPIO41) || \
+                                    ((type) == HBN_OUT0_INT_RTC) ||    \
+                                    ((type) == HBN_OUT0_INT_MAX))
+
+/** @defgroup  HBN_OUT1_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) ||    \
+                                    ((type) == HBN_OUT1_INT_BOD) ||    \
+                                    ((type) == HBN_OUT1_INT_ACOMP0) || \
+                                    ((type) == HBN_OUT1_INT_ACOMP1) || \
+                                    ((type) == HBN_OUT1_INT_MAX))
+
+/** @defgroup  HBN_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P70V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P75V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P80V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P85V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P90V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P95V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P00V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P05V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P10V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P15V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P20V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P25V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P30V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P35V))
+
+/** @defgroup  HBN_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \
+                                 ((type) == HBN_LEVEL_1))
+
+/*@} end of group HBN_Public_Constants */
+
+/** @defgroup  HBN_Public_Macros
+ *  @{
+ */
+#define HBN_RAM_SIZE               (4 * 1024)
+#define HBN_RTC_COMP_BIT0_39       0x01
+#define HBN_RTC_COMP_BIT0_23       0x02
+#define HBN_RTC_COMP_BIT13_39      0x04
+#define HBN_STATUS_ENTER_FLAG      0x4e424845
+#define HBN_STATUS_WAKEUP_FLAG     0x4e424857
+#define APP_JUMP_ENTER_FLAG        0x50504145
+#define APP_JUMP_DONE_FLAG         0x50504157
+#define HBN_RELEASE_CORE_FLAG      (0x4)
+#define HBN_LDO18IO_POWER_DLY_FLAG (0x52)
+#define HBN_XTAL_FLAG_VALUE        (0x8)
+#define HBN_FLASH_POWER_DLY_FLAG   (0x6)
+#define HBN_GPIO_KEEP_FLAG         (0x2)
+#define PDS_GPIO_KEEP_FLAG         (0x2)
+
+/* 0x108 : HBN_RSV2 */
+#define HBN_LDO18IO_POWER_ON_DLY       HBN_LDO18IO_POWER_ON_DLY
+#define HBN_LDO18IO_POWER_ON_DLY_POS   (0U)
+#define HBN_LDO18IO_POWER_ON_DLY_LEN   (11U)
+#define HBN_LDO18IO_POWER_ON_DLY_MSK   (((1U << HBN_LDO18IO_POWER_ON_DLY_LEN) - 1) << HBN_LDO18IO_POWER_ON_DLY_POS)
+#define HBN_LDO18IO_POWER_ON_DLY_UMSK  (~(((1U << HBN_LDO18IO_POWER_ON_DLY_LEN) - 1) << HBN_LDO18IO_POWER_ON_DLY_POS))
+#define HBN_LDO18IO_POWER_OFF_DLY      HBN_LDO18IO_POWER_OFF_DLY
+#define HBN_LDO18IO_POWER_OFF_DLY_POS  (11U)
+#define HBN_LDO18IO_POWER_OFF_DLY_LEN  (5U)
+#define HBN_LDO18IO_POWER_OFF_DLY_MSK  (((1U << HBN_LDO18IO_POWER_OFF_DLY_LEN) - 1) << HBN_LDO18IO_POWER_OFF_DLY_POS)
+#define HBN_LDO18IO_POWER_OFF_DLY_UMSK (~(((1U << HBN_LDO18IO_POWER_OFF_DLY_LEN) - 1) << HBN_LDO18IO_POWER_OFF_DLY_POS))
+#define HBN_LDO18IO_POWER_DLY_STS      HBN_LDO18IO_POWER_DLY_STS
+#define HBN_LDO18IO_POWER_DLY_STS_POS  (16U)
+#define HBN_LDO18IO_POWER_DLY_STS_LEN  (8U)
+#define HBN_LDO18IO_POWER_DLY_STS_MSK  (((1U << HBN_LDO18IO_POWER_DLY_STS_LEN) - 1) << HBN_LDO18IO_POWER_DLY_STS_POS)
+#define HBN_LDO18IO_POWER_DLY_STS_UMSK (~(((1U << HBN_LDO18IO_POWER_DLY_STS_LEN) - 1) << HBN_LDO18IO_POWER_DLY_STS_POS))
+#define HBN_CORE_UNHALT                HBN_CORE_UNHALT
+#define HBN_CORE_UNHALT_POS            (25U)
+#define HBN_CORE_UNHALT_LEN            (1U)
+#define HBN_CORE_UNHALT_MSK            (((1U << HBN_CORE_UNHALT_LEN) - 1) << HBN_CORE_UNHALT_POS)
+#define HBN_CORE_UNHALT_UMSK           (~(((1U << HBN_CORE_UNHALT_LEN) - 1) << HBN_CORE_UNHALT_POS))
+#define HBN_USER_BOOT_SEL              HBN_USER_BOOT_SEL
+#define HBN_USER_BOOT_SEL_POS          (26U)
+#define HBN_USER_BOOT_SEL_LEN          (2U)
+#define HBN_USER_BOOT_SEL_MSK          (((1U << HBN_USER_BOOT_SEL_LEN) - 1) << HBN_USER_BOOT_SEL_POS)
+#define HBN_USER_BOOT_SEL_UMSK         (~(((1U << HBN_USER_BOOT_SEL_LEN) - 1) << HBN_USER_BOOT_SEL_POS))
+#define HBN_RELEASE_CORE               HBN_RELEASE_CORE
+#define HBN_RELEASE_CORE_POS           (28U)
+#define HBN_RELEASE_CORE_LEN           (4U)
+#define HBN_RELEASE_CORE_MSK           (((1U << HBN_RELEASE_CORE_LEN) - 1) << HBN_RELEASE_CORE_POS)
+#define HBN_RELEASE_CORE_UMSK          (~(((1U << HBN_RELEASE_CORE_LEN) - 1) << HBN_RELEASE_CORE_POS))
+
+/* 0x108 : HBN_RSV3 */
+#define HBN_XTAL_TYPE            HBN_XTAL_TYPE
+#define HBN_XTAL_TYPE_POS        (0U)
+#define HBN_XTAL_TYPE_LEN        (4U)
+#define HBN_XTAL_TYPE_MSK        (((1U << HBN_XTAL_TYPE_LEN) - 1) << HBN_XTAL_TYPE_POS)
+#define HBN_XTAL_TYPE_UMSK       (~(((1U << HBN_XTAL_TYPE_LEN) - 1) << HBN_XTAL_TYPE_POS))
+#define HBN_XTAL_STS             HBN_XTAL_STS
+#define HBN_XTAL_STS_POS         (4U)
+#define HBN_XTAL_STS_LEN         (4U)
+#define HBN_XTAL_STS_MSK         (((1U << HBN_XTAL_STS_LEN) - 1) << HBN_XTAL_STS_POS)
+#define HBN_XTAL_STS_UMSK        (~(((1U << HBN_XTAL_STS_LEN) - 1) << HBN_XTAL_STS_POS))
+#define HBN_FLASH_POWER_DLY      HBN_FLASH_POWER_DLY
+#define HBN_FLASH_POWER_DLY_POS  (8U)
+#define HBN_FLASH_POWER_DLY_LEN  (8U)
+#define HBN_FLASH_POWER_DLY_MSK  (((1U << HBN_FLASH_POWER_DLY_LEN) - 1) << HBN_FLASH_POWER_DLY_POS)
+#define HBN_FLASH_POWER_DLY_UMSK (~(((1U << HBN_FLASH_POWER_DLY_LEN) - 1) << HBN_FLASH_POWER_DLY_POS))
+#define HBN_FLASH_POWER_STS      HBN_FLASH_POWER_STS
+#define HBN_FLASH_POWER_STS_POS  (16U)
+#define HBN_FLASH_POWER_STS_LEN  (4U)
+#define HBN_FLASH_POWER_STS_MSK  (((1U << HBN_FLASH_POWER_STS_LEN) - 1) << HBN_FLASH_POWER_STS_POS)
+#define HBN_FLASH_POWER_STS_UMSK (~(((1U << HBN_FLASH_POWER_STS_LEN) - 1) << HBN_FLASH_POWER_STS_POS))
+#define PDS_GPIO_KEEP_PIN        PDS_GPIO_KEEP_PIN
+#define PDS_GPIO_KEEP_PIN_POS    (20U)
+#define PDS_GPIO_KEEP_PIN_LEN    (4U)
+#define PDS_GPIO_KEEP_PIN_MSK    (((1U << PDS_GPIO_KEEP_PIN_LEN) - 1) << PDS_GPIO_KEEP_PIN_POS)
+#define PDS_GPIO_KEEP_PIN_UMSK   (~(((1U << PDS_GPIO_KEEP_PIN_LEN) - 1) << PDS_GPIO_KEEP_PIN_POS))
+#define HBN_GPIO_KEEP_PIN        HBN_GPIO_KEEP_PIN
+#define HBN_GPIO_KEEP_PIN_POS    (24U)
+#define HBN_GPIO_KEEP_PIN_LEN    (4U)
+#define HBN_GPIO_KEEP_PIN_MSK    (((1U << HBN_GPIO_KEEP_PIN_LEN) - 1) << HBN_GPIO_KEEP_PIN_POS)
+#define HBN_GPIO_KEEP_PIN_UMSK   (~(((1U << HBN_GPIO_KEEP_PIN_LEN) - 1) << HBN_GPIO_KEEP_PIN_POS))
+#define PDS_GPIO_KEEP_STS        PDS_GPIO_KEEP_STS
+#define PDS_GPIO_KEEP_STS_POS    (28U)
+#define PDS_GPIO_KEEP_STS_LEN    (2U)
+#define PDS_GPIO_KEEP_STS_MSK    (((1U << PDS_GPIO_KEEP_STS_LEN) - 1) << PDS_GPIO_KEEP_STS_POS)
+#define PDS_GPIO_KEEP_STS_UMSK   (~(((1U << PDS_GPIO_KEEP_STS_LEN) - 1) << PDS_GPIO_KEEP_STS_POS))
+#define HBN_GPIO_KEEP_STS        HBN_GPIO_KEEP_STS
+#define HBN_GPIO_KEEP_STS_POS    (30U)
+#define HBN_GPIO_KEEP_STS_LEN    (2U)
+#define HBN_GPIO_KEEP_STS_MSK    (((1U << HBN_GPIO_KEEP_STS_LEN) - 1) << HBN_GPIO_KEEP_STS_POS)
+#define HBN_GPIO_KEEP_STS_UMSK   (~(((1U << HBN_GPIO_KEEP_STS_LEN) - 1) << HBN_GPIO_KEEP_STS_POS))
+
+/*@} end of group HBN_Public_Macros */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void);
+void HBN_OUT1_IRQHandler(void);
+#endif
+/*----------*/
+void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
+void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg);
+void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq);
+BL_Err_Type HBN_Reset(void);
+/*----------*/
+BL_Err_Type HBN_Set_GPADC_CLK_Sel(HBN_GPADC_CLK_Type clkSel);
+BL_Err_Type HBN_PIR_Enable(void);
+BL_Err_Type HBN_PIR_Disable(void);
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg);
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf);
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf);
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold);
+uint16_t HBN_Get_PIR_Threshold(void);
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval);
+uint16_t HBN_Get_PIR_Interval(void);
+/*----------*/
+BL_Sts_Type HBN_Get_BOD_OUT_State(void);
+BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode);
+/*----------*/
+BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+/*----------*/
+BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
+HBN_MCU_XCLK_Type HBN_Get_MCU_XCLK_Sel(void);
+BL_Err_Type HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_Type xclk);
+HBN_MCU_ROOT_CLK_Type HBN_Get_MCU_Root_CLK_Sel(void);
+BL_Err_Type HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_Type rootClk);
+/*----------*/
+BL_Err_Type HBN_Set_HRAM_slp(void);
+BL_Err_Type HBN_Set_HRAM_Ret(void);
+/*----------*/
+uint32_t HBN_Get_Status_Flag(void);
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag);
+uint32_t HBN_Get_Wakeup_Addr(void);
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr);
+/*----------*/
+uint8_t HBN_Get_Core_Unhalt_Config(void);
+BL_Err_Type HBN_Set_Core_Reboot_Config(uint8_t core, uint8_t hcfg);
+uint8_t HBN_Get_User_Boot_Config(void);
+BL_Err_Type HBN_Set_User_Boot_Config(uint8_t ubCfg);
+BL_Err_Type HBN_Get_Ldo18io_Power_Delay_Config(uint16_t *pwrOffDly, uint16_t *pwrOnDly);
+BL_Err_Type HBN_Set_Ldo18io_Power_Delay_Config(uint16_t pwrOffDly, uint16_t pwrOnDly);
+/*----------*/
+BL_Err_Type HBN_Set_Xtal_Type(uint8_t xtalType);
+BL_Err_Type HBN_Get_Xtal_Type(uint8_t *xtalType);
+BL_Err_Type HBN_Get_Xtal_Value(uint32_t *xtalVal);
+BL_Err_Type HBN_Set_Flash_Power_Delay(uint8_t flashPwrDly);
+BL_Err_Type HBN_Get_Flash_Power_Delay(uint8_t *flashPwrDly);
+BL_Err_Type HBN_Set_Gpio_Keep(uint8_t gpioKeep);
+BL_Err_Type HBN_Get_Gpio_Keep(uint8_t *gpioKeep);
+BL_Err_Type HBN_Clear_Gpio_Keep(uint8_t gpioKeep);
+BL_Err_Type HBN_Set_PDS_Gpio_Keep(uint8_t gpioKeep);
+BL_Err_Type HBN_Get_PDS_Gpio_Keep(uint8_t *gpioKeep);
+BL_Err_Type HBN_Clear_PDS_Gpio_Keep(uint8_t gpioKeep);
+
+/*----------*/
+BL_Err_Type HBN_Clear_RTC_Counter(void);
+BL_Err_Type HBN_Enable_RTC_Counter(void);
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode);
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh);
+BL_Err_Type HBN_Recal_RC32K(int32_t expected_counter, int32_t actual_counter);
+BL_Err_Type HBN_Clear_RTC_IRQ(void);
+/*----------*/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType);
+BL_Err_Type HBN_GPIO_INT_Disable(void);
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType);
+uint8_t HBN_Get_Pin_Wakeup_Mode(void);
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType);
+BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable);
+BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal);
+BL_Err_Type HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2);
+BL_Err_Type HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg);
+BL_Err_Type HBN_Aon_Pad_Cfg_Set(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio);
+/*----------*/
+BL_Err_Type HBN_Enable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge);
+/*----------*/
+BL_Err_Type HBN_Enable_BOD_IRQ(void);
+BL_Err_Type HBN_Disable_BOD_IRQ(void);
+/*----------*/
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec);
+/*----------*/
+BL_Err_Type HBN_Power_On_Xtal_32K(void);
+BL_Err_Type HBN_Power_Off_Xtal_32K(void);
+BL_Err_Type HBN_Keep_On_RC32K(void);
+BL_Err_Type HBN_Power_Off_RC32K(void);
+BL_Err_Type HBN_Trim_Ldo33VoutTrim(void);
+BL_Err_Type HBN_Trim_RC32K(void);
+BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg);
+BL_Err_Type HBN_Clear_RTC_INT(void);
+/*----------*/
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_HBN_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_lz4d.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_l1c.h
old mode 100644
new mode 100755
similarity index 50%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_lz4d.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_l1c.h
index c3fc3ab415..028858c454
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_lz4d.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_l1c.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_lz4d.h
+  * @file    bl616_l1c.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,83 +33,86 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_LZ4D_H__
-#define __BL808_LZ4D_H__
+#ifndef __BL616_L1C_H__
+#define __BL616_L1C_H__
 
-#include "lz4_reg.h"
+// #include "pds_reg.h"
+#include "bl616_common.h"
 
-/** @addtogroup  BL808_Peripheral_Driver
+/** @addtogroup  BL616_Peripheral_Driver
  *  @{
  */
 
-/** @addtogroup  LZ4D
+/** @addtogroup  L1C
  *  @{
  */
 
-/** @defgroup  LZ4D_Public_Types
+/** @defgroup  L1C_Public_Types
  *  @{
  */
 
-typedef enum {
-    LZ4D_STATUS_INVALID = 0,
-    LZ4D_STATUS_DONE = (1 << 0),  /*!< 0->decompress done */
-    LZ4D_STATUS_ERROR = (1 << 1), /*!< 1->decompress error */
-    LZ4D_STATUS_MAX = 0x7FFFFFFF
-} LZ4D_STATUS_Type;
-
-typedef enum {
-    LZ4D_ADDR_END_SRC = 0,         /*!< 0->src address end: 26-bit */
-    LZ4D_ADDR_END_DST,             /*!< 1->dst address end: 26-bit */
-    LZ4D_ADDR_BASE_SRC,            /*!< 2->src address start: 32-bit */
-    LZ4D_ADDR_BASE_DST,            /*!< 3->dst address start: 32-bit */
-    LZ4D_ADDR_END_MAX = 0x03FFFFFF /* max: 64MB */
-} LZ4D_ADDR_REG_Type;
-
 /**
- *  @brief LZ4D interrupt type definition
+ *  @brief L1C configuration structure type definition
  */
-typedef enum {
-    LZ4D_INT_DONE,  /*!< LZ4 decompress job done */
-    LZ4D_INT_ERROR, /*!< LZ4 decompress processing error */
-    LZ4D_INT_ALL,   /*!< LZ4D all interrupts */
-    LZ4D_INT_MAX = 0x7FFFFFFF
-} LZ4D_INT_Type;
+typedef struct
+{
+    uint8_t cacheEn;
+    uint8_t wayDis;
+    uint8_t wa;
+    uint8_t wb;
+    uint8_t wt;
+    uint8_t rsvd[3];
+    uint32_t cacheRangeL;
+    uint32_t cacheRangeH;
+} L1C_CACHE_Cfg_Type;
 
-/*@} end of group LZ4D_Public_Types */
+/*@} end of group L1C_Public_Types */
 
-/** @defgroup  LZ4D_Public_Constants
+/** @defgroup  L1C_Public_Constants
  *  @{
  */
 
-/*@} end of group LZ4D_Public_Constants */
+/*@} end of group L1C_Public_Constants */
 
-/** @defgroup  LZ4D_Public_Macros
+/** @defgroup  L1C_Public_Macros
+ *  @{
+ */
+#define L1C_WAY_DISABLE_NONE       0x00
+#define L1C_WAY_DISABLE_ONE        0x01
+#define L1C_WAY_DISABLE_TWO        0x03
+#define L1C_WAY_DISABLE_ALL        0x03
+#define L1C_WAY_DISABLE_NOT_CAHNGE 0xFF
+
+/*@} end of group L1C_Public_Macros */
+
+/** @defgroup  L1C_Public_Functions
  *  @{
  */
 
-#define LZ4DECOMPRESSOR ((lz4_reg_t *)(LZ4D_BASE))
+/*----------*/
+BL_Err_Type L1C_ICache_Enable(uint8_t wayDsiable);
+BL_Err_Type L1C_DCache_Enable(uint8_t wayDsiable);
+BL_Err_Type L1C_ICache_Disable(void);
+BL_Err_Type L1C_DCache_Disable(void);
+void L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn);
+BL_Err_Type L1C_DCache_Clean_All(void);
+BL_Err_Type L1C_DCache_Clean_Invalid_All(void);
+BL_Err_Type L1C_ICache_Invalid_All(void);
+BL_Err_Type L1C_DCache_Invalid_All(void);
+BL_Err_Type L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len);
+BL_Err_Type L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len);
+BL_Err_Type L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len);
+BL_Err_Type L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len);
+/*----------*/
+BL_Err_Type L1C_Set_Wrap(uint8_t en);
+BL_Err_Type L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting);
+/*----------*/
+int L1C_Is_DCache_Range(uintptr_t addr);
+int L1C_Get_None_Cache_Addr(uintptr_t addr);
+/*@} end of group L1C_Public_Functions */
 
-/*@} end of group LZ4D_Public_Macros */
+/*@} end of group L1C */
 
-/** @defgroup  LZ4D_Public_Functions
- *  @{
- */
-void LZ4D_Stop(void);
-void LZ4D_Start(void);
-uint32_t LZ4D_GetAddrReg(LZ4D_ADDR_REG_Type addr);
-uint32_t LZ4D_GetDecompressLen(void);
-uint32_t LZ4D_GetStatus(LZ4D_STATUS_Type sts);
-void LZ4D_Decompress(const void *in, void *out);
-void LZ4D_IntMask(LZ4D_INT_Type intType, BL_Mask_Type intMask);
-#ifndef BFLB_USE_HAL_DRIVER
-void LZ4D_Int_Callback_Install(LZ4D_INT_Type intType, intCallback_Type *cbFun);
-#endif
-void LZ4D_Init(void);
+/*@} end of group BL616_Peripheral_Driver */
 
-/*@} end of group LZ4D_Public_Functions */
-
-/*@} end of group LZ4D */
-
-/*@} end of group BL808_Peripheral_Driver */
-
-#endif /* __BL808_LZ4D_H__ */
+#endif /* __BL616_L1C_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_efuse.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_efuse.h
new file mode 100755
index 0000000000..a486c9d8ba
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_efuse.h
@@ -0,0 +1,31 @@
+#ifndef __BL616_MFG_EFUSE_H__
+#define __BL616_MFG_EFUSE_H__
+
+#include "stdint.h"
+
+uint8_t mfg_efuse_get_rf_cal_slots(void);
+void mfg_efuse_set_rf_cal_slots(uint8_t slots);
+uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload);
+int mfg_efuse_write_xtal_capcode_pre(uint8_t capcode, uint8_t program);
+void mfg_efuse_write_xtal_capcode(void);
+int mfg_efuse_read_xtal_capcode(uint8_t *capcode, uint8_t reload);
+uint8_t mfg_efuse_is_hp_poweroffset_slot_empty(uint8_t reload);
+int mfg_efuse_write_hp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program);
+void mfg_efuse_write_hp_poweroffset(void);
+int mfg_efuse_read_hp_poweroffset(int8_t pwr_offset[14], uint8_t reload);
+uint8_t mfg_efuse_is_lp_poweroffset_slot_empty(uint8_t reload);
+int mfg_efuse_write_lp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program);
+void mfg_efuse_write_lp_poweroffset(void);
+int mfg_efuse_read_lp_poweroffset(int8_t pwr_offset[14], uint8_t reload);
+uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload);
+int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6], uint8_t program);
+void mfg_efuse_write_macaddr(void);
+int8_t mfg_efuse_read_macaddr(uint8_t mac[6], uint8_t reload);
+uint8_t mfg_efuse_is_bz_poweroffset_slot_empty(uint8_t reload);
+int mfg_efuse_write_bz_poweroffset_pre(int8_t pwr_offset[5], uint8_t program);
+void mfg_efuse_write_bz_poweroffset(void);
+int mfg_efuse_read_bz_poweroffset(int8_t pwr_offset[20], uint8_t reload);
+void mfg_efuse_program(uint32_t addr,uint32_t *pword,uint32_t countInword,uint32_t program);
+void mfg_efuse_read(uint32_t addr,uint32_t *pword,uint32_t countInword,uint8_t reload);
+
+#endif /*__BL616_MFG_EFUSE_H__*/
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_flash.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_flash.h
new file mode 100755
index 0000000000..4480272b21
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_flash.h
@@ -0,0 +1,36 @@
+#ifndef __BL616_MFG_FLASH_H__
+#define __BL616_MFG_FLASH_H__
+
+#include "stdint.h"
+#include "bflb_xip_sflash.h"
+
+typedef struct rf_para_flash_tag {
+    uint32_t magic;        //"RFPA"
+    uint8_t capcode_valid; //0x5A
+    uint8_t capcode;
+    uint8_t poweroffset_valid; //0x5A
+    int8_t poweroffset[3];
+    uint8_t mac_valid; //0x5A
+    uint8_t mac[6];
+    uint8_t rsvd[3];
+    uint32_t crc32;
+} rf_para_flash_t;
+
+int mfg_flash_init(spi_flash_cfg_type *flashCfg);
+int mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program);
+void mfg_flash_write_xtal_capcode(void);
+int mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload);
+int mfg_flash_write_hp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program);
+void mfg_flash_write_hp_poweroffset(void);
+int mfg_flash_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
+int mfg_flash_write_lp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program);
+void mfg_flash_write_lp_poweroffset(void);
+int mfg_flash_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
+int mfg_flash_write_macaddr_pre(uint8_t mac[6], uint8_t program);
+void mfg_flash_write_macaddr(void);
+int mfg_flash_read_macaddr(uint8_t mac[6], uint8_t reload);
+int mfg_flash_write_bz_poweroffset_pre(int8_t pwrOffset[5], uint8_t program);
+void mfg_flash_write_bz_poweroffset(void);
+int mfg_flash_read_bz_poweroffset(int8_t pwrOffset[20], uint8_t reload);
+
+#endif /*__BL616_MFG_FLASH_H__*/
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_media.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_media.h
new file mode 100755
index 0000000000..c325f802fc
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_mfg_media.h
@@ -0,0 +1,52 @@
+#ifndef __BL616_MFG_MEDIA_H__
+#define __BL616_MFG_MEDIA_H__
+
+#include "stdint.h"
+#include "bl616_mfg_efuse.h"
+#include "bl616_mfg_flash.h"
+
+int mfg_media_init_need_lock(spi_flash_cfg_type *flashCfg);
+int mfg_media_init_with_lock(spi_flash_cfg_type *flashCfg);
+uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload);
+int mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program);
+int mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program);
+void mfg_media_write_xtal_capcode_need_lock(void);
+void mfg_media_write_xtal_capcode_with_lock(void);
+int mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode, uint8_t reload);
+int mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode, uint8_t reload);
+int mfg_media_read_xtal_capcode(uint8_t *capcode, uint8_t reload);
+uint8_t mfg_media_is_hp_poweroffset_slot_empty(uint8_t reload);
+int mfg_media_write_hp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program);
+int mfg_media_write_hp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program);
+void mfg_media_write_hp_poweroffset_need_lock(void);
+void mfg_media_write_hp_poweroffset_with_lock(void);
+int mfg_media_read_hp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload);
+int mfg_media_read_hp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload);
+int mfg_media_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
+uint8_t mfg_media_is_lp_poweroffset_slot_empty(uint8_t reload);
+int mfg_media_write_lp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program);
+int mfg_media_write_lp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program);
+void mfg_media_write_lp_poweroffset_need_lock(void);
+void mfg_media_write_lp_poweroffset_with_lock(void);
+int mfg_media_read_lp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload);
+int mfg_media_read_lp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload);
+int mfg_media_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload);
+uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload);
+int mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6], uint8_t program);
+int mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6], uint8_t program);
+void mfg_media_write_macaddr_need_lock(void);
+void mfg_media_write_macaddr_with_lock(void);
+int mfg_media_read_macaddr_need_lock(uint8_t mac[6], uint8_t reload);
+int mfg_media_read_macaddr_with_lock(uint8_t mac[6], uint8_t reload);
+int mfg_media_read_macaddr(uint8_t mac[6], uint8_t reload);
+uint8_t mfg_media_is_bz_poweroffset_slot_empty(uint8_t reload);
+int mfg_media_write_bz_poweroffset_pre_need_lock(int8_t pwrOffset[5], uint8_t program);
+int mfg_media_write_bz_poweroffset_pre_with_lock(int8_t pwrOffset[5], uint8_t program);
+void mfg_media_write_bz_poweroffset_need_lock(void);
+void mfg_media_write_bz_poweroffset_with_lock(void);
+int mfg_media_read_bz_poweroffset_need_lock(int8_t pwrOffset[5], uint8_t reload);
+int mfg_media_read_bz_poweroffset_with_lock(int8_t pwrOffset[5], uint8_t reload);
+int mfg_media_read_bz_poweroffset(int8_t pwrOffset[5], uint8_t reload);
+
+
+#endif /*__BL616_MFG_MEDIA_H__*/
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pds.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pds.h
new file mode 100755
index 0000000000..07ca104e25
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pds.h
@@ -0,0 +1,585 @@
+/**
+  ******************************************************************************
+  * @file    bl616_pds.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_PDS_H__
+#define __BL616_PDS_H__
+
+#include "pds_reg.h"
+#include "glb_reg.h"
+#include "bl616_clock.h"
+#include "bl616_aon.h"
+#include "bl616_hbn.h"
+#include "bl616_common.h"
+#include "bl616_acomp.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_ctrl.h"
+
+#define PDS_WAKEUP_BY_PDS_TIMER_EN           PDS_WAKEUP_BY_PDS_TIMER_EN
+#define PDS_WAKEUP_BY_PDS_TIMER_EN_POS       (10U)
+#define PDS_WAKEUP_BY_PDS_TIMER_EN_LEN       (1U)
+#define PDS_WAKEUP_BY_PDS_TIMER_EN_MSK       (((1U << PDS_WAKEUP_BY_PDS_TIMER_EN_LEN) - 1) << PDS_WAKEUP_BY_PDS_TIMER_EN_POS)
+#define PDS_WAKEUP_BY_PDS_TIMER_EN_UMSK      (~(((1U << PDS_WAKEUP_BY_PDS_TIMER_EN_LEN) - 1) << PDS_WAKEUP_BY_PDS_TIMER_EN_POS))
+#define PDS_WAKEUP_BY_HBN_IRQ_OUT_EN         PDS_WAKEUP_BY_HBN_IRQ_OUT_EN
+#define PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_POS     (11U)
+#define PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_LEN     (1U)
+#define PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_MSK     (((1U << PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_LEN) - 1) << PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_POS)
+#define PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_UMSK    (~(((1U << PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_LEN) - 1) << PDS_WAKEUP_BY_HBN_IRQ_OUT_EN_POS))
+#define PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN        PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN
+#define PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_POS    (12U)
+#define PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_LEN    (1U)
+#define PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_MSK    (((1U << PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_LEN) - 1) << PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_POS)
+#define PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_UMSK   (~(((1U << PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_LEN) - 1) << PDS_WAKEUP_BY_GLB_GPIO_IRQ_EN_POS))
+#define PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN        PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN
+#define PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_POS    (13U)
+#define PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_LEN    (1U)
+#define PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_MSK    (((1U << PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_LEN) - 1) << PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_POS)
+#define PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_UMSK   (~(((1U << PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_LEN) - 1) << PDS_WAKEUP_BY_PDS_GPIO_IRQ_EN_POS))
+#define PDS_WAKEUP_BY_IRRX_EN                PDS_WAKEUP_BY_IRRX_EN
+#define PDS_WAKEUP_BY_IRRX_EN_POS            (14U)
+#define PDS_WAKEUP_BY_IRRX_EN_LEN            (1U)
+#define PDS_WAKEUP_BY_IRRX_EN_MSK            (((1U << PDS_WAKEUP_BY_IRRX_EN_LEN) - 1) << PDS_WAKEUP_BY_IRRX_EN_POS)
+#define PDS_WAKEUP_BY_IRRX_EN_UMSK           (~(((1U << PDS_WAKEUP_BY_IRRX_EN_LEN) - 1) << PDS_WAKEUP_BY_IRRX_EN_POS))
+#define PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN      PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN
+#define PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_POS  (15U)
+#define PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_LEN  (1U)
+#define PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_MSK  (((1U << PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_LEN) - 1) << PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_POS)
+#define PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_UMSK (~(((1U << PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_LEN) - 1) << PDS_WAKEUP_BY_WIFI_WKP_EVENT_EN_POS))
+#define PDS_WAKEUP_BY_DM_SLP_IRQ_EN          PDS_WAKEUP_BY_DM_SLP_IRQ_EN
+#define PDS_WAKEUP_BY_DM_SLP_IRQ_EN_POS      (16U)
+#define PDS_WAKEUP_BY_DM_SLP_IRQ_EN_LEN      (1U)
+#define PDS_WAKEUP_BY_DM_SLP_IRQ_EN_MSK      (((1U << PDS_WAKEUP_BY_DM_SLP_IRQ_EN_LEN) - 1) << PDS_WAKEUP_BY_DM_SLP_IRQ_EN_POS)
+#define PDS_WAKEUP_BY_DM_SLP_IRQ_EN_UMSK     (~(((1U << PDS_WAKEUP_BY_PDS_TIMER_EN_LEN) - 1) << PDS_WAKEUP_BY_DM_SLP_IRQ_EN_POS))
+#define PDS_WAKEUP_BY_USBH_WKP_DET_EN        PDS_WAKEUP_BY_USBH_WKP_DET_EN
+#define PDS_WAKEUP_BY_USBH_WKP_DET_EN_POS    (17U)
+#define PDS_WAKEUP_BY_USBH_WKP_DET_EN_LEN    (1U)
+#define PDS_WAKEUP_BY_USBH_WKP_DET_EN_MSK    (((1U << PDS_WAKEUP_BY_USBH_WKP_DET_EN_LEN) - 1) << PDS_WAKEUP_BY_USBH_WKP_DET_EN_POS)
+#define PDS_WAKEUP_BY_USBH_WKP_DET_EN_UMSK   (~(((1U << PDS_WAKEUP_BY_USBH_WKP_DET_EN_LEN) - 1) << PDS_WAKEUP_BY_USBH_WKP_DET_EN_POS))
+#define PDS_WAKEUP_BY_USBH_CONN_DET_EN       PDS_WAKEUP_BY_USBH_CONN_DET_EN
+#define PDS_WAKEUP_BY_USBH_CONN_DET_EN_POS   (18U)
+#define PDS_WAKEUP_BY_USBH_CONN_DET_EN_LEN   (1U)
+#define PDS_WAKEUP_BY_USBH_CONN_DET_EN_MSK   (((1U << PDS_WAKEUP_BY_USBH_CONN_DET_EN_LEN) - 1) << PDS_WAKEUP_BY_USBH_CONN_DET_EN_POS)
+#define PDS_WAKEUP_BY_USBH_CONN_DET_EN_UMSK  (~(((1U << PDS_WAKEUP_BY_USBH_CONN_DET_EN_LEN) - 1) << PDS_WAKEUP_BY_USBH_CONN_DET_EN_POS))
+#define PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN       PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN
+#define PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_POS   (19U)
+#define PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_LEN   (1U)
+#define PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_MSK   (((1U << PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_LEN) - 1) << PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_POS)
+#define PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_UMSK  (~(((1U << PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_LEN) - 1) << PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_POS))
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief PDS GPIO int set type
+ */
+typedef enum {
+    PDS_GPIO_INT_SET_1_GPIO0_GPIO7,   /*!< gpio int set 1, gpio0 - gpio7          */
+    PDS_GPIO_INT_SET_2_GPIO8_GPIO15,  /*!< gpio int set 2, gpio8 - gpio15         */
+    PDS_GPIO_INT_SET_3_GPIO20_GPIO27, /*!< gpio int set 3, gpio20 - gpio27        */
+    PDS_GPIO_INT_SET_4_GPIO28_GPIO34, /*!< gpio int set 4, gpio28 - gpio34        */
+} PDS_GPIO_INT_SET_Type;
+
+/**
+ *  @brief PDS GPIO group set type
+ */
+typedef enum {
+    PDS_GPIO_GROUP_SET_GPIO0_GPIO15,  /*!< gpio int set 0, gpio0 - gpio15          */
+    PDS_GPIO_GROUP_SET_GPIO20_GPIO36, /*!< gpio int set 1, gpio20 - gpio36         */
+} PDS_GPIO_GROUP_SET_Type;
+
+/**
+ *  @brief PDS GPIO interrupt control mode type definition
+ */
+typedef enum {
+    PDS_GPIO_INT_SYNC_FALLING_EDGE = 0,        /*!< GPIO interrupt sync mode, GPIO negedge pulse trigger interrupt */
+    PDS_GPIO_INT_SYNC_RISING_EDGE = 1,         /*!< GPIO interrupt sync mode, GPIO posedge pulse trigger interrupt */
+    PDS_GPIO_INT_SYNC_LOW_LEVEL = 2,           /*!< GPIO interrupt sync mode, GPIO negedge level trigger interrupt */
+    PDS_GPIO_INT_SYNC_HIGH_LEVEL = 3,          /*!< GPIO interrupt sync mode, GPIO posedge level trigger interrupt */
+    PDS_GPIO_INT_SYNC_RISING_FALLING_EDGE = 4, /*!< GPIO interrupt sync mode, GPIO posedge negedge pulse trigger interrupt */
+    PDS_GPIO_INT_ASYNC_FALLING_EDGE = 8,       /*!< GPIO interrupt async mode, GPIO negedge pulse trigger interrupt */
+    PDS_GPIO_INT_ASYNC_RISING_EDGE = 9,        /*!< GPIO interrupt async mode, GPIO posedge pulse trigger interrupt */
+    PDS_GPIO_INT_ASYNC_LOW_LEVEL = 10,         /*!< GPIO interrupt async mode, GPIO negedge level trigger interrupt */
+    PDS_GPIO_INT_ASYNC_HIGH_LEVEL = 11,        /*!< GPIO interrupt async mode, GPIO posedge level trigger interrupt */
+} PDS_GPIO_INT_TRIG_Type;
+
+/**
+ *  @brief PDS LDO level type definition
+ */
+typedef enum {
+    PDS_LDO_LEVEL_0P70V = 2,  /*!< PDS LDO voltage 0.70V */
+    PDS_LDO_LEVEL_0P75V = 3,  /*!< PDS LDO voltage 0.75V */
+    PDS_LDO_LEVEL_0P80V = 4,  /*!< PDS LDO voltage 0.80V */
+    PDS_LDO_LEVEL_0P85V = 5,  /*!< PDS LDO voltage 0.85V */
+    PDS_LDO_LEVEL_0P90V = 6,  /*!< PDS LDO voltage 0.90V */
+    PDS_LDO_LEVEL_0P95V = 7,  /*!< PDS LDO voltage 0.95V */
+    PDS_LDO_LEVEL_1P00V = 8,  /*!< PDS LDO voltage 1.00V */
+    PDS_LDO_LEVEL_1P05V = 9,  /*!< PDS LDO voltage 1.05V */
+    PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */
+    PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */
+    PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */
+    PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */
+    PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */
+    PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */
+} PDS_LDO_LEVEL_Type;
+
+/**
+ *  @brief PDS configuration type definition
+ */
+typedef struct
+{
+    uint32_t pdsStart        : 1; /*!< [0]PDS Start */
+    uint32_t sleepForever    : 1; /*!< [1]PDS sleep forever */
+    uint32_t xtalForceOff    : 1; /*!< [2]Power off xtal force */
+    uint32_t saveWiFiState   : 1; /*!< [3]Save WIFI State Before Enter PDS */
+    uint32_t ldo11Off        : 1; /*!< [4]power down ldo11 during PDS */
+    uint32_t bgSysOff        : 1; /*!< [5]power down bg_sys during PDS */
+    uint32_t ctrlGpioIePuPd  : 1; /*!< [6]PDS control the GPIO IE/PU/PD at Sleep Mode */
+    uint32_t dcdc18Off       : 1; /*!< [7]power down dcdc18 during PDS */
+    uint32_t clkOff          : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
+    uint32_t memStby         : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
+    uint32_t glbRstProtect   : 1; /*!< [10]avoid glb_reg reset by any reset */
+    uint32_t isolation       : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
+    uint32_t waitXtalRdy     : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
+    uint32_t pdsPwrOff       : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
+    uint32_t xtalOff         : 1; /*!< [14]xtal power down during PDS */
+    uint32_t socEnbForceOn   : 1; /*!< [15]pds_soc_enb always active */
+    uint32_t pdsRstSocEn     : 1; /*!< [16]pds_rst controlled by PDS */
+    uint32_t pdsRC32mOn      : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
+    uint32_t pdsDcdc11VselEn : 1; /*!< [18]PDS "SLEEP" control DCDC11 voltage enable */
+    uint32_t usbpllOff       : 1; /*!< [19]PDS Control USB PLL off When pds_pwr_off */
+    uint32_t aupllOff        : 1; /*!< [20]PDS control aupll power off */
+    uint32_t rsvd_21         : 1; /*!< [21]reserved */
+    uint32_t wifipllOff      : 1; /*!< [22]PDS control wifipll power off */
+    uint32_t pdsDcdc11Vsel   : 5; /*!< [27:23]DCDC11 voltage selection in PDS mode */
+    uint32_t pdsCtlRfSel     : 2; /*!< [29:28]select the way RF controlled by PDS */
+    uint32_t pdsUseTbttSlp   : 1; /*!< [30]PDS Auto Sleep When wifi_tbtt_sleep_irq detect to 1 */
+    uint32_t pdsGpioIsoMod   : 1; /*!< [31]HW Keep GPIO at PDS Mode */
+} PDS_CTL_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t cpuPwrOff   : 1; /*!< [0] */
+    uint32_t cpuRst      : 1; /*!< [1] */
+    uint32_t cpuMemStby  : 1; /*!< [2] */
+    uint32_t cpuGateClk  : 1; /*!< [3] */
+    uint32_t rsv4_11     : 8; /*!< [11:4]reserve */
+    uint32_t wbPwrOff    : 1; /*!< [12] */
+    uint32_t wbRst       : 1; /*!< [13] */
+    uint32_t wbMemStby   : 1; /*!< [14] */
+    uint32_t wbGateClk   : 1; /*!< [15] */
+    uint32_t rsv16_19    : 4; /*!< [19:16]reserve */
+    uint32_t usbPwrOff   : 1; /*!< [20] */
+    uint32_t usbRst      : 1; /*!< [21] */
+    uint32_t usbMemStby  : 1; /*!< [22] */
+    uint32_t usbGateClk  : 1; /*!< [23] */
+    uint32_t miscPwrOff  : 1; /*!< [24] */
+    uint32_t miscRst     : 1; /*!< [25] */
+    uint32_t miscMemStby : 1; /*!< [26] */
+    uint32_t miscGateClk : 1; /*!< [27] */
+    uint32_t rsv28_31    : 4; /*!< [31:28]reserve */
+} PDS_CTL4_Type;
+
+/**
+ *  @brief PDS interrupt type definition
+ */
+typedef enum {
+    PDS_INT_WAKEUP = 0,           /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */
+    PDS_INT_RF_DONE = 1,          /*!< PDS RF done interrupt */
+    PDS_INT_WIFI_TBTT_SLEEP = 2,  /*!< PDS wifi tbtt sleep interrupt */
+    PDS_INT_WIFI_TBTT_WAKEUP = 3, /*!< PDS wifi tbtt wakeup interrupt */
+    PDS_INT_MAX = 4,              /*!< PDS int max number */
+} PDS_INT_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t forceCpuPwrOff  : 1;  /*!< [0]manual force NP power off */
+    uint32_t rsv1            : 1;  /*!< [1]reserved */
+    uint32_t forceWbPwrOff   : 1;  /*!< [2]manual force WB power off */
+    uint32_t forceUsbPwrOff  : 1;  /*!< [3]manual force USB power off */
+    uint32_t forceCpuIso     : 1;  /*!< [4]manual force NP isolation */
+    uint32_t rsv5            : 1;  /*!< [5]reserved */
+    uint32_t forceWbIso      : 1;  /*!< [6]manual force WB isolation */
+    uint32_t forceUsbIso     : 1;  /*!< [7]manual force USB isolation */
+    uint32_t forceCpuPdsRst  : 1;  /*!< [8]manual force NP pds reset */
+    uint32_t rsv9            : 1;  /*!< [9]reserved */
+    uint32_t forceWbPdsRst   : 1;  /*!< [10]manual force WB pds reset */
+    uint32_t forceUsbPdsRst  : 1;  /*!< [11]manual force USB pds reset */
+    uint32_t forceCpuMemStby : 1;  /*!< [12]manual force NP memory sleep */
+    uint32_t rsv13           : 1;  /*!< [13]reserved */
+    uint32_t forceWbMemStby  : 1;  /*!< [14]manual force WB memory sleep */
+    uint32_t forceUsbMemStby : 1;  /*!< [15]manual force USB memory sleep */
+    uint32_t forceCpuGateClk : 1;  /*!< [16]manual force NP clock gated */
+    uint32_t rsv17           : 1;  /*!< [17]reserved */
+    uint32_t forceWbGateClk  : 1;  /*!< [18]manual force WB clock gated */
+    uint32_t forceUsbGateClk : 1;  /*!< [19]manual force USB clock gated */
+    uint32_t rsv20_31        : 12; /*!< [31:20]reserve */
+} PDS_CTL2_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t rsv0             : 1;  /*!< [0]reserve */
+    uint32_t forceMiscPwrOff  : 1;  /*!< [1]manual force MISC pwr_off */
+    uint32_t rsv2_3           : 2;  /*!< [3:2]reserve */
+    uint32_t forceMiscIsoEn   : 1;  /*!< [4]manual force MISC iso_en */
+    uint32_t rsv5_6           : 2;  /*!< [6:5]reserve */
+    uint32_t forceMiscPdsRst  : 1;  /*!< [7]manual force MISC pds_rst */
+    uint32_t rsv8_9           : 2;  /*!< [9:8]reserve */
+    uint32_t forceMiscMemStby : 1;  /*!< [10]manual force MISC mem_stby */
+    uint32_t rsv11_12         : 2;  /*!< [12:11]reserve */
+    uint32_t forceMiscGateClk : 1;  /*!< [13]manual force MISC gate_clk */
+    uint32_t rsv14_23         : 10; /*!< [23:14]reserve */
+    uint32_t cpuIsoEn         : 1;  /*!< [24]make CPU isolated at PDS Sleep state */
+    uint32_t rsv25_26         : 2;  /*!< [26:25]reserve */
+    uint32_t wbIsoEn          : 1;  /*!< [27]make WB isolated at PDS Sleep state */
+    uint32_t rsv28            : 1;  /*!< [28]reserve */
+    uint32_t usbIsoEn         : 1;  /*!< [29]make USB isolated at PDS Sleep state */
+    uint32_t miscIsoEn        : 1;  /*!< [30]make misc isolated at PDS Sleep state */
+    uint32_t rsv31            : 1;  /*!< [31]reserve */
+} PDS_CTL3_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t cpuWfiMask  : 1;  /*!< [0]pds start condition mask np_wfi */
+    uint32_t pdsPadOdEn  : 1;  /*!< [1]GPIO21/22/28/29 5V Tolerant PAD Open Drain Enable */
+    uint32_t rsv2_7      : 6;  /*!< [7:2]reserve */
+    uint32_t ctrlUsb33   : 1;  /*!< [8]HW control turn on/off USB 3.3V @USB1.1V Power On/OFF */
+    uint32_t ldo18ioOff  : 1;  /*!< [9]power down ldo18io during PDS */
+    uint32_t rsv10_15    : 6;  /*!< [15:10]reserve */
+    uint32_t pdsGpioKeep : 3;  /*!< [18:16]enable or disable keep function */
+    uint32_t rsv19_31    : 13; /*!< [31:19]reserve */
+} PDS_CTL5_Type;
+
+/**
+ *  @brief PDS default level configuration type definition
+ */
+typedef struct
+{
+    PDS_CTL_Type pdsCtl;   /*!< PDS_CTL configuration */
+    PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */
+    PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */
+    PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */
+    PDS_CTL5_Type pdsCtl5; /*!< PDS_CTL5 configuration */
+} PDS_DEFAULT_LV_CFG_Type;
+
+/**
+ *  @brief PDS control RAM1 type definition
+ */
+typedef struct
+{
+    uint32_t rsv0_7     : 8; /*!< [7:0] reserve */
+    uint32_t ramClkCnt  : 6; /*!< [13:8] HW Option : Assert Extra Clock Counter in  MEM_STBY */
+    uint32_t rsv14_15   : 2; /*!< [15:14] reserved */
+    uint32_t ramClkCnt2 : 6; /*!< [21:16] HW Option : Assert Extra Clock Counter in MEM_IDLE/LV_MEM_IDLE */
+    uint32_t rsv22_23   : 2; /*!< [23:22] reserved */
+    uint32_t cpuRamClk  : 1; /*!< [24] PDS Control PD_CORE_CPU SRAM Clock */
+    uint32_t rsv25      : 1; /*!< [25] reserved */
+    uint32_t wbRamClk   : 1; /*!< [26] PDS Control PD_WB SRAM Clock */
+    uint32_t usbRamClk  : 1; /*!< [27] PDS Control PD_usb SRAM Clock */
+    uint32_t miscRamClk : 1; /*!< [28] PDS Control PD_CORE_MISC SRAM Clock */
+    uint32_t rsv29      : 1; /*!< [29] reserved */
+    uint32_t ctlRamClk2 : 1; /*!< [30] To assert extra clock during PDS on sequence */
+    uint32_t ctlRamClk  : 1; /*!< [31] Enable PDS Control PD_CORE SRAM Clock */
+} PDS_CTRL_RAM1_Type;
+
+/**
+ *  @brief PDS control RAM2 type definition
+ */
+typedef struct
+{
+    uint32_t wramSlp  : 10; /*!< [9:0] cr_wram_slp */
+    uint32_t wramRet  : 10; /*!< [19:10] cr_wram_ret */
+    uint32_t rsv20_31 : 12; /*!< [31:20] reserved */
+} PDS_CTRL_RAM2_Type;
+
+/**
+ *  @brief PDS control RAM3 type definition
+ */
+typedef struct
+{
+    uint32_t cr_ocram_ret   : 20; /* [19: 0],        r/w,        0x0 */
+    uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+} PDS_CTRL_RAM3_Type;
+
+/**
+ *  @brief PDS control RAM4 type definition
+ */
+typedef struct
+{
+    uint32_t cr_ocram_slp   : 20; /* [19: 0],        r/w,        0x0 */
+    uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+} PDS_CTRL_RAM4_Type;
+
+typedef struct
+{
+    PDS_CTRL_RAM1_Type *pds_ram1; /*!< PDS_RAM1 configuration */
+    PDS_CTRL_RAM2_Type *pds_ram2; /*!< PDS_RAM2 configuration */
+    PDS_CTRL_RAM3_Type *pds_ram3; /*!< PDS_RAM3 configuration */
+    PDS_CTRL_RAM4_Type *pds_ram4; /*!< PDS_RAM4 configuration */
+} PDS_RAM_CFG_Type;
+
+/**
+ *  @brief PDS OCRAM configuration type definition
+ */
+typedef struct
+{
+    uint32_t PDS_OCRAM_CFG_0KB_16KB_CPU_RAM_SLP  : 1;  /*!< [0]   0~16KB cpu_ram sleep */
+    uint32_t PDS_OCRAM_CFG_16KB_32KB_CPU_RAM_SLP : 1;  /*!< [1]   16~32KB cpu_ram sleep */
+    uint32_t PDS_OCRAM_CFG_32KB_48KB_CPU_RAM_SLP : 1;  /*!< [2]   32~48KB cpu_ram sleep */
+    uint32_t PDS_OCRAM_CFG_48KB_64KB_CPU_RAM_SLP : 1;  /*!< [3]   48~64KB cpu_ram sleep */
+    uint32_t PDS_OCRAM_CFG_0KB_16KB_CPU_RAM_RET  : 1;  /*!< [4]   0~16KB cpu_ram retension */
+    uint32_t PDS_OCRAM_CFG_16KB_32KB_CPU_RAM_RET : 1;  /*!< [5]   16~32KB cpu_ram retension */
+    uint32_t PDS_OCRAM_CFG_32KB_48KB_CPU_RAM_RET : 1;  /*!< [6]   32~48KB cpu_ram retension */
+    uint32_t PDS_OCRAM_CFG_48KB_64KB_CPU_RAM_RET : 1;  /*!< [7]   48~64KB cpu_ram retension */
+    uint32_t PDS_OCRAM_CFG_RSV                   : 24; /*!< [31:8]reserve */
+} PDS_OCRAM_CFG_Type;
+
+/**
+ *  @brief PDS WRAM configuration type definition
+ */
+typedef struct
+{
+    uint32_t PDS_WRAM_CFG_0KB_16KB_CPU_RAM_SLP    : 1;  /*!< [0]   0~16KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_16KB_32KB_CPU_RAM_SLP   : 1;  /*!< [1]   16~32KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_32KB_48KB_CPU_RAM_SLP   : 1;  /*!< [2]   32~48KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_48KB_64KB_CPU_RAM_SLP   : 1;  /*!< [3]   48~64KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_64KB_80KB_CPU_RAM_SLP   : 1;  /*!< [4]   64~80KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_80KB_96KB_CPU_RAM_SLP   : 1;  /*!< [5]   80~96KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_96KB_112KB_CPU_RAM_SLP  : 1;  /*!< [6]   96~112KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_112KB_128KB_CPU_RAM_SLP : 1;  /*!< [7]   112~128KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_128KB_144KB_CPU_RAM_SLP : 1;  /*!< [8]   128~144KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_144KB_160KB_CPU_RAM_SLP : 1;  /*!< [9]   144~160KB cpu_ram sleep */
+    uint32_t PDS_WRAM_CFG_0KB_16KB_CPU_RAM_RET    : 1;  /*!< [10]   0~16KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_16KB_32KB_CPU_RAM_RET   : 1;  /*!< [11]   16~32KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_32KB_48KB_CPU_RAM_RET   : 1;  /*!< [12]   32~48KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_48KB_64KB_CPU_RAM_RET   : 1;  /*!< [13]   48~64KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_64KB_80KB_CPU_RAM_RET   : 1;  /*!< [14]   64~80KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_80KB_96KB_CPU_RAM_RET   : 1;  /*!< [15]   80~96KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_96KB_112KB_CPU_RAM_RET  : 1;  /*!< [16]   96~112KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_112KB_128KB_CPU_RAM_RET : 1;  /*!< [17]   112~128KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_128KB_144KB_CPU_RAM_RET : 1;  /*!< [18]   128~144KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_144KB_160KB_CPU_RAM_RET : 1;  /*!< [19]   144~160KB cpu_ram retension */
+    uint32_t PDS_WRAM_CFG_RSV                     : 22; /*!< [31:20]reserve */
+} PDS_WRAM_CFG_Type;
+
+/**
+ *  @brief PDS level 0/1/2/3 mode HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE = 0,   /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE = 1,    /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL = 2,      /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL = 3,     /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync high level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_FALLING = 7, /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: sync rising+falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE = 8,  /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE = 9,   /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL = 10,    /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL = 11,   /*!< PDS level 0/1/2/3 mode HBN GPIO INT trigger type: async high level trigger */
+} PDS_AON_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief PDS APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t pdsLevel;                                 /*!< PDS level */
+    uint8_t turnOffRF;                                /*!< Wheather turn off RF */
+    uint8_t useXtal32k;                               /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint8_t pdsAonGpioWakeupSrc;                      /*!< PDS level 0/1/2/3 mode always on GPIO Wakeup source(HBN wakeup pin) */
+    PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0/1/2/3 mode always on GPIO Triger type(HBN wakeup pin) */
+    uint8_t powerDownFlash;                           /*!< Whether power down flash */
+    uint8_t turnOffFlashPad;                          /*!< Whether turn off embedded flash pad */
+    uint8_t ocramRetetion;                            /*!< Whether OCRAM Retention */
+    uint8_t turnoffPLL;                               /*!< Whether trun off PLL */
+    uint8_t xtalType;                                 /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
+    uint8_t flashContRead;                            /*!< Whether enable flash continue read */
+    uint32_t sleepTime;                               /*!< PDS sleep time */
+    spi_flash_cfg_type *flashCfg;                     /*!< Flash config pointer, used when power down flash */
+    PDS_LDO_LEVEL_Type ldoLevel;                      /*!< LDO level */
+    void (*preCbFun)(void);                           /*!< Pre callback function */
+    void (*postCbFun)(void);                          /*!< Post callback function */
+} PDS_APP_CFG_Type;
+
+/*@} end of group PDS_Public_Types */
+
+/** @defgroup  PDS_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  PDS_GPIO_INT_SET_TYPE
+ *  @{
+ */
+#define IS_PDS_GPIO_INT_SET_TYPE(type) (((type) == PDS_GPIO_INT_SET_1_GPIO0_GPIO7) ||   \
+                                        ((type) == PDS_GPIO_INT_SET_2_GPIO8_GPIO15) ||  \
+                                        ((type) == PDS_GPIO_INT_SET_3_GPIO20_GPIO27) || \
+                                        ((type) == PDS_GPIO_INT_SET_4_GPIO28_GPIO34))
+
+/** @defgroup  PDS_GPIO_GROUP_SET_TYPE
+ *  @{
+ */
+#define IS_PDS_GPIO_GROUP_SET_TYPE(type) (((type) == PDS_GPIO_GROUP_SET_GPIO0_GPIO15) || \
+                                          ((type) == PDS_GPIO_GROUP_SET_GPIO20_GPIO36))
+
+/** @defgroup  GLB_GPIO_INT_TRIG_TYPE
+ *  @{
+ */
+#define IS_PDS_GPIO_INT_TRIG_TYPE(type) (((type) == PDS_GPIO_INT_SYNC_FALLING_EDGE) ||        \
+                                         ((type) == PDS_GPIO_INT_SYNC_RISING_EDGE) ||         \
+                                         ((type) == PDS_GPIO_INT_SYNC_LOW_LEVEL) ||           \
+                                         ((type) == PDS_GPIO_INT_SYNC_HIGH_LEVEL) ||          \
+                                         ((type) == PDS_GPIO_INT_SYNC_RISING_FALLING_EDGE) || \
+                                         ((type) == PDS_GPIO_INT_ASYNC_FALLING_EDGE) ||       \
+                                         ((type) == PDS_GPIO_INT_ASYNC_RISING_EDGE) ||        \
+                                         ((type) == PDS_GPIO_INT_ASYNC_LOW_LEVEL) ||          \
+                                         ((type) == PDS_GPIO_INT_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  PDS_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P70V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P75V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P80V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P85V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P90V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P95V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P00V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P05V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P10V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P15V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P20V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P25V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P30V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P35V))
+
+/** @defgroup  PDS_INT_TYPE
+ *  @{
+ */
+#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) ||           \
+                               ((type) == PDS_INT_RF_DONE) ||          \
+                               ((type) == PDS_INT_WIFI_TBTT_SLEEP) ||  \
+                               ((type) == PDS_INT_WIFI_TBTT_WAKEUP) || \
+                               ((type) == PDS_INT_MAX))
+
+/** @defgroup  PDS_AON_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||   \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||    \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||      \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||     \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_FALLING) || \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) ||  \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||   \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||     \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/*@} end of group PDS_Public_Constants */
+
+/** @defgroup  PDS_Public_Macros
+ *  @{
+ */
+#define PDS_LDO_MIN_PU_CNT      (25) /* LDO need 25 cycles to power up */
+#define PDS_WARMUP_LATENCY_CNT  (38) /* LDO hw warmup compensation latency cycles */
+#define PDS_INT_MASK_BIT_OFFSET (4)
+
+/*@} end of group PDS_Public_Macros */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void);
+#endif
+BL_Err_Type PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(PDS_GPIO_GROUP_SET_Type grp, uint8_t pu, uint8_t pd, uint8_t ie);
+BL_Err_Type PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask);
+BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig);
+BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set);
+BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad);
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg);
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg);
+BL_Err_Type PDS_Disable_GPIO_Keep(void);
+BL_Err_Type PDS_Set_MCU0_Clock_Enable(void);
+BL_Err_Type PDS_Set_MCU0_Clock_Disable(void);
+BL_Err_Type PDS_Set_MCU0_Reset_Address(uint32_t addr);
+BL_Err_Type PDS_Pu_PLL_Enable(void);
+BL_Err_Type PDS_Pu_PLL_Disable(void);
+/*----------*/
+BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt);
+BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5);
+BL_Err_Type PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg,
+                           PDS_CTRL_RAM3_Type *ram3Cfg, PDS_CTRL_RAM4_Type *ram4Cfg);
+/*----------*/
+BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt);
+/*----------*/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask);
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType);
+BL_Err_Type PDS_IntClear(void);
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type PDS_Trim_RC32M(void);
+/*----------*/
+BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady);
+BL_Err_Type PDS_Turn_Off_USB(void);
+BL_Err_Type PDS_Set_USB_Suspend(void);
+BL_Err_Type PDS_Set_USB_Resume(void);
+/*----------*/
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_PDS_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pm.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pm.h
new file mode 100755
index 0000000000..0bee062fed
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_pm.h
@@ -0,0 +1,43 @@
+#include "bl616_common.h"
+
+enum pm_pds_sleep_level {
+    PM_PDS_LEVEL_1 = 1,
+    PM_PDS_LEVEL_2 = 2,
+    PM_PDS_LEVEL_3 = 3,
+    PM_PDS_LEVEL_7 = 7,
+    PM_PDS_LEVEL_15 = 15,
+};
+
+enum pm_hbn_sleep_level {
+    PM_HBN_LEVEL_0,
+    PM_HBN_LEVEL_1,
+    PM_HBN_LEVEL_2,
+};
+
+enum pm_event_type {
+    PM_HBN_WAKEUP_EVENT_NONE,
+    PM_HBN_GPIO16_WAKEUP_EVENT,
+    PM_HBN_GPIO17_WAKEUP_EVENT,
+    PM_HBN_GPIO18_WAKEUP_EVENT,
+    PM_HBN_GPIO19_WAKEUP_EVENT,
+    PM_HBN_RTC_WAKEUP_EVENT,
+    PM_HBN_BOD_WAKEUP_EVENT,
+    PM_HBN_ACOMP0_WAKEUP_EVENT,
+    PM_HBN_ACOMP1_WAKEUP_EVENT,
+};
+
+void pm_pds_mask_all_wakeup_src(void);
+BL_Err_Type pm_pds_wakeup_src_en(uint32_t WakeupType);
+BL_Sts_Type pm_pds_get_wakeup_src(uint32_t WakeupType);
+void pm_pds_mode_enter(enum pm_pds_sleep_level pds_level, uint32_t sleep_time);
+void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level, uint8_t sleep_time);
+void pm_set_wakeup_callback(void (*wakeup_callback)(void));
+void pm_set_boot2_app_jump_para(uint32_t para);
+void pm_hbn_out0_irq_register(void);
+void pm_hbn_out1_irq_register(void);
+void HBN_OUT0_IRQ(void);
+void HBN_OUT1_IRQ(void);
+void pm_irq_callback(enum pm_event_type event);
+void pm_pds_irq_register(void);
+void PDS_WAKEUP_IRQ(void);
+void hal_pm_ldo11_use_ext_dcdc(void);
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_psram.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_psram.h
new file mode 100755
index 0000000000..054a866cb1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_psram.h
@@ -0,0 +1,487 @@
+/**
+  ******************************************************************************
+  * @file    bl616_psram.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2022 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_PSRAM_CTRL_H__
+#define __BL616_PSRAM_CTRL_H__
+
+#include "psram_reg.h"
+#include "bl616_common.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PSRAM_CTRL
+ *  @{
+ */
+
+/** @defgroup  PSRAM_CTRL_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief PSRAM ID
+ */
+typedef enum {
+    PSRAM0_ID, /*!< PSRAM0 identifier */
+} PSRAM_ID_Type;
+
+/**
+ *  @brief PSRAM Ctrl IO mode type definition
+ */
+typedef enum {
+    PSRAM_CTRL_X8_MODE,  /*!< PSRAM X8 mode */
+    PSRAM_CTRL_X16_MODE, /*!< PSRAM X16 mode */
+} PSRAM_Ctrl_Io_Mode_Type;
+
+/**
+ *  @brief PSRAM Ctrl  PSRAM vendor type definition
+ */
+typedef enum {
+    PSRAM_CTRL_VENDOR_WINBOND = 0x1,           /*!< Winbond psram */
+    PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB = 0x2, /*!< AP memory psram exclude 4MB size */
+    PSRAM_CTRL_VENDOR_APMEM_4MB = 0x4,         /*!< AP memory psram 4MB size */
+} PSRAM_Ctrl_Vendor_Type;
+
+/**
+ *  @brief PSRAM SIZE
+ */
+typedef enum {
+    PSRAM_SIZE_4MB = 0x3,   /*!< PSRAM size is 4MB */
+    PSRAM_SIZE_8MB = 0x7,   /*!< PSRAM size is 8MB */
+    PSRAM_SIZE_16MB = 0xf,  /*!< PSRAM size is 16MB */
+    PSRAM_SIZE_32MB = 0x1f, /*!< PSRAM size is 32MB */
+} PSRAM_Ctrl_Size_Type;
+
+/**
+ *  @brief Winbond PSRAM configuration register type definition
+ */
+typedef enum {
+    PSRAM_WINBOND_REG_ID0, /*!< Winbond register ID0 */
+    PSRAM_WINBOND_REG_ID1, /*!< Winbond register ID1 */
+    PSRAM_WINBOND_REG_CR0, /*!< Winbond register CR0 */
+    PSRAM_WINBOND_REG_CR1, /*!< Winbond register CR1 */
+    PSRAM_WINBOND_REG_CR2, /*!< Winbond register CR2 */
+    PSRAM_WINBOND_REG_CR3, /*!< Winbond register CR3 */
+    PSRAM_WINBOND_REG_CR4, /*!< Winbond register CR4 */
+} PSRAM_Ctrl_Winbond_Cfg_Reg_Type;
+
+/**
+ *  @brief APMemory PSRAM configuration register type definition
+ */
+typedef enum {
+    PSRAM_APMEM_REG_0 = 0, /*!< APMemory register 0 */
+    PSRAM_APMEM_REG_1,     /*!< APMemory register 1 */
+    PSRAM_APMEM_REG_2,     /*!< APMemory register 2 */
+    PSRAM_APMEM_REG_3,     /*!< APMemory register 3 */
+    PSRAM_APMEM_REG_4,     /*!< APMemory register 4 */
+    PSRAM_APMEM_REG_5,     /*!< APMemory register 5 */
+    PSRAM_APMEM_REG_6,     /*!< APMemory register 6 */
+    PSRAM_APMEM_REG_8,     /*!< APMemory register 8 */
+} PSRAM_Ctrl_ApMem_Cfg_Reg_Type;
+
+/**
+ *  @brief PSRAM Latency Counter type definition
+ */
+typedef enum {
+    PSRAM_WINBOND_5_CLOCKS_LATENCY,        /*!< PSRAM 5 clocks latency 133MHZ */
+    PSRAM_WINBOND_6_CLOCKS_LATENCY,        /*!< PSRAM 6 clocks latency 166MHZ */
+    PSRAM_WINBOND_7_CLOCKS_LATENCY,        /*!< PSRAM 7 clocks latency 200MHZ */
+    PSRAM_WINBOND_3_CLOCKS_LATENCY = 0xE,  /*!< PSRAM 3 clocks latency 83MHZ */
+    PSRAM_WINBOND_4_CLOCKS_LATENCY = 0xF,  /*!< PSRAM 4 clocks latency 100MHZ */
+    PSRAM_WINBOND_14_CLOCKS_LATENCY = 0x7, /*!< PSRAM 14 clocks latency only for Hyperbus3 400MHZ */
+    PSRAM_WINBOND_19_CLOCKS_LATENCY = 0x9, /*!< PSRAM 19 clocks latency only for Hyperbus3 533MHZ */
+} PSRAM_Latency_Winbond_Type;
+
+/**
+ *  @brief PSRAM Burst Type
+ */
+typedef enum {
+    PSRAM_HYBRID_BURST,  /*!< PSRAM use hybrid brust */
+    PSRAM_WRAPPED_BURST, /*!< PSRAM use warpped brust */
+} PSRAM_Burst_Type;
+
+/**
+ *  @brief PSRAM Latency Counter type definition
+ */
+typedef enum {
+    PSRAM_APMEM_3_CLOCKS_LATENCY,       /*!< PSRAM 3 clocks latency */
+    PSRAM_APMEM_4_CLOCKS_LATENCY = 0x4, /*!< PSRAM 4 clocks latency */
+    PSRAM_APMEM_5_CLOCKS_LATENCY = 0x2, /*!< PSRAM 5 clocks latency */
+    PSRAM_APMEM_6_CLOCKS_LATENCY = 0x6, /*!< PSRAM 6 clocks latency */
+    PSRAM_APMEM_7_CLOCKS_LATENCY = 0x1, /*!< PSRAM 7 clocks latency */
+} PSRAM_Latency_ApMem_Type;
+
+/**
+ *  @brief PSRAM Drive Strength type definition for Winbon 4M
+ */
+typedef enum {
+    PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M,  /*!< drive strength 50 ohms for 4M size ,34 ohms for 8M size */
+    PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M, /*!< drive strength 35 ohms for 4M size ,115 ohms for 8M size */
+    PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M, /*!< drive strength 100 ohms for 4M size ,67 ohms for 8M size */
+    PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M, /*!< drive strength 200 ohms for 4M size ,46 ohms for 8M size */
+    PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M,                    /*!< drive strength 34 ohms only for 8M size */
+    PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M,                    /*!< drive strength 27 ohms only for 8M size */
+    PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M,                    /*!< drive strength 22 ohms only for 8M size */
+    PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M,                    /*!< drive strength 19 ohms only for 8M size */
+} PSRAM_Winbond_Drive_Strength;
+
+/**
+ *  @brief PSRAM Drive Strength type definition for Winbon 8MB
+ */
+typedef enum {
+    PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS,  /*!< drive strength 25 ohms */
+    PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS,  /*!< drive strength 50 ohms */
+    PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS, /*!< drive strength 100 ohms */
+    PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS, /*!< drive strength 200 ohms */
+} PSRAM_ApMem_Drive_Strength;
+
+/**
+ *  @brief PSRAM Burst Length type definition
+ */
+typedef enum {
+    PSRAM_WINBOND_BURST_LENGTH_128_BYTES = 0x4, /*!< Burst Length 128 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_64_BYTES,        /*!< Burst Length 64 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_16_BYTES,        /*!< Burst Length 16 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_32_BYTES,        /*!< Burst Length 32 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_512_BYTES,       /*!< Burst Length 512 only for HyperBus3 */
+} PSRAM_Winbond_Burst_Length;
+
+/**
+ *  @brief PSRAM Burst Length type definition
+ */
+typedef enum {
+    PSRAM_APMEM_BURST_LENGTH_16_BYTES,                   /*!< Burst Length 16 bytes */
+    PSRAM_APMEM_BURST_LENGTH_32_BYTES,                   /*!< Burst Length 32 bytes */
+    PSRAM_APMEM_BURST_LENGTH_64_BYTES,                   /*!< Burst Length 64 bytes */
+    PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256, /*!< Burst Length 1K bytes for APS6408L and 2Kbytes for APS256XXN */
+} PSRAM_ApMem_Burst_Length;
+
+/**
+ *  @brief PSRAM Fixed Latency Enable type definition
+ */
+typedef enum {
+    PSRAM_VARIALBE_INITIAL_LATENCY,      /*!< 1 or 2 times Initial Latency depending on RWDS during CA cycles */
+    PSRAM_FIXED_2_TIMES_INITIAL_LATENCY, /*!< Fixed 2 times Initial Latency (default) */
+} PSRAM_Fixed_Latency_Enable;
+
+/**
+ *  @brief PSRAM Deep Power Down Enable type definition
+ */
+typedef enum {
+    PSRAM_DPD_ENTER,  /*!< Writing 0 to CR0[15] causes the device to enter Deep Power Down */
+    PSRAM_DPD_NORMAL, /*!< Normal operation (default) */
+} PSRAM_Deep_Power_Down;
+
+/**
+ *  @brief Partial Array Self Refresh definition
+ */
+typedef enum {
+    PSRAM_PARTIAL_REFRESH_FULL,        /*!< PSRAM partial refresh full array (000000h - 1FFFFFh) */
+    PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2, /*!< PSRAM partial refresh Bottom 1/2 array (000000h - 0FFFFFh) */
+    PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4, /*!< PSRAM partial refresh Bottom 1/4 array (000000h - 07FFFFh) */
+    PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8, /*!< PSRAM partial refresh Bottom 1/8 array (000000h - 03FFFFh) */
+    PSRAM_PARTIAL_REFRESH_NONE,        /*!< PSRAM partial refresh None */
+    PSRAM_PARTIAL_REFRESH_TOP_1TO2,    /*!< PSRAM partial refresh Top 1/2 array (100000h - 1FFFFFh) */
+    PSRAM_PARTIAL_REFRESH_TOP_1TO4,    /*!< PSRAM partial refresh Top 1/4 array (180000h - 1FFFFFh) */
+    PSRAM_PARTIAL_REFRESH_TOP_1TO8,    /*!< PSRAM partial refresh Top 1/8 array (1C0000h - 1FFFFFh) */
+} PSRAM_Partial_Array_Refresh;
+
+/**
+ *  @brief PSRAM ApMem self-fresh freq
+ */
+typedef enum {
+    PSRAM_APMEM_FAST_REFRESH, /*!< Fast Refresh (default) */
+    PSRAM_APMEM_SLOW_REFRESH, /*!< Enables Slow Refresh when temperature allows */
+} PSRAM_ApMem_Refresh_Speed;
+
+/**
+ *  @brief PSRAM Hybrid Sleep Mode type definition
+ */
+typedef enum {
+    PSRAM_HYBRID_SLEEP_DISABLE, /*!< not in Hybrid Sleep Mode */
+    PSRAM_HYBRID_SLEEP_ENABLE,  /*!< entering Hybrid Sleep Mode */
+} PSRAM_Hybrid_Sleep_Mode;
+
+/**
+ *  @brief PSRAM Master Clock type definition
+ */
+typedef enum {
+    PSRAM_CLOCK_DIFF,   /*!< PSRAM Master Clock is differential */
+    PSRAM_CLOCK_SINGLE, /*!< PSRAM Master Clock is single end */
+} PSRAM_Clock_Type;
+
+/**
+ *  @brief PSRAM delay chain configuration definition
+ */
+typedef struct
+{
+    PSRAM_Ctrl_Vendor_Type vendor;  /*!< PSRAM Vendor */
+    PSRAM_Ctrl_Io_Mode_Type ioMode; /*!< PSRAM interface mode */
+    PSRAM_Ctrl_Size_Type size;      /*!< PSRAM size */
+    uint32_t dqs_delay;             /*!< PSRAM dqs delay value */
+} PSRAM_Ctrl_Cfg_Type;
+
+/**
+ *  @brief PSRAM Winbon configuration definition
+ */
+typedef struct
+{
+    BL_Fun_Type rst;                            /*!< Winbond pSRAM CR1 - Software Reset */
+    PSRAM_Clock_Type clockType;                 /*!< Winbond pSRAM CR1 - Master Clock Type */
+    BL_Fun_Type inputPowerDownMode;             /*!< Winbond pSRAM CR1 - Input Power Down */
+    BL_Fun_Type linear_dis;                     /*!< Winbond pSRAM linear burst disable */
+    BL_Fun_Type hybridSleepMode;                /*!< Winbond pSRAM CR1 - Hybrid Sleep Mode configuration */
+    PSRAM_Partial_Array_Refresh PASR;           /*!< Winbond pSRAM CR1 - Partial Array Refresh + Distributed Refresh Interval */
+    BL_Fun_Type disDeepPowerDownMode;           /*!< Winbond pSRAM CR0 - Deep Power-Down Disable configuration */
+    BL_Fun_Type fixedLatency;                   /*!< Winbond pSRAM CR1 - Fix Latency configuration */
+    PSRAM_Winbond_Burst_Length brustLen;        /*!< Winbond pSRAM CR0 - Burst Length configuration */
+    PSRAM_Burst_Type brustType;                 /*!< Winbond pSRAM CR0 - Hybrid Burst Enable */
+    PSRAM_Winbond_Drive_Strength driveStrength; /*!< Winbond pSRAM CR0 - Drive Strength configuration */
+    PSRAM_Latency_Winbond_Type latency;         /*!< Winbond pSRAM CR0 - Latency Counter configuration */
+} PSRAM_Winbond_Cfg_Type;
+
+/**
+ *  @brief PSRAM Winbon configuration definition
+ */
+typedef struct
+{
+    BL_Fun_Type rst;                          /*!< AP Memory pSRAM configure global reset enable */
+    BL_Fun_Type fixedLatency;                 /*!< AP Memory pSRAM configure MR0 - read latency type */
+    PSRAM_Latency_ApMem_Type readLatency;     /*!< AP Memory pSRAM configure MR0 - read latency code */
+    PSRAM_ApMem_Refresh_Speed refreshFreq;    /*!< AP Memory pSRAM configure MR4 - refresh frequency */
+    PSRAM_ApMem_Drive_Strength driveStrength; /*!< AP Memory pSRAM configure MR0 - drive strength */
+    PSRAM_Latency_ApMem_Type writeLatency;    /*!< AP Memory pSRAM configure MR4 - write latency code */
+    PSRAM_Partial_Array_Refresh PASR;         /*!< AP Memory pSRAM configure MR4 - partial array refresh */
+    BL_Fun_Type halfSleepModeEnable;          /*!< AP Memory pSRAM configure MR6 - Half Sleep enable */
+    BL_Fun_Type deepPowerDownModeEnable;      /*!< AP Memory pSRAM configure MR6 - Deep Power Down enable */
+    BL_Fun_Type crossBoundaryEnable;          /*!< AP Memory pSRAM configure MR8 - cross boundary enable 1'b0 - Read within 1K boundary 1'b1 -
+                                                 Read cross 1K boundary */
+    PSRAM_Burst_Type brustType;               /*!< AP Memory pSRAM configure MR8 - burst type */
+    PSRAM_ApMem_Burst_Length brustLen;        /*!< AP Memory pSRAM configure MR8 - burst length */
+} PSRAM_APMemory_Cfg_Type;
+
+/*@} end of group PSRAM_CTRL_Public_Types */
+
+/** @defgroup  PSRAM_CTRL_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  PSRAM_ID_TYPE
+ *  @{
+ */
+#define IS_PSRAM_ID_TYPE(type) (((type) == PSRAM0_ID))
+
+/** @defgroup  PSRAM_CTRL_IO_MODE_TYPE
+ *  @{
+ */
+#define IS_PSRAM_CTRL_IO_MODE_TYPE(type) (((type) == PSRAM_CTRL_X8_MODE) || \
+                                          ((type) == PSRAM_CTRL_X16_MODE))
+
+/** @defgroup  PSRAM_CTRL_VENDOR_TYPE
+ *  @{
+ */
+#define IS_PSRAM_CTRL_VENDOR_TYPE(type) (((type) == PSRAM_CTRL_VENDOR_WINBOND) ||           \
+                                         ((type) == PSRAM_CTRL_VENDOR_APMEM_EXCLUDE_4MB) || \
+                                         ((type) == PSRAM_CTRL_VENDOR_APMEM_4MB))
+
+/** @defgroup  PSRAM_CTRL_SIZE_TYPE
+ *  @{
+ */
+#define IS_PSRAM_CTRL_SIZE_TYPE(type) (((type) == PSRAM_SIZE_4MB) ||  \
+                                       ((type) == PSRAM_SIZE_8MB) ||  \
+                                       ((type) == PSRAM_SIZE_16MB) || \
+                                       ((type) == PSRAM_SIZE_32MB))
+
+/** @defgroup  PSRAM_CTRL_WINBOND_CFG_REG_TYPE
+ *  @{
+ */
+#define IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(type) (((type) == PSRAM_WINBOND_REG_ID0) || \
+                                                  ((type) == PSRAM_WINBOND_REG_ID1) || \
+                                                  ((type) == PSRAM_WINBOND_REG_CR0) || \
+                                                  ((type) == PSRAM_WINBOND_REG_CR1) || \
+                                                  ((type) == PSRAM_WINBOND_REG_CR2) || \
+                                                  ((type) == PSRAM_WINBOND_REG_CR3) || \
+                                                  ((type) == PSRAM_WINBOND_REG_CR4))
+
+/** @defgroup  PSRAM_CTRL_APMEM_CFG_REG_TYPE
+ *  @{
+ */
+#define IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(type) (((type) == PSRAM_APMEM_REG_0) || \
+                                                ((type) == PSRAM_APMEM_REG_1) || \
+                                                ((type) == PSRAM_APMEM_REG_2) || \
+                                                ((type) == PSRAM_APMEM_REG_3) || \
+                                                ((type) == PSRAM_APMEM_REG_4) || \
+                                                ((type) == PSRAM_APMEM_REG_5) || \
+                                                ((type) == PSRAM_APMEM_REG_6) || \
+                                                ((type) == PSRAM_APMEM_REG_8))
+
+/** @defgroup  PSRAM_LATENCY_WINBOND_TYPE
+ *  @{
+ */
+#define IS_PSRAM_LATENCY_WINBOND_TYPE(type) (((type) == PSRAM_WINBOND_5_CLOCKS_LATENCY) ||  \
+                                             ((type) == PSRAM_WINBOND_6_CLOCKS_LATENCY) ||  \
+                                             ((type) == PSRAM_WINBOND_7_CLOCKS_LATENCY) ||  \
+                                             ((type) == PSRAM_WINBOND_3_CLOCKS_LATENCY) ||  \
+                                             ((type) == PSRAM_WINBOND_4_CLOCKS_LATENCY) ||  \
+                                             ((type) == PSRAM_WINBOND_14_CLOCKS_LATENCY) || \
+                                             ((type) == PSRAM_WINBOND_19_CLOCKS_LATENCY))
+
+/** @defgroup  PSRAM_BURST_TYPE
+ *  @{
+ */
+#define IS_PSRAM_BURST_TYPE(type) (((type) == PSRAM_HYBRID_BURST) || \
+                                   ((type) == PSRAM_WRAPPED_BURST))
+
+/** @defgroup  PSRAM_LATENCY_APMEM_TYPE
+ *  @{
+ */
+#define IS_PSRAM_LATENCY_APMEM_TYPE(type) (((type) == PSRAM_APMEM_3_CLOCKS_LATENCY) || \
+                                           ((type) == PSRAM_APMEM_4_CLOCKS_LATENCY) || \
+                                           ((type) == PSRAM_APMEM_5_CLOCKS_LATENCY) || \
+                                           ((type) == PSRAM_APMEM_6_CLOCKS_LATENCY) || \
+                                           ((type) == PSRAM_APMEM_7_CLOCKS_LATENCY))
+
+/** @defgroup  PSRAM_WINBOND_DRIVE_STRENGTH
+ *  @{
+ */
+#define IS_PSRAM_WINBOND_DRIVE_STRENGTH(type) (((type) == PSRAM_WINBOND_DRIVE_STRENGTH_50_OHMS_FOR_4M_34_OHMS_FOR_8M) ||  \
+                                               ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_35_OHMS_FOR_4M_115_OHMS_FOR_8M) || \
+                                               ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_100_OHMS_FOR_4M_67_OHMS_FOR_8M) || \
+                                               ((type) == PSRAM_WINBOND_DRIVE_STRENGTH_200_OHMS_FOR_4M_46_OHMS_FOR_8M) || \
+                                               ((type) == PSRAM_DRIVE_STRENGTH_34_OHMS_ONLY_FOR_8M) ||                    \
+                                               ((type) == PSRAM_DRIVE_STRENGTH_27_OHMS_ONLY_FOR_8M) ||                    \
+                                               ((type) == PSRAM_DRIVE_STRENGTH_22_OHMS_ONLY_FOR_8M) ||                    \
+                                               ((type) == PSRAM_DRIVE_STRENGTH_19_OHMS_ONLY_FOR_8M))
+
+/** @defgroup  PSRAM_APMEM_DRIVE_STRENGTH
+ *  @{
+ */
+#define IS_PSRAM_APMEM_DRIVE_STRENGTH(type) (((type) == PSRAM_APMEM_DRIVE_STRENGTH_25_OHMS) ||  \
+                                             ((type) == PSRAM_APMEM_DRIVE_STRENGTH_50_OHMS) ||  \
+                                             ((type) == PSRAM_APMEM_DRIVE_STRENGTH_100_OHMS) || \
+                                             ((type) == PSRAM_APMEM_DRIVE_STRENGTH_200_OHMS))
+
+/** @defgroup  PSRAM_WINBOND_BURST_LENGTH
+ *  @{
+ */
+#define IS_PSRAM_WINBOND_BURST_LENGTH(type) (((type) == PSRAM_WINBOND_BURST_LENGTH_128_BYTES) || \
+                                             ((type) == PSRAM_WINBOND_BURST_LENGTH_64_BYTES) ||  \
+                                             ((type) == PSRAM_WINBOND_BURST_LENGTH_16_BYTES) ||  \
+                                             ((type) == PSRAM_WINBOND_BURST_LENGTH_32_BYTES) ||  \
+                                             ((type) == PSRAM_WINBOND_BURST_LENGTH_512_BYTES))
+
+/** @defgroup  PSRAM_APMEM_BURST_LENGTH
+ *  @{
+ */
+#define IS_PSRAM_APMEM_BURST_LENGTH(type) (((type) == PSRAM_APMEM_BURST_LENGTH_16_BYTES) || \
+                                           ((type) == PSRAM_APMEM_BURST_LENGTH_32_BYTES) || \
+                                           ((type) == PSRAM_APMEM_BURST_LENGTH_64_BYTES) || \
+                                           ((type) == PSRAM_APMEM_BURST_LENGTH_1K_FOR_APS64_2K_FOR_APS256))
+
+/** @defgroup  PSRAM_FIXED_LATENCY_ENABLE
+ *  @{
+ */
+#define IS_PSRAM_FIXED_LATENCY_ENABLE(type) (((type) == PSRAM_VARIALBE_INITIAL_LATENCY) || \
+                                             ((type) == PSRAM_FIXED_2_TIMES_INITIAL_LATENCY))
+
+/** @defgroup  PSRAM_DEEP_POWER_DOWN
+ *  @{
+ */
+#define IS_PSRAM_DEEP_POWER_DOWN(type) (((type) == PSRAM_DPD_ENTER) || \
+                                        ((type) == PSRAM_DPD_NORMAL))
+
+/** @defgroup  PSRAM_PARTIAL_ARRAY_REFRESH
+ *  @{
+ */
+#define IS_PSRAM_PARTIAL_ARRAY_REFRESH(type) (((type) == PSRAM_PARTIAL_REFRESH_FULL) ||        \
+                                              ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO2) || \
+                                              ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO4) || \
+                                              ((type) == PSRAM_PARTIAL_REFRESH_BOTTOM_1TO8) || \
+                                              ((type) == PSRAM_PARTIAL_REFRESH_NONE) ||        \
+                                              ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO2) ||    \
+                                              ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO4) ||    \
+                                              ((type) == PSRAM_PARTIAL_REFRESH_TOP_1TO8))
+
+/** @defgroup  PSRAM_APMEM_REFRESH_SPEED
+ *  @{
+ */
+#define IS_PSRAM_APMEM_REFRESH_SPEED(type) (((type) == PSRAM_APMEM_FAST_REFRESH) || \
+                                            ((type) == PSRAM_APMEM_SLOW_REFRESH))
+
+/** @defgroup  PSRAM_HYBRID_SLEEP_MODE
+ *  @{
+ */
+#define IS_PSRAM_HYBRID_SLEEP_MODE(type) (((type) == PSRAM_HYBRID_SLEEP_DISABLE) || \
+                                          ((type) == PSRAM_HYBRID_SLEEP_ENABLE))
+
+/** @defgroup  PSRAM_CLOCK_TYPE
+ *  @{
+ */
+#define IS_PSRAM_CLOCK_TYPE(type) (((type) == PSRAM_CLOCK_DIFF) || \
+                                   ((type) == PSRAM_CLOCK_SINGLE))
+
+/*@} end of group PSRAM_CTRL_Public_Constants */
+
+/** @defgroup  PSRAM_CTRL_Public_Macros
+ *  @{
+ */
+
+/*@} end of group PSRAM_CTRL_Public_Macros */
+
+/** @defgroup  PSRAM_CTRL_Public_Functions
+ *  @{
+ */
+void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg);
+BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);
+BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,
+                                         PSRAM_Winbond_Cfg_Type *reg_cfg);
+BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);
+BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,
+                                       PSRAM_APMemory_Cfg_Type *reg_cfg);
+void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID);
+void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel);
+void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID);
+uint8_t PSram_Ctrl_Get_Timeout_Flag(PSRAM_ID_Type PSRAM_ID);
+void PSram_Ctrl_Clear_Timout_Flag(PSRAM_ID_Type PSRAM_ID);
+void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t timeoutThr);
+
+/*@} end of group PSRAM_CTRL_Public_Functions */
+
+/*@} end of group PSRAM_CTRL */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_PSRAM_CTRL_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romapi_patch.h
old mode 100644
new mode 100755
similarity index 70%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romapi_patch.h
index 453ff3e345..53259618c0
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romapi_patch.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romapi_patch.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_romapi_patch.h
+  * @file    bl616_romapi_patch.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,24 +33,13 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_ROMAPI_PATCH_H__
-#define __BL808_ROMAPI_PATCH_H__
+#ifndef __BL616_ROMAPI_PATCH_H__
+#define __BL616_ROMAPI_PATCH_H__
 
-#include "bl808_uart.h"
-#include "bl808_pds.h"
-#include "bl808_sflash.h"
-#include "bl808_xip_sflash.h"
-#include "bl808_ef_ctrl.h"
-#include "bl808_clock.h"
-#include "bl808_hbn.h"
-#include "softcrc.h"
-#include "bl808_sf_ctrl.h"
-
-
-BL_Err_Type GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_Type pllType, GLB_PLL_REF_CLK_Type refClk);
-BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg,
-                                               uint8_t group, SF_Ctrl_Bank_Select bank);
-uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault,
-                                   SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank);
+#include "bflb_sflash.h"
+#include "bflb_xip_sflash.h"
+#include "bl616_pds.h"
+#include "bl616_clock.h"
+// #include "bl616_uart.h"
 
 #endif
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romdriver_e907.h
old mode 100644
new mode 100755
similarity index 64%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romdriver_e907.h
index 52ed7d5057..2e23abef4b
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_romdriver_e907.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_romdriver_e907.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_romdriver_e907.h
+  * @file    bl616_romdriver_e907.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,19 +33,22 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_ROMDRIVER_E907_H__
-#define __BL808_ROMDRIVER_E907_H__
+#ifndef __BL616_ROMDRIVER_E907_H__
+#define __BL616_ROMDRIVER_E907_H__
 
-#include "bl808_glb.h"
-#include "bl808_pds.h"
-#include "bl808_hbn.h"
-#include "bl808_clock.h"
-#include "bl808_uart.h"
-#include "bl808_sflash.h"
-#include "bl808_xip_sflash.h"
-#include "bl808_ef_ctrl.h"
+#include "bl616_glb.h"
+#include "bl616_glb_gpio.h"
+#include "bl616_pds.h"
+#include "bl616_hbn.h"
+#include "bl616_clock.h"
+#include "bl616_ef_ctrl.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_cfg.h"
+#include "bflb_xip_sflash.h"
+// #include "bl616_uart.h"
 
-/** @addtogroup  bl808_Peripheral_Driver
+/** @addtogroup  bl616_Peripheral_Driver
  *  @{
  */
 
@@ -67,8 +70,6 @@ typedef enum {
     ROM_API_INDEX_RSVD_LAST,
 
 
-    ROM_API_INDEX_AON_LowPower_Enter_PDS0,
-    ROM_API_INDEX_AON_LowPower_Exit_PDS0,
     ROM_API_INDEX_AON_Power_Off_BG,
     ROM_API_INDEX_AON_Power_Off_LDO15_RF,
     ROM_API_INDEX_AON_Power_Off_MBG,
@@ -79,17 +80,34 @@ typedef enum {
     ROM_API_INDEX_AON_Power_On_MBG,
     ROM_API_INDEX_AON_Power_On_SFReg,
     ROM_API_INDEX_AON_Power_On_XTAL,
-    ROM_API_INDEX_AON_Set_DCDC11_Top_Vout,
     ROM_API_INDEX_AON_Set_Xtal_CapCode,
-    ROM_API_INDEX_AON_Trim_DCDC11_Vout,
-    ROM_API_INDEX_AON_Trim_DCDC18_Vout,
-    ROM_API_INDEX_AON_Trim_USB20_RCAL,
+    ROM_API_INDEX_AON_Trim_DcdcDis,
+    ROM_API_INDEX_AON_Trim_DcdcVoutSel,
+    ROM_API_INDEX_AON_Trim_DcdcVoutTrim,
+    ROM_API_INDEX_AON_Trim_Ldo11socVoutTrim,
+    ROM_API_INDEX_AON_Trim_Usb20RcalCode,
     ROM_API_INDEX_AON_Get_Xtal_CapCode,
 
-    ROM_API_INDEX_ASM_Delay_Us,
+    ROM_API_INDEX_CPU_MTimer_Delay_MS,
+    ROM_API_INDEX_CPU_MTimer_Delay_US,
+    ROM_API_INDEX_CPU_Reset_MTimer,
+    ROM_API_INDEX_CPU_Set_MTimer_CLK,
+    ROM_API_INDEX_CPU_Set_MTimer_RST,
+    ROM_API_INDEX_CPU_Get_MTimer_Clock,
+    ROM_API_INDEX_CPU_Get_MTimer_Source_Clock,
 
-    ROM_API_INDEX_arch_delay_ms,
-    ROM_API_INDEX_arch_delay_us,
+    ROM_API_INDEX_Clock_Audio_ADC_Clock_Get,
+    ROM_API_INDEX_Clock_Get_ISP_Clk,
+    ROM_API_INDEX_Clock_Get_PSRAMB_Clk,
+    ROM_API_INDEX_Clock_Peripheral_Clock_Get,
+    ROM_API_INDEX_Clock_System_Clock_Get,
+
+    ROM_API_INDEX_SystemCoreClockGet,
+
+    ROM_API_INDEX_CPU_Get_CPU_Cycle,
+    ROM_API_INDEX_CPU_Get_MTimer_Counter,
+    ROM_API_INDEX_CPU_Get_MTimer_MS,
+    ROM_API_INDEX_CPU_Get_MTimer_US,
 
     ROM_API_INDEX_EF_Ctrl_Crc_Result,
     ROM_API_INDEX_EF_Ctrl_Get_Customer_PIDVID,
@@ -101,40 +119,37 @@ typedef enum {
     ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy,
     ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity,
     ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero,
+    ROM_API_INDEX_EF_Ctrl_Read_FlashDlyCoe,
     ROM_API_INDEX_EF_Ctrl_Clear,
     ROM_API_INDEX_EF_Ctrl_Crc_Enable,
     ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden,
     ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0,
-    ROM_API_INDEX_EF_Ctrl_Load_Efuse_R1,
-    ROM_API_INDEX_EF_Ctrl_Program_Direct,
     ROM_API_INDEX_EF_Ctrl_Program_Direct_R0,
-    ROM_API_INDEX_EF_Ctrl_Program_Direct_R1,
     ROM_API_INDEX_EF_Ctrl_Program_Efuse_0,
-    ROM_API_INDEX_EF_Ctrl_Program_Efuse_1,
     ROM_API_INDEX_EF_Ctrl_Read_ADC_Gain_Trim,
     ROM_API_INDEX_EF_Ctrl_Read_AES_Key,
-    ROM_API_INDEX_EF_Ctrl_Read_DCDC11_Trim,
-    ROM_API_INDEX_EF_Ctrl_Read_DCDC18_Trim,
     ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd,
+    ROM_API_INDEX_EF_Ctrl_Read_DcdcDis_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_DcdcVoutSel_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_DcdcVoutTrim_Trim,
     ROM_API_INDEX_EF_Ctrl_Read_Device_Info,
-    ROM_API_INDEX_EF_Ctrl_Read_Direct,
     ROM_API_INDEX_EF_Ctrl_Read_Direct_R0,
-    ROM_API_INDEX_EF_Ctrl_Read_Direct_R1,
-    ROM_API_INDEX_EF_Ctrl_Read_LDO18FLASH_Trim,
-    ROM_API_INDEX_EF_Ctrl_Read_LDO18IO_Vout_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_Ldo11socVoutTrim_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioBypass_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioVoutSel_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioVoutTrim_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_Ldo33VoutTrim_Trim,
     ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim,
     ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim,
     ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot,
     ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg,
     ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage,
     ROM_API_INDEX_EF_Ctrl_Read_TSEN_Trim,
-    ROM_API_INDEX_EF_Ctrl_Read_USB20RCAL_Trim,
-    ROM_API_INDEX_EF_Ctrl_Read_Xtal_Trim_RC32M,
+    ROM_API_INDEX_EF_Ctrl_Read_Usb20RcalCode_Trim,
     ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key,
     ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd,
     ROM_API_INDEX_EF_Ctrl_Set_sf_key_re_sel,
     ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0,
-    ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_1,
     ROM_API_INDEX_EF_Ctrl_Write_AES_Key,
     ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd,
     ROM_API_INDEX_EF_Ctrl_Write_MAC_Address,
@@ -146,149 +161,90 @@ typedef enum {
     ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address,
     ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage,
 
-    ROM_API_INDEX_GLB_AHB_DSP_Software_Reset,
     ROM_API_INDEX_GLB_AHB_MCU_Software_Reset,
+    ROM_API_INDEX_GLB_AUPLL_Ref_Clk_Sel,
     ROM_API_INDEX_GLB_BMX_TO_Init,
     ROM_API_INDEX_GLB_Clr_BMX_TO_Status,
     ROM_API_INDEX_GLB_Clr_EMI_Reset_Gate,
-    ROM_API_INDEX_GLB_Config_AUDIO_PLL,
-    ROM_API_INDEX_GLB_Config_CPU_PLL,
-    ROM_API_INDEX_GLB_Config_MIPI_PLL,
-    ROM_API_INDEX_GLB_Config_MIPI_PLL_Div,
-    ROM_API_INDEX_GLB_Config_UHS_PLL,
-    ROM_API_INDEX_GLB_Config_WIFI_PLL,
-    ROM_API_INDEX_GLB_DSP0_Clock_Disable,
-    ROM_API_INDEX_GLB_DSP0_Clock_Enable,
-    ROM_API_INDEX_GLB_DSP_Clr_MCU_IntStatus,
-    ROM_API_INDEX_GLB_DSP_Codec_Sub_Reset,
-    ROM_API_INDEX_GLB_DSP_DSP2_Sub_Reset,
-    ROM_API_INDEX_GLB_DSP_Image_Sensor_Reset,
-    ROM_API_INDEX_GLB_DSP_Peripheral_Reset,
-    ROM_API_INDEX_GLB_DSP_SW_System_Reset,
-    ROM_API_INDEX_GLB_DSP_Set_LP_IntEn,
-    ROM_API_INDEX_GLB_DSP_Set_MCU_IntMask,
+    ROM_API_INDEX_GLB_Clr_Reset_Reason,
+    ROM_API_INDEX_GLB_Config_SDIO_Host_Interrupt_CPU,
+    ROM_API_INDEX_GLB_Config_SDIO_Host_Reset_SDU,
+    ROM_API_INDEX_GLB_Config_SDIO_Host_Reset_System,
     ROM_API_INDEX_GLB_Get_Auto_Calc_Xtal_Type,
-    ROM_API_INDEX_GLB_Get_DSP_PBCLK_Div,
-    ROM_API_INDEX_GLB_Get_DSP_System_CLK_Div,
     ROM_API_INDEX_GLB_Get_MCU_System_CLK_Div,
-    ROM_API_INDEX_GLB_Halt_CPU,
-    ROM_API_INDEX_GLB_IR_LED_Driver_Disable,
-    ROM_API_INDEX_GLB_IR_LED_Driver_Enable,
+    ROM_API_INDEX_GLB_Get_Reset_Reason,
     ROM_API_INDEX_GLB_IR_RX_GPIO_Sel,
     ROM_API_INDEX_GLB_Invert_ETH_REF_O_CLK,
     ROM_API_INDEX_GLB_Invert_ETH_RX_CLK,
     ROM_API_INDEX_GLB_Invert_ETH_TX_CLK,
-    ROM_API_INDEX_GLB_MCU_Clr_DSP_IntStatus,
     ROM_API_INDEX_GLB_MCU_SW_System_Reset,
-    ROM_API_INDEX_GLB_MCU_Set_DSP_IntMask,
-    ROM_API_INDEX_GLB_Output_EMAC_CLK,
     ROM_API_INDEX_GLB_PER_Clock_Gate,
     ROM_API_INDEX_GLB_PER_Clock_UnGate,
     ROM_API_INDEX_GLB_PLL_CGEN_Clock_Gate,
     ROM_API_INDEX_GLB_PLL_CGEN_Clock_UnGate,
     ROM_API_INDEX_GLB_Platform_Wakeup_PDS_Enable,
-    ROM_API_INDEX_GLB_Power_Off_MU_PLL,
-    ROM_API_INDEX_GLB_Power_Off_WAC_PLL,
-    ROM_API_INDEX_GLB_Power_On_MU_PLL,
-    ROM_API_INDEX_GLB_Power_On_WAC_PLL,
+    ROM_API_INDEX_GLB_Power_Off_AUPLL,
+    ROM_API_INDEX_GLB_Power_Off_WIFIPLL,
+    ROM_API_INDEX_GLB_Power_On_AUPLL,
+    ROM_API_INDEX_GLB_Power_On_WIFIPLL,
     ROM_API_INDEX_GLB_Power_On_XTAL_And_PLL_CLK,
-    ROM_API_INDEX_GLB_Release_CPU,
+    ROM_API_INDEX_GLB_SPI_Sig_Swap_Set,
     ROM_API_INDEX_GLB_SW_CPU_Reset,
     ROM_API_INDEX_GLB_SW_POR_Reset,
     ROM_API_INDEX_GLB_SW_System_Reset,
-    ROM_API_INDEX_GLB_Sel_DSP_TMR_GPIO_Clock,
     ROM_API_INDEX_GLB_Sel_MCU_TMR_GPIO_Clock,
     ROM_API_INDEX_GLB_Set_ADC_CLK,
     ROM_API_INDEX_GLB_Set_Audio_ADC_CLK,
     ROM_API_INDEX_GLB_Set_Audio_AUTO_CLK,
-    ROM_API_INDEX_GLB_Set_Audio_DAC_CLK,
-    ROM_API_INDEX_GLB_Set_Audio_PDM_CLK,
+    ROM_API_INDEX_GLB_Set_Audio_SOLO_CLK,
     ROM_API_INDEX_GLB_Set_Auto_Calc_Xtal_Type,
     ROM_API_INDEX_GLB_Set_CAM_CLK,
     ROM_API_INDEX_GLB_Set_CPU_Reset_Address,
-    ROM_API_INDEX_GLB_Set_CSI_DSI_CLK_Sel,
-    ROM_API_INDEX_GLB_Set_Chip_Clock_Out0_Sel,
-    ROM_API_INDEX_GLB_Set_Chip_Clock_Out1_Sel,
-    ROM_API_INDEX_GLB_Set_Chip_Clock_Out2_Sel,
-    ROM_API_INDEX_GLB_Set_Chip_Clock_Out3_Sel,
+    ROM_API_INDEX_GLB_Set_Chip_Clock_Out_Sel,
+    ROM_API_INDEX_GLB_Set_DBI_CLK,
     ROM_API_INDEX_GLB_Set_DIG_32K_CLK,
     ROM_API_INDEX_GLB_Set_DIG_512K_CLK,
     ROM_API_INDEX_GLB_Set_DIG_CLK_Sel,
     ROM_API_INDEX_GLB_Set_DMA_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_CNN_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_DP_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_H264_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_I2C0_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_I2C1_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_DSP2_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_L2SRAM_Available_Size,
-    ROM_API_INDEX_GLB_Set_DSP_MTimer_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_MUXPLL_CLK_Sel,
-    ROM_API_INDEX_GLB_Set_DSP_Muxpll_160M_Sel,
-    ROM_API_INDEX_GLB_Set_DSP_Muxpll_240M_Sel,
-    ROM_API_INDEX_GLB_Set_DSP_Muxpll_320M_Sel,
-    ROM_API_INDEX_GLB_Set_DSP_PBCLK,
-    ROM_API_INDEX_GLB_Set_DSP_PBCLK_Div,
-    ROM_API_INDEX_GLB_Set_DSP_PBROOT_CLK_Sel,
-    ROM_API_INDEX_GLB_Set_DSP_ROOT_CLK_Sel,
-    ROM_API_INDEX_GLB_Set_DSP_SPI_0_ACT_MOD_Sel,
-    ROM_API_INDEX_GLB_Set_DSP_SPI_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_System_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_System_CLK_Div,
-    ROM_API_INDEX_GLB_Set_DSP_UART0_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_UART1_CLK,
-    ROM_API_INDEX_GLB_Set_DSP_XCLK_Sel,
-    ROM_API_INDEX_GLB_Set_Display_CLK,
-    ROM_API_INDEX_GLB_Set_EMAC_CLK,
-    ROM_API_INDEX_GLB_Set_EMI_CLK,
     ROM_API_INDEX_GLB_Set_EM_Sel,
     ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel,
-    ROM_API_INDEX_GLB_Set_Flash_IO_PARM,
-    ROM_API_INDEX_GLB_Set_Flash_Id_Value,
+    ROM_API_INDEX_GLB_Set_PEC_CLK,
     ROM_API_INDEX_GLB_Set_I2C_CLK,
     ROM_API_INDEX_GLB_Set_I2S_CLK,
     ROM_API_INDEX_GLB_Set_IR_CLK,
-    ROM_API_INDEX_GLB_Set_MCU_MTimer_CLK,
+    ROM_API_INDEX_GLB_Set_ISP_Muxpll_80M_Sel,
     ROM_API_INDEX_GLB_Set_MCU_Muxpll_160M_Sel,
     ROM_API_INDEX_GLB_Set_MCU_Muxpll_80M_Sel,
     ROM_API_INDEX_GLB_Set_MCU_SPI_0_ACT_MOD_Sel,
     ROM_API_INDEX_GLB_Set_MCU_System_CLK,
     ROM_API_INDEX_GLB_Set_MCU_System_CLK_Div,
-    ROM_API_INDEX_GLB_Set_PADC_CLK,
     ROM_API_INDEX_GLB_Set_PDM_IO_Sel,
     ROM_API_INDEX_GLB_Set_PKA_CLK_Sel,
-    ROM_API_INDEX_GLB_Set_PSram_CLK,
+    ROM_API_INDEX_GLB_Set_PSRAMB_CLK_Sel,
     ROM_API_INDEX_GLB_Set_PWM1_IO_Sel,
-    ROM_API_INDEX_GLB_Set_PWM2_IO_Sel,
     ROM_API_INDEX_GLB_Set_Peripheral_DMA_CN,
     ROM_API_INDEX_GLB_Set_SDH_CLK,
     ROM_API_INDEX_GLB_Set_SF_CLK,
+    ROM_API_INDEX_GLB_Set_SFlash2_IO_PARM,
+    ROM_API_INDEX_GLB_Set_SFlash_IO_PARM,
     ROM_API_INDEX_GLB_Set_SPI_CLK,
     ROM_API_INDEX_GLB_Set_SRAM_PARM,
     ROM_API_INDEX_GLB_Set_SRAM_RET,
     ROM_API_INDEX_GLB_Set_SRAM_SLP,
-    ROM_API_INDEX_GLB_Set_UART2_IO_Sel,
+    ROM_API_INDEX_GLB_Set_SSC_CLK_From_WIFIPLL,
+    ROM_API_INDEX_GLB_Set_Slave_Grp_0_CLK,
     ROM_API_INDEX_GLB_Set_UART_CLK,
     ROM_API_INDEX_GLB_Set_USB_CLK_From_WIFIPLL,
-    ROM_API_INDEX_GLB_Swap_DSP_SPI_0_MOSI_With_MISO,
     ROM_API_INDEX_GLB_Swap_MCU_SPI_0_MOSI_With_MISO,
-    ROM_API_INDEX_GLB_Trim_LDO18FLASH_Vout,
-    ROM_API_INDEX_GLB_Trim_LDO18IO_Vout,
+    ROM_API_INDEX_GLB_Trim_Ldo18ioBypass,
+    ROM_API_INDEX_GLB_Trim_Ldo18ioVoutSel,
+    ROM_API_INDEX_GLB_Trim_Ldo18ioVoutTrim,
     ROM_API_INDEX_GLB_UART_Fun_Sel,
     ROM_API_INDEX_GLB_UART_Sig_Swap_Set,
-    ROM_API_INDEX_GLB_DSP_Get_LP_IntStatus,
-    ROM_API_INDEX_GLB_DSP_Get_MCU_IntStatus,
-    ROM_API_INDEX_GLB_MCU_Get_DSP_IntStatus,
+    ROM_API_INDEX_GLB_WIFIPLL_Ref_Clk_Sel,
     ROM_API_INDEX_GLB_Get_Core_Type,
-    ROM_API_INDEX_GLB_Get_DSP_Muxpll_160M_Sel,
-    ROM_API_INDEX_GLB_Get_DSP_Muxpll_240M_Sel,
-    ROM_API_INDEX_GLB_Get_DSP_Muxpll_320M_Sel,
-    ROM_API_INDEX_GLB_Get_DSP_PBROOT_CLK_Sel,
-    ROM_API_INDEX_GLB_Get_DSP_ROOT_CLK_Sel,
-    ROM_API_INDEX_GLB_Get_DSP_XCLK_Sel,
     ROM_API_INDEX_GLB_Get_MCU_Muxpll_160M_Sel,
     ROM_API_INDEX_GLB_Get_MCU_Muxpll_80M_Sel,
-    ROM_API_INDEX_GLB_Get_Flash_Id_Value,
     ROM_API_INDEX_GLB_Get_SRAM_PARM,
     ROM_API_INDEX_GLB_Get_SRAM_RET,
     ROM_API_INDEX_GLB_Get_SRAM_SLP,
@@ -322,9 +278,12 @@ typedef enum {
 
     ROM_API_INDEX_HBN_32K_Sel,
     ROM_API_INDEX_HBN_Aon_Pad_Cfg,
+    ROM_API_INDEX_HBN_Aon_Pad_Cfg_Set,
     ROM_API_INDEX_HBN_Aon_Pad_Ctrl,
     ROM_API_INDEX_HBN_Aon_Pad_WakeUpCfg,
+    ROM_API_INDEX_HBN_Clear_Gpio_Keep,
     ROM_API_INDEX_HBN_Clear_IRQ,
+    ROM_API_INDEX_HBN_Clear_PDS_Gpio_Keep,
     ROM_API_INDEX_HBN_Clear_RTC_Counter,
     ROM_API_INDEX_HBN_Clear_RTC_INT,
     ROM_API_INDEX_HBN_Disable_AComp0_IRQ,
@@ -336,12 +295,14 @@ typedef enum {
     ROM_API_INDEX_HBN_Enable_RTC_Counter,
     ROM_API_INDEX_HBN_GPIO_INT_Disable,
     ROM_API_INDEX_HBN_GPIO_INT_Enable,
-    ROM_API_INDEX_HBN_Get_RTC_Misc_Cfg,
+    ROM_API_INDEX_HBN_Get_Flash_Power_Delay,
+    ROM_API_INDEX_HBN_Get_Gpio_Keep,
+    ROM_API_INDEX_HBN_Get_Ldo18io_Power_Delay_Config,
+    ROM_API_INDEX_HBN_Get_PDS_Gpio_Keep,
     ROM_API_INDEX_HBN_Get_RTC_Timer_Val,
     ROM_API_INDEX_HBN_Get_Xtal_Type,
     ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg,
-    ROM_API_INDEX_HBN_PD_RC32K_All_State,
-    ROM_API_INDEX_HBN_PD_RC32K_In_Poff,
+    ROM_API_INDEX_HBN_Keep_On_RC32K,
     ROM_API_INDEX_HBN_PIR_Disable,
     ROM_API_INDEX_HBN_PIR_Enable,
     ROM_API_INDEX_HBN_PIR_HPF_Sel,
@@ -350,46 +311,45 @@ typedef enum {
     ROM_API_INDEX_HBN_Pin_WakeUp_Mask,
     ROM_API_INDEX_HBN_Power_Off_RC32K,
     ROM_API_INDEX_HBN_Power_Off_Xtal_32K,
-    ROM_API_INDEX_HBN_Power_On_RC32K,
     ROM_API_INDEX_HBN_Power_On_Xtal_32K,
     ROM_API_INDEX_HBN_Reset,
     ROM_API_INDEX_HBN_Set_BOD_Cfg,
     ROM_API_INDEX_HBN_Set_BOD_Config,
     ROM_API_INDEX_HBN_Set_Core_Reboot_Config,
+    ROM_API_INDEX_HBN_Set_Flash_Power_Delay,
+    ROM_API_INDEX_HBN_Set_GPADC_CLK_Sel,
+    ROM_API_INDEX_HBN_Set_Gpio_Keep,
     ROM_API_INDEX_HBN_Set_HRAM_Ret,
     ROM_API_INDEX_HBN_Set_HRAM_slp,
-    ROM_API_INDEX_HBN_Set_Hand_Off_Config,
-    ROM_API_INDEX_HBN_Set_IO4041_As_Xtal_32K_IO,
     ROM_API_INDEX_HBN_Set_Ldo11_All_Vout,
     ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout,
     ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout,
-    ROM_API_INDEX_HBN_Set_Ldo11_Rtc_Vout,
-    ROM_API_INDEX_HBN_Set_Ldo18flash_Repower_Delay,
+    ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout,
+    ROM_API_INDEX_HBN_Set_Ldo18io_Power_Delay_Config,
     ROM_API_INDEX_HBN_Set_MCU_Root_CLK_Sel,
     ROM_API_INDEX_HBN_Set_MCU_XCLK_Sel,
-    ROM_API_INDEX_HBN_Set_MM_Power_Config,
+    ROM_API_INDEX_HBN_Set_PDS_Gpio_Keep,
     ROM_API_INDEX_HBN_Set_PIR_Interval,
     ROM_API_INDEX_HBN_Set_PIR_Threshold,
-    ROM_API_INDEX_HBN_Set_RTC_Misc_Cfg,
     ROM_API_INDEX_HBN_Set_RTC_Timer,
     ROM_API_INDEX_HBN_Set_Status_Flag,
     ROM_API_INDEX_HBN_Set_UART_CLK_Sel,
+    ROM_API_INDEX_HBN_Set_User_Boot_Config,
     ROM_API_INDEX_HBN_Set_Wakeup_Addr,
     ROM_API_INDEX_HBN_Set_Xtal_Type,
+    ROM_API_INDEX_HBN_Trim_Ldo33VoutTrim,
     ROM_API_INDEX_HBN_Trim_RC32K,
     ROM_API_INDEX_HBN_Get_BOD_OUT_State,
     ROM_API_INDEX_HBN_Get_INT_State,
     ROM_API_INDEX_HBN_Get_MCU_Root_CLK_Sel,
     ROM_API_INDEX_HBN_Get_MCU_XCLK_Sel,
-    ROM_API_INDEX_HBN_Get_Ldo18flash_Repower_Config,
     ROM_API_INDEX_HBN_Get_PIR_Interval,
     ROM_API_INDEX_HBN_Get_PIR_Threshold,
     ROM_API_INDEX_HBN_Get_Status_Flag,
     ROM_API_INDEX_HBN_Get_Wakeup_Addr,
     ROM_API_INDEX_HBN_Get_Core_Unhalt_Config,
-    ROM_API_INDEX_HBN_Get_Hand_Off_Config,
-    ROM_API_INDEX_HBN_Get_MM_Power_Config,
     ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode,
+    ROM_API_INDEX_HBN_Get_User_Boot_Config,
     ROM_API_INDEX_HBN_Enable,
     ROM_API_INDEX_HBN_Mode_Enter,
     ROM_API_INDEX_HBN_Power_Down_Flash,
@@ -408,30 +368,21 @@ typedef enum {
     ROM_API_INDEX_L1C_ICache_Invalid_By_Addr,
     ROM_API_INDEX_L1C_Set_Cache_Setting_By_ID,
     ROM_API_INDEX_L1C_Set_Wrap,
-    ROM_API_INDEX_L1C_Get_None_Cache_Addr,
-    ROM_API_INDEX_L1C_Is_DCache_Range,
     ROM_API_INDEX_L1C_DCache_Write_Set,
 
     ROM_API_INDEX_PDS_Default_Level_Config,
+    ROM_API_INDEX_PDS_Disable_GPIO_Keep,
     ROM_API_INDEX_PDS_Enable,
     ROM_API_INDEX_PDS_Force_Config,
     ROM_API_INDEX_PDS_IntClear,
     ROM_API_INDEX_PDS_IntMask,
-    ROM_API_INDEX_PDS_Power_On_MM_System,
     ROM_API_INDEX_PDS_RAM_Config,
-    ROM_API_INDEX_PDS_Reset_LP_RTC,
     ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None,
     ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast,
     ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr,
     ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask,
     ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode,
     ROM_API_INDEX_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie,
-    ROM_API_INDEX_PDS_Set_LP_Clock_Disable,
-    ROM_API_INDEX_PDS_Set_LP_Clock_Enable,
-    ROM_API_INDEX_PDS_Set_LP_RTC_CLK,
-    ROM_API_INDEX_PDS_Set_LP_Reset_Address,
-    ROM_API_INDEX_PDS_Set_LP_System_CLK,
-    ROM_API_INDEX_PDS_Set_LP_System_CLK_Div,
     ROM_API_INDEX_PDS_Set_MCU0_Clock_Disable,
     ROM_API_INDEX_PDS_Set_MCU0_Clock_Enable,
     ROM_API_INDEX_PDS_Set_MCU0_Reset_Address,
@@ -442,17 +393,15 @@ typedef enum {
     ROM_API_INDEX_PDS_Turn_On_USB,
     ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus,
     ROM_API_INDEX_PDS_Get_IntStatus,
-    ROM_API_INDEX_PDS_Get_MM_System_Power_On_State,
 
     ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio,
     ROM_API_INDEX_SF_Cfg_Flash_Init,
     ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock,
-    ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext,
     ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Init_Flash2_Gpio,
     ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio,
     ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init,
     ROM_API_INDEX_SF_Cfg_Flash_Identify,
-    ROM_API_INDEX_SF_Cfg_Flash_Identify_Ext,
     ROM_API_INDEX_SF_Ctrl_GetBusyState,
     ROM_API_INDEX_SF_Ctrl_Is_AES_Enable,
     ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable,
@@ -533,7 +482,6 @@ typedef enum {
     ROM_API_INDEX_SFlash_SetBurstWrap,
     ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable,
 
-    ROM_API_INDEX_UART_ApplyAbrResult,
     ROM_API_INDEX_UART_AutoBaudDetection,
     ROM_API_INDEX_UART_ClrRtsValue,
     ROM_API_INDEX_UART_ClrTxValue,
@@ -550,7 +498,7 @@ typedef enum {
     ROM_API_INDEX_UART_SendData,
     ROM_API_INDEX_UART_SendDataBlock,
     ROM_API_INDEX_UART_SetAllowableError0X55,
-    ROM_API_INDEX_UART_SetBaudRate,
+    ROM_API_INDEX_UART_SetBaudrate,
     ROM_API_INDEX_UART_SetDeglitchCount,
     ROM_API_INDEX_UART_SetRS485,
     ROM_API_INDEX_UART_SetRtsValue,
@@ -583,6 +531,23 @@ typedef enum {
     ROM_API_INDEX_XIP_SFlash_Opt_Enter,
     ROM_API_INDEX_XIP_SFlash_Opt_Exit,
 
+    ROM_API_INDEX_MD_Clr_GPIO_IntStatus,
+    ROM_API_INDEX_MD_Embedded_Flash_Pad_Enable,
+    ROM_API_INDEX_MD_GPIO_Clr,
+    ROM_API_INDEX_MD_GPIO_Init,
+    ROM_API_INDEX_MD_GPIO_Input_Disable,
+    ROM_API_INDEX_MD_GPIO_Input_Enable,
+    ROM_API_INDEX_MD_GPIO_IntMask,
+    ROM_API_INDEX_MD_GPIO_Int_Init,
+    ROM_API_INDEX_MD_GPIO_Output_Disable,
+    ROM_API_INDEX_MD_GPIO_Output_Enable,
+    ROM_API_INDEX_MD_GPIO_Set,
+    ROM_API_INDEX_MD_GPIO_Set_HZ,
+    ROM_API_INDEX_MD_GPIO_Write,
+    ROM_API_INDEX_MD_Get_GPIO_IntStatus,
+    ROM_API_INDEX_MD_GPIO_Read,
+    ROM_API_INDEX_MD_GPIO_Get_Fun,
+
     ROM_API_INDEX_FUNC_EMPTY_START,
 
     ROM_API_INDEX_FUNC_EMPTY_END = ROMAPI_INDEX_MAX
@@ -602,15 +567,9 @@ typedef enum {
  */
 
 
-#define ROM_APITABLE            ((uint32_t *)0x90014800)
+#define ROM_APITABLE            ((uint32_t *)0x90015800)
 
 
-#define RomDriver_AON_LowPower_Enter_PDS0                 \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Enter_PDS0])
-
-#define RomDriver_AON_LowPower_Exit_PDS0                  \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_LowPower_Exit_PDS0])
-
 #define RomDriver_AON_Power_Off_BG                        \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_BG])
 
@@ -641,32 +600,77 @@ typedef enum {
 #define RomDriver_AON_Power_On_XTAL                       \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL])
 
-#define RomDriver_AON_Set_DCDC11_Top_Vout                 \
-    ((BL_Err_Type (*) (AON_DCDC_LEVEL_Type dcdcLevel))ROM_APITABLE[ROM_API_INDEX_AON_Set_DCDC11_Top_Vout])
-
 #define RomDriver_AON_Set_Xtal_CapCode                    \
     ((BL_Err_Type (*) (uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode])
 
-#define RomDriver_AON_Trim_DCDC11_Vout                    \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_DCDC11_Vout])
+#define RomDriver_AON_Trim_DcdcDis                        \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_DcdcDis])
 
-#define RomDriver_AON_Trim_DCDC18_Vout                    \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_DCDC18_Vout])
+#define RomDriver_AON_Trim_DcdcVoutSel                    \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_DcdcVoutSel])
 
-#define RomDriver_AON_Trim_USB20_RCAL                     \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_USB20_RCAL])
+#define RomDriver_AON_Trim_DcdcVoutTrim                   \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_DcdcVoutTrim])
+
+#define RomDriver_AON_Trim_Ldo11socVoutTrim               \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_Ldo11socVoutTrim])
+
+#define RomDriver_AON_Trim_Usb20RcalCode                  \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Trim_Usb20RcalCode])
 
 #define RomDriver_AON_Get_Xtal_CapCode                    \
     ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_AON_Get_Xtal_CapCode])
 
-#define RomDriver_ASM_Delay_Us                            \
-    ((void (*) (uint32_t core, uint32_t cnt, uint32_t loopT))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us])
+#define RomDriver_CPU_MTimer_Delay_MS                     \
+    ((BL_Err_Type (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_CPU_MTimer_Delay_MS])
 
-#define RomDriver_arch_delay_ms                           \
-    ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_arch_delay_ms])
+#define RomDriver_CPU_MTimer_Delay_US                     \
+    ((BL_Err_Type (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_CPU_MTimer_Delay_US])
 
-#define RomDriver_arch_delay_us                           \
-    ((void (*) (uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_arch_delay_us])
+#define RomDriver_CPU_Reset_MTimer                        \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Reset_MTimer])
+
+#define RomDriver_CPU_Set_MTimer_CLK                      \
+    ((BL_Err_Type (*) (uint8_t enable, BL_MTimer_Source_Clock_Type mTimerSourceClockType, uint16_t div))ROM_APITABLE[ROM_API_INDEX_CPU_Set_MTimer_CLK])
+
+#define RomDriver_CPU_Set_MTimer_RST                      \
+    ((BL_Err_Type (*) (uint8_t rstEn))ROM_APITABLE[ROM_API_INDEX_CPU_Set_MTimer_RST])
+
+#define RomDriver_CPU_Get_MTimer_Clock                    \
+    ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_Clock])
+
+#define RomDriver_CPU_Get_MTimer_Source_Clock             \
+    ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_Source_Clock])
+
+#define RomDriver_Clock_Audio_ADC_Clock_Get               \
+    ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_Clock_Audio_ADC_Clock_Get])
+
+#define RomDriver_Clock_Get_ISP_Clk                       \
+    ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_Clock_Get_ISP_Clk])
+
+#define RomDriver_Clock_Get_PSRAMB_Clk                    \
+    ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_Clock_Get_PSRAMB_Clk])
+
+#define RomDriver_Clock_Peripheral_Clock_Get              \
+    ((uint32_t (*) (BL_Peripheral_Type type))ROM_APITABLE[ROM_API_INDEX_Clock_Peripheral_Clock_Get])
+
+#define RomDriver_Clock_System_Clock_Get                  \
+    ((uint32_t (*) (BL_System_Clock_Type type))ROM_APITABLE[ROM_API_INDEX_Clock_System_Clock_Get])
+
+#define RomDriver_SystemCoreClockGet                      \
+    ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SystemCoreClockGet])
+
+#define RomDriver_CPU_Get_CPU_Cycle                       \
+    ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_CPU_Cycle])
+
+#define RomDriver_CPU_Get_MTimer_Counter                  \
+    ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_Counter])
+
+#define RomDriver_CPU_Get_MTimer_MS                       \
+    ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_MS])
+
+#define RomDriver_CPU_Get_MTimer_US                       \
+    ((uint64_t (*) (void))ROM_APITABLE[ROM_API_INDEX_CPU_Get_MTimer_US])
 
 #define RomDriver_EF_Ctrl_Crc_Result                      \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Result])
@@ -698,8 +702,11 @@ typedef enum {
 #define RomDriver_EF_Ctrl_Is_All_Bits_Zero                \
     ((uint8_t (*) (uint32_t val, uint8_t start, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero])
 
+#define RomDriver_EF_Ctrl_Read_FlashDlyCoe                \
+    ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_FlashDlyCoe])
+
 #define RomDriver_EF_Ctrl_Clear                           \
-    ((void (*) (uint8_t region, uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])
+    ((void (*) (uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])
 
 #define RomDriver_EF_Ctrl_Crc_Enable                      \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Crc_Enable])
@@ -710,56 +717,50 @@ typedef enum {
 #define RomDriver_EF_Ctrl_Load_Efuse_R0                   \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0])
 
-#define RomDriver_EF_Ctrl_Load_Efuse_R1                   \
-    ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R1])
-
-#define RomDriver_EF_Ctrl_Program_Direct                  \
-    ((void (*) (uint32_t region, uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Direct])
-
 #define RomDriver_EF_Ctrl_Program_Direct_R0               \
     ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Direct_R0])
 
-#define RomDriver_EF_Ctrl_Program_Direct_R1               \
-    ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Direct_R1])
-
 #define RomDriver_EF_Ctrl_Program_Efuse_0                 \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_0])
 
-#define RomDriver_EF_Ctrl_Program_Efuse_1                 \
-    ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Program_Efuse_1])
-
 #define RomDriver_EF_Ctrl_Read_ADC_Gain_Trim              \
     ((void (*) (Efuse_ADC_Gain_Coeff_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_ADC_Gain_Trim])
 
 #define RomDriver_EF_Ctrl_Read_AES_Key                    \
     ((void (*) (uint8_t index, uint32_t *keyData, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_AES_Key])
 
-#define RomDriver_EF_Ctrl_Read_DCDC11_Trim                \
-    ((void (*) (Efuse_Ana_DCDC11_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_DCDC11_Trim])
-
-#define RomDriver_EF_Ctrl_Read_DCDC18_Trim                \
-    ((void (*) (Efuse_Ana_DCDC18_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_DCDC18_Trim])
-
 #define RomDriver_EF_Ctrl_Read_Dbg_Pwd                    \
     ((void (*) (uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd])
 
+#define RomDriver_EF_Ctrl_Read_DcdcDis_Trim               \
+    ((void (*) (Efuse_Ana_DcdcDis_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_DcdcDis_Trim])
+
+#define RomDriver_EF_Ctrl_Read_DcdcVoutSel_Trim           \
+    ((void (*) (Efuse_Ana_DcdcVoutSel_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_DcdcVoutSel_Trim])
+
+#define RomDriver_EF_Ctrl_Read_DcdcVoutTrim_Trim          \
+    ((void (*) (Efuse_Ana_DcdcVoutTrim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_DcdcVoutTrim_Trim])
+
 #define RomDriver_EF_Ctrl_Read_Device_Info                \
     ((void (*) (Efuse_Device_Info_Type *deviceInfo))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Device_Info])
 
-#define RomDriver_EF_Ctrl_Read_Direct                     \
-    ((void (*) (uint32_t region, uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Direct])
-
 #define RomDriver_EF_Ctrl_Read_Direct_R0                  \
     ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Direct_R0])
 
-#define RomDriver_EF_Ctrl_Read_Direct_R1                  \
-    ((void (*) (uint32_t index, uint32_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Direct_R1])
+#define RomDriver_EF_Ctrl_Read_Ldo11socVoutTrim_Trim      \
+    ((void (*) (Efuse_Ana_Ldo11socVoutTrim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Ldo11socVoutTrim_Trim])
 
-#define RomDriver_EF_Ctrl_Read_LDO18FLASH_Trim            \
-    ((void (*) (Efuse_Ana_LDO18FLASH_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_LDO18FLASH_Trim])
+#define RomDriver_EF_Ctrl_Read_Ldo18ioBypass_Trim         \
+    ((void (*) (Efuse_Ana_Ldo18ioBypass_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioBypass_Trim])
 
-#define RomDriver_EF_Ctrl_Read_LDO18IO_Vout_Trim          \
-    ((void (*) (Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_LDO18IO_Vout_Trim])
+#define RomDriver_EF_Ctrl_Read_Ldo18ioVoutSel_Trim        \
+    ((void (*) (Efuse_Ana_Ldo18ioVoutSel_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioVoutSel_Trim])
+
+#define RomDriver_EF_Ctrl_Read_Ldo18ioVoutTrim_Trim       \
+    ((void (*) (Efuse_Ana_Ldo18ioVoutTrim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioVoutTrim_Trim])
+
+#define RomDriver_EF_Ctrl_Read_Ldo33VoutTrim_Trim         \
+    ((void (*) (Efuse_Ana_Ldo33VoutTrim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Ldo33VoutTrim_Trim])
 
 #define RomDriver_EF_Ctrl_Read_RC32K_Trim                 \
     ((void (*) (Efuse_Ana_RC32K_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim])
@@ -779,11 +780,8 @@ typedef enum {
 #define RomDriver_EF_Ctrl_Read_TSEN_Trim                  \
     ((void (*) (Efuse_TSEN_Refcode_Corner_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_TSEN_Trim])
 
-#define RomDriver_EF_Ctrl_Read_USB20RCAL_Trim             \
-    ((void (*) (Efuse_Ana_USB20RCAL_Trim_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_USB20RCAL_Trim])
-
-#define RomDriver_EF_Ctrl_Read_Xtal_Trim_RC32M            \
-    ((void (*) (uint8_t *forceNoTrim, uint8_t *noXtal))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Xtal_Trim_RC32M])
+#define RomDriver_EF_Ctrl_Read_Usb20RcalCode_Trim         \
+    ((void (*) (Efuse_Ana_Usb20RcalCode_Type *trim))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_Usb20RcalCode_Trim])
 
 #define RomDriver_EF_Ctrl_Readlock_AES_Key                \
     ((void (*) (uint8_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key])
@@ -797,9 +795,6 @@ typedef enum {
 #define RomDriver_EF_Ctrl_Sw_AHB_Clk_0                    \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0])
 
-#define RomDriver_EF_Ctrl_Sw_AHB_Clk_1                    \
-    ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_1])
-
 #define RomDriver_EF_Ctrl_Write_AES_Key                   \
     ((void (*) (uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Write_AES_Key])
 
@@ -830,12 +825,12 @@ typedef enum {
 #define RomDriver_EF_Ctrl_Writelock_Sw_Usage              \
     ((void (*) (uint32_t index, uint8_t program))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage])
 
-#define RomDriver_GLB_AHB_DSP_Software_Reset              \
-    ((BL_Err_Type (*) (GLB_AHB_DSP_SW_Type swrst))ROM_APITABLE[ROM_API_INDEX_GLB_AHB_DSP_Software_Reset])
-
 #define RomDriver_GLB_AHB_MCU_Software_Reset              \
     ((BL_Err_Type (*) (GLB_AHB_MCU_SW_Type swrst))ROM_APITABLE[ROM_API_INDEX_GLB_AHB_MCU_Software_Reset])
 
+#define RomDriver_GLB_AUPLL_Ref_Clk_Sel                   \
+    ((BL_Err_Type (*) (GLB_PLL_REF_CLK_Type refClk))ROM_APITABLE[ROM_API_INDEX_GLB_AUPLL_Ref_Clk_Sel])
+
 #define RomDriver_GLB_BMX_TO_Init                         \
     ((BL_Err_Type (*) (BMX_TO_Cfg_Type *BmxCfg))ROM_APITABLE[ROM_API_INDEX_GLB_BMX_TO_Init])
 
@@ -845,74 +840,26 @@ typedef enum {
 #define RomDriver_GLB_Clr_EMI_Reset_Gate                  \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Clr_EMI_Reset_Gate])
 
-#define RomDriver_GLB_Config_AUDIO_PLL                    \
-    ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_AUDIO_PLL])
+#define RomDriver_GLB_Clr_Reset_Reason                    \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Clr_Reset_Reason])
 
-#define RomDriver_GLB_Config_CPU_PLL                      \
-    ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_CPU_PLL])
+#define RomDriver_GLB_Config_SDIO_Host_Interrupt_CPU      \
+    ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Config_SDIO_Host_Interrupt_CPU])
 
-#define RomDriver_GLB_Config_MIPI_PLL                     \
-    ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_MIPI_PLL])
+#define RomDriver_GLB_Config_SDIO_Host_Reset_SDU          \
+    ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Config_SDIO_Host_Reset_SDU])
 
-#define RomDriver_GLB_Config_MIPI_PLL_Div                 \
-    ((BL_Err_Type (*) (uint8_t divEn, uint8_t divRatio))ROM_APITABLE[ROM_API_INDEX_GLB_Config_MIPI_PLL_Div])
-
-#define RomDriver_GLB_Config_UHS_PLL                      \
-    ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_UHS_PLL])
-
-#define RomDriver_GLB_Config_WIFI_PLL                     \
-    ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList))ROM_APITABLE[ROM_API_INDEX_GLB_Config_WIFI_PLL])
-
-#define RomDriver_GLB_DSP0_Clock_Disable                  \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_DSP0_Clock_Disable])
-
-#define RomDriver_GLB_DSP0_Clock_Enable                   \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_DSP0_Clock_Enable])
-
-#define RomDriver_GLB_DSP_Clr_MCU_IntStatus               \
-    ((BL_Err_Type (*) (GLB_MCU_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Clr_MCU_IntStatus])
-
-#define RomDriver_GLB_DSP_Codec_Sub_Reset                 \
-    ((BL_Err_Type (*) (GLB_DSP_CODEC_SUB_Type codecPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Codec_Sub_Reset])
-
-#define RomDriver_GLB_DSP_DSP2_Sub_Reset                   \
-    ((BL_Err_Type (*) (GLB_DSP_DSP2_SUB_Type dsp2Part))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_DSP2_Sub_Reset])
-
-#define RomDriver_GLB_DSP_Image_Sensor_Reset              \
-    ((BL_Err_Type (*) (GLB_DSP_IMAGE_SENSOR_Type imageSensorPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Image_Sensor_Reset])
-
-#define RomDriver_GLB_DSP_Peripheral_Reset                \
-    ((BL_Err_Type (*) (GLB_DSP_PERIPHERAL_Type periPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Peripheral_Reset])
-
-#define RomDriver_GLB_DSP_SW_System_Reset                 \
-    ((BL_Err_Type (*) (GLB_DSP_SW_SYSTEM_Type sysPart))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_SW_System_Reset])
-
-#define RomDriver_GLB_DSP_Set_LP_IntEn                    \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_LP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Set_LP_IntEn])
-
-#define RomDriver_GLB_DSP_Set_MCU_IntMask                 \
-    ((BL_Err_Type (*) (GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Set_MCU_IntMask])
+#define RomDriver_GLB_Config_SDIO_Host_Reset_System       \
+    ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Config_SDIO_Host_Reset_System])
 
 #define RomDriver_GLB_Get_Auto_Calc_Xtal_Type             \
     ((BL_Err_Type (*) (GLB_XTAL_Type *calcXtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Auto_Calc_Xtal_Type])
 
-#define RomDriver_GLB_Get_DSP_PBCLK_Div                   \
-    ((BL_Err_Type (*) (uint8_t *dspPBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_PBCLK_Div])
-
-#define RomDriver_GLB_Get_DSP_System_CLK_Div              \
-    ((BL_Err_Type (*) (uint8_t *dspClkDiv, uint8_t *dspBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_System_CLK_Div])
-
 #define RomDriver_GLB_Get_MCU_System_CLK_Div              \
-    ((BL_Err_Type (*) (uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Get_MCU_System_CLK_Div])
+    ((BL_Err_Type (*) (uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Get_MCU_System_CLK_Div])
 
-#define RomDriver_GLB_Halt_CPU                            \
-    ((BL_Err_Type (*) (GLB_CORE_ID_Type coreID))ROM_APITABLE[ROM_API_INDEX_GLB_Halt_CPU])
-
-#define RomDriver_GLB_IR_LED_Driver_Disable               \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Disable])
-
-#define RomDriver_GLB_IR_LED_Driver_Enable                \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_IR_LED_Driver_Enable])
+#define RomDriver_GLB_Get_Reset_Reason                    \
+    ((BL_Err_Type (*) (GLB_RESET_RECORD_Type *reason))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Reset_Reason])
 
 #define RomDriver_GLB_IR_RX_GPIO_Sel                      \
     ((BL_Err_Type (*) (GLB_GPIO_Type gpio))ROM_APITABLE[ROM_API_INDEX_GLB_IR_RX_GPIO_Sel])
@@ -926,18 +873,9 @@ typedef enum {
 #define RomDriver_GLB_Invert_ETH_TX_CLK                   \
     ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Invert_ETH_TX_CLK])
 
-#define RomDriver_GLB_MCU_Clr_DSP_IntStatus               \
-    ((BL_Err_Type (*) (GLB_DSP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_Clr_DSP_IntStatus])
-
 #define RomDriver_GLB_MCU_SW_System_Reset                 \
     ((BL_Err_Type (*) (GLB_MCU_SW_SYSTEM_Type sysPart))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_SW_System_Reset])
 
-#define RomDriver_GLB_MCU_Set_DSP_IntMask                 \
-    ((BL_Err_Type (*) (GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_Set_DSP_IntMask])
-
-#define RomDriver_GLB_Output_EMAC_CLK                     \
-    ((BL_Err_Type (*) (uint8_t gpio))ROM_APITABLE[ROM_API_INDEX_GLB_Output_EMAC_CLK])
-
 #define RomDriver_GLB_PER_Clock_Gate                      \
     ((BL_Err_Type (*) (uint64_t ips))ROM_APITABLE[ROM_API_INDEX_GLB_PER_Clock_Gate])
 
@@ -953,23 +891,23 @@ typedef enum {
 #define RomDriver_GLB_Platform_Wakeup_PDS_Enable          \
     ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Platform_Wakeup_PDS_Enable])
 
-#define RomDriver_GLB_Power_Off_MU_PLL                    \
-    ((BL_Err_Type (*) (GLB_MU_PLL_Type pllType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_MU_PLL])
+#define RomDriver_GLB_Power_Off_AUPLL                     \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_AUPLL])
 
-#define RomDriver_GLB_Power_Off_WAC_PLL                   \
-    ((BL_Err_Type (*) (GLB_WAC_PLL_Type pllType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_WAC_PLL])
+#define RomDriver_GLB_Power_Off_WIFIPLL                   \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_WIFIPLL])
 
-#define RomDriver_GLB_Power_On_MU_PLL                     \
-    ((BL_Err_Type (*) (GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_MU_PLL])
+#define RomDriver_GLB_Power_On_AUPLL                      \
+    ((BL_Err_Type (*) (const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_AUPLL])
 
-#define RomDriver_GLB_Power_On_WAC_PLL                    \
-    ((BL_Err_Type (*) (GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_WAC_PLL])
+#define RomDriver_GLB_Power_On_WIFIPLL                    \
+    ((BL_Err_Type (*) (const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_WIFIPLL])
 
 #define RomDriver_GLB_Power_On_XTAL_And_PLL_CLK           \
     ((BL_Err_Type (*) (GLB_XTAL_Type xtalType, GLB_PLL_Type pllType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_XTAL_And_PLL_CLK])
 
-#define RomDriver_GLB_Release_CPU                         \
-    ((BL_Err_Type (*) (GLB_CORE_ID_Type coreID))ROM_APITABLE[ROM_API_INDEX_GLB_Release_CPU])
+#define RomDriver_GLB_SPI_Sig_Swap_Set                    \
+    ((BL_Err_Type (*) (GLB_SPI_SIG_SWAP_GRP_Type group, uint8_t swap))ROM_APITABLE[ROM_API_INDEX_GLB_SPI_Sig_Swap_Set])
 
 #define RomDriver_GLB_SW_CPU_Reset                        \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset])
@@ -980,9 +918,6 @@ typedef enum {
 #define RomDriver_GLB_SW_System_Reset                     \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset])
 
-#define RomDriver_GLB_Sel_DSP_TMR_GPIO_Clock              \
-    ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Sel_DSP_TMR_GPIO_Clock])
-
 #define RomDriver_GLB_Sel_MCU_TMR_GPIO_Clock              \
     ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Sel_MCU_TMR_GPIO_Clock])
 
@@ -995,11 +930,8 @@ typedef enum {
 #define RomDriver_GLB_Set_Audio_AUTO_CLK                  \
     ((BL_Err_Type (*) (uint8_t divEn))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_AUTO_CLK])
 
-#define RomDriver_GLB_Set_Audio_DAC_CLK                   \
-    ((BL_Err_Type (*) (uint8_t enable, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_DAC_CLK])
-
-#define RomDriver_GLB_Set_Audio_PDM_CLK                   \
-    ((BL_Err_Type (*) (uint8_t enable, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_PDM_CLK])
+#define RomDriver_GLB_Set_Audio_SOLO_CLK                  \
+    ((BL_Err_Type (*) (uint8_t enable, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Audio_SOLO_CLK])
 
 #define RomDriver_GLB_Set_Auto_Calc_Xtal_Type             \
     ((BL_Err_Type (*) (GLB_XTAL_Type calcXtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Auto_Calc_Xtal_Type])
@@ -1010,20 +942,11 @@ typedef enum {
 #define RomDriver_GLB_Set_CPU_Reset_Address               \
     ((BL_Err_Type (*) (GLB_CORE_ID_Type coreID, uint32_t addr))ROM_APITABLE[ROM_API_INDEX_GLB_Set_CPU_Reset_Address])
 
-#define RomDriver_GLB_Set_CSI_DSI_CLK_Sel                 \
-    ((BL_Err_Type (*) (GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_CSI_DSI_CLK_Sel])
+#define RomDriver_GLB_Set_Chip_Clock_Out_Sel              \
+    ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out_Sel])
 
-#define RomDriver_GLB_Set_Chip_Clock_Out0_Sel             \
-    ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_0_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out0_Sel])
-
-#define RomDriver_GLB_Set_Chip_Clock_Out1_Sel             \
-    ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_1_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out1_Sel])
-
-#define RomDriver_GLB_Set_Chip_Clock_Out2_Sel             \
-    ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_2_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out2_Sel])
-
-#define RomDriver_GLB_Set_Chip_Clock_Out3_Sel             \
-    ((BL_Err_Type (*) (GLB_CHIP_CLK_OUT_3_Type clkOutType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Chip_Clock_Out3_Sel])
+#define RomDriver_GLB_Set_DBI_CLK                         \
+    ((BL_Err_Type (*) (uint8_t enable, GLB_DBI_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DBI_CLK])
 
 #define RomDriver_GLB_Set_DIG_32K_CLK                     \
     ((BL_Err_Type (*) (uint8_t enable, uint8_t compensationEn, uint16_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DIG_32K_CLK])
@@ -1037,95 +960,14 @@ typedef enum {
 #define RomDriver_GLB_Set_DMA_CLK                         \
     ((BL_Err_Type (*) (uint8_t enable, GLB_DMA_CLK_ID_Type clk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DMA_CLK])
 
-#define RomDriver_GLB_Set_DSP_CNN_CLK                     \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_CNN_CLK])
-
-#define RomDriver_GLB_Set_DSP_DP_CLK                      \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_DP_CLK])
-
-#define RomDriver_GLB_Set_DSP_H264_CLK                    \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_H264_CLK])
-
-#define RomDriver_GLB_Set_DSP_I2C0_CLK                    \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_I2C0_CLK])
-
-#define RomDriver_GLB_Set_DSP_I2C1_CLK                    \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_I2C1_CLK])
-
-#define RomDriver_GLB_Set_DSP_DSP2_CLK                     \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_DSP2_CLK])
-
-#define RomDriver_GLB_Set_DSP_L2SRAM_Available_Size       \
-    ((BL_Err_Type (*) (uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_L2SRAM_Available_Size])
-
-#define RomDriver_GLB_Set_DSP_MTimer_CLK                  \
-    ((BL_Err_Type (*) (uint8_t enable, uint16_t div, uint8_t rst))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_MTimer_CLK])
-
-#define RomDriver_GLB_Set_DSP_MUXPLL_CLK_Sel              \
-    ((BL_Err_Type (*) (GLB_DSP_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_MUXPLL_CLK_Sel])
-
-#define RomDriver_GLB_Set_DSP_Muxpll_160M_Sel             \
-    ((BL_Err_Type (*) (GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_Muxpll_160M_Sel])
-
-#define RomDriver_GLB_Set_DSP_Muxpll_240M_Sel             \
-    ((BL_Err_Type (*) (GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_Muxpll_240M_Sel])
-
-#define RomDriver_GLB_Set_DSP_Muxpll_320M_Sel             \
-    ((BL_Err_Type (*) (GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_Muxpll_320M_Sel])
-
-#define RomDriver_GLB_Set_DSP_PBCLK                       \
-    ((BL_Err_Type (*) (GLB_DSP_SYS_PBCLK_Type pbClkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_PBCLK])
-
-#define RomDriver_GLB_Set_DSP_PBCLK_Div                   \
-    ((BL_Err_Type (*) (uint8_t dspPBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_PBCLK_Div])
-
-#define RomDriver_GLB_Set_DSP_PBROOT_CLK_Sel              \
-    ((BL_Err_Type (*) (GLB_DSP_PBROOT_CLK_Type pbrootClk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_PBROOT_CLK_Sel])
-
-#define RomDriver_GLB_Set_DSP_ROOT_CLK_Sel                \
-    ((BL_Err_Type (*) (GLB_DSP_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_ROOT_CLK_Sel])
-
-#define RomDriver_GLB_Set_DSP_SPI_0_ACT_MOD_Sel           \
-    ((BL_Err_Type (*) (GLB_SPI_PAD_ACT_AS_Type mod))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_SPI_0_ACT_MOD_Sel])
-
-#define RomDriver_GLB_Set_DSP_SPI_CLK                     \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_SPI_CLK])
-
-#define RomDriver_GLB_Set_DSP_System_CLK                  \
-    ((BL_Err_Type (*) (GLB_DSP_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_System_CLK])
-
-#define RomDriver_GLB_Set_DSP_System_CLK_Div              \
-    ((BL_Err_Type (*) (uint8_t dspClkDiv, uint8_t dspBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_System_CLK_Div])
-
-#define RomDriver_GLB_Set_DSP_UART0_CLK                   \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_UART0_CLK])
-
-#define RomDriver_GLB_Set_DSP_UART1_CLK                   \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_UART1_CLK])
-
-#define RomDriver_GLB_Set_DSP_XCLK_Sel                    \
-    ((BL_Err_Type (*) (GLB_DSP_XCLK_Type xclk))ROM_APITABLE[ROM_API_INDEX_GLB_Set_DSP_XCLK_Sel])
-
-#define RomDriver_GLB_Set_Display_CLK                     \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Display_CLK])
-
-#define RomDriver_GLB_Set_EMAC_CLK                        \
-    ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_EMAC_CLK])
-
-#define RomDriver_GLB_Set_EMI_CLK                         \
-    ((BL_Err_Type (*) (uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_EMI_CLK])
-
 #define RomDriver_GLB_Set_EM_Sel                          \
     ((BL_Err_Type (*) (GLB_EM_Type emType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_EM_Sel])
 
 #define RomDriver_GLB_Set_ETH_REF_O_CLK_Sel               \
     ((BL_Err_Type (*) (GLB_ETH_REF_CLK_OUT_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel])
 
-#define RomDriver_GLB_Set_Flash_IO_PARM                   \
-    ((BL_Err_Type (*) (uint8_t selEmbedded, uint8_t swap))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Flash_IO_PARM])
-
-#define RomDriver_GLB_Set_Flash_Id_Value                  \
-    ((BL_Err_Type (*) (uint32_t idValue))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Flash_Id_Value])
+#define RomDriver_GLB_Set_PEC_CLK                         \
+    ((BL_Err_Type (*) (uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PEC_CLK])
 
 #define RomDriver_GLB_Set_I2C_CLK                         \
     ((BL_Err_Type (*) (uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_I2C_CLK])
@@ -1136,8 +978,8 @@ typedef enum {
 #define RomDriver_GLB_Set_IR_CLK                          \
     ((BL_Err_Type (*) (uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_IR_CLK])
 
-#define RomDriver_GLB_Set_MCU_MTimer_CLK                  \
-    ((BL_Err_Type (*) (uint8_t enable, uint16_t div, uint8_t rst))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_MTimer_CLK])
+#define RomDriver_GLB_Set_ISP_Muxpll_80M_Sel              \
+    ((BL_Err_Type (*) (GLB_ISP_MUXPLL_80M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_ISP_Muxpll_80M_Sel])
 
 #define RomDriver_GLB_Set_MCU_Muxpll_160M_Sel             \
     ((BL_Err_Type (*) (GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_Muxpll_160M_Sel])
@@ -1152,10 +994,7 @@ typedef enum {
     ((BL_Err_Type (*) (GLB_MCU_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_System_CLK])
 
 #define RomDriver_GLB_Set_MCU_System_CLK_Div              \
-    ((BL_Err_Type (*) (uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_System_CLK_Div])
-
-#define RomDriver_GLB_Set_PADC_CLK                        \
-    ((BL_Err_Type (*) (uint8_t enable, uint16_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PADC_CLK])
+    ((BL_Err_Type (*) (uint8_t mcuClkDiv, uint8_t mcuPBclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_MCU_System_CLK_Div])
 
 #define RomDriver_GLB_Set_PDM_IO_Sel                      \
     ((BL_Err_Type (*) (GLB_PDM_IO_SEL_Type ioSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PDM_IO_Sel])
@@ -1163,15 +1002,12 @@ typedef enum {
 #define RomDriver_GLB_Set_PKA_CLK_Sel                     \
     ((BL_Err_Type (*) (GLB_PKA_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PKA_CLK_Sel])
 
-#define RomDriver_GLB_Set_PSram_CLK                       \
-    ((BL_Err_Type (*) (uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PSram_CLK])
+#define RomDriver_GLB_Set_PSRAMB_CLK_Sel                  \
+    ((BL_Err_Type (*) (uint8_t enable, GLB_PSRAMB_PLL_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PSRAMB_CLK_Sel])
 
 #define RomDriver_GLB_Set_PWM1_IO_Sel                     \
     ((BL_Err_Type (*) (GLB_PWM1_IO_SEL_Type ioSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PWM1_IO_Sel])
 
-#define RomDriver_GLB_Set_PWM2_IO_Sel                     \
-    ((BL_Err_Type (*) (GLB_PWM2_IO_SEL_Type ioSel))ROM_APITABLE[ROM_API_INDEX_GLB_Set_PWM2_IO_Sel])
-
 #define RomDriver_GLB_Set_Peripheral_DMA_CN               \
     ((BL_Err_Type (*) (GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Peripheral_DMA_CN])
 
@@ -1181,6 +1017,12 @@ typedef enum {
 #define RomDriver_GLB_Set_SF_CLK                          \
     ((BL_Err_Type (*) (uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK])
 
+#define RomDriver_GLB_Set_SFlash2_IO_PARM                 \
+    ((BL_Err_Type (*) (uint8_t swapIo3Io0))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SFlash2_IO_PARM])
+
+#define RomDriver_GLB_Set_SFlash_IO_PARM                  \
+    ((BL_Err_Type (*) (uint8_t selEmbedded, uint8_t swapIo3Io0, uint8_t swapIo2Cs))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SFlash_IO_PARM])
+
 #define RomDriver_GLB_Set_SPI_CLK                         \
     ((BL_Err_Type (*) (uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SPI_CLK])
 
@@ -1193,8 +1035,11 @@ typedef enum {
 #define RomDriver_GLB_Set_SRAM_SLP                        \
     ((BL_Err_Type (*) (uint32_t value))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SRAM_SLP])
 
-#define RomDriver_GLB_Set_UART2_IO_Sel                    \
-    ((BL_Err_Type (*) (GLB_UART2_IO_SEL_Type ioType))ROM_APITABLE[ROM_API_INDEX_GLB_Set_UART2_IO_Sel])
+#define RomDriver_GLB_Set_SSC_CLK_From_WIFIPLL            \
+    ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SSC_CLK_From_WIFIPLL])
+
+#define RomDriver_GLB_Set_Slave_Grp_0_CLK                 \
+    ((BL_Err_Type (*) (GLB_SLAVE_GRP_0_Type slave, uint8_t enable, GLB_SLAVE_GRP_0_CLK_SEL_Type clkSel, uint32_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_Slave_Grp_0_CLK])
 
 #define RomDriver_GLB_Set_UART_CLK                        \
     ((BL_Err_Type (*) (uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_UART_CLK])
@@ -1202,17 +1047,17 @@ typedef enum {
 #define RomDriver_GLB_Set_USB_CLK_From_WIFIPLL            \
     ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_GLB_Set_USB_CLK_From_WIFIPLL])
 
-#define RomDriver_GLB_Swap_DSP_SPI_0_MOSI_With_MISO       \
-    ((BL_Err_Type (*) (BL_Fun_Type newState))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_DSP_SPI_0_MOSI_With_MISO])
-
 #define RomDriver_GLB_Swap_MCU_SPI_0_MOSI_With_MISO       \
     ((BL_Err_Type (*) (BL_Fun_Type newState))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_MCU_SPI_0_MOSI_With_MISO])
 
-#define RomDriver_GLB_Trim_LDO18FLASH_Vout                \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_LDO18FLASH_Vout])
+#define RomDriver_GLB_Trim_Ldo18ioBypass                  \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_Ldo18ioBypass])
 
-#define RomDriver_GLB_Trim_LDO18IO_Vout                   \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_LDO18IO_Vout])
+#define RomDriver_GLB_Trim_Ldo18ioVoutSel                 \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_Ldo18ioVoutSel])
+
+#define RomDriver_GLB_Trim_Ldo18ioVoutTrim                \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Trim_Ldo18ioVoutTrim])
 
 #define RomDriver_GLB_UART_Fun_Sel                        \
     ((BL_Err_Type (*) (GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun))ROM_APITABLE[ROM_API_INDEX_GLB_UART_Fun_Sel])
@@ -1220,45 +1065,18 @@ typedef enum {
 #define RomDriver_GLB_UART_Sig_Swap_Set                   \
     ((BL_Err_Type (*) (GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap))ROM_APITABLE[ROM_API_INDEX_GLB_UART_Sig_Swap_Set])
 
-#define RomDriver_GLB_DSP_Get_LP_IntStatus                \
-    ((BL_Sts_Type (*) (GLB_LP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Get_LP_IntStatus])
-
-#define RomDriver_GLB_DSP_Get_MCU_IntStatus               \
-    ((BL_Sts_Type (*) (GLB_MCU_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_DSP_Get_MCU_IntStatus])
-
-#define RomDriver_GLB_MCU_Get_DSP_IntStatus               \
-    ((BL_Sts_Type (*) (GLB_DSP_ALL_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_GLB_MCU_Get_DSP_IntStatus])
+#define RomDriver_GLB_WIFIPLL_Ref_Clk_Sel                 \
+    ((BL_Err_Type (*) (GLB_PLL_REF_CLK_Type refClk))ROM_APITABLE[ROM_API_INDEX_GLB_WIFIPLL_Ref_Clk_Sel])
 
 #define RomDriver_GLB_Get_Core_Type                       \
     ((GLB_CORE_ID_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Core_Type])
 
-#define RomDriver_GLB_Get_DSP_Muxpll_160M_Sel             \
-    ((GLB_DSP_MUXPLL_160M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_Muxpll_160M_Sel])
-
-#define RomDriver_GLB_Get_DSP_Muxpll_240M_Sel             \
-    ((GLB_DSP_MUXPLL_240M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_Muxpll_240M_Sel])
-
-#define RomDriver_GLB_Get_DSP_Muxpll_320M_Sel             \
-    ((GLB_DSP_MUXPLL_320M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_Muxpll_320M_Sel])
-
-#define RomDriver_GLB_Get_DSP_PBROOT_CLK_Sel              \
-    ((GLB_DSP_PBROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_PBROOT_CLK_Sel])
-
-#define RomDriver_GLB_Get_DSP_ROOT_CLK_Sel                \
-    ((GLB_DSP_ROOT_CLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_ROOT_CLK_Sel])
-
-#define RomDriver_GLB_Get_DSP_XCLK_Sel                    \
-    ((GLB_DSP_XCLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_DSP_XCLK_Sel])
-
 #define RomDriver_GLB_Get_MCU_Muxpll_160M_Sel             \
     ((GLB_MCU_MUXPLL_160M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_MCU_Muxpll_160M_Sel])
 
 #define RomDriver_GLB_Get_MCU_Muxpll_80M_Sel              \
     ((GLB_MCU_MUXPLL_80M_CLK_SEL_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_MCU_Muxpll_80M_Sel])
 
-#define RomDriver_GLB_Get_Flash_Id_Value                  \
-    ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Flash_Id_Value])
-
 #define RomDriver_GLB_Get_SRAM_PARM                       \
     ((uint32_t (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_SRAM_PARM])
 
@@ -1275,7 +1093,7 @@ typedef enum {
     ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_Clr_GPIO_IntStatus])
 
 #define RomDriver_GLB_Embedded_Flash_Pad_Enable           \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_GLB_Embedded_Flash_Pad_Enable])
+    ((BL_Err_Type (*) (uint8_t swapIo2Cs))ROM_APITABLE[ROM_API_INDEX_GLB_Embedded_Flash_Pad_Enable])
 
 #define RomDriver_GLB_GPIO_Clr                            \
     ((BL_Err_Type (*) (GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Clr])
@@ -1355,15 +1173,24 @@ typedef enum {
 #define RomDriver_HBN_Aon_Pad_Cfg                         \
     ((BL_Err_Type (*) (uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_Cfg])
 
+#define RomDriver_HBN_Aon_Pad_Cfg_Set                     \
+    ((BL_Err_Type (*) (uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_Cfg_Set])
+
 #define RomDriver_HBN_Aon_Pad_Ctrl                        \
     ((BL_Err_Type (*) (uint32_t aonPadCtl1, uint32_t aonPadCtl2))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_Ctrl])
 
 #define RomDriver_HBN_Aon_Pad_WakeUpCfg                   \
     ((BL_Err_Type (*) (BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec))ROM_APITABLE[ROM_API_INDEX_HBN_Aon_Pad_WakeUpCfg])
 
+#define RomDriver_HBN_Clear_Gpio_Keep                     \
+    ((BL_Err_Type (*) (uint8_t gpioKeep))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_Gpio_Keep])
+
 #define RomDriver_HBN_Clear_IRQ                           \
     ((BL_Err_Type (*) (HBN_INT_Type irqType))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_IRQ])
 
+#define RomDriver_HBN_Clear_PDS_Gpio_Keep                 \
+    ((BL_Err_Type (*) (uint8_t gpioKeep))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_PDS_Gpio_Keep])
+
 #define RomDriver_HBN_Clear_RTC_Counter                   \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Clear_RTC_Counter])
 
@@ -1397,8 +1224,17 @@ typedef enum {
 #define RomDriver_HBN_GPIO_INT_Enable                     \
     ((BL_Err_Type (*) (HBN_GPIO_INT_Trigger_Type gpioIntTrigType))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_INT_Enable])
 
-#define RomDriver_HBN_Get_RTC_Misc_Cfg                    \
-    ((BL_Err_Type (*) (HBN_RTC_MISC_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Get_RTC_Misc_Cfg])
+#define RomDriver_HBN_Get_Flash_Power_Delay               \
+    ((BL_Err_Type (*) (uint8_t *flashPwrDly))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Flash_Power_Delay])
+
+#define RomDriver_HBN_Get_Gpio_Keep                       \
+    ((BL_Err_Type (*) (uint8_t *gpioKeep))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Gpio_Keep])
+
+#define RomDriver_HBN_Get_Ldo18io_Power_Delay_Config      \
+    ((BL_Err_Type (*) (uint16_t *pwrOffDly, uint16_t *pwrOnDly))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Ldo18io_Power_Delay_Config])
+
+#define RomDriver_HBN_Get_PDS_Gpio_Keep                   \
+    ((BL_Err_Type (*) (uint8_t *gpioKeep))ROM_APITABLE[ROM_API_INDEX_HBN_Get_PDS_Gpio_Keep])
 
 #define RomDriver_HBN_Get_RTC_Timer_Val                   \
     ((BL_Err_Type (*) (uint32_t *valLow, uint32_t *valHigh))ROM_APITABLE[ROM_API_INDEX_HBN_Get_RTC_Timer_Val])
@@ -1409,11 +1245,8 @@ typedef enum {
 #define RomDriver_HBN_Hw_Pu_Pd_Cfg                        \
     ((BL_Err_Type (*) (uint8_t enable))ROM_APITABLE[ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg])
 
-#define RomDriver_HBN_PD_RC32K_All_State                  \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_PD_RC32K_All_State])
-
-#define RomDriver_HBN_PD_RC32K_In_Poff                    \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_PD_RC32K_In_Poff])
+#define RomDriver_HBN_Keep_On_RC32K                       \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Keep_On_RC32K])
 
 #define RomDriver_HBN_PIR_Disable                         \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_PIR_Disable])
@@ -1439,9 +1272,6 @@ typedef enum {
 #define RomDriver_HBN_Power_Off_Xtal_32K                  \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Off_Xtal_32K])
 
-#define RomDriver_HBN_Power_On_RC32K                      \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_RC32K])
-
 #define RomDriver_HBN_Power_On_Xtal_32K                   \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Power_On_Xtal_32K])
 
@@ -1457,18 +1287,21 @@ typedef enum {
 #define RomDriver_HBN_Set_Core_Reboot_Config              \
     ((BL_Err_Type (*) (uint8_t core, uint8_t hcfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Core_Reboot_Config])
 
+#define RomDriver_HBN_Set_Flash_Power_Delay               \
+    ((BL_Err_Type (*) (uint8_t flashPwrDly))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Flash_Power_Delay])
+
+#define RomDriver_HBN_Set_GPADC_CLK_Sel                   \
+    ((BL_Err_Type (*) (HBN_GPADC_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_GPADC_CLK_Sel])
+
+#define RomDriver_HBN_Set_Gpio_Keep                       \
+    ((BL_Err_Type (*) (uint8_t gpioKeep))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Gpio_Keep])
+
 #define RomDriver_HBN_Set_HRAM_Ret                        \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Set_HRAM_Ret])
 
 #define RomDriver_HBN_Set_HRAM_slp                        \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Set_HRAM_slp])
 
-#define RomDriver_HBN_Set_Hand_Off_Config                 \
-    ((BL_Err_Type (*) (uint8_t dcfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Hand_Off_Config])
-
-#define RomDriver_HBN_Set_IO4041_As_Xtal_32K_IO           \
-    ((BL_Err_Type (*) (uint8_t xtal32kIoEn))ROM_APITABLE[ROM_API_INDEX_HBN_Set_IO4041_As_Xtal_32K_IO])
-
 #define RomDriver_HBN_Set_Ldo11_All_Vout                  \
     ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_All_Vout])
 
@@ -1478,11 +1311,11 @@ typedef enum {
 #define RomDriver_HBN_Set_Ldo11_Rt_Vout                   \
     ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout])
 
-#define RomDriver_HBN_Set_Ldo11_Rtc_Vout                  \
-    ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Rtc_Vout])
+#define RomDriver_HBN_Set_Ldo11_Soc_Vout                  \
+    ((BL_Err_Type (*) (HBN_LDO_LEVEL_Type ldoLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout])
 
-#define RomDriver_HBN_Set_Ldo18flash_Repower_Delay        \
-    ((BL_Err_Type (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo18flash_Repower_Delay])
+#define RomDriver_HBN_Set_Ldo18io_Power_Delay_Config      \
+    ((BL_Err_Type (*) (uint16_t pwrOffDly, uint16_t pwrOnDly))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Ldo18io_Power_Delay_Config])
 
 #define RomDriver_HBN_Set_MCU_Root_CLK_Sel                \
     ((BL_Err_Type (*) (HBN_MCU_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_MCU_Root_CLK_Sel])
@@ -1490,8 +1323,8 @@ typedef enum {
 #define RomDriver_HBN_Set_MCU_XCLK_Sel                    \
     ((BL_Err_Type (*) (HBN_MCU_XCLK_Type xclk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_MCU_XCLK_Sel])
 
-#define RomDriver_HBN_Set_MM_Power_Config                 \
-    ((BL_Err_Type (*) (uint8_t pcfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_MM_Power_Config])
+#define RomDriver_HBN_Set_PDS_Gpio_Keep                   \
+    ((BL_Err_Type (*) (uint8_t gpioKeep))ROM_APITABLE[ROM_API_INDEX_HBN_Set_PDS_Gpio_Keep])
 
 #define RomDriver_HBN_Set_PIR_Interval                    \
     ((BL_Err_Type (*) (uint16_t interval))ROM_APITABLE[ROM_API_INDEX_HBN_Set_PIR_Interval])
@@ -1499,9 +1332,6 @@ typedef enum {
 #define RomDriver_HBN_Set_PIR_Threshold                   \
     ((BL_Err_Type (*) (uint16_t threshold))ROM_APITABLE[ROM_API_INDEX_HBN_Set_PIR_Threshold])
 
-#define RomDriver_HBN_Set_RTC_Misc_Cfg                    \
-    ((BL_Err_Type (*) (HBN_RTC_MISC_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_RTC_Misc_Cfg])
-
 #define RomDriver_HBN_Set_RTC_Timer                       \
     ((BL_Err_Type (*) (HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode))ROM_APITABLE[ROM_API_INDEX_HBN_Set_RTC_Timer])
 
@@ -1511,12 +1341,18 @@ typedef enum {
 #define RomDriver_HBN_Set_UART_CLK_Sel                    \
     ((BL_Err_Type (*) (HBN_UART_CLK_Type clkSel))ROM_APITABLE[ROM_API_INDEX_HBN_Set_UART_CLK_Sel])
 
+#define RomDriver_HBN_Set_User_Boot_Config                \
+    ((BL_Err_Type (*) (uint8_t ubCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Set_User_Boot_Config])
+
 #define RomDriver_HBN_Set_Wakeup_Addr                     \
     ((BL_Err_Type (*) (uint32_t addr))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Wakeup_Addr])
 
 #define RomDriver_HBN_Set_Xtal_Type                       \
     ((BL_Err_Type (*) (uint8_t xtalType))ROM_APITABLE[ROM_API_INDEX_HBN_Set_Xtal_Type])
 
+#define RomDriver_HBN_Trim_Ldo33VoutTrim                  \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_Ldo33VoutTrim])
+
 #define RomDriver_HBN_Trim_RC32K                          \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K])
 
@@ -1532,9 +1368,6 @@ typedef enum {
 #define RomDriver_HBN_Get_MCU_XCLK_Sel                    \
     ((HBN_MCU_XCLK_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_MCU_XCLK_Sel])
 
-#define RomDriver_HBN_Get_Ldo18flash_Repower_Config       \
-    ((uint16_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Ldo18flash_Repower_Config])
-
 #define RomDriver_HBN_Get_PIR_Interval                    \
     ((uint16_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_PIR_Interval])
 
@@ -1550,15 +1383,12 @@ typedef enum {
 #define RomDriver_HBN_Get_Core_Unhalt_Config              \
     ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Core_Unhalt_Config])
 
-#define RomDriver_HBN_Get_Hand_Off_Config                 \
-    ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Hand_Off_Config])
-
-#define RomDriver_HBN_Get_MM_Power_Config                 \
-    ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_MM_Power_Config])
-
 #define RomDriver_HBN_Get_Pin_Wakeup_Mode                 \
     ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode])
 
+#define RomDriver_HBN_Get_User_Boot_Config                \
+    ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_HBN_Get_User_Boot_Config])
+
 #define RomDriver_HBN_Enable                              \
     ((void (*) (uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])
 
@@ -1566,7 +1396,7 @@ typedef enum {
     ((void (*) (HBN_APP_CFG_Type *cfg))ROM_APITABLE[ROM_API_INDEX_HBN_Mode_Enter])
 
 #define RomDriver_HBN_Power_Down_Flash                    \
-    ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
+    ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_HBN_Power_Down_Flash])
 
 #define RomDriver_L1C_DCache_Clean_All                    \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Clean_All])
@@ -1610,17 +1440,14 @@ typedef enum {
 #define RomDriver_L1C_Set_Wrap                            \
     ((BL_Err_Type (*) (uint8_t en))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap])
 
-#define RomDriver_L1C_Get_None_Cache_Addr                 \
-    ((int (*) (uintptr_t addr))ROM_APITABLE[ROM_API_INDEX_L1C_Get_None_Cache_Addr])
-
-#define RomDriver_L1C_Is_DCache_Range                     \
-    ((int (*) (uintptr_t addr))ROM_APITABLE[ROM_API_INDEX_L1C_Is_DCache_Range])
-
 #define RomDriver_L1C_DCache_Write_Set                    \
     ((void (*) (BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_L1C_DCache_Write_Set])
 
 #define RomDriver_PDS_Default_Level_Config                \
-    ((BL_Err_Type (*) (PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config])
+    ((BL_Err_Type (*) (PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Default_Level_Config])
+
+#define RomDriver_PDS_Disable_GPIO_Keep                   \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_GPIO_Keep])
 
 #define RomDriver_PDS_Enable                              \
     ((BL_Err_Type (*) (PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt))ROM_APITABLE[ROM_API_INDEX_PDS_Enable])
@@ -1634,20 +1461,14 @@ typedef enum {
 #define RomDriver_PDS_IntMask                             \
     ((BL_Err_Type (*) (PDS_INT_Type intType, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_PDS_IntMask])
 
-#define RomDriver_PDS_Power_On_MM_System                  \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_MM_System])
-
 #define RomDriver_PDS_RAM_Config                          \
-    ((BL_Err_Type (*) (PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config])
-
-#define RomDriver_PDS_Reset_LP_RTC                        \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset_LP_RTC])
+    ((BL_Err_Type (*) (PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, PDS_CTRL_RAM3_Type *ram3Cfg, PDS_CTRL_RAM4_Type *ram4Cfg))ROM_APITABLE[ROM_API_INDEX_PDS_RAM_Config])
 
 #define RomDriver_PDS_Set_Flash_Pad_Pull_None             \
-    ((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None])
+    ((BL_Err_Type (*) (uint8_t pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None])
 
 #define RomDriver_PDS_Set_Flash_Pad_Pull_None_Fast        \
-    ((BL_Err_Type (*) (SF_Ctrl_Pin_Select pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast])
+    ((BL_Err_Type (*) (uint8_t pinCfg))ROM_APITABLE[ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast])
 
 #define RomDriver_PDS_Set_GPIO_Pad_IntClr                 \
     ((BL_Err_Type (*) (PDS_GPIO_INT_SET_Type set))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr])
@@ -1659,25 +1480,7 @@ typedef enum {
     ((BL_Err_Type (*) (PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode])
 
 #define RomDriver_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie            \
-    ((BL_Err_Type (*) (GLB_GPIO_Type pad, uint8_t pu, uint8_t pd, uint8_t ie))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie])
-
-#define RomDriver_PDS_Set_LP_Clock_Disable                \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_Clock_Disable])
-
-#define RomDriver_PDS_Set_LP_Clock_Enable                 \
-    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_Clock_Enable])
-
-#define RomDriver_PDS_Set_LP_RTC_CLK                      \
-    ((BL_Err_Type (*) (uint8_t enable, uint16_t div))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_RTC_CLK])
-
-#define RomDriver_PDS_Set_LP_Reset_Address                \
-    ((BL_Err_Type (*) (uint32_t addr))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_Reset_Address])
-
-#define RomDriver_PDS_Set_LP_System_CLK                   \
-    ((BL_Err_Type (*) (PDS_LP_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_System_CLK])
-
-#define RomDriver_PDS_Set_LP_System_CLK_Div               \
-    ((BL_Err_Type (*) (uint8_t div))ROM_APITABLE[ROM_API_INDEX_PDS_Set_LP_System_CLK_Div])
+    ((BL_Err_Type (*) (PDS_GPIO_GROUP_SET_Type grp, uint8_t pu, uint8_t pd, uint8_t ie))ROM_APITABLE[ROM_API_INDEX_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie])
 
 #define RomDriver_PDS_Set_MCU0_Clock_Disable              \
     ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Set_MCU0_Clock_Disable])
@@ -1709,49 +1512,41 @@ typedef enum {
 #define RomDriver_PDS_Get_IntStatus                       \
     ((BL_Sts_Type (*) (PDS_INT_Type intType))ROM_APITABLE[ROM_API_INDEX_PDS_Get_IntStatus])
 
-#define RomDriver_PDS_Get_MM_System_Power_On_State        \
-    ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_PDS_Get_MM_System_Power_On_State])
-
 #define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio            \
-    ((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
+    ((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
 
 #define RomDriver_SF_Cfg_Flash_Init                       \
-    ((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Init])
+    ((int (*) (uint8_t sel, const struct sf_ctrl_cfg_type *pSfCtrlCfg, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Init])
 
-#if 0
 #define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock          \
-    ((BL_Err_Type (*) (uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
-#endif
-
-#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext      \
-    ((BL_Err_Type (*) (uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext])
+    ((int (*) (uint32_t flashID, spi_flash_cfg_type *pFlashCfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
 
 #define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio              \
-    ((BL_Err_Type (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
+    ((int (*) (uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
+
+#define RomDriver_SF_Cfg_Init_Flash2_Gpio                 \
+    ((int (*) (uint8_t swap))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash2_Gpio])
 
 #define RomDriver_SF_Cfg_Init_Flash_Gpio                  \
-    ((BL_Err_Type (*) (SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
+    ((int (*) (uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
 
 #define RomDriver_SF_Cfg_Sbus2_Flash_Init                 \
-    ((BL_Err_Type (*) (SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init])
+    ((int (*) (uint8_t sel, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init])
 
 #define RomDriver_SF_Cfg_Flash_Identify                   \
-    ((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
-
-#define RomDriver_SF_Cfg_Flash_Identify_Ext               \
-    ((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify_Ext])
+    ((uint32_t (*) (uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type *pFlashCfg, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
 
 #define RomDriver_SF_Ctrl_GetBusyState                    \
-    ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
+    ((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
 
 #define RomDriver_SF_Ctrl_Is_AES_Enable                   \
-    ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
+    ((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
 
 #define RomDriver_SF_Ctrl_Is_Sbus2_Enable                 \
-    ((BL_Sts_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable])
+    ((int (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable])
 
 #define RomDriver_SF_Ctrl_Get_Flash_Image_Offset          \
-    ((uint32_t (*) (uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
+    ((uint32_t (*) (uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
 
 #define RomDriver_SF_Ctrl_Get_Clock_Delay                 \
     ((uint8_t (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])
@@ -1781,13 +1576,13 @@ typedef enum {
     ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])
 
 #define RomDriver_SF_Ctrl_AES_Set_Key                     \
-    ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
+    ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
 
 #define RomDriver_SF_Ctrl_AES_Set_Key_BE                  \
-    ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
+    ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
 
 #define RomDriver_SF_Ctrl_AES_Set_Mode                    \
-    ((void (*) (SF_Ctrl_AES_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Mode])
+    ((void (*) (uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Mode])
 
 #define RomDriver_SF_Ctrl_AES_Set_Region                  \
     ((void (*) (uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
@@ -1799,16 +1594,16 @@ typedef enum {
     ((void (*) (uint8_t region, uint8_t *iv, uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_IV_BE])
 
 #define RomDriver_SF_Ctrl_AES_XTS_Set_Key                 \
-    ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key])
+    ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key])
 
 #define RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE              \
-    ((void (*) (uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE])
+    ((void (*) (uint8_t region, uint8_t *key, uint8_t keyType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_XTS_Set_Key_BE])
 
 #define RomDriver_SF_Ctrl_Bank2_Enable                    \
-    ((void (*) (const SF_Ctrl_Bank2_Cfg *bank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Bank2_Enable])
+    ((void (*) (const struct sf_ctrl_bank2_cfg *bank2Cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Bank2_Enable])
 
 #define RomDriver_SF_Ctrl_Cmds_Set                        \
-    ((void (*) (SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])
+    ((void (*) (struct sf_ctrl_cmds_cfg *cmdsCfg, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])
 
 #define RomDriver_SF_Ctrl_Disable                         \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
@@ -1817,19 +1612,19 @@ typedef enum {
     ((void (*) (uint8_t disable))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable_Wrap_Access])
 
 #define RomDriver_SF_Ctrl_Enable                          \
-    ((void (*) (const SF_Ctrl_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
+    ((void (*) (const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
 
 #define RomDriver_SF_Ctrl_Flash2_Read_Icache_Set          \
-    ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set])
+    ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash2_Read_Icache_Set])
 
 #define RomDriver_SF_Ctrl_Flash_Read_Icache_Set           \
-    ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])
+    ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmdValid))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])
 
 #define RomDriver_SF_Ctrl_Lock_Flash_Image_Offset         \
     ((void (*) (uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Lock_Flash_Image_Offset])
 
 #define RomDriver_SF_Ctrl_Remap_Set                       \
-    ((void (*) (SF_Ctrl_Remap_Type remap, uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Remap_Set])
+    ((void (*) (uint8_t remap, uint8_t lock))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Remap_Set])
 
 #define RomDriver_SF_Ctrl_Sbus2_Hold_Sram                 \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Hold_Sram])
@@ -1838,7 +1633,7 @@ typedef enum {
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Release_Sram])
 
 #define RomDriver_SF_Ctrl_Sbus2_Replace                   \
-    ((void (*) (SF_Ctrl_Pad_Type pad))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Replace])
+    ((void (*) (uint8_t pad))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Replace])
 
 #define RomDriver_SF_Ctrl_Sbus2_Revoke_replace            \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Revoke_replace])
@@ -1847,109 +1642,109 @@ typedef enum {
     ((void (*) (uint8_t clkDelay, uint8_t rxClkInvert))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus2_Set_Delay])
 
 #define RomDriver_SF_Ctrl_Sbus_Select_Bank                \
-    ((void (*) (SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank])
+    ((void (*) (uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Sbus_Select_Bank])
 
 #define RomDriver_SF_Ctrl_Select_Pad                      \
-    ((void (*) (SF_Ctrl_Pin_Select sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
+    ((void (*) (uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
 
 #define RomDriver_SF_Ctrl_SendCmd                         \
-    ((void (*) (SF_Ctrl_Cmd_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
+    ((void (*) (struct sf_ctrl_cmd_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
 
 #define RomDriver_SF_Ctrl_Set_Clock_Delay                 \
     ((void (*) (uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
 
 #define RomDriver_SF_Ctrl_Set_Flash_Image_Offset          \
-    ((void (*) (uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
+    ((void (*) (uint32_t addrOffset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
 
 #define RomDriver_SF_Ctrl_Set_IO_Delay                    \
-    ((void (*) (SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_IO_Delay])
+    ((void (*) (uint8_t pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_IO_Delay])
 
 #define RomDriver_SF_Ctrl_Set_Owner                       \
-    ((void (*) (SF_Ctrl_Owner_Type owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
+    ((void (*) (uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
 
 #define RomDriver_SFlash_Blk32_Erase                      \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
 
 #define RomDriver_SFlash_Blk64_Erase                      \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t blkNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
 
 #define RomDriver_SFlash_Chip_Erase                       \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
+    ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
 
 #define RomDriver_SFlash_Erase                            \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t startaddr, uint32_t endaddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
 
 #define RomDriver_SFlash_Erase_Security_Register          \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase_Security_Register])
+    ((int (*) (spi_flash_cfg_type *pFlashCfg, struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Erase_Security_Register])
 
 #define RomDriver_SFlash_IDbus_Read_Enable                \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
 
 #define RomDriver_SFlash_Program                          \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
 
 #define RomDriver_SFlash_Program_Security_Register        \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Program_Security_Register])
+    ((int (*) (spi_flash_cfg_type *pFlashCfg, struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Program_Security_Register])
 
 #define RomDriver_SFlash_Qspi_Disable                     \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Disable])
+    ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Disable])
 
 #define RomDriver_SFlash_Qspi_Enable                      \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
+    ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
 
 #define RomDriver_SFlash_RCV_Enable                       \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos))ROM_APITABLE[ROM_API_INDEX_SFlash_RCV_Enable])
+    ((int (*) (spi_flash_cfg_type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos))ROM_APITABLE[ROM_API_INDEX_SFlash_RCV_Enable])
 
 #define RomDriver_SFlash_Read                             \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
 
 #define RomDriver_SFlash_Read_Reg                         \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
 
 #define RomDriver_SFlash_Read_Reg_With_Cmd                \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
 
 #define RomDriver_SFlash_Read_Security_Register           \
-    ((BL_Err_Type (*) (SFlash_Sec_Reg_Cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Security_Register])
+    ((int (*) (struct sflash_sec_reg_cfg *pSecRegCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Security_Register])
 
 #define RomDriver_SFlash_Restore_From_Powerdown           \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
+    ((int (*) (spi_flash_cfg_type *pFlashCfg, uint8_t flashContRead, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
 
 #define RomDriver_SFlash_Sector_Erase                     \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint32_t secNum))ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
 
 #define RomDriver_SFlash_Set32BitsAddrMode                \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Set32BitsAddrMode])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t en32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_Set32BitsAddrMode])
 
 #define RomDriver_SFlash_SetSPIMode                       \
-    ((BL_Err_Type (*) (SF_Ctrl_Mode_Type mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
+    ((int (*) (uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
 
 #define RomDriver_SFlash_Set_IDbus_Cfg                    \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t ioMode, uint8_t contRead, uint32_t addr, uint32_t len, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
 
 #define RomDriver_SFlash_Software_Reset                   \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
+    ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
 
 #define RomDriver_SFlash_Write_Enable                     \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
+    ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
 
 #define RomDriver_SFlash_Write_Reg                        \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
 
 #define RomDriver_SFlash_Write_Reg_With_Cmd               \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
+    ((int (*) (spi_flash_cfg_type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen))ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
 
 #define RomDriver_SFlash_Busy                             \
-    ((BL_Sts_Type (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
+    ((int (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
 
 #define RomDriver_SFlash_DisableBurstWrap                 \
-    ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
+    ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
 
 #define RomDriver_SFlash_GetDeviceId                      \
-    ((void (*) (uint8_t *data, BL_Fun_Type is32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
+    ((void (*) (uint8_t *data, uint8_t is32BitsAddr))ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
 
 #define RomDriver_SFlash_GetJedecId                       \
-    ((void (*) (SPI_Flash_Cfg_Type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
+    ((void (*) (spi_flash_cfg_type *flashCfg, uint8_t *data))ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
 
 #define RomDriver_SFlash_GetUniqueId                      \
     ((void (*) (uint8_t *data, uint8_t idLen))ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
@@ -1958,25 +1753,22 @@ typedef enum {
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Disable])
 
 #define RomDriver_SFlash_Init                             \
-    ((void (*) (const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
+    ((void (*) (const struct sf_ctrl_cfg_type *pSfCtrlCfg, const struct sf_ctrl_bank2_cfg *pBank2Cfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
 
 #define RomDriver_SFlash_Powerdown                        \
     ((void (*) (void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
 
 #define RomDriver_SFlash_Release_Powerdown                \
-    ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Release_Powerdown])
+    ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Release_Powerdown])
 
 #define RomDriver_SFlash_Reset_Continue_Read              \
-    ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
+    ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
 
 #define RomDriver_SFlash_SetBurstWrap                     \
-    ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
+    ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
 
 #define RomDriver_SFlash_Volatile_Reg_Write_Enable        \
-    ((void (*) (SPI_Flash_Cfg_Type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
-
-#define RomDriver_UART_ApplyAbrResult                     \
-    ((BL_Err_Type (*) (UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet))ROM_APITABLE[ROM_API_INDEX_UART_ApplyAbrResult])
+    ((void (*) (spi_flash_cfg_type *flashCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
 
 #define RomDriver_UART_AutoBaudDetection                  \
     ((BL_Err_Type (*) (UART_ID_Type uartId, BL_Fun_Type autoBaud))ROM_APITABLE[ROM_API_INDEX_UART_AutoBaudDetection])
@@ -2026,8 +1818,8 @@ typedef enum {
 #define RomDriver_UART_SetAllowableError0X55              \
     ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t allowableError))ROM_APITABLE[ROM_API_INDEX_UART_SetAllowableError0X55])
 
-#define RomDriver_UART_SetBaudRate                        \
-    ((BL_Err_Type (*) (UART_ID_Type uartId, uint32_t baudRate))ROM_APITABLE[ROM_API_INDEX_UART_SetBaudRate])
+#define RomDriver_UART_SetBaudrate                        \
+    ((BL_Err_Type (*) (UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet))ROM_APITABLE[ROM_API_INDEX_UART_SetBaudrate])
 
 #define RomDriver_UART_SetDeglitchCount                   \
     ((BL_Err_Type (*) (UART_ID_Type uartId, uint8_t deglitchCnt))ROM_APITABLE[ROM_API_INDEX_UART_SetDeglitchCount])
@@ -2087,31 +1879,31 @@ typedef enum {
     ((uint8_t (*) (UART_ID_Type uartId))ROM_APITABLE[ROM_API_INDEX_UART_GetTxFifoCount])
 
 #define RomDriver_XIP_SFlash_Erase_Need_Lock              \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
 
 #define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock        \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
 
 #define RomDriver_XIP_SFlash_GetJedecId_Need_Lock         \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
 
 #define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock        \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
 
 #define RomDriver_XIP_SFlash_Read_Need_Lock               \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
 
 #define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock     \
-    ((BL_Err_Type (*) (uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
+    ((BL_Err_Type (*) (uint32_t addr, uint8_t *data, uint32_t len))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
 
 #define RomDriver_XIP_SFlash_State_Restore                \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t offset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
 
 #define RomDriver_XIP_SFlash_State_Save                   \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t *offset, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
 
 #define RomDriver_XIP_SFlash_Write_Need_Lock              \
-    ((BL_Err_Type (*) (SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
+    ((BL_Err_Type (*) (spi_flash_cfg_type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
 
 #define RomDriver_XIP_SFlash_Opt_Enter                    \
     ((void (*) (uint8_t *aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Enter])
@@ -2119,6 +1911,54 @@ typedef enum {
 #define RomDriver_XIP_SFlash_Opt_Exit                     \
     ((void (*) (uint8_t aesEnable))ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Opt_Exit])
 
+#define RomDriver_MD_Clr_GPIO_IntStatus                   \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_Clr_GPIO_IntStatus])
+
+#define RomDriver_MD_Embedded_Flash_Pad_Enable            \
+    ((BL_Err_Type (*) (void))ROM_APITABLE[ROM_API_INDEX_MD_Embedded_Flash_Pad_Enable])
+
+#define RomDriver_MD_GPIO_Clr                             \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Clr])
+
+#define RomDriver_MD_GPIO_Init                            \
+    ((BL_Err_Type (*) (MD_GPIO_Cfg_Type *cfg))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Init])
+
+#define RomDriver_MD_GPIO_Input_Disable                   \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Input_Disable])
+
+#define RomDriver_MD_GPIO_Input_Enable                    \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Input_Enable])
+
+#define RomDriver_MD_GPIO_IntMask                         \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin, BL_Mask_Type intMask))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_IntMask])
+
+#define RomDriver_MD_GPIO_Int_Init                        \
+    ((BL_Err_Type (*) (MD_GPIO_INT_Cfg_Type *intCfg))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Int_Init])
+
+#define RomDriver_MD_GPIO_Output_Disable                  \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Output_Disable])
+
+#define RomDriver_MD_GPIO_Output_Enable                   \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Output_Enable])
+
+#define RomDriver_MD_GPIO_Set                             \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Set])
+
+#define RomDriver_MD_GPIO_Set_HZ                          \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Set_HZ])
+
+#define RomDriver_MD_GPIO_Write                           \
+    ((BL_Err_Type (*) (MD_GPIO_Type gpioPin, uint32_t val))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Write])
+
+#define RomDriver_MD_Get_GPIO_IntStatus                   \
+    ((BL_Sts_Type (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_Get_GPIO_IntStatus])
+
+#define RomDriver_MD_GPIO_Read                            \
+    ((uint32_t (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Read])
+
+#define RomDriver_MD_GPIO_Get_Fun                         \
+    ((uint8_t (*) (MD_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_MD_GPIO_Get_Fun])
+
 /*@} end of group ROMDRIVER_Public_Macros */
 
 /** @defgroup  ROMDRIVER_Public_Functions
@@ -2129,6 +1969,6 @@ typedef enum {
 
 /*@} end of group ROMDRIVER */
 
-/*@} end of group bl808_Peripheral_Driver */
+/*@} end of group bl616_Peripheral_Driver */
 
-#endif /* __bl808_ROMDRIVER_H__ */
+#endif /* __bl616_ROMDRIVER_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdh.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdh.h
new file mode 100755
index 0000000000..e8983a53c3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdh.h
@@ -0,0 +1,979 @@
+/**
+  ******************************************************************************
+  * @file    bl616_sdh.h
+  * @version V1.2
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2018 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_SDH_H__
+#define __BL616_SDH_H__
+
+#include "sdh_reg.h"
+#include "bl616_common.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SDH
+ *  @{
+ */
+
+/** @defgroup  SDH_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief SDH status type definition
+ */
+typedef enum {
+    SDH_STAT_SUCCESS = 0,        /*!< SDH status success */
+    SDH_STAT_BUSY,               /*!< SDH status busy */
+    SDH_STAT_INVLAID_PARA,       /*!< SDH status invalid parameter */
+    SDH_STAT_NOT_SUPPORT,        /*!< SDH not support this feature */
+    SDH_STAT_OUTOF_RANGE,        /*!< SDH out of range */
+    SDH_STAT_PREPARE_DESC,       /*!< SDH status prepare ADMA descriptor */
+    SDH_STAT_SEND_CMD_FAIL,      /*!< SDH status send command fail */
+    SDH_STAT_SEND_DATA_FAIL,     /*!< SDH status send data fail */
+    SDH_STAT_RECV_DATA_FAIL,     /*!< SDH status receive data fail */
+    SDH_STAT_DMA_ADDR_NOT_ALIGN, /*!< SDH status DMA address not align */
+    SDH_STAT_RETUNE_REQ,         /*!< SDH status re-tune request */
+    SDH_STAT_TUNE_ERROR,         /*!< SDH status tune error */
+} SDH_Stat_Type;
+
+/**
+ *  @brief SDH capability type definition
+ */
+typedef enum {
+    SDH_CAP_SUPPORT_8BITS = 0x00000004,       /*!< SDH support 8 bits */
+    SDH_CAP_SUPPORT_ADMA2 = 0x00000008,       /*!< SDH support ADMA 2 */
+    SDH_CAP_SUPPORT_ADMA1 = 0x00000010,       /*!< SDH support ADMA 1 */
+    SDH_CAP_SUPPORT_HIGHSPEED = 0x00000020,   /*!< SDH support SDMA */
+    SDH_CAP_SUPPORT_SDMA = 0x00000040,        /*!< SDH support high speed */
+    SDH_CAP_SUPPORT_SUS_RES = 0x00000080,     /*!< SDH support suspend and resume */
+    SDH_CAP_SUPPORT_VLT33 = 0x00000100,       /*!< SDH support voltgae 3.3V */
+    SDH_CAP_SUPPORT_VLT30 = 0x00000200,       /*!< SDH support voltage 3.0V */
+    SDH_CAP_SUPPORT_VLT18 = 0x00000400,       /*!< SDH support voltage 1.8V */
+    SDH_CAP_SUPPORT_SBUS_64BITS = 0x00001000, /*!< SDH support system bus 64 bits */
+    SDH_CAP_SUPPORT_ASYNC_INT = 0x00002000,   /*!< SDH support async interrupt */
+    SDH_CAP_SUPPORT_DDR50 = 0x00010000,       /*!< SDH support DDR 50MHz */
+    SDH_CAP_SUPPORT_SDR104 = 0x00020000,      /*!< SDH support SDR 104MHz */
+    SDH_CAP_SUPPORT_SDR50 = 0x00040000,       /*!< SDH support SDR 50MHz */
+    SDH_CAP_SUPPORT_DRV_TYPE_A = 0x00100000,  /*!< SDH support driver type C */
+    SDH_CAP_SUPPORT_DRV_TYPE_C = 0x00200000,  /*!< SDH support driver type A */
+    SDH_CAP_SUPPORT_DRV_TYPE_D = 0x00400000,  /*!< SDH support driver type A */
+    SDH_CAP_SUPPORT_SDR50_TUNE = 0x20000000,  /*!< SDH support SDR 50MHz tuning */
+} SDH_Cap_Support_Type;
+
+/**
+ *  @brief SDH wakeup event type definition
+ */
+typedef enum {
+    SDH_WAKEUP_EVENT_INT,    /*!< Wakeup on card interrupt */
+    SDH_WAKEUP_EVENT_INSERT, /*!< Wakeup on card insertion */
+    SDH_WAKEUP_EVENT_REMOVE, /*!< Wakeup on card remove */
+} SDH_Wakeup_Event_Type;
+
+/**
+ *  @brief SDH trnasfer flag type definition
+ */
+typedef enum {
+    SDH_TRANS_FLAG_NONE = 0x00000000,
+    SDH_TRANS_FLAG_EN_DMA = 0x00000001,                /*!< Enable DMA */
+    SDH_TRANS_FLAG_EN_BLK_COUNT = 0x00000002,          /*!< Enable block count */
+    SDH_TRANS_FLAG_EN_AUTO_CMD12 = 0x00000004,         /*!< Enable auto CMD12 */
+    SDH_TRANS_FLAG_EN_AUTO_CMD23 = 0x00000008,         /*!< Enable auto CMD23 */
+    SDH_TRANS_FLAG_READ_DATA = 0x00000010,             /*!< Enable read data */
+    SDH_TRANS_FLAG_MULTI_BLK = 0x00000020,             /*!< Enable multi-block data operation */
+    SDH_TRANS_FLAG_RESP_136BITS = 0x00010000,          /*!< Response is 136 bits length */
+    SDH_TRANS_FLAG_RESP_48BITS = 0x00020000,           /*!< Response is 48 bits length */
+    SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY = 0x00030000, /*!< Response is 48 bits length with busy status */
+    SDH_TRANS_FLAG_EN_CRC_CHECK = 0x00080000,          /*!< Enable CRC check */
+    SDH_TRANS_FLAG_EN_INDEX_CHECK = 0x00100000,        /*!< Enable index check */
+    SDH_TRANS_FLAG_DATA_PRESENT = 0x00200000,          /*!< Data present */
+    SDH_TRANS_FLAG_SUSPEND = 0x00400000,               /*!< Suspend command */
+    SDH_TRANS_FLAG_RESUME = 0x00800000,                /*!< Resume command */
+    SDH_TRANS_FLAG_ABORT = 0x00C00000,                 /*!< Abort command */
+} SDH_Trans_Flag_Type;
+
+/**
+ *  @brief SDH present flag type definition
+ */
+typedef enum {
+    SDH_PRESENT_FLAG_CMD_INHBIT = 0x00000001,       /*!< Command inhbit */
+    SDH_PRESENT_FLAG_DATA_INHBIT = 0x00000002,      /*!< Data inhbit */
+    SDH_PRESENT_FLAG_DATA_LINE_ACTIVE = 0x00000004, /*!< Data line active */
+    SDH_PRESENT_FLAG_RETUNE_REQ = 0x00000008,       /*!< Retuning request */
+    SDH_PRESENT_FLAG_TX_ACTIVE = 0x00000100,        /*!< Write trnasfer atcive */
+    SDH_PRESENT_FLAG_RX_ACTIVE = 0x00000200,        /*!< Read transfer active */
+    SDH_PRESENT_FLAG_BUF_WRITE_ENABLE = 0x00000400, /*!< Buffer write enabled */
+    SDH_PRESENT_FLAG_BUF_READ_ENABLE = 0x00000800,  /*!< Buffer read enabled */
+    SDH_PRESENT_FLAG_CARD_INSERT = 0x00010000,      /*!< Card intert */
+    SDH_PRESENT_FLAG_CARD_STABLE = 0x00020000,      /*!< Card stable */
+    SDH_PRESENT_FLAG_CARD_DET = 0x00040000,         /*!< Card detect */
+    SDH_PRESENT_FLAG_CARD_WP = 0x00080000,          /*!< Card write protect */
+    SDH_PRESENT_FLAG_DATA0_LINE_LEVEL = 0x00100000, /*!< Data 0 line signal level */
+    SDH_PRESENT_FLAG_DATA1_LINE_LEVEL = 0x00200000, /*!< Data 1 line signal level */
+    SDH_PRESENT_FLAG_DATA2_LINE_LEVEL = 0x00400000, /*!< Data 2 line signal level */
+    SDH_PRESENT_FLAG_DATA3_LINE_LEVEL = 0x00800000, /*!< Data 3 line signal level */
+    SDH_PRESENT_FLAG_CMD_LINE_LEVEL = 0x01000000,   /*!< Command line signal level */
+} SDH_Present_Flag_Type;
+
+/**
+ *  @brief SDH interrupt type definition
+ */
+#define SDH_INT_CMD_COMPLETED      ((uint32_t)(0x00000001)) /*!< SDH command complete interrupt */
+#define SDH_INT_DATA_COMPLETED     ((uint32_t)(0x00000002)) /*!< SDH data complete interrupt */
+#define SDH_INT_BLK_GAP_EVENT      ((uint32_t)(0x00000004)) /*!< SDH block gap event interrupt */
+#define SDH_INT_DMA_COMPLETED      ((uint32_t)(0x00000008)) /*!< SDH DMA complete interrupt */
+#define SDH_INT_BUFFER_WRITE_READY ((uint32_t)(0x00000010)) /*!< SDH buffer write ready interrupt */
+#define SDH_INT_BUFFER_READ_READY  ((uint32_t)(0x00000020)) /*!< SDH buffer read ready interrupt */
+#define SDH_INT_CARD_INSERT        ((uint32_t)(0x00000040)) /*!< SDH card insert interrupt */
+#define SDH_INT_CARD_REMOVE        ((uint32_t)(0x00000080)) /*!< SDH card remove interrupt */
+#define SDH_INT_CARD               ((uint32_t)(0x00000100)) /*!< SDH card produce interrupt */
+#define SDH_INT_DRIVER_TA          ((uint32_t)(0x00000200)) /*!< SDH driver type A interrupt */
+#define SDH_INT_DRIVER_TB          ((uint32_t)(0x00000400)) /*!< SDH driver type B interrupt */
+#define SDH_INT_DRIVER_TC          ((uint32_t)(0x00000800)) /*!< SDH driver type C interrupt */
+#define SDH_INT_RETUNE_EVENT       ((uint32_t)(0x00001000)) /*!< SDH re-tuning event interrupt */
+#define SDH_INT_CMD_TIMEOUT        ((uint32_t)(0x00010000)) /*!< SDH command timeout interrupt */
+#define SDH_INT_CMD_CRC_ERROR      ((uint32_t)(0x00020000)) /*!< SDH command CRC error interrupt */
+#define SDH_INT_CMD_ENDBIT_ERROR   ((uint32_t)(0x00040000)) /*!< SDH command endbit error interrupt */
+#define SDH_INT_CMD_INDEX_ERROR    ((uint32_t)(0x00080000)) /*!< SDH command index error interrupt */
+#define SDH_INT_DATA_TIMEOUT       ((uint32_t)(0x00100000)) /*!< SDH data timeout interrupt */
+#define SDH_INT_DATA_CRC_ERROR     ((uint32_t)(0x00200000)) /*!< SDH data CRC error interrupt */
+#define SDH_INT_DATA_ENDBIT_ERROR  ((uint32_t)(0x00400000)) /*!< SDH data endbit error interrupt */
+#define SDH_INT_CURRENT_ERROR      ((uint32_t)(0x00800000)) /*!< SDH current error interrupt */
+#define SDH_INT_AUTO_CMD12_ERROR   ((uint32_t)(0x01000000)) /*!< SDH auto command12 error */
+#define SDH_INT_DMA_ERROR          ((uint32_t)(0x02000000)) /*!< SDH DMA error interrupt */
+#define SDH_INT_TUNE_ERROR         ((uint32_t)(0x04000000)) /*!< SDH tuning maybe fail,this bit is set when an unrecoverable error is detected in a tuning circuit except during tuning procedure */
+#define SDH_INT_SPI_ERROR          ((uint32_t)(0x10000000)) /*!< SDH SPI mode error,read   field in the SPI mode register */
+#define SDH_INT_AXI_RESP_ERROR     ((uint32_t)(0x20000000)) /*!< SDH AXI bus response error */
+#define SDH_INT_CPL_TIMEOUT_ERROR  ((uint32_t)(0x40000000)) /*!< SDH command completion signal timeout error,this field is applicable for CE-ATA mode only */
+#define SDH_INT_CRC_STAT_ERROR     ((uint32_t)(0x80000000)) /*!< SDH CRC status start bit or CRC status end bit or boot ack status, returned from the card in write transaction has errors */
+#define SDH_INT_CMD_ERRORS         ((uint32_t)(0x000f0000)) /*!< SDH all command errors */
+#define SDH_INT_DATA_ERRORS        ((uint32_t)(0x01700000)) /*!< SDH all data errors */
+#define SDH_INT_ALL                ((uint32_t)(0xffffffff)) /*!< SDH all interrupt */
+
+/**
+ *  @brief SDH boot mode type definition
+ */
+typedef enum {
+    SDH_BOOT_MODE_NORMAL, /*!< SDH normal boot mode */
+    SDH_BOOT_MODE_ALT,    /*!< SDH alternative boot mode */
+} SDH_Boot_Mode_Type;
+
+/**
+ *  @brief SDH auto command 12 error status type definition
+ */
+typedef enum {
+    SDH_AUTO_CMD12_ERR_NOT_EXE,   /*!< SDH auto command not execute error */
+    SDH_AUTO_CMD12_ERR_TIMEOUT,   /*!< SDH auto command timeout error */
+    SDH_AUTO_CMD12_ERR_ENDBIT,    /*!< SDH auto command endbit error */
+    SDH_AUTO_CMD12_ERR_INDEX,     /*!< SDH auto command index error */
+    SDH_AUTO_CMD12_ERR_CRC,       /*!< SDH auto command CRC error */
+    SDH_AUTO_CMD12_ERR_NOT_ISSUE, /*!< SDH auto command not issue error */
+} SDH_AUTO_CMD12_ERR_Type;
+
+/**
+ *  @brief SDH ADMA error type definition
+ */
+typedef enum {
+    SDH_ADMA_ERR_LEN_MISMATCH, /*!< SDH ADMA length mismatch */
+    SDH_ADMA_ERR_DESC_ERROR,   /*!< SDH ADMA descriptor error */
+} SDH_ADMA_ERR_Type;
+
+/**
+ *  @brief SDH ADMA error status type definition
+ */
+typedef enum {
+    SDH_ADMA_ERR_STAT_STOP_DMA,     /*!< SDH ADMA stop */
+    SDH_ADMA_ERR_STAT_FETCH_DESC,   /*!< SDH ADMA fetch descriptor */
+    SDH_ADMA_ERR_STAT_CHANGE_ADDR,  /*!< SDH ADMA change address */
+    SDH_ADMA_ERR_STAT_TRANS_DATA,   /*!< SDH ADMA transfer data */
+    SDH_ADMA_ERR_STAT_INVALID_LEN,  /*!< SDH ADMA invalid length */
+    SDH_ADMA_ERR_STAT_INVALID_DESC, /*!< SDH ADMA invalid descriptor */
+} SDH_ADMA_ERR_Stat_Type;
+
+/**
+ *  @brief SDH force event type definition
+ */
+typedef enum {
+    SDH_FORCE_EVENT_AUTO_CMD12_NOT_EXE,     /*!< SDH force event auto command 12 not executed */
+    SDH_FORCE_EVENT_AUTO_CMD12_TIMEOUT,     /*!< SDH force event auto command 12 timeout */
+    SDH_FORCE_EVENT_AUTO_CMD12_CRC_ERROR,   /*!< SDH force event auto command 12 crc error */
+    SDH_FORCE_EVENT_AUTO_CMD12_INDEX_ERROR, /*!< SDH force event auto command 12 index error */
+    SDH_FORCE_EVENT_AUTO_CMD12_NOT_ISSUE,   /*!< SDH force event auto command 12 not issue */
+    SDH_FORCE_EVENT_ENDBIT_ERROR,           /*!< SDH force event end bit error */
+    SDH_FORCE_EVENT_CMD_TIMEOUT,            /*!< SDH force event command timeout */
+    SDH_FORCE_EVENT_CMD_CRC_ERROR,          /*!< SDH force event command crc error */
+    SDH_FORCE_EVENT_CMD_ENDBIT_ERROR,       /*!< SDH force event command end bit error */
+    SDH_FORCE_EVENT_CMD_INDEX_ERROR,        /*!< SDH force event command index error */
+    SDH_FORCE_EVENT_DATA_TIMEOUT,           /*!< SDH force event data timeout */
+    SDH_FORCE_EVENT_DATA_CRC_ERROR,         /*!< SDH force event data crc error */
+    SDH_FORCE_EVENT_DATA_ENDBIT_ERROR,      /*!< SDH force event data end bit error */
+    SDH_FORCE_EVENT_DATA_INDEX_ERROR,       /*!< SDH force event data index error */
+    SDH_FORCE_EVENT_AUTO_CMD12_ERROR,       /*!< SDH force event auto command 12 error */
+    SDH_FORCE_EVENT_CARD_INT,               /*!< SDH force event card interrupt */
+    SDH_FORCE_EVENT_DMA_ERROR,              /*!< SDH force event DMA error */
+} SDH_Force_Event_Type;
+
+/**
+ *  @brief SDH speed mode type definition
+ */
+typedef enum {
+    SDH_SPEED_MODE_SDR12,  /*!< SDH speed :12.5MHZ */
+    SDH_SPEED_MODE_SDR25,  /*!< SDH speed :25MHZ */
+    SDH_SPEED_MODE_SDR50,  /*!< SDH speed :50MHZ */
+    SDH_SPEED_MODE_SDR104, /*!< SDH speed :104MHZ */
+    SDH_SPEED_MODE_DDR50,  /*!< SDH speed :50MHZ (DDR mode) */
+} SDH_Speed_Mode_Type;
+
+/**
+ *  @brief SDH data bus width type definition
+ */
+typedef enum {
+    SDH_DATA_BUS_WIDTH_1BIT,  /*!< SDH data bus width 1 bit */
+    SDH_DATA_BUS_WIDTH_4BITS, /*!< SDH data bus width 4 bits */
+    SDH_DATA_BUS_WIDTH_8BITS, /*!< SDH data bus width 8 bits */
+} SDH_Data_Bus_Width_Type;
+
+/**
+ *  @brief SDH voltage type definition
+ */
+typedef enum {
+    SDH_VOLTAGE_3P3V = 0x07, /*!< SDH voltage 3.3V */
+    SDH_VOLTAGE_3P0V = 0x06, /*!< SDH voltage 3.0V */
+    SDH_VOLTAGE_1P8V = 0x05, /*!< SDH voltage 1.8V */
+} SDH_Voltage_Type;
+
+/**
+ *  @brief SDH DMA mode type definition
+ */
+typedef enum {
+    SDH_DMA_MODE_SIMPLE, /*!< SDH DMA mode:simple */
+    SDH_DMA_MODE_ADMA1,  /*!< SDH DMA mode:ADMA1 */
+    SDH_DMA_MODE_ADMA2,  /*!< SDH DMA mode:ADMA2 */
+} SDH_DMA_Mode_Type;
+
+/**
+ *  @brief SDH control flag type definition
+ */
+typedef enum {
+    SDH_CTRL_FLAG_STOP_AT_BLK_GAP,         /*!< SDH control flag: stop at block gap */
+    SDH_CTRL_FLAG_READ_WAIT,               /*!< SDH control flag: read wait */
+    SDH_CTRL_FLAG_INT_AT_BLK_GAP,          /*!< SDH control flag: interrupt at block gap */
+    SDH_CTRL_FLAG_RAED_DONE_WITHOUT_8CLKS, /*!< SDH control flag: read done without 8 clks for block gap */
+    SDH_CTRL_FLAG_EXACT_BLK_NUM_READ,      /*!< SDH control flag: Exact block number read */
+} SDH_Ctrl_Flag_Type;
+
+/**
+ *  @brief SDH Command type definition
+ */
+typedef enum {
+    SDH_CMD_NORMAL,  /*!< SDH command type:normal */
+    SDH_CMD_SUSPEND, /*!< SDH command type:suspend */
+    SDH_CMD_RESUME,  /*!< SDH command type:resume */
+    SDH_CMD_ABORT,   /*!< SDH command type:abort */
+    SDH_CMD_EMPTY,   /*!< SDH command type:empty */
+} SDH_Cmd_Type;
+
+/**
+ *  @brief SDH response type definition
+ */
+typedef enum {
+    SDH_RESP_NONE, /*!< SDH response type:none */
+    SDH_RESP_136LEN,
+    SDH_RESP_48LEN,
+    SDH_RESP_48LEN_BUSY,
+    SDH_RESP_R1,  /*!< SDH response type:r1 */
+    SDH_RESP_R1B, /*!< SDH response type:r1b */
+    SDH_RESP_R2,  /*!< SDH response type:r2 */
+    SDH_RESP_R3,  /*!< SDH response type:r3 */
+    SDH_RESP_R4,  /*!< SDH response type:r4 */
+    SDH_RESP_R5,  /*!< SDH response type:r5 */
+    SDH_RESP_R5B, /*!< SDH response type:r5b */
+    SDH_RESP_R6,  /*!< SDH response type:r6 */
+    SDH_RESP_R7,  /*!< SDH response type:r7 */
+} SDH_Resp_Type;
+
+/**
+ *  @brief SDH ADMA descriptor chain type definition
+ */
+typedef enum {
+    SDH_ADMA_FLAG_SINGLE_DESC, /*!< SDH transfer a single ADMA descriptor */
+    SDH_ADMA_FLAG_MULTI_DESC,  /*!< SDH create multiple ADMA descriptor within the ADMA table(mmc boot mode) */
+} SDH_ADMA_Flag_Type;
+
+/**
+ *  @brief SDH ADMA1 descriptor flag type definition
+ */
+typedef enum {
+    SDH_ADMA1_DESC_FLAG_VALID = 0X01,    /*!< SDH ADMA1 descriptor valid flag */
+    SDH_ADMA1_DESC_FLAG_END = 0X02,      /*!< SDH ADMA1 descriptor end flag */
+    SDH_ADMA1_DESC_FLAG_INT = 0X04,      /*!< SDH ADMA1 descriptor interrupt flag */
+    SDH_ADMA1_DESC_FLAG_ACTIVE1 = 0X10,  /*!< SDH ADMA1 descriptor atcive1 flag */
+    SDH_ADMA1_DESC_FLAG_ACTIVE2 = 0X20,  /*!< SDH ADMA1 descriptor active2 flag */
+    SDH_ADMA1_DESC_FLAG_TRANSFER = 0x21, /*!< SDH ADMA1 trnasfer descriptor flag\ */
+    SDH_ADMA1_DESC_FLAG_LINK = 0x31,     /*!< SDH ADMA1 link descriptor flag */
+    SDH_ADMA1_DESC_FLAG_SETLEN = 0x11,   /*!< SDH ADMA1 set length descriptor flag */
+} SDH_ADMA1_Desc_Flag_Type;
+
+/**
+ *  @brief SDH ADMA2 descriptor flag type definition
+ */
+typedef enum {
+    SDH_ADMA2_DESC_FLAG_VALID = 0X01,    /*!< SDH ADMA2 descriptor valid flag */
+    SDH_ADMA2_DESC_FLAG_END = 0X02,      /*!< SDH ADMA2 descriptor end flag */
+    SDH_ADMA2_DESC_FLAG_INT = 0X04,      /*!< SDH ADMA2 descriptor interrupt flag */
+    SDH_ADMA2_DESC_FLAG_ACTIVE1 = 0X10,  /*!< SDH ADMA2 descriptor atcive1 flag */
+    SDH_ADMA2_DESC_FLAG_ACTIVE2 = 0X20,  /*!< SDH ADMA2 descriptor active2 flag */
+    SDH_ADMA2_DESC_FLAG_TRANSFER = 0x21, /*!< SDH ADMA2 trnasfer descriptor flag\ */
+    SDH_ADMA2_DESC_FLAG_LINK = 0x31,     /*!< SDH ADMA2 link descriptor flag */
+} SDH_ADMA2_Desc_Flag_Type;
+
+/**
+ *  @brief SDH burst length type definition
+ */
+typedef enum {
+    SDH_BUSRT_INCR,  /*!< SDH burst length incremental */
+    SDH_BUSRT_INCR4, /*!< SDH ADMA2 length INCR4 */
+    SDH_BUSRT_WRAP4, /*!< SDH ADMA2 length Wrap 4 */
+} SDH_Burst_Type;
+
+/**
+ *  @brief SDH FIFO threshold type definition
+ */
+typedef enum {
+    SDH_FIFO_THRESHOLD_64_BYTES,  /*!< SDH FIFO threshold is 64 bytes to generate DMA request */
+    SDH_FIFO_THRESHOLD_128_BYTES, /*!< SDH FIFO threshold is 128 bytes to generate DMA request */
+    SDH_FIFO_THRESHOLD_192_BYTES, /*!< SDH FIFO threshold is 192 bytes to generate DMA request */
+    SDH_FIFO_THRESHOLD_256_BYTES, /*!< SDH FIFO threshold is 256 bytes to generate DMA request */
+} SDH_FIFO_Threshold_Type;
+
+/**
+ *  @brief SDH burst length type definition
+ */
+typedef enum {
+    SDH_BURST_SIZE_32_BYTES,  /*!< SDH busrt size is 32 bytes */
+    SDH_BURST_SIZE_64_BYTES,  /*!< SDH busrt size is 64 bytes */
+    SDH_BURST_SIZE_128_BYTES, /*!< SDH busrt size is 128 bytes */
+    SDH_BURST_SIZE_256_BYTES, /*!< SDH busrt size is 256 bytes */
+} SDH_Burst_Size_Type;
+
+/**
+ *  @brief SDH transferd data type definition
+ */
+typedef enum {
+    SDH_TRANS_DATA_NORMAL,    /*!< SDH transfer normal data */
+    SDH_TRANS_DATA_TUNING,    /*!< SDH transfer tuning data */
+    SDH_TRANS_DATA_BOOT,      /*!< SDH transfer boot data */
+    SDH_TRANS_DATA_BOOT_CONT, /*!< SDH transfer boot data continous */
+} SDH_Trans_Data_Type;
+
+/**
+ *  @brief SDH ADMA2 descriptor structure type definition
+ */
+typedef struct
+{
+    uint32_t attribute;      /*!< SDH ADMA2 descriptor attribute */
+    const uint32_t *address; /*!< SDH ADMA2 descriptor address pointer */
+} SDH_ADMA2_Desc_Type;
+
+/**
+ *  @brief SDH capability structure type definition
+ */
+typedef struct
+{
+    uint32_t sdVersion;      /*!< SDH support SD card/sdio version */
+    uint32_t mmcVersion;     /*!< SDH support emmc card version */
+    uint32_t maxBlockLength; /*!< SDH maximum block length united as byte */
+    uint32_t maxBlockCount;  /*!< SDH maximum block count can be set one time */
+    uint32_t flags;          /*!< SDH capability flags to indicate the support information */
+} SDH_Cap_Cfg_Type;
+
+/**
+ *  @brief SDH boot config structure type definition
+ */
+typedef struct
+{
+    uint32_t ackTimeoutCount;         /*!< SDH timeout value for the boot ACK. The available range is 0 ~ 15 */
+    SDH_Boot_Mode_Type bootMode;      /*!< SDH boot mode selection */
+    uint32_t blockCount;              /*!< SDH stop at block gap value of automatic mode. Available range is 0 ~ 65535 */
+    uint32_t blockSize;               /*!< SDH block size */
+    uint8_t enableBootAck;            /*!< SDH enable or disable boot ACK */
+    uint8_t enableAutoStopAtBlockGap; /*!< SDH enable or disable auto stop at block gap function in boot period */
+} SDH_Boot_Cfg_Type;
+
+/**
+ *  @brief SDH config structure type definition
+ */
+typedef struct
+{
+    SDH_Speed_Mode_Type speed;         /*!< SDH host controller speed */
+    BL_Fun_Type vlot18Enable;          /*!< SDH enable 1.8V */
+    BL_Fun_Type highSpeed;             /*!< SDH enable high speed */
+    SDH_Data_Bus_Width_Type dataWidth; /*!< SDH data bus width */
+    SDH_Voltage_Type volt;             /*!< SDH voltage */
+    uint32_t srcClock;                 /*!< SDH source clock frequency in HZ */
+    uint32_t busClock;                 /*!< SDH bus clock frequency in HZ */
+    uint32_t dataTimeout;              /*!< SDH data timeout value */
+    uint8_t readWatermarkLevel;        /*!< SDH watermark level for DMA read operation. Available range is 1 ~ 128. */
+    uint8_t writeWatermarkLevel;       /*!< SDH watermark level for DMA write operation. Available range is 1 ~ 128. */
+    uint8_t readBurstLen;              /*!< SDH read burst len */
+    uint8_t writeBurstLen;             /*!< SDH write burst len */
+} SDH_Cfg_Type;
+
+/**
+ *  @brief SDH config structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type enableAutoCommand12; /*!< SDH enable auto CMD12 */
+    BL_Fun_Type enableAutoCommand23; /*!< SDH enable auto CMD23 */
+    BL_Fun_Type enableIgnoreError;   /*!< SDH enable to ignore error event to read/write all the data */
+    SDH_Trans_Data_Type dataType;    /*!< SDH this is used to distinguish the normal/tuning/boot data */
+    uint32_t blockSize;              /*!< SDH block size */
+    uint32_t blockCount;             /*!< SDH block count */
+    uint32_t rxDataLen;              /*!< SDH RX data length */
+    uint32_t *rxData;                /*!< SDH buffer to save data read */
+    const uint32_t *txData;          /*!< SDH data buffer to write */
+    uint32_t txDataLen;              /*!< SDH TX data length */
+} SDH_Data_Cfg_Type;
+
+/**
+ *  @brief SDH command config structure type definition
+ */
+typedef struct
+{
+    uint32_t index;         /*!< SDH command index */
+    uint32_t argument;      /*!< SDH command argument */
+    SDH_Cmd_Type type;      /*!< SDH command type */
+    SDH_Resp_Type respType; /*!< SDH command response type */
+    uint32_t response[4U];  /*!< SDH response for this command */
+    uint32_t flag;          /*!< SDH cmd flag */
+} SDH_CMD_Cfg_Type;
+
+/**
+ *  @brief SDH DMA config structure type definition
+ */
+typedef struct
+{
+    SDH_DMA_Mode_Type dmaMode; /*!< SDH DMA mode */
+    //SDH_Burst_Type burstType;               /*!< SDH burst type config */
+    SDH_Burst_Size_Type burstSize;         /*!< SDH DMA burst size type */
+    SDH_FIFO_Threshold_Type fifoThreshold; /*!< SDH FIFO threshold */
+    uint32_t *admaEntries;                 /*!< SDH ADMA table entries address */
+    uint32_t maxEntries;                   /*!< SDH ADMA table entries size */
+} SDH_DMA_Cfg_Type;
+
+/**
+ *  @brief SDH transfer config structure type definition
+ */
+typedef struct
+{
+    SDH_Data_Cfg_Type *dataCfg; /*!< SDH data config */
+    SDH_CMD_Cfg_Type *cmdCfg;   /*!< SDH command config */
+} SDH_Trans_Cfg_Type;
+
+typedef struct SDH_Handle_Cfg_Tag SDH_Handle_Cfg_Type;
+
+/**
+ *  @brief SDH transfer callback function config structure type definition
+ */
+typedef struct
+{
+    void (*SDH_CallBack_CardInserted)(void *userData);                                                           /*!< SDH card inserted occurs when DAT3/CD pin is for card detect */
+    void (*SDH_CallBack_CardRemoved)(void *userData);                                                            /*!< SDH card removed occurs */
+    void (*SDH_CallBack_SdioInterrupt)(void *userData);                                                          /*!< SDH SDIO card interrupt occurs */
+    void (*SDH_CallBack_BlockGap)(void *userData);                                                               /*!< SDH stopped at block gap event */
+    void (*SDH_CallBack_TransferFinished)(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData);    /*!< SDH transfer complete callback */
+    void (*SDH_CMDCallBack_TransferFinished)(SDH_Handle_Cfg_Type *handle, SDH_Stat_Type status, void *userData); /*!< SDH transfer complete callback */
+    void (*SDH_CallBack_ReTuning)(void *userData);                                                               /*!< SDH handle the re-tuning */
+    void (*SDH_CallBack_Vendor)(void *userData);                                                                 /*!< SDH handle vendor specified interrupt callback */
+} SDH_Trans_Callback_Cfg_Type;
+
+struct SDH_Handle_Cfg_Tag {
+    SDH_Data_Cfg_Type *dataCfg;           /*!< SDH data config to transfer */
+    SDH_CMD_Cfg_Type *cmdCfg;             /*!< SDH command config to transfer */
+    uint32_t intFlag;                     /*!< SDH interrupt flags of last transaction */
+    SDH_Trans_Callback_Cfg_Type callBack; /*!< SDH callback function */
+    void *userData;                       /*!< SDH parameter for transfer complete callback */
+};
+
+/*@} end of group SDH_Public_Types */
+
+/** @defgroup  SDH_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  SDH_STAT_TYPE
+ *  @{
+ */
+#define IS_SDH_STAT_TYPE(type) (((type) == SDH_STAT_SUCCESS) ||            \
+                                ((type) == SDH_STAT_BUSY) ||               \
+                                ((type) == SDH_STAT_INVLAID_PARA) ||       \
+                                ((type) == SDH_STAT_NOT_SUPPORT) ||        \
+                                ((type) == SDH_STAT_OUTOF_RANGE) ||        \
+                                ((type) == SDH_STAT_PREPARE_DESC) ||       \
+                                ((type) == SDH_STAT_SEND_CMD_FAIL) ||      \
+                                ((type) == SDH_STAT_SEND_DATA_FAIL) ||     \
+                                ((type) == SDH_STAT_RECV_DATA_FAIL) ||     \
+                                ((type) == SDH_STAT_DMA_ADDR_NOT_ALIGN) || \
+                                ((type) == SDH_STAT_RETUNE_REQ) ||         \
+                                ((type) == SDH_STAT_TUNE_ERROR))
+
+/** @defgroup  SDH_CAP_SUPPORT_TYPE
+ *  @{
+ */
+#define IS_SDH_CAP_SUPPORT_TYPE(type) (((type) == SDH_CAP_SUPPORT_8BITS) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_ADMA2) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_ADMA1) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_HIGHSPEED) ||   \
+                                       ((type) == SDH_CAP_SUPPORT_SDMA) ||        \
+                                       ((type) == SDH_CAP_SUPPORT_SUS_RES) ||     \
+                                       ((type) == SDH_CAP_SUPPORT_VLT33) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_VLT30) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_VLT18) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_SBUS_64BITS) || \
+                                       ((type) == SDH_CAP_SUPPORT_ASYNC_INT) ||   \
+                                       ((type) == SDH_CAP_SUPPORT_DDR50) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_SDR104) ||      \
+                                       ((type) == SDH_CAP_SUPPORT_SDR50) ||       \
+                                       ((type) == SDH_CAP_SUPPORT_DRV_TYPE_A) ||  \
+                                       ((type) == SDH_CAP_SUPPORT_DRV_TYPE_C) ||  \
+                                       ((type) == SDH_CAP_SUPPORT_DRV_TYPE_D) ||  \
+                                       ((type) == SDH_CAP_SUPPORT_SDR50_TUNE))
+
+/** @defgroup  SDH_WAKEUP_EVENT_TYPE
+ *  @{
+ */
+#define IS_SDH_WAKEUP_EVENT_TYPE(type) (((type) == SDH_WAKEUP_EVENT_INT) ||    \
+                                        ((type) == SDH_WAKEUP_EVENT_INSERT) || \
+                                        ((type) == SDH_WAKEUP_EVENT_REMOVE))
+
+/** @defgroup  SDH_TRANS_FLAG_TYPE
+ *  @{
+ */
+#define IS_SDH_TRANS_FLAG_TYPE(type) (((type) == SDH_TRANS_FLAG_EN_DMA) ||                \
+                                      ((type) == SDH_TRANS_FLAG_EN_BLK_COUNT) ||          \
+                                      ((type) == SDH_TRANS_FLAG_EN_AUTO_CMD12) ||         \
+                                      ((type) == SDH_TRANS_FLAG_EN_AUTO_CMD23) ||         \
+                                      ((type) == SDH_TRANS_FLAG_READ_DATA) ||             \
+                                      ((type) == SDH_TRANS_FLAG_MULTI_BLK) ||             \
+                                      ((type) == SDH_TRANS_FLAG_RESP_136BITS) ||          \
+                                      ((type) == SDH_TRANS_FLAG_RESP_48BITS) ||           \
+                                      ((type) == SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY) || \
+                                      ((type) == SDH_TRANS_FLAG_EN_CRC_CHECK) ||          \
+                                      ((type) == SDH_TRANS_FLAG_EN_INDEX_CHECK) ||        \
+                                      ((type) == SDH_TRANS_FLAG_DATA_PRESENT) ||          \
+                                      ((type) == SDH_TRANS_FLAG_SUSPEND) ||               \
+                                      ((type) == SDH_TRANS_FLAG_RESUME) ||                \
+                                      ((type) == SDH_TRANS_FLAG_ABORT))
+
+/** @defgroup  SDH_PRESENT_FLAG_TYPE
+ *  @{
+ */
+#define IS_SDH_PRESENT_FLAG_TYPE(type) (((type) == SDH_PRESENT_FLAG_CMD_INHBIT) ||       \
+                                        ((type) == SDH_PRESENT_FLAG_DATA_INHBIT) ||      \
+                                        ((type) == SDH_PRESENT_FLAG_DATA_LINE_ACTIVE) || \
+                                        ((type) == SDH_PRESENT_FLAG_RETUNE_REQ) ||       \
+                                        ((type) == SDH_PRESENT_FLAG_TX_ACTIVE) ||        \
+                                        ((type) == SDH_PRESENT_FLAG_RX_ACTIVE) ||        \
+                                        ((type) == SDH_PRESENT_FLAG_BUF_WRITE_ENABLE) || \
+                                        ((type) == SDH_PRESENT_FLAG_BUF_READ_ENABLE) ||  \
+                                        ((type) == SDH_PRESENT_FLAG_CARD_INSERT) ||      \
+                                        ((type) == SDH_PRESENT_FLAG_CARD_STABLE) ||      \
+                                        ((type) == SDH_PRESENT_FLAG_CARD_DET) ||         \
+                                        ((type) == SDH_PRESENT_FLAG_CARD_WP) ||          \
+                                        ((type) == SDH_PRESENT_FLAG_DATA0_LINE_LEVEL) || \
+                                        ((type) == SDH_PRESENT_FLAG_DATA1_LINE_LEVEL) || \
+                                        ((type) == SDH_PRESENT_FLAG_DATA2_LINE_LEVEL) || \
+                                        ((type) == SDH_PRESENT_FLAG_DATA3_LINE_LEVEL) || \
+                                        ((type) == SDH_PRESENT_FLAG_CMD_LINE_LEVEL))
+
+/** @defgroup  SDH_INT_TYPE
+ *  @{
+ */
+#define IS_SDH_INT_TYPE(type) (((type) == SDH_INT_CMD_COMPLETED) ||      \
+                               ((type) == SDH_INT_DATA_COMPLETED) ||     \
+                               ((type) == SDH_INT_BLK_GAP_EVENT) ||      \
+                               ((type) == SDH_INT_DMA_COMPLETED) ||      \
+                               ((type) == SDH_INT_BUFFER_WRITE_READY) || \
+                               ((type) == SDH_INT_BUFFER_READ_READY) ||  \
+                               ((type) == SDH_INT_CARD_INSERT) ||        \
+                               ((type) == SDH_INT_CARD_REMOVE) ||        \
+                               ((type) == SDH_INT_CARD) ||               \
+                               ((type) == SDH_INT_DRIVER_TA) ||          \
+                               ((type) == SDH_INT_DRIVER_TB) ||          \
+                               ((type) == SDH_INT_DRIVER_TC) ||          \
+                               ((type) == SDH_INT_RETUNE_EVENT) ||       \
+                               ((type) == SDH_INT_CMD_TIMEOUT) ||        \
+                               ((type) == SDH_INT_CMD_CRC_ERROR) ||      \
+                               ((type) == SDH_INT_CMD_ENDBIT_ERROR) ||   \
+                               ((type) == SDH_INT_CMD_INDEX_ERROR) ||    \
+                               ((type) == SDH_INT_DATA_TIMEOUT) ||       \
+                               ((type) == SDH_INT_DATA_CRC_ERROR) ||     \
+                               ((type) == SDH_INT_DATA_ENDBIT_ERROR) ||  \
+                               ((type) == SDH_INT_CURRENT_ERROR) ||      \
+                               ((type) == SDH_INT_AUTO_CMD12_ERROR) ||   \
+                               ((type) == SDH_INT_DMA_ERROR) ||          \
+                               ((type) == SDH_INT_TUNE_ERROR) ||         \
+                               ((type) == SDH_INT_SPI_ERROR) ||          \
+                               ((type) == SDH_INT_AXI_RESP_ERROR) ||     \
+                               ((type) == SDH_INT_CPL_TIMEOUT_ERROR) ||  \
+                               ((type) == SDH_INT_CRC_STAT_ERROR) ||     \
+                               ((type) == SDH_INT_CMD_ERRORS) ||         \
+                               ((type) == SDH_INT_DATA_ERRORS) ||        \
+                               ((type) == SDH_INT_ALL))
+
+/** @defgroup  SDH_BOOT_MODE_TYPE
+ *  @{
+ */
+#define IS_SDH_BOOT_MODE_TYPE(type) (((type) == SDH_BOOT_MODE_NORMAL) || \
+                                     ((type) == SDH_BOOT_MODE_ALT))
+
+/** @defgroup  SDH_AUTO_CMD12_ERR_TYPE
+ *  @{
+ */
+#define IS_SDH_AUTO_CMD12_ERR_TYPE(type) (((type) == SDH_AUTO_CMD12_ERR_NOT_EXE) || \
+                                          ((type) == SDH_AUTO_CMD12_ERR_TIMEOUT) || \
+                                          ((type) == SDH_AUTO_CMD12_ERR_ENDBIT) ||  \
+                                          ((type) == SDH_AUTO_CMD12_ERR_INDEX) ||   \
+                                          ((type) == SDH_AUTO_CMD12_ERR_CRC) ||     \
+                                          ((type) == SDH_AUTO_CMD12_ERR_NOT_ISSUE))
+
+/** @defgroup  SDH_ADMA_ERR_TYPE
+ *  @{
+ */
+#define IS_SDH_ADMA_ERR_TYPE(type) (((type) == SDH_ADMA_ERR_LEN_MISMATCH) || \
+                                    ((type) == SDH_ADMA_ERR_DESC_ERROR))
+
+/** @defgroup  SDH_ADMA_ERR_STAT_TYPE
+ *  @{
+ */
+#define IS_SDH_ADMA_ERR_STAT_TYPE(type) (((type) == SDH_ADMA_ERR_STAT_STOP_DMA) ||    \
+                                         ((type) == SDH_ADMA_ERR_STAT_FETCH_DESC) ||  \
+                                         ((type) == SDH_ADMA_ERR_STAT_CHANGE_ADDR) || \
+                                         ((type) == SDH_ADMA_ERR_STAT_TRANS_DATA) ||  \
+                                         ((type) == SDH_ADMA_ERR_STAT_INVALID_LEN) || \
+                                         ((type) == SDH_ADMA_ERR_STAT_INVALID_DESC))
+
+/** @defgroup  SDH_FORCE_EVENT_TYPE
+ *  @{
+ */
+#define IS_SDH_FORCE_EVENT_TYPE(type) (((type) == SDH_FORCE_EVENT_AUTO_CMD12_NOT_EXE) ||     \
+                                       ((type) == SDH_FORCE_EVENT_AUTO_CMD12_TIMEOUT) ||     \
+                                       ((type) == SDH_FORCE_EVENT_AUTO_CMD12_CRC_ERROR) ||   \
+                                       ((type) == SDH_FORCE_EVENT_AUTO_CMD12_INDEX_ERROR) || \
+                                       ((type) == SDH_FORCE_EVENT_AUTO_CMD12_NOT_ISSUE) ||   \
+                                       ((type) == SDH_FORCE_EVENT_ENDBIT_ERROR) ||           \
+                                       ((type) == SDH_FORCE_EVENT_CMD_TIMEOUT) ||            \
+                                       ((type) == SDH_FORCE_EVENT_CMD_CRC_ERROR) ||          \
+                                       ((type) == SDH_FORCE_EVENT_CMD_ENDBIT_ERROR) ||       \
+                                       ((type) == SDH_FORCE_EVENT_CMD_INDEX_ERROR) ||        \
+                                       ((type) == SDH_FORCE_EVENT_DATA_TIMEOUT) ||           \
+                                       ((type) == SDH_FORCE_EVENT_DATA_CRC_ERROR) ||         \
+                                       ((type) == SDH_FORCE_EVENT_DATA_ENDBIT_ERROR) ||      \
+                                       ((type) == SDH_FORCE_EVENT_DATA_INDEX_ERROR) ||       \
+                                       ((type) == SDH_FORCE_EVENT_AUTO_CMD12_ERROR) ||       \
+                                       ((type) == SDH_FORCE_EVENT_CARD_INT) ||               \
+                                       ((type) == SDH_FORCE_EVENT_DMA_ERROR))
+
+/** @defgroup  SDH_SPEED_MODE_TYPE
+ *  @{
+ */
+#define IS_SDH_SPEED_MODE_TYPE(type) (((type) == SDH_SPEED_MODE_SDR12) ||  \
+                                      ((type) == SDH_SPEED_MODE_SDR25) ||  \
+                                      ((type) == SDH_SPEED_MODE_SDR50) ||  \
+                                      ((type) == SDH_SPEED_MODE_SDR104) || \
+                                      ((type) == SDH_SPEED_MODE_DDR50))
+
+/** @defgroup  SDH_DATA_BUS_WIDTH_TYPE
+ *  @{
+ */
+#define IS_SDH_DATA_BUS_WIDTH_TYPE(type) (((type) == SDH_DATA_BUS_WIDTH_1BIT) ||  \
+                                          ((type) == SDH_DATA_BUS_WIDTH_4BITS) || \
+                                          ((type) == SDH_DATA_BUS_WIDTH_8BITS))
+
+/** @defgroup  SDH_VOLTAGE_TYPE
+ *  @{
+ */
+#define IS_SDH_VOLTAGE_TYPE(type) (((type) == SDH_VOLTAGE_3P3V) || \
+                                   ((type) == SDH_VOLTAGE_3P0V) || \
+                                   ((type) == SDH_VOLTAGE_1P8V))
+
+/** @defgroup  SDH_DMA_MODE_TYPE
+ *  @{
+ */
+#define IS_SDH_DMA_MODE_TYPE(type) (((type) == SDH_DMA_MODE_SIMPLE) || \
+                                    ((type) == SDH_DMA_MODE_ADMA1) ||  \
+                                    ((type) == SDH_DMA_MODE_ADMA2))
+
+/** @defgroup  SDH_CTRL_FLAG_TYPE
+ *  @{
+ */
+#define IS_SDH_CTRL_FLAG_TYPE(type) (((type) == SDH_CTRL_FLAG_STOP_AT_BLK_GAP) ||         \
+                                     ((type) == SDH_CTRL_FLAG_READ_WAIT) ||               \
+                                     ((type) == SDH_CTRL_FLAG_INT_AT_BLK_GAP) ||          \
+                                     ((type) == SDH_CTRL_FLAG_RAED_DONE_WITHOUT_8CLKS) || \
+                                     ((type) == SDH_CTRL_FLAG_EXACT_BLK_NUM_READ))
+
+/** @defgroup  SDH_CMD_TYPE
+ *  @{
+ */
+#define IS_SDH_CMD_TYPE(type) (((type) == SDH_CMD_NORMAL) ||  \
+                               ((type) == SDH_CMD_SUSPEND) || \
+                               ((type) == SDH_CMD_RESUME) ||  \
+                               ((type) == SDH_CMD_ABORT) ||   \
+                               ((type) == SDH_CMD_EMPTY))
+
+/** @defgroup  SDH_RESP_TYPE
+ *  @{
+ */
+#define IS_SDH_RESP_TYPE(type) (((type) == SDH_RESP_NONE) || \
+                                ((type) == SDH_RESP_R1) ||   \
+                                ((type) == SDH_RESP_R1B) ||  \
+                                ((type) == SDH_RESP_R2) ||   \
+                                ((type) == SDH_RESP_R3) ||   \
+                                ((type) == SDH_RESP_R4) ||   \
+                                ((type) == SDH_RESP_R5) ||   \
+                                ((type) == SDH_RESP_R5B) ||  \
+                                ((type) == SDH_RESP_R6) ||   \
+                                ((type) == SDH_RESP_R7))
+
+/** @defgroup  SDH_ADMA_FLAG_TYPE
+ *  @{
+ */
+#define IS_SDH_ADMA_FLAG_TYPE(type) (((type) == SDH_ADMA_FLAG_SINGLE_DESC) || \
+                                     ((type) == SDH_ADMA_FLAG_MULTI_DESC))
+
+/** @defgroup  SDH_ADMA1_DESC_FLAG_TYPE
+ *  @{
+ */
+#define IS_SDH_ADMA1_DESC_FLAG_TYPE(type) (((type) == SDH_ADMA1_DESC_FLAG_VALID) ||    \
+                                           ((type) == SDH_ADMA1_DESC_FLAG_END) ||      \
+                                           ((type) == SDH_ADMA1_DESC_FLAG_INT) ||      \
+                                           ((type) == SDH_ADMA1_DESC_FLAG_ACTIVE1) ||  \
+                                           ((type) == SDH_ADMA1_DESC_FLAG_ACTIVE2) ||  \
+                                           ((type) == SDH_ADMA1_DESC_FLAG_TRANSFER) || \
+                                           ((type) == SDH_ADMA1_DESC_FLAG_LINK) ||     \
+                                           ((type) == SDH_ADMA1_DESC_FLAG_SETLEN))
+
+/** @defgroup  SDH_ADMA2_DESC_FLAG_TYPE
+ *  @{
+ */
+#define IS_SDH_ADMA2_DESC_FLAG_TYPE(type) (((type) == SDH_ADMA2_DESC_FLAG_VALID) ||    \
+                                           ((type) == SDH_ADMA2_DESC_FLAG_END) ||      \
+                                           ((type) == SDH_ADMA2_DESC_FLAG_INT) ||      \
+                                           ((type) == SDH_ADMA2_DESC_FLAG_ACTIVE1) ||  \
+                                           ((type) == SDH_ADMA2_DESC_FLAG_ACTIVE2) ||  \
+                                           ((type) == SDH_ADMA2_DESC_FLAG_TRANSFER) || \
+                                           ((type) == SDH_ADMA2_DESC_FLAG_LINK))
+
+/** @defgroup  SDH_BURST_TYPE
+ *  @{
+ */
+#define IS_SDH_BURST_TYPE(type) (((type) == SDH_BUSRT_INCR) ||  \
+                                 ((type) == SDH_BUSRT_INCR4) || \
+                                 ((type) == SDH_BUSRT_WRAP4))
+
+/** @defgroup  SDH_FIFO_THRESHOLD_TYPE
+ *  @{
+ */
+#define IS_SDH_FIFO_THRESHOLD_TYPE(type) (((type) == SDH_FIFO_THRESHOLD_64_BYTES) ||  \
+                                          ((type) == SDH_FIFO_THRESHOLD_128_BYTES) || \
+                                          ((type) == SDH_FIFO_THRESHOLD_192_BYTES) || \
+                                          ((type) == SDH_FIFO_THRESHOLD_256_BYTES))
+
+/** @defgroup  SDH_BURST_SIZE_TYPE
+ *  @{
+ */
+#define IS_SDH_BURST_SIZE_TYPE(type) (((type) == SDH_BURST_SIZE_32_BYTES) ||  \
+                                      ((type) == SDH_BURST_SIZE_64_BYTES) ||  \
+                                      ((type) == SDH_BURST_SIZE_128_BYTES) || \
+                                      ((type) == SDH_BURST_SIZE_256_BYTES))
+
+/** @defgroup  SDH_TRANS_DATA_TYPE
+ *  @{
+ */
+#define IS_SDH_TRANS_DATA_TYPE(type) (((type) == SDH_TRANS_DATA_NORMAL) || \
+                                      ((type) == SDH_TRANS_DATA_TUNING) || \
+                                      ((type) == SDH_TRANS_DATA_BOOT) ||   \
+                                      ((type) == SDH_TRANS_DATA_BOOT_CONT))
+
+/*@} end of group SDH_Public_Constants */
+
+/** @defgroup  SDH_Public_Macros
+ *  @{
+ */
+/* The alignment size for ADDRESS filed in SDMA */
+#define SDH_SDMA_ADDRESS_ALIGN (1U)
+/* The alignment size for LENGTH field in SDMA */
+#define SDH_SDMA_LENGTH_ALIGN (1U)
+/* The alignment size for ADDRESS filed in ADMA1's descriptor */
+#define SDH_ADMA1_ADDRESS_ALIGN (4096U)
+/* The alignment size for ADDRESS field in ADMA2's descriptor */
+#define SDH_ADMA2_ADDRESS_ALIGN (1U)
+/* The alignment size for LENGTH filed in ADMA2's descriptor */
+#define SDH_ADMA2_LENGTH_ALIGN (1U)
+/* ADMA1 descriptor table
+* |------------------------|---------|--------------------------|
+* | Address/page field     |Reserved |         Attribute        |
+* |------------------------|---------|--------------------------|
+* |31                    12|11      6|05  |04  |03|02 |01 |00   |
+* |------------------------|---------|----|----|--|---|---|-----|
+* | address or data length | 000000  |Act2|Act1| 0|Int|End|Valid|
+* |------------------------|---------|----|----|--|---|---|-----|
+*
+*
+* |------|------|-----------------|-------|-------------|
+* | Act2 | Act1 |     Comment     | 31-28 | 27 - 12     |
+* |------|------|-----------------|---------------------|
+* |   0  |   0  | No op           | Don't care          |
+* |------|------|-----------------|-------|-------------|
+* |   0  |   1  | Set data length |  0000 | Data Length |
+* |------|------|-----------------|-------|-------------|
+* |   1  |   0  | Transfer data   | Data address        |
+* |------|------|-----------------|---------------------|
+* |   1  |   1  | Link descriptor | Descriptor address  |
+* |------|------|-----------------|---------------------|
+*/
+/* The bit shift for ADDRESS filed in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_ADDRESS_POS (12U)
+/* The bit mask for ADDRESS field in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_ADDRESS_MASK (0xFFFFFU)
+/* The bit shift for LENGTH filed in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_LENGTH_POS (12U)
+/* The mask for LENGTH field in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
+/* The maximum value of LENGTH filed in ADMA1's descriptor */
+#define SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDH_ADMA1_DESCRIPTOR_LENGTH_MASK - 3U)
+/* ADMA2 descriptor table
+* |----------------|---------------|-------------|--------------------------|
+* | Address field  |     Length    | Reserved    |         Attribute        |
+* |----------------|---------------|-------------|--------------------------|
+* |63            32|31           16|15         06|05  |04  |03|02 |01 |00   |
+* |----------------|---------------|-------------|----|----|--|---|---|-----|
+* | 32-bit address | 16-bit length | 0000000000  |Act2|Act1| 0|Int|End|Valid|
+* |----------------|---------------|-------------|----|----|--|---|---|-----|
+*
+*
+* | Act2 | Act1 |     Comment     | Operation                                                         |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* |   0  |   0  | No op           | Don't care                                                        |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* |   0  |   1  | Reserved        | Read this line and go to next one                                 |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* |   1  |   0  | Transfer data   | Transfer data with address and length set in this descriptor line |
+* |------|------|-----------------|-------------------------------------------------------------------|
+* |   1  |   1  | Link descriptor | Link to another descriptor                                        |
+* |------|------|-----------------|-------------------------------------------------------------------|
+*/
+/* The bit shift for LENGTH field in ADMA2's descriptor */
+#define SDH_ADMA2_DESCRIPTOR_LENGTH_POS (16U)
+/* The bit mask for LENGTH field in ADMA2's descriptor */
+#define SDH_ADMA2_DESCRIPTOR_LENGTH_MASK (0xFFFFU)
+/* The maximum value of LENGTH field in ADMA2's descriptor */
+#define SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY (SDH_ADMA2_DESCRIPTOR_LENGTH_MASK - 3U)
+#define SDH_EnableIntStatus(mask)                                             \
+    do {                                                                      \
+        BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN,                      \
+                  BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN) | (mask)); \
+    } while (0)
+#define SDH_DisableIntStatus(mask)                                               \
+    do {                                                                         \
+        BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN,                         \
+                  BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_EN) & (~(mask))); \
+    } while (0)
+#define SDH_EnableIntSource(mask)                                                 \
+    do {                                                                          \
+        BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN,                      \
+                  BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN) | (mask)); \
+    } while (0)
+#define SDH_DisableIntSource(mask)                                                   \
+    do {                                                                             \
+        BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN,                         \
+                  BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN) & (~(mask))); \
+    } while (0)
+#define SDH_GetIntStatus()       BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS);
+#define SDH_GetIntEnableStatus() BL_RD_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS_INT_EN);
+#define SDH_ClearIntStatus(mask) BL_WR_REG(SDH_BASE, SDH_SD_NORMAL_INT_STATUS, (mask));
+#define SDH_AutoCmd12ErrStatus() BL_RD_SHORT(SDH_BASE + SDH_SD_AUTO_CMD12_ERROR_STATUS_OFFSET);
+#define SDH_GetDMAErrStatus()    BL_RD_SHORT(SDH_BASE + SDH_SD_ADMA_ERROR_STATUS_OFFSET);
+#define SDH_GetPresentStatus()   BL_RD_REG(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+#define SDH_MAX_BLOCK_COUNT      0xffff
+//#define SDH_CMD_INDEX(x)                    (x)
+
+/*@} end of group SDH_Public_Macros */
+
+/** @defgroup  SDH_Public_Functions
+ *  @{
+ */
+void SDH_MMC1_IRQHandler(void);
+
+void SDH_Reset(void);
+void SDH_Set_Timeout(uint8_t tmo);
+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);
+void SDH_ITConfig(uint32_t SDH_IT_FLAG, BL_Fun_Type NewState);
+void SDH_Ctrl_Init(const SDH_Cfg_Type *cfg);
+void SDH_Powon(void);
+void SDH_SendCommand(SDH_CMD_Cfg_Type *cmd);
+void SDH_DisableDMA(void);
+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);
+SDH_Stat_Type SDH_GetCmdResp(SDH_CMD_Cfg_Type *cmd);
+uint32_t SDH_ReadDataPort(SDH_Data_Cfg_Type *dataCfg);
+SDH_Stat_Type SDH_WaitCommandDone(SDH_CMD_Cfg_Type *cmd);
+SDH_Stat_Type SDH_ConfigDataTranfer(SDH_Data_Cfg_Type *dataCfg);
+SDH_Stat_Type SDH_TransferDataBlocking(SDH_Data_Cfg_Type *dataCfg, uint8_t enDMA);
+SDH_Stat_Type SDH_TransferBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer);
+SDH_Stat_Type SDH_TransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer);
+void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle, const SDH_Trans_Callback_Cfg_Type *callBack, void *userData);
+void SDH_EnableDMA(SDH_DMA_Mode_Type dmaMode);
+void SDH_EnableStatus(void);
+SDH_Stat_Type SDH_ReadDataPortBlock(SDH_Data_Cfg_Type *dataCfg);
+uint32_t SDH_WriteDataPort(SDH_Data_Cfg_Type *dataCfg);
+SDH_Stat_Type SDH_WriteDataPortBlock(SDH_Data_Cfg_Type *dataCfg);
+void SDH_DisableSdClock(void);
+void SDH_Deinit(void);
+void SDH_GetCapability(SDH_Cap_Cfg_Type *capability);
+SDH_Stat_Type SDH_CreateADMA1Descriptor(uint32_t *adma1Entries, uint32_t maxEntries,
+                                        const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag);
+SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint32_t maxEntries,
+                                        const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag);
+SDH_Stat_Type SDH_SetInternalDmaConfig(SDH_DMA_Cfg_Type *dmaCfg, const uint32_t *data, uint8_t enAutoCmd23);
+SDH_Stat_Type SDH_CreateAdmaEntryConfig(SDH_DMA_Cfg_Type *dmaCfg, SDH_Data_Cfg_Type *dataCfg, SDH_ADMA_Flag_Type flag);
+/*@} end of group SDH_Public_Functions */
+
+/*@} end of group SDH */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_SDH_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdu.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdu.h
new file mode 100755
index 0000000000..426f80ec97
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_sdu.h
@@ -0,0 +1,194 @@
+#ifndef __BL616_SDU_H__
+#define __BL616_SDU_H__
+
+#include "bl616.h"
+#include "bl616_common.h"
+
+#define NUM_FUNC         1        
+#define FUNC_WIFI        0  
+
+// SDIO I/O Enable
+#define BL_SDIO_IO_ENABLE           SDU_BASE + 0x00000002 
+//CCCR (Fn0) Registers
+
+// SDIO Device Sleep
+#define BL_SDIO_DEV_SLEEP           SDU_BASE + 0x00000092
+
+// Start Address of CCR
+#define BL_SDIO_CCR_BASE            SDU_BASE + 0x00000100
+// Address offset of CCR between two functions
+#define BL_SDIO_CCR_FUNC_OFFSET     0x00000100
+
+
+// Address for sdio block size information
+#define SDIO_FN1_BLK_SIZE_0        (SDU_BASE + 0x00000028)
+#define SDIO_FN1_BLK_SIZE_1        (SDU_BASE + 0x00000029)
+#define SDIO_FN1_BLK_SIZE_1_MASK   0x01
+
+#define BL_FUNC_SCRATCH_BASE       SDU_BASE + 0x00000160
+
+typedef struct
+{
+    uint8_t   HostToCardEvent;   // 0x100/200
+    uint8_t   HostIntCause;      // 0x101/201
+    uint8_t   HostIntMask;       // 0x102/202
+    uint8_t   HostIntStatus;     // 0x103/203
+    uint16_t  RdBitMap;          // 0x104/204
+    uint16_t  WrBitMap;          // 0x106/206
+    uint16_t  RdLen[16];         // 0x108/208
+    uint8_t   HostTransferStatus;// 0x128/228
+    uint8_t   reserved1[0x130-0x128-1];
+    uint8_t   CardToHostEvent;   // 0x130/230
+    uint8_t   reserved2[3];
+    uint8_t   CardIntMask;       // 0x134/234
+    uint8_t   reserved3[3];
+    uint8_t   CardIntStatus;     // 0x138/238
+    uint8_t   reserved4[3];
+    uint8_t   CardIntMode;       // 0x13C/23C
+    uint8_t   reserved5[3];
+    uint32_t  SqReadBase;        // 0x140/240
+    uint32_t  SqWriteBase;       // 0x144/244
+    uint8_t   RdIdx;             // 0x148/248
+    uint8_t   WrIdx;             // 0x149/249
+    uint8_t   DnldQueueWrPtr;    // 0x14A/24A
+    uint8_t   UpldQueueWrPtr;    // 0x14B/24B
+    uint8_t   DnldQueue[8];      // 0x14C/24C
+    uint8_t   UpldQueue[8];      // 0x154/254
+    uint8_t   ChipRev;           // 0x15C      //RO
+    uint8_t   reserved6;         // 0x15D      //NOT_DEFINE
+    uint8_t   IPRev0;            // 0x15E      //RO
+    uint8_t   IPRev1;            // 0x15F      //RO
+    uint8_t   reserved7[4];      // 0x160/260
+    uint16_t  Scratch2;          // 0x164/264
+    uint16_t  Scratch1;          // 0x166/266
+    uint8_t   Ocr0;              // 0x168/268
+    uint8_t   Ocr1;              // 0x169/269
+    uint8_t   Ocr2;              // 0x16A/26A
+    uint8_t   Config;            // 0x16B/26B
+    uint32_t  Config2;           // 0x16C/26C
+    uint32_t  Debug;             // 0x170/270
+    uint32_t  DmaAddr;           // 0x174/274
+    uint8_t   IoPort[3];         // 0x178/278
+} __attribute__((packed)) HidSdio_RegMap_t, *pHidSdio_RegMap_t;
+
+// Common I/O Area Registers (CIA) Offset
+//
+// Bit Def. Host To Card Interrupt Event (Offset 0x100/200)
+#define SDIO_HCR_CONFIG_HostPwrUp               (1<<1)
+
+// Bit Def. Host Transfer Status (Offset 0x128/228)
+#define SDIO_CCR_HOST_INT_DnLdReStart           (1<<0)
+#define SDIO_CCR_HOST_INT_UpLdReStart           (1<<1)
+#define SDIO_CCR_HOST_INT_DnLdCRC_err           (1<<2)
+
+// Bit Def. Card To Host Interrupt Event (Offset 0x130/230)
+#define SDIO_CCR_CS_DnLdRdy                     (1<<0)
+#define SDIO_CCR_CS_UpLdRdy                     (1<<1)
+#define SDIO_CCR_CS_ReadCISRdy                  (1<<2)
+#define SDIO_CCR_CS_IORdy                       (1<<3)
+
+
+// Bit Def. Card Interrupt Mask (Offset 0x134/234)
+#define SDIO_CCR_CIM_DnLdOvr                    (1<<0)
+#define SDIO_CCR_CIM_UpLdOvr                    (1<<1)
+#define SDIO_CCR_CIM_Abort                      (1<<2)
+#define SDIO_CCR_CIM_PwrDn                      (1<<3)
+#define SDIO_CCR_CIM_PwrUp                      (1<<4)
+
+#define SDIO_CCR_CIM_MASK                       0x0007
+
+
+// Bit Def. Card Interrupt Status (Offset 0x138/238)
+#define SDIO_CCR_CIC_DnLdOvr                    (1<<0)
+#define SDIO_CCR_CIC_UpLdOvr                    (1<<1)
+#define SDIO_CCR_CIC_Abort                      (1<<2)
+#define SDIO_CCR_CIC_PwrDn                      (1<<3)
+#define SDIO_CCR_CIC_PwrUp                      (1<<4)
+
+
+
+#define SDIO_CCR_CIC_MASK                       0x001F
+
+// Bit Def. Card Interrupt RSR (Offset 0x13C/23C)
+#define SDIO_CCR_CIO_DnLdOvr                    (1<<0)
+#define SDIO_CCR_CIO_UpLdOvr                    (1<<1)
+#define SDIO_CCR_CIO_Abort                      (1<<2)
+#define SDIO_CCR_CIO_PwrDn                      (1<<3)
+#define SDIO_CCR_CIO_PwrUp                      (1<<4)
+#define SDIO_CCR_CIO_MASK                       0x001F
+
+
+//Config2 register mask
+#define CONFIG2_MSK                             0x00000C00
+
+
+//CardIntMode register mask
+
+#define CARD_INT_MODE_MSK                       0x00000003
+#define HOST_INT_MSK                            0x00000002
+
+//=============================================================================
+//                                PUBLIC MACROS
+//=============================================================================
+
+#define BL_REGS8(x)     (*(volatile unsigned char *)(x))
+#define BL_REGS16(x)    (*(volatile unsigned short *)(x))
+#define BL_REGS32(x)    (*(volatile unsigned long *)(x))
+
+#define BL_READ_REGS8(reg,val)      ((val) = BL_REGS8(reg))
+#define BL_READ_REGS16(reg,val)     ((val) = BL_REGS16(reg))
+#define BL_READ_REGS32(reg,val)     ((val) = BL_REGS32(reg))
+#define BL_READ_BYTE(reg,val)       ((val) = BL_REGS8(reg))
+#define BL_READ_HWORD(reg,val)      ((val) = BL_REGS16(reg)) /*half word; */
+#define BL_READ_WORD(reg,val)       ((val) = BL_REGS32(reg)) /*32 bits */
+
+#define BL_WRITE_REGS8(reg,val)     (BL_REGS8(reg) = (val))
+#define BL_WRITE_REGS16(reg,val)    (BL_REGS16(reg) = (val))
+#define BL_WRITE_REGS32(reg,val)    (BL_REGS32(reg) = (val))
+#define BL_WRITE_BYTE(reg,val)      (BL_REGS8(reg) = (val))
+#define BL_WRITE_HWORD(reg,val)     (BL_REGS16(reg) = (val))  /*half word; */
+#define BL_WRITE_WORD(reg,val)      (BL_REGS32(reg) = (val))  /*32 bits */
+// Write uint32 to a low 16-bit register and a high 16-bit register
+#define WRITE2REGS(lo,hi,u32) \
+    BL_WRITE_HWORD(lo, (uint16_t)((u32) & 0xffff)); \
+    BL_WRITE_HWORD(hi, (uint16_t)(((u32) >> 16) & 0xffff))
+
+#define BL_REGS8_SETBITS(reg, val)  (BL_REGS8(reg) |= (uint8)(val))
+#define BL_REGS16_SETBITS(reg, val) (BL_REGS16(reg) |= (uint16)(val))
+#define BL_REGS32_SETBITS(reg, val) (BL_REGS32(reg) |= (val))
+#define BL_REGS8_CLRBITS(reg, val)  (BL_REGS8(reg) = (uint8)(BL_REGS8(reg)&~(val)))
+#define BL_REGS16_CLRBITS(reg, val) (BL_REGS16(reg) = (uint16)(BL_REGS16(reg)&~(val)))
+#define BL_REGS32_CLRBITS(reg, val) (BL_REGS32(reg) = (BL_REGS32(reg)&~(val)))
+
+//=============================================================================
+//                                ENUM TYPE DEFINITION
+//=============================================================================
+
+/******************************************************************/
+/*!
+ *  \enum SDIO_CMD_TYPE
+ *
+ *******************************************************************/
+typedef enum
+{
+  IOCTL_GET_CONFIG = 0,         /*!< Get configuration info */
+
+
+ /* HID IOCTLs*/
+  IOCTL_HID_GET_BLOCK_SIZE,		/*!< Get Block size */
+
+} SDIO_CMD_TYPE;
+
+//=============================================================================
+//                                FUNCTION DECLARATION
+//=============================================================================
+extern void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value);
+extern uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg);
+
+//=============================================================================
+//                                Variable DECLARATION
+//=============================================================================
+extern volatile pHidSdio_RegMap_t SdioFuncReg[];
+extern uint8_t flag_mport[];
+#endif /* __BL616_SDU_H__ */
+
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_tzc_sec.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_tzc_sec.h
new file mode 100755
index 0000000000..43af4fa314
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/bl616_tzc_sec.h
@@ -0,0 +1,247 @@
+/**
+  ******************************************************************************
+  * @file    bl616_tzc_sec.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2021 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL616_TZC_SEC_H__
+#define __BL616_TZC_SEC_H__
+
+#include "tzc_sec_reg.h"
+#include "bl616_common.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  TZC_SEC
+ *  @{
+ */
+
+/** @defgroup  TZC_SEC_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief TZC_SEC master type definition
+ */
+typedef enum {
+    TZC_SEC_MASTER_RSVD,  /*!< TZC Master:Reserved */
+    TZC_SEC_MASTER_RSVD1, /*!< TZC Master:Reserved */
+    TZC_SEC_MASTER_USB,   /*!< TZC Master:USB */
+    TZC_SEC_MASTER_WIFI,  /*!< TZC Master:WIFI */
+    TZC_SEC_MASTER_CCI,   /*!< TZC Master:CCI */
+    TZC_SEC_MASTER_SDH,   /*!< TZC Master:SDH */
+    TZC_SEC_MASTER_EMAC,  /*!< TZC Master:EMAC */
+    TZC_SEC_MASTER_M0,    /*!< TZC Master:M0 CPU */
+    TZC_SEC_MASTER_DMA0,  /*!< TZC Master:DMA0 */
+    TZC_SEC_MASTER_RSVD2, /*!< TZC Master:Reserved */
+    TZC_SEC_MASTER_RSVD3, /*!< TZC Master:Reserved */
+    TZC_SEC_MASTER_SDU,   /*!< TZC Master:SDU */
+    TZC_SEC_MASTER_MAX,   /*!< TZC Master max */
+} TZC_SEC_Master_Type;
+
+/**
+ *  @brief TZC_SEC slave type definition
+ */
+typedef enum {
+    TZC_SEC_SLAVE_S0_RSVD,          /*!< TZC Slave:Reserved */
+    TZC_SEC_SLAVE_S0_DMA,           /*!< TZC Slave:DMA */
+    TZC_SEC_SLAVE_S0_RSVD1,         /*!< TZC Slave:Reserved */
+    TZC_SEC_SLAVE_S0_PWR,           /*!< TZC Slave:PWR */
+    TZC_SEC_SLAVE_S0_SDH,           /*!< TZC Slave:SDH */
+    TZC_SEC_SLAVE_S0_EMAC,          /*!< TZC Slave:EMAC */
+    TZC_SEC_SLAVE_S0_SDU,           /*!< TZC Slave:SDU */
+    TZC_SEC_SLAVE_S1_GLB,           /*!< TZC Slave:GLB */
+    TZC_SEC_SLAVE_S1_MIX,           /*!< TZC Slave:MIX */
+    TZC_SEC_SLAVE_S1_GPIP,          /*!< TZC Slave:GPIP */
+    TZC_SEC_SLAVE_S1_DBG,           /*!< TZC Slave:DBG */
+    TZC_SEC_SLAVE_S1_RSVD2,         /*!< TZC Slave:Reserved */
+    TZC_SEC_SLAVE_S1_TZC1,          /*!< TZC Slave:TZC1 */
+    TZC_SEC_SLAVE_S1_TZC2,          /*!< TZC Slave:TZC2 */
+    TZC_SEC_SLAVE_S1_RSVD3,         /*!< TZC Slave:Reserved */
+    TZC_SEC_SLAVE_S1_CCI,           /*!< TZC Slave:CCI */
+    TZC_SEC_SLAVE_S1_MCU_MISC,      /*!< TZC Slave:MCU_MISC */
+    TZC_SEC_SLAVE_S2_EMI_MISC = 23, /*!< TZC Slave:EMI MISC */
+    TZC_SEC_SLAVE_S2_RSVD4,         /*!< TZC Slave:Reserved */
+    TZC_SEC_SLAVE_S2_PSRAM0,        /*!< TZC Slave:PSRAM0 */
+    TZC_SEC_SLAVE_S2_USB_HS,        /*!< TZC Slave:USB HS */
+    TZC_SEC_SLAVE_S2_RSVD5,         /*!< TZC Slave:Reserved */
+    TZC_SEC_SLAVE_S2_AUDIO,         /*!< TZC Slave:AUDIO */
+    TZC_SEC_SLAVE_S2_EF_CTRL,       /*!< TZC Slave:efuse control*/
+    TZC_SEC_SLAVE_S2_D2XA,          /*!< TZC Slave:D2XA */
+    TZC_SEC_SLAVE_S2_D2XB,          /*!< TZC Slave:D2XB */
+    TZC_SEC_SLAVE_S2_JENC,          /*!< TZC Slave:JENC */
+    TZC_SEC_SLAVE_S2_PEC,           /*!< TZC Slave:PEC */
+    TZC_SEC_SLAVE_S1A_UART0 = 39,   /*!< TZC Slave:UART0 */
+    TZC_SEC_SLAVE_S1A_UART1,        /*!< TZC Slave:UART1 */
+    TZC_SEC_SLAVE_S1A_SPI,          /*!< TZC Slave:SPI */
+    TZC_SEC_SLAVE_S1A_I2C0,         /*!< TZC Slave:I2C0 */
+    TZC_SEC_SLAVE_S1A_PWM,          /*!< TZC Slave:PWM */
+    TZC_SEC_SLAVE_S1A_TMR,          /*!< TZC Slave:TMR */
+    TZC_SEC_SLAVE_S1A_IRR,          /*!< TZC Slave:IRR */
+    TZC_SEC_SLAVE_S1A_CKS,          /*!< TZC Slave:CKS */
+    TZC_SEC_SLAVE_S1A_DBI,          /*!< TZC Slave:DBI */
+    TZC_SEC_SLAVE_S1A_I2C1,         /*!< TZC Slave:I2C1 */
+    TZC_SEC_SLAVE_S1A_CAN,          /*!< TZC Slave:CAN */
+    TZC_SEC_SLAVE_S1A_I2S,          /*!< TZC Slave:I2S */
+    TZC_SEC_SLAVE_S1A_PDM,          /*!< TZC Slave:PDM */
+    TZC_SEC_SLAVE_S1A_LZ4,          /*!< TZC Slave:LZ4 */
+    TZC_SEC_SLAVE_MAX,              /*!< TZC slave max*/
+} TZC_SEC_Slave_Type;
+
+/**
+ *  @brief TZC_SEC GLB Ctrl type definition
+ */
+typedef enum {
+    TZC_SEC_GLB_CTRL_POR_RESET,  /*!< TZC GLB Ctrl: Power on reset */
+    TZC_SEC_GLB_CTRL_CPU_RESET,  /*!< TZC GLB Ctrl: CPU reset */
+    TZC_SEC_GLB_CTRL_SYS_RESET,  /*!< TZC GLB Ctrl: System reset */
+    TZC_SEC_GLB_CTRL_CCPU_RESET, /*!< TZC GLB Ctrl: CCPU */
+    TZC_SEC_GLB_CTRL_MISC,       /*!< TZC GLB Ctrl: MISC */
+    TZC_SEC_GLB_CTRL_SRAM,       /*!< TZC GLB Ctrl: SRAM */
+    TZC_SEC_GLB_CTRL_SWRESET,    /*!< TZC GLB Ctrl: Software reset */
+    TZC_SEC_GLB_CTRL_BMX,        /*!< TZC GLB Ctrl: BMX */
+    TZC_SEC_GLB_CTRL_DBG,        /*!< TZC GLB Ctrl: DBG */
+    TZC_SEC_GLB_CTRL_MBIST,      /*!< TZC GLB Ctrl: MBIST */
+    TZC_SEC_GLB_CTRL_CLK,        /*!< TZC GLB Ctrl: CLK */
+    TZC_SEC_GLB_CTRL_INT,        /*!< TZC GLB Ctrl: Interrupt */
+    TZC_SEC_GLB_CTRL_PWR,        /*!< TZC GLB Ctrl: Power */
+    TZC_SEC_GLB_CTRL_MAX,
+} TZC_SEC_GLB_Ctrl_Type;
+
+/**
+ *  @brief TZC_SEC SE Ctrl type definition
+ */
+typedef enum {
+    TZC_SEC_SE_CTRL_SHA,  /*!< TZC SE Ctrl: SHA */
+    TZC_SEC_SE_CTRL_AES,  /*!< TZC SE Ctrl: AES */
+    TZC_SEC_SE_CTRL_TRNG, /*!< TZC SE Ctrl: TRNG */
+    TZC_SEC_SE_CTRL_PKA,  /*!< TZC SE Ctrl: PKA */
+    TZC_SEC_SE_CTRL_CDET, /*!< TZC SE Ctrl: CEDT */
+    TZC_SEC_SE_CTRL_GMAC, /*!< TZC SE Ctrl: GMAC */
+    TZC_SEC_SE_CTRL_MAX,
+} TZC_SEC_SE_Ctrl_Type;
+
+/**
+ *  @brief TZC_SEC SF Ctrl type definition
+ */
+typedef enum {
+    TZC_SEC_SF_CTRL_CR,  /*!< TZC SF Ctrl: control register */
+    TZC_SEC_SF_CTRL_SEC, /*!< TZC SF Ctrl: security register */
+    TZC_SEC_SF_CTRL_MAX,
+} TZC_SEC_SF_Ctrl_Type;
+
+/**
+ *  @brief TZC_SEC SE Ctrl mode definition
+ */
+typedef enum {
+    TZC_SEC_SE_MODE_ARB, /*!< TZC SE Ctrl mode: cpus arbitrate */
+    TZC_SEC_SE_MODE_TZC, /*!< TZC SE Ctrl: TZC control as group */
+} TZC_SEC_SE_Ctrl_Mode;
+
+/**
+ *  @brief TZC_SEC SF Ctrl mode definition
+ */
+typedef enum {
+    TZC_SEC_SF_MODE_ARB, /*!< TZC SF Ctrl mode: cpus arbitrate */
+    TZC_SEC_SF_MODE_TZC, /*!< TZC SF Ctrl: TZC control as group */
+} TZC_SEC_SF_Ctrl_Mode;
+
+/**
+ *  @brief TZC_SEC Auth group
+ */
+typedef enum {
+    TZC_SEC_AUTH_GRP_0, /*!< TZC auth group 0 */
+    TZC_SEC_AUTH_GRP_1, /*!< TZC auth group 1 */
+} TZC_SEC_Auth_Group;
+
+/**
+ *  @brief TZC_SEC Advance Auth group
+ */
+typedef enum {
+    TZC_SEC_ADV_AUTH_GRP_0_IBUS = 0x01, /*!< TZC advance auth group 0 IBUS */
+    TZC_SEC_ADV_AUTH_GRP_0_DBUS = 0x02, /*!< TZC advance auth group 0 DBUS */
+    TZC_SEC_ADV_AUTH_GRP_1_IBUS = 0x04, /*!< TZC advance auth group 1 IBUS */
+    TZC_SEC_ADV_AUTH_GRP_1_DBUS = 0x08, /*!< TZC advance auth group 1 DBUS */
+} TZC_SEC_Advance_Auth_Group;
+
+/*@} end of group TZC_SEC_Public_Types */
+
+/** @defgroup  TZC_SEC_Public_Constants
+ *  @{
+ */
+
+/*@} end of group TZC_SEC_Public_Constants */
+
+/** @defgroup  TZC_SEC_Public_Macros
+ *  @{
+ */
+
+#define TZC_SEC_MAX_AUTH_GRP 3
+/*@} end of group TZC_SEC_Public_Macros */
+
+/** @defgroup  TZC_SEC_Public_Functions
+ *  @{
+ */
+void Tzc_Sec_Set_Sboot_Done(void);
+void Tzc_Sec_Set_Bus_Remap(uint8_t busRmpEn);
+void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group);
+void Tzc_Sec_Set_Codec_Group(uint8_t group);
+void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group);
+void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group);
+void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group);
+void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_ROM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group);
+void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group);
+void Tzc_Sec_Flash_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group);
+void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_PSRAMB_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group);
+void Tzc_Sec_PSRAMB_Access_Release(void);
+void Tzc_Sec_HBNRAM_Access_Set(uint32_t startAddr, uint32_t length);
+void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode);
+void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SF_Ctrl_Mode mode);
+void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group);
+void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group);
+void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue);
+/*@} end of group TZC_SEC_Public_Functions */
+
+/*@} end of group TZC_SEC */
+
+/*@} end of group BL616_Peripheral_Driver */
+
+#endif /* __BL616_TZC_SEC_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/aon_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/aon_reg.h
new file mode 100755
index 0000000000..d499374160
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/aon_reg.h
@@ -0,0 +1,1762 @@
+/**
+  ******************************************************************************
+  * @file    aon_reg.h
+  * @version V1.0
+  * @date    2021-11-22
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __AON_REG_H__
+#define __AON_REG_H__
+
+#include "bl616.h"
+
+/* 0x800 : aon */
+#define AON_OFFSET                     (0x800)
+#define AON_RESV                       AON_RESV
+#define AON_RESV_POS                   (0U)
+#define AON_RESV_LEN                   (8U)
+#define AON_RESV_MSK                   (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)
+#define AON_RESV_UMSK                  (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS))
+#define AON_PU_AON_DC_TBUF             AON_PU_AON_DC_TBUF
+#define AON_PU_AON_DC_TBUF_POS         (12U)
+#define AON_PU_AON_DC_TBUF_LEN         (1U)
+#define AON_PU_AON_DC_TBUF_MSK         (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)
+#define AON_PU_AON_DC_TBUF_UMSK        (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS))
+#define AON_LDO11_RT_PULLDOWN          AON_LDO11_RT_PULLDOWN
+#define AON_LDO11_RT_PULLDOWN_POS      (20U)
+#define AON_LDO11_RT_PULLDOWN_LEN      (1U)
+#define AON_LDO11_RT_PULLDOWN_MSK      (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)
+#define AON_LDO11_RT_PULLDOWN_UMSK     (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS))
+#define AON_LDO11_RT_PULLDOWN_SEL      AON_LDO11_RT_PULLDOWN_SEL
+#define AON_LDO11_RT_PULLDOWN_SEL_POS  (21U)
+#define AON_LDO11_RT_PULLDOWN_SEL_LEN  (1U)
+#define AON_LDO11_RT_PULLDOWN_SEL_MSK  (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)
+#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS))
+#define AON_SW_PU_LDO11_RT             AON_SW_PU_LDO11_RT
+#define AON_SW_PU_LDO11_RT_POS         (22U)
+#define AON_SW_PU_LDO11_RT_LEN         (1U)
+#define AON_SW_PU_LDO11_RT_MSK         (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)
+#define AON_SW_PU_LDO11_RT_UMSK        (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS))
+
+/* 0x804 : aon_common */
+#define AON_COMMON_OFFSET         (0x804)
+#define AON_TMUX_AON              AON_TMUX_AON
+#define AON_TMUX_AON_POS          (0U)
+#define AON_TMUX_AON_LEN          (3U)
+#define AON_TMUX_AON_MSK          (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)
+#define AON_TMUX_AON_UMSK         (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS))
+#define AON_TEN_AON               AON_TEN_AON
+#define AON_TEN_AON_POS           (4U)
+#define AON_TEN_AON_LEN           (1U)
+#define AON_TEN_AON_MSK           (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)
+#define AON_TEN_AON_UMSK          (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS))
+#define AON_TEN_VDDCORE_AON       AON_TEN_VDDCORE_AON
+#define AON_TEN_VDDCORE_AON_POS   (8U)
+#define AON_TEN_VDDCORE_AON_LEN   (1U)
+#define AON_TEN_VDDCORE_AON_MSK   (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)
+#define AON_TEN_VDDCORE_AON_UMSK  (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS))
+#define AON_TEN_LDO11SOC_AON      AON_TEN_LDO11SOC_AON
+#define AON_TEN_LDO11SOC_AON_POS  (9U)
+#define AON_TEN_LDO11SOC_AON_LEN  (1U)
+#define AON_TEN_LDO11SOC_AON_MSK  (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)
+#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS))
+#define AON_TEN_DCDC_0_AON        AON_TEN_DCDC_0_AON
+#define AON_TEN_DCDC_0_AON_POS    (10U)
+#define AON_TEN_DCDC_0_AON_LEN    (1U)
+#define AON_TEN_DCDC_0_AON_MSK    (((1U << AON_TEN_DCDC_0_AON_LEN) - 1) << AON_TEN_DCDC_0_AON_POS)
+#define AON_TEN_DCDC_0_AON_UMSK   (~(((1U << AON_TEN_DCDC_0_AON_LEN) - 1) << AON_TEN_DCDC_0_AON_POS))
+#define AON_TEN_DCDC_1_AON        AON_TEN_DCDC_1_AON
+#define AON_TEN_DCDC_1_AON_POS    (11U)
+#define AON_TEN_DCDC_1_AON_LEN    (1U)
+#define AON_TEN_DCDC_1_AON_MSK    (((1U << AON_TEN_DCDC_1_AON_LEN) - 1) << AON_TEN_DCDC_1_AON_POS)
+#define AON_TEN_DCDC_1_AON_UMSK   (~(((1U << AON_TEN_DCDC_1_AON_LEN) - 1) << AON_TEN_DCDC_1_AON_POS))
+#define AON_TEN_BG_SYS_AON        AON_TEN_BG_SYS_AON
+#define AON_TEN_BG_SYS_AON_POS    (12U)
+#define AON_TEN_BG_SYS_AON_LEN    (1U)
+#define AON_TEN_BG_SYS_AON_MSK    (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)
+#define AON_TEN_BG_SYS_AON_UMSK   (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS))
+#define AON_TEN_LDO15RF_AON       AON_TEN_LDO15RF_AON
+#define AON_TEN_LDO15RF_AON_POS   (16U)
+#define AON_TEN_LDO15RF_AON_LEN   (1U)
+#define AON_TEN_LDO15RF_AON_MSK   (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)
+#define AON_TEN_LDO15RF_AON_UMSK  (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS))
+#define AON_TEN_XTAL_AON          AON_TEN_XTAL_AON
+#define AON_TEN_XTAL_AON_POS      (17U)
+#define AON_TEN_XTAL_AON_LEN      (1U)
+#define AON_TEN_XTAL_AON_MSK      (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)
+#define AON_TEN_XTAL_AON_UMSK     (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS))
+#define AON_DTEN_XTAL_AON         AON_DTEN_XTAL_AON
+#define AON_DTEN_XTAL_AON_POS     (18U)
+#define AON_DTEN_XTAL_AON_LEN     (1U)
+#define AON_DTEN_XTAL_AON_MSK     (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)
+#define AON_DTEN_XTAL_AON_UMSK    (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS))
+#define AON_TEN_MBG_AON           AON_TEN_MBG_AON
+#define AON_TEN_MBG_AON_POS       (19U)
+#define AON_TEN_MBG_AON_LEN       (1U)
+#define AON_TEN_MBG_AON_MSK       (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)
+#define AON_TEN_MBG_AON_UMSK      (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS))
+#define AON_TEN_CIP_MISC_AON      AON_TEN_CIP_MISC_AON
+#define AON_TEN_CIP_MISC_AON_POS  (20U)
+#define AON_TEN_CIP_MISC_AON_LEN  (1U)
+#define AON_TEN_CIP_MISC_AON_MSK  (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)
+#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS))
+
+/* 0x808 : aon_misc */
+#define AON_MISC_OFFSET        (0x808)
+#define AON_SW_SOC_EN_AON      AON_SW_SOC_EN_AON
+#define AON_SW_SOC_EN_AON_POS  (0U)
+#define AON_SW_SOC_EN_AON_LEN  (1U)
+#define AON_SW_SOC_EN_AON_MSK  (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)
+#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS))
+#define AON_SW_WB_EN_AON       AON_SW_WB_EN_AON
+#define AON_SW_WB_EN_AON_POS   (1U)
+#define AON_SW_WB_EN_AON_LEN   (1U)
+#define AON_SW_WB_EN_AON_MSK   (((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS)
+#define AON_SW_WB_EN_AON_UMSK  (~(((1U << AON_SW_WB_EN_AON_LEN) - 1) << AON_SW_WB_EN_AON_POS))
+
+/* 0x810 : bg_sys_top */
+#define AON_BG_SYS_TOP_OFFSET    (0x810)
+#define AON_PU_BG_SYS_AON        AON_PU_BG_SYS_AON
+#define AON_PU_BG_SYS_AON_POS    (0U)
+#define AON_PU_BG_SYS_AON_LEN    (1U)
+#define AON_PU_BG_SYS_AON_MSK    (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)
+#define AON_PU_BG_SYS_AON_UMSK   (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS))
+#define AON_ISTART_CTRL_AON      AON_ISTART_CTRL_AON
+#define AON_ISTART_CTRL_AON_POS  (1U)
+#define AON_ISTART_CTRL_AON_LEN  (1U)
+#define AON_ISTART_CTRL_AON_MSK  (((1U << AON_ISTART_CTRL_AON_LEN) - 1) << AON_ISTART_CTRL_AON_POS)
+#define AON_ISTART_CTRL_AON_UMSK (~(((1U << AON_ISTART_CTRL_AON_LEN) - 1) << AON_ISTART_CTRL_AON_POS))
+#define AON_PMIP_RESV_AON        AON_PMIP_RESV_AON
+#define AON_PMIP_RESV_AON_POS    (8U)
+#define AON_PMIP_RESV_AON_LEN    (8U)
+#define AON_PMIP_RESV_AON_MSK    (((1U << AON_PMIP_RESV_AON_LEN) - 1) << AON_PMIP_RESV_AON_POS)
+#define AON_PMIP_RESV_AON_UMSK   (~(((1U << AON_PMIP_RESV_AON_LEN) - 1) << AON_PMIP_RESV_AON_POS))
+
+/* 0x814 : dcdc_top_0 */
+#define AON_DCDC_TOP_0_OFFSET               (0x814)
+#define AON_DCDC_VOUT_SEL_AON               AON_DCDC_VOUT_SEL_AON
+#define AON_DCDC_VOUT_SEL_AON_POS           (0U)
+#define AON_DCDC_VOUT_SEL_AON_LEN           (5U)
+#define AON_DCDC_VOUT_SEL_AON_MSK           (((1U << AON_DCDC_VOUT_SEL_AON_LEN) - 1) << AON_DCDC_VOUT_SEL_AON_POS)
+#define AON_DCDC_VOUT_SEL_AON_UMSK          (~(((1U << AON_DCDC_VOUT_SEL_AON_LEN) - 1) << AON_DCDC_VOUT_SEL_AON_POS))
+#define AON_DCDC_VPFM_AON                   AON_DCDC_VPFM_AON
+#define AON_DCDC_VPFM_AON_POS               (8U)
+#define AON_DCDC_VPFM_AON_LEN               (4U)
+#define AON_DCDC_VPFM_AON_MSK               (((1U << AON_DCDC_VPFM_AON_LEN) - 1) << AON_DCDC_VPFM_AON_POS)
+#define AON_DCDC_VPFM_AON_UMSK              (~(((1U << AON_DCDC_VPFM_AON_LEN) - 1) << AON_DCDC_VPFM_AON_POS))
+#define AON_DCDC_OSC_2M_MODE_AON            AON_DCDC_OSC_2M_MODE_AON
+#define AON_DCDC_OSC_2M_MODE_AON_POS        (12U)
+#define AON_DCDC_OSC_2M_MODE_AON_LEN        (1U)
+#define AON_DCDC_OSC_2M_MODE_AON_MSK        (((1U << AON_DCDC_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC_OSC_2M_MODE_AON_POS)
+#define AON_DCDC_OSC_2M_MODE_AON_UMSK       (~(((1U << AON_DCDC_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC_OSC_2M_MODE_AON_POS))
+#define AON_DCDC_OSC_FREQ_TRIM_AON          AON_DCDC_OSC_FREQ_TRIM_AON
+#define AON_DCDC_OSC_FREQ_TRIM_AON_POS      (16U)
+#define AON_DCDC_OSC_FREQ_TRIM_AON_LEN      (4U)
+#define AON_DCDC_OSC_FREQ_TRIM_AON_MSK      (((1U << AON_DCDC_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC_OSC_FREQ_TRIM_AON_POS)
+#define AON_DCDC_OSC_FREQ_TRIM_AON_UMSK     (~(((1U << AON_DCDC_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC_OSC_FREQ_TRIM_AON_POS))
+#define AON_DCDC_SLOPE_CURR_SEL_AON         AON_DCDC_SLOPE_CURR_SEL_AON
+#define AON_DCDC_SLOPE_CURR_SEL_AON_POS     (20U)
+#define AON_DCDC_SLOPE_CURR_SEL_AON_LEN     (5U)
+#define AON_DCDC_SLOPE_CURR_SEL_AON_MSK     (((1U << AON_DCDC_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC_SLOPE_CURR_SEL_AON_POS)
+#define AON_DCDC_SLOPE_CURR_SEL_AON_UMSK    (~(((1U << AON_DCDC_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC_SLOPE_CURR_SEL_AON_POS))
+#define AON_DCDC_EN_STOP_OSC_AON            AON_DCDC_EN_STOP_OSC_AON
+#define AON_DCDC_EN_STOP_OSC_AON_POS        (25U)
+#define AON_DCDC_EN_STOP_OSC_AON_LEN        (1U)
+#define AON_DCDC_EN_STOP_OSC_AON_MSK        (((1U << AON_DCDC_EN_STOP_OSC_AON_LEN) - 1) << AON_DCDC_EN_STOP_OSC_AON_POS)
+#define AON_DCDC_EN_STOP_OSC_AON_UMSK       (~(((1U << AON_DCDC_EN_STOP_OSC_AON_LEN) - 1) << AON_DCDC_EN_STOP_OSC_AON_POS))
+#define AON_DCDC_EN_SLOW_OSC_AON            AON_DCDC_EN_SLOW_OSC_AON
+#define AON_DCDC_EN_SLOW_OSC_AON_POS        (26U)
+#define AON_DCDC_EN_SLOW_OSC_AON_LEN        (1U)
+#define AON_DCDC_EN_SLOW_OSC_AON_MSK        (((1U << AON_DCDC_EN_SLOW_OSC_AON_LEN) - 1) << AON_DCDC_EN_SLOW_OSC_AON_POS)
+#define AON_DCDC_EN_SLOW_OSC_AON_UMSK       (~(((1U << AON_DCDC_EN_SLOW_OSC_AON_LEN) - 1) << AON_DCDC_EN_SLOW_OSC_AON_POS))
+#define AON_DCDC_EN_OSC_INHIBIT_T2_AON      AON_DCDC_EN_OSC_INHIBIT_T2_AON
+#define AON_DCDC_EN_OSC_INHIBIT_T2_AON_POS  (27U)
+#define AON_DCDC_EN_OSC_INHIBIT_T2_AON_LEN  (1U)
+#define AON_DCDC_EN_OSC_INHIBIT_T2_AON_MSK  (((1U << AON_DCDC_EN_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC_EN_OSC_INHIBIT_T2_AON_POS)
+#define AON_DCDC_EN_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC_EN_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC_EN_OSC_INHIBIT_T2_AON_POS))
+#define AON_DCDC_SSTART_TIME_AON            AON_DCDC_SSTART_TIME_AON
+#define AON_DCDC_SSTART_TIME_AON_POS        (28U)
+#define AON_DCDC_SSTART_TIME_AON_LEN        (2U)
+#define AON_DCDC_SSTART_TIME_AON_MSK        (((1U << AON_DCDC_SSTART_TIME_AON_LEN) - 1) << AON_DCDC_SSTART_TIME_AON_POS)
+#define AON_DCDC_SSTART_TIME_AON_UMSK       (~(((1U << AON_DCDC_SSTART_TIME_AON_LEN) - 1) << AON_DCDC_SSTART_TIME_AON_POS))
+#define AON_DCDC_DIS_AON                    AON_DCDC_DIS_AON
+#define AON_DCDC_DIS_AON_POS                (30U)
+#define AON_DCDC_DIS_AON_LEN                (1U)
+#define AON_DCDC_DIS_AON_MSK                (((1U << AON_DCDC_DIS_AON_LEN) - 1) << AON_DCDC_DIS_AON_POS)
+#define AON_DCDC_DIS_AON_UMSK               (~(((1U << AON_DCDC_DIS_AON_LEN) - 1) << AON_DCDC_DIS_AON_POS))
+#define AON_DCDC_RDY_AON                    AON_DCDC_RDY_AON
+#define AON_DCDC_RDY_AON_POS                (31U)
+#define AON_DCDC_RDY_AON_LEN                (1U)
+#define AON_DCDC_RDY_AON_MSK                (((1U << AON_DCDC_RDY_AON_LEN) - 1) << AON_DCDC_RDY_AON_POS)
+#define AON_DCDC_RDY_AON_UMSK               (~(((1U << AON_DCDC_RDY_AON_LEN) - 1) << AON_DCDC_RDY_AON_POS))
+
+/* 0x818 : dcdc_top_1 */
+#define AON_DCDC_TOP_1_OFFSET             (0x818)
+#define AON_DCDC_FORCE_EN_CS_ZVS_AON      AON_DCDC_FORCE_EN_CS_ZVS_AON
+#define AON_DCDC_FORCE_EN_CS_ZVS_AON_POS  (0U)
+#define AON_DCDC_FORCE_EN_CS_ZVS_AON_LEN  (1U)
+#define AON_DCDC_FORCE_EN_CS_ZVS_AON_MSK  (((1U << AON_DCDC_FORCE_EN_CS_ZVS_AON_LEN) - 1) << AON_DCDC_FORCE_EN_CS_ZVS_AON_POS)
+#define AON_DCDC_FORCE_EN_CS_ZVS_AON_UMSK (~(((1U << AON_DCDC_FORCE_EN_CS_ZVS_AON_LEN) - 1) << AON_DCDC_FORCE_EN_CS_ZVS_AON_POS))
+#define AON_DCDC_CS_DELAY_AON             AON_DCDC_CS_DELAY_AON
+#define AON_DCDC_CS_DELAY_AON_POS         (1U)
+#define AON_DCDC_CS_DELAY_AON_LEN         (3U)
+#define AON_DCDC_CS_DELAY_AON_MSK         (((1U << AON_DCDC_CS_DELAY_AON_LEN) - 1) << AON_DCDC_CS_DELAY_AON_POS)
+#define AON_DCDC_CS_DELAY_AON_UMSK        (~(((1U << AON_DCDC_CS_DELAY_AON_LEN) - 1) << AON_DCDC_CS_DELAY_AON_POS))
+#define AON_DCDC_ZVS_TD_OPT_AON           AON_DCDC_ZVS_TD_OPT_AON
+#define AON_DCDC_ZVS_TD_OPT_AON_POS       (4U)
+#define AON_DCDC_ZVS_TD_OPT_AON_LEN       (3U)
+#define AON_DCDC_ZVS_TD_OPT_AON_MSK       (((1U << AON_DCDC_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC_ZVS_TD_OPT_AON_POS)
+#define AON_DCDC_ZVS_TD_OPT_AON_UMSK      (~(((1U << AON_DCDC_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC_ZVS_TD_OPT_AON_POS))
+#define AON_DCDC_NONOVERLAP_TD_AON        AON_DCDC_NONOVERLAP_TD_AON
+#define AON_DCDC_NONOVERLAP_TD_AON_POS    (8U)
+#define AON_DCDC_NONOVERLAP_TD_AON_LEN    (5U)
+#define AON_DCDC_NONOVERLAP_TD_AON_MSK    (((1U << AON_DCDC_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC_NONOVERLAP_TD_AON_POS)
+#define AON_DCDC_NONOVERLAP_TD_AON_UMSK   (~(((1U << AON_DCDC_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC_NONOVERLAP_TD_AON_POS))
+#define AON_DCDC_RC_SEL_AON               AON_DCDC_RC_SEL_AON
+#define AON_DCDC_RC_SEL_AON_POS           (16U)
+#define AON_DCDC_RC_SEL_AON_LEN           (4U)
+#define AON_DCDC_RC_SEL_AON_MSK           (((1U << AON_DCDC_RC_SEL_AON_LEN) - 1) << AON_DCDC_RC_SEL_AON_POS)
+#define AON_DCDC_RC_SEL_AON_UMSK          (~(((1U << AON_DCDC_RC_SEL_AON_LEN) - 1) << AON_DCDC_RC_SEL_AON_POS))
+#define AON_DCDC_CHF_SEL_AON              AON_DCDC_CHF_SEL_AON
+#define AON_DCDC_CHF_SEL_AON_POS          (20U)
+#define AON_DCDC_CHF_SEL_AON_LEN          (4U)
+#define AON_DCDC_CHF_SEL_AON_MSK          (((1U << AON_DCDC_CHF_SEL_AON_LEN) - 1) << AON_DCDC_CHF_SEL_AON_POS)
+#define AON_DCDC_CHF_SEL_AON_UMSK         (~(((1U << AON_DCDC_CHF_SEL_AON_LEN) - 1) << AON_DCDC_CHF_SEL_AON_POS))
+#define AON_DCDC_CFB_SEL_AON              AON_DCDC_CFB_SEL_AON
+#define AON_DCDC_CFB_SEL_AON_POS          (24U)
+#define AON_DCDC_CFB_SEL_AON_LEN          (4U)
+#define AON_DCDC_CFB_SEL_AON_MSK          (((1U << AON_DCDC_CFB_SEL_AON_LEN) - 1) << AON_DCDC_CFB_SEL_AON_POS)
+#define AON_DCDC_CFB_SEL_AON_UMSK         (~(((1U << AON_DCDC_CFB_SEL_AON_LEN) - 1) << AON_DCDC_CFB_SEL_AON_POS))
+#define AON_DCDC_EN_ANTIRING_AON          AON_DCDC_EN_ANTIRING_AON
+#define AON_DCDC_EN_ANTIRING_AON_POS      (28U)
+#define AON_DCDC_EN_ANTIRING_AON_LEN      (1U)
+#define AON_DCDC_EN_ANTIRING_AON_MSK      (((1U << AON_DCDC_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC_EN_ANTIRING_AON_POS)
+#define AON_DCDC_EN_ANTIRING_AON_UMSK     (~(((1U << AON_DCDC_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC_EN_ANTIRING_AON_POS))
+#define AON_DCDC_PULLDOWN_AON             AON_DCDC_PULLDOWN_AON
+#define AON_DCDC_PULLDOWN_AON_POS         (29U)
+#define AON_DCDC_PULLDOWN_AON_LEN         (1U)
+#define AON_DCDC_PULLDOWN_AON_MSK         (((1U << AON_DCDC_PULLDOWN_AON_LEN) - 1) << AON_DCDC_PULLDOWN_AON_POS)
+#define AON_DCDC_PULLDOWN_AON_UMSK        (~(((1U << AON_DCDC_PULLDOWN_AON_LEN) - 1) << AON_DCDC_PULLDOWN_AON_POS))
+
+/* 0x81C : ldo11soc_and_dctest */
+#define AON_LDO11SOC_AND_DCTEST_OFFSET     (0x81C)
+#define AON_LDO11SOC_VOUT_TRIM_AON         AON_LDO11SOC_VOUT_TRIM_AON
+#define AON_LDO11SOC_VOUT_TRIM_AON_POS     (0U)
+#define AON_LDO11SOC_VOUT_TRIM_AON_LEN     (4U)
+#define AON_LDO11SOC_VOUT_TRIM_AON_MSK     (((1U << AON_LDO11SOC_VOUT_TRIM_AON_LEN) - 1) << AON_LDO11SOC_VOUT_TRIM_AON_POS)
+#define AON_LDO11SOC_VOUT_TRIM_AON_UMSK    (~(((1U << AON_LDO11SOC_VOUT_TRIM_AON_LEN) - 1) << AON_LDO11SOC_VOUT_TRIM_AON_POS))
+#define AON_PU_LDO11SOC_AON                AON_PU_LDO11SOC_AON
+#define AON_PU_LDO11SOC_AON_POS            (4U)
+#define AON_PU_LDO11SOC_AON_LEN            (1U)
+#define AON_PU_LDO11SOC_AON_MSK            (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)
+#define AON_PU_LDO11SOC_AON_UMSK           (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS))
+#define AON_LDO11SOC_SSTART_EN_AON         AON_LDO11SOC_SSTART_EN_AON
+#define AON_LDO11SOC_SSTART_EN_AON_POS     (5U)
+#define AON_LDO11SOC_SSTART_EN_AON_LEN     (1U)
+#define AON_LDO11SOC_SSTART_EN_AON_MSK     (((1U << AON_LDO11SOC_SSTART_EN_AON_LEN) - 1) << AON_LDO11SOC_SSTART_EN_AON_POS)
+#define AON_LDO11SOC_SSTART_EN_AON_UMSK    (~(((1U << AON_LDO11SOC_SSTART_EN_AON_LEN) - 1) << AON_LDO11SOC_SSTART_EN_AON_POS))
+#define AON_LDO11SOC_SSTART_DELAY_AON      AON_LDO11SOC_SSTART_DELAY_AON
+#define AON_LDO11SOC_SSTART_DELAY_AON_POS  (8U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_MSK  (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)
+#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_AON          AON_LDO11SOC_PULLDOWN_AON
+#define AON_LDO11SOC_PULLDOWN_AON_POS      (10U)
+#define AON_LDO11SOC_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO11SOC_PULLDOWN_AON_MSK      (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_SEL_AON      AON_LDO11SOC_PULLDOWN_SEL_AON
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS  (11U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS))
+#define AON_LDO11SOC_VTH_SEL_AON           AON_LDO11SOC_VTH_SEL_AON
+#define AON_LDO11SOC_VTH_SEL_AON_POS       (12U)
+#define AON_LDO11SOC_VTH_SEL_AON_LEN       (2U)
+#define AON_LDO11SOC_VTH_SEL_AON_MSK       (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)
+#define AON_LDO11SOC_VTH_SEL_AON_UMSK      (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS))
+#define AON_LDO11SOC_CC_AON                AON_LDO11SOC_CC_AON
+#define AON_LDO11SOC_CC_AON_POS            (24U)
+#define AON_LDO11SOC_CC_AON_LEN            (2U)
+#define AON_LDO11SOC_CC_AON_MSK            (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)
+#define AON_LDO11SOC_CC_AON_UMSK           (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS))
+#define AON_LDO11SOC_RDY_AON               AON_LDO11SOC_RDY_AON
+#define AON_LDO11SOC_RDY_AON_POS           (28U)
+#define AON_LDO11SOC_RDY_AON_LEN           (1U)
+#define AON_LDO11SOC_RDY_AON_MSK           (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)
+#define AON_LDO11SOC_RDY_AON_UMSK          (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS))
+#define AON_LDO11SOC_POWER_GOOD_AON        AON_LDO11SOC_POWER_GOOD_AON
+#define AON_LDO11SOC_POWER_GOOD_AON_POS    (29U)
+#define AON_LDO11SOC_POWER_GOOD_AON_LEN    (1U)
+#define AON_LDO11SOC_POWER_GOOD_AON_MSK    (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)
+#define AON_LDO11SOC_POWER_GOOD_AON_UMSK   (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS))
+#define AON_PMIP_DC_TP_OUT_EN_AON          AON_PMIP_DC_TP_OUT_EN_AON
+#define AON_PMIP_DC_TP_OUT_EN_AON_POS      (31U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_LEN      (1U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_MSK      (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)
+#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK     (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS))
+
+/* 0x820 : psw_irrcv */
+#define AON_PSW_IRRCV_OFFSET   (0x820)
+#define AON_PU_IR_PSW_AON      AON_PU_IR_PSW_AON
+#define AON_PU_IR_PSW_AON_POS  (0U)
+#define AON_PU_IR_PSW_AON_LEN  (1U)
+#define AON_PU_IR_PSW_AON_MSK  (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)
+#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS))
+
+/* 0x824 : dcdc_top_2 */
+#define AON_DCDC_TOP_2_OFFSET           (0x824)
+#define AON_DCDC_VOUT_TRIM_AON          AON_DCDC_VOUT_TRIM_AON
+#define AON_DCDC_VOUT_TRIM_AON_POS      (0U)
+#define AON_DCDC_VOUT_TRIM_AON_LEN      (4U)
+#define AON_DCDC_VOUT_TRIM_AON_MSK      (((1U << AON_DCDC_VOUT_TRIM_AON_LEN) - 1) << AON_DCDC_VOUT_TRIM_AON_POS)
+#define AON_DCDC_VOUT_TRIM_AON_UMSK     (~(((1U << AON_DCDC_VOUT_TRIM_AON_LEN) - 1) << AON_DCDC_VOUT_TRIM_AON_POS))
+#define AON_DCDC_OSC_SS_RSTN_AON        AON_DCDC_OSC_SS_RSTN_AON
+#define AON_DCDC_OSC_SS_RSTN_AON_POS    (4U)
+#define AON_DCDC_OSC_SS_RSTN_AON_LEN    (1U)
+#define AON_DCDC_OSC_SS_RSTN_AON_MSK    (((1U << AON_DCDC_OSC_SS_RSTN_AON_LEN) - 1) << AON_DCDC_OSC_SS_RSTN_AON_POS)
+#define AON_DCDC_OSC_SS_RSTN_AON_UMSK   (~(((1U << AON_DCDC_OSC_SS_RSTN_AON_LEN) - 1) << AON_DCDC_OSC_SS_RSTN_AON_POS))
+#define AON_DCDC_OSC_SS_EN_AON          AON_DCDC_OSC_SS_EN_AON
+#define AON_DCDC_OSC_SS_EN_AON_POS      (5U)
+#define AON_DCDC_OSC_SS_EN_AON_LEN      (1U)
+#define AON_DCDC_OSC_SS_EN_AON_MSK      (((1U << AON_DCDC_OSC_SS_EN_AON_LEN) - 1) << AON_DCDC_OSC_SS_EN_AON_POS)
+#define AON_DCDC_OSC_SS_EN_AON_UMSK     (~(((1U << AON_DCDC_OSC_SS_EN_AON_LEN) - 1) << AON_DCDC_OSC_SS_EN_AON_POS))
+#define AON_DCDC_OSC_SS_PERIOD_AON      AON_DCDC_OSC_SS_PERIOD_AON
+#define AON_DCDC_OSC_SS_PERIOD_AON_POS  (8U)
+#define AON_DCDC_OSC_SS_PERIOD_AON_LEN  (2U)
+#define AON_DCDC_OSC_SS_PERIOD_AON_MSK  (((1U << AON_DCDC_OSC_SS_PERIOD_AON_LEN) - 1) << AON_DCDC_OSC_SS_PERIOD_AON_POS)
+#define AON_DCDC_OSC_SS_PERIOD_AON_UMSK (~(((1U << AON_DCDC_OSC_SS_PERIOD_AON_LEN) - 1) << AON_DCDC_OSC_SS_PERIOD_AON_POS))
+#define AON_DCDC_OSC_SS_FDEV_AON        AON_DCDC_OSC_SS_FDEV_AON
+#define AON_DCDC_OSC_SS_FDEV_AON_POS    (10U)
+#define AON_DCDC_OSC_SS_FDEV_AON_LEN    (2U)
+#define AON_DCDC_OSC_SS_FDEV_AON_MSK    (((1U << AON_DCDC_OSC_SS_FDEV_AON_LEN) - 1) << AON_DCDC_OSC_SS_FDEV_AON_POS)
+#define AON_DCDC_OSC_SS_FDEV_AON_UMSK   (~(((1U << AON_DCDC_OSC_SS_FDEV_AON_LEN) - 1) << AON_DCDC_OSC_SS_FDEV_AON_POS))
+#define AON_DCDC_COMP_GM_SEL_AON        AON_DCDC_COMP_GM_SEL_AON
+#define AON_DCDC_COMP_GM_SEL_AON_POS    (12U)
+#define AON_DCDC_COMP_GM_SEL_AON_LEN    (3U)
+#define AON_DCDC_COMP_GM_SEL_AON_MSK    (((1U << AON_DCDC_COMP_GM_SEL_AON_LEN) - 1) << AON_DCDC_COMP_GM_SEL_AON_POS)
+#define AON_DCDC_COMP_GM_SEL_AON_UMSK   (~(((1U << AON_DCDC_COMP_GM_SEL_AON_LEN) - 1) << AON_DCDC_COMP_GM_SEL_AON_POS))
+#define AON_DCDC_ISENSE_TRIM_AON        AON_DCDC_ISENSE_TRIM_AON
+#define AON_DCDC_ISENSE_TRIM_AON_POS    (16U)
+#define AON_DCDC_ISENSE_TRIM_AON_LEN    (3U)
+#define AON_DCDC_ISENSE_TRIM_AON_MSK    (((1U << AON_DCDC_ISENSE_TRIM_AON_LEN) - 1) << AON_DCDC_ISENSE_TRIM_AON_POS)
+#define AON_DCDC_ISENSE_TRIM_AON_UMSK   (~(((1U << AON_DCDC_ISENSE_TRIM_AON_LEN) - 1) << AON_DCDC_ISENSE_TRIM_AON_POS))
+#define AON_DCDC_VC_CLAMP_VTH_AON       AON_DCDC_VC_CLAMP_VTH_AON
+#define AON_DCDC_VC_CLAMP_VTH_AON_POS   (20U)
+#define AON_DCDC_VC_CLAMP_VTH_AON_LEN   (3U)
+#define AON_DCDC_VC_CLAMP_VTH_AON_MSK   (((1U << AON_DCDC_VC_CLAMP_VTH_AON_LEN) - 1) << AON_DCDC_VC_CLAMP_VTH_AON_POS)
+#define AON_DCDC_VC_CLAMP_VTH_AON_UMSK  (~(((1U << AON_DCDC_VC_CLAMP_VTH_AON_LEN) - 1) << AON_DCDC_VC_CLAMP_VTH_AON_POS))
+#define AON_DCDC_OCP_VTH_AON            AON_DCDC_OCP_VTH_AON
+#define AON_DCDC_OCP_VTH_AON_POS        (24U)
+#define AON_DCDC_OCP_VTH_AON_LEN        (3U)
+#define AON_DCDC_OCP_VTH_AON_MSK        (((1U << AON_DCDC_OCP_VTH_AON_LEN) - 1) << AON_DCDC_OCP_VTH_AON_POS)
+#define AON_DCDC_OCP_VTH_AON_UMSK       (~(((1U << AON_DCDC_OCP_VTH_AON_LEN) - 1) << AON_DCDC_OCP_VTH_AON_POS))
+#define AON_DCDC_OCP_RST_AON            AON_DCDC_OCP_RST_AON
+#define AON_DCDC_OCP_RST_AON_POS        (27U)
+#define AON_DCDC_OCP_RST_AON_LEN        (1U)
+#define AON_DCDC_OCP_RST_AON_MSK        (((1U << AON_DCDC_OCP_RST_AON_LEN) - 1) << AON_DCDC_OCP_RST_AON_POS)
+#define AON_DCDC_OCP_RST_AON_UMSK       (~(((1U << AON_DCDC_OCP_RST_AON_LEN) - 1) << AON_DCDC_OCP_RST_AON_POS))
+#define AON_DCDC_OCP_OUT_AON            AON_DCDC_OCP_OUT_AON
+#define AON_DCDC_OCP_OUT_AON_POS        (28U)
+#define AON_DCDC_OCP_OUT_AON_LEN        (1U)
+#define AON_DCDC_OCP_OUT_AON_MSK        (((1U << AON_DCDC_OCP_OUT_AON_LEN) - 1) << AON_DCDC_OCP_OUT_AON_POS)
+#define AON_DCDC_OCP_OUT_AON_UMSK       (~(((1U << AON_DCDC_OCP_OUT_AON_LEN) - 1) << AON_DCDC_OCP_OUT_AON_POS))
+#define AON_DCDC_DRV_SR_AON             AON_DCDC_DRV_SR_AON
+#define AON_DCDC_DRV_SR_AON_POS         (29U)
+#define AON_DCDC_DRV_SR_AON_LEN         (2U)
+#define AON_DCDC_DRV_SR_AON_MSK         (((1U << AON_DCDC_DRV_SR_AON_LEN) - 1) << AON_DCDC_DRV_SR_AON_POS)
+#define AON_DCDC_DRV_SR_AON_UMSK        (~(((1U << AON_DCDC_DRV_SR_AON_LEN) - 1) << AON_DCDC_DRV_SR_AON_POS))
+
+/* 0x828 : vddcore_psw */
+#define AON_VDDCORE_PSW_OFFSET (0x828)
+
+/* 0x82C : psw_misc */
+#define AON_PSW_MISC_OFFSET            (0x82C)
+#define AON_PU_PSW_IRRCV_AON           AON_PU_PSW_IRRCV_AON
+#define AON_PU_PSW_IRRCV_AON_POS       (0U)
+#define AON_PU_PSW_IRRCV_AON_LEN       (1U)
+#define AON_PU_PSW_IRRCV_AON_MSK       (((1U << AON_PU_PSW_IRRCV_AON_LEN) - 1) << AON_PU_PSW_IRRCV_AON_POS)
+#define AON_PU_PSW_IRRCV_AON_UMSK      (~(((1U << AON_PU_PSW_IRRCV_AON_LEN) - 1) << AON_PU_PSW_IRRCV_AON_POS))
+#define AON_USB20_RREF_EXT_EN_AON      AON_USB20_RREF_EXT_EN_AON
+#define AON_USB20_RREF_EXT_EN_AON_POS  (19U)
+#define AON_USB20_RREF_EXT_EN_AON_LEN  (1U)
+#define AON_USB20_RREF_EXT_EN_AON_MSK  (((1U << AON_USB20_RREF_EXT_EN_AON_LEN) - 1) << AON_USB20_RREF_EXT_EN_AON_POS)
+#define AON_USB20_RREF_EXT_EN_AON_UMSK (~(((1U << AON_USB20_RREF_EXT_EN_AON_LEN) - 1) << AON_USB20_RREF_EXT_EN_AON_POS))
+#define AON_EN_POR33_AON               AON_EN_POR33_AON
+#define AON_EN_POR33_AON_POS           (20U)
+#define AON_EN_POR33_AON_LEN           (1U)
+#define AON_EN_POR33_AON_MSK           (((1U << AON_EN_POR33_AON_LEN) - 1) << AON_EN_POR33_AON_POS)
+#define AON_EN_POR33_AON_UMSK          (~(((1U << AON_EN_POR33_AON_LEN) - 1) << AON_EN_POR33_AON_POS))
+#define AON_USB20_RREF_HIZ_AON         AON_USB20_RREF_HIZ_AON
+#define AON_USB20_RREF_HIZ_AON_POS     (21U)
+#define AON_USB20_RREF_HIZ_AON_LEN     (1U)
+#define AON_USB20_RREF_HIZ_AON_MSK     (((1U << AON_USB20_RREF_HIZ_AON_LEN) - 1) << AON_USB20_RREF_HIZ_AON_POS)
+#define AON_USB20_RREF_HIZ_AON_UMSK    (~(((1U << AON_USB20_RREF_HIZ_AON_LEN) - 1) << AON_USB20_RREF_HIZ_AON_POS))
+#define AON_USB20_RCAL_CODE_AON        AON_USB20_RCAL_CODE_AON
+#define AON_USB20_RCAL_CODE_AON_POS    (24U)
+#define AON_USB20_RCAL_CODE_AON_LEN    (6U)
+#define AON_USB20_RCAL_CODE_AON_MSK    (((1U << AON_USB20_RCAL_CODE_AON_LEN) - 1) << AON_USB20_RCAL_CODE_AON_POS)
+#define AON_USB20_RCAL_CODE_AON_UMSK   (~(((1U << AON_USB20_RCAL_CODE_AON_LEN) - 1) << AON_USB20_RCAL_CODE_AON_POS))
+
+/* 0x880 : rf_top_aon */
+#define AON_RF_TOP_AON_OFFSET             (0x880)
+#define AON_PU_MBG_AON                    AON_PU_MBG_AON
+#define AON_PU_MBG_AON_POS                (0U)
+#define AON_PU_MBG_AON_LEN                (1U)
+#define AON_PU_MBG_AON_MSK                (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)
+#define AON_PU_MBG_AON_UMSK               (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS))
+#define AON_PU_LDO15RF_AON                AON_PU_LDO15RF_AON
+#define AON_PU_LDO15RF_AON_POS            (1U)
+#define AON_PU_LDO15RF_AON_LEN            (1U)
+#define AON_PU_LDO15RF_AON_MSK            (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)
+#define AON_PU_LDO15RF_AON_UMSK           (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS))
+#define AON_PU_SFREG_AON                  AON_PU_SFREG_AON
+#define AON_PU_SFREG_AON_POS              (2U)
+#define AON_PU_SFREG_AON_LEN              (1U)
+#define AON_PU_SFREG_AON_MSK              (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)
+#define AON_PU_SFREG_AON_UMSK             (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS))
+#define AON_PU_XTAL_BUF_AON               AON_PU_XTAL_BUF_AON
+#define AON_PU_XTAL_BUF_AON_POS           (4U)
+#define AON_PU_XTAL_BUF_AON_LEN           (1U)
+#define AON_PU_XTAL_BUF_AON_MSK           (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)
+#define AON_PU_XTAL_BUF_AON_UMSK          (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS))
+#define AON_PU_XTAL_AON                   AON_PU_XTAL_AON
+#define AON_PU_XTAL_AON_POS               (5U)
+#define AON_PU_XTAL_AON_LEN               (1U)
+#define AON_PU_XTAL_AON_MSK               (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)
+#define AON_PU_XTAL_AON_UMSK              (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS))
+#define AON_LDO15RF_SSTART_SEL_AON        AON_LDO15RF_SSTART_SEL_AON
+#define AON_LDO15RF_SSTART_SEL_AON_POS    (8U)
+#define AON_LDO15RF_SSTART_SEL_AON_LEN    (1U)
+#define AON_LDO15RF_SSTART_SEL_AON_MSK    (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)
+#define AON_LDO15RF_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS))
+#define AON_LDO15RF_SSTART_DELAY_AON      AON_LDO15RF_SSTART_DELAY_AON
+#define AON_LDO15RF_SSTART_DELAY_AON_POS  (9U)
+#define AON_LDO15RF_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO15RF_SSTART_DELAY_AON_MSK  (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)
+#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS))
+#define AON_LDO15RF_PULLDOWN_AON          AON_LDO15RF_PULLDOWN_AON
+#define AON_LDO15RF_PULLDOWN_AON_POS      (12U)
+#define AON_LDO15RF_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO15RF_PULLDOWN_AON_MSK      (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)
+#define AON_LDO15RF_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS))
+#define AON_LDO15RF_PULLDOWN_SEL_AON      AON_LDO15RF_PULLDOWN_SEL_AON
+#define AON_LDO15RF_PULLDOWN_SEL_AON_POS  (13U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS))
+#define AON_LDO15RF_VOUT_SEL_AON          AON_LDO15RF_VOUT_SEL_AON
+#define AON_LDO15RF_VOUT_SEL_AON_POS      (16U)
+#define AON_LDO15RF_VOUT_SEL_AON_LEN      (3U)
+#define AON_LDO15RF_VOUT_SEL_AON_MSK      (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)
+#define AON_LDO15RF_VOUT_SEL_AON_UMSK     (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS))
+#define AON_LDO15RF_CC_AON                AON_LDO15RF_CC_AON
+#define AON_LDO15RF_CC_AON_POS            (24U)
+#define AON_LDO15RF_CC_AON_LEN            (2U)
+#define AON_LDO15RF_CC_AON_MSK            (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)
+#define AON_LDO15RF_CC_AON_UMSK           (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS))
+#define AON_LDO15RF_BYPASS_AON            AON_LDO15RF_BYPASS_AON
+#define AON_LDO15RF_BYPASS_AON_POS        (27U)
+#define AON_LDO15RF_BYPASS_AON_LEN        (1U)
+#define AON_LDO15RF_BYPASS_AON_MSK        (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)
+#define AON_LDO15RF_BYPASS_AON_UMSK       (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS))
+#define AON_LDO15RF_VOUT_TRIM_AON         AON_LDO15RF_VOUT_TRIM_AON
+#define AON_LDO15RF_VOUT_TRIM_AON_POS     (28U)
+#define AON_LDO15RF_VOUT_TRIM_AON_LEN     (4U)
+#define AON_LDO15RF_VOUT_TRIM_AON_MSK     (((1U << AON_LDO15RF_VOUT_TRIM_AON_LEN) - 1) << AON_LDO15RF_VOUT_TRIM_AON_POS)
+#define AON_LDO15RF_VOUT_TRIM_AON_UMSK    (~(((1U << AON_LDO15RF_VOUT_TRIM_AON_LEN) - 1) << AON_LDO15RF_VOUT_TRIM_AON_POS))
+
+/* 0x884 : xtal_cfg */
+#define AON_XTAL_CFG_OFFSET             (0x884)
+#define AON_XTAL_BK_AON                 AON_XTAL_BK_AON
+#define AON_XTAL_BK_AON_POS             (0U)
+#define AON_XTAL_BK_AON_LEN             (2U)
+#define AON_XTAL_BK_AON_MSK             (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)
+#define AON_XTAL_BK_AON_UMSK            (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS))
+#define AON_XTAL_CAPCODE_EXTRA_AON      AON_XTAL_CAPCODE_EXTRA_AON
+#define AON_XTAL_CAPCODE_EXTRA_AON_POS  (2U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_LEN  (1U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_MSK  (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)
+#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS))
+#define AON_XTAL_EXT_SEL_AON            AON_XTAL_EXT_SEL_AON
+#define AON_XTAL_EXT_SEL_AON_POS        (3U)
+#define AON_XTAL_EXT_SEL_AON_LEN        (1U)
+#define AON_XTAL_EXT_SEL_AON_MSK        (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)
+#define AON_XTAL_EXT_SEL_AON_UMSK       (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS))
+#define AON_XTAL_BUF_EN_AON             AON_XTAL_BUF_EN_AON
+#define AON_XTAL_BUF_EN_AON_POS         (4U)
+#define AON_XTAL_BUF_EN_AON_LEN         (2U)
+#define AON_XTAL_BUF_EN_AON_MSK         (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)
+#define AON_XTAL_BUF_EN_AON_UMSK        (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS))
+#define AON_XTAL_ACBUF_EN_AON           AON_XTAL_ACBUF_EN_AON
+#define AON_XTAL_ACBUF_EN_AON_POS       (6U)
+#define AON_XTAL_ACBUF_EN_AON_LEN       (1U)
+#define AON_XTAL_ACBUF_EN_AON_MSK       (((1U << AON_XTAL_ACBUF_EN_AON_LEN) - 1) << AON_XTAL_ACBUF_EN_AON_POS)
+#define AON_XTAL_ACBUF_EN_AON_UMSK      (~(((1U << AON_XTAL_ACBUF_EN_AON_LEN) - 1) << AON_XTAL_ACBUF_EN_AON_POS))
+#define AON_XTAL_ACBUF_MODE_AON         AON_XTAL_ACBUF_MODE_AON
+#define AON_XTAL_ACBUF_MODE_AON_POS     (7U)
+#define AON_XTAL_ACBUF_MODE_AON_LEN     (1U)
+#define AON_XTAL_ACBUF_MODE_AON_MSK     (((1U << AON_XTAL_ACBUF_MODE_AON_LEN) - 1) << AON_XTAL_ACBUF_MODE_AON_POS)
+#define AON_XTAL_ACBUF_MODE_AON_UMSK    (~(((1U << AON_XTAL_ACBUF_MODE_AON_LEN) - 1) << AON_XTAL_ACBUF_MODE_AON_POS))
+#define AON_XTAL_BUF_HP_AON             AON_XTAL_BUF_HP_AON
+#define AON_XTAL_BUF_HP_AON_POS         (8U)
+#define AON_XTAL_BUF_HP_AON_LEN         (2U)
+#define AON_XTAL_BUF_HP_AON_MSK         (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)
+#define AON_XTAL_BUF_HP_AON_UMSK        (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS))
+#define AON_XTAL_SOCBUF_EN_AON          AON_XTAL_SOCBUF_EN_AON
+#define AON_XTAL_SOCBUF_EN_AON_POS      (11U)
+#define AON_XTAL_SOCBUF_EN_AON_LEN      (1U)
+#define AON_XTAL_SOCBUF_EN_AON_MSK      (((1U << AON_XTAL_SOCBUF_EN_AON_LEN) - 1) << AON_XTAL_SOCBUF_EN_AON_POS)
+#define AON_XTAL_SOCBUF_EN_AON_UMSK     (~(((1U << AON_XTAL_SOCBUF_EN_AON_LEN) - 1) << AON_XTAL_SOCBUF_EN_AON_POS))
+#define AON_XTAL_FAST_STARTUP_AON       AON_XTAL_FAST_STARTUP_AON
+#define AON_XTAL_FAST_STARTUP_AON_POS   (12U)
+#define AON_XTAL_FAST_STARTUP_AON_LEN   (1U)
+#define AON_XTAL_FAST_STARTUP_AON_MSK   (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)
+#define AON_XTAL_FAST_STARTUP_AON_UMSK  (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS))
+#define AON_XTAL_SLEEP_AON              AON_XTAL_SLEEP_AON
+#define AON_XTAL_SLEEP_AON_POS          (13U)
+#define AON_XTAL_SLEEP_AON_LEN          (1U)
+#define AON_XTAL_SLEEP_AON_MSK          (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)
+#define AON_XTAL_SLEEP_AON_UMSK         (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS))
+#define AON_XTAL_AMP_CTRL_AON           AON_XTAL_AMP_CTRL_AON
+#define AON_XTAL_AMP_CTRL_AON_POS       (14U)
+#define AON_XTAL_AMP_CTRL_AON_LEN       (2U)
+#define AON_XTAL_AMP_CTRL_AON_MSK       (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)
+#define AON_XTAL_AMP_CTRL_AON_UMSK      (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS))
+#define AON_XTAL_CAPCODE_OUT_AON        AON_XTAL_CAPCODE_OUT_AON
+#define AON_XTAL_CAPCODE_OUT_AON_POS    (16U)
+#define AON_XTAL_CAPCODE_OUT_AON_LEN    (6U)
+#define AON_XTAL_CAPCODE_OUT_AON_MSK    (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)
+#define AON_XTAL_CAPCODE_OUT_AON_UMSK   (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS))
+#define AON_XTAL_CAPCODE_IN_AON         AON_XTAL_CAPCODE_IN_AON
+#define AON_XTAL_CAPCODE_IN_AON_POS     (22U)
+#define AON_XTAL_CAPCODE_IN_AON_LEN     (6U)
+#define AON_XTAL_CAPCODE_IN_AON_MSK     (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)
+#define AON_XTAL_CAPCODE_IN_AON_UMSK    (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS))
+#define AON_XTAL_GM_BOOST_AON           AON_XTAL_GM_BOOST_AON
+#define AON_XTAL_GM_BOOST_AON_POS       (28U)
+#define AON_XTAL_GM_BOOST_AON_LEN       (2U)
+#define AON_XTAL_GM_BOOST_AON_MSK       (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)
+#define AON_XTAL_GM_BOOST_AON_UMSK      (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS))
+#define AON_XTAL_RDY_SEL_AON            AON_XTAL_RDY_SEL_AON
+#define AON_XTAL_RDY_SEL_AON_POS        (30U)
+#define AON_XTAL_RDY_SEL_AON_LEN        (2U)
+#define AON_XTAL_RDY_SEL_AON_MSK        (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)
+#define AON_XTAL_RDY_SEL_AON_UMSK       (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS))
+
+/* 0x888 : tsen */
+#define AON_TSEN_OFFSET               (0x888)
+#define AON_TSEN_REFCODE_CORNER       AON_TSEN_REFCODE_CORNER
+#define AON_TSEN_REFCODE_CORNER_POS   (0U)
+#define AON_TSEN_REFCODE_CORNER_LEN   (12U)
+#define AON_TSEN_REFCODE_CORNER_MSK   (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)
+#define AON_TSEN_REFCODE_CORNER_UMSK  (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS))
+#define AON_TSEN_REFCODE_RFCAL        AON_TSEN_REFCODE_RFCAL
+#define AON_TSEN_REFCODE_RFCAL_POS    (16U)
+#define AON_TSEN_REFCODE_RFCAL_LEN    (12U)
+#define AON_TSEN_REFCODE_RFCAL_MSK    (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)
+#define AON_TSEN_REFCODE_RFCAL_UMSK   (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS))
+#define AON_XTAL_RDY                  AON_XTAL_RDY
+#define AON_XTAL_RDY_POS              (28U)
+#define AON_XTAL_RDY_LEN              (1U)
+#define AON_XTAL_RDY_MSK              (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)
+#define AON_XTAL_RDY_UMSK             (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS))
+#define AON_XTAL_INN_CFG_EN_AON       AON_XTAL_INN_CFG_EN_AON
+#define AON_XTAL_INN_CFG_EN_AON_POS   (29U)
+#define AON_XTAL_INN_CFG_EN_AON_LEN   (1U)
+#define AON_XTAL_INN_CFG_EN_AON_MSK   (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)
+#define AON_XTAL_INN_CFG_EN_AON_UMSK  (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS))
+#define AON_XTAL_RDY_INT_SEL_AON      AON_XTAL_RDY_INT_SEL_AON
+#define AON_XTAL_RDY_INT_SEL_AON_POS  (30U)
+#define AON_XTAL_RDY_INT_SEL_AON_LEN  (2U)
+#define AON_XTAL_RDY_INT_SEL_AON_MSK  (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)
+#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS))
+
+/* 0x900 : acomp0_ctrl */
+#define AON_ACOMP0_CTRL_OFFSET    (0x900)
+#define AON_ACOMP0_EN             AON_ACOMP0_EN
+#define AON_ACOMP0_EN_POS         (0U)
+#define AON_ACOMP0_EN_LEN         (1U)
+#define AON_ACOMP0_EN_MSK         (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)
+#define AON_ACOMP0_EN_UMSK        (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS))
+#define AON_ACOMP0_HYST_SELN      AON_ACOMP0_HYST_SELN
+#define AON_ACOMP0_HYST_SELN_POS  (4U)
+#define AON_ACOMP0_HYST_SELN_LEN  (3U)
+#define AON_ACOMP0_HYST_SELN_MSK  (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)
+#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS))
+#define AON_ACOMP0_HYST_SELP      AON_ACOMP0_HYST_SELP
+#define AON_ACOMP0_HYST_SELP_POS  (7U)
+#define AON_ACOMP0_HYST_SELP_LEN  (3U)
+#define AON_ACOMP0_HYST_SELP_MSK  (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)
+#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS))
+#define AON_ACOMP0_BIAS_PROG      AON_ACOMP0_BIAS_PROG
+#define AON_ACOMP0_BIAS_PROG_POS  (10U)
+#define AON_ACOMP0_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP0_BIAS_PROG_MSK  (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)
+#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS))
+#define AON_ACOMP0_LEVEL_SEL      AON_ACOMP0_LEVEL_SEL
+#define AON_ACOMP0_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP0_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP0_LEVEL_SEL_MSK  (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)
+#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS))
+#define AON_ACOMP0_NEG_SEL        AON_ACOMP0_NEG_SEL
+#define AON_ACOMP0_NEG_SEL_POS    (18U)
+#define AON_ACOMP0_NEG_SEL_LEN    (4U)
+#define AON_ACOMP0_NEG_SEL_MSK    (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)
+#define AON_ACOMP0_NEG_SEL_UMSK   (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS))
+#define AON_ACOMP0_POS_SEL        AON_ACOMP0_POS_SEL
+#define AON_ACOMP0_POS_SEL_POS    (22U)
+#define AON_ACOMP0_POS_SEL_LEN    (4U)
+#define AON_ACOMP0_POS_SEL_MSK    (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)
+#define AON_ACOMP0_POS_SEL_UMSK   (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS))
+#define AON_ACOMP0_MUXEN          AON_ACOMP0_MUXEN
+#define AON_ACOMP0_MUXEN_POS      (26U)
+#define AON_ACOMP0_MUXEN_LEN      (1U)
+#define AON_ACOMP0_MUXEN_MSK      (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)
+#define AON_ACOMP0_MUXEN_UMSK     (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS))
+
+/* 0x904 : acomp1_ctrl */
+#define AON_ACOMP1_CTRL_OFFSET    (0x904)
+#define AON_ACOMP1_EN             AON_ACOMP1_EN
+#define AON_ACOMP1_EN_POS         (0U)
+#define AON_ACOMP1_EN_LEN         (1U)
+#define AON_ACOMP1_EN_MSK         (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)
+#define AON_ACOMP1_EN_UMSK        (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS))
+#define AON_ACOMP1_HYST_SELN      AON_ACOMP1_HYST_SELN
+#define AON_ACOMP1_HYST_SELN_POS  (4U)
+#define AON_ACOMP1_HYST_SELN_LEN  (3U)
+#define AON_ACOMP1_HYST_SELN_MSK  (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)
+#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS))
+#define AON_ACOMP1_HYST_SELP      AON_ACOMP1_HYST_SELP
+#define AON_ACOMP1_HYST_SELP_POS  (7U)
+#define AON_ACOMP1_HYST_SELP_LEN  (3U)
+#define AON_ACOMP1_HYST_SELP_MSK  (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)
+#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS))
+#define AON_ACOMP1_BIAS_PROG      AON_ACOMP1_BIAS_PROG
+#define AON_ACOMP1_BIAS_PROG_POS  (10U)
+#define AON_ACOMP1_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP1_BIAS_PROG_MSK  (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)
+#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS))
+#define AON_ACOMP1_LEVEL_SEL      AON_ACOMP1_LEVEL_SEL
+#define AON_ACOMP1_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP1_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP1_LEVEL_SEL_MSK  (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)
+#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS))
+#define AON_ACOMP1_NEG_SEL        AON_ACOMP1_NEG_SEL
+#define AON_ACOMP1_NEG_SEL_POS    (18U)
+#define AON_ACOMP1_NEG_SEL_LEN    (4U)
+#define AON_ACOMP1_NEG_SEL_MSK    (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)
+#define AON_ACOMP1_NEG_SEL_UMSK   (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS))
+#define AON_ACOMP1_POS_SEL        AON_ACOMP1_POS_SEL
+#define AON_ACOMP1_POS_SEL_POS    (22U)
+#define AON_ACOMP1_POS_SEL_LEN    (4U)
+#define AON_ACOMP1_POS_SEL_MSK    (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)
+#define AON_ACOMP1_POS_SEL_UMSK   (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS))
+#define AON_ACOMP1_MUXEN          AON_ACOMP1_MUXEN
+#define AON_ACOMP1_MUXEN_POS      (26U)
+#define AON_ACOMP1_MUXEN_LEN      (1U)
+#define AON_ACOMP1_MUXEN_MSK      (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)
+#define AON_ACOMP1_MUXEN_UMSK     (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS))
+
+/* 0x908 : acomp_ctrl */
+#define AON_ACOMP_CTRL_OFFSET    (0x908)
+#define AON_ACOMP1_RSTN_ANA      AON_ACOMP1_RSTN_ANA
+#define AON_ACOMP1_RSTN_ANA_POS  (0U)
+#define AON_ACOMP1_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP1_RSTN_ANA_MSK  (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)
+#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS))
+#define AON_ACOMP0_RSTN_ANA      AON_ACOMP0_RSTN_ANA
+#define AON_ACOMP0_RSTN_ANA_POS  (1U)
+#define AON_ACOMP0_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP0_RSTN_ANA_MSK  (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)
+#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS))
+#define AON_ACOMP1_TEST_EN       AON_ACOMP1_TEST_EN
+#define AON_ACOMP1_TEST_EN_POS   (8U)
+#define AON_ACOMP1_TEST_EN_LEN   (1U)
+#define AON_ACOMP1_TEST_EN_MSK   (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)
+#define AON_ACOMP1_TEST_EN_UMSK  (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS))
+#define AON_ACOMP0_TEST_EN       AON_ACOMP0_TEST_EN
+#define AON_ACOMP0_TEST_EN_POS   (9U)
+#define AON_ACOMP0_TEST_EN_LEN   (1U)
+#define AON_ACOMP0_TEST_EN_MSK   (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)
+#define AON_ACOMP0_TEST_EN_UMSK  (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS))
+#define AON_ACOMP1_TEST_SEL      AON_ACOMP1_TEST_SEL
+#define AON_ACOMP1_TEST_SEL_POS  (10U)
+#define AON_ACOMP1_TEST_SEL_LEN  (2U)
+#define AON_ACOMP1_TEST_SEL_MSK  (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)
+#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS))
+#define AON_ACOMP0_TEST_SEL      AON_ACOMP0_TEST_SEL
+#define AON_ACOMP0_TEST_SEL_POS  (12U)
+#define AON_ACOMP0_TEST_SEL_LEN  (2U)
+#define AON_ACOMP0_TEST_SEL_MSK  (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)
+#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS))
+#define AON_ACOMP1_OUT_RAW       AON_ACOMP1_OUT_RAW
+#define AON_ACOMP1_OUT_RAW_POS   (17U)
+#define AON_ACOMP1_OUT_RAW_LEN   (1U)
+#define AON_ACOMP1_OUT_RAW_MSK   (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)
+#define AON_ACOMP1_OUT_RAW_UMSK  (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS))
+#define AON_ACOMP0_OUT_RAW       AON_ACOMP0_OUT_RAW
+#define AON_ACOMP0_OUT_RAW_POS   (19U)
+#define AON_ACOMP0_OUT_RAW_LEN   (1U)
+#define AON_ACOMP0_OUT_RAW_MSK   (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)
+#define AON_ACOMP0_OUT_RAW_UMSK  (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS))
+#define AON_ACOMP_VREF_SEL       AON_ACOMP_VREF_SEL
+#define AON_ACOMP_VREF_SEL_POS   (24U)
+#define AON_ACOMP_VREF_SEL_LEN   (6U)
+#define AON_ACOMP_VREF_SEL_MSK   (((1U << AON_ACOMP_VREF_SEL_LEN) - 1) << AON_ACOMP_VREF_SEL_POS)
+#define AON_ACOMP_VREF_SEL_UMSK  (~(((1U << AON_ACOMP_VREF_SEL_LEN) - 1) << AON_ACOMP_VREF_SEL_POS))
+#define AON_ACOMP_RESERVED       AON_ACOMP_RESERVED
+#define AON_ACOMP_RESERVED_POS   (30U)
+#define AON_ACOMP_RESERVED_LEN   (2U)
+#define AON_ACOMP_RESERVED_MSK   (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)
+#define AON_ACOMP_RESERVED_UMSK  (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS))
+
+/* 0x90C : gpadc_reg_cmd */
+#define AON_GPADC_REG_CMD_OFFSET        (0x90C)
+#define AON_GPADC_GLOBAL_EN             AON_GPADC_GLOBAL_EN
+#define AON_GPADC_GLOBAL_EN_POS         (0U)
+#define AON_GPADC_GLOBAL_EN_LEN         (1U)
+#define AON_GPADC_GLOBAL_EN_MSK         (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)
+#define AON_GPADC_GLOBAL_EN_UMSK        (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS))
+#define AON_GPADC_CONV_START            AON_GPADC_CONV_START
+#define AON_GPADC_CONV_START_POS        (1U)
+#define AON_GPADC_CONV_START_LEN        (1U)
+#define AON_GPADC_CONV_START_MSK        (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)
+#define AON_GPADC_CONV_START_UMSK       (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS))
+#define AON_GPADC_SOFT_RST              AON_GPADC_SOFT_RST
+#define AON_GPADC_SOFT_RST_POS          (2U)
+#define AON_GPADC_SOFT_RST_LEN          (1U)
+#define AON_GPADC_SOFT_RST_MSK          (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)
+#define AON_GPADC_SOFT_RST_UMSK         (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS))
+#define AON_GPADC_NEG_SEL               AON_GPADC_NEG_SEL
+#define AON_GPADC_NEG_SEL_POS           (3U)
+#define AON_GPADC_NEG_SEL_LEN           (5U)
+#define AON_GPADC_NEG_SEL_MSK           (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)
+#define AON_GPADC_NEG_SEL_UMSK          (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS))
+#define AON_GPADC_POS_SEL               AON_GPADC_POS_SEL
+#define AON_GPADC_POS_SEL_POS           (8U)
+#define AON_GPADC_POS_SEL_LEN           (5U)
+#define AON_GPADC_POS_SEL_MSK           (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)
+#define AON_GPADC_POS_SEL_UMSK          (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS))
+#define AON_GPADC_NEG_GND               AON_GPADC_NEG_GND
+#define AON_GPADC_NEG_GND_POS           (13U)
+#define AON_GPADC_NEG_GND_LEN           (1U)
+#define AON_GPADC_NEG_GND_MSK           (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)
+#define AON_GPADC_NEG_GND_UMSK          (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS))
+#define AON_GPADC_MICBIAS_EN            AON_GPADC_MICBIAS_EN
+#define AON_GPADC_MICBIAS_EN_POS        (14U)
+#define AON_GPADC_MICBIAS_EN_LEN        (1U)
+#define AON_GPADC_MICBIAS_EN_MSK        (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)
+#define AON_GPADC_MICBIAS_EN_UMSK       (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS))
+#define AON_GPADC_MICPGA_EN             AON_GPADC_MICPGA_EN
+#define AON_GPADC_MICPGA_EN_POS         (15U)
+#define AON_GPADC_MICPGA_EN_LEN         (1U)
+#define AON_GPADC_MICPGA_EN_MSK         (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)
+#define AON_GPADC_MICPGA_EN_UMSK        (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS))
+#define AON_GPADC_BYP_MICBOOST          AON_GPADC_BYP_MICBOOST
+#define AON_GPADC_BYP_MICBOOST_POS      (16U)
+#define AON_GPADC_BYP_MICBOOST_LEN      (1U)
+#define AON_GPADC_BYP_MICBOOST_MSK      (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)
+#define AON_GPADC_BYP_MICBOOST_UMSK     (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS))
+#define AON_GPADC_RCAL_EN               AON_GPADC_RCAL_EN
+#define AON_GPADC_RCAL_EN_POS           (17U)
+#define AON_GPADC_RCAL_EN_LEN           (1U)
+#define AON_GPADC_RCAL_EN_MSK           (((1U << AON_GPADC_RCAL_EN_LEN) - 1) << AON_GPADC_RCAL_EN_POS)
+#define AON_GPADC_RCAL_EN_UMSK          (~(((1U << AON_GPADC_RCAL_EN_LEN) - 1) << AON_GPADC_RCAL_EN_POS))
+#define AON_GPADC_DWA_EN                AON_GPADC_DWA_EN
+#define AON_GPADC_DWA_EN_POS            (18U)
+#define AON_GPADC_DWA_EN_LEN            (1U)
+#define AON_GPADC_DWA_EN_MSK            (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)
+#define AON_GPADC_DWA_EN_UMSK           (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS))
+#define AON_GPADC_MIC2_DIFF             AON_GPADC_MIC2_DIFF
+#define AON_GPADC_MIC2_DIFF_POS         (19U)
+#define AON_GPADC_MIC2_DIFF_LEN         (1U)
+#define AON_GPADC_MIC2_DIFF_MSK         (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)
+#define AON_GPADC_MIC2_DIFF_UMSK        (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS))
+#define AON_GPADC_MIC1_DIFF             AON_GPADC_MIC1_DIFF
+#define AON_GPADC_MIC1_DIFF_POS         (20U)
+#define AON_GPADC_MIC1_DIFF_LEN         (1U)
+#define AON_GPADC_MIC1_DIFF_MSK         (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)
+#define AON_GPADC_MIC1_DIFF_UMSK        (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS))
+#define AON_GPADC_MIC_PGA2_GAIN         AON_GPADC_MIC_PGA2_GAIN
+#define AON_GPADC_MIC_PGA2_GAIN_POS     (21U)
+#define AON_GPADC_MIC_PGA2_GAIN_LEN     (2U)
+#define AON_GPADC_MIC_PGA2_GAIN_MSK     (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)
+#define AON_GPADC_MIC_PGA2_GAIN_UMSK    (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS))
+#define AON_GPADC_MICBOOST_32DB_EN      AON_GPADC_MICBOOST_32DB_EN
+#define AON_GPADC_MICBOOST_32DB_EN_POS  (23U)
+#define AON_GPADC_MICBOOST_32DB_EN_LEN  (1U)
+#define AON_GPADC_MICBOOST_32DB_EN_MSK  (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)
+#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS))
+#define AON_GPADC_CHIP_SEN_PU           AON_GPADC_CHIP_SEN_PU
+#define AON_GPADC_CHIP_SEN_PU_POS       (27U)
+#define AON_GPADC_CHIP_SEN_PU_LEN       (1U)
+#define AON_GPADC_CHIP_SEN_PU_MSK       (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)
+#define AON_GPADC_CHIP_SEN_PU_UMSK      (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS))
+#define AON_GPADC_SEN_SEL               AON_GPADC_SEN_SEL
+#define AON_GPADC_SEN_SEL_POS           (28U)
+#define AON_GPADC_SEN_SEL_LEN           (3U)
+#define AON_GPADC_SEN_SEL_MSK           (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)
+#define AON_GPADC_SEN_SEL_UMSK          (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS))
+#define AON_GPADC_SEN_TEST_EN           AON_GPADC_SEN_TEST_EN
+#define AON_GPADC_SEN_TEST_EN_POS       (31U)
+#define AON_GPADC_SEN_TEST_EN_LEN       (1U)
+#define AON_GPADC_SEN_TEST_EN_MSK       (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)
+#define AON_GPADC_SEN_TEST_EN_UMSK      (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS))
+
+/* 0x910 : gpadc_reg_config1 */
+#define AON_GPADC_REG_CONFIG1_OFFSET  (0x910)
+#define AON_GPADC_CAL_OS_EN           AON_GPADC_CAL_OS_EN
+#define AON_GPADC_CAL_OS_EN_POS       (0U)
+#define AON_GPADC_CAL_OS_EN_LEN       (1U)
+#define AON_GPADC_CAL_OS_EN_MSK       (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)
+#define AON_GPADC_CAL_OS_EN_UMSK      (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS))
+#define AON_GPADC_CONT_CONV_EN        AON_GPADC_CONT_CONV_EN
+#define AON_GPADC_CONT_CONV_EN_POS    (1U)
+#define AON_GPADC_CONT_CONV_EN_LEN    (1U)
+#define AON_GPADC_CONT_CONV_EN_MSK    (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)
+#define AON_GPADC_CONT_CONV_EN_UMSK   (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS))
+#define AON_GPADC_RES_SEL             AON_GPADC_RES_SEL
+#define AON_GPADC_RES_SEL_POS         (2U)
+#define AON_GPADC_RES_SEL_LEN         (3U)
+#define AON_GPADC_RES_SEL_MSK         (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)
+#define AON_GPADC_RES_SEL_UMSK        (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS))
+#define AON_GPADC_VCM_SEL_EN          AON_GPADC_VCM_SEL_EN
+#define AON_GPADC_VCM_SEL_EN_POS      (8U)
+#define AON_GPADC_VCM_SEL_EN_LEN      (1U)
+#define AON_GPADC_VCM_SEL_EN_MSK      (((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS)
+#define AON_GPADC_VCM_SEL_EN_UMSK     (~(((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS))
+#define AON_GPADC_VCM_HYST_SEL        AON_GPADC_VCM_HYST_SEL
+#define AON_GPADC_VCM_HYST_SEL_POS    (9U)
+#define AON_GPADC_VCM_HYST_SEL_LEN    (1U)
+#define AON_GPADC_VCM_HYST_SEL_MSK    (((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS)
+#define AON_GPADC_VCM_HYST_SEL_UMSK   (~(((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS))
+#define AON_GPADC_LOWV_DET_EN         AON_GPADC_LOWV_DET_EN
+#define AON_GPADC_LOWV_DET_EN_POS     (10U)
+#define AON_GPADC_LOWV_DET_EN_LEN     (1U)
+#define AON_GPADC_LOWV_DET_EN_MSK     (((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS)
+#define AON_GPADC_LOWV_DET_EN_UMSK    (~(((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS))
+#define AON_GPADC_PWM_TRG_EN          AON_GPADC_PWM_TRG_EN
+#define AON_GPADC_PWM_TRG_EN_POS      (11U)
+#define AON_GPADC_PWM_TRG_EN_LEN      (1U)
+#define AON_GPADC_PWM_TRG_EN_MSK      (((1U << AON_GPADC_PWM_TRG_EN_LEN) - 1) << AON_GPADC_PWM_TRG_EN_POS)
+#define AON_GPADC_PWM_TRG_EN_UMSK     (~(((1U << AON_GPADC_PWM_TRG_EN_LEN) - 1) << AON_GPADC_PWM_TRG_EN_POS))
+#define AON_GPADC_CLK_ANA_DLY         AON_GPADC_CLK_ANA_DLY
+#define AON_GPADC_CLK_ANA_DLY_POS     (12U)
+#define AON_GPADC_CLK_ANA_DLY_LEN     (4U)
+#define AON_GPADC_CLK_ANA_DLY_MSK     (((1U << AON_GPADC_CLK_ANA_DLY_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_POS)
+#define AON_GPADC_CLK_ANA_DLY_UMSK    (~(((1U << AON_GPADC_CLK_ANA_DLY_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_POS))
+#define AON_GPADC_CLK_ANA_DLY_EN      AON_GPADC_CLK_ANA_DLY_EN
+#define AON_GPADC_CLK_ANA_DLY_EN_POS  (16U)
+#define AON_GPADC_CLK_ANA_DLY_EN_LEN  (1U)
+#define AON_GPADC_CLK_ANA_DLY_EN_MSK  (((1U << AON_GPADC_CLK_ANA_DLY_EN_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_EN_POS)
+#define AON_GPADC_CLK_ANA_DLY_EN_UMSK (~(((1U << AON_GPADC_CLK_ANA_DLY_EN_LEN) - 1) << AON_GPADC_CLK_ANA_DLY_EN_POS))
+#define AON_GPADC_CLK_ANA_INV         AON_GPADC_CLK_ANA_INV
+#define AON_GPADC_CLK_ANA_INV_POS     (17U)
+#define AON_GPADC_CLK_ANA_INV_LEN     (1U)
+#define AON_GPADC_CLK_ANA_INV_MSK     (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)
+#define AON_GPADC_CLK_ANA_INV_UMSK    (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS))
+#define AON_GPADC_CLK_DIV_RATIO       AON_GPADC_CLK_DIV_RATIO
+#define AON_GPADC_CLK_DIV_RATIO_POS   (18U)
+#define AON_GPADC_CLK_DIV_RATIO_LEN   (3U)
+#define AON_GPADC_CLK_DIV_RATIO_MSK   (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)
+#define AON_GPADC_CLK_DIV_RATIO_UMSK  (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS))
+#define AON_GPADC_SCAN_LENGTH         AON_GPADC_SCAN_LENGTH
+#define AON_GPADC_SCAN_LENGTH_POS     (21U)
+#define AON_GPADC_SCAN_LENGTH_LEN     (4U)
+#define AON_GPADC_SCAN_LENGTH_MSK     (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)
+#define AON_GPADC_SCAN_LENGTH_UMSK    (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS))
+#define AON_GPADC_SCAN_EN             AON_GPADC_SCAN_EN
+#define AON_GPADC_SCAN_EN_POS         (25U)
+#define AON_GPADC_SCAN_EN_LEN         (1U)
+#define AON_GPADC_SCAN_EN_MSK         (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)
+#define AON_GPADC_SCAN_EN_UMSK        (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS))
+#define AON_GPADC_DITHER_EN           AON_GPADC_DITHER_EN
+#define AON_GPADC_DITHER_EN_POS       (26U)
+#define AON_GPADC_DITHER_EN_LEN       (1U)
+#define AON_GPADC_DITHER_EN_MSK       (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)
+#define AON_GPADC_DITHER_EN_UMSK      (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS))
+#define AON_GPADC_V11_SEL             AON_GPADC_V11_SEL
+#define AON_GPADC_V11_SEL_POS         (27U)
+#define AON_GPADC_V11_SEL_LEN         (2U)
+#define AON_GPADC_V11_SEL_MSK         (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)
+#define AON_GPADC_V11_SEL_UMSK        (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS))
+#define AON_GPADC_V18_SEL             AON_GPADC_V18_SEL
+#define AON_GPADC_V18_SEL_POS         (29U)
+#define AON_GPADC_V18_SEL_LEN         (2U)
+#define AON_GPADC_V18_SEL_MSK         (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)
+#define AON_GPADC_V18_SEL_UMSK        (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS))
+
+/* 0x914 : gpadc_reg_config2 */
+#define AON_GPADC_REG_CONFIG2_OFFSET (0x914)
+#define AON_GPADC_DIFF_MODE          AON_GPADC_DIFF_MODE
+#define AON_GPADC_DIFF_MODE_POS      (2U)
+#define AON_GPADC_DIFF_MODE_LEN      (1U)
+#define AON_GPADC_DIFF_MODE_MSK      (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)
+#define AON_GPADC_DIFF_MODE_UMSK     (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS))
+#define AON_GPADC_VREF_SEL           AON_GPADC_VREF_SEL
+#define AON_GPADC_VREF_SEL_POS       (3U)
+#define AON_GPADC_VREF_SEL_LEN       (1U)
+#define AON_GPADC_VREF_SEL_MSK       (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)
+#define AON_GPADC_VREF_SEL_UMSK      (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS))
+#define AON_GPADC_VBAT_EN            AON_GPADC_VBAT_EN
+#define AON_GPADC_VBAT_EN_POS        (4U)
+#define AON_GPADC_VBAT_EN_LEN        (1U)
+#define AON_GPADC_VBAT_EN_MSK        (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)
+#define AON_GPADC_VBAT_EN_UMSK       (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS))
+#define AON_GPADC_TSEXT_SEL          AON_GPADC_TSEXT_SEL
+#define AON_GPADC_TSEXT_SEL_POS      (5U)
+#define AON_GPADC_TSEXT_SEL_LEN      (1U)
+#define AON_GPADC_TSEXT_SEL_MSK      (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)
+#define AON_GPADC_TSEXT_SEL_UMSK     (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS))
+#define AON_GPADC_TS_EN              AON_GPADC_TS_EN
+#define AON_GPADC_TS_EN_POS          (6U)
+#define AON_GPADC_TS_EN_LEN          (1U)
+#define AON_GPADC_TS_EN_MSK          (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)
+#define AON_GPADC_TS_EN_UMSK         (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS))
+#define AON_GPADC_PGA_VCM            AON_GPADC_PGA_VCM
+#define AON_GPADC_PGA_VCM_POS        (7U)
+#define AON_GPADC_PGA_VCM_LEN        (2U)
+#define AON_GPADC_PGA_VCM_MSK        (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)
+#define AON_GPADC_PGA_VCM_UMSK       (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS))
+#define AON_GPADC_PGA_OS_CAL         AON_GPADC_PGA_OS_CAL
+#define AON_GPADC_PGA_OS_CAL_POS     (9U)
+#define AON_GPADC_PGA_OS_CAL_LEN     (4U)
+#define AON_GPADC_PGA_OS_CAL_MSK     (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)
+#define AON_GPADC_PGA_OS_CAL_UMSK    (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS))
+#define AON_GPADC_PGA_EN             AON_GPADC_PGA_EN
+#define AON_GPADC_PGA_EN_POS         (13U)
+#define AON_GPADC_PGA_EN_LEN         (1U)
+#define AON_GPADC_PGA_EN_MSK         (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)
+#define AON_GPADC_PGA_EN_UMSK        (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS))
+#define AON_GPADC_PGA_VCMI_EN        AON_GPADC_PGA_VCMI_EN
+#define AON_GPADC_PGA_VCMI_EN_POS    (14U)
+#define AON_GPADC_PGA_VCMI_EN_LEN    (1U)
+#define AON_GPADC_PGA_VCMI_EN_MSK    (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)
+#define AON_GPADC_PGA_VCMI_EN_UMSK   (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS))
+#define AON_GPADC_CHOP_MODE          AON_GPADC_CHOP_MODE
+#define AON_GPADC_CHOP_MODE_POS      (15U)
+#define AON_GPADC_CHOP_MODE_LEN      (2U)
+#define AON_GPADC_CHOP_MODE_MSK      (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)
+#define AON_GPADC_CHOP_MODE_UMSK     (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS))
+#define AON_GPADC_BIAS_SEL           AON_GPADC_BIAS_SEL
+#define AON_GPADC_BIAS_SEL_POS       (17U)
+#define AON_GPADC_BIAS_SEL_LEN       (1U)
+#define AON_GPADC_BIAS_SEL_MSK       (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)
+#define AON_GPADC_BIAS_SEL_UMSK      (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS))
+#define AON_GPADC_TEST_EN            AON_GPADC_TEST_EN
+#define AON_GPADC_TEST_EN_POS        (18U)
+#define AON_GPADC_TEST_EN_LEN        (1U)
+#define AON_GPADC_TEST_EN_MSK        (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)
+#define AON_GPADC_TEST_EN_UMSK       (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS))
+#define AON_GPADC_TEST_SEL           AON_GPADC_TEST_SEL
+#define AON_GPADC_TEST_SEL_POS       (19U)
+#define AON_GPADC_TEST_SEL_LEN       (3U)
+#define AON_GPADC_TEST_SEL_MSK       (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)
+#define AON_GPADC_TEST_SEL_UMSK      (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS))
+#define AON_GPADC_PGA2_GAIN          AON_GPADC_PGA2_GAIN
+#define AON_GPADC_PGA2_GAIN_POS      (22U)
+#define AON_GPADC_PGA2_GAIN_LEN      (3U)
+#define AON_GPADC_PGA2_GAIN_MSK      (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)
+#define AON_GPADC_PGA2_GAIN_UMSK     (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS))
+#define AON_GPADC_PGA1_GAIN          AON_GPADC_PGA1_GAIN
+#define AON_GPADC_PGA1_GAIN_POS      (25U)
+#define AON_GPADC_PGA1_GAIN_LEN      (3U)
+#define AON_GPADC_PGA1_GAIN_MSK      (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)
+#define AON_GPADC_PGA1_GAIN_UMSK     (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS))
+#define AON_GPADC_DLY_SEL            AON_GPADC_DLY_SEL
+#define AON_GPADC_DLY_SEL_POS        (28U)
+#define AON_GPADC_DLY_SEL_LEN        (3U)
+#define AON_GPADC_DLY_SEL_MSK        (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)
+#define AON_GPADC_DLY_SEL_UMSK       (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS))
+#define AON_GPADC_TSVBE_LOW          AON_GPADC_TSVBE_LOW
+#define AON_GPADC_TSVBE_LOW_POS      (31U)
+#define AON_GPADC_TSVBE_LOW_LEN      (1U)
+#define AON_GPADC_TSVBE_LOW_MSK      (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)
+#define AON_GPADC_TSVBE_LOW_UMSK     (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS))
+
+/* 0x918 : adc converation sequence 1 */
+#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918)
+#define AON_GPADC_SCAN_POS_0          AON_GPADC_SCAN_POS_0
+#define AON_GPADC_SCAN_POS_0_POS      (0U)
+#define AON_GPADC_SCAN_POS_0_LEN      (5U)
+#define AON_GPADC_SCAN_POS_0_MSK      (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)
+#define AON_GPADC_SCAN_POS_0_UMSK     (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS))
+#define AON_GPADC_SCAN_POS_1          AON_GPADC_SCAN_POS_1
+#define AON_GPADC_SCAN_POS_1_POS      (5U)
+#define AON_GPADC_SCAN_POS_1_LEN      (5U)
+#define AON_GPADC_SCAN_POS_1_MSK      (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)
+#define AON_GPADC_SCAN_POS_1_UMSK     (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS))
+#define AON_GPADC_SCAN_POS_2          AON_GPADC_SCAN_POS_2
+#define AON_GPADC_SCAN_POS_2_POS      (10U)
+#define AON_GPADC_SCAN_POS_2_LEN      (5U)
+#define AON_GPADC_SCAN_POS_2_MSK      (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)
+#define AON_GPADC_SCAN_POS_2_UMSK     (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS))
+#define AON_GPADC_SCAN_POS_3          AON_GPADC_SCAN_POS_3
+#define AON_GPADC_SCAN_POS_3_POS      (15U)
+#define AON_GPADC_SCAN_POS_3_LEN      (5U)
+#define AON_GPADC_SCAN_POS_3_MSK      (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)
+#define AON_GPADC_SCAN_POS_3_UMSK     (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS))
+#define AON_GPADC_SCAN_POS_4          AON_GPADC_SCAN_POS_4
+#define AON_GPADC_SCAN_POS_4_POS      (20U)
+#define AON_GPADC_SCAN_POS_4_LEN      (5U)
+#define AON_GPADC_SCAN_POS_4_MSK      (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)
+#define AON_GPADC_SCAN_POS_4_UMSK     (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS))
+#define AON_GPADC_SCAN_POS_5          AON_GPADC_SCAN_POS_5
+#define AON_GPADC_SCAN_POS_5_POS      (25U)
+#define AON_GPADC_SCAN_POS_5_LEN      (5U)
+#define AON_GPADC_SCAN_POS_5_MSK      (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)
+#define AON_GPADC_SCAN_POS_5_UMSK     (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS))
+
+/* 0x91C : adc converation sequence 2 */
+#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C)
+#define AON_GPADC_SCAN_POS_6          AON_GPADC_SCAN_POS_6
+#define AON_GPADC_SCAN_POS_6_POS      (0U)
+#define AON_GPADC_SCAN_POS_6_LEN      (5U)
+#define AON_GPADC_SCAN_POS_6_MSK      (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)
+#define AON_GPADC_SCAN_POS_6_UMSK     (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS))
+#define AON_GPADC_SCAN_POS_7          AON_GPADC_SCAN_POS_7
+#define AON_GPADC_SCAN_POS_7_POS      (5U)
+#define AON_GPADC_SCAN_POS_7_LEN      (5U)
+#define AON_GPADC_SCAN_POS_7_MSK      (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)
+#define AON_GPADC_SCAN_POS_7_UMSK     (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS))
+#define AON_GPADC_SCAN_POS_8          AON_GPADC_SCAN_POS_8
+#define AON_GPADC_SCAN_POS_8_POS      (10U)
+#define AON_GPADC_SCAN_POS_8_LEN      (5U)
+#define AON_GPADC_SCAN_POS_8_MSK      (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)
+#define AON_GPADC_SCAN_POS_8_UMSK     (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS))
+#define AON_GPADC_SCAN_POS_9          AON_GPADC_SCAN_POS_9
+#define AON_GPADC_SCAN_POS_9_POS      (15U)
+#define AON_GPADC_SCAN_POS_9_LEN      (5U)
+#define AON_GPADC_SCAN_POS_9_MSK      (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)
+#define AON_GPADC_SCAN_POS_9_UMSK     (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS))
+#define AON_GPADC_SCAN_POS_10         AON_GPADC_SCAN_POS_10
+#define AON_GPADC_SCAN_POS_10_POS     (20U)
+#define AON_GPADC_SCAN_POS_10_LEN     (5U)
+#define AON_GPADC_SCAN_POS_10_MSK     (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)
+#define AON_GPADC_SCAN_POS_10_UMSK    (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS))
+#define AON_GPADC_SCAN_POS_11         AON_GPADC_SCAN_POS_11
+#define AON_GPADC_SCAN_POS_11_POS     (25U)
+#define AON_GPADC_SCAN_POS_11_LEN     (5U)
+#define AON_GPADC_SCAN_POS_11_MSK     (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)
+#define AON_GPADC_SCAN_POS_11_UMSK    (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS))
+
+/* 0x920 : adc converation sequence 3 */
+#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920)
+#define AON_GPADC_SCAN_NEG_0          AON_GPADC_SCAN_NEG_0
+#define AON_GPADC_SCAN_NEG_0_POS      (0U)
+#define AON_GPADC_SCAN_NEG_0_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_0_MSK      (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)
+#define AON_GPADC_SCAN_NEG_0_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS))
+#define AON_GPADC_SCAN_NEG_1          AON_GPADC_SCAN_NEG_1
+#define AON_GPADC_SCAN_NEG_1_POS      (5U)
+#define AON_GPADC_SCAN_NEG_1_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_1_MSK      (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)
+#define AON_GPADC_SCAN_NEG_1_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS))
+#define AON_GPADC_SCAN_NEG_2          AON_GPADC_SCAN_NEG_2
+#define AON_GPADC_SCAN_NEG_2_POS      (10U)
+#define AON_GPADC_SCAN_NEG_2_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_2_MSK      (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)
+#define AON_GPADC_SCAN_NEG_2_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS))
+#define AON_GPADC_SCAN_NEG_3          AON_GPADC_SCAN_NEG_3
+#define AON_GPADC_SCAN_NEG_3_POS      (15U)
+#define AON_GPADC_SCAN_NEG_3_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_3_MSK      (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)
+#define AON_GPADC_SCAN_NEG_3_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS))
+#define AON_GPADC_SCAN_NEG_4          AON_GPADC_SCAN_NEG_4
+#define AON_GPADC_SCAN_NEG_4_POS      (20U)
+#define AON_GPADC_SCAN_NEG_4_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_4_MSK      (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)
+#define AON_GPADC_SCAN_NEG_4_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS))
+#define AON_GPADC_SCAN_NEG_5          AON_GPADC_SCAN_NEG_5
+#define AON_GPADC_SCAN_NEG_5_POS      (25U)
+#define AON_GPADC_SCAN_NEG_5_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_5_MSK      (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)
+#define AON_GPADC_SCAN_NEG_5_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS))
+
+/* 0x924 : adc converation sequence 4 */
+#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924)
+#define AON_GPADC_SCAN_NEG_6          AON_GPADC_SCAN_NEG_6
+#define AON_GPADC_SCAN_NEG_6_POS      (0U)
+#define AON_GPADC_SCAN_NEG_6_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_6_MSK      (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)
+#define AON_GPADC_SCAN_NEG_6_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS))
+#define AON_GPADC_SCAN_NEG_7          AON_GPADC_SCAN_NEG_7
+#define AON_GPADC_SCAN_NEG_7_POS      (5U)
+#define AON_GPADC_SCAN_NEG_7_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_7_MSK      (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)
+#define AON_GPADC_SCAN_NEG_7_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS))
+#define AON_GPADC_SCAN_NEG_8          AON_GPADC_SCAN_NEG_8
+#define AON_GPADC_SCAN_NEG_8_POS      (10U)
+#define AON_GPADC_SCAN_NEG_8_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_8_MSK      (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)
+#define AON_GPADC_SCAN_NEG_8_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS))
+#define AON_GPADC_SCAN_NEG_9          AON_GPADC_SCAN_NEG_9
+#define AON_GPADC_SCAN_NEG_9_POS      (15U)
+#define AON_GPADC_SCAN_NEG_9_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_9_MSK      (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)
+#define AON_GPADC_SCAN_NEG_9_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS))
+#define AON_GPADC_SCAN_NEG_10         AON_GPADC_SCAN_NEG_10
+#define AON_GPADC_SCAN_NEG_10_POS     (20U)
+#define AON_GPADC_SCAN_NEG_10_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_10_MSK     (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)
+#define AON_GPADC_SCAN_NEG_10_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS))
+#define AON_GPADC_SCAN_NEG_11         AON_GPADC_SCAN_NEG_11
+#define AON_GPADC_SCAN_NEG_11_POS     (25U)
+#define AON_GPADC_SCAN_NEG_11_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_11_MSK     (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)
+#define AON_GPADC_SCAN_NEG_11_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS))
+
+/* 0x928 : gpadc_reg_status */
+#define AON_GPADC_REG_STATUS_OFFSET (0x928)
+#define AON_GPADC_DATA_RDY          AON_GPADC_DATA_RDY
+#define AON_GPADC_DATA_RDY_POS      (0U)
+#define AON_GPADC_DATA_RDY_LEN      (1U)
+#define AON_GPADC_DATA_RDY_MSK      (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)
+#define AON_GPADC_DATA_RDY_UMSK     (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS))
+#define AON_GPADC_RESERVED          AON_GPADC_RESERVED
+#define AON_GPADC_RESERVED_POS      (16U)
+#define AON_GPADC_RESERVED_LEN      (16U)
+#define AON_GPADC_RESERVED_MSK      (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)
+#define AON_GPADC_RESERVED_UMSK     (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS))
+
+/* 0x92C : gpadc_reg_isr */
+#define AON_GPADC_REG_ISR_OFFSET      (0x92C)
+#define AON_GPADC_NEG_SATUR           AON_GPADC_NEG_SATUR
+#define AON_GPADC_NEG_SATUR_POS       (0U)
+#define AON_GPADC_NEG_SATUR_LEN       (1U)
+#define AON_GPADC_NEG_SATUR_MSK       (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)
+#define AON_GPADC_NEG_SATUR_UMSK      (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS))
+#define AON_GPADC_POS_SATUR           AON_GPADC_POS_SATUR
+#define AON_GPADC_POS_SATUR_POS       (1U)
+#define AON_GPADC_POS_SATUR_LEN       (1U)
+#define AON_GPADC_POS_SATUR_MSK       (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)
+#define AON_GPADC_POS_SATUR_UMSK      (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS))
+#define AON_GPADC_NEG_SATUR_CLR       AON_GPADC_NEG_SATUR_CLR
+#define AON_GPADC_NEG_SATUR_CLR_POS   (4U)
+#define AON_GPADC_NEG_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_NEG_SATUR_CLR_MSK   (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)
+#define AON_GPADC_NEG_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS))
+#define AON_GPADC_POS_SATUR_CLR       AON_GPADC_POS_SATUR_CLR
+#define AON_GPADC_POS_SATUR_CLR_POS   (5U)
+#define AON_GPADC_POS_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_POS_SATUR_CLR_MSK   (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)
+#define AON_GPADC_POS_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS))
+#define AON_GPADC_NEG_SATUR_MASK      AON_GPADC_NEG_SATUR_MASK
+#define AON_GPADC_NEG_SATUR_MASK_POS  (8U)
+#define AON_GPADC_NEG_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_NEG_SATUR_MASK_MSK  (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)
+#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS))
+#define AON_GPADC_POS_SATUR_MASK      AON_GPADC_POS_SATUR_MASK
+#define AON_GPADC_POS_SATUR_MASK_POS  (9U)
+#define AON_GPADC_POS_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_POS_SATUR_MASK_MSK  (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)
+#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS))
+
+/* 0x930 : gpadc_reg_result */
+#define AON_GPADC_REG_RESULT_OFFSET (0x930)
+#define AON_GPADC_DATA_OUT          AON_GPADC_DATA_OUT
+#define AON_GPADC_DATA_OUT_POS      (0U)
+#define AON_GPADC_DATA_OUT_LEN      (26U)
+#define AON_GPADC_DATA_OUT_MSK      (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)
+#define AON_GPADC_DATA_OUT_UMSK     (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS))
+
+/* 0x934 : gpadc_reg_raw_result */
+#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934)
+#define AON_GPADC_RAW_DATA              AON_GPADC_RAW_DATA
+#define AON_GPADC_RAW_DATA_POS          (0U)
+#define AON_GPADC_RAW_DATA_LEN          (12U)
+#define AON_GPADC_RAW_DATA_MSK          (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)
+#define AON_GPADC_RAW_DATA_UMSK         (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS))
+
+/* 0x938 : gpadc_reg_define */
+#define AON_GPADC_REG_DEFINE_OFFSET (0x938)
+#define AON_GPADC_OS_CAL_DATA       AON_GPADC_OS_CAL_DATA
+#define AON_GPADC_OS_CAL_DATA_POS   (0U)
+#define AON_GPADC_OS_CAL_DATA_LEN   (16U)
+#define AON_GPADC_OS_CAL_DATA_MSK   (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)
+#define AON_GPADC_OS_CAL_DATA_UMSK  (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS))
+
+/* 0x93C : hbncore_resv0 */
+#define AON_HBNCORE_RESV0_OFFSET    (0x93C)
+#define AON_HBNCORE_RESV0_DATA      AON_HBNCORE_RESV0_DATA
+#define AON_HBNCORE_RESV0_DATA_POS  (0U)
+#define AON_HBNCORE_RESV0_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV0_DATA_MSK  (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)
+#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS))
+
+/* 0x940 : hbncore_resv1 */
+#define AON_HBNCORE_RESV1_OFFSET    (0x940)
+#define AON_HBNCORE_RESV1_DATA      AON_HBNCORE_RESV1_DATA
+#define AON_HBNCORE_RESV1_DATA_POS  (0U)
+#define AON_HBNCORE_RESV1_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV1_DATA_MSK  (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)
+#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS))
+
+/* 0xf00 : hbnram ctrl */
+#define AON_TZC_HBNRAM_CTRL_OFFSET  (0xF00)
+#define AON_TZC_HBNRAM_R0_EN        AON_TZC_HBNRAM_R0_EN
+#define AON_TZC_HBNRAM_R0_EN_POS    (16U)
+#define AON_TZC_HBNRAM_R0_EN_LEN    (1U)
+#define AON_TZC_HBNRAM_R0_EN_MSK    (((1U << AON_TZC_HBNRAM_R0_EN_LEN) - 1) << AON_TZC_HBNRAM_R0_EN_POS)
+#define AON_TZC_HBNRAM_R0_EN_UMSK   (~(((1U << AON_TZC_HBNRAM_R0_EN_LEN) - 1) << AON_TZC_HBNRAM_R0_EN_POS))
+#define AON_TZC_HBNRAM_R0_LOCK      AON_TZC_HBNRAM_R0_LOCK
+#define AON_TZC_HBNRAM_R0_LOCK_POS  (24U)
+#define AON_TZC_HBNRAM_R0_LOCK_LEN  (1U)
+#define AON_TZC_HBNRAM_R0_LOCK_MSK  (((1U << AON_TZC_HBNRAM_R0_LOCK_LEN) - 1) << AON_TZC_HBNRAM_R0_LOCK_POS)
+#define AON_TZC_HBNRAM_R0_LOCK_UMSK (~(((1U << AON_TZC_HBNRAM_R0_LOCK_LEN) - 1) << AON_TZC_HBNRAM_R0_LOCK_POS))
+
+/* 0xf04 : hbnram r0 */
+#define AON_TZC_HBNRAM_R0_OFFSET     (0xF04)
+#define AON_TZC_HBNRAM_R0_END        AON_TZC_HBNRAM_R0_END
+#define AON_TZC_HBNRAM_R0_END_POS    (0U)
+#define AON_TZC_HBNRAM_R0_END_LEN    (11U)
+#define AON_TZC_HBNRAM_R0_END_MSK    (((1U << AON_TZC_HBNRAM_R0_END_LEN) - 1) << AON_TZC_HBNRAM_R0_END_POS)
+#define AON_TZC_HBNRAM_R0_END_UMSK   (~(((1U << AON_TZC_HBNRAM_R0_END_LEN) - 1) << AON_TZC_HBNRAM_R0_END_POS))
+#define AON_TZC_HBNRAM_R0_START      AON_TZC_HBNRAM_R0_START
+#define AON_TZC_HBNRAM_R0_START_POS  (16U)
+#define AON_TZC_HBNRAM_R0_START_LEN  (11U)
+#define AON_TZC_HBNRAM_R0_START_MSK  (((1U << AON_TZC_HBNRAM_R0_START_LEN) - 1) << AON_TZC_HBNRAM_R0_START_POS)
+#define AON_TZC_HBNRAM_R0_START_UMSK (~(((1U << AON_TZC_HBNRAM_R0_START_LEN) - 1) << AON_TZC_HBNRAM_R0_START_POS))
+
+
+struct aon_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[2048];
+
+    /* 0x800 : aon */
+    union {
+        struct {
+            uint32_t aon_resv              : 8; /* [ 7: 0],        r/w,        0xf */
+            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t pu_aon_dc_tbuf        : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_19        : 7; /* [19:13],       rsvd,        0x0 */
+            uint32_t ldo11_rt_pulldown     : 1; /* [   20],        r/w,        0x0 */
+            uint32_t ldo11_rt_pulldown_sel : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sw_pu_ldo11_rt        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23_31        : 9; /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon;
+
+    /* 0x804 : aon_common */
+    union {
+        struct {
+            uint32_t tmux_aon         : 3;  /* [ 2: 0],        r/w,        0x0 */
+            uint32_t reserved_3       : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t ten_aon          : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_7     : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t ten_vddcore_aon  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t ten_ldo11soc_aon : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t ten_dcdc_0_aon   : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ten_dcdc_1_aon   : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t ten_bg_sys_aon   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15   : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t ten_ldo15rf_aon  : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t ten_xtal_aon     : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t dten_xtal_aon    : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t ten_mbg_aon      : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t ten_cip_misc_aon : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31   : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_common;
+
+    /* 0x808 : aon_misc */
+    union {
+        struct {
+            uint32_t sw_soc_en_aon : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t sw_wb_en_aon  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_misc;
+
+    /* 0x80c  reserved */
+    uint8_t RESERVED0x80c[4];
+
+    /* 0x810 : bg_sys_top */
+    union {
+        struct {
+            uint32_t pu_bg_sys_aon   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t istart_ctrl_aon : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_7    : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t pmip_resv_aon   : 8;  /* [15: 8],        r/w,        0x0 */
+            uint32_t reserved_16_31  : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bg_sys_top;
+
+    /* 0x814 : dcdc_top_0 */
+    union {
+        struct {
+            uint32_t dcdc_vout_sel_aon          : 5; /* [ 4: 0],        r/w,       0x1b */
+            uint32_t reserved_5_7               : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t dcdc_vpfm_aon              : 4; /* [11: 8],        r/w,        0x7 */
+            uint32_t dcdc_osc_2m_mode_aon       : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15             : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc_osc_freq_trim_aon     : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc_slope_curr_sel_aon    : 5; /* [24:20],        r/w,        0x5 */
+            uint32_t dcdc_en_stop_osc_aon       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t dcdc_en_slow_osc_aon       : 1; /* [   26],        r/w,        0x0 */
+            uint32_t dcdc_en_osc_inhibit_t2_aon : 1; /* [   27],        r/w,        0x0 */
+            uint32_t dcdc_sstart_time_aon       : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t dcdc_dis_aon               : 1; /* [   30],        r/w,        0x0 */
+            uint32_t dcdc_rdy_aon               : 1; /* [   31],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } dcdc_top_0;
+
+    /* 0x818 : dcdc_top_1 */
+    union {
+        struct {
+            uint32_t dcdc_force_en_cs_zvs_aon : 1; /* [    0],        r/w,        0x0 */
+            uint32_t dcdc_cs_delay_aon        : 3; /* [ 3: 1],        r/w,        0x4 */
+            uint32_t dcdc_zvs_td_opt_aon      : 3; /* [ 6: 4],        r/w,        0x4 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t dcdc_nonoverlap_td_aon   : 5; /* [12: 8],        r/w,        0x0 */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc_rc_sel_aon          : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc_chf_sel_aon         : 4; /* [23:20],        r/w,        0x1 */
+            uint32_t dcdc_cfb_sel_aon         : 4; /* [27:24],        r/w,        0x8 */
+            uint32_t dcdc_en_antiring_aon     : 1; /* [   28],        r/w,        0x1 */
+            uint32_t dcdc_pulldown_aon        : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31           : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dcdc_top_1;
+
+    /* 0x81C : ldo11soc_and_dctest */
+    union {
+        struct {
+            uint32_t ldo11soc_vout_trim_aon    : 4;  /* [ 3: 0],        r/w,        0x8 */
+            uint32_t pu_ldo11soc_aon           : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t ldo11soc_sstart_en_aon    : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7              : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t ldo11soc_sstart_delay_aon : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_aon     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_sel_aon : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t ldo11soc_vth_sel_aon      : 2;  /* [13:12],        r/w,        0x1 */
+            uint32_t reserved_14_23            : 10; /* [23:14],       rsvd,        0x0 */
+            uint32_t ldo11soc_cc_aon           : 2;  /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27            : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t ldo11soc_rdy_aon          : 1;  /* [   28],          r,        0x1 */
+            uint32_t ldo11soc_power_good_aon   : 1;  /* [   29],          r,        0x1 */
+            uint32_t reserved_30               : 1;  /* [   30],       rsvd,        0x0 */
+            uint32_t pmip_dc_tp_out_en_aon     : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ldo11soc_and_dctest;
+
+    /* 0x820 : psw_irrcv */
+    union {
+        struct {
+            uint32_t pu_ir_psw_aon : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psw_irrcv;
+
+    /* 0x824 : dcdc_top_2 */
+    union {
+        struct {
+            uint32_t dcdc_vout_trim_aon     : 4; /* [ 3: 0],        r/w,        0x8 */
+            uint32_t dcdc_osc_ss_rstn_aon   : 1; /* [    4],        r/w,        0x0 */
+            uint32_t dcdc_osc_ss_en_aon     : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7           : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t dcdc_osc_ss_period_aon : 2; /* [ 9: 8],        r/w,        0x0 */
+            uint32_t dcdc_osc_ss_fdev_aon   : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t dcdc_comp_gm_sel_aon   : 3; /* [14:12],        r/w,        0x4 */
+            uint32_t reserved_15            : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t dcdc_isense_trim_aon   : 3; /* [18:16],        r/w,        0x4 */
+            uint32_t reserved_19            : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t dcdc_vc_clamp_vth_aon  : 3; /* [22:20],        r/w,        0x4 */
+            uint32_t reserved_23            : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t dcdc_ocp_vth_aon       : 3; /* [26:24],        r/w,        0x4 */
+            uint32_t dcdc_ocp_rst_aon       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t dcdc_ocp_out_aon       : 1; /* [   28],          r,        0x0 */
+            uint32_t dcdc_drv_sr_aon        : 2; /* [30:29],        r/w,        0x3 */
+            uint32_t reserved_31            : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dcdc_top_2;
+
+    /* 0x828 : vddcore_psw */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } vddcore_psw;
+
+    /* 0x82C : psw_misc */
+    union {
+        struct {
+            uint32_t pu_psw_irrcv_aon      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_18         : 18; /* [18: 1],       rsvd,        0x0 */
+            uint32_t usb20_rref_ext_en_aon : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t en_por33_aon          : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t usb20_rref_hiz_aon    : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23        : 2;  /* [23:22],       rsvd,        0x0 */
+            uint32_t usb20_rcal_code_aon   : 6;  /* [29:24],        r/w,       0x1a */
+            uint32_t reserved_30_31        : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psw_misc;
+
+    /* 0x830  reserved */
+    uint8_t RESERVED0x830[80];
+
+    /* 0x880 : rf_top_aon */
+    union {
+        struct {
+            uint32_t pu_mbg_aon               : 1; /* [    0],        r/w,        0x1 */
+            uint32_t pu_ldo15rf_aon           : 1; /* [    1],        r/w,        0x1 */
+            uint32_t pu_sfreg_aon             : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3               : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t pu_xtal_buf_aon          : 1; /* [    4],        r/w,        0x1 */
+            uint32_t pu_xtal_aon              : 1; /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7             : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t ldo15rf_sstart_sel_aon   : 1; /* [    8],        r/w,        0x1 */
+            uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t ldo15rf_pulldown_aon     : 1; /* [   12],        r/w,        0x0 */
+            uint32_t ldo15rf_pulldown_sel_aon : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t ldo15rf_vout_sel_aon     : 3; /* [18:16],        r/w,        0x2 */
+            uint32_t reserved_19_23           : 5; /* [23:19],       rsvd,        0x0 */
+            uint32_t ldo15rf_cc_aon           : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26              : 1; /* [   26],       rsvd,        0x0 */
+            uint32_t ldo15rf_bypass_aon       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t ldo15rf_vout_trim_aon    : 4; /* [31:28],        r/w,        0x7 */
+        } BF;
+        uint32_t WORD;
+    } rf_top_aon;
+
+    /* 0x884 : xtal_cfg */
+    union {
+        struct {
+            uint32_t xtal_bk_aon            : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t xtal_capcode_extra_aon : 1; /* [    2],        r/w,        0x0 */
+            uint32_t xtal_ext_sel_aon       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t xtal_buf_en_aon        : 2; /* [ 5: 4],        r/w,        0x3 */
+            uint32_t xtal_acbuf_en_aon      : 1; /* [    6],        r/w,        0x1 */
+            uint32_t xtal_acbuf_mode_aon    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t xtal_buf_hp_aon        : 2; /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10            : 1; /* [   10],       rsvd,        0x0 */
+            uint32_t xtal_socbuf_en_aon     : 1; /* [   11],        r/w,        0x1 */
+            uint32_t xtal_fast_startup_aon  : 1; /* [   12],        r/w,        0x1 */
+            uint32_t xtal_sleep_aon         : 1; /* [   13],        r/w,        0x1 */
+            uint32_t xtal_amp_ctrl_aon      : 2; /* [15:14],        r/w,        0x3 */
+            uint32_t xtal_capcode_out_aon   : 6; /* [21:16],        r/w,       0x10 */
+            uint32_t xtal_capcode_in_aon    : 6; /* [27:22],        r/w,       0x10 */
+            uint32_t xtal_gm_boost_aon      : 2; /* [29:28],        r/w,        0x3 */
+            uint32_t xtal_rdy_sel_aon       : 2; /* [31:30],        r/w,        0x2 */
+        } BF;
+        uint32_t WORD;
+    } xtal_cfg;
+
+    /* 0x888 : tsen */
+    union {
+        struct {
+            uint32_t tsen_refcode_corner  : 12; /* [11: 0],        r/w,      0x8ff */
+            uint32_t reserved_12_15       : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t tsen_refcode_rfcal   : 12; /* [27:16],        r/w,      0x8ff */
+            uint32_t xtal_rdy             : 1;  /* [   28],          r,        0x1 */
+            uint32_t xtal_inn_cfg_en_aon  : 1;  /* [   29],        r/w,        0x1 */
+            uint32_t xtal_rdy_int_sel_aon : 2;  /* [31:30],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } tsen;
+
+    /* 0x88c  reserved */
+    uint8_t RESERVED0x88c[116];
+
+    /* 0x900 : acomp0_ctrl */
+    union {
+        struct {
+            uint32_t acomp0_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp0_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp0_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp0_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp0_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp0_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp0_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp0_ctrl;
+
+    /* 0x904 : acomp1_ctrl */
+    union {
+        struct {
+            uint32_t acomp1_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp1_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp1_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp1_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp1_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp1_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp1_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp1_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp1_ctrl;
+
+    /* 0x908 : acomp_ctrl */
+    union {
+        struct {
+            uint32_t acomp1_rstn_ana : 1; /* [    0],        r/w,        0x1 */
+            uint32_t acomp0_rstn_ana : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_7    : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t acomp1_test_en  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t acomp0_test_en  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t acomp1_test_sel : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_test_sel : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t reserved_14_16  : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t acomp1_out_raw  : 1; /* [   17],          r,        0x0 */
+            uint32_t reserved_18     : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t acomp0_out_raw  : 1; /* [   19],          r,        0x0 */
+            uint32_t reserved_20_23  : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t acomp_vref_sel  : 6; /* [29:24],        r/w,        0x0 */
+            uint32_t acomp_reserved  : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp_ctrl;
+
+    /* 0x90C : gpadc_reg_cmd */
+    union {
+        struct {
+            uint32_t gpadc_global_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_conv_start       : 1; /* [    1],        r/w,        0x0 */
+            uint32_t gpadc_soft_rst         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_neg_sel          : 5; /* [ 7: 3],        r/w,        0xf */
+            uint32_t gpadc_pos_sel          : 5; /* [12: 8],        r/w,        0xf */
+            uint32_t gpadc_neg_gnd          : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_micbias_en       : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_micpga_en        : 1; /* [   15],        r/w,        0x0 */
+            uint32_t gpadc_byp_micboost     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t gpadc_rcal_en          : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_dwa_en           : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_mic2_diff        : 1; /* [   19],        r/w,        0x0 */
+            uint32_t gpadc_mic1_diff        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpadc_mic_pga2_gain    : 2; /* [22:21],        r/w,        0x0 */
+            uint32_t gpadc_micboost_32db_en : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_26         : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t gpadc_chip_sen_pu      : 1; /* [   27],        r/w,        0x0 */
+            uint32_t gpadc_sen_sel          : 3; /* [30:28],        r/w,        0x0 */
+            uint32_t gpadc_sen_test_en      : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_cmd;
+
+    /* 0x910 : gpadc_reg_config1 */
+    union {
+        struct {
+            uint32_t gpadc_cal_os_en      : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_cont_conv_en   : 1; /* [    1],        r/w,        0x1 */
+            uint32_t gpadc_res_sel        : 3; /* [ 4: 2],        r/w,        0x0 */
+            uint32_t reserved_5_7         : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t gpadc_vcm_sel_en     : 1; /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_vcm_hyst_sel   : 1; /* [    9],        r/w,        0x0 */
+            uint32_t gpadc_lowv_det_en    : 1; /* [   10],        r/w,        0x0 */
+            uint32_t gpadc_pwm_trg_en     : 1; /* [   11],        r/w,        0x0 */
+            uint32_t gpadc_clk_ana_dly    : 4; /* [15:12],        r/w,        0x0 */
+            uint32_t gpadc_clk_ana_dly_en : 1; /* [   16],        r/w,        0x0 */
+            uint32_t gpadc_clk_ana_inv    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_clk_div_ratio  : 3; /* [20:18],        r/w,        0x3 */
+            uint32_t gpadc_scan_length    : 4; /* [24:21],        r/w,        0x0 */
+            uint32_t gpadc_scan_en        : 1; /* [   25],        r/w,        0x0 */
+            uint32_t gpadc_dither_en      : 1; /* [   26],        r/w,        0x0 */
+            uint32_t gpadc_v11_sel        : 2; /* [28:27],        r/w,        0x0 */
+            uint32_t gpadc_v18_sel        : 2; /* [30:29],        r/w,        0x0 */
+            uint32_t reserved_31          : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config1;
+
+    /* 0x914 : gpadc_reg_config2 */
+    union {
+        struct {
+            uint32_t reserved_0_1      : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t gpadc_diff_mode   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_vref_sel    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t gpadc_vbat_en     : 1; /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_tsext_sel   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t gpadc_ts_en       : 1; /* [    6],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcm     : 2; /* [ 8: 7],        r/w,        0x2 */
+            uint32_t gpadc_pga_os_cal  : 4; /* [12: 9],        r/w,        0x8 */
+            uint32_t gpadc_pga_en      : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcmi_en : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_chop_mode   : 2; /* [16:15],        r/w,        0x3 */
+            uint32_t gpadc_bias_sel    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_test_en     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_test_sel    : 3; /* [21:19],        r/w,        0x0 */
+            uint32_t gpadc_pga2_gain   : 3; /* [24:22],        r/w,        0x0 */
+            uint32_t gpadc_pga1_gain   : 3; /* [27:25],        r/w,        0x0 */
+            uint32_t gpadc_dly_sel     : 3; /* [30:28],        r/w,        0x0 */
+            uint32_t gpadc_tsvbe_low   : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config2;
+
+    /* 0x918 : adc converation sequence 1 */
+    union {
+        struct {
+            uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos1;
+
+    /* 0x91C : adc converation sequence 2 */
+    union {
+        struct {
+            uint32_t gpadc_scan_pos_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos2;
+
+    /* 0x920 : adc converation sequence 3 */
+    union {
+        struct {
+            uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg1;
+
+    /* 0x924 : adc converation sequence 4 */
+    union {
+        struct {
+            uint32_t gpadc_scan_neg_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg2;
+
+    /* 0x928 : gpadc_reg_status */
+    union {
+        struct {
+            uint32_t gpadc_data_rdy : 1;  /* [    0],          r,        0x0 */
+            uint32_t reserved_1_15  : 15; /* [15: 1],       rsvd,        0x0 */
+            uint32_t gpadc_reserved : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_status;
+
+    /* 0x92C : gpadc_reg_isr */
+    union {
+        struct {
+            uint32_t gpadc_neg_satur      : 1;  /* [    0],          r,        0x0 */
+            uint32_t gpadc_pos_satur      : 1;  /* [    1],          r,        0x0 */
+            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_clr  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_clr  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_mask : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_mask : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31       : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_isr;
+
+    /* 0x930 : gpadc_reg_result */
+    union {
+        struct {
+            uint32_t gpadc_data_out : 26; /* [25: 0],          r,  0x1ef0000 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_result;
+
+    /* 0x934 : gpadc_reg_raw_result */
+    union {
+        struct {
+            uint32_t gpadc_raw_data : 12; /* [11: 0],          r,        0x0 */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_raw_result;
+
+    /* 0x938 : gpadc_reg_define */
+    union {
+        struct {
+            uint32_t gpadc_os_cal_data : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31    : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_define;
+
+    /* 0x93C : hbncore_resv0 */
+    union {
+        struct {
+            uint32_t hbncore_resv0_data : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv0;
+
+    /* 0x940 : hbncore_resv1 */
+    union {
+        struct {
+            uint32_t hbncore_resv1_data : 32; /* [31: 0],        r/w, 0xffffffff */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv1;
+};
+
+typedef volatile struct aon_reg aon_reg_t;
+
+#endif /* __AON_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/bl616.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/bl616.h
new file mode 100755
index 0000000000..b29cd69273
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/bl616.h
@@ -0,0 +1,354 @@
+#ifndef __BL616_H__
+#define __BL616_H__
+
+/** @addtogroup Configuration_section_for_RISCV
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Processor and Core Peripherals
+   */
+
+#define CORE_ID_ADDRESS       (0xF0000000)
+#define CORE_ID_M0            (0xE9070000)
+#define CORE_ID_D0            (0xDEAD5500)
+#define CORE_ID_LP            (0xDEADE902)
+
+#define CORE_M0_JTAG_TCK_PIN  (GLB_GPIO_PIN_27)
+#define CORE_M0_JTAG_TMS_PIN  (GLB_GPIO_PIN_28)
+#define CORE_M0_JTAG_TCK_FUNC (GPIO_FUN_M_CJTAG)
+#define CORE_M0_JTAG_TMS_FUNC (GPIO_FUN_M_CJTAG)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+#ifdef ARCH_ARM
+#define IRQ_NUM_BASE 0
+#endif
+
+#ifdef ARCH_RISCV
+#if (__riscv_xlen == 64)
+#define IRQ_NUM_BASE 16 /* PLIC ===> MEXT_IRQn */
+#else
+#define IRQ_NUM_BASE 16
+#endif
+#endif
+/**
+ * @brief BL616 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum {
+#ifdef ARCH_ARM
+    /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+    NonMaskableInt_IRQn = -14,   /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+    HardFault_IRQn = -13,        /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+    BusFault_IRQn = -11,         /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+    UsageFault_IRQn = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+    SVCall_IRQn = -5,            /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+    DebugMonitor_IRQn = -4,      /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+    PendSV_IRQn = -2,            /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+    SysTick_IRQn = -1,           /*!< 15 Cortex-M4 System Tick Interrupt                                */
+#endif
+#ifdef ARCH_RISCV
+    SSOFT_IRQn = 1,           /*!< 1 RISCV supervisor software Interrupt                             */
+    MSOFT_IRQn = 3,           /*!< 3 RISCV machine software Interrupt                                */
+    STIME_IRQn = 5,           /*!< 5 RISCV supervisor time Interrupt                                 */
+    MTIME_IRQn = 7,           /*!< 7 RISCV machine time Interrupt                                    */
+    SEXT_IRQn = 9,            /*!< 9 RISCV S-mode external  Interrupt                                */
+    MEXT_IRQn = 11,           /*!< 11 RISCV M-mode external  Interrupt                               */
+    CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending  Interrupt                         */
+#if (__riscv_xlen == 64)
+    HPM_OVF_IRQn = 17, /*!< 17 RISCV HPM counter overflow Interrupt                           */
+#endif
+#endif
+    /******  BL616 specific Interrupt Numbers **********************************************************************/
+    BMX_MCU_BUS_ERR_IRQn = IRQ_NUM_BASE + 0,                    /*!< bmx mcu bus_err_int Interrupt                                     */
+    BMX_MCU_TO_IRQn = IRQ_NUM_BASE + 1,                         /*!< bmx_timeout_int|mcu_timeout_int Interrupt                         */
+    DBI_IRQn = IRQ_NUM_BASE + 2,                                /*!< DBI Interrupt                                                     */
+    SDU_SOFT_RST_IRQn = IRQ_NUM_BASE + 3,                       /*!< SDU software reset Interrupt                                                */
+    AUDIO_IRQn = IRQ_NUM_BASE + 4,                              /*!< Audio Interrupt                                                   */
+    RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5,                        /*!< RF_TOP_INT0 Interrupt                                             */
+    RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6,                        /*!< RF_TOP_INT1 Interrupt                                             */
+    SDIO_IRQn = IRQ_NUM_BASE + 7,                               /*!< SDIO Interrupt                                        */
+    WIFI_TBTT_SLEEP_IRQn = IRQ_NUM_BASE + 8,                    /*!< gauge_itf_int Interrupt                                           */
+    SEC_ENG_ID1_SHA_AES_TRNG_PKA_GMAC_IRQn = IRQ_NUM_BASE + 9,  /*!< sec_eng_id1 Interrupt                                             */
+    SEC_ENG_ID0_SHA_AES_TRNG_PKA_GMAC_IRQn = IRQ_NUM_BASE + 10, /*!< sec_eng_id0 Interrupt                                             */
+    SEC_ENG_ID1_CDET_IRQn = IRQ_NUM_BASE + 11,                  /*!< sec_eng_id1_cdet  Interrupt                                       */
+    SEC_ENG_ID0_CDET_IRQn = IRQ_NUM_BASE + 12,                  /*!< sec_eng_id0_cdet Interrupt                                        */
+    SF_CTRL_ID1_IRQn = IRQ_NUM_BASE + 13,                       /*!< sf_ctrl_id1 Interrupt                                             */
+    SF_CTRL_ID0_IRQn = IRQ_NUM_BASE + 14,                       /*!< sf_ctrl_id0 Interrupt                                             */
+    DMA0_ALL_IRQn = IRQ_NUM_BASE + 15,                          /*!< DMA0_INTR_ALL Interrupt                                           */
+    DVP2BUS_INT0_IRQn = IRQ_NUM_BASE + 16,                      /*!< DVP2BUS_INTR_ALL Interrupt                                           */
+    SDH_IRQn = IRQ_NUM_BASE + 17,                               /*!< sdh Interrupt                                                     */
+    DVP2BUS_INT1_IRQn = IRQ_NUM_BASE + 18,                      /*!< MM System All Interrupt                                           */
+    WIFI_TBTT_WAKEUP_IRQn = IRQ_NUM_BASE + 19,                  /*!< IR TX Interrupt                                                   */
+    IRRX_IRQn = IRQ_NUM_BASE + 20,                              /*!< IR RX Interrupt                                                   */
+    USB_IRQn = IRQ_NUM_BASE + 21,                               /*!< USB  Interrupt                                                    */
+    AUPDM_IRQn = IRQ_NUM_BASE + 22,                             /*!< aupdm_int Interrupt                                               */
+    MJPEG_IRQn = IRQ_NUM_BASE + 23,                             /*!< reserved Interrupt                                                */
+    EMAC_IRQn = IRQ_NUM_BASE + 24,                              /*!< EMAC  Interrupt                                                   */
+    GPADC_DMA_IRQn = IRQ_NUM_BASE + 25,                         /*!< GPADC_DMA Interrupt                                               */
+    EFUSE_IRQn = IRQ_NUM_BASE + 26,                             /*!< Efuse Interrupt                                                   */
+    SPI0_IRQn = IRQ_NUM_BASE + 27,                              /*!< SPI0  Interrupt                                                   */
+    UART0_IRQn = IRQ_NUM_BASE + 28,                             /*!< UART0 Interrupt                                                   */
+    UART1_IRQn = IRQ_NUM_BASE + 29,                             /*!< UART1 Interrupt                                                   */
+    ISO11898_IRQn = IRQ_NUM_BASE + 30,                          /*!< ISO11898 Interrupt                                                */
+    GPIO_DMA_IRQn = IRQ_NUM_BASE + 31,                          /*!< GPIO DMA Interrupt                                                */
+    I2C0_IRQn = IRQ_NUM_BASE + 32,                              /*!< I2C0  Interrupt                                                   */
+    PWM_IRQn = IRQ_NUM_BASE + 33,                               /*!< PWM Interrupt                                                     */
+    RESERVED0_IRQn = IRQ_NUM_BASE + 34,                         /*!< RESERVED Interrupt                                                */
+    RESERVED1_IRQn = IRQ_NUM_BASE + 35,                         /*!< RESERVED Interrupt                                                */
+    TIMER0_CH0_IRQn = IRQ_NUM_BASE + 36,                        /*!< Timer0 Channel 0 Interrupt                                        */
+    TIMER0_CH1_IRQn = IRQ_NUM_BASE + 37,                        /*!< Timer0 Channel 1 Interrupt                                        */
+    TIMER0_WDT_IRQn = IRQ_NUM_BASE + 38,                        /*!< Timer0 Watch Dog Interrupt                                        */
+    I2C1_IRQn = IRQ_NUM_BASE + 39,                              /*!< I2C1  Interrupt                                                   */
+    I2S_IRQn = IRQ_NUM_BASE + 40,                               /*!< I2S  Interrupt                                                    */
+    ANA_OCP_OUT_TO_CPU_0_IRQn = IRQ_NUM_BASE + 41,              /*!< ana_ocp_out_to_cpu_irq0 Interrupt                                 */
+    ANA_OCP_OUT_TO_CPU_1_IRQn = IRQ_NUM_BASE + 42,              /*!< ana_ocp_out_to_cpu_irq1 Interrupt                                 */
+    XTAL_RDY_SCAN_IRQn = IRQ_NUM_BASE + 43,                     /*!< ana_ocp_out_to_cpu_irq2 Interrupt                                 */
+    GPIO_INT0_IRQn = IRQ_NUM_BASE + 44,                         /*!< GPIO Interrupt                                                    */
+    DM_IRQn = IRQ_NUM_BASE + 45,                                /*!< DM Interrupt                                                      */
+    BT_IRQn = IRQ_NUM_BASE + 46,                                /*!< BT Interrupt                                                      */
+    M154_REQ_ACK_IRQn = IRQ_NUM_BASE + 47,                      /*!< M154 req enh ack Interrupt                                        */
+    M154_INT_IRQn = IRQ_NUM_BASE + 48,                          /*!< M154 Interrupt                                                    */
+    M154_AES_IRQn = IRQ_NUM_BASE + 49,                          /*!< m154 aes Interrupt                                                */
+    PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50,                        /*!< PDS Wakeup Interrupt                                              */
+    HBN_OUT0_IRQn = IRQ_NUM_BASE + 51,                          /*!< Hibernate out 0 Interrupt                                         */
+    HBN_OUT1_IRQn = IRQ_NUM_BASE + 52,                          /*!< Hibernate out 1 Interrupt                                         */
+    BOD_IRQn = IRQ_NUM_BASE + 53,                               /*!< BOR Interrupt                                                     */
+    WIFI_IRQn = IRQ_NUM_BASE + 54,                              /*!< WIFI To CPU Interrupt                                             */
+    BZ_PHY_INT_IRQn = IRQ_NUM_BASE + 55,                        /*!< BZ phy Interrupt                                                  */
+    BLE_IRQn = IRQ_NUM_BASE + 56,                               /*!< BLE Interrupt                                                     */
+    MAC_INT_TIMER_IRQn = IRQ_NUM_BASE + 57,                     /*!< MAC Tx Rx Timer Interrupt                                         */
+    MAC_INT_MISC_IRQn = IRQ_NUM_BASE + 58,                      /*!< MAC Tx Rx Misc Interrupt                                          */
+    MAC_INT_RX_TRIGGER_IRQn = IRQ_NUM_BASE + 59,                /*!< MAC Rx Trigger Interrupt                                          */
+    MAC_INT_TX_TRIGGER_IRQn = IRQ_NUM_BASE + 60,                /*!< MAC tx Trigger Interrupt                                          */
+    MAC_INT_GEN_IRQn = IRQ_NUM_BASE + 61,                       /*!< MAC Gen Interrupt                                                 */
+    MAC_INT_PROT_TRIGGER_IRQn = IRQ_NUM_BASE + 62,              /*!< MAC Prot Trigger Interrupt                                        */
+    WIFI_IPC_IRQn = IRQ_NUM_BASE + 63,                          /*!< WIFI Ipc Interrupt                                                */
+    IRQn_LAST,
+} IRQn_Type;
+
+/**
+ * @brief BL616 Memory Map Definitions
+ */
+#define BL616_OCRAM_BASE                     (0x20FC0000)
+#define BL616_OCRAM_END                      (0x20FC0000 + 320 * 1024)
+#define BL616_OCRAM_CACHEABLE_BASE           (0x60FC0000)
+#define BL616_OCRAM_CACHEABLE_END            (0x60FC0000 + 320 * 1024)
+#define BL616_OCRAM_BUSREMAP_BASE            (0x22FC0000)
+#define BL616_OCRAM_BUSREMAP_END             (0x22FC0000 + 320 * 1024)
+#define BL616_OCRAM_BUSREMAP_CACHEABLE_BASE  (0x62FC0000)
+#define BL616_OCRAM_BUSREMAP_CACHEABLE_END   (0x62FC0000 + 320 * 1024)
+
+#define BL616_WRAM_BASE                      (0x21010000)
+#define BL616_WRAM_END                       (0x21010000 + 160 * 1024)
+#define BL616_WRAM_CACHEABLE_BASE            (0x61010000)
+#define BL616_WRAM_CACHEABLE_END             (0x61010000 + 160 * 1024)
+#define BL616_WRAM_BUSREMAP_BASE             (0x23010000)
+#define BL616_WRAM_BUSREMAP_END              (0x23010000 + 160 * 1024)
+#define BL616_WRAM_BUSREMAP_CACHEABLE_BASE   (0x63010000)
+#define BL616_WRAM_BUSREMAP_CACHEABLE_END    (0x63010000 + 160 * 1024)
+
+#define BL616_FLASH_XIP_BASE                 (0xA0000000)
+#define BL616_FLASH_XIP_END                  (0xA0000000 + 64 * 1024 * 1024)
+#define BL616_FLASH_XIP_REMAP0_BASE          (0xD0000000)
+#define BL616_FLASH_XIP_REMAP0_END           (0xD0000000 + 64 * 1024 * 1024)
+#define BL616_FLASH_XIP_BUSREMAP_BASE        (0xA0000000)
+#define BL616_FLASH_XIP_BUSREMAP_END         (0xA0000000 + 64 * 1024 * 1024)
+
+#define BL616_FLASH2_XIP_BASE                (0x84000000)
+#define BL616_FLASH2_XIP_END                 (0x84000000 + 64 * 1024 * 1024)
+#define BL616_FLASH2_XIP_REMAP0_BASE         (0xD4000000)
+#define BL616_FLASH2_XIP_REMAP0_END          (0xD4000000 + 64 * 1024 * 1024)
+#define BL616_FLASH2_XIP_BUSREMAP_BASE       (0xA4000000)
+#define BL616_FLASH2_XIP_BUSREMAP_END        (0xA4000000 + 64 * 1024 * 1024)
+
+#define BL616_PSRAM_BASE                     (0x88000000)
+#define BL616_PSRAM_END                      (0x88000000 + 128 * 1024 * 1024)
+#define BL616_PSRAM_REMAP0_BASE              (0xD8000000)
+#define BL616_PSRAM_REMAP0_END               (0xD8000000 + 128 * 1024 * 1024)
+#define BL616_PSRAM_BUSREMAP_BASE            (0xA8000000)
+#define BL616_PSRAM_BUSREMAP_END             (0xA8000000 + 128 * 1024 * 1024)
+
+#define BL616_ALLRAM_BASE                    (0x20FC0000)
+#define BL616_ALLRAM_END                     (0x20FC0000 + 320 * 1024 + 160 * 1024)
+#define BL616_ALLRAM_CACHEABLE_BASE          (0x60FC0000)
+#define BL616_ALLRAM_CACHEABLE_END           (0x60FC0000 + 320 * 1024 + 160 * 1024)
+#define BL616_ALLRAM_BUSREMAP_BASE           (0x22FC0000)
+#define BL616_ALLRAM_BUSREMAP_END            (0x22FC0000 + 320 * 1024 + 160 * 1024)
+#define BL616_ALLRAM_BUSREMAP_CACHEABLE_BASE (0x62FC0000)
+#define BL616_ALLRAM_BUSREMAP_CACHEABLE_END  (0x62FC0000 + 320 * 1024 + 160 * 1024)
+
+/*@} end of group Memory_Map_Section */
+
+/* BL616 peripherals base address */
+/* WLSYS */
+#define GLB_BASE                             ((uint32_t)0x20000000)
+#define MIX_BASE                             ((uint32_t)0x20001000)
+#define GPIP_BASE                            ((uint32_t)0x20002000)
+#define PHY_BASE                             ((uint32_t)0x20002800)
+#define AGC_BASE                             ((uint32_t)0x20002c00)
+#define SEC_DBG_BASE                         ((uint32_t)0x20003000)
+#define SEC_ENG_BASE                         ((uint32_t)0x20004000)
+#define TZ1_BASE                             ((uint32_t)0x20005000)
+#define TZC_SEC_BASE                         ((uint32_t)0x20005000)
+#define TZ2_BASE                             ((uint32_t)0x20006000)
+#define TZC_NSEC_BASE                        ((uint32_t)0x20006000)
+#define CCI_BASE                             ((uint32_t)0x20008000)
+#define MCU_MISC_BASE                        ((uint32_t)0x20009000)
+#define L1C_BASE                             ((uint32_t)0x20009000)
+#define UART0_BASE                           ((uint32_t)0x2000a000)
+#define UART1_BASE                           ((uint32_t)0x2000a100)
+#define SPI_BASE                             ((uint32_t)0x2000a200)
+#define I2C0_BASE                            ((uint32_t)0x2000a300)
+#define PWM_BASE                             ((uint32_t)0x2000a400)
+#define TIMER_BASE                           ((uint32_t)0x2000a500)
+#define IR_BASE                              ((uint32_t)0x2000a600)
+#define CKS_BASE                             ((uint32_t)0x2000a700)
+#define DBI_BASE                             ((uint32_t)0x2000a800)
+#define I2C1_BASE                            ((uint32_t)0x2000a900)
+#define ISO11898_BASE                        ((uint32_t)0x2000aa00)
+#define I2S_BASE                             ((uint32_t)0x2000ab00)
+#define AUADC_BASE                           ((uint32_t)0x2000ac00)
+#define QSPI_BASE                            ((uint32_t)0x2000b000)
+#define SF_CTRL_BASE                         ((uint32_t)0x2000b000)
+#define SF_CTRL_BUF_BASE                     ((uint32_t)0x2000b600)
+#define DMA_BASE                             ((uint32_t)0x2000c000)
+#define SDU_BASE                             ((uint32_t)0x2000d000)
+#define PDS_BASE                             ((uint32_t)0x2000e000)
+#define HBN_BASE                             ((uint32_t)0x2000f000)
+#define AON_BASE                             ((uint32_t)0x2000f000)
+#define MM_MISC_BASE                         ((uint32_t)0x20050000)
+#define PSRAM_CTRL_BASE                      ((uint32_t)0x20052000)
+#define AUDAC_BASE                           ((uint32_t)0x20055000)
+#define EFUSE_BASE                           ((uint32_t)0x20056000)
+#define EF_DATA_BASE                         ((uint32_t)0x20056000)
+#define EF_CTRL_BASE                         ((uint32_t)0x20056000)
+#define DVP2AXI0_BASE                        ((uint32_t)0x20057000)
+#define DVP2AXI1_BASE                        ((uint32_t)0x20058000)
+#define MJPEG_BASE                           ((uint32_t)0x20059000)
+#define SDH_BASE                             ((uint32_t)0x20060000)
+#define EMAC_BASE                            ((uint32_t)0x20070000)
+#define USB_BASE                             ((uint32_t)0x20072000)
+#define HBN_RAM_BASE                         ((uint32_t)0x20010000)
+
+typedef enum {
+    BL_AHB_MASTER_CPU = 0x00,
+    BL_AHB_MASTER_SDU = 0x01,
+    BL_AHB_MASTER_SEC = 0x02,
+    BL_AHB_MASTER_DMA = 0x03,
+    BL_AHB_MASTER_CCI = 0x04,
+    BL_AHB_MASTER_WIFI_PLATFORM = 0x05,
+    BL_AHB_MASTER_WIFI_MAC_PHY = 0x06,
+    BL_AHB_MASTER_WIFI_PHY = 0x07,
+    BL_AHB_MASTER_MAX = 0x08,
+} BL_AHB_Master_Type;
+
+typedef enum {
+    BL_AHB_SLAVE1_GLB = 0x00,    //cgen rsvd
+    BL_AHB_SLAVE1_RF_TOP = 0x01, //swrst mix
+    BL_AHB_SLAVE1_GPIP = 0x02,
+    BL_AHB_SLAVE1_SEC_DBG = 0x03,
+    BL_AHB_SLAVE1_SEC_ENG = 0x04,
+    BL_AHB_SLAVE1_TZ = 0x05,    //swrst tz1,cgen tz1+tz2
+    BL_AHB_SLAVE1_RSVD6 = 0x06, //swrst tz2,
+    BL_AHB_SLAVE1_EF_CTRL = 0x07,
+    BL_AHB_SLAVE1_CCI = 0x08, //cgen rsvd
+    BL_AHB_SLAVE1_L1C = 0x09, //cgen rsvd
+    BL_AHB_SLAVE1_RSVD10 = 0x0A,
+    BL_AHB_SLAVE1_SF_CTRL = 0x0B,
+    BL_AHB_SLAVE1_DMA = 0x0C,
+    BL_AHB_SLAVE1_SDU = 0x0D, //cgen rsvd
+    BL_AHB_SLAVE1_PDS = 0x0E, //cgen rsvd
+    BL_AHB_SLAVE1_RSVD15 = 0x0F,
+    BL_AHB_SLAVE1_UART0 = 0x10,
+    BL_AHB_SLAVE1_UART1 = 0x11,
+    BL_AHB_SLAVE1_SPI = 0x12,
+    BL_AHB_SLAVE1_I2C = 0x13,
+    BL_AHB_SLAVE1_PWM = 0x14,
+    BL_AHB_SLAVE1_TIMER = 0x15,
+    BL_AHB_SLAVE1_IRR = 0x16,
+    BL_AHB_SLAVE1_CKS = 0x17,
+    BL_AHB_SLAVE1_QDEC = 0x18,
+    BL_AHB_SLAVE1_KYS = 0x19,
+    BL_AHB_SLAVE1_UART2 = 0x1A,
+    BL_AHB_SLAVE1_RSVD27 = 0x1B,
+    BL_AHB_SLAVE1_RSVD28 = 0x1C,
+    BL_AHB_SLAVE1_RSVD29 = 0x1D,
+    BL_AHB_SLAVE1_RSVD30 = 0x1E,
+    BL_AHB_SLAVE1_RSVD31 = 0x1F,
+    BL_AHB_SLAVE1_MAX = 0x20,
+    BL_AHB_SLAVE1_GPADC = 0x21, /* not used for cgen and swrst */
+    BL_AHB_SLAVE1_GPDAC = 0x22, /* not used for cgen and swrst */
+    BL_AHB_SLAVE1_I2S = 0x23,   /* not used for cgen and swrst */
+    BL_AHB_SLAVE1_CAM = 0x24,   /* not used for cgen and swrst */
+} BL_AHB_Slave1_Type;
+
+typedef enum {
+    BL_AHB_SLAVE2_RSVD0 = 0x00,
+    BL_AHB_SLAVE2_RSVD1 = 0x01,
+    BL_AHB_SLAVE2_RSVD2 = 0x02,
+    BL_AHB_SLAVE2_RSVD3 = 0x03,
+    BL_AHB_SLAVE2_WIFI = 0x04,
+    BL_AHB_SLAVE2_RSVD5 = 0x05,
+    BL_AHB_SLAVE2_RSVD6 = 0x06,
+    BL_AHB_SLAVE2_RSVD7 = 0x07,
+    BL_AHB_SLAVE2_BT_BLE = 0x08,
+    BL_AHB_SLAVE2_M154 = 0x09,
+    BL_AHB_SLAVE2_BT_BLE2 = 0x0A,
+    BL_AHB_SLAVE2_M1542 = 0x0B,
+    BL_AHB_SLAVE2_RSVD12 = 0x0C,
+    BL_AHB_SLAVE2_RSVD13 = 0x0D,
+    BL_AHB_SLAVE2_RSVD14 = 0x0E,
+    BL_AHB_SLAVE2_RSVD15 = 0x0F,
+    BL_AHB_SLAVE2_EXT_EMI_MISC = 0x10,
+    BL_AHB_SLAVE2_EXT_PSRAM0_CTRL = 0x11,
+    BL_AHB_SLAVE2_EXT_PSRAM1_CTRL = 0x12,
+    BL_AHB_SLAVE2_EXT_USB = 0x13,
+    BL_AHB_SLAVE2_EXT_MIX2 = 0x14,
+    BL_AHB_SLAVE2_EXT_AUDIO = 0x15,
+    BL_AHB_SLAVE2_EXT_SDH = 0x16,
+    BL_AHB_SLAVE2_EXT_EMAC = 0x17,
+    BL_AHB_SLAVE2_EXT_DMA2 = 0x18,
+    BL_AHB_SLAVE2_EXT_RSVD25 = 0x19,
+    BL_AHB_SLAVE2_EXT_RSVD26 = 0x1A,
+    BL_AHB_SLAVE2_EXT_RSVD27 = 0x1B,
+    BL_AHB_SLAVE2_MAX = 0x1C,
+} BL_AHB_Slave2_Type;
+
+typedef enum {
+    BL_AHB_SEC_ENG_AES0 = 0,
+    BL_AHB_SEC_ENG_AES1,
+    BL_AHB_SEC_ENG_SHA0,
+    BL_AHB_SEC_ENG_SHA1,
+} BL_AHB_Sec_Eng_Type;
+
+typedef enum {
+    BL_AHB_DMA0_CH0 = 0,
+    BL_AHB_DMA0_CH1,
+    BL_AHB_DMA0_CH2,
+    BL_AHB_DMA0_CH3,
+    BL_AHB_DMA0_CH4,
+    BL_AHB_DMA0_CH5,
+    BL_AHB_DMA0_CH6,
+    BL_AHB_DMA0_CH7,
+} BL_AHB_DMA0_CHNL_Type;
+
+/**
+  * @}
+  */
+#include 
+
+/* RISCV CPU include files */
+#ifdef __GNUC__
+#include 
+#endif
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/cci_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/cci_reg.h
new file mode 100755
index 0000000000..640cc53242
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/cci_reg.h
@@ -0,0 +1,777 @@
+/**
+  ******************************************************************************
+  * @file    cci_reg.h
+  * @version V1.0
+  * @date    2021-11-13
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __CCI_REG_H__
+#define __CCI_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : cci_cfg */
+#define CCI_CFG_OFFSET              (0x0)
+#define CCI_EN                      CCI_EN
+#define CCI_EN_POS                  (0U)
+#define CCI_EN_LEN                  (1U)
+#define CCI_EN_MSK                  (((1U << CCI_EN_LEN) - 1) << CCI_EN_POS)
+#define CCI_EN_UMSK                 (~(((1U << CCI_EN_LEN) - 1) << CCI_EN_POS))
+#define CCI_SLV_SEL_CCI2            CCI_SLV_SEL_CCI2
+#define CCI_SLV_SEL_CCI2_POS        (1U)
+#define CCI_SLV_SEL_CCI2_LEN        (1U)
+#define CCI_SLV_SEL_CCI2_MSK        (((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS)
+#define CCI_SLV_SEL_CCI2_UMSK       (~(((1U << CCI_SLV_SEL_CCI2_LEN) - 1) << CCI_SLV_SEL_CCI2_POS))
+#define CCI_MAS_SEL_CCI2            CCI_MAS_SEL_CCI2
+#define CCI_MAS_SEL_CCI2_POS        (2U)
+#define CCI_MAS_SEL_CCI2_LEN        (1U)
+#define CCI_MAS_SEL_CCI2_MSK        (((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS)
+#define CCI_MAS_SEL_CCI2_UMSK       (~(((1U << CCI_MAS_SEL_CCI2_LEN) - 1) << CCI_MAS_SEL_CCI2_POS))
+#define CCI_MAS_HW_MODE             CCI_MAS_HW_MODE
+#define CCI_MAS_HW_MODE_POS         (3U)
+#define CCI_MAS_HW_MODE_LEN         (1U)
+#define CCI_MAS_HW_MODE_MSK         (((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS)
+#define CCI_MAS_HW_MODE_UMSK        (~(((1U << CCI_MAS_HW_MODE_LEN) - 1) << CCI_MAS_HW_MODE_POS))
+#define CCI_REG_M_CCI_SCLK_EN       CCI_REG_M_CCI_SCLK_EN
+#define CCI_REG_M_CCI_SCLK_EN_POS   (4U)
+#define CCI_REG_M_CCI_SCLK_EN_LEN   (1U)
+#define CCI_REG_M_CCI_SCLK_EN_MSK   (((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS)
+#define CCI_REG_M_CCI_SCLK_EN_UMSK  (~(((1U << CCI_REG_M_CCI_SCLK_EN_LEN) - 1) << CCI_REG_M_CCI_SCLK_EN_POS))
+#define CCI_REG_DIV_M_CCI_SCLK      CCI_REG_DIV_M_CCI_SCLK
+#define CCI_REG_DIV_M_CCI_SCLK_POS  (5U)
+#define CCI_REG_DIV_M_CCI_SCLK_LEN  (2U)
+#define CCI_REG_DIV_M_CCI_SCLK_MSK  (((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS)
+#define CCI_REG_DIV_M_CCI_SCLK_UMSK (~(((1U << CCI_REG_DIV_M_CCI_SCLK_LEN) - 1) << CCI_REG_DIV_M_CCI_SCLK_POS))
+#define CCI_CFG_CCI1_PRE_READ       CCI_CFG_CCI1_PRE_READ
+#define CCI_CFG_CCI1_PRE_READ_POS   (7U)
+#define CCI_CFG_CCI1_PRE_READ_LEN   (1U)
+#define CCI_CFG_CCI1_PRE_READ_MSK   (((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS)
+#define CCI_CFG_CCI1_PRE_READ_UMSK  (~(((1U << CCI_CFG_CCI1_PRE_READ_LEN) - 1) << CCI_CFG_CCI1_PRE_READ_POS))
+#define CCI_REG_SCCI_CLK_INV        CCI_REG_SCCI_CLK_INV
+#define CCI_REG_SCCI_CLK_INV_POS    (8U)
+#define CCI_REG_SCCI_CLK_INV_LEN    (1U)
+#define CCI_REG_SCCI_CLK_INV_MSK    (((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS)
+#define CCI_REG_SCCI_CLK_INV_UMSK   (~(((1U << CCI_REG_SCCI_CLK_INV_LEN) - 1) << CCI_REG_SCCI_CLK_INV_POS))
+#define CCI_REG_MCCI_CLK_INV        CCI_REG_MCCI_CLK_INV
+#define CCI_REG_MCCI_CLK_INV_POS    (9U)
+#define CCI_REG_MCCI_CLK_INV_LEN    (1U)
+#define CCI_REG_MCCI_CLK_INV_MSK    (((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS)
+#define CCI_REG_MCCI_CLK_INV_UMSK   (~(((1U << CCI_REG_MCCI_CLK_INV_LEN) - 1) << CCI_REG_MCCI_CLK_INV_POS))
+#define CCI_CFG_MCCI_DLY_R          CCI_CFG_MCCI_DLY_R
+#define CCI_CFG_MCCI_DLY_R_POS      (16U)
+#define CCI_CFG_MCCI_DLY_R_LEN      (1U)
+#define CCI_CFG_MCCI_DLY_R_MSK      (((1U << CCI_CFG_MCCI_DLY_R_LEN) - 1) << CCI_CFG_MCCI_DLY_R_POS)
+#define CCI_CFG_MCCI_DLY_R_UMSK     (~(((1U << CCI_CFG_MCCI_DLY_R_LEN) - 1) << CCI_CFG_MCCI_DLY_R_POS))
+
+/* 0x4 : cci_addr */
+#define CCI_ADDR_OFFSET       (0x4)
+#define CCI_APB_CCI_ADDR      CCI_APB_CCI_ADDR
+#define CCI_APB_CCI_ADDR_POS  (0U)
+#define CCI_APB_CCI_ADDR_LEN  (32U)
+#define CCI_APB_CCI_ADDR_MSK  (((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS)
+#define CCI_APB_CCI_ADDR_UMSK (~(((1U << CCI_APB_CCI_ADDR_LEN) - 1) << CCI_APB_CCI_ADDR_POS))
+
+/* 0x8 : cci_wdata */
+#define CCI_WDATA_OFFSET       (0x8)
+#define CCI_APB_CCI_WDATA      CCI_APB_CCI_WDATA
+#define CCI_APB_CCI_WDATA_POS  (0U)
+#define CCI_APB_CCI_WDATA_LEN  (32U)
+#define CCI_APB_CCI_WDATA_MSK  (((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS)
+#define CCI_APB_CCI_WDATA_UMSK (~(((1U << CCI_APB_CCI_WDATA_LEN) - 1) << CCI_APB_CCI_WDATA_POS))
+
+/* 0xC : cci_rdata */
+#define CCI_RDATA_OFFSET       (0xC)
+#define CCI_APB_CCI_RDATA      CCI_APB_CCI_RDATA
+#define CCI_APB_CCI_RDATA_POS  (0U)
+#define CCI_APB_CCI_RDATA_LEN  (32U)
+#define CCI_APB_CCI_RDATA_MSK  (((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS)
+#define CCI_APB_CCI_RDATA_UMSK (~(((1U << CCI_APB_CCI_RDATA_LEN) - 1) << CCI_APB_CCI_RDATA_POS))
+
+/* 0x10 : cci_ctl */
+#define CCI_CTL_OFFSET      (0x10)
+#define CCI_WRITE_FLAG      CCI_WRITE_FLAG
+#define CCI_WRITE_FLAG_POS  (0U)
+#define CCI_WRITE_FLAG_LEN  (1U)
+#define CCI_WRITE_FLAG_MSK  (((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS)
+#define CCI_WRITE_FLAG_UMSK (~(((1U << CCI_WRITE_FLAG_LEN) - 1) << CCI_WRITE_FLAG_POS))
+#define CCI_READ_FLAG       CCI_READ_FLAG
+#define CCI_READ_FLAG_POS   (1U)
+#define CCI_READ_FLAG_LEN   (1U)
+#define CCI_READ_FLAG_MSK   (((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS)
+#define CCI_READ_FLAG_UMSK  (~(((1U << CCI_READ_FLAG_LEN) - 1) << CCI_READ_FLAG_POS))
+#define CCI_AHB_STATE       CCI_AHB_STATE
+#define CCI_AHB_STATE_POS   (2U)
+#define CCI_AHB_STATE_LEN   (2U)
+#define CCI_AHB_STATE_MSK   (((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS)
+#define CCI_AHB_STATE_UMSK  (~(((1U << CCI_AHB_STATE_LEN) - 1) << CCI_AHB_STATE_POS))
+
+/* 0x750 : audio_pll_cfg0 */
+#define CCI_AUDIO_PLL_CFG0_OFFSET   (0x750)
+#define CCI_AUPLL_SDM_RSTB          CCI_AUPLL_SDM_RSTB
+#define CCI_AUPLL_SDM_RSTB_POS      (0U)
+#define CCI_AUPLL_SDM_RSTB_LEN      (1U)
+#define CCI_AUPLL_SDM_RSTB_MSK      (((1U << CCI_AUPLL_SDM_RSTB_LEN) - 1) << CCI_AUPLL_SDM_RSTB_POS)
+#define CCI_AUPLL_SDM_RSTB_UMSK     (~(((1U << CCI_AUPLL_SDM_RSTB_LEN) - 1) << CCI_AUPLL_SDM_RSTB_POS))
+#define CCI_AUPLL_POSTDIV_RSTB      CCI_AUPLL_POSTDIV_RSTB
+#define CCI_AUPLL_POSTDIV_RSTB_POS  (1U)
+#define CCI_AUPLL_POSTDIV_RSTB_LEN  (1U)
+#define CCI_AUPLL_POSTDIV_RSTB_MSK  (((1U << CCI_AUPLL_POSTDIV_RSTB_LEN) - 1) << CCI_AUPLL_POSTDIV_RSTB_POS)
+#define CCI_AUPLL_POSTDIV_RSTB_UMSK (~(((1U << CCI_AUPLL_POSTDIV_RSTB_LEN) - 1) << CCI_AUPLL_POSTDIV_RSTB_POS))
+#define CCI_AUPLL_FBDV_RSTB         CCI_AUPLL_FBDV_RSTB
+#define CCI_AUPLL_FBDV_RSTB_POS     (2U)
+#define CCI_AUPLL_FBDV_RSTB_LEN     (1U)
+#define CCI_AUPLL_FBDV_RSTB_MSK     (((1U << CCI_AUPLL_FBDV_RSTB_LEN) - 1) << CCI_AUPLL_FBDV_RSTB_POS)
+#define CCI_AUPLL_FBDV_RSTB_UMSK    (~(((1U << CCI_AUPLL_FBDV_RSTB_LEN) - 1) << CCI_AUPLL_FBDV_RSTB_POS))
+#define CCI_AUPLL_REFDIV_RSTB       CCI_AUPLL_REFDIV_RSTB
+#define CCI_AUPLL_REFDIV_RSTB_POS   (3U)
+#define CCI_AUPLL_REFDIV_RSTB_LEN   (1U)
+#define CCI_AUPLL_REFDIV_RSTB_MSK   (((1U << CCI_AUPLL_REFDIV_RSTB_LEN) - 1) << CCI_AUPLL_REFDIV_RSTB_POS)
+#define CCI_AUPLL_REFDIV_RSTB_UMSK  (~(((1U << CCI_AUPLL_REFDIV_RSTB_LEN) - 1) << CCI_AUPLL_REFDIV_RSTB_POS))
+#define CCI_PU_AUPLL_POSTDIV        CCI_PU_AUPLL_POSTDIV
+#define CCI_PU_AUPLL_POSTDIV_POS    (4U)
+#define CCI_PU_AUPLL_POSTDIV_LEN    (1U)
+#define CCI_PU_AUPLL_POSTDIV_MSK    (((1U << CCI_PU_AUPLL_POSTDIV_LEN) - 1) << CCI_PU_AUPLL_POSTDIV_POS)
+#define CCI_PU_AUPLL_POSTDIV_UMSK   (~(((1U << CCI_PU_AUPLL_POSTDIV_LEN) - 1) << CCI_PU_AUPLL_POSTDIV_POS))
+#define CCI_PU_AUPLL_FBDV           CCI_PU_AUPLL_FBDV
+#define CCI_PU_AUPLL_FBDV_POS       (5U)
+#define CCI_PU_AUPLL_FBDV_LEN       (1U)
+#define CCI_PU_AUPLL_FBDV_MSK       (((1U << CCI_PU_AUPLL_FBDV_LEN) - 1) << CCI_PU_AUPLL_FBDV_POS)
+#define CCI_PU_AUPLL_FBDV_UMSK      (~(((1U << CCI_PU_AUPLL_FBDV_LEN) - 1) << CCI_PU_AUPLL_FBDV_POS))
+#define CCI_PU_AUPLL_CLAMP_OP       CCI_PU_AUPLL_CLAMP_OP
+#define CCI_PU_AUPLL_CLAMP_OP_POS   (6U)
+#define CCI_PU_AUPLL_CLAMP_OP_LEN   (1U)
+#define CCI_PU_AUPLL_CLAMP_OP_MSK   (((1U << CCI_PU_AUPLL_CLAMP_OP_LEN) - 1) << CCI_PU_AUPLL_CLAMP_OP_POS)
+#define CCI_PU_AUPLL_CLAMP_OP_UMSK  (~(((1U << CCI_PU_AUPLL_CLAMP_OP_LEN) - 1) << CCI_PU_AUPLL_CLAMP_OP_POS))
+#define CCI_PU_AUPLL_PFD            CCI_PU_AUPLL_PFD
+#define CCI_PU_AUPLL_PFD_POS        (7U)
+#define CCI_PU_AUPLL_PFD_LEN        (1U)
+#define CCI_PU_AUPLL_PFD_MSK        (((1U << CCI_PU_AUPLL_PFD_LEN) - 1) << CCI_PU_AUPLL_PFD_POS)
+#define CCI_PU_AUPLL_PFD_UMSK       (~(((1U << CCI_PU_AUPLL_PFD_LEN) - 1) << CCI_PU_AUPLL_PFD_POS))
+#define CCI_PU_AUPLL_CP             CCI_PU_AUPLL_CP
+#define CCI_PU_AUPLL_CP_POS         (8U)
+#define CCI_PU_AUPLL_CP_LEN         (1U)
+#define CCI_PU_AUPLL_CP_MSK         (((1U << CCI_PU_AUPLL_CP_LEN) - 1) << CCI_PU_AUPLL_CP_POS)
+#define CCI_PU_AUPLL_CP_UMSK        (~(((1U << CCI_PU_AUPLL_CP_LEN) - 1) << CCI_PU_AUPLL_CP_POS))
+#define CCI_PU_AUPLL_SFREG          CCI_PU_AUPLL_SFREG
+#define CCI_PU_AUPLL_SFREG_POS      (9U)
+#define CCI_PU_AUPLL_SFREG_LEN      (1U)
+#define CCI_PU_AUPLL_SFREG_MSK      (((1U << CCI_PU_AUPLL_SFREG_LEN) - 1) << CCI_PU_AUPLL_SFREG_POS)
+#define CCI_PU_AUPLL_SFREG_UMSK     (~(((1U << CCI_PU_AUPLL_SFREG_LEN) - 1) << CCI_PU_AUPLL_SFREG_POS))
+#define CCI_PU_AUPLL                CCI_PU_AUPLL
+#define CCI_PU_AUPLL_POS            (10U)
+#define CCI_PU_AUPLL_LEN            (1U)
+#define CCI_PU_AUPLL_MSK            (((1U << CCI_PU_AUPLL_LEN) - 1) << CCI_PU_AUPLL_POS)
+#define CCI_PU_AUPLL_UMSK           (~(((1U << CCI_PU_AUPLL_LEN) - 1) << CCI_PU_AUPLL_POS))
+#define CCI_PU_AUPLL_CLKTREE        CCI_PU_AUPLL_CLKTREE
+#define CCI_PU_AUPLL_CLKTREE_POS    (11U)
+#define CCI_PU_AUPLL_CLKTREE_LEN    (1U)
+#define CCI_PU_AUPLL_CLKTREE_MSK    (((1U << CCI_PU_AUPLL_CLKTREE_LEN) - 1) << CCI_PU_AUPLL_CLKTREE_POS)
+#define CCI_PU_AUPLL_CLKTREE_UMSK   (~(((1U << CCI_PU_AUPLL_CLKTREE_LEN) - 1) << CCI_PU_AUPLL_CLKTREE_POS))
+
+/* 0x754 : audio_pll_cfg1 */
+#define CCI_AUDIO_PLL_CFG1_OFFSET   (0x754)
+#define CCI_AUPLL_POSTDIV           CCI_AUPLL_POSTDIV
+#define CCI_AUPLL_POSTDIV_POS       (0U)
+#define CCI_AUPLL_POSTDIV_LEN       (7U)
+#define CCI_AUPLL_POSTDIV_MSK       (((1U << CCI_AUPLL_POSTDIV_LEN) - 1) << CCI_AUPLL_POSTDIV_POS)
+#define CCI_AUPLL_POSTDIV_UMSK      (~(((1U << CCI_AUPLL_POSTDIV_LEN) - 1) << CCI_AUPLL_POSTDIV_POS))
+#define CCI_AUPLL_REFDIV_RATIO      CCI_AUPLL_REFDIV_RATIO
+#define CCI_AUPLL_REFDIV_RATIO_POS  (8U)
+#define CCI_AUPLL_REFDIV_RATIO_LEN  (4U)
+#define CCI_AUPLL_REFDIV_RATIO_MSK  (((1U << CCI_AUPLL_REFDIV_RATIO_LEN) - 1) << CCI_AUPLL_REFDIV_RATIO_POS)
+#define CCI_AUPLL_REFDIV_RATIO_UMSK (~(((1U << CCI_AUPLL_REFDIV_RATIO_LEN) - 1) << CCI_AUPLL_REFDIV_RATIO_POS))
+#define CCI_AUPLL_REFCLK_SEL        CCI_AUPLL_REFCLK_SEL
+#define CCI_AUPLL_REFCLK_SEL_POS    (16U)
+#define CCI_AUPLL_REFCLK_SEL_LEN    (2U)
+#define CCI_AUPLL_REFCLK_SEL_MSK    (((1U << CCI_AUPLL_REFCLK_SEL_LEN) - 1) << CCI_AUPLL_REFCLK_SEL_POS)
+#define CCI_AUPLL_REFCLK_SEL_UMSK   (~(((1U << CCI_AUPLL_REFCLK_SEL_LEN) - 1) << CCI_AUPLL_REFCLK_SEL_POS))
+#define CCI_AUPLL_VG11_SEL          CCI_AUPLL_VG11_SEL
+#define CCI_AUPLL_VG11_SEL_POS      (20U)
+#define CCI_AUPLL_VG11_SEL_LEN      (2U)
+#define CCI_AUPLL_VG11_SEL_MSK      (((1U << CCI_AUPLL_VG11_SEL_LEN) - 1) << CCI_AUPLL_VG11_SEL_POS)
+#define CCI_AUPLL_VG11_SEL_UMSK     (~(((1U << CCI_AUPLL_VG11_SEL_LEN) - 1) << CCI_AUPLL_VG11_SEL_POS))
+#define CCI_AUPLL_VG13_SEL          CCI_AUPLL_VG13_SEL
+#define CCI_AUPLL_VG13_SEL_POS      (24U)
+#define CCI_AUPLL_VG13_SEL_LEN      (2U)
+#define CCI_AUPLL_VG13_SEL_MSK      (((1U << CCI_AUPLL_VG13_SEL_LEN) - 1) << CCI_AUPLL_VG13_SEL_POS)
+#define CCI_AUPLL_VG13_SEL_UMSK     (~(((1U << CCI_AUPLL_VG13_SEL_LEN) - 1) << CCI_AUPLL_VG13_SEL_POS))
+
+/* 0x758 : audio_pll_cfg2 */
+#define CCI_AUDIO_PLL_CFG2_OFFSET    (0x758)
+#define CCI_AUPLL_SEL_CP_BIAS        CCI_AUPLL_SEL_CP_BIAS
+#define CCI_AUPLL_SEL_CP_BIAS_POS    (0U)
+#define CCI_AUPLL_SEL_CP_BIAS_LEN    (1U)
+#define CCI_AUPLL_SEL_CP_BIAS_MSK    (((1U << CCI_AUPLL_SEL_CP_BIAS_LEN) - 1) << CCI_AUPLL_SEL_CP_BIAS_POS)
+#define CCI_AUPLL_SEL_CP_BIAS_UMSK   (~(((1U << CCI_AUPLL_SEL_CP_BIAS_LEN) - 1) << CCI_AUPLL_SEL_CP_BIAS_POS))
+#define CCI_AUPLL_ICP_5U             CCI_AUPLL_ICP_5U
+#define CCI_AUPLL_ICP_5U_POS         (4U)
+#define CCI_AUPLL_ICP_5U_LEN         (2U)
+#define CCI_AUPLL_ICP_5U_MSK         (((1U << CCI_AUPLL_ICP_5U_LEN) - 1) << CCI_AUPLL_ICP_5U_POS)
+#define CCI_AUPLL_ICP_5U_UMSK        (~(((1U << CCI_AUPLL_ICP_5U_LEN) - 1) << CCI_AUPLL_ICP_5U_POS))
+#define CCI_AUPLL_ICP_1U             CCI_AUPLL_ICP_1U
+#define CCI_AUPLL_ICP_1U_POS         (6U)
+#define CCI_AUPLL_ICP_1U_LEN         (2U)
+#define CCI_AUPLL_ICP_1U_MSK         (((1U << CCI_AUPLL_ICP_1U_LEN) - 1) << CCI_AUPLL_ICP_1U_POS)
+#define CCI_AUPLL_ICP_1U_UMSK        (~(((1U << CCI_AUPLL_ICP_1U_LEN) - 1) << CCI_AUPLL_ICP_1U_POS))
+#define CCI_AUPLL_INT_FRAC_SW        CCI_AUPLL_INT_FRAC_SW
+#define CCI_AUPLL_INT_FRAC_SW_POS    (8U)
+#define CCI_AUPLL_INT_FRAC_SW_LEN    (1U)
+#define CCI_AUPLL_INT_FRAC_SW_MSK    (((1U << CCI_AUPLL_INT_FRAC_SW_LEN) - 1) << CCI_AUPLL_INT_FRAC_SW_POS)
+#define CCI_AUPLL_INT_FRAC_SW_UMSK   (~(((1U << CCI_AUPLL_INT_FRAC_SW_LEN) - 1) << CCI_AUPLL_INT_FRAC_SW_POS))
+#define CCI_AUPLL_CP_STARTUP_EN      CCI_AUPLL_CP_STARTUP_EN
+#define CCI_AUPLL_CP_STARTUP_EN_POS  (9U)
+#define CCI_AUPLL_CP_STARTUP_EN_LEN  (1U)
+#define CCI_AUPLL_CP_STARTUP_EN_MSK  (((1U << CCI_AUPLL_CP_STARTUP_EN_LEN) - 1) << CCI_AUPLL_CP_STARTUP_EN_POS)
+#define CCI_AUPLL_CP_STARTUP_EN_UMSK (~(((1U << CCI_AUPLL_CP_STARTUP_EN_LEN) - 1) << CCI_AUPLL_CP_STARTUP_EN_POS))
+#define CCI_AUPLL_CP_OPAMP_EN        CCI_AUPLL_CP_OPAMP_EN
+#define CCI_AUPLL_CP_OPAMP_EN_POS    (10U)
+#define CCI_AUPLL_CP_OPAMP_EN_LEN    (1U)
+#define CCI_AUPLL_CP_OPAMP_EN_MSK    (((1U << CCI_AUPLL_CP_OPAMP_EN_LEN) - 1) << CCI_AUPLL_CP_OPAMP_EN_POS)
+#define CCI_AUPLL_CP_OPAMP_EN_UMSK   (~(((1U << CCI_AUPLL_CP_OPAMP_EN_LEN) - 1) << CCI_AUPLL_CP_OPAMP_EN_POS))
+
+/* 0x75C : audio_pll_cfg3 */
+#define CCI_AUDIO_PLL_CFG3_OFFSET (0x75C)
+#define CCI_AUPLL_C4_EN           CCI_AUPLL_C4_EN
+#define CCI_AUPLL_C4_EN_POS       (0U)
+#define CCI_AUPLL_C4_EN_LEN       (1U)
+#define CCI_AUPLL_C4_EN_MSK       (((1U << CCI_AUPLL_C4_EN_LEN) - 1) << CCI_AUPLL_C4_EN_POS)
+#define CCI_AUPLL_C4_EN_UMSK      (~(((1U << CCI_AUPLL_C4_EN_LEN) - 1) << CCI_AUPLL_C4_EN_POS))
+#define CCI_AUPLL_R4              CCI_AUPLL_R4
+#define CCI_AUPLL_R4_POS          (4U)
+#define CCI_AUPLL_R4_LEN          (2U)
+#define CCI_AUPLL_R4_MSK          (((1U << CCI_AUPLL_R4_LEN) - 1) << CCI_AUPLL_R4_POS)
+#define CCI_AUPLL_R4_UMSK         (~(((1U << CCI_AUPLL_R4_LEN) - 1) << CCI_AUPLL_R4_POS))
+#define CCI_AUPLL_R4_SHORT        CCI_AUPLL_R4_SHORT
+#define CCI_AUPLL_R4_SHORT_POS    (8U)
+#define CCI_AUPLL_R4_SHORT_LEN    (1U)
+#define CCI_AUPLL_R4_SHORT_MSK    (((1U << CCI_AUPLL_R4_SHORT_LEN) - 1) << CCI_AUPLL_R4_SHORT_POS)
+#define CCI_AUPLL_R4_SHORT_UMSK   (~(((1U << CCI_AUPLL_R4_SHORT_LEN) - 1) << CCI_AUPLL_R4_SHORT_POS))
+#define CCI_AUPLL_C3              CCI_AUPLL_C3
+#define CCI_AUPLL_C3_POS          (12U)
+#define CCI_AUPLL_C3_LEN          (2U)
+#define CCI_AUPLL_C3_MSK          (((1U << CCI_AUPLL_C3_LEN) - 1) << CCI_AUPLL_C3_POS)
+#define CCI_AUPLL_C3_UMSK         (~(((1U << CCI_AUPLL_C3_LEN) - 1) << CCI_AUPLL_C3_POS))
+#define CCI_AUPLL_CZ              CCI_AUPLL_CZ
+#define CCI_AUPLL_CZ_POS          (14U)
+#define CCI_AUPLL_CZ_LEN          (2U)
+#define CCI_AUPLL_CZ_MSK          (((1U << CCI_AUPLL_CZ_LEN) - 1) << CCI_AUPLL_CZ_POS)
+#define CCI_AUPLL_CZ_UMSK         (~(((1U << CCI_AUPLL_CZ_LEN) - 1) << CCI_AUPLL_CZ_POS))
+#define CCI_AUPLL_RZ              CCI_AUPLL_RZ
+#define CCI_AUPLL_RZ_POS          (16U)
+#define CCI_AUPLL_RZ_LEN          (3U)
+#define CCI_AUPLL_RZ_MSK          (((1U << CCI_AUPLL_RZ_LEN) - 1) << CCI_AUPLL_RZ_POS)
+#define CCI_AUPLL_RZ_UMSK         (~(((1U << CCI_AUPLL_RZ_LEN) - 1) << CCI_AUPLL_RZ_POS))
+
+/* 0x760 : audio_pll_cfg4 */
+#define CCI_AUDIO_PLL_CFG4_OFFSET     (0x760)
+#define CCI_AUPLL_SEL_SAMPLE_CLK      CCI_AUPLL_SEL_SAMPLE_CLK
+#define CCI_AUPLL_SEL_SAMPLE_CLK_POS  (0U)
+#define CCI_AUPLL_SEL_SAMPLE_CLK_LEN  (2U)
+#define CCI_AUPLL_SEL_SAMPLE_CLK_MSK  (((1U << CCI_AUPLL_SEL_SAMPLE_CLK_LEN) - 1) << CCI_AUPLL_SEL_SAMPLE_CLK_POS)
+#define CCI_AUPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << CCI_AUPLL_SEL_SAMPLE_CLK_LEN) - 1) << CCI_AUPLL_SEL_SAMPLE_CLK_POS))
+#define CCI_AUPLL_SEL_FB_CLK          CCI_AUPLL_SEL_FB_CLK
+#define CCI_AUPLL_SEL_FB_CLK_POS      (4U)
+#define CCI_AUPLL_SEL_FB_CLK_LEN      (2U)
+#define CCI_AUPLL_SEL_FB_CLK_MSK      (((1U << CCI_AUPLL_SEL_FB_CLK_LEN) - 1) << CCI_AUPLL_SEL_FB_CLK_POS)
+#define CCI_AUPLL_SEL_FB_CLK_UMSK     (~(((1U << CCI_AUPLL_SEL_FB_CLK_LEN) - 1) << CCI_AUPLL_SEL_FB_CLK_POS))
+#define CCI_AUPLL_SDMCLK_SEL          CCI_AUPLL_SDMCLK_SEL
+#define CCI_AUPLL_SDMCLK_SEL_POS      (8U)
+#define CCI_AUPLL_SDMCLK_SEL_LEN      (1U)
+#define CCI_AUPLL_SDMCLK_SEL_MSK      (((1U << CCI_AUPLL_SDMCLK_SEL_LEN) - 1) << CCI_AUPLL_SDMCLK_SEL_POS)
+#define CCI_AUPLL_SDMCLK_SEL_UMSK     (~(((1U << CCI_AUPLL_SDMCLK_SEL_LEN) - 1) << CCI_AUPLL_SDMCLK_SEL_POS))
+
+/* 0x764 : audio_pll_cfg5 */
+#define CCI_AUDIO_PLL_CFG5_OFFSET (0x764)
+#define CCI_AUPLL_VCO_SPEED       CCI_AUPLL_VCO_SPEED
+#define CCI_AUPLL_VCO_SPEED_POS   (0U)
+#define CCI_AUPLL_VCO_SPEED_LEN   (3U)
+#define CCI_AUPLL_VCO_SPEED_MSK   (((1U << CCI_AUPLL_VCO_SPEED_LEN) - 1) << CCI_AUPLL_VCO_SPEED_POS)
+#define CCI_AUPLL_VCO_SPEED_UMSK  (~(((1U << CCI_AUPLL_VCO_SPEED_LEN) - 1) << CCI_AUPLL_VCO_SPEED_POS))
+
+/* 0x768 : audio_pll_cfg6 */
+#define CCI_AUDIO_PLL_CFG6_OFFSET (0x768)
+#define CCI_AUPLL_SDMIN           CCI_AUPLL_SDMIN
+#define CCI_AUPLL_SDMIN_POS       (0U)
+#define CCI_AUPLL_SDMIN_LEN       (19U)
+#define CCI_AUPLL_SDMIN_MSK       (((1U << CCI_AUPLL_SDMIN_LEN) - 1) << CCI_AUPLL_SDMIN_POS)
+#define CCI_AUPLL_SDMIN_UMSK      (~(((1U << CCI_AUPLL_SDMIN_LEN) - 1) << CCI_AUPLL_SDMIN_POS))
+#define CCI_AUPLL_SDM_BYPASS      CCI_AUPLL_SDM_BYPASS
+#define CCI_AUPLL_SDM_BYPASS_POS  (24U)
+#define CCI_AUPLL_SDM_BYPASS_LEN  (1U)
+#define CCI_AUPLL_SDM_BYPASS_MSK  (((1U << CCI_AUPLL_SDM_BYPASS_LEN) - 1) << CCI_AUPLL_SDM_BYPASS_POS)
+#define CCI_AUPLL_SDM_BYPASS_UMSK (~(((1U << CCI_AUPLL_SDM_BYPASS_LEN) - 1) << CCI_AUPLL_SDM_BYPASS_POS))
+
+/* 0x76C : audio_pll_cfg7 */
+#define CCI_AUDIO_PLL_CFG7_OFFSET       (0x76C)
+#define CCI_AUPLL_SDM_ORDER_SEL         CCI_AUPLL_SDM_ORDER_SEL
+#define CCI_AUPLL_SDM_ORDER_SEL_POS     (0U)
+#define CCI_AUPLL_SDM_ORDER_SEL_LEN     (1U)
+#define CCI_AUPLL_SDM_ORDER_SEL_MSK     (((1U << CCI_AUPLL_SDM_ORDER_SEL_LEN) - 1) << CCI_AUPLL_SDM_ORDER_SEL_POS)
+#define CCI_AUPLL_SDM_ORDER_SEL_UMSK    (~(((1U << CCI_AUPLL_SDM_ORDER_SEL_LEN) - 1) << CCI_AUPLL_SDM_ORDER_SEL_POS))
+#define CCI_AUPLL_SDM_SIG_DITH_SEL      CCI_AUPLL_SDM_SIG_DITH_SEL
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_POS  (16U)
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_LEN  (2U)
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_MSK  (((1U << CCI_AUPLL_SDM_SIG_DITH_SEL_LEN) - 1) << CCI_AUPLL_SDM_SIG_DITH_SEL_POS)
+#define CCI_AUPLL_SDM_SIG_DITH_SEL_UMSK (~(((1U << CCI_AUPLL_SDM_SIG_DITH_SEL_LEN) - 1) << CCI_AUPLL_SDM_SIG_DITH_SEL_POS))
+
+/* 0x770 : audio_pll_cfg8 */
+#define CCI_AUDIO_PLL_CFG8_OFFSET    (0x770)
+#define CCI_AUPLL_EN_DIV1            CCI_AUPLL_EN_DIV1
+#define CCI_AUPLL_EN_DIV1_POS        (0U)
+#define CCI_AUPLL_EN_DIV1_LEN        (1U)
+#define CCI_AUPLL_EN_DIV1_MSK        (((1U << CCI_AUPLL_EN_DIV1_LEN) - 1) << CCI_AUPLL_EN_DIV1_POS)
+#define CCI_AUPLL_EN_DIV1_UMSK       (~(((1U << CCI_AUPLL_EN_DIV1_LEN) - 1) << CCI_AUPLL_EN_DIV1_POS))
+#define CCI_AUPLL_EN_DIV2            CCI_AUPLL_EN_DIV2
+#define CCI_AUPLL_EN_DIV2_POS        (1U)
+#define CCI_AUPLL_EN_DIV2_LEN        (1U)
+#define CCI_AUPLL_EN_DIV2_MSK        (((1U << CCI_AUPLL_EN_DIV2_LEN) - 1) << CCI_AUPLL_EN_DIV2_POS)
+#define CCI_AUPLL_EN_DIV2_UMSK       (~(((1U << CCI_AUPLL_EN_DIV2_LEN) - 1) << CCI_AUPLL_EN_DIV2_POS))
+#define CCI_AUPLL_EN_DIV2P5          CCI_AUPLL_EN_DIV2P5
+#define CCI_AUPLL_EN_DIV2P5_POS      (2U)
+#define CCI_AUPLL_EN_DIV2P5_LEN      (1U)
+#define CCI_AUPLL_EN_DIV2P5_MSK      (((1U << CCI_AUPLL_EN_DIV2P5_LEN) - 1) << CCI_AUPLL_EN_DIV2P5_POS)
+#define CCI_AUPLL_EN_DIV2P5_UMSK     (~(((1U << CCI_AUPLL_EN_DIV2P5_LEN) - 1) << CCI_AUPLL_EN_DIV2P5_POS))
+#define CCI_AUPLL_EN_DIV3            CCI_AUPLL_EN_DIV3
+#define CCI_AUPLL_EN_DIV3_POS        (3U)
+#define CCI_AUPLL_EN_DIV3_LEN        (1U)
+#define CCI_AUPLL_EN_DIV3_MSK        (((1U << CCI_AUPLL_EN_DIV3_LEN) - 1) << CCI_AUPLL_EN_DIV3_POS)
+#define CCI_AUPLL_EN_DIV3_UMSK       (~(((1U << CCI_AUPLL_EN_DIV3_LEN) - 1) << CCI_AUPLL_EN_DIV3_POS))
+#define CCI_AUPLL_EN_DIV4            CCI_AUPLL_EN_DIV4
+#define CCI_AUPLL_EN_DIV4_POS        (4U)
+#define CCI_AUPLL_EN_DIV4_LEN        (1U)
+#define CCI_AUPLL_EN_DIV4_MSK        (((1U << CCI_AUPLL_EN_DIV4_LEN) - 1) << CCI_AUPLL_EN_DIV4_POS)
+#define CCI_AUPLL_EN_DIV4_UMSK       (~(((1U << CCI_AUPLL_EN_DIV4_LEN) - 1) << CCI_AUPLL_EN_DIV4_POS))
+#define CCI_AUPLL_EN_DIV5            CCI_AUPLL_EN_DIV5
+#define CCI_AUPLL_EN_DIV5_POS        (5U)
+#define CCI_AUPLL_EN_DIV5_LEN        (1U)
+#define CCI_AUPLL_EN_DIV5_MSK        (((1U << CCI_AUPLL_EN_DIV5_LEN) - 1) << CCI_AUPLL_EN_DIV5_POS)
+#define CCI_AUPLL_EN_DIV5_UMSK       (~(((1U << CCI_AUPLL_EN_DIV5_LEN) - 1) << CCI_AUPLL_EN_DIV5_POS))
+#define CCI_AUPLL_EN_DIV6            CCI_AUPLL_EN_DIV6
+#define CCI_AUPLL_EN_DIV6_POS        (6U)
+#define CCI_AUPLL_EN_DIV6_LEN        (1U)
+#define CCI_AUPLL_EN_DIV6_MSK        (((1U << CCI_AUPLL_EN_DIV6_LEN) - 1) << CCI_AUPLL_EN_DIV6_POS)
+#define CCI_AUPLL_EN_DIV6_UMSK       (~(((1U << CCI_AUPLL_EN_DIV6_LEN) - 1) << CCI_AUPLL_EN_DIV6_POS))
+#define CCI_AUPLL_EN_DIV10           CCI_AUPLL_EN_DIV10
+#define CCI_AUPLL_EN_DIV10_POS       (7U)
+#define CCI_AUPLL_EN_DIV10_LEN       (1U)
+#define CCI_AUPLL_EN_DIV10_MSK       (((1U << CCI_AUPLL_EN_DIV10_LEN) - 1) << CCI_AUPLL_EN_DIV10_POS)
+#define CCI_AUPLL_EN_DIV10_UMSK      (~(((1U << CCI_AUPLL_EN_DIV10_LEN) - 1) << CCI_AUPLL_EN_DIV10_POS))
+#define CCI_AUPLL_EN_DIV15           CCI_AUPLL_EN_DIV15
+#define CCI_AUPLL_EN_DIV15_POS       (8U)
+#define CCI_AUPLL_EN_DIV15_LEN       (1U)
+#define CCI_AUPLL_EN_DIV15_MSK       (((1U << CCI_AUPLL_EN_DIV15_LEN) - 1) << CCI_AUPLL_EN_DIV15_POS)
+#define CCI_AUPLL_EN_DIV15_UMSK      (~(((1U << CCI_AUPLL_EN_DIV15_LEN) - 1) << CCI_AUPLL_EN_DIV15_POS))
+#define CCI_AUPLL_SEL_DIV1_DIV2      CCI_AUPLL_SEL_DIV1_DIV2
+#define CCI_AUPLL_SEL_DIV1_DIV2_POS  (9U)
+#define CCI_AUPLL_SEL_DIV1_DIV2_LEN  (1U)
+#define CCI_AUPLL_SEL_DIV1_DIV2_MSK  (((1U << CCI_AUPLL_SEL_DIV1_DIV2_LEN) - 1) << CCI_AUPLL_SEL_DIV1_DIV2_POS)
+#define CCI_AUPLL_SEL_DIV1_DIV2_UMSK (~(((1U << CCI_AUPLL_SEL_DIV1_DIV2_LEN) - 1) << CCI_AUPLL_SEL_DIV1_DIV2_POS))
+
+/* 0x774 : audio_pll_cfg9 */
+#define CCI_AUDIO_PLL_CFG9_OFFSET       (0x774)
+#define CCI_AUPLL_DC_TP_OUT_EN          CCI_AUPLL_DC_TP_OUT_EN
+#define CCI_AUPLL_DC_TP_OUT_EN_POS      (0U)
+#define CCI_AUPLL_DC_TP_OUT_EN_LEN      (1U)
+#define CCI_AUPLL_DC_TP_OUT_EN_MSK      (((1U << CCI_AUPLL_DC_TP_OUT_EN_LEN) - 1) << CCI_AUPLL_DC_TP_OUT_EN_POS)
+#define CCI_AUPLL_DC_TP_OUT_EN_UMSK     (~(((1U << CCI_AUPLL_DC_TP_OUT_EN_LEN) - 1) << CCI_AUPLL_DC_TP_OUT_EN_POS))
+#define CCI_TEN_AUPLL                   CCI_TEN_AUPLL
+#define CCI_TEN_AUPLL_POS               (1U)
+#define CCI_TEN_AUPLL_LEN               (1U)
+#define CCI_TEN_AUPLL_MSK               (((1U << CCI_TEN_AUPLL_LEN) - 1) << CCI_TEN_AUPLL_POS)
+#define CCI_TEN_AUPLL_UMSK              (~(((1U << CCI_TEN_AUPLL_LEN) - 1) << CCI_TEN_AUPLL_POS))
+#define CCI_TEN_AUPLL_SFREG             CCI_TEN_AUPLL_SFREG
+#define CCI_TEN_AUPLL_SFREG_POS         (2U)
+#define CCI_TEN_AUPLL_SFREG_LEN         (1U)
+#define CCI_TEN_AUPLL_SFREG_MSK         (((1U << CCI_TEN_AUPLL_SFREG_LEN) - 1) << CCI_TEN_AUPLL_SFREG_POS)
+#define CCI_TEN_AUPLL_SFREG_UMSK        (~(((1U << CCI_TEN_AUPLL_SFREG_LEN) - 1) << CCI_TEN_AUPLL_SFREG_POS))
+#define CCI_DTEN_AUPLL_FIN              CCI_DTEN_AUPLL_FIN
+#define CCI_DTEN_AUPLL_FIN_POS          (4U)
+#define CCI_DTEN_AUPLL_FIN_LEN          (1U)
+#define CCI_DTEN_AUPLL_FIN_MSK          (((1U << CCI_DTEN_AUPLL_FIN_LEN) - 1) << CCI_DTEN_AUPLL_FIN_POS)
+#define CCI_DTEN_AUPLL_FIN_UMSK         (~(((1U << CCI_DTEN_AUPLL_FIN_LEN) - 1) << CCI_DTEN_AUPLL_FIN_POS))
+#define CCI_DTEN_AUPLL_FREF             CCI_DTEN_AUPLL_FREF
+#define CCI_DTEN_AUPLL_FREF_POS         (5U)
+#define CCI_DTEN_AUPLL_FREF_LEN         (1U)
+#define CCI_DTEN_AUPLL_FREF_MSK         (((1U << CCI_DTEN_AUPLL_FREF_LEN) - 1) << CCI_DTEN_AUPLL_FREF_POS)
+#define CCI_DTEN_AUPLL_FREF_UMSK        (~(((1U << CCI_DTEN_AUPLL_FREF_LEN) - 1) << CCI_DTEN_AUPLL_FREF_POS))
+#define CCI_DTEN_AUPLL_FSDM             CCI_DTEN_AUPLL_FSDM
+#define CCI_DTEN_AUPLL_FSDM_POS         (6U)
+#define CCI_DTEN_AUPLL_FSDM_LEN         (1U)
+#define CCI_DTEN_AUPLL_FSDM_MSK         (((1U << CCI_DTEN_AUPLL_FSDM_LEN) - 1) << CCI_DTEN_AUPLL_FSDM_POS)
+#define CCI_DTEN_AUPLL_FSDM_UMSK        (~(((1U << CCI_DTEN_AUPLL_FSDM_LEN) - 1) << CCI_DTEN_AUPLL_FSDM_POS))
+#define CCI_DTEN_AUPLL_DIV15            CCI_DTEN_AUPLL_DIV15
+#define CCI_DTEN_AUPLL_DIV15_POS        (7U)
+#define CCI_DTEN_AUPLL_DIV15_LEN        (1U)
+#define CCI_DTEN_AUPLL_DIV15_MSK        (((1U << CCI_DTEN_AUPLL_DIV15_LEN) - 1) << CCI_DTEN_AUPLL_DIV15_POS)
+#define CCI_DTEN_AUPLL_DIV15_UMSK       (~(((1U << CCI_DTEN_AUPLL_DIV15_LEN) - 1) << CCI_DTEN_AUPLL_DIV15_POS))
+#define CCI_DTEN_AUPLL_DIV5             CCI_DTEN_AUPLL_DIV5
+#define CCI_DTEN_AUPLL_DIV5_POS         (8U)
+#define CCI_DTEN_AUPLL_DIV5_LEN         (1U)
+#define CCI_DTEN_AUPLL_DIV5_MSK         (((1U << CCI_DTEN_AUPLL_DIV5_LEN) - 1) << CCI_DTEN_AUPLL_DIV5_POS)
+#define CCI_DTEN_AUPLL_DIV5_UMSK        (~(((1U << CCI_DTEN_AUPLL_DIV5_LEN) - 1) << CCI_DTEN_AUPLL_DIV5_POS))
+#define CCI_DTEN_AUPLL_POSTDIV_CLK      CCI_DTEN_AUPLL_POSTDIV_CLK
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_POS  (9U)
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_LEN  (1U)
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_MSK  (((1U << CCI_DTEN_AUPLL_POSTDIV_CLK_LEN) - 1) << CCI_DTEN_AUPLL_POSTDIV_CLK_POS)
+#define CCI_DTEN_AUPLL_POSTDIV_CLK_UMSK (~(((1U << CCI_DTEN_AUPLL_POSTDIV_CLK_LEN) - 1) << CCI_DTEN_AUPLL_POSTDIV_CLK_POS))
+#define CCI_DTEST_AUPLL_PULLDOWN        CCI_DTEST_AUPLL_PULLDOWN
+#define CCI_DTEST_AUPLL_PULLDOWN_POS    (10U)
+#define CCI_DTEST_AUPLL_PULLDOWN_LEN    (1U)
+#define CCI_DTEST_AUPLL_PULLDOWN_MSK    (((1U << CCI_DTEST_AUPLL_PULLDOWN_LEN) - 1) << CCI_DTEST_AUPLL_PULLDOWN_POS)
+#define CCI_DTEST_AUPLL_PULLDOWN_UMSK   (~(((1U << CCI_DTEST_AUPLL_PULLDOWN_LEN) - 1) << CCI_DTEST_AUPLL_PULLDOWN_POS))
+
+/* 0x778 : audio_pll_cfg10 */
+#define CCI_AUDIO_PLL_CFG10_OFFSET       (0x778)
+#define CCI_AUPLL_SSC_EN                 CCI_AUPLL_SSC_EN
+#define CCI_AUPLL_SSC_EN_POS             (0U)
+#define CCI_AUPLL_SSC_EN_LEN             (1U)
+#define CCI_AUPLL_SSC_EN_MSK             (((1U << CCI_AUPLL_SSC_EN_LEN) - 1) << CCI_AUPLL_SSC_EN_POS)
+#define CCI_AUPLL_SSC_EN_UMSK            (~(((1U << CCI_AUPLL_SSC_EN_LEN) - 1) << CCI_AUPLL_SSC_EN_POS))
+#define CCI_AUPLL_SSC_CNT                CCI_AUPLL_SSC_CNT
+#define CCI_AUPLL_SSC_CNT_POS            (4U)
+#define CCI_AUPLL_SSC_CNT_LEN            (8U)
+#define CCI_AUPLL_SSC_CNT_MSK            (((1U << CCI_AUPLL_SSC_CNT_LEN) - 1) << CCI_AUPLL_SSC_CNT_POS)
+#define CCI_AUPLL_SSC_CNT_UMSK           (~(((1U << CCI_AUPLL_SSC_CNT_LEN) - 1) << CCI_AUPLL_SSC_CNT_POS))
+#define CCI_AUPLL_SSC_GAIN               CCI_AUPLL_SSC_GAIN
+#define CCI_AUPLL_SSC_GAIN_POS           (12U)
+#define CCI_AUPLL_SSC_GAIN_LEN           (3U)
+#define CCI_AUPLL_SSC_GAIN_MSK           (((1U << CCI_AUPLL_SSC_GAIN_LEN) - 1) << CCI_AUPLL_SSC_GAIN_POS)
+#define CCI_AUPLL_SSC_GAIN_UMSK          (~(((1U << CCI_AUPLL_SSC_GAIN_LEN) - 1) << CCI_AUPLL_SSC_GAIN_POS))
+#define CCI_AUPLL_SSC_START_GATE_EN      CCI_AUPLL_SSC_START_GATE_EN
+#define CCI_AUPLL_SSC_START_GATE_EN_POS  (16U)
+#define CCI_AUPLL_SSC_START_GATE_EN_LEN  (1U)
+#define CCI_AUPLL_SSC_START_GATE_EN_MSK  (((1U << CCI_AUPLL_SSC_START_GATE_EN_LEN) - 1) << CCI_AUPLL_SSC_START_GATE_EN_POS)
+#define CCI_AUPLL_SSC_START_GATE_EN_UMSK (~(((1U << CCI_AUPLL_SSC_START_GATE_EN_LEN) - 1) << CCI_AUPLL_SSC_START_GATE_EN_POS))
+#define CCI_AUPLL_SSC_START              CCI_AUPLL_SSC_START
+#define CCI_AUPLL_SSC_START_POS          (20U)
+#define CCI_AUPLL_SSC_START_LEN          (1U)
+#define CCI_AUPLL_SSC_START_MSK          (((1U << CCI_AUPLL_SSC_START_LEN) - 1) << CCI_AUPLL_SSC_START_POS)
+#define CCI_AUPLL_SSC_START_UMSK         (~(((1U << CCI_AUPLL_SSC_START_LEN) - 1) << CCI_AUPLL_SSC_START_POS))
+
+/* 0x77C : audio_pll_cfg11 */
+#define CCI_AUDIO_PLL_CFG11_OFFSET (0x77C)
+#define CCI_AUPLL_RESV             CCI_AUPLL_RESV
+#define CCI_AUPLL_RESV_POS         (0U)
+#define CCI_AUPLL_RESV_LEN         (16U)
+#define CCI_AUPLL_RESV_MSK         (((1U << CCI_AUPLL_RESV_LEN) - 1) << CCI_AUPLL_RESV_POS)
+#define CCI_AUPLL_RESV_UMSK        (~(((1U << CCI_AUPLL_RESV_LEN) - 1) << CCI_AUPLL_RESV_POS))
+#define CCI_AUPLL_DL_CTRL_15       CCI_AUPLL_DL_CTRL_15
+#define CCI_AUPLL_DL_CTRL_15_POS   (23U)
+#define CCI_AUPLL_DL_CTRL_15_LEN   (1U)
+#define CCI_AUPLL_DL_CTRL_15_MSK   (((1U << CCI_AUPLL_DL_CTRL_15_LEN) - 1) << CCI_AUPLL_DL_CTRL_15_POS)
+#define CCI_AUPLL_DL_CTRL_15_UMSK  (~(((1U << CCI_AUPLL_DL_CTRL_15_LEN) - 1) << CCI_AUPLL_DL_CTRL_15_POS))
+#define CCI_AUPLL_DL_CTRL_10       CCI_AUPLL_DL_CTRL_10
+#define CCI_AUPLL_DL_CTRL_10_POS   (24U)
+#define CCI_AUPLL_DL_CTRL_10_LEN   (1U)
+#define CCI_AUPLL_DL_CTRL_10_MSK   (((1U << CCI_AUPLL_DL_CTRL_10_LEN) - 1) << CCI_AUPLL_DL_CTRL_10_POS)
+#define CCI_AUPLL_DL_CTRL_10_UMSK  (~(((1U << CCI_AUPLL_DL_CTRL_10_LEN) - 1) << CCI_AUPLL_DL_CTRL_10_POS))
+#define CCI_AUPLL_DL_CTRL_6        CCI_AUPLL_DL_CTRL_6
+#define CCI_AUPLL_DL_CTRL_6_POS    (25U)
+#define CCI_AUPLL_DL_CTRL_6_LEN    (1U)
+#define CCI_AUPLL_DL_CTRL_6_MSK    (((1U << CCI_AUPLL_DL_CTRL_6_LEN) - 1) << CCI_AUPLL_DL_CTRL_6_POS)
+#define CCI_AUPLL_DL_CTRL_6_UMSK   (~(((1U << CCI_AUPLL_DL_CTRL_6_LEN) - 1) << CCI_AUPLL_DL_CTRL_6_POS))
+#define CCI_AUPLL_DL_CTRL_5        CCI_AUPLL_DL_CTRL_5
+#define CCI_AUPLL_DL_CTRL_5_POS    (26U)
+#define CCI_AUPLL_DL_CTRL_5_LEN    (1U)
+#define CCI_AUPLL_DL_CTRL_5_MSK    (((1U << CCI_AUPLL_DL_CTRL_5_LEN) - 1) << CCI_AUPLL_DL_CTRL_5_POS)
+#define CCI_AUPLL_DL_CTRL_5_UMSK   (~(((1U << CCI_AUPLL_DL_CTRL_5_LEN) - 1) << CCI_AUPLL_DL_CTRL_5_POS))
+#define CCI_AUPLL_DL_CTRL_4        CCI_AUPLL_DL_CTRL_4
+#define CCI_AUPLL_DL_CTRL_4_POS    (27U)
+#define CCI_AUPLL_DL_CTRL_4_LEN    (1U)
+#define CCI_AUPLL_DL_CTRL_4_MSK    (((1U << CCI_AUPLL_DL_CTRL_4_LEN) - 1) << CCI_AUPLL_DL_CTRL_4_POS)
+#define CCI_AUPLL_DL_CTRL_4_UMSK   (~(((1U << CCI_AUPLL_DL_CTRL_4_LEN) - 1) << CCI_AUPLL_DL_CTRL_4_POS))
+#define CCI_AUPLL_DL_CTRL_3        CCI_AUPLL_DL_CTRL_3
+#define CCI_AUPLL_DL_CTRL_3_POS    (28U)
+#define CCI_AUPLL_DL_CTRL_3_LEN    (1U)
+#define CCI_AUPLL_DL_CTRL_3_MSK    (((1U << CCI_AUPLL_DL_CTRL_3_LEN) - 1) << CCI_AUPLL_DL_CTRL_3_POS)
+#define CCI_AUPLL_DL_CTRL_3_UMSK   (~(((1U << CCI_AUPLL_DL_CTRL_3_LEN) - 1) << CCI_AUPLL_DL_CTRL_3_POS))
+#define CCI_AUPLL_DL_CTRL_2P5      CCI_AUPLL_DL_CTRL_2P5
+#define CCI_AUPLL_DL_CTRL_2P5_POS  (29U)
+#define CCI_AUPLL_DL_CTRL_2P5_LEN  (1U)
+#define CCI_AUPLL_DL_CTRL_2P5_MSK  (((1U << CCI_AUPLL_DL_CTRL_2P5_LEN) - 1) << CCI_AUPLL_DL_CTRL_2P5_POS)
+#define CCI_AUPLL_DL_CTRL_2P5_UMSK (~(((1U << CCI_AUPLL_DL_CTRL_2P5_LEN) - 1) << CCI_AUPLL_DL_CTRL_2P5_POS))
+#define CCI_AUPLL_DL_CTRL_2        CCI_AUPLL_DL_CTRL_2
+#define CCI_AUPLL_DL_CTRL_2_POS    (30U)
+#define CCI_AUPLL_DL_CTRL_2_LEN    (1U)
+#define CCI_AUPLL_DL_CTRL_2_MSK    (((1U << CCI_AUPLL_DL_CTRL_2_LEN) - 1) << CCI_AUPLL_DL_CTRL_2_POS)
+#define CCI_AUPLL_DL_CTRL_2_UMSK   (~(((1U << CCI_AUPLL_DL_CTRL_2_LEN) - 1) << CCI_AUPLL_DL_CTRL_2_POS))
+#define CCI_AUPLL_DL_CTRL_1        CCI_AUPLL_DL_CTRL_1
+#define CCI_AUPLL_DL_CTRL_1_POS    (31U)
+#define CCI_AUPLL_DL_CTRL_1_LEN    (1U)
+#define CCI_AUPLL_DL_CTRL_1_MSK    (((1U << CCI_AUPLL_DL_CTRL_1_LEN) - 1) << CCI_AUPLL_DL_CTRL_1_POS)
+#define CCI_AUPLL_DL_CTRL_1_UMSK   (~(((1U << CCI_AUPLL_DL_CTRL_1_LEN) - 1) << CCI_AUPLL_DL_CTRL_1_POS))
+
+struct cci_reg {
+    /* 0x0 : cci_cfg */
+    union {
+        struct {
+            uint32_t cci_en             : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t cci_slv_sel_cci2   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cci_mas_sel_cci2   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cci_mas_hw_mode    : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reg_m_cci_sclk_en  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_div_m_cci_sclk : 2;  /* [ 6: 5],        r/w,        0x1 */
+            uint32_t cfg_cci1_pre_read  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reg_scci_clk_inv   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reg_mcci_clk_inv   : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t cfg_mcci_dly_r     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31     : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_cfg;
+
+    /* 0x4 : cci_addr */
+    union {
+        struct {
+            uint32_t apb_cci_addr : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_addr;
+
+    /* 0x8 : cci_wdata */
+    union {
+        struct {
+            uint32_t apb_cci_wdata : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_wdata;
+
+    /* 0xC : cci_rdata */
+    union {
+        struct {
+            uint32_t apb_cci_rdata : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_rdata;
+
+    /* 0x10 : cci_ctl */
+    union {
+        struct {
+            uint32_t cci_write_flag : 1;  /* [    0],          r,        0x0 */
+            uint32_t cci_read_flag  : 1;  /* [    1],          r,        0x0 */
+            uint32_t ahb_state      : 2;  /* [ 3: 2],          r,        0x0 */
+            uint32_t reserved_4_31  : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cci_ctl;
+
+    /* 0x14  reserved */
+    uint8_t RESERVED0x14[1852];
+
+    /* 0x750 : audio_pll_cfg0 */
+    union {
+        struct {
+            uint32_t aupll_sdm_rstb     : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t aupll_postdiv_rstb : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t aupll_fbdv_rstb    : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t aupll_refdiv_rstb  : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pu_aupll_postdiv   : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t pu_aupll_fbdv      : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t pu_aupll_clamp_op  : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t pu_aupll_pfd       : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t pu_aupll_cp        : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t pu_aupll_sfreg     : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t pu_aupll           : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t pu_aupll_clktree   : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t reserved_12_31     : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg0;
+
+    /* 0x754 : audio_pll_cfg1 */
+    union {
+        struct {
+            uint32_t aupll_postdiv      : 7; /* [ 6: 0],        r/w,       0x12 */
+            uint32_t reserved_7         : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t aupll_refdiv_ratio : 4; /* [11: 8],        r/w,        0x4 */
+            uint32_t reserved_12_15     : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t aupll_refclk_sel   : 2; /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_19     : 2; /* [19:18],       rsvd,        0x0 */
+            uint32_t aupll_vg11_sel     : 2; /* [21:20],        r/w,        0x1 */
+            uint32_t reserved_22_23     : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t aupll_vg13_sel     : 2; /* [25:24],        r/w,        0x1 */
+            uint32_t reserved_26_31     : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg1;
+
+    /* 0x758 : audio_pll_cfg2 */
+    union {
+        struct {
+            uint32_t aupll_sel_cp_bias   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3        : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t aupll_icp_5u        : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t aupll_icp_1u        : 2;  /* [ 7: 6],        r/w,        0x1 */
+            uint32_t aupll_int_frac_sw   : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t aupll_cp_startup_en : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t aupll_cp_opamp_en   : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_31      : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg2;
+
+    /* 0x75C : audio_pll_cfg3 */
+    union {
+        struct {
+            uint32_t aupll_c4_en    : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3   : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t aupll_r4       : 2;  /* [ 5: 4],        r/w,        0x2 */
+            uint32_t reserved_6_7   : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t aupll_r4_short : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_11  : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t aupll_c3       : 2;  /* [13:12],        r/w,        0x2 */
+            uint32_t aupll_cz       : 2;  /* [15:14],        r/w,        0x2 */
+            uint32_t aupll_rz       : 3;  /* [18:16],        r/w,        0x5 */
+            uint32_t reserved_19_31 : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg3;
+
+    /* 0x760 : audio_pll_cfg4 */
+    union {
+        struct {
+            uint32_t aupll_sel_sample_clk : 2;  /* [ 1: 0],        r/w,        0x1 */
+            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t aupll_sel_fb_clk     : 2;  /* [ 5: 4],        r/w,        0x1 */
+            uint32_t reserved_6_7         : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t aupll_sdmclk_sel     : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31        : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg4;
+
+    /* 0x764 : audio_pll_cfg5 */
+    union {
+        struct {
+            uint32_t aupll_vco_speed : 3;  /* [ 2: 0],        r/w,        0x3 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg5;
+
+    /* 0x768 : audio_pll_cfg6 */
+    union {
+        struct {
+            uint32_t aupll_sdmin      : 19; /* [18: 0],        r/w,    0x161e5 */
+            uint32_t reserved_19_23   : 5;  /* [23:19],       rsvd,        0x0 */
+            uint32_t aupll_sdm_bypass : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t reserved_25_31   : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg6;
+
+    /* 0x76C : audio_pll_cfg7 */
+    union {
+        struct {
+            uint32_t aupll_sdm_order_sel    : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_15          : 15; /* [15: 1],       rsvd,        0x0 */
+            uint32_t aupll_sdm_sig_dith_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31         : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg7;
+
+    /* 0x770 : audio_pll_cfg8 */
+    union {
+        struct {
+            uint32_t aupll_en_div1       : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t aupll_en_div2       : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t aupll_en_div2p5     : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t aupll_en_div3       : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t aupll_en_div4       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t aupll_en_div5       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t aupll_en_div6       : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t aupll_en_div10      : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t aupll_en_div15      : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t aupll_sel_div1_div2 : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31      : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg8;
+
+    /* 0x774 : audio_pll_cfg9 */
+    union {
+        struct {
+            uint32_t aupll_dc_tp_out_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ten_aupll              : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ten_aupll_sfreg        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3             : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t dten_aupll_fin         : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t dten_aupll_fref        : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t dten_aupll_fsdm        : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t dten_aupll_div15       : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t dten_aupll_div5        : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t dten_aupll_postdiv_clk : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t dtest_aupll_pulldown   : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_31         : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg9;
+
+    /* 0x778 : audio_pll_cfg10 */
+    union {
+        struct {
+            uint32_t aupll_ssc_en            : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3            : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t aupll_ssc_cnt           : 8;  /* [11: 4],        r/w,       0x64 */
+            uint32_t aupll_ssc_gain          : 3;  /* [14:12],        r/w,        0x4 */
+            uint32_t reserved_15             : 1;  /* [   15],       rsvd,        0x0 */
+            uint32_t aupll_ssc_start_gate_en : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_19          : 3;  /* [19:17],       rsvd,        0x0 */
+            uint32_t aupll_ssc_start         : 1;  /* [   20],        r/w,        0x1 */
+            uint32_t reserved_21_31          : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg10;
+
+    /* 0x77C : audio_pll_cfg11 */
+    union {
+        struct {
+            uint32_t aupll_resv        : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_22    : 7;  /* [22:16],       rsvd,        0x0 */
+            uint32_t aupll_dl_ctrl_15  : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_10  : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_6   : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_5   : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_4   : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_3   : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_2p5 : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_2   : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t aupll_dl_ctrl_1   : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_pll_cfg11;
+};
+
+typedef volatile struct cci_reg cci_reg_t;
+
+#endif /* __CCI_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/ef_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/ef_ctrl_reg.h
new file mode 100755
index 0000000000..1ffa5149af
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/ef_ctrl_reg.h
@@ -0,0 +1,895 @@
+/**
+  ******************************************************************************
+  * @file    ef_ctrl_reg.h
+  * @version V1.0
+  * @date    2021-10-20
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __EF_CTRL_REG_H__
+#define  __EF_CTRL_REG_H__
+
+#include "bl616.h"
+
+/* 0x800 : ef_if_ctrl_0 */
+#define EF_CTRL_EF_IF_CTRL_0_OFFSET                             (0x800)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE                        EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS                    (0U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN                    (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK                    (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __EF_DATA_REG_H__
+#define  __EF_DATA_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : ef_cfg_0 */
+#define EF_DATA_EF_CFG_0_OFFSET                                 (0x0)
+#define EF_DATA_EF_SF_AES_MODE                                  EF_DATA_EF_SF_AES_MODE
+#define EF_DATA_EF_SF_AES_MODE_POS                              (0U)
+#define EF_DATA_EF_SF_AES_MODE_LEN                              (2U)
+#define EF_DATA_EF_SF_AES_MODE_MSK                              (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __GLB_REG_H__
+#define __GLB_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : soc_info0 */
+#define GLB_SOC_INFO0_OFFSET (0x0)
+#define GLB_CHIP_RDY         GLB_CHIP_RDY
+#define GLB_CHIP_RDY_POS     (27U)
+#define GLB_CHIP_RDY_LEN     (1U)
+#define GLB_CHIP_RDY_MSK     (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
+#define GLB_CHIP_RDY_UMSK    (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
+#define GLB_ID               GLB_ID
+#define GLB_ID_POS           (28U)
+#define GLB_ID_LEN           (4U)
+#define GLB_ID_MSK           (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
+#define GLB_ID_UMSK          (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))
+
+/* 0x50 : core_cfg16 */
+#define GLB_CORE_CFG16_OFFSET (0x50)
+#define GLB_NP_INT_STA0       GLB_NP_INT_STA0
+#define GLB_NP_INT_STA0_POS   (0U)
+#define GLB_NP_INT_STA0_LEN   (32U)
+#define GLB_NP_INT_STA0_MSK   (((1U << GLB_NP_INT_STA0_LEN) - 1) << GLB_NP_INT_STA0_POS)
+#define GLB_NP_INT_STA0_UMSK  (~(((1U << GLB_NP_INT_STA0_LEN) - 1) << GLB_NP_INT_STA0_POS))
+
+/* 0x54 : core_cfg17 */
+#define GLB_CORE_CFG17_OFFSET (0x54)
+#define GLB_NP_INT_STA1       GLB_NP_INT_STA1
+#define GLB_NP_INT_STA1_POS   (0U)
+#define GLB_NP_INT_STA1_LEN   (32U)
+#define GLB_NP_INT_STA1_MSK   (((1U << GLB_NP_INT_STA1_LEN) - 1) << GLB_NP_INT_STA1_POS)
+#define GLB_NP_INT_STA1_UMSK  (~(((1U << GLB_NP_INT_STA1_LEN) - 1) << GLB_NP_INT_STA1_POS))
+
+/* 0x58 : core_cfg18 */
+#define GLB_CORE_CFG18_OFFSET (0x58)
+#define GLB_NP_INT_MASK0      GLB_NP_INT_MASK0
+#define GLB_NP_INT_MASK0_POS  (0U)
+#define GLB_NP_INT_MASK0_LEN  (32U)
+#define GLB_NP_INT_MASK0_MSK  (((1U << GLB_NP_INT_MASK0_LEN) - 1) << GLB_NP_INT_MASK0_POS)
+#define GLB_NP_INT_MASK0_UMSK (~(((1U << GLB_NP_INT_MASK0_LEN) - 1) << GLB_NP_INT_MASK0_POS))
+
+/* 0x5C : core_cfg19 */
+#define GLB_CORE_CFG19_OFFSET (0x5C)
+#define GLB_NP_INT_MASK1      GLB_NP_INT_MASK1
+#define GLB_NP_INT_MASK1_POS  (0U)
+#define GLB_NP_INT_MASK1_LEN  (32U)
+#define GLB_NP_INT_MASK1_MSK  (((1U << GLB_NP_INT_MASK1_LEN) - 1) << GLB_NP_INT_MASK1_POS)
+#define GLB_NP_INT_MASK1_UMSK (~(((1U << GLB_NP_INT_MASK1_LEN) - 1) << GLB_NP_INT_MASK1_POS))
+
+/* 0x60 : core_cfg20 */
+#define GLB_CORE_CFG20_OFFSET (0x60)
+#define GLB_NP_INT_CLR0       GLB_NP_INT_CLR0
+#define GLB_NP_INT_CLR0_POS   (0U)
+#define GLB_NP_INT_CLR0_LEN   (32U)
+#define GLB_NP_INT_CLR0_MSK   (((1U << GLB_NP_INT_CLR0_LEN) - 1) << GLB_NP_INT_CLR0_POS)
+#define GLB_NP_INT_CLR0_UMSK  (~(((1U << GLB_NP_INT_CLR0_LEN) - 1) << GLB_NP_INT_CLR0_POS))
+
+/* 0x64 : core_cfg21 */
+#define GLB_CORE_CFG21_OFFSET (0x64)
+#define GLB_NP_INT_CLR1       GLB_NP_INT_CLR1
+#define GLB_NP_INT_CLR1_POS   (0U)
+#define GLB_NP_INT_CLR1_LEN   (32U)
+#define GLB_NP_INT_CLR1_MSK   (((1U << GLB_NP_INT_CLR1_LEN) - 1) << GLB_NP_INT_CLR1_POS)
+#define GLB_NP_INT_CLR1_UMSK  (~(((1U << GLB_NP_INT_CLR1_LEN) - 1) << GLB_NP_INT_CLR1_POS))
+
+/* 0x90 : sys_cfg0 */
+#define GLB_SYS_CFG0_OFFSET       (0x90)
+#define GLB_REG_PLL_EN            GLB_REG_PLL_EN
+#define GLB_REG_PLL_EN_POS        (0U)
+#define GLB_REG_PLL_EN_LEN        (1U)
+#define GLB_REG_PLL_EN_MSK        (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
+#define GLB_REG_PLL_EN_UMSK       (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
+#define GLB_REG_FCLK_EN           GLB_REG_FCLK_EN
+#define GLB_REG_FCLK_EN_POS       (1U)
+#define GLB_REG_FCLK_EN_LEN       (1U)
+#define GLB_REG_FCLK_EN_MSK       (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
+#define GLB_REG_FCLK_EN_UMSK      (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
+#define GLB_REG_HCLK_EN           GLB_REG_HCLK_EN
+#define GLB_REG_HCLK_EN_POS       (2U)
+#define GLB_REG_HCLK_EN_LEN       (1U)
+#define GLB_REG_HCLK_EN_MSK       (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
+#define GLB_REG_HCLK_EN_UMSK      (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
+#define GLB_REG_BCLK_EN           GLB_REG_BCLK_EN
+#define GLB_REG_BCLK_EN_POS       (3U)
+#define GLB_REG_BCLK_EN_LEN       (1U)
+#define GLB_REG_BCLK_EN_MSK       (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
+#define GLB_REG_BCLK_EN_UMSK      (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
+#define GLB_HBN_ROOT_CLK_SEL      GLB_HBN_ROOT_CLK_SEL
+#define GLB_HBN_ROOT_CLK_SEL_POS  (6U)
+#define GLB_HBN_ROOT_CLK_SEL_LEN  (2U)
+#define GLB_HBN_ROOT_CLK_SEL_MSK  (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
+#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
+#define GLB_REG_HCLK_DIV          GLB_REG_HCLK_DIV
+#define GLB_REG_HCLK_DIV_POS      (8U)
+#define GLB_REG_HCLK_DIV_LEN      (8U)
+#define GLB_REG_HCLK_DIV_MSK      (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
+#define GLB_REG_HCLK_DIV_UMSK     (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
+#define GLB_REG_BCLK_DIV          GLB_REG_BCLK_DIV
+#define GLB_REG_BCLK_DIV_POS      (16U)
+#define GLB_REG_BCLK_DIV_LEN      (8U)
+#define GLB_REG_BCLK_DIV_MSK      (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
+#define GLB_REG_BCLK_DIV_UMSK     (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
+
+/* 0x94 : sys_cfg1 */
+#define GLB_SYS_CFG1_OFFSET             (0x94)
+#define GLB_REG_BCLK_DIV_ACT_PULSE      GLB_REG_BCLK_DIV_ACT_PULSE
+#define GLB_REG_BCLK_DIV_ACT_PULSE_POS  (0U)
+#define GLB_REG_BCLK_DIV_ACT_PULSE_LEN  (1U)
+#define GLB_REG_BCLK_DIV_ACT_PULSE_MSK  (((1U << GLB_REG_BCLK_DIV_ACT_PULSE_LEN) - 1) << GLB_REG_BCLK_DIV_ACT_PULSE_POS)
+#define GLB_REG_BCLK_DIV_ACT_PULSE_UMSK (~(((1U << GLB_REG_BCLK_DIV_ACT_PULSE_LEN) - 1) << GLB_REG_BCLK_DIV_ACT_PULSE_POS))
+#define GLB_REG_BCLK_DIV_BYPASS         GLB_REG_BCLK_DIV_BYPASS
+#define GLB_REG_BCLK_DIV_BYPASS_POS     (1U)
+#define GLB_REG_BCLK_DIV_BYPASS_LEN     (1U)
+#define GLB_REG_BCLK_DIV_BYPASS_MSK     (((1U << GLB_REG_BCLK_DIV_BYPASS_LEN) - 1) << GLB_REG_BCLK_DIV_BYPASS_POS)
+#define GLB_REG_BCLK_DIV_BYPASS_UMSK    (~(((1U << GLB_REG_BCLK_DIV_BYPASS_LEN) - 1) << GLB_REG_BCLK_DIV_BYPASS_POS))
+#define GLB_STS_BCLK_PROT_DONE          GLB_STS_BCLK_PROT_DONE
+#define GLB_STS_BCLK_PROT_DONE_POS      (2U)
+#define GLB_STS_BCLK_PROT_DONE_LEN      (1U)
+#define GLB_STS_BCLK_PROT_DONE_MSK      (((1U << GLB_STS_BCLK_PROT_DONE_LEN) - 1) << GLB_STS_BCLK_PROT_DONE_POS)
+#define GLB_STS_BCLK_PROT_DONE_UMSK     (~(((1U << GLB_STS_BCLK_PROT_DONE_LEN) - 1) << GLB_STS_BCLK_PROT_DONE_POS))
+#define GLB_REG_BCLK_SW_DONE_CNT        GLB_REG_BCLK_SW_DONE_CNT
+#define GLB_REG_BCLK_SW_DONE_CNT_POS    (4U)
+#define GLB_REG_BCLK_SW_DONE_CNT_LEN    (4U)
+#define GLB_REG_BCLK_SW_DONE_CNT_MSK    (((1U << GLB_REG_BCLK_SW_DONE_CNT_LEN) - 1) << GLB_REG_BCLK_SW_DONE_CNT_POS)
+#define GLB_REG_BCLK_SW_DONE_CNT_UMSK   (~(((1U << GLB_REG_BCLK_SW_DONE_CNT_LEN) - 1) << GLB_REG_BCLK_SW_DONE_CNT_POS))
+#define GLB_FCLK_SW_STATE               GLB_FCLK_SW_STATE
+#define GLB_FCLK_SW_STATE_POS           (24U)
+#define GLB_FCLK_SW_STATE_LEN           (3U)
+#define GLB_FCLK_SW_STATE_MSK           (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
+#define GLB_FCLK_SW_STATE_UMSK          (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
+
+/* 0xA0 : bus_cfg0 */
+#define GLB_BUS_CFG0_OFFSET        (0xA0)
+#define GLB_RG_APB2_PCK_FORCE      GLB_RG_APB2_PCK_FORCE
+#define GLB_RG_APB2_PCK_FORCE_POS  (0U)
+#define GLB_RG_APB2_PCK_FORCE_LEN  (16U)
+#define GLB_RG_APB2_PCK_FORCE_MSK  (((1U << GLB_RG_APB2_PCK_FORCE_LEN) - 1) << GLB_RG_APB2_PCK_FORCE_POS)
+#define GLB_RG_APB2_PCK_FORCE_UMSK (~(((1U << GLB_RG_APB2_PCK_FORCE_LEN) - 1) << GLB_RG_APB2_PCK_FORCE_POS))
+#define GLB_RG_APB_PCK_FORCE       GLB_RG_APB_PCK_FORCE
+#define GLB_RG_APB_PCK_FORCE_POS   (16U)
+#define GLB_RG_APB_PCK_FORCE_LEN   (16U)
+#define GLB_RG_APB_PCK_FORCE_MSK   (((1U << GLB_RG_APB_PCK_FORCE_LEN) - 1) << GLB_RG_APB_PCK_FORCE_POS)
+#define GLB_RG_APB_PCK_FORCE_UMSK  (~(((1U << GLB_RG_APB_PCK_FORCE_LEN) - 1) << GLB_RG_APB_PCK_FORCE_POS))
+
+/* 0xF0 : rtc_cfg0 */
+#define GLB_RTC_CFG0_OFFSET (0xF0)
+
+/* 0x110 : adc_cfg0 */
+#define GLB_ADC_CFG0_OFFSET        (0x110)
+#define GLB_GPADC_32M_CLK_DIV      GLB_GPADC_32M_CLK_DIV
+#define GLB_GPADC_32M_CLK_DIV_POS  (0U)
+#define GLB_GPADC_32M_CLK_DIV_LEN  (6U)
+#define GLB_GPADC_32M_CLK_DIV_MSK  (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
+#define GLB_GPADC_32M_CLK_DIV_UMSK (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
+#define GLB_GPADC_32M_CLK_SEL      GLB_GPADC_32M_CLK_SEL
+#define GLB_GPADC_32M_CLK_SEL_POS  (7U)
+#define GLB_GPADC_32M_CLK_SEL_LEN  (1U)
+#define GLB_GPADC_32M_CLK_SEL_MSK  (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
+#define GLB_GPADC_32M_CLK_SEL_UMSK (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
+#define GLB_GPADC_32M_DIV_EN       GLB_GPADC_32M_DIV_EN
+#define GLB_GPADC_32M_DIV_EN_POS   (8U)
+#define GLB_GPADC_32M_DIV_EN_LEN   (1U)
+#define GLB_GPADC_32M_DIV_EN_MSK   (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
+#define GLB_GPADC_32M_DIV_EN_UMSK  (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
+
+/* 0x120 : dac_cfg0 */
+#define GLB_DAC_CFG0_OFFSET        (0x120)
+#define GLB_GPDACA_RSTN_ANA        GLB_GPDACA_RSTN_ANA
+#define GLB_GPDACA_RSTN_ANA_POS    (0U)
+#define GLB_GPDACA_RSTN_ANA_LEN    (1U)
+#define GLB_GPDACA_RSTN_ANA_MSK    (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
+#define GLB_GPDACA_RSTN_ANA_UMSK   (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
+#define GLB_GPDACB_RSTN_ANA        GLB_GPDACB_RSTN_ANA
+#define GLB_GPDACB_RSTN_ANA_POS    (1U)
+#define GLB_GPDACB_RSTN_ANA_LEN    (1U)
+#define GLB_GPDACB_RSTN_ANA_MSK    (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
+#define GLB_GPDACB_RSTN_ANA_UMSK   (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
+#define GLB_GPDAC_TEST_EN          GLB_GPDAC_TEST_EN
+#define GLB_GPDAC_TEST_EN_POS      (7U)
+#define GLB_GPDAC_TEST_EN_LEN      (1U)
+#define GLB_GPDAC_TEST_EN_MSK      (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
+#define GLB_GPDAC_TEST_EN_UMSK     (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
+#define GLB_GPDAC_REF_SEL          GLB_GPDAC_REF_SEL
+#define GLB_GPDAC_REF_SEL_POS      (8U)
+#define GLB_GPDAC_REF_SEL_LEN      (1U)
+#define GLB_GPDAC_REF_SEL_MSK      (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
+#define GLB_GPDAC_REF_SEL_UMSK     (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
+#define GLB_GPDAC_TEST_SEL         GLB_GPDAC_TEST_SEL
+#define GLB_GPDAC_TEST_SEL_POS     (9U)
+#define GLB_GPDAC_TEST_SEL_LEN     (3U)
+#define GLB_GPDAC_TEST_SEL_MSK     (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
+#define GLB_GPDAC_TEST_SEL_UMSK    (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
+#define GLB_GPDAC_ANA_CLK_SEL      GLB_GPDAC_ANA_CLK_SEL
+#define GLB_GPDAC_ANA_CLK_SEL_POS  (12U)
+#define GLB_GPDAC_ANA_CLK_SEL_LEN  (1U)
+#define GLB_GPDAC_ANA_CLK_SEL_MSK  (((1U << GLB_GPDAC_ANA_CLK_SEL_LEN) - 1) << GLB_GPDAC_ANA_CLK_SEL_POS)
+#define GLB_GPDAC_ANA_CLK_SEL_UMSK (~(((1U << GLB_GPDAC_ANA_CLK_SEL_LEN) - 1) << GLB_GPDAC_ANA_CLK_SEL_POS))
+#define GLB_GPDAC_DAT_CHA_SEL      GLB_GPDAC_DAT_CHA_SEL
+#define GLB_GPDAC_DAT_CHA_SEL_POS  (13U)
+#define GLB_GPDAC_DAT_CHA_SEL_LEN  (1U)
+#define GLB_GPDAC_DAT_CHA_SEL_MSK  (((1U << GLB_GPDAC_DAT_CHA_SEL_LEN) - 1) << GLB_GPDAC_DAT_CHA_SEL_POS)
+#define GLB_GPDAC_DAT_CHA_SEL_UMSK (~(((1U << GLB_GPDAC_DAT_CHA_SEL_LEN) - 1) << GLB_GPDAC_DAT_CHA_SEL_POS))
+#define GLB_GPDAC_DAT_CHB_SEL      GLB_GPDAC_DAT_CHB_SEL
+#define GLB_GPDAC_DAT_CHB_SEL_POS  (14U)
+#define GLB_GPDAC_DAT_CHB_SEL_LEN  (1U)
+#define GLB_GPDAC_DAT_CHB_SEL_MSK  (((1U << GLB_GPDAC_DAT_CHB_SEL_LEN) - 1) << GLB_GPDAC_DAT_CHB_SEL_POS)
+#define GLB_GPDAC_DAT_CHB_SEL_UMSK (~(((1U << GLB_GPDAC_DAT_CHB_SEL_LEN) - 1) << GLB_GPDAC_DAT_CHB_SEL_POS))
+#define GLB_GPDAC_RESERVED         GLB_GPDAC_RESERVED
+#define GLB_GPDAC_RESERVED_POS     (24U)
+#define GLB_GPDAC_RESERVED_LEN     (8U)
+#define GLB_GPDAC_RESERVED_MSK     (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
+#define GLB_GPDAC_RESERVED_UMSK    (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
+
+/* 0x124 : dac_cfg1 */
+#define GLB_DAC_CFG1_OFFSET     (0x124)
+#define GLB_GPDAC_A_EN          GLB_GPDAC_A_EN
+#define GLB_GPDAC_A_EN_POS      (0U)
+#define GLB_GPDAC_A_EN_LEN      (1U)
+#define GLB_GPDAC_A_EN_MSK      (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
+#define GLB_GPDAC_A_EN_UMSK     (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
+#define GLB_GPDAC_IOA_EN        GLB_GPDAC_IOA_EN
+#define GLB_GPDAC_IOA_EN_POS    (1U)
+#define GLB_GPDAC_IOA_EN_LEN    (1U)
+#define GLB_GPDAC_IOA_EN_MSK    (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
+#define GLB_GPDAC_IOA_EN_UMSK   (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
+#define GLB_GPDAC_A_RNG         GLB_GPDAC_A_RNG
+#define GLB_GPDAC_A_RNG_POS     (18U)
+#define GLB_GPDAC_A_RNG_LEN     (2U)
+#define GLB_GPDAC_A_RNG_MSK     (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
+#define GLB_GPDAC_A_RNG_UMSK    (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
+#define GLB_GPDAC_A_OUTMUX      GLB_GPDAC_A_OUTMUX
+#define GLB_GPDAC_A_OUTMUX_POS  (20U)
+#define GLB_GPDAC_A_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_A_OUTMUX_MSK  (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
+#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
+
+/* 0x128 : dac_cfg2 */
+#define GLB_DAC_CFG2_OFFSET     (0x128)
+#define GLB_GPDAC_B_EN          GLB_GPDAC_B_EN
+#define GLB_GPDAC_B_EN_POS      (0U)
+#define GLB_GPDAC_B_EN_LEN      (1U)
+#define GLB_GPDAC_B_EN_MSK      (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
+#define GLB_GPDAC_B_EN_UMSK     (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
+#define GLB_GPDAC_IOB_EN        GLB_GPDAC_IOB_EN
+#define GLB_GPDAC_IOB_EN_POS    (1U)
+#define GLB_GPDAC_IOB_EN_LEN    (1U)
+#define GLB_GPDAC_IOB_EN_MSK    (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
+#define GLB_GPDAC_IOB_EN_UMSK   (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
+#define GLB_GPDAC_B_RNG         GLB_GPDAC_B_RNG
+#define GLB_GPDAC_B_RNG_POS     (18U)
+#define GLB_GPDAC_B_RNG_LEN     (2U)
+#define GLB_GPDAC_B_RNG_MSK     (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
+#define GLB_GPDAC_B_RNG_UMSK    (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
+#define GLB_GPDAC_B_OUTMUX      GLB_GPDAC_B_OUTMUX
+#define GLB_GPDAC_B_OUTMUX_POS  (20U)
+#define GLB_GPDAC_B_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_B_OUTMUX_MSK  (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
+#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
+
+/* 0x12C : dac_cfg3 */
+#define GLB_DAC_CFG3_OFFSET   (0x12C)
+#define GLB_GPDAC_B_DATA      GLB_GPDAC_B_DATA
+#define GLB_GPDAC_B_DATA_POS  (0U)
+#define GLB_GPDAC_B_DATA_LEN  (12U)
+#define GLB_GPDAC_B_DATA_MSK  (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
+#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
+#define GLB_GPDAC_A_DATA      GLB_GPDAC_A_DATA
+#define GLB_GPDAC_A_DATA_POS  (16U)
+#define GLB_GPDAC_A_DATA_LEN  (12U)
+#define GLB_GPDAC_A_DATA_MSK  (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
+#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
+
+/* 0x130 : dma_cfg0 */
+#define GLB_DMA_CFG0_OFFSET (0x130)
+#define GLB_DMA_CLK_EN      GLB_DMA_CLK_EN
+#define GLB_DMA_CLK_EN_POS  (24U)
+#define GLB_DMA_CLK_EN_LEN  (8U)
+#define GLB_DMA_CLK_EN_MSK  (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
+#define GLB_DMA_CLK_EN_UMSK (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
+
+/* 0x134 : dma_cfg1 */
+#define GLB_DMA_CFG1_OFFSET  (0x134)
+#define GLB_DMA2_CLK_EN      GLB_DMA2_CLK_EN
+#define GLB_DMA2_CLK_EN_POS  (24U)
+#define GLB_DMA2_CLK_EN_LEN  (8U)
+#define GLB_DMA2_CLK_EN_MSK  (((1U << GLB_DMA2_CLK_EN_LEN) - 1) << GLB_DMA2_CLK_EN_POS)
+#define GLB_DMA2_CLK_EN_UMSK (~(((1U << GLB_DMA2_CLK_EN_LEN) - 1) << GLB_DMA2_CLK_EN_POS))
+
+/* 0x138 : dma_cfg2 */
+#define GLB_DMA_CFG2_OFFSET     (0x138)
+#define GLB_REG_DMA_CN_SEL      GLB_REG_DMA_CN_SEL
+#define GLB_REG_DMA_CN_SEL_POS  (0U)
+#define GLB_REG_DMA_CN_SEL_LEN  (32U)
+#define GLB_REG_DMA_CN_SEL_MSK  (((1U << GLB_REG_DMA_CN_SEL_LEN) - 1) << GLB_REG_DMA_CN_SEL_POS)
+#define GLB_REG_DMA_CN_SEL_UMSK (~(((1U << GLB_REG_DMA_CN_SEL_LEN) - 1) << GLB_REG_DMA_CN_SEL_POS))
+
+/* 0x140 : ir_cfg0 */
+#define GLB_IR_CFG0_OFFSET  (0x140)
+#define GLB_IR_CLK_DIV      GLB_IR_CLK_DIV
+#define GLB_IR_CLK_DIV_POS  (16U)
+#define GLB_IR_CLK_DIV_LEN  (6U)
+#define GLB_IR_CLK_DIV_MSK  (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
+#define GLB_IR_CLK_DIV_UMSK (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
+#define GLB_IR_CLK_EN       GLB_IR_CLK_EN
+#define GLB_IR_CLK_EN_POS   (23U)
+#define GLB_IR_CLK_EN_LEN   (1U)
+#define GLB_IR_CLK_EN_MSK   (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
+#define GLB_IR_CLK_EN_UMSK  (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
+
+/* 0x144 : ir_cfg1 */
+#define GLB_IR_CFG1_OFFSET      (0x144)
+#define GLB_IR_RX_GPIO_SEL      GLB_IR_RX_GPIO_SEL
+#define GLB_IR_RX_GPIO_SEL_POS  (8U)
+#define GLB_IR_RX_GPIO_SEL_LEN  (4U)
+#define GLB_IR_RX_GPIO_SEL_MSK  (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
+#define GLB_IR_RX_GPIO_SEL_UMSK (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
+
+/* 0x150 : uart_cfg0 */
+#define GLB_UART_CFG0_OFFSET       (0x150)
+#define GLB_UART_CLK_DIV           GLB_UART_CLK_DIV
+#define GLB_UART_CLK_DIV_POS       (0U)
+#define GLB_UART_CLK_DIV_LEN       (3U)
+#define GLB_UART_CLK_DIV_MSK       (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
+#define GLB_UART_CLK_DIV_UMSK      (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
+#define GLB_UART_CLK_EN            GLB_UART_CLK_EN
+#define GLB_UART_CLK_EN_POS        (4U)
+#define GLB_UART_CLK_EN_LEN        (1U)
+#define GLB_UART_CLK_EN_MSK        (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
+#define GLB_UART_CLK_EN_UMSK       (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
+#define GLB_HBN_UART_CLK_SEL       GLB_HBN_UART_CLK_SEL
+#define GLB_HBN_UART_CLK_SEL_POS   (7U)
+#define GLB_HBN_UART_CLK_SEL_LEN   (1U)
+#define GLB_HBN_UART_CLK_SEL_MSK   (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
+#define GLB_HBN_UART_CLK_SEL_UMSK  (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
+#define GLB_HBN_UART_CLK_SEL2      GLB_HBN_UART_CLK_SEL2
+#define GLB_HBN_UART_CLK_SEL2_POS  (22U)
+#define GLB_HBN_UART_CLK_SEL2_LEN  (1U)
+#define GLB_HBN_UART_CLK_SEL2_MSK  (((1U << GLB_HBN_UART_CLK_SEL2_LEN) - 1) << GLB_HBN_UART_CLK_SEL2_POS)
+#define GLB_HBN_UART_CLK_SEL2_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL2_LEN) - 1) << GLB_HBN_UART_CLK_SEL2_POS))
+
+/* 0x154 : uart_cfg1 */
+#define GLB_UART_CFG1_OFFSET    (0x154)
+#define GLB_UART_SIG_0_SEL      GLB_UART_SIG_0_SEL
+#define GLB_UART_SIG_0_SEL_POS  (0U)
+#define GLB_UART_SIG_0_SEL_LEN  (4U)
+#define GLB_UART_SIG_0_SEL_MSK  (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
+#define GLB_UART_SIG_0_SEL_UMSK (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
+#define GLB_UART_SIG_1_SEL      GLB_UART_SIG_1_SEL
+#define GLB_UART_SIG_1_SEL_POS  (4U)
+#define GLB_UART_SIG_1_SEL_LEN  (4U)
+#define GLB_UART_SIG_1_SEL_MSK  (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
+#define GLB_UART_SIG_1_SEL_UMSK (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
+#define GLB_UART_SIG_2_SEL      GLB_UART_SIG_2_SEL
+#define GLB_UART_SIG_2_SEL_POS  (8U)
+#define GLB_UART_SIG_2_SEL_LEN  (4U)
+#define GLB_UART_SIG_2_SEL_MSK  (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
+#define GLB_UART_SIG_2_SEL_UMSK (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
+#define GLB_UART_SIG_3_SEL      GLB_UART_SIG_3_SEL
+#define GLB_UART_SIG_3_SEL_POS  (12U)
+#define GLB_UART_SIG_3_SEL_LEN  (4U)
+#define GLB_UART_SIG_3_SEL_MSK  (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
+#define GLB_UART_SIG_3_SEL_UMSK (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
+#define GLB_UART_SIG_4_SEL      GLB_UART_SIG_4_SEL
+#define GLB_UART_SIG_4_SEL_POS  (16U)
+#define GLB_UART_SIG_4_SEL_LEN  (4U)
+#define GLB_UART_SIG_4_SEL_MSK  (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
+#define GLB_UART_SIG_4_SEL_UMSK (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
+#define GLB_UART_SIG_5_SEL      GLB_UART_SIG_5_SEL
+#define GLB_UART_SIG_5_SEL_POS  (20U)
+#define GLB_UART_SIG_5_SEL_LEN  (4U)
+#define GLB_UART_SIG_5_SEL_MSK  (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
+#define GLB_UART_SIG_5_SEL_UMSK (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
+#define GLB_UART_SIG_6_SEL      GLB_UART_SIG_6_SEL
+#define GLB_UART_SIG_6_SEL_POS  (24U)
+#define GLB_UART_SIG_6_SEL_LEN  (4U)
+#define GLB_UART_SIG_6_SEL_MSK  (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
+#define GLB_UART_SIG_6_SEL_UMSK (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
+#define GLB_UART_SIG_7_SEL      GLB_UART_SIG_7_SEL
+#define GLB_UART_SIG_7_SEL_POS  (28U)
+#define GLB_UART_SIG_7_SEL_LEN  (4U)
+#define GLB_UART_SIG_7_SEL_MSK  (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
+#define GLB_UART_SIG_7_SEL_UMSK (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
+
+/* 0x158 : uart_cfg2 */
+#define GLB_UART_CFG2_OFFSET     (0x158)
+#define GLB_UART_SIG_8_SEL       GLB_UART_SIG_8_SEL
+#define GLB_UART_SIG_8_SEL_POS   (0U)
+#define GLB_UART_SIG_8_SEL_LEN   (4U)
+#define GLB_UART_SIG_8_SEL_MSK   (((1U << GLB_UART_SIG_8_SEL_LEN) - 1) << GLB_UART_SIG_8_SEL_POS)
+#define GLB_UART_SIG_8_SEL_UMSK  (~(((1U << GLB_UART_SIG_8_SEL_LEN) - 1) << GLB_UART_SIG_8_SEL_POS))
+#define GLB_UART_SIG_9_SEL       GLB_UART_SIG_9_SEL
+#define GLB_UART_SIG_9_SEL_POS   (4U)
+#define GLB_UART_SIG_9_SEL_LEN   (4U)
+#define GLB_UART_SIG_9_SEL_MSK   (((1U << GLB_UART_SIG_9_SEL_LEN) - 1) << GLB_UART_SIG_9_SEL_POS)
+#define GLB_UART_SIG_9_SEL_UMSK  (~(((1U << GLB_UART_SIG_9_SEL_LEN) - 1) << GLB_UART_SIG_9_SEL_POS))
+#define GLB_UART_SIG_10_SEL      GLB_UART_SIG_10_SEL
+#define GLB_UART_SIG_10_SEL_POS  (8U)
+#define GLB_UART_SIG_10_SEL_LEN  (4U)
+#define GLB_UART_SIG_10_SEL_MSK  (((1U << GLB_UART_SIG_10_SEL_LEN) - 1) << GLB_UART_SIG_10_SEL_POS)
+#define GLB_UART_SIG_10_SEL_UMSK (~(((1U << GLB_UART_SIG_10_SEL_LEN) - 1) << GLB_UART_SIG_10_SEL_POS))
+#define GLB_UART_SIG_11_SEL      GLB_UART_SIG_11_SEL
+#define GLB_UART_SIG_11_SEL_POS  (12U)
+#define GLB_UART_SIG_11_SEL_LEN  (4U)
+#define GLB_UART_SIG_11_SEL_MSK  (((1U << GLB_UART_SIG_11_SEL_LEN) - 1) << GLB_UART_SIG_11_SEL_POS)
+#define GLB_UART_SIG_11_SEL_UMSK (~(((1U << GLB_UART_SIG_11_SEL_LEN) - 1) << GLB_UART_SIG_11_SEL_POS))
+
+/* 0x170 : sf_cfg0 */
+#define GLB_SF_CFG0_OFFSET   (0x170)
+#define GLB_SF_CLK_DIV       GLB_SF_CLK_DIV
+#define GLB_SF_CLK_DIV_POS   (8U)
+#define GLB_SF_CLK_DIV_LEN   (3U)
+#define GLB_SF_CLK_DIV_MSK   (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
+#define GLB_SF_CLK_DIV_UMSK  (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
+#define GLB_SF_CLK_EN        GLB_SF_CLK_EN
+#define GLB_SF_CLK_EN_POS    (11U)
+#define GLB_SF_CLK_EN_LEN    (1U)
+#define GLB_SF_CLK_EN_MSK    (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
+#define GLB_SF_CLK_EN_UMSK   (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
+#define GLB_SF_CLK_SEL       GLB_SF_CLK_SEL
+#define GLB_SF_CLK_SEL_POS   (12U)
+#define GLB_SF_CLK_SEL_LEN   (2U)
+#define GLB_SF_CLK_SEL_MSK   (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
+#define GLB_SF_CLK_SEL_UMSK  (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
+#define GLB_SF_CLK_SEL2      GLB_SF_CLK_SEL2
+#define GLB_SF_CLK_SEL2_POS  (14U)
+#define GLB_SF_CLK_SEL2_LEN  (2U)
+#define GLB_SF_CLK_SEL2_MSK  (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
+#define GLB_SF_CLK_SEL2_UMSK (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
+
+/* 0x180 : i2c_cfg0 */
+#define GLB_I2C_CFG0_OFFSET  (0x180)
+#define GLB_I2C_CLK_DIV      GLB_I2C_CLK_DIV
+#define GLB_I2C_CLK_DIV_POS  (16U)
+#define GLB_I2C_CLK_DIV_LEN  (8U)
+#define GLB_I2C_CLK_DIV_MSK  (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
+#define GLB_I2C_CLK_DIV_UMSK (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
+#define GLB_I2C_CLK_EN       GLB_I2C_CLK_EN
+#define GLB_I2C_CLK_EN_POS   (24U)
+#define GLB_I2C_CLK_EN_LEN   (1U)
+#define GLB_I2C_CLK_EN_MSK   (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
+#define GLB_I2C_CLK_EN_UMSK  (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
+#define GLB_I2C_CLK_SEL      GLB_I2C_CLK_SEL
+#define GLB_I2C_CLK_SEL_POS  (25U)
+#define GLB_I2C_CLK_SEL_LEN  (1U)
+#define GLB_I2C_CLK_SEL_MSK  (((1U << GLB_I2C_CLK_SEL_LEN) - 1) << GLB_I2C_CLK_SEL_POS)
+#define GLB_I2C_CLK_SEL_UMSK (~(((1U << GLB_I2C_CLK_SEL_LEN) - 1) << GLB_I2C_CLK_SEL_POS))
+
+/* 0x190 : i2s_cfg0 */
+#define GLB_I2S_CFG0_OFFSET             (0x190)
+#define GLB_REG_I2S_REF_CLK_DIV         GLB_REG_I2S_REF_CLK_DIV
+#define GLB_REG_I2S_REF_CLK_DIV_POS     (0U)
+#define GLB_REG_I2S_REF_CLK_DIV_LEN     (6U)
+#define GLB_REG_I2S_REF_CLK_DIV_MSK     (((1U << GLB_REG_I2S_REF_CLK_DIV_LEN) - 1) << GLB_REG_I2S_REF_CLK_DIV_POS)
+#define GLB_REG_I2S_REF_CLK_DIV_UMSK    (~(((1U << GLB_REG_I2S_REF_CLK_DIV_LEN) - 1) << GLB_REG_I2S_REF_CLK_DIV_POS))
+#define GLB_REG_I2S_DI_REF_CLK_SEL      GLB_REG_I2S_DI_REF_CLK_SEL
+#define GLB_REG_I2S_DI_REF_CLK_SEL_POS  (6U)
+#define GLB_REG_I2S_DI_REF_CLK_SEL_LEN  (1U)
+#define GLB_REG_I2S_DI_REF_CLK_SEL_MSK  (((1U << GLB_REG_I2S_DI_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DI_REF_CLK_SEL_POS)
+#define GLB_REG_I2S_DI_REF_CLK_SEL_UMSK (~(((1U << GLB_REG_I2S_DI_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DI_REF_CLK_SEL_POS))
+#define GLB_REG_I2S_REF_CLK_EN          GLB_REG_I2S_REF_CLK_EN
+#define GLB_REG_I2S_REF_CLK_EN_POS      (7U)
+#define GLB_REG_I2S_REF_CLK_EN_LEN      (1U)
+#define GLB_REG_I2S_REF_CLK_EN_MSK      (((1U << GLB_REG_I2S_REF_CLK_EN_LEN) - 1) << GLB_REG_I2S_REF_CLK_EN_POS)
+#define GLB_REG_I2S_REF_CLK_EN_UMSK     (~(((1U << GLB_REG_I2S_REF_CLK_EN_LEN) - 1) << GLB_REG_I2S_REF_CLK_EN_POS))
+#define GLB_REG_I2S_DO_REF_CLK_SEL      GLB_REG_I2S_DO_REF_CLK_SEL
+#define GLB_REG_I2S_DO_REF_CLK_SEL_POS  (8U)
+#define GLB_REG_I2S_DO_REF_CLK_SEL_LEN  (1U)
+#define GLB_REG_I2S_DO_REF_CLK_SEL_MSK  (((1U << GLB_REG_I2S_DO_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DO_REF_CLK_SEL_POS)
+#define GLB_REG_I2S_DO_REF_CLK_SEL_UMSK (~(((1U << GLB_REG_I2S_DO_REF_CLK_SEL_LEN) - 1) << GLB_REG_I2S_DO_REF_CLK_SEL_POS))
+
+/* 0x1B0 : spi_cfg0 */
+#define GLB_SPI_CFG0_OFFSET   (0x1B0)
+#define GLB_SPI_CLK_DIV       GLB_SPI_CLK_DIV
+#define GLB_SPI_CLK_DIV_POS   (0U)
+#define GLB_SPI_CLK_DIV_LEN   (5U)
+#define GLB_SPI_CLK_DIV_MSK   (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
+#define GLB_SPI_CLK_DIV_UMSK  (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
+#define GLB_SPI_CLK_EN        GLB_SPI_CLK_EN
+#define GLB_SPI_CLK_EN_POS    (8U)
+#define GLB_SPI_CLK_EN_LEN    (1U)
+#define GLB_SPI_CLK_EN_MSK    (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
+#define GLB_SPI_CLK_EN_UMSK   (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
+#define GLB_SPI_CLK_SEL       GLB_SPI_CLK_SEL
+#define GLB_SPI_CLK_SEL_POS   (9U)
+#define GLB_SPI_CLK_SEL_LEN   (1U)
+#define GLB_SPI_CLK_SEL_MSK   (((1U << GLB_SPI_CLK_SEL_LEN) - 1) << GLB_SPI_CLK_SEL_POS)
+#define GLB_SPI_CLK_SEL_UMSK  (~(((1U << GLB_SPI_CLK_SEL_LEN) - 1) << GLB_SPI_CLK_SEL_POS))
+#define GLB_SPI_SWAP_SET      GLB_SPI_SWAP_SET
+#define GLB_SPI_SWAP_SET_POS  (16U)
+#define GLB_SPI_SWAP_SET_LEN  (4U)
+#define GLB_SPI_SWAP_SET_MSK  (((1U << GLB_SPI_SWAP_SET_LEN) - 1) << GLB_SPI_SWAP_SET_POS)
+#define GLB_SPI_SWAP_SET_UMSK (~(((1U << GLB_SPI_SWAP_SET_LEN) - 1) << GLB_SPI_SWAP_SET_POS))
+
+/* 0x1C0 : pec_cfg0 */
+#define GLB_PEC_CFG0_OFFSET  (0x1C0)
+#define GLB_PEC_CLK_DIV      GLB_PEC_CLK_DIV
+#define GLB_PEC_CLK_DIV_POS  (0U)
+#define GLB_PEC_CLK_DIV_LEN  (5U)
+#define GLB_PEC_CLK_DIV_MSK  (((1U << GLB_PEC_CLK_DIV_LEN) - 1) << GLB_PEC_CLK_DIV_POS)
+#define GLB_PEC_CLK_DIV_UMSK (~(((1U << GLB_PEC_CLK_DIV_LEN) - 1) << GLB_PEC_CLK_DIV_POS))
+#define GLB_PEC_CLK_EN       GLB_PEC_CLK_EN
+#define GLB_PEC_CLK_EN_POS   (8U)
+#define GLB_PEC_CLK_EN_LEN   (1U)
+#define GLB_PEC_CLK_EN_MSK   (((1U << GLB_PEC_CLK_EN_LEN) - 1) << GLB_PEC_CLK_EN_POS)
+#define GLB_PEC_CLK_EN_UMSK  (~(((1U << GLB_PEC_CLK_EN_LEN) - 1) << GLB_PEC_CLK_EN_POS))
+#define GLB_PEC_CLK_SEL      GLB_PEC_CLK_SEL
+#define GLB_PEC_CLK_SEL_POS  (9U)
+#define GLB_PEC_CLK_SEL_LEN  (1U)
+#define GLB_PEC_CLK_SEL_MSK  (((1U << GLB_PEC_CLK_SEL_LEN) - 1) << GLB_PEC_CLK_SEL_POS)
+#define GLB_PEC_CLK_SEL_UMSK (~(((1U << GLB_PEC_CLK_SEL_LEN) - 1) << GLB_PEC_CLK_SEL_POS))
+
+/* 0x1C0 : pwm_cfg0 */
+#define GLB_PWM_CFG0_OFFSET      (0x1C0)
+#define GLB_REG_PWM1_IO_SEL      GLB_REG_PWM1_IO_SEL
+#define GLB_REG_PWM1_IO_SEL_POS  (0U)
+#define GLB_REG_PWM1_IO_SEL_LEN  (1U)
+#define GLB_REG_PWM1_IO_SEL_MSK  (((1U << GLB_REG_PWM1_IO_SEL_LEN) - 1) << GLB_REG_PWM1_IO_SEL_POS)
+#define GLB_REG_PWM1_IO_SEL_UMSK (~(((1U << GLB_REG_PWM1_IO_SEL_LEN) - 1) << GLB_REG_PWM1_IO_SEL_POS))
+
+/* 0x1E0 : pdm_cfg0 */
+#define GLB_PDM_CFG0_OFFSET     (0x1E0)
+#define GLB_REG_PDM_IO_SEL      GLB_REG_PDM_IO_SEL
+#define GLB_REG_PDM_IO_SEL_POS  (0U)
+#define GLB_REG_PDM_IO_SEL_LEN  (1U)
+#define GLB_REG_PDM_IO_SEL_MSK  (((1U << GLB_REG_PDM_IO_SEL_LEN) - 1) << GLB_REG_PDM_IO_SEL_POS)
+#define GLB_REG_PDM_IO_SEL_UMSK (~(((1U << GLB_REG_PDM_IO_SEL_LEN) - 1) << GLB_REG_PDM_IO_SEL_POS))
+
+/* 0x1F0 : dbi_cfg0 */
+#define GLB_DBI_CFG0_OFFSET  (0x1F0)
+#define GLB_DBI_CLK_DIV      GLB_DBI_CLK_DIV
+#define GLB_DBI_CLK_DIV_POS  (0U)
+#define GLB_DBI_CLK_DIV_LEN  (5U)
+#define GLB_DBI_CLK_DIV_MSK  (((1U << GLB_DBI_CLK_DIV_LEN) - 1) << GLB_DBI_CLK_DIV_POS)
+#define GLB_DBI_CLK_DIV_UMSK (~(((1U << GLB_DBI_CLK_DIV_LEN) - 1) << GLB_DBI_CLK_DIV_POS))
+#define GLB_DBI_CLK_EN       GLB_DBI_CLK_EN
+#define GLB_DBI_CLK_EN_POS   (8U)
+#define GLB_DBI_CLK_EN_LEN   (1U)
+#define GLB_DBI_CLK_EN_MSK   (((1U << GLB_DBI_CLK_EN_LEN) - 1) << GLB_DBI_CLK_EN_POS)
+#define GLB_DBI_CLK_EN_UMSK  (~(((1U << GLB_DBI_CLK_EN_LEN) - 1) << GLB_DBI_CLK_EN_POS))
+#define GLB_DBI_CLK_SEL      GLB_DBI_CLK_SEL
+#define GLB_DBI_CLK_SEL_POS  (9U)
+#define GLB_DBI_CLK_SEL_LEN  (1U)
+#define GLB_DBI_CLK_SEL_MSK  (((1U << GLB_DBI_CLK_SEL_LEN) - 1) << GLB_DBI_CLK_SEL_POS)
+#define GLB_DBI_CLK_SEL_UMSK (~(((1U << GLB_DBI_CLK_SEL_LEN) - 1) << GLB_DBI_CLK_SEL_POS))
+
+/* 0x250 : dig_clk_cfg0 */
+#define GLB_DIG_CLK_CFG0_OFFSET         (0x250)
+#define GLB_DIG_32K_DIV                 GLB_DIG_32K_DIV
+#define GLB_DIG_32K_DIV_POS             (0U)
+#define GLB_DIG_32K_DIV_LEN             (11U)
+#define GLB_DIG_32K_DIV_MSK             (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
+#define GLB_DIG_32K_DIV_UMSK            (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
+#define GLB_DIG_32K_EN                  GLB_DIG_32K_EN
+#define GLB_DIG_32K_EN_POS              (12U)
+#define GLB_DIG_32K_EN_LEN              (1U)
+#define GLB_DIG_32K_EN_MSK              (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
+#define GLB_DIG_32K_EN_UMSK             (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
+#define GLB_DIG_32K_COMP                GLB_DIG_32K_COMP
+#define GLB_DIG_32K_COMP_POS            (13U)
+#define GLB_DIG_32K_COMP_LEN            (1U)
+#define GLB_DIG_32K_COMP_MSK            (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
+#define GLB_DIG_32K_COMP_UMSK           (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
+#define GLB_DIG_512K_DIV                GLB_DIG_512K_DIV
+#define GLB_DIG_512K_DIV_POS            (16U)
+#define GLB_DIG_512K_DIV_LEN            (7U)
+#define GLB_DIG_512K_DIV_MSK            (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
+#define GLB_DIG_512K_DIV_UMSK           (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
+#define GLB_DIG_512K_EN                 GLB_DIG_512K_EN
+#define GLB_DIG_512K_EN_POS             (24U)
+#define GLB_DIG_512K_EN_LEN             (1U)
+#define GLB_DIG_512K_EN_MSK             (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
+#define GLB_DIG_512K_EN_UMSK            (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
+#define GLB_DIG_512K_COMP               GLB_DIG_512K_COMP
+#define GLB_DIG_512K_COMP_POS           (25U)
+#define GLB_DIG_512K_COMP_LEN           (1U)
+#define GLB_DIG_512K_COMP_MSK           (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
+#define GLB_DIG_512K_COMP_UMSK          (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
+#define GLB_DIG_CLK_SRC_SEL             GLB_DIG_CLK_SRC_SEL
+#define GLB_DIG_CLK_SRC_SEL_POS         (28U)
+#define GLB_DIG_CLK_SRC_SEL_LEN         (2U)
+#define GLB_DIG_CLK_SRC_SEL_MSK         (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
+#define GLB_DIG_CLK_SRC_SEL_UMSK        (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
+#define GLB_REG_EN_PLATFORM_WAKEUP      GLB_REG_EN_PLATFORM_WAKEUP
+#define GLB_REG_EN_PLATFORM_WAKEUP_POS  (31U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_LEN  (1U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_MSK  (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)
+#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS))
+
+/* 0x254 : dig_clk_cfg1 */
+#define GLB_DIG_CLK_CFG1_OFFSET          (0x254)
+#define GLB_REG_ISP_MUXPLL_80M_SEL       GLB_REG_ISP_MUXPLL_80M_SEL
+#define GLB_REG_ISP_MUXPLL_80M_SEL_POS   (0U)
+#define GLB_REG_ISP_MUXPLL_80M_SEL_LEN   (2U)
+#define GLB_REG_ISP_MUXPLL_80M_SEL_MSK   (((1U << GLB_REG_ISP_MUXPLL_80M_SEL_LEN) - 1) << GLB_REG_ISP_MUXPLL_80M_SEL_POS)
+#define GLB_REG_ISP_MUXPLL_80M_SEL_UMSK  (~(((1U << GLB_REG_ISP_MUXPLL_80M_SEL_LEN) - 1) << GLB_REG_ISP_MUXPLL_80M_SEL_POS))
+#define GLB_REG_TOP_MUXPLL_80M_SEL       GLB_REG_TOP_MUXPLL_80M_SEL
+#define GLB_REG_TOP_MUXPLL_80M_SEL_POS   (8U)
+#define GLB_REG_TOP_MUXPLL_80M_SEL_LEN   (2U)
+#define GLB_REG_TOP_MUXPLL_80M_SEL_MSK   (((1U << GLB_REG_TOP_MUXPLL_80M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_80M_SEL_POS)
+#define GLB_REG_TOP_MUXPLL_80M_SEL_UMSK  (~(((1U << GLB_REG_TOP_MUXPLL_80M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_80M_SEL_POS))
+#define GLB_REG_TOP_MUXPLL_160M_SEL      GLB_REG_TOP_MUXPLL_160M_SEL
+#define GLB_REG_TOP_MUXPLL_160M_SEL_POS  (10U)
+#define GLB_REG_TOP_MUXPLL_160M_SEL_LEN  (2U)
+#define GLB_REG_TOP_MUXPLL_160M_SEL_MSK  (((1U << GLB_REG_TOP_MUXPLL_160M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_160M_SEL_POS)
+#define GLB_REG_TOP_MUXPLL_160M_SEL_UMSK (~(((1U << GLB_REG_TOP_MUXPLL_160M_SEL_LEN) - 1) << GLB_REG_TOP_MUXPLL_160M_SEL_POS))
+
+/* 0x258 : dig_clk_cfg2 */
+#define GLB_DIG_CLK_CFG2_OFFSET     (0x258)
+#define GLB_CHIP_CLK_OUT_0_SEL      GLB_CHIP_CLK_OUT_0_SEL
+#define GLB_CHIP_CLK_OUT_0_SEL_POS  (0U)
+#define GLB_CHIP_CLK_OUT_0_SEL_LEN  (2U)
+#define GLB_CHIP_CLK_OUT_0_SEL_MSK  (((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS)
+#define GLB_CHIP_CLK_OUT_0_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS))
+#define GLB_CHIP_CLK_OUT_1_SEL      GLB_CHIP_CLK_OUT_1_SEL
+#define GLB_CHIP_CLK_OUT_1_SEL_POS  (2U)
+#define GLB_CHIP_CLK_OUT_1_SEL_LEN  (2U)
+#define GLB_CHIP_CLK_OUT_1_SEL_MSK  (((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS)
+#define GLB_CHIP_CLK_OUT_1_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS))
+#define GLB_CHIP_CLK_OUT_2_SEL      GLB_CHIP_CLK_OUT_2_SEL
+#define GLB_CHIP_CLK_OUT_2_SEL_POS  (4U)
+#define GLB_CHIP_CLK_OUT_2_SEL_LEN  (2U)
+#define GLB_CHIP_CLK_OUT_2_SEL_MSK  (((1U << GLB_CHIP_CLK_OUT_2_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_2_SEL_POS)
+#define GLB_CHIP_CLK_OUT_2_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_2_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_2_SEL_POS))
+#define GLB_CHIP_CLK_OUT_3_SEL      GLB_CHIP_CLK_OUT_3_SEL
+#define GLB_CHIP_CLK_OUT_3_SEL_POS  (6U)
+#define GLB_CHIP_CLK_OUT_3_SEL_LEN  (2U)
+#define GLB_CHIP_CLK_OUT_3_SEL_MSK  (((1U << GLB_CHIP_CLK_OUT_3_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_3_SEL_POS)
+#define GLB_CHIP_CLK_OUT_3_SEL_UMSK (~(((1U << GLB_CHIP_CLK_OUT_3_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_3_SEL_POS))
+#define GLB_CHIP_CLK_OUT_0_EN       GLB_CHIP_CLK_OUT_0_EN
+#define GLB_CHIP_CLK_OUT_0_EN_POS   (8U)
+#define GLB_CHIP_CLK_OUT_0_EN_LEN   (1U)
+#define GLB_CHIP_CLK_OUT_0_EN_MSK   (((1U << GLB_CHIP_CLK_OUT_0_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_0_EN_POS)
+#define GLB_CHIP_CLK_OUT_0_EN_UMSK  (~(((1U << GLB_CHIP_CLK_OUT_0_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_0_EN_POS))
+#define GLB_CHIP_CLK_OUT_1_EN       GLB_CHIP_CLK_OUT_1_EN
+#define GLB_CHIP_CLK_OUT_1_EN_POS   (9U)
+#define GLB_CHIP_CLK_OUT_1_EN_LEN   (1U)
+#define GLB_CHIP_CLK_OUT_1_EN_MSK   (((1U << GLB_CHIP_CLK_OUT_1_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_1_EN_POS)
+#define GLB_CHIP_CLK_OUT_1_EN_UMSK  (~(((1U << GLB_CHIP_CLK_OUT_1_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_1_EN_POS))
+#define GLB_CHIP_CLK_OUT_2_EN       GLB_CHIP_CLK_OUT_2_EN
+#define GLB_CHIP_CLK_OUT_2_EN_POS   (10U)
+#define GLB_CHIP_CLK_OUT_2_EN_LEN   (1U)
+#define GLB_CHIP_CLK_OUT_2_EN_MSK   (((1U << GLB_CHIP_CLK_OUT_2_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_2_EN_POS)
+#define GLB_CHIP_CLK_OUT_2_EN_UMSK  (~(((1U << GLB_CHIP_CLK_OUT_2_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_2_EN_POS))
+#define GLB_CHIP_CLK_OUT_3_EN       GLB_CHIP_CLK_OUT_3_EN
+#define GLB_CHIP_CLK_OUT_3_EN_POS   (11U)
+#define GLB_CHIP_CLK_OUT_3_EN_LEN   (1U)
+#define GLB_CHIP_CLK_OUT_3_EN_MSK   (((1U << GLB_CHIP_CLK_OUT_3_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_3_EN_POS)
+#define GLB_CHIP_CLK_OUT_3_EN_UMSK  (~(((1U << GLB_CHIP_CLK_OUT_3_EN_LEN) - 1) << GLB_CHIP_CLK_OUT_3_EN_POS))
+#define GLB_GPIO_TMR_CLK_SEL        GLB_GPIO_TMR_CLK_SEL
+#define GLB_GPIO_TMR_CLK_SEL_POS    (12U)
+#define GLB_GPIO_TMR_CLK_SEL_LEN    (2U)
+#define GLB_GPIO_TMR_CLK_SEL_MSK    (((1U << GLB_GPIO_TMR_CLK_SEL_LEN) - 1) << GLB_GPIO_TMR_CLK_SEL_POS)
+#define GLB_GPIO_TMR_CLK_SEL_UMSK   (~(((1U << GLB_GPIO_TMR_CLK_SEL_LEN) - 1) << GLB_GPIO_TMR_CLK_SEL_POS))
+
+/* 0x25C : dig_clk_cfg3 */
+#define GLB_DIG_CLK_CFG3_OFFSET (0x25C)
+
+/* 0x260 : rf_cfg0 */
+#define GLB_RF_CFG0_OFFSET (0x260)
+
+/* 0x2E0 : dbg_cfg0 */
+#define GLB_DBG_CFG0_OFFSET      (0x2E0)
+#define GLB_REG_DBG_LL_CTRL      GLB_REG_DBG_LL_CTRL
+#define GLB_REG_DBG_LL_CTRL_POS  (0U)
+#define GLB_REG_DBG_LL_CTRL_LEN  (30U)
+#define GLB_REG_DBG_LL_CTRL_MSK  (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
+#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
+#define GLB_REG_DBG_LL_SEL       GLB_REG_DBG_LL_SEL
+#define GLB_REG_DBG_LL_SEL_POS   (30U)
+#define GLB_REG_DBG_LL_SEL_LEN   (2U)
+#define GLB_REG_DBG_LL_SEL_MSK   (((1U << GLB_REG_DBG_LL_SEL_LEN) - 1) << GLB_REG_DBG_LL_SEL_POS)
+#define GLB_REG_DBG_LL_SEL_UMSK  (~(((1U << GLB_REG_DBG_LL_SEL_LEN) - 1) << GLB_REG_DBG_LL_SEL_POS))
+
+/* 0x2E4 : dbg_cfg1 */
+#define GLB_DBG_CFG1_OFFSET      (0x2E4)
+#define GLB_REG_DBG_LH_CTRL      GLB_REG_DBG_LH_CTRL
+#define GLB_REG_DBG_LH_CTRL_POS  (0U)
+#define GLB_REG_DBG_LH_CTRL_LEN  (30U)
+#define GLB_REG_DBG_LH_CTRL_MSK  (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
+#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
+#define GLB_REG_DBG_LH_SEL       GLB_REG_DBG_LH_SEL
+#define GLB_REG_DBG_LH_SEL_POS   (30U)
+#define GLB_REG_DBG_LH_SEL_LEN   (2U)
+#define GLB_REG_DBG_LH_SEL_MSK   (((1U << GLB_REG_DBG_LH_SEL_LEN) - 1) << GLB_REG_DBG_LH_SEL_POS)
+#define GLB_REG_DBG_LH_SEL_UMSK  (~(((1U << GLB_REG_DBG_LH_SEL_LEN) - 1) << GLB_REG_DBG_LH_SEL_POS))
+
+/* 0x2E8 : dbg_cfg2 */
+#define GLB_DBG_CFG2_OFFSET      (0x2E8)
+#define GLB_REG_DBG_HL_CTRL      GLB_REG_DBG_HL_CTRL
+#define GLB_REG_DBG_HL_CTRL_POS  (0U)
+#define GLB_REG_DBG_HL_CTRL_LEN  (30U)
+#define GLB_REG_DBG_HL_CTRL_MSK  (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
+#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
+#define GLB_REG_DBG_HL_SEL       GLB_REG_DBG_HL_SEL
+#define GLB_REG_DBG_HL_SEL_POS   (30U)
+#define GLB_REG_DBG_HL_SEL_LEN   (2U)
+#define GLB_REG_DBG_HL_SEL_MSK   (((1U << GLB_REG_DBG_HL_SEL_LEN) - 1) << GLB_REG_DBG_HL_SEL_POS)
+#define GLB_REG_DBG_HL_SEL_UMSK  (~(((1U << GLB_REG_DBG_HL_SEL_LEN) - 1) << GLB_REG_DBG_HL_SEL_POS))
+
+/* 0x2EC : dbg_cfg3 */
+#define GLB_DBG_CFG3_OFFSET      (0x2EC)
+#define GLB_REG_DBG_HH_CTRL      GLB_REG_DBG_HH_CTRL
+#define GLB_REG_DBG_HH_CTRL_POS  (0U)
+#define GLB_REG_DBG_HH_CTRL_LEN  (30U)
+#define GLB_REG_DBG_HH_CTRL_MSK  (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
+#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
+#define GLB_REG_DBG_HH_SEL       GLB_REG_DBG_HH_SEL
+#define GLB_REG_DBG_HH_SEL_POS   (30U)
+#define GLB_REG_DBG_HH_SEL_LEN   (2U)
+#define GLB_REG_DBG_HH_SEL_MSK   (((1U << GLB_REG_DBG_HH_SEL_LEN) - 1) << GLB_REG_DBG_HH_SEL_POS)
+#define GLB_REG_DBG_HH_SEL_UMSK  (~(((1U << GLB_REG_DBG_HH_SEL_LEN) - 1) << GLB_REG_DBG_HH_SEL_POS))
+
+/* 0x2F0 : dbg_cfg4 */
+#define GLB_DBG_CFG4_OFFSET (0x2F0)
+#define GLB_DEBUG_OE        GLB_DEBUG_OE
+#define GLB_DEBUG_OE_POS    (0U)
+#define GLB_DEBUG_OE_LEN    (1U)
+#define GLB_DEBUG_OE_MSK    (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
+#define GLB_DEBUG_OE_UMSK   (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
+#define GLB_DEBUG_I         GLB_DEBUG_I
+#define GLB_DEBUG_I_POS     (1U)
+#define GLB_DEBUG_I_LEN     (31U)
+#define GLB_DEBUG_I_MSK     (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
+#define GLB_DEBUG_I_UMSK    (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
+
+/* 0x300 : mbist_cfg0 */
+#define GLB_MBIST_CFG0_OFFSET               (0x300)
+#define GLB_OCRAM_MBIST_MODE                GLB_OCRAM_MBIST_MODE
+#define GLB_OCRAM_MBIST_MODE_POS            (0U)
+#define GLB_OCRAM_MBIST_MODE_LEN            (4U)
+#define GLB_OCRAM_MBIST_MODE_MSK            (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
+#define GLB_OCRAM_MBIST_MODE_UMSK           (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
+#define GLB_WRAM_MBIST_MODE                 GLB_WRAM_MBIST_MODE
+#define GLB_WRAM_MBIST_MODE_POS             (4U)
+#define GLB_WRAM_MBIST_MODE_LEN             (2U)
+#define GLB_WRAM_MBIST_MODE_MSK             (((1U << GLB_WRAM_MBIST_MODE_LEN) - 1) << GLB_WRAM_MBIST_MODE_POS)
+#define GLB_WRAM_MBIST_MODE_UMSK            (~(((1U << GLB_WRAM_MBIST_MODE_LEN) - 1) << GLB_WRAM_MBIST_MODE_POS))
+#define GLB_REG_WRAM_OCRAM_MBIST_RST_N      GLB_REG_WRAM_OCRAM_MBIST_RST_N
+#define GLB_REG_WRAM_OCRAM_MBIST_RST_N_POS  (8U)
+#define GLB_REG_WRAM_OCRAM_MBIST_RST_N_LEN  (1U)
+#define GLB_REG_WRAM_OCRAM_MBIST_RST_N_MSK  (((1U << GLB_REG_WRAM_OCRAM_MBIST_RST_N_LEN) - 1) << GLB_REG_WRAM_OCRAM_MBIST_RST_N_POS)
+#define GLB_REG_WRAM_OCRAM_MBIST_RST_N_UMSK (~(((1U << GLB_REG_WRAM_OCRAM_MBIST_RST_N_LEN) - 1) << GLB_REG_WRAM_OCRAM_MBIST_RST_N_POS))
+#define GLB_OCRAM_MBIST_DONE                GLB_OCRAM_MBIST_DONE
+#define GLB_OCRAM_MBIST_DONE_POS            (16U)
+#define GLB_OCRAM_MBIST_DONE_LEN            (4U)
+#define GLB_OCRAM_MBIST_DONE_MSK            (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
+#define GLB_OCRAM_MBIST_DONE_UMSK           (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
+#define GLB_WRAM_MBIST_DONE                 GLB_WRAM_MBIST_DONE
+#define GLB_WRAM_MBIST_DONE_POS             (20U)
+#define GLB_WRAM_MBIST_DONE_LEN             (2U)
+#define GLB_WRAM_MBIST_DONE_MSK             (((1U << GLB_WRAM_MBIST_DONE_LEN) - 1) << GLB_WRAM_MBIST_DONE_POS)
+#define GLB_WRAM_MBIST_DONE_UMSK            (~(((1U << GLB_WRAM_MBIST_DONE_LEN) - 1) << GLB_WRAM_MBIST_DONE_POS))
+#define GLB_OCRAM_MBIST_FAIL                GLB_OCRAM_MBIST_FAIL
+#define GLB_OCRAM_MBIST_FAIL_POS            (24U)
+#define GLB_OCRAM_MBIST_FAIL_LEN            (4U)
+#define GLB_OCRAM_MBIST_FAIL_MSK            (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
+#define GLB_OCRAM_MBIST_FAIL_UMSK           (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
+#define GLB_WRAM_MBIST_FAIL                 GLB_WRAM_MBIST_FAIL
+#define GLB_WRAM_MBIST_FAIL_POS             (28U)
+#define GLB_WRAM_MBIST_FAIL_LEN             (2U)
+#define GLB_WRAM_MBIST_FAIL_MSK             (((1U << GLB_WRAM_MBIST_FAIL_LEN) - 1) << GLB_WRAM_MBIST_FAIL_POS)
+#define GLB_WRAM_MBIST_FAIL_UMSK            (~(((1U << GLB_WRAM_MBIST_FAIL_LEN) - 1) << GLB_WRAM_MBIST_FAIL_POS))
+
+/* 0x304 : mbist_cfg1 */
+#define GLB_MBIST_CFG1_OFFSET        (0x304)
+#define GLB_TOP_MBIST_MODE           GLB_TOP_MBIST_MODE
+#define GLB_TOP_MBIST_MODE_POS       (0U)
+#define GLB_TOP_MBIST_MODE_LEN       (1U)
+#define GLB_TOP_MBIST_MODE_MSK       (((1U << GLB_TOP_MBIST_MODE_LEN) - 1) << GLB_TOP_MBIST_MODE_POS)
+#define GLB_TOP_MBIST_MODE_UMSK      (~(((1U << GLB_TOP_MBIST_MODE_LEN) - 1) << GLB_TOP_MBIST_MODE_POS))
+#define GLB_REG_TOP_MBIST_RST_N      GLB_REG_TOP_MBIST_RST_N
+#define GLB_REG_TOP_MBIST_RST_N_POS  (8U)
+#define GLB_REG_TOP_MBIST_RST_N_LEN  (1U)
+#define GLB_REG_TOP_MBIST_RST_N_MSK  (((1U << GLB_REG_TOP_MBIST_RST_N_LEN) - 1) << GLB_REG_TOP_MBIST_RST_N_POS)
+#define GLB_REG_TOP_MBIST_RST_N_UMSK (~(((1U << GLB_REG_TOP_MBIST_RST_N_LEN) - 1) << GLB_REG_TOP_MBIST_RST_N_POS))
+#define GLB_EF_MBIST_DONE            GLB_EF_MBIST_DONE
+#define GLB_EF_MBIST_DONE_POS        (16U)
+#define GLB_EF_MBIST_DONE_LEN        (2U)
+#define GLB_EF_MBIST_DONE_MSK        (((1U << GLB_EF_MBIST_DONE_LEN) - 1) << GLB_EF_MBIST_DONE_POS)
+#define GLB_EF_MBIST_DONE_UMSK       (~(((1U << GLB_EF_MBIST_DONE_LEN) - 1) << GLB_EF_MBIST_DONE_POS))
+#define GLB_USB_MBIST_DONE           GLB_USB_MBIST_DONE
+#define GLB_USB_MBIST_DONE_POS       (18U)
+#define GLB_USB_MBIST_DONE_LEN       (1U)
+#define GLB_USB_MBIST_DONE_MSK       (((1U << GLB_USB_MBIST_DONE_LEN) - 1) << GLB_USB_MBIST_DONE_POS)
+#define GLB_USB_MBIST_DONE_UMSK      (~(((1U << GLB_USB_MBIST_DONE_LEN) - 1) << GLB_USB_MBIST_DONE_POS))
+#define GLB_SDH_MBIST_DONE           GLB_SDH_MBIST_DONE
+#define GLB_SDH_MBIST_DONE_POS       (19U)
+#define GLB_SDH_MBIST_DONE_LEN       (1U)
+#define GLB_SDH_MBIST_DONE_MSK       (((1U << GLB_SDH_MBIST_DONE_LEN) - 1) << GLB_SDH_MBIST_DONE_POS)
+#define GLB_SDH_MBIST_DONE_UMSK      (~(((1U << GLB_SDH_MBIST_DONE_LEN) - 1) << GLB_SDH_MBIST_DONE_POS))
+#define GLB_SEC_MBIST_DONE           GLB_SEC_MBIST_DONE
+#define GLB_SEC_MBIST_DONE_POS       (20U)
+#define GLB_SEC_MBIST_DONE_LEN       (1U)
+#define GLB_SEC_MBIST_DONE_MSK       (((1U << GLB_SEC_MBIST_DONE_LEN) - 1) << GLB_SEC_MBIST_DONE_POS)
+#define GLB_SEC_MBIST_DONE_UMSK      (~(((1U << GLB_SEC_MBIST_DONE_LEN) - 1) << GLB_SEC_MBIST_DONE_POS))
+#define GLB_SF_MBIST_DONE            GLB_SF_MBIST_DONE
+#define GLB_SF_MBIST_DONE_POS        (21U)
+#define GLB_SF_MBIST_DONE_LEN        (1U)
+#define GLB_SF_MBIST_DONE_MSK        (((1U << GLB_SF_MBIST_DONE_LEN) - 1) << GLB_SF_MBIST_DONE_POS)
+#define GLB_SF_MBIST_DONE_UMSK       (~(((1U << GLB_SF_MBIST_DONE_LEN) - 1) << GLB_SF_MBIST_DONE_POS))
+#define GLB_EMAC_MBIST_DONE          GLB_EMAC_MBIST_DONE
+#define GLB_EMAC_MBIST_DONE_POS      (22U)
+#define GLB_EMAC_MBIST_DONE_LEN      (1U)
+#define GLB_EMAC_MBIST_DONE_MSK      (((1U << GLB_EMAC_MBIST_DONE_LEN) - 1) << GLB_EMAC_MBIST_DONE_POS)
+#define GLB_EMAC_MBIST_DONE_UMSK     (~(((1U << GLB_EMAC_MBIST_DONE_LEN) - 1) << GLB_EMAC_MBIST_DONE_POS))
+#define GLB_EF_MBIST_FAIL            GLB_EF_MBIST_FAIL
+#define GLB_EF_MBIST_FAIL_POS        (24U)
+#define GLB_EF_MBIST_FAIL_LEN        (2U)
+#define GLB_EF_MBIST_FAIL_MSK        (((1U << GLB_EF_MBIST_FAIL_LEN) - 1) << GLB_EF_MBIST_FAIL_POS)
+#define GLB_EF_MBIST_FAIL_UMSK       (~(((1U << GLB_EF_MBIST_FAIL_LEN) - 1) << GLB_EF_MBIST_FAIL_POS))
+#define GLB_USB_MBIST_FAIL           GLB_USB_MBIST_FAIL
+#define GLB_USB_MBIST_FAIL_POS       (26U)
+#define GLB_USB_MBIST_FAIL_LEN       (1U)
+#define GLB_USB_MBIST_FAIL_MSK       (((1U << GLB_USB_MBIST_FAIL_LEN) - 1) << GLB_USB_MBIST_FAIL_POS)
+#define GLB_USB_MBIST_FAIL_UMSK      (~(((1U << GLB_USB_MBIST_FAIL_LEN) - 1) << GLB_USB_MBIST_FAIL_POS))
+#define GLB_SDH_MBIST_FAIL           GLB_SDH_MBIST_FAIL
+#define GLB_SDH_MBIST_FAIL_POS       (27U)
+#define GLB_SDH_MBIST_FAIL_LEN       (1U)
+#define GLB_SDH_MBIST_FAIL_MSK       (((1U << GLB_SDH_MBIST_FAIL_LEN) - 1) << GLB_SDH_MBIST_FAIL_POS)
+#define GLB_SDH_MBIST_FAIL_UMSK      (~(((1U << GLB_SDH_MBIST_FAIL_LEN) - 1) << GLB_SDH_MBIST_FAIL_POS))
+#define GLB_SEC_MBIST_FAIL           GLB_SEC_MBIST_FAIL
+#define GLB_SEC_MBIST_FAIL_POS       (28U)
+#define GLB_SEC_MBIST_FAIL_LEN       (1U)
+#define GLB_SEC_MBIST_FAIL_MSK       (((1U << GLB_SEC_MBIST_FAIL_LEN) - 1) << GLB_SEC_MBIST_FAIL_POS)
+#define GLB_SEC_MBIST_FAIL_UMSK      (~(((1U << GLB_SEC_MBIST_FAIL_LEN) - 1) << GLB_SEC_MBIST_FAIL_POS))
+#define GLB_SF_MBIST_FAIL            GLB_SF_MBIST_FAIL
+#define GLB_SF_MBIST_FAIL_POS        (29U)
+#define GLB_SF_MBIST_FAIL_LEN        (1U)
+#define GLB_SF_MBIST_FAIL_MSK        (((1U << GLB_SF_MBIST_FAIL_LEN) - 1) << GLB_SF_MBIST_FAIL_POS)
+#define GLB_SF_MBIST_FAIL_UMSK       (~(((1U << GLB_SF_MBIST_FAIL_LEN) - 1) << GLB_SF_MBIST_FAIL_POS))
+#define GLB_EMAC_MBIST_FAIL          GLB_EMAC_MBIST_FAIL
+#define GLB_EMAC_MBIST_FAIL_POS      (30U)
+#define GLB_EMAC_MBIST_FAIL_LEN      (1U)
+#define GLB_EMAC_MBIST_FAIL_MSK      (((1U << GLB_EMAC_MBIST_FAIL_LEN) - 1) << GLB_EMAC_MBIST_FAIL_POS)
+#define GLB_EMAC_MBIST_FAIL_UMSK     (~(((1U << GLB_EMAC_MBIST_FAIL_LEN) - 1) << GLB_EMAC_MBIST_FAIL_POS))
+
+/* 0x320 : bmx_cfg0 */
+#define GLB_BMX_CFG0_OFFSET          (0x320)
+#define GLB_REG_BMX_TIMEOUT_EN       GLB_REG_BMX_TIMEOUT_EN
+#define GLB_REG_BMX_TIMEOUT_EN_POS   (0U)
+#define GLB_REG_BMX_TIMEOUT_EN_LEN   (4U)
+#define GLB_REG_BMX_TIMEOUT_EN_MSK   (((1U << GLB_REG_BMX_TIMEOUT_EN_LEN) - 1) << GLB_REG_BMX_TIMEOUT_EN_POS)
+#define GLB_REG_BMX_TIMEOUT_EN_UMSK  (~(((1U << GLB_REG_BMX_TIMEOUT_EN_LEN) - 1) << GLB_REG_BMX_TIMEOUT_EN_POS))
+#define GLB_REG_BMX_ARB_MODE         GLB_REG_BMX_ARB_MODE
+#define GLB_REG_BMX_ARB_MODE_POS     (5U)
+#define GLB_REG_BMX_ARB_MODE_LEN     (1U)
+#define GLB_REG_BMX_ARB_MODE_MSK     (((1U << GLB_REG_BMX_ARB_MODE_LEN) - 1) << GLB_REG_BMX_ARB_MODE_POS)
+#define GLB_REG_BMX_ARB_MODE_UMSK    (~(((1U << GLB_REG_BMX_ARB_MODE_LEN) - 1) << GLB_REG_BMX_ARB_MODE_POS))
+#define GLB_REG_BMX_TIMEOUT_CLR      GLB_REG_BMX_TIMEOUT_CLR
+#define GLB_REG_BMX_TIMEOUT_CLR_POS  (6U)
+#define GLB_REG_BMX_TIMEOUT_CLR_LEN  (1U)
+#define GLB_REG_BMX_TIMEOUT_CLR_MSK  (((1U << GLB_REG_BMX_TIMEOUT_CLR_LEN) - 1) << GLB_REG_BMX_TIMEOUT_CLR_POS)
+#define GLB_REG_BMX_TIMEOUT_CLR_UMSK (~(((1U << GLB_REG_BMX_TIMEOUT_CLR_LEN) - 1) << GLB_REG_BMX_TIMEOUT_CLR_POS))
+#define GLB_STS_BMX_TIMEOUT_STS      GLB_STS_BMX_TIMEOUT_STS
+#define GLB_STS_BMX_TIMEOUT_STS_POS  (11U)
+#define GLB_STS_BMX_TIMEOUT_STS_LEN  (4U)
+#define GLB_STS_BMX_TIMEOUT_STS_MSK  (((1U << GLB_STS_BMX_TIMEOUT_STS_LEN) - 1) << GLB_STS_BMX_TIMEOUT_STS_POS)
+#define GLB_STS_BMX_TIMEOUT_STS_UMSK (~(((1U << GLB_STS_BMX_TIMEOUT_STS_LEN) - 1) << GLB_STS_BMX_TIMEOUT_STS_POS))
+#define GLB_PDS_APB_CFG              GLB_PDS_APB_CFG
+#define GLB_PDS_APB_CFG_POS          (16U)
+#define GLB_PDS_APB_CFG_LEN          (8U)
+#define GLB_PDS_APB_CFG_MSK          (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
+#define GLB_PDS_APB_CFG_UMSK         (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
+#define GLB_HBN_APB_CFG              GLB_HBN_APB_CFG
+#define GLB_HBN_APB_CFG_POS          (24U)
+#define GLB_HBN_APB_CFG_LEN          (8U)
+#define GLB_HBN_APB_CFG_MSK          (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
+#define GLB_HBN_APB_CFG_UMSK         (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
+
+/* 0x324 : bmx_cfg1 */
+#define GLB_BMX_CFG1_OFFSET          (0x324)
+#define GLB_REG_BMX_BERR_INT_EN      GLB_REG_BMX_BERR_INT_EN
+#define GLB_REG_BMX_BERR_INT_EN_POS  (0U)
+#define GLB_REG_BMX_BERR_INT_EN_LEN  (1U)
+#define GLB_REG_BMX_BERR_INT_EN_MSK  (((1U << GLB_REG_BMX_BERR_INT_EN_LEN) - 1) << GLB_REG_BMX_BERR_INT_EN_POS)
+#define GLB_REG_BMX_BERR_INT_EN_UMSK (~(((1U << GLB_REG_BMX_BERR_INT_EN_LEN) - 1) << GLB_REG_BMX_BERR_INT_EN_POS))
+#define GLB_REG_MCU_BERR_INT_EN      GLB_REG_MCU_BERR_INT_EN
+#define GLB_REG_MCU_BERR_INT_EN_POS  (1U)
+#define GLB_REG_MCU_BERR_INT_EN_LEN  (1U)
+#define GLB_REG_MCU_BERR_INT_EN_MSK  (((1U << GLB_REG_MCU_BERR_INT_EN_LEN) - 1) << GLB_REG_MCU_BERR_INT_EN_POS)
+#define GLB_REG_MCU_BERR_INT_EN_UMSK (~(((1U << GLB_REG_MCU_BERR_INT_EN_LEN) - 1) << GLB_REG_MCU_BERR_INT_EN_POS))
+#define GLB_REG_BMX_QOS_CPU          GLB_REG_BMX_QOS_CPU
+#define GLB_REG_BMX_QOS_CPU_POS      (16U)
+#define GLB_REG_BMX_QOS_CPU_LEN      (1U)
+#define GLB_REG_BMX_QOS_CPU_MSK      (((1U << GLB_REG_BMX_QOS_CPU_LEN) - 1) << GLB_REG_BMX_QOS_CPU_POS)
+#define GLB_REG_BMX_QOS_CPU_UMSK     (~(((1U << GLB_REG_BMX_QOS_CPU_LEN) - 1) << GLB_REG_BMX_QOS_CPU_POS))
+#define GLB_REG_BMX_QOS_SDU          GLB_REG_BMX_QOS_SDU
+#define GLB_REG_BMX_QOS_SDU_POS      (17U)
+#define GLB_REG_BMX_QOS_SDU_LEN      (1U)
+#define GLB_REG_BMX_QOS_SDU_MSK      (((1U << GLB_REG_BMX_QOS_SDU_LEN) - 1) << GLB_REG_BMX_QOS_SDU_POS)
+#define GLB_REG_BMX_QOS_SDU_UMSK     (~(((1U << GLB_REG_BMX_QOS_SDU_LEN) - 1) << GLB_REG_BMX_QOS_SDU_POS))
+#define GLB_REG_BMX_QOS_SEC0         GLB_REG_BMX_QOS_SEC0
+#define GLB_REG_BMX_QOS_SEC0_POS     (18U)
+#define GLB_REG_BMX_QOS_SEC0_LEN     (1U)
+#define GLB_REG_BMX_QOS_SEC0_MSK     (((1U << GLB_REG_BMX_QOS_SEC0_LEN) - 1) << GLB_REG_BMX_QOS_SEC0_POS)
+#define GLB_REG_BMX_QOS_SEC0_UMSK    (~(((1U << GLB_REG_BMX_QOS_SEC0_LEN) - 1) << GLB_REG_BMX_QOS_SEC0_POS))
+#define GLB_REG_BMX_QOS_SEC1         GLB_REG_BMX_QOS_SEC1
+#define GLB_REG_BMX_QOS_SEC1_POS     (19U)
+#define GLB_REG_BMX_QOS_SEC1_LEN     (1U)
+#define GLB_REG_BMX_QOS_SEC1_MSK     (((1U << GLB_REG_BMX_QOS_SEC1_LEN) - 1) << GLB_REG_BMX_QOS_SEC1_POS)
+#define GLB_REG_BMX_QOS_SEC1_UMSK    (~(((1U << GLB_REG_BMX_QOS_SEC1_LEN) - 1) << GLB_REG_BMX_QOS_SEC1_POS))
+#define GLB_REG_BMX_QOS_SEC2         GLB_REG_BMX_QOS_SEC2
+#define GLB_REG_BMX_QOS_SEC2_POS     (20U)
+#define GLB_REG_BMX_QOS_SEC2_LEN     (1U)
+#define GLB_REG_BMX_QOS_SEC2_MSK     (((1U << GLB_REG_BMX_QOS_SEC2_LEN) - 1) << GLB_REG_BMX_QOS_SEC2_POS)
+#define GLB_REG_BMX_QOS_SEC2_UMSK    (~(((1U << GLB_REG_BMX_QOS_SEC2_LEN) - 1) << GLB_REG_BMX_QOS_SEC2_POS))
+#define GLB_REG_BMX_QOS_DMA          GLB_REG_BMX_QOS_DMA
+#define GLB_REG_BMX_QOS_DMA_POS      (21U)
+#define GLB_REG_BMX_QOS_DMA_LEN      (1U)
+#define GLB_REG_BMX_QOS_DMA_MSK      (((1U << GLB_REG_BMX_QOS_DMA_LEN) - 1) << GLB_REG_BMX_QOS_DMA_POS)
+#define GLB_REG_BMX_QOS_DMA_UMSK     (~(((1U << GLB_REG_BMX_QOS_DMA_LEN) - 1) << GLB_REG_BMX_QOS_DMA_POS))
+#define GLB_REG_BMX_QOS_CCI          GLB_REG_BMX_QOS_CCI
+#define GLB_REG_BMX_QOS_CCI_POS      (22U)
+#define GLB_REG_BMX_QOS_CCI_LEN      (1U)
+#define GLB_REG_BMX_QOS_CCI_MSK      (((1U << GLB_REG_BMX_QOS_CCI_LEN) - 1) << GLB_REG_BMX_QOS_CCI_POS)
+#define GLB_REG_BMX_QOS_CCI_UMSK     (~(((1U << GLB_REG_BMX_QOS_CCI_LEN) - 1) << GLB_REG_BMX_QOS_CCI_POS))
+#define GLB_REG_BMX_QOS_PLDMA        GLB_REG_BMX_QOS_PLDMA
+#define GLB_REG_BMX_QOS_PLDMA_POS    (23U)
+#define GLB_REG_BMX_QOS_PLDMA_LEN    (1U)
+#define GLB_REG_BMX_QOS_PLDMA_MSK    (((1U << GLB_REG_BMX_QOS_PLDMA_LEN) - 1) << GLB_REG_BMX_QOS_PLDMA_POS)
+#define GLB_REG_BMX_QOS_PLDMA_UMSK   (~(((1U << GLB_REG_BMX_QOS_PLDMA_LEN) - 1) << GLB_REG_BMX_QOS_PLDMA_POS))
+#define GLB_REG_BMX_QOS_BLEM         GLB_REG_BMX_QOS_BLEM
+#define GLB_REG_BMX_QOS_BLEM_POS     (24U)
+#define GLB_REG_BMX_QOS_BLEM_LEN     (1U)
+#define GLB_REG_BMX_QOS_BLEM_MSK     (((1U << GLB_REG_BMX_QOS_BLEM_LEN) - 1) << GLB_REG_BMX_QOS_BLEM_POS)
+#define GLB_REG_BMX_QOS_BLEM_UMSK    (~(((1U << GLB_REG_BMX_QOS_BLEM_LEN) - 1) << GLB_REG_BMX_QOS_BLEM_POS))
+#define GLB_REG_BMX_QOS_EMACA        GLB_REG_BMX_QOS_EMACA
+#define GLB_REG_BMX_QOS_EMACA_POS    (25U)
+#define GLB_REG_BMX_QOS_EMACA_LEN    (1U)
+#define GLB_REG_BMX_QOS_EMACA_MSK    (((1U << GLB_REG_BMX_QOS_EMACA_LEN) - 1) << GLB_REG_BMX_QOS_EMACA_POS)
+#define GLB_REG_BMX_QOS_EMACA_UMSK   (~(((1U << GLB_REG_BMX_QOS_EMACA_LEN) - 1) << GLB_REG_BMX_QOS_EMACA_POS))
+#define GLB_REG_BMX_QOS_SDHM         GLB_REG_BMX_QOS_SDHM
+#define GLB_REG_BMX_QOS_SDHM_POS     (27U)
+#define GLB_REG_BMX_QOS_SDHM_LEN     (1U)
+#define GLB_REG_BMX_QOS_SDHM_MSK     (((1U << GLB_REG_BMX_QOS_SDHM_LEN) - 1) << GLB_REG_BMX_QOS_SDHM_POS)
+#define GLB_REG_BMX_QOS_SDHM_UMSK    (~(((1U << GLB_REG_BMX_QOS_SDHM_LEN) - 1) << GLB_REG_BMX_QOS_SDHM_POS))
+#define GLB_BMX_DBG_SEL              GLB_BMX_DBG_SEL
+#define GLB_BMX_DBG_SEL_POS          (28U)
+#define GLB_BMX_DBG_SEL_LEN          (4U)
+#define GLB_BMX_DBG_SEL_MSK          (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
+#define GLB_BMX_DBG_SEL_UMSK         (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
+
+/* 0x328 : bmx_cfg2 */
+#define GLB_BMX_CFG2_OFFSET      (0x328)
+#define GLB_REG_BMX_BERR_EN      GLB_REG_BMX_BERR_EN
+#define GLB_REG_BMX_BERR_EN_POS  (0U)
+#define GLB_REG_BMX_BERR_EN_LEN  (10U)
+#define GLB_REG_BMX_BERR_EN_MSK  (((1U << GLB_REG_BMX_BERR_EN_LEN) - 1) << GLB_REG_BMX_BERR_EN_POS)
+#define GLB_REG_BMX_BERR_EN_UMSK (~(((1U << GLB_REG_BMX_BERR_EN_LEN) - 1) << GLB_REG_BMX_BERR_EN_POS))
+#define GLB_REG_MCU_BERR_EN      GLB_REG_MCU_BERR_EN
+#define GLB_REG_MCU_BERR_EN_POS  (16U)
+#define GLB_REG_MCU_BERR_EN_LEN  (1U)
+#define GLB_REG_MCU_BERR_EN_MSK  (((1U << GLB_REG_MCU_BERR_EN_LEN) - 1) << GLB_REG_MCU_BERR_EN_POS)
+#define GLB_REG_MCU_BERR_EN_UMSK (~(((1U << GLB_REG_MCU_BERR_EN_LEN) - 1) << GLB_REG_MCU_BERR_EN_POS))
+
+/* 0x32C : bmx_cfg3 */
+#define GLB_BMX_CFG3_OFFSET         (0x32C)
+#define GLB_REG_BMX_BERR_CLR        GLB_REG_BMX_BERR_CLR
+#define GLB_REG_BMX_BERR_CLR_POS    (0U)
+#define GLB_REG_BMX_BERR_CLR_LEN    (1U)
+#define GLB_REG_BMX_BERR_CLR_MSK    (((1U << GLB_REG_BMX_BERR_CLR_LEN) - 1) << GLB_REG_BMX_BERR_CLR_POS)
+#define GLB_REG_BMX_BERR_CLR_UMSK   (~(((1U << GLB_REG_BMX_BERR_CLR_LEN) - 1) << GLB_REG_BMX_BERR_CLR_POS))
+#define GLB_REG_BMX_BERR_LAST       GLB_REG_BMX_BERR_LAST
+#define GLB_REG_BMX_BERR_LAST_POS   (1U)
+#define GLB_REG_BMX_BERR_LAST_LEN   (1U)
+#define GLB_REG_BMX_BERR_LAST_MSK   (((1U << GLB_REG_BMX_BERR_LAST_LEN) - 1) << GLB_REG_BMX_BERR_LAST_POS)
+#define GLB_REG_BMX_BERR_LAST_UMSK  (~(((1U << GLB_REG_BMX_BERR_LAST_LEN) - 1) << GLB_REG_BMX_BERR_LAST_POS))
+#define GLB_REG_MCU_BERR_CLR        GLB_REG_MCU_BERR_CLR
+#define GLB_REG_MCU_BERR_CLR_POS    (8U)
+#define GLB_REG_MCU_BERR_CLR_LEN    (1U)
+#define GLB_REG_MCU_BERR_CLR_MSK    (((1U << GLB_REG_MCU_BERR_CLR_LEN) - 1) << GLB_REG_MCU_BERR_CLR_POS)
+#define GLB_REG_MCU_BERR_CLR_UMSK   (~(((1U << GLB_REG_MCU_BERR_CLR_LEN) - 1) << GLB_REG_MCU_BERR_CLR_POS))
+#define GLB_REG_MCU_BERR_LAST       GLB_REG_MCU_BERR_LAST
+#define GLB_REG_MCU_BERR_LAST_POS   (9U)
+#define GLB_REG_MCU_BERR_LAST_LEN   (1U)
+#define GLB_REG_MCU_BERR_LAST_MSK   (((1U << GLB_REG_MCU_BERR_LAST_LEN) - 1) << GLB_REG_MCU_BERR_LAST_POS)
+#define GLB_REG_MCU_BERR_LAST_UMSK  (~(((1U << GLB_REG_MCU_BERR_LAST_LEN) - 1) << GLB_REG_MCU_BERR_LAST_POS))
+#define GLB_STS_BMX_BERR            GLB_STS_BMX_BERR
+#define GLB_STS_BMX_BERR_POS        (16U)
+#define GLB_STS_BMX_BERR_LEN        (1U)
+#define GLB_STS_BMX_BERR_MSK        (((1U << GLB_STS_BMX_BERR_LEN) - 1) << GLB_STS_BMX_BERR_POS)
+#define GLB_STS_BMX_BERR_UMSK       (~(((1U << GLB_STS_BMX_BERR_LEN) - 1) << GLB_STS_BMX_BERR_POS))
+#define GLB_STS_MCU_BERR            GLB_STS_MCU_BERR
+#define GLB_STS_MCU_BERR_POS        (17U)
+#define GLB_STS_MCU_BERR_LEN        (1U)
+#define GLB_STS_MCU_BERR_MSK        (((1U << GLB_STS_MCU_BERR_LEN) - 1) << GLB_STS_MCU_BERR_POS)
+#define GLB_STS_MCU_BERR_UMSK       (~(((1U << GLB_STS_MCU_BERR_LEN) - 1) << GLB_STS_MCU_BERR_POS))
+#define GLB_STS_BMX_BERR_WRITE      GLB_STS_BMX_BERR_WRITE
+#define GLB_STS_BMX_BERR_WRITE_POS  (24U)
+#define GLB_STS_BMX_BERR_WRITE_LEN  (1U)
+#define GLB_STS_BMX_BERR_WRITE_MSK  (((1U << GLB_STS_BMX_BERR_WRITE_LEN) - 1) << GLB_STS_BMX_BERR_WRITE_POS)
+#define GLB_STS_BMX_BERR_WRITE_UMSK (~(((1U << GLB_STS_BMX_BERR_WRITE_LEN) - 1) << GLB_STS_BMX_BERR_WRITE_POS))
+#define GLB_STS_MCU_BERR_WRITE      GLB_STS_MCU_BERR_WRITE
+#define GLB_STS_MCU_BERR_WRITE_POS  (25U)
+#define GLB_STS_MCU_BERR_WRITE_LEN  (1U)
+#define GLB_STS_MCU_BERR_WRITE_MSK  (((1U << GLB_STS_MCU_BERR_WRITE_LEN) - 1) << GLB_STS_MCU_BERR_WRITE_POS)
+#define GLB_STS_MCU_BERR_WRITE_UMSK (~(((1U << GLB_STS_MCU_BERR_WRITE_LEN) - 1) << GLB_STS_MCU_BERR_WRITE_POS))
+
+/* 0x330 : bmx_cfg4 */
+#define GLB_BMX_CFG4_OFFSET       (0x330)
+#define GLB_STS_BMX_BERR_SRC      GLB_STS_BMX_BERR_SRC
+#define GLB_STS_BMX_BERR_SRC_POS  (0U)
+#define GLB_STS_BMX_BERR_SRC_LEN  (10U)
+#define GLB_STS_BMX_BERR_SRC_MSK  (((1U << GLB_STS_BMX_BERR_SRC_LEN) - 1) << GLB_STS_BMX_BERR_SRC_POS)
+#define GLB_STS_BMX_BERR_SRC_UMSK (~(((1U << GLB_STS_BMX_BERR_SRC_LEN) - 1) << GLB_STS_BMX_BERR_SRC_POS))
+#define GLB_STS_MCU_BERR_SRC      GLB_STS_MCU_BERR_SRC
+#define GLB_STS_MCU_BERR_SRC_POS  (16U)
+#define GLB_STS_MCU_BERR_SRC_LEN  (1U)
+#define GLB_STS_MCU_BERR_SRC_MSK  (((1U << GLB_STS_MCU_BERR_SRC_LEN) - 1) << GLB_STS_MCU_BERR_SRC_POS)
+#define GLB_STS_MCU_BERR_SRC_UMSK (~(((1U << GLB_STS_MCU_BERR_SRC_LEN) - 1) << GLB_STS_MCU_BERR_SRC_POS))
+#define GLB_STS_MCU_BERR_ID       GLB_STS_MCU_BERR_ID
+#define GLB_STS_MCU_BERR_ID_POS   (24U)
+#define GLB_STS_MCU_BERR_ID_LEN   (8U)
+#define GLB_STS_MCU_BERR_ID_MSK   (((1U << GLB_STS_MCU_BERR_ID_LEN) - 1) << GLB_STS_MCU_BERR_ID_POS)
+#define GLB_STS_MCU_BERR_ID_UMSK  (~(((1U << GLB_STS_MCU_BERR_ID_LEN) - 1) << GLB_STS_MCU_BERR_ID_POS))
+
+/* 0x334 : bmx_cfg5 */
+#define GLB_BMX_CFG5_OFFSET        (0x334)
+#define GLB_STS_BMX_BERR_ADDR      GLB_STS_BMX_BERR_ADDR
+#define GLB_STS_BMX_BERR_ADDR_POS  (0U)
+#define GLB_STS_BMX_BERR_ADDR_LEN  (32U)
+#define GLB_STS_BMX_BERR_ADDR_MSK  (((1U << GLB_STS_BMX_BERR_ADDR_LEN) - 1) << GLB_STS_BMX_BERR_ADDR_POS)
+#define GLB_STS_BMX_BERR_ADDR_UMSK (~(((1U << GLB_STS_BMX_BERR_ADDR_LEN) - 1) << GLB_STS_BMX_BERR_ADDR_POS))
+
+/* 0x338 : bmx_cfg6 */
+#define GLB_BMX_CFG6_OFFSET        (0x338)
+#define GLB_STS_MCU_BERR_ADDR      GLB_STS_MCU_BERR_ADDR
+#define GLB_STS_MCU_BERR_ADDR_POS  (0U)
+#define GLB_STS_MCU_BERR_ADDR_LEN  (32U)
+#define GLB_STS_MCU_BERR_ADDR_MSK  (((1U << GLB_STS_MCU_BERR_ADDR_LEN) - 1) << GLB_STS_MCU_BERR_ADDR_POS)
+#define GLB_STS_MCU_BERR_ADDR_UMSK (~(((1U << GLB_STS_MCU_BERR_ADDR_LEN) - 1) << GLB_STS_MCU_BERR_ADDR_POS))
+
+/* 0x340 : audio_cfg0 */
+#define GLB_AUDIO_CFG0_OFFSET          (0x340)
+#define GLB_REG_AUDIO_ADC_CLK_DIV      GLB_REG_AUDIO_ADC_CLK_DIV
+#define GLB_REG_AUDIO_ADC_CLK_DIV_POS  (8U)
+#define GLB_REG_AUDIO_ADC_CLK_DIV_LEN  (6U)
+#define GLB_REG_AUDIO_ADC_CLK_DIV_MSK  (((1U << GLB_REG_AUDIO_ADC_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_DIV_POS)
+#define GLB_REG_AUDIO_ADC_CLK_DIV_UMSK (~(((1U << GLB_REG_AUDIO_ADC_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_DIV_POS))
+#define GLB_REG_AUDIO_ADC_CLK_EN       GLB_REG_AUDIO_ADC_CLK_EN
+#define GLB_REG_AUDIO_ADC_CLK_EN_POS   (15U)
+#define GLB_REG_AUDIO_ADC_CLK_EN_LEN   (1U)
+#define GLB_REG_AUDIO_ADC_CLK_EN_MSK   (((1U << GLB_REG_AUDIO_ADC_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_EN_POS)
+#define GLB_REG_AUDIO_ADC_CLK_EN_UMSK  (~(((1U << GLB_REG_AUDIO_ADC_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_ADC_CLK_EN_POS))
+#define GLB_REG_AUDIO_AUTO_DIV_EN      GLB_REG_AUDIO_AUTO_DIV_EN
+#define GLB_REG_AUDIO_AUTO_DIV_EN_POS  (31U)
+#define GLB_REG_AUDIO_AUTO_DIV_EN_LEN  (1U)
+#define GLB_REG_AUDIO_AUTO_DIV_EN_MSK  (((1U << GLB_REG_AUDIO_AUTO_DIV_EN_LEN) - 1) << GLB_REG_AUDIO_AUTO_DIV_EN_POS)
+#define GLB_REG_AUDIO_AUTO_DIV_EN_UMSK (~(((1U << GLB_REG_AUDIO_AUTO_DIV_EN_LEN) - 1) << GLB_REG_AUDIO_AUTO_DIV_EN_POS))
+
+/* 0x344 : audio_cfg1 */
+#define GLB_AUDIO_CFG1_OFFSET           (0x344)
+#define GLB_REG_AUDIO_SOLO_CLK_DIV      GLB_REG_AUDIO_SOLO_CLK_DIV
+#define GLB_REG_AUDIO_SOLO_CLK_DIV_POS  (16U)
+#define GLB_REG_AUDIO_SOLO_CLK_DIV_LEN  (8U)
+#define GLB_REG_AUDIO_SOLO_CLK_DIV_MSK  (((1U << GLB_REG_AUDIO_SOLO_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_SOLO_CLK_DIV_POS)
+#define GLB_REG_AUDIO_SOLO_CLK_DIV_UMSK (~(((1U << GLB_REG_AUDIO_SOLO_CLK_DIV_LEN) - 1) << GLB_REG_AUDIO_SOLO_CLK_DIV_POS))
+#define GLB_REG_AUDIO_SOLO_CLK_EN       GLB_REG_AUDIO_SOLO_CLK_EN
+#define GLB_REG_AUDIO_SOLO_CLK_EN_POS   (24U)
+#define GLB_REG_AUDIO_SOLO_CLK_EN_LEN   (1U)
+#define GLB_REG_AUDIO_SOLO_CLK_EN_MSK   (((1U << GLB_REG_AUDIO_SOLO_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_SOLO_CLK_EN_POS)
+#define GLB_REG_AUDIO_SOLO_CLK_EN_UMSK  (~(((1U << GLB_REG_AUDIO_SOLO_CLK_EN_LEN) - 1) << GLB_REG_AUDIO_SOLO_CLK_EN_POS))
+
+/* 0x390 : eth_cfg0 */
+#define GLB_ETH_CFG0_OFFSET            (0x390)
+#define GLB_CFG_SEL_ETH_REF_CLK_O      GLB_CFG_SEL_ETH_REF_CLK_O
+#define GLB_CFG_SEL_ETH_REF_CLK_O_POS  (5U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_LEN  (1U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_REF_CLK_O      GLB_CFG_INV_ETH_REF_CLK_O
+#define GLB_CFG_INV_ETH_REF_CLK_O_POS  (6U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_LEN  (1U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS)
+#define GLB_CFG_INV_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_TX_CLK         GLB_CFG_INV_ETH_TX_CLK
+#define GLB_CFG_INV_ETH_TX_CLK_POS     (7U)
+#define GLB_CFG_INV_ETH_TX_CLK_LEN     (1U)
+#define GLB_CFG_INV_ETH_TX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS)
+#define GLB_CFG_INV_ETH_TX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS))
+#define GLB_CFG_INV_ETH_RX_CLK         GLB_CFG_INV_ETH_RX_CLK
+#define GLB_CFG_INV_ETH_RX_CLK_POS     (10U)
+#define GLB_CFG_INV_ETH_RX_CLK_LEN     (1U)
+#define GLB_CFG_INV_ETH_RX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS)
+#define GLB_CFG_INV_ETH_RX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS))
+
+/* 0x420 : cam_cfg0 */
+#define GLB_CAM_CFG0_OFFSET              (0x420)
+#define GLB_REG_CAM_REF_CLK_EN           GLB_REG_CAM_REF_CLK_EN
+#define GLB_REG_CAM_REF_CLK_EN_POS       (27U)
+#define GLB_REG_CAM_REF_CLK_EN_LEN       (1U)
+#define GLB_REG_CAM_REF_CLK_EN_MSK       (((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS)
+#define GLB_REG_CAM_REF_CLK_EN_UMSK      (~(((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS))
+#define GLB_REG_CAM_REF_CLK_SRC_SEL      GLB_REG_CAM_REF_CLK_SRC_SEL
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_POS  (28U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_LEN  (2U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_MSK  (((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS))
+#define GLB_REG_CAM_REF_CLK_DIV          GLB_REG_CAM_REF_CLK_DIV
+#define GLB_REG_CAM_REF_CLK_DIV_POS      (30U)
+#define GLB_REG_CAM_REF_CLK_DIV_LEN      (2U)
+#define GLB_REG_CAM_REF_CLK_DIV_MSK      (((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS)
+#define GLB_REG_CAM_REF_CLK_DIV_UMSK     (~(((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS))
+
+/* 0x430 : sdh_cfg0 */
+#define GLB_SDH_CFG0_OFFSET      (0x430)
+#define GLB_REG_SDH_CLK_DIV      GLB_REG_SDH_CLK_DIV
+#define GLB_REG_SDH_CLK_DIV_POS  (9U)
+#define GLB_REG_SDH_CLK_DIV_LEN  (3U)
+#define GLB_REG_SDH_CLK_DIV_MSK  (((1U << GLB_REG_SDH_CLK_DIV_LEN) - 1) << GLB_REG_SDH_CLK_DIV_POS)
+#define GLB_REG_SDH_CLK_DIV_UMSK (~(((1U << GLB_REG_SDH_CLK_DIV_LEN) - 1) << GLB_REG_SDH_CLK_DIV_POS))
+#define GLB_REG_SDH_CLK_SEL      GLB_REG_SDH_CLK_SEL
+#define GLB_REG_SDH_CLK_SEL_POS  (12U)
+#define GLB_REG_SDH_CLK_SEL_LEN  (1U)
+#define GLB_REG_SDH_CLK_SEL_MSK  (((1U << GLB_REG_SDH_CLK_SEL_LEN) - 1) << GLB_REG_SDH_CLK_SEL_POS)
+#define GLB_REG_SDH_CLK_SEL_UMSK (~(((1U << GLB_REG_SDH_CLK_SEL_LEN) - 1) << GLB_REG_SDH_CLK_SEL_POS))
+#define GLB_REG_SDH_CLK_EN       GLB_REG_SDH_CLK_EN
+#define GLB_REG_SDH_CLK_EN_POS   (13U)
+#define GLB_REG_SDH_CLK_EN_LEN   (1U)
+#define GLB_REG_SDH_CLK_EN_MSK   (((1U << GLB_REG_SDH_CLK_EN_LEN) - 1) << GLB_REG_SDH_CLK_EN_POS)
+#define GLB_REG_SDH_CLK_EN_UMSK  (~(((1U << GLB_REG_SDH_CLK_EN_LEN) - 1) << GLB_REG_SDH_CLK_EN_POS))
+
+/* 0x440 : sdio_cfg0 */
+#define GLB_SDIO_CFG0_OFFSET          (0x440)
+#define GLB_REG_SDIO_INT_SYS_DIS      GLB_REG_SDIO_INT_SYS_DIS
+#define GLB_REG_SDIO_INT_SYS_DIS_POS  (0U)
+#define GLB_REG_SDIO_INT_SYS_DIS_LEN  (1U)
+#define GLB_REG_SDIO_INT_SYS_DIS_MSK  (((1U << GLB_REG_SDIO_INT_SYS_DIS_LEN) - 1) << GLB_REG_SDIO_INT_SYS_DIS_POS)
+#define GLB_REG_SDIO_INT_SYS_DIS_UMSK (~(((1U << GLB_REG_SDIO_INT_SYS_DIS_LEN) - 1) << GLB_REG_SDIO_INT_SYS_DIS_POS))
+#define GLB_REG_SD_RST_SD_DIS         GLB_REG_SD_RST_SD_DIS
+#define GLB_REG_SD_RST_SD_DIS_POS     (1U)
+#define GLB_REG_SD_RST_SD_DIS_LEN     (1U)
+#define GLB_REG_SD_RST_SD_DIS_MSK     (((1U << GLB_REG_SD_RST_SD_DIS_LEN) - 1) << GLB_REG_SD_RST_SD_DIS_POS)
+#define GLB_REG_SD_RST_SD_DIS_UMSK    (~(((1U << GLB_REG_SD_RST_SD_DIS_LEN) - 1) << GLB_REG_SD_RST_SD_DIS_POS))
+#define GLB_REG_SDU_RST_SD_DIS        GLB_REG_SDU_RST_SD_DIS
+#define GLB_REG_SDU_RST_SD_DIS_POS    (2U)
+#define GLB_REG_SDU_RST_SD_DIS_LEN    (1U)
+#define GLB_REG_SDU_RST_SD_DIS_MSK    (((1U << GLB_REG_SDU_RST_SD_DIS_LEN) - 1) << GLB_REG_SDU_RST_SD_DIS_POS)
+#define GLB_REG_SDU_RST_SD_DIS_UMSK   (~(((1U << GLB_REG_SDU_RST_SD_DIS_LEN) - 1) << GLB_REG_SDU_RST_SD_DIS_POS))
+#define GLB_REG_SYS_RST_SD_EN         GLB_REG_SYS_RST_SD_EN
+#define GLB_REG_SYS_RST_SD_EN_POS     (3U)
+#define GLB_REG_SYS_RST_SD_EN_LEN     (1U)
+#define GLB_REG_SYS_RST_SD_EN_MSK     (((1U << GLB_REG_SYS_RST_SD_EN_LEN) - 1) << GLB_REG_SYS_RST_SD_EN_POS)
+#define GLB_REG_SYS_RST_SD_EN_UMSK    (~(((1U << GLB_REG_SYS_RST_SD_EN_LEN) - 1) << GLB_REG_SYS_RST_SD_EN_POS))
+#define GLB_SDU_CMDRCVD               GLB_SDU_CMDRCVD
+#define GLB_SDU_CMDRCVD_POS           (12U)
+#define GLB_SDU_CMDRCVD_LEN           (1U)
+#define GLB_SDU_CMDRCVD_MSK           (((1U << GLB_SDU_CMDRCVD_LEN) - 1) << GLB_SDU_CMDRCVD_POS)
+#define GLB_SDU_CMDRCVD_UMSK          (~(((1U << GLB_SDU_CMDRCVD_LEN) - 1) << GLB_SDU_CMDRCVD_POS))
+#define GLB_SDU_CLK_SWITCH_OK         GLB_SDU_CLK_SWITCH_OK
+#define GLB_SDU_CLK_SWITCH_OK_POS     (13U)
+#define GLB_SDU_CLK_SWITCH_OK_LEN     (1U)
+#define GLB_SDU_CLK_SWITCH_OK_MSK     (((1U << GLB_SDU_CLK_SWITCH_OK_LEN) - 1) << GLB_SDU_CLK_SWITCH_OK_POS)
+#define GLB_SDU_CLK_SWITCH_OK_UMSK    (~(((1U << GLB_SDU_CLK_SWITCH_OK_LEN) - 1) << GLB_SDU_CLK_SWITCH_OK_POS))
+#define GLB_SD_PWUP                   GLB_SD_PWUP
+#define GLB_SD_PWUP_POS               (14U)
+#define GLB_SD_PWUP_LEN               (1U)
+#define GLB_SD_PWUP_MSK               (((1U << GLB_SD_PWUP_LEN) - 1) << GLB_SD_PWUP_POS)
+#define GLB_SD_PWUP_UMSK              (~(((1U << GLB_SD_PWUP_LEN) - 1) << GLB_SD_PWUP_POS))
+#define GLB_SDU_DBG                   GLB_SDU_DBG
+#define GLB_SDU_DBG_POS               (16U)
+#define GLB_SDU_DBG_LEN               (16U)
+#define GLB_SDU_DBG_MSK               (((1U << GLB_SDU_DBG_LEN) - 1) << GLB_SDU_DBG_POS)
+#define GLB_SDU_DBG_UMSK              (~(((1U << GLB_SDU_DBG_LEN) - 1) << GLB_SDU_DBG_POS))
+
+/* 0x490 : tzc_cfg0 */
+#define GLB_TZC_CFG0_OFFSET              (0x490)
+#define GLB_TZC_GLB_PWRON_RST_LOCK       GLB_TZC_GLB_PWRON_RST_LOCK
+#define GLB_TZC_GLB_PWRON_RST_LOCK_POS   (12U)
+#define GLB_TZC_GLB_PWRON_RST_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_PWRON_RST_LOCK_MSK   (((1U << GLB_TZC_GLB_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_PWRON_RST_LOCK_POS)
+#define GLB_TZC_GLB_PWRON_RST_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_PWRON_RST_LOCK_POS))
+#define GLB_TZC_GLB_CPU_RESET_LOCK       GLB_TZC_GLB_CPU_RESET_LOCK
+#define GLB_TZC_GLB_CPU_RESET_LOCK_POS   (13U)
+#define GLB_TZC_GLB_CPU_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CPU_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CPU_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU_RESET_LOCK_POS))
+#define GLB_TZC_GLB_SYS_RESET_LOCK       GLB_TZC_GLB_SYS_RESET_LOCK
+#define GLB_TZC_GLB_SYS_RESET_LOCK_POS   (14U)
+#define GLB_TZC_GLB_SYS_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_SYS_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_SYS_RESET_LOCK_POS)
+#define GLB_TZC_GLB_SYS_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_SYS_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CPU2_RESET_LOCK      GLB_TZC_GLB_CPU2_RESET_LOCK
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_POS  (15U)
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_MSK  (((1U << GLB_TZC_GLB_CPU2_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU2_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CPU2_RESET_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CPU2_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CPU2_RESET_LOCK_POS))
+#define GLB_TZC_GLB_PWR_LOCK             GLB_TZC_GLB_PWR_LOCK
+#define GLB_TZC_GLB_PWR_LOCK_POS         (21U)
+#define GLB_TZC_GLB_PWR_LOCK_LEN         (1U)
+#define GLB_TZC_GLB_PWR_LOCK_MSK         (((1U << GLB_TZC_GLB_PWR_LOCK_LEN) - 1) << GLB_TZC_GLB_PWR_LOCK_POS)
+#define GLB_TZC_GLB_PWR_LOCK_UMSK        (~(((1U << GLB_TZC_GLB_PWR_LOCK_LEN) - 1) << GLB_TZC_GLB_PWR_LOCK_POS))
+#define GLB_TZC_GLB_INT_LOCK             GLB_TZC_GLB_INT_LOCK
+#define GLB_TZC_GLB_INT_LOCK_POS         (22U)
+#define GLB_TZC_GLB_INT_LOCK_LEN         (1U)
+#define GLB_TZC_GLB_INT_LOCK_MSK         (((1U << GLB_TZC_GLB_INT_LOCK_LEN) - 1) << GLB_TZC_GLB_INT_LOCK_POS)
+#define GLB_TZC_GLB_INT_LOCK_UMSK        (~(((1U << GLB_TZC_GLB_INT_LOCK_LEN) - 1) << GLB_TZC_GLB_INT_LOCK_POS))
+#define GLB_TZC_GLB_CPUPLL_LOCK          GLB_TZC_GLB_CPUPLL_LOCK
+#define GLB_TZC_GLB_CPUPLL_LOCK_POS      (24U)
+#define GLB_TZC_GLB_CPUPLL_LOCK_LEN      (1U)
+#define GLB_TZC_GLB_CPUPLL_LOCK_MSK      (((1U << GLB_TZC_GLB_CPUPLL_LOCK_LEN) - 1) << GLB_TZC_GLB_CPUPLL_LOCK_POS)
+#define GLB_TZC_GLB_CPUPLL_LOCK_UMSK     (~(((1U << GLB_TZC_GLB_CPUPLL_LOCK_LEN) - 1) << GLB_TZC_GLB_CPUPLL_LOCK_POS))
+#define GLB_TZC_GLB_MISC_LOCK            GLB_TZC_GLB_MISC_LOCK
+#define GLB_TZC_GLB_MISC_LOCK_POS        (25U)
+#define GLB_TZC_GLB_MISC_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_MISC_LOCK_MSK        (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
+#define GLB_TZC_GLB_MISC_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
+#define GLB_TZC_GLB_SRAM_LOCK            GLB_TZC_GLB_SRAM_LOCK
+#define GLB_TZC_GLB_SRAM_LOCK_POS        (26U)
+#define GLB_TZC_GLB_SRAM_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SRAM_LOCK_MSK        (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
+#define GLB_TZC_GLB_SRAM_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_LOCK           GLB_TZC_GLB_SWRST_LOCK
+#define GLB_TZC_GLB_SWRST_LOCK_POS       (27U)
+#define GLB_TZC_GLB_SWRST_LOCK_LEN       (1U)
+#define GLB_TZC_GLB_SWRST_LOCK_MSK       (((1U << GLB_TZC_GLB_SWRST_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_LOCK_UMSK      (~(((1U << GLB_TZC_GLB_SWRST_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_LOCK_POS))
+#define GLB_TZC_GLB_BMX_LOCK             GLB_TZC_GLB_BMX_LOCK
+#define GLB_TZC_GLB_BMX_LOCK_POS         (28U)
+#define GLB_TZC_GLB_BMX_LOCK_LEN         (1U)
+#define GLB_TZC_GLB_BMX_LOCK_MSK         (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
+#define GLB_TZC_GLB_BMX_LOCK_UMSK        (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
+#define GLB_TZC_GLB_DBG_LOCK             GLB_TZC_GLB_DBG_LOCK
+#define GLB_TZC_GLB_DBG_LOCK_POS         (29U)
+#define GLB_TZC_GLB_DBG_LOCK_LEN         (1U)
+#define GLB_TZC_GLB_DBG_LOCK_MSK         (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
+#define GLB_TZC_GLB_DBG_LOCK_UMSK        (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
+#define GLB_TZC_GLB_MBIST_LOCK           GLB_TZC_GLB_MBIST_LOCK
+#define GLB_TZC_GLB_MBIST_LOCK_POS       (30U)
+#define GLB_TZC_GLB_MBIST_LOCK_LEN       (1U)
+#define GLB_TZC_GLB_MBIST_LOCK_MSK       (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
+#define GLB_TZC_GLB_MBIST_LOCK_UMSK      (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
+#define GLB_TZC_GLB_CLK_LOCK             GLB_TZC_GLB_CLK_LOCK
+#define GLB_TZC_GLB_CLK_LOCK_POS         (31U)
+#define GLB_TZC_GLB_CLK_LOCK_LEN         (1U)
+#define GLB_TZC_GLB_CLK_LOCK_MSK         (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
+#define GLB_TZC_GLB_CLK_LOCK_UMSK        (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
+
+/* 0x510 : glb_parm_cfg0 */
+#define GLB_PARM_CFG0_OFFSET            (0x510)
+#define GLB_UART_SWAP_SET               GLB_UART_SWAP_SET
+#define GLB_UART_SWAP_SET_POS           (2U)
+#define GLB_UART_SWAP_SET_LEN           (4U)
+#define GLB_UART_SWAP_SET_MSK           (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
+#define GLB_UART_SWAP_SET_UMSK          (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
+#define GLB_SWAP_SFLASH_IO_3_IO_0       GLB_SWAP_SFLASH_IO_3_IO_0
+#define GLB_SWAP_SFLASH_IO_3_IO_0_POS   (8U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_LEN   (1U)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_MSK   (((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS)
+#define GLB_SWAP_SFLASH_IO_3_IO_0_UMSK  (~(((1U << GLB_SWAP_SFLASH_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH_IO_3_IO_0_POS))
+#define GLB_SEL_EMBEDDED_SFLASH         GLB_SEL_EMBEDDED_SFLASH
+#define GLB_SEL_EMBEDDED_SFLASH_POS     (9U)
+#define GLB_SEL_EMBEDDED_SFLASH_LEN     (1U)
+#define GLB_SEL_EMBEDDED_SFLASH_MSK     (((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS)
+#define GLB_SEL_EMBEDDED_SFLASH_UMSK    (~(((1U << GLB_SEL_EMBEDDED_SFLASH_LEN) - 1) << GLB_SEL_EMBEDDED_SFLASH_POS))
+#define GLB_SWAP_SFLASH_IO_2_CS         GLB_SWAP_SFLASH_IO_2_CS
+#define GLB_SWAP_SFLASH_IO_2_CS_POS     (10U)
+#define GLB_SWAP_SFLASH_IO_2_CS_LEN     (1U)
+#define GLB_SWAP_SFLASH_IO_2_CS_MSK     (((1U << GLB_SWAP_SFLASH_IO_2_CS_LEN) - 1) << GLB_SWAP_SFLASH_IO_2_CS_POS)
+#define GLB_SWAP_SFLASH_IO_2_CS_UMSK    (~(((1U << GLB_SWAP_SFLASH_IO_2_CS_LEN) - 1) << GLB_SWAP_SFLASH_IO_2_CS_POS))
+#define GLB_SWAP_SFLASH2_IO_3_IO_0      GLB_SWAP_SFLASH2_IO_3_IO_0
+#define GLB_SWAP_SFLASH2_IO_3_IO_0_POS  (11U)
+#define GLB_SWAP_SFLASH2_IO_3_IO_0_LEN  (1U)
+#define GLB_SWAP_SFLASH2_IO_3_IO_0_MSK  (((1U << GLB_SWAP_SFLASH2_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH2_IO_3_IO_0_POS)
+#define GLB_SWAP_SFLASH2_IO_3_IO_0_UMSK (~(((1U << GLB_SWAP_SFLASH2_IO_3_IO_0_LEN) - 1) << GLB_SWAP_SFLASH2_IO_3_IO_0_POS))
+#define GLB_REG_SPI_0_MASTER_MODE       GLB_REG_SPI_0_MASTER_MODE
+#define GLB_REG_SPI_0_MASTER_MODE_POS   (12U)
+#define GLB_REG_SPI_0_MASTER_MODE_LEN   (1U)
+#define GLB_REG_SPI_0_MASTER_MODE_MSK   (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)
+#define GLB_REG_SPI_0_MASTER_MODE_UMSK  (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS))
+#define GLB_REG_SPI_0_SWAP              GLB_REG_SPI_0_SWAP
+#define GLB_REG_SPI_0_SWAP_POS          (13U)
+#define GLB_REG_SPI_0_SWAP_LEN          (1U)
+#define GLB_REG_SPI_0_SWAP_MSK          (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
+#define GLB_REG_SPI_0_SWAP_UMSK         (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
+#define GLB_ANT_SWITCH_SEL              GLB_ANT_SWITCH_SEL
+#define GLB_ANT_SWITCH_SEL_POS          (15U)
+#define GLB_ANT_SWITCH_SEL_LEN          (1U)
+#define GLB_ANT_SWITCH_SEL_MSK          (((1U << GLB_ANT_SWITCH_SEL_LEN) - 1) << GLB_ANT_SWITCH_SEL_POS)
+#define GLB_ANT_SWITCH_SEL_UMSK         (~(((1U << GLB_ANT_SWITCH_SEL_LEN) - 1) << GLB_ANT_SWITCH_SEL_POS))
+#define GLB_P3_CCI_USE_IO_10_13         GLB_P3_CCI_USE_IO_10_13
+#define GLB_P3_CCI_USE_IO_10_13_POS     (19U)
+#define GLB_P3_CCI_USE_IO_10_13_LEN     (1U)
+#define GLB_P3_CCI_USE_IO_10_13_MSK     (((1U << GLB_P3_CCI_USE_IO_10_13_LEN) - 1) << GLB_P3_CCI_USE_IO_10_13_POS)
+#define GLB_P3_CCI_USE_IO_10_13_UMSK    (~(((1U << GLB_P3_CCI_USE_IO_10_13_LEN) - 1) << GLB_P3_CCI_USE_IO_10_13_POS))
+#define GLB_AUDIO_TEST_MODE             GLB_AUDIO_TEST_MODE
+#define GLB_AUDIO_TEST_MODE_POS         (29U)
+#define GLB_AUDIO_TEST_MODE_LEN         (1U)
+#define GLB_AUDIO_TEST_MODE_MSK         (((1U << GLB_AUDIO_TEST_MODE_LEN) - 1) << GLB_AUDIO_TEST_MODE_POS)
+#define GLB_AUDIO_TEST_MODE_UMSK        (~(((1U << GLB_AUDIO_TEST_MODE_LEN) - 1) << GLB_AUDIO_TEST_MODE_POS))
+#define GLB_SEL_RF_AUDIO_TEST           GLB_SEL_RF_AUDIO_TEST
+#define GLB_SEL_RF_AUDIO_TEST_POS       (30U)
+#define GLB_SEL_RF_AUDIO_TEST_LEN       (2U)
+#define GLB_SEL_RF_AUDIO_TEST_MSK       (((1U << GLB_SEL_RF_AUDIO_TEST_LEN) - 1) << GLB_SEL_RF_AUDIO_TEST_POS)
+#define GLB_SEL_RF_AUDIO_TEST_UMSK      (~(((1U << GLB_SEL_RF_AUDIO_TEST_LEN) - 1) << GLB_SEL_RF_AUDIO_TEST_POS))
+
+/* 0x520 : debug_cfg0 */
+#define GLB_DEBUG_CFG0_OFFSET (0x520)
+
+/* 0x524 : debug_cfg1 */
+#define GLB_DEBUG_CFG1_OFFSET       (0x524)
+#define GLB_DEBUG_NDRESET_GATE      GLB_DEBUG_NDRESET_GATE
+#define GLB_DEBUG_NDRESET_GATE_POS  (20U)
+#define GLB_DEBUG_NDRESET_GATE_LEN  (1U)
+#define GLB_DEBUG_NDRESET_GATE_MSK  (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
+#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
+
+/* 0x530 : reset_sts0 */
+#define GLB_RESET_STS0_OFFSET           (0x530)
+#define GLB_TOP_RESET_RECORDER          GLB_TOP_RESET_RECORDER
+#define GLB_TOP_RESET_RECORDER_POS      (0U)
+#define GLB_TOP_RESET_RECORDER_LEN      (7U)
+#define GLB_TOP_RESET_RECORDER_MSK      (((1U << GLB_TOP_RESET_RECORDER_LEN) - 1) << GLB_TOP_RESET_RECORDER_POS)
+#define GLB_TOP_RESET_RECORDER_UMSK     (~(((1U << GLB_TOP_RESET_RECORDER_LEN) - 1) << GLB_TOP_RESET_RECORDER_POS))
+#define GLB_CLR_TOP_RESET_RECORDER      GLB_CLR_TOP_RESET_RECORDER
+#define GLB_CLR_TOP_RESET_RECORDER_POS  (7U)
+#define GLB_CLR_TOP_RESET_RECORDER_LEN  (1U)
+#define GLB_CLR_TOP_RESET_RECORDER_MSK  (((1U << GLB_CLR_TOP_RESET_RECORDER_LEN) - 1) << GLB_CLR_TOP_RESET_RECORDER_POS)
+#define GLB_CLR_TOP_RESET_RECORDER_UMSK (~(((1U << GLB_CLR_TOP_RESET_RECORDER_LEN) - 1) << GLB_CLR_TOP_RESET_RECORDER_POS))
+
+/* 0x540 : swrst_s1_ext + swrst_s3 + swrst_s2 */
+#define GLB_SWRST_CFG0_OFFSET             (0x540)
+#define GLB_SWRST_S00                     GLB_SWRST_S00
+#define GLB_SWRST_S00_POS                 (0U)
+#define GLB_SWRST_S00_LEN                 (1U)
+#define GLB_SWRST_S00_MSK                 (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
+#define GLB_SWRST_S00_UMSK                (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
+#define GLB_SWRST_S01                     GLB_SWRST_S01
+#define GLB_SWRST_S01_POS                 (1U)
+#define GLB_SWRST_S01_LEN                 (1U)
+#define GLB_SWRST_S01_MSK                 (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
+#define GLB_SWRST_S01_UMSK                (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
+#define GLB_SWRST_S20                     GLB_SWRST_S20
+#define GLB_SWRST_S20_POS                 (4U)
+#define GLB_SWRST_S20_LEN                 (1U)
+#define GLB_SWRST_S20_MSK                 (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
+#define GLB_SWRST_S20_UMSK                (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
+#define GLB_SWRST_S30                     GLB_SWRST_S30
+#define GLB_SWRST_S30_POS                 (8U)
+#define GLB_SWRST_S30_LEN                 (1U)
+#define GLB_SWRST_S30_MSK                 (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
+#define GLB_SWRST_S30_UMSK                (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
+#define GLB_SWRST_S31                     GLB_SWRST_S31
+#define GLB_SWRST_S31_POS                 (9U)
+#define GLB_SWRST_S31_LEN                 (1U)
+#define GLB_SWRST_S31_MSK                 (((1U << GLB_SWRST_S31_LEN) - 1) << GLB_SWRST_S31_POS)
+#define GLB_SWRST_S31_UMSK                (~(((1U << GLB_SWRST_S31_LEN) - 1) << GLB_SWRST_S31_POS))
+#define GLB_SWRST_S32                     GLB_SWRST_S32
+#define GLB_SWRST_S32_POS                 (10U)
+#define GLB_SWRST_S32_LEN                 (1U)
+#define GLB_SWRST_S32_MSK                 (((1U << GLB_SWRST_S32_LEN) - 1) << GLB_SWRST_S32_POS)
+#define GLB_SWRST_S32_UMSK                (~(((1U << GLB_SWRST_S32_LEN) - 1) << GLB_SWRST_S32_POS))
+#define GLB_SWRST_S33                     GLB_SWRST_S33
+#define GLB_SWRST_S33_POS                 (11U)
+#define GLB_SWRST_S33_LEN                 (1U)
+#define GLB_SWRST_S33_MSK                 (((1U << GLB_SWRST_S33_LEN) - 1) << GLB_SWRST_S33_POS)
+#define GLB_SWRST_S33_UMSK                (~(((1U << GLB_SWRST_S33_LEN) - 1) << GLB_SWRST_S33_POS))
+#define GLB_SWRST_S1_EXT_EMI_MISC         GLB_SWRST_S1_EXT_EMI_MISC
+#define GLB_SWRST_S1_EXT_EMI_MISC_POS     (16U)
+#define GLB_SWRST_S1_EXT_EMI_MISC_LEN     (1U)
+#define GLB_SWRST_S1_EXT_EMI_MISC_MSK     (((1U << GLB_SWRST_S1_EXT_EMI_MISC_LEN) - 1) << GLB_SWRST_S1_EXT_EMI_MISC_POS)
+#define GLB_SWRST_S1_EXT_EMI_MISC_UMSK    (~(((1U << GLB_SWRST_S1_EXT_EMI_MISC_LEN) - 1) << GLB_SWRST_S1_EXT_EMI_MISC_POS))
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL      GLB_SWRST_S1_EXT_PSRAM0_CTRL
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_POS  (17U)
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_LEN  (1U)
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_MSK  (((1U << GLB_SWRST_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM0_CTRL_POS)
+#define GLB_SWRST_S1_EXT_PSRAM0_CTRL_UMSK (~(((1U << GLB_SWRST_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM0_CTRL_POS))
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL      GLB_SWRST_S1_EXT_PSRAM1_CTRL
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_POS  (18U)
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_LEN  (1U)
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_MSK  (((1U << GLB_SWRST_S1_EXT_PSRAM1_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM1_CTRL_POS)
+#define GLB_SWRST_S1_EXT_PSRAM1_CTRL_UMSK (~(((1U << GLB_SWRST_S1_EXT_PSRAM1_CTRL_LEN) - 1) << GLB_SWRST_S1_EXT_PSRAM1_CTRL_POS))
+#define GLB_SWRST_S1_EXT_USB              GLB_SWRST_S1_EXT_USB
+#define GLB_SWRST_S1_EXT_USB_POS          (19U)
+#define GLB_SWRST_S1_EXT_USB_LEN          (1U)
+#define GLB_SWRST_S1_EXT_USB_MSK          (((1U << GLB_SWRST_S1_EXT_USB_LEN) - 1) << GLB_SWRST_S1_EXT_USB_POS)
+#define GLB_SWRST_S1_EXT_USB_UMSK         (~(((1U << GLB_SWRST_S1_EXT_USB_LEN) - 1) << GLB_SWRST_S1_EXT_USB_POS))
+#define GLB_SWRST_S1_EXT_MIX2             GLB_SWRST_S1_EXT_MIX2
+#define GLB_SWRST_S1_EXT_MIX2_POS         (20U)
+#define GLB_SWRST_S1_EXT_MIX2_LEN         (1U)
+#define GLB_SWRST_S1_EXT_MIX2_MSK         (((1U << GLB_SWRST_S1_EXT_MIX2_LEN) - 1) << GLB_SWRST_S1_EXT_MIX2_POS)
+#define GLB_SWRST_S1_EXT_MIX2_UMSK        (~(((1U << GLB_SWRST_S1_EXT_MIX2_LEN) - 1) << GLB_SWRST_S1_EXT_MIX2_POS))
+#define GLB_SWRST_S1_EXT_AUDIO            GLB_SWRST_S1_EXT_AUDIO
+#define GLB_SWRST_S1_EXT_AUDIO_POS        (21U)
+#define GLB_SWRST_S1_EXT_AUDIO_LEN        (1U)
+#define GLB_SWRST_S1_EXT_AUDIO_MSK        (((1U << GLB_SWRST_S1_EXT_AUDIO_LEN) - 1) << GLB_SWRST_S1_EXT_AUDIO_POS)
+#define GLB_SWRST_S1_EXT_AUDIO_UMSK       (~(((1U << GLB_SWRST_S1_EXT_AUDIO_LEN) - 1) << GLB_SWRST_S1_EXT_AUDIO_POS))
+#define GLB_SWRST_S1_EXT_SDH              GLB_SWRST_S1_EXT_SDH
+#define GLB_SWRST_S1_EXT_SDH_POS          (22U)
+#define GLB_SWRST_S1_EXT_SDH_LEN          (1U)
+#define GLB_SWRST_S1_EXT_SDH_MSK          (((1U << GLB_SWRST_S1_EXT_SDH_LEN) - 1) << GLB_SWRST_S1_EXT_SDH_POS)
+#define GLB_SWRST_S1_EXT_SDH_UMSK         (~(((1U << GLB_SWRST_S1_EXT_SDH_LEN) - 1) << GLB_SWRST_S1_EXT_SDH_POS))
+#define GLB_SWRST_S1_EXT_EMAC             GLB_SWRST_S1_EXT_EMAC
+#define GLB_SWRST_S1_EXT_EMAC_POS         (23U)
+#define GLB_SWRST_S1_EXT_EMAC_LEN         (1U)
+#define GLB_SWRST_S1_EXT_EMAC_MSK         (((1U << GLB_SWRST_S1_EXT_EMAC_LEN) - 1) << GLB_SWRST_S1_EXT_EMAC_POS)
+#define GLB_SWRST_S1_EXT_EMAC_UMSK        (~(((1U << GLB_SWRST_S1_EXT_EMAC_LEN) - 1) << GLB_SWRST_S1_EXT_EMAC_POS))
+#define GLB_SWRST_S1_EXT_DMA2             GLB_SWRST_S1_EXT_DMA2
+#define GLB_SWRST_S1_EXT_DMA2_POS         (24U)
+#define GLB_SWRST_S1_EXT_DMA2_LEN         (1U)
+#define GLB_SWRST_S1_EXT_DMA2_MSK         (((1U << GLB_SWRST_S1_EXT_DMA2_LEN) - 1) << GLB_SWRST_S1_EXT_DMA2_POS)
+#define GLB_SWRST_S1_EXT_DMA2_UMSK        (~(((1U << GLB_SWRST_S1_EXT_DMA2_LEN) - 1) << GLB_SWRST_S1_EXT_DMA2_POS))
+#define GLB_SWRST_D2XA                    GLB_SWRST_D2XA
+#define GLB_SWRST_D2XA_POS                (25U)
+#define GLB_SWRST_D2XA_LEN                (1U)
+#define GLB_SWRST_D2XA_MSK                (((1U << GLB_SWRST_D2XA_LEN) - 1) << GLB_SWRST_D2XA_POS)
+#define GLB_SWRST_D2XA_UMSK               (~(((1U << GLB_SWRST_D2XA_LEN) - 1) << GLB_SWRST_D2XA_POS))
+#define GLB_SWRST_D2XB                    GLB_SWRST_D2XB
+#define GLB_SWRST_D2XB_POS                (26U)
+#define GLB_SWRST_D2XB_LEN                (1U)
+#define GLB_SWRST_D2XB_MSK                (((1U << GLB_SWRST_D2XB_LEN) - 1) << GLB_SWRST_D2XB_POS)
+#define GLB_SWRST_D2XB_UMSK               (~(((1U << GLB_SWRST_D2XB_LEN) - 1) << GLB_SWRST_D2XB_POS))
+#define GLB_SWRST_JENC                    GLB_SWRST_JENC
+#define GLB_SWRST_JENC_POS                (27U)
+#define GLB_SWRST_JENC_LEN                (1U)
+#define GLB_SWRST_JENC_MSK                (((1U << GLB_SWRST_JENC_LEN) - 1) << GLB_SWRST_JENC_POS)
+#define GLB_SWRST_JENC_UMSK               (~(((1U << GLB_SWRST_JENC_LEN) - 1) << GLB_SWRST_JENC_POS))
+#define GLB_SWRST_S1_EXT_PIO              GLB_SWRST_S1_EXT_PIO
+#define GLB_SWRST_S1_EXT_PIO_POS          (28U)
+#define GLB_SWRST_S1_EXT_PIO_LEN          (1U)
+#define GLB_SWRST_S1_EXT_PIO_MSK          (((1U << GLB_SWRST_S1_EXT_PIO_LEN) - 1) << GLB_SWRST_S1_EXT_PIO_POS)
+#define GLB_SWRST_S1_EXT_PIO_UMSK         (~(((1U << GLB_SWRST_S1_EXT_PIO_LEN) - 1) << GLB_SWRST_S1_EXT_PIO_POS))
+
+/* 0x544 : swrst_s1 */
+#define GLB_SWRST_CFG1_OFFSET (0x544)
+#define GLB_SWRST_S10         GLB_SWRST_S10
+#define GLB_SWRST_S10_POS     (0U)
+#define GLB_SWRST_S10_LEN     (1U)
+#define GLB_SWRST_S10_MSK     (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
+#define GLB_SWRST_S10_UMSK    (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
+#define GLB_SWRST_S11         GLB_SWRST_S11
+#define GLB_SWRST_S11_POS     (1U)
+#define GLB_SWRST_S11_LEN     (1U)
+#define GLB_SWRST_S11_MSK     (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
+#define GLB_SWRST_S11_UMSK    (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
+#define GLB_SWRST_S12         GLB_SWRST_S12
+#define GLB_SWRST_S12_POS     (2U)
+#define GLB_SWRST_S12_LEN     (1U)
+#define GLB_SWRST_S12_MSK     (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
+#define GLB_SWRST_S12_UMSK    (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
+#define GLB_SWRST_S13         GLB_SWRST_S13
+#define GLB_SWRST_S13_POS     (3U)
+#define GLB_SWRST_S13_LEN     (1U)
+#define GLB_SWRST_S13_MSK     (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
+#define GLB_SWRST_S13_UMSK    (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
+#define GLB_SWRST_S14         GLB_SWRST_S14
+#define GLB_SWRST_S14_POS     (4U)
+#define GLB_SWRST_S14_LEN     (1U)
+#define GLB_SWRST_S14_MSK     (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
+#define GLB_SWRST_S14_UMSK    (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
+#define GLB_SWRST_S15         GLB_SWRST_S15
+#define GLB_SWRST_S15_POS     (5U)
+#define GLB_SWRST_S15_LEN     (1U)
+#define GLB_SWRST_S15_MSK     (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
+#define GLB_SWRST_S15_UMSK    (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
+#define GLB_SWRST_S16         GLB_SWRST_S16
+#define GLB_SWRST_S16_POS     (6U)
+#define GLB_SWRST_S16_LEN     (1U)
+#define GLB_SWRST_S16_MSK     (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
+#define GLB_SWRST_S16_UMSK    (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
+#define GLB_SWRST_S17         GLB_SWRST_S17
+#define GLB_SWRST_S17_POS     (7U)
+#define GLB_SWRST_S17_LEN     (1U)
+#define GLB_SWRST_S17_MSK     (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
+#define GLB_SWRST_S17_UMSK    (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
+#define GLB_SWRST_S18         GLB_SWRST_S18
+#define GLB_SWRST_S18_POS     (8U)
+#define GLB_SWRST_S18_LEN     (1U)
+#define GLB_SWRST_S18_MSK     (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
+#define GLB_SWRST_S18_UMSK    (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
+#define GLB_SWRST_S19         GLB_SWRST_S19
+#define GLB_SWRST_S19_POS     (9U)
+#define GLB_SWRST_S19_LEN     (1U)
+#define GLB_SWRST_S19_MSK     (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
+#define GLB_SWRST_S19_UMSK    (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
+#define GLB_SWRST_S1A         GLB_SWRST_S1A
+#define GLB_SWRST_S1A_POS     (10U)
+#define GLB_SWRST_S1A_LEN     (1U)
+#define GLB_SWRST_S1A_MSK     (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
+#define GLB_SWRST_S1A_UMSK    (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
+#define GLB_SWRST_S1B         GLB_SWRST_S1B
+#define GLB_SWRST_S1B_POS     (11U)
+#define GLB_SWRST_S1B_LEN     (1U)
+#define GLB_SWRST_S1B_MSK     (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
+#define GLB_SWRST_S1B_UMSK    (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
+#define GLB_SWRST_S1C         GLB_SWRST_S1C
+#define GLB_SWRST_S1C_POS     (12U)
+#define GLB_SWRST_S1C_LEN     (1U)
+#define GLB_SWRST_S1C_MSK     (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
+#define GLB_SWRST_S1C_UMSK    (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
+#define GLB_SWRST_S1D         GLB_SWRST_S1D
+#define GLB_SWRST_S1D_POS     (13U)
+#define GLB_SWRST_S1D_LEN     (1U)
+#define GLB_SWRST_S1D_MSK     (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
+#define GLB_SWRST_S1D_UMSK    (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
+#define GLB_SWRST_S1E         GLB_SWRST_S1E
+#define GLB_SWRST_S1E_POS     (14U)
+#define GLB_SWRST_S1E_LEN     (1U)
+#define GLB_SWRST_S1E_MSK     (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
+#define GLB_SWRST_S1E_UMSK    (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
+#define GLB_SWRST_S1F         GLB_SWRST_S1F
+#define GLB_SWRST_S1F_POS     (15U)
+#define GLB_SWRST_S1F_LEN     (1U)
+#define GLB_SWRST_S1F_MSK     (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
+#define GLB_SWRST_S1F_UMSK    (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
+#define GLB_SWRST_S1A0        GLB_SWRST_S1A0
+#define GLB_SWRST_S1A0_POS    (16U)
+#define GLB_SWRST_S1A0_LEN    (1U)
+#define GLB_SWRST_S1A0_MSK    (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
+#define GLB_SWRST_S1A0_UMSK   (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
+#define GLB_SWRST_S1A1        GLB_SWRST_S1A1
+#define GLB_SWRST_S1A1_POS    (17U)
+#define GLB_SWRST_S1A1_LEN    (1U)
+#define GLB_SWRST_S1A1_MSK    (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
+#define GLB_SWRST_S1A1_UMSK   (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
+#define GLB_SWRST_S1A2        GLB_SWRST_S1A2
+#define GLB_SWRST_S1A2_POS    (18U)
+#define GLB_SWRST_S1A2_LEN    (1U)
+#define GLB_SWRST_S1A2_MSK    (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
+#define GLB_SWRST_S1A2_UMSK   (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
+#define GLB_SWRST_S1A3        GLB_SWRST_S1A3
+#define GLB_SWRST_S1A3_POS    (19U)
+#define GLB_SWRST_S1A3_LEN    (1U)
+#define GLB_SWRST_S1A3_MSK    (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
+#define GLB_SWRST_S1A3_UMSK   (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
+#define GLB_SWRST_S1A4        GLB_SWRST_S1A4
+#define GLB_SWRST_S1A4_POS    (20U)
+#define GLB_SWRST_S1A4_LEN    (1U)
+#define GLB_SWRST_S1A4_MSK    (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
+#define GLB_SWRST_S1A4_UMSK   (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
+#define GLB_SWRST_S1A5        GLB_SWRST_S1A5
+#define GLB_SWRST_S1A5_POS    (21U)
+#define GLB_SWRST_S1A5_LEN    (1U)
+#define GLB_SWRST_S1A5_MSK    (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
+#define GLB_SWRST_S1A5_UMSK   (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
+#define GLB_SWRST_S1A6        GLB_SWRST_S1A6
+#define GLB_SWRST_S1A6_POS    (22U)
+#define GLB_SWRST_S1A6_LEN    (1U)
+#define GLB_SWRST_S1A6_MSK    (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
+#define GLB_SWRST_S1A6_UMSK   (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
+#define GLB_SWRST_S1A7        GLB_SWRST_S1A7
+#define GLB_SWRST_S1A7_POS    (23U)
+#define GLB_SWRST_S1A7_LEN    (1U)
+#define GLB_SWRST_S1A7_MSK    (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
+#define GLB_SWRST_S1A7_UMSK   (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
+#define GLB_SWRST_S1A8        GLB_SWRST_S1A8
+#define GLB_SWRST_S1A8_POS    (24U)
+#define GLB_SWRST_S1A8_LEN    (1U)
+#define GLB_SWRST_S1A8_MSK    (((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS)
+#define GLB_SWRST_S1A8_UMSK   (~(((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS))
+#define GLB_SWRST_S1A9        GLB_SWRST_S1A9
+#define GLB_SWRST_S1A9_POS    (25U)
+#define GLB_SWRST_S1A9_LEN    (1U)
+#define GLB_SWRST_S1A9_MSK    (((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS)
+#define GLB_SWRST_S1A9_UMSK   (~(((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS))
+#define GLB_SWRST_S1AA        GLB_SWRST_S1AA
+#define GLB_SWRST_S1AA_POS    (26U)
+#define GLB_SWRST_S1AA_LEN    (1U)
+#define GLB_SWRST_S1AA_MSK    (((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS)
+#define GLB_SWRST_S1AA_UMSK   (~(((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS))
+#define GLB_SWRST_S1AB        GLB_SWRST_S1AB
+#define GLB_SWRST_S1AB_POS    (27U)
+#define GLB_SWRST_S1AB_LEN    (1U)
+#define GLB_SWRST_S1AB_MSK    (((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS)
+#define GLB_SWRST_S1AB_UMSK   (~(((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS))
+#define GLB_SWRST_S1AC        GLB_SWRST_S1AC
+#define GLB_SWRST_S1AC_POS    (28U)
+#define GLB_SWRST_S1AC_LEN    (1U)
+#define GLB_SWRST_S1AC_MSK    (((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS)
+#define GLB_SWRST_S1AC_UMSK   (~(((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS))
+#define GLB_SWRST_S1AD        GLB_SWRST_S1AD
+#define GLB_SWRST_S1AD_POS    (29U)
+#define GLB_SWRST_S1AD_LEN    (1U)
+#define GLB_SWRST_S1AD_MSK    (((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS)
+#define GLB_SWRST_S1AD_UMSK   (~(((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS))
+#define GLB_SWRST_S1AE        GLB_SWRST_S1AE
+#define GLB_SWRST_S1AE_POS    (30U)
+#define GLB_SWRST_S1AE_LEN    (1U)
+#define GLB_SWRST_S1AE_MSK    (((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS)
+#define GLB_SWRST_S1AE_UMSK   (~(((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS))
+#define GLB_SWRST_S1AF        GLB_SWRST_S1AF
+#define GLB_SWRST_S1AF_POS    (31U)
+#define GLB_SWRST_S1AF_LEN    (1U)
+#define GLB_SWRST_S1AF_MSK    (((1U << GLB_SWRST_S1AF_LEN) - 1) << GLB_SWRST_S1AF_POS)
+#define GLB_SWRST_S1AF_UMSK   (~(((1U << GLB_SWRST_S1AF_LEN) - 1) << GLB_SWRST_S1AF_POS))
+
+/* 0x548 : swrst_cfg2 */
+#define GLB_SWRST_CFG2_OFFSET         (0x548)
+#define GLB_REG_CTRL_PWRON_RST        GLB_REG_CTRL_PWRON_RST
+#define GLB_REG_CTRL_PWRON_RST_POS    (0U)
+#define GLB_REG_CTRL_PWRON_RST_LEN    (1U)
+#define GLB_REG_CTRL_PWRON_RST_MSK    (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
+#define GLB_REG_CTRL_PWRON_RST_UMSK   (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
+#define GLB_REG_CTRL_CPU_RESET        GLB_REG_CTRL_CPU_RESET
+#define GLB_REG_CTRL_CPU_RESET_POS    (1U)
+#define GLB_REG_CTRL_CPU_RESET_LEN    (1U)
+#define GLB_REG_CTRL_CPU_RESET_MSK    (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
+#define GLB_REG_CTRL_CPU_RESET_UMSK   (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
+#define GLB_REG_CTRL_SYS_RESET        GLB_REG_CTRL_SYS_RESET
+#define GLB_REG_CTRL_SYS_RESET_POS    (2U)
+#define GLB_REG_CTRL_SYS_RESET_LEN    (1U)
+#define GLB_REG_CTRL_SYS_RESET_MSK    (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
+#define GLB_REG_CTRL_SYS_RESET_UMSK   (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
+#define GLB_REG_CTRL_PICO_RESET       GLB_REG_CTRL_PICO_RESET
+#define GLB_REG_CTRL_PICO_RESET_POS   (3U)
+#define GLB_REG_CTRL_PICO_RESET_LEN   (1U)
+#define GLB_REG_CTRL_PICO_RESET_MSK   (((1U << GLB_REG_CTRL_PICO_RESET_LEN) - 1) << GLB_REG_CTRL_PICO_RESET_POS)
+#define GLB_REG_CTRL_PICO_RESET_UMSK  (~(((1U << GLB_REG_CTRL_PICO_RESET_LEN) - 1) << GLB_REG_CTRL_PICO_RESET_POS))
+#define GLB_REG_CTRL_CPU2_RESET       GLB_REG_CTRL_CPU2_RESET
+#define GLB_REG_CTRL_CPU2_RESET_POS   (4U)
+#define GLB_REG_CTRL_CPU2_RESET_LEN   (1U)
+#define GLB_REG_CTRL_CPU2_RESET_MSK   (((1U << GLB_REG_CTRL_CPU2_RESET_LEN) - 1) << GLB_REG_CTRL_CPU2_RESET_POS)
+#define GLB_REG_CTRL_CPU2_RESET_UMSK  (~(((1U << GLB_REG_CTRL_CPU2_RESET_LEN) - 1) << GLB_REG_CTRL_CPU2_RESET_POS))
+#define GLB_REG_CTRL_CHIP_RESET       GLB_REG_CTRL_CHIP_RESET
+#define GLB_REG_CTRL_CHIP_RESET_POS   (5U)
+#define GLB_REG_CTRL_CHIP_RESET_LEN   (1U)
+#define GLB_REG_CTRL_CHIP_RESET_MSK   (((1U << GLB_REG_CTRL_CHIP_RESET_LEN) - 1) << GLB_REG_CTRL_CHIP_RESET_POS)
+#define GLB_REG_CTRL_CHIP_RESET_UMSK  (~(((1U << GLB_REG_CTRL_CHIP_RESET_LEN) - 1) << GLB_REG_CTRL_CHIP_RESET_POS))
+#define GLB_PKA_CLK_SEL               GLB_PKA_CLK_SEL
+#define GLB_PKA_CLK_SEL_POS           (24U)
+#define GLB_PKA_CLK_SEL_LEN           (1U)
+#define GLB_PKA_CLK_SEL_MSK           (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
+#define GLB_PKA_CLK_SEL_UMSK          (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
+#define GLB_REG_CTRL_RESET_DUMMY      GLB_REG_CTRL_RESET_DUMMY
+#define GLB_REG_CTRL_RESET_DUMMY_POS  (28U)
+#define GLB_REG_CTRL_RESET_DUMMY_LEN  (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_MSK  (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
+#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS))
+
+/* 0x54C : Disable hreset */
+#define GLB_SWRST_CFG3_OFFSET (0x54C)
+#define GLB_DISRST_S12        GLB_DISRST_S12
+#define GLB_DISRST_S12_POS    (2U)
+#define GLB_DISRST_S12_LEN    (1U)
+#define GLB_DISRST_S12_MSK    (((1U << GLB_DISRST_S12_LEN) - 1) << GLB_DISRST_S12_POS)
+#define GLB_DISRST_S12_UMSK   (~(((1U << GLB_DISRST_S12_LEN) - 1) << GLB_DISRST_S12_POS))
+#define GLB_DISRST_S14        GLB_DISRST_S14
+#define GLB_DISRST_S14_POS    (4U)
+#define GLB_DISRST_S14_LEN    (1U)
+#define GLB_DISRST_S14_MSK    (((1U << GLB_DISRST_S14_LEN) - 1) << GLB_DISRST_S14_POS)
+#define GLB_DISRST_S14_UMSK   (~(((1U << GLB_DISRST_S14_LEN) - 1) << GLB_DISRST_S14_POS))
+#define GLB_DISRST_S18        GLB_DISRST_S18
+#define GLB_DISRST_S18_POS    (8U)
+#define GLB_DISRST_S18_LEN    (1U)
+#define GLB_DISRST_S18_MSK    (((1U << GLB_DISRST_S18_LEN) - 1) << GLB_DISRST_S18_POS)
+#define GLB_DISRST_S18_UMSK   (~(((1U << GLB_DISRST_S18_LEN) - 1) << GLB_DISRST_S18_POS))
+#define GLB_DISRST_S1B        GLB_DISRST_S1B
+#define GLB_DISRST_S1B_POS    (11U)
+#define GLB_DISRST_S1B_LEN    (1U)
+#define GLB_DISRST_S1B_MSK    (((1U << GLB_DISRST_S1B_LEN) - 1) << GLB_DISRST_S1B_POS)
+#define GLB_DISRST_S1B_UMSK   (~(((1U << GLB_DISRST_S1B_LEN) - 1) << GLB_DISRST_S1B_POS))
+#define GLB_DISRST_S1A0       GLB_DISRST_S1A0
+#define GLB_DISRST_S1A0_POS   (16U)
+#define GLB_DISRST_S1A0_LEN   (1U)
+#define GLB_DISRST_S1A0_MSK   (((1U << GLB_DISRST_S1A0_LEN) - 1) << GLB_DISRST_S1A0_POS)
+#define GLB_DISRST_S1A0_UMSK  (~(((1U << GLB_DISRST_S1A0_LEN) - 1) << GLB_DISRST_S1A0_POS))
+#define GLB_DISRST_S1A1       GLB_DISRST_S1A1
+#define GLB_DISRST_S1A1_POS   (17U)
+#define GLB_DISRST_S1A1_LEN   (1U)
+#define GLB_DISRST_S1A1_MSK   (((1U << GLB_DISRST_S1A1_LEN) - 1) << GLB_DISRST_S1A1_POS)
+#define GLB_DISRST_S1A1_UMSK  (~(((1U << GLB_DISRST_S1A1_LEN) - 1) << GLB_DISRST_S1A1_POS))
+#define GLB_DISRST_S1A2       GLB_DISRST_S1A2
+#define GLB_DISRST_S1A2_POS   (18U)
+#define GLB_DISRST_S1A2_LEN   (1U)
+#define GLB_DISRST_S1A2_MSK   (((1U << GLB_DISRST_S1A2_LEN) - 1) << GLB_DISRST_S1A2_POS)
+#define GLB_DISRST_S1A2_UMSK  (~(((1U << GLB_DISRST_S1A2_LEN) - 1) << GLB_DISRST_S1A2_POS))
+#define GLB_DISRST_S1A3       GLB_DISRST_S1A3
+#define GLB_DISRST_S1A3_POS   (19U)
+#define GLB_DISRST_S1A3_LEN   (1U)
+#define GLB_DISRST_S1A3_MSK   (((1U << GLB_DISRST_S1A3_LEN) - 1) << GLB_DISRST_S1A3_POS)
+#define GLB_DISRST_S1A3_UMSK  (~(((1U << GLB_DISRST_S1A3_LEN) - 1) << GLB_DISRST_S1A3_POS))
+#define GLB_DISRST_S1A4       GLB_DISRST_S1A4
+#define GLB_DISRST_S1A4_POS   (20U)
+#define GLB_DISRST_S1A4_LEN   (1U)
+#define GLB_DISRST_S1A4_MSK   (((1U << GLB_DISRST_S1A4_LEN) - 1) << GLB_DISRST_S1A4_POS)
+#define GLB_DISRST_S1A4_UMSK  (~(((1U << GLB_DISRST_S1A4_LEN) - 1) << GLB_DISRST_S1A4_POS))
+#define GLB_DISRST_S1A5       GLB_DISRST_S1A5
+#define GLB_DISRST_S1A5_POS   (21U)
+#define GLB_DISRST_S1A5_LEN   (1U)
+#define GLB_DISRST_S1A5_MSK   (((1U << GLB_DISRST_S1A5_LEN) - 1) << GLB_DISRST_S1A5_POS)
+#define GLB_DISRST_S1A5_UMSK  (~(((1U << GLB_DISRST_S1A5_LEN) - 1) << GLB_DISRST_S1A5_POS))
+#define GLB_DISRST_S1A6       GLB_DISRST_S1A6
+#define GLB_DISRST_S1A6_POS   (22U)
+#define GLB_DISRST_S1A6_LEN   (1U)
+#define GLB_DISRST_S1A6_MSK   (((1U << GLB_DISRST_S1A6_LEN) - 1) << GLB_DISRST_S1A6_POS)
+#define GLB_DISRST_S1A6_UMSK  (~(((1U << GLB_DISRST_S1A6_LEN) - 1) << GLB_DISRST_S1A6_POS))
+#define GLB_DISRST_S1A7       GLB_DISRST_S1A7
+#define GLB_DISRST_S1A7_POS   (23U)
+#define GLB_DISRST_S1A7_LEN   (1U)
+#define GLB_DISRST_S1A7_MSK   (((1U << GLB_DISRST_S1A7_LEN) - 1) << GLB_DISRST_S1A7_POS)
+#define GLB_DISRST_S1A7_UMSK  (~(((1U << GLB_DISRST_S1A7_LEN) - 1) << GLB_DISRST_S1A7_POS))
+#define GLB_DISRST_S1A8       GLB_DISRST_S1A8
+#define GLB_DISRST_S1A8_POS   (24U)
+#define GLB_DISRST_S1A8_LEN   (1U)
+#define GLB_DISRST_S1A8_MSK   (((1U << GLB_DISRST_S1A8_LEN) - 1) << GLB_DISRST_S1A8_POS)
+#define GLB_DISRST_S1A8_UMSK  (~(((1U << GLB_DISRST_S1A8_LEN) - 1) << GLB_DISRST_S1A8_POS))
+#define GLB_DISRST_S1A9       GLB_DISRST_S1A9
+#define GLB_DISRST_S1A9_POS   (25U)
+#define GLB_DISRST_S1A9_LEN   (1U)
+#define GLB_DISRST_S1A9_MSK   (((1U << GLB_DISRST_S1A9_LEN) - 1) << GLB_DISRST_S1A9_POS)
+#define GLB_DISRST_S1A9_UMSK  (~(((1U << GLB_DISRST_S1A9_LEN) - 1) << GLB_DISRST_S1A9_POS))
+#define GLB_DISRST_S1AA       GLB_DISRST_S1AA
+#define GLB_DISRST_S1AA_POS   (26U)
+#define GLB_DISRST_S1AA_LEN   (1U)
+#define GLB_DISRST_S1AA_MSK   (((1U << GLB_DISRST_S1AA_LEN) - 1) << GLB_DISRST_S1AA_POS)
+#define GLB_DISRST_S1AA_UMSK  (~(((1U << GLB_DISRST_S1AA_LEN) - 1) << GLB_DISRST_S1AA_POS))
+
+/* 0x580 : cgen_m */
+#define GLB_CGEN_CFG0_OFFSET (0x580)
+#define GLB_CGEN_M_CPU       GLB_CGEN_M_CPU
+#define GLB_CGEN_M_CPU_POS   (0U)
+#define GLB_CGEN_M_CPU_LEN   (1U)
+#define GLB_CGEN_M_CPU_MSK   (((1U << GLB_CGEN_M_CPU_LEN) - 1) << GLB_CGEN_M_CPU_POS)
+#define GLB_CGEN_M_CPU_UMSK  (~(((1U << GLB_CGEN_M_CPU_LEN) - 1) << GLB_CGEN_M_CPU_POS))
+#define GLB_CGEN_M_SDU       GLB_CGEN_M_SDU
+#define GLB_CGEN_M_SDU_POS   (1U)
+#define GLB_CGEN_M_SDU_LEN   (1U)
+#define GLB_CGEN_M_SDU_MSK   (((1U << GLB_CGEN_M_SDU_LEN) - 1) << GLB_CGEN_M_SDU_POS)
+#define GLB_CGEN_M_SDU_UMSK  (~(((1U << GLB_CGEN_M_SDU_LEN) - 1) << GLB_CGEN_M_SDU_POS))
+#define GLB_CGEN_M_SEC       GLB_CGEN_M_SEC
+#define GLB_CGEN_M_SEC_POS   (2U)
+#define GLB_CGEN_M_SEC_LEN   (1U)
+#define GLB_CGEN_M_SEC_MSK   (((1U << GLB_CGEN_M_SEC_LEN) - 1) << GLB_CGEN_M_SEC_POS)
+#define GLB_CGEN_M_SEC_UMSK  (~(((1U << GLB_CGEN_M_SEC_LEN) - 1) << GLB_CGEN_M_SEC_POS))
+#define GLB_CGEN_M_DMA       GLB_CGEN_M_DMA
+#define GLB_CGEN_M_DMA_POS   (3U)
+#define GLB_CGEN_M_DMA_LEN   (1U)
+#define GLB_CGEN_M_DMA_MSK   (((1U << GLB_CGEN_M_DMA_LEN) - 1) << GLB_CGEN_M_DMA_POS)
+#define GLB_CGEN_M_DMA_UMSK  (~(((1U << GLB_CGEN_M_DMA_LEN) - 1) << GLB_CGEN_M_DMA_POS))
+#define GLB_CGEN_M_CCI       GLB_CGEN_M_CCI
+#define GLB_CGEN_M_CCI_POS   (4U)
+#define GLB_CGEN_M_CCI_LEN   (1U)
+#define GLB_CGEN_M_CCI_MSK   (((1U << GLB_CGEN_M_CCI_LEN) - 1) << GLB_CGEN_M_CCI_POS)
+#define GLB_CGEN_M_CCI_UMSK  (~(((1U << GLB_CGEN_M_CCI_LEN) - 1) << GLB_CGEN_M_CCI_POS))
+
+/* 0x584 : cgen_s1a + cgen_s1 */
+#define GLB_CGEN_CFG1_OFFSET     (0x584)
+#define GLB_CGEN_S1_RSVD0        GLB_CGEN_S1_RSVD0
+#define GLB_CGEN_S1_RSVD0_POS    (0U)
+#define GLB_CGEN_S1_RSVD0_LEN    (1U)
+#define GLB_CGEN_S1_RSVD0_MSK    (((1U << GLB_CGEN_S1_RSVD0_LEN) - 1) << GLB_CGEN_S1_RSVD0_POS)
+#define GLB_CGEN_S1_RSVD0_UMSK   (~(((1U << GLB_CGEN_S1_RSVD0_LEN) - 1) << GLB_CGEN_S1_RSVD0_POS))
+#define GLB_CGEN_S1_GPIP         GLB_CGEN_S1_GPIP
+#define GLB_CGEN_S1_GPIP_POS     (2U)
+#define GLB_CGEN_S1_GPIP_LEN     (1U)
+#define GLB_CGEN_S1_GPIP_MSK     (((1U << GLB_CGEN_S1_GPIP_LEN) - 1) << GLB_CGEN_S1_GPIP_POS)
+#define GLB_CGEN_S1_GPIP_UMSK    (~(((1U << GLB_CGEN_S1_GPIP_LEN) - 1) << GLB_CGEN_S1_GPIP_POS))
+#define GLB_CGEN_S1_SEC_DBG      GLB_CGEN_S1_SEC_DBG
+#define GLB_CGEN_S1_SEC_DBG_POS  (3U)
+#define GLB_CGEN_S1_SEC_DBG_LEN  (1U)
+#define GLB_CGEN_S1_SEC_DBG_MSK  (((1U << GLB_CGEN_S1_SEC_DBG_LEN) - 1) << GLB_CGEN_S1_SEC_DBG_POS)
+#define GLB_CGEN_S1_SEC_DBG_UMSK (~(((1U << GLB_CGEN_S1_SEC_DBG_LEN) - 1) << GLB_CGEN_S1_SEC_DBG_POS))
+#define GLB_CGEN_S1_SEC_ENG      GLB_CGEN_S1_SEC_ENG
+#define GLB_CGEN_S1_SEC_ENG_POS  (4U)
+#define GLB_CGEN_S1_SEC_ENG_LEN  (1U)
+#define GLB_CGEN_S1_SEC_ENG_MSK  (((1U << GLB_CGEN_S1_SEC_ENG_LEN) - 1) << GLB_CGEN_S1_SEC_ENG_POS)
+#define GLB_CGEN_S1_SEC_ENG_UMSK (~(((1U << GLB_CGEN_S1_SEC_ENG_LEN) - 1) << GLB_CGEN_S1_SEC_ENG_POS))
+#define GLB_CGEN_S1_TZ           GLB_CGEN_S1_TZ
+#define GLB_CGEN_S1_TZ_POS       (5U)
+#define GLB_CGEN_S1_TZ_LEN       (1U)
+#define GLB_CGEN_S1_TZ_MSK       (((1U << GLB_CGEN_S1_TZ_LEN) - 1) << GLB_CGEN_S1_TZ_POS)
+#define GLB_CGEN_S1_TZ_UMSK      (~(((1U << GLB_CGEN_S1_TZ_LEN) - 1) << GLB_CGEN_S1_TZ_POS))
+#define GLB_CGEN_S1_RSVD6        GLB_CGEN_S1_RSVD6
+#define GLB_CGEN_S1_RSVD6_POS    (6U)
+#define GLB_CGEN_S1_RSVD6_LEN    (1U)
+#define GLB_CGEN_S1_RSVD6_MSK    (((1U << GLB_CGEN_S1_RSVD6_LEN) - 1) << GLB_CGEN_S1_RSVD6_POS)
+#define GLB_CGEN_S1_RSVD6_UMSK   (~(((1U << GLB_CGEN_S1_RSVD6_LEN) - 1) << GLB_CGEN_S1_RSVD6_POS))
+#define GLB_CGEN_S1_EF_CTRL      GLB_CGEN_S1_EF_CTRL
+#define GLB_CGEN_S1_EF_CTRL_POS  (7U)
+#define GLB_CGEN_S1_EF_CTRL_LEN  (1U)
+#define GLB_CGEN_S1_EF_CTRL_MSK  (((1U << GLB_CGEN_S1_EF_CTRL_LEN) - 1) << GLB_CGEN_S1_EF_CTRL_POS)
+#define GLB_CGEN_S1_EF_CTRL_UMSK (~(((1U << GLB_CGEN_S1_EF_CTRL_LEN) - 1) << GLB_CGEN_S1_EF_CTRL_POS))
+#define GLB_CGEN_S1_RSVD8        GLB_CGEN_S1_RSVD8
+#define GLB_CGEN_S1_RSVD8_POS    (8U)
+#define GLB_CGEN_S1_RSVD8_LEN    (1U)
+#define GLB_CGEN_S1_RSVD8_MSK    (((1U << GLB_CGEN_S1_RSVD8_LEN) - 1) << GLB_CGEN_S1_RSVD8_POS)
+#define GLB_CGEN_S1_RSVD8_UMSK   (~(((1U << GLB_CGEN_S1_RSVD8_LEN) - 1) << GLB_CGEN_S1_RSVD8_POS))
+#define GLB_CGEN_S1_RSVD9        GLB_CGEN_S1_RSVD9
+#define GLB_CGEN_S1_RSVD9_POS    (9U)
+#define GLB_CGEN_S1_RSVD9_LEN    (1U)
+#define GLB_CGEN_S1_RSVD9_MSK    (((1U << GLB_CGEN_S1_RSVD9_LEN) - 1) << GLB_CGEN_S1_RSVD9_POS)
+#define GLB_CGEN_S1_RSVD9_UMSK   (~(((1U << GLB_CGEN_S1_RSVD9_LEN) - 1) << GLB_CGEN_S1_RSVD9_POS))
+#define GLB_CGEN_S1_RSVD10       GLB_CGEN_S1_RSVD10
+#define GLB_CGEN_S1_RSVD10_POS   (10U)
+#define GLB_CGEN_S1_RSVD10_LEN   (1U)
+#define GLB_CGEN_S1_RSVD10_MSK   (((1U << GLB_CGEN_S1_RSVD10_LEN) - 1) << GLB_CGEN_S1_RSVD10_POS)
+#define GLB_CGEN_S1_RSVD10_UMSK  (~(((1U << GLB_CGEN_S1_RSVD10_LEN) - 1) << GLB_CGEN_S1_RSVD10_POS))
+#define GLB_CGEN_S1_SF_CTRL      GLB_CGEN_S1_SF_CTRL
+#define GLB_CGEN_S1_SF_CTRL_POS  (11U)
+#define GLB_CGEN_S1_SF_CTRL_LEN  (1U)
+#define GLB_CGEN_S1_SF_CTRL_MSK  (((1U << GLB_CGEN_S1_SF_CTRL_LEN) - 1) << GLB_CGEN_S1_SF_CTRL_POS)
+#define GLB_CGEN_S1_SF_CTRL_UMSK (~(((1U << GLB_CGEN_S1_SF_CTRL_LEN) - 1) << GLB_CGEN_S1_SF_CTRL_POS))
+#define GLB_CGEN_S1_DMA          GLB_CGEN_S1_DMA
+#define GLB_CGEN_S1_DMA_POS      (12U)
+#define GLB_CGEN_S1_DMA_LEN      (1U)
+#define GLB_CGEN_S1_DMA_MSK      (((1U << GLB_CGEN_S1_DMA_LEN) - 1) << GLB_CGEN_S1_DMA_POS)
+#define GLB_CGEN_S1_DMA_UMSK     (~(((1U << GLB_CGEN_S1_DMA_LEN) - 1) << GLB_CGEN_S1_DMA_POS))
+#define GLB_CGEN_S1_RSVD13       GLB_CGEN_S1_RSVD13
+#define GLB_CGEN_S1_RSVD13_POS   (13U)
+#define GLB_CGEN_S1_RSVD13_LEN   (1U)
+#define GLB_CGEN_S1_RSVD13_MSK   (((1U << GLB_CGEN_S1_RSVD13_LEN) - 1) << GLB_CGEN_S1_RSVD13_POS)
+#define GLB_CGEN_S1_RSVD13_UMSK  (~(((1U << GLB_CGEN_S1_RSVD13_LEN) - 1) << GLB_CGEN_S1_RSVD13_POS))
+#define GLB_CGEN_S1_RSVD14       GLB_CGEN_S1_RSVD14
+#define GLB_CGEN_S1_RSVD14_POS   (14U)
+#define GLB_CGEN_S1_RSVD14_LEN   (1U)
+#define GLB_CGEN_S1_RSVD14_MSK   (((1U << GLB_CGEN_S1_RSVD14_LEN) - 1) << GLB_CGEN_S1_RSVD14_POS)
+#define GLB_CGEN_S1_RSVD14_UMSK  (~(((1U << GLB_CGEN_S1_RSVD14_LEN) - 1) << GLB_CGEN_S1_RSVD14_POS))
+#define GLB_CGEN_S1_RSVD15       GLB_CGEN_S1_RSVD15
+#define GLB_CGEN_S1_RSVD15_POS   (15U)
+#define GLB_CGEN_S1_RSVD15_LEN   (1U)
+#define GLB_CGEN_S1_RSVD15_MSK   (((1U << GLB_CGEN_S1_RSVD15_LEN) - 1) << GLB_CGEN_S1_RSVD15_POS)
+#define GLB_CGEN_S1_RSVD15_UMSK  (~(((1U << GLB_CGEN_S1_RSVD15_LEN) - 1) << GLB_CGEN_S1_RSVD15_POS))
+#define GLB_CGEN_S1A_UART0       GLB_CGEN_S1A_UART0
+#define GLB_CGEN_S1A_UART0_POS   (16U)
+#define GLB_CGEN_S1A_UART0_LEN   (1U)
+#define GLB_CGEN_S1A_UART0_MSK   (((1U << GLB_CGEN_S1A_UART0_LEN) - 1) << GLB_CGEN_S1A_UART0_POS)
+#define GLB_CGEN_S1A_UART0_UMSK  (~(((1U << GLB_CGEN_S1A_UART0_LEN) - 1) << GLB_CGEN_S1A_UART0_POS))
+#define GLB_CGEN_S1A_UART1       GLB_CGEN_S1A_UART1
+#define GLB_CGEN_S1A_UART1_POS   (17U)
+#define GLB_CGEN_S1A_UART1_LEN   (1U)
+#define GLB_CGEN_S1A_UART1_MSK   (((1U << GLB_CGEN_S1A_UART1_LEN) - 1) << GLB_CGEN_S1A_UART1_POS)
+#define GLB_CGEN_S1A_UART1_UMSK  (~(((1U << GLB_CGEN_S1A_UART1_LEN) - 1) << GLB_CGEN_S1A_UART1_POS))
+#define GLB_CGEN_S1A_SPI         GLB_CGEN_S1A_SPI
+#define GLB_CGEN_S1A_SPI_POS     (18U)
+#define GLB_CGEN_S1A_SPI_LEN     (1U)
+#define GLB_CGEN_S1A_SPI_MSK     (((1U << GLB_CGEN_S1A_SPI_LEN) - 1) << GLB_CGEN_S1A_SPI_POS)
+#define GLB_CGEN_S1A_SPI_UMSK    (~(((1U << GLB_CGEN_S1A_SPI_LEN) - 1) << GLB_CGEN_S1A_SPI_POS))
+#define GLB_CGEN_S1A_I2C         GLB_CGEN_S1A_I2C
+#define GLB_CGEN_S1A_I2C_POS     (19U)
+#define GLB_CGEN_S1A_I2C_LEN     (1U)
+#define GLB_CGEN_S1A_I2C_MSK     (((1U << GLB_CGEN_S1A_I2C_LEN) - 1) << GLB_CGEN_S1A_I2C_POS)
+#define GLB_CGEN_S1A_I2C_UMSK    (~(((1U << GLB_CGEN_S1A_I2C_LEN) - 1) << GLB_CGEN_S1A_I2C_POS))
+#define GLB_CGEN_S1A_PWM         GLB_CGEN_S1A_PWM
+#define GLB_CGEN_S1A_PWM_POS     (20U)
+#define GLB_CGEN_S1A_PWM_LEN     (1U)
+#define GLB_CGEN_S1A_PWM_MSK     (((1U << GLB_CGEN_S1A_PWM_LEN) - 1) << GLB_CGEN_S1A_PWM_POS)
+#define GLB_CGEN_S1A_PWM_UMSK    (~(((1U << GLB_CGEN_S1A_PWM_LEN) - 1) << GLB_CGEN_S1A_PWM_POS))
+#define GLB_CGEN_S1A_TIMER       GLB_CGEN_S1A_TIMER
+#define GLB_CGEN_S1A_TIMER_POS   (21U)
+#define GLB_CGEN_S1A_TIMER_LEN   (1U)
+#define GLB_CGEN_S1A_TIMER_MSK   (((1U << GLB_CGEN_S1A_TIMER_LEN) - 1) << GLB_CGEN_S1A_TIMER_POS)
+#define GLB_CGEN_S1A_TIMER_UMSK  (~(((1U << GLB_CGEN_S1A_TIMER_LEN) - 1) << GLB_CGEN_S1A_TIMER_POS))
+#define GLB_CGEN_S1A_IR          GLB_CGEN_S1A_IR
+#define GLB_CGEN_S1A_IR_POS      (22U)
+#define GLB_CGEN_S1A_IR_LEN      (1U)
+#define GLB_CGEN_S1A_IR_MSK      (((1U << GLB_CGEN_S1A_IR_LEN) - 1) << GLB_CGEN_S1A_IR_POS)
+#define GLB_CGEN_S1A_IR_UMSK     (~(((1U << GLB_CGEN_S1A_IR_LEN) - 1) << GLB_CGEN_S1A_IR_POS))
+#define GLB_CGEN_S1A_CKS         GLB_CGEN_S1A_CKS
+#define GLB_CGEN_S1A_CKS_POS     (23U)
+#define GLB_CGEN_S1A_CKS_LEN     (1U)
+#define GLB_CGEN_S1A_CKS_MSK     (((1U << GLB_CGEN_S1A_CKS_LEN) - 1) << GLB_CGEN_S1A_CKS_POS)
+#define GLB_CGEN_S1A_CKS_UMSK    (~(((1U << GLB_CGEN_S1A_CKS_LEN) - 1) << GLB_CGEN_S1A_CKS_POS))
+#define GLB_CGEN_S1A_DBI         GLB_CGEN_S1A_DBI
+#define GLB_CGEN_S1A_DBI_POS     (24U)
+#define GLB_CGEN_S1A_DBI_LEN     (1U)
+#define GLB_CGEN_S1A_DBI_MSK     (((1U << GLB_CGEN_S1A_DBI_LEN) - 1) << GLB_CGEN_S1A_DBI_POS)
+#define GLB_CGEN_S1A_DBI_UMSK    (~(((1U << GLB_CGEN_S1A_DBI_LEN) - 1) << GLB_CGEN_S1A_DBI_POS))
+#define GLB_CGEN_S1A_I2C1        GLB_CGEN_S1A_I2C1
+#define GLB_CGEN_S1A_I2C1_POS    (25U)
+#define GLB_CGEN_S1A_I2C1_LEN    (1U)
+#define GLB_CGEN_S1A_I2C1_MSK    (((1U << GLB_CGEN_S1A_I2C1_LEN) - 1) << GLB_CGEN_S1A_I2C1_POS)
+#define GLB_CGEN_S1A_I2C1_UMSK   (~(((1U << GLB_CGEN_S1A_I2C1_LEN) - 1) << GLB_CGEN_S1A_I2C1_POS))
+#define GLB_CGEN_S1A_UART2       GLB_CGEN_S1A_UART2
+#define GLB_CGEN_S1A_UART2_POS   (26U)
+#define GLB_CGEN_S1A_UART2_LEN   (1U)
+#define GLB_CGEN_S1A_UART2_MSK   (((1U << GLB_CGEN_S1A_UART2_LEN) - 1) << GLB_CGEN_S1A_UART2_POS)
+#define GLB_CGEN_S1A_UART2_UMSK  (~(((1U << GLB_CGEN_S1A_UART2_LEN) - 1) << GLB_CGEN_S1A_UART2_POS))
+#define GLB_CGEN_S1A_RSVD11      GLB_CGEN_S1A_RSVD11
+#define GLB_CGEN_S1A_RSVD11_POS  (27U)
+#define GLB_CGEN_S1A_RSVD11_LEN  (1U)
+#define GLB_CGEN_S1A_RSVD11_MSK  (((1U << GLB_CGEN_S1A_RSVD11_LEN) - 1) << GLB_CGEN_S1A_RSVD11_POS)
+#define GLB_CGEN_S1A_RSVD11_UMSK (~(((1U << GLB_CGEN_S1A_RSVD11_LEN) - 1) << GLB_CGEN_S1A_RSVD11_POS))
+#define GLB_CGEN_S1A_RSVD12      GLB_CGEN_S1A_RSVD12
+#define GLB_CGEN_S1A_RSVD12_POS  (28U)
+#define GLB_CGEN_S1A_RSVD12_LEN  (1U)
+#define GLB_CGEN_S1A_RSVD12_MSK  (((1U << GLB_CGEN_S1A_RSVD12_LEN) - 1) << GLB_CGEN_S1A_RSVD12_POS)
+#define GLB_CGEN_S1A_RSVD12_UMSK (~(((1U << GLB_CGEN_S1A_RSVD12_LEN) - 1) << GLB_CGEN_S1A_RSVD12_POS))
+#define GLB_CGEN_S1A_RSVD13      GLB_CGEN_S1A_RSVD13
+#define GLB_CGEN_S1A_RSVD13_POS  (29U)
+#define GLB_CGEN_S1A_RSVD13_LEN  (1U)
+#define GLB_CGEN_S1A_RSVD13_MSK  (((1U << GLB_CGEN_S1A_RSVD13_LEN) - 1) << GLB_CGEN_S1A_RSVD13_POS)
+#define GLB_CGEN_S1A_RSVD13_UMSK (~(((1U << GLB_CGEN_S1A_RSVD13_LEN) - 1) << GLB_CGEN_S1A_RSVD13_POS))
+#define GLB_CGEN_S1A_RSVD14      GLB_CGEN_S1A_RSVD14
+#define GLB_CGEN_S1A_RSVD14_POS  (30U)
+#define GLB_CGEN_S1A_RSVD14_LEN  (1U)
+#define GLB_CGEN_S1A_RSVD14_MSK  (((1U << GLB_CGEN_S1A_RSVD14_LEN) - 1) << GLB_CGEN_S1A_RSVD14_POS)
+#define GLB_CGEN_S1A_RSVD14_UMSK (~(((1U << GLB_CGEN_S1A_RSVD14_LEN) - 1) << GLB_CGEN_S1A_RSVD14_POS))
+#define GLB_CGEN_S1A_RSVD15      GLB_CGEN_S1A_RSVD15
+#define GLB_CGEN_S1A_RSVD15_POS  (31U)
+#define GLB_CGEN_S1A_RSVD15_LEN  (1U)
+#define GLB_CGEN_S1A_RSVD15_MSK  (((1U << GLB_CGEN_S1A_RSVD15_LEN) - 1) << GLB_CGEN_S1A_RSVD15_POS)
+#define GLB_CGEN_S1A_RSVD15_UMSK (~(((1U << GLB_CGEN_S1A_RSVD15_LEN) - 1) << GLB_CGEN_S1A_RSVD15_POS))
+
+/* 0x588 : cgen_s1_ext + cgen_s3 */
+#define GLB_CGEN_CFG2_OFFSET             (0x588)
+#define GLB_CGEN_S0                      GLB_CGEN_S0
+#define GLB_CGEN_S0_POS                  (0U)
+#define GLB_CGEN_S0_LEN                  (1U)
+#define GLB_CGEN_S0_MSK                  (((1U << GLB_CGEN_S0_LEN) - 1) << GLB_CGEN_S0_POS)
+#define GLB_CGEN_S0_UMSK                 (~(((1U << GLB_CGEN_S0_LEN) - 1) << GLB_CGEN_S0_POS))
+#define GLB_CGEN_S2_WIFI                 GLB_CGEN_S2_WIFI
+#define GLB_CGEN_S2_WIFI_POS             (4U)
+#define GLB_CGEN_S2_WIFI_LEN             (1U)
+#define GLB_CGEN_S2_WIFI_MSK             (((1U << GLB_CGEN_S2_WIFI_LEN) - 1) << GLB_CGEN_S2_WIFI_POS)
+#define GLB_CGEN_S2_WIFI_UMSK            (~(((1U << GLB_CGEN_S2_WIFI_LEN) - 1) << GLB_CGEN_S2_WIFI_POS))
+#define GLB_CGEN_S3_BT_BLE2              GLB_CGEN_S3_BT_BLE2
+#define GLB_CGEN_S3_BT_BLE2_POS          (10U)
+#define GLB_CGEN_S3_BT_BLE2_LEN          (1U)
+#define GLB_CGEN_S3_BT_BLE2_MSK          (((1U << GLB_CGEN_S3_BT_BLE2_LEN) - 1) << GLB_CGEN_S3_BT_BLE2_POS)
+#define GLB_CGEN_S3_BT_BLE2_UMSK         (~(((1U << GLB_CGEN_S3_BT_BLE2_LEN) - 1) << GLB_CGEN_S3_BT_BLE2_POS))
+#define GLB_CGEN_S3_M1542                GLB_CGEN_S3_M1542
+#define GLB_CGEN_S3_M1542_POS            (11U)
+#define GLB_CGEN_S3_M1542_LEN            (1U)
+#define GLB_CGEN_S3_M1542_MSK            (((1U << GLB_CGEN_S3_M1542_LEN) - 1) << GLB_CGEN_S3_M1542_POS)
+#define GLB_CGEN_S3_M1542_UMSK           (~(((1U << GLB_CGEN_S3_M1542_LEN) - 1) << GLB_CGEN_S3_M1542_POS))
+#define GLB_CGEN_S1_EXT_EMI_MISC         GLB_CGEN_S1_EXT_EMI_MISC
+#define GLB_CGEN_S1_EXT_EMI_MISC_POS     (16U)
+#define GLB_CGEN_S1_EXT_EMI_MISC_LEN     (1U)
+#define GLB_CGEN_S1_EXT_EMI_MISC_MSK     (((1U << GLB_CGEN_S1_EXT_EMI_MISC_LEN) - 1) << GLB_CGEN_S1_EXT_EMI_MISC_POS)
+#define GLB_CGEN_S1_EXT_EMI_MISC_UMSK    (~(((1U << GLB_CGEN_S1_EXT_EMI_MISC_LEN) - 1) << GLB_CGEN_S1_EXT_EMI_MISC_POS))
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL      GLB_CGEN_S1_EXT_PSRAM0_CTRL
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_POS  (17U)
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_LEN  (1U)
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_MSK  (((1U << GLB_CGEN_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM0_CTRL_POS)
+#define GLB_CGEN_S1_EXT_PSRAM0_CTRL_UMSK (~(((1U << GLB_CGEN_S1_EXT_PSRAM0_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM0_CTRL_POS))
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL       GLB_CGEN_S1_EXT_PSRAM_CTRL
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_POS   (18U)
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_LEN   (1U)
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_MSK   (((1U << GLB_CGEN_S1_EXT_PSRAM_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM_CTRL_POS)
+#define GLB_CGEN_S1_EXT_PSRAM_CTRL_UMSK  (~(((1U << GLB_CGEN_S1_EXT_PSRAM_CTRL_LEN) - 1) << GLB_CGEN_S1_EXT_PSRAM_CTRL_POS))
+#define GLB_CGEN_S1_EXT_USB              GLB_CGEN_S1_EXT_USB
+#define GLB_CGEN_S1_EXT_USB_POS          (19U)
+#define GLB_CGEN_S1_EXT_USB_LEN          (1U)
+#define GLB_CGEN_S1_EXT_USB_MSK          (((1U << GLB_CGEN_S1_EXT_USB_LEN) - 1) << GLB_CGEN_S1_EXT_USB_POS)
+#define GLB_CGEN_S1_EXT_USB_UMSK         (~(((1U << GLB_CGEN_S1_EXT_USB_LEN) - 1) << GLB_CGEN_S1_EXT_USB_POS))
+#define GLB_CGEN_S1_EXT_MIX2             GLB_CGEN_S1_EXT_MIX2
+#define GLB_CGEN_S1_EXT_MIX2_POS         (20U)
+#define GLB_CGEN_S1_EXT_MIX2_LEN         (1U)
+#define GLB_CGEN_S1_EXT_MIX2_MSK         (((1U << GLB_CGEN_S1_EXT_MIX2_LEN) - 1) << GLB_CGEN_S1_EXT_MIX2_POS)
+#define GLB_CGEN_S1_EXT_MIX2_UMSK        (~(((1U << GLB_CGEN_S1_EXT_MIX2_LEN) - 1) << GLB_CGEN_S1_EXT_MIX2_POS))
+#define GLB_CGEN_S1_EXT_AUDIO            GLB_CGEN_S1_EXT_AUDIO
+#define GLB_CGEN_S1_EXT_AUDIO_POS        (21U)
+#define GLB_CGEN_S1_EXT_AUDIO_LEN        (1U)
+#define GLB_CGEN_S1_EXT_AUDIO_MSK        (((1U << GLB_CGEN_S1_EXT_AUDIO_LEN) - 1) << GLB_CGEN_S1_EXT_AUDIO_POS)
+#define GLB_CGEN_S1_EXT_AUDIO_UMSK       (~(((1U << GLB_CGEN_S1_EXT_AUDIO_LEN) - 1) << GLB_CGEN_S1_EXT_AUDIO_POS))
+#define GLB_CGEN_S1_EXT_SDH              GLB_CGEN_S1_EXT_SDH
+#define GLB_CGEN_S1_EXT_SDH_POS          (22U)
+#define GLB_CGEN_S1_EXT_SDH_LEN          (1U)
+#define GLB_CGEN_S1_EXT_SDH_MSK          (((1U << GLB_CGEN_S1_EXT_SDH_LEN) - 1) << GLB_CGEN_S1_EXT_SDH_POS)
+#define GLB_CGEN_S1_EXT_SDH_UMSK         (~(((1U << GLB_CGEN_S1_EXT_SDH_LEN) - 1) << GLB_CGEN_S1_EXT_SDH_POS))
+#define GLB_CGEN_S1_EXT_EMAC             GLB_CGEN_S1_EXT_EMAC
+#define GLB_CGEN_S1_EXT_EMAC_POS         (23U)
+#define GLB_CGEN_S1_EXT_EMAC_LEN         (1U)
+#define GLB_CGEN_S1_EXT_EMAC_MSK         (((1U << GLB_CGEN_S1_EXT_EMAC_LEN) - 1) << GLB_CGEN_S1_EXT_EMAC_POS)
+#define GLB_CGEN_S1_EXT_EMAC_UMSK        (~(((1U << GLB_CGEN_S1_EXT_EMAC_LEN) - 1) << GLB_CGEN_S1_EXT_EMAC_POS))
+#define GLB_CGEN_S1_EXT_DMA2             GLB_CGEN_S1_EXT_DMA2
+#define GLB_CGEN_S1_EXT_DMA2_POS         (24U)
+#define GLB_CGEN_S1_EXT_DMA2_LEN         (1U)
+#define GLB_CGEN_S1_EXT_DMA2_MSK         (((1U << GLB_CGEN_S1_EXT_DMA2_LEN) - 1) << GLB_CGEN_S1_EXT_DMA2_POS)
+#define GLB_CGEN_S1_EXT_DMA2_UMSK        (~(((1U << GLB_CGEN_S1_EXT_DMA2_LEN) - 1) << GLB_CGEN_S1_EXT_DMA2_POS))
+#define GLB_CGEN_S1_EXT_PIO              GLB_CGEN_S1_EXT_PIO
+#define GLB_CGEN_S1_EXT_PIO_POS          (25U)
+#define GLB_CGEN_S1_EXT_PIO_LEN          (1U)
+#define GLB_CGEN_S1_EXT_PIO_MSK          (((1U << GLB_CGEN_S1_EXT_PIO_LEN) - 1) << GLB_CGEN_S1_EXT_PIO_POS)
+#define GLB_CGEN_S1_EXT_PIO_UMSK         (~(((1U << GLB_CGEN_S1_EXT_PIO_LEN) - 1) << GLB_CGEN_S1_EXT_PIO_POS))
+#define GLB_CGEN_S1_EXT_RSVD10           GLB_CGEN_S1_EXT_RSVD10
+#define GLB_CGEN_S1_EXT_RSVD10_POS       (26U)
+#define GLB_CGEN_S1_EXT_RSVD10_LEN       (1U)
+#define GLB_CGEN_S1_EXT_RSVD10_MSK       (((1U << GLB_CGEN_S1_EXT_RSVD10_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD10_POS)
+#define GLB_CGEN_S1_EXT_RSVD10_UMSK      (~(((1U << GLB_CGEN_S1_EXT_RSVD10_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD10_POS))
+#define GLB_CGEN_S1_EXT_RSVD11           GLB_CGEN_S1_EXT_RSVD11
+#define GLB_CGEN_S1_EXT_RSVD11_POS       (27U)
+#define GLB_CGEN_S1_EXT_RSVD11_LEN       (1U)
+#define GLB_CGEN_S1_EXT_RSVD11_MSK       (((1U << GLB_CGEN_S1_EXT_RSVD11_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD11_POS)
+#define GLB_CGEN_S1_EXT_RSVD11_UMSK      (~(((1U << GLB_CGEN_S1_EXT_RSVD11_LEN) - 1) << GLB_CGEN_S1_EXT_RSVD11_POS))
+
+/* 0x58C : cgen_cfg3 */
+#define GLB_CGEN_CFG3_OFFSET              (0x58C)
+#define GLB_CGEN_ISP_WIFIPLL_80M          GLB_CGEN_ISP_WIFIPLL_80M
+#define GLB_CGEN_ISP_WIFIPLL_80M_POS      (2U)
+#define GLB_CGEN_ISP_WIFIPLL_80M_LEN      (1U)
+#define GLB_CGEN_ISP_WIFIPLL_80M_MSK      (((1U << GLB_CGEN_ISP_WIFIPLL_80M_LEN) - 1) << GLB_CGEN_ISP_WIFIPLL_80M_POS)
+#define GLB_CGEN_ISP_WIFIPLL_80M_UMSK     (~(((1U << GLB_CGEN_ISP_WIFIPLL_80M_LEN) - 1) << GLB_CGEN_ISP_WIFIPLL_80M_POS))
+#define GLB_CGEN_ISP_AUPLL_DIV5           GLB_CGEN_ISP_AUPLL_DIV5
+#define GLB_CGEN_ISP_AUPLL_DIV5_POS       (3U)
+#define GLB_CGEN_ISP_AUPLL_DIV5_LEN       (1U)
+#define GLB_CGEN_ISP_AUPLL_DIV5_MSK       (((1U << GLB_CGEN_ISP_AUPLL_DIV5_LEN) - 1) << GLB_CGEN_ISP_AUPLL_DIV5_POS)
+#define GLB_CGEN_ISP_AUPLL_DIV5_UMSK      (~(((1U << GLB_CGEN_ISP_AUPLL_DIV5_LEN) - 1) << GLB_CGEN_ISP_AUPLL_DIV5_POS))
+#define GLB_CGEN_ISP_AUPLL_DIV6           GLB_CGEN_ISP_AUPLL_DIV6
+#define GLB_CGEN_ISP_AUPLL_DIV6_POS       (4U)
+#define GLB_CGEN_ISP_AUPLL_DIV6_LEN       (1U)
+#define GLB_CGEN_ISP_AUPLL_DIV6_MSK       (((1U << GLB_CGEN_ISP_AUPLL_DIV6_LEN) - 1) << GLB_CGEN_ISP_AUPLL_DIV6_POS)
+#define GLB_CGEN_ISP_AUPLL_DIV6_UMSK      (~(((1U << GLB_CGEN_ISP_AUPLL_DIV6_LEN) - 1) << GLB_CGEN_ISP_AUPLL_DIV6_POS))
+#define GLB_CGEN_TOP_AUPLL_DIV5           GLB_CGEN_TOP_AUPLL_DIV5
+#define GLB_CGEN_TOP_AUPLL_DIV5_POS       (5U)
+#define GLB_CGEN_TOP_AUPLL_DIV5_LEN       (1U)
+#define GLB_CGEN_TOP_AUPLL_DIV5_MSK       (((1U << GLB_CGEN_TOP_AUPLL_DIV5_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV5_POS)
+#define GLB_CGEN_TOP_AUPLL_DIV5_UMSK      (~(((1U << GLB_CGEN_TOP_AUPLL_DIV5_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV5_POS))
+#define GLB_CGEN_TOP_AUPLL_DIV6           GLB_CGEN_TOP_AUPLL_DIV6
+#define GLB_CGEN_TOP_AUPLL_DIV6_POS       (6U)
+#define GLB_CGEN_TOP_AUPLL_DIV6_LEN       (1U)
+#define GLB_CGEN_TOP_AUPLL_DIV6_MSK       (((1U << GLB_CGEN_TOP_AUPLL_DIV6_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV6_POS)
+#define GLB_CGEN_TOP_AUPLL_DIV6_UMSK      (~(((1U << GLB_CGEN_TOP_AUPLL_DIV6_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV6_POS))
+#define GLB_CGEN_PSRAMB_WIFIPLL_320M      GLB_CGEN_PSRAMB_WIFIPLL_320M
+#define GLB_CGEN_PSRAMB_WIFIPLL_320M_POS  (7U)
+#define GLB_CGEN_PSRAMB_WIFIPLL_320M_LEN  (1U)
+#define GLB_CGEN_PSRAMB_WIFIPLL_320M_MSK  (((1U << GLB_CGEN_PSRAMB_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_PSRAMB_WIFIPLL_320M_POS)
+#define GLB_CGEN_PSRAMB_WIFIPLL_320M_UMSK (~(((1U << GLB_CGEN_PSRAMB_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_PSRAMB_WIFIPLL_320M_POS))
+#define GLB_CGEN_PSRAMB_AUPLL_DIV1        GLB_CGEN_PSRAMB_AUPLL_DIV1
+#define GLB_CGEN_PSRAMB_AUPLL_DIV1_POS    (8U)
+#define GLB_CGEN_PSRAMB_AUPLL_DIV1_LEN    (1U)
+#define GLB_CGEN_PSRAMB_AUPLL_DIV1_MSK    (((1U << GLB_CGEN_PSRAMB_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_PSRAMB_AUPLL_DIV1_POS)
+#define GLB_CGEN_PSRAMB_AUPLL_DIV1_UMSK   (~(((1U << GLB_CGEN_PSRAMB_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_PSRAMB_AUPLL_DIV1_POS))
+#define GLB_CGEN_TOP_WIFIPLL_240M         GLB_CGEN_TOP_WIFIPLL_240M
+#define GLB_CGEN_TOP_WIFIPLL_240M_POS     (13U)
+#define GLB_CGEN_TOP_WIFIPLL_240M_LEN     (1U)
+#define GLB_CGEN_TOP_WIFIPLL_240M_MSK     (((1U << GLB_CGEN_TOP_WIFIPLL_240M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_240M_POS)
+#define GLB_CGEN_TOP_WIFIPLL_240M_UMSK    (~(((1U << GLB_CGEN_TOP_WIFIPLL_240M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_240M_POS))
+#define GLB_CGEN_TOP_WIFIPLL_320M         GLB_CGEN_TOP_WIFIPLL_320M
+#define GLB_CGEN_TOP_WIFIPLL_320M_POS     (14U)
+#define GLB_CGEN_TOP_WIFIPLL_320M_LEN     (1U)
+#define GLB_CGEN_TOP_WIFIPLL_320M_MSK     (((1U << GLB_CGEN_TOP_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_320M_POS)
+#define GLB_CGEN_TOP_WIFIPLL_320M_UMSK    (~(((1U << GLB_CGEN_TOP_WIFIPLL_320M_LEN) - 1) << GLB_CGEN_TOP_WIFIPLL_320M_POS))
+#define GLB_CGEN_TOP_AUPLL_DIV2           GLB_CGEN_TOP_AUPLL_DIV2
+#define GLB_CGEN_TOP_AUPLL_DIV2_POS       (15U)
+#define GLB_CGEN_TOP_AUPLL_DIV2_LEN       (1U)
+#define GLB_CGEN_TOP_AUPLL_DIV2_MSK       (((1U << GLB_CGEN_TOP_AUPLL_DIV2_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV2_POS)
+#define GLB_CGEN_TOP_AUPLL_DIV2_UMSK      (~(((1U << GLB_CGEN_TOP_AUPLL_DIV2_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV2_POS))
+#define GLB_CGEN_TOP_AUPLL_DIV1           GLB_CGEN_TOP_AUPLL_DIV1
+#define GLB_CGEN_TOP_AUPLL_DIV1_POS       (16U)
+#define GLB_CGEN_TOP_AUPLL_DIV1_LEN       (1U)
+#define GLB_CGEN_TOP_AUPLL_DIV1_MSK       (((1U << GLB_CGEN_TOP_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV1_POS)
+#define GLB_CGEN_TOP_AUPLL_DIV1_UMSK      (~(((1U << GLB_CGEN_TOP_AUPLL_DIV1_LEN) - 1) << GLB_CGEN_TOP_AUPLL_DIV1_POS))
+
+/* 0x5C0 : hw_rsv0 */
+#define GLB_HW_RSV0_OFFSET (0x5C0)
+
+/* 0x5C4 : hw_rsv1 */
+#define GLB_HW_RSV1_OFFSET (0x5C4)
+
+/* 0x5C8 : hw_rsv2 */
+#define GLB_HW_RSV2_OFFSET (0x5C8)
+
+/* 0x5CC : hw_rsv3 */
+#define GLB_HW_RSV3_OFFSET (0x5CC)
+
+/* 0x600 : reg_sram_ret */
+#define GLB_SRAM_CFG0_OFFSET      (0x600)
+#define GLB_CR_MCU_CACHE_RET      GLB_CR_MCU_CACHE_RET
+#define GLB_CR_MCU_CACHE_RET_POS  (0U)
+#define GLB_CR_MCU_CACHE_RET_LEN  (2U)
+#define GLB_CR_MCU_CACHE_RET_MSK  (((1U << GLB_CR_MCU_CACHE_RET_LEN) - 1) << GLB_CR_MCU_CACHE_RET_POS)
+#define GLB_CR_MCU_CACHE_RET_UMSK (~(((1U << GLB_CR_MCU_CACHE_RET_LEN) - 1) << GLB_CR_MCU_CACHE_RET_POS))
+#define GLB_CR_MCU_HSRAM_RET      GLB_CR_MCU_HSRAM_RET
+#define GLB_CR_MCU_HSRAM_RET_POS  (2U)
+#define GLB_CR_MCU_HSRAM_RET_LEN  (4U)
+#define GLB_CR_MCU_HSRAM_RET_MSK  (((1U << GLB_CR_MCU_HSRAM_RET_LEN) - 1) << GLB_CR_MCU_HSRAM_RET_POS)
+#define GLB_CR_MCU_HSRAM_RET_UMSK (~(((1U << GLB_CR_MCU_HSRAM_RET_LEN) - 1) << GLB_CR_MCU_HSRAM_RET_POS))
+#define GLB_CR_WB_RAM_RET         GLB_CR_WB_RAM_RET
+#define GLB_CR_WB_RAM_RET_POS     (8U)
+#define GLB_CR_WB_RAM_RET_LEN     (1U)
+#define GLB_CR_WB_RAM_RET_MSK     (((1U << GLB_CR_WB_RAM_RET_LEN) - 1) << GLB_CR_WB_RAM_RET_POS)
+#define GLB_CR_WB_RAM_RET_UMSK    (~(((1U << GLB_CR_WB_RAM_RET_LEN) - 1) << GLB_CR_WB_RAM_RET_POS))
+#define GLB_CR_MISC_RAM_RET       GLB_CR_MISC_RAM_RET
+#define GLB_CR_MISC_RAM_RET_POS   (9U)
+#define GLB_CR_MISC_RAM_RET_LEN   (2U)
+#define GLB_CR_MISC_RAM_RET_MSK   (((1U << GLB_CR_MISC_RAM_RET_LEN) - 1) << GLB_CR_MISC_RAM_RET_POS)
+#define GLB_CR_MISC_RAM_RET_UMSK  (~(((1U << GLB_CR_MISC_RAM_RET_LEN) - 1) << GLB_CR_MISC_RAM_RET_POS))
+
+/* 0x604 : reg_sram_slp */
+#define GLB_SRAM_CFG1_OFFSET      (0x604)
+#define GLB_CR_MCU_CACHE_SLP      GLB_CR_MCU_CACHE_SLP
+#define GLB_CR_MCU_CACHE_SLP_POS  (0U)
+#define GLB_CR_MCU_CACHE_SLP_LEN  (2U)
+#define GLB_CR_MCU_CACHE_SLP_MSK  (((1U << GLB_CR_MCU_CACHE_SLP_LEN) - 1) << GLB_CR_MCU_CACHE_SLP_POS)
+#define GLB_CR_MCU_CACHE_SLP_UMSK (~(((1U << GLB_CR_MCU_CACHE_SLP_LEN) - 1) << GLB_CR_MCU_CACHE_SLP_POS))
+#define GLB_CR_MCU_HSRAM_SLP      GLB_CR_MCU_HSRAM_SLP
+#define GLB_CR_MCU_HSRAM_SLP_POS  (2U)
+#define GLB_CR_MCU_HSRAM_SLP_LEN  (4U)
+#define GLB_CR_MCU_HSRAM_SLP_MSK  (((1U << GLB_CR_MCU_HSRAM_SLP_LEN) - 1) << GLB_CR_MCU_HSRAM_SLP_POS)
+#define GLB_CR_MCU_HSRAM_SLP_UMSK (~(((1U << GLB_CR_MCU_HSRAM_SLP_LEN) - 1) << GLB_CR_MCU_HSRAM_SLP_POS))
+#define GLB_CR_MCU_ROM_SLP        GLB_CR_MCU_ROM_SLP
+#define GLB_CR_MCU_ROM_SLP_POS    (6U)
+#define GLB_CR_MCU_ROM_SLP_LEN    (2U)
+#define GLB_CR_MCU_ROM_SLP_MSK    (((1U << GLB_CR_MCU_ROM_SLP_LEN) - 1) << GLB_CR_MCU_ROM_SLP_POS)
+#define GLB_CR_MCU_ROM_SLP_UMSK   (~(((1U << GLB_CR_MCU_ROM_SLP_LEN) - 1) << GLB_CR_MCU_ROM_SLP_POS))
+#define GLB_CR_WB_RAM_SLP         GLB_CR_WB_RAM_SLP
+#define GLB_CR_WB_RAM_SLP_POS     (8U)
+#define GLB_CR_WB_RAM_SLP_LEN     (1U)
+#define GLB_CR_WB_RAM_SLP_MSK     (((1U << GLB_CR_WB_RAM_SLP_LEN) - 1) << GLB_CR_WB_RAM_SLP_POS)
+#define GLB_CR_WB_RAM_SLP_UMSK    (~(((1U << GLB_CR_WB_RAM_SLP_LEN) - 1) << GLB_CR_WB_RAM_SLP_POS))
+#define GLB_CR_MISC_RAM_SLP       GLB_CR_MISC_RAM_SLP
+#define GLB_CR_MISC_RAM_SLP_POS   (9U)
+#define GLB_CR_MISC_RAM_SLP_LEN   (2U)
+#define GLB_CR_MISC_RAM_SLP_MSK   (((1U << GLB_CR_MISC_RAM_SLP_LEN) - 1) << GLB_CR_MISC_RAM_SLP_POS)
+#define GLB_CR_MISC_RAM_SLP_UMSK  (~(((1U << GLB_CR_MISC_RAM_SLP_LEN) - 1) << GLB_CR_MISC_RAM_SLP_POS))
+
+/* 0x608 : reg_sram_parm */
+#define GLB_SRAM_CFG2_OFFSET       (0x608)
+#define GLB_CR_MCU_CACHE_DVSE      GLB_CR_MCU_CACHE_DVSE
+#define GLB_CR_MCU_CACHE_DVSE_POS  (0U)
+#define GLB_CR_MCU_CACHE_DVSE_LEN  (1U)
+#define GLB_CR_MCU_CACHE_DVSE_MSK  (((1U << GLB_CR_MCU_CACHE_DVSE_LEN) - 1) << GLB_CR_MCU_CACHE_DVSE_POS)
+#define GLB_CR_MCU_CACHE_DVSE_UMSK (~(((1U << GLB_CR_MCU_CACHE_DVSE_LEN) - 1) << GLB_CR_MCU_CACHE_DVSE_POS))
+#define GLB_CR_MCU_HSRAM_DVSE      GLB_CR_MCU_HSRAM_DVSE
+#define GLB_CR_MCU_HSRAM_DVSE_POS  (1U)
+#define GLB_CR_MCU_HSRAM_DVSE_LEN  (1U)
+#define GLB_CR_MCU_HSRAM_DVSE_MSK  (((1U << GLB_CR_MCU_HSRAM_DVSE_LEN) - 1) << GLB_CR_MCU_HSRAM_DVSE_POS)
+#define GLB_CR_MCU_HSRAM_DVSE_UMSK (~(((1U << GLB_CR_MCU_HSRAM_DVSE_LEN) - 1) << GLB_CR_MCU_HSRAM_DVSE_POS))
+#define GLB_CR_MCU_ROM_DVSE        GLB_CR_MCU_ROM_DVSE
+#define GLB_CR_MCU_ROM_DVSE_POS    (2U)
+#define GLB_CR_MCU_ROM_DVSE_LEN    (1U)
+#define GLB_CR_MCU_ROM_DVSE_MSK    (((1U << GLB_CR_MCU_ROM_DVSE_LEN) - 1) << GLB_CR_MCU_ROM_DVSE_POS)
+#define GLB_CR_MCU_ROM_DVSE_UMSK   (~(((1U << GLB_CR_MCU_ROM_DVSE_LEN) - 1) << GLB_CR_MCU_ROM_DVSE_POS))
+#define GLB_CR_WB_RAM_DVSE         GLB_CR_WB_RAM_DVSE
+#define GLB_CR_WB_RAM_DVSE_POS     (3U)
+#define GLB_CR_WB_RAM_DVSE_LEN     (1U)
+#define GLB_CR_WB_RAM_DVSE_MSK     (((1U << GLB_CR_WB_RAM_DVSE_LEN) - 1) << GLB_CR_WB_RAM_DVSE_POS)
+#define GLB_CR_WB_RAM_DVSE_UMSK    (~(((1U << GLB_CR_WB_RAM_DVSE_LEN) - 1) << GLB_CR_WB_RAM_DVSE_POS))
+#define GLB_CR_MISC_RAM_DVSE       GLB_CR_MISC_RAM_DVSE
+#define GLB_CR_MISC_RAM_DVSE_POS   (4U)
+#define GLB_CR_MISC_RAM_DVSE_LEN   (1U)
+#define GLB_CR_MISC_RAM_DVSE_MSK   (((1U << GLB_CR_MISC_RAM_DVSE_LEN) - 1) << GLB_CR_MISC_RAM_DVSE_POS)
+#define GLB_CR_MISC_RAM_DVSE_UMSK  (~(((1U << GLB_CR_MISC_RAM_DVSE_LEN) - 1) << GLB_CR_MISC_RAM_DVSE_POS))
+#define GLB_CR_OCRAM_DVSE          GLB_CR_OCRAM_DVSE
+#define GLB_CR_OCRAM_DVSE_POS      (5U)
+#define GLB_CR_OCRAM_DVSE_LEN      (1U)
+#define GLB_CR_OCRAM_DVSE_MSK      (((1U << GLB_CR_OCRAM_DVSE_LEN) - 1) << GLB_CR_OCRAM_DVSE_POS)
+#define GLB_CR_OCRAM_DVSE_UMSK     (~(((1U << GLB_CR_OCRAM_DVSE_LEN) - 1) << GLB_CR_OCRAM_DVSE_POS))
+#define GLB_CR_WRAM_DVSE           GLB_CR_WRAM_DVSE
+#define GLB_CR_WRAM_DVSE_POS       (6U)
+#define GLB_CR_WRAM_DVSE_LEN       (1U)
+#define GLB_CR_WRAM_DVSE_MSK       (((1U << GLB_CR_WRAM_DVSE_LEN) - 1) << GLB_CR_WRAM_DVSE_POS)
+#define GLB_CR_WRAM_DVSE_UMSK      (~(((1U << GLB_CR_WRAM_DVSE_LEN) - 1) << GLB_CR_WRAM_DVSE_POS))
+#define GLB_CR_MCU_CACHE_NAP       GLB_CR_MCU_CACHE_NAP
+#define GLB_CR_MCU_CACHE_NAP_POS   (8U)
+#define GLB_CR_MCU_CACHE_NAP_LEN   (1U)
+#define GLB_CR_MCU_CACHE_NAP_MSK   (((1U << GLB_CR_MCU_CACHE_NAP_LEN) - 1) << GLB_CR_MCU_CACHE_NAP_POS)
+#define GLB_CR_MCU_CACHE_NAP_UMSK  (~(((1U << GLB_CR_MCU_CACHE_NAP_LEN) - 1) << GLB_CR_MCU_CACHE_NAP_POS))
+#define GLB_CR_MCU_HSRAM_NAP       GLB_CR_MCU_HSRAM_NAP
+#define GLB_CR_MCU_HSRAM_NAP_POS   (9U)
+#define GLB_CR_MCU_HSRAM_NAP_LEN   (1U)
+#define GLB_CR_MCU_HSRAM_NAP_MSK   (((1U << GLB_CR_MCU_HSRAM_NAP_LEN) - 1) << GLB_CR_MCU_HSRAM_NAP_POS)
+#define GLB_CR_MCU_HSRAM_NAP_UMSK  (~(((1U << GLB_CR_MCU_HSRAM_NAP_LEN) - 1) << GLB_CR_MCU_HSRAM_NAP_POS))
+#define GLB_CR_WB_RAM_NAP          GLB_CR_WB_RAM_NAP
+#define GLB_CR_WB_RAM_NAP_POS      (11U)
+#define GLB_CR_WB_RAM_NAP_LEN      (1U)
+#define GLB_CR_WB_RAM_NAP_MSK      (((1U << GLB_CR_WB_RAM_NAP_LEN) - 1) << GLB_CR_WB_RAM_NAP_POS)
+#define GLB_CR_WB_RAM_NAP_UMSK     (~(((1U << GLB_CR_WB_RAM_NAP_LEN) - 1) << GLB_CR_WB_RAM_NAP_POS))
+#define GLB_CR_MISC_RAM_NAP        GLB_CR_MISC_RAM_NAP
+#define GLB_CR_MISC_RAM_NAP_POS    (12U)
+#define GLB_CR_MISC_RAM_NAP_LEN    (1U)
+#define GLB_CR_MISC_RAM_NAP_MSK    (((1U << GLB_CR_MISC_RAM_NAP_LEN) - 1) << GLB_CR_MISC_RAM_NAP_POS)
+#define GLB_CR_MISC_RAM_NAP_UMSK   (~(((1U << GLB_CR_MISC_RAM_NAP_LEN) - 1) << GLB_CR_MISC_RAM_NAP_POS))
+#define GLB_CR_OCRAM_NAP           GLB_CR_OCRAM_NAP
+#define GLB_CR_OCRAM_NAP_POS       (13U)
+#define GLB_CR_OCRAM_NAP_LEN       (1U)
+#define GLB_CR_OCRAM_NAP_MSK       (((1U << GLB_CR_OCRAM_NAP_LEN) - 1) << GLB_CR_OCRAM_NAP_POS)
+#define GLB_CR_OCRAM_NAP_UMSK      (~(((1U << GLB_CR_OCRAM_NAP_LEN) - 1) << GLB_CR_OCRAM_NAP_POS))
+#define GLB_CR_WRAM_NAP            GLB_CR_WRAM_NAP
+#define GLB_CR_WRAM_NAP_POS        (14U)
+#define GLB_CR_WRAM_NAP_LEN        (1U)
+#define GLB_CR_WRAM_NAP_MSK        (((1U << GLB_CR_WRAM_NAP_LEN) - 1) << GLB_CR_WRAM_NAP_POS)
+#define GLB_CR_WRAM_NAP_UMSK       (~(((1U << GLB_CR_WRAM_NAP_LEN) - 1) << GLB_CR_WRAM_NAP_POS))
+
+/* 0x60C : sram_cfg3 */
+#define GLB_SRAM_CFG3_OFFSET (0x60C)
+#define GLB_EM_SEL           GLB_EM_SEL
+#define GLB_EM_SEL_POS       (0U)
+#define GLB_EM_SEL_LEN       (4U)
+#define GLB_EM_SEL_MSK       (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
+#define GLB_EM_SEL_UMSK      (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
+
+/* 0x610 : reg_sram_parm2 */
+#define GLB_SRAM_CFG4_OFFSET      (0x610)
+#define GLB_CR_MCU_CACHE_DVS      GLB_CR_MCU_CACHE_DVS
+#define GLB_CR_MCU_CACHE_DVS_POS  (0U)
+#define GLB_CR_MCU_CACHE_DVS_LEN  (4U)
+#define GLB_CR_MCU_CACHE_DVS_MSK  (((1U << GLB_CR_MCU_CACHE_DVS_LEN) - 1) << GLB_CR_MCU_CACHE_DVS_POS)
+#define GLB_CR_MCU_CACHE_DVS_UMSK (~(((1U << GLB_CR_MCU_CACHE_DVS_LEN) - 1) << GLB_CR_MCU_CACHE_DVS_POS))
+#define GLB_CR_MCU_HSRAM_DVS      GLB_CR_MCU_HSRAM_DVS
+#define GLB_CR_MCU_HSRAM_DVS_POS  (4U)
+#define GLB_CR_MCU_HSRAM_DVS_LEN  (4U)
+#define GLB_CR_MCU_HSRAM_DVS_MSK  (((1U << GLB_CR_MCU_HSRAM_DVS_LEN) - 1) << GLB_CR_MCU_HSRAM_DVS_POS)
+#define GLB_CR_MCU_HSRAM_DVS_UMSK (~(((1U << GLB_CR_MCU_HSRAM_DVS_LEN) - 1) << GLB_CR_MCU_HSRAM_DVS_POS))
+#define GLB_CR_MCU_ROM_DVS        GLB_CR_MCU_ROM_DVS
+#define GLB_CR_MCU_ROM_DVS_POS    (8U)
+#define GLB_CR_MCU_ROM_DVS_LEN    (4U)
+#define GLB_CR_MCU_ROM_DVS_MSK    (((1U << GLB_CR_MCU_ROM_DVS_LEN) - 1) << GLB_CR_MCU_ROM_DVS_POS)
+#define GLB_CR_MCU_ROM_DVS_UMSK   (~(((1U << GLB_CR_MCU_ROM_DVS_LEN) - 1) << GLB_CR_MCU_ROM_DVS_POS))
+#define GLB_CR_WB_RAM_DVS         GLB_CR_WB_RAM_DVS
+#define GLB_CR_WB_RAM_DVS_POS     (12U)
+#define GLB_CR_WB_RAM_DVS_LEN     (4U)
+#define GLB_CR_WB_RAM_DVS_MSK     (((1U << GLB_CR_WB_RAM_DVS_LEN) - 1) << GLB_CR_WB_RAM_DVS_POS)
+#define GLB_CR_WB_RAM_DVS_UMSK    (~(((1U << GLB_CR_WB_RAM_DVS_LEN) - 1) << GLB_CR_WB_RAM_DVS_POS))
+#define GLB_CR_MISC_RAM_DVS       GLB_CR_MISC_RAM_DVS
+#define GLB_CR_MISC_RAM_DVS_POS   (16U)
+#define GLB_CR_MISC_RAM_DVS_LEN   (4U)
+#define GLB_CR_MISC_RAM_DVS_MSK   (((1U << GLB_CR_MISC_RAM_DVS_LEN) - 1) << GLB_CR_MISC_RAM_DVS_POS)
+#define GLB_CR_MISC_RAM_DVS_UMSK  (~(((1U << GLB_CR_MISC_RAM_DVS_LEN) - 1) << GLB_CR_MISC_RAM_DVS_POS))
+#define GLB_CR_OCRAM_DVS          GLB_CR_OCRAM_DVS
+#define GLB_CR_OCRAM_DVS_POS      (20U)
+#define GLB_CR_OCRAM_DVS_LEN      (4U)
+#define GLB_CR_OCRAM_DVS_MSK      (((1U << GLB_CR_OCRAM_DVS_LEN) - 1) << GLB_CR_OCRAM_DVS_POS)
+#define GLB_CR_OCRAM_DVS_UMSK     (~(((1U << GLB_CR_OCRAM_DVS_LEN) - 1) << GLB_CR_OCRAM_DVS_POS))
+#define GLB_CR_WRAM_DVS           GLB_CR_WRAM_DVS
+#define GLB_CR_WRAM_DVS_POS       (24U)
+#define GLB_CR_WRAM_DVS_LEN       (4U)
+#define GLB_CR_WRAM_DVS_MSK       (((1U << GLB_CR_WRAM_DVS_LEN) - 1) << GLB_CR_WRAM_DVS_POS)
+#define GLB_CR_WRAM_DVS_UMSK      (~(((1U << GLB_CR_WRAM_DVS_LEN) - 1) << GLB_CR_WRAM_DVS_POS))
+
+/* 0x620 : psram_cfg0 */
+#define GLB_PSRAM_CFG0_OFFSET       (0x620)
+#define GLB_REG_PSRAMB_CLK_EN       GLB_REG_PSRAMB_CLK_EN
+#define GLB_REG_PSRAMB_CLK_EN_POS   (27U)
+#define GLB_REG_PSRAMB_CLK_EN_LEN   (1U)
+#define GLB_REG_PSRAMB_CLK_EN_MSK   (((1U << GLB_REG_PSRAMB_CLK_EN_LEN) - 1) << GLB_REG_PSRAMB_CLK_EN_POS)
+#define GLB_REG_PSRAMB_CLK_EN_UMSK  (~(((1U << GLB_REG_PSRAMB_CLK_EN_LEN) - 1) << GLB_REG_PSRAMB_CLK_EN_POS))
+#define GLB_REG_PSRAMB_CLK_SEL      GLB_REG_PSRAMB_CLK_SEL
+#define GLB_REG_PSRAMB_CLK_SEL_POS  (28U)
+#define GLB_REG_PSRAMB_CLK_SEL_LEN  (1U)
+#define GLB_REG_PSRAMB_CLK_SEL_MSK  (((1U << GLB_REG_PSRAMB_CLK_SEL_LEN) - 1) << GLB_REG_PSRAMB_CLK_SEL_POS)
+#define GLB_REG_PSRAMB_CLK_SEL_UMSK (~(((1U << GLB_REG_PSRAMB_CLK_SEL_LEN) - 1) << GLB_REG_PSRAMB_CLK_SEL_POS))
+#define GLB_REG_PSRAMB_CLK_DIV      GLB_REG_PSRAMB_CLK_DIV
+#define GLB_REG_PSRAMB_CLK_DIV_POS  (30U)
+#define GLB_REG_PSRAMB_CLK_DIV_LEN  (2U)
+#define GLB_REG_PSRAMB_CLK_DIV_MSK  (((1U << GLB_REG_PSRAMB_CLK_DIV_LEN) - 1) << GLB_REG_PSRAMB_CLK_DIV_POS)
+#define GLB_REG_PSRAMB_CLK_DIV_UMSK (~(((1U << GLB_REG_PSRAMB_CLK_DIV_LEN) - 1) << GLB_REG_PSRAMB_CLK_DIV_POS))
+
+/* 0x6F0 : proc_mon */
+#define GLB_PROC_MON_OFFSET          (0x6F0)
+#define GLB_PU_PROC_MON              GLB_PU_PROC_MON
+#define GLB_PU_PROC_MON_POS          (0U)
+#define GLB_PU_PROC_MON_LEN          (1U)
+#define GLB_PU_PROC_MON_MSK          (((1U << GLB_PU_PROC_MON_LEN) - 1) << GLB_PU_PROC_MON_POS)
+#define GLB_PU_PROC_MON_UMSK         (~(((1U << GLB_PU_PROC_MON_LEN) - 1) << GLB_PU_PROC_MON_POS))
+#define GLB_OSC_EN_RVT               GLB_OSC_EN_RVT
+#define GLB_OSC_EN_RVT_POS           (1U)
+#define GLB_OSC_EN_RVT_LEN           (1U)
+#define GLB_OSC_EN_RVT_MSK           (((1U << GLB_OSC_EN_RVT_LEN) - 1) << GLB_OSC_EN_RVT_POS)
+#define GLB_OSC_EN_RVT_UMSK          (~(((1U << GLB_OSC_EN_RVT_LEN) - 1) << GLB_OSC_EN_RVT_POS))
+#define GLB_OSC_EN_LVT               GLB_OSC_EN_LVT
+#define GLB_OSC_EN_LVT_POS           (2U)
+#define GLB_OSC_EN_LVT_LEN           (1U)
+#define GLB_OSC_EN_LVT_MSK           (((1U << GLB_OSC_EN_LVT_LEN) - 1) << GLB_OSC_EN_LVT_POS)
+#define GLB_OSC_EN_LVT_UMSK          (~(((1U << GLB_OSC_EN_LVT_LEN) - 1) << GLB_OSC_EN_LVT_POS))
+#define GLB_OSC_SEL                  GLB_OSC_SEL
+#define GLB_OSC_SEL_POS              (3U)
+#define GLB_OSC_SEL_LEN              (1U)
+#define GLB_OSC_SEL_MSK              (((1U << GLB_OSC_SEL_LEN) - 1) << GLB_OSC_SEL_POS)
+#define GLB_OSC_SEL_UMSK             (~(((1U << GLB_OSC_SEL_LEN) - 1) << GLB_OSC_SEL_POS))
+#define GLB_RSTN_RINGCOUNT           GLB_RSTN_RINGCOUNT
+#define GLB_RSTN_RINGCOUNT_POS       (4U)
+#define GLB_RSTN_RINGCOUNT_LEN       (1U)
+#define GLB_RSTN_RINGCOUNT_MSK       (((1U << GLB_RSTN_RINGCOUNT_LEN) - 1) << GLB_RSTN_RINGCOUNT_POS)
+#define GLB_RSTN_RINGCOUNT_UMSK      (~(((1U << GLB_RSTN_RINGCOUNT_LEN) - 1) << GLB_RSTN_RINGCOUNT_POS))
+#define GLB_RSTN_REFCOUNT            GLB_RSTN_REFCOUNT
+#define GLB_RSTN_REFCOUNT_POS        (5U)
+#define GLB_RSTN_REFCOUNT_LEN        (1U)
+#define GLB_RSTN_REFCOUNT_MSK        (((1U << GLB_RSTN_REFCOUNT_LEN) - 1) << GLB_RSTN_REFCOUNT_POS)
+#define GLB_RSTN_REFCOUNT_UMSK       (~(((1U << GLB_RSTN_REFCOUNT_LEN) - 1) << GLB_RSTN_REFCOUNT_POS))
+#define GLB_REFCOUNT_DIV_ONEHOT      GLB_REFCOUNT_DIV_ONEHOT
+#define GLB_REFCOUNT_DIV_ONEHOT_POS  (8U)
+#define GLB_REFCOUNT_DIV_ONEHOT_LEN  (4U)
+#define GLB_REFCOUNT_DIV_ONEHOT_MSK  (((1U << GLB_REFCOUNT_DIV_ONEHOT_LEN) - 1) << GLB_REFCOUNT_DIV_ONEHOT_POS)
+#define GLB_REFCOUNT_DIV_ONEHOT_UMSK (~(((1U << GLB_REFCOUNT_DIV_ONEHOT_LEN) - 1) << GLB_REFCOUNT_DIV_ONEHOT_POS))
+#define GLB_RING_FREQ                GLB_RING_FREQ
+#define GLB_RING_FREQ_POS            (12U)
+#define GLB_RING_FREQ_LEN            (16U)
+#define GLB_RING_FREQ_MSK            (((1U << GLB_RING_FREQ_LEN) - 1) << GLB_RING_FREQ_POS)
+#define GLB_RING_FREQ_UMSK           (~(((1U << GLB_RING_FREQ_LEN) - 1) << GLB_RING_FREQ_POS))
+#define GLB_RING_FREQ_RDY            GLB_RING_FREQ_RDY
+#define GLB_RING_FREQ_RDY_POS        (28U)
+#define GLB_RING_FREQ_RDY_LEN        (1U)
+#define GLB_RING_FREQ_RDY_MSK        (((1U << GLB_RING_FREQ_RDY_LEN) - 1) << GLB_RING_FREQ_RDY_POS)
+#define GLB_RING_FREQ_RDY_UMSK       (~(((1U << GLB_RING_FREQ_RDY_LEN) - 1) << GLB_RING_FREQ_RDY_POS))
+
+/* 0x700 : dll_cfg0 */
+#define GLB_DLL_CFG0_OFFSET (0x700)
+
+/* 0x810 : wifi_pll_cfg0 */
+#define GLB_WIFI_PLL_CFG0_OFFSET      (0x810)
+#define GLB_WIFIPLL_SDM_RSTB          GLB_WIFIPLL_SDM_RSTB
+#define GLB_WIFIPLL_SDM_RSTB_POS      (0U)
+#define GLB_WIFIPLL_SDM_RSTB_LEN      (1U)
+#define GLB_WIFIPLL_SDM_RSTB_MSK      (((1U << GLB_WIFIPLL_SDM_RSTB_LEN) - 1) << GLB_WIFIPLL_SDM_RSTB_POS)
+#define GLB_WIFIPLL_SDM_RSTB_UMSK     (~(((1U << GLB_WIFIPLL_SDM_RSTB_LEN) - 1) << GLB_WIFIPLL_SDM_RSTB_POS))
+#define GLB_WIFIPLL_POSTDIV_RSTB      GLB_WIFIPLL_POSTDIV_RSTB
+#define GLB_WIFIPLL_POSTDIV_RSTB_POS  (1U)
+#define GLB_WIFIPLL_POSTDIV_RSTB_LEN  (1U)
+#define GLB_WIFIPLL_POSTDIV_RSTB_MSK  (((1U << GLB_WIFIPLL_POSTDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_POSTDIV_RSTB_POS)
+#define GLB_WIFIPLL_POSTDIV_RSTB_UMSK (~(((1U << GLB_WIFIPLL_POSTDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_POSTDIV_RSTB_POS))
+#define GLB_WIFIPLL_FBDV_RSTB         GLB_WIFIPLL_FBDV_RSTB
+#define GLB_WIFIPLL_FBDV_RSTB_POS     (2U)
+#define GLB_WIFIPLL_FBDV_RSTB_LEN     (1U)
+#define GLB_WIFIPLL_FBDV_RSTB_MSK     (((1U << GLB_WIFIPLL_FBDV_RSTB_LEN) - 1) << GLB_WIFIPLL_FBDV_RSTB_POS)
+#define GLB_WIFIPLL_FBDV_RSTB_UMSK    (~(((1U << GLB_WIFIPLL_FBDV_RSTB_LEN) - 1) << GLB_WIFIPLL_FBDV_RSTB_POS))
+#define GLB_WIFIPLL_REFDIV_RSTB       GLB_WIFIPLL_REFDIV_RSTB
+#define GLB_WIFIPLL_REFDIV_RSTB_POS   (3U)
+#define GLB_WIFIPLL_REFDIV_RSTB_LEN   (1U)
+#define GLB_WIFIPLL_REFDIV_RSTB_MSK   (((1U << GLB_WIFIPLL_REFDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_REFDIV_RSTB_POS)
+#define GLB_WIFIPLL_REFDIV_RSTB_UMSK  (~(((1U << GLB_WIFIPLL_REFDIV_RSTB_LEN) - 1) << GLB_WIFIPLL_REFDIV_RSTB_POS))
+#define GLB_PU_WIFIPLL_CLKTREE        GLB_PU_WIFIPLL_CLKTREE
+#define GLB_PU_WIFIPLL_CLKTREE_POS    (4U)
+#define GLB_PU_WIFIPLL_CLKTREE_LEN    (1U)
+#define GLB_PU_WIFIPLL_CLKTREE_MSK    (((1U << GLB_PU_WIFIPLL_CLKTREE_LEN) - 1) << GLB_PU_WIFIPLL_CLKTREE_POS)
+#define GLB_PU_WIFIPLL_CLKTREE_UMSK   (~(((1U << GLB_PU_WIFIPLL_CLKTREE_LEN) - 1) << GLB_PU_WIFIPLL_CLKTREE_POS))
+#define GLB_PU_WIFIPLL_POSTDIV        GLB_PU_WIFIPLL_POSTDIV
+#define GLB_PU_WIFIPLL_POSTDIV_POS    (5U)
+#define GLB_PU_WIFIPLL_POSTDIV_LEN    (1U)
+#define GLB_PU_WIFIPLL_POSTDIV_MSK    (((1U << GLB_PU_WIFIPLL_POSTDIV_LEN) - 1) << GLB_PU_WIFIPLL_POSTDIV_POS)
+#define GLB_PU_WIFIPLL_POSTDIV_UMSK   (~(((1U << GLB_PU_WIFIPLL_POSTDIV_LEN) - 1) << GLB_PU_WIFIPLL_POSTDIV_POS))
+#define GLB_PU_WIFIPLL_FBDV           GLB_PU_WIFIPLL_FBDV
+#define GLB_PU_WIFIPLL_FBDV_POS       (6U)
+#define GLB_PU_WIFIPLL_FBDV_LEN       (1U)
+#define GLB_PU_WIFIPLL_FBDV_MSK       (((1U << GLB_PU_WIFIPLL_FBDV_LEN) - 1) << GLB_PU_WIFIPLL_FBDV_POS)
+#define GLB_PU_WIFIPLL_FBDV_UMSK      (~(((1U << GLB_PU_WIFIPLL_FBDV_LEN) - 1) << GLB_PU_WIFIPLL_FBDV_POS))
+#define GLB_PU_WIFIPLL_CLAMP_OP       GLB_PU_WIFIPLL_CLAMP_OP
+#define GLB_PU_WIFIPLL_CLAMP_OP_POS   (7U)
+#define GLB_PU_WIFIPLL_CLAMP_OP_LEN   (1U)
+#define GLB_PU_WIFIPLL_CLAMP_OP_MSK   (((1U << GLB_PU_WIFIPLL_CLAMP_OP_LEN) - 1) << GLB_PU_WIFIPLL_CLAMP_OP_POS)
+#define GLB_PU_WIFIPLL_CLAMP_OP_UMSK  (~(((1U << GLB_PU_WIFIPLL_CLAMP_OP_LEN) - 1) << GLB_PU_WIFIPLL_CLAMP_OP_POS))
+#define GLB_PU_WIFIPLL_PFD            GLB_PU_WIFIPLL_PFD
+#define GLB_PU_WIFIPLL_PFD_POS        (8U)
+#define GLB_PU_WIFIPLL_PFD_LEN        (1U)
+#define GLB_PU_WIFIPLL_PFD_MSK        (((1U << GLB_PU_WIFIPLL_PFD_LEN) - 1) << GLB_PU_WIFIPLL_PFD_POS)
+#define GLB_PU_WIFIPLL_PFD_UMSK       (~(((1U << GLB_PU_WIFIPLL_PFD_LEN) - 1) << GLB_PU_WIFIPLL_PFD_POS))
+#define GLB_PU_WIFIPLL_CP             GLB_PU_WIFIPLL_CP
+#define GLB_PU_WIFIPLL_CP_POS         (9U)
+#define GLB_PU_WIFIPLL_CP_LEN         (1U)
+#define GLB_PU_WIFIPLL_CP_MSK         (((1U << GLB_PU_WIFIPLL_CP_LEN) - 1) << GLB_PU_WIFIPLL_CP_POS)
+#define GLB_PU_WIFIPLL_CP_UMSK        (~(((1U << GLB_PU_WIFIPLL_CP_LEN) - 1) << GLB_PU_WIFIPLL_CP_POS))
+#define GLB_PU_WIFIPLL_SFREG          GLB_PU_WIFIPLL_SFREG
+#define GLB_PU_WIFIPLL_SFREG_POS      (10U)
+#define GLB_PU_WIFIPLL_SFREG_LEN      (1U)
+#define GLB_PU_WIFIPLL_SFREG_MSK      (((1U << GLB_PU_WIFIPLL_SFREG_LEN) - 1) << GLB_PU_WIFIPLL_SFREG_POS)
+#define GLB_PU_WIFIPLL_SFREG_UMSK     (~(((1U << GLB_PU_WIFIPLL_SFREG_LEN) - 1) << GLB_PU_WIFIPLL_SFREG_POS))
+#define GLB_PU_WIFIPLL                GLB_PU_WIFIPLL
+#define GLB_PU_WIFIPLL_POS            (11U)
+#define GLB_PU_WIFIPLL_LEN            (1U)
+#define GLB_PU_WIFIPLL_MSK            (((1U << GLB_PU_WIFIPLL_LEN) - 1) << GLB_PU_WIFIPLL_POS)
+#define GLB_PU_WIFIPLL_UMSK           (~(((1U << GLB_PU_WIFIPLL_LEN) - 1) << GLB_PU_WIFIPLL_POS))
+
+/* 0x814 : wifi_pll_cfg1 */
+#define GLB_WIFI_PLL_CFG1_OFFSET      (0x814)
+#define GLB_WIFIPLL_POSTDIV           GLB_WIFIPLL_POSTDIV
+#define GLB_WIFIPLL_POSTDIV_POS       (0U)
+#define GLB_WIFIPLL_POSTDIV_LEN       (7U)
+#define GLB_WIFIPLL_POSTDIV_MSK       (((1U << GLB_WIFIPLL_POSTDIV_LEN) - 1) << GLB_WIFIPLL_POSTDIV_POS)
+#define GLB_WIFIPLL_POSTDIV_UMSK      (~(((1U << GLB_WIFIPLL_POSTDIV_LEN) - 1) << GLB_WIFIPLL_POSTDIV_POS))
+#define GLB_WIFIPLL_REFDIV_RATIO      GLB_WIFIPLL_REFDIV_RATIO
+#define GLB_WIFIPLL_REFDIV_RATIO_POS  (8U)
+#define GLB_WIFIPLL_REFDIV_RATIO_LEN  (4U)
+#define GLB_WIFIPLL_REFDIV_RATIO_MSK  (((1U << GLB_WIFIPLL_REFDIV_RATIO_LEN) - 1) << GLB_WIFIPLL_REFDIV_RATIO_POS)
+#define GLB_WIFIPLL_REFDIV_RATIO_UMSK (~(((1U << GLB_WIFIPLL_REFDIV_RATIO_LEN) - 1) << GLB_WIFIPLL_REFDIV_RATIO_POS))
+#define GLB_WIFIPLL_REFCLK_SEL        GLB_WIFIPLL_REFCLK_SEL
+#define GLB_WIFIPLL_REFCLK_SEL_POS    (16U)
+#define GLB_WIFIPLL_REFCLK_SEL_LEN    (2U)
+#define GLB_WIFIPLL_REFCLK_SEL_MSK    (((1U << GLB_WIFIPLL_REFCLK_SEL_LEN) - 1) << GLB_WIFIPLL_REFCLK_SEL_POS)
+#define GLB_WIFIPLL_REFCLK_SEL_UMSK   (~(((1U << GLB_WIFIPLL_REFCLK_SEL_LEN) - 1) << GLB_WIFIPLL_REFCLK_SEL_POS))
+#define GLB_WIFIPLL_VG11_SEL          GLB_WIFIPLL_VG11_SEL
+#define GLB_WIFIPLL_VG11_SEL_POS      (20U)
+#define GLB_WIFIPLL_VG11_SEL_LEN      (2U)
+#define GLB_WIFIPLL_VG11_SEL_MSK      (((1U << GLB_WIFIPLL_VG11_SEL_LEN) - 1) << GLB_WIFIPLL_VG11_SEL_POS)
+#define GLB_WIFIPLL_VG11_SEL_UMSK     (~(((1U << GLB_WIFIPLL_VG11_SEL_LEN) - 1) << GLB_WIFIPLL_VG11_SEL_POS))
+#define GLB_WIFIPLL_VG13_SEL          GLB_WIFIPLL_VG13_SEL
+#define GLB_WIFIPLL_VG13_SEL_POS      (24U)
+#define GLB_WIFIPLL_VG13_SEL_LEN      (2U)
+#define GLB_WIFIPLL_VG13_SEL_MSK      (((1U << GLB_WIFIPLL_VG13_SEL_LEN) - 1) << GLB_WIFIPLL_VG13_SEL_POS)
+#define GLB_WIFIPLL_VG13_SEL_UMSK     (~(((1U << GLB_WIFIPLL_VG13_SEL_LEN) - 1) << GLB_WIFIPLL_VG13_SEL_POS))
+
+/* 0x818 : wifi_pll_cfg2 */
+#define GLB_WIFI_PLL_CFG2_OFFSET       (0x818)
+#define GLB_WIFIPLL_SEL_CP_BIAS        GLB_WIFIPLL_SEL_CP_BIAS
+#define GLB_WIFIPLL_SEL_CP_BIAS_POS    (0U)
+#define GLB_WIFIPLL_SEL_CP_BIAS_LEN    (1U)
+#define GLB_WIFIPLL_SEL_CP_BIAS_MSK    (((1U << GLB_WIFIPLL_SEL_CP_BIAS_LEN) - 1) << GLB_WIFIPLL_SEL_CP_BIAS_POS)
+#define GLB_WIFIPLL_SEL_CP_BIAS_UMSK   (~(((1U << GLB_WIFIPLL_SEL_CP_BIAS_LEN) - 1) << GLB_WIFIPLL_SEL_CP_BIAS_POS))
+#define GLB_WIFIPLL_ICP_5U             GLB_WIFIPLL_ICP_5U
+#define GLB_WIFIPLL_ICP_5U_POS         (4U)
+#define GLB_WIFIPLL_ICP_5U_LEN         (2U)
+#define GLB_WIFIPLL_ICP_5U_MSK         (((1U << GLB_WIFIPLL_ICP_5U_LEN) - 1) << GLB_WIFIPLL_ICP_5U_POS)
+#define GLB_WIFIPLL_ICP_5U_UMSK        (~(((1U << GLB_WIFIPLL_ICP_5U_LEN) - 1) << GLB_WIFIPLL_ICP_5U_POS))
+#define GLB_WIFIPLL_ICP_1U             GLB_WIFIPLL_ICP_1U
+#define GLB_WIFIPLL_ICP_1U_POS         (6U)
+#define GLB_WIFIPLL_ICP_1U_LEN         (2U)
+#define GLB_WIFIPLL_ICP_1U_MSK         (((1U << GLB_WIFIPLL_ICP_1U_LEN) - 1) << GLB_WIFIPLL_ICP_1U_POS)
+#define GLB_WIFIPLL_ICP_1U_UMSK        (~(((1U << GLB_WIFIPLL_ICP_1U_LEN) - 1) << GLB_WIFIPLL_ICP_1U_POS))
+#define GLB_WIFIPLL_INT_FRAC_SW        GLB_WIFIPLL_INT_FRAC_SW
+#define GLB_WIFIPLL_INT_FRAC_SW_POS    (8U)
+#define GLB_WIFIPLL_INT_FRAC_SW_LEN    (1U)
+#define GLB_WIFIPLL_INT_FRAC_SW_MSK    (((1U << GLB_WIFIPLL_INT_FRAC_SW_LEN) - 1) << GLB_WIFIPLL_INT_FRAC_SW_POS)
+#define GLB_WIFIPLL_INT_FRAC_SW_UMSK   (~(((1U << GLB_WIFIPLL_INT_FRAC_SW_LEN) - 1) << GLB_WIFIPLL_INT_FRAC_SW_POS))
+#define GLB_WIFIPLL_CP_STARTUP_EN      GLB_WIFIPLL_CP_STARTUP_EN
+#define GLB_WIFIPLL_CP_STARTUP_EN_POS  (9U)
+#define GLB_WIFIPLL_CP_STARTUP_EN_LEN  (1U)
+#define GLB_WIFIPLL_CP_STARTUP_EN_MSK  (((1U << GLB_WIFIPLL_CP_STARTUP_EN_LEN) - 1) << GLB_WIFIPLL_CP_STARTUP_EN_POS)
+#define GLB_WIFIPLL_CP_STARTUP_EN_UMSK (~(((1U << GLB_WIFIPLL_CP_STARTUP_EN_LEN) - 1) << GLB_WIFIPLL_CP_STARTUP_EN_POS))
+#define GLB_WIFIPLL_CP_OPAMP_EN        GLB_WIFIPLL_CP_OPAMP_EN
+#define GLB_WIFIPLL_CP_OPAMP_EN_POS    (10U)
+#define GLB_WIFIPLL_CP_OPAMP_EN_LEN    (1U)
+#define GLB_WIFIPLL_CP_OPAMP_EN_MSK    (((1U << GLB_WIFIPLL_CP_OPAMP_EN_LEN) - 1) << GLB_WIFIPLL_CP_OPAMP_EN_POS)
+#define GLB_WIFIPLL_CP_OPAMP_EN_UMSK   (~(((1U << GLB_WIFIPLL_CP_OPAMP_EN_LEN) - 1) << GLB_WIFIPLL_CP_OPAMP_EN_POS))
+
+/* 0x81C : wifi_pll_cfg3 */
+#define GLB_WIFI_PLL_CFG3_OFFSET  (0x81C)
+#define GLB_WIFIPLL_C4_EN         GLB_WIFIPLL_C4_EN
+#define GLB_WIFIPLL_C4_EN_POS     (0U)
+#define GLB_WIFIPLL_C4_EN_LEN     (1U)
+#define GLB_WIFIPLL_C4_EN_MSK     (((1U << GLB_WIFIPLL_C4_EN_LEN) - 1) << GLB_WIFIPLL_C4_EN_POS)
+#define GLB_WIFIPLL_C4_EN_UMSK    (~(((1U << GLB_WIFIPLL_C4_EN_LEN) - 1) << GLB_WIFIPLL_C4_EN_POS))
+#define GLB_WIFIPLL_R4            GLB_WIFIPLL_R4
+#define GLB_WIFIPLL_R4_POS        (4U)
+#define GLB_WIFIPLL_R4_LEN        (2U)
+#define GLB_WIFIPLL_R4_MSK        (((1U << GLB_WIFIPLL_R4_LEN) - 1) << GLB_WIFIPLL_R4_POS)
+#define GLB_WIFIPLL_R4_UMSK       (~(((1U << GLB_WIFIPLL_R4_LEN) - 1) << GLB_WIFIPLL_R4_POS))
+#define GLB_WIFIPLL_R4_SHORT      GLB_WIFIPLL_R4_SHORT
+#define GLB_WIFIPLL_R4_SHORT_POS  (8U)
+#define GLB_WIFIPLL_R4_SHORT_LEN  (1U)
+#define GLB_WIFIPLL_R4_SHORT_MSK  (((1U << GLB_WIFIPLL_R4_SHORT_LEN) - 1) << GLB_WIFIPLL_R4_SHORT_POS)
+#define GLB_WIFIPLL_R4_SHORT_UMSK (~(((1U << GLB_WIFIPLL_R4_SHORT_LEN) - 1) << GLB_WIFIPLL_R4_SHORT_POS))
+#define GLB_WIFIPLL_C3            GLB_WIFIPLL_C3
+#define GLB_WIFIPLL_C3_POS        (12U)
+#define GLB_WIFIPLL_C3_LEN        (2U)
+#define GLB_WIFIPLL_C3_MSK        (((1U << GLB_WIFIPLL_C3_LEN) - 1) << GLB_WIFIPLL_C3_POS)
+#define GLB_WIFIPLL_C3_UMSK       (~(((1U << GLB_WIFIPLL_C3_LEN) - 1) << GLB_WIFIPLL_C3_POS))
+#define GLB_WIFIPLL_CZ            GLB_WIFIPLL_CZ
+#define GLB_WIFIPLL_CZ_POS        (14U)
+#define GLB_WIFIPLL_CZ_LEN        (2U)
+#define GLB_WIFIPLL_CZ_MSK        (((1U << GLB_WIFIPLL_CZ_LEN) - 1) << GLB_WIFIPLL_CZ_POS)
+#define GLB_WIFIPLL_CZ_UMSK       (~(((1U << GLB_WIFIPLL_CZ_LEN) - 1) << GLB_WIFIPLL_CZ_POS))
+#define GLB_WIFIPLL_RZ            GLB_WIFIPLL_RZ
+#define GLB_WIFIPLL_RZ_POS        (16U)
+#define GLB_WIFIPLL_RZ_LEN        (3U)
+#define GLB_WIFIPLL_RZ_MSK        (((1U << GLB_WIFIPLL_RZ_LEN) - 1) << GLB_WIFIPLL_RZ_POS)
+#define GLB_WIFIPLL_RZ_UMSK       (~(((1U << GLB_WIFIPLL_RZ_LEN) - 1) << GLB_WIFIPLL_RZ_POS))
+
+/* 0x820 : wifi_pll_cfg4 */
+#define GLB_WIFI_PLL_CFG4_OFFSET        (0x820)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK      GLB_WIFIPLL_SEL_SAMPLE_CLK
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_POS  (0U)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_LEN  (2U)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_MSK  (((1U << GLB_WIFIPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_SAMPLE_CLK_POS)
+#define GLB_WIFIPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << GLB_WIFIPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_SAMPLE_CLK_POS))
+#define GLB_WIFIPLL_SEL_FB_CLK          GLB_WIFIPLL_SEL_FB_CLK
+#define GLB_WIFIPLL_SEL_FB_CLK_POS      (4U)
+#define GLB_WIFIPLL_SEL_FB_CLK_LEN      (2U)
+#define GLB_WIFIPLL_SEL_FB_CLK_MSK      (((1U << GLB_WIFIPLL_SEL_FB_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_FB_CLK_POS)
+#define GLB_WIFIPLL_SEL_FB_CLK_UMSK     (~(((1U << GLB_WIFIPLL_SEL_FB_CLK_LEN) - 1) << GLB_WIFIPLL_SEL_FB_CLK_POS))
+#define GLB_WIFIPLL_SDMCLK_SEL          GLB_WIFIPLL_SDMCLK_SEL
+#define GLB_WIFIPLL_SDMCLK_SEL_POS      (8U)
+#define GLB_WIFIPLL_SDMCLK_SEL_LEN      (1U)
+#define GLB_WIFIPLL_SDMCLK_SEL_MSK      (((1U << GLB_WIFIPLL_SDMCLK_SEL_LEN) - 1) << GLB_WIFIPLL_SDMCLK_SEL_POS)
+#define GLB_WIFIPLL_SDMCLK_SEL_UMSK     (~(((1U << GLB_WIFIPLL_SDMCLK_SEL_LEN) - 1) << GLB_WIFIPLL_SDMCLK_SEL_POS))
+
+/* 0x824 : wifi_pll_cfg5 */
+#define GLB_WIFI_PLL_CFG5_OFFSET     (0x824)
+#define GLB_WIFIPLL_VCO_SPEED        GLB_WIFIPLL_VCO_SPEED
+#define GLB_WIFIPLL_VCO_SPEED_POS    (0U)
+#define GLB_WIFIPLL_VCO_SPEED_LEN    (3U)
+#define GLB_WIFIPLL_VCO_SPEED_MSK    (((1U << GLB_WIFIPLL_VCO_SPEED_LEN) - 1) << GLB_WIFIPLL_VCO_SPEED_POS)
+#define GLB_WIFIPLL_VCO_SPEED_UMSK   (~(((1U << GLB_WIFIPLL_VCO_SPEED_LEN) - 1) << GLB_WIFIPLL_VCO_SPEED_POS))
+#define GLB_WIFIPLL_VCO_DIV3_EN      GLB_WIFIPLL_VCO_DIV3_EN
+#define GLB_WIFIPLL_VCO_DIV3_EN_POS  (3U)
+#define GLB_WIFIPLL_VCO_DIV3_EN_LEN  (1U)
+#define GLB_WIFIPLL_VCO_DIV3_EN_MSK  (((1U << GLB_WIFIPLL_VCO_DIV3_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV3_EN_POS)
+#define GLB_WIFIPLL_VCO_DIV3_EN_UMSK (~(((1U << GLB_WIFIPLL_VCO_DIV3_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV3_EN_POS))
+#define GLB_WIFIPLL_VCO_DIV2_EN      GLB_WIFIPLL_VCO_DIV2_EN
+#define GLB_WIFIPLL_VCO_DIV2_EN_POS  (4U)
+#define GLB_WIFIPLL_VCO_DIV2_EN_LEN  (1U)
+#define GLB_WIFIPLL_VCO_DIV2_EN_MSK  (((1U << GLB_WIFIPLL_VCO_DIV2_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV2_EN_POS)
+#define GLB_WIFIPLL_VCO_DIV2_EN_UMSK (~(((1U << GLB_WIFIPLL_VCO_DIV2_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV2_EN_POS))
+#define GLB_WIFIPLL_VCO_DIV1_EN      GLB_WIFIPLL_VCO_DIV1_EN
+#define GLB_WIFIPLL_VCO_DIV1_EN_POS  (5U)
+#define GLB_WIFIPLL_VCO_DIV1_EN_LEN  (1U)
+#define GLB_WIFIPLL_VCO_DIV1_EN_MSK  (((1U << GLB_WIFIPLL_VCO_DIV1_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV1_EN_POS)
+#define GLB_WIFIPLL_VCO_DIV1_EN_UMSK (~(((1U << GLB_WIFIPLL_VCO_DIV1_EN_LEN) - 1) << GLB_WIFIPLL_VCO_DIV1_EN_POS))
+
+/* 0x828 : wifi_pll_cfg6 */
+#define GLB_WIFI_PLL_CFG6_OFFSET       (0x828)
+#define GLB_WIFIPLL_SDMIN              GLB_WIFIPLL_SDMIN
+#define GLB_WIFIPLL_SDMIN_POS          (0U)
+#define GLB_WIFIPLL_SDMIN_LEN          (26U)
+#define GLB_WIFIPLL_SDMIN_MSK          (((1U << GLB_WIFIPLL_SDMIN_LEN) - 1) << GLB_WIFIPLL_SDMIN_POS)
+#define GLB_WIFIPLL_SDMIN_UMSK         (~(((1U << GLB_WIFIPLL_SDMIN_LEN) - 1) << GLB_WIFIPLL_SDMIN_POS))
+#define GLB_WIFIPLL_SDM_BYPASS         GLB_WIFIPLL_SDM_BYPASS
+#define GLB_WIFIPLL_SDM_BYPASS_POS     (26U)
+#define GLB_WIFIPLL_SDM_BYPASS_LEN     (1U)
+#define GLB_WIFIPLL_SDM_BYPASS_MSK     (((1U << GLB_WIFIPLL_SDM_BYPASS_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_POS)
+#define GLB_WIFIPLL_SDM_BYPASS_UMSK    (~(((1U << GLB_WIFIPLL_SDM_BYPASS_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_POS))
+#define GLB_WIFIPLL_SDM_BYPASS_HW      GLB_WIFIPLL_SDM_BYPASS_HW
+#define GLB_WIFIPLL_SDM_BYPASS_HW_POS  (30U)
+#define GLB_WIFIPLL_SDM_BYPASS_HW_LEN  (1U)
+#define GLB_WIFIPLL_SDM_BYPASS_HW_MSK  (((1U << GLB_WIFIPLL_SDM_BYPASS_HW_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_HW_POS)
+#define GLB_WIFIPLL_SDM_BYPASS_HW_UMSK (~(((1U << GLB_WIFIPLL_SDM_BYPASS_HW_LEN) - 1) << GLB_WIFIPLL_SDM_BYPASS_HW_POS))
+#define GLB_WIFIPLL_SDM_CTRL_HW        GLB_WIFIPLL_SDM_CTRL_HW
+#define GLB_WIFIPLL_SDM_CTRL_HW_POS    (31U)
+#define GLB_WIFIPLL_SDM_CTRL_HW_LEN    (1U)
+#define GLB_WIFIPLL_SDM_CTRL_HW_MSK    (((1U << GLB_WIFIPLL_SDM_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_SDM_CTRL_HW_POS)
+#define GLB_WIFIPLL_SDM_CTRL_HW_UMSK   (~(((1U << GLB_WIFIPLL_SDM_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_SDM_CTRL_HW_POS))
+
+/* 0x82C : wifi_pll_cfg7 */
+#define GLB_WIFI_PLL_CFG7_OFFSET          (0x82C)
+#define GLB_WIFIPLL_SDM_ORDER_SEL         GLB_WIFIPLL_SDM_ORDER_SEL
+#define GLB_WIFIPLL_SDM_ORDER_SEL_POS     (0U)
+#define GLB_WIFIPLL_SDM_ORDER_SEL_LEN     (2U)
+#define GLB_WIFIPLL_SDM_ORDER_SEL_MSK     (((1U << GLB_WIFIPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_ORDER_SEL_POS)
+#define GLB_WIFIPLL_SDM_ORDER_SEL_UMSK    (~(((1U << GLB_WIFIPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_ORDER_SEL_POS))
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL      GLB_WIFIPLL_SDM_NOI_PRBS_SEL
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_POS  (4U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_LEN  (2U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_MSK  (((1U << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_POS)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_SEL_POS))
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN       GLB_WIFIPLL_SDM_NOI_PRBS_EN
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_POS   (8U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_LEN   (1U)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_MSK   (((1U << GLB_WIFIPLL_SDM_NOI_PRBS_EN_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_EN_POS)
+#define GLB_WIFIPLL_SDM_NOI_PRBS_EN_UMSK  (~(((1U << GLB_WIFIPLL_SDM_NOI_PRBS_EN_LEN) - 1) << GLB_WIFIPLL_SDM_NOI_PRBS_EN_POS))
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL      GLB_WIFIPLL_SDM_SIG_PRBS_SEL
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_POS  (12U)
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_LEN  (2U)
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_MSK  (((1U << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_POS)
+#define GLB_WIFIPLL_SDM_SIG_PRBS_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_PRBS_SEL_POS))
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL      GLB_WIFIPLL_SDM_SIG_DITH_SEL
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_POS  (16U)
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_LEN  (2U)
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_MSK  (((1U << GLB_WIFIPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_DITH_SEL_POS)
+#define GLB_WIFIPLL_SDM_SIG_DITH_SEL_UMSK (~(((1U << GLB_WIFIPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_WIFIPLL_SDM_SIG_DITH_SEL_POS))
+
+/* 0x830 : wifi_pll_cfg8 */
+#define GLB_WIFI_PLL_CFG8_OFFSET        (0x830)
+#define GLB_WIFIPLL_EN_RF_DIV3          GLB_WIFIPLL_EN_RF_DIV3
+#define GLB_WIFIPLL_EN_RF_DIV3_POS      (0U)
+#define GLB_WIFIPLL_EN_RF_DIV3_LEN      (1U)
+#define GLB_WIFIPLL_EN_RF_DIV3_MSK      (((1U << GLB_WIFIPLL_EN_RF_DIV3_LEN) - 1) << GLB_WIFIPLL_EN_RF_DIV3_POS)
+#define GLB_WIFIPLL_EN_RF_DIV3_UMSK     (~(((1U << GLB_WIFIPLL_EN_RF_DIV3_LEN) - 1) << GLB_WIFIPLL_EN_RF_DIV3_POS))
+#define GLB_WIFIPLL_EN_RF_DIV6          GLB_WIFIPLL_EN_RF_DIV6
+#define GLB_WIFIPLL_EN_RF_DIV6_POS      (1U)
+#define GLB_WIFIPLL_EN_RF_DIV6_LEN      (1U)
+#define GLB_WIFIPLL_EN_RF_DIV6_MSK      (((1U << GLB_WIFIPLL_EN_RF_DIV6_LEN) - 1) << GLB_WIFIPLL_EN_RF_DIV6_POS)
+#define GLB_WIFIPLL_EN_RF_DIV6_UMSK     (~(((1U << GLB_WIFIPLL_EN_RF_DIV6_LEN) - 1) << GLB_WIFIPLL_EN_RF_DIV6_POS))
+#define GLB_WIFIPLL_SEL_DIV3_DIV6       GLB_WIFIPLL_SEL_DIV3_DIV6
+#define GLB_WIFIPLL_SEL_DIV3_DIV6_POS   (2U)
+#define GLB_WIFIPLL_SEL_DIV3_DIV6_LEN   (1U)
+#define GLB_WIFIPLL_SEL_DIV3_DIV6_MSK   (((1U << GLB_WIFIPLL_SEL_DIV3_DIV6_LEN) - 1) << GLB_WIFIPLL_SEL_DIV3_DIV6_POS)
+#define GLB_WIFIPLL_SEL_DIV3_DIV6_UMSK  (~(((1U << GLB_WIFIPLL_SEL_DIV3_DIV6_LEN) - 1) << GLB_WIFIPLL_SEL_DIV3_DIV6_POS))
+#define GLB_WIFIPLL_SEL_DIV6_DIV12      GLB_WIFIPLL_SEL_DIV6_DIV12
+#define GLB_WIFIPLL_SEL_DIV6_DIV12_POS  (3U)
+#define GLB_WIFIPLL_SEL_DIV6_DIV12_LEN  (1U)
+#define GLB_WIFIPLL_SEL_DIV6_DIV12_MSK  (((1U << GLB_WIFIPLL_SEL_DIV6_DIV12_LEN) - 1) << GLB_WIFIPLL_SEL_DIV6_DIV12_POS)
+#define GLB_WIFIPLL_SEL_DIV6_DIV12_UMSK (~(((1U << GLB_WIFIPLL_SEL_DIV6_DIV12_LEN) - 1) << GLB_WIFIPLL_SEL_DIV6_DIV12_POS))
+#define GLB_WIFIPLL_EN_DIV3             GLB_WIFIPLL_EN_DIV3
+#define GLB_WIFIPLL_EN_DIV3_POS         (4U)
+#define GLB_WIFIPLL_EN_DIV3_LEN         (1U)
+#define GLB_WIFIPLL_EN_DIV3_MSK         (((1U << GLB_WIFIPLL_EN_DIV3_LEN) - 1) << GLB_WIFIPLL_EN_DIV3_POS)
+#define GLB_WIFIPLL_EN_DIV3_UMSK        (~(((1U << GLB_WIFIPLL_EN_DIV3_LEN) - 1) << GLB_WIFIPLL_EN_DIV3_POS))
+#define GLB_WIFIPLL_EN_DIV4             GLB_WIFIPLL_EN_DIV4
+#define GLB_WIFIPLL_EN_DIV4_POS         (5U)
+#define GLB_WIFIPLL_EN_DIV4_LEN         (1U)
+#define GLB_WIFIPLL_EN_DIV4_MSK         (((1U << GLB_WIFIPLL_EN_DIV4_LEN) - 1) << GLB_WIFIPLL_EN_DIV4_POS)
+#define GLB_WIFIPLL_EN_DIV4_UMSK        (~(((1U << GLB_WIFIPLL_EN_DIV4_LEN) - 1) << GLB_WIFIPLL_EN_DIV4_POS))
+#define GLB_WIFIPLL_EN_DIV5             GLB_WIFIPLL_EN_DIV5
+#define GLB_WIFIPLL_EN_DIV5_POS         (6U)
+#define GLB_WIFIPLL_EN_DIV5_LEN         (1U)
+#define GLB_WIFIPLL_EN_DIV5_MSK         (((1U << GLB_WIFIPLL_EN_DIV5_LEN) - 1) << GLB_WIFIPLL_EN_DIV5_POS)
+#define GLB_WIFIPLL_EN_DIV5_UMSK        (~(((1U << GLB_WIFIPLL_EN_DIV5_LEN) - 1) << GLB_WIFIPLL_EN_DIV5_POS))
+#define GLB_WIFIPLL_EN_DIV6             GLB_WIFIPLL_EN_DIV6
+#define GLB_WIFIPLL_EN_DIV6_POS         (7U)
+#define GLB_WIFIPLL_EN_DIV6_LEN         (1U)
+#define GLB_WIFIPLL_EN_DIV6_MSK         (((1U << GLB_WIFIPLL_EN_DIV6_LEN) - 1) << GLB_WIFIPLL_EN_DIV6_POS)
+#define GLB_WIFIPLL_EN_DIV6_UMSK        (~(((1U << GLB_WIFIPLL_EN_DIV6_LEN) - 1) << GLB_WIFIPLL_EN_DIV6_POS))
+#define GLB_WIFIPLL_EN_DIV8             GLB_WIFIPLL_EN_DIV8
+#define GLB_WIFIPLL_EN_DIV8_POS         (8U)
+#define GLB_WIFIPLL_EN_DIV8_LEN         (1U)
+#define GLB_WIFIPLL_EN_DIV8_MSK         (((1U << GLB_WIFIPLL_EN_DIV8_LEN) - 1) << GLB_WIFIPLL_EN_DIV8_POS)
+#define GLB_WIFIPLL_EN_DIV8_UMSK        (~(((1U << GLB_WIFIPLL_EN_DIV8_LEN) - 1) << GLB_WIFIPLL_EN_DIV8_POS))
+#define GLB_WIFIPLL_EN_DIV10            GLB_WIFIPLL_EN_DIV10
+#define GLB_WIFIPLL_EN_DIV10_POS        (9U)
+#define GLB_WIFIPLL_EN_DIV10_LEN        (1U)
+#define GLB_WIFIPLL_EN_DIV10_MSK        (((1U << GLB_WIFIPLL_EN_DIV10_LEN) - 1) << GLB_WIFIPLL_EN_DIV10_POS)
+#define GLB_WIFIPLL_EN_DIV10_UMSK       (~(((1U << GLB_WIFIPLL_EN_DIV10_LEN) - 1) << GLB_WIFIPLL_EN_DIV10_POS))
+#define GLB_WIFIPLL_EN_DIV12            GLB_WIFIPLL_EN_DIV12
+#define GLB_WIFIPLL_EN_DIV12_POS        (10U)
+#define GLB_WIFIPLL_EN_DIV12_LEN        (1U)
+#define GLB_WIFIPLL_EN_DIV12_MSK        (((1U << GLB_WIFIPLL_EN_DIV12_LEN) - 1) << GLB_WIFIPLL_EN_DIV12_POS)
+#define GLB_WIFIPLL_EN_DIV12_UMSK       (~(((1U << GLB_WIFIPLL_EN_DIV12_LEN) - 1) << GLB_WIFIPLL_EN_DIV12_POS))
+#define GLB_WIFIPLL_EN_DIV20            GLB_WIFIPLL_EN_DIV20
+#define GLB_WIFIPLL_EN_DIV20_POS        (11U)
+#define GLB_WIFIPLL_EN_DIV20_LEN        (1U)
+#define GLB_WIFIPLL_EN_DIV20_MSK        (((1U << GLB_WIFIPLL_EN_DIV20_LEN) - 1) << GLB_WIFIPLL_EN_DIV20_POS)
+#define GLB_WIFIPLL_EN_DIV20_UMSK       (~(((1U << GLB_WIFIPLL_EN_DIV20_LEN) - 1) << GLB_WIFIPLL_EN_DIV20_POS))
+#define GLB_WIFIPLL_EN_DIV30            GLB_WIFIPLL_EN_DIV30
+#define GLB_WIFIPLL_EN_DIV30_POS        (12U)
+#define GLB_WIFIPLL_EN_DIV30_LEN        (1U)
+#define GLB_WIFIPLL_EN_DIV30_MSK        (((1U << GLB_WIFIPLL_EN_DIV30_LEN) - 1) << GLB_WIFIPLL_EN_DIV30_POS)
+#define GLB_WIFIPLL_EN_DIV30_UMSK       (~(((1U << GLB_WIFIPLL_EN_DIV30_LEN) - 1) << GLB_WIFIPLL_EN_DIV30_POS))
+#define GLB_WIFIPLL_EN_RF_DIV3_HW       GLB_WIFIPLL_EN_RF_DIV3_HW
+#define GLB_WIFIPLL_EN_RF_DIV3_HW_POS   (20U)
+#define GLB_WIFIPLL_EN_RF_DIV3_HW_LEN   (1U)
+#define GLB_WIFIPLL_EN_RF_DIV3_HW_MSK   (((1U << GLB_WIFIPLL_EN_RF_DIV3_HW_LEN) - 1) << GLB_WIFIPLL_EN_RF_DIV3_HW_POS)
+#define GLB_WIFIPLL_EN_RF_DIV3_HW_UMSK  (~(((1U << GLB_WIFIPLL_EN_RF_DIV3_HW_LEN) - 1) << GLB_WIFIPLL_EN_RF_DIV3_HW_POS))
+#define GLB_WIFIPLL_EN_CTRL_HW          GLB_WIFIPLL_EN_CTRL_HW
+#define GLB_WIFIPLL_EN_CTRL_HW_POS      (31U)
+#define GLB_WIFIPLL_EN_CTRL_HW_LEN      (1U)
+#define GLB_WIFIPLL_EN_CTRL_HW_MSK      (((1U << GLB_WIFIPLL_EN_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_EN_CTRL_HW_POS)
+#define GLB_WIFIPLL_EN_CTRL_HW_UMSK     (~(((1U << GLB_WIFIPLL_EN_CTRL_HW_LEN) - 1) << GLB_WIFIPLL_EN_CTRL_HW_POS))
+
+/* 0x834 : wifi_pll_cfg9 */
+#define GLB_WIFI_PLL_CFG9_OFFSET          (0x834)
+#define GLB_WIFIPLL_DC_TP_OUT_EN          GLB_WIFIPLL_DC_TP_OUT_EN
+#define GLB_WIFIPLL_DC_TP_OUT_EN_POS      (0U)
+#define GLB_WIFIPLL_DC_TP_OUT_EN_LEN      (1U)
+#define GLB_WIFIPLL_DC_TP_OUT_EN_MSK      (((1U << GLB_WIFIPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_WIFIPLL_DC_TP_OUT_EN_POS)
+#define GLB_WIFIPLL_DC_TP_OUT_EN_UMSK     (~(((1U << GLB_WIFIPLL_DC_TP_OUT_EN_LEN) - 1) << GLB_WIFIPLL_DC_TP_OUT_EN_POS))
+#define GLB_TEN_WIFIPLL                   GLB_TEN_WIFIPLL
+#define GLB_TEN_WIFIPLL_POS               (1U)
+#define GLB_TEN_WIFIPLL_LEN               (1U)
+#define GLB_TEN_WIFIPLL_MSK               (((1U << GLB_TEN_WIFIPLL_LEN) - 1) << GLB_TEN_WIFIPLL_POS)
+#define GLB_TEN_WIFIPLL_UMSK              (~(((1U << GLB_TEN_WIFIPLL_LEN) - 1) << GLB_TEN_WIFIPLL_POS))
+#define GLB_TEN_WIFIPLL_SFREG             GLB_TEN_WIFIPLL_SFREG
+#define GLB_TEN_WIFIPLL_SFREG_POS         (2U)
+#define GLB_TEN_WIFIPLL_SFREG_LEN         (1U)
+#define GLB_TEN_WIFIPLL_SFREG_MSK         (((1U << GLB_TEN_WIFIPLL_SFREG_LEN) - 1) << GLB_TEN_WIFIPLL_SFREG_POS)
+#define GLB_TEN_WIFIPLL_SFREG_UMSK        (~(((1U << GLB_TEN_WIFIPLL_SFREG_LEN) - 1) << GLB_TEN_WIFIPLL_SFREG_POS))
+#define GLB_DTEN_WIFIPLL_FIN              GLB_DTEN_WIFIPLL_FIN
+#define GLB_DTEN_WIFIPLL_FIN_POS          (4U)
+#define GLB_DTEN_WIFIPLL_FIN_LEN          (1U)
+#define GLB_DTEN_WIFIPLL_FIN_MSK          (((1U << GLB_DTEN_WIFIPLL_FIN_LEN) - 1) << GLB_DTEN_WIFIPLL_FIN_POS)
+#define GLB_DTEN_WIFIPLL_FIN_UMSK         (~(((1U << GLB_DTEN_WIFIPLL_FIN_LEN) - 1) << GLB_DTEN_WIFIPLL_FIN_POS))
+#define GLB_DTEN_WIFIPLL_FREF             GLB_DTEN_WIFIPLL_FREF
+#define GLB_DTEN_WIFIPLL_FREF_POS         (5U)
+#define GLB_DTEN_WIFIPLL_FREF_LEN         (1U)
+#define GLB_DTEN_WIFIPLL_FREF_MSK         (((1U << GLB_DTEN_WIFIPLL_FREF_LEN) - 1) << GLB_DTEN_WIFIPLL_FREF_POS)
+#define GLB_DTEN_WIFIPLL_FREF_UMSK        (~(((1U << GLB_DTEN_WIFIPLL_FREF_LEN) - 1) << GLB_DTEN_WIFIPLL_FREF_POS))
+#define GLB_DTEN_WIFIPLL_FSDM             GLB_DTEN_WIFIPLL_FSDM
+#define GLB_DTEN_WIFIPLL_FSDM_POS         (6U)
+#define GLB_DTEN_WIFIPLL_FSDM_LEN         (1U)
+#define GLB_DTEN_WIFIPLL_FSDM_MSK         (((1U << GLB_DTEN_WIFIPLL_FSDM_LEN) - 1) << GLB_DTEN_WIFIPLL_FSDM_POS)
+#define GLB_DTEN_WIFIPLL_FSDM_UMSK        (~(((1U << GLB_DTEN_WIFIPLL_FSDM_LEN) - 1) << GLB_DTEN_WIFIPLL_FSDM_POS))
+#define GLB_DTEN_WIFIPLL_DIV30            GLB_DTEN_WIFIPLL_DIV30
+#define GLB_DTEN_WIFIPLL_DIV30_POS        (7U)
+#define GLB_DTEN_WIFIPLL_DIV30_LEN        (1U)
+#define GLB_DTEN_WIFIPLL_DIV30_MSK        (((1U << GLB_DTEN_WIFIPLL_DIV30_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV30_POS)
+#define GLB_DTEN_WIFIPLL_DIV30_UMSK       (~(((1U << GLB_DTEN_WIFIPLL_DIV30_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV30_POS))
+#define GLB_DTEN_WIFIPLL_DIV10            GLB_DTEN_WIFIPLL_DIV10
+#define GLB_DTEN_WIFIPLL_DIV10_POS        (8U)
+#define GLB_DTEN_WIFIPLL_DIV10_LEN        (1U)
+#define GLB_DTEN_WIFIPLL_DIV10_MSK        (((1U << GLB_DTEN_WIFIPLL_DIV10_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV10_POS)
+#define GLB_DTEN_WIFIPLL_DIV10_UMSK       (~(((1U << GLB_DTEN_WIFIPLL_DIV10_LEN) - 1) << GLB_DTEN_WIFIPLL_DIV10_POS))
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK      GLB_DTEN_WIFIPLL_POSTDIV_CLK
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_POS  (9U)
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_LEN  (1U)
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_MSK  (((1U << GLB_DTEN_WIFIPLL_POSTDIV_CLK_LEN) - 1) << GLB_DTEN_WIFIPLL_POSTDIV_CLK_POS)
+#define GLB_DTEN_WIFIPLL_POSTDIV_CLK_UMSK (~(((1U << GLB_DTEN_WIFIPLL_POSTDIV_CLK_LEN) - 1) << GLB_DTEN_WIFIPLL_POSTDIV_CLK_POS))
+#define GLB_DTEN_USBPLL_PCLK              GLB_DTEN_USBPLL_PCLK
+#define GLB_DTEN_USBPLL_PCLK_POS          (10U)
+#define GLB_DTEN_USBPLL_PCLK_LEN          (1U)
+#define GLB_DTEN_USBPLL_PCLK_MSK          (((1U << GLB_DTEN_USBPLL_PCLK_LEN) - 1) << GLB_DTEN_USBPLL_PCLK_POS)
+#define GLB_DTEN_USBPLL_PCLK_UMSK         (~(((1U << GLB_DTEN_USBPLL_PCLK_LEN) - 1) << GLB_DTEN_USBPLL_PCLK_POS))
+#define GLB_DTEN_USBPLL_CLKOUT            GLB_DTEN_USBPLL_CLKOUT
+#define GLB_DTEN_USBPLL_CLKOUT_POS        (11U)
+#define GLB_DTEN_USBPLL_CLKOUT_LEN        (1U)
+#define GLB_DTEN_USBPLL_CLKOUT_MSK        (((1U << GLB_DTEN_USBPLL_CLKOUT_LEN) - 1) << GLB_DTEN_USBPLL_CLKOUT_POS)
+#define GLB_DTEN_USBPLL_CLKOUT_UMSK       (~(((1U << GLB_DTEN_USBPLL_CLKOUT_LEN) - 1) << GLB_DTEN_USBPLL_CLKOUT_POS))
+#define GLB_DTEN_SSCDIV_PCLK              GLB_DTEN_SSCDIV_PCLK
+#define GLB_DTEN_SSCDIV_PCLK_POS          (12U)
+#define GLB_DTEN_SSCDIV_PCLK_LEN          (1U)
+#define GLB_DTEN_SSCDIV_PCLK_MSK          (((1U << GLB_DTEN_SSCDIV_PCLK_LEN) - 1) << GLB_DTEN_SSCDIV_PCLK_POS)
+#define GLB_DTEN_SSCDIV_PCLK_UMSK         (~(((1U << GLB_DTEN_SSCDIV_PCLK_LEN) - 1) << GLB_DTEN_SSCDIV_PCLK_POS))
+#define GLB_DTEN_SSCDIV_CLKOUT            GLB_DTEN_SSCDIV_CLKOUT
+#define GLB_DTEN_SSCDIV_CLKOUT_POS        (13U)
+#define GLB_DTEN_SSCDIV_CLKOUT_LEN        (1U)
+#define GLB_DTEN_SSCDIV_CLKOUT_MSK        (((1U << GLB_DTEN_SSCDIV_CLKOUT_LEN) - 1) << GLB_DTEN_SSCDIV_CLKOUT_POS)
+#define GLB_DTEN_SSCDIV_CLKOUT_UMSK       (~(((1U << GLB_DTEN_SSCDIV_CLKOUT_LEN) - 1) << GLB_DTEN_SSCDIV_CLKOUT_POS))
+#define GLB_DTEST_PULLDOWN                GLB_DTEST_PULLDOWN
+#define GLB_DTEST_PULLDOWN_POS            (14U)
+#define GLB_DTEST_PULLDOWN_LEN            (1U)
+#define GLB_DTEST_PULLDOWN_MSK            (((1U << GLB_DTEST_PULLDOWN_LEN) - 1) << GLB_DTEST_PULLDOWN_POS)
+#define GLB_DTEST_PULLDOWN_UMSK           (~(((1U << GLB_DTEST_PULLDOWN_LEN) - 1) << GLB_DTEST_PULLDOWN_POS))
+
+/* 0x838 : wifi_pll_cfg10 */
+#define GLB_WIFI_PLL_CFG10_OFFSET        (0x838)
+#define GLB_USBPLL_SDMIN                 GLB_USBPLL_SDMIN
+#define GLB_USBPLL_SDMIN_POS             (0U)
+#define GLB_USBPLL_SDMIN_LEN             (19U)
+#define GLB_USBPLL_SDMIN_MSK             (((1U << GLB_USBPLL_SDMIN_LEN) - 1) << GLB_USBPLL_SDMIN_POS)
+#define GLB_USBPLL_SDMIN_UMSK            (~(((1U << GLB_USBPLL_SDMIN_LEN) - 1) << GLB_USBPLL_SDMIN_POS))
+#define GLB_USBPLL_SDM_BYPASS            GLB_USBPLL_SDM_BYPASS
+#define GLB_USBPLL_SDM_BYPASS_POS        (20U)
+#define GLB_USBPLL_SDM_BYPASS_LEN        (1U)
+#define GLB_USBPLL_SDM_BYPASS_MSK        (((1U << GLB_USBPLL_SDM_BYPASS_LEN) - 1) << GLB_USBPLL_SDM_BYPASS_POS)
+#define GLB_USBPLL_SDM_BYPASS_UMSK       (~(((1U << GLB_USBPLL_SDM_BYPASS_LEN) - 1) << GLB_USBPLL_SDM_BYPASS_POS))
+#define GLB_USBPLL_SDM_ORDER_SEL         GLB_USBPLL_SDM_ORDER_SEL
+#define GLB_USBPLL_SDM_ORDER_SEL_POS     (21U)
+#define GLB_USBPLL_SDM_ORDER_SEL_LEN     (1U)
+#define GLB_USBPLL_SDM_ORDER_SEL_MSK     (((1U << GLB_USBPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_USBPLL_SDM_ORDER_SEL_POS)
+#define GLB_USBPLL_SDM_ORDER_SEL_UMSK    (~(((1U << GLB_USBPLL_SDM_ORDER_SEL_LEN) - 1) << GLB_USBPLL_SDM_ORDER_SEL_POS))
+#define GLB_USBPLL_SDM_SIG_DITH_SEL      GLB_USBPLL_SDM_SIG_DITH_SEL
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_POS  (22U)
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_LEN  (2U)
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_MSK  (((1U << GLB_USBPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_USBPLL_SDM_SIG_DITH_SEL_POS)
+#define GLB_USBPLL_SDM_SIG_DITH_SEL_UMSK (~(((1U << GLB_USBPLL_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_USBPLL_SDM_SIG_DITH_SEL_POS))
+#define GLB_USBPLL_DIV2_EN               GLB_USBPLL_DIV2_EN
+#define GLB_USBPLL_DIV2_EN_POS           (24U)
+#define GLB_USBPLL_DIV2_EN_LEN           (1U)
+#define GLB_USBPLL_DIV2_EN_MSK           (((1U << GLB_USBPLL_DIV2_EN_LEN) - 1) << GLB_USBPLL_DIV2_EN_POS)
+#define GLB_USBPLL_DIV2_EN_UMSK          (~(((1U << GLB_USBPLL_DIV2_EN_LEN) - 1) << GLB_USBPLL_DIV2_EN_POS))
+#define GLB_USBPLL_CLKOUT_EN             GLB_USBPLL_CLKOUT_EN
+#define GLB_USBPLL_CLKOUT_EN_POS         (25U)
+#define GLB_USBPLL_CLKOUT_EN_LEN         (1U)
+#define GLB_USBPLL_CLKOUT_EN_MSK         (((1U << GLB_USBPLL_CLKOUT_EN_LEN) - 1) << GLB_USBPLL_CLKOUT_EN_POS)
+#define GLB_USBPLL_CLKOUT_EN_UMSK        (~(((1U << GLB_USBPLL_CLKOUT_EN_LEN) - 1) << GLB_USBPLL_CLKOUT_EN_POS))
+#define GLB_USBPLL_SEL_SAMPLE_CLK        GLB_USBPLL_SEL_SAMPLE_CLK
+#define GLB_USBPLL_SEL_SAMPLE_CLK_POS    (26U)
+#define GLB_USBPLL_SEL_SAMPLE_CLK_LEN    (2U)
+#define GLB_USBPLL_SEL_SAMPLE_CLK_MSK    (((1U << GLB_USBPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_USBPLL_SEL_SAMPLE_CLK_POS)
+#define GLB_USBPLL_SEL_SAMPLE_CLK_UMSK   (~(((1U << GLB_USBPLL_SEL_SAMPLE_CLK_LEN) - 1) << GLB_USBPLL_SEL_SAMPLE_CLK_POS))
+#define GLB_USBPLL_RSTB                  GLB_USBPLL_RSTB
+#define GLB_USBPLL_RSTB_POS              (28U)
+#define GLB_USBPLL_RSTB_LEN              (1U)
+#define GLB_USBPLL_RSTB_MSK              (((1U << GLB_USBPLL_RSTB_LEN) - 1) << GLB_USBPLL_RSTB_POS)
+#define GLB_USBPLL_RSTB_UMSK             (~(((1U << GLB_USBPLL_RSTB_LEN) - 1) << GLB_USBPLL_RSTB_POS))
+#define GLB_PU_USBPLL_MMDIV              GLB_PU_USBPLL_MMDIV
+#define GLB_PU_USBPLL_MMDIV_POS          (29U)
+#define GLB_PU_USBPLL_MMDIV_LEN          (1U)
+#define GLB_PU_USBPLL_MMDIV_MSK          (((1U << GLB_PU_USBPLL_MMDIV_LEN) - 1) << GLB_PU_USBPLL_MMDIV_POS)
+#define GLB_PU_USBPLL_MMDIV_UMSK         (~(((1U << GLB_PU_USBPLL_MMDIV_LEN) - 1) << GLB_PU_USBPLL_MMDIV_POS))
+
+/* 0x83C : wifi_pll_cfg11 */
+#define GLB_WIFI_PLL_CFG11_OFFSET         (0x83C)
+#define GLB_USBPLL_SSC_CNT                GLB_USBPLL_SSC_CNT
+#define GLB_USBPLL_SSC_CNT_POS            (0U)
+#define GLB_USBPLL_SSC_CNT_LEN            (9U)
+#define GLB_USBPLL_SSC_CNT_MSK            (((1U << GLB_USBPLL_SSC_CNT_LEN) - 1) << GLB_USBPLL_SSC_CNT_POS)
+#define GLB_USBPLL_SSC_CNT_UMSK           (~(((1U << GLB_USBPLL_SSC_CNT_LEN) - 1) << GLB_USBPLL_SSC_CNT_POS))
+#define GLB_USBPLL_SSC_START              GLB_USBPLL_SSC_START
+#define GLB_USBPLL_SSC_START_POS          (9U)
+#define GLB_USBPLL_SSC_START_LEN          (1U)
+#define GLB_USBPLL_SSC_START_MSK          (((1U << GLB_USBPLL_SSC_START_LEN) - 1) << GLB_USBPLL_SSC_START_POS)
+#define GLB_USBPLL_SSC_START_UMSK         (~(((1U << GLB_USBPLL_SSC_START_LEN) - 1) << GLB_USBPLL_SSC_START_POS))
+#define GLB_USBPLL_SSC_START_GATE_EN      GLB_USBPLL_SSC_START_GATE_EN
+#define GLB_USBPLL_SSC_START_GATE_EN_POS  (10U)
+#define GLB_USBPLL_SSC_START_GATE_EN_LEN  (1U)
+#define GLB_USBPLL_SSC_START_GATE_EN_MSK  (((1U << GLB_USBPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_USBPLL_SSC_START_GATE_EN_POS)
+#define GLB_USBPLL_SSC_START_GATE_EN_UMSK (~(((1U << GLB_USBPLL_SSC_START_GATE_EN_LEN) - 1) << GLB_USBPLL_SSC_START_GATE_EN_POS))
+#define GLB_USBPLL_SSC_GAIN               GLB_USBPLL_SSC_GAIN
+#define GLB_USBPLL_SSC_GAIN_POS           (12U)
+#define GLB_USBPLL_SSC_GAIN_LEN           (3U)
+#define GLB_USBPLL_SSC_GAIN_MSK           (((1U << GLB_USBPLL_SSC_GAIN_LEN) - 1) << GLB_USBPLL_SSC_GAIN_POS)
+#define GLB_USBPLL_SSC_GAIN_UMSK          (~(((1U << GLB_USBPLL_SSC_GAIN_LEN) - 1) << GLB_USBPLL_SSC_GAIN_POS))
+#define GLB_USBPLL_SSC_EN                 GLB_USBPLL_SSC_EN
+#define GLB_USBPLL_SSC_EN_POS             (16U)
+#define GLB_USBPLL_SSC_EN_LEN             (1U)
+#define GLB_USBPLL_SSC_EN_MSK             (((1U << GLB_USBPLL_SSC_EN_LEN) - 1) << GLB_USBPLL_SSC_EN_POS)
+#define GLB_USBPLL_SSC_EN_UMSK            (~(((1U << GLB_USBPLL_SSC_EN_LEN) - 1) << GLB_USBPLL_SSC_EN_POS))
+
+/* 0x840 : wifi_pll_cfg12 */
+#define GLB_WIFI_PLL_CFG12_OFFSET        (0x840)
+#define GLB_SSCDIV_SDMIN                 GLB_SSCDIV_SDMIN
+#define GLB_SSCDIV_SDMIN_POS             (0U)
+#define GLB_SSCDIV_SDMIN_LEN             (19U)
+#define GLB_SSCDIV_SDMIN_MSK             (((1U << GLB_SSCDIV_SDMIN_LEN) - 1) << GLB_SSCDIV_SDMIN_POS)
+#define GLB_SSCDIV_SDMIN_UMSK            (~(((1U << GLB_SSCDIV_SDMIN_LEN) - 1) << GLB_SSCDIV_SDMIN_POS))
+#define GLB_SSCDIV_SDM_BYPASS            GLB_SSCDIV_SDM_BYPASS
+#define GLB_SSCDIV_SDM_BYPASS_POS        (20U)
+#define GLB_SSCDIV_SDM_BYPASS_LEN        (1U)
+#define GLB_SSCDIV_SDM_BYPASS_MSK        (((1U << GLB_SSCDIV_SDM_BYPASS_LEN) - 1) << GLB_SSCDIV_SDM_BYPASS_POS)
+#define GLB_SSCDIV_SDM_BYPASS_UMSK       (~(((1U << GLB_SSCDIV_SDM_BYPASS_LEN) - 1) << GLB_SSCDIV_SDM_BYPASS_POS))
+#define GLB_SSCDIV_SDM_ORDER_SEL         GLB_SSCDIV_SDM_ORDER_SEL
+#define GLB_SSCDIV_SDM_ORDER_SEL_POS     (21U)
+#define GLB_SSCDIV_SDM_ORDER_SEL_LEN     (1U)
+#define GLB_SSCDIV_SDM_ORDER_SEL_MSK     (((1U << GLB_SSCDIV_SDM_ORDER_SEL_LEN) - 1) << GLB_SSCDIV_SDM_ORDER_SEL_POS)
+#define GLB_SSCDIV_SDM_ORDER_SEL_UMSK    (~(((1U << GLB_SSCDIV_SDM_ORDER_SEL_LEN) - 1) << GLB_SSCDIV_SDM_ORDER_SEL_POS))
+#define GLB_SSCDIV_SDM_SIG_DITH_SEL      GLB_SSCDIV_SDM_SIG_DITH_SEL
+#define GLB_SSCDIV_SDM_SIG_DITH_SEL_POS  (22U)
+#define GLB_SSCDIV_SDM_SIG_DITH_SEL_LEN  (2U)
+#define GLB_SSCDIV_SDM_SIG_DITH_SEL_MSK  (((1U << GLB_SSCDIV_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_SSCDIV_SDM_SIG_DITH_SEL_POS)
+#define GLB_SSCDIV_SDM_SIG_DITH_SEL_UMSK (~(((1U << GLB_SSCDIV_SDM_SIG_DITH_SEL_LEN) - 1) << GLB_SSCDIV_SDM_SIG_DITH_SEL_POS))
+#define GLB_SSCDIV_DIV2_EN               GLB_SSCDIV_DIV2_EN
+#define GLB_SSCDIV_DIV2_EN_POS           (24U)
+#define GLB_SSCDIV_DIV2_EN_LEN           (1U)
+#define GLB_SSCDIV_DIV2_EN_MSK           (((1U << GLB_SSCDIV_DIV2_EN_LEN) - 1) << GLB_SSCDIV_DIV2_EN_POS)
+#define GLB_SSCDIV_DIV2_EN_UMSK          (~(((1U << GLB_SSCDIV_DIV2_EN_LEN) - 1) << GLB_SSCDIV_DIV2_EN_POS))
+#define GLB_SSCDIV_CLKOUT_EN             GLB_SSCDIV_CLKOUT_EN
+#define GLB_SSCDIV_CLKOUT_EN_POS         (25U)
+#define GLB_SSCDIV_CLKOUT_EN_LEN         (1U)
+#define GLB_SSCDIV_CLKOUT_EN_MSK         (((1U << GLB_SSCDIV_CLKOUT_EN_LEN) - 1) << GLB_SSCDIV_CLKOUT_EN_POS)
+#define GLB_SSCDIV_CLKOUT_EN_UMSK        (~(((1U << GLB_SSCDIV_CLKOUT_EN_LEN) - 1) << GLB_SSCDIV_CLKOUT_EN_POS))
+#define GLB_SSCDIV_SEL_SAMPLE_CLK        GLB_SSCDIV_SEL_SAMPLE_CLK
+#define GLB_SSCDIV_SEL_SAMPLE_CLK_POS    (26U)
+#define GLB_SSCDIV_SEL_SAMPLE_CLK_LEN    (2U)
+#define GLB_SSCDIV_SEL_SAMPLE_CLK_MSK    (((1U << GLB_SSCDIV_SEL_SAMPLE_CLK_LEN) - 1) << GLB_SSCDIV_SEL_SAMPLE_CLK_POS)
+#define GLB_SSCDIV_SEL_SAMPLE_CLK_UMSK   (~(((1U << GLB_SSCDIV_SEL_SAMPLE_CLK_LEN) - 1) << GLB_SSCDIV_SEL_SAMPLE_CLK_POS))
+#define GLB_SSCDIV_RSTB                  GLB_SSCDIV_RSTB
+#define GLB_SSCDIV_RSTB_POS              (28U)
+#define GLB_SSCDIV_RSTB_LEN              (1U)
+#define GLB_SSCDIV_RSTB_MSK              (((1U << GLB_SSCDIV_RSTB_LEN) - 1) << GLB_SSCDIV_RSTB_POS)
+#define GLB_SSCDIV_RSTB_UMSK             (~(((1U << GLB_SSCDIV_RSTB_LEN) - 1) << GLB_SSCDIV_RSTB_POS))
+#define GLB_PU_SSCDIV_MMDIV              GLB_PU_SSCDIV_MMDIV
+#define GLB_PU_SSCDIV_MMDIV_POS          (29U)
+#define GLB_PU_SSCDIV_MMDIV_LEN          (1U)
+#define GLB_PU_SSCDIV_MMDIV_MSK          (((1U << GLB_PU_SSCDIV_MMDIV_LEN) - 1) << GLB_PU_SSCDIV_MMDIV_POS)
+#define GLB_PU_SSCDIV_MMDIV_UMSK         (~(((1U << GLB_PU_SSCDIV_MMDIV_LEN) - 1) << GLB_PU_SSCDIV_MMDIV_POS))
+
+/* 0x844 : wifi_pll_cfg13 */
+#define GLB_WIFI_PLL_CFG13_OFFSET         (0x844)
+#define GLB_SSCDIV_SSC_CNT                GLB_SSCDIV_SSC_CNT
+#define GLB_SSCDIV_SSC_CNT_POS            (0U)
+#define GLB_SSCDIV_SSC_CNT_LEN            (9U)
+#define GLB_SSCDIV_SSC_CNT_MSK            (((1U << GLB_SSCDIV_SSC_CNT_LEN) - 1) << GLB_SSCDIV_SSC_CNT_POS)
+#define GLB_SSCDIV_SSC_CNT_UMSK           (~(((1U << GLB_SSCDIV_SSC_CNT_LEN) - 1) << GLB_SSCDIV_SSC_CNT_POS))
+#define GLB_SSCDIV_SSC_START              GLB_SSCDIV_SSC_START
+#define GLB_SSCDIV_SSC_START_POS          (9U)
+#define GLB_SSCDIV_SSC_START_LEN          (1U)
+#define GLB_SSCDIV_SSC_START_MSK          (((1U << GLB_SSCDIV_SSC_START_LEN) - 1) << GLB_SSCDIV_SSC_START_POS)
+#define GLB_SSCDIV_SSC_START_UMSK         (~(((1U << GLB_SSCDIV_SSC_START_LEN) - 1) << GLB_SSCDIV_SSC_START_POS))
+#define GLB_SSCDIV_SSC_START_GATE_EN      GLB_SSCDIV_SSC_START_GATE_EN
+#define GLB_SSCDIV_SSC_START_GATE_EN_POS  (10U)
+#define GLB_SSCDIV_SSC_START_GATE_EN_LEN  (1U)
+#define GLB_SSCDIV_SSC_START_GATE_EN_MSK  (((1U << GLB_SSCDIV_SSC_START_GATE_EN_LEN) - 1) << GLB_SSCDIV_SSC_START_GATE_EN_POS)
+#define GLB_SSCDIV_SSC_START_GATE_EN_UMSK (~(((1U << GLB_SSCDIV_SSC_START_GATE_EN_LEN) - 1) << GLB_SSCDIV_SSC_START_GATE_EN_POS))
+#define GLB_SSCDIV_SSC_GAIN               GLB_SSCDIV_SSC_GAIN
+#define GLB_SSCDIV_SSC_GAIN_POS           (12U)
+#define GLB_SSCDIV_SSC_GAIN_LEN           (3U)
+#define GLB_SSCDIV_SSC_GAIN_MSK           (((1U << GLB_SSCDIV_SSC_GAIN_LEN) - 1) << GLB_SSCDIV_SSC_GAIN_POS)
+#define GLB_SSCDIV_SSC_GAIN_UMSK          (~(((1U << GLB_SSCDIV_SSC_GAIN_LEN) - 1) << GLB_SSCDIV_SSC_GAIN_POS))
+#define GLB_SSCDIV_SSC_EN                 GLB_SSCDIV_SSC_EN
+#define GLB_SSCDIV_SSC_EN_POS             (16U)
+#define GLB_SSCDIV_SSC_EN_LEN             (1U)
+#define GLB_SSCDIV_SSC_EN_MSK             (((1U << GLB_SSCDIV_SSC_EN_LEN) - 1) << GLB_SSCDIV_SSC_EN_POS)
+#define GLB_SSCDIV_SSC_EN_UMSK            (~(((1U << GLB_SSCDIV_SSC_EN_LEN) - 1) << GLB_SSCDIV_SSC_EN_POS))
+
+/* 0x848 : wifi_pll_cfg14 */
+#define GLB_WIFI_PLL_CFG14_OFFSET     (0x848)
+#define GLB_WIFIPLL_RESV              GLB_WIFIPLL_RESV
+#define GLB_WIFIPLL_RESV_POS          (0U)
+#define GLB_WIFIPLL_RESV_LEN          (16U)
+#define GLB_WIFIPLL_RESV_MSK          (((1U << GLB_WIFIPLL_RESV_LEN) - 1) << GLB_WIFIPLL_RESV_POS)
+#define GLB_WIFIPLL_RESV_UMSK         (~(((1U << GLB_WIFIPLL_RESV_LEN) - 1) << GLB_WIFIPLL_RESV_POS))
+#define GLB_SSCDIV_DL_CTRL            GLB_SSCDIV_DL_CTRL
+#define GLB_SSCDIV_DL_CTRL_POS        (16U)
+#define GLB_SSCDIV_DL_CTRL_LEN        (1U)
+#define GLB_SSCDIV_DL_CTRL_MSK        (((1U << GLB_SSCDIV_DL_CTRL_LEN) - 1) << GLB_SSCDIV_DL_CTRL_POS)
+#define GLB_SSCDIV_DL_CTRL_UMSK       (~(((1U << GLB_SSCDIV_DL_CTRL_LEN) - 1) << GLB_SSCDIV_DL_CTRL_POS))
+#define GLB_USBPLL_DL_CTRL            GLB_USBPLL_DL_CTRL
+#define GLB_USBPLL_DL_CTRL_POS        (17U)
+#define GLB_USBPLL_DL_CTRL_LEN        (1U)
+#define GLB_USBPLL_DL_CTRL_MSK        (((1U << GLB_USBPLL_DL_CTRL_LEN) - 1) << GLB_USBPLL_DL_CTRL_POS)
+#define GLB_USBPLL_DL_CTRL_UMSK       (~(((1U << GLB_USBPLL_DL_CTRL_LEN) - 1) << GLB_USBPLL_DL_CTRL_POS))
+#define GLB_WIFIPLL_DL_CTRL_30        GLB_WIFIPLL_DL_CTRL_30
+#define GLB_WIFIPLL_DL_CTRL_30_POS    (18U)
+#define GLB_WIFIPLL_DL_CTRL_30_LEN    (1U)
+#define GLB_WIFIPLL_DL_CTRL_30_MSK    (((1U << GLB_WIFIPLL_DL_CTRL_30_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_30_POS)
+#define GLB_WIFIPLL_DL_CTRL_30_UMSK   (~(((1U << GLB_WIFIPLL_DL_CTRL_30_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_30_POS))
+#define GLB_WIFIPLL_DL_CTRL_20        GLB_WIFIPLL_DL_CTRL_20
+#define GLB_WIFIPLL_DL_CTRL_20_POS    (19U)
+#define GLB_WIFIPLL_DL_CTRL_20_LEN    (1U)
+#define GLB_WIFIPLL_DL_CTRL_20_MSK    (((1U << GLB_WIFIPLL_DL_CTRL_20_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_20_POS)
+#define GLB_WIFIPLL_DL_CTRL_20_UMSK   (~(((1U << GLB_WIFIPLL_DL_CTRL_20_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_20_POS))
+#define GLB_WIFIPLL_DL_CTRL_12        GLB_WIFIPLL_DL_CTRL_12
+#define GLB_WIFIPLL_DL_CTRL_12_POS    (20U)
+#define GLB_WIFIPLL_DL_CTRL_12_LEN    (1U)
+#define GLB_WIFIPLL_DL_CTRL_12_MSK    (((1U << GLB_WIFIPLL_DL_CTRL_12_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_12_POS)
+#define GLB_WIFIPLL_DL_CTRL_12_UMSK   (~(((1U << GLB_WIFIPLL_DL_CTRL_12_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_12_POS))
+#define GLB_WIFIPLL_DL_CTRL_10        GLB_WIFIPLL_DL_CTRL_10
+#define GLB_WIFIPLL_DL_CTRL_10_POS    (21U)
+#define GLB_WIFIPLL_DL_CTRL_10_LEN    (1U)
+#define GLB_WIFIPLL_DL_CTRL_10_MSK    (((1U << GLB_WIFIPLL_DL_CTRL_10_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_10_POS)
+#define GLB_WIFIPLL_DL_CTRL_10_UMSK   (~(((1U << GLB_WIFIPLL_DL_CTRL_10_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_10_POS))
+#define GLB_WIFIPLL_DL_CTRL_8         GLB_WIFIPLL_DL_CTRL_8
+#define GLB_WIFIPLL_DL_CTRL_8_POS     (22U)
+#define GLB_WIFIPLL_DL_CTRL_8_LEN     (1U)
+#define GLB_WIFIPLL_DL_CTRL_8_MSK     (((1U << GLB_WIFIPLL_DL_CTRL_8_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_8_POS)
+#define GLB_WIFIPLL_DL_CTRL_8_UMSK    (~(((1U << GLB_WIFIPLL_DL_CTRL_8_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_8_POS))
+#define GLB_WIFIPLL_DL_CTRL_6_RF      GLB_WIFIPLL_DL_CTRL_6_RF
+#define GLB_WIFIPLL_DL_CTRL_6_RF_POS  (23U)
+#define GLB_WIFIPLL_DL_CTRL_6_RF_LEN  (1U)
+#define GLB_WIFIPLL_DL_CTRL_6_RF_MSK  (((1U << GLB_WIFIPLL_DL_CTRL_6_RF_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_6_RF_POS)
+#define GLB_WIFIPLL_DL_CTRL_6_RF_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_6_RF_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_6_RF_POS))
+#define GLB_WIFIPLL_DL_CTRL_6         GLB_WIFIPLL_DL_CTRL_6
+#define GLB_WIFIPLL_DL_CTRL_6_POS     (24U)
+#define GLB_WIFIPLL_DL_CTRL_6_LEN     (1U)
+#define GLB_WIFIPLL_DL_CTRL_6_MSK     (((1U << GLB_WIFIPLL_DL_CTRL_6_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_6_POS)
+#define GLB_WIFIPLL_DL_CTRL_6_UMSK    (~(((1U << GLB_WIFIPLL_DL_CTRL_6_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_6_POS))
+#define GLB_WIFIPLL_DL_CTRL_5         GLB_WIFIPLL_DL_CTRL_5
+#define GLB_WIFIPLL_DL_CTRL_5_POS     (25U)
+#define GLB_WIFIPLL_DL_CTRL_5_LEN     (1U)
+#define GLB_WIFIPLL_DL_CTRL_5_MSK     (((1U << GLB_WIFIPLL_DL_CTRL_5_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_5_POS)
+#define GLB_WIFIPLL_DL_CTRL_5_UMSK    (~(((1U << GLB_WIFIPLL_DL_CTRL_5_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_5_POS))
+#define GLB_WIFIPLL_DL_CTRL_4         GLB_WIFIPLL_DL_CTRL_4
+#define GLB_WIFIPLL_DL_CTRL_4_POS     (26U)
+#define GLB_WIFIPLL_DL_CTRL_4_LEN     (1U)
+#define GLB_WIFIPLL_DL_CTRL_4_MSK     (((1U << GLB_WIFIPLL_DL_CTRL_4_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_4_POS)
+#define GLB_WIFIPLL_DL_CTRL_4_UMSK    (~(((1U << GLB_WIFIPLL_DL_CTRL_4_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_4_POS))
+#define GLB_WIFIPLL_DL_CTRL_3_RF      GLB_WIFIPLL_DL_CTRL_3_RF
+#define GLB_WIFIPLL_DL_CTRL_3_RF_POS  (27U)
+#define GLB_WIFIPLL_DL_CTRL_3_RF_LEN  (1U)
+#define GLB_WIFIPLL_DL_CTRL_3_RF_MSK  (((1U << GLB_WIFIPLL_DL_CTRL_3_RF_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_3_RF_POS)
+#define GLB_WIFIPLL_DL_CTRL_3_RF_UMSK (~(((1U << GLB_WIFIPLL_DL_CTRL_3_RF_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_3_RF_POS))
+#define GLB_WIFIPLL_DL_CTRL_3         GLB_WIFIPLL_DL_CTRL_3
+#define GLB_WIFIPLL_DL_CTRL_3_POS     (28U)
+#define GLB_WIFIPLL_DL_CTRL_3_LEN     (1U)
+#define GLB_WIFIPLL_DL_CTRL_3_MSK     (((1U << GLB_WIFIPLL_DL_CTRL_3_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_3_POS)
+#define GLB_WIFIPLL_DL_CTRL_3_UMSK    (~(((1U << GLB_WIFIPLL_DL_CTRL_3_LEN) - 1) << GLB_WIFIPLL_DL_CTRL_3_POS))
+
+/* 0x884 : ldo18io */
+#define GLB_LDO18IO_OFFSET            (0x884)
+#define GLB_PU_LDO18IO                GLB_PU_LDO18IO
+#define GLB_PU_LDO18IO_POS            (0U)
+#define GLB_PU_LDO18IO_LEN            (1U)
+#define GLB_PU_LDO18IO_MSK            (((1U << GLB_PU_LDO18IO_LEN) - 1) << GLB_PU_LDO18IO_POS)
+#define GLB_PU_LDO18IO_UMSK           (~(((1U << GLB_PU_LDO18IO_LEN) - 1) << GLB_PU_LDO18IO_POS))
+#define GLB_LDO18IO_BYPASS            GLB_LDO18IO_BYPASS
+#define GLB_LDO18IO_BYPASS_POS        (1U)
+#define GLB_LDO18IO_BYPASS_LEN        (1U)
+#define GLB_LDO18IO_BYPASS_MSK        (((1U << GLB_LDO18IO_BYPASS_LEN) - 1) << GLB_LDO18IO_BYPASS_POS)
+#define GLB_LDO18IO_BYPASS_UMSK       (~(((1U << GLB_LDO18IO_BYPASS_LEN) - 1) << GLB_LDO18IO_BYPASS_POS))
+#define GLB_TEN_LDO18IO               GLB_TEN_LDO18IO
+#define GLB_TEN_LDO18IO_POS           (2U)
+#define GLB_TEN_LDO18IO_LEN           (1U)
+#define GLB_TEN_LDO18IO_MSK           (((1U << GLB_TEN_LDO18IO_LEN) - 1) << GLB_TEN_LDO18IO_POS)
+#define GLB_TEN_LDO18IO_UMSK          (~(((1U << GLB_TEN_LDO18IO_LEN) - 1) << GLB_TEN_LDO18IO_POS))
+#define GLB_LDO18IO_OCP_OUT           GLB_LDO18IO_OCP_OUT
+#define GLB_LDO18IO_OCP_OUT_POS       (3U)
+#define GLB_LDO18IO_OCP_OUT_LEN       (1U)
+#define GLB_LDO18IO_OCP_OUT_MSK       (((1U << GLB_LDO18IO_OCP_OUT_LEN) - 1) << GLB_LDO18IO_OCP_OUT_POS)
+#define GLB_LDO18IO_OCP_OUT_UMSK      (~(((1U << GLB_LDO18IO_OCP_OUT_LEN) - 1) << GLB_LDO18IO_OCP_OUT_POS))
+#define GLB_LDO18IO_BM                GLB_LDO18IO_BM
+#define GLB_LDO18IO_BM_POS            (4U)
+#define GLB_LDO18IO_BM_LEN            (3U)
+#define GLB_LDO18IO_BM_MSK            (((1U << GLB_LDO18IO_BM_LEN) - 1) << GLB_LDO18IO_BM_POS)
+#define GLB_LDO18IO_BM_UMSK           (~(((1U << GLB_LDO18IO_BM_LEN) - 1) << GLB_LDO18IO_BM_POS))
+#define GLB_LDO18IO_CC                GLB_LDO18IO_CC
+#define GLB_LDO18IO_CC_POS            (8U)
+#define GLB_LDO18IO_CC_LEN            (3U)
+#define GLB_LDO18IO_CC_MSK            (((1U << GLB_LDO18IO_CC_LEN) - 1) << GLB_LDO18IO_CC_POS)
+#define GLB_LDO18IO_CC_UMSK           (~(((1U << GLB_LDO18IO_CC_LEN) - 1) << GLB_LDO18IO_CC_POS))
+#define GLB_LDO18IO_OCP_TH            GLB_LDO18IO_OCP_TH
+#define GLB_LDO18IO_OCP_TH_POS        (12U)
+#define GLB_LDO18IO_OCP_TH_LEN        (3U)
+#define GLB_LDO18IO_OCP_TH_MSK        (((1U << GLB_LDO18IO_OCP_TH_LEN) - 1) << GLB_LDO18IO_OCP_TH_POS)
+#define GLB_LDO18IO_OCP_TH_UMSK       (~(((1U << GLB_LDO18IO_OCP_TH_LEN) - 1) << GLB_LDO18IO_OCP_TH_POS))
+#define GLB_LDO18IO_OCP_EN            GLB_LDO18IO_OCP_EN
+#define GLB_LDO18IO_OCP_EN_POS        (15U)
+#define GLB_LDO18IO_OCP_EN_LEN        (1U)
+#define GLB_LDO18IO_OCP_EN_MSK        (((1U << GLB_LDO18IO_OCP_EN_LEN) - 1) << GLB_LDO18IO_OCP_EN_POS)
+#define GLB_LDO18IO_OCP_EN_UMSK       (~(((1U << GLB_LDO18IO_OCP_EN_LEN) - 1) << GLB_LDO18IO_OCP_EN_POS))
+#define GLB_LDO18IO_PULLDOWN          GLB_LDO18IO_PULLDOWN
+#define GLB_LDO18IO_PULLDOWN_POS      (16U)
+#define GLB_LDO18IO_PULLDOWN_LEN      (1U)
+#define GLB_LDO18IO_PULLDOWN_MSK      (((1U << GLB_LDO18IO_PULLDOWN_LEN) - 1) << GLB_LDO18IO_PULLDOWN_POS)
+#define GLB_LDO18IO_PULLDOWN_UMSK     (~(((1U << GLB_LDO18IO_PULLDOWN_LEN) - 1) << GLB_LDO18IO_PULLDOWN_POS))
+#define GLB_LDO18IO_PULLDOWN_SEL      GLB_LDO18IO_PULLDOWN_SEL
+#define GLB_LDO18IO_PULLDOWN_SEL_POS  (17U)
+#define GLB_LDO18IO_PULLDOWN_SEL_LEN  (1U)
+#define GLB_LDO18IO_PULLDOWN_SEL_MSK  (((1U << GLB_LDO18IO_PULLDOWN_SEL_LEN) - 1) << GLB_LDO18IO_PULLDOWN_SEL_POS)
+#define GLB_LDO18IO_PULLDOWN_SEL_UMSK (~(((1U << GLB_LDO18IO_PULLDOWN_SEL_LEN) - 1) << GLB_LDO18IO_PULLDOWN_SEL_POS))
+#define GLB_LDO18IO_SSTART_DELAY      GLB_LDO18IO_SSTART_DELAY
+#define GLB_LDO18IO_SSTART_DELAY_POS  (20U)
+#define GLB_LDO18IO_SSTART_DELAY_LEN  (3U)
+#define GLB_LDO18IO_SSTART_DELAY_MSK  (((1U << GLB_LDO18IO_SSTART_DELAY_LEN) - 1) << GLB_LDO18IO_SSTART_DELAY_POS)
+#define GLB_LDO18IO_SSTART_DELAY_UMSK (~(((1U << GLB_LDO18IO_SSTART_DELAY_LEN) - 1) << GLB_LDO18IO_SSTART_DELAY_POS))
+#define GLB_LDO18IO_SSTART_EN         GLB_LDO18IO_SSTART_EN
+#define GLB_LDO18IO_SSTART_EN_POS     (23U)
+#define GLB_LDO18IO_SSTART_EN_LEN     (1U)
+#define GLB_LDO18IO_SSTART_EN_MSK     (((1U << GLB_LDO18IO_SSTART_EN_LEN) - 1) << GLB_LDO18IO_SSTART_EN_POS)
+#define GLB_LDO18IO_SSTART_EN_UMSK    (~(((1U << GLB_LDO18IO_SSTART_EN_LEN) - 1) << GLB_LDO18IO_SSTART_EN_POS))
+#define GLB_LDO18IO_VOUT_SEL          GLB_LDO18IO_VOUT_SEL
+#define GLB_LDO18IO_VOUT_SEL_POS      (24U)
+#define GLB_LDO18IO_VOUT_SEL_LEN      (4U)
+#define GLB_LDO18IO_VOUT_SEL_MSK      (((1U << GLB_LDO18IO_VOUT_SEL_LEN) - 1) << GLB_LDO18IO_VOUT_SEL_POS)
+#define GLB_LDO18IO_VOUT_SEL_UMSK     (~(((1U << GLB_LDO18IO_VOUT_SEL_LEN) - 1) << GLB_LDO18IO_VOUT_SEL_POS))
+#define GLB_LDO18IO_VOUT_TRIM         GLB_LDO18IO_VOUT_TRIM
+#define GLB_LDO18IO_VOUT_TRIM_POS     (28U)
+#define GLB_LDO18IO_VOUT_TRIM_LEN     (4U)
+#define GLB_LDO18IO_VOUT_TRIM_MSK     (((1U << GLB_LDO18IO_VOUT_TRIM_LEN) - 1) << GLB_LDO18IO_VOUT_TRIM_POS)
+#define GLB_LDO18IO_VOUT_TRIM_UMSK    (~(((1U << GLB_LDO18IO_VOUT_TRIM_LEN) - 1) << GLB_LDO18IO_VOUT_TRIM_POS))
+
+/* 0x8A4 : gauge */
+#define GLB_GAUGE_OFFSET (0x8A4)
+
+/* 0x8C4 : gpio_cfg0 */
+#define GLB_GPIO_CFG0_OFFSET             (0x8C4)
+#define GLB_REG_GPIO_0_IE                GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS            (0U)
+#define GLB_REG_GPIO_0_IE_LEN            (1U)
+#define GLB_REG_GPIO_0_IE_MSK            (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK           (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT               GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS           (1U)
+#define GLB_REG_GPIO_0_SMT_LEN           (1U)
+#define GLB_REG_GPIO_0_SMT_MSK           (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK          (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV               GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS           (2U)
+#define GLB_REG_GPIO_0_DRV_LEN           (2U)
+#define GLB_REG_GPIO_0_DRV_MSK           (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK          (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU                GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS            (4U)
+#define GLB_REG_GPIO_0_PU_LEN            (1U)
+#define GLB_REG_GPIO_0_PU_MSK            (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK           (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD                GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS            (5U)
+#define GLB_REG_GPIO_0_PD_LEN            (1U)
+#define GLB_REG_GPIO_0_PD_MSK            (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK           (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_OE                GLB_REG_GPIO_0_OE
+#define GLB_REG_GPIO_0_OE_POS            (6U)
+#define GLB_REG_GPIO_0_OE_LEN            (1U)
+#define GLB_REG_GPIO_0_OE_MSK            (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
+#define GLB_REG_GPIO_0_OE_UMSK           (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL          GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_0_INT_MODE_SET      GLB_REG_GPIO_0_INT_MODE_SET
+#define GLB_REG_GPIO_0_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_0_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_0_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_0_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_0_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_0_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_0_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_0_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_0_INT_CLR           GLB_REG_GPIO_0_INT_CLR
+#define GLB_REG_GPIO_0_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_0_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_0_INT_CLR_MSK       (((1U << GLB_REG_GPIO_0_INT_CLR_LEN) - 1) << GLB_REG_GPIO_0_INT_CLR_POS)
+#define GLB_REG_GPIO_0_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_0_INT_CLR_LEN) - 1) << GLB_REG_GPIO_0_INT_CLR_POS))
+#define GLB_GPIO_0_INT_STAT              GLB_GPIO_0_INT_STAT
+#define GLB_GPIO_0_INT_STAT_POS          (21U)
+#define GLB_GPIO_0_INT_STAT_LEN          (1U)
+#define GLB_GPIO_0_INT_STAT_MSK          (((1U << GLB_GPIO_0_INT_STAT_LEN) - 1) << GLB_GPIO_0_INT_STAT_POS)
+#define GLB_GPIO_0_INT_STAT_UMSK         (~(((1U << GLB_GPIO_0_INT_STAT_LEN) - 1) << GLB_GPIO_0_INT_STAT_POS))
+#define GLB_REG_GPIO_0_INT_MASK          GLB_REG_GPIO_0_INT_MASK
+#define GLB_REG_GPIO_0_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_0_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_0_INT_MASK_MSK      (((1U << GLB_REG_GPIO_0_INT_MASK_LEN) - 1) << GLB_REG_GPIO_0_INT_MASK_POS)
+#define GLB_REG_GPIO_0_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_0_INT_MASK_LEN) - 1) << GLB_REG_GPIO_0_INT_MASK_POS))
+#define GLB_REG_GPIO_0_O                 GLB_REG_GPIO_0_O
+#define GLB_REG_GPIO_0_O_POS             (24U)
+#define GLB_REG_GPIO_0_O_LEN             (1U)
+#define GLB_REG_GPIO_0_O_MSK             (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
+#define GLB_REG_GPIO_0_O_UMSK            (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
+#define GLB_REG_GPIO_0_SET               GLB_REG_GPIO_0_SET
+#define GLB_REG_GPIO_0_SET_POS           (25U)
+#define GLB_REG_GPIO_0_SET_LEN           (1U)
+#define GLB_REG_GPIO_0_SET_MSK           (((1U << GLB_REG_GPIO_0_SET_LEN) - 1) << GLB_REG_GPIO_0_SET_POS)
+#define GLB_REG_GPIO_0_SET_UMSK          (~(((1U << GLB_REG_GPIO_0_SET_LEN) - 1) << GLB_REG_GPIO_0_SET_POS))
+#define GLB_REG_GPIO_0_CLR               GLB_REG_GPIO_0_CLR
+#define GLB_REG_GPIO_0_CLR_POS           (26U)
+#define GLB_REG_GPIO_0_CLR_LEN           (1U)
+#define GLB_REG_GPIO_0_CLR_MSK           (((1U << GLB_REG_GPIO_0_CLR_LEN) - 1) << GLB_REG_GPIO_0_CLR_POS)
+#define GLB_REG_GPIO_0_CLR_UMSK          (~(((1U << GLB_REG_GPIO_0_CLR_LEN) - 1) << GLB_REG_GPIO_0_CLR_POS))
+#define GLB_REG_GPIO_0_I                 GLB_REG_GPIO_0_I
+#define GLB_REG_GPIO_0_I_POS             (28U)
+#define GLB_REG_GPIO_0_I_LEN             (1U)
+#define GLB_REG_GPIO_0_I_MSK             (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
+#define GLB_REG_GPIO_0_I_UMSK            (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
+#define GLB_REG_GPIO_0_MODE              GLB_REG_GPIO_0_MODE
+#define GLB_REG_GPIO_0_MODE_POS          (30U)
+#define GLB_REG_GPIO_0_MODE_LEN          (2U)
+#define GLB_REG_GPIO_0_MODE_MSK          (((1U << GLB_REG_GPIO_0_MODE_LEN) - 1) << GLB_REG_GPIO_0_MODE_POS)
+#define GLB_REG_GPIO_0_MODE_UMSK         (~(((1U << GLB_REG_GPIO_0_MODE_LEN) - 1) << GLB_REG_GPIO_0_MODE_POS))
+
+/* 0x8C8 : gpio_cfg1 */
+#define GLB_GPIO_CFG1_OFFSET             (0x8C8)
+#define GLB_REG_GPIO_1_IE                GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS            (0U)
+#define GLB_REG_GPIO_1_IE_LEN            (1U)
+#define GLB_REG_GPIO_1_IE_MSK            (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK           (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT               GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS           (1U)
+#define GLB_REG_GPIO_1_SMT_LEN           (1U)
+#define GLB_REG_GPIO_1_SMT_MSK           (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK          (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV               GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS           (2U)
+#define GLB_REG_GPIO_1_DRV_LEN           (2U)
+#define GLB_REG_GPIO_1_DRV_MSK           (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK          (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU                GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS            (4U)
+#define GLB_REG_GPIO_1_PU_LEN            (1U)
+#define GLB_REG_GPIO_1_PU_MSK            (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK           (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD                GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS            (5U)
+#define GLB_REG_GPIO_1_PD_LEN            (1U)
+#define GLB_REG_GPIO_1_PD_MSK            (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK           (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_OE                GLB_REG_GPIO_1_OE
+#define GLB_REG_GPIO_1_OE_POS            (6U)
+#define GLB_REG_GPIO_1_OE_LEN            (1U)
+#define GLB_REG_GPIO_1_OE_MSK            (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
+#define GLB_REG_GPIO_1_OE_UMSK           (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL          GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_INT_MODE_SET      GLB_REG_GPIO_1_INT_MODE_SET
+#define GLB_REG_GPIO_1_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_1_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_1_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_1_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_1_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_1_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_1_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_1_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_1_INT_CLR           GLB_REG_GPIO_1_INT_CLR
+#define GLB_REG_GPIO_1_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_1_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_1_INT_CLR_MSK       (((1U << GLB_REG_GPIO_1_INT_CLR_LEN) - 1) << GLB_REG_GPIO_1_INT_CLR_POS)
+#define GLB_REG_GPIO_1_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_1_INT_CLR_LEN) - 1) << GLB_REG_GPIO_1_INT_CLR_POS))
+#define GLB_GPIO_1_INT_STAT              GLB_GPIO_1_INT_STAT
+#define GLB_GPIO_1_INT_STAT_POS          (21U)
+#define GLB_GPIO_1_INT_STAT_LEN          (1U)
+#define GLB_GPIO_1_INT_STAT_MSK          (((1U << GLB_GPIO_1_INT_STAT_LEN) - 1) << GLB_GPIO_1_INT_STAT_POS)
+#define GLB_GPIO_1_INT_STAT_UMSK         (~(((1U << GLB_GPIO_1_INT_STAT_LEN) - 1) << GLB_GPIO_1_INT_STAT_POS))
+#define GLB_REG_GPIO_1_INT_MASK          GLB_REG_GPIO_1_INT_MASK
+#define GLB_REG_GPIO_1_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_1_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_1_INT_MASK_MSK      (((1U << GLB_REG_GPIO_1_INT_MASK_LEN) - 1) << GLB_REG_GPIO_1_INT_MASK_POS)
+#define GLB_REG_GPIO_1_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_1_INT_MASK_LEN) - 1) << GLB_REG_GPIO_1_INT_MASK_POS))
+#define GLB_REG_GPIO_1_O                 GLB_REG_GPIO_1_O
+#define GLB_REG_GPIO_1_O_POS             (24U)
+#define GLB_REG_GPIO_1_O_LEN             (1U)
+#define GLB_REG_GPIO_1_O_MSK             (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
+#define GLB_REG_GPIO_1_O_UMSK            (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
+#define GLB_REG_GPIO_1_SET               GLB_REG_GPIO_1_SET
+#define GLB_REG_GPIO_1_SET_POS           (25U)
+#define GLB_REG_GPIO_1_SET_LEN           (1U)
+#define GLB_REG_GPIO_1_SET_MSK           (((1U << GLB_REG_GPIO_1_SET_LEN) - 1) << GLB_REG_GPIO_1_SET_POS)
+#define GLB_REG_GPIO_1_SET_UMSK          (~(((1U << GLB_REG_GPIO_1_SET_LEN) - 1) << GLB_REG_GPIO_1_SET_POS))
+#define GLB_REG_GPIO_1_CLR               GLB_REG_GPIO_1_CLR
+#define GLB_REG_GPIO_1_CLR_POS           (26U)
+#define GLB_REG_GPIO_1_CLR_LEN           (1U)
+#define GLB_REG_GPIO_1_CLR_MSK           (((1U << GLB_REG_GPIO_1_CLR_LEN) - 1) << GLB_REG_GPIO_1_CLR_POS)
+#define GLB_REG_GPIO_1_CLR_UMSK          (~(((1U << GLB_REG_GPIO_1_CLR_LEN) - 1) << GLB_REG_GPIO_1_CLR_POS))
+#define GLB_REG_GPIO_1_I                 GLB_REG_GPIO_1_I
+#define GLB_REG_GPIO_1_I_POS             (28U)
+#define GLB_REG_GPIO_1_I_LEN             (1U)
+#define GLB_REG_GPIO_1_I_MSK             (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
+#define GLB_REG_GPIO_1_I_UMSK            (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
+#define GLB_REG_GPIO_1_MODE              GLB_REG_GPIO_1_MODE
+#define GLB_REG_GPIO_1_MODE_POS          (30U)
+#define GLB_REG_GPIO_1_MODE_LEN          (2U)
+#define GLB_REG_GPIO_1_MODE_MSK          (((1U << GLB_REG_GPIO_1_MODE_LEN) - 1) << GLB_REG_GPIO_1_MODE_POS)
+#define GLB_REG_GPIO_1_MODE_UMSK         (~(((1U << GLB_REG_GPIO_1_MODE_LEN) - 1) << GLB_REG_GPIO_1_MODE_POS))
+
+/* 0x8CC : gpio_cfg2 */
+#define GLB_GPIO_CFG2_OFFSET             (0x8CC)
+#define GLB_REG_GPIO_2_IE                GLB_REG_GPIO_2_IE
+#define GLB_REG_GPIO_2_IE_POS            (0U)
+#define GLB_REG_GPIO_2_IE_LEN            (1U)
+#define GLB_REG_GPIO_2_IE_MSK            (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
+#define GLB_REG_GPIO_2_IE_UMSK           (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
+#define GLB_REG_GPIO_2_SMT               GLB_REG_GPIO_2_SMT
+#define GLB_REG_GPIO_2_SMT_POS           (1U)
+#define GLB_REG_GPIO_2_SMT_LEN           (1U)
+#define GLB_REG_GPIO_2_SMT_MSK           (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
+#define GLB_REG_GPIO_2_SMT_UMSK          (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
+#define GLB_REG_GPIO_2_DRV               GLB_REG_GPIO_2_DRV
+#define GLB_REG_GPIO_2_DRV_POS           (2U)
+#define GLB_REG_GPIO_2_DRV_LEN           (2U)
+#define GLB_REG_GPIO_2_DRV_MSK           (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
+#define GLB_REG_GPIO_2_DRV_UMSK          (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
+#define GLB_REG_GPIO_2_PU                GLB_REG_GPIO_2_PU
+#define GLB_REG_GPIO_2_PU_POS            (4U)
+#define GLB_REG_GPIO_2_PU_LEN            (1U)
+#define GLB_REG_GPIO_2_PU_MSK            (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
+#define GLB_REG_GPIO_2_PU_UMSK           (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
+#define GLB_REG_GPIO_2_PD                GLB_REG_GPIO_2_PD
+#define GLB_REG_GPIO_2_PD_POS            (5U)
+#define GLB_REG_GPIO_2_PD_LEN            (1U)
+#define GLB_REG_GPIO_2_PD_MSK            (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
+#define GLB_REG_GPIO_2_PD_UMSK           (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
+#define GLB_REG_GPIO_2_OE                GLB_REG_GPIO_2_OE
+#define GLB_REG_GPIO_2_OE_POS            (6U)
+#define GLB_REG_GPIO_2_OE_LEN            (1U)
+#define GLB_REG_GPIO_2_OE_MSK            (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
+#define GLB_REG_GPIO_2_OE_UMSK           (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
+#define GLB_REG_GPIO_2_FUNC_SEL          GLB_REG_GPIO_2_FUNC_SEL
+#define GLB_REG_GPIO_2_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_2_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_2_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
+#define GLB_REG_GPIO_2_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
+#define GLB_REG_GPIO_2_INT_MODE_SET      GLB_REG_GPIO_2_INT_MODE_SET
+#define GLB_REG_GPIO_2_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_2_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_2_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_2_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_2_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_2_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_2_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_2_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_2_INT_CLR           GLB_REG_GPIO_2_INT_CLR
+#define GLB_REG_GPIO_2_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_2_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_2_INT_CLR_MSK       (((1U << GLB_REG_GPIO_2_INT_CLR_LEN) - 1) << GLB_REG_GPIO_2_INT_CLR_POS)
+#define GLB_REG_GPIO_2_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_2_INT_CLR_LEN) - 1) << GLB_REG_GPIO_2_INT_CLR_POS))
+#define GLB_GPIO_2_INT_STAT              GLB_GPIO_2_INT_STAT
+#define GLB_GPIO_2_INT_STAT_POS          (21U)
+#define GLB_GPIO_2_INT_STAT_LEN          (1U)
+#define GLB_GPIO_2_INT_STAT_MSK          (((1U << GLB_GPIO_2_INT_STAT_LEN) - 1) << GLB_GPIO_2_INT_STAT_POS)
+#define GLB_GPIO_2_INT_STAT_UMSK         (~(((1U << GLB_GPIO_2_INT_STAT_LEN) - 1) << GLB_GPIO_2_INT_STAT_POS))
+#define GLB_REG_GPIO_2_INT_MASK          GLB_REG_GPIO_2_INT_MASK
+#define GLB_REG_GPIO_2_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_2_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_2_INT_MASK_MSK      (((1U << GLB_REG_GPIO_2_INT_MASK_LEN) - 1) << GLB_REG_GPIO_2_INT_MASK_POS)
+#define GLB_REG_GPIO_2_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_2_INT_MASK_LEN) - 1) << GLB_REG_GPIO_2_INT_MASK_POS))
+#define GLB_REG_GPIO_2_O                 GLB_REG_GPIO_2_O
+#define GLB_REG_GPIO_2_O_POS             (24U)
+#define GLB_REG_GPIO_2_O_LEN             (1U)
+#define GLB_REG_GPIO_2_O_MSK             (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
+#define GLB_REG_GPIO_2_O_UMSK            (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
+#define GLB_REG_GPIO_2_SET               GLB_REG_GPIO_2_SET
+#define GLB_REG_GPIO_2_SET_POS           (25U)
+#define GLB_REG_GPIO_2_SET_LEN           (1U)
+#define GLB_REG_GPIO_2_SET_MSK           (((1U << GLB_REG_GPIO_2_SET_LEN) - 1) << GLB_REG_GPIO_2_SET_POS)
+#define GLB_REG_GPIO_2_SET_UMSK          (~(((1U << GLB_REG_GPIO_2_SET_LEN) - 1) << GLB_REG_GPIO_2_SET_POS))
+#define GLB_REG_GPIO_2_CLR               GLB_REG_GPIO_2_CLR
+#define GLB_REG_GPIO_2_CLR_POS           (26U)
+#define GLB_REG_GPIO_2_CLR_LEN           (1U)
+#define GLB_REG_GPIO_2_CLR_MSK           (((1U << GLB_REG_GPIO_2_CLR_LEN) - 1) << GLB_REG_GPIO_2_CLR_POS)
+#define GLB_REG_GPIO_2_CLR_UMSK          (~(((1U << GLB_REG_GPIO_2_CLR_LEN) - 1) << GLB_REG_GPIO_2_CLR_POS))
+#define GLB_REG_GPIO_2_I                 GLB_REG_GPIO_2_I
+#define GLB_REG_GPIO_2_I_POS             (28U)
+#define GLB_REG_GPIO_2_I_LEN             (1U)
+#define GLB_REG_GPIO_2_I_MSK             (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
+#define GLB_REG_GPIO_2_I_UMSK            (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
+#define GLB_REG_GPIO_2_MODE              GLB_REG_GPIO_2_MODE
+#define GLB_REG_GPIO_2_MODE_POS          (30U)
+#define GLB_REG_GPIO_2_MODE_LEN          (2U)
+#define GLB_REG_GPIO_2_MODE_MSK          (((1U << GLB_REG_GPIO_2_MODE_LEN) - 1) << GLB_REG_GPIO_2_MODE_POS)
+#define GLB_REG_GPIO_2_MODE_UMSK         (~(((1U << GLB_REG_GPIO_2_MODE_LEN) - 1) << GLB_REG_GPIO_2_MODE_POS))
+
+/* 0x8D0 : gpio_cfg3 */
+#define GLB_GPIO_CFG3_OFFSET             (0x8D0)
+#define GLB_REG_GPIO_3_IE                GLB_REG_GPIO_3_IE
+#define GLB_REG_GPIO_3_IE_POS            (0U)
+#define GLB_REG_GPIO_3_IE_LEN            (1U)
+#define GLB_REG_GPIO_3_IE_MSK            (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
+#define GLB_REG_GPIO_3_IE_UMSK           (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
+#define GLB_REG_GPIO_3_SMT               GLB_REG_GPIO_3_SMT
+#define GLB_REG_GPIO_3_SMT_POS           (1U)
+#define GLB_REG_GPIO_3_SMT_LEN           (1U)
+#define GLB_REG_GPIO_3_SMT_MSK           (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
+#define GLB_REG_GPIO_3_SMT_UMSK          (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
+#define GLB_REG_GPIO_3_DRV               GLB_REG_GPIO_3_DRV
+#define GLB_REG_GPIO_3_DRV_POS           (2U)
+#define GLB_REG_GPIO_3_DRV_LEN           (2U)
+#define GLB_REG_GPIO_3_DRV_MSK           (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
+#define GLB_REG_GPIO_3_DRV_UMSK          (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
+#define GLB_REG_GPIO_3_PU                GLB_REG_GPIO_3_PU
+#define GLB_REG_GPIO_3_PU_POS            (4U)
+#define GLB_REG_GPIO_3_PU_LEN            (1U)
+#define GLB_REG_GPIO_3_PU_MSK            (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
+#define GLB_REG_GPIO_3_PU_UMSK           (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
+#define GLB_REG_GPIO_3_PD                GLB_REG_GPIO_3_PD
+#define GLB_REG_GPIO_3_PD_POS            (5U)
+#define GLB_REG_GPIO_3_PD_LEN            (1U)
+#define GLB_REG_GPIO_3_PD_MSK            (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
+#define GLB_REG_GPIO_3_PD_UMSK           (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
+#define GLB_REG_GPIO_3_OE                GLB_REG_GPIO_3_OE
+#define GLB_REG_GPIO_3_OE_POS            (6U)
+#define GLB_REG_GPIO_3_OE_LEN            (1U)
+#define GLB_REG_GPIO_3_OE_MSK            (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
+#define GLB_REG_GPIO_3_OE_UMSK           (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
+#define GLB_REG_GPIO_3_FUNC_SEL          GLB_REG_GPIO_3_FUNC_SEL
+#define GLB_REG_GPIO_3_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_3_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_3_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
+#define GLB_REG_GPIO_3_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))
+#define GLB_REG_GPIO_3_INT_MODE_SET      GLB_REG_GPIO_3_INT_MODE_SET
+#define GLB_REG_GPIO_3_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_3_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_3_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_3_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_3_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_3_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_3_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_3_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_3_INT_CLR           GLB_REG_GPIO_3_INT_CLR
+#define GLB_REG_GPIO_3_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_3_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_3_INT_CLR_MSK       (((1U << GLB_REG_GPIO_3_INT_CLR_LEN) - 1) << GLB_REG_GPIO_3_INT_CLR_POS)
+#define GLB_REG_GPIO_3_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_3_INT_CLR_LEN) - 1) << GLB_REG_GPIO_3_INT_CLR_POS))
+#define GLB_GPIO_3_INT_STAT              GLB_GPIO_3_INT_STAT
+#define GLB_GPIO_3_INT_STAT_POS          (21U)
+#define GLB_GPIO_3_INT_STAT_LEN          (1U)
+#define GLB_GPIO_3_INT_STAT_MSK          (((1U << GLB_GPIO_3_INT_STAT_LEN) - 1) << GLB_GPIO_3_INT_STAT_POS)
+#define GLB_GPIO_3_INT_STAT_UMSK         (~(((1U << GLB_GPIO_3_INT_STAT_LEN) - 1) << GLB_GPIO_3_INT_STAT_POS))
+#define GLB_REG_GPIO_3_INT_MASK          GLB_REG_GPIO_3_INT_MASK
+#define GLB_REG_GPIO_3_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_3_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_3_INT_MASK_MSK      (((1U << GLB_REG_GPIO_3_INT_MASK_LEN) - 1) << GLB_REG_GPIO_3_INT_MASK_POS)
+#define GLB_REG_GPIO_3_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_3_INT_MASK_LEN) - 1) << GLB_REG_GPIO_3_INT_MASK_POS))
+#define GLB_REG_GPIO_3_O                 GLB_REG_GPIO_3_O
+#define GLB_REG_GPIO_3_O_POS             (24U)
+#define GLB_REG_GPIO_3_O_LEN             (1U)
+#define GLB_REG_GPIO_3_O_MSK             (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
+#define GLB_REG_GPIO_3_O_UMSK            (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
+#define GLB_REG_GPIO_3_SET               GLB_REG_GPIO_3_SET
+#define GLB_REG_GPIO_3_SET_POS           (25U)
+#define GLB_REG_GPIO_3_SET_LEN           (1U)
+#define GLB_REG_GPIO_3_SET_MSK           (((1U << GLB_REG_GPIO_3_SET_LEN) - 1) << GLB_REG_GPIO_3_SET_POS)
+#define GLB_REG_GPIO_3_SET_UMSK          (~(((1U << GLB_REG_GPIO_3_SET_LEN) - 1) << GLB_REG_GPIO_3_SET_POS))
+#define GLB_REG_GPIO_3_CLR               GLB_REG_GPIO_3_CLR
+#define GLB_REG_GPIO_3_CLR_POS           (26U)
+#define GLB_REG_GPIO_3_CLR_LEN           (1U)
+#define GLB_REG_GPIO_3_CLR_MSK           (((1U << GLB_REG_GPIO_3_CLR_LEN) - 1) << GLB_REG_GPIO_3_CLR_POS)
+#define GLB_REG_GPIO_3_CLR_UMSK          (~(((1U << GLB_REG_GPIO_3_CLR_LEN) - 1) << GLB_REG_GPIO_3_CLR_POS))
+#define GLB_REG_GPIO_3_I                 GLB_REG_GPIO_3_I
+#define GLB_REG_GPIO_3_I_POS             (28U)
+#define GLB_REG_GPIO_3_I_LEN             (1U)
+#define GLB_REG_GPIO_3_I_MSK             (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
+#define GLB_REG_GPIO_3_I_UMSK            (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
+#define GLB_REG_GPIO_3_MODE              GLB_REG_GPIO_3_MODE
+#define GLB_REG_GPIO_3_MODE_POS          (30U)
+#define GLB_REG_GPIO_3_MODE_LEN          (2U)
+#define GLB_REG_GPIO_3_MODE_MSK          (((1U << GLB_REG_GPIO_3_MODE_LEN) - 1) << GLB_REG_GPIO_3_MODE_POS)
+#define GLB_REG_GPIO_3_MODE_UMSK         (~(((1U << GLB_REG_GPIO_3_MODE_LEN) - 1) << GLB_REG_GPIO_3_MODE_POS))
+
+/* 0x8D4 : gpio_cfg4 */
+#define GLB_GPIO_CFG4_OFFSET             (0x8D4)
+#define GLB_REG_GPIO_4_IE                GLB_REG_GPIO_4_IE
+#define GLB_REG_GPIO_4_IE_POS            (0U)
+#define GLB_REG_GPIO_4_IE_LEN            (1U)
+#define GLB_REG_GPIO_4_IE_MSK            (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
+#define GLB_REG_GPIO_4_IE_UMSK           (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
+#define GLB_REG_GPIO_4_SMT               GLB_REG_GPIO_4_SMT
+#define GLB_REG_GPIO_4_SMT_POS           (1U)
+#define GLB_REG_GPIO_4_SMT_LEN           (1U)
+#define GLB_REG_GPIO_4_SMT_MSK           (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
+#define GLB_REG_GPIO_4_SMT_UMSK          (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
+#define GLB_REG_GPIO_4_DRV               GLB_REG_GPIO_4_DRV
+#define GLB_REG_GPIO_4_DRV_POS           (2U)
+#define GLB_REG_GPIO_4_DRV_LEN           (2U)
+#define GLB_REG_GPIO_4_DRV_MSK           (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
+#define GLB_REG_GPIO_4_DRV_UMSK          (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
+#define GLB_REG_GPIO_4_PU                GLB_REG_GPIO_4_PU
+#define GLB_REG_GPIO_4_PU_POS            (4U)
+#define GLB_REG_GPIO_4_PU_LEN            (1U)
+#define GLB_REG_GPIO_4_PU_MSK            (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
+#define GLB_REG_GPIO_4_PU_UMSK           (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
+#define GLB_REG_GPIO_4_PD                GLB_REG_GPIO_4_PD
+#define GLB_REG_GPIO_4_PD_POS            (5U)
+#define GLB_REG_GPIO_4_PD_LEN            (1U)
+#define GLB_REG_GPIO_4_PD_MSK            (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
+#define GLB_REG_GPIO_4_PD_UMSK           (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
+#define GLB_REG_GPIO_4_OE                GLB_REG_GPIO_4_OE
+#define GLB_REG_GPIO_4_OE_POS            (6U)
+#define GLB_REG_GPIO_4_OE_LEN            (1U)
+#define GLB_REG_GPIO_4_OE_MSK            (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
+#define GLB_REG_GPIO_4_OE_UMSK           (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
+#define GLB_REG_GPIO_4_FUNC_SEL          GLB_REG_GPIO_4_FUNC_SEL
+#define GLB_REG_GPIO_4_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_4_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_4_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
+#define GLB_REG_GPIO_4_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
+#define GLB_REG_GPIO_4_INT_MODE_SET      GLB_REG_GPIO_4_INT_MODE_SET
+#define GLB_REG_GPIO_4_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_4_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_4_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_4_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_4_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_4_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_4_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_4_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_4_INT_CLR           GLB_REG_GPIO_4_INT_CLR
+#define GLB_REG_GPIO_4_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_4_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_4_INT_CLR_MSK       (((1U << GLB_REG_GPIO_4_INT_CLR_LEN) - 1) << GLB_REG_GPIO_4_INT_CLR_POS)
+#define GLB_REG_GPIO_4_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_4_INT_CLR_LEN) - 1) << GLB_REG_GPIO_4_INT_CLR_POS))
+#define GLB_GPIO_4_INT_STAT              GLB_GPIO_4_INT_STAT
+#define GLB_GPIO_4_INT_STAT_POS          (21U)
+#define GLB_GPIO_4_INT_STAT_LEN          (1U)
+#define GLB_GPIO_4_INT_STAT_MSK          (((1U << GLB_GPIO_4_INT_STAT_LEN) - 1) << GLB_GPIO_4_INT_STAT_POS)
+#define GLB_GPIO_4_INT_STAT_UMSK         (~(((1U << GLB_GPIO_4_INT_STAT_LEN) - 1) << GLB_GPIO_4_INT_STAT_POS))
+#define GLB_REG_GPIO_4_INT_MASK          GLB_REG_GPIO_4_INT_MASK
+#define GLB_REG_GPIO_4_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_4_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_4_INT_MASK_MSK      (((1U << GLB_REG_GPIO_4_INT_MASK_LEN) - 1) << GLB_REG_GPIO_4_INT_MASK_POS)
+#define GLB_REG_GPIO_4_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_4_INT_MASK_LEN) - 1) << GLB_REG_GPIO_4_INT_MASK_POS))
+#define GLB_REG_GPIO_4_O                 GLB_REG_GPIO_4_O
+#define GLB_REG_GPIO_4_O_POS             (24U)
+#define GLB_REG_GPIO_4_O_LEN             (1U)
+#define GLB_REG_GPIO_4_O_MSK             (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
+#define GLB_REG_GPIO_4_O_UMSK            (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
+#define GLB_REG_GPIO_4_SET               GLB_REG_GPIO_4_SET
+#define GLB_REG_GPIO_4_SET_POS           (25U)
+#define GLB_REG_GPIO_4_SET_LEN           (1U)
+#define GLB_REG_GPIO_4_SET_MSK           (((1U << GLB_REG_GPIO_4_SET_LEN) - 1) << GLB_REG_GPIO_4_SET_POS)
+#define GLB_REG_GPIO_4_SET_UMSK          (~(((1U << GLB_REG_GPIO_4_SET_LEN) - 1) << GLB_REG_GPIO_4_SET_POS))
+#define GLB_REG_GPIO_4_CLR               GLB_REG_GPIO_4_CLR
+#define GLB_REG_GPIO_4_CLR_POS           (26U)
+#define GLB_REG_GPIO_4_CLR_LEN           (1U)
+#define GLB_REG_GPIO_4_CLR_MSK           (((1U << GLB_REG_GPIO_4_CLR_LEN) - 1) << GLB_REG_GPIO_4_CLR_POS)
+#define GLB_REG_GPIO_4_CLR_UMSK          (~(((1U << GLB_REG_GPIO_4_CLR_LEN) - 1) << GLB_REG_GPIO_4_CLR_POS))
+#define GLB_REG_GPIO_4_I                 GLB_REG_GPIO_4_I
+#define GLB_REG_GPIO_4_I_POS             (28U)
+#define GLB_REG_GPIO_4_I_LEN             (1U)
+#define GLB_REG_GPIO_4_I_MSK             (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
+#define GLB_REG_GPIO_4_I_UMSK            (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
+#define GLB_REG_GPIO_4_MODE              GLB_REG_GPIO_4_MODE
+#define GLB_REG_GPIO_4_MODE_POS          (30U)
+#define GLB_REG_GPIO_4_MODE_LEN          (2U)
+#define GLB_REG_GPIO_4_MODE_MSK          (((1U << GLB_REG_GPIO_4_MODE_LEN) - 1) << GLB_REG_GPIO_4_MODE_POS)
+#define GLB_REG_GPIO_4_MODE_UMSK         (~(((1U << GLB_REG_GPIO_4_MODE_LEN) - 1) << GLB_REG_GPIO_4_MODE_POS))
+
+/* 0x8D8 : gpio_cfg5 */
+#define GLB_GPIO_CFG5_OFFSET             (0x8D8)
+#define GLB_REG_GPIO_5_IE                GLB_REG_GPIO_5_IE
+#define GLB_REG_GPIO_5_IE_POS            (0U)
+#define GLB_REG_GPIO_5_IE_LEN            (1U)
+#define GLB_REG_GPIO_5_IE_MSK            (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
+#define GLB_REG_GPIO_5_IE_UMSK           (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
+#define GLB_REG_GPIO_5_SMT               GLB_REG_GPIO_5_SMT
+#define GLB_REG_GPIO_5_SMT_POS           (1U)
+#define GLB_REG_GPIO_5_SMT_LEN           (1U)
+#define GLB_REG_GPIO_5_SMT_MSK           (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
+#define GLB_REG_GPIO_5_SMT_UMSK          (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
+#define GLB_REG_GPIO_5_DRV               GLB_REG_GPIO_5_DRV
+#define GLB_REG_GPIO_5_DRV_POS           (2U)
+#define GLB_REG_GPIO_5_DRV_LEN           (2U)
+#define GLB_REG_GPIO_5_DRV_MSK           (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
+#define GLB_REG_GPIO_5_DRV_UMSK          (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
+#define GLB_REG_GPIO_5_PU                GLB_REG_GPIO_5_PU
+#define GLB_REG_GPIO_5_PU_POS            (4U)
+#define GLB_REG_GPIO_5_PU_LEN            (1U)
+#define GLB_REG_GPIO_5_PU_MSK            (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
+#define GLB_REG_GPIO_5_PU_UMSK           (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
+#define GLB_REG_GPIO_5_PD                GLB_REG_GPIO_5_PD
+#define GLB_REG_GPIO_5_PD_POS            (5U)
+#define GLB_REG_GPIO_5_PD_LEN            (1U)
+#define GLB_REG_GPIO_5_PD_MSK            (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
+#define GLB_REG_GPIO_5_PD_UMSK           (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
+#define GLB_REG_GPIO_5_OE                GLB_REG_GPIO_5_OE
+#define GLB_REG_GPIO_5_OE_POS            (6U)
+#define GLB_REG_GPIO_5_OE_LEN            (1U)
+#define GLB_REG_GPIO_5_OE_MSK            (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
+#define GLB_REG_GPIO_5_OE_UMSK           (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
+#define GLB_REG_GPIO_5_FUNC_SEL          GLB_REG_GPIO_5_FUNC_SEL
+#define GLB_REG_GPIO_5_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_5_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_5_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
+#define GLB_REG_GPIO_5_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))
+#define GLB_REG_GPIO_5_INT_MODE_SET      GLB_REG_GPIO_5_INT_MODE_SET
+#define GLB_REG_GPIO_5_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_5_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_5_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_5_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_5_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_5_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_5_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_5_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_5_INT_CLR           GLB_REG_GPIO_5_INT_CLR
+#define GLB_REG_GPIO_5_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_5_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_5_INT_CLR_MSK       (((1U << GLB_REG_GPIO_5_INT_CLR_LEN) - 1) << GLB_REG_GPIO_5_INT_CLR_POS)
+#define GLB_REG_GPIO_5_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_5_INT_CLR_LEN) - 1) << GLB_REG_GPIO_5_INT_CLR_POS))
+#define GLB_GPIO_5_INT_STAT              GLB_GPIO_5_INT_STAT
+#define GLB_GPIO_5_INT_STAT_POS          (21U)
+#define GLB_GPIO_5_INT_STAT_LEN          (1U)
+#define GLB_GPIO_5_INT_STAT_MSK          (((1U << GLB_GPIO_5_INT_STAT_LEN) - 1) << GLB_GPIO_5_INT_STAT_POS)
+#define GLB_GPIO_5_INT_STAT_UMSK         (~(((1U << GLB_GPIO_5_INT_STAT_LEN) - 1) << GLB_GPIO_5_INT_STAT_POS))
+#define GLB_REG_GPIO_5_INT_MASK          GLB_REG_GPIO_5_INT_MASK
+#define GLB_REG_GPIO_5_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_5_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_5_INT_MASK_MSK      (((1U << GLB_REG_GPIO_5_INT_MASK_LEN) - 1) << GLB_REG_GPIO_5_INT_MASK_POS)
+#define GLB_REG_GPIO_5_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_5_INT_MASK_LEN) - 1) << GLB_REG_GPIO_5_INT_MASK_POS))
+#define GLB_REG_GPIO_5_O                 GLB_REG_GPIO_5_O
+#define GLB_REG_GPIO_5_O_POS             (24U)
+#define GLB_REG_GPIO_5_O_LEN             (1U)
+#define GLB_REG_GPIO_5_O_MSK             (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
+#define GLB_REG_GPIO_5_O_UMSK            (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
+#define GLB_REG_GPIO_5_SET               GLB_REG_GPIO_5_SET
+#define GLB_REG_GPIO_5_SET_POS           (25U)
+#define GLB_REG_GPIO_5_SET_LEN           (1U)
+#define GLB_REG_GPIO_5_SET_MSK           (((1U << GLB_REG_GPIO_5_SET_LEN) - 1) << GLB_REG_GPIO_5_SET_POS)
+#define GLB_REG_GPIO_5_SET_UMSK          (~(((1U << GLB_REG_GPIO_5_SET_LEN) - 1) << GLB_REG_GPIO_5_SET_POS))
+#define GLB_REG_GPIO_5_CLR               GLB_REG_GPIO_5_CLR
+#define GLB_REG_GPIO_5_CLR_POS           (26U)
+#define GLB_REG_GPIO_5_CLR_LEN           (1U)
+#define GLB_REG_GPIO_5_CLR_MSK           (((1U << GLB_REG_GPIO_5_CLR_LEN) - 1) << GLB_REG_GPIO_5_CLR_POS)
+#define GLB_REG_GPIO_5_CLR_UMSK          (~(((1U << GLB_REG_GPIO_5_CLR_LEN) - 1) << GLB_REG_GPIO_5_CLR_POS))
+#define GLB_REG_GPIO_5_I                 GLB_REG_GPIO_5_I
+#define GLB_REG_GPIO_5_I_POS             (28U)
+#define GLB_REG_GPIO_5_I_LEN             (1U)
+#define GLB_REG_GPIO_5_I_MSK             (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
+#define GLB_REG_GPIO_5_I_UMSK            (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
+#define GLB_REG_GPIO_5_MODE              GLB_REG_GPIO_5_MODE
+#define GLB_REG_GPIO_5_MODE_POS          (30U)
+#define GLB_REG_GPIO_5_MODE_LEN          (2U)
+#define GLB_REG_GPIO_5_MODE_MSK          (((1U << GLB_REG_GPIO_5_MODE_LEN) - 1) << GLB_REG_GPIO_5_MODE_POS)
+#define GLB_REG_GPIO_5_MODE_UMSK         (~(((1U << GLB_REG_GPIO_5_MODE_LEN) - 1) << GLB_REG_GPIO_5_MODE_POS))
+
+/* 0x8DC : gpio_cfg6 */
+#define GLB_GPIO_CFG6_OFFSET             (0x8DC)
+#define GLB_REG_GPIO_6_IE                GLB_REG_GPIO_6_IE
+#define GLB_REG_GPIO_6_IE_POS            (0U)
+#define GLB_REG_GPIO_6_IE_LEN            (1U)
+#define GLB_REG_GPIO_6_IE_MSK            (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
+#define GLB_REG_GPIO_6_IE_UMSK           (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
+#define GLB_REG_GPIO_6_SMT               GLB_REG_GPIO_6_SMT
+#define GLB_REG_GPIO_6_SMT_POS           (1U)
+#define GLB_REG_GPIO_6_SMT_LEN           (1U)
+#define GLB_REG_GPIO_6_SMT_MSK           (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
+#define GLB_REG_GPIO_6_SMT_UMSK          (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
+#define GLB_REG_GPIO_6_DRV               GLB_REG_GPIO_6_DRV
+#define GLB_REG_GPIO_6_DRV_POS           (2U)
+#define GLB_REG_GPIO_6_DRV_LEN           (2U)
+#define GLB_REG_GPIO_6_DRV_MSK           (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
+#define GLB_REG_GPIO_6_DRV_UMSK          (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
+#define GLB_REG_GPIO_6_PU                GLB_REG_GPIO_6_PU
+#define GLB_REG_GPIO_6_PU_POS            (4U)
+#define GLB_REG_GPIO_6_PU_LEN            (1U)
+#define GLB_REG_GPIO_6_PU_MSK            (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
+#define GLB_REG_GPIO_6_PU_UMSK           (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
+#define GLB_REG_GPIO_6_PD                GLB_REG_GPIO_6_PD
+#define GLB_REG_GPIO_6_PD_POS            (5U)
+#define GLB_REG_GPIO_6_PD_LEN            (1U)
+#define GLB_REG_GPIO_6_PD_MSK            (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
+#define GLB_REG_GPIO_6_PD_UMSK           (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
+#define GLB_REG_GPIO_6_OE                GLB_REG_GPIO_6_OE
+#define GLB_REG_GPIO_6_OE_POS            (6U)
+#define GLB_REG_GPIO_6_OE_LEN            (1U)
+#define GLB_REG_GPIO_6_OE_MSK            (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
+#define GLB_REG_GPIO_6_OE_UMSK           (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
+#define GLB_REG_GPIO_6_FUNC_SEL          GLB_REG_GPIO_6_FUNC_SEL
+#define GLB_REG_GPIO_6_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_6_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_6_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
+#define GLB_REG_GPIO_6_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
+#define GLB_REG_GPIO_6_INT_MODE_SET      GLB_REG_GPIO_6_INT_MODE_SET
+#define GLB_REG_GPIO_6_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_6_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_6_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_6_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_6_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_6_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_6_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_6_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_6_INT_CLR           GLB_REG_GPIO_6_INT_CLR
+#define GLB_REG_GPIO_6_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_6_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_6_INT_CLR_MSK       (((1U << GLB_REG_GPIO_6_INT_CLR_LEN) - 1) << GLB_REG_GPIO_6_INT_CLR_POS)
+#define GLB_REG_GPIO_6_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_6_INT_CLR_LEN) - 1) << GLB_REG_GPIO_6_INT_CLR_POS))
+#define GLB_GPIO_6_INT_STAT              GLB_GPIO_6_INT_STAT
+#define GLB_GPIO_6_INT_STAT_POS          (21U)
+#define GLB_GPIO_6_INT_STAT_LEN          (1U)
+#define GLB_GPIO_6_INT_STAT_MSK          (((1U << GLB_GPIO_6_INT_STAT_LEN) - 1) << GLB_GPIO_6_INT_STAT_POS)
+#define GLB_GPIO_6_INT_STAT_UMSK         (~(((1U << GLB_GPIO_6_INT_STAT_LEN) - 1) << GLB_GPIO_6_INT_STAT_POS))
+#define GLB_REG_GPIO_6_INT_MASK          GLB_REG_GPIO_6_INT_MASK
+#define GLB_REG_GPIO_6_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_6_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_6_INT_MASK_MSK      (((1U << GLB_REG_GPIO_6_INT_MASK_LEN) - 1) << GLB_REG_GPIO_6_INT_MASK_POS)
+#define GLB_REG_GPIO_6_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_6_INT_MASK_LEN) - 1) << GLB_REG_GPIO_6_INT_MASK_POS))
+#define GLB_REG_GPIO_6_O                 GLB_REG_GPIO_6_O
+#define GLB_REG_GPIO_6_O_POS             (24U)
+#define GLB_REG_GPIO_6_O_LEN             (1U)
+#define GLB_REG_GPIO_6_O_MSK             (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
+#define GLB_REG_GPIO_6_O_UMSK            (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
+#define GLB_REG_GPIO_6_SET               GLB_REG_GPIO_6_SET
+#define GLB_REG_GPIO_6_SET_POS           (25U)
+#define GLB_REG_GPIO_6_SET_LEN           (1U)
+#define GLB_REG_GPIO_6_SET_MSK           (((1U << GLB_REG_GPIO_6_SET_LEN) - 1) << GLB_REG_GPIO_6_SET_POS)
+#define GLB_REG_GPIO_6_SET_UMSK          (~(((1U << GLB_REG_GPIO_6_SET_LEN) - 1) << GLB_REG_GPIO_6_SET_POS))
+#define GLB_REG_GPIO_6_CLR               GLB_REG_GPIO_6_CLR
+#define GLB_REG_GPIO_6_CLR_POS           (26U)
+#define GLB_REG_GPIO_6_CLR_LEN           (1U)
+#define GLB_REG_GPIO_6_CLR_MSK           (((1U << GLB_REG_GPIO_6_CLR_LEN) - 1) << GLB_REG_GPIO_6_CLR_POS)
+#define GLB_REG_GPIO_6_CLR_UMSK          (~(((1U << GLB_REG_GPIO_6_CLR_LEN) - 1) << GLB_REG_GPIO_6_CLR_POS))
+#define GLB_REG_GPIO_6_I                 GLB_REG_GPIO_6_I
+#define GLB_REG_GPIO_6_I_POS             (28U)
+#define GLB_REG_GPIO_6_I_LEN             (1U)
+#define GLB_REG_GPIO_6_I_MSK             (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
+#define GLB_REG_GPIO_6_I_UMSK            (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
+#define GLB_REG_GPIO_6_MODE              GLB_REG_GPIO_6_MODE
+#define GLB_REG_GPIO_6_MODE_POS          (30U)
+#define GLB_REG_GPIO_6_MODE_LEN          (2U)
+#define GLB_REG_GPIO_6_MODE_MSK          (((1U << GLB_REG_GPIO_6_MODE_LEN) - 1) << GLB_REG_GPIO_6_MODE_POS)
+#define GLB_REG_GPIO_6_MODE_UMSK         (~(((1U << GLB_REG_GPIO_6_MODE_LEN) - 1) << GLB_REG_GPIO_6_MODE_POS))
+
+/* 0x8E0 : gpio_cfg7 */
+#define GLB_GPIO_CFG7_OFFSET             (0x8E0)
+#define GLB_REG_GPIO_7_IE                GLB_REG_GPIO_7_IE
+#define GLB_REG_GPIO_7_IE_POS            (0U)
+#define GLB_REG_GPIO_7_IE_LEN            (1U)
+#define GLB_REG_GPIO_7_IE_MSK            (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
+#define GLB_REG_GPIO_7_IE_UMSK           (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
+#define GLB_REG_GPIO_7_SMT               GLB_REG_GPIO_7_SMT
+#define GLB_REG_GPIO_7_SMT_POS           (1U)
+#define GLB_REG_GPIO_7_SMT_LEN           (1U)
+#define GLB_REG_GPIO_7_SMT_MSK           (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
+#define GLB_REG_GPIO_7_SMT_UMSK          (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
+#define GLB_REG_GPIO_7_DRV               GLB_REG_GPIO_7_DRV
+#define GLB_REG_GPIO_7_DRV_POS           (2U)
+#define GLB_REG_GPIO_7_DRV_LEN           (2U)
+#define GLB_REG_GPIO_7_DRV_MSK           (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
+#define GLB_REG_GPIO_7_DRV_UMSK          (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
+#define GLB_REG_GPIO_7_PU                GLB_REG_GPIO_7_PU
+#define GLB_REG_GPIO_7_PU_POS            (4U)
+#define GLB_REG_GPIO_7_PU_LEN            (1U)
+#define GLB_REG_GPIO_7_PU_MSK            (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
+#define GLB_REG_GPIO_7_PU_UMSK           (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
+#define GLB_REG_GPIO_7_PD                GLB_REG_GPIO_7_PD
+#define GLB_REG_GPIO_7_PD_POS            (5U)
+#define GLB_REG_GPIO_7_PD_LEN            (1U)
+#define GLB_REG_GPIO_7_PD_MSK            (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
+#define GLB_REG_GPIO_7_PD_UMSK           (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
+#define GLB_REG_GPIO_7_OE                GLB_REG_GPIO_7_OE
+#define GLB_REG_GPIO_7_OE_POS            (6U)
+#define GLB_REG_GPIO_7_OE_LEN            (1U)
+#define GLB_REG_GPIO_7_OE_MSK            (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
+#define GLB_REG_GPIO_7_OE_UMSK           (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
+#define GLB_REG_GPIO_7_FUNC_SEL          GLB_REG_GPIO_7_FUNC_SEL
+#define GLB_REG_GPIO_7_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_7_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_7_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
+#define GLB_REG_GPIO_7_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))
+#define GLB_REG_GPIO_7_INT_MODE_SET      GLB_REG_GPIO_7_INT_MODE_SET
+#define GLB_REG_GPIO_7_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_7_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_7_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_7_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_7_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_7_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_7_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_7_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_7_INT_CLR           GLB_REG_GPIO_7_INT_CLR
+#define GLB_REG_GPIO_7_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_7_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_7_INT_CLR_MSK       (((1U << GLB_REG_GPIO_7_INT_CLR_LEN) - 1) << GLB_REG_GPIO_7_INT_CLR_POS)
+#define GLB_REG_GPIO_7_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_7_INT_CLR_LEN) - 1) << GLB_REG_GPIO_7_INT_CLR_POS))
+#define GLB_GPIO_7_INT_STAT              GLB_GPIO_7_INT_STAT
+#define GLB_GPIO_7_INT_STAT_POS          (21U)
+#define GLB_GPIO_7_INT_STAT_LEN          (1U)
+#define GLB_GPIO_7_INT_STAT_MSK          (((1U << GLB_GPIO_7_INT_STAT_LEN) - 1) << GLB_GPIO_7_INT_STAT_POS)
+#define GLB_GPIO_7_INT_STAT_UMSK         (~(((1U << GLB_GPIO_7_INT_STAT_LEN) - 1) << GLB_GPIO_7_INT_STAT_POS))
+#define GLB_REG_GPIO_7_INT_MASK          GLB_REG_GPIO_7_INT_MASK
+#define GLB_REG_GPIO_7_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_7_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_7_INT_MASK_MSK      (((1U << GLB_REG_GPIO_7_INT_MASK_LEN) - 1) << GLB_REG_GPIO_7_INT_MASK_POS)
+#define GLB_REG_GPIO_7_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_7_INT_MASK_LEN) - 1) << GLB_REG_GPIO_7_INT_MASK_POS))
+#define GLB_REG_GPIO_7_O                 GLB_REG_GPIO_7_O
+#define GLB_REG_GPIO_7_O_POS             (24U)
+#define GLB_REG_GPIO_7_O_LEN             (1U)
+#define GLB_REG_GPIO_7_O_MSK             (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
+#define GLB_REG_GPIO_7_O_UMSK            (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
+#define GLB_REG_GPIO_7_SET               GLB_REG_GPIO_7_SET
+#define GLB_REG_GPIO_7_SET_POS           (25U)
+#define GLB_REG_GPIO_7_SET_LEN           (1U)
+#define GLB_REG_GPIO_7_SET_MSK           (((1U << GLB_REG_GPIO_7_SET_LEN) - 1) << GLB_REG_GPIO_7_SET_POS)
+#define GLB_REG_GPIO_7_SET_UMSK          (~(((1U << GLB_REG_GPIO_7_SET_LEN) - 1) << GLB_REG_GPIO_7_SET_POS))
+#define GLB_REG_GPIO_7_CLR               GLB_REG_GPIO_7_CLR
+#define GLB_REG_GPIO_7_CLR_POS           (26U)
+#define GLB_REG_GPIO_7_CLR_LEN           (1U)
+#define GLB_REG_GPIO_7_CLR_MSK           (((1U << GLB_REG_GPIO_7_CLR_LEN) - 1) << GLB_REG_GPIO_7_CLR_POS)
+#define GLB_REG_GPIO_7_CLR_UMSK          (~(((1U << GLB_REG_GPIO_7_CLR_LEN) - 1) << GLB_REG_GPIO_7_CLR_POS))
+#define GLB_REG_GPIO_7_I                 GLB_REG_GPIO_7_I
+#define GLB_REG_GPIO_7_I_POS             (28U)
+#define GLB_REG_GPIO_7_I_LEN             (1U)
+#define GLB_REG_GPIO_7_I_MSK             (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
+#define GLB_REG_GPIO_7_I_UMSK            (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
+#define GLB_REG_GPIO_7_MODE              GLB_REG_GPIO_7_MODE
+#define GLB_REG_GPIO_7_MODE_POS          (30U)
+#define GLB_REG_GPIO_7_MODE_LEN          (2U)
+#define GLB_REG_GPIO_7_MODE_MSK          (((1U << GLB_REG_GPIO_7_MODE_LEN) - 1) << GLB_REG_GPIO_7_MODE_POS)
+#define GLB_REG_GPIO_7_MODE_UMSK         (~(((1U << GLB_REG_GPIO_7_MODE_LEN) - 1) << GLB_REG_GPIO_7_MODE_POS))
+
+/* 0x8E4 : gpio_cfg8 */
+#define GLB_GPIO_CFG8_OFFSET             (0x8E4)
+#define GLB_REG_GPIO_8_IE                GLB_REG_GPIO_8_IE
+#define GLB_REG_GPIO_8_IE_POS            (0U)
+#define GLB_REG_GPIO_8_IE_LEN            (1U)
+#define GLB_REG_GPIO_8_IE_MSK            (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
+#define GLB_REG_GPIO_8_IE_UMSK           (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
+#define GLB_REG_GPIO_8_SMT               GLB_REG_GPIO_8_SMT
+#define GLB_REG_GPIO_8_SMT_POS           (1U)
+#define GLB_REG_GPIO_8_SMT_LEN           (1U)
+#define GLB_REG_GPIO_8_SMT_MSK           (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
+#define GLB_REG_GPIO_8_SMT_UMSK          (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
+#define GLB_REG_GPIO_8_DRV               GLB_REG_GPIO_8_DRV
+#define GLB_REG_GPIO_8_DRV_POS           (2U)
+#define GLB_REG_GPIO_8_DRV_LEN           (2U)
+#define GLB_REG_GPIO_8_DRV_MSK           (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
+#define GLB_REG_GPIO_8_DRV_UMSK          (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
+#define GLB_REG_GPIO_8_PU                GLB_REG_GPIO_8_PU
+#define GLB_REG_GPIO_8_PU_POS            (4U)
+#define GLB_REG_GPIO_8_PU_LEN            (1U)
+#define GLB_REG_GPIO_8_PU_MSK            (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
+#define GLB_REG_GPIO_8_PU_UMSK           (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
+#define GLB_REG_GPIO_8_PD                GLB_REG_GPIO_8_PD
+#define GLB_REG_GPIO_8_PD_POS            (5U)
+#define GLB_REG_GPIO_8_PD_LEN            (1U)
+#define GLB_REG_GPIO_8_PD_MSK            (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
+#define GLB_REG_GPIO_8_PD_UMSK           (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
+#define GLB_REG_GPIO_8_OE                GLB_REG_GPIO_8_OE
+#define GLB_REG_GPIO_8_OE_POS            (6U)
+#define GLB_REG_GPIO_8_OE_LEN            (1U)
+#define GLB_REG_GPIO_8_OE_MSK            (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
+#define GLB_REG_GPIO_8_OE_UMSK           (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
+#define GLB_REG_GPIO_8_FUNC_SEL          GLB_REG_GPIO_8_FUNC_SEL
+#define GLB_REG_GPIO_8_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_8_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_8_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
+#define GLB_REG_GPIO_8_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
+#define GLB_REG_GPIO_8_INT_MODE_SET      GLB_REG_GPIO_8_INT_MODE_SET
+#define GLB_REG_GPIO_8_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_8_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_8_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_8_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_8_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_8_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_8_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_8_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_8_INT_CLR           GLB_REG_GPIO_8_INT_CLR
+#define GLB_REG_GPIO_8_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_8_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_8_INT_CLR_MSK       (((1U << GLB_REG_GPIO_8_INT_CLR_LEN) - 1) << GLB_REG_GPIO_8_INT_CLR_POS)
+#define GLB_REG_GPIO_8_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_8_INT_CLR_LEN) - 1) << GLB_REG_GPIO_8_INT_CLR_POS))
+#define GLB_GPIO_8_INT_STAT              GLB_GPIO_8_INT_STAT
+#define GLB_GPIO_8_INT_STAT_POS          (21U)
+#define GLB_GPIO_8_INT_STAT_LEN          (1U)
+#define GLB_GPIO_8_INT_STAT_MSK          (((1U << GLB_GPIO_8_INT_STAT_LEN) - 1) << GLB_GPIO_8_INT_STAT_POS)
+#define GLB_GPIO_8_INT_STAT_UMSK         (~(((1U << GLB_GPIO_8_INT_STAT_LEN) - 1) << GLB_GPIO_8_INT_STAT_POS))
+#define GLB_REG_GPIO_8_INT_MASK          GLB_REG_GPIO_8_INT_MASK
+#define GLB_REG_GPIO_8_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_8_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_8_INT_MASK_MSK      (((1U << GLB_REG_GPIO_8_INT_MASK_LEN) - 1) << GLB_REG_GPIO_8_INT_MASK_POS)
+#define GLB_REG_GPIO_8_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_8_INT_MASK_LEN) - 1) << GLB_REG_GPIO_8_INT_MASK_POS))
+#define GLB_REG_GPIO_8_O                 GLB_REG_GPIO_8_O
+#define GLB_REG_GPIO_8_O_POS             (24U)
+#define GLB_REG_GPIO_8_O_LEN             (1U)
+#define GLB_REG_GPIO_8_O_MSK             (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
+#define GLB_REG_GPIO_8_O_UMSK            (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
+#define GLB_REG_GPIO_8_SET               GLB_REG_GPIO_8_SET
+#define GLB_REG_GPIO_8_SET_POS           (25U)
+#define GLB_REG_GPIO_8_SET_LEN           (1U)
+#define GLB_REG_GPIO_8_SET_MSK           (((1U << GLB_REG_GPIO_8_SET_LEN) - 1) << GLB_REG_GPIO_8_SET_POS)
+#define GLB_REG_GPIO_8_SET_UMSK          (~(((1U << GLB_REG_GPIO_8_SET_LEN) - 1) << GLB_REG_GPIO_8_SET_POS))
+#define GLB_REG_GPIO_8_CLR               GLB_REG_GPIO_8_CLR
+#define GLB_REG_GPIO_8_CLR_POS           (26U)
+#define GLB_REG_GPIO_8_CLR_LEN           (1U)
+#define GLB_REG_GPIO_8_CLR_MSK           (((1U << GLB_REG_GPIO_8_CLR_LEN) - 1) << GLB_REG_GPIO_8_CLR_POS)
+#define GLB_REG_GPIO_8_CLR_UMSK          (~(((1U << GLB_REG_GPIO_8_CLR_LEN) - 1) << GLB_REG_GPIO_8_CLR_POS))
+#define GLB_REG_GPIO_8_I                 GLB_REG_GPIO_8_I
+#define GLB_REG_GPIO_8_I_POS             (28U)
+#define GLB_REG_GPIO_8_I_LEN             (1U)
+#define GLB_REG_GPIO_8_I_MSK             (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
+#define GLB_REG_GPIO_8_I_UMSK            (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
+#define GLB_REG_GPIO_8_MODE              GLB_REG_GPIO_8_MODE
+#define GLB_REG_GPIO_8_MODE_POS          (30U)
+#define GLB_REG_GPIO_8_MODE_LEN          (2U)
+#define GLB_REG_GPIO_8_MODE_MSK          (((1U << GLB_REG_GPIO_8_MODE_LEN) - 1) << GLB_REG_GPIO_8_MODE_POS)
+#define GLB_REG_GPIO_8_MODE_UMSK         (~(((1U << GLB_REG_GPIO_8_MODE_LEN) - 1) << GLB_REG_GPIO_8_MODE_POS))
+
+/* 0x8E8 : gpio_cfg9 */
+#define GLB_GPIO_CFG9_OFFSET             (0x8E8)
+#define GLB_REG_GPIO_9_IE                GLB_REG_GPIO_9_IE
+#define GLB_REG_GPIO_9_IE_POS            (0U)
+#define GLB_REG_GPIO_9_IE_LEN            (1U)
+#define GLB_REG_GPIO_9_IE_MSK            (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
+#define GLB_REG_GPIO_9_IE_UMSK           (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
+#define GLB_REG_GPIO_9_SMT               GLB_REG_GPIO_9_SMT
+#define GLB_REG_GPIO_9_SMT_POS           (1U)
+#define GLB_REG_GPIO_9_SMT_LEN           (1U)
+#define GLB_REG_GPIO_9_SMT_MSK           (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
+#define GLB_REG_GPIO_9_SMT_UMSK          (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
+#define GLB_REG_GPIO_9_DRV               GLB_REG_GPIO_9_DRV
+#define GLB_REG_GPIO_9_DRV_POS           (2U)
+#define GLB_REG_GPIO_9_DRV_LEN           (2U)
+#define GLB_REG_GPIO_9_DRV_MSK           (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
+#define GLB_REG_GPIO_9_DRV_UMSK          (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
+#define GLB_REG_GPIO_9_PU                GLB_REG_GPIO_9_PU
+#define GLB_REG_GPIO_9_PU_POS            (4U)
+#define GLB_REG_GPIO_9_PU_LEN            (1U)
+#define GLB_REG_GPIO_9_PU_MSK            (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
+#define GLB_REG_GPIO_9_PU_UMSK           (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
+#define GLB_REG_GPIO_9_PD                GLB_REG_GPIO_9_PD
+#define GLB_REG_GPIO_9_PD_POS            (5U)
+#define GLB_REG_GPIO_9_PD_LEN            (1U)
+#define GLB_REG_GPIO_9_PD_MSK            (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
+#define GLB_REG_GPIO_9_PD_UMSK           (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
+#define GLB_REG_GPIO_9_OE                GLB_REG_GPIO_9_OE
+#define GLB_REG_GPIO_9_OE_POS            (6U)
+#define GLB_REG_GPIO_9_OE_LEN            (1U)
+#define GLB_REG_GPIO_9_OE_MSK            (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
+#define GLB_REG_GPIO_9_OE_UMSK           (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
+#define GLB_REG_GPIO_9_FUNC_SEL          GLB_REG_GPIO_9_FUNC_SEL
+#define GLB_REG_GPIO_9_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_9_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_9_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
+#define GLB_REG_GPIO_9_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))
+#define GLB_REG_GPIO_9_INT_MODE_SET      GLB_REG_GPIO_9_INT_MODE_SET
+#define GLB_REG_GPIO_9_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_9_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_9_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_9_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_9_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_9_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_9_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_9_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_9_INT_CLR           GLB_REG_GPIO_9_INT_CLR
+#define GLB_REG_GPIO_9_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_9_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_9_INT_CLR_MSK       (((1U << GLB_REG_GPIO_9_INT_CLR_LEN) - 1) << GLB_REG_GPIO_9_INT_CLR_POS)
+#define GLB_REG_GPIO_9_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_9_INT_CLR_LEN) - 1) << GLB_REG_GPIO_9_INT_CLR_POS))
+#define GLB_GPIO_9_INT_STAT              GLB_GPIO_9_INT_STAT
+#define GLB_GPIO_9_INT_STAT_POS          (21U)
+#define GLB_GPIO_9_INT_STAT_LEN          (1U)
+#define GLB_GPIO_9_INT_STAT_MSK          (((1U << GLB_GPIO_9_INT_STAT_LEN) - 1) << GLB_GPIO_9_INT_STAT_POS)
+#define GLB_GPIO_9_INT_STAT_UMSK         (~(((1U << GLB_GPIO_9_INT_STAT_LEN) - 1) << GLB_GPIO_9_INT_STAT_POS))
+#define GLB_REG_GPIO_9_INT_MASK          GLB_REG_GPIO_9_INT_MASK
+#define GLB_REG_GPIO_9_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_9_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_9_INT_MASK_MSK      (((1U << GLB_REG_GPIO_9_INT_MASK_LEN) - 1) << GLB_REG_GPIO_9_INT_MASK_POS)
+#define GLB_REG_GPIO_9_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_9_INT_MASK_LEN) - 1) << GLB_REG_GPIO_9_INT_MASK_POS))
+#define GLB_REG_GPIO_9_O                 GLB_REG_GPIO_9_O
+#define GLB_REG_GPIO_9_O_POS             (24U)
+#define GLB_REG_GPIO_9_O_LEN             (1U)
+#define GLB_REG_GPIO_9_O_MSK             (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
+#define GLB_REG_GPIO_9_O_UMSK            (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
+#define GLB_REG_GPIO_9_SET               GLB_REG_GPIO_9_SET
+#define GLB_REG_GPIO_9_SET_POS           (25U)
+#define GLB_REG_GPIO_9_SET_LEN           (1U)
+#define GLB_REG_GPIO_9_SET_MSK           (((1U << GLB_REG_GPIO_9_SET_LEN) - 1) << GLB_REG_GPIO_9_SET_POS)
+#define GLB_REG_GPIO_9_SET_UMSK          (~(((1U << GLB_REG_GPIO_9_SET_LEN) - 1) << GLB_REG_GPIO_9_SET_POS))
+#define GLB_REG_GPIO_9_CLR               GLB_REG_GPIO_9_CLR
+#define GLB_REG_GPIO_9_CLR_POS           (26U)
+#define GLB_REG_GPIO_9_CLR_LEN           (1U)
+#define GLB_REG_GPIO_9_CLR_MSK           (((1U << GLB_REG_GPIO_9_CLR_LEN) - 1) << GLB_REG_GPIO_9_CLR_POS)
+#define GLB_REG_GPIO_9_CLR_UMSK          (~(((1U << GLB_REG_GPIO_9_CLR_LEN) - 1) << GLB_REG_GPIO_9_CLR_POS))
+#define GLB_REG_GPIO_9_I                 GLB_REG_GPIO_9_I
+#define GLB_REG_GPIO_9_I_POS             (28U)
+#define GLB_REG_GPIO_9_I_LEN             (1U)
+#define GLB_REG_GPIO_9_I_MSK             (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
+#define GLB_REG_GPIO_9_I_UMSK            (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
+#define GLB_REG_GPIO_9_MODE              GLB_REG_GPIO_9_MODE
+#define GLB_REG_GPIO_9_MODE_POS          (30U)
+#define GLB_REG_GPIO_9_MODE_LEN          (2U)
+#define GLB_REG_GPIO_9_MODE_MSK          (((1U << GLB_REG_GPIO_9_MODE_LEN) - 1) << GLB_REG_GPIO_9_MODE_POS)
+#define GLB_REG_GPIO_9_MODE_UMSK         (~(((1U << GLB_REG_GPIO_9_MODE_LEN) - 1) << GLB_REG_GPIO_9_MODE_POS))
+
+/* 0x8EC : gpio_cfg10 */
+#define GLB_GPIO_CFG10_OFFSET             (0x8EC)
+#define GLB_REG_GPIO_10_IE                GLB_REG_GPIO_10_IE
+#define GLB_REG_GPIO_10_IE_POS            (0U)
+#define GLB_REG_GPIO_10_IE_LEN            (1U)
+#define GLB_REG_GPIO_10_IE_MSK            (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
+#define GLB_REG_GPIO_10_IE_UMSK           (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
+#define GLB_REG_GPIO_10_SMT               GLB_REG_GPIO_10_SMT
+#define GLB_REG_GPIO_10_SMT_POS           (1U)
+#define GLB_REG_GPIO_10_SMT_LEN           (1U)
+#define GLB_REG_GPIO_10_SMT_MSK           (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
+#define GLB_REG_GPIO_10_SMT_UMSK          (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
+#define GLB_REG_GPIO_10_DRV               GLB_REG_GPIO_10_DRV
+#define GLB_REG_GPIO_10_DRV_POS           (2U)
+#define GLB_REG_GPIO_10_DRV_LEN           (2U)
+#define GLB_REG_GPIO_10_DRV_MSK           (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
+#define GLB_REG_GPIO_10_DRV_UMSK          (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
+#define GLB_REG_GPIO_10_PU                GLB_REG_GPIO_10_PU
+#define GLB_REG_GPIO_10_PU_POS            (4U)
+#define GLB_REG_GPIO_10_PU_LEN            (1U)
+#define GLB_REG_GPIO_10_PU_MSK            (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
+#define GLB_REG_GPIO_10_PU_UMSK           (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
+#define GLB_REG_GPIO_10_PD                GLB_REG_GPIO_10_PD
+#define GLB_REG_GPIO_10_PD_POS            (5U)
+#define GLB_REG_GPIO_10_PD_LEN            (1U)
+#define GLB_REG_GPIO_10_PD_MSK            (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
+#define GLB_REG_GPIO_10_PD_UMSK           (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
+#define GLB_REG_GPIO_10_OE                GLB_REG_GPIO_10_OE
+#define GLB_REG_GPIO_10_OE_POS            (6U)
+#define GLB_REG_GPIO_10_OE_LEN            (1U)
+#define GLB_REG_GPIO_10_OE_MSK            (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
+#define GLB_REG_GPIO_10_OE_UMSK           (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
+#define GLB_REG_GPIO_10_FUNC_SEL          GLB_REG_GPIO_10_FUNC_SEL
+#define GLB_REG_GPIO_10_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_10_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_10_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
+#define GLB_REG_GPIO_10_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS))
+#define GLB_REG_GPIO_10_INT_MODE_SET      GLB_REG_GPIO_10_INT_MODE_SET
+#define GLB_REG_GPIO_10_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_10_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_10_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_10_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_10_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_10_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_10_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_10_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_10_INT_CLR           GLB_REG_GPIO_10_INT_CLR
+#define GLB_REG_GPIO_10_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_10_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_10_INT_CLR_MSK       (((1U << GLB_REG_GPIO_10_INT_CLR_LEN) - 1) << GLB_REG_GPIO_10_INT_CLR_POS)
+#define GLB_REG_GPIO_10_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_10_INT_CLR_LEN) - 1) << GLB_REG_GPIO_10_INT_CLR_POS))
+#define GLB_GPIO_10_INT_STAT              GLB_GPIO_10_INT_STAT
+#define GLB_GPIO_10_INT_STAT_POS          (21U)
+#define GLB_GPIO_10_INT_STAT_LEN          (1U)
+#define GLB_GPIO_10_INT_STAT_MSK          (((1U << GLB_GPIO_10_INT_STAT_LEN) - 1) << GLB_GPIO_10_INT_STAT_POS)
+#define GLB_GPIO_10_INT_STAT_UMSK         (~(((1U << GLB_GPIO_10_INT_STAT_LEN) - 1) << GLB_GPIO_10_INT_STAT_POS))
+#define GLB_REG_GPIO_10_INT_MASK          GLB_REG_GPIO_10_INT_MASK
+#define GLB_REG_GPIO_10_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_10_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_10_INT_MASK_MSK      (((1U << GLB_REG_GPIO_10_INT_MASK_LEN) - 1) << GLB_REG_GPIO_10_INT_MASK_POS)
+#define GLB_REG_GPIO_10_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_10_INT_MASK_LEN) - 1) << GLB_REG_GPIO_10_INT_MASK_POS))
+#define GLB_REG_GPIO_10_O                 GLB_REG_GPIO_10_O
+#define GLB_REG_GPIO_10_O_POS             (24U)
+#define GLB_REG_GPIO_10_O_LEN             (1U)
+#define GLB_REG_GPIO_10_O_MSK             (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
+#define GLB_REG_GPIO_10_O_UMSK            (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
+#define GLB_REG_GPIO_10_SET               GLB_REG_GPIO_10_SET
+#define GLB_REG_GPIO_10_SET_POS           (25U)
+#define GLB_REG_GPIO_10_SET_LEN           (1U)
+#define GLB_REG_GPIO_10_SET_MSK           (((1U << GLB_REG_GPIO_10_SET_LEN) - 1) << GLB_REG_GPIO_10_SET_POS)
+#define GLB_REG_GPIO_10_SET_UMSK          (~(((1U << GLB_REG_GPIO_10_SET_LEN) - 1) << GLB_REG_GPIO_10_SET_POS))
+#define GLB_REG_GPIO_10_CLR               GLB_REG_GPIO_10_CLR
+#define GLB_REG_GPIO_10_CLR_POS           (26U)
+#define GLB_REG_GPIO_10_CLR_LEN           (1U)
+#define GLB_REG_GPIO_10_CLR_MSK           (((1U << GLB_REG_GPIO_10_CLR_LEN) - 1) << GLB_REG_GPIO_10_CLR_POS)
+#define GLB_REG_GPIO_10_CLR_UMSK          (~(((1U << GLB_REG_GPIO_10_CLR_LEN) - 1) << GLB_REG_GPIO_10_CLR_POS))
+#define GLB_REG_GPIO_10_I                 GLB_REG_GPIO_10_I
+#define GLB_REG_GPIO_10_I_POS             (28U)
+#define GLB_REG_GPIO_10_I_LEN             (1U)
+#define GLB_REG_GPIO_10_I_MSK             (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
+#define GLB_REG_GPIO_10_I_UMSK            (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
+#define GLB_REG_GPIO_10_MODE              GLB_REG_GPIO_10_MODE
+#define GLB_REG_GPIO_10_MODE_POS          (30U)
+#define GLB_REG_GPIO_10_MODE_LEN          (2U)
+#define GLB_REG_GPIO_10_MODE_MSK          (((1U << GLB_REG_GPIO_10_MODE_LEN) - 1) << GLB_REG_GPIO_10_MODE_POS)
+#define GLB_REG_GPIO_10_MODE_UMSK         (~(((1U << GLB_REG_GPIO_10_MODE_LEN) - 1) << GLB_REG_GPIO_10_MODE_POS))
+
+/* 0x8F0 : gpio_cfg11 */
+#define GLB_GPIO_CFG11_OFFSET             (0x8F0)
+#define GLB_REG_GPIO_11_IE                GLB_REG_GPIO_11_IE
+#define GLB_REG_GPIO_11_IE_POS            (0U)
+#define GLB_REG_GPIO_11_IE_LEN            (1U)
+#define GLB_REG_GPIO_11_IE_MSK            (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
+#define GLB_REG_GPIO_11_IE_UMSK           (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
+#define GLB_REG_GPIO_11_SMT               GLB_REG_GPIO_11_SMT
+#define GLB_REG_GPIO_11_SMT_POS           (1U)
+#define GLB_REG_GPIO_11_SMT_LEN           (1U)
+#define GLB_REG_GPIO_11_SMT_MSK           (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
+#define GLB_REG_GPIO_11_SMT_UMSK          (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
+#define GLB_REG_GPIO_11_DRV               GLB_REG_GPIO_11_DRV
+#define GLB_REG_GPIO_11_DRV_POS           (2U)
+#define GLB_REG_GPIO_11_DRV_LEN           (2U)
+#define GLB_REG_GPIO_11_DRV_MSK           (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
+#define GLB_REG_GPIO_11_DRV_UMSK          (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
+#define GLB_REG_GPIO_11_PU                GLB_REG_GPIO_11_PU
+#define GLB_REG_GPIO_11_PU_POS            (4U)
+#define GLB_REG_GPIO_11_PU_LEN            (1U)
+#define GLB_REG_GPIO_11_PU_MSK            (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
+#define GLB_REG_GPIO_11_PU_UMSK           (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
+#define GLB_REG_GPIO_11_PD                GLB_REG_GPIO_11_PD
+#define GLB_REG_GPIO_11_PD_POS            (5U)
+#define GLB_REG_GPIO_11_PD_LEN            (1U)
+#define GLB_REG_GPIO_11_PD_MSK            (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
+#define GLB_REG_GPIO_11_PD_UMSK           (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
+#define GLB_REG_GPIO_11_OE                GLB_REG_GPIO_11_OE
+#define GLB_REG_GPIO_11_OE_POS            (6U)
+#define GLB_REG_GPIO_11_OE_LEN            (1U)
+#define GLB_REG_GPIO_11_OE_MSK            (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
+#define GLB_REG_GPIO_11_OE_UMSK           (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
+#define GLB_REG_GPIO_11_FUNC_SEL          GLB_REG_GPIO_11_FUNC_SEL
+#define GLB_REG_GPIO_11_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_11_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_11_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
+#define GLB_REG_GPIO_11_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS))
+#define GLB_REG_GPIO_11_INT_MODE_SET      GLB_REG_GPIO_11_INT_MODE_SET
+#define GLB_REG_GPIO_11_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_11_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_11_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_11_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_11_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_11_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_11_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_11_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_11_INT_CLR           GLB_REG_GPIO_11_INT_CLR
+#define GLB_REG_GPIO_11_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_11_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_11_INT_CLR_MSK       (((1U << GLB_REG_GPIO_11_INT_CLR_LEN) - 1) << GLB_REG_GPIO_11_INT_CLR_POS)
+#define GLB_REG_GPIO_11_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_11_INT_CLR_LEN) - 1) << GLB_REG_GPIO_11_INT_CLR_POS))
+#define GLB_GPIO_11_INT_STAT              GLB_GPIO_11_INT_STAT
+#define GLB_GPIO_11_INT_STAT_POS          (21U)
+#define GLB_GPIO_11_INT_STAT_LEN          (1U)
+#define GLB_GPIO_11_INT_STAT_MSK          (((1U << GLB_GPIO_11_INT_STAT_LEN) - 1) << GLB_GPIO_11_INT_STAT_POS)
+#define GLB_GPIO_11_INT_STAT_UMSK         (~(((1U << GLB_GPIO_11_INT_STAT_LEN) - 1) << GLB_GPIO_11_INT_STAT_POS))
+#define GLB_REG_GPIO_11_INT_MASK          GLB_REG_GPIO_11_INT_MASK
+#define GLB_REG_GPIO_11_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_11_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_11_INT_MASK_MSK      (((1U << GLB_REG_GPIO_11_INT_MASK_LEN) - 1) << GLB_REG_GPIO_11_INT_MASK_POS)
+#define GLB_REG_GPIO_11_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_11_INT_MASK_LEN) - 1) << GLB_REG_GPIO_11_INT_MASK_POS))
+#define GLB_REG_GPIO_11_O                 GLB_REG_GPIO_11_O
+#define GLB_REG_GPIO_11_O_POS             (24U)
+#define GLB_REG_GPIO_11_O_LEN             (1U)
+#define GLB_REG_GPIO_11_O_MSK             (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
+#define GLB_REG_GPIO_11_O_UMSK            (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
+#define GLB_REG_GPIO_11_SET               GLB_REG_GPIO_11_SET
+#define GLB_REG_GPIO_11_SET_POS           (25U)
+#define GLB_REG_GPIO_11_SET_LEN           (1U)
+#define GLB_REG_GPIO_11_SET_MSK           (((1U << GLB_REG_GPIO_11_SET_LEN) - 1) << GLB_REG_GPIO_11_SET_POS)
+#define GLB_REG_GPIO_11_SET_UMSK          (~(((1U << GLB_REG_GPIO_11_SET_LEN) - 1) << GLB_REG_GPIO_11_SET_POS))
+#define GLB_REG_GPIO_11_CLR               GLB_REG_GPIO_11_CLR
+#define GLB_REG_GPIO_11_CLR_POS           (26U)
+#define GLB_REG_GPIO_11_CLR_LEN           (1U)
+#define GLB_REG_GPIO_11_CLR_MSK           (((1U << GLB_REG_GPIO_11_CLR_LEN) - 1) << GLB_REG_GPIO_11_CLR_POS)
+#define GLB_REG_GPIO_11_CLR_UMSK          (~(((1U << GLB_REG_GPIO_11_CLR_LEN) - 1) << GLB_REG_GPIO_11_CLR_POS))
+#define GLB_REG_GPIO_11_I                 GLB_REG_GPIO_11_I
+#define GLB_REG_GPIO_11_I_POS             (28U)
+#define GLB_REG_GPIO_11_I_LEN             (1U)
+#define GLB_REG_GPIO_11_I_MSK             (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
+#define GLB_REG_GPIO_11_I_UMSK            (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
+#define GLB_REG_GPIO_11_MODE              GLB_REG_GPIO_11_MODE
+#define GLB_REG_GPIO_11_MODE_POS          (30U)
+#define GLB_REG_GPIO_11_MODE_LEN          (2U)
+#define GLB_REG_GPIO_11_MODE_MSK          (((1U << GLB_REG_GPIO_11_MODE_LEN) - 1) << GLB_REG_GPIO_11_MODE_POS)
+#define GLB_REG_GPIO_11_MODE_UMSK         (~(((1U << GLB_REG_GPIO_11_MODE_LEN) - 1) << GLB_REG_GPIO_11_MODE_POS))
+
+/* 0x8F4 : gpio_cfg12 */
+#define GLB_GPIO_CFG12_OFFSET             (0x8F4)
+#define GLB_REG_GPIO_12_IE                GLB_REG_GPIO_12_IE
+#define GLB_REG_GPIO_12_IE_POS            (0U)
+#define GLB_REG_GPIO_12_IE_LEN            (1U)
+#define GLB_REG_GPIO_12_IE_MSK            (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
+#define GLB_REG_GPIO_12_IE_UMSK           (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
+#define GLB_REG_GPIO_12_SMT               GLB_REG_GPIO_12_SMT
+#define GLB_REG_GPIO_12_SMT_POS           (1U)
+#define GLB_REG_GPIO_12_SMT_LEN           (1U)
+#define GLB_REG_GPIO_12_SMT_MSK           (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
+#define GLB_REG_GPIO_12_SMT_UMSK          (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
+#define GLB_REG_GPIO_12_DRV               GLB_REG_GPIO_12_DRV
+#define GLB_REG_GPIO_12_DRV_POS           (2U)
+#define GLB_REG_GPIO_12_DRV_LEN           (2U)
+#define GLB_REG_GPIO_12_DRV_MSK           (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
+#define GLB_REG_GPIO_12_DRV_UMSK          (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
+#define GLB_REG_GPIO_12_PU                GLB_REG_GPIO_12_PU
+#define GLB_REG_GPIO_12_PU_POS            (4U)
+#define GLB_REG_GPIO_12_PU_LEN            (1U)
+#define GLB_REG_GPIO_12_PU_MSK            (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
+#define GLB_REG_GPIO_12_PU_UMSK           (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
+#define GLB_REG_GPIO_12_PD                GLB_REG_GPIO_12_PD
+#define GLB_REG_GPIO_12_PD_POS            (5U)
+#define GLB_REG_GPIO_12_PD_LEN            (1U)
+#define GLB_REG_GPIO_12_PD_MSK            (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
+#define GLB_REG_GPIO_12_PD_UMSK           (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
+#define GLB_REG_GPIO_12_OE                GLB_REG_GPIO_12_OE
+#define GLB_REG_GPIO_12_OE_POS            (6U)
+#define GLB_REG_GPIO_12_OE_LEN            (1U)
+#define GLB_REG_GPIO_12_OE_MSK            (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
+#define GLB_REG_GPIO_12_OE_UMSK           (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
+#define GLB_REG_GPIO_12_FUNC_SEL          GLB_REG_GPIO_12_FUNC_SEL
+#define GLB_REG_GPIO_12_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_12_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_12_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
+#define GLB_REG_GPIO_12_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS))
+#define GLB_REG_GPIO_12_INT_MODE_SET      GLB_REG_GPIO_12_INT_MODE_SET
+#define GLB_REG_GPIO_12_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_12_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_12_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_12_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_12_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_12_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_12_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_12_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_12_INT_CLR           GLB_REG_GPIO_12_INT_CLR
+#define GLB_REG_GPIO_12_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_12_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_12_INT_CLR_MSK       (((1U << GLB_REG_GPIO_12_INT_CLR_LEN) - 1) << GLB_REG_GPIO_12_INT_CLR_POS)
+#define GLB_REG_GPIO_12_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_12_INT_CLR_LEN) - 1) << GLB_REG_GPIO_12_INT_CLR_POS))
+#define GLB_GPIO_12_INT_STAT              GLB_GPIO_12_INT_STAT
+#define GLB_GPIO_12_INT_STAT_POS          (21U)
+#define GLB_GPIO_12_INT_STAT_LEN          (1U)
+#define GLB_GPIO_12_INT_STAT_MSK          (((1U << GLB_GPIO_12_INT_STAT_LEN) - 1) << GLB_GPIO_12_INT_STAT_POS)
+#define GLB_GPIO_12_INT_STAT_UMSK         (~(((1U << GLB_GPIO_12_INT_STAT_LEN) - 1) << GLB_GPIO_12_INT_STAT_POS))
+#define GLB_REG_GPIO_12_INT_MASK          GLB_REG_GPIO_12_INT_MASK
+#define GLB_REG_GPIO_12_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_12_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_12_INT_MASK_MSK      (((1U << GLB_REG_GPIO_12_INT_MASK_LEN) - 1) << GLB_REG_GPIO_12_INT_MASK_POS)
+#define GLB_REG_GPIO_12_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_12_INT_MASK_LEN) - 1) << GLB_REG_GPIO_12_INT_MASK_POS))
+#define GLB_REG_GPIO_12_O                 GLB_REG_GPIO_12_O
+#define GLB_REG_GPIO_12_O_POS             (24U)
+#define GLB_REG_GPIO_12_O_LEN             (1U)
+#define GLB_REG_GPIO_12_O_MSK             (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
+#define GLB_REG_GPIO_12_O_UMSK            (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
+#define GLB_REG_GPIO_12_SET               GLB_REG_GPIO_12_SET
+#define GLB_REG_GPIO_12_SET_POS           (25U)
+#define GLB_REG_GPIO_12_SET_LEN           (1U)
+#define GLB_REG_GPIO_12_SET_MSK           (((1U << GLB_REG_GPIO_12_SET_LEN) - 1) << GLB_REG_GPIO_12_SET_POS)
+#define GLB_REG_GPIO_12_SET_UMSK          (~(((1U << GLB_REG_GPIO_12_SET_LEN) - 1) << GLB_REG_GPIO_12_SET_POS))
+#define GLB_REG_GPIO_12_CLR               GLB_REG_GPIO_12_CLR
+#define GLB_REG_GPIO_12_CLR_POS           (26U)
+#define GLB_REG_GPIO_12_CLR_LEN           (1U)
+#define GLB_REG_GPIO_12_CLR_MSK           (((1U << GLB_REG_GPIO_12_CLR_LEN) - 1) << GLB_REG_GPIO_12_CLR_POS)
+#define GLB_REG_GPIO_12_CLR_UMSK          (~(((1U << GLB_REG_GPIO_12_CLR_LEN) - 1) << GLB_REG_GPIO_12_CLR_POS))
+#define GLB_REG_GPIO_12_I                 GLB_REG_GPIO_12_I
+#define GLB_REG_GPIO_12_I_POS             (28U)
+#define GLB_REG_GPIO_12_I_LEN             (1U)
+#define GLB_REG_GPIO_12_I_MSK             (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
+#define GLB_REG_GPIO_12_I_UMSK            (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
+#define GLB_REG_GPIO_12_MODE              GLB_REG_GPIO_12_MODE
+#define GLB_REG_GPIO_12_MODE_POS          (30U)
+#define GLB_REG_GPIO_12_MODE_LEN          (2U)
+#define GLB_REG_GPIO_12_MODE_MSK          (((1U << GLB_REG_GPIO_12_MODE_LEN) - 1) << GLB_REG_GPIO_12_MODE_POS)
+#define GLB_REG_GPIO_12_MODE_UMSK         (~(((1U << GLB_REG_GPIO_12_MODE_LEN) - 1) << GLB_REG_GPIO_12_MODE_POS))
+
+/* 0x8F8 : gpio_cfg13 */
+#define GLB_GPIO_CFG13_OFFSET             (0x8F8)
+#define GLB_REG_GPIO_13_IE                GLB_REG_GPIO_13_IE
+#define GLB_REG_GPIO_13_IE_POS            (0U)
+#define GLB_REG_GPIO_13_IE_LEN            (1U)
+#define GLB_REG_GPIO_13_IE_MSK            (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
+#define GLB_REG_GPIO_13_IE_UMSK           (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
+#define GLB_REG_GPIO_13_SMT               GLB_REG_GPIO_13_SMT
+#define GLB_REG_GPIO_13_SMT_POS           (1U)
+#define GLB_REG_GPIO_13_SMT_LEN           (1U)
+#define GLB_REG_GPIO_13_SMT_MSK           (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
+#define GLB_REG_GPIO_13_SMT_UMSK          (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
+#define GLB_REG_GPIO_13_DRV               GLB_REG_GPIO_13_DRV
+#define GLB_REG_GPIO_13_DRV_POS           (2U)
+#define GLB_REG_GPIO_13_DRV_LEN           (2U)
+#define GLB_REG_GPIO_13_DRV_MSK           (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
+#define GLB_REG_GPIO_13_DRV_UMSK          (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
+#define GLB_REG_GPIO_13_PU                GLB_REG_GPIO_13_PU
+#define GLB_REG_GPIO_13_PU_POS            (4U)
+#define GLB_REG_GPIO_13_PU_LEN            (1U)
+#define GLB_REG_GPIO_13_PU_MSK            (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
+#define GLB_REG_GPIO_13_PU_UMSK           (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
+#define GLB_REG_GPIO_13_PD                GLB_REG_GPIO_13_PD
+#define GLB_REG_GPIO_13_PD_POS            (5U)
+#define GLB_REG_GPIO_13_PD_LEN            (1U)
+#define GLB_REG_GPIO_13_PD_MSK            (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
+#define GLB_REG_GPIO_13_PD_UMSK           (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
+#define GLB_REG_GPIO_13_OE                GLB_REG_GPIO_13_OE
+#define GLB_REG_GPIO_13_OE_POS            (6U)
+#define GLB_REG_GPIO_13_OE_LEN            (1U)
+#define GLB_REG_GPIO_13_OE_MSK            (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
+#define GLB_REG_GPIO_13_OE_UMSK           (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
+#define GLB_REG_GPIO_13_FUNC_SEL          GLB_REG_GPIO_13_FUNC_SEL
+#define GLB_REG_GPIO_13_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_13_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_13_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
+#define GLB_REG_GPIO_13_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS))
+#define GLB_REG_GPIO_13_INT_MODE_SET      GLB_REG_GPIO_13_INT_MODE_SET
+#define GLB_REG_GPIO_13_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_13_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_13_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_13_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_13_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_13_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_13_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_13_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_13_INT_CLR           GLB_REG_GPIO_13_INT_CLR
+#define GLB_REG_GPIO_13_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_13_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_13_INT_CLR_MSK       (((1U << GLB_REG_GPIO_13_INT_CLR_LEN) - 1) << GLB_REG_GPIO_13_INT_CLR_POS)
+#define GLB_REG_GPIO_13_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_13_INT_CLR_LEN) - 1) << GLB_REG_GPIO_13_INT_CLR_POS))
+#define GLB_GPIO_13_INT_STAT              GLB_GPIO_13_INT_STAT
+#define GLB_GPIO_13_INT_STAT_POS          (21U)
+#define GLB_GPIO_13_INT_STAT_LEN          (1U)
+#define GLB_GPIO_13_INT_STAT_MSK          (((1U << GLB_GPIO_13_INT_STAT_LEN) - 1) << GLB_GPIO_13_INT_STAT_POS)
+#define GLB_GPIO_13_INT_STAT_UMSK         (~(((1U << GLB_GPIO_13_INT_STAT_LEN) - 1) << GLB_GPIO_13_INT_STAT_POS))
+#define GLB_REG_GPIO_13_INT_MASK          GLB_REG_GPIO_13_INT_MASK
+#define GLB_REG_GPIO_13_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_13_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_13_INT_MASK_MSK      (((1U << GLB_REG_GPIO_13_INT_MASK_LEN) - 1) << GLB_REG_GPIO_13_INT_MASK_POS)
+#define GLB_REG_GPIO_13_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_13_INT_MASK_LEN) - 1) << GLB_REG_GPIO_13_INT_MASK_POS))
+#define GLB_REG_GPIO_13_O                 GLB_REG_GPIO_13_O
+#define GLB_REG_GPIO_13_O_POS             (24U)
+#define GLB_REG_GPIO_13_O_LEN             (1U)
+#define GLB_REG_GPIO_13_O_MSK             (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
+#define GLB_REG_GPIO_13_O_UMSK            (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
+#define GLB_REG_GPIO_13_SET               GLB_REG_GPIO_13_SET
+#define GLB_REG_GPIO_13_SET_POS           (25U)
+#define GLB_REG_GPIO_13_SET_LEN           (1U)
+#define GLB_REG_GPIO_13_SET_MSK           (((1U << GLB_REG_GPIO_13_SET_LEN) - 1) << GLB_REG_GPIO_13_SET_POS)
+#define GLB_REG_GPIO_13_SET_UMSK          (~(((1U << GLB_REG_GPIO_13_SET_LEN) - 1) << GLB_REG_GPIO_13_SET_POS))
+#define GLB_REG_GPIO_13_CLR               GLB_REG_GPIO_13_CLR
+#define GLB_REG_GPIO_13_CLR_POS           (26U)
+#define GLB_REG_GPIO_13_CLR_LEN           (1U)
+#define GLB_REG_GPIO_13_CLR_MSK           (((1U << GLB_REG_GPIO_13_CLR_LEN) - 1) << GLB_REG_GPIO_13_CLR_POS)
+#define GLB_REG_GPIO_13_CLR_UMSK          (~(((1U << GLB_REG_GPIO_13_CLR_LEN) - 1) << GLB_REG_GPIO_13_CLR_POS))
+#define GLB_REG_GPIO_13_I                 GLB_REG_GPIO_13_I
+#define GLB_REG_GPIO_13_I_POS             (28U)
+#define GLB_REG_GPIO_13_I_LEN             (1U)
+#define GLB_REG_GPIO_13_I_MSK             (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
+#define GLB_REG_GPIO_13_I_UMSK            (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
+#define GLB_REG_GPIO_13_MODE              GLB_REG_GPIO_13_MODE
+#define GLB_REG_GPIO_13_MODE_POS          (30U)
+#define GLB_REG_GPIO_13_MODE_LEN          (2U)
+#define GLB_REG_GPIO_13_MODE_MSK          (((1U << GLB_REG_GPIO_13_MODE_LEN) - 1) << GLB_REG_GPIO_13_MODE_POS)
+#define GLB_REG_GPIO_13_MODE_UMSK         (~(((1U << GLB_REG_GPIO_13_MODE_LEN) - 1) << GLB_REG_GPIO_13_MODE_POS))
+
+/* 0x8FC : gpio_cfg14 */
+#define GLB_GPIO_CFG14_OFFSET             (0x8FC)
+#define GLB_REG_GPIO_14_IE                GLB_REG_GPIO_14_IE
+#define GLB_REG_GPIO_14_IE_POS            (0U)
+#define GLB_REG_GPIO_14_IE_LEN            (1U)
+#define GLB_REG_GPIO_14_IE_MSK            (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
+#define GLB_REG_GPIO_14_IE_UMSK           (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
+#define GLB_REG_GPIO_14_SMT               GLB_REG_GPIO_14_SMT
+#define GLB_REG_GPIO_14_SMT_POS           (1U)
+#define GLB_REG_GPIO_14_SMT_LEN           (1U)
+#define GLB_REG_GPIO_14_SMT_MSK           (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
+#define GLB_REG_GPIO_14_SMT_UMSK          (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
+#define GLB_REG_GPIO_14_DRV               GLB_REG_GPIO_14_DRV
+#define GLB_REG_GPIO_14_DRV_POS           (2U)
+#define GLB_REG_GPIO_14_DRV_LEN           (2U)
+#define GLB_REG_GPIO_14_DRV_MSK           (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
+#define GLB_REG_GPIO_14_DRV_UMSK          (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
+#define GLB_REG_GPIO_14_PU                GLB_REG_GPIO_14_PU
+#define GLB_REG_GPIO_14_PU_POS            (4U)
+#define GLB_REG_GPIO_14_PU_LEN            (1U)
+#define GLB_REG_GPIO_14_PU_MSK            (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
+#define GLB_REG_GPIO_14_PU_UMSK           (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
+#define GLB_REG_GPIO_14_PD                GLB_REG_GPIO_14_PD
+#define GLB_REG_GPIO_14_PD_POS            (5U)
+#define GLB_REG_GPIO_14_PD_LEN            (1U)
+#define GLB_REG_GPIO_14_PD_MSK            (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
+#define GLB_REG_GPIO_14_PD_UMSK           (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
+#define GLB_REG_GPIO_14_OE                GLB_REG_GPIO_14_OE
+#define GLB_REG_GPIO_14_OE_POS            (6U)
+#define GLB_REG_GPIO_14_OE_LEN            (1U)
+#define GLB_REG_GPIO_14_OE_MSK            (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
+#define GLB_REG_GPIO_14_OE_UMSK           (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
+#define GLB_REG_GPIO_14_FUNC_SEL          GLB_REG_GPIO_14_FUNC_SEL
+#define GLB_REG_GPIO_14_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_14_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_14_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
+#define GLB_REG_GPIO_14_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS))
+#define GLB_REG_GPIO_14_INT_MODE_SET      GLB_REG_GPIO_14_INT_MODE_SET
+#define GLB_REG_GPIO_14_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_14_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_14_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_14_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_14_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_14_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_14_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_14_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_14_INT_CLR           GLB_REG_GPIO_14_INT_CLR
+#define GLB_REG_GPIO_14_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_14_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_14_INT_CLR_MSK       (((1U << GLB_REG_GPIO_14_INT_CLR_LEN) - 1) << GLB_REG_GPIO_14_INT_CLR_POS)
+#define GLB_REG_GPIO_14_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_14_INT_CLR_LEN) - 1) << GLB_REG_GPIO_14_INT_CLR_POS))
+#define GLB_GPIO_14_INT_STAT              GLB_GPIO_14_INT_STAT
+#define GLB_GPIO_14_INT_STAT_POS          (21U)
+#define GLB_GPIO_14_INT_STAT_LEN          (1U)
+#define GLB_GPIO_14_INT_STAT_MSK          (((1U << GLB_GPIO_14_INT_STAT_LEN) - 1) << GLB_GPIO_14_INT_STAT_POS)
+#define GLB_GPIO_14_INT_STAT_UMSK         (~(((1U << GLB_GPIO_14_INT_STAT_LEN) - 1) << GLB_GPIO_14_INT_STAT_POS))
+#define GLB_REG_GPIO_14_INT_MASK          GLB_REG_GPIO_14_INT_MASK
+#define GLB_REG_GPIO_14_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_14_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_14_INT_MASK_MSK      (((1U << GLB_REG_GPIO_14_INT_MASK_LEN) - 1) << GLB_REG_GPIO_14_INT_MASK_POS)
+#define GLB_REG_GPIO_14_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_14_INT_MASK_LEN) - 1) << GLB_REG_GPIO_14_INT_MASK_POS))
+#define GLB_REG_GPIO_14_O                 GLB_REG_GPIO_14_O
+#define GLB_REG_GPIO_14_O_POS             (24U)
+#define GLB_REG_GPIO_14_O_LEN             (1U)
+#define GLB_REG_GPIO_14_O_MSK             (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
+#define GLB_REG_GPIO_14_O_UMSK            (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
+#define GLB_REG_GPIO_14_SET               GLB_REG_GPIO_14_SET
+#define GLB_REG_GPIO_14_SET_POS           (25U)
+#define GLB_REG_GPIO_14_SET_LEN           (1U)
+#define GLB_REG_GPIO_14_SET_MSK           (((1U << GLB_REG_GPIO_14_SET_LEN) - 1) << GLB_REG_GPIO_14_SET_POS)
+#define GLB_REG_GPIO_14_SET_UMSK          (~(((1U << GLB_REG_GPIO_14_SET_LEN) - 1) << GLB_REG_GPIO_14_SET_POS))
+#define GLB_REG_GPIO_14_CLR               GLB_REG_GPIO_14_CLR
+#define GLB_REG_GPIO_14_CLR_POS           (26U)
+#define GLB_REG_GPIO_14_CLR_LEN           (1U)
+#define GLB_REG_GPIO_14_CLR_MSK           (((1U << GLB_REG_GPIO_14_CLR_LEN) - 1) << GLB_REG_GPIO_14_CLR_POS)
+#define GLB_REG_GPIO_14_CLR_UMSK          (~(((1U << GLB_REG_GPIO_14_CLR_LEN) - 1) << GLB_REG_GPIO_14_CLR_POS))
+#define GLB_REG_GPIO_14_I                 GLB_REG_GPIO_14_I
+#define GLB_REG_GPIO_14_I_POS             (28U)
+#define GLB_REG_GPIO_14_I_LEN             (1U)
+#define GLB_REG_GPIO_14_I_MSK             (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
+#define GLB_REG_GPIO_14_I_UMSK            (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
+#define GLB_REG_GPIO_14_MODE              GLB_REG_GPIO_14_MODE
+#define GLB_REG_GPIO_14_MODE_POS          (30U)
+#define GLB_REG_GPIO_14_MODE_LEN          (2U)
+#define GLB_REG_GPIO_14_MODE_MSK          (((1U << GLB_REG_GPIO_14_MODE_LEN) - 1) << GLB_REG_GPIO_14_MODE_POS)
+#define GLB_REG_GPIO_14_MODE_UMSK         (~(((1U << GLB_REG_GPIO_14_MODE_LEN) - 1) << GLB_REG_GPIO_14_MODE_POS))
+
+/* 0x900 : gpio_cfg15 */
+#define GLB_GPIO_CFG15_OFFSET             (0x900)
+#define GLB_REG_GPIO_15_IE                GLB_REG_GPIO_15_IE
+#define GLB_REG_GPIO_15_IE_POS            (0U)
+#define GLB_REG_GPIO_15_IE_LEN            (1U)
+#define GLB_REG_GPIO_15_IE_MSK            (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
+#define GLB_REG_GPIO_15_IE_UMSK           (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
+#define GLB_REG_GPIO_15_SMT               GLB_REG_GPIO_15_SMT
+#define GLB_REG_GPIO_15_SMT_POS           (1U)
+#define GLB_REG_GPIO_15_SMT_LEN           (1U)
+#define GLB_REG_GPIO_15_SMT_MSK           (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
+#define GLB_REG_GPIO_15_SMT_UMSK          (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
+#define GLB_REG_GPIO_15_DRV               GLB_REG_GPIO_15_DRV
+#define GLB_REG_GPIO_15_DRV_POS           (2U)
+#define GLB_REG_GPIO_15_DRV_LEN           (2U)
+#define GLB_REG_GPIO_15_DRV_MSK           (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
+#define GLB_REG_GPIO_15_DRV_UMSK          (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
+#define GLB_REG_GPIO_15_PU                GLB_REG_GPIO_15_PU
+#define GLB_REG_GPIO_15_PU_POS            (4U)
+#define GLB_REG_GPIO_15_PU_LEN            (1U)
+#define GLB_REG_GPIO_15_PU_MSK            (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
+#define GLB_REG_GPIO_15_PU_UMSK           (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
+#define GLB_REG_GPIO_15_PD                GLB_REG_GPIO_15_PD
+#define GLB_REG_GPIO_15_PD_POS            (5U)
+#define GLB_REG_GPIO_15_PD_LEN            (1U)
+#define GLB_REG_GPIO_15_PD_MSK            (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
+#define GLB_REG_GPIO_15_PD_UMSK           (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
+#define GLB_REG_GPIO_15_OE                GLB_REG_GPIO_15_OE
+#define GLB_REG_GPIO_15_OE_POS            (6U)
+#define GLB_REG_GPIO_15_OE_LEN            (1U)
+#define GLB_REG_GPIO_15_OE_MSK            (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
+#define GLB_REG_GPIO_15_OE_UMSK           (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
+#define GLB_REG_GPIO_15_FUNC_SEL          GLB_REG_GPIO_15_FUNC_SEL
+#define GLB_REG_GPIO_15_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_15_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_15_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
+#define GLB_REG_GPIO_15_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS))
+#define GLB_REG_GPIO_15_INT_MODE_SET      GLB_REG_GPIO_15_INT_MODE_SET
+#define GLB_REG_GPIO_15_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_15_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_15_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_15_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_15_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_15_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_15_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_15_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_15_INT_CLR           GLB_REG_GPIO_15_INT_CLR
+#define GLB_REG_GPIO_15_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_15_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_15_INT_CLR_MSK       (((1U << GLB_REG_GPIO_15_INT_CLR_LEN) - 1) << GLB_REG_GPIO_15_INT_CLR_POS)
+#define GLB_REG_GPIO_15_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_15_INT_CLR_LEN) - 1) << GLB_REG_GPIO_15_INT_CLR_POS))
+#define GLB_GPIO_15_INT_STAT              GLB_GPIO_15_INT_STAT
+#define GLB_GPIO_15_INT_STAT_POS          (21U)
+#define GLB_GPIO_15_INT_STAT_LEN          (1U)
+#define GLB_GPIO_15_INT_STAT_MSK          (((1U << GLB_GPIO_15_INT_STAT_LEN) - 1) << GLB_GPIO_15_INT_STAT_POS)
+#define GLB_GPIO_15_INT_STAT_UMSK         (~(((1U << GLB_GPIO_15_INT_STAT_LEN) - 1) << GLB_GPIO_15_INT_STAT_POS))
+#define GLB_REG_GPIO_15_INT_MASK          GLB_REG_GPIO_15_INT_MASK
+#define GLB_REG_GPIO_15_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_15_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_15_INT_MASK_MSK      (((1U << GLB_REG_GPIO_15_INT_MASK_LEN) - 1) << GLB_REG_GPIO_15_INT_MASK_POS)
+#define GLB_REG_GPIO_15_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_15_INT_MASK_LEN) - 1) << GLB_REG_GPIO_15_INT_MASK_POS))
+#define GLB_REG_GPIO_15_O                 GLB_REG_GPIO_15_O
+#define GLB_REG_GPIO_15_O_POS             (24U)
+#define GLB_REG_GPIO_15_O_LEN             (1U)
+#define GLB_REG_GPIO_15_O_MSK             (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
+#define GLB_REG_GPIO_15_O_UMSK            (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
+#define GLB_REG_GPIO_15_SET               GLB_REG_GPIO_15_SET
+#define GLB_REG_GPIO_15_SET_POS           (25U)
+#define GLB_REG_GPIO_15_SET_LEN           (1U)
+#define GLB_REG_GPIO_15_SET_MSK           (((1U << GLB_REG_GPIO_15_SET_LEN) - 1) << GLB_REG_GPIO_15_SET_POS)
+#define GLB_REG_GPIO_15_SET_UMSK          (~(((1U << GLB_REG_GPIO_15_SET_LEN) - 1) << GLB_REG_GPIO_15_SET_POS))
+#define GLB_REG_GPIO_15_CLR               GLB_REG_GPIO_15_CLR
+#define GLB_REG_GPIO_15_CLR_POS           (26U)
+#define GLB_REG_GPIO_15_CLR_LEN           (1U)
+#define GLB_REG_GPIO_15_CLR_MSK           (((1U << GLB_REG_GPIO_15_CLR_LEN) - 1) << GLB_REG_GPIO_15_CLR_POS)
+#define GLB_REG_GPIO_15_CLR_UMSK          (~(((1U << GLB_REG_GPIO_15_CLR_LEN) - 1) << GLB_REG_GPIO_15_CLR_POS))
+#define GLB_REG_GPIO_15_I                 GLB_REG_GPIO_15_I
+#define GLB_REG_GPIO_15_I_POS             (28U)
+#define GLB_REG_GPIO_15_I_LEN             (1U)
+#define GLB_REG_GPIO_15_I_MSK             (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
+#define GLB_REG_GPIO_15_I_UMSK            (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
+#define GLB_REG_GPIO_15_MODE              GLB_REG_GPIO_15_MODE
+#define GLB_REG_GPIO_15_MODE_POS          (30U)
+#define GLB_REG_GPIO_15_MODE_LEN          (2U)
+#define GLB_REG_GPIO_15_MODE_MSK          (((1U << GLB_REG_GPIO_15_MODE_LEN) - 1) << GLB_REG_GPIO_15_MODE_POS)
+#define GLB_REG_GPIO_15_MODE_UMSK         (~(((1U << GLB_REG_GPIO_15_MODE_LEN) - 1) << GLB_REG_GPIO_15_MODE_POS))
+
+/* 0x904 : gpio_cfg16 */
+#define GLB_GPIO_CFG16_OFFSET             (0x904)
+#define GLB_REG_GPIO_16_IE                GLB_REG_GPIO_16_IE
+#define GLB_REG_GPIO_16_IE_POS            (0U)
+#define GLB_REG_GPIO_16_IE_LEN            (1U)
+#define GLB_REG_GPIO_16_IE_MSK            (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
+#define GLB_REG_GPIO_16_IE_UMSK           (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
+#define GLB_REG_GPIO_16_SMT               GLB_REG_GPIO_16_SMT
+#define GLB_REG_GPIO_16_SMT_POS           (1U)
+#define GLB_REG_GPIO_16_SMT_LEN           (1U)
+#define GLB_REG_GPIO_16_SMT_MSK           (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
+#define GLB_REG_GPIO_16_SMT_UMSK          (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
+#define GLB_REG_GPIO_16_DRV               GLB_REG_GPIO_16_DRV
+#define GLB_REG_GPIO_16_DRV_POS           (2U)
+#define GLB_REG_GPIO_16_DRV_LEN           (2U)
+#define GLB_REG_GPIO_16_DRV_MSK           (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
+#define GLB_REG_GPIO_16_DRV_UMSK          (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
+#define GLB_REG_GPIO_16_PU                GLB_REG_GPIO_16_PU
+#define GLB_REG_GPIO_16_PU_POS            (4U)
+#define GLB_REG_GPIO_16_PU_LEN            (1U)
+#define GLB_REG_GPIO_16_PU_MSK            (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
+#define GLB_REG_GPIO_16_PU_UMSK           (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
+#define GLB_REG_GPIO_16_PD                GLB_REG_GPIO_16_PD
+#define GLB_REG_GPIO_16_PD_POS            (5U)
+#define GLB_REG_GPIO_16_PD_LEN            (1U)
+#define GLB_REG_GPIO_16_PD_MSK            (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
+#define GLB_REG_GPIO_16_PD_UMSK           (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
+#define GLB_REG_GPIO_16_OE                GLB_REG_GPIO_16_OE
+#define GLB_REG_GPIO_16_OE_POS            (6U)
+#define GLB_REG_GPIO_16_OE_LEN            (1U)
+#define GLB_REG_GPIO_16_OE_MSK            (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
+#define GLB_REG_GPIO_16_OE_UMSK           (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
+#define GLB_REG_GPIO_16_FUNC_SEL          GLB_REG_GPIO_16_FUNC_SEL
+#define GLB_REG_GPIO_16_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_16_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_16_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
+#define GLB_REG_GPIO_16_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS))
+#define GLB_REG_GPIO_16_INT_MODE_SET      GLB_REG_GPIO_16_INT_MODE_SET
+#define GLB_REG_GPIO_16_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_16_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_16_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_16_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_16_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_16_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_16_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_16_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_16_INT_CLR           GLB_REG_GPIO_16_INT_CLR
+#define GLB_REG_GPIO_16_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_16_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_16_INT_CLR_MSK       (((1U << GLB_REG_GPIO_16_INT_CLR_LEN) - 1) << GLB_REG_GPIO_16_INT_CLR_POS)
+#define GLB_REG_GPIO_16_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_16_INT_CLR_LEN) - 1) << GLB_REG_GPIO_16_INT_CLR_POS))
+#define GLB_GPIO_16_INT_STAT              GLB_GPIO_16_INT_STAT
+#define GLB_GPIO_16_INT_STAT_POS          (21U)
+#define GLB_GPIO_16_INT_STAT_LEN          (1U)
+#define GLB_GPIO_16_INT_STAT_MSK          (((1U << GLB_GPIO_16_INT_STAT_LEN) - 1) << GLB_GPIO_16_INT_STAT_POS)
+#define GLB_GPIO_16_INT_STAT_UMSK         (~(((1U << GLB_GPIO_16_INT_STAT_LEN) - 1) << GLB_GPIO_16_INT_STAT_POS))
+#define GLB_REG_GPIO_16_INT_MASK          GLB_REG_GPIO_16_INT_MASK
+#define GLB_REG_GPIO_16_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_16_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_16_INT_MASK_MSK      (((1U << GLB_REG_GPIO_16_INT_MASK_LEN) - 1) << GLB_REG_GPIO_16_INT_MASK_POS)
+#define GLB_REG_GPIO_16_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_16_INT_MASK_LEN) - 1) << GLB_REG_GPIO_16_INT_MASK_POS))
+#define GLB_REG_GPIO_16_O                 GLB_REG_GPIO_16_O
+#define GLB_REG_GPIO_16_O_POS             (24U)
+#define GLB_REG_GPIO_16_O_LEN             (1U)
+#define GLB_REG_GPIO_16_O_MSK             (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
+#define GLB_REG_GPIO_16_O_UMSK            (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
+#define GLB_REG_GPIO_16_SET               GLB_REG_GPIO_16_SET
+#define GLB_REG_GPIO_16_SET_POS           (25U)
+#define GLB_REG_GPIO_16_SET_LEN           (1U)
+#define GLB_REG_GPIO_16_SET_MSK           (((1U << GLB_REG_GPIO_16_SET_LEN) - 1) << GLB_REG_GPIO_16_SET_POS)
+#define GLB_REG_GPIO_16_SET_UMSK          (~(((1U << GLB_REG_GPIO_16_SET_LEN) - 1) << GLB_REG_GPIO_16_SET_POS))
+#define GLB_REG_GPIO_16_CLR               GLB_REG_GPIO_16_CLR
+#define GLB_REG_GPIO_16_CLR_POS           (26U)
+#define GLB_REG_GPIO_16_CLR_LEN           (1U)
+#define GLB_REG_GPIO_16_CLR_MSK           (((1U << GLB_REG_GPIO_16_CLR_LEN) - 1) << GLB_REG_GPIO_16_CLR_POS)
+#define GLB_REG_GPIO_16_CLR_UMSK          (~(((1U << GLB_REG_GPIO_16_CLR_LEN) - 1) << GLB_REG_GPIO_16_CLR_POS))
+#define GLB_REG_GPIO_16_I                 GLB_REG_GPIO_16_I
+#define GLB_REG_GPIO_16_I_POS             (28U)
+#define GLB_REG_GPIO_16_I_LEN             (1U)
+#define GLB_REG_GPIO_16_I_MSK             (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
+#define GLB_REG_GPIO_16_I_UMSK            (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
+#define GLB_REG_GPIO_16_MODE              GLB_REG_GPIO_16_MODE
+#define GLB_REG_GPIO_16_MODE_POS          (30U)
+#define GLB_REG_GPIO_16_MODE_LEN          (2U)
+#define GLB_REG_GPIO_16_MODE_MSK          (((1U << GLB_REG_GPIO_16_MODE_LEN) - 1) << GLB_REG_GPIO_16_MODE_POS)
+#define GLB_REG_GPIO_16_MODE_UMSK         (~(((1U << GLB_REG_GPIO_16_MODE_LEN) - 1) << GLB_REG_GPIO_16_MODE_POS))
+
+/* 0x908 : gpio_cfg17 */
+#define GLB_GPIO_CFG17_OFFSET             (0x908)
+#define GLB_REG_GPIO_17_IE                GLB_REG_GPIO_17_IE
+#define GLB_REG_GPIO_17_IE_POS            (0U)
+#define GLB_REG_GPIO_17_IE_LEN            (1U)
+#define GLB_REG_GPIO_17_IE_MSK            (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
+#define GLB_REG_GPIO_17_IE_UMSK           (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
+#define GLB_REG_GPIO_17_SMT               GLB_REG_GPIO_17_SMT
+#define GLB_REG_GPIO_17_SMT_POS           (1U)
+#define GLB_REG_GPIO_17_SMT_LEN           (1U)
+#define GLB_REG_GPIO_17_SMT_MSK           (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
+#define GLB_REG_GPIO_17_SMT_UMSK          (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
+#define GLB_REG_GPIO_17_DRV               GLB_REG_GPIO_17_DRV
+#define GLB_REG_GPIO_17_DRV_POS           (2U)
+#define GLB_REG_GPIO_17_DRV_LEN           (2U)
+#define GLB_REG_GPIO_17_DRV_MSK           (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
+#define GLB_REG_GPIO_17_DRV_UMSK          (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
+#define GLB_REG_GPIO_17_PU                GLB_REG_GPIO_17_PU
+#define GLB_REG_GPIO_17_PU_POS            (4U)
+#define GLB_REG_GPIO_17_PU_LEN            (1U)
+#define GLB_REG_GPIO_17_PU_MSK            (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
+#define GLB_REG_GPIO_17_PU_UMSK           (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
+#define GLB_REG_GPIO_17_PD                GLB_REG_GPIO_17_PD
+#define GLB_REG_GPIO_17_PD_POS            (5U)
+#define GLB_REG_GPIO_17_PD_LEN            (1U)
+#define GLB_REG_GPIO_17_PD_MSK            (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
+#define GLB_REG_GPIO_17_PD_UMSK           (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
+#define GLB_REG_GPIO_17_OE                GLB_REG_GPIO_17_OE
+#define GLB_REG_GPIO_17_OE_POS            (6U)
+#define GLB_REG_GPIO_17_OE_LEN            (1U)
+#define GLB_REG_GPIO_17_OE_MSK            (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
+#define GLB_REG_GPIO_17_OE_UMSK           (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
+#define GLB_REG_GPIO_17_FUNC_SEL          GLB_REG_GPIO_17_FUNC_SEL
+#define GLB_REG_GPIO_17_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_17_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_17_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
+#define GLB_REG_GPIO_17_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS))
+#define GLB_REG_GPIO_17_INT_MODE_SET      GLB_REG_GPIO_17_INT_MODE_SET
+#define GLB_REG_GPIO_17_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_17_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_17_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_17_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_17_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_17_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_17_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_17_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_17_INT_CLR           GLB_REG_GPIO_17_INT_CLR
+#define GLB_REG_GPIO_17_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_17_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_17_INT_CLR_MSK       (((1U << GLB_REG_GPIO_17_INT_CLR_LEN) - 1) << GLB_REG_GPIO_17_INT_CLR_POS)
+#define GLB_REG_GPIO_17_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_17_INT_CLR_LEN) - 1) << GLB_REG_GPIO_17_INT_CLR_POS))
+#define GLB_GPIO_17_INT_STAT              GLB_GPIO_17_INT_STAT
+#define GLB_GPIO_17_INT_STAT_POS          (21U)
+#define GLB_GPIO_17_INT_STAT_LEN          (1U)
+#define GLB_GPIO_17_INT_STAT_MSK          (((1U << GLB_GPIO_17_INT_STAT_LEN) - 1) << GLB_GPIO_17_INT_STAT_POS)
+#define GLB_GPIO_17_INT_STAT_UMSK         (~(((1U << GLB_GPIO_17_INT_STAT_LEN) - 1) << GLB_GPIO_17_INT_STAT_POS))
+#define GLB_REG_GPIO_17_INT_MASK          GLB_REG_GPIO_17_INT_MASK
+#define GLB_REG_GPIO_17_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_17_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_17_INT_MASK_MSK      (((1U << GLB_REG_GPIO_17_INT_MASK_LEN) - 1) << GLB_REG_GPIO_17_INT_MASK_POS)
+#define GLB_REG_GPIO_17_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_17_INT_MASK_LEN) - 1) << GLB_REG_GPIO_17_INT_MASK_POS))
+#define GLB_REG_GPIO_17_O                 GLB_REG_GPIO_17_O
+#define GLB_REG_GPIO_17_O_POS             (24U)
+#define GLB_REG_GPIO_17_O_LEN             (1U)
+#define GLB_REG_GPIO_17_O_MSK             (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
+#define GLB_REG_GPIO_17_O_UMSK            (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
+#define GLB_REG_GPIO_17_SET               GLB_REG_GPIO_17_SET
+#define GLB_REG_GPIO_17_SET_POS           (25U)
+#define GLB_REG_GPIO_17_SET_LEN           (1U)
+#define GLB_REG_GPIO_17_SET_MSK           (((1U << GLB_REG_GPIO_17_SET_LEN) - 1) << GLB_REG_GPIO_17_SET_POS)
+#define GLB_REG_GPIO_17_SET_UMSK          (~(((1U << GLB_REG_GPIO_17_SET_LEN) - 1) << GLB_REG_GPIO_17_SET_POS))
+#define GLB_REG_GPIO_17_CLR               GLB_REG_GPIO_17_CLR
+#define GLB_REG_GPIO_17_CLR_POS           (26U)
+#define GLB_REG_GPIO_17_CLR_LEN           (1U)
+#define GLB_REG_GPIO_17_CLR_MSK           (((1U << GLB_REG_GPIO_17_CLR_LEN) - 1) << GLB_REG_GPIO_17_CLR_POS)
+#define GLB_REG_GPIO_17_CLR_UMSK          (~(((1U << GLB_REG_GPIO_17_CLR_LEN) - 1) << GLB_REG_GPIO_17_CLR_POS))
+#define GLB_REG_GPIO_17_I                 GLB_REG_GPIO_17_I
+#define GLB_REG_GPIO_17_I_POS             (28U)
+#define GLB_REG_GPIO_17_I_LEN             (1U)
+#define GLB_REG_GPIO_17_I_MSK             (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
+#define GLB_REG_GPIO_17_I_UMSK            (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
+#define GLB_REG_GPIO_17_MODE              GLB_REG_GPIO_17_MODE
+#define GLB_REG_GPIO_17_MODE_POS          (30U)
+#define GLB_REG_GPIO_17_MODE_LEN          (2U)
+#define GLB_REG_GPIO_17_MODE_MSK          (((1U << GLB_REG_GPIO_17_MODE_LEN) - 1) << GLB_REG_GPIO_17_MODE_POS)
+#define GLB_REG_GPIO_17_MODE_UMSK         (~(((1U << GLB_REG_GPIO_17_MODE_LEN) - 1) << GLB_REG_GPIO_17_MODE_POS))
+
+/* 0x90C : gpio_cfg18 */
+#define GLB_GPIO_CFG18_OFFSET             (0x90C)
+#define GLB_REG_GPIO_18_IE                GLB_REG_GPIO_18_IE
+#define GLB_REG_GPIO_18_IE_POS            (0U)
+#define GLB_REG_GPIO_18_IE_LEN            (1U)
+#define GLB_REG_GPIO_18_IE_MSK            (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
+#define GLB_REG_GPIO_18_IE_UMSK           (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
+#define GLB_REG_GPIO_18_SMT               GLB_REG_GPIO_18_SMT
+#define GLB_REG_GPIO_18_SMT_POS           (1U)
+#define GLB_REG_GPIO_18_SMT_LEN           (1U)
+#define GLB_REG_GPIO_18_SMT_MSK           (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
+#define GLB_REG_GPIO_18_SMT_UMSK          (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
+#define GLB_REG_GPIO_18_DRV               GLB_REG_GPIO_18_DRV
+#define GLB_REG_GPIO_18_DRV_POS           (2U)
+#define GLB_REG_GPIO_18_DRV_LEN           (2U)
+#define GLB_REG_GPIO_18_DRV_MSK           (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
+#define GLB_REG_GPIO_18_DRV_UMSK          (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
+#define GLB_REG_GPIO_18_PU                GLB_REG_GPIO_18_PU
+#define GLB_REG_GPIO_18_PU_POS            (4U)
+#define GLB_REG_GPIO_18_PU_LEN            (1U)
+#define GLB_REG_GPIO_18_PU_MSK            (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
+#define GLB_REG_GPIO_18_PU_UMSK           (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
+#define GLB_REG_GPIO_18_PD                GLB_REG_GPIO_18_PD
+#define GLB_REG_GPIO_18_PD_POS            (5U)
+#define GLB_REG_GPIO_18_PD_LEN            (1U)
+#define GLB_REG_GPIO_18_PD_MSK            (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
+#define GLB_REG_GPIO_18_PD_UMSK           (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
+#define GLB_REG_GPIO_18_OE                GLB_REG_GPIO_18_OE
+#define GLB_REG_GPIO_18_OE_POS            (6U)
+#define GLB_REG_GPIO_18_OE_LEN            (1U)
+#define GLB_REG_GPIO_18_OE_MSK            (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
+#define GLB_REG_GPIO_18_OE_UMSK           (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
+#define GLB_REG_GPIO_18_FUNC_SEL          GLB_REG_GPIO_18_FUNC_SEL
+#define GLB_REG_GPIO_18_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_18_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_18_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
+#define GLB_REG_GPIO_18_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS))
+#define GLB_REG_GPIO_18_INT_MODE_SET      GLB_REG_GPIO_18_INT_MODE_SET
+#define GLB_REG_GPIO_18_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_18_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_18_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_18_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_18_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_18_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_18_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_18_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_18_INT_CLR           GLB_REG_GPIO_18_INT_CLR
+#define GLB_REG_GPIO_18_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_18_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_18_INT_CLR_MSK       (((1U << GLB_REG_GPIO_18_INT_CLR_LEN) - 1) << GLB_REG_GPIO_18_INT_CLR_POS)
+#define GLB_REG_GPIO_18_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_18_INT_CLR_LEN) - 1) << GLB_REG_GPIO_18_INT_CLR_POS))
+#define GLB_GPIO_18_INT_STAT              GLB_GPIO_18_INT_STAT
+#define GLB_GPIO_18_INT_STAT_POS          (21U)
+#define GLB_GPIO_18_INT_STAT_LEN          (1U)
+#define GLB_GPIO_18_INT_STAT_MSK          (((1U << GLB_GPIO_18_INT_STAT_LEN) - 1) << GLB_GPIO_18_INT_STAT_POS)
+#define GLB_GPIO_18_INT_STAT_UMSK         (~(((1U << GLB_GPIO_18_INT_STAT_LEN) - 1) << GLB_GPIO_18_INT_STAT_POS))
+#define GLB_REG_GPIO_18_INT_MASK          GLB_REG_GPIO_18_INT_MASK
+#define GLB_REG_GPIO_18_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_18_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_18_INT_MASK_MSK      (((1U << GLB_REG_GPIO_18_INT_MASK_LEN) - 1) << GLB_REG_GPIO_18_INT_MASK_POS)
+#define GLB_REG_GPIO_18_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_18_INT_MASK_LEN) - 1) << GLB_REG_GPIO_18_INT_MASK_POS))
+#define GLB_REG_GPIO_18_O                 GLB_REG_GPIO_18_O
+#define GLB_REG_GPIO_18_O_POS             (24U)
+#define GLB_REG_GPIO_18_O_LEN             (1U)
+#define GLB_REG_GPIO_18_O_MSK             (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
+#define GLB_REG_GPIO_18_O_UMSK            (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
+#define GLB_REG_GPIO_18_SET               GLB_REG_GPIO_18_SET
+#define GLB_REG_GPIO_18_SET_POS           (25U)
+#define GLB_REG_GPIO_18_SET_LEN           (1U)
+#define GLB_REG_GPIO_18_SET_MSK           (((1U << GLB_REG_GPIO_18_SET_LEN) - 1) << GLB_REG_GPIO_18_SET_POS)
+#define GLB_REG_GPIO_18_SET_UMSK          (~(((1U << GLB_REG_GPIO_18_SET_LEN) - 1) << GLB_REG_GPIO_18_SET_POS))
+#define GLB_REG_GPIO_18_CLR               GLB_REG_GPIO_18_CLR
+#define GLB_REG_GPIO_18_CLR_POS           (26U)
+#define GLB_REG_GPIO_18_CLR_LEN           (1U)
+#define GLB_REG_GPIO_18_CLR_MSK           (((1U << GLB_REG_GPIO_18_CLR_LEN) - 1) << GLB_REG_GPIO_18_CLR_POS)
+#define GLB_REG_GPIO_18_CLR_UMSK          (~(((1U << GLB_REG_GPIO_18_CLR_LEN) - 1) << GLB_REG_GPIO_18_CLR_POS))
+#define GLB_REG_GPIO_18_I                 GLB_REG_GPIO_18_I
+#define GLB_REG_GPIO_18_I_POS             (28U)
+#define GLB_REG_GPIO_18_I_LEN             (1U)
+#define GLB_REG_GPIO_18_I_MSK             (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
+#define GLB_REG_GPIO_18_I_UMSK            (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
+#define GLB_REG_GPIO_18_MODE              GLB_REG_GPIO_18_MODE
+#define GLB_REG_GPIO_18_MODE_POS          (30U)
+#define GLB_REG_GPIO_18_MODE_LEN          (2U)
+#define GLB_REG_GPIO_18_MODE_MSK          (((1U << GLB_REG_GPIO_18_MODE_LEN) - 1) << GLB_REG_GPIO_18_MODE_POS)
+#define GLB_REG_GPIO_18_MODE_UMSK         (~(((1U << GLB_REG_GPIO_18_MODE_LEN) - 1) << GLB_REG_GPIO_18_MODE_POS))
+
+/* 0x910 : gpio_cfg19 */
+#define GLB_GPIO_CFG19_OFFSET             (0x910)
+#define GLB_REG_GPIO_19_IE                GLB_REG_GPIO_19_IE
+#define GLB_REG_GPIO_19_IE_POS            (0U)
+#define GLB_REG_GPIO_19_IE_LEN            (1U)
+#define GLB_REG_GPIO_19_IE_MSK            (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
+#define GLB_REG_GPIO_19_IE_UMSK           (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
+#define GLB_REG_GPIO_19_SMT               GLB_REG_GPIO_19_SMT
+#define GLB_REG_GPIO_19_SMT_POS           (1U)
+#define GLB_REG_GPIO_19_SMT_LEN           (1U)
+#define GLB_REG_GPIO_19_SMT_MSK           (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
+#define GLB_REG_GPIO_19_SMT_UMSK          (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
+#define GLB_REG_GPIO_19_DRV               GLB_REG_GPIO_19_DRV
+#define GLB_REG_GPIO_19_DRV_POS           (2U)
+#define GLB_REG_GPIO_19_DRV_LEN           (2U)
+#define GLB_REG_GPIO_19_DRV_MSK           (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
+#define GLB_REG_GPIO_19_DRV_UMSK          (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
+#define GLB_REG_GPIO_19_PU                GLB_REG_GPIO_19_PU
+#define GLB_REG_GPIO_19_PU_POS            (4U)
+#define GLB_REG_GPIO_19_PU_LEN            (1U)
+#define GLB_REG_GPIO_19_PU_MSK            (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
+#define GLB_REG_GPIO_19_PU_UMSK           (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
+#define GLB_REG_GPIO_19_PD                GLB_REG_GPIO_19_PD
+#define GLB_REG_GPIO_19_PD_POS            (5U)
+#define GLB_REG_GPIO_19_PD_LEN            (1U)
+#define GLB_REG_GPIO_19_PD_MSK            (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
+#define GLB_REG_GPIO_19_PD_UMSK           (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
+#define GLB_REG_GPIO_19_OE                GLB_REG_GPIO_19_OE
+#define GLB_REG_GPIO_19_OE_POS            (6U)
+#define GLB_REG_GPIO_19_OE_LEN            (1U)
+#define GLB_REG_GPIO_19_OE_MSK            (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
+#define GLB_REG_GPIO_19_OE_UMSK           (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
+#define GLB_REG_GPIO_19_FUNC_SEL          GLB_REG_GPIO_19_FUNC_SEL
+#define GLB_REG_GPIO_19_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_19_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_19_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
+#define GLB_REG_GPIO_19_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS))
+#define GLB_REG_GPIO_19_INT_MODE_SET      GLB_REG_GPIO_19_INT_MODE_SET
+#define GLB_REG_GPIO_19_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_19_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_19_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_19_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_19_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_19_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_19_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_19_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_19_INT_CLR           GLB_REG_GPIO_19_INT_CLR
+#define GLB_REG_GPIO_19_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_19_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_19_INT_CLR_MSK       (((1U << GLB_REG_GPIO_19_INT_CLR_LEN) - 1) << GLB_REG_GPIO_19_INT_CLR_POS)
+#define GLB_REG_GPIO_19_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_19_INT_CLR_LEN) - 1) << GLB_REG_GPIO_19_INT_CLR_POS))
+#define GLB_GPIO_19_INT_STAT              GLB_GPIO_19_INT_STAT
+#define GLB_GPIO_19_INT_STAT_POS          (21U)
+#define GLB_GPIO_19_INT_STAT_LEN          (1U)
+#define GLB_GPIO_19_INT_STAT_MSK          (((1U << GLB_GPIO_19_INT_STAT_LEN) - 1) << GLB_GPIO_19_INT_STAT_POS)
+#define GLB_GPIO_19_INT_STAT_UMSK         (~(((1U << GLB_GPIO_19_INT_STAT_LEN) - 1) << GLB_GPIO_19_INT_STAT_POS))
+#define GLB_REG_GPIO_19_INT_MASK          GLB_REG_GPIO_19_INT_MASK
+#define GLB_REG_GPIO_19_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_19_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_19_INT_MASK_MSK      (((1U << GLB_REG_GPIO_19_INT_MASK_LEN) - 1) << GLB_REG_GPIO_19_INT_MASK_POS)
+#define GLB_REG_GPIO_19_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_19_INT_MASK_LEN) - 1) << GLB_REG_GPIO_19_INT_MASK_POS))
+#define GLB_REG_GPIO_19_O                 GLB_REG_GPIO_19_O
+#define GLB_REG_GPIO_19_O_POS             (24U)
+#define GLB_REG_GPIO_19_O_LEN             (1U)
+#define GLB_REG_GPIO_19_O_MSK             (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
+#define GLB_REG_GPIO_19_O_UMSK            (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
+#define GLB_REG_GPIO_19_SET               GLB_REG_GPIO_19_SET
+#define GLB_REG_GPIO_19_SET_POS           (25U)
+#define GLB_REG_GPIO_19_SET_LEN           (1U)
+#define GLB_REG_GPIO_19_SET_MSK           (((1U << GLB_REG_GPIO_19_SET_LEN) - 1) << GLB_REG_GPIO_19_SET_POS)
+#define GLB_REG_GPIO_19_SET_UMSK          (~(((1U << GLB_REG_GPIO_19_SET_LEN) - 1) << GLB_REG_GPIO_19_SET_POS))
+#define GLB_REG_GPIO_19_CLR               GLB_REG_GPIO_19_CLR
+#define GLB_REG_GPIO_19_CLR_POS           (26U)
+#define GLB_REG_GPIO_19_CLR_LEN           (1U)
+#define GLB_REG_GPIO_19_CLR_MSK           (((1U << GLB_REG_GPIO_19_CLR_LEN) - 1) << GLB_REG_GPIO_19_CLR_POS)
+#define GLB_REG_GPIO_19_CLR_UMSK          (~(((1U << GLB_REG_GPIO_19_CLR_LEN) - 1) << GLB_REG_GPIO_19_CLR_POS))
+#define GLB_REG_GPIO_19_I                 GLB_REG_GPIO_19_I
+#define GLB_REG_GPIO_19_I_POS             (28U)
+#define GLB_REG_GPIO_19_I_LEN             (1U)
+#define GLB_REG_GPIO_19_I_MSK             (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
+#define GLB_REG_GPIO_19_I_UMSK            (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
+#define GLB_REG_GPIO_19_MODE              GLB_REG_GPIO_19_MODE
+#define GLB_REG_GPIO_19_MODE_POS          (30U)
+#define GLB_REG_GPIO_19_MODE_LEN          (2U)
+#define GLB_REG_GPIO_19_MODE_MSK          (((1U << GLB_REG_GPIO_19_MODE_LEN) - 1) << GLB_REG_GPIO_19_MODE_POS)
+#define GLB_REG_GPIO_19_MODE_UMSK         (~(((1U << GLB_REG_GPIO_19_MODE_LEN) - 1) << GLB_REG_GPIO_19_MODE_POS))
+
+/* 0x914 : gpio_cfg20 */
+#define GLB_GPIO_CFG20_OFFSET             (0x914)
+#define GLB_REG_GPIO_20_IE                GLB_REG_GPIO_20_IE
+#define GLB_REG_GPIO_20_IE_POS            (0U)
+#define GLB_REG_GPIO_20_IE_LEN            (1U)
+#define GLB_REG_GPIO_20_IE_MSK            (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
+#define GLB_REG_GPIO_20_IE_UMSK           (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
+#define GLB_REG_GPIO_20_SMT               GLB_REG_GPIO_20_SMT
+#define GLB_REG_GPIO_20_SMT_POS           (1U)
+#define GLB_REG_GPIO_20_SMT_LEN           (1U)
+#define GLB_REG_GPIO_20_SMT_MSK           (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
+#define GLB_REG_GPIO_20_SMT_UMSK          (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
+#define GLB_REG_GPIO_20_DRV               GLB_REG_GPIO_20_DRV
+#define GLB_REG_GPIO_20_DRV_POS           (2U)
+#define GLB_REG_GPIO_20_DRV_LEN           (2U)
+#define GLB_REG_GPIO_20_DRV_MSK           (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
+#define GLB_REG_GPIO_20_DRV_UMSK          (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
+#define GLB_REG_GPIO_20_PU                GLB_REG_GPIO_20_PU
+#define GLB_REG_GPIO_20_PU_POS            (4U)
+#define GLB_REG_GPIO_20_PU_LEN            (1U)
+#define GLB_REG_GPIO_20_PU_MSK            (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
+#define GLB_REG_GPIO_20_PU_UMSK           (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
+#define GLB_REG_GPIO_20_PD                GLB_REG_GPIO_20_PD
+#define GLB_REG_GPIO_20_PD_POS            (5U)
+#define GLB_REG_GPIO_20_PD_LEN            (1U)
+#define GLB_REG_GPIO_20_PD_MSK            (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
+#define GLB_REG_GPIO_20_PD_UMSK           (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
+#define GLB_REG_GPIO_20_OE                GLB_REG_GPIO_20_OE
+#define GLB_REG_GPIO_20_OE_POS            (6U)
+#define GLB_REG_GPIO_20_OE_LEN            (1U)
+#define GLB_REG_GPIO_20_OE_MSK            (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
+#define GLB_REG_GPIO_20_OE_UMSK           (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
+#define GLB_REG_GPIO_20_FUNC_SEL          GLB_REG_GPIO_20_FUNC_SEL
+#define GLB_REG_GPIO_20_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_20_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_20_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
+#define GLB_REG_GPIO_20_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS))
+#define GLB_REG_GPIO_20_INT_MODE_SET      GLB_REG_GPIO_20_INT_MODE_SET
+#define GLB_REG_GPIO_20_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_20_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_20_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_20_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_20_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_20_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_20_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_20_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_20_INT_CLR           GLB_REG_GPIO_20_INT_CLR
+#define GLB_REG_GPIO_20_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_20_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_20_INT_CLR_MSK       (((1U << GLB_REG_GPIO_20_INT_CLR_LEN) - 1) << GLB_REG_GPIO_20_INT_CLR_POS)
+#define GLB_REG_GPIO_20_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_20_INT_CLR_LEN) - 1) << GLB_REG_GPIO_20_INT_CLR_POS))
+#define GLB_GPIO_20_INT_STAT              GLB_GPIO_20_INT_STAT
+#define GLB_GPIO_20_INT_STAT_POS          (21U)
+#define GLB_GPIO_20_INT_STAT_LEN          (1U)
+#define GLB_GPIO_20_INT_STAT_MSK          (((1U << GLB_GPIO_20_INT_STAT_LEN) - 1) << GLB_GPIO_20_INT_STAT_POS)
+#define GLB_GPIO_20_INT_STAT_UMSK         (~(((1U << GLB_GPIO_20_INT_STAT_LEN) - 1) << GLB_GPIO_20_INT_STAT_POS))
+#define GLB_REG_GPIO_20_INT_MASK          GLB_REG_GPIO_20_INT_MASK
+#define GLB_REG_GPIO_20_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_20_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_20_INT_MASK_MSK      (((1U << GLB_REG_GPIO_20_INT_MASK_LEN) - 1) << GLB_REG_GPIO_20_INT_MASK_POS)
+#define GLB_REG_GPIO_20_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_20_INT_MASK_LEN) - 1) << GLB_REG_GPIO_20_INT_MASK_POS))
+#define GLB_REG_GPIO_20_O                 GLB_REG_GPIO_20_O
+#define GLB_REG_GPIO_20_O_POS             (24U)
+#define GLB_REG_GPIO_20_O_LEN             (1U)
+#define GLB_REG_GPIO_20_O_MSK             (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
+#define GLB_REG_GPIO_20_O_UMSK            (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
+#define GLB_REG_GPIO_20_SET               GLB_REG_GPIO_20_SET
+#define GLB_REG_GPIO_20_SET_POS           (25U)
+#define GLB_REG_GPIO_20_SET_LEN           (1U)
+#define GLB_REG_GPIO_20_SET_MSK           (((1U << GLB_REG_GPIO_20_SET_LEN) - 1) << GLB_REG_GPIO_20_SET_POS)
+#define GLB_REG_GPIO_20_SET_UMSK          (~(((1U << GLB_REG_GPIO_20_SET_LEN) - 1) << GLB_REG_GPIO_20_SET_POS))
+#define GLB_REG_GPIO_20_CLR               GLB_REG_GPIO_20_CLR
+#define GLB_REG_GPIO_20_CLR_POS           (26U)
+#define GLB_REG_GPIO_20_CLR_LEN           (1U)
+#define GLB_REG_GPIO_20_CLR_MSK           (((1U << GLB_REG_GPIO_20_CLR_LEN) - 1) << GLB_REG_GPIO_20_CLR_POS)
+#define GLB_REG_GPIO_20_CLR_UMSK          (~(((1U << GLB_REG_GPIO_20_CLR_LEN) - 1) << GLB_REG_GPIO_20_CLR_POS))
+#define GLB_REG_GPIO_20_I                 GLB_REG_GPIO_20_I
+#define GLB_REG_GPIO_20_I_POS             (28U)
+#define GLB_REG_GPIO_20_I_LEN             (1U)
+#define GLB_REG_GPIO_20_I_MSK             (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
+#define GLB_REG_GPIO_20_I_UMSK            (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
+#define GLB_REG_GPIO_20_MODE              GLB_REG_GPIO_20_MODE
+#define GLB_REG_GPIO_20_MODE_POS          (30U)
+#define GLB_REG_GPIO_20_MODE_LEN          (2U)
+#define GLB_REG_GPIO_20_MODE_MSK          (((1U << GLB_REG_GPIO_20_MODE_LEN) - 1) << GLB_REG_GPIO_20_MODE_POS)
+#define GLB_REG_GPIO_20_MODE_UMSK         (~(((1U << GLB_REG_GPIO_20_MODE_LEN) - 1) << GLB_REG_GPIO_20_MODE_POS))
+
+/* 0x918 : gpio_cfg21 */
+#define GLB_GPIO_CFG21_OFFSET             (0x918)
+#define GLB_REG_GPIO_21_IE                GLB_REG_GPIO_21_IE
+#define GLB_REG_GPIO_21_IE_POS            (0U)
+#define GLB_REG_GPIO_21_IE_LEN            (1U)
+#define GLB_REG_GPIO_21_IE_MSK            (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
+#define GLB_REG_GPIO_21_IE_UMSK           (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
+#define GLB_REG_GPIO_21_SMT               GLB_REG_GPIO_21_SMT
+#define GLB_REG_GPIO_21_SMT_POS           (1U)
+#define GLB_REG_GPIO_21_SMT_LEN           (1U)
+#define GLB_REG_GPIO_21_SMT_MSK           (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
+#define GLB_REG_GPIO_21_SMT_UMSK          (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
+#define GLB_REG_GPIO_21_DRV               GLB_REG_GPIO_21_DRV
+#define GLB_REG_GPIO_21_DRV_POS           (2U)
+#define GLB_REG_GPIO_21_DRV_LEN           (2U)
+#define GLB_REG_GPIO_21_DRV_MSK           (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
+#define GLB_REG_GPIO_21_DRV_UMSK          (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
+#define GLB_REG_GPIO_21_PU                GLB_REG_GPIO_21_PU
+#define GLB_REG_GPIO_21_PU_POS            (4U)
+#define GLB_REG_GPIO_21_PU_LEN            (1U)
+#define GLB_REG_GPIO_21_PU_MSK            (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
+#define GLB_REG_GPIO_21_PU_UMSK           (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
+#define GLB_REG_GPIO_21_PD                GLB_REG_GPIO_21_PD
+#define GLB_REG_GPIO_21_PD_POS            (5U)
+#define GLB_REG_GPIO_21_PD_LEN            (1U)
+#define GLB_REG_GPIO_21_PD_MSK            (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
+#define GLB_REG_GPIO_21_PD_UMSK           (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
+#define GLB_REG_GPIO_21_OE                GLB_REG_GPIO_21_OE
+#define GLB_REG_GPIO_21_OE_POS            (6U)
+#define GLB_REG_GPIO_21_OE_LEN            (1U)
+#define GLB_REG_GPIO_21_OE_MSK            (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
+#define GLB_REG_GPIO_21_OE_UMSK           (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
+#define GLB_REG_GPIO_21_FUNC_SEL          GLB_REG_GPIO_21_FUNC_SEL
+#define GLB_REG_GPIO_21_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_21_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_21_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
+#define GLB_REG_GPIO_21_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS))
+#define GLB_REG_GPIO_21_INT_MODE_SET      GLB_REG_GPIO_21_INT_MODE_SET
+#define GLB_REG_GPIO_21_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_21_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_21_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_21_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_21_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_21_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_21_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_21_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_21_INT_CLR           GLB_REG_GPIO_21_INT_CLR
+#define GLB_REG_GPIO_21_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_21_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_21_INT_CLR_MSK       (((1U << GLB_REG_GPIO_21_INT_CLR_LEN) - 1) << GLB_REG_GPIO_21_INT_CLR_POS)
+#define GLB_REG_GPIO_21_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_21_INT_CLR_LEN) - 1) << GLB_REG_GPIO_21_INT_CLR_POS))
+#define GLB_GPIO_21_INT_STAT              GLB_GPIO_21_INT_STAT
+#define GLB_GPIO_21_INT_STAT_POS          (21U)
+#define GLB_GPIO_21_INT_STAT_LEN          (1U)
+#define GLB_GPIO_21_INT_STAT_MSK          (((1U << GLB_GPIO_21_INT_STAT_LEN) - 1) << GLB_GPIO_21_INT_STAT_POS)
+#define GLB_GPIO_21_INT_STAT_UMSK         (~(((1U << GLB_GPIO_21_INT_STAT_LEN) - 1) << GLB_GPIO_21_INT_STAT_POS))
+#define GLB_REG_GPIO_21_INT_MASK          GLB_REG_GPIO_21_INT_MASK
+#define GLB_REG_GPIO_21_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_21_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_21_INT_MASK_MSK      (((1U << GLB_REG_GPIO_21_INT_MASK_LEN) - 1) << GLB_REG_GPIO_21_INT_MASK_POS)
+#define GLB_REG_GPIO_21_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_21_INT_MASK_LEN) - 1) << GLB_REG_GPIO_21_INT_MASK_POS))
+#define GLB_REG_GPIO_21_O                 GLB_REG_GPIO_21_O
+#define GLB_REG_GPIO_21_O_POS             (24U)
+#define GLB_REG_GPIO_21_O_LEN             (1U)
+#define GLB_REG_GPIO_21_O_MSK             (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
+#define GLB_REG_GPIO_21_O_UMSK            (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
+#define GLB_REG_GPIO_21_SET               GLB_REG_GPIO_21_SET
+#define GLB_REG_GPIO_21_SET_POS           (25U)
+#define GLB_REG_GPIO_21_SET_LEN           (1U)
+#define GLB_REG_GPIO_21_SET_MSK           (((1U << GLB_REG_GPIO_21_SET_LEN) - 1) << GLB_REG_GPIO_21_SET_POS)
+#define GLB_REG_GPIO_21_SET_UMSK          (~(((1U << GLB_REG_GPIO_21_SET_LEN) - 1) << GLB_REG_GPIO_21_SET_POS))
+#define GLB_REG_GPIO_21_CLR               GLB_REG_GPIO_21_CLR
+#define GLB_REG_GPIO_21_CLR_POS           (26U)
+#define GLB_REG_GPIO_21_CLR_LEN           (1U)
+#define GLB_REG_GPIO_21_CLR_MSK           (((1U << GLB_REG_GPIO_21_CLR_LEN) - 1) << GLB_REG_GPIO_21_CLR_POS)
+#define GLB_REG_GPIO_21_CLR_UMSK          (~(((1U << GLB_REG_GPIO_21_CLR_LEN) - 1) << GLB_REG_GPIO_21_CLR_POS))
+#define GLB_REG_GPIO_21_I                 GLB_REG_GPIO_21_I
+#define GLB_REG_GPIO_21_I_POS             (28U)
+#define GLB_REG_GPIO_21_I_LEN             (1U)
+#define GLB_REG_GPIO_21_I_MSK             (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
+#define GLB_REG_GPIO_21_I_UMSK            (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
+#define GLB_REG_GPIO_21_MODE              GLB_REG_GPIO_21_MODE
+#define GLB_REG_GPIO_21_MODE_POS          (30U)
+#define GLB_REG_GPIO_21_MODE_LEN          (2U)
+#define GLB_REG_GPIO_21_MODE_MSK          (((1U << GLB_REG_GPIO_21_MODE_LEN) - 1) << GLB_REG_GPIO_21_MODE_POS)
+#define GLB_REG_GPIO_21_MODE_UMSK         (~(((1U << GLB_REG_GPIO_21_MODE_LEN) - 1) << GLB_REG_GPIO_21_MODE_POS))
+
+/* 0x91C : gpio_cfg22 */
+#define GLB_GPIO_CFG22_OFFSET             (0x91C)
+#define GLB_REG_GPIO_22_IE                GLB_REG_GPIO_22_IE
+#define GLB_REG_GPIO_22_IE_POS            (0U)
+#define GLB_REG_GPIO_22_IE_LEN            (1U)
+#define GLB_REG_GPIO_22_IE_MSK            (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
+#define GLB_REG_GPIO_22_IE_UMSK           (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
+#define GLB_REG_GPIO_22_SMT               GLB_REG_GPIO_22_SMT
+#define GLB_REG_GPIO_22_SMT_POS           (1U)
+#define GLB_REG_GPIO_22_SMT_LEN           (1U)
+#define GLB_REG_GPIO_22_SMT_MSK           (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
+#define GLB_REG_GPIO_22_SMT_UMSK          (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
+#define GLB_REG_GPIO_22_DRV               GLB_REG_GPIO_22_DRV
+#define GLB_REG_GPIO_22_DRV_POS           (2U)
+#define GLB_REG_GPIO_22_DRV_LEN           (2U)
+#define GLB_REG_GPIO_22_DRV_MSK           (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
+#define GLB_REG_GPIO_22_DRV_UMSK          (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
+#define GLB_REG_GPIO_22_PU                GLB_REG_GPIO_22_PU
+#define GLB_REG_GPIO_22_PU_POS            (4U)
+#define GLB_REG_GPIO_22_PU_LEN            (1U)
+#define GLB_REG_GPIO_22_PU_MSK            (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
+#define GLB_REG_GPIO_22_PU_UMSK           (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
+#define GLB_REG_GPIO_22_PD                GLB_REG_GPIO_22_PD
+#define GLB_REG_GPIO_22_PD_POS            (5U)
+#define GLB_REG_GPIO_22_PD_LEN            (1U)
+#define GLB_REG_GPIO_22_PD_MSK            (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
+#define GLB_REG_GPIO_22_PD_UMSK           (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
+#define GLB_REG_GPIO_22_OE                GLB_REG_GPIO_22_OE
+#define GLB_REG_GPIO_22_OE_POS            (6U)
+#define GLB_REG_GPIO_22_OE_LEN            (1U)
+#define GLB_REG_GPIO_22_OE_MSK            (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
+#define GLB_REG_GPIO_22_OE_UMSK           (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
+#define GLB_REG_GPIO_22_FUNC_SEL          GLB_REG_GPIO_22_FUNC_SEL
+#define GLB_REG_GPIO_22_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_22_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_22_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
+#define GLB_REG_GPIO_22_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS))
+#define GLB_REG_GPIO_22_INT_MODE_SET      GLB_REG_GPIO_22_INT_MODE_SET
+#define GLB_REG_GPIO_22_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_22_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_22_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_22_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_22_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_22_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_22_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_22_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_22_INT_CLR           GLB_REG_GPIO_22_INT_CLR
+#define GLB_REG_GPIO_22_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_22_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_22_INT_CLR_MSK       (((1U << GLB_REG_GPIO_22_INT_CLR_LEN) - 1) << GLB_REG_GPIO_22_INT_CLR_POS)
+#define GLB_REG_GPIO_22_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_22_INT_CLR_LEN) - 1) << GLB_REG_GPIO_22_INT_CLR_POS))
+#define GLB_GPIO_22_INT_STAT              GLB_GPIO_22_INT_STAT
+#define GLB_GPIO_22_INT_STAT_POS          (21U)
+#define GLB_GPIO_22_INT_STAT_LEN          (1U)
+#define GLB_GPIO_22_INT_STAT_MSK          (((1U << GLB_GPIO_22_INT_STAT_LEN) - 1) << GLB_GPIO_22_INT_STAT_POS)
+#define GLB_GPIO_22_INT_STAT_UMSK         (~(((1U << GLB_GPIO_22_INT_STAT_LEN) - 1) << GLB_GPIO_22_INT_STAT_POS))
+#define GLB_REG_GPIO_22_INT_MASK          GLB_REG_GPIO_22_INT_MASK
+#define GLB_REG_GPIO_22_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_22_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_22_INT_MASK_MSK      (((1U << GLB_REG_GPIO_22_INT_MASK_LEN) - 1) << GLB_REG_GPIO_22_INT_MASK_POS)
+#define GLB_REG_GPIO_22_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_22_INT_MASK_LEN) - 1) << GLB_REG_GPIO_22_INT_MASK_POS))
+#define GLB_REG_GPIO_22_O                 GLB_REG_GPIO_22_O
+#define GLB_REG_GPIO_22_O_POS             (24U)
+#define GLB_REG_GPIO_22_O_LEN             (1U)
+#define GLB_REG_GPIO_22_O_MSK             (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
+#define GLB_REG_GPIO_22_O_UMSK            (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
+#define GLB_REG_GPIO_22_SET               GLB_REG_GPIO_22_SET
+#define GLB_REG_GPIO_22_SET_POS           (25U)
+#define GLB_REG_GPIO_22_SET_LEN           (1U)
+#define GLB_REG_GPIO_22_SET_MSK           (((1U << GLB_REG_GPIO_22_SET_LEN) - 1) << GLB_REG_GPIO_22_SET_POS)
+#define GLB_REG_GPIO_22_SET_UMSK          (~(((1U << GLB_REG_GPIO_22_SET_LEN) - 1) << GLB_REG_GPIO_22_SET_POS))
+#define GLB_REG_GPIO_22_CLR               GLB_REG_GPIO_22_CLR
+#define GLB_REG_GPIO_22_CLR_POS           (26U)
+#define GLB_REG_GPIO_22_CLR_LEN           (1U)
+#define GLB_REG_GPIO_22_CLR_MSK           (((1U << GLB_REG_GPIO_22_CLR_LEN) - 1) << GLB_REG_GPIO_22_CLR_POS)
+#define GLB_REG_GPIO_22_CLR_UMSK          (~(((1U << GLB_REG_GPIO_22_CLR_LEN) - 1) << GLB_REG_GPIO_22_CLR_POS))
+#define GLB_REG_GPIO_22_I                 GLB_REG_GPIO_22_I
+#define GLB_REG_GPIO_22_I_POS             (28U)
+#define GLB_REG_GPIO_22_I_LEN             (1U)
+#define GLB_REG_GPIO_22_I_MSK             (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
+#define GLB_REG_GPIO_22_I_UMSK            (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
+#define GLB_REG_GPIO_22_MODE              GLB_REG_GPIO_22_MODE
+#define GLB_REG_GPIO_22_MODE_POS          (30U)
+#define GLB_REG_GPIO_22_MODE_LEN          (2U)
+#define GLB_REG_GPIO_22_MODE_MSK          (((1U << GLB_REG_GPIO_22_MODE_LEN) - 1) << GLB_REG_GPIO_22_MODE_POS)
+#define GLB_REG_GPIO_22_MODE_UMSK         (~(((1U << GLB_REG_GPIO_22_MODE_LEN) - 1) << GLB_REG_GPIO_22_MODE_POS))
+
+/* 0x920 : gpio_cfg23 */
+#define GLB_GPIO_CFG23_OFFSET             (0x920)
+#define GLB_REG_GPIO_23_IE                GLB_REG_GPIO_23_IE
+#define GLB_REG_GPIO_23_IE_POS            (0U)
+#define GLB_REG_GPIO_23_IE_LEN            (1U)
+#define GLB_REG_GPIO_23_IE_MSK            (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
+#define GLB_REG_GPIO_23_IE_UMSK           (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
+#define GLB_REG_GPIO_23_SMT               GLB_REG_GPIO_23_SMT
+#define GLB_REG_GPIO_23_SMT_POS           (1U)
+#define GLB_REG_GPIO_23_SMT_LEN           (1U)
+#define GLB_REG_GPIO_23_SMT_MSK           (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
+#define GLB_REG_GPIO_23_SMT_UMSK          (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
+#define GLB_REG_GPIO_23_DRV               GLB_REG_GPIO_23_DRV
+#define GLB_REG_GPIO_23_DRV_POS           (2U)
+#define GLB_REG_GPIO_23_DRV_LEN           (2U)
+#define GLB_REG_GPIO_23_DRV_MSK           (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
+#define GLB_REG_GPIO_23_DRV_UMSK          (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
+#define GLB_REG_GPIO_23_PU                GLB_REG_GPIO_23_PU
+#define GLB_REG_GPIO_23_PU_POS            (4U)
+#define GLB_REG_GPIO_23_PU_LEN            (1U)
+#define GLB_REG_GPIO_23_PU_MSK            (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
+#define GLB_REG_GPIO_23_PU_UMSK           (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
+#define GLB_REG_GPIO_23_PD                GLB_REG_GPIO_23_PD
+#define GLB_REG_GPIO_23_PD_POS            (5U)
+#define GLB_REG_GPIO_23_PD_LEN            (1U)
+#define GLB_REG_GPIO_23_PD_MSK            (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
+#define GLB_REG_GPIO_23_PD_UMSK           (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
+#define GLB_REG_GPIO_23_OE                GLB_REG_GPIO_23_OE
+#define GLB_REG_GPIO_23_OE_POS            (6U)
+#define GLB_REG_GPIO_23_OE_LEN            (1U)
+#define GLB_REG_GPIO_23_OE_MSK            (((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS)
+#define GLB_REG_GPIO_23_OE_UMSK           (~(((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS))
+#define GLB_REG_GPIO_23_FUNC_SEL          GLB_REG_GPIO_23_FUNC_SEL
+#define GLB_REG_GPIO_23_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_23_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_23_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS)
+#define GLB_REG_GPIO_23_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS))
+#define GLB_REG_GPIO_23_INT_MODE_SET      GLB_REG_GPIO_23_INT_MODE_SET
+#define GLB_REG_GPIO_23_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_23_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_23_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_23_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_23_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_23_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_23_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_23_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_23_INT_CLR           GLB_REG_GPIO_23_INT_CLR
+#define GLB_REG_GPIO_23_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_23_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_23_INT_CLR_MSK       (((1U << GLB_REG_GPIO_23_INT_CLR_LEN) - 1) << GLB_REG_GPIO_23_INT_CLR_POS)
+#define GLB_REG_GPIO_23_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_23_INT_CLR_LEN) - 1) << GLB_REG_GPIO_23_INT_CLR_POS))
+#define GLB_GPIO_23_INT_STAT              GLB_GPIO_23_INT_STAT
+#define GLB_GPIO_23_INT_STAT_POS          (21U)
+#define GLB_GPIO_23_INT_STAT_LEN          (1U)
+#define GLB_GPIO_23_INT_STAT_MSK          (((1U << GLB_GPIO_23_INT_STAT_LEN) - 1) << GLB_GPIO_23_INT_STAT_POS)
+#define GLB_GPIO_23_INT_STAT_UMSK         (~(((1U << GLB_GPIO_23_INT_STAT_LEN) - 1) << GLB_GPIO_23_INT_STAT_POS))
+#define GLB_REG_GPIO_23_INT_MASK          GLB_REG_GPIO_23_INT_MASK
+#define GLB_REG_GPIO_23_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_23_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_23_INT_MASK_MSK      (((1U << GLB_REG_GPIO_23_INT_MASK_LEN) - 1) << GLB_REG_GPIO_23_INT_MASK_POS)
+#define GLB_REG_GPIO_23_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_23_INT_MASK_LEN) - 1) << GLB_REG_GPIO_23_INT_MASK_POS))
+#define GLB_REG_GPIO_23_O                 GLB_REG_GPIO_23_O
+#define GLB_REG_GPIO_23_O_POS             (24U)
+#define GLB_REG_GPIO_23_O_LEN             (1U)
+#define GLB_REG_GPIO_23_O_MSK             (((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS)
+#define GLB_REG_GPIO_23_O_UMSK            (~(((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS))
+#define GLB_REG_GPIO_23_SET               GLB_REG_GPIO_23_SET
+#define GLB_REG_GPIO_23_SET_POS           (25U)
+#define GLB_REG_GPIO_23_SET_LEN           (1U)
+#define GLB_REG_GPIO_23_SET_MSK           (((1U << GLB_REG_GPIO_23_SET_LEN) - 1) << GLB_REG_GPIO_23_SET_POS)
+#define GLB_REG_GPIO_23_SET_UMSK          (~(((1U << GLB_REG_GPIO_23_SET_LEN) - 1) << GLB_REG_GPIO_23_SET_POS))
+#define GLB_REG_GPIO_23_CLR               GLB_REG_GPIO_23_CLR
+#define GLB_REG_GPIO_23_CLR_POS           (26U)
+#define GLB_REG_GPIO_23_CLR_LEN           (1U)
+#define GLB_REG_GPIO_23_CLR_MSK           (((1U << GLB_REG_GPIO_23_CLR_LEN) - 1) << GLB_REG_GPIO_23_CLR_POS)
+#define GLB_REG_GPIO_23_CLR_UMSK          (~(((1U << GLB_REG_GPIO_23_CLR_LEN) - 1) << GLB_REG_GPIO_23_CLR_POS))
+#define GLB_REG_GPIO_23_I                 GLB_REG_GPIO_23_I
+#define GLB_REG_GPIO_23_I_POS             (28U)
+#define GLB_REG_GPIO_23_I_LEN             (1U)
+#define GLB_REG_GPIO_23_I_MSK             (((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS)
+#define GLB_REG_GPIO_23_I_UMSK            (~(((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS))
+#define GLB_REG_GPIO_23_MODE              GLB_REG_GPIO_23_MODE
+#define GLB_REG_GPIO_23_MODE_POS          (30U)
+#define GLB_REG_GPIO_23_MODE_LEN          (2U)
+#define GLB_REG_GPIO_23_MODE_MSK          (((1U << GLB_REG_GPIO_23_MODE_LEN) - 1) << GLB_REG_GPIO_23_MODE_POS)
+#define GLB_REG_GPIO_23_MODE_UMSK         (~(((1U << GLB_REG_GPIO_23_MODE_LEN) - 1) << GLB_REG_GPIO_23_MODE_POS))
+
+/* 0x924 : gpio_cfg24 */
+#define GLB_GPIO_CFG24_OFFSET             (0x924)
+#define GLB_REG_GPIO_24_IE                GLB_REG_GPIO_24_IE
+#define GLB_REG_GPIO_24_IE_POS            (0U)
+#define GLB_REG_GPIO_24_IE_LEN            (1U)
+#define GLB_REG_GPIO_24_IE_MSK            (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
+#define GLB_REG_GPIO_24_IE_UMSK           (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
+#define GLB_REG_GPIO_24_SMT               GLB_REG_GPIO_24_SMT
+#define GLB_REG_GPIO_24_SMT_POS           (1U)
+#define GLB_REG_GPIO_24_SMT_LEN           (1U)
+#define GLB_REG_GPIO_24_SMT_MSK           (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
+#define GLB_REG_GPIO_24_SMT_UMSK          (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
+#define GLB_REG_GPIO_24_DRV               GLB_REG_GPIO_24_DRV
+#define GLB_REG_GPIO_24_DRV_POS           (2U)
+#define GLB_REG_GPIO_24_DRV_LEN           (2U)
+#define GLB_REG_GPIO_24_DRV_MSK           (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
+#define GLB_REG_GPIO_24_DRV_UMSK          (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
+#define GLB_REG_GPIO_24_PU                GLB_REG_GPIO_24_PU
+#define GLB_REG_GPIO_24_PU_POS            (4U)
+#define GLB_REG_GPIO_24_PU_LEN            (1U)
+#define GLB_REG_GPIO_24_PU_MSK            (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
+#define GLB_REG_GPIO_24_PU_UMSK           (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
+#define GLB_REG_GPIO_24_PD                GLB_REG_GPIO_24_PD
+#define GLB_REG_GPIO_24_PD_POS            (5U)
+#define GLB_REG_GPIO_24_PD_LEN            (1U)
+#define GLB_REG_GPIO_24_PD_MSK            (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
+#define GLB_REG_GPIO_24_PD_UMSK           (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
+#define GLB_REG_GPIO_24_OE                GLB_REG_GPIO_24_OE
+#define GLB_REG_GPIO_24_OE_POS            (6U)
+#define GLB_REG_GPIO_24_OE_LEN            (1U)
+#define GLB_REG_GPIO_24_OE_MSK            (((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS)
+#define GLB_REG_GPIO_24_OE_UMSK           (~(((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS))
+#define GLB_REG_GPIO_24_FUNC_SEL          GLB_REG_GPIO_24_FUNC_SEL
+#define GLB_REG_GPIO_24_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_24_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_24_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS)
+#define GLB_REG_GPIO_24_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS))
+#define GLB_REG_GPIO_24_INT_MODE_SET      GLB_REG_GPIO_24_INT_MODE_SET
+#define GLB_REG_GPIO_24_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_24_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_24_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_24_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_24_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_24_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_24_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_24_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_24_INT_CLR           GLB_REG_GPIO_24_INT_CLR
+#define GLB_REG_GPIO_24_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_24_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_24_INT_CLR_MSK       (((1U << GLB_REG_GPIO_24_INT_CLR_LEN) - 1) << GLB_REG_GPIO_24_INT_CLR_POS)
+#define GLB_REG_GPIO_24_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_24_INT_CLR_LEN) - 1) << GLB_REG_GPIO_24_INT_CLR_POS))
+#define GLB_GPIO_24_INT_STAT              GLB_GPIO_24_INT_STAT
+#define GLB_GPIO_24_INT_STAT_POS          (21U)
+#define GLB_GPIO_24_INT_STAT_LEN          (1U)
+#define GLB_GPIO_24_INT_STAT_MSK          (((1U << GLB_GPIO_24_INT_STAT_LEN) - 1) << GLB_GPIO_24_INT_STAT_POS)
+#define GLB_GPIO_24_INT_STAT_UMSK         (~(((1U << GLB_GPIO_24_INT_STAT_LEN) - 1) << GLB_GPIO_24_INT_STAT_POS))
+#define GLB_REG_GPIO_24_INT_MASK          GLB_REG_GPIO_24_INT_MASK
+#define GLB_REG_GPIO_24_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_24_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_24_INT_MASK_MSK      (((1U << GLB_REG_GPIO_24_INT_MASK_LEN) - 1) << GLB_REG_GPIO_24_INT_MASK_POS)
+#define GLB_REG_GPIO_24_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_24_INT_MASK_LEN) - 1) << GLB_REG_GPIO_24_INT_MASK_POS))
+#define GLB_REG_GPIO_24_O                 GLB_REG_GPIO_24_O
+#define GLB_REG_GPIO_24_O_POS             (24U)
+#define GLB_REG_GPIO_24_O_LEN             (1U)
+#define GLB_REG_GPIO_24_O_MSK             (((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS)
+#define GLB_REG_GPIO_24_O_UMSK            (~(((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS))
+#define GLB_REG_GPIO_24_SET               GLB_REG_GPIO_24_SET
+#define GLB_REG_GPIO_24_SET_POS           (25U)
+#define GLB_REG_GPIO_24_SET_LEN           (1U)
+#define GLB_REG_GPIO_24_SET_MSK           (((1U << GLB_REG_GPIO_24_SET_LEN) - 1) << GLB_REG_GPIO_24_SET_POS)
+#define GLB_REG_GPIO_24_SET_UMSK          (~(((1U << GLB_REG_GPIO_24_SET_LEN) - 1) << GLB_REG_GPIO_24_SET_POS))
+#define GLB_REG_GPIO_24_CLR               GLB_REG_GPIO_24_CLR
+#define GLB_REG_GPIO_24_CLR_POS           (26U)
+#define GLB_REG_GPIO_24_CLR_LEN           (1U)
+#define GLB_REG_GPIO_24_CLR_MSK           (((1U << GLB_REG_GPIO_24_CLR_LEN) - 1) << GLB_REG_GPIO_24_CLR_POS)
+#define GLB_REG_GPIO_24_CLR_UMSK          (~(((1U << GLB_REG_GPIO_24_CLR_LEN) - 1) << GLB_REG_GPIO_24_CLR_POS))
+#define GLB_REG_GPIO_24_I                 GLB_REG_GPIO_24_I
+#define GLB_REG_GPIO_24_I_POS             (28U)
+#define GLB_REG_GPIO_24_I_LEN             (1U)
+#define GLB_REG_GPIO_24_I_MSK             (((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS)
+#define GLB_REG_GPIO_24_I_UMSK            (~(((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS))
+#define GLB_REG_GPIO_24_MODE              GLB_REG_GPIO_24_MODE
+#define GLB_REG_GPIO_24_MODE_POS          (30U)
+#define GLB_REG_GPIO_24_MODE_LEN          (2U)
+#define GLB_REG_GPIO_24_MODE_MSK          (((1U << GLB_REG_GPIO_24_MODE_LEN) - 1) << GLB_REG_GPIO_24_MODE_POS)
+#define GLB_REG_GPIO_24_MODE_UMSK         (~(((1U << GLB_REG_GPIO_24_MODE_LEN) - 1) << GLB_REG_GPIO_24_MODE_POS))
+
+/* 0x928 : gpio_cfg25 */
+#define GLB_GPIO_CFG25_OFFSET             (0x928)
+#define GLB_REG_GPIO_25_IE                GLB_REG_GPIO_25_IE
+#define GLB_REG_GPIO_25_IE_POS            (0U)
+#define GLB_REG_GPIO_25_IE_LEN            (1U)
+#define GLB_REG_GPIO_25_IE_MSK            (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
+#define GLB_REG_GPIO_25_IE_UMSK           (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
+#define GLB_REG_GPIO_25_SMT               GLB_REG_GPIO_25_SMT
+#define GLB_REG_GPIO_25_SMT_POS           (1U)
+#define GLB_REG_GPIO_25_SMT_LEN           (1U)
+#define GLB_REG_GPIO_25_SMT_MSK           (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
+#define GLB_REG_GPIO_25_SMT_UMSK          (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
+#define GLB_REG_GPIO_25_DRV               GLB_REG_GPIO_25_DRV
+#define GLB_REG_GPIO_25_DRV_POS           (2U)
+#define GLB_REG_GPIO_25_DRV_LEN           (2U)
+#define GLB_REG_GPIO_25_DRV_MSK           (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
+#define GLB_REG_GPIO_25_DRV_UMSK          (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
+#define GLB_REG_GPIO_25_PU                GLB_REG_GPIO_25_PU
+#define GLB_REG_GPIO_25_PU_POS            (4U)
+#define GLB_REG_GPIO_25_PU_LEN            (1U)
+#define GLB_REG_GPIO_25_PU_MSK            (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
+#define GLB_REG_GPIO_25_PU_UMSK           (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
+#define GLB_REG_GPIO_25_PD                GLB_REG_GPIO_25_PD
+#define GLB_REG_GPIO_25_PD_POS            (5U)
+#define GLB_REG_GPIO_25_PD_LEN            (1U)
+#define GLB_REG_GPIO_25_PD_MSK            (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
+#define GLB_REG_GPIO_25_PD_UMSK           (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
+#define GLB_REG_GPIO_25_OE                GLB_REG_GPIO_25_OE
+#define GLB_REG_GPIO_25_OE_POS            (6U)
+#define GLB_REG_GPIO_25_OE_LEN            (1U)
+#define GLB_REG_GPIO_25_OE_MSK            (((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS)
+#define GLB_REG_GPIO_25_OE_UMSK           (~(((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS))
+#define GLB_REG_GPIO_25_FUNC_SEL          GLB_REG_GPIO_25_FUNC_SEL
+#define GLB_REG_GPIO_25_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_25_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_25_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS)
+#define GLB_REG_GPIO_25_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS))
+#define GLB_REG_GPIO_25_INT_MODE_SET      GLB_REG_GPIO_25_INT_MODE_SET
+#define GLB_REG_GPIO_25_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_25_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_25_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_25_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_25_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_25_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_25_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_25_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_25_INT_CLR           GLB_REG_GPIO_25_INT_CLR
+#define GLB_REG_GPIO_25_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_25_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_25_INT_CLR_MSK       (((1U << GLB_REG_GPIO_25_INT_CLR_LEN) - 1) << GLB_REG_GPIO_25_INT_CLR_POS)
+#define GLB_REG_GPIO_25_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_25_INT_CLR_LEN) - 1) << GLB_REG_GPIO_25_INT_CLR_POS))
+#define GLB_GPIO_25_INT_STAT              GLB_GPIO_25_INT_STAT
+#define GLB_GPIO_25_INT_STAT_POS          (21U)
+#define GLB_GPIO_25_INT_STAT_LEN          (1U)
+#define GLB_GPIO_25_INT_STAT_MSK          (((1U << GLB_GPIO_25_INT_STAT_LEN) - 1) << GLB_GPIO_25_INT_STAT_POS)
+#define GLB_GPIO_25_INT_STAT_UMSK         (~(((1U << GLB_GPIO_25_INT_STAT_LEN) - 1) << GLB_GPIO_25_INT_STAT_POS))
+#define GLB_REG_GPIO_25_INT_MASK          GLB_REG_GPIO_25_INT_MASK
+#define GLB_REG_GPIO_25_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_25_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_25_INT_MASK_MSK      (((1U << GLB_REG_GPIO_25_INT_MASK_LEN) - 1) << GLB_REG_GPIO_25_INT_MASK_POS)
+#define GLB_REG_GPIO_25_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_25_INT_MASK_LEN) - 1) << GLB_REG_GPIO_25_INT_MASK_POS))
+#define GLB_REG_GPIO_25_O                 GLB_REG_GPIO_25_O
+#define GLB_REG_GPIO_25_O_POS             (24U)
+#define GLB_REG_GPIO_25_O_LEN             (1U)
+#define GLB_REG_GPIO_25_O_MSK             (((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS)
+#define GLB_REG_GPIO_25_O_UMSK            (~(((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS))
+#define GLB_REG_GPIO_25_SET               GLB_REG_GPIO_25_SET
+#define GLB_REG_GPIO_25_SET_POS           (25U)
+#define GLB_REG_GPIO_25_SET_LEN           (1U)
+#define GLB_REG_GPIO_25_SET_MSK           (((1U << GLB_REG_GPIO_25_SET_LEN) - 1) << GLB_REG_GPIO_25_SET_POS)
+#define GLB_REG_GPIO_25_SET_UMSK          (~(((1U << GLB_REG_GPIO_25_SET_LEN) - 1) << GLB_REG_GPIO_25_SET_POS))
+#define GLB_REG_GPIO_25_CLR               GLB_REG_GPIO_25_CLR
+#define GLB_REG_GPIO_25_CLR_POS           (26U)
+#define GLB_REG_GPIO_25_CLR_LEN           (1U)
+#define GLB_REG_GPIO_25_CLR_MSK           (((1U << GLB_REG_GPIO_25_CLR_LEN) - 1) << GLB_REG_GPIO_25_CLR_POS)
+#define GLB_REG_GPIO_25_CLR_UMSK          (~(((1U << GLB_REG_GPIO_25_CLR_LEN) - 1) << GLB_REG_GPIO_25_CLR_POS))
+#define GLB_REG_GPIO_25_I                 GLB_REG_GPIO_25_I
+#define GLB_REG_GPIO_25_I_POS             (28U)
+#define GLB_REG_GPIO_25_I_LEN             (1U)
+#define GLB_REG_GPIO_25_I_MSK             (((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS)
+#define GLB_REG_GPIO_25_I_UMSK            (~(((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS))
+#define GLB_REG_GPIO_25_MODE              GLB_REG_GPIO_25_MODE
+#define GLB_REG_GPIO_25_MODE_POS          (30U)
+#define GLB_REG_GPIO_25_MODE_LEN          (2U)
+#define GLB_REG_GPIO_25_MODE_MSK          (((1U << GLB_REG_GPIO_25_MODE_LEN) - 1) << GLB_REG_GPIO_25_MODE_POS)
+#define GLB_REG_GPIO_25_MODE_UMSK         (~(((1U << GLB_REG_GPIO_25_MODE_LEN) - 1) << GLB_REG_GPIO_25_MODE_POS))
+
+/* 0x92C : gpio_cfg26 */
+#define GLB_GPIO_CFG26_OFFSET             (0x92C)
+#define GLB_REG_GPIO_26_IE                GLB_REG_GPIO_26_IE
+#define GLB_REG_GPIO_26_IE_POS            (0U)
+#define GLB_REG_GPIO_26_IE_LEN            (1U)
+#define GLB_REG_GPIO_26_IE_MSK            (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
+#define GLB_REG_GPIO_26_IE_UMSK           (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
+#define GLB_REG_GPIO_26_SMT               GLB_REG_GPIO_26_SMT
+#define GLB_REG_GPIO_26_SMT_POS           (1U)
+#define GLB_REG_GPIO_26_SMT_LEN           (1U)
+#define GLB_REG_GPIO_26_SMT_MSK           (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
+#define GLB_REG_GPIO_26_SMT_UMSK          (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
+#define GLB_REG_GPIO_26_DRV               GLB_REG_GPIO_26_DRV
+#define GLB_REG_GPIO_26_DRV_POS           (2U)
+#define GLB_REG_GPIO_26_DRV_LEN           (2U)
+#define GLB_REG_GPIO_26_DRV_MSK           (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
+#define GLB_REG_GPIO_26_DRV_UMSK          (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
+#define GLB_REG_GPIO_26_PU                GLB_REG_GPIO_26_PU
+#define GLB_REG_GPIO_26_PU_POS            (4U)
+#define GLB_REG_GPIO_26_PU_LEN            (1U)
+#define GLB_REG_GPIO_26_PU_MSK            (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
+#define GLB_REG_GPIO_26_PU_UMSK           (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
+#define GLB_REG_GPIO_26_PD                GLB_REG_GPIO_26_PD
+#define GLB_REG_GPIO_26_PD_POS            (5U)
+#define GLB_REG_GPIO_26_PD_LEN            (1U)
+#define GLB_REG_GPIO_26_PD_MSK            (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
+#define GLB_REG_GPIO_26_PD_UMSK           (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
+#define GLB_REG_GPIO_26_OE                GLB_REG_GPIO_26_OE
+#define GLB_REG_GPIO_26_OE_POS            (6U)
+#define GLB_REG_GPIO_26_OE_LEN            (1U)
+#define GLB_REG_GPIO_26_OE_MSK            (((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS)
+#define GLB_REG_GPIO_26_OE_UMSK           (~(((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS))
+#define GLB_REG_GPIO_26_FUNC_SEL          GLB_REG_GPIO_26_FUNC_SEL
+#define GLB_REG_GPIO_26_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_26_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_26_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS)
+#define GLB_REG_GPIO_26_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS))
+#define GLB_REG_GPIO_26_INT_MODE_SET      GLB_REG_GPIO_26_INT_MODE_SET
+#define GLB_REG_GPIO_26_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_26_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_26_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_26_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_26_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_26_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_26_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_26_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_26_INT_CLR           GLB_REG_GPIO_26_INT_CLR
+#define GLB_REG_GPIO_26_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_26_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_26_INT_CLR_MSK       (((1U << GLB_REG_GPIO_26_INT_CLR_LEN) - 1) << GLB_REG_GPIO_26_INT_CLR_POS)
+#define GLB_REG_GPIO_26_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_26_INT_CLR_LEN) - 1) << GLB_REG_GPIO_26_INT_CLR_POS))
+#define GLB_GPIO_26_INT_STAT              GLB_GPIO_26_INT_STAT
+#define GLB_GPIO_26_INT_STAT_POS          (21U)
+#define GLB_GPIO_26_INT_STAT_LEN          (1U)
+#define GLB_GPIO_26_INT_STAT_MSK          (((1U << GLB_GPIO_26_INT_STAT_LEN) - 1) << GLB_GPIO_26_INT_STAT_POS)
+#define GLB_GPIO_26_INT_STAT_UMSK         (~(((1U << GLB_GPIO_26_INT_STAT_LEN) - 1) << GLB_GPIO_26_INT_STAT_POS))
+#define GLB_REG_GPIO_26_INT_MASK          GLB_REG_GPIO_26_INT_MASK
+#define GLB_REG_GPIO_26_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_26_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_26_INT_MASK_MSK      (((1U << GLB_REG_GPIO_26_INT_MASK_LEN) - 1) << GLB_REG_GPIO_26_INT_MASK_POS)
+#define GLB_REG_GPIO_26_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_26_INT_MASK_LEN) - 1) << GLB_REG_GPIO_26_INT_MASK_POS))
+#define GLB_REG_GPIO_26_O                 GLB_REG_GPIO_26_O
+#define GLB_REG_GPIO_26_O_POS             (24U)
+#define GLB_REG_GPIO_26_O_LEN             (1U)
+#define GLB_REG_GPIO_26_O_MSK             (((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS)
+#define GLB_REG_GPIO_26_O_UMSK            (~(((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS))
+#define GLB_REG_GPIO_26_SET               GLB_REG_GPIO_26_SET
+#define GLB_REG_GPIO_26_SET_POS           (25U)
+#define GLB_REG_GPIO_26_SET_LEN           (1U)
+#define GLB_REG_GPIO_26_SET_MSK           (((1U << GLB_REG_GPIO_26_SET_LEN) - 1) << GLB_REG_GPIO_26_SET_POS)
+#define GLB_REG_GPIO_26_SET_UMSK          (~(((1U << GLB_REG_GPIO_26_SET_LEN) - 1) << GLB_REG_GPIO_26_SET_POS))
+#define GLB_REG_GPIO_26_CLR               GLB_REG_GPIO_26_CLR
+#define GLB_REG_GPIO_26_CLR_POS           (26U)
+#define GLB_REG_GPIO_26_CLR_LEN           (1U)
+#define GLB_REG_GPIO_26_CLR_MSK           (((1U << GLB_REG_GPIO_26_CLR_LEN) - 1) << GLB_REG_GPIO_26_CLR_POS)
+#define GLB_REG_GPIO_26_CLR_UMSK          (~(((1U << GLB_REG_GPIO_26_CLR_LEN) - 1) << GLB_REG_GPIO_26_CLR_POS))
+#define GLB_REG_GPIO_26_I                 GLB_REG_GPIO_26_I
+#define GLB_REG_GPIO_26_I_POS             (28U)
+#define GLB_REG_GPIO_26_I_LEN             (1U)
+#define GLB_REG_GPIO_26_I_MSK             (((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS)
+#define GLB_REG_GPIO_26_I_UMSK            (~(((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS))
+#define GLB_REG_GPIO_26_MODE              GLB_REG_GPIO_26_MODE
+#define GLB_REG_GPIO_26_MODE_POS          (30U)
+#define GLB_REG_GPIO_26_MODE_LEN          (2U)
+#define GLB_REG_GPIO_26_MODE_MSK          (((1U << GLB_REG_GPIO_26_MODE_LEN) - 1) << GLB_REG_GPIO_26_MODE_POS)
+#define GLB_REG_GPIO_26_MODE_UMSK         (~(((1U << GLB_REG_GPIO_26_MODE_LEN) - 1) << GLB_REG_GPIO_26_MODE_POS))
+
+/* 0x930 : gpio_cfg27 */
+#define GLB_GPIO_CFG27_OFFSET             (0x930)
+#define GLB_REG_GPIO_27_IE                GLB_REG_GPIO_27_IE
+#define GLB_REG_GPIO_27_IE_POS            (0U)
+#define GLB_REG_GPIO_27_IE_LEN            (1U)
+#define GLB_REG_GPIO_27_IE_MSK            (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
+#define GLB_REG_GPIO_27_IE_UMSK           (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
+#define GLB_REG_GPIO_27_SMT               GLB_REG_GPIO_27_SMT
+#define GLB_REG_GPIO_27_SMT_POS           (1U)
+#define GLB_REG_GPIO_27_SMT_LEN           (1U)
+#define GLB_REG_GPIO_27_SMT_MSK           (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
+#define GLB_REG_GPIO_27_SMT_UMSK          (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
+#define GLB_REG_GPIO_27_DRV               GLB_REG_GPIO_27_DRV
+#define GLB_REG_GPIO_27_DRV_POS           (2U)
+#define GLB_REG_GPIO_27_DRV_LEN           (2U)
+#define GLB_REG_GPIO_27_DRV_MSK           (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
+#define GLB_REG_GPIO_27_DRV_UMSK          (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
+#define GLB_REG_GPIO_27_PU                GLB_REG_GPIO_27_PU
+#define GLB_REG_GPIO_27_PU_POS            (4U)
+#define GLB_REG_GPIO_27_PU_LEN            (1U)
+#define GLB_REG_GPIO_27_PU_MSK            (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
+#define GLB_REG_GPIO_27_PU_UMSK           (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
+#define GLB_REG_GPIO_27_PD                GLB_REG_GPIO_27_PD
+#define GLB_REG_GPIO_27_PD_POS            (5U)
+#define GLB_REG_GPIO_27_PD_LEN            (1U)
+#define GLB_REG_GPIO_27_PD_MSK            (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
+#define GLB_REG_GPIO_27_PD_UMSK           (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
+#define GLB_REG_GPIO_27_OE                GLB_REG_GPIO_27_OE
+#define GLB_REG_GPIO_27_OE_POS            (6U)
+#define GLB_REG_GPIO_27_OE_LEN            (1U)
+#define GLB_REG_GPIO_27_OE_MSK            (((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS)
+#define GLB_REG_GPIO_27_OE_UMSK           (~(((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS))
+#define GLB_REG_GPIO_27_FUNC_SEL          GLB_REG_GPIO_27_FUNC_SEL
+#define GLB_REG_GPIO_27_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_27_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_27_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS)
+#define GLB_REG_GPIO_27_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS))
+#define GLB_REG_GPIO_27_INT_MODE_SET      GLB_REG_GPIO_27_INT_MODE_SET
+#define GLB_REG_GPIO_27_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_27_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_27_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_27_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_27_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_27_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_27_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_27_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_27_INT_CLR           GLB_REG_GPIO_27_INT_CLR
+#define GLB_REG_GPIO_27_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_27_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_27_INT_CLR_MSK       (((1U << GLB_REG_GPIO_27_INT_CLR_LEN) - 1) << GLB_REG_GPIO_27_INT_CLR_POS)
+#define GLB_REG_GPIO_27_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_27_INT_CLR_LEN) - 1) << GLB_REG_GPIO_27_INT_CLR_POS))
+#define GLB_GPIO_27_INT_STAT              GLB_GPIO_27_INT_STAT
+#define GLB_GPIO_27_INT_STAT_POS          (21U)
+#define GLB_GPIO_27_INT_STAT_LEN          (1U)
+#define GLB_GPIO_27_INT_STAT_MSK          (((1U << GLB_GPIO_27_INT_STAT_LEN) - 1) << GLB_GPIO_27_INT_STAT_POS)
+#define GLB_GPIO_27_INT_STAT_UMSK         (~(((1U << GLB_GPIO_27_INT_STAT_LEN) - 1) << GLB_GPIO_27_INT_STAT_POS))
+#define GLB_REG_GPIO_27_INT_MASK          GLB_REG_GPIO_27_INT_MASK
+#define GLB_REG_GPIO_27_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_27_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_27_INT_MASK_MSK      (((1U << GLB_REG_GPIO_27_INT_MASK_LEN) - 1) << GLB_REG_GPIO_27_INT_MASK_POS)
+#define GLB_REG_GPIO_27_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_27_INT_MASK_LEN) - 1) << GLB_REG_GPIO_27_INT_MASK_POS))
+#define GLB_REG_GPIO_27_O                 GLB_REG_GPIO_27_O
+#define GLB_REG_GPIO_27_O_POS             (24U)
+#define GLB_REG_GPIO_27_O_LEN             (1U)
+#define GLB_REG_GPIO_27_O_MSK             (((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS)
+#define GLB_REG_GPIO_27_O_UMSK            (~(((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS))
+#define GLB_REG_GPIO_27_SET               GLB_REG_GPIO_27_SET
+#define GLB_REG_GPIO_27_SET_POS           (25U)
+#define GLB_REG_GPIO_27_SET_LEN           (1U)
+#define GLB_REG_GPIO_27_SET_MSK           (((1U << GLB_REG_GPIO_27_SET_LEN) - 1) << GLB_REG_GPIO_27_SET_POS)
+#define GLB_REG_GPIO_27_SET_UMSK          (~(((1U << GLB_REG_GPIO_27_SET_LEN) - 1) << GLB_REG_GPIO_27_SET_POS))
+#define GLB_REG_GPIO_27_CLR               GLB_REG_GPIO_27_CLR
+#define GLB_REG_GPIO_27_CLR_POS           (26U)
+#define GLB_REG_GPIO_27_CLR_LEN           (1U)
+#define GLB_REG_GPIO_27_CLR_MSK           (((1U << GLB_REG_GPIO_27_CLR_LEN) - 1) << GLB_REG_GPIO_27_CLR_POS)
+#define GLB_REG_GPIO_27_CLR_UMSK          (~(((1U << GLB_REG_GPIO_27_CLR_LEN) - 1) << GLB_REG_GPIO_27_CLR_POS))
+#define GLB_REG_GPIO_27_I                 GLB_REG_GPIO_27_I
+#define GLB_REG_GPIO_27_I_POS             (28U)
+#define GLB_REG_GPIO_27_I_LEN             (1U)
+#define GLB_REG_GPIO_27_I_MSK             (((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS)
+#define GLB_REG_GPIO_27_I_UMSK            (~(((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS))
+#define GLB_REG_GPIO_27_MODE              GLB_REG_GPIO_27_MODE
+#define GLB_REG_GPIO_27_MODE_POS          (30U)
+#define GLB_REG_GPIO_27_MODE_LEN          (2U)
+#define GLB_REG_GPIO_27_MODE_MSK          (((1U << GLB_REG_GPIO_27_MODE_LEN) - 1) << GLB_REG_GPIO_27_MODE_POS)
+#define GLB_REG_GPIO_27_MODE_UMSK         (~(((1U << GLB_REG_GPIO_27_MODE_LEN) - 1) << GLB_REG_GPIO_27_MODE_POS))
+
+/* 0x934 : gpio_cfg28 */
+#define GLB_GPIO_CFG28_OFFSET             (0x934)
+#define GLB_REG_GPIO_28_IE                GLB_REG_GPIO_28_IE
+#define GLB_REG_GPIO_28_IE_POS            (0U)
+#define GLB_REG_GPIO_28_IE_LEN            (1U)
+#define GLB_REG_GPIO_28_IE_MSK            (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
+#define GLB_REG_GPIO_28_IE_UMSK           (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
+#define GLB_REG_GPIO_28_SMT               GLB_REG_GPIO_28_SMT
+#define GLB_REG_GPIO_28_SMT_POS           (1U)
+#define GLB_REG_GPIO_28_SMT_LEN           (1U)
+#define GLB_REG_GPIO_28_SMT_MSK           (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
+#define GLB_REG_GPIO_28_SMT_UMSK          (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
+#define GLB_REG_GPIO_28_DRV               GLB_REG_GPIO_28_DRV
+#define GLB_REG_GPIO_28_DRV_POS           (2U)
+#define GLB_REG_GPIO_28_DRV_LEN           (2U)
+#define GLB_REG_GPIO_28_DRV_MSK           (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
+#define GLB_REG_GPIO_28_DRV_UMSK          (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
+#define GLB_REG_GPIO_28_PU                GLB_REG_GPIO_28_PU
+#define GLB_REG_GPIO_28_PU_POS            (4U)
+#define GLB_REG_GPIO_28_PU_LEN            (1U)
+#define GLB_REG_GPIO_28_PU_MSK            (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
+#define GLB_REG_GPIO_28_PU_UMSK           (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
+#define GLB_REG_GPIO_28_PD                GLB_REG_GPIO_28_PD
+#define GLB_REG_GPIO_28_PD_POS            (5U)
+#define GLB_REG_GPIO_28_PD_LEN            (1U)
+#define GLB_REG_GPIO_28_PD_MSK            (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
+#define GLB_REG_GPIO_28_PD_UMSK           (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
+#define GLB_REG_GPIO_28_OE                GLB_REG_GPIO_28_OE
+#define GLB_REG_GPIO_28_OE_POS            (6U)
+#define GLB_REG_GPIO_28_OE_LEN            (1U)
+#define GLB_REG_GPIO_28_OE_MSK            (((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS)
+#define GLB_REG_GPIO_28_OE_UMSK           (~(((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS))
+#define GLB_REG_GPIO_28_FUNC_SEL          GLB_REG_GPIO_28_FUNC_SEL
+#define GLB_REG_GPIO_28_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_28_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_28_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS)
+#define GLB_REG_GPIO_28_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS))
+#define GLB_REG_GPIO_28_INT_MODE_SET      GLB_REG_GPIO_28_INT_MODE_SET
+#define GLB_REG_GPIO_28_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_28_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_28_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_28_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_28_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_28_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_28_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_28_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_28_INT_CLR           GLB_REG_GPIO_28_INT_CLR
+#define GLB_REG_GPIO_28_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_28_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_28_INT_CLR_MSK       (((1U << GLB_REG_GPIO_28_INT_CLR_LEN) - 1) << GLB_REG_GPIO_28_INT_CLR_POS)
+#define GLB_REG_GPIO_28_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_28_INT_CLR_LEN) - 1) << GLB_REG_GPIO_28_INT_CLR_POS))
+#define GLB_GPIO_28_INT_STAT              GLB_GPIO_28_INT_STAT
+#define GLB_GPIO_28_INT_STAT_POS          (21U)
+#define GLB_GPIO_28_INT_STAT_LEN          (1U)
+#define GLB_GPIO_28_INT_STAT_MSK          (((1U << GLB_GPIO_28_INT_STAT_LEN) - 1) << GLB_GPIO_28_INT_STAT_POS)
+#define GLB_GPIO_28_INT_STAT_UMSK         (~(((1U << GLB_GPIO_28_INT_STAT_LEN) - 1) << GLB_GPIO_28_INT_STAT_POS))
+#define GLB_REG_GPIO_28_INT_MASK          GLB_REG_GPIO_28_INT_MASK
+#define GLB_REG_GPIO_28_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_28_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_28_INT_MASK_MSK      (((1U << GLB_REG_GPIO_28_INT_MASK_LEN) - 1) << GLB_REG_GPIO_28_INT_MASK_POS)
+#define GLB_REG_GPIO_28_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_28_INT_MASK_LEN) - 1) << GLB_REG_GPIO_28_INT_MASK_POS))
+#define GLB_REG_GPIO_28_O                 GLB_REG_GPIO_28_O
+#define GLB_REG_GPIO_28_O_POS             (24U)
+#define GLB_REG_GPIO_28_O_LEN             (1U)
+#define GLB_REG_GPIO_28_O_MSK             (((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS)
+#define GLB_REG_GPIO_28_O_UMSK            (~(((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS))
+#define GLB_REG_GPIO_28_SET               GLB_REG_GPIO_28_SET
+#define GLB_REG_GPIO_28_SET_POS           (25U)
+#define GLB_REG_GPIO_28_SET_LEN           (1U)
+#define GLB_REG_GPIO_28_SET_MSK           (((1U << GLB_REG_GPIO_28_SET_LEN) - 1) << GLB_REG_GPIO_28_SET_POS)
+#define GLB_REG_GPIO_28_SET_UMSK          (~(((1U << GLB_REG_GPIO_28_SET_LEN) - 1) << GLB_REG_GPIO_28_SET_POS))
+#define GLB_REG_GPIO_28_CLR               GLB_REG_GPIO_28_CLR
+#define GLB_REG_GPIO_28_CLR_POS           (26U)
+#define GLB_REG_GPIO_28_CLR_LEN           (1U)
+#define GLB_REG_GPIO_28_CLR_MSK           (((1U << GLB_REG_GPIO_28_CLR_LEN) - 1) << GLB_REG_GPIO_28_CLR_POS)
+#define GLB_REG_GPIO_28_CLR_UMSK          (~(((1U << GLB_REG_GPIO_28_CLR_LEN) - 1) << GLB_REG_GPIO_28_CLR_POS))
+#define GLB_REG_GPIO_28_I                 GLB_REG_GPIO_28_I
+#define GLB_REG_GPIO_28_I_POS             (28U)
+#define GLB_REG_GPIO_28_I_LEN             (1U)
+#define GLB_REG_GPIO_28_I_MSK             (((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS)
+#define GLB_REG_GPIO_28_I_UMSK            (~(((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS))
+#define GLB_REG_GPIO_28_MODE              GLB_REG_GPIO_28_MODE
+#define GLB_REG_GPIO_28_MODE_POS          (30U)
+#define GLB_REG_GPIO_28_MODE_LEN          (2U)
+#define GLB_REG_GPIO_28_MODE_MSK          (((1U << GLB_REG_GPIO_28_MODE_LEN) - 1) << GLB_REG_GPIO_28_MODE_POS)
+#define GLB_REG_GPIO_28_MODE_UMSK         (~(((1U << GLB_REG_GPIO_28_MODE_LEN) - 1) << GLB_REG_GPIO_28_MODE_POS))
+
+/* 0x938 : gpio_cfg29 */
+#define GLB_GPIO_CFG29_OFFSET             (0x938)
+#define GLB_REG_GPIO_29_IE                GLB_REG_GPIO_29_IE
+#define GLB_REG_GPIO_29_IE_POS            (0U)
+#define GLB_REG_GPIO_29_IE_LEN            (1U)
+#define GLB_REG_GPIO_29_IE_MSK            (((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS)
+#define GLB_REG_GPIO_29_IE_UMSK           (~(((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS))
+#define GLB_REG_GPIO_29_SMT               GLB_REG_GPIO_29_SMT
+#define GLB_REG_GPIO_29_SMT_POS           (1U)
+#define GLB_REG_GPIO_29_SMT_LEN           (1U)
+#define GLB_REG_GPIO_29_SMT_MSK           (((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS)
+#define GLB_REG_GPIO_29_SMT_UMSK          (~(((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS))
+#define GLB_REG_GPIO_29_DRV               GLB_REG_GPIO_29_DRV
+#define GLB_REG_GPIO_29_DRV_POS           (2U)
+#define GLB_REG_GPIO_29_DRV_LEN           (2U)
+#define GLB_REG_GPIO_29_DRV_MSK           (((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS)
+#define GLB_REG_GPIO_29_DRV_UMSK          (~(((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS))
+#define GLB_REG_GPIO_29_PU                GLB_REG_GPIO_29_PU
+#define GLB_REG_GPIO_29_PU_POS            (4U)
+#define GLB_REG_GPIO_29_PU_LEN            (1U)
+#define GLB_REG_GPIO_29_PU_MSK            (((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS)
+#define GLB_REG_GPIO_29_PU_UMSK           (~(((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS))
+#define GLB_REG_GPIO_29_PD                GLB_REG_GPIO_29_PD
+#define GLB_REG_GPIO_29_PD_POS            (5U)
+#define GLB_REG_GPIO_29_PD_LEN            (1U)
+#define GLB_REG_GPIO_29_PD_MSK            (((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS)
+#define GLB_REG_GPIO_29_PD_UMSK           (~(((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS))
+#define GLB_REG_GPIO_29_OE                GLB_REG_GPIO_29_OE
+#define GLB_REG_GPIO_29_OE_POS            (6U)
+#define GLB_REG_GPIO_29_OE_LEN            (1U)
+#define GLB_REG_GPIO_29_OE_MSK            (((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS)
+#define GLB_REG_GPIO_29_OE_UMSK           (~(((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS))
+#define GLB_REG_GPIO_29_FUNC_SEL          GLB_REG_GPIO_29_FUNC_SEL
+#define GLB_REG_GPIO_29_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_29_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_29_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS)
+#define GLB_REG_GPIO_29_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS))
+#define GLB_REG_GPIO_29_INT_MODE_SET      GLB_REG_GPIO_29_INT_MODE_SET
+#define GLB_REG_GPIO_29_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_29_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_29_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_29_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_29_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_29_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_29_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_29_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_29_INT_CLR           GLB_REG_GPIO_29_INT_CLR
+#define GLB_REG_GPIO_29_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_29_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_29_INT_CLR_MSK       (((1U << GLB_REG_GPIO_29_INT_CLR_LEN) - 1) << GLB_REG_GPIO_29_INT_CLR_POS)
+#define GLB_REG_GPIO_29_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_29_INT_CLR_LEN) - 1) << GLB_REG_GPIO_29_INT_CLR_POS))
+#define GLB_GPIO_29_INT_STAT              GLB_GPIO_29_INT_STAT
+#define GLB_GPIO_29_INT_STAT_POS          (21U)
+#define GLB_GPIO_29_INT_STAT_LEN          (1U)
+#define GLB_GPIO_29_INT_STAT_MSK          (((1U << GLB_GPIO_29_INT_STAT_LEN) - 1) << GLB_GPIO_29_INT_STAT_POS)
+#define GLB_GPIO_29_INT_STAT_UMSK         (~(((1U << GLB_GPIO_29_INT_STAT_LEN) - 1) << GLB_GPIO_29_INT_STAT_POS))
+#define GLB_REG_GPIO_29_INT_MASK          GLB_REG_GPIO_29_INT_MASK
+#define GLB_REG_GPIO_29_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_29_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_29_INT_MASK_MSK      (((1U << GLB_REG_GPIO_29_INT_MASK_LEN) - 1) << GLB_REG_GPIO_29_INT_MASK_POS)
+#define GLB_REG_GPIO_29_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_29_INT_MASK_LEN) - 1) << GLB_REG_GPIO_29_INT_MASK_POS))
+#define GLB_REG_GPIO_29_O                 GLB_REG_GPIO_29_O
+#define GLB_REG_GPIO_29_O_POS             (24U)
+#define GLB_REG_GPIO_29_O_LEN             (1U)
+#define GLB_REG_GPIO_29_O_MSK             (((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS)
+#define GLB_REG_GPIO_29_O_UMSK            (~(((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS))
+#define GLB_REG_GPIO_29_SET               GLB_REG_GPIO_29_SET
+#define GLB_REG_GPIO_29_SET_POS           (25U)
+#define GLB_REG_GPIO_29_SET_LEN           (1U)
+#define GLB_REG_GPIO_29_SET_MSK           (((1U << GLB_REG_GPIO_29_SET_LEN) - 1) << GLB_REG_GPIO_29_SET_POS)
+#define GLB_REG_GPIO_29_SET_UMSK          (~(((1U << GLB_REG_GPIO_29_SET_LEN) - 1) << GLB_REG_GPIO_29_SET_POS))
+#define GLB_REG_GPIO_29_CLR               GLB_REG_GPIO_29_CLR
+#define GLB_REG_GPIO_29_CLR_POS           (26U)
+#define GLB_REG_GPIO_29_CLR_LEN           (1U)
+#define GLB_REG_GPIO_29_CLR_MSK           (((1U << GLB_REG_GPIO_29_CLR_LEN) - 1) << GLB_REG_GPIO_29_CLR_POS)
+#define GLB_REG_GPIO_29_CLR_UMSK          (~(((1U << GLB_REG_GPIO_29_CLR_LEN) - 1) << GLB_REG_GPIO_29_CLR_POS))
+#define GLB_REG_GPIO_29_I                 GLB_REG_GPIO_29_I
+#define GLB_REG_GPIO_29_I_POS             (28U)
+#define GLB_REG_GPIO_29_I_LEN             (1U)
+#define GLB_REG_GPIO_29_I_MSK             (((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS)
+#define GLB_REG_GPIO_29_I_UMSK            (~(((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS))
+#define GLB_REG_GPIO_29_MODE              GLB_REG_GPIO_29_MODE
+#define GLB_REG_GPIO_29_MODE_POS          (30U)
+#define GLB_REG_GPIO_29_MODE_LEN          (2U)
+#define GLB_REG_GPIO_29_MODE_MSK          (((1U << GLB_REG_GPIO_29_MODE_LEN) - 1) << GLB_REG_GPIO_29_MODE_POS)
+#define GLB_REG_GPIO_29_MODE_UMSK         (~(((1U << GLB_REG_GPIO_29_MODE_LEN) - 1) << GLB_REG_GPIO_29_MODE_POS))
+
+/* 0x93C : gpio_cfg30 */
+#define GLB_GPIO_CFG30_OFFSET             (0x93C)
+#define GLB_REG_GPIO_30_IE                GLB_REG_GPIO_30_IE
+#define GLB_REG_GPIO_30_IE_POS            (0U)
+#define GLB_REG_GPIO_30_IE_LEN            (1U)
+#define GLB_REG_GPIO_30_IE_MSK            (((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS)
+#define GLB_REG_GPIO_30_IE_UMSK           (~(((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS))
+#define GLB_REG_GPIO_30_SMT               GLB_REG_GPIO_30_SMT
+#define GLB_REG_GPIO_30_SMT_POS           (1U)
+#define GLB_REG_GPIO_30_SMT_LEN           (1U)
+#define GLB_REG_GPIO_30_SMT_MSK           (((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS)
+#define GLB_REG_GPIO_30_SMT_UMSK          (~(((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS))
+#define GLB_REG_GPIO_30_DRV               GLB_REG_GPIO_30_DRV
+#define GLB_REG_GPIO_30_DRV_POS           (2U)
+#define GLB_REG_GPIO_30_DRV_LEN           (2U)
+#define GLB_REG_GPIO_30_DRV_MSK           (((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS)
+#define GLB_REG_GPIO_30_DRV_UMSK          (~(((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS))
+#define GLB_REG_GPIO_30_PU                GLB_REG_GPIO_30_PU
+#define GLB_REG_GPIO_30_PU_POS            (4U)
+#define GLB_REG_GPIO_30_PU_LEN            (1U)
+#define GLB_REG_GPIO_30_PU_MSK            (((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS)
+#define GLB_REG_GPIO_30_PU_UMSK           (~(((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS))
+#define GLB_REG_GPIO_30_PD                GLB_REG_GPIO_30_PD
+#define GLB_REG_GPIO_30_PD_POS            (5U)
+#define GLB_REG_GPIO_30_PD_LEN            (1U)
+#define GLB_REG_GPIO_30_PD_MSK            (((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS)
+#define GLB_REG_GPIO_30_PD_UMSK           (~(((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS))
+#define GLB_REG_GPIO_30_OE                GLB_REG_GPIO_30_OE
+#define GLB_REG_GPIO_30_OE_POS            (6U)
+#define GLB_REG_GPIO_30_OE_LEN            (1U)
+#define GLB_REG_GPIO_30_OE_MSK            (((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS)
+#define GLB_REG_GPIO_30_OE_UMSK           (~(((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS))
+#define GLB_REG_GPIO_30_FUNC_SEL          GLB_REG_GPIO_30_FUNC_SEL
+#define GLB_REG_GPIO_30_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_30_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_30_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS)
+#define GLB_REG_GPIO_30_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS))
+#define GLB_REG_GPIO_30_INT_MODE_SET      GLB_REG_GPIO_30_INT_MODE_SET
+#define GLB_REG_GPIO_30_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_30_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_30_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_30_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_30_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_30_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_30_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_30_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_30_INT_CLR           GLB_REG_GPIO_30_INT_CLR
+#define GLB_REG_GPIO_30_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_30_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_30_INT_CLR_MSK       (((1U << GLB_REG_GPIO_30_INT_CLR_LEN) - 1) << GLB_REG_GPIO_30_INT_CLR_POS)
+#define GLB_REG_GPIO_30_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_30_INT_CLR_LEN) - 1) << GLB_REG_GPIO_30_INT_CLR_POS))
+#define GLB_GPIO_30_INT_STAT              GLB_GPIO_30_INT_STAT
+#define GLB_GPIO_30_INT_STAT_POS          (21U)
+#define GLB_GPIO_30_INT_STAT_LEN          (1U)
+#define GLB_GPIO_30_INT_STAT_MSK          (((1U << GLB_GPIO_30_INT_STAT_LEN) - 1) << GLB_GPIO_30_INT_STAT_POS)
+#define GLB_GPIO_30_INT_STAT_UMSK         (~(((1U << GLB_GPIO_30_INT_STAT_LEN) - 1) << GLB_GPIO_30_INT_STAT_POS))
+#define GLB_REG_GPIO_30_INT_MASK          GLB_REG_GPIO_30_INT_MASK
+#define GLB_REG_GPIO_30_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_30_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_30_INT_MASK_MSK      (((1U << GLB_REG_GPIO_30_INT_MASK_LEN) - 1) << GLB_REG_GPIO_30_INT_MASK_POS)
+#define GLB_REG_GPIO_30_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_30_INT_MASK_LEN) - 1) << GLB_REG_GPIO_30_INT_MASK_POS))
+#define GLB_REG_GPIO_30_O                 GLB_REG_GPIO_30_O
+#define GLB_REG_GPIO_30_O_POS             (24U)
+#define GLB_REG_GPIO_30_O_LEN             (1U)
+#define GLB_REG_GPIO_30_O_MSK             (((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS)
+#define GLB_REG_GPIO_30_O_UMSK            (~(((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS))
+#define GLB_REG_GPIO_30_SET               GLB_REG_GPIO_30_SET
+#define GLB_REG_GPIO_30_SET_POS           (25U)
+#define GLB_REG_GPIO_30_SET_LEN           (1U)
+#define GLB_REG_GPIO_30_SET_MSK           (((1U << GLB_REG_GPIO_30_SET_LEN) - 1) << GLB_REG_GPIO_30_SET_POS)
+#define GLB_REG_GPIO_30_SET_UMSK          (~(((1U << GLB_REG_GPIO_30_SET_LEN) - 1) << GLB_REG_GPIO_30_SET_POS))
+#define GLB_REG_GPIO_30_CLR               GLB_REG_GPIO_30_CLR
+#define GLB_REG_GPIO_30_CLR_POS           (26U)
+#define GLB_REG_GPIO_30_CLR_LEN           (1U)
+#define GLB_REG_GPIO_30_CLR_MSK           (((1U << GLB_REG_GPIO_30_CLR_LEN) - 1) << GLB_REG_GPIO_30_CLR_POS)
+#define GLB_REG_GPIO_30_CLR_UMSK          (~(((1U << GLB_REG_GPIO_30_CLR_LEN) - 1) << GLB_REG_GPIO_30_CLR_POS))
+#define GLB_REG_GPIO_30_I                 GLB_REG_GPIO_30_I
+#define GLB_REG_GPIO_30_I_POS             (28U)
+#define GLB_REG_GPIO_30_I_LEN             (1U)
+#define GLB_REG_GPIO_30_I_MSK             (((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS)
+#define GLB_REG_GPIO_30_I_UMSK            (~(((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS))
+#define GLB_REG_GPIO_30_MODE              GLB_REG_GPIO_30_MODE
+#define GLB_REG_GPIO_30_MODE_POS          (30U)
+#define GLB_REG_GPIO_30_MODE_LEN          (2U)
+#define GLB_REG_GPIO_30_MODE_MSK          (((1U << GLB_REG_GPIO_30_MODE_LEN) - 1) << GLB_REG_GPIO_30_MODE_POS)
+#define GLB_REG_GPIO_30_MODE_UMSK         (~(((1U << GLB_REG_GPIO_30_MODE_LEN) - 1) << GLB_REG_GPIO_30_MODE_POS))
+
+/* 0x940 : gpio_cfg31 */
+#define GLB_GPIO_CFG31_OFFSET             (0x940)
+#define GLB_REG_GPIO_31_IE                GLB_REG_GPIO_31_IE
+#define GLB_REG_GPIO_31_IE_POS            (0U)
+#define GLB_REG_GPIO_31_IE_LEN            (1U)
+#define GLB_REG_GPIO_31_IE_MSK            (((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS)
+#define GLB_REG_GPIO_31_IE_UMSK           (~(((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS))
+#define GLB_REG_GPIO_31_SMT               GLB_REG_GPIO_31_SMT
+#define GLB_REG_GPIO_31_SMT_POS           (1U)
+#define GLB_REG_GPIO_31_SMT_LEN           (1U)
+#define GLB_REG_GPIO_31_SMT_MSK           (((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS)
+#define GLB_REG_GPIO_31_SMT_UMSK          (~(((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS))
+#define GLB_REG_GPIO_31_DRV               GLB_REG_GPIO_31_DRV
+#define GLB_REG_GPIO_31_DRV_POS           (2U)
+#define GLB_REG_GPIO_31_DRV_LEN           (2U)
+#define GLB_REG_GPIO_31_DRV_MSK           (((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS)
+#define GLB_REG_GPIO_31_DRV_UMSK          (~(((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS))
+#define GLB_REG_GPIO_31_PU                GLB_REG_GPIO_31_PU
+#define GLB_REG_GPIO_31_PU_POS            (4U)
+#define GLB_REG_GPIO_31_PU_LEN            (1U)
+#define GLB_REG_GPIO_31_PU_MSK            (((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS)
+#define GLB_REG_GPIO_31_PU_UMSK           (~(((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS))
+#define GLB_REG_GPIO_31_PD                GLB_REG_GPIO_31_PD
+#define GLB_REG_GPIO_31_PD_POS            (5U)
+#define GLB_REG_GPIO_31_PD_LEN            (1U)
+#define GLB_REG_GPIO_31_PD_MSK            (((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS)
+#define GLB_REG_GPIO_31_PD_UMSK           (~(((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS))
+#define GLB_REG_GPIO_31_OE                GLB_REG_GPIO_31_OE
+#define GLB_REG_GPIO_31_OE_POS            (6U)
+#define GLB_REG_GPIO_31_OE_LEN            (1U)
+#define GLB_REG_GPIO_31_OE_MSK            (((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS)
+#define GLB_REG_GPIO_31_OE_UMSK           (~(((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS))
+#define GLB_REG_GPIO_31_FUNC_SEL          GLB_REG_GPIO_31_FUNC_SEL
+#define GLB_REG_GPIO_31_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_31_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_31_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS)
+#define GLB_REG_GPIO_31_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS))
+#define GLB_REG_GPIO_31_INT_MODE_SET      GLB_REG_GPIO_31_INT_MODE_SET
+#define GLB_REG_GPIO_31_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_31_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_31_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_31_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_31_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_31_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_31_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_31_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_31_INT_CLR           GLB_REG_GPIO_31_INT_CLR
+#define GLB_REG_GPIO_31_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_31_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_31_INT_CLR_MSK       (((1U << GLB_REG_GPIO_31_INT_CLR_LEN) - 1) << GLB_REG_GPIO_31_INT_CLR_POS)
+#define GLB_REG_GPIO_31_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_31_INT_CLR_LEN) - 1) << GLB_REG_GPIO_31_INT_CLR_POS))
+#define GLB_GPIO_31_INT_STAT              GLB_GPIO_31_INT_STAT
+#define GLB_GPIO_31_INT_STAT_POS          (21U)
+#define GLB_GPIO_31_INT_STAT_LEN          (1U)
+#define GLB_GPIO_31_INT_STAT_MSK          (((1U << GLB_GPIO_31_INT_STAT_LEN) - 1) << GLB_GPIO_31_INT_STAT_POS)
+#define GLB_GPIO_31_INT_STAT_UMSK         (~(((1U << GLB_GPIO_31_INT_STAT_LEN) - 1) << GLB_GPIO_31_INT_STAT_POS))
+#define GLB_REG_GPIO_31_INT_MASK          GLB_REG_GPIO_31_INT_MASK
+#define GLB_REG_GPIO_31_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_31_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_31_INT_MASK_MSK      (((1U << GLB_REG_GPIO_31_INT_MASK_LEN) - 1) << GLB_REG_GPIO_31_INT_MASK_POS)
+#define GLB_REG_GPIO_31_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_31_INT_MASK_LEN) - 1) << GLB_REG_GPIO_31_INT_MASK_POS))
+#define GLB_REG_GPIO_31_O                 GLB_REG_GPIO_31_O
+#define GLB_REG_GPIO_31_O_POS             (24U)
+#define GLB_REG_GPIO_31_O_LEN             (1U)
+#define GLB_REG_GPIO_31_O_MSK             (((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS)
+#define GLB_REG_GPIO_31_O_UMSK            (~(((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS))
+#define GLB_REG_GPIO_31_SET               GLB_REG_GPIO_31_SET
+#define GLB_REG_GPIO_31_SET_POS           (25U)
+#define GLB_REG_GPIO_31_SET_LEN           (1U)
+#define GLB_REG_GPIO_31_SET_MSK           (((1U << GLB_REG_GPIO_31_SET_LEN) - 1) << GLB_REG_GPIO_31_SET_POS)
+#define GLB_REG_GPIO_31_SET_UMSK          (~(((1U << GLB_REG_GPIO_31_SET_LEN) - 1) << GLB_REG_GPIO_31_SET_POS))
+#define GLB_REG_GPIO_31_CLR               GLB_REG_GPIO_31_CLR
+#define GLB_REG_GPIO_31_CLR_POS           (26U)
+#define GLB_REG_GPIO_31_CLR_LEN           (1U)
+#define GLB_REG_GPIO_31_CLR_MSK           (((1U << GLB_REG_GPIO_31_CLR_LEN) - 1) << GLB_REG_GPIO_31_CLR_POS)
+#define GLB_REG_GPIO_31_CLR_UMSK          (~(((1U << GLB_REG_GPIO_31_CLR_LEN) - 1) << GLB_REG_GPIO_31_CLR_POS))
+#define GLB_REG_GPIO_31_I                 GLB_REG_GPIO_31_I
+#define GLB_REG_GPIO_31_I_POS             (28U)
+#define GLB_REG_GPIO_31_I_LEN             (1U)
+#define GLB_REG_GPIO_31_I_MSK             (((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS)
+#define GLB_REG_GPIO_31_I_UMSK            (~(((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS))
+#define GLB_REG_GPIO_31_MODE              GLB_REG_GPIO_31_MODE
+#define GLB_REG_GPIO_31_MODE_POS          (30U)
+#define GLB_REG_GPIO_31_MODE_LEN          (2U)
+#define GLB_REG_GPIO_31_MODE_MSK          (((1U << GLB_REG_GPIO_31_MODE_LEN) - 1) << GLB_REG_GPIO_31_MODE_POS)
+#define GLB_REG_GPIO_31_MODE_UMSK         (~(((1U << GLB_REG_GPIO_31_MODE_LEN) - 1) << GLB_REG_GPIO_31_MODE_POS))
+
+/* 0x944 : gpio_cfg32 */
+#define GLB_GPIO_CFG32_OFFSET             (0x944)
+#define GLB_REG_GPIO_32_IE                GLB_REG_GPIO_32_IE
+#define GLB_REG_GPIO_32_IE_POS            (0U)
+#define GLB_REG_GPIO_32_IE_LEN            (1U)
+#define GLB_REG_GPIO_32_IE_MSK            (((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS)
+#define GLB_REG_GPIO_32_IE_UMSK           (~(((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS))
+#define GLB_REG_GPIO_32_SMT               GLB_REG_GPIO_32_SMT
+#define GLB_REG_GPIO_32_SMT_POS           (1U)
+#define GLB_REG_GPIO_32_SMT_LEN           (1U)
+#define GLB_REG_GPIO_32_SMT_MSK           (((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS)
+#define GLB_REG_GPIO_32_SMT_UMSK          (~(((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS))
+#define GLB_REG_GPIO_32_DRV               GLB_REG_GPIO_32_DRV
+#define GLB_REG_GPIO_32_DRV_POS           (2U)
+#define GLB_REG_GPIO_32_DRV_LEN           (2U)
+#define GLB_REG_GPIO_32_DRV_MSK           (((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS)
+#define GLB_REG_GPIO_32_DRV_UMSK          (~(((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS))
+#define GLB_REG_GPIO_32_PU                GLB_REG_GPIO_32_PU
+#define GLB_REG_GPIO_32_PU_POS            (4U)
+#define GLB_REG_GPIO_32_PU_LEN            (1U)
+#define GLB_REG_GPIO_32_PU_MSK            (((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS)
+#define GLB_REG_GPIO_32_PU_UMSK           (~(((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS))
+#define GLB_REG_GPIO_32_PD                GLB_REG_GPIO_32_PD
+#define GLB_REG_GPIO_32_PD_POS            (5U)
+#define GLB_REG_GPIO_32_PD_LEN            (1U)
+#define GLB_REG_GPIO_32_PD_MSK            (((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS)
+#define GLB_REG_GPIO_32_PD_UMSK           (~(((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS))
+#define GLB_REG_GPIO_32_OE                GLB_REG_GPIO_32_OE
+#define GLB_REG_GPIO_32_OE_POS            (6U)
+#define GLB_REG_GPIO_32_OE_LEN            (1U)
+#define GLB_REG_GPIO_32_OE_MSK            (((1U << GLB_REG_GPIO_32_OE_LEN) - 1) << GLB_REG_GPIO_32_OE_POS)
+#define GLB_REG_GPIO_32_OE_UMSK           (~(((1U << GLB_REG_GPIO_32_OE_LEN) - 1) << GLB_REG_GPIO_32_OE_POS))
+#define GLB_REG_GPIO_32_FUNC_SEL          GLB_REG_GPIO_32_FUNC_SEL
+#define GLB_REG_GPIO_32_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_32_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_32_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_32_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_32_FUNC_SEL_POS)
+#define GLB_REG_GPIO_32_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_32_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_32_FUNC_SEL_POS))
+#define GLB_REG_GPIO_32_INT_MODE_SET      GLB_REG_GPIO_32_INT_MODE_SET
+#define GLB_REG_GPIO_32_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_32_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_32_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_32_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_32_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_32_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_32_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_32_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_32_INT_CLR           GLB_REG_GPIO_32_INT_CLR
+#define GLB_REG_GPIO_32_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_32_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_32_INT_CLR_MSK       (((1U << GLB_REG_GPIO_32_INT_CLR_LEN) - 1) << GLB_REG_GPIO_32_INT_CLR_POS)
+#define GLB_REG_GPIO_32_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_32_INT_CLR_LEN) - 1) << GLB_REG_GPIO_32_INT_CLR_POS))
+#define GLB_GPIO_32_INT_STAT              GLB_GPIO_32_INT_STAT
+#define GLB_GPIO_32_INT_STAT_POS          (21U)
+#define GLB_GPIO_32_INT_STAT_LEN          (1U)
+#define GLB_GPIO_32_INT_STAT_MSK          (((1U << GLB_GPIO_32_INT_STAT_LEN) - 1) << GLB_GPIO_32_INT_STAT_POS)
+#define GLB_GPIO_32_INT_STAT_UMSK         (~(((1U << GLB_GPIO_32_INT_STAT_LEN) - 1) << GLB_GPIO_32_INT_STAT_POS))
+#define GLB_REG_GPIO_32_INT_MASK          GLB_REG_GPIO_32_INT_MASK
+#define GLB_REG_GPIO_32_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_32_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_32_INT_MASK_MSK      (((1U << GLB_REG_GPIO_32_INT_MASK_LEN) - 1) << GLB_REG_GPIO_32_INT_MASK_POS)
+#define GLB_REG_GPIO_32_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_32_INT_MASK_LEN) - 1) << GLB_REG_GPIO_32_INT_MASK_POS))
+#define GLB_REG_GPIO_32_O                 GLB_REG_GPIO_32_O
+#define GLB_REG_GPIO_32_O_POS             (24U)
+#define GLB_REG_GPIO_32_O_LEN             (1U)
+#define GLB_REG_GPIO_32_O_MSK             (((1U << GLB_REG_GPIO_32_O_LEN) - 1) << GLB_REG_GPIO_32_O_POS)
+#define GLB_REG_GPIO_32_O_UMSK            (~(((1U << GLB_REG_GPIO_32_O_LEN) - 1) << GLB_REG_GPIO_32_O_POS))
+#define GLB_REG_GPIO_32_SET               GLB_REG_GPIO_32_SET
+#define GLB_REG_GPIO_32_SET_POS           (25U)
+#define GLB_REG_GPIO_32_SET_LEN           (1U)
+#define GLB_REG_GPIO_32_SET_MSK           (((1U << GLB_REG_GPIO_32_SET_LEN) - 1) << GLB_REG_GPIO_32_SET_POS)
+#define GLB_REG_GPIO_32_SET_UMSK          (~(((1U << GLB_REG_GPIO_32_SET_LEN) - 1) << GLB_REG_GPIO_32_SET_POS))
+#define GLB_REG_GPIO_32_CLR               GLB_REG_GPIO_32_CLR
+#define GLB_REG_GPIO_32_CLR_POS           (26U)
+#define GLB_REG_GPIO_32_CLR_LEN           (1U)
+#define GLB_REG_GPIO_32_CLR_MSK           (((1U << GLB_REG_GPIO_32_CLR_LEN) - 1) << GLB_REG_GPIO_32_CLR_POS)
+#define GLB_REG_GPIO_32_CLR_UMSK          (~(((1U << GLB_REG_GPIO_32_CLR_LEN) - 1) << GLB_REG_GPIO_32_CLR_POS))
+#define GLB_REG_GPIO_32_I                 GLB_REG_GPIO_32_I
+#define GLB_REG_GPIO_32_I_POS             (28U)
+#define GLB_REG_GPIO_32_I_LEN             (1U)
+#define GLB_REG_GPIO_32_I_MSK             (((1U << GLB_REG_GPIO_32_I_LEN) - 1) << GLB_REG_GPIO_32_I_POS)
+#define GLB_REG_GPIO_32_I_UMSK            (~(((1U << GLB_REG_GPIO_32_I_LEN) - 1) << GLB_REG_GPIO_32_I_POS))
+#define GLB_REG_GPIO_32_MODE              GLB_REG_GPIO_32_MODE
+#define GLB_REG_GPIO_32_MODE_POS          (30U)
+#define GLB_REG_GPIO_32_MODE_LEN          (2U)
+#define GLB_REG_GPIO_32_MODE_MSK          (((1U << GLB_REG_GPIO_32_MODE_LEN) - 1) << GLB_REG_GPIO_32_MODE_POS)
+#define GLB_REG_GPIO_32_MODE_UMSK         (~(((1U << GLB_REG_GPIO_32_MODE_LEN) - 1) << GLB_REG_GPIO_32_MODE_POS))
+
+/* 0x948 : gpio_cfg33 */
+#define GLB_GPIO_CFG33_OFFSET             (0x948)
+#define GLB_REG_GPIO_33_IE                GLB_REG_GPIO_33_IE
+#define GLB_REG_GPIO_33_IE_POS            (0U)
+#define GLB_REG_GPIO_33_IE_LEN            (1U)
+#define GLB_REG_GPIO_33_IE_MSK            (((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS)
+#define GLB_REG_GPIO_33_IE_UMSK           (~(((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS))
+#define GLB_REG_GPIO_33_SMT               GLB_REG_GPIO_33_SMT
+#define GLB_REG_GPIO_33_SMT_POS           (1U)
+#define GLB_REG_GPIO_33_SMT_LEN           (1U)
+#define GLB_REG_GPIO_33_SMT_MSK           (((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS)
+#define GLB_REG_GPIO_33_SMT_UMSK          (~(((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS))
+#define GLB_REG_GPIO_33_DRV               GLB_REG_GPIO_33_DRV
+#define GLB_REG_GPIO_33_DRV_POS           (2U)
+#define GLB_REG_GPIO_33_DRV_LEN           (2U)
+#define GLB_REG_GPIO_33_DRV_MSK           (((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS)
+#define GLB_REG_GPIO_33_DRV_UMSK          (~(((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS))
+#define GLB_REG_GPIO_33_PU                GLB_REG_GPIO_33_PU
+#define GLB_REG_GPIO_33_PU_POS            (4U)
+#define GLB_REG_GPIO_33_PU_LEN            (1U)
+#define GLB_REG_GPIO_33_PU_MSK            (((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS)
+#define GLB_REG_GPIO_33_PU_UMSK           (~(((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS))
+#define GLB_REG_GPIO_33_PD                GLB_REG_GPIO_33_PD
+#define GLB_REG_GPIO_33_PD_POS            (5U)
+#define GLB_REG_GPIO_33_PD_LEN            (1U)
+#define GLB_REG_GPIO_33_PD_MSK            (((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS)
+#define GLB_REG_GPIO_33_PD_UMSK           (~(((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS))
+#define GLB_REG_GPIO_33_OE                GLB_REG_GPIO_33_OE
+#define GLB_REG_GPIO_33_OE_POS            (6U)
+#define GLB_REG_GPIO_33_OE_LEN            (1U)
+#define GLB_REG_GPIO_33_OE_MSK            (((1U << GLB_REG_GPIO_33_OE_LEN) - 1) << GLB_REG_GPIO_33_OE_POS)
+#define GLB_REG_GPIO_33_OE_UMSK           (~(((1U << GLB_REG_GPIO_33_OE_LEN) - 1) << GLB_REG_GPIO_33_OE_POS))
+#define GLB_REG_GPIO_33_FUNC_SEL          GLB_REG_GPIO_33_FUNC_SEL
+#define GLB_REG_GPIO_33_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_33_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_33_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_33_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_33_FUNC_SEL_POS)
+#define GLB_REG_GPIO_33_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_33_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_33_FUNC_SEL_POS))
+#define GLB_REG_GPIO_33_INT_MODE_SET      GLB_REG_GPIO_33_INT_MODE_SET
+#define GLB_REG_GPIO_33_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_33_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_33_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_33_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_33_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_33_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_33_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_33_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_33_INT_CLR           GLB_REG_GPIO_33_INT_CLR
+#define GLB_REG_GPIO_33_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_33_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_33_INT_CLR_MSK       (((1U << GLB_REG_GPIO_33_INT_CLR_LEN) - 1) << GLB_REG_GPIO_33_INT_CLR_POS)
+#define GLB_REG_GPIO_33_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_33_INT_CLR_LEN) - 1) << GLB_REG_GPIO_33_INT_CLR_POS))
+#define GLB_GPIO_33_INT_STAT              GLB_GPIO_33_INT_STAT
+#define GLB_GPIO_33_INT_STAT_POS          (21U)
+#define GLB_GPIO_33_INT_STAT_LEN          (1U)
+#define GLB_GPIO_33_INT_STAT_MSK          (((1U << GLB_GPIO_33_INT_STAT_LEN) - 1) << GLB_GPIO_33_INT_STAT_POS)
+#define GLB_GPIO_33_INT_STAT_UMSK         (~(((1U << GLB_GPIO_33_INT_STAT_LEN) - 1) << GLB_GPIO_33_INT_STAT_POS))
+#define GLB_REG_GPIO_33_INT_MASK          GLB_REG_GPIO_33_INT_MASK
+#define GLB_REG_GPIO_33_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_33_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_33_INT_MASK_MSK      (((1U << GLB_REG_GPIO_33_INT_MASK_LEN) - 1) << GLB_REG_GPIO_33_INT_MASK_POS)
+#define GLB_REG_GPIO_33_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_33_INT_MASK_LEN) - 1) << GLB_REG_GPIO_33_INT_MASK_POS))
+#define GLB_REG_GPIO_33_O                 GLB_REG_GPIO_33_O
+#define GLB_REG_GPIO_33_O_POS             (24U)
+#define GLB_REG_GPIO_33_O_LEN             (1U)
+#define GLB_REG_GPIO_33_O_MSK             (((1U << GLB_REG_GPIO_33_O_LEN) - 1) << GLB_REG_GPIO_33_O_POS)
+#define GLB_REG_GPIO_33_O_UMSK            (~(((1U << GLB_REG_GPIO_33_O_LEN) - 1) << GLB_REG_GPIO_33_O_POS))
+#define GLB_REG_GPIO_33_SET               GLB_REG_GPIO_33_SET
+#define GLB_REG_GPIO_33_SET_POS           (25U)
+#define GLB_REG_GPIO_33_SET_LEN           (1U)
+#define GLB_REG_GPIO_33_SET_MSK           (((1U << GLB_REG_GPIO_33_SET_LEN) - 1) << GLB_REG_GPIO_33_SET_POS)
+#define GLB_REG_GPIO_33_SET_UMSK          (~(((1U << GLB_REG_GPIO_33_SET_LEN) - 1) << GLB_REG_GPIO_33_SET_POS))
+#define GLB_REG_GPIO_33_CLR               GLB_REG_GPIO_33_CLR
+#define GLB_REG_GPIO_33_CLR_POS           (26U)
+#define GLB_REG_GPIO_33_CLR_LEN           (1U)
+#define GLB_REG_GPIO_33_CLR_MSK           (((1U << GLB_REG_GPIO_33_CLR_LEN) - 1) << GLB_REG_GPIO_33_CLR_POS)
+#define GLB_REG_GPIO_33_CLR_UMSK          (~(((1U << GLB_REG_GPIO_33_CLR_LEN) - 1) << GLB_REG_GPIO_33_CLR_POS))
+#define GLB_REG_GPIO_33_I                 GLB_REG_GPIO_33_I
+#define GLB_REG_GPIO_33_I_POS             (28U)
+#define GLB_REG_GPIO_33_I_LEN             (1U)
+#define GLB_REG_GPIO_33_I_MSK             (((1U << GLB_REG_GPIO_33_I_LEN) - 1) << GLB_REG_GPIO_33_I_POS)
+#define GLB_REG_GPIO_33_I_UMSK            (~(((1U << GLB_REG_GPIO_33_I_LEN) - 1) << GLB_REG_GPIO_33_I_POS))
+#define GLB_REG_GPIO_33_MODE              GLB_REG_GPIO_33_MODE
+#define GLB_REG_GPIO_33_MODE_POS          (30U)
+#define GLB_REG_GPIO_33_MODE_LEN          (2U)
+#define GLB_REG_GPIO_33_MODE_MSK          (((1U << GLB_REG_GPIO_33_MODE_LEN) - 1) << GLB_REG_GPIO_33_MODE_POS)
+#define GLB_REG_GPIO_33_MODE_UMSK         (~(((1U << GLB_REG_GPIO_33_MODE_LEN) - 1) << GLB_REG_GPIO_33_MODE_POS))
+
+/* 0x94C : gpio_cfg34 */
+#define GLB_GPIO_CFG34_OFFSET             (0x94C)
+#define GLB_REG_GPIO_34_IE                GLB_REG_GPIO_34_IE
+#define GLB_REG_GPIO_34_IE_POS            (0U)
+#define GLB_REG_GPIO_34_IE_LEN            (1U)
+#define GLB_REG_GPIO_34_IE_MSK            (((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS)
+#define GLB_REG_GPIO_34_IE_UMSK           (~(((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS))
+#define GLB_REG_GPIO_34_SMT               GLB_REG_GPIO_34_SMT
+#define GLB_REG_GPIO_34_SMT_POS           (1U)
+#define GLB_REG_GPIO_34_SMT_LEN           (1U)
+#define GLB_REG_GPIO_34_SMT_MSK           (((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS)
+#define GLB_REG_GPIO_34_SMT_UMSK          (~(((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS))
+#define GLB_REG_GPIO_34_DRV               GLB_REG_GPIO_34_DRV
+#define GLB_REG_GPIO_34_DRV_POS           (2U)
+#define GLB_REG_GPIO_34_DRV_LEN           (2U)
+#define GLB_REG_GPIO_34_DRV_MSK           (((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS)
+#define GLB_REG_GPIO_34_DRV_UMSK          (~(((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS))
+#define GLB_REG_GPIO_34_PU                GLB_REG_GPIO_34_PU
+#define GLB_REG_GPIO_34_PU_POS            (4U)
+#define GLB_REG_GPIO_34_PU_LEN            (1U)
+#define GLB_REG_GPIO_34_PU_MSK            (((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS)
+#define GLB_REG_GPIO_34_PU_UMSK           (~(((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS))
+#define GLB_REG_GPIO_34_PD                GLB_REG_GPIO_34_PD
+#define GLB_REG_GPIO_34_PD_POS            (5U)
+#define GLB_REG_GPIO_34_PD_LEN            (1U)
+#define GLB_REG_GPIO_34_PD_MSK            (((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS)
+#define GLB_REG_GPIO_34_PD_UMSK           (~(((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS))
+#define GLB_REG_GPIO_34_OE                GLB_REG_GPIO_34_OE
+#define GLB_REG_GPIO_34_OE_POS            (6U)
+#define GLB_REG_GPIO_34_OE_LEN            (1U)
+#define GLB_REG_GPIO_34_OE_MSK            (((1U << GLB_REG_GPIO_34_OE_LEN) - 1) << GLB_REG_GPIO_34_OE_POS)
+#define GLB_REG_GPIO_34_OE_UMSK           (~(((1U << GLB_REG_GPIO_34_OE_LEN) - 1) << GLB_REG_GPIO_34_OE_POS))
+#define GLB_REG_GPIO_34_FUNC_SEL          GLB_REG_GPIO_34_FUNC_SEL
+#define GLB_REG_GPIO_34_FUNC_SEL_POS      (8U)
+#define GLB_REG_GPIO_34_FUNC_SEL_LEN      (5U)
+#define GLB_REG_GPIO_34_FUNC_SEL_MSK      (((1U << GLB_REG_GPIO_34_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_34_FUNC_SEL_POS)
+#define GLB_REG_GPIO_34_FUNC_SEL_UMSK     (~(((1U << GLB_REG_GPIO_34_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_34_FUNC_SEL_POS))
+#define GLB_REG_GPIO_34_INT_MODE_SET      GLB_REG_GPIO_34_INT_MODE_SET
+#define GLB_REG_GPIO_34_INT_MODE_SET_POS  (16U)
+#define GLB_REG_GPIO_34_INT_MODE_SET_LEN  (4U)
+#define GLB_REG_GPIO_34_INT_MODE_SET_MSK  (((1U << GLB_REG_GPIO_34_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_34_INT_MODE_SET_POS)
+#define GLB_REG_GPIO_34_INT_MODE_SET_UMSK (~(((1U << GLB_REG_GPIO_34_INT_MODE_SET_LEN) - 1) << GLB_REG_GPIO_34_INT_MODE_SET_POS))
+#define GLB_REG_GPIO_34_INT_CLR           GLB_REG_GPIO_34_INT_CLR
+#define GLB_REG_GPIO_34_INT_CLR_POS       (20U)
+#define GLB_REG_GPIO_34_INT_CLR_LEN       (1U)
+#define GLB_REG_GPIO_34_INT_CLR_MSK       (((1U << GLB_REG_GPIO_34_INT_CLR_LEN) - 1) << GLB_REG_GPIO_34_INT_CLR_POS)
+#define GLB_REG_GPIO_34_INT_CLR_UMSK      (~(((1U << GLB_REG_GPIO_34_INT_CLR_LEN) - 1) << GLB_REG_GPIO_34_INT_CLR_POS))
+#define GLB_GPIO_34_INT_STAT              GLB_GPIO_34_INT_STAT
+#define GLB_GPIO_34_INT_STAT_POS          (21U)
+#define GLB_GPIO_34_INT_STAT_LEN          (1U)
+#define GLB_GPIO_34_INT_STAT_MSK          (((1U << GLB_GPIO_34_INT_STAT_LEN) - 1) << GLB_GPIO_34_INT_STAT_POS)
+#define GLB_GPIO_34_INT_STAT_UMSK         (~(((1U << GLB_GPIO_34_INT_STAT_LEN) - 1) << GLB_GPIO_34_INT_STAT_POS))
+#define GLB_REG_GPIO_34_INT_MASK          GLB_REG_GPIO_34_INT_MASK
+#define GLB_REG_GPIO_34_INT_MASK_POS      (22U)
+#define GLB_REG_GPIO_34_INT_MASK_LEN      (1U)
+#define GLB_REG_GPIO_34_INT_MASK_MSK      (((1U << GLB_REG_GPIO_34_INT_MASK_LEN) - 1) << GLB_REG_GPIO_34_INT_MASK_POS)
+#define GLB_REG_GPIO_34_INT_MASK_UMSK     (~(((1U << GLB_REG_GPIO_34_INT_MASK_LEN) - 1) << GLB_REG_GPIO_34_INT_MASK_POS))
+#define GLB_REG_GPIO_34_O                 GLB_REG_GPIO_34_O
+#define GLB_REG_GPIO_34_O_POS             (24U)
+#define GLB_REG_GPIO_34_O_LEN             (1U)
+#define GLB_REG_GPIO_34_O_MSK             (((1U << GLB_REG_GPIO_34_O_LEN) - 1) << GLB_REG_GPIO_34_O_POS)
+#define GLB_REG_GPIO_34_O_UMSK            (~(((1U << GLB_REG_GPIO_34_O_LEN) - 1) << GLB_REG_GPIO_34_O_POS))
+#define GLB_REG_GPIO_34_SET               GLB_REG_GPIO_34_SET
+#define GLB_REG_GPIO_34_SET_POS           (25U)
+#define GLB_REG_GPIO_34_SET_LEN           (1U)
+#define GLB_REG_GPIO_34_SET_MSK           (((1U << GLB_REG_GPIO_34_SET_LEN) - 1) << GLB_REG_GPIO_34_SET_POS)
+#define GLB_REG_GPIO_34_SET_UMSK          (~(((1U << GLB_REG_GPIO_34_SET_LEN) - 1) << GLB_REG_GPIO_34_SET_POS))
+#define GLB_REG_GPIO_34_CLR               GLB_REG_GPIO_34_CLR
+#define GLB_REG_GPIO_34_CLR_POS           (26U)
+#define GLB_REG_GPIO_34_CLR_LEN           (1U)
+#define GLB_REG_GPIO_34_CLR_MSK           (((1U << GLB_REG_GPIO_34_CLR_LEN) - 1) << GLB_REG_GPIO_34_CLR_POS)
+#define GLB_REG_GPIO_34_CLR_UMSK          (~(((1U << GLB_REG_GPIO_34_CLR_LEN) - 1) << GLB_REG_GPIO_34_CLR_POS))
+#define GLB_REG_GPIO_34_I                 GLB_REG_GPIO_34_I
+#define GLB_REG_GPIO_34_I_POS             (28U)
+#define GLB_REG_GPIO_34_I_LEN             (1U)
+#define GLB_REG_GPIO_34_I_MSK             (((1U << GLB_REG_GPIO_34_I_LEN) - 1) << GLB_REG_GPIO_34_I_POS)
+#define GLB_REG_GPIO_34_I_UMSK            (~(((1U << GLB_REG_GPIO_34_I_LEN) - 1) << GLB_REG_GPIO_34_I_POS))
+#define GLB_REG_GPIO_34_MODE              GLB_REG_GPIO_34_MODE
+#define GLB_REG_GPIO_34_MODE_POS          (30U)
+#define GLB_REG_GPIO_34_MODE_LEN          (2U)
+#define GLB_REG_GPIO_34_MODE_MSK          (((1U << GLB_REG_GPIO_34_MODE_LEN) - 1) << GLB_REG_GPIO_34_MODE_POS)
+#define GLB_REG_GPIO_34_MODE_UMSK         (~(((1U << GLB_REG_GPIO_34_MODE_LEN) - 1) << GLB_REG_GPIO_34_MODE_POS))
+
+/* 0x950 : gpio_cfg35 */
+#define GLB_GPIO_CFG35_OFFSET    (0x950)
+#define GLB_REG_GPIO_35_IE       GLB_REG_GPIO_35_IE
+#define GLB_REG_GPIO_35_IE_POS   (0U)
+#define GLB_REG_GPIO_35_IE_LEN   (1U)
+#define GLB_REG_GPIO_35_IE_MSK   (((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS)
+#define GLB_REG_GPIO_35_IE_UMSK  (~(((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS))
+#define GLB_REG_GPIO_35_SMT      GLB_REG_GPIO_35_SMT
+#define GLB_REG_GPIO_35_SMT_POS  (1U)
+#define GLB_REG_GPIO_35_SMT_LEN  (1U)
+#define GLB_REG_GPIO_35_SMT_MSK  (((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS)
+#define GLB_REG_GPIO_35_SMT_UMSK (~(((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS))
+#define GLB_REG_GPIO_35_DRV      GLB_REG_GPIO_35_DRV
+#define GLB_REG_GPIO_35_DRV_POS  (2U)
+#define GLB_REG_GPIO_35_DRV_LEN  (2U)
+#define GLB_REG_GPIO_35_DRV_MSK  (((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS)
+#define GLB_REG_GPIO_35_DRV_UMSK (~(((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS))
+#define GLB_REG_GPIO_35_PU       GLB_REG_GPIO_35_PU
+#define GLB_REG_GPIO_35_PU_POS   (4U)
+#define GLB_REG_GPIO_35_PU_LEN   (1U)
+#define GLB_REG_GPIO_35_PU_MSK   (((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS)
+#define GLB_REG_GPIO_35_PU_UMSK  (~(((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS))
+#define GLB_REG_GPIO_35_PD       GLB_REG_GPIO_35_PD
+#define GLB_REG_GPIO_35_PD_POS   (5U)
+#define GLB_REG_GPIO_35_PD_LEN   (1U)
+#define GLB_REG_GPIO_35_PD_MSK   (((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS)
+#define GLB_REG_GPIO_35_PD_UMSK  (~(((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS))
+
+/* 0x954 : gpio_cfg36 */
+#define GLB_GPIO_CFG36_OFFSET    (0x954)
+#define GLB_REG_GPIO_36_IE       GLB_REG_GPIO_36_IE
+#define GLB_REG_GPIO_36_IE_POS   (0U)
+#define GLB_REG_GPIO_36_IE_LEN   (1U)
+#define GLB_REG_GPIO_36_IE_MSK   (((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS)
+#define GLB_REG_GPIO_36_IE_UMSK  (~(((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS))
+#define GLB_REG_GPIO_36_SMT      GLB_REG_GPIO_36_SMT
+#define GLB_REG_GPIO_36_SMT_POS  (1U)
+#define GLB_REG_GPIO_36_SMT_LEN  (1U)
+#define GLB_REG_GPIO_36_SMT_MSK  (((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS)
+#define GLB_REG_GPIO_36_SMT_UMSK (~(((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS))
+#define GLB_REG_GPIO_36_DRV      GLB_REG_GPIO_36_DRV
+#define GLB_REG_GPIO_36_DRV_POS  (2U)
+#define GLB_REG_GPIO_36_DRV_LEN  (2U)
+#define GLB_REG_GPIO_36_DRV_MSK  (((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS)
+#define GLB_REG_GPIO_36_DRV_UMSK (~(((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS))
+#define GLB_REG_GPIO_36_PU       GLB_REG_GPIO_36_PU
+#define GLB_REG_GPIO_36_PU_POS   (4U)
+#define GLB_REG_GPIO_36_PU_LEN   (1U)
+#define GLB_REG_GPIO_36_PU_MSK   (((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS)
+#define GLB_REG_GPIO_36_PU_UMSK  (~(((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS))
+#define GLB_REG_GPIO_36_PD       GLB_REG_GPIO_36_PD
+#define GLB_REG_GPIO_36_PD_POS   (5U)
+#define GLB_REG_GPIO_36_PD_LEN   (1U)
+#define GLB_REG_GPIO_36_PD_MSK   (((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS)
+#define GLB_REG_GPIO_36_PD_UMSK  (~(((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS))
+
+/* 0x958 : gpio_cfg37 */
+#define GLB_GPIO_CFG37_OFFSET    (0x958)
+#define GLB_REG_GPIO_37_IE       GLB_REG_GPIO_37_IE
+#define GLB_REG_GPIO_37_IE_POS   (0U)
+#define GLB_REG_GPIO_37_IE_LEN   (1U)
+#define GLB_REG_GPIO_37_IE_MSK   (((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS)
+#define GLB_REG_GPIO_37_IE_UMSK  (~(((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS))
+#define GLB_REG_GPIO_37_SMT      GLB_REG_GPIO_37_SMT
+#define GLB_REG_GPIO_37_SMT_POS  (1U)
+#define GLB_REG_GPIO_37_SMT_LEN  (1U)
+#define GLB_REG_GPIO_37_SMT_MSK  (((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS)
+#define GLB_REG_GPIO_37_SMT_UMSK (~(((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS))
+#define GLB_REG_GPIO_37_DRV      GLB_REG_GPIO_37_DRV
+#define GLB_REG_GPIO_37_DRV_POS  (2U)
+#define GLB_REG_GPIO_37_DRV_LEN  (2U)
+#define GLB_REG_GPIO_37_DRV_MSK  (((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS)
+#define GLB_REG_GPIO_37_DRV_UMSK (~(((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS))
+#define GLB_REG_GPIO_37_PU       GLB_REG_GPIO_37_PU
+#define GLB_REG_GPIO_37_PU_POS   (4U)
+#define GLB_REG_GPIO_37_PU_LEN   (1U)
+#define GLB_REG_GPIO_37_PU_MSK   (((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS)
+#define GLB_REG_GPIO_37_PU_UMSK  (~(((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS))
+#define GLB_REG_GPIO_37_PD       GLB_REG_GPIO_37_PD
+#define GLB_REG_GPIO_37_PD_POS   (5U)
+#define GLB_REG_GPIO_37_PD_LEN   (1U)
+#define GLB_REG_GPIO_37_PD_MSK   (((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS)
+#define GLB_REG_GPIO_37_PD_UMSK  (~(((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS))
+
+/* 0x95C : gpio_cfg38 */
+#define GLB_GPIO_CFG38_OFFSET    (0x95C)
+#define GLB_REG_GPIO_38_IE       GLB_REG_GPIO_38_IE
+#define GLB_REG_GPIO_38_IE_POS   (0U)
+#define GLB_REG_GPIO_38_IE_LEN   (1U)
+#define GLB_REG_GPIO_38_IE_MSK   (((1U << GLB_REG_GPIO_38_IE_LEN) - 1) << GLB_REG_GPIO_38_IE_POS)
+#define GLB_REG_GPIO_38_IE_UMSK  (~(((1U << GLB_REG_GPIO_38_IE_LEN) - 1) << GLB_REG_GPIO_38_IE_POS))
+#define GLB_REG_GPIO_38_SMT      GLB_REG_GPIO_38_SMT
+#define GLB_REG_GPIO_38_SMT_POS  (1U)
+#define GLB_REG_GPIO_38_SMT_LEN  (1U)
+#define GLB_REG_GPIO_38_SMT_MSK  (((1U << GLB_REG_GPIO_38_SMT_LEN) - 1) << GLB_REG_GPIO_38_SMT_POS)
+#define GLB_REG_GPIO_38_SMT_UMSK (~(((1U << GLB_REG_GPIO_38_SMT_LEN) - 1) << GLB_REG_GPIO_38_SMT_POS))
+#define GLB_REG_GPIO_38_DRV      GLB_REG_GPIO_38_DRV
+#define GLB_REG_GPIO_38_DRV_POS  (2U)
+#define GLB_REG_GPIO_38_DRV_LEN  (2U)
+#define GLB_REG_GPIO_38_DRV_MSK  (((1U << GLB_REG_GPIO_38_DRV_LEN) - 1) << GLB_REG_GPIO_38_DRV_POS)
+#define GLB_REG_GPIO_38_DRV_UMSK (~(((1U << GLB_REG_GPIO_38_DRV_LEN) - 1) << GLB_REG_GPIO_38_DRV_POS))
+#define GLB_REG_GPIO_38_PU       GLB_REG_GPIO_38_PU
+#define GLB_REG_GPIO_38_PU_POS   (4U)
+#define GLB_REG_GPIO_38_PU_LEN   (1U)
+#define GLB_REG_GPIO_38_PU_MSK   (((1U << GLB_REG_GPIO_38_PU_LEN) - 1) << GLB_REG_GPIO_38_PU_POS)
+#define GLB_REG_GPIO_38_PU_UMSK  (~(((1U << GLB_REG_GPIO_38_PU_LEN) - 1) << GLB_REG_GPIO_38_PU_POS))
+#define GLB_REG_GPIO_38_PD       GLB_REG_GPIO_38_PD
+#define GLB_REG_GPIO_38_PD_POS   (5U)
+#define GLB_REG_GPIO_38_PD_LEN   (1U)
+#define GLB_REG_GPIO_38_PD_MSK   (((1U << GLB_REG_GPIO_38_PD_LEN) - 1) << GLB_REG_GPIO_38_PD_POS)
+#define GLB_REG_GPIO_38_PD_UMSK  (~(((1U << GLB_REG_GPIO_38_PD_LEN) - 1) << GLB_REG_GPIO_38_PD_POS))
+
+/* 0x960 : gpio_cfg39 */
+#define GLB_GPIO_CFG39_OFFSET    (0x960)
+#define GLB_REG_GPIO_39_IE       GLB_REG_GPIO_39_IE
+#define GLB_REG_GPIO_39_IE_POS   (0U)
+#define GLB_REG_GPIO_39_IE_LEN   (1U)
+#define GLB_REG_GPIO_39_IE_MSK   (((1U << GLB_REG_GPIO_39_IE_LEN) - 1) << GLB_REG_GPIO_39_IE_POS)
+#define GLB_REG_GPIO_39_IE_UMSK  (~(((1U << GLB_REG_GPIO_39_IE_LEN) - 1) << GLB_REG_GPIO_39_IE_POS))
+#define GLB_REG_GPIO_39_SMT      GLB_REG_GPIO_39_SMT
+#define GLB_REG_GPIO_39_SMT_POS  (1U)
+#define GLB_REG_GPIO_39_SMT_LEN  (1U)
+#define GLB_REG_GPIO_39_SMT_MSK  (((1U << GLB_REG_GPIO_39_SMT_LEN) - 1) << GLB_REG_GPIO_39_SMT_POS)
+#define GLB_REG_GPIO_39_SMT_UMSK (~(((1U << GLB_REG_GPIO_39_SMT_LEN) - 1) << GLB_REG_GPIO_39_SMT_POS))
+#define GLB_REG_GPIO_39_DRV      GLB_REG_GPIO_39_DRV
+#define GLB_REG_GPIO_39_DRV_POS  (2U)
+#define GLB_REG_GPIO_39_DRV_LEN  (2U)
+#define GLB_REG_GPIO_39_DRV_MSK  (((1U << GLB_REG_GPIO_39_DRV_LEN) - 1) << GLB_REG_GPIO_39_DRV_POS)
+#define GLB_REG_GPIO_39_DRV_UMSK (~(((1U << GLB_REG_GPIO_39_DRV_LEN) - 1) << GLB_REG_GPIO_39_DRV_POS))
+#define GLB_REG_GPIO_39_PU       GLB_REG_GPIO_39_PU
+#define GLB_REG_GPIO_39_PU_POS   (4U)
+#define GLB_REG_GPIO_39_PU_LEN   (1U)
+#define GLB_REG_GPIO_39_PU_MSK   (((1U << GLB_REG_GPIO_39_PU_LEN) - 1) << GLB_REG_GPIO_39_PU_POS)
+#define GLB_REG_GPIO_39_PU_UMSK  (~(((1U << GLB_REG_GPIO_39_PU_LEN) - 1) << GLB_REG_GPIO_39_PU_POS))
+#define GLB_REG_GPIO_39_PD       GLB_REG_GPIO_39_PD
+#define GLB_REG_GPIO_39_PD_POS   (5U)
+#define GLB_REG_GPIO_39_PD_LEN   (1U)
+#define GLB_REG_GPIO_39_PD_MSK   (((1U << GLB_REG_GPIO_39_PD_LEN) - 1) << GLB_REG_GPIO_39_PD_POS)
+#define GLB_REG_GPIO_39_PD_UMSK  (~(((1U << GLB_REG_GPIO_39_PD_LEN) - 1) << GLB_REG_GPIO_39_PD_POS))
+
+/* 0x964 : gpio_cfg40 */
+#define GLB_GPIO_CFG40_OFFSET    (0x964)
+#define GLB_REG_GPIO_40_IE       GLB_REG_GPIO_40_IE
+#define GLB_REG_GPIO_40_IE_POS   (0U)
+#define GLB_REG_GPIO_40_IE_LEN   (1U)
+#define GLB_REG_GPIO_40_IE_MSK   (((1U << GLB_REG_GPIO_40_IE_LEN) - 1) << GLB_REG_GPIO_40_IE_POS)
+#define GLB_REG_GPIO_40_IE_UMSK  (~(((1U << GLB_REG_GPIO_40_IE_LEN) - 1) << GLB_REG_GPIO_40_IE_POS))
+#define GLB_REG_GPIO_40_SMT      GLB_REG_GPIO_40_SMT
+#define GLB_REG_GPIO_40_SMT_POS  (1U)
+#define GLB_REG_GPIO_40_SMT_LEN  (1U)
+#define GLB_REG_GPIO_40_SMT_MSK  (((1U << GLB_REG_GPIO_40_SMT_LEN) - 1) << GLB_REG_GPIO_40_SMT_POS)
+#define GLB_REG_GPIO_40_SMT_UMSK (~(((1U << GLB_REG_GPIO_40_SMT_LEN) - 1) << GLB_REG_GPIO_40_SMT_POS))
+#define GLB_REG_GPIO_40_DRV      GLB_REG_GPIO_40_DRV
+#define GLB_REG_GPIO_40_DRV_POS  (2U)
+#define GLB_REG_GPIO_40_DRV_LEN  (2U)
+#define GLB_REG_GPIO_40_DRV_MSK  (((1U << GLB_REG_GPIO_40_DRV_LEN) - 1) << GLB_REG_GPIO_40_DRV_POS)
+#define GLB_REG_GPIO_40_DRV_UMSK (~(((1U << GLB_REG_GPIO_40_DRV_LEN) - 1) << GLB_REG_GPIO_40_DRV_POS))
+#define GLB_REG_GPIO_40_PU       GLB_REG_GPIO_40_PU
+#define GLB_REG_GPIO_40_PU_POS   (4U)
+#define GLB_REG_GPIO_40_PU_LEN   (1U)
+#define GLB_REG_GPIO_40_PU_MSK   (((1U << GLB_REG_GPIO_40_PU_LEN) - 1) << GLB_REG_GPIO_40_PU_POS)
+#define GLB_REG_GPIO_40_PU_UMSK  (~(((1U << GLB_REG_GPIO_40_PU_LEN) - 1) << GLB_REG_GPIO_40_PU_POS))
+#define GLB_REG_GPIO_40_PD       GLB_REG_GPIO_40_PD
+#define GLB_REG_GPIO_40_PD_POS   (5U)
+#define GLB_REG_GPIO_40_PD_LEN   (1U)
+#define GLB_REG_GPIO_40_PD_MSK   (((1U << GLB_REG_GPIO_40_PD_LEN) - 1) << GLB_REG_GPIO_40_PD_POS)
+#define GLB_REG_GPIO_40_PD_UMSK  (~(((1U << GLB_REG_GPIO_40_PD_LEN) - 1) << GLB_REG_GPIO_40_PD_POS))
+
+/* 0x968 : gpio_cfg41 */
+#define GLB_GPIO_CFG41_OFFSET    (0x968)
+#define GLB_REG_GPIO_41_IE       GLB_REG_GPIO_41_IE
+#define GLB_REG_GPIO_41_IE_POS   (0U)
+#define GLB_REG_GPIO_41_IE_LEN   (1U)
+#define GLB_REG_GPIO_41_IE_MSK   (((1U << GLB_REG_GPIO_41_IE_LEN) - 1) << GLB_REG_GPIO_41_IE_POS)
+#define GLB_REG_GPIO_41_IE_UMSK  (~(((1U << GLB_REG_GPIO_41_IE_LEN) - 1) << GLB_REG_GPIO_41_IE_POS))
+#define GLB_REG_GPIO_41_SMT      GLB_REG_GPIO_41_SMT
+#define GLB_REG_GPIO_41_SMT_POS  (1U)
+#define GLB_REG_GPIO_41_SMT_LEN  (1U)
+#define GLB_REG_GPIO_41_SMT_MSK  (((1U << GLB_REG_GPIO_41_SMT_LEN) - 1) << GLB_REG_GPIO_41_SMT_POS)
+#define GLB_REG_GPIO_41_SMT_UMSK (~(((1U << GLB_REG_GPIO_41_SMT_LEN) - 1) << GLB_REG_GPIO_41_SMT_POS))
+#define GLB_REG_GPIO_41_DRV      GLB_REG_GPIO_41_DRV
+#define GLB_REG_GPIO_41_DRV_POS  (2U)
+#define GLB_REG_GPIO_41_DRV_LEN  (2U)
+#define GLB_REG_GPIO_41_DRV_MSK  (((1U << GLB_REG_GPIO_41_DRV_LEN) - 1) << GLB_REG_GPIO_41_DRV_POS)
+#define GLB_REG_GPIO_41_DRV_UMSK (~(((1U << GLB_REG_GPIO_41_DRV_LEN) - 1) << GLB_REG_GPIO_41_DRV_POS))
+#define GLB_REG_GPIO_41_PU       GLB_REG_GPIO_41_PU
+#define GLB_REG_GPIO_41_PU_POS   (4U)
+#define GLB_REG_GPIO_41_PU_LEN   (1U)
+#define GLB_REG_GPIO_41_PU_MSK   (((1U << GLB_REG_GPIO_41_PU_LEN) - 1) << GLB_REG_GPIO_41_PU_POS)
+#define GLB_REG_GPIO_41_PU_UMSK  (~(((1U << GLB_REG_GPIO_41_PU_LEN) - 1) << GLB_REG_GPIO_41_PU_POS))
+#define GLB_REG_GPIO_41_PD       GLB_REG_GPIO_41_PD
+#define GLB_REG_GPIO_41_PD_POS   (5U)
+#define GLB_REG_GPIO_41_PD_LEN   (1U)
+#define GLB_REG_GPIO_41_PD_MSK   (((1U << GLB_REG_GPIO_41_PD_LEN) - 1) << GLB_REG_GPIO_41_PD_POS)
+#define GLB_REG_GPIO_41_PD_UMSK  (~(((1U << GLB_REG_GPIO_41_PD_LEN) - 1) << GLB_REG_GPIO_41_PD_POS))
+
+/* 0x96C : gpio_cfg42 */
+#define GLB_GPIO_CFG42_OFFSET    (0x96C)
+#define GLB_REG_GPIO_42_IE       GLB_REG_GPIO_42_IE
+#define GLB_REG_GPIO_42_IE_POS   (0U)
+#define GLB_REG_GPIO_42_IE_LEN   (1U)
+#define GLB_REG_GPIO_42_IE_MSK   (((1U << GLB_REG_GPIO_42_IE_LEN) - 1) << GLB_REG_GPIO_42_IE_POS)
+#define GLB_REG_GPIO_42_IE_UMSK  (~(((1U << GLB_REG_GPIO_42_IE_LEN) - 1) << GLB_REG_GPIO_42_IE_POS))
+#define GLB_REG_GPIO_42_SMT      GLB_REG_GPIO_42_SMT
+#define GLB_REG_GPIO_42_SMT_POS  (1U)
+#define GLB_REG_GPIO_42_SMT_LEN  (1U)
+#define GLB_REG_GPIO_42_SMT_MSK  (((1U << GLB_REG_GPIO_42_SMT_LEN) - 1) << GLB_REG_GPIO_42_SMT_POS)
+#define GLB_REG_GPIO_42_SMT_UMSK (~(((1U << GLB_REG_GPIO_42_SMT_LEN) - 1) << GLB_REG_GPIO_42_SMT_POS))
+#define GLB_REG_GPIO_42_DRV      GLB_REG_GPIO_42_DRV
+#define GLB_REG_GPIO_42_DRV_POS  (2U)
+#define GLB_REG_GPIO_42_DRV_LEN  (2U)
+#define GLB_REG_GPIO_42_DRV_MSK  (((1U << GLB_REG_GPIO_42_DRV_LEN) - 1) << GLB_REG_GPIO_42_DRV_POS)
+#define GLB_REG_GPIO_42_DRV_UMSK (~(((1U << GLB_REG_GPIO_42_DRV_LEN) - 1) << GLB_REG_GPIO_42_DRV_POS))
+#define GLB_REG_GPIO_42_PU       GLB_REG_GPIO_42_PU
+#define GLB_REG_GPIO_42_PU_POS   (4U)
+#define GLB_REG_GPIO_42_PU_LEN   (1U)
+#define GLB_REG_GPIO_42_PU_MSK   (((1U << GLB_REG_GPIO_42_PU_LEN) - 1) << GLB_REG_GPIO_42_PU_POS)
+#define GLB_REG_GPIO_42_PU_UMSK  (~(((1U << GLB_REG_GPIO_42_PU_LEN) - 1) << GLB_REG_GPIO_42_PU_POS))
+#define GLB_REG_GPIO_42_PD       GLB_REG_GPIO_42_PD
+#define GLB_REG_GPIO_42_PD_POS   (5U)
+#define GLB_REG_GPIO_42_PD_LEN   (1U)
+#define GLB_REG_GPIO_42_PD_MSK   (((1U << GLB_REG_GPIO_42_PD_LEN) - 1) << GLB_REG_GPIO_42_PD_POS)
+#define GLB_REG_GPIO_42_PD_UMSK  (~(((1U << GLB_REG_GPIO_42_PD_LEN) - 1) << GLB_REG_GPIO_42_PD_POS))
+
+/* 0x970 : gpio_cfg43 */
+#define GLB_GPIO_CFG43_OFFSET    (0x970)
+#define GLB_REG_GPIO_43_IE       GLB_REG_GPIO_43_IE
+#define GLB_REG_GPIO_43_IE_POS   (0U)
+#define GLB_REG_GPIO_43_IE_LEN   (1U)
+#define GLB_REG_GPIO_43_IE_MSK   (((1U << GLB_REG_GPIO_43_IE_LEN) - 1) << GLB_REG_GPIO_43_IE_POS)
+#define GLB_REG_GPIO_43_IE_UMSK  (~(((1U << GLB_REG_GPIO_43_IE_LEN) - 1) << GLB_REG_GPIO_43_IE_POS))
+#define GLB_REG_GPIO_43_SMT      GLB_REG_GPIO_43_SMT
+#define GLB_REG_GPIO_43_SMT_POS  (1U)
+#define GLB_REG_GPIO_43_SMT_LEN  (1U)
+#define GLB_REG_GPIO_43_SMT_MSK  (((1U << GLB_REG_GPIO_43_SMT_LEN) - 1) << GLB_REG_GPIO_43_SMT_POS)
+#define GLB_REG_GPIO_43_SMT_UMSK (~(((1U << GLB_REG_GPIO_43_SMT_LEN) - 1) << GLB_REG_GPIO_43_SMT_POS))
+#define GLB_REG_GPIO_43_DRV      GLB_REG_GPIO_43_DRV
+#define GLB_REG_GPIO_43_DRV_POS  (2U)
+#define GLB_REG_GPIO_43_DRV_LEN  (2U)
+#define GLB_REG_GPIO_43_DRV_MSK  (((1U << GLB_REG_GPIO_43_DRV_LEN) - 1) << GLB_REG_GPIO_43_DRV_POS)
+#define GLB_REG_GPIO_43_DRV_UMSK (~(((1U << GLB_REG_GPIO_43_DRV_LEN) - 1) << GLB_REG_GPIO_43_DRV_POS))
+#define GLB_REG_GPIO_43_PU       GLB_REG_GPIO_43_PU
+#define GLB_REG_GPIO_43_PU_POS   (4U)
+#define GLB_REG_GPIO_43_PU_LEN   (1U)
+#define GLB_REG_GPIO_43_PU_MSK   (((1U << GLB_REG_GPIO_43_PU_LEN) - 1) << GLB_REG_GPIO_43_PU_POS)
+#define GLB_REG_GPIO_43_PU_UMSK  (~(((1U << GLB_REG_GPIO_43_PU_LEN) - 1) << GLB_REG_GPIO_43_PU_POS))
+#define GLB_REG_GPIO_43_PD       GLB_REG_GPIO_43_PD
+#define GLB_REG_GPIO_43_PD_POS   (5U)
+#define GLB_REG_GPIO_43_PD_LEN   (1U)
+#define GLB_REG_GPIO_43_PD_MSK   (((1U << GLB_REG_GPIO_43_PD_LEN) - 1) << GLB_REG_GPIO_43_PD_POS)
+#define GLB_REG_GPIO_43_PD_UMSK  (~(((1U << GLB_REG_GPIO_43_PD_LEN) - 1) << GLB_REG_GPIO_43_PD_POS))
+
+/* 0x974 : gpio_cfg44 */
+#define GLB_GPIO_CFG44_OFFSET    (0x974)
+#define GLB_REG_GPIO_44_IE       GLB_REG_GPIO_44_IE
+#define GLB_REG_GPIO_44_IE_POS   (0U)
+#define GLB_REG_GPIO_44_IE_LEN   (1U)
+#define GLB_REG_GPIO_44_IE_MSK   (((1U << GLB_REG_GPIO_44_IE_LEN) - 1) << GLB_REG_GPIO_44_IE_POS)
+#define GLB_REG_GPIO_44_IE_UMSK  (~(((1U << GLB_REG_GPIO_44_IE_LEN) - 1) << GLB_REG_GPIO_44_IE_POS))
+#define GLB_REG_GPIO_44_SMT      GLB_REG_GPIO_44_SMT
+#define GLB_REG_GPIO_44_SMT_POS  (1U)
+#define GLB_REG_GPIO_44_SMT_LEN  (1U)
+#define GLB_REG_GPIO_44_SMT_MSK  (((1U << GLB_REG_GPIO_44_SMT_LEN) - 1) << GLB_REG_GPIO_44_SMT_POS)
+#define GLB_REG_GPIO_44_SMT_UMSK (~(((1U << GLB_REG_GPIO_44_SMT_LEN) - 1) << GLB_REG_GPIO_44_SMT_POS))
+#define GLB_REG_GPIO_44_DRV      GLB_REG_GPIO_44_DRV
+#define GLB_REG_GPIO_44_DRV_POS  (2U)
+#define GLB_REG_GPIO_44_DRV_LEN  (2U)
+#define GLB_REG_GPIO_44_DRV_MSK  (((1U << GLB_REG_GPIO_44_DRV_LEN) - 1) << GLB_REG_GPIO_44_DRV_POS)
+#define GLB_REG_GPIO_44_DRV_UMSK (~(((1U << GLB_REG_GPIO_44_DRV_LEN) - 1) << GLB_REG_GPIO_44_DRV_POS))
+#define GLB_REG_GPIO_44_PU       GLB_REG_GPIO_44_PU
+#define GLB_REG_GPIO_44_PU_POS   (4U)
+#define GLB_REG_GPIO_44_PU_LEN   (1U)
+#define GLB_REG_GPIO_44_PU_MSK   (((1U << GLB_REG_GPIO_44_PU_LEN) - 1) << GLB_REG_GPIO_44_PU_POS)
+#define GLB_REG_GPIO_44_PU_UMSK  (~(((1U << GLB_REG_GPIO_44_PU_LEN) - 1) << GLB_REG_GPIO_44_PU_POS))
+#define GLB_REG_GPIO_44_PD       GLB_REG_GPIO_44_PD
+#define GLB_REG_GPIO_44_PD_POS   (5U)
+#define GLB_REG_GPIO_44_PD_LEN   (1U)
+#define GLB_REG_GPIO_44_PD_MSK   (((1U << GLB_REG_GPIO_44_PD_LEN) - 1) << GLB_REG_GPIO_44_PD_POS)
+#define GLB_REG_GPIO_44_PD_UMSK  (~(((1U << GLB_REG_GPIO_44_PD_LEN) - 1) << GLB_REG_GPIO_44_PD_POS))
+
+/* 0x978 : gpio_cfg45 */
+#define GLB_GPIO_CFG45_OFFSET    (0x978)
+#define GLB_REG_GPIO_45_IE       GLB_REG_GPIO_45_IE
+#define GLB_REG_GPIO_45_IE_POS   (0U)
+#define GLB_REG_GPIO_45_IE_LEN   (1U)
+#define GLB_REG_GPIO_45_IE_MSK   (((1U << GLB_REG_GPIO_45_IE_LEN) - 1) << GLB_REG_GPIO_45_IE_POS)
+#define GLB_REG_GPIO_45_IE_UMSK  (~(((1U << GLB_REG_GPIO_45_IE_LEN) - 1) << GLB_REG_GPIO_45_IE_POS))
+#define GLB_REG_GPIO_45_SMT      GLB_REG_GPIO_45_SMT
+#define GLB_REG_GPIO_45_SMT_POS  (1U)
+#define GLB_REG_GPIO_45_SMT_LEN  (1U)
+#define GLB_REG_GPIO_45_SMT_MSK  (((1U << GLB_REG_GPIO_45_SMT_LEN) - 1) << GLB_REG_GPIO_45_SMT_POS)
+#define GLB_REG_GPIO_45_SMT_UMSK (~(((1U << GLB_REG_GPIO_45_SMT_LEN) - 1) << GLB_REG_GPIO_45_SMT_POS))
+#define GLB_REG_GPIO_45_DRV      GLB_REG_GPIO_45_DRV
+#define GLB_REG_GPIO_45_DRV_POS  (2U)
+#define GLB_REG_GPIO_45_DRV_LEN  (2U)
+#define GLB_REG_GPIO_45_DRV_MSK  (((1U << GLB_REG_GPIO_45_DRV_LEN) - 1) << GLB_REG_GPIO_45_DRV_POS)
+#define GLB_REG_GPIO_45_DRV_UMSK (~(((1U << GLB_REG_GPIO_45_DRV_LEN) - 1) << GLB_REG_GPIO_45_DRV_POS))
+#define GLB_REG_GPIO_45_PU       GLB_REG_GPIO_45_PU
+#define GLB_REG_GPIO_45_PU_POS   (4U)
+#define GLB_REG_GPIO_45_PU_LEN   (1U)
+#define GLB_REG_GPIO_45_PU_MSK   (((1U << GLB_REG_GPIO_45_PU_LEN) - 1) << GLB_REG_GPIO_45_PU_POS)
+#define GLB_REG_GPIO_45_PU_UMSK  (~(((1U << GLB_REG_GPIO_45_PU_LEN) - 1) << GLB_REG_GPIO_45_PU_POS))
+#define GLB_REG_GPIO_45_PD       GLB_REG_GPIO_45_PD
+#define GLB_REG_GPIO_45_PD_POS   (5U)
+#define GLB_REG_GPIO_45_PD_LEN   (1U)
+#define GLB_REG_GPIO_45_PD_MSK   (((1U << GLB_REG_GPIO_45_PD_LEN) - 1) << GLB_REG_GPIO_45_PD_POS)
+#define GLB_REG_GPIO_45_PD_UMSK  (~(((1U << GLB_REG_GPIO_45_PD_LEN) - 1) << GLB_REG_GPIO_45_PD_POS))
+
+/* 0x97C : gpio_cfg46 */
+#define GLB_GPIO_CFG46_OFFSET    (0x97C)
+#define GLB_REG_GPIO_46_IE       GLB_REG_GPIO_46_IE
+#define GLB_REG_GPIO_46_IE_POS   (0U)
+#define GLB_REG_GPIO_46_IE_LEN   (1U)
+#define GLB_REG_GPIO_46_IE_MSK   (((1U << GLB_REG_GPIO_46_IE_LEN) - 1) << GLB_REG_GPIO_46_IE_POS)
+#define GLB_REG_GPIO_46_IE_UMSK  (~(((1U << GLB_REG_GPIO_46_IE_LEN) - 1) << GLB_REG_GPIO_46_IE_POS))
+#define GLB_REG_GPIO_46_SMT      GLB_REG_GPIO_46_SMT
+#define GLB_REG_GPIO_46_SMT_POS  (1U)
+#define GLB_REG_GPIO_46_SMT_LEN  (1U)
+#define GLB_REG_GPIO_46_SMT_MSK  (((1U << GLB_REG_GPIO_46_SMT_LEN) - 1) << GLB_REG_GPIO_46_SMT_POS)
+#define GLB_REG_GPIO_46_SMT_UMSK (~(((1U << GLB_REG_GPIO_46_SMT_LEN) - 1) << GLB_REG_GPIO_46_SMT_POS))
+#define GLB_REG_GPIO_46_DRV      GLB_REG_GPIO_46_DRV
+#define GLB_REG_GPIO_46_DRV_POS  (2U)
+#define GLB_REG_GPIO_46_DRV_LEN  (2U)
+#define GLB_REG_GPIO_46_DRV_MSK  (((1U << GLB_REG_GPIO_46_DRV_LEN) - 1) << GLB_REG_GPIO_46_DRV_POS)
+#define GLB_REG_GPIO_46_DRV_UMSK (~(((1U << GLB_REG_GPIO_46_DRV_LEN) - 1) << GLB_REG_GPIO_46_DRV_POS))
+#define GLB_REG_GPIO_46_PU       GLB_REG_GPIO_46_PU
+#define GLB_REG_GPIO_46_PU_POS   (4U)
+#define GLB_REG_GPIO_46_PU_LEN   (1U)
+#define GLB_REG_GPIO_46_PU_MSK   (((1U << GLB_REG_GPIO_46_PU_LEN) - 1) << GLB_REG_GPIO_46_PU_POS)
+#define GLB_REG_GPIO_46_PU_UMSK  (~(((1U << GLB_REG_GPIO_46_PU_LEN) - 1) << GLB_REG_GPIO_46_PU_POS))
+#define GLB_REG_GPIO_46_PD       GLB_REG_GPIO_46_PD
+#define GLB_REG_GPIO_46_PD_POS   (5U)
+#define GLB_REG_GPIO_46_PD_LEN   (1U)
+#define GLB_REG_GPIO_46_PD_MSK   (((1U << GLB_REG_GPIO_46_PD_LEN) - 1) << GLB_REG_GPIO_46_PD_POS)
+#define GLB_REG_GPIO_46_PD_UMSK  (~(((1U << GLB_REG_GPIO_46_PD_LEN) - 1) << GLB_REG_GPIO_46_PD_POS))
+
+/* 0x980 : gpio_cfg47 */
+#define GLB_GPIO_CFG47_OFFSET    (0x980)
+#define GLB_REG_GPIO_47_IE       GLB_REG_GPIO_47_IE
+#define GLB_REG_GPIO_47_IE_POS   (0U)
+#define GLB_REG_GPIO_47_IE_LEN   (1U)
+#define GLB_REG_GPIO_47_IE_MSK   (((1U << GLB_REG_GPIO_47_IE_LEN) - 1) << GLB_REG_GPIO_47_IE_POS)
+#define GLB_REG_GPIO_47_IE_UMSK  (~(((1U << GLB_REG_GPIO_47_IE_LEN) - 1) << GLB_REG_GPIO_47_IE_POS))
+#define GLB_REG_GPIO_47_SMT      GLB_REG_GPIO_47_SMT
+#define GLB_REG_GPIO_47_SMT_POS  (1U)
+#define GLB_REG_GPIO_47_SMT_LEN  (1U)
+#define GLB_REG_GPIO_47_SMT_MSK  (((1U << GLB_REG_GPIO_47_SMT_LEN) - 1) << GLB_REG_GPIO_47_SMT_POS)
+#define GLB_REG_GPIO_47_SMT_UMSK (~(((1U << GLB_REG_GPIO_47_SMT_LEN) - 1) << GLB_REG_GPIO_47_SMT_POS))
+#define GLB_REG_GPIO_47_DRV      GLB_REG_GPIO_47_DRV
+#define GLB_REG_GPIO_47_DRV_POS  (2U)
+#define GLB_REG_GPIO_47_DRV_LEN  (2U)
+#define GLB_REG_GPIO_47_DRV_MSK  (((1U << GLB_REG_GPIO_47_DRV_LEN) - 1) << GLB_REG_GPIO_47_DRV_POS)
+#define GLB_REG_GPIO_47_DRV_UMSK (~(((1U << GLB_REG_GPIO_47_DRV_LEN) - 1) << GLB_REG_GPIO_47_DRV_POS))
+#define GLB_REG_GPIO_47_PU       GLB_REG_GPIO_47_PU
+#define GLB_REG_GPIO_47_PU_POS   (4U)
+#define GLB_REG_GPIO_47_PU_LEN   (1U)
+#define GLB_REG_GPIO_47_PU_MSK   (((1U << GLB_REG_GPIO_47_PU_LEN) - 1) << GLB_REG_GPIO_47_PU_POS)
+#define GLB_REG_GPIO_47_PU_UMSK  (~(((1U << GLB_REG_GPIO_47_PU_LEN) - 1) << GLB_REG_GPIO_47_PU_POS))
+#define GLB_REG_GPIO_47_PD       GLB_REG_GPIO_47_PD
+#define GLB_REG_GPIO_47_PD_POS   (5U)
+#define GLB_REG_GPIO_47_PD_LEN   (1U)
+#define GLB_REG_GPIO_47_PD_MSK   (((1U << GLB_REG_GPIO_47_PD_LEN) - 1) << GLB_REG_GPIO_47_PD_POS)
+#define GLB_REG_GPIO_47_PD_UMSK  (~(((1U << GLB_REG_GPIO_47_PD_LEN) - 1) << GLB_REG_GPIO_47_PD_POS))
+
+/* 0x984 : gpio_cfg48 */
+#define GLB_GPIO_CFG48_OFFSET    (0x984)
+#define GLB_REG_GPIO_48_IE       GLB_REG_GPIO_48_IE
+#define GLB_REG_GPIO_48_IE_POS   (0U)
+#define GLB_REG_GPIO_48_IE_LEN   (1U)
+#define GLB_REG_GPIO_48_IE_MSK   (((1U << GLB_REG_GPIO_48_IE_LEN) - 1) << GLB_REG_GPIO_48_IE_POS)
+#define GLB_REG_GPIO_48_IE_UMSK  (~(((1U << GLB_REG_GPIO_48_IE_LEN) - 1) << GLB_REG_GPIO_48_IE_POS))
+#define GLB_REG_GPIO_48_SMT      GLB_REG_GPIO_48_SMT
+#define GLB_REG_GPIO_48_SMT_POS  (1U)
+#define GLB_REG_GPIO_48_SMT_LEN  (1U)
+#define GLB_REG_GPIO_48_SMT_MSK  (((1U << GLB_REG_GPIO_48_SMT_LEN) - 1) << GLB_REG_GPIO_48_SMT_POS)
+#define GLB_REG_GPIO_48_SMT_UMSK (~(((1U << GLB_REG_GPIO_48_SMT_LEN) - 1) << GLB_REG_GPIO_48_SMT_POS))
+#define GLB_REG_GPIO_48_DRV      GLB_REG_GPIO_48_DRV
+#define GLB_REG_GPIO_48_DRV_POS  (2U)
+#define GLB_REG_GPIO_48_DRV_LEN  (2U)
+#define GLB_REG_GPIO_48_DRV_MSK  (((1U << GLB_REG_GPIO_48_DRV_LEN) - 1) << GLB_REG_GPIO_48_DRV_POS)
+#define GLB_REG_GPIO_48_DRV_UMSK (~(((1U << GLB_REG_GPIO_48_DRV_LEN) - 1) << GLB_REG_GPIO_48_DRV_POS))
+#define GLB_REG_GPIO_48_PU       GLB_REG_GPIO_48_PU
+#define GLB_REG_GPIO_48_PU_POS   (4U)
+#define GLB_REG_GPIO_48_PU_LEN   (1U)
+#define GLB_REG_GPIO_48_PU_MSK   (((1U << GLB_REG_GPIO_48_PU_LEN) - 1) << GLB_REG_GPIO_48_PU_POS)
+#define GLB_REG_GPIO_48_PU_UMSK  (~(((1U << GLB_REG_GPIO_48_PU_LEN) - 1) << GLB_REG_GPIO_48_PU_POS))
+#define GLB_REG_GPIO_48_PD       GLB_REG_GPIO_48_PD
+#define GLB_REG_GPIO_48_PD_POS   (5U)
+#define GLB_REG_GPIO_48_PD_LEN   (1U)
+#define GLB_REG_GPIO_48_PD_MSK   (((1U << GLB_REG_GPIO_48_PD_LEN) - 1) << GLB_REG_GPIO_48_PD_POS)
+#define GLB_REG_GPIO_48_PD_UMSK  (~(((1U << GLB_REG_GPIO_48_PD_LEN) - 1) << GLB_REG_GPIO_48_PD_POS))
+
+/* 0x988 : gpio_cfg49 */
+#define GLB_GPIO_CFG49_OFFSET    (0x988)
+#define GLB_REG_GPIO_49_IE       GLB_REG_GPIO_49_IE
+#define GLB_REG_GPIO_49_IE_POS   (0U)
+#define GLB_REG_GPIO_49_IE_LEN   (1U)
+#define GLB_REG_GPIO_49_IE_MSK   (((1U << GLB_REG_GPIO_49_IE_LEN) - 1) << GLB_REG_GPIO_49_IE_POS)
+#define GLB_REG_GPIO_49_IE_UMSK  (~(((1U << GLB_REG_GPIO_49_IE_LEN) - 1) << GLB_REG_GPIO_49_IE_POS))
+#define GLB_REG_GPIO_49_SMT      GLB_REG_GPIO_49_SMT
+#define GLB_REG_GPIO_49_SMT_POS  (1U)
+#define GLB_REG_GPIO_49_SMT_LEN  (1U)
+#define GLB_REG_GPIO_49_SMT_MSK  (((1U << GLB_REG_GPIO_49_SMT_LEN) - 1) << GLB_REG_GPIO_49_SMT_POS)
+#define GLB_REG_GPIO_49_SMT_UMSK (~(((1U << GLB_REG_GPIO_49_SMT_LEN) - 1) << GLB_REG_GPIO_49_SMT_POS))
+#define GLB_REG_GPIO_49_DRV      GLB_REG_GPIO_49_DRV
+#define GLB_REG_GPIO_49_DRV_POS  (2U)
+#define GLB_REG_GPIO_49_DRV_LEN  (2U)
+#define GLB_REG_GPIO_49_DRV_MSK  (((1U << GLB_REG_GPIO_49_DRV_LEN) - 1) << GLB_REG_GPIO_49_DRV_POS)
+#define GLB_REG_GPIO_49_DRV_UMSK (~(((1U << GLB_REG_GPIO_49_DRV_LEN) - 1) << GLB_REG_GPIO_49_DRV_POS))
+#define GLB_REG_GPIO_49_PU       GLB_REG_GPIO_49_PU
+#define GLB_REG_GPIO_49_PU_POS   (4U)
+#define GLB_REG_GPIO_49_PU_LEN   (1U)
+#define GLB_REG_GPIO_49_PU_MSK   (((1U << GLB_REG_GPIO_49_PU_LEN) - 1) << GLB_REG_GPIO_49_PU_POS)
+#define GLB_REG_GPIO_49_PU_UMSK  (~(((1U << GLB_REG_GPIO_49_PU_LEN) - 1) << GLB_REG_GPIO_49_PU_POS))
+#define GLB_REG_GPIO_49_PD       GLB_REG_GPIO_49_PD
+#define GLB_REG_GPIO_49_PD_POS   (5U)
+#define GLB_REG_GPIO_49_PD_LEN   (1U)
+#define GLB_REG_GPIO_49_PD_MSK   (((1U << GLB_REG_GPIO_49_PD_LEN) - 1) << GLB_REG_GPIO_49_PD_POS)
+#define GLB_REG_GPIO_49_PD_UMSK  (~(((1U << GLB_REG_GPIO_49_PD_LEN) - 1) << GLB_REG_GPIO_49_PD_POS))
+
+/* 0x98C : gpio_cfg50 */
+#define GLB_GPIO_CFG50_OFFSET    (0x98C)
+#define GLB_REG_GPIO_50_IE       GLB_REG_GPIO_50_IE
+#define GLB_REG_GPIO_50_IE_POS   (0U)
+#define GLB_REG_GPIO_50_IE_LEN   (1U)
+#define GLB_REG_GPIO_50_IE_MSK   (((1U << GLB_REG_GPIO_50_IE_LEN) - 1) << GLB_REG_GPIO_50_IE_POS)
+#define GLB_REG_GPIO_50_IE_UMSK  (~(((1U << GLB_REG_GPIO_50_IE_LEN) - 1) << GLB_REG_GPIO_50_IE_POS))
+#define GLB_REG_GPIO_50_SMT      GLB_REG_GPIO_50_SMT
+#define GLB_REG_GPIO_50_SMT_POS  (1U)
+#define GLB_REG_GPIO_50_SMT_LEN  (1U)
+#define GLB_REG_GPIO_50_SMT_MSK  (((1U << GLB_REG_GPIO_50_SMT_LEN) - 1) << GLB_REG_GPIO_50_SMT_POS)
+#define GLB_REG_GPIO_50_SMT_UMSK (~(((1U << GLB_REG_GPIO_50_SMT_LEN) - 1) << GLB_REG_GPIO_50_SMT_POS))
+#define GLB_REG_GPIO_50_DRV      GLB_REG_GPIO_50_DRV
+#define GLB_REG_GPIO_50_DRV_POS  (2U)
+#define GLB_REG_GPIO_50_DRV_LEN  (2U)
+#define GLB_REG_GPIO_50_DRV_MSK  (((1U << GLB_REG_GPIO_50_DRV_LEN) - 1) << GLB_REG_GPIO_50_DRV_POS)
+#define GLB_REG_GPIO_50_DRV_UMSK (~(((1U << GLB_REG_GPIO_50_DRV_LEN) - 1) << GLB_REG_GPIO_50_DRV_POS))
+#define GLB_REG_GPIO_50_PU       GLB_REG_GPIO_50_PU
+#define GLB_REG_GPIO_50_PU_POS   (4U)
+#define GLB_REG_GPIO_50_PU_LEN   (1U)
+#define GLB_REG_GPIO_50_PU_MSK   (((1U << GLB_REG_GPIO_50_PU_LEN) - 1) << GLB_REG_GPIO_50_PU_POS)
+#define GLB_REG_GPIO_50_PU_UMSK  (~(((1U << GLB_REG_GPIO_50_PU_LEN) - 1) << GLB_REG_GPIO_50_PU_POS))
+#define GLB_REG_GPIO_50_PD       GLB_REG_GPIO_50_PD
+#define GLB_REG_GPIO_50_PD_POS   (5U)
+#define GLB_REG_GPIO_50_PD_LEN   (1U)
+#define GLB_REG_GPIO_50_PD_MSK   (((1U << GLB_REG_GPIO_50_PD_LEN) - 1) << GLB_REG_GPIO_50_PD_POS)
+#define GLB_REG_GPIO_50_PD_UMSK  (~(((1U << GLB_REG_GPIO_50_PD_LEN) - 1) << GLB_REG_GPIO_50_PD_POS))
+
+/* 0x990 : gpio_cfg51 */
+#define GLB_GPIO_CFG51_OFFSET    (0x990)
+#define GLB_REG_GPIO_51_IE       GLB_REG_GPIO_51_IE
+#define GLB_REG_GPIO_51_IE_POS   (0U)
+#define GLB_REG_GPIO_51_IE_LEN   (1U)
+#define GLB_REG_GPIO_51_IE_MSK   (((1U << GLB_REG_GPIO_51_IE_LEN) - 1) << GLB_REG_GPIO_51_IE_POS)
+#define GLB_REG_GPIO_51_IE_UMSK  (~(((1U << GLB_REG_GPIO_51_IE_LEN) - 1) << GLB_REG_GPIO_51_IE_POS))
+#define GLB_REG_GPIO_51_SMT      GLB_REG_GPIO_51_SMT
+#define GLB_REG_GPIO_51_SMT_POS  (1U)
+#define GLB_REG_GPIO_51_SMT_LEN  (1U)
+#define GLB_REG_GPIO_51_SMT_MSK  (((1U << GLB_REG_GPIO_51_SMT_LEN) - 1) << GLB_REG_GPIO_51_SMT_POS)
+#define GLB_REG_GPIO_51_SMT_UMSK (~(((1U << GLB_REG_GPIO_51_SMT_LEN) - 1) << GLB_REG_GPIO_51_SMT_POS))
+#define GLB_REG_GPIO_51_DRV      GLB_REG_GPIO_51_DRV
+#define GLB_REG_GPIO_51_DRV_POS  (2U)
+#define GLB_REG_GPIO_51_DRV_LEN  (2U)
+#define GLB_REG_GPIO_51_DRV_MSK  (((1U << GLB_REG_GPIO_51_DRV_LEN) - 1) << GLB_REG_GPIO_51_DRV_POS)
+#define GLB_REG_GPIO_51_DRV_UMSK (~(((1U << GLB_REG_GPIO_51_DRV_LEN) - 1) << GLB_REG_GPIO_51_DRV_POS))
+#define GLB_REG_GPIO_51_PU       GLB_REG_GPIO_51_PU
+#define GLB_REG_GPIO_51_PU_POS   (4U)
+#define GLB_REG_GPIO_51_PU_LEN   (1U)
+#define GLB_REG_GPIO_51_PU_MSK   (((1U << GLB_REG_GPIO_51_PU_LEN) - 1) << GLB_REG_GPIO_51_PU_POS)
+#define GLB_REG_GPIO_51_PU_UMSK  (~(((1U << GLB_REG_GPIO_51_PU_LEN) - 1) << GLB_REG_GPIO_51_PU_POS))
+#define GLB_REG_GPIO_51_PD       GLB_REG_GPIO_51_PD
+#define GLB_REG_GPIO_51_PD_POS   (5U)
+#define GLB_REG_GPIO_51_PD_LEN   (1U)
+#define GLB_REG_GPIO_51_PD_MSK   (((1U << GLB_REG_GPIO_51_PD_LEN) - 1) << GLB_REG_GPIO_51_PD_POS)
+#define GLB_REG_GPIO_51_PD_UMSK  (~(((1U << GLB_REG_GPIO_51_PD_LEN) - 1) << GLB_REG_GPIO_51_PD_POS))
+
+/* 0x994 : gpio_cfg52 */
+#define GLB_GPIO_CFG52_OFFSET    (0x994)
+#define GLB_REG_GPIO_52_IE       GLB_REG_GPIO_52_IE
+#define GLB_REG_GPIO_52_IE_POS   (0U)
+#define GLB_REG_GPIO_52_IE_LEN   (1U)
+#define GLB_REG_GPIO_52_IE_MSK   (((1U << GLB_REG_GPIO_52_IE_LEN) - 1) << GLB_REG_GPIO_52_IE_POS)
+#define GLB_REG_GPIO_52_IE_UMSK  (~(((1U << GLB_REG_GPIO_52_IE_LEN) - 1) << GLB_REG_GPIO_52_IE_POS))
+#define GLB_REG_GPIO_52_SMT      GLB_REG_GPIO_52_SMT
+#define GLB_REG_GPIO_52_SMT_POS  (1U)
+#define GLB_REG_GPIO_52_SMT_LEN  (1U)
+#define GLB_REG_GPIO_52_SMT_MSK  (((1U << GLB_REG_GPIO_52_SMT_LEN) - 1) << GLB_REG_GPIO_52_SMT_POS)
+#define GLB_REG_GPIO_52_SMT_UMSK (~(((1U << GLB_REG_GPIO_52_SMT_LEN) - 1) << GLB_REG_GPIO_52_SMT_POS))
+#define GLB_REG_GPIO_52_DRV      GLB_REG_GPIO_52_DRV
+#define GLB_REG_GPIO_52_DRV_POS  (2U)
+#define GLB_REG_GPIO_52_DRV_LEN  (2U)
+#define GLB_REG_GPIO_52_DRV_MSK  (((1U << GLB_REG_GPIO_52_DRV_LEN) - 1) << GLB_REG_GPIO_52_DRV_POS)
+#define GLB_REG_GPIO_52_DRV_UMSK (~(((1U << GLB_REG_GPIO_52_DRV_LEN) - 1) << GLB_REG_GPIO_52_DRV_POS))
+#define GLB_REG_GPIO_52_PU       GLB_REG_GPIO_52_PU
+#define GLB_REG_GPIO_52_PU_POS   (4U)
+#define GLB_REG_GPIO_52_PU_LEN   (1U)
+#define GLB_REG_GPIO_52_PU_MSK   (((1U << GLB_REG_GPIO_52_PU_LEN) - 1) << GLB_REG_GPIO_52_PU_POS)
+#define GLB_REG_GPIO_52_PU_UMSK  (~(((1U << GLB_REG_GPIO_52_PU_LEN) - 1) << GLB_REG_GPIO_52_PU_POS))
+#define GLB_REG_GPIO_52_PD       GLB_REG_GPIO_52_PD
+#define GLB_REG_GPIO_52_PD_POS   (5U)
+#define GLB_REG_GPIO_52_PD_LEN   (1U)
+#define GLB_REG_GPIO_52_PD_MSK   (((1U << GLB_REG_GPIO_52_PD_LEN) - 1) << GLB_REG_GPIO_52_PD_POS)
+#define GLB_REG_GPIO_52_PD_UMSK  (~(((1U << GLB_REG_GPIO_52_PD_LEN) - 1) << GLB_REG_GPIO_52_PD_POS))
+
+/* 0x998 : gpio_cfg53 */
+#define GLB_GPIO_CFG53_OFFSET    (0x998)
+#define GLB_REG_GPIO_53_IE       GLB_REG_GPIO_53_IE
+#define GLB_REG_GPIO_53_IE_POS   (0U)
+#define GLB_REG_GPIO_53_IE_LEN   (1U)
+#define GLB_REG_GPIO_53_IE_MSK   (((1U << GLB_REG_GPIO_53_IE_LEN) - 1) << GLB_REG_GPIO_53_IE_POS)
+#define GLB_REG_GPIO_53_IE_UMSK  (~(((1U << GLB_REG_GPIO_53_IE_LEN) - 1) << GLB_REG_GPIO_53_IE_POS))
+#define GLB_REG_GPIO_53_SMT      GLB_REG_GPIO_53_SMT
+#define GLB_REG_GPIO_53_SMT_POS  (1U)
+#define GLB_REG_GPIO_53_SMT_LEN  (1U)
+#define GLB_REG_GPIO_53_SMT_MSK  (((1U << GLB_REG_GPIO_53_SMT_LEN) - 1) << GLB_REG_GPIO_53_SMT_POS)
+#define GLB_REG_GPIO_53_SMT_UMSK (~(((1U << GLB_REG_GPIO_53_SMT_LEN) - 1) << GLB_REG_GPIO_53_SMT_POS))
+#define GLB_REG_GPIO_53_DRV      GLB_REG_GPIO_53_DRV
+#define GLB_REG_GPIO_53_DRV_POS  (2U)
+#define GLB_REG_GPIO_53_DRV_LEN  (2U)
+#define GLB_REG_GPIO_53_DRV_MSK  (((1U << GLB_REG_GPIO_53_DRV_LEN) - 1) << GLB_REG_GPIO_53_DRV_POS)
+#define GLB_REG_GPIO_53_DRV_UMSK (~(((1U << GLB_REG_GPIO_53_DRV_LEN) - 1) << GLB_REG_GPIO_53_DRV_POS))
+#define GLB_REG_GPIO_53_PU       GLB_REG_GPIO_53_PU
+#define GLB_REG_GPIO_53_PU_POS   (4U)
+#define GLB_REG_GPIO_53_PU_LEN   (1U)
+#define GLB_REG_GPIO_53_PU_MSK   (((1U << GLB_REG_GPIO_53_PU_LEN) - 1) << GLB_REG_GPIO_53_PU_POS)
+#define GLB_REG_GPIO_53_PU_UMSK  (~(((1U << GLB_REG_GPIO_53_PU_LEN) - 1) << GLB_REG_GPIO_53_PU_POS))
+#define GLB_REG_GPIO_53_PD       GLB_REG_GPIO_53_PD
+#define GLB_REG_GPIO_53_PD_POS   (5U)
+#define GLB_REG_GPIO_53_PD_LEN   (1U)
+#define GLB_REG_GPIO_53_PD_MSK   (((1U << GLB_REG_GPIO_53_PD_LEN) - 1) << GLB_REG_GPIO_53_PD_POS)
+#define GLB_REG_GPIO_53_PD_UMSK  (~(((1U << GLB_REG_GPIO_53_PD_LEN) - 1) << GLB_REG_GPIO_53_PD_POS))
+
+/* 0x99C : gpio_cfg54 */
+#define GLB_GPIO_CFG54_OFFSET    (0x99C)
+#define GLB_REG_GPIO_54_IE       GLB_REG_GPIO_54_IE
+#define GLB_REG_GPIO_54_IE_POS   (0U)
+#define GLB_REG_GPIO_54_IE_LEN   (1U)
+#define GLB_REG_GPIO_54_IE_MSK   (((1U << GLB_REG_GPIO_54_IE_LEN) - 1) << GLB_REG_GPIO_54_IE_POS)
+#define GLB_REG_GPIO_54_IE_UMSK  (~(((1U << GLB_REG_GPIO_54_IE_LEN) - 1) << GLB_REG_GPIO_54_IE_POS))
+#define GLB_REG_GPIO_54_SMT      GLB_REG_GPIO_54_SMT
+#define GLB_REG_GPIO_54_SMT_POS  (1U)
+#define GLB_REG_GPIO_54_SMT_LEN  (1U)
+#define GLB_REG_GPIO_54_SMT_MSK  (((1U << GLB_REG_GPIO_54_SMT_LEN) - 1) << GLB_REG_GPIO_54_SMT_POS)
+#define GLB_REG_GPIO_54_SMT_UMSK (~(((1U << GLB_REG_GPIO_54_SMT_LEN) - 1) << GLB_REG_GPIO_54_SMT_POS))
+#define GLB_REG_GPIO_54_DRV      GLB_REG_GPIO_54_DRV
+#define GLB_REG_GPIO_54_DRV_POS  (2U)
+#define GLB_REG_GPIO_54_DRV_LEN  (2U)
+#define GLB_REG_GPIO_54_DRV_MSK  (((1U << GLB_REG_GPIO_54_DRV_LEN) - 1) << GLB_REG_GPIO_54_DRV_POS)
+#define GLB_REG_GPIO_54_DRV_UMSK (~(((1U << GLB_REG_GPIO_54_DRV_LEN) - 1) << GLB_REG_GPIO_54_DRV_POS))
+#define GLB_REG_GPIO_54_PU       GLB_REG_GPIO_54_PU
+#define GLB_REG_GPIO_54_PU_POS   (4U)
+#define GLB_REG_GPIO_54_PU_LEN   (1U)
+#define GLB_REG_GPIO_54_PU_MSK   (((1U << GLB_REG_GPIO_54_PU_LEN) - 1) << GLB_REG_GPIO_54_PU_POS)
+#define GLB_REG_GPIO_54_PU_UMSK  (~(((1U << GLB_REG_GPIO_54_PU_LEN) - 1) << GLB_REG_GPIO_54_PU_POS))
+#define GLB_REG_GPIO_54_PD       GLB_REG_GPIO_54_PD
+#define GLB_REG_GPIO_54_PD_POS   (5U)
+#define GLB_REG_GPIO_54_PD_LEN   (1U)
+#define GLB_REG_GPIO_54_PD_MSK   (((1U << GLB_REG_GPIO_54_PD_LEN) - 1) << GLB_REG_GPIO_54_PD_POS)
+#define GLB_REG_GPIO_54_PD_UMSK  (~(((1U << GLB_REG_GPIO_54_PD_LEN) - 1) << GLB_REG_GPIO_54_PD_POS))
+
+/* 0x9A0 : gpio_cfg55 */
+#define GLB_GPIO_CFG55_OFFSET    (0x9A0)
+#define GLB_REG_GPIO_55_IE       GLB_REG_GPIO_55_IE
+#define GLB_REG_GPIO_55_IE_POS   (0U)
+#define GLB_REG_GPIO_55_IE_LEN   (1U)
+#define GLB_REG_GPIO_55_IE_MSK   (((1U << GLB_REG_GPIO_55_IE_LEN) - 1) << GLB_REG_GPIO_55_IE_POS)
+#define GLB_REG_GPIO_55_IE_UMSK  (~(((1U << GLB_REG_GPIO_55_IE_LEN) - 1) << GLB_REG_GPIO_55_IE_POS))
+#define GLB_REG_GPIO_55_SMT      GLB_REG_GPIO_55_SMT
+#define GLB_REG_GPIO_55_SMT_POS  (1U)
+#define GLB_REG_GPIO_55_SMT_LEN  (1U)
+#define GLB_REG_GPIO_55_SMT_MSK  (((1U << GLB_REG_GPIO_55_SMT_LEN) - 1) << GLB_REG_GPIO_55_SMT_POS)
+#define GLB_REG_GPIO_55_SMT_UMSK (~(((1U << GLB_REG_GPIO_55_SMT_LEN) - 1) << GLB_REG_GPIO_55_SMT_POS))
+#define GLB_REG_GPIO_55_DRV      GLB_REG_GPIO_55_DRV
+#define GLB_REG_GPIO_55_DRV_POS  (2U)
+#define GLB_REG_GPIO_55_DRV_LEN  (2U)
+#define GLB_REG_GPIO_55_DRV_MSK  (((1U << GLB_REG_GPIO_55_DRV_LEN) - 1) << GLB_REG_GPIO_55_DRV_POS)
+#define GLB_REG_GPIO_55_DRV_UMSK (~(((1U << GLB_REG_GPIO_55_DRV_LEN) - 1) << GLB_REG_GPIO_55_DRV_POS))
+#define GLB_REG_GPIO_55_PU       GLB_REG_GPIO_55_PU
+#define GLB_REG_GPIO_55_PU_POS   (4U)
+#define GLB_REG_GPIO_55_PU_LEN   (1U)
+#define GLB_REG_GPIO_55_PU_MSK   (((1U << GLB_REG_GPIO_55_PU_LEN) - 1) << GLB_REG_GPIO_55_PU_POS)
+#define GLB_REG_GPIO_55_PU_UMSK  (~(((1U << GLB_REG_GPIO_55_PU_LEN) - 1) << GLB_REG_GPIO_55_PU_POS))
+#define GLB_REG_GPIO_55_PD       GLB_REG_GPIO_55_PD
+#define GLB_REG_GPIO_55_PD_POS   (5U)
+#define GLB_REG_GPIO_55_PD_LEN   (1U)
+#define GLB_REG_GPIO_55_PD_MSK   (((1U << GLB_REG_GPIO_55_PD_LEN) - 1) << GLB_REG_GPIO_55_PD_POS)
+#define GLB_REG_GPIO_55_PD_UMSK  (~(((1U << GLB_REG_GPIO_55_PD_LEN) - 1) << GLB_REG_GPIO_55_PD_POS))
+
+/* 0x9A4 : gpio_cfg56 */
+#define GLB_GPIO_CFG56_OFFSET (0x9A4)
+
+/* 0x9A8 : gpio_cfg57 */
+#define GLB_GPIO_CFG57_OFFSET (0x9A8)
+
+/* 0x9AC : gpio_cfg58 */
+#define GLB_GPIO_CFG58_OFFSET (0x9AC)
+
+/* 0x9B0 : gpio_cfg59 */
+#define GLB_GPIO_CFG59_OFFSET (0x9B0)
+
+/* 0x9B4 : gpio_cfg60 */
+#define GLB_GPIO_CFG60_OFFSET (0x9B4)
+
+/* 0x9B8 : gpio_cfg61 */
+#define GLB_GPIO_CFG61_OFFSET (0x9B8)
+
+/* 0x9BC : gpio_cfg62 */
+#define GLB_GPIO_CFG62_OFFSET (0x9BC)
+
+/* 0x9C0 : gpio_cfg63 */
+#define GLB_GPIO_CFG63_OFFSET (0x9C0)
+
+/* 0xAC4 : gpio_cfg128 */
+#define GLB_GPIO_CFG128_OFFSET  (0xAC4)
+#define GLB_REG2_GPIO_0_I       GLB_REG2_GPIO_0_I
+#define GLB_REG2_GPIO_0_I_POS   (0U)
+#define GLB_REG2_GPIO_0_I_LEN   (1U)
+#define GLB_REG2_GPIO_0_I_MSK   (((1U << GLB_REG2_GPIO_0_I_LEN) - 1) << GLB_REG2_GPIO_0_I_POS)
+#define GLB_REG2_GPIO_0_I_UMSK  (~(((1U << GLB_REG2_GPIO_0_I_LEN) - 1) << GLB_REG2_GPIO_0_I_POS))
+#define GLB_REG2_GPIO_1_I       GLB_REG2_GPIO_1_I
+#define GLB_REG2_GPIO_1_I_POS   (1U)
+#define GLB_REG2_GPIO_1_I_LEN   (1U)
+#define GLB_REG2_GPIO_1_I_MSK   (((1U << GLB_REG2_GPIO_1_I_LEN) - 1) << GLB_REG2_GPIO_1_I_POS)
+#define GLB_REG2_GPIO_1_I_UMSK  (~(((1U << GLB_REG2_GPIO_1_I_LEN) - 1) << GLB_REG2_GPIO_1_I_POS))
+#define GLB_REG2_GPIO_2_I       GLB_REG2_GPIO_2_I
+#define GLB_REG2_GPIO_2_I_POS   (2U)
+#define GLB_REG2_GPIO_2_I_LEN   (1U)
+#define GLB_REG2_GPIO_2_I_MSK   (((1U << GLB_REG2_GPIO_2_I_LEN) - 1) << GLB_REG2_GPIO_2_I_POS)
+#define GLB_REG2_GPIO_2_I_UMSK  (~(((1U << GLB_REG2_GPIO_2_I_LEN) - 1) << GLB_REG2_GPIO_2_I_POS))
+#define GLB_REG2_GPIO_3_I       GLB_REG2_GPIO_3_I
+#define GLB_REG2_GPIO_3_I_POS   (3U)
+#define GLB_REG2_GPIO_3_I_LEN   (1U)
+#define GLB_REG2_GPIO_3_I_MSK   (((1U << GLB_REG2_GPIO_3_I_LEN) - 1) << GLB_REG2_GPIO_3_I_POS)
+#define GLB_REG2_GPIO_3_I_UMSK  (~(((1U << GLB_REG2_GPIO_3_I_LEN) - 1) << GLB_REG2_GPIO_3_I_POS))
+#define GLB_REG2_GPIO_4_I       GLB_REG2_GPIO_4_I
+#define GLB_REG2_GPIO_4_I_POS   (4U)
+#define GLB_REG2_GPIO_4_I_LEN   (1U)
+#define GLB_REG2_GPIO_4_I_MSK   (((1U << GLB_REG2_GPIO_4_I_LEN) - 1) << GLB_REG2_GPIO_4_I_POS)
+#define GLB_REG2_GPIO_4_I_UMSK  (~(((1U << GLB_REG2_GPIO_4_I_LEN) - 1) << GLB_REG2_GPIO_4_I_POS))
+#define GLB_REG2_GPIO_5_I       GLB_REG2_GPIO_5_I
+#define GLB_REG2_GPIO_5_I_POS   (5U)
+#define GLB_REG2_GPIO_5_I_LEN   (1U)
+#define GLB_REG2_GPIO_5_I_MSK   (((1U << GLB_REG2_GPIO_5_I_LEN) - 1) << GLB_REG2_GPIO_5_I_POS)
+#define GLB_REG2_GPIO_5_I_UMSK  (~(((1U << GLB_REG2_GPIO_5_I_LEN) - 1) << GLB_REG2_GPIO_5_I_POS))
+#define GLB_REG2_GPIO_6_I       GLB_REG2_GPIO_6_I
+#define GLB_REG2_GPIO_6_I_POS   (6U)
+#define GLB_REG2_GPIO_6_I_LEN   (1U)
+#define GLB_REG2_GPIO_6_I_MSK   (((1U << GLB_REG2_GPIO_6_I_LEN) - 1) << GLB_REG2_GPIO_6_I_POS)
+#define GLB_REG2_GPIO_6_I_UMSK  (~(((1U << GLB_REG2_GPIO_6_I_LEN) - 1) << GLB_REG2_GPIO_6_I_POS))
+#define GLB_REG2_GPIO_7_I       GLB_REG2_GPIO_7_I
+#define GLB_REG2_GPIO_7_I_POS   (7U)
+#define GLB_REG2_GPIO_7_I_LEN   (1U)
+#define GLB_REG2_GPIO_7_I_MSK   (((1U << GLB_REG2_GPIO_7_I_LEN) - 1) << GLB_REG2_GPIO_7_I_POS)
+#define GLB_REG2_GPIO_7_I_UMSK  (~(((1U << GLB_REG2_GPIO_7_I_LEN) - 1) << GLB_REG2_GPIO_7_I_POS))
+#define GLB_REG2_GPIO_8_I       GLB_REG2_GPIO_8_I
+#define GLB_REG2_GPIO_8_I_POS   (8U)
+#define GLB_REG2_GPIO_8_I_LEN   (1U)
+#define GLB_REG2_GPIO_8_I_MSK   (((1U << GLB_REG2_GPIO_8_I_LEN) - 1) << GLB_REG2_GPIO_8_I_POS)
+#define GLB_REG2_GPIO_8_I_UMSK  (~(((1U << GLB_REG2_GPIO_8_I_LEN) - 1) << GLB_REG2_GPIO_8_I_POS))
+#define GLB_REG2_GPIO_9_I       GLB_REG2_GPIO_9_I
+#define GLB_REG2_GPIO_9_I_POS   (9U)
+#define GLB_REG2_GPIO_9_I_LEN   (1U)
+#define GLB_REG2_GPIO_9_I_MSK   (((1U << GLB_REG2_GPIO_9_I_LEN) - 1) << GLB_REG2_GPIO_9_I_POS)
+#define GLB_REG2_GPIO_9_I_UMSK  (~(((1U << GLB_REG2_GPIO_9_I_LEN) - 1) << GLB_REG2_GPIO_9_I_POS))
+#define GLB_REG2_GPIO_10_I      GLB_REG2_GPIO_10_I
+#define GLB_REG2_GPIO_10_I_POS  (10U)
+#define GLB_REG2_GPIO_10_I_LEN  (1U)
+#define GLB_REG2_GPIO_10_I_MSK  (((1U << GLB_REG2_GPIO_10_I_LEN) - 1) << GLB_REG2_GPIO_10_I_POS)
+#define GLB_REG2_GPIO_10_I_UMSK (~(((1U << GLB_REG2_GPIO_10_I_LEN) - 1) << GLB_REG2_GPIO_10_I_POS))
+#define GLB_REG2_GPIO_11_I      GLB_REG2_GPIO_11_I
+#define GLB_REG2_GPIO_11_I_POS  (11U)
+#define GLB_REG2_GPIO_11_I_LEN  (1U)
+#define GLB_REG2_GPIO_11_I_MSK  (((1U << GLB_REG2_GPIO_11_I_LEN) - 1) << GLB_REG2_GPIO_11_I_POS)
+#define GLB_REG2_GPIO_11_I_UMSK (~(((1U << GLB_REG2_GPIO_11_I_LEN) - 1) << GLB_REG2_GPIO_11_I_POS))
+#define GLB_REG2_GPIO_12_I      GLB_REG2_GPIO_12_I
+#define GLB_REG2_GPIO_12_I_POS  (12U)
+#define GLB_REG2_GPIO_12_I_LEN  (1U)
+#define GLB_REG2_GPIO_12_I_MSK  (((1U << GLB_REG2_GPIO_12_I_LEN) - 1) << GLB_REG2_GPIO_12_I_POS)
+#define GLB_REG2_GPIO_12_I_UMSK (~(((1U << GLB_REG2_GPIO_12_I_LEN) - 1) << GLB_REG2_GPIO_12_I_POS))
+#define GLB_REG2_GPIO_13_I      GLB_REG2_GPIO_13_I
+#define GLB_REG2_GPIO_13_I_POS  (13U)
+#define GLB_REG2_GPIO_13_I_LEN  (1U)
+#define GLB_REG2_GPIO_13_I_MSK  (((1U << GLB_REG2_GPIO_13_I_LEN) - 1) << GLB_REG2_GPIO_13_I_POS)
+#define GLB_REG2_GPIO_13_I_UMSK (~(((1U << GLB_REG2_GPIO_13_I_LEN) - 1) << GLB_REG2_GPIO_13_I_POS))
+#define GLB_REG2_GPIO_14_I      GLB_REG2_GPIO_14_I
+#define GLB_REG2_GPIO_14_I_POS  (14U)
+#define GLB_REG2_GPIO_14_I_LEN  (1U)
+#define GLB_REG2_GPIO_14_I_MSK  (((1U << GLB_REG2_GPIO_14_I_LEN) - 1) << GLB_REG2_GPIO_14_I_POS)
+#define GLB_REG2_GPIO_14_I_UMSK (~(((1U << GLB_REG2_GPIO_14_I_LEN) - 1) << GLB_REG2_GPIO_14_I_POS))
+#define GLB_REG2_GPIO_15_I      GLB_REG2_GPIO_15_I
+#define GLB_REG2_GPIO_15_I_POS  (15U)
+#define GLB_REG2_GPIO_15_I_LEN  (1U)
+#define GLB_REG2_GPIO_15_I_MSK  (((1U << GLB_REG2_GPIO_15_I_LEN) - 1) << GLB_REG2_GPIO_15_I_POS)
+#define GLB_REG2_GPIO_15_I_UMSK (~(((1U << GLB_REG2_GPIO_15_I_LEN) - 1) << GLB_REG2_GPIO_15_I_POS))
+#define GLB_REG2_GPIO_16_I      GLB_REG2_GPIO_16_I
+#define GLB_REG2_GPIO_16_I_POS  (16U)
+#define GLB_REG2_GPIO_16_I_LEN  (1U)
+#define GLB_REG2_GPIO_16_I_MSK  (((1U << GLB_REG2_GPIO_16_I_LEN) - 1) << GLB_REG2_GPIO_16_I_POS)
+#define GLB_REG2_GPIO_16_I_UMSK (~(((1U << GLB_REG2_GPIO_16_I_LEN) - 1) << GLB_REG2_GPIO_16_I_POS))
+#define GLB_REG2_GPIO_17_I      GLB_REG2_GPIO_17_I
+#define GLB_REG2_GPIO_17_I_POS  (17U)
+#define GLB_REG2_GPIO_17_I_LEN  (1U)
+#define GLB_REG2_GPIO_17_I_MSK  (((1U << GLB_REG2_GPIO_17_I_LEN) - 1) << GLB_REG2_GPIO_17_I_POS)
+#define GLB_REG2_GPIO_17_I_UMSK (~(((1U << GLB_REG2_GPIO_17_I_LEN) - 1) << GLB_REG2_GPIO_17_I_POS))
+#define GLB_REG2_GPIO_18_I      GLB_REG2_GPIO_18_I
+#define GLB_REG2_GPIO_18_I_POS  (18U)
+#define GLB_REG2_GPIO_18_I_LEN  (1U)
+#define GLB_REG2_GPIO_18_I_MSK  (((1U << GLB_REG2_GPIO_18_I_LEN) - 1) << GLB_REG2_GPIO_18_I_POS)
+#define GLB_REG2_GPIO_18_I_UMSK (~(((1U << GLB_REG2_GPIO_18_I_LEN) - 1) << GLB_REG2_GPIO_18_I_POS))
+#define GLB_REG2_GPIO_19_I      GLB_REG2_GPIO_19_I
+#define GLB_REG2_GPIO_19_I_POS  (19U)
+#define GLB_REG2_GPIO_19_I_LEN  (1U)
+#define GLB_REG2_GPIO_19_I_MSK  (((1U << GLB_REG2_GPIO_19_I_LEN) - 1) << GLB_REG2_GPIO_19_I_POS)
+#define GLB_REG2_GPIO_19_I_UMSK (~(((1U << GLB_REG2_GPIO_19_I_LEN) - 1) << GLB_REG2_GPIO_19_I_POS))
+#define GLB_REG2_GPIO_20_I      GLB_REG2_GPIO_20_I
+#define GLB_REG2_GPIO_20_I_POS  (20U)
+#define GLB_REG2_GPIO_20_I_LEN  (1U)
+#define GLB_REG2_GPIO_20_I_MSK  (((1U << GLB_REG2_GPIO_20_I_LEN) - 1) << GLB_REG2_GPIO_20_I_POS)
+#define GLB_REG2_GPIO_20_I_UMSK (~(((1U << GLB_REG2_GPIO_20_I_LEN) - 1) << GLB_REG2_GPIO_20_I_POS))
+#define GLB_REG2_GPIO_21_I      GLB_REG2_GPIO_21_I
+#define GLB_REG2_GPIO_21_I_POS  (21U)
+#define GLB_REG2_GPIO_21_I_LEN  (1U)
+#define GLB_REG2_GPIO_21_I_MSK  (((1U << GLB_REG2_GPIO_21_I_LEN) - 1) << GLB_REG2_GPIO_21_I_POS)
+#define GLB_REG2_GPIO_21_I_UMSK (~(((1U << GLB_REG2_GPIO_21_I_LEN) - 1) << GLB_REG2_GPIO_21_I_POS))
+#define GLB_REG2_GPIO_22_I      GLB_REG2_GPIO_22_I
+#define GLB_REG2_GPIO_22_I_POS  (22U)
+#define GLB_REG2_GPIO_22_I_LEN  (1U)
+#define GLB_REG2_GPIO_22_I_MSK  (((1U << GLB_REG2_GPIO_22_I_LEN) - 1) << GLB_REG2_GPIO_22_I_POS)
+#define GLB_REG2_GPIO_22_I_UMSK (~(((1U << GLB_REG2_GPIO_22_I_LEN) - 1) << GLB_REG2_GPIO_22_I_POS))
+#define GLB_REG2_GPIO_23_I      GLB_REG2_GPIO_23_I
+#define GLB_REG2_GPIO_23_I_POS  (23U)
+#define GLB_REG2_GPIO_23_I_LEN  (1U)
+#define GLB_REG2_GPIO_23_I_MSK  (((1U << GLB_REG2_GPIO_23_I_LEN) - 1) << GLB_REG2_GPIO_23_I_POS)
+#define GLB_REG2_GPIO_23_I_UMSK (~(((1U << GLB_REG2_GPIO_23_I_LEN) - 1) << GLB_REG2_GPIO_23_I_POS))
+#define GLB_REG2_GPIO_24_I      GLB_REG2_GPIO_24_I
+#define GLB_REG2_GPIO_24_I_POS  (24U)
+#define GLB_REG2_GPIO_24_I_LEN  (1U)
+#define GLB_REG2_GPIO_24_I_MSK  (((1U << GLB_REG2_GPIO_24_I_LEN) - 1) << GLB_REG2_GPIO_24_I_POS)
+#define GLB_REG2_GPIO_24_I_UMSK (~(((1U << GLB_REG2_GPIO_24_I_LEN) - 1) << GLB_REG2_GPIO_24_I_POS))
+#define GLB_REG2_GPIO_25_I      GLB_REG2_GPIO_25_I
+#define GLB_REG2_GPIO_25_I_POS  (25U)
+#define GLB_REG2_GPIO_25_I_LEN  (1U)
+#define GLB_REG2_GPIO_25_I_MSK  (((1U << GLB_REG2_GPIO_25_I_LEN) - 1) << GLB_REG2_GPIO_25_I_POS)
+#define GLB_REG2_GPIO_25_I_UMSK (~(((1U << GLB_REG2_GPIO_25_I_LEN) - 1) << GLB_REG2_GPIO_25_I_POS))
+#define GLB_REG2_GPIO_26_I      GLB_REG2_GPIO_26_I
+#define GLB_REG2_GPIO_26_I_POS  (26U)
+#define GLB_REG2_GPIO_26_I_LEN  (1U)
+#define GLB_REG2_GPIO_26_I_MSK  (((1U << GLB_REG2_GPIO_26_I_LEN) - 1) << GLB_REG2_GPIO_26_I_POS)
+#define GLB_REG2_GPIO_26_I_UMSK (~(((1U << GLB_REG2_GPIO_26_I_LEN) - 1) << GLB_REG2_GPIO_26_I_POS))
+#define GLB_REG2_GPIO_27_I      GLB_REG2_GPIO_27_I
+#define GLB_REG2_GPIO_27_I_POS  (27U)
+#define GLB_REG2_GPIO_27_I_LEN  (1U)
+#define GLB_REG2_GPIO_27_I_MSK  (((1U << GLB_REG2_GPIO_27_I_LEN) - 1) << GLB_REG2_GPIO_27_I_POS)
+#define GLB_REG2_GPIO_27_I_UMSK (~(((1U << GLB_REG2_GPIO_27_I_LEN) - 1) << GLB_REG2_GPIO_27_I_POS))
+#define GLB_REG2_GPIO_28_I      GLB_REG2_GPIO_28_I
+#define GLB_REG2_GPIO_28_I_POS  (28U)
+#define GLB_REG2_GPIO_28_I_LEN  (1U)
+#define GLB_REG2_GPIO_28_I_MSK  (((1U << GLB_REG2_GPIO_28_I_LEN) - 1) << GLB_REG2_GPIO_28_I_POS)
+#define GLB_REG2_GPIO_28_I_UMSK (~(((1U << GLB_REG2_GPIO_28_I_LEN) - 1) << GLB_REG2_GPIO_28_I_POS))
+#define GLB_REG2_GPIO_29_I      GLB_REG2_GPIO_29_I
+#define GLB_REG2_GPIO_29_I_POS  (29U)
+#define GLB_REG2_GPIO_29_I_LEN  (1U)
+#define GLB_REG2_GPIO_29_I_MSK  (((1U << GLB_REG2_GPIO_29_I_LEN) - 1) << GLB_REG2_GPIO_29_I_POS)
+#define GLB_REG2_GPIO_29_I_UMSK (~(((1U << GLB_REG2_GPIO_29_I_LEN) - 1) << GLB_REG2_GPIO_29_I_POS))
+#define GLB_REG2_GPIO_30_I      GLB_REG2_GPIO_30_I
+#define GLB_REG2_GPIO_30_I_POS  (30U)
+#define GLB_REG2_GPIO_30_I_LEN  (1U)
+#define GLB_REG2_GPIO_30_I_MSK  (((1U << GLB_REG2_GPIO_30_I_LEN) - 1) << GLB_REG2_GPIO_30_I_POS)
+#define GLB_REG2_GPIO_30_I_UMSK (~(((1U << GLB_REG2_GPIO_30_I_LEN) - 1) << GLB_REG2_GPIO_30_I_POS))
+#define GLB_REG2_GPIO_31_I      GLB_REG2_GPIO_31_I
+#define GLB_REG2_GPIO_31_I_POS  (31U)
+#define GLB_REG2_GPIO_31_I_LEN  (1U)
+#define GLB_REG2_GPIO_31_I_MSK  (((1U << GLB_REG2_GPIO_31_I_LEN) - 1) << GLB_REG2_GPIO_31_I_POS)
+#define GLB_REG2_GPIO_31_I_UMSK (~(((1U << GLB_REG2_GPIO_31_I_LEN) - 1) << GLB_REG2_GPIO_31_I_POS))
+
+/* 0xAC8 : gpio_cfg129 */
+#define GLB_GPIO_CFG129_OFFSET  (0xAC8)
+#define GLB_REG2_GPIO_32_I      GLB_REG2_GPIO_32_I
+#define GLB_REG2_GPIO_32_I_POS  (0U)
+#define GLB_REG2_GPIO_32_I_LEN  (1U)
+#define GLB_REG2_GPIO_32_I_MSK  (((1U << GLB_REG2_GPIO_32_I_LEN) - 1) << GLB_REG2_GPIO_32_I_POS)
+#define GLB_REG2_GPIO_32_I_UMSK (~(((1U << GLB_REG2_GPIO_32_I_LEN) - 1) << GLB_REG2_GPIO_32_I_POS))
+#define GLB_REG2_GPIO_33_I      GLB_REG2_GPIO_33_I
+#define GLB_REG2_GPIO_33_I_POS  (1U)
+#define GLB_REG2_GPIO_33_I_LEN  (1U)
+#define GLB_REG2_GPIO_33_I_MSK  (((1U << GLB_REG2_GPIO_33_I_LEN) - 1) << GLB_REG2_GPIO_33_I_POS)
+#define GLB_REG2_GPIO_33_I_UMSK (~(((1U << GLB_REG2_GPIO_33_I_LEN) - 1) << GLB_REG2_GPIO_33_I_POS))
+#define GLB_REG2_GPIO_34_I      GLB_REG2_GPIO_34_I
+#define GLB_REG2_GPIO_34_I_POS  (2U)
+#define GLB_REG2_GPIO_34_I_LEN  (1U)
+#define GLB_REG2_GPIO_34_I_MSK  (((1U << GLB_REG2_GPIO_34_I_LEN) - 1) << GLB_REG2_GPIO_34_I_POS)
+#define GLB_REG2_GPIO_34_I_UMSK (~(((1U << GLB_REG2_GPIO_34_I_LEN) - 1) << GLB_REG2_GPIO_34_I_POS))
+
+/* 0xAE4 : gpio_cfg136 */
+#define GLB_GPIO_CFG136_OFFSET  (0xAE4)
+#define GLB_REG2_GPIO_0_O       GLB_REG2_GPIO_0_O
+#define GLB_REG2_GPIO_0_O_POS   (0U)
+#define GLB_REG2_GPIO_0_O_LEN   (1U)
+#define GLB_REG2_GPIO_0_O_MSK   (((1U << GLB_REG2_GPIO_0_O_LEN) - 1) << GLB_REG2_GPIO_0_O_POS)
+#define GLB_REG2_GPIO_0_O_UMSK  (~(((1U << GLB_REG2_GPIO_0_O_LEN) - 1) << GLB_REG2_GPIO_0_O_POS))
+#define GLB_REG2_GPIO_1_O       GLB_REG2_GPIO_1_O
+#define GLB_REG2_GPIO_1_O_POS   (1U)
+#define GLB_REG2_GPIO_1_O_LEN   (1U)
+#define GLB_REG2_GPIO_1_O_MSK   (((1U << GLB_REG2_GPIO_1_O_LEN) - 1) << GLB_REG2_GPIO_1_O_POS)
+#define GLB_REG2_GPIO_1_O_UMSK  (~(((1U << GLB_REG2_GPIO_1_O_LEN) - 1) << GLB_REG2_GPIO_1_O_POS))
+#define GLB_REG2_GPIO_2_O       GLB_REG2_GPIO_2_O
+#define GLB_REG2_GPIO_2_O_POS   (2U)
+#define GLB_REG2_GPIO_2_O_LEN   (1U)
+#define GLB_REG2_GPIO_2_O_MSK   (((1U << GLB_REG2_GPIO_2_O_LEN) - 1) << GLB_REG2_GPIO_2_O_POS)
+#define GLB_REG2_GPIO_2_O_UMSK  (~(((1U << GLB_REG2_GPIO_2_O_LEN) - 1) << GLB_REG2_GPIO_2_O_POS))
+#define GLB_REG2_GPIO_3_O       GLB_REG2_GPIO_3_O
+#define GLB_REG2_GPIO_3_O_POS   (3U)
+#define GLB_REG2_GPIO_3_O_LEN   (1U)
+#define GLB_REG2_GPIO_3_O_MSK   (((1U << GLB_REG2_GPIO_3_O_LEN) - 1) << GLB_REG2_GPIO_3_O_POS)
+#define GLB_REG2_GPIO_3_O_UMSK  (~(((1U << GLB_REG2_GPIO_3_O_LEN) - 1) << GLB_REG2_GPIO_3_O_POS))
+#define GLB_REG2_GPIO_4_O       GLB_REG2_GPIO_4_O
+#define GLB_REG2_GPIO_4_O_POS   (4U)
+#define GLB_REG2_GPIO_4_O_LEN   (1U)
+#define GLB_REG2_GPIO_4_O_MSK   (((1U << GLB_REG2_GPIO_4_O_LEN) - 1) << GLB_REG2_GPIO_4_O_POS)
+#define GLB_REG2_GPIO_4_O_UMSK  (~(((1U << GLB_REG2_GPIO_4_O_LEN) - 1) << GLB_REG2_GPIO_4_O_POS))
+#define GLB_REG2_GPIO_5_O       GLB_REG2_GPIO_5_O
+#define GLB_REG2_GPIO_5_O_POS   (5U)
+#define GLB_REG2_GPIO_5_O_LEN   (1U)
+#define GLB_REG2_GPIO_5_O_MSK   (((1U << GLB_REG2_GPIO_5_O_LEN) - 1) << GLB_REG2_GPIO_5_O_POS)
+#define GLB_REG2_GPIO_5_O_UMSK  (~(((1U << GLB_REG2_GPIO_5_O_LEN) - 1) << GLB_REG2_GPIO_5_O_POS))
+#define GLB_REG2_GPIO_6_O       GLB_REG2_GPIO_6_O
+#define GLB_REG2_GPIO_6_O_POS   (6U)
+#define GLB_REG2_GPIO_6_O_LEN   (1U)
+#define GLB_REG2_GPIO_6_O_MSK   (((1U << GLB_REG2_GPIO_6_O_LEN) - 1) << GLB_REG2_GPIO_6_O_POS)
+#define GLB_REG2_GPIO_6_O_UMSK  (~(((1U << GLB_REG2_GPIO_6_O_LEN) - 1) << GLB_REG2_GPIO_6_O_POS))
+#define GLB_REG2_GPIO_7_O       GLB_REG2_GPIO_7_O
+#define GLB_REG2_GPIO_7_O_POS   (7U)
+#define GLB_REG2_GPIO_7_O_LEN   (1U)
+#define GLB_REG2_GPIO_7_O_MSK   (((1U << GLB_REG2_GPIO_7_O_LEN) - 1) << GLB_REG2_GPIO_7_O_POS)
+#define GLB_REG2_GPIO_7_O_UMSK  (~(((1U << GLB_REG2_GPIO_7_O_LEN) - 1) << GLB_REG2_GPIO_7_O_POS))
+#define GLB_REG2_GPIO_8_O       GLB_REG2_GPIO_8_O
+#define GLB_REG2_GPIO_8_O_POS   (8U)
+#define GLB_REG2_GPIO_8_O_LEN   (1U)
+#define GLB_REG2_GPIO_8_O_MSK   (((1U << GLB_REG2_GPIO_8_O_LEN) - 1) << GLB_REG2_GPIO_8_O_POS)
+#define GLB_REG2_GPIO_8_O_UMSK  (~(((1U << GLB_REG2_GPIO_8_O_LEN) - 1) << GLB_REG2_GPIO_8_O_POS))
+#define GLB_REG2_GPIO_9_O       GLB_REG2_GPIO_9_O
+#define GLB_REG2_GPIO_9_O_POS   (9U)
+#define GLB_REG2_GPIO_9_O_LEN   (1U)
+#define GLB_REG2_GPIO_9_O_MSK   (((1U << GLB_REG2_GPIO_9_O_LEN) - 1) << GLB_REG2_GPIO_9_O_POS)
+#define GLB_REG2_GPIO_9_O_UMSK  (~(((1U << GLB_REG2_GPIO_9_O_LEN) - 1) << GLB_REG2_GPIO_9_O_POS))
+#define GLB_REG2_GPIO_10_O      GLB_REG2_GPIO_10_O
+#define GLB_REG2_GPIO_10_O_POS  (10U)
+#define GLB_REG2_GPIO_10_O_LEN  (1U)
+#define GLB_REG2_GPIO_10_O_MSK  (((1U << GLB_REG2_GPIO_10_O_LEN) - 1) << GLB_REG2_GPIO_10_O_POS)
+#define GLB_REG2_GPIO_10_O_UMSK (~(((1U << GLB_REG2_GPIO_10_O_LEN) - 1) << GLB_REG2_GPIO_10_O_POS))
+#define GLB_REG2_GPIO_11_O      GLB_REG2_GPIO_11_O
+#define GLB_REG2_GPIO_11_O_POS  (11U)
+#define GLB_REG2_GPIO_11_O_LEN  (1U)
+#define GLB_REG2_GPIO_11_O_MSK  (((1U << GLB_REG2_GPIO_11_O_LEN) - 1) << GLB_REG2_GPIO_11_O_POS)
+#define GLB_REG2_GPIO_11_O_UMSK (~(((1U << GLB_REG2_GPIO_11_O_LEN) - 1) << GLB_REG2_GPIO_11_O_POS))
+#define GLB_REG2_GPIO_12_O      GLB_REG2_GPIO_12_O
+#define GLB_REG2_GPIO_12_O_POS  (12U)
+#define GLB_REG2_GPIO_12_O_LEN  (1U)
+#define GLB_REG2_GPIO_12_O_MSK  (((1U << GLB_REG2_GPIO_12_O_LEN) - 1) << GLB_REG2_GPIO_12_O_POS)
+#define GLB_REG2_GPIO_12_O_UMSK (~(((1U << GLB_REG2_GPIO_12_O_LEN) - 1) << GLB_REG2_GPIO_12_O_POS))
+#define GLB_REG2_GPIO_13_O      GLB_REG2_GPIO_13_O
+#define GLB_REG2_GPIO_13_O_POS  (13U)
+#define GLB_REG2_GPIO_13_O_LEN  (1U)
+#define GLB_REG2_GPIO_13_O_MSK  (((1U << GLB_REG2_GPIO_13_O_LEN) - 1) << GLB_REG2_GPIO_13_O_POS)
+#define GLB_REG2_GPIO_13_O_UMSK (~(((1U << GLB_REG2_GPIO_13_O_LEN) - 1) << GLB_REG2_GPIO_13_O_POS))
+#define GLB_REG2_GPIO_14_O      GLB_REG2_GPIO_14_O
+#define GLB_REG2_GPIO_14_O_POS  (14U)
+#define GLB_REG2_GPIO_14_O_LEN  (1U)
+#define GLB_REG2_GPIO_14_O_MSK  (((1U << GLB_REG2_GPIO_14_O_LEN) - 1) << GLB_REG2_GPIO_14_O_POS)
+#define GLB_REG2_GPIO_14_O_UMSK (~(((1U << GLB_REG2_GPIO_14_O_LEN) - 1) << GLB_REG2_GPIO_14_O_POS))
+#define GLB_REG2_GPIO_15_O      GLB_REG2_GPIO_15_O
+#define GLB_REG2_GPIO_15_O_POS  (15U)
+#define GLB_REG2_GPIO_15_O_LEN  (1U)
+#define GLB_REG2_GPIO_15_O_MSK  (((1U << GLB_REG2_GPIO_15_O_LEN) - 1) << GLB_REG2_GPIO_15_O_POS)
+#define GLB_REG2_GPIO_15_O_UMSK (~(((1U << GLB_REG2_GPIO_15_O_LEN) - 1) << GLB_REG2_GPIO_15_O_POS))
+#define GLB_REG2_GPIO_16_O      GLB_REG2_GPIO_16_O
+#define GLB_REG2_GPIO_16_O_POS  (16U)
+#define GLB_REG2_GPIO_16_O_LEN  (1U)
+#define GLB_REG2_GPIO_16_O_MSK  (((1U << GLB_REG2_GPIO_16_O_LEN) - 1) << GLB_REG2_GPIO_16_O_POS)
+#define GLB_REG2_GPIO_16_O_UMSK (~(((1U << GLB_REG2_GPIO_16_O_LEN) - 1) << GLB_REG2_GPIO_16_O_POS))
+#define GLB_REG2_GPIO_17_O      GLB_REG2_GPIO_17_O
+#define GLB_REG2_GPIO_17_O_POS  (17U)
+#define GLB_REG2_GPIO_17_O_LEN  (1U)
+#define GLB_REG2_GPIO_17_O_MSK  (((1U << GLB_REG2_GPIO_17_O_LEN) - 1) << GLB_REG2_GPIO_17_O_POS)
+#define GLB_REG2_GPIO_17_O_UMSK (~(((1U << GLB_REG2_GPIO_17_O_LEN) - 1) << GLB_REG2_GPIO_17_O_POS))
+#define GLB_REG2_GPIO_18_O      GLB_REG2_GPIO_18_O
+#define GLB_REG2_GPIO_18_O_POS  (18U)
+#define GLB_REG2_GPIO_18_O_LEN  (1U)
+#define GLB_REG2_GPIO_18_O_MSK  (((1U << GLB_REG2_GPIO_18_O_LEN) - 1) << GLB_REG2_GPIO_18_O_POS)
+#define GLB_REG2_GPIO_18_O_UMSK (~(((1U << GLB_REG2_GPIO_18_O_LEN) - 1) << GLB_REG2_GPIO_18_O_POS))
+#define GLB_REG2_GPIO_19_O      GLB_REG2_GPIO_19_O
+#define GLB_REG2_GPIO_19_O_POS  (19U)
+#define GLB_REG2_GPIO_19_O_LEN  (1U)
+#define GLB_REG2_GPIO_19_O_MSK  (((1U << GLB_REG2_GPIO_19_O_LEN) - 1) << GLB_REG2_GPIO_19_O_POS)
+#define GLB_REG2_GPIO_19_O_UMSK (~(((1U << GLB_REG2_GPIO_19_O_LEN) - 1) << GLB_REG2_GPIO_19_O_POS))
+#define GLB_REG2_GPIO_20_O      GLB_REG2_GPIO_20_O
+#define GLB_REG2_GPIO_20_O_POS  (20U)
+#define GLB_REG2_GPIO_20_O_LEN  (1U)
+#define GLB_REG2_GPIO_20_O_MSK  (((1U << GLB_REG2_GPIO_20_O_LEN) - 1) << GLB_REG2_GPIO_20_O_POS)
+#define GLB_REG2_GPIO_20_O_UMSK (~(((1U << GLB_REG2_GPIO_20_O_LEN) - 1) << GLB_REG2_GPIO_20_O_POS))
+#define GLB_REG2_GPIO_21_O      GLB_REG2_GPIO_21_O
+#define GLB_REG2_GPIO_21_O_POS  (21U)
+#define GLB_REG2_GPIO_21_O_LEN  (1U)
+#define GLB_REG2_GPIO_21_O_MSK  (((1U << GLB_REG2_GPIO_21_O_LEN) - 1) << GLB_REG2_GPIO_21_O_POS)
+#define GLB_REG2_GPIO_21_O_UMSK (~(((1U << GLB_REG2_GPIO_21_O_LEN) - 1) << GLB_REG2_GPIO_21_O_POS))
+#define GLB_REG2_GPIO_22_O      GLB_REG2_GPIO_22_O
+#define GLB_REG2_GPIO_22_O_POS  (22U)
+#define GLB_REG2_GPIO_22_O_LEN  (1U)
+#define GLB_REG2_GPIO_22_O_MSK  (((1U << GLB_REG2_GPIO_22_O_LEN) - 1) << GLB_REG2_GPIO_22_O_POS)
+#define GLB_REG2_GPIO_22_O_UMSK (~(((1U << GLB_REG2_GPIO_22_O_LEN) - 1) << GLB_REG2_GPIO_22_O_POS))
+#define GLB_REG2_GPIO_23_O      GLB_REG2_GPIO_23_O
+#define GLB_REG2_GPIO_23_O_POS  (23U)
+#define GLB_REG2_GPIO_23_O_LEN  (1U)
+#define GLB_REG2_GPIO_23_O_MSK  (((1U << GLB_REG2_GPIO_23_O_LEN) - 1) << GLB_REG2_GPIO_23_O_POS)
+#define GLB_REG2_GPIO_23_O_UMSK (~(((1U << GLB_REG2_GPIO_23_O_LEN) - 1) << GLB_REG2_GPIO_23_O_POS))
+#define GLB_REG2_GPIO_24_O      GLB_REG2_GPIO_24_O
+#define GLB_REG2_GPIO_24_O_POS  (24U)
+#define GLB_REG2_GPIO_24_O_LEN  (1U)
+#define GLB_REG2_GPIO_24_O_MSK  (((1U << GLB_REG2_GPIO_24_O_LEN) - 1) << GLB_REG2_GPIO_24_O_POS)
+#define GLB_REG2_GPIO_24_O_UMSK (~(((1U << GLB_REG2_GPIO_24_O_LEN) - 1) << GLB_REG2_GPIO_24_O_POS))
+#define GLB_REG2_GPIO_25_O      GLB_REG2_GPIO_25_O
+#define GLB_REG2_GPIO_25_O_POS  (25U)
+#define GLB_REG2_GPIO_25_O_LEN  (1U)
+#define GLB_REG2_GPIO_25_O_MSK  (((1U << GLB_REG2_GPIO_25_O_LEN) - 1) << GLB_REG2_GPIO_25_O_POS)
+#define GLB_REG2_GPIO_25_O_UMSK (~(((1U << GLB_REG2_GPIO_25_O_LEN) - 1) << GLB_REG2_GPIO_25_O_POS))
+#define GLB_REG2_GPIO_26_O      GLB_REG2_GPIO_26_O
+#define GLB_REG2_GPIO_26_O_POS  (26U)
+#define GLB_REG2_GPIO_26_O_LEN  (1U)
+#define GLB_REG2_GPIO_26_O_MSK  (((1U << GLB_REG2_GPIO_26_O_LEN) - 1) << GLB_REG2_GPIO_26_O_POS)
+#define GLB_REG2_GPIO_26_O_UMSK (~(((1U << GLB_REG2_GPIO_26_O_LEN) - 1) << GLB_REG2_GPIO_26_O_POS))
+#define GLB_REG2_GPIO_27_O      GLB_REG2_GPIO_27_O
+#define GLB_REG2_GPIO_27_O_POS  (27U)
+#define GLB_REG2_GPIO_27_O_LEN  (1U)
+#define GLB_REG2_GPIO_27_O_MSK  (((1U << GLB_REG2_GPIO_27_O_LEN) - 1) << GLB_REG2_GPIO_27_O_POS)
+#define GLB_REG2_GPIO_27_O_UMSK (~(((1U << GLB_REG2_GPIO_27_O_LEN) - 1) << GLB_REG2_GPIO_27_O_POS))
+#define GLB_REG2_GPIO_28_O      GLB_REG2_GPIO_28_O
+#define GLB_REG2_GPIO_28_O_POS  (28U)
+#define GLB_REG2_GPIO_28_O_LEN  (1U)
+#define GLB_REG2_GPIO_28_O_MSK  (((1U << GLB_REG2_GPIO_28_O_LEN) - 1) << GLB_REG2_GPIO_28_O_POS)
+#define GLB_REG2_GPIO_28_O_UMSK (~(((1U << GLB_REG2_GPIO_28_O_LEN) - 1) << GLB_REG2_GPIO_28_O_POS))
+#define GLB_REG2_GPIO_29_O      GLB_REG2_GPIO_29_O
+#define GLB_REG2_GPIO_29_O_POS  (29U)
+#define GLB_REG2_GPIO_29_O_LEN  (1U)
+#define GLB_REG2_GPIO_29_O_MSK  (((1U << GLB_REG2_GPIO_29_O_LEN) - 1) << GLB_REG2_GPIO_29_O_POS)
+#define GLB_REG2_GPIO_29_O_UMSK (~(((1U << GLB_REG2_GPIO_29_O_LEN) - 1) << GLB_REG2_GPIO_29_O_POS))
+#define GLB_REG2_GPIO_30_O      GLB_REG2_GPIO_30_O
+#define GLB_REG2_GPIO_30_O_POS  (30U)
+#define GLB_REG2_GPIO_30_O_LEN  (1U)
+#define GLB_REG2_GPIO_30_O_MSK  (((1U << GLB_REG2_GPIO_30_O_LEN) - 1) << GLB_REG2_GPIO_30_O_POS)
+#define GLB_REG2_GPIO_30_O_UMSK (~(((1U << GLB_REG2_GPIO_30_O_LEN) - 1) << GLB_REG2_GPIO_30_O_POS))
+#define GLB_REG2_GPIO_31_O      GLB_REG2_GPIO_31_O
+#define GLB_REG2_GPIO_31_O_POS  (31U)
+#define GLB_REG2_GPIO_31_O_LEN  (1U)
+#define GLB_REG2_GPIO_31_O_MSK  (((1U << GLB_REG2_GPIO_31_O_LEN) - 1) << GLB_REG2_GPIO_31_O_POS)
+#define GLB_REG2_GPIO_31_O_UMSK (~(((1U << GLB_REG2_GPIO_31_O_LEN) - 1) << GLB_REG2_GPIO_31_O_POS))
+
+/* 0xAE8 : gpio_cfg137 */
+#define GLB_GPIO_CFG137_OFFSET  (0xAE8)
+#define GLB_REG2_GPIO_32_O      GLB_REG2_GPIO_32_O
+#define GLB_REG2_GPIO_32_O_POS  (0U)
+#define GLB_REG2_GPIO_32_O_LEN  (1U)
+#define GLB_REG2_GPIO_32_O_MSK  (((1U << GLB_REG2_GPIO_32_O_LEN) - 1) << GLB_REG2_GPIO_32_O_POS)
+#define GLB_REG2_GPIO_32_O_UMSK (~(((1U << GLB_REG2_GPIO_32_O_LEN) - 1) << GLB_REG2_GPIO_32_O_POS))
+#define GLB_REG2_GPIO_33_O      GLB_REG2_GPIO_33_O
+#define GLB_REG2_GPIO_33_O_POS  (1U)
+#define GLB_REG2_GPIO_33_O_LEN  (1U)
+#define GLB_REG2_GPIO_33_O_MSK  (((1U << GLB_REG2_GPIO_33_O_LEN) - 1) << GLB_REG2_GPIO_33_O_POS)
+#define GLB_REG2_GPIO_33_O_UMSK (~(((1U << GLB_REG2_GPIO_33_O_LEN) - 1) << GLB_REG2_GPIO_33_O_POS))
+#define GLB_REG2_GPIO_34_O      GLB_REG2_GPIO_34_O
+#define GLB_REG2_GPIO_34_O_POS  (2U)
+#define GLB_REG2_GPIO_34_O_LEN  (1U)
+#define GLB_REG2_GPIO_34_O_MSK  (((1U << GLB_REG2_GPIO_34_O_LEN) - 1) << GLB_REG2_GPIO_34_O_POS)
+#define GLB_REG2_GPIO_34_O_UMSK (~(((1U << GLB_REG2_GPIO_34_O_LEN) - 1) << GLB_REG2_GPIO_34_O_POS))
+
+/* 0xAEC : gpio_cfg138 */
+#define GLB_GPIO_CFG138_OFFSET    (0xAEC)
+#define GLB_REG2_GPIO_0_SET       GLB_REG2_GPIO_0_SET
+#define GLB_REG2_GPIO_0_SET_POS   (0U)
+#define GLB_REG2_GPIO_0_SET_LEN   (1U)
+#define GLB_REG2_GPIO_0_SET_MSK   (((1U << GLB_REG2_GPIO_0_SET_LEN) - 1) << GLB_REG2_GPIO_0_SET_POS)
+#define GLB_REG2_GPIO_0_SET_UMSK  (~(((1U << GLB_REG2_GPIO_0_SET_LEN) - 1) << GLB_REG2_GPIO_0_SET_POS))
+#define GLB_REG2_GPIO_1_SET       GLB_REG2_GPIO_1_SET
+#define GLB_REG2_GPIO_1_SET_POS   (1U)
+#define GLB_REG2_GPIO_1_SET_LEN   (1U)
+#define GLB_REG2_GPIO_1_SET_MSK   (((1U << GLB_REG2_GPIO_1_SET_LEN) - 1) << GLB_REG2_GPIO_1_SET_POS)
+#define GLB_REG2_GPIO_1_SET_UMSK  (~(((1U << GLB_REG2_GPIO_1_SET_LEN) - 1) << GLB_REG2_GPIO_1_SET_POS))
+#define GLB_REG2_GPIO_2_SET       GLB_REG2_GPIO_2_SET
+#define GLB_REG2_GPIO_2_SET_POS   (2U)
+#define GLB_REG2_GPIO_2_SET_LEN   (1U)
+#define GLB_REG2_GPIO_2_SET_MSK   (((1U << GLB_REG2_GPIO_2_SET_LEN) - 1) << GLB_REG2_GPIO_2_SET_POS)
+#define GLB_REG2_GPIO_2_SET_UMSK  (~(((1U << GLB_REG2_GPIO_2_SET_LEN) - 1) << GLB_REG2_GPIO_2_SET_POS))
+#define GLB_REG2_GPIO_3_SET       GLB_REG2_GPIO_3_SET
+#define GLB_REG2_GPIO_3_SET_POS   (3U)
+#define GLB_REG2_GPIO_3_SET_LEN   (1U)
+#define GLB_REG2_GPIO_3_SET_MSK   (((1U << GLB_REG2_GPIO_3_SET_LEN) - 1) << GLB_REG2_GPIO_3_SET_POS)
+#define GLB_REG2_GPIO_3_SET_UMSK  (~(((1U << GLB_REG2_GPIO_3_SET_LEN) - 1) << GLB_REG2_GPIO_3_SET_POS))
+#define GLB_REG2_GPIO_4_SET       GLB_REG2_GPIO_4_SET
+#define GLB_REG2_GPIO_4_SET_POS   (4U)
+#define GLB_REG2_GPIO_4_SET_LEN   (1U)
+#define GLB_REG2_GPIO_4_SET_MSK   (((1U << GLB_REG2_GPIO_4_SET_LEN) - 1) << GLB_REG2_GPIO_4_SET_POS)
+#define GLB_REG2_GPIO_4_SET_UMSK  (~(((1U << GLB_REG2_GPIO_4_SET_LEN) - 1) << GLB_REG2_GPIO_4_SET_POS))
+#define GLB_REG2_GPIO_5_SET       GLB_REG2_GPIO_5_SET
+#define GLB_REG2_GPIO_5_SET_POS   (5U)
+#define GLB_REG2_GPIO_5_SET_LEN   (1U)
+#define GLB_REG2_GPIO_5_SET_MSK   (((1U << GLB_REG2_GPIO_5_SET_LEN) - 1) << GLB_REG2_GPIO_5_SET_POS)
+#define GLB_REG2_GPIO_5_SET_UMSK  (~(((1U << GLB_REG2_GPIO_5_SET_LEN) - 1) << GLB_REG2_GPIO_5_SET_POS))
+#define GLB_REG2_GPIO_6_SET       GLB_REG2_GPIO_6_SET
+#define GLB_REG2_GPIO_6_SET_POS   (6U)
+#define GLB_REG2_GPIO_6_SET_LEN   (1U)
+#define GLB_REG2_GPIO_6_SET_MSK   (((1U << GLB_REG2_GPIO_6_SET_LEN) - 1) << GLB_REG2_GPIO_6_SET_POS)
+#define GLB_REG2_GPIO_6_SET_UMSK  (~(((1U << GLB_REG2_GPIO_6_SET_LEN) - 1) << GLB_REG2_GPIO_6_SET_POS))
+#define GLB_REG2_GPIO_7_SET       GLB_REG2_GPIO_7_SET
+#define GLB_REG2_GPIO_7_SET_POS   (7U)
+#define GLB_REG2_GPIO_7_SET_LEN   (1U)
+#define GLB_REG2_GPIO_7_SET_MSK   (((1U << GLB_REG2_GPIO_7_SET_LEN) - 1) << GLB_REG2_GPIO_7_SET_POS)
+#define GLB_REG2_GPIO_7_SET_UMSK  (~(((1U << GLB_REG2_GPIO_7_SET_LEN) - 1) << GLB_REG2_GPIO_7_SET_POS))
+#define GLB_REG2_GPIO_8_SET       GLB_REG2_GPIO_8_SET
+#define GLB_REG2_GPIO_8_SET_POS   (8U)
+#define GLB_REG2_GPIO_8_SET_LEN   (1U)
+#define GLB_REG2_GPIO_8_SET_MSK   (((1U << GLB_REG2_GPIO_8_SET_LEN) - 1) << GLB_REG2_GPIO_8_SET_POS)
+#define GLB_REG2_GPIO_8_SET_UMSK  (~(((1U << GLB_REG2_GPIO_8_SET_LEN) - 1) << GLB_REG2_GPIO_8_SET_POS))
+#define GLB_REG2_GPIO_9_SET       GLB_REG2_GPIO_9_SET
+#define GLB_REG2_GPIO_9_SET_POS   (9U)
+#define GLB_REG2_GPIO_9_SET_LEN   (1U)
+#define GLB_REG2_GPIO_9_SET_MSK   (((1U << GLB_REG2_GPIO_9_SET_LEN) - 1) << GLB_REG2_GPIO_9_SET_POS)
+#define GLB_REG2_GPIO_9_SET_UMSK  (~(((1U << GLB_REG2_GPIO_9_SET_LEN) - 1) << GLB_REG2_GPIO_9_SET_POS))
+#define GLB_REG2_GPIO_10_SET      GLB_REG2_GPIO_10_SET
+#define GLB_REG2_GPIO_10_SET_POS  (10U)
+#define GLB_REG2_GPIO_10_SET_LEN  (1U)
+#define GLB_REG2_GPIO_10_SET_MSK  (((1U << GLB_REG2_GPIO_10_SET_LEN) - 1) << GLB_REG2_GPIO_10_SET_POS)
+#define GLB_REG2_GPIO_10_SET_UMSK (~(((1U << GLB_REG2_GPIO_10_SET_LEN) - 1) << GLB_REG2_GPIO_10_SET_POS))
+#define GLB_REG2_GPIO_11_SET      GLB_REG2_GPIO_11_SET
+#define GLB_REG2_GPIO_11_SET_POS  (11U)
+#define GLB_REG2_GPIO_11_SET_LEN  (1U)
+#define GLB_REG2_GPIO_11_SET_MSK  (((1U << GLB_REG2_GPIO_11_SET_LEN) - 1) << GLB_REG2_GPIO_11_SET_POS)
+#define GLB_REG2_GPIO_11_SET_UMSK (~(((1U << GLB_REG2_GPIO_11_SET_LEN) - 1) << GLB_REG2_GPIO_11_SET_POS))
+#define GLB_REG2_GPIO_12_SET      GLB_REG2_GPIO_12_SET
+#define GLB_REG2_GPIO_12_SET_POS  (12U)
+#define GLB_REG2_GPIO_12_SET_LEN  (1U)
+#define GLB_REG2_GPIO_12_SET_MSK  (((1U << GLB_REG2_GPIO_12_SET_LEN) - 1) << GLB_REG2_GPIO_12_SET_POS)
+#define GLB_REG2_GPIO_12_SET_UMSK (~(((1U << GLB_REG2_GPIO_12_SET_LEN) - 1) << GLB_REG2_GPIO_12_SET_POS))
+#define GLB_REG2_GPIO_13_SET      GLB_REG2_GPIO_13_SET
+#define GLB_REG2_GPIO_13_SET_POS  (13U)
+#define GLB_REG2_GPIO_13_SET_LEN  (1U)
+#define GLB_REG2_GPIO_13_SET_MSK  (((1U << GLB_REG2_GPIO_13_SET_LEN) - 1) << GLB_REG2_GPIO_13_SET_POS)
+#define GLB_REG2_GPIO_13_SET_UMSK (~(((1U << GLB_REG2_GPIO_13_SET_LEN) - 1) << GLB_REG2_GPIO_13_SET_POS))
+#define GLB_REG2_GPIO_14_SET      GLB_REG2_GPIO_14_SET
+#define GLB_REG2_GPIO_14_SET_POS  (14U)
+#define GLB_REG2_GPIO_14_SET_LEN  (1U)
+#define GLB_REG2_GPIO_14_SET_MSK  (((1U << GLB_REG2_GPIO_14_SET_LEN) - 1) << GLB_REG2_GPIO_14_SET_POS)
+#define GLB_REG2_GPIO_14_SET_UMSK (~(((1U << GLB_REG2_GPIO_14_SET_LEN) - 1) << GLB_REG2_GPIO_14_SET_POS))
+#define GLB_REG2_GPIO_15_SET      GLB_REG2_GPIO_15_SET
+#define GLB_REG2_GPIO_15_SET_POS  (15U)
+#define GLB_REG2_GPIO_15_SET_LEN  (1U)
+#define GLB_REG2_GPIO_15_SET_MSK  (((1U << GLB_REG2_GPIO_15_SET_LEN) - 1) << GLB_REG2_GPIO_15_SET_POS)
+#define GLB_REG2_GPIO_15_SET_UMSK (~(((1U << GLB_REG2_GPIO_15_SET_LEN) - 1) << GLB_REG2_GPIO_15_SET_POS))
+#define GLB_REG2_GPIO_16_SET      GLB_REG2_GPIO_16_SET
+#define GLB_REG2_GPIO_16_SET_POS  (16U)
+#define GLB_REG2_GPIO_16_SET_LEN  (1U)
+#define GLB_REG2_GPIO_16_SET_MSK  (((1U << GLB_REG2_GPIO_16_SET_LEN) - 1) << GLB_REG2_GPIO_16_SET_POS)
+#define GLB_REG2_GPIO_16_SET_UMSK (~(((1U << GLB_REG2_GPIO_16_SET_LEN) - 1) << GLB_REG2_GPIO_16_SET_POS))
+#define GLB_REG2_GPIO_17_SET      GLB_REG2_GPIO_17_SET
+#define GLB_REG2_GPIO_17_SET_POS  (17U)
+#define GLB_REG2_GPIO_17_SET_LEN  (1U)
+#define GLB_REG2_GPIO_17_SET_MSK  (((1U << GLB_REG2_GPIO_17_SET_LEN) - 1) << GLB_REG2_GPIO_17_SET_POS)
+#define GLB_REG2_GPIO_17_SET_UMSK (~(((1U << GLB_REG2_GPIO_17_SET_LEN) - 1) << GLB_REG2_GPIO_17_SET_POS))
+#define GLB_REG2_GPIO_18_SET      GLB_REG2_GPIO_18_SET
+#define GLB_REG2_GPIO_18_SET_POS  (18U)
+#define GLB_REG2_GPIO_18_SET_LEN  (1U)
+#define GLB_REG2_GPIO_18_SET_MSK  (((1U << GLB_REG2_GPIO_18_SET_LEN) - 1) << GLB_REG2_GPIO_18_SET_POS)
+#define GLB_REG2_GPIO_18_SET_UMSK (~(((1U << GLB_REG2_GPIO_18_SET_LEN) - 1) << GLB_REG2_GPIO_18_SET_POS))
+#define GLB_REG2_GPIO_19_SET      GLB_REG2_GPIO_19_SET
+#define GLB_REG2_GPIO_19_SET_POS  (19U)
+#define GLB_REG2_GPIO_19_SET_LEN  (1U)
+#define GLB_REG2_GPIO_19_SET_MSK  (((1U << GLB_REG2_GPIO_19_SET_LEN) - 1) << GLB_REG2_GPIO_19_SET_POS)
+#define GLB_REG2_GPIO_19_SET_UMSK (~(((1U << GLB_REG2_GPIO_19_SET_LEN) - 1) << GLB_REG2_GPIO_19_SET_POS))
+#define GLB_REG2_GPIO_20_SET      GLB_REG2_GPIO_20_SET
+#define GLB_REG2_GPIO_20_SET_POS  (20U)
+#define GLB_REG2_GPIO_20_SET_LEN  (1U)
+#define GLB_REG2_GPIO_20_SET_MSK  (((1U << GLB_REG2_GPIO_20_SET_LEN) - 1) << GLB_REG2_GPIO_20_SET_POS)
+#define GLB_REG2_GPIO_20_SET_UMSK (~(((1U << GLB_REG2_GPIO_20_SET_LEN) - 1) << GLB_REG2_GPIO_20_SET_POS))
+#define GLB_REG2_GPIO_21_SET      GLB_REG2_GPIO_21_SET
+#define GLB_REG2_GPIO_21_SET_POS  (21U)
+#define GLB_REG2_GPIO_21_SET_LEN  (1U)
+#define GLB_REG2_GPIO_21_SET_MSK  (((1U << GLB_REG2_GPIO_21_SET_LEN) - 1) << GLB_REG2_GPIO_21_SET_POS)
+#define GLB_REG2_GPIO_21_SET_UMSK (~(((1U << GLB_REG2_GPIO_21_SET_LEN) - 1) << GLB_REG2_GPIO_21_SET_POS))
+#define GLB_REG2_GPIO_22_SET      GLB_REG2_GPIO_22_SET
+#define GLB_REG2_GPIO_22_SET_POS  (22U)
+#define GLB_REG2_GPIO_22_SET_LEN  (1U)
+#define GLB_REG2_GPIO_22_SET_MSK  (((1U << GLB_REG2_GPIO_22_SET_LEN) - 1) << GLB_REG2_GPIO_22_SET_POS)
+#define GLB_REG2_GPIO_22_SET_UMSK (~(((1U << GLB_REG2_GPIO_22_SET_LEN) - 1) << GLB_REG2_GPIO_22_SET_POS))
+#define GLB_REG2_GPIO_23_SET      GLB_REG2_GPIO_23_SET
+#define GLB_REG2_GPIO_23_SET_POS  (23U)
+#define GLB_REG2_GPIO_23_SET_LEN  (1U)
+#define GLB_REG2_GPIO_23_SET_MSK  (((1U << GLB_REG2_GPIO_23_SET_LEN) - 1) << GLB_REG2_GPIO_23_SET_POS)
+#define GLB_REG2_GPIO_23_SET_UMSK (~(((1U << GLB_REG2_GPIO_23_SET_LEN) - 1) << GLB_REG2_GPIO_23_SET_POS))
+#define GLB_REG2_GPIO_24_SET      GLB_REG2_GPIO_24_SET
+#define GLB_REG2_GPIO_24_SET_POS  (24U)
+#define GLB_REG2_GPIO_24_SET_LEN  (1U)
+#define GLB_REG2_GPIO_24_SET_MSK  (((1U << GLB_REG2_GPIO_24_SET_LEN) - 1) << GLB_REG2_GPIO_24_SET_POS)
+#define GLB_REG2_GPIO_24_SET_UMSK (~(((1U << GLB_REG2_GPIO_24_SET_LEN) - 1) << GLB_REG2_GPIO_24_SET_POS))
+#define GLB_REG2_GPIO_25_SET      GLB_REG2_GPIO_25_SET
+#define GLB_REG2_GPIO_25_SET_POS  (25U)
+#define GLB_REG2_GPIO_25_SET_LEN  (1U)
+#define GLB_REG2_GPIO_25_SET_MSK  (((1U << GLB_REG2_GPIO_25_SET_LEN) - 1) << GLB_REG2_GPIO_25_SET_POS)
+#define GLB_REG2_GPIO_25_SET_UMSK (~(((1U << GLB_REG2_GPIO_25_SET_LEN) - 1) << GLB_REG2_GPIO_25_SET_POS))
+#define GLB_REG2_GPIO_26_SET      GLB_REG2_GPIO_26_SET
+#define GLB_REG2_GPIO_26_SET_POS  (26U)
+#define GLB_REG2_GPIO_26_SET_LEN  (1U)
+#define GLB_REG2_GPIO_26_SET_MSK  (((1U << GLB_REG2_GPIO_26_SET_LEN) - 1) << GLB_REG2_GPIO_26_SET_POS)
+#define GLB_REG2_GPIO_26_SET_UMSK (~(((1U << GLB_REG2_GPIO_26_SET_LEN) - 1) << GLB_REG2_GPIO_26_SET_POS))
+#define GLB_REG2_GPIO_27_SET      GLB_REG2_GPIO_27_SET
+#define GLB_REG2_GPIO_27_SET_POS  (27U)
+#define GLB_REG2_GPIO_27_SET_LEN  (1U)
+#define GLB_REG2_GPIO_27_SET_MSK  (((1U << GLB_REG2_GPIO_27_SET_LEN) - 1) << GLB_REG2_GPIO_27_SET_POS)
+#define GLB_REG2_GPIO_27_SET_UMSK (~(((1U << GLB_REG2_GPIO_27_SET_LEN) - 1) << GLB_REG2_GPIO_27_SET_POS))
+#define GLB_REG2_GPIO_28_SET      GLB_REG2_GPIO_28_SET
+#define GLB_REG2_GPIO_28_SET_POS  (28U)
+#define GLB_REG2_GPIO_28_SET_LEN  (1U)
+#define GLB_REG2_GPIO_28_SET_MSK  (((1U << GLB_REG2_GPIO_28_SET_LEN) - 1) << GLB_REG2_GPIO_28_SET_POS)
+#define GLB_REG2_GPIO_28_SET_UMSK (~(((1U << GLB_REG2_GPIO_28_SET_LEN) - 1) << GLB_REG2_GPIO_28_SET_POS))
+#define GLB_REG2_GPIO_29_SET      GLB_REG2_GPIO_29_SET
+#define GLB_REG2_GPIO_29_SET_POS  (29U)
+#define GLB_REG2_GPIO_29_SET_LEN  (1U)
+#define GLB_REG2_GPIO_29_SET_MSK  (((1U << GLB_REG2_GPIO_29_SET_LEN) - 1) << GLB_REG2_GPIO_29_SET_POS)
+#define GLB_REG2_GPIO_29_SET_UMSK (~(((1U << GLB_REG2_GPIO_29_SET_LEN) - 1) << GLB_REG2_GPIO_29_SET_POS))
+#define GLB_REG2_GPIO_30_SET      GLB_REG2_GPIO_30_SET
+#define GLB_REG2_GPIO_30_SET_POS  (30U)
+#define GLB_REG2_GPIO_30_SET_LEN  (1U)
+#define GLB_REG2_GPIO_30_SET_MSK  (((1U << GLB_REG2_GPIO_30_SET_LEN) - 1) << GLB_REG2_GPIO_30_SET_POS)
+#define GLB_REG2_GPIO_30_SET_UMSK (~(((1U << GLB_REG2_GPIO_30_SET_LEN) - 1) << GLB_REG2_GPIO_30_SET_POS))
+#define GLB_REG2_GPIO_31_SET      GLB_REG2_GPIO_31_SET
+#define GLB_REG2_GPIO_31_SET_POS  (31U)
+#define GLB_REG2_GPIO_31_SET_LEN  (1U)
+#define GLB_REG2_GPIO_31_SET_MSK  (((1U << GLB_REG2_GPIO_31_SET_LEN) - 1) << GLB_REG2_GPIO_31_SET_POS)
+#define GLB_REG2_GPIO_31_SET_UMSK (~(((1U << GLB_REG2_GPIO_31_SET_LEN) - 1) << GLB_REG2_GPIO_31_SET_POS))
+
+/* 0xAF0 : gpio_cfg139 */
+#define GLB_GPIO_CFG139_OFFSET    (0xAF0)
+#define GLB_REG2_GPIO_32_SET      GLB_REG2_GPIO_32_SET
+#define GLB_REG2_GPIO_32_SET_POS  (0U)
+#define GLB_REG2_GPIO_32_SET_LEN  (1U)
+#define GLB_REG2_GPIO_32_SET_MSK  (((1U << GLB_REG2_GPIO_32_SET_LEN) - 1) << GLB_REG2_GPIO_32_SET_POS)
+#define GLB_REG2_GPIO_32_SET_UMSK (~(((1U << GLB_REG2_GPIO_32_SET_LEN) - 1) << GLB_REG2_GPIO_32_SET_POS))
+#define GLB_REG2_GPIO_33_SET      GLB_REG2_GPIO_33_SET
+#define GLB_REG2_GPIO_33_SET_POS  (1U)
+#define GLB_REG2_GPIO_33_SET_LEN  (1U)
+#define GLB_REG2_GPIO_33_SET_MSK  (((1U << GLB_REG2_GPIO_33_SET_LEN) - 1) << GLB_REG2_GPIO_33_SET_POS)
+#define GLB_REG2_GPIO_33_SET_UMSK (~(((1U << GLB_REG2_GPIO_33_SET_LEN) - 1) << GLB_REG2_GPIO_33_SET_POS))
+#define GLB_REG2_GPIO_34_SET      GLB_REG2_GPIO_34_SET
+#define GLB_REG2_GPIO_34_SET_POS  (2U)
+#define GLB_REG2_GPIO_34_SET_LEN  (1U)
+#define GLB_REG2_GPIO_34_SET_MSK  (((1U << GLB_REG2_GPIO_34_SET_LEN) - 1) << GLB_REG2_GPIO_34_SET_POS)
+#define GLB_REG2_GPIO_34_SET_UMSK (~(((1U << GLB_REG2_GPIO_34_SET_LEN) - 1) << GLB_REG2_GPIO_34_SET_POS))
+
+/* 0xAF4 : gpio_cfg140 */
+#define GLB_GPIO_CFG140_OFFSET    (0xAF4)
+#define GLB_REG2_GPIO_0_CLR       GLB_REG2_GPIO_0_CLR
+#define GLB_REG2_GPIO_0_CLR_POS   (0U)
+#define GLB_REG2_GPIO_0_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_0_CLR_MSK   (((1U << GLB_REG2_GPIO_0_CLR_LEN) - 1) << GLB_REG2_GPIO_0_CLR_POS)
+#define GLB_REG2_GPIO_0_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_0_CLR_LEN) - 1) << GLB_REG2_GPIO_0_CLR_POS))
+#define GLB_REG2_GPIO_1_CLR       GLB_REG2_GPIO_1_CLR
+#define GLB_REG2_GPIO_1_CLR_POS   (1U)
+#define GLB_REG2_GPIO_1_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_1_CLR_MSK   (((1U << GLB_REG2_GPIO_1_CLR_LEN) - 1) << GLB_REG2_GPIO_1_CLR_POS)
+#define GLB_REG2_GPIO_1_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_1_CLR_LEN) - 1) << GLB_REG2_GPIO_1_CLR_POS))
+#define GLB_REG2_GPIO_2_CLR       GLB_REG2_GPIO_2_CLR
+#define GLB_REG2_GPIO_2_CLR_POS   (2U)
+#define GLB_REG2_GPIO_2_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_2_CLR_MSK   (((1U << GLB_REG2_GPIO_2_CLR_LEN) - 1) << GLB_REG2_GPIO_2_CLR_POS)
+#define GLB_REG2_GPIO_2_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_2_CLR_LEN) - 1) << GLB_REG2_GPIO_2_CLR_POS))
+#define GLB_REG2_GPIO_3_CLR       GLB_REG2_GPIO_3_CLR
+#define GLB_REG2_GPIO_3_CLR_POS   (3U)
+#define GLB_REG2_GPIO_3_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_3_CLR_MSK   (((1U << GLB_REG2_GPIO_3_CLR_LEN) - 1) << GLB_REG2_GPIO_3_CLR_POS)
+#define GLB_REG2_GPIO_3_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_3_CLR_LEN) - 1) << GLB_REG2_GPIO_3_CLR_POS))
+#define GLB_REG2_GPIO_4_CLR       GLB_REG2_GPIO_4_CLR
+#define GLB_REG2_GPIO_4_CLR_POS   (4U)
+#define GLB_REG2_GPIO_4_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_4_CLR_MSK   (((1U << GLB_REG2_GPIO_4_CLR_LEN) - 1) << GLB_REG2_GPIO_4_CLR_POS)
+#define GLB_REG2_GPIO_4_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_4_CLR_LEN) - 1) << GLB_REG2_GPIO_4_CLR_POS))
+#define GLB_REG2_GPIO_5_CLR       GLB_REG2_GPIO_5_CLR
+#define GLB_REG2_GPIO_5_CLR_POS   (5U)
+#define GLB_REG2_GPIO_5_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_5_CLR_MSK   (((1U << GLB_REG2_GPIO_5_CLR_LEN) - 1) << GLB_REG2_GPIO_5_CLR_POS)
+#define GLB_REG2_GPIO_5_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_5_CLR_LEN) - 1) << GLB_REG2_GPIO_5_CLR_POS))
+#define GLB_REG2_GPIO_6_CLR       GLB_REG2_GPIO_6_CLR
+#define GLB_REG2_GPIO_6_CLR_POS   (6U)
+#define GLB_REG2_GPIO_6_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_6_CLR_MSK   (((1U << GLB_REG2_GPIO_6_CLR_LEN) - 1) << GLB_REG2_GPIO_6_CLR_POS)
+#define GLB_REG2_GPIO_6_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_6_CLR_LEN) - 1) << GLB_REG2_GPIO_6_CLR_POS))
+#define GLB_REG2_GPIO_7_CLR       GLB_REG2_GPIO_7_CLR
+#define GLB_REG2_GPIO_7_CLR_POS   (7U)
+#define GLB_REG2_GPIO_7_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_7_CLR_MSK   (((1U << GLB_REG2_GPIO_7_CLR_LEN) - 1) << GLB_REG2_GPIO_7_CLR_POS)
+#define GLB_REG2_GPIO_7_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_7_CLR_LEN) - 1) << GLB_REG2_GPIO_7_CLR_POS))
+#define GLB_REG2_GPIO_8_CLR       GLB_REG2_GPIO_8_CLR
+#define GLB_REG2_GPIO_8_CLR_POS   (8U)
+#define GLB_REG2_GPIO_8_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_8_CLR_MSK   (((1U << GLB_REG2_GPIO_8_CLR_LEN) - 1) << GLB_REG2_GPIO_8_CLR_POS)
+#define GLB_REG2_GPIO_8_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_8_CLR_LEN) - 1) << GLB_REG2_GPIO_8_CLR_POS))
+#define GLB_REG2_GPIO_9_CLR       GLB_REG2_GPIO_9_CLR
+#define GLB_REG2_GPIO_9_CLR_POS   (9U)
+#define GLB_REG2_GPIO_9_CLR_LEN   (1U)
+#define GLB_REG2_GPIO_9_CLR_MSK   (((1U << GLB_REG2_GPIO_9_CLR_LEN) - 1) << GLB_REG2_GPIO_9_CLR_POS)
+#define GLB_REG2_GPIO_9_CLR_UMSK  (~(((1U << GLB_REG2_GPIO_9_CLR_LEN) - 1) << GLB_REG2_GPIO_9_CLR_POS))
+#define GLB_REG2_GPIO_10_CLR      GLB_REG2_GPIO_10_CLR
+#define GLB_REG2_GPIO_10_CLR_POS  (10U)
+#define GLB_REG2_GPIO_10_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_10_CLR_MSK  (((1U << GLB_REG2_GPIO_10_CLR_LEN) - 1) << GLB_REG2_GPIO_10_CLR_POS)
+#define GLB_REG2_GPIO_10_CLR_UMSK (~(((1U << GLB_REG2_GPIO_10_CLR_LEN) - 1) << GLB_REG2_GPIO_10_CLR_POS))
+#define GLB_REG2_GPIO_11_CLR      GLB_REG2_GPIO_11_CLR
+#define GLB_REG2_GPIO_11_CLR_POS  (11U)
+#define GLB_REG2_GPIO_11_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_11_CLR_MSK  (((1U << GLB_REG2_GPIO_11_CLR_LEN) - 1) << GLB_REG2_GPIO_11_CLR_POS)
+#define GLB_REG2_GPIO_11_CLR_UMSK (~(((1U << GLB_REG2_GPIO_11_CLR_LEN) - 1) << GLB_REG2_GPIO_11_CLR_POS))
+#define GLB_REG2_GPIO_12_CLR      GLB_REG2_GPIO_12_CLR
+#define GLB_REG2_GPIO_12_CLR_POS  (12U)
+#define GLB_REG2_GPIO_12_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_12_CLR_MSK  (((1U << GLB_REG2_GPIO_12_CLR_LEN) - 1) << GLB_REG2_GPIO_12_CLR_POS)
+#define GLB_REG2_GPIO_12_CLR_UMSK (~(((1U << GLB_REG2_GPIO_12_CLR_LEN) - 1) << GLB_REG2_GPIO_12_CLR_POS))
+#define GLB_REG2_GPIO_13_CLR      GLB_REG2_GPIO_13_CLR
+#define GLB_REG2_GPIO_13_CLR_POS  (13U)
+#define GLB_REG2_GPIO_13_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_13_CLR_MSK  (((1U << GLB_REG2_GPIO_13_CLR_LEN) - 1) << GLB_REG2_GPIO_13_CLR_POS)
+#define GLB_REG2_GPIO_13_CLR_UMSK (~(((1U << GLB_REG2_GPIO_13_CLR_LEN) - 1) << GLB_REG2_GPIO_13_CLR_POS))
+#define GLB_REG2_GPIO_14_CLR      GLB_REG2_GPIO_14_CLR
+#define GLB_REG2_GPIO_14_CLR_POS  (14U)
+#define GLB_REG2_GPIO_14_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_14_CLR_MSK  (((1U << GLB_REG2_GPIO_14_CLR_LEN) - 1) << GLB_REG2_GPIO_14_CLR_POS)
+#define GLB_REG2_GPIO_14_CLR_UMSK (~(((1U << GLB_REG2_GPIO_14_CLR_LEN) - 1) << GLB_REG2_GPIO_14_CLR_POS))
+#define GLB_REG2_GPIO_15_CLR      GLB_REG2_GPIO_15_CLR
+#define GLB_REG2_GPIO_15_CLR_POS  (15U)
+#define GLB_REG2_GPIO_15_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_15_CLR_MSK  (((1U << GLB_REG2_GPIO_15_CLR_LEN) - 1) << GLB_REG2_GPIO_15_CLR_POS)
+#define GLB_REG2_GPIO_15_CLR_UMSK (~(((1U << GLB_REG2_GPIO_15_CLR_LEN) - 1) << GLB_REG2_GPIO_15_CLR_POS))
+#define GLB_REG2_GPIO_16_CLR      GLB_REG2_GPIO_16_CLR
+#define GLB_REG2_GPIO_16_CLR_POS  (16U)
+#define GLB_REG2_GPIO_16_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_16_CLR_MSK  (((1U << GLB_REG2_GPIO_16_CLR_LEN) - 1) << GLB_REG2_GPIO_16_CLR_POS)
+#define GLB_REG2_GPIO_16_CLR_UMSK (~(((1U << GLB_REG2_GPIO_16_CLR_LEN) - 1) << GLB_REG2_GPIO_16_CLR_POS))
+#define GLB_REG2_GPIO_17_CLR      GLB_REG2_GPIO_17_CLR
+#define GLB_REG2_GPIO_17_CLR_POS  (17U)
+#define GLB_REG2_GPIO_17_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_17_CLR_MSK  (((1U << GLB_REG2_GPIO_17_CLR_LEN) - 1) << GLB_REG2_GPIO_17_CLR_POS)
+#define GLB_REG2_GPIO_17_CLR_UMSK (~(((1U << GLB_REG2_GPIO_17_CLR_LEN) - 1) << GLB_REG2_GPIO_17_CLR_POS))
+#define GLB_REG2_GPIO_18_CLR      GLB_REG2_GPIO_18_CLR
+#define GLB_REG2_GPIO_18_CLR_POS  (18U)
+#define GLB_REG2_GPIO_18_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_18_CLR_MSK  (((1U << GLB_REG2_GPIO_18_CLR_LEN) - 1) << GLB_REG2_GPIO_18_CLR_POS)
+#define GLB_REG2_GPIO_18_CLR_UMSK (~(((1U << GLB_REG2_GPIO_18_CLR_LEN) - 1) << GLB_REG2_GPIO_18_CLR_POS))
+#define GLB_REG2_GPIO_19_CLR      GLB_REG2_GPIO_19_CLR
+#define GLB_REG2_GPIO_19_CLR_POS  (19U)
+#define GLB_REG2_GPIO_19_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_19_CLR_MSK  (((1U << GLB_REG2_GPIO_19_CLR_LEN) - 1) << GLB_REG2_GPIO_19_CLR_POS)
+#define GLB_REG2_GPIO_19_CLR_UMSK (~(((1U << GLB_REG2_GPIO_19_CLR_LEN) - 1) << GLB_REG2_GPIO_19_CLR_POS))
+#define GLB_REG2_GPIO_20_CLR      GLB_REG2_GPIO_20_CLR
+#define GLB_REG2_GPIO_20_CLR_POS  (20U)
+#define GLB_REG2_GPIO_20_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_20_CLR_MSK  (((1U << GLB_REG2_GPIO_20_CLR_LEN) - 1) << GLB_REG2_GPIO_20_CLR_POS)
+#define GLB_REG2_GPIO_20_CLR_UMSK (~(((1U << GLB_REG2_GPIO_20_CLR_LEN) - 1) << GLB_REG2_GPIO_20_CLR_POS))
+#define GLB_REG2_GPIO_21_CLR      GLB_REG2_GPIO_21_CLR
+#define GLB_REG2_GPIO_21_CLR_POS  (21U)
+#define GLB_REG2_GPIO_21_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_21_CLR_MSK  (((1U << GLB_REG2_GPIO_21_CLR_LEN) - 1) << GLB_REG2_GPIO_21_CLR_POS)
+#define GLB_REG2_GPIO_21_CLR_UMSK (~(((1U << GLB_REG2_GPIO_21_CLR_LEN) - 1) << GLB_REG2_GPIO_21_CLR_POS))
+#define GLB_REG2_GPIO_22_CLR      GLB_REG2_GPIO_22_CLR
+#define GLB_REG2_GPIO_22_CLR_POS  (22U)
+#define GLB_REG2_GPIO_22_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_22_CLR_MSK  (((1U << GLB_REG2_GPIO_22_CLR_LEN) - 1) << GLB_REG2_GPIO_22_CLR_POS)
+#define GLB_REG2_GPIO_22_CLR_UMSK (~(((1U << GLB_REG2_GPIO_22_CLR_LEN) - 1) << GLB_REG2_GPIO_22_CLR_POS))
+#define GLB_REG2_GPIO_23_CLR      GLB_REG2_GPIO_23_CLR
+#define GLB_REG2_GPIO_23_CLR_POS  (23U)
+#define GLB_REG2_GPIO_23_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_23_CLR_MSK  (((1U << GLB_REG2_GPIO_23_CLR_LEN) - 1) << GLB_REG2_GPIO_23_CLR_POS)
+#define GLB_REG2_GPIO_23_CLR_UMSK (~(((1U << GLB_REG2_GPIO_23_CLR_LEN) - 1) << GLB_REG2_GPIO_23_CLR_POS))
+#define GLB_REG2_GPIO_24_CLR      GLB_REG2_GPIO_24_CLR
+#define GLB_REG2_GPIO_24_CLR_POS  (24U)
+#define GLB_REG2_GPIO_24_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_24_CLR_MSK  (((1U << GLB_REG2_GPIO_24_CLR_LEN) - 1) << GLB_REG2_GPIO_24_CLR_POS)
+#define GLB_REG2_GPIO_24_CLR_UMSK (~(((1U << GLB_REG2_GPIO_24_CLR_LEN) - 1) << GLB_REG2_GPIO_24_CLR_POS))
+#define GLB_REG2_GPIO_25_CLR      GLB_REG2_GPIO_25_CLR
+#define GLB_REG2_GPIO_25_CLR_POS  (25U)
+#define GLB_REG2_GPIO_25_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_25_CLR_MSK  (((1U << GLB_REG2_GPIO_25_CLR_LEN) - 1) << GLB_REG2_GPIO_25_CLR_POS)
+#define GLB_REG2_GPIO_25_CLR_UMSK (~(((1U << GLB_REG2_GPIO_25_CLR_LEN) - 1) << GLB_REG2_GPIO_25_CLR_POS))
+#define GLB_REG2_GPIO_26_CLR      GLB_REG2_GPIO_26_CLR
+#define GLB_REG2_GPIO_26_CLR_POS  (26U)
+#define GLB_REG2_GPIO_26_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_26_CLR_MSK  (((1U << GLB_REG2_GPIO_26_CLR_LEN) - 1) << GLB_REG2_GPIO_26_CLR_POS)
+#define GLB_REG2_GPIO_26_CLR_UMSK (~(((1U << GLB_REG2_GPIO_26_CLR_LEN) - 1) << GLB_REG2_GPIO_26_CLR_POS))
+#define GLB_REG2_GPIO_27_CLR      GLB_REG2_GPIO_27_CLR
+#define GLB_REG2_GPIO_27_CLR_POS  (27U)
+#define GLB_REG2_GPIO_27_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_27_CLR_MSK  (((1U << GLB_REG2_GPIO_27_CLR_LEN) - 1) << GLB_REG2_GPIO_27_CLR_POS)
+#define GLB_REG2_GPIO_27_CLR_UMSK (~(((1U << GLB_REG2_GPIO_27_CLR_LEN) - 1) << GLB_REG2_GPIO_27_CLR_POS))
+#define GLB_REG2_GPIO_28_CLR      GLB_REG2_GPIO_28_CLR
+#define GLB_REG2_GPIO_28_CLR_POS  (28U)
+#define GLB_REG2_GPIO_28_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_28_CLR_MSK  (((1U << GLB_REG2_GPIO_28_CLR_LEN) - 1) << GLB_REG2_GPIO_28_CLR_POS)
+#define GLB_REG2_GPIO_28_CLR_UMSK (~(((1U << GLB_REG2_GPIO_28_CLR_LEN) - 1) << GLB_REG2_GPIO_28_CLR_POS))
+#define GLB_REG2_GPIO_29_CLR      GLB_REG2_GPIO_29_CLR
+#define GLB_REG2_GPIO_29_CLR_POS  (29U)
+#define GLB_REG2_GPIO_29_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_29_CLR_MSK  (((1U << GLB_REG2_GPIO_29_CLR_LEN) - 1) << GLB_REG2_GPIO_29_CLR_POS)
+#define GLB_REG2_GPIO_29_CLR_UMSK (~(((1U << GLB_REG2_GPIO_29_CLR_LEN) - 1) << GLB_REG2_GPIO_29_CLR_POS))
+#define GLB_REG2_GPIO_30_CLR      GLB_REG2_GPIO_30_CLR
+#define GLB_REG2_GPIO_30_CLR_POS  (30U)
+#define GLB_REG2_GPIO_30_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_30_CLR_MSK  (((1U << GLB_REG2_GPIO_30_CLR_LEN) - 1) << GLB_REG2_GPIO_30_CLR_POS)
+#define GLB_REG2_GPIO_30_CLR_UMSK (~(((1U << GLB_REG2_GPIO_30_CLR_LEN) - 1) << GLB_REG2_GPIO_30_CLR_POS))
+#define GLB_REG2_GPIO_31_CLR      GLB_REG2_GPIO_31_CLR
+#define GLB_REG2_GPIO_31_CLR_POS  (31U)
+#define GLB_REG2_GPIO_31_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_31_CLR_MSK  (((1U << GLB_REG2_GPIO_31_CLR_LEN) - 1) << GLB_REG2_GPIO_31_CLR_POS)
+#define GLB_REG2_GPIO_31_CLR_UMSK (~(((1U << GLB_REG2_GPIO_31_CLR_LEN) - 1) << GLB_REG2_GPIO_31_CLR_POS))
+
+/* 0xAF8 : gpio_cfg141 */
+#define GLB_GPIO_CFG141_OFFSET    (0xAF8)
+#define GLB_REG2_GPIO_32_CLR      GLB_REG2_GPIO_32_CLR
+#define GLB_REG2_GPIO_32_CLR_POS  (0U)
+#define GLB_REG2_GPIO_32_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_32_CLR_MSK  (((1U << GLB_REG2_GPIO_32_CLR_LEN) - 1) << GLB_REG2_GPIO_32_CLR_POS)
+#define GLB_REG2_GPIO_32_CLR_UMSK (~(((1U << GLB_REG2_GPIO_32_CLR_LEN) - 1) << GLB_REG2_GPIO_32_CLR_POS))
+#define GLB_REG2_GPIO_33_CLR      GLB_REG2_GPIO_33_CLR
+#define GLB_REG2_GPIO_33_CLR_POS  (1U)
+#define GLB_REG2_GPIO_33_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_33_CLR_MSK  (((1U << GLB_REG2_GPIO_33_CLR_LEN) - 1) << GLB_REG2_GPIO_33_CLR_POS)
+#define GLB_REG2_GPIO_33_CLR_UMSK (~(((1U << GLB_REG2_GPIO_33_CLR_LEN) - 1) << GLB_REG2_GPIO_33_CLR_POS))
+#define GLB_REG2_GPIO_34_CLR      GLB_REG2_GPIO_34_CLR
+#define GLB_REG2_GPIO_34_CLR_POS  (2U)
+#define GLB_REG2_GPIO_34_CLR_LEN  (1U)
+#define GLB_REG2_GPIO_34_CLR_MSK  (((1U << GLB_REG2_GPIO_34_CLR_LEN) - 1) << GLB_REG2_GPIO_34_CLR_POS)
+#define GLB_REG2_GPIO_34_CLR_UMSK (~(((1U << GLB_REG2_GPIO_34_CLR_LEN) - 1) << GLB_REG2_GPIO_34_CLR_POS))
+
+/* 0xAFC : gpio_cfg142 */
+#define GLB_GPIO_CFG142_OFFSET        (0xAFC)
+#define GLB_CR_GPIO_TX_EN             GLB_CR_GPIO_TX_EN
+#define GLB_CR_GPIO_TX_EN_POS         (0U)
+#define GLB_CR_GPIO_TX_EN_LEN         (1U)
+#define GLB_CR_GPIO_TX_EN_MSK         (((1U << GLB_CR_GPIO_TX_EN_LEN) - 1) << GLB_CR_GPIO_TX_EN_POS)
+#define GLB_CR_GPIO_TX_EN_UMSK        (~(((1U << GLB_CR_GPIO_TX_EN_LEN) - 1) << GLB_CR_GPIO_TX_EN_POS))
+#define GLB_CR_INVERT_CODE0_HIGH      GLB_CR_INVERT_CODE0_HIGH
+#define GLB_CR_INVERT_CODE0_HIGH_POS  (1U)
+#define GLB_CR_INVERT_CODE0_HIGH_LEN  (1U)
+#define GLB_CR_INVERT_CODE0_HIGH_MSK  (((1U << GLB_CR_INVERT_CODE0_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE0_HIGH_POS)
+#define GLB_CR_INVERT_CODE0_HIGH_UMSK (~(((1U << GLB_CR_INVERT_CODE0_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE0_HIGH_POS))
+#define GLB_CR_INVERT_CODE1_HIGH      GLB_CR_INVERT_CODE1_HIGH
+#define GLB_CR_INVERT_CODE1_HIGH_POS  (2U)
+#define GLB_CR_INVERT_CODE1_HIGH_LEN  (1U)
+#define GLB_CR_INVERT_CODE1_HIGH_MSK  (((1U << GLB_CR_INVERT_CODE1_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE1_HIGH_POS)
+#define GLB_CR_INVERT_CODE1_HIGH_UMSK (~(((1U << GLB_CR_INVERT_CODE1_HIGH_LEN) - 1) << GLB_CR_INVERT_CODE1_HIGH_POS))
+#define GLB_CR_CODE_TOTAL_TIME        GLB_CR_CODE_TOTAL_TIME
+#define GLB_CR_CODE_TOTAL_TIME_POS    (7U)
+#define GLB_CR_CODE_TOTAL_TIME_LEN    (9U)
+#define GLB_CR_CODE_TOTAL_TIME_MSK    (((1U << GLB_CR_CODE_TOTAL_TIME_LEN) - 1) << GLB_CR_CODE_TOTAL_TIME_POS)
+#define GLB_CR_CODE_TOTAL_TIME_UMSK   (~(((1U << GLB_CR_CODE_TOTAL_TIME_LEN) - 1) << GLB_CR_CODE_TOTAL_TIME_POS))
+#define GLB_CR_CODE0_HIGH_TIME        GLB_CR_CODE0_HIGH_TIME
+#define GLB_CR_CODE0_HIGH_TIME_POS    (16U)
+#define GLB_CR_CODE0_HIGH_TIME_LEN    (8U)
+#define GLB_CR_CODE0_HIGH_TIME_MSK    (((1U << GLB_CR_CODE0_HIGH_TIME_LEN) - 1) << GLB_CR_CODE0_HIGH_TIME_POS)
+#define GLB_CR_CODE0_HIGH_TIME_UMSK   (~(((1U << GLB_CR_CODE0_HIGH_TIME_LEN) - 1) << GLB_CR_CODE0_HIGH_TIME_POS))
+#define GLB_CR_CODE1_HIGH_TIME        GLB_CR_CODE1_HIGH_TIME
+#define GLB_CR_CODE1_HIGH_TIME_POS    (24U)
+#define GLB_CR_CODE1_HIGH_TIME_LEN    (8U)
+#define GLB_CR_CODE1_HIGH_TIME_MSK    (((1U << GLB_CR_CODE1_HIGH_TIME_LEN) - 1) << GLB_CR_CODE1_HIGH_TIME_POS)
+#define GLB_CR_CODE1_HIGH_TIME_UMSK   (~(((1U << GLB_CR_CODE1_HIGH_TIME_LEN) - 1) << GLB_CR_CODE1_HIGH_TIME_POS))
+
+/* 0xB00 : gpio_cfg143 */
+#define GLB_GPIO_CFG143_OFFSET             (0xB00)
+#define GLB_CR_GPIO_DMA_TX_EN              GLB_CR_GPIO_DMA_TX_EN
+#define GLB_CR_GPIO_DMA_TX_EN_POS          (0U)
+#define GLB_CR_GPIO_DMA_TX_EN_LEN          (1U)
+#define GLB_CR_GPIO_DMA_TX_EN_MSK          (((1U << GLB_CR_GPIO_DMA_TX_EN_LEN) - 1) << GLB_CR_GPIO_DMA_TX_EN_POS)
+#define GLB_CR_GPIO_DMA_TX_EN_UMSK         (~(((1U << GLB_CR_GPIO_DMA_TX_EN_LEN) - 1) << GLB_CR_GPIO_DMA_TX_EN_POS))
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH      GLB_CR_GPIO_DMA_OUT_SEL_LATCH
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_POS  (1U)
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_LEN  (1U)
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_MSK  (((1U << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_LEN) - 1) << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_POS)
+#define GLB_CR_GPIO_DMA_OUT_SEL_LATCH_UMSK (~(((1U << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_LEN) - 1) << GLB_CR_GPIO_DMA_OUT_SEL_LATCH_POS))
+#define GLB_GPIO_TX_FIFO_CLR               GLB_GPIO_TX_FIFO_CLR
+#define GLB_GPIO_TX_FIFO_CLR_POS           (2U)
+#define GLB_GPIO_TX_FIFO_CLR_LEN           (1U)
+#define GLB_GPIO_TX_FIFO_CLR_MSK           (((1U << GLB_GPIO_TX_FIFO_CLR_LEN) - 1) << GLB_GPIO_TX_FIFO_CLR_POS)
+#define GLB_GPIO_TX_FIFO_CLR_UMSK          (~(((1U << GLB_GPIO_TX_FIFO_CLR_LEN) - 1) << GLB_GPIO_TX_FIFO_CLR_POS))
+#define GLB_GPIO_TX_END_CLR                GLB_GPIO_TX_END_CLR
+#define GLB_GPIO_TX_END_CLR_POS            (3U)
+#define GLB_GPIO_TX_END_CLR_LEN            (1U)
+#define GLB_GPIO_TX_END_CLR_MSK            (((1U << GLB_GPIO_TX_END_CLR_LEN) - 1) << GLB_GPIO_TX_END_CLR_POS)
+#define GLB_GPIO_TX_END_CLR_UMSK           (~(((1U << GLB_GPIO_TX_END_CLR_LEN) - 1) << GLB_GPIO_TX_END_CLR_POS))
+#define GLB_GPIO_TX_FIFO_OVERFLOW          GLB_GPIO_TX_FIFO_OVERFLOW
+#define GLB_GPIO_TX_FIFO_OVERFLOW_POS      (4U)
+#define GLB_GPIO_TX_FIFO_OVERFLOW_LEN      (1U)
+#define GLB_GPIO_TX_FIFO_OVERFLOW_MSK      (((1U << GLB_GPIO_TX_FIFO_OVERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_OVERFLOW_POS)
+#define GLB_GPIO_TX_FIFO_OVERFLOW_UMSK     (~(((1U << GLB_GPIO_TX_FIFO_OVERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_OVERFLOW_POS))
+#define GLB_GPIO_TX_FIFO_UNDERFLOW         GLB_GPIO_TX_FIFO_UNDERFLOW
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_POS     (5U)
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_LEN     (1U)
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_MSK     (((1U << GLB_GPIO_TX_FIFO_UNDERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_UNDERFLOW_POS)
+#define GLB_GPIO_TX_FIFO_UNDERFLOW_UMSK    (~(((1U << GLB_GPIO_TX_FIFO_UNDERFLOW_LEN) - 1) << GLB_GPIO_TX_FIFO_UNDERFLOW_POS))
+#define GLB_CR_GPIO_DMA_PARK_VALUE         GLB_CR_GPIO_DMA_PARK_VALUE
+#define GLB_CR_GPIO_DMA_PARK_VALUE_POS     (7U)
+#define GLB_CR_GPIO_DMA_PARK_VALUE_LEN     (1U)
+#define GLB_CR_GPIO_DMA_PARK_VALUE_MSK     (((1U << GLB_CR_GPIO_DMA_PARK_VALUE_LEN) - 1) << GLB_CR_GPIO_DMA_PARK_VALUE_POS)
+#define GLB_CR_GPIO_DMA_PARK_VALUE_UMSK    (~(((1U << GLB_CR_GPIO_DMA_PARK_VALUE_LEN) - 1) << GLB_CR_GPIO_DMA_PARK_VALUE_POS))
+#define GLB_GPIO_TX_FIFO_CNT               GLB_GPIO_TX_FIFO_CNT
+#define GLB_GPIO_TX_FIFO_CNT_POS           (8U)
+#define GLB_GPIO_TX_FIFO_CNT_LEN           (8U)
+#define GLB_GPIO_TX_FIFO_CNT_MSK           (((1U << GLB_GPIO_TX_FIFO_CNT_LEN) - 1) << GLB_GPIO_TX_FIFO_CNT_POS)
+#define GLB_GPIO_TX_FIFO_CNT_UMSK          (~(((1U << GLB_GPIO_TX_FIFO_CNT_LEN) - 1) << GLB_GPIO_TX_FIFO_CNT_POS))
+#define GLB_CR_GPIO_TX_FIFO_TH             GLB_CR_GPIO_TX_FIFO_TH
+#define GLB_CR_GPIO_TX_FIFO_TH_POS         (16U)
+#define GLB_CR_GPIO_TX_FIFO_TH_LEN         (7U)
+#define GLB_CR_GPIO_TX_FIFO_TH_MSK         (((1U << GLB_CR_GPIO_TX_FIFO_TH_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_TH_POS)
+#define GLB_CR_GPIO_TX_FIFO_TH_UMSK        (~(((1U << GLB_CR_GPIO_TX_FIFO_TH_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_TH_POS))
+#define GLB_CR_GPIO_TX_END_MASK            GLB_CR_GPIO_TX_END_MASK
+#define GLB_CR_GPIO_TX_END_MASK_POS        (23U)
+#define GLB_CR_GPIO_TX_END_MASK_LEN        (1U)
+#define GLB_CR_GPIO_TX_END_MASK_MSK        (((1U << GLB_CR_GPIO_TX_END_MASK_LEN) - 1) << GLB_CR_GPIO_TX_END_MASK_POS)
+#define GLB_CR_GPIO_TX_END_MASK_UMSK       (~(((1U << GLB_CR_GPIO_TX_END_MASK_LEN) - 1) << GLB_CR_GPIO_TX_END_MASK_POS))
+#define GLB_CR_GPIO_TX_FIFO_MASK           GLB_CR_GPIO_TX_FIFO_MASK
+#define GLB_CR_GPIO_TX_FIFO_MASK_POS       (24U)
+#define GLB_CR_GPIO_TX_FIFO_MASK_LEN       (1U)
+#define GLB_CR_GPIO_TX_FIFO_MASK_MSK       (((1U << GLB_CR_GPIO_TX_FIFO_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_MASK_POS)
+#define GLB_CR_GPIO_TX_FIFO_MASK_UMSK      (~(((1U << GLB_CR_GPIO_TX_FIFO_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_MASK_POS))
+#define GLB_CR_GPIO_TX_FER_MASK            GLB_CR_GPIO_TX_FER_MASK
+#define GLB_CR_GPIO_TX_FER_MASK_POS        (25U)
+#define GLB_CR_GPIO_TX_FER_MASK_LEN        (1U)
+#define GLB_CR_GPIO_TX_FER_MASK_MSK        (((1U << GLB_CR_GPIO_TX_FER_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FER_MASK_POS)
+#define GLB_CR_GPIO_TX_FER_MASK_UMSK       (~(((1U << GLB_CR_GPIO_TX_FER_MASK_LEN) - 1) << GLB_CR_GPIO_TX_FER_MASK_POS))
+#define GLB_R_GPIO_TX_END_INT              GLB_R_GPIO_TX_END_INT
+#define GLB_R_GPIO_TX_END_INT_POS          (26U)
+#define GLB_R_GPIO_TX_END_INT_LEN          (1U)
+#define GLB_R_GPIO_TX_END_INT_MSK          (((1U << GLB_R_GPIO_TX_END_INT_LEN) - 1) << GLB_R_GPIO_TX_END_INT_POS)
+#define GLB_R_GPIO_TX_END_INT_UMSK         (~(((1U << GLB_R_GPIO_TX_END_INT_LEN) - 1) << GLB_R_GPIO_TX_END_INT_POS))
+#define GLB_R_GPIO_TX_FIFO_INT             GLB_R_GPIO_TX_FIFO_INT
+#define GLB_R_GPIO_TX_FIFO_INT_POS         (27U)
+#define GLB_R_GPIO_TX_FIFO_INT_LEN         (1U)
+#define GLB_R_GPIO_TX_FIFO_INT_MSK         (((1U << GLB_R_GPIO_TX_FIFO_INT_LEN) - 1) << GLB_R_GPIO_TX_FIFO_INT_POS)
+#define GLB_R_GPIO_TX_FIFO_INT_UMSK        (~(((1U << GLB_R_GPIO_TX_FIFO_INT_LEN) - 1) << GLB_R_GPIO_TX_FIFO_INT_POS))
+#define GLB_R_GPIO_TX_FER_INT              GLB_R_GPIO_TX_FER_INT
+#define GLB_R_GPIO_TX_FER_INT_POS          (28U)
+#define GLB_R_GPIO_TX_FER_INT_LEN          (1U)
+#define GLB_R_GPIO_TX_FER_INT_MSK          (((1U << GLB_R_GPIO_TX_FER_INT_LEN) - 1) << GLB_R_GPIO_TX_FER_INT_POS)
+#define GLB_R_GPIO_TX_FER_INT_UMSK         (~(((1U << GLB_R_GPIO_TX_FER_INT_LEN) - 1) << GLB_R_GPIO_TX_FER_INT_POS))
+#define GLB_CR_GPIO_TX_END_EN              GLB_CR_GPIO_TX_END_EN
+#define GLB_CR_GPIO_TX_END_EN_POS          (29U)
+#define GLB_CR_GPIO_TX_END_EN_LEN          (1U)
+#define GLB_CR_GPIO_TX_END_EN_MSK          (((1U << GLB_CR_GPIO_TX_END_EN_LEN) - 1) << GLB_CR_GPIO_TX_END_EN_POS)
+#define GLB_CR_GPIO_TX_END_EN_UMSK         (~(((1U << GLB_CR_GPIO_TX_END_EN_LEN) - 1) << GLB_CR_GPIO_TX_END_EN_POS))
+#define GLB_CR_GPIO_TX_FIFO_EN             GLB_CR_GPIO_TX_FIFO_EN
+#define GLB_CR_GPIO_TX_FIFO_EN_POS         (30U)
+#define GLB_CR_GPIO_TX_FIFO_EN_LEN         (1U)
+#define GLB_CR_GPIO_TX_FIFO_EN_MSK         (((1U << GLB_CR_GPIO_TX_FIFO_EN_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_EN_POS)
+#define GLB_CR_GPIO_TX_FIFO_EN_UMSK        (~(((1U << GLB_CR_GPIO_TX_FIFO_EN_LEN) - 1) << GLB_CR_GPIO_TX_FIFO_EN_POS))
+#define GLB_CR_GPIO_TX_FER_EN              GLB_CR_GPIO_TX_FER_EN
+#define GLB_CR_GPIO_TX_FER_EN_POS          (31U)
+#define GLB_CR_GPIO_TX_FER_EN_LEN          (1U)
+#define GLB_CR_GPIO_TX_FER_EN_MSK          (((1U << GLB_CR_GPIO_TX_FER_EN_LEN) - 1) << GLB_CR_GPIO_TX_FER_EN_POS)
+#define GLB_CR_GPIO_TX_FER_EN_UMSK         (~(((1U << GLB_CR_GPIO_TX_FER_EN_LEN) - 1) << GLB_CR_GPIO_TX_FER_EN_POS))
+
+/* 0xB04 : gpio_cfg144 */
+#define GLB_GPIO_CFG144_OFFSET        (0xB04)
+#define GLB_GPIO_TX_DATA_TO_FIFO      GLB_GPIO_TX_DATA_TO_FIFO
+#define GLB_GPIO_TX_DATA_TO_FIFO_POS  (0U)
+#define GLB_GPIO_TX_DATA_TO_FIFO_LEN  (16U)
+#define GLB_GPIO_TX_DATA_TO_FIFO_MSK  (((1U << GLB_GPIO_TX_DATA_TO_FIFO_LEN) - 1) << GLB_GPIO_TX_DATA_TO_FIFO_POS)
+#define GLB_GPIO_TX_DATA_TO_FIFO_UMSK (~(((1U << GLB_GPIO_TX_DATA_TO_FIFO_LEN) - 1) << GLB_GPIO_TX_DATA_TO_FIFO_POS))
+
+struct glb_reg {
+    /* 0x0 : soc_info0 */
+    union {
+        struct {
+            uint32_t reserved_0_26 : 27; /* [26: 0],       rsvd,        0x0 */
+            uint32_t chip_rdy      : 1;  /* [   27],          r,        0x0 */
+            uint32_t glb_id        : 4;  /* [31:28],          r,        0x6 */
+        } BF;
+        uint32_t WORD;
+    } soc_info0;
+
+    /* 0x4  reserved */
+    uint8_t RESERVED0x4[76];
+
+    /* 0x50 : core_cfg16 */
+    union {
+        struct {
+            uint32_t np_int_sta0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } core_cfg16;
+
+    /* 0x54 : core_cfg17 */
+    union {
+        struct {
+            uint32_t np_int_sta1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } core_cfg17;
+
+    /* 0x58 : core_cfg18 */
+    union {
+        struct {
+            uint32_t np_int_mask0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } core_cfg18;
+
+    /* 0x5C : core_cfg19 */
+    union {
+        struct {
+            uint32_t np_int_mask1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } core_cfg19;
+
+    /* 0x60 : core_cfg20 */
+    union {
+        struct {
+            uint32_t np_int_clr0 : 32; /* [31: 0],        w1c,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } core_cfg20;
+
+    /* 0x64 : core_cfg21 */
+    union {
+        struct {
+            uint32_t np_int_clr1 : 32; /* [31: 0],        w1c,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } core_cfg21;
+
+    /* 0x68  reserved */
+    uint8_t RESERVED0x68[40];
+
+    /* 0x90 : sys_cfg0 */
+    union {
+        struct {
+            uint32_t reg_pll_en       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_fclk_en      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_hclk_en      : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reg_bclk_en      : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_5     : 2; /* [ 5: 4],       rsvd,        0x0 */
+            uint32_t hbn_root_clk_sel : 2; /* [ 7: 6],          r,        0x0 */
+            uint32_t reg_hclk_div     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_bclk_div     : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reserved_24_31   : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sys_cfg0;
+
+    /* 0x94 : sys_cfg1 */
+    union {
+        struct {
+            uint32_t reg_bclk_div_act_pulse : 1;  /* [    0],        w1p,        0x0 */
+            uint32_t reg_bclk_div_bypass    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t sts_bclk_prot_done     : 1;  /* [    2],          r,        0x1 */
+            uint32_t reserved_3             : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t reg_bclk_sw_done_cnt   : 4;  /* [ 7: 4],        r/w,        0x5 */
+            uint32_t reserved_8_23          : 16; /* [23: 8],       rsvd,        0x0 */
+            uint32_t fclk_sw_state          : 3;  /* [26:24],          r,        0x0 */
+            uint32_t reserved_27_31         : 5;  /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sys_cfg1;
+
+    /* 0x98  reserved */
+    uint8_t RESERVED0x98[8];
+
+    /* 0xA0 : bus_cfg0 */
+    union {
+        struct {
+            uint32_t rg_apb2_pck_force : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t rg_apb_pck_force  : 16; /* [31:16],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } bus_cfg0;
+
+    /* 0xa4  reserved */
+    uint8_t RESERVED0xa4[76];
+
+    /* 0xF0 : rtc_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rtc_cfg0;
+
+    /* 0xf4  reserved */
+    uint8_t RESERVED0xf4[28];
+
+    /* 0x110 : adc_cfg0 */
+    union {
+        struct {
+            uint32_t gpadc_32m_clk_div : 6;  /* [ 5: 0],        r/w,        0x2 */
+            uint32_t reserved_6        : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t gpadc_32m_clk_sel : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_32m_div_en  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31     : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } adc_cfg0;
+
+    /* 0x114  reserved */
+    uint8_t RESERVED0x114[12];
+
+    /* 0x120 : dac_cfg0 */
+    union {
+        struct {
+            uint32_t gpdaca_rstn_ana   : 1; /* [    0],        r/w,        0x1 */
+            uint32_t gpdacb_rstn_ana   : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_6      : 5; /* [ 6: 2],       rsvd,        0x0 */
+            uint32_t gpdac_test_en     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t gpdac_ref_sel     : 1; /* [    8],        r/w,        0x0 */
+            uint32_t gpdac_test_sel    : 3; /* [11: 9],        r/w,        0x0 */
+            uint32_t gpdac_ana_clk_sel : 1; /* [   12],        r/w,        0x0 */
+            uint32_t gpdac_dat_cha_sel : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpdac_dat_chb_sel : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reserved_15_23    : 9; /* [23:15],       rsvd,        0x0 */
+            uint32_t gpdac_reserved    : 8; /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } dac_cfg0;
+
+    /* 0x124 : dac_cfg1 */
+    union {
+        struct {
+            uint32_t gpdac_a_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_ioa_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_a_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_a_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dac_cfg1;
+
+    /* 0x128 : dac_cfg2 */
+    union {
+        struct {
+            uint32_t gpdac_b_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_iob_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_b_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_b_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dac_cfg2;
+
+    /* 0x12C : dac_cfg3 */
+    union {
+        struct {
+            uint32_t gpdac_b_data   : 12; /* [11: 0],        r/w,        0x0 */
+            uint32_t reserved_12_15 : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t gpdac_a_data   : 12; /* [27:16],        r/w,        0x0 */
+            uint32_t reserved_28_31 : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dac_cfg3;
+
+    /* 0x130 : dma_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_23 : 24; /* [23: 0],       rsvd,        0x0 */
+            uint32_t dma_clk_en    : 8;  /* [31:24],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } dma_cfg0;
+
+    /* 0x134 : dma_cfg1 */
+    union {
+        struct {
+            uint32_t reserved_0_23 : 24; /* [23: 0],       rsvd,        0x0 */
+            uint32_t dma2_clk_en   : 8;  /* [31:24],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } dma_cfg1;
+
+    /* 0x138 : dma_cfg2 */
+    union {
+        struct {
+            uint32_t reg_dma_cn_sel : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dma_cfg2;
+
+    /* 0x13c  reserved */
+    uint8_t RESERVED0x13c[4];
+
+    /* 0x140 : ir_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_15  : 16; /* [15: 0],       rsvd,        0x0 */
+            uint32_t ir_clk_div     : 6;  /* [21:16],        r/w,        0xf */
+            uint32_t reserved_22    : 1;  /* [   22],       rsvd,        0x0 */
+            uint32_t ir_clk_en      : 1;  /* [   23],        r/w,        0x1 */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ir_cfg0;
+
+    /* 0x144 : ir_cfg1 */
+    union {
+        struct {
+            uint32_t reserved_0_7   : 8;  /* [ 7: 0],       rsvd,        0x0 */
+            uint32_t ir_rx_gpio_sel : 4;  /* [11: 8],        r/w,        0x0 */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ir_cfg1;
+
+    /* 0x148  reserved */
+    uint8_t RESERVED0x148[8];
+
+    /* 0x150 : uart_cfg0 */
+    union {
+        struct {
+            uint32_t uart_clk_div      : 3;  /* [ 2: 0],        r/w,        0x7 */
+            uint32_t reserved_3        : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t uart_clk_en       : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_6      : 2;  /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t hbn_uart_clk_sel  : 1;  /* [    7],          r,        0x0 */
+            uint32_t reserved_8_21     : 14; /* [21: 8],       rsvd,        0x0 */
+            uint32_t hbn_uart_clk_sel2 : 1;  /* [   22],          r,        0x0 */
+            uint32_t reserved_23_31    : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_cfg0;
+
+    /* 0x154 : uart_cfg1 */
+    union {
+        struct {
+            uint32_t uart_sig_0_sel : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t uart_sig_1_sel : 4; /* [ 7: 4],        r/w,        0x1 */
+            uint32_t uart_sig_2_sel : 4; /* [11: 8],        r/w,        0x2 */
+            uint32_t uart_sig_3_sel : 4; /* [15:12],        r/w,        0x3 */
+            uint32_t uart_sig_4_sel : 4; /* [19:16],        r/w,        0x4 */
+            uint32_t uart_sig_5_sel : 4; /* [23:20],        r/w,        0x5 */
+            uint32_t uart_sig_6_sel : 4; /* [27:24],        r/w,        0x8 */
+            uint32_t uart_sig_7_sel : 4; /* [31:28],        r/w,        0x9 */
+        } BF;
+        uint32_t WORD;
+    } uart_cfg1;
+
+    /* 0x158 : uart_cfg2 */
+    union {
+        struct {
+            uint32_t uart_sig_8_sel  : 4;  /* [ 3: 0],        r/w,        0x6 */
+            uint32_t uart_sig_9_sel  : 4;  /* [ 7: 4],        r/w,        0x7 */
+            uint32_t uart_sig_10_sel : 4;  /* [11: 8],        r/w,        0xa */
+            uint32_t uart_sig_11_sel : 4;  /* [15:12],        r/w,        0xb */
+            uint32_t reserved_16_31  : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } uart_cfg2;
+
+    /* 0x15c  reserved */
+    uint8_t RESERVED0x15c[20];
+
+    /* 0x170 : sf_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_7   : 8;  /* [ 7: 0],       rsvd,        0x0 */
+            uint32_t sf_clk_div     : 3;  /* [10: 8],        r/w,        0x3 */
+            uint32_t sf_clk_en      : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t sf_clk_sel     : 2;  /* [13:12],        r/w,        0x2 */
+            uint32_t sf_clk_sel2    : 2;  /* [15:14],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_cfg0;
+
+    /* 0x174  reserved */
+    uint8_t RESERVED0x174[12];
+
+    /* 0x180 : i2c_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_15  : 16; /* [15: 0],       rsvd,        0x0 */
+            uint32_t i2c_clk_div    : 8;  /* [23:16],        r/w,       0xff */
+            uint32_t i2c_clk_en     : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t i2c_clk_sel    : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2c_cfg0;
+
+    /* 0x184  reserved */
+    uint8_t RESERVED0x184[12];
+
+    /* 0x190 : i2s_cfg0 */
+    union {
+        struct {
+            uint32_t reg_i2s_ref_clk_div    : 6;  /* [ 5: 0],        r/w,        0x1 */
+            uint32_t reg_i2s_di_ref_clk_sel : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reg_i2s_ref_clk_en     : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t reg_i2s_do_ref_clk_sel : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31          : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } i2s_cfg0;
+
+    /* 0x194  reserved */
+    uint8_t RESERVED0x194[28];
+
+    /* 0x1B0 : spi_cfg0 */
+    union {
+        struct {
+            uint32_t spi_clk_div    : 5;  /* [ 4: 0],        r/w,        0x3 */
+            uint32_t reserved_5_7   : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t spi_clk_en     : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t spi_clk_sel    : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_15 : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t spi_swap_set   : 4;  /* [19:16],        r/w,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } spi_cfg0;
+
+    /* 0x1b4  reserved */
+    uint8_t RESERVED0x1b4[12];
+
+    /* 0x1C0 : pio_cfg0 */
+    union {
+        struct {
+            uint32_t pio_clk_div    : 5;  /* [ 4: 0],        r/w,        0x3 */
+            uint32_t reserved_5_7   : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t pio_clk_en     : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t pio_clk_sel    : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pio_cfg0;
+
+    /* 0x1c4  reserved */
+    uint8_t RESERVED0x1c4[12];
+
+    /* 0x1D0 : pwm_cfg0 */
+    union {
+        struct {
+            uint32_t reg_pwm1_io_sel : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31   : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pwm_cfg0;
+
+    /* 0x1d4  reserved */
+    uint8_t RESERVED0x1d4[12];
+
+    /* 0x1E0 : pdm_cfg0 */
+    union {
+        struct {
+            uint32_t reg_pdm_io_sel : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31  : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pdm_cfg0;
+
+    /* 0x1e4  reserved */
+    uint8_t RESERVED0x1e4[12];
+
+    /* 0x1F0 : dbi_cfg0 */
+    union {
+        struct {
+            uint32_t dbi_clk_div    : 5;  /* [ 4: 0],        r/w,        0x3 */
+            uint32_t reserved_5_7   : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t dbi_clk_en     : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t dbi_clk_sel    : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dbi_cfg0;
+
+    /* 0x1f4  reserved */
+    uint8_t RESERVED0x1f4[92];
+
+    /* 0x250 : dig_clk_cfg0 */
+    union {
+        struct {
+            uint32_t dig_32k_div            : 11; /* [10: 0],        r/w,      0x3e8 */
+            uint32_t reserved_11            : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t dig_32k_en             : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t dig_32k_comp           : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15         : 2;  /* [15:14],       rsvd,        0x0 */
+            uint32_t dig_512k_div           : 7;  /* [22:16],        r/w,       0x3e */
+            uint32_t reserved_23            : 1;  /* [   23],       rsvd,        0x0 */
+            uint32_t dig_512k_en            : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t dig_512k_comp          : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t reserved_26_27         : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t dig_clk_src_sel        : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t reserved_30            : 1;  /* [   30],       rsvd,        0x0 */
+            uint32_t reg_en_platform_wakeup : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dig_clk_cfg0;
+
+    /* 0x254 : dig_clk_cfg1 */
+    union {
+        struct {
+            uint32_t reg_isp_muxpll_80m_sel  : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7            : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t reg_top_muxpll_80m_sel  : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reg_top_muxpll_160m_sel : 2;  /* [11:10],        r/w,        0x0 */
+            uint32_t reserved_12_31          : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dig_clk_cfg1;
+
+    /* 0x258 : dig_clk_cfg2 */
+    union {
+        struct {
+            uint32_t chip_clk_out_0_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t chip_clk_out_1_sel : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t chip_clk_out_2_sel : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t chip_clk_out_3_sel : 2;  /* [ 7: 6],        r/w,        0x0 */
+            uint32_t chip_clk_out_0_en  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t chip_clk_out_1_en  : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t chip_clk_out_2_en  : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t chip_clk_out_3_en  : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t gpio_tmr_clk_sel   : 2;  /* [13:12],        r/w,        0x0 */
+            uint32_t reserved_14_31     : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dig_clk_cfg2;
+
+    /* 0x25C : dig_clk_cfg3 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dig_clk_cfg3;
+
+    /* 0x260 : rf_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rf_cfg0;
+
+    /* 0x264  reserved */
+    uint8_t RESERVED0x264[124];
+
+    /* 0x2E0 : dbg_cfg0 */
+    union {
+        struct {
+            uint32_t reg_dbg_ll_ctrl : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reg_dbg_ll_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dbg_cfg0;
+
+    /* 0x2E4 : dbg_cfg1 */
+    union {
+        struct {
+            uint32_t reg_dbg_lh_ctrl : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reg_dbg_lh_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dbg_cfg1;
+
+    /* 0x2E8 : dbg_cfg2 */
+    union {
+        struct {
+            uint32_t reg_dbg_hl_ctrl : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reg_dbg_hl_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dbg_cfg2;
+
+    /* 0x2EC : dbg_cfg3 */
+    union {
+        struct {
+            uint32_t reg_dbg_hh_ctrl : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reg_dbg_hh_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dbg_cfg3;
+
+    /* 0x2F0 : dbg_cfg4 */
+    union {
+        struct {
+            uint32_t debug_oe : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t debug_i  : 31; /* [31: 1],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dbg_cfg4;
+
+    /* 0x2f4  reserved */
+    uint8_t RESERVED0x2f4[12];
+
+    /* 0x300 : mbist_cfg0 */
+    union {
+        struct {
+            uint32_t ocram_mbist_mode           : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t wram_mbist_mode            : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_7               : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_wram_ocram_mbist_rst_n : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_15              : 7; /* [15: 9],       rsvd,        0x0 */
+            uint32_t ocram_mbist_done           : 4; /* [19:16],          r,        0x0 */
+            uint32_t wram_mbist_done            : 2; /* [21:20],          r,        0x0 */
+            uint32_t reserved_22_23             : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t ocram_mbist_fail           : 4; /* [27:24],          r,        0x0 */
+            uint32_t wram_mbist_fail            : 2; /* [29:28],          r,        0x0 */
+            uint32_t reserved_30_31             : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mbist_cfg0;
+
+    /* 0x304 : mbist_cfg1 */
+    union {
+        struct {
+            uint32_t top_mbist_mode      : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_7        : 7; /* [ 7: 1],       rsvd,        0x0 */
+            uint32_t reg_top_mbist_rst_n : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_15       : 7; /* [15: 9],       rsvd,        0x0 */
+            uint32_t ef_mbist_done       : 2; /* [17:16],          r,        0x0 */
+            uint32_t usb_mbist_done      : 1; /* [   18],          r,        0x0 */
+            uint32_t sdh_mbist_done      : 1; /* [   19],          r,        0x0 */
+            uint32_t sec_mbist_done      : 1; /* [   20],          r,        0x0 */
+            uint32_t sf_mbist_done       : 1; /* [   21],          r,        0x0 */
+            uint32_t emac_mbist_done     : 1; /* [   22],          r,        0x0 */
+            uint32_t reserved_23         : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t ef_mbist_fail       : 2; /* [25:24],          r,        0x0 */
+            uint32_t usb_mbist_fail      : 1; /* [   26],          r,        0x0 */
+            uint32_t sdh_mbist_fail      : 1; /* [   27],          r,        0x0 */
+            uint32_t sec_mbist_fail      : 1; /* [   28],          r,        0x0 */
+            uint32_t sf_mbist_fail       : 1; /* [   29],          r,        0x0 */
+            uint32_t emac_mbist_fail     : 1; /* [   30],          r,        0x0 */
+            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mbist_cfg1;
+
+    /* 0x308  reserved */
+    uint8_t RESERVED0x308[24];
+
+    /* 0x320 : bmx_cfg0 */
+    union {
+        struct {
+            uint32_t reg_bmx_timeout_en  : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t reserved_4          : 1; /* [    4],       rsvd,        0x0 */
+            uint32_t reg_bmx_arb_mode    : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_bmx_timeout_clr : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7_10       : 4; /* [10: 7],       rsvd,        0x0 */
+            uint32_t sts_bmx_timeout_sts : 4; /* [14:11],          r,        0x0 */
+            uint32_t reserved_15         : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t pds_apb_cfg         : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t hbn_apb_cfg         : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg0;
+
+    /* 0x324 : bmx_cfg1 */
+    union {
+        struct {
+            uint32_t reg_bmx_berr_int_en : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_mcu_berr_int_en : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_15       : 14; /* [15: 2],       rsvd,        0x0 */
+            uint32_t reg_bmx_qos_cpu     : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_sdu     : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_sec0    : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_sec1    : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_sec2    : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_dma     : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_cci     : 1;  /* [   22],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_pldma   : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_blem    : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t reg_bmx_qos_emacA   : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t reserved_26         : 1;  /* [   26],       rsvd,        0x0 */
+            uint32_t reg_bmx_qos_sdhm    : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t bmx_dbg_sel         : 4;  /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg1;
+
+    /* 0x328 : bmx_cfg2 */
+    union {
+        struct {
+            uint32_t reg_bmx_berr_en : 10; /* [ 9: 0],        r/w,      0x3ff */
+            uint32_t reserved_10_15  : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t reg_mcu_berr_en : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reserved_17_31  : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg2;
+
+    /* 0x32C : bmx_cfg3 */
+    union {
+        struct {
+            uint32_t reg_bmx_berr_clr   : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_bmx_berr_last  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t reg_mcu_berr_clr   : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_mcu_berr_last  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6; /* [15:10],       rsvd,        0x0 */
+            uint32_t sts_bmx_berr       : 1; /* [   16],          r,        0x0 */
+            uint32_t sts_mcu_berr       : 1; /* [   17],          r,        0x0 */
+            uint32_t reserved_18_23     : 6; /* [23:18],       rsvd,        0x0 */
+            uint32_t sts_bmx_berr_write : 1; /* [   24],          r,        0x0 */
+            uint32_t sts_mcu_berr_write : 1; /* [   25],          r,        0x0 */
+            uint32_t reserved_26_31     : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg3;
+
+    /* 0x330 : bmx_cfg4 */
+    union {
+        struct {
+            uint32_t sts_bmx_berr_src : 10; /* [ 9: 0],          r,        0x0 */
+            uint32_t reserved_10_15   : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sts_mcu_berr_src : 1;  /* [   16],          r,        0x0 */
+            uint32_t reserved_17_23   : 7;  /* [23:17],       rsvd,        0x0 */
+            uint32_t sts_mcu_berr_id  : 8;  /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg4;
+
+    /* 0x334 : bmx_cfg5 */
+    union {
+        struct {
+            uint32_t sts_bmx_berr_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg5;
+
+    /* 0x338 : bmx_cfg6 */
+    union {
+        struct {
+            uint32_t sts_mcu_berr_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg6;
+
+    /* 0x33c  reserved */
+    uint8_t RESERVED0x33c[4];
+
+    /* 0x340 : audio_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_7          : 8;  /* [ 7: 0],       rsvd,        0x0 */
+            uint32_t reg_audio_adc_clk_div : 6;  /* [13: 8],        r/w,        0x3 */
+            uint32_t reserved_14           : 1;  /* [   14],       rsvd,        0x0 */
+            uint32_t reg_audio_adc_clk_en  : 1;  /* [   15],        r/w,        0x1 */
+            uint32_t reserved_16_30        : 15; /* [30:16],       rsvd,        0x0 */
+            uint32_t reg_audio_auto_div_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } audio_cfg0;
+
+    /* 0x344 : audio_cfg1 */
+    union {
+        struct {
+            uint32_t reserved_0_15          : 16; /* [15: 0],       rsvd,        0x0 */
+            uint32_t reg_audio_solo_clk_div : 8;  /* [23:16],        r/w,        0x3 */
+            uint32_t reg_audio_solo_clk_en  : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_31         : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } audio_cfg1;
+
+    /* 0x348  reserved */
+    uint8_t RESERVED0x348[72];
+
+    /* 0x390 : eth_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_4          : 5;  /* [ 4: 0],       rsvd,        0x0 */
+            uint32_t cfg_sel_eth_ref_clk_o : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t cfg_inv_eth_ref_clk_o : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t cfg_inv_eth_tx_clk    : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t reserved_8_9          : 2;  /* [ 9: 8],       rsvd,        0x0 */
+            uint32_t cfg_inv_eth_rx_clk    : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_31        : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } eth_cfg0;
+
+    /* 0x394  reserved */
+    uint8_t RESERVED0x394[140];
+
+    /* 0x420 : cam_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_26           : 27; /* [26: 0],       rsvd,        0x0 */
+            uint32_t reg_cam_ref_clk_en      : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t reg_cam_ref_clk_src_sel : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t reg_cam_ref_clk_div     : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cam_cfg0;
+
+    /* 0x424  reserved */
+    uint8_t RESERVED0x424[12];
+
+    /* 0x430 : sdh_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_8    : 9;  /* [ 8: 0],       rsvd,        0x0 */
+            uint32_t reg_sdh_clk_div : 3;  /* [11: 9],        r/w,        0x0 */
+            uint32_t reg_sdh_clk_sel : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reg_sdh_clk_en  : 1;  /* [   13],        r/w,        0x1 */
+            uint32_t reserved_14_31  : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sdh_cfg0;
+
+    /* 0x434  reserved */
+    uint8_t RESERVED0x434[12];
+
+    /* 0x440 : sdio_cfg0 */
+    union {
+        struct {
+            uint32_t reg_sdio_int_sys_dis : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_sd_rst_sd_dis    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_sdu_rst_sd_dis   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reg_sys_rst_sd_en    : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_11        : 8;  /* [11: 4],       rsvd,        0x0 */
+            uint32_t sdu_cmdRcvd          : 1;  /* [   12],          r,        0x0 */
+            uint32_t sdu_clk_switch_ok    : 1;  /* [   13],          r,        0x0 */
+            uint32_t sd_pwup              : 1;  /* [   14],          r,        0x0 */
+            uint32_t reserved_15          : 1;  /* [   15],       rsvd,        0x0 */
+            uint32_t sdu_dbg              : 16; /* [31:16],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sdio_cfg0;
+
+    /* 0x444  reserved */
+    uint8_t RESERVED0x444[76];
+
+    /* 0x490 : tzc_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_11           : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t tzc_glb_pwron_rst_lock  : 1;  /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_cpu_reset_lock  : 1;  /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_sys_reset_lock  : 1;  /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_cpu2_reset_lock : 1;  /* [   15],          r,        0x0 */
+            uint32_t reserved_16_20          : 5;  /* [20:16],       rsvd,        0x0 */
+            uint32_t tzc_glb_pwr_lock        : 1;  /* [   21],          r,        0x0 */
+            uint32_t tzc_glb_int_lock        : 1;  /* [   22],          r,        0x0 */
+            uint32_t reserved_23             : 1;  /* [   23],       rsvd,        0x0 */
+            uint32_t tzc_glb_cpupll_lock     : 1;  /* [   24],          r,        0x0 */
+            uint32_t tzc_glb_misc_lock       : 1;  /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_sram_lock       : 1;  /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_swrst_lock      : 1;  /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_bmx_lock        : 1;  /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_dbg_lock        : 1;  /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_mbist_lock      : 1;  /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_clk_lock        : 1;  /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_cfg0;
+
+    /* 0x494  reserved */
+    uint8_t RESERVED0x494[124];
+
+    /* 0x510 : glb_parm_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_1           : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t uart_swap_set          : 4; /* [ 5: 2],        r/w,        0x0 */
+            uint32_t reserved_6_7           : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t swap_sflash_io_3_io_0  : 1; /* [    8],        r/w,        0x1 */
+            uint32_t sel_embedded_sflash    : 1; /* [    9],        r/w,        0x1 */
+            uint32_t swap_sflash_io_2_cs    : 1; /* [   10],        r/w,        0x0 */
+            uint32_t swap_sflash2_io_3_io_0 : 1; /* [   11],        r/w,        0x1 */
+            uint32_t reg_spi_0_master_mode  : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_spi_0_swap         : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14            : 1; /* [   14],       rsvd,        0x0 */
+            uint32_t ant_switch_sel         : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reserved_16_18         : 3; /* [18:16],       rsvd,        0x0 */
+            uint32_t p3_cci_use_io_10_13    : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20_28         : 9; /* [28:20],       rsvd,        0x0 */
+            uint32_t audio_test_mode        : 1; /* [   29],        r/w,        0x0 */
+            uint32_t sel_rf_audio_test      : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } glb_parm_cfg0;
+
+    /* 0x514  reserved */
+    uint8_t RESERVED0x514[12];
+
+    /* 0x520 : debug_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } debug_cfg0;
+
+    /* 0x524 : debug_cfg1 */
+    union {
+        struct {
+            uint32_t reserved_0_19      : 20; /* [19: 0],       rsvd,        0x0 */
+            uint32_t debug_ndreset_gate : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31     : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } debug_cfg1;
+
+    /* 0x528  reserved */
+    uint8_t RESERVED0x528[8];
+
+    /* 0x530 : reset_sts0 */
+    union {
+        struct {
+            uint32_t top_reset_recorder     : 7;  /* [ 6: 0],          r,        0x0 */
+            uint32_t clr_top_reset_recorder : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_31          : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } reset_sts0;
+
+    /* 0x534  reserved */
+    uint8_t RESERVED0x534[12];
+
+    /* 0x540 : swrst_s1_ext + swrst_s3 + swrst_s2 */
+    union {
+        struct {
+            uint32_t swrst_s00                : 1; /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s01                : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3             : 2; /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t swrst_s20                : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_7             : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t swrst_s30                : 1; /* [    8],        r/w,        0x0 */
+            uint32_t swrst_s31                : 1; /* [    9],        r/w,        0x0 */
+            uint32_t swrst_s32                : 1; /* [   10],        r/w,        0x0 */
+            uint32_t swrst_s33                : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15           : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t swrst_s1_ext_emi_misc    : 1; /* [   16],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_psram0_ctrl : 1; /* [   17],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_psram1_ctrl : 1; /* [   18],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_usb         : 1; /* [   19],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_mix2        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_audio       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_sdh         : 1; /* [   22],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_emac        : 1; /* [   23],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_dma2        : 1; /* [   24],        r/w,        0x0 */
+            uint32_t swrst_d2xA               : 1; /* [   25],        r/w,        0x0 */
+            uint32_t swrst_d2xB               : 1; /* [   26],        r/w,        0x0 */
+            uint32_t swrst_jenc               : 1; /* [   27],        r/w,        0x0 */
+            uint32_t swrst_s1_ext_pio         : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29_31           : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg0;
+
+    /* 0x544 : swrst_s1 */
+    union {
+        struct {
+            uint32_t swrst_s10  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s11  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t swrst_s12  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t swrst_s13  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t swrst_s14  : 1; /* [    4],        r/w,        0x0 */
+            uint32_t swrst_s15  : 1; /* [    5],        r/w,        0x0 */
+            uint32_t swrst_s16  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t swrst_s17  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t swrst_s18  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t swrst_s19  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t swrst_s1a  : 1; /* [   10],        r/w,        0x0 */
+            uint32_t swrst_s1b  : 1; /* [   11],        r/w,        0x0 */
+            uint32_t swrst_s1c  : 1; /* [   12],        r/w,        0x0 */
+            uint32_t swrst_s1d  : 1; /* [   13],        r/w,        0x0 */
+            uint32_t swrst_s1e  : 1; /* [   14],        r/w,        0x0 */
+            uint32_t swrst_s1f  : 1; /* [   15],        r/w,        0x0 */
+            uint32_t swrst_s1a0 : 1; /* [   16],        r/w,        0x0 */
+            uint32_t swrst_s1a1 : 1; /* [   17],        r/w,        0x0 */
+            uint32_t swrst_s1a2 : 1; /* [   18],        r/w,        0x0 */
+            uint32_t swrst_s1a3 : 1; /* [   19],        r/w,        0x0 */
+            uint32_t swrst_s1a4 : 1; /* [   20],        r/w,        0x0 */
+            uint32_t swrst_s1a5 : 1; /* [   21],        r/w,        0x0 */
+            uint32_t swrst_s1a6 : 1; /* [   22],        r/w,        0x0 */
+            uint32_t swrst_s1a7 : 1; /* [   23],        r/w,        0x0 */
+            uint32_t swrst_s1a8 : 1; /* [   24],        r/w,        0x0 */
+            uint32_t swrst_s1a9 : 1; /* [   25],        r/w,        0x0 */
+            uint32_t swrst_s1aa : 1; /* [   26],        r/w,        0x0 */
+            uint32_t swrst_s1ab : 1; /* [   27],        r/w,        0x0 */
+            uint32_t swrst_s1ac : 1; /* [   28],        r/w,        0x0 */
+            uint32_t swrst_s1ad : 1; /* [   29],        r/w,        0x0 */
+            uint32_t swrst_s1ae : 1; /* [   30],        r/w,        0x0 */
+            uint32_t swrst_s1af : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg1;
+
+    /* 0x548 : swrst_cfg2 */
+    union {
+        struct {
+            uint32_t reg_ctrl_pwron_rst   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_ctrl_cpu_reset   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_ctrl_sys_reset   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reg_ctrl_pico_reset  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reg_ctrl_cpu2_reset  : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reg_ctrl_chip_reset  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_23        : 18; /* [23: 6],       rsvd,        0x0 */
+            uint32_t pka_clk_sel          : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t reserved_25_27       : 3;  /* [27:25],       rsvd,        0x0 */
+            uint32_t reg_ctrl_reset_dummy : 4;  /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg2;
+
+    /* 0x54C : Disable hreset */
+    union {
+        struct {
+            uint32_t reserved_0_1   : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t disrst_s12     : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3     : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t disrst_s14     : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_7   : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t disrst_s18     : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_10  : 2; /* [10: 9],       rsvd,        0x0 */
+            uint32_t disrst_s1b     : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15 : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t disrst_s1a0    : 1; /* [   16],        r/w,        0x0 */
+            uint32_t disrst_s1a1    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t disrst_s1a2    : 1; /* [   18],        r/w,        0x0 */
+            uint32_t disrst_s1a3    : 1; /* [   19],        r/w,        0x0 */
+            uint32_t disrst_s1a4    : 1; /* [   20],        r/w,        0x0 */
+            uint32_t disrst_s1a5    : 1; /* [   21],        r/w,        0x0 */
+            uint32_t disrst_s1a6    : 1; /* [   22],        r/w,        0x0 */
+            uint32_t disrst_s1a7    : 1; /* [   23],        r/w,        0x0 */
+            uint32_t disrst_s1a8    : 1; /* [   24],        r/w,        0x0 */
+            uint32_t disrst_s1a9    : 1; /* [   25],        r/w,        0x0 */
+            uint32_t disrst_s1aa    : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31 : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg3;
+
+    /* 0x550  reserved */
+    uint8_t RESERVED0x550[48];
+
+    /* 0x580 : cgen_m */
+    union {
+        struct {
+            uint32_t cgen_m_cpu    : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t cgen_m_sdu    : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t cgen_m_sec    : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t cgen_m_dma    : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t cgen_m_cci    : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_31 : 27; /* [31: 5],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg0;
+
+    /* 0x584 : cgen_s1a + cgen_s1 */
+    union {
+        struct {
+            uint32_t cgen_s1_rsvd0   : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1      : 1; /* [    1],       rsvd,        0x0 */
+            uint32_t cgen_s1_gpip    : 1; /* [    2],        r/w,        0x1 */
+            uint32_t cgen_s1_sec_dbg : 1; /* [    3],        r/w,        0x1 */
+            uint32_t cgen_s1_sec_eng : 1; /* [    4],        r/w,        0x1 */
+            uint32_t cgen_s1_tz      : 1; /* [    5],        r/w,        0x1 */
+            uint32_t cgen_s1_rsvd6   : 1; /* [    6],        r/w,        0x1 */
+            uint32_t cgen_s1_ef_ctrl : 1; /* [    7],        r/w,        0x1 */
+            uint32_t cgen_s1_rsvd8   : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cgen_s1_rsvd9   : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cgen_s1_rsvd10  : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cgen_s1_sf_ctrl : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cgen_s1_dma     : 1; /* [   12],        r/w,        0x0 */
+            uint32_t cgen_s1_rsvd13  : 1; /* [   13],        r/w,        0x0 */
+            uint32_t cgen_s1_rsvd14  : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cgen_s1_rsvd15  : 1; /* [   15],        r/w,        0x1 */
+            uint32_t cgen_s1a_uart0  : 1; /* [   16],        r/w,        0x1 */
+            uint32_t cgen_s1a_uart1  : 1; /* [   17],        r/w,        0x1 */
+            uint32_t cgen_s1a_spi    : 1; /* [   18],        r/w,        0x0 */
+            uint32_t cgen_s1a_i2c    : 1; /* [   19],        r/w,        0x0 */
+            uint32_t cgen_s1a_pwm    : 1; /* [   20],        r/w,        0x0 */
+            uint32_t cgen_s1a_timer  : 1; /* [   21],        r/w,        0x1 */
+            uint32_t cgen_s1a_ir     : 1; /* [   22],        r/w,        0x0 */
+            uint32_t cgen_s1a_cks    : 1; /* [   23],        r/w,        0x0 */
+            uint32_t cgen_s1a_dbi    : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cgen_s1a_i2c1   : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cgen_s1a_uart2  : 1; /* [   26],        r/w,        0x0 */
+            uint32_t cgen_s1a_rsvd11 : 1; /* [   27],        r/w,        0x1 */
+            uint32_t cgen_s1a_rsvd12 : 1; /* [   28],        r/w,        0x1 */
+            uint32_t cgen_s1a_rsvd13 : 1; /* [   29],        r/w,        0x0 */
+            uint32_t cgen_s1a_rsvd14 : 1; /* [   30],        r/w,        0x0 */
+            uint32_t cgen_s1a_rsvd15 : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg1;
+
+    /* 0x588 : cgen_s1_ext + cgen_s3 */
+    union {
+        struct {
+            uint32_t cgen_s0                 : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3            : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t cgen_s2_wifi            : 1; /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_9            : 5; /* [ 9: 5],       rsvd,        0x0 */
+            uint32_t cgen_s3_bt_ble2         : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cgen_s3_m1542           : 1; /* [   11],        r/w,        0x1 */
+            uint32_t reserved_12_15          : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t cgen_s1_ext_emi_misc    : 1; /* [   16],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_psram0_ctrl : 1; /* [   17],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_psram_ctrl  : 1; /* [   18],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_usb         : 1; /* [   19],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_mix2        : 1; /* [   20],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_audio       : 1; /* [   21],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_sdh         : 1; /* [   22],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_emac        : 1; /* [   23],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_dma2        : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_pio         : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_rsvd10      : 1; /* [   26],        r/w,        0x1 */
+            uint32_t cgen_s1_ext_rsvd11      : 1; /* [   27],        r/w,        0x1 */
+            uint32_t reserved_28_31          : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg2;
+
+    /* 0x58C : cgen_cfg3 */
+    union {
+        struct {
+            uint32_t reserved_0_1             : 2;  /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t cgen_isp_wifipll_80m     : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t cgen_isp_aupll_div5      : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t cgen_isp_aupll_div6      : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t cgen_top_aupll_div5      : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t cgen_top_aupll_div6      : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t cgen_psramB_wifipll_320m : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t cgen_psramB_aupll_div1   : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_12            : 4;  /* [12: 9],       rsvd,        0x0 */
+            uint32_t cgen_top_wifipll_240m    : 1;  /* [   13],        r/w,        0x1 */
+            uint32_t cgen_top_wifipll_320m    : 1;  /* [   14],        r/w,        0x1 */
+            uint32_t cgen_top_aupll_div2      : 1;  /* [   15],        r/w,        0x1 */
+            uint32_t cgen_top_aupll_div1      : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reserved_17_31           : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg3;
+
+    /* 0x590  reserved */
+    uint8_t RESERVED0x590[48];
+
+    /* 0x5C0 : hw_rsv0 */
+    union {
+        struct {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hw_rsv0;
+
+    /* 0x5C4 : hw_rsv1 */
+    union {
+        struct {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hw_rsv1;
+
+    /* 0x5C8 : hw_rsv2 */
+    union {
+        struct {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hw_rsv2;
+
+    /* 0x5CC : hw_rsv3 */
+    union {
+        struct {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd, 0xffffffff */
+        } BF;
+        uint32_t WORD;
+    } hw_rsv3;
+
+    /* 0x5d0  reserved */
+    uint8_t RESERVED0x5d0[48];
+
+    /* 0x600 : reg_sram_ret */
+    union {
+        struct {
+            uint32_t cr_mcu_cache_ret : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t cr_mcu_hsram_ret : 4;  /* [ 5: 2],        r/w,        0x0 */
+            uint32_t reserved_6_7     : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t cr_wb_ram_ret    : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_misc_ram_ret  : 2;  /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11_31   : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_cfg0;
+
+    /* 0x604 : reg_sram_slp */
+    union {
+        struct {
+            uint32_t cr_mcu_cache_slp : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t cr_mcu_hsram_slp : 4;  /* [ 5: 2],        r/w,        0x0 */
+            uint32_t cr_mcu_rom_slp   : 2;  /* [ 7: 6],        r/w,        0x0 */
+            uint32_t cr_wb_ram_slp    : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_misc_ram_slp  : 2;  /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11_31   : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_cfg1;
+
+    /* 0x608 : reg_sram_parm */
+    union {
+        struct {
+            uint32_t cr_mcu_cache_dvse : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_mcu_hsram_dvse : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t cr_mcu_rom_dvse   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_wb_ram_dvse    : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_misc_ram_dvse  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t cr_ocram_dvse     : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t cr_wram_dvse      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7        : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t cr_mcu_cache_nap  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_mcu_hsram_nap  : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10       : 1;  /* [   10],       rsvd,        0x0 */
+            uint32_t cr_wb_ram_nap     : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t cr_misc_ram_nap   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t cr_ocram_nap      : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t cr_wram_nap       : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t reserved_15_31    : 17; /* [31:15],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_cfg2;
+
+    /* 0x60C : sram_cfg3 */
+    union {
+        struct {
+            uint32_t em_sel        : 4;  /* [ 3: 0],        r/w,        0x3 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_cfg3;
+
+    /* 0x610 : reg_sram_parm2 */
+    union {
+        struct {
+            uint32_t cr_mcu_cache_dvs : 4; /* [ 3: 0],        r/w,        0xc */
+            uint32_t cr_mcu_hsram_dvs : 4; /* [ 7: 4],        r/w,        0xc */
+            uint32_t cr_mcu_rom_dvs   : 4; /* [11: 8],        r/w,        0xc */
+            uint32_t cr_wb_ram_dvs    : 4; /* [15:12],        r/w,        0xc */
+            uint32_t cr_misc_ram_dvs  : 4; /* [19:16],        r/w,        0xc */
+            uint32_t cr_ocram_dvs     : 4; /* [23:20],        r/w,        0xc */
+            uint32_t cr_wram_dvs      : 4; /* [27:24],        r/w,        0xc */
+            uint32_t reserved_28_31   : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_cfg4;
+
+    /* 0x614  reserved */
+    uint8_t RESERVED0x614[12];
+
+    /* 0x620 : psram_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_26      : 27; /* [26: 0],       rsvd,        0x0 */
+            uint32_t reg_psramB_clk_en  : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t reg_psramB_clk_sel : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29        : 1;  /* [   29],       rsvd,        0x0 */
+            uint32_t reg_psramB_clk_div : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_cfg0;
+
+    /* 0x624  reserved */
+    uint8_t RESERVED0x624[204];
+
+    /* 0x6F0 : proc_mon */
+    union {
+        struct {
+            uint32_t pu_proc_mon         : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t osc_en_rvt          : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t osc_en_lvt          : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t osc_sel             : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t rstn_ringcount      : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t rstn_refcount       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t refcount_div_onehot : 4;  /* [11: 8],        r/w,        0x4 */
+            uint32_t ring_freq           : 16; /* [27:12],          r,        0x0 */
+            uint32_t ring_freq_rdy       : 1;  /* [   28],          r,        0x0 */
+            uint32_t reserved_29_31      : 3;  /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } proc_mon;
+
+    /* 0x6f4  reserved */
+    uint8_t RESERVED0x6f4[12];
+
+    /* 0x700 : dll_cfg0 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dll_cfg0;
+
+    /* 0x704  reserved */
+    uint8_t RESERVED0x704[268];
+
+    /* 0x810 : wifi_pll_cfg0 */
+    union {
+        struct {
+            uint32_t wifipll_sdm_rstb     : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t wifipll_postdiv_rstb : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t wifipll_fbdv_rstb    : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t wifipll_refdiv_rstb  : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t pu_wifipll_clktree   : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t pu_wifipll_postdiv   : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t pu_wifipll_fbdv      : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t pu_wifipll_clamp_op  : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t pu_wifipll_pfd       : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t pu_wifipll_cp        : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t pu_wifipll_sfreg     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t pu_wifipll           : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_31       : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg0;
+
+    /* 0x814 : wifi_pll_cfg1 */
+    union {
+        struct {
+            uint32_t wifipll_postdiv      : 7; /* [ 6: 0],        r/w,       0x14 */
+            uint32_t reserved_7           : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t wifipll_refdiv_ratio : 4; /* [11: 8],        r/w,        0x2 */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t wifipll_refclk_sel   : 2; /* [17:16],        r/w,        0x1 */
+            uint32_t reserved_18_19       : 2; /* [19:18],       rsvd,        0x0 */
+            uint32_t wifipll_vg11_sel     : 2; /* [21:20],        r/w,        0x1 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t wifipll_vg13_sel     : 2; /* [25:24],        r/w,        0x1 */
+            uint32_t reserved_26_31       : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg1;
+
+    /* 0x818 : wifi_pll_cfg2 */
+    union {
+        struct {
+            uint32_t wifipll_sel_cp_bias   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3          : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t wifipll_icp_5u        : 2;  /* [ 5: 4],        r/w,        0x2 */
+            uint32_t wifipll_icp_1u        : 2;  /* [ 7: 6],        r/w,        0x0 */
+            uint32_t wifipll_int_frac_sw   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t wifipll_cp_startup_en : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t wifipll_cp_opamp_en   : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_31        : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg2;
+
+    /* 0x81C : wifi_pll_cfg3 */
+    union {
+        struct {
+            uint32_t wifipll_c4_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t wifipll_r4       : 2;  /* [ 5: 4],        r/w,        0x2 */
+            uint32_t reserved_6_7     : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t wifipll_r4_short : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_11    : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t wifipll_c3       : 2;  /* [13:12],        r/w,        0x2 */
+            uint32_t wifipll_cz       : 2;  /* [15:14],        r/w,        0x1 */
+            uint32_t wifipll_rz       : 3;  /* [18:16],        r/w,        0x3 */
+            uint32_t reserved_19_31   : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg3;
+
+    /* 0x820 : wifi_pll_cfg4 */
+    union {
+        struct {
+            uint32_t wifipll_sel_sample_clk : 2;  /* [ 1: 0],        r/w,        0x1 */
+            uint32_t reserved_2_3           : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t wifipll_sel_fb_clk     : 2;  /* [ 5: 4],        r/w,        0x1 */
+            uint32_t reserved_6_7           : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t wifipll_sdmclk_sel     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31          : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg4;
+
+    /* 0x824 : wifi_pll_cfg5 */
+    union {
+        struct {
+            uint32_t wifipll_vco_speed   : 3;  /* [ 2: 0],        r/w,        0x5 */
+            uint32_t wifipll_vco_div3_en : 1;  /* [    3],        r/w,        0x1 */
+            uint32_t wifipll_vco_div2_en : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t wifipll_vco_div1_en : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31       : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg5;
+
+    /* 0x828 : wifi_pll_cfg6 */
+    union {
+        struct {
+            uint32_t wifipll_sdmin         : 26; /* [25: 0],        r/w,  0x1800000 */
+            uint32_t wifipll_sdm_bypass    : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t reserved_27_29        : 3;  /* [29:27],       rsvd,        0x0 */
+            uint32_t wifipll_sdm_bypass_hw : 1;  /* [   30],          r,        0x0 */
+            uint32_t wifipll_sdm_ctrl_hw   : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg6;
+
+    /* 0x82C : wifi_pll_cfg7 */
+    union {
+        struct {
+            uint32_t wifipll_sdm_order_sel    : 2;  /* [ 1: 0],        r/w,        0x2 */
+            uint32_t reserved_2_3             : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t wifipll_sdm_noi_prbs_sel : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_7             : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t wifipll_sdm_noi_prbs_en  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_11            : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t wifipll_sdm_sig_prbs_sel : 2;  /* [13:12],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2;  /* [15:14],       rsvd,        0x0 */
+            uint32_t wifipll_sdm_sig_dith_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31           : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg7;
+
+    /* 0x830 : wifi_pll_cfg8 */
+    union {
+        struct {
+            uint32_t wifipll_en_rf_div3     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t wifipll_en_rf_div6     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t wifipll_sel_div3_div6  : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t wifipll_sel_div6_div12 : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t wifipll_en_div3        : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t wifipll_en_div4        : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t wifipll_en_div5        : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t wifipll_en_div6        : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t wifipll_en_div8        : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t wifipll_en_div10       : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t wifipll_en_div12       : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t wifipll_en_div20       : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t wifipll_en_div30       : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t reserved_13_19         : 7;  /* [19:13],       rsvd,        0x0 */
+            uint32_t wifipll_en_rf_div3_hw  : 1;  /* [   20],          r,        0x1 */
+            uint32_t reserved_21_30         : 10; /* [30:21],       rsvd,        0x0 */
+            uint32_t wifipll_en_ctrl_hw     : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg8;
+
+    /* 0x834 : wifi_pll_cfg9 */
+    union {
+        struct {
+            uint32_t wifipll_dc_tp_out_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t ten_wifipll              : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ten_wifipll_sfreg        : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3               : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t dten_wifipll_fin         : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t dten_wifipll_fref        : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t dten_wifipll_fsdm        : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t dten_wifipll_div30       : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t dten_wifipll_div10       : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t dten_wifipll_postdiv_clk : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t dten_usbpll_pclk         : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t dten_usbpll_clkout       : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t dten_sscdiv_pclk         : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t dten_sscdiv_clkout       : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t dtest_pulldown           : 1;  /* [   14],        r/w,        0x1 */
+            uint32_t reserved_15_31           : 17; /* [31:15],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg9;
+
+    /* 0x838 : wifi_pll_cfg10 */
+    union {
+        struct {
+            uint32_t usbpll_sdmin            : 19; /* [18: 0],        r/w,    0x28000 */
+            uint32_t reserved_19             : 1;  /* [   19],       rsvd,        0x0 */
+            uint32_t usbpll_sdm_bypass       : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t usbpll_sdm_order_sel    : 1;  /* [   21],        r/w,        0x1 */
+            uint32_t usbpll_sdm_sig_dith_sel : 2;  /* [23:22],        r/w,        0x0 */
+            uint32_t usbpll_div2_en          : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t usbpll_clkout_en        : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t usbpll_sel_sample_clk   : 2;  /* [27:26],        r/w,        0x1 */
+            uint32_t usbpll_rstb             : 1;  /* [   28],        r/w,        0x1 */
+            uint32_t pu_usbpll_mmdiv         : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg10;
+
+    /* 0x83C : wifi_pll_cfg11 */
+    union {
+        struct {
+            uint32_t usbpll_ssc_cnt           : 9;  /* [ 8: 0],        r/w,       0xf0 */
+            uint32_t usbpll_ssc_start         : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t usbpll_ssc_start_gate_en : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11              : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t usbpll_ssc_gain          : 3;  /* [14:12],        r/w,        0x3 */
+            uint32_t reserved_15              : 1;  /* [   15],       rsvd,        0x0 */
+            uint32_t usbpll_ssc_en            : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31           : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg11;
+
+    /* 0x840 : wifi_pll_cfg12 */
+    union {
+        struct {
+            uint32_t sscdiv_sdmin            : 19; /* [18: 0],        r/w,    0x28000 */
+            uint32_t reserved_19             : 1;  /* [   19],       rsvd,        0x0 */
+            uint32_t sscdiv_sdm_bypass       : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t sscdiv_sdm_order_sel    : 1;  /* [   21],        r/w,        0x1 */
+            uint32_t sscdiv_sdm_sig_dith_sel : 2;  /* [23:22],        r/w,        0x0 */
+            uint32_t sscdiv_div2_en          : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sscdiv_clkout_en        : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t sscdiv_sel_sample_clk   : 2;  /* [27:26],        r/w,        0x1 */
+            uint32_t sscdiv_rstb             : 1;  /* [   28],        r/w,        0x1 */
+            uint32_t pu_sscdiv_mmdiv         : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg12;
+
+    /* 0x844 : wifi_pll_cfg13 */
+    union {
+        struct {
+            uint32_t sscdiv_ssc_cnt           : 9;  /* [ 8: 0],        r/w,      0x1e0 */
+            uint32_t sscdiv_ssc_start         : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t sscdiv_ssc_start_gate_en : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11              : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t sscdiv_ssc_gain          : 3;  /* [14:12],        r/w,        0x2 */
+            uint32_t reserved_15              : 1;  /* [   15],       rsvd,        0x0 */
+            uint32_t sscdiv_ssc_en            : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31           : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg13;
+
+    /* 0x848 : wifi_pll_cfg14 */
+    union {
+        struct {
+            uint32_t wifipll_resv         : 16; /* [15: 0],        r/w,     0xff00 */
+            uint32_t sscdiv_dl_ctrl       : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t usbpll_dl_ctrl       : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_30   : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_20   : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_12   : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_10   : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_8    : 1;  /* [   22],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_6_rf : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_6    : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_5    : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_4    : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_3_rf : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t wifipll_dl_ctrl_3    : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29_31       : 3;  /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } wifi_pll_cfg14;
+
+    /* 0x84c  reserved */
+    uint8_t RESERVED0x84c[56];
+
+    /* 0x884 : ldo18io */
+    union {
+        struct {
+            uint32_t pu_ldo18io           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t ldo18io_bypass       : 1; /* [    1],        r/w,        0x0 */
+            uint32_t ten_ldo18io          : 1; /* [    2],        r/w,        0x0 */
+            uint32_t ldo18io_ocp_out      : 1; /* [    3],          r,        0x0 */
+            uint32_t ldo18io_bm           : 3; /* [ 6: 4],        r/w,        0x3 */
+            uint32_t reserved_7           : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t ldo18io_cc           : 3; /* [10: 8],        r/w,        0x3 */
+            uint32_t reserved_11          : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t ldo18io_ocp_th       : 3; /* [14:12],        r/w,        0x4 */
+            uint32_t ldo18io_ocp_en       : 1; /* [   15],        r/w,        0x1 */
+            uint32_t ldo18io_pulldown     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ldo18io_pulldown_sel : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reserved_18_19       : 2; /* [19:18],       rsvd,        0x0 */
+            uint32_t ldo18io_sstart_delay : 3; /* [22:20],        r/w,        0x3 */
+            uint32_t ldo18io_sstart_en    : 1; /* [   23],        r/w,        0x1 */
+            uint32_t ldo18io_vout_sel     : 4; /* [27:24],        r/w,        0x3 */
+            uint32_t ldo18io_vout_trim    : 4; /* [31:28],        r/w,        0x7 */
+        } BF;
+        uint32_t WORD;
+    } ldo18io;
+
+    /* 0x888  reserved */
+    uint8_t RESERVED0x888[28];
+
+    /* 0x8A4 : gauge */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gauge;
+
+    /* 0x8a8  reserved */
+    uint8_t RESERVED0x8a8[28];
+
+    /* 0x8C4 : gpio_cfg0 */
+    union {
+        struct {
+            uint32_t reg_gpio_0_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_0_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_0_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_0_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_0_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_0_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_0_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_0_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_0_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg0;
+
+    /* 0x8C8 : gpio_cfg1 */
+    union {
+        struct {
+            uint32_t reg_gpio_1_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_1_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_1_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_1_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_1_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_1_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_1_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_1_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_1_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg1;
+
+    /* 0x8CC : gpio_cfg2 */
+    union {
+        struct {
+            uint32_t reg_gpio_2_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_2_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_2_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_2_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_2_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_2_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_2_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_2_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_2_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg2;
+
+    /* 0x8D0 : gpio_cfg3 */
+    union {
+        struct {
+            uint32_t reg_gpio_3_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_3_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_3_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_3_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_3_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_3_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_3_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_3_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_3_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg3;
+
+    /* 0x8D4 : gpio_cfg4 */
+    union {
+        struct {
+            uint32_t reg_gpio_4_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_4_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_4_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_4_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_4_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_4_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_4_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_4_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_4_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg4;
+
+    /* 0x8D8 : gpio_cfg5 */
+    union {
+        struct {
+            uint32_t reg_gpio_5_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_5_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_5_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_5_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_5_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_5_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_5_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_5_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_5_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg5;
+
+    /* 0x8DC : gpio_cfg6 */
+    union {
+        struct {
+            uint32_t reg_gpio_6_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_6_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_6_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_6_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_6_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_6_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_6_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_6_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_6_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg6;
+
+    /* 0x8E0 : gpio_cfg7 */
+    union {
+        struct {
+            uint32_t reg_gpio_7_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_7_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_7_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_7_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_7_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_7_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_7_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_7_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_7_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg7;
+
+    /* 0x8E4 : gpio_cfg8 */
+    union {
+        struct {
+            uint32_t reg_gpio_8_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_8_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_8_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_8_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_8_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_8_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_8_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_8_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_8_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg8;
+
+    /* 0x8E8 : gpio_cfg9 */
+    union {
+        struct {
+            uint32_t reg_gpio_9_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_9_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_9_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_9_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7              : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15          : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_9_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_9_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_9_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23             : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_9_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_9_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29             : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg9;
+
+    /* 0x8EC : gpio_cfg10 */
+    union {
+        struct {
+            uint32_t reg_gpio_10_ie           : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_10_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_10_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_10_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_func_sel     : 5; /* [12: 8],        r/w,        0xf */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_10_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_10_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_10_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_10_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_10_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg10;
+
+    /* 0x8F0 : gpio_cfg11 */
+    union {
+        struct {
+            uint32_t reg_gpio_11_ie           : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_11_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_11_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_11_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_func_sel     : 5; /* [12: 8],        r/w,        0xf */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_11_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_11_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_11_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_11_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_11_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg11;
+
+    /* 0x8F4 : gpio_cfg12 */
+    union {
+        struct {
+            uint32_t reg_gpio_12_ie           : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_12_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_12_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_12_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_func_sel     : 5; /* [12: 8],        r/w,        0xf */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_12_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_12_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_12_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_12_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_12_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg12;
+
+    /* 0x8F8 : gpio_cfg13 */
+    union {
+        struct {
+            uint32_t reg_gpio_13_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_13_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_13_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_13_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_13_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_13_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_13_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_13_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_13_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg13;
+
+    /* 0x8FC : gpio_cfg14 */
+    union {
+        struct {
+            uint32_t reg_gpio_14_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_14_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_14_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_14_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_14_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_14_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_14_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_14_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_14_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg14;
+
+    /* 0x900 : gpio_cfg15 */
+    union {
+        struct {
+            uint32_t reg_gpio_15_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_15_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_15_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_15_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_15_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_15_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_15_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_15_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_15_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg15;
+
+    /* 0x904 : gpio_cfg16 */
+    union {
+        struct {
+            uint32_t reg_gpio_16_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_16_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_16_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_16_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_16_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_16_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_16_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_16_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_16_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg16;
+
+    /* 0x908 : gpio_cfg17 */
+    union {
+        struct {
+            uint32_t reg_gpio_17_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_17_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_17_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_17_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_17_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_17_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_17_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_17_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_17_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg17;
+
+    /* 0x90C : gpio_cfg18 */
+    union {
+        struct {
+            uint32_t reg_gpio_18_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_18_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_18_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_18_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_18_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_18_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_18_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_18_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_18_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg18;
+
+    /* 0x910 : gpio_cfg19 */
+    union {
+        struct {
+            uint32_t reg_gpio_19_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_19_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_19_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_19_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_19_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_19_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_19_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_19_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_19_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg19;
+
+    /* 0x914 : gpio_cfg20 */
+    union {
+        struct {
+            uint32_t reg_gpio_20_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_20_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_20_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_20_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_20_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_20_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_20_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_20_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_20_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg20;
+
+    /* 0x918 : gpio_cfg21 */
+    union {
+        struct {
+            uint32_t reg_gpio_21_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_21_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_21_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_21_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_21_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_21_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_21_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_21_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_21_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg21;
+
+    /* 0x91C : gpio_cfg22 */
+    union {
+        struct {
+            uint32_t reg_gpio_22_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_22_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_22_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_22_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_22_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_22_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_22_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_22_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_22_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg22;
+
+    /* 0x920 : gpio_cfg23 */
+    union {
+        struct {
+            uint32_t reg_gpio_23_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_23_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_23_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_23_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_23_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_23_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_23_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_23_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_23_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg23;
+
+    /* 0x924 : gpio_cfg24 */
+    union {
+        struct {
+            uint32_t reg_gpio_24_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_24_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_24_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_24_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_24_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_24_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_24_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_24_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_24_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_24_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_24_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_24_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_24_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_24_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg24;
+
+    /* 0x928 : gpio_cfg25 */
+    union {
+        struct {
+            uint32_t reg_gpio_25_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_25_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_25_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_25_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_25_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_25_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_25_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_25_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_25_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg25;
+
+    /* 0x92C : gpio_cfg26 */
+    union {
+        struct {
+            uint32_t reg_gpio_26_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_26_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_26_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_26_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_26_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_26_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_26_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_26_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_26_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_26_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_26_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_26_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_26_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_26_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg26;
+
+    /* 0x930 : gpio_cfg27 */
+    union {
+        struct {
+            uint32_t reg_gpio_27_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_27_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_27_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_27_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_27_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_27_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_27_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_27_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_27_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg27;
+
+    /* 0x934 : gpio_cfg28 */
+    union {
+        struct {
+            uint32_t reg_gpio_28_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_28_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_28_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_28_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_28_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_28_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_28_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_28_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_28_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_28_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_28_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_28_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_28_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_28_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg28;
+
+    /* 0x938 : gpio_cfg29 */
+    union {
+        struct {
+            uint32_t reg_gpio_29_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_29_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_29_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_29_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_29_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_29_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_29_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_29_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_29_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_29_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_29_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg29;
+
+    /* 0x93C : gpio_cfg30 */
+    union {
+        struct {
+            uint32_t reg_gpio_30_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_30_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_30_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_30_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_30_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_30_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_30_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_30_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_30_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_30_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_30_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_30_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_30_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_30_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_30_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_30_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg30;
+
+    /* 0x940 : gpio_cfg31 */
+    union {
+        struct {
+            uint32_t reg_gpio_31_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_31_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_31_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_31_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_31_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_31_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_31_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_31_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_31_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_31_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_31_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg31;
+
+    /* 0x944 : gpio_cfg32 */
+    union {
+        struct {
+            uint32_t reg_gpio_32_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_32_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_32_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_32_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_32_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_32_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_32_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_32_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_32_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_32_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_32_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_32_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_32_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_32_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_32_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_32_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg32;
+
+    /* 0x948 : gpio_cfg33 */
+    union {
+        struct {
+            uint32_t reg_gpio_33_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_33_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_33_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_33_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_33_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_33_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_33_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_33_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_33_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_33_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_33_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_33_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_33_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_33_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_33_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_33_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg33;
+
+    /* 0x94C : gpio_cfg34 */
+    union {
+        struct {
+            uint32_t reg_gpio_34_ie           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_34_smt          : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_34_drv          : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_34_pu           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_34_pd           : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_34_oe           : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_gpio_34_func_sel     : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_34_int_mode_set : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t reg_gpio_34_int_clr      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpio_34_int_stat         : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_34_int_mask     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_gpio_34_o            : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_34_set          : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg_gpio_34_clr          : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reserved_27              : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t reg_gpio_34_i            : 1; /* [   28],          r,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t reg_gpio_34_mode         : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg34;
+
+    /* 0x950 : gpio_cfg35 */
+    union {
+        struct {
+            uint32_t reg_gpio_35_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_35_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_35_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_35_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_35_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg35;
+
+    /* 0x954 : gpio_cfg36 */
+    union {
+        struct {
+            uint32_t reg_gpio_36_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_36_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_36_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_36_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_36_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg36;
+
+    /* 0x958 : gpio_cfg37 */
+    union {
+        struct {
+            uint32_t reg_gpio_37_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_37_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_37_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_37_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_37_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg37;
+
+    /* 0x95C : gpio_cfg38 */
+    union {
+        struct {
+            uint32_t reg_gpio_38_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_38_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_38_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_38_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_38_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg38;
+
+    /* 0x960 : gpio_cfg39 */
+    union {
+        struct {
+            uint32_t reg_gpio_39_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_39_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_39_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_39_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_39_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg39;
+
+    /* 0x964 : gpio_cfg40 */
+    union {
+        struct {
+            uint32_t reg_gpio_40_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_40_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_40_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_40_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_40_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg40;
+
+    /* 0x968 : gpio_cfg41 */
+    union {
+        struct {
+            uint32_t reg_gpio_41_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_41_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_41_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_41_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_41_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg41;
+
+    /* 0x96C : gpio_cfg42 */
+    union {
+        struct {
+            uint32_t reg_gpio_42_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_42_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_42_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_42_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_42_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg42;
+
+    /* 0x970 : gpio_cfg43 */
+    union {
+        struct {
+            uint32_t reg_gpio_43_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_43_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_43_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_43_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_43_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg43;
+
+    /* 0x974 : gpio_cfg44 */
+    union {
+        struct {
+            uint32_t reg_gpio_44_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_44_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_44_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_44_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_44_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg44;
+
+    /* 0x978 : gpio_cfg45 */
+    union {
+        struct {
+            uint32_t reg_gpio_45_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_45_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_45_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_45_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_45_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg45;
+
+    /* 0x97C : gpio_cfg46 */
+    union {
+        struct {
+            uint32_t reg_gpio_46_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_46_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_46_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_46_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_46_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg46;
+
+    /* 0x980 : gpio_cfg47 */
+    union {
+        struct {
+            uint32_t reg_gpio_47_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_47_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_47_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_47_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_47_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg47;
+
+    /* 0x984 : gpio_cfg48 */
+    union {
+        struct {
+            uint32_t reg_gpio_48_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_48_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_48_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_48_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_48_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg48;
+
+    /* 0x988 : gpio_cfg49 */
+    union {
+        struct {
+            uint32_t reg_gpio_49_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_49_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_49_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_49_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_49_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg49;
+
+    /* 0x98C : gpio_cfg50 */
+    union {
+        struct {
+            uint32_t reg_gpio_50_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_50_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_50_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_50_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_50_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg50;
+
+    /* 0x990 : gpio_cfg51 */
+    union {
+        struct {
+            uint32_t reg_gpio_51_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_51_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_51_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_51_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_51_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg51;
+
+    /* 0x994 : gpio_cfg52 */
+    union {
+        struct {
+            uint32_t reg_gpio_52_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_52_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_52_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_52_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_52_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg52;
+
+    /* 0x998 : gpio_cfg53 */
+    union {
+        struct {
+            uint32_t reg_gpio_53_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_53_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_53_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_53_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_53_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg53;
+
+    /* 0x99C : gpio_cfg54 */
+    union {
+        struct {
+            uint32_t reg_gpio_54_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_54_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_54_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_54_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_54_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg54;
+
+    /* 0x9A0 : gpio_cfg55 */
+    union {
+        struct {
+            uint32_t reg_gpio_55_ie  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_55_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_55_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_55_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_55_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_31   : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg55;
+
+    /* 0x9A4 : gpio_cfg56 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg56;
+
+    /* 0x9A8 : gpio_cfg57 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg57;
+
+    /* 0x9AC : gpio_cfg58 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg58;
+
+    /* 0x9B0 : gpio_cfg59 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg59;
+
+    /* 0x9B4 : gpio_cfg60 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg60;
+
+    /* 0x9B8 : gpio_cfg61 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg61;
+
+    /* 0x9BC : gpio_cfg62 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg62;
+
+    /* 0x9C0 : gpio_cfg63 */
+    union {
+        struct {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg63;
+
+    /* 0x9c4  reserved */
+    uint8_t RESERVED0x9c4[256];
+
+    /* 0xAC4 : gpio_cfg128 */
+    union {
+        struct {
+            uint32_t reg2_gpio_0_i  : 1; /* [    0],          r,        0x0 */
+            uint32_t reg2_gpio_1_i  : 1; /* [    1],          r,        0x0 */
+            uint32_t reg2_gpio_2_i  : 1; /* [    2],          r,        0x0 */
+            uint32_t reg2_gpio_3_i  : 1; /* [    3],          r,        0x0 */
+            uint32_t reg2_gpio_4_i  : 1; /* [    4],          r,        0x0 */
+            uint32_t reg2_gpio_5_i  : 1; /* [    5],          r,        0x0 */
+            uint32_t reg2_gpio_6_i  : 1; /* [    6],          r,        0x0 */
+            uint32_t reg2_gpio_7_i  : 1; /* [    7],          r,        0x0 */
+            uint32_t reg2_gpio_8_i  : 1; /* [    8],          r,        0x0 */
+            uint32_t reg2_gpio_9_i  : 1; /* [    9],          r,        0x0 */
+            uint32_t reg2_gpio_10_i : 1; /* [   10],          r,        0x0 */
+            uint32_t reg2_gpio_11_i : 1; /* [   11],          r,        0x0 */
+            uint32_t reg2_gpio_12_i : 1; /* [   12],          r,        0x0 */
+            uint32_t reg2_gpio_13_i : 1; /* [   13],          r,        0x0 */
+            uint32_t reg2_gpio_14_i : 1; /* [   14],          r,        0x0 */
+            uint32_t reg2_gpio_15_i : 1; /* [   15],          r,        0x0 */
+            uint32_t reg2_gpio_16_i : 1; /* [   16],          r,        0x0 */
+            uint32_t reg2_gpio_17_i : 1; /* [   17],          r,        0x0 */
+            uint32_t reg2_gpio_18_i : 1; /* [   18],          r,        0x0 */
+            uint32_t reg2_gpio_19_i : 1; /* [   19],          r,        0x0 */
+            uint32_t reg2_gpio_20_i : 1; /* [   20],          r,        0x0 */
+            uint32_t reg2_gpio_21_i : 1; /* [   21],          r,        0x0 */
+            uint32_t reg2_gpio_22_i : 1; /* [   22],          r,        0x0 */
+            uint32_t reg2_gpio_23_i : 1; /* [   23],          r,        0x0 */
+            uint32_t reg2_gpio_24_i : 1; /* [   24],          r,        0x0 */
+            uint32_t reg2_gpio_25_i : 1; /* [   25],          r,        0x0 */
+            uint32_t reg2_gpio_26_i : 1; /* [   26],          r,        0x0 */
+            uint32_t reg2_gpio_27_i : 1; /* [   27],          r,        0x0 */
+            uint32_t reg2_gpio_28_i : 1; /* [   28],          r,        0x0 */
+            uint32_t reg2_gpio_29_i : 1; /* [   29],          r,        0x0 */
+            uint32_t reg2_gpio_30_i : 1; /* [   30],          r,        0x0 */
+            uint32_t reg2_gpio_31_i : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg128;
+
+    /* 0xAC8 : gpio_cfg129 */
+    union {
+        struct {
+            uint32_t reg2_gpio_32_i : 1;  /* [    0],          r,        0x0 */
+            uint32_t reg2_gpio_33_i : 1;  /* [    1],          r,        0x0 */
+            uint32_t reg2_gpio_34_i : 1;  /* [    2],          r,        0x0 */
+            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg129;
+
+    /* 0xacc  reserved */
+    uint8_t RESERVED0xacc[24];
+
+    /* 0xAE4 : gpio_cfg136 */
+    union {
+        struct {
+            uint32_t reg2_gpio_0_o  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg2_gpio_1_o  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg2_gpio_2_o  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg2_gpio_3_o  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg2_gpio_4_o  : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg2_gpio_5_o  : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg2_gpio_6_o  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg2_gpio_7_o  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg2_gpio_8_o  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg2_gpio_9_o  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reg2_gpio_10_o : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg2_gpio_11_o : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg2_gpio_12_o : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg2_gpio_13_o : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg2_gpio_14_o : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg2_gpio_15_o : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg2_gpio_16_o : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg2_gpio_17_o : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reg2_gpio_18_o : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg2_gpio_19_o : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg2_gpio_20_o : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg2_gpio_21_o : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reg2_gpio_22_o : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reg2_gpio_23_o : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reg2_gpio_24_o : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg2_gpio_25_o : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reg2_gpio_26_o : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reg2_gpio_27_o : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reg2_gpio_28_o : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg2_gpio_29_o : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg2_gpio_30_o : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reg2_gpio_31_o : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg136;
+
+    /* 0xAE8 : gpio_cfg137 */
+    union {
+        struct {
+            uint32_t reg2_gpio_32_o : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg2_gpio_33_o : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg2_gpio_34_o : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31  : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg137;
+
+    /* 0xAEC : gpio_cfg138 */
+    union {
+        struct {
+            uint32_t reg2_gpio_0_set  : 1; /* [    0],        w1p,        0x0 */
+            uint32_t reg2_gpio_1_set  : 1; /* [    1],        w1p,        0x0 */
+            uint32_t reg2_gpio_2_set  : 1; /* [    2],        w1p,        0x0 */
+            uint32_t reg2_gpio_3_set  : 1; /* [    3],        w1p,        0x0 */
+            uint32_t reg2_gpio_4_set  : 1; /* [    4],        w1p,        0x0 */
+            uint32_t reg2_gpio_5_set  : 1; /* [    5],        w1p,        0x0 */
+            uint32_t reg2_gpio_6_set  : 1; /* [    6],        w1p,        0x0 */
+            uint32_t reg2_gpio_7_set  : 1; /* [    7],        w1p,        0x0 */
+            uint32_t reg2_gpio_8_set  : 1; /* [    8],        w1p,        0x0 */
+            uint32_t reg2_gpio_9_set  : 1; /* [    9],        w1p,        0x0 */
+            uint32_t reg2_gpio_10_set : 1; /* [   10],        w1p,        0x0 */
+            uint32_t reg2_gpio_11_set : 1; /* [   11],        w1p,        0x0 */
+            uint32_t reg2_gpio_12_set : 1; /* [   12],        w1p,        0x0 */
+            uint32_t reg2_gpio_13_set : 1; /* [   13],        w1p,        0x0 */
+            uint32_t reg2_gpio_14_set : 1; /* [   14],        w1p,        0x0 */
+            uint32_t reg2_gpio_15_set : 1; /* [   15],        w1p,        0x0 */
+            uint32_t reg2_gpio_16_set : 1; /* [   16],        w1p,        0x0 */
+            uint32_t reg2_gpio_17_set : 1; /* [   17],        w1p,        0x0 */
+            uint32_t reg2_gpio_18_set : 1; /* [   18],        w1p,        0x0 */
+            uint32_t reg2_gpio_19_set : 1; /* [   19],        w1p,        0x0 */
+            uint32_t reg2_gpio_20_set : 1; /* [   20],        w1p,        0x0 */
+            uint32_t reg2_gpio_21_set : 1; /* [   21],        w1p,        0x0 */
+            uint32_t reg2_gpio_22_set : 1; /* [   22],        w1p,        0x0 */
+            uint32_t reg2_gpio_23_set : 1; /* [   23],        w1p,        0x0 */
+            uint32_t reg2_gpio_24_set : 1; /* [   24],        w1p,        0x0 */
+            uint32_t reg2_gpio_25_set : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg2_gpio_26_set : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reg2_gpio_27_set : 1; /* [   27],        w1p,        0x0 */
+            uint32_t reg2_gpio_28_set : 1; /* [   28],        w1p,        0x0 */
+            uint32_t reg2_gpio_29_set : 1; /* [   29],        w1p,        0x0 */
+            uint32_t reg2_gpio_30_set : 1; /* [   30],        w1p,        0x0 */
+            uint32_t reg2_gpio_31_set : 1; /* [   31],        w1p,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg138;
+
+    /* 0xAF0 : gpio_cfg139 */
+    union {
+        struct {
+            uint32_t reg2_gpio_32_set : 1;  /* [    0],        w1p,        0x0 */
+            uint32_t reg2_gpio_33_set : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t reg2_gpio_34_set : 1;  /* [    2],        w1p,        0x0 */
+            uint32_t reserved_3_31    : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg139;
+
+    /* 0xAF4 : gpio_cfg140 */
+    union {
+        struct {
+            uint32_t reg2_gpio_0_clr  : 1; /* [    0],        w1p,        0x0 */
+            uint32_t reg2_gpio_1_clr  : 1; /* [    1],        w1p,        0x0 */
+            uint32_t reg2_gpio_2_clr  : 1; /* [    2],        w1p,        0x0 */
+            uint32_t reg2_gpio_3_clr  : 1; /* [    3],        w1p,        0x0 */
+            uint32_t reg2_gpio_4_clr  : 1; /* [    4],        w1p,        0x0 */
+            uint32_t reg2_gpio_5_clr  : 1; /* [    5],        w1p,        0x0 */
+            uint32_t reg2_gpio_6_clr  : 1; /* [    6],        w1p,        0x0 */
+            uint32_t reg2_gpio_7_clr  : 1; /* [    7],        w1p,        0x0 */
+            uint32_t reg2_gpio_8_clr  : 1; /* [    8],        w1p,        0x0 */
+            uint32_t reg2_gpio_9_clr  : 1; /* [    9],        w1p,        0x0 */
+            uint32_t reg2_gpio_10_clr : 1; /* [   10],        w1p,        0x0 */
+            uint32_t reg2_gpio_11_clr : 1; /* [   11],        w1p,        0x0 */
+            uint32_t reg2_gpio_12_clr : 1; /* [   12],        w1p,        0x0 */
+            uint32_t reg2_gpio_13_clr : 1; /* [   13],        w1p,        0x0 */
+            uint32_t reg2_gpio_14_clr : 1; /* [   14],        w1p,        0x0 */
+            uint32_t reg2_gpio_15_clr : 1; /* [   15],        w1p,        0x0 */
+            uint32_t reg2_gpio_16_clr : 1; /* [   16],        w1p,        0x0 */
+            uint32_t reg2_gpio_17_clr : 1; /* [   17],        w1p,        0x0 */
+            uint32_t reg2_gpio_18_clr : 1; /* [   18],        w1p,        0x0 */
+            uint32_t reg2_gpio_19_clr : 1; /* [   19],        w1p,        0x0 */
+            uint32_t reg2_gpio_20_clr : 1; /* [   20],        w1p,        0x0 */
+            uint32_t reg2_gpio_21_clr : 1; /* [   21],        w1p,        0x0 */
+            uint32_t reg2_gpio_22_clr : 1; /* [   22],        w1p,        0x0 */
+            uint32_t reg2_gpio_23_clr : 1; /* [   23],        w1p,        0x0 */
+            uint32_t reg2_gpio_24_clr : 1; /* [   24],        w1p,        0x0 */
+            uint32_t reg2_gpio_25_clr : 1; /* [   25],        w1p,        0x0 */
+            uint32_t reg2_gpio_26_clr : 1; /* [   26],        w1p,        0x0 */
+            uint32_t reg2_gpio_27_clr : 1; /* [   27],        w1p,        0x0 */
+            uint32_t reg2_gpio_28_clr : 1; /* [   28],        w1p,        0x0 */
+            uint32_t reg2_gpio_29_clr : 1; /* [   29],        w1p,        0x0 */
+            uint32_t reg2_gpio_30_clr : 1; /* [   30],        w1p,        0x0 */
+            uint32_t reg2_gpio_31_clr : 1; /* [   31],        w1p,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg140;
+
+    /* 0xAF8 : gpio_cfg141 */
+    union {
+        struct {
+            uint32_t reg2_gpio_32_clr : 1;  /* [    0],        w1p,        0x0 */
+            uint32_t reg2_gpio_33_clr : 1;  /* [    1],        w1p,        0x0 */
+            uint32_t reg2_gpio_34_clr : 1;  /* [    2],        w1p,        0x0 */
+            uint32_t reserved_3_31    : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg141;
+
+    /* 0xAFC : gpio_cfg142 */
+    union {
+        struct {
+            uint32_t cr_gpio_tx_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t cr_invert_code0_high : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_invert_code1_high : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_6         : 4; /* [ 6: 3],       rsvd,        0x0 */
+            uint32_t cr_code_total_time   : 9; /* [15: 7],        r/w,      0x190 */
+            uint32_t cr_code0_high_time   : 8; /* [23:16],        r/w,       0xc8 */
+            uint32_t cr_code1_high_time   : 8; /* [31:24],        r/w,       0xc8 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg142;
+
+    /* 0xB00 : gpio_cfg143 */
+    union {
+        struct {
+            uint32_t cr_gpio_dma_tx_en         : 1; /* [    0],        r/w,        0x0 */
+            uint32_t cr_gpio_dma_out_sel_latch : 1; /* [    1],        r/w,        0x0 */
+            uint32_t gpio_tx_fifo_clr          : 1; /* [    2],        w1c,        0x0 */
+            uint32_t gpio_tx_end_clr           : 1; /* [    3],        w1c,        0x0 */
+            uint32_t gpio_tx_fifo_overflow     : 1; /* [    4],          r,        0x0 */
+            uint32_t gpio_tx_fifo_underflow    : 1; /* [    5],          r,        0x0 */
+            uint32_t reserved_6                : 1; /* [    6],       rsvd,        0x0 */
+            uint32_t cr_gpio_dma_park_value    : 1; /* [    7],        r/w,        0x0 */
+            uint32_t gpio_tx_fifo_cnt          : 8; /* [15: 8],          r,       0x80 */
+            uint32_t cr_gpio_tx_fifo_th        : 7; /* [22:16],        r/w,        0x0 */
+            uint32_t cr_gpio_tx_end_mask       : 1; /* [   23],        r/w,        0x1 */
+            uint32_t cr_gpio_tx_fifo_mask      : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cr_gpio_tx_fer_mask       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t r_gpio_tx_end_int         : 1; /* [   26],          r,        0x0 */
+            uint32_t r_gpio_tx_fifo_int        : 1; /* [   27],          r,        0x0 */
+            uint32_t r_gpio_tx_fer_int         : 1; /* [   28],          r,        0x0 */
+            uint32_t cr_gpio_tx_end_en         : 1; /* [   29],        r/w,        0x1 */
+            uint32_t cr_gpio_tx_fifo_en        : 1; /* [   30],        r/w,        0x1 */
+            uint32_t cr_gpio_tx_fer_en         : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg143;
+
+    /* 0xB04 : gpio_cfg144 */
+    union {
+        struct {
+            uint32_t gpio_tx_data_to_fifo : 16; /* [15: 0],          w,          x */
+            uint32_t reserved_16_31       : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpio_cfg144;
+};
+
+typedef volatile struct glb_reg glb_reg_t;
+
+#endif /* __GLB_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/hbn_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/hbn_reg.h
new file mode 100755
index 0000000000..c06379b28a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/hbn_reg.h
@@ -0,0 +1,941 @@
+/**
+  ******************************************************************************
+  * @file    hbn_reg.h
+  * @version V1.0
+  * @date    2021-11-22
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HBN_REG_H__
+#define __HBN_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : HBN_CTL */
+#define HBN_CTL_OFFSET                (0x0)
+#define HBN_RTC_CTL                   HBN_RTC_CTL
+#define HBN_RTC_CTL_POS               (0U)
+#define HBN_RTC_CTL_LEN               (4U)
+#define HBN_RTC_CTL_MSK               (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
+#define HBN_RTC_CTL_UMSK              (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
+#define HBN_RTC_DLY_OPTION            HBN_RTC_DLY_OPTION
+#define HBN_RTC_DLY_OPTION_POS        (4U)
+#define HBN_RTC_DLY_OPTION_LEN        (1U)
+#define HBN_RTC_DLY_OPTION_MSK        (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
+#define HBN_RTC_DLY_OPTION_UMSK       (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
+#define HBN_MODE                      HBN_MODE
+#define HBN_MODE_POS                  (7U)
+#define HBN_MODE_LEN                  (1U)
+#define HBN_MODE_MSK                  (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
+#define HBN_MODE_UMSK                 (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
+#define HBN_TRAP_MODE                 HBN_TRAP_MODE
+#define HBN_TRAP_MODE_POS             (8U)
+#define HBN_TRAP_MODE_LEN             (1U)
+#define HBN_TRAP_MODE_MSK             (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
+#define HBN_TRAP_MODE_UMSK            (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
+#define HBN_PWRDN_HBN_CORE            HBN_PWRDN_HBN_CORE
+#define HBN_PWRDN_HBN_CORE_POS        (9U)
+#define HBN_PWRDN_HBN_CORE_LEN        (1U)
+#define HBN_PWRDN_HBN_CORE_MSK        (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
+#define HBN_PWRDN_HBN_CORE_UMSK       (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
+#define HBN_PWRDN_HBN_RTC             HBN_PWRDN_HBN_RTC
+#define HBN_PWRDN_HBN_RTC_POS         (11U)
+#define HBN_PWRDN_HBN_RTC_LEN         (1U)
+#define HBN_PWRDN_HBN_RTC_MSK         (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)
+#define HBN_PWRDN_HBN_RTC_UMSK        (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS))
+#define HBN_SW_RST                    HBN_SW_RST
+#define HBN_SW_RST_POS                (12U)
+#define HBN_SW_RST_LEN                (1U)
+#define HBN_SW_RST_MSK                (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
+#define HBN_SW_RST_UMSK               (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
+#define HBN_DIS_PWR_OFF_LDO11         HBN_DIS_PWR_OFF_LDO11
+#define HBN_DIS_PWR_OFF_LDO11_POS     (13U)
+#define HBN_DIS_PWR_OFF_LDO11_LEN     (1U)
+#define HBN_DIS_PWR_OFF_LDO11_MSK     (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
+#define HBN_DIS_PWR_OFF_LDO11_UMSK    (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
+#define HBN_DIS_PWR_OFF_LDO11_RT      HBN_DIS_PWR_OFF_LDO11_RT
+#define HBN_DIS_PWR_OFF_LDO11_RT_POS  (14U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_LEN  (1U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_MSK  (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
+#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
+#define HBN_LDO11_RT_VOUT_SEL         HBN_LDO11_RT_VOUT_SEL
+#define HBN_LDO11_RT_VOUT_SEL_POS     (15U)
+#define HBN_LDO11_RT_VOUT_SEL_LEN     (4U)
+#define HBN_LDO11_RT_VOUT_SEL_MSK     (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
+#define HBN_LDO11_RT_VOUT_SEL_UMSK    (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
+#define HBN_LDO11_AON_VOUT_SEL        HBN_LDO11_AON_VOUT_SEL
+#define HBN_LDO11_AON_VOUT_SEL_POS    (19U)
+#define HBN_LDO11_AON_VOUT_SEL_LEN    (4U)
+#define HBN_LDO11_AON_VOUT_SEL_MSK    (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
+#define HBN_LDO11_AON_VOUT_SEL_UMSK   (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
+#define HBN_PU_DCDC18_AON             HBN_PU_DCDC18_AON
+#define HBN_PU_DCDC18_AON_POS         (24U)
+#define HBN_PU_DCDC18_AON_LEN         (1U)
+#define HBN_PU_DCDC18_AON_MSK         (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
+#define HBN_PU_DCDC18_AON_UMSK        (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
+#define HBN_PWR_ON_OPTION             HBN_PWR_ON_OPTION
+#define HBN_PWR_ON_OPTION_POS         (25U)
+#define HBN_PWR_ON_OPTION_LEN         (1U)
+#define HBN_PWR_ON_OPTION_MSK         (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
+#define HBN_PWR_ON_OPTION_UMSK        (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
+#define HBN_SRAM_SLP_OPTION           HBN_SRAM_SLP_OPTION
+#define HBN_SRAM_SLP_OPTION_POS       (26U)
+#define HBN_SRAM_SLP_OPTION_LEN       (1U)
+#define HBN_SRAM_SLP_OPTION_MSK       (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
+#define HBN_SRAM_SLP_OPTION_UMSK      (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
+#define HBN_SRAM_SLP                  HBN_SRAM_SLP
+#define HBN_SRAM_SLP_POS              (27U)
+#define HBN_SRAM_SLP_LEN              (1U)
+#define HBN_SRAM_SLP_MSK              (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
+#define HBN_SRAM_SLP_UMSK             (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
+#define HBN_STATE                     HBN_STATE
+#define HBN_STATE_POS                 (28U)
+#define HBN_STATE_LEN                 (4U)
+#define HBN_STATE_MSK                 (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
+#define HBN_STATE_UMSK                (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
+
+/* 0x4 : HBN_TIME_L */
+#define HBN_TIME_L_OFFSET (0x4)
+#define HBN_TIME_L        HBN_TIME_L
+#define HBN_TIME_L_POS    (0U)
+#define HBN_TIME_L_LEN    (32U)
+#define HBN_TIME_L_MSK    (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
+#define HBN_TIME_L_UMSK   (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
+
+/* 0x8 : HBN_TIME_H */
+#define HBN_TIME_H_OFFSET (0x8)
+#define HBN_TIME_H        HBN_TIME_H
+#define HBN_TIME_H_POS    (0U)
+#define HBN_TIME_H_LEN    (8U)
+#define HBN_TIME_H_MSK    (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
+#define HBN_TIME_H_UMSK   (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
+
+/* 0xC : RTC_TIME_L */
+#define HBN_RTC_TIME_L_OFFSET     (0xC)
+#define HBN_RTC_TIME_LATCH_L      HBN_RTC_TIME_LATCH_L
+#define HBN_RTC_TIME_LATCH_L_POS  (0U)
+#define HBN_RTC_TIME_LATCH_L_LEN  (32U)
+#define HBN_RTC_TIME_LATCH_L_MSK  (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
+#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
+
+/* 0x10 : RTC_TIME_H */
+#define HBN_RTC_TIME_H_OFFSET     (0x10)
+#define HBN_RTC_TIME_LATCH_H      HBN_RTC_TIME_LATCH_H
+#define HBN_RTC_TIME_LATCH_H_POS  (0U)
+#define HBN_RTC_TIME_LATCH_H_LEN  (8U)
+#define HBN_RTC_TIME_LATCH_H_MSK  (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
+#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
+#define HBN_RTC_TIME_LATCH        HBN_RTC_TIME_LATCH
+#define HBN_RTC_TIME_LATCH_POS    (31U)
+#define HBN_RTC_TIME_LATCH_LEN    (1U)
+#define HBN_RTC_TIME_LATCH_MSK    (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
+#define HBN_RTC_TIME_LATCH_UMSK   (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
+
+/* 0x14 : HBN_IRQ_MODE */
+#define HBN_IRQ_MODE_OFFSET      (0x14)
+#define HBN_PIN_WAKEUP_MODE      HBN_PIN_WAKEUP_MODE
+#define HBN_PIN_WAKEUP_MODE_POS  (0U)
+#define HBN_PIN_WAKEUP_MODE_LEN  (4U)
+#define HBN_PIN_WAKEUP_MODE_MSK  (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
+#define HBN_PIN_WAKEUP_MODE_UMSK (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
+#define HBN_PIN_WAKEUP_MASK      HBN_PIN_WAKEUP_MASK
+#define HBN_PIN_WAKEUP_MASK_POS  (4U)
+#define HBN_PIN_WAKEUP_MASK_LEN  (4U)
+#define HBN_PIN_WAKEUP_MASK_MSK  (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
+#define HBN_PIN_WAKEUP_MASK_UMSK (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
+#define HBN_REG_EN_HW_PU_PD      HBN_REG_EN_HW_PU_PD
+#define HBN_REG_EN_HW_PU_PD_POS  (16U)
+#define HBN_REG_EN_HW_PU_PD_LEN  (1U)
+#define HBN_REG_EN_HW_PU_PD_MSK  (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
+#define HBN_REG_EN_HW_PU_PD_UMSK (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
+#define HBN_IRQ_BOR_EN           HBN_IRQ_BOR_EN
+#define HBN_IRQ_BOR_EN_POS       (18U)
+#define HBN_IRQ_BOR_EN_LEN       (1U)
+#define HBN_IRQ_BOR_EN_MSK       (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
+#define HBN_IRQ_BOR_EN_UMSK      (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
+#define HBN_IRQ_ACOMP0_EN        HBN_IRQ_ACOMP0_EN
+#define HBN_IRQ_ACOMP0_EN_POS    (20U)
+#define HBN_IRQ_ACOMP0_EN_LEN    (2U)
+#define HBN_IRQ_ACOMP0_EN_MSK    (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
+#define HBN_IRQ_ACOMP0_EN_UMSK   (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
+#define HBN_IRQ_ACOMP1_EN        HBN_IRQ_ACOMP1_EN
+#define HBN_IRQ_ACOMP1_EN_POS    (22U)
+#define HBN_IRQ_ACOMP1_EN_LEN    (2U)
+#define HBN_IRQ_ACOMP1_EN_MSK    (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
+#define HBN_IRQ_ACOMP1_EN_UMSK   (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
+#define HBN_PIN_WAKEUP_SEL       HBN_PIN_WAKEUP_SEL
+#define HBN_PIN_WAKEUP_SEL_POS   (24U)
+#define HBN_PIN_WAKEUP_SEL_LEN   (3U)
+#define HBN_PIN_WAKEUP_SEL_MSK   (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
+#define HBN_PIN_WAKEUP_SEL_UMSK  (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
+#define HBN_PIN_WAKEUP_EN        HBN_PIN_WAKEUP_EN
+#define HBN_PIN_WAKEUP_EN_POS    (27U)
+#define HBN_PIN_WAKEUP_EN_LEN    (1U)
+#define HBN_PIN_WAKEUP_EN_MSK    (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
+#define HBN_PIN_WAKEUP_EN_UMSK   (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
+
+/* 0x18 : HBN_IRQ_STAT */
+#define HBN_IRQ_STAT_OFFSET (0x18)
+#define HBN_IRQ_STAT        HBN_IRQ_STAT
+#define HBN_IRQ_STAT_POS    (0U)
+#define HBN_IRQ_STAT_LEN    (32U)
+#define HBN_IRQ_STAT_MSK    (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
+#define HBN_IRQ_STAT_UMSK   (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
+
+/* 0x1C : HBN_IRQ_CLR */
+#define HBN_IRQ_CLR_OFFSET (0x1C)
+#define HBN_IRQ_CLR        HBN_IRQ_CLR
+#define HBN_IRQ_CLR_POS    (0U)
+#define HBN_IRQ_CLR_LEN    (32U)
+#define HBN_IRQ_CLR_MSK    (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
+#define HBN_IRQ_CLR_UMSK   (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
+
+/* 0x20 : HBN_PIR_CFG */
+#define HBN_PIR_CFG_OFFSET   (0x20)
+#define HBN_PIR_HPF_SEL      HBN_PIR_HPF_SEL
+#define HBN_PIR_HPF_SEL_POS  (0U)
+#define HBN_PIR_HPF_SEL_LEN  (2U)
+#define HBN_PIR_HPF_SEL_MSK  (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
+#define HBN_PIR_HPF_SEL_UMSK (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
+#define HBN_PIR_LPF_SEL      HBN_PIR_LPF_SEL
+#define HBN_PIR_LPF_SEL_POS  (2U)
+#define HBN_PIR_LPF_SEL_LEN  (1U)
+#define HBN_PIR_LPF_SEL_MSK  (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
+#define HBN_PIR_LPF_SEL_UMSK (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
+#define HBN_PIR_DIS          HBN_PIR_DIS
+#define HBN_PIR_DIS_POS      (4U)
+#define HBN_PIR_DIS_LEN      (2U)
+#define HBN_PIR_DIS_MSK      (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
+#define HBN_PIR_DIS_UMSK     (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
+#define HBN_PIR_EN           HBN_PIR_EN
+#define HBN_PIR_EN_POS       (7U)
+#define HBN_PIR_EN_LEN       (1U)
+#define HBN_PIR_EN_MSK       (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
+#define HBN_PIR_EN_UMSK      (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
+#define HBN_GPADC_CS         HBN_GPADC_CS
+#define HBN_GPADC_CS_POS     (8U)
+#define HBN_GPADC_CS_LEN     (1U)
+#define HBN_GPADC_CS_MSK     (((1U << HBN_GPADC_CS_LEN) - 1) << HBN_GPADC_CS_POS)
+#define HBN_GPADC_CS_UMSK    (~(((1U << HBN_GPADC_CS_LEN) - 1) << HBN_GPADC_CS_POS))
+
+/* 0x24 : HBN_PIR_VTH */
+#define HBN_PIR_VTH_OFFSET (0x24)
+#define HBN_PIR_VTH        HBN_PIR_VTH
+#define HBN_PIR_VTH_POS    (0U)
+#define HBN_PIR_VTH_LEN    (14U)
+#define HBN_PIR_VTH_MSK    (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
+#define HBN_PIR_VTH_UMSK   (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
+
+/* 0x28 : HBN_PIR_INTERVAL */
+#define HBN_PIR_INTERVAL_OFFSET (0x28)
+#define HBN_PIR_INTERVAL        HBN_PIR_INTERVAL
+#define HBN_PIR_INTERVAL_POS    (0U)
+#define HBN_PIR_INTERVAL_LEN    (12U)
+#define HBN_PIR_INTERVAL_MSK    (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
+#define HBN_PIR_INTERVAL_UMSK   (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
+
+/* 0x2C : HBN_BOR_CFG */
+#define HBN_BOR_CFG_OFFSET (0x2C)
+#define HBN_BOD_SEL        HBN_BOD_SEL
+#define HBN_BOD_SEL_POS    (0U)
+#define HBN_BOD_SEL_LEN    (1U)
+#define HBN_BOD_SEL_MSK    (((1U << HBN_BOD_SEL_LEN) - 1) << HBN_BOD_SEL_POS)
+#define HBN_BOD_SEL_UMSK   (~(((1U << HBN_BOD_SEL_LEN) - 1) << HBN_BOD_SEL_POS))
+#define HBN_BOD_VTH        HBN_BOD_VTH
+#define HBN_BOD_VTH_POS    (1U)
+#define HBN_BOD_VTH_LEN    (3U)
+#define HBN_BOD_VTH_MSK    (((1U << HBN_BOD_VTH_LEN) - 1) << HBN_BOD_VTH_POS)
+#define HBN_BOD_VTH_UMSK   (~(((1U << HBN_BOD_VTH_LEN) - 1) << HBN_BOD_VTH_POS))
+#define HBN_PU_BOD         HBN_PU_BOD
+#define HBN_PU_BOD_POS     (4U)
+#define HBN_PU_BOD_LEN     (1U)
+#define HBN_PU_BOD_MSK     (((1U << HBN_PU_BOD_LEN) - 1) << HBN_PU_BOD_POS)
+#define HBN_PU_BOD_UMSK    (~(((1U << HBN_PU_BOD_LEN) - 1) << HBN_PU_BOD_POS))
+#define HBN_R_BOD_OUT      HBN_R_BOD_OUT
+#define HBN_R_BOD_OUT_POS  (5U)
+#define HBN_R_BOD_OUT_LEN  (1U)
+#define HBN_R_BOD_OUT_MSK  (((1U << HBN_R_BOD_OUT_LEN) - 1) << HBN_R_BOD_OUT_POS)
+#define HBN_R_BOD_OUT_UMSK (~(((1U << HBN_R_BOD_OUT_LEN) - 1) << HBN_R_BOD_OUT_POS))
+
+/* 0x30 : HBN_GLB */
+#define HBN_GLB_OFFSET                    (0x30)
+#define HBN_ROOT_CLK_SEL                  HBN_ROOT_CLK_SEL
+#define HBN_ROOT_CLK_SEL_POS              (0U)
+#define HBN_ROOT_CLK_SEL_LEN              (2U)
+#define HBN_ROOT_CLK_SEL_MSK              (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
+#define HBN_ROOT_CLK_SEL_UMSK             (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
+#define HBN_UART_CLK_SEL                  HBN_UART_CLK_SEL
+#define HBN_UART_CLK_SEL_POS              (2U)
+#define HBN_UART_CLK_SEL_LEN              (1U)
+#define HBN_UART_CLK_SEL_MSK              (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
+#define HBN_UART_CLK_SEL_UMSK             (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
+#define HBN_F32K_SEL                      HBN_F32K_SEL
+#define HBN_F32K_SEL_POS                  (3U)
+#define HBN_F32K_SEL_LEN                  (2U)
+#define HBN_F32K_SEL_MSK                  (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
+#define HBN_F32K_SEL_UMSK                 (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
+#define HBN_PU_RC32K                      HBN_PU_RC32K
+#define HBN_PU_RC32K_POS                  (5U)
+#define HBN_PU_RC32K_LEN                  (1U)
+#define HBN_PU_RC32K_MSK                  (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
+#define HBN_PU_RC32K_UMSK                 (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
+#define HBN_RESET_EVENT                   HBN_RESET_EVENT
+#define HBN_RESET_EVENT_POS               (7U)
+#define HBN_RESET_EVENT_LEN               (5U)
+#define HBN_RESET_EVENT_MSK               (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)
+#define HBN_RESET_EVENT_UMSK              (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS))
+#define HBN_UART_CLK_SEL2                 HBN_UART_CLK_SEL2
+#define HBN_UART_CLK_SEL2_POS             (15U)
+#define HBN_UART_CLK_SEL2_LEN             (1U)
+#define HBN_UART_CLK_SEL2_MSK             (((1U << HBN_UART_CLK_SEL2_LEN) - 1) << HBN_UART_CLK_SEL2_POS)
+#define HBN_UART_CLK_SEL2_UMSK            (~(((1U << HBN_UART_CLK_SEL2_LEN) - 1) << HBN_UART_CLK_SEL2_POS))
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON      HBN_SW_LDO11SOC_VOUT_SEL_AON
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS  (16U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN  (4U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK  (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
+#define HBN_SW_LDO11_RT_VOUT_SEL          HBN_SW_LDO11_RT_VOUT_SEL
+#define HBN_SW_LDO11_RT_VOUT_SEL_POS      (24U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_LEN      (4U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_MSK      (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
+#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK     (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
+#define HBN_SW_LDO11_AON_VOUT_SEL         HBN_SW_LDO11_AON_VOUT_SEL
+#define HBN_SW_LDO11_AON_VOUT_SEL_POS     (28U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_LEN     (4U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_MSK     (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
+#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK    (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))
+
+/* 0x34 : HBN_SRAM */
+#define HBN_SRAM_OFFSET     (0x34)
+#define HBN_RETRAM_RET      HBN_RETRAM_RET
+#define HBN_RETRAM_RET_POS  (6U)
+#define HBN_RETRAM_RET_LEN  (1U)
+#define HBN_RETRAM_RET_MSK  (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
+#define HBN_RETRAM_RET_UMSK (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
+#define HBN_RETRAM_SLP      HBN_RETRAM_SLP
+#define HBN_RETRAM_SLP_POS  (7U)
+#define HBN_RETRAM_SLP_LEN  (1U)
+#define HBN_RETRAM_SLP_MSK  (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
+#define HBN_RETRAM_SLP_UMSK (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
+
+/* 0x38 : HBN_PAD_CTRL_0 */
+#define HBN_PAD_CTRL_0_OFFSET          (0x38)
+#define HBN_REG_AON_PAD_IE_SMT         HBN_REG_AON_PAD_IE_SMT
+#define HBN_REG_AON_PAD_IE_SMT_POS     (0U)
+#define HBN_REG_AON_PAD_IE_SMT_LEN     (4U)
+#define HBN_REG_AON_PAD_IE_SMT_MSK     (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
+#define HBN_REG_AON_PAD_IE_SMT_UMSK    (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
+#define HBN_REG_AON_LED_SEL            HBN_REG_AON_LED_SEL
+#define HBN_REG_AON_LED_SEL_POS        (10U)
+#define HBN_REG_AON_LED_SEL_LEN        (9U)
+#define HBN_REG_AON_LED_SEL_MSK        (((1U << HBN_REG_AON_LED_SEL_LEN) - 1) << HBN_REG_AON_LED_SEL_POS)
+#define HBN_REG_AON_LED_SEL_UMSK       (~(((1U << HBN_REG_AON_LED_SEL_LEN) - 1) << HBN_REG_AON_LED_SEL_POS))
+#define HBN_REG_EN_AON_CTRL_GPIO       HBN_REG_EN_AON_CTRL_GPIO
+#define HBN_REG_EN_AON_CTRL_GPIO_POS   (20U)
+#define HBN_REG_EN_AON_CTRL_GPIO_LEN   (4U)
+#define HBN_REG_EN_AON_CTRL_GPIO_MSK   (((1U << HBN_REG_EN_AON_CTRL_GPIO_LEN) - 1) << HBN_REG_EN_AON_CTRL_GPIO_POS)
+#define HBN_REG_EN_AON_CTRL_GPIO_UMSK  (~(((1U << HBN_REG_EN_AON_CTRL_GPIO_LEN) - 1) << HBN_REG_EN_AON_CTRL_GPIO_POS))
+#define HBN_CR_GPIO_KEEP_EN            HBN_CR_GPIO_KEEP_EN
+#define HBN_CR_GPIO_KEEP_EN_POS        (28U)
+#define HBN_CR_GPIO_KEEP_EN_LEN        (3U)
+#define HBN_CR_GPIO_KEEP_EN_MSK        (((1U << HBN_CR_GPIO_KEEP_EN_LEN) - 1) << HBN_CR_GPIO_KEEP_EN_POS)
+#define HBN_CR_GPIO_KEEP_EN_UMSK       (~(((1U << HBN_CR_GPIO_KEEP_EN_LEN) - 1) << HBN_CR_GPIO_KEEP_EN_POS))
+#define HBN_REG_AON_GPIO_ISO_MODE      HBN_REG_AON_GPIO_ISO_MODE
+#define HBN_REG_AON_GPIO_ISO_MODE_POS  (31U)
+#define HBN_REG_AON_GPIO_ISO_MODE_LEN  (1U)
+#define HBN_REG_AON_GPIO_ISO_MODE_MSK  (((1U << HBN_REG_AON_GPIO_ISO_MODE_LEN) - 1) << HBN_REG_AON_GPIO_ISO_MODE_POS)
+#define HBN_REG_AON_GPIO_ISO_MODE_UMSK (~(((1U << HBN_REG_AON_GPIO_ISO_MODE_LEN) - 1) << HBN_REG_AON_GPIO_ISO_MODE_POS))
+
+/* 0x3C : HBN_PAD_CTRL_1 */
+#define HBN_PAD_CTRL_1_OFFSET   (0x3C)
+#define HBN_REG_AON_PAD_OE      HBN_REG_AON_PAD_OE
+#define HBN_REG_AON_PAD_OE_POS  (0U)
+#define HBN_REG_AON_PAD_OE_LEN  (4U)
+#define HBN_REG_AON_PAD_OE_MSK  (((1U << HBN_REG_AON_PAD_OE_LEN) - 1) << HBN_REG_AON_PAD_OE_POS)
+#define HBN_REG_AON_PAD_OE_UMSK (~(((1U << HBN_REG_AON_PAD_OE_LEN) - 1) << HBN_REG_AON_PAD_OE_POS))
+#define HBN_REG_AON_PAD_PD      HBN_REG_AON_PAD_PD
+#define HBN_REG_AON_PAD_PD_POS  (10U)
+#define HBN_REG_AON_PAD_PD_LEN  (4U)
+#define HBN_REG_AON_PAD_PD_MSK  (((1U << HBN_REG_AON_PAD_PD_LEN) - 1) << HBN_REG_AON_PAD_PD_POS)
+#define HBN_REG_AON_PAD_PD_UMSK (~(((1U << HBN_REG_AON_PAD_PD_LEN) - 1) << HBN_REG_AON_PAD_PD_POS))
+#define HBN_REG_AON_PAD_PU      HBN_REG_AON_PAD_PU
+#define HBN_REG_AON_PAD_PU_POS  (20U)
+#define HBN_REG_AON_PAD_PU_LEN  (4U)
+#define HBN_REG_AON_PAD_PU_MSK  (((1U << HBN_REG_AON_PAD_PU_LEN) - 1) << HBN_REG_AON_PAD_PU_POS)
+#define HBN_REG_AON_PAD_PU_UMSK (~(((1U << HBN_REG_AON_PAD_PU_LEN) - 1) << HBN_REG_AON_PAD_PU_POS))
+
+/* 0x40 : vbat_ldo */
+#define HBN_VBAT_LDO_OFFSET             (0x40)
+#define HBN_LDO33_BM_AON                HBN_LDO33_BM_AON
+#define HBN_LDO33_BM_AON_POS            (0U)
+#define HBN_LDO33_BM_AON_LEN            (2U)
+#define HBN_LDO33_BM_AON_MSK            (((1U << HBN_LDO33_BM_AON_LEN) - 1) << HBN_LDO33_BM_AON_POS)
+#define HBN_LDO33_BM_AON_UMSK           (~(((1U << HBN_LDO33_BM_AON_LEN) - 1) << HBN_LDO33_BM_AON_POS))
+#define HBN_LDO33_CC_AON                HBN_LDO33_CC_AON
+#define HBN_LDO33_CC_AON_POS            (4U)
+#define HBN_LDO33_CC_AON_LEN            (3U)
+#define HBN_LDO33_CC_AON_MSK            (((1U << HBN_LDO33_CC_AON_LEN) - 1) << HBN_LDO33_CC_AON_POS)
+#define HBN_LDO33_CC_AON_UMSK           (~(((1U << HBN_LDO33_CC_AON_LEN) - 1) << HBN_LDO33_CC_AON_POS))
+#define HBN_LDO33_OCP_EN_AON            HBN_LDO33_OCP_EN_AON
+#define HBN_LDO33_OCP_EN_AON_POS        (7U)
+#define HBN_LDO33_OCP_EN_AON_LEN        (1U)
+#define HBN_LDO33_OCP_EN_AON_MSK        (((1U << HBN_LDO33_OCP_EN_AON_LEN) - 1) << HBN_LDO33_OCP_EN_AON_POS)
+#define HBN_LDO33_OCP_EN_AON_UMSK       (~(((1U << HBN_LDO33_OCP_EN_AON_LEN) - 1) << HBN_LDO33_OCP_EN_AON_POS))
+#define HBN_LDO33_OCP_TH_AON            HBN_LDO33_OCP_TH_AON
+#define HBN_LDO33_OCP_TH_AON_POS        (8U)
+#define HBN_LDO33_OCP_TH_AON_LEN        (3U)
+#define HBN_LDO33_OCP_TH_AON_MSK        (((1U << HBN_LDO33_OCP_TH_AON_LEN) - 1) << HBN_LDO33_OCP_TH_AON_POS)
+#define HBN_LDO33_OCP_TH_AON_UMSK       (~(((1U << HBN_LDO33_OCP_TH_AON_LEN) - 1) << HBN_LDO33_OCP_TH_AON_POS))
+#define HBN_LDO33_SSTART_DELAY_AON      HBN_LDO33_SSTART_DELAY_AON
+#define HBN_LDO33_SSTART_DELAY_AON_POS  (12U)
+#define HBN_LDO33_SSTART_DELAY_AON_LEN  (3U)
+#define HBN_LDO33_SSTART_DELAY_AON_MSK  (((1U << HBN_LDO33_SSTART_DELAY_AON_LEN) - 1) << HBN_LDO33_SSTART_DELAY_AON_POS)
+#define HBN_LDO33_SSTART_DELAY_AON_UMSK (~(((1U << HBN_LDO33_SSTART_DELAY_AON_LEN) - 1) << HBN_LDO33_SSTART_DELAY_AON_POS))
+#define HBN_LDO33_SSTART_EN_AON         HBN_LDO33_SSTART_EN_AON
+#define HBN_LDO33_SSTART_EN_AON_POS     (15U)
+#define HBN_LDO33_SSTART_EN_AON_LEN     (1U)
+#define HBN_LDO33_SSTART_EN_AON_MSK     (((1U << HBN_LDO33_SSTART_EN_AON_LEN) - 1) << HBN_LDO33_SSTART_EN_AON_POS)
+#define HBN_LDO33_SSTART_EN_AON_UMSK    (~(((1U << HBN_LDO33_SSTART_EN_AON_LEN) - 1) << HBN_LDO33_SSTART_EN_AON_POS))
+#define HBN_LDO33_VOUT_SEL_AON          HBN_LDO33_VOUT_SEL_AON
+#define HBN_LDO33_VOUT_SEL_AON_POS      (16U)
+#define HBN_LDO33_VOUT_SEL_AON_LEN      (4U)
+#define HBN_LDO33_VOUT_SEL_AON_MSK      (((1U << HBN_LDO33_VOUT_SEL_AON_LEN) - 1) << HBN_LDO33_VOUT_SEL_AON_POS)
+#define HBN_LDO33_VOUT_SEL_AON_UMSK     (~(((1U << HBN_LDO33_VOUT_SEL_AON_LEN) - 1) << HBN_LDO33_VOUT_SEL_AON_POS))
+#define HBN_LDO33_VOUT_TRIM_AON         HBN_LDO33_VOUT_TRIM_AON
+#define HBN_LDO33_VOUT_TRIM_AON_POS     (20U)
+#define HBN_LDO33_VOUT_TRIM_AON_LEN     (4U)
+#define HBN_LDO33_VOUT_TRIM_AON_MSK     (((1U << HBN_LDO33_VOUT_TRIM_AON_LEN) - 1) << HBN_LDO33_VOUT_TRIM_AON_POS)
+#define HBN_LDO33_VOUT_TRIM_AON_UMSK    (~(((1U << HBN_LDO33_VOUT_TRIM_AON_LEN) - 1) << HBN_LDO33_VOUT_TRIM_AON_POS))
+#define HBN_LDO33_OTP_EN_AON            HBN_LDO33_OTP_EN_AON
+#define HBN_LDO33_OTP_EN_AON_POS        (24U)
+#define HBN_LDO33_OTP_EN_AON_LEN        (1U)
+#define HBN_LDO33_OTP_EN_AON_MSK        (((1U << HBN_LDO33_OTP_EN_AON_LEN) - 1) << HBN_LDO33_OTP_EN_AON_POS)
+#define HBN_LDO33_OTP_EN_AON_UMSK       (~(((1U << HBN_LDO33_OTP_EN_AON_LEN) - 1) << HBN_LDO33_OTP_EN_AON_POS))
+#define HBN_LDO33_OTP_OUT_AON           HBN_LDO33_OTP_OUT_AON
+#define HBN_LDO33_OTP_OUT_AON_POS       (25U)
+#define HBN_LDO33_OTP_OUT_AON_LEN       (1U)
+#define HBN_LDO33_OTP_OUT_AON_MSK       (((1U << HBN_LDO33_OTP_OUT_AON_LEN) - 1) << HBN_LDO33_OTP_OUT_AON_POS)
+#define HBN_LDO33_OTP_OUT_AON_UMSK      (~(((1U << HBN_LDO33_OTP_OUT_AON_LEN) - 1) << HBN_LDO33_OTP_OUT_AON_POS))
+#define HBN_LDO33_OCP_OUT_AON           HBN_LDO33_OCP_OUT_AON
+#define HBN_LDO33_OCP_OUT_AON_POS       (26U)
+#define HBN_LDO33_OCP_OUT_AON_LEN       (1U)
+#define HBN_LDO33_OCP_OUT_AON_MSK       (((1U << HBN_LDO33_OCP_OUT_AON_LEN) - 1) << HBN_LDO33_OCP_OUT_AON_POS)
+#define HBN_LDO33_OCP_OUT_AON_UMSK      (~(((1U << HBN_LDO33_OCP_OUT_AON_LEN) - 1) << HBN_LDO33_OCP_OUT_AON_POS))
+#define HBN_TEN_LDO33_AON               HBN_TEN_LDO33_AON
+#define HBN_TEN_LDO33_AON_POS           (27U)
+#define HBN_TEN_LDO33_AON_LEN           (1U)
+#define HBN_TEN_LDO33_AON_MSK           (((1U << HBN_TEN_LDO33_AON_LEN) - 1) << HBN_TEN_LDO33_AON_POS)
+#define HBN_TEN_LDO33_AON_UMSK          (~(((1U << HBN_TEN_LDO33_AON_LEN) - 1) << HBN_TEN_LDO33_AON_POS))
+#define HBN_LDO33_OTP_TH_AON            HBN_LDO33_OTP_TH_AON
+#define HBN_LDO33_OTP_TH_AON_POS        (28U)
+#define HBN_LDO33_OTP_TH_AON_LEN        (3U)
+#define HBN_LDO33_OTP_TH_AON_MSK        (((1U << HBN_LDO33_OTP_TH_AON_LEN) - 1) << HBN_LDO33_OTP_TH_AON_POS)
+#define HBN_LDO33_OTP_TH_AON_UMSK       (~(((1U << HBN_LDO33_OTP_TH_AON_LEN) - 1) << HBN_LDO33_OTP_TH_AON_POS))
+#define HBN_LDO33_OTP_SD_AON            HBN_LDO33_OTP_SD_AON
+#define HBN_LDO33_OTP_SD_AON_POS        (31U)
+#define HBN_LDO33_OTP_SD_AON_LEN        (1U)
+#define HBN_LDO33_OTP_SD_AON_MSK        (((1U << HBN_LDO33_OTP_SD_AON_LEN) - 1) << HBN_LDO33_OTP_SD_AON_POS)
+#define HBN_LDO33_OTP_SD_AON_UMSK       (~(((1U << HBN_LDO33_OTP_SD_AON_LEN) - 1) << HBN_LDO33_OTP_SD_AON_POS))
+
+/* 0x100 : HBN_RSV0 */
+#define HBN_RSV0_OFFSET (0x100)
+#define HBN_RSV0        HBN_RSV0
+#define HBN_RSV0_POS    (0U)
+#define HBN_RSV0_LEN    (32U)
+#define HBN_RSV0_MSK    (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
+#define HBN_RSV0_UMSK   (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
+
+/* 0x104 : HBN_RSV1 */
+#define HBN_RSV1_OFFSET (0x104)
+#define HBN_RSV1        HBN_RSV1
+#define HBN_RSV1_POS    (0U)
+#define HBN_RSV1_LEN    (32U)
+#define HBN_RSV1_MSK    (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
+#define HBN_RSV1_UMSK   (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
+
+/* 0x108 : HBN_RSV2 */
+#define HBN_RSV2_OFFSET (0x108)
+#define HBN_RSV2        HBN_RSV2
+#define HBN_RSV2_POS    (0U)
+#define HBN_RSV2_LEN    (32U)
+#define HBN_RSV2_MSK    (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
+#define HBN_RSV2_UMSK   (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
+
+/* 0x10C : HBN_RSV3 */
+#define HBN_RSV3_OFFSET (0x10C)
+#define HBN_RSV3        HBN_RSV3
+#define HBN_RSV3_POS    (0U)
+#define HBN_RSV3_LEN    (32U)
+#define HBN_RSV3_MSK    (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
+#define HBN_RSV3_UMSK   (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
+
+/* 0x200 : rc32k_ctrl0 */
+#define HBN_RC32K_CTRL0_OFFSET         (0x200)
+#define HBN_RC32K_CAL_DONE             HBN_RC32K_CAL_DONE
+#define HBN_RC32K_CAL_DONE_POS         (0U)
+#define HBN_RC32K_CAL_DONE_LEN         (1U)
+#define HBN_RC32K_CAL_DONE_MSK         (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
+#define HBN_RC32K_CAL_DONE_UMSK        (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
+#define HBN_RC32K_RDY                  HBN_RC32K_RDY
+#define HBN_RC32K_RDY_POS              (1U)
+#define HBN_RC32K_RDY_LEN              (1U)
+#define HBN_RC32K_RDY_MSK              (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
+#define HBN_RC32K_RDY_UMSK             (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
+#define HBN_RC32K_CAL_INPROGRESS       HBN_RC32K_CAL_INPROGRESS
+#define HBN_RC32K_CAL_INPROGRESS_POS   (2U)
+#define HBN_RC32K_CAL_INPROGRESS_LEN   (1U)
+#define HBN_RC32K_CAL_INPROGRESS_MSK   (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
+#define HBN_RC32K_CAL_INPROGRESS_UMSK  (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
+#define HBN_RC32K_CAL_DIV              HBN_RC32K_CAL_DIV
+#define HBN_RC32K_CAL_DIV_POS          (3U)
+#define HBN_RC32K_CAL_DIV_LEN          (2U)
+#define HBN_RC32K_CAL_DIV_MSK          (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
+#define HBN_RC32K_CAL_DIV_UMSK         (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
+#define HBN_RC32K_CAL_PRECHARGE        HBN_RC32K_CAL_PRECHARGE
+#define HBN_RC32K_CAL_PRECHARGE_POS    (5U)
+#define HBN_RC32K_CAL_PRECHARGE_LEN    (1U)
+#define HBN_RC32K_CAL_PRECHARGE_MSK    (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
+#define HBN_RC32K_CAL_PRECHARGE_UMSK   (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
+#define HBN_RC32K_DIG_CODE_FR_CAL      HBN_RC32K_DIG_CODE_FR_CAL
+#define HBN_RC32K_DIG_CODE_FR_CAL_POS  (6U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_LEN  (10U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_MSK  (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
+#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
+#define HBN_RC32K_VREF_DLY             HBN_RC32K_VREF_DLY
+#define HBN_RC32K_VREF_DLY_POS         (16U)
+#define HBN_RC32K_VREF_DLY_LEN         (2U)
+#define HBN_RC32K_VREF_DLY_MSK         (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
+#define HBN_RC32K_VREF_DLY_UMSK        (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
+#define HBN_RC32K_ALLOW_CAL            HBN_RC32K_ALLOW_CAL
+#define HBN_RC32K_ALLOW_CAL_POS        (18U)
+#define HBN_RC32K_ALLOW_CAL_LEN        (1U)
+#define HBN_RC32K_ALLOW_CAL_MSK        (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
+#define HBN_RC32K_ALLOW_CAL_UMSK       (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
+#define HBN_RC32K_EXT_CODE_EN          HBN_RC32K_EXT_CODE_EN
+#define HBN_RC32K_EXT_CODE_EN_POS      (19U)
+#define HBN_RC32K_EXT_CODE_EN_LEN      (1U)
+#define HBN_RC32K_EXT_CODE_EN_MSK      (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
+#define HBN_RC32K_EXT_CODE_EN_UMSK     (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
+#define HBN_RC32K_CAL_EN               HBN_RC32K_CAL_EN
+#define HBN_RC32K_CAL_EN_POS           (20U)
+#define HBN_RC32K_CAL_EN_LEN           (1U)
+#define HBN_RC32K_CAL_EN_MSK           (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
+#define HBN_RC32K_CAL_EN_UMSK          (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
+#define HBN_CR_PU_RC32K                HBN_CR_PU_RC32K
+#define HBN_CR_PU_RC32K_POS            (21U)
+#define HBN_CR_PU_RC32K_LEN            (1U)
+#define HBN_CR_PU_RC32K_MSK            (((1U << HBN_CR_PU_RC32K_LEN) - 1) << HBN_CR_PU_RC32K_POS)
+#define HBN_CR_PU_RC32K_UMSK           (~(((1U << HBN_CR_PU_RC32K_LEN) - 1) << HBN_CR_PU_RC32K_POS))
+#define HBN_RC32K_CODE_FR_EXT          HBN_RC32K_CODE_FR_EXT
+#define HBN_RC32K_CODE_FR_EXT_POS      (22U)
+#define HBN_RC32K_CODE_FR_EXT_LEN      (10U)
+#define HBN_RC32K_CODE_FR_EXT_MSK      (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
+#define HBN_RC32K_CODE_FR_EXT_UMSK     (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
+
+/* 0x204 : xtal32k */
+#define HBN_XTAL32K_OFFSET            (0x204)
+#define HBN_XTAL32K_EXT_SEL           HBN_XTAL32K_EXT_SEL
+#define HBN_XTAL32K_EXT_SEL_POS       (2U)
+#define HBN_XTAL32K_EXT_SEL_LEN       (1U)
+#define HBN_XTAL32K_EXT_SEL_MSK       (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
+#define HBN_XTAL32K_EXT_SEL_UMSK      (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
+#define HBN_XTAL32K_AMP_CTRL          HBN_XTAL32K_AMP_CTRL
+#define HBN_XTAL32K_AMP_CTRL_POS      (3U)
+#define HBN_XTAL32K_AMP_CTRL_LEN      (2U)
+#define HBN_XTAL32K_AMP_CTRL_MSK      (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
+#define HBN_XTAL32K_AMP_CTRL_UMSK     (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
+#define HBN_XTAL32K_REG               HBN_XTAL32K_REG
+#define HBN_XTAL32K_REG_POS           (5U)
+#define HBN_XTAL32K_REG_LEN           (2U)
+#define HBN_XTAL32K_REG_MSK           (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
+#define HBN_XTAL32K_REG_UMSK          (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
+#define HBN_XTAL32K_OUTBUF_STRE       HBN_XTAL32K_OUTBUF_STRE
+#define HBN_XTAL32K_OUTBUF_STRE_POS   (7U)
+#define HBN_XTAL32K_OUTBUF_STRE_LEN   (1U)
+#define HBN_XTAL32K_OUTBUF_STRE_MSK   (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
+#define HBN_XTAL32K_OUTBUF_STRE_UMSK  (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
+#define HBN_XTAL32K_OTF_SHORT         HBN_XTAL32K_OTF_SHORT
+#define HBN_XTAL32K_OTF_SHORT_POS     (8U)
+#define HBN_XTAL32K_OTF_SHORT_LEN     (1U)
+#define HBN_XTAL32K_OTF_SHORT_MSK     (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
+#define HBN_XTAL32K_OTF_SHORT_UMSK    (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
+#define HBN_XTAL32K_INV_STRE          HBN_XTAL32K_INV_STRE
+#define HBN_XTAL32K_INV_STRE_POS      (9U)
+#define HBN_XTAL32K_INV_STRE_LEN      (2U)
+#define HBN_XTAL32K_INV_STRE_MSK      (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
+#define HBN_XTAL32K_INV_STRE_UMSK     (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
+#define HBN_XTAL32K_CAPBANK           HBN_XTAL32K_CAPBANK
+#define HBN_XTAL32K_CAPBANK_POS       (11U)
+#define HBN_XTAL32K_CAPBANK_LEN       (6U)
+#define HBN_XTAL32K_CAPBANK_MSK       (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
+#define HBN_XTAL32K_CAPBANK_UMSK      (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
+#define HBN_XTAL32K_AC_CAP_SHORT      HBN_XTAL32K_AC_CAP_SHORT
+#define HBN_XTAL32K_AC_CAP_SHORT_POS  (17U)
+#define HBN_XTAL32K_AC_CAP_SHORT_LEN  (1U)
+#define HBN_XTAL32K_AC_CAP_SHORT_MSK  (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
+#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
+#define HBN_PU_XTAL32K_BUF            HBN_PU_XTAL32K_BUF
+#define HBN_PU_XTAL32K_BUF_POS        (18U)
+#define HBN_PU_XTAL32K_BUF_LEN        (1U)
+#define HBN_PU_XTAL32K_BUF_MSK        (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
+#define HBN_PU_XTAL32K_BUF_UMSK       (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
+#define HBN_PU_XTAL32K                HBN_PU_XTAL32K
+#define HBN_PU_XTAL32K_POS            (19U)
+#define HBN_PU_XTAL32K_LEN            (1U)
+#define HBN_PU_XTAL32K_MSK            (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
+#define HBN_PU_XTAL32K_UMSK           (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
+#define HBN_XTAL32K_LOWV_EN           HBN_XTAL32K_LOWV_EN
+#define HBN_XTAL32K_LOWV_EN_POS       (20U)
+#define HBN_XTAL32K_LOWV_EN_LEN       (1U)
+#define HBN_XTAL32K_LOWV_EN_MSK       (((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS)
+#define HBN_XTAL32K_LOWV_EN_UMSK      (~(((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS))
+#define HBN_XTAL32K_HIZ_EN            HBN_XTAL32K_HIZ_EN
+#define HBN_XTAL32K_HIZ_EN_POS        (21U)
+#define HBN_XTAL32K_HIZ_EN_LEN        (1U)
+#define HBN_XTAL32K_HIZ_EN_MSK        (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)
+#define HBN_XTAL32K_HIZ_EN_UMSK       (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS))
+#define HBN_DTEN_XTAL32K              HBN_DTEN_XTAL32K
+#define HBN_DTEN_XTAL32K_POS          (22U)
+#define HBN_DTEN_XTAL32K_LEN          (1U)
+#define HBN_DTEN_XTAL32K_MSK          (((1U << HBN_DTEN_XTAL32K_LEN) - 1) << HBN_DTEN_XTAL32K_POS)
+#define HBN_DTEN_XTAL32K_UMSK         (~(((1U << HBN_DTEN_XTAL32K_LEN) - 1) << HBN_DTEN_XTAL32K_POS))
+#define HBN_TEN_XTAL32K               HBN_TEN_XTAL32K
+#define HBN_TEN_XTAL32K_POS           (23U)
+#define HBN_TEN_XTAL32K_LEN           (1U)
+#define HBN_TEN_XTAL32K_MSK           (((1U << HBN_TEN_XTAL32K_LEN) - 1) << HBN_TEN_XTAL32K_POS)
+#define HBN_TEN_XTAL32K_UMSK          (~(((1U << HBN_TEN_XTAL32K_LEN) - 1) << HBN_TEN_XTAL32K_POS))
+
+struct hbn_reg {
+    /* 0x0 : HBN_CTL */
+    union {
+        struct {
+            uint32_t rtc_ctl                  : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t rtc_dly_option           : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_6             : 2; /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t hbn_mode                 : 1; /* [    7],          w,        0x0 */
+            uint32_t trap_mode                : 1; /* [    8],          r,        0x0 */
+            uint32_t pwrdn_hbn_core           : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10              : 1; /* [   10],       rsvd,        0x0 */
+            uint32_t pwrdn_hbn_rtc            : 1; /* [   11],        r/w,        0x0 */
+            uint32_t sw_rst                   : 1; /* [   12],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [   14],        r/w,        0x0 */
+            uint32_t hbn_ldo11_rt_vout_sel    : 4; /* [18:15],        r/w,        0xa */
+            uint32_t hbn_ldo11_aon_vout_sel   : 4; /* [22:19],        r/w,        0xa */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t pu_dcdc18_aon            : 1; /* [   24],        r/w,        0x1 */
+            uint32_t pwr_on_option            : 1; /* [   25],        r/w,        0x0 */
+            uint32_t sram_slp_option          : 1; /* [   26],        r/w,        0x0 */
+            uint32_t sram_slp                 : 1; /* [   27],          r,        0x0 */
+            uint32_t hbn_state                : 4; /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_CTL;
+
+    /* 0x4 : HBN_TIME_L */
+    union {
+        struct {
+            uint32_t hbn_time_l : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_L;
+
+    /* 0x8 : HBN_TIME_H */
+    union {
+        struct {
+            uint32_t hbn_time_h    : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_H;
+
+    /* 0xC : RTC_TIME_L */
+    union {
+        struct {
+            uint32_t rtc_time_latch_l : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_L;
+
+    /* 0x10 : RTC_TIME_H */
+    union {
+        struct {
+            uint32_t rtc_time_latch_h : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_30    : 23; /* [30: 8],       rsvd,        0x0 */
+            uint32_t rtc_time_latch   : 1;  /* [   31],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_H;
+
+    /* 0x14 : HBN_IRQ_MODE */
+    union {
+        struct {
+            uint32_t hbn_pin_wakeup_mode : 4; /* [ 3: 0],        r/w,        0x5 */
+            uint32_t hbn_pin_wakeup_mask : 4; /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_15       : 8; /* [15: 8],       rsvd,        0x0 */
+            uint32_t reg_en_hw_pu_pd     : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reserved_17         : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t irq_bor_en          : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t irq_acomp0_en       : 2; /* [21:20],        r/w,        0x0 */
+            uint32_t irq_acomp1_en       : 2; /* [23:22],        r/w,        0x0 */
+            uint32_t pin_wakeup_sel      : 3; /* [26:24],        r/w,        0x3 */
+            uint32_t pin_wakeup_en       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reserved_28_31      : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_MODE;
+
+    /* 0x18 : HBN_IRQ_STAT */
+    union {
+        struct {
+            uint32_t irq_stat : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_STAT;
+
+    /* 0x1C : HBN_IRQ_CLR */
+    union {
+        struct {
+            uint32_t irq_clr : 32; /* [31: 0],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_CLR;
+
+    /* 0x20 : HBN_PIR_CFG */
+    union {
+        struct {
+            uint32_t pir_hpf_sel   : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pir_lpf_sel   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3    : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t pir_dis       : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6    : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t pir_en        : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_cs      : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_CFG;
+
+    /* 0x24 : HBN_PIR_VTH */
+    union {
+        struct {
+            uint32_t pir_vth        : 14; /* [13: 0],        r/w,      0x3ff */
+            uint32_t reserved_14_31 : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_VTH;
+
+    /* 0x28 : HBN_PIR_INTERVAL */
+    union {
+        struct {
+            uint32_t pir_interval   : 12; /* [11: 0],        r/w,      0xa3d */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_INTERVAL;
+
+    /* 0x2C : HBN_BOR_CFG */
+    union {
+        struct {
+            uint32_t bod_sel       : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t bod_vth       : 3;  /* [ 3: 1],        r/w,        0x5 */
+            uint32_t pu_bod        : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t r_bod_out     : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_31 : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_BOR_CFG;
+
+    /* 0x30 : HBN_GLB */
+    union {
+        struct {
+            uint32_t hbn_root_clk_sel         : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t hbn_uart_clk_sel         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t hbn_f32k_sel             : 2; /* [ 4: 3],        r/w,        0x0 */
+            uint32_t hbn_pu_rc32k             : 1; /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6               : 1; /* [    6],       rsvd,        0x0 */
+            uint32_t hbn_reset_event          : 5; /* [11: 7],          r,        0x0 */
+            uint32_t reserved_12_14           : 3; /* [14:12],       rsvd,        0x0 */
+            uint32_t hbn_uart_clk_sel2        : 1; /* [   15],        r/w,        0x0 */
+            uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16],        r/w,        0xa */
+            uint32_t reserved_20_23           : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t sw_ldo11_rt_vout_sel     : 4; /* [27:24],        r/w,        0xa */
+            uint32_t sw_ldo11_aon_vout_sel    : 4; /* [31:28],        r/w,        0xa */
+        } BF;
+        uint32_t WORD;
+    } HBN_GLB;
+
+    /* 0x34 : HBN_SRAM */
+    union {
+        struct {
+            uint32_t reserved_0_5  : 6;  /* [ 5: 0],       rsvd,        0x0 */
+            uint32_t retram_ret    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t retram_slp    : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_SRAM;
+
+    /* 0x38 : HBN_PAD_CTRL_0 */
+    union {
+        struct {
+            uint32_t reg_aon_pad_ie_smt    : 4; /* [ 3: 0],       None,        0x0 */
+            uint32_t reserved_4_9          : 6; /* [ 9: 4],       rsvd,        0x0 */
+            uint32_t reg_aon_led_sel       : 9; /* [18:10],       None,        0x0 */
+            uint32_t reserved_19           : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t reg_en_aon_ctrl_gpio  : 4; /* [23:20],       None,        0x0 */
+            uint32_t reserved_24_27        : 4; /* [27:24],       rsvd,        0x0 */
+            uint32_t cr_gpio_keep_en       : 3; /* [30:28],        r/w,        0x0 */
+            uint32_t reg_aon_gpio_iso_mode : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PAD_CTRL_0;
+
+    /* 0x3C : HBN_PAD_CTRL_1 */
+    union {
+        struct {
+            uint32_t reg_aon_pad_oe : 4; /* [ 3: 0],       None,        0x0 */
+            uint32_t reserved_4_9   : 6; /* [ 9: 4],       rsvd,        0x0 */
+            uint32_t reg_aon_pad_pd : 4; /* [13:10],       None,        0x0 */
+            uint32_t reserved_14_19 : 6; /* [19:14],       rsvd,        0x0 */
+            uint32_t reg_aon_pad_pu : 4; /* [23:20],       None,        0x0 */
+            uint32_t reserved_24_31 : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PAD_CTRL_1;
+
+    /* 0x40 : vbat_ldo */
+    union {
+        struct {
+            uint32_t ldo33_bm_aon           : 2; /* [ 1: 0],        r/w,        0x1 */
+            uint32_t reserved_2_3           : 2; /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t ldo33_cc_aon           : 3; /* [ 6: 4],        r/w,        0x1 */
+            uint32_t ldo33_ocp_en_aon       : 1; /* [    7],        r/w,        0x1 */
+            uint32_t ldo33_ocp_th_aon       : 3; /* [10: 8],        r/w,        0x5 */
+            uint32_t reserved_11            : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t ldo33_sstart_delay_aon : 3; /* [14:12],        r/w,        0x3 */
+            uint32_t ldo33_sstart_en_aon    : 1; /* [   15],        r/w,        0x1 */
+            uint32_t ldo33_vout_sel_aon     : 4; /* [19:16],        r/w,        0xb */
+            uint32_t ldo33_vout_trim_aon    : 4; /* [23:20],        r/w,        0x8 */
+            uint32_t ldo33_otp_en_aon       : 1; /* [   24],        r/w,        0x1 */
+            uint32_t ldo33_otp_out_aon      : 1; /* [   25],          r,        0x0 */
+            uint32_t ldo33_ocp_out_aon      : 1; /* [   26],          r,        0x0 */
+            uint32_t ten_ldo33_aon          : 1; /* [   27],        r/w,        0x0 */
+            uint32_t ldo33_otp_th_aon       : 3; /* [30:28],        r/w,        0x7 */
+            uint32_t ldo33_otp_sd_aon       : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } vbat_ldo;
+
+    /* 0x44  reserved */
+    uint8_t RESERVED0x44[188];
+
+    /* 0x100 : HBN_RSV0 */
+    union {
+        struct {
+            uint32_t HBN_RSV0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV0;
+
+    /* 0x104 : HBN_RSV1 */
+    union {
+        struct {
+            uint32_t HBN_RSV1 : 32; /* [31: 0],        r/w, 0xffffffff */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV1;
+
+    /* 0x108 : HBN_RSV2 */
+    union {
+        struct {
+            uint32_t HBN_RSV2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV2;
+
+    /* 0x10C : HBN_RSV3 */
+    union {
+        struct {
+            uint32_t HBN_RSV3 : 32; /* [31: 0],        r/w, 0xffffffff */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV3;
+
+    /* 0x110  reserved */
+    uint8_t RESERVED0x110[240];
+
+    /* 0x200 : rc32k_ctrl0 */
+    union {
+        struct {
+            uint32_t rc32k_cal_done        : 1;  /* [    0],          r,        0x1 */
+            uint32_t rc32k_rdy             : 1;  /* [    1],          r,        0x1 */
+            uint32_t rc32k_cal_inprogress  : 1;  /* [    2],          r,        0x0 */
+            uint32_t rc32k_cal_div         : 2;  /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32k_cal_precharge   : 1;  /* [    5],          r,        0x0 */
+            uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6],          r,      0x200 */
+            uint32_t rc32k_vref_dly        : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t rc32k_allow_cal       : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t rc32k_ext_code_en     : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t rc32k_cal_en          : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t pu_rc32k              : 1;  /* [   21],        r/w,        0x1 */
+            uint32_t rc32k_code_fr_ext     : 10; /* [31:22],        r/w,      0x12c */
+        } BF;
+        uint32_t WORD;
+    } rc32k_ctrl0;
+
+    /* 0x204 : xtal32k */
+    union {
+        struct {
+            uint32_t reserved_0_1         : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t xtal32k_ext_sel      : 1; /* [    2],        r/w,        0x0 */
+            uint32_t xtal32k_amp_ctrl     : 2; /* [ 4: 3],        r/w,        0x1 */
+            uint32_t xtal32k_reg          : 2; /* [ 6: 5],        r/w,        0x1 */
+            uint32_t xtal32k_outbuf_stre  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t xtal32k_otf_short    : 1; /* [    8],        r/w,        0x0 */
+            uint32_t xtal32k_inv_stre     : 2; /* [10: 9],        r/w,        0x1 */
+            uint32_t xtal32k_capbank      : 6; /* [16:11],        r/w,       0x20 */
+            uint32_t xtal32k_ac_cap_short : 1; /* [   17],        r/w,        0x0 */
+            uint32_t pu_xtal32k_buf       : 1; /* [   18],        r/w,        0x1 */
+            uint32_t pu_xtal32k           : 1; /* [   19],        r/w,        0x0 */
+            uint32_t xtal32k_lowv_en      : 1; /* [   20],        r/w,        0x0 */
+            uint32_t xtal32k_hiz_en       : 1; /* [   21],        r/w,        0x1 */
+            uint32_t dten_xtal32k         : 1; /* [   22],        r/w,        0x0 */
+            uint32_t ten_xtal32k          : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_31       : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } xtal32k;
+};
+
+typedef volatile struct hbn_reg hbn_reg_t;
+
+#endif /* __HBN_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mcu_misc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mcu_misc_reg.h
new file mode 100755
index 0000000000..fb9bf06c7b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mcu_misc_reg.h
@@ -0,0 +1,421 @@
+/**
+  ******************************************************************************
+  * @file    mcu_misc_reg.h
+  * @version V1.0
+  * @date    2021-11-19
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __MCU_MISC_REG_H__
+#define __MCU_MISC_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : mcu_bus_cfg0 */
+#define MCU_MISC_MCU_BUS_CFG0_OFFSET            (0x0)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN       MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS   (0U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN   (1U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_MSK   (((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_UMSK  (~(((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_EN_POS))
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR      MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS  (1U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN  (1U)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_MSK  (((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS)
+#define MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_TIMEOUT_CLR_POS))
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT          MCU_MISC_STS_MCU_INFRA_TIMEOUT
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS      (16U)
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN      (1U)
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_MSK      (((1U << MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN) - 1) << MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS)
+#define MCU_MISC_STS_MCU_INFRA_TIMEOUT_UMSK     (~(((1U << MCU_MISC_STS_MCU_INFRA_TIMEOUT_LEN) - 1) << MCU_MISC_STS_MCU_INFRA_TIMEOUT_POS))
+
+/* 0x4 : mcu_bus_cfg1 */
+#define MCU_MISC_MCU_BUS_CFG1_OFFSET         (0x4)
+#define MCU_MISC_REG_MCU1_HQOS               MCU_MISC_REG_MCU1_HQOS
+#define MCU_MISC_REG_MCU1_HQOS_POS           (0U)
+#define MCU_MISC_REG_MCU1_HQOS_LEN           (1U)
+#define MCU_MISC_REG_MCU1_HQOS_MSK           (((1U << MCU_MISC_REG_MCU1_HQOS_LEN) - 1) << MCU_MISC_REG_MCU1_HQOS_POS)
+#define MCU_MISC_REG_MCU1_HQOS_UMSK          (~(((1U << MCU_MISC_REG_MCU1_HQOS_LEN) - 1) << MCU_MISC_REG_MCU1_HQOS_POS))
+#define MCU_MISC_REG_MCU1_AWQOS              MCU_MISC_REG_MCU1_AWQOS
+#define MCU_MISC_REG_MCU1_AWQOS_POS          (1U)
+#define MCU_MISC_REG_MCU1_AWQOS_LEN          (1U)
+#define MCU_MISC_REG_MCU1_AWQOS_MSK          (((1U << MCU_MISC_REG_MCU1_AWQOS_LEN) - 1) << MCU_MISC_REG_MCU1_AWQOS_POS)
+#define MCU_MISC_REG_MCU1_AWQOS_UMSK         (~(((1U << MCU_MISC_REG_MCU1_AWQOS_LEN) - 1) << MCU_MISC_REG_MCU1_AWQOS_POS))
+#define MCU_MISC_REG_MCU1_ARQOS              MCU_MISC_REG_MCU1_ARQOS
+#define MCU_MISC_REG_MCU1_ARQOS_POS          (2U)
+#define MCU_MISC_REG_MCU1_ARQOS_LEN          (1U)
+#define MCU_MISC_REG_MCU1_ARQOS_MSK          (((1U << MCU_MISC_REG_MCU1_ARQOS_LEN) - 1) << MCU_MISC_REG_MCU1_ARQOS_POS)
+#define MCU_MISC_REG_MCU1_ARQOS_UMSK         (~(((1U << MCU_MISC_REG_MCU1_ARQOS_LEN) - 1) << MCU_MISC_REG_MCU1_ARQOS_POS))
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT         MCU_MISC_REG_X_WTHRE_MCU2EXT
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_POS     (7U)
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN     (2U)
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_MSK     (((1U << MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN) - 1) << MCU_MISC_REG_X_WTHRE_MCU2EXT_POS)
+#define MCU_MISC_REG_X_WTHRE_MCU2EXT_UMSK    (~(((1U << MCU_MISC_REG_X_WTHRE_MCU2EXT_LEN) - 1) << MCU_MISC_REG_X_WTHRE_MCU2EXT_POS))
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE      MCU_MISC_REG_MCU_INFRA_ARB_MODE
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS  (16U)
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN  (1U)
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_MSK  (((1U << MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS)
+#define MCU_MISC_REG_MCU_INFRA_ARB_MODE_UMSK (~(((1U << MCU_MISC_REG_MCU_INFRA_ARB_MODE_LEN) - 1) << MCU_MISC_REG_MCU_INFRA_ARB_MODE_POS))
+
+/* 0x14 : mcu_e907_rtc */
+#define MCU_MISC_MCU_E907_RTC_OFFSET      (0x14)
+#define MCU_MISC_REG_MCU_RTC_DIV          MCU_MISC_REG_MCU_RTC_DIV
+#define MCU_MISC_REG_MCU_RTC_DIV_POS      (0U)
+#define MCU_MISC_REG_MCU_RTC_DIV_LEN      (10U)
+#define MCU_MISC_REG_MCU_RTC_DIV_MSK      (((1U << MCU_MISC_REG_MCU_RTC_DIV_LEN) - 1) << MCU_MISC_REG_MCU_RTC_DIV_POS)
+#define MCU_MISC_REG_MCU_RTC_DIV_UMSK     (~(((1U << MCU_MISC_REG_MCU_RTC_DIV_LEN) - 1) << MCU_MISC_REG_MCU_RTC_DIV_POS))
+#define MCU_MISC_REG_MCU_RTC_CLK_SEL      MCU_MISC_REG_MCU_RTC_CLK_SEL
+#define MCU_MISC_REG_MCU_RTC_CLK_SEL_POS  (29U)
+#define MCU_MISC_REG_MCU_RTC_CLK_SEL_LEN  (1U)
+#define MCU_MISC_REG_MCU_RTC_CLK_SEL_MSK  (((1U << MCU_MISC_REG_MCU_RTC_CLK_SEL_LEN) - 1) << MCU_MISC_REG_MCU_RTC_CLK_SEL_POS)
+#define MCU_MISC_REG_MCU_RTC_CLK_SEL_UMSK (~(((1U << MCU_MISC_REG_MCU_RTC_CLK_SEL_LEN) - 1) << MCU_MISC_REG_MCU_RTC_CLK_SEL_POS))
+#define MCU_MISC_REG_MCU_RTC_RST          MCU_MISC_REG_MCU_RTC_RST
+#define MCU_MISC_REG_MCU_RTC_RST_POS      (30U)
+#define MCU_MISC_REG_MCU_RTC_RST_LEN      (1U)
+#define MCU_MISC_REG_MCU_RTC_RST_MSK      (((1U << MCU_MISC_REG_MCU_RTC_RST_LEN) - 1) << MCU_MISC_REG_MCU_RTC_RST_POS)
+#define MCU_MISC_REG_MCU_RTC_RST_UMSK     (~(((1U << MCU_MISC_REG_MCU_RTC_RST_LEN) - 1) << MCU_MISC_REG_MCU_RTC_RST_POS))
+#define MCU_MISC_REG_MCU_RTC_EN           MCU_MISC_REG_MCU_RTC_EN
+#define MCU_MISC_REG_MCU_RTC_EN_POS       (31U)
+#define MCU_MISC_REG_MCU_RTC_EN_LEN       (1U)
+#define MCU_MISC_REG_MCU_RTC_EN_MSK       (((1U << MCU_MISC_REG_MCU_RTC_EN_LEN) - 1) << MCU_MISC_REG_MCU_RTC_EN_POS)
+#define MCU_MISC_REG_MCU_RTC_EN_UMSK      (~(((1U << MCU_MISC_REG_MCU_RTC_EN_LEN) - 1) << MCU_MISC_REG_MCU_RTC_EN_POS))
+
+/* 0x100 : mcu_cfg1 */
+#define MCU_MISC_MCU_CFG1_OFFSET        (0x100)
+#define MCU_MISC_REG_MCU1_DFS_REQ       MCU_MISC_REG_MCU1_DFS_REQ
+#define MCU_MISC_REG_MCU1_DFS_REQ_POS   (0U)
+#define MCU_MISC_REG_MCU1_DFS_REQ_LEN   (1U)
+#define MCU_MISC_REG_MCU1_DFS_REQ_MSK   (((1U << MCU_MISC_REG_MCU1_DFS_REQ_LEN) - 1) << MCU_MISC_REG_MCU1_DFS_REQ_POS)
+#define MCU_MISC_REG_MCU1_DFS_REQ_UMSK  (~(((1U << MCU_MISC_REG_MCU1_DFS_REQ_LEN) - 1) << MCU_MISC_REG_MCU1_DFS_REQ_POS))
+#define MCU_MISC_STS_MCU1_DFS_ACK       MCU_MISC_STS_MCU1_DFS_ACK
+#define MCU_MISC_STS_MCU1_DFS_ACK_POS   (2U)
+#define MCU_MISC_STS_MCU1_DFS_ACK_LEN   (1U)
+#define MCU_MISC_STS_MCU1_DFS_ACK_MSK   (((1U << MCU_MISC_STS_MCU1_DFS_ACK_LEN) - 1) << MCU_MISC_STS_MCU1_DFS_ACK_POS)
+#define MCU_MISC_STS_MCU1_DFS_ACK_UMSK  (~(((1U << MCU_MISC_STS_MCU1_DFS_ACK_LEN) - 1) << MCU_MISC_STS_MCU1_DFS_ACK_POS))
+#define MCU_MISC_REG_MCU1_SRST_EN       MCU_MISC_REG_MCU1_SRST_EN
+#define MCU_MISC_REG_MCU1_SRST_EN_POS   (4U)
+#define MCU_MISC_REG_MCU1_SRST_EN_LEN   (2U)
+#define MCU_MISC_REG_MCU1_SRST_EN_MSK   (((1U << MCU_MISC_REG_MCU1_SRST_EN_LEN) - 1) << MCU_MISC_REG_MCU1_SRST_EN_POS)
+#define MCU_MISC_REG_MCU1_SRST_EN_UMSK  (~(((1U << MCU_MISC_REG_MCU1_SRST_EN_LEN) - 1) << MCU_MISC_REG_MCU1_SRST_EN_POS))
+#define MCU_MISC_STS_MCU1_LPMD_B        MCU_MISC_STS_MCU1_LPMD_B
+#define MCU_MISC_STS_MCU1_LPMD_B_POS    (10U)
+#define MCU_MISC_STS_MCU1_LPMD_B_LEN    (2U)
+#define MCU_MISC_STS_MCU1_LPMD_B_MSK    (((1U << MCU_MISC_STS_MCU1_LPMD_B_LEN) - 1) << MCU_MISC_STS_MCU1_LPMD_B_POS)
+#define MCU_MISC_STS_MCU1_LPMD_B_UMSK   (~(((1U << MCU_MISC_STS_MCU1_LPMD_B_LEN) - 1) << MCU_MISC_STS_MCU1_LPMD_B_POS))
+#define MCU_MISC_MCU1_WFI_FORCE         MCU_MISC_MCU1_WFI_FORCE
+#define MCU_MISC_MCU1_WFI_FORCE_POS     (16U)
+#define MCU_MISC_MCU1_WFI_FORCE_LEN     (1U)
+#define MCU_MISC_MCU1_WFI_FORCE_MSK     (((1U << MCU_MISC_MCU1_WFI_FORCE_LEN) - 1) << MCU_MISC_MCU1_WFI_FORCE_POS)
+#define MCU_MISC_MCU1_WFI_FORCE_UMSK    (~(((1U << MCU_MISC_MCU1_WFI_FORCE_LEN) - 1) << MCU_MISC_MCU1_WFI_FORCE_POS))
+#define MCU_MISC_MCU1_NDM_RSTN_EN       MCU_MISC_MCU1_NDM_RSTN_EN
+#define MCU_MISC_MCU1_NDM_RSTN_EN_POS   (28U)
+#define MCU_MISC_MCU1_NDM_RSTN_EN_LEN   (1U)
+#define MCU_MISC_MCU1_NDM_RSTN_EN_MSK   (((1U << MCU_MISC_MCU1_NDM_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_EN_POS)
+#define MCU_MISC_MCU1_NDM_RSTN_EN_UMSK  (~(((1U << MCU_MISC_MCU1_NDM_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_EN_POS))
+#define MCU_MISC_MCU1_HART_RSTN_EN      MCU_MISC_MCU1_HART_RSTN_EN
+#define MCU_MISC_MCU1_HART_RSTN_EN_POS  (29U)
+#define MCU_MISC_MCU1_HART_RSTN_EN_LEN  (1U)
+#define MCU_MISC_MCU1_HART_RSTN_EN_MSK  (((1U << MCU_MISC_MCU1_HART_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_EN_POS)
+#define MCU_MISC_MCU1_HART_RSTN_EN_UMSK (~(((1U << MCU_MISC_MCU1_HART_RSTN_EN_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_EN_POS))
+
+/* 0x110 : mcu1_log1 */
+#define MCU_MISC_MCU1_LOG1_OFFSET     (0x110)
+#define MCU_MISC_STS_MCU1_MCAUSE      MCU_MISC_STS_MCU1_MCAUSE
+#define MCU_MISC_STS_MCU1_MCAUSE_POS  (0U)
+#define MCU_MISC_STS_MCU1_MCAUSE_LEN  (32U)
+#define MCU_MISC_STS_MCU1_MCAUSE_MSK  (((1U << MCU_MISC_STS_MCU1_MCAUSE_LEN) - 1) << MCU_MISC_STS_MCU1_MCAUSE_POS)
+#define MCU_MISC_STS_MCU1_MCAUSE_UMSK (~(((1U << MCU_MISC_STS_MCU1_MCAUSE_LEN) - 1) << MCU_MISC_STS_MCU1_MCAUSE_POS))
+
+/* 0x114 : mcu1_log2 */
+#define MCU_MISC_MCU1_LOG2_OFFSET         (0x114)
+#define MCU_MISC_STS_MCU1_MINTSTATUS      MCU_MISC_STS_MCU1_MINTSTATUS
+#define MCU_MISC_STS_MCU1_MINTSTATUS_POS  (0U)
+#define MCU_MISC_STS_MCU1_MINTSTATUS_LEN  (32U)
+#define MCU_MISC_STS_MCU1_MINTSTATUS_MSK  (((1U << MCU_MISC_STS_MCU1_MINTSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MINTSTATUS_POS)
+#define MCU_MISC_STS_MCU1_MINTSTATUS_UMSK (~(((1U << MCU_MISC_STS_MCU1_MINTSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MINTSTATUS_POS))
+
+/* 0x118 : mcu1_log3 */
+#define MCU_MISC_MCU1_LOG3_OFFSET      (0x118)
+#define MCU_MISC_STS_MCU1_MSTATUS      MCU_MISC_STS_MCU1_MSTATUS
+#define MCU_MISC_STS_MCU1_MSTATUS_POS  (0U)
+#define MCU_MISC_STS_MCU1_MSTATUS_LEN  (32U)
+#define MCU_MISC_STS_MCU1_MSTATUS_MSK  (((1U << MCU_MISC_STS_MCU1_MSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MSTATUS_POS)
+#define MCU_MISC_STS_MCU1_MSTATUS_UMSK (~(((1U << MCU_MISC_STS_MCU1_MSTATUS_LEN) - 1) << MCU_MISC_STS_MCU1_MSTATUS_POS))
+
+/* 0x11C : mcu1_log4 */
+#define MCU_MISC_MCU1_LOG4_OFFSET (0x11C)
+#define MCU_MISC_STS_MCU1_SP      MCU_MISC_STS_MCU1_SP
+#define MCU_MISC_STS_MCU1_SP_POS  (0U)
+#define MCU_MISC_STS_MCU1_SP_LEN  (1U)
+#define MCU_MISC_STS_MCU1_SP_MSK  (((1U << MCU_MISC_STS_MCU1_SP_LEN) - 1) << MCU_MISC_STS_MCU1_SP_POS)
+#define MCU_MISC_STS_MCU1_SP_UMSK (~(((1U << MCU_MISC_STS_MCU1_SP_LEN) - 1) << MCU_MISC_STS_MCU1_SP_POS))
+#define MCU_MISC_STS_MCU1_PC      MCU_MISC_STS_MCU1_PC
+#define MCU_MISC_STS_MCU1_PC_POS  (1U)
+#define MCU_MISC_STS_MCU1_PC_LEN  (31U)
+#define MCU_MISC_STS_MCU1_PC_MSK  (((1U << MCU_MISC_STS_MCU1_PC_LEN) - 1) << MCU_MISC_STS_MCU1_PC_POS)
+#define MCU_MISC_STS_MCU1_PC_UMSK (~(((1U << MCU_MISC_STS_MCU1_PC_LEN) - 1) << MCU_MISC_STS_MCU1_PC_POS))
+
+/* 0x120 : mcu1_log5 */
+#define MCU_MISC_MCU1_LOG5_OFFSET        (0x120)
+#define MCU_MISC_STS_MCU1_LOCKUP         MCU_MISC_STS_MCU1_LOCKUP
+#define MCU_MISC_STS_MCU1_LOCKUP_POS     (24U)
+#define MCU_MISC_STS_MCU1_LOCKUP_LEN     (1U)
+#define MCU_MISC_STS_MCU1_LOCKUP_MSK     (((1U << MCU_MISC_STS_MCU1_LOCKUP_LEN) - 1) << MCU_MISC_STS_MCU1_LOCKUP_POS)
+#define MCU_MISC_STS_MCU1_LOCKUP_UMSK    (~(((1U << MCU_MISC_STS_MCU1_LOCKUP_LEN) - 1) << MCU_MISC_STS_MCU1_LOCKUP_POS))
+#define MCU_MISC_STS_MCU1_HALTED         MCU_MISC_STS_MCU1_HALTED
+#define MCU_MISC_STS_MCU1_HALTED_POS     (25U)
+#define MCU_MISC_STS_MCU1_HALTED_LEN     (1U)
+#define MCU_MISC_STS_MCU1_HALTED_MSK     (((1U << MCU_MISC_STS_MCU1_HALTED_LEN) - 1) << MCU_MISC_STS_MCU1_HALTED_POS)
+#define MCU_MISC_STS_MCU1_HALTED_UMSK    (~(((1U << MCU_MISC_STS_MCU1_HALTED_LEN) - 1) << MCU_MISC_STS_MCU1_HALTED_POS))
+#define MCU_MISC_MCU1_NDM_RSTN_REQ       MCU_MISC_MCU1_NDM_RSTN_REQ
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_POS   (28U)
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_LEN   (1U)
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_MSK   (((1U << MCU_MISC_MCU1_NDM_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_REQ_POS)
+#define MCU_MISC_MCU1_NDM_RSTN_REQ_UMSK  (~(((1U << MCU_MISC_MCU1_NDM_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_NDM_RSTN_REQ_POS))
+#define MCU_MISC_MCU1_HART_RSTN_REQ      MCU_MISC_MCU1_HART_RSTN_REQ
+#define MCU_MISC_MCU1_HART_RSTN_REQ_POS  (29U)
+#define MCU_MISC_MCU1_HART_RSTN_REQ_LEN  (1U)
+#define MCU_MISC_MCU1_HART_RSTN_REQ_MSK  (((1U << MCU_MISC_MCU1_HART_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_REQ_POS)
+#define MCU_MISC_MCU1_HART_RSTN_REQ_UMSK (~(((1U << MCU_MISC_MCU1_HART_RSTN_REQ_LEN) - 1) << MCU_MISC_MCU1_HART_RSTN_REQ_POS))
+
+/* 0x200 : cpu_mbist */
+#define MCU_MISC_CPU_MBIST_OFFSET         (0x200)
+#define MCU_MISC_CPU_MBIST_MODE           MCU_MISC_CPU_MBIST_MODE
+#define MCU_MISC_CPU_MBIST_MODE_POS       (0U)
+#define MCU_MISC_CPU_MBIST_MODE_LEN       (1U)
+#define MCU_MISC_CPU_MBIST_MODE_MSK       (((1U << MCU_MISC_CPU_MBIST_MODE_LEN) - 1) << MCU_MISC_CPU_MBIST_MODE_POS)
+#define MCU_MISC_CPU_MBIST_MODE_UMSK      (~(((1U << MCU_MISC_CPU_MBIST_MODE_LEN) - 1) << MCU_MISC_CPU_MBIST_MODE_POS))
+#define MCU_MISC_IROM_MBIST_MODE          MCU_MISC_IROM_MBIST_MODE
+#define MCU_MISC_IROM_MBIST_MODE_POS      (1U)
+#define MCU_MISC_IROM_MBIST_MODE_LEN      (1U)
+#define MCU_MISC_IROM_MBIST_MODE_MSK      (((1U << MCU_MISC_IROM_MBIST_MODE_LEN) - 1) << MCU_MISC_IROM_MBIST_MODE_POS)
+#define MCU_MISC_IROM_MBIST_MODE_UMSK     (~(((1U << MCU_MISC_IROM_MBIST_MODE_LEN) - 1) << MCU_MISC_IROM_MBIST_MODE_POS))
+#define MCU_MISC_REG_CPU_MBIST_RST_N      MCU_MISC_REG_CPU_MBIST_RST_N
+#define MCU_MISC_REG_CPU_MBIST_RST_N_POS  (8U)
+#define MCU_MISC_REG_CPU_MBIST_RST_N_LEN  (1U)
+#define MCU_MISC_REG_CPU_MBIST_RST_N_MSK  (((1U << MCU_MISC_REG_CPU_MBIST_RST_N_LEN) - 1) << MCU_MISC_REG_CPU_MBIST_RST_N_POS)
+#define MCU_MISC_REG_CPU_MBIST_RST_N_UMSK (~(((1U << MCU_MISC_REG_CPU_MBIST_RST_N_LEN) - 1) << MCU_MISC_REG_CPU_MBIST_RST_N_POS))
+#define MCU_MISC_CPU_MBIST_DONE           MCU_MISC_CPU_MBIST_DONE
+#define MCU_MISC_CPU_MBIST_DONE_POS       (16U)
+#define MCU_MISC_CPU_MBIST_DONE_LEN       (6U)
+#define MCU_MISC_CPU_MBIST_DONE_MSK       (((1U << MCU_MISC_CPU_MBIST_DONE_LEN) - 1) << MCU_MISC_CPU_MBIST_DONE_POS)
+#define MCU_MISC_CPU_MBIST_DONE_UMSK      (~(((1U << MCU_MISC_CPU_MBIST_DONE_LEN) - 1) << MCU_MISC_CPU_MBIST_DONE_POS))
+#define MCU_MISC_IROM_MBIST_DONE          MCU_MISC_IROM_MBIST_DONE
+#define MCU_MISC_IROM_MBIST_DONE_POS      (22U)
+#define MCU_MISC_IROM_MBIST_DONE_LEN      (1U)
+#define MCU_MISC_IROM_MBIST_DONE_MSK      (((1U << MCU_MISC_IROM_MBIST_DONE_LEN) - 1) << MCU_MISC_IROM_MBIST_DONE_POS)
+#define MCU_MISC_IROM_MBIST_DONE_UMSK     (~(((1U << MCU_MISC_IROM_MBIST_DONE_LEN) - 1) << MCU_MISC_IROM_MBIST_DONE_POS))
+#define MCU_MISC_CPU_MBIST_FAIL           MCU_MISC_CPU_MBIST_FAIL
+#define MCU_MISC_CPU_MBIST_FAIL_POS       (24U)
+#define MCU_MISC_CPU_MBIST_FAIL_LEN       (6U)
+#define MCU_MISC_CPU_MBIST_FAIL_MSK       (((1U << MCU_MISC_CPU_MBIST_FAIL_LEN) - 1) << MCU_MISC_CPU_MBIST_FAIL_POS)
+#define MCU_MISC_CPU_MBIST_FAIL_UMSK      (~(((1U << MCU_MISC_CPU_MBIST_FAIL_LEN) - 1) << MCU_MISC_CPU_MBIST_FAIL_POS))
+#define MCU_MISC_IROM_MBIST_FAIL          MCU_MISC_IROM_MBIST_FAIL
+#define MCU_MISC_IROM_MBIST_FAIL_POS      (30U)
+#define MCU_MISC_IROM_MBIST_FAIL_LEN      (1U)
+#define MCU_MISC_IROM_MBIST_FAIL_MSK      (((1U << MCU_MISC_IROM_MBIST_FAIL_LEN) - 1) << MCU_MISC_IROM_MBIST_FAIL_POS)
+#define MCU_MISC_IROM_MBIST_FAIL_UMSK     (~(((1U << MCU_MISC_IROM_MBIST_FAIL_LEN) - 1) << MCU_MISC_IROM_MBIST_FAIL_POS))
+
+/* 0x208 : irom1_misr_dataout_0 */
+#define MCU_MISC_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
+#define MCU_MISC_IROM_MISR_DATAOUT_0         MCU_MISC_IROM_MISR_DATAOUT_0
+#define MCU_MISC_IROM_MISR_DATAOUT_0_POS     (0U)
+#define MCU_MISC_IROM_MISR_DATAOUT_0_LEN     (32U)
+#define MCU_MISC_IROM_MISR_DATAOUT_0_MSK     (((1U << MCU_MISC_IROM_MISR_DATAOUT_0_LEN) - 1) << MCU_MISC_IROM_MISR_DATAOUT_0_POS)
+#define MCU_MISC_IROM_MISR_DATAOUT_0_UMSK    (~(((1U << MCU_MISC_IROM_MISR_DATAOUT_0_LEN) - 1) << MCU_MISC_IROM_MISR_DATAOUT_0_POS))
+
+/* 0x20C : irom1_misr_dataout_1 */
+#define MCU_MISC_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
+#define MCU_MISC_IROM_MISR_DATAOUT_1         MCU_MISC_IROM_MISR_DATAOUT_1
+#define MCU_MISC_IROM_MISR_DATAOUT_1_POS     (0U)
+#define MCU_MISC_IROM_MISR_DATAOUT_1_LEN     (32U)
+#define MCU_MISC_IROM_MISR_DATAOUT_1_MSK     (((1U << MCU_MISC_IROM_MISR_DATAOUT_1_LEN) - 1) << MCU_MISC_IROM_MISR_DATAOUT_1_POS)
+#define MCU_MISC_IROM_MISR_DATAOUT_1_UMSK    (~(((1U << MCU_MISC_IROM_MISR_DATAOUT_1_LEN) - 1) << MCU_MISC_IROM_MISR_DATAOUT_1_POS))
+
+struct mcu_misc_reg {
+    /* 0x0 : mcu_bus_cfg0 */
+    union {
+        struct {
+            uint32_t reg_mcu_infra_timeout_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_mcu_infra_timeout_clr : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_15             : 14; /* [15: 2],       rsvd,        0x0 */
+            uint32_t sts_mcu_infra_timeout     : 1;  /* [   16],          r,        0x0 */
+            uint32_t reserved_17_31            : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu_bus_cfg0;
+
+    /* 0x4 : mcu_bus_cfg1 */
+    union {
+        struct {
+            uint32_t reg_mcu1_hqos          : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_mcu1_awqos         : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_mcu1_arqos         : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_6           : 4;  /* [ 6: 3],       rsvd,        0x0 */
+            uint32_t reg_x_wthre_mcu2ext    : 2;  /* [ 8: 7],        r/w,        0x0 */
+            uint32_t reserved_9_15          : 7;  /* [15: 9],       rsvd,        0x0 */
+            uint32_t reg_mcu_infra_arb_mode : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31         : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu_bus_cfg1;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[12];
+
+    /* 0x14 : mcu_e907_rtc */
+    union {
+        struct {
+            uint32_t reg_mcu_rtc_div     : 10; /* [ 9: 0],        r/w,        0xa */
+            uint32_t reserved_10_28      : 19; /* [28:10],       rsvd,        0x0 */
+            uint32_t reg_mcu_rtc_clk_sel : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t reg_mcu_rtc_rst     : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t reg_mcu_rtc_en      : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } mcu_e907_rtc;
+
+    /* 0x18  reserved */
+    uint8_t RESERVED0x18[232];
+
+    /* 0x100 : mcu_cfg1 */
+    union {
+        struct {
+            uint32_t reg_mcu1_dfs_req  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1        : 1;  /* [    1],       rsvd,        0x0 */
+            uint32_t sts_mcu1_dfs_ack  : 1;  /* [    2],          r,        0x0 */
+            uint32_t reserved_3        : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t reg_mcu1_srst_en  : 2;  /* [ 5: 4],        r/w,        0x3 */
+            uint32_t reserved_6_9      : 4;  /* [ 9: 6],       rsvd,        0x0 */
+            uint32_t sts_mcu1_lpmd_b   : 2;  /* [11:10],          r,        0x0 */
+            uint32_t reserved_12_15    : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t MCU1_WFI_FORCE    : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_27    : 11; /* [27:17],       rsvd,        0x0 */
+            uint32_t mcu1_ndm_rstn_en  : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t mcu1_hart_rstn_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31    : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu_cfg1;
+
+    /* 0x104  reserved */
+    uint8_t RESERVED0x104[12];
+
+    /* 0x110 : mcu1_log1 */
+    union {
+        struct {
+            uint32_t sts_mcu1_mcause : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu1_log1;
+
+    /* 0x114 : mcu1_log2 */
+    union {
+        struct {
+            uint32_t sts_mcu1_mintstatus : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu1_log2;
+
+    /* 0x118 : mcu1_log3 */
+    union {
+        struct {
+            uint32_t sts_mcu1_mstatus : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu1_log3;
+
+    /* 0x11C : mcu1_log4 */
+    union {
+        struct {
+            uint32_t sts_mcu1_sp : 1;  /* [    0],          r,        0x0 */
+            uint32_t sts_mcu1_pc : 31; /* [31: 1],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu1_log4;
+
+    /* 0x120 : mcu1_log5 */
+    union {
+        struct {
+            uint32_t reserved_0_23      : 24; /* [23: 0],       rsvd,        0x0 */
+            uint32_t sts_mcu1_lockup    : 1;  /* [   24],          r,        0x0 */
+            uint32_t sts_mcu1_halted    : 1;  /* [   25],          r,        0x0 */
+            uint32_t reserved_26_27     : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t mcu1_ndm_rstn_req  : 1;  /* [   28],          r,        0x0 */
+            uint32_t mcu1_hart_rstn_req : 1;  /* [   29],          r,        0x0 */
+            uint32_t reserved_30_31     : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mcu1_log5;
+
+    /* 0x124  reserved */
+    uint8_t RESERVED0x124[220];
+
+    /* 0x200 : cpu_mbist */
+    union {
+        struct {
+            uint32_t cpu_mbist_mode      : 1; /* [    0],        r/w,        0x0 */
+            uint32_t irom_mbist_mode     : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t reg_cpu_mbist_rst_n : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_15       : 7; /* [15: 9],       rsvd,        0x0 */
+            uint32_t cpu_mbist_done      : 6; /* [21:16],          r,        0x0 */
+            uint32_t irom_mbist_done     : 1; /* [   22],          r,        0x0 */
+            uint32_t reserved_23         : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t cpu_mbist_fail      : 6; /* [29:24],          r,        0x0 */
+            uint32_t irom_mbist_fail     : 1; /* [   30],          r,        0x0 */
+            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cpu_mbist;
+
+    /* 0x204  reserved */
+    uint8_t RESERVED0x204[4];
+
+    /* 0x208 : irom1_misr_dataout_0 */
+    union {
+        struct {
+            uint32_t irom_misr_dataout_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_0;
+
+    /* 0x20C : irom1_misr_dataout_1 */
+    union {
+        struct {
+            uint32_t irom_misr_dataout_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_1;
+};
+
+typedef volatile struct mcu_misc_reg mcu_misc_reg_t;
+
+#endif /* __MCU_MISC_REG_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mm_glb_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mm_glb_reg.h
old mode 100644
new mode 100755
similarity index 92%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mm_glb_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mm_glb_reg.h
index 29ab241023..46f38e5bd6
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mm_glb_reg.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mm_glb_reg.h
@@ -36,7 +36,7 @@
 #ifndef __MM_GLB_REG_H__
 #define __MM_GLB_REG_H__
 
-#include "bl808.h"
+#include "bl616.h"
 
 /* 0x0 : mm_clk_ctrl_cpu */
 #define MM_GLB_MM_CLK_CTRL_CPU_OFFSET        (0x0)
@@ -159,23 +159,23 @@
 #define MM_GLB_REG_BCLK1X_DIV_MSK      (((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS)
 #define MM_GLB_REG_BCLK1X_DIV_UMSK     (~(((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS))
 
-/* 0x8 : dsp2_dp_clk */
-#define MM_GLB_DSP2_DP_CLK_OFFSET       (0x8)
-#define MM_GLB_REG_DSP2_CLK_DIV_EN      MM_GLB_REG_DSP2_CLK_DIV_EN
-#define MM_GLB_REG_DSP2_CLK_DIV_EN_POS  (0U)
-#define MM_GLB_REG_DSP2_CLK_DIV_EN_LEN  (1U)
-#define MM_GLB_REG_DSP2_CLK_DIV_EN_MSK  (((1U << MM_GLB_REG_DSP2_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DSP2_CLK_DIV_EN_POS)
-#define MM_GLB_REG_DSP2_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_DSP2_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DSP2_CLK_DIV_EN_POS))
-#define MM_GLB_REG_DSP2_CLK_SEL         MM_GLB_REG_DSP2_CLK_SEL
-#define MM_GLB_REG_DSP2_CLK_SEL_POS     (1U)
-#define MM_GLB_REG_DSP2_CLK_SEL_LEN     (2U)
-#define MM_GLB_REG_DSP2_CLK_SEL_MSK     (((1U << MM_GLB_REG_DSP2_CLK_SEL_LEN) - 1) << MM_GLB_REG_DSP2_CLK_SEL_POS)
-#define MM_GLB_REG_DSP2_CLK_SEL_UMSK    (~(((1U << MM_GLB_REG_DSP2_CLK_SEL_LEN) - 1) << MM_GLB_REG_DSP2_CLK_SEL_POS))
-#define MM_GLB_REG_DSP2_CLK_DIV         MM_GLB_REG_DSP2_CLK_DIV
-#define MM_GLB_REG_DSP2_CLK_DIV_POS     (8U)
-#define MM_GLB_REG_DSP2_CLK_DIV_LEN     (8U)
-#define MM_GLB_REG_DSP2_CLK_DIV_MSK     (((1U << MM_GLB_REG_DSP2_CLK_DIV_LEN) - 1) << MM_GLB_REG_DSP2_CLK_DIV_POS)
-#define MM_GLB_REG_DSP2_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_DSP2_CLK_DIV_LEN) - 1) << MM_GLB_REG_DSP2_CLK_DIV_POS))
+/* 0x8 : isp_dp_clk */
+#define MM_GLB_ISP_DP_CLK_OFFSET       (0x8)
+#define MM_GLB_REG_ISP_CLK_DIV_EN      MM_GLB_REG_ISP_CLK_DIV_EN
+#define MM_GLB_REG_ISP_CLK_DIV_EN_POS  (0U)
+#define MM_GLB_REG_ISP_CLK_DIV_EN_LEN  (1U)
+#define MM_GLB_REG_ISP_CLK_DIV_EN_MSK  (((1U << MM_GLB_REG_ISP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_ISP_CLK_DIV_EN_POS)
+#define MM_GLB_REG_ISP_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_ISP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_ISP_CLK_DIV_EN_POS))
+#define MM_GLB_REG_ISP_CLK_SEL         MM_GLB_REG_ISP_CLK_SEL
+#define MM_GLB_REG_ISP_CLK_SEL_POS     (1U)
+#define MM_GLB_REG_ISP_CLK_SEL_LEN     (2U)
+#define MM_GLB_REG_ISP_CLK_SEL_MSK     (((1U << MM_GLB_REG_ISP_CLK_SEL_LEN) - 1) << MM_GLB_REG_ISP_CLK_SEL_POS)
+#define MM_GLB_REG_ISP_CLK_SEL_UMSK    (~(((1U << MM_GLB_REG_ISP_CLK_SEL_LEN) - 1) << MM_GLB_REG_ISP_CLK_SEL_POS))
+#define MM_GLB_REG_ISP_CLK_DIV         MM_GLB_REG_ISP_CLK_DIV
+#define MM_GLB_REG_ISP_CLK_DIV_POS     (8U)
+#define MM_GLB_REG_ISP_CLK_DIV_LEN     (8U)
+#define MM_GLB_REG_ISP_CLK_DIV_MSK     (((1U << MM_GLB_REG_ISP_CLK_DIV_LEN) - 1) << MM_GLB_REG_ISP_CLK_DIV_POS)
+#define MM_GLB_REG_ISP_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_ISP_CLK_DIV_LEN) - 1) << MM_GLB_REG_ISP_CLK_DIV_POS))
 #define MM_GLB_REG_DP_CLK_DIV_EN       MM_GLB_REG_DP_CLK_DIV_EN
 #define MM_GLB_REG_DP_CLK_DIV_EN_POS   (16U)
 #define MM_GLB_REG_DP_CLK_DIV_EN_LEN   (1U)
@@ -372,23 +372,23 @@
 #define MM_GLB_SWRST_PUHS_MSK          (((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS)
 #define MM_GLB_SWRST_PUHS_UMSK         (~(((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS))
 
-/* 0x48 : sw_reset_dsp2_sub */
-#define MM_GLB_SW_RESET_DSP2_SUB_OFFSET (0x48)
-#define MM_GLB_SWRST_DSP2_MISC          MM_GLB_SWRST_DSP2_MISC
-#define MM_GLB_SWRST_DSP2_MISC_POS      (0U)
-#define MM_GLB_SWRST_DSP2_MISC_LEN      (1U)
-#define MM_GLB_SWRST_DSP2_MISC_MSK      (((1U << MM_GLB_SWRST_DSP2_MISC_LEN) - 1) << MM_GLB_SWRST_DSP2_MISC_POS)
-#define MM_GLB_SWRST_DSP2_MISC_UMSK     (~(((1U << MM_GLB_SWRST_DSP2_MISC_LEN) - 1) << MM_GLB_SWRST_DSP2_MISC_POS))
-#define MM_GLB_SWRST_DSP2_MAIN          MM_GLB_SWRST_DSP2_MAIN
-#define MM_GLB_SWRST_DSP2_MAIN_POS      (1U)
-#define MM_GLB_SWRST_DSP2_MAIN_LEN      (1U)
-#define MM_GLB_SWRST_DSP2_MAIN_MSK      (((1U << MM_GLB_SWRST_DSP2_MAIN_LEN) - 1) << MM_GLB_SWRST_DSP2_MAIN_POS)
-#define MM_GLB_SWRST_DSP2_MAIN_UMSK     (~(((1U << MM_GLB_SWRST_DSP2_MAIN_LEN) - 1) << MM_GLB_SWRST_DSP2_MAIN_POS))
-#define MM_GLB_SWRST_DSP2_TSRC          MM_GLB_SWRST_DSP2_TSRC
-#define MM_GLB_SWRST_DSP2_TSRC_POS      (2U)
-#define MM_GLB_SWRST_DSP2_TSRC_LEN      (1U)
-#define MM_GLB_SWRST_DSP2_TSRC_MSK      (((1U << MM_GLB_SWRST_DSP2_TSRC_LEN) - 1) << MM_GLB_SWRST_DSP2_TSRC_POS)
-#define MM_GLB_SWRST_DSP2_TSRC_UMSK     (~(((1U << MM_GLB_SWRST_DSP2_TSRC_LEN) - 1) << MM_GLB_SWRST_DSP2_TSRC_POS))
+/* 0x48 : sw_reset_isp_sub */
+#define MM_GLB_SW_RESET_ISP_SUB_OFFSET (0x48)
+#define MM_GLB_SWRST_ISP_MISC          MM_GLB_SWRST_ISP_MISC
+#define MM_GLB_SWRST_ISP_MISC_POS      (0U)
+#define MM_GLB_SWRST_ISP_MISC_LEN      (1U)
+#define MM_GLB_SWRST_ISP_MISC_MSK      (((1U << MM_GLB_SWRST_ISP_MISC_LEN) - 1) << MM_GLB_SWRST_ISP_MISC_POS)
+#define MM_GLB_SWRST_ISP_MISC_UMSK     (~(((1U << MM_GLB_SWRST_ISP_MISC_LEN) - 1) << MM_GLB_SWRST_ISP_MISC_POS))
+#define MM_GLB_SWRST_ISP_MAIN          MM_GLB_SWRST_ISP_MAIN
+#define MM_GLB_SWRST_ISP_MAIN_POS      (1U)
+#define MM_GLB_SWRST_ISP_MAIN_LEN      (1U)
+#define MM_GLB_SWRST_ISP_MAIN_MSK      (((1U << MM_GLB_SWRST_ISP_MAIN_LEN) - 1) << MM_GLB_SWRST_ISP_MAIN_POS)
+#define MM_GLB_SWRST_ISP_MAIN_UMSK     (~(((1U << MM_GLB_SWRST_ISP_MAIN_LEN) - 1) << MM_GLB_SWRST_ISP_MAIN_POS))
+#define MM_GLB_SWRST_ISP_TSRC          MM_GLB_SWRST_ISP_TSRC
+#define MM_GLB_SWRST_ISP_TSRC_POS      (2U)
+#define MM_GLB_SWRST_ISP_TSRC_LEN      (1U)
+#define MM_GLB_SWRST_ISP_TSRC_MSK      (((1U << MM_GLB_SWRST_ISP_TSRC_LEN) - 1) << MM_GLB_SWRST_ISP_TSRC_POS)
+#define MM_GLB_SWRST_ISP_TSRC_UMSK     (~(((1U << MM_GLB_SWRST_ISP_TSRC_LEN) - 1) << MM_GLB_SWRST_ISP_TSRC_POS))
 #define MM_GLB_SWRST_DP_TSRC           MM_GLB_SWRST_DP_TSRC
 #define MM_GLB_SWRST_DP_TSRC_POS       (3U)
 #define MM_GLB_SWRST_DP_TSRC_LEN       (1U)
@@ -424,11 +424,11 @@
 #define MM_GLB_SWRST_MIPI_LEN          (1U)
 #define MM_GLB_SWRST_MIPI_MSK          (((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS)
 #define MM_GLB_SWRST_MIPI_UMSK         (~(((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS))
-#define MM_GLB_SWRST_DSP2_REG           MM_GLB_SWRST_DSP2_REG
-#define MM_GLB_SWRST_DSP2_REG_POS       (16U)
-#define MM_GLB_SWRST_DSP2_REG_LEN       (1U)
-#define MM_GLB_SWRST_DSP2_REG_MSK       (((1U << MM_GLB_SWRST_DSP2_REG_LEN) - 1) << MM_GLB_SWRST_DSP2_REG_POS)
-#define MM_GLB_SWRST_DSP2_REG_UMSK      (~(((1U << MM_GLB_SWRST_DSP2_REG_LEN) - 1) << MM_GLB_SWRST_DSP2_REG_POS))
+#define MM_GLB_SWRST_ISP_REG           MM_GLB_SWRST_ISP_REG
+#define MM_GLB_SWRST_ISP_REG_POS       (16U)
+#define MM_GLB_SWRST_ISP_REG_LEN       (1U)
+#define MM_GLB_SWRST_ISP_REG_MSK       (((1U << MM_GLB_SWRST_ISP_REG_LEN) - 1) << MM_GLB_SWRST_ISP_REG_POS)
+#define MM_GLB_SWRST_ISP_REG_UMSK      (~(((1U << MM_GLB_SWRST_ISP_REG_LEN) - 1) << MM_GLB_SWRST_ISP_REG_POS))
 #define MM_GLB_SWRST_DVP2BUSE          MM_GLB_SWRST_DVP2BUSE
 #define MM_GLB_SWRST_DVP2BUSE_POS      (17U)
 #define MM_GLB_SWRST_DVP2BUSE_LEN      (1U)
@@ -562,13 +562,13 @@ struct mm_glb_reg {
         uint32_t WORD;
     } mm_clk_cpu;
 
-    /* 0x8 : dsp2_dp_clk */
+    /* 0x8 : isp_dp_clk */
     union {
         struct {
-            uint32_t reg_dsp2_clk_div_en : 1; /* [    0],        r/w,        0x1 */
-            uint32_t reg_dsp2_clk_sel    : 2; /* [ 2: 1],        r/w,        0x0 */
+            uint32_t reg_isp_clk_div_en : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_isp_clk_sel    : 2; /* [ 2: 1],        r/w,        0x0 */
             uint32_t reserved_3_7       : 5; /* [ 7: 3],       rsvd,        0x0 */
-            uint32_t reg_dsp2_clk_div    : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_isp_clk_div    : 8; /* [15: 8],        r/w,        0x0 */
             uint32_t reg_dp_clk_div_en  : 1; /* [   16],        r/w,        0x1 */
             uint32_t reg_dp_clk_sel     : 1; /* [   17],        r/w,        0x0 */
             uint32_t reserved_18_19     : 2; /* [19:18],       rsvd,        0x0 */
@@ -576,7 +576,7 @@ struct mm_glb_reg {
             uint32_t reserved_24_31     : 8; /* [31:24],       rsvd,        0x0 */
         } BF;
         uint32_t WORD;
-    } dsp2_dp_clk;
+    } isp_dp_clk;
 
     /* 0xC : codec_clk */
     union {
@@ -664,12 +664,12 @@ struct mm_glb_reg {
         uint32_t WORD;
     } sw_reset_mm_peri;
 
-    /* 0x48 : sw_reset_dsp2_sub */
+    /* 0x48 : sw_reset_isp_sub */
     union {
         struct {
-            uint32_t swrst_dsp2_misc  : 1;  /* [    0],        r/w,        0x0 */
-            uint32_t swrst_dsp2_main  : 1;  /* [    1],        r/w,        0x0 */
-            uint32_t swrst_dsp2_tsrc  : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t swrst_isp_misc  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t swrst_isp_main  : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t swrst_isp_tsrc  : 1;  /* [    2],        r/w,        0x0 */
             uint32_t swrst_dp_tsrc   : 1;  /* [    3],        r/w,        0x0 */
             uint32_t swrst_nr3d_ctrl : 1;  /* [    4],        r/w,        0x0 */
             uint32_t swrst_dvp2busA  : 1;  /* [    5],        r/w,        0x0 */
@@ -678,7 +678,7 @@ struct mm_glb_reg {
             uint32_t swrst_dvp2busD  : 1;  /* [    8],        r/w,        0x0 */
             uint32_t swrst_mipi      : 1;  /* [    9],        r/w,        0x0 */
             uint32_t reserved_10_15  : 6;  /* [15:10],       rsvd,        0x0 */
-            uint32_t swrst_dsp2_reg   : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t swrst_isp_reg   : 1;  /* [   16],        r/w,        0x0 */
             uint32_t swrst_dvp2busE  : 1;  /* [   17],        r/w,        0x0 */
             uint32_t swrst_dvp2busF  : 1;  /* [   18],        r/w,        0x0 */
             uint32_t swrst_dvp2busG  : 1;  /* [   19],        r/w,        0x0 */
@@ -686,7 +686,7 @@ struct mm_glb_reg {
             uint32_t reserved_21_31  : 11; /* [31:21],       rsvd,        0x0 */
         } BF;
         uint32_t WORD;
-    } sw_reset_dsp2_sub;
+    } sw_reset_isp_sub;
 
     /* 0x4C : sw_reset_codec_sub */
     union {
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mm_misc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mm_misc_reg.h
new file mode 100755
index 0000000000..412d31b3dc
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/mm_misc_reg.h
@@ -0,0 +1,243 @@
+/**
+  ******************************************************************************
+  * @file    mm_misc_reg.h
+  * @version V1.0
+  * @date    2021-11-13
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __MM_MISC_REG_H__
+#define __MM_MISC_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : config */
+#define MM_MISC_CONFIG_OFFSET          (0x0)
+#define MM_MISC_RG_DVPAS_ENABLE        MM_MISC_RG_DVPAS_ENABLE
+#define MM_MISC_RG_DVPAS_ENABLE_POS    (0U)
+#define MM_MISC_RG_DVPAS_ENABLE_LEN    (1U)
+#define MM_MISC_RG_DVPAS_ENABLE_MSK    (((1U << MM_MISC_RG_DVPAS_ENABLE_LEN) - 1) << MM_MISC_RG_DVPAS_ENABLE_POS)
+#define MM_MISC_RG_DVPAS_ENABLE_UMSK   (~(((1U << MM_MISC_RG_DVPAS_ENABLE_LEN) - 1) << MM_MISC_RG_DVPAS_ENABLE_POS))
+#define MM_MISC_RG_DVPAS_HS_INV        MM_MISC_RG_DVPAS_HS_INV
+#define MM_MISC_RG_DVPAS_HS_INV_POS    (1U)
+#define MM_MISC_RG_DVPAS_HS_INV_LEN    (1U)
+#define MM_MISC_RG_DVPAS_HS_INV_MSK    (((1U << MM_MISC_RG_DVPAS_HS_INV_LEN) - 1) << MM_MISC_RG_DVPAS_HS_INV_POS)
+#define MM_MISC_RG_DVPAS_HS_INV_UMSK   (~(((1U << MM_MISC_RG_DVPAS_HS_INV_LEN) - 1) << MM_MISC_RG_DVPAS_HS_INV_POS))
+#define MM_MISC_RG_DVPAS_VS_INV        MM_MISC_RG_DVPAS_VS_INV
+#define MM_MISC_RG_DVPAS_VS_INV_POS    (2U)
+#define MM_MISC_RG_DVPAS_VS_INV_LEN    (1U)
+#define MM_MISC_RG_DVPAS_VS_INV_MSK    (((1U << MM_MISC_RG_DVPAS_VS_INV_LEN) - 1) << MM_MISC_RG_DVPAS_VS_INV_POS)
+#define MM_MISC_RG_DVPAS_VS_INV_UMSK   (~(((1U << MM_MISC_RG_DVPAS_VS_INV_LEN) - 1) << MM_MISC_RG_DVPAS_VS_INV_POS))
+#define MM_MISC_RG_DVPAS_DA_ORDER      MM_MISC_RG_DVPAS_DA_ORDER
+#define MM_MISC_RG_DVPAS_DA_ORDER_POS  (3U)
+#define MM_MISC_RG_DVPAS_DA_ORDER_LEN  (1U)
+#define MM_MISC_RG_DVPAS_DA_ORDER_MSK  (((1U << MM_MISC_RG_DVPAS_DA_ORDER_LEN) - 1) << MM_MISC_RG_DVPAS_DA_ORDER_POS)
+#define MM_MISC_RG_DVPAS_DA_ORDER_UMSK (~(((1U << MM_MISC_RG_DVPAS_DA_ORDER_LEN) - 1) << MM_MISC_RG_DVPAS_DA_ORDER_POS))
+#define MM_MISC_RG_DVPAS_FIFO_TH       MM_MISC_RG_DVPAS_FIFO_TH
+#define MM_MISC_RG_DVPAS_FIFO_TH_POS   (16U)
+#define MM_MISC_RG_DVPAS_FIFO_TH_LEN   (11U)
+#define MM_MISC_RG_DVPAS_FIFO_TH_MSK   (((1U << MM_MISC_RG_DVPAS_FIFO_TH_LEN) - 1) << MM_MISC_RG_DVPAS_FIFO_TH_POS)
+#define MM_MISC_RG_DVPAS_FIFO_TH_UMSK  (~(((1U << MM_MISC_RG_DVPAS_FIFO_TH_LEN) - 1) << MM_MISC_RG_DVPAS_FIFO_TH_POS))
+
+/* 0x8 : dvp2bus_src_sel_1 */
+#define MM_MISC_DVP2BUS_SRC_SEL_1_OFFSET (0x8)
+#define MM_MISC_RG_D2X_DVP_SEL           MM_MISC_RG_D2X_DVP_SEL
+#define MM_MISC_RG_D2X_DVP_SEL_POS       (0U)
+#define MM_MISC_RG_D2X_DVP_SEL_LEN       (1U)
+#define MM_MISC_RG_D2X_DVP_SEL_MSK       (((1U << MM_MISC_RG_D2X_DVP_SEL_LEN) - 1) << MM_MISC_RG_D2X_DVP_SEL_POS)
+#define MM_MISC_RG_D2X_DVP_SEL_UMSK      (~(((1U << MM_MISC_RG_D2X_DVP_SEL_LEN) - 1) << MM_MISC_RG_D2X_DVP_SEL_POS))
+
+/* 0xC : snsr_ctrl */
+#define MM_MISC_SNSR_CTRL_OFFSET  (0xC)
+#define MM_MISC_RG_SNSR_RST       MM_MISC_RG_SNSR_RST
+#define MM_MISC_RG_SNSR_RST_POS   (0U)
+#define MM_MISC_RG_SNSR_RST_LEN   (1U)
+#define MM_MISC_RG_SNSR_RST_MSK   (((1U << MM_MISC_RG_SNSR_RST_LEN) - 1) << MM_MISC_RG_SNSR_RST_POS)
+#define MM_MISC_RG_SNSR_RST_UMSK  (~(((1U << MM_MISC_RG_SNSR_RST_LEN) - 1) << MM_MISC_RG_SNSR_RST_POS))
+#define MM_MISC_RG_SNSR_PWDN      MM_MISC_RG_SNSR_PWDN
+#define MM_MISC_RG_SNSR_PWDN_POS  (1U)
+#define MM_MISC_RG_SNSR_PWDN_LEN  (1U)
+#define MM_MISC_RG_SNSR_PWDN_MSK  (((1U << MM_MISC_RG_SNSR_PWDN_LEN) - 1) << MM_MISC_RG_SNSR_PWDN_POS)
+#define MM_MISC_RG_SNSR_PWDN_UMSK (~(((1U << MM_MISC_RG_SNSR_PWDN_LEN) - 1) << MM_MISC_RG_SNSR_PWDN_POS))
+
+/* 0x10 : emi_misc */
+#define MM_MISC_EMI_MISC_OFFSET       (0x10)
+#define MM_MISC_REG_X_WTHRE_PB        MM_MISC_REG_X_WTHRE_PB
+#define MM_MISC_REG_X_WTHRE_PB_POS    (0U)
+#define MM_MISC_REG_X_WTHRE_PB_LEN    (2U)
+#define MM_MISC_REG_X_WTHRE_PB_MSK    (((1U << MM_MISC_REG_X_WTHRE_PB_LEN) - 1) << MM_MISC_REG_X_WTHRE_PB_POS)
+#define MM_MISC_REG_X_WTHRE_PB_UMSK   (~(((1U << MM_MISC_REG_X_WTHRE_PB_LEN) - 1) << MM_MISC_REG_X_WTHRE_PB_POS))
+#define MM_MISC_REG_SF_HARB_MODE      MM_MISC_REG_SF_HARB_MODE
+#define MM_MISC_REG_SF_HARB_MODE_POS  (4U)
+#define MM_MISC_REG_SF_HARB_MODE_LEN  (1U)
+#define MM_MISC_REG_SF_HARB_MODE_MSK  (((1U << MM_MISC_REG_SF_HARB_MODE_LEN) - 1) << MM_MISC_REG_SF_HARB_MODE_POS)
+#define MM_MISC_REG_SF_HARB_MODE_UMSK (~(((1U << MM_MISC_REG_SF_HARB_MODE_LEN) - 1) << MM_MISC_REG_SF_HARB_MODE_POS))
+
+/* 0x14 : isp_id_yuv */
+#define MM_MISC_ISP_ID_YUV_OFFSET           (0x14)
+#define MM_MISC_REG_YUV_IDGEN_RST           MM_MISC_REG_YUV_IDGEN_RST
+#define MM_MISC_REG_YUV_IDGEN_RST_POS       (0U)
+#define MM_MISC_REG_YUV_IDGEN_RST_LEN       (1U)
+#define MM_MISC_REG_YUV_IDGEN_RST_MSK       (((1U << MM_MISC_REG_YUV_IDGEN_RST_LEN) - 1) << MM_MISC_REG_YUV_IDGEN_RST_POS)
+#define MM_MISC_REG_YUV_IDGEN_RST_UMSK      (~(((1U << MM_MISC_REG_YUV_IDGEN_RST_LEN) - 1) << MM_MISC_REG_YUV_IDGEN_RST_POS))
+#define MM_MISC_REG_YUV_IDGEN_EDGE          MM_MISC_REG_YUV_IDGEN_EDGE
+#define MM_MISC_REG_YUV_IDGEN_EDGE_POS      (1U)
+#define MM_MISC_REG_YUV_IDGEN_EDGE_LEN      (1U)
+#define MM_MISC_REG_YUV_IDGEN_EDGE_MSK      (((1U << MM_MISC_REG_YUV_IDGEN_EDGE_LEN) - 1) << MM_MISC_REG_YUV_IDGEN_EDGE_POS)
+#define MM_MISC_REG_YUV_IDGEN_EDGE_UMSK     (~(((1U << MM_MISC_REG_YUV_IDGEN_EDGE_LEN) - 1) << MM_MISC_REG_YUV_IDGEN_EDGE_POS))
+#define MM_MISC_REG_YUV_IDGEN_CNT_INCR      MM_MISC_REG_YUV_IDGEN_CNT_INCR
+#define MM_MISC_REG_YUV_IDGEN_CNT_INCR_POS  (16U)
+#define MM_MISC_REG_YUV_IDGEN_CNT_INCR_LEN  (16U)
+#define MM_MISC_REG_YUV_IDGEN_CNT_INCR_MSK  (((1U << MM_MISC_REG_YUV_IDGEN_CNT_INCR_LEN) - 1) << MM_MISC_REG_YUV_IDGEN_CNT_INCR_POS)
+#define MM_MISC_REG_YUV_IDGEN_CNT_INCR_UMSK (~(((1U << MM_MISC_REG_YUV_IDGEN_CNT_INCR_LEN) - 1) << MM_MISC_REG_YUV_IDGEN_CNT_INCR_POS))
+
+/* 0x100 : mm_mbist_ctrl */
+#define MM_MISC_MM_MBIST_CTRL_OFFSET (0x100)
+#define MM_MISC_MBIST_MODE           MM_MISC_MBIST_MODE
+#define MM_MISC_MBIST_MODE_POS       (0U)
+#define MM_MISC_MBIST_MODE_LEN       (1U)
+#define MM_MISC_MBIST_MODE_MSK       (((1U << MM_MISC_MBIST_MODE_LEN) - 1) << MM_MISC_MBIST_MODE_POS)
+#define MM_MISC_MBIST_MODE_UMSK      (~(((1U << MM_MISC_MBIST_MODE_LEN) - 1) << MM_MISC_MBIST_MODE_POS))
+#define MM_MISC_REG_MBIST_RST_N      MM_MISC_REG_MBIST_RST_N
+#define MM_MISC_REG_MBIST_RST_N_POS  (1U)
+#define MM_MISC_REG_MBIST_RST_N_LEN  (1U)
+#define MM_MISC_REG_MBIST_RST_N_MSK  (((1U << MM_MISC_REG_MBIST_RST_N_LEN) - 1) << MM_MISC_REG_MBIST_RST_N_POS)
+#define MM_MISC_REG_MBIST_RST_N_UMSK (~(((1U << MM_MISC_REG_MBIST_RST_N_LEN) - 1) << MM_MISC_REG_MBIST_RST_N_POS))
+#define MM_MISC_NAP                  MM_MISC_NAP
+#define MM_MISC_NAP_POS              (4U)
+#define MM_MISC_NAP_LEN              (1U)
+#define MM_MISC_NAP_MSK              (((1U << MM_MISC_NAP_LEN) - 1) << MM_MISC_NAP_POS)
+#define MM_MISC_NAP_UMSK             (~(((1U << MM_MISC_NAP_LEN) - 1) << MM_MISC_NAP_POS))
+#define MM_MISC_DVSE                 MM_MISC_DVSE
+#define MM_MISC_DVSE_POS             (5U)
+#define MM_MISC_DVSE_LEN             (1U)
+#define MM_MISC_DVSE_MSK             (((1U << MM_MISC_DVSE_LEN) - 1) << MM_MISC_DVSE_POS)
+#define MM_MISC_DVSE_UMSK            (~(((1U << MM_MISC_DVSE_LEN) - 1) << MM_MISC_DVSE_POS))
+#define MM_MISC_DVS                  MM_MISC_DVS
+#define MM_MISC_DVS_POS              (8U)
+#define MM_MISC_DVS_LEN              (4U)
+#define MM_MISC_DVS_MSK              (((1U << MM_MISC_DVS_LEN) - 1) << MM_MISC_DVS_POS)
+#define MM_MISC_DVS_UMSK             (~(((1U << MM_MISC_DVS_LEN) - 1) << MM_MISC_DVS_POS))
+#define MM_MISC_MM_MBIST_DONE        MM_MISC_MM_MBIST_DONE
+#define MM_MISC_MM_MBIST_DONE_POS    (16U)
+#define MM_MISC_MM_MBIST_DONE_LEN    (7U)
+#define MM_MISC_MM_MBIST_DONE_MSK    (((1U << MM_MISC_MM_MBIST_DONE_LEN) - 1) << MM_MISC_MM_MBIST_DONE_POS)
+#define MM_MISC_MM_MBIST_DONE_UMSK   (~(((1U << MM_MISC_MM_MBIST_DONE_LEN) - 1) << MM_MISC_MM_MBIST_DONE_POS))
+#define MM_MISC_MM_MBIST_FAIL        MM_MISC_MM_MBIST_FAIL
+#define MM_MISC_MM_MBIST_FAIL_POS    (24U)
+#define MM_MISC_MM_MBIST_FAIL_LEN    (7U)
+#define MM_MISC_MM_MBIST_FAIL_MSK    (((1U << MM_MISC_MM_MBIST_FAIL_LEN) - 1) << MM_MISC_MM_MBIST_FAIL_POS)
+#define MM_MISC_MM_MBIST_FAIL_UMSK   (~(((1U << MM_MISC_MM_MBIST_FAIL_LEN) - 1) << MM_MISC_MM_MBIST_FAIL_POS))
+
+struct mm_misc_reg {
+    /* 0x0 : config */
+    union {
+        struct {
+            uint32_t rg_dvpas_enable   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t rg_dvpas_hs_inv   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rg_dvpas_vs_inv   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t rg_dvpas_da_order : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_15     : 12; /* [15: 4],       rsvd,        0x0 */
+            uint32_t rg_dvpas_fifo_th  : 11; /* [26:16],        r/w,        0x0 */
+            uint32_t reserved_27_31    : 5;  /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } config;
+
+    /* 0x4  reserved */
+    uint8_t RESERVED0x4[4];
+
+    /* 0x8 : dvp2bus_src_sel_1 */
+    union {
+        struct {
+            uint32_t rg_d2x_dvp_sel : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31  : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dvp2bus_src_sel_1;
+
+    /* 0xC : snsr_ctrl */
+    union {
+        struct {
+            uint32_t rg_snsr_rst   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t rg_snsr_pwdn  : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } snsr_ctrl;
+
+    /* 0x10 : emi_misc */
+    union {
+        struct {
+            uint32_t reg_x_wthre_pB   : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_3     : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t reg_sf_harb_mode : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_31    : 27; /* [31: 5],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } emi_misc;
+
+    /* 0x14 : isp_id_yuv */
+    union {
+        struct {
+            uint32_t reg_yuv_idgen_rst      : 1;  /* [    0],        w1p,        0x0 */
+            uint32_t reg_yuv_idgen_edge     : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_15          : 14; /* [15: 2],       rsvd,        0x0 */
+            uint32_t reg_yuv_idgen_cnt_incr : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } isp_id_yuv;
+
+    /* 0x18  reserved */
+    uint8_t RESERVED0x18[232];
+
+    /* 0x100 : mm_mbist_ctrl */
+    union {
+        struct {
+            uint32_t mbist_mode      : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_mbist_rst_n : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_3    : 2; /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t NAP             : 1; /* [    4],        r/w,        0x0 */
+            uint32_t DVSE            : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7    : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t DVS             : 4; /* [11: 8],        r/w,        0xc */
+            uint32_t reserved_12_15  : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t mm_mbist_done   : 7; /* [22:16],          r,        0x0 */
+            uint32_t reserved_23     : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t mm_mbist_fail   : 7; /* [30:24],          r,        0x0 */
+            uint32_t reserved_31     : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mm_mbist_ctrl;
+};
+
+typedef volatile struct mm_misc_reg mm_misc_reg_t;
+
+#endif /* __MM_MISC_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/pds_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/pds_reg.h
new file mode 100755
index 0000000000..f2339131ab
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/pds_reg.h
@@ -0,0 +1,1264 @@
+/**
+  ******************************************************************************
+  * @file    pds_reg.h
+  * @version V1.0
+  * @date    2021-11-22
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PDS_REG_H__
+#define __PDS_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : PDS_CTL */
+#define PDS_CTL_OFFSET                        (0x0)
+#define PDS_START_PS                          PDS_START_PS
+#define PDS_START_PS_POS                      (0U)
+#define PDS_START_PS_LEN                      (1U)
+#define PDS_START_PS_MSK                      (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
+#define PDS_START_PS_UMSK                     (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
+#define PDS_CR_SLEEP_FOREVER                  PDS_CR_SLEEP_FOREVER
+#define PDS_CR_SLEEP_FOREVER_POS              (1U)
+#define PDS_CR_SLEEP_FOREVER_LEN              (1U)
+#define PDS_CR_SLEEP_FOREVER_MSK              (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
+#define PDS_CR_SLEEP_FOREVER_UMSK             (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
+#define PDS_CR_XTAL_FORCE_OFF                 PDS_CR_XTAL_FORCE_OFF
+#define PDS_CR_XTAL_FORCE_OFF_POS             (2U)
+#define PDS_CR_XTAL_FORCE_OFF_LEN             (1U)
+#define PDS_CR_XTAL_FORCE_OFF_MSK             (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
+#define PDS_CR_XTAL_FORCE_OFF_UMSK            (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
+#define PDS_CR_PDS_WIFI_SAVE_STATE            PDS_CR_PDS_WIFI_SAVE_STATE
+#define PDS_CR_PDS_WIFI_SAVE_STATE_POS        (3U)
+#define PDS_CR_PDS_WIFI_SAVE_STATE_LEN        (1U)
+#define PDS_CR_PDS_WIFI_SAVE_STATE_MSK        (((1U << PDS_CR_PDS_WIFI_SAVE_STATE_LEN) - 1) << PDS_CR_PDS_WIFI_SAVE_STATE_POS)
+#define PDS_CR_PDS_WIFI_SAVE_STATE_UMSK       (~(((1U << PDS_CR_PDS_WIFI_SAVE_STATE_LEN) - 1) << PDS_CR_PDS_WIFI_SAVE_STATE_POS))
+#define PDS_CR_PDS_PD_LDO11                   PDS_CR_PDS_PD_LDO11
+#define PDS_CR_PDS_PD_LDO11_POS               (4U)
+#define PDS_CR_PDS_PD_LDO11_LEN               (1U)
+#define PDS_CR_PDS_PD_LDO11_MSK               (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)
+#define PDS_CR_PDS_PD_LDO11_UMSK              (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS))
+#define PDS_CR_PDS_PD_BG_SYS                  PDS_CR_PDS_PD_BG_SYS
+#define PDS_CR_PDS_PD_BG_SYS_POS              (5U)
+#define PDS_CR_PDS_PD_BG_SYS_LEN              (1U)
+#define PDS_CR_PDS_PD_BG_SYS_MSK              (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
+#define PDS_CR_PDS_PD_BG_SYS_UMSK             (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD         PDS_CR_PDS_CTRL_GPIO_IE_PU_PD
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS     (6U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN     (1U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK     (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK    (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS))
+#define PDS_CR_PDS_PD_DCDC18                  PDS_CR_PDS_PD_DCDC18
+#define PDS_CR_PDS_PD_DCDC18_POS              (7U)
+#define PDS_CR_PDS_PD_DCDC18_LEN              (1U)
+#define PDS_CR_PDS_PD_DCDC18_MSK              (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
+#define PDS_CR_PDS_PD_DCDC18_UMSK             (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
+#define PDS_CR_PDS_GATE_CLK                   PDS_CR_PDS_GATE_CLK
+#define PDS_CR_PDS_GATE_CLK_POS               (8U)
+#define PDS_CR_PDS_GATE_CLK_LEN               (1U)
+#define PDS_CR_PDS_GATE_CLK_MSK               (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
+#define PDS_CR_PDS_GATE_CLK_UMSK              (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
+#define PDS_CR_PDS_MEM_STBY                   PDS_CR_PDS_MEM_STBY
+#define PDS_CR_PDS_MEM_STBY_POS               (9U)
+#define PDS_CR_PDS_MEM_STBY_LEN               (1U)
+#define PDS_CR_PDS_MEM_STBY_MSK               (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
+#define PDS_CR_PDS_MEM_STBY_UMSK              (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT      PDS_CR_PDS_GLB_REG_RESET_PROTECT
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS  (10U)
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN  (1U)
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_MSK  (((1U << PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN) - 1) << PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS)
+#define PDS_CR_PDS_GLB_REG_RESET_PROTECT_UMSK (~(((1U << PDS_CR_PDS_GLB_REG_RESET_PROTECT_LEN) - 1) << PDS_CR_PDS_GLB_REG_RESET_PROTECT_POS))
+#define PDS_CR_PDS_ISO_EN                     PDS_CR_PDS_ISO_EN
+#define PDS_CR_PDS_ISO_EN_POS                 (11U)
+#define PDS_CR_PDS_ISO_EN_LEN                 (1U)
+#define PDS_CR_PDS_ISO_EN_MSK                 (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
+#define PDS_CR_PDS_ISO_EN_UMSK                (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
+#define PDS_CR_PDS_WAIT_XTAL_RDY              PDS_CR_PDS_WAIT_XTAL_RDY
+#define PDS_CR_PDS_WAIT_XTAL_RDY_POS          (12U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN          (1U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK          (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK         (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
+#define PDS_CR_PDS_PWR_OFF                    PDS_CR_PDS_PWR_OFF
+#define PDS_CR_PDS_PWR_OFF_POS                (13U)
+#define PDS_CR_PDS_PWR_OFF_LEN                (1U)
+#define PDS_CR_PDS_PWR_OFF_MSK                (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
+#define PDS_CR_PDS_PWR_OFF_UMSK               (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
+#define PDS_CR_PDS_PD_XTAL                    PDS_CR_PDS_PD_XTAL
+#define PDS_CR_PDS_PD_XTAL_POS                (14U)
+#define PDS_CR_PDS_PD_XTAL_LEN                (1U)
+#define PDS_CR_PDS_PD_XTAL_MSK                (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
+#define PDS_CR_PDS_PD_XTAL_UMSK               (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
+#define PDS_CR_PDS_CTRL_SOC_ENB               PDS_CR_PDS_CTRL_SOC_ENB
+#define PDS_CR_PDS_CTRL_SOC_ENB_POS           (15U)
+#define PDS_CR_PDS_CTRL_SOC_ENB_LEN           (1U)
+#define PDS_CR_PDS_CTRL_SOC_ENB_MSK           (((1U << PDS_CR_PDS_CTRL_SOC_ENB_LEN) - 1) << PDS_CR_PDS_CTRL_SOC_ENB_POS)
+#define PDS_CR_PDS_CTRL_SOC_ENB_UMSK          (~(((1U << PDS_CR_PDS_CTRL_SOC_ENB_LEN) - 1) << PDS_CR_PDS_CTRL_SOC_ENB_POS))
+#define PDS_CR_PDS_RST_SOC                    PDS_CR_PDS_RST_SOC
+#define PDS_CR_PDS_RST_SOC_POS                (16U)
+#define PDS_CR_PDS_RST_SOC_LEN                (1U)
+#define PDS_CR_PDS_RST_SOC_MSK                (((1U << PDS_CR_PDS_RST_SOC_LEN) - 1) << PDS_CR_PDS_RST_SOC_POS)
+#define PDS_CR_PDS_RST_SOC_UMSK               (~(((1U << PDS_CR_PDS_RST_SOC_LEN) - 1) << PDS_CR_PDS_RST_SOC_POS))
+#define PDS_CR_PDS_RC32M_OFF_DIS              PDS_CR_PDS_RC32M_OFF_DIS
+#define PDS_CR_PDS_RC32M_OFF_DIS_POS          (17U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_LEN          (1U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_MSK          (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
+#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK         (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
+#define PDS_CR_PDS_LDO11_VSEL_EN              PDS_CR_PDS_LDO11_VSEL_EN
+#define PDS_CR_PDS_LDO11_VSEL_EN_POS          (18U)
+#define PDS_CR_PDS_LDO11_VSEL_EN_LEN          (1U)
+#define PDS_CR_PDS_LDO11_VSEL_EN_MSK          (((1U << PDS_CR_PDS_LDO11_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO11_VSEL_EN_POS)
+#define PDS_CR_PDS_LDO11_VSEL_EN_UMSK         (~(((1U << PDS_CR_PDS_LDO11_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO11_VSEL_EN_POS))
+#define PDS_CR_PDS_CTRL_USBPLL_PD             PDS_CR_PDS_CTRL_USBPLL_PD
+#define PDS_CR_PDS_CTRL_USBPLL_PD_POS         (19U)
+#define PDS_CR_PDS_CTRL_USBPLL_PD_LEN         (1U)
+#define PDS_CR_PDS_CTRL_USBPLL_PD_MSK         (((1U << PDS_CR_PDS_CTRL_USBPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_USBPLL_PD_POS)
+#define PDS_CR_PDS_CTRL_USBPLL_PD_UMSK        (~(((1U << PDS_CR_PDS_CTRL_USBPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_USBPLL_PD_POS))
+#define PDS_CR_PDS_CTRL_AUPLL_PD              PDS_CR_PDS_CTRL_AUPLL_PD
+#define PDS_CR_PDS_CTRL_AUPLL_PD_POS          (20U)
+#define PDS_CR_PDS_CTRL_AUPLL_PD_LEN          (1U)
+#define PDS_CR_PDS_CTRL_AUPLL_PD_MSK          (((1U << PDS_CR_PDS_CTRL_AUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_AUPLL_PD_POS)
+#define PDS_CR_PDS_CTRL_AUPLL_PD_UMSK         (~(((1U << PDS_CR_PDS_CTRL_AUPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_AUPLL_PD_POS))
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD            PDS_CR_PDS_CTRL_WIFIPLL_PD
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_POS        (22U)
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN        (1U)
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_MSK        (((1U << PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_WIFIPLL_PD_POS)
+#define PDS_CR_PDS_CTRL_WIFIPLL_PD_UMSK       (~(((1U << PDS_CR_PDS_CTRL_WIFIPLL_PD_LEN) - 1) << PDS_CR_PDS_CTRL_WIFIPLL_PD_POS))
+#define PDS_CR_PDS_LDO11_VOL                  PDS_CR_PDS_LDO11_VOL
+#define PDS_CR_PDS_LDO11_VOL_POS              (23U)
+#define PDS_CR_PDS_LDO11_VOL_LEN              (5U)
+#define PDS_CR_PDS_LDO11_VOL_MSK              (((1U << PDS_CR_PDS_LDO11_VOL_LEN) - 1) << PDS_CR_PDS_LDO11_VOL_POS)
+#define PDS_CR_PDS_LDO11_VOL_UMSK             (~(((1U << PDS_CR_PDS_LDO11_VOL_LEN) - 1) << PDS_CR_PDS_LDO11_VOL_POS))
+#define PDS_CR_PDS_CTRL_RF                    PDS_CR_PDS_CTRL_RF
+#define PDS_CR_PDS_CTRL_RF_POS                (28U)
+#define PDS_CR_PDS_CTRL_RF_LEN                (2U)
+#define PDS_CR_PDS_CTRL_RF_MSK                (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
+#define PDS_CR_PDS_CTRL_RF_UMSK               (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP       PDS_CR_PDS_START_USE_TBTT_SLEEP
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_POS   (30U)
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN   (1U)
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_MSK   (((1U << PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN) - 1) << PDS_CR_PDS_START_USE_TBTT_SLEEP_POS)
+#define PDS_CR_PDS_START_USE_TBTT_SLEEP_UMSK  (~(((1U << PDS_CR_PDS_START_USE_TBTT_SLEEP_LEN) - 1) << PDS_CR_PDS_START_USE_TBTT_SLEEP_POS))
+#define PDS_CR_PDS_GPIO_ISO_MODE              PDS_CR_PDS_GPIO_ISO_MODE
+#define PDS_CR_PDS_GPIO_ISO_MODE_POS          (31U)
+#define PDS_CR_PDS_GPIO_ISO_MODE_LEN          (1U)
+#define PDS_CR_PDS_GPIO_ISO_MODE_MSK          (((1U << PDS_CR_PDS_GPIO_ISO_MODE_LEN) - 1) << PDS_CR_PDS_GPIO_ISO_MODE_POS)
+#define PDS_CR_PDS_GPIO_ISO_MODE_UMSK         (~(((1U << PDS_CR_PDS_GPIO_ISO_MODE_LEN) - 1) << PDS_CR_PDS_GPIO_ISO_MODE_POS))
+
+/* 0x4 : PDS_TIME1 */
+#define PDS_TIME1_OFFSET           (0x4)
+#define PDS_CR_SLEEP_DURATION      PDS_CR_SLEEP_DURATION
+#define PDS_CR_SLEEP_DURATION_POS  (0U)
+#define PDS_CR_SLEEP_DURATION_LEN  (32U)
+#define PDS_CR_SLEEP_DURATION_MSK  (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
+#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))
+
+/* 0xC : PDS_INT */
+#define PDS_INT_OFFSET                            (0xC)
+#define PDS_RO_PDS_WAKE_INT                       PDS_RO_PDS_WAKE_INT
+#define PDS_RO_PDS_WAKE_INT_POS                   (0U)
+#define PDS_RO_PDS_WAKE_INT_LEN                   (1U)
+#define PDS_RO_PDS_WAKE_INT_MSK                   (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
+#define PDS_RO_PDS_WAKE_INT_UMSK                  (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
+#define PDS_RO_PDS_RF_DONE_INT                    PDS_RO_PDS_RF_DONE_INT
+#define PDS_RO_PDS_RF_DONE_INT_POS                (1U)
+#define PDS_RO_PDS_RF_DONE_INT_LEN                (1U)
+#define PDS_RO_PDS_RF_DONE_INT_MSK                (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
+#define PDS_RO_PDS_RF_DONE_INT_UMSK               (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ            PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS        (2U)
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN        (1U)
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_MSK        (((1U << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS)
+#define PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_UMSK       (~(((1U << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_SLEEP_IRQ_POS))
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ           PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS       (3U)
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN       (1U)
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_MSK       (((1U << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS)
+#define PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_UMSK      (~(((1U << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_LEN) - 1) << PDS_RO_PDS_WIFI_TBTT_WAKEUP_IRQ_POS))
+#define PDS_CR_PDS_WAKE_INT_MASK                  PDS_CR_PDS_WAKE_INT_MASK
+#define PDS_CR_PDS_WAKE_INT_MASK_POS              (4U)
+#define PDS_CR_PDS_WAKE_INT_MASK_LEN              (1U)
+#define PDS_CR_PDS_WAKE_INT_MASK_MSK              (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
+#define PDS_CR_PDS_WAKE_INT_MASK_UMSK             (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
+#define PDS_CR_PDS_RF_DONE_INT_MASK               PDS_CR_PDS_RF_DONE_INT_MASK
+#define PDS_CR_PDS_RF_DONE_INT_MASK_POS           (5U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN           (1U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK           (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK          (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK       PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS   (6U)
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN   (1U)
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_MSK   (((1U << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS)
+#define PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_UMSK  (~(((1U << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK_POS))
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK      PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS  (7U)
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN  (1U)
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_MSK  (((1U << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS)
+#define PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_UMSK (~(((1U << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_LEN) - 1) << PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK_POS))
+#define PDS_CR_PDS_INT_CLR                        PDS_CR_PDS_INT_CLR
+#define PDS_CR_PDS_INT_CLR_POS                    (8U)
+#define PDS_CR_PDS_INT_CLR_LEN                    (1U)
+#define PDS_CR_PDS_INT_CLR_MSK                    (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
+#define PDS_CR_PDS_INT_CLR_UMSK                   (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
+#define PDS_CR_PDS_WAKEUP_SRC_EN                  PDS_CR_PDS_WAKEUP_SRC_EN
+#define PDS_CR_PDS_WAKEUP_SRC_EN_POS              (10U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN              (10U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK              (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK             (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS))
+#define PDS_RO_PDS_WAKEUP_EVENT                   PDS_RO_PDS_WAKEUP_EVENT
+#define PDS_RO_PDS_WAKEUP_EVENT_POS               (21U)
+#define PDS_RO_PDS_WAKEUP_EVENT_LEN               (10U)
+#define PDS_RO_PDS_WAKEUP_EVENT_MSK               (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)
+#define PDS_RO_PDS_WAKEUP_EVENT_UMSK              (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS))
+
+/* 0x10 : PDS_CTL2 */
+#define PDS_CTL2_OFFSET                    (0x10)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF        PDS_CR_PDS_FORCE_NP_PWR_OFF
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS    (0U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF        PDS_CR_PDS_FORCE_WB_PWR_OFF
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_POS    (2U)
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_WB_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF       PDS_CR_PDS_FORCE_USB_PWR_OFF
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS   (3U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_NP_ISO_EN         PDS_CR_PDS_FORCE_NP_ISO_EN
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS     (4U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_WB_ISO_EN         PDS_CR_PDS_FORCE_WB_ISO_EN
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_POS     (6U)
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_WB_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_WB_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_USB_ISO_EN        PDS_CR_PDS_FORCE_USB_ISO_EN
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS    (7U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_NP_PDS_RST        PDS_CR_PDS_FORCE_NP_PDS_RST
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS    (8U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_WB_PDS_RST        PDS_CR_PDS_FORCE_WB_PDS_RST
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_POS    (10U)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_WB_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_WB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_WB_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_USB_PDS_RST       PDS_CR_PDS_FORCE_USB_PDS_RST
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS   (11U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY       PDS_CR_PDS_FORCE_NP_MEM_STBY
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS   (12U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY       PDS_CR_PDS_FORCE_WB_MEM_STBY
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_POS   (14U)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_WB_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_WB_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY      PDS_CR_PDS_FORCE_USB_MEM_STBY
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS  (15U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK       PDS_CR_PDS_FORCE_NP_GATE_CLK
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS   (16U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK       PDS_CR_PDS_FORCE_WB_GATE_CLK
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_POS   (18U)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_WB_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_WB_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK      PDS_CR_PDS_FORCE_USB_GATE_CLK
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS  (19U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS))
+
+/* 0x14 : PDS_CTL3 */
+#define PDS_CTL3_OFFSET                     (0x14)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF       PDS_CR_PDS_FORCE_MISC_PWR_OFF
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN        PDS_CR_PDS_FORCE_MISC_ISO_EN
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_POS    (4U)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_MISC_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST       PDS_CR_PDS_FORCE_MISC_PDS_RST
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS   (7U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY      PDS_CR_PDS_FORCE_MISC_MEM_STBY
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS  (10U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK      PDS_CR_PDS_FORCE_MISC_GATE_CLK
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS  (13U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
+#define PDS_CR_PDS_NP_ISO_EN                PDS_CR_PDS_NP_ISO_EN
+#define PDS_CR_PDS_NP_ISO_EN_POS            (24U)
+#define PDS_CR_PDS_NP_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_NP_ISO_EN_MSK            (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)
+#define PDS_CR_PDS_NP_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS))
+#define PDS_CR_PDS_WB_ISO_EN                PDS_CR_PDS_WB_ISO_EN
+#define PDS_CR_PDS_WB_ISO_EN_POS            (27U)
+#define PDS_CR_PDS_WB_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_WB_ISO_EN_MSK            (((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS)
+#define PDS_CR_PDS_WB_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_WB_ISO_EN_LEN) - 1) << PDS_CR_PDS_WB_ISO_EN_POS))
+#define PDS_CR_PDS_USB_ISO_EN               PDS_CR_PDS_USB_ISO_EN
+#define PDS_CR_PDS_USB_ISO_EN_POS           (29U)
+#define PDS_CR_PDS_USB_ISO_EN_LEN           (1U)
+#define PDS_CR_PDS_USB_ISO_EN_MSK           (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)
+#define PDS_CR_PDS_USB_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS))
+#define PDS_CR_PDS_MISC_ISO_EN              PDS_CR_PDS_MISC_ISO_EN
+#define PDS_CR_PDS_MISC_ISO_EN_POS          (30U)
+#define PDS_CR_PDS_MISC_ISO_EN_LEN          (1U)
+#define PDS_CR_PDS_MISC_ISO_EN_MSK          (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_MISC_ISO_EN_UMSK         (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))
+
+/* 0x18 : PDS_CTL4 */
+#define PDS_CTL4_OFFSET               (0x18)
+#define PDS_CR_PDS_NP_PWR_OFF         PDS_CR_PDS_NP_PWR_OFF
+#define PDS_CR_PDS_NP_PWR_OFF_POS     (0U)
+#define PDS_CR_PDS_NP_PWR_OFF_LEN     (1U)
+#define PDS_CR_PDS_NP_PWR_OFF_MSK     (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_NP_PWR_OFF_UMSK    (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_NP_RESET           PDS_CR_PDS_NP_RESET
+#define PDS_CR_PDS_NP_RESET_POS       (1U)
+#define PDS_CR_PDS_NP_RESET_LEN       (1U)
+#define PDS_CR_PDS_NP_RESET_MSK       (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
+#define PDS_CR_PDS_NP_RESET_UMSK      (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
+#define PDS_CR_PDS_NP_MEM_STBY        PDS_CR_PDS_NP_MEM_STBY
+#define PDS_CR_PDS_NP_MEM_STBY_POS    (2U)
+#define PDS_CR_PDS_NP_MEM_STBY_LEN    (1U)
+#define PDS_CR_PDS_NP_MEM_STBY_MSK    (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_NP_MEM_STBY_UMSK   (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_NP_GATE_CLK        PDS_CR_PDS_NP_GATE_CLK
+#define PDS_CR_PDS_NP_GATE_CLK_POS    (3U)
+#define PDS_CR_PDS_NP_GATE_CLK_LEN    (1U)
+#define PDS_CR_PDS_NP_GATE_CLK_MSK    (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_NP_GATE_CLK_UMSK   (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_WB_PWR_OFF         PDS_CR_PDS_WB_PWR_OFF
+#define PDS_CR_PDS_WB_PWR_OFF_POS     (12U)
+#define PDS_CR_PDS_WB_PWR_OFF_LEN     (1U)
+#define PDS_CR_PDS_WB_PWR_OFF_MSK     (((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS)
+#define PDS_CR_PDS_WB_PWR_OFF_UMSK    (~(((1U << PDS_CR_PDS_WB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_WB_PWR_OFF_POS))
+#define PDS_CR_PDS_WB_RESET           PDS_CR_PDS_WB_RESET
+#define PDS_CR_PDS_WB_RESET_POS       (13U)
+#define PDS_CR_PDS_WB_RESET_LEN       (1U)
+#define PDS_CR_PDS_WB_RESET_MSK       (((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS)
+#define PDS_CR_PDS_WB_RESET_UMSK      (~(((1U << PDS_CR_PDS_WB_RESET_LEN) - 1) << PDS_CR_PDS_WB_RESET_POS))
+#define PDS_CR_PDS_WB_MEM_STBY        PDS_CR_PDS_WB_MEM_STBY
+#define PDS_CR_PDS_WB_MEM_STBY_POS    (14U)
+#define PDS_CR_PDS_WB_MEM_STBY_LEN    (1U)
+#define PDS_CR_PDS_WB_MEM_STBY_MSK    (((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS)
+#define PDS_CR_PDS_WB_MEM_STBY_UMSK   (~(((1U << PDS_CR_PDS_WB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_WB_MEM_STBY_POS))
+#define PDS_CR_PDS_WB_GATE_CLK        PDS_CR_PDS_WB_GATE_CLK
+#define PDS_CR_PDS_WB_GATE_CLK_POS    (15U)
+#define PDS_CR_PDS_WB_GATE_CLK_LEN    (1U)
+#define PDS_CR_PDS_WB_GATE_CLK_MSK    (((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS)
+#define PDS_CR_PDS_WB_GATE_CLK_UMSK   (~(((1U << PDS_CR_PDS_WB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_WB_GATE_CLK_POS))
+#define PDS_CR_PDS_USB_PWR_OFF        PDS_CR_PDS_USB_PWR_OFF
+#define PDS_CR_PDS_USB_PWR_OFF_POS    (20U)
+#define PDS_CR_PDS_USB_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_USB_PWR_OFF_MSK    (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_USB_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_USB_RESET          PDS_CR_PDS_USB_RESET
+#define PDS_CR_PDS_USB_RESET_POS      (21U)
+#define PDS_CR_PDS_USB_RESET_LEN      (1U)
+#define PDS_CR_PDS_USB_RESET_MSK      (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)
+#define PDS_CR_PDS_USB_RESET_UMSK     (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS))
+#define PDS_CR_PDS_USB_MEM_STBY       PDS_CR_PDS_USB_MEM_STBY
+#define PDS_CR_PDS_USB_MEM_STBY_POS   (22U)
+#define PDS_CR_PDS_USB_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_USB_MEM_STBY_MSK   (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_USB_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_USB_GATE_CLK       PDS_CR_PDS_USB_GATE_CLK
+#define PDS_CR_PDS_USB_GATE_CLK_POS   (23U)
+#define PDS_CR_PDS_USB_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_USB_GATE_CLK_MSK   (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_USB_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS))
+#define PDS_CR_PDS_MISC_PWR_OFF       PDS_CR_PDS_MISC_PWR_OFF
+#define PDS_CR_PDS_MISC_PWR_OFF_POS   (24U)
+#define PDS_CR_PDS_MISC_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_MISC_RESET         PDS_CR_PDS_MISC_RESET
+#define PDS_CR_PDS_MISC_RESET_POS     (25U)
+#define PDS_CR_PDS_MISC_RESET_LEN     (1U)
+#define PDS_CR_PDS_MISC_RESET_MSK     (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
+#define PDS_CR_PDS_MISC_RESET_UMSK    (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
+#define PDS_CR_PDS_MISC_MEM_STBY      PDS_CR_PDS_MISC_MEM_STBY
+#define PDS_CR_PDS_MISC_MEM_STBY_POS  (26U)
+#define PDS_CR_PDS_MISC_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_MISC_GATE_CLK      PDS_CR_PDS_MISC_GATE_CLK
+#define PDS_CR_PDS_MISC_GATE_CLK_POS  (27U)
+#define PDS_CR_PDS_MISC_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))
+
+/* 0x1C : pds_stat */
+#define PDS_STAT_OFFSET          (0x1C)
+#define PDS_RO_PDS_STATE         PDS_RO_PDS_STATE
+#define PDS_RO_PDS_STATE_POS     (0U)
+#define PDS_RO_PDS_STATE_LEN     (5U)
+#define PDS_RO_PDS_STATE_MSK     (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
+#define PDS_RO_PDS_STATE_UMSK    (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
+#define PDS_RO_PDS_RF_STATE      PDS_RO_PDS_RF_STATE
+#define PDS_RO_PDS_RF_STATE_POS  (8U)
+#define PDS_RO_PDS_RF_STATE_LEN  (5U)
+#define PDS_RO_PDS_RF_STATE_MSK  (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
+#define PDS_RO_PDS_RF_STATE_UMSK (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
+#define PDS_RESET_EVENT          PDS_RESET_EVENT
+#define PDS_RESET_EVENT_POS      (24U)
+#define PDS_RESET_EVENT_LEN      (3U)
+#define PDS_RESET_EVENT_MSK      (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)
+#define PDS_RESET_EVENT_UMSK     (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS))
+#define PDS_CLR_RESET_EVENT      PDS_CLR_RESET_EVENT
+#define PDS_CLR_RESET_EVENT_POS  (31U)
+#define PDS_CLR_RESET_EVENT_LEN  (1U)
+#define PDS_CLR_RESET_EVENT_MSK  (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)
+#define PDS_CLR_RESET_EVENT_UMSK (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS))
+
+/* 0x20 : pds_ram1 */
+#define PDS_RAM1_OFFSET                   (0x20)
+#define PDS_CR_PDS_RAM_CLK_CNT            PDS_CR_PDS_RAM_CLK_CNT
+#define PDS_CR_PDS_RAM_CLK_CNT_POS        (8U)
+#define PDS_CR_PDS_RAM_CLK_CNT_LEN        (6U)
+#define PDS_CR_PDS_RAM_CLK_CNT_MSK        (((1U << PDS_CR_PDS_RAM_CLK_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK_CNT_POS)
+#define PDS_CR_PDS_RAM_CLK_CNT_UMSK       (~(((1U << PDS_CR_PDS_RAM_CLK_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK_CNT_POS))
+#define PDS_CR_PDS_RAM_CLK2_CNT           PDS_CR_PDS_RAM_CLK2_CNT
+#define PDS_CR_PDS_RAM_CLK2_CNT_POS       (16U)
+#define PDS_CR_PDS_RAM_CLK2_CNT_LEN       (6U)
+#define PDS_CR_PDS_RAM_CLK2_CNT_MSK       (((1U << PDS_CR_PDS_RAM_CLK2_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK2_CNT_POS)
+#define PDS_CR_PDS_RAM_CLK2_CNT_UMSK      (~(((1U << PDS_CR_PDS_RAM_CLK2_CNT_LEN) - 1) << PDS_CR_PDS_RAM_CLK2_CNT_POS))
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK        PDS_CR_PDS_CTRL_NP_RAM_CLK
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_POS    (24U)
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN    (1U)
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_MSK    (((1U << PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_NP_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_NP_RAM_CLK_UMSK   (~(((1U << PDS_CR_PDS_CTRL_NP_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_NP_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK        PDS_CR_PDS_CTRL_WB_RAM_CLK
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_POS    (26U)
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN    (1U)
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_MSK    (((1U << PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_WB_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_WB_RAM_CLK_UMSK   (~(((1U << PDS_CR_PDS_CTRL_WB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_WB_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK       PDS_CR_PDS_CTRL_USB_RAM_CLK
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_POS   (27U)
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN   (1U)
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_MSK   (((1U << PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_USB_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_USB_RAM_CLK_UMSK  (~(((1U << PDS_CR_PDS_CTRL_USB_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_USB_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK      PDS_CR_PDS_CTRL_MISC_RAM_CLK
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS  (28U)
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN  (1U)
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_MSK  (((1U << PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_MISC_RAM_CLK_UMSK (~(((1U << PDS_CR_PDS_CTRL_MISC_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_MISC_RAM_CLK_POS))
+#define PDS_CR_PDS_CTRL_RAM_CLK2          PDS_CR_PDS_CTRL_RAM_CLK2
+#define PDS_CR_PDS_CTRL_RAM_CLK2_POS      (30U)
+#define PDS_CR_PDS_CTRL_RAM_CLK2_LEN      (1U)
+#define PDS_CR_PDS_CTRL_RAM_CLK2_MSK      (((1U << PDS_CR_PDS_CTRL_RAM_CLK2_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK2_POS)
+#define PDS_CR_PDS_CTRL_RAM_CLK2_UMSK     (~(((1U << PDS_CR_PDS_CTRL_RAM_CLK2_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK2_POS))
+#define PDS_CR_PDS_CTRL_RAM_CLK           PDS_CR_PDS_CTRL_RAM_CLK
+#define PDS_CR_PDS_CTRL_RAM_CLK_POS       (31U)
+#define PDS_CR_PDS_CTRL_RAM_CLK_LEN       (1U)
+#define PDS_CR_PDS_CTRL_RAM_CLK_MSK       (((1U << PDS_CR_PDS_CTRL_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK_POS)
+#define PDS_CR_PDS_CTRL_RAM_CLK_UMSK      (~(((1U << PDS_CR_PDS_CTRL_RAM_CLK_LEN) - 1) << PDS_CR_PDS_CTRL_RAM_CLK_POS))
+
+/* 0x24 : PDS_CTL5 */
+#define PDS_CTL5_OFFSET              (0x24)
+#define PDS_CR_NP_WFI_MASK           PDS_CR_NP_WFI_MASK
+#define PDS_CR_NP_WFI_MASK_POS       (0U)
+#define PDS_CR_NP_WFI_MASK_LEN       (1U)
+#define PDS_CR_NP_WFI_MASK_MSK       (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
+#define PDS_CR_NP_WFI_MASK_UMSK      (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
+#define PDS_CR_PDS_PAD_OD_EN         PDS_CR_PDS_PAD_OD_EN
+#define PDS_CR_PDS_PAD_OD_EN_POS     (1U)
+#define PDS_CR_PDS_PAD_OD_EN_LEN     (1U)
+#define PDS_CR_PDS_PAD_OD_EN_MSK     (((1U << PDS_CR_PDS_PAD_OD_EN_LEN) - 1) << PDS_CR_PDS_PAD_OD_EN_POS)
+#define PDS_CR_PDS_PAD_OD_EN_UMSK    (~(((1U << PDS_CR_PDS_PAD_OD_EN_LEN) - 1) << PDS_CR_PDS_PAD_OD_EN_POS))
+#define PDS_CR_PDS_CTRL_USB33        PDS_CR_PDS_CTRL_USB33
+#define PDS_CR_PDS_CTRL_USB33_POS    (8U)
+#define PDS_CR_PDS_CTRL_USB33_LEN    (1U)
+#define PDS_CR_PDS_CTRL_USB33_MSK    (((1U << PDS_CR_PDS_CTRL_USB33_LEN) - 1) << PDS_CR_PDS_CTRL_USB33_POS)
+#define PDS_CR_PDS_CTRL_USB33_UMSK   (~(((1U << PDS_CR_PDS_CTRL_USB33_LEN) - 1) << PDS_CR_PDS_CTRL_USB33_POS))
+#define PDS_CR_PDS_PD_LDO18IO        PDS_CR_PDS_PD_LDO18IO
+#define PDS_CR_PDS_PD_LDO18IO_POS    (9U)
+#define PDS_CR_PDS_PD_LDO18IO_LEN    (1U)
+#define PDS_CR_PDS_PD_LDO18IO_MSK    (((1U << PDS_CR_PDS_PD_LDO18IO_LEN) - 1) << PDS_CR_PDS_PD_LDO18IO_POS)
+#define PDS_CR_PDS_PD_LDO18IO_UMSK   (~(((1U << PDS_CR_PDS_PD_LDO18IO_LEN) - 1) << PDS_CR_PDS_PD_LDO18IO_POS))
+#define PDS_CR_PDS_GPIO_KEEP_EN      PDS_CR_PDS_GPIO_KEEP_EN
+#define PDS_CR_PDS_GPIO_KEEP_EN_POS  (16U)
+#define PDS_CR_PDS_GPIO_KEEP_EN_LEN  (3U)
+#define PDS_CR_PDS_GPIO_KEEP_EN_MSK  (((1U << PDS_CR_PDS_GPIO_KEEP_EN_LEN) - 1) << PDS_CR_PDS_GPIO_KEEP_EN_POS)
+#define PDS_CR_PDS_GPIO_KEEP_EN_UMSK (~(((1U << PDS_CR_PDS_GPIO_KEEP_EN_LEN) - 1) << PDS_CR_PDS_GPIO_KEEP_EN_POS))
+
+/* 0x28 : PDS_RAM2 */
+#define PDS_RAM2_OFFSET      (0x28)
+#define PDS_CR_WRAM_SLP      PDS_CR_WRAM_SLP
+#define PDS_CR_WRAM_SLP_POS  (0U)
+#define PDS_CR_WRAM_SLP_LEN  (10U)
+#define PDS_CR_WRAM_SLP_MSK  (((1U << PDS_CR_WRAM_SLP_LEN) - 1) << PDS_CR_WRAM_SLP_POS)
+#define PDS_CR_WRAM_SLP_UMSK (~(((1U << PDS_CR_WRAM_SLP_LEN) - 1) << PDS_CR_WRAM_SLP_POS))
+#define PDS_CR_WRAM_RET      PDS_CR_WRAM_RET
+#define PDS_CR_WRAM_RET_POS  (10U)
+#define PDS_CR_WRAM_RET_LEN  (10U)
+#define PDS_CR_WRAM_RET_MSK  (((1U << PDS_CR_WRAM_RET_LEN) - 1) << PDS_CR_WRAM_RET_POS)
+#define PDS_CR_WRAM_RET_UMSK (~(((1U << PDS_CR_WRAM_RET_LEN) - 1) << PDS_CR_WRAM_RET_POS))
+
+/* 0x30 : pds_gpio_i_set */
+#define PDS_GPIO_I_SET_OFFSET       (0x30)
+#define PDS_CR_PDS_GPIO_IE_SET      PDS_CR_PDS_GPIO_IE_SET
+#define PDS_CR_PDS_GPIO_IE_SET_POS  (0U)
+#define PDS_CR_PDS_GPIO_IE_SET_LEN  (2U)
+#define PDS_CR_PDS_GPIO_IE_SET_MSK  (((1U << PDS_CR_PDS_GPIO_IE_SET_LEN) - 1) << PDS_CR_PDS_GPIO_IE_SET_POS)
+#define PDS_CR_PDS_GPIO_IE_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_IE_SET_LEN) - 1) << PDS_CR_PDS_GPIO_IE_SET_POS))
+#define PDS_CR_PDS_GPIO_PD_SET      PDS_CR_PDS_GPIO_PD_SET
+#define PDS_CR_PDS_GPIO_PD_SET_POS  (3U)
+#define PDS_CR_PDS_GPIO_PD_SET_LEN  (2U)
+#define PDS_CR_PDS_GPIO_PD_SET_MSK  (((1U << PDS_CR_PDS_GPIO_PD_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PD_SET_POS)
+#define PDS_CR_PDS_GPIO_PD_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_PD_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PD_SET_POS))
+#define PDS_CR_PDS_GPIO_PU_SET      PDS_CR_PDS_GPIO_PU_SET
+#define PDS_CR_PDS_GPIO_PU_SET_POS  (6U)
+#define PDS_CR_PDS_GPIO_PU_SET_LEN  (2U)
+#define PDS_CR_PDS_GPIO_PU_SET_MSK  (((1U << PDS_CR_PDS_GPIO_PU_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PU_SET_POS)
+#define PDS_CR_PDS_GPIO_PU_SET_UMSK (~(((1U << PDS_CR_PDS_GPIO_PU_SET_LEN) - 1) << PDS_CR_PDS_GPIO_PU_SET_POS))
+
+/* 0x34 : pds_gpio_pd_set */
+#define PDS_GPIO_PD_SET_OFFSET            (0x34)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK      PDS_CR_PDS_GPIO_SET_INT_MASK
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_POS  (0U)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_LEN  (31U)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_MSK  (((1U << PDS_CR_PDS_GPIO_SET_INT_MASK_LEN) - 1) << PDS_CR_PDS_GPIO_SET_INT_MASK_POS)
+#define PDS_CR_PDS_GPIO_SET_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_GPIO_SET_INT_MASK_LEN) - 1) << PDS_CR_PDS_GPIO_SET_INT_MASK_POS))
+
+/* 0x40 : pds_gpio_int */
+#define PDS_GPIO_INT_OFFSET         (0x40)
+#define PDS_GPIO_SET1_INT_CLR       PDS_GPIO_SET1_INT_CLR
+#define PDS_GPIO_SET1_INT_CLR_POS   (2U)
+#define PDS_GPIO_SET1_INT_CLR_LEN   (1U)
+#define PDS_GPIO_SET1_INT_CLR_MSK   (((1U << PDS_GPIO_SET1_INT_CLR_LEN) - 1) << PDS_GPIO_SET1_INT_CLR_POS)
+#define PDS_GPIO_SET1_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET1_INT_CLR_LEN) - 1) << PDS_GPIO_SET1_INT_CLR_POS))
+#define PDS_GPIO_SET1_INT_MODE      PDS_GPIO_SET1_INT_MODE
+#define PDS_GPIO_SET1_INT_MODE_POS  (4U)
+#define PDS_GPIO_SET1_INT_MODE_LEN  (4U)
+#define PDS_GPIO_SET1_INT_MODE_MSK  (((1U << PDS_GPIO_SET1_INT_MODE_LEN) - 1) << PDS_GPIO_SET1_INT_MODE_POS)
+#define PDS_GPIO_SET1_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET1_INT_MODE_LEN) - 1) << PDS_GPIO_SET1_INT_MODE_POS))
+#define PDS_GPIO_SET2_INT_CLR       PDS_GPIO_SET2_INT_CLR
+#define PDS_GPIO_SET2_INT_CLR_POS   (10U)
+#define PDS_GPIO_SET2_INT_CLR_LEN   (1U)
+#define PDS_GPIO_SET2_INT_CLR_MSK   (((1U << PDS_GPIO_SET2_INT_CLR_LEN) - 1) << PDS_GPIO_SET2_INT_CLR_POS)
+#define PDS_GPIO_SET2_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET2_INT_CLR_LEN) - 1) << PDS_GPIO_SET2_INT_CLR_POS))
+#define PDS_GPIO_SET2_INT_MODE      PDS_GPIO_SET2_INT_MODE
+#define PDS_GPIO_SET2_INT_MODE_POS  (12U)
+#define PDS_GPIO_SET2_INT_MODE_LEN  (4U)
+#define PDS_GPIO_SET2_INT_MODE_MSK  (((1U << PDS_GPIO_SET2_INT_MODE_LEN) - 1) << PDS_GPIO_SET2_INT_MODE_POS)
+#define PDS_GPIO_SET2_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET2_INT_MODE_LEN) - 1) << PDS_GPIO_SET2_INT_MODE_POS))
+#define PDS_GPIO_SET3_INT_CLR       PDS_GPIO_SET3_INT_CLR
+#define PDS_GPIO_SET3_INT_CLR_POS   (18U)
+#define PDS_GPIO_SET3_INT_CLR_LEN   (1U)
+#define PDS_GPIO_SET3_INT_CLR_MSK   (((1U << PDS_GPIO_SET3_INT_CLR_LEN) - 1) << PDS_GPIO_SET3_INT_CLR_POS)
+#define PDS_GPIO_SET3_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET3_INT_CLR_LEN) - 1) << PDS_GPIO_SET3_INT_CLR_POS))
+#define PDS_GPIO_SET3_INT_MODE      PDS_GPIO_SET3_INT_MODE
+#define PDS_GPIO_SET3_INT_MODE_POS  (20U)
+#define PDS_GPIO_SET3_INT_MODE_LEN  (4U)
+#define PDS_GPIO_SET3_INT_MODE_MSK  (((1U << PDS_GPIO_SET3_INT_MODE_LEN) - 1) << PDS_GPIO_SET3_INT_MODE_POS)
+#define PDS_GPIO_SET3_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET3_INT_MODE_LEN) - 1) << PDS_GPIO_SET3_INT_MODE_POS))
+#define PDS_GPIO_SET4_INT_CLR       PDS_GPIO_SET4_INT_CLR
+#define PDS_GPIO_SET4_INT_CLR_POS   (26U)
+#define PDS_GPIO_SET4_INT_CLR_LEN   (1U)
+#define PDS_GPIO_SET4_INT_CLR_MSK   (((1U << PDS_GPIO_SET4_INT_CLR_LEN) - 1) << PDS_GPIO_SET4_INT_CLR_POS)
+#define PDS_GPIO_SET4_INT_CLR_UMSK  (~(((1U << PDS_GPIO_SET4_INT_CLR_LEN) - 1) << PDS_GPIO_SET4_INT_CLR_POS))
+#define PDS_GPIO_SET4_INT_MODE      PDS_GPIO_SET4_INT_MODE
+#define PDS_GPIO_SET4_INT_MODE_POS  (28U)
+#define PDS_GPIO_SET4_INT_MODE_LEN  (4U)
+#define PDS_GPIO_SET4_INT_MODE_MSK  (((1U << PDS_GPIO_SET4_INT_MODE_LEN) - 1) << PDS_GPIO_SET4_INT_MODE_POS)
+#define PDS_GPIO_SET4_INT_MODE_UMSK (~(((1U << PDS_GPIO_SET4_INT_MODE_LEN) - 1) << PDS_GPIO_SET4_INT_MODE_POS))
+
+/* 0x44 : pds_gpio_stat */
+#define PDS_GPIO_STAT_OFFSET   (0x44)
+#define PDS_GPIO_INT_STAT      PDS_GPIO_INT_STAT
+#define PDS_GPIO_INT_STAT_POS  (0U)
+#define PDS_GPIO_INT_STAT_LEN  (31U)
+#define PDS_GPIO_INT_STAT_MSK  (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)
+#define PDS_GPIO_INT_STAT_UMSK (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS))
+
+/* 0x48 : PDS_RAM3 */
+#define PDS_RAM3_OFFSET       (0x48)
+#define PDS_CR_OCRAM_RET      PDS_CR_OCRAM_RET
+#define PDS_CR_OCRAM_RET_POS  (0U)
+#define PDS_CR_OCRAM_RET_LEN  (20U)
+#define PDS_CR_OCRAM_RET_MSK  (((1U << PDS_CR_OCRAM_RET_LEN) - 1) << PDS_CR_OCRAM_RET_POS)
+#define PDS_CR_OCRAM_RET_UMSK (~(((1U << PDS_CR_OCRAM_RET_LEN) - 1) << PDS_CR_OCRAM_RET_POS))
+
+/* 0x4C : PDS_RAM4 */
+#define PDS_RAM4_OFFSET       (0x4C)
+#define PDS_CR_OCRAM_SLP      PDS_CR_OCRAM_SLP
+#define PDS_CR_OCRAM_SLP_POS  (0U)
+#define PDS_CR_OCRAM_SLP_LEN  (20U)
+#define PDS_CR_OCRAM_SLP_MSK  (((1U << PDS_CR_OCRAM_SLP_LEN) - 1) << PDS_CR_OCRAM_SLP_POS)
+#define PDS_CR_OCRAM_SLP_UMSK (~(((1U << PDS_CR_OCRAM_SLP_LEN) - 1) << PDS_CR_OCRAM_SLP_POS))
+
+/* 0x114 : cpu_core_cfg1 */
+#define PDS_CPU_CORE_CFG1_OFFSET (0x114)
+#define PDS_REG_PLL_SEL          PDS_REG_PLL_SEL
+#define PDS_REG_PLL_SEL_POS      (4U)
+#define PDS_REG_PLL_SEL_LEN      (2U)
+#define PDS_REG_PLL_SEL_MSK      (((1U << PDS_REG_PLL_SEL_LEN) - 1) << PDS_REG_PLL_SEL_POS)
+#define PDS_REG_PLL_SEL_UMSK     (~(((1U << PDS_REG_PLL_SEL_LEN) - 1) << PDS_REG_PLL_SEL_POS))
+#define PDS_REG_MCU1_CLK_EN      PDS_REG_MCU1_CLK_EN
+#define PDS_REG_MCU1_CLK_EN_POS  (8U)
+#define PDS_REG_MCU1_CLK_EN_LEN  (1U)
+#define PDS_REG_MCU1_CLK_EN_MSK  (((1U << PDS_REG_MCU1_CLK_EN_LEN) - 1) << PDS_REG_MCU1_CLK_EN_POS)
+#define PDS_REG_MCU1_CLK_EN_UMSK (~(((1U << PDS_REG_MCU1_CLK_EN_LEN) - 1) << PDS_REG_MCU1_CLK_EN_POS))
+
+/* 0x148 : cpu_core_cfg14 */
+#define PDS_CPU_CORE_CFG14_OFFSET (0x148)
+#define PDS_E906_RST_ADDR         PDS_E906_RST_ADDR
+#define PDS_E906_RST_ADDR_POS     (0U)
+#define PDS_E906_RST_ADDR_LEN     (32U)
+#define PDS_E906_RST_ADDR_MSK     (((1U << PDS_E906_RST_ADDR_LEN) - 1) << PDS_E906_RST_ADDR_POS)
+#define PDS_E906_RST_ADDR_UMSK    (~(((1U << PDS_E906_RST_ADDR_LEN) - 1) << PDS_E906_RST_ADDR_POS))
+
+/* 0x300 : rc32m_ctrl0 */
+#define PDS_RC32M_CTRL0_OFFSET         (0x300)
+#define PDS_RC32M_CAL_DONE             PDS_RC32M_CAL_DONE
+#define PDS_RC32M_CAL_DONE_POS         (0U)
+#define PDS_RC32M_CAL_DONE_LEN         (1U)
+#define PDS_RC32M_CAL_DONE_MSK         (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
+#define PDS_RC32M_CAL_DONE_UMSK        (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
+#define PDS_RC32M_RDY                  PDS_RC32M_RDY
+#define PDS_RC32M_RDY_POS              (1U)
+#define PDS_RC32M_RDY_LEN              (1U)
+#define PDS_RC32M_RDY_MSK              (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
+#define PDS_RC32M_RDY_UMSK             (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
+#define PDS_RC32M_CAL_INPROGRESS       PDS_RC32M_CAL_INPROGRESS
+#define PDS_RC32M_CAL_INPROGRESS_POS   (2U)
+#define PDS_RC32M_CAL_INPROGRESS_LEN   (1U)
+#define PDS_RC32M_CAL_INPROGRESS_MSK   (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
+#define PDS_RC32M_CAL_INPROGRESS_UMSK  (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
+#define PDS_RC32M_CAL_DIV              PDS_RC32M_CAL_DIV
+#define PDS_RC32M_CAL_DIV_POS          (3U)
+#define PDS_RC32M_CAL_DIV_LEN          (2U)
+#define PDS_RC32M_CAL_DIV_MSK          (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
+#define PDS_RC32M_CAL_DIV_UMSK         (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
+#define PDS_RC32M_CAL_PRECHARGE        PDS_RC32M_CAL_PRECHARGE
+#define PDS_RC32M_CAL_PRECHARGE_POS    (5U)
+#define PDS_RC32M_CAL_PRECHARGE_LEN    (1U)
+#define PDS_RC32M_CAL_PRECHARGE_MSK    (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
+#define PDS_RC32M_CAL_PRECHARGE_UMSK   (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
+#define PDS_RC32M_DIG_CODE_FR_CAL      PDS_RC32M_DIG_CODE_FR_CAL
+#define PDS_RC32M_DIG_CODE_FR_CAL_POS  (6U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_LEN  (8U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_MSK  (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
+#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
+#define PDS_RC32M_ALLOW_CAL            PDS_RC32M_ALLOW_CAL
+#define PDS_RC32M_ALLOW_CAL_POS        (17U)
+#define PDS_RC32M_ALLOW_CAL_LEN        (1U)
+#define PDS_RC32M_ALLOW_CAL_MSK        (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
+#define PDS_RC32M_ALLOW_CAL_UMSK       (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
+#define PDS_RC32M_REFCLK_HALF          PDS_RC32M_REFCLK_HALF
+#define PDS_RC32M_REFCLK_HALF_POS      (18U)
+#define PDS_RC32M_REFCLK_HALF_LEN      (1U)
+#define PDS_RC32M_REFCLK_HALF_MSK      (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
+#define PDS_RC32M_REFCLK_HALF_UMSK     (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
+#define PDS_RC32M_EXT_CODE_EN          PDS_RC32M_EXT_CODE_EN
+#define PDS_RC32M_EXT_CODE_EN_POS      (19U)
+#define PDS_RC32M_EXT_CODE_EN_LEN      (1U)
+#define PDS_RC32M_EXT_CODE_EN_MSK      (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
+#define PDS_RC32M_EXT_CODE_EN_UMSK     (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
+#define PDS_RC32M_CAL_EN               PDS_RC32M_CAL_EN
+#define PDS_RC32M_CAL_EN_POS           (20U)
+#define PDS_RC32M_CAL_EN_LEN           (1U)
+#define PDS_RC32M_CAL_EN_MSK           (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
+#define PDS_RC32M_CAL_EN_UMSK          (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
+#define PDS_RC32M_PD                   PDS_RC32M_PD
+#define PDS_RC32M_PD_POS               (21U)
+#define PDS_RC32M_PD_LEN               (1U)
+#define PDS_RC32M_PD_MSK               (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
+#define PDS_RC32M_PD_UMSK              (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
+#define PDS_RC32M_CODE_FR_EXT          PDS_RC32M_CODE_FR_EXT
+#define PDS_RC32M_CODE_FR_EXT_POS      (22U)
+#define PDS_RC32M_CODE_FR_EXT_LEN      (8U)
+#define PDS_RC32M_CODE_FR_EXT_MSK      (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
+#define PDS_RC32M_CODE_FR_EXT_UMSK     (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))
+
+/* 0x304 : rc32m_ctrl1 */
+#define PDS_RC32M_CTRL1_OFFSET      (0x304)
+#define PDS_RC32M_TEST_EN           PDS_RC32M_TEST_EN
+#define PDS_RC32M_TEST_EN_POS       (0U)
+#define PDS_RC32M_TEST_EN_LEN       (1U)
+#define PDS_RC32M_TEST_EN_MSK       (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
+#define PDS_RC32M_TEST_EN_UMSK      (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
+#define PDS_RC32M_SOFT_RST          PDS_RC32M_SOFT_RST
+#define PDS_RC32M_SOFT_RST_POS      (1U)
+#define PDS_RC32M_SOFT_RST_LEN      (1U)
+#define PDS_RC32M_SOFT_RST_MSK      (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
+#define PDS_RC32M_SOFT_RST_UMSK     (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
+#define PDS_RC32M_CLK_SOFT_RST      PDS_RC32M_CLK_SOFT_RST
+#define PDS_RC32M_CLK_SOFT_RST_POS  (2U)
+#define PDS_RC32M_CLK_SOFT_RST_LEN  (1U)
+#define PDS_RC32M_CLK_SOFT_RST_MSK  (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
+#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
+#define PDS_RC32M_CLK_INV           PDS_RC32M_CLK_INV
+#define PDS_RC32M_CLK_INV_POS       (3U)
+#define PDS_RC32M_CLK_INV_LEN       (1U)
+#define PDS_RC32M_CLK_INV_MSK       (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
+#define PDS_RC32M_CLK_INV_UMSK      (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
+#define PDS_RC32M_CLK_FORCE_ON      PDS_RC32M_CLK_FORCE_ON
+#define PDS_RC32M_CLK_FORCE_ON_POS  (4U)
+#define PDS_RC32M_CLK_FORCE_ON_LEN  (1U)
+#define PDS_RC32M_CLK_FORCE_ON_MSK  (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
+#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
+#define PDS_RC32M_RESERVED          PDS_RC32M_RESERVED
+#define PDS_RC32M_RESERVED_POS      (24U)
+#define PDS_RC32M_RESERVED_LEN      (8U)
+#define PDS_RC32M_RESERVED_MSK      (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
+#define PDS_RC32M_RESERVED_UMSK     (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))
+
+/* 0x308 : rc32m_ctrl2 */
+#define PDS_RC32M_CTRL2_OFFSET      (0x308)
+#define PDS_RC32M_CODE_FR_EXT2      PDS_RC32M_CODE_FR_EXT2
+#define PDS_RC32M_CODE_FR_EXT2_POS  (22U)
+#define PDS_RC32M_CODE_FR_EXT2_LEN  (8U)
+#define PDS_RC32M_CODE_FR_EXT2_MSK  (((1U << PDS_RC32M_CODE_FR_EXT2_LEN) - 1) << PDS_RC32M_CODE_FR_EXT2_POS)
+#define PDS_RC32M_CODE_FR_EXT2_UMSK (~(((1U << PDS_RC32M_CODE_FR_EXT2_LEN) - 1) << PDS_RC32M_CODE_FR_EXT2_POS))
+#define PDS_RC32M_EXT_CODE_SEL      PDS_RC32M_EXT_CODE_SEL
+#define PDS_RC32M_EXT_CODE_SEL_POS  (31U)
+#define PDS_RC32M_EXT_CODE_SEL_LEN  (1U)
+#define PDS_RC32M_EXT_CODE_SEL_MSK  (((1U << PDS_RC32M_EXT_CODE_SEL_LEN) - 1) << PDS_RC32M_EXT_CODE_SEL_POS)
+#define PDS_RC32M_EXT_CODE_SEL_UMSK (~(((1U << PDS_RC32M_EXT_CODE_SEL_LEN) - 1) << PDS_RC32M_EXT_CODE_SEL_POS))
+
+/* 0x400 : pu_rst_clkpll */
+#define PDS_PU_RST_CLKPLL_OFFSET        (0x400)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG      PDS_CR_PDS_PU_CLKPLL_SFREG
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_POS  (9U)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_LEN  (1U)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_MSK  (((1U << PDS_CR_PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_SFREG_POS)
+#define PDS_CR_PDS_PU_CLKPLL_SFREG_UMSK (~(((1U << PDS_CR_PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_SFREG_POS))
+#define PDS_CR_PDS_PU_CLKPLL            PDS_CR_PDS_PU_CLKPLL
+#define PDS_CR_PDS_PU_CLKPLL_POS        (10U)
+#define PDS_CR_PDS_PU_CLKPLL_LEN        (1U)
+#define PDS_CR_PDS_PU_CLKPLL_MSK        (((1U << PDS_CR_PDS_PU_CLKPLL_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_POS)
+#define PDS_CR_PDS_PU_CLKPLL_UMSK       (~(((1U << PDS_CR_PDS_PU_CLKPLL_LEN) - 1) << PDS_CR_PDS_PU_CLKPLL_POS))
+
+/* 0x500 : usb_ctl */
+#define PDS_USB_CTL_OFFSET          (0x500)
+#define PDS_REG_USB_SW_RST_N        PDS_REG_USB_SW_RST_N
+#define PDS_REG_USB_SW_RST_N_POS    (0U)
+#define PDS_REG_USB_SW_RST_N_LEN    (1U)
+#define PDS_REG_USB_SW_RST_N_MSK    (((1U << PDS_REG_USB_SW_RST_N_LEN) - 1) << PDS_REG_USB_SW_RST_N_POS)
+#define PDS_REG_USB_SW_RST_N_UMSK   (~(((1U << PDS_REG_USB_SW_RST_N_LEN) - 1) << PDS_REG_USB_SW_RST_N_POS))
+#define PDS_REG_USB_EXT_SUSP_N      PDS_REG_USB_EXT_SUSP_N
+#define PDS_REG_USB_EXT_SUSP_N_POS  (1U)
+#define PDS_REG_USB_EXT_SUSP_N_LEN  (1U)
+#define PDS_REG_USB_EXT_SUSP_N_MSK  (((1U << PDS_REG_USB_EXT_SUSP_N_LEN) - 1) << PDS_REG_USB_EXT_SUSP_N_POS)
+#define PDS_REG_USB_EXT_SUSP_N_UMSK (~(((1U << PDS_REG_USB_EXT_SUSP_N_LEN) - 1) << PDS_REG_USB_EXT_SUSP_N_POS))
+#define PDS_REG_USB_WAKEUP          PDS_REG_USB_WAKEUP
+#define PDS_REG_USB_WAKEUP_POS      (2U)
+#define PDS_REG_USB_WAKEUP_LEN      (1U)
+#define PDS_REG_USB_WAKEUP_MSK      (((1U << PDS_REG_USB_WAKEUP_LEN) - 1) << PDS_REG_USB_WAKEUP_POS)
+#define PDS_REG_USB_WAKEUP_UMSK     (~(((1U << PDS_REG_USB_WAKEUP_LEN) - 1) << PDS_REG_USB_WAKEUP_POS))
+#define PDS_REG_USB_L1_WAKEUP       PDS_REG_USB_L1_WAKEUP
+#define PDS_REG_USB_L1_WAKEUP_POS   (3U)
+#define PDS_REG_USB_L1_WAKEUP_LEN   (1U)
+#define PDS_REG_USB_L1_WAKEUP_MSK   (((1U << PDS_REG_USB_L1_WAKEUP_LEN) - 1) << PDS_REG_USB_L1_WAKEUP_POS)
+#define PDS_REG_USB_L1_WAKEUP_UMSK  (~(((1U << PDS_REG_USB_L1_WAKEUP_LEN) - 1) << PDS_REG_USB_L1_WAKEUP_POS))
+#define PDS_REG_USB_DRVBUS_POL      PDS_REG_USB_DRVBUS_POL
+#define PDS_REG_USB_DRVBUS_POL_POS  (4U)
+#define PDS_REG_USB_DRVBUS_POL_LEN  (1U)
+#define PDS_REG_USB_DRVBUS_POL_MSK  (((1U << PDS_REG_USB_DRVBUS_POL_LEN) - 1) << PDS_REG_USB_DRVBUS_POL_POS)
+#define PDS_REG_USB_DRVBUS_POL_UMSK (~(((1U << PDS_REG_USB_DRVBUS_POL_LEN) - 1) << PDS_REG_USB_DRVBUS_POL_POS))
+#define PDS_REG_USB_IDDIG           PDS_REG_USB_IDDIG
+#define PDS_REG_USB_IDDIG_POS       (5U)
+#define PDS_REG_USB_IDDIG_LEN       (1U)
+#define PDS_REG_USB_IDDIG_MSK       (((1U << PDS_REG_USB_IDDIG_LEN) - 1) << PDS_REG_USB_IDDIG_POS)
+#define PDS_REG_USB_IDDIG_UMSK      (~(((1U << PDS_REG_USB_IDDIG_LEN) - 1) << PDS_REG_USB_IDDIG_POS))
+
+/* 0x504 : usb_phy_ctrl */
+#define PDS_USB_PHY_CTRL_OFFSET        (0x504)
+#define PDS_REG_USB_PHY_PONRST         PDS_REG_USB_PHY_PONRST
+#define PDS_REG_USB_PHY_PONRST_POS     (0U)
+#define PDS_REG_USB_PHY_PONRST_LEN     (1U)
+#define PDS_REG_USB_PHY_PONRST_MSK     (((1U << PDS_REG_USB_PHY_PONRST_LEN) - 1) << PDS_REG_USB_PHY_PONRST_POS)
+#define PDS_REG_USB_PHY_PONRST_UMSK    (~(((1U << PDS_REG_USB_PHY_PONRST_LEN) - 1) << PDS_REG_USB_PHY_PONRST_POS))
+#define PDS_REG_USB_PHY_OSCOUTEN       PDS_REG_USB_PHY_OSCOUTEN
+#define PDS_REG_USB_PHY_OSCOUTEN_POS   (1U)
+#define PDS_REG_USB_PHY_OSCOUTEN_LEN   (1U)
+#define PDS_REG_USB_PHY_OSCOUTEN_MSK   (((1U << PDS_REG_USB_PHY_OSCOUTEN_LEN) - 1) << PDS_REG_USB_PHY_OSCOUTEN_POS)
+#define PDS_REG_USB_PHY_OSCOUTEN_UMSK  (~(((1U << PDS_REG_USB_PHY_OSCOUTEN_LEN) - 1) << PDS_REG_USB_PHY_OSCOUTEN_POS))
+#define PDS_REG_USB_PHY_XTLSEL         PDS_REG_USB_PHY_XTLSEL
+#define PDS_REG_USB_PHY_XTLSEL_POS     (2U)
+#define PDS_REG_USB_PHY_XTLSEL_LEN     (2U)
+#define PDS_REG_USB_PHY_XTLSEL_MSK     (((1U << PDS_REG_USB_PHY_XTLSEL_LEN) - 1) << PDS_REG_USB_PHY_XTLSEL_POS)
+#define PDS_REG_USB_PHY_XTLSEL_UMSK    (~(((1U << PDS_REG_USB_PHY_XTLSEL_LEN) - 1) << PDS_REG_USB_PHY_XTLSEL_POS))
+#define PDS_REG_USB_PHY_OUTCLKSEL      PDS_REG_USB_PHY_OUTCLKSEL
+#define PDS_REG_USB_PHY_OUTCLKSEL_POS  (4U)
+#define PDS_REG_USB_PHY_OUTCLKSEL_LEN  (1U)
+#define PDS_REG_USB_PHY_OUTCLKSEL_MSK  (((1U << PDS_REG_USB_PHY_OUTCLKSEL_LEN) - 1) << PDS_REG_USB_PHY_OUTCLKSEL_POS)
+#define PDS_REG_USB_PHY_OUTCLKSEL_UMSK (~(((1U << PDS_REG_USB_PHY_OUTCLKSEL_LEN) - 1) << PDS_REG_USB_PHY_OUTCLKSEL_POS))
+#define PDS_REG_USB_PHY_PLLALIV        PDS_REG_USB_PHY_PLLALIV
+#define PDS_REG_USB_PHY_PLLALIV_POS    (5U)
+#define PDS_REG_USB_PHY_PLLALIV_LEN    (1U)
+#define PDS_REG_USB_PHY_PLLALIV_MSK    (((1U << PDS_REG_USB_PHY_PLLALIV_LEN) - 1) << PDS_REG_USB_PHY_PLLALIV_POS)
+#define PDS_REG_USB_PHY_PLLALIV_UMSK   (~(((1U << PDS_REG_USB_PHY_PLLALIV_LEN) - 1) << PDS_REG_USB_PHY_PLLALIV_POS))
+#define PDS_REG_PU_USB20_PSW           PDS_REG_PU_USB20_PSW
+#define PDS_REG_PU_USB20_PSW_POS       (6U)
+#define PDS_REG_PU_USB20_PSW_LEN       (1U)
+#define PDS_REG_PU_USB20_PSW_MSK       (((1U << PDS_REG_PU_USB20_PSW_LEN) - 1) << PDS_REG_PU_USB20_PSW_POS)
+#define PDS_REG_PU_USB20_PSW_UMSK      (~(((1U << PDS_REG_PU_USB20_PSW_LEN) - 1) << PDS_REG_PU_USB20_PSW_POS))
+
+struct pds_reg {
+    /* 0x0 : PDS_CTL */
+    union {
+        struct {
+            uint32_t pds_start_ps                 : 1; /* [    0],        w1p,        0x0 */
+            uint32_t cr_sleep_forever             : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_xtal_force_off            : 1; /* [    2],        r/w,        0x0 */
+            uint32_t cr_pds_wifi_save_state       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t cr_pds_pd_ldo11              : 1; /* [    4],        r/w,        0x0 */
+            uint32_t cr_pds_pd_bg_sys             : 1; /* [    5],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_gpio_ie_pu_pd    : 1; /* [    6],        r/w,        0x0 */
+            uint32_t cr_pds_pd_dcdc18             : 1; /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_gate_clk              : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_pds_mem_stby              : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cr_pds_glb_reg_reset_protect : 1; /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_iso_en                : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_pds_wait_xtal_rdy         : 1; /* [   12],        r/w,        0x0 */
+            uint32_t cr_pds_pwr_off               : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_pd_xtal               : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_ctrl_soc_enb          : 1; /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_rst_soc               : 1; /* [   16],        r/w,        0x0 */
+            uint32_t cr_pds_rc32m_off_dis         : 1; /* [   17],        r/w,        0x0 */
+            uint32_t cr_pds_ldo11_vsel_en         : 1; /* [   18],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_usbpll_pd        : 1; /* [   19],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_aupll_pd         : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21                  : 1; /* [   21],       rsvd,        0x0 */
+            uint32_t cr_pds_ctrl_wifipll_pd       : 1; /* [   22],        r/w,        0x0 */
+            uint32_t cr_pds_ldo11_vol             : 5; /* [27:23],        r/w,        0x8 */
+            uint32_t cr_pds_ctrl_rf               : 2; /* [29:28],        r/w,        0x1 */
+            uint32_t cr_pds_start_use_tbtt_sleep  : 1; /* [   30],        r/w,        0x0 */
+            uint32_t cr_pds_gpio_iso_mode         : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL;
+
+    /* 0x4 : PDS_TIME1 */
+    union {
+        struct {
+            uint32_t cr_sleep_duration : 32; /* [31: 0],        r/w,      0xca8 */
+        } BF;
+        uint32_t WORD;
+    } PDS_TIME1;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[4];
+
+    /* 0xC : PDS_INT */
+    union {
+        struct {
+            uint32_t ro_pds_wake_int                  : 1;  /* [    0],          r,        0x0 */
+            uint32_t ro_pds_rf_done_int               : 1;  /* [    1],          r,        0x0 */
+            uint32_t ro_pds_wifi_tbtt_sleep_irq       : 1;  /* [    2],          r,        0x0 */
+            uint32_t ro_pds_wifi_tbtt_wakeup_irq      : 1;  /* [    3],          r,        0x0 */
+            uint32_t cr_pds_wake_int_mask             : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t cr_pds_rf_done_int_mask          : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t cr_pds_wifi_tbtt_sleep_irq_mask  : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t cr_pds_wifi_tbtt_wakeup_irq_mask : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_int_clr                   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9                       : 1;  /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_wakeup_src_en             : 10; /* [19:10],        r/w,      0x3ff */
+            uint32_t reserved_20                      : 1;  /* [   20],       rsvd,        0x0 */
+            uint32_t ro_pds_wakeup_event              : 10; /* [30:21],          r,        0x0 */
+            uint32_t reserved_31                      : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_INT;
+
+    /* 0x10 : PDS_CTL2 */
+    union {
+        struct {
+            uint32_t cr_pds_force_np_pwr_off   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1                : 1;  /* [    1],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_pwr_off   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_pwr_off  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_iso_en    : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5                : 1;  /* [    5],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_iso_en    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_iso_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_pds_rst   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9                : 1;  /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_pds_rst   : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_pds_rst  : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_mem_stby  : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13               : 1;  /* [   13],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_mem_stby  : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_mem_stby : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_gate_clk  : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17               : 1;  /* [   17],       rsvd,        0x0 */
+            uint32_t cr_pds_force_wb_gate_clk  : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_gate_clk : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20_31            : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL2;
+
+    /* 0x14 : PDS_CTL3 */
+    union {
+        struct {
+            uint32_t reserved_0                 : 1;  /* [    0],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pwr_off  : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3               : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_iso_en   : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_6               : 2;  /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pds_rst  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_9               : 2;  /* [ 9: 8],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_mem_stby : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_12             : 2;  /* [12:11],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_gate_clk : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_23             : 10; /* [23:14],       rsvd,        0x0 */
+            uint32_t cr_pds_np_iso_en           : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_26             : 2;  /* [26:25],       rsvd,        0x0 */
+            uint32_t cr_pds_wb_iso_en           : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t reserved_28                : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t cr_pds_usb_iso_en          : 1;  /* [   29],        r/w,        0x1 */
+            uint32_t cr_pds_misc_iso_en         : 1;  /* [   30],        r/w,        0x1 */
+            uint32_t reserved_31                : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL3;
+
+    /* 0x18 : PDS_CTL4 */
+    union {
+        struct {
+            uint32_t cr_pds_np_pwr_off    : 1; /* [    0],        r/w,        0x1 */
+            uint32_t cr_pds_np_reset      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t cr_pds_np_mem_stby   : 1; /* [    2],        r/w,        0x1 */
+            uint32_t cr_pds_np_gate_clk   : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_11        : 8; /* [11: 4],       rsvd,        0x0 */
+            uint32_t cr_pds_wb_pwr_off    : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_pds_wb_reset      : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_wb_mem_stby   : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_wb_gate_clk   : 1; /* [   15],        r/w,        0x1 */
+            uint32_t reserved_16_19       : 4; /* [19:16],       rsvd,        0x0 */
+            uint32_t cr_pds_usb_pwr_off   : 1; /* [   20],        r/w,        0x1 */
+            uint32_t cr_pds_usb_reset     : 1; /* [   21],        r/w,        0x1 */
+            uint32_t cr_pds_usb_mem_stby  : 1; /* [   22],        r/w,        0x1 */
+            uint32_t cr_pds_usb_gate_clk  : 1; /* [   23],        r/w,        0x1 */
+            uint32_t cr_pds_misc_pwr_off  : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cr_pds_misc_reset    : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cr_pds_misc_mem_stby : 1; /* [   26],        r/w,        0x1 */
+            uint32_t cr_pds_misc_gate_clk : 1; /* [   27],        r/w,        0x1 */
+            uint32_t reserved_28_31       : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL4;
+
+    /* 0x1C : pds_stat */
+    union {
+        struct {
+            uint32_t ro_pds_state        : 5;  /* [ 4: 0],          r,        0x0 */
+            uint32_t reserved_5_7        : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t ro_pds_rf_state     : 5;  /* [12: 8],          r,        0x0 */
+            uint32_t reserved_13_23      : 11; /* [23:13],       rsvd,        0x0 */
+            uint32_t pds_reset_event     : 3;  /* [26:24],          r,        0x0 */
+            uint32_t reserved_27_30      : 4;  /* [30:27],       rsvd,        0x0 */
+            uint32_t pds_clr_reset_event : 1;  /* [   31],        w1c,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_stat;
+
+    /* 0x20 : pds_ram1 */
+    union {
+        struct {
+            uint32_t reserved_0_7             : 8; /* [ 7: 0],       rsvd,        0x0 */
+            uint32_t cr_pds_ram_clk_cnt       : 6; /* [13: 8],        r/w,        0x8 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t cr_pds_ram_clk2_cnt      : 6; /* [21:16],        r/w,       0x18 */
+            uint32_t reserved_22_23           : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t cr_pds_ctrl_np_ram_clk   : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reserved_25              : 1; /* [   25],       rsvd,        0x0 */
+            uint32_t cr_pds_ctrl_wb_ram_clk   : 1; /* [   26],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_usb_ram_clk  : 1; /* [   27],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_misc_ram_clk : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29              : 1; /* [   29],       rsvd,        0x0 */
+            uint32_t cr_pds_ctrl_ram_clk2     : 1; /* [   30],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_ram_clk      : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_ram1;
+
+    /* 0x24 : PDS_CTL5 */
+    union {
+        struct {
+            uint32_t cr_np_wfi_mask      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t cr_pds_pad_od_en    : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t cr_pds_ctrl_usb33   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t cr_pds_pd_ldo18io   : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_keep_en : 3;  /* [18:16],        r/w,        0x7 */
+            uint32_t reserved_19_31      : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL5;
+
+    /* 0x28 : PDS_RAM2 */
+    union {
+        struct {
+            uint32_t cr_wram_slp    : 10; /* [ 9: 0],        r/w,        0x0 */
+            uint32_t cr_wram_ret    : 10; /* [19:10],        r/w,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_RAM2;
+
+    /* 0x2c  reserved */
+    uint8_t RESERVED0x2c[4];
+
+    /* 0x30 : pds_gpio_i_set */
+    union {
+        struct {
+            uint32_t cr_pds_gpio_ie_set : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2         : 1;  /* [    2],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_pd_set : 2;  /* [ 4: 3],        r/w,        0x0 */
+            uint32_t reserved_5         : 1;  /* [    5],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_pu_set : 2;  /* [ 7: 6],        r/w,        0x0 */
+            uint32_t reserved_8_31      : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_i_set;
+
+    /* 0x34 : pds_gpio_pd_set */
+    union {
+        struct {
+            uint32_t cr_pds_gpio_set_int_mask : 31; /* [30: 0],        r/w, 0x7fffffff */
+            uint32_t reserved_31              : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_pd_set;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[8];
+
+    /* 0x40 : pds_gpio_int */
+    union {
+        struct {
+            uint32_t reserved_0_1           : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t pds_gpio_set1_int_clr  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3             : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t pds_gpio_set1_int_mode : 4; /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_9           : 2; /* [ 9: 8],       rsvd,        0x0 */
+            uint32_t pds_gpio_set2_int_clr  : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11            : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t pds_gpio_set2_int_mode : 4; /* [15:12],        r/w,        0x0 */
+            uint32_t reserved_16_17         : 2; /* [17:16],       rsvd,        0x0 */
+            uint32_t pds_gpio_set3_int_clr  : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19            : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t pds_gpio_set3_int_mode : 4; /* [23:20],        r/w,        0x0 */
+            uint32_t reserved_24_25         : 2; /* [25:24],       rsvd,        0x0 */
+            uint32_t pds_gpio_set4_int_clr  : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27            : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t pds_gpio_set4_int_mode : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_int;
+
+    /* 0x44 : pds_gpio_stat */
+    union {
+        struct {
+            uint32_t pds_gpio_int_stat : 31; /* [30: 0],          r,        0x0 */
+            uint32_t reserved_31       : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_stat;
+
+    /* 0x48 : PDS_RAM3 */
+    union {
+        struct {
+            uint32_t cr_ocram_ret   : 20; /* [19: 0],        r/w,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_RAM3;
+
+    /* 0x4C : PDS_RAM4 */
+    union {
+        struct {
+            uint32_t cr_ocram_slp   : 20; /* [19: 0],        r/w,        0x0 */
+            uint32_t reserved_20_31 : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_RAM4;
+
+    /* 0x50  reserved */
+    uint8_t RESERVED0x50[196];
+
+    /* 0x114 : cpu_core_cfg1 */
+    union {
+        struct {
+            uint32_t reserved_0_3    : 4;  /* [ 3: 0],       rsvd,        0x0 */
+            uint32_t reg_pll_sel     : 2;  /* [ 5: 4],        r/w,        0x3 */
+            uint32_t reserved_6_7    : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_mcu1_clk_en : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31   : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cpu_core_cfg1;
+
+    /* 0x118  reserved */
+    uint8_t RESERVED0x118[48];
+
+    /* 0x148 : cpu_core_cfg14 */
+    union {
+        struct {
+            uint32_t e906_rst_addr : 32; /* [31: 0],        r/w, 0x90000000 */
+        } BF;
+        uint32_t WORD;
+    } cpu_core_cfg14;
+
+    /* 0x14c  reserved */
+    uint8_t RESERVED0x14c[436];
+
+    /* 0x300 : rc32m_ctrl0 */
+    union {
+        struct {
+            uint32_t rc32m_cal_done        : 1; /* [    0],          r,        0x0 */
+            uint32_t rc32m_rdy             : 1; /* [    1],          r,        0x0 */
+            uint32_t rc32m_cal_inprogress  : 1; /* [    2],          r,        0x0 */
+            uint32_t rc32m_cal_div         : 2; /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32m_cal_precharge   : 1; /* [    5],          r,        0x0 */
+            uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6],          r,        0x0 */
+            uint32_t reserved_14_16        : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t rc32m_allow_cal       : 1; /* [   17],        r/w,        0x0 */
+            uint32_t rc32m_refclk_half     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t rc32m_ext_code_en     : 1; /* [   19],        r/w,        0x1 */
+            uint32_t rc32m_cal_en          : 1; /* [   20],        r/w,        0x0 */
+            uint32_t rc32m_pd              : 1; /* [   21],        r/w,        0x0 */
+            uint32_t rc32m_code_fr_ext     : 8; /* [29:22],        r/w,       0x60 */
+            uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl0;
+
+    /* 0x304 : rc32m_ctrl1 */
+    union {
+        struct {
+            uint32_t rc32m_test_en      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t rc32m_soft_rst     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rc32m_clk_soft_rst : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t rc32m_clk_inv      : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t rc32m_clk_force_on : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_23      : 19; /* [23: 5],       rsvd,        0x0 */
+            uint32_t rc32m_reserved     : 8;  /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl1;
+
+    /* 0x308 : rc32m_ctrl2 */
+    union {
+        struct {
+            uint32_t reserved_0_21      : 22; /* [21: 0],       rsvd,        0x0 */
+            uint32_t rc32m_code_fr_ext2 : 8;  /* [29:22],        r/w,       0x60 */
+            uint32_t reserved_30        : 1;  /* [   30],       rsvd,        0x0 */
+            uint32_t rc32m_ext_code_sel : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl2;
+
+    /* 0x30c  reserved */
+    uint8_t RESERVED0x30c[244];
+
+    /* 0x400 : pu_rst_clkpll */
+    union {
+        struct {
+            uint32_t reserved_0_8           : 9;  /* [ 8: 0],       rsvd,        0x0 */
+            uint32_t cr_pds_pu_clkpll_sfreg : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t cr_pds_pu_clkpll       : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_31         : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pu_rst_clkpll;
+
+    /* 0x404  reserved */
+    uint8_t RESERVED0x404[252];
+
+    /* 0x500 : usb_ctl */
+    union {
+        struct {
+            uint32_t reg_usb_sw_rst_n   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_usb_ext_susp_n : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_usb_wakeup     : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reg_usb_l1_wakeup  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reg_usb_drvbus_pol : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_usb_iddig      : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_31      : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_ctl;
+
+    /* 0x504 : usb_phy_ctrl */
+    union {
+        struct {
+            uint32_t reg_usb_phy_ponrst    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_usb_phy_oscouten  : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_usb_phy_xtlsel    : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_usb_phy_outclksel : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_usb_phy_pllaliv   : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reg_pu_usb20_psw      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7_31         : 25; /* [31: 7],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_phy_ctrl;
+};
+
+typedef volatile struct pds_reg pds_reg_t;
+
+#endif /* __PDS_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/psram_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/psram_reg.h
new file mode 100755
index 0000000000..c0c89c752d
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/psram_reg.h
@@ -0,0 +1,1377 @@
+/**
+  ******************************************************************************
+  * @file    psram_reg.h
+  * @version V1.0
+  * @date    2021-11-09
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PSRAM_REG_H__
+#define __PSRAM_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : psram_configure */
+#define PSRAM_CONFIGURE_OFFSET        (0x0)
+#define PSRAM_REG_VENDOR_SEL          PSRAM_REG_VENDOR_SEL
+#define PSRAM_REG_VENDOR_SEL_POS      (0U)
+#define PSRAM_REG_VENDOR_SEL_LEN      (3U)
+#define PSRAM_REG_VENDOR_SEL_MSK      (((1U << PSRAM_REG_VENDOR_SEL_LEN) - 1) << PSRAM_REG_VENDOR_SEL_POS)
+#define PSRAM_REG_VENDOR_SEL_UMSK     (~(((1U << PSRAM_REG_VENDOR_SEL_LEN) - 1) << PSRAM_REG_VENDOR_SEL_POS))
+#define PSRAM_REG_AP_MR               PSRAM_REG_AP_MR
+#define PSRAM_REG_AP_MR_POS           (4U)
+#define PSRAM_REG_AP_MR_LEN           (3U)
+#define PSRAM_REG_AP_MR_MSK           (((1U << PSRAM_REG_AP_MR_LEN) - 1) << PSRAM_REG_AP_MR_POS)
+#define PSRAM_REG_AP_MR_UMSK          (~(((1U << PSRAM_REG_AP_MR_LEN) - 1) << PSRAM_REG_AP_MR_POS))
+#define PSRAM_REG_WB_REG_SEL          PSRAM_REG_WB_REG_SEL
+#define PSRAM_REG_WB_REG_SEL_POS      (8U)
+#define PSRAM_REG_WB_REG_SEL_LEN      (3U)
+#define PSRAM_REG_WB_REG_SEL_MSK      (((1U << PSRAM_REG_WB_REG_SEL_LEN) - 1) << PSRAM_REG_WB_REG_SEL_POS)
+#define PSRAM_REG_WB_REG_SEL_UMSK     (~(((1U << PSRAM_REG_WB_REG_SEL_LEN) - 1) << PSRAM_REG_WB_REG_SEL_POS))
+#define PSRAM_REG_CONFIG_W_PUSLE      PSRAM_REG_CONFIG_W_PUSLE
+#define PSRAM_REG_CONFIG_W_PUSLE_POS  (12U)
+#define PSRAM_REG_CONFIG_W_PUSLE_LEN  (1U)
+#define PSRAM_REG_CONFIG_W_PUSLE_MSK  (((1U << PSRAM_REG_CONFIG_W_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_W_PUSLE_POS)
+#define PSRAM_REG_CONFIG_W_PUSLE_UMSK (~(((1U << PSRAM_REG_CONFIG_W_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_W_PUSLE_POS))
+#define PSRAM_REG_CONFIG_R_PUSLE      PSRAM_REG_CONFIG_R_PUSLE
+#define PSRAM_REG_CONFIG_R_PUSLE_POS  (13U)
+#define PSRAM_REG_CONFIG_R_PUSLE_LEN  (1U)
+#define PSRAM_REG_CONFIG_R_PUSLE_MSK  (((1U << PSRAM_REG_CONFIG_R_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_R_PUSLE_POS)
+#define PSRAM_REG_CONFIG_R_PUSLE_UMSK (~(((1U << PSRAM_REG_CONFIG_R_PUSLE_LEN) - 1) << PSRAM_REG_CONFIG_R_PUSLE_POS))
+#define PSRAM_STS_CONFIG_W_DONE       PSRAM_STS_CONFIG_W_DONE
+#define PSRAM_STS_CONFIG_W_DONE_POS   (14U)
+#define PSRAM_STS_CONFIG_W_DONE_LEN   (1U)
+#define PSRAM_STS_CONFIG_W_DONE_MSK   (((1U << PSRAM_STS_CONFIG_W_DONE_LEN) - 1) << PSRAM_STS_CONFIG_W_DONE_POS)
+#define PSRAM_STS_CONFIG_W_DONE_UMSK  (~(((1U << PSRAM_STS_CONFIG_W_DONE_LEN) - 1) << PSRAM_STS_CONFIG_W_DONE_POS))
+#define PSRAM_STS_CONFIG_R_DONE       PSRAM_STS_CONFIG_R_DONE
+#define PSRAM_STS_CONFIG_R_DONE_POS   (15U)
+#define PSRAM_STS_CONFIG_R_DONE_LEN   (1U)
+#define PSRAM_STS_CONFIG_R_DONE_MSK   (((1U << PSRAM_STS_CONFIG_R_DONE_LEN) - 1) << PSRAM_STS_CONFIG_R_DONE_POS)
+#define PSRAM_STS_CONFIG_R_DONE_UMSK  (~(((1U << PSRAM_STS_CONFIG_R_DONE_LEN) - 1) << PSRAM_STS_CONFIG_R_DONE_POS))
+#define PSRAM_REG_CONFIG_REQ          PSRAM_REG_CONFIG_REQ
+#define PSRAM_REG_CONFIG_REQ_POS      (16U)
+#define PSRAM_REG_CONFIG_REQ_LEN      (1U)
+#define PSRAM_REG_CONFIG_REQ_MSK      (((1U << PSRAM_REG_CONFIG_REQ_LEN) - 1) << PSRAM_REG_CONFIG_REQ_POS)
+#define PSRAM_REG_CONFIG_REQ_UMSK     (~(((1U << PSRAM_REG_CONFIG_REQ_LEN) - 1) << PSRAM_REG_CONFIG_REQ_POS))
+#define PSRAM_REG_CONFIG_GNT          PSRAM_REG_CONFIG_GNT
+#define PSRAM_REG_CONFIG_GNT_POS      (17U)
+#define PSRAM_REG_CONFIG_GNT_LEN      (1U)
+#define PSRAM_REG_CONFIG_GNT_MSK      (((1U << PSRAM_REG_CONFIG_GNT_LEN) - 1) << PSRAM_REG_CONFIG_GNT_POS)
+#define PSRAM_REG_CONFIG_GNT_UMSK     (~(((1U << PSRAM_REG_CONFIG_GNT_LEN) - 1) << PSRAM_REG_CONFIG_GNT_POS))
+#define PSRAM_REG_X16_MODE            PSRAM_REG_X16_MODE
+#define PSRAM_REG_X16_MODE_POS        (18U)
+#define PSRAM_REG_X16_MODE_LEN        (1U)
+#define PSRAM_REG_X16_MODE_MSK        (((1U << PSRAM_REG_X16_MODE_LEN) - 1) << PSRAM_REG_X16_MODE_POS)
+#define PSRAM_REG_X16_MODE_UMSK       (~(((1U << PSRAM_REG_X16_MODE_LEN) - 1) << PSRAM_REG_X16_MODE_POS))
+#define PSRAM_REG_WB_HYPER3           PSRAM_REG_WB_HYPER3
+#define PSRAM_REG_WB_HYPER3_POS       (19U)
+#define PSRAM_REG_WB_HYPER3_LEN       (1U)
+#define PSRAM_REG_WB_HYPER3_MSK       (((1U << PSRAM_REG_WB_HYPER3_LEN) - 1) << PSRAM_REG_WB_HYPER3_POS)
+#define PSRAM_REG_WB_HYPER3_UMSK      (~(((1U << PSRAM_REG_WB_HYPER3_LEN) - 1) << PSRAM_REG_WB_HYPER3_POS))
+#define PSRAM_REG_PCK_S_DIV           PSRAM_REG_PCK_S_DIV
+#define PSRAM_REG_PCK_S_DIV_POS       (20U)
+#define PSRAM_REG_PCK_S_DIV_LEN       (3U)
+#define PSRAM_REG_PCK_S_DIV_MSK       (((1U << PSRAM_REG_PCK_S_DIV_LEN) - 1) << PSRAM_REG_PCK_S_DIV_POS)
+#define PSRAM_REG_PCK_S_DIV_UMSK      (~(((1U << PSRAM_REG_PCK_S_DIV_LEN) - 1) << PSRAM_REG_PCK_S_DIV_POS))
+#define PSRAM_REG_CLKN_FREE           PSRAM_REG_CLKN_FREE
+#define PSRAM_REG_CLKN_FREE_POS       (23U)
+#define PSRAM_REG_CLKN_FREE_LEN       (1U)
+#define PSRAM_REG_CLKN_FREE_MSK       (((1U << PSRAM_REG_CLKN_FREE_LEN) - 1) << PSRAM_REG_CLKN_FREE_POS)
+#define PSRAM_REG_CLKN_FREE_UMSK      (~(((1U << PSRAM_REG_CLKN_FREE_LEN) - 1) << PSRAM_REG_CLKN_FREE_POS))
+#define PSRAM_REG_LINEAR_BND_B        PSRAM_REG_LINEAR_BND_B
+#define PSRAM_REG_LINEAR_BND_B_POS    (28U)
+#define PSRAM_REG_LINEAR_BND_B_LEN    (4U)
+#define PSRAM_REG_LINEAR_BND_B_MSK    (((1U << PSRAM_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_REG_LINEAR_BND_B_POS)
+#define PSRAM_REG_LINEAR_BND_B_UMSK   (~(((1U << PSRAM_REG_LINEAR_BND_B_LEN) - 1) << PSRAM_REG_LINEAR_BND_B_POS))
+
+/* 0x4 : psram_manual_control */
+#define PSRAM_MANUAL_CONTROL_OFFSET    (0x4)
+#define PSRAM_REG_WC_SW                PSRAM_REG_WC_SW
+#define PSRAM_REG_WC_SW_POS            (0U)
+#define PSRAM_REG_WC_SW_LEN            (7U)
+#define PSRAM_REG_WC_SW_MSK            (((1U << PSRAM_REG_WC_SW_LEN) - 1) << PSRAM_REG_WC_SW_POS)
+#define PSRAM_REG_WC_SW_UMSK           (~(((1U << PSRAM_REG_WC_SW_LEN) - 1) << PSRAM_REG_WC_SW_POS))
+#define PSRAM_REG_WC_SW_EN             PSRAM_REG_WC_SW_EN
+#define PSRAM_REG_WC_SW_EN_POS         (8U)
+#define PSRAM_REG_WC_SW_EN_LEN         (1U)
+#define PSRAM_REG_WC_SW_EN_MSK         (((1U << PSRAM_REG_WC_SW_EN_LEN) - 1) << PSRAM_REG_WC_SW_EN_POS)
+#define PSRAM_REG_WC_SW_EN_UMSK        (~(((1U << PSRAM_REG_WC_SW_EN_LEN) - 1) << PSRAM_REG_WC_SW_EN_POS))
+#define PSRAM_REG_STATE_HOLD_TICK      PSRAM_REG_STATE_HOLD_TICK
+#define PSRAM_REG_STATE_HOLD_TICK_POS  (9U)
+#define PSRAM_REG_STATE_HOLD_TICK_LEN  (1U)
+#define PSRAM_REG_STATE_HOLD_TICK_MSK  (((1U << PSRAM_REG_STATE_HOLD_TICK_LEN) - 1) << PSRAM_REG_STATE_HOLD_TICK_POS)
+#define PSRAM_REG_STATE_HOLD_TICK_UMSK (~(((1U << PSRAM_REG_STATE_HOLD_TICK_LEN) - 1) << PSRAM_REG_STATE_HOLD_TICK_POS))
+#define PSRAM_REG_DQS_LATCH_INV        PSRAM_REG_DQS_LATCH_INV
+#define PSRAM_REG_DQS_LATCH_INV_POS    (10U)
+#define PSRAM_REG_DQS_LATCH_INV_LEN    (1U)
+#define PSRAM_REG_DQS_LATCH_INV_MSK    (((1U << PSRAM_REG_DQS_LATCH_INV_LEN) - 1) << PSRAM_REG_DQS_LATCH_INV_POS)
+#define PSRAM_REG_DQS_LATCH_INV_UMSK   (~(((1U << PSRAM_REG_DQS_LATCH_INV_LEN) - 1) << PSRAM_REG_DQS_LATCH_INV_POS))
+#define PSRAM_REG_WB_BL2_MASK          PSRAM_REG_WB_BL2_MASK
+#define PSRAM_REG_WB_BL2_MASK_POS      (11U)
+#define PSRAM_REG_WB_BL2_MASK_LEN      (1U)
+#define PSRAM_REG_WB_BL2_MASK_MSK      (((1U << PSRAM_REG_WB_BL2_MASK_LEN) - 1) << PSRAM_REG_WB_BL2_MASK_POS)
+#define PSRAM_REG_WB_BL2_MASK_UMSK     (~(((1U << PSRAM_REG_WB_BL2_MASK_LEN) - 1) << PSRAM_REG_WB_BL2_MASK_POS))
+#define PSRAM_REG_FORCE_CEB_LOW        PSRAM_REG_FORCE_CEB_LOW
+#define PSRAM_REG_FORCE_CEB_LOW_POS    (12U)
+#define PSRAM_REG_FORCE_CEB_LOW_LEN    (1U)
+#define PSRAM_REG_FORCE_CEB_LOW_MSK    (((1U << PSRAM_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_REG_FORCE_CEB_LOW_POS)
+#define PSRAM_REG_FORCE_CEB_LOW_UMSK   (~(((1U << PSRAM_REG_FORCE_CEB_LOW_LEN) - 1) << PSRAM_REG_FORCE_CEB_LOW_POS))
+#define PSRAM_REG_FORCE_CEB_HIGH       PSRAM_REG_FORCE_CEB_HIGH
+#define PSRAM_REG_FORCE_CEB_HIGH_POS   (13U)
+#define PSRAM_REG_FORCE_CEB_HIGH_LEN   (1U)
+#define PSRAM_REG_FORCE_CEB_HIGH_MSK   (((1U << PSRAM_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_REG_FORCE_CEB_HIGH_POS)
+#define PSRAM_REG_FORCE_CEB_HIGH_UMSK  (~(((1U << PSRAM_REG_FORCE_CEB_HIGH_LEN) - 1) << PSRAM_REG_FORCE_CEB_HIGH_POS))
+#define PSRAM_REG_PSRAM_RESETB         PSRAM_REG_PSRAM_RESETB
+#define PSRAM_REG_PSRAM_RESETB_POS     (14U)
+#define PSRAM_REG_PSRAM_RESETB_LEN     (1U)
+#define PSRAM_REG_PSRAM_RESETB_MSK     (((1U << PSRAM_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_REG_PSRAM_RESETB_POS)
+#define PSRAM_REG_PSRAM_RESETB_UMSK    (~(((1U << PSRAM_REG_PSRAM_RESETB_LEN) - 1) << PSRAM_REG_PSRAM_RESETB_POS))
+#define PSRAM_REG_CK_EDGE_NALI         PSRAM_REG_CK_EDGE_NALI
+#define PSRAM_REG_CK_EDGE_NALI_POS     (15U)
+#define PSRAM_REG_CK_EDGE_NALI_LEN     (1U)
+#define PSRAM_REG_CK_EDGE_NALI_MSK     (((1U << PSRAM_REG_CK_EDGE_NALI_LEN) - 1) << PSRAM_REG_CK_EDGE_NALI_POS)
+#define PSRAM_REG_CK_EDGE_NALI_UMSK    (~(((1U << PSRAM_REG_CK_EDGE_NALI_LEN) - 1) << PSRAM_REG_CK_EDGE_NALI_POS))
+#define PSRAM_STS_CONFIG_READ          PSRAM_STS_CONFIG_READ
+#define PSRAM_STS_CONFIG_READ_POS      (16U)
+#define PSRAM_STS_CONFIG_READ_LEN      (16U)
+#define PSRAM_STS_CONFIG_READ_MSK      (((1U << PSRAM_STS_CONFIG_READ_LEN) - 1) << PSRAM_STS_CONFIG_READ_POS)
+#define PSRAM_STS_CONFIG_READ_UMSK     (~(((1U << PSRAM_STS_CONFIG_READ_LEN) - 1) << PSRAM_STS_CONFIG_READ_POS))
+
+/* 0x8 : fifo_thres_control */
+#define PSRAM_FIFO_THRES_CONTROL_OFFSET (0x8)
+#define PSRAM_REG_MASK_W_FIFO_CNT       PSRAM_REG_MASK_W_FIFO_CNT
+#define PSRAM_REG_MASK_W_FIFO_CNT_POS   (0U)
+#define PSRAM_REG_MASK_W_FIFO_CNT_LEN   (16U)
+#define PSRAM_REG_MASK_W_FIFO_CNT_MSK   (((1U << PSRAM_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_REG_MASK_W_FIFO_CNT_POS)
+#define PSRAM_REG_MASK_W_FIFO_CNT_UMSK  (~(((1U << PSRAM_REG_MASK_W_FIFO_CNT_LEN) - 1) << PSRAM_REG_MASK_W_FIFO_CNT_POS))
+#define PSRAM_REG_MASK_R_FIFO_REM       PSRAM_REG_MASK_R_FIFO_REM
+#define PSRAM_REG_MASK_R_FIFO_REM_POS   (16U)
+#define PSRAM_REG_MASK_R_FIFO_REM_LEN   (16U)
+#define PSRAM_REG_MASK_R_FIFO_REM_MSK   (((1U << PSRAM_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_REG_MASK_R_FIFO_REM_POS)
+#define PSRAM_REG_MASK_R_FIFO_REM_UMSK  (~(((1U << PSRAM_REG_MASK_R_FIFO_REM_LEN) - 1) << PSRAM_REG_MASK_R_FIFO_REM_POS))
+
+/* 0xC : psram_manual_control2 */
+#define PSRAM_MANUAL_CONTROL2_OFFSET  (0xC)
+#define PSRAM_REG_HOLD_CYCLE_SW       PSRAM_REG_HOLD_CYCLE_SW
+#define PSRAM_REG_HOLD_CYCLE_SW_POS   (0U)
+#define PSRAM_REG_HOLD_CYCLE_SW_LEN   (7U)
+#define PSRAM_REG_HOLD_CYCLE_SW_MSK   (((1U << PSRAM_REG_HOLD_CYCLE_SW_LEN) - 1) << PSRAM_REG_HOLD_CYCLE_SW_POS)
+#define PSRAM_REG_HOLD_CYCLE_SW_UMSK  (~(((1U << PSRAM_REG_HOLD_CYCLE_SW_LEN) - 1) << PSRAM_REG_HOLD_CYCLE_SW_POS))
+#define PSRAM_REG_HC_SW_EN            PSRAM_REG_HC_SW_EN
+#define PSRAM_REG_HC_SW_EN_POS        (7U)
+#define PSRAM_REG_HC_SW_EN_LEN        (1U)
+#define PSRAM_REG_HC_SW_EN_MSK        (((1U << PSRAM_REG_HC_SW_EN_LEN) - 1) << PSRAM_REG_HC_SW_EN_POS)
+#define PSRAM_REG_HC_SW_EN_UMSK       (~(((1U << PSRAM_REG_HC_SW_EN_LEN) - 1) << PSRAM_REG_HC_SW_EN_POS))
+#define PSRAM_REG_DQS_REL_VAL         PSRAM_REG_DQS_REL_VAL
+#define PSRAM_REG_DQS_REL_VAL_POS     (8U)
+#define PSRAM_REG_DQS_REL_VAL_LEN     (7U)
+#define PSRAM_REG_DQS_REL_VAL_MSK     (((1U << PSRAM_REG_DQS_REL_VAL_LEN) - 1) << PSRAM_REG_DQS_REL_VAL_POS)
+#define PSRAM_REG_DQS_REL_VAL_UMSK    (~(((1U << PSRAM_REG_DQS_REL_VAL_LEN) - 1) << PSRAM_REG_DQS_REL_VAL_POS))
+#define PSRAM_REG_PWRAP_SW_SHT_B      PSRAM_REG_PWRAP_SW_SHT_B
+#define PSRAM_REG_PWRAP_SW_SHT_B_POS  (16U)
+#define PSRAM_REG_PWRAP_SW_SHT_B_LEN  (4U)
+#define PSRAM_REG_PWRAP_SW_SHT_B_MSK  (((1U << PSRAM_REG_PWRAP_SW_SHT_B_LEN) - 1) << PSRAM_REG_PWRAP_SW_SHT_B_POS)
+#define PSRAM_REG_PWRAP_SW_SHT_B_UMSK (~(((1U << PSRAM_REG_PWRAP_SW_SHT_B_LEN) - 1) << PSRAM_REG_PWRAP_SW_SHT_B_POS))
+#define PSRAM_REG_PWRAP_SW_EN         PSRAM_REG_PWRAP_SW_EN
+#define PSRAM_REG_PWRAP_SW_EN_POS     (23U)
+#define PSRAM_REG_PWRAP_SW_EN_LEN     (1U)
+#define PSRAM_REG_PWRAP_SW_EN_MSK     (((1U << PSRAM_REG_PWRAP_SW_EN_LEN) - 1) << PSRAM_REG_PWRAP_SW_EN_POS)
+#define PSRAM_REG_PWRAP_SW_EN_UMSK    (~(((1U << PSRAM_REG_PWRAP_SW_EN_LEN) - 1) << PSRAM_REG_PWRAP_SW_EN_POS))
+#define PSRAM_REG_ADDR_MASK           PSRAM_REG_ADDR_MASK
+#define PSRAM_REG_ADDR_MASK_POS       (24U)
+#define PSRAM_REG_ADDR_MASK_LEN       (8U)
+#define PSRAM_REG_ADDR_MASK_MSK       (((1U << PSRAM_REG_ADDR_MASK_LEN) - 1) << PSRAM_REG_ADDR_MASK_POS)
+#define PSRAM_REG_ADDR_MASK_UMSK      (~(((1U << PSRAM_REG_ADDR_MASK_LEN) - 1) << PSRAM_REG_ADDR_MASK_POS))
+
+/* 0x10 : winbond_psram_configure */
+#define PSRAM_WINBOND_PSRAM_CONFIGURE_OFFSET (0x10)
+#define PSRAM_REG_WB_LATENCY                 PSRAM_REG_WB_LATENCY
+#define PSRAM_REG_WB_LATENCY_POS             (0U)
+#define PSRAM_REG_WB_LATENCY_LEN             (4U)
+#define PSRAM_REG_WB_LATENCY_MSK             (((1U << PSRAM_REG_WB_LATENCY_LEN) - 1) << PSRAM_REG_WB_LATENCY_POS)
+#define PSRAM_REG_WB_LATENCY_UMSK            (~(((1U << PSRAM_REG_WB_LATENCY_LEN) - 1) << PSRAM_REG_WB_LATENCY_POS))
+#define PSRAM_REG_WB_DRIVE_ST                PSRAM_REG_WB_DRIVE_ST
+#define PSRAM_REG_WB_DRIVE_ST_POS            (4U)
+#define PSRAM_REG_WB_DRIVE_ST_LEN            (3U)
+#define PSRAM_REG_WB_DRIVE_ST_MSK            (((1U << PSRAM_REG_WB_DRIVE_ST_LEN) - 1) << PSRAM_REG_WB_DRIVE_ST_POS)
+#define PSRAM_REG_WB_DRIVE_ST_UMSK           (~(((1U << PSRAM_REG_WB_DRIVE_ST_LEN) - 1) << PSRAM_REG_WB_DRIVE_ST_POS))
+#define PSRAM_REG_WB_HYBRID_EN               PSRAM_REG_WB_HYBRID_EN
+#define PSRAM_REG_WB_HYBRID_EN_POS           (7U)
+#define PSRAM_REG_WB_HYBRID_EN_LEN           (1U)
+#define PSRAM_REG_WB_HYBRID_EN_MSK           (((1U << PSRAM_REG_WB_HYBRID_EN_LEN) - 1) << PSRAM_REG_WB_HYBRID_EN_POS)
+#define PSRAM_REG_WB_HYBRID_EN_UMSK          (~(((1U << PSRAM_REG_WB_HYBRID_EN_LEN) - 1) << PSRAM_REG_WB_HYBRID_EN_POS))
+#define PSRAM_REG_WB_BURST_LENGTH            PSRAM_REG_WB_BURST_LENGTH
+#define PSRAM_REG_WB_BURST_LENGTH_POS        (8U)
+#define PSRAM_REG_WB_BURST_LENGTH_LEN        (3U)
+#define PSRAM_REG_WB_BURST_LENGTH_MSK        (((1U << PSRAM_REG_WB_BURST_LENGTH_LEN) - 1) << PSRAM_REG_WB_BURST_LENGTH_POS)
+#define PSRAM_REG_WB_BURST_LENGTH_UMSK       (~(((1U << PSRAM_REG_WB_BURST_LENGTH_LEN) - 1) << PSRAM_REG_WB_BURST_LENGTH_POS))
+#define PSRAM_REG_WB_FIX_LATENCY             PSRAM_REG_WB_FIX_LATENCY
+#define PSRAM_REG_WB_FIX_LATENCY_POS         (12U)
+#define PSRAM_REG_WB_FIX_LATENCY_LEN         (1U)
+#define PSRAM_REG_WB_FIX_LATENCY_MSK         (((1U << PSRAM_REG_WB_FIX_LATENCY_LEN) - 1) << PSRAM_REG_WB_FIX_LATENCY_POS)
+#define PSRAM_REG_WB_FIX_LATENCY_UMSK        (~(((1U << PSRAM_REG_WB_FIX_LATENCY_LEN) - 1) << PSRAM_REG_WB_FIX_LATENCY_POS))
+#define PSRAM_REG_WB_DPD_DIS                 PSRAM_REG_WB_DPD_DIS
+#define PSRAM_REG_WB_DPD_DIS_POS             (13U)
+#define PSRAM_REG_WB_DPD_DIS_LEN             (1U)
+#define PSRAM_REG_WB_DPD_DIS_MSK             (((1U << PSRAM_REG_WB_DPD_DIS_LEN) - 1) << PSRAM_REG_WB_DPD_DIS_POS)
+#define PSRAM_REG_WB_DPD_DIS_UMSK            (~(((1U << PSRAM_REG_WB_DPD_DIS_LEN) - 1) << PSRAM_REG_WB_DPD_DIS_POS))
+#define PSRAM_REG_WB_PASR                    PSRAM_REG_WB_PASR
+#define PSRAM_REG_WB_PASR_POS                (16U)
+#define PSRAM_REG_WB_PASR_LEN                (5U)
+#define PSRAM_REG_WB_PASR_MSK                (((1U << PSRAM_REG_WB_PASR_LEN) - 1) << PSRAM_REG_WB_PASR_POS)
+#define PSRAM_REG_WB_PASR_UMSK               (~(((1U << PSRAM_REG_WB_PASR_LEN) - 1) << PSRAM_REG_WB_PASR_POS))
+#define PSRAM_REG_WB_HYBRID_SLP              PSRAM_REG_WB_HYBRID_SLP
+#define PSRAM_REG_WB_HYBRID_SLP_POS          (24U)
+#define PSRAM_REG_WB_HYBRID_SLP_LEN          (1U)
+#define PSRAM_REG_WB_HYBRID_SLP_MSK          (((1U << PSRAM_REG_WB_HYBRID_SLP_LEN) - 1) << PSRAM_REG_WB_HYBRID_SLP_POS)
+#define PSRAM_REG_WB_HYBRID_SLP_UMSK         (~(((1U << PSRAM_REG_WB_HYBRID_SLP_LEN) - 1) << PSRAM_REG_WB_HYBRID_SLP_POS))
+#define PSRAM_REG_WB_LINEAR_DIS              PSRAM_REG_WB_LINEAR_DIS
+#define PSRAM_REG_WB_LINEAR_DIS_POS          (25U)
+#define PSRAM_REG_WB_LINEAR_DIS_LEN          (1U)
+#define PSRAM_REG_WB_LINEAR_DIS_MSK          (((1U << PSRAM_REG_WB_LINEAR_DIS_LEN) - 1) << PSRAM_REG_WB_LINEAR_DIS_POS)
+#define PSRAM_REG_WB_LINEAR_DIS_UMSK         (~(((1U << PSRAM_REG_WB_LINEAR_DIS_LEN) - 1) << PSRAM_REG_WB_LINEAR_DIS_POS))
+#define PSRAM_REG_WB_IPD                     PSRAM_REG_WB_IPD
+#define PSRAM_REG_WB_IPD_POS                 (29U)
+#define PSRAM_REG_WB_IPD_LEN                 (1U)
+#define PSRAM_REG_WB_IPD_MSK                 (((1U << PSRAM_REG_WB_IPD_LEN) - 1) << PSRAM_REG_WB_IPD_POS)
+#define PSRAM_REG_WB_IPD_UMSK                (~(((1U << PSRAM_REG_WB_IPD_LEN) - 1) << PSRAM_REG_WB_IPD_POS))
+#define PSRAM_REG_WB_MCLK_TYPE               PSRAM_REG_WB_MCLK_TYPE
+#define PSRAM_REG_WB_MCLK_TYPE_POS           (30U)
+#define PSRAM_REG_WB_MCLK_TYPE_LEN           (1U)
+#define PSRAM_REG_WB_MCLK_TYPE_MSK           (((1U << PSRAM_REG_WB_MCLK_TYPE_LEN) - 1) << PSRAM_REG_WB_MCLK_TYPE_POS)
+#define PSRAM_REG_WB_MCLK_TYPE_UMSK          (~(((1U << PSRAM_REG_WB_MCLK_TYPE_LEN) - 1) << PSRAM_REG_WB_MCLK_TYPE_POS))
+#define PSRAM_REG_WB_SW_RST                  PSRAM_REG_WB_SW_RST
+#define PSRAM_REG_WB_SW_RST_POS              (31U)
+#define PSRAM_REG_WB_SW_RST_LEN              (1U)
+#define PSRAM_REG_WB_SW_RST_MSK              (((1U << PSRAM_REG_WB_SW_RST_LEN) - 1) << PSRAM_REG_WB_SW_RST_POS)
+#define PSRAM_REG_WB_SW_RST_UMSK             (~(((1U << PSRAM_REG_WB_SW_RST_LEN) - 1) << PSRAM_REG_WB_SW_RST_POS))
+
+/* 0x14 : winbond_psram_status */
+#define PSRAM_WINBOND_PSRAM_STATUS_OFFSET (0x14)
+#define PSRAM_STS_WB_LATENCY              PSRAM_STS_WB_LATENCY
+#define PSRAM_STS_WB_LATENCY_POS          (0U)
+#define PSRAM_STS_WB_LATENCY_LEN          (4U)
+#define PSRAM_STS_WB_LATENCY_MSK          (((1U << PSRAM_STS_WB_LATENCY_LEN) - 1) << PSRAM_STS_WB_LATENCY_POS)
+#define PSRAM_STS_WB_LATENCY_UMSK         (~(((1U << PSRAM_STS_WB_LATENCY_LEN) - 1) << PSRAM_STS_WB_LATENCY_POS))
+#define PSRAM_STS_WB_DRIVE_ST             PSRAM_STS_WB_DRIVE_ST
+#define PSRAM_STS_WB_DRIVE_ST_POS         (4U)
+#define PSRAM_STS_WB_DRIVE_ST_LEN         (3U)
+#define PSRAM_STS_WB_DRIVE_ST_MSK         (((1U << PSRAM_STS_WB_DRIVE_ST_LEN) - 1) << PSRAM_STS_WB_DRIVE_ST_POS)
+#define PSRAM_STS_WB_DRIVE_ST_UMSK        (~(((1U << PSRAM_STS_WB_DRIVE_ST_LEN) - 1) << PSRAM_STS_WB_DRIVE_ST_POS))
+#define PSRAM_STS_WB_HYBRID_EN            PSRAM_STS_WB_HYBRID_EN
+#define PSRAM_STS_WB_HYBRID_EN_POS        (7U)
+#define PSRAM_STS_WB_HYBRID_EN_LEN        (1U)
+#define PSRAM_STS_WB_HYBRID_EN_MSK        (((1U << PSRAM_STS_WB_HYBRID_EN_LEN) - 1) << PSRAM_STS_WB_HYBRID_EN_POS)
+#define PSRAM_STS_WB_HYBRID_EN_UMSK       (~(((1U << PSRAM_STS_WB_HYBRID_EN_LEN) - 1) << PSRAM_STS_WB_HYBRID_EN_POS))
+#define PSRAM_STS_WB_BURST_LENGTH         PSRAM_STS_WB_BURST_LENGTH
+#define PSRAM_STS_WB_BURST_LENGTH_POS     (8U)
+#define PSRAM_STS_WB_BURST_LENGTH_LEN     (3U)
+#define PSRAM_STS_WB_BURST_LENGTH_MSK     (((1U << PSRAM_STS_WB_BURST_LENGTH_LEN) - 1) << PSRAM_STS_WB_BURST_LENGTH_POS)
+#define PSRAM_STS_WB_BURST_LENGTH_UMSK    (~(((1U << PSRAM_STS_WB_BURST_LENGTH_LEN) - 1) << PSRAM_STS_WB_BURST_LENGTH_POS))
+#define PSRAM_STS_WB_FIX_LATENCY          PSRAM_STS_WB_FIX_LATENCY
+#define PSRAM_STS_WB_FIX_LATENCY_POS      (12U)
+#define PSRAM_STS_WB_FIX_LATENCY_LEN      (1U)
+#define PSRAM_STS_WB_FIX_LATENCY_MSK      (((1U << PSRAM_STS_WB_FIX_LATENCY_LEN) - 1) << PSRAM_STS_WB_FIX_LATENCY_POS)
+#define PSRAM_STS_WB_FIX_LATENCY_UMSK     (~(((1U << PSRAM_STS_WB_FIX_LATENCY_LEN) - 1) << PSRAM_STS_WB_FIX_LATENCY_POS))
+#define PSRAM_STS_WB_DPD_DIS              PSRAM_STS_WB_DPD_DIS
+#define PSRAM_STS_WB_DPD_DIS_POS          (13U)
+#define PSRAM_STS_WB_DPD_DIS_LEN          (1U)
+#define PSRAM_STS_WB_DPD_DIS_MSK          (((1U << PSRAM_STS_WB_DPD_DIS_LEN) - 1) << PSRAM_STS_WB_DPD_DIS_POS)
+#define PSRAM_STS_WB_DPD_DIS_UMSK         (~(((1U << PSRAM_STS_WB_DPD_DIS_LEN) - 1) << PSRAM_STS_WB_DPD_DIS_POS))
+#define PSRAM_STS_WB_PASR                 PSRAM_STS_WB_PASR
+#define PSRAM_STS_WB_PASR_POS             (16U)
+#define PSRAM_STS_WB_PASR_LEN             (5U)
+#define PSRAM_STS_WB_PASR_MSK             (((1U << PSRAM_STS_WB_PASR_LEN) - 1) << PSRAM_STS_WB_PASR_POS)
+#define PSRAM_STS_WB_PASR_UMSK            (~(((1U << PSRAM_STS_WB_PASR_LEN) - 1) << PSRAM_STS_WB_PASR_POS))
+#define PSRAM_STS_WB_HYBRID_SLP           PSRAM_STS_WB_HYBRID_SLP
+#define PSRAM_STS_WB_HYBRID_SLP_POS       (24U)
+#define PSRAM_STS_WB_HYBRID_SLP_LEN       (1U)
+#define PSRAM_STS_WB_HYBRID_SLP_MSK       (((1U << PSRAM_STS_WB_HYBRID_SLP_LEN) - 1) << PSRAM_STS_WB_HYBRID_SLP_POS)
+#define PSRAM_STS_WB_HYBRID_SLP_UMSK      (~(((1U << PSRAM_STS_WB_HYBRID_SLP_LEN) - 1) << PSRAM_STS_WB_HYBRID_SLP_POS))
+#define PSRAM_STS_WB_MCLK_TYPE            PSRAM_STS_WB_MCLK_TYPE
+#define PSRAM_STS_WB_MCLK_TYPE_POS        (30U)
+#define PSRAM_STS_WB_MCLK_TYPE_LEN        (1U)
+#define PSRAM_STS_WB_MCLK_TYPE_MSK        (((1U << PSRAM_STS_WB_MCLK_TYPE_LEN) - 1) << PSRAM_STS_WB_MCLK_TYPE_POS)
+#define PSRAM_STS_WB_MCLK_TYPE_UMSK       (~(((1U << PSRAM_STS_WB_MCLK_TYPE_LEN) - 1) << PSRAM_STS_WB_MCLK_TYPE_POS))
+
+/* 0x18 : winbond_psram_configure2 */
+#define PSRAM_WINBOND_PSRAM_CONFIGURE2_OFFSET (0x18)
+#define PSRAM_REG_WB_ZQ_CODE                  PSRAM_REG_WB_ZQ_CODE
+#define PSRAM_REG_WB_ZQ_CODE_POS              (0U)
+#define PSRAM_REG_WB_ZQ_CODE_LEN              (4U)
+#define PSRAM_REG_WB_ZQ_CODE_MSK              (((1U << PSRAM_REG_WB_ZQ_CODE_LEN) - 1) << PSRAM_REG_WB_ZQ_CODE_POS)
+#define PSRAM_REG_WB_ZQ_CODE_UMSK             (~(((1U << PSRAM_REG_WB_ZQ_CODE_LEN) - 1) << PSRAM_REG_WB_ZQ_CODE_POS))
+
+/* 0x20 : apmemory_psram_configure */
+#define PSRAM_APMEMORY_PSRAM_CONFIGURE_OFFSET (0x20)
+#define PSRAM_REG_AP_BURST_LENGTH             PSRAM_REG_AP_BURST_LENGTH
+#define PSRAM_REG_AP_BURST_LENGTH_POS         (0U)
+#define PSRAM_REG_AP_BURST_LENGTH_LEN         (2U)
+#define PSRAM_REG_AP_BURST_LENGTH_MSK         (((1U << PSRAM_REG_AP_BURST_LENGTH_LEN) - 1) << PSRAM_REG_AP_BURST_LENGTH_POS)
+#define PSRAM_REG_AP_BURST_LENGTH_UMSK        (~(((1U << PSRAM_REG_AP_BURST_LENGTH_LEN) - 1) << PSRAM_REG_AP_BURST_LENGTH_POS))
+#define PSRAM_REG_AP_BURST_TYPE               PSRAM_REG_AP_BURST_TYPE
+#define PSRAM_REG_AP_BURST_TYPE_POS           (4U)
+#define PSRAM_REG_AP_BURST_TYPE_LEN           (1U)
+#define PSRAM_REG_AP_BURST_TYPE_MSK           (((1U << PSRAM_REG_AP_BURST_TYPE_LEN) - 1) << PSRAM_REG_AP_BURST_TYPE_POS)
+#define PSRAM_REG_AP_BURST_TYPE_UMSK          (~(((1U << PSRAM_REG_AP_BURST_TYPE_LEN) - 1) << PSRAM_REG_AP_BURST_TYPE_POS))
+#define PSRAM_REG_AP_RBX                      PSRAM_REG_AP_RBX
+#define PSRAM_REG_AP_RBX_POS                  (5U)
+#define PSRAM_REG_AP_RBX_LEN                  (1U)
+#define PSRAM_REG_AP_RBX_MSK                  (((1U << PSRAM_REG_AP_RBX_LEN) - 1) << PSRAM_REG_AP_RBX_POS)
+#define PSRAM_REG_AP_RBX_UMSK                 (~(((1U << PSRAM_REG_AP_RBX_LEN) - 1) << PSRAM_REG_AP_RBX_POS))
+#define PSRAM_REG_AP_DPD                      PSRAM_REG_AP_DPD
+#define PSRAM_REG_AP_DPD_POS                  (6U)
+#define PSRAM_REG_AP_DPD_LEN                  (1U)
+#define PSRAM_REG_AP_DPD_MSK                  (((1U << PSRAM_REG_AP_DPD_LEN) - 1) << PSRAM_REG_AP_DPD_POS)
+#define PSRAM_REG_AP_DPD_UMSK                 (~(((1U << PSRAM_REG_AP_DPD_LEN) - 1) << PSRAM_REG_AP_DPD_POS))
+#define PSRAM_REG_AP_SLEEP                    PSRAM_REG_AP_SLEEP
+#define PSRAM_REG_AP_SLEEP_POS                (7U)
+#define PSRAM_REG_AP_SLEEP_LEN                (1U)
+#define PSRAM_REG_AP_SLEEP_MSK                (((1U << PSRAM_REG_AP_SLEEP_LEN) - 1) << PSRAM_REG_AP_SLEEP_POS)
+#define PSRAM_REG_AP_SLEEP_UMSK               (~(((1U << PSRAM_REG_AP_SLEEP_LEN) - 1) << PSRAM_REG_AP_SLEEP_POS))
+#define PSRAM_REG_AP_PASR                     PSRAM_REG_AP_PASR
+#define PSRAM_REG_AP_PASR_POS                 (8U)
+#define PSRAM_REG_AP_PASR_LEN                 (3U)
+#define PSRAM_REG_AP_PASR_MSK                 (((1U << PSRAM_REG_AP_PASR_LEN) - 1) << PSRAM_REG_AP_PASR_POS)
+#define PSRAM_REG_AP_PASR_UMSK                (~(((1U << PSRAM_REG_AP_PASR_LEN) - 1) << PSRAM_REG_AP_PASR_POS))
+#define PSRAM_REG_AP_W_LATENCY_CODE           PSRAM_REG_AP_W_LATENCY_CODE
+#define PSRAM_REG_AP_W_LATENCY_CODE_POS       (12U)
+#define PSRAM_REG_AP_W_LATENCY_CODE_LEN       (3U)
+#define PSRAM_REG_AP_W_LATENCY_CODE_MSK       (((1U << PSRAM_REG_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_W_LATENCY_CODE_POS)
+#define PSRAM_REG_AP_W_LATENCY_CODE_UMSK      (~(((1U << PSRAM_REG_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_W_LATENCY_CODE_POS))
+#define PSRAM_REG_AP_DRIVE_ST                 PSRAM_REG_AP_DRIVE_ST
+#define PSRAM_REG_AP_DRIVE_ST_POS             (16U)
+#define PSRAM_REG_AP_DRIVE_ST_LEN             (2U)
+#define PSRAM_REG_AP_DRIVE_ST_MSK             (((1U << PSRAM_REG_AP_DRIVE_ST_LEN) - 1) << PSRAM_REG_AP_DRIVE_ST_POS)
+#define PSRAM_REG_AP_DRIVE_ST_UMSK            (~(((1U << PSRAM_REG_AP_DRIVE_ST_LEN) - 1) << PSRAM_REG_AP_DRIVE_ST_POS))
+#define PSRAM_REG_AP_RF                       PSRAM_REG_AP_RF
+#define PSRAM_REG_AP_RF_POS                   (18U)
+#define PSRAM_REG_AP_RF_LEN                   (2U)
+#define PSRAM_REG_AP_RF_MSK                   (((1U << PSRAM_REG_AP_RF_LEN) - 1) << PSRAM_REG_AP_RF_POS)
+#define PSRAM_REG_AP_RF_UMSK                  (~(((1U << PSRAM_REG_AP_RF_LEN) - 1) << PSRAM_REG_AP_RF_POS))
+#define PSRAM_REG_AP_R_LATENCY_CODE           PSRAM_REG_AP_R_LATENCY_CODE
+#define PSRAM_REG_AP_R_LATENCY_CODE_POS       (20U)
+#define PSRAM_REG_AP_R_LATENCY_CODE_LEN       (3U)
+#define PSRAM_REG_AP_R_LATENCY_CODE_MSK       (((1U << PSRAM_REG_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_CODE_POS)
+#define PSRAM_REG_AP_R_LATENCY_CODE_UMSK      (~(((1U << PSRAM_REG_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_CODE_POS))
+#define PSRAM_REG_AP_R_LATENCY_TYPE           PSRAM_REG_AP_R_LATENCY_TYPE
+#define PSRAM_REG_AP_R_LATENCY_TYPE_POS       (24U)
+#define PSRAM_REG_AP_R_LATENCY_TYPE_LEN       (1U)
+#define PSRAM_REG_AP_R_LATENCY_TYPE_MSK       (((1U << PSRAM_REG_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_TYPE_POS)
+#define PSRAM_REG_AP_R_LATENCY_TYPE_UMSK      (~(((1U << PSRAM_REG_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_REG_AP_R_LATENCY_TYPE_POS))
+#define PSRAM_REG_AP_LINEAR_DIS               PSRAM_REG_AP_LINEAR_DIS
+#define PSRAM_REG_AP_LINEAR_DIS_POS           (25U)
+#define PSRAM_REG_AP_LINEAR_DIS_LEN           (1U)
+#define PSRAM_REG_AP_LINEAR_DIS_MSK           (((1U << PSRAM_REG_AP_LINEAR_DIS_LEN) - 1) << PSRAM_REG_AP_LINEAR_DIS_POS)
+#define PSRAM_REG_AP_LINEAR_DIS_UMSK          (~(((1U << PSRAM_REG_AP_LINEAR_DIS_LEN) - 1) << PSRAM_REG_AP_LINEAR_DIS_POS))
+#define PSRAM_REG_GLB_RESET_PULSE             PSRAM_REG_GLB_RESET_PULSE
+#define PSRAM_REG_GLB_RESET_PULSE_POS         (28U)
+#define PSRAM_REG_GLB_RESET_PULSE_LEN         (1U)
+#define PSRAM_REG_GLB_RESET_PULSE_MSK         (((1U << PSRAM_REG_GLB_RESET_PULSE_LEN) - 1) << PSRAM_REG_GLB_RESET_PULSE_POS)
+#define PSRAM_REG_GLB_RESET_PULSE_UMSK        (~(((1U << PSRAM_REG_GLB_RESET_PULSE_LEN) - 1) << PSRAM_REG_GLB_RESET_PULSE_POS))
+
+/* 0x24 : apmemory_psram_status */
+#define PSRAM_APMEMORY_PSRAM_STATUS_OFFSET (0x24)
+#define PSRAM_STS_AP_BURST_LENGTH          PSRAM_STS_AP_BURST_LENGTH
+#define PSRAM_STS_AP_BURST_LENGTH_POS      (0U)
+#define PSRAM_STS_AP_BURST_LENGTH_LEN      (2U)
+#define PSRAM_STS_AP_BURST_LENGTH_MSK      (((1U << PSRAM_STS_AP_BURST_LENGTH_LEN) - 1) << PSRAM_STS_AP_BURST_LENGTH_POS)
+#define PSRAM_STS_AP_BURST_LENGTH_UMSK     (~(((1U << PSRAM_STS_AP_BURST_LENGTH_LEN) - 1) << PSRAM_STS_AP_BURST_LENGTH_POS))
+#define PSRAM_STS_AP_BURST_TYPE            PSRAM_STS_AP_BURST_TYPE
+#define PSRAM_STS_AP_BURST_TYPE_POS        (4U)
+#define PSRAM_STS_AP_BURST_TYPE_LEN        (1U)
+#define PSRAM_STS_AP_BURST_TYPE_MSK        (((1U << PSRAM_STS_AP_BURST_TYPE_LEN) - 1) << PSRAM_STS_AP_BURST_TYPE_POS)
+#define PSRAM_STS_AP_BURST_TYPE_UMSK       (~(((1U << PSRAM_STS_AP_BURST_TYPE_LEN) - 1) << PSRAM_STS_AP_BURST_TYPE_POS))
+#define PSRAM_STS_AP_RBX                   PSRAM_STS_AP_RBX
+#define PSRAM_STS_AP_RBX_POS               (5U)
+#define PSRAM_STS_AP_RBX_LEN               (1U)
+#define PSRAM_STS_AP_RBX_MSK               (((1U << PSRAM_STS_AP_RBX_LEN) - 1) << PSRAM_STS_AP_RBX_POS)
+#define PSRAM_STS_AP_RBX_UMSK              (~(((1U << PSRAM_STS_AP_RBX_LEN) - 1) << PSRAM_STS_AP_RBX_POS))
+#define PSRAM_STS_AP_X16_MODE              PSRAM_STS_AP_X16_MODE
+#define PSRAM_STS_AP_X16_MODE_POS          (6U)
+#define PSRAM_STS_AP_X16_MODE_LEN          (1U)
+#define PSRAM_STS_AP_X16_MODE_MSK          (((1U << PSRAM_STS_AP_X16_MODE_LEN) - 1) << PSRAM_STS_AP_X16_MODE_POS)
+#define PSRAM_STS_AP_X16_MODE_UMSK         (~(((1U << PSRAM_STS_AP_X16_MODE_LEN) - 1) << PSRAM_STS_AP_X16_MODE_POS))
+#define PSRAM_STS_AP_PASR                  PSRAM_STS_AP_PASR
+#define PSRAM_STS_AP_PASR_POS              (8U)
+#define PSRAM_STS_AP_PASR_LEN              (3U)
+#define PSRAM_STS_AP_PASR_MSK              (((1U << PSRAM_STS_AP_PASR_LEN) - 1) << PSRAM_STS_AP_PASR_POS)
+#define PSRAM_STS_AP_PASR_UMSK             (~(((1U << PSRAM_STS_AP_PASR_LEN) - 1) << PSRAM_STS_AP_PASR_POS))
+#define PSRAM_STS_AP_W_LATENCY_CODE        PSRAM_STS_AP_W_LATENCY_CODE
+#define PSRAM_STS_AP_W_LATENCY_CODE_POS    (12U)
+#define PSRAM_STS_AP_W_LATENCY_CODE_LEN    (3U)
+#define PSRAM_STS_AP_W_LATENCY_CODE_MSK    (((1U << PSRAM_STS_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_W_LATENCY_CODE_POS)
+#define PSRAM_STS_AP_W_LATENCY_CODE_UMSK   (~(((1U << PSRAM_STS_AP_W_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_W_LATENCY_CODE_POS))
+#define PSRAM_STS_AP_DRIVE_ST              PSRAM_STS_AP_DRIVE_ST
+#define PSRAM_STS_AP_DRIVE_ST_POS          (16U)
+#define PSRAM_STS_AP_DRIVE_ST_LEN          (2U)
+#define PSRAM_STS_AP_DRIVE_ST_MSK          (((1U << PSRAM_STS_AP_DRIVE_ST_LEN) - 1) << PSRAM_STS_AP_DRIVE_ST_POS)
+#define PSRAM_STS_AP_DRIVE_ST_UMSK         (~(((1U << PSRAM_STS_AP_DRIVE_ST_LEN) - 1) << PSRAM_STS_AP_DRIVE_ST_POS))
+#define PSRAM_STS_AP_RF                    PSRAM_STS_AP_RF
+#define PSRAM_STS_AP_RF_POS                (18U)
+#define PSRAM_STS_AP_RF_LEN                (2U)
+#define PSRAM_STS_AP_RF_MSK                (((1U << PSRAM_STS_AP_RF_LEN) - 1) << PSRAM_STS_AP_RF_POS)
+#define PSRAM_STS_AP_RF_UMSK               (~(((1U << PSRAM_STS_AP_RF_LEN) - 1) << PSRAM_STS_AP_RF_POS))
+#define PSRAM_STS_AP_R_LATENCY_CODE        PSRAM_STS_AP_R_LATENCY_CODE
+#define PSRAM_STS_AP_R_LATENCY_CODE_POS    (20U)
+#define PSRAM_STS_AP_R_LATENCY_CODE_LEN    (3U)
+#define PSRAM_STS_AP_R_LATENCY_CODE_MSK    (((1U << PSRAM_STS_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_CODE_POS)
+#define PSRAM_STS_AP_R_LATENCY_CODE_UMSK   (~(((1U << PSRAM_STS_AP_R_LATENCY_CODE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_CODE_POS))
+#define PSRAM_STS_AP_R_LATENCY_TYPE        PSRAM_STS_AP_R_LATENCY_TYPE
+#define PSRAM_STS_AP_R_LATENCY_TYPE_POS    (24U)
+#define PSRAM_STS_AP_R_LATENCY_TYPE_LEN    (1U)
+#define PSRAM_STS_AP_R_LATENCY_TYPE_MSK    (((1U << PSRAM_STS_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_TYPE_POS)
+#define PSRAM_STS_AP_R_LATENCY_TYPE_UMSK   (~(((1U << PSRAM_STS_AP_R_LATENCY_TYPE_LEN) - 1) << PSRAM_STS_AP_R_LATENCY_TYPE_POS))
+
+/* 0x30 : psram_manual_control3 */
+#define PSRAM_MANUAL_CONTROL3_OFFSET    (0x30)
+#define PSRAM_REG_ADQ_REL_VAL           PSRAM_REG_ADQ_REL_VAL
+#define PSRAM_REG_ADQ_REL_VAL_POS       (0U)
+#define PSRAM_REG_ADQ_REL_VAL_LEN       (7U)
+#define PSRAM_REG_ADQ_REL_VAL_MSK       (((1U << PSRAM_REG_ADQ_REL_VAL_LEN) - 1) << PSRAM_REG_ADQ_REL_VAL_POS)
+#define PSRAM_REG_ADQ_REL_VAL_UMSK      (~(((1U << PSRAM_REG_ADQ_REL_VAL_LEN) - 1) << PSRAM_REG_ADQ_REL_VAL_POS))
+#define PSRAM_REG_WRAP2INCR_EN          PSRAM_REG_WRAP2INCR_EN
+#define PSRAM_REG_WRAP2INCR_EN_POS      (8U)
+#define PSRAM_REG_WRAP2INCR_EN_LEN      (1U)
+#define PSRAM_REG_WRAP2INCR_EN_MSK      (((1U << PSRAM_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_REG_WRAP2INCR_EN_POS)
+#define PSRAM_REG_WRAP2INCR_EN_UMSK     (~(((1U << PSRAM_REG_WRAP2INCR_EN_LEN) - 1) << PSRAM_REG_WRAP2INCR_EN_POS))
+#define PSRAM_REG_APH_RWDS_THRE_SW      PSRAM_REG_APH_RWDS_THRE_SW
+#define PSRAM_REG_APH_RWDS_THRE_SW_POS  (16U)
+#define PSRAM_REG_APH_RWDS_THRE_SW_LEN  (6U)
+#define PSRAM_REG_APH_RWDS_THRE_SW_MSK  (((1U << PSRAM_REG_APH_RWDS_THRE_SW_LEN) - 1) << PSRAM_REG_APH_RWDS_THRE_SW_POS)
+#define PSRAM_REG_APH_RWDS_THRE_SW_UMSK (~(((1U << PSRAM_REG_APH_RWDS_THRE_SW_LEN) - 1) << PSRAM_REG_APH_RWDS_THRE_SW_POS))
+
+/* 0x80 : psram_intf_delay_ctrl0 */
+#define PSRAM_INTF_DELAY_CTRL0_OFFSET       (0x80)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0      PSRAM_REG_DELAY_SEL_O_DQS_OEN0
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS  (0U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS_OEN0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_OEN0_POS))
+#define PSRAM_REG_DELAY_SEL_O_CEB           PSRAM_REG_DELAY_SEL_O_CEB
+#define PSRAM_REG_DELAY_SEL_O_CEB_POS       (8U)
+#define PSRAM_REG_DELAY_SEL_O_CEB_LEN       (8U)
+#define PSRAM_REG_DELAY_SEL_O_CEB_MSK       (((1U << PSRAM_REG_DELAY_SEL_O_CEB_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CEB_POS)
+#define PSRAM_REG_DELAY_SEL_O_CEB_UMSK      (~(((1U << PSRAM_REG_DELAY_SEL_O_CEB_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CEB_POS))
+#define PSRAM_REG_DELAY_SEL_O_CLK_N         PSRAM_REG_DELAY_SEL_O_CLK_N
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_POS     (16U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_LEN     (8U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_MSK     (((1U << PSRAM_REG_DELAY_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_N_POS)
+#define PSRAM_REG_DELAY_SEL_O_CLK_N_UMSK    (~(((1U << PSRAM_REG_DELAY_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_N_POS))
+#define PSRAM_REG_DELAY_SEL_O_CLK           PSRAM_REG_DELAY_SEL_O_CLK
+#define PSRAM_REG_DELAY_SEL_O_CLK_POS       (24U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_LEN       (8U)
+#define PSRAM_REG_DELAY_SEL_O_CLK_MSK       (((1U << PSRAM_REG_DELAY_SEL_O_CLK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_POS)
+#define PSRAM_REG_DELAY_SEL_O_CLK_UMSK      (~(((1U << PSRAM_REG_DELAY_SEL_O_CLK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_CLK_POS))
+
+/* 0x84 : psram_intf_delay_ctrl1 */
+#define PSRAM_INTF_DELAY_CTRL1_OFFSET       (0x84)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1          PSRAM_REG_DELAY_SEL_O_ADQ1
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_POS      (0U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_LEN      (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ1_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ1_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ1_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ0          PSRAM_REG_DELAY_SEL_O_ADQ0
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_POS      (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_LEN      (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ0_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ0_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ0_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0      PSRAM_REG_DELAY_SEL_O_ADQ_OEN0
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS  (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN0_POS))
+#define PSRAM_REG_DELAY_SEL_O_DQS0          PSRAM_REG_DELAY_SEL_O_DQS0
+#define PSRAM_REG_DELAY_SEL_O_DQS0_POS      (24U)
+#define PSRAM_REG_DELAY_SEL_O_DQS0_LEN      (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS0_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS0_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS0_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS0_POS))
+
+/* 0x88 : psram_intf_delay_ctrl2 */
+#define PSRAM_INTF_DELAY_CTRL2_OFFSET   (0x88)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5      PSRAM_REG_DELAY_SEL_O_ADQ5
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_POS  (0U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ5_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ5_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ5_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ4      PSRAM_REG_DELAY_SEL_O_ADQ4
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_POS  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ4_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ4_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ4_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ3      PSRAM_REG_DELAY_SEL_O_ADQ3
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_POS  (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ3_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ3_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ3_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ2      PSRAM_REG_DELAY_SEL_O_ADQ2
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_POS  (24U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ2_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ2_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ2_POS))
+
+/* 0x8C : psram_intf_delay_ctrl3 */
+#define PSRAM_INTF_DELAY_CTRL3_OFFSET   (0x8C)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1      PSRAM_REG_DELAY_SEL_I_ADQ1
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_POS  (0U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ1_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ1_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ0      PSRAM_REG_DELAY_SEL_I_ADQ0
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_POS  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ0_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ0_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ7      PSRAM_REG_DELAY_SEL_O_ADQ7
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_POS  (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ7_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ7_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ7_POS))
+#define PSRAM_REG_DELAY_SEL_O_ADQ6      PSRAM_REG_DELAY_SEL_O_ADQ6
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_POS  (24U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ6_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ6_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ6_POS))
+
+/* 0x90 : psram_intf_delay_ctrl4 */
+#define PSRAM_INTF_DELAY_CTRL4_OFFSET   (0x90)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5      PSRAM_REG_DELAY_SEL_I_ADQ5
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_POS  (0U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ5_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ5_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ5_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ4      PSRAM_REG_DELAY_SEL_I_ADQ4
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_POS  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ4_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ4_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ4_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ3      PSRAM_REG_DELAY_SEL_I_ADQ3
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_POS  (16U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ3_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ3_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ3_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ2      PSRAM_REG_DELAY_SEL_I_ADQ2
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_POS  (24U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ2_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ2_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ2_POS))
+
+/* 0x94 : psram_intf_delay_ctrl5 */
+#define PSRAM_INTF_DELAY_CTRL5_OFFSET   (0x94)
+#define PSRAM_REG_DELAY_SEL_I_DQS0      PSRAM_REG_DELAY_SEL_I_DQS0
+#define PSRAM_REG_DELAY_SEL_I_DQS0_POS  (0U)
+#define PSRAM_REG_DELAY_SEL_I_DQS0_LEN  (16U)
+#define PSRAM_REG_DELAY_SEL_I_DQS0_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS0_POS)
+#define PSRAM_REG_DELAY_SEL_I_DQS0_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_DQS0_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ7      PSRAM_REG_DELAY_SEL_I_ADQ7
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_POS  (16U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ7_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ7_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ7_POS))
+#define PSRAM_REG_DELAY_SEL_I_ADQ6      PSRAM_REG_DELAY_SEL_I_ADQ6
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_POS  (24U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_MSK  (((1U << PSRAM_REG_DELAY_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ6_POS)
+#define PSRAM_REG_DELAY_SEL_I_ADQ6_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_DELAY_SEL_I_ADQ6_POS))
+
+/* 0x98 : psram_intf_delay_ctrl6 */
+#define PSRAM_INTF_DELAY_CTRL6_OFFSET       (0x98)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1      PSRAM_REG_DELAY_SEL_O_ADQ_OEN1
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS  (16U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS)
+#define PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_ADQ_OEN1_POS))
+#define PSRAM_REG_DELAY_SEL_O_DQS1          PSRAM_REG_DELAY_SEL_O_DQS1
+#define PSRAM_REG_DELAY_SEL_O_DQS1_POS      (24U)
+#define PSRAM_REG_DELAY_SEL_O_DQS1_LEN      (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS1_MSK      (((1U << PSRAM_REG_DELAY_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS1_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS1_UMSK     (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS1_POS))
+
+/* 0xAC : psram_intf_delay_ctrlB */
+#define PSRAM_INTF_DELAY_CTRLB_OFFSET       (0xAC)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK      PSRAM_REG_DELAY_SEL_O_DQS_MASK
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS  (0U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN  (8U)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_MSK  (((1U << PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS)
+#define PSRAM_REG_DELAY_SEL_O_DQS_MASK_UMSK (~(((1U << PSRAM_REG_DELAY_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_DELAY_SEL_O_DQS_MASK_POS))
+
+/* 0xC0 : psram_dbg_sel */
+#define PSRAM_DBG_SEL_OFFSET         (0xC0)
+#define PSRAM_REG_PSRAM_DBG_EN       PSRAM_REG_PSRAM_DBG_EN
+#define PSRAM_REG_PSRAM_DBG_EN_POS   (0U)
+#define PSRAM_REG_PSRAM_DBG_EN_LEN   (1U)
+#define PSRAM_REG_PSRAM_DBG_EN_MSK   (((1U << PSRAM_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_REG_PSRAM_DBG_EN_POS)
+#define PSRAM_REG_PSRAM_DBG_EN_UMSK  (~(((1U << PSRAM_REG_PSRAM_DBG_EN_LEN) - 1) << PSRAM_REG_PSRAM_DBG_EN_POS))
+#define PSRAM_REG_PSRAM_DBG_SEL      PSRAM_REG_PSRAM_DBG_SEL
+#define PSRAM_REG_PSRAM_DBG_SEL_POS  (4U)
+#define PSRAM_REG_PSRAM_DBG_SEL_LEN  (4U)
+#define PSRAM_REG_PSRAM_DBG_SEL_MSK  (((1U << PSRAM_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_REG_PSRAM_DBG_SEL_POS)
+#define PSRAM_REG_PSRAM_DBG_SEL_UMSK (~(((1U << PSRAM_REG_PSRAM_DBG_SEL_LEN) - 1) << PSRAM_REG_PSRAM_DBG_SEL_POS))
+
+/* 0xF0 : psram_dummy_reg */
+#define PSRAM_DUMMY_REG_OFFSET         (0xF0)
+#define PSRAM_REG_PSRAM_DUMMY_REG      PSRAM_REG_PSRAM_DUMMY_REG
+#define PSRAM_REG_PSRAM_DUMMY_REG_POS  (0U)
+#define PSRAM_REG_PSRAM_DUMMY_REG_LEN  (32U)
+#define PSRAM_REG_PSRAM_DUMMY_REG_MSK  (((1U << PSRAM_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_REG_PSRAM_DUMMY_REG_POS)
+#define PSRAM_REG_PSRAM_DUMMY_REG_UMSK (~(((1U << PSRAM_REG_PSRAM_DUMMY_REG_LEN) - 1) << PSRAM_REG_PSRAM_DUMMY_REG_POS))
+
+/* 0xF4 : psram_timeout_reg */
+#define PSRAM_TIMEOUT_REG_OFFSET   (0xF4)
+#define PSRAM_REG_TIMEOUT_EN       PSRAM_REG_TIMEOUT_EN
+#define PSRAM_REG_TIMEOUT_EN_POS   (0U)
+#define PSRAM_REG_TIMEOUT_EN_LEN   (1U)
+#define PSRAM_REG_TIMEOUT_EN_MSK   (((1U << PSRAM_REG_TIMEOUT_EN_LEN) - 1) << PSRAM_REG_TIMEOUT_EN_POS)
+#define PSRAM_REG_TIMEOUT_EN_UMSK  (~(((1U << PSRAM_REG_TIMEOUT_EN_LEN) - 1) << PSRAM_REG_TIMEOUT_EN_POS))
+#define PSRAM_REG_TIMEOUT_CLR      PSRAM_REG_TIMEOUT_CLR
+#define PSRAM_REG_TIMEOUT_CLR_POS  (1U)
+#define PSRAM_REG_TIMEOUT_CLR_LEN  (1U)
+#define PSRAM_REG_TIMEOUT_CLR_MSK  (((1U << PSRAM_REG_TIMEOUT_CLR_LEN) - 1) << PSRAM_REG_TIMEOUT_CLR_POS)
+#define PSRAM_REG_TIMEOUT_CLR_UMSK (~(((1U << PSRAM_REG_TIMEOUT_CLR_LEN) - 1) << PSRAM_REG_TIMEOUT_CLR_POS))
+#define PSRAM_STS_TIMEOUT          PSRAM_STS_TIMEOUT
+#define PSRAM_STS_TIMEOUT_POS      (2U)
+#define PSRAM_STS_TIMEOUT_LEN      (1U)
+#define PSRAM_STS_TIMEOUT_MSK      (((1U << PSRAM_STS_TIMEOUT_LEN) - 1) << PSRAM_STS_TIMEOUT_POS)
+#define PSRAM_STS_TIMEOUT_UMSK     (~(((1U << PSRAM_STS_TIMEOUT_LEN) - 1) << PSRAM_STS_TIMEOUT_POS))
+#define PSRAM_REG_TIMEOUT_CNT      PSRAM_REG_TIMEOUT_CNT
+#define PSRAM_REG_TIMEOUT_CNT_POS  (16U)
+#define PSRAM_REG_TIMEOUT_CNT_LEN  (12U)
+#define PSRAM_REG_TIMEOUT_CNT_MSK  (((1U << PSRAM_REG_TIMEOUT_CNT_LEN) - 1) << PSRAM_REG_TIMEOUT_CNT_POS)
+#define PSRAM_REG_TIMEOUT_CNT_UMSK (~(((1U << PSRAM_REG_TIMEOUT_CNT_LEN) - 1) << PSRAM_REG_TIMEOUT_CNT_POS))
+
+/* 0x100 : psram_rough_delay_ctrl0 */
+#define PSRAM_ROUGH_DELAY_CTRL0_OFFSET      (0x100)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0      PSRAM_REG_ROUGH_SEL_O_DQS_OEN0
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_CEB           PSRAM_REG_ROUGH_SEL_O_CEB
+#define PSRAM_REG_ROUGH_SEL_O_CEB_POS       (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CEB_LEN       (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CEB_MSK       (((1U << PSRAM_REG_ROUGH_SEL_O_CEB_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CEB_POS)
+#define PSRAM_REG_ROUGH_SEL_O_CEB_UMSK      (~(((1U << PSRAM_REG_ROUGH_SEL_O_CEB_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CEB_POS))
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N         PSRAM_REG_ROUGH_SEL_O_CLK_N
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_POS     (16U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN     (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_MSK     (((1U << PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_N_POS)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_N_UMSK    (~(((1U << PSRAM_REG_ROUGH_SEL_O_CLK_N_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_N_POS))
+#define PSRAM_REG_ROUGH_SEL_O_CLK           PSRAM_REG_ROUGH_SEL_O_CLK
+#define PSRAM_REG_ROUGH_SEL_O_CLK_POS       (24U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_LEN       (8U)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_MSK       (((1U << PSRAM_REG_ROUGH_SEL_O_CLK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_POS)
+#define PSRAM_REG_ROUGH_SEL_O_CLK_UMSK      (~(((1U << PSRAM_REG_ROUGH_SEL_O_CLK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_CLK_POS))
+
+/* 0x104 : psram_rough_delay_ctrl1 */
+#define PSRAM_ROUGH_DELAY_CTRL1_OFFSET      (0x104)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1          PSRAM_REG_ROUGH_SEL_O_ADQ1
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_POS      (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ1_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ1_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0          PSRAM_REG_ROUGH_SEL_O_ADQ0
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_POS      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ0_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0      PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_DQS0          PSRAM_REG_ROUGH_SEL_O_DQS0
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_POS      (24U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_LEN      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS0_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS0_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS0_POS))
+
+/* 0x108 : psram_rough_delay_ctrl2 */
+#define PSRAM_ROUGH_DELAY_CTRL2_OFFSET  (0x108)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5      PSRAM_REG_ROUGH_SEL_O_ADQ5
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ5_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ5_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ5_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4      PSRAM_REG_ROUGH_SEL_O_ADQ4
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_POS  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ4_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ4_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ4_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3      PSRAM_REG_ROUGH_SEL_O_ADQ3
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ3_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ3_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ3_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2      PSRAM_REG_ROUGH_SEL_O_ADQ2
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ2_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ2_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ2_POS))
+
+/* 0x10C : psram_rough_delay_ctrl3 */
+#define PSRAM_ROUGH_DELAY_CTRL3_OFFSET  (0x10C)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1      PSRAM_REG_ROUGH_SEL_I_ADQ1
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ1_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ1_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0      PSRAM_REG_ROUGH_SEL_I_ADQ0
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_POS  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ0_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ0_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7      PSRAM_REG_ROUGH_SEL_O_ADQ7
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ7_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ7_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ7_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6      PSRAM_REG_ROUGH_SEL_O_ADQ6
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ6_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ6_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ6_POS))
+
+/* 0x110 : psram_rough_delay_ctrl4 */
+#define PSRAM_ROUGH_DELAY_CTRL4_OFFSET  (0x110)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5      PSRAM_REG_ROUGH_SEL_I_ADQ5
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ5_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ5_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ5_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ5_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4      PSRAM_REG_ROUGH_SEL_I_ADQ4
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_POS  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ4_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ4_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ4_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ4_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3      PSRAM_REG_ROUGH_SEL_I_ADQ3
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ3_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ3_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ3_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ3_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2      PSRAM_REG_ROUGH_SEL_I_ADQ2
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ2_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ2_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ2_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ2_POS))
+
+/* 0x114 : psram_rough_delay_ctrl5 */
+#define PSRAM_ROUGH_DELAY_CTRL5_OFFSET  (0x114)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0      PSRAM_REG_ROUGH_SEL_I_DQS0
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_LEN  (16U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS0_POS)
+#define PSRAM_REG_ROUGH_SEL_I_DQS0_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_DQS0_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS0_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7      PSRAM_REG_ROUGH_SEL_I_ADQ7
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ7_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ7_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ7_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ7_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6      PSRAM_REG_ROUGH_SEL_I_ADQ6
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ6_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ6_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ6_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ6_POS))
+
+/* 0x118 : psram_rough_delay_ctrl6 */
+#define PSRAM_ROUGH_DELAY_CTRL6_OFFSET      (0x118)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9          PSRAM_REG_ROUGH_SEL_O_ADQ9
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_POS      (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ9_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ9_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ9_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8          PSRAM_REG_ROUGH_SEL_O_ADQ8
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_POS      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ8_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ8_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ8_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1      PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ_OEN1_POS))
+#define PSRAM_REG_ROUGH_SEL_O_DQS1          PSRAM_REG_ROUGH_SEL_O_DQS1
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_POS      (24U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_LEN      (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_MSK      (((1U << PSRAM_REG_ROUGH_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS1_UMSK     (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS1_POS))
+
+/* 0x11C : psram_rough_delay_ctrl7 */
+#define PSRAM_ROUGH_DELAY_CTRL7_OFFSET   (0x11C)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13      PSRAM_REG_ROUGH_SEL_O_ADQ13
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ13_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ13_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ13_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12      PSRAM_REG_ROUGH_SEL_O_ADQ12
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_POS  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ12_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ12_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ12_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11      PSRAM_REG_ROUGH_SEL_O_ADQ11
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ11_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ11_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ11_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10      PSRAM_REG_ROUGH_SEL_O_ADQ10
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ10_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ10_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ10_POS))
+
+/* 0x120 : psram_rough_delay_ctrl8 */
+#define PSRAM_ROUGH_DELAY_CTRL8_OFFSET   (0x120)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9       PSRAM_REG_ROUGH_SEL_I_ADQ9
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_POS   (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN   (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_MSK   (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ9_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ9_UMSK  (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ9_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ9_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8       PSRAM_REG_ROUGH_SEL_I_ADQ8
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_POS   (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN   (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_MSK   (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ8_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ8_UMSK  (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ8_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ8_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15      PSRAM_REG_ROUGH_SEL_O_ADQ15
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ15_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ15_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ15_POS))
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14      PSRAM_REG_ROUGH_SEL_O_ADQ14
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ14_POS)
+#define PSRAM_REG_ROUGH_SEL_O_ADQ14_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_ADQ14_POS))
+
+/* 0x124 : psram_rough_delay_ctrl9 */
+#define PSRAM_ROUGH_DELAY_CTRL9_OFFSET   (0x124)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13      PSRAM_REG_ROUGH_SEL_I_ADQ13
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ13_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ13_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ13_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ13_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12      PSRAM_REG_ROUGH_SEL_I_ADQ12
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_POS  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ12_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ12_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ12_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ12_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11      PSRAM_REG_ROUGH_SEL_I_ADQ11
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ11_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ11_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ11_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ11_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10      PSRAM_REG_ROUGH_SEL_I_ADQ10
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ10_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ10_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ10_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ10_POS))
+
+/* 0x128 : psram_rough_delay_ctrlA */
+#define PSRAM_ROUGH_DELAY_CTRLA_OFFSET   (0x128)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1       PSRAM_REG_ROUGH_SEL_I_DQS1
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_POS   (0U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_LEN   (16U)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_MSK   (((1U << PSRAM_REG_ROUGH_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS1_POS)
+#define PSRAM_REG_ROUGH_SEL_I_DQS1_UMSK  (~(((1U << PSRAM_REG_ROUGH_SEL_I_DQS1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_DQS1_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15      PSRAM_REG_ROUGH_SEL_I_ADQ15
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_POS  (16U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ15_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ15_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ15_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ15_POS))
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14      PSRAM_REG_ROUGH_SEL_I_ADQ14
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_POS  (24U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_MSK  (((1U << PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ14_POS)
+#define PSRAM_REG_ROUGH_SEL_I_ADQ14_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_I_ADQ14_LEN) - 1) << PSRAM_REG_ROUGH_SEL_I_ADQ14_POS))
+
+/* 0x12C : psram_rough_delay_ctrlB */
+#define PSRAM_ROUGH_DELAY_CTRLB_OFFSET      (0x12C)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK      PSRAM_REG_ROUGH_SEL_O_DQS_MASK
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS  (0U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_MASK_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_MASK_POS))
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1      PSRAM_REG_ROUGH_SEL_O_DQS_OEN1
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN  (8U)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_MSK  (((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS)
+#define PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_UMSK (~(((1U << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_LEN) - 1) << PSRAM_REG_ROUGH_SEL_O_DQS_OEN1_POS))
+
+struct psram_reg {
+    /* 0x0 : psram_configure */
+    union {
+        struct {
+            uint32_t reg_vendor_sel     : 3; /* [ 2: 0],        r/w,        0x2 */
+            uint32_t reserved_3         : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t reg_ap_mr          : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t reserved_7         : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t reg_wb_reg_sel     : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t reserved_11        : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t reg_config_w_pusle : 1; /* [   12],        w1p,        0x0 */
+            uint32_t reg_config_r_pusle : 1; /* [   13],        w1p,        0x0 */
+            uint32_t sts_config_w_done  : 1; /* [   14],          r,        0x1 */
+            uint32_t sts_config_r_done  : 1; /* [   15],          r,        0x1 */
+            uint32_t reg_config_req     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_config_gnt     : 1; /* [   17],          r,        0x0 */
+            uint32_t reg_x16_mode       : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg_wb_hyper3      : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg_pck_s_div      : 3; /* [22:20],        r/w,        0x0 */
+            uint32_t reg_clkn_free      : 1; /* [   23],        r/w,        0x1 */
+            uint32_t reserved_24_27     : 4; /* [27:24],       rsvd,        0x0 */
+            uint32_t reg_linear_bnd_b   : 4; /* [31:28],        r/w,        0xa */
+        } BF;
+        uint32_t WORD;
+    } psram_configure;
+
+    /* 0x4 : psram_manual_control */
+    union {
+        struct {
+            uint32_t reg_wc_sw           : 7;  /* [ 6: 0],        r/w,        0x0 */
+            uint32_t reserved_7          : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t reg_wc_sw_en        : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reg_state_hold_tick : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reg_dqs_latch_inv   : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reg_wb_bl2_mask     : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t reg_force_ceb_low   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reg_force_ceb_high  : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reg_psram_resetb    : 1;  /* [   14],        r/w,        0x1 */
+            uint32_t reg_ck_edge_nali    : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t sts_config_read     : 16; /* [31:16],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_manual_control;
+
+    /* 0x8 : fifo_thres_control */
+    union {
+        struct {
+            uint32_t reg_mask_w_fifo_cnt : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reg_mask_r_fifo_rem : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } fifo_thres_control;
+
+    /* 0xC : psram_manual_control2 */
+    union {
+        struct {
+            uint32_t reg_hold_cycle_sw  : 7; /* [ 6: 0],        r/w,        0x8 */
+            uint32_t reg_hc_sw_en       : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_dqs_rel_val    : 7; /* [14: 8],        r/w,       0x20 */
+            uint32_t reserved_15        : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t reg_pwrap_sw_sht_b : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t reserved_20_22     : 3; /* [22:20],       rsvd,        0x0 */
+            uint32_t reg_pwrap_sw_en    : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reg_addr_mask      : 8; /* [31:24],        r/w,       0x1f */
+        } BF;
+        uint32_t WORD;
+    } psram_manual_control2;
+
+    /* 0x10 : winbond_psram_configure */
+    union {
+        struct {
+            uint32_t reg_wb_latency      : 4; /* [ 3: 0],        r/w,        0x2 */
+            uint32_t reg_wb_drive_st     : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t reg_wb_hybrid_en    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t reg_wb_burst_length : 3; /* [10: 8],        r/w,        0x7 */
+            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t reg_wb_fix_latency  : 1; /* [   12],        r/w,        0x1 */
+            uint32_t reg_wb_dpd_dis      : 1; /* [   13],        r/w,        0x1 */
+            uint32_t reserved_14_15      : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t reg_wb_pasr         : 5; /* [20:16],        r/w,        0x0 */
+            uint32_t reserved_21_23      : 3; /* [23:21],       rsvd,        0x0 */
+            uint32_t reg_wb_hybrid_slp   : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_wb_linear_dis   : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reserved_26_28      : 3; /* [28:26],       rsvd,        0x0 */
+            uint32_t reg_wb_ipd          : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_wb_mclk_type    : 1; /* [   30],        r/w,        0x1 */
+            uint32_t reg_wb_sw_rst       : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } winbond_psram_configure;
+
+    /* 0x14 : winbond_psram_status */
+    union {
+        struct {
+            uint32_t sts_wb_latency      : 4; /* [ 3: 0],          r,        0x2 */
+            uint32_t sts_wb_drive_st     : 3; /* [ 6: 4],          r,        0x0 */
+            uint32_t sts_wb_hybrid_en    : 1; /* [    7],          r,        0x1 */
+            uint32_t sts_wb_burst_length : 3; /* [10: 8],          r,        0x3 */
+            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t sts_wb_fix_latency  : 1; /* [   12],          r,        0x1 */
+            uint32_t sts_wb_dpd_dis      : 1; /* [   13],          r,        0x1 */
+            uint32_t reserved_14_15      : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t sts_wb_pasr         : 5; /* [20:16],          r,        0x0 */
+            uint32_t reserved_21_23      : 3; /* [23:21],       rsvd,        0x0 */
+            uint32_t sts_wb_hybrid_slp   : 1; /* [   24],          r,        0x0 */
+            uint32_t reserved_25_29      : 5; /* [29:25],       rsvd,        0x0 */
+            uint32_t sts_wb_mclk_type    : 1; /* [   30],          r,        0x1 */
+            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } winbond_psram_status;
+
+    /* 0x18 : winbond_psram_configure2 */
+    union {
+        struct {
+            uint32_t reg_wb_zq_code : 4;  /* [ 3: 0],        r/w,        0x0 */
+            uint32_t reserved_4_31  : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } winbond_psram_configure2;
+
+    /* 0x1c  reserved */
+    uint8_t RESERVED0x1c[4];
+
+    /* 0x20 : apmemory_psram_configure */
+    union {
+        struct {
+            uint32_t reg_ap_burst_length   : 2; /* [ 1: 0],        r/w,        0x1 */
+            uint32_t reserved_2_3          : 2; /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t reg_ap_burst_type     : 1; /* [    4],        r/w,        0x1 */
+            uint32_t reg_ap_rbx            : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_ap_dpd            : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_ap_sleep          : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_ap_pasr           : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t reserved_11           : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t reg_ap_w_latency_code : 3; /* [14:12],        r/w,        0x2 */
+            uint32_t reserved_15           : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t reg_ap_drive_st       : 2; /* [17:16],        r/w,        0x1 */
+            uint32_t reg_ap_rf             : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_ap_r_latency_code : 3; /* [22:20],        r/w,        0x2 */
+            uint32_t reserved_23           : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t reg_ap_r_latency_type : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_ap_linear_dis     : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reserved_26_27        : 2; /* [27:26],       rsvd,        0x0 */
+            uint32_t reg_glb_reset_pulse   : 1; /* [   28],        w1p,        0x0 */
+            uint32_t reserved_29_31        : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } apmemory_psram_configure;
+
+    /* 0x24 : apmemory_psram_status */
+    union {
+        struct {
+            uint32_t sts_ap_burst_length   : 2; /* [ 1: 0],          r,        0x1 */
+            uint32_t reserved_2_3          : 2; /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t sts_ap_burst_type     : 1; /* [    4],          r,        0x1 */
+            uint32_t sts_ap_rbx            : 1; /* [    5],          r,        0x0 */
+            uint32_t sts_ap_x16_mode       : 1; /* [    6],          r,        0x0 */
+            uint32_t reserved_7            : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t sts_ap_pasr           : 3; /* [10: 8],          r,        0x0 */
+            uint32_t reserved_11           : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t sts_ap_w_latency_code : 3; /* [14:12],          r,        0x2 */
+            uint32_t reserved_15           : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t sts_ap_drive_st       : 2; /* [17:16],          r,        0x1 */
+            uint32_t sts_ap_rf             : 2; /* [19:18],          r,        0x0 */
+            uint32_t sts_ap_r_latency_code : 3; /* [22:20],          r,        0x2 */
+            uint32_t reserved_23           : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t sts_ap_r_latency_type : 1; /* [   24],          r,        0x0 */
+            uint32_t reserved_25_31        : 7; /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } apmemory_psram_status;
+
+    /* 0x28  reserved */
+    uint8_t RESERVED0x28[8];
+
+    /* 0x30 : psram_manual_control3 */
+    union {
+        struct {
+            uint32_t reg_adq_rel_val      : 7;  /* [ 6: 0],        r/w,       0x20 */
+            uint32_t reserved_7           : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t reg_wrap2incr_en     : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_15        : 7;  /* [15: 9],       rsvd,        0x0 */
+            uint32_t reg_aph_rwds_thre_sw : 6;  /* [21:16],        r/w,        0x0 */
+            uint32_t reserved_22_31       : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_manual_control3;
+
+    /* 0x34  reserved */
+    uint8_t RESERVED0x34[76];
+
+    /* 0x80 : psram_intf_delay_ctrl0 */
+    union {
+        struct {
+            uint32_t reg_delay_sel_o_dqs_oen0 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_ceb      : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_clk_n    : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_clk      : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrl0;
+
+    /* 0x84 : psram_intf_delay_ctrl1 */
+    union {
+        struct {
+            uint32_t reg_delay_sel_o_adq1     : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_adq0     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_adq_oen0 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_dqs0     : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrl1;
+
+    /* 0x88 : psram_intf_delay_ctrl2 */
+    union {
+        struct {
+            uint32_t reg_delay_sel_o_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_adq4 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_adq3 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_adq2 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrl2;
+
+    /* 0x8C : psram_intf_delay_ctrl3 */
+    union {
+        struct {
+            uint32_t reg_delay_sel_i_adq1 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_delay_sel_i_adq0 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_adq7 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_adq6 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrl3;
+
+    /* 0x90 : psram_intf_delay_ctrl4 */
+    union {
+        struct {
+            uint32_t reg_delay_sel_i_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_delay_sel_i_adq4 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_delay_sel_i_adq3 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_delay_sel_i_adq2 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrl4;
+
+    /* 0x94 : psram_intf_delay_ctrl5 */
+    union {
+        struct {
+            uint32_t reg_delay_sel_i_dqs0 : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reg_delay_sel_i_adq7 : 8;  /* [23:16],        r/w,        0x0 */
+            uint32_t reg_delay_sel_i_adq6 : 8;  /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrl5;
+
+    /* 0x98 : psram_intf_delay_ctrl6 */
+    union {
+        struct {
+            uint32_t reserved_0_15            : 16; /* [15: 0],       rsvd,        0x0 */
+            uint32_t reg_delay_sel_o_adq_oen1 : 8;  /* [23:16],        r/w,        0x0 */
+            uint32_t reg_delay_sel_o_dqs1     : 8;  /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrl6;
+
+    /* 0x9c  reserved */
+    uint8_t RESERVED0x9c[16];
+
+    /* 0xAC : psram_intf_delay_ctrlB */
+    union {
+        struct {
+            uint32_t reg_delay_sel_o_dqs_mask : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_31            : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_intf_delay_ctrlB;
+
+    /* 0xb0  reserved */
+    uint8_t RESERVED0xb0[16];
+
+    /* 0xC0 : psram_dbg_sel */
+    union {
+        struct {
+            uint32_t reg_psram_dbg_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3      : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t reg_psram_dbg_sel : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_31     : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_dbg_sel;
+
+    /* 0xc4  reserved */
+    uint8_t RESERVED0xc4[44];
+
+    /* 0xF0 : psram_dummy_reg */
+    union {
+        struct {
+            uint32_t reg_psram_dummy_reg : 32; /* [31: 0],        r/w, 0xffff0000 */
+        } BF;
+        uint32_t WORD;
+    } psram_dummy_reg;
+
+    /* 0xF4 : psram_timeout_reg */
+    union {
+        struct {
+            uint32_t reg_timeout_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_timeout_clr : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t sts_timeout     : 1;  /* [    2],          r,        0x0 */
+            uint32_t reserved_3_15   : 13; /* [15: 3],       rsvd,        0x0 */
+            uint32_t reg_timeout_cnt : 12; /* [27:16],        r/w,      0x100 */
+            uint32_t reserved_28_31  : 4;  /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_timeout_reg;
+
+    /* 0xf8  reserved */
+    uint8_t RESERVED0xf8[8];
+
+    /* 0x100 : psram_rough_delay_ctrl0 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_o_dqs_oen0 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_ceb      : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_clk_n    : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_clk      : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl0;
+
+    /* 0x104 : psram_rough_delay_ctrl1 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_o_adq1     : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq0     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq_oen0 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_dqs0     : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl1;
+
+    /* 0x108 : psram_rough_delay_ctrl2 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_o_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq4 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq3 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq2 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl2;
+
+    /* 0x10C : psram_rough_delay_ctrl3 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_i_adq1 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq0 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq7 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq6 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl3;
+
+    /* 0x110 : psram_rough_delay_ctrl4 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_i_adq5 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq4 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq3 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq2 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl4;
+
+    /* 0x114 : psram_rough_delay_ctrl5 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_i_dqs0 : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq7 : 8;  /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq6 : 8;  /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl5;
+
+    /* 0x118 : psram_rough_delay_ctrl6 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_o_adq9     : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq8     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq_oen1 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_dqs1     : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl6;
+
+    /* 0x11C : psram_rough_delay_ctrl7 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_o_adq13 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq12 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq11 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq10 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl7;
+
+    /* 0x120 : psram_rough_delay_ctrl8 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_i_adq9  : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq8  : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq15 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_adq14 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl8;
+
+    /* 0x124 : psram_rough_delay_ctrl9 */
+    union {
+        struct {
+            uint32_t reg_rough_sel_i_adq13 : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq12 : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq11 : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq10 : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrl9;
+
+    /* 0x128 : psram_rough_delay_ctrlA */
+    union {
+        struct {
+            uint32_t reg_rough_sel_i_dqs1  : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq15 : 8;  /* [23:16],        r/w,        0x0 */
+            uint32_t reg_rough_sel_i_adq14 : 8;  /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrlA;
+
+    /* 0x12C : psram_rough_delay_ctrlB */
+    union {
+        struct {
+            uint32_t reg_rough_sel_o_dqs_mask : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_rough_sel_o_dqs_oen1 : 8;  /* [15: 8],        r/w,        0x0 */
+            uint32_t reserved_16_31           : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psram_rough_delay_ctrlB;
+};
+
+typedef volatile struct psram_reg psram_reg_t;
+
+#endif /* __PSRAM_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sdh_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sdh_reg.h
new file mode 100755
index 0000000000..ebb0fea3f7
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sdh_reg.h
@@ -0,0 +1,2732 @@
+/**
+  ******************************************************************************
+  * @file    sdh_reg.h
+  * @version V1.2
+  * @date    2018-10-08
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2018 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __SDH_REG_H__
+#define __SDH_REG_H__
+
+#include "bl616.h"
+
+/* 0x00 : System Address Low Register */
+#define SDH_SD_SYS_ADDR_LOW_OFFSET (0x00)
+#define SDH_DMA_ADDR_L             SDH_DMA_ADDR_L
+#define SDH_DMA_ADDR_L_POS         (0U)
+#define SDH_DMA_ADDR_L_LEN         (16U)
+#define SDH_DMA_ADDR_L_MSK         (((1U << SDH_DMA_ADDR_L_LEN) - 1) << SDH_DMA_ADDR_L_POS)
+#define SDH_DMA_ADDR_L_UMSK        (~(((1U << SDH_DMA_ADDR_L_LEN) - 1) << SDH_DMA_ADDR_L_POS))
+
+/* 0x02 : System Address High Register */
+#define SDH_SD_SYS_ADDR_HIGH_OFFSET (0x02)
+#define SDH_DMA_ADDR_H              SDH_DMA_ADDR_H
+#define SDH_DMA_ADDR_H_POS          (0U)
+#define SDH_DMA_ADDR_H_LEN          (16U)
+#define SDH_DMA_ADDR_H_MSK          (((1U << SDH_DMA_ADDR_H_LEN) - 1) << SDH_DMA_ADDR_H_POS)
+#define SDH_DMA_ADDR_H_UMSK         (~(((1U << SDH_DMA_ADDR_H_LEN) - 1) << SDH_DMA_ADDR_H_POS))
+
+/* 0x04 : Block Size Register */
+#define SDH_SD_BLOCK_SIZE_OFFSET (0x04)
+#define SDH_BLOCK_SIZE           SDH_BLOCK_SIZE
+#define SDH_BLOCK_SIZE_POS       (0U)
+#define SDH_BLOCK_SIZE_LEN       (12U)
+#define SDH_BLOCK_SIZE_MSK       (((1U << SDH_BLOCK_SIZE_LEN) - 1) << SDH_BLOCK_SIZE_POS)
+#define SDH_BLOCK_SIZE_UMSK      (~(((1U << SDH_BLOCK_SIZE_LEN) - 1) << SDH_BLOCK_SIZE_POS))
+#define SDH_HOST_DMA_BDRY        SDH_HOST_DMA_BDRY
+#define SDH_HOST_DMA_BDRY_POS    (12U)
+#define SDH_HOST_DMA_BDRY_LEN    (3U)
+#define SDH_HOST_DMA_BDRY_MSK    (((1U << SDH_HOST_DMA_BDRY_LEN) - 1) << SDH_HOST_DMA_BDRY_POS)
+#define SDH_HOST_DMA_BDRY_UMSK   (~(((1U << SDH_HOST_DMA_BDRY_LEN) - 1) << SDH_HOST_DMA_BDRY_POS))
+
+/* 0x06 : Block Count Register */
+#define SDH_SD_BLOCK_COUNT_OFFSET (0x06)
+#define SDH_BLOCK_COUNT           SDH_BLOCK_COUNT
+#define SDH_BLOCK_COUNT_POS       (0U)
+#define SDH_BLOCK_COUNT_LEN       (16U)
+#define SDH_BLOCK_COUNT_MSK       (((1U << SDH_BLOCK_COUNT_LEN) - 1) << SDH_BLOCK_COUNT_POS)
+#define SDH_BLOCK_COUNT_UMSK      (~(((1U << SDH_BLOCK_COUNT_LEN) - 1) << SDH_BLOCK_COUNT_POS))
+
+/* 0x08 : Argument Low Register */
+#define SDH_SD_ARG_LOW_OFFSET (0x08)
+#define SDH_ARG_L             SDH_ARG_L
+#define SDH_ARG_L_POS         (0U)
+#define SDH_ARG_L_LEN         (16U)
+#define SDH_ARG_L_MSK         (((1U << SDH_ARG_L_LEN) - 1) << SDH_ARG_L_POS)
+#define SDH_ARG_L_UMSK        (~(((1U << SDH_ARG_L_LEN) - 1) << SDH_ARG_L_POS))
+
+/* 0x0A : Argument High Register */
+#define SDH_SD_ARG_HIGH_OFFSET (0x0A)
+#define SDH_ARG_H              SDH_ARG_H
+#define SDH_ARG_H_POS          (0U)
+#define SDH_ARG_H_LEN          (16U)
+#define SDH_ARG_H_MSK          (((1U << SDH_ARG_H_LEN) - 1) << SDH_ARG_H_POS)
+#define SDH_ARG_H_UMSK         (~(((1U << SDH_ARG_H_LEN) - 1) << SDH_ARG_H_POS))
+
+/* 0x0C : Transfer Mode Register */
+#define SDH_SD_TRANSFER_MODE_OFFSET (0x0C)
+#define SDH_DMA_EN                  SDH_DMA_EN
+#define SDH_DMA_EN_POS              (0U)
+#define SDH_DMA_EN_LEN              (1U)
+#define SDH_DMA_EN_MSK              (((1U << SDH_DMA_EN_LEN) - 1) << SDH_DMA_EN_POS)
+#define SDH_DMA_EN_UMSK             (~(((1U << SDH_DMA_EN_LEN) - 1) << SDH_DMA_EN_POS))
+#define SDH_BLK_CNT_EN              SDH_BLK_CNT_EN
+#define SDH_BLK_CNT_EN_POS          (1U)
+#define SDH_BLK_CNT_EN_LEN          (1U)
+#define SDH_BLK_CNT_EN_MSK          (((1U << SDH_BLK_CNT_EN_LEN) - 1) << SDH_BLK_CNT_EN_POS)
+#define SDH_BLK_CNT_EN_UMSK         (~(((1U << SDH_BLK_CNT_EN_LEN) - 1) << SDH_BLK_CNT_EN_POS))
+#define SDH_AUTO_CMD_EN             SDH_AUTO_CMD_EN
+#define SDH_AUTO_CMD_EN_POS         (2U)
+#define SDH_AUTO_CMD_EN_LEN         (2U)
+#define SDH_AUTO_CMD_EN_MSK         (((1U << SDH_AUTO_CMD_EN_LEN) - 1) << SDH_AUTO_CMD_EN_POS)
+#define SDH_AUTO_CMD_EN_UMSK        (~(((1U << SDH_AUTO_CMD_EN_LEN) - 1) << SDH_AUTO_CMD_EN_POS))
+#define SDH_TO_HOST_DIR             SDH_TO_HOST_DIR
+#define SDH_TO_HOST_DIR_POS         (4U)
+#define SDH_TO_HOST_DIR_LEN         (1U)
+#define SDH_TO_HOST_DIR_MSK         (((1U << SDH_TO_HOST_DIR_LEN) - 1) << SDH_TO_HOST_DIR_POS)
+#define SDH_TO_HOST_DIR_UMSK        (~(((1U << SDH_TO_HOST_DIR_LEN) - 1) << SDH_TO_HOST_DIR_POS))
+#define SDH_MULTI_BLK_SEL           SDH_MULTI_BLK_SEL
+#define SDH_MULTI_BLK_SEL_POS       (5U)
+#define SDH_MULTI_BLK_SEL_LEN       (1U)
+#define SDH_MULTI_BLK_SEL_MSK       (((1U << SDH_MULTI_BLK_SEL_LEN) - 1) << SDH_MULTI_BLK_SEL_POS)
+#define SDH_MULTI_BLK_SEL_UMSK      (~(((1U << SDH_MULTI_BLK_SEL_LEN) - 1) << SDH_MULTI_BLK_SEL_POS))
+
+/* 0x0E : Command Register */
+#define SDH_SD_CMD_OFFSET         (0x0E)
+#define SDH_RESP_TYPE             SDH_RESP_TYPE
+#define SDH_RESP_TYPE_POS         (0U)
+#define SDH_RESP_TYPE_LEN         (2U)
+#define SDH_RESP_TYPE_MSK         (((1U << SDH_RESP_TYPE_LEN) - 1) << SDH_RESP_TYPE_POS)
+#define SDH_RESP_TYPE_UMSK        (~(((1U << SDH_RESP_TYPE_LEN) - 1) << SDH_RESP_TYPE_POS))
+#define SDH_CMD_CRC_CHK_EN        SDH_CMD_CRC_CHK_EN
+#define SDH_CMD_CRC_CHK_EN_POS    (3U)
+#define SDH_CMD_CRC_CHK_EN_LEN    (1U)
+#define SDH_CMD_CRC_CHK_EN_MSK    (((1U << SDH_CMD_CRC_CHK_EN_LEN) - 1) << SDH_CMD_CRC_CHK_EN_POS)
+#define SDH_CMD_CRC_CHK_EN_UMSK   (~(((1U << SDH_CMD_CRC_CHK_EN_LEN) - 1) << SDH_CMD_CRC_CHK_EN_POS))
+#define SDH_CMD_INDEX_CHK_EN      SDH_CMD_INDEX_CHK_EN
+#define SDH_CMD_INDEX_CHK_EN_POS  (4U)
+#define SDH_CMD_INDEX_CHK_EN_LEN  (1U)
+#define SDH_CMD_INDEX_CHK_EN_MSK  (((1U << SDH_CMD_INDEX_CHK_EN_LEN) - 1) << SDH_CMD_INDEX_CHK_EN_POS)
+#define SDH_CMD_INDEX_CHK_EN_UMSK (~(((1U << SDH_CMD_INDEX_CHK_EN_LEN) - 1) << SDH_CMD_INDEX_CHK_EN_POS))
+#define SDH_DATA_PRESENT          SDH_DATA_PRESENT
+#define SDH_DATA_PRESENT_POS      (5U)
+#define SDH_DATA_PRESENT_LEN      (1U)
+#define SDH_DATA_PRESENT_MSK      (((1U << SDH_DATA_PRESENT_LEN) - 1) << SDH_DATA_PRESENT_POS)
+#define SDH_DATA_PRESENT_UMSK     (~(((1U << SDH_DATA_PRESENT_LEN) - 1) << SDH_DATA_PRESENT_POS))
+#define SDH_CMD_TYPE              SDH_CMD_TYPE
+#define SDH_CMD_TYPE_POS          (6U)
+#define SDH_CMD_TYPE_LEN          (2U)
+#define SDH_CMD_TYPE_MSK          (((1U << SDH_CMD_TYPE_LEN) - 1) << SDH_CMD_TYPE_POS)
+#define SDH_CMD_TYPE_UMSK         (~(((1U << SDH_CMD_TYPE_LEN) - 1) << SDH_CMD_TYPE_POS))
+#define SDH_CMD_INDEX             SDH_CMD_INDEX
+#define SDH_CMD_INDEX_POS         (8U)
+#define SDH_CMD_INDEX_LEN         (6U)
+#define SDH_CMD_INDEX_MSK         (((1U << SDH_CMD_INDEX_LEN) - 1) << SDH_CMD_INDEX_POS)
+#define SDH_CMD_INDEX_UMSK        (~(((1U << SDH_CMD_INDEX_LEN) - 1) << SDH_CMD_INDEX_POS))
+
+/* 0x10 : Response Register 0 */
+#define SDH_SD_RESP_0_OFFSET (0x10)
+#define SDH_RESP0            SDH_RESP0
+#define SDH_RESP0_POS        (0U)
+#define SDH_RESP0_LEN        (16U)
+#define SDH_RESP0_MSK        (((1U << SDH_RESP0_LEN) - 1) << SDH_RESP0_POS)
+#define SDH_RESP0_UMSK       (~(((1U << SDH_RESP0_LEN) - 1) << SDH_RESP0_POS))
+
+/* 0x12 : Response Register 1 */
+#define SDH_SD_RESP_1_OFFSET (0x12)
+#define SDH_RESP1            SDH_RESP1
+#define SDH_RESP1_POS        (0U)
+#define SDH_RESP1_LEN        (16U)
+#define SDH_RESP1_MSK        (((1U << SDH_RESP1_LEN) - 1) << SDH_RESP1_POS)
+#define SDH_RESP1_UMSK       (~(((1U << SDH_RESP1_LEN) - 1) << SDH_RESP1_POS))
+
+/* 0x14 : Response Register 2 */
+#define SDH_SD_RESP_2_OFFSET (0x14)
+#define SDH_RESP2            SDH_RESP2
+#define SDH_RESP2_POS        (0U)
+#define SDH_RESP2_LEN        (16U)
+#define SDH_RESP2_MSK        (((1U << SDH_RESP2_LEN) - 1) << SDH_RESP2_POS)
+#define SDH_RESP2_UMSK       (~(((1U << SDH_RESP2_LEN) - 1) << SDH_RESP2_POS))
+
+/* 0x16 : Response Register 3 */
+#define SDH_SD_RESP_3_OFFSET (0x16)
+#define SDH_RESP3            SDH_RESP3
+#define SDH_RESP3_POS        (0U)
+#define SDH_RESP3_LEN        (16U)
+#define SDH_RESP3_MSK        (((1U << SDH_RESP3_LEN) - 1) << SDH_RESP3_POS)
+#define SDH_RESP3_UMSK       (~(((1U << SDH_RESP3_LEN) - 1) << SDH_RESP3_POS))
+
+/* 0x18 : Response Register 4 */
+#define SDH_SD_RESP_4_OFFSET (0x18)
+#define SDH_RESP4            SDH_RESP4
+#define SDH_RESP4_POS        (0U)
+#define SDH_RESP4_LEN        (16U)
+#define SDH_RESP4_MSK        (((1U << SDH_RESP4_LEN) - 1) << SDH_RESP4_POS)
+#define SDH_RESP4_UMSK       (~(((1U << SDH_RESP4_LEN) - 1) << SDH_RESP4_POS))
+
+/* 0x1A : Response Register 5 */
+#define SDH_SD_RESP_5_OFFSET (0x1A)
+#define SDH_RESP5            SDH_RESP5
+#define SDH_RESP5_POS        (0U)
+#define SDH_RESP5_LEN        (16U)
+#define SDH_RESP5_MSK        (((1U << SDH_RESP5_LEN) - 1) << SDH_RESP5_POS)
+#define SDH_RESP5_UMSK       (~(((1U << SDH_RESP5_LEN) - 1) << SDH_RESP5_POS))
+
+/* 0x1C : Response Register 6 */
+#define SDH_SD_RESP_6_OFFSET (0x1C)
+#define SDH_RESP6            SDH_RESP6
+#define SDH_RESP6_POS        (0U)
+#define SDH_RESP6_LEN        (16U)
+#define SDH_RESP6_MSK        (((1U << SDH_RESP6_LEN) - 1) << SDH_RESP6_POS)
+#define SDH_RESP6_UMSK       (~(((1U << SDH_RESP6_LEN) - 1) << SDH_RESP6_POS))
+
+/* 0x1E : Response Register 7 */
+#define SDH_SD_RESP_7_OFFSET (0x1E)
+#define SDH_RESP7            SDH_RESP7
+#define SDH_RESP7_POS        (0U)
+#define SDH_RESP7_LEN        (16U)
+#define SDH_RESP7_MSK        (((1U << SDH_RESP7_LEN) - 1) << SDH_RESP7_POS)
+#define SDH_RESP7_UMSK       (~(((1U << SDH_RESP7_LEN) - 1) << SDH_RESP7_POS))
+
+/* 0x20 : Buffer Data Port 0 Register */
+#define SDH_SD_BUFFER_DATA_PORT_0_OFFSET (0x20)
+#define SDH_CPU_DATA0                    SDH_CPU_DATA0
+#define SDH_CPU_DATA0_POS                (0U)
+#define SDH_CPU_DATA0_LEN                (16U)
+#define SDH_CPU_DATA0_MSK                (((1U << SDH_CPU_DATA0_LEN) - 1) << SDH_CPU_DATA0_POS)
+#define SDH_CPU_DATA0_UMSK               (~(((1U << SDH_CPU_DATA0_LEN) - 1) << SDH_CPU_DATA0_POS))
+
+/* 0x22 : Buffer Data Port 1 Register */
+#define SDH_SD_BUFFER_DATA_PORT_1_OFFSET (0x22)
+#define SDH_CPU_DATA1                    SDH_CPU_DATA1
+#define SDH_CPU_DATA1_POS                (0U)
+#define SDH_CPU_DATA1_LEN                (16U)
+#define SDH_CPU_DATA1_MSK                (((1U << SDH_CPU_DATA1_LEN) - 1) << SDH_CPU_DATA1_POS)
+#define SDH_CPU_DATA1_UMSK               (~(((1U << SDH_CPU_DATA1_LEN) - 1) << SDH_CPU_DATA1_POS))
+
+/* 0x24 : Present State Register 1 */
+#define SDH_SD_PRESENT_STATE_1_OFFSET (0x24)
+#define SDH_CMD_INHIBIT_CMD           SDH_CMD_INHIBIT_CMD
+#define SDH_CMD_INHIBIT_CMD_POS       (0U)
+#define SDH_CMD_INHIBIT_CMD_LEN       (1U)
+#define SDH_CMD_INHIBIT_CMD_MSK       (((1U << SDH_CMD_INHIBIT_CMD_LEN) - 1) << SDH_CMD_INHIBIT_CMD_POS)
+#define SDH_CMD_INHIBIT_CMD_UMSK      (~(((1U << SDH_CMD_INHIBIT_CMD_LEN) - 1) << SDH_CMD_INHIBIT_CMD_POS))
+#define SDH_CMD_INHIBIT_DAT           SDH_CMD_INHIBIT_DAT
+#define SDH_CMD_INHIBIT_DAT_POS       (1U)
+#define SDH_CMD_INHIBIT_DAT_LEN       (1U)
+#define SDH_CMD_INHIBIT_DAT_MSK       (((1U << SDH_CMD_INHIBIT_DAT_LEN) - 1) << SDH_CMD_INHIBIT_DAT_POS)
+#define SDH_CMD_INHIBIT_DAT_UMSK      (~(((1U << SDH_CMD_INHIBIT_DAT_LEN) - 1) << SDH_CMD_INHIBIT_DAT_POS))
+#define SDH__DAT_ACTIVE               SDH__DAT_ACTIVE
+#define SDH__DAT_ACTIVE_POS           (2U)
+#define SDH__DAT_ACTIVE_LEN           (1U)
+#define SDH__DAT_ACTIVE_MSK           (((1U << SDH__DAT_ACTIVE_LEN) - 1) << SDH__DAT_ACTIVE_POS)
+#define SDH__DAT_ACTIVE_UMSK          (~(((1U << SDH__DAT_ACTIVE_LEN) - 1) << SDH__DAT_ACTIVE_POS))
+#define SDH_RETUNING_REQ              SDH_RETUNING_REQ
+#define SDH_RETUNING_REQ_POS          (3U)
+#define SDH_RETUNING_REQ_LEN          (1U)
+#define SDH_RETUNING_REQ_MSK          (((1U << SDH_RETUNING_REQ_LEN) - 1) << SDH_RETUNING_REQ_POS)
+#define SDH_RETUNING_REQ_UMSK         (~(((1U << SDH_RETUNING_REQ_LEN) - 1) << SDH_RETUNING_REQ_POS))
+#define SDH_TX_ACTIVE                 SDH_TX_ACTIVE
+#define SDH_TX_ACTIVE_POS             (8U)
+#define SDH_TX_ACTIVE_LEN             (1U)
+#define SDH_TX_ACTIVE_MSK             (((1U << SDH_TX_ACTIVE_LEN) - 1) << SDH_TX_ACTIVE_POS)
+#define SDH_TX_ACTIVE_UMSK            (~(((1U << SDH_TX_ACTIVE_LEN) - 1) << SDH_TX_ACTIVE_POS))
+#define SDH_RX_ACTIVE                 SDH_RX_ACTIVE
+#define SDH_RX_ACTIVE_POS             (9U)
+#define SDH_RX_ACTIVE_LEN             (1U)
+#define SDH_RX_ACTIVE_MSK             (((1U << SDH_RX_ACTIVE_LEN) - 1) << SDH_RX_ACTIVE_POS)
+#define SDH_RX_ACTIVE_UMSK            (~(((1U << SDH_RX_ACTIVE_LEN) - 1) << SDH_RX_ACTIVE_POS))
+#define SDH_BUFFER_WR_EN              SDH_BUFFER_WR_EN
+#define SDH_BUFFER_WR_EN_POS          (10U)
+#define SDH_BUFFER_WR_EN_LEN          (1U)
+#define SDH_BUFFER_WR_EN_MSK          (((1U << SDH_BUFFER_WR_EN_LEN) - 1) << SDH_BUFFER_WR_EN_POS)
+#define SDH_BUFFER_WR_EN_UMSK         (~(((1U << SDH_BUFFER_WR_EN_LEN) - 1) << SDH_BUFFER_WR_EN_POS))
+#define SDH_BUFFER_RD_EN              SDH_BUFFER_RD_EN
+#define SDH_BUFFER_RD_EN_POS          (11U)
+#define SDH_BUFFER_RD_EN_LEN          (1U)
+#define SDH_BUFFER_RD_EN_MSK          (((1U << SDH_BUFFER_RD_EN_LEN) - 1) << SDH_BUFFER_RD_EN_POS)
+#define SDH_BUFFER_RD_EN_UMSK         (~(((1U << SDH_BUFFER_RD_EN_LEN) - 1) << SDH_BUFFER_RD_EN_POS))
+
+/* 0x26 : Present State Register 2 */
+#define SDH_SD_PRESENT_STATE_2_OFFSET (0x26)
+#define SDH_CARD_INSERTED             SDH_CARD_INSERTED
+#define SDH_CARD_INSERTED_POS         (0U)
+#define SDH_CARD_INSERTED_LEN         (1U)
+#define SDH_CARD_INSERTED_MSK         (((1U << SDH_CARD_INSERTED_LEN) - 1) << SDH_CARD_INSERTED_POS)
+#define SDH_CARD_INSERTED_UMSK        (~(((1U << SDH_CARD_INSERTED_LEN) - 1) << SDH_CARD_INSERTED_POS))
+#define SDH_CARD_STABLE               SDH_CARD_STABLE
+#define SDH_CARD_STABLE_POS           (1U)
+#define SDH_CARD_STABLE_LEN           (1U)
+#define SDH_CARD_STABLE_MSK           (((1U << SDH_CARD_STABLE_LEN) - 1) << SDH_CARD_STABLE_POS)
+#define SDH_CARD_STABLE_UMSK          (~(((1U << SDH_CARD_STABLE_LEN) - 1) << SDH_CARD_STABLE_POS))
+#define SDH_CARD_DET                  SDH_CARD_DET
+#define SDH_CARD_DET_POS              (2U)
+#define SDH_CARD_DET_LEN              (1U)
+#define SDH_CARD_DET_MSK              (((1U << SDH_CARD_DET_LEN) - 1) << SDH_CARD_DET_POS)
+#define SDH_CARD_DET_UMSK             (~(((1U << SDH_CARD_DET_LEN) - 1) << SDH_CARD_DET_POS))
+#define SDH_WRITE_PROT                SDH_WRITE_PROT
+#define SDH_WRITE_PROT_POS            (3U)
+#define SDH_WRITE_PROT_LEN            (1U)
+#define SDH_WRITE_PROT_MSK            (((1U << SDH_WRITE_PROT_LEN) - 1) << SDH_WRITE_PROT_POS)
+#define SDH_WRITE_PROT_UMSK           (~(((1U << SDH_WRITE_PROT_LEN) - 1) << SDH_WRITE_PROT_POS))
+#define SDH_DAT_LEVEL                 SDH_DAT_LEVEL
+#define SDH_DAT_LEVEL_POS             (4U)
+#define SDH_DAT_LEVEL_LEN             (4U)
+#define SDH_DAT_LEVEL_MSK             (((1U << SDH_DAT_LEVEL_LEN) - 1) << SDH_DAT_LEVEL_POS)
+#define SDH_DAT_LEVEL_UMSK            (~(((1U << SDH_DAT_LEVEL_LEN) - 1) << SDH_DAT_LEVEL_POS))
+#define SDH_CMD_LEVEL                 SDH_CMD_LEVEL
+#define SDH_CMD_LEVEL_POS             (8U)
+#define SDH_CMD_LEVEL_LEN             (1U)
+#define SDH_CMD_LEVEL_MSK             (((1U << SDH_CMD_LEVEL_LEN) - 1) << SDH_CMD_LEVEL_POS)
+#define SDH_CMD_LEVEL_UMSK            (~(((1U << SDH_CMD_LEVEL_LEN) - 1) << SDH_CMD_LEVEL_POS))
+
+/* 0x28 : Host Control Register */
+#define SDH_SD_HOST_CTRL_OFFSET (0x28)
+#define SDH_LED_CTRL            SDH_LED_CTRL
+#define SDH_LED_CTRL_POS        (0U)
+#define SDH_LED_CTRL_LEN        (1U)
+#define SDH_LED_CTRL_MSK        (((1U << SDH_LED_CTRL_LEN) - 1) << SDH_LED_CTRL_POS)
+#define SDH_LED_CTRL_UMSK       (~(((1U << SDH_LED_CTRL_LEN) - 1) << SDH_LED_CTRL_POS))
+#define SDH_DATA_WIDTH          SDH_DATA_WIDTH
+#define SDH_DATA_WIDTH_POS      (1U)
+#define SDH_DATA_WIDTH_LEN      (1U)
+#define SDH_DATA_WIDTH_MSK      (((1U << SDH_DATA_WIDTH_LEN) - 1) << SDH_DATA_WIDTH_POS)
+#define SDH_DATA_WIDTH_UMSK     (~(((1U << SDH_DATA_WIDTH_LEN) - 1) << SDH_DATA_WIDTH_POS))
+#define SDH_HI_SPEED_EN         SDH_HI_SPEED_EN
+#define SDH_HI_SPEED_EN_POS     (2U)
+#define SDH_HI_SPEED_EN_LEN     (1U)
+#define SDH_HI_SPEED_EN_MSK     (((1U << SDH_HI_SPEED_EN_LEN) - 1) << SDH_HI_SPEED_EN_POS)
+#define SDH_HI_SPEED_EN_UMSK    (~(((1U << SDH_HI_SPEED_EN_LEN) - 1) << SDH_HI_SPEED_EN_POS))
+#define SDH_DMA_SEL             SDH_DMA_SEL
+#define SDH_DMA_SEL_POS         (3U)
+#define SDH_DMA_SEL_LEN         (2U)
+#define SDH_DMA_SEL_MSK         (((1U << SDH_DMA_SEL_LEN) - 1) << SDH_DMA_SEL_POS)
+#define SDH_DMA_SEL_UMSK        (~(((1U << SDH_DMA_SEL_LEN) - 1) << SDH_DMA_SEL_POS))
+#define SDH_EX_DATA_WIDTH       SDH_EX_DATA_WIDTH
+#define SDH_EX_DATA_WIDTH_POS   (5U)
+#define SDH_EX_DATA_WIDTH_LEN   (1U)
+#define SDH_EX_DATA_WIDTH_MSK   (((1U << SDH_EX_DATA_WIDTH_LEN) - 1) << SDH_EX_DATA_WIDTH_POS)
+#define SDH_EX_DATA_WIDTH_UMSK  (~(((1U << SDH_EX_DATA_WIDTH_LEN) - 1) << SDH_EX_DATA_WIDTH_POS))
+#define SDH_CARD_DET_L          SDH_CARD_DET_L
+#define SDH_CARD_DET_L_POS      (6U)
+#define SDH_CARD_DET_L_LEN      (1U)
+#define SDH_CARD_DET_L_MSK      (((1U << SDH_CARD_DET_L_LEN) - 1) << SDH_CARD_DET_L_POS)
+#define SDH_CARD_DET_L_UMSK     (~(((1U << SDH_CARD_DET_L_LEN) - 1) << SDH_CARD_DET_L_POS))
+#define SDH_CARD_DET_S          SDH_CARD_DET_S
+#define SDH_CARD_DET_S_POS      (7U)
+#define SDH_CARD_DET_S_LEN      (1U)
+#define SDH_CARD_DET_S_MSK      (((1U << SDH_CARD_DET_S_LEN) - 1) << SDH_CARD_DET_S_POS)
+#define SDH_CARD_DET_S_UMSK     (~(((1U << SDH_CARD_DET_S_LEN) - 1) << SDH_CARD_DET_S_POS))
+#define SDH_SD_BUS_POWER        SDH_SD_BUS_POWER
+#define SDH_SD_BUS_POWER_POS    (8U)
+#define SDH_SD_BUS_POWER_LEN    (1U)
+#define SDH_SD_BUS_POWER_MSK    (((1U << SDH_SD_BUS_POWER_LEN) - 1) << SDH_SD_BUS_POWER_POS)
+#define SDH_SD_BUS_POWER_UMSK   (~(((1U << SDH_SD_BUS_POWER_LEN) - 1) << SDH_SD_BUS_POWER_POS))
+#define SDH_SD_BUS_VLT          SDH_SD_BUS_VLT
+#define SDH_SD_BUS_VLT_POS      (9U)
+#define SDH_SD_BUS_VLT_LEN      (3U)
+#define SDH_SD_BUS_VLT_MSK      (((1U << SDH_SD_BUS_VLT_LEN) - 1) << SDH_SD_BUS_VLT_POS)
+#define SDH_SD_BUS_VLT_UMSK     (~(((1U << SDH_SD_BUS_VLT_LEN) - 1) << SDH_SD_BUS_VLT_POS))
+
+/* 0x2A : Block Gap Control Register */
+#define SDH_SD_BLOCK_GAP_CTRL_OFFSET   (0x2A)
+#define SDH_STOP_AT_BLOCK_GAP_REQ      SDH_STOP_AT_BLOCK_GAP_REQ
+#define SDH_STOP_AT_BLOCK_GAP_REQ_POS  (0U)
+#define SDH_STOP_AT_BLOCK_GAP_REQ_LEN  (1U)
+#define SDH_STOP_AT_BLOCK_GAP_REQ_MSK  (((1U << SDH_STOP_AT_BLOCK_GAP_REQ_LEN) - 1) << SDH_STOP_AT_BLOCK_GAP_REQ_POS)
+#define SDH_STOP_AT_BLOCK_GAP_REQ_UMSK (~(((1U << SDH_STOP_AT_BLOCK_GAP_REQ_LEN) - 1) << SDH_STOP_AT_BLOCK_GAP_REQ_POS))
+#define SDH_CONT_REQ                   SDH_CONT_REQ
+#define SDH_CONT_REQ_POS               (1U)
+#define SDH_CONT_REQ_LEN               (1U)
+#define SDH_CONT_REQ_MSK               (((1U << SDH_CONT_REQ_LEN) - 1) << SDH_CONT_REQ_POS)
+#define SDH_CONT_REQ_UMSK              (~(((1U << SDH_CONT_REQ_LEN) - 1) << SDH_CONT_REQ_POS))
+#define SDH_RD_WAIT_CTL                SDH_RD_WAIT_CTL
+#define SDH_RD_WAIT_CTL_POS            (2U)
+#define SDH_RD_WAIT_CTL_LEN            (1U)
+#define SDH_RD_WAIT_CTL_MSK            (((1U << SDH_RD_WAIT_CTL_LEN) - 1) << SDH_RD_WAIT_CTL_POS)
+#define SDH_RD_WAIT_CTL_UMSK           (~(((1U << SDH_RD_WAIT_CTL_LEN) - 1) << SDH_RD_WAIT_CTL_POS))
+#define SDH_INT_BLK_GAP                SDH_INT_BLK_GAP
+#define SDH_INT_BLK_GAP_POS            (3U)
+#define SDH_INT_BLK_GAP_LEN            (1U)
+#define SDH_INT_BLK_GAP_MSK            (((1U << SDH_INT_BLK_GAP_LEN) - 1) << SDH_INT_BLK_GAP_POS)
+#define SDH_INT_BLK_GAP_UMSK           (~(((1U << SDH_INT_BLK_GAP_LEN) - 1) << SDH_INT_BLK_GAP_POS))
+#define SDH_W_CARD_INT                 SDH_W_CARD_INT
+#define SDH_W_CARD_INT_POS             (8U)
+#define SDH_W_CARD_INT_LEN             (1U)
+#define SDH_W_CARD_INT_MSK             (((1U << SDH_W_CARD_INT_LEN) - 1) << SDH_W_CARD_INT_POS)
+#define SDH_W_CARD_INT_UMSK            (~(((1U << SDH_W_CARD_INT_LEN) - 1) << SDH_W_CARD_INT_POS))
+#define SDH_W_INSERTION                SDH_W_INSERTION
+#define SDH_W_INSERTION_POS            (9U)
+#define SDH_W_INSERTION_LEN            (1U)
+#define SDH_W_INSERTION_MSK            (((1U << SDH_W_INSERTION_LEN) - 1) << SDH_W_INSERTION_POS)
+#define SDH_W_INSERTION_UMSK           (~(((1U << SDH_W_INSERTION_LEN) - 1) << SDH_W_INSERTION_POS))
+#define SDH_W_REMOVAL                  SDH_W_REMOVAL
+#define SDH_W_REMOVAL_POS              (10U)
+#define SDH_W_REMOVAL_LEN              (1U)
+#define SDH_W_REMOVAL_MSK              (((1U << SDH_W_REMOVAL_LEN) - 1) << SDH_W_REMOVAL_POS)
+#define SDH_W_REMOVAL_UMSK             (~(((1U << SDH_W_REMOVAL_LEN) - 1) << SDH_W_REMOVAL_POS))
+
+/* 0x2C : Clock Control Register */
+#define SDH_SD_CLOCK_CTRL_OFFSET (0x2C)
+#define SDH_INT_CLK_EN           SDH_INT_CLK_EN
+#define SDH_INT_CLK_EN_POS       (0U)
+#define SDH_INT_CLK_EN_LEN       (1U)
+#define SDH_INT_CLK_EN_MSK       (((1U << SDH_INT_CLK_EN_LEN) - 1) << SDH_INT_CLK_EN_POS)
+#define SDH_INT_CLK_EN_UMSK      (~(((1U << SDH_INT_CLK_EN_LEN) - 1) << SDH_INT_CLK_EN_POS))
+#define SDH_INT_CLK_STABLE       SDH_INT_CLK_STABLE
+#define SDH_INT_CLK_STABLE_POS   (1U)
+#define SDH_INT_CLK_STABLE_LEN   (1U)
+#define SDH_INT_CLK_STABLE_MSK   (((1U << SDH_INT_CLK_STABLE_LEN) - 1) << SDH_INT_CLK_STABLE_POS)
+#define SDH_INT_CLK_STABLE_UMSK  (~(((1U << SDH_INT_CLK_STABLE_LEN) - 1) << SDH_INT_CLK_STABLE_POS))
+#define SDH_SD_CLK_EN            SDH_SD_CLK_EN
+#define SDH_SD_CLK_EN_POS        (2U)
+#define SDH_SD_CLK_EN_LEN        (1U)
+#define SDH_SD_CLK_EN_MSK        (((1U << SDH_SD_CLK_EN_LEN) - 1) << SDH_SD_CLK_EN_POS)
+#define SDH_SD_CLK_EN_UMSK       (~(((1U << SDH_SD_CLK_EN_LEN) - 1) << SDH_SD_CLK_EN_POS))
+#define SDH_CLK_GEN_SEL          SDH_CLK_GEN_SEL
+#define SDH_CLK_GEN_SEL_POS      (5U)
+#define SDH_CLK_GEN_SEL_LEN      (1U)
+#define SDH_CLK_GEN_SEL_MSK      (((1U << SDH_CLK_GEN_SEL_LEN) - 1) << SDH_CLK_GEN_SEL_POS)
+#define SDH_CLK_GEN_SEL_UMSK     (~(((1U << SDH_CLK_GEN_SEL_LEN) - 1) << SDH_CLK_GEN_SEL_POS))
+#define SDH_SD_FREQ_SEL_HI       SDH_SD_FREQ_SEL_HI
+#define SDH_SD_FREQ_SEL_HI_POS   (6U)
+#define SDH_SD_FREQ_SEL_HI_LEN   (2U)
+#define SDH_SD_FREQ_SEL_HI_MSK   (((1U << SDH_SD_FREQ_SEL_HI_LEN) - 1) << SDH_SD_FREQ_SEL_HI_POS)
+#define SDH_SD_FREQ_SEL_HI_UMSK  (~(((1U << SDH_SD_FREQ_SEL_HI_LEN) - 1) << SDH_SD_FREQ_SEL_HI_POS))
+#define SDH_SD_FREQ_SEL_LO       SDH_SD_FREQ_SEL_LO
+#define SDH_SD_FREQ_SEL_LO_POS   (8U)
+#define SDH_SD_FREQ_SEL_LO_LEN   (8U)
+#define SDH_SD_FREQ_SEL_LO_MSK   (((1U << SDH_SD_FREQ_SEL_LO_LEN) - 1) << SDH_SD_FREQ_SEL_LO_POS)
+#define SDH_SD_FREQ_SEL_LO_UMSK  (~(((1U << SDH_SD_FREQ_SEL_LO_LEN) - 1) << SDH_SD_FREQ_SEL_LO_POS))
+
+/* 0x2E : Timeout Control/Software Reset Register */
+#define SDH_SD_TIMEOUT_CTRL_SW_RESET_OFFSET (0x2E)
+#define SDH_TIMEOUT_VALUE                   SDH_TIMEOUT_VALUE
+#define SDH_TIMEOUT_VALUE_POS               (0U)
+#define SDH_TIMEOUT_VALUE_LEN               (4U)
+#define SDH_TIMEOUT_VALUE_MSK               (((1U << SDH_TIMEOUT_VALUE_LEN) - 1) << SDH_TIMEOUT_VALUE_POS)
+#define SDH_TIMEOUT_VALUE_UMSK              (~(((1U << SDH_TIMEOUT_VALUE_LEN) - 1) << SDH_TIMEOUT_VALUE_POS))
+#define SDH_SW_RST_ALL                      SDH_SW_RST_ALL
+#define SDH_SW_RST_ALL_POS                  (8U)
+#define SDH_SW_RST_ALL_LEN                  (1U)
+#define SDH_SW_RST_ALL_MSK                  (((1U << SDH_SW_RST_ALL_LEN) - 1) << SDH_SW_RST_ALL_POS)
+#define SDH_SW_RST_ALL_UMSK                 (~(((1U << SDH_SW_RST_ALL_LEN) - 1) << SDH_SW_RST_ALL_POS))
+#define SDH_SW_RST_CMD                      SDH_SW_RST_CMD
+#define SDH_SW_RST_CMD_POS                  (9U)
+#define SDH_SW_RST_CMD_LEN                  (1U)
+#define SDH_SW_RST_CMD_MSK                  (((1U << SDH_SW_RST_CMD_LEN) - 1) << SDH_SW_RST_CMD_POS)
+#define SDH_SW_RST_CMD_UMSK                 (~(((1U << SDH_SW_RST_CMD_LEN) - 1) << SDH_SW_RST_CMD_POS))
+#define SDH_SW_RST_DAT                      SDH_SW_RST_DAT
+#define SDH_SW_RST_DAT_POS                  (10U)
+#define SDH_SW_RST_DAT_LEN                  (1U)
+#define SDH_SW_RST_DAT_MSK                  (((1U << SDH_SW_RST_DAT_LEN) - 1) << SDH_SW_RST_DAT_POS)
+#define SDH_SW_RST_DAT_UMSK                 (~(((1U << SDH_SW_RST_DAT_LEN) - 1) << SDH_SW_RST_DAT_POS))
+
+/* 0x30 : Normal Interrupt Status Register */
+#define SDH_SD_NORMAL_INT_STATUS_OFFSET (0x30)
+#define SDH_CMD_COMPLETE                SDH_CMD_COMPLETE
+#define SDH_CMD_COMPLETE_POS            (0U)
+#define SDH_CMD_COMPLETE_LEN            (1U)
+#define SDH_CMD_COMPLETE_MSK            (((1U << SDH_CMD_COMPLETE_LEN) - 1) << SDH_CMD_COMPLETE_POS)
+#define SDH_CMD_COMPLETE_UMSK           (~(((1U << SDH_CMD_COMPLETE_LEN) - 1) << SDH_CMD_COMPLETE_POS))
+#define SDH_XFER_COMPLETE               SDH_XFER_COMPLETE
+#define SDH_XFER_COMPLETE_POS           (1U)
+#define SDH_XFER_COMPLETE_LEN           (1U)
+#define SDH_XFER_COMPLETE_MSK           (((1U << SDH_XFER_COMPLETE_LEN) - 1) << SDH_XFER_COMPLETE_POS)
+#define SDH_XFER_COMPLETE_UMSK          (~(((1U << SDH_XFER_COMPLETE_LEN) - 1) << SDH_XFER_COMPLETE_POS))
+#define SDH_BLOCK_GAP_EVT               SDH_BLOCK_GAP_EVT
+#define SDH_BLOCK_GAP_EVT_POS           (2U)
+#define SDH_BLOCK_GAP_EVT_LEN           (1U)
+#define SDH_BLOCK_GAP_EVT_MSK           (((1U << SDH_BLOCK_GAP_EVT_LEN) - 1) << SDH_BLOCK_GAP_EVT_POS)
+#define SDH_BLOCK_GAP_EVT_UMSK          (~(((1U << SDH_BLOCK_GAP_EVT_LEN) - 1) << SDH_BLOCK_GAP_EVT_POS))
+#define SDH_DMA_INT                     SDH_DMA_INT
+#define SDH_DMA_INT_POS                 (3U)
+#define SDH_DMA_INT_LEN                 (1U)
+#define SDH_DMA_INT_MSK                 (((1U << SDH_DMA_INT_LEN) - 1) << SDH_DMA_INT_POS)
+#define SDH_DMA_INT_UMSK                (~(((1U << SDH_DMA_INT_LEN) - 1) << SDH_DMA_INT_POS))
+#define SDH_TX_RDY                      SDH_TX_RDY
+#define SDH_TX_RDY_POS                  (4U)
+#define SDH_TX_RDY_LEN                  (1U)
+#define SDH_TX_RDY_MSK                  (((1U << SDH_TX_RDY_LEN) - 1) << SDH_TX_RDY_POS)
+#define SDH_TX_RDY_UMSK                 (~(((1U << SDH_TX_RDY_LEN) - 1) << SDH_TX_RDY_POS))
+#define SDH_RX_RDY                      SDH_RX_RDY
+#define SDH_RX_RDY_POS                  (5U)
+#define SDH_RX_RDY_LEN                  (1U)
+#define SDH_RX_RDY_MSK                  (((1U << SDH_RX_RDY_LEN) - 1) << SDH_RX_RDY_POS)
+#define SDH_RX_RDY_UMSK                 (~(((1U << SDH_RX_RDY_LEN) - 1) << SDH_RX_RDY_POS))
+#define SDH_CARD_INS_INT                SDH_CARD_INS_INT
+#define SDH_CARD_INS_INT_POS            (6U)
+#define SDH_CARD_INS_INT_LEN            (1U)
+#define SDH_CARD_INS_INT_MSK            (((1U << SDH_CARD_INS_INT_LEN) - 1) << SDH_CARD_INS_INT_POS)
+#define SDH_CARD_INS_INT_UMSK           (~(((1U << SDH_CARD_INS_INT_LEN) - 1) << SDH_CARD_INS_INT_POS))
+#define SDH_CARD_REM_INT                SDH_CARD_REM_INT
+#define SDH_CARD_REM_INT_POS            (7U)
+#define SDH_CARD_REM_INT_LEN            (1U)
+#define SDH_CARD_REM_INT_MSK            (((1U << SDH_CARD_REM_INT_LEN) - 1) << SDH_CARD_REM_INT_POS)
+#define SDH_CARD_REM_INT_UMSK           (~(((1U << SDH_CARD_REM_INT_LEN) - 1) << SDH_CARD_REM_INT_POS))
+#define SDH_CARD_INT                    SDH_CARD_INT
+#define SDH_CARD_INT_POS                (8U)
+#define SDH_CARD_INT_LEN                (1U)
+#define SDH_CARD_INT_MSK                (((1U << SDH_CARD_INT_LEN) - 1) << SDH_CARD_INT_POS)
+#define SDH_CARD_INT_UMSK               (~(((1U << SDH_CARD_INT_LEN) - 1) << SDH_CARD_INT_POS))
+#define SDH_INT_A                       SDH_INT_A
+#define SDH_INT_A_POS                   (9U)
+#define SDH_INT_A_LEN                   (1U)
+#define SDH_INT_A_MSK                   (((1U << SDH_INT_A_LEN) - 1) << SDH_INT_A_POS)
+#define SDH_INT_A_UMSK                  (~(((1U << SDH_INT_A_LEN) - 1) << SDH_INT_A_POS))
+#define SDH_INT_B                       SDH_INT_B
+#define SDH_INT_B_POS                   (10U)
+#define SDH_INT_B_LEN                   (1U)
+#define SDH_INT_B_MSK                   (((1U << SDH_INT_B_LEN) - 1) << SDH_INT_B_POS)
+#define SDH_INT_B_UMSK                  (~(((1U << SDH_INT_B_LEN) - 1) << SDH_INT_B_POS))
+#define SDH_INT_C                       SDH_INT_C
+#define SDH_INT_C_POS                   (11U)
+#define SDH_INT_C_LEN                   (1U)
+#define SDH_INT_C_MSK                   (((1U << SDH_INT_C_LEN) - 1) << SDH_INT_C_POS)
+#define SDH_INT_C_UMSK                  (~(((1U << SDH_INT_C_LEN) - 1) << SDH_INT_C_POS))
+#define SDH_RETUNING_INT                SDH_RETUNING_INT
+#define SDH_RETUNING_INT_POS            (12U)
+#define SDH_RETUNING_INT_LEN            (1U)
+#define SDH_RETUNING_INT_MSK            (((1U << SDH_RETUNING_INT_LEN) - 1) << SDH_RETUNING_INT_POS)
+#define SDH_RETUNING_INT_UMSK           (~(((1U << SDH_RETUNING_INT_LEN) - 1) << SDH_RETUNING_INT_POS))
+#define SDH_ERR_INT                     SDH_ERR_INT
+#define SDH_ERR_INT_POS                 (15U)
+#define SDH_ERR_INT_LEN                 (1U)
+#define SDH_ERR_INT_MSK                 (((1U << SDH_ERR_INT_LEN) - 1) << SDH_ERR_INT_POS)
+#define SDH_ERR_INT_UMSK                (~(((1U << SDH_ERR_INT_LEN) - 1) << SDH_ERR_INT_POS))
+
+/* 0x32 : Error Interrupt Status Register */
+#define SDH_SD_ERROR_INT_STATUS_OFFSET (0x32)
+#define SDH_CMD_TIMEOUT_ERR            SDH_CMD_TIMEOUT_ERR
+#define SDH_CMD_TIMEOUT_ERR_POS        (0U)
+#define SDH_CMD_TIMEOUT_ERR_LEN        (1U)
+#define SDH_CMD_TIMEOUT_ERR_MSK        (((1U << SDH_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_POS)
+#define SDH_CMD_TIMEOUT_ERR_UMSK       (~(((1U << SDH_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_POS))
+#define SDH_CMD_CRC_ERR                SDH_CMD_CRC_ERR
+#define SDH_CMD_CRC_ERR_POS            (1U)
+#define SDH_CMD_CRC_ERR_LEN            (1U)
+#define SDH_CMD_CRC_ERR_MSK            (((1U << SDH_CMD_CRC_ERR_LEN) - 1) << SDH_CMD_CRC_ERR_POS)
+#define SDH_CMD_CRC_ERR_UMSK           (~(((1U << SDH_CMD_CRC_ERR_LEN) - 1) << SDH_CMD_CRC_ERR_POS))
+#define SDH_CMD_END_BIT_ERR            SDH_CMD_END_BIT_ERR
+#define SDH_CMD_END_BIT_ERR_POS        (2U)
+#define SDH_CMD_END_BIT_ERR_LEN        (1U)
+#define SDH_CMD_END_BIT_ERR_MSK        (((1U << SDH_CMD_END_BIT_ERR_LEN) - 1) << SDH_CMD_END_BIT_ERR_POS)
+#define SDH_CMD_END_BIT_ERR_UMSK       (~(((1U << SDH_CMD_END_BIT_ERR_LEN) - 1) << SDH_CMD_END_BIT_ERR_POS))
+#define SDH_CMD_INDEX_ERR              SDH_CMD_INDEX_ERR
+#define SDH_CMD_INDEX_ERR_POS          (3U)
+#define SDH_CMD_INDEX_ERR_LEN          (1U)
+#define SDH_CMD_INDEX_ERR_MSK          (((1U << SDH_CMD_INDEX_ERR_LEN) - 1) << SDH_CMD_INDEX_ERR_POS)
+#define SDH_CMD_INDEX_ERR_UMSK         (~(((1U << SDH_CMD_INDEX_ERR_LEN) - 1) << SDH_CMD_INDEX_ERR_POS))
+#define SDH_DATA_TIMEOUT_ERR           SDH_DATA_TIMEOUT_ERR
+#define SDH_DATA_TIMEOUT_ERR_POS       (4U)
+#define SDH_DATA_TIMEOUT_ERR_LEN       (1U)
+#define SDH_DATA_TIMEOUT_ERR_MSK       (((1U << SDH_DATA_TIMEOUT_ERR_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_POS)
+#define SDH_DATA_TIMEOUT_ERR_UMSK      (~(((1U << SDH_DATA_TIMEOUT_ERR_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_POS))
+#define SDH_RD_DATA_CRC_ERR            SDH_RD_DATA_CRC_ERR
+#define SDH_RD_DATA_CRC_ERR_POS        (5U)
+#define SDH_RD_DATA_CRC_ERR_LEN        (1U)
+#define SDH_RD_DATA_CRC_ERR_MSK        (((1U << SDH_RD_DATA_CRC_ERR_LEN) - 1) << SDH_RD_DATA_CRC_ERR_POS)
+#define SDH_RD_DATA_CRC_ERR_UMSK       (~(((1U << SDH_RD_DATA_CRC_ERR_LEN) - 1) << SDH_RD_DATA_CRC_ERR_POS))
+#define SDH_RD_DATA_END_BIT_ERR        SDH_RD_DATA_END_BIT_ERR
+#define SDH_RD_DATA_END_BIT_ERR_POS    (6U)
+#define SDH_RD_DATA_END_BIT_ERR_LEN    (1U)
+#define SDH_RD_DATA_END_BIT_ERR_MSK    (((1U << SDH_RD_DATA_END_BIT_ERR_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_POS)
+#define SDH_RD_DATA_END_BIT_ERR_UMSK   (~(((1U << SDH_RD_DATA_END_BIT_ERR_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_POS))
+#define SDH_CUR_LIMIT_ERR              SDH_CUR_LIMIT_ERR
+#define SDH_CUR_LIMIT_ERR_POS          (7U)
+#define SDH_CUR_LIMIT_ERR_LEN          (1U)
+#define SDH_CUR_LIMIT_ERR_MSK          (((1U << SDH_CUR_LIMIT_ERR_LEN) - 1) << SDH_CUR_LIMIT_ERR_POS)
+#define SDH_CUR_LIMIT_ERR_UMSK         (~(((1U << SDH_CUR_LIMIT_ERR_LEN) - 1) << SDH_CUR_LIMIT_ERR_POS))
+#define SDH_AUTO_CMD12_ERR             SDH_AUTO_CMD12_ERR
+#define SDH_AUTO_CMD12_ERR_POS         (8U)
+#define SDH_AUTO_CMD12_ERR_LEN         (1U)
+#define SDH_AUTO_CMD12_ERR_MSK         (((1U << SDH_AUTO_CMD12_ERR_LEN) - 1) << SDH_AUTO_CMD12_ERR_POS)
+#define SDH_AUTO_CMD12_ERR_UMSK        (~(((1U << SDH_AUTO_CMD12_ERR_LEN) - 1) << SDH_AUTO_CMD12_ERR_POS))
+#define SDH_ADMA_ERR                   SDH_ADMA_ERR
+#define SDH_ADMA_ERR_POS               (9U)
+#define SDH_ADMA_ERR_LEN               (1U)
+#define SDH_ADMA_ERR_MSK               (((1U << SDH_ADMA_ERR_LEN) - 1) << SDH_ADMA_ERR_POS)
+#define SDH_ADMA_ERR_UMSK              (~(((1U << SDH_ADMA_ERR_LEN) - 1) << SDH_ADMA_ERR_POS))
+#define SDH_TUNE_ERR                   SDH_TUNE_ERR
+#define SDH_TUNE_ERR_POS               (10U)
+#define SDH_TUNE_ERR_LEN               (1U)
+#define SDH_TUNE_ERR_MSK               (((1U << SDH_TUNE_ERR_LEN) - 1) << SDH_TUNE_ERR_POS)
+#define SDH_TUNE_ERR_UMSK              (~(((1U << SDH_TUNE_ERR_LEN) - 1) << SDH_TUNE_ERR_POS))
+#define SDH_SPI_ERR                    SDH_SPI_ERR
+#define SDH_SPI_ERR_POS                (12U)
+#define SDH_SPI_ERR_LEN                (1U)
+#define SDH_SPI_ERR_MSK                (((1U << SDH_SPI_ERR_LEN) - 1) << SDH_SPI_ERR_POS)
+#define SDH_SPI_ERR_UMSK               (~(((1U << SDH_SPI_ERR_LEN) - 1) << SDH_SPI_ERR_POS))
+#define SDH_AXI_RESP_ERR               SDH_AXI_RESP_ERR
+#define SDH_AXI_RESP_ERR_POS           (13U)
+#define SDH_AXI_RESP_ERR_LEN           (1U)
+#define SDH_AXI_RESP_ERR_MSK           (((1U << SDH_AXI_RESP_ERR_LEN) - 1) << SDH_AXI_RESP_ERR_POS)
+#define SDH_AXI_RESP_ERR_UMSK          (~(((1U << SDH_AXI_RESP_ERR_LEN) - 1) << SDH_AXI_RESP_ERR_POS))
+#define SDH_CPL_TIMEOUT_ERR            SDH_CPL_TIMEOUT_ERR
+#define SDH_CPL_TIMEOUT_ERR_POS        (14U)
+#define SDH_CPL_TIMEOUT_ERR_LEN        (1U)
+#define SDH_CPL_TIMEOUT_ERR_MSK        (((1U << SDH_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_POS)
+#define SDH_CPL_TIMEOUT_ERR_UMSK       (~(((1U << SDH_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_POS))
+#define SDH_CRC_STATUS_ERR             SDH_CRC_STATUS_ERR
+#define SDH_CRC_STATUS_ERR_POS         (15U)
+#define SDH_CRC_STATUS_ERR_LEN         (1U)
+#define SDH_CRC_STATUS_ERR_MSK         (((1U << SDH_CRC_STATUS_ERR_LEN) - 1) << SDH_CRC_STATUS_ERR_POS)
+#define SDH_CRC_STATUS_ERR_UMSK        (~(((1U << SDH_CRC_STATUS_ERR_LEN) - 1) << SDH_CRC_STATUS_ERR_POS))
+
+/* 0x34 : Normal Interrupt Status Enable Register */
+#define SDH_SD_NORMAL_INT_STATUS_EN_OFFSET (0x34)
+#define SDH_CMD_COMPLETE_EN                SDH_CMD_COMPLETE_EN
+#define SDH_CMD_COMPLETE_EN_POS            (0U)
+#define SDH_CMD_COMPLETE_EN_LEN            (1U)
+#define SDH_CMD_COMPLETE_EN_MSK            (((1U << SDH_CMD_COMPLETE_EN_LEN) - 1) << SDH_CMD_COMPLETE_EN_POS)
+#define SDH_CMD_COMPLETE_EN_UMSK           (~(((1U << SDH_CMD_COMPLETE_EN_LEN) - 1) << SDH_CMD_COMPLETE_EN_POS))
+#define SDH_XFER_COMPLETE_EN               SDH_XFER_COMPLETE_EN
+#define SDH_XFER_COMPLETE_EN_POS           (1U)
+#define SDH_XFER_COMPLETE_EN_LEN           (1U)
+#define SDH_XFER_COMPLETE_EN_MSK           (((1U << SDH_XFER_COMPLETE_EN_LEN) - 1) << SDH_XFER_COMPLETE_EN_POS)
+#define SDH_XFER_COMPLETE_EN_UMSK          (~(((1U << SDH_XFER_COMPLETE_EN_LEN) - 1) << SDH_XFER_COMPLETE_EN_POS))
+#define SDH_BLOCK_GAP_EVT_EN               SDH_BLOCK_GAP_EVT_EN
+#define SDH_BLOCK_GAP_EVT_EN_POS           (2U)
+#define SDH_BLOCK_GAP_EVT_EN_LEN           (1U)
+#define SDH_BLOCK_GAP_EVT_EN_MSK           (((1U << SDH_BLOCK_GAP_EVT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_EN_POS)
+#define SDH_BLOCK_GAP_EVT_EN_UMSK          (~(((1U << SDH_BLOCK_GAP_EVT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_EN_POS))
+#define SDH_DMA_INT_EN                     SDH_DMA_INT_EN
+#define SDH_DMA_INT_EN_POS                 (3U)
+#define SDH_DMA_INT_EN_LEN                 (1U)
+#define SDH_DMA_INT_EN_MSK                 (((1U << SDH_DMA_INT_EN_LEN) - 1) << SDH_DMA_INT_EN_POS)
+#define SDH_DMA_INT_EN_UMSK                (~(((1U << SDH_DMA_INT_EN_LEN) - 1) << SDH_DMA_INT_EN_POS))
+#define SDH_TX_RDY_EN                      SDH_TX_RDY_EN
+#define SDH_TX_RDY_EN_POS                  (4U)
+#define SDH_TX_RDY_EN_LEN                  (1U)
+#define SDH_TX_RDY_EN_MSK                  (((1U << SDH_TX_RDY_EN_LEN) - 1) << SDH_TX_RDY_EN_POS)
+#define SDH_TX_RDY_EN_UMSK                 (~(((1U << SDH_TX_RDY_EN_LEN) - 1) << SDH_TX_RDY_EN_POS))
+#define SDH_RD_RDY_EN                      SDH_RD_RDY_EN
+#define SDH_RD_RDY_EN_POS                  (5U)
+#define SDH_RD_RDY_EN_LEN                  (1U)
+#define SDH_RD_RDY_EN_MSK                  (((1U << SDH_RD_RDY_EN_LEN) - 1) << SDH_RD_RDY_EN_POS)
+#define SDH_RD_RDY_EN_UMSK                 (~(((1U << SDH_RD_RDY_EN_LEN) - 1) << SDH_RD_RDY_EN_POS))
+#define SDH_CARD_INS_EN                    SDH_CARD_INS_EN
+#define SDH_CARD_INS_EN_POS                (6U)
+#define SDH_CARD_INS_EN_LEN                (1U)
+#define SDH_CARD_INS_EN_MSK                (((1U << SDH_CARD_INS_EN_LEN) - 1) << SDH_CARD_INS_EN_POS)
+#define SDH_CARD_INS_EN_UMSK               (~(((1U << SDH_CARD_INS_EN_LEN) - 1) << SDH_CARD_INS_EN_POS))
+#define SDH_CARD_REM_EN                    SDH_CARD_REM_EN
+#define SDH_CARD_REM_EN_POS                (7U)
+#define SDH_CARD_REM_EN_LEN                (1U)
+#define SDH_CARD_REM_EN_MSK                (((1U << SDH_CARD_REM_EN_LEN) - 1) << SDH_CARD_REM_EN_POS)
+#define SDH_CARD_REM_EN_UMSK               (~(((1U << SDH_CARD_REM_EN_LEN) - 1) << SDH_CARD_REM_EN_POS))
+#define SDH_CARD_INT_EN                    SDH_CARD_INT_EN
+#define SDH_CARD_INT_EN_POS                (8U)
+#define SDH_CARD_INT_EN_LEN                (1U)
+#define SDH_CARD_INT_EN_MSK                (((1U << SDH_CARD_INT_EN_LEN) - 1) << SDH_CARD_INT_EN_POS)
+#define SDH_CARD_INT_EN_UMSK               (~(((1U << SDH_CARD_INT_EN_LEN) - 1) << SDH_CARD_INT_EN_POS))
+#define SDH_INT_A_INT_EN                   SDH_INT_A_INT_EN
+#define SDH_INT_A_INT_EN_POS               (9U)
+#define SDH_INT_A_INT_EN_LEN               (1U)
+#define SDH_INT_A_INT_EN_MSK               (((1U << SDH_INT_A_INT_EN_LEN) - 1) << SDH_INT_A_INT_EN_POS)
+#define SDH_INT_A_INT_EN_UMSK              (~(((1U << SDH_INT_A_INT_EN_LEN) - 1) << SDH_INT_A_INT_EN_POS))
+#define SDH_INT_B_INT_EN                   SDH_INT_B_INT_EN
+#define SDH_INT_B_INT_EN_POS               (10U)
+#define SDH_INT_B_INT_EN_LEN               (1U)
+#define SDH_INT_B_INT_EN_MSK               (((1U << SDH_INT_B_INT_EN_LEN) - 1) << SDH_INT_B_INT_EN_POS)
+#define SDH_INT_B_INT_EN_UMSK              (~(((1U << SDH_INT_B_INT_EN_LEN) - 1) << SDH_INT_B_INT_EN_POS))
+#define SDH_INT_C_INT_EN                   SDH_INT_C_INT_EN
+#define SDH_INT_C_INT_EN_POS               (11U)
+#define SDH_INT_C_INT_EN_LEN               (1U)
+#define SDH_INT_C_INT_EN_MSK               (((1U << SDH_INT_C_INT_EN_LEN) - 1) << SDH_INT_C_INT_EN_POS)
+#define SDH_INT_C_INT_EN_UMSK              (~(((1U << SDH_INT_C_INT_EN_LEN) - 1) << SDH_INT_C_INT_EN_POS))
+#define SDH_RETUNE_INT_EN                  SDH_RETUNE_INT_EN
+#define SDH_RETUNE_INT_EN_POS              (12U)
+#define SDH_RETUNE_INT_EN_LEN              (1U)
+#define SDH_RETUNE_INT_EN_MSK              (((1U << SDH_RETUNE_INT_EN_LEN) - 1) << SDH_RETUNE_INT_EN_POS)
+#define SDH_RETUNE_INT_EN_UMSK             (~(((1U << SDH_RETUNE_INT_EN_LEN) - 1) << SDH_RETUNE_INT_EN_POS))
+
+/* 0x36 : Error Interrupt Status Enable Register */
+#define SDH_SD_ERROR_INT_STATUS_EN_OFFSET (0x36)
+#define SDH_CMD_TIMEOUT_ERR_EN            SDH_CMD_TIMEOUT_ERR_EN
+#define SDH_CMD_TIMEOUT_ERR_EN_POS        (0U)
+#define SDH_CMD_TIMEOUT_ERR_EN_LEN        (1U)
+#define SDH_CMD_TIMEOUT_ERR_EN_MSK        (((1U << SDH_CMD_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_EN_POS)
+#define SDH_CMD_TIMEOUT_ERR_EN_UMSK       (~(((1U << SDH_CMD_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_EN_POS))
+#define SDH_CMD_CRC_ERR_EN                SDH_CMD_CRC_ERR_EN
+#define SDH_CMD_CRC_ERR_EN_POS            (1U)
+#define SDH_CMD_CRC_ERR_EN_LEN            (1U)
+#define SDH_CMD_CRC_ERR_EN_MSK            (((1U << SDH_CMD_CRC_ERR_EN_LEN) - 1) << SDH_CMD_CRC_ERR_EN_POS)
+#define SDH_CMD_CRC_ERR_EN_UMSK           (~(((1U << SDH_CMD_CRC_ERR_EN_LEN) - 1) << SDH_CMD_CRC_ERR_EN_POS))
+#define SDH_CMD_END_BIT_ERR_EN            SDH_CMD_END_BIT_ERR_EN
+#define SDH_CMD_END_BIT_ERR_EN_POS        (2U)
+#define SDH_CMD_END_BIT_ERR_EN_LEN        (1U)
+#define SDH_CMD_END_BIT_ERR_EN_MSK        (((1U << SDH_CMD_END_BIT_ERR_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_EN_POS)
+#define SDH_CMD_END_BIT_ERR_EN_UMSK       (~(((1U << SDH_CMD_END_BIT_ERR_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_EN_POS))
+#define SDH_CMD_INDEX_ERR_EN              SDH_CMD_INDEX_ERR_EN
+#define SDH_CMD_INDEX_ERR_EN_POS          (3U)
+#define SDH_CMD_INDEX_ERR_EN_LEN          (1U)
+#define SDH_CMD_INDEX_ERR_EN_MSK          (((1U << SDH_CMD_INDEX_ERR_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_EN_POS)
+#define SDH_CMD_INDEX_ERR_EN_UMSK         (~(((1U << SDH_CMD_INDEX_ERR_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_EN_POS))
+#define SDH_DATA_TIMEOUT_ERR_EN           SDH_DATA_TIMEOUT_ERR_EN
+#define SDH_DATA_TIMEOUT_ERR_EN_POS       (4U)
+#define SDH_DATA_TIMEOUT_ERR_EN_LEN       (1U)
+#define SDH_DATA_TIMEOUT_ERR_EN_MSK       (((1U << SDH_DATA_TIMEOUT_ERR_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_EN_POS)
+#define SDH_DATA_TIMEOUT_ERR_EN_UMSK      (~(((1U << SDH_DATA_TIMEOUT_ERR_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_EN_POS))
+#define SDH_RD_DATA_CRC_ERR_EN            SDH_RD_DATA_CRC_ERR_EN
+#define SDH_RD_DATA_CRC_ERR_EN_POS        (5U)
+#define SDH_RD_DATA_CRC_ERR_EN_LEN        (1U)
+#define SDH_RD_DATA_CRC_ERR_EN_MSK        (((1U << SDH_RD_DATA_CRC_ERR_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_EN_POS)
+#define SDH_RD_DATA_CRC_ERR_EN_UMSK       (~(((1U << SDH_RD_DATA_CRC_ERR_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_EN_POS))
+#define SDH_RD_DATA_END_BIT_ERR_EN        SDH_RD_DATA_END_BIT_ERR_EN
+#define SDH_RD_DATA_END_BIT_ERR_EN_POS    (6U)
+#define SDH_RD_DATA_END_BIT_ERR_EN_LEN    (1U)
+#define SDH_RD_DATA_END_BIT_ERR_EN_MSK    (((1U << SDH_RD_DATA_END_BIT_ERR_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_EN_POS)
+#define SDH_RD_DATA_END_BIT_ERR_EN_UMSK   (~(((1U << SDH_RD_DATA_END_BIT_ERR_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_EN_POS))
+#define SDH_CUR_LIM_ERR_EN                SDH_CUR_LIM_ERR_EN
+#define SDH_CUR_LIM_ERR_EN_POS            (7U)
+#define SDH_CUR_LIM_ERR_EN_LEN            (1U)
+#define SDH_CUR_LIM_ERR_EN_MSK            (((1U << SDH_CUR_LIM_ERR_EN_LEN) - 1) << SDH_CUR_LIM_ERR_EN_POS)
+#define SDH_CUR_LIM_ERR_EN_UMSK           (~(((1U << SDH_CUR_LIM_ERR_EN_LEN) - 1) << SDH_CUR_LIM_ERR_EN_POS))
+#define SDH_AUTO_CMD12_ERR_EN             SDH_AUTO_CMD12_ERR_EN
+#define SDH_AUTO_CMD12_ERR_EN_POS         (8U)
+#define SDH_AUTO_CMD12_ERR_EN_LEN         (1U)
+#define SDH_AUTO_CMD12_ERR_EN_MSK         (((1U << SDH_AUTO_CMD12_ERR_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_EN_POS)
+#define SDH_AUTO_CMD12_ERR_EN_UMSK        (~(((1U << SDH_AUTO_CMD12_ERR_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_EN_POS))
+#define SDH_ADMA_ERR_EN                   SDH_ADMA_ERR_EN
+#define SDH_ADMA_ERR_EN_POS               (9U)
+#define SDH_ADMA_ERR_EN_LEN               (1U)
+#define SDH_ADMA_ERR_EN_MSK               (((1U << SDH_ADMA_ERR_EN_LEN) - 1) << SDH_ADMA_ERR_EN_POS)
+#define SDH_ADMA_ERR_EN_UMSK              (~(((1U << SDH_ADMA_ERR_EN_LEN) - 1) << SDH_ADMA_ERR_EN_POS))
+#define SDH_TUNING_ERR_EN                 SDH_TUNING_ERR_EN
+#define SDH_TUNING_ERR_EN_POS             (10U)
+#define SDH_TUNING_ERR_EN_LEN             (1U)
+#define SDH_TUNING_ERR_EN_MSK             (((1U << SDH_TUNING_ERR_EN_LEN) - 1) << SDH_TUNING_ERR_EN_POS)
+#define SDH_TUNING_ERR_EN_UMSK            (~(((1U << SDH_TUNING_ERR_EN_LEN) - 1) << SDH_TUNING_ERR_EN_POS))
+#define SDH_SPI_ERR_EN                    SDH_SPI_ERR_EN
+#define SDH_SPI_ERR_EN_POS                (12U)
+#define SDH_SPI_ERR_EN_LEN                (1U)
+#define SDH_SPI_ERR_EN_MSK                (((1U << SDH_SPI_ERR_EN_LEN) - 1) << SDH_SPI_ERR_EN_POS)
+#define SDH_SPI_ERR_EN_UMSK               (~(((1U << SDH_SPI_ERR_EN_LEN) - 1) << SDH_SPI_ERR_EN_POS))
+#define SDH_AXI_RESP_ERR_EN               SDH_AXI_RESP_ERR_EN
+#define SDH_AXI_RESP_ERR_EN_POS           (13U)
+#define SDH_AXI_RESP_ERR_EN_LEN           (1U)
+#define SDH_AXI_RESP_ERR_EN_MSK           (((1U << SDH_AXI_RESP_ERR_EN_LEN) - 1) << SDH_AXI_RESP_ERR_EN_POS)
+#define SDH_AXI_RESP_ERR_EN_UMSK          (~(((1U << SDH_AXI_RESP_ERR_EN_LEN) - 1) << SDH_AXI_RESP_ERR_EN_POS))
+#define SDH_CPL_TIMEOUT_ERR_EN            SDH_CPL_TIMEOUT_ERR_EN
+#define SDH_CPL_TIMEOUT_ERR_EN_POS        (14U)
+#define SDH_CPL_TIMEOUT_ERR_EN_LEN        (1U)
+#define SDH_CPL_TIMEOUT_ERR_EN_MSK        (((1U << SDH_CPL_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_EN_POS)
+#define SDH_CPL_TIMEOUT_ERR_EN_UMSK       (~(((1U << SDH_CPL_TIMEOUT_ERR_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_EN_POS))
+#define SDH_CRC_STATUS_ERR_EN             SDH_CRC_STATUS_ERR_EN
+#define SDH_CRC_STATUS_ERR_EN_POS         (15U)
+#define SDH_CRC_STATUS_ERR_EN_LEN         (1U)
+#define SDH_CRC_STATUS_ERR_EN_MSK         (((1U << SDH_CRC_STATUS_ERR_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_EN_POS)
+#define SDH_CRC_STATUS_ERR_EN_UMSK        (~(((1U << SDH_CRC_STATUS_ERR_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_EN_POS))
+
+/* 0x38 : Normal Interrupt Status Interrupt Enable Register */
+#define SDH_SD_NORMAL_INT_STATUS_INT_EN_OFFSET (0x38)
+#define SDH_CMD_COMPLETE_INT_EN                SDH_CMD_COMPLETE_INT_EN
+#define SDH_CMD_COMPLETE_INT_EN_POS            (0U)
+#define SDH_CMD_COMPLETE_INT_EN_LEN            (1U)
+#define SDH_CMD_COMPLETE_INT_EN_MSK            (((1U << SDH_CMD_COMPLETE_INT_EN_LEN) - 1) << SDH_CMD_COMPLETE_INT_EN_POS)
+#define SDH_CMD_COMPLETE_INT_EN_UMSK           (~(((1U << SDH_CMD_COMPLETE_INT_EN_LEN) - 1) << SDH_CMD_COMPLETE_INT_EN_POS))
+#define SDH_XFER_COMPLETE_INT_EN               SDH_XFER_COMPLETE_INT_EN
+#define SDH_XFER_COMPLETE_INT_EN_POS           (1U)
+#define SDH_XFER_COMPLETE_INT_EN_LEN           (1U)
+#define SDH_XFER_COMPLETE_INT_EN_MSK           (((1U << SDH_XFER_COMPLETE_INT_EN_LEN) - 1) << SDH_XFER_COMPLETE_INT_EN_POS)
+#define SDH_XFER_COMPLETE_INT_EN_UMSK          (~(((1U << SDH_XFER_COMPLETE_INT_EN_LEN) - 1) << SDH_XFER_COMPLETE_INT_EN_POS))
+#define SDH_BLOCK_GAP_EVT_INT_EN               SDH_BLOCK_GAP_EVT_INT_EN
+#define SDH_BLOCK_GAP_EVT_INT_EN_POS           (2U)
+#define SDH_BLOCK_GAP_EVT_INT_EN_LEN           (1U)
+#define SDH_BLOCK_GAP_EVT_INT_EN_MSK           (((1U << SDH_BLOCK_GAP_EVT_INT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_INT_EN_POS)
+#define SDH_BLOCK_GAP_EVT_INT_EN_UMSK          (~(((1U << SDH_BLOCK_GAP_EVT_INT_EN_LEN) - 1) << SDH_BLOCK_GAP_EVT_INT_EN_POS))
+#define SDH_DMA_INT_INT_EN                     SDH_DMA_INT_INT_EN
+#define SDH_DMA_INT_INT_EN_POS                 (3U)
+#define SDH_DMA_INT_INT_EN_LEN                 (1U)
+#define SDH_DMA_INT_INT_EN_MSK                 (((1U << SDH_DMA_INT_INT_EN_LEN) - 1) << SDH_DMA_INT_INT_EN_POS)
+#define SDH_DMA_INT_INT_EN_UMSK                (~(((1U << SDH_DMA_INT_INT_EN_LEN) - 1) << SDH_DMA_INT_INT_EN_POS))
+#define SDH_TX_RDY_INT_EN                      SDH_TX_RDY_INT_EN
+#define SDH_TX_RDY_INT_EN_POS                  (4U)
+#define SDH_TX_RDY_INT_EN_LEN                  (1U)
+#define SDH_TX_RDY_INT_EN_MSK                  (((1U << SDH_TX_RDY_INT_EN_LEN) - 1) << SDH_TX_RDY_INT_EN_POS)
+#define SDH_TX_RDY_INT_EN_UMSK                 (~(((1U << SDH_TX_RDY_INT_EN_LEN) - 1) << SDH_TX_RDY_INT_EN_POS))
+#define SDH_RX_RDY_INT_EN                      SDH_RX_RDY_INT_EN
+#define SDH_RX_RDY_INT_EN_POS                  (5U)
+#define SDH_RX_RDY_INT_EN_LEN                  (1U)
+#define SDH_RX_RDY_INT_EN_MSK                  (((1U << SDH_RX_RDY_INT_EN_LEN) - 1) << SDH_RX_RDY_INT_EN_POS)
+#define SDH_RX_RDY_INT_EN_UMSK                 (~(((1U << SDH_RX_RDY_INT_EN_LEN) - 1) << SDH_RX_RDY_INT_EN_POS))
+#define SDH_CARD_INS_INT_EN                    SDH_CARD_INS_INT_EN
+#define SDH_CARD_INS_INT_EN_POS                (6U)
+#define SDH_CARD_INS_INT_EN_LEN                (1U)
+#define SDH_CARD_INS_INT_EN_MSK                (((1U << SDH_CARD_INS_INT_EN_LEN) - 1) << SDH_CARD_INS_INT_EN_POS)
+#define SDH_CARD_INS_INT_EN_UMSK               (~(((1U << SDH_CARD_INS_INT_EN_LEN) - 1) << SDH_CARD_INS_INT_EN_POS))
+#define SDH_CARD_REM_INT_EN                    SDH_CARD_REM_INT_EN
+#define SDH_CARD_REM_INT_EN_POS                (7U)
+#define SDH_CARD_REM_INT_EN_LEN                (1U)
+#define SDH_CARD_REM_INT_EN_MSK                (((1U << SDH_CARD_REM_INT_EN_LEN) - 1) << SDH_CARD_REM_INT_EN_POS)
+#define SDH_CARD_REM_INT_EN_UMSK               (~(((1U << SDH_CARD_REM_INT_EN_LEN) - 1) << SDH_CARD_REM_INT_EN_POS))
+#define SDH_CARD_INT_INT_EN                    SDH_CARD_INT_INT_EN
+#define SDH_CARD_INT_INT_EN_POS                (8U)
+#define SDH_CARD_INT_INT_EN_LEN                (1U)
+#define SDH_CARD_INT_INT_EN_MSK                (((1U << SDH_CARD_INT_INT_EN_LEN) - 1) << SDH_CARD_INT_INT_EN_POS)
+#define SDH_CARD_INT_INT_EN_UMSK               (~(((1U << SDH_CARD_INT_INT_EN_LEN) - 1) << SDH_CARD_INT_INT_EN_POS))
+#define SDH_INT_A_INT_INT_EN                   SDH_INT_A_INT_INT_EN
+#define SDH_INT_A_INT_INT_EN_POS               (9U)
+#define SDH_INT_A_INT_INT_EN_LEN               (1U)
+#define SDH_INT_A_INT_INT_EN_MSK               (((1U << SDH_INT_A_INT_INT_EN_LEN) - 1) << SDH_INT_A_INT_INT_EN_POS)
+#define SDH_INT_A_INT_INT_EN_UMSK              (~(((1U << SDH_INT_A_INT_INT_EN_LEN) - 1) << SDH_INT_A_INT_INT_EN_POS))
+#define SDH_INT_B_INT_INT_EN                   SDH_INT_B_INT_INT_EN
+#define SDH_INT_B_INT_INT_EN_POS               (10U)
+#define SDH_INT_B_INT_INT_EN_LEN               (1U)
+#define SDH_INT_B_INT_INT_EN_MSK               (((1U << SDH_INT_B_INT_INT_EN_LEN) - 1) << SDH_INT_B_INT_INT_EN_POS)
+#define SDH_INT_B_INT_INT_EN_UMSK              (~(((1U << SDH_INT_B_INT_INT_EN_LEN) - 1) << SDH_INT_B_INT_INT_EN_POS))
+#define SDH_INT_C_INT_INT_EN                   SDH_INT_C_INT_INT_EN
+#define SDH_INT_C_INT_INT_EN_POS               (11U)
+#define SDH_INT_C_INT_INT_EN_LEN               (1U)
+#define SDH_INT_C_INT_INT_EN_MSK               (((1U << SDH_INT_C_INT_INT_EN_LEN) - 1) << SDH_INT_C_INT_INT_EN_POS)
+#define SDH_INT_C_INT_INT_EN_UMSK              (~(((1U << SDH_INT_C_INT_INT_EN_LEN) - 1) << SDH_INT_C_INT_INT_EN_POS))
+#define SDH_RETUNE_INT_INT_EN                  SDH_RETUNE_INT_INT_EN
+#define SDH_RETUNE_INT_INT_EN_POS              (12U)
+#define SDH_RETUNE_INT_INT_EN_LEN              (1U)
+#define SDH_RETUNE_INT_INT_EN_MSK              (((1U << SDH_RETUNE_INT_INT_EN_LEN) - 1) << SDH_RETUNE_INT_INT_EN_POS)
+#define SDH_RETUNE_INT_INT_EN_UMSK             (~(((1U << SDH_RETUNE_INT_INT_EN_LEN) - 1) << SDH_RETUNE_INT_INT_EN_POS))
+
+/* 0x3A : Error Interrupt Status Interrupt Enable Register */
+#define SDH_SD_ERROR_INT_STATUS_INT_EN_OFFSET (0x3A)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN            SDH_CMD_TIMEOUT_ERR_INT_EN
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_POS        (0U)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_LEN        (1U)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_MSK        (((1U << SDH_CMD_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_INT_EN_POS)
+#define SDH_CMD_TIMEOUT_ERR_INT_EN_UMSK       (~(((1U << SDH_CMD_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CMD_TIMEOUT_ERR_INT_EN_POS))
+#define SDH_CMD_CRC_ERR_INT_EN                SDH_CMD_CRC_ERR_INT_EN
+#define SDH_CMD_CRC_ERR_INT_EN_POS            (1U)
+#define SDH_CMD_CRC_ERR_INT_EN_LEN            (1U)
+#define SDH_CMD_CRC_ERR_INT_EN_MSK            (((1U << SDH_CMD_CRC_ERR_INT_EN_LEN) - 1) << SDH_CMD_CRC_ERR_INT_EN_POS)
+#define SDH_CMD_CRC_ERR_INT_EN_UMSK           (~(((1U << SDH_CMD_CRC_ERR_INT_EN_LEN) - 1) << SDH_CMD_CRC_ERR_INT_EN_POS))
+#define SDH_CMD_END_BIT_ERR_INT_EN            SDH_CMD_END_BIT_ERR_INT_EN
+#define SDH_CMD_END_BIT_ERR_INT_EN_POS        (2U)
+#define SDH_CMD_END_BIT_ERR_INT_EN_LEN        (1U)
+#define SDH_CMD_END_BIT_ERR_INT_EN_MSK        (((1U << SDH_CMD_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_INT_EN_POS)
+#define SDH_CMD_END_BIT_ERR_INT_EN_UMSK       (~(((1U << SDH_CMD_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_CMD_END_BIT_ERR_INT_EN_POS))
+#define SDH_CMD_INDEX_ERR_INT_EN              SDH_CMD_INDEX_ERR_INT_EN
+#define SDH_CMD_INDEX_ERR_INT_EN_POS          (3U)
+#define SDH_CMD_INDEX_ERR_INT_EN_LEN          (1U)
+#define SDH_CMD_INDEX_ERR_INT_EN_MSK          (((1U << SDH_CMD_INDEX_ERR_INT_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_INT_EN_POS)
+#define SDH_CMD_INDEX_ERR_INT_EN_UMSK         (~(((1U << SDH_CMD_INDEX_ERR_INT_EN_LEN) - 1) << SDH_CMD_INDEX_ERR_INT_EN_POS))
+#define SDH_DATA_TIMEOUT_ERR_INT_EN           SDH_DATA_TIMEOUT_ERR_INT_EN
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_POS       (4U)
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_LEN       (1U)
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_MSK       (((1U << SDH_DATA_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_INT_EN_POS)
+#define SDH_DATA_TIMEOUT_ERR_INT_EN_UMSK      (~(((1U << SDH_DATA_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_DATA_TIMEOUT_ERR_INT_EN_POS))
+#define SDH_RD_DATA_CRC_ERR_INT_EN            SDH_RD_DATA_CRC_ERR_INT_EN
+#define SDH_RD_DATA_CRC_ERR_INT_EN_POS        (5U)
+#define SDH_RD_DATA_CRC_ERR_INT_EN_LEN        (1U)
+#define SDH_RD_DATA_CRC_ERR_INT_EN_MSK        (((1U << SDH_RD_DATA_CRC_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_INT_EN_POS)
+#define SDH_RD_DATA_CRC_ERR_INT_EN_UMSK       (~(((1U << SDH_RD_DATA_CRC_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_CRC_ERR_INT_EN_POS))
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN        SDH_RD_DATA_END_BIT_ERR_INT_EN
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_POS    (6U)
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_LEN    (1U)
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_MSK    (((1U << SDH_RD_DATA_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_INT_EN_POS)
+#define SDH_RD_DATA_END_BIT_ERR_INT_EN_UMSK   (~(((1U << SDH_RD_DATA_END_BIT_ERR_INT_EN_LEN) - 1) << SDH_RD_DATA_END_BIT_ERR_INT_EN_POS))
+#define SDH_CUR_LIM_ERR_INT_EN                SDH_CUR_LIM_ERR_INT_EN
+#define SDH_CUR_LIM_ERR_INT_EN_POS            (7U)
+#define SDH_CUR_LIM_ERR_INT_EN_LEN            (1U)
+#define SDH_CUR_LIM_ERR_INT_EN_MSK            (((1U << SDH_CUR_LIM_ERR_INT_EN_LEN) - 1) << SDH_CUR_LIM_ERR_INT_EN_POS)
+#define SDH_CUR_LIM_ERR_INT_EN_UMSK           (~(((1U << SDH_CUR_LIM_ERR_INT_EN_LEN) - 1) << SDH_CUR_LIM_ERR_INT_EN_POS))
+#define SDH_AUTO_CMD12_ERR_INT_EN             SDH_AUTO_CMD12_ERR_INT_EN
+#define SDH_AUTO_CMD12_ERR_INT_EN_POS         (8U)
+#define SDH_AUTO_CMD12_ERR_INT_EN_LEN         (1U)
+#define SDH_AUTO_CMD12_ERR_INT_EN_MSK         (((1U << SDH_AUTO_CMD12_ERR_INT_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_INT_EN_POS)
+#define SDH_AUTO_CMD12_ERR_INT_EN_UMSK        (~(((1U << SDH_AUTO_CMD12_ERR_INT_EN_LEN) - 1) << SDH_AUTO_CMD12_ERR_INT_EN_POS))
+#define SDH_ADMA_ERR_INT_EN                   SDH_ADMA_ERR_INT_EN
+#define SDH_ADMA_ERR_INT_EN_POS               (9U)
+#define SDH_ADMA_ERR_INT_EN_LEN               (1U)
+#define SDH_ADMA_ERR_INT_EN_MSK               (((1U << SDH_ADMA_ERR_INT_EN_LEN) - 1) << SDH_ADMA_ERR_INT_EN_POS)
+#define SDH_ADMA_ERR_INT_EN_UMSK              (~(((1U << SDH_ADMA_ERR_INT_EN_LEN) - 1) << SDH_ADMA_ERR_INT_EN_POS))
+#define SDH_TUNE_ERR_INT_EN                   SDH_TUNE_ERR_INT_EN
+#define SDH_TUNE_ERR_INT_EN_POS               (10U)
+#define SDH_TUNE_ERR_INT_EN_LEN               (1U)
+#define SDH_TUNE_ERR_INT_EN_MSK               (((1U << SDH_TUNE_ERR_INT_EN_LEN) - 1) << SDH_TUNE_ERR_INT_EN_POS)
+#define SDH_TUNE_ERR_INT_EN_UMSK              (~(((1U << SDH_TUNE_ERR_INT_EN_LEN) - 1) << SDH_TUNE_ERR_INT_EN_POS))
+#define SDH_SPI_ERR_INT_EN                    SDH_SPI_ERR_INT_EN
+#define SDH_SPI_ERR_INT_EN_POS                (12U)
+#define SDH_SPI_ERR_INT_EN_LEN                (1U)
+#define SDH_SPI_ERR_INT_EN_MSK                (((1U << SDH_SPI_ERR_INT_EN_LEN) - 1) << SDH_SPI_ERR_INT_EN_POS)
+#define SDH_SPI_ERR_INT_EN_UMSK               (~(((1U << SDH_SPI_ERR_INT_EN_LEN) - 1) << SDH_SPI_ERR_INT_EN_POS))
+#define SDH_AXI_RESP_ERR_INT_EN               SDH_AXI_RESP_ERR_INT_EN
+#define SDH_AXI_RESP_ERR_INT_EN_POS           (13U)
+#define SDH_AXI_RESP_ERR_INT_EN_LEN           (1U)
+#define SDH_AXI_RESP_ERR_INT_EN_MSK           (((1U << SDH_AXI_RESP_ERR_INT_EN_LEN) - 1) << SDH_AXI_RESP_ERR_INT_EN_POS)
+#define SDH_AXI_RESP_ERR_INT_EN_UMSK          (~(((1U << SDH_AXI_RESP_ERR_INT_EN_LEN) - 1) << SDH_AXI_RESP_ERR_INT_EN_POS))
+#define SDH_CPL_TIMEOUT_ERR_INT_EN            SDH_CPL_TIMEOUT_ERR_INT_EN
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_POS        (14U)
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_LEN        (1U)
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_MSK        (((1U << SDH_CPL_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_INT_EN_POS)
+#define SDH_CPL_TIMEOUT_ERR_INT_EN_UMSK       (~(((1U << SDH_CPL_TIMEOUT_ERR_INT_EN_LEN) - 1) << SDH_CPL_TIMEOUT_ERR_INT_EN_POS))
+#define SDH_CRC_STATUS_ERR_INT_EN             SDH_CRC_STATUS_ERR_INT_EN
+#define SDH_CRC_STATUS_ERR_INT_EN_POS         (15U)
+#define SDH_CRC_STATUS_ERR_INT_EN_LEN         (1U)
+#define SDH_CRC_STATUS_ERR_INT_EN_MSK         (((1U << SDH_CRC_STATUS_ERR_INT_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_INT_EN_POS)
+#define SDH_CRC_STATUS_ERR_INT_EN_UMSK        (~(((1U << SDH_CRC_STATUS_ERR_INT_EN_LEN) - 1) << SDH_CRC_STATUS_ERR_INT_EN_POS))
+
+/* 0x3C : Auto CMD12 Error Status Register */
+#define SDH_SD_AUTO_CMD12_ERROR_STATUS_OFFSET (0x3C)
+#define SDH_AUTO_CMD12_NOT_EXE                SDH_AUTO_CMD12_NOT_EXE
+#define SDH_AUTO_CMD12_NOT_EXE_POS            (0U)
+#define SDH_AUTO_CMD12_NOT_EXE_LEN            (1U)
+#define SDH_AUTO_CMD12_NOT_EXE_MSK            (((1U << SDH_AUTO_CMD12_NOT_EXE_LEN) - 1) << SDH_AUTO_CMD12_NOT_EXE_POS)
+#define SDH_AUTO_CMD12_NOT_EXE_UMSK           (~(((1U << SDH_AUTO_CMD12_NOT_EXE_LEN) - 1) << SDH_AUTO_CMD12_NOT_EXE_POS))
+#define SDH_AUTO_CMD_TIMEOUT_ERR              SDH_AUTO_CMD_TIMEOUT_ERR
+#define SDH_AUTO_CMD_TIMEOUT_ERR_POS          (1U)
+#define SDH_AUTO_CMD_TIMEOUT_ERR_LEN          (1U)
+#define SDH_AUTO_CMD_TIMEOUT_ERR_MSK          (((1U << SDH_AUTO_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_AUTO_CMD_TIMEOUT_ERR_POS)
+#define SDH_AUTO_CMD_TIMEOUT_ERR_UMSK         (~(((1U << SDH_AUTO_CMD_TIMEOUT_ERR_LEN) - 1) << SDH_AUTO_CMD_TIMEOUT_ERR_POS))
+#define SDH_AUTO_CMD_CRC_ERR                  SDH_AUTO_CMD_CRC_ERR
+#define SDH_AUTO_CMD_CRC_ERR_POS              (2U)
+#define SDH_AUTO_CMD_CRC_ERR_LEN              (1U)
+#define SDH_AUTO_CMD_CRC_ERR_MSK              (((1U << SDH_AUTO_CMD_CRC_ERR_LEN) - 1) << SDH_AUTO_CMD_CRC_ERR_POS)
+#define SDH_AUTO_CMD_CRC_ERR_UMSK             (~(((1U << SDH_AUTO_CMD_CRC_ERR_LEN) - 1) << SDH_AUTO_CMD_CRC_ERR_POS))
+#define SDH_AUTO_CMD_END_BIT_ERR              SDH_AUTO_CMD_END_BIT_ERR
+#define SDH_AUTO_CMD_END_BIT_ERR_POS          (3U)
+#define SDH_AUTO_CMD_END_BIT_ERR_LEN          (1U)
+#define SDH_AUTO_CMD_END_BIT_ERR_MSK          (((1U << SDH_AUTO_CMD_END_BIT_ERR_LEN) - 1) << SDH_AUTO_CMD_END_BIT_ERR_POS)
+#define SDH_AUTO_CMD_END_BIT_ERR_UMSK         (~(((1U << SDH_AUTO_CMD_END_BIT_ERR_LEN) - 1) << SDH_AUTO_CMD_END_BIT_ERR_POS))
+#define SDH_AUTO_CMD_INDEX_ERR                SDH_AUTO_CMD_INDEX_ERR
+#define SDH_AUTO_CMD_INDEX_ERR_POS            (4U)
+#define SDH_AUTO_CMD_INDEX_ERR_LEN            (1U)
+#define SDH_AUTO_CMD_INDEX_ERR_MSK            (((1U << SDH_AUTO_CMD_INDEX_ERR_LEN) - 1) << SDH_AUTO_CMD_INDEX_ERR_POS)
+#define SDH_AUTO_CMD_INDEX_ERR_UMSK           (~(((1U << SDH_AUTO_CMD_INDEX_ERR_LEN) - 1) << SDH_AUTO_CMD_INDEX_ERR_POS))
+#define SDH_CMD_NOT_ISSUED                    SDH_CMD_NOT_ISSUED
+#define SDH_CMD_NOT_ISSUED_POS                (7U)
+#define SDH_CMD_NOT_ISSUED_LEN                (1U)
+#define SDH_CMD_NOT_ISSUED_MSK                (((1U << SDH_CMD_NOT_ISSUED_LEN) - 1) << SDH_CMD_NOT_ISSUED_POS)
+#define SDH_CMD_NOT_ISSUED_UMSK               (~(((1U << SDH_CMD_NOT_ISSUED_LEN) - 1) << SDH_CMD_NOT_ISSUED_POS))
+
+/* 0x3e : Host Control 2 Register */
+#define SDH_HOST_CTRL_2_OFFSET    (0x3e)
+#define SDH_UHS_MODE_SEL          SDH_UHS_MODE_SEL
+#define SDH_UHS_MODE_SEL_POS      (0U)
+#define SDH_UHS_MODE_SEL_LEN      (3U)
+#define SDH_UHS_MODE_SEL_MSK      (((1U << SDH_UHS_MODE_SEL_LEN) - 1) << SDH_UHS_MODE_SEL_POS)
+#define SDH_UHS_MODE_SEL_UMSK     (~(((1U << SDH_UHS_MODE_SEL_LEN) - 1) << SDH_UHS_MODE_SEL_POS))
+#define SDH_SDH_V18_EN            SDH_SDH_V18_EN
+#define SDH_SDH_V18_EN_POS        (3U)
+#define SDH_SDH_V18_EN_LEN        (1U)
+#define SDH_SDH_V18_EN_MSK        (((1U << SDH_SDH_V18_EN_LEN) - 1) << SDH_SDH_V18_EN_POS)
+#define SDH_SDH_V18_EN_UMSK       (~(((1U << SDH_SDH_V18_EN_LEN) - 1) << SDH_SDH_V18_EN_POS))
+#define SDH_DRV_STRENGTH_SEL      SDH_DRV_STRENGTH_SEL
+#define SDH_DRV_STRENGTH_SEL_POS  (4U)
+#define SDH_DRV_STRENGTH_SEL_LEN  (2U)
+#define SDH_DRV_STRENGTH_SEL_MSK  (((1U << SDH_DRV_STRENGTH_SEL_LEN) - 1) << SDH_DRV_STRENGTH_SEL_POS)
+#define SDH_DRV_STRENGTH_SEL_UMSK (~(((1U << SDH_DRV_STRENGTH_SEL_LEN) - 1) << SDH_DRV_STRENGTH_SEL_POS))
+#define SDH_EXE_TUNING            SDH_EXE_TUNING
+#define SDH_EXE_TUNING_POS        (6U)
+#define SDH_EXE_TUNING_LEN        (1U)
+#define SDH_EXE_TUNING_MSK        (((1U << SDH_EXE_TUNING_LEN) - 1) << SDH_EXE_TUNING_POS)
+#define SDH_EXE_TUNING_UMSK       (~(((1U << SDH_EXE_TUNING_LEN) - 1) << SDH_EXE_TUNING_POS))
+#define SDH_SAMPLING_CLK_SEL      SDH_SAMPLING_CLK_SEL
+#define SDH_SAMPLING_CLK_SEL_POS  (7U)
+#define SDH_SAMPLING_CLK_SEL_LEN  (1U)
+#define SDH_SAMPLING_CLK_SEL_MSK  (((1U << SDH_SAMPLING_CLK_SEL_LEN) - 1) << SDH_SAMPLING_CLK_SEL_POS)
+#define SDH_SAMPLING_CLK_SEL_UMSK (~(((1U << SDH_SAMPLING_CLK_SEL_LEN) - 1) << SDH_SAMPLING_CLK_SEL_POS))
+#define SDH_ASYNC_INT_EN          SDH_ASYNC_INT_EN
+#define SDH_ASYNC_INT_EN_POS      (14U)
+#define SDH_ASYNC_INT_EN_LEN      (1U)
+#define SDH_ASYNC_INT_EN_MSK      (((1U << SDH_ASYNC_INT_EN_LEN) - 1) << SDH_ASYNC_INT_EN_POS)
+#define SDH_ASYNC_INT_EN_UMSK     (~(((1U << SDH_ASYNC_INT_EN_LEN) - 1) << SDH_ASYNC_INT_EN_POS))
+#define SDH_PRE_VAL_EN            SDH_PRE_VAL_EN
+#define SDH_PRE_VAL_EN_POS        (15U)
+#define SDH_PRE_VAL_EN_LEN        (1U)
+#define SDH_PRE_VAL_EN_MSK        (((1U << SDH_PRE_VAL_EN_LEN) - 1) << SDH_PRE_VAL_EN_POS)
+#define SDH_PRE_VAL_EN_UMSK       (~(((1U << SDH_PRE_VAL_EN_LEN) - 1) << SDH_PRE_VAL_EN_POS))
+
+/* 0x40 : Capabilities Register 1 */
+#define SDH_SD_CAPABILITIES_1_OFFSET (0x40)
+#define SDH_TIMEOUT_FREQ             SDH_TIMEOUT_FREQ
+#define SDH_TIMEOUT_FREQ_POS         (0U)
+#define SDH_TIMEOUT_FREQ_LEN         (6U)
+#define SDH_TIMEOUT_FREQ_MSK         (((1U << SDH_TIMEOUT_FREQ_LEN) - 1) << SDH_TIMEOUT_FREQ_POS)
+#define SDH_TIMEOUT_FREQ_UMSK        (~(((1U << SDH_TIMEOUT_FREQ_LEN) - 1) << SDH_TIMEOUT_FREQ_POS))
+#define SDH_TIMEOUT_UNIT             SDH_TIMEOUT_UNIT
+#define SDH_TIMEOUT_UNIT_POS         (7U)
+#define SDH_TIMEOUT_UNIT_LEN         (1U)
+#define SDH_TIMEOUT_UNIT_MSK         (((1U << SDH_TIMEOUT_UNIT_LEN) - 1) << SDH_TIMEOUT_UNIT_POS)
+#define SDH_TIMEOUT_UNIT_UMSK        (~(((1U << SDH_TIMEOUT_UNIT_LEN) - 1) << SDH_TIMEOUT_UNIT_POS))
+#define SDH_BASE_FREQ                SDH_BASE_FREQ
+#define SDH_BASE_FREQ_POS            (8U)
+#define SDH_BASE_FREQ_LEN            (8U)
+#define SDH_BASE_FREQ_MSK            (((1U << SDH_BASE_FREQ_LEN) - 1) << SDH_BASE_FREQ_POS)
+#define SDH_BASE_FREQ_UMSK           (~(((1U << SDH_BASE_FREQ_LEN) - 1) << SDH_BASE_FREQ_POS))
+
+/* 0x42 : Capabilities Register 2 */
+#define SDH_SD_CAPABILITIES_2_OFFSET   (0x42)
+#define SDH_MAX_BLK_LEN                SDH_MAX_BLK_LEN
+#define SDH_MAX_BLK_LEN_POS            (0U)
+#define SDH_MAX_BLK_LEN_LEN            (2U)
+#define SDH_MAX_BLK_LEN_MSK            (((1U << SDH_MAX_BLK_LEN_LEN) - 1) << SDH_MAX_BLK_LEN_POS)
+#define SDH_MAX_BLK_LEN_UMSK           (~(((1U << SDH_MAX_BLK_LEN_LEN) - 1) << SDH_MAX_BLK_LEN_POS))
+#define SDH_EX_DATA_WIDTH_SUPPORT      SDH_EX_DATA_WIDTH_SUPPORT
+#define SDH_EX_DATA_WIDTH_SUPPORT_POS  (2U)
+#define SDH_EX_DATA_WIDTH_SUPPORT_LEN  (1U)
+#define SDH_EX_DATA_WIDTH_SUPPORT_MSK  (((1U << SDH_EX_DATA_WIDTH_SUPPORT_LEN) - 1) << SDH_EX_DATA_WIDTH_SUPPORT_POS)
+#define SDH_EX_DATA_WIDTH_SUPPORT_UMSK (~(((1U << SDH_EX_DATA_WIDTH_SUPPORT_LEN) - 1) << SDH_EX_DATA_WIDTH_SUPPORT_POS))
+#define SDH_ADMA2_SUPPORT              SDH_ADMA2_SUPPORT
+#define SDH_ADMA2_SUPPORT_POS          (3U)
+#define SDH_ADMA2_SUPPORT_LEN          (1U)
+#define SDH_ADMA2_SUPPORT_MSK          (((1U << SDH_ADMA2_SUPPORT_LEN) - 1) << SDH_ADMA2_SUPPORT_POS)
+#define SDH_ADMA2_SUPPORT_UMSK         (~(((1U << SDH_ADMA2_SUPPORT_LEN) - 1) << SDH_ADMA2_SUPPORT_POS))
+#define SDH_ADMA1_SUPPORT              SDH_ADMA1_SUPPORT
+#define SDH_ADMA1_SUPPORT_POS          (4U)
+#define SDH_ADMA1_SUPPORT_LEN          (1U)
+#define SDH_ADMA1_SUPPORT_MSK          (((1U << SDH_ADMA1_SUPPORT_LEN) - 1) << SDH_ADMA1_SUPPORT_POS)
+#define SDH_ADMA1_SUPPORT_UMSK         (~(((1U << SDH_ADMA1_SUPPORT_LEN) - 1) << SDH_ADMA1_SUPPORT_POS))
+#define SDH_HI_SPEED_SUPPORT           SDH_HI_SPEED_SUPPORT
+#define SDH_HI_SPEED_SUPPORT_POS       (5U)
+#define SDH_HI_SPEED_SUPPORT_LEN       (1U)
+#define SDH_HI_SPEED_SUPPORT_MSK       (((1U << SDH_HI_SPEED_SUPPORT_LEN) - 1) << SDH_HI_SPEED_SUPPORT_POS)
+#define SDH_HI_SPEED_SUPPORT_UMSK      (~(((1U << SDH_HI_SPEED_SUPPORT_LEN) - 1) << SDH_HI_SPEED_SUPPORT_POS))
+#define SDH_SDMA_SUPPORT               SDH_SDMA_SUPPORT
+#define SDH_SDMA_SUPPORT_POS           (6U)
+#define SDH_SDMA_SUPPORT_LEN           (1U)
+#define SDH_SDMA_SUPPORT_MSK           (((1U << SDH_SDMA_SUPPORT_LEN) - 1) << SDH_SDMA_SUPPORT_POS)
+#define SDH_SDMA_SUPPORT_UMSK          (~(((1U << SDH_SDMA_SUPPORT_LEN) - 1) << SDH_SDMA_SUPPORT_POS))
+#define SDH_SUS_RES_SUPPORT            SDH_SUS_RES_SUPPORT
+#define SDH_SUS_RES_SUPPORT_POS        (7U)
+#define SDH_SUS_RES_SUPPORT_LEN        (1U)
+#define SDH_SUS_RES_SUPPORT_MSK        (((1U << SDH_SUS_RES_SUPPORT_LEN) - 1) << SDH_SUS_RES_SUPPORT_POS)
+#define SDH_SUS_RES_SUPPORT_UMSK       (~(((1U << SDH_SUS_RES_SUPPORT_LEN) - 1) << SDH_SUS_RES_SUPPORT_POS))
+#define SDH_VLG_33_SUPPORT             SDH_VLG_33_SUPPORT
+#define SDH_VLG_33_SUPPORT_POS         (8U)
+#define SDH_VLG_33_SUPPORT_LEN         (1U)
+#define SDH_VLG_33_SUPPORT_MSK         (((1U << SDH_VLG_33_SUPPORT_LEN) - 1) << SDH_VLG_33_SUPPORT_POS)
+#define SDH_VLG_33_SUPPORT_UMSK        (~(((1U << SDH_VLG_33_SUPPORT_LEN) - 1) << SDH_VLG_33_SUPPORT_POS))
+#define SDH_VLG_30_SUPPORT             SDH_VLG_30_SUPPORT
+#define SDH_VLG_30_SUPPORT_POS         (9U)
+#define SDH_VLG_30_SUPPORT_LEN         (1U)
+#define SDH_VLG_30_SUPPORT_MSK         (((1U << SDH_VLG_30_SUPPORT_LEN) - 1) << SDH_VLG_30_SUPPORT_POS)
+#define SDH_VLG_30_SUPPORT_UMSK        (~(((1U << SDH_VLG_30_SUPPORT_LEN) - 1) << SDH_VLG_30_SUPPORT_POS))
+#define SDH_VLG_18_SUPPORT             SDH_VLG_18_SUPPORT
+#define SDH_VLG_18_SUPPORT_POS         (10U)
+#define SDH_VLG_18_SUPPORT_LEN         (1U)
+#define SDH_VLG_18_SUPPORT_MSK         (((1U << SDH_VLG_18_SUPPORT_LEN) - 1) << SDH_VLG_18_SUPPORT_POS)
+#define SDH_VLG_18_SUPPORT_UMSK        (~(((1U << SDH_VLG_18_SUPPORT_LEN) - 1) << SDH_VLG_18_SUPPORT_POS))
+#define SDH_SYS_BUS_64_SUPPORT         SDH_SYS_BUS_64_SUPPORT
+#define SDH_SYS_BUS_64_SUPPORT_POS     (12U)
+#define SDH_SYS_BUS_64_SUPPORT_LEN     (1U)
+#define SDH_SYS_BUS_64_SUPPORT_MSK     (((1U << SDH_SYS_BUS_64_SUPPORT_LEN) - 1) << SDH_SYS_BUS_64_SUPPORT_POS)
+#define SDH_SYS_BUS_64_SUPPORT_UMSK    (~(((1U << SDH_SYS_BUS_64_SUPPORT_LEN) - 1) << SDH_SYS_BUS_64_SUPPORT_POS))
+#define SDH_ASYNC_INT_SUPPORT          SDH_ASYNC_INT_SUPPORT
+#define SDH_ASYNC_INT_SUPPORT_POS      (13U)
+#define SDH_ASYNC_INT_SUPPORT_LEN      (1U)
+#define SDH_ASYNC_INT_SUPPORT_MSK      (((1U << SDH_ASYNC_INT_SUPPORT_LEN) - 1) << SDH_ASYNC_INT_SUPPORT_POS)
+#define SDH_ASYNC_INT_SUPPORT_UMSK     (~(((1U << SDH_ASYNC_INT_SUPPORT_LEN) - 1) << SDH_ASYNC_INT_SUPPORT_POS))
+#define SDH_CFG_SLOT_TYPE              SDH_CFG_SLOT_TYPE
+#define SDH_CFG_SLOT_TYPE_POS          (14U)
+#define SDH_CFG_SLOT_TYPE_LEN          (2U)
+#define SDH_CFG_SLOT_TYPE_MSK          (((1U << SDH_CFG_SLOT_TYPE_LEN) - 1) << SDH_CFG_SLOT_TYPE_POS)
+#define SDH_CFG_SLOT_TYPE_UMSK         (~(((1U << SDH_CFG_SLOT_TYPE_LEN) - 1) << SDH_CFG_SLOT_TYPE_POS))
+
+/* 0x44 : Capabilities Register 3 */
+#define SDH_SD_CAPABILITIES_3_OFFSET (0x44)
+#define SDH_SDR50_SUPPORT            SDH_SDR50_SUPPORT
+#define SDH_SDR50_SUPPORT_POS        (0U)
+#define SDH_SDR50_SUPPORT_LEN        (1U)
+#define SDH_SDR50_SUPPORT_MSK        (((1U << SDH_SDR50_SUPPORT_LEN) - 1) << SDH_SDR50_SUPPORT_POS)
+#define SDH_SDR50_SUPPORT_UMSK       (~(((1U << SDH_SDR50_SUPPORT_LEN) - 1) << SDH_SDR50_SUPPORT_POS))
+#define SDH_SDR104_SUPPORT           SDH_SDR104_SUPPORT
+#define SDH_SDR104_SUPPORT_POS       (1U)
+#define SDH_SDR104_SUPPORT_LEN       (1U)
+#define SDH_SDR104_SUPPORT_MSK       (((1U << SDH_SDR104_SUPPORT_LEN) - 1) << SDH_SDR104_SUPPORT_POS)
+#define SDH_SDR104_SUPPORT_UMSK      (~(((1U << SDH_SDR104_SUPPORT_LEN) - 1) << SDH_SDR104_SUPPORT_POS))
+#define SDH_DDR50_SUPPORT            SDH_DDR50_SUPPORT
+#define SDH_DDR50_SUPPORT_POS        (2U)
+#define SDH_DDR50_SUPPORT_LEN        (1U)
+#define SDH_DDR50_SUPPORT_MSK        (((1U << SDH_DDR50_SUPPORT_LEN) - 1) << SDH_DDR50_SUPPORT_POS)
+#define SDH_DDR50_SUPPORT_UMSK       (~(((1U << SDH_DDR50_SUPPORT_LEN) - 1) << SDH_DDR50_SUPPORT_POS))
+#define SDH_DRV_TYPE_A               SDH_DRV_TYPE_A
+#define SDH_DRV_TYPE_A_POS           (4U)
+#define SDH_DRV_TYPE_A_LEN           (1U)
+#define SDH_DRV_TYPE_A_MSK           (((1U << SDH_DRV_TYPE_A_LEN) - 1) << SDH_DRV_TYPE_A_POS)
+#define SDH_DRV_TYPE_A_UMSK          (~(((1U << SDH_DRV_TYPE_A_LEN) - 1) << SDH_DRV_TYPE_A_POS))
+#define SDH_DRV_TYPE_C               SDH_DRV_TYPE_C
+#define SDH_DRV_TYPE_C_POS           (5U)
+#define SDH_DRV_TYPE_C_LEN           (1U)
+#define SDH_DRV_TYPE_C_MSK           (((1U << SDH_DRV_TYPE_C_LEN) - 1) << SDH_DRV_TYPE_C_POS)
+#define SDH_DRV_TYPE_C_UMSK          (~(((1U << SDH_DRV_TYPE_C_LEN) - 1) << SDH_DRV_TYPE_C_POS))
+#define SDH_DRV_TYPE_D               SDH_DRV_TYPE_D
+#define SDH_DRV_TYPE_D_POS           (6U)
+#define SDH_DRV_TYPE_D_LEN           (1U)
+#define SDH_DRV_TYPE_D_MSK           (((1U << SDH_DRV_TYPE_D_LEN) - 1) << SDH_DRV_TYPE_D_POS)
+#define SDH_DRV_TYPE_D_UMSK          (~(((1U << SDH_DRV_TYPE_D_LEN) - 1) << SDH_DRV_TYPE_D_POS))
+#define SDH_TMR_RETUNE               SDH_TMR_RETUNE
+#define SDH_TMR_RETUNE_POS           (8U)
+#define SDH_TMR_RETUNE_LEN           (4U)
+#define SDH_TMR_RETUNE_MSK           (((1U << SDH_TMR_RETUNE_LEN) - 1) << SDH_TMR_RETUNE_POS)
+#define SDH_TMR_RETUNE_UMSK          (~(((1U << SDH_TMR_RETUNE_LEN) - 1) << SDH_TMR_RETUNE_POS))
+#define SDH_SDR50_TUNE               SDH_SDR50_TUNE
+#define SDH_SDR50_TUNE_POS           (13U)
+#define SDH_SDR50_TUNE_LEN           (1U)
+#define SDH_SDR50_TUNE_MSK           (((1U << SDH_SDR50_TUNE_LEN) - 1) << SDH_SDR50_TUNE_POS)
+#define SDH_SDR50_TUNE_UMSK          (~(((1U << SDH_SDR50_TUNE_LEN) - 1) << SDH_SDR50_TUNE_POS))
+#define SDH_RETUNE_MODES             SDH_RETUNE_MODES
+#define SDH_RETUNE_MODES_POS         (14U)
+#define SDH_RETUNE_MODES_LEN         (2U)
+#define SDH_RETUNE_MODES_MSK         (((1U << SDH_RETUNE_MODES_LEN) - 1) << SDH_RETUNE_MODES_POS)
+#define SDH_RETUNE_MODES_UMSK        (~(((1U << SDH_RETUNE_MODES_LEN) - 1) << SDH_RETUNE_MODES_POS))
+
+/* 0x46 : Capabilities Register 4 */
+#define SDH_SD_CAPABILITIES_4_OFFSET (0x46)
+#define SDH_CLK_MULTIPLIER           SDH_CLK_MULTIPLIER
+#define SDH_CLK_MULTIPLIER_POS       (0U)
+#define SDH_CLK_MULTIPLIER_LEN       (8U)
+#define SDH_CLK_MULTIPLIER_MSK       (((1U << SDH_CLK_MULTIPLIER_LEN) - 1) << SDH_CLK_MULTIPLIER_POS)
+#define SDH_CLK_MULTIPLIER_UMSK      (~(((1U << SDH_CLK_MULTIPLIER_LEN) - 1) << SDH_CLK_MULTIPLIER_POS))
+
+/* 0x48 : Maximum Current Register 1 */
+#define SDH_SD_MAX_CURRENT_1_OFFSET (0x48)
+#define SDH_MAX_CUR_33              SDH_MAX_CUR_33
+#define SDH_MAX_CUR_33_POS          (0U)
+#define SDH_MAX_CUR_33_LEN          (8U)
+#define SDH_MAX_CUR_33_MSK          (((1U << SDH_MAX_CUR_33_LEN) - 1) << SDH_MAX_CUR_33_POS)
+#define SDH_MAX_CUR_33_UMSK         (~(((1U << SDH_MAX_CUR_33_LEN) - 1) << SDH_MAX_CUR_33_POS))
+#define SDH_MAX_CUR_30              SDH_MAX_CUR_30
+#define SDH_MAX_CUR_30_POS          (8U)
+#define SDH_MAX_CUR_30_LEN          (8U)
+#define SDH_MAX_CUR_30_MSK          (((1U << SDH_MAX_CUR_30_LEN) - 1) << SDH_MAX_CUR_30_POS)
+#define SDH_MAX_CUR_30_UMSK         (~(((1U << SDH_MAX_CUR_30_LEN) - 1) << SDH_MAX_CUR_30_POS))
+
+/* 0x4A : Maximum Current Register 2 */
+#define SDH_SD_MAX_CURRENT_2_OFFSET (0x4A)
+#define SDH_MAX_CUR_18              SDH_MAX_CUR_18
+#define SDH_MAX_CUR_18_POS          (0U)
+#define SDH_MAX_CUR_18_LEN          (8U)
+#define SDH_MAX_CUR_18_MSK          (((1U << SDH_MAX_CUR_18_LEN) - 1) << SDH_MAX_CUR_18_POS)
+#define SDH_MAX_CUR_18_UMSK         (~(((1U << SDH_MAX_CUR_18_LEN) - 1) << SDH_MAX_CUR_18_POS))
+
+/* 0x4C : Maximum Current Register 3 */
+#define SDH_SD_MAX_CURRENT_3_OFFSET (0x4C)
+
+/* 0x4E : Maximum Current Register 4 */
+#define SDH_SD_MAX_CURRENT_4_OFFSET (0x4E)
+
+/* 0x50 : Force Event Auto cmd12 Error Register */
+#define SDH_SD_FORCE_EVENT_AUTO_CMD12_ERROR_OFFSET (0x50)
+#define SDH_F_ACMD12_NEXE_ERR                      SDH_F_ACMD12_NEXE_ERR
+#define SDH_F_ACMD12_NEXE_ERR_POS                  (0U)
+#define SDH_F_ACMD12_NEXE_ERR_LEN                  (1U)
+#define SDH_F_ACMD12_NEXE_ERR_MSK                  (((1U << SDH_F_ACMD12_NEXE_ERR_LEN) - 1) << SDH_F_ACMD12_NEXE_ERR_POS)
+#define SDH_F_ACMD12_NEXE_ERR_UMSK                 (~(((1U << SDH_F_ACMD12_NEXE_ERR_LEN) - 1) << SDH_F_ACMD12_NEXE_ERR_POS))
+#define SDH_F_ACMD_TO_ERR                          SDH_F_ACMD_TO_ERR
+#define SDH_F_ACMD_TO_ERR_POS                      (1U)
+#define SDH_F_ACMD_TO_ERR_LEN                      (1U)
+#define SDH_F_ACMD_TO_ERR_MSK                      (((1U << SDH_F_ACMD_TO_ERR_LEN) - 1) << SDH_F_ACMD_TO_ERR_POS)
+#define SDH_F_ACMD_TO_ERR_UMSK                     (~(((1U << SDH_F_ACMD_TO_ERR_LEN) - 1) << SDH_F_ACMD_TO_ERR_POS))
+#define SDH_F_ACMD_CRC_ERR                         SDH_F_ACMD_CRC_ERR
+#define SDH_F_ACMD_CRC_ERR_POS                     (2U)
+#define SDH_F_ACMD_CRC_ERR_LEN                     (1U)
+#define SDH_F_ACMD_CRC_ERR_MSK                     (((1U << SDH_F_ACMD_CRC_ERR_LEN) - 1) << SDH_F_ACMD_CRC_ERR_POS)
+#define SDH_F_ACMD_CRC_ERR_UMSK                    (~(((1U << SDH_F_ACMD_CRC_ERR_LEN) - 1) << SDH_F_ACMD_CRC_ERR_POS))
+#define SDH_F__ACMD_EBIT_ERR                       SDH_F__ACMD_EBIT_ERR
+#define SDH_F__ACMD_EBIT_ERR_POS                   (3U)
+#define SDH_F__ACMD_EBIT_ERR_LEN                   (1U)
+#define SDH_F__ACMD_EBIT_ERR_MSK                   (((1U << SDH_F__ACMD_EBIT_ERR_LEN) - 1) << SDH_F__ACMD_EBIT_ERR_POS)
+#define SDH_F__ACMD_EBIT_ERR_UMSK                  (~(((1U << SDH_F__ACMD_EBIT_ERR_LEN) - 1) << SDH_F__ACMD_EBIT_ERR_POS))
+#define SDH_F_ACMD_INDEX_ERR                       SDH_F_ACMD_INDEX_ERR
+#define SDH_F_ACMD_INDEX_ERR_POS                   (4U)
+#define SDH_F_ACMD_INDEX_ERR_LEN                   (1U)
+#define SDH_F_ACMD_INDEX_ERR_MSK                   (((1U << SDH_F_ACMD_INDEX_ERR_LEN) - 1) << SDH_F_ACMD_INDEX_ERR_POS)
+#define SDH_F_ACMD_INDEX_ERR_UMSK                  (~(((1U << SDH_F_ACMD_INDEX_ERR_LEN) - 1) << SDH_F_ACMD_INDEX_ERR_POS))
+#define SDH_F_ACMD12_ISSUE_ERR                     SDH_F_ACMD12_ISSUE_ERR
+#define SDH_F_ACMD12_ISSUE_ERR_POS                 (7U)
+#define SDH_F_ACMD12_ISSUE_ERR_LEN                 (1U)
+#define SDH_F_ACMD12_ISSUE_ERR_MSK                 (((1U << SDH_F_ACMD12_ISSUE_ERR_LEN) - 1) << SDH_F_ACMD12_ISSUE_ERR_POS)
+#define SDH_F_ACMD12_ISSUE_ERR_UMSK                (~(((1U << SDH_F_ACMD12_ISSUE_ERR_LEN) - 1) << SDH_F_ACMD12_ISSUE_ERR_POS))
+
+/* 0x52 : Force Event for Error Status Register */
+#define SDH_SD_FORCE_EVENT_FOR_ERROR_STATUS_OFFSET (0x52)
+#define SDH_F_CMD_TO_ERR                           SDH_F_CMD_TO_ERR
+#define SDH_F_CMD_TO_ERR_POS                       (0U)
+#define SDH_F_CMD_TO_ERR_LEN                       (1U)
+#define SDH_F_CMD_TO_ERR_MSK                       (((1U << SDH_F_CMD_TO_ERR_LEN) - 1) << SDH_F_CMD_TO_ERR_POS)
+#define SDH_F_CMD_TO_ERR_UMSK                      (~(((1U << SDH_F_CMD_TO_ERR_LEN) - 1) << SDH_F_CMD_TO_ERR_POS))
+#define SDH_F_CMD_CRC_ERR                          SDH_F_CMD_CRC_ERR
+#define SDH_F_CMD_CRC_ERR_POS                      (1U)
+#define SDH_F_CMD_CRC_ERR_LEN                      (1U)
+#define SDH_F_CMD_CRC_ERR_MSK                      (((1U << SDH_F_CMD_CRC_ERR_LEN) - 1) << SDH_F_CMD_CRC_ERR_POS)
+#define SDH_F_CMD_CRC_ERR_UMSK                     (~(((1U << SDH_F_CMD_CRC_ERR_LEN) - 1) << SDH_F_CMD_CRC_ERR_POS))
+#define SDH_F_CMD_END_BIT_ERR                      SDH_F_CMD_END_BIT_ERR
+#define SDH_F_CMD_END_BIT_ERR_POS                  (2U)
+#define SDH_F_CMD_END_BIT_ERR_LEN                  (1U)
+#define SDH_F_CMD_END_BIT_ERR_MSK                  (((1U << SDH_F_CMD_END_BIT_ERR_LEN) - 1) << SDH_F_CMD_END_BIT_ERR_POS)
+#define SDH_F_CMD_END_BIT_ERR_UMSK                 (~(((1U << SDH_F_CMD_END_BIT_ERR_LEN) - 1) << SDH_F_CMD_END_BIT_ERR_POS))
+#define SDH_F_CMD_INDEX_ERR                        SDH_F_CMD_INDEX_ERR
+#define SDH_F_CMD_INDEX_ERR_POS                    (3U)
+#define SDH_F_CMD_INDEX_ERR_LEN                    (1U)
+#define SDH_F_CMD_INDEX_ERR_MSK                    (((1U << SDH_F_CMD_INDEX_ERR_LEN) - 1) << SDH_F_CMD_INDEX_ERR_POS)
+#define SDH_F_CMD_INDEX_ERR_UMSK                   (~(((1U << SDH_F_CMD_INDEX_ERR_LEN) - 1) << SDH_F_CMD_INDEX_ERR_POS))
+#define SDH_F_DAT_TO_ERR                           SDH_F_DAT_TO_ERR
+#define SDH_F_DAT_TO_ERR_POS                       (4U)
+#define SDH_F_DAT_TO_ERR_LEN                       (1U)
+#define SDH_F_DAT_TO_ERR_MSK                       (((1U << SDH_F_DAT_TO_ERR_LEN) - 1) << SDH_F_DAT_TO_ERR_POS)
+#define SDH_F_DAT_TO_ERR_UMSK                      (~(((1U << SDH_F_DAT_TO_ERR_LEN) - 1) << SDH_F_DAT_TO_ERR_POS))
+#define SDH_F_DAT_CRC_ERR                          SDH_F_DAT_CRC_ERR
+#define SDH_F_DAT_CRC_ERR_POS                      (5U)
+#define SDH_F_DAT_CRC_ERR_LEN                      (1U)
+#define SDH_F_DAT_CRC_ERR_MSK                      (((1U << SDH_F_DAT_CRC_ERR_LEN) - 1) << SDH_F_DAT_CRC_ERR_POS)
+#define SDH_F_DAT_CRC_ERR_UMSK                     (~(((1U << SDH_F_DAT_CRC_ERR_LEN) - 1) << SDH_F_DAT_CRC_ERR_POS))
+#define SDH_F_DAT_END_BIT_ERR                      SDH_F_DAT_END_BIT_ERR
+#define SDH_F_DAT_END_BIT_ERR_POS                  (6U)
+#define SDH_F_DAT_END_BIT_ERR_LEN                  (1U)
+#define SDH_F_DAT_END_BIT_ERR_MSK                  (((1U << SDH_F_DAT_END_BIT_ERR_LEN) - 1) << SDH_F_DAT_END_BIT_ERR_POS)
+#define SDH_F_DAT_END_BIT_ERR_UMSK                 (~(((1U << SDH_F_DAT_END_BIT_ERR_LEN) - 1) << SDH_F_DAT_END_BIT_ERR_POS))
+#define SDH_F_CURRENT_ERR                          SDH_F_CURRENT_ERR
+#define SDH_F_CURRENT_ERR_POS                      (7U)
+#define SDH_F_CURRENT_ERR_LEN                      (1U)
+#define SDH_F_CURRENT_ERR_MSK                      (((1U << SDH_F_CURRENT_ERR_LEN) - 1) << SDH_F_CURRENT_ERR_POS)
+#define SDH_F_CURRENT_ERR_UMSK                     (~(((1U << SDH_F_CURRENT_ERR_LEN) - 1) << SDH_F_CURRENT_ERR_POS))
+#define SDH_F_ACMD12_ERR                           SDH_F_ACMD12_ERR
+#define SDH_F_ACMD12_ERR_POS                       (8U)
+#define SDH_F_ACMD12_ERR_LEN                       (1U)
+#define SDH_F_ACMD12_ERR_MSK                       (((1U << SDH_F_ACMD12_ERR_LEN) - 1) << SDH_F_ACMD12_ERR_POS)
+#define SDH_F_ACMD12_ERR_UMSK                      (~(((1U << SDH_F_ACMD12_ERR_LEN) - 1) << SDH_F_ACMD12_ERR_POS))
+#define SDH_F_ADMA_ERR                             SDH_F_ADMA_ERR
+#define SDH_F_ADMA_ERR_POS                         (9U)
+#define SDH_F_ADMA_ERR_LEN                         (1U)
+#define SDH_F_ADMA_ERR_MSK                         (((1U << SDH_F_ADMA_ERR_LEN) - 1) << SDH_F_ADMA_ERR_POS)
+#define SDH_F_ADMA_ERR_UMSK                        (~(((1U << SDH_F_ADMA_ERR_LEN) - 1) << SDH_F_ADMA_ERR_POS))
+#define SDH_F_SPI_ERR                              SDH_F_SPI_ERR
+#define SDH_F_SPI_ERR_POS                          (12U)
+#define SDH_F_SPI_ERR_LEN                          (1U)
+#define SDH_F_SPI_ERR_MSK                          (((1U << SDH_F_SPI_ERR_LEN) - 1) << SDH_F_SPI_ERR_POS)
+#define SDH_F_SPI_ERR_UMSK                         (~(((1U << SDH_F_SPI_ERR_LEN) - 1) << SDH_F_SPI_ERR_POS))
+#define SDH_F_AXI_RESP_ERR                         SDH_F_AXI_RESP_ERR
+#define SDH_F_AXI_RESP_ERR_POS                     (13U)
+#define SDH_F_AXI_RESP_ERR_LEN                     (1U)
+#define SDH_F_AXI_RESP_ERR_MSK                     (((1U << SDH_F_AXI_RESP_ERR_LEN) - 1) << SDH_F_AXI_RESP_ERR_POS)
+#define SDH_F_AXI_RESP_ERR_UMSK                    (~(((1U << SDH_F_AXI_RESP_ERR_LEN) - 1) << SDH_F_AXI_RESP_ERR_POS))
+#define SDH_F_CPL_TIMEOUT_ERR                      SDH_F_CPL_TIMEOUT_ERR
+#define SDH_F_CPL_TIMEOUT_ERR_POS                  (14U)
+#define SDH_F_CPL_TIMEOUT_ERR_LEN                  (1U)
+#define SDH_F_CPL_TIMEOUT_ERR_MSK                  (((1U << SDH_F_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_F_CPL_TIMEOUT_ERR_POS)
+#define SDH_F_CPL_TIMEOUT_ERR_UMSK                 (~(((1U << SDH_F_CPL_TIMEOUT_ERR_LEN) - 1) << SDH_F_CPL_TIMEOUT_ERR_POS))
+#define SDH_F_CRC_STATUS_ERR                       SDH_F_CRC_STATUS_ERR
+#define SDH_F_CRC_STATUS_ERR_POS                   (15U)
+#define SDH_F_CRC_STATUS_ERR_LEN                   (1U)
+#define SDH_F_CRC_STATUS_ERR_MSK                   (((1U << SDH_F_CRC_STATUS_ERR_LEN) - 1) << SDH_F_CRC_STATUS_ERR_POS)
+#define SDH_F_CRC_STATUS_ERR_UMSK                  (~(((1U << SDH_F_CRC_STATUS_ERR_LEN) - 1) << SDH_F_CRC_STATUS_ERR_POS))
+
+/* 0x54 : ADMA Error Status Register */
+#define SDH_SD_ADMA_ERROR_STATUS_OFFSET (0x54)
+#define SDH_ADMA_STATE                  SDH_ADMA_STATE
+#define SDH_ADMA_STATE_POS              (0U)
+#define SDH_ADMA_STATE_LEN              (2U)
+#define SDH_ADMA_STATE_MSK              (((1U << SDH_ADMA_STATE_LEN) - 1) << SDH_ADMA_STATE_POS)
+#define SDH_ADMA_STATE_UMSK             (~(((1U << SDH_ADMA_STATE_LEN) - 1) << SDH_ADMA_STATE_POS))
+#define SDH_ADMA_LEN_ERR                SDH_ADMA_LEN_ERR
+#define SDH_ADMA_LEN_ERR_POS            (2U)
+#define SDH_ADMA_LEN_ERR_LEN            (1U)
+#define SDH_ADMA_LEN_ERR_MSK            (((1U << SDH_ADMA_LEN_ERR_LEN) - 1) << SDH_ADMA_LEN_ERR_POS)
+#define SDH_ADMA_LEN_ERR_UMSK           (~(((1U << SDH_ADMA_LEN_ERR_LEN) - 1) << SDH_ADMA_LEN_ERR_POS))
+
+/* 0x58 : ADMA System Address Register 1 */
+#define SDH_SD_ADMA_SYS_ADDR_1_OFFSET (0x58)
+#define SDH_ADMA_SYS_ADDR             SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS         (0U)
+#define SDH_ADMA_SYS_ADDR_LEN         (16U)
+#define SDH_ADMA_SYS_ADDR_MSK         (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK        (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x5A : ADMA System Address Register 2 */
+#define SDH_SD_ADMA_SYS_ADDR_2_OFFSET (0x5A)
+#define SDH_ADMA_SYS_ADDR             SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS         (0U)
+#define SDH_ADMA_SYS_ADDR_LEN         (16U)
+#define SDH_ADMA_SYS_ADDR_MSK         (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK        (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x5C : ADMA System Address Register 3 */
+#define SDH_SD_ADMA_SYS_ADDR_3_OFFSET (0x5C)
+#define SDH_ADMA_SYS_ADDR             SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS         (0U)
+#define SDH_ADMA_SYS_ADDR_LEN         (16U)
+#define SDH_ADMA_SYS_ADDR_MSK         (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK        (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x5E : ADMA System Address Register 4 */
+#define SDH_SD_ADMA_SYS_ADDR_4_OFFSET (0x5E)
+#define SDH_ADMA_SYS_ADDR             SDH_ADMA_SYS_ADDR
+#define SDH_ADMA_SYS_ADDR_POS         (0U)
+#define SDH_ADMA_SYS_ADDR_LEN         (16U)
+#define SDH_ADMA_SYS_ADDR_MSK         (((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS)
+#define SDH_ADMA_SYS_ADDR_UMSK        (~(((1U << SDH_ADMA_SYS_ADDR_LEN) - 1) << SDH_ADMA_SYS_ADDR_POS))
+
+/* 0x60 : Preset Value Register for Initialization */
+#define SDH_PRESET_VALUE_FOR_INIT_OFFSET (0x60)
+#define SDH_SDCLK_FREQ_SEL_VAL           SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS       (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN       (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK       (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK      (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL               SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS           (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN           (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK           (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK          (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL             SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS         (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN         (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK         (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK        (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x62 : Preset Value Register for Default Speed */
+#define SDH_PRESET_VALUE_FOR_DS_OFFSET (0x62)
+#define SDH_SDCLK_FREQ_SEL_VAL         SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS     (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN     (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK     (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK    (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL             SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS         (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN         (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK         (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK        (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL           SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS       (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN       (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK       (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK      (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x64 : Preset Value Register for High Speed */
+#define SDH_PRESET_VALUE_FOR_HS_OFFSET (0x64)
+#define SDH_SDCLK_FREQ_SEL_VAL         SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS     (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN     (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK     (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK    (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL             SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS         (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN         (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK         (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK        (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL           SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS       (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN       (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK       (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK      (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x66 : Preset Value Register for SDR12 */
+#define SDH_PRESET_VALUE_FOR_SDR12_OFFSET (0x66)
+#define SDH_SDCLK_FREQ_SEL_VAL            SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS        (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN        (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK        (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK       (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL                SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS            (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN            (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK            (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK           (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL              SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS          (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN          (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK          (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK         (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x68 : Preset Value Register for SDR25 */
+#define SDH_PRESET_VALUE_FOR_SDR25_OFFSET (0x68)
+#define SDH_SDCLK_FREQ_SEL_VAL            SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS        (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN        (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK        (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK       (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL                SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS            (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN            (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK            (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK           (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL              SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS          (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN          (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK          (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK         (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x6a : Preset Value Register for SDR50 */
+#define SDH_PRESET_VALUE_FOR_SDR50_OFFSET (0x6a)
+#define SDH_SDCLK_FREQ_SEL_VAL            SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS        (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN        (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK        (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK       (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL                SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS            (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN            (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK            (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK           (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL              SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS          (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN          (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK          (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK         (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x6c : Preset Value Register for SDR104 */
+#define SDH_PRESET_VALUE_FOR_SDR104_OFFSET (0x6c)
+#define SDH_SDCLK_FREQ_SEL_VAL             SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS         (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN         (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK         (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK        (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL                 SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS             (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN             (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK             (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK            (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL               SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS           (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN           (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK           (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK          (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0x6e : Preset Value Register for DDR50 */
+#define SDH_PRESET_VALUE_FOR_DDR50_OFFSET (0x6e)
+#define SDH_SDCLK_FREQ_SEL_VAL            SDH_SDCLK_FREQ_SEL_VAL
+#define SDH_SDCLK_FREQ_SEL_VAL_POS        (0U)
+#define SDH_SDCLK_FREQ_SEL_VAL_LEN        (10U)
+#define SDH_SDCLK_FREQ_SEL_VAL_MSK        (((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS)
+#define SDH_SDCLK_FREQ_SEL_VAL_UMSK       (~(((1U << SDH_SDCLK_FREQ_SEL_VAL_LEN) - 1) << SDH_SDCLK_FREQ_SEL_VAL_POS))
+#define SDH_CLKGEN_SEL_VAL                SDH_CLKGEN_SEL_VAL
+#define SDH_CLKGEN_SEL_VAL_POS            (10U)
+#define SDH_CLKGEN_SEL_VAL_LEN            (1U)
+#define SDH_CLKGEN_SEL_VAL_MSK            (((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS)
+#define SDH_CLKGEN_SEL_VAL_UMSK           (~(((1U << SDH_CLKGEN_SEL_VAL_LEN) - 1) << SDH_CLKGEN_SEL_VAL_POS))
+#define SDH_DRV_STRENGTH_VAL              SDH_DRV_STRENGTH_VAL
+#define SDH_DRV_STRENGTH_VAL_POS          (14U)
+#define SDH_DRV_STRENGTH_VAL_LEN          (2U)
+#define SDH_DRV_STRENGTH_VAL_MSK          (((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS)
+#define SDH_DRV_STRENGTH_VAL_UMSK         (~(((1U << SDH_DRV_STRENGTH_VAL_LEN) - 1) << SDH_DRV_STRENGTH_VAL_POS))
+
+/* 0xe0 : Shared Bus Control Register */
+#define SDH_SHARED_BUS_CTRL_OFFSET (0xe0)
+#define SDH_NUM_CLK_PINS           SDH_NUM_CLK_PINS
+#define SDH_NUM_CLK_PINS_POS       (0U)
+#define SDH_NUM_CLK_PINS_LEN       (3U)
+#define SDH_NUM_CLK_PINS_MSK       (((1U << SDH_NUM_CLK_PINS_LEN) - 1) << SDH_NUM_CLK_PINS_POS)
+#define SDH_NUM_CLK_PINS_UMSK      (~(((1U << SDH_NUM_CLK_PINS_LEN) - 1) << SDH_NUM_CLK_PINS_POS))
+#define SDH_NUM_INT_PINS           SDH_NUM_INT_PINS
+#define SDH_NUM_INT_PINS_POS       (4U)
+#define SDH_NUM_INT_PINS_LEN       (2U)
+#define SDH_NUM_INT_PINS_MSK       (((1U << SDH_NUM_INT_PINS_LEN) - 1) << SDH_NUM_INT_PINS_POS)
+#define SDH_NUM_INT_PINS_UMSK      (~(((1U << SDH_NUM_INT_PINS_LEN) - 1) << SDH_NUM_INT_PINS_POS))
+#define SDH_BUS_WIDTH_PRESET       SDH_BUS_WIDTH_PRESET
+#define SDH_BUS_WIDTH_PRESET_POS   (8U)
+#define SDH_BUS_WIDTH_PRESET_LEN   (7U)
+#define SDH_BUS_WIDTH_PRESET_MSK   (((1U << SDH_BUS_WIDTH_PRESET_LEN) - 1) << SDH_BUS_WIDTH_PRESET_POS)
+#define SDH_BUS_WIDTH_PRESET_UMSK  (~(((1U << SDH_BUS_WIDTH_PRESET_LEN) - 1) << SDH_BUS_WIDTH_PRESET_POS))
+#define SDH_CLK_PIN_SEL            SDH_CLK_PIN_SEL
+#define SDH_CLK_PIN_SEL_POS        (16U)
+#define SDH_CLK_PIN_SEL_LEN        (3U)
+#define SDH_CLK_PIN_SEL_MSK        (((1U << SDH_CLK_PIN_SEL_LEN) - 1) << SDH_CLK_PIN_SEL_POS)
+#define SDH_CLK_PIN_SEL_UMSK       (~(((1U << SDH_CLK_PIN_SEL_LEN) - 1) << SDH_CLK_PIN_SEL_POS))
+#define SDH_INT_PIN_SEL            SDH_INT_PIN_SEL
+#define SDH_INT_PIN_SEL_POS        (20U)
+#define SDH_INT_PIN_SEL_LEN        (3U)
+#define SDH_INT_PIN_SEL_MSK        (((1U << SDH_INT_PIN_SEL_LEN) - 1) << SDH_INT_PIN_SEL_POS)
+#define SDH_INT_PIN_SEL_UMSK       (~(((1U << SDH_INT_PIN_SEL_LEN) - 1) << SDH_INT_PIN_SEL_POS))
+#define SDH_BEND_PWR_CTRL          SDH_BEND_PWR_CTRL
+#define SDH_BEND_PWR_CTRL_POS      (24U)
+#define SDH_BEND_PWR_CTRL_LEN      (7U)
+#define SDH_BEND_PWR_CTRL_MSK      (((1U << SDH_BEND_PWR_CTRL_LEN) - 1) << SDH_BEND_PWR_CTRL_POS)
+#define SDH_BEND_PWR_CTRL_UMSK     (~(((1U << SDH_BEND_PWR_CTRL_LEN) - 1) << SDH_BEND_PWR_CTRL_POS))
+
+/* 0xFC : Slot Interrupt Status Register */
+#define SDH_SD_SLOT_INT_STATUS_OFFSET (0xFC)
+#define SDH_SLOT_INT0                 SDH_SLOT_INT0
+#define SDH_SLOT_INT0_POS             (0U)
+#define SDH_SLOT_INT0_LEN             (1U)
+#define SDH_SLOT_INT0_MSK             (((1U << SDH_SLOT_INT0_LEN) - 1) << SDH_SLOT_INT0_POS)
+#define SDH_SLOT_INT0_UMSK            (~(((1U << SDH_SLOT_INT0_LEN) - 1) << SDH_SLOT_INT0_POS))
+#define SDH_SLOT_INT1                 SDH_SLOT_INT1
+#define SDH_SLOT_INT1_POS             (1U)
+#define SDH_SLOT_INT1_LEN             (1U)
+#define SDH_SLOT_INT1_MSK             (((1U << SDH_SLOT_INT1_LEN) - 1) << SDH_SLOT_INT1_POS)
+#define SDH_SLOT_INT1_UMSK            (~(((1U << SDH_SLOT_INT1_LEN) - 1) << SDH_SLOT_INT1_POS))
+
+/* 0xFE : Host Control Version Register */
+#define SDH_SD_HOST_CTRL_VER_OFFSET (0xFE)
+#define SDH_SD_VER                  SDH_SD_VER
+#define SDH_SD_VER_POS              (0U)
+#define SDH_SD_VER_LEN              (8U)
+#define SDH_SD_VER_MSK              (((1U << SDH_SD_VER_LEN) - 1) << SDH_SD_VER_POS)
+#define SDH_SD_VER_UMSK             (~(((1U << SDH_SD_VER_LEN) - 1) << SDH_SD_VER_POS))
+#define SDH_VENDOR_VER              SDH_VENDOR_VER
+#define SDH_VENDOR_VER_POS          (8U)
+#define SDH_VENDOR_VER_LEN          (8U)
+#define SDH_VENDOR_VER_MSK          (((1U << SDH_VENDOR_VER_LEN) - 1) << SDH_VENDOR_VER_POS)
+#define SDH_VENDOR_VER_UMSK         (~(((1U << SDH_VENDOR_VER_LEN) - 1) << SDH_VENDOR_VER_POS))
+
+/* 0x100 : SD Extra Parameters Register */
+#define SDH_SD_CFG_FIFO_PARAM_OFFSET (0x100)
+#define SDH_BOOT_ACK                 SDH_BOOT_ACK
+#define SDH_BOOT_ACK_POS             (3U)
+#define SDH_BOOT_ACK_LEN             (1U)
+#define SDH_BOOT_ACK_MSK             (((1U << SDH_BOOT_ACK_LEN) - 1) << SDH_BOOT_ACK_POS)
+#define SDH_BOOT_ACK_UMSK            (~(((1U << SDH_BOOT_ACK_LEN) - 1) << SDH_BOOT_ACK_POS))
+#define SDH_SQU_EMPTY_CHK            SDH_SQU_EMPTY_CHK
+#define SDH_SQU_EMPTY_CHK_POS        (4U)
+#define SDH_SQU_EMPTY_CHK_LEN        (1U)
+#define SDH_SQU_EMPTY_CHK_MSK        (((1U << SDH_SQU_EMPTY_CHK_LEN) - 1) << SDH_SQU_EMPTY_CHK_POS)
+#define SDH_SQU_EMPTY_CHK_UMSK       (~(((1U << SDH_SQU_EMPTY_CHK_LEN) - 1) << SDH_SQU_EMPTY_CHK_POS))
+#define SDH_SQU_FULL_CHK             SDH_SQU_FULL_CHK
+#define SDH_SQU_FULL_CHK_POS         (5U)
+#define SDH_SQU_FULL_CHK_LEN         (1U)
+#define SDH_SQU_FULL_CHK_MSK         (((1U << SDH_SQU_FULL_CHK_LEN) - 1) << SDH_SQU_FULL_CHK_POS)
+#define SDH_SQU_FULL_CHK_UMSK        (~(((1U << SDH_SQU_FULL_CHK_LEN) - 1) << SDH_SQU_FULL_CHK_POS))
+#define SDH_GEN_PAD_CLK_ON           SDH_GEN_PAD_CLK_ON
+#define SDH_GEN_PAD_CLK_ON_POS       (6U)
+#define SDH_GEN_PAD_CLK_ON_LEN       (1U)
+#define SDH_GEN_PAD_CLK_ON_MSK       (((1U << SDH_GEN_PAD_CLK_ON_LEN) - 1) << SDH_GEN_PAD_CLK_ON_POS)
+#define SDH_GEN_PAD_CLK_ON_UMSK      (~(((1U << SDH_GEN_PAD_CLK_ON_LEN) - 1) << SDH_GEN_PAD_CLK_ON_POS))
+#define SDH_GEN_PAD_CLK_CNT          SDH_GEN_PAD_CLK_CNT
+#define SDH_GEN_PAD_CLK_CNT_POS      (24U)
+#define SDH_GEN_PAD_CLK_CNT_LEN      (8U)
+#define SDH_GEN_PAD_CLK_CNT_MSK      (((1U << SDH_GEN_PAD_CLK_CNT_LEN) - 1) << SDH_GEN_PAD_CLK_CNT_POS)
+#define SDH_GEN_PAD_CLK_CNT_UMSK     (~(((1U << SDH_GEN_PAD_CLK_CNT_LEN) - 1) << SDH_GEN_PAD_CLK_CNT_POS))
+
+/* 0x104 : FIFO Parameters Register */
+#define SDH_SD_FIFO_PARAM_OFFSET  (0x104)
+#define SDH_RTC                   SDH_RTC
+#define SDH_RTC_POS               (0U)
+#define SDH_RTC_LEN               (2U)
+#define SDH_RTC_MSK               (((1U << SDH_RTC_LEN) - 1) << SDH_RTC_POS)
+#define SDH_RTC_UMSK              (~(((1U << SDH_RTC_LEN) - 1) << SDH_RTC_POS))
+#define SDH_WTC                   SDH_WTC
+#define SDH_WTC_POS               (2U)
+#define SDH_WTC_LEN               (2U)
+#define SDH_WTC_MSK               (((1U << SDH_WTC_LEN) - 1) << SDH_WTC_POS)
+#define SDH_WTC_UMSK              (~(((1U << SDH_WTC_LEN) - 1) << SDH_WTC_POS))
+#define SDH_FIFO_CLK              SDH_FIFO_CLK
+#define SDH_FIFO_CLK_POS          (4U)
+#define SDH_FIFO_CLK_LEN          (1U)
+#define SDH_FIFO_CLK_MSK          (((1U << SDH_FIFO_CLK_LEN) - 1) << SDH_FIFO_CLK_POS)
+#define SDH_FIFO_CLK_UMSK         (~(((1U << SDH_FIFO_CLK_LEN) - 1) << SDH_FIFO_CLK_POS))
+#define SDH_FIFO_CS               SDH_FIFO_CS
+#define SDH_FIFO_CS_POS           (5U)
+#define SDH_FIFO_CS_LEN           (1U)
+#define SDH_FIFO_CS_MSK           (((1U << SDH_FIFO_CS_LEN) - 1) << SDH_FIFO_CS_POS)
+#define SDH_FIFO_CS_UMSK          (~(((1U << SDH_FIFO_CS_LEN) - 1) << SDH_FIFO_CS_POS))
+#define SDH_PDWN                  SDH_PDWN
+#define SDH_PDWN_POS              (6U)
+#define SDH_PDWN_LEN              (1U)
+#define SDH_PDWN_MSK              (((1U << SDH_PDWN_LEN) - 1) << SDH_PDWN_POS)
+#define SDH_PDWN_UMSK             (~(((1U << SDH_PDWN_LEN) - 1) << SDH_PDWN_POS))
+#define SDH_USE_DAT3              SDH_USE_DAT3
+#define SDH_USE_DAT3_POS          (7U)
+#define SDH_USE_DAT3_LEN          (1U)
+#define SDH_USE_DAT3_MSK          (((1U << SDH_USE_DAT3_LEN) - 1) << SDH_USE_DAT3_POS)
+#define SDH_USE_DAT3_UMSK         (~(((1U << SDH_USE_DAT3_LEN) - 1) << SDH_USE_DAT3_POS))
+#define SDH_CLK_GATE_CTL          SDH_CLK_GATE_CTL
+#define SDH_CLK_GATE_CTL_POS      (8U)
+#define SDH_CLK_GATE_CTL_LEN      (1U)
+#define SDH_CLK_GATE_CTL_MSK      (((1U << SDH_CLK_GATE_CTL_LEN) - 1) << SDH_CLK_GATE_CTL_POS)
+#define SDH_CLK_GATE_CTL_UMSK     (~(((1U << SDH_CLK_GATE_CTL_LEN) - 1) << SDH_CLK_GATE_CTL_POS))
+#define SDH_CLK_GATE_ON           SDH_CLK_GATE_ON
+#define SDH_CLK_GATE_ON_POS       (9U)
+#define SDH_CLK_GATE_ON_LEN       (1U)
+#define SDH_CLK_GATE_ON_MSK       (((1U << SDH_CLK_GATE_ON_LEN) - 1) << SDH_CLK_GATE_ON_POS)
+#define SDH_CLK_GATE_ON_UMSK      (~(((1U << SDH_CLK_GATE_ON_LEN) - 1) << SDH_CLK_GATE_ON_POS))
+#define SDH_OVRRD_CLK_OEN         SDH_OVRRD_CLK_OEN
+#define SDH_OVRRD_CLK_OEN_POS     (11U)
+#define SDH_OVRRD_CLK_OEN_LEN     (1U)
+#define SDH_OVRRD_CLK_OEN_MSK     (((1U << SDH_OVRRD_CLK_OEN_LEN) - 1) << SDH_OVRRD_CLK_OEN_POS)
+#define SDH_OVRRD_CLK_OEN_UMSK    (~(((1U << SDH_OVRRD_CLK_OEN_LEN) - 1) << SDH_OVRRD_CLK_OEN_POS))
+#define SDH_FORCE_CLK_ON          SDH_FORCE_CLK_ON
+#define SDH_FORCE_CLK_ON_POS      (12U)
+#define SDH_FORCE_CLK_ON_LEN      (1U)
+#define SDH_FORCE_CLK_ON_MSK      (((1U << SDH_FORCE_CLK_ON_LEN) - 1) << SDH_FORCE_CLK_ON_POS)
+#define SDH_FORCE_CLK_ON_UMSK     (~(((1U << SDH_FORCE_CLK_ON_LEN) - 1) << SDH_FORCE_CLK_ON_POS))
+#define SDH_PDFVSSM               SDH_PDFVSSM
+#define SDH_PDFVSSM_POS           (13U)
+#define SDH_PDFVSSM_LEN           (1U)
+#define SDH_PDFVSSM_MSK           (((1U << SDH_PDFVSSM_LEN) - 1) << SDH_PDFVSSM_POS)
+#define SDH_PDFVSSM_UMSK          (~(((1U << SDH_PDFVSSM_LEN) - 1) << SDH_PDFVSSM_POS))
+#define SDH_PDLVMC                SDH_PDLVMC
+#define SDH_PDLVMC_POS            (14U)
+#define SDH_PDLVMC_LEN            (1U)
+#define SDH_PDLVMC_MSK            (((1U << SDH_PDLVMC_LEN) - 1) << SDH_PDLVMC_POS)
+#define SDH_PDLVMC_UMSK           (~(((1U << SDH_PDLVMC_LEN) - 1) << SDH_PDLVMC_POS))
+#define SDH_PRE_GATE_CLK_CNT      SDH_PRE_GATE_CLK_CNT
+#define SDH_PRE_GATE_CLK_CNT_POS  (16U)
+#define SDH_PRE_GATE_CLK_CNT_LEN  (4U)
+#define SDH_PRE_GATE_CLK_CNT_MSK  (((1U << SDH_PRE_GATE_CLK_CNT_LEN) - 1) << SDH_PRE_GATE_CLK_CNT_POS)
+#define SDH_PRE_GATE_CLK_CNT_UMSK (~(((1U << SDH_PRE_GATE_CLK_CNT_LEN) - 1) << SDH_PRE_GATE_CLK_CNT_POS))
+
+/* 0x108 : SPI Mode Register */
+#define SDH_SD_SPI_MODE_OFFSET (0x108)
+#define SDH_SPI_EN             SDH_SPI_EN
+#define SDH_SPI_EN_POS         (0U)
+#define SDH_SPI_EN_LEN         (1U)
+#define SDH_SPI_EN_MSK         (((1U << SDH_SPI_EN_LEN) - 1) << SDH_SPI_EN_POS)
+#define SDH_SPI_EN_UMSK        (~(((1U << SDH_SPI_EN_LEN) - 1) << SDH_SPI_EN_POS))
+#define SDH_SPI_ERR_TOKEN      SDH_SPI_ERR_TOKEN
+#define SDH_SPI_ERR_TOKEN_POS  (8U)
+#define SDH_SPI_ERR_TOKEN_LEN  (5U)
+#define SDH_SPI_ERR_TOKEN_MSK  (((1U << SDH_SPI_ERR_TOKEN_LEN) - 1) << SDH_SPI_ERR_TOKEN_POS)
+#define SDH_SPI_ERR_TOKEN_UMSK (~(((1U << SDH_SPI_ERR_TOKEN_LEN) - 1) << SDH_SPI_ERR_TOKEN_POS))
+
+/* 0x10a : Clock and Burst Size Setup Register */
+#define SDH_SD_CLOCK_AND_BURST_SIZE_SETUP_OFFSET (0x10a)
+#define SDH_BRST_SIZE                            SDH_BRST_SIZE
+#define SDH_BRST_SIZE_POS                        (0U)
+#define SDH_BRST_SIZE_LEN                        (2U)
+#define SDH_BRST_SIZE_MSK                        (((1U << SDH_BRST_SIZE_LEN) - 1) << SDH_BRST_SIZE_POS)
+#define SDH_BRST_SIZE_UMSK                       (~(((1U << SDH_BRST_SIZE_LEN) - 1) << SDH_BRST_SIZE_POS))
+#define SDH_DMA_SIZE                             SDH_DMA_SIZE
+#define SDH_DMA_SIZE_POS                         (2U)
+#define SDH_DMA_SIZE_LEN                         (2U)
+#define SDH_DMA_SIZE_MSK                         (((1U << SDH_DMA_SIZE_LEN) - 1) << SDH_DMA_SIZE_POS)
+#define SDH_DMA_SIZE_UMSK                        (~(((1U << SDH_DMA_SIZE_LEN) - 1) << SDH_DMA_SIZE_POS))
+#define SDH_PRIORITY                             SDH_PRIORITY
+#define SDH_PRIORITY_POS                         (4U)
+#define SDH_PRIORITY_LEN                         (1U)
+#define SDH_PRIORITY_MSK                         (((1U << SDH_PRIORITY_LEN) - 1) << SDH_PRIORITY_POS)
+#define SDH_PRIORITY_UMSK                        (~(((1U << SDH_PRIORITY_LEN) - 1) << SDH_PRIORITY_POS))
+#define SDH_AXI_NON_POST_WR                      SDH_AXI_NON_POST_WR
+#define SDH_AXI_NON_POST_WR_POS                  (5U)
+#define SDH_AXI_NON_POST_WR_LEN                  (1U)
+#define SDH_AXI_NON_POST_WR_MSK                  (((1U << SDH_AXI_NON_POST_WR_LEN) - 1) << SDH_AXI_NON_POST_WR_POS)
+#define SDH_AXI_NON_POST_WR_UMSK                 (~(((1U << SDH_AXI_NON_POST_WR_LEN) - 1) << SDH_AXI_NON_POST_WR_POS))
+#define SDH_RD_ENDIAN                            SDH_RD_ENDIAN
+#define SDH_RD_ENDIAN_POS                        (6U)
+#define SDH_RD_ENDIAN_LEN                        (1U)
+#define SDH_RD_ENDIAN_MSK                        (((1U << SDH_RD_ENDIAN_LEN) - 1) << SDH_RD_ENDIAN_POS)
+#define SDH_RD_ENDIAN_UMSK                       (~(((1U << SDH_RD_ENDIAN_LEN) - 1) << SDH_RD_ENDIAN_POS))
+#define SDH_WR_ENDIAN                            SDH_WR_ENDIAN
+#define SDH_WR_ENDIAN_POS                        (7U)
+#define SDH_WR_ENDIAN_LEN                        (1U)
+#define SDH_WR_ENDIAN_MSK                        (((1U << SDH_WR_ENDIAN_LEN) - 1) << SDH_WR_ENDIAN_POS)
+#define SDH_WR_ENDIAN_UMSK                       (~(((1U << SDH_WR_ENDIAN_LEN) - 1) << SDH_WR_ENDIAN_POS))
+#define SDH_RD_OSTDG                             SDH_RD_OSTDG
+#define SDH_RD_OSTDG_POS                         (14U)
+#define SDH_RD_OSTDG_LEN                         (1U)
+#define SDH_RD_OSTDG_MSK                         (((1U << SDH_RD_OSTDG_LEN) - 1) << SDH_RD_OSTDG_POS)
+#define SDH_RD_OSTDG_UMSK                        (~(((1U << SDH_RD_OSTDG_LEN) - 1) << SDH_RD_OSTDG_POS))
+#define SDH_WR_OSTDG                             SDH_WR_OSTDG
+#define SDH_WR_OSTDG_POS                         (15U)
+#define SDH_WR_OSTDG_LEN                         (1U)
+#define SDH_WR_OSTDG_MSK                         (((1U << SDH_WR_OSTDG_LEN) - 1) << SDH_WR_OSTDG_POS)
+#define SDH_WR_OSTDG_UMSK                        (~(((1U << SDH_WR_OSTDG_LEN) - 1) << SDH_WR_OSTDG_POS))
+
+/* 0x10c : CE-ATA Register 1 */
+#define SDH_SD_CE_ATA_1_OFFSET (0x10c)
+#define SDH_CPL_TIMEOUT        SDH_CPL_TIMEOUT
+#define SDH_CPL_TIMEOUT_POS    (0U)
+#define SDH_CPL_TIMEOUT_LEN    (14U)
+#define SDH_CPL_TIMEOUT_MSK    (((1U << SDH_CPL_TIMEOUT_LEN) - 1) << SDH_CPL_TIMEOUT_POS)
+#define SDH_CPL_TIMEOUT_UMSK   (~(((1U << SDH_CPL_TIMEOUT_LEN) - 1) << SDH_CPL_TIMEOUT_POS))
+
+/* 0x10e : CE-ATA Register 2 */
+#define SDH_SD_CE_ATA_2_OFFSET       (0x10e)
+#define SDH_MISC_INT_INT_EN          SDH_MISC_INT_INT_EN
+#define SDH_MISC_INT_INT_EN_POS      (0U)
+#define SDH_MISC_INT_INT_EN_LEN      (1U)
+#define SDH_MISC_INT_INT_EN_MSK      (((1U << SDH_MISC_INT_INT_EN_LEN) - 1) << SDH_MISC_INT_INT_EN_POS)
+#define SDH_MISC_INT_INT_EN_UMSK     (~(((1U << SDH_MISC_INT_INT_EN_LEN) - 1) << SDH_MISC_INT_INT_EN_POS))
+#define SDH_MISC_INT_EN              SDH_MISC_INT_EN
+#define SDH_MISC_INT_EN_POS          (1U)
+#define SDH_MISC_INT_EN_LEN          (1U)
+#define SDH_MISC_INT_EN_MSK          (((1U << SDH_MISC_INT_EN_LEN) - 1) << SDH_MISC_INT_EN_POS)
+#define SDH_MISC_INT_EN_UMSK         (~(((1U << SDH_MISC_INT_EN_LEN) - 1) << SDH_MISC_INT_EN_POS))
+#define SDH_MISC_INT                 SDH_MISC_INT
+#define SDH_MISC_INT_POS             (2U)
+#define SDH_MISC_INT_LEN             (1U)
+#define SDH_MISC_INT_MSK             (((1U << SDH_MISC_INT_LEN) - 1) << SDH_MISC_INT_POS)
+#define SDH_MISC_INT_UMSK            (~(((1U << SDH_MISC_INT_LEN) - 1) << SDH_MISC_INT_POS))
+#define SDH_CPL_COMPLETE_INT_EN      SDH_CPL_COMPLETE_INT_EN
+#define SDH_CPL_COMPLETE_INT_EN_POS  (4U)
+#define SDH_CPL_COMPLETE_INT_EN_LEN  (1U)
+#define SDH_CPL_COMPLETE_INT_EN_MSK  (((1U << SDH_CPL_COMPLETE_INT_EN_LEN) - 1) << SDH_CPL_COMPLETE_INT_EN_POS)
+#define SDH_CPL_COMPLETE_INT_EN_UMSK (~(((1U << SDH_CPL_COMPLETE_INT_EN_LEN) - 1) << SDH_CPL_COMPLETE_INT_EN_POS))
+#define SDH_CPL_COMPLETE_EN          SDH_CPL_COMPLETE_EN
+#define SDH_CPL_COMPLETE_EN_POS      (5U)
+#define SDH_CPL_COMPLETE_EN_LEN      (1U)
+#define SDH_CPL_COMPLETE_EN_MSK      (((1U << SDH_CPL_COMPLETE_EN_LEN) - 1) << SDH_CPL_COMPLETE_EN_POS)
+#define SDH_CPL_COMPLETE_EN_UMSK     (~(((1U << SDH_CPL_COMPLETE_EN_LEN) - 1) << SDH_CPL_COMPLETE_EN_POS))
+#define SDH_CPL_COMPLETE             SDH_CPL_COMPLETE
+#define SDH_CPL_COMPLETE_POS         (6U)
+#define SDH_CPL_COMPLETE_LEN         (1U)
+#define SDH_CPL_COMPLETE_MSK         (((1U << SDH_CPL_COMPLETE_LEN) - 1) << SDH_CPL_COMPLETE_POS)
+#define SDH_CPL_COMPLETE_UMSK        (~(((1U << SDH_CPL_COMPLETE_LEN) - 1) << SDH_CPL_COMPLETE_POS))
+#define SDH_MMC_RESETN               SDH_MMC_RESETN
+#define SDH_MMC_RESETN_POS           (11U)
+#define SDH_MMC_RESETN_LEN           (1U)
+#define SDH_MMC_RESETN_MSK           (((1U << SDH_MMC_RESETN_LEN) - 1) << SDH_MMC_RESETN_POS)
+#define SDH_MMC_RESETN_UMSK          (~(((1U << SDH_MMC_RESETN_LEN) - 1) << SDH_MMC_RESETN_POS))
+#define SDH_MMC_CARD                 SDH_MMC_CARD
+#define SDH_MMC_CARD_POS             (12U)
+#define SDH_MMC_CARD_LEN             (1U)
+#define SDH_MMC_CARD_MSK             (((1U << SDH_MMC_CARD_LEN) - 1) << SDH_MMC_CARD_POS)
+#define SDH_MMC_CARD_UMSK            (~(((1U << SDH_MMC_CARD_LEN) - 1) << SDH_MMC_CARD_POS))
+#define SDH_CEATA_CARD               SDH_CEATA_CARD
+#define SDH_CEATA_CARD_POS           (13U)
+#define SDH_CEATA_CARD_LEN           (1U)
+#define SDH_CEATA_CARD_MSK           (((1U << SDH_CEATA_CARD_LEN) - 1) << SDH_CEATA_CARD_POS)
+#define SDH_CEATA_CARD_UMSK          (~(((1U << SDH_CEATA_CARD_LEN) - 1) << SDH_CEATA_CARD_POS))
+#define SDH_SND_CPL                  SDH_SND_CPL
+#define SDH_SND_CPL_POS              (14U)
+#define SDH_SND_CPL_LEN              (1U)
+#define SDH_SND_CPL_MSK              (((1U << SDH_SND_CPL_LEN) - 1) << SDH_SND_CPL_POS)
+#define SDH_SND_CPL_UMSK             (~(((1U << SDH_SND_CPL_LEN) - 1) << SDH_SND_CPL_POS))
+#define SDH_CHK_CPL                  SDH_CHK_CPL
+#define SDH_CHK_CPL_POS              (15U)
+#define SDH_CHK_CPL_LEN              (1U)
+#define SDH_CHK_CPL_MSK              (((1U << SDH_CHK_CPL_LEN) - 1) << SDH_CHK_CPL_POS)
+#define SDH_CHK_CPL_UMSK             (~(((1U << SDH_CHK_CPL_LEN) - 1) << SDH_CHK_CPL_POS))
+
+/* 0x110 : PAD I/O Setup Register */
+#define SDH_SD_PAD_IO_SETUP_OFFSET (0x110)
+#define SDH_ASYNC_IO_EN            SDH_ASYNC_IO_EN
+#define SDH_ASYNC_IO_EN_POS        (0U)
+#define SDH_ASYNC_IO_EN_LEN        (1U)
+#define SDH_ASYNC_IO_EN_MSK        (((1U << SDH_ASYNC_IO_EN_LEN) - 1) << SDH_ASYNC_IO_EN_POS)
+#define SDH_ASYNC_IO_EN_UMSK       (~(((1U << SDH_ASYNC_IO_EN_LEN) - 1) << SDH_ASYNC_IO_EN_POS))
+#define SDH_INAND_SEL              SDH_INAND_SEL
+#define SDH_INAND_SEL_POS          (1U)
+#define SDH_INAND_SEL_LEN          (1U)
+#define SDH_INAND_SEL_MSK          (((1U << SDH_INAND_SEL_LEN) - 1) << SDH_INAND_SEL_POS)
+#define SDH_INAND_SEL_UMSK         (~(((1U << SDH_INAND_SEL_LEN) - 1) << SDH_INAND_SEL_POS))
+#define SDH_ECO_REG                SDH_ECO_REG
+#define SDH_ECO_REG_POS            (16U)
+#define SDH_ECO_REG_LEN            (8U)
+#define SDH_ECO_REG_MSK            (((1U << SDH_ECO_REG_LEN) - 1) << SDH_ECO_REG_POS)
+#define SDH_ECO_REG_UMSK           (~(((1U << SDH_ECO_REG_LEN) - 1) << SDH_ECO_REG_POS))
+
+/* 0x114 : RX Configuration Register */
+#define SDH_RX_CFG_REG_OFFSET   (0x114)
+#define SDH_SDCLK_SEL0          SDH_SDCLK_SEL0
+#define SDH_SDCLK_SEL0_POS      (0U)
+#define SDH_SDCLK_SEL0_LEN      (2U)
+#define SDH_SDCLK_SEL0_MSK      (((1U << SDH_SDCLK_SEL0_LEN) - 1) << SDH_SDCLK_SEL0_POS)
+#define SDH_SDCLK_SEL0_UMSK     (~(((1U << SDH_SDCLK_SEL0_LEN) - 1) << SDH_SDCLK_SEL0_POS))
+#define SDH_SDCLK_SEL1          SDH_SDCLK_SEL1
+#define SDH_SDCLK_SEL1_POS      (2U)
+#define SDH_SDCLK_SEL1_LEN      (2U)
+#define SDH_SDCLK_SEL1_MSK      (((1U << SDH_SDCLK_SEL1_LEN) - 1) << SDH_SDCLK_SEL1_POS)
+#define SDH_SDCLK_SEL1_UMSK     (~(((1U << SDH_SDCLK_SEL1_LEN) - 1) << SDH_SDCLK_SEL1_POS))
+#define SDH_SDCLK_DELAY         SDH_SDCLK_DELAY
+#define SDH_SDCLK_DELAY_POS     (8U)
+#define SDH_SDCLK_DELAY_LEN     (10U)
+#define SDH_SDCLK_DELAY_MSK     (((1U << SDH_SDCLK_DELAY_LEN) - 1) << SDH_SDCLK_DELAY_POS)
+#define SDH_SDCLK_DELAY_UMSK    (~(((1U << SDH_SDCLK_DELAY_LEN) - 1) << SDH_SDCLK_DELAY_POS))
+#define SDH_TUNING_DLY_INC      SDH_TUNING_DLY_INC
+#define SDH_TUNING_DLY_INC_POS  (18U)
+#define SDH_TUNING_DLY_INC_LEN  (10U)
+#define SDH_TUNING_DLY_INC_MSK  (((1U << SDH_TUNING_DLY_INC_LEN) - 1) << SDH_TUNING_DLY_INC_POS)
+#define SDH_TUNING_DLY_INC_UMSK (~(((1U << SDH_TUNING_DLY_INC_LEN) - 1) << SDH_TUNING_DLY_INC_POS))
+
+/* 0x118 : TX Configuration Register */
+#define SDH_TX_CFG_REG_OFFSET   (0x118)
+#define SDH_TX_HOLD_DELAY0      SDH_TX_HOLD_DELAY0
+#define SDH_TX_HOLD_DELAY0_POS  (0U)
+#define SDH_TX_HOLD_DELAY0_LEN  (10U)
+#define SDH_TX_HOLD_DELAY0_MSK  (((1U << SDH_TX_HOLD_DELAY0_LEN) - 1) << SDH_TX_HOLD_DELAY0_POS)
+#define SDH_TX_HOLD_DELAY0_UMSK (~(((1U << SDH_TX_HOLD_DELAY0_LEN) - 1) << SDH_TX_HOLD_DELAY0_POS))
+#define SDH_TX_HOLD_DELAY1      SDH_TX_HOLD_DELAY1
+#define SDH_TX_HOLD_DELAY1_POS  (16U)
+#define SDH_TX_HOLD_DELAY1_LEN  (10U)
+#define SDH_TX_HOLD_DELAY1_MSK  (((1U << SDH_TX_HOLD_DELAY1_LEN) - 1) << SDH_TX_HOLD_DELAY1_POS)
+#define SDH_TX_HOLD_DELAY1_UMSK (~(((1U << SDH_TX_HOLD_DELAY1_LEN) - 1) << SDH_TX_HOLD_DELAY1_POS))
+#define SDH_TX_INT_CLK_SEL      SDH_TX_INT_CLK_SEL
+#define SDH_TX_INT_CLK_SEL_POS  (30U)
+#define SDH_TX_INT_CLK_SEL_LEN  (1U)
+#define SDH_TX_INT_CLK_SEL_MSK  (((1U << SDH_TX_INT_CLK_SEL_LEN) - 1) << SDH_TX_INT_CLK_SEL_POS)
+#define SDH_TX_INT_CLK_SEL_UMSK (~(((1U << SDH_TX_INT_CLK_SEL_LEN) - 1) << SDH_TX_INT_CLK_SEL_POS))
+#define SDH_TX_MUX_SEL          SDH_TX_MUX_SEL
+#define SDH_TX_MUX_SEL_POS      (31U)
+#define SDH_TX_MUX_SEL_LEN      (1U)
+#define SDH_TX_MUX_SEL_MSK      (((1U << SDH_TX_MUX_SEL_LEN) - 1) << SDH_TX_MUX_SEL_POS)
+#define SDH_TX_MUX_SEL_UMSK     (~(((1U << SDH_TX_MUX_SEL_LEN) - 1) << SDH_TX_MUX_SEL_POS))
+
+/* 0x11c : TUNING CONFIG Register */
+#define SDH_TUNING_CFG_REG_OFFSET   (0x11c)
+#define SDH_TUNING_TT_CNT           SDH_TUNING_TT_CNT
+#define SDH_TUNING_TT_CNT_POS       (0U)
+#define SDH_TUNING_TT_CNT_LEN       (8U)
+#define SDH_TUNING_TT_CNT_MSK       (((1U << SDH_TUNING_TT_CNT_LEN) - 1) << SDH_TUNING_TT_CNT_POS)
+#define SDH_TUNING_TT_CNT_UMSK      (~(((1U << SDH_TUNING_TT_CNT_LEN) - 1) << SDH_TUNING_TT_CNT_POS))
+#define SDH_TUNING_WD_CNT           SDH_TUNING_WD_CNT
+#define SDH_TUNING_WD_CNT_POS       (8U)
+#define SDH_TUNING_WD_CNT_LEN       (6U)
+#define SDH_TUNING_WD_CNT_MSK       (((1U << SDH_TUNING_WD_CNT_LEN) - 1) << SDH_TUNING_WD_CNT_POS)
+#define SDH_TUNING_WD_CNT_UMSK      (~(((1U << SDH_TUNING_WD_CNT_LEN) - 1) << SDH_TUNING_WD_CNT_POS))
+#define SDH_TUNING_CLK_DLY          SDH_TUNING_CLK_DLY
+#define SDH_TUNING_CLK_DLY_POS      (14U)
+#define SDH_TUNING_CLK_DLY_LEN      (10U)
+#define SDH_TUNING_CLK_DLY_MSK      (((1U << SDH_TUNING_CLK_DLY_LEN) - 1) << SDH_TUNING_CLK_DLY_POS)
+#define SDH_TUNING_CLK_DLY_UMSK     (~(((1U << SDH_TUNING_CLK_DLY_LEN) - 1) << SDH_TUNING_CLK_DLY_POS))
+#define SDH_TUNING_SUCCESS_CNT      SDH_TUNING_SUCCESS_CNT
+#define SDH_TUNING_SUCCESS_CNT_POS  (24U)
+#define SDH_TUNING_SUCCESS_CNT_LEN  (6U)
+#define SDH_TUNING_SUCCESS_CNT_MSK  (((1U << SDH_TUNING_SUCCESS_CNT_LEN) - 1) << SDH_TUNING_SUCCESS_CNT_POS)
+#define SDH_TUNING_SUCCESS_CNT_UMSK (~(((1U << SDH_TUNING_SUCCESS_CNT_LEN) - 1) << SDH_TUNING_SUCCESS_CNT_POS))
+
+struct sdh_reg {
+    /* 0x00 : System Address Low Register */
+    union {
+        struct
+        {
+            uint16_t DMA_ADDR_L : 16; /* [15: 0],         RW,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_SYS_ADDR_LOW;
+
+    /* 0x02 : System Address High Register */
+    union {
+        struct
+        {
+            uint16_t DMA_ADDR_H : 16; /* [15: 0],         RW,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_SYS_ADDR_HIGH;
+
+    /* 0x04 : Block Size Register */
+    union {
+        struct
+        {
+            uint16_t BLOCK_SIZE    : 12; /* [11: 0],         RW,      0x000 */
+            uint16_t HOST_DMA_BDRY : 3;  /* [14:12],         RW,        0x0 */
+            uint16_t Reserved_15   : 1;  /* [   15],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_BLOCK_SIZE;
+
+    /* 0x06 : Block Count Register */
+    union {
+        struct
+        {
+            uint16_t BLOCK_COUNT : 16; /* [15: 0],         RW,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_BLOCK_COUNT;
+
+    /* 0x08 : Argument Low Register */
+    union {
+        struct
+        {
+            uint16_t ARG_L : 16; /* [15: 0],        RW ,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ARG_LOW;
+
+    /* 0x0A : Argument High Register */
+    union {
+        struct
+        {
+            uint16_t ARG_H : 16; /* [15: 0],         RW,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ARG_HIGH;
+
+    /* 0x0C : Transfer Mode Register */
+    union {
+        struct
+        {
+            uint16_t DMA_EN        : 1;  /* [    0],         RW,        0x0 */
+            uint16_t BLK_CNT_EN    : 1;  /* [    1],         RW,        0x0 */
+            uint16_t AUTO_CMD_EN   : 2;  /* [ 3: 2],         RW,        0x0 */
+            uint16_t TO_HOST_DIR   : 1;  /* [    4],         RW,        0x0 */
+            uint16_t MULTI_BLK_SEL : 1;  /* [    5],         RW,        0x0 */
+            uint16_t Reserved_15_6 : 10; /* [15: 6],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_TRANSFER_MODE;
+
+    /* 0x0E : Command Register */
+    union {
+        struct
+        {
+            uint16_t RESP_TYPE        : 2; /* [ 1: 0],         RW,        0x0 */
+            uint16_t Reserved_2       : 1; /* [    2],       RSVD,        0x0 */
+            uint16_t CMD_CRC_CHK_EN   : 1; /* [    3],         RW,        0x0 */
+            uint16_t CMD_INDEX_CHK_EN : 1; /* [    4],         RW,        0x0 */
+            uint16_t DATA_PRESENT     : 1; /* [    5],         RW,        0x0 */
+            uint16_t CMD_TYPE         : 2; /* [ 7: 6],         RW,        0x0 */
+            uint16_t CMD_INDEX        : 6; /* [13: 8],         RW,       0x00 */
+            uint16_t Reserved_15_14   : 2; /* [15:14],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CMD;
+
+    /* 0x10 : Response Register 0 */
+    union {
+        struct
+        {
+            uint16_t RESP0 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_0;
+
+    /* 0x12 : Response Register 1 */
+    union {
+        struct
+        {
+            uint16_t RESP1 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_1;
+
+    /* 0x14 : Response Register 2 */
+    union {
+        struct
+        {
+            uint16_t RESP2 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_2;
+
+    /* 0x16 : Response Register 3 */
+    union {
+        struct
+        {
+            uint16_t RESP3 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_3;
+
+    /* 0x18 : Response Register 4 */
+    union {
+        struct
+        {
+            uint16_t RESP4 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_4;
+
+    /* 0x1A : Response Register 5 */
+    union {
+        struct
+        {
+            uint16_t RESP5 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_5;
+
+    /* 0x1C : Response Register 6 */
+    union {
+        struct
+        {
+            uint16_t RESP6 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_6;
+
+    /* 0x1E : Response Register 7 */
+    union {
+        struct
+        {
+            uint16_t RESP7 : 16; /* [15: 0],         RO,     0x0000 */
+        } BF;
+        uint16_t SHORT;
+    } SD_RESP_7;
+
+    /* 0x20 : Buffer Data Port 0 Register */
+    union {
+        struct
+        {
+            uint16_t CPU_DATA0 : 16; /* [15: 0],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_BUFFER_DATA_PORT_0;
+
+    /* 0x22 : Buffer Data Port 1 Register */
+    union {
+        struct
+        {
+            uint16_t CPU_DATA1 : 16; /* [15: 0],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_BUFFER_DATA_PORT_1;
+
+    /* 0x24 : Present State Register 1 */
+    union {
+        struct
+        {
+            uint16_t CMD_INHIBIT_CMD : 1; /* [    0],         RO,        0x0 */
+            uint16_t CMD_INHIBIT_DAT : 1; /* [    1],         RO,        0x0 */
+            uint16_t _DAT_ACTIVE     : 1; /* [    2],         RO,        0x0 */
+            uint16_t RETUNING_REQ    : 1; /* [    3],         RO,        0x0 */
+            uint16_t Reserved_7_4    : 4; /* [ 7: 4],       RSVD,        0x0 */
+            uint16_t TX_ACTIVE       : 1; /* [    8],         RO,        0x0 */
+            uint16_t RX_ACTIVE       : 1; /* [    9],         RO,        0x0 */
+            uint16_t BUFFER_WR_EN    : 1; /* [   10],         RO,        0x1 */
+            uint16_t BUFFER_RD_EN    : 1; /* [   11],         RO,        0x0 */
+            uint16_t Reserved_15_12  : 4; /* [15:12],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_PRESENT_STATE_1;
+
+    /* 0x26 : Present State Register 2 */
+    union {
+        struct
+        {
+            uint16_t CARD_INSERTED : 1; /* [    0],         RO,        0x0 */
+            uint16_t CARD_STABLE   : 1; /* [    1],         RO,        0x0 */
+            uint16_t CARD_DET      : 1; /* [    2],         RO,        0x0 */
+            uint16_t WRITE_PROT    : 1; /* [    3],         RO,        0x0 */
+            uint16_t DAT_LEVEL     : 4; /* [ 7: 4],         RO,        0xF */
+            uint16_t CMD_LEVEL     : 1; /* [    8],         RO,        0x1 */
+            uint16_t Reserved_15_9 : 7; /* [15: 9],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_PRESENT_STATE_2;
+
+    /* 0x28 : Host Control Register */
+    union {
+        struct
+        {
+            uint16_t LED_CTRL       : 1; /* [    0],         RW,        0x0 */
+            uint16_t DATA_WIDTH     : 1; /* [    1],         RW,        0x0 */
+            uint16_t HI_SPEED_EN    : 1; /* [    2],         RW,        0x0 */
+            uint16_t DMA_SEL        : 2; /* [ 4: 3],         RW,        0x0 */
+            uint16_t EX_DATA_WIDTH  : 1; /* [    5],         RW,        0x0 */
+            uint16_t CARD_DET_L     : 1; /* [    6],         RW,        0x0 */
+            uint16_t CARD_DET_S     : 1; /* [    7],         RW,        0x0 */
+            uint16_t SD_BUS_POWER   : 1; /* [    8],         RW,        0x0 */
+            uint16_t SD_BUS_VLT     : 3; /* [11: 9],         RW,        0x0 */
+            uint16_t Reserved_15_12 : 4; /* [15:12],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_HOST_CTRL;
+
+    /* 0x2A : Block Gap Control Register */
+    union {
+        struct
+        {
+            uint16_t STOP_AT_BLOCK_GAP_REQ : 1; /* [    0],         RW,        0x0 */
+            uint16_t CONT_REQ              : 1; /* [    1],       RWAC,        0x0 */
+            uint16_t RD_WAIT_CTL           : 1; /* [    2],         RW,        0x0 */
+            uint16_t INT_BLK_GAP           : 1; /* [    3],         RW,        0x0 */
+            uint16_t Reserved_7_4          : 4; /* [ 7: 4],       RSVD,        0x0 */
+            uint16_t W_CARD_INT            : 1; /* [    8],         RW,        0x0 */
+            uint16_t W_INSERTION           : 1; /* [    9],         RW,        0x0 */
+            uint16_t W_REMOVAL             : 1; /* [   10],         RW,        0x0 */
+            uint16_t Reserved_15_11        : 5; /* [15:11],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_BLOCK_GAP_CTRL;
+
+    /* 0x2C : Clock Control Register */
+    union {
+        struct
+        {
+            uint16_t INT_CLK_EN     : 1; /* [    0],         RW,        0x0 */
+            uint16_t INT_CLK_STABLE : 1; /* [    1],         RO,        0x0 */
+            uint16_t SD_CLK_EN      : 1; /* [    2],         RW,        0x0 */
+            uint16_t Reserved_4_3   : 2; /* [ 4: 3],       RSVD,        0x0 */
+            uint16_t CLK_GEN_SEL    : 1; /* [    5],         RW,        0x0 */
+            uint16_t SD_FREQ_SEL_HI : 2; /* [ 7: 6],         RW,        0x0 */
+            uint16_t SD_FREQ_SEL_LO : 8; /* [15: 8],         RW,       0x00 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CLOCK_CTRL;
+
+    /* 0x2E : Timeout Control/Software Reset Register */
+    union {
+        struct
+        {
+            uint16_t TIMEOUT_VALUE  : 4; /* [ 3: 0],         RW,        0x0 */
+            uint16_t Reserved_7_4   : 4; /* [ 7: 4],       RSVD,        0x0 */
+            uint16_t SW_RST_ALL     : 1; /* [    8],       RWAC,        0x0 */
+            uint16_t SW_RST_CMD     : 1; /* [    9],       RWAC,        0x0 */
+            uint16_t SW_RST_DAT     : 1; /* [   10],       RWAC,        0x0 */
+            uint16_t Reserved_15_11 : 5; /* [15:11],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_TIMEOUT_CTRL_SW_RESET;
+
+    /* 0x30 : Normal Interrupt Status Register */
+    union {
+        struct
+        {
+            uint16_t CMD_COMPLETE   : 1; /* [    0],       RW1C,        0x0 */
+            uint16_t XFER_COMPLETE  : 1; /* [    1],       RW1C,        0x0 */
+            uint16_t BLOCK_GAP_EVT  : 1; /* [    2],       RW1C,        0x0 */
+            uint16_t DMA_INT        : 1; /* [    3],       RW1C,        0x0 */
+            uint16_t TX_RDY         : 1; /* [    4],       RW1C,        0x1 */
+            uint16_t RX_RDY         : 1; /* [    5],       RW1C,        0x0 */
+            uint16_t CARD_INS_INT   : 1; /* [    6],       RW1C,        0x0 */
+            uint16_t CARD_REM_INT   : 1; /* [    7],       RW1C,        0x0 */
+            uint16_t CARD_INT       : 1; /* [    8],         RO,        0x0 */
+            uint16_t INT_A          : 1; /* [    9],       RW1C,        0x0 */
+            uint16_t INT_B          : 1; /* [   10],       RW1C,        0x0 */
+            uint16_t INT_C          : 1; /* [   11],       RW1C,        0x0 */
+            uint16_t RETUNING_INT   : 1; /* [   12],       RW1C,        0x0 */
+            uint16_t Reserved_14_13 : 2; /* [14:13],       RSVD,        0x0 */
+            uint16_t ERR_INT        : 1; /* [   15],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_NORMAL_INT_STATUS;
+
+    /* 0x32 : Error Interrupt Status Register */
+    union {
+        struct
+        {
+            uint16_t CMD_TIMEOUT_ERR     : 1; /* [    0],       RW1C,        0x0 */
+            uint16_t CMD_CRC_ERR         : 1; /* [    1],       RW1C,        0x0 */
+            uint16_t CMD_END_BIT_ERR     : 1; /* [    2],       RW1C,        0x0 */
+            uint16_t CMD_INDEX_ERR       : 1; /* [    3],       RW1C,        0x0 */
+            uint16_t DATA_TIMEOUT_ERR    : 1; /* [    4],       RW1C,        0x0 */
+            uint16_t RD_DATA_CRC_ERR     : 1; /* [    5],       RW1C,        0x0 */
+            uint16_t RD_DATA_END_BIT_ERR : 1; /* [    6],       RW1C,        0x0 */
+            uint16_t CUR_LIMIT_ERR       : 1; /* [    7],       RW1C,        0x0 */
+            uint16_t AUTO_CMD12_ERR      : 1; /* [    8],       RW1C,        0x0 */
+            uint16_t ADMA_ERR            : 1; /* [    9],       RW1C,        0x0 */
+            uint16_t TUNE_ERR            : 1; /* [   10],       RW1C,        0x0 */
+            uint16_t Reserved_11         : 1; /* [   11],       RSVD,        0x0 */
+            uint16_t SPI_ERR             : 1; /* [   12],       RW1C,        0x0 */
+            uint16_t AXI_RESP_ERR        : 1; /* [   13],       RW1C,        0x0 */
+            uint16_t CPL_TIMEOUT_ERR     : 1; /* [   14],       RW1C,        0x0 */
+            uint16_t CRC_STATUS_ERR      : 1; /* [   15],       RW1C,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ERROR_INT_STATUS;
+
+    /* 0x34 : Normal Interrupt Status Enable Register */
+    union {
+        struct
+        {
+            uint16_t CMD_COMPLETE_EN  : 1; /* [    0],         RW,        0x0 */
+            uint16_t XFER_COMPLETE_EN : 1; /* [    1],         RW,        0x0 */
+            uint16_t BLOCK_GAP_EVT_EN : 1; /* [    2],         RW,        0x0 */
+            uint16_t DMA_INT_EN       : 1; /* [    3],         RW,        0x0 */
+            uint16_t TX_RDY_EN        : 1; /* [    4],         RW,        0x0 */
+            uint16_t RD_RDY_EN        : 1; /* [    5],         RW,        0x0 */
+            uint16_t CARD_INS_EN      : 1; /* [    6],         RW,        0x0 */
+            uint16_t CARD_REM_EN      : 1; /* [    7],         RW,        0x0 */
+            uint16_t CARD_INT_EN      : 1; /* [    8],         RW,        0x0 */
+            uint16_t INT_A_INT_EN     : 1; /* [    9],         RW,        0x0 */
+            uint16_t INT_B_INT_EN     : 1; /* [   10],         RW,        0x0 */
+            uint16_t INT_C_INT_EN     : 1; /* [   11],         RW,        0x0 */
+            uint16_t RETUNE_INT_EN    : 1; /* [   12],         RW,        0x0 */
+            uint16_t Reserved_15_13   : 3; /* [15:13],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_NORMAL_INT_STATUS_EN;
+
+    /* 0x36 : Error Interrupt Status Enable Register */
+    union {
+        struct
+        {
+            uint16_t CMD_TIMEOUT_ERR_EN     : 1; /* [    0],         RW,        0x0 */
+            uint16_t CMD_CRC_ERR_EN         : 1; /* [    1],         RW,        0x0 */
+            uint16_t CMD_END_BIT_ERR_EN     : 1; /* [    2],         RW,        0x0 */
+            uint16_t CMD_INDEX_ERR_EN       : 1; /* [    3],         RW,        0x0 */
+            uint16_t DATA_TIMEOUT_ERR_EN    : 1; /* [    4],         RW,        0x0 */
+            uint16_t RD_DATA_CRC_ERR_EN     : 1; /* [    5],         RW,        0x0 */
+            uint16_t RD_DATA_END_BIT_ERR_EN : 1; /* [    6],         RW,        0x0 */
+            uint16_t CUR_LIM_ERR_EN         : 1; /* [    7],         RW,        0x0 */
+            uint16_t AUTO_CMD12_ERR_EN      : 1; /* [    8],         RW,        0x0 */
+            uint16_t ADMA_ERR_EN            : 1; /* [    9],         RW,        0x0 */
+            uint16_t TUNING_ERR_EN          : 1; /* [   10],         RW,        0x0 */
+            uint16_t Reserved_11            : 1; /* [   11],       RSVD,        0x0 */
+            uint16_t SPI_ERR_EN             : 1; /* [   12],         RW,        0x0 */
+            uint16_t AXI_RESP_ERR_EN        : 1; /* [   13],         RW,        0x0 */
+            uint16_t CPL_TIMEOUT_ERR_EN     : 1; /* [   14],         RW,        0x0 */
+            uint16_t CRC_STATUS_ERR_EN      : 1; /* [   15],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ERROR_INT_STATUS_EN;
+
+    /* 0x38 : Normal Interrupt Status Interrupt Enable Register */
+    union {
+        struct
+        {
+            uint16_t CMD_COMPLETE_INT_EN  : 1; /* [    0],         RW,        0x0 */
+            uint16_t XFER_COMPLETE_INT_EN : 1; /* [    1],         RW,        0x0 */
+            uint16_t BLOCK_GAP_EVT_INT_EN : 1; /* [    2],         RW,        0x0 */
+            uint16_t DMA_INT_INT_EN       : 1; /* [    3],         RW,        0x0 */
+            uint16_t TX_RDY_INT_EN        : 1; /* [    4],         RW,        0x0 */
+            uint16_t RX_RDY_INT_EN        : 1; /* [    5],         RW,        0x0 */
+            uint16_t CARD_INS_INT_EN      : 1; /* [    6],         RW,        0x0 */
+            uint16_t CARD_REM_INT_EN      : 1; /* [    7],         RW,        0x0 */
+            uint16_t CARD_INT_INT_EN      : 1; /* [    8],         RW,        0x0 */
+            uint16_t INT_A_INT_INT_EN     : 1; /* [    9],         RW,        0x0 */
+            uint16_t INT_B_INT_INT_EN     : 1; /* [   10],         RW,        0x0 */
+            uint16_t INT_C_INT_INT_EN     : 1; /* [   11],         RW,        0x0 */
+            uint16_t RETUNE_INT_INT_EN    : 1; /* [   12],         RW,        0x0 */
+            uint16_t Reserved_15_13       : 3; /* [15:13],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_NORMAL_INT_STATUS_INT_EN;
+
+    /* 0x3A : Error Interrupt Status Interrupt Enable Register */
+    union {
+        struct
+        {
+            uint16_t CMD_TIMEOUT_ERR_INT_EN     : 1; /* [    0],         RW,        0x0 */
+            uint16_t CMD_CRC_ERR_INT_EN         : 1; /* [    1],         RW,        0x0 */
+            uint16_t CMD_END_BIT_ERR_INT_EN     : 1; /* [    2],         RW,        0x0 */
+            uint16_t CMD_INDEX_ERR_INT_EN       : 1; /* [    3],         RW,        0x0 */
+            uint16_t DATA_TIMEOUT_ERR_INT_EN    : 1; /* [    4],         RW,        0x0 */
+            uint16_t RD_DATA_CRC_ERR_INT_EN     : 1; /* [    5],         RW,        0x0 */
+            uint16_t RD_DATA_END_BIT_ERR_INT_EN : 1; /* [    6],         RW,        0x0 */
+            uint16_t CUR_LIM_ERR_INT_EN         : 1; /* [    7],         RW,        0x0 */
+            uint16_t AUTO_CMD12_ERR_INT_EN      : 1; /* [    8],         RW,        0x0 */
+            uint16_t ADMA_ERR_INT_EN            : 1; /* [    9],         RW,        0x0 */
+            uint16_t TUNE_ERR_INT_EN            : 1; /* [   10],         RW,        0x0 */
+            uint16_t Reserved_11                : 1; /* [   11],       RSVD,        0x0 */
+            uint16_t SPI_ERR_INT_EN             : 1; /* [   12],         RW,        0x0 */
+            uint16_t AXI_RESP_ERR_INT_EN        : 1; /* [   13],         RW,        0x0 */
+            uint16_t CPL_TIMEOUT_ERR_INT_EN     : 1; /* [   14],         RW,        0x0 */
+            uint16_t CRC_STATUS_ERR_INT_EN      : 1; /* [   15],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ERROR_INT_STATUS_INT_EN;
+
+    /* 0x3C : Auto CMD12 Error Status Register */
+    union {
+        struct
+        {
+            uint16_t AUTO_CMD12_NOT_EXE   : 1; /* [    0],       RW1C,        0x0 */
+            uint16_t AUTO_CMD_TIMEOUT_ERR : 1; /* [    1],       RW1C,        0x0 */
+            uint16_t AUTO_CMD_CRC_ERR     : 1; /* [    2],       RW1C,        0x0 */
+            uint16_t AUTO_CMD_END_BIT_ERR : 1; /* [    3],       RW1C,        0x0 */
+            uint16_t AUTO_CMD_INDEX_ERR   : 1; /* [    4],       RW1C,        0x0 */
+            uint16_t Reserved_6_5         : 2; /* [ 6: 5],       RSVD,        0x0 */
+            uint16_t CMD_NOT_ISSUED       : 1; /* [    7],        ROC,        0x0 */
+            uint16_t Reserved_15_8        : 8; /* [15: 8],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_AUTO_CMD12_ERROR_STATUS;
+
+    /* 0x3e : Host Control 2 Register */
+    union {
+        struct
+        {
+            uint16_t UHS_MODE_SEL     : 3; /* [ 2: 0],         RW,        0x0 */
+            uint16_t SDH_V18_EN       : 1; /* [    3],         RW,        0x0 */
+            uint16_t DRV_STRENGTH_SEL : 2; /* [ 5: 4],         RW,        0x0 */
+            uint16_t EXE_TUNING       : 1; /* [    6],       RWAC,        0x0 */
+            uint16_t SAMPLING_CLK_SEL : 1; /* [    7],         RW,        0x0 */
+            uint16_t Reserved_13_8    : 6; /* [13: 8],       RSVD,        0x0 */
+            uint16_t ASYNC_INT_EN     : 1; /* [   14],         RW,        0x1 */
+            uint16_t PRE_VAL_EN       : 1; /* [   15],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } HOST_CTRL_2;
+
+    /* 0x40 : Capabilities Register 1 */
+    union {
+        struct
+        {
+            uint16_t TIMEOUT_FREQ : 6; /* [ 5: 0],         RO,       0x00 */
+            uint16_t Reserved_6   : 1; /* [    6],       RSVD,        0x0 */
+            uint16_t TIMEOUT_UNIT : 1; /* [    7],         RO,        0x1 */
+            uint16_t BASE_FREQ    : 8; /* [15: 8],         RO,       0x00 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CAPABILITIES_1;
+
+    /* 0x42 : Capabilities Register 2 */
+    union {
+        struct
+        {
+            uint16_t MAX_BLK_LEN           : 2; /* [ 1: 0],         RO,        0x0 */
+            uint16_t EX_DATA_WIDTH_SUPPORT : 1; /* [    2],         RO,        0x1 */
+            uint16_t ADMA2_SUPPORT         : 1; /* [    3],         RO,        0x1 */
+            uint16_t ADMA1_SUPPORT         : 1; /* [    4],         RO,        0x1 */
+            uint16_t HI_SPEED_SUPPORT      : 1; /* [    5],         RO,        0x1 */
+            uint16_t SDMA_SUPPORT          : 1; /* [    6],         RO,        0x1 */
+            uint16_t SUS_RES_SUPPORT       : 1; /* [    7],         RO,        0x1 */
+            uint16_t VLG_33_SUPPORT        : 1; /* [    8],         RO,        0x1 */
+            uint16_t VLG_30_SUPPORT        : 1; /* [    9],         RO,        0x0 */
+            uint16_t VLG_18_SUPPORT        : 1; /* [   10],         RO,        0x1 */
+            uint16_t Reserved_11           : 1; /* [   11],       RSVD,        0x0 */
+            uint16_t SYS_BUS_64_SUPPORT    : 1; /* [   12],         RO,        0x0 */
+            uint16_t ASYNC_INT_SUPPORT     : 1; /* [   13],         RO,        0x1 */
+            uint16_t CFG_SLOT_TYPE         : 2; /* [15:14],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CAPABILITIES_2;
+
+    /* 0x44 : Capabilities Register 3 */
+    union {
+        struct
+        {
+            uint16_t SDR50_SUPPORT  : 1; /* [    0],         RO,        0x1 */
+            uint16_t SDR104_SUPPORT : 1; /* [    1],         RO,        0x1 */
+            uint16_t DDR50_SUPPORT  : 1; /* [    2],         RO,        0x1 */
+            uint16_t Reserved_3     : 1; /* [    3],       RSVD,        0x0 */
+            uint16_t DRV_TYPE_A     : 1; /* [    4],         RO,        0x1 */
+            uint16_t DRV_TYPE_C     : 1; /* [    5],         RO,        0x1 */
+            uint16_t DRV_TYPE_D     : 1; /* [    6],         RO,        0x1 */
+            uint16_t Reserved_7     : 1; /* [    7],       RSVD,        0x0 */
+            uint16_t TMR_RETUNE     : 4; /* [11: 8],         RO,        0xf */
+            uint16_t Reserved_12    : 1; /* [   12],       RSVD,        0x0 */
+            uint16_t SDR50_TUNE     : 1; /* [   13],         RO,        0x1 */
+            uint16_t RETUNE_MODES   : 2; /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CAPABILITIES_3;
+
+    /* 0x46 : Capabilities Register 4 */
+    union {
+        struct
+        {
+            uint16_t clk_multiplier : 8; /* [ 7: 0],         RO,        0x0 */
+            uint16_t Reserved_15_8  : 8; /* [15: 8],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CAPABILITIES_4;
+
+    /* 0x48 : Maximum Current Register 1 */
+    union {
+        struct
+        {
+            uint16_t MAX_CUR_33 : 8; /* [ 7: 0],         RO,        0x0 */
+            uint16_t MAX_CUR_30 : 8; /* [15: 8],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_MAX_CURRENT_1;
+
+    /* 0x4A : Maximum Current Register 2 */
+    union {
+        struct
+        {
+            uint16_t MAX_CUR_18    : 8; /* [ 7: 0],         RO,        0x0 */
+            uint16_t Reserved_15_8 : 8; /* [15: 8],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_MAX_CURRENT_2;
+
+    /* 0x4C : Maximum Current Register 3 */
+    union {
+        struct
+        {
+            uint16_t Reserved_15_0 : 16; /* [15: 0],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_MAX_CURRENT_3;
+
+    /* 0x4E : Maximum Current Register 4 */
+    union {
+        struct
+        {
+            uint16_t Reserved_15_0 : 16; /* [15: 0],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_MAX_CURRENT_4;
+
+    /* 0x50 : Force Event Auto cmd12 Error Register */
+    union {
+        struct
+        {
+            uint16_t F_ACMD12_NEXE_ERR  : 1; /* [    0],         WO,        0x0 */
+            uint16_t F_ACMD_TO_ERR      : 1; /* [    1],         WO,        0x0 */
+            uint16_t F_ACMD_CRC_ERR     : 1; /* [    2],         WO,        0x0 */
+            uint16_t F__ACMD_EBIT_ERR   : 1; /* [    3],         WO,        0x0 */
+            uint16_t F_ACMD_INDEX_ERR   : 1; /* [    4],         WO,        0x0 */
+            uint16_t Reserved_6_5       : 2; /* [ 6: 5],       RSVD,        0x0 */
+            uint16_t F_ACMD12_ISSUE_ERR : 1; /* [    7],         WO,        0x0 */
+            uint16_t Reserved_15_8      : 8; /* [15: 8],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_FORCE_EVENT_AUTO_CMD12_ERROR;
+
+    /* 0x52 : Force Event for Error Status Register */
+    union {
+        struct
+        {
+            uint16_t F_CMD_TO_ERR      : 1; /* [    0],         WO,        0x0 */
+            uint16_t F_CMD_CRC_ERR     : 1; /* [    1],         WO,        0x0 */
+            uint16_t F_CMD_END_BIT_ERR : 1; /* [    2],         WO,        0x0 */
+            uint16_t F_CMD_INDEX_ERR   : 1; /* [    3],         WO,        0x0 */
+            uint16_t F_DAT_TO_ERR      : 1; /* [    4],         WO,        0x0 */
+            uint16_t F_DAT_CRC_ERR     : 1; /* [    5],         WO,        0x0 */
+            uint16_t F_DAT_END_BIT_ERR : 1; /* [    6],         WO,        0x0 */
+            uint16_t F_CURRENT_ERR     : 1; /* [    7],         WO,        0x0 */
+            uint16_t F_ACMD12_ERR      : 1; /* [    8],         WO,        0x0 */
+            uint16_t F_ADMA_ERR        : 1; /* [    9],         WO,        0x0 */
+            uint16_t Reserved_11_10    : 2; /* [11:10],       RSVD,        0x0 */
+            uint16_t F_SPI_ERR         : 1; /* [   12],         WO,        0x0 */
+            uint16_t F_AXI_RESP_ERR    : 1; /* [   13],         WO,        0x0 */
+            uint16_t F_CPL_TIMEOUT_ERR : 1; /* [   14],         WO,        0x0 */
+            uint16_t F_CRC_STATUS_ERR  : 1; /* [   15],         WO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_FORCE_EVENT_FOR_ERROR_STATUS;
+
+    /* 0x54 : ADMA Error Status Register */
+    union {
+        struct
+        {
+            uint16_t ADMA_STATE    : 2;  /* [ 1: 0],         RW,        0x0 */
+            uint16_t ADMA_LEN_ERR  : 1;  /* [    2],         RW,        0x0 */
+            uint16_t Reserved_15_3 : 13; /* [15: 3],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ADMA_ERROR_STATUS;
+
+    /* 0x56  reserved */
+    uint8_t RESERVED0x56[2];
+
+    /* 0x58 : ADMA System Address Register 1 */
+    union {
+        struct
+        {
+            uint16_t ADMA_SYS_ADDR : 16; /* [15: 0],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ADMA_SYS_ADDR_1;
+
+    /* 0x5A : ADMA System Address Register 2 */
+    union {
+        struct
+        {
+            uint16_t ADMA_SYS_ADDR : 16; /* [15: 0],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ADMA_SYS_ADDR_2;
+
+    /* 0x5C : ADMA System Address Register 3 */
+    union {
+        struct
+        {
+            uint16_t ADMA_SYS_ADDR : 16; /* [15: 0],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ADMA_SYS_ADDR_3;
+
+    /* 0x5E : ADMA System Address Register 4 */
+    union {
+        struct
+        {
+            uint16_t ADMA_SYS_ADDR : 16; /* [15: 0],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_ADMA_SYS_ADDR_4;
+
+    /* 0x60 : Preset Value Register for Initialization */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,      0x100 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_INIT;
+
+    /* 0x62 : Preset Value Register for Default Speed */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,      0x004 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_DS;
+
+    /* 0x64 : Preset Value Register for High Speed */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,      0x002 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_HS;
+
+    /* 0x66 : Preset Value Register for SDR12 */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,      0x004 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_SDR12;
+
+    /* 0x68 : Preset Value Register for SDR25 */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,      0x002 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_SDR25;
+
+    /* 0x6a : Preset Value Register for SDR50 */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,      0x001 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_SDR50;
+
+    /* 0x6c : Preset Value Register for SDR104 */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,        0x0 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_SDR104;
+
+    /* 0x6e : Preset Value Register for DDR50 */
+    union {
+        struct
+        {
+            uint16_t SDCLK_FREQ_SEL_VAL : 10; /* [ 9: 0],         RO,      0x002 */
+            uint16_t CLKGEN_SEL_VAL     : 1;  /* [   10],         RO,        0x0 */
+            uint16_t Reserved_13_11     : 3;  /* [13:11],       RSVD,        0x0 */
+            uint16_t DRV_STRENGTH_VAL   : 2;  /* [15:14],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } PRESET_VALUE_FOR_DDR50;
+
+    /* 0x70  reserved */
+    uint8_t RESERVED0x70[112];
+
+    /* 0xe0 : Shared Bus Control Register */
+    union {
+        struct
+        {
+            uint32_t NUM_CLK_PINS     : 3; /* [ 2: 0],         RO,        0x0 */
+            uint32_t Reserved_3       : 1; /* [    3],       RSVD,        0x0 */
+            uint32_t NUM_INT_PINS     : 2; /* [ 5: 4],         RO,        0x0 */
+            uint32_t Reserved_7_6     : 2; /* [ 7: 6],       RSVD,        0x0 */
+            uint32_t BUS_WIDTH_PRESET : 7; /* [14: 8],         RO,        0x0 */
+            uint32_t Reserved_15      : 1; /* [   15],       RSVD,        0x0 */
+            uint32_t CLK_PIN_SEL      : 3; /* [18:16],         RW,        0x0 */
+            uint32_t Reserved_19      : 1; /* [   19],       RSVD,        0x0 */
+            uint32_t INT_PIN_SEL      : 3; /* [22:20],         RW,        0x0 */
+            uint32_t Reserved_23      : 1; /* [   23],       RSVD,        0x0 */
+            uint32_t BEND_PWR_CTRL    : 7; /* [30:24],         RW,        0x0 */
+            uint32_t Reserved_31      : 1; /* [   31],       RSVD,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } SHARED_BUS_CTRL;
+
+    /* 0xe4  reserved */
+    uint8_t RESERVED0xe4[24];
+
+    /* 0xFC : Slot Interrupt Status Register */
+    union {
+        struct
+        {
+            uint16_t SLOT_INT0     : 1;  /* [    0],         RO,        0x0 */
+            uint16_t SLOT_INT1     : 1;  /* [    1],         RO,        0x0 */
+            uint16_t Reserved_15_2 : 14; /* [15: 2],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_SLOT_INT_STATUS;
+
+    /* 0xFE : Host Control Version Register */
+    union {
+        struct
+        {
+            uint16_t SD_VER     : 8; /* [ 7: 0],         RO,        0x2 */
+            uint16_t VENDOR_VER : 8; /* [15: 8],         RO,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_HOST_CTRL_VER;
+
+    /* 0x100 : SD Extra Parameters Register */
+    union {
+        struct
+        {
+            uint32_t Reserved_0      : 1;  /* [    0],       RSVD,        0x0 */
+            uint32_t Reserved_2_1    : 2;  /* [ 2: 1],       RSVD,        0x0 */
+            uint32_t BOOT_ACK        : 1;  /* [    3],         RW,        0x0 */
+            uint32_t SQU_EMPTY_CHK   : 1;  /* [    4],         RW,        0x0 */
+            uint32_t SQU_FULL_CHK    : 1;  /* [    5],         RW,        0x0 */
+            uint32_t GEN_PAD_CLK_ON  : 1;  /* [    6],       RWAC,        0x0 */
+            uint32_t Reserved_23_7   : 17; /* [23: 7],       RSVD,        0x0 */
+            uint32_t GEN_PAD_CLK_CNT : 8;  /* [31:24],         RW,       0x4a */
+        } BF;
+        uint32_t WORD;
+    } SD_CFG_FIFO_PARAM;
+
+    /* 0x104 : FIFO Parameters Register */
+    union {
+        struct
+        {
+            uint32_t RTC              : 2;  /* [ 1: 0],         RW,        0x1 */
+            uint32_t WTC              : 2;  /* [ 3: 2],         RW,        0x1 */
+            uint32_t FIFO_CLK         : 1;  /* [    4],         RW,        0x0 */
+            uint32_t FIFO_CS          : 1;  /* [    5],         RW,        0x0 */
+            uint32_t PDWN             : 1;  /* [    6],         RW,        0x0 */
+            uint32_t use_dat3         : 1;  /* [    7],         RW,        0x0 */
+            uint32_t CLK_GATE_CTL     : 1;  /* [    8],         RW,        0x0 */
+            uint32_t CLK_GATE_ON      : 1;  /* [    9],         RW,        0x0 */
+            uint32_t Reserved_10      : 1;  /* [   10],       RSVD,        0x0 */
+            uint32_t OVRRD_CLK_OEN    : 1;  /* [   11],         RW,        0x0 */
+            uint32_t FORCE_CLK_ON     : 1;  /* [   12],         RW,        0x0 */
+            uint32_t PDFVSSM          : 1;  /* [   13],         RW,        0x0 */
+            uint32_t PDLVMC           : 1;  /* [   14],         RW,        0x0 */
+            uint32_t Reserved_15      : 1;  /* [   15],       RSVD,        0x0 */
+            uint32_t PRE_GATE_CLK_CNT : 4;  /* [19:16],         RW,        0x7 */
+            uint32_t Reserved_31_20   : 12; /* [31:20],       RSVD,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } SD_FIFO_PARAM;
+
+    /* 0x108 : SPI Mode Register */
+    union {
+        struct
+        {
+            uint16_t SPI_EN         : 1; /* [    0],         RW,        0x0 */
+            uint16_t Reserved_7_1   : 7; /* [ 7: 1],       RSVD,        0x0 */
+            uint16_t SPI_ERR_TOKEN  : 5; /* [12: 8],         RW,        0x0 */
+            uint16_t Reserved_15_13 : 3; /* [15:13],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_SPI_MODE;
+
+    /* 0x10a : Clock and Burst Size Setup Register */
+    union {
+        struct
+        {
+            uint16_t BRST_SIZE       : 2; /* [ 1: 0],         RW,        0x2 */
+            uint16_t DMA_SIZE        : 2; /* [ 3: 2],         RW,        0x3 */
+            uint16_t priority        : 1; /* [    4],         RW,        0x0 */
+            uint16_t AXI_NON_POST_WR : 1; /* [    5],         RW,        0x0 */
+            uint16_t RD_ENDIAN       : 1; /* [    6],         RW,        0x1 */
+            uint16_t WR_ENDIAN       : 1; /* [    7],         RW,        0x1 */
+            uint16_t Reserved_13_8   : 6; /* [13: 8],       RSVD,        0x0 */
+            uint16_t RD_OSTDG        : 1; /* [   14],         RW,        0x0 */
+            uint16_t WR_OSTDG        : 1; /* [   15],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CLOCK_AND_BURST_SIZE_SETUP;
+
+    /* 0x10c : CE-ATA Register 1 */
+    union {
+        struct
+        {
+            uint16_t CPL_TIMEOUT    : 14; /* [13: 0],         RW,     0x3FFF */
+            uint16_t Reserved_15_14 : 2;  /* [15:14],       RSVD,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CE_ATA_1;
+
+    /* 0x10e : CE-ATA Register 2 */
+    union {
+        struct
+        {
+            uint16_t MISC_INT_INT_EN     : 1; /* [    0],         RW,        0x0 */
+            uint16_t MISC_INT_EN         : 1; /* [    1],         RW,        0x0 */
+            uint16_t MISC_INT            : 1; /* [    2],       RW1C,        0x0 */
+            uint16_t Reserved_3          : 1; /* [    3],       RSVD,        0x0 */
+            uint16_t CPL_COMPLETE_INT_EN : 1; /* [    4],         RW,        0x0 */
+            uint16_t CPL_COMPLETE_EN     : 1; /* [    5],         RW,        0x0 */
+            uint16_t CPL_COMPLETE        : 1; /* [    6],       RW1C,        0x0 */
+            uint16_t Reserved_10_7       : 4; /* [10: 7],       RSVD,        0x0 */
+            uint16_t MMC_RESETN          : 1; /* [   11],         RW,        0x1 */
+            uint16_t MMC_CARD            : 1; /* [   12],         RW,        0x0 */
+            uint16_t CEATA_CARD          : 1; /* [   13],         RW,        0x0 */
+            uint16_t SND_CPL             : 1; /* [   14],         RW,        0x0 */
+            uint16_t CHK_CPL             : 1; /* [   15],         RW,        0x0 */
+        } BF;
+        uint16_t SHORT;
+    } SD_CE_ATA_2;
+
+    /* 0x110 : PAD I/O Setup Register */
+    union {
+        struct
+        {
+            uint32_t ASYNC_IO_EN    : 1;  /* [    0],         RW,        0x0 */
+            uint32_t INAND_SEL      : 1;  /* [    1],         RW,        0x1 */
+            uint32_t Reserved_15_2  : 14; /* [15: 2],       RSVD,        0x0 */
+            uint32_t ECO_REG        : 8;  /* [23:16],         RW,        0x0 */
+            uint32_t Reserved_31_24 : 8;  /* [31:24],       RSVD,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } SD_PAD_IO_SETUP;
+
+    /* 0x114 : RX Configuration Register */
+    union {
+        struct
+        {
+            uint32_t SDCLK_SEL0     : 2;  /* [ 1: 0],         RW,        0x0 */
+            uint32_t SDCLK_SEL1     : 2;  /* [ 3: 2],         RW,        0x0 */
+            uint32_t Reserved_7_4   : 4;  /* [ 7: 4],       RSVD,        0x0 */
+            uint32_t SDCLK_DELAY    : 10; /* [17: 8],         RW,        0x0 */
+            uint32_t TUNING_DLY_INC : 10; /* [27:18],         RW,        0x0 */
+            uint32_t Reserved_31_28 : 4;  /* [31:28],       RSVD,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RX_CFG_REG;
+
+    /* 0x118 : TX Configuration Register */
+    union {
+        struct
+        {
+            uint32_t TX_HOLD_DELAY0 : 10; /* [ 9: 0],         RW,       0x70 */
+            uint32_t Reserved_15_10 : 6;  /* [15:10],       RSVD,        0x0 */
+            uint32_t TX_HOLD_DELAY1 : 10; /* [25:16],         RW,       0x29 */
+            uint32_t Reserved_29_26 : 4;  /* [29:26],       RSVD,        0x0 */
+            uint32_t TX_INT_CLK_SEL : 1;  /* [   30],         RW,        0x0 */
+            uint32_t TX_MUX_SEL     : 1;  /* [   31],         RW,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TX_CFG_REG;
+
+    /* 0x11c : TUNING CONFIG Register */
+    union {
+        struct
+        {
+            uint32_t TUNING_TT_CNT  : 8;  /* [ 7: 0],         RW,       0x27 */
+            uint32_t TUNING_WD_CNT  : 6;  /* [13: 8],         RW,       0x0a */
+            uint32_t TUNING_CLK_DLY : 10; /* [23:14],         RO,        0x0 */
+            uint32_t
+                TUNING_SUCCESS_CNT  : 6; /* [29:24],         RO,        0x0 */
+            uint32_t Reserved_31_30 : 2; /* [31:30],       RSVD,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } TUNING_CFG_REG;
+};
+
+typedef volatile struct sdh_reg sdh_reg_t;
+
+#endif /* __SDH_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sf_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sf_ctrl_reg.h
new file mode 100755
index 0000000000..5fcd5ee492
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/include/hardware/sf_ctrl_reg.h
@@ -0,0 +1,3371 @@
+/**
+  ******************************************************************************
+  * @file    sf_ctrl_reg.h
+  * @version V1.0
+  * @date    2021-07-13
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __SF_CTRL_REG_H__
+#define  __SF_CTRL_REG_H__
+
+#include "bl616.h"
+
+/* 0x0 : sf_ctrl_0 */
+#define SF_CTRL_0_OFFSET                                        (0x0)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL                            SF_CTRL_SF_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS                        (2U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN                        (1U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK                        (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __TZC_NSEC_REG_H__
+#define  __TZC_NSEC_REG_H__
+
+#include "bl616.h"
+
+/* 0x40 : tzc_rom_tzsrg_ctrl */
+#define TZC_NSEC_TZC_ROM_TZSRG_CTRL_OFFSET                      (0x40)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN                         TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_POS                     (0U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_LEN                     (4U)
+#define TZC_NSEC_TZC_ROM_TZSRG_R0_ID_EN_MSK                     (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef  __TZC_SEC_REG_H__
+#define  __TZC_SEC_REG_H__
+
+#include "bl616.h"
+
+/* 0x40 : tzc_rom_tzsrg_ctrl */
+#define TZC_SEC_TZC_ROM_TZSRG_CTRL_OFFSET                       (0x40)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN                          TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_POS                      (0U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_LEN                      (4U)
+#define TZC_SEC_TZC_ROM_TZSRG_R0_ID_EN_MSK                      (((1U<
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616_aon.h"
+#include "bl616_ef_cfg.h"
+#include "bl616_ef_ctrl.h"
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Private_Macros
+ *  @{
+ */
+#define AON_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group AON_Private_Macros */
+
+/** @defgroup  AON_Private_Types
+ *  @{
+ */
+
+/*@} end of group AON_Private_Types */
+
+/** @defgroup  AON_Private_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Private_Variables */
+
+/** @defgroup  AON_Global_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Global_Variables */
+
+/** @defgroup  AON_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group AON_Private_Fun_Declaration */
+
+/** @defgroup  AON_Private_Functions
+ *  @{
+ */
+
+/*@} end of group AON_Private_Functions */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Power on Main band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    arch_delay_us(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off Main band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power OFF */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* Polling for ready */
+    do {
+        arch_delay_us(10);
+        timeOut++;
+        tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
+
+    if (timeOut >= 120) {
+        return TIMEOUT;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set XTAL cap code
+ *
+ * @param  capIn: Cap code in
+ * @param  capOut: Cap code out
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    arch_delay_us(100);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get XTAL cap code
+ *
+ * @param  None
+ *
+ * @return Cap code
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    arch_delay_us(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    arch_delay_us(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power on */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    arch_delay_us(90);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power off */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  LDO15_RF Output Float
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Output_Float_LDO15_RF(void)
+{
+    uint32_t tmpVal=0;
+
+    /* ldo15rf pulldown select by aon */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* ldo15rf float output */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief   LDO15_RF Pulldown Output to Groud
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Output_Pulldown_LDO15_RF(void)
+{
+    uint32_t tmpVal=0;
+
+    /* ldo15rf pulldown select by aon */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* ldo15rf pulldown output to ground */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  LDO15_RF Output Pulldown Controlled by PD Signal
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Output_LDO15_RF_Ctrl_by_Pd(void)
+{
+    uint32_t tmpVal=0;
+
+    /* output ldo15rf pulldown select by pd signal */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_LDO15RF_PULLDOWN_SEL_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+
+
+/****************************************************************************/ /**
+ * @brief  power on source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power on sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    arch_delay_us(10);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power off source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power on mic bias
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_MicBias(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power on sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+
+    arch_delay_us(10);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power off mic bias
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_MicBias(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_GPADC_REG_CMD);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_GPADC_MICBIAS_EN);
+    BL_WR_REG(AON_BASE, AON_GPADC_REG_CMD, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off the power can be shut down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* gating Clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpVal = tmpVal & (~(1 << 6));
+    tmpVal = tmpVal & (~(1 << 7));
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    arch_delay_us(20);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    arch_delay_us(60);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    arch_delay_us(20);
+
+    /* power on wb */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_WB_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    /* ungating Clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpVal = tmpVal | ((1 << 6));
+    tmpVal = tmpVal | ((1 << 7));
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  trim DCDC dis
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcDis(void)
+{
+    Efuse_Ana_DcdcDis_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_DcdcDis_Trim(&trim);
+    if (trim.dcdcDisAonEn) {
+        if (trim.dcdcDisAonParity == EF_Ctrl_Get_Trim_Parity(trim.dcdcDisAon, 1)) {
+            tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_DIS_AON, trim.dcdcDisAon);
+            BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  trim DCDC vout sel
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutSel(void)
+{
+    Efuse_Ana_DcdcVoutSel_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_DcdcVoutSel_Trim(&trim);
+    if (trim.dcdcVoutSelAonEn) {
+        if (trim.dcdcVoutSelAonParity == EF_Ctrl_Get_Trim_Parity(trim.dcdcVoutSelAon, 5)) {
+            tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_VOUT_SEL_AON, trim.dcdcVoutSelAon);
+            BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  trim DCDC vout trim
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Trim_DcdcVoutTrim(void)
+{
+    Efuse_Ana_DcdcVoutTrim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_DcdcVoutTrim_Trim(&trim);
+    if (trim.dcdcVoutTrimAonEn) {
+        if (trim.dcdcVoutTrimAonParity == EF_Ctrl_Get_Trim_Parity(trim.dcdcVoutTrimAon, 4)) {
+            tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_2);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_VOUT_TRIM_AON, trim.dcdcVoutTrimAon);
+            BL_WR_REG(AON_BASE, AON_DCDC_TOP_2, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  trim LDO11SOC vout
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Trim_Ldo11socVoutTrim(void)
+{
+    Efuse_Ana_Ldo11socVoutTrim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_Ldo11socVoutTrim_Trim(&trim);
+    if (trim.ldo11socVoutTrimAonEn) {
+        if (trim.ldo11socVoutTrimAonTrim == EF_Ctrl_Get_Trim_Parity(trim.ldo11socVoutTrimAon, 4)) {
+            tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_VOUT_TRIM_AON, trim.ldo11socVoutTrimAon);
+            BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  trim USB20 rcal code
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+BL_Err_Type ATTR_TCM_SECTION AON_Trim_Usb20RcalCode(void)
+{
+    Efuse_Ana_Usb20RcalCode_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_Usb20RcalCode_Trim(&trim);
+    if (trim.usb20RcalCodeAonEn) {
+        if (trim.usb20RcalCodeAonParity == EF_Ctrl_Get_Trim_Parity(trim.usb20RcalCodeAon, 6)) {
+            tmpVal = BL_RD_REG(AON_BASE, AON_PSW_MISC);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_USB20_RCAL_CODE_AON, trim.usb20RcalCodeAon);
+            BL_WR_REG(AON_BASE, AON_PSW_MISC, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_clock.c
new file mode 100755
index 0000000000..60e1e09384
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_clock.c
@@ -0,0 +1,1424 @@
+/**
+  ******************************************************************************
+  * @file    bl616_clock.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616_clock.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Private_Macros
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Macros */
+
+/** @defgroup  CLOCK_Private_Types
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Types */
+
+/** @defgroup  CLOCK_Private_Variables
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Variables */
+
+/** @defgroup  CLOCK_Global_Variables
+ *  @{
+ */
+
+/*@} end of group CLOCK_Global_Variables */
+
+/** @defgroup  CLOCK_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Fun_Declaration */
+
+/** @defgroup  CLOCK_Private_Functions
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Functions */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut)
+{
+    return pllOut;
+}
+
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clockAupllType)
+{
+    uint8_t xtalType = 0;
+    uint32_t tmpVal = 0;
+    uint32_t vcoFreq = 0;
+    uint32_t calculationDiv = (1 << 11);
+
+    tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG6), CCI_AUPLL_SDMIN);
+
+    if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+        switch (xtalType) {
+            /* Calculation method:xtal_freq * 1000 * aupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */
+            case GLB_XTAL_NONE:
+                return (0);
+            case GLB_XTAL_24M:
+                /* 491519500;451576000;399996000;3840000000 */
+                vcoFreq = 24 * 1000 * tmpVal / calculationDiv * (1000 / 2);
+                break;
+            case GLB_XTAL_32M:
+                /* 491519500;451578000;400000000;3840000000 */
+                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+                break;
+            case GLB_XTAL_38P4M:
+                /* 491517000;451579500;399998250;3840000000 */
+                vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
+                break;
+            case GLB_XTAL_40M:
+                /* 491518500;451577000;400000000;383999000 */
+                vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+                break;
+            case GLB_XTAL_26M:
+                /* 491518000;451578500;399997500;383995000 */
+                vcoFreq = 26 * 1000 * tmpVal / calculationDiv * (1000 / 2);
+                break;
+            case GLB_XTAL_RC32M:
+                /* 491519500;451578000;400000000;3840000000 */
+                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
+                break;
+            default:
+                return (0);
+        }
+    } else {
+        return (0);
+    }
+
+    if ((vcoFreq >= 491000000) && (vcoFreq <= 492000000)) {
+        /* vcoFreq:491517000~491519500 */
+        vcoFreq = 491520000;
+    } else if ((vcoFreq >= 451000000) && (vcoFreq <= 452000000)) {
+        /* vcoFreq:451577000~451579500 */
+        vcoFreq = 451580000;
+    } else if ((vcoFreq >= 399000000) && (vcoFreq <= 401000000)) {
+        /* vcoFreq:451577000~451579500 */
+        vcoFreq = 400000000;
+    } else if ((vcoFreq >= 383000000) && (vcoFreq <= 385000000)) {
+        /* vcoFreq:383995000~3840000000 */
+        vcoFreq = 384000000;
+    } else {
+        return (0);
+    }
+
+    switch (clockAupllType) {
+        case CLOCK_AUPLL_DIV1:
+            return (vcoFreq);
+        case CLOCK_AUPLL_DIV2:
+            return (vcoFreq / 2);
+        case CLOCK_AUPLL_DIV2P5:
+            return (vcoFreq * 2 / 5);
+        case CLOCK_AUPLL_DIV3:
+            return (vcoFreq / 3);
+        case CLOCK_AUPLL_DIV4:
+            return (vcoFreq / 4);
+        case CLOCK_AUPLL_DIV5:
+            return (vcoFreq / 5);
+        case CLOCK_AUPLL_DIV6:
+            return (vcoFreq / 6);
+        case CLOCK_AUPLL_DIV10:
+            return (vcoFreq / 10);
+        case CLOCK_AUPLL_DIV15:
+            return (vcoFreq / 15);
+        default:
+            return 0;
+    }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output()
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG1), CCI_AUPLL_POSTDIV);
+
+    return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1) / tmpVal;
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
+{
+    uint8_t xtalType = 0;
+
+    if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
+        switch (xtalType) {
+            case GLB_XTAL_NONE:
+                return 0;
+            case GLB_XTAL_24M:
+                return 24 * 1000 * 1000;
+            case GLB_XTAL_32M:
+                return 32 * 1000 * 1000;
+            case GLB_XTAL_38P4M:
+                return 38.4 * 1000 * 1000;
+            case GLB_XTAL_40M:
+                return 40 * 1000 * 1000;
+            case GLB_XTAL_26M:
+                return 26 * 1000 * 1000;
+            case GLB_XTAL_RC32M:
+                return 32 * 1000 * 1000;
+            default:
+                return 0;
+        }
+    } else {
+        return 40 * 1000 * 1000;
+    }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* rc32m */
+        return (32 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* xtal */
+        return Clock_Xtal_Output();
+    } else {
+        return 0;
+    }
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
+{
+    uint32_t tmpVal;
+    uint32_t div = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV);
+
+    if (sel == 0) {
+        /* src32k */
+        return (32 * 1000);
+    } else if (sel == 1) {
+        /* xtal 32K */
+        return (32 * 1000);
+    } else {
+        return Clock_Xtal_Output() / (div + 1);
+    }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* wifi pll 160m */
+        return Clock_Get_WIFI_PLL_Output(160 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* aupll div3 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV3);
+    } else if (sel == 2) {
+        /* aupll div2 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);
+    } else if (sel == 3) {
+        //* aupll div2p5 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2P5);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* wifi pll 80m */
+        return Clock_Get_WIFI_PLL_Output(80 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* aupll div5 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
+    } else if (sel == 2) {
+        /* aupll div6 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV6);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* aupll div2 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV2);
+    } else if (sel == 1) {
+        /* aupll div1 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
+    } else if (sel == 2) {
+        /* wifi pll 240m */
+        return Clock_Get_WIFI_PLL_Output(240 * 1000 * 1000);
+    } else if (sel == 3) {
+        /* wifi pll 320m */
+        return Clock_Get_WIFI_PLL_Output(320 * 1000 * 1000);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    return (tmpVal & 0x1);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    return ((tmpVal >> 1) & 0x1);
+}
+
+static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
+{
+    uint32_t tmpVal;
+
+    if (sel == 0) {
+        /* xclk */
+        return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+    } else if (sel == 1) {
+        /* pll */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+        sel = BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL);
+        return Clock_MCU_Clk_Mux_Output(sel);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
+}
+
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
+}
+
+/****************************************************************************/ /**
+ * @brief  Get System Clock
+ *
+ * @param  type: System clock type
+ *
+ * @return System clock value
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type)
+{
+    uint32_t clock = 0;
+    uint32_t div = 0;
+
+    switch (type) {
+        case BL_SYSTEM_CLOCK_MCU_ROOT_CLK:
+            /*!< mcu root clock */
+            return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+
+        case BL_SYSTEM_CLOCK_MCU_CLK:
+            /*!< mcu fast clock/cpu clock */
+            clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+            div = Clock_Get_MCU_HClk_Div_Val();
+            return clock / (div + 1);
+
+        case BL_SYSTEM_CLOCK_MCU_PBCLK:
+            /*!< mcu peri bus clock */
+            clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+            div = Clock_Get_Peri_BClk_Div_Val();
+            return clock / (div + 1);
+
+        case BL_SYSTEM_CLOCK_F32K:
+            /*!< f32k clock */
+            return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+
+        case BL_SYSTEM_CLOCK_XCLK:
+            /*!< xclk:rc32M or xtal */
+            return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+
+        case BL_SYSTEM_CLOCK_XTAL:
+            /*!< xtal clock */
+            return Clock_Xtal_Output();
+
+        default:
+            return 0;
+    }
+}
+
+static inline uint32_t Clock_PARAMB_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* wifi pll 320m */
+        return Clock_Get_WIFI_PLL_Output(320 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* aupll div1 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t Clock_Get_PSRAMB_Clk_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_PSRAMB_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL);
+}
+
+uint32_t Clock_Get_PSRAMB_Clk(void)
+{
+    uint32_t div = 0;
+
+    div = Clock_Get_PSRAMB_Clk_Div_Val();
+
+    return Clock_PARAMB_Clk_Mux_Output(Clock_Get_PSRAMB_Clk_Sel_Val()) / (div + 1);
+}
+
+static inline uint32_t Clock_ISP_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* wifi pll 80m */
+        return Clock_Get_WIFI_PLL_Output(80 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* aupll div5 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
+    } else if (sel == 2 || sel == 3) {
+        /* aupll div6 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV6);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t Clock_Get_ISP_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_ISP_MUXPLL_80M_SEL);
+}
+
+uint32_t Clock_Get_ISP_Clk(void)
+{
+    return Clock_ISP_Clk_Mux_Output(Clock_Get_ISP_Clk_Sel_Val());
+}
+
+static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* mcu bclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+    } else if (sel == 1) {
+        /* mux 160Mkz */
+        return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+
+    return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL));
+}
+
+static inline uint8_t Clock_Get_UART_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
+}
+
+static inline uint32_t Clock_PKA_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* mcu pbclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+    } else if (sel == 1) {
+        /* mux 160m */
+        return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t Clock_Get_PKA_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL);
+}
+
+static inline uint32_t Clock_IR_Clk_Mux_Output(void)
+{
+    /* xclk */
+    return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+}
+
+static inline uint8_t Clock_Get_IR_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
+}
+
+static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* wifi pll 120m */
+        return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* xtal */
+        return Clock_Xtal_Output();
+    } else if (sel == 2) {
+        /* wifi pll 120m */
+        return Clock_Get_WIFI_PLL_Output(120 * 1000 * 1000);
+    } else {
+        /* aupll div5 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
+    }
+}
+
+static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* sf sel2 */
+        return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val());
+    } else if (sel == 1) {
+        /* mux 80m */
+        return Clock_80M_Clk_Mux_Output(Clock_Get_Muxpll_80M_Sel_Val());
+    } else if (sel == 2) {
+        /* mcu pbclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+    } else {
+        /* wifi 96m */
+        return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
+    }
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SF_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);
+}
+
+static inline uint32_t Clock_SPI_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* mux 160Mkz */
+        return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_SPI_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SPI_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
+}
+
+static inline uint32_t Clock_PEC_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* mux 160Mkz */
+        return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_PEC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_PEC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV);
+}
+
+static inline uint32_t Clock_DBI_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* mux 160Mkz */
+        return Clock_160M_Clk_Mux_Output(Clock_Get_Muxpll_160M_Sel_Val());
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_DBI_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_DBI_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_DIV);
+}
+
+static inline uint32_t Clock_I2C_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* mcu pblck */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+    } else if (sel == 1) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t Clock_Get_I2C_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_I2C_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* audio pll clk */
+        return Clock_Get_Audio_PLL_Output();
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_GPADC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
+{
+    uint32_t div = 0;
+
+    if (sel == 1) {
+        /* f32k bclk */
+        return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+    } else {
+        div = Clock_Get_GPADC_Div_Val();
+        return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1);
+    }
+}
+
+static inline uint32_t Clock_I2S_Clk_Mux_Output(void)
+{
+    /* audio pll clk */
+    return Clock_Get_Audio_PLL_Output();
+}
+
+static inline uint8_t Clock_Get_I2S_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV);
+}
+
+static inline uint32_t Clock_ADC_Clk_Mux_Output(void)
+{
+    /* audio pll clk */
+    return Clock_Get_Audio_PLL_Output();
+}
+
+static inline uint8_t Clock_Get_ADC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_SOLO_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS);
+}
+
+static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* wifi pll 32m */
+        return Clock_Get_WIFI_PLL_Output(32 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else {
+        /* audio pll clk */
+        return Clock_Get_Audio_PLL_Output();
+    }
+}
+
+static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
+}
+
+static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
+}
+
+static inline uint32_t Clock_SDH_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* wifi pll 96m */
+        return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
+    } else {
+        /* aupll div5 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
+    }
+}
+
+static inline uint8_t Clock_Get_SDH_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SDH_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV);
+}
+
+static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else if (sel == 1) {
+        /* wifi pull 96m */
+        return Clock_Get_WIFI_PLL_Output(96 * 1000 * 1000);
+    } else if (sel == 2 || sel == 3) {
+        /* aupll div5 clk */
+        return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV5);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
+}
+
+static inline uint8_t Clock_Get_CAM_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
+}
+
+/****************************************************************************/ /**
+
+ * @brief  Get Audio ADC Clock
+ *
+ * @return Audio ADC clock value
+ *
+*******************************************************************************/
+uint32_t Clock_Audio_ADC_Clock_Get(void)
+{
+    uint32_t clock = 0;
+    uint32_t div = 0;
+
+    clock = Clock_ADC_Clk_Mux_Output();
+    div = Clock_Get_ADC_Div_Val();
+
+    return clock / (div + 1);
+}
+
+/****************************************************************************/ /**
+
+ * @brief  Get Peripheral1 Clock
+ *
+ * @param  type: Peripheral1 clock type
+ *
+ * @return Peripheral1 clock value
+ *
+*******************************************************************************/
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
+{
+    uint32_t clock = 0;
+    uint32_t div = 0;
+
+    switch (type) {
+        /*!< uart0 clock */
+        case BL_PERIPHERAL_CLOCK_UART0:
+            ATTR_FALLTHROUGH();
+
+        /*!< uart1 clock */
+        case BL_PERIPHERAL_CLOCK_UART1:
+            ATTR_FALLTHROUGH();
+
+        /*!< uart2 clock */
+        case BL_PERIPHERAL_CLOCK_UART2:
+            clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val());
+            div = Clock_Get_UART_Div_Val();
+            return clock / (div + 1);
+
+        /*!< spi clock */
+        case BL_PERIPHERAL_CLOCK_SPI:
+            clock = Clock_SPI_Clk_Mux_Output(Clock_Get_SPI_Clk_Sel_Val());
+            div = Clock_Get_SPI_Div_Val();
+            return clock / (div + 1);
+
+        /*!< pec clock */
+        case BL_PERIPHERAL_CLOCK_PEC:
+            clock = Clock_PEC_Clk_Mux_Output(Clock_Get_PEC_Clk_Sel_Val());
+            div = Clock_Get_PEC_Div_Val();
+            return clock / (div + 1);
+
+        /*!< dbi clock */
+        case BL_PERIPHERAL_CLOCK_DBI:
+            clock = Clock_DBI_Clk_Mux_Output(Clock_Get_DBI_Clk_Sel_Val());
+            div = Clock_Get_DBI_Div_Val();
+            return clock / (div + 1);
+
+        /*!< i2c0 clock */
+        case BL_PERIPHERAL_CLOCK_I2C0:
+            ATTR_FALLTHROUGH();
+
+        /*!< i2c1 clock */
+        case BL_PERIPHERAL_CLOCK_I2C1:
+            clock = Clock_I2C_Clk_Mux_Output(Clock_Get_I2C_Clk_Sel_Val());
+            div = Clock_Get_I2C_Div_Val();
+            return clock / (div + 1);
+
+        /*!< PSRAMB clock */
+        case BL_PERIPHERAL_CLOCK_PSRAMB:
+            return Clock_Get_PSRAMB_Clk();
+
+        /*!< emi clock */
+        case BL_PERIPHERAL_CLOCK_EMI:
+            /* mcu pblck */
+            return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_PBCLK);
+
+        /*!< isp clock */
+        case BL_PERIPHERAL_CLOCK_ISP:
+            return Clock_Get_ISP_Clk();
+
+        /*!< FLASH clock */
+        case BL_PERIPHERAL_CLOCK_FLASH:
+            clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val());
+            div = Clock_Get_SF_Div_Val();
+            return clock / (div + 1);
+
+        /*!< I2S clock */
+        case BL_PERIPHERAL_CLOCK_I2S:
+            clock = Clock_I2S_Clk_Mux_Output();
+            div = Clock_Get_I2S_Div_Val();
+            return clock / (div + 1);
+
+        /*!< IR clock */
+        case BL_PERIPHERAL_CLOCK_IR:
+            clock = Clock_IR_Clk_Mux_Output();
+            div = Clock_Get_IR_Div_Val();
+            return clock / (div + 1);
+
+        /*!< ADC clock */
+        case BL_PERIPHERAL_CLOCK_ADC:
+            return Clock_Audio_ADC_Clock_Get();
+
+        /*!< GPADC clock */
+        case BL_PERIPHERAL_CLOCK_GPADC:
+            return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val());
+
+        /*!< GPDAC clock */
+        case BL_PERIPHERAL_CLOCK_GPDAC:
+            clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val());
+            div = Clock_Get_GPDAC_Div_Val();
+            return clock / (div + 1);
+
+        /*!< CAM clock */
+        case BL_PERIPHERAL_CLOCK_CAM:
+            clock = Clock_CAM_Clk_Mux_Output(Clock_Get_CAM_Clk_Sel_Val());
+            div = Clock_Get_CAM_Div_Val();
+            return clock / (div + 1);
+
+        /*!< SDH clock */
+        case BL_PERIPHERAL_CLOCK_SDH:
+            clock = Clock_SDH_Clk_Mux_Output(Clock_Get_SDH_Clk_Sel_Val());
+            div = Clock_Get_SDH_Div_Val();
+            return clock / (div + 1);
+
+        /*!< PKA clock */
+        case BL_PERIPHERAL_CLOCK_PKA:
+            return Clock_PKA_Clk_Mux_Output(Clock_Get_PKA_Clk_Sel_Val());
+
+        default:
+            return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  get system core clock
+ *
+ * @param  None
+ *
+ * @return system core clock value
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION SystemCoreClockGet(void)
+{
+    uint32_t clockVal = 0;
+
+    switch (GLB_Get_Core_Type()) {
+        case GLB_CORE_ID_M0:
+            clockVal = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+            break;
+        default:
+            clockVal = 0;
+            break;
+    }
+    clockVal = clockVal ? clockVal : (32 * 1000 * 1000);
+
+    return clockVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  mcu rtc reset
+ *
+ * @param  rstEn: hold reset or not
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_RST(uint8_t rstEn)
+{
+    uint32_t tmpVal = 0;
+    uint32_t address = 0;
+
+    switch (GLB_Get_Core_Type()) {
+        case GLB_CORE_ID_M0:
+            address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+            break;
+        default:
+            address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+            break;
+    }
+
+    /* set reset */
+    /* MCU RTC_RST is [30] */
+    /* DSP RTC_RST is [30] */
+    /* LP  RTC_RST is [30] */
+    tmpVal = BL_RD_WORD(address);
+    if (rstEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_RST);
+    }
+    BL_WR_WORD(address, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  mcu rtc reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_Reset_MTimer(void)
+{
+    CPU_Set_MTimer_RST(1);
+    CPU_Set_MTimer_RST(0);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set mcu rtc clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  mTimerSourceClockType: Souce Clock Type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_Set_MTimer_CLK(uint8_t enable, BL_MTimer_Source_Clock_Type mTimerSourceClockType, uint16_t div)
+{
+    uint32_t tmpVal = 0;
+    uint32_t address = 0;
+
+    CHECK_PARAM((div <= 0x3FF));
+
+    address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+
+    /* Set MTimer Source Clock */
+    tmpVal = BL_RD_WORD(address);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_CLK_SEL, mTimerSourceClockType);
+    BL_WR_WORD(address, tmpVal);
+
+    /* disable rtc first */
+    /* MCU RTC_EN is [31] */
+    /* DSP RTC_EN is [31] */
+    /* LP  RTC_EN is [31] */
+    tmpVal = BL_RD_WORD(address);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+    BL_WR_WORD(address, tmpVal);
+
+    /* set div */
+    /* MCU RTC_DIV is [9:0] */
+    /* DSP RTC_DIV is [9:0] */
+    /* LP  RTC_DIV is [9:0] */
+    tmpVal = BL_RD_WORD(address);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_DIV, div);
+    BL_WR_WORD(address, tmpVal);
+
+    /* enable or not */
+    /* MCU RTC_EN is [31] */
+    /* DSP RTC_EN is [31] */
+    /* LP  RTC_EN is [31] */
+    tmpVal = BL_RD_WORD(address);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, MCU_MISC_REG_MCU_RTC_EN);
+    }
+    BL_WR_WORD(address, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get cpu rtc source clock
+ *
+ * @param  None
+ *
+ * @return cpu rtc source clock
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Source_Clock(void)
+{
+    uint32_t coreFreq = 0;
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(MCU_MISC_BASE, MCU_MISC_MCU_E907_RTC);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_CLK_SEL);
+
+    /* get cpu core clock */
+    switch (GLB_Get_Core_Type()) {
+        case GLB_CORE_ID_M0:
+            if (tmpVal == BL_MTIMER_SOURCE_CLOCK_MCU_XCLK) {
+                coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+            } else {
+                coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+            }
+            break;
+        default:
+            coreFreq = 0;
+            break;
+    }
+    coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
+
+    return coreFreq;
+}
+
+/****************************************************************************/ /**
+ * @brief  get mcu rtc clock
+ *
+ * @param  None
+ *
+ * @return mcu rtc counter clock
+ *
+*******************************************************************************/
+uint32_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Clock(void)
+{
+    uint32_t coreFreq = 0;
+    uint32_t address = 0;
+    uint32_t div = 0;
+    uint32_t tmpVal = 0;
+
+    address = MCU_MISC_BASE + MCU_MISC_MCU_E907_RTC_OFFSET;
+
+    tmpVal = BL_RD_WORD(address);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, MCU_MISC_REG_MCU_RTC_CLK_SEL);
+
+    /* get cpu core clock */
+    /* get mtimer clock div */
+    switch (GLB_Get_Core_Type()) {
+        case GLB_CORE_ID_M0:
+            if (tmpVal == BL_MTIMER_SOURCE_CLOCK_MCU_XCLK) {
+                coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+            } else {
+                coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+            }
+            break;
+        default:
+            coreFreq = 0;
+            break;
+    }
+    /* MCU RTC_DIV is [9:0] */
+    /* DSP RTC_DIV is [9:0] */
+    /* LP  RTC_DIV is [9:0] */
+    div = BL_GET_REG_BITS_VAL(BL_RD_WORD(address), MCU_MISC_REG_MCU_RTC_DIV);
+    div += 1;
+    coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
+    coreFreq = coreFreq / div; /* mtimer clock = cpu clock / mtimer div */
+
+    return coreFreq;
+}
+
+/****************************************************************************/ /**
+ * @brief  get mcu rtc counter
+ *
+ * @param  None
+ *
+ * @return mcu rtc counter
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_Counter(void)
+{
+    volatile uint64_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
+    uint8_t cnt = 0;
+
+    do {
+        tmpValHigh = (uint64_t)csi_coret_get_valueh();
+        tmpValLow = (uint64_t)csi_coret_get_value();
+        tmpValLow1 = (uint64_t)csi_coret_get_value();
+        tmpValHigh1 = (uint64_t)csi_coret_get_valueh();
+        cnt++;
+        if (cnt > 4) {
+            break;
+        }
+    } while (tmpValLow > tmpValLow1 || tmpValHigh != tmpValHigh1);
+
+    return (uint64_t)((tmpValHigh1 << 32) + tmpValLow1);
+}
+
+/****************************************************************************/ /**
+ * @brief  get mcu cycle
+ *
+ * @param  None
+ *
+ * @return mcu cycle
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_CPU_Cycle(void)
+{
+#if (__riscv_xlen == 64)
+    return (uint64_t)__get_MCYCLE();
+#else
+    volatile uint64_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
+    uint8_t cnt = 0;
+
+    do {
+        tmpValHigh = (uint64_t)__get_MCYCLEH();
+        tmpValLow = (uint64_t)__get_MCYCLE();
+        tmpValLow1 = (uint64_t)__get_MCYCLE();
+        tmpValHigh1 = (uint64_t)__get_MCYCLEH();
+        cnt++;
+        if (cnt > 4) {
+            break;
+        }
+    } while (tmpValLow > tmpValLow1 || tmpValHigh != tmpValHigh1);
+
+    return (uint64_t)((tmpValHigh1 << 32) + tmpValLow1);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  get mcu rtc counter in us
+ *
+ * @param  None
+ *
+ * @return mcu rtc counter in us
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_US(void)
+{
+    uint32_t clk = CPU_Get_MTimer_Clock();
+    uint64_t mtimer_counter = CPU_Get_MTimer_Counter();
+    if (mtimer_counter == 0) {
+        mtimer_counter = CPU_Get_CPU_Cycle();
+        clk = SystemCoreClockGet();
+    }
+
+    if (clk < 1000 * 1000) {
+        return mtimer_counter * 1000 / (clk / 1000);
+    } else {
+        return mtimer_counter / (clk / 1000 / 1000);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  get mcu rtc counter in ms
+ *
+ * @param  None
+ *
+ * @return mcu rtc counter in ms
+ *
+*******************************************************************************/
+uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_MS(void)
+{
+    uint32_t clk = CPU_Get_MTimer_Clock();
+    uint64_t mtimer_counter = CPU_Get_MTimer_Counter();
+    if (mtimer_counter == 0) {
+        mtimer_counter = CPU_Get_CPU_Cycle();
+        clk = SystemCoreClockGet();
+    }
+
+    return mtimer_counter / (clk / 1000);
+}
+
+/****************************************************************************/ /**
+ * @brief  mcu timer delay us
+ *
+ * @param  cnt: us
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_US(uint32_t cnt)
+{
+    volatile uint64_t us1 = 0;
+    volatile uint64_t us2 = 0;
+
+    us1 = CPU_Get_MTimer_US();
+    do {
+        us2 = CPU_Get_MTimer_US();
+    } while (((us2 - us1) < (uint64_t)(cnt)));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  mcu timer delay ms
+ *
+ * @param  cnt: ms
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION CPU_MTimer_Delay_MS(uint32_t cnt)
+{
+    volatile uint64_t ms1 = 0;
+    volatile uint64_t ms2 = 0;
+
+    ms1 = CPU_Get_MTimer_MS();
+    do {
+        ms2 = CPU_Get_MTimer_MS();
+    } while (((ms2 - ms1) < (uint64_t)(cnt)));
+
+    return SUCCESS;
+}
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_common.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_common.c
new file mode 100755
index 0000000000..9248d9a123
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_common.c
@@ -0,0 +1,224 @@
+#include "bl616_common.h"
+#include "bl616_glb.h"
+#include "bl616_clock.h"
+
+/** @addtogroup  BL616_Periph_Driver
+ *  @{
+ */
+
+/** @defgroup DRIVER_COMMON DRIVER_COMMON
+ *  @brief Digger driver common functions
+ *  @{
+ */
+
+/** @defgroup DRIVER_Private_Type
+ *  @{
+ */
+
+/*@} end of group DRIVER_Private_Type*/
+
+/** @defgroup DRIVER_Private_Defines
+ *  @{
+ */
+
+/*@} end of group DRIVER_Private_Defines */
+
+/** @defgroup DRIVER_Private_Variables
+ *  @{
+ */
+
+/*@} end of group DRIVER_Private_Variables */
+
+/** @defgroup DRIVER_Global_Variables
+ *  @{
+ */
+
+/*@} end of group DRIVER_Global_Variables */
+
+/** @defgroup DRIVER_Private_FunctionDeclaration
+ *  @{
+ */
+
+/*@} end of group DRIVER_Private_FunctionDeclaration */
+
+/** @defgroup DRIVER_Private_Functions
+ *  @{
+ */
+
+/*@} end of group DRIVER_Private_Functions */
+
+/** @defgroup DRIVER_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  core:  systemcoreclock
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifdef ARCH_RISCV
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT)
+{
+    volatile uint32_t divVal = loopT;
+    volatile uint32_t speed = 0;
+    volatile uint32_t cycNum = 0;
+
+    /* 1M=100K*10, so multiple is 10 */
+    /* loop function take 4 instructions, so instructionNum is 4 */
+    /* divVal = multiple*instructionNum */
+
+    if (core >= 1 * 1000 * 1000) {
+        /* CPU clock >= 1MHz */
+        speed = core / (100 * 1000);
+        cycNum = speed * cnt;
+        cycNum = cycNum / 10;
+        cycNum = cycNum / divVal;
+        /* cycNum >= 0 */
+    } else {
+        /* CPU clock < 1MHz */
+        speed = core / 1000;
+        cycNum = speed * cnt;
+        cycNum = cycNum / 1000;
+        cycNum = cycNum / divVal;
+        /* cycNum >= 0 */
+    }
+
+    if (!cycNum) {
+        return;
+    }
+
+    __asm__ __volatile__(
+        "mv       a4,%0\n\t"
+        "li       a5,0x0\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        ".align 4\n\t"
+        "1  :\n"
+        "beq      a5,a4,2f\n\t"
+        "addi     a5,a5,0x1\n\t"
+        "j        1b\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        "2   :\n\t"
+        "nop\n"
+        :             /* output */
+        : "r"(cycNum) /* input */
+        : "a4", "a5"  /* destruct description */
+    );
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION arch_delay_us(uint32_t cnt)
+{
+    uint32_t coreFreq;
+    uint32_t loopTick = 3;
+#if defined(__riscv_xthead) || defined(__riscv_xtheadc)
+#if ((__ICACHE_PRESENT == 1U) && (__DCACHE_PRESENT == 1U))
+    uint32_t iCacheEn;
+    uint32_t dCacheEn;
+
+    /* requirement: icache enable && dcache enable */
+    /* otherwise the latency depends on the code address */
+    iCacheEn = (__get_MHCR() & CACHE_MHCR_IE_Msk) >> CACHE_MHCR_IE_Pos;
+    dCacheEn = (__get_MHCR() & CACHE_MHCR_DE_Msk) >> CACHE_MHCR_DE_Pos;
+
+    if(iCacheEn && dCacheEn){
+        loopTick = 3;
+    }else if(iCacheEn && !dCacheEn){
+        loopTick = 4;
+    }else if(!iCacheEn && !dCacheEn){
+        loopTick = 24;
+    }else{
+        /* not recommend */
+    }
+#endif
+#endif
+
+#if defined(DUAL_CORE)
+    GLB_CORE_ID_Type coreID;
+    coreID = GLB_Get_Core_Type();
+    switch (coreID) {
+        case GLB_CORE_ID_M0:
+#endif
+            coreFreq = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_CLK);
+#if defined(DUAL_CORE)
+            break;
+        default:
+            coreFreq = 32 * 1000 * 1000;
+            break;
+    }
+#endif
+
+    coreFreq = coreFreq ? coreFreq : (32 * 1000 * 1000);
+
+    ASM_Delay_Us(coreFreq, cnt, loopTick);
+}
+
+/****************************************************************************/ /**
+ * @brief      delay ms
+ *
+ * @param[in]  cnt:  delay cnt ms
+ *
+ * @return none
+ *
+ *******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION arch_delay_ms(uint32_t cnt)
+{
+    uint32_t i = 0;
+    uint32_t count = 0;
+
+    if (cnt >= 1024) {
+        /* delay (n*1024) ms */
+        for (i = 0; i < (cnt / 1024); i++) {
+            arch_delay_us(1024 * 1000);
+        }
+    }
+
+    count = cnt & 0x3FF;
+
+    if (count) {
+        /* delay (1-1023)ms */
+        arch_delay_us(count * 1000);
+    }
+}
+
+#ifdef DEBUG
+/*******************************************************************************
+* @brief  Reports the name of the source file and the source line number
+*         where the CHECK_PARAM error has occurred.
+
+* @param  file: Pointer to the source file name
+* @param  line: assert_param error line source number
+
+* @return None
+*******************************************************************************/
+void ATTR_TCM_SECTION check_failed(uint8_t *file, uint32_t line)
+{
+    /* Infinite loop */
+    while (1)
+        ;
+}
+#endif /* DEBUG */
+
+/*@} end of group DRIVER_Public_Functions */
+
+/*@} end of group DRIVER_COMMON */
+
+/*@} end of group BL616_Periph_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_ef_cfg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_ef_cfg.c
new file mode 100755
index 0000000000..b70c66e6d8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_ef_cfg.c
@@ -0,0 +1,584 @@
+/**
+  ******************************************************************************
+  * @file    bl616_ef_ctrl.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "bl616_ef_cfg.h"
+#include "hardware/ef_data_reg.h"
+
+extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+
+static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
+    {
+        .name = "ldo15",
+        .en_addr = 0x68 * 8 + 31,
+        .parity_addr = 0x68 * 8 + 30,
+        .value_addr = 0x68 * 8 + 27,
+        .value_len = 3,
+    },
+    {
+        .name = "iptat",
+        .en_addr = 0x74 * 8 + 31,
+        .parity_addr = 0x74 * 8 + 30,
+        .value_addr = 0x68 * 8 + 22,
+        .value_len = 5,
+    },
+    {
+        .name = "icx",
+        .en_addr = 0x74 * 8 + 29,
+        .parity_addr = 0x74 * 8 + 28,
+        .value_addr = 0x74 * 8 + 22,
+        .value_len = 6,
+    },
+    {
+        .name = "dcdc_trim",
+        .en_addr = 0x78 * 8 + 31,
+        .parity_addr = 0x78 * 8 + 30,
+        .value_addr = 0x78 * 8 + 26,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo18_sel",
+        .en_addr = 0x78 * 8 + 25,
+        .parity_addr = 0x78 * 8 + 24,
+        .value_addr = 0x78 * 8 + 20,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo18_trim",
+        .en_addr = 0x78 * 8 + 19,
+        .parity_addr = 0x78 * 8 + 18,
+        .value_addr = 0x78 * 8 + 14,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo33_trim",
+        .en_addr = 0x78 * 8 + 13,
+        .parity_addr = 0x78 * 8 + 12,
+        .value_addr = 0x78 * 8 + 8,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo11_tirm",
+        .en_addr = 0x78 * 8 + 7,
+        .parity_addr = 0x78 * 8 + 6,
+        .value_addr = 0x78 * 8 + 2,
+        .value_len = 4,
+    },
+    {
+        .name = "rc32m",
+        .en_addr = 0x78 * 8 + 1,
+        .parity_addr = 0x78 * 8 + 0,
+        .value_addr = 0x7C * 8 + 4,
+        .value_len = 8,
+    },
+    {
+        .name = "hp_poffset0",
+        .en_addr = 0xCC * 8 + 26,
+        .parity_addr = 0xC0 * 8 + 15,
+        .value_addr = 0xC0 * 8 + 0,
+        .value_len = 15,
+    },
+    {
+        .name = "hp_poffset1",
+        .en_addr = 0xCC * 8 + 27,
+        .parity_addr = 0xC0 * 8 + 31,
+        .value_addr = 0xC0 * 8 + 16,
+        .value_len = 15,
+    },
+    {
+        .name = "hp_poffset2",
+        .en_addr = 0xCC * 8 + 28,
+        .parity_addr = 0xC4 * 8 + 15,
+        .value_addr = 0xC4 * 8 + 0,
+        .value_len = 15,
+    },
+    {
+        .name = "lp_poffset0",
+        .en_addr = 0xCC * 8 + 29,
+        .parity_addr = 0xC4 * 8 + 31,
+        .value_addr = 0xC4 * 8 + 16,
+        .value_len = 15,
+    },
+    {
+        .name = "lp_poffset1",
+        .en_addr = 0xCC * 8 + 30,
+        .parity_addr = 0xC8 * 8 + 15,
+        .value_addr = 0xC8 * 8 + 0,
+        .value_len = 15,
+    },
+    {
+        .name = "lp_poffset2",
+        .en_addr = 0xCC * 8 + 31,
+        .parity_addr = 0xC8 * 8 + 31,
+        .value_addr = 0xC8 * 8 + 16,
+        .value_len = 15,
+    },
+    {
+        .name = "bz_poffset0",
+        .en_addr = 0xD0 * 8 + 26,
+        .parity_addr = 0xCC * 8 + 25,
+        .value_addr = 0xCC * 8 + 0,
+        .value_len = 25,
+    },
+    {
+        .name = "bz_poffset1",
+        .en_addr = 0xD0 * 8 + 27,
+        .parity_addr = 0xD0 * 8 + 25,
+        .value_addr = 0xD0 * 8 + 0,
+        .value_len = 25,
+    },
+    {
+        .name = "bz_poffset2",
+        .en_addr = 0xD0 * 8 + 28,
+        .parity_addr = 0xD4 * 8 + 25,
+        .value_addr = 0xD4 * 8 + 0,
+        .value_len = 25,
+    },
+    {
+        .name = "tmp_mp0",
+        .en_addr = 0xD8 * 8 + 9,
+        .parity_addr = 0xD8 * 8 + 8,
+        .value_addr = 0xD8 * 8 + 0,
+        .value_len = 8,
+    },
+    {
+        .name = "tmp_mp1",
+        .en_addr = 0xD8 * 8 + 19,
+        .parity_addr = 0xD8 * 8 + 18,
+        .value_addr = 0xD8 * 8 + 10,
+        .value_len = 8,
+    },
+    {
+        .name = "tmp_mp2",
+        .en_addr = 0xD8 * 8 + 29,
+        .parity_addr = 0xD8 * 8 + 28,
+        .value_addr = 0xD8 * 8 + 20,
+        .value_len = 8,
+    },
+    {
+        .name = "auadc_gain",
+        .en_addr = 0xDC * 8 + 25,
+        .parity_addr = 0xDC * 8 + 24,
+        .value_addr = 0xDC * 8 + 0,
+        .value_len = 24,
+    },
+    {
+        .name = "auadc_offset",
+        .en_addr = 0xE0 * 8 + 25,
+        .parity_addr = 0xE0 * 8 + 24,
+        .value_addr = 0xE0 * 8 + 0,
+        .value_len = 24,
+    },
+    {
+        .name = "psram_trim",
+        .en_addr = 0xE8 * 8 + 12,
+        .parity_addr = 0xE8 * 8 + 11,
+        .value_addr = 0xE8 * 8 + 0,
+        .value_len = 11,
+    },
+    {
+        .name = "rc32k",
+        .en_addr = 0xEC * 8 + 19,
+        .parity_addr = 0xEC * 8 + 18,
+        .value_addr = 0xEC * 8 + 8,
+        .value_len = 10,
+    },
+    {
+        .name = "xtal0",
+        .en_addr = 0xEC * 8 + 7,
+        .parity_addr = 0xEC * 8 + 6,
+        .value_addr = 0xEC * 8 + 0,
+        .value_len = 6,
+    },
+    {
+        .name = "xtal1",
+        .en_addr = 0xF0 * 8 + 31,
+        .parity_addr = 0xF0 * 8 + 30,
+        .value_addr = 0xF4 * 8 + 26,
+        .value_len = 6,
+    },
+    {
+        .name = "xtal2",
+        .en_addr = 0xF0 * 8 + 29,
+        .parity_addr = 0xF0 * 8 + 28,
+        .value_addr = 0xF4 * 8 + 20,
+        .value_len = 6,
+    },
+    {
+        .name = "gpadc_gain",
+        .en_addr = 0xF0 * 8 + 27,
+        .parity_addr = 0xF0 * 8 + 26,
+        .value_addr = 0xF0 * 8 + 14,
+        .value_len = 12,
+    },
+    {
+        .name = "tsen",
+        .en_addr = 0xF0 * 8 + 13,
+        .parity_addr = 0xF0 * 8 + 12,
+        .value_addr = 0xF0 * 8 + 0,
+        .value_len = 12,
+    },
+    {
+        .name = "dcdc_dis",
+        .en_addr = 0xF4 * 8 + 19,
+        .parity_addr = 0xF4 * 8 + 18,
+        .value_addr = 0xF4 * 8 + 17,
+        .value_len = 1,
+    },
+    {
+        .name = "dcdc_vout",
+        .en_addr = 0xF4 * 8 + 16,
+        .parity_addr = 0xF4 * 8 + 15,
+        .value_addr = 0xF4 * 8 + 10,
+        .value_len = 5,
+    },
+    {
+        .name = "ldo18_bypass",
+        .en_addr = 0xF4 * 8 + 9,
+        .parity_addr = 0xF4 * 8 + 8,
+        .value_addr = 0xF4 * 8 + 4,
+        .value_len = 1,
+    },
+    {
+        .name = "usb20",
+        .en_addr = 0xF8 * 8 + 15,
+        .parity_addr = 0xF8 * 8 + 14,
+        .value_addr = 0xF8 * 8 + 8,
+        .value_len = 6,
+    }
+};
+
+/****************************************************************************/ /**
+ * @brief  Efuse get trim list
+ *
+ * @param  trim_list: Trim list pointer
+ *
+ * @return Trim list count
+ *
+*******************************************************************************/
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
+{
+    *ptrim_list = &trim_list[0];
+    return sizeof(trim_list) / sizeof(trim_list[0]);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read device info
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
+{
+    uint32_t *p = (uint32_t *)deviceInfo;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, p, 1, 1);
+}
+
+void bflb_efuse_get_chipid(uint8_t chipid[8])
+{
+    bflb_efuse_read_mac_address_opt(0, chipid, 1);
+    chipid[6] = 0;
+    chipid[7] = 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Whether MAC address slot is empty
+ *
+ * @param  slot: MAC address slot
+ * @param  reload: whether  reload to check
+ *
+ * @return 0 for all slots full,1 for others
+ *
+*******************************************************************************/
+uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
+{
+    uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
+    uint32_t part1Empty = 0, part2Empty = 0;
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_2_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_3_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_11_W1_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_11_W2_OFFSET, &tmp2, 1, reload);
+    }
+
+    part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
+    part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
+
+    return (part1Empty && part2Empty);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse write optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  program: Whether program
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval;
+    uint32_t i = 0, cnt;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    /* Change to local order */
+    for (i = 0; i < 3; i++) {
+        tmpval = mac[i];
+        mac[i] = mac[5 - i];
+        mac[5 - i] = tmpval;
+    }
+
+    /* The low 32 bits */
+    tmpval = BL_RDWD_FRM_BYTEP(maclow);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_2_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, program);
+    }
+
+    /* The high 16 bits */
+    tmpval = machigh[0] + (machigh[1] << 8);
+    cnt = 0;
+
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    tmpval |= ((cnt & 0x3f) << 16);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_3_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, program);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  reload: Whether reload
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval = 0;
+    uint32_t i = 0;
+    uint32_t cnt = 0;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_2_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, reload);
+    }
+
+    BL_WRWD_TO_BYTEP(maclow, tmpval);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_3_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, reload);
+    }
+
+    machigh[0] = tmpval & 0xff;
+    machigh[1] = (tmpval >> 8) & 0xff;
+
+    /* Check parity */
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) {
+        /* Change to network order */
+        for (i = 0; i < 3; i++) {
+            tmpval = mac[i];
+            mac[i] = mac[5 - i];
+            mac[5 - i] = tmpval;
+        }
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+float bflb_efuse_get_adc_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+    uint32_t tmp;
+
+    float coe = 1.0;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
+
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            tmp = trim.value;
+
+            if (tmp & 0x800) {
+                tmp = ~tmp;
+                tmp += 1;
+                tmp = tmp & 0xfff;
+                coe = (1.0 + ((float)tmp / 2048.0));
+            } else {
+                coe = (1.0 - ((float)tmp / 2048.0));
+            }
+        }
+    }
+
+    return coe;
+}
+
+uint32_t bflb_efuse_get_adc_tsen_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            return trim.value;
+        }
+    }
+
+    return 2042;
+}
+
+void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
+{
+    uint32_t tmpval = 0;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+    *sign = ((tmpval & EF_DATA_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_EF_SBOOT_SIGN_MODE_POS) & 0x01;
+    *aes = ((tmpval & EF_DATA_EF_SF_AES_MODE_MSK) >> EF_DATA_EF_SF_AES_MODE_POS);
+}
+
+void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 5 : index);
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_write_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
+    }
+}
+
+void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 5 : index);
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_read_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
+    }
+}
+
+void bflb_efuse_lock_aes_key_write(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 8 : index);
+        lock |= (1 << (index + 17));
+        bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        lock |= (1 << (index + 15));
+        bflb_ef_ctrl_write_direct(NULL, 0xfc, &lock, 1, 1);
+    }
+}
+
+void bflb_efuse_lock_aes_key_read(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 4 : index);
+        lock |= (1 << (index + 27));
+        bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        lock |= (1 << (index + 25));
+        bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
+    }
+}
+
+void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
+{
+    bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
+}
+
+void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
+{
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb.c
new file mode 100755
index 0000000000..a6fa4edfeb
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb.c
@@ -0,0 +1,3823 @@
+/**
+  ******************************************************************************
+  * @file    bl616_glb.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616_clock.h"
+#include "bl616_glb.h"
+#include "bl616_aon.h"
+#include "bl616_hbn.h"
+#include "bl616_pds.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Private_Macros
+ *  @{
+ */
+#define GLB_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+#define GLB_CLK_SET_DUMMY_TIMEOUT (0xFF)
+#define GLB_FREQ_RC32M            (32000000)
+
+/*@} end of group GLB_Private_Macros */
+
+/** @defgroup  GLB_Private_Types
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };
+#endif
+
+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit);
+
+/*@} end of group GLB_Private_Types */
+
+/** @defgroup  GLB_Private_Variables
+ *  @{
+ */
+
+/* WiFi PLL Config*/
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {
+    .clkpllRefdivRatio = 2,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 0,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 0,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 2,        /*!< pll_icp_5u */
+    .clkpllRz = 3,           /*!< pll_rz */
+    .clkpllCz = 1,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 1,      /*!< pll_r4_short */
+    .clkpllC4En = 0,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 1,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 1,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = {
+    .clkpllRefdivRatio = 1,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 0,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 0,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 2,        /*!< pll_icp_5u */
+    .clkpllRz = 3,           /*!< pll_rz */
+    .clkpllCz = 1,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 1,      /*!< pll_r4_short */
+    .clkpllC4En = 0,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 1,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 1,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = {
+    .clkpllRefdivRatio = 1,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 0 },                                 /*!< XTAL is None */
+    { &wifiPllBasicCfg_24M, 0x1400000, 0 },           /*!< XTAL is 24M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000, 0 }, /*!< XTAL is 32M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000, 0 }, /*!< XTAL is 38.4M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000, 0 }, /*!< XTAL is 40M */
+    { &wifiPllBasicCfg_26M, 0x1276276, 0 },           /*!< XTAL is 26M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000, 0 }, /*!< XTAL is RC32M */
+};
+const uint32_t ATTR_CLOCK_CONST_SECTION usbPllSdmin_12M = 0x28000;
+const uint32_t ATTR_CLOCK_CONST_SECTION sscDivSdmin_24M = 0x28000;
+
+/* Audio PLL Config*/
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = {
+    .clkpllRefdivRatio = 2,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = {
+    .clkpllRefdivRatio = 4,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_491P52M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 20 },                                /*!< XTAL is None */
+    { &audioPllBasicCfg_24M_26M, 0x147AE, 20 },       /*!< XTAL is 24M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1EB85, 20 }, /*!< XTAL is 32M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x19999, 20 }, /*!< XTAL is 38.4M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x18937, 20 }, /*!< XTAL is 40M */
+    { &audioPllBasicCfg_24M_26M, 0x12E79, 20 },       /*!< XTAL is 26M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1EB85, 20 }, /*!< XTAL is RC32M */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P58M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 20 },                                /*!< XTAL is None */
+    { &audioPllBasicCfg_24M_26M, 0x12D0D, 20 },       /*!< XTAL is 24M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1C394, 20 }, /*!< XTAL is 32M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x17851, 20 }, /*!< XTAL is 38.4M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x16943, 20 }, /*!< XTAL is 40M */
+    { &audioPllBasicCfg_24M_26M, 0x115E5, 20 },       /*!< XTAL is 26M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1C394, 20 }, /*!< XTAL is RC32M */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_400M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 8 },                                /*!< XTAL is None */
+    { &audioPllBasicCfg_24M_26M, 0x10AAA, 8 },       /*!< XTAL is 24M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x19000, 8 }, /*!< XTAL is 32M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x14D55, 8 }, /*!< XTAL is 38.4M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x14000, 8 }, /*!< XTAL is 40M */
+    { &audioPllBasicCfg_24M_26M, 0xF627, 8 },        /*!< XTAL is 26M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x19000, 8 }, /*!< XTAL is RC32M */
+};
+
+/* Audio PLL Config*/
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPll384BasicCfg_24M_26M = {
+    .clkpllRefdivRatio = 2,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPll384BasicCfg_32M_38P4M_40M = {
+    .clkpllRefdivRatio = 4,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_384M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 8 },                                   /*!< XTAL is None */
+    { &audioPll384BasicCfg_24M_26M, 0x10000, 8 },       /*!< XTAL is 24M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x18000, 8 }, /*!< XTAL is 32M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x14000, 8 }, /*!< XTAL is 38.4M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x13333, 8 }, /*!< XTAL is 40M */
+    { &audioPll384BasicCfg_24M_26M, 0xEC4E, 8 },        /*!< XTAL is 26M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x18000, 8 }, /*!< XTAL is RC32M */
+};
+
+const GLB_SLAVE_GRP_0_TBL_Type ATTR_CLOCK_CONST_SECTION glb_slave_grp_0_table[GLB_SLAVE_GRP_0_MAX] = {
+    { GLB_ADC_CFG0_OFFSET, GLB_GPADC_32M_DIV_EN_POS, GLB_GPADC_32M_CLK_SEL_POS, GLB_GPADC_32M_CLK_DIV_POS, GLB_GPADC_32M_DIV_EN_LEN, GLB_GPADC_32M_CLK_SEL_LEN, GLB_GPADC_32M_CLK_DIV_LEN },
+    { GLB_IR_CFG0_OFFSET, GLB_IR_CLK_EN_POS, 0, GLB_IR_CLK_DIV_POS, GLB_IR_CLK_EN_LEN, 0, GLB_IR_CLK_DIV_LEN },
+    { GLB_I2C_CFG0_OFFSET, GLB_I2C_CLK_EN_POS, GLB_I2C_CLK_SEL_POS, GLB_I2C_CLK_DIV_POS, GLB_I2C_CLK_EN_LEN, GLB_I2C_CLK_SEL_LEN, GLB_I2C_CLK_DIV_LEN },
+    { GLB_SPI_CFG0_OFFSET, GLB_SPI_CLK_EN_POS, GLB_SPI_CLK_SEL_POS, GLB_SPI_CLK_DIV_POS, GLB_SPI_CLK_EN_LEN, GLB_SPI_CLK_SEL_LEN, GLB_SPI_CLK_DIV_LEN },
+    { GLB_PEC_CFG0_OFFSET, GLB_PEC_CLK_EN_POS, GLB_PEC_CLK_SEL_POS, GLB_PEC_CLK_DIV_POS, GLB_PEC_CLK_EN_LEN, GLB_PEC_CLK_SEL_LEN, GLB_PEC_CLK_DIV_LEN },
+    { GLB_DBI_CFG0_OFFSET, GLB_DBI_CLK_EN_POS, GLB_DBI_CLK_SEL_POS, GLB_DBI_CLK_DIV_POS, GLB_DBI_CLK_EN_LEN, GLB_DBI_CLK_SEL_LEN, GLB_DBI_CLK_DIV_LEN },
+    { GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_AUTO_DIV_EN_POS, 0, 0, GLB_REG_AUDIO_AUTO_DIV_EN_LEN, 0, 0 },
+    { GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_ADC_CLK_EN_POS, 0, GLB_REG_AUDIO_ADC_CLK_DIV_POS, GLB_REG_AUDIO_ADC_CLK_EN_LEN, 0, GLB_REG_AUDIO_ADC_CLK_DIV_LEN },
+    { GLB_AUDIO_CFG1_OFFSET, GLB_REG_AUDIO_SOLO_CLK_EN_POS, 0, GLB_REG_AUDIO_SOLO_CLK_DIV_POS, GLB_REG_AUDIO_SOLO_CLK_EN_LEN, 0, GLB_REG_AUDIO_SOLO_CLK_DIV_LEN },
+    { GLB_CAM_CFG0_OFFSET, GLB_REG_CAM_REF_CLK_EN_POS, GLB_REG_CAM_REF_CLK_SRC_SEL_POS, GLB_REG_CAM_REF_CLK_DIV_POS, GLB_REG_CAM_REF_CLK_EN_LEN, GLB_REG_CAM_REF_CLK_SRC_SEL_LEN, GLB_REG_CAM_REF_CLK_DIV_LEN },
+    { GLB_SDH_CFG0_OFFSET, GLB_REG_SDH_CLK_EN_POS, GLB_REG_SDH_CLK_SEL_POS, GLB_REG_SDH_CLK_DIV_POS, GLB_REG_SDH_CLK_EN_LEN, GLB_REG_SDH_CLK_SEL_LEN, GLB_REG_SDH_CLK_DIV_LEN },
+    { GLB_PSRAM_CFG0_OFFSET, GLB_REG_PSRAMB_CLK_EN_POS, GLB_REG_PSRAMB_CLK_SEL_POS, GLB_REG_PSRAMB_CLK_DIV_POS, GLB_REG_PSRAMB_CLK_EN_LEN, GLB_REG_PSRAMB_CLK_SEL_LEN, GLB_REG_PSRAMB_CLK_DIV_LEN },
+};
+
+/*@} end of group GLB_Private_Variables */
+
+/** @defgroup  GLB_Global_Variables
+ *  @{
+ */
+
+/*@} end of group GLB_Global_Variables */
+
+/** @defgroup  GLB_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Fun_Declaration */
+
+/** @defgroup  GLB_Private_Functions
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Functions */
+
+/** @defgroup  GLB_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  set mcu muxpll 160M selection
+ *
+ * @param  clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_160M_Sel(GLB_MCU_MUXPLL_160M_CLK_SEL_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_MCU_MUXPLL_160M_CLK_SEL_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get mcu muxpll 160M selection
+ *
+ * @param  None
+ *
+ * @return 160M mux select value
+ *
+*******************************************************************************/
+GLB_MCU_MUXPLL_160M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_160M_Sel(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+    return (GLB_MCU_MUXPLL_160M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief  set top muxpll 80M selection
+ *
+ * @param  clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_Muxpll_80M_Sel(GLB_MCU_MUXPLL_80M_CLK_SEL_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_MCU_MUXPLL_80M_CLK_SEL_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get mcu muxpll 80M selection
+ *
+ * @param  None
+ *
+ * @return 80M mux select value
+ *
+*******************************************************************************/
+GLB_MCU_MUXPLL_80M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_MCU_Muxpll_80M_Sel(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+    return (GLB_MCU_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief  set isp muxpll 80M selection
+ *
+ * @param  clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_ISP_Muxpll_80M_Sel(GLB_ISP_MUXPLL_80M_CLK_SEL_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_ISP_MUXPLL_80M_CLK_SEL_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_ISP_MUXPLL_80M_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get isp muxpll 80M selection
+ *
+ * @param  None
+ *
+ * @return 80M mux select value
+ *
+*******************************************************************************/
+GLB_ISP_MUXPLL_80M_CLK_SEL_Type ATTR_CLOCK_SECTION GLB_Get_ISP_Muxpll_80M_Sel(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG1);
+    return (GLB_ISP_MUXPLL_80M_CLK_SEL_Type)(BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_ISP_MUXPLL_80M_SEL));
+}
+
+/****************************************************************************/ /**
+ * @brief  power on all PLL clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  pllType: only power on xtal
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type pllType)
+{
+    uint32_t tmpVal;
+    HBN_MCU_XCLK_Type mcuXclkSel;
+    HBN_MCU_ROOT_CLK_Type mcuRootClkSel;
+    volatile GLB_PLL_REF_CLK_Type refClk;
+
+    CHECK_PARAM(IS_GLB_XTAL_TYPE(xtalType));
+    CHECK_PARAM((pllType < (GLB_PLL_AUPLL * 2)));
+
+    if (xtalType == GLB_XTAL_NONE) {
+        return ERROR;
+    }
+
+    if (xtalType != GLB_XTAL_RC32M) {
+        /* power on xtal first */
+        AON_Power_On_XTAL();
+    }
+
+#if defined(DUAL_CORE)
+    GLB_CORE_ID_Type coreType;
+    coreType = GLB_Get_Core_Type();
+    if ((GLB_CORE_ID_M0 == coreType)) {
+#endif
+        /* M0 */
+        /* Before config XTAL and PLL ,make sure root clk is from RC32M */
+        mcuXclkSel = HBN_Get_MCU_XCLK_Sel();
+        mcuRootClkSel = HBN_Get_MCU_Root_CLK_Sel();
+        if ((mcuXclkSel != HBN_MCU_XCLK_RC32M) || (mcuRootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {
+            HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+        }
+        GLB_Set_MCU_System_CLK_Div(0, 0);
+#if defined(DUAL_CORE)
+    }
+#endif
+
+    HBN_Set_Xtal_Type(xtalType);
+
+    if (GLB_PLL_NONE == pllType) {
+        GLB_CLK_SET_DUMMY_WAIT;
+        return SUCCESS;
+    }
+
+    if (xtalType == GLB_XTAL_RC32M) {
+        refClk = GLB_PLL_REFCLK_RC32M;
+    } else {
+        refClk = GLB_PLL_REFCLK_XTAL;
+    }
+
+    /* power on wifipll */
+    if (pllType & GLB_PLL_WIFIPLL) {
+        GLB_Power_Off_WIFIPLL();
+        GLB_WIFIPLL_Ref_Clk_Sel(refClk);
+        GLB_Power_On_WIFIPLL(&wifiPllCfg_960M[xtalType], 0);
+    }
+
+    /* power on aupll */
+    if (pllType & GLB_PLL_AUPLL) {
+        GLB_Power_Off_AUPLL();
+        GLB_AUPLL_Ref_Clk_Sel(refClk);
+        GLB_Power_On_AUPLL(&audioPllCfg_491P52M[xtalType], 0);
+    }
+
+    arch_delay_us(75);
+
+    if (xtalType != GLB_XTAL_RC32M) {
+        /* if power on xtal, always set xclk from xtal */
+        HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);
+    }
+
+    /* enable all PLL clock output */
+    /* GLB reg_pll_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
+    BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
+
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB power off wifipll
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_WIFIPLL(void)
+{
+    uint32_t REG_PLL_BASE_ADDRESS = 0;
+    uint32_t tmpVal = 0;
+
+    REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
+
+    /* cfg0 : pu_wifipll=0 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* cfg0 : pu_wifipll_sfreg=0 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL_SFREG, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB wifipll ref clock select
+ *
+ * @param  refClk: PLL ref clock select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_WIFIPLL_Ref_Clk_Sel(GLB_PLL_REF_CLK_Type refClk)
+{
+    uint32_t REG_PLL_BASE_ADDRESS = 0;
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));
+
+    REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
+
+    /* xxxpll_refclk_sel */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+    if (GLB_PLL_REFCLK_XTAL == refClk) {
+        /* wifipll_refclk_sel different from other's pll, 1 means xtal */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_REFCLK_SEL, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_REFCLK_SEL, refClk);
+    }
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB power on wifipll
+ *
+ * @param  cfg: GLB PLL configuration
+ * @param  waitStable: wait PLL clock stable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WIFIPLL(const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable)
+{
+    uint32_t REG_PLL_BASE_ADDRESS = 0;
+    uint32_t tmpVal = 0;
+
+    REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
+
+    /* Step1:config parameter */
+    /* cfg1:Set wifipll_refclk_sel and wifipll_refdiv_ratio */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+    /* cfg2:Set wifipll_int_frac_sw,wifipll_icp_1u,wifipll_icp_5u */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);
+
+    /* cfg3:Set wifipll_rz,wifipll_cz,wifipll_c3,wifipll_r4_short,wifipll_r4_en */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_RZ, cfg->basicCfg->clkpllRz);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_CZ, cfg->basicCfg->clkpllCz);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_C3, cfg->basicCfg->clkpllC3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_C4_EN, cfg->basicCfg->clkpllC4En);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);
+
+    /* cfg4:Set wifipll_sel_sample_clk */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);
+
+    /* cfg5:Set wifipll_vco_speed */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);
+
+    /* cfg6:Set wifipll_sdm_bypass,wifipll_sdmin */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);
+
+    /* cfg10:always set usbpll_sdmin */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USBPLL_SDMIN, usbPllSdmin_12M);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 10, tmpVal);
+
+    /* cfg12:always set sscdiv_sdmin */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 12);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SSCDIV_SDMIN, sscDivSdmin_24M);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 12, tmpVal);
+
+    /* Step2:config pu */
+    /* cfg0 : pu_wifipll_sfreg=1 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL_SFREG, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* delay > 2us */
+    arch_delay_us(3);
+
+    /* cfg0 : pu_wifipll=1 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* delay > 2us */
+    arch_delay_us(3);
+
+    /* toggle sdm_reset (pulse 0 > 1us) */
+    /* cfg0 : wifipll_sdm_reset */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* Step3:reset pll */
+    /* cfg0 : toggle wifipll_reset_fbdv, pulse 0 > 1us */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* Step4:enable output clock */
+    /* cfg8 : wifipll clock enable */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV3);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV12);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV20);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV30);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);
+
+    if (waitStable) {
+        /* Wait 1.5*30us    */
+        arch_delay_us(45);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB power off aupll
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_AUPLL(void)
+{
+    uint32_t REG_PLL_BASE_ADDRESS = 0;
+    uint32_t tmpVal = 0;
+
+    REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+
+    /* cfg0 : pu_aupll=0 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* cfg0 : pu_aupll_sfreg=0 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB wifi aupll ref clock select
+ *
+ * @param  refClk: PLL ref clock select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_AUPLL_Ref_Clk_Sel(GLB_PLL_REF_CLK_Type refClk)
+{
+    uint32_t REG_PLL_BASE_ADDRESS = 0;
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PLL_REF_CLK_TYPE(refClk));
+
+    REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+
+    /* xxxpll_refclk_sel */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFCLK_SEL, refClk);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB power on PLL
+ *
+ * @param  cfg: GLB PLL configuration
+ * @param  waitStable: wait PLL clock stable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_AUPLL(const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable)
+{
+    uint32_t REG_PLL_BASE_ADDRESS = 0;
+    uint32_t tmpVal = 0;
+
+    REG_PLL_BASE_ADDRESS = CCI_BASE + CCI_AUDIO_PLL_CFG0_OFFSET;
+
+    /* Step1:config parameter */
+    /* cfg1:Set aupll_refclk_sel and aupll_refdiv_ratio */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+    /* cfg2:Set aupll_int_frac_sw,aupll_icp_1u,aupll_icp_5u */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);
+
+    /* cfg3:Set aupll_rz,aupll_cz,aupll_c3,aupll_r4_short,aupll_r4_en */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_RZ, cfg->basicCfg->clkpllRz);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_CZ, cfg->basicCfg->clkpllCz);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C3, cfg->basicCfg->clkpllC3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_C4_EN, cfg->basicCfg->clkpllC4En);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);
+
+    /* cfg4:Set aupll_sel_sample_clk */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);
+
+    /* cfg5:Set aupll_vco_speed */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);
+
+    /* cfg6:Set aupll_sdm_bypass,aupll_sdmin */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDMIN, cfg->clkpllSdmin);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);
+
+    /* cfg1:Set aupll_postdiv */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, cfg->clkpllPostDiv);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+    /* Step2:config pu */
+    /* cfg0 : pu_aupll_sfreg=1 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL_SFREG, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* delay > 2us */
+    arch_delay_us(3);
+
+    /* cfg0 : pu_wifipll=1 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_PU_AUPLL, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* delay > 2us */
+    arch_delay_us(3);
+
+    /* toggle sdm_reset (pulse 0 > 1us) */
+    /* cfg0 : aupll_sdm_reset */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_SDM_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* Step3:reset pll */
+    /* cfg0 : toggle aupll_reset_fbdv, pulse 0 > 1us */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_FBDV_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* Step4:enable output clock */
+    /* cfg8 : wifipll/aupll/cpupll clock enable */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);
+    tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV2P5);
+    tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV5);
+    tmpVal = BL_SET_REG_BIT(tmpVal, CCI_AUPLL_EN_DIV6);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);
+
+    if (waitStable) {
+        /* Wait 1.5*30us    */
+        arch_delay_us(45);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB enable or disable USB clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    /* pu_usbpll_mmdiv */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_USBPLL_MMDIV);
+    }
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+
+    /* delay > 2us */
+    arch_delay_us(3);
+
+    /* toggle usbpll_rstb */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USBPLL_RSTB);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG10);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USBPLL_RSTB);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG10, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GLB enable or disable SSC clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SSC_CLK_From_WIFIPLL(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    /* pu_usbpll_mmdiv */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG12);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_SSCDIV_MMDIV);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_SSCDIV_MMDIV);
+    }
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG12, tmpVal);
+
+    /* delay > 2us */
+    arch_delay_us(3);
+
+    /* toggle sscdiv_rstb */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG12);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SSCDIV_RSTB);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG12, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG12);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SSCDIV_RSTB);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG12, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG12);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SSCDIV_RSTB);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_PLL_CFG12, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set System clock divider
+ *
+ * @param  mcuClkDiv: HCLK divider
+ * @param  mcuPBclkDiv: BCLK divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv)
+{
+    uint32_t tmpVal;
+    uint32_t timeout = 1024;
+    HBN_MCU_XCLK_Type xclkSel;
+    HBN_MCU_ROOT_CLK_Type rootClkSel;
+
+    /* get root clock */
+    xclkSel = HBN_Get_MCU_XCLK_Sel();
+    rootClkSel = HBN_Get_MCU_Root_CLK_Sel();
+
+    if ((xclkSel != HBN_MCU_XCLK_RC32M) || (rootClkSel != HBN_MCU_ROOT_CLK_XCLK)) {
+        HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+        HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+    }
+
+    /* config hclk_div=mcuClkDiv */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, mcuClkDiv);
+    BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
+
+    /* config bclk_div=mcuPBclkDiv */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, mcuPBclkDiv);
+    BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
+    /* bclk act pulse */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV_ACT_PULSE, 1);
+    BL_WR_REG(GLB_BASE, GLB_SYS_CFG1, tmpVal);
+
+    timeout = 1024;
+    do {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG1);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_STS_BCLK_PROT_DONE);
+    } while ((--timeout) && (!tmpVal));
+    if (!timeout) {
+        return ERROR;
+    }
+
+    /* recover root clock */
+    HBN_Set_MCU_XCLK_Sel(xclkSel);
+    HBN_Set_MCU_Root_CLK_Sel(rootClkSel);
+
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get System clock divider
+ *
+ * @param  mcuClkDiv: HCLK divider
+ * @param  mcuPBclkDiv: BCLK divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv)
+{
+    if ((NULL == mcuClkDiv) || (NULL == mcuPBclkDiv)) {
+        return ERROR;
+    }
+
+    *mcuClkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_HCLK_DIV);
+    *mcuPBclkDiv = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_SYS_CFG0), GLB_REG_BCLK_DIV);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set mcu System clock
+ *
+ * @param  clkFreq: mcu system clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq)
+{
+    uint32_t tmpVal;
+    HBN_MCU_XCLK_Type mcuXclkSel;
+
+    CHECK_PARAM(IS_GLB_MCU_SYS_CLK_TYPE(clkFreq));
+
+    /* get xclk&&rootclk clock */
+    mcuXclkSel = HBN_Get_MCU_XCLK_Sel();
+
+    /* change root clock to rc32m */
+    HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+    HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+    GLB_Set_MCU_System_CLK_Div(0, 0);
+
+    /* select pll output clock before select root clock */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+    switch (clkFreq) {
+        case GLB_MCU_SYS_CLK_TOP_AUPLL_DIV2:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 0);
+            break;
+        case GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 1);
+            break;
+        case GLB_MCU_SYS_CLK_TOP_WIFIPLL_240M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 2);
+            break;
+        case GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_PLL_SEL, 3);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);
+
+    /* select root clock */
+    switch (clkFreq) {
+        case GLB_MCU_SYS_CLK_RC32M:
+            GLB_Set_MCU_System_CLK_Div(0, 0);
+            HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+            break;
+        case GLB_MCU_SYS_CLK_XTAL:
+            GLB_Set_MCU_System_CLK_Div(0, 0);
+            HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+            break;
+        case GLB_MCU_SYS_CLK_TOP_AUPLL_DIV2:
+            /* For high speed, set DIV first */
+            GLB_Set_MCU_System_CLK_Div(0, 2);
+            /* Set IROM 2T Access 0 since we use RC32M, unuseful now */
+            /* MCU_MISC_IROM_2T_Access_Set(0); */
+            /* unuseful for mcu, useful for dsp, just for safe */
+            GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_AUPLL_DIV2);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);
+            /* recover xclk */
+            HBN_Set_MCU_XCLK_Sel(mcuXclkSel);
+            break;
+        case GLB_MCU_SYS_CLK_TOP_AUPLL_DIV1:
+            /* For high speed, set DIV first */
+            GLB_Set_MCU_System_CLK_Div(1, 2);
+            /* Set IROM 2T Access 0 since we use RC32M, unuseful now */
+            /* MCU_MISC_IROM_2T_Access_Set(0); */
+            /* unuseful for mcu, useful for dsp, just for safe */
+            GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_AUPLL_DIV1);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);
+            /* recover xclk */
+            HBN_Set_MCU_XCLK_Sel(mcuXclkSel);
+            break;
+        case GLB_MCU_SYS_CLK_TOP_WIFIPLL_240M:
+            /* For high speed, set DIV first */
+            GLB_Set_MCU_System_CLK_Div(0, 2);
+            /* Set IROM 2T Access 0 since we use RC32M, unuseful now */
+            /* MCU_MISC_IROM_2T_Access_Set(0); */
+            /* unuseful for mcu, useful for dsp, just for safe */
+            GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_WIFIPLL_240M);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);
+            /* recover xclk */
+            HBN_Set_MCU_XCLK_Sel(mcuXclkSel);
+            break;
+        case GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M:
+            /* For high speed, set DIV first */
+            GLB_Set_MCU_System_CLK_Div(0, 3);
+            /* Set IROM 2T Access 0 since we use RC32M, unuseful now */
+            /* MCU_MISC_IROM_2T_Access_Set(0); */
+            GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_WIFIPLL_320M);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_PLL);
+            /* recover xclk */
+            HBN_Set_MCU_XCLK_Sel(mcuXclkSel);
+            break;
+        default:
+            break;
+    }
+
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get core type
+ *
+ * @param  None
+ *
+ * @return core type
+ *
+*******************************************************************************/
+GLB_CORE_ID_Type ATTR_CLOCK_SECTION GLB_Get_Core_Type(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_WORD(CORE_ID_ADDRESS);
+
+    switch (tmpVal) {
+        case CORE_ID_M0:
+            return GLB_CORE_ID_M0;
+        default:
+            return GLB_CORE_ID_INVALID;
+    }
+
+    return GLB_CORE_ID_INVALID;
+}
+
+/****************************************************************************/ /**
+ * @brief  set CPU reset address
+ *
+ * @param  coreID: core type
+ * @param  addr: reset address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr)
+{
+    CHECK_PARAM(IS_GLB_CORE_ID_TYPE(coreID));
+
+    switch (coreID) {
+        case GLB_CORE_ID_M0:
+            BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr);
+            break;
+        default:
+            return ERROR;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Clr_EMI_Reset_Gate(void)
+{
+    uint32_t tmpVal;
+
+    /* clear EMI swrst bit */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWRST_S1_EXT_EMI_MISC);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG0, tmpVal);
+
+    /* set EMI cgen bit */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CGEN_S1_EXT_EMI_MISC);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set ADC clock
+ *
+ * @param  enable: enable frequency divider or not
+ * @param  clkSel: ADC clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3F));
+
+    /* disable ADC clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DMA clock
+ *
+ * @param  enable: Enable or disable
+ * @param  clk: DMA clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_GLB_DMA_CLK_ID_TYPE(clk));
+
+    /* DMA0 */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG0);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);
+    if (enable) {
+        tmpVal2 |= (1 << clk);
+    } else {
+        tmpVal2 &= (~(1 << clk));
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);
+    BL_WR_REG(GLB_BASE, GLB_DMA_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set peripheral DMA cn
+ *
+ * @param  peri: peripheral
+ * @param  cn: cn
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PERI_DMA_TYPE(peri));
+    CHECK_PARAM(IS_GLB_PERI_DMA_CN_SEL_TYPE(cn));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DMA_CFG2);
+    switch (cn) {
+        case GLB_PERI_DMA_CN_SEL_DMA0:
+            tmpVal &= ~(1 << peri);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DMA_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set IR clock divider
+ *
+ * @param  enable: enable or disable IR clock
+ * @param  clkSel: IR clock type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3F));
+
+    (void)clkSel;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select ir rx gpio (gpio11~gpio13)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    /* Select gpio between gpio9 and gpio23 */
+    if (gpio > 8 && gpio < 24) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 8);
+        BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);
+    }
+
+    /* Close ir rx */
+    if (gpio == 0) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, 0);
+        BL_WR_REG(GLB_BASE, GLB_IR_CFG1, tmpVal);
+    } else {
+        return ERROR;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set UART clock
+ *
+ * @param  enable: Enable or disable UART clock
+ * @param  clkSel: UART clock type
+ * @param  div: UART clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x7));
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    /* disable UART clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);
+
+    /* Set div */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);
+
+    /* Select clock source for uart */
+    HBN_Set_UART_CLK_Sel(clkSel);
+
+    /* Set enable or disable */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_UART_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select UART signal function
+ *
+ * @param  sig: UART signal
+ * @param  fun: UART function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)
+{
+    uint32_t sig_pos = 0;
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));
+    CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));
+
+    if (sig < GLB_UART_SIG_8) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG1);
+        sig_pos = (sig * 4);
+        /* Clear original val */
+        tmpVal &= (~(0xf << sig_pos));
+        /* Set new value */
+        tmpVal |= (fun << sig_pos);
+        BL_WR_REG(GLB_BASE, GLB_UART_CFG1, tmpVal);
+    } else {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_CFG2);
+        sig_pos = ((sig - 8) * 4);
+        /* Clear original val */
+        tmpVal &= (~(0xf << sig_pos));
+        /* Set new value */
+        tmpVal |= (fun << sig_pos);
+        BL_WR_REG(GLB_BASE, GLB_UART_CFG2, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set sflash clock
+ *
+ * @param  enable: enable or disable sflash clock
+ * @param  clkSel: sflash clock type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x7));
+
+    /* disable SFLASH clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);
+
+    if (clkSel == GLB_SFLASH_CLK_TOP_AUPLL_DIV5) {
+        GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_TOP_AUPLL_DIV5);
+    }
+
+    /* clock divider */
+    /* Select flash clock, all Flash CLKs are divied by PLL_480M */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);
+    switch (clkSel) {
+        case GLB_SFLASH_CLK_WIFIPLL_120M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);
+            break;
+        case GLB_SFLASH_CLK_XTAL:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);
+            break;
+        case GLB_SFLASH_CLK_TOP_AUPLL_DIV5:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);
+            break;
+        case GLB_SFLASH_CLK_MUXPLL_80M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);
+            break;
+        case GLB_SFLASH_CLK_BCLK:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);
+            break;
+        case GLB_SFLASH_CLK_WIFIPLL_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);
+
+    /* enable or disable flash clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SF_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SF_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2C clock
+ *
+ * @param  enable: Enable or disable I2C clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_I2C_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2S clock
+ *
+ * @param  refClkEn: ref clock ENABLE or DISABLE
+ * @param  refClkDiv: divider
+ * @param  inRef: di ref clock
+ * @param  outRef: do ref clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((refClkDiv <= 0x3F));
+    CHECK_PARAM(IS_GLB_I2S_DI_REF_CLK_TYPE(inRef));
+    CHECK_PARAM(IS_GLB_I2S_DO_REF_CLK_TYPE(outRef));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2S_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DO_REF_CLK_SEL, outRef);
+    if (refClkEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S_REF_CLK_EN);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_DI_REF_CLK_SEL, inRef);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV, refClkDiv);
+    BL_WR_REG(GLB_BASE, GLB_I2S_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set SPI clock
+ *
+ * @param  enable: Enable or disable SPI clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_SPI_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap SPI gpio pins sig function
+ *
+ * @param  group: SPI swap set group
+ * @param  swap: swap or no swap
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_SPI_Sig_Swap_Set(GLB_SPI_SIG_SWAP_GRP_Type group, uint8_t swap)
+{
+    uint32_t tmpVal = 0;
+    uint32_t tmpVal2 = 0;
+
+    CHECK_PARAM(IS_GLB_SPI_SIG_SWAP_GRP_TYPE(group));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_SWAP_SET);
+    if (swap) {
+        tmpVal2 |= (1 << group);
+    } else {
+        tmpVal2 &= ~(1 << group);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_SWAP_SET, tmpVal2);
+    BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set PEC clock
+ *
+ * @param  enable: Enable or disable PEC clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PEC_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+    tmpVal >>= 1;
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+    tmpVal >>= 1;
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+    tmpVal >>= 1;
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set PWM1 clock
+ *
+ * @param  ioSel: io select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PWM1_IO_SEL_TYPE(ioSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PWM_CFG0);
+    tmpVal >>= 1;
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PWM1_IO_SEL, ioSel);
+    BL_WR_REG(GLB_BASE, GLB_PWM_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set PDM clock
+ *
+ * @param  ioSel: io select
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PDM_IO_Sel(GLB_PDM_IO_SEL_Type ioSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PDM_IO_SEL_TYPE(ioSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM_IO_SEL, ioSel);
+    BL_WR_REG(GLB_BASE, GLB_PDM_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DBI clock
+ *
+ * @param  enable: Enable or disable DBI clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DBI_CLK(uint8_t enable, GLB_DBI_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DBI_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DBI_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_DBI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DBI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DBI_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DBI_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DBI_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select DIG clock source
+ *
+ * @param  clkSel: DIG clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+    uint32_t dig512kEn;
+    uint32_t dig32kEn;
+
+    CHECK_PARAM(IS_GLB_DIG_CLK_TYPE(clkSel));
+
+    /* disable DIG512K and DIG32K clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);
+    dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    /* repristinate DIG512K and DIG32K clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 512K clock
+ *
+ * @param  enable: enable or disable DIG 512K clock
+ * @param  compensationEn: enable or disable DIG 512K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensationEn, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((div <= 0x7F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    if (compensationEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 32K clock
+ *
+ * @param  enable: enable or disable DIG 32K clock
+ * @param  compensationEn: enable or disable DIG 32K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((div <= 0x7FF));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    if (compensationEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  platform wakeup becomes one of  pds_wakeup source
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EN_PLATFORM_WAKEUP);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  mcu gpio timer clock select
+ *
+ * @param  gpioPin: gpio pin number
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    switch (gpioPin & 0x3) {
+        case 0: /* inout_sig_0 */
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 0);
+            break;
+        case 1: /* inout_sig_1 */
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 1);
+            break;
+        case 2: /* inout_sig_2 */
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 2);
+            break;
+        case 3: /* inout_sig_3 */
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPIO_TMR_CLK_SEL, 3);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out0 select
+ *
+ * @param  clkOutType: chip clock out0 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out0 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out1 select
+ *
+ * @param  clkOutType: chip clock out1 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out1 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out2 select
+ *
+ * @param  clkOutType: chip clock out2 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out2 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out3 select
+ *
+ * @param  clkOutType: chip clock out3 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out3 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX init
+ *
+ * @param  BmxCfg: BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF);
+    CHECK_PARAM(IS_BMX_ARB_TYPE(BmxCfg->arbMod));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BMX_ARB_MODE, BmxCfg->arbMod);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(BMX_MCU_TO_IRQn, BMX_TO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get BMX TO status
+ *
+ * @param  None
+ *
+ * @return BMX TO status
+ *
+*******************************************************************************/
+uint8_t GLB_Get_BMX_TO_Status(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_BMX_CFG0), GLB_STS_BMX_TIMEOUT_STS);
+}
+
+/****************************************************************************/ /**
+ * @brief  clear BMX TO status
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Clr_BMX_TO_Status(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_BMX_TIMEOUT_CLR);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX timeout interrupt callback install
+ *
+ * @param  intType: BMX timeout interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));
+
+    glbBmxToIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  BMX Time Out interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_TO_IRQHandler(void)
+{
+    BMX_TO_INT_Type intType;
+
+    for (intType = 0; intType < BMX_TO_INT_ALL; intType++) {
+        if (glbBmxToIntCbfArra[intType] != NULL) {
+            glbBmxToIntCbfArra[intType]();
+        }
+    }
+    GLB_Clr_BMX_TO_Status();
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set audio auto clock
+ *
+ * @param  divEn: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    if (divEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set audio ADC clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x3F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set audio SOLO clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  div: divider
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_SOLO_CLK(uint8_t enable, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0xFF));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_SOLO_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_SOLO_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_SOLO_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_SOLO_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth rx clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+    }
+    BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth tx clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+    }
+    BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth ref clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+    }
+    BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set eth ref clock select
+ *
+ * @param  clkSel: clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_ETH_REF_CLK_OUT_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ETH_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_ETH_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set CAM clock
+ *
+ * @param  enable: Enable or disable CAM clock
+ * @param  clkSel: CAM clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set SDH clock
+ *
+ * @param  enable: Enable or disable
+ * @param  clkSel: SDH clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_SDH_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x7));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable or Disable Host config 0x6[3] to reset System
+ *
+ * @param  enable: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Config_SDIO_Host_Reset_System(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDIO_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SYS_RST_SD_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SYS_RST_SD_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SDIO_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable or Disable Host config 0x6[3] to reset SDU sdu_rst_ sd_rst_
+ *
+ * @param  enable: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Config_SDIO_Host_Reset_SDU(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDIO_CFG0);
+    if (enable) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDU_RST_SD_DIS);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SD_RST_SD_DIS);
+    } else {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDU_RST_SD_DIS);
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SD_RST_SD_DIS);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SDIO_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable or Disable Host config 0x7[4] to interrupt CPU
+ *
+ * @param  enable: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Config_SDIO_Host_Interrupt_CPU(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDIO_CFG0);
+    if (enable) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDIO_INT_SYS_DIS);
+    } else {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDIO_INT_SYS_DIS);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SDIO_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap UART gpio pins sig function
+ *
+ * @param  group: UART swap set group
+ * @param  swap: swap or no swap
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap)
+{
+    uint32_t tmpVal = 0;
+    uint32_t tmpVal2 = 0;
+
+    CHECK_PARAM(IS_GLB_UART_SIG_SWAP_GRP_TYPE(group));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET);
+    if (swap) {
+        tmpVal2 |= (1 << group);
+    } else {
+        tmpVal2 &= ~(1 << group);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, tmpVal2);
+    BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap SPI0 MOSI with MISO
+ *
+ * @param  newState: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);
+    BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select SPI_0 act mode
+ *
+ * @param  mod: SPI work mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);
+    BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set flash io parameter
+ *
+ * @param  selEmbedded: Select embedded flash pin
+ * @param  swapIo3Io0: Select embedded flash swap io0 with io3
+ * @param  swapIo2Cs: Select embedded flash swap cs with io2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_SFlash_IO_PARM(uint8_t selEmbedded, uint8_t swapIo3Io0, uint8_t swapIo2Cs)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+    if (selEmbedded) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
+        if (swapIo3Io0) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+        } else {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+        }
+        if (swapIo2Cs) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_2_CS);
+        } else {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_2_CS);
+        }
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SEL_EMBEDDED_SFLASH);
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_3_IO_0);
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH_IO_2_CS);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+    if (selEmbedded) {
+        GLB_Embedded_Flash_Pad_Enable(swapIo2Cs);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set sflash2 io parameter
+ *
+ * @param  swapIo3Io0: Select embedded flash swap io0 with io3
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_SFlash2_IO_PARM(uint8_t swapIo3Io0)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
+    if (swapIo3Io0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SWAP_SFLASH2_IO_3_IO_0);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SWAP_SFLASH2_IO_3_IO_0);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  clear reset recorder
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Clr_Reset_Reason(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_RESET_STS0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CLR_TOP_RESET_RECORDER);
+    BL_WR_REG(GLB_BASE, GLB_RESET_STS0, tmpVal);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_RESET_STS0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CLR_TOP_RESET_RECORDER);
+    BL_WR_REG(GLB_BASE, GLB_RESET_STS0, tmpVal);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_RESET_STS0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CLR_TOP_RESET_RECORDER);
+    BL_WR_REG(GLB_BASE, GLB_RESET_STS0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get reset reason
+ *
+ * @param  reason: store reset reason
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Get_Reset_Reason(GLB_RESET_RECORD_Type *reason)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((NULL != reason));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_RESET_STS0);
+    reason->reset_recorder_ana_powb = (tmpVal >> 0) & 0x1;
+    reason->reset_recorder_ext_rst_n = (tmpVal >> 1) & 0x1;
+    reason->reset_recorder_pds_reset = (tmpVal >> 2) & 0x1;
+    reason->reset_recorder_wdt_rst_n = (tmpVal >> 3) & 0x1;
+    reason->reset_recorder_cpu_porst_n = (tmpVal >> 4) & 0x1;
+    reason->reset_recorder_sys_reset_n = (tmpVal >> 5) & 0x1;
+    reason->reset_recorder_cpu_sys_rstreq_n = (tmpVal >> 6) & 0x1;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  software reset
+ *
+ * @param  swrst: reset num
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst)
+{
+    uint32_t tmpVal = 0;
+    uint32_t bit = 0;
+    uint32_t regAddr = 0;
+
+    CHECK_PARAM(IS_GLB_AHB_MCU_SW_TYPE(swrst));
+
+    if (swrst < 32) {
+        bit = swrst;
+        regAddr = GLB_BASE + GLB_SWRST_CFG0_OFFSET;
+    } else if (swrst < 64) {
+        bit = swrst - 32;
+        regAddr = GLB_BASE + GLB_SWRST_CFG1_OFFSET;
+    } else if (swrst < 96) {
+        bit = swrst - 64;
+        regAddr = GLB_BASE + GLB_SWRST_CFG2_OFFSET;
+    }
+
+    tmpVal = BL_RD_WORD(regAddr);
+    tmpVal &= ~(1 << bit);
+    BL_WR_WORD(regAddr, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_WORD(regAddr);
+    tmpVal |= (1 << bit);
+    BL_WR_WORD(regAddr, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_WORD(regAddr);
+    tmpVal &= ~(1 << bit);
+    BL_WR_WORD(regAddr, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  dis reset
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  disrst: disrst macro
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Disrst_Set(uint8_t enable, GLB_DISRST_Type disrst)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DISRST_TYPE(disrst));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG3);
+    if (enable) {
+        tmpVal |= (1 << disrst);
+    } else {
+        tmpVal &= ~(1 << disrst);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get first 1 from u64, then clear it
+ *
+ * @param  val: target value
+ * @param  bit: first 1 in bit
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit)
+{
+    if (!*val) {
+        return ERROR;
+    }
+
+    for (uint8_t i = 0; i < 64; i++) {
+        if ((*val) & ((uint64_t)1 << i)) {
+            *bit = i;
+            (*val) &= ~((uint64_t)1 << i);
+            break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  hold IPs clock
+ *
+ * @param  ips: GLB_AHB_CLOCK_CPU | GLB_AHB_CLOCK_RSVD | ...... (not GLB_AHB_CLOCK_IP_xxx)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t bitfield = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    while (ips) {
+        if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+            switch (bitfield) {
+                case GLB_AHB_CLOCK_IP_CPU:
+                    tmpValCfg0 &= ~(1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_RSVD:
+                    tmpValCfg0 &= ~(1 << 1);
+                    break;
+                case GLB_AHB_CLOCK_IP_SEC:
+                    tmpValCfg0 &= ~(1 << 2);
+                    tmpValCfg1 &= ~(1 << 3);
+                    tmpValCfg1 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_0:
+                    tmpValCfg0 &= ~(1 << 3);
+                    tmpValCfg1 &= ~(1 << 12);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_1:
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_2:
+                    break;
+                case GLB_AHB_CLOCK_IP_CCI:
+                    tmpValCfg0 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_RF_TOP:
+                    break;
+                case GLB_AHB_CLOCK_IP_GPIP:
+                    tmpValCfg1 &= ~(1 << 2);
+                    break;
+                case GLB_AHB_CLOCK_IP_TZC:
+                    tmpValCfg1 &= ~(1 << 5);
+                    break;
+                case GLB_AHB_CLOCK_IP_EF_CTRL:
+                    tmpValCfg1 &= ~(1 << 7);
+                    break;
+                case GLB_AHB_CLOCK_IP_SF_CTRL:
+                    tmpValCfg1 &= ~(1 << 11);
+                    break;
+                case GLB_AHB_CLOCK_IP_EMAC:
+                    tmpValCfg2 &= ~(1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART0:
+                    tmpValCfg1 &= ~(1 << 16);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART1:
+                    tmpValCfg1 &= ~(1 << 17);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART2:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART3:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART4:
+                    break;
+                case GLB_AHB_CLOCK_IP_SPI:
+                    tmpValCfg1 &= ~(1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C:
+                    tmpValCfg1 &= ~(1 << 19);
+                    break;
+                case GLB_AHB_CLOCK_IP_PWM:
+                    tmpValCfg1 &= ~(1 << 20);
+                    break;
+                case GLB_AHB_CLOCK_IP_TIMER:
+                    tmpValCfg1 &= ~(1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_IR:
+                    tmpValCfg1 &= ~(1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_CHECKSUM:
+                    tmpValCfg1 &= ~(1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_QDEC:
+                    break;
+                case GLB_AHB_CLOCK_IP_KYS:
+                    break;
+                case GLB_AHB_CLOCK_IP_I2S:
+                    tmpValCfg1 &= ~(1 << 27);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB11:
+                    break;
+                case GLB_AHB_CLOCK_IP_CAM:
+                    break;
+                case GLB_AHB_CLOCK_IP_MJPEG:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                    tmpValCfg2 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_EMI_MISC:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                    tmpValCfg2 &= ~(1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB20_SDU:
+                    tmpValCfg1 &= ~(1 << 13);
+                    break;
+                case GLB_AHB_CLOCK_IP_MIX2:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUDIO:
+                    tmpValCfg2 &= ~(1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_SDH:
+                    tmpValCfg2 &= ~(1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C1:
+                    tmpValCfg1 &= ~(1 << 25);
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_PHY:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:
+                    break;
+                case GLB_AHB_CLOCK_IP_LZ4:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUPDM:
+                    break;
+                case GLB_AHB_CLOCK_IP_GAUGE:
+                    break;
+                case GLB_AHB_CLOCK_IP_DBI:
+                    tmpValCfg1 &= ~(1 << 24);
+                    break;
+                case GLB_AHB_CLOCK_IP_PEC:
+                    tmpValCfg2 &= ~(1 << 25);
+                    break;
+                case GLB_AHB_CLOCK_IP_ISO11898:
+                    tmpValCfg1 &= ~(1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_AUSOLO_TOP:
+                    tmpValCfg1 &= ~(1 << 28);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_GPIO:
+                    tmpValCfg1 &= ~(1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_MM_MISC:
+                    tmpValCfg2 &= ~(1 << 16);
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  release IPs clock
+ *
+ * @param  ips: GLB_AHB_CLOCK_CPU | GLB_AHB_CLOCK_RSVD | ...... (not GLB_AHB_CLOCK_IP_xxx)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t bitfield = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    while (ips) {
+        if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+            switch (bitfield) {
+                case GLB_AHB_CLOCK_IP_CPU:
+                    tmpValCfg0 |= (1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_RSVD:
+                    tmpValCfg0 |= (1 << 1);
+                    break;
+                case GLB_AHB_CLOCK_IP_SEC:
+                    tmpValCfg0 |= (1 << 2);
+                    tmpValCfg1 |= (1 << 3);
+                    tmpValCfg1 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_0:
+                    tmpValCfg0 |= (1 << 3);
+                    tmpValCfg1 |= (1 << 12);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_1:
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_2:
+                    break;
+                case GLB_AHB_CLOCK_IP_CCI:
+                    tmpValCfg0 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_RF_TOP:
+                    break;
+                case GLB_AHB_CLOCK_IP_GPIP:
+                    tmpValCfg1 |= (1 << 2);
+                    break;
+                case GLB_AHB_CLOCK_IP_TZC:
+                    tmpValCfg1 |= (1 << 5);
+                    break;
+                case GLB_AHB_CLOCK_IP_EF_CTRL:
+                    tmpValCfg1 |= (1 << 7);
+                    break;
+                case GLB_AHB_CLOCK_IP_SF_CTRL:
+                    tmpValCfg1 |= (1 << 11);
+                    break;
+                case GLB_AHB_CLOCK_IP_EMAC:
+                    tmpValCfg2 |= (1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART0:
+                    tmpValCfg1 |= (1 << 16);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART1:
+                    tmpValCfg1 |= (1 << 17);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART2:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART3:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART4:
+                    break;
+                case GLB_AHB_CLOCK_IP_SPI:
+                    tmpValCfg1 |= (1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C:
+                    tmpValCfg1 |= (1 << 19);
+                    break;
+                case GLB_AHB_CLOCK_IP_PWM:
+                    tmpValCfg1 |= (1 << 20);
+                    break;
+                case GLB_AHB_CLOCK_IP_TIMER:
+                    tmpValCfg1 |= (1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_IR:
+                    tmpValCfg1 |= (1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_CHECKSUM:
+                    tmpValCfg1 |= (1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_QDEC:
+                    break;
+                case GLB_AHB_CLOCK_IP_KYS:
+                    break;
+                case GLB_AHB_CLOCK_IP_I2S:
+                    tmpValCfg1 |= (1 << 27);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB11:
+                    break;
+                case GLB_AHB_CLOCK_IP_CAM:
+                    break;
+                case GLB_AHB_CLOCK_IP_MJPEG:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                    tmpValCfg2 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_EMI_MISC:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                    tmpValCfg2 |= (1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB20_SDU:
+                    tmpValCfg1 |= (1 << 13);
+                    break;
+                case GLB_AHB_CLOCK_IP_MIX2:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUDIO:
+                    tmpValCfg2 |= (1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_SDH:
+                    tmpValCfg2 |= (1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C1:
+                    tmpValCfg1 |= (1 << 25);
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_PHY:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_MAC_PHY:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_PLATFORM:
+                    break;
+                case GLB_AHB_CLOCK_IP_LZ4:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUPDM:
+                    break;
+                case GLB_AHB_CLOCK_IP_GAUGE:
+                    break;
+                case GLB_AHB_CLOCK_IP_DBI:
+                    tmpValCfg1 |= (1 << 24);
+                    break;
+                case GLB_AHB_CLOCK_IP_PEC:
+                    tmpValCfg2 |= (1 << 25);
+                    break;
+                case GLB_AHB_CLOCK_IP_ISO11898:
+                    tmpValCfg1 |= (1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_AUSOLO_TOP:
+                    tmpValCfg1 |= (1 << 28);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_GPIO:
+                    tmpValCfg1 |= (1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_MM_MISC:
+                    tmpValCfg2 |= (1 << 16);
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  gate pll clock cgen
+ *
+ * @param  clk: pll clock cgen
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);
+    tmpVal &= (~(1 << clk));
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  gate pll clock cgen
+ *
+ * @param  clk: pll clock cgen
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PLL_CGEN_TYPE(clk));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG3);
+    tmpVal |= (1 << clk);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select PKA clock source
+ *
+ * @param  clkSel: PKA clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  mcu system part reset
+ *
+ * @param  sysPart: mcu reset part
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_MCU_SW_SYSTEM_TYPE(sysPart));
+
+    /* reset=0 */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal &= ~(1 << sysPart);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+    BL_DRV_DUMMY;
+    /* reset=1 */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal |= (1 << sysPart);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+    BL_DRV_DUMMY;
+    /* reset=1 */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal &= ~(1 << sysPart);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Software system reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)
+{
+    uint32_t tmpVal;
+
+    /* Swicth MCU clock to RC32M, no divider */
+    HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+    HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+    GLB_Set_MCU_System_CLK_Div(0, 0);
+
+    /* reset M0/SYS(bus) */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        arch_delay_us(10);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Software CPU reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)
+{
+    uint32_t tmpVal;
+
+#if defined(DUAL_CORE)
+    GLB_CORE_ID_Type core = GLB_CORE_ID_INVALID;
+    /* Do reset */
+    core = GLB_Get_Core_Type();
+    switch (core) {
+        case GLB_CORE_ID_M0:
+#endif
+            /* Swicth MCU clock to RC32M, no divider */
+            HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+            HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+            GLB_Set_MCU_System_CLK_Div(0, 0);
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+            BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+            BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+            BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+#if defined(DUAL_CORE)
+            break;
+        default:
+            break;
+    }
+#endif
+
+    /* waiting for reset */
+    while (1) {
+        arch_delay_us(10);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Software power on reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)
+{
+    uint32_t tmpVal;
+
+    /* Swicth MCU clock to RC32M, no divider */
+    HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+    HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+    GLB_Set_MCU_System_CLK_Div(0, 0);
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        arch_delay_us(10);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set auto calc xtal type value
+ *
+ * @param  calcXtalType: auto calc xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_XTAL_TYPE(calcXtalType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);
+    tmpVal = tmpVal & 0xffff0000;
+    tmpVal |= GLB_AUTO_CALC_XTAL_FLAG_VALUE;
+    tmpVal |= calcXtalType;
+    BL_WR_REG(GLB_BASE, GLB_HW_RSV0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set auto calc xtal type value
+ *
+ * @param  calcXtalType: auto calc xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV0);
+    if ((tmpVal & GLB_AUTO_CALC_XTAL_FLAG_MASK) == GLB_AUTO_CALC_XTAL_FLAG_VALUE) {
+        *calcXtalType = (tmpVal & 0xff);
+        return SUCCESS;
+    } else {
+        *calcXtalType = 0;
+        return ERROR;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  set flash id value
+ *
+ * @param  idValue: flash id value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue)
+{
+    BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue | BFLB_FLASH_ID_VALID_FLAG));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get flash id value
+ *
+ * @param  None
+ *
+ * @return flash id
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1);
+    if ((tmpVal & BFLB_FLASH_ID_VALID_FLAG) != 0) {
+        return (tmpVal & BFLB_FLASH_ID_VALID_MASK);
+    }
+
+    return 0x00000000;
+}
+
+/****************************************************************************/ /**
+ * @brief  trim LDO18IO vout sel
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Trim_Ldo18ioVoutSel(void)
+{
+    Efuse_Ana_Ldo18ioVoutSel_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_Ldo18ioVoutSel_Trim(&trim);
+    if (trim.ldo18ioVoutSelEn) {
+        if (trim.ldo18ioVoutSelParity == EF_Ctrl_Get_Trim_Parity(trim.ldo18ioVoutSelAon, 4)) {
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18IO);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18IO_VOUT_SEL, trim.ldo18ioVoutSelAon);
+            BL_WR_REG(GLB_BASE, GLB_LDO18IO, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  trim LDO18IO bypass
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Trim_Ldo18ioBypass(void)
+{
+    Efuse_Ana_Ldo18ioBypass_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_Ldo18ioBypass_Trim(&trim);
+    if (trim.ldo18ioBypassEn) {
+        if (trim.ldo18ioBypassParity == EF_Ctrl_Get_Trim_Parity(trim.ldo18ioBypassAon, 1)) {
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18IO);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18IO_BYPASS, trim.ldo18ioBypassAon);
+            BL_WR_REG(GLB_BASE, GLB_LDO18IO, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  trim LDO18IO vout
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Trim_Ldo18ioVoutTrim(void)
+{
+    Efuse_Ana_Ldo18ioVoutTrim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_Ldo18ioVoutTrim_Trim(&trim);
+    if (trim.ldo18ioVoutTrimEn) {
+        if (trim.ldo18ioVoutTrimParity == EF_Ctrl_Get_Trim_Parity(trim.ldo18ioVoutTrimAon, 4)) {
+            tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO18IO);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO18IO_VOUT_TRIM, trim.ldo18ioVoutTrimAon);
+            BL_WR_REG(GLB_BASE, GLB_LDO18IO, tmpVal);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_ret value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_CFG0, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_ret value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_RET(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG0);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_slp value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_CFG1, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_slp value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_SLP(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG1);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_param value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_CFG2, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_parm value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_PARM(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_CFG2);
+}
+
+/****************************************************************************/ /**
+ * @brief  select EM type
+ *
+ * @param  emType: EM type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_EM_TYPE(emType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SRAM_CFG3);
+    switch (emType) {
+        case GLB_WRAM160KB_EM0KB:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00);
+            break;
+        case GLB_WRAM128KB_EM32KB:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);
+            break;
+        case GLB_WRAM96KB_EM64KB:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x0F);
+            break;
+        default:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x03);
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_SRAM_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set PSRAMB clock
+ *
+ * @param  enable: Enable or disable
+ * @param  clkSel: PSRAMB clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PSRAMB_CLK_Sel(uint8_t enable, GLB_PSRAMB_PLL_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PSRAMB_PLL_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PSRAMB_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PSRAMB_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PSRAMB_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set PSRAMB clock
+ *
+ * @param  slave: slave IP
+ * @param  enable: enable or disable clock
+ * @param  clkSel: clock selection
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_Slave_Grp_0_CLK(GLB_SLAVE_GRP_0_Type slave, uint8_t enable, GLB_SLAVE_GRP_0_CLK_SEL_Type clkSel, uint32_t div)
+{
+    uint32_t tmpVal;
+    uint32_t regAddr = GLB_BASE + glb_slave_grp_0_table[slave].clkOffSetAddr;
+    uint8_t enPos = glb_slave_grp_0_table[slave].clkEnPos;
+    uint8_t selPos = glb_slave_grp_0_table[slave].clkSelPos;
+    uint8_t divPos = glb_slave_grp_0_table[slave].clkDivPos;
+    uint8_t enLen = glb_slave_grp_0_table[slave].clkEnLen;
+    uint8_t selLen = glb_slave_grp_0_table[slave].clkSelLen;
+    uint8_t divLen = glb_slave_grp_0_table[slave].clkDivLen;
+
+    CHECK_PARAM(IS_GLB_SLAVE_GRP_0_TYPE(slave));
+
+    /* disable clock first */
+    if (enLen) {
+        tmpVal = BL_RD_BYTE(regAddr);
+        tmpVal &= ~(((1ULL << enLen) - 1) << enPos);
+        BL_WR_BYTE(regAddr, tmpVal);
+    }
+
+    /* set clock sel or div */
+    tmpVal = BL_RD_BYTE(regAddr);
+    if (selLen) {
+        tmpVal &= ~(((1ULL << selLen) - 1) << selPos);
+        tmpVal |= (((clkSel.clkSel) & ((1 << selLen) - 1)) << selPos);
+    }
+    if (divLen) {
+        tmpVal &= ~(((1ULL << divLen) - 1) << divPos);
+        tmpVal |= ((div & ((1 << divLen) - 1)) << divPos);
+    }
+    BL_WR_BYTE(regAddr, tmpVal);
+
+    /* enable clock */
+    if (enLen && enable) {
+        tmpVal = BL_RD_BYTE(regAddr);
+        tmpVal |= (((1ULL << enLen) - 1) << enPos);
+        BL_WR_BYTE(regAddr, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  reconfigure WIFIPLL clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type *pllCfgList)
+{
+    GLB_PLL_REF_CLK_Type refClk;
+
+    if (xtalType == GLB_XTAL_RC32M) {
+        refClk = GLB_PLL_REFCLK_RC32M;
+    } else {
+        refClk = GLB_PLL_REFCLK_XTAL;
+    }
+
+    GLB_Power_Off_WIFIPLL();
+    GLB_WIFIPLL_Ref_Clk_Sel(refClk);
+    GLB_Power_On_WIFIPLL(&(pllCfgList[xtalType]), 1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  reconfigure AUPLL clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type *pllCfgList)
+{
+    GLB_PLL_REF_CLK_Type refClk;
+
+    if (xtalType == GLB_XTAL_RC32M) {
+        refClk = GLB_PLL_REFCLK_RC32M;
+    } else {
+        refClk = GLB_PLL_REFCLK_XTAL;
+    }
+
+    GLB_Power_Off_AUPLL();
+    GLB_AUPLL_Ref_Clk_Sel(refClk);
+    GLB_Power_On_AUPLL(&(pllCfgList[xtalType]), 1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 384M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_384M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    /* we take 384M for CPU use,so set LDO to 1.2V*/
+    HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P20V);
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_384M);
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 400M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_400M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_400M);
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 451P58M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_451P58M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_451P58M);
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 491P52M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_491P52M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_491P52M);
+}
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb_gpio.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb_gpio.c
new file mode 100755
index 0000000000..54ecf47591
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_glb_gpio.c
@@ -0,0 +1,962 @@
+/**
+  ******************************************************************************
+  * @file    bl616_glb_gpio.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616_clock.h"
+#include "bl616_glb.h"
+#include "bl616_hbn.h"
+#include "bl616_pds.h"
+#include "bl616_glb_gpio.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB_GPIO
+ *  @{
+ */
+
+/** @defgroup  GLB_GPIO_Private_Macros
+ *  @{
+ */
+#define GLB_GPIO_INT0_NUM           (GLB_GPIO_PIN_MAX)
+#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
+
+/*@} end of group GLB_GPIO_Private_Macros */
+#define GLB_GPIO_TIMEOUT_COUNT (160 * 1000)
+/** @defgroup  GLB_GPIO_Private_Types
+ *  @{
+ */
+
+/*@} end of group GLB_GPIO_Private_Types */
+
+/** @defgroup  GLB_GPIO_Private_Variables
+ *  @{
+ */
+
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL };
+
+static intCallback_Type *ATTR_TCM_CONST_SECTION glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_ALL] = { NULL };
+#endif
+
+/*@} end of group GLB_GPIO_Private_Variables */
+
+/** @defgroup  GLB_GPIO_Global_Variables
+ *  @{
+ */
+
+/*@} end of group GLB_GPIO_Global_Variables */
+
+/** @defgroup  GLB_GPIO_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group GLB_GPIO_Private_Fun_Declaration */
+
+/** @defgroup  GLB_GPIO_Private_Functions
+ *  @{
+ */
+
+/*@} end of group GLB_GPIO_Private_Functions */
+
+/** @defgroup  GLB_GPIO_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  GPIO initialization
+ *
+ * @param  cfg: GPIO configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+    uint8_t gpioPin = cfg->gpioPin;
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    /* drive strength(drive) = 0  <=>  8.0mA  @ 3.3V */
+    /* drive strength(drive) = 1  <=>  9.6mA  @ 3.3V */
+    /* drive strength(drive) = 2  <=>  11.2mA @ 3.3V */
+    /* drive strength(drive) = 3  <=>  12.8mA @ 3.3V */
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    /* Disable output anyway*/
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    /* input/output, pull up/down, drive, smt, function */
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+    if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+        /* not analog mode */
+
+        if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+        } else {
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+        }
+
+        if (cfg->pullType == GPIO_PULL_UP) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+        } else if (cfg->pullType == GPIO_PULL_DOWN) {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+        } else {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+        }
+    } else {
+        /* analog mode */
+
+        /* clear ie && oe */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+
+        /* clear pu && pd */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_MODE, cfg->outputMode);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  init GPIO function in pin list
+ *
+ * @param  gpioFun: GPIO pin function
+ * @param  pinList: GPIO pin list
+ * @param  cnt: GPIO pin count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_0,
+        .gpioFun = (uint8_t)gpioFun,
+        .gpioMode = GPIO_MODE_AF,
+        .pullType = GPIO_PULL_UP,
+        .drive = 1,
+        .smtCtrl = 1
+    };
+
+    if (gpioFun == GPIO_FUN_ANALOG) {
+        gpioCfg.gpioMode = GPIO_MODE_ANALOG;
+    }
+
+    for (uint8_t i = 0; i < cnt; i++) {
+        gpioCfg.gpioPin = pinList[i];
+        GLB_GPIO_Init(&gpioCfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Embedded flash set input function enable
+ *
+ * @param  swapIo2Cs: Select embedded flash swap cs with io2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Embedded_Flash_Pad_Enable(uint8_t swapIo2Cs)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+    uint8_t gpioPin[4];
+    uint8_t i;
+
+    if (swapIo2Cs) {
+        gpioPin[0] = 37;
+        gpioPin[1] = 38;
+        gpioPin[2] = 36;
+        gpioPin[3] = 40;
+    } else {
+        gpioPin[0] = 37;
+        gpioPin[1] = 38;
+        gpioPin[2] = 39;
+        gpioPin[3] = 40;
+    }
+    for (i = 0; i < 4; i++) {
+        gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin[i] << 2);
+        tmpVal = BL_RD_WORD(gpioCfgAddress);
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+        BL_WR_WORD(gpioCfgAddress, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Input_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Output_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set High-Z
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    /* Disable output anyway*/
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    /* ie=0, oe=0, drive=0, smt=0, pu=1 (pull up), pd=0, func=swgpio */
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_OE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, 0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU); /* pull up */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, 0xB);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GPIO function
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO function
+ *
+*******************************************************************************/
+uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
+}
+
+/****************************************************************************/ /**
+ * @brief  Read GPIO
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO value
+ *
+*******************************************************************************/
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_I) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Write GPIO
+ *
+ * @param  gpioPin: GPIO type
+ * @param  val: GPIO value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+
+    if (val) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_O);
+    }
+
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  turn GPIO output high
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Set(GLB_GPIO_Type gpioPin)
+{
+    if (gpioPin < GLB_GPIO_PIN_32) {
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG138_OFFSET, 1 << gpioPin);
+    } else {
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG139_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  turn GPIO output low
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Clr(GLB_GPIO_Type gpioPin)
+{
+    if (gpioPin < GLB_GPIO_PIN_32) {
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG140_OFFSET, 1 << gpioPin);
+    } else {
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_CFG141_OFFSET, 1 << (gpioPin - GLB_GPIO_PIN_32));
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt initialization
+ *
+ * @param  intCfg: GPIO interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Int_Init(GLB_GPIO_INT_Cfg_Type *intCfg)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+    uint32_t gpioPin = intCfg->gpioPin;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MODE_SET, intCfg->trig);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intCfg->intMask);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intMask: GPIO interrupt MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_INT_MASK, intMask);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GLB GPIO interrupt status
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    return BL_GET_REG_BITS_VAL(BL_RD_WORD(gpioCfgAddress), GLB_GPIO_0_INT_STAT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear GLB GPIO interrupt status
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+    uint32_t gpioCfgAddress;
+    uint32_t tmpVal;
+
+    gpioCfgAddress = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpioPin << 2);
+
+    /* clr=1 */
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    /* clr=0 */
+    tmpVal = BL_RD_WORD(gpioCfgAddress);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_INT_CLR);
+    BL_WR_WORD(gpioCfgAddress, tmpVal);
+
+    return SUCCESS;
+}
+
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_FIFO_IRQHandler(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+    if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_END_MASK)) {
+        if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END] != NULL) {
+            glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_END]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FER_MASK)) {
+        if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER] != NULL) {
+            glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FER]();
+        }
+    }
+
+    if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) && !BL_IS_REG_BIT_SET(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK)) {
+        if (glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO] != NULL) {
+            glbGpioFifoCbfArra[GLB_GPIO_FIFO_INT_FIFO]();
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  GPIO INT0 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+BL_Err_Type GLB_GPIO_FIFO_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(GPIO_DMA_IRQn, GPIO_FIFO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler callback install
+ *
+ * @param  gpioPin: GPIO pin type
+ * @param  cbFun: callback function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
+{
+    if (gpioPin < GLB_GPIO_PIN_MAX) {
+        glbGpioInt0CbfArra[gpioPin] = cbFun;
+    }
+
+    return SUCCESS;
+}
+#endif
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type GLB_GPIO_Fifo_Callback_Install(GLB_GPIO_FIFO_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+
+    glbGpioFifoCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_INT0_IRQHandler(void)
+{
+    GLB_GPIO_Type gpioPin;
+    uint32_t timeOut = 0;
+
+    for (gpioPin = GLB_GPIO_PIN_0; gpioPin < GLB_GPIO_PIN_MAX; gpioPin++) {
+        if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
+            GLB_Clr_GPIO_IntStatus(gpioPin);
+
+            /* timeout check */
+            timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+
+            do {
+                timeOut--;
+            } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
+
+            if (!timeOut) {
+                //MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+            }
+
+            if (glbGpioInt0CbfArra[gpioPin] != NULL) {
+                /* Call the callback function */
+                glbGpioInt0CbfArra[gpioPin]();
+            }
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  GPIO fifo function initialization
+ *
+ * @param  cfg: GPIO fifo configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_Init(GLB_GPIO_FIFO_CFG_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code0Phase));
+    CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->code1Phase));
+    CHECK_PARAM(IS_GLB_GPIO_FIFO_PHASE_Type(cfg->latch));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_TX_EN, cfg->fifoDmaEnable);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_TX_FIFO_TH, cfg->fifoDmaThreshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_OUT_SEL_LATCH, cfg->latch);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_GPIO_DMA_PARK_VALUE, cfg->idle);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE0_HIGH_TIME, cfg->code0FirstTime);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE1_HIGH_TIME, cfg->code1FirstTime);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_CODE_TOTAL_TIME, cfg->codeTotalTime);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE0_HIGH, cfg->code0Phase);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CR_INVERT_CODE1_HIGH, cfg->code1Phase);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
+
+    GLB_GPIO_FIFO_IRQHandler_Install();
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Push data to GPIO fifo
+ *
+ * @param  data: the pointer of data buffer
+ * @param  len: the len of data buffer
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_Push(uint16_t *data, uint16_t len)
+{
+    uint32_t txLen = 0;
+    uint32_t timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
+
+    while (txLen < len) {
+        if (GLB_GPIO_Fifo_GetCount() > 0) {
+            BL_WR_REG(GLB_BASE, GLB_GPIO_CFG144, data[txLen++]);
+            timeoutCnt = GLB_GPIO_TIMEOUT_COUNT;
+        } else {
+            timeoutCnt--;
+
+            if (timeoutCnt == 0) {
+                return TIMEOUT;
+            }
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GPIO fifo available count
+ *
+ * @param  None
+ *
+ * @return The count of available count
+ *
+*******************************************************************************/
+uint32_t GLB_GPIO_Fifo_GetCount(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CNT);
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear GPIO fifo
+ *
+ * @param  None
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_Clear(void)
+{
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, BL_SET_REG_BIT(BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143), GLB_GPIO_TX_FIFO_CLR));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Mask or Unmask GPIO FIFO Interrupt
+ *
+ * @param  intType: interrupt type
+ * @param  intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_IntMask(GLB_GPIO_FIFO_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+    CHECK_PARAM(IS_BL_MASK_TYPE(intMask));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+    /* Mask or unmask certain or all interrupt */
+    if (MASK == intMask) {
+        switch (intType) {
+            case GLB_GPIO_FIFO_INT_FER:
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+                break;
+
+            case GLB_GPIO_FIFO_INT_FIFO:
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+                break;
+
+            case GLB_GPIO_FIFO_INT_END:
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+                break;
+
+            case GLB_GPIO_FIFO_INT_ALL:
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+                break;
+
+            default:
+                break;
+        }
+    } else {
+        switch (intType) {
+            case GLB_GPIO_FIFO_INT_FER:
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+                break;
+
+            case GLB_GPIO_FIFO_INT_FIFO:
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+                break;
+
+            case GLB_GPIO_FIFO_INT_END:
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+                break;
+
+            case GLB_GPIO_FIFO_INT_ALL:
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_END_MASK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FIFO_MASK);
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_FER_MASK);
+                break;
+
+            default:
+                break;
+        }
+    }
+
+    /* Write back */
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear GPIO fifo interrupt
+ *
+ * @param  intType: interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Fifo_IntClear(GLB_GPIO_FIFO_INT_Type intType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+    /* Clear certain or all interrupt */
+    switch (intType) {
+        case GLB_GPIO_FIFO_INT_FER:
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+            break;
+
+        case GLB_GPIO_FIFO_INT_FIFO:
+            //tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+            break;
+
+        case GLB_GPIO_FIFO_INT_END:
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
+            break;
+
+        case GLB_GPIO_FIFO_INT_ALL:
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_FIFO_CLR);
+            tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPIO_TX_END_CLR);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Write back */
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFG143, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GPIO fifo interrupt status
+ *
+ * @param  intType: interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_GPIO_Fifo_GetIntStatus(GLB_GPIO_FIFO_INT_Type intType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_GLB_GPIO_FIFO_INT_TYPE(intType));
+
+    /* Get certain or all interrupt status */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG143);
+
+    if (GLB_GPIO_FIFO_INT_ALL == intType) {
+        if (BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT) ||
+            BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT) ||
+            BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT)) {
+            return SET;
+        } else {
+            return RESET;
+        }
+    } else {
+        switch (intType) {
+            case GLB_GPIO_FIFO_INT_FER:
+                return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FER_INT);
+
+            case GLB_GPIO_FIFO_INT_FIFO:
+                return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_FIFO_INT);
+
+            case GLB_GPIO_FIFO_INT_END:
+                return BL_IS_REG_BIT_SET(tmpVal, GLB_R_GPIO_TX_END_INT);
+
+            default:
+                return RESET;
+        }
+    }
+}
+BL_Err_Type GLB_GPIO_Fifo_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
+
+    return SUCCESS;
+}
+BL_Err_Type GLB_GPIO_Fifo_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFG142);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CR_GPIO_TX_EN);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFG142, tmpVal);
+
+    return SUCCESS;
+}
+
+/*@} end of group GLB_GPIO_Public_Functions */
+
+/*@} end of group GLB_GPIO */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c
new file mode 100755
index 0000000000..a255387421
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_hbn.c
@@ -0,0 +1,2216 @@
+/**
+  ******************************************************************************
+  * @file    bl616_hbn.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616_hbn.h"
+#include "bl616_acomp.h"
+#include "bl616_glb.h"
+#include "bl616_xip_sflash.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Private_Macros
+ *  @{
+ */
+#define HBN_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group HBN_Private_Macros */
+
+/** @defgroup  HBN_Private_Types
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Types */
+
+/** @defgroup  HBN_Private_Variables
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_INT_MAX] = { NULL };
+static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_INT_MAX] = { NULL };
+#endif
+
+/*@} end of group HBN_Private_Variables */
+
+/** @defgroup  HBN_Global_Variables
+ *  @{
+ */
+
+/*@} end of group HBN_Global_Variables */
+
+/** @defgroup  HBN_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Fun_Declaration */
+
+/** @defgroup  HBN_Private_Functions
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Functions */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enter HBN
+ *
+ * @param  cfg: HBN APP Config
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
+{
+#ifndef BOOTROM
+    uint32_t valLow = 0, valHigh = 0;
+    uint64_t val;
+
+    if (cfg->useXtal32k) {
+        HBN_32K_Sel(HBN_32K_XTAL);
+    } else {
+        HBN_32K_Sel(HBN_32K_RC);
+        HBN_Power_Off_Xtal_32K();
+    }
+
+    /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
+    HBN_Hw_Pu_Pd_Cfg(DISABLE);
+
+    HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));
+    if (cfg->gpioWakeupSrc != 0) {
+        HBN_GPIO_INT_Enable(cfg->gpioTrigType);
+    }
+
+    /* HBN RTC config and enable */
+    HBN_Clear_RTC_Counter();
+    if (cfg->sleepTime != 0) {
+        HBN_Get_RTC_Timer_Val(&valLow, &valHigh);
+        val = valLow + ((uint64_t)valHigh << 32);
+        val += cfg->sleepTime;
+        HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);
+        HBN_Enable_RTC_Counter();
+    }
+
+    HBN_Power_Down_Flash(cfg->flashCfg);
+
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
+
+    HBN_Enable(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel, cfg->dcdcPuSeq);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  power down and switch clock
+ *
+ * @param  flashCfg: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg)
+{
+    SPI_Flash_Cfg_Type bhFlashCfg;
+
+    if (flashCfg == NULL) {
+        L1C_DCache_Invalid_By_Addr(BL616_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type));
+        XIP_SFlash_Read_Via_Cache_Need_Lock(BL616_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg), sizeof(SPI_Flash_Cfg_Type));
+        L1C_DCache_Invalid_By_Addr(BL616_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type));
+
+        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+        SFlash_Reset_Continue_Read(&bhFlashCfg);
+    } else {
+        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
+        SFlash_Reset_Continue_Read(flashCfg);
+    }
+
+    SFlash_Powerdown();
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN mode
+ *
+ * @param  aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to
+ *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param  ldoLevel: LDO volatge level
+ * @param  hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+    CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+    /* Setting from guide */
+    /* HBN_SRAM Retion */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    /* AON GPIO IE */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    /* HBN mode LDO level */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* power on dcdc18 sequence  */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    if (dcdcPuSeq) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);
+    }
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Select RC32M */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbnLevel) {
+        case HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            break;
+
+        case HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            break;
+
+        default:
+            break;
+    }
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        arch_delay_ms(1000);
+    }
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  Reset HBN mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Reset HBN mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select GPADC clk source
+ *
+ * @param  clkSel: GPADC clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_GPADC_CLK_Sel(HBN_GPADC_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_GPADC_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS, clkSel);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Enable(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Disable(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Config HBN PIR interrupt
+ *
+ * @param  pirIntCfg: HBN PIR interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+    uint32_t bit4 = 0;
+    uint32_t bit5 = 0;
+    uint32_t bitVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    /* low trigger interrupt */
+    if (pirIntCfg->lowIntEn == ENABLE) {
+        bit5 = 0;
+    } else {
+        bit5 = 1;
+    }
+
+    /* high trigger interrupt */
+    if (pirIntCfg->highIntEn == ENABLE) {
+        bit4 = 0;
+    } else {
+        bit4 = 1;
+    }
+
+    bitVal = bit4 | (bit5 << 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR low pass filter
+ *
+ * @param  lpf: HBN PIR low pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR high pass filter
+ *
+ * @param  hpf: HBN PIR high pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR threshold value
+ *
+ * @param  threshold: HBN PIR threshold value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM((threshold <= 0x3FFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR threshold value
+ *
+ * @param  None
+ *
+ * @return HBN PIR threshold value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Threshold(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR interval value
+ *
+ * @param  interval: HBN PIR interval value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM((interval <= 0xFFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR interval value
+ *
+ * @param  None
+ *
+ * @return HBN PIR interval value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Interval(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL);
+}
+
+/****************************************************************************/ /**
+ * @brief  get HBN bod out state
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_BOD_OUT_State(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_BOR_CFG), HBN_R_BOD_OUT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN bod config
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset
+ * @param  threshold: bod threshold
+ * @param  mode: bod work mode with por
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_BOD_THRES_TYPE(threshold));
+    CHECK_PARAM(IS_HBN_BOD_MODE_TYPE(mode));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 0);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, threshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_SEL, mode);
+    BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11aon voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11rt voltage out
+ *
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11soc voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11 all voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN select 32K
+ *
+ * @param  clkType: HBN 32k clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType));
+
+    HBN_Trim_RC32K();
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select uart clock source
+ *
+ * @param  clkSel: uart clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    if ((HBN_UART_CLK_MCU_BCLK == clkSel) || (HBN_UART_CLK_MUXPLL_160M == clkSel)) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL2, 0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel);
+    } else {
+        /* mcu_bclk as default */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL2, 1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, 0);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get xclk clock source Select
+ *
+ * @param  None
+ *
+ * @return xclk clock type selection
+ *
+*******************************************************************************/
+HBN_MCU_XCLK_Type ATTR_CLOCK_SECTION HBN_Get_MCU_XCLK_Sel(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    return (HBN_MCU_XCLK_Type)(tmpVal & 0x1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Select xclk clock source
+ *
+ * @param  xclk: xclk clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_Type xclk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_MCU_XCLK_TYPE(xclk));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+    switch (xclk) {
+        case HBN_MCU_XCLK_RC32M:
+            tmpVal2 &= (~(1 << 0));
+            break;
+        case HBN_MCU_XCLK_XTAL:
+            tmpVal2 |= (1 << 0);
+            break;
+        default:
+            break;
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get root clock selection
+ *
+ * @param  None
+ *
+ * @return root clock selection
+ *
+*******************************************************************************/
+HBN_MCU_ROOT_CLK_Type ATTR_CLOCK_SECTION HBN_Get_MCU_Root_CLK_Sel(void)
+{
+    uint32_t tmpVal = 0;
+    uint32_t rootClkSel = 0;
+
+    /* root_clock_select = hbn_root_clk_sel[1] */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    rootClkSel = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL) >> 1;
+    if (0 == rootClkSel) {
+        return HBN_MCU_ROOT_CLK_XCLK;
+    } else {
+        return HBN_MCU_ROOT_CLK_PLL;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Select root clk source
+ *
+ * @param  rootClk: root clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_Type rootClk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_MCU_ROOT_CLK_TYPE(rootClk));
+
+    /* root_clock_select = hbn_root_clk_sel[1] */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+    switch (rootClk) {
+        case HBN_MCU_ROOT_CLK_XCLK:
+            tmpVal2 &= 0x1; //[1]=0
+            break;
+        case HBN_MCU_ROOT_CLK_PLL:
+            tmpVal2 |= 0x2; //[1]=1
+            break;
+        default:
+            break;
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM sleep mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_HRAM_slp(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM retension mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_HRAM_Ret(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ * @note can't use GPIO16&17 after calling this function
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    /* Delay >1s */
+    arch_delay_us(1100);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ * @note can use GPIO16&17 after calling this function
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_XTAL32K_HIZ_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Keep RC32K On during rtc power domain off
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ * @note  Don't turn off rc32k, which move to RTC Domain
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Keep_On_RC32K(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off RC3K during rtc power domain off
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_Ldo33VoutTrim(void)
+{
+    Efuse_Ana_Ldo33VoutTrim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_Ldo33VoutTrim_Trim(&trim);
+    if (trim.ldo33VoutTrimAonEn) {
+        if (trim.ldo33VoutTrimAonParity == EF_Ctrl_Get_Trim_Parity(trim.ldo33VoutTrimAon, 4)) {
+            tmpVal = BL_RD_REG(HBN_BASE, HBN_VBAT_LDO);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO33_VOUT_TRIM_AON, trim.ldo33VoutTrimAon);
+            BL_WR_REG(HBN_BASE, HBN_VBAT_LDO, tmpVal);
+            arch_delay_us(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void)
+{
+    Efuse_Ana_RC32K_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32K_Trim(&trim);
+    if (trim.rc32kCodeFrExtEn) {
+        if (trim.rc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.rc32kCodeFrExt, 10)) {
+            tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.rc32kCodeFrExt);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN);
+            BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+            arch_delay_us(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN status flag
+ *
+ * @param  None
+ *
+ * @return HBN status flag value
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Status_Flag(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV0);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN status flag
+ *
+ * @param  flag: Status Flag
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV0, flag);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN wakeup address
+ *
+ * @param  None
+ *
+ * @return HBN wakeup address
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Wakeup_Addr(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN wakeup address
+ *
+ * @param  addr: HBN wakeup address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV1, addr);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get core reboot flag
+ *
+ * @param  None
+ *
+ * @return repower flag
+ *
+*******************************************************************************/
+uint8_t ATTR_TCM_SECTION HBN_Get_Core_Unhalt_Config(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {
+        return BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT);
+    }
+
+    return 0x00;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set core reboot flag
+ *
+ * @param  core: core ID
+ * @param  hcfg: reboot cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Core_Reboot_Config(uint8_t core, uint8_t hcfg)
+{
+    uint32_t tmpVal = 0;
+    uint8_t unhalt = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);
+    unhalt = BL_GET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT);
+    if (hcfg) {
+        unhalt |= (1 << core);
+    } else {
+        unhalt &= ~(1 << core);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_CORE_UNHALT, unhalt);
+    BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get user boot config
+ *
+ * @param  None
+ *
+ * @return user boot config
+ *
+*******************************************************************************/
+uint8_t HBN_Get_User_Boot_Config(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    if (HBN_RELEASE_CORE_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE)) {
+        return BL_GET_REG_BITS_VAL(tmpVal, HBN_USER_BOOT_SEL);
+    }
+
+    return 0x00;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set user boot config
+ *
+ * @param  ubCfg: user boot config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_User_Boot_Config(uint8_t ubCfg)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RELEASE_CORE, HBN_RELEASE_CORE_FLAG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_USER_BOOT_SEL, ubCfg);
+    BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get ldo18io power delay config
+ *
+ * @param  pwrOffDly: power off delay
+ * @param  pwrOnDly: power on delay
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Ldo18io_Power_Delay_Config(uint16_t *pwrOffDly, uint16_t *pwrOnDly)
+{
+    uint32_t tmpVal = 0;
+
+    if ((NULL == pwrOffDly) || (NULL == pwrOnDly)) {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    if (HBN_LDO18IO_POWER_DLY_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_LDO18IO_POWER_DLY_STS)) {
+        *pwrOffDly = BL_GET_REG_BITS_VAL(tmpVal, HBN_LDO18IO_POWER_OFF_DLY);
+        *pwrOnDly = BL_GET_REG_BITS_VAL(tmpVal, HBN_LDO18IO_POWER_ON_DLY);
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set ldo18io power delay config
+ *
+ * @param  pwrOffDly: power off delay
+ * @param  pwrOnDly: power on delay
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo18io_Power_Delay_Config(uint16_t pwrOffDly, uint16_t pwrOnDly)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO18IO_POWER_DLY_STS, HBN_LDO18IO_POWER_DLY_FLAG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO18IO_POWER_OFF_DLY, pwrOffDly);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO18IO_POWER_ON_DLY, pwrOnDly);
+    BL_WR_REG(HBN_BASE, HBN_RSV2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set Xtal type
+ *
+ * @param  xtalType:Xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Xtal_Type(uint8_t xtalType)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL_STS, HBN_XTAL_FLAG_VALUE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_XTAL_TYPE, xtalType);
+    BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Xtal type
+ *
+ * @param  xtalType:Xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Type(uint8_t *xtalType)
+{
+    uint32_t tmpVal = 0;
+
+    if (NULL == xtalType) {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    if (HBN_XTAL_FLAG_VALUE == BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_STS)) {
+        *xtalType = BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_TYPE);
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Xtal value
+ *
+ * @param  xtalVal:Xtal value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Value(uint32_t *xtalVal)
+{
+    uint32_t tmpVal = 0;
+    uint8_t xtalType = 0;
+
+    if (NULL == xtalVal) {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    if (HBN_XTAL_FLAG_VALUE == BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_STS)) {
+        xtalType = BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_TYPE);
+        switch (xtalType) {
+            case GLB_XTAL_NONE:
+                *xtalVal = 0;
+                break;
+            case GLB_XTAL_24M:
+                *xtalVal = 24000000;
+                break;
+            case GLB_XTAL_32M:
+                *xtalVal = 32000000;
+                break;
+            case GLB_XTAL_38P4M:
+                *xtalVal = 38400000;
+                break;
+            case GLB_XTAL_40M:
+                *xtalVal = 40000000;
+                break;
+            case GLB_XTAL_26M:
+                *xtalVal = 26000000;
+                break;
+            case GLB_XTAL_RC32M:
+                *xtalVal = 32000000;
+                break;
+            default:
+                *xtalVal = 0;
+                break;
+        }
+        return SUCCESS;
+    }
+
+    *xtalVal = 0;
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set Flash Power Delay
+ *
+ * @param  flashPwrDly:flash power delay
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Flash_Power_Delay(uint8_t flashPwrDly)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_POWER_STS, HBN_FLASH_POWER_DLY_FLAG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_POWER_DLY, flashPwrDly);
+    BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Power Delay
+ *
+ * @param  flashPwrDly:flash power delay
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Flash_Power_Delay(uint8_t *flashPwrDly)
+{
+    uint32_t tmpVal = 0;
+
+    if (NULL == flashPwrDly) {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    if (HBN_FLASH_POWER_DLY_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_FLASH_POWER_STS)) {
+        *flashPwrDly = BL_GET_REG_BITS_VAL(tmpVal, HBN_FLASH_POWER_DLY);
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN Gpio Keep
+ *
+ * @param  gpioKeep:HBN gpio keep reg cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Gpio_Keep(uint8_t gpioKeep)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_GPIO_KEEP_STS, HBN_GPIO_KEEP_FLAG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_GPIO_KEEP_PIN, gpioKeep);
+    BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN GPIO Keep bit
+ *
+ * @param  gpioKeep:HBN gpio keep reg cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Gpio_Keep(uint8_t *gpioKeep)
+{
+    uint32_t tmpVal = 0;
+
+    if (NULL == gpioKeep) {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    if (HBN_GPIO_KEEP_FLAG == BL_GET_REG_BITS_VAL(tmpVal, HBN_GPIO_KEEP_STS)) {
+        *gpioKeep = BL_GET_REG_BITS_VAL(tmpVal, HBN_GPIO_KEEP_PIN);
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear HBN GPIO Keep bit
+ *
+ * @param  gpioKeep:HBN gpio keep reg cfg
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Clear_Gpio_Keep(uint8_t gpioKeep)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_CR_GPIO_KEEP_EN, (gpioKeep & 0x7));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_GPIO_ISO_MODE, ((gpioKeep >> 3) & 0x1));
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set PDS Gpio Keep
+ *
+ * @param  gpioKeep:PDS gpio keep reg cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_PDS_Gpio_Keep(uint8_t gpioKeep)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_KEEP_STS, PDS_GPIO_KEEP_FLAG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_KEEP_PIN, gpioKeep);
+    BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get PDS GPIO Keep bit
+ *
+ * @param  gpioKeep:PDS gpio keep reg cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_PDS_Gpio_Keep(uint8_t *gpioKeep)
+{
+    uint32_t tmpVal = 0;
+
+    if (NULL == gpioKeep) {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    if (PDS_GPIO_KEEP_FLAG == BL_GET_REG_BITS_VAL(tmpVal, PDS_GPIO_KEEP_STS)) {
+        *gpioKeep = BL_GET_REG_BITS_VAL(tmpVal, PDS_GPIO_KEEP_PIN);
+        return SUCCESS;
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clear PDS GPIO Keep bit
+ *
+ * @param  gpioKeep:PDS gpio keep reg cfg
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Clear_PDS_Gpio_Keep(uint8_t gpioKeep)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL5);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_KEEP_EN, (gpioKeep & 0x7));
+    BL_WR_REG(PDS_BASE, PDS_CTL5, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_ISO_MODE, ((gpioKeep >> 3) & 0x1));
+    /* don't entry PDS */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_START_PS);
+    BL_WR_REG(PDS_BASE, PDS_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Clear_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Enable_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set RTC timer configuration
+ *
+ * @param  delay: RTC interrupt delay 32 clocks
+ * @param  compValLow: RTC interrupt commpare value low 32 bits
+ * @param  compValHigh: RTC interrupt commpare value high 32 bits
+ * @param  compMode: RTC interrupt commpare
+ *                   mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay));
+
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set interrupt delay option */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay);
+    /* Set RTC compare mode */
+    tmpVal |= (compMode << 1);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get RTC timer count value
+ *
+ * @param  valLow: RTC count value pointer for low 32 bits
+ * @param  valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+    uint32_t tmpVal;
+
+    /* Tigger RTC val read */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+
+    /* Read RTC val */
+    *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
+    *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN Re-Cal RC32K
+ *
+ * @param  expected_counter: Expected rtc counter
+ * @param  actual_counter: Actual rtc counter
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Recal_RC32K(int32_t expected_counter, int32_t actual_counter)
+{
+    int32_t tmpVal = 0;
+    int32_t current = 0;
+    int32_t delta = 0;
+
+    delta = actual_counter - expected_counter;
+
+    /* normalize to 1s count */
+    delta = (delta * 32768) / expected_counter;
+
+    if ((delta < 32) && (delta > -32)) {
+        return -1;
+    }
+    if (delta < -320) {
+        delta = -320;
+    } else if (delta > 320) {
+        delta = 320;
+    }
+
+    if (delta >= 64 || delta <= -64) {
+        delta = delta / 64;
+    } else {
+        delta = delta / 32;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+    current = BL_GET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT);
+    current += delta;
+    current &= ((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, current);
+    BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_INT(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable GPIO interrupt
+ *
+ * @param  gpioIntTrigType: HBN GPIO interrupt trigger type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable GPIO interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Disable(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT);
+
+    if (tmpVal & (1 << irqType)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get pin wakeup mode value
+ *
+ * @param  None
+ *
+ * @return HBN pin wakeup mode value
+ *
+*******************************************************************************/
+uint8_t HBN_Get_Pin_Wakeup_Mode(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE);
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_INT_TYPE(irqType));
+
+    /* set clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal |= (1 << irqType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    /* unset clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal &= (~(1 << irqType));
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN hardware pullup or pulldown configuration
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    }
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN wakeup pin mask configuration
+ *
+ * @param  maskVal: mask value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN aon pad ctrl configuration
+ *
+ * @param  aonPadCtl1: ctrl value 1
+ * @param  aonpadCtl2: ctrl value 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2)
+{
+#ifndef BOOTROM
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, aonPadCtl1);
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, aonPadCtl2);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN aon pad cfg configuration
+ *
+ * @param  aonPadHwCtrlEn: hw control aon pad enable
+ * @param  aonGpio: aon pad number
+ * @param  aonPadCfg: aon pad configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HBN_AON_PAD_CFG_Type *aonPadCfg)
+{
+    uint32_t tmpVal0;
+    uint32_t tmpVal1;
+    uint32_t enAonCtrlGpio;
+    uint32_t aonPadIeSmt;
+    uint32_t aonPadPu;
+    uint32_t aonPadPd;
+    uint32_t aonPadOe;
+
+    CHECK_PARAM(IS_HBN_AON_PAD_TYPE(aonGpio));
+
+    if (NULL == aonPadCfg) {
+        return ERROR;
+    }
+
+    /* hbn_pad_ctrl_0 */
+    tmpVal0 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+    enAonCtrlGpio = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO);
+    if (aonPadCfg->ctrlEn) {
+        enAonCtrlGpio |= (1 << aonGpio);
+    } else {
+        enAonCtrlGpio &= ~(1 << aonGpio);
+    }
+    tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_EN_AON_CTRL_GPIO, enAonCtrlGpio);
+    aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_PAD_IE_SMT);
+    if (aonPadCfg->ie) {
+        aonPadIeSmt |= (1 << aonGpio);
+    } else {
+        aonPadIeSmt &= ~(1 << aonGpio);
+    }
+    tmpVal0 = BL_SET_REG_BITS_VAL(tmpVal0, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal0);
+
+    /* hbn_pad_ctrl_1 */
+    tmpVal1 = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_1);
+    aonPadPu = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PU);
+    if (aonPadCfg->pullUp) {
+        aonPadPu |= (1 << aonGpio);
+    } else {
+        aonPadPu &= ~(1 << aonGpio);
+    }
+    tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PU, aonPadPu);
+    aonPadPd = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PD);
+    if (aonPadCfg->pullDown) {
+        aonPadPd |= (1 << aonGpio);
+    } else {
+        aonPadPd &= ~(1 << aonGpio);
+    }
+    tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_PD, aonPadPd);
+    aonPadOe = BL_GET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_OE);
+    if (aonPadCfg->oe) {
+        aonPadOe |= (1 << aonGpio);
+    } else {
+        aonPadOe &= ~(1 << aonGpio);
+    }
+    tmpVal1 = BL_SET_REG_BITS_VAL(tmpVal1, HBN_REG_AON_PAD_OE, aonPadOe);
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, tmpVal1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN Set AON_HW control aon pad or not
+ *
+ * @param  aonPadHwCtrlEn: hw control aon pad enable
+ * @param  aonGpio: aon pad number
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Cfg_Set(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+    uint32_t enAonCtrlGpio;
+
+    /* hbn_pad_ctrl_0 */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+    enAonCtrlGpio = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_EN_AON_CTRL_GPIO);
+
+    if (aonPadHwCtrlEn) {
+        enAonCtrlGpio |= (1 << aonGpio);
+    } else {
+        enAonCtrlGpio &= ~(1 << aonGpio);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_AON_CTRL_GPIO, enAonCtrlGpio);
+
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP interrupt
+ *
+ * @param  acompId: HBN Acomp ID
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompId));
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    if (acompId == AON_ACOMP0_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+        tmpVal2 = tmpVal2 | edge;
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    } else if (acompId == AON_ACOMP1_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+        tmpVal2 = tmpVal2 | edge;
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP interrupt
+ *
+ * @param  acompId: HBN Acomp ID
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompId));
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    if (acompId == (uint8_t)AON_ACOMP0_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+        tmpVal2 = tmpVal2 & (~edge);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    } else if (acompId == (uint8_t)AON_ACOMP1_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+        tmpVal2 = tmpVal2 & (~edge);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable BOD interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_BOD_IRQ(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable BOD interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_BOD_IRQ(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out0 install interrupt callback
+ *
+ * @param  intType: HBN out0 interrupt type
+ * @param  cbFun: HBN out0 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType));
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler);
+#endif
+
+    hbnInt0CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN out1 install interrupt callback
+ *
+ * @param  intType: HBN out1 interrupt type
+ * @param  cbFun: HBN out1 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType));
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler);
+#endif
+
+    hbnInt1CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN aon pad debbug pull config
+ *
+ * @param  puPdEn: Enable or disable aon pad pull down and pull up
+ * @param  ieSmtEn: Enable or disable aon pad IE and SMT
+ * @param  trigMode: trigger mode
+ * @param  maskVal: int mask
+ * @param  dlyEn: Enable or disable aon pad wakeup delay function
+ * @param  dlySec: aon pad wakeup delay sec 1 to 7
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));
+    CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(trigMode));
+    CHECK_PARAM((maskVal <= 0x3FF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, puPdEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, trigMode);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set Embedded Flash Pullup enabe or disable
+ *
+ * @param  cfg: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    if (cfg->enableBodInt) {
+        HBN_Enable_BOD_IRQ();
+    } else {
+        HBN_Disable_BOD_IRQ();
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, cfg->bodThreshold);
+    if (cfg->enablePorInBod) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOD_SEL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOD_SEL);
+    }
+
+    if (cfg->enableBod) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOD);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOD);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT0 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void)
+{
+    HBN_OUT0_INT_Type out0Int = HBN_OUT0_INT_GPIO16;
+
+    /* GPIO and RTC */
+    for (HBN_INT_Type gpioInt = HBN_INT_GPIO16; gpioInt <= HBN_INT_GPIO19; gpioInt++) {
+        if (SET == HBN_Get_INT_State(gpioInt)) {
+            HBN_Clear_IRQ(gpioInt);
+            switch (gpioInt) {
+                case HBN_INT_GPIO16:
+                    out0Int = HBN_OUT0_INT_GPIO16;
+                    break;
+                case HBN_INT_GPIO17:
+                    out0Int = HBN_OUT0_INT_GPIO17;
+                    break;
+                case HBN_INT_GPIO18:
+                    out0Int = HBN_OUT0_INT_GPIO18;
+                    break;
+                case HBN_INT_GPIO19:
+                    out0Int = HBN_OUT0_INT_GPIO19;
+                    break;
+                default:
+                    break;
+            }
+            if (hbnInt0CbfArra[out0Int] != NULL) {
+                hbnInt0CbfArra[out0Int]();
+            }
+        }
+    }
+    if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {
+        HBN_Clear_IRQ(HBN_INT_RTC);
+        if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_RTC]();
+        }
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT1 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT1_IRQHandler(void)
+{
+    /* PIR */
+    if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
+        HBN_Clear_IRQ(HBN_INT_PIR);
+        if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_PIR]();
+        }
+    }
+    /* BOD */
+    if (SET == HBN_Get_INT_State(HBN_INT_BOD)) {
+        HBN_Clear_IRQ(HBN_INT_BOD);
+        if (hbnInt1CbfArra[HBN_OUT1_INT_BOD] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_BOD]();
+        }
+    }
+    /* ACOMP0 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP0);
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0]();
+        }
+    }
+    /* ACOMP1 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP1);
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1]();
+        }
+    }
+}
+#endif
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_l1c.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_l1c.c
new file mode 100755
index 0000000000..c9917501df
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_l1c.c
@@ -0,0 +1,388 @@
+/**
+  ******************************************************************************
+  * @file    bl616_l1c.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616_l1c.h"
+#include "bl616_common.h"
+// #include "bl616_glb.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  L1C
+ *  @{
+ */
+
+/** @defgroup  L1C_Private_Macros
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Macros */
+
+/** @defgroup  L1C_Private_Types
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Types */
+
+/** @defgroup  L1C_Private_Variables
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Variables */
+
+/** @defgroup  L1C_Global_Variables
+ *  @{
+ */
+
+/*@} end of group L1C_Global_Variables */
+
+/** @defgroup  L1C_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Fun_Declaration */
+
+/** @defgroup  L1C_Private_Functions
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Functions */
+
+/** @defgroup  L1C_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enable I-Cache
+ *
+ * @param  wayDsiable: cache way disable config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Enable(uint8_t wayDsiable)
+{
+#ifndef __riscv_32e
+    csi_icache_enable();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable D-Cache
+ *
+ * @param  wayDsiable: cache way disable config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Enable(uint8_t wayDsiable)
+{
+#ifndef __riscv_32e
+    csi_dcache_enable();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable I-Cache
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Disable(void)
+{
+#ifndef __riscv_32e
+    csi_icache_disable();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable D-Cache
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Disable(void)
+{
+#ifndef __riscv_32e
+    csi_dcache_disable();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C D-Cache write set
+ *
+ * @param  wtEn: L1C write through enable
+ * @param  wbEn: L1C write back enable
+ * @param  waEn: L1C write allocate enable
+ *
+ * @return None
+ *
+*******************************************************************************/
+__WEAK
+void ATTR_TCM_SECTION L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
+{
+    return;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clean all D_Cache
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_All(void)
+{
+#ifndef __riscv_32e
+    csi_dcache_clean();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clean and invalid all D_Cache
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_All(void)
+{
+#ifndef __riscv_32e
+    csi_dcache_clean_invalid();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Invalid all I-Cache
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_All(void)
+{
+#ifndef __riscv_32e
+    csi_icache_invalid();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Invalid all D_Cache
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_All(void)
+{
+#ifndef __riscv_32e
+    csi_dcache_invalid();
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clean D-Cache according to address
+ *
+ * @param  addr: Address to clean
+ * @param  len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_By_Addr(uintptr_t addr, uint32_t len)
+{
+#ifndef __riscv_32e
+#ifdef CPU_D0
+    csi_dcache_clean_range((uintptr_t *)addr, len);
+#else
+    csi_dcache_clean_range((uint32_t *)(uintptr_t *)addr, len);
+#endif
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Clean and invalid D-Cache according to address
+ *
+ * @param  addr: Address to clean
+ * @param  len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Clean_Invalid_By_Addr(uintptr_t addr, uint32_t len)
+{
+#ifndef __riscv_32e
+#ifdef CPU_D0
+    csi_dcache_clean_invalid_range((uintptr_t *)addr, len);
+#else
+    csi_dcache_clean_invalid_range((uint32_t *)(uintptr_t *)addr, len);
+#endif
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Invalid I-Cache according to address
+ *
+ * @param  addr: Address to clean
+ * @param  len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_ICache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
+{
+    L1C_ICache_Invalid_All();
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Invalid D-Cache according to address
+ *
+ * @param  addr: Address to clean
+ * @param  len: Length to clean
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_DCache_Invalid_By_Addr(uintptr_t addr, uint32_t len)
+{
+#ifndef __riscv_32e
+#ifdef CPU_D0
+    csi_dcache_invalid_range((uintptr_t *)addr, len);
+#else
+    csi_dcache_invalid_range((uint32_t *)(uintptr_t *)addr, len);
+#endif
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  cache wrap
+ *
+ * @param  en: wrap enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(uint8_t en)
+{
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  cache wrap
+ *
+ * @param  core: cpu core
+ * @param  cacheSetting: cache setting
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Cache_Setting_By_ID(uint8_t core, L1C_CACHE_Cfg_Type *cacheSetting)
+{
+    (void)core;
+    (void)cacheSetting;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Judge addr is in cache range
+ *
+ * @param  addr: phyical addr
+ *
+ * @return 1 for addr is in cache range and 0 for not in cache range
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION L1C_Is_DCache_Range(uintptr_t addr)
+{
+    if(((addr>>16)&0xffff)>=0x62FC){
+        return 1;
+    }else{
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get None Cache address according to Cache address
+ *
+ * @param  addr: cache addr
+ *
+ * @return none cache addr
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION L1C_Get_None_Cache_Addr(uintptr_t addr)
+{
+    return (addr&0x0FFFFFFF)|0x20000000;
+}
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_efuse.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_efuse.c
new file mode 100755
index 0000000000..bf132e9829
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_efuse.c
@@ -0,0 +1,434 @@
+#include "bl616_glb.h"
+#include "bl616_mfg_efuse.h"
+#include "bflb_ef_ctrl.h"
+#include "bflb_efuse.h"
+
+static uint8_t rf_cal_slots = 3;
+extern void main(void);
+#define RF_CAL_SLOT_CFG_OFFSET (4 * 13)
+
+#define mfg_print printf
+
+uint8_t mfg_efuse_get_rf_cal_slots(void)
+{
+    return rf_cal_slots;
+}
+
+void mfg_efuse_set_rf_cal_slots(uint8_t slots)
+{
+    rf_cal_slots = slots;
+}
+
+static int mfg_efuse_get_empty_slot(char *name, int *slot, int32_t *last_val, uint8_t reload)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+    char buf[16] = { 0 };
+    int len = strlen(name);
+
+    *slot = -1;
+    *last_val = -1;
+    memcpy(buf, name, len);
+    buf[len + 1] = '\0';
+
+    if (rf_cal_slots >= 1) {
+        buf[len] = '0';
+        bflb_ef_ctrl_read_common_trim(NULL, buf, &trim, reload);
+        if (trim.empty) {
+            mfg_print("Empty slot:%d\r\n", 0);
+            *slot = 0;
+            return 0;
+        } else {
+            if (trim.en == 1 && trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+                *last_val = (int32_t)trim.value;
+            }
+        }
+    }
+    if (rf_cal_slots >= 2) {
+        buf[len] = '1';
+        bflb_ef_ctrl_read_common_trim(NULL, buf, &trim, reload);
+        if (trim.empty) {
+            mfg_print("Empty slot:%d\r\n", 1);
+            *slot = 1;
+            return 0;
+        } else {
+            if (trim.en == 1 && trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+                *last_val = (int32_t)trim.value;
+            }
+        }
+    }
+    if (rf_cal_slots >= 3) {
+        buf[len] = '2';
+        bflb_ef_ctrl_read_common_trim(NULL, buf, &trim, reload);
+        if (trim.empty) {
+            mfg_print("Empty slot:%d\r\n", 2);
+            *slot = 2;
+            return 0;
+        } else {
+            if (trim.en == 1 && trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+                *last_val = (int32_t)trim.value;
+            }
+        }
+    }
+
+    return -1;
+}
+
+uint8_t mfg_efuse_is_xtal_capcode_slot_empty(uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+
+    mfg_efuse_get_empty_slot("xtal", &slot, &last_val, reload);
+
+    if (slot == -1) {
+        return 0;
+    } else {
+        return 1;
+    }
+}
+
+int mfg_efuse_write_xtal_capcode_pre(uint8_t capcode, uint8_t program)
+{
+    int slot;
+    int32_t last_val;
+    char buf[16];
+
+    mfg_efuse_get_empty_slot("xtal", &slot, &last_val, 1);
+
+    if (slot == -1) {
+        return -1;
+    } else {
+        sprintf(buf, "xtal%d", slot);
+        bflb_ef_ctrl_write_common_trim(NULL, buf, capcode, program);
+        mfg_print("Write slot:%d\r\n", slot);
+        return 0;
+    }
+}
+
+int mfg_efuse_read_xtal_capcode(uint8_t *capcode, uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+
+    mfg_efuse_get_empty_slot("xtal", &slot, &last_val, reload);
+
+    if (last_val == -1) {
+        mfg_print("No written slot found\r\n");
+        return -1;
+    } else {
+        *capcode = (uint8_t)last_val;
+        return 0;
+    }
+}
+
+static void mfg_efuse_poweroffset_linear(int8_t pwr_offset[14], int8_t pwr_offset_tmp[3])
+{
+    int32_t step = 0;
+
+    memset(pwr_offset, 0, 14);
+
+    pwr_offset[0] = pwr_offset_tmp[0];
+
+    step = (pwr_offset_tmp[1] - pwr_offset_tmp[0]) * 100 / 6;
+    pwr_offset[1] = (step + 50) / 100 + pwr_offset_tmp[0];
+    pwr_offset[2] = (step * 2 + 50) / 100 + pwr_offset_tmp[0];
+    pwr_offset[3] = (step * 3 + 50) / 100 + pwr_offset_tmp[0];
+    pwr_offset[4] = (step * 4 + 50) / 100 + pwr_offset_tmp[0];
+    pwr_offset[5] = (step * 5 + 50) / 100 + pwr_offset_tmp[0];
+
+    pwr_offset[6] = pwr_offset_tmp[1];
+
+    step = (pwr_offset_tmp[2] - pwr_offset_tmp[1]) * 100 / 6;
+    pwr_offset[7] = (step + 50) / 100 + pwr_offset_tmp[1];
+    pwr_offset[8] = (step * 2 + 50) / 100 + pwr_offset_tmp[1];
+    pwr_offset[9] = (step * 3 + 50) / 100 + pwr_offset_tmp[1];
+    pwr_offset[10] = (step * 4 + 50) / 100 + pwr_offset_tmp[1];
+    pwr_offset[11] = (step * 5 + 50) / 100 + pwr_offset_tmp[1];
+
+    pwr_offset[12] = pwr_offset_tmp[2];
+
+    pwr_offset[13] = (step * 7 + 50) / 100 + pwr_offset_tmp[1];
+}
+
+uint8_t mfg_efuse_is_hp_poweroffset_slot_empty(uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+
+    mfg_efuse_get_empty_slot("hp_poffset", &slot, &last_val, reload);
+
+    if (slot == -1) {
+        return 0;
+    } else {
+        return 1;
+    }
+}
+
+int mfg_efuse_write_hp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program)
+{
+    int slot;
+    int32_t last_val;
+    char buf[32];
+    uint32_t cur_val = 0;
+
+    mfg_efuse_get_empty_slot("hp_poffset", &slot, &last_val, 1);
+
+    if (slot == -1) {
+        return -1;
+    } else {
+        sprintf(buf, "hp_poffset%d", slot);
+        cur_val = (pwr_offset[0] & 0x1f) | ((pwr_offset[6] & 0x1f) << 5) | ((pwr_offset[12] & 0x1f) << 10);
+        bflb_ef_ctrl_write_common_trim(NULL, buf, cur_val, program);
+        mfg_print("Write slot:%d\r\n", slot);
+        return 0;
+    }
+}
+
+void mfg_efuse_write_hp_poweroffset(void)
+{
+    // EF_Ctrl_Program_Direct(0, NULL, 0);
+    // while (SET == EF_Ctrl_Busy())
+    //     ;
+}
+
+int mfg_efuse_read_hp_poweroffset(int8_t pwr_offset[14], uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+    int8_t pwr_offset_tmp[3];
+    uint32_t tmp = 0, k;
+
+    mfg_efuse_get_empty_slot("hp_poffset", &slot, &last_val, reload);
+
+    if (last_val == -1) {
+        mfg_print("No written slot found\r\n");
+        return -1;
+    } else {
+        for (k = 0; k < 3; k++) {
+            tmp = (last_val >> (k * 5)) & 0x1f;
+
+            if (tmp >= 16) {
+                pwr_offset_tmp[k] = tmp - 32;
+            } else {
+                pwr_offset_tmp[k] = tmp;
+            }
+        }
+        mfg_efuse_poweroffset_linear(pwr_offset, pwr_offset_tmp);
+        return 0;
+    }
+}
+
+uint8_t mfg_efuse_is_lp_poweroffset_slot_empty(uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+
+    mfg_efuse_get_empty_slot("lp_poffset", &slot, &last_val, reload);
+
+    if (slot == -1) {
+        return 0;
+    } else {
+        return 1;
+    }
+}
+
+int mfg_efuse_write_lp_poweroffset_pre(int8_t pwr_offset[14], uint8_t program)
+{
+    int slot;
+    int32_t last_val;
+    char buf[32];
+    uint32_t cur_val = 0;
+
+    mfg_efuse_get_empty_slot("lp_poffset", &slot, &last_val, 1);
+
+    if (slot == -1) {
+        return -1;
+    } else {
+        sprintf(buf, "lp_poffset%d", slot);
+        cur_val = (pwr_offset[0] & 0x1f) | ((pwr_offset[6] & 0x1f) << 5) | ((pwr_offset[12] & 0x1f) << 10);
+        bflb_ef_ctrl_write_common_trim(NULL, buf, cur_val, program);
+        mfg_print("Write slot:%d\r\n", slot);
+        return 0;
+    }
+}
+
+void mfg_efuse_write_lp_poweroffset(void)
+{
+    bflb_ef_ctrl_write_direct(NULL, 0, NULL, 0, 1);
+}
+
+int mfg_efuse_read_lp_poweroffset(int8_t pwr_offset[14], uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+    int8_t pwr_offset_tmp[3];
+    uint32_t tmp = 0, k;
+
+    mfg_efuse_get_empty_slot("lp_poffset", &slot, &last_val, reload);
+
+    if (last_val == -1) {
+        mfg_print("No written slot found\r\n");
+        return -1;
+    } else {
+        for (k = 0; k < 3; k++) {
+            tmp = (last_val >> (k * 5)) & 0x1f;
+
+            if (tmp >= 16) {
+                pwr_offset_tmp[k] = tmp - 32;
+            } else {
+                pwr_offset_tmp[k] = tmp;
+            }
+        }
+        mfg_efuse_poweroffset_linear(pwr_offset, pwr_offset_tmp);
+        return 0;
+    }
+}
+
+uint8_t mfg_efuse_is_macaddr_slot_empty(uint8_t reload)
+{
+    uint8_t empty = 0;
+
+    if (rf_cal_slots >= 1 && bflb_efuse_is_mac_address_slot_empty(0, reload)) {
+        empty = 1;
+    } else if (rf_cal_slots >= 2 && bflb_efuse_is_mac_address_slot_empty(1, reload)) {
+        empty = 1;
+    } else if (rf_cal_slots >= 3 && bflb_efuse_is_mac_address_slot_empty(2, reload)) {
+        empty = 1;
+    } else {
+    }
+
+    return empty;
+}
+
+int8_t mfg_efuse_write_macaddr_pre(uint8_t mac[6], uint8_t program)
+{
+    int ret = -1;
+    uint8_t slot = 0xff;
+
+    if (rf_cal_slots >= 1 && bflb_efuse_is_mac_address_slot_empty(0, 1)) {
+        slot = 0;
+    } else if (rf_cal_slots >= 2 && bflb_efuse_is_mac_address_slot_empty(1, 1)) {
+        slot = 1;
+    } else if (rf_cal_slots >= 3 && bflb_efuse_is_mac_address_slot_empty(2, 1)) {
+        slot = 2;
+    } else {
+        mfg_print("No empty slot found\r\n");
+    }
+
+    if (slot != 0xff) {
+        ret = bflb_efuse_write_mac_address_opt(slot, mac, program);
+        mfg_print("Write slot:%d\r\n", slot);
+    }
+
+    if (ret == 0) {
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+void mfg_efuse_write_macaddr(void)
+{
+    bflb_ef_ctrl_write_direct(NULL, 0, NULL, 0, 1);
+}
+
+int8_t mfg_efuse_read_macaddr(uint8_t mac[6], uint8_t reload)
+{
+    uint8_t slot = 0xff;
+    int ret = -1;
+
+    if (rf_cal_slots >= 3 && (!bflb_efuse_is_mac_address_slot_empty(2, reload))) {
+        slot = 2;
+    } else if (rf_cal_slots >= 2 && (!bflb_efuse_is_mac_address_slot_empty(1, reload))) {
+        slot = 1;
+    } else if (rf_cal_slots >= 1 && (!bflb_efuse_is_mac_address_slot_empty(0, reload))) {
+        slot = 0;
+    }
+
+    if (slot != 0xff) {
+        mfg_print("Read slot:%d\r\n", slot);
+        ret = bflb_efuse_read_mac_address_opt(slot, mac, reload);
+    } else {
+        mfg_print("No written slot found\r\n");
+    }
+
+    if (ret == 0) {
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+uint8_t mfg_efuse_is_bz_poweroffset_slot_empty(uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+
+    mfg_efuse_get_empty_slot("bz_poffset", &slot, &last_val, reload);
+
+    if (slot == -1) {
+        return 0;
+    } else {
+        return 1;
+    }
+}
+
+int mfg_efuse_write_bz_poweroffset_pre(int8_t pwr_offset[5], uint8_t program)
+{
+    int slot;
+    int32_t last_val;
+    char buf[32];
+    uint32_t cur_val = 0;
+
+    mfg_efuse_get_empty_slot("bz_poffset", &slot, &last_val, 1);
+
+    if (slot == -1) {
+        return -1;
+    } else {
+        sprintf(buf, "bz_poffset%d", slot);
+        cur_val = (pwr_offset[0] & 0x1f) | ((pwr_offset[1] & 0x1f) << 5) | ((pwr_offset[2] & 0x1f) << 10) | ((pwr_offset[3] & 0x1f) << 15) | ((pwr_offset[4] & 0x1f) << 20);
+        bflb_ef_ctrl_write_common_trim(NULL, buf, cur_val, program);
+        mfg_print("Write slot:%d\r\n", slot);
+        return 0;
+    }
+}
+
+void mfg_efuse_write_bz_poweroffset(void)
+{
+    bflb_ef_ctrl_write_direct(NULL, 0, NULL, 0, 1);
+}
+
+int mfg_efuse_read_bz_poweroffset(int8_t pwr_offset[5], uint8_t reload)
+{
+    int slot;
+    int32_t last_val;
+    uint32_t tmp = 0, k;
+
+    mfg_efuse_get_empty_slot("bz_poffset", &slot, &last_val, reload);
+
+    if (last_val == -1) {
+        mfg_print("No written slot found\r\n");
+        return -1;
+    } else {
+        for (k = 0; k < 5; k++) {
+            tmp = (last_val >> (k * 5)) & 0x1f;
+
+            if (tmp >= 16) {
+                pwr_offset[k] = tmp - 32;
+            } else {
+                pwr_offset[k] = tmp;
+            }
+        }
+        return 0;
+    }
+}
+
+void mfg_efuse_program(uint32_t addr, uint32_t *pword, uint32_t countInword, uint32_t program)
+{
+    bflb_ef_ctrl_write_direct(NULL, addr, pword, countInword, program);
+}
+
+void mfg_efuse_read(uint32_t addr, uint32_t *pword, uint32_t countInword, uint8_t reload)
+{
+    bflb_ef_ctrl_read_direct(NULL, addr, pword, countInword, reload);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_flash.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_flash.c
new file mode 100755
index 0000000000..703bc82c34
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_flash.c
@@ -0,0 +1,116 @@
+#include "bl616_mfg_flash.h"
+
+//static rf_para_flash_t rf_para;
+//static uint32_t rf_para_addr = 0;
+//static spi_flash_cfg_type *pFlashCfg;
+
+//#define RF_PARA_MAGIC_FLAG      0x41504652
+#define RF_PARA_MAGIC_FLAG 0x41
+#define RF_PARA_VALID_FLAG 0x5A
+#define RF_PARA_PART_NAME  "rf_para"
+
+static int PtTable_Flash_Read(uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return 0;
+}
+
+int mfg_flash_init(spi_flash_cfg_type *flashCfg)
+{
+    PtTable_Flash_Read(0, NULL, 0);
+    return -1;
+}
+
+static int mfg_flash_program(void)
+{
+    return 0;
+}
+
+static int mfg_flash_read(void)
+{
+    return 0;
+}
+
+int mfg_flash_write_xtal_capcode_pre(uint8_t capcode, uint8_t program)
+{
+    mfg_flash_program();
+    return 0;
+}
+
+void mfg_flash_write_xtal_capcode(void)
+{
+    mfg_flash_program();
+}
+
+int mfg_flash_read_xtal_capcode(uint8_t *capcode, uint8_t reload)
+{
+    mfg_flash_read();
+    return 0;
+}
+
+int mfg_flash_write_hp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program)
+{
+    mfg_flash_program();
+    return 0;
+}
+
+void mfg_flash_write_hp_poweroffset(void)
+{
+    mfg_flash_program();
+}
+
+int mfg_flash_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
+{
+    mfg_flash_read();
+    return 0;
+}
+
+int mfg_flash_write_lp_poweroffset_pre(int8_t pwrOffset[14], uint8_t program)
+{
+    mfg_flash_program();
+    return 0;
+}
+
+void mfg_flash_write_lp_poweroffset(void)
+{
+    mfg_flash_program();
+}
+
+int mfg_flash_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
+{
+    mfg_flash_read();
+    return 0;
+}
+
+int mfg_flash_write_macaddr_pre(uint8_t mac[6], uint8_t program)
+{
+    mfg_flash_program();
+    return 0;
+}
+
+void mfg_flash_write_macaddr(void)
+{
+    mfg_flash_program();
+}
+
+int mfg_flash_read_macaddr(uint8_t mac[6], uint8_t reload)
+{
+    mfg_flash_read();
+    return 0;
+}
+
+int mfg_flash_write_bz_poweroffset_pre(int8_t pwrOffset[5], uint8_t program)
+{
+    mfg_flash_program();
+    return 0;
+}
+
+void mfg_flash_write_bz_poweroffset(void)
+{
+    mfg_flash_program();
+}
+
+int mfg_flash_read_bz_poweroffset(int8_t pwrOffset[5], uint8_t reload)
+{
+    mfg_flash_read();
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_media.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_media.c
new file mode 100755
index 0000000000..f39b81ec6b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_mfg_media.c
@@ -0,0 +1,396 @@
+#include "bl616_mfg_media.h"
+
+static uint8_t rf_para_on_flash = 0;
+
+int mfg_media_init_need_lock(spi_flash_cfg_type *flashCfg)
+{
+    if (0 == mfg_flash_init(flashCfg)) {
+        rf_para_on_flash = 1;
+    } else {
+        rf_para_on_flash = 0;
+    }
+    return 0;
+}
+
+int mfg_media_init_with_lock(spi_flash_cfg_type *flashCfg)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_init_need_lock(flashCfg);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+uint8_t mfg_media_is_xtal_capcode_slot_empty(uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return 1;
+    } else {
+        return mfg_efuse_is_xtal_capcode_slot_empty(reload);
+    }
+}
+
+int mfg_media_write_xtal_capcode_pre_need_lock(uint8_t capcode, uint8_t program)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_xtal_capcode_pre(capcode, program);
+    } else {
+        return mfg_efuse_write_xtal_capcode_pre(capcode, program);
+    }
+}
+
+int mfg_media_write_xtal_capcode_pre_with_lock(uint8_t capcode, uint8_t program)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_write_xtal_capcode_pre_need_lock(capcode, program);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+void mfg_media_write_xtal_capcode_need_lock(void)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_xtal_capcode();
+    } else {
+        return mfg_efuse_write_xtal_capcode();
+    }
+}
+
+void mfg_media_write_xtal_capcode_with_lock(void)
+{
+    uintptr_t flag;
+    flag = bflb_irq_save();
+    mfg_media_write_xtal_capcode_need_lock();
+    bflb_irq_restore(flag);
+}
+
+int mfg_media_read_xtal_capcode_need_lock(uint8_t *capcode, uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_read_xtal_capcode(capcode, reload);
+    } else {
+        return mfg_efuse_read_xtal_capcode(capcode, reload);
+    }
+}
+
+int mfg_media_read_xtal_capcode_with_lock(uint8_t *capcode, uint8_t reload)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_read_xtal_capcode_need_lock(capcode, reload);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+int mfg_media_read_xtal_capcode(uint8_t *capcode, uint8_t reload)
+{
+    return mfg_media_read_xtal_capcode_need_lock(capcode, reload);
+}
+
+uint8_t mfg_media_is_hp_poweroffset_slot_empty(uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return 1;
+    } else {
+        return mfg_efuse_is_hp_poweroffset_slot_empty(reload);
+    }
+}
+
+int mfg_media_write_hp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_hp_poweroffset_pre(pwrOffset, program);
+    } else {
+        return mfg_efuse_write_hp_poweroffset_pre(pwrOffset, program);
+    }
+}
+
+int mfg_media_write_hp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_write_hp_poweroffset_pre_need_lock(pwrOffset, program);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+void mfg_media_write_hp_poweroffset_need_lock(void)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_hp_poweroffset();
+    } else {
+        return mfg_efuse_write_hp_poweroffset();
+    }
+}
+
+void mfg_media_write_hp_poweroffset_with_lock(void)
+{
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    mfg_media_write_hp_poweroffset_need_lock();
+    bflb_irq_restore(flag);
+}
+
+int mfg_media_read_hp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_read_hp_poweroffset(pwrOffset, reload);
+    } else {
+        return mfg_efuse_read_hp_poweroffset(pwrOffset, reload);
+    }
+}
+
+int mfg_media_read_hp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_read_hp_poweroffset_need_lock(pwrOffset, reload);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+int mfg_media_read_hp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
+{
+    return mfg_media_read_hp_poweroffset_need_lock(pwrOffset, reload);
+}
+
+uint8_t mfg_media_is_lp_poweroffset_slot_empty(uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return 1;
+    } else {
+        return mfg_efuse_is_lp_poweroffset_slot_empty(reload);
+    }
+}
+
+int mfg_media_write_lp_poweroffset_pre_need_lock(int8_t pwrOffset[14], uint8_t program)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_lp_poweroffset_pre(pwrOffset, program);
+    } else {
+        return mfg_efuse_write_lp_poweroffset_pre(pwrOffset, program);
+    }
+}
+
+int mfg_media_write_lp_poweroffset_pre_with_lock(int8_t pwrOffset[14], uint8_t program)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_write_lp_poweroffset_pre_need_lock(pwrOffset, program);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+void mfg_media_write_lp_poweroffset_need_lock(void)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_lp_poweroffset();
+    } else {
+        return mfg_efuse_write_lp_poweroffset();
+    }
+}
+
+void mfg_media_write_lp_poweroffset_with_lock(void)
+{
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    mfg_media_write_lp_poweroffset_need_lock();
+    bflb_irq_restore(flag);
+}
+
+int mfg_media_read_lp_poweroffset_need_lock(int8_t pwrOffset[14], uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_read_lp_poweroffset(pwrOffset, reload);
+    } else {
+        return mfg_efuse_read_lp_poweroffset(pwrOffset, reload);
+    }
+}
+
+int mfg_media_read_lp_poweroffset_with_lock(int8_t pwrOffset[14], uint8_t reload)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_read_lp_poweroffset_need_lock(pwrOffset, reload);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+int mfg_media_read_lp_poweroffset(int8_t pwrOffset[14], uint8_t reload)
+{
+    return mfg_media_read_lp_poweroffset_need_lock(pwrOffset, reload);
+}
+
+uint8_t mfg_media_is_macaddr_slot_empty(uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return 1;
+    } else {
+        return mfg_efuse_is_macaddr_slot_empty(reload);
+    }
+}
+
+int mfg_media_write_macaddr_pre_need_lock(uint8_t mac[6], uint8_t program)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_macaddr_pre(mac, program);
+    } else {
+        return mfg_efuse_write_macaddr_pre(mac, program);
+    }
+}
+
+int mfg_media_write_macaddr_pre_with_lock(uint8_t mac[6], uint8_t program)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_write_macaddr_pre_need_lock(mac, program);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+void mfg_media_write_macaddr_need_lock(void)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_macaddr();
+    } else {
+        return mfg_efuse_write_macaddr();
+    }
+}
+
+void mfg_media_write_macaddr_with_lock(void)
+{
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    mfg_media_write_macaddr_need_lock();
+    bflb_irq_restore(flag);
+}
+
+int mfg_media_read_macaddr_need_lock(uint8_t mac[6], uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_read_macaddr(mac, reload);
+    } else {
+        return mfg_efuse_read_macaddr(mac, reload);
+    }
+}
+
+int mfg_media_read_macaddr_with_lock(uint8_t mac[6], uint8_t reload)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_read_macaddr_need_lock(mac, reload);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+int mfg_media_read_macaddr(uint8_t mac[6], uint8_t reload)
+{
+    return mfg_media_read_macaddr_need_lock(mac, reload);
+}
+
+
+
+uint8_t mfg_media_is_bz_poweroffset_slot_empty(uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return 1;
+    } else {
+        return mfg_efuse_is_bz_poweroffset_slot_empty(reload);
+    }
+}
+
+int mfg_media_write_bz_poweroffset_pre_need_lock(int8_t pwrOffset[5], uint8_t program)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_bz_poweroffset_pre(pwrOffset, program);
+    } else {
+        return mfg_efuse_write_bz_poweroffset_pre(pwrOffset, program);
+    }
+}
+
+int mfg_media_write_bz_poweroffset_pre_with_lock(int8_t pwrOffset[5], uint8_t program)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_write_bz_poweroffset_pre_need_lock(pwrOffset, program);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+void mfg_media_write_bz_poweroffset_need_lock(void)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_write_bz_poweroffset();
+    } else {
+        return mfg_efuse_write_bz_poweroffset();
+    }
+}
+
+void mfg_media_write_bz_poweroffset_with_lock(void)
+{
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    mfg_media_write_bz_poweroffset_need_lock();
+    bflb_irq_restore(flag);
+}
+
+int mfg_media_read_bz_poweroffset_need_lock(int8_t pwrOffset[5], uint8_t reload)
+{
+    if (rf_para_on_flash) {
+        return mfg_flash_read_bz_poweroffset(pwrOffset, reload);
+    } else {
+        return mfg_efuse_read_bz_poweroffset(pwrOffset, reload);
+    }
+}
+
+int mfg_media_read_bz_poweroffset_with_lock(int8_t pwrOffset[5], uint8_t reload)
+{
+    int ret;
+    uintptr_t flag;
+
+    flag = bflb_irq_save();
+    ret = mfg_media_read_bz_poweroffset_need_lock(pwrOffset, reload);
+    bflb_irq_restore(flag);
+
+    return ret;
+}
+
+int mfg_media_read_bz_poweroffset(int8_t pwrOffset[5], uint8_t reload)
+{
+    return mfg_media_read_bz_poweroffset_need_lock(pwrOffset, reload);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pds.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pds.c
new file mode 100755
index 0000000000..57853747be
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pds.c
@@ -0,0 +1,863 @@
+/**
+  ******************************************************************************
+  * @file    bl616_pds.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616.h"
+#include "bl616_pds.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Private_Macros
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Macros */
+
+/** @defgroup  PDS_Private_Types
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Types */
+
+/** @defgroup  PDS_Private_Variables
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX] = { NULL };
+#endif
+
+/*@} end of group PDS_Private_Variables */
+
+/** @defgroup  PDS_Global_Variables
+ *  @{
+ */
+
+/*@} end of group PDS_Global_Variables */
+
+/** @defgroup  PDS_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Fun_Declaration */
+
+/** @defgroup  PDS_Private_Functions
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Functions */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  set gpio pad pull type in pds
+ *
+ * @param  pad: gpio type
+ * @param  pu: power up
+ * @param  pd: power down
+ * @param  ie: Active IE (interrupt)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(PDS_GPIO_GROUP_SET_Type grp, uint8_t pu, uint8_t pd, uint8_t ie)
+{
+    uint32_t tmpVal;
+    uint32_t tmpValPu;
+    uint32_t tmpValPd;
+    uint32_t tmpValIe;
+
+    CHECK_PARAM(IS_PDS_GPIO_GROUP_SET_TYPE(grp));
+
+    /* pu/pd/ie config */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_I_SET);
+    tmpValPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET);
+    if (pu) {
+        tmpValPu |= (1 << grp);
+    } else {
+        tmpValPu &= ~(1 << grp);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PU_SET, tmpValPu);
+    tmpValPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET);
+    if (pd) {
+        tmpValPd |= (1 << grp);
+    } else {
+        tmpValPd &= ~(1 << grp);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_PD_SET, tmpValPd);
+    tmpValIe = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET);
+    if (ie) {
+        tmpValIe |= (1 << grp);
+    } else {
+        tmpValIe &= ~(1 << grp);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_IE_SET, tmpValIe);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_I_SET, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set gpio pad int mask type in pds
+ *
+ * @param  pad: gpio type
+ * @param  intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal = 0;
+    uint32_t pos = 0;
+
+    /* [15:0] : GPIO0~15   */
+    /* [30:16] : GPIO20~34 */
+    if (pad <= GLB_GPIO_PIN_15) {
+        pos = pad;
+    } else if ((pad >= GLB_GPIO_PIN_20) && (pad <= GLB_GPIO_PIN_34)) {
+        pos = pad - 4;
+    } else {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_PD_SET);
+    if (UNMASK != intMask) {
+        /* MASK */
+        tmpVal |= (1 << pos);
+    } else {
+        /* UNMASK */
+        tmpVal &= ~(1 << pos);
+    }
+    BL_WR_REG(PDS_BASE, PDS_GPIO_PD_SET, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set gpio pad trig type in pds
+ *
+ * @param  set: set type
+ * @param  trig: trig type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_PDS_GPIO_INT_SET_TYPE(set));
+    CHECK_PARAM(IS_PDS_GPIO_INT_TRIG_TYPE(trig));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    switch (set) {
+        case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET1_INT_MODE, trig);
+            break;
+        case PDS_GPIO_INT_SET_2_GPIO8_GPIO15:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET2_INT_MODE, trig);
+            break;
+        case PDS_GPIO_INT_SET_3_GPIO20_GPIO27:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET3_INT_MODE, trig);
+            break;
+        case PDS_GPIO_INT_SET_4_GPIO28_GPIO34:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_SET4_INT_MODE, trig);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set gpio pad int clear in pds
+ *
+ * @param  set: set type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_PDS_GPIO_INT_SET_TYPE(set));
+
+    /* pds_gpio_setx_int_clr = 0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    switch (set) {
+        case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_2_GPIO8_GPIO15:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_3_GPIO20_GPIO27:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_4_GPIO28_GPIO34:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    /* pds_gpio_setx_int_clr = 1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    switch (set) {
+        case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_2_GPIO8_GPIO15:
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_3_GPIO20_GPIO27:
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_4_GPIO28_GPIO34:
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    /* pds_gpio_setx_int_clr = 0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    switch (set) {
+        case PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_2_GPIO8_GPIO15:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_3_GPIO20_GPIO27:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);
+            break;
+        case PDS_GPIO_INT_SET_4_GPIO28_GPIO34:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get gpio pad int status
+ *
+ * @param  pad: gpio type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Sts_Type ATTR_TCM_SECTION PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad)
+{
+    uint32_t pos = 0;
+
+    /* [15:0]  : GPIO0~15  */
+    /* [30:16] : GPIO20~34 */
+    if (pad <= GLB_GPIO_PIN_15) {
+        pos = pad;
+    } else if ((pad >= GLB_GPIO_PIN_20) && (pad <= GLB_GPIO_PIN_34)) {
+        pos = pad - 4;
+    } else {
+        return RESET;
+    }
+
+    return (BL_RD_REG(PDS_BASE, PDS_GPIO_STAT) & (1 << pos)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set flash pad pull none
+ *
+ * @param  pinCfg: flash pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg)
+{
+    if (pinCfg >= SF_IO_EXT_SF2_SWAP_IO3IO0) {
+        PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(PDS_GPIO_GROUP_SET_GPIO0_GPIO15, 0, 0, 0);
+    } else {
+        return INVALID;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set flash pad pull none
+ *
+ * @param  pinCfg: flash pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+ * @note ext_flash need call this function after pds mode
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg)
+{
+    uint32_t tmpVal;
+
+    if (pinCfg >= SF_IO_EXT_SF2_SWAP_IO3IO0) {
+        /* pu/pd/ie config */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_I_SET);
+        /* GPIO4~9 [6][3][0] = 0 */
+        tmpVal &= ~(0x49);
+        BL_WR_REG(PDS_BASE, PDS_GPIO_I_SET, tmpVal);
+    } else {
+        return INVALID;
+    }
+    return SUCCESS;
+}
+/****************************************************************************/ /**
+ * @brief  Disable PDS GPIO Keep
+ *
+ * @return SUCCESS
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Disable_GPIO_Keep(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* PDS_IO keep disable */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_GPIO_ISO_MODE);
+    /* don't entry PDS */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_START_PS);
+    BL_WR_REG(PDS_BASE, PDS_CTL, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL5);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_GPIO_KEEP_EN);
+    BL_WR_REG(PDS_BASE, PDS_CTL5, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set MCU0 clock enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Clock_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN);
+    BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set MCU0 clock disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Clock_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CPU_CORE_CFG1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_MCU1_CLK_EN);
+    BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set MCU0 reset address
+ *
+ * @param  addr: address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_MCU0_Reset_Address(uint32_t addr)
+{
+    BL_WR_REG(PDS_BASE, PDS_CPU_CORE_CFG14, addr);
+
+    return SUCCESS;
+}
+/****************************************************************************/ /**
+ * @brief  Enable PDS power on PLL
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Pu_PLL_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL_SFREG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable PDS power on PLL
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Pu_PLL_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL_SFREG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable power down sleep
+ *
+ * @param  cfg: power down sleep configuration 1
+ * @param  cfg4: power down sleep configuration 2
+ * @param  pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
+{
+    uint32_t tmpVal = 0;
+    /* sleepForever set 1, chip will sleep forever */
+    /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
+    /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
+    if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
+        return ERROR;
+    } else if (pdsSleepCnt > PDS_WARMUP_LATENCY_CNT) {
+        BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
+    } else {
+    }
+
+    /* PDS_CTL4 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
+
+    /* PDS_CTL config */
+    if (cfg->pdsStart) {
+        /* clear pds int */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
+    } else {
+        BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  cfg2: power down sleep force configuration 1
+ * @param  cfg3: power down sleep force configuration 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5)
+{
+    /* PDS_CTL2 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);
+
+    /* PDS_CTL3 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);
+
+    /* PDS_CTL5 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL5, *(uint32_t *)cfg5);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep ram configure
+ *
+ * @param  ocramCfg: power down sleep force ocram configuration
+ * @param  wramCfg: power down sleep force wram configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg,
+                                            PDS_CTRL_RAM3_Type *ram3Cfg, PDS_CTRL_RAM4_Type *ram4Cfg)
+{
+    if ((NULL == ram1Cfg) || (NULL == ram2Cfg) || (NULL == ram3Cfg) || (NULL == ram4Cfg)) {
+        return ERROR;
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ram1Cfg);
+    BL_WR_REG(PDS_BASE, PDS_RAM2, *(uint32_t *)ram2Cfg);
+    BL_WR_REG(PDS_BASE, PDS_RAM3, *(uint32_t *)ram3Cfg);
+    BL_WR_REG(PDS_BASE, PDS_RAM4, *(uint32_t *)ram4Cfg);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  defaultLvCfg: power down sleep default level configuration
+ * @param  ramCfg: ram configuration
+ * @param  pdsSleepCnt: power down sleep time count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt)
+{
+    PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3), (PDS_CTL5_Type *)&(defaultLvCfg->pdsCtl5));
+    PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep int mask
+ *
+ * @param  intType: PDS int type
+ * @param  intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    if (intMask != UNMASK) {
+        tmpVal = tmpVal | (1 << (intType + PDS_INT_MASK_BIT_OFFSET));
+    } else {
+        tmpVal = tmpVal & ~(1 << (intType + PDS_INT_MASK_BIT_OFFSET));
+    }
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep int status
+ *
+ * @param  intType: PDS int type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
+{
+    return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << intType)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  clear power down sleep int status
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_IntClear(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Install PDS interrupt callback function
+ *
+ * @param  intType: PDS int type
+ * @param  cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
+#endif
+
+    pdsIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
+{
+    Efuse_Ana_RC32M_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32M_Trim(&trim);
+    if (trim.rc32mCodeFrExt2En) {
+        if (trim.rc32mCodeFrExt2Parity == EF_Ctrl_Get_Trim_Parity(trim.rc32mCodeFrExt2, 8)) {
+            tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
+            BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
+            arch_delay_us(2);
+            tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL2);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT2, trim.rc32mCodeFrExt2);
+            BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL2, tmpVal);
+            tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL2);
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_SEL);
+            BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL2, tmpVal);
+            /* hw_5T + sw_5T  */
+            arch_delay_us(1);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  PDS turn on USB
+ *
+ * @param  waitReady : wait turn on usb finish
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Turn_On_USB(uint8_t waitReady)
+{
+    uint32_t tmpVal = 0;
+
+    /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0                             */
+    /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
+    /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1        */
+    /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0               */
+    /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1             */
+    /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1               */
+    /* #1.2ms; wait UCLK                                                  */
+    /* wait(soc616_b0.usb_uclk);                                          */
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0);
+    BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW);
+    BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST);
+    BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+    /* greater than 5T */
+    arch_delay_us(1);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);
+    BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+    /* greater than 5T */
+    arch_delay_us(1);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);
+    BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+    /* wait UCLK 1.2ms */
+    arch_delay_ms(3);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_SW_RST_N);
+    BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+    if (waitReady) {
+        arch_delay_ms(2);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  PDS turn off USB
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Turn_Off_USB(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* USB_PHY_CTRL[3:2] reg_usb_phy_xtlsel=0                             */
+    /* 2000e504 = 0x40; #100; USB_PHY_CTRL[6] reg_pu_usb20_psw=1 (VCC33A) */
+    /* 2000e504 = 0x41; #500; USB_PHY_CTRL[0] reg_usb_phy_ponrst=1        */
+    /* 2000e500 = 0x20; #100; USB_CTL[0] reg_usb_sw_rst_n=0               */
+    /* 2000e500 = 0x22; #500; USB_CTL[1] reg_usb_ext_susp_n=1             */
+    /* 2000e500 = 0x23; #100; USB_CTL[0] reg_usb_sw_rst_n=1               */
+    /* #1.2ms; wait UCLK                                                  */
+    /* wait(soc616_b0.usb_uclk);                                          */
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_REG_USB_PHY_XTLSEL, 0);
+    BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_PU_USB20_PSW);
+    BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_PHY_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_PHY_PONRST);
+    BL_WR_REG(PDS_BASE, PDS_USB_PHY_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  USB phy suspend
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_USB_Suspend(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);
+    BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  USB phy resume
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_USB_Resume(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_USB_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_REG_USB_EXT_SUSP_N);
+    BL_WR_REG(PDS_BASE, PDS_USB_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power down sleep wake up interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void)
+{
+    for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
+        if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType] != NULL)) {
+            pdsIntCbfArra[intType]();
+        }
+    }
+
+    PDS_IntClear();
+}
+#endif
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c
new file mode 100755
index 0000000000..21e11b1336
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_pm.c
@@ -0,0 +1,974 @@
+#include "bl616_pm.h"
+#include "bflb_flash.h"
+#include "bl616_clock.h"
+#include "bflb_rtc.h"
+#include "bl616_glb.h"
+#include "bl616_hbn.h"
+#include "bl616_pds.h"
+#include "ef_data_reg.h"
+
+#ifndef PM_PDS_GPIO_KEEP_EN
+#define PM_PDS_GPIO_KEEP_EN 0
+#endif
+
+#ifndef PM_HBN_GPIO_KEEP_EN
+#define PM_HBN_GPIO_KEEP_EN 0
+#endif
+
+#ifndef PM_PDS_FLASH_POWER_OFF
+#define PM_PDS_FLASH_POWER_OFF 1
+#endif
+
+#ifndef PM_PDS_PLL_POWER_OFF
+#define PM_PDS_PLL_POWER_OFF 1
+#endif
+
+#ifndef PM_PDS_RF_POWER_OFF
+#define PM_PDS_RF_POWER_OFF 1
+#endif
+
+#ifndef PM_PDS_LDO_LEVEL_DEFAULT
+#define PM_PDS_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_1P10V
+#endif
+
+#ifndef PM_HBN_FLASH_POWER_OFF
+#define PM_HBN_FLASH_POWER_OFF 1
+#endif
+
+#ifndef PM_HBN_LDO_LEVEL_DEFAULT
+#define PM_HBN_LDO_LEVEL_DEFAULT HBN_LDO_LEVEL_0P90V
+#endif
+
+/* Cache Way Disable, will get from l1c register */
+uint8_t cacheWayDisable = 0;
+
+/* PSRAM IO Configuration, will get from glb register */
+uint32_t psramIoCfg = 0;
+
+/* Flash offset value, will get from sf_ctrl register */
+uint32_t flash_offset = 0;
+
+spi_flash_cfg_type *flash_cfg;
+
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel1 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWiFiState = 0,
+        .ldo11Off = 1,
+        .bgSysOff = 1,
+        .ctrlGpioIePuPd = 0,
+        .dcdc18Off = 1,
+        .clkOff = 1,
+        .memStby = 1,
+        .glbRstProtect = 0,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 1,
+        .socEnbForceOn = 0,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsDcdc11VselEn = 0,
+        .usbpllOff = 1,
+        .aupllOff = 1,
+        .wifipllOff = 1,
+        .pdsDcdc11Vsel = 0x8,
+        .pdsCtlRfSel = 3,
+        .pdsUseTbttSlp = 0,
+        .pdsGpioIsoMod = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceWbPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIso = 0,
+        .forceWbIso = 0,
+        .forceUsbIso = 0,
+        .forceCpuPdsRst = 0,
+        .forceWbPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceWbMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceWbGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceMiscIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceMiscGateClk = 0,
+        .cpuIsoEn = 0,
+        .wbIsoEn = 1,
+        .usbIsoEn = 0,
+        .miscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 0,
+        .cpuRst = 0,
+        .cpuMemStby = 0,
+        .cpuGateClk = 0,
+        .wbPwrOff = 1,
+        .wbRst = 1,
+        .wbMemStby = 0,
+        .wbGateClk = 0,
+        .usbPwrOff = 0,
+        .usbRst = 0,
+        .usbMemStby = 0,
+        .usbGateClk = 0,
+        .miscPwrOff = 0,
+        .miscRst = 0,
+        .miscMemStby = 0,
+        .miscGateClk = 0,
+    },
+    .pdsCtl5 = {
+        .cpuWfiMask = 0,
+        .pdsPadOdEn = 0,
+        .ctrlUsb33 = 0,
+        .ldo18ioOff = 1,
+        .pdsGpioKeep = 0,
+    }
+};
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel2 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWiFiState = 0,
+        .ldo11Off = 1,
+        .bgSysOff = 1,
+        .ctrlGpioIePuPd = 0,
+        .dcdc18Off = 1,
+        .clkOff = 1,
+        .memStby = 1,
+        .glbRstProtect = 0,
+        .isolation = 1,
+        .waitXtalRdy = 0,
+        .pdsPwrOff = 1,
+        .xtalOff = 1,
+        .socEnbForceOn = 1,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsDcdc11VselEn = 0,
+        .usbpllOff = 1,
+        .aupllOff = 1,
+        .wifipllOff = 1,
+        .pdsDcdc11Vsel = 0x8,
+        .pdsCtlRfSel = 3,
+        .pdsUseTbttSlp = 0,
+        .pdsGpioIsoMod = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceWbPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIso = 0,
+        .forceWbIso = 0,
+        .forceUsbIso = 0,
+        .forceCpuPdsRst = 0,
+        .forceWbPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceWbMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceWbGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceMiscIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceMiscGateClk = 0,
+        .cpuIsoEn = 1,
+        .wbIsoEn = 0,
+        .usbIsoEn = 0,
+        .miscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 0,
+        .cpuGateClk = 0,
+        .wbPwrOff = 0,
+        .wbRst = 0,
+        .wbMemStby = 0,
+        .wbGateClk = 0,
+        .usbPwrOff = 0,
+        .usbRst = 0,
+        .usbMemStby = 0,
+        .usbGateClk = 0,
+        .miscPwrOff = 0,
+        .miscRst = 0,
+        .miscMemStby = 0,
+        .miscGateClk = 0,
+    },
+    .pdsCtl5 = {
+        .cpuWfiMask = 0,
+        .pdsPadOdEn = 0,
+        .ctrlUsb33 = 1,
+        .ldo18ioOff = 1,
+        .pdsGpioKeep = 0,
+    }
+};
+
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel3 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWiFiState = 0,
+        .ldo11Off = 1,
+        .bgSysOff = 1,
+        .ctrlGpioIePuPd = 0,
+        .dcdc18Off = 1,
+        .clkOff = 1,
+        .memStby = 1,
+        .glbRstProtect = 0,
+        .isolation = 1,
+        .waitXtalRdy = 1,
+        .pdsPwrOff = 1,
+        .xtalOff = 1,
+        .socEnbForceOn = 0,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsDcdc11VselEn = 0,
+        .usbpllOff = 1,
+        .aupllOff = 1,
+        .wifipllOff = 1,
+        .pdsDcdc11Vsel = 0x8,
+        .pdsCtlRfSel = 3,
+        .pdsUseTbttSlp = 0,
+        .pdsGpioIsoMod = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceWbPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIso = 0,
+        .forceWbIso = 0,
+        .forceUsbIso = 0,
+        .forceCpuPdsRst = 0,
+        .forceWbPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceWbMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceWbGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceMiscIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceMiscGateClk = 0,
+        .cpuIsoEn = 1,
+        .wbIsoEn = 1,
+        .usbIsoEn = 0,
+        .miscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 0,
+        .cpuGateClk = 0,
+        .wbPwrOff = 1,
+        .wbRst = 1,
+        .wbMemStby = 0,
+        .wbGateClk = 0,
+        .usbPwrOff = 0,
+        .usbRst = 0,
+        .usbMemStby = 0,
+        .usbGateClk = 0,
+        .miscPwrOff = 0,
+        .miscRst = 0,
+        .miscMemStby = 0,
+        .miscGateClk = 0,
+    },
+    .pdsCtl5 = {
+        .cpuWfiMask = 0,
+        .pdsPadOdEn = 0,
+        .ctrlUsb33 = 1,
+        .ldo18ioOff = 1,
+        .pdsGpioKeep = 0,
+    }
+};
+
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel7 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWiFiState = 0,
+        .ldo11Off = 1,
+        .bgSysOff = 1,
+        .ctrlGpioIePuPd = 0,
+        .dcdc18Off = 1,
+        .clkOff = 1,
+        .memStby = 1,
+        .glbRstProtect = 0,
+        .isolation = 1,
+        .waitXtalRdy = 1,
+        .pdsPwrOff = 1,
+        .xtalOff = 1,
+        .socEnbForceOn = 0,
+        .pdsRstSocEn = 0,
+        .pdsRC32mOn = 0,
+        .pdsDcdc11VselEn = 0,
+        .usbpllOff = 1,
+        .aupllOff = 1,
+        .wifipllOff = 1,
+        .pdsDcdc11Vsel = 0x8,
+        .pdsCtlRfSel = 3,
+        .pdsUseTbttSlp = 0,
+        .pdsGpioIsoMod = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceWbPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIso = 0,
+        .forceWbIso = 0,
+        .forceUsbIso = 0,
+        .forceCpuPdsRst = 0,
+        .forceWbPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceWbMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceWbGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceMiscIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceMiscGateClk = 0,
+        .cpuIsoEn = 1,
+        .wbIsoEn = 1,
+        .usbIsoEn = 1,
+        .miscIsoEn = 0,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 0,
+        .cpuGateClk = 0,
+        .wbPwrOff = 1,
+        .wbRst = 1,
+        .wbMemStby = 0,
+        .wbGateClk = 0,
+        .usbPwrOff = 1,
+        .usbRst = 1,
+        .usbMemStby = 0,
+        .usbGateClk = 0,
+        .miscPwrOff = 0,
+        .miscRst = 0,
+        .miscMemStby = 0,
+        .miscGateClk = 0,
+    },
+    .pdsCtl5 = {
+        .cpuWfiMask = 0,
+        .pdsPadOdEn = 0,
+        .ctrlUsb33 = 1,
+        .ldo18ioOff = 1,
+        .pdsGpioKeep = 0,
+    }
+};
+
+static PDS_DEFAULT_LV_CFG_Type ATTR_TCM_CONST_SECTION pdsCfgLevel15 = {
+    .pdsCtl = {
+        .pdsStart = 1,
+        .sleepForever = 0,
+        .xtalForceOff = 0,
+        .saveWiFiState = 0,
+        .ldo11Off = 1,
+        .bgSysOff = 1,
+        .ctrlGpioIePuPd = 0,
+        .dcdc18Off = 1,
+        .clkOff = 1,
+        .memStby = 1,
+        .glbRstProtect = 0,
+        .isolation = 1,
+        .waitXtalRdy = 1,
+        .pdsPwrOff = 1,
+        .xtalOff = 1,
+        .socEnbForceOn = 0,
+        .pdsRstSocEn = 1,
+        .pdsRC32mOn = 0,
+        .pdsDcdc11VselEn = 0,
+        .usbpllOff = 1,
+        .aupllOff = 1,
+        .wifipllOff = 1,
+        .pdsDcdc11Vsel = 0x8,
+        .pdsCtlRfSel = 3,
+        .pdsUseTbttSlp = 0,
+        .pdsGpioIsoMod = 0,
+    },
+    .pdsCtl2 = {
+        .forceCpuPwrOff = 0,
+        .forceWbPwrOff = 0,
+        .forceUsbPwrOff = 0,
+        .forceCpuIso = 0,
+        .forceWbIso = 0,
+        .forceUsbIso = 0,
+        .forceCpuPdsRst = 0,
+        .forceWbPdsRst = 0,
+        .forceUsbPdsRst = 0,
+        .forceCpuMemStby = 0,
+        .forceWbMemStby = 0,
+        .forceUsbMemStby = 0,
+        .forceCpuGateClk = 0,
+        .forceWbGateClk = 0,
+        .forceUsbGateClk = 0,
+    },
+    .pdsCtl3 = {
+        .forceMiscPwrOff = 0,
+        .forceMiscIsoEn = 0,
+        .forceMiscPdsRst = 0,
+        .forceMiscMemStby = 0,
+        .forceMiscGateClk = 0,
+        .cpuIsoEn = 1,
+        .wbIsoEn = 1,
+        .usbIsoEn = 1,
+        .miscIsoEn = 1,
+    },
+    .pdsCtl4 = {
+        .cpuPwrOff = 1,
+        .cpuRst = 1,
+        .cpuMemStby = 0,
+        .cpuGateClk = 0,
+        .wbPwrOff = 1,
+        .wbRst = 1,
+        .wbMemStby = 0,
+        .wbGateClk = 0,
+        .usbPwrOff = 1,
+        .usbRst = 1,
+        .usbMemStby = 0,
+        .usbGateClk = 0,
+        .miscPwrOff = 1,
+        .miscRst = 1,
+        .miscMemStby = 0,
+        .miscGateClk = 0,
+    },
+    .pdsCtl5 = {
+        .cpuWfiMask = 0,
+        .pdsPadOdEn = 0,
+        .ctrlUsb33 = 1,
+        .ldo18ioOff = 1,
+        .pdsGpioKeep = 0,
+    }
+};
+/******************************************************************************
+ * @brief  set power down sleep VDDCORE gpio interrupt mask
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+static BL_Err_Type ATTR_TCM_SECTION pm_clr_pds_gpio_int(void)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    // PDS_GPIO_INT_SET_1_GPIO0_GPIO7:
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET1_INT_CLR);
+    // PDS_GPIO_INT_SET_2_GPIO8_16_GPIO22:
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET2_INT_CLR);
+    // PDS_GPIO_INT_SET_3_GPIO23_GPIO30:
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET3_INT_CLR);
+    // PDS_GPIO_INT_SET_4_GPIO31_GPIO38:
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_SET4_INT_CLR);
+
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+    return SUCCESS;
+}
+
+/******************************************************************************
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  delay: None
+ *
+ * @return SUCCESS or ERROR
+ *
+ *******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((delay <= 0x3));
+
+    /* config ldo11soc_sstart_delay_aon */
+    tmpVal = BL_RD_REG(AON_BASE, AON_DCDC_TOP_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC_SSTART_TIME_AON, delay);
+    BL_WR_REG(AON_BASE, AON_DCDC_TOP_0, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type pm_pds_wakeup_src_en(uint32_t WakeupType)
+{
+    if ((WakeupType < PDS_WAKEUP_BY_PDS_TIMER_EN_POS) || (WakeupType > PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_POS)) {
+        return INVALID;
+    }
+
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal |= ((uint32_t)1 << WakeupType);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Sts_Type pm_pds_get_wakeup_src(uint32_t WakeupType)
+{
+    if ((WakeupType < PDS_WAKEUP_BY_PDS_TIMER_EN_POS) || (WakeupType > PDS_WAKEUP_BY_WIFI_TBTT_IRQ_EN_POS)) {
+        return INVALID;
+    }
+
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RO_PDS_WAKEUP_EVENT);
+    tmpVal &= ((uint32_t)1 << (WakeupType - PDS_WAKEUP_BY_PDS_TIMER_EN_POS));
+
+    return tmpVal ? SET : RESET;
+}
+
+void pm_pds_mask_all_wakeup_src(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_WAKEUP_SRC_EN);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_RF_DONE_INT_MASK);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_WIFI_TBTT_SLEEP_IRQ_MASK);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_WIFI_TBTT_WAKEUP_IRQ_MASK);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+}
+
+static void pm_pds_intc_clr(void)
+{
+    pm_clr_pds_gpio_int();
+    PDS_IntClear();
+}
+
+/**
+ * @brief power management in pds(power down sleep) mode
+ *
+ * cpu's behavior after wakeup depend on psd level,see flow table if cpu off ,
+ * cpu will reset after wakeup
+ *
+ *    PD_CORE   PD_CORE_MISC_DIG    PD_CORE_MISC_ANA   PD_CORE_CPU PD_BZ PD_USB
+ *PDS0    ON           ON                   ON            ON        ON      ON
+ *PDS1    ON           ON                   ON            ON        ON      OFF
+ *PDS2    ON           ON                   ON            ON        OFF     ON
+ *PDS3    ON           ON                   ON            ON        OFF     OFF
+ *PDS4    ON           ON                   ON            OFF       ON      ON
+ *PDS5    ON           ON                   ON            OFF       ON      OFF
+ *PDS6    ON           ON                   ON            OFF       OFF     ON
+ *PDS7    ON           ON                   ON            OFF       OFF     OFF
+ */
+void ATTR_TCM_SECTION pm_pds_mode_enter(enum pm_pds_sleep_level pds_level,
+                                        uint32_t sleep_time)
+{
+    PDS_DEFAULT_LV_CFG_Type *pPdsCfg = NULL;
+    uint32_t tmpVal;
+    uint32_t pds_ram[4];
+    PDS_RAM_CFG_Type pds_ram_ctrl = { (PDS_CTRL_RAM1_Type *)&pds_ram[0], (PDS_CTRL_RAM2_Type *)&pds_ram[1],
+                                      (PDS_CTRL_RAM3_Type *)&pds_ram[2], (PDS_CTRL_RAM4_Type *)&pds_ram[3] };
+    uint8_t xtal_type = 0;
+
+    if ((sleep_time != 0) && (sleep_time <= PDS_WARMUP_LATENCY_CNT)) {
+        return;
+    }
+
+    /* To make it simple and safe*/
+    __ASM volatile("csrc mstatus, 8");
+
+    /* get xtal type */
+    HBN_Get_Xtal_Type(&xtal_type);
+
+    HBN_Set_Ldo11_Rt_Vout(PM_PDS_LDO_LEVEL_DEFAULT);
+    /************************ PDS INT SET ***********************/
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+
+    if (sleep_time)
+        tmpVal |= (1 << 10); // unmask pds sleep time wakeup
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    /* clear all interrupt status */
+    pm_pds_intc_clr();
+
+    /* enable PDS interrupt to wakeup CPU (PDS1:CPU not powerdown, CPU __WFI)*/
+    pm_pds_irq_register();
+    /***********************************************************/
+
+    switch (pds_level) {
+        case PM_PDS_LEVEL_1:
+            pPdsCfg = &pdsCfgLevel1;
+            break;
+        case PM_PDS_LEVEL_2:
+            pPdsCfg = &pdsCfgLevel2;
+            break;
+        case PM_PDS_LEVEL_3:
+            pPdsCfg = &pdsCfgLevel3;
+            break;
+        case PM_PDS_LEVEL_7:
+            pPdsCfg = &pdsCfgLevel7;
+            break;
+        case PM_PDS_LEVEL_15:
+            pPdsCfg = &pdsCfgLevel15;
+            break;
+        default:
+            return;
+    }
+
+#if PM_PDS_FLASH_POWER_OFF
+    uint32_t flash_cfg_len;
+    uint32_t sf_pin_select = 0;
+
+    /* get sw uasge 0 */
+    // EF_Ctrl_Read_Sw_Usage(0, (uint32_t *)&tmpVal);
+    tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_EF_SW_USAGE_0);
+    /* get flash type */
+    sf_pin_select = (tmpVal >> 14) & 0x3f;
+    /* get flash config */
+    bflb_flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
+
+    HBN_Power_Down_Flash(flash_cfg);
+    /* Turn Off Flash/PSRAM PAD IE */
+    if (sf_pin_select & (1 << 2)) {
+        for (uint8_t i = 4; i < 10; i++) {
+            *((volatile uint32_t *)(0x200008C4 + i * 4)) = 0;
+        }
+    } else if (sf_pin_select & (1 << 3)) {
+        for (uint8_t i = 10; i < 16; i++) {
+            *((volatile uint32_t *)(0x200008C4 + i * 4)) = 0;
+        }
+    } else {
+    }
+
+    // psram io config
+    for (uint8_t i = 35; i < 56; i++) {
+        //*((volatile uint32_t *)(0x200008C4 + i * 4)) = 0;
+    }
+
+#endif
+
+#if PM_PDS_GPIO_KEEP_EN
+    pPdsCfg->pdsCtl.pdsGpioIsoMod = 1;
+    pPdsCfg->pdsCtl5.pdsGpioKeep = 7;
+#endif
+
+#if PM_PDS_PLL_POWER_OFF
+    /* MCU CLK SELECT RC32M */
+    PDS_Pu_PLL_Enable();
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
+    GLB_Power_Off_AUPLL();
+    GLB_Power_Off_WIFIPLL();
+    // AON_Power_Off_XTAL();
+#endif
+
+#if PM_PDS_RF_POWER_OFF == 0
+    pPdsCfg->pdsCtl.pdsCtlRfSel = 0;
+#endif
+
+    if (0 != (0xF & BL_RD_REG(PDS_BASE, PDS_GPIO_I_SET))) {
+        pPdsCfg->pdsCtl.ctrlGpioIePuPd = 1;
+    }
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    /* if enable wakeup trigger by irrx */
+    if (BL_IS_REG_BIT_SET(tmpVal, PDS_WAKEUP_BY_IRRX_EN)) {
+        /* xclk selecet xtal,xtal can't power off */
+        GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_XTAL);
+        pPdsCfg->pdsCtl.xtalOff = 0;
+        // pPdsCfg->pdsCtl.pdsRC32mOn = 1;
+        // pPdsCfg->pdsCtl.clkOff = 0;
+    }
+
+    /* config  ldo11soc_sstart_delay_aon =2 , cr_pds_pd_ldo11=0 to speedup
+   * ldo11soc_rdy_aon */
+    AON_Set_LDO11_SOC_Sstart_Delay(0x2);
+
+    pds_ram[0] = BL_RD_REG(PDS_BASE, PDS_RAM1);
+    pds_ram[1] = BL_RD_REG(PDS_BASE, PDS_RAM2);
+    pds_ram[2] = BL_RD_REG(PDS_BASE, PDS_RAM3);
+    pds_ram[3] = BL_RD_REG(PDS_BASE, PDS_RAM4);
+
+    /* Enable PDS control pd_core Sram Clock */
+    pds_ram_ctrl.pds_ram1->ctlRamClk = 1;
+
+    if (pds_level == PM_PDS_LEVEL_15) {
+        /* WRAM Sleep */
+        pds_ram_ctrl.pds_ram2->wramSlp &= ~0x3ff;
+        /* WRAM Retention */
+        pds_ram_ctrl.pds_ram2->wramRet |= 0x3ff;
+
+        /* OCRAM Sleep */
+        pds_ram_ctrl.pds_ram4->cr_ocram_slp &= ~0xfffff;
+        /* OCRAM Retention */
+        pds_ram_ctrl.pds_ram3->cr_ocram_ret |= 0xfffff;
+    } else {
+        /* WRAM Sleep */
+        pds_ram_ctrl.pds_ram2->wramSlp &= ~0x3ff;
+        /* OCRAM Sleep */
+        pds_ram_ctrl.pds_ram4->cr_ocram_slp &= ~0xfffff;
+    }
+
+    PDS_RAM_Config(
+        (PDS_CTRL_RAM1_Type *)pds_ram_ctrl.pds_ram1, (PDS_CTRL_RAM2_Type *)pds_ram_ctrl.pds_ram2,
+        (PDS_CTRL_RAM3_Type *)pds_ram_ctrl.pds_ram3, (PDS_CTRL_RAM4_Type *)pds_ram_ctrl.pds_ram4);
+
+    PDS_Default_Level_Config(pPdsCfg, sleep_time);
+
+    __WFI();
+
+/******************************* Wakeup Flow *******************************/
+#if PM_PDS_PLL_POWER_OFF
+    GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_40M, GLB_PLL_WIFIPLL);
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_TOP_WIFIPLL_320M);
+#endif
+
+#if PM_PDS_FLASH_POWER_OFF
+    if (pds_level < PM_PDS_LEVEL_2) {
+        /* Init flash gpio */
+        bflb_sf_cfg_init_flash_gpio((uint8_t)sf_pin_select, 1);
+
+        bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+        bflb_sflash_restore_from_powerdown(flash_cfg, 0, SF_CTRL_FLASH_BANK0);
+    }
+#endif
+
+    /* enable global interrupts */
+    __asm volatile("csrs mstatus, 8");
+
+    /*************************************************************************/
+}
+
+/**
+ * @brief
+ *
+ * power management in hbn(hibernation) mode
+ * cpu will reset after wakeup
+ *
+ * HBN_LEVEL PD_AON PD_AON_HBNRTC PD_AON_HBNCORE PD_CORE&...
+ * HBN0        ON       ON            ON            OFF
+ * HBN1        ON       ON            OFF           OFF
+ * HBN2        ON       OFF           OFF           OFF
+ *
+ * @param hbn_level
+ */
+ATTR_TCM_SECTION void pm_hbn_mode_enter(enum pm_hbn_sleep_level hbn_level,
+                                        uint8_t sleep_time)
+{
+    uint32_t tmpVal;
+
+    /* To make it simple and safe*/
+    __ASM volatile("csrc mstatus, 8");
+
+    bflb_irq_clear_pending(HBN_OUT0_IRQn);
+    bflb_irq_clear_pending(HBN_OUT1_IRQn);
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+    if (sleep_time) {
+        struct bflb_device_s *rtc_dev = NULL;
+        bflb_rtc_set_time(rtc_dev,sleep_time); // sleep time,unit is second
+    }
+
+    if (hbn_level >= PM_HBN_LEVEL_2) {
+        HBN_Power_Off_RC32K();
+    } else {
+        HBN_Keep_On_RC32K();
+    }
+
+    /* MCU CLK SELECT RC32M */
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
+
+#if PM_HBN_FLASH_POWER_OFF
+    uint32_t flash_cfg_len;
+
+    /* get flash config */
+    bflb_flash_get_cfg((uint8_t **)&flash_cfg, &flash_cfg_len);
+
+    HBN_Power_Down_Flash(flash_cfg);
+#endif
+
+    /* HBN mode LDO level */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, PM_HBN_LDO_LEVEL_DEFAULT);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbn_level) {
+        case PM_HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+        case PM_HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+        case PM_HBN_LEVEL_2:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+    }
+
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0xffffffff);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, 0);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        arch_delay_ms(100);
+        GLB_SW_POR_Reset();
+    }
+}
+
+void pm_set_wakeup_callback(void (*wakeup_callback)(void))
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV1, (uint32_t)wakeup_callback);
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+}
+
+void pm_set_boot2_app_jump_para(uint32_t para)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV1, para);
+    /* Set APP jump flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, APP_JUMP_ENTER_FLAG);
+}
+
+void pm_hbn_out0_irq_register(void)
+{
+    Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQ);
+    CPU_Interrupt_Enable(HBN_OUT0_IRQn);
+}
+
+void pm_hbn_out1_irq_register(void)
+{
+    Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQ);
+    CPU_Interrupt_Enable(HBN_OUT1_IRQn);
+}
+
+void HBN_OUT0_IRQ(void)
+{
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO16)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO16);
+        pm_irq_callback(PM_HBN_GPIO16_WAKEUP_EVENT);
+    } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO17)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO17);
+        pm_irq_callback(PM_HBN_GPIO17_WAKEUP_EVENT);
+    } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO18)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO18);
+        pm_irq_callback(PM_HBN_GPIO18_WAKEUP_EVENT);
+    } else if (SET == HBN_Get_INT_State(HBN_INT_GPIO19)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO19);
+        pm_irq_callback(PM_HBN_GPIO19_WAKEUP_EVENT);
+    } else {
+        HBN_Clear_RTC_INT();
+        HBN_Clear_IRQ(HBN_INT_RTC);
+        pm_irq_callback(PM_HBN_RTC_WAKEUP_EVENT);
+    }
+}
+
+void ATTR_TCM_SECTION HBN_OUT1_IRQ(void)
+{
+    /* PIR */
+    if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
+        HBN_Clear_IRQ(HBN_INT_PIR);
+    }
+    /* BOR */
+    else if (SET == HBN_Get_INT_State(HBN_INT_BOD)) {
+        HBN_Clear_IRQ(HBN_INT_BOD);
+        pm_irq_callback(PM_HBN_BOD_WAKEUP_EVENT);
+    }
+    /* ACOMP0 */
+    else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP0);
+        pm_irq_callback(PM_HBN_ACOMP0_WAKEUP_EVENT);
+    }
+    /* ACOMP1 */
+    else if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP1);
+        pm_irq_callback(PM_HBN_ACOMP1_WAKEUP_EVENT);
+    }
+}
+
+void hal_pm_ldo11_use_ext_dcdc(void)
+{
+    for (uint8_t i = 0; i < 9; i++) {
+        HBN_Set_Ldo11_Rt_Vout(9 - i);
+        HBN_Set_Ldo11_Soc_Vout(9 - i);
+        arch_delay_ms(1);
+    }
+    HBN_Set_Ldo11_Rt_Vout(0);
+    HBN_Set_Ldo11_Soc_Vout(0);
+}
+__WEAK void pm_irq_callback(enum pm_event_type event)
+{
+}
+
+void pm_pds_irq_register(void)
+{
+    Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQ);
+    CPU_Interrupt_Enable(PDS_WAKEUP_IRQn);
+}
+
+void ATTR_TCM_SECTION PDS_WAKEUP_IRQ(void)
+{
+    /* WAKE INT */
+    if (SET == PDS_Get_IntStatus(PDS_INT_WAKEUP)) {
+    }
+    /* RF DONE */
+    else if (SET == PDS_Get_IntStatus(PDS_INT_RF_DONE)) {
+    }
+    /* WIFI_TBTT_SLEEP */
+    else if (SET == PDS_Get_IntStatus(PDS_INT_WIFI_TBTT_SLEEP)) {
+    }
+    /* WIFI_TBTT_WAKEUP */
+    else if (SET == PDS_Get_IntStatus(PDS_INT_WIFI_TBTT_WAKEUP)) {
+    } else {
+    }
+
+    PDS_IntClear();
+}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_psram.c
old mode 100644
new mode 100755
similarity index 91%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_psram.c
index a270b82f07..076d3ec193
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_psram.c
@@ -1,13 +1,13 @@
 /**
   ******************************************************************************
-  * @file    bl808p_psram_ctrl.c
+  * @file    bl616_psram_ctrl.c
   * @version V1.0
   * @date
   * @brief   This file is the standard driver c file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  * 
© COPYRIGHT(c) 2022 Bouffalo Lab

   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,11 +33,11 @@
   *
   ******************************************************************************
   */
-#include "bl808_glb.h"
-#include "bl808_psram.h"
+#include "bl616_glb.h"
+#include "bl616_psram.h"
 #include "psram_reg.h"
 
-/** @addtogroup  BL808P_Peripheral_Driver
+/** @addtogroup  BL616_Peripheral_Driver
  *  @{
  */
 
@@ -48,7 +48,7 @@
 /** @defgroup  PSRAM_CTRL_Private_Macros
  *  @{
  */
-
+#define PSRAM_X8_CTRL_WAIT_TIMEOUT 1000
 /*@} end of group PSRAM_CTRL_Private_Macros */
 
 /** @defgroup  PSRAM_CTRL_Private_Types
@@ -104,19 +104,14 @@ void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg)
 
     //PSRAM initial sequence
     arch_delay_us(150);
-    /* set psram ctrl x8 */
-    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM_CFG0);
-    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SEL_PSRAM0_X16, 0x0);
-    BL_WR_REG(GLB_BASE, GLB_PARM_CFG0, tmpVal);
-
     /* set psram dqs delay 0xfff0 */
     tmpVal = BL_RD_REG(psram_base, PSRAM_ROUGH_DELAY_CTRL5);
-    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_ROUGH_SEL_I_DQS0, 0xfff0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_ROUGH_SEL_I_DQS0, psramCtrlCfg->dqs_delay);
     BL_WR_REG(psram_base, PSRAM_ROUGH_DELAY_CTRL5, tmpVal);
 
     /* Set vendor and mode for psram controller */
     tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
-    //  tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_PCK_S_DIV, 0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_PCK_S_DIV, 0x1);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_VENDOR_SEL, psramCtrlCfg->vendor);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_X16_MODE, psramCtrlCfg->ioMode);
     BL_WR_REG(psram_base, PSRAM_CONFIGURE, tmpVal);
@@ -146,6 +141,7 @@ static void PSram_Ctrl_Request(PSRAM_ID_Type PSRAM_ID)
 {
     uint32_t tmpVal = 0;
     uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
+    uint32_t time_out = 0;
 
     //start configure request
     tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
@@ -155,6 +151,9 @@ static void PSram_Ctrl_Request(PSRAM_ID_Type PSRAM_ID)
     //Waiting for the authorization
     do {
         tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
+        if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
+            break;
+        }
     } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_REG_CONFIG_GNT));
 }
 
@@ -184,13 +183,14 @@ static void PSram_Ctrl_Release(PSRAM_ID_Type PSRAM_ID)
  * @param  reg_addr: PSRAM Register ID CR0 or CR1
  * @param  regVal: read Reister value
  *
- * @return None
+ * @return SUCCESS or TIMEOUT
  *
 *******************************************************************************/
-void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal)
+BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal)
 {
     uint32_t tmpVal = 0;
     uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
+    uint32_t time_out = 0;
 
     CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
     CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));
@@ -211,6 +211,9 @@ void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_
     //waiting confiure complete
     do {
         tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
+        if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
+            return TIMEOUT;
+        }
     } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));
 
     //read reg data form sts_config_read
@@ -218,6 +221,8 @@ void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_
     *regVal = (uint16_t)(tmpVal >> 16);
 
     PSram_Ctrl_Release(PSRAM_ID);
+
+    return SUCCESS;
 }
 
 /****************************************************************************/ /**
@@ -227,14 +232,15 @@ void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_
  * @param  reg_addr: PSRAM Register ID CR0 or CR1
  * @param  reg_cfg: winbond configuration
  *
- * @return None
+ * @return SUCCESS or TIMEOUT
  *
 *******************************************************************************/
-void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, PSRAM_Winbond_Cfg_Type *reg_cfg)
+BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, PSRAM_Winbond_Cfg_Type *reg_cfg)
 {
     uint32_t tmpVal = 0;
     uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
     PSRAM_Ctrl_Size_Type psramDensity;
+    uint32_t time_out = 0;
 
     CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
     CHECK_PARAM(IS_PSRAM_CTRL_WINBOND_CFG_REG_TYPE(reg_addr));
@@ -267,8 +273,7 @@ void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_IPD, reg_cfg->inputPowerDownMode);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_MCLK_TYPE, reg_cfg->clockType);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_LINEAR_DIS, reg_cfg->linear_dis);
-    /* W955D8MKY don't support sw rst */
-    /* tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_SW_RST, reg_cfg->rst); */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_REG_WB_SW_RST, reg_cfg->rst);
 
     BL_WR_REG(psram_base, PSRAM_WINBOND_PSRAM_CONFIGURE, tmpVal);
 
@@ -285,9 +290,14 @@ void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg
     //waiting confiure complete
     do {
         tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
+        if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
+            return TIMEOUT;
+        }
     } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));
 
     PSram_Ctrl_Release(PSRAM_ID);
+
+    return SUCCESS;
 }
 
 /****************************************************************************/ /**
@@ -297,13 +307,14 @@ void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg
  * @param  reg_addr: PSRAM Register ID CR0 or CR1
  * @param  regVal: read Reister value
  *
- * @return None
+ * @return SUCCESS or TIMEOUT
  *
 *******************************************************************************/
-void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal)
+BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal)
 {
     uint32_t tmpVal = 0;
     uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
+    uint32_t time_out = 0;
 
     CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
     CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));
@@ -324,6 +335,9 @@ void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_
     //waiting confiure complete
     do {
         tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
+        if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
+            return TIMEOUT;
+        }
     } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_R_DONE));
 
     //read reg data form sts_config_read
@@ -331,6 +345,8 @@ void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_
     *regVal = (uint16_t)(tmpVal >> 16);
 
     PSram_Ctrl_Release(PSRAM_ID);
+
+    return SUCCESS;
 }
 
 /****************************************************************************/ /**
@@ -340,13 +356,14 @@ void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_
  * @param  reg_addr: PSRAM Register ID
  * @param  reg_cfg: winbond configuration
  *
- * @return None
+ * @return SUCCESS or TIMEOUT
  *
 *******************************************************************************/
-void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, PSRAM_APMemory_Cfg_Type *reg_cfg)
+BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, PSRAM_APMemory_Cfg_Type *reg_cfg)
 {
     uint32_t tmpVal = 0;
     uint32_t psram_base = PSRAM_CTRL_BASE + (0x1000 * PSRAM_ID);
+    uint32_t time_out = 0;
 
     CHECK_PARAM(IS_PSRAM_WINBON_CFG_TYPE(reg_cfg));
     CHECK_PARAM(IS_PSRAM_CTRL_APMEM_CFG_REG_TYPE(reg_addr));
@@ -384,9 +401,14 @@ void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg
     //waiting confiure complete
     do {
         tmpVal = BL_RD_REG(psram_base, PSRAM_CONFIGURE);
+        if (time_out++ > PSRAM_X8_CTRL_WAIT_TIMEOUT) {
+            return TIMEOUT;
+        }
     } while (!BL_IS_REG_BIT_SET(tmpVal, PSRAM_STS_CONFIG_W_DONE));
 
     PSram_Ctrl_Release(PSRAM_ID);
+
+    return SUCCESS;
 }
 
 /****************************************************************************/ /**
@@ -534,4 +556,4 @@ void PSram_Ctrl_Debug_Timout(PSRAM_ID_Type PSRAM_ID, uint8_t enable, uint32_t ti
 
 /*@} end of group PSRAM_CTRL */
 
-/*@} end of group BL808P_Peripheral_Driver */
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c
old mode 100644
new mode 100755
similarity index 53%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c
index 7ecfc91620..f7e11000be
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romapi_e907.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_e907.c
@@ -1,16 +1,6 @@
-#include "bl808_romdriver_e907.h"
+#include "bl616_romdriver_e907.h"
 
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type AON_LowPower_Enter_PDS0(void){
-    return RomDriver_AON_LowPower_Enter_PDS0();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type AON_LowPower_Exit_PDS0(void){
-    return RomDriver_AON_LowPower_Exit_PDS0();
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type AON_Power_Off_BG(void){
     return RomDriver_AON_Power_Off_BG();
@@ -61,29 +51,34 @@ BL_Err_Type AON_Power_On_XTAL(void){
     return RomDriver_AON_Power_On_XTAL();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type AON_Set_DCDC11_Top_Vout(AON_DCDC_LEVEL_Type dcdcLevel){
-    return RomDriver_AON_Set_DCDC11_Top_Vout(dcdcLevel);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut){
     return RomDriver_AON_Set_Xtal_CapCode(capIn,capOut);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type AON_Trim_DCDC11_Vout(void){
-    return RomDriver_AON_Trim_DCDC11_Vout();
+BL_Err_Type AON_Trim_DcdcDis(void){
+    return RomDriver_AON_Trim_DcdcDis();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type AON_Trim_DCDC18_Vout(void){
-    return RomDriver_AON_Trim_DCDC18_Vout();
+BL_Err_Type AON_Trim_DcdcVoutSel(void){
+    return RomDriver_AON_Trim_DcdcVoutSel();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type AON_Trim_USB20_RCAL(void){
-    return RomDriver_AON_Trim_USB20_RCAL();
+BL_Err_Type AON_Trim_DcdcVoutTrim(void){
+    return RomDriver_AON_Trim_DcdcVoutTrim();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type AON_Trim_Ldo11socVoutTrim(void){
+    return RomDriver_AON_Trim_Ldo11socVoutTrim();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type AON_Trim_Usb20RcalCode(void){
+    return RomDriver_AON_Trim_Usb20RcalCode();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -92,18 +87,88 @@ uint8_t AON_Get_Xtal_CapCode(void){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT){
-    return RomDriver_ASM_Delay_Us(core,cnt,loopT);
+BL_Err_Type CPU_MTimer_Delay_MS(uint32_t cnt){
+    return RomDriver_CPU_MTimer_Delay_MS(cnt);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void arch_delay_ms(uint32_t cnt){
-    return RomDriver_arch_delay_ms(cnt);
+BL_Err_Type CPU_MTimer_Delay_US(uint32_t cnt){
+    return RomDriver_CPU_MTimer_Delay_US(cnt);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void arch_delay_us(uint32_t cnt){
-    return RomDriver_arch_delay_us(cnt);
+BL_Err_Type CPU_Reset_MTimer(void){
+    return RomDriver_CPU_Reset_MTimer();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type CPU_Set_MTimer_CLK(uint8_t enable, BL_MTimer_Source_Clock_Type mTimerSourceClockType, uint16_t div){
+    return RomDriver_CPU_Set_MTimer_CLK(enable,mTimerSourceClockType,div);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type CPU_Set_MTimer_RST(uint8_t rstEn){
+    return RomDriver_CPU_Set_MTimer_RST(rstEn);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t CPU_Get_MTimer_Clock(void){
+    return RomDriver_CPU_Get_MTimer_Clock();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t CPU_Get_MTimer_Source_Clock(void){
+    return RomDriver_CPU_Get_MTimer_Source_Clock();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t Clock_Audio_ADC_Clock_Get(void){
+    return RomDriver_Clock_Audio_ADC_Clock_Get();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t Clock_Get_ISP_Clk(void){
+    return RomDriver_Clock_Get_ISP_Clk();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t Clock_Get_PSRAMB_Clk(void){
+    return RomDriver_Clock_Get_PSRAMB_Clk();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type){
+    return RomDriver_Clock_Peripheral_Clock_Get(type);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type){
+    return RomDriver_Clock_System_Clock_Get(type);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t SystemCoreClockGet(void){
+    return RomDriver_SystemCoreClockGet();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint64_t CPU_Get_CPU_Cycle(void){
+    return RomDriver_CPU_Get_CPU_Cycle();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint64_t CPU_Get_MTimer_Counter(void){
+    return RomDriver_CPU_Get_MTimer_Counter();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint64_t CPU_Get_MTimer_MS(void){
+    return RomDriver_CPU_Get_MTimer_MS();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint64_t CPU_Get_MTimer_US(void){
+    return RomDriver_CPU_Get_MTimer_US();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -157,8 +222,13 @@ uint8_t EF_Ctrl_Is_All_Bits_Zero(uint32_t val, uint8_t start, uint8_t len){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len){
-    return RomDriver_EF_Ctrl_Clear(region,index,len);
+uint8_t EF_Ctrl_Read_FlashDlyCoe(void){
+    return RomDriver_EF_Ctrl_Read_FlashDlyCoe();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void EF_Ctrl_Clear(uint32_t index, uint32_t len){
+    return RomDriver_EF_Ctrl_Clear(index,len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -176,35 +246,17 @@ void EF_Ctrl_Load_Efuse_R0(void){
     return RomDriver_EF_Ctrl_Load_Efuse_R0();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Load_Efuse_R1(void){
-    return RomDriver_EF_Ctrl_Load_Efuse_R1();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Program_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len){
-    return RomDriver_EF_Ctrl_Program_Direct(region,index,data,len);
-}
-
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){
     return RomDriver_EF_Ctrl_Program_Direct_R0(index,data,len);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Program_Direct_R1(uint32_t index, uint32_t *data, uint32_t len){
-    return RomDriver_EF_Ctrl_Program_Direct_R1(index,data,len);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void EF_Ctrl_Program_Efuse_0(void){
     return RomDriver_EF_Ctrl_Program_Efuse_0();
 }
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Program_Efuse_1(void){
-    return RomDriver_EF_Ctrl_Program_Efuse_1();
-}
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim){
@@ -216,21 +268,26 @@ void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len){
     return RomDriver_EF_Ctrl_Read_AES_Key(index,keyData,len);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_DCDC11_Trim(Efuse_Ana_DCDC11_Trim_Type *trim){
-    return RomDriver_EF_Ctrl_Read_DCDC11_Trim(trim);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_DCDC18_Trim(Efuse_Ana_DCDC18_Trim_Type *trim){
-    return RomDriver_EF_Ctrl_Read_DCDC18_Trim(trim);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void EF_Ctrl_Read_Dbg_Pwd(uint8_t slot, uint32_t *passWdLow, uint32_t *passWdHigh){
     return RomDriver_EF_Ctrl_Read_Dbg_Pwd(slot,passWdLow,passWdHigh);
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void EF_Ctrl_Read_DcdcDis_Trim(Efuse_Ana_DcdcDis_Type *trim){
+    return RomDriver_EF_Ctrl_Read_DcdcDis_Trim(trim);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void EF_Ctrl_Read_DcdcVoutSel_Trim(Efuse_Ana_DcdcVoutSel_Type *trim){
+    return RomDriver_EF_Ctrl_Read_DcdcVoutSel_Trim(trim);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void EF_Ctrl_Read_DcdcVoutTrim_Trim(Efuse_Ana_DcdcVoutTrim_Type *trim){
+    return RomDriver_EF_Ctrl_Read_DcdcVoutTrim_Trim(trim);
+}
+
 #if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo){
@@ -238,29 +295,36 @@ void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo){
 }
 #endif
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len){
-    return RomDriver_EF_Ctrl_Read_Direct(region,index,data,len);
-}
-
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len){
     return RomDriver_EF_Ctrl_Read_Direct_R0(index,data,len);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_Direct_R1(uint32_t index, uint32_t *data, uint32_t len){
-    return RomDriver_EF_Ctrl_Read_Direct_R1(index,data,len);
+void EF_Ctrl_Read_Ldo11socVoutTrim_Trim(Efuse_Ana_Ldo11socVoutTrim_Type *trim){
+    return RomDriver_EF_Ctrl_Read_Ldo11socVoutTrim_Trim(trim);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_LDO18FLASH_Trim(Efuse_Ana_LDO18FLASH_Trim_Type *trim){
-    return RomDriver_EF_Ctrl_Read_LDO18FLASH_Trim(trim);
+void EF_Ctrl_Read_Ldo18ioBypass_Trim(Efuse_Ana_Ldo18ioBypass_Type *trim){
+    return RomDriver_EF_Ctrl_Read_Ldo18ioBypass_Trim(trim);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_LDO18IO_Vout_Trim(Efuse_Ana_LDO18IO_VOUT_Trim_Type *trim){
-    return RomDriver_EF_Ctrl_Read_LDO18IO_Vout_Trim(trim);
+void EF_Ctrl_Read_Ldo18ioVoutSel_Trim(Efuse_Ana_Ldo18ioVoutSel_Type *trim){
+    return RomDriver_EF_Ctrl_Read_Ldo18ioVoutSel_Trim(trim);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void EF_Ctrl_Read_Ldo18ioVoutTrim_Trim(Efuse_Ana_Ldo18ioVoutTrim_Type *trim){
+    return RomDriver_EF_Ctrl_Read_Ldo18ioVoutTrim_Trim(trim);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void EF_Ctrl_Read_Ldo33VoutTrim_Trim(Efuse_Ana_Ldo33VoutTrim_Type *trim){
+    return RomDriver_EF_Ctrl_Read_Ldo33VoutTrim_Trim(trim);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -294,13 +358,8 @@ void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_USB20RCAL_Trim(Efuse_Ana_USB20RCAL_Trim_Type *trim){
-    return RomDriver_EF_Ctrl_Read_USB20RCAL_Trim(trim);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Read_Xtal_Trim_RC32M(uint8_t *forceNoTrim, uint8_t *noXtal){
-    return RomDriver_EF_Ctrl_Read_Xtal_Trim_RC32M(forceNoTrim,noXtal);
+void EF_Ctrl_Read_Usb20RcalCode_Trim(Efuse_Ana_Usb20RcalCode_Type *trim){
+    return RomDriver_EF_Ctrl_Read_Usb20RcalCode_Trim(trim);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -323,11 +382,6 @@ void EF_Ctrl_Sw_AHB_Clk_0(void){
     return RomDriver_EF_Ctrl_Sw_AHB_Clk_0();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-void EF_Ctrl_Sw_AHB_Clk_1(void){
-    return RomDriver_EF_Ctrl_Sw_AHB_Clk_1();
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program){
     return RomDriver_EF_Ctrl_Write_AES_Key(index,keyData,len,program);
@@ -378,20 +432,22 @@ void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program){
     return RomDriver_EF_Ctrl_Writelock_Sw_Usage(index,program);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst){
-    return RomDriver_GLB_AHB_DSP_Software_Reset(swrst);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst){
     return RomDriver_GLB_AHB_MCU_Software_Reset(swrst);
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_AUPLL_Ref_Clk_Sel(GLB_PLL_REF_CLK_Type refClk){
+    return RomDriver_GLB_AUPLL_Ref_Clk_Sel(refClk);
+}
+
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_BMX_TO_Init(BMX_TO_Cfg_Type *BmxCfg){
     return RomDriver_GLB_BMX_TO_Init(BmxCfg);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Clr_BMX_TO_Status(void){
@@ -404,83 +460,23 @@ BL_Err_Type GLB_Clr_EMI_Reset_Gate(void){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList){
-    return RomDriver_GLB_Config_AUDIO_PLL(xtalType,pllCfgList);
+BL_Err_Type GLB_Clr_Reset_Reason(void){
+    return RomDriver_GLB_Clr_Reset_Reason();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList){
-    return RomDriver_GLB_Config_CPU_PLL(xtalType,pllCfgList);
+BL_Err_Type GLB_Config_SDIO_Host_Interrupt_CPU(uint8_t enable){
+    return RomDriver_GLB_Config_SDIO_Host_Interrupt_CPU(enable);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList){
-    return RomDriver_GLB_Config_MIPI_PLL(xtalType,pllCfgList);
+BL_Err_Type GLB_Config_SDIO_Host_Reset_SDU(uint8_t enable){
+    return RomDriver_GLB_Config_SDIO_Host_Reset_SDU(enable);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio){
-    return RomDriver_GLB_Config_MIPI_PLL_Div(divEn,divRatio);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList){
-    return RomDriver_GLB_Config_UHS_PLL(xtalType,pllCfgList);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList){
-    return RomDriver_GLB_Config_WIFI_PLL(xtalType,pllCfgList);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP0_Clock_Disable(void){
-    return RomDriver_GLB_DSP0_Clock_Disable();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP0_Clock_Enable(void){
-    return RomDriver_GLB_DSP0_Clock_Enable();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_Clr_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType){
-    return RomDriver_GLB_DSP_Clr_MCU_IntStatus(intType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart){
-    return RomDriver_GLB_DSP_Codec_Sub_Reset(codecPart);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part){
-    return RomDriver_GLB_DSP_DSP2_Sub_Reset(dsp2Part);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart){
-    return RomDriver_GLB_DSP_Image_Sensor_Reset(imageSensorPart);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart){
-    return RomDriver_GLB_DSP_Peripheral_Reset(periPart);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart){
-    return RomDriver_GLB_DSP_SW_System_Reset(sysPart);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_Set_LP_IntEn(uint8_t enable, GLB_LP_ALL_INT_Type intType){
-    return RomDriver_GLB_DSP_Set_LP_IntEn(enable,intType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_DSP_Set_MCU_IntMask(GLB_MCU_ALL_INT_Type intType, BL_Mask_Type intMask){
-    return RomDriver_GLB_DSP_Set_MCU_IntMask(intType,intMask);
+BL_Err_Type GLB_Config_SDIO_Host_Reset_System(uint8_t enable){
+    return RomDriver_GLB_Config_SDIO_Host_Reset_System(enable);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -489,33 +485,13 @@ BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Get_DSP_PBCLK_Div(uint8_t *dspPBclkDiv){
-    return RomDriver_GLB_Get_DSP_PBCLK_Div(dspPBclkDiv);
+BL_Err_Type GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv){
+    return RomDriver_GLB_Get_MCU_System_CLK_Div(mcuClkDiv,mcuPBclkDiv);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Get_DSP_System_CLK_Div(uint8_t *dspClkDiv, uint8_t *dspBclkDiv){
-    return RomDriver_GLB_Get_DSP_System_CLK_Div(dspClkDiv,dspBclkDiv);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Get_MCU_System_CLK_Div(uint8_t *mcuClkDiv, uint8_t *mcuPBclkDiv, uint8_t *lpClkDiv){
-    return RomDriver_GLB_Get_MCU_System_CLK_Div(mcuClkDiv,mcuPBclkDiv,lpClkDiv);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Halt_CPU(GLB_CORE_ID_Type coreID){
-    return RomDriver_GLB_Halt_CPU(coreID);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_IR_LED_Driver_Disable(void){
-    return RomDriver_GLB_IR_LED_Driver_Disable();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_IR_LED_Driver_Enable(void){
-    return RomDriver_GLB_IR_LED_Driver_Enable();
+BL_Err_Type GLB_Get_Reset_Reason(GLB_RESET_RECORD_Type *reason){
+    return RomDriver_GLB_Get_Reset_Reason(reason);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -538,26 +514,11 @@ BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable){
     return RomDriver_GLB_Invert_ETH_TX_CLK(enable);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_MCU_Clr_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType){
-    return RomDriver_GLB_MCU_Clr_DSP_IntStatus(intType);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_MCU_SW_System_Reset(GLB_MCU_SW_SYSTEM_Type sysPart){
     return RomDriver_GLB_MCU_SW_System_Reset(sysPart);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_MCU_Set_DSP_IntMask(GLB_DSP_ALL_INT_Type intType, BL_Mask_Type intMask){
-    return RomDriver_GLB_MCU_Set_DSP_IntMask(intType,intMask);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Output_EMAC_CLK(uint8_t gpio){
-    return RomDriver_GLB_Output_EMAC_CLK(gpio);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips){
     return RomDriver_GLB_PER_Clock_Gate(ips);
@@ -584,23 +545,23 @@ BL_Err_Type GLB_Platform_Wakeup_PDS_Enable(uint8_t enable){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Power_Off_MU_PLL(GLB_MU_PLL_Type pllType){
-    return RomDriver_GLB_Power_Off_MU_PLL(pllType);
+BL_Err_Type GLB_Power_Off_AUPLL(void){
+    return RomDriver_GLB_Power_Off_AUPLL();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Power_Off_WAC_PLL(GLB_WAC_PLL_Type pllType){
-    return RomDriver_GLB_Power_Off_WAC_PLL(pllType);
+BL_Err_Type GLB_Power_Off_WIFIPLL(void){
+    return RomDriver_GLB_Power_Off_WIFIPLL();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Power_On_MU_PLL(GLB_MU_PLL_Type pllType, const GLB_MU_PLL_Cfg_Type *const cfg, uint8_t waitStable){
-    return RomDriver_GLB_Power_On_MU_PLL(pllType,cfg,waitStable);
+BL_Err_Type GLB_Power_On_AUPLL(const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable){
+    return RomDriver_GLB_Power_On_AUPLL(cfg,waitStable);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, const GLB_WAC_PLL_Cfg_Type *const cfg, uint8_t waitStable){
-    return RomDriver_GLB_Power_On_WAC_PLL(pllType,cfg,waitStable);
+BL_Err_Type GLB_Power_On_WIFIPLL(const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable){
+    return RomDriver_GLB_Power_On_WIFIPLL(cfg,waitStable);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -609,8 +570,8 @@ BL_Err_Type GLB_Power_On_XTAL_And_PLL_CLK(GLB_XTAL_Type xtalType, GLB_PLL_Type p
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Release_CPU(GLB_CORE_ID_Type coreID){
-    return RomDriver_GLB_Release_CPU(coreID);
+BL_Err_Type GLB_SPI_Sig_Swap_Set(GLB_SPI_SIG_SWAP_GRP_Type group, uint8_t swap){
+    return RomDriver_GLB_SPI_Sig_Swap_Set(group,swap);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -628,80 +589,62 @@ BL_Err_Type GLB_SW_System_Reset(void){
     return RomDriver_GLB_SW_System_Reset();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Sel_DSP_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin){
-    return RomDriver_GLB_Sel_DSP_TMR_GPIO_Clock(gpioPin);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Sel_MCU_TMR_GPIO_Clock(GLB_GPIO_Type gpioPin){
     return RomDriver_GLB_Sel_MCU_TMR_GPIO_Clock(gpioPin);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div){
     return RomDriver_GLB_Set_ADC_CLK(enable,clkSel,div);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div){
     return RomDriver_GLB_Set_Audio_ADC_CLK(enable,div);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn){
     return RomDriver_GLB_Set_Audio_AUTO_CLK(divEn);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Audio_DAC_CLK(uint8_t enable, uint8_t div){
-    return RomDriver_GLB_Set_Audio_DAC_CLK(enable,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Audio_PDM_CLK(uint8_t enable, uint8_t div){
-    return RomDriver_GLB_Set_Audio_PDM_CLK(enable,div);
+BL_Err_Type GLB_Set_Audio_SOLO_CLK(uint8_t enable, uint8_t div){
+    return RomDriver_GLB_Set_Audio_SOLO_CLK(enable,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_Auto_Calc_Xtal_Type(GLB_XTAL_Type calcXtalType){
     return RomDriver_GLB_Set_Auto_Calc_Xtal_Type(calcXtalType);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div){
     return RomDriver_GLB_Set_CAM_CLK(enable,clkSel,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_CPU_Reset_Address(GLB_CORE_ID_Type coreID, uint32_t addr){
     return RomDriver_GLB_Set_CPU_Reset_Address(coreID,addr);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_CSI_DSI_CLK_Sel(GLB_CSI_DSI_CLK_SEL_Type csiClkSel, GLB_CSI_DSI_CLK_SEL_Type dsiClkSel){
-    return RomDriver_GLB_Set_CSI_DSI_CLK_Sel(csiClkSel,dsiClkSel);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType){
-    return RomDriver_GLB_Set_Chip_Clock_Out0_Sel(clkOutType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType){
-    return RomDriver_GLB_Set_Chip_Clock_Out1_Sel(clkOutType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType){
-    return RomDriver_GLB_Set_Chip_Clock_Out2_Sel(clkOutType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType){
-    return RomDriver_GLB_Set_Chip_Clock_Out3_Sel(clkOutType);
+BL_Err_Type GLB_Set_DBI_CLK(uint8_t enable, GLB_DBI_CLK_Type clkSel, uint8_t div){
+    return RomDriver_GLB_Set_DBI_CLK(enable,clkSel,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensationEn, uint16_t div){
@@ -723,136 +666,6 @@ BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk){
     return RomDriver_GLB_Set_DMA_CLK(enable,clk);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div){
-    return RomDriver_GLB_Set_DSP_CNN_CLK(enable,clkSel,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div){
-    return RomDriver_GLB_Set_DSP_DP_CLK(enable,clkSel,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div){
-    return RomDriver_GLB_Set_DSP_H264_CLK(enable,clkSel,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_I2C0_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div){
-    return RomDriver_GLB_Set_DSP_I2C0_CLK(enable,clkSel,divEn,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, uint8_t divEn, uint8_t div){
-    return RomDriver_GLB_Set_DSP_I2C1_CLK(enable,clkSel,divEn,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div){
-    return RomDriver_GLB_Set_DSP_DSP2_CLK(enable,clkSel,div);
-}
-#if 0
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel){
-    return RomDriver_GLB_Set_DSP_L2SRAM_Available_Size(h2pfSramRel,vramSramRel,dspl2SramRel,blaiSramRel);
-}
-#endif
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst){
-    return RomDriver_GLB_Set_DSP_MTimer_CLK(enable,div,rst);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_MUXPLL_CLK_Sel(GLB_DSP_PLL_CLK_Type pllClk){
-    return RomDriver_GLB_Set_DSP_MUXPLL_CLK_Sel(pllClk);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_Muxpll_160M_Sel(GLB_DSP_MUXPLL_160M_CLK_SEL_Type clkSel){
-    return RomDriver_GLB_Set_DSP_Muxpll_160M_Sel(clkSel);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_Muxpll_240M_Sel(GLB_DSP_MUXPLL_240M_CLK_SEL_Type clkSel){
-    return RomDriver_GLB_Set_DSP_Muxpll_240M_Sel(clkSel);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_Muxpll_320M_Sel(GLB_DSP_MUXPLL_320M_CLK_SEL_Type clkSel){
-    return RomDriver_GLB_Set_DSP_Muxpll_320M_Sel(clkSel);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_PBCLK(GLB_DSP_SYS_PBCLK_Type pbClkSel){
-    return RomDriver_GLB_Set_DSP_PBCLK(pbClkSel);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_PBCLK_Div(uint8_t dspPBclkDiv){
-    return RomDriver_GLB_Set_DSP_PBCLK_Div(dspPBclkDiv);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_PBROOT_CLK_Sel(GLB_DSP_PBROOT_CLK_Type pbrootClk){
-    return RomDriver_GLB_Set_DSP_PBROOT_CLK_Sel(pbrootClk);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_ROOT_CLK_Sel(GLB_DSP_ROOT_CLK_Type rootClk){
-    return RomDriver_GLB_Set_DSP_ROOT_CLK_Sel(rootClk);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod){
-    return RomDriver_GLB_Set_DSP_SPI_0_ACT_MOD_Sel(mod);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div){
-    return RomDriver_GLB_Set_DSP_SPI_CLK(enable,clkSel,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_System_CLK(GLB_DSP_SYS_CLK_Type clkFreq){
-    return RomDriver_GLB_Set_DSP_System_CLK(clkFreq);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_System_CLK_Div(uint8_t dspClkDiv, uint8_t dspBclkDiv){
-    return RomDriver_GLB_Set_DSP_System_CLK_Div(dspClkDiv,dspBclkDiv);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div){
-    return RomDriver_GLB_Set_DSP_UART0_CLK(enable,uartClk,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_UART1_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div){
-    return RomDriver_GLB_Set_DSP_UART1_CLK(enable,uartClk,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_DSP_XCLK_Sel(GLB_DSP_XCLK_Type xclk){
-    return RomDriver_GLB_Set_DSP_XCLK_Sel(xclk);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_t evenDiv){
-    return RomDriver_GLB_Set_Display_CLK(enable,srcClk,evenDiv);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_EMAC_CLK(uint8_t enable){
-    return RomDriver_GLB_Set_EMAC_CLK(enable);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_EMI_CLK(uint8_t enable, GLB_EMI_CLK_Type clkSel, uint32_t div){
-    return RomDriver_GLB_Set_EMI_CLK(enable,clkSel,div);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType){
     return RomDriver_GLB_Set_EM_Sel(emType);
@@ -863,34 +676,35 @@ BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel){
     return RomDriver_GLB_Set_ETH_REF_O_CLK_Sel(clkSel);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap){
-    return RomDriver_GLB_Set_Flash_IO_PARM(selEmbedded,swap);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue){
-    return RomDriver_GLB_Set_Flash_Id_Value(idValue);
+BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div){
+    return RomDriver_GLB_Set_PEC_CLK(enable,clkSel,div);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div){
     return RomDriver_GLB_Set_I2C_CLK(enable,clkSel,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_I2S_CLK(uint8_t refClkEn, uint8_t refClkDiv, GLB_I2S_DI_REF_CLK_Type inRef, GLB_I2S_DO_REF_CLK_Type outRef){
     return RomDriver_GLB_Set_I2S_CLK(refClkEn,refClkDiv,inRef,outRef);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div){
     return RomDriver_GLB_Set_IR_CLK(enable,clkSel,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_MCU_MTimer_CLK(uint8_t enable, uint16_t div, uint8_t rst){
-    return RomDriver_GLB_Set_MCU_MTimer_CLK(enable,div,rst);
+BL_Err_Type GLB_Set_ISP_Muxpll_80M_Sel(GLB_ISP_MUXPLL_80M_CLK_SEL_Type clkSel){
+    return RomDriver_GLB_Set_ISP_Muxpll_80M_Sel(clkSel);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -914,13 +728,8 @@ BL_Err_Type GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_Type clkFreq){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv, uint8_t lpClkDiv){
-    return RomDriver_GLB_Set_MCU_System_CLK_Div(mcuClkDiv,mcuPBclkDiv,lpClkDiv);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_PADC_CLK(uint8_t enable, uint16_t div){
-    return RomDriver_GLB_Set_PADC_CLK(enable,div);
+BL_Err_Type GLB_Set_MCU_System_CLK_Div(uint8_t mcuClkDiv, uint8_t mcuPBclkDiv){
+    return RomDriver_GLB_Set_MCU_System_CLK_Div(mcuClkDiv,mcuPBclkDiv);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -933,40 +742,51 @@ BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel){
     return RomDriver_GLB_Set_PKA_CLK_Sel(clkSel);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_PSram_CLK(uint8_t id, uint8_t enable, GLB_PSRAM_PLL_Type pll, uint8_t div){
-    return RomDriver_GLB_Set_PSram_CLK(id,enable,pll,div);
+BL_Err_Type GLB_Set_PSRAMB_CLK_Sel(uint8_t enable, GLB_PSRAMB_PLL_Type clkSel, uint8_t div){
+    return RomDriver_GLB_Set_PSRAMB_CLK_Sel(enable,clkSel,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_PWM1_IO_Sel(GLB_PWM1_IO_SEL_Type ioSel){
     return RomDriver_GLB_Set_PWM1_IO_Sel(ioSel);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_PWM2_IO_Sel(GLB_PWM2_IO_SEL_Type ioSel){
-    return RomDriver_GLB_Set_PWM2_IO_Sel(ioSel);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_Peripheral_DMA_CN(GLB_PERI_DMA_Type peri, GLB_PERI_DMA_CN_SEL_Type cn){
     return RomDriver_GLB_Set_Peripheral_DMA_CN(peri,cn);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div){
     return RomDriver_GLB_Set_SDH_CLK(enable,clkSel,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div){
     return RomDriver_GLB_Set_SF_CLK(enable,clkSel,div);
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_Set_SFlash2_IO_PARM(uint8_t swapIo3Io0){
+    return RomDriver_GLB_Set_SFlash2_IO_PARM(swapIo3Io0);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_Set_SFlash_IO_PARM(uint8_t selEmbedded, uint8_t swapIo3Io0, uint8_t swapIo2Cs){
+    return RomDriver_GLB_Set_SFlash_IO_PARM(selEmbedded,swapIo3Io0,swapIo2Cs);
+}
+
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div){
     return RomDriver_GLB_Set_SPI_CLK(enable,clkSel,div);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value){
@@ -984,8 +804,13 @@ BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Set_UART2_IO_Sel(GLB_UART2_IO_SEL_Type ioType){
-    return RomDriver_GLB_Set_UART2_IO_Sel(ioType);
+BL_Err_Type GLB_Set_SSC_CLK_From_WIFIPLL(uint8_t enable){
+    return RomDriver_GLB_Set_SSC_CLK_From_WIFIPLL(enable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_Set_Slave_Grp_0_CLK(GLB_SLAVE_GRP_0_Type slave, uint8_t enable, GLB_SLAVE_GRP_0_CLK_SEL_Type clkSel, uint32_t div){
+    return RomDriver_GLB_Set_Slave_Grp_0_CLK(slave,enable,clkSel,div);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -998,24 +823,24 @@ BL_Err_Type GLB_Set_USB_CLK_From_WIFIPLL(uint8_t enable){
     return RomDriver_GLB_Set_USB_CLK_From_WIFIPLL(enable);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState){
-    return RomDriver_GLB_Swap_DSP_SPI_0_MOSI_With_MISO(newState);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState){
     return RomDriver_GLB_Swap_MCU_SPI_0_MOSI_With_MISO(newState);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Trim_LDO18FLASH_Vout(void){
-    return RomDriver_GLB_Trim_LDO18FLASH_Vout();
+BL_Err_Type GLB_Trim_Ldo18ioBypass(void){
+    return RomDriver_GLB_Trim_Ldo18ioBypass();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Trim_LDO18IO_Vout(void){
-    return RomDriver_GLB_Trim_LDO18IO_Vout();
+BL_Err_Type GLB_Trim_Ldo18ioVoutSel(void){
+    return RomDriver_GLB_Trim_Ldo18ioVoutSel();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_Trim_Ldo18ioVoutTrim(void){
+    return RomDriver_GLB_Trim_Ldo18ioVoutTrim();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1029,18 +854,8 @@ BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type GLB_DSP_Get_LP_IntStatus(GLB_LP_ALL_INT_Type intType){
-    return RomDriver_GLB_DSP_Get_LP_IntStatus(intType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type GLB_DSP_Get_MCU_IntStatus(GLB_MCU_ALL_INT_Type intType){
-    return RomDriver_GLB_DSP_Get_MCU_IntStatus(intType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type GLB_MCU_Get_DSP_IntStatus(GLB_DSP_ALL_INT_Type intType){
-    return RomDriver_GLB_MCU_Get_DSP_IntStatus(intType);
+BL_Err_Type GLB_WIFIPLL_Ref_Clk_Sel(GLB_PLL_REF_CLK_Type refClk){
+    return RomDriver_GLB_WIFIPLL_Ref_Clk_Sel(refClk);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1048,36 +863,6 @@ GLB_CORE_ID_Type GLB_Get_Core_Type(void){
     return RomDriver_GLB_Get_Core_Type();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-GLB_DSP_MUXPLL_160M_CLK_SEL_Type GLB_Get_DSP_Muxpll_160M_Sel(void){
-    return RomDriver_GLB_Get_DSP_Muxpll_160M_Sel();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-GLB_DSP_MUXPLL_240M_CLK_SEL_Type GLB_Get_DSP_Muxpll_240M_Sel(void){
-    return RomDriver_GLB_Get_DSP_Muxpll_240M_Sel();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-GLB_DSP_MUXPLL_320M_CLK_SEL_Type GLB_Get_DSP_Muxpll_320M_Sel(void){
-    return RomDriver_GLB_Get_DSP_Muxpll_320M_Sel();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-GLB_DSP_PBROOT_CLK_Type GLB_Get_DSP_PBROOT_CLK_Sel(void){
-    return RomDriver_GLB_Get_DSP_PBROOT_CLK_Sel();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-GLB_DSP_ROOT_CLK_Type GLB_Get_DSP_ROOT_CLK_Sel(void){
-    return RomDriver_GLB_Get_DSP_ROOT_CLK_Sel();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-GLB_DSP_XCLK_Type GLB_Get_DSP_XCLK_Sel(void){
-    return RomDriver_GLB_Get_DSP_XCLK_Sel();
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 GLB_MCU_MUXPLL_160M_CLK_SEL_Type GLB_Get_MCU_Muxpll_160M_Sel(void){
     return RomDriver_GLB_Get_MCU_Muxpll_160M_Sel();
@@ -1088,11 +873,6 @@ GLB_MCU_MUXPLL_80M_CLK_SEL_Type GLB_Get_MCU_Muxpll_80M_Sel(void){
     return RomDriver_GLB_Get_MCU_Muxpll_80M_Sel();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint32_t GLB_Get_Flash_Id_Value(void){
-    return RomDriver_GLB_Get_Flash_Id_Value();
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 uint32_t GLB_Get_SRAM_PARM(void){
     return RomDriver_GLB_Get_SRAM_PARM();
@@ -1119,8 +899,8 @@ BL_Err_Type GLB_Clr_GPIO_IntStatus(GLB_GPIO_Type gpioPin){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type GLB_Embedded_Flash_Pad_Enable(void){
-    return RomDriver_GLB_Embedded_Flash_Pad_Enable();
+BL_Err_Type GLB_Embedded_Flash_Pad_Enable(uint8_t swapIo2Cs){
+    return RomDriver_GLB_Embedded_Flash_Pad_Enable(swapIo2Cs);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1209,12 +989,12 @@ BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type GLB_GPIO_Fifo_Disable(void){
+BL_Err_Type GLB_GPIO_Fifo_Disable(void){
     return RomDriver_GLB_GPIO_Fifo_Disable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type GLB_GPIO_Fifo_Enable(void){
+BL_Err_Type GLB_GPIO_Fifo_Enable(void){
     return RomDriver_GLB_GPIO_Fifo_Enable();
 }
 
@@ -1253,21 +1033,42 @@ BL_Err_Type HBN_Aon_Pad_Cfg(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio, HB
     return RomDriver_HBN_Aon_Pad_Cfg(aonPadHwCtrlEn,aonGpio,aonPadCfg);
 }
 
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Aon_Pad_Cfg_Set(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio){
+    return RomDriver_HBN_Aon_Pad_Cfg_Set(aonPadHwCtrlEn,aonGpio);
+}
+#endif
+
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2){
     return RomDriver_HBN_Aon_Pad_Ctrl(aonPadCtl1,aonPadCtl2);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec){
     return RomDriver_HBN_Aon_Pad_WakeUpCfg(puPdEn,trigMode,maskVal,dlyEn,dlySec);
 }
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Clear_Gpio_Keep(uint8_t gpioKeep){
+    return RomDriver_HBN_Clear_Gpio_Keep(gpioKeep);
+}
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType){
     return RomDriver_HBN_Clear_IRQ(irqType);
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Clear_PDS_Gpio_Keep(uint8_t gpioKeep){
+    return RomDriver_HBN_Clear_PDS_Gpio_Keep(gpioKeep);
+}
+
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Clear_RTC_Counter(void){
     return RomDriver_HBN_Clear_RTC_Counter();
@@ -1290,10 +1091,12 @@ BL_Err_Type HBN_Disable_AComp1_IRQ(void){
 }
 #endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Disable_BOD_IRQ(void){
     return RomDriver_HBN_Disable_BOD_IRQ();
 }
+#endif
 
 #if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1307,29 +1110,50 @@ BL_Err_Type HBN_Enable_AComp1_IRQ(void){
 }
 #endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Enable_BOD_IRQ(void){
     return RomDriver_HBN_Enable_BOD_IRQ();
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Enable_RTC_Counter(void){
     return RomDriver_HBN_Enable_RTC_Counter();
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_GPIO_INT_Disable(void){
     return RomDriver_HBN_GPIO_INT_Disable();
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType){
     return RomDriver_HBN_GPIO_INT_Enable(gpioIntTrigType);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Get_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg){
-    return RomDriver_HBN_Get_RTC_Misc_Cfg(cfg);
+BL_Err_Type HBN_Get_Flash_Power_Delay(uint8_t *flashPwrDly){
+    return RomDriver_HBN_Get_Flash_Power_Delay(flashPwrDly);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Get_Gpio_Keep(uint8_t *gpioKeep){
+    return RomDriver_HBN_Get_Gpio_Keep(gpioKeep);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Get_Ldo18io_Power_Delay_Config(uint16_t *pwrOffDly, uint16_t *pwrOnDly){
+    return RomDriver_HBN_Get_Ldo18io_Power_Delay_Config(pwrOffDly,pwrOnDly);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Get_PDS_Gpio_Keep(uint8_t *gpioKeep){
+    return RomDriver_HBN_Get_PDS_Gpio_Keep(gpioKeep);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1347,40 +1171,47 @@ BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable){
     return RomDriver_HBN_Hw_Pu_Pd_Cfg(enable);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_PD_RC32K_All_State(void){
-    return RomDriver_HBN_PD_RC32K_All_State();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_PD_RC32K_In_Poff(void){
-    return RomDriver_HBN_PD_RC32K_In_Poff();
+BL_Err_Type HBN_Keep_On_RC32K(void){
+    return RomDriver_HBN_Keep_On_RC32K();
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_PIR_Disable(void){
     return RomDriver_HBN_PIR_Disable();
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_PIR_Enable(void){
     return RomDriver_HBN_PIR_Enable();
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf){
     return RomDriver_HBN_PIR_HPF_Sel(hpf);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg){
     return RomDriver_HBN_PIR_INT_Config(pirIntCfg);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf){
     return RomDriver_HBN_PIR_LPF_Sel(lpf);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal){
@@ -1397,11 +1228,6 @@ BL_Err_Type HBN_Power_Off_Xtal_32K(void){
     return RomDriver_HBN_Power_Off_Xtal_32K();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Power_On_RC32K(void){
-    return RomDriver_HBN_Power_On_RC32K();
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Power_On_Xtal_32K(void){
     return RomDriver_HBN_Power_On_Xtal_32K();
@@ -1412,21 +1238,42 @@ BL_Err_Type HBN_Reset(void){
     return RomDriver_HBN_Reset();
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg){
     return RomDriver_HBN_Set_BOD_Cfg(cfg);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode){
     return RomDriver_HBN_Set_BOD_Config(enable,threshold,mode);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_Core_Reboot_Config(uint8_t core, uint8_t hcfg){
     return RomDriver_HBN_Set_Core_Reboot_Config(core,hcfg);
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Set_Flash_Power_Delay(uint8_t flashPwrDly){
+    return RomDriver_HBN_Set_Flash_Power_Delay(flashPwrDly);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Set_GPADC_CLK_Sel(HBN_GPADC_CLK_Type clkSel){
+    return RomDriver_HBN_Set_GPADC_CLK_Sel(clkSel);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Set_Gpio_Keep(uint8_t gpioKeep){
+    return RomDriver_HBN_Set_Gpio_Keep(gpioKeep);
+}
+#endif
+
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_HRAM_Ret(void){
     return RomDriver_HBN_Set_HRAM_Ret();
@@ -1437,21 +1284,11 @@ BL_Err_Type HBN_Set_HRAM_slp(void){
     return RomDriver_HBN_Set_HRAM_slp();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Set_Hand_Off_Config(uint8_t dcfg){
-    return RomDriver_HBN_Set_Hand_Off_Config(dcfg);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Set_IO4041_As_Xtal_32K_IO(uint8_t xtal32kIoEn){
-    return RomDriver_HBN_Set_IO4041_As_Xtal_32K_IO(xtal32kIoEn);
-}
-#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel){
     return RomDriver_HBN_Set_Ldo11_All_Vout(ldoLevel);
 }
-#endif
+
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel){
     return RomDriver_HBN_Set_Ldo11_Aon_Vout(ldoLevel);
@@ -1461,15 +1298,15 @@ __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel){
     return RomDriver_HBN_Set_Ldo11_Rt_Vout(ldoLevel);
 }
-#if 0
+
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Set_Ldo11_Rtc_Vout(HBN_LDO_LEVEL_Type ldoLevel){
-    return RomDriver_HBN_Set_Ldo11_Rtc_Vout(ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel){
+    return RomDriver_HBN_Set_Ldo11_Soc_Vout(ldoLevel);
 }
-#endif
+
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Set_Ldo18flash_Repower_Delay(uint8_t delay){
-    return RomDriver_HBN_Set_Ldo18flash_Repower_Delay(delay);
+BL_Err_Type HBN_Set_Ldo18io_Power_Delay_Config(uint16_t pwrOffDly, uint16_t pwrOnDly){
+    return RomDriver_HBN_Set_Ldo18io_Power_Delay_Config(pwrOffDly,pwrOnDly);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1483,24 +1320,23 @@ BL_Err_Type HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_Type xclk){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Set_MM_Power_Config(uint8_t pcfg){
-    return RomDriver_HBN_Set_MM_Power_Config(pcfg);
+BL_Err_Type HBN_Set_PDS_Gpio_Keep(uint8_t gpioKeep){
+    return RomDriver_HBN_Set_PDS_Gpio_Keep(gpioKeep);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval){
     return RomDriver_HBN_Set_PIR_Interval(interval);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold){
     return RomDriver_HBN_Set_PIR_Threshold(threshold);
 }
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type HBN_Set_RTC_Misc_Cfg(HBN_RTC_MISC_Type *cfg){
-    return RomDriver_HBN_Set_RTC_Misc_Cfg(cfg);
-}
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode){
@@ -1517,6 +1353,11 @@ BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel){
     return RomDriver_HBN_Set_UART_CLK_Sel(clkSel);
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Set_User_Boot_Config(uint8_t ubCfg){
+    return RomDriver_HBN_Set_User_Boot_Config(ubCfg);
+}
+
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr){
     return RomDriver_HBN_Set_Wakeup_Addr(addr);
@@ -1527,6 +1368,11 @@ BL_Err_Type HBN_Set_Xtal_Type(uint8_t xtalType){
     return RomDriver_HBN_Set_Xtal_Type(xtalType);
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type HBN_Trim_Ldo33VoutTrim(void){
+    return RomDriver_HBN_Trim_Ldo33VoutTrim();
+}
+
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type HBN_Trim_RC32K(void){
     return RomDriver_HBN_Trim_RC32K();
@@ -1552,11 +1398,6 @@ HBN_MCU_XCLK_Type HBN_Get_MCU_XCLK_Sel(void){
     return RomDriver_HBN_Get_MCU_XCLK_Sel();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint16_t HBN_Get_Ldo18flash_Repower_Config(void){
-    return RomDriver_HBN_Get_Ldo18flash_Repower_Config();
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 uint16_t HBN_Get_PIR_Interval(void){
     return RomDriver_HBN_Get_PIR_Interval();
@@ -1582,34 +1423,33 @@ uint8_t HBN_Get_Core_Unhalt_Config(void){
     return RomDriver_HBN_Get_Core_Unhalt_Config();
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint8_t HBN_Get_Hand_Off_Config(void){
-    return RomDriver_HBN_Get_Hand_Off_Config();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint8_t HBN_Get_MM_Power_Config(void){
-    return RomDriver_HBN_Get_MM_Power_Config();
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 uint8_t HBN_Get_Pin_Wakeup_Mode(void){
     return RomDriver_HBN_Get_Pin_Wakeup_Mode();
 }
 
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint8_t HBN_Get_User_Boot_Config(void){
+    return RomDriver_HBN_Get_User_Boot_Config();
+}
+
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq){
     return RomDriver_HBN_Enable(aGPIOIeCfg,ldoLevel,hbnLevel,dcdcPuSeq);
 }
+#endif
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg){
     return RomDriver_HBN_Mode_Enter(cfg);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_HBN_Power_Down_Flash(flashCfg);
+void HBN_Power_Down_Flash(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_HBN_Power_Down_Flash(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1682,30 +1522,29 @@ BL_Err_Type L1C_Set_Wrap(uint8_t en){
     return RomDriver_L1C_Set_Wrap(en);
 }
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-int L1C_Get_None_Cache_Addr(uintptr_t addr){
-    return RomDriver_L1C_Get_None_Cache_Addr(addr);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-int L1C_Is_DCache_Range(uintptr_t addr){
-    return RomDriver_L1C_Is_DCache_Range(addr);
-}
-
 __ALWAYS_INLINE ATTR_TCM_SECTION
 void L1C_DCache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn){
     return RomDriver_L1C_DCache_Write_Set(wtEn,wbEn,waEn);
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, uint32_t pdsSleepCnt){
-    return RomDriver_PDS_Default_Level_Config(defaultLvCfg,ram1Cfg,ram2Cfg,pdsSleepCnt);
+BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt){
+    return RomDriver_PDS_Default_Level_Config(defaultLvCfg,pdsSleepCnt);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type PDS_Disable_GPIO_Keep(void){
+    return RomDriver_PDS_Disable_GPIO_Keep();
 }
 
+#if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt){
     return RomDriver_PDS_Enable(cfg,cfg4,pdsSleepCnt);
 }
+#endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
 BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3, PDS_CTL5_Type *cfg5){
@@ -1723,27 +1562,17 @@ BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Power_On_MM_System(void){
-    return RomDriver_PDS_Power_On_MM_System();
+BL_Err_Type PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg, PDS_CTRL_RAM3_Type *ram3Cfg, PDS_CTRL_RAM4_Type *ram4Cfg){
+    return RomDriver_PDS_RAM_Config(ram1Cfg,ram2Cfg,ram3Cfg,ram4Cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_RAM_Config(PDS_CTRL_RAM1_Type *ram1Cfg, PDS_CTRL_RAM2_Type *ram2Cfg){
-    return RomDriver_PDS_RAM_Config(ram1Cfg,ram2Cfg);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Reset_LP_RTC(void){
-    return RomDriver_PDS_Reset_LP_RTC();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg){
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg){
     return RomDriver_PDS_Set_Flash_Pad_Pull_None(pinCfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg){
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg){
     return RomDriver_PDS_Set_Flash_Pad_Pull_None_Fast(pinCfg);
 }
 
@@ -1763,38 +1592,8 @@ BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRI
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(GLB_GPIO_Type pad, uint8_t pu, uint8_t pd, uint8_t ie){
-    return RomDriver_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(pad,pu,pd,ie);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_LP_Clock_Disable(void){
-    return RomDriver_PDS_Set_LP_Clock_Disable();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_LP_Clock_Enable(void){
-    return RomDriver_PDS_Set_LP_Clock_Enable();
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_LP_RTC_CLK(uint8_t enable, uint16_t div){
-    return RomDriver_PDS_Set_LP_RTC_CLK(enable,div);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_LP_Reset_Address(uint32_t addr){
-    return RomDriver_PDS_Set_LP_Reset_Address(addr);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_LP_System_CLK(PDS_LP_SYS_CLK_Type clkFreq){
-    return RomDriver_PDS_Set_LP_System_CLK(clkFreq);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type PDS_Set_LP_System_CLK_Div(uint8_t div){
-    return RomDriver_PDS_Set_LP_System_CLK_Div(div);
+BL_Err_Type PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(PDS_GPIO_GROUP_SET_Type grp, uint8_t pu, uint8_t pd, uint8_t ie){
+    return RomDriver_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie(grp,pu,pd,ie);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
@@ -1848,689 +1647,590 @@ BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType){
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type PDS_Get_MM_System_Power_On_State(void){
-    return RomDriver_PDS_Get_MM_System_Power_On_State();
+int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin){
+    return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SF_Cfg_Deinit_Ext_Flash_Gpio(uint8_t extFlashPin){
-    return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(extFlashPin);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SF_Cfg_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){
-    return RomDriver_SF_Cfg_Flash_Init(sel,pSfCtrlCfg,pBank2Cfg);
+int bflb_sf_cfg_flash_init(uint8_t sel, const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg){
+    return RomDriver_SF_Cfg_Flash_Init(sel,p_sf_ctrl_cfg,p_bank2_cfg);
 }
 
 #if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flashID,pFlashCfg,group,bank);
+int bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id,flash_cfg);
 }
 #endif
 
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(uint32_t flashID, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext(flashID,pFlashCfg,group,bank);
+__ALWAYS_INLINE
+int bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin){
+    return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SF_Cfg_Init_Ext_Flash_Gpio(uint8_t extFlashPin){
-    return RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(extFlashPin);
+int bflb_sf_cfg_init_flash2_gpio(uint8_t swap){
+    return RomDriver_SF_Cfg_Init_Flash2_Gpio(swap);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SF_Cfg_Init_Flash_Gpio(SF_Ctrl_Pin_Select flashPinCfg, uint8_t restoreDefault){
-    return RomDriver_SF_Cfg_Init_Flash_Gpio(flashPinCfg,restoreDefault);
+int bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default){
+    return RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg,restore_default);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SF_Cfg_Sbus2_Flash_Init(SF_Ctrl_Pin_Select sel, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){
-    return RomDriver_SF_Cfg_Sbus2_Flash_Init(sel,pBank2Cfg);
+int bflb_sf_cfg_sbus2_flash_init(uint8_t sel, const struct sf_ctrl_bank2_cfg *p_bank2_cfg){
+    return RomDriver_SF_Cfg_Sbus2_Flash_Init(sel,p_bank2_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-uint32_t SF_Cfg_Flash_Identify(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SF_Cfg_Flash_Identify(callFromFlash,flashPinCfg,restoreDefault,pFlashCfg,group,bank);
+uint32_t bflb_sf_cfg_flash_identify(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default, spi_flash_cfg_type *flash_cfg, uint8_t group, uint8_t bank){
+    return RomDriver_SF_Cfg_Flash_Identify(call_from_flash,flash_pin_cfg,restore_default,flash_cfg,group,bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-uint32_t SF_Cfg_Flash_Identify_Ext(uint8_t callFromFlash, uint8_t flashPinCfg, uint8_t restoreDefault, SPI_Flash_Cfg_Type *pFlashCfg, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SF_Cfg_Flash_Identify_Ext(callFromFlash,flashPinCfg,restoreDefault,pFlashCfg,group,bank);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type SF_Ctrl_GetBusyState(void){
+uint8_t bflb_sf_ctrl_get_busy_state(void){
     return RomDriver_SF_Ctrl_GetBusyState();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type SF_Ctrl_Is_AES_Enable(void){
+uint8_t bflb_sf_ctrl_is_aes_enable(void){
     return RomDriver_SF_Ctrl_Is_AES_Enable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type SF_Ctrl_Is_Sbus2_Enable(void){
+uint8_t bflb_sf_ctrl_is_sbus2_enable(void){
     return RomDriver_SF_Ctrl_Is_Sbus2_Enable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-uint32_t SF_Ctrl_Get_Flash_Image_Offset(uint8_t group, SF_Ctrl_Bank_Select bank){
+uint32_t bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank){
     return RomDriver_SF_Ctrl_Get_Flash_Image_Offset(group,bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-uint8_t SF_Ctrl_Get_Clock_Delay(void){
+uint8_t bflb_sf_ctrl_get_clock_delay(void){
     return RomDriver_SF_Ctrl_Get_Clock_Delay();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-uint8_t SF_Ctrl_Get_Wrap_Queue_Value(void){
+uint8_t bflb_sf_ctrl_get_wrap_queue_value(void){
     return RomDriver_SF_Ctrl_Get_Wrap_Queue_Value();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_32bits_Addr_En(BL_Fun_Type en32BitsAddr){
-    return RomDriver_SF_Ctrl_32bits_Addr_En(en32BitsAddr);
+void bflb_sf_ctrl_32bits_addr_en(BL_Fun_Type en_32bits_addr){
+    return RomDriver_SF_Ctrl_32bits_Addr_En(en_32bits_addr);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Disable(void){
+void bflb_sf_ctrl_aes_disable(void){
     return RomDriver_SF_Ctrl_AES_Disable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Enable(void){
+void bflb_sf_ctrl_aes_enable(void){
     return RomDriver_SF_Ctrl_AES_Enable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Enable_BE(void){
+void bflb_sf_ctrl_aes_enable_be(void){
     return RomDriver_SF_Ctrl_AES_Enable_BE();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Enable_LE(void){
+void bflb_sf_ctrl_aes_enable_le(void){
     return RomDriver_SF_Ctrl_AES_Enable_LE();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset){
-    return RomDriver_SF_Ctrl_AES_Set_IV(region,iv,addrOffset);
+void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset){
+    return RomDriver_SF_Ctrl_AES_Set_IV(region,iv,addr_offset);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset){
-    return RomDriver_SF_Ctrl_AES_Set_IV_BE(region,iv,addrOffset);
+void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset){
+    return RomDriver_SF_Ctrl_AES_Set_IV_BE(region,iv,addr_offset);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){
-    return RomDriver_SF_Ctrl_AES_Set_Key(region,key,keyType);
+void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type){
+    return RomDriver_SF_Ctrl_AES_Set_Key(region,key,key_type);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){
-    return RomDriver_SF_Ctrl_AES_Set_Key_BE(region,key,keyType);
+void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type){
+    return RomDriver_SF_Ctrl_AES_Set_Key_BE(region,key,key_type);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Set_Mode(SF_Ctrl_AES_Mode_Type mode){
+void bflb_sf_ctrl_aes_set_mode(uint8_t mode){
     return RomDriver_SF_Ctrl_AES_Set_Mode(mode);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_Set_Region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked){
-    return RomDriver_SF_Ctrl_AES_Set_Region(region,enable,hwKey,startAddr,endAddr,locked);
+void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t start_addr, uint32_t end_addr, uint8_t locked){
+    return RomDriver_SF_Ctrl_AES_Set_Region(region,enable,hwKey,start_addr,end_addr,locked);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_XTS_Set_IV(uint8_t region, uint8_t *iv, uint32_t addrOffset){
-    return RomDriver_SF_Ctrl_AES_XTS_Set_IV(region,iv,addrOffset);
+void bflb_sf_ctrl_aes_xts_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset){
+    return RomDriver_SF_Ctrl_AES_XTS_Set_IV(region,iv,addr_offset);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_XTS_Set_IV_BE(uint8_t region, uint8_t *iv, uint32_t addrOffset){
-    return RomDriver_SF_Ctrl_AES_XTS_Set_IV_BE(region,iv,addrOffset);
+void bflb_sf_ctrl_aes_xts_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset){
+    return RomDriver_SF_Ctrl_AES_XTS_Set_IV_BE(region,iv,addr_offset);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_XTS_Set_Key(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){
-    return RomDriver_SF_Ctrl_AES_XTS_Set_Key(region,key,keyType);
+void bflb_sf_ctrl_aes_xts_set_key(uint8_t region, uint8_t *key, uint8_t key_type){
+    return RomDriver_SF_Ctrl_AES_XTS_Set_Key(region,key,key_type);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_AES_XTS_Set_Key_BE(uint8_t region, uint8_t *key, SF_Ctrl_AES_Key_Type keyType){
-    return RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE(region,key,keyType);
+void bflb_sf_ctrl_aes_xts_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type){
+    return RomDriver_SF_Ctrl_AES_XTS_Set_Key_BE(region,key,key_type);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Bank2_Enable(const SF_Ctrl_Bank2_Cfg *bank2Cfg){
-    return RomDriver_SF_Ctrl_Bank2_Enable(bank2Cfg);
+void bflb_sf_ctrl_bank2_enable(const struct sf_ctrl_bank2_cfg *bank2_cfg){
+    return RomDriver_SF_Ctrl_Bank2_Enable(bank2_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Cmds_Set(SF_Ctrl_Cmds_Cfg *cmdsCfg, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SF_Ctrl_Cmds_Set(cmdsCfg,bank);
+void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t bank){
+    return RomDriver_SF_Ctrl_Cmds_Set(cmds_cfg,bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Disable(void){
+void bflb_sf_ctrl_disable(void){
     return RomDriver_SF_Ctrl_Disable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Disable_Wrap_Access(uint8_t disable){
+void bflb_sf_ctrl_disable_wrap_access(uint8_t disable){
     return RomDriver_SF_Ctrl_Disable_Wrap_Access(disable);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Enable(const SF_Ctrl_Cfg_Type *cfg){
+void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg){
     return RomDriver_SF_Ctrl_Enable(cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Flash2_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid){
-    return RomDriver_SF_Ctrl_Flash2_Read_Icache_Set(cfg,cmdValid);
+void bflb_sf_ctrl_xip2_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid){
+    return RomDriver_SF_Ctrl_Flash2_Read_Icache_Set(cfg,cmd_valid);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Flash_Read_Icache_Set(SF_Ctrl_Cmd_Cfg_Type *cfg, uint8_t cmdValid){
-    return RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg,cmdValid);
+void bflb_sf_ctrl_xip_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid){
+    return RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg,cmd_valid);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Lock_Flash_Image_Offset(uint8_t lock){
+void bflb_sf_ctrl_lock_flash_image_offset(uint8_t lock){
     return RomDriver_SF_Ctrl_Lock_Flash_Image_Offset(lock);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Remap_Set(SF_Ctrl_Remap_Type remap, uint8_t lock){
+void bflb_sf_ctrl_remap_set(uint8_t remap, uint8_t lock){
     return RomDriver_SF_Ctrl_Remap_Set(remap,lock);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Sbus2_Hold_Sram(void){
+void bflb_sf_ctrl_sbus2_hold_sram(void){
     return RomDriver_SF_Ctrl_Sbus2_Hold_Sram();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Sbus2_Release_Sram(void){
+void bflb_sf_ctrl_sbus2_release_sram(void){
     return RomDriver_SF_Ctrl_Sbus2_Release_Sram();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Sbus2_Replace(SF_Ctrl_Pad_Type pad){
+void bflb_sf_ctrl_sbus2_replace(uint8_t pad){
     return RomDriver_SF_Ctrl_Sbus2_Replace(pad);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Sbus2_Revoke_replace(void){
+void bflb_sf_ctrl_sbus2_revoke_replace(void){
     return RomDriver_SF_Ctrl_Sbus2_Revoke_replace();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Sbus2_Set_Delay(uint8_t clkDelay, uint8_t rxClkInvert){
-    return RomDriver_SF_Ctrl_Sbus2_Set_Delay(clkDelay,rxClkInvert);
+void bflb_sf_ctrl_sbus2_set_delay(uint8_t clk_delay, uint8_t rx_clk_invert){
+    return RomDriver_SF_Ctrl_Sbus2_Set_Delay(clk_delay,rx_clk_invert);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Sbus_Select_Bank(SF_Ctrl_Bank_Select bank){
+void bflb_sf_ctrl_sbus_select_bank(uint8_t bank){
     return RomDriver_SF_Ctrl_Sbus_Select_Bank(bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Select_Pad(SF_Ctrl_Pin_Select sel){
+void bflb_sf_ctrl_select_pad(uint8_t sel){
     return RomDriver_SF_Ctrl_Select_Pad(sel);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_SendCmd(SF_Ctrl_Cmd_Cfg_Type *cfg){
+void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg){
     return RomDriver_SF_Ctrl_SendCmd(cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Set_Clock_Delay(uint8_t delay){
+void bflb_sf_ctrl_set_clock_delay(uint8_t delay){
     return RomDriver_SF_Ctrl_Set_Clock_Delay(delay);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Set_Flash_Image_Offset(uint32_t addrOffset, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addrOffset,group,bank);
+void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank){
+    return RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset,group,bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Set_IO_Delay(SF_Ctrl_Pad_Type pad, uint8_t doDelay, uint8_t diDelay, uint8_t oeDelay){
-    return RomDriver_SF_Ctrl_Set_IO_Delay(pad,doDelay,diDelay,oeDelay);
+void bflb_sf_ctrl_set_io_delay(uint8_t pad, uint8_t do_delay, uint8_t di_delay, uint8_t oe_delay){
+    return RomDriver_SF_Ctrl_Set_IO_Delay(pad,do_delay,di_delay,oe_delay);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SF_Ctrl_Set_Owner(SF_Ctrl_Owner_Type owner){
+void bflb_sf_ctrl_set_owner(uint8_t owner){
     return RomDriver_SF_Ctrl_Set_Owner(owner);
 }
 
 #if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum){
-    return RomDriver_SFlash_Blk32_Erase(flashCfg,blkNum);
+int bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num){
+    return RomDriver_SFlash_Blk32_Erase(flash_cfg,blk_num);
 }
 #endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum){
-    return RomDriver_SFlash_Blk64_Erase(flashCfg,blkNum);
+int bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num){
+    return RomDriver_SFlash_Blk64_Erase(flash_cfg,blk_num);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Chip_Erase(flashCfg);
+int bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Chip_Erase(flash_cfg);
 }
 
 #if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr){
-    return RomDriver_SFlash_Erase(flashCfg,startaddr,endaddr);
+int bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr){
+    return RomDriver_SFlash_Erase(flash_cfg,start_addr,end_addr);
 }
 #endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg){
-    return RomDriver_SFlash_Erase_Security_Register(pFlashCfg,pSecRegCfg);
+int bflb_sflash_erase_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg){
+    return RomDriver_SFlash_Erase_Security_Register(flash_cfg,p_sec_reg_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SFlash_IDbus_Read_Enable(flashCfg,ioMode,contRead,bank);
+int bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint8_t bank){
+    return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg,io_mode,cont_read,bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len){
-    return RomDriver_SFlash_Program(flashCfg,ioMode,addr,data,len);
+int bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len){
+    return RomDriver_SFlash_Program(flash_cfg,io_mode,addr,data,len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg){
-    return RomDriver_SFlash_Program_Security_Register(pFlashCfg,pSecRegCfg);
+int bflb_sflash_program_security_register(spi_flash_cfg_type *flash_cfg, struct sflash_sec_reg_cfg *p_sec_reg_cfg){
+    return RomDriver_SFlash_Program_Security_Register(flash_cfg,p_sec_reg_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Qspi_Disable(flashCfg);
+int bflb_sflash_qspi_disable(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Qspi_Disable(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Qspi_Enable(flashCfg);
+int bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Qspi_Enable(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos){
-    return RomDriver_SFlash_RCV_Enable(pFlashCfg,rCmd,wCmd,bitPos);
+int bflb_sflash_rcv_enable(spi_flash_cfg_type *flash_cfg, uint8_t r_cmd, uint8_t w_cmd, uint8_t bit_pos){
+    return RomDriver_SFlash_RCV_Enable(flash_cfg,r_cmd,w_cmd,bit_pos);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len){
-    return RomDriver_SFlash_Read(flashCfg,ioMode,contRead,addr,data,len);
+int bflb_sflash_read(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint8_t *data, uint32_t len){
+    return RomDriver_SFlash_Read(flash_cfg,io_mode,cont_read,addr,data,len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen){
-    return RomDriver_SFlash_Read_Reg(flashCfg,regIndex,regValue,regLen);
+int bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len){
+    return RomDriver_SFlash_Read_Reg(flash_cfg,reg_index,reg_value,reg_len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue, uint8_t regLen){
-    return RomDriver_SFlash_Read_Reg_With_Cmd(flashCfg,readRegCmd,regValue,regLen);
+int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len){
+    return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg,read_reg_cmd,reg_value,reg_len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg){
-    return RomDriver_SFlash_Read_Security_Register(pSecRegCfg);
+int bflb_sflash_read_security_register(struct sflash_sec_reg_cfg *p_sec_reg_cfg){
+    return RomDriver_SFlash_Read_Security_Register(p_sec_reg_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SFlash_Restore_From_Powerdown(pFlashCfg,flashContRead,bank);
+int bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *flash_cfg, uint8_t flash_cont_read, uint8_t bank){
+    return RomDriver_SFlash_Restore_From_Powerdown(flash_cfg,flash_cont_read,bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum){
-    return RomDriver_SFlash_Sector_Erase(flashCfg,secNum);
+int bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t sec_num){
+    return RomDriver_SFlash_Sector_Erase(flash_cfg,sec_num);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr){
-    return RomDriver_SFlash_Set32BitsAddrMode(flashCfg,en32BitsAddr);
+int bflb_sflash_set_32bits_addr_mode(spi_flash_cfg_type *flash_cfg, BL_Fun_Type en_32bits_addr){
+    return RomDriver_SFlash_Set32BitsAddrMode(flash_cfg,en_32bits_addr);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode){
+int bflb_sflash_set_spi_mode(uint8_t mode){
     return RomDriver_SFlash_SetSPIMode(mode);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint32_t len, SF_Ctrl_Bank_Select bank){
-    return RomDriver_SFlash_Set_IDbus_Cfg(flashCfg,ioMode,contRead,addr,len,bank);
+int bflb_sflash_set_xip_cfg(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t cont_read, uint32_t addr, uint32_t len, uint8_t bank){
+    return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg,io_mode,cont_read,addr,len,bank);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Software_Reset(flashCfg);
+int bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Software_Reset(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Write_Enable(flashCfg);
+int bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Write_Enable(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen){
-    return RomDriver_SFlash_Write_Reg(flashCfg,regIndex,regValue,regLen);
+int bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len){
+    return RomDriver_SFlash_Write_Reg(flash_cfg,reg_index,reg_value,reg_len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue, uint8_t regLen){
-    return RomDriver_SFlash_Write_Reg_With_Cmd(flashCfg,writeRegCmd,regValue,regLen);
+int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t write_reg_cmd, uint8_t *reg_value, uint8_t reg_len){
+    return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg,write_reg_cmd,reg_value,reg_len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Busy(flashCfg);
+int bflb_sflash_busy(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Busy(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_DisableBurstWrap(flashCfg);
+void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_DisableBurstWrap(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr){
-    return RomDriver_SFlash_GetDeviceId(data,is32BitsAddr);
+void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr){
+    return RomDriver_SFlash_GetDeviceId(data,is_32bits_addr);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data){
-    return RomDriver_SFlash_GetJedecId(flashCfg,data);
+void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data){
+    return RomDriver_SFlash_GetJedecId(flash_cfg,data);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen){
-    return RomDriver_SFlash_GetUniqueId(data,idLen);
+void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len){
+    return RomDriver_SFlash_GetUniqueId(data,id_len);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_IDbus_Read_Disable(void){
+void bflb_sflash_idbus_read_disable(void){
     return RomDriver_SFlash_IDbus_Read_Disable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg){
-    return RomDriver_SFlash_Init(pSfCtrlCfg,pBank2Cfg);
+void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg, const struct sf_ctrl_bank2_cfg *p_bank2_cfg){
+    return RomDriver_SFlash_Init(p_sf_ctrl_cfg,p_bank2_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_Powerdown(void){
+void bflb_sflash_powerdown(void){
     return RomDriver_SFlash_Powerdown();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Release_Powerdown(flashCfg);
+void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Release_Powerdown(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Reset_Continue_Read(flashCfg);
+void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Reset_Continue_Read(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_SetBurstWrap(flashCfg);
+void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_SetBurstWrap(flash_cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg){
-    return RomDriver_SFlash_Volatile_Reg_Write_Enable(flashCfg);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_ApplyAbrResult(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){
-    return RomDriver_UART_ApplyAbrResult(uartId,autoBaudDet);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_AutoBaudDetection(UART_ID_Type uartId, BL_Fun_Type autoBaud){
-    return RomDriver_UART_AutoBaudDetection(uartId,autoBaud);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_ClrRtsValue(UART_ID_Type uartId){
-    return RomDriver_UART_ClrRtsValue(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_ClrTxValue(UART_ID_Type uartId){
-    return RomDriver_UART_ClrTxValue(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_DeInit(UART_ID_Type uartId){
-    return RomDriver_UART_DeInit(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_Disable(UART_ID_Type uartId, UART_Direction_Type direct){
-    return RomDriver_UART_Disable(uartId,direct);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_Enable(UART_ID_Type uartId, UART_Direction_Type direct){
-    return RomDriver_UART_Enable(uartId,direct);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_FifoConfig(UART_ID_Type uartId, UART_FifoCfg_Type *fifoCfg){
-    return RomDriver_UART_FifoConfig(uartId,fifoCfg);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_GetBitWidth0X55(UART_ID_Type uartId, uint16_t *width){
-    return RomDriver_UART_GetBitWidth0X55(uartId,width);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_Init(UART_ID_Type uartId, UART_CFG_Type *uartCfg){
-    return RomDriver_UART_Init(uartId,uartCfg);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_IntClear(UART_ID_Type uartId, UART_INT_Type intType){
-    return RomDriver_UART_IntClear(uartId,intType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_IntMask(UART_ID_Type uartId, UART_INT_Type intType, BL_Mask_Type intMask){
-    return RomDriver_UART_IntMask(uartId,intType,intMask);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_IrConfig(UART_ID_Type uartId, UART_IrCfg_Type *irCfg){
-    return RomDriver_UART_IrConfig(uartId,irCfg);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_RxFifoClear(UART_ID_Type uartId){
-    return RomDriver_UART_RxFifoClear(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SendData(UART_ID_Type uartId, uint8_t *data, uint32_t len){
-    return RomDriver_UART_SendData(uartId,data,len);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SendDataBlock(UART_ID_Type uartId, uint8_t *data, uint32_t len){
-    return RomDriver_UART_SendDataBlock(uartId,data,len);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetAllowableError0X55(UART_ID_Type uartId, uint8_t allowableError){
-    return RomDriver_UART_SetAllowableError0X55(uartId,allowableError);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetBaudRate(UART_ID_Type uartId, uint32_t baudRate){
-    return RomDriver_UART_SetBaudRate(uartId,baudRate);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetDeglitchCount(UART_ID_Type uartId, uint8_t deglitchCnt){
-    return RomDriver_UART_SetDeglitchCount(uartId,deglitchCnt);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetRS485(UART_ID_Type uartId, BL_Fun_Type enable, UART_RS485Polarity_Type polarity){
-    return RomDriver_UART_SetRS485(uartId,enable,polarity);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetRtsValue(UART_ID_Type uartId){
-    return RomDriver_UART_SetRtsValue(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetRxByteCount(UART_ID_Type uartId, uint16_t count){
-    return RomDriver_UART_SetRxByteCount(uartId,count);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetRxDataLength(UART_ID_Type uartId, uint16_t length){
-    return RomDriver_UART_SetRxDataLength(uartId,length);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetRxTimeoutValue(UART_ID_Type uartId, uint8_t time){
-    return RomDriver_UART_SetRxTimeoutValue(uartId,time);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetTxDataLength(UART_ID_Type uartId, uint16_t length){
-    return RomDriver_UART_SetTxDataLength(uartId,length);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_SetTxValue(UART_ID_Type uartId){
-    return RomDriver_UART_SetTxValue(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_TxFifoClear(UART_ID_Type uartId){
-    return RomDriver_UART_TxFifoClear(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type UART_TxFreeRun(UART_ID_Type uartId, BL_Fun_Type txFreeRun){
-    return RomDriver_UART_TxFreeRun(uartId,txFreeRun);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type UART_GetIntStatus(UART_ID_Type uartId, UART_INT_Type intType){
-    return RomDriver_UART_GetIntStatus(uartId,intType);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type UART_GetOverflowStatus(UART_ID_Type uartId, UART_Overflow_Type overflow){
-    return RomDriver_UART_GetOverflowStatus(uartId,overflow);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type UART_GetRxBusBusyStatus(UART_ID_Type uartId){
-    return RomDriver_UART_GetRxBusBusyStatus(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Sts_Type UART_GetTxBusBusyStatus(UART_ID_Type uartId){
-    return RomDriver_UART_GetTxBusBusyStatus(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint16_t UART_GetAutoBaudCount(UART_ID_Type uartId, UART_AutoBaudDetection_Type autoBaudDet){
-    return RomDriver_UART_GetAutoBaudCount(uartId,autoBaudDet);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint16_t UART_GetRxByteCount(UART_ID_Type uartId){
-    return RomDriver_UART_GetRxByteCount(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint32_t UART_ReceiveData(UART_ID_Type uartId, uint8_t *data, uint32_t maxLen){
-    return RomDriver_UART_ReceiveData(uartId,data,maxLen);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint8_t UART_GetRxFifoCount(UART_ID_Type uartId){
-    return RomDriver_UART_GetRxFifoCount(uartId);
-}
-
-__ALWAYS_INLINE ATTR_TCM_SECTION
-uint8_t UART_GetTxFifoCount(UART_ID_Type uartId){
-    return RomDriver_UART_GetTxFifoCount(uartId);
+void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg){
+    return RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg);
 }
 
 #if 0
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_Erase_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t startaddr, int len, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_Erase_Need_Lock(pFlashCfg,startaddr,len,group,bank);
+int bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, int len, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_Erase_Need_Lock(flash_cfg,start_addr,len,group,bank);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+int bflb_xip_sflash_getdeviceid_need_lock(spi_flash_cfg_type *flash_cfg, BL_Fun_Type is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(flash_cfg,is_32bits_addr,data,group,bank);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+int bflb_xip_sflash_getjedecid_need_lock(spi_flash_cfg_type *flash_cfg, uint8_t *data, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(flash_cfg,data,group,bank);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+int bflb_xip_sflash_getuniqueid_need_lock(spi_flash_cfg_type *flash_cfg, uint8_t *data, uint8_t id_len, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(flash_cfg,data,id_len,group,bank);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+int bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_Read_Need_Lock(flash_cfg,addr,data,len,group,bank);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len){
+    return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr,data,len);
 }
 #endif
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_GetDeviceId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, BL_Fun_Type is32BitsAddr, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(pFlashCfg,is32BitsAddr,data,group,bank);
+int bflb_xip_sflash_state_restore(spi_flash_cfg_type *flash_cfg, uint32_t offset, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_State_Restore(flash_cfg,offset,group,bank);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+int bflb_xip_sflash_state_save(spi_flash_cfg_type *flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_State_Save(flash_cfg,offset,group,bank);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+int bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank){
+    return RomDriver_XIP_SFlash_Write_Need_Lock(flash_cfg,addr,data,len,group,bank);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void bflb_xip_sflash_opt_enter(uint8_t *aes_enable){
+    return RomDriver_XIP_SFlash_Opt_Enter(aes_enable);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_GetJedecId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(pFlashCfg,data,group,bank);
+void bflb_xip_sflash_opt_exit(uint8_t aes_enable){
+    return RomDriver_XIP_SFlash_Opt_Exit(aes_enable);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type MD_Clr_GPIO_IntStatus(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_Clr_GPIO_IntStatus(gpioPin);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_GetUniqueId_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t *data, uint8_t idLen, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(pFlashCfg,data,idLen,group,bank);
+BL_Err_Type MD_Embedded_Flash_Pad_Enable(void){
+    return RomDriver_MD_Embedded_Flash_Pad_Enable();
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_Read_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_Read_Need_Lock(pFlashCfg,addr,data,len,group,bank);
+BL_Err_Type MD_GPIO_Clr(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Clr(gpioPin);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_Read_Via_Cache_Need_Lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr,data,len,group,bank);
+BL_Err_Type MD_GPIO_Init(MD_GPIO_Cfg_Type *cfg){
+    return RomDriver_MD_GPIO_Init(cfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_State_Restore(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t offset, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_State_Restore(pFlashCfg,offset,group,bank);
+BL_Err_Type MD_GPIO_Input_Disable(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Input_Disable(gpioPin);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_State_Save(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t *offset, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_State_Save(pFlashCfg,offset,group,bank);
+BL_Err_Type MD_GPIO_Input_Enable(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Input_Enable(gpioPin);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-BL_Err_Type XIP_SFlash_Write_Need_Lock(SPI_Flash_Cfg_Type *pFlashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, SF_Ctrl_Bank_Select bank){
-    return RomDriver_XIP_SFlash_Write_Need_Lock(pFlashCfg,addr,data,len,group,bank);
+BL_Err_Type MD_GPIO_IntMask(MD_GPIO_Type gpioPin, BL_Mask_Type intMask){
+    return RomDriver_MD_GPIO_IntMask(gpioPin,intMask);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void XIP_SFlash_Opt_Enter(uint8_t *aesEnable){
-    return RomDriver_XIP_SFlash_Opt_Enter(aesEnable);
+BL_Err_Type MD_GPIO_Int_Init(MD_GPIO_INT_Cfg_Type *intCfg){
+    return RomDriver_MD_GPIO_Int_Init(intCfg);
 }
 
 __ALWAYS_INLINE ATTR_TCM_SECTION
-void XIP_SFlash_Opt_Exit(uint8_t aesEnable){
-    return RomDriver_XIP_SFlash_Opt_Exit(aesEnable);
+BL_Err_Type MD_GPIO_Output_Disable(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Output_Disable(gpioPin);
 }
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type MD_GPIO_Output_Enable(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Output_Enable(gpioPin);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type MD_GPIO_Set(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Set(gpioPin);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type MD_GPIO_Set_HZ(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Set_HZ(gpioPin);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type MD_GPIO_Write(MD_GPIO_Type gpioPin, uint32_t val){
+    return RomDriver_MD_GPIO_Write(gpioPin,val);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Sts_Type MD_Get_GPIO_IntStatus(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_Get_GPIO_IntStatus(gpioPin);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint32_t MD_GPIO_Read(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Read(gpioPin);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+uint8_t MD_GPIO_Get_Fun(MD_GPIO_Type gpioPin){
+    return RomDriver_MD_GPIO_Get_Fun(gpioPin);
+}
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c
new file mode 100755
index 0000000000..c5b592124e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romapi_patch.c
@@ -0,0 +1,3200 @@
+/**
+  ******************************************************************************
+  * @file    bl808_romapi_patch.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2021 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616_romapi_patch.h"
+#include "bl616_romdriver_e907.h"
+
+/* WiFi PLL Config*/
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {
+    .clkpllRefdivRatio = 2,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 0,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 0,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 2,        /*!< pll_icp_5u */
+    .clkpllRz = 3,           /*!< pll_rz */
+    .clkpllCz = 1,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 1,      /*!< pll_r4_short */
+    .clkpllC4En = 0,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 1,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 1,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_24M = {
+    .clkpllRefdivRatio = 1,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 0,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 0,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 2,        /*!< pll_icp_5u */
+    .clkpllRz = 3,           /*!< pll_rz */
+    .clkpllCz = 1,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 1,      /*!< pll_r4_short */
+    .clkpllC4En = 0,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 1,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 1,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_26M = {
+    .clkpllRefdivRatio = 1,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION wifiPllCfg_960M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 0 },                                 /*!< XTAL is None */
+    { &wifiPllBasicCfg_24M, 0x1400000, 0 },           /*!< XTAL is 24M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000, 0 }, /*!< XTAL is 32M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1900000, 0 }, /*!< XTAL is 38.4M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1800000, 0 }, /*!< XTAL is 40M */
+    { &wifiPllBasicCfg_26M, 0x1276276, 0 },           /*!< XTAL is 26M */
+    { &wifiPllBasicCfg_32M_38P4M_40M, 0x1E00000, 0 }, /*!< XTAL is RC32M */
+};
+
+/* Audio PLL Config*/
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_24M_26M = {
+    .clkpllRefdivRatio = 2,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPllBasicCfg_32M_38P4M_40M = {
+    .clkpllRefdivRatio = 4,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_491P52M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 20 },                                /*!< XTAL is None */
+    { &audioPllBasicCfg_24M_26M, 0x147AE, 20 },       /*!< XTAL is 24M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1EB85, 20 }, /*!< XTAL is 32M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x19999, 20 }, /*!< XTAL is 38.4M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x18937, 20 }, /*!< XTAL is 40M */
+    { &audioPllBasicCfg_24M_26M, 0x12E79, 20 },       /*!< XTAL is 26M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1EB85, 20 }, /*!< XTAL is RC32M */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_451P58M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 20 },                                /*!< XTAL is None */
+    { &audioPllBasicCfg_24M_26M, 0x12D0D, 20 },       /*!< XTAL is 24M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1C394, 20 }, /*!< XTAL is 32M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x17851, 20 }, /*!< XTAL is 38.4M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x16943, 20 }, /*!< XTAL is 40M */
+    { &audioPllBasicCfg_24M_26M, 0x115E5, 20 },       /*!< XTAL is 26M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x1C394, 20 }, /*!< XTAL is RC32M */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_400M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 8 },                                /*!< XTAL is None */
+    { &audioPllBasicCfg_24M_26M, 0x10AAA, 8 },       /*!< XTAL is 24M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x19000, 8 }, /*!< XTAL is 32M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x14D55, 8 }, /*!< XTAL is 38.4M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x14000, 8 }, /*!< XTAL is 40M */
+    { &audioPllBasicCfg_24M_26M, 0xF627, 8 },        /*!< XTAL is 26M */
+    { &audioPllBasicCfg_32M_38P4M_40M, 0x19000, 8 }, /*!< XTAL is RC32M */
+};
+
+/* Audio PLL Config*/
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPll384BasicCfg_24M_26M = {
+    .clkpllRefdivRatio = 2,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION audioPll384BasicCfg_32M_38P4M_40M = {
+    .clkpllRefdivRatio = 4,  /*!< pll_refdiv_ratio */
+    .clkpllIntFracSw = 1,    /*!< pll_int_frac_sw */
+    .clkpllIcp1u = 1,        /*!< pll_icp_1u */
+    .clkpllIcp5u = 0,        /*!< pll_icp_5u */
+    .clkpllRz = 5,           /*!< pll_rz */
+    .clkpllCz = 2,           /*!< pll_cz */
+    .clkpllC3 = 2,           /*!< pll_c3 */
+    .clkpllR4Short = 0,      /*!< pll_r4_short */
+    .clkpllC4En = 1,         /*!< pll_r4_en */
+    .clkpllSelSampleClk = 1, /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,     /*!< pll_vco_speed */
+    .clkpllSdmCtrlHw = 0,    /*!< pll_sdm_ctrl_hw */
+    .clkpllSdmBypass = 0,    /*!< pll_sdm_bypass */
+};
+const GLB_WA_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION audioPllCfg_384M[GLB_XTAL_MAX] = {
+    { NULL, 0x0, 8 },                                   /*!< XTAL is None */
+    { &audioPll384BasicCfg_24M_26M, 0x10000, 8 },       /*!< XTAL is 24M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x18000, 8 }, /*!< XTAL is 32M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x14000, 8 }, /*!< XTAL is 38.4M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x13333, 8 }, /*!< XTAL is 40M */
+    { &audioPll384BasicCfg_24M_26M, 0xEC4E, 8 },        /*!< XTAL is 26M */
+    { &audioPll384BasicCfg_32M_38P4M_40M, 0x18000, 8 }, /*!< XTAL is RC32M */
+};
+
+const GLB_SLAVE_GRP_0_TBL_Type ATTR_CLOCK_CONST_SECTION glb_slave_grp_0_table[GLB_SLAVE_GRP_0_MAX] = {
+    { GLB_ADC_CFG0_OFFSET, GLB_GPADC_32M_DIV_EN_POS, GLB_GPADC_32M_CLK_SEL_POS, GLB_GPADC_32M_CLK_DIV_POS, GLB_GPADC_32M_DIV_EN_LEN, GLB_GPADC_32M_CLK_SEL_LEN, GLB_GPADC_32M_CLK_DIV_LEN },
+    { GLB_IR_CFG0_OFFSET, GLB_IR_CLK_EN_POS, 0, GLB_IR_CLK_DIV_POS, GLB_IR_CLK_EN_LEN, 0, GLB_IR_CLK_DIV_LEN },
+    { GLB_I2C_CFG0_OFFSET, GLB_I2C_CLK_EN_POS, GLB_I2C_CLK_SEL_POS, GLB_I2C_CLK_DIV_POS, GLB_I2C_CLK_EN_LEN, GLB_I2C_CLK_SEL_LEN, GLB_I2C_CLK_DIV_LEN },
+    { GLB_SPI_CFG0_OFFSET, GLB_SPI_CLK_EN_POS, GLB_SPI_CLK_SEL_POS, GLB_SPI_CLK_DIV_POS, GLB_SPI_CLK_EN_LEN, GLB_SPI_CLK_SEL_LEN, GLB_SPI_CLK_DIV_LEN },
+    { GLB_PEC_CFG0_OFFSET, GLB_PEC_CLK_EN_POS, GLB_PEC_CLK_SEL_POS, GLB_PEC_CLK_DIV_POS, GLB_PEC_CLK_EN_LEN, GLB_PEC_CLK_SEL_LEN, GLB_PEC_CLK_DIV_LEN },
+    { GLB_DBI_CFG0_OFFSET, GLB_DBI_CLK_EN_POS, GLB_DBI_CLK_SEL_POS, GLB_DBI_CLK_DIV_POS, GLB_DBI_CLK_EN_LEN, GLB_DBI_CLK_SEL_LEN, GLB_DBI_CLK_DIV_LEN },
+    { GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_AUTO_DIV_EN_POS, 0, 0, GLB_REG_AUDIO_AUTO_DIV_EN_LEN, 0, 0 },
+    { GLB_AUDIO_CFG0_OFFSET, GLB_REG_AUDIO_ADC_CLK_EN_POS, 0, GLB_REG_AUDIO_ADC_CLK_DIV_POS, GLB_REG_AUDIO_ADC_CLK_EN_LEN, 0, GLB_REG_AUDIO_ADC_CLK_DIV_LEN },
+    { GLB_AUDIO_CFG1_OFFSET, GLB_REG_AUDIO_SOLO_CLK_EN_POS, 0, GLB_REG_AUDIO_SOLO_CLK_DIV_POS, GLB_REG_AUDIO_SOLO_CLK_EN_LEN, 0, GLB_REG_AUDIO_SOLO_CLK_DIV_LEN },
+    { GLB_CAM_CFG0_OFFSET, GLB_REG_CAM_REF_CLK_EN_POS, GLB_REG_CAM_REF_CLK_SRC_SEL_POS, GLB_REG_CAM_REF_CLK_DIV_POS, GLB_REG_CAM_REF_CLK_EN_LEN, GLB_REG_CAM_REF_CLK_SRC_SEL_LEN, GLB_REG_CAM_REF_CLK_DIV_LEN },
+    { GLB_SDH_CFG0_OFFSET, GLB_REG_SDH_CLK_EN_POS, GLB_REG_SDH_CLK_SEL_POS, GLB_REG_SDH_CLK_DIV_POS, GLB_REG_SDH_CLK_EN_LEN, GLB_REG_SDH_CLK_SEL_LEN, GLB_REG_SDH_CLK_DIV_LEN },
+    { GLB_PSRAM_CFG0_OFFSET, GLB_REG_PSRAMB_CLK_EN_POS, GLB_REG_PSRAMB_CLK_SEL_POS, GLB_REG_PSRAMB_CLK_DIV_POS, GLB_REG_PSRAMB_CLK_EN_LEN, GLB_REG_PSRAMB_CLK_SEL_LEN, GLB_REG_PSRAMB_CLK_DIV_LEN },
+};
+
+typedef struct
+{
+    uint32_t jedec_id;
+    char *name;
+    const spi_flash_cfg_type *cfg;
+} Flash_Info_t;
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_GD_LQ64E = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xa0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3d,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 500,
+    .time_e_32k = 2000,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_GD_Q64E = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Winb_16JV = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02, /*Q08BV,Q16DV: 0x02.Q32FW,Q32FV: 0x01 */
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xa0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3d,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Winb_64JV = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0xFF,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 400,
+    .time_e_32k = 1600,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Winb_256FV = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xa0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = 0x24,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 400,
+    .time_e_32k = 1600,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 3,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flash_cfg_Mxic_25U256 = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc2,
+
+    .de_burst_wrap_cmd = 0xC0,
+    .de_burst_wrap_cmd_dmy_clk = 0x00,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .de_burst_wrap_data = 0x10,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 0,
+    .qe_bit = 0x06,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x15,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA5,
+
+    .burst_wrap_cmd = 0xC0,
+    .burst_wrap_cmd_dmy_clk = 0x00,
+    .burst_wrap_data_mode = SF_CTRL_DATA_1_LINE,
+    .burst_wrap_data = 0x02,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x38,
+    .qpp_addr_mode = SF_CTRL_ADDR_4_LINES,
+
+    .io_mode = (SF_CTRL_QIO_MODE | 0x20),
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .enter_32bits_addr_cmd = 0xb7,
+    .exit_32bits_addr_cmd = 0xe9,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 400,
+    .time_e_32k = 1000,
+    .time_e_64k = 2000,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION Flash_Info_t flash_infos[] = {
+    {
+        .jedec_id = 0x1740ef,
+        //.name="WB_64JV_64_33",
+        .cfg = &flash_cfg_Winb_64JV,
+    },
+    {
+        .jedec_id = 0x1940ef,
+        //.name="WB_256FV_256_33",
+        .cfg = &flash_cfg_Winb_256FV,
+    },
+    {
+        .jedec_id = 0x1760ef,
+        //.name="WB_64JW_64_18",
+        .cfg = &flash_cfg_Winb_64JV,
+    },
+    {
+        .jedec_id = 0x1570ef,
+        //.name="WB_16JV_16_33",
+        .cfg = &flash_cfg_Winb_16JV,
+    },
+    {
+        .jedec_id = 0x1740c8,
+        //.name="GD_64E_64_33",
+        .cfg = &flash_cfg_GD_Q64E,
+    },
+    {
+        .jedec_id = 0x1760c8,
+        //.name="GD_LQ64E_64_18",
+        .cfg = &flash_cfg_GD_LQ64E,
+    },
+    {
+        .jedec_id = 0x1860c8,
+        //.name="GD_LQ128E_128_18",
+        .cfg = &flash_cfg_GD_LQ64E,
+    },
+    {
+        .jedec_id = 0x15345e,
+        //.name="ZB_WQ16A_16_33",
+        .cfg = &flash_cfg_GD_Q64E,
+    },
+    {
+        .jedec_id = 0x15405e,
+        //.name="ZB_16B_16_33",
+        .cfg = &flash_cfg_GD_Q64E,
+    },
+    {
+        .jedec_id = 0x16405e,
+        //.name="ZB_32B_32_33",
+        .cfg = &flash_cfg_GD_Q64E,
+    },
+    {
+        .jedec_id = 0x17405e,
+        //.name="ZB_VQ64_64_33",
+        .cfg = &flash_cfg_GD_Q64E,
+    },
+    {
+        .jedec_id = 0x15605e,
+        //.name="ZB_VQ16_16_33",
+        .cfg = &flash_cfg_GD_Q64E,
+    },
+    {
+        .jedec_id = 0x3925c2,
+        //.name="MX_U25643G_256_18",
+        .cfg = &flash_cfg_Mxic_25U256,
+    },
+    {
+        .jedec_id = 0x144020,
+        //.name="XM_QH80_08_33",
+        .cfg = &flash_cfg_Winb_16JV,
+    },
+    {
+        .jedec_id = 0x154020,
+        //.name="XM_QH16_16_33",
+        .cfg = &flash_cfg_Winb_16JV,
+    },
+    {
+        .jedec_id = 0x164020,
+        //.name="XM_QH32_32_33",
+        .cfg = &flash_cfg_Winb_16JV,
+    },
+    {
+        .jedec_id = 0x174020,
+        //.name="XM_QH64_64_33",
+        .cfg = &flash_cfg_Winb_16JV,
+    },
+    {
+        .jedec_id = 0x174220,
+        //.name="XM_QW64_64_1833",
+        .cfg = &flash_cfg_Winb_16JV,
+    },
+    {
+        .jedec_id = 0x17400b,
+        //.name="XT_F64B_64_33",
+        .cfg = &flash_cfg_GD_LQ64E,
+    },
+};
+
+//CLOCK
+//EFUSE
+//PDS
+
+//FLASH
+/****************************************************************************/ /**
+ * @brief  Erase flash one 32K block
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  blk_num: flash 32K block number
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blk_num)
+{
+    uint32_t cnt = 0;
+    uint8_t is_32bits_addr = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    int stat = bflb_sflash_write_enable(flash_cfg);
+
+    if (stat != 0) {
+        return stat;
+    }
+
+    if (((uintptr_t)&flash_cmd) % 4 == 0) {
+        ARCH_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        ARCH_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    is_32bits_addr = (flash_cfg->io_mode & 0x20);
+    /* rw_flag don't care */
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.addr_size = 3;
+
+    if (is_32bits_addr > 0) {
+        flash_cmd.addr_size++;
+        flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) >> 8);
+        flash_cmd.cmd_buf[1] = ((BFLB_SPIFLASH_BLK32K_SIZE * blk_num) << 24);
+    } else {
+        flash_cmd.cmd_buf[0] = (flash_cfg->blk32_erase_cmd << 24) | (BFLB_SPIFLASH_BLK32K_SIZE * blk_num);
+    }
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (SET == bflb_sflash_busy(flash_cfg)) {
+        arch_delay_us(500);
+        cnt++;
+
+        if (cnt > flash_cfg->time_e_32k * 3) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one region
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  start_addr: start address to erase
+ * @param  end_addr: end address(include this address) to erase
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t start_addr, uint32_t end_addr)
+{
+    uint32_t len = 0;
+    uint32_t erase_len = 0;
+    int ret = 0;
+
+    if (start_addr > end_addr) {
+        return -1;
+    }
+
+    while (start_addr <= end_addr) {
+        len = end_addr - start_addr + 1;
+
+        if (flash_cfg->blk64_erase_cmd != BFLB_SPIFLASH_CMD_INVALID &&
+            (start_addr & (BFLB_SPIFLASH_BLK64K_SIZE - 1)) == 0 &&
+            len > (BFLB_SPIFLASH_BLK64K_SIZE - flash_cfg->sector_size * 1024)) {
+            /* 64K margin address,and length > 64K-sector size, erase one first */
+            ret = bflb_sflash_blk64_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK64K_SIZE);
+            erase_len = BFLB_SPIFLASH_BLK64K_SIZE;
+        } else if (flash_cfg->blk32_erase_cmd != BFLB_SPIFLASH_CMD_INVALID &&
+                   (start_addr & (BFLB_SPIFLASH_BLK32K_SIZE - 1)) == 0 &&
+                   len > (BFLB_SPIFLASH_BLK32K_SIZE - flash_cfg->sector_size * 1024)) {
+            /* 32K margin address,and length > 32K-sector size, erase one first */
+            ret = bflb_sflash_blk32_erase(flash_cfg, start_addr / BFLB_SPIFLASH_BLK32K_SIZE);
+            erase_len = BFLB_SPIFLASH_BLK32K_SIZE;
+        } else {
+            /* Sector erase */
+            start_addr = ((start_addr) & (~(flash_cfg->sector_size * 1024 - 1)));
+            ret = bflb_sflash_sector_erase(flash_cfg, start_addr / flash_cfg->sector_size / 1024);
+            erase_len = flash_cfg->sector_size * 1024;
+        }
+
+        start_addr += erase_len;
+
+        if (ret != 0) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register
+ *
+ * @param  flash_cfg: Flash configuration pointer
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_SFlash_Clear_Status_Register(spi_flash_cfg_type *flash_cfg)
+{
+    uint32_t ret = 0;
+    uint32_t qe_value = 0;
+    uint32_t reg_value = 0;
+    uint32_t read_value = 0;
+    uint8_t read_reg_value0 = 0;
+    uint8_t read_reg_value1 = 0;
+
+    if((flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE){
+        qe_value = 1;
+    }
+
+    bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&read_reg_value0, 1);
+    bflb_sflash_read_reg(flash_cfg, 1, (uint8_t *)&read_reg_value1, 1);
+    read_value = (read_reg_value0|(read_reg_value1<<8));
+    if ((read_value & (~((1<<(flash_cfg->qe_index*8+flash_cfg->qe_bit)) |
+                        (1<<(flash_cfg->busy_index*8+flash_cfg->busy_bit)) |
+                        (1<<(flash_cfg->wr_enable_index*8+flash_cfg->wr_enable_bit))))) == 0){
+        return 0;
+    }
+
+    ret = bflb_sflash_write_enable(flash_cfg);
+    if (0 != ret) {
+        return -1;
+    }
+    if (flash_cfg->qe_write_reg_len == 2) {
+        reg_value = (qe_value<<(flash_cfg->qe_index*8+flash_cfg->qe_bit));
+        bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 2);
+    } else {
+        if (flash_cfg->qe_index == 0) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)®_value, 1);
+        ret = bflb_sflash_write_enable(flash_cfg);
+        if (SUCCESS != ret) {
+            return -1;
+        }
+        if (flash_cfg->qe_index == 1) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(flash_cfg, 1, (uint8_t *)®_value, 1);
+    }
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get flash config according to flash ID patch
+ *
+ * @param  flash_id: Flash ID
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                                             uint8_t group, uint8_t bank)
+{
+    uint32_t i;
+    uint8_t buf[sizeof(spi_flash_cfg_type) + 8];
+    uint32_t crc, *p_crc;
+    uint32_t xip_offset;
+    char flash_cfg_magic[] = "FCFG";
+
+    if (flash_id == 0) {
+        xip_offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+        bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+        bflb_xip_sflash_read_via_cache_need_lock(8 + BL616_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank);
+        bflb_sf_ctrl_set_flash_image_offset(xip_offset, group, bank);
+
+        if (ARCH_MemCmp(buf, flash_cfg_magic, 4) == 0) {
+            crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+            p_crc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type));
+
+            if (*p_crc == crc) {
+                arch_memcpy_fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+                return 0;
+            }
+        }
+    } else {
+        if (RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg) == 0) {
+            return 0;
+        }
+        for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+            if (flash_infos[i].jedec_id == flash_id) {
+                arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+                return 0;
+            }
+        }
+    }
+
+    return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Identify one flash patch
+ *
+ * @param  call_from_flash: code run at flash or ram
+ * @param  flash_pin_cfg: Bit 7: autoscan, Bit6-0: flash GPIO config
+ * @param  restore_default: Wether restore default flash GPIO config
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg,
+                  uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    uint32_t jedec_id = 0;
+    uint32_t i = 0;
+    uint32_t ret = 0;
+
+    ret = bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank);
+    if (call_from_flash) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, p_flash_cfg->io_mode & 0xf, 1, 0, 32, bank);
+    }
+    if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) {
+        return ret;
+    }
+
+    jedec_id = (ret & 0xffffff);
+    for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+        if (flash_infos[i].jedec_id == jedec_id) {
+            arch_memcpy_fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+            break;
+        }
+    }
+    if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) {
+        return jedec_id;
+    } else {
+        return (jedec_id | BFLB_FLASH_ID_VALID_FLAG);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash via XIP
+ *
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len,
+                                                              uint8_t group, uint8_t bank)
+{
+    uint32_t offset;
+
+    addr = addr & (BL616_FLASH_XIP_END - BL616_FLASH_XIP_BASE - 1);
+    addr |= BL616_FLASH_XIP_BASE;
+
+    offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+    bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+    /* Flash read */
+    arch_memcpy_fast(data, (void *)(uintptr_t)(addr - bflb_sf_ctrl_get_flash_image_offset(group, bank)), len);
+    bflb_sf_ctrl_set_flash_image_offset(offset, group, bank);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Save flash controller state
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  offset: CPU XIP flash offset pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset,
+                                                uint8_t group, uint8_t bank)
+{
+    /* XIP_SFlash_Delay */
+    volatile uint32_t i = 32 * 2;
+
+    while (i--)
+        ;
+
+    if (bank == SF_CTRL_FLASH_BANK1) {
+        bflb_sf_ctrl_sbus2_replace(SF_CTRL_PAD2);
+    }
+    bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+    /* Exit form continous read for accepting command */
+    bflb_sflash_reset_continue_read(p_flash_cfg);
+    /* For disable command that is setting register instaed of send command, we need write enable */
+    bflb_sflash_disable_burst_wrap(p_flash_cfg);
+    /* Enable 32Bits addr mode again in case reset command make it reset */
+    bflb_sflash_set_32bits_addr_mode(p_flash_cfg, 1);
+    if ((p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QO_MODE || (p_flash_cfg->io_mode & 0x0f) == SF_CTRL_QIO_MODE) {
+        /* Enable QE again in case reset command make it reset */
+        bflb_sflash_qspi_enable(p_flash_cfg);
+    }
+    /* Deburst again to make sure */
+    bflb_sflash_disable_burst_wrap(p_flash_cfg);
+
+    /* Clear offset setting*/
+    *offset = bflb_sf_ctrl_get_flash_image_offset(group, bank);
+    bflb_sf_ctrl_set_flash_image_offset(0, group, bank);
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Erase flash one region
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  start_addr: start address to erase
+ * @param  len: data length to erase
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t start_addr,
+                                                     int len, uint8_t group, uint8_t bank)
+{
+    int stat;
+    uint32_t offset;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_erase(p_flash_cfg, start_addr, start_addr + len - 1);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Program flash one region
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: start address to be programed
+ * @param  data: data pointer to be programed
+ * @param  len: data length to be programed
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+                                                     uint32_t len, uint8_t group, uint8_t bank)
+{
+    int stat;
+    uint32_t offset;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_program(p_flash_cfg, io_mode, addr, data, len);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from flash
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data,
+                                                    uint32_t len, uint8_t group, uint8_t bank)
+{
+    int stat;
+    uint32_t offset;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat = bflb_sflash_read(p_flash_cfg, io_mode, 0, addr, data, len);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Jedec ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  data: data pointer to store Jedec ID Read from flash
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_getjedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                                          uint8_t group, uint8_t bank)
+{
+    int stat;
+    uint32_t offset;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_jedecid(p_flash_cfg, data);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Device ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  is_32bits_addr: Is flash addr mode in 32-bits
+ * @param  data: data pointer to store Device ID Read from flash
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_getdeviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, BL_Fun_Type is_32bits_addr,
+                                                           uint8_t *data, uint8_t group, uint8_t bank)
+{
+    int stat;
+    uint32_t offset;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_deviceid(data, is_32bits_addr);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Flash Unique ID
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  data: data pointer to store Device ID Read from flash
+ * @param  idLen: Unique id len
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_xip_sflash_getuniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data,
+                                                           uint8_t idLen, uint8_t group, uint8_t bank)
+{
+    int stat;
+    uint32_t offset;
+    uint8_t aes_enable = 0;
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+
+    bflb_xip_sflash_opt_enter(&aes_enable);
+    stat = bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+
+    if (stat != SUCCESS) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        bflb_sflash_get_uniqueid(data, idLen);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    bflb_xip_sflash_opt_exit(aes_enable);
+
+    return stat;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register need lock
+ *
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_XIP_SFlash_Clear_Status_Register_Need_Lock(spi_flash_cfg_type *p_flash_cfg,
+                                                                     uint8_t group, uint8_t bank)
+{
+    int stat;
+    uint32_t offset;
+    uint8_t io_mode = p_flash_cfg->io_mode&0xf;
+
+    stat=bflb_xip_sflash_state_save(p_flash_cfg, &offset, group, bank);
+    if (stat != 0) {
+        bflb_sflash_set_xip_cfg(p_flash_cfg, io_mode, 1, 0, 32, bank);
+    } else {
+        stat=bflb_sflash_clear_status_register(p_flash_cfg);
+        bflb_xip_sflash_state_restore(p_flash_cfg, offset, group, bank);
+    }
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  reconfigure WIFIPLL clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type *pllCfgList)
+{
+    GLB_PLL_REF_CLK_Type refClk;
+
+    if (xtalType == GLB_XTAL_RC32M) {
+        refClk = GLB_PLL_REFCLK_RC32M;
+    } else {
+        refClk = GLB_PLL_REFCLK_XTAL;
+    }
+
+    GLB_Power_Off_WIFIPLL();
+    GLB_WIFIPLL_Ref_Clk_Sel(refClk);
+    GLB_Power_On_WIFIPLL(&(pllCfgList[xtalType]), 1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  reconfigure AUPLL clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  pllCfg: PLL configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WA_PLL_Cfg_Type *pllCfgList)
+{
+    GLB_PLL_REF_CLK_Type refClk;
+
+    if (xtalType == GLB_XTAL_RC32M) {
+        refClk = GLB_PLL_REFCLK_RC32M;
+    } else {
+        refClk = GLB_PLL_REFCLK_XTAL;
+    }
+
+    GLB_Power_Off_AUPLL();
+    GLB_AUPLL_Ref_Clk_Sel(refClk);
+    GLB_Power_On_AUPLL(&(pllCfgList[xtalType]), 1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 384M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_384M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    /* we take 384M for CPU use,so set LDO to 1.2V*/
+    HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_1P20V);
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_384M);
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 400M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_400M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_400M);
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 451P58M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_451P58M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_451P58M);
+}
+
+/****************************************************************************/ /**
+ * @brief  Configure AUPLL clock to 491P52M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL_To_491P52M(void)
+{
+    /* GLB_XTAL_Type */
+    uint8_t xtalType = GLB_XTAL_NONE;
+
+    HBN_Get_Xtal_Type(&xtalType);
+    return GLB_Config_AUDIO_PLL((GLB_XTAL_Type)xtalType, audioPllCfg_491P52M);
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out0 select
+ *
+ * @param  clkOutType: chip clock out0 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out0_Sel(GLB_CHIP_CLK_OUT_0_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out0 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out1 select
+ *
+ * @param  clkOutType: chip clock out1 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out1_Sel(GLB_CHIP_CLK_OUT_1_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out1 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out2 select
+ *
+ * @param  clkOutType: chip clock out2 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out2_Sel(GLB_CHIP_CLK_OUT_2_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out2 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_2_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  chip clock out3 select
+ *
+ * @param  clkOutType: chip clock out3 output type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Clock_Out3_Sel(GLB_CHIP_CLK_OUT_3_Type clkOutType)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG_CLK_CFG2);
+    /* set clk out3 output enable */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_3_SEL, clkOutType);
+    BL_WR_REG(GLB_BASE, GLB_DIG_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set flash id value
+ *
+ * @param  idValue: flash id value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue)
+{
+    BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue | BFLB_FLASH_ID_VALID_FLAG));
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get flash id value
+ *
+ * @param  None
+ *
+ * @return flash id
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1);
+    if ((tmpVal & BFLB_FLASH_ID_VALID_FLAG) != 0) {
+        return (tmpVal & BFLB_FLASH_ID_VALID_MASK);
+    }
+
+    return 0x00000000;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable PDS power on PLL
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Pu_PLL_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL_SFREG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable PDS power on PLL
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Pu_PLL_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL_SFREG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable power down sleep
+ *
+ * @param  cfg: power down sleep configuration 1
+ * @param  cfg4: power down sleep configuration 2
+ * @param  pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
+{
+    uint32_t tmpVal = 0;
+    /* sleepForever set 1, chip will sleep forever */
+    /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
+    /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
+    if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
+        return ERROR;
+    } else if (pdsSleepCnt > PDS_WARMUP_LATENCY_CNT) {
+        BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
+    } else {
+    }
+
+    /* PDS_CTL4 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
+
+    /* PDS_CTL config */
+    if (cfg->pdsStart) {
+        /* clear pds int */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
+    } else {
+        BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  defaultLvCfg: power down sleep default level configuration
+ * @param  ramCfg: ram configuration
+ * @param  pdsSleepCnt: power down sleep time count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt)
+{
+    PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3), (PDS_CTL5_Type *)&(defaultLvCfg->pdsCtl5));
+    PDS_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Xtal value
+ *
+ * @param  xtalVal:Xtal value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Get_Xtal_Value(uint32_t *xtalVal)
+{
+    uint32_t tmpVal = 0;
+    uint8_t xtalType = 0;
+
+    if (NULL == xtalVal) {
+        return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    if (HBN_XTAL_FLAG_VALUE == BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_STS)) {
+        xtalType = BL_GET_REG_BITS_VAL(tmpVal, HBN_XTAL_TYPE);
+        switch (xtalType) {
+            case GLB_XTAL_NONE:
+                *xtalVal = 0;
+                break;
+            case GLB_XTAL_24M:
+                *xtalVal = 24000000;
+                break;
+            case GLB_XTAL_32M:
+                *xtalVal = 32000000;
+                break;
+            case GLB_XTAL_38P4M:
+                *xtalVal = 38400000;
+                break;
+            case GLB_XTAL_40M:
+                *xtalVal = 40000000;
+                break;
+            case GLB_XTAL_26M:
+                *xtalVal = 26000000;
+                break;
+            case GLB_XTAL_RC32M:
+                *xtalVal = 32000000;
+                break;
+            default:
+                *xtalVal = 0;
+                break;
+        }
+        return SUCCESS;
+    }
+
+    *xtalVal = 0;
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP interrupt
+ *
+ * @param  acompId: HBN Acomp ID
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompId));
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    if (acompId == AON_ACOMP0_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+        tmpVal2 = tmpVal2 | edge;
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    } else if (acompId == AON_ACOMP1_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+        tmpVal2 = tmpVal2 | edge;
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP interrupt
+ *
+ * @param  acompId: HBN Acomp ID
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp_IRQ(uint8_t acompId, HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_AON_ACOMP_ID_TYPE(acompId));
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    if (acompId == (uint8_t)AON_ACOMP0_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+        tmpVal2 = tmpVal2 & (~edge);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    } else if (acompId == (uint8_t)AON_ACOMP1_ID) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+        tmpVal2 = tmpVal2 & (~edge);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set ADC clock
+ *
+ * @param  enable: enable frequency divider or not
+ * @param  clkSel: ADC clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3F));
+
+    /* disable ADC clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_ADC_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_ADC_CFG0, tmpVal);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set IR clock divider
+ *
+ * @param  enable: enable or disable IR clock
+ * @param  clkSel: IR clock type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3F));
+
+    (void)clkSel;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_IR_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_IR_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2C clock
+ *
+ * @param  enable: Enable or disable I2C clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, GLB_I2C_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_I2C_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_I2C_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_I2C_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set SPI clock
+ *
+ * @param  enable: Enable or disable SPI clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, GLB_SPI_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_SPI_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SPI_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SPI_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set PEC clock
+ *
+ * @param  enable: Enable or disable PEC clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PEC_CLK(uint8_t enable, GLB_PEC_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PEC_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+    tmpVal >>= 1;
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+    tmpVal >>= 1;
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PEC_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PEC_CFG0);
+    tmpVal >>= 1;
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PEC_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PEC_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DBI clock
+ *
+ * @param  enable: Enable or disable DBI clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DBI_CLK(uint8_t enable, GLB_DBI_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DBI_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DBI_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_DBI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DBI_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DBI_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DBI_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DBI_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DBI_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DBI_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set audio auto clock
+ *
+ * @param  divEn: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_AUTO_CLK(uint8_t divEn)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    if (divEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_AUTO_DIV_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set audio ADC clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_ADC_CLK(uint8_t enable, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x3F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_ADC_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set audio SOLO clock
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  div: divider
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Audio_SOLO_CLK(uint8_t enable, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0xFF));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_SOLO_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_SOLO_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_AUDIO_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_AUDIO_SOLO_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_AUDIO_SOLO_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_AUDIO_CFG1, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set CAM clock
+ *
+ * @param  enable: Enable or disable CAM clock
+ * @param  clkSel: CAM clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CAM_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CAM_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set SDH clock
+ *
+ * @param  enable: Enable or disable
+ * @param  clkSel: SDH clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_SDH_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x7));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SDH_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_SDH_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_SDH_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set PSRAMB clock
+ *
+ * @param  enable: Enable or disable
+ * @param  clkSel: PSRAMB clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PSRAMB_CLK_Sel(uint8_t enable, GLB_PSRAMB_PLL_Type clkSel, uint8_t div)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PSRAMB_PLL_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PSRAMB_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PSRAM_CFG0);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PSRAMB_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PSRAMB_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PSRAM_CFG0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enter HBN
+ *
+ * @param  cfg: HBN APP Config
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
+{
+#ifndef BOOTROM
+    uint32_t valLow = 0, valHigh = 0;
+    uint64_t val;
+
+    if (cfg->useXtal32k) {
+        HBN_32K_Sel(HBN_32K_XTAL);
+    } else {
+        HBN_32K_Sel(HBN_32K_RC);
+        HBN_Power_Off_Xtal_32K();
+    }
+
+    /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
+    HBN_Hw_Pu_Pd_Cfg(DISABLE);
+
+    HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));
+    if (cfg->gpioWakeupSrc != 0) {
+        HBN_GPIO_INT_Enable(cfg->gpioTrigType);
+    }
+
+    /* HBN RTC config and enable */
+    HBN_Clear_RTC_Counter();
+    if (cfg->sleepTime != 0) {
+        HBN_Get_RTC_Timer_Val(&valLow, &valHigh);
+        val = valLow + ((uint64_t)valHigh << 32);
+        val += cfg->sleepTime;
+        HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);
+        HBN_Enable_RTC_Counter();
+    }
+
+    HBN_Power_Down_Flash(cfg->flashCfg);
+
+    GLB_Set_MCU_System_CLK(GLB_MCU_SYS_CLK_RC32M);
+
+    HBN_Enable(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel, cfg->dcdcPuSeq);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN mode
+ *
+ * @param  aGPIOIeCfg: AON GPIO input enable config. Bit(s) of Wakeup GPIO(s) must not be set to
+ *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param  ldoLevel: LDO volatge level
+ * @param  hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+    CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+    /* Setting from guide */
+    /* HBN_SRAM Retion */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    /* AON GPIO IE */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    /* HBN mode LDO level */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* power on dcdc18 sequence  */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    if (dcdcPuSeq) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_DCDC18_AON);
+    }
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Select RC32M */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbnLevel) {
+        case HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            break;
+
+        case HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            break;
+
+        default:
+            break;
+    }
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        arch_delay_ms(1000);
+    }
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Enable(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Disable(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Config HBN PIR interrupt
+ *
+ * @param  pirIntCfg: HBN PIR interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+    uint32_t bit4 = 0;
+    uint32_t bit5 = 0;
+    uint32_t bitVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    /* low trigger interrupt */
+    if (pirIntCfg->lowIntEn == ENABLE) {
+        bit5 = 0;
+    } else {
+        bit5 = 1;
+    }
+
+    /* high trigger interrupt */
+    if (pirIntCfg->highIntEn == ENABLE) {
+        bit4 = 0;
+    } else {
+        bit4 = 1;
+    }
+
+    bitVal = bit4 | (bit5 << 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR low pass filter
+ *
+ * @param  lpf: HBN PIR low pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR high pass filter
+ *
+ * @param  hpf: HBN PIR high pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR threshold value
+ *
+ * @param  threshold: HBN PIR threshold value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM((threshold <= 0x3FFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR interval value
+ *
+ * @param  interval: HBN PIR interval value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM((interval <= 0xFFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN bod config
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset
+ * @param  threshold: bod threshold
+ * @param  mode: bod work mode with por
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOD_Config(uint8_t enable, HBN_BOD_THRES_Type threshold, HBN_BOD_MODE_Type mode)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_BOD_THRES_TYPE(threshold));
+    CHECK_PARAM(IS_HBN_BOD_MODE_TYPE(mode));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOD, 0);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, threshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_SEL, mode);
+    BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Keep RC32K On during rtc power domain off
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ * @note  Don't turn off rc32k, which move to RTC Domain
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Keep_On_RC32K(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN Gpio Keep
+ *
+ * @param  gpioKeep:HBN gpio keep reg cfg
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Gpio_Keep(uint8_t gpioKeep)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RSV3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_GPIO_KEEP_STS, HBN_GPIO_KEEP_FLAG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_GPIO_KEEP_PIN, gpioKeep);
+    BL_WR_REG(HBN_BASE, HBN_RSV3, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable GPIO interrupt
+ *
+ * @param  gpioIntTrigType: HBN GPIO interrupt trigger type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable GPIO interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Disable(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN aon pad ctrl configuration
+ *
+ * @param  aonPadCtl1: ctrl value 1
+ * @param  aonpadCtl2: ctrl value 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Ctrl(uint32_t aonPadCtl1, uint32_t aonPadCtl2)
+{
+#ifndef BOOTROM
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, aonPadCtl1);
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_1, aonPadCtl2);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN Set AON_HW control aon pad or not
+ *
+ * @param  aonPadHwCtrlEn: hw control aon pad enable
+ * @param  aonGpio: aon pad number
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Aon_Pad_Cfg_Set(uint8_t aonPadHwCtrlEn, HBN_AON_PAD_Type aonGpio)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+    uint32_t enAonCtrlGpio;
+
+    /* hbn_pad_ctrl_0 */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PAD_CTRL_0);
+    enAonCtrlGpio = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_EN_AON_CTRL_GPIO);
+
+    if (aonPadHwCtrlEn) {
+        enAonCtrlGpio |= (1 << aonGpio);
+    } else {
+        enAonCtrlGpio &= ~(1 << aonGpio);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_AON_CTRL_GPIO, enAonCtrlGpio);
+
+    BL_WR_REG(HBN_BASE, HBN_PAD_CTRL_0, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable BOD interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_BOD_IRQ(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable BOD interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_BOD_IRQ(void)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN aon pad debbug pull config
+ *
+ * @param  puPdEn: Enable or disable aon pad pull down and pull up
+ * @param  ieSmtEn: Enable or disable aon pad IE and SMT
+ * @param  trigMode: trigger mode
+ * @param  maskVal: int mask
+ * @param  dlyEn: Enable or disable aon pad wakeup delay function
+ * @param  dlySec: aon pad wakeup delay sec 1 to 7
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Aon_Pad_WakeUpCfg(BL_Fun_Type puPdEn, HBN_GPIO_INT_Trigger_Type trigMode, uint32_t maskVal, BL_Fun_Type dlyEn, uint8_t dlySec)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal;
+
+    CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));
+    CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(trigMode));
+    CHECK_PARAM((maskVal <= 0x3FF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, puPdEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, trigMode);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set Embedded Flash Pullup enabe or disable
+ *
+ * @param  cfg: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOD_Cfg(HBN_BOD_CFG_Type *cfg)
+{
+#ifndef BOOTROM
+    uint32_t tmpVal = 0;
+
+    if (cfg->enableBodInt) {
+        HBN_Enable_BOD_IRQ();
+    } else {
+        HBN_Disable_BOD_IRQ();
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_BOR_CFG);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOD_VTH, cfg->bodThreshold);
+    if (cfg->enablePorInBod) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOD_SEL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOD_SEL);
+    }
+
+    if (cfg->enableBod) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOD);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOD);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_BOR_CFG, tmpVal);
+#endif
+    return SUCCESS;
+}
+
+#define GLB_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+const uint32_t ATTR_CLOCK_CONST_SECTION usbPllSdmin_12M = 0x28000;
+const uint32_t ATTR_CLOCK_CONST_SECTION sscDivSdmin_24M = 0x28000;
+
+void glb_40M_delay_us(uint32_t us)
+{
+    for (uint32_t i = 0; i < us; i++) {
+        GLB_CLK_SET_DUMMY_WAIT;
+        GLB_CLK_SET_DUMMY_WAIT;
+        GLB_CLK_SET_DUMMY_WAIT;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  power on wifipll quickly
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  pllType: only power on xtal
+ *******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Fast_Power_On_WIFIPLL(const GLB_WA_PLL_Cfg_Type *const cfg, uint8_t waitStable)
+{
+    uint32_t REG_PLL_BASE_ADDRESS = 0;
+    uint32_t tmpVal = 0;
+
+    REG_PLL_BASE_ADDRESS = GLB_BASE + GLB_WIFI_PLL_CFG0_OFFSET;
+
+    /* Step1:config parameter */
+    /* cfg1:Set wifipll_refclk_sel and wifipll_refdiv_ratio */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_REFDIV_RATIO, cfg->basicCfg->clkpllRefdivRatio);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 1, tmpVal);
+
+    /* cfg2:Set wifipll_int_frac_sw,wifipll_icp_1u,wifipll_icp_5u */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_INT_FRAC_SW, cfg->basicCfg->clkpllIntFracSw);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_ICP_1U, cfg->basicCfg->clkpllIcp1u);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_ICP_5U, cfg->basicCfg->clkpllIcp5u);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 2, tmpVal);
+
+    /* cfg3:Set wifipll_rz,wifipll_cz,wifipll_c3,wifipll_r4_short,wifipll_r4_en */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_RZ, cfg->basicCfg->clkpllRz);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_CZ, cfg->basicCfg->clkpllCz);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_C3, cfg->basicCfg->clkpllC3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_R4_SHORT, cfg->basicCfg->clkpllR4Short);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_C4_EN, cfg->basicCfg->clkpllC4En);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 3, tmpVal);
+
+    /* cfg4:Set wifipll_sel_sample_clk */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SEL_SAMPLE_CLK, cfg->basicCfg->clkpllSelSampleClk);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 4, tmpVal);
+
+    /* cfg5:Set wifipll_vco_speed */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 5);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_VCO_SPEED, cfg->basicCfg->clkpllVcoSpeed);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 5, tmpVal);
+
+    /* cfg6:Set wifipll_sdm_bypass,wifipll_sdmin */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 6);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_CTRL_HW, cfg->basicCfg->clkpllSdmCtrlHw);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_BYPASS, cfg->basicCfg->clkpllSdmBypass);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDMIN, cfg->clkpllSdmin);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 6, tmpVal);
+
+    /* cfg10:always set usbpll_sdmin */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_USBPLL_SDMIN, usbPllSdmin_12M);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 10, tmpVal);
+
+    /* cfg12:always set sscdiv_sdmin */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 12);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SSCDIV_SDMIN, sscDivSdmin_24M);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 12, tmpVal);
+
+    /* Step2:config pu */
+    /* cfg0 : pu_wifipll_sfreg=1 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL_SFREG, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* delay > 2us */
+    glb_40M_delay_us(3);
+
+    /* cfg0 : pu_wifipll=1 */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_WIFIPLL, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* delay > 2us */
+    glb_40M_delay_us(3);
+
+    /* toggle sdm_reset (pulse 0 > 1us) */
+    /* cfg0 : wifipll_sdm_reset */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    glb_40M_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    glb_40M_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_SDM_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* Step3:reset pll */
+    /* cfg0 : toggle wifipll_reset_fbdv, pulse 0 > 1us */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    glb_40M_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 0);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+    glb_40M_delay_us(2);
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_WIFIPLL_FBDV_RSTB, 1);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 0, tmpVal);
+
+    /* Step4:enable output clock */
+    /* cfg8 : wifipll clock enable */
+    tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 8);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV3);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV4);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV5);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV6);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV8);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV10);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV12);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV20);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_WIFIPLL_EN_DIV30);
+    BL_WR_WORD(REG_PLL_BASE_ADDRESS + 4 * 8, tmpVal);
+
+    if (waitStable) {
+        /* Wait 1.5*30us    */
+        glb_40M_delay_us(45);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power on xtal and wifipll quickly
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  pllType: only power on xtal
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Fast_Power_On_XTAL_40M_And_WIFIPLL(void)
+{
+    uint32_t tmpVal;
+    volatile GLB_PLL_REF_CLK_Type refClk;
+
+    refClk = GLB_PLL_REFCLK_XTAL;
+
+    /* power on xtal first */
+    AON_Power_On_XTAL();
+
+    HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_RC32M);
+    HBN_Set_MCU_Root_CLK_Sel(HBN_MCU_ROOT_CLK_XCLK);
+
+    HBN_Set_Xtal_Type(GLB_XTAL_40M);
+
+    /* power on wifipll */
+    GLB_Power_Off_WIFIPLL();
+    GLB_WIFIPLL_Ref_Clk_Sel(refClk);
+    GLB_Fast_Power_On_WIFIPLL(&wifiPllCfg_960M[GLB_XTAL_40M], 0);
+
+    glb_40M_delay_us(30);
+
+    /* if power on xtal, always set xclk from xtal */
+    HBN_Set_MCU_XCLK_Sel(HBN_MCU_XCLK_XTAL);
+
+    /* enable all PLL clock output */
+    /* GLB reg_pll_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SYS_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
+    BL_WR_REG(GLB_BASE, GLB_SYS_CFG0, tmpVal);
+
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Program data to efuse
+ *
+ * @param  offset: offset of efuse address to program
+ * @param  pword: data pointer to buffer which is aligned to word
+ * @param  count: count of data in words to program
+ *
+ * @return None
+ *
+*******************************************************************************/
+void EF_Ctrl_Program_Direct(uint32_t offset, uint32_t *pword, uint32_t count)
+{
+    uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + offset);
+
+    /* Switch to AHB clock */
+    EF_Ctrl_Sw_AHB_Clk_0();
+
+    /* Add delay for CLK to be stable */
+    arch_delay_us(4);
+
+    if (pword != NULL) {
+        ARCH_MemCpy4(pEfuseStart0, pword, count);
+    }
+
+    EF_Ctrl_Program_Efuse_0();
+}
+
+/****************************************************************************/ /**
+ * @brief  Read data from efuse
+ *
+ * @param  offset: offset of efuse address to read
+ * @param  pword: data pointer to buffer which is aligned to word
+ * @param  count: count of data in words to read
+ *
+ * @return None
+ *
+*******************************************************************************/
+void EF_Ctrl_Read_Direct(uint32_t offset, uint32_t *pword, uint32_t count)
+{
+    uint32_t *pEfuseStart0 = (uint32_t *)(EF_DATA_BASE + offset);
+
+    EF_Ctrl_Load_Efuse_R0();
+
+    ARCH_MemCpy4(pword, pEfuseStart0, count);
+}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c
old mode 100644
new mode 100755
similarity index 74%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c
index f67cc96281..bb5b21ecaa
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_romdriver_e907.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_romdriver_e907.c
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_romdriver_e907.c
+  * @file    bl616_romdriver_e907.c
   * @version V1.0
   * @date
   * @brief   This file is the standard driver c file
@@ -33,11 +33,11 @@
   *
   ******************************************************************************
   */
-
-#include "bl808_romdriver_e907.h"
+  
+#include "bl616_romdriver_e907.h"
 #include 
 
-/** @addtogroup  BL808_Periph_Driver
+/** @addtogroup  BL616_Periph_Driver
  *  @{
  */
 
@@ -60,24 +60,22 @@
 
 /** @defgroup ROMDRIVER_Private_Variables
  *  @{
- */
+ */                               
 
 /*@} end of group ROMDRIVER_Private_Variables */
 
 /** @defgroup ROMDRIVER_Global_Variables
  *  @{
- */
-
+ */ 
+ 
 
 uint32_t const romDriverTable[]={
-    0x08080001,
+    0x06160001,
     0x00000000,
     0x00000000,
     0x00000000,
 
 
-    [ROM_API_INDEX_AON_LowPower_Enter_PDS0]                = (uint32_t)AON_LowPower_Enter_PDS0,
-    [ROM_API_INDEX_AON_LowPower_Exit_PDS0]                 = (uint32_t)AON_LowPower_Exit_PDS0,
     [ROM_API_INDEX_AON_Power_Off_BG]                       = (uint32_t)AON_Power_Off_BG,
     [ROM_API_INDEX_AON_Power_Off_LDO15_RF]                 = (uint32_t)AON_Power_Off_LDO15_RF,
     [ROM_API_INDEX_AON_Power_Off_MBG]                      = (uint32_t)AON_Power_Off_MBG,
@@ -88,17 +86,34 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_AON_Power_On_MBG]                       = (uint32_t)AON_Power_On_MBG,
     [ROM_API_INDEX_AON_Power_On_SFReg]                     = (uint32_t)AON_Power_On_SFReg,
     [ROM_API_INDEX_AON_Power_On_XTAL]                      = (uint32_t)AON_Power_On_XTAL,
-    [ROM_API_INDEX_AON_Set_DCDC11_Top_Vout]                = (uint32_t)AON_Set_DCDC11_Top_Vout,
     [ROM_API_INDEX_AON_Set_Xtal_CapCode]                   = (uint32_t)AON_Set_Xtal_CapCode,
-    [ROM_API_INDEX_AON_Trim_DCDC11_Vout]                   = (uint32_t)AON_Trim_DCDC11_Vout,
-    [ROM_API_INDEX_AON_Trim_DCDC18_Vout]                   = (uint32_t)AON_Trim_DCDC18_Vout,
-    [ROM_API_INDEX_AON_Trim_USB20_RCAL]                    = (uint32_t)AON_Trim_USB20_RCAL,
+    [ROM_API_INDEX_AON_Trim_DcdcDis]                       = (uint32_t)AON_Trim_DcdcDis,
+    [ROM_API_INDEX_AON_Trim_DcdcVoutSel]                   = (uint32_t)AON_Trim_DcdcVoutSel,
+    [ROM_API_INDEX_AON_Trim_DcdcVoutTrim]                  = (uint32_t)AON_Trim_DcdcVoutTrim,
+    [ROM_API_INDEX_AON_Trim_Ldo11socVoutTrim]              = (uint32_t)AON_Trim_Ldo11socVoutTrim,
+    [ROM_API_INDEX_AON_Trim_Usb20RcalCode]                 = (uint32_t)AON_Trim_Usb20RcalCode,
     [ROM_API_INDEX_AON_Get_Xtal_CapCode]                   = (uint32_t)AON_Get_Xtal_CapCode,
 
-    [ROM_API_INDEX_ASM_Delay_Us]                           = (uint32_t)ASM_Delay_Us,
+    [ROM_API_INDEX_CPU_MTimer_Delay_MS]                    = (uint32_t)CPU_MTimer_Delay_MS,
+    [ROM_API_INDEX_CPU_MTimer_Delay_US]                    = (uint32_t)CPU_MTimer_Delay_US,
+    [ROM_API_INDEX_CPU_Reset_MTimer]                       = (uint32_t)CPU_Reset_MTimer,
+    [ROM_API_INDEX_CPU_Set_MTimer_CLK]                     = (uint32_t)CPU_Set_MTimer_CLK,
+    [ROM_API_INDEX_CPU_Set_MTimer_RST]                     = (uint32_t)CPU_Set_MTimer_RST,
+    [ROM_API_INDEX_CPU_Get_MTimer_Clock]                   = (uint32_t)CPU_Get_MTimer_Clock,
+    [ROM_API_INDEX_CPU_Get_MTimer_Source_Clock]            = (uint32_t)CPU_Get_MTimer_Source_Clock,
 
-    [ROM_API_INDEX_arch_delay_ms]                          = (uint32_t)arch_delay_ms,
-    [ROM_API_INDEX_arch_delay_us]                          = (uint32_t)arch_delay_us,
+    [ROM_API_INDEX_Clock_Audio_ADC_Clock_Get]              = (uint32_t)Clock_Audio_ADC_Clock_Get,
+    [ROM_API_INDEX_Clock_Get_ISP_Clk]                      = (uint32_t)Clock_Get_ISP_Clk,
+    [ROM_API_INDEX_Clock_Get_PSRAMB_Clk]                   = (uint32_t)Clock_Get_PSRAMB_Clk,
+    [ROM_API_INDEX_Clock_Peripheral_Clock_Get]             = (uint32_t)Clock_Peripheral_Clock_Get,
+    [ROM_API_INDEX_Clock_System_Clock_Get]                 = (uint32_t)Clock_System_Clock_Get,
+
+    [ROM_API_INDEX_SystemCoreClockGet]                     = (uint32_t)SystemCoreClockGet,
+
+    [ROM_API_INDEX_CPU_Get_CPU_Cycle]                      = (uint32_t)CPU_Get_CPU_Cycle,
+    [ROM_API_INDEX_CPU_Get_MTimer_Counter]                 = (uint32_t)CPU_Get_MTimer_Counter,
+    [ROM_API_INDEX_CPU_Get_MTimer_MS]                      = (uint32_t)CPU_Get_MTimer_MS,
+    [ROM_API_INDEX_CPU_Get_MTimer_US]                      = (uint32_t)CPU_Get_MTimer_US,
 
     [ROM_API_INDEX_EF_Ctrl_Crc_Result]                     = (uint32_t)EF_Ctrl_Crc_Result,
     [ROM_API_INDEX_EF_Ctrl_Get_Customer_PIDVID]            = (uint32_t)EF_Ctrl_Get_Customer_PIDVID,
@@ -110,40 +125,37 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_EF_Ctrl_Crc_Is_Busy]                    = (uint32_t)EF_Ctrl_Crc_Is_Busy,
     [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity]                = (uint32_t)EF_Ctrl_Get_Trim_Parity,
     [ROM_API_INDEX_EF_Ctrl_Is_All_Bits_Zero]               = (uint32_t)EF_Ctrl_Is_All_Bits_Zero,
+    [ROM_API_INDEX_EF_Ctrl_Read_FlashDlyCoe]               = (uint32_t)EF_Ctrl_Read_FlashDlyCoe,
     [ROM_API_INDEX_EF_Ctrl_Clear]                          = (uint32_t)EF_Ctrl_Clear,
     [ROM_API_INDEX_EF_Ctrl_Crc_Enable]                     = (uint32_t)EF_Ctrl_Crc_Enable,
     [ROM_API_INDEX_EF_Ctrl_Crc_Set_Golden]                 = (uint32_t)EF_Ctrl_Crc_Set_Golden,
     [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0]                  = (uint32_t)EF_Ctrl_Load_Efuse_R0,
-    [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R1]                  = (uint32_t)EF_Ctrl_Load_Efuse_R1,
-    [ROM_API_INDEX_EF_Ctrl_Program_Direct]                 = (uint32_t)EF_Ctrl_Program_Direct,
     [ROM_API_INDEX_EF_Ctrl_Program_Direct_R0]              = (uint32_t)EF_Ctrl_Program_Direct_R0,
-    [ROM_API_INDEX_EF_Ctrl_Program_Direct_R1]              = (uint32_t)EF_Ctrl_Program_Direct_R1,
     [ROM_API_INDEX_EF_Ctrl_Program_Efuse_0]                = (uint32_t)EF_Ctrl_Program_Efuse_0,
-    [ROM_API_INDEX_EF_Ctrl_Program_Efuse_1]                = (uint32_t)EF_Ctrl_Program_Efuse_1,
     [ROM_API_INDEX_EF_Ctrl_Read_ADC_Gain_Trim]             = (uint32_t)EF_Ctrl_Read_ADC_Gain_Trim,
     [ROM_API_INDEX_EF_Ctrl_Read_AES_Key]                   = (uint32_t)EF_Ctrl_Read_AES_Key,
-    [ROM_API_INDEX_EF_Ctrl_Read_DCDC11_Trim]               = (uint32_t)EF_Ctrl_Read_DCDC11_Trim,
-    [ROM_API_INDEX_EF_Ctrl_Read_DCDC18_Trim]               = (uint32_t)EF_Ctrl_Read_DCDC18_Trim,
     [ROM_API_INDEX_EF_Ctrl_Read_Dbg_Pwd]                   = (uint32_t)EF_Ctrl_Read_Dbg_Pwd,
+    [ROM_API_INDEX_EF_Ctrl_Read_DcdcDis_Trim]              = (uint32_t)EF_Ctrl_Read_DcdcDis_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_DcdcVoutSel_Trim]          = (uint32_t)EF_Ctrl_Read_DcdcVoutSel_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_DcdcVoutTrim_Trim]         = (uint32_t)EF_Ctrl_Read_DcdcVoutTrim_Trim,
     [ROM_API_INDEX_EF_Ctrl_Read_Device_Info]               = (uint32_t)EF_Ctrl_Read_Device_Info,
-    [ROM_API_INDEX_EF_Ctrl_Read_Direct]                    = (uint32_t)EF_Ctrl_Read_Direct,
     [ROM_API_INDEX_EF_Ctrl_Read_Direct_R0]                 = (uint32_t)EF_Ctrl_Read_Direct_R0,
-    [ROM_API_INDEX_EF_Ctrl_Read_Direct_R1]                 = (uint32_t)EF_Ctrl_Read_Direct_R1,
-    [ROM_API_INDEX_EF_Ctrl_Read_LDO18FLASH_Trim]           = (uint32_t)EF_Ctrl_Read_LDO18FLASH_Trim,
-    [ROM_API_INDEX_EF_Ctrl_Read_LDO18IO_Vout_Trim]         = (uint32_t)EF_Ctrl_Read_LDO18IO_Vout_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_Ldo11socVoutTrim_Trim]     = (uint32_t)EF_Ctrl_Read_Ldo11socVoutTrim_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioBypass_Trim]        = (uint32_t)EF_Ctrl_Read_Ldo18ioBypass_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioVoutSel_Trim]       = (uint32_t)EF_Ctrl_Read_Ldo18ioVoutSel_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_Ldo18ioVoutTrim_Trim]      = (uint32_t)EF_Ctrl_Read_Ldo18ioVoutTrim_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_Ldo33VoutTrim_Trim]        = (uint32_t)EF_Ctrl_Read_Ldo33VoutTrim_Trim,
     [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim]                = (uint32_t)EF_Ctrl_Read_RC32K_Trim,
     [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim]                = (uint32_t)EF_Ctrl_Read_RC32M_Trim,
     [ROM_API_INDEX_EF_Ctrl_Read_Secure_Boot]               = (uint32_t)EF_Ctrl_Read_Secure_Boot,
     [ROM_API_INDEX_EF_Ctrl_Read_Secure_Cfg]                = (uint32_t)EF_Ctrl_Read_Secure_Cfg,
     [ROM_API_INDEX_EF_Ctrl_Read_Sw_Usage]                  = (uint32_t)EF_Ctrl_Read_Sw_Usage,
     [ROM_API_INDEX_EF_Ctrl_Read_TSEN_Trim]                 = (uint32_t)EF_Ctrl_Read_TSEN_Trim,
-    [ROM_API_INDEX_EF_Ctrl_Read_USB20RCAL_Trim]            = (uint32_t)EF_Ctrl_Read_USB20RCAL_Trim,
-    [ROM_API_INDEX_EF_Ctrl_Read_Xtal_Trim_RC32M]           = (uint32_t)EF_Ctrl_Read_Xtal_Trim_RC32M,
+    [ROM_API_INDEX_EF_Ctrl_Read_Usb20RcalCode_Trim]        = (uint32_t)EF_Ctrl_Read_Usb20RcalCode_Trim,
     [ROM_API_INDEX_EF_Ctrl_Readlock_AES_Key]               = (uint32_t)EF_Ctrl_Readlock_AES_Key,
     [ROM_API_INDEX_EF_Ctrl_Readlock_Dbg_Pwd]               = (uint32_t)EF_Ctrl_Readlock_Dbg_Pwd,
     [ROM_API_INDEX_EF_Ctrl_Set_sf_key_re_sel]              = (uint32_t)EF_Ctrl_Set_sf_key_re_sel,
     [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0]                   = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0,
-    [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_1]                   = (uint32_t)EF_Ctrl_Sw_AHB_Clk_1,
     [ROM_API_INDEX_EF_Ctrl_Write_AES_Key]                  = (uint32_t)EF_Ctrl_Write_AES_Key,
     [ROM_API_INDEX_EF_Ctrl_Write_Dbg_Pwd]                  = (uint32_t)EF_Ctrl_Write_Dbg_Pwd,
     [ROM_API_INDEX_EF_Ctrl_Write_MAC_Address]              = (uint32_t)EF_Ctrl_Write_MAC_Address,
@@ -155,149 +167,90 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_EF_Ctrl_Writelock_MAC_Address]          = (uint32_t)EF_Ctrl_Writelock_MAC_Address,
     [ROM_API_INDEX_EF_Ctrl_Writelock_Sw_Usage]             = (uint32_t)EF_Ctrl_Writelock_Sw_Usage,
 
-    [ROM_API_INDEX_GLB_AHB_DSP_Software_Reset]             = (uint32_t)GLB_AHB_DSP_Software_Reset,
     [ROM_API_INDEX_GLB_AHB_MCU_Software_Reset]             = (uint32_t)GLB_AHB_MCU_Software_Reset,
+    [ROM_API_INDEX_GLB_AUPLL_Ref_Clk_Sel]                  = (uint32_t)GLB_AUPLL_Ref_Clk_Sel,
     [ROM_API_INDEX_GLB_BMX_TO_Init]                        = (uint32_t)GLB_BMX_TO_Init,
     [ROM_API_INDEX_GLB_Clr_BMX_TO_Status]                  = (uint32_t)GLB_Clr_BMX_TO_Status,
     [ROM_API_INDEX_GLB_Clr_EMI_Reset_Gate]                 = (uint32_t)GLB_Clr_EMI_Reset_Gate,
-    [ROM_API_INDEX_GLB_Config_AUDIO_PLL]                   = (uint32_t)GLB_Config_AUDIO_PLL,
-    [ROM_API_INDEX_GLB_Config_CPU_PLL]                     = (uint32_t)GLB_Config_CPU_PLL,
-    [ROM_API_INDEX_GLB_Config_MIPI_PLL]                    = (uint32_t)GLB_Config_MIPI_PLL,
-    [ROM_API_INDEX_GLB_Config_MIPI_PLL_Div]                = (uint32_t)GLB_Config_MIPI_PLL_Div,
-    [ROM_API_INDEX_GLB_Config_UHS_PLL]                     = (uint32_t)GLB_Config_UHS_PLL,
-    [ROM_API_INDEX_GLB_Config_WIFI_PLL]                    = (uint32_t)GLB_Config_WIFI_PLL,
-    [ROM_API_INDEX_GLB_DSP0_Clock_Disable]                 = (uint32_t)GLB_DSP0_Clock_Disable,
-    [ROM_API_INDEX_GLB_DSP0_Clock_Enable]                  = (uint32_t)GLB_DSP0_Clock_Enable,
-    [ROM_API_INDEX_GLB_DSP_Clr_MCU_IntStatus]              = (uint32_t)GLB_DSP_Clr_MCU_IntStatus,
-    [ROM_API_INDEX_GLB_DSP_Codec_Sub_Reset]                = (uint32_t)GLB_DSP_Codec_Sub_Reset,
-    [ROM_API_INDEX_GLB_DSP_DSP2_Sub_Reset]                  = (uint32_t)GLB_DSP_DSP2_Sub_Reset,
-    [ROM_API_INDEX_GLB_DSP_Image_Sensor_Reset]             = (uint32_t)GLB_DSP_Image_Sensor_Reset,
-    [ROM_API_INDEX_GLB_DSP_Peripheral_Reset]               = (uint32_t)GLB_DSP_Peripheral_Reset,
-    [ROM_API_INDEX_GLB_DSP_SW_System_Reset]                = (uint32_t)GLB_DSP_SW_System_Reset,
-    [ROM_API_INDEX_GLB_DSP_Set_LP_IntEn]                   = (uint32_t)GLB_DSP_Set_LP_IntEn,
-    [ROM_API_INDEX_GLB_DSP_Set_MCU_IntMask]                = (uint32_t)GLB_DSP_Set_MCU_IntMask,
+    [ROM_API_INDEX_GLB_Clr_Reset_Reason]                   = (uint32_t)GLB_Clr_Reset_Reason,
+    [ROM_API_INDEX_GLB_Config_SDIO_Host_Interrupt_CPU]     = (uint32_t)GLB_Config_SDIO_Host_Interrupt_CPU,
+    [ROM_API_INDEX_GLB_Config_SDIO_Host_Reset_SDU]         = (uint32_t)GLB_Config_SDIO_Host_Reset_SDU,
+    [ROM_API_INDEX_GLB_Config_SDIO_Host_Reset_System]      = (uint32_t)GLB_Config_SDIO_Host_Reset_System,
     [ROM_API_INDEX_GLB_Get_Auto_Calc_Xtal_Type]            = (uint32_t)GLB_Get_Auto_Calc_Xtal_Type,
-    [ROM_API_INDEX_GLB_Get_DSP_PBCLK_Div]                  = (uint32_t)GLB_Get_DSP_PBCLK_Div,
-    [ROM_API_INDEX_GLB_Get_DSP_System_CLK_Div]             = (uint32_t)GLB_Get_DSP_System_CLK_Div,
     [ROM_API_INDEX_GLB_Get_MCU_System_CLK_Div]             = (uint32_t)GLB_Get_MCU_System_CLK_Div,
-    [ROM_API_INDEX_GLB_Halt_CPU]                           = (uint32_t)GLB_Halt_CPU,
-    [ROM_API_INDEX_GLB_IR_LED_Driver_Disable]              = (uint32_t)GLB_IR_LED_Driver_Disable,
-    [ROM_API_INDEX_GLB_IR_LED_Driver_Enable]               = (uint32_t)GLB_IR_LED_Driver_Enable,
+    [ROM_API_INDEX_GLB_Get_Reset_Reason]                   = (uint32_t)GLB_Get_Reset_Reason,
     [ROM_API_INDEX_GLB_IR_RX_GPIO_Sel]                     = (uint32_t)GLB_IR_RX_GPIO_Sel,
     [ROM_API_INDEX_GLB_Invert_ETH_REF_O_CLK]               = (uint32_t)GLB_Invert_ETH_REF_O_CLK,
     [ROM_API_INDEX_GLB_Invert_ETH_RX_CLK]                  = (uint32_t)GLB_Invert_ETH_RX_CLK,
     [ROM_API_INDEX_GLB_Invert_ETH_TX_CLK]                  = (uint32_t)GLB_Invert_ETH_TX_CLK,
-    [ROM_API_INDEX_GLB_MCU_Clr_DSP_IntStatus]              = (uint32_t)GLB_MCU_Clr_DSP_IntStatus,
     [ROM_API_INDEX_GLB_MCU_SW_System_Reset]                = (uint32_t)GLB_MCU_SW_System_Reset,
-    [ROM_API_INDEX_GLB_MCU_Set_DSP_IntMask]                = (uint32_t)GLB_MCU_Set_DSP_IntMask,
-    [ROM_API_INDEX_GLB_Output_EMAC_CLK]                    = (uint32_t)GLB_Output_EMAC_CLK,
     [ROM_API_INDEX_GLB_PER_Clock_Gate]                     = (uint32_t)GLB_PER_Clock_Gate,
     [ROM_API_INDEX_GLB_PER_Clock_UnGate]                   = (uint32_t)GLB_PER_Clock_UnGate,
     [ROM_API_INDEX_GLB_PLL_CGEN_Clock_Gate]                = (uint32_t)GLB_PLL_CGEN_Clock_Gate,
     [ROM_API_INDEX_GLB_PLL_CGEN_Clock_UnGate]              = (uint32_t)GLB_PLL_CGEN_Clock_UnGate,
     [ROM_API_INDEX_GLB_Platform_Wakeup_PDS_Enable]         = (uint32_t)GLB_Platform_Wakeup_PDS_Enable,
-    [ROM_API_INDEX_GLB_Power_Off_MU_PLL]                   = (uint32_t)GLB_Power_Off_MU_PLL,
-    [ROM_API_INDEX_GLB_Power_Off_WAC_PLL]                  = (uint32_t)GLB_Power_Off_WAC_PLL,
-    [ROM_API_INDEX_GLB_Power_On_MU_PLL]                    = (uint32_t)GLB_Power_On_MU_PLL,
-    [ROM_API_INDEX_GLB_Power_On_WAC_PLL]                   = (uint32_t)GLB_Power_On_WAC_PLL,
+    [ROM_API_INDEX_GLB_Power_Off_AUPLL]                    = (uint32_t)GLB_Power_Off_AUPLL,
+    [ROM_API_INDEX_GLB_Power_Off_WIFIPLL]                  = (uint32_t)GLB_Power_Off_WIFIPLL,
+    [ROM_API_INDEX_GLB_Power_On_AUPLL]                     = (uint32_t)GLB_Power_On_AUPLL,
+    [ROM_API_INDEX_GLB_Power_On_WIFIPLL]                   = (uint32_t)GLB_Power_On_WIFIPLL,
     [ROM_API_INDEX_GLB_Power_On_XTAL_And_PLL_CLK]          = (uint32_t)GLB_Power_On_XTAL_And_PLL_CLK,
-    [ROM_API_INDEX_GLB_Release_CPU]                        = (uint32_t)GLB_Release_CPU,
+    [ROM_API_INDEX_GLB_SPI_Sig_Swap_Set]                   = (uint32_t)GLB_SPI_Sig_Swap_Set,
     [ROM_API_INDEX_GLB_SW_CPU_Reset]                       = (uint32_t)GLB_SW_CPU_Reset,
     [ROM_API_INDEX_GLB_SW_POR_Reset]                       = (uint32_t)GLB_SW_POR_Reset,
     [ROM_API_INDEX_GLB_SW_System_Reset]                    = (uint32_t)GLB_SW_System_Reset,
-    [ROM_API_INDEX_GLB_Sel_DSP_TMR_GPIO_Clock]             = (uint32_t)GLB_Sel_DSP_TMR_GPIO_Clock,
     [ROM_API_INDEX_GLB_Sel_MCU_TMR_GPIO_Clock]             = (uint32_t)GLB_Sel_MCU_TMR_GPIO_Clock,
     [ROM_API_INDEX_GLB_Set_ADC_CLK]                        = (uint32_t)GLB_Set_ADC_CLK,
     [ROM_API_INDEX_GLB_Set_Audio_ADC_CLK]                  = (uint32_t)GLB_Set_Audio_ADC_CLK,
     [ROM_API_INDEX_GLB_Set_Audio_AUTO_CLK]                 = (uint32_t)GLB_Set_Audio_AUTO_CLK,
-    [ROM_API_INDEX_GLB_Set_Audio_DAC_CLK]                  = (uint32_t)GLB_Set_Audio_DAC_CLK,
-    [ROM_API_INDEX_GLB_Set_Audio_PDM_CLK]                  = (uint32_t)GLB_Set_Audio_PDM_CLK,
+    [ROM_API_INDEX_GLB_Set_Audio_SOLO_CLK]                 = (uint32_t)GLB_Set_Audio_SOLO_CLK,
     [ROM_API_INDEX_GLB_Set_Auto_Calc_Xtal_Type]            = (uint32_t)GLB_Set_Auto_Calc_Xtal_Type,
     [ROM_API_INDEX_GLB_Set_CAM_CLK]                        = (uint32_t)GLB_Set_CAM_CLK,
     [ROM_API_INDEX_GLB_Set_CPU_Reset_Address]              = (uint32_t)GLB_Set_CPU_Reset_Address,
-    [ROM_API_INDEX_GLB_Set_CSI_DSI_CLK_Sel]                = (uint32_t)GLB_Set_CSI_DSI_CLK_Sel,
-    [ROM_API_INDEX_GLB_Set_Chip_Clock_Out0_Sel]            = (uint32_t)GLB_Set_Chip_Clock_Out0_Sel,
-    [ROM_API_INDEX_GLB_Set_Chip_Clock_Out1_Sel]            = (uint32_t)GLB_Set_Chip_Clock_Out1_Sel,
-    [ROM_API_INDEX_GLB_Set_Chip_Clock_Out2_Sel]            = (uint32_t)GLB_Set_Chip_Clock_Out2_Sel,
-    [ROM_API_INDEX_GLB_Set_Chip_Clock_Out3_Sel]            = (uint32_t)GLB_Set_Chip_Clock_Out3_Sel,
+    [ROM_API_INDEX_GLB_Set_Chip_Clock_Out_Sel]             = (uint32_t)GLB_Set_Chip_Clock_Out_Sel,
+    [ROM_API_INDEX_GLB_Set_DBI_CLK]                        = (uint32_t)GLB_Set_DBI_CLK,
     [ROM_API_INDEX_GLB_Set_DIG_32K_CLK]                    = (uint32_t)GLB_Set_DIG_32K_CLK,
     [ROM_API_INDEX_GLB_Set_DIG_512K_CLK]                   = (uint32_t)GLB_Set_DIG_512K_CLK,
     [ROM_API_INDEX_GLB_Set_DIG_CLK_Sel]                    = (uint32_t)GLB_Set_DIG_CLK_Sel,
     [ROM_API_INDEX_GLB_Set_DMA_CLK]                        = (uint32_t)GLB_Set_DMA_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_CNN_CLK]                    = (uint32_t)GLB_Set_DSP_CNN_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_DP_CLK]                     = (uint32_t)GLB_Set_DSP_DP_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_H264_CLK]                   = (uint32_t)GLB_Set_DSP_H264_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_I2C0_CLK]                   = (uint32_t)GLB_Set_DSP_I2C0_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_I2C1_CLK]                   = (uint32_t)GLB_Set_DSP_I2C1_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_DSP2_CLK]                    = (uint32_t)GLB_Set_DSP_DSP2_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_L2SRAM_Available_Size]      = (uint32_t)GLB_Set_DSP_L2SRAM_Available_Size,
-    [ROM_API_INDEX_GLB_Set_DSP_MTimer_CLK]                 = (uint32_t)GLB_Set_DSP_MTimer_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_MUXPLL_CLK_Sel]             = (uint32_t)GLB_Set_DSP_MUXPLL_CLK_Sel,
-    [ROM_API_INDEX_GLB_Set_DSP_Muxpll_160M_Sel]            = (uint32_t)GLB_Set_DSP_Muxpll_160M_Sel,
-    [ROM_API_INDEX_GLB_Set_DSP_Muxpll_240M_Sel]            = (uint32_t)GLB_Set_DSP_Muxpll_240M_Sel,
-    [ROM_API_INDEX_GLB_Set_DSP_Muxpll_320M_Sel]            = (uint32_t)GLB_Set_DSP_Muxpll_320M_Sel,
-    [ROM_API_INDEX_GLB_Set_DSP_PBCLK]                      = (uint32_t)GLB_Set_DSP_PBCLK,
-    [ROM_API_INDEX_GLB_Set_DSP_PBCLK_Div]                  = (uint32_t)GLB_Set_DSP_PBCLK_Div,
-    [ROM_API_INDEX_GLB_Set_DSP_PBROOT_CLK_Sel]             = (uint32_t)GLB_Set_DSP_PBROOT_CLK_Sel,
-    [ROM_API_INDEX_GLB_Set_DSP_ROOT_CLK_Sel]               = (uint32_t)GLB_Set_DSP_ROOT_CLK_Sel,
-    [ROM_API_INDEX_GLB_Set_DSP_SPI_0_ACT_MOD_Sel]          = (uint32_t)GLB_Set_DSP_SPI_0_ACT_MOD_Sel,
-    [ROM_API_INDEX_GLB_Set_DSP_SPI_CLK]                    = (uint32_t)GLB_Set_DSP_SPI_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_System_CLK]                 = (uint32_t)GLB_Set_DSP_System_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_System_CLK_Div]             = (uint32_t)GLB_Set_DSP_System_CLK_Div,
-    [ROM_API_INDEX_GLB_Set_DSP_UART0_CLK]                  = (uint32_t)GLB_Set_DSP_UART0_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_UART1_CLK]                  = (uint32_t)GLB_Set_DSP_UART1_CLK,
-    [ROM_API_INDEX_GLB_Set_DSP_XCLK_Sel]                   = (uint32_t)GLB_Set_DSP_XCLK_Sel,
-    [ROM_API_INDEX_GLB_Set_Display_CLK]                    = (uint32_t)GLB_Set_Display_CLK,
-    [ROM_API_INDEX_GLB_Set_EMAC_CLK]                       = (uint32_t)GLB_Set_EMAC_CLK,
-    [ROM_API_INDEX_GLB_Set_EMI_CLK]                        = (uint32_t)GLB_Set_EMI_CLK,
     [ROM_API_INDEX_GLB_Set_EM_Sel]                         = (uint32_t)GLB_Set_EM_Sel,
     [ROM_API_INDEX_GLB_Set_ETH_REF_O_CLK_Sel]              = (uint32_t)GLB_Set_ETH_REF_O_CLK_Sel,
-    [ROM_API_INDEX_GLB_Set_Flash_IO_PARM]                  = (uint32_t)GLB_Set_Flash_IO_PARM,
-    [ROM_API_INDEX_GLB_Set_Flash_Id_Value]                 = (uint32_t)GLB_Set_Flash_Id_Value,
+    [ROM_API_INDEX_GLB_Set_PEC_CLK]                        = (uint32_t)GLB_Set_PEC_CLK,
     [ROM_API_INDEX_GLB_Set_I2C_CLK]                        = (uint32_t)GLB_Set_I2C_CLK,
     [ROM_API_INDEX_GLB_Set_I2S_CLK]                        = (uint32_t)GLB_Set_I2S_CLK,
     [ROM_API_INDEX_GLB_Set_IR_CLK]                         = (uint32_t)GLB_Set_IR_CLK,
-    [ROM_API_INDEX_GLB_Set_MCU_MTimer_CLK]                 = (uint32_t)GLB_Set_MCU_MTimer_CLK,
+    [ROM_API_INDEX_GLB_Set_ISP_Muxpll_80M_Sel]             = (uint32_t)GLB_Set_ISP_Muxpll_80M_Sel,
     [ROM_API_INDEX_GLB_Set_MCU_Muxpll_160M_Sel]            = (uint32_t)GLB_Set_MCU_Muxpll_160M_Sel,
     [ROM_API_INDEX_GLB_Set_MCU_Muxpll_80M_Sel]             = (uint32_t)GLB_Set_MCU_Muxpll_80M_Sel,
     [ROM_API_INDEX_GLB_Set_MCU_SPI_0_ACT_MOD_Sel]          = (uint32_t)GLB_Set_MCU_SPI_0_ACT_MOD_Sel,
     [ROM_API_INDEX_GLB_Set_MCU_System_CLK]                 = (uint32_t)GLB_Set_MCU_System_CLK,
     [ROM_API_INDEX_GLB_Set_MCU_System_CLK_Div]             = (uint32_t)GLB_Set_MCU_System_CLK_Div,
-    [ROM_API_INDEX_GLB_Set_PADC_CLK]                       = (uint32_t)GLB_Set_PADC_CLK,
     [ROM_API_INDEX_GLB_Set_PDM_IO_Sel]                     = (uint32_t)GLB_Set_PDM_IO_Sel,
     [ROM_API_INDEX_GLB_Set_PKA_CLK_Sel]                    = (uint32_t)GLB_Set_PKA_CLK_Sel,
-    [ROM_API_INDEX_GLB_Set_PSram_CLK]                      = (uint32_t)GLB_Set_PSram_CLK,
+    [ROM_API_INDEX_GLB_Set_PSRAMB_CLK_Sel]                 = (uint32_t)GLB_Set_PSRAMB_CLK_Sel,
     [ROM_API_INDEX_GLB_Set_PWM1_IO_Sel]                    = (uint32_t)GLB_Set_PWM1_IO_Sel,
-    [ROM_API_INDEX_GLB_Set_PWM2_IO_Sel]                    = (uint32_t)GLB_Set_PWM2_IO_Sel,
     [ROM_API_INDEX_GLB_Set_Peripheral_DMA_CN]              = (uint32_t)GLB_Set_Peripheral_DMA_CN,
     [ROM_API_INDEX_GLB_Set_SDH_CLK]                        = (uint32_t)GLB_Set_SDH_CLK,
     [ROM_API_INDEX_GLB_Set_SF_CLK]                         = (uint32_t)GLB_Set_SF_CLK,
+    [ROM_API_INDEX_GLB_Set_SFlash2_IO_PARM]                = (uint32_t)GLB_Set_SFlash2_IO_PARM,
+    [ROM_API_INDEX_GLB_Set_SFlash_IO_PARM]                 = (uint32_t)GLB_Set_SFlash_IO_PARM,
     [ROM_API_INDEX_GLB_Set_SPI_CLK]                        = (uint32_t)GLB_Set_SPI_CLK,
     [ROM_API_INDEX_GLB_Set_SRAM_PARM]                      = (uint32_t)GLB_Set_SRAM_PARM,
     [ROM_API_INDEX_GLB_Set_SRAM_RET]                       = (uint32_t)GLB_Set_SRAM_RET,
     [ROM_API_INDEX_GLB_Set_SRAM_SLP]                       = (uint32_t)GLB_Set_SRAM_SLP,
-    [ROM_API_INDEX_GLB_Set_UART2_IO_Sel]                   = (uint32_t)GLB_Set_UART2_IO_Sel,
+    [ROM_API_INDEX_GLB_Set_SSC_CLK_From_WIFIPLL]           = (uint32_t)GLB_Set_SSC_CLK_From_WIFIPLL,
+    [ROM_API_INDEX_GLB_Set_Slave_Grp_0_CLK]                = (uint32_t)GLB_Set_Slave_Grp_0_CLK,
     [ROM_API_INDEX_GLB_Set_UART_CLK]                       = (uint32_t)GLB_Set_UART_CLK,
     [ROM_API_INDEX_GLB_Set_USB_CLK_From_WIFIPLL]           = (uint32_t)GLB_Set_USB_CLK_From_WIFIPLL,
-    [ROM_API_INDEX_GLB_Swap_DSP_SPI_0_MOSI_With_MISO]      = (uint32_t)GLB_Swap_DSP_SPI_0_MOSI_With_MISO,
     [ROM_API_INDEX_GLB_Swap_MCU_SPI_0_MOSI_With_MISO]      = (uint32_t)GLB_Swap_MCU_SPI_0_MOSI_With_MISO,
-    [ROM_API_INDEX_GLB_Trim_LDO18FLASH_Vout]               = (uint32_t)GLB_Trim_LDO18FLASH_Vout,
-    [ROM_API_INDEX_GLB_Trim_LDO18IO_Vout]                  = (uint32_t)GLB_Trim_LDO18IO_Vout,
+    [ROM_API_INDEX_GLB_Trim_Ldo18ioBypass]                 = (uint32_t)GLB_Trim_Ldo18ioBypass,
+    [ROM_API_INDEX_GLB_Trim_Ldo18ioVoutSel]                = (uint32_t)GLB_Trim_Ldo18ioVoutSel,
+    [ROM_API_INDEX_GLB_Trim_Ldo18ioVoutTrim]               = (uint32_t)GLB_Trim_Ldo18ioVoutTrim,
     [ROM_API_INDEX_GLB_UART_Fun_Sel]                       = (uint32_t)GLB_UART_Fun_Sel,
     [ROM_API_INDEX_GLB_UART_Sig_Swap_Set]                  = (uint32_t)GLB_UART_Sig_Swap_Set,
-    [ROM_API_INDEX_GLB_DSP_Get_LP_IntStatus]               = (uint32_t)GLB_DSP_Get_LP_IntStatus,
-    [ROM_API_INDEX_GLB_DSP_Get_MCU_IntStatus]              = (uint32_t)GLB_DSP_Get_MCU_IntStatus,
-    [ROM_API_INDEX_GLB_MCU_Get_DSP_IntStatus]              = (uint32_t)GLB_MCU_Get_DSP_IntStatus,
+    [ROM_API_INDEX_GLB_WIFIPLL_Ref_Clk_Sel]                = (uint32_t)GLB_WIFIPLL_Ref_Clk_Sel,
     [ROM_API_INDEX_GLB_Get_Core_Type]                      = (uint32_t)GLB_Get_Core_Type,
-    [ROM_API_INDEX_GLB_Get_DSP_Muxpll_160M_Sel]            = (uint32_t)GLB_Get_DSP_Muxpll_160M_Sel,
-    [ROM_API_INDEX_GLB_Get_DSP_Muxpll_240M_Sel]            = (uint32_t)GLB_Get_DSP_Muxpll_240M_Sel,
-    [ROM_API_INDEX_GLB_Get_DSP_Muxpll_320M_Sel]            = (uint32_t)GLB_Get_DSP_Muxpll_320M_Sel,
-    [ROM_API_INDEX_GLB_Get_DSP_PBROOT_CLK_Sel]             = (uint32_t)GLB_Get_DSP_PBROOT_CLK_Sel,
-    [ROM_API_INDEX_GLB_Get_DSP_ROOT_CLK_Sel]               = (uint32_t)GLB_Get_DSP_ROOT_CLK_Sel,
-    [ROM_API_INDEX_GLB_Get_DSP_XCLK_Sel]                   = (uint32_t)GLB_Get_DSP_XCLK_Sel,
     [ROM_API_INDEX_GLB_Get_MCU_Muxpll_160M_Sel]            = (uint32_t)GLB_Get_MCU_Muxpll_160M_Sel,
     [ROM_API_INDEX_GLB_Get_MCU_Muxpll_80M_Sel]             = (uint32_t)GLB_Get_MCU_Muxpll_80M_Sel,
-    [ROM_API_INDEX_GLB_Get_Flash_Id_Value]                 = (uint32_t)GLB_Get_Flash_Id_Value,
     [ROM_API_INDEX_GLB_Get_SRAM_PARM]                      = (uint32_t)GLB_Get_SRAM_PARM,
     [ROM_API_INDEX_GLB_Get_SRAM_RET]                       = (uint32_t)GLB_Get_SRAM_RET,
     [ROM_API_INDEX_GLB_Get_SRAM_SLP]                       = (uint32_t)GLB_Get_SRAM_SLP,
@@ -331,9 +284,12 @@ uint32_t const romDriverTable[]={
 
     [ROM_API_INDEX_HBN_32K_Sel]                            = (uint32_t)HBN_32K_Sel,
     [ROM_API_INDEX_HBN_Aon_Pad_Cfg]                        = (uint32_t)HBN_Aon_Pad_Cfg,
+    [ROM_API_INDEX_HBN_Aon_Pad_Cfg_Set]                    = (uint32_t)HBN_Aon_Pad_Cfg_Set,
     [ROM_API_INDEX_HBN_Aon_Pad_Ctrl]                       = (uint32_t)HBN_Aon_Pad_Ctrl,
     [ROM_API_INDEX_HBN_Aon_Pad_WakeUpCfg]                  = (uint32_t)HBN_Aon_Pad_WakeUpCfg,
+    [ROM_API_INDEX_HBN_Clear_Gpio_Keep]                    = (uint32_t)HBN_Clear_Gpio_Keep,
     [ROM_API_INDEX_HBN_Clear_IRQ]                          = (uint32_t)HBN_Clear_IRQ,
+    [ROM_API_INDEX_HBN_Clear_PDS_Gpio_Keep]                = (uint32_t)HBN_Clear_PDS_Gpio_Keep,
     [ROM_API_INDEX_HBN_Clear_RTC_Counter]                  = (uint32_t)HBN_Clear_RTC_Counter,
     [ROM_API_INDEX_HBN_Clear_RTC_INT]                      = (uint32_t)HBN_Clear_RTC_INT,
     [ROM_API_INDEX_HBN_Disable_AComp0_IRQ]                 = (uint32_t)HBN_Disable_AComp0_IRQ,
@@ -345,12 +301,14 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_HBN_Enable_RTC_Counter]                 = (uint32_t)HBN_Enable_RTC_Counter,
     [ROM_API_INDEX_HBN_GPIO_INT_Disable]                   = (uint32_t)HBN_GPIO_INT_Disable,
     [ROM_API_INDEX_HBN_GPIO_INT_Enable]                    = (uint32_t)HBN_GPIO_INT_Enable,
-    [ROM_API_INDEX_HBN_Get_RTC_Misc_Cfg]                   = (uint32_t)HBN_Get_RTC_Misc_Cfg,
+    [ROM_API_INDEX_HBN_Get_Flash_Power_Delay]              = (uint32_t)HBN_Get_Flash_Power_Delay,
+    [ROM_API_INDEX_HBN_Get_Gpio_Keep]                      = (uint32_t)HBN_Get_Gpio_Keep,
+    [ROM_API_INDEX_HBN_Get_Ldo18io_Power_Delay_Config]     = (uint32_t)HBN_Get_Ldo18io_Power_Delay_Config,
+    [ROM_API_INDEX_HBN_Get_PDS_Gpio_Keep]                  = (uint32_t)HBN_Get_PDS_Gpio_Keep,
     [ROM_API_INDEX_HBN_Get_RTC_Timer_Val]                  = (uint32_t)HBN_Get_RTC_Timer_Val,
     [ROM_API_INDEX_HBN_Get_Xtal_Type]                      = (uint32_t)HBN_Get_Xtal_Type,
     [ROM_API_INDEX_HBN_Hw_Pu_Pd_Cfg]                       = (uint32_t)HBN_Hw_Pu_Pd_Cfg,
-    [ROM_API_INDEX_HBN_PD_RC32K_All_State]                 = (uint32_t)HBN_PD_RC32K_All_State,
-    [ROM_API_INDEX_HBN_PD_RC32K_In_Poff]                   = (uint32_t)HBN_PD_RC32K_In_Poff,
+    [ROM_API_INDEX_HBN_Keep_On_RC32K]                      = (uint32_t)HBN_Keep_On_RC32K,
     [ROM_API_INDEX_HBN_PIR_Disable]                        = (uint32_t)HBN_PIR_Disable,
     [ROM_API_INDEX_HBN_PIR_Enable]                         = (uint32_t)HBN_PIR_Enable,
     [ROM_API_INDEX_HBN_PIR_HPF_Sel]                        = (uint32_t)HBN_PIR_HPF_Sel,
@@ -359,46 +317,45 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_HBN_Pin_WakeUp_Mask]                    = (uint32_t)HBN_Pin_WakeUp_Mask,
     [ROM_API_INDEX_HBN_Power_Off_RC32K]                    = (uint32_t)HBN_Power_Off_RC32K,
     [ROM_API_INDEX_HBN_Power_Off_Xtal_32K]                 = (uint32_t)HBN_Power_Off_Xtal_32K,
-    [ROM_API_INDEX_HBN_Power_On_RC32K]                     = (uint32_t)HBN_Power_On_RC32K,
     [ROM_API_INDEX_HBN_Power_On_Xtal_32K]                  = (uint32_t)HBN_Power_On_Xtal_32K,
     [ROM_API_INDEX_HBN_Reset]                              = (uint32_t)HBN_Reset,
     [ROM_API_INDEX_HBN_Set_BOD_Cfg]                        = (uint32_t)HBN_Set_BOD_Cfg,
     [ROM_API_INDEX_HBN_Set_BOD_Config]                     = (uint32_t)HBN_Set_BOD_Config,
     [ROM_API_INDEX_HBN_Set_Core_Reboot_Config]             = (uint32_t)HBN_Set_Core_Reboot_Config,
+    [ROM_API_INDEX_HBN_Set_Flash_Power_Delay]              = (uint32_t)HBN_Set_Flash_Power_Delay,
+    [ROM_API_INDEX_HBN_Set_GPADC_CLK_Sel]                  = (uint32_t)HBN_Set_GPADC_CLK_Sel,
+    [ROM_API_INDEX_HBN_Set_Gpio_Keep]                      = (uint32_t)HBN_Set_Gpio_Keep,
     [ROM_API_INDEX_HBN_Set_HRAM_Ret]                       = (uint32_t)HBN_Set_HRAM_Ret,
     [ROM_API_INDEX_HBN_Set_HRAM_slp]                       = (uint32_t)HBN_Set_HRAM_slp,
-    [ROM_API_INDEX_HBN_Set_Hand_Off_Config]                = (uint32_t)HBN_Set_Hand_Off_Config,
-    [ROM_API_INDEX_HBN_Set_IO4041_As_Xtal_32K_IO]          = (uint32_t)HBN_Set_IO4041_As_Xtal_32K_IO,
     [ROM_API_INDEX_HBN_Set_Ldo11_All_Vout]                 = (uint32_t)HBN_Set_Ldo11_All_Vout,
     [ROM_API_INDEX_HBN_Set_Ldo11_Aon_Vout]                 = (uint32_t)HBN_Set_Ldo11_Aon_Vout,
     [ROM_API_INDEX_HBN_Set_Ldo11_Rt_Vout]                  = (uint32_t)HBN_Set_Ldo11_Rt_Vout,
-    [ROM_API_INDEX_HBN_Set_Ldo11_Rtc_Vout]                 = (uint32_t)HBN_Set_Ldo11_Rtc_Vout,
-    [ROM_API_INDEX_HBN_Set_Ldo18flash_Repower_Delay]       = (uint32_t)HBN_Set_Ldo18flash_Repower_Delay,
+    [ROM_API_INDEX_HBN_Set_Ldo11_Soc_Vout]                 = (uint32_t)HBN_Set_Ldo11_Soc_Vout,
+    [ROM_API_INDEX_HBN_Set_Ldo18io_Power_Delay_Config]     = (uint32_t)HBN_Set_Ldo18io_Power_Delay_Config,
     [ROM_API_INDEX_HBN_Set_MCU_Root_CLK_Sel]               = (uint32_t)HBN_Set_MCU_Root_CLK_Sel,
     [ROM_API_INDEX_HBN_Set_MCU_XCLK_Sel]                   = (uint32_t)HBN_Set_MCU_XCLK_Sel,
-    [ROM_API_INDEX_HBN_Set_MM_Power_Config]                = (uint32_t)HBN_Set_MM_Power_Config,
+    [ROM_API_INDEX_HBN_Set_PDS_Gpio_Keep]                  = (uint32_t)HBN_Set_PDS_Gpio_Keep,
     [ROM_API_INDEX_HBN_Set_PIR_Interval]                   = (uint32_t)HBN_Set_PIR_Interval,
     [ROM_API_INDEX_HBN_Set_PIR_Threshold]                  = (uint32_t)HBN_Set_PIR_Threshold,
-    [ROM_API_INDEX_HBN_Set_RTC_Misc_Cfg]                   = (uint32_t)HBN_Set_RTC_Misc_Cfg,
     [ROM_API_INDEX_HBN_Set_RTC_Timer]                      = (uint32_t)HBN_Set_RTC_Timer,
     [ROM_API_INDEX_HBN_Set_Status_Flag]                    = (uint32_t)HBN_Set_Status_Flag,
     [ROM_API_INDEX_HBN_Set_UART_CLK_Sel]                   = (uint32_t)HBN_Set_UART_CLK_Sel,
+    [ROM_API_INDEX_HBN_Set_User_Boot_Config]               = (uint32_t)HBN_Set_User_Boot_Config,
     [ROM_API_INDEX_HBN_Set_Wakeup_Addr]                    = (uint32_t)HBN_Set_Wakeup_Addr,
     [ROM_API_INDEX_HBN_Set_Xtal_Type]                      = (uint32_t)HBN_Set_Xtal_Type,
+    [ROM_API_INDEX_HBN_Trim_Ldo33VoutTrim]                 = (uint32_t)HBN_Trim_Ldo33VoutTrim,
     [ROM_API_INDEX_HBN_Trim_RC32K]                         = (uint32_t)HBN_Trim_RC32K,
     [ROM_API_INDEX_HBN_Get_BOD_OUT_State]                  = (uint32_t)HBN_Get_BOD_OUT_State,
     [ROM_API_INDEX_HBN_Get_INT_State]                      = (uint32_t)HBN_Get_INT_State,
     [ROM_API_INDEX_HBN_Get_MCU_Root_CLK_Sel]               = (uint32_t)HBN_Get_MCU_Root_CLK_Sel,
     [ROM_API_INDEX_HBN_Get_MCU_XCLK_Sel]                   = (uint32_t)HBN_Get_MCU_XCLK_Sel,
-    [ROM_API_INDEX_HBN_Get_Ldo18flash_Repower_Config]      = (uint32_t)HBN_Get_Ldo18flash_Repower_Config,
     [ROM_API_INDEX_HBN_Get_PIR_Interval]                   = (uint32_t)HBN_Get_PIR_Interval,
     [ROM_API_INDEX_HBN_Get_PIR_Threshold]                  = (uint32_t)HBN_Get_PIR_Threshold,
     [ROM_API_INDEX_HBN_Get_Status_Flag]                    = (uint32_t)HBN_Get_Status_Flag,
     [ROM_API_INDEX_HBN_Get_Wakeup_Addr]                    = (uint32_t)HBN_Get_Wakeup_Addr,
     [ROM_API_INDEX_HBN_Get_Core_Unhalt_Config]             = (uint32_t)HBN_Get_Core_Unhalt_Config,
-    [ROM_API_INDEX_HBN_Get_Hand_Off_Config]                = (uint32_t)HBN_Get_Hand_Off_Config,
-    [ROM_API_INDEX_HBN_Get_MM_Power_Config]                = (uint32_t)HBN_Get_MM_Power_Config,
     [ROM_API_INDEX_HBN_Get_Pin_Wakeup_Mode]                = (uint32_t)HBN_Get_Pin_Wakeup_Mode,
+    [ROM_API_INDEX_HBN_Get_User_Boot_Config]               = (uint32_t)HBN_Get_User_Boot_Config,
     [ROM_API_INDEX_HBN_Enable]                             = (uint32_t)HBN_Enable,
     [ROM_API_INDEX_HBN_Mode_Enter]                         = (uint32_t)HBN_Mode_Enter,
     [ROM_API_INDEX_HBN_Power_Down_Flash]                   = (uint32_t)HBN_Power_Down_Flash,
@@ -417,30 +374,21 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_L1C_ICache_Invalid_By_Addr]             = (uint32_t)L1C_ICache_Invalid_By_Addr,
     [ROM_API_INDEX_L1C_Set_Cache_Setting_By_ID]            = (uint32_t)L1C_Set_Cache_Setting_By_ID,
     [ROM_API_INDEX_L1C_Set_Wrap]                           = (uint32_t)L1C_Set_Wrap,
-    [ROM_API_INDEX_L1C_Get_None_Cache_Addr]                = (uint32_t)L1C_Get_None_Cache_Addr,
-    [ROM_API_INDEX_L1C_Is_DCache_Range]                    = (uint32_t)L1C_Is_DCache_Range,
     [ROM_API_INDEX_L1C_DCache_Write_Set]                   = (uint32_t)L1C_DCache_Write_Set,
 
     [ROM_API_INDEX_PDS_Default_Level_Config]               = (uint32_t)PDS_Default_Level_Config,
+    [ROM_API_INDEX_PDS_Disable_GPIO_Keep]                  = (uint32_t)PDS_Disable_GPIO_Keep,
     [ROM_API_INDEX_PDS_Enable]                             = (uint32_t)PDS_Enable,
     [ROM_API_INDEX_PDS_Force_Config]                       = (uint32_t)PDS_Force_Config,
     [ROM_API_INDEX_PDS_IntClear]                           = (uint32_t)PDS_IntClear,
     [ROM_API_INDEX_PDS_IntMask]                            = (uint32_t)PDS_IntMask,
-    [ROM_API_INDEX_PDS_Power_On_MM_System]                 = (uint32_t)PDS_Power_On_MM_System,
     [ROM_API_INDEX_PDS_RAM_Config]                         = (uint32_t)PDS_RAM_Config,
-    [ROM_API_INDEX_PDS_Reset_LP_RTC]                       = (uint32_t)PDS_Reset_LP_RTC,
     [ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None]            = (uint32_t)PDS_Set_Flash_Pad_Pull_None,
     [ROM_API_INDEX_PDS_Set_Flash_Pad_Pull_None_Fast]       = (uint32_t)PDS_Set_Flash_Pad_Pull_None_Fast,
     [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntClr]                = (uint32_t)PDS_Set_GPIO_Pad_IntClr,
     [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMask]               = (uint32_t)PDS_Set_GPIO_Pad_IntMask,
     [ROM_API_INDEX_PDS_Set_GPIO_Pad_IntMode]               = (uint32_t)PDS_Set_GPIO_Pad_IntMode,
     [ROM_API_INDEX_PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie]           = (uint32_t)PDS_Set_GPIO_Pad_Pn_Pu_Pd_Ie,
-    [ROM_API_INDEX_PDS_Set_LP_Clock_Disable]               = (uint32_t)PDS_Set_LP_Clock_Disable,
-    [ROM_API_INDEX_PDS_Set_LP_Clock_Enable]                = (uint32_t)PDS_Set_LP_Clock_Enable,
-    [ROM_API_INDEX_PDS_Set_LP_RTC_CLK]                     = (uint32_t)PDS_Set_LP_RTC_CLK,
-    [ROM_API_INDEX_PDS_Set_LP_Reset_Address]               = (uint32_t)PDS_Set_LP_Reset_Address,
-    [ROM_API_INDEX_PDS_Set_LP_System_CLK]                  = (uint32_t)PDS_Set_LP_System_CLK,
-    [ROM_API_INDEX_PDS_Set_LP_System_CLK_Div]              = (uint32_t)PDS_Set_LP_System_CLK_Div,
     [ROM_API_INDEX_PDS_Set_MCU0_Clock_Disable]             = (uint32_t)PDS_Set_MCU0_Clock_Disable,
     [ROM_API_INDEX_PDS_Set_MCU0_Clock_Enable]              = (uint32_t)PDS_Set_MCU0_Clock_Enable,
     [ROM_API_INDEX_PDS_Set_MCU0_Reset_Address]             = (uint32_t)PDS_Set_MCU0_Reset_Address,
@@ -451,17 +399,15 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_PDS_Turn_On_USB]                        = (uint32_t)PDS_Turn_On_USB,
     [ROM_API_INDEX_PDS_Get_GPIO_Pad_IntStatus]             = (uint32_t)PDS_Get_GPIO_Pad_IntStatus,
     [ROM_API_INDEX_PDS_Get_IntStatus]                      = (uint32_t)PDS_Get_IntStatus,
-    [ROM_API_INDEX_PDS_Get_MM_System_Power_On_State]       = (uint32_t)PDS_Get_MM_System_Power_On_State,
 
     [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio]           = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio,
     [ROM_API_INDEX_SF_Cfg_Flash_Init]                      = (uint32_t)SF_Cfg_Flash_Init,
     [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock]         = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock,
-    [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext]     = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock_Ext,
     [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio]             = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Init_Flash2_Gpio]                = (uint32_t)SF_Cfg_Init_Flash2_Gpio,
     [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio]                 = (uint32_t)SF_Cfg_Init_Flash_Gpio,
     [ROM_API_INDEX_SF_Cfg_Sbus2_Flash_Init]                = (uint32_t)SF_Cfg_Sbus2_Flash_Init,
     [ROM_API_INDEX_SF_Cfg_Flash_Identify]                  = (uint32_t)SF_Cfg_Flash_Identify,
-    [ROM_API_INDEX_SF_Cfg_Flash_Identify_Ext]              = (uint32_t)SF_Cfg_Flash_Identify_Ext,
     [ROM_API_INDEX_SF_Ctrl_GetBusyState]                   = (uint32_t)SF_Ctrl_GetBusyState,
     [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable]                  = (uint32_t)SF_Ctrl_Is_AES_Enable,
     [ROM_API_INDEX_SF_Ctrl_Is_Sbus2_Enable]                = (uint32_t)SF_Ctrl_Is_Sbus2_Enable,
@@ -542,7 +488,6 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_SFlash_SetBurstWrap]                    = (uint32_t)SFlash_SetBurstWrap,
     [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable]       = (uint32_t)SFlash_Volatile_Reg_Write_Enable,
 
-    [ROM_API_INDEX_UART_ApplyAbrResult]                    = (uint32_t)UART_ApplyAbrResult,
     [ROM_API_INDEX_UART_AutoBaudDetection]                 = (uint32_t)UART_AutoBaudDetection,
     [ROM_API_INDEX_UART_ClrRtsValue]                       = (uint32_t)UART_ClrRtsValue,
     [ROM_API_INDEX_UART_ClrTxValue]                        = (uint32_t)UART_ClrTxValue,
@@ -559,7 +504,7 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_UART_SendData]                          = (uint32_t)UART_SendData,
     [ROM_API_INDEX_UART_SendDataBlock]                     = (uint32_t)UART_SendDataBlock,
     [ROM_API_INDEX_UART_SetAllowableError0X55]             = (uint32_t)UART_SetAllowableError0X55,
-    [ROM_API_INDEX_UART_SetBaudRate]                       = (uint32_t)UART_SetBaudRate,
+    [ROM_API_INDEX_UART_SetBaudrate]                       = (uint32_t)UART_SetBaudrate,
     [ROM_API_INDEX_UART_SetDeglitchCount]                  = (uint32_t)UART_SetDeglitchCount,
     [ROM_API_INDEX_UART_SetRS485]                          = (uint32_t)UART_SetRS485,
     [ROM_API_INDEX_UART_SetRtsValue]                       = (uint32_t)UART_SetRtsValue,
@@ -592,6 +537,23 @@ uint32_t const romDriverTable[]={
     [ROM_API_INDEX_XIP_SFlash_Opt_Enter]                   = (uint32_t)XIP_SFlash_Opt_Enter,
     [ROM_API_INDEX_XIP_SFlash_Opt_Exit]                    = (uint32_t)XIP_SFlash_Opt_Exit,
 
+    [ROM_API_INDEX_MD_Clr_GPIO_IntStatus]                  = (uint32_t)MD_Clr_GPIO_IntStatus,
+    [ROM_API_INDEX_MD_Embedded_Flash_Pad_Enable]           = (uint32_t)MD_Embedded_Flash_Pad_Enable,
+    [ROM_API_INDEX_MD_GPIO_Clr]                            = (uint32_t)MD_GPIO_Clr,
+    [ROM_API_INDEX_MD_GPIO_Init]                           = (uint32_t)MD_GPIO_Init,
+    [ROM_API_INDEX_MD_GPIO_Input_Disable]                  = (uint32_t)MD_GPIO_Input_Disable,
+    [ROM_API_INDEX_MD_GPIO_Input_Enable]                   = (uint32_t)MD_GPIO_Input_Enable,
+    [ROM_API_INDEX_MD_GPIO_IntMask]                        = (uint32_t)MD_GPIO_IntMask,
+    [ROM_API_INDEX_MD_GPIO_Int_Init]                       = (uint32_t)MD_GPIO_Int_Init,
+    [ROM_API_INDEX_MD_GPIO_Output_Disable]                 = (uint32_t)MD_GPIO_Output_Disable,
+    [ROM_API_INDEX_MD_GPIO_Output_Enable]                  = (uint32_t)MD_GPIO_Output_Enable,
+    [ROM_API_INDEX_MD_GPIO_Set]                            = (uint32_t)MD_GPIO_Set,
+    [ROM_API_INDEX_MD_GPIO_Set_HZ]                         = (uint32_t)MD_GPIO_Set_HZ,
+    [ROM_API_INDEX_MD_GPIO_Write]                          = (uint32_t)MD_GPIO_Write,
+    [ROM_API_INDEX_MD_Get_GPIO_IntStatus]                  = (uint32_t)MD_Get_GPIO_IntStatus,
+    [ROM_API_INDEX_MD_GPIO_Read]                           = (uint32_t)MD_GPIO_Read,
+    [ROM_API_INDEX_MD_GPIO_Get_Fun]                        = (uint32_t)MD_GPIO_Get_Fun,
+
     [ROM_API_INDEX_FUNC_EMPTY_START ... ROM_API_INDEX_FUNC_EMPTY_END] = 0xdeedbeef,
 };
 
@@ -618,6 +580,6 @@ uint32_t const romDriverTable[]={
 
 /*@} end of group ROMDRIVER_COMMON */
 
-/*@} end of group BL808_Periph_Driver */
+/*@} end of group BL616_Periph_Driver */
 
 
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdh.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdh.c
new file mode 100755
index 0000000000..a3888155f0
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdh.c
@@ -0,0 +1,1363 @@
+/**
+  ******************************************************************************
+  * @file    bl616_sdh.c
+  * @version V1.2
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2018 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl616.h"
+#include "string.h"
+#include "bl616_sdh.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SDH
+ *  @{
+ */
+
+/** @defgroup  SDH_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SDH_Private_Macros */
+
+/** @defgroup  SDH_Private_Types
+ *  @{
+ */
+
+/*@} end of group SDH_Private_Types */
+
+/** @defgroup  SDH_Private_Variables
+ *  @{
+ */
+static uint32_t bootDummy = 0;
+static SDH_Handle_Cfg_Type *sdhHandle = NULL;
+
+/*@} end of group SDH_Private_Variables */
+
+/** @defgroup  SDH_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SDH_Global_Variables */
+
+/** @defgroup  SDH_Private_Fun_Declaration
+ *  @{
+ */
+static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle);
+
+/*@} end of group SDH_Private_Fun_Declaration */
+
+/** @defgroup  SDH_Private_Functions
+ *  @{
+ */
+
+/*@} end of group SDH_Private_Functions */
+
+/** @defgroup  SDH_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enable SDH DMA
+ *
+ * @param  dmaMode: DMA mode select
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_EnableDMA(SDH_DMA_Mode_Type dmaMode)
+{
+    uint16_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_SDH_DMA_MODE_TYPE(dmaMode));
+
+    /* Select DMA type */
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DMA_SEL, dmaMode);
+    BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SDH_DMA_EN);
+    BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable SDH DMA
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_DisableDMA(void)
+{
+    uint16_t tmpVal;
+
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_DMA_EN);
+    BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+}
+/****************************************************************************/ /**
+ * @brief  SDH enable interrupt
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_ITConfig(uint32_t SDH_IT_FLAG, BL_Fun_Type NewState)
+{
+    if (NewState != DISABLE) {
+        /* Enable the SDH interrupts */
+        SDH_EnableIntSource(SDH_IT_FLAG);
+    } else {
+        /* Disable the SDH interrupts */
+        SDH_DisableIntSource(SDH_IT_FLAG);
+    }
+}
+/****************************************************************************/ /**
+ * @brief  SDH enable interrupt
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_EnableStatus(void)
+{
+    uint32_t tmpVal;
+
+    /* Disable all interrupts */
+    SDH_DisableIntStatus(SDH_INT_ALL);
+
+    tmpVal = (SDH_INT_CMD_TIMEOUT | SDH_INT_CMD_CRC_ERROR | SDH_INT_CMD_ENDBIT_ERROR |
+              SDH_INT_CMD_INDEX_ERROR | SDH_INT_CMD_COMPLETED |
+              SDH_INT_CARD_INSERT | SDH_INT_CARD_REMOVE |
+              SDH_INT_DATA_COMPLETED | SDH_INT_DMA_COMPLETED |
+              SDH_INT_BUFFER_WRITE_READY | SDH_INT_BUFFER_READ_READY |
+              SDH_INT_DATA_TIMEOUT | SDH_INT_DATA_CRC_ERROR | SDH_INT_DATA_ENDBIT_ERROR |
+              SDH_INT_AUTO_CMD12_ERROR | SDH_INT_DMA_ERROR | SDH_INT_BLK_GAP_EVENT |
+              SDH_INT_RETUNE_EVENT | SDH_INT_TUNE_ERROR);
+
+    SDH_EnableIntStatus(tmpVal);
+}
+/****************************************************************************/ /**
+ * @brief  SDH enable interrupt
+ *
+ * @param  dataCfg: Transfer data config pointer
+ *
+ * @return SDH status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_ConfigDataTranfer(SDH_Data_Cfg_Type *dataCfg)
+{
+    uint16_t tmpVal;
+
+    if (dataCfg != NULL) {
+        /* For transfer boot continous, only need to set the CREQ bit */
+        if (dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) {
+            tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_BLOCK_GAP_CTRL);
+            /* Clear stop at block gap request */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_STOP_AT_BLOCK_GAP_REQ);
+            /* Continous transfer data */
+            tmpVal = BL_SET_REG_BIT(tmpVal, SDH_CONT_REQ);
+            BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_GAP_CTRL, tmpVal);
+
+            return SDH_STAT_SUCCESS;
+        }
+
+        tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+
+        /* Check data inhibit flag */
+        if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_DAT)) {
+            return SDH_STAT_BUSY;
+        }
+
+        tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+
+        /* Check transfer block count */
+        if ((dataCfg->blockCount > SDH_MAX_BLOCK_COUNT) || ((dataCfg->txData == NULL) && (dataCfg->rxData == NULL))) {
+            return SDH_STAT_INVLAID_PARA;
+        }
+
+        if (dataCfg->rxData) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, SDH_TO_HOST_DIR);
+        } else {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_TO_HOST_DIR);
+        }
+
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x00);
+
+        /* auto command 23, auto send set block count cmd before multiple read/write */
+        if (dataCfg->enableAutoCommand23) {
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x02);
+            BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, dataCfg->blockCount);
+        } else if (dataCfg->enableAutoCommand12) {
+            /* auto command 12 */
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x01);
+        }
+
+        if (dataCfg->blockCount > 1U) {
+            tmpVal = BL_SET_REG_BIT(tmpVal, SDH_MULTI_BLK_SEL);
+        } else {
+            tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_MULTI_BLK_SEL);
+        }
+
+        /* Enable block count */
+        tmpVal = BL_SET_REG_BIT(tmpVal, SDH_BLK_CNT_EN);
+
+        BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+
+        /* if transfer boot data, leave the block count to SDH_SetMmcBootConfig function */
+        if (dataCfg->dataType != SDH_TRANS_DATA_BOOT) {
+            /* config data block size/block count */
+            BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_SIZE, dataCfg->blockSize);
+            BL_WR_REG16(SDH_BASE, SDH_SD_BLOCK_COUNT, dataCfg->blockCount);
+        }
+    } else {
+        /* clear data flags */
+        tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_AUTO_CMD_EN, 0x00);
+        BL_WR_REG16(SDH_BASE, SDH_SD_TRANSFER_MODE, tmpVal);
+
+        tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+
+        /* Check data inhibit flag */
+        if (BL_IS_REG_BIT_SET(tmpVal, SDH_CMD_INHIBIT_CMD)) {
+            return SDH_STAT_BUSY;
+        }
+    }
+
+    return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH enable interrupt
+ *
+ * @param  cmd: Transfer data config pointer
+ *
+ * @return SDH status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_GetCmdResp(SDH_CMD_Cfg_Type *cmd)
+{
+    if (cmd->respType != SDH_RESP_NONE) {
+        cmd->response[0U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_0);
+        cmd->response[1U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_2);
+        cmd->response[2U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_4);
+        cmd->response[3U] = BL_RD_REG(SDH_BASE, SDH_SD_RESP_6);
+    }
+
+    return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH read data port
+ *
+ * @param  dataCfg: Transfer data config pointer
+ *
+ * @return Read length
+ *
+*******************************************************************************/
+uint32_t SDH_ReadDataPort(SDH_Data_Cfg_Type *dataCfg)
+{
+    uint32_t tmpVal;
+    uint32_t totalLen, recvLen = 0;
+
+    totalLen = (dataCfg->blockCount * dataCfg->blockSize);
+    tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_TRANSFER_MODE);
+
+    if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) {
+        do {
+            dataCfg->rxData[dataCfg->rxDataLen++] = BL_RD_REG(SDH_BASE, SDH_SD_BUFFER_DATA_PORT_0);
+            recvLen += 4;
+        } while (recvLen < totalLen);
+    }
+
+    return recvLen;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH read data port
+ *
+ * @param  dataCfg: Transfer data config pointer
+ *
+ * @return Read length
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_ReadDataPortBlock(SDH_Data_Cfg_Type *dataCfg)
+{
+    uint32_t intStatus = 0U;
+    SDH_Stat_Type error = SDH_STAT_SUCCESS;
+
+    /* Make sure the buffer size is 4 byte aligned */
+    if (dataCfg->blockSize % sizeof(uint32_t) != 0U) {
+        dataCfg->blockSize += sizeof(uint32_t) - (dataCfg->blockSize % sizeof(uint32_t));
+    }
+
+    while (!(intStatus & (SDH_INT_BUFFER_READ_READY | SDH_INT_DATA_ERRORS | SDH_INT_TUNE_ERROR))) {
+        intStatus = SDH_GetIntStatus();
+    }
+
+    /* during std tuning process, software do not need to read data, but wait BRR is enough */
+    if ((dataCfg->dataType == SDH_TRANS_DATA_TUNING) && (intStatus & SDH_INT_BUFFER_READ_READY)) {
+        SDH_ClearIntStatus(SDH_INT_BUFFER_READ_READY);
+        return SDH_STAT_SUCCESS;
+    } else if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+        SDH_ClearIntStatus(SDH_INT_TUNE_ERROR);
+        /* if tuning error occur ,return directly */
+        error = SDH_STAT_TUNE_ERROR;
+    } else if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {
+        if (!(dataCfg->enableIgnoreError)) {
+            error = SDH_STAT_RECV_DATA_FAIL;
+        }
+
+        /* clear data error flag */
+        SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);
+    }
+
+    if (error == SDH_STAT_SUCCESS) {
+        SDH_ReadDataPort(dataCfg);
+        /* clear buffer read ready */
+        SDH_ClearIntStatus(SDH_INT_BUFFER_READ_READY);
+        intStatus = 0U;
+    }
+
+    /* Clear data complete flag after the last read operation. */
+    SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED);
+
+    return error;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH write data port
+ *
+ * @param  dataCfg: Transfer data config pointer
+ *
+ * @return write length
+ *
+*******************************************************************************/
+uint32_t SDH_WriteDataPort(SDH_Data_Cfg_Type *dataCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_TRANSFER_MODE);
+
+    if (!BL_IS_REG_BIT_SET(tmpVal, SDH_DMA_EN)) {
+        BL_WR_REG(SDH_BASE, SDH_SD_BUFFER_DATA_PORT_0, dataCfg->txData[dataCfg->txDataLen++]);
+    }
+
+    return 4;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH write data port
+ *
+ * @param  dataCfg: Transfer data config pointer
+ *
+ * @return Write length
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_WriteDataPortBlock(SDH_Data_Cfg_Type *dataCfg)
+{
+    uint32_t totalLen;
+    uint32_t txLen = 0U, intStatus = 0U;
+    SDH_Stat_Type error = SDH_STAT_SUCCESS;
+
+    /* Make sure the buffer size is 4 byte aligned */
+    if (dataCfg->blockSize % sizeof(uint32_t) != 0U) {
+        dataCfg->blockSize += sizeof(uint32_t) - (dataCfg->blockSize % sizeof(uint32_t));
+    }
+
+    totalLen = (dataCfg->blockCount * dataCfg->blockSize);
+
+    while ((error == SDH_STAT_SUCCESS) && (txLen < totalLen)) {
+        while (!(intStatus & (SDH_INT_BUFFER_WRITE_READY | SDH_INT_DATA_ERRORS | SDH_INT_TUNE_ERROR))) {
+            intStatus = SDH_GetIntStatus();
+        }
+
+        if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+            SDH_ClearIntStatus(SDH_INT_TUNE_ERROR);
+            /* if tuning error occur ,return directly */
+            error = SDH_STAT_TUNE_ERROR;
+        } else if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {
+            if (!(dataCfg->enableIgnoreError)) {
+                error = SDH_STAT_RECV_DATA_FAIL;
+            }
+
+            /* clear data error flag */
+            SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);
+        }
+
+        if (error == SDH_STAT_SUCCESS) {
+            txLen += SDH_WriteDataPort(dataCfg);
+            /* clear buffer read ready */
+            SDH_ClearIntStatus(SDH_INT_BUFFER_WRITE_READY);
+            intStatus = 0U;
+        }
+    }
+
+    while (!(intStatus & (SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS))) {
+        intStatus = SDH_GetIntStatus();
+    }
+
+    if ((intStatus & SDH_INT_DATA_ERRORS) != 0U) {
+        if (!(dataCfg->enableIgnoreError)) {
+            error = SDH_STAT_RECV_DATA_FAIL;
+        }
+
+        /* clear data error flag */
+        SDH_ClearIntStatus(SDH_INT_DATA_ERRORS);
+    }
+
+    SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED);
+
+    return error;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH send command
+ *
+ * @param  cmd: command config pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_SendCommand(SDH_CMD_Cfg_Type *cmd)
+{
+    uint32_t tmpVal;
+    uint32_t flag = cmd->flag;
+    //uint32_t flag = 0;
+
+    tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_PRESENT_STATE_1);
+
+    if (((tmpVal & SDH_PRESENT_FLAG_CMD_INHBIT) == 0U) && (cmd->type != SDH_CMD_EMPTY)) {
+        /* Define the flag corresponding to each response type. */
+        switch (cmd->respType) {
+            case SDH_RESP_NONE:
+                break;
+
+            case SDH_RESP_R1: /* Response 1 */
+            case SDH_RESP_R5: /* Response 5 */
+            case SDH_RESP_R6: /* Response 6 */
+            case SDH_RESP_R7: /* Response 7 */
+                flag |= (SDH_TRANS_FLAG_RESP_48BITS | SDH_TRANS_FLAG_EN_CRC_CHECK | SDH_TRANS_FLAG_EN_INDEX_CHECK);
+                break;
+
+            case SDH_RESP_R1B: /* Response 1 with busy */
+            case SDH_RESP_R5B: /* Response 5 with busy */
+                flag |= (SDH_TRANS_FLAG_RESP_48BITS_WITH_BUSY | SDH_TRANS_FLAG_EN_CRC_CHECK | SDH_TRANS_FLAG_EN_INDEX_CHECK);
+                break;
+
+            case SDH_RESP_R2: /* Response 2 */
+                flag |= (SDH_TRANS_FLAG_RESP_136BITS | SDH_TRANS_FLAG_EN_CRC_CHECK);
+                break;
+
+            case SDH_RESP_R3: /* Response 3 */
+            case SDH_RESP_R4: /* Response 4 */
+                flag |= (SDH_TRANS_FLAG_RESP_48BITS);
+                break;
+
+            default:
+                break;
+        }
+
+        /* Config command index */
+        tmpVal = flag >> 16;
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CMD_TYPE, cmd->type);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CMD_INDEX, cmd->index);
+
+        /* Config command argument */
+        BL_WR_REG(SDH_BASE, SDH_SD_ARG_LOW, cmd->argument);
+
+        /* Config command index */
+        BL_WR_REG16(SDH_BASE, SDH_SD_CMD, tmpVal);
+    }
+
+    /* FIXME:how to enable again */
+    if (cmd->type == SDH_CMD_EMPTY) {
+        SDH_DisableIntSource(SDH_INT_CMD_COMPLETED);
+    }
+}
+/****************************************************************************/ /**
+ * @brief  SDH wait command send done
+ *
+ * @param  cmd: Command config pointer
+ *
+ * @return Command deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_WaitCommandDone(SDH_CMD_Cfg_Type *cmd)
+{
+    uint32_t intStatus = 0U;
+    SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+
+    /* Wait command complete or encounters error. */
+    while (!(intStatus & (SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS | SDH_INT_TUNE_ERROR))) {
+        intStatus = SDH_GetIntStatus();
+    }
+
+    if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+        stat = SDH_STAT_TUNE_ERROR;
+    } else if ((intStatus & SDH_INT_CMD_ERRORS) != 0U) {
+        stat = SDH_STAT_SEND_CMD_FAIL;
+    }
+
+    /* Receive response when command completes successfully. */
+    if (stat == SDH_STAT_SUCCESS) {
+        stat = SDH_GetCmdResp(cmd);
+    }
+
+    SDH_ClearIntStatus(SDH_INT_CMD_COMPLETED | SDH_INT_CMD_ERRORS | SDH_INT_TUNE_ERROR);
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH transfer data
+ *
+ * @param  dataCfg: Data config pointer
+ * @param  enDMA: Whether enable DMA
+ *
+ * @return command deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_TransferDataBlocking(SDH_Data_Cfg_Type *dataCfg, uint8_t enDMA)
+{
+    SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+    uint32_t intStatus = 0U;
+
+    if (enDMA) {
+        /* Wait dataCfg complete or encounters error. */
+        while (!(intStatus & (SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS |
+                              SDH_INT_DMA_ERROR | SDH_INT_TUNE_ERROR))) {
+            intStatus = SDH_GetIntStatus();
+        }
+
+        if ((intStatus & SDH_INT_TUNE_ERROR) != 0U) {
+            stat = SDH_STAT_TUNE_ERROR;
+        } else if ((intStatus & (SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR)) != 0U) {
+            if ((!(dataCfg->enableIgnoreError)) || (intStatus & SDH_INT_DATA_TIMEOUT)) {
+                stat = SDH_STAT_SEND_DATA_FAIL;
+            }
+        }
+
+        /* load dummy data */
+        if ((dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) && (stat == SDH_STAT_SUCCESS)) {
+            *(dataCfg->rxData) = bootDummy;
+        }
+
+        SDH_ClearIntStatus(SDH_INT_DATA_COMPLETED | SDH_INT_DATA_ERRORS |
+                           SDH_INT_DMA_ERROR | SDH_INT_TUNE_ERROR);
+    } else {
+        if (dataCfg->rxData) {
+            stat = SDH_ReadDataPortBlock(dataCfg);
+        } else {
+            stat = SDH_WriteDataPortBlock(dataCfg);
+        }
+    }
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH set clock
+ *
+ * @param  srcClock: Source clock frequency in Hz
+ * @param  busClock: SDH clock frequency in Hz
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock)
+{
+    uint16_t tmpVal;
+    uint16_t div = srcClock / busClock / 2;
+
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL);
+
+    /* Disable internal clock*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_INT_CLK_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_SD_CLK_EN);
+
+    /* Set divdier */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_FREQ_SEL_LO, div & 0xff);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_FREQ_SEL_HI, (div >> 8) & 0x3);
+    /* 0x1 = Programmable Clock Mode,0x0 = Divided Clock mode */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_CLK_GEN_SEL, 0);
+
+    /* Enable internal clock*/
+    tmpVal = BL_SET_REG_BIT(tmpVal, SDH_INT_CLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SD_CLK_EN);
+
+    BL_WR_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL, tmpVal);
+
+    /* Wait for clock stable */
+    do {
+        tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_CTRL);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, SDH_INT_CLK_STABLE));
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH disable clock
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_DisableSdClock(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(SDH_BASE, SDH_SD_CLOCK_CTRL);
+
+    /* Disable internal clock*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_INT_CLK_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_SD_CLK_EN);
+
+    BL_WR_REG(SDH_BASE, SDH_SD_CLOCK_CTRL, tmpVal);
+}
+/****************************************************************************
+ * @brief  SDH init function
+ *
+ * @param  cfg: SDH config pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Powon(void)
+{
+    uint32_t tmpVal;
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SD_BUS_POWER);
+    BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);
+}
+/****************************************************************************
+ * @brief  SDH init function
+ *
+ * @param  cfg: SDH config pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Ctrl_Init(const SDH_Cfg_Type *cfg)
+{
+    uint32_t tmpVal;
+
+    SDH_SetSdClock(cfg->srcClock, cfg->busClock);
+    SDH_DisableDMA();
+
+    /* Set SDH config */
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_HOST_CTRL);
+
+    if (cfg->dataWidth == SDH_DATA_BUS_WIDTH_8BITS) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, SDH_EX_DATA_WIDTH);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, SDH_EX_DATA_WIDTH);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DATA_WIDTH, cfg->dataWidth);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_HI_SPEED_EN, cfg->highSpeed);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SD_BUS_VLT, cfg->volt);
+
+    BL_WR_REG16(SDH_BASE, SDH_SD_HOST_CTRL, tmpVal);
+
+    if (cfg->vlot18Enable) {
+        tmpVal = BL_RD_REG16(SDH_BASE, SDH_HOST_CTRL_2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_UHS_MODE_SEL, cfg->speed);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_SDH_V18_EN, cfg->vlot18Enable);
+        BL_WR_REG16(SDH_BASE, SDH_HOST_CTRL_2, tmpVal);
+    }
+
+    tmpVal = BL_RD_REG(SDH_BASE, SDH_TX_CFG_REG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SDH_TX_INT_CLK_SEL);
+    BL_WR_REG(SDH_BASE, SDH_TX_CFG_REG, tmpVal);
+
+    SDH_EnableStatus();
+
+#ifndef BFLB_USE_HAL_DRIVER
+    /*!< use bflb irq */
+    // Interrupt_Handler_Register(SDH_IRQn, SDH_MMC1_IRQHandler);
+#endif
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH deinit function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Deinit(void)
+{
+    SDH_DisableDMA();
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH reset function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Reset(void)
+{
+    uint16_t tmpVal;
+
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, SDH_SW_RST_ALL);
+    BL_WR_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET, tmpVal);
+
+    /* Wait for reset done */
+    do {
+        tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);
+    } while (BL_IS_REG_BIT_SET(tmpVal, SDH_SW_RST_ALL));
+}
+/****************************************************************************/ /**
+ * @brief  SDH set timeout function
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_Set_Timeout(uint8_t tmo)
+{
+    uint16_t tmpVal;
+
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_TIMEOUT_VALUE, tmo);
+    BL_WR_REG16(SDH_BASE, SDH_SD_TIMEOUT_CTRL_SW_RESET, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH get capability
+ *
+ * @param  capability: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_GetCapability(SDH_Cap_Cfg_Type *capability)
+{
+    /* Get the capability  */
+    capability->maxBlockLength = 512;
+    capability->maxBlockCount = 65536;
+    capability->flags = (SDH_CAP_SUPPORT_8BITS |
+                         SDH_CAP_SUPPORT_ADMA2 |
+                         SDH_CAP_SUPPORT_ADMA1 |
+                         SDH_CAP_SUPPORT_HIGHSPEED |
+                         SDH_CAP_SUPPORT_SDMA |
+                         SDH_CAP_SUPPORT_SUS_RES |
+                         SDH_CAP_SUPPORT_VLT33 |
+                         SDH_CAP_SUPPORT_VLT18 |
+                         SDH_CAP_SUPPORT_SBUS_64BITS |
+                         SDH_CAP_SUPPORT_ASYNC_INT |
+                         SDH_CAP_SUPPORT_DDR50 |
+                         SDH_CAP_SUPPORT_SDR104 |
+                         SDH_CAP_SUPPORT_SDR50 |
+                         SDH_CAP_SUPPORT_DRV_TYPE_A |
+                         SDH_CAP_SUPPORT_DRV_TYPE_C |
+                         SDH_CAP_SUPPORT_DRV_TYPE_D |
+                         SDH_CAP_SUPPORT_SDR50_TUNE);
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH create ADMA1 descriptor
+ *
+ * @param  adma1Entries: ADMA1 entries pointer
+ * @param  maxEntries: ADMA1 entries size
+ * @param  data: Data buffer to deal with
+ * @param  dataLen: Data length
+ * @param  flag: ADMA setting flag
+ *
+ * @return SDH deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_CreateADMA1Descriptor(uint32_t *adma1Entries, uint32_t maxEntries,
+                                        const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag)
+{
+    uint32_t miniEntries, startEntries = 0U;
+    uint32_t i, dmaBufferLen = 0U;
+
+    if (((uintptr_t)data % SDH_ADMA1_ADDRESS_ALIGN) != 0U) {
+        return SDH_STAT_DMA_ADDR_NOT_ALIGN;
+    }
+
+    if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
+        return SDH_STAT_NOT_SUPPORT;
+    }
+
+    /* TODO:align */
+    /* Make sure the buffer size is 4 byte aligned */
+    if (dataLen % sizeof(uint32_t) != 0U) {
+        /* make the data length as word-aligned */
+        dataLen += sizeof(uint32_t) - (dataLen % sizeof(uint32_t));
+    }
+
+    /* Check if ADMA descriptor's number is enough. */
+    if ((dataLen % SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) {
+        miniEntries = dataLen / SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+    } else {
+        miniEntries = ((dataLen / SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
+    }
+
+    /* ADMA1 needs two descriptors to finish a transfer */
+    miniEntries <<= 1U;
+
+    if (miniEntries + startEntries > maxEntries) {
+        return SDH_STAT_OUTOF_RANGE;
+    }
+
+    for (i = startEntries; i < (miniEntries + startEntries); i += 2U) {
+        if (dataLen > SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) {
+            dmaBufferLen = SDH_ADMA1_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+        } else {
+            dmaBufferLen = dataLen;
+        }
+
+        adma1Entries[i] = (dmaBufferLen << SDH_ADMA1_DESCRIPTOR_LENGTH_POS);
+        adma1Entries[i] |= SDH_ADMA1_DESC_FLAG_SETLEN;
+        adma1Entries[i + 1U] = (uintptr_t)(data);
+        adma1Entries[i + 1U] |= SDH_ADMA1_DESC_FLAG_TRANSFER;
+        data += (dmaBufferLen / sizeof(uint32_t));
+        dataLen -= dmaBufferLen;
+    }
+
+    /* Set end of the descriptor */
+    adma1Entries[i - 1U] |= SDH_ADMA1_DESC_FLAG_END;
+
+    return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH create ADMA2 descriptor
+ *
+ * @param  adma2Entries: ADMA2 entries pointer
+ * @param  maxEntries: ADMA2 entries size
+ * @param  data: Data buffer to deal with
+ * @param  dataLen: Data length
+ * @param  flag: ADMA setting flag
+ *
+ * @return SDH deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint32_t maxEntries,
+                                        const uint32_t *data, uint32_t dataLen, SDH_ADMA_Flag_Type flag)
+{
+    uint32_t miniEntries, startEntries = 0U;
+    uint32_t i, dmaBufferLen = 0U;
+
+    if (((uintptr_t)data % SDH_ADMA2_ADDRESS_ALIGN) != 0U) {
+        return SDH_STAT_DMA_ADDR_NOT_ALIGN;
+    }
+
+    /* TODO:align */
+    /* Make sure the buffer size is 4 byte aligned */
+    if (dataLen % sizeof(uint32_t) != 0U) {
+        /* make the data length as word-aligned */
+        dataLen += sizeof(uint32_t) - (dataLen % sizeof(uint32_t));
+    }
+
+    /* Check if ADMA descriptor's number is enough. */
+    if ((dataLen % SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) == 0U) {
+        miniEntries = dataLen / SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+    } else {
+        miniEntries = ((dataLen / SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) + 1U);
+    }
+
+    /* Calculate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor
+	data address and data size is enough */
+    if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
+        for (i = 0U; i < maxEntries; i++) {
+            if ((adma2Entries[i].attribute & SDH_ADMA2_DESC_FLAG_VALID) == 0U) {
+                break;
+            }
+        }
+
+        startEntries = i;
+        /* Add one entry for dummy entry */
+        miniEntries += 1U;
+    }
+
+    if (miniEntries + startEntries > maxEntries) {
+        return SDH_STAT_OUTOF_RANGE;
+    }
+
+    for (i = startEntries; i < (miniEntries + startEntries); i++) {
+        if (dataLen > SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY) {
+            dmaBufferLen = SDH_ADMA2_DESCRIPTOR_MAX_LENGTH_PER_ENTRY;
+        } else {
+            /* TODO:align */
+            /* Adma don't support 0 data length transfer descriptor */
+            dmaBufferLen = (dataLen == 0U ? sizeof(uint32_t) : dataLen);
+        }
+
+        /* Each descriptor for ADMA2 is 64-bit in length */
+        adma2Entries[i].address = (dataLen == 0U) ? &bootDummy : data;
+        adma2Entries[i].attribute = (dmaBufferLen << SDH_ADMA2_DESCRIPTOR_LENGTH_POS);
+        adma2Entries[i].attribute |=
+            (dataLen == 0U) ? 0U : (SDH_ADMA2_DESC_FLAG_TRANSFER);
+        //          (dataLen == 0U) ? 0U : (SDH_ADMA2_DESC_FLAG_TRANSFER | SDH_ADMA2_DESC_FLAG_INT);
+        /* TODO:align */
+        data += (dmaBufferLen / sizeof(uint32_t));
+
+        if (dataLen != 0U) {
+            dataLen -= dmaBufferLen;
+        }
+    }
+
+    /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA
+	engine  will not stop at block gap */
+    if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
+        //adma2Entries[startEntries + 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;
+        adma2Entries[i - 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;
+    } else {
+        /* Set the end bit */
+        adma2Entries[i - 1U].attribute |= SDH_ADMA2_DESC_FLAG_END;
+    }
+
+    return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH set DMA config
+ *
+ * @param  dmaCfg: DMA config pointer
+ * @param  data: Data pointer for sending
+ * @param  enAutoCmd23: Whether enable auto command 23
+ *
+ * @return DMA config deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_SetInternalDmaConfig(SDH_DMA_Cfg_Type *dmaCfg, const uint32_t *data, uint8_t enAutoCmd23)
+{
+    uint16_t tmpVal;
+
+    if (dmaCfg->dmaMode == SDH_DMA_MODE_SIMPLE) {
+        /* Check DMA data buffer address align or not */
+        if (((uintptr_t)data % SDH_SDMA_LENGTH_ALIGN) != 0U) {
+            return SDH_STAT_DMA_ADDR_NOT_ALIGN;
+        }
+
+        /* In simple DMA mode if use auto CMD23, address should load to ADMA addr,
+		     and block count should load to DS_ADDR*/
+        if (enAutoCmd23) {
+            BL_WR_REG(SDH_BASE, SDH_SD_ADMA_SYS_ADDR_1, (uintptr_t)data);
+        } else {
+            BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, (uintptr_t)data);
+        }
+    } else {
+        /* When use ADMA, disable simple DMA */
+        BL_WR_REG(SDH_BASE, SDH_SD_SYS_ADDR_LOW, (uint32_t)0);
+        BL_WR_REG(SDH_BASE, SDH_SD_ADMA_SYS_ADDR_1, (uintptr_t)(dmaCfg->admaEntries));
+    }
+
+    /* Select DMA mode and config the burst length */
+    SDH_EnableDMA(dmaCfg->dmaMode);
+
+    /* Set DMA burst size and FIFO threshold */
+    tmpVal = BL_RD_REG16(SDH_BASE, SDH_SD_CLOCK_AND_BURST_SIZE_SETUP);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_DMA_SIZE, dmaCfg->fifoThreshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, SDH_BRST_SIZE, dmaCfg->burstSize);
+    BL_WR_REG16(SDH_BASE, SDH_SD_CLOCK_AND_BURST_SIZE_SETUP, tmpVal);
+
+    return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH create DMA entries according to DMA config
+ *
+ * @param  dmaCfg: DMA config pointer
+ * @param  dataCfg: Data config pointer
+ * @param  flag: ADMA create entries flag
+ *
+ * @return Create entries result
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_CreateAdmaEntryConfig(SDH_DMA_Cfg_Type *dmaCfg, SDH_Data_Cfg_Type *dataCfg, SDH_ADMA_Flag_Type flag)
+{
+    SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+
+    /* TODO:align */
+    uint32_t bootDummyOffset = (dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT ? sizeof(uint32_t) : 0);
+    const uint32_t *data = (const uint32_t *)((dataCfg->rxData == NULL) ? dataCfg->txData : dataCfg->rxData);
+    uint32_t dataLen = dataCfg->blockSize * dataCfg->blockCount;
+
+    data += bootDummyOffset;
+    dataLen -= bootDummyOffset;
+
+    switch (dmaCfg->dmaMode) {
+        case SDH_DMA_MODE_SIMPLE:
+            stat = SDH_STAT_SUCCESS;
+            break;
+
+        case SDH_DMA_MODE_ADMA1:
+            stat = SDH_CreateADMA1Descriptor(dmaCfg->admaEntries, dmaCfg->maxEntries, data, dataLen, flag);
+            break;
+
+        case SDH_DMA_MODE_ADMA2:
+            stat = SDH_CreateADMA2Descriptor((SDH_ADMA2_Desc_Type *)dmaCfg->admaEntries, dmaCfg->maxEntries, data, dataLen, flag);
+            break;
+
+        default:
+            return SDH_STAT_SEND_DATA_FAIL;
+    }
+
+    /* For internal dma, internal DMA configurations should not update the configurations when continous transfer the
+	 * boot data, only the DMA descriptor need update */
+    if ((stat == SDH_STAT_SUCCESS) && (dataCfg->dataType != SDH_TRANS_DATA_BOOT_CONT)) {
+        stat = SDH_SetInternalDmaConfig(dmaCfg, data, dataCfg->enableAutoCommand23);
+    }
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH transfer data in blocking way
+ *
+ * @param  dmaCfg: DMA config pointer
+ * @param  transfer: Transfer config pointer
+ *
+ * @return Transfer deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_TransferBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer)
+{
+    SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+    SDH_CMD_Cfg_Type *cmdCfg = transfer->cmdCfg;
+    SDH_Data_Cfg_Type *dataCfg = transfer->dataCfg;
+    uint32_t intStatus;
+    uint8_t enDMA = 1;
+    uint8_t executeTuning = ((dataCfg == NULL) ? 0 : dataCfg->dataType == SDH_TRANS_DATA_TUNING);
+    //volatile uint32_t tmp;
+    /* Check re-tuning request */
+    intStatus = SDH_GetIntStatus();
+
+    if ((intStatus & SDH_INT_RETUNE_EVENT) != 0U) {
+        SDH_ClearIntStatus(SDH_INT_RETUNE_EVENT);
+        return SDH_STAT_RETUNE_REQ;
+    }
+
+    /* Update ADMA descriptor table according to different DMA mode(simple DMA, ADMA1, ADMA2).*/
+    if ((dataCfg != NULL) && (dmaCfg != NULL) && (!executeTuning)) {
+        stat = SDH_CreateAdmaEntryConfig(dmaCfg, dataCfg, (dataCfg->dataType & SDH_TRANS_DATA_BOOT) ? SDH_ADMA_FLAG_MULTI_DESC : SDH_ADMA_FLAG_SINGLE_DESC);
+    }
+
+    /* If the DMA desciptor configure fail or not needed , disable it */
+    if ((stat != SDH_STAT_SUCCESS) || (dmaCfg == NULL)) {
+        enDMA = 0;
+        /* Disable DMA, using polling mode in this situation */
+        SDH_DisableDMA();
+    }
+
+    /* Config the data transfer parameter */
+    stat = SDH_ConfigDataTranfer(dataCfg);
+
+    if (SDH_STAT_SUCCESS != stat) {
+        return stat;
+    }
+
+    /* Send command first */
+    if (dataCfg != NULL) {
+        cmdCfg->flag = SDH_TRANS_FLAG_DATA_PRESENT;
+    } else {
+        cmdCfg->flag = 0;
+    }
+
+    SDH_SendCommand(cmdCfg);
+
+    /* Wait command done */
+    if ((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL)) {
+        stat = SDH_WaitCommandDone(cmdCfg);
+    }
+
+    /*
+	tmp = BL_RD_REG16(SDH_BASE,SDH_SD_ADMA_ERROR_STATUS);
+	bflb_platform_printf("SDH_SD_ADMA_ERROR_STATUS->0x%x!\r\n",tmp);
+	tmp = BL_RD_REG16(SDH_BASE,SDH_SD_AUTO_CMD12_ERROR_STATUS);
+	*/
+
+    /* Wait for transferring data finish */
+    if ((dataCfg != NULL) && (stat == SDH_STAT_SUCCESS)) {
+        stat = SDH_TransferDataBlocking(dataCfg, enDMA);
+    }
+
+    return stat;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH transfer data in blocking way
+ *
+ * @param  handle: SDH handler
+ * @param  dmaCfg: DMA config pointer
+ * @param  transfer: Transfer config pointer
+ *
+ * @return Transfer deal status
+ *
+*******************************************************************************/
+SDH_Stat_Type SDH_TransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type *transfer)
+{
+    SDH_Stat_Type stat = SDH_STAT_SUCCESS;
+    SDH_CMD_Cfg_Type *cmdCfg = transfer->cmdCfg;
+    SDH_Data_Cfg_Type *dataCfg = transfer->dataCfg;
+    uint32_t intStatus;
+    uint8_t executeTuning = ((dataCfg == NULL) ? 0 : dataCfg->dataType == SDH_TRANS_DATA_TUNING);
+
+    /* Check re-tuning request */
+    intStatus = SDH_GetIntStatus();
+
+    if ((intStatus & SDH_INT_RETUNE_EVENT) != 0U) {
+        SDH_ClearIntStatus(SDH_INT_RETUNE_EVENT);
+        return SDH_STAT_RETUNE_REQ;
+    }
+
+    /* Update ADMA descriptor table according to different DMA mode(simple DMA, ADMA1, ADMA2).*/
+    if ((dataCfg != NULL) && (dmaCfg != NULL) && (!executeTuning)) {
+        stat = SDH_CreateAdmaEntryConfig(dmaCfg, dataCfg, (dataCfg->dataType & SDH_TRANS_DATA_BOOT) ? SDH_ADMA_FLAG_MULTI_DESC : SDH_ADMA_FLAG_SINGLE_DESC);
+    }
+
+    /* If the DMA desciptor configure fail or not needed , disable it */
+    if (stat != SDH_STAT_SUCCESS) {
+        /* Disable DMA, using polling mode in this situation */
+        //SDH_DisableDMA();
+        return stat;
+    }
+
+    /* Config the data transfer parameter */
+    stat = SDH_ConfigDataTranfer(dataCfg);
+
+    if (SDH_STAT_SUCCESS != stat) {
+        return stat;
+    }
+
+    /* Send command first */
+    if (dataCfg != NULL) {
+        cmdCfg->flag |= SDH_TRANS_FLAG_DATA_PRESENT;
+    }
+
+#if 0
+	SDH_SendCommand(cmdCfg);
+
+
+	/* Wait command done */
+	if((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL))
+	{
+		stat = SDH_WaitCommandDone(cmdCfg);
+	}
+
+#endif
+
+    return SDH_STAT_SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH install callback function for handler
+ *
+ * @param  handle: SDH handler
+ * @param  callBack: SDH callBack function
+ * @param  userData: User private data for SDH handler
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle,
+                               const SDH_Trans_Callback_Cfg_Type *callBack, void *userData)
+{
+    /* Zero the handle. */
+    ARCH_MemSet(handle, 0, sizeof(SDH_Handle_Cfg_Type));
+
+    /* Set the callback. */
+    handle->callBack.SDH_CallBack_CardInserted = callBack->SDH_CallBack_CardInserted;
+    handle->callBack.SDH_CallBack_CardRemoved = callBack->SDH_CallBack_CardRemoved;
+    handle->callBack.SDH_CallBack_SdioInterrupt = callBack->SDH_CallBack_SdioInterrupt;
+    handle->callBack.SDH_CallBack_BlockGap = callBack->SDH_CallBack_BlockGap;
+    handle->callBack.SDH_CallBack_TransferFinished = callBack->SDH_CallBack_TransferFinished;
+    handle->callBack.SDH_CMDCallBack_TransferFinished = callBack->SDH_CMDCallBack_TransferFinished;
+    handle->callBack.SDH_CallBack_ReTuning = callBack->SDH_CallBack_ReTuning;
+    handle->callBack.SDH_CallBack_Vendor = callBack->SDH_CallBack_ReTuning;
+    handle->userData = userData;
+
+    /* Save the handle in global variables  */
+    sdhHandle = handle;
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH interrupt handle
+ *
+ * @param  intPeriph: Select the peripheral
+ * @param  handle: SDH handler
+ *
+ * @return None
+ *
+*******************************************************************************/
+static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
+{
+    uint32_t intFlag, intMask;
+
+    intFlag = SDH_GetIntStatus();
+    intMask = SDH_GetIntEnableStatus();
+    intFlag &= intMask;
+
+    if (NULL == handle) {
+        SDH_ClearIntStatus(intFlag);
+        return;
+    }
+
+    handle->intFlag = intFlag;
+
+    /* Card insert interrupt */
+    if (intFlag & SDH_INT_CARD_INSERT) {
+        if (NULL != handle->callBack.SDH_CallBack_CardInserted) {
+            handle->callBack.SDH_CallBack_CardInserted(handle->userData);
+        }
+    }
+
+    /* Card remove interrupt */
+    if (intFlag & SDH_INT_CARD_REMOVE) {
+        if (NULL != handle->callBack.SDH_CallBack_CardRemoved) {
+            handle->callBack.SDH_CallBack_CardRemoved(handle->userData);
+        }
+    }
+
+    /* Command error interrupt */
+    if (intFlag & (SDH_INT_CMD_ERRORS)) {
+        if (NULL != handle->callBack.SDH_CMDCallBack_TransferFinished) {
+            handle->callBack.SDH_CMDCallBack_TransferFinished(handle, SDH_STAT_SEND_CMD_FAIL, handle->userData);
+        }
+    }
+
+    /* Command success interrupt */
+    if (intFlag & SDH_INT_CMD_COMPLETED) {
+        if (NULL != handle->callBack.SDH_CMDCallBack_TransferFinished &&
+            NULL == handle->dataCfg) {
+            /* Only deal with pure command, user need check response to make sure in SDH_CallBack_TransferFinished */
+            handle->callBack.SDH_CMDCallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);
+        }
+    }
+
+    /* Data error interrupt */
+    if (intFlag & (SDH_INT_DATA_ERRORS | SDH_INT_DMA_ERROR)) {
+        if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+            handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SEND_DATA_FAIL, handle->userData);
+        }
+    }
+
+    /* Data success interrupt*/
+    if (intFlag & SDH_INT_DATA_COMPLETED) {
+        if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+            handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);
+        }
+    }
+
+    /* Card interrupt */
+    if (intFlag & SDH_INT_CARD) {
+        if (handle->callBack.SDH_CallBack_SdioInterrupt) {
+            handle->callBack.SDH_CallBack_SdioInterrupt(handle->userData);
+        }
+    }
+
+    /* Buffer read ready interrupt*/
+    if (intFlag & SDH_INT_BUFFER_READ_READY) {
+        if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+            handle->callBack.SDH_CallBack_TransferFinished(handle, SDH_STAT_SUCCESS, handle->userData);
+        } else {
+            handle->dataCfg->rxDataLen += SDH_ReadDataPort(handle->dataCfg);
+        }
+    }
+
+    /* Buffer write ready interrupt */
+    if (intFlag & SDH_INT_BUFFER_WRITE_READY) {
+        if (NULL != handle->callBack.SDH_CallBack_TransferFinished) {
+            handle->dataCfg->txDataLen += SDH_WriteDataPort(handle->dataCfg);
+        }
+    }
+
+    /* DMA success interrupt*/
+    if (intFlag & SDH_INT_DMA_COMPLETED) {
+        if (handle->dataCfg->dataType == SDH_TRANS_DATA_BOOT_CONT) {
+            *(handle->dataCfg->rxData) = bootDummy;
+        }
+    }
+
+    /* Block gap event interrupt */
+    if (intFlag & SDH_INT_BLK_GAP_EVENT) {
+        if (handle->callBack.SDH_CallBack_BlockGap) {
+            handle->callBack.SDH_CallBack_BlockGap(handle->userData);
+        }
+    }
+
+    /* Re-tuning event interrupt */
+    if (intFlag & SDH_INT_RETUNE_EVENT) {
+        if (handle->callBack.SDH_CallBack_ReTuning) {
+            handle->callBack.SDH_CallBack_ReTuning(handle->userData);
+        }
+    }
+
+    /* Vendor specified interrupt */
+    if (intFlag & (SDH_INT_SPI_ERROR |
+                   SDH_INT_AXI_RESP_ERROR |
+                   SDH_INT_CPL_TIMEOUT_ERROR |
+                   SDH_INT_CRC_STAT_ERROR)) {
+        if (handle->callBack.SDH_CallBack_Vendor) {
+            handle->callBack.SDH_CallBack_Vendor(handle->userData);
+        }
+    }
+
+    SDH_ClearIntStatus(intFlag);
+}
+
+/****************************************************************************/ /**
+ * @brief  SDH interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void SDH_MMC1_IRQHandler(void)
+{
+    SDH_IntHandler(SDH_IRQn, sdhHandle);
+}
+
+/*@} end of group SDH_Public_Functions */
+
+/*@} end of group SDH */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdu.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdu.c
new file mode 100755
index 0000000000..b61414d334
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_sdu.c
@@ -0,0 +1,76 @@
+#include "bl616_sdu.h"
+
+volatile pHidSdio_RegMap_t SdioFuncReg[] =
+{
+    (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE),
+#if NUM_FUNC == 2
+    (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE+BL_SDIO_CCR_FUNC_OFFSET)
+#elif NUM_FUNC == 3
+    (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE+BL_SDIO_CCR_FUNC_OFFSET),
+    (pHidSdio_RegMap_t)(BL_SDIO_CCR_BASE+(2 * BL_SDIO_CCR_FUNC_OFFSET))
+#endif
+};
+
+/* if flag_mport = 0, then it supports mport
+ *    flag_mport = 1, then mport disabled
+ */
+uint8_t flag_mport[NUM_FUNC] = 
+{
+    0,
+#if NUM_FUNC == 2
+    1
+#elif NUM_FUNC == 3
+    1,1
+#endif
+};
+
+void sdio_GEN_CARD2HOST_INT(uint32_t port_id, uint16_t value)
+{
+    /* We do not want to generate Download rdy for command port
+     * only. Currently there is a condition where if we generate
+     * download ready for command, followed by a download
+     * ready for data, the download ready for data would be gated
+     * by the SDIO controller. To avoid this we do not generate
+     * a download ready for command. Download ready is only generated for data.
+     */
+    /*
+    if (!flag_mport[port_id] &&
+        (value & SDIO_CCR_CS_DnLdRdy) && (prev_WrBitMap[port_id] == 0x01))
+    {
+        value &= ~SDIO_CCR_CS_DnLdRdy;
+        if (!value)
+        {
+            return;
+        }
+    }
+    */
+    SdioFuncReg[port_id]->CardToHostEvent = value;
+}
+
+
+uint32_t sdio_ioctl(uint32_t port_id, SDIO_CMD_TYPE cmd, void *arg)
+{
+    switch(cmd)
+    {
+    case IOCTL_HID_GET_BLOCK_SIZE:
+	{
+        if (port_id == FUNC_WIFI)
+        {
+            uint32_t blockSize = BL_REGS8(SDIO_FN1_BLK_SIZE_0);
+
+            blockSize |= ((BL_REGS8(SDIO_FN1_BLK_SIZE_1) & 
+                           SDIO_FN1_BLK_SIZE_1_MASK ) << 8);
+
+            if(blockSize == 0)
+            {
+                blockSize = 512;
+            }
+            return(blockSize);
+        }
+        break;
+	}
+    default:
+        break;
+    }
+    return 0;
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_tzc_sec.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_tzc_sec.c
new file mode 100755
index 0000000000..f9af22cc60
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/src/bl616_tzc_sec.c
@@ -0,0 +1,826 @@
+/**
+  ******************************************************************************
+  * @file    bl616_tzc_sec.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "string.h"
+#include "bl616_tzc_sec.h"
+#include "bl616_glb.h"
+
+/** @addtogroup  BL616_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  TZC_ENG
+ *  @{
+ */
+
+/** @defgroup  TZC_ENG_Private_Macros
+ *  @{
+ */
+
+/*@} end of group TZC_ENG_Private_Macros */
+
+/** @defgroup  TZC_ENG_Private_Types
+ *  @{
+ */
+
+/*@} end of group TZC_ENG_Private_Types */
+
+/** @defgroup  TZC_ENG_Private_Variables
+ *  @{
+ */
+
+/*@} end of group TZC_ENG_Private_Variables */
+
+/** @defgroup  TZC_ENG_Global_Variables
+ *  @{
+ */
+
+/*@} end of group TZC_ENG_Global_Variables */
+
+/** @defgroup  TZC_ENG_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group TZC_ENG_Private_Fun_Declaration */
+
+/** @defgroup  TZC_ENG_Private_Functions
+ *  @{
+ */
+
+/*@} end of group TZC_ENG_Private_Functions */
+
+/** @defgroup  TZC_ENG_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  None
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_Sboot_Done(void)
+{
+    uint32_t tmpVal;
+    /* Set Sboot done */
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SBOOT_DONE, 0xf);
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+}
+
+void Tzc_Sec_Set_Bus_Remap(uint8_t busRmpEn)
+{
+    uint32_t tmpVal;
+
+    /* Set bus remap */
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    if (busRmpEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, TZC_SEC_TZC_BUS_RMP_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, TZC_SEC_TZC_BUS_RMP_EN);
+    }
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+
+    /* Set Lock */
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, TZC_SEC_TZC_BUS_RMP_EN_LOCK);
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+}
+
+void Tzc_Sec_Set_Master_Group(TZC_SEC_Master_Type masterType, uint8_t group)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
+    tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
+
+    if (group == 0) {
+        tmpVal &= (~(1 << masterType));
+    } else {
+        tmpVal |= (1 << masterType);
+    }
+    tmpVal |= (1 << (masterType + 16));
+    tmpVal2 |= (1 << masterType);
+
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
+}
+
+void Tzc_Sec_Set_Slave_Group(TZC_SEC_Slave_Type slaveType, uint8_t group)
+{
+    uint32_t tmpVal;
+
+    if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SLAVE_MAX) {
+        return;
+    }
+    group = 1 << (group);
+
+    if (slaveType < TZC_SEC_SLAVE_S1_GLB) {
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0);
+        /* set group */
+        tmpVal &= (~(3 << (slaveType * 2)));
+        tmpVal |= (group << (slaveType * 2));
+        /* set lock*/
+        tmpVal |= (1 << (slaveType + 16));
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S0, tmpVal);
+    } else if ((slaveType >= TZC_SEC_SLAVE_S1_GLB) && (slaveType < TZC_SEC_SLAVE_S2_EMI_MISC)) {
+        slaveType -= TZC_SEC_SLAVE_S1_GLB;
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1);
+        /* set group */
+        tmpVal &= (~(3 << (slaveType * 2)));
+        tmpVal |= (group << (slaveType * 2));
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1, tmpVal);
+
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);
+        /* set lock */
+        tmpVal |= (1 << slaveType);
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);
+    } else if ((slaveType >= TZC_SEC_SLAVE_S2_EMI_MISC) && (slaveType < TZC_SEC_SLAVE_S1A_UART0)) {
+        slaveType -= TZC_SEC_SLAVE_S2_EMI_MISC;
+
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2);
+        /* set group */
+        tmpVal &= (~(3 << (slaveType * 2)));
+        tmpVal |= (group << (slaveType * 2));
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S2, tmpVal);
+
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK);
+        /* set lock */
+        tmpVal |= (1 << (slaveType + (TZC_SEC_SLAVE_S2_EMI_MISC - TZC_SEC_SLAVE_S1_GLB)));
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S_LOCK, tmpVal);
+    } else {
+        slaveType -= TZC_SEC_SLAVE_S1A_UART0;
+
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1A);
+        /* set group */
+        tmpVal &= (~(3 << (slaveType * 2)));
+        tmpVal |= (group << (slaveType * 2));
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1A, tmpVal);
+
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1A_LOCK);
+        /* set lock */
+        tmpVal |= (1 << slaveType);
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_S1A_LOCK, tmpVal);
+    }
+}
+
+void Tzc_Sec_Set_Codec_Group(uint8_t group)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID);
+    tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK);
+
+    if (group == 0) {
+        tmpVal &= (~(1 << 2));
+    } else {
+        tmpVal |= (1 << 2);
+    }
+    tmpVal |= (1 << (2 + 16));
+    tmpVal2 |= (1 << 2);
+
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID, tmpVal);
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_TZMID_LOCK, tmpVal2);
+}
+
+void Tzc_Sec_Set_Glb_Ctrl_Group(TZC_SEC_GLB_Ctrl_Type slaveType, uint8_t group)
+{
+    uint32_t tmpVal;
+
+    if (slaveType >= TZC_SEC_GLB_CTRL_MAX || group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0);
+    /* set group */
+    tmpVal &= (~(3 << (slaveType * 2)));
+    tmpVal |= (group << (slaveType * 2));
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_0, tmpVal);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2);
+    /* set lock */
+    tmpVal |= (1 << slaveType);
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_GLB_CTRL_2, tmpVal);
+}
+
+void Tzc_Sec_Set_CPU_Group(uint8_t cpu, uint8_t group)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    if (cpu == GLB_CORE_ID_M0) {
+        tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID);
+        tmpVal2 = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK);
+
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_CPU_TZMID, group);
+        tmpVal2 = BL_SET_REG_BITS_VAL(tmpVal2, TZC_SEC_TZC_CPU_TZMID_LOCK, 1);
+
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID, tmpVal);
+        BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_BMX_TZMID_LOCK, tmpVal2);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set ROM region access configuration
+ *
+ * @param  region: ROM region index 0-2
+ * @param  startAddr: ROM region start address
+ * @param  length: ROM region end length
+ * @param  group: ROM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_ROM_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 24);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set ROM region access configuration
+ *
+ * @param  region: ROM region index 0-2
+ * @param  startAddr: ROM region start address
+ * @param  length: ROM region end length
+ * @param  group: ROM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_ROM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3) {
+        return;
+    }
+    group = group & 0xf;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 24);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set OCRAM region access configuration
+ *
+ * @param  region: OCRAM region index 0-2
+ * @param  startAddr: OCRAM region start address
+ * @param  length: OCRAM region end length
+ * @param  group: OCRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_OCRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3) {
+        return;
+    }
+    group = group & 0xf;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_OCRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 20);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set OCRAM regionx access configuration
+ *
+ * @param  group: OCRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_OCRAM_Access_Set_Regionx(uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint8_t region = 3;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 20);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_OCRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set WRAM region access configuration
+ *
+ * @param  region: WRAM region index 0-2
+ * @param  startAddr: WRAM region start address
+ * @param  length: WRAM region end length
+ * @param  group: WRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_WRAM_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3) {
+        return;
+    }
+    group = group & 0xf;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_WRAM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 20);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set WRAM regionx access configuration
+ *
+ * @param  group: WRAM region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_WRAM_Access_Set_Regionx(uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint8_t region = 3;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 20);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_WRAM_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set HBNRAM region access configuration
+ *
+ * @param  startAddr: HBNRAM region start address
+ * @param  length: HBNRAM region end length
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_HBNRAM_Access_Set(uint32_t startAddr, uint32_t length)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 3) & ~0x3;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_TZC_HBNRAM_R0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_START, ((startAddr >> 2) & 0xffff));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_END, (((alignEnd >> 2) & 0xffff) - 1));
+    BL_WR_REG(AON_BASE, AON_TZC_HBNRAM_R0, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(AON_BASE, AON_TZC_HBNRAM_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_TZC_HBNRAM_R0_LOCK, 1);
+    BL_WR_REG(AON_BASE, AON_TZC_HBNRAM_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set Flash region access configuration
+ *
+ * @param  region: Flash region index 0-2
+ * @param  startAddr: Flash region start address
+ * @param  length: Flash region end length
+ * @param  group: Flash region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Flash_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t tmpVal2 = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+
+    /* Set range */
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* Set range MSB */
+    tmpVal = BL_RD_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET);
+    tmpVal = tmpVal & (0xff << (8 * region));
+    tmpVal2 = ((alignEnd >> 26) & 0x7) | (((startAddr >> 26) & 0x7) << 3);
+    tmpVal2 = tmpVal2 << (8 * region);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET, tmpVal | tmpVal2);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 20);
+    tmpVal |= 1 << (region + 25);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set Flash regionx access configuration
+ *
+ * @param  group: Flash region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Flash_Access_Set_Regionx(uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint8_t region = 4;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 20);
+    tmpVal |= 1 << (region + 25);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set Flash region access advance configuration
+ *
+ * @param  region: Flash region index 0-2
+ * @param  startAddr: Flash region start address
+ * @param  length: Flash region end length
+ * @param  group: Flash region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Flash_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t tmpVal2 = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3) {
+        return;
+    }
+    group = group & 0xf;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+
+    /* Set range */
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* Set range MSB */
+    tmpVal = BL_RD_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET);
+    tmpVal = tmpVal & (0xff << (8 * region));
+    tmpVal2 = ((alignEnd >> 26) & 0x7) | (((startAddr >> 26) & 0x7) << 3);
+    tmpVal2 = tmpVal2 << (8 * region);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_SF_TZSRG_MSB_OFFSET, tmpVal | tmpVal2);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 20);
+    tmpVal |= 1 << (region + 25);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SF_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set PSRAMB region access configuration
+ *
+ * @param  region: PSRAMB region index 0-2
+ * @param  startAddr: PSRAMB region start address
+ * @param  length: PSRAMB region end length
+ * @param  group: PSRAMB region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_PSRAMB_Access_Set(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 24);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+}
+
+/**
+ * @brief TrustZone Security set Release PSRAMB region access
+ *
+ */
+void Tzc_Sec_PSRAMB_Access_Release(void)
+{
+    uint32_t tmpVal = 0;
+    uint32_t region = 0;
+    /* set disable */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+    tmpVal &= (~(1 << (region + 16)));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set PSRAMB region access configuration
+ *
+ * @param  region: PSRAMB region index 0-2
+ * @param  startAddr: PSRAMB region start address
+ * @param  length: PSRAMB region end length
+ * @param  group: PSRAMB region auth group type
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_PSRAMB_Access_Set_Advance(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    CHECK_PARAM(IS_TZC_SEC_GROUP_TYPE(group));
+    if (region >= 3 || group > TZC_SEC_MAX_AUTH_GRP) {
+        return;
+    }
+    group = 0xf & group;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    tmpVal |= 1 << (region + 24);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set sec_eng module config
+ *
+ * @param  mode: sec_eng control mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_Se_Ctrl_Mode(TZC_SEC_SE_Ctrl_Mode mode)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD, mode);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+    /* set lock */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_TZSID_CRMD_LOCK, 1);
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set sf_ctrl module config
+ *
+ * @param  mode: sf_ctrl control mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_Sf_Ctrl_Mode(TZC_SEC_SF_Ctrl_Mode mode)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD, mode);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+    /* set lock */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SF_TZSID_CRMD_LOCK, 1);
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+void Tzc_Sec_Set_Se_Group(TZC_SEC_SE_Ctrl_Type slaveType, uint8_t group)
+{
+    uint32_t tmpVal;
+
+    if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SE_CTRL_MAX) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0);
+    /* set group */
+    tmpVal &= (~(3 << (slaveType * 2)));
+    tmpVal |= (group << (slaveType * 2));
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+    /* set lock */
+    tmpVal |= (1 << (slaveType));
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+void Tzc_Sec_Set_Sf_Group(TZC_SEC_SF_Ctrl_Type slaveType, uint8_t group)
+{
+    uint32_t tmpVal;
+
+    if (group > TZC_SEC_MAX_AUTH_GRP || slaveType >= TZC_SEC_SF_CTRL_MAX) {
+        return;
+    }
+    group = 1 << (group);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1);
+    /* set group */
+    tmpVal &= (~(3 << (slaveType * 2)));
+    tmpVal |= (group << (slaveType * 2));
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_1, tmpVal);
+
+    tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2);
+    /* set lock */
+    tmpVal |= (1 << (slaveType + 16));
+    BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_SE_CTRL_2, tmpVal);
+}
+
+/****************************************************************************/ /**
+ * @brief  TrustZone Security set watchdog reset delay value
+ *
+ * @param  mode: sec_eng control mode
+ *
+ * @return None
+ *
+*******************************************************************************/
+void Tzc_Sec_Set_WTD_Rst_Delay(uint16_t delayValue)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, TZC_SEC_TZC_SE_WDT_DLY, delayValue);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_SE_CTRL_0, tmpVal);
+}
+
+/*@} end of group TZC_ENG_Public_Functions */
+
+/*@} end of group TZC_ENG */
+
+/*@} end of group BL616_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/interrupt.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/interrupt.c
new file mode 100755
index 0000000000..b48bed4759
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/interrupt.c
@@ -0,0 +1,185 @@
+/**
+ * @file interrupt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bflb_core.h"
+#include 
+#include "irq_ctx.h"
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
+
+extern void default_trap_handler(void);
+extern void default_interrupt_handler(void);
+
+const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*  3: M-mode Soft IRQ   */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*  7: M-mode Timer IRQ  */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+
+    default_interrupt_handler, //BMX_ERR_IRQHandler_Wrapper,              /* 16 +  0 */
+    default_interrupt_handler, //BMX_TO_IRQHandler_Wrapper,               /* 16 +  1 */
+    default_interrupt_handler, //L1C_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  2 */
+    default_interrupt_handler, //L1C_BMX_TO_IRQHandler_Wrapper,           /* 16 +  3 */
+    default_interrupt_handler, //SEC_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  4 */
+    default_interrupt_handler, //RF_TOP_INT0_IRQHandler_Wrapper,          /* 16 +  5 */
+    default_interrupt_handler, //RF_TOP_INT1_IRQHandler_Wrapper,          /* 16 +  6 */
+    default_interrupt_handler, //SDIO_IRQHandler_Wrapper,                 /* 16 +  7 */
+    default_interrupt_handler, //DMA_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  8 */
+    default_interrupt_handler, //SEC_GMAC_IRQHandler_Wrapper,             /* 16 +  9 */
+    default_interrupt_handler, //SEC_CDET_IRQHandler_Wrapper,             /* 16 + 10 */
+    default_interrupt_handler, //SEC_PKA_IRQHandler_Wrapper,              /* 16 + 11 */
+    default_interrupt_handler, //SEC_TRNG_IRQHandler_Wrapper,             /* 16 + 12 */
+    default_interrupt_handler, //SEC_AES_IRQHandler_Wrapper,              /* 16 + 13 */
+    default_interrupt_handler, //SEC_SHA_IRQHandler_Wrapper,              /* 16 + 14 */
+    default_interrupt_handler, //DMA_ALL_IRQHandler_Wrapper,              /* 16 + 15 */
+    default_interrupt_handler, //0,                                       /* 16 + 16 */
+    default_interrupt_handler, //0,                                       /* 16 + 17 */
+    default_interrupt_handler, //0,                                       /* 16 + 18 */
+    default_interrupt_handler, //IRTX_IRQHandler_Wrapper,                 /* 16 + 19 */
+    default_interrupt_handler, //IRRX_IRQHandler_Wrapper,                 /* 16 + 20 */
+    default_interrupt_handler, //0,                                       /* 16 + 21 */
+    default_interrupt_handler, //0,                                       /* 16 + 22 */
+    default_interrupt_handler, //SF_CTRL_IRQHandler_Wrapper,              /* 16 + 23 */
+    default_interrupt_handler, //0,                                       /* 16 + 24 */
+    default_interrupt_handler, //GPADC_DMA_IRQHandler_Wrapper,            /* 16 + 25 */
+    default_interrupt_handler, //EFUSE_IRQHandler_Wrapper,                /* 16 + 26 */
+    default_interrupt_handler, //SPI_IRQHandler_Wrapper,                  /* 16 + 27 */
+    default_interrupt_handler, //0,                                       /* 16 + 28 */
+    default_interrupt_handler, //UART0_IRQHandler_Wrapper,                /* 16 + 29 */
+    default_interrupt_handler, //UART1_IRQHandler_Wrapper,                /* 16 + 30 */
+    default_interrupt_handler, //0,                                       /* 16 + 31 */
+    default_interrupt_handler, //I2C_IRQHandler_Wrapper,                  /* 16 + 32 */
+    default_interrupt_handler, //0,                                       /* 16 + 33 */
+    default_interrupt_handler, //PWM_IRQHandler_Wrapper,                  /* 16 + 34 */
+    default_interrupt_handler, //0,                                       /* 16 + 35 */
+    default_interrupt_handler, //TIMER_CH0_IRQHandler_Wrapper,            /* 16 + 36 */
+    default_interrupt_handler, //TIMER_CH1_IRQHandler_Wrapper,            /* 16 + 37 */
+    default_interrupt_handler, //TIMER_WDT_IRQHandler_Wrapper,            /* 16 + 38 */
+    default_interrupt_handler, //0,                                       /* 16 + 39 */
+    default_interrupt_handler, //0,                                       /* 16 + 40 */
+    default_interrupt_handler, //0,                                       /* 16 + 41 */
+    default_interrupt_handler, //0,                                       /* 16 + 42 */
+    default_interrupt_handler, //0,                                       /* 16 + 43 */
+    default_interrupt_handler, //GPIO_INT0_IRQHandler_Wrapper,            /* 16 + 44 */
+    default_interrupt_handler, //0,                                       /* 16 + 45 */
+    default_interrupt_handler, //0,                                       /* 16 + 46 */
+    default_interrupt_handler, //0,                                       /* 16 + 47 */
+    default_interrupt_handler, //0,                                       /* 16 + 48 */
+    default_interrupt_handler, //0,                                       /* 16 + 49 */
+    default_interrupt_handler, //PDS_WAKEUP_IRQHandler_Wrapper,           /* 16 + 50 */
+    default_interrupt_handler, //HBN_OUT0_IRQHandler_Wrapper,             /* 16 + 51 */
+    default_interrupt_handler, //HBN_OUT1_IRQHandler_Wrapper,             /* 16 + 52 */
+    default_interrupt_handler, //BOR_IRQHandler_Wrapper,                  /* 16 + 53 */
+    default_interrupt_handler, //WIFI_IRQHandler_Wrapper,                 /* 16 + 54 */
+    default_interrupt_handler, //BZ_PHY_IRQHandler_Wrapper,               /* 16 + 55 */
+    default_interrupt_handler, //BLE_IRQHandler_Wrapper,                  /* 16 + 56 */
+    default_interrupt_handler, //MAC_TXRX_TIMER_IRQHandler_Wrapper,       /* 16 + 57 */
+    default_interrupt_handler, //MAC_TXRX_MISC_IRQHandler_Wrapper,        /* 16 + 58 */
+    default_interrupt_handler, //MAC_RX_TRG_IRQHandler_Wrapper,           /* 16 + 59 */
+    default_interrupt_handler, //MAC_TX_TRG_IRQHandler_Wrapper,           /* 16 + 60 */
+    default_interrupt_handler, //MAC_GEN_IRQHandler_Wrapper,              /* 16 + 61 */
+    default_interrupt_handler, //MAC_PORT_TRG_IRQHandler_Wrapper,         /* 16 + 62 */
+    default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper,      /* 16 + 63 */
+};
+
+void exception_entry(uintptr_t *regs)
+{
+    unsigned long cause;
+    unsigned long epc;
+    unsigned long tval;
+
+    printf("exception_entry\r\n");
+
+    cause = READ_CSR(CSR_MCAUSE);
+    printf("mcause=%08x\r\n", (int)cause);
+    epc = READ_CSR(CSR_MEPC);
+    printf("mepc:%08x\r\n", (int)epc);
+    tval = READ_CSR(CSR_MTVAL);
+    printf("mtval:%08x\r\n", (int)tval);
+
+    cause = (cause & 0x3ff);
+
+#ifndef CONFIG_TRAP_DUMP_DISABLE
+    const char *mcause_str[] = {
+        "Instruction address misaligned",
+        "Instruction access fault",
+        "Illegal instruction",
+        "Breakpoint",
+        "Load address misaligned",
+        "Load access fault",
+        "Store/AMO address misaligned",
+        "Store/AMO access fault",
+        "Environment call from U-mode",
+        "Environment call from S-mode",
+        "RSVD",
+        "Environment call from M-mode",
+        "Instruction page fault",
+        "Load page fault",
+        "RSVD",
+        "Store/AMO page fault"
+    };
+
+    printf("%s\r\n", mcause_str[cause & 0xf]);
+#endif
+    if ((cause == 8) || (cause == 11)) {
+        epc += 4;
+        WRITE_CSR(CSR_MEPC, epc);
+    } else {
+        while (1) {
+        }
+    }
+}
+
+void interrupt_entry(void)
+{
+    irq_callback handler;
+    void *arg;
+    volatile uint32_t mcause = 0UL;
+    uint32_t irq_num;
+
+    mcause = READ_CSR(CSR_MCAUSE);
+    irq_num = mcause & 0x3FF;
+
+    if (irq_num < CONFIG_IRQ_NUM) {
+        handler = g_irqvector[irq_num].handler;
+        arg = g_irqvector[irq_num].arg;
+        if (handler) {
+            handler(irq_num, arg);
+        } else {
+        }
+    } else {
+    }
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/irq_ctx.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/irq_ctx.h
new file mode 100755
index 0000000000..24fe032ab2
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/irq_ctx.h
@@ -0,0 +1,378 @@
+#ifndef __IRQ_CTX_H__
+#define __IRQ_CTX_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#if defined(__riscv_flen)
+# define CONFIG_ARCH_FPU
+#else
+# undef CONFIG_ARCH_FPU
+#endif
+
+/* Processor PC */
+
+#define REG_EPC_NDX 0
+
+/* General pupose registers
+ * $0: Zero register does not need to be saved
+ * $1: ra (return address)
+ */
+
+#define REG_X1_NDX 1
+
+/* $2: Stack POinter
+ * $3: Global Pointer
+ * $4: Thread Pointer
+ */
+
+#define REG_X2_NDX 2
+#define REG_X3_NDX 3
+#define REG_X4_NDX 4
+
+/* $5-$7 = t0-t3: Temporary registers */
+
+#define REG_X5_NDX 5
+#define REG_X6_NDX 6
+#define REG_X7_NDX 7
+
+/* $8: s0 / fp Frame pointer */
+
+#define REG_X8_NDX 8
+
+/* $89 s1 Saved register */
+
+#define REG_X9_NDX 9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_X10_NDX 10
+#define REG_X11_NDX 11
+#define REG_X12_NDX 12
+#define REG_X13_NDX 13
+#define REG_X14_NDX 14
+#define REG_X15_NDX 15
+#define REG_X16_NDX 16
+#define REG_X17_NDX 17
+
+/* $18-$27 = s2-s11: Saved registers */
+
+#define REG_X18_NDX 18
+#define REG_X19_NDX 19
+#define REG_X20_NDX 20
+#define REG_X21_NDX 21
+#define REG_X22_NDX 22
+#define REG_X23_NDX 23
+#define REG_X24_NDX 24
+#define REG_X25_NDX 25
+#define REG_X26_NDX 26
+#define REG_X27_NDX 27
+
+/* $28-31 = t3-t6: Temporary (Volatile) registers */
+
+#define REG_X28_NDX 28
+#define REG_X29_NDX 29
+#define REG_X30_NDX 30
+#define REG_X31_NDX 31
+
+/* Interrupt Context register */
+
+#define REG_INT_CTX_NDX 32
+
+#define INT_XCPT_REGS 33
+
+#define INT_XCPT_SIZE (4 * INT_XCPT_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+#define FPU_REG_SIZE 1 /* size in uint32_t */
+
+#define REG_F0_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 0)
+#define REG_F1_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 1)
+#define REG_F2_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 2)
+#define REG_F3_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 3)
+#define REG_F4_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 4)
+#define REG_F5_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 5)
+#define REG_F6_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 6)
+#define REG_F7_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 7)
+#define REG_F8_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 8)
+#define REG_F9_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 9)
+#define REG_F10_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 10)
+#define REG_F11_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 11)
+#define REG_F12_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 12)
+#define REG_F13_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 13)
+#define REG_F14_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 14)
+#define REG_F15_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 15)
+#define REG_F16_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 16)
+#define REG_F17_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 17)
+#define REG_F18_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 18)
+#define REG_F19_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 19)
+#define REG_F20_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 20)
+#define REG_F21_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 21)
+#define REG_F22_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 22)
+#define REG_F23_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 23)
+#define REG_F24_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 24)
+#define REG_F25_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 25)
+#define REG_F26_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 26)
+#define REG_F27_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 27)
+#define REG_F28_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 28)
+#define REG_F29_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 29)
+#define REG_F30_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 30)
+#define REG_F31_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 31)
+#define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32)
+
+#define FPU_XCPT_REGS (FPU_REG_SIZE * 33)
+#else
+#define FPU_XCPT_REGS 0
+#endif
+
+#define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS)
+
+#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
+
+/* In assembly language, values have to be referenced as byte address
+ * offsets.  But in C, it is more convenient to reference registers as
+ * register save table offsets.
+ */
+
+#ifdef __ASSEMBLY__
+#define REG_EPC     (4 * REG_EPC_NDX)
+#define REG_X1      (4 * REG_X1_NDX)
+#define REG_X2      (4 * REG_X2_NDX)
+#define REG_X3      (4 * REG_X3_NDX)
+#define REG_X4      (4 * REG_X4_NDX)
+#define REG_X5      (4 * REG_X5_NDX)
+#define REG_X6      (4 * REG_X6_NDX)
+#define REG_X7      (4 * REG_X7_NDX)
+#define REG_X8      (4 * REG_X8_NDX)
+#define REG_X9      (4 * REG_X9_NDX)
+#define REG_X10     (4 * REG_X10_NDX)
+#define REG_X11     (4 * REG_X11_NDX)
+#define REG_X12     (4 * REG_X12_NDX)
+#define REG_X13     (4 * REG_X13_NDX)
+#define REG_X14     (4 * REG_X14_NDX)
+#define REG_X15     (4 * REG_X15_NDX)
+#define REG_X16     (4 * REG_X16_NDX)
+#define REG_X17     (4 * REG_X17_NDX)
+#define REG_X18     (4 * REG_X18_NDX)
+#define REG_X19     (4 * REG_X19_NDX)
+#define REG_X20     (4 * REG_X20_NDX)
+#define REG_X21     (4 * REG_X21_NDX)
+#define REG_X22     (4 * REG_X22_NDX)
+#define REG_X23     (4 * REG_X23_NDX)
+#define REG_X24     (4 * REG_X24_NDX)
+#define REG_X25     (4 * REG_X25_NDX)
+#define REG_X26     (4 * REG_X26_NDX)
+#define REG_X27     (4 * REG_X27_NDX)
+#define REG_X28     (4 * REG_X28_NDX)
+#define REG_X29     (4 * REG_X29_NDX)
+#define REG_X30     (4 * REG_X30_NDX)
+#define REG_X31     (4 * REG_X31_NDX)
+#define REG_INT_CTX (4 * REG_INT_CTX_NDX)
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0   (4 * REG_F0_NDX)
+#define REG_F1   (4 * REG_F1_NDX)
+#define REG_F2   (4 * REG_F2_NDX)
+#define REG_F3   (4 * REG_F3_NDX)
+#define REG_F4   (4 * REG_F4_NDX)
+#define REG_F5   (4 * REG_F5_NDX)
+#define REG_F6   (4 * REG_F6_NDX)
+#define REG_F7   (4 * REG_F7_NDX)
+#define REG_F8   (4 * REG_F8_NDX)
+#define REG_F9   (4 * REG_F9_NDX)
+#define REG_F10  (4 * REG_F10_NDX)
+#define REG_F11  (4 * REG_F11_NDX)
+#define REG_F12  (4 * REG_F12_NDX)
+#define REG_F13  (4 * REG_F13_NDX)
+#define REG_F14  (4 * REG_F14_NDX)
+#define REG_F15  (4 * REG_F15_NDX)
+#define REG_F16  (4 * REG_F16_NDX)
+#define REG_F17  (4 * REG_F17_NDX)
+#define REG_F18  (4 * REG_F18_NDX)
+#define REG_F19  (4 * REG_F19_NDX)
+#define REG_F20  (4 * REG_F20_NDX)
+#define REG_F21  (4 * REG_F21_NDX)
+#define REG_F22  (4 * REG_F22_NDX)
+#define REG_F23  (4 * REG_F23_NDX)
+#define REG_F24  (4 * REG_F24_NDX)
+#define REG_F25  (4 * REG_F25_NDX)
+#define REG_F26  (4 * REG_F26_NDX)
+#define REG_F27  (4 * REG_F27_NDX)
+#define REG_F28  (4 * REG_F28_NDX)
+#define REG_F29  (4 * REG_F29_NDX)
+#define REG_F30  (4 * REG_F30_NDX)
+#define REG_F31  (4 * REG_F31_NDX)
+#define REG_FCSR (4 * REG_FCSR_NDX)
+#endif
+
+#else
+#define REG_EPC     REG_EPC_NDX
+#define REG_X1      REG_X1_NDX
+#define REG_X2      REG_X2_NDX
+#define REG_X3      REG_X3_NDX
+#define REG_X4      REG_X4_NDX
+#define REG_X5      REG_X5_NDX
+#define REG_X6      REG_X6_NDX
+#define REG_X7      REG_X7_NDX
+#define REG_X8      REG_X8_NDX
+#define REG_X9      REG_X9_NDX
+#define REG_X10     REG_X10_NDX
+#define REG_X11     REG_X11_NDX
+#define REG_X12     REG_X12_NDX
+#define REG_X13     REG_X13_NDX
+#define REG_X14     REG_X14_NDX
+#define REG_X15     REG_X15_NDX
+#define REG_X16     REG_X16_NDX
+#define REG_X17     REG_X17_NDX
+#define REG_X18     REG_X18_NDX
+#define REG_X19     REG_X19_NDX
+#define REG_X20     REG_X20_NDX
+#define REG_X21     REG_X21_NDX
+#define REG_X22     REG_X22_NDX
+#define REG_X23     REG_X23_NDX
+#define REG_X24     REG_X24_NDX
+#define REG_X25     REG_X25_NDX
+#define REG_X26     REG_X26_NDX
+#define REG_X27     REG_X27_NDX
+#define REG_X28     REG_X28_NDX
+#define REG_X29     REG_X29_NDX
+#define REG_X30     REG_X30_NDX
+#define REG_X31     REG_X31_NDX
+#define REG_INT_CTX REG_INT_CTX_NDX
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0   REG_F0_NDX
+#define REG_F1   REG_F1_NDX
+#define REG_F2   REG_F2_NDX
+#define REG_F3   REG_F3_NDX
+#define REG_F4   REG_F4_NDX
+#define REG_F5   REG_F5_NDX
+#define REG_F6   REG_F6_NDX
+#define REG_F7   REG_F7_NDX
+#define REG_F8   REG_F8_NDX
+#define REG_F9   REG_F9_NDX
+#define REG_F10  REG_F10_NDX
+#define REG_F11  REG_F11_NDX
+#define REG_F12  REG_F12_NDX
+#define REG_F13  REG_F13_NDX
+#define REG_F14  REG_F14_NDX
+#define REG_F15  REG_F15_NDX
+#define REG_F16  REG_F16_NDX
+#define REG_F17  REG_F17_NDX
+#define REG_F18  REG_F18_NDX
+#define REG_F19  REG_F19_NDX
+#define REG_F20  REG_F20_NDX
+#define REG_F21  REG_F21_NDX
+#define REG_F22  REG_F22_NDX
+#define REG_F23  REG_F23_NDX
+#define REG_F24  REG_F24_NDX
+#define REG_F25  REG_F25_NDX
+#define REG_F26  REG_F26_NDX
+#define REG_F27  REG_F27_NDX
+#define REG_F28  REG_F28_NDX
+#define REG_F29  REG_F29_NDX
+#define REG_F30  REG_F30_NDX
+#define REG_F31  REG_F31_NDX
+#define REG_FCSR REG_FCSR_NDX
+#endif
+
+#endif
+
+/* Now define more user friendly alternative name that can be used either
+ * in assembly or C contexts.
+ */
+
+/* $1 = ra: Return address */
+
+#define REG_RA REG_X1
+
+/* $2 = sp:  The value of the stack pointer on return from the exception */
+
+#define REG_SP REG_X2
+
+/* $3 = gp: Only needs to be saved under conditions where there are
+ * multiple, per-thread values for the GP.
+ */
+
+#define REG_GP REG_X3
+
+/* $4 = tp:  Thread Pointer */
+
+#define REG_TP REG_X4
+
+/* $5-$7 = t0-t2: Caller saved temporary registers */
+
+#define REG_T0 REG_X5
+#define REG_T1 REG_X6
+#define REG_T2 REG_X7
+
+/* $8 = either s0 or fp:  Depends if a frame pointer is used or not */
+
+#define REG_S0 REG_X8
+#define REG_FP REG_X8
+
+/* $9 = s1: Caller saved register */
+
+#define REG_S1 REG_X9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_A0 REG_X10
+#define REG_A1 REG_X11
+#define REG_A2 REG_X12
+#define REG_A3 REG_X13
+#define REG_A4 REG_X14
+#define REG_A5 REG_X15
+#define REG_A6 REG_X16
+#define REG_A7 REG_X17
+
+/* $18-$27 = s2-s11: Callee saved registers */
+
+#define REG_S2  REG_X18
+#define REG_S3  REG_X19
+#define REG_S4  REG_X20
+#define REG_S5  REG_X21
+#define REG_S6  REG_X22
+#define REG_S7  REG_X23
+#define REG_S8  REG_X24
+#define REG_S9  REG_X25
+#define REG_S10 REG_X26
+#define REG_S11 REG_X27
+
+/* $28-$31 = t3-t6: Caller saved temporary registers */
+
+#define REG_T3 REG_X28
+#define REG_T4 REG_X29
+#define REG_T5 REG_X30
+#define REG_T6 REG_X31
+
+#ifndef __ASSEMBLY__
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+# ifdef CONFIG_ARCH_FPU
+    extern void riscv_savefpu(uintptr_t *regs);
+    extern void riscv_restorefpu(uintptr_t *regs);
+# else
+    void riscv_savefpu(uintptr_t *regs) {};
+    void riscv_restorefpu(uintptr_t *regs) {};
+# endif
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __IRQ_CTX_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/riscv_fpu.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/riscv_fpu.S
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/riscv_fpu.S
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/riscv_fpu.S
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/start.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/start.S
new file mode 100755
index 0000000000..bea95f0dc6
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/start.S
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016-2020 Bouffalo Lab
+ */
+
+    .section .init
+    .align  2
+    .globl  __start
+    .type   __start, %function
+__start:
+.option push
+.option norelax
+    la      gp, __global_pointer$
+.option pop
+    csrci   mstatus, 8
+
+    /* mtvec: for all exceptions and non-vector mode IRQs */
+    la      a0, default_trap_handler
+    ori     a0, a0, 3
+    csrw    mtvec, a0
+
+    /* mtvt: for all vector mode IRQs */
+    la      a0, __Vectors
+    csrw    mtvt, a0
+
+#if defined(__riscv_flen)
+    /* FP: initial state */
+    csrr    t0, mstatus
+    li      t1, ~0x6000
+    and     t0, t0, t1
+    li      t1, 0x2000
+    or      t0, t0, t1
+    csrw    mstatus, t0
+    /* csrwi   fcsr, 0 */
+#endif
+
+    .weak __StackTop
+    la      sp, __StackTop
+    csrw    mscratch, sp
+
+    /* Load data section removed */
+
+    /* Clear bss section removed */
+
+    jal     SystemInit
+
+    /* start load code to itcm like. */
+    jal     start_load
+
+    jal     System_Post_Init
+
+    jal     entry
+
+    .size   __start, . - __start
+
+__exit:
+    j      __exit
+
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/start_load.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/start_load.c
old mode 100644
new mode 100755
similarity index 78%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/start_load.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/start_load.c
index fe08dce0c0..f9715fccac
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/start_load.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/start_load.c
@@ -9,6 +9,7 @@ extern uint32_t __itcm_load_addr;
 extern uint32_t __dtcm_load_addr;
 extern uint32_t __system_ram_load_addr;
 extern uint32_t __ram_load_addr;
+extern uint32_t __nocache_ram_load_addr;
 
 extern uint32_t __text_code_start__;
 extern uint32_t __text_code_end__;
@@ -16,14 +17,14 @@ extern uint32_t __tcm_code_start__;
 extern uint32_t __tcm_code_end__;
 extern uint32_t __tcm_data_start__;
 extern uint32_t __tcm_data_end__;
-extern uint32_t __system_ram_data_start__;
-extern uint32_t __system_ram_data_end__;
 extern uint32_t __ram_data_start__;
 extern uint32_t __ram_data_end__;
 extern uint32_t __bss_start__;
 extern uint32_t __bss_end__;
 extern uint32_t __noinit_data_start__;
 extern uint32_t __noinit_data_end__;
+extern uint32_t __nocache_ram_data_start__;
+extern uint32_t __nocache_ram_data_end__;
 
 extern uint32_t __StackTop;
 extern uint32_t __StackLimit;
@@ -56,14 +57,6 @@ void start_load(void)
         *pDest++ = *pSrc++;
     }
 
-    /* BF Add system RAM data copy */
-    pSrc = &__system_ram_load_addr;
-    pDest = &__system_ram_data_start__;
-
-    for (; pDest < &__system_ram_data_end__;) {
-        *pDest++ = *pSrc++;
-    }
-
     /* BF Add OCARAM data copy */
     pSrc = &__ram_load_addr;
     pDest = &__ram_data_start__;
@@ -72,15 +65,23 @@ void start_load(void)
         *pDest++ = *pSrc++;
     }
 
+    /* BF Add no cache ram data copy */
+    pSrc = &__nocache_ram_load_addr;
+    pDest = &__nocache_ram_data_start__;
+
+    for (; pDest < &__nocache_ram_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
 #ifdef __STARTUP_CLEAR_BSS
     /*  Single BSS section scheme.
-     *
-     *  The BSS section is specified by following symbols
-     *    __bss_start__: start of the BSS section.
-     *    __bss_end__: end of the BSS section.
-     *
-     *  Both addresses must be aligned to 4 bytes boundary.
-     */
+	 *
+	 *  The BSS section is specified by following symbols
+	 *    __bss_start__: start of the BSS section.
+	 *    __bss_end__: end of the BSS section.
+	 *
+	 *  Both addresses must be aligned to 4 bytes boundary.
+	 */
     pDest = &__bss_start__;
 
     for (; pDest < &__bss_end__;) {
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/system_bl616.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/system_bl616.c
new file mode 100755
index 0000000000..0047c2afd7
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/system_bl616.c
@@ -0,0 +1,147 @@
+#include "bl616_clock.h"
+#include "bl616_pds.h"
+#include "tzc_sec_reg.h"
+#include "rv_hart.h"
+#include "rv_pmp.h"
+
+static void Tzc_Sec_PSRAMB_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t endAddr, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+    tmpVal &= (~(3 << (region * 2)));
+    tmpVal |= (group << (region * 2));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+
+    tmpVal = ((((endAddr >> 10) & 0xffff) - 1) & 0xffff) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_PSRAMB_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable but not lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    //tmpVal |= 1<<(region+24);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_PSRAMB_TZSRG_CTRL, tmpVal);
+}
+static void Tzc_Sec_ROM_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t length, uint8_t group)
+{
+    uint32_t tmpVal = 0;
+    uint32_t alignEnd = (startAddr + length + 1023) & ~0x3FF;
+
+    /* check the parameter */
+    group = group & 0xf;
+
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal &= (~(0xf << (region * 4)));
+    tmpVal |= (group << (region * 4));
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+
+    tmpVal = (((alignEnd >> 10) & 0xffff) - 1) | (((startAddr >> 10) & 0xffff) << 16);
+    BL_WR_WORD(TZC_SEC_BASE + TZC_SEC_TZC_ROM_TZSRG_R0_OFFSET + region * 4, tmpVal);
+
+    /* set enable and lock */
+    tmpVal = BL_RD_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL);
+    tmpVal |= 1 << (region + 16);
+    // tmpVal |= 1 << (region + 24);
+    BL_WR_REG(TZC_SEC_BASE, TZC_SEC_TZC_ROM_TZSRG_CTRL, tmpVal);
+}
+static void pmp_init(void)
+{
+    const pmp_config_entry_t pmp_entry_tab[6] = {
+        /* no access 0x00000000-0x20000000*/
+        [0] = {
+            .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
+            .entry_pa_base = 0x00000000,
+            .entry_pa_length = PMP_REG_SZ_512M,
+        },
+        /* no access 0x40000000-0x60000000*/
+        [1] = {
+            .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
+            .entry_pa_base = 0x40000000,
+            .entry_pa_length = PMP_REG_SZ_512M,
+        },
+        /* no access 0x70000000-0x80000000*/
+        [2] = {
+            .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
+            .entry_pa_base = 0x70000000,
+            .entry_pa_length = PMP_REG_SZ_256M,
+        },
+        /* no access 0x80000000-0x90000000*/
+        [3] = {
+            .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
+            .entry_pa_base = 0x80000000,
+            .entry_pa_length = PMP_REG_SZ_256M,
+        },
+        /* no access 0xB0000000-0xC0000000*/
+        [4] = {
+            .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
+            .entry_pa_base = 0xB0000000,
+            .entry_pa_length = PMP_REG_SZ_256M,
+        },
+        /* no access 0xC0000000-0xE0000000*/
+        [5] = {
+            .entry_flag = ENTRY_FLAG_ADDR_NAPOT | ENTRY_FLAG_M_MODE_L,
+            .entry_pa_base = 0xC0000000,
+            .entry_pa_length = PMP_REG_SZ_512M,
+        }
+    };
+    rvpmp_init(pmp_entry_tab, sizeof(pmp_entry_tab) / sizeof(pmp_config_entry_t));
+}
+
+void SystemInit(void)
+{
+    uint32_t i = 0;
+
+    /* CPU Prefetching barrier */
+    Tzc_Sec_PSRAMB_Access_Set_Not_Lock(0, 0x0, 64 * 1024 * 1024, 0);
+    Tzc_Sec_ROM_Access_Set_Not_Lock(1, 0x90020000, ((256 * 1024 * 1024) - (128 * 1024)), 0);
+    pmp_init();
+
+    /* enable mstatus FS */
+    uint32_t mstatus = __get_MSTATUS();
+    mstatus |= (1 << 13);
+    __set_MSTATUS(mstatus);
+
+    /* enable mxstatus THEADISAEE */
+    uint32_t mxstatus = __get_MXSTATUS();
+    mxstatus |= (1 << 22);
+    /* enable mxstatus MM */
+    mxstatus |= (1 << 15);
+    __set_MXSTATUS(mxstatus);
+
+    /* get interrupt level from info */
+    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
+
+    /* Every interrupt should be clear by software*/
+    for (i = 0; i < IRQn_LAST; i++) {
+        CLIC->CLICINT[i].IE = 0;
+        CLIC->CLICINT[i].IP = 0;
+        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+    }
+
+    /* tspend interrupt will be clear auto*/
+    /* tspend use positive interrupt */
+    CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
+
+    csi_dcache_enable();
+    csi_icache_enable();
+
+    /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/
+    uint32_t mexstatus = __get_MEXSTATUS();
+    mexstatus &= ~(0x3 << 16);
+    __set_MEXSTATUS(mexstatus);
+
+    BL_WR_REG(GLB_BASE, GLB_UART_CFG1, 0xffffffff);
+    BL_WR_REG(GLB_BASE, GLB_UART_CFG2, 0x0000ffff);
+}
+
+void System_Post_Init(void)
+{
+    /* Bootrom not use dcache,so ignore this flush*/
+#ifndef BOOTROM
+    csi_dcache_clean();
+    csi_icache_invalid();
+#endif
+
+    /* global IRQ enable */
+    __enable_irq();
+}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/vectors.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/vector.S
old mode 100644
new mode 100755
similarity index 74%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/vectors.S
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/vector.S
index 6e39e39b5b..8b605245d1
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/vectors.S
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl616/std/startup/vector.S
@@ -26,7 +26,7 @@ g_trap_sp_base:
     .space 512
 #endif
 g_trap_sp:
-
+#if 0
 .section .bss.g_irq_stack
     .align 4
     .global g_irq_sp_base
@@ -34,25 +34,48 @@ g_trap_sp:
 g_irq_sp_base:
     .space 1024
 g_irq_sp:
-
+#endif
 /******************************************************************************
  * Functions:
- *     void Default_IRQHandler(void);
+ *     void default_interrupt_handler(void);
  * default handler for all the vector mode IRQs
  ******************************************************************************/
 
-    .section .text.vectors.Default_IRQHandler, "ax", %progbits
+    .section .text.vectors.default_interrupt_handler, "ax", %progbits
     .align  6
-    .global Default_IRQHandler
-    .weak   Default_IRQHandler
+    .global default_interrupt_handler
+    .weak   default_interrupt_handler
     /* FreeRTOS will define tspend_handler for context switch */
-    .weak   tspend_handler
-    .weak   Mtimer_IRQHandler
-    .type   Default_IRQHandler, %function
-tspend_handler:
-Mtimer_IRQHandler:
-Default_IRQHandler:
-    ipush
+    .type   default_interrupt_handler, %function
+default_interrupt_handler:
+    /* ipush */
+    addi  sp, sp, -76
+
+    /* save x5 x6 then save mepc mcause */
+    sw    x5, 4(sp)
+    sw    x6, 8(sp)
+    csrr  t0, mepc
+    csrr  t1, mcause
+    sw    t1, 64(sp)
+    sw    t0, 68(sp)
+    csrr  t0, mscratch
+    sw    t0, 72(sp)
+    /* save regs */
+    sw      x1, 0(sp)
+    sw      x7, 12(sp)
+    sw      x10, 16(sp)
+    sw      x11, 20(sp)
+    sw      x12, 24(sp)
+    sw      x13, 28(sp)
+    sw      x14, 32(sp)
+    sw      x15, 36(sp)
+    sw      x16, 40(sp)
+    sw      x17, 44(sp)
+    sw      x28, 48(sp)
+    sw      x29, 52(sp)
+    sw      x30, 56(sp)
+    sw      x31, 60(sp)
+
     /*
      * IRQ stack contents after ipush:
      * ~mem addr high:
@@ -78,6 +101,7 @@ Default_IRQHandler:
      * ~mem addr low:
      */
     /* WARNING: global IRQ enabled by ipush */
+    csrs    mstatus, 8
 
     /* keep stack 16bytes aligned */
     addi    sp, sp, -88
@@ -115,14 +139,7 @@ Default_IRQHandler:
     csrr    a0, mcause
     andi    t1, a0, 0x3FF
     /* get ISR */
-    la      t0, g_irqvector
-#if defined( __riscv_xtheade )
-    lrw     t2, t0, t1, 2
-#else
-    slli    t1, t1, 2
-    add     t0, t0, t1
-    lw      t2, (t0)
-#endif
+    la      t2, interrupt_entry
     jalr    t2
 
     lw      t1, 84(sp)
@@ -155,23 +172,52 @@ Default_IRQHandler:
 .F_RegNotLoad:
     addi    sp, sp, 88
     /* mret included, and IRQ tail-chain may happen */
-    ipop
+    /* ipop */
 
-    .size   Default_IRQHandler, . - Default_IRQHandler
+    csrc    mstatus, 8
+    /* restore mepc mcause mscrath */
+    lw      t0, 68(sp)
+    csrw    mepc, t0
+    lw      t0, 64(sp)
+    csrw    mcause, t0
+    lw      t0, 72(sp)
+    csrw    mscratch, t0
+    /* restore regs */
+    lw      x1, 0(sp)
+    lw      x5, 4(sp)
+    lw      x6, 8(sp)
+    lw      x7, 12(sp)
+    lw      x10, 16(sp)
+    lw      x11, 20(sp)
+    lw      x12, 24(sp)
+    lw      x13, 28(sp)
+    lw      x14, 32(sp)
+    lw      x15, 36(sp)
+    lw      x16, 40(sp)
+    lw      x17, 44(sp)
+    lw      x28, 48(sp)
+    lw      x29, 52(sp)
+    lw      x30, 56(sp)
+    lw      x31, 60(sp)
+
+    addi    sp, sp, 76
+    mret
+
+    .size   default_interrupt_handler, . - default_interrupt_handler
 
 /******************************************************************************
  * Functions:
  *     void trap(void);
  * default handler for exceptions and non-vector mode IRQs
  ******************************************************************************/
-    .section .text.vectors.Default_Handler, "ax", %progbits
+    .section .text.vectors.default_trap_handler, "ax", %progbits
     .align  6
     .global trap
     .type   trap, %function
-    .weak   Default_Handler
-    .global Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
+    .weak   default_trap_handler
+    .global default_trap_handler
+    .type   default_trap_handler, %function
+default_trap_handler:
 trap:
     /* Check for interrupt */
     sw      t0, -4(sp)
@@ -222,7 +268,7 @@ trap:
     mv      sp, a0
     sw      t0, REG_X5(sp)
 
-    jal     trap_c
+    jal     exception_entry
 
     lw      t0, REG_INT_CTX(sp)
     csrw    mstatus, t0
@@ -267,19 +313,8 @@ trap:
     lw      t0, -4(sp)
 /* MSOFT IRQ for FreeRTOS context switch
  * Config MSOFT IRQ to non-vector mode
- * tspend_handler is a weak alias to Default_IRQHandler
+ * tspend_handler is a weak alias to default_interrupt_handler
  */
-    j       tspend_handler
+    j       default_interrupt_handler
 
-    .size   Default_Handler, . - Default_Handler
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro  def_irq_handler handler_name
-    .weak   \handler_name
-    .globl  \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
-
-    def_irq_handler Mtspend_Handler
+    .size   default_trap_handler, . - default_trap_handler
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/SConscript
new file mode 100755
index 0000000000..0a3d1fe3b2
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/SConscript
@@ -0,0 +1,48 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = []
+
+CPPPATH = [cwd]
+CPPDEFINES = []
+
+src += Split("""
+    std/startup/start.S
+    std/startup/start_load.c
+    std/startup/system_bl702.c
+    std/startup/interrupt.c
+""")
+
+src += Split("""
+    std/src/bl702_aon.c
+    std/src/bl702_common.c
+    std/src/bl702_clock.c
+    std/src/bl702_ef_cfg.c
+    std/src/bl702_glb.c
+    std/src/bl702_hbn.c
+    std/src/bl702_l1c.c
+    std/src/bl702_pds.c 
+    std/src/bl702_sflash_ext.c
+    std/src/bl702_xip_sflash_ext.c
+    std/src/bl702_sf_cfg_ext.c
+""")
+src += ['std/port/bl702_clock.c']
+
+CPPPATH += [cwd + r'/std/include',
+        cwd + r'/std/include/hardware']
+
+if GetDepend('BSP_USING_ROMAPI'):
+    src += Split("""
+        std/src/bl702_romapi.c
+    """)
+    CPPDEFINES += ['BFLB_USE_ROM_DRIVER']
+
+CPPDEFINES += ['CONFIG_IRQ_NUM=80', 'BFLB_USE_HAL_DRIVER', 'BL702', 'default_interrupt_handler=SW_handler']
+LOCAL_CFLAGS = ' -DARCH_RISCV'
+
+group = DefineGroup('bl702', src, depend = ['BSP_USING_BL70X'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
+
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_aon.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_aon.h
new file mode 100755
index 0000000000..317f5a7fd3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_aon.h
@@ -0,0 +1,111 @@
+/**
+  ******************************************************************************
+  * @file    bl702_aon.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_AON_H__
+#define __BL702_AON_H__
+
+#include "aon_reg.h"
+#include "glb_reg.h"
+#include "hbn_reg.h"
+#include "pds_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Public_Types
+ *  @{
+ */
+
+/*@} end of group AON_Public_Types */
+
+/** @defgroup  AON_Public_Constants
+ *  @{
+ */
+
+/*@} end of group AON_Public_Constants */
+
+/** @defgroup  AON_Public_Macros
+ *  @{
+ */
+
+/*@} end of group AON_Public_Macros */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+/*----------*/
+BL_Err_Type AON_Power_On_MBG(void);
+BL_Err_Type AON_Power_Off_MBG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_XTAL(void);
+BL_Err_Type AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut);
+uint8_t AON_Get_Xtal_CapCode(void);
+BL_Err_Type AON_Set_Xtal_CapCode_Extra(uint8_t extra);
+BL_Err_Type AON_Power_Off_XTAL(void);
+/*----------*/
+BL_Err_Type AON_Power_On_BG(void);
+BL_Err_Type AON_Power_Off_BG(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO11_SOC(void);
+BL_Err_Type AON_Power_Off_LDO11_SOC(void);
+/*----------*/
+BL_Err_Type AON_Power_On_LDO15_RF(void);
+BL_Err_Type AON_Power_Off_LDO15_RF(void);
+/*----------*/
+BL_Err_Type AON_Power_On_SFReg(void);
+BL_Err_Type AON_Power_Off_SFReg(void);
+/*----------*/
+BL_Err_Type AON_LowPower_Enter_PDS0(void);
+BL_Err_Type AON_LowPower_Exit_PDS0(void);
+/*----------*/
+BL_Err_Type AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay);
+/*----------*/
+BL_Err_Type AON_Set_DCDC18_Top_0(uint8_t voutSel, uint8_t vpfm);
+BL_Err_Type AON_Set_Xtal_Cfg(uint8_t gmBoost, uint8_t ampCtrl, uint8_t fastStartup);
+/*----------*/
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_AON_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_clock.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_clock.h
new file mode 100755
index 0000000000..0033dfea9f
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_clock.h
@@ -0,0 +1,134 @@
+/**
+  ******************************************************************************
+  * @file    bl702_clock.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_CLOCK_H__
+#define __BL702_CLOCK_H__
+
+#include "glb_reg.h"
+#include "bl702_hbn.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief System clock type definition
+ */
+typedef enum {
+    BL_SYSTEM_CLOCK_ROOT, /*!< ROOT clock */
+    BL_SYSTEM_CLOCK_FCLK, /*!< Fast clock/CPU clock */
+    BL_SYSTEM_CLOCK_BCLK, /*!< BUS clock */
+    BL_SYSTEM_CLOCK_F32K, /*!< F32K clock */
+    BL_SYSTEM_CLOCK_XCLK, /*!< XCLK:RC32M or XTAL */
+    BL_SYSTEM_CLOCK_XTAL, /*!< XTAL clock */
+    BL_SYSTEM_CLOCK_MAX,  /*!< MAX type of system clock */
+} BL_System_Clock_Type;
+
+typedef enum {
+    BL_PERIPHERAL_CLOCK_UART0,   /*!< UART0 clock */
+    BL_PERIPHERAL_CLOCK_UART1,   /*!< UART1 clock */
+    BL_PERIPHERAL_CLOCK_SPI0,    /*!< SPI0 clock */
+    BL_PERIPHERAL_CLOCK_I2C0,    /*!< I2C0 clock */
+    BL_PERIPHERAL_CLOCK_I2S,     /*!< I2S clock */
+    BL_PERIPHERAL_CLOCK_GPADC,   /*!< GPADC clock */
+    BL_PERIPHERAL_CLOCK_GPDAC,   /*!< GPDAC clock */
+    BL_PERIPHERAL_CLOCK_PWM,     /*!< PWM clock */
+    BL_PERIPHERAL_CLOCK_IR,      /*!< IR clock */
+    BL_PERIPHERAL_CLOCK_FLASH,   /*!< FLASH clock */
+    BL_PERIPHERAL_CLOCK_CAM,     /*!< CAM clock */
+    BL_PERIPHERAL_CLOCK_QDEC,    /*!< QDEC clock */
+    BL_PERIPHERAL_CLOCK_TIMER0,  /*!< TIMER0 clock */
+    BL_PERIPHERAL_CLOCK_TIMER1,  /*!< TIMER1 clock */
+    BL_PERIPHERAL_CLOCK_WDT,     /*!< WDT clock */
+    BL_PERIPHERAL_CLOCK_MAX,
+} BL_Peripheral_Type;
+
+/**
+ *  @brief SOC clock config type
+ */
+typedef struct
+{
+    uint16_t systemClock[BL_SYSTEM_CLOCK_MAX];   /*!< System lock value */
+    uint16_t peripheralClock[BL_AHB_SLAVE1_MAX]; /*!< Pewripherals clock value */
+    uint32_t i2sClock;                           /*!< I2S clock */
+} Clock_Cfg_Type;
+
+/*@} end of group CLOCK_Public_Types */
+
+/** @defgroup  CLOCK_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  BL_SYSTEM_CLOCK_TYPE
+ *  @{
+ */
+#define IS_BL_SYSTEM_CLOCK_TYPE(type) (((type) == BL_SYSTEM_CLOCK_ROOT) || \
+                                       ((type) == BL_SYSTEM_CLOCK_FCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_BCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_F32K) || \
+                                       ((type) == BL_SYSTEM_CLOCK_XCLK) || \
+                                       ((type) == BL_SYSTEM_CLOCK_XTAL) || \
+                                       ((type) == BL_SYSTEM_CLOCK_MAX))
+
+/*@} end of group CLOCK_Public_Constants */
+
+/** @defgroup  CLOCK_Public_Macros
+ *  @{
+ */
+
+/*@} end of group CLOCK_Public_Macros */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type);
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type);
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_CLOCK_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_common.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_common.h
new file mode 100755
index 0000000000..5142f70d83
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_common.h
@@ -0,0 +1,215 @@
+#ifndef __BL702_COMMON_H__
+#define __BL702_COMMON_H__
+
+#include "bl702.h"
+#include "bflb_core.h"
+
+/**
+ * @brief Memory access macro
+ */
+#define BL_RD_WORD(addr)       (*((volatile uint32_t *)(uintptr_t)(addr)))
+#define BL_WR_WORD(addr, val)  ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_SHORT(addr)      (*((volatile uint16_t *)(uintptr_t)(addr)))
+#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_BYTE(addr)       (*((volatile uint8_t *)(uintptr_t)(addr)))
+#define BL_WR_BYTE(addr, val)  ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val))
+#define BL_RDWD_FRM_BYTEP(p)   ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+
+#define BL_WRWD_TO_BYTEP(p, val)   \
+    {                              \
+        p[0] = val & 0xff;         \
+        p[1] = (val >> 8) & 0xff;  \
+        p[2] = (val >> 16) & 0xff; \
+        p[3] = (val >> 24) & 0xff; \
+    }
+/**
+ * @brief Register access macro
+ */
+#define BL_RD_REG16(addr, regname)                BL_RD_SHORT(addr + regname##_OFFSET)
+#define BL_WR_REG16(addr, regname, val)           BL_WR_SHORT(addr + regname##_OFFSET, val)
+#define BL_RD_REG(addr, regname)                  BL_RD_WORD(addr + regname##_OFFSET)
+#define BL_WR_REG(addr, regname, val)             BL_WR_WORD(addr + regname##_OFFSET, val)
+#define BL_SET_REG_BIT(val, bitname)              ((val) | (1U << bitname##_POS))
+#define BL_CLR_REG_BIT(val, bitname)              ((val)&bitname##_UMSK)
+#define BL_GET_REG_BITS_VAL(val, bitname)         (((val)&bitname##_MSK) >> bitname##_POS)
+#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
+#define BL_IS_REG_BIT_SET(val, bitname)           (((val) & (1U << (bitname##_POS))) != 0)
+#define BL_DRV_DUMMY           \
+    {                          \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+    }
+
+/** @defgroup  COMMON_Public_Types
+ *  @{
+ */
+#ifdef BIT
+#undef BIT
+#define BIT(n) (1UL << (n))
+#else
+#define BIT(n) (1UL << (n))
+#endif
+
+/**
+ * @brief Null Type definition
+ */
+#ifndef NULL
+#define NULL 0
+#endif
+
+/**
+ * @brief Error type definition
+ */
+typedef enum {
+    SUCCESS = 0,
+    ERROR = 1,
+    TIMEOUT = 2,
+    INVALID = 3, /* invalid arguments */
+    NORESC = 4   /* no resource or resource temperary unavailable */
+} BL_Err_Type;
+
+/**
+ * @brief Functional type definition
+ */
+typedef enum {
+    DISABLE = 0,
+    ENABLE = 1,
+} BL_Fun_Type;
+
+/**
+ * @brief Status type definition
+ */
+typedef enum {
+    RESET = 0,
+    SET = 1,
+} BL_Sts_Type;
+
+/**
+ * @brief Mask type definition
+ */
+typedef enum {
+    UNMASK = 0,
+    MASK = 1
+} BL_Mask_Type;
+
+/**
+ * @brief Logical status Type definition
+ */
+typedef enum {
+    LOGIC_LO = 0,
+    LOGIC_HI = !LOGIC_LO
+} LogicalStatus;
+
+/**
+ * @brief Active status Type definition
+ */
+typedef enum {
+    DEACTIVE = 0,
+    ACTIVE = !DEACTIVE
+} ActiveStatus;
+
+/**
+ *  @brief Interrupt callback function type
+ */
+typedef void(intCallback_Type)(void);
+typedef void (*pFunc)(void);
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr) ((void)0)
+#endif /* DEBUG */
+
+#ifndef __NOP
+#define __NOP() __ASM volatile("nop") /* This implementation generates debug information */
+#endif
+#ifndef __WFI
+#define __WFI() __ASM volatile("wfi") /* This implementation generates debug information */
+#endif
+#ifndef __WFE
+#define __WFE() __ASM volatile("wfe") /* This implementation generates debug information */
+#endif
+#ifndef __SEV
+#define __SEV() __ASM volatile("sev") /* This implementation generates debug information */
+#endif
+#ifndef __set_MSP
+#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
+#endif
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV(uint32_t value)
+{
+    //return __builtin_bswap32(value);
+    uint32_t res = 0;
+
+    res = (value << 24) | (value >> 24);
+    res &= 0xFF0000FF; /* only for sure */
+    res |= ((value >> 8) & 0x0000FF00) | ((value << 8) & 0x00FF0000);
+
+    return res;
+}
+
+__attribute__((always_inline)) __STATIC_INLINE uint32_t __REV16(uint32_t value)
+{
+    return __builtin_bswap16(value);
+}
+
+/**
+  \brief   Enable IRQ Interrupts
+  \details Enables IRQ interrupts by setting the IE-bit in the PSR.
+           Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __enable_irq(void)
+{
+    __ASM volatile("csrs mstatus, 8");
+}
+
+/**
+  \brief   Disable IRQ Interrupts
+  \details Disables IRQ interrupts by clearing the IE-bit in the PSR.
+  Can only be executed in Privileged modes.
+ */
+__ALWAYS_STATIC_INLINE void __disable_irq(void)
+{
+    __ASM volatile("csrc mstatus, 8");
+}
+
+/** @defgroup  COMMON_Public_Constants
+ *  @{
+ */
+
+/** @defgroup DRIVER_INT_PERIPH
+ *  @{
+ */
+#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
+
+/*@} end of group DRIVER_INT_PERIPH */
+
+/** @defgroup DRIVER_INT_MASK
+ *  @{
+ */
+#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
+
+/*@} end of group COMMON_Public_Constants */
+
+/*@} end of group DRIVER_Public_Macro */
+#define BL702_MemCpy      arch_memcpy
+#define BL702_MemSet      arch_memset
+#define BL702_MemCmp      arch_memcmp
+#define BL702_MemCpy4     arch_memcpy4
+#define BL702_MemCpy_Fast arch_memcpy_fast
+#define BL702_MemSet4     arch_memset4
+
+#define BL702_Delay_US arch_delay_us
+#define BL702_Delay_MS arch_delay_ms
+
+#define BFLB_Soft_CRC32 bflb_soft_crc32
+#define CPU_Interrupt_Enable(irq)
+#define CPU_Interrupt_Disable(irq)
+#define Interrupt_Handler_Register(irq, callback)
+
+void BL702_Delay_US(uint32_t cnt);
+void BL702_Delay_MS(uint32_t cnt);
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_cfg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_cfg.h
new file mode 100755
index 0000000000..eceaf1d907
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_cfg.h
@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    bl702_ef_cfg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_EF_CFG_H__
+#define __BL702_EF_CFG_H__
+
+#include "bflb_ef_ctrl.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_Public_Types
+ *  @{
+ */
+/**
+ *  @brief Efuse analog device info type definition
+ */
+typedef struct
+{
+    uint32_t rsvd_21_0   : 22; /*!< Reserved */
+    uint32_t sf_swap_cfg : 2;  /*!< 0:swap none, 1:swap SF2_CS & SF2_IO2, 2:swap SF2_IO0 & SF2_IO3, 3:swap both */
+    uint32_t psram_cfg   : 2;  /*!< 0:no psram, 1:2MB psram, 2:external psram, 3:reserved */
+    uint32_t flash_cfg   : 3;  /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1, 5:2MB flash */
+    uint32_t rsvd_29     : 1;  /*!< Reserved */
+    uint32_t pkg_info    : 2;  /*!< 0:QFN32, 1:QFN40, 2:QFN48, 3:reserved */
+} bflb_efuse_device_info_type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
+ *  @{
+ */
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup  EF_CTRL_Public_Macros
+ *  @{
+ */
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup  EF_CTRL_Public_Functions
+ *  @{
+ */
+void bflb_efuse_switch_cpu_clock_save(void);
+void bflb_efuse_switch_cpu_clock_restore(void);
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo);
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **trim_list);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_EF_CFG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_ctrl.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_ctrl.h
new file mode 100755
index 0000000000..d2c492a3f3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_ef_ctrl.h
@@ -0,0 +1,329 @@
+/**
+  ******************************************************************************
+  * @file    bl702_ef_ctrl.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_EF_CTRL_H__
+#define __BL702_EF_CTRL_H__
+
+#include "ef_ctrl_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  EF_CTRL
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Efuse Ctrl key slot type definition
+ */
+typedef enum {
+    EF_CTRL_KEY_SLOT0, /*!< key slot 0 */
+    EF_CTRL_KEY_SLOT1, /*!< key slot 1 */
+    EF_CTRL_KEY_SLOT2, /*!< key slot 2 */
+    EF_CTRL_KEY_SLOT3, /*!< key slot 3 */
+    EF_CTRL_KEY_SLOT4, /*!< key slot 4 */
+    EF_CTRL_KEY_SLOT5, /*!< key slot 5 */
+    EF_CTRL_KEY_MAX,   /*!<  */
+} EF_Ctrl_Key_Type;
+
+/**
+ *  @brief Efuse Ctrl sign type definition
+ */
+typedef enum {
+    EF_CTRL_SIGN_NONE, /*!< no sign */
+    EF_CTRL_SIGN_RSA,  /*!< use RSA to sign */
+    EF_CTRL_SIGN_ECC,  /*!< use ECC to sign */
+} EF_Ctrl_Sign_Type;
+
+/**
+ *  @brief Efuse Ctrl flash AES type definition
+ */
+typedef enum {
+    EF_CTRL_SF_AES_NONE, /*!< No AES */
+    EF_CTRL_SF_AES_128,  /*!< AES 128 */
+    EF_CTRL_SF_AES_192,  /*!< AES 192 */
+    EF_CTRL_SF_AES_256,  /*!< AES 256 */
+} EF_Ctrl_SF_AES_Type;
+
+/**
+ *  @brief Efuse Ctrl Dbg type definition
+ */
+typedef enum {
+    EF_CTRL_DBG_OPEN = 0,  /*!< Open debug */
+    EF_CTRL_DBG_PASSWORD,  /*!< Open debug with password */
+    EF_CTRL_DBG_CLOSE = 4, /*!< Close debug */
+} EF_Ctrl_Dbg_Mode_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_EF_CLK,   /*!< Select efuse clock */
+    EF_CTRL_SAHB_CLK, /*!< Select SAHB clock */
+} EF_Ctrl_CLK_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_PARA_DFT,    /*!< Select default cyc parameter */
+    EF_CTRL_PARA_MANUAL, /*!< Select manual cyc parameter */
+} EF_Ctrl_CYC_PARA_Type;
+
+/**
+ *  @brief Efuse Ctrl clock type definition
+ */
+typedef enum {
+    EF_CTRL_OP_MODE_AUTO,   /*!< Select efuse program auto mode */
+    EF_CTRL_OP_MODE_MANUAL, /*!< Select efuse program manual mode */
+} EF_Ctrl_OP_MODE_Type;
+
+/**
+ *  @brief Efuse Ctrl secure configuration structure type definition
+ */
+typedef struct
+{
+    EF_Ctrl_Dbg_Mode_Type ef_dbg_mode; /*!< Efuse debug mode */
+    uint8_t ef_dbg_jtag_0_dis;         /*!< Jtag debug disable config value */
+    uint8_t ef_sboot_en;               /*!< Secure boot enable config value */
+} EF_Ctrl_Sec_Param_Type;
+
+/**
+ *  @brief Efuse analog RC32M trim type definition
+ */
+typedef struct
+{
+    uint32_t trimRc32mCodeFrExt       : 8;  /*!< Efuse analog trim:trim_rc32m_code_fr_ext */
+    uint32_t trimRc32mCodeFrExtParity : 1;  /*!< Efuse analog trim:trim_rc32m_ext_code_en_parity */
+    uint32_t trimRc32mExtCodeEn       : 1;  /*!< Efuse analog trim:trim_rc32m_ext_code_en */
+    uint32_t reserved                 : 22; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32M_Trim_Type;
+
+/**
+ *  @brief Efuse analog RC32K trim type definition
+ */
+typedef struct
+{
+    uint32_t trimRc32kCodeFrExt       : 10; /*!< Efuse analog trim:trim_rc32k_code_fr_ext */
+    uint32_t trimRc32kCodeFrExtParity : 1;  /*!< Efuse analog trim:trim_rc32k_code_fr_ext_parity */
+    uint32_t trimRc32kExtCodeEn       : 1;  /*!< Efuse analog trim:trim_rc32k_ext_code_en */
+    uint32_t reserved                 : 20; /*!< Efuse analog trim:reserved */
+} Efuse_Ana_RC32K_Trim_Type;
+
+/**
+ *  @brief Efuse analog TSEN trim type definition
+ */
+typedef struct
+{
+    uint32_t tsenRefcodeCorner        : 12; /*!< TSEN refcode */
+    uint32_t tsenRefcodeCornerParity  : 1;  /*!< TSEN refcode parity */
+    uint32_t tsenRefcodeCornerEn      : 1;  /*!< TSEN refcode enable */
+    uint32_t tsenRefcodeCornerVersion : 1;  /*!< TSEN ATE Version */
+    uint32_t reserved                 : 18; /*!< TSEN analog trim:reserved */
+} Efuse_TSEN_Refcode_Corner_Type;
+
+/**
+ *  @brief Efuse analog ADC Gain trim type definition
+ */
+typedef struct
+{
+    uint32_t adcGainCoeff       : 12; /*!< ADC gain coeff */
+    uint32_t adcGainCoeffParity : 1;  /*!< ADC gain coeff parity */
+    uint32_t adcGainCoeffEn     : 1;  /*!< ADC gain coeff enable */
+    uint32_t reserved           : 18; /*!< ADC gain coeff:reserved */
+} Efuse_ADC_Gain_Coeff_Type;
+
+/**
+ *  @brief Efuse analog device info type definition
+ */
+typedef struct
+{
+    uint32_t rsvd_21_0   : 22; /*!< Reserved */
+    uint32_t sf_swap_cfg : 2;  /*!< 0:swap none, 1:swap SF2_CS & SF2_IO2, 2:swap SF2_IO0 & SF2_IO3, 3:swap both */
+    uint32_t psram_cfg   : 2;  /*!< 0:no psram, 1:2MB psram, 2:external psram, 3:reserved */
+    uint32_t flash_cfg   : 3;  /*!< 0:external flash SF2, 1:0.5MB flash, 2:1MB flash, 3:external flash SF1 */
+    uint32_t rsvd_29     : 1;  /*!< Reserved */
+    uint32_t pkg_info    : 2;  /*!< 0:QFN32, 1:QFN40, 2:QFN48, 3:reserved */
+} Efuse_Device_Info_Type;
+
+/**
+ *  @brief Efuse Capcode type definition
+ */
+typedef struct
+{
+    uint32_t capCode : 6;  /*!< Cap code value */
+    uint32_t parity  : 1;  /*!< Parity of capcode */
+    uint32_t en      : 1;  /*!< Enable status */
+    uint32_t rsvd    : 24; /*!< Reserved */
+} Efuse_Capcode_Info_Type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  EF_CTRL_KEY_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_KEY_TYPE(type) (((type) == EF_CTRL_KEY_SLOT0) || \
+                                   ((type) == EF_CTRL_KEY_SLOT1) || \
+                                   ((type) == EF_CTRL_KEY_SLOT2) || \
+                                   ((type) == EF_CTRL_KEY_SLOT3) || \
+                                   ((type) == EF_CTRL_KEY_SLOT4) || \
+                                   ((type) == EF_CTRL_KEY_SLOT5) || \
+                                   ((type) == EF_CTRL_KEY_MAX))
+
+/** @defgroup  EF_CTRL_SIGN_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SIGN_TYPE(type) (((type) == EF_CTRL_SIGN_NONE) || \
+                                    ((type) == EF_CTRL_SIGN_RSA) ||  \
+                                    ((type) == EF_CTRL_SIGN_ECC))
+
+/** @defgroup  EF_CTRL_SF_AES_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_SF_AES_TYPE(type) (((type) == EF_CTRL_SF_AES_NONE) || \
+                                      ((type) == EF_CTRL_SF_AES_128) ||  \
+                                      ((type) == EF_CTRL_SF_AES_192) ||  \
+                                      ((type) == EF_CTRL_SF_AES_256))
+
+/** @defgroup  EF_CTRL_DBG_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_DBG_MODE_TYPE(type) (((type) == EF_CTRL_DBG_OPEN) ||     \
+                                        ((type) == EF_CTRL_DBG_PASSWORD) || \
+                                        ((type) == EF_CTRL_DBG_CLOSE))
+
+/** @defgroup  EF_CTRL_CLK_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CLK_TYPE(type) (((type) == EF_CTRL_EF_CLK) || \
+                                   ((type) == EF_CTRL_SAHB_CLK))
+
+/** @defgroup  EF_CTRL_CYC_PARA_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_CYC_PARA_TYPE(type) (((type) == EF_CTRL_PARA_DFT) || \
+                                        ((type) == EF_CTRL_PARA_MANUAL))
+
+/** @defgroup  EF_CTRL_OP_MODE_TYPE
+ *  @{
+ */
+#define IS_EF_CTRL_OP_MODE_TYPE(type) (((type) == EF_CTRL_OP_MODE_AUTO) || \
+                                       ((type) == EF_CTRL_OP_MODE_MANUAL))
+
+/*@} end of group EF_CTRL_Public_Constants */
+
+/** @defgroup  EF_CTRL_Public_Macros
+ *  @{
+ */
+#define EF_CTRL_EFUSE_R0_SIZE 128
+
+/*@} end of group EF_CTRL_Public_Macros */
+
+/** @defgroup  EF_CTRL_Public_Functions
+ *  @{
+ */
+void EF_Ctrl_Load_Efuse_R0(void);
+BL_Sts_Type EF_Ctrl_Busy(void);
+BL_Sts_Type EF_Ctrl_AutoLoad_Done(void);
+void EF_Ctrl_Write_Dbg_Pwd(uint32_t passWdLow, uint32_t passWdHigh, uint8_t program);
+void EF_Ctrl_Read_Dbg_Pwd(uint32_t *passWdLow, uint32_t *passWdHigh);
+void EF_Ctrl_Readlock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Writelock_Dbg_Pwd(uint8_t program);
+void EF_Ctrl_Write_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg, uint8_t program);
+void EF_Ctrl_Read_Secure_Cfg(EF_Ctrl_Sec_Param_Type *cfg);
+void EF_Ctrl_Write_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1], uint8_t program);
+void EF_Ctrl_Read_Secure_Boot(EF_Ctrl_Sign_Type sign[1], EF_Ctrl_SF_AES_Type aes[1]);
+void EF_Ctrl_Read_CPU_Cfg(uint8_t *apDisabled, uint8_t *npDisabled, uint8_t *npCpuType);
+uint8_t EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len);
+void EF_Ctrl_Write_Ana_Trim(uint32_t index, uint32_t trim, uint8_t program);
+void EF_Ctrl_Read_Ana_Trim(uint32_t index, uint32_t *trim);
+void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim);
+void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim);
+void EF_Ctrl_Read_TSEN_Trim(Efuse_TSEN_Refcode_Corner_Type *trim);
+void EF_Ctrl_Read_ADC_Gain_Trim(Efuse_ADC_Gain_Coeff_Type *trim);
+void EF_Ctrl_Write_Sw_Usage(uint32_t index, uint32_t usage, uint8_t program);
+void EF_Ctrl_Read_Sw_Usage(uint32_t index, uint32_t *usage);
+void EF_Ctrl_Writelock_Sw_Usage(uint32_t index, uint8_t program);
+void EF_Ctrl_Write_MAC_Address(uint8_t mac[6], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address(uint8_t mac[8]);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Raw(uint8_t mac[7]);
+void EF_Ctrl_Writelock_MAC_Address(uint8_t program);
+uint8_t EF_Ctrl_Is_MAC_Address_Slot_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_MAC_Address_Opt(uint8_t slot, uint8_t mac[8], uint8_t reload);
+BL_Err_Type EF_Ctrl_Read_Chip_ID(uint8_t id[8]);
+/*----------*/
+BL_Err_Type EF_Ctrl_Get_Chip_PIDVID(uint16_t pid[1], uint16_t vid[1]);
+BL_Err_Type EF_Ctrl_Get_Customer_PIDVID(uint16_t pid[1], uint16_t vid[1]);
+/*----------*/
+void EF_Ctrl_Read_Device_Info(Efuse_Device_Info_Type *deviceInfo);
+uint8_t EF_Ctrl_Is_CapCode_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_CapCode_Opt(uint8_t slot, uint8_t code, uint8_t program);
+BL_Err_Type EF_Ctrl_Read_CapCode_Opt(uint8_t slot, uint8_t *code, uint8_t reload);
+uint8_t EF_Ctrl_Is_PowerOffset_Slot_Empty(uint8_t slot, uint8_t reload);
+BL_Err_Type EF_Ctrl_Write_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t program);
+BL_Err_Type EF_Ctrl_Read_PowerOffset_Opt(uint8_t slot, int8_t pwrOffset[2], uint8_t reload);
+void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8_t program);
+void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
+void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program);
+void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Program_Direct(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Read_Direct(uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Clear(uint32_t index, uint32_t len);
+void EF_Ctrl_Crc_Enable(void);
+BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
+void EF_Ctrl_Crc_Set_Golden(uint32_t goldenValue);
+BL_Err_Type EF_Ctrl_Crc_Result(void);
+void EF_Ctrl_Sw_AHB_Clk_0(void);
+
+/*@} end of group EF_CTRL_Public_Functions */
+
+/*@} end of group EF_CTRL */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_EF_CTRL_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_glb.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_glb.h
new file mode 100755
index 0000000000..c26d60d9ad
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_glb.h
@@ -0,0 +1,822 @@
+/**
+  ******************************************************************************
+  * @file    bl702_glb.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_GLB_H__
+#define __BL702_GLB_H__
+
+#include "glb_reg.h"
+#include "pds_reg.h"
+#include "bl702_gpio.h"
+#include "bl702_l1c.h"
+#include "bl702_hbn.h"
+#include "bl702_aon.h"
+#include "bl702_ef_ctrl.h"
+#include "bl702_pds.h"
+#include "bl702_common.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief GLB root clock type definition
+ */
+typedef enum {
+    GLB_ROOT_CLK_RC32M, /*!< root clock select RC32M */
+    GLB_ROOT_CLK_XTAL,  /*!< root clock select XTAL */
+    GLB_ROOT_CLK_DLL,   /*!< root clock select DLL others, PLL120M not recommend */
+} GLB_ROOT_CLK_Type;
+
+/**
+ *  @brief GLB system clock type definition
+ */
+typedef enum {
+    GLB_SYS_CLK_RC32M,    /*!< use RC32M as system clock frequency */
+    GLB_SYS_CLK_XTAL,     /*!< use XTAL as system clock */
+    GLB_SYS_CLK_DLL57P6M, /*!< use DLL output 57.6M as system clock */
+    GLB_SYS_CLK_DLL96M,   /*!< use DLL output 96M as system clock */
+    GLB_SYS_CLK_DLL144M,  /*!< use DLL output 144M as system clock, PLL120M not recommend */
+} GLB_SYS_CLK_Type;
+
+/**
+ *  @brief GLB CAM clock type definition
+ */
+typedef enum {
+    GLB_CAM_CLK_XCLK,   /*!< Select XCLK as CAM clock */
+    GLB_CAM_CLK_DLL96M, /*!< Select DLL96M as CAM clock */
+} GLB_CAM_CLK_Type;
+
+/**
+ *  @brief GLB I2S output ref clock type definition
+ */
+typedef enum {
+    GLB_I2S_OUT_REF_CLK_NONE, /*!< no output reference clock on I2S_0 ref_clock port */
+    GLB_I2S_OUT_REF_CLK_SRC,  /*!< output reference clock on I2S_0 ref_clock port */
+} GLB_I2S_OUT_REF_CLK_Type;
+
+/**
+ *  @brief GLB qdec clock type definition
+ */
+typedef enum {
+    GLB_QDEC_CLK_XCLK, /*!< Select XCLK as QDEC clock */
+    GLB_QDEC_CLK_F32K, /*!< Select f32k as QDEC clock (PDS mode) */
+} GLB_QDEC_CLK_Type;
+
+/**
+ *  @brief GLB DMA clock ID type definition
+ */
+typedef enum {
+    GLB_DMA_CLK_DMA0_CH0, /*!< DMA clock ID:channel 0 */
+    GLB_DMA_CLK_DMA0_CH1, /*!< DMA clock ID:channel 1 */
+    GLB_DMA_CLK_DMA0_CH2, /*!< DMA clock ID:channel 2 */
+    GLB_DMA_CLK_DMA0_CH3, /*!< DMA clock ID:channel 3 */
+    GLB_DMA_CLK_DMA0_CH4, /*!< DMA clock ID:channel 4 */
+    GLB_DMA_CLK_DMA0_CH5, /*!< DMA clock ID:channel 5 */
+    GLB_DMA_CLK_DMA0_CH6, /*!< DMA clock ID:channel 6 */
+    GLB_DMA_CLK_DMA0_CH7, /*!< DMA clock ID:channel 7 */
+} GLB_DMA_CLK_ID_Type;
+
+/**
+ *  @brief GLB clock source type definition
+ */
+typedef enum {
+    GLB_IR_CLK_SRC_XCLK, /*!< IR clock source select XCLK */
+} GLB_IR_CLK_SRC_Type;
+
+/**
+ *  @brief GLB flash clock type definition
+ */
+typedef enum {
+    GLB_SFLASH_CLK_144M,  /*!< Select 144M as flash clock */
+    GLB_SFLASH_CLK_XCLK,  /*!< Select XCLK as flash clock */
+    GLB_SFLASH_CLK_57P6M, /*!< Select 57.6M as flash clock */
+    GLB_SFLASH_CLK_72M,   /*!< Select 72M as flash clock */
+    GLB_SFLASH_CLK_BCLK,  /*!< Select BCLK as flash clock */
+    GLB_SFLASH_CLK_96M,   /*!< Select 96M as flash clock */
+} GLB_SFLASH_CLK_Type;
+
+/**
+ *  @brief GLB chip clock out type definition
+ */
+typedef enum {
+    GLB_CHIP_CLK_OUT_NONE,          /*!< no chip clock out */
+    GLB_CHIP_CLK_OUT_I2S_REF_CLK,   /*!< i2s_ref_clk out */
+    GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK, /*!< audio_pll_clk out */
+    GLB_CHIP_CLK_OUT_XTAL_SOC_32M,  /*!< clk_xtal_soc_32M */
+} GLB_CHIP_CLK_OUT_Type;
+
+/**
+ *  @brief GLB eth ref clock out type definition
+ */
+typedef enum {
+    GLB_ETH_REF_CLK_OUT_OUTSIDE_50M, /*!< select outside 50MHz RMII ref clock */
+    GLB_ETH_REF_CLK_OUT_INSIDE_50M,  /*!< select inside 50MHz RMII ref clock */
+} GLB_ETH_REF_CLK_OUT_Type;
+
+/**
+ *  @brief GLB SPI pad action type definition
+ */
+typedef enum {
+    GLB_SPI_PAD_ACT_AS_SLAVE,  /*!< SPI pad act as slave */
+    GLB_SPI_PAD_ACT_AS_MASTER, /*!< SPI pad act as master */
+} GLB_SPI_PAD_ACT_AS_Type;
+
+/**
+ *  @brief GLB PKA clock type definition
+ */
+typedef enum {
+    GLB_PKA_CLK_HCLK,   /*!< Select HCLK as PKA clock */
+    GLB_PKA_CLK_DLL96M, /*!< Select DLL 96M as PKA clock */
+} GLB_PKA_CLK_Type;
+
+/**
+ *  @brief BMX arb mode type definition
+ */
+typedef enum {
+    BMX_ARB_FIX,         /*!< 0->fix */
+    BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
+    BMX_ARB_RANDOM,      /*!< 3->random */
+} BMX_ARB_Type;
+
+/**
+ *  @brief BMX configuration structure type definition
+ */
+typedef struct {
+    uint8_t timeoutEn;   /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+    BL_Fun_Type errEn;   /*!< Bus error response enable */
+    BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+} BMX_Cfg_Type;
+
+/**
+ *  @brief BMX bus err type definition
+ */
+typedef enum {
+    BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+    BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
+} BMX_BUS_ERR_Type;
+
+/**
+ *  @brief BMX bus err interrupt type definition
+ */
+typedef enum {
+    BMX_ERR_INT_ERR, /*!< BMX bus err interrupt */
+    BMX_ERR_INT_ALL, /*!< BMX bus err interrupt max num */
+} BMX_ERR_INT_Type;
+
+/**
+ *  @brief BMX time out interrupt type definition
+ */
+typedef enum {
+    BMX_TO_INT_TIMEOUT, /*!< BMX timeout interrupt */
+    BMX_TO_INT_ALL,     /*!< BMX timeout interrupt max num */
+} BMX_TO_INT_Type;
+
+/**
+ *  @brief GLB EM type definition
+ */
+typedef enum {
+    GLB_EM_0KB = 0x0,  /*!< 0x0 --> 0KB */
+    GLB_EM_8KB = 0x3,  /*!< 0x3 --> 8KB */
+    GLB_EM_16KB = 0xF, /*!< 0xF --> 16KB */
+} GLB_EM_Type;
+
+/**
+ *  @brief GLB EMAC and CAM pin type definition
+ */
+typedef enum {
+    GLB_EMAC_CAM_PIN_EMAC, /*!< select pin as emac */
+    GLB_EMAC_CAM_PIN_CAM,  /*!< select pin as cam */
+} GLB_EMAC_CAM_PIN_Type;
+
+/**
+ *  @brief GLB RTC clock type definition
+ */
+typedef enum {
+    GLB_MTIMER_CLK_BCLK, /*!< BUS clock */
+    GLB_MTIMER_CLK_32K,  /*!< 32KHz */
+} GLB_MTIMER_CLK_Type;
+
+/**
+ *  @brief GLB ADC clock type definition
+ */
+typedef enum {
+    GLB_ADC_CLK_AUDIO_PLL, /*!< use Audio PLL as ADC clock */
+    GLB_ADC_CLK_XCLK,      /*!< use XCLK as ADC clock */
+} GLB_ADC_CLK_Type;
+
+/**
+ *  @brief GLB DAC clock type definition
+ */
+typedef enum {
+    GLB_DAC_CLK_PLL_32M,   /*!< select PLL 32M as DAC clock source */
+    GLB_DAC_CLK_XCLK,      /*!< select XCLK as DAC clock source */
+    GLB_DAC_CLK_AUDIO_PLL, /*!< select Audio PLL as DAC clock source */
+} GLB_DAC_CLK_Type;
+
+/**
+ *  @brief GLB DIG clock source select type definition
+ */
+typedef enum {
+    GLB_DIG_CLK_PLL_32M,   /*!< select PLL 32M as DIG clock source */
+    GLB_DIG_CLK_XCLK,      /*!< select XCLK as DIG clock source */
+    GLB_DIG_CLK_AUDIO_PLL, /*!< select Audio PLL as DIG clock source */
+} GLB_DIG_CLK_Type;
+
+/**
+ *  @brief GLB BT bandwidth type definition
+ */
+typedef enum {
+    GLB_BT_BANDWIDTH_1M, /*!< BT bandwidth 1MHz */
+    GLB_BT_BANDWIDTH_2M, /*!< BT bandwidth 2MHz */
+} GLB_BT_BANDWIDTH_Type;
+
+/**
+ *  @brief GLB UART signal type definition
+ */
+typedef enum {
+    GLB_UART_SIG_0, /*!< UART signal 0 */
+    GLB_UART_SIG_1, /*!< UART signal 1 */
+    GLB_UART_SIG_2, /*!< UART signal 2 */
+    GLB_UART_SIG_3, /*!< UART signal 3 */
+    GLB_UART_SIG_4, /*!< UART signal 4 */
+    GLB_UART_SIG_5, /*!< UART signal 5 */
+    GLB_UART_SIG_6, /*!< UART signal 6 */
+    GLB_UART_SIG_7, /*!< UART signal 7 */
+} GLB_UART_SIG_Type;
+
+/**
+ *  @brief GLB UART signal  function type definition
+ */
+typedef enum {
+    GLB_UART_SIG_FUN_UART0_RTS, /*!< UART funtion: UART 0 RTS */
+    GLB_UART_SIG_FUN_UART0_CTS, /*!< UART funtion: UART 0 CTS */
+    GLB_UART_SIG_FUN_UART0_TXD, /*!< UART funtion: UART 0 TXD */
+    GLB_UART_SIG_FUN_UART0_RXD, /*!< UART funtion: UART 0 RXD */
+    GLB_UART_SIG_FUN_UART1_RTS, /*!< UART funtion: UART 1 RTS */
+    GLB_UART_SIG_FUN_UART1_CTS, /*!< UART funtion: UART 1 CTS */
+    GLB_UART_SIG_FUN_UART1_TXD, /*!< UART funtion: UART 1 TXD */
+    GLB_UART_SIG_FUN_UART1_RXD, /*!< UART funtion: UART 1 RXD */
+} GLB_UART_SIG_FUN_Type;
+
+/**
+ *  @brief GLB DLL output clock type definition
+ */
+typedef enum {
+    GLB_DLL_CLK_57P6M, /*!< DLL output 57P6M clock */
+    GLB_DLL_CLK_96M,   /*!< DLL output 96M clock */
+    GLB_DLL_CLK_144M,  /*!< DLL output 144M clock */
+    GLB_DLL_CLK_288M,  /*!< DLL output 288M clock */
+    GLB_DLL_CLK_MMDIV, /*!< DLL output mmdiv clock */
+} GLB_DLL_CLK_Type;
+
+/**
+ *  @brief GLB GPIO interrupt trigger mode type definition
+ */
+typedef enum {
+    GLB_GPIO_INT_TRIG_NEG_PULSE, /*!< GPIO negedge pulse trigger interrupt */
+    GLB_GPIO_INT_TRIG_POS_PULSE, /*!< GPIO posedge pulse trigger interrupt */
+    GLB_GPIO_INT_TRIG_NEG_LEVEL, /*!< GPIO negedge level trigger interrupt (32k 3T) */
+    GLB_GPIO_INT_TRIG_POS_LEVEL, /*!< GPIO posedge level trigger interrupt (32k 3T) */
+} GLB_GPIO_INT_TRIG_Type;
+
+/**
+ *  @brief GLB GPIO interrupt control mode type definition
+ */
+typedef enum {
+    GLB_GPIO_INT_CONTROL_SYNC,  /*!< GPIO interrupt sync mode */
+    GLB_GPIO_INT_CONTROL_ASYNC, /*!< GPIO interrupt async mode */
+} GLB_GPIO_INT_CONTROL_Type;
+
+/**
+ *  @brief PLL XTAL type definition
+ */
+typedef enum {
+    GLB_DLL_XTAL_NONE,  /*!< XTAL is none */
+    GLB_DLL_XTAL_32M,   /*!< XTAL is 32M */
+    GLB_DLL_XTAL_RC32M, /*!< XTAL is RC32M */
+} GLB_DLL_XTAL_Type;
+
+typedef enum {
+    GLB_AHB_CLOCK_IP_CPU,
+    GLB_AHB_CLOCK_IP_SDU,
+    GLB_AHB_CLOCK_IP_SEC,
+    GLB_AHB_CLOCK_IP_DMA_0,
+    GLB_AHB_CLOCK_IP_DMA_1,
+    GLB_AHB_CLOCK_IP_DMA_2,
+    GLB_AHB_CLOCK_IP_CCI,
+    GLB_AHB_CLOCK_IP_RF_TOP,
+    GLB_AHB_CLOCK_IP_GPIP,
+    GLB_AHB_CLOCK_IP_TZC,
+    GLB_AHB_CLOCK_IP_EF_CTRL,
+    GLB_AHB_CLOCK_IP_SF_CTRL,
+    GLB_AHB_CLOCK_IP_EMAC,
+    GLB_AHB_CLOCK_IP_UART0,
+    GLB_AHB_CLOCK_IP_UART1,
+    GLB_AHB_CLOCK_IP_UART2,
+    GLB_AHB_CLOCK_IP_UART3,
+    GLB_AHB_CLOCK_IP_UART4,
+    GLB_AHB_CLOCK_IP_SPI,
+    GLB_AHB_CLOCK_IP_I2C,
+    GLB_AHB_CLOCK_IP_PWM,
+    GLB_AHB_CLOCK_IP_TIMER,
+    GLB_AHB_CLOCK_IP_IR,
+    GLB_AHB_CLOCK_IP_CHECKSUM,
+    GLB_AHB_CLOCK_IP_QDEC,
+    GLB_AHB_CLOCK_IP_KYS,
+    GLB_AHB_CLOCK_IP_I2S,
+    GLB_AHB_CLOCK_IP_USB11,
+    GLB_AHB_CLOCK_IP_CAM,
+    GLB_AHB_CLOCK_IP_MJPEG,
+    GLB_AHB_CLOCK_IP_BT_BLE_NORMAL,
+    GLB_AHB_CLOCK_IP_BT_BLE_LP,
+    GLB_AHB_CLOCK_IP_ZB_NORMAL,
+    GLB_AHB_CLOCK_IP_ZB_LP,
+    GLB_AHB_CLOCK_IP_WIFI_NORMAL,
+    GLB_AHB_CLOCK_IP_WIFI_LP,
+    GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL,
+    GLB_AHB_CLOCK_IP_BT_BLE_2_LP,
+    GLB_AHB_CLOCK_IP_EMI_MISC,
+    GLB_AHB_CLOCK_IP_PSRAM0_CTRL,
+    GLB_AHB_CLOCK_IP_PSRAM1_CTRL,
+    GLB_AHB_CLOCK_IP_USB20,
+    GLB_AHB_CLOCK_IP_MIX2,
+    GLB_AHB_CLOCK_IP_AUDIO,
+    GLB_AHB_CLOCK_IP_SDH,
+} GLB_AHB_CLOCK_IP_Type;
+
+/*@} end of group GLB_Public_Types */
+
+/** @defgroup  GLB_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  GLB_ROOT_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_ROOT_CLK_TYPE(type) (((type) == GLB_ROOT_CLK_RC32M) || \
+                                    ((type) == GLB_ROOT_CLK_XTAL) ||  \
+                                    ((type) == GLB_ROOT_CLK_DLL))
+
+/** @defgroup  GLB_SYS_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SYS_CLK_TYPE(type) (((type) == GLB_SYS_CLK_RC32M) ||    \
+                                   ((type) == GLB_SYS_CLK_XTAL) ||     \
+                                   ((type) == GLB_SYS_CLK_DLL57P6M) || \
+                                   ((type) == GLB_SYS_CLK_DLL96M) ||   \
+                                   ((type) == GLB_SYS_CLK_DLL144M))
+
+/** @defgroup  GLB_CAM_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_CAM_CLK_TYPE(type) (((type) == GLB_CAM_CLK_XCLK) || \
+                                   ((type) == GLB_CAM_CLK_DLL96M))
+
+/** @defgroup  GLB_I2S_OUT_REF_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_I2S_OUT_REF_CLK_TYPE(type) (((type) == GLB_I2S_OUT_REF_CLK_NONE) || \
+                                           ((type) == GLB_I2S_OUT_REF_CLK_SRC))
+
+/** @defgroup  GLB_QDEC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_QDEC_CLK_TYPE(type) (((type) == GLB_QDEC_CLK_XCLK) || \
+                                    ((type) == GLB_QDEC_CLK_F32K))
+
+/** @defgroup  GLB_DMA_CLK_ID_TYPE
+ *  @{
+ */
+#define IS_GLB_DMA_CLK_ID_TYPE(type) (((type) == GLB_DMA_CLK_DMA0_CH0) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH1) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH2) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH3) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH4) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH5) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH6) || \
+                                      ((type) == GLB_DMA_CLK_DMA0_CH7))
+
+/** @defgroup  GLB_IR_CLK_SRC_TYPE
+ *  @{
+ */
+#define IS_GLB_IR_CLK_SRC_TYPE(type) (((type) == GLB_IR_CLK_SRC_XCLK))
+
+/** @defgroup  GLB_SFLASH_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_SFLASH_CLK_TYPE(type) (((type) == GLB_SFLASH_CLK_144M) ||  \
+                                      ((type) == GLB_SFLASH_CLK_XCLK) ||  \
+                                      ((type) == GLB_SFLASH_CLK_57P6M) || \
+                                      ((type) == GLB_SFLASH_CLK_72M) ||   \
+                                      ((type) == GLB_SFLASH_CLK_BCLK) ||  \
+                                      ((type) == GLB_SFLASH_CLK_96M))
+
+/** @defgroup  GLB_CHIP_CLK_OUT_TYPE
+ *  @{
+ */
+#define IS_GLB_CHIP_CLK_OUT_TYPE(type) (((type) == GLB_CHIP_CLK_OUT_NONE) ||          \
+                                        ((type) == GLB_CHIP_CLK_OUT_I2S_REF_CLK) ||   \
+                                        ((type) == GLB_CHIP_CLK_OUT_AUDIO_PLL_CLK) || \
+                                        ((type) == GLB_CHIP_CLK_OUT_XTAL_SOC_32M))
+
+/** @defgroup  GLB_ETH_REF_CLK_OUT_TYPE
+ *  @{
+ */
+#define IS_GLB_ETH_REF_CLK_OUT_TYPE(type) (((type) == GLB_ETH_REF_CLK_OUT_OUTSIDE_50M) || \
+                                           ((type) == GLB_ETH_REF_CLK_OUT_INSIDE_50M))
+
+/** @defgroup  GLB_SPI_PAD_ACT_AS_TYPE
+ *  @{
+ */
+#define IS_GLB_SPI_PAD_ACT_AS_TYPE(type) (((type) == GLB_SPI_PAD_ACT_AS_SLAVE) || \
+                                          ((type) == GLB_SPI_PAD_ACT_AS_MASTER))
+
+/** @defgroup  GLB_PKA_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_PKA_CLK_TYPE(type) (((type) == GLB_PKA_CLK_HCLK) || \
+                                   ((type) == GLB_PKA_CLK_DLL96M))
+
+/** @defgroup  BMX_ARB_TYPE
+ *  @{
+ */
+#define IS_BMX_ARB_TYPE(type) (((type) == BMX_ARB_FIX) ||         \
+                               ((type) == BMX_ARB_ROUND_ROBIN) || \
+                               ((type) == BMX_ARB_RANDOM))
+
+/** @defgroup  BMX_BUS_ERR_TYPE
+ *  @{
+ */
+#define IS_BMX_BUS_ERR_TYPE(type) (((type) == BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+                                   ((type) == BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup  BMX_ERR_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_ERR_INT_TYPE(type) (((type) == BMX_ERR_INT_ERR) || \
+                                   ((type) == BMX_ERR_INT_ALL))
+
+/** @defgroup  BMX_TO_INT_TYPE
+ *  @{
+ */
+#define IS_BMX_TO_INT_TYPE(type) (((type) == BMX_TO_INT_TIMEOUT) || \
+                                  ((type) == BMX_TO_INT_ALL))
+
+/** @defgroup  GLB_EM_TYPE
+ *  @{
+ */
+#define IS_GLB_EM_TYPE(type) (((type) == GLB_EM_0KB) || \
+                              ((type) == GLB_EM_8KB) || \
+                              ((type) == GLB_EM_16KB))
+
+/** @defgroup  GLB_EMAC_CAM_PIN_TYPE
+ *  @{
+ */
+#define IS_GLB_EMAC_CAM_PIN_TYPE(type) (((type) == GLB_EMAC_CAM_PIN_EMAC) || \
+                                        ((type) == GLB_EMAC_CAM_PIN_CAM))
+
+/** @defgroup  GLB_MTIMER_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_MTIMER_CLK_TYPE(type) (((type) == GLB_MTIMER_CLK_BCLK) || \
+                                      ((type) == GLB_MTIMER_CLK_32K))
+
+/** @defgroup  GLB_ADC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_ADC_CLK_TYPE(type) (((type) == GLB_ADC_CLK_AUDIO_PLL) || \
+                                   ((type) == GLB_ADC_CLK_XCLK))
+
+/** @defgroup  GLB_DAC_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DAC_CLK_TYPE(type) (((type) == GLB_DAC_CLK_PLL_32M) || \
+                                   ((type) == GLB_DAC_CLK_XCLK) ||    \
+                                   ((type) == GLB_DAC_CLK_AUDIO_PLL))
+
+/** @defgroup  GLB_DIG_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DIG_CLK_TYPE(type) (((type) == GLB_DIG_CLK_PLL_32M) || \
+                                   ((type) == GLB_DIG_CLK_XCLK) ||    \
+                                   ((type) == GLB_DIG_CLK_AUDIO_PLL))
+
+/** @defgroup  GLB_BT_BANDWIDTH_TYPE
+ *  @{
+ */
+#define IS_GLB_BT_BANDWIDTH_TYPE(type) (((type) == GLB_BT_BANDWIDTH_1M) || \
+                                        ((type) == GLB_BT_BANDWIDTH_2M))
+
+/** @defgroup  GLB_UART_SIG_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_TYPE(type) (((type) == GLB_UART_SIG_0) || \
+                                    ((type) == GLB_UART_SIG_1) || \
+                                    ((type) == GLB_UART_SIG_2) || \
+                                    ((type) == GLB_UART_SIG_3) || \
+                                    ((type) == GLB_UART_SIG_4) || \
+                                    ((type) == GLB_UART_SIG_5) || \
+                                    ((type) == GLB_UART_SIG_6) || \
+                                    ((type) == GLB_UART_SIG_7))
+
+/** @defgroup  GLB_UART_SIG_FUN_TYPE
+ *  @{
+ */
+#define IS_GLB_UART_SIG_FUN_TYPE(type) (((type) == GLB_UART_SIG_FUN_UART0_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART0_RXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_CTS) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_TXD) || \
+                                        ((type) == GLB_UART_SIG_FUN_UART1_RXD))
+
+/** @defgroup  GLB_DLL_CLK_TYPE
+ *  @{
+ */
+#define IS_GLB_DLL_CLK_TYPE(type) (((type) == GLB_DLL_CLK_57P6M) || \
+                                   ((type) == GLB_DLL_CLK_96M) ||   \
+                                   ((type) == GLB_DLL_CLK_144M) ||  \
+                                   ((type) == GLB_DLL_CLK_288M) ||  \
+                                   ((type) == GLB_DLL_CLK_MMDIV))
+
+/** @defgroup  GLB_GPIO_INT_TRIG_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_INT_TRIG_TYPE(type) (((type) == GLB_GPIO_INT_TRIG_NEG_PULSE) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_POS_PULSE) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_NEG_LEVEL) || \
+                                         ((type) == GLB_GPIO_INT_TRIG_POS_LEVEL))
+
+/** @defgroup  GLB_GPIO_INT_CONTROL_TYPE
+ *  @{
+ */
+#define IS_GLB_GPIO_INT_CONTROL_TYPE(type) (((type) == GLB_GPIO_INT_CONTROL_SYNC) || \
+                                            ((type) == GLB_GPIO_INT_CONTROL_ASYNC))
+
+/** @defgroup  GLB_DLL_XTAL_TYPE
+ *  @{
+ */
+#define IS_GLB_DLL_XTAL_TYPE(type) (((type) == GLB_DLL_XTAL_NONE) || \
+                                    ((type) == GLB_DLL_XTAL_32M) ||  \
+                                    ((type) == GLB_DLL_XTAL_RC32M))
+
+/*@} end of group GLB_Public_Constants */
+
+/** @defgroup  GLB_Public_Macros
+ *  @{
+ */
+#define UART_SIG_SWAP_GPIO0_GPIO7   0x01 /* GPIO0-7   uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_GPIO8_GPIO15  0x02 /* GPIO8-15  uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_GPIO16_GPIO22 0x04 /* GPIO16-22 uart_sig[0:7] -> uart_sig[4:7], uart_sig[0:3] */
+#define UART_SIG_SWAP_NONE          0x00 /* GPIO0-22  uart_sig[0:7] <- uart_sig[4:7], uart_sig[0:3] */
+#define JTAG_SIG_SWAP_GPIO0_GPIO3   0x01 /* GPIO0-3   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO4_GPIO7   0x02 /* GPIO4-7   E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO8_GPIO11  0x04 /* GPIO8-11  E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO12_GPIO15 0x08 /* GPIO12-15 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO16_GPIO19 0x10 /* GPIO16-19 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_GPIO20_GPIO22 0x20 /* GPIO20-22 E21_TMS/E21_TDI/E21_TCK/E21_TDO -> E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+#define JTAG_SIG_SWAP_NONE          0x00 /* GPIO0-22  E21_TMS/E21_TDI/E21_TCK/E21_TDO <- E21_TCK/E21_TDO/E21_TMS/E21_TDI */
+
+#define GLB_AHB_CLOCK_CPU             (0x0000000000000001UL)
+#define GLB_AHB_CLOCK_SDU             (0x0000000000000002UL)
+#define GLB_AHB_CLOCK_SEC             (0x0000000000000004UL)
+#define GLB_AHB_CLOCK_DMA_0           (0x0000000000000008UL)
+#define GLB_AHB_CLOCK_DMA_1           (0x0000000000000010UL)
+#define GLB_AHB_CLOCK_DMA_2           (0x0000000000000020UL)
+#define GLB_AHB_CLOCK_CCI             (0x0000000000000040UL)
+#define GLB_AHB_CLOCK_RF_TOP          (0x0000000000000080UL)
+#define GLB_AHB_CLOCK_GPIP            (0x0000000000000100UL)
+#define GLB_AHB_CLOCK_TZC             (0x0000000000000200UL)
+#define GLB_AHB_CLOCK_EF_CTRL         (0x0000000000000400UL)
+#define GLB_AHB_CLOCK_SF_CTRL         (0x0000000000000800UL)
+#define GLB_AHB_CLOCK_EMAC            (0x0000000000001000UL)
+#define GLB_AHB_CLOCK_UART0           (0x0000000000002000UL)
+#define GLB_AHB_CLOCK_UART1           (0x0000000000004000UL)
+#define GLB_AHB_CLOCK_UART2           (0x0000000000008000UL)
+#define GLB_AHB_CLOCK_UART3           (0x0000000000010000UL)
+#define GLB_AHB_CLOCK_UART4           (0x0000000000020000UL)
+#define GLB_AHB_CLOCK_SPI             (0x0000000000040000UL)
+#define GLB_AHB_CLOCK_I2C             (0x0000000000080000UL)
+#define GLB_AHB_CLOCK_PWM             (0x0000000000100000UL)
+#define GLB_AHB_CLOCK_TIMER           (0x0000000000200000UL)
+#define GLB_AHB_CLOCK_IR              (0x0000000000400000UL)
+#define GLB_AHB_CLOCK_CHECKSUM        (0x0000000000800000UL)
+#define GLB_AHB_CLOCK_QDEC            (0x0000000001000000UL)
+#define GLB_AHB_CLOCK_KYS             (0x0000000002000000UL)
+#define GLB_AHB_CLOCK_I2S             (0x0000000004000000UL)
+#define GLB_AHB_CLOCK_USB11           (0x0000000008000000UL)
+#define GLB_AHB_CLOCK_CAM             (0x0000000010000000UL)
+#define GLB_AHB_CLOCK_MJPEG           (0x0000000020000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_NORMAL   (0x0000000040000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_LP       (0x0000000080000000UL)
+#define GLB_AHB_CLOCK_ZB_NORMAL       (0x0000000100000000UL)
+#define GLB_AHB_CLOCK_ZB_LP           (0x0000000200000000UL)
+#define GLB_AHB_CLOCK_WIFI_NORMAL     (0x0000000400000000UL)
+#define GLB_AHB_CLOCK_WIFI_LP         (0x0000000800000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_2_NORMAL (0x0000001000000000UL)
+#define GLB_AHB_CLOCK_BT_BLE_2_LP     (0x0000002000000000UL)
+#define GLB_AHB_CLOCK_EMI_MISC        (0x0000004000000000UL)
+#define GLB_AHB_CLOCK_PSRAM0_CTRL     (0x0000008000000000UL)
+#define GLB_AHB_CLOCK_PSRAM1_CTRL     (0x0000010000000000UL)
+#define GLB_AHB_CLOCK_USB20           (0x0000020000000000UL)
+#define GLB_AHB_CLOCK_MIX2            (0x0000040000000000UL)
+#define GLB_AHB_CLOCK_AUDIO           (0x0000080000000000UL)
+#define GLB_AHB_CLOCK_SDH             (0x0000100000000000UL)
+
+/*@} end of group GLB_Public_Macros */
+
+/** @defgroup  GLB_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_ERR_IRQHandler(void);
+void BMX_TO_IRQHandler(void);
+void GPIO_INT0_IRQHandler(void);
+#endif
+/*----------*/
+GLB_ROOT_CLK_Type GLB_Get_Root_CLK_Sel(void);
+BL_Err_Type GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv);
+uint8_t GLB_Get_BCLK_Div(void);
+uint8_t GLB_Get_HCLK_Div(void);
+BL_Err_Type Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType);
+BL_Err_Type GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq);
+BL_Err_Type System_Core_Clock_Update_From_RC32M(void);
+/*----------*/
+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef);
+BL_Err_Type GLB_Set_USB_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk);
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel);
+BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel);
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div);
+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable);
+BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div);
+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable);
+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable);
+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel);
+/*----------*/
+BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel);
+BL_Err_Type GLB_SW_System_Reset(void);
+BL_Err_Type GLB_SW_CPU_Reset(void);
+BL_Err_Type GLB_SW_POR_Reset(void);
+BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1);
+BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1);
+uint64_t GLB_PER_Clock_Gate_Status_Get(void);
+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips);
+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips);
+/*----------*/
+BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg);
+BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void);
+BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void);
+BL_Err_Type GLB_BMX_BusErrResponse_Enable(void);
+BL_Err_Type GLB_BMX_BusErrResponse_Disable(void);
+BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType);
+uint32_t GLB_BMX_Get_Err_Addr(void);
+BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value);
+uint32_t GLB_Get_SRAM_RET(void);
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value);
+uint32_t GLB_Get_SRAM_SLP(void);
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value);
+uint32_t GLB_Get_SRAM_PARM(void);
+/*----------*/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType);
+/*----------*/
+BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType);
+BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable);
+BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable);
+BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel);
+BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel);
+BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable);
+BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable);
+BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState);
+BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod);
+BL_Err_Type GLB_Select_Internal_Flash(void);
+BL_Err_Type GLB_Select_External_Flash(void);
+BL_Err_Type GLB_Deswap_Flash_Pin(void);
+BL_Err_Type GLB_Swap_Flash_CS_IO2_Pin();
+BL_Err_Type GLB_Swap_Flash_IO0_IO3_Pin();
+BL_Err_Type GLB_Swap_Flash_Pin(void);
+BL_Err_Type GLB_Select_Internal_PSram(void);
+/*----------*/
+BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div);
+/*----------*/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div);
+/*----------*/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel);
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div);
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div);
+/*----------*/
+BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth,
+                                   uint8_t pti, uint8_t channel);
+/*----------*/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun);
+/*----------*/
+BL_Err_Type GLB_Power_Off_DLL(void);
+BL_Err_Type GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType);
+BL_Err_Type GLB_Enable_DLL_All_Clks(void);
+BL_Err_Type GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk);
+BL_Err_Type GLB_Disable_DLL_All_Clks(void);
+BL_Err_Type GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk);
+/*----------*/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio);
+BL_Err_Type GLB_IR_LED_Driver_Enable(void);
+BL_Err_Type GLB_IR_LED_Driver_Disable(void);
+BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio);
+BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio);
+BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias);
+/*----------*/
+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg);
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt);
+BL_Err_Type GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Set_Flash_Pad_HZ(void);
+BL_Err_Type GLB_Set_Psram_Pad_HZ(void);
+uint8_t GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val);
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
+BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear);
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod,
+                                GLB_GPIO_INT_TRIG_Type intTrgMod);
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask);
+BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear);
+BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod,
+                                 GLB_GPIO_INT_TRIG_Type intTrgMod);
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin);
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void);
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
+BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun);
+/*----------*/;
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_GLB_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_gpio.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_gpio.h
new file mode 100755
index 0000000000..59eee9d809
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_gpio.h
@@ -0,0 +1,952 @@
+/**
+
+  ******************************************************************************
+
+  * @file    bl702_gpio.h
+
+  * @version V1.2
+
+  * @date    2020-09-04
+
+  * @brief   This file is the description of.IP register
+
+  ******************************************************************************
+
+  * @attention
+
+  *
+
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+
+  *
+
+  * Redistribution and use in source and binary forms, with or without modification,
+
+  * are permitted provided that the following conditions are met:
+
+  *   1. Redistributions of source code must retain the above copyright notice,
+
+  *      this list of conditions and the following disclaimer.
+
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+
+  *      this list of conditions and the following disclaimer in the documentation
+
+  *      and/or other materials provided with the distribution.
+
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+
+  *      may be used to endorse or promote products derived from this software
+
+  *      without specific prior written permission.
+
+  *
+
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+
+  *
+
+  ******************************************************************************
+
+  */
+
+#ifndef __BL702_GPIO_H__
+#define __BL702_GPIO_H__
+
+typedef enum {
+    GLB_GPIO_PIN_0 = 0,
+    GLB_GPIO_PIN_1,
+    GLB_GPIO_PIN_2,
+    GLB_GPIO_PIN_3,
+    GLB_GPIO_PIN_4,
+    GLB_GPIO_PIN_5,
+    GLB_GPIO_PIN_6,
+    GLB_GPIO_PIN_7,
+    GLB_GPIO_PIN_8,
+    GLB_GPIO_PIN_9,
+    GLB_GPIO_PIN_10,
+    GLB_GPIO_PIN_11,
+    GLB_GPIO_PIN_12,
+    GLB_GPIO_PIN_13,
+    GLB_GPIO_PIN_14,
+    GLB_GPIO_PIN_15,
+    GLB_GPIO_PIN_16,
+    GLB_GPIO_PIN_17,
+    GLB_GPIO_PIN_18,
+    GLB_GPIO_PIN_19,
+    GLB_GPIO_PIN_20,
+    GLB_GPIO_PIN_21,
+    GLB_GPIO_PIN_22,
+    GLB_GPIO_PIN_23,
+    GLB_GPIO_PIN_24,
+    GLB_GPIO_PIN_25,
+    GLB_GPIO_PIN_26,
+    GLB_GPIO_PIN_27,
+    GLB_GPIO_PIN_28,
+    GLB_GPIO_PIN_29,
+    GLB_GPIO_PIN_30,
+    GLB_GPIO_PIN_31,
+    GLB_GPIO_PIN_MAX,
+} GLB_GPIO_Type;
+
+#define GPIO_MODE_INPUT  ((uint32_t)0x00000000U) /*!< Input Floating Mode                   */
+#define GPIO_MODE_OUTPUT ((uint32_t)0x00000001U) /*!< Output Push Pull Mode                 */
+#define GPIO_MODE_AF     ((uint32_t)0x00000002U) /*!< Alternate function                    */
+#define GPIO_MODE_ANALOG ((uint32_t)0x00000003U) /*!< Analog function                       */
+#define GPIO_PULL_UP     ((uint32_t)0x00000000U) /*!< GPIO pull up                          */
+#define GPIO_PULL_DOWN   ((uint32_t)0x00000001U) /*!< GPIO pull down                        */
+#define GPIO_PULL_NONE   ((uint32_t)0x00000002U) /*!< GPIO no pull up or down               */
+
+typedef enum {
+    GPIO_FUN_CLK_OUT = 0,
+    GPIO_FUN_BT_COEXIST = 1,
+    GPIO_FUN_FLASH_PSRAM = 2,
+    GPIO_FUN_QSPI = 2,
+    GPIO_FUN_I2S = 3,
+    GPIO_FUN_SPI = 4,
+    GPIO_FUN_I2C = 6,
+    GPIO_FUN_UART = 7,
+    GPIO_FUN_PWM = 8,
+    GPIO_FUN_CAM = 9,
+    GPIO_FUN_ANALOG = 10,
+    GPIO_FUN_GPIO = 11,
+    GPIO_FUN_RF_TEST = 12,
+    GPIO_FUN_SCAN = 13,
+    GPIO_FUN_E21_JTAG = 14,
+    GPIO_FUN_DEBUG = 15,
+    GPIO_FUN_EXTERNAL_PA = 16,
+    GPIO_FUN_USB_TRANCEIVER = 17,
+    GPIO_FUN_USB_CONTROLLER = 18,
+    GPIO_FUN_ETHER_MAC = 19,
+    GPIO_FUN_EMAC = 19,
+    GPIO_FUN_QDEC = 20,
+    GPIO_FUN_KEY_SCAN_IN = 21,
+    GPIO_FUN_KEY_SCAN_ROW = 21,
+    GPIO_FUN_KEY_SCAN_DRIVE = 22,
+    GPIO_FUN_KEY_SCAN_COL = 22,
+    GPIO_FUN_CAM_MISC = 23,
+    GPIO_FUN_USB = 0xD0,
+    GPIO_FUN_DAC = 0xD1,
+    GPIO_FUN_ADC = 0xD2,
+    GPIO_FUN_QDEC_LED = 0xD3,
+    GPIO_FUN_GPIO_OUTPUT_UP = 0xE0,
+    GPIO_FUN_GPIO_OUTPUT_DOWN = 0xE1,
+    GPIO_FUN_GPIO_OUTPUT_NONE = 0xE2,
+    GPIO_FUN_GPIO_INPUT_UP = 0xE3,
+    GPIO_FUN_GPIO_INPUT_DOWN = 0xE4,
+    GPIO_FUN_GPIO_INPUT_NONE = 0xE5,
+    GPIO_FUN_GPIO_EXTI_RISING_EDGE = 0xE6,
+    GPIO_FUN_GPIO_EXTI_FALLING_EDGE = 0xE7,
+    GPIO_FUN_GPIO_EXTI_HIGH_LEVEL = 0xE8,
+    GPIO_FUN_GPIO_EXTI_LOW_LEVEL = 0xE9,
+    GPIO_FUN_UART0_RTS = 0xF0,
+    GPIO_FUN_UART0_CTS = 0xF1,
+    GPIO_FUN_UART0_TX = 0xF2,
+    GPIO_FUN_UART0_RX = 0xF3,
+    GPIO_FUN_UART1_RTS = 0xF4,
+    GPIO_FUN_UART1_CTS = 0xF5,
+    GPIO_FUN_UART1_TX = 0xF6,
+    GPIO_FUN_UART1_RX = 0xF7,
+    GPIO_FUN_WAKEUP = 0xFE,
+    GPIO_FUN_UNUSED = 0xFF
+} GLB_GPIO_FUNC_Type;
+
+typedef struct
+{
+    uint8_t gpioPin;
+    uint8_t gpioFun;
+    uint8_t gpioMode;
+    uint8_t pullType;
+    uint8_t drive;
+    uint8_t smtCtrl;
+} GLB_GPIO_Cfg_Type;
+
+/* GPIO0 function definition */
+#define GPIO0_FUN_CLK_OUT_0             0
+#define GPIO0_FUN_BT_ABORT              1
+#define GPIO0_FUN_UNUSED2               2
+#define GPIO0_FUN_I2S0_BCLK             3
+#define GPIO0_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO0_FUN_I2C0_SCL              6
+#define GPIO0_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO0_FUN_PWM_CH0               8
+#define GPIO0_FUN_PIX_CLK               9
+#define GPIO0_FUN_UNUSED10              10
+#define GPIO0_FUN_REG_GPIO_0            11
+#define GPIO0_FUN_UNUSED12              12
+#define GPIO0_FUN_SCAN_IN_0             13
+#define GPIO0_FUN_E21_TMS_E21_TCK       14
+#define GPIO0_FUN_S_CCI_CLK             15
+#define GPIO0_FUN_FEM_GPIO_0            16
+#define GPIO0_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO0_FUN_USB_SUS               18
+#define GPIO0_FUN_MII_REF_CLK           19
+#define GPIO0_FUN_QDEC0_A               20
+#define GPIO0_FUN_ROW_I_0               21
+#define GPIO0_FUN_COL_O_0               22
+#define GPIO0_FUN_CAM_PWRDN             23
+/* GPIO1 function definition */
+#define GPIO1_FUN_CLK_OUT_1             0
+#define GPIO1_FUN_BT_ACTIVE             1
+#define GPIO1_FUN_UNUSED2               2
+#define GPIO1_FUN_I2S0_FS               3
+#define GPIO1_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO1_FUN_I2C0_SDA              6
+#define GPIO1_FUN_UART_SIG1_UART_SIG5   7
+#define GPIO1_FUN_PWM_CH1               8
+#define GPIO1_FUN_FRAME_VLD             9
+#define GPIO1_FUN_UNUSED10              10
+#define GPIO1_FUN_REG_GPIO_1            11
+#define GPIO1_FUN_UNUSED12              12
+#define GPIO1_FUN_SCAN_IN_1             13
+#define GPIO1_FUN_E21_TDI_E21_TDO       14
+#define GPIO1_FUN_S_CCI_CS              15
+#define GPIO1_FUN_FEM_GPIO_1            16
+#define GPIO1_FUN_USB_TX_OE             17
+#define GPIO1_FUN_USB_ENUM              18
+#define GPIO1_FUN_MII_TXD_0             19
+#define GPIO1_FUN_QDEC0_B               20
+#define GPIO1_FUN_ROW_I_1               21
+#define GPIO1_FUN_COL_O_1               22
+#define GPIO1_FUN_CAM_REF_CLK           23
+/* GPIO2 function definition */
+#define GPIO2_FUN_CLK_OUT_0           0
+#define GPIO2_FUN_BT_PRI              1
+#define GPIO2_FUN_UNUSED2             2
+#define GPIO2_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO2_FUN_SPI_0_SS            4
+#define GPIO2_FUN_I2C0_SCL            6
+#define GPIO2_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO2_FUN_PWM_CH2             8
+#define GPIO2_FUN_LINE_VLD            9
+#define GPIO2_FUN_UNUSED10            10
+#define GPIO2_FUN_REG_GPIO_2          11
+#define GPIO2_FUN_UNUSED12            12
+#define GPIO2_FUN_SCAN_IN_2           13
+#define GPIO2_FUN_E21_TCK_E21_TMS     14
+#define GPIO2_FUN_S_CCI_DATA_0        15
+#define GPIO2_FUN_FEM_GPIO_2          16
+#define GPIO2_FUN_USB_TX_DP_USB_RX_DP 17
+#define GPIO2_FUN_USB_OEB             18
+#define GPIO2_FUN_MII_TXD_1           19
+#define GPIO2_FUN_QDEC0_LED           20
+#define GPIO2_FUN_ROW_I_2             21
+#define GPIO2_FUN_COL_O_2             22
+#define GPIO2_FUN_CAM_RESET           23
+/* GPIO3 function definition */
+#define GPIO3_FUN_CLK_OUT_1           0
+#define GPIO3_FUN_BT_ABORT            1
+#define GPIO3_FUN_UNUSED2             2
+#define GPIO3_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO3_FUN_SPI_0_SCLK          4
+#define GPIO3_FUN_I2C0_SDA            6
+#define GPIO3_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO3_FUN_PWM_CH3             8
+#define GPIO3_FUN_PIX_DAT0            9
+#define GPIO3_FUN_UNUSED10            10
+#define GPIO3_FUN_REG_GPIO_3          11
+#define GPIO3_FUN_RF_TEST_0           12
+#define GPIO3_FUN_UNUSED13            13
+#define GPIO3_FUN_E21_TDO_E21_TDI     14
+#define GPIO3_FUN_DEBUG_0             15
+#define GPIO3_FUN_FEM_GPIO_3          16
+#define GPIO3_FUN_USB_SUS_EXT         17
+#define GPIO3_FUN_VOP                 18
+#define GPIO3_FUN_UNUSED19            19
+#define GPIO3_FUN_QDEC1_A             20
+#define GPIO3_FUN_ROW_I_3             21
+#define GPIO3_FUN_COL_O_3             22
+#define GPIO3_FUN_CAM_PWRDN           23
+/* GPIO4 function definition */
+#define GPIO4_FUN_CLK_OUT_0             0
+#define GPIO4_FUN_BT_ACTIVE             1
+#define GPIO4_FUN_UNUSED2               2
+#define GPIO4_FUN_I2S0_BCLK             3
+#define GPIO4_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO4_FUN_I2C0_SCL              6
+#define GPIO4_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO4_FUN_PWM_CH4               8
+#define GPIO4_FUN_PIX_DAT1              9
+#define GPIO4_FUN_UNUSED10              10
+#define GPIO4_FUN_REG_GPIO_4            11
+#define GPIO4_FUN_RF_TEST_1             12
+#define GPIO4_FUN_UNUSED13              13
+#define GPIO4_FUN_E21_TMS_E21_TCK       14
+#define GPIO4_FUN_DEBUG_1               15
+#define GPIO4_FUN_FEM_GPIO_4            16
+#define GPIO4_FUN_USB_ENUM_EXT          17
+#define GPIO4_FUN_VOM                   18
+#define GPIO4_FUN_UNUSED19              19
+#define GPIO4_FUN_QDEC1_B               20
+#define GPIO4_FUN_ROW_I_4               21
+#define GPIO4_FUN_COL_O_4               22
+#define GPIO4_FUN_CAM_REF_CLK           23
+/* GPIO5 function definition */
+#define GPIO5_FUN_CLK_OUT_1             0
+#define GPIO5_FUN_BT_PRI                1
+#define GPIO5_FUN_UNUSED2               2
+#define GPIO5_FUN_I2S0_FS               3
+#define GPIO5_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO5_FUN_I2C0_SDA              6
+#define GPIO5_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO5_FUN_PWM_CH0               8
+#define GPIO5_FUN_PIX_DAT2              9
+#define GPIO5_FUN_UNUSED10              10
+#define GPIO5_FUN_REG_GPIO_5            11
+#define GPIO5_FUN_RF_TEST_2             12
+#define GPIO5_FUN_UNUSED13              13
+#define GPIO5_FUN_E21_TDI_E21_TDO       14
+#define GPIO5_FUN_DEBUG_2               15
+#define GPIO5_FUN_FEM_GPIO_0            16
+#define GPIO5_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO5_FUN_BD                    18
+#define GPIO5_FUN_UNUSED19              19
+#define GPIO5_FUN_QDEC1_LED             20
+#define GPIO5_FUN_ROW_I_5               21
+#define GPIO5_FUN_COL_O_5               22
+#define GPIO5_FUN_CAM_RESET             23
+/* GPIO6 function definition */
+#define GPIO6_FUN_CLK_OUT_0           0
+#define GPIO6_FUN_BT_ABORT            1
+#define GPIO6_FUN_UNUSED2             2
+#define GPIO6_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO6_FUN_SPI_0_SS            4
+#define GPIO6_FUN_I2C0_SCL            6
+#define GPIO6_FUN_UART_SIG6_UART_SIG2 7
+#define GPIO6_FUN_PWM_CH1             8
+#define GPIO6_FUN_PIX_DAT3            9
+#define GPIO6_FUN_UNUSED10            10
+#define GPIO6_FUN_REG_GPIO_6          11
+#define GPIO6_FUN_RF_TEST_3           12
+#define GPIO6_FUN_UNUSED13            13
+#define GPIO6_FUN_E21_TCK_E21_TMS     14
+#define GPIO6_FUN_DEBUG_3             15
+#define GPIO6_FUN_FEM_GPIO_1          16
+#define GPIO6_FUN_USB_TX_OE           17
+#define GPIO6_FUN_VIP                 18
+#define GPIO6_FUN_UNUSED19            19
+#define GPIO6_FUN_QDEC2_A             20
+#define GPIO6_FUN_ROW_I_6             21
+#define GPIO6_FUN_COL_O_6             22
+#define GPIO6_FUN_CAM_PWRDN           23
+/* GPIO7 function definition */
+#define GPIO7_FUN_CLK_OUT_1                       0
+#define GPIO7_FUN_BT_ACTIVE                       1
+#define GPIO7_FUN_UNUSED2                         2
+#define GPIO7_FUN_I2S0_RCLK_O_I2S0_DI             3
+#define GPIO7_FUN_SPI_0_SCLK                      4
+#define GPIO7_FUN_I2C0_SDA                        6
+#define GPIO7_FUN_UART_SIG7_UART_SIG3             7
+#define GPIO7_FUN_PWM_CH2                         8
+#define GPIO7_FUN_UNUSED9                         9
+#define GPIO7_FUN_USB_DP_GPIP_CH_6_GPDAC_VREF_EXT 10
+#define GPIO7_FUN_REG_GPIO_7                      11
+#define GPIO7_FUN_UNUSED12                        12
+#define GPIO7_FUN_SCAN_RSTB                       13
+#define GPIO7_FUN_E21_TDO_E21_TDI                 14
+#define GPIO7_FUN_S_CCI_DATA_1                    15
+#define GPIO7_FUN_FEM_GPIO_2                      16
+#define GPIO7_FUN_USB_TX_DP_USB_RX_DP             17
+#define GPIO7_FUN_VIM                             18
+#define GPIO7_FUN_MII_RXD_0                       19
+#define GPIO7_FUN_QDEC2_B                         20
+#define GPIO7_FUN_ROW_I_7                         21
+#define GPIO7_FUN_COL_O_7                         22
+#define GPIO7_FUN_CAM_REF_CLK                     23
+/* GPIO8 function definition */
+#define GPIO8_FUN_CLK_OUT_0             0
+#define GPIO8_FUN_BT_PRI                1
+#define GPIO8_FUN_UNUSED2               2
+#define GPIO8_FUN_I2S0_BCLK             3
+#define GPIO8_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO8_FUN_I2C0_SCL              6
+#define GPIO8_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO8_FUN_PWM_CH3               8
+#define GPIO8_FUN_UNUSED9               9
+#define GPIO8_FUN_USB_DM_GPIP_CH_0      10
+#define GPIO8_FUN_REG_GPIO_8            11
+#define GPIO8_FUN_RF_TEST_4             12
+#define GPIO8_FUN_SCAN_CLK              13
+#define GPIO8_FUN_E21_TMS_E21_TCK       14
+#define GPIO8_FUN_DEBUG_4               15
+#define GPIO8_FUN_FEM_GPIO_3            16
+#define GPIO8_FUN_USB_SUS_EXT           17
+#define GPIO8_FUN_RCV                   18
+#define GPIO8_FUN_MII_RXD_1             19
+#define GPIO8_FUN_QDEC2_LED             20
+#define GPIO8_FUN_ROW_I_0               21
+#define GPIO8_FUN_COL_O_8               22
+#define GPIO8_FUN_CAM_RESET             23
+/* GPIO9 function definition */
+#define GPIO9_FUN_CLK_OUT_1                         0
+#define GPIO9_FUN_BT_ABORT                          1
+#define GPIO9_FUN_UNUSED2                           2
+#define GPIO9_FUN_I2S0_FS                           3
+#define GPIO9_FUN_SPI_0_MISO_SPI_0_MOSI             4
+#define GPIO9_FUN_I2C0_SDA                          6
+#define GPIO9_FUN_UART_SIG1_UART_SIG5               7
+#define GPIO9_FUN_PWM_CH4                           8
+#define GPIO9_FUN_UNUSED9                           9
+#define GPIO9_FUN_PMIP_DC_TP_CLKPLL_DC_TP_GPIP_CH_7 10
+#define GPIO9_FUN_REG_GPIO_9                        11
+#define GPIO9_FUN_RF_TEST_5                         12
+#define GPIO9_FUN_SCAN_EN                           13
+#define GPIO9_FUN_E21_TDI_E21_TDO                   14
+#define GPIO9_FUN_DEBUG_5                           15
+#define GPIO9_FUN_FEM_GPIO_4                        16
+#define GPIO9_FUN_USB_ENUM_EXT                      17
+#define GPIO9_FUN_USB_SUS                           18
+#define GPIO9_FUN_UNUSED19                          19
+#define GPIO9_FUN_QDEC0_A                           20
+#define GPIO9_FUN_ROW_I_1                           21
+#define GPIO9_FUN_COL_O_9                           22
+#define GPIO9_FUN_CAM_PWRDN                         23
+/* GPIO10 function definition */
+#define GPIO10_FUN_CLK_OUT_0           0
+#define GPIO10_FUN_BT_ACTIVE           1
+#define GPIO10_FUN_UNUSED2             2
+#define GPIO10_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO10_FUN_SPI_0_SS            4
+#define GPIO10_FUN_I2C0_SCL            6
+#define GPIO10_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO10_FUN_PWM_CH0             8
+#define GPIO10_FUN_UNUSED9             9
+#define GPIO10_FUN_MICBIAS             10
+#define GPIO10_FUN_REG_GPIO_10         11
+#define GPIO10_FUN_RF_TEST_6           12
+#define GPIO10_FUN_UNUSED13            13
+#define GPIO10_FUN_E21_TCK_E21_TMS     14
+#define GPIO10_FUN_DEBUG_6             15
+#define GPIO10_FUN_FEM_GPIO_0          16
+#define GPIO10_FUN_USB_TX_DN_USB_RX_DN 17
+#define GPIO10_FUN_USB_ENUM            18
+#define GPIO10_FUN_UNUSED19            19
+#define GPIO10_FUN_QDEC0_B             20
+#define GPIO10_FUN_ROW_I_2             21
+#define GPIO10_FUN_COL_O_10            22
+#define GPIO10_FUN_CAM_REF_CLK         23
+/* GPIO11 function definition */
+#define GPIO11_FUN_CLK_OUT_1           0
+#define GPIO11_FUN_BT_PRI              1
+#define GPIO11_FUN_UNUSED2             2
+#define GPIO11_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO11_FUN_SPI_0_SCLK          4
+#define GPIO11_FUN_I2C0_SDA            6
+#define GPIO11_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO11_FUN_PWM_CH1             8
+#define GPIO11_FUN_UNUSED9             9
+#define GPIO11_FUN_GPIP_CH_3           10
+#define GPIO11_FUN_REG_GPIO_11         11
+#define GPIO11_FUN_RF_TEST_7           12
+#define GPIO11_FUN_UNUSED13            13
+#define GPIO11_FUN_E21_TDO_E21_TDI     14
+#define GPIO11_FUN_DEBUG_7             15
+#define GPIO11_FUN_FEM_GPIO_1          16
+#define GPIO11_FUN_USB_TX_OE           17
+#define GPIO11_FUN_USB_OEB             18
+#define GPIO11_FUN_UNUSED19            19
+#define GPIO11_FUN_QDEC0_LED           20
+#define GPIO11_FUN_ROW_I_3             21
+#define GPIO11_FUN_COL_O_11            22
+#define GPIO11_FUN_CAM_RESET           23
+/* GPIO12 function definition */
+#define GPIO12_FUN_CLK_OUT_0             0
+#define GPIO12_FUN_BT_ABORT              1
+#define GPIO12_FUN_UNUSED2               2
+#define GPIO12_FUN_I2S0_BCLK             3
+#define GPIO12_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO12_FUN_I2C0_SCL              6
+#define GPIO12_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO12_FUN_PWM_CH2               8
+#define GPIO12_FUN_PIX_DAT4              9
+#define GPIO12_FUN_GPIP_CH_4             10
+#define GPIO12_FUN_REG_GPIO_12           11
+#define GPIO12_FUN_RF_TEST_8             12
+#define GPIO12_FUN_UNUSED13              13
+#define GPIO12_FUN_E21_TMS_E21_TCK       14
+#define GPIO12_FUN_DEBUG_8               15
+#define GPIO12_FUN_FEM_GPIO_2            16
+#define GPIO12_FUN_USB_TX_DP_USB_RX_DP   17
+#define GPIO12_FUN_VOP                   18
+#define GPIO12_FUN_UNUSED19              19
+#define GPIO12_FUN_QDEC1_A               20
+#define GPIO12_FUN_ROW_I_4               21
+#define GPIO12_FUN_COL_O_12              22
+#define GPIO12_FUN_CAM_PWRDN             23
+/* GPIO13 function definition */
+#define GPIO13_FUN_CLK_OUT_1             0
+#define GPIO13_FUN_BT_ACTIVE             1
+#define GPIO13_FUN_UNUSED2               2
+#define GPIO13_FUN_I2S0_FS               3
+#define GPIO13_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO13_FUN_I2C0_SDA              6
+#define GPIO13_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO13_FUN_PWM_CH3               8
+#define GPIO13_FUN_UNUSED9               9
+#define GPIO13_FUN_UNUSED10              10
+#define GPIO13_FUN_REG_GPIO_13           11
+#define GPIO13_FUN_UNUSED12              12
+#define GPIO13_FUN_UNUSED13              13
+#define GPIO13_FUN_E21_TDI_E21_TDO       14
+#define GPIO13_FUN_DEBUG_9               15
+#define GPIO13_FUN_FEM_GPIO_3            16
+#define GPIO13_FUN_USB_SUS_EXT           17
+#define GPIO13_FUN_VOM                   18
+#define GPIO13_FUN_UNUSED19              19
+#define GPIO13_FUN_QDEC1_B               20
+#define GPIO13_FUN_ROW_I_5               21
+#define GPIO13_FUN_COL_O_13              22
+#define GPIO13_FUN_CAM_REF_CLK           23
+/* GPIO14 function definition */
+#define GPIO14_FUN_CLK_OUT_0             0
+#define GPIO14_FUN_BT_PRI                1
+#define GPIO14_FUN_UNUSED2               2
+#define GPIO14_FUN_I2S0_DIO_I2S0_DO      3
+#define GPIO14_FUN_SPI_0_SS              4
+#define GPIO14_FUN_I2C0_SCL              6
+#define GPIO14_FUN_UART_SIG6_UART_SIG2   7
+#define GPIO14_FUN_PWM_CH4               8
+#define GPIO14_FUN_UNUSED9               9
+#define GPIO14_FUN_GPIP_CH_5_ATEST_OUT_0 10
+#define GPIO14_FUN_REG_GPIO_14           11
+#define GPIO14_FUN_RF_TEST_9             12
+#define GPIO14_FUN_SCAN_OUT_0            13
+#define GPIO14_FUN_E21_TCK_E21_TMS       14
+#define GPIO14_FUN_DEBUG_10              15
+#define GPIO14_FUN_FEM_GPIO_4            16
+#define GPIO14_FUN_USB_ENUM_EXT          17
+#define GPIO14_FUN_BD                    18
+#define GPIO14_FUN_UNUSED19              19
+#define GPIO14_FUN_QDEC1_LED             20
+#define GPIO14_FUN_ROW_I_6               21
+#define GPIO14_FUN_COL_O_14              22
+#define GPIO14_FUN_CAM_RESET             23
+/* GPIO15 function definition */
+#define GPIO15_FUN_CLK_OUT_1             0
+#define GPIO15_FUN_BT_ABORT              1
+#define GPIO15_FUN_UNUSED2               2
+#define GPIO15_FUN_I2S0_RCLK_O_I2S0_DI   3
+#define GPIO15_FUN_SPI_0_SCLK            4
+#define GPIO15_FUN_I2C0_SDA              6
+#define GPIO15_FUN_UART_SIG7_UART_SIG3   7
+#define GPIO15_FUN_PWM_CH0               8
+#define GPIO15_FUN_UNUSED9               9
+#define GPIO15_FUN_GPIP_CH_1_ATEST_OUT_1 10
+#define GPIO15_FUN_REG_GPIO_15           11
+#define GPIO15_FUN_RF_TEST_10            12
+#define GPIO15_FUN_SCAN_OUT_1            13
+#define GPIO15_FUN_E21_TDO_E21_TDI       14
+#define GPIO15_FUN_DEBUG_11              15
+#define GPIO15_FUN_FEM_GPIO_0            16
+#define GPIO15_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO15_FUN_VIP                   18
+#define GPIO15_FUN_UNUSED19              19
+#define GPIO15_FUN_QDEC2_A               20
+#define GPIO15_FUN_ROW_I_7               21
+#define GPIO15_FUN_COL_O_15              22
+#define GPIO15_FUN_CAM_PWRDN             23
+/* GPIO16 function definition */
+#define GPIO16_FUN_CLK_OUT_0             0
+#define GPIO16_FUN_BT_ACTIVE             1
+#define GPIO16_FUN_UNUSED2               2
+#define GPIO16_FUN_I2S0_BCLK             3
+#define GPIO16_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO16_FUN_I2C0_SCL              6
+#define GPIO16_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO16_FUN_PWM_CH1               8
+#define GPIO16_FUN_UNUSED9               9
+#define GPIO16_FUN_UNUSED10              10
+#define GPIO16_FUN_REG_GPIO_16           11
+#define GPIO16_FUN_RF_TEST_11            12
+#define GPIO16_FUN_UNUSED13              13
+#define GPIO16_FUN_E21_TMS_E21_TCK       14
+#define GPIO16_FUN_DEBUG_12              15
+#define GPIO16_FUN_FEM_GPIO_1            16
+#define GPIO16_FUN_USB_TX_OE             17
+#define GPIO16_FUN_VIM                   18
+#define GPIO16_FUN_UNUSED19              19
+#define GPIO16_FUN_QDEC2_B               20
+#define GPIO16_FUN_ROW_I_0               21
+#define GPIO16_FUN_COL_O_16              22
+#define GPIO16_FUN_CAM_REF_CLK           23
+/* GPIO17 function definition */
+#define GPIO17_FUN_CLK_OUT_1             0
+#define GPIO17_FUN_BT_PRI                1
+#define GPIO17_FUN_SF_IO_0_SF2_CS2       2
+#define GPIO17_FUN_I2S0_FS               3
+#define GPIO17_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO17_FUN_I2C0_SDA              6
+#define GPIO17_FUN_UART_SIG1_UART_SIG5   7
+#define GPIO17_FUN_PWM_CH2               8
+#define GPIO17_FUN_PIX_DAT4              9
+#define GPIO17_FUN_GPIP_CH_2_PSW_IRRCV   10
+#define GPIO17_FUN_REG_GPIO_17           11
+#define GPIO17_FUN_RF_TEST_12            12
+#define GPIO17_FUN_SCAN_OUT_2            13
+#define GPIO17_FUN_E21_TDI_E21_TDO       14
+#define GPIO17_FUN_DEBUG_13              15
+#define GPIO17_FUN_FEM_GPIO_2            16
+#define GPIO17_FUN_USB_TX_DP_USB_RX_DP   17
+#define GPIO17_FUN_RCV                   18
+#define GPIO17_FUN_UNUSED19              19
+#define GPIO17_FUN_QDEC2_LED             20
+#define GPIO17_FUN_ROW_I_1               21
+#define GPIO17_FUN_COL_O_17              22
+#define GPIO17_FUN_CAM_RESET             23
+/* GPIO18 function definition */
+#define GPIO18_FUN_CLK_OUT_0           0
+#define GPIO18_FUN_BT_ABORT            1
+#define GPIO18_FUN_SF_IO_1             2
+#define GPIO18_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO18_FUN_SPI_0_SS            4
+#define GPIO18_FUN_I2C0_SCL            6
+#define GPIO18_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO18_FUN_PWM_CH3             8
+#define GPIO18_FUN_PIX_DAT5            9
+#define GPIO18_FUN_GPIP_CH_8           10
+#define GPIO18_FUN_REG_GPIO_18         11
+#define GPIO18_FUN_RF_TEST_13          12
+#define GPIO18_FUN_UNUSED13            13
+#define GPIO18_FUN_E21_TCK_E21_TMS     14
+#define GPIO18_FUN_M_CCI_CLK_DEBUG_14  15
+#define GPIO18_FUN_FEM_GPIO_3          16
+#define GPIO18_FUN_USB_SUS_EXT         17
+#define GPIO18_FUN_USB_SUS             18
+#define GPIO18_FUN_RMII_MDC            19
+#define GPIO18_FUN_QDEC0_A             20
+#define GPIO18_FUN_ROW_I_2             21
+#define GPIO18_FUN_COL_O_18            22
+#define GPIO18_FUN_CAM_PWRDN           23
+/* GPIO19 function definition */
+#define GPIO19_FUN_CLK_OUT_1           0
+#define GPIO19_FUN_BT_ACTIVE           1
+#define GPIO19_FUN_SF_CS               2
+#define GPIO19_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO19_FUN_SPI_0_SCLK          4
+#define GPIO19_FUN_I2C0_SDA            6
+#define GPIO19_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO19_FUN_PWM_CH4             8
+#define GPIO19_FUN_PIX_DAT6            9
+#define GPIO19_FUN_GPIP_CH_9           10
+#define GPIO19_FUN_REG_GPIO_19         11
+#define GPIO19_FUN_RF_TEST_14          12
+#define GPIO19_FUN_UNUSED13            13
+#define GPIO19_FUN_E21_TDO_E21_TDI     14
+#define GPIO19_FUN_M_CCI_CS_DEBUG_15   15
+#define GPIO19_FUN_FEM_GPIO_4          16
+#define GPIO19_FUN_USB_ENUM_EXT        17
+#define GPIO19_FUN_USB_ENUM            18
+#define GPIO19_FUN_RMII_MDIO           19
+#define GPIO19_FUN_QDEC0_B             20
+#define GPIO19_FUN_ROW_I_3             21
+#define GPIO19_FUN_COL_O_19            22
+#define GPIO19_FUN_CAM_REF_CLK         23
+/* GPIO20 function definition */
+#define GPIO20_FUN_CLK_OUT_0             0
+#define GPIO20_FUN_BT_PRI                1
+#define GPIO20_FUN_SF_IO_3               2
+#define GPIO20_FUN_I2S0_BCLK             3
+#define GPIO20_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO20_FUN_I2C0_SCL              6
+#define GPIO20_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO20_FUN_PWM_CH0               8
+#define GPIO20_FUN_PIX_DAT7              9
+#define GPIO20_FUN_GPIP_CH_10            10
+#define GPIO20_FUN_REG_GPIO_20           11
+#define GPIO20_FUN_RF_TEST_15            12
+#define GPIO20_FUN_UNUSED13              13
+#define GPIO20_FUN_E21_TMS_E21_TCK       14
+#define GPIO20_FUN_M_CCI_DI_DEBUG_16     15
+#define GPIO20_FUN_FEM_GPIO_0            16
+#define GPIO20_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO20_FUN_USB_OEB               18
+#define GPIO20_FUN_RMII_RXERR            19
+#define GPIO20_FUN_QDEC0_LED             20
+#define GPIO20_FUN_ROW_I_4               21
+#define GPIO20_FUN_COL_O_0               22
+#define GPIO20_FUN_CAM_RESET             23
+/* GPIO21 function definition */
+#define GPIO21_FUN_CLK_OUT_1             0
+#define GPIO21_FUN_BT_ABORT              1
+#define GPIO21_FUN_SF_CLK                2
+#define GPIO21_FUN_I2S0_FS               3
+#define GPIO21_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO21_FUN_I2C0_SDA              6
+#define GPIO21_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO21_FUN_PWM_CH1               8
+#define GPIO21_FUN_UNUSED9               9
+#define GPIO21_FUN_GPIP_CH_11            10
+#define GPIO21_FUN_REG_GPIO_21           11
+#define GPIO21_FUN_RF_TEST_16            12
+#define GPIO21_FUN_UNUSED13              13
+#define GPIO21_FUN_E21_TDI_E21_TDO       14
+#define GPIO21_FUN_M_CCI_DO_DEBUG_17     15
+#define GPIO21_FUN_FEM_GPIO_1            16
+#define GPIO21_FUN_USB_TX_OE             17
+#define GPIO21_FUN_VOP                   18
+#define GPIO21_FUN_RMII_TX_EN            19
+#define GPIO21_FUN_QDEC1_A               20
+#define GPIO21_FUN_ROW_I_5               21
+#define GPIO21_FUN_COL_O_1               22
+#define GPIO21_FUN_CAM_PWRDN             23
+/* GPIO22 function definition */
+#define GPIO22_FUN_CLK_OUT_0           0
+#define GPIO22_FUN_BT_ACTIVE           1
+#define GPIO22_FUN_SF_IO_2             2
+#define GPIO22_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO22_FUN_SPI_0_SS            4
+#define GPIO22_FUN_I2C0_SCL            6
+#define GPIO22_FUN_UART_SIG6_UART_SIG2 7
+#define GPIO22_FUN_PWM_CH2             8
+#define GPIO22_FUN_UNUSED9             9
+#define GPIO22_FUN_LEDDRV_0            10
+#define GPIO22_FUN_REG_GPIO_22         11
+#define GPIO22_FUN_RF_TEST_17          12
+#define GPIO22_FUN_UNUSED13            13
+#define GPIO22_FUN_E21_TCK_E21_TMS     14
+#define GPIO22_FUN_DEBUG_18            15
+#define GPIO22_FUN_FEM_GPIO_2          16
+#define GPIO22_FUN_USB_TX_DP_USB_RX_DP 17
+#define GPIO22_FUN_VOM                 18
+#define GPIO22_FUN_RMII_RX_DV          19
+#define GPIO22_FUN_QDEC1_B             20
+#define GPIO22_FUN_ROW_I_6             21
+#define GPIO22_FUN_COL_O_2             22
+#define GPIO22_FUN_CAM_REF_CLK         23
+/* GPIO23 function definition */
+#define GPIO23_FUN_CLK_OUT_1                 0
+#define GPIO23_FUN_BT_PRI                    1
+#define GPIO23_FUN_SF2_IO_2_SF3_CS2          2
+#define GPIO23_FUN_I2S0_RCLK_O_I2S0_DI       3
+#define GPIO23_FUN_SPI_0_SCLK                4
+#define GPIO23_FUN_I2C0_SDA                  6
+#define GPIO23_FUN_UART_SIG7_UART_SIG3       7
+#define GPIO23_FUN_PWM_CH3                   8
+#define GPIO23_FUN_PIX_DAT4                  9
+#define GPIO23_FUN_LEDDRV_1_FLASH_PULL_OUT_0 10
+#define GPIO23_FUN_REG_GPIO_23               11
+#define GPIO23_FUN_RF_TEST_18                12
+#define GPIO23_FUN_UNUSED13                  13
+#define GPIO23_FUN_E21_TDO_E21_TDI           14
+#define GPIO23_FUN_DEBUG_19                  15
+#define GPIO23_FUN_FEM_GPIO_3                16
+#define GPIO23_FUN_USB_SUS_EXT               17
+#define GPIO23_FUN_BD                        18
+#define GPIO23_FUN_UNUSED19                  19
+#define GPIO23_FUN_QDEC1_LED                 20
+#define GPIO23_FUN_ROW_I_7                   21
+#define GPIO23_FUN_COL_O_3                   22
+#define GPIO23_FUN_CAM_RESET                 23
+/* GPIO24 function definition */
+#define GPIO24_FUN_CLK_OUT_0             0
+#define GPIO24_FUN_BT_ABORT              1
+#define GPIO24_FUN_SF2_IO_1              2
+#define GPIO24_FUN_I2S0_BCLK             3
+#define GPIO24_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO24_FUN_I2C0_SCL              6
+#define GPIO24_FUN_UART_SIG0_UART_SIG4   7
+#define GPIO24_FUN_PWM_CH4               8
+#define GPIO24_FUN_PIX_DAT5              9
+#define GPIO24_FUN_FLASH_PULL_OUT_1      10
+#define GPIO24_FUN_REG_GPIO_24           11
+#define GPIO24_FUN_RF_TEST_19            12
+#define GPIO24_FUN_UNUSED13              13
+#define GPIO24_FUN_E21_TMS_E21_TCK       14
+#define GPIO24_FUN_DEBUG_20              15
+#define GPIO24_FUN_FEM_GPIO_4            16
+#define GPIO24_FUN_USB_ENUM_EXT          17
+#define GPIO24_FUN_VIP                   18
+#define GPIO24_FUN_RMII_MDC              19
+#define GPIO24_FUN_QDEC2_A               20
+#define GPIO24_FUN_ROW_I_0               21
+#define GPIO24_FUN_COL_O_4               22
+#define GPIO24_FUN_CAM_PWRDN             23
+/* GPIO25 function definition */
+#define GPIO25_FUN_CLK_OUT_1             0
+#define GPIO25_FUN_BT_ACTIVE             1
+#define GPIO25_FUN_SF2_CS                2
+#define GPIO25_FUN_I2S0_FS               3
+#define GPIO25_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO25_FUN_I2C0_SDA              6
+#define GPIO25_FUN_UART_SIG1_UART_SIG5   7
+#define GPIO25_FUN_PWM_CH0               8
+#define GPIO25_FUN_PIX_DAT6              9
+#define GPIO25_FUN_FLASH_PULL_OUT_2      10
+#define GPIO25_FUN_REG_GPIO_25           11
+#define GPIO25_FUN_RF_TEST_20            12
+#define GPIO25_FUN_UNUSED13              13
+#define GPIO25_FUN_E21_TDI_E21_TDO       14
+#define GPIO25_FUN_DEBUG_21              15
+#define GPIO25_FUN_FEM_GPIO_0            16
+#define GPIO25_FUN_USB_TX_DN_USB_RX_DN   17
+#define GPIO25_FUN_VIM                   18
+#define GPIO25_FUN_RMII_MDIO             19
+#define GPIO25_FUN_QDEC2_B               20
+#define GPIO25_FUN_ROW_I_1               21
+#define GPIO25_FUN_COL_O_5               22
+#define GPIO25_FUN_CAM_REF_CLK           23
+/* GPIO26 function definition */
+#define GPIO26_FUN_CLK_OUT_0           0
+#define GPIO26_FUN_BT_PRI              1
+#define GPIO26_FUN_SF2_IO_3            2
+#define GPIO26_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO26_FUN_SPI_0_SS            4
+#define GPIO26_FUN_I2C0_SCL            6
+#define GPIO26_FUN_UART_SIG2_UART_SIG6 7
+#define GPIO26_FUN_PWM_CH1             8
+#define GPIO26_FUN_PIX_DAT7            9
+#define GPIO26_FUN_FLASH_PULL_OUT_3    10
+#define GPIO26_FUN_REG_GPIO_26         11
+#define GPIO26_FUN_RF_TEST_21          12
+#define GPIO26_FUN_UNUSED13            13
+#define GPIO26_FUN_E21_TCK_E21_TMS     14
+#define GPIO26_FUN_DEBUG_22            15
+#define GPIO26_FUN_FEM_GPIO_1          16
+#define GPIO26_FUN_USB_TX_OE           17
+#define GPIO26_FUN_RCV                 18
+#define GPIO26_FUN_RMII_RXERR          19
+#define GPIO26_FUN_QDEC2_LED           20
+#define GPIO26_FUN_ROW_I_2             21
+#define GPIO26_FUN_COL_O_6             22
+#define GPIO26_FUN_CAM_RESET           23
+/* GPIO27 function definition */
+#define GPIO27_FUN_CLK_OUT_1           0
+#define GPIO27_FUN_BT_ABORT            1
+#define GPIO27_FUN_SF2_CLK             2
+#define GPIO27_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO27_FUN_SPI_0_SCLK          4
+#define GPIO27_FUN_I2C0_SDA            6
+#define GPIO27_FUN_UART_SIG3_UART_SIG7 7
+#define GPIO27_FUN_PWM_CH2             8
+#define GPIO27_FUN_UNUSED9             9
+#define GPIO27_FUN_FLASH_PULL_OUT_4    10
+#define GPIO27_FUN_REG_GPIO_27         11
+#define GPIO27_FUN_RF_TEST_22          12
+#define GPIO27_FUN_UNUSED13            13
+#define GPIO27_FUN_E21_TDO_E21_TDI     14
+#define GPIO27_FUN_DEBUG_23            15
+#define GPIO27_FUN_FEM_GPIO_2          16
+#define GPIO27_FUN_USB_TX_DP_USB_RX_DP 17
+#define GPIO27_FUN_USB_SUS             18
+#define GPIO27_FUN_RMII_TX_EN          19
+#define GPIO27_FUN_QDEC0_A             20
+#define GPIO27_FUN_ROW_I_3             21
+#define GPIO27_FUN_COL_O_7             22
+#define GPIO27_FUN_CAM_PWRDN           23
+/* GPIO28 function definition */
+#define GPIO28_FUN_CLK_OUT_0             0
+#define GPIO28_FUN_BT_ACTIVE             1
+#define GPIO28_FUN_SF2_IO_0              2
+#define GPIO28_FUN_I2S0_BCLK             3
+#define GPIO28_FUN_SPI_0_MOSI_SPI_0_MISO 4
+#define GPIO28_FUN_I2C0_SCL              6
+#define GPIO28_FUN_UART_SIG4_UART_SIG0   7
+#define GPIO28_FUN_PWM_CH3               8
+#define GPIO28_FUN_PIX_DAT4              9
+#define GPIO28_FUN_FLASH_PULL_OUT_5      10
+#define GPIO28_FUN_REG_GPIO_28           11
+#define GPIO28_FUN_RF_TEST_23            12
+#define GPIO28_FUN_UNUSED13              13
+#define GPIO28_FUN_E21_TMS_E21_TCK       14
+#define GPIO28_FUN_DEBUG_24              15
+#define GPIO28_FUN_FEM_GPIO_3            16
+#define GPIO28_FUN_USB_SUS_EXT           17
+#define GPIO28_FUN_USB_ENUM              18
+#define GPIO28_FUN_RMII_RX_DV            19
+#define GPIO28_FUN_QDEC0_B               20
+#define GPIO28_FUN_ROW_I_4               21
+#define GPIO28_FUN_COL_O_8               22
+#define GPIO28_FUN_CAM_REF_CLK           23
+/* GPIO29 function definition */
+#define GPIO29_FUN_CLK_OUT_1             0
+#define GPIO29_FUN_BT_PRI                1
+#define GPIO29_FUN_UNUSED2               2
+#define GPIO29_FUN_I2S0_FS               3
+#define GPIO29_FUN_SPI_0_MISO_SPI_0_MOSI 4
+#define GPIO29_FUN_I2C0_SDA              6
+#define GPIO29_FUN_UART_SIG5_UART_SIG1   7
+#define GPIO29_FUN_PWM_CH4               8
+#define GPIO29_FUN_PIX_DAT5              9
+#define GPIO29_FUN_UNUSED10              10
+#define GPIO29_FUN_REG_GPIO_29           11
+#define GPIO29_FUN_RF_TEST_24            12
+#define GPIO29_FUN_UNUSED13              13
+#define GPIO29_FUN_E21_TDI_E21_TDO       14
+#define GPIO29_FUN_DEBUG_25              15
+#define GPIO29_FUN_FEM_GPIO_4            16
+#define GPIO29_FUN_USB_ENUM_EXT          17
+#define GPIO29_FUN_USB_OEB               18
+#define GPIO29_FUN_UNUSED19              19
+#define GPIO29_FUN_QDEC0_LED             20
+#define GPIO29_FUN_ROW_I_5               21
+#define GPIO29_FUN_COL_O_9               22
+#define GPIO29_FUN_CAM_RESET             23
+/* GPIO30 function definition */
+#define GPIO30_FUN_CLK_OUT_0           0
+#define GPIO30_FUN_BT_ABORT            1
+#define GPIO30_FUN_UNUSED2             2
+#define GPIO30_FUN_I2S0_DIO_I2S0_DO    3
+#define GPIO30_FUN_SPI_0_SS            4
+#define GPIO30_FUN_I2C0_SCL            6
+#define GPIO30_FUN_UART_SIG6_UART_SIG2 7
+#define GPIO30_FUN_PWM_CH0             8
+#define GPIO30_FUN_PIX_DAT6            9
+#define GPIO30_FUN_UNUSED10            10
+#define GPIO30_FUN_REG_GPIO_30         11
+#define GPIO30_FUN_RF_TEST_25          12
+#define GPIO30_FUN_UNUSED13            13
+#define GPIO30_FUN_E21_TCK_E21_TMS     14
+#define GPIO30_FUN_DEBUG_26            15
+#define GPIO30_FUN_FEM_GPIO_0          16
+#define GPIO30_FUN_USB_TX_DN_USB_RX_DN 17
+#define GPIO30_FUN_VOP                 18
+#define GPIO30_FUN_UNUSED19            19
+#define GPIO30_FUN_QDEC1_A             20
+#define GPIO30_FUN_ROW_I_6             21
+#define GPIO30_FUN_COL_O_10            22
+#define GPIO30_FUN_CAM_PWRDN           23
+/* GPIO31 function definition */
+#define GPIO31_FUN_CLK_OUT_1           0
+#define GPIO31_FUN_BT_ACTIVE           1
+#define GPIO31_FUN_UNUSED2             2
+#define GPIO31_FUN_I2S0_RCLK_O_I2S0_DI 3
+#define GPIO31_FUN_SPI_0_SCLK          4
+#define GPIO31_FUN_I2C0_SDA            6
+#define GPIO31_FUN_UART_SIG7_UART_SIG3 7
+#define GPIO31_FUN_PWM_CH1             8
+#define GPIO31_FUN_PIX_DAT7            9
+#define GPIO31_FUN_UNUSED10            10
+#define GPIO31_FUN_REG_GPIO_31         11
+#define GPIO31_FUN_RF_TEST_26          12
+#define GPIO31_FUN_UNUSED13            13
+#define GPIO31_FUN_E21_TDO_E21_TDI     14
+#define GPIO31_FUN_DEBUG_27            15
+#define GPIO31_FUN_FEM_GPIO_1          16
+#define GPIO31_FUN_USB_TX_OE           17
+#define GPIO31_FUN_VOM                 18
+#define GPIO31_FUN_UNUSED19            19
+#define GPIO31_FUN_QDEC1_B             20
+#define GPIO31_FUN_ROW_I_7             21
+#define GPIO31_FUN_COL_O_11            22
+#define GPIO31_FUN_CAM_REF_CLK         23
+
+
+#endif /*__BL702_GPIO_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_hbn.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_hbn.h
new file mode 100755
index 0000000000..90760bb1ec
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_hbn.h
@@ -0,0 +1,564 @@
+/**
+  ******************************************************************************
+  * @file    bl702_hbn.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_HBN_H__
+#define __BL702_HBN_H__
+
+#include "hbn_reg.h"
+#include "bl702_aon.h"
+#include "bl702_common.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief HBN PIR interrupt configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type lowIntEn;  /*!< Low will trigger interrupt */
+    BL_Fun_Type highIntEn; /*!< High will trigger interrupt */
+} HBN_PIR_INT_CFG_Type;
+
+/**
+ *  @brief HBN PIR low pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_LPF_DIV1, /*!< HBN PIR lpf div 1 */
+    HBN_PIR_LPF_DIV2, /*!< HBN PIR lpf div 2 */
+} HBN_PIR_LPF_Type;
+
+/**
+ *  @brief HBN PIR high pass filter type definition
+ */
+typedef enum {
+    HBN_PIR_HPF_METHOD0, /*!< HBN PIR hpf calc method 0, 1-z^-1 */
+    HBN_PIR_HPF_METHOD1, /*!< HBN PIR hpf calc method 1, 1-z^-2 */
+    HBN_PIR_HPF_METHOD2, /*!< HBN PIR hpf calc method 2, 1-z^-3 */
+} HBN_PIR_HPF_Type;
+
+/**
+ *  @brief HBN BOR threshold type definition
+ */
+typedef enum {
+    HBN_BOR_THRES_2P0V, /*!< BOR threshold 2.0V */
+    HBN_BOR_THRES_2P4V, /*!< BOR threshold 2.4V */
+} HBN_BOR_THRES_Type;
+
+/**
+ *  @brief HBN BOR mode type definition
+ */
+typedef enum {
+    HBN_BOR_MODE_POR_INDEPENDENT, /*!< POR is independent of BOR */
+    HBN_BOR_MODE_POR_RELEVANT,    /*!< POR is relevant to BOR */
+} HBN_BOR_MODE_Type;
+
+/**
+ *  @brief HBN 32K clock type definition
+ */
+typedef enum {
+    HBN_32K_RC = 0,  /*!< HBN use rc 32k */
+    HBN_32K_XTAL,    /*!< HBN use xtal 32k */
+    HBN_32K_DIG = 3, /*!< HBN use dig 32k */
+} HBN_32K_CLK_Type;
+
+/**
+ *  @brief HBN xclk clock type definition
+ */
+typedef enum {
+    HBN_XCLK_CLK_RC32M, /*!< use RC32M as xclk clock */
+    HBN_XCLK_CLK_XTAL,  /*!< use XTAL as xclk clock */
+} HBN_XCLK_CLK_Type;
+
+/**
+ *  @brief HBN root clock type definition
+ */
+typedef enum {
+    HBN_ROOT_CLK_RC32M, /*!< use RC32M as root clock */
+    HBN_ROOT_CLK_XTAL,  /*!< use XTAL as root clock */
+    HBN_ROOT_CLK_DLL,   /*!< use DLL as root clock */
+} HBN_ROOT_CLK_Type;
+
+/**
+ *  @brief HBN UART clock type definition
+ */
+typedef enum {
+    HBN_UART_CLK_FCLK = 0, /*!< Select FCLK as UART clock */
+    HBN_UART_CLK_96M,      /*!< Select 96M as UART clock */
+} HBN_UART_CLK_Type;
+
+/**
+ *  @brief HBN RTC interrupt delay type definition
+ */
+typedef enum {
+    HBN_RTC_INT_DELAY_32T = 0, /*!< HBN RTC interrupt delay 32T */
+    HBN_RTC_INT_DELAY_0T = 1,  /*!< HBN RTC interrupt delay 0T */
+} HBN_RTC_INT_Delay_Type;
+
+/**
+ *  @brief HBN interrupt type definition
+ */
+typedef enum {
+    HBN_INT_GPIO9 = 0,   /*!< HBN interrupt type: GPIO9 */
+    HBN_INT_GPIO10 = 1,  /*!< HBN interrupt type: GPIO10 */
+    HBN_INT_GPIO11 = 2,  /*!< HBN interrupt type: GPIO11 */
+    HBN_INT_GPIO12 = 3,  /*!< HBN interrupt type: GPIO12 */
+    HBN_INT_GPIO13 = 4,  /*!< HBN interrupt type: GPIO13 */
+    HBN_INT_RTC = 16,    /*!< HBN interrupt type: RTC */
+    HBN_INT_PIR,         /*!< HBN interrupt type: PIR */
+    HBN_INT_BOR,         /*!< HBN interrupt type: BOR */
+    HBN_INT_ACOMP0 = 20, /*!< HBN interrupt type: ACOMP0 */
+    HBN_INT_ACOMP1 = 22, /*!< HBN interrupt type: ACOMP1 */
+} HBN_INT_Type;
+
+/**
+ *  @brief HBN acomp interrupt type definition
+ */
+typedef enum {
+    HBN_ACOMP_INT_EDGE_POSEDGE = 0, /*!< HBN acomp interrupt edge posedge */
+    HBN_ACOMP_INT_EDGE_NEGEDGE = 1, /*!< HBN acomp interrupt edge negedge */
+} HBN_ACOMP_INT_EDGE_Type;
+
+/**
+ *  @brief HBN reset event type definition
+ */
+typedef enum {
+    HBN_RST_EVENT_POR_OUT,   /*!< por_out event */
+    HBN_RST_EVENT_EXT_RST_N, /*!< ext_rst_n event */
+    HBN_RST_EVENT_SW_RST,    /*!< sw_rst event */
+    HBN_RST_EVENT_PWR_RST_N, /*!< pwr_rst_n event */
+    HBN_RST_EVENT_BOR_OUT,   /*!< bor_out_ event */
+} HBN_RST_EVENT_Type;
+
+/**
+ *  @brief HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< HBN GPIO INT trigger type: sync falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< HBN GPIO INT trigger type: sync rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< HBN GPIO INT trigger type: sync low level trigger */
+    HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< HBN GPIO INT trigger type: sync high level trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< HBN GPIO INT trigger type: async falling edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< HBN GPIO INT trigger type: async rising edge trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< HBN GPIO INT trigger type: async low level trigger */
+    HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< HBN GPIO INT trigger type: async high level trigger */
+} HBN_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT0_INT_GPIO9 = 0,  /*!< HBN out 0 interrupt type: GPIO9 */
+    HBN_OUT0_INT_GPIO10 = 1, /*!< HBN out 0 interrupt type: GPIO10 */
+    HBN_OUT0_INT_GPIO11 = 2, /*!< HBN out 0 interrupt type: GPIO11 */
+    HBN_OUT0_INT_GPIO12 = 3, /*!< HBN out 0 interrupt type: GPIO12 */
+    HBN_OUT0_INT_GPIO13 = 4, /*!< HBN out 0 interrupt type: GPIO13 */
+    HBN_OUT0_INT_RTC,        /*!< HBN out 0 interrupt type: RTC */
+    HBN_OUT0_MAX,            /*!< HBN out 0 max num */
+} HBN_OUT0_INT_Type;
+
+/**
+ *  @brief HBN OUT0 interrupt type definition
+ */
+typedef enum {
+    HBN_OUT1_INT_PIR,    /*!< HBN out 1 interrupt type: PIR */
+    HBN_OUT1_INT_BOR,    /*!< HBN out 1 interrupt type: BOR */
+    HBN_OUT1_INT_ACOMP0, /*!< HBN out 1 interrupt type: ACOMP0 */
+    HBN_OUT1_INT_ACOMP1, /*!< HBN out 1 interrupt type: ACOMP1 */
+    HBN_OUT1_MAX,        /*!< HBN out 1 max num */
+} HBN_OUT1_INT_Type;
+
+/**
+ *  @brief HBN LDO level type definition
+ */
+typedef enum {
+    HBN_LDO_LEVEL_0P60V = 0,  /*!< HBN LDO voltage 0.60V */
+    HBN_LDO_LEVEL_0P65V = 1,  /*!< HBN LDO voltage 0.65V */
+    HBN_LDO_LEVEL_0P70V = 2,  /*!< HBN LDO voltage 0.70V */
+    HBN_LDO_LEVEL_0P75V = 3,  /*!< HBN LDO voltage 0.75V */
+    HBN_LDO_LEVEL_0P80V = 4,  /*!< HBN LDO voltage 0.80V */
+    HBN_LDO_LEVEL_0P85V = 5,  /*!< HBN LDO voltage 0.85V */
+    HBN_LDO_LEVEL_0P90V = 6,  /*!< HBN LDO voltage 0.90V */
+    HBN_LDO_LEVEL_0P95V = 7,  /*!< HBN LDO voltage 0.95V */
+    HBN_LDO_LEVEL_1P00V = 8,  /*!< HBN LDO voltage 1.00V */
+    HBN_LDO_LEVEL_1P05V = 9,  /*!< HBN LDO voltage 1.05V */
+    HBN_LDO_LEVEL_1P10V = 10, /*!< HBN LDO voltage 1.10V */
+    HBN_LDO_LEVEL_1P15V = 11, /*!< HBN LDO voltage 1.15V */
+    HBN_LDO_LEVEL_1P20V = 12, /*!< HBN LDO voltage 1.20V */
+    HBN_LDO_LEVEL_1P25V = 13, /*!< HBN LDO voltage 1.25V */
+    HBN_LDO_LEVEL_1P30V = 14, /*!< HBN LDO voltage 1.30V */
+    HBN_LDO_LEVEL_1P35V = 15, /*!< HBN LDO voltage 1.35V */
+} HBN_LDO_LEVEL_Type;
+
+/**
+ *  @brief HBN LDO11RT drive strength type definition
+ */
+typedef enum {
+    HBN_LDO11RT_DRIVE_STRENGTH_5_50UA = 0,   /*!< HBN LDO11RT drive strength 0: 5uA to 50uA */
+    HBN_LDO11RT_DRIVE_STRENGTH_10_100UA = 1, /*!< HBN LDO11RT drive strength 1: 10uA to 100uA */
+    HBN_LDO11RT_DRIVE_STRENGTH_15_150UA = 2, /*!< HBN LDO11RT drive strength 2: 15uA to 150uA */
+    HBN_LDO11RT_DRIVE_STRENGTH_25_250UA = 3, /*!< HBN LDO11RT drive strength 3: 25uA to 250uA */
+} HBN_LDO11RT_DRIVE_STRENGTH_Type;
+
+/**
+ *  @brief HBN level type definition
+ */
+typedef enum {
+    HBN_LEVEL_0, /*!< HBN pd_core */
+    HBN_LEVEL_1, /*!< HBN pd_aon_hbncore + pd_core */
+    HBN_LEVEL_2, /*!< HBN pd_aon_hbncore + pd_core */
+    HBN_LEVEL_3, /*!< HBN pd_aon_hbnrtc + pd_aon_hbncore + pd_core */
+} HBN_LEVEL_Type;
+
+/**
+ *  @brief HBN BOR configuration type definition
+ */
+typedef struct
+{
+    uint8_t enableBor;      /*!< Enable BOR or not */
+    uint8_t enableBorInt;   /*!< Enable BOR interrupt or not */
+    uint8_t borThreshold;   /*!< BOR threshold */
+    uint8_t enablePorInBor; /*!< Enable POR when BOR occure or not */
+} HBN_BOR_CFG_Type;
+
+/**
+ *  @brief HBN APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t useXtal32k;                     /*!< Whether use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint32_t sleepTime;                     /*!< HBN sleep time */
+    uint8_t gpioWakeupSrc;                  /*!< GPIO Wakeup source */
+    HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
+    spi_flash_cfg_type *flashCfg;           /*!< Flash config pointer, used when power down flash */
+    uint8_t flashPinCfg;                    /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */
+    HBN_LEVEL_Type hbnLevel;                /*!< HBN level */
+    HBN_LDO_LEVEL_Type ldoLevel;            /*!< LDO level */
+} HBN_APP_CFG_Type;
+
+/*@} end of group HBN_Public_Types */
+
+/** @defgroup  HBN_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  HBN_PIR_LPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_LPF_TYPE(type) (((type) == HBN_PIR_LPF_DIV1) || \
+                                   ((type) == HBN_PIR_LPF_DIV2))
+
+/** @defgroup  HBN_PIR_HPF_TYPE
+ *  @{
+ */
+#define IS_HBN_PIR_HPF_TYPE(type) (((type) == HBN_PIR_HPF_METHOD0) || \
+                                   ((type) == HBN_PIR_HPF_METHOD1) || \
+                                   ((type) == HBN_PIR_HPF_METHOD2))
+
+/** @defgroup  HBN_BOR_THRES_TYPE
+ *  @{
+ */
+#define IS_HBN_BOR_THRES_TYPE(type) (((type) == HBN_BOR_THRES_2P0V) || \
+                                     ((type) == HBN_BOR_THRES_2P4V))
+
+/** @defgroup  HBN_BOR_MODE_TYPE
+ *  @{
+ */
+#define IS_HBN_BOR_MODE_TYPE(type) (((type) == HBN_BOR_MODE_POR_INDEPENDENT) || \
+                                    ((type) == HBN_BOR_MODE_POR_RELEVANT))
+
+/** @defgroup  HBN_32K_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_32K_CLK_TYPE(type) (((type) == HBN_32K_RC) ||   \
+                                   ((type) == HBN_32K_XTAL) || \
+                                   ((type) == HBN_32K_DIG))
+
+/** @defgroup  HBN_XCLK_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_XCLK_CLK_TYPE(type) (((type) == HBN_XCLK_CLK_RC32M) || \
+                                    ((type) == HBN_XCLK_CLK_XTAL))
+
+/** @defgroup  HBN_ROOT_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_ROOT_CLK_TYPE(type) (((type) == HBN_ROOT_CLK_RC32M) || \
+                                    ((type) == HBN_ROOT_CLK_XTAL) ||  \
+                                    ((type) == HBN_ROOT_CLK_DLL))
+
+/** @defgroup  HBN_UART_CLK_TYPE
+ *  @{
+ */
+#define IS_HBN_UART_CLK_TYPE(type) (((type) == HBN_UART_CLK_FCLK) || \
+                                    ((type) == HBN_UART_CLK_96M))
+
+/** @defgroup  HBN_RTC_INT_DELAY_TYPE
+ *  @{
+ */
+#define IS_HBN_RTC_INT_DELAY_TYPE(type) (((type) == HBN_RTC_INT_DELAY_32T) || \
+                                         ((type) == HBN_RTC_INT_DELAY_0T))
+
+/** @defgroup  HBN_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_INT_TYPE(type) (((type) == HBN_INT_GPIO9) ||  \
+                               ((type) == HBN_INT_GPIO10) || \
+                               ((type) == HBN_INT_GPIO11) || \
+                               ((type) == HBN_INT_GPIO12) || \
+                               ((type) == HBN_INT_GPIO13) || \
+                               ((type) == HBN_INT_RTC) ||    \
+                               ((type) == HBN_INT_PIR) ||    \
+                               ((type) == HBN_INT_BOR) ||    \
+                               ((type) == HBN_INT_ACOMP0) || \
+                               ((type) == HBN_INT_ACOMP1))
+
+/** @defgroup  HBN_ACOMP_INT_EDGE_TYPE
+ *  @{
+ */
+#define IS_HBN_ACOMP_INT_EDGE_TYPE(type) (((type) == HBN_ACOMP_INT_EDGE_POSEDGE) || \
+                                          ((type) == HBN_ACOMP_INT_EDGE_NEGEDGE))
+
+/** @defgroup  HBN_RST_EVENT_TYPE
+ *  @{
+ */
+#define IS_HBN_RST_EVENT_TYPE(type) (((type) == HBN_RST_EVENT_POR_OUT) ||   \
+                                     ((type) == HBN_RST_EVENT_EXT_RST_N) || \
+                                     ((type) == HBN_RST_EVENT_SW_RST) ||    \
+                                     ((type) == HBN_RST_EVENT_PWR_RST_N) || \
+                                     ((type) == HBN_RST_EVENT_BOR_OUT))
+
+/** @defgroup  HBN_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_HBN_GPIO_INT_TRIGGER_TYPE(type) (((type) == HBN_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
+                                            ((type) == HBN_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  HBN_OUT0_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT0_INT_TYPE(type) (((type) == HBN_OUT0_INT_GPIO9) ||  \
+                                    ((type) == HBN_OUT0_INT_GPIO10) || \
+                                    ((type) == HBN_OUT0_INT_GPIO11) || \
+                                    ((type) == HBN_OUT0_INT_GPIO12) || \
+                                    ((type) == HBN_OUT0_INT_GPIO13) || \
+                                    ((type) == HBN_OUT0_INT_RTC) ||    \
+                                    ((type) == HBN_OUT0_MAX))
+
+/** @defgroup  HBN_OUT1_INT_TYPE
+ *  @{
+ */
+#define IS_HBN_OUT1_INT_TYPE(type) (((type) == HBN_OUT1_INT_PIR) ||    \
+                                    ((type) == HBN_OUT1_INT_BOR) ||    \
+                                    ((type) == HBN_OUT1_INT_ACOMP0) || \
+                                    ((type) == HBN_OUT1_INT_ACOMP1) || \
+                                    ((type) == HBN_OUT1_MAX))
+
+/** @defgroup  HBN_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LDO_LEVEL_TYPE(type) (((type) == HBN_LDO_LEVEL_0P60V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P65V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P70V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P75V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P80V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P85V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P90V) || \
+                                     ((type) == HBN_LDO_LEVEL_0P95V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P00V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P05V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P10V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P15V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P20V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P25V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P30V) || \
+                                     ((type) == HBN_LDO_LEVEL_1P35V))
+
+/** @defgroup  HBN_LDO11RT_DRIVE_STRENGTH_TYPE
+ *  @{
+ */
+#define IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(type) (((type) == HBN_LDO11RT_DRIVE_STRENGTH_5_50UA) ||   \
+                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_10_100UA) || \
+                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_15_150UA) || \
+                                                  ((type) == HBN_LDO11RT_DRIVE_STRENGTH_25_250UA))
+
+/** @defgroup  HBN_LEVEL_TYPE
+ *  @{
+ */
+#define IS_HBN_LEVEL_TYPE(type) (((type) == HBN_LEVEL_0) || \
+                                 ((type) == HBN_LEVEL_1) || \
+                                 ((type) == HBN_LEVEL_2) || \
+                                 ((type) == HBN_LEVEL_3))
+
+/*@} end of group HBN_Public_Constants */
+
+/** @defgroup  HBN_Public_Macros
+ *  @{
+ */
+#define HBN_RAM_SIZE           (4 * 1024)
+#define HBN_RTC_COMP_BIT0_39   0x01
+#define HBN_RTC_COMP_BIT0_23   0x02
+#define HBN_RTC_COMP_BIT13_39  0x04
+#define HBN_STATUS_ENTER_FLAG  0x4e424845
+#define HBN_STATUS_WAKEUP_FLAG 0x4e424857
+#define HBN_WAKEUP_GPIO_NONE   0x00
+#define HBN_WAKEUP_GPIO_9      0x01
+#define HBN_WAKEUP_GPIO_10     0x02
+#define HBN_WAKEUP_GPIO_11     0x04
+#define HBN_WAKEUP_GPIO_12     0x08
+#define HBN_WAKEUP_GPIO_13     0x10
+#define HBN_WAKEUP_GPIO_ALL    0x1E
+
+/*@} end of group HBN_Public_Macros */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void HBN_OUT0_IRQHandler(void);
+void HBN_OUT1_IRQHandler(void);
+#endif
+/*----------*/
+void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
+void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg);
+void HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
+BL_Err_Type HBN_Reset(void);
+BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv);
+BL_Err_Type HBN_Disable(void);
+/*----------*/
+BL_Err_Type HBN_PIR_Enable(void);
+BL_Err_Type HBN_PIR_Disable(void);
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg);
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf);
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf);
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold);
+uint16_t HBN_Get_PIR_Threshold(void);
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval);
+uint16_t HBN_Get_PIR_Interval(void);
+/*----------*/
+BL_Sts_Type HBN_Get_BOR_OUT_State(void);
+BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode);
+/*----------*/
+BL_Err_Type HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel);
+BL_Err_Type HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength);
+/*----------*/
+BL_Err_Type HBN_32K_Sel(HBN_32K_CLK_Type clkType);
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel);
+BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk);
+BL_Err_Type HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk);
+/*----------*/
+BL_Err_Type HBN_Set_HRAM_slp(void);
+BL_Err_Type HBN_Set_HRAM_Ret(void);
+/*----------*/
+uint32_t HBN_Get_Status_Flag(void);
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag);
+uint32_t HBN_Get_Wakeup_Addr(void);
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr);
+/*----------*/
+BL_Err_Type HBN_Clear_RTC_Counter(void);
+BL_Err_Type HBN_Enable_RTC_Counter(void);
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode);
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh);
+BL_Err_Type HBN_Clear_RTC_INT(void);
+/*----------*/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType);
+BL_Err_Type HBN_GPIO_INT_Disable(void);
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType);
+uint8_t HBN_Get_Pin_Wakeup_Mode(void);
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType);
+BL_Err_Type HBN_Hw_Pu_Pd_Cfg(uint8_t enable);
+BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg);
+BL_Err_Type HBN_Pin_WakeUp_Mask(uint8_t maskVal);
+/*----------*/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge);
+/*----------*/
+BL_Err_Type HBN_Enable_BOR_IRQ(void);
+BL_Err_Type HBN_Disable_BOR_IRQ(void);
+/*----------*/
+BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event);
+BL_Err_Type HBN_Clear_Reset_Event(void);
+/*----------*/
+BL_Err_Type HBN_Out0_IRQHandler_Install(void);
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type HBN_Out1_IRQHandler_Install(void);
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn,
+                                  uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask);
+/*----------*/
+BL_Err_Type HBN_Power_On_Xtal_32K(void);
+BL_Err_Type HBN_Power_Off_Xtal_32K(void);
+BL_Err_Type HBN_Power_On_RC32K(void);
+BL_Err_Type HBN_Power_Off_RC32K(void);
+BL_Err_Type HBN_Trim_RC32K(void);
+BL_Err_Type HBN_Set_Pad_23_28_Pullnone(void);
+BL_Err_Type HBN_Set_Pad_23_28_Pullup(void);
+BL_Err_Type HBN_Set_Pad_23_28_Pulldown(void);
+BL_Err_Type HBN_Set_Pad_23_28_ActiveIE(void);
+BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg);
+/*----------*/
+void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel);
+/*----------*/;
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_HBN_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_l1c.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_l1c.h
new file mode 100755
index 0000000000..4222093079
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_l1c.h
@@ -0,0 +1,202 @@
+/**
+  ******************************************************************************
+  * @file    bl702_l1c.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_L1C_H__
+#define __BL702_L1C_H__
+
+#include "l1c_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  L1C
+ *  @{
+ */
+
+/** @defgroup  L1C_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief L1C configuration structure type definition
+ */
+typedef struct
+{
+    BL_Fun_Type wrapDis;  /*!< wrap disable */
+    BL_Fun_Type bypassEn; /*!< bypass cache enable */
+    uint8_t wayDis;       /*!< Disable part of cache ways & used as ITCM */
+    BL_Fun_Type cntEn;    /*!< l1c count enable */
+} L1C_CACHE_Cfg_Type;
+
+/**
+ *  @brief L1C BMX arb mode type definition
+ */
+typedef enum {
+    L1C_BMX_ARB_FIX,         /*!< 0->fix */
+    L1C_BMX_ARB_ROUND_ROBIN, /*!< 2->round-robin */
+    L1C_BMX_ARB_RANDOM,      /*!< 3->random */
+} L1C_BMX_ARB_Type;
+
+/**
+ *  @brief L1C BMX configuration structure type definition
+ */
+typedef struct
+{
+    uint8_t timeoutEn;       /*!< Bus timeout enable: detect slave no reaponse in 1024 cycles */
+    BL_Fun_Type errEn;       /*!< Bus error response enable */
+    L1C_BMX_ARB_Type arbMod; /*!< 0->fix, 2->round-robin, 3->random */
+} L1C_BMX_Cfg_Type;
+
+/**
+ *  @brief L1C BMX bus err type definition
+ */
+typedef enum {
+    L1C_BMX_BUS_ERR_TRUSTZONE_DECODE, /*!< Bus trustzone decode error */
+    L1C_BMX_BUS_ERR_ADDR_DECODE,      /*!< Bus addr decode error */
+} L1C_BMX_BUS_ERR_Type;
+
+/**
+ *  @brief L1C BMX bus err interrupt type definition
+ */
+typedef enum {
+    L1C_BMX_ERR_INT_ERR, /*!< L1C BMX bus err interrupt */
+    L1C_BMX_ERR_INT_ALL, /*!< L1C BMX bus err interrupt max num */
+} L1C_BMX_ERR_INT_Type;
+
+/**
+ *  @brief L1C BMX time out interrupt type definition
+ */
+typedef enum {
+    L1C_BMX_TO_INT_TIMEOUT, /*!< L1C_BMX timeout interrupt */
+    L1C_BMX_TO_INT_ALL,     /*!< L1C_BMX timeout interrupt max num */
+} L1C_BMX_TO_INT_Type;
+
+/*@} end of group L1C_Public_Types */
+
+/** @defgroup  L1C_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  L1C_BMX_ARB_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_ARB_TYPE(type) (((type) == L1C_BMX_ARB_FIX) ||         \
+                                   ((type) == L1C_BMX_ARB_ROUND_ROBIN) || \
+                                   ((type) == L1C_BMX_ARB_RANDOM))
+
+/** @defgroup  L1C_BMX_BUS_ERR_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_BUS_ERR_TYPE(type) (((type) == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) || \
+                                       ((type) == L1C_BMX_BUS_ERR_ADDR_DECODE))
+
+/** @defgroup  L1C_BMX_ERR_INT_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_ERR_INT_TYPE(type) (((type) == L1C_BMX_ERR_INT_ERR) || \
+                                       ((type) == L1C_BMX_ERR_INT_ALL))
+
+/** @defgroup  L1C_BMX_TO_INT_TYPE
+ *  @{
+ */
+#define IS_L1C_BMX_TO_INT_TYPE(type) (((type) == L1C_BMX_TO_INT_TIMEOUT) || \
+                                      ((type) == L1C_BMX_TO_INT_ALL))
+
+/*@} end of group L1C_Public_Constants */
+
+/** @defgroup  L1C_Public_Macros
+ *  @{
+ */
+#define L1C_WAY_DISABLE_NONE  0x00
+#define L1C_WAY_DISABLE_ONE   0x01
+#define L1C_WAY_DISABLE_TWO   0x03
+#define L1C_WAY_DISABLE_THREE 0x07
+#define L1C_WAY_DISABLE_ALL   0x0F
+#define L1C_WAY_DISABLE_USER  0xFF
+#if 1
+/*NP config address */
+#define L1C_CONF_REG        (L1C_BASE + 0x00)
+#define L1C_HIT_CNT_LSB_REG (L1C_BASE + 0x04)
+#define L1C_HIT_CNT_MSB_REG (L1C_BASE + 0x08)
+#define L1C_MISS_CNT_REG    (L1C_BASE + 0x0C)
+/* Get miss and hit count */
+#define L1C_Get_Miss_Cnt()    BL702_REG_RD(L1C_MISS_CNT_REG)
+#define L1C_Get_Hit_Cnt_LSB() BL702_REG_RD(L1C_HIT_CNT_LSB_REG)
+#define L1C_Get_Hit_Cnt_MSB() BL702_REG_RD(L1C_HIT_CNT_MSB_REG)
+#endif
+
+/*@} end of group L1C_Public_Macros */
+
+/** @defgroup  L1C_Public_Functions
+ *  @{
+ */
+/*----------*/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_ERR_IRQHandler(void);
+void L1C_BMX_TO_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type L1C_Cache_Enable_Set(uint8_t wayDisable);
+void L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn);
+BL_Err_Type L1C_Cache_Flush(void);
+void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh);
+uint32_t L1C_Cache_Miss_Count_Get(void);
+void L1C_Cache_Read_Disable(void);
+/*----------*/
+BL_Err_Type L1C_Set_Wrap(BL_Fun_Type wrap);
+BL_Err_Type L1C_Set_Way_Disable(uint8_t disableVal);
+BL_Err_Type L1C_IROM_2T_Access_Set(uint8_t enable);
+/*----------*/
+BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg);
+BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void);
+BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void);
+BL_Err_Type L1C_BMX_BusErrResponse_Enable(void);
+BL_Err_Type L1C_BMX_BusErrResponse_Disable(void);
+BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType);
+uint32_t L1C_BMX_Get_Err_Addr(void);
+BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun);
+BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType,
+                                                 intCallback_Type *cbFun);
+/*----------*/;
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_L1C_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nf_cfg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nf_cfg.h
new file mode 100755
index 0000000000..c3764d32ad
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nf_cfg.h
@@ -0,0 +1,48 @@
+/**
+  ******************************************************************************
+  * @file    bl702_nf_cfg.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_NF_CFG_H__
+#define __BL702_NF_CFG_H__
+
+#include "string.h"
+#include "bl702_nflash.h"
+#include "bl702_sf_ctrl.h"
+
+/** @defgroup  NF_CFG_Public_Functions
+ *  @{
+ */
+uint32_t NF_Cfg_Flash_Identify(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, Nand_Flash_Cfg_Type *pFlashCfg);
+
+#endif /* __BL702_NF_CFG_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nflash.h
old mode 100644
new mode 100755
similarity index 58%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nflash.h
index 51f9bc2e1e..e7ed487b83
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sflash.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_nflash.h
@@ -1,6 +1,6 @@
 /**
   ******************************************************************************
-  * @file    bl808_sflah.h
+  * @file    bl702_nflah.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
@@ -33,13 +33,13 @@
   *
   ******************************************************************************
   */
-#ifndef __BL808_SFLAH_H__
-#define __BL808_SFLAH_H__
+#ifndef __BL702_NFLAH_H__
+#define __BL702_NFLAH_H__
 
-#include "bl808_common.h"
-#include "bl808_sf_ctrl.h"
+#include "bl702_common.h"
+#include "bl702_sf_ctrl.h"
 
-/** @addtogroup  BL808_Peripheral_Driver
+/** @addtogroup  BL602_Peripheral_Driver
  *  @{
  */
 
@@ -54,9 +54,44 @@
 /**
  *  @brief Serial flash configuration structure type definition
  */
+/*@} end of group SFLAH_Public_Types */
+
+/** @defgroup  SFLAH_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SFLAH_Public_Constants */
+
+/** @defgroup  SFLAH_Public_Macros
+ *  @{
+ */
+#define BFLB_NAND_FLASH_BLK_DATA_SIZE   (128 * 1024)
+#define BFLB_NAND_FLASH_BLK_TOTAL_SIZE  ((128 + 4) * 1024)
+#define BFLB_NAND_FLASH_PAGE_SIZE       (2048)
+#define BFLB_NAND_FLASH_PAGE_TOTAL_SIZE (2048 + 64)
+#define BFLB_NAND_FLASH_PAGES_PER_BLOCK (64)
+#define BFLB_NAND_FLASH_CMD_INVALID     (0xff)
+#define DISK_SECTOR_SIZE                (512)
+typedef unsigned char BYTE;
+typedef unsigned long DWORD;
+typedef unsigned int UINT;
+typedef BYTE DSTATUS;
+typedef enum {
+    RES_OK = 0, /* 0: Successful */
+    RES_ERROR,  /* 1: R/W Error */
+    RES_WRPRT,  /* 2: Write Protected */
+    RES_NOTRDY, /* 3: Not Ready */
+    RES_PARERR  /* 4: Invalid Parameter */
+} DRESULT;
+
+typedef enum {
+    READ_DATA_FROM_CACHE = 0,       //date:2048 bytes in each page
+    READ_SPARE_DATA_FROM_CACHE = 1, //spare date:64 bytes in each page
+} BL_Nand_Flash_READ_DATE_TYPE;
+
 typedef struct
 {
-    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap,bit5:32-bits addr mode support */
+    uint8_t ioMode;               /*!< Serail flash interface mode,bit0-3:IF mode,bit4:unwrap */
     uint8_t cReadSupport;         /*!< Support continuous read mode,bit0:continuous read mode support,bit1:read mode cfg */
     uint8_t clkDelay;             /*!< SPI clock delay,bit0-3:delay,bit4-6:pad delay */
     uint8_t clkInvert;            /*!< SPI clock phase invert,bit0:clck invert,bit1:rx invert,bit2-4:pad delay,bit5-7:pad delay */
@@ -66,19 +101,24 @@ typedef struct
     uint8_t resetCreadCmdSize;    /*!< Flash reset continuous read command size */
     uint8_t jedecIdCmd;           /*!< JEDEC ID command */
     uint8_t jedecIdCmdDmyClk;     /*!< JEDEC ID command dummy clock */
-    uint8_t enter32BitsAddrCmd;   /*!< Enter 32-bits addr command */
-    uint8_t exit32BitsAddrCmd;    /*!< Exit 32-bits addr command */
+    uint8_t qpiJedecIdCmd;        /*!< QPI JEDEC ID comamnd */
+    uint8_t qpiJedecIdCmdDmyClk;  /*!< QPI JEDEC ID command dummy clock */
     uint8_t sectorSize;           /*!< *1024bytes */
     uint8_t mid;                  /*!< Manufacturer ID */
     uint16_t pageSize;            /*!< Page size */
     uint8_t chipEraseCmd;         /*!< Chip erase cmd */
     uint8_t sectorEraseCmd;       /*!< Sector erase command */
-    uint8_t blk32EraseCmd;        /*!< Block 32K erase command,some Micron not support */
-    uint8_t blk64EraseCmd;        /*!< Block 64K erase command */
+    uint8_t blk128EraseCmd;       /*!< Block 128K erase command */
     uint8_t writeEnableCmd;       /*!< Need before every erase or program */
+    uint8_t programLoadCmd;       /*!< Program Load cmd */
+    uint8_t qprogramLoadCmd;      /*!< Program Load cmd x4*/
     uint8_t pageProgramCmd;       /*!< Page program cmd */
     uint8_t qpageProgramCmd;      /*!< QIO page program cmd */
     uint8_t qppAddrMode;          /*!< QIO page program address mode */
+    uint8_t pageReadToCacheCmd;   /*!< Page read comamnd */
+    uint8_t getFeaturesCmd;       /*!< GET FEATURES command to read the status */
+    uint8_t setFeaturesCmd;       /*!< SET FEATURES command to read the status */
+    uint8_t readFromCacheCmd;     /*!< Read from cache command */
     uint8_t fastReadCmd;          /*!< Fast read command */
     uint8_t frDmyClk;             /*!< Fast read command dummy clock */
     uint8_t qpiFastReadCmd;       /*!< QPI fast read command */
@@ -122,97 +162,35 @@ typedef struct
     uint8_t deBurstWrapDataMode;  /*!< Data and address mode for this command */
     uint8_t deBurstWrapData;      /*!< Data to disable burst wrap */
     uint16_t timeEsector;         /*!< 4K erase time */
-    uint16_t timeE32k;            /*!< 32K erase time */
-    uint16_t timeE64k;            /*!< 64K erase time */
+    uint16_t timeE132k;           /*!< 132K erase time */
     uint16_t timePagePgm;         /*!< Page program time */
     uint16_t timeCe;              /*!< Chip erase time in ms */
     uint8_t pdDelay;              /*!< Release power down command delay time for wake up */
     uint8_t qeData;               /*!< QE set data */
-} __attribute__((packed)) SPI_Flash_Cfg_Type;
+} __attribute__((packed)) Nand_Flash_Cfg_Type;
 
-/**
- *  @brief Serial flash security register configuration
- */
-typedef struct
-{
-    uint8_t eraseCmd;       /*!< Erase security register command */
-    uint8_t programCmd;     /*!< Program security register command */
-    uint8_t readCmd;        /*!< Read security register command */
-    uint8_t enterSecOptCmd; /*!< Enter security register option mode command */
-    uint8_t exitSecOptCmd;  /*!< Exit security register option mode command */
-    uint8_t blockNum;       /*!< Security register block number */
-    uint8_t *data;          /*!< Data pointer to be program/read */
-    uint32_t addr;          /*!< Start address to be program/read */
-    uint32_t len;           /*!< Data length to be program/read */
-} SFlash_Sec_Reg_Cfg;
-/*@} end of group SFLAH_Public_Types */
-
-/** @defgroup  SFLAH_Public_Constants
- *  @{
- */
-
-/*@} end of group SFLAH_Public_Constants */
-
-/** @defgroup  SFLAH_Public_Macros
- *  @{
- */
-#define BFLB_SPIFLASH_BLK32K_SIZE (32 * 1024)
-#define BFLB_SPIFLASH_BLK64K_SIZE (64 * 1024)
-#define BFLB_SPIFLASH_CMD_INVALID 0xff
-
-/*@} end of group SFLAH_Public_Macros */
-
-/** @defgroup  SFLAH_Public_Functions
- *  @{
- */
-void ATTR_TCM_SECTION SFlash_Init(const SF_Ctrl_Cfg_Type *pSfCtrlCfg, const SF_Ctrl_Bank2_Cfg *pBank2Cfg);
-BL_Err_Type SFlash_SetSPIMode(SF_Ctrl_Mode_Type mode);
-BL_Err_Type SFlash_Read_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
-BL_Err_Type SFlash_Write_Reg(SPI_Flash_Cfg_Type *flashCfg, uint8_t regIndex, uint8_t *regValue, uint8_t regLen);
-BL_Err_Type SFlash_Read_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t readRegCmd, uint8_t *regValue,
-                                     uint8_t regLen);
-BL_Err_Type SFlash_Write_Reg_With_Cmd(SPI_Flash_Cfg_Type *flashCfg, uint8_t writeRegCmd, uint8_t *regValue,
-                                      uint8_t regLen);
-BL_Sts_Type SFlash_Busy(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Qspi_Enable(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Qspi_Disable(SPI_Flash_Cfg_Type *flashCfg);
-void SFlash_Volatile_Reg_Write_Enable(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Chip_Erase(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Sector_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t secNum);
-BL_Err_Type SFlash_Blk32_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
-BL_Err_Type SFlash_Blk64_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t blkNum);
-BL_Err_Type SFlash_Erase(SPI_Flash_Cfg_Type *flashCfg, uint32_t startaddr, uint32_t endaddr);
-void SFlash_GetUniqueId(uint8_t *data, uint8_t idLen);
-void SFlash_GetJedecId(SPI_Flash_Cfg_Type *flashCfg, uint8_t *data);
-void SFlash_GetDeviceId(uint8_t *data, BL_Fun_Type is32BitsAddr);
-void SFlash_Powerdown(void);
-void SFlash_Release_Powerdown(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Restore_From_Powerdown(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t flashContRead,
-                                          SF_Ctrl_Bank_Select bank);
-void SFlash_SetBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
-void SFlash_DisableBurstWrap(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Set32BitsAddrMode(SPI_Flash_Cfg_Type *flashCfg, BL_Fun_Type en32BitsAddr);
-BL_Err_Type SFlash_Software_Reset(SPI_Flash_Cfg_Type *flashCfg);
-void SFlash_Reset_Continue_Read(SPI_Flash_Cfg_Type *flashCfg);
-BL_Err_Type SFlash_Set_IDbus_Cfg(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr,
-                                 uint32_t len, SF_Ctrl_Bank_Select bank);
-BL_Err_Type SFlash_IDbus_Read_Enable(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead,
-                                     SF_Ctrl_Bank_Select bank);
-void SFlash_IDbus_Read_Disable(void);
-BL_Err_Type SFlash_RCV_Enable(SPI_Flash_Cfg_Type *pFlashCfg, uint8_t rCmd, uint8_t wCmd, uint8_t bitPos);
-BL_Err_Type SFlash_Erase_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg, SFlash_Sec_Reg_Cfg *pSecRegCfg);
-BL_Err_Type SFlash_Program_Security_Register(SPI_Flash_Cfg_Type *pFlashCfg,
-                                             SFlash_Sec_Reg_Cfg *pSecRegCfg);
-BL_Err_Type SFlash_Read_Security_Register(SFlash_Sec_Reg_Cfg *pSecRegCfg);
-BL_Err_Type SFlash_Read(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint8_t contRead, uint32_t addr, uint8_t *data,
-                        uint32_t len);
-BL_Err_Type SFlash_Program(SPI_Flash_Cfg_Type *flashCfg, SF_Ctrl_IO_Type ioMode, uint32_t addr, uint8_t *data, uint32_t len);
+//BL_Nand_Flash_Program_Bit_Err_Type ATTR_TCM_SECTION NFlash_Pass(uint8_t errorCode, BL_Nand_Flash_OP_Type opType);
+BL_Err_Type NFlash_GetJedecId(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t startAddr, uint32_t endAddr);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Blk128_Erase(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Write_Enable(Nand_Flash_Cfg_Type *flashCfg);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Read(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Program(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Page_Read_To_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t absolutePageNum);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Get_Feature(Nand_Flash_Cfg_Type *flashCfg, uint8_t *data, uint8_t cmdType);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Read_From_Cache(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t readType);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Execute(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Set_Feature(Nand_Flash_Cfg_Type *flashCfg);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Program_Load(Nand_Flash_Cfg_Type *flashCfg, uint32_t addr, const uint8_t *data, uint32_t len);
+BL_Err_Type ATTR_TCM_SECTION NFlash_Check_Bad_Block(Nand_Flash_Cfg_Type *flashCfg, uint32_t blockNum, uint8_t *data, uint32_t len);
+DRESULT ff_disk_read(BYTE pdrv, BYTE *buff, DWORD sector, UINT count);
+DRESULT ff_disk_write(BYTE pdrv, const BYTE *buff, DWORD sector, UINT count);
+DSTATUS ff_disk_initialize(BYTE pdrv);
 
 /*@} end of group SFLAH_Public_Functions */
 
 /*@} end of group SFLAH */
 
-/*@} end of group BL808_Peripheral_Driver */
+/*@} end of group BL602_Peripheral_Driver */
 
-#endif /* __BL808_SFLAH_H__ */
+#endif /* __BL602_SFLAH_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_pds.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_pds.h
new file mode 100755
index 0000000000..f6ab168cee
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_pds.h
@@ -0,0 +1,802 @@
+/**
+  ******************************************************************************
+  * @file    bl702_pds.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_PDS_H__
+#define __BL702_PDS_H__
+
+#include "pds_reg.h"
+#include "bl702_ef_ctrl.h"
+#include "bl702_aon.h"
+#include "bl702_hbn.h"
+#include "bl702_common.h"
+#include "bflb_sflash.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief PDS LDO level type definition
+ */
+typedef enum {
+    PDS_LDO_LEVEL_0P60V = 0,  /*!< PDS LDO voltage 0.60V */
+    PDS_LDO_LEVEL_0P65V = 1,  /*!< PDS LDO voltage 0.65V */
+    PDS_LDO_LEVEL_0P70V = 2,  /*!< PDS LDO voltage 0.70V */
+    PDS_LDO_LEVEL_0P75V = 3,  /*!< PDS LDO voltage 0.75V */
+    PDS_LDO_LEVEL_0P80V = 4,  /*!< PDS LDO voltage 0.80V */
+    PDS_LDO_LEVEL_0P85V = 5,  /*!< PDS LDO voltage 0.85V */
+    PDS_LDO_LEVEL_0P90V = 6,  /*!< PDS LDO voltage 0.90V */
+    PDS_LDO_LEVEL_0P95V = 7,  /*!< PDS LDO voltage 0.95V */
+    PDS_LDO_LEVEL_1P00V = 8,  /*!< PDS LDO voltage 1.00V */
+    PDS_LDO_LEVEL_1P05V = 9,  /*!< PDS LDO voltage 1.05V */
+    PDS_LDO_LEVEL_1P10V = 10, /*!< PDS LDO voltage 1.10V */
+    PDS_LDO_LEVEL_1P15V = 11, /*!< PDS LDO voltage 1.15V */
+    PDS_LDO_LEVEL_1P20V = 12, /*!< PDS LDO voltage 1.20V */
+    PDS_LDO_LEVEL_1P25V = 13, /*!< PDS LDO voltage 1.25V */
+    PDS_LDO_LEVEL_1P30V = 14, /*!< PDS LDO voltage 1.30V */
+    PDS_LDO_LEVEL_1P35V = 15, /*!< PDS LDO voltage 1.35V */
+} PDS_LDO_LEVEL_Type;
+
+/**
+ *  @brief PDS RAM configuration type definition
+ */
+typedef struct
+{
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET1N  : 1;  /*!< [0] 0~16KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET1N : 1;  /*!< [1] 16~32KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET1N : 1;  /*!< [2] 32~48KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET1N : 1;  /*!< [3] 48~64KB cpu_ram RET1N */
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_RET2N  : 1;  /*!< [4] 0~16KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_RET2N : 1;  /*!< [5] 16~32KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_RET2N : 1;  /*!< [6] 32~48KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_RET2N : 1;  /*!< [7] 48~64KB cpu_ram RET2N */
+    uint32_t PDS_RAM_CFG_0KB_16KB_CPU_RAM_PGEN   : 1;  /*!< [8] 0~16KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_16KB_32KB_CPU_RAM_PGEN  : 1;  /*!< [9] 16~32KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_32KB_48KB_CPU_RAM_PGEN  : 1;  /*!< [10] 32~48KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_48KB_64KB_CPU_RAM_PGEN  : 1;  /*!< [11] 48~64KB cpu_ram PGEN */
+    uint32_t PDS_RAM_CFG_RSV                     : 20; /*!< [31:12]reserve */
+} PDS_RAM_CFG_Type;
+
+/**
+ *  @brief PDS PAD pin configuration type definition
+ */
+typedef enum {
+    PDS_PAD_PIN_GPIO_17, /*!< PAD GPIO 17 */
+    PDS_PAD_PIN_GPIO_18, /*!< PAD GPIO 18 */
+    PDS_PAD_PIN_GPIO_19, /*!< PAD GPIO 19 */
+    PDS_PAD_PIN_GPIO_20, /*!< PAD GPIO 20 */
+    PDS_PAD_PIN_GPIO_21, /*!< PAD GPIO 21 */
+    PDS_PAD_PIN_GPIO_22, /*!< PAD GPIO 22 */
+    PDS_PAD_PIN_GPIO_23, /*!< PAD GPIO 23 */
+    PDS_PAD_PIN_GPIO_24, /*!< PAD GPIO 24 */
+    PDS_PAD_PIN_GPIO_25, /*!< PAD GPIO 25 */
+    PDS_PAD_PIN_GPIO_26, /*!< PAD GPIO 26 */
+    PDS_PAD_PIN_GPIO_27, /*!< PAD GPIO 27 */
+    PDS_PAD_PIN_GPIO_28, /*!< PAD GPIO 28 */
+} PDS_PAD_PIN_Type;
+
+/**
+ *  @brief PDS PAD configuration type definition
+ */
+typedef enum {
+    PDS_PAD_CFG_PULL_NONE, /*!< no PD/PU/IE on PAD */
+    PDS_PAD_CFG_PULL_DOWN, /*!< Pulldown PAD */
+    PDS_PAD_CFG_PULL_UP,   /*!< Pullup PAD */
+    PDS_PAD_CFG_ACTIVE_IE, /*!< Active IE */
+} PDS_PAD_CFG_Type;
+
+/**
+ *  @brief PDS configuration type definition
+ */
+typedef struct
+{
+    uint32_t pdsStart                : 1; /*!< [0]PDS Start */
+    uint32_t sleepForever            : 1; /*!< [1]PDS sleep forever */
+    uint32_t xtalForceOff            : 1; /*!< [2]Power off xtal force */
+    uint32_t saveWifiState           : 1; /*!< [3]Save WIFI State Before Enter PDS */
+    uint32_t dcdc18Off               : 1; /*!< [4]power down dcdc18 during PDS */
+    uint32_t bgSysOff                : 1; /*!< [5]power down bg_sys during PDS */
+    uint32_t gpioIePuPd              : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */
+    uint32_t puFlash                 : 1; /*!< [7]turn off Flash Power During PDS */
+    uint32_t clkOff                  : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
+    uint32_t memStby                 : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
+    uint32_t swPuFlash               : 1; /*!< [10]SW Turn on Flash */
+    uint32_t isolation               : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
+    uint32_t waitXtalRdy             : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
+    uint32_t pdsPwrOff               : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
+    uint32_t xtalOff                 : 1; /*!< [14]xtal power down during PDS */
+    uint32_t socEnbForceOn           : 1; /*!< [15]pds_soc_enb always active */
+    uint32_t pdsRstSocEn             : 1; /*!< [16]pds_rst controlled by PDS */
+    uint32_t pdsRC32mOn              : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
+    uint32_t pdsLdoVselEn            : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
+    uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */
+    uint32_t reserved20              : 1; /*!< [20]Reserved */
+    uint32_t cpu0WfiMask             : 1; /*!< [21]pds start condition mask np_wfi */
+    uint32_t ldo11Off                : 1; /*!< [22]power down ldo11 during PDS */
+    uint32_t pdsForceRamClkEn        : 1; /*!< [23]Force SRAM CLK Enable */
+    uint32_t pdsLdoVol               : 4; /*!< [27:24]LDO voltage value in PDS mode */
+    uint32_t pdsCtlRfSel             : 2; /*!< [29:28]select the way RF controlled by PDS */
+    uint32_t pdsCtlPllSel            : 2; /*!< [31:30]select the way PLL controlled by PDS */
+} PDS_CFG_Type;
+
+/**
+ *  @brief PDS configuration type definition
+ */
+typedef struct
+{
+    uint32_t pdsStart                : 1; /*!< [0]PDS Start */
+    uint32_t sleepForever            : 1; /*!< [1]PDS sleep forever */
+    uint32_t xtalForceOff            : 1; /*!< [2]Power off xtal force */
+    uint32_t saveWifiState           : 1; /*!< [3]Save WIFI State Before Enter PDS */
+    uint32_t dcdc18Off               : 1; /*!< [4]power down dcdc18 during PDS */
+    uint32_t bgSysOff                : 1; /*!< [5]power down bg_sys during PDS */
+    uint32_t gpioIePuPd              : 1; /*!< [6]allow PDS Control the GPIO IE/PU/PD at Sleep Mode */
+    uint32_t puFlash                 : 1; /*!< [7]turn off Flash Power During PDS */
+    uint32_t clkOff                  : 1; /*!< [8]gate clock during PDS (each pwr domain has its own control) */
+    uint32_t memStby                 : 1; /*!< [9]mem_stby during PDS (each power domain can has its own control) */
+    uint32_t swPuFlash               : 1; /*!< [10]SW Turn on Flash */
+    uint32_t isolation               : 1; /*!< [11]Isolation during PDS (each power domain can has its own control) */
+    uint32_t waitXtalRdy             : 1; /*!< [12]wait XTAL Ready during before PDS Interrupt */
+    uint32_t pdsPwrOff               : 1; /*!< [13]Power off during PDS (each power domain can has its own control) */
+    uint32_t xtalOff                 : 1; /*!< [14]xtal power down during PDS */
+    uint32_t socEnbForceOn           : 1; /*!< [15]pds_soc_enb always active */
+    uint32_t pdsRstSocEn             : 1; /*!< [16]pds_rst controlled by PDS */
+    uint32_t pdsRC32mOn              : 1; /*!< [17]RC32M always on or RC32M on/off controlled by PDS state */
+    uint32_t pdsLdoVselEn            : 1; /*!< [18]PDS "SLEEP" control LDO voltage enable */
+    uint32_t pdsRamLowPowerWithClkEn : 1; /*!< [19]Control SRAM Low Power with CLK (Sync) */
+    uint32_t reserved20              : 1; /*!< [20]Reserved */
+    uint32_t cpu0WfiMask             : 1; /*!< [21]pds start condition mask np_wfi */
+    uint32_t ldo11Off                : 1; /*!< [22]power down ldo11 during PDS */
+    uint32_t pdsForceRamClkEn        : 1; /*!< [23]Force SRAM CLK Enable */
+    uint32_t pdsLdoVol               : 4; /*!< [27:24]LDO voltage value in PDS mode */
+    uint32_t pdsCtlRfSel             : 2; /*!< [29:28]select the way RF controlled by PDS */
+    uint32_t pdsCtlPllSel            : 2; /*!< [31:30]select the way PLL controlled by PDS */
+} PDS_CTL_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t forceCpuPwrOff  : 1;  /*!< [0]manual force NP power off */
+    uint32_t rsv1            : 1;  /*!< [1]reserve */
+    uint32_t forceBzPwrOff   : 1;  /*!< [2]manual force BZ power off */
+    uint32_t forceUsbPwrOff  : 1;  /*!< [3]manual force USB power off */
+    uint32_t forceCpuIsoEn   : 1;  /*!< [4]manual force NP isolation */
+    uint32_t rsv5            : 1;  /*!< [5]reserve */
+    uint32_t forceBzIsoEn    : 1;  /*!< [6]manual force BZ isolation */
+    uint32_t forceUsbIsoEn   : 1;  /*!< [7]manual force USB isolation */
+    uint32_t forceCpuPdsRst  : 1;  /*!< [8]manual force NP pds reset */
+    uint32_t rsv9            : 1;  /*!< [9]reserve */
+    uint32_t forceBzPdsRst   : 1;  /*!< [10]manual force BZ pds reset */
+    uint32_t forceUsbPdsRst  : 1;  /*!< [11]manual force USB pds reset */
+    uint32_t forceCpuMemStby : 1;  /*!< [12]manual force NP memory sleep */
+    uint32_t rsv13           : 1;  /*!< [13]reserve */
+    uint32_t forceBzMemStby  : 1;  /*!< [14]manual force BZ memory sleep */
+    uint32_t forceUsbMemStby : 1;  /*!< [15]manual force USB memory sleep */
+    uint32_t forceCpuGateClk : 1;  /*!< [16]manual force NP clock gated */
+    uint32_t rsv17           : 1;  /*!< [17]reserve */
+    uint32_t forceBzGateClk  : 1;  /*!< [18]manual force BZ clock gated */
+    uint32_t forceUsbGateClk : 1;  /*!< [19]manual force USB clock gated */
+    uint32_t rsv20_31        : 12; /*!< [31:20]reserve */
+} PDS_CTL2_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t rsv0             : 1; /*!< [0]reserve */
+    uint32_t forceMiscPwrOff  : 1; /*!< [1]manual force MISC pwr_off */
+    uint32_t forceBlePwrOff   : 1; /*!< [2]manual force BZ_BLE pwr_off */
+    uint32_t rsv3_4           : 2; /*!< [4:3]reserve */
+    uint32_t forceBleIsoEn    : 1; /*!< [5]manual force BZ_BLE iso_en */
+    uint32_t rsv6             : 1; /*!< [6]reserve */
+    uint32_t forceMiscPdsRst  : 1; /*!< [7]manual force MISC pds_rst */
+    uint32_t forceBlePdsRst   : 1; /*!< [8]manual force BZ_BLE pds_rst */
+    uint32_t rsv9             : 1; /*!< [9]reserve */
+    uint32_t forceMiscMemStby : 1; /*!< [10]manual force MISC mem_stby */
+    uint32_t forceBleMemStby  : 1; /*!< [11]manual force BZ_BLE mem_stby */
+    uint32_t rsv12            : 1; /*!< [12]reserve */
+    uint32_t forceMiscGateClk : 1; /*!< [13]manual force MISC gate_clk */
+    uint32_t forceBleGateClk  : 1; /*!< [14]manual force BZ_BLE gate_clk */
+    uint32_t rsv15_23         : 9; /*!< [23:15]reserve */
+    uint32_t CpuIsoEn         : 1; /*!< [24]make NP isolated at PDS Sleep state */
+    uint32_t rsv25_26         : 2; /*!< [26:25]reserve */
+    uint32_t BzIsoEn          : 1; /*!< [27]make BZ isolated at PDS Sleep state */
+    uint32_t BleIsoEn         : 1; /*!< [28]make Ble isolated at PDS Sleep state */
+    uint32_t UsbIsoEn         : 1; /*!< [29]make USB isolated at PDS Sleep state */
+    uint32_t MiscIsoEn        : 1; /*!< [30]make misc isolated at PDS Sleep state */
+    uint32_t rsv31            : 1; /*!< [31]reserve */
+} PDS_CTL3_Type;
+
+/**
+ *  @brief PDS force configuration type definition
+ */
+typedef struct
+{
+    uint32_t cpuPwrOff     : 1; /*!< [0] */
+    uint32_t cpuRst        : 1; /*!< [1] */
+    uint32_t cpuMemStby    : 1; /*!< [2] */
+    uint32_t cpuGateClk    : 1; /*!< [3] */
+    uint32_t rsv4_11       : 8; /*!< [11:4]reserve */
+    uint32_t BzPwrOff      : 1; /*!< [12] */
+    uint32_t BzRst         : 1; /*!< [13] */
+    uint32_t BzMemStby     : 1; /*!< [14] */
+    uint32_t BzGateClk     : 1; /*!< [15] */
+    uint32_t BlePwrOff     : 1; /*!< [16] */
+    uint32_t BleRst        : 1; /*!< [17] */
+    uint32_t BleMemStby    : 1; /*!< [18] */
+    uint32_t BleGateClk    : 1; /*!< [19] */
+    uint32_t UsbPwrOff     : 1; /*!< [20] */
+    uint32_t UsbRst        : 1; /*!< [21] */
+    uint32_t UsbMemStby    : 1; /*!< [22] */
+    uint32_t UsbGateClk    : 1; /*!< [23] */
+    uint32_t MiscPwrOff    : 1; /*!< [24] */
+    uint32_t MiscRst       : 1; /*!< [25] */
+    uint32_t MiscMemStby   : 1; /*!< [26] */
+    uint32_t MiscGateClk   : 1; /*!< [27] */
+    uint32_t rsv28_29      : 2; /*!< [29:28]reserve */
+    uint32_t MiscAnaPwrOff : 1; /*!< [30] */
+    uint32_t MiscDigPwrOff : 1; /*!< [31] */
+} PDS_CTL4_Type;
+
+/**
+ *  @brief PDS default level configuration type definition
+ */
+typedef struct
+{
+    PDS_CTL_Type pdsCtl;   /*!< PDS_CTL configuration */
+    PDS_CTL2_Type pdsCtl2; /*!< PDS_CTL2 configuration */
+    PDS_CTL3_Type pdsCtl3; /*!< PDS_CTL3 configuration */
+    PDS_CTL4_Type pdsCtl4; /*!< PDS_CTL4 configuration */
+} PDS_DEFAULT_LV_CFG_Type;
+
+/**
+ *  @brief PDS interrupt type definition
+ */
+typedef enum {
+    PDS_INT_WAKEUP = 0,    /*!< PDS wakeup interrupt(assert bit while wakeup, include PDS_Timer/...) */
+    PDS_INT_RF_DONE,       /*!< PDS RF done interrupt */
+    PDS_INT_PLL_DONE,      /*!< PDS PLL done interrupt */
+    PDS_INT_PDS_SLEEP_CNT, /*!< wakeup trigger by pds_sleep_cnt=0 */
+    PDS_INT_HBN_IRQ_OUT0,  /*!< wakeup trigger by hbn_irq_out[0] */
+    PDS_INT_HBN_IRQ_OUT1,  /*!< wakeup trigger by hbn_irq_out[1] */
+    PDS_INT_GPIO_IRQ,      /*!< wakeup trigger by gpio_irq */
+    PDS_INT_IRRX,          /*!< wakeup trigger by irrx_int */
+    PDS_INT_BLE_SLP_IRQ,   /*!< wakeup trigger by ble_slp_irq */
+    PDS_INT_USB_WKUP,      /*!< wakeup trigger by usb_wkup */
+    PDS_INT_KYS_QDEC,      /*!< wakeup trigger by kys_int or qdec */
+    PDS_INT_MAX,           /*!< PDS int max number */
+} PDS_INT_Type;
+
+/**
+ *  @brief PDS vddcore GPIO interrupt type definition
+ */
+typedef enum {
+    PDS_VDDCORE_GPIO_SRC_GPIO_0, /*!< PDS VDDCORE GPIO0 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_1, /*!< PDS VDDCORE GPIO1 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_2, /*!< PDS VDDCORE GPIO2 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_3, /*!< PDS VDDCORE GPIO3 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_4, /*!< PDS VDDCORE GPIO4 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_5, /*!< PDS VDDCORE GPIO5 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_6, /*!< PDS VDDCORE GPIO6 as PDS interrupt source */
+    PDS_VDDCORE_GPIO_SRC_GPIO_7, /*!< PDS VDDCORE GPIO7 as PDS interrupt source */
+} PDS_VDDCORE_GPIO_SRC_Type;
+
+/**
+ *  @brief PDS reset event type definition
+ */
+typedef enum {
+    PDS_RST_EVENT_BUS_RST,        /*!< hreset_n (Bus Reset) */
+    PDS_RST_EVENT_HBN_PWR_ON_RST, /*!< pwr_rst_n (hbn power on reset) */
+    PDS_RST_EVENT_PDS_RST,        /*!< pds_rst_n (pds reset) */
+    PDS_RST_EVENT_MAX,            /*!< PDS rst event max number */
+} PDS_RST_EVENT_Type;
+
+/**
+ *  @brief PDS PLL status type definition
+ */
+typedef enum {
+    PDS_PLL_STS_OFF = 0,   /*!< 2'b00 */
+    PDS_PLL_STS_SFREG = 1, /*!< 2'b01 */
+    PDS_PLL_STS_PU = 2,    /*!< 2'b10 */
+    PDS_PLL_STS_RDY = 3,   /*!< 2'b11 */
+} PDS_PLL_STS_Type;
+
+/**
+ *  @brief PDS RF status type definition
+ */
+typedef enum {
+    PDS_RF_STS_OFF = 0,        /*!< 4'b0000 */
+    PDS_RF_STS_PU_MBG = 1,     /*!< 4'b0001 */
+    PDS_RF_STS_PU_LDO15RF = 3, /*!< 4'b0011 */
+    PDS_RF_STS_PU_SFREG = 7,   /*!< 4'b0111 */
+    PDS_RF_STS_BZ_EN_AON = 15, /*!< 4'b1111 */
+} PDS_RF_STS_Type;
+
+/**
+ *  @brief PDS status type definition
+ */
+typedef enum {
+    PDS_STS_IDLE = 0,            /*!< 4'b0000 */
+    PDS_STS_ECG = 8,             /*!< 4'b1000 */
+    PDS_STS_ERST = 12,           /*!< 4'b1100 */
+    PDS_STS_EISO = 15,           /*!< 4'b1111 */
+    PDS_STS_POFF = 7,            /*!< 4'b0111 */
+    PDS_STS_PRE_BGON = 3,        /*!< 4'b0011 */
+    PDS_STS_PRE_BGON1 = 1,       /*!< 4'b0001 */
+    PDS_STS_BGON = 5,            /*!< 4'b0101 */
+    PDS_STS_CLK_SW_32M = 4,      /*!< 4'b0100 */
+    PDS_STS_PON_DCDC = 6,        /*!< 4'b0110 */
+    PDS_STS_PON_LDO11_MISC = 14, /*!< 4'b1110 */
+    PDS_STS_PON = 10,            /*!< 4'b1010 */
+    PDS_STS_DISO = 2,            /*!< 4'b0010 */
+    PDS_STS_DCG = 13,            /*!< 4'b1101 */
+    PDS_STS_DRST = 11,           /*!< 4'b1011 */
+    PDS_STS_WAIT_EFUSE = 9,      /*!< 4'b1001 */
+} PDS_STS_Type;
+
+/**
+ *  @brief PLL XTAL type definition
+ */
+typedef enum {
+    PDS_PLL_XTAL_NONE,  /*!< XTAL is none */
+    PDS_PLL_XTAL_32M,   /*!< XTAL is 32M */
+    PDS_PLL_XTAL_RC32M, /*!< XTAL is RC32M */
+} PDS_PLL_XTAL_Type;
+
+/**
+ *  @brief PLL output clock type definition
+ */
+typedef enum {
+    PDS_PLL_CLK_480M, /*!< PLL output clock:480M */
+    PDS_PLL_CLK_240M, /*!< PLL output clock:240M */
+    PDS_PLL_CLK_192M, /*!< PLL output clock:192M */
+    PDS_PLL_CLK_160M, /*!< PLL output clock:160M */
+    PDS_PLL_CLK_120M, /*!< PLL output clock:120M */
+    PDS_PLL_CLK_96M,  /*!< PLL output clock:96M */
+    PDS_PLL_CLK_80M,  /*!< PLL output clock:80M */
+    PDS_PLL_CLK_48M,  /*!< PLL output clock:48M */
+    PDS_PLL_CLK_32M,  /*!< PLL output clock:32M */
+} PDS_PLL_CLK_Type;
+
+/**
+ *  @brief PDS level 0-7 mode HBN GPIO interrupt trigger type definition
+ */
+typedef enum {
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE,  /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE,   /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL,     /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL,    /*!< PDS level 0-7 mode HBN GPIO INT trigger type: sync high level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE, /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async falling edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE,  /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async rising edge trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL,    /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async low level trigger */
+    PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL,   /*!< PDS level 0-7 mode HBN GPIO INT trigger type: async high level trigger */
+} PDS_AON_GPIO_INT_Trigger_Type;
+
+/**
+ *  @brief PDS APP configuration type definition
+ */
+typedef struct
+{
+    uint8_t pdsLevel;                                 /*!< PDS level */
+    uint8_t turnOffXtal32m;                           /*!< Wheather turn off XTAL32M */
+    uint8_t turnOffDll;                               /*!< Wheather turn off DLL */
+    uint8_t turnOffRF;                                /*!< Wheather turn off RF */
+    uint8_t useXtal32k;                               /*!< Wheather use xtal 32K as 32K clock source,otherwise use rc32k */
+    uint8_t pdsAonGpioWakeupSrc;                      /*!< PDS level 0-7,31 mode aon GPIO Wakeup source(HBN wakeup pin) */
+    PDS_AON_GPIO_INT_Trigger_Type pdsAonGpioTrigType; /*!< PDS level 0-7,31 mode aon GPIO Triger type(HBN wakeup pin) */
+    uint8_t powerDownFlash;                           /*!< Whether power down flash */
+    uint8_t pdsHoldGpio;                              /*!< Whether pds hold gpio level */
+    uint8_t turnOffFlashPad;                          /*!< Whether turn off flash pad(GPIO17-GPIO22, GPIO23-GPIO28) */
+    uint8_t flashPinCfg;                              /*!< 0 ext flash 23-28, 1 internal flash 23-28, 2 internal flash 23-28, 3 ext flash 17-22 */
+    uint8_t turnoffPLL;                               /*!< Whether trun off PLL */
+    uint8_t xtalType;                                 /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
+    uint8_t flashContRead;                            /*!< Whether enable flash continue read */
+    uint32_t sleepTime;                               /*!< PDS sleep time */
+    spi_flash_cfg_type *flashCfg;                     /*!< Flash config pointer, used when power down flash */
+    HBN_LDO_LEVEL_Type ldoLevel;                      /*!< LDO level */
+    void (*preCbFun)(void);                           /*!< Pre callback function */
+    void (*postCbFun)(void);                          /*!< Post callback function */
+} PDS_APP_CFG_Type;
+
+/**
+ *  @brief PDS LDO voltage type definition
+ */
+typedef enum {
+    PDS_LDO_VOLTAGE_0P60V, /*!< PDS LDO voltage 0.60V */
+    PDS_LDO_VOLTAGE_0P65V, /*!< PDS LDO voltage 0.65V */
+    PDS_LDO_VOLTAGE_0P70V, /*!< PDS LDO voltage 0.70V */
+    PDS_LDO_VOLTAGE_0P75V, /*!< PDS LDO voltage 0.75V */
+    PDS_LDO_VOLTAGE_0P80V, /*!< PDS LDO voltage 0.80V */
+    PDS_LDO_VOLTAGE_0P85V, /*!< PDS LDO voltage 0.85V */
+    PDS_LDO_VOLTAGE_0P90V, /*!< PDS LDO voltage 0.9V */
+    PDS_LDO_VOLTAGE_0P95V, /*!< PDS LDO voltage 0.95V */
+    PDS_LDO_VOLTAGE_1P00V, /*!< PDS LDO voltage 1.0V */
+    PDS_LDO_VOLTAGE_1P05V, /*!< PDS LDO voltage 1.05V */
+    PDS_LDO_VOLTAGE_1P10V, /*!< PDS LDO voltage 1.1V */
+    PDS_LDO_VOLTAGE_1P15V, /*!< PDS LDO voltage 1.15V */
+    PDS_LDO_VOLTAGE_1P20V, /*!< PDS LDO voltage 1.2V */
+    PDS_LDO_VOLTAGE_1P25V, /*!< PDS LDO voltage 1.25V */
+    PDS_LDO_VOLTAGE_1P30V, /*!< PDS LDO voltage 1.3V */
+    PDS_LDO_VOLTAGE_1P35V, /*!< PDS LDO voltage 1.35V */
+} PDS_LDO_VOLTAGE_Type;
+
+/**
+ *  @brief PDS auto power down configuration type definition
+ */
+typedef struct
+{
+    BL_Fun_Type mbgPower;      /*!< PDS auto [31] MBG power */
+    BL_Fun_Type ldo18rfPower;  /*!< PDS auto [30] LDO18RF power */
+    BL_Fun_Type sfregPower;    /*!< PDS auto [29] SF_REG power */
+    BL_Fun_Type pllPower;      /*!< PDS auto [28] PLL power */
+    BL_Fun_Type cpu0Power;     /*!< PDS auto [19] NP power */
+    BL_Fun_Type rc32mPower;    /*!< PDS auto [17] RC32M power */
+    BL_Fun_Type xtalPower;     /*!< PDS auto [14] XTAL power */
+    BL_Fun_Type allPower;      /*!< PDS auto [13] all power */
+    BL_Fun_Type isoPower;      /*!< PDS auto [11] ISO power */
+    BL_Fun_Type bzPower;       /*!< PDS auto [10] BZ power */
+    BL_Fun_Type sramDisStanby; /*!< PDS auto [9] SRAM memory stanby disable */
+    BL_Fun_Type cgPower;       /*!< PDS auto [8] CG power */
+    BL_Fun_Type cpu1Power;     /*!< PDS auto [7] AP power */
+    BL_Fun_Type usbPower;      /*!< PDS auto [3] USB power */
+} PDS_AUTO_POWER_DOWN_CFG_Type;
+
+/**
+ *  @brief PDS auto configuration type definition
+ */
+typedef struct
+{
+    PDS_LDO_VOLTAGE_Type vddcoreVol; /*!< PDS auto [27:24] VDDCORE voltage, reference 0x4001F80C[27:24], recommended 0xA */
+    BL_Fun_Type vddcoreVolEn;        /*!< PDS auto [18] VDDCORE voltage enable bit */
+    BL_Fun_Type cpu0NotNeedWFI;      /*!< PDS auto [21] NP not need WFI to get in PDS mode */
+    BL_Fun_Type cpu1NotNeedWFI;      /*!< PDS auto [20] AP not need WFI to get in PDS mode */
+    BL_Fun_Type busReset;            /*!< PDS auto [16] bus reset bit, reset after wake up from PDS mode */
+    BL_Fun_Type disIrqWakeUp;        /*!< PDS auto [15] disable IRQ request to wake up from PDS mode, except PDS counter IRQ */
+    BL_Fun_Type powerOffXtalForever; /*!< PDS auto [2] power off xtal after get in PDS mode, and never power on xtal after wake up */
+    BL_Fun_Type sleepForever;        /*!< PDS auto [1] sleep forever after get in PDS mode, need reset system to restart */
+} PDS_AUTO_NORMAL_CFG_Type;
+
+/**
+ *  @brief PDS force type definition
+ */
+typedef enum {
+    PDS_FORCE_NP,  /*!< PDS force NP */
+    PDS_FORCE_RSV, /*!< rsv */
+    PDS_FORCE_BZ,  /*!< PDS force BZ */
+    PDS_FORCE_USB, /*!< PDS force USB */
+} PDS_FORCE_Type;
+
+/**
+ *  @brief PDS force type definition
+ */
+typedef enum {
+    AUDIO_PLL_12288000_HZ, /*!< PDS AUDIO PLL SET AS 12.288MHZ */
+    AUDIO_PLL_11289600_HZ, /*!< PDS AUDIO PLL SET AS 11.2896HZ */
+    AUDIO_PLL_5644800_HZ,  /*!< PDS AUDIO PLL SET AS 2.822400HZ */
+    AUDIO_PLL_24576000_HZ, /*!< PDS AUDIO PLL SET AS 24.576000MHZ */
+    AUDIO_PLL_24000000_HZ, /*!< PDS AUDIO PLL SET AS 24.000000MHZ */
+    AUDIO_PLL_50000000_HZ, /*!< PDS AUDIO PLL SET AS 50.000000MHZ */
+} PDS_AUDIO_PLL_Type;
+
+/*@} end of group PDS_Public_Types */
+
+/** @defgroup  PDS_Public_Constants
+ *  @{
+ */
+
+/** @defgroup  PDS_LDO_LEVEL_TYPE
+ *  @{
+ */
+#define IS_PDS_LDO_LEVEL_TYPE(type) (((type) == PDS_LDO_LEVEL_0P60V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P65V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P70V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P75V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P80V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P85V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P90V) || \
+                                     ((type) == PDS_LDO_LEVEL_0P95V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P00V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P05V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P10V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P15V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P20V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P25V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P30V) || \
+                                     ((type) == PDS_LDO_LEVEL_1P35V))
+
+/** @defgroup  PDS_PAD_PIN_TYPE
+ *  @{
+ */
+#define IS_PDS_PAD_PIN_TYPE(type) (((type) == PDS_PAD_PIN_GPIO_17) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_18) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_19) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_20) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_21) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_22) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_23) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_24) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_25) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_26) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_27) || \
+                                   ((type) == PDS_PAD_PIN_GPIO_28))
+
+/** @defgroup  PDS_PAD_CFG_TYPE
+ *  @{
+ */
+#define IS_PDS_PAD_CFG_TYPE(type) (((type) == PDS_PAD_CFG_PULL_NONE) || \
+                                   ((type) == PDS_PAD_CFG_PULL_DOWN) || \
+                                   ((type) == PDS_PAD_CFG_PULL_UP) ||   \
+                                   ((type) == PDS_PAD_CFG_ACTIVE_IE))
+
+/** @defgroup  PDS_INT_TYPE
+ *  @{
+ */
+#define IS_PDS_INT_TYPE(type) (((type) == PDS_INT_WAKEUP) ||        \
+                               ((type) == PDS_INT_RF_DONE) ||       \
+                               ((type) == PDS_INT_PLL_DONE) ||      \
+                               ((type) == PDS_INT_PDS_SLEEP_CNT) || \
+                               ((type) == PDS_INT_HBN_IRQ_OUT0) ||  \
+                               ((type) == PDS_INT_HBN_IRQ_OUT1) ||  \
+                               ((type) == PDS_INT_GPIO_IRQ) ||      \
+                               ((type) == PDS_INT_IRRX) ||          \
+                               ((type) == PDS_INT_BLE_SLP_IRQ) ||   \
+                               ((type) == PDS_INT_USB_WKUP) ||      \
+                               ((type) == PDS_INT_KYS_QDEC) ||      \
+                               ((type) == PDS_INT_MAX))
+
+/** @defgroup  PDS_VDDCORE_GPIO_SRC_TYPE
+ *  @{
+ */
+#define IS_PDS_VDDCORE_GPIO_SRC_TYPE(type) (((type) == PDS_VDDCORE_GPIO_SRC_GPIO_0) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_1) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_2) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_3) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_4) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_5) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_6) || \
+                                            ((type) == PDS_VDDCORE_GPIO_SRC_GPIO_7))
+
+/** @defgroup  PDS_RST_EVENT_TYPE
+ *  @{
+ */
+#define IS_PDS_RST_EVENT_TYPE(type) (((type) == PDS_RST_EVENT_BUS_RST) ||        \
+                                     ((type) == PDS_RST_EVENT_HBN_PWR_ON_RST) || \
+                                     ((type) == PDS_RST_EVENT_PDS_RST) ||        \
+                                     ((type) == PDS_RST_EVENT_MAX))
+
+/** @defgroup  PDS_PLL_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_STS_TYPE(type) (((type) == PDS_PLL_STS_OFF) ||   \
+                                   ((type) == PDS_PLL_STS_SFREG) || \
+                                   ((type) == PDS_PLL_STS_PU) ||    \
+                                   ((type) == PDS_PLL_STS_RDY))
+
+/** @defgroup  PDS_RF_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_RF_STS_TYPE(type) (((type) == PDS_RF_STS_OFF) ||        \
+                                  ((type) == PDS_RF_STS_PU_MBG) ||     \
+                                  ((type) == PDS_RF_STS_PU_LDO15RF) || \
+                                  ((type) == PDS_RF_STS_PU_SFREG) ||   \
+                                  ((type) == PDS_RF_STS_BZ_EN_AON))
+
+/** @defgroup  PDS_STS_TYPE
+ *  @{
+ */
+#define IS_PDS_STS_TYPE(type) (((type) == PDS_STS_IDLE) ||           \
+                               ((type) == PDS_STS_ECG) ||            \
+                               ((type) == PDS_STS_ERST) ||           \
+                               ((type) == PDS_STS_EISO) ||           \
+                               ((type) == PDS_STS_POFF) ||           \
+                               ((type) == PDS_STS_PRE_BGON) ||       \
+                               ((type) == PDS_STS_PRE_BGON1) ||      \
+                               ((type) == PDS_STS_BGON) ||           \
+                               ((type) == PDS_STS_CLK_SW_32M) ||     \
+                               ((type) == PDS_STS_PON_DCDC) ||       \
+                               ((type) == PDS_STS_PON_LDO11_MISC) || \
+                               ((type) == PDS_STS_PON) ||            \
+                               ((type) == PDS_STS_DISO) ||           \
+                               ((type) == PDS_STS_DCG) ||            \
+                               ((type) == PDS_STS_DRST) ||           \
+                               ((type) == PDS_STS_WAIT_EFUSE))
+
+/** @defgroup  PDS_PLL_XTAL_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_XTAL_TYPE(type) (((type) == PDS_PLL_XTAL_NONE) || \
+                                    ((type) == PDS_PLL_XTAL_32M) ||  \
+                                    ((type) == PDS_PLL_XTAL_RC32M))
+
+/** @defgroup  PDS_PLL_CLK_TYPE
+ *  @{
+ */
+#define IS_PDS_PLL_CLK_TYPE(type) (((type) == PDS_PLL_CLK_480M) || \
+                                   ((type) == PDS_PLL_CLK_240M) || \
+                                   ((type) == PDS_PLL_CLK_192M) || \
+                                   ((type) == PDS_PLL_CLK_160M) || \
+                                   ((type) == PDS_PLL_CLK_120M) || \
+                                   ((type) == PDS_PLL_CLK_96M) ||  \
+                                   ((type) == PDS_PLL_CLK_80M) ||  \
+                                   ((type) == PDS_PLL_CLK_48M) ||  \
+                                   ((type) == PDS_PLL_CLK_32M))
+
+/** @defgroup  PDS_AON_GPIO_INT_TRIGGER_TYPE
+ *  @{
+ */
+#define IS_PDS_AON_GPIO_INT_TRIGGER_TYPE(type) (((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_FALLING_EDGE) ||  \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_RISING_EDGE) ||   \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_LOW_LEVEL) ||     \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_SYNC_HIGH_LEVEL) ||    \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_FALLING_EDGE) || \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_RISING_EDGE) ||  \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_LOW_LEVEL) ||    \
+                                                ((type) == PDS_AON_GPIO_INT_TRIGGER_ASYNC_HIGH_LEVEL))
+
+/** @defgroup  PDS_LDO_VOLTAGE_TYPE
+ *  @{
+ */
+#define IS_PDS_LDO_VOLTAGE_TYPE(type) (((type) == PDS_LDO_VOLTAGE_0P60V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P65V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P70V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P75V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P80V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P85V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P90V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_0P95V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P00V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P05V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P10V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P15V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P20V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P25V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P30V) || \
+                                       ((type) == PDS_LDO_VOLTAGE_1P35V))
+
+/** @defgroup  PDS_FORCE_TYPE
+ *  @{
+ */
+#define IS_PDS_FORCE_TYPE(type) (((type) == PDS_FORCE_NP) ||  \
+                                 ((type) == PDS_FORCE_RSV) || \
+                                 ((type) == PDS_FORCE_BZ) ||  \
+                                 ((type) == PDS_FORCE_USB))
+
+/** @defgroup  PDS_AUDIO_PLL_TYPE
+ *  @{
+ */
+#define IS_PDS_AUDIO_PLL_TYPE(type) (((type) == AUDIO_PLL_12288000_HZ) || \
+                                     ((type) == AUDIO_PLL_11289600_HZ) || \
+                                     ((type) == AUDIO_PLL_5644800_HZ)  || \
+                                     ((type) == AUDIO_PLL_24576000_HZ) || \
+                                     ((type) == AUDIO_PLL_24000000_HZ) || \
+                                     ((type) == AUDIO_PLL_50000000_HZ))
+
+/*@} end of group PDS_Public_Constants */
+
+/** @defgroup  PDS_Public_Macros
+ *  @{
+ */
+#define PDS_LDO_MIN_PU_CNT        (25) /* LDO need 25 cycles to power up */
+#define PDS_WARMUP_CNT            (38) /* LDO hw warmup compensation latency cycles */
+#define PDS_WARMUP_LATENCY_CNT    (38) /* LDO hw warmup compensation latency cycles */
+#define PDS_FORCE_PWR_OFF_OFFSET  (0)
+#define PDS_FORCE_ISO_EN_OFFSET   (4)
+#define PDS_FORCE_PDS_RST_OFFSET  (8)
+#define PDS_FORCE_MEM_STBY_OFFSET (12)
+#define PDS_FORCE_GATE_CLK_OFFSET (16)
+#define PDS_INT_MASK_BIT_OFFSET   (8)
+#define PDS_AON_WAKEUP_GPIO_NONE  (0x00)
+#define PDS_AON_WAKEUP_GPIO_9     (0x01)
+#define PDS_AON_WAKEUP_GPIO_10    (0x02)
+#define PDS_AON_WAKEUP_GPIO_11    (0x04)
+#define PDS_AON_WAKEUP_GPIO_12    (0x08)
+#define PDS_AON_WAKEUP_GPIO_13    (0x10)
+#define PDS_AON_WAKEUP_GPIO_ALL   (0x1E)
+
+/*@} end of group PDS_Public_Macros */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+#ifndef BFLB_USE_HAL_DRIVER
+void PDS_WAKEUP_IRQHandler(void);
+#endif
+/*----------*/
+BL_Err_Type PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg);
+BL_Err_Type PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg);
+/*----------*/
+BL_Err_Type PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt);
+BL_Err_Type PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3);
+BL_Err_Type PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt);
+/*----------*/
+BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable);
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask);
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType);
+BL_Err_Type PDS_IntClear(void);
+PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void);
+PDS_RF_STS_Type PDS_Get_PdsRfStstus(void);
+PDS_STS_Type PDS_Get_PdsStstus(void);
+/*----------*/
+BL_Err_Type PDS_Clear_Reset_Event(void);
+BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event);
+/*----------*/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src,
+                                        PDS_AON_GPIO_INT_Trigger_Type mode);
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask);
+BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void);
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void);
+/*----------*/
+BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void);
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun);
+/*----------*/
+BL_Err_Type PDS_Trim_RC32M(void);
+BL_Err_Type PDS_Select_RC32M_As_PLL_Ref(void);
+BL_Err_Type PDS_Select_XTAL_As_PLL_Ref(void);
+BL_Err_Type PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType);
+BL_Err_Type PDS_Enable_PLL_All_Clks(void);
+BL_Err_Type PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
+BL_Err_Type PDS_Disable_PLL_All_Clks(void);
+BL_Err_Type PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk);
+BL_Err_Type PDS_Power_Off_PLL(void);
+BL_Err_Type PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq);
+/*----------*/
+void PDS_Reset(void);
+void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt);
+void PDS_Auto_Time_Config(uint32_t sleepDuration);
+void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable);
+void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain);
+void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain);
+/*----------*/
+BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel);
+/*----------*/
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_PDS_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_romdriver.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_romdriver.h
new file mode 100755
index 0000000000..f1971fffab
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_romdriver.h
@@ -0,0 +1,632 @@
+/**
+  ******************************************************************************
+  * @file    bl702_romdriver.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_ROMDRIVER_H__
+#define __BL702_ROMDRIVER_H__
+
+#include "bl702_common.h"
+#include "bl702_aon.h"
+#include "bl702_glb.h"
+#include "bl702_hbn.h"
+#include "bflb_spi_psram.h"
+#include "bflb_xip_sflash.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_ctrl.h"
+// #include "softcrc.h"
+
+#define ROMAPI_INDEX_SECT_SIZE (0x800)
+#define ROMAPI_INDEX_MAX       (ROMAPI_INDEX_SECT_SIZE / 4 - 1)
+
+typedef enum {
+    ROM_API_INDEX_REV = 0,
+
+    ROM_API_INDEX_FUNC_START = 4,
+
+    ROM_API_INDEX_AON_Power_On_MBG = ROM_API_INDEX_FUNC_START,
+    ROM_API_INDEX_AON_Power_Off_MBG,
+    ROM_API_INDEX_AON_Power_On_XTAL,
+    ROM_API_INDEX_AON_Set_Xtal_CapCode,
+    ROM_API_INDEX_AON_Power_Off_XTAL,
+
+    ROM_API_INDEX_ASM_Delay_Us,
+    ROM_API_INDEX_BL702_Delay_US,
+    ROM_API_INDEX_BL702_Delay_MS,
+    ROM_API_INDEX_BL702_MemCpy,
+    ROM_API_INDEX_BL702_MemCpy4,
+    ROM_API_INDEX_BL702_MemCpy_Fast,
+    ROM_API_INDEX_ARCH_MemCpy_Fast,
+    ROM_API_INDEX_BL702_MemSet,
+    ROM_API_INDEX_BL702_MemSet4,
+    ROM_API_INDEX_BL702_MemCmp,
+    ROM_API_INDEX_BFLB_Soft_CRC32,
+
+    ROM_API_INDEX_GLB_Get_Root_CLK_Sel,
+    ROM_API_INDEX_GLB_Set_System_CLK_Div,
+    ROM_API_INDEX_GLB_Get_BCLK_Div,
+    ROM_API_INDEX_GLB_Get_HCLK_Div,
+    ROM_API_INDEX_Update_SystemCoreClockWith_XTAL,
+    ROM_API_INDEX_GLB_Set_System_CLK,
+    ROM_API_INDEX_System_Core_Clock_Update_From_RC32M,
+    ROM_API_INDEX_GLB_Set_SF_CLK,
+    ROM_API_INDEX_GLB_Power_Off_DLL,
+    ROM_API_INDEX_GLB_Power_On_DLL,
+    ROM_API_INDEX_GLB_Enable_DLL_All_Clks,
+    ROM_API_INDEX_GLB_Enable_DLL_Clk,
+    ROM_API_INDEX_GLB_Disable_DLL_All_Clks,
+    ROM_API_INDEX_GLB_Disable_DLL_Clk,
+    ROM_API_INDEX_GLB_SW_System_Reset,
+    ROM_API_INDEX_GLB_SW_CPU_Reset,
+    ROM_API_INDEX_GLB_SW_POR_Reset,
+    ROM_API_INDEX_GLB_Select_Internal_Flash,
+    ROM_API_INDEX_GLB_Swap_Flash_Pin,
+    ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin,
+    ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin,
+    ROM_API_INDEX_GLB_Select_Internal_PSram,
+    ROM_API_INDEX_GLB_GPIO_Init,
+    ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable,
+    ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable,
+    ROM_API_INDEX_GLB_GPIO_Set_HZ,
+    ROM_API_INDEX_GLB_Deswap_Flash_Pin,
+    ROM_API_INDEX_GLB_Select_External_Flash,
+    ROM_API_INDEX_GLB_GPIO_Get_Fun,
+
+    ROM_API_INDEX_EF_Ctrl_Busy,
+    ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0,
+    ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0,
+    ROM_API_INDEX_EF_Ctrl_Clear,
+    ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity,
+    ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim,
+    ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim,
+
+    ROM_API_INDEX_PDS_Trim_RC32M,
+    ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref,
+    ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref,
+    ROM_API_INDEX_PDS_Power_On_PLL,
+    ROM_API_INDEX_PDS_Enable_PLL_All_Clks,
+    ROM_API_INDEX_PDS_Disable_PLL_All_Clks,
+    ROM_API_INDEX_PDS_Enable_PLL_Clk,
+    ROM_API_INDEX_PDS_Disable_PLL_Clk,
+    ROM_API_INDEX_PDS_Power_Off_PLL,
+    ROM_API_INDEX_PDS_Reset,
+    ROM_API_INDEX_PDS_Enable,
+    ROM_API_INDEX_PDS_Auto_Time_Config,
+    ROM_API_INDEX_PDS_Auto_Enable,
+    ROM_API_INDEX_PDS_Manual_Force_Turn_Off,
+    ROM_API_INDEX_PDS_Manual_Force_Turn_On,
+
+    ROM_API_INDEX_HBN_Enable,
+    ROM_API_INDEX_HBN_Reset,
+    ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg,
+    ROM_API_INDEX_HBN_Trim_RC32K,
+    ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel,
+
+    ROM_API_INDEX_XIP_SFlash_State_Save,
+    ROM_API_INDEX_XIP_SFlash_State_Restore,
+    ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Write_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock,
+    ROM_API_INDEX_XIP_SFlash_Read_With_Lock,
+    ROM_API_INDEX_XIP_SFlash_Write_With_Lock,
+    ROM_API_INDEX_XIP_SFlash_Erase_With_Lock,
+
+    ROM_API_INDEX_SFlash_Init,
+    ROM_API_INDEX_SFlash_SetSPIMode,
+    ROM_API_INDEX_SFlash_Read_Reg,
+    ROM_API_INDEX_SFlash_Write_Reg,
+    ROM_API_INDEX_SFlash_Read_Reg_With_Cmd,
+    ROM_API_INDEX_SFlash_Write_Reg_With_Cmd,
+    ROM_API_INDEX_SFlash_Busy,
+    ROM_API_INDEX_SFlash_Write_Enable,
+    ROM_API_INDEX_SFlash_Qspi_Enable,
+    ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable,
+    ROM_API_INDEX_SFlash_Chip_Erase,
+    ROM_API_INDEX_SFlash_Sector_Erase,
+    ROM_API_INDEX_SFlash_Blk32_Erase,
+    ROM_API_INDEX_SFlash_Blk64_Erase,
+    ROM_API_INDEX_SFlash_Erase,
+    ROM_API_INDEX_SFlash_Program,
+    ROM_API_INDEX_SFlash_GetUniqueId,
+    ROM_API_INDEX_SFlash_GetJedecId,
+    ROM_API_INDEX_SFlash_GetDeviceId,
+    ROM_API_INDEX_SFlash_Powerdown,
+    ROM_API_INDEX_SFlash_Releae_Powerdown,
+    ROM_API_INDEX_SFlash_Restore_From_Powerdown,
+    ROM_API_INDEX_SFlash_SetBurstWrap,
+    ROM_API_INDEX_SFlash_DisableBurstWrap,
+    ROM_API_INDEX_SFlash_Software_Reset,
+    ROM_API_INDEX_SFlash_Reset_Continue_Read,
+    ROM_API_INDEX_SFlash_Set_IDbus_Cfg,
+    ROM_API_INDEX_SFlash_IDbus_Read_Enable,
+    ROM_API_INDEX_SFlash_Cache_Read_Enable,
+    ROM_API_INDEX_SFlash_Cache_Read_Disable,
+    ROM_API_INDEX_SFlash_Read,
+
+    ROM_API_INDEX_L1C_Cache_Enable_Set,
+    ROM_API_INDEX_L1C_Cache_Write_Set,
+    ROM_API_INDEX_L1C_Cache_Flush,
+    ROM_API_INDEX_L1C_Cache_Hit_Count_Get,
+    ROM_API_INDEX_L1C_Cache_Miss_Count_Get,
+    ROM_API_INDEX_L1C_Cache_Read_Disable,
+    ROM_API_INDEX_L1C_Set_Wrap,
+    ROM_API_INDEX_L1C_Set_Way_Disable,
+    ROM_API_INDEX_L1C_IROM_2T_Access_Set,
+
+    ROM_API_INDEX_SF_Ctrl_Enable,
+    ROM_API_INDEX_SF_Ctrl_Psram_Init,
+    ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay,
+    ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay,
+    ROM_API_INDEX_SF_Ctrl_Cmds_Set,
+    ROM_API_INDEX_SF_Ctrl_Set_Owner,
+    ROM_API_INDEX_SF_Ctrl_Disable,
+    ROM_API_INDEX_SF_Ctrl_Select_Pad,
+    ROM_API_INDEX_SF_Ctrl_Select_Bank,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable_LE,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Region,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Key,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_IV,
+    ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE,
+    ROM_API_INDEX_SF_Ctrl_AES_Enable,
+    ROM_API_INDEX_SF_Ctrl_AES_Disable,
+    ROM_API_INDEX_SF_Ctrl_Is_AES_Enable,
+    ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset,
+    ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset,
+    ROM_API_INDEX_SF_Ctrl_Select_Clock,
+    ROM_API_INDEX_SF_Ctrl_SendCmd,
+    ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set,
+    ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set,
+    ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set,
+    ROM_API_INDEX_SF_Ctrl_GetBusyState,
+    ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock,
+    ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio,
+    ROM_API_INDEX_SF_Cfg_Flash_Identify,
+
+    ROM_API_INDEX_Psram_Init,
+    ROM_API_INDEX_Psram_ReadReg,
+    ROM_API_INDEX_Psram_WriteReg,
+    ROM_API_INDEX_Psram_SetDriveStrength,
+    ROM_API_INDEX_Psram_SetBurstWrap,
+    ROM_API_INDEX_Psram_ReadId,
+    ROM_API_INDEX_Psram_EnterQuadMode,
+    ROM_API_INDEX_Psram_ExitQuadMode,
+    ROM_API_INDEX_Psram_ToggleBurstLength,
+    ROM_API_INDEX_Psram_SoftwareReset,
+    ROM_API_INDEX_Psram_Set_IDbus_Cfg,
+    ROM_API_INDEX_Psram_Cache_Write_Set,
+    ROM_API_INDEX_Psram_Write,
+    ROM_API_INDEX_Psram_Read,
+
+    ROM_API_INDEX_FUNC_LAST = ROM_API_INDEX_Psram_Read,
+
+    ROM_API_INDEX_FUNC_INVALID_START,
+
+    ROM_API_INDEX_FUNC_LAST_ENTRY = ROMAPI_INDEX_MAX
+} ROM_API_INDEX_e;
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  ROMDRIVER
+ *  @{
+ */
+
+/** @defgroup  ROMDRIVER_Public_Types
+ *  @{
+ */
+#define ROM_APITABLE ((uint32_t *)0x21018800)
+
+#define RomDriver_AON_Power_On_MBG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_MBG])
+#define RomDriver_AON_Power_Off_MBG \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_MBG])
+#define RomDriver_AON_Power_On_XTAL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_On_XTAL])
+#define RomDriver_AON_Set_Xtal_CapCode \
+    ((BL_Err_Type(*)(uint8_t capIn, uint8_t capOut))ROM_APITABLE[ROM_API_INDEX_AON_Set_Xtal_CapCode])
+#define RomDriver_AON_Power_Off_XTAL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_AON_Power_Off_XTAL])
+
+#define RomDriver_ASM_Delay_Us \
+    ((void (*)(uint32_t core, uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_ASM_Delay_Us])
+#define RomDriver_BL702_Delay_US \
+    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_US])
+#define RomDriver_BL702_Delay_MS \
+    ((void (*)(uint32_t cnt))ROM_APITABLE[ROM_API_INDEX_BL702_Delay_MS])
+#define RomDriver_BL702_MemCpy \
+    ((void *(*)(void *dst, const void *src, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy])
+#define RomDriver_BL702_MemCpy4 \
+    ((uint32_t * (*)(uint32_t * dst, const uint32_t *src, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy4])
+#define RomDriver_BL702_MemCpy_Fast \
+    ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCpy_Fast])
+#define RomDriver_ARCH_MemCpy_Fast \
+    ((void *(*)(void *pdst, const void *psrc, uint32_t n))ROM_APITABLE[ROM_API_INDEX_ARCH_MemCpy_Fast])
+#define RomDriver_BL702_MemSet \
+    ((void *(*)(void *s, uint8_t c, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemSet])
+#define RomDriver_BL702_MemSet4 \
+    ((uint32_t * (*)(uint32_t * dst, const uint32_t val, uint32_t n)) ROM_APITABLE[ROM_API_INDEX_BL702_MemSet4])
+#define RomDriver_BL702_MemCmp \
+    ((int (*)(const void *s1, const void *s2, uint32_t n))ROM_APITABLE[ROM_API_INDEX_BL702_MemCmp])
+#define RomDriver_BFLB_Soft_CRC32 \
+    ((uint32_t(*)(void *dataIn, uint32_t len))ROM_APITABLE[ROM_API_INDEX_BFLB_Soft_CRC32])
+
+#define RomDriver_GLB_Get_Root_CLK_Sel \
+    ((GLB_ROOT_CLK_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_Root_CLK_Sel])
+#define RomDriver_GLB_Set_System_CLK_Div \
+    ((BL_Err_Type(*)(uint8_t hclkDiv, uint8_t bclkDiv))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK_Div])
+#define RomDriver_GLB_Get_BCLK_Div \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_BCLK_Div])
+#define RomDriver_GLB_Get_HCLK_Div \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Get_HCLK_Div])
+#define RomDriver_Update_SystemCoreClockWith_XTAL \
+    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_Update_SystemCoreClockWith_XTAL])
+#define RomDriver_GLB_Set_System_CLK \
+    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq))ROM_APITABLE[ROM_API_INDEX_GLB_Set_System_CLK])
+#define RomDriver_System_Core_Clock_Update_From_RC32M \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_System_Core_Clock_Update_From_RC32M])
+#define RomDriver_GLB_Set_SF_CLK \
+    ((BL_Err_Type(*)(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div))ROM_APITABLE[ROM_API_INDEX_GLB_Set_SF_CLK])
+#define RomDriver_GLB_Power_Off_DLL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Power_Off_DLL])
+#define RomDriver_GLB_Power_On_DLL \
+    ((BL_Err_Type(*)(GLB_DLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_GLB_Power_On_DLL])
+#define RomDriver_GLB_Enable_DLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_All_Clks])
+#define RomDriver_GLB_Enable_DLL_Clk \
+    ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Enable_DLL_Clk])
+#define RomDriver_GLB_Disable_DLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_All_Clks])
+#define RomDriver_GLB_Disable_DLL_Clk \
+    ((BL_Err_Type(*)(GLB_DLL_CLK_Type dllClk))ROM_APITABLE[ROM_API_INDEX_GLB_Disable_DLL_Clk])
+#define RomDriver_GLB_SW_System_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_System_Reset])
+#define RomDriver_GLB_SW_CPU_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_CPU_Reset])
+#define RomDriver_GLB_SW_POR_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_SW_POR_Reset])
+#define RomDriver_GLB_Select_Internal_Flash \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_Flash])
+#define RomDriver_GLB_Swap_Flash_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_Pin])
+#define RomDriver_GLB_Swap_Flash_CS_IO2_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin])
+#define RomDriver_GLB_Swap_Flash_IO0_IO3_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin])
+#define RomDriver_GLB_Select_Internal_PSram \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_Internal_PSram])
+#define RomDriver_GLB_GPIO_Init \
+    ((BL_Err_Type(*)(GLB_GPIO_Cfg_Type * cfg)) ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Init])
+#define RomDriver_GLB_GPIO_OUTPUT_Enable \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable])
+#define RomDriver_GLB_GPIO_OUTPUT_Disable \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable])
+#define RomDriver_GLB_GPIO_Set_HZ \
+    ((BL_Err_Type(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Set_HZ])
+#define RomDriver_GLB_Deswap_Flash_Pin \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Deswap_Flash_Pin])
+#define RomDriver_GLB_Select_External_Flash \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_GLB_Select_External_Flash])
+#define RomDriver_GLB_GPIO_Get_Fun \
+    ((uint8_t(*)(GLB_GPIO_Type gpioPin))ROM_APITABLE[ROM_API_INDEX_GLB_GPIO_Get_Fun])
+
+#define RomDriver_EF_Ctrl_Busy \
+    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Busy])
+#define RomDriver_EF_Ctrl_Sw_AHB_Clk_0 \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0])
+#define RomDriver_EF_Ctrl_Load_Efuse_R0 \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0])
+#define RomDriver_EF_Ctrl_Clear \
+    ((void (*)(uint32_t index, uint32_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Clear])
+#define RomDriver_EF_Ctrl_Get_Trim_Parity \
+    ((uint8_t(*)(uint32_t val, uint8_t len))ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity])
+#define RomDriver_EF_Ctrl_Read_RC32K_Trim \
+    ((void (*)(Efuse_Ana_RC32K_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim])
+#define RomDriver_EF_Ctrl_Read_RC32M_Trim \
+    ((void (*)(Efuse_Ana_RC32M_Trim_Type * trim)) ROM_APITABLE[ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim])
+
+#define RomDriver_PDS_Trim_RC32M \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Trim_RC32M])
+#define RomDriver_PDS_Select_RC32M_As_PLL_Ref \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref])
+#define RomDriver_PDS_Select_XTAL_As_PLL_Ref \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref])
+#define RomDriver_PDS_Power_On_PLL \
+    ((BL_Err_Type(*)(PDS_PLL_XTAL_Type xtalType))ROM_APITABLE[ROM_API_INDEX_PDS_Power_On_PLL])
+#define RomDriver_PDS_Enable_PLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_All_Clks])
+#define RomDriver_PDS_Disable_PLL_All_Clks \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_All_Clks])
+#define RomDriver_PDS_Enable_PLL_Clk \
+    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Enable_PLL_Clk])
+#define RomDriver_PDS_Disable_PLL_Clk \
+    ((BL_Err_Type(*)(PDS_PLL_CLK_Type pllClk))ROM_APITABLE[ROM_API_INDEX_PDS_Disable_PLL_Clk])
+#define RomDriver_PDS_Power_Off_PLL \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Power_Off_PLL])
+#define RomDriver_PDS_Reset \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_PDS_Reset])
+#define RomDriver_PDS_Enable \
+    ((void (*)(PDS_CFG_Type * cfg, uint32_t pdsSleepCnt)) ROM_APITABLE[ROM_API_INDEX_PDS_Enable])
+#define RomDriver_PDS_Auto_Time_Config \
+    ((void (*)(uint32_t sleepDuration))ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Time_Config])
+#define RomDriver_PDS_Auto_Enable \
+    ((void (*)(PDS_AUTO_POWER_DOWN_CFG_Type * powerCfg, PDS_AUTO_NORMAL_CFG_Type * normalCfg, BL_Fun_Type enable)) ROM_APITABLE[ROM_API_INDEX_PDS_Auto_Enable])
+#define RomDriver_PDS_Manual_Force_Turn_Off \
+    ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_Off])
+#define RomDriver_PDS_Manual_Force_Turn_On \
+    ((void (*)(PDS_FORCE_Type domain))ROM_APITABLE[ROM_API_INDEX_PDS_Manual_Force_Turn_On])
+
+#define RomDriver_HBN_Enable \
+    ((void (*)(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel))ROM_APITABLE[ROM_API_INDEX_HBN_Enable])
+#define RomDriver_HBN_Reset \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Reset])
+#define RomDriver_HBN_GPIO_Dbg_Pull_Cfg \
+    ((BL_Err_Type(*)(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask))ROM_APITABLE[ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg])
+#define RomDriver_HBN_Trim_RC32K \
+    ((BL_Err_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_HBN_Trim_RC32K])
+#define RomDriver_HBN_Set_ROOT_CLK_Sel \
+    ((BL_Err_Type(*)(HBN_ROOT_CLK_Type rootClk))ROM_APITABLE[ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel])
+
+#define RomDriver_XIP_SFlash_State_Save \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint32_t * offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Save])
+#define RomDriver_XIP_SFlash_State_Restore \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t offset)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_State_Restore])
+#define RomDriver_XIP_SFlash_Erase_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock])
+#define RomDriver_XIP_SFlash_Write_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_Need_Lock])
+#define RomDriver_XIP_SFlash_Read_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Need_Lock])
+#define RomDriver_XIP_SFlash_GetJedecId_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock])
+#define RomDriver_XIP_SFlash_GetDeviceId_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock])
+#define RomDriver_XIP_SFlash_GetUniqueId_Need_Lock \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock])
+#define RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock \
+    ((int(*)(uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock])
+#define RomDriver_XIP_SFlash_Read_With_Lock \
+    ((int (*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * dst, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Read_With_Lock])
+#define RomDriver_XIP_SFlash_Write_With_Lock \
+    ((int (*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, uint8_t * src, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Write_With_Lock])
+#define RomDriver_XIP_SFlash_Erase_With_Lock \
+    ((int (*)(spi_flash_cfg_type * pFlashCfg, uint8_t ioMode, uint32_t addr, int len)) ROM_APITABLE[ROM_API_INDEX_XIP_SFlash_Erase_With_Lock])
+
+#define RomDriver_SFlash_Init \
+    ((void (*)(const struct sf_ctrl_cfg_type *pSfCtrlCfg))ROM_APITABLE[ROM_API_INDEX_SFlash_Init])
+#define RomDriver_SFlash_SetSPIMode \
+    ((int(*)(uint8_t mode))ROM_APITABLE[ROM_API_INDEX_SFlash_SetSPIMode])
+#define RomDriver_SFlash_Read_Reg \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg])
+#define RomDriver_SFlash_Write_Reg \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t regIndex, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg])
+#define RomDriver_SFlash_Read_Reg_With_Cmd \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t readRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read_Reg_With_Cmd])
+#define RomDriver_SFlash_Write_Reg_With_Cmd \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t writeRegCmd, uint8_t * regValue, uint8_t regLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Reg_With_Cmd])
+#define RomDriver_SFlash_Busy \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Busy])
+#define RomDriver_SFlash_Write_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Write_Enable])
+#define RomDriver_SFlash_Qspi_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Qspi_Enable])
+#define RomDriver_SFlash_Volatile_Reg_Write_Enable \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable])
+#define RomDriver_SFlash_Chip_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Chip_Erase])
+#define RomDriver_SFlash_Sector_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t secNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Sector_Erase])
+#define RomDriver_SFlash_Blk32_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk32_Erase])
+#define RomDriver_SFlash_Blk64_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t blkNum)) ROM_APITABLE[ROM_API_INDEX_SFlash_Blk64_Erase])
+#define RomDriver_SFlash_Erase \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint32_t startaddr, uint32_t endaddr)) ROM_APITABLE[ROM_API_INDEX_SFlash_Erase])
+#define RomDriver_SFlash_Program \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Program])
+#define RomDriver_SFlash_GetUniqueId \
+    ((void (*)(uint8_t * data, uint8_t idLen)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetUniqueId])
+#define RomDriver_SFlash_GetJedecId \
+    ((void (*)(spi_flash_cfg_type * flashCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetJedecId])
+#define RomDriver_SFlash_GetDeviceId \
+    ((void (*)(uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_SFlash_GetDeviceId])
+#define RomDriver_SFlash_Powerdown \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Powerdown])
+#define RomDriver_SFlash_Releae_Powerdown \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Releae_Powerdown])
+#define RomDriver_SFlash_Restore_From_Powerdown \
+    ((int(*)(spi_flash_cfg_type * pFlashCfg, uint8_t flashcont_read)) ROM_APITABLE[ROM_API_INDEX_SFlash_Restore_From_Powerdown])
+#define RomDriver_SFlash_SetBurstWrap \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_SetBurstWrap])
+#define RomDriver_SFlash_DisableBurstWrap \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_DisableBurstWrap])
+#define RomDriver_SFlash_Software_Reset \
+    ((int(*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Software_Reset])
+#define RomDriver_SFlash_Reset_Continue_Read \
+    ((void (*)(spi_flash_cfg_type * flashCfg)) ROM_APITABLE[ROM_API_INDEX_SFlash_Reset_Continue_Read])
+#define RomDriver_SFlash_Set_IDbus_Cfg \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Set_IDbus_Cfg])
+#define RomDriver_SFlash_IDbus_Read_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read)) ROM_APITABLE[ROM_API_INDEX_SFlash_IDbus_Read_Enable])
+#define RomDriver_SFlash_Cache_Read_Enable \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read, uint8_t wayDisable)) ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Enable])
+#define RomDriver_SFlash_Cache_Read_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SFlash_Cache_Read_Disable])
+#define RomDriver_SFlash_Read \
+    ((int(*)(spi_flash_cfg_type * flashCfg, uint8_t ioMode, uint8_t cont_read, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_SFlash_Read])
+
+#define RomDriver_L1C_Cache_Enable_Set \
+    ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Enable_Set])
+#define RomDriver_L1C_Cache_Write_Set \
+    ((void (*)(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Write_Set])
+#define RomDriver_L1C_Cache_Flush \
+    ((BL_Err_Type(*)(uint8_t wayDisable))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Flush])
+#define RomDriver_L1C_Cache_Hit_Count_Get \
+    ((void (*)(uint32_t * hitCountLow, uint32_t * hitCountHigh)) ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Hit_Count_Get])
+#define RomDriver_L1C_Cache_Miss_Count_Get \
+    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Miss_Count_Get])
+#define RomDriver_L1C_Cache_Read_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_L1C_Cache_Read_Disable])
+#define RomDriver_L1C_Set_Wrap \
+    ((BL_Err_Type(*)(BL_Fun_Type wrap))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Wrap])
+#define RomDriver_L1C_Set_Way_Disable \
+    ((BL_Err_Type(*)(uint8_t disableVal))ROM_APITABLE[ROM_API_INDEX_L1C_Set_Way_Disable])
+#define RomDriver_L1C_IROM_2T_Access_Set \
+    ((BL_Err_Type(*)(uint8_t enable))ROM_APITABLE[ROM_API_INDEX_L1C_IROM_2T_Access_Set])
+
+#define RomDriver_SF_Ctrl_Enable \
+    ((void (*)(const struct sf_ctrl_cfg_type *cfg))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Enable])
+#define RomDriver_SF_Ctrl_Psram_Init \
+    ((void (*)(struct sf_ctrl_psram_cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Init])
+#define RomDriver_SF_Ctrl_Get_Clock_Delay \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay])
+#define RomDriver_SF_Ctrl_Set_Clock_Delay \
+    ((void (*)(uint8_t delay))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay])
+#define RomDriver_SF_Ctrl_Cmds_Set \
+    ((void (*)(struct sf_ctrl_cmds_cfg * cmdsCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Cmds_Set])
+#define RomDriver_SF_Ctrl_Set_Owner \
+    ((void (*)(uint8_t owner))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Owner])
+#define RomDriver_SF_Ctrl_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Disable])
+#define RomDriver_SF_Ctrl_Select_Pad \
+    ((void (*)(uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Pad])
+#define RomDriver_SF_Ctrl_Select_Bank \
+    ((void (*)(uint8_t sel))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Bank])
+#define RomDriver_SF_Ctrl_AES_Enable_BE \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_BE])
+#define RomDriver_SF_Ctrl_AES_Enable_LE \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable_LE])
+#define RomDriver_SF_Ctrl_AES_Set_Region \
+    ((void (*)(uint8_t region, uint8_t enable, uint8_t hwKey, uint32_t startAddr, uint32_t endAddr, uint8_t locked))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Region])
+#define RomDriver_SF_Ctrl_AES_Set_Key \
+    ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key])
+#define RomDriver_SF_Ctrl_AES_Set_Key_BE \
+    ((void (*)(uint8_t region, uint8_t * key, uint8_t keyType)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE])
+#define RomDriver_SF_Ctrl_AES_Set_IV \
+    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV])
+#define RomDriver_SF_Ctrl_AES_Set_IV_BE \
+    ((void (*)(uint8_t region, uint8_t * iv, uint32_t addrOffset)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE])
+#define RomDriver_SF_Ctrl_AES_Enable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Enable])
+#define RomDriver_SF_Ctrl_AES_Disable \
+    ((void (*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_AES_Disable])
+#define RomDriver_SF_Ctrl_Is_AES_Enable \
+    ((uint8_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Is_AES_Enable])
+#define RomDriver_SF_Ctrl_Set_Flash_Image_Offset \
+    ((void (*)(uint32_t addrOffset))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset])
+#define RomDriver_SF_Ctrl_Get_Flash_Image_Offset \
+    ((uint32_t(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset])
+#define RomDriver_SF_Ctrl_Select_Clock \
+    ((void (*)(uint8_t sahbType))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Select_Clock])
+#define RomDriver_SF_Ctrl_SendCmd \
+    ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_SendCmd])
+#define RomDriver_SF_Ctrl_Flash_Read_Icache_Set \
+    ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set])
+#define RomDriver_SF_Ctrl_Psram_Write_Icache_Set \
+    ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set])
+#define RomDriver_SF_Ctrl_Psram_Read_Icache_Set \
+    ((void (*)(struct sf_ctrl_cmd_cfg_type * cfg, uint8_t cmdValid)) ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set])
+#define RomDriver_SF_Ctrl_GetBusyState \
+    ((BL_Sts_Type(*)(void))ROM_APITABLE[ROM_API_INDEX_SF_Ctrl_GetBusyState])
+#define RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio \
+    ((int (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio])
+#define RomDriver_SF_Cfg_Init_Ext_Flash_Gpio \
+    ((void (*)(uint8_t extFlashPin))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio])
+#define RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock \
+    ((BL_Err_Type(*)(uint32_t flashID, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock])
+#define RomDriver_SF_Cfg_Init_Flash_Gpio \
+    ((void (*)(uint8_t flashPinCfg, uint8_t restoreDefault))ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio])
+#define RomDriver_SF_Cfg_Flash_Identify \
+    ((uint32_t(*)(uint8_t callFromFlash, uint32_t autoScan, uint32_t flashPinCfg, uint8_t restoreDefault, spi_flash_cfg_type * pFlashCfg)) ROM_APITABLE[ROM_API_INDEX_SF_Cfg_Flash_Identify])
+
+#define RomDriver_Psram_Init \
+    ((void (*)(struct spi_psram_cfg_type * psramCfg, struct sf_ctrl_cmds_cfg * cmdsCfg, struct sf_ctrl_psram_cfg * sfCtrlPsramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_Init])
+#define RomDriver_Psram_ReadReg \
+    ((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadReg])
+#define RomDriver_Psram_WriteReg \
+    ((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * regValue)) ROM_APITABLE[ROM_API_INDEX_Psram_WriteReg])
+#define RomDriver_Psram_SetDriveStrength \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetDriveStrength])
+#define RomDriver_Psram_SetBurstWrap \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_SetBurstWrap])
+#define RomDriver_Psram_ReadId \
+    ((void (*)(struct spi_psram_cfg_type * psramCfg, uint8_t * data)) ROM_APITABLE[ROM_API_INDEX_Psram_ReadId])
+#define RomDriver_Psram_EnterQuadMode \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_EnterQuadMode])
+#define RomDriver_Psram_ExitQuadMode \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg)) ROM_APITABLE[ROM_API_INDEX_Psram_ExitQuadMode])
+#define RomDriver_Psram_ToggleBurstLength \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_ToggleBurstLength])
+#define RomDriver_Psram_SoftwareReset \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ctrlMode)) ROM_APITABLE[ROM_API_INDEX_Psram_SoftwareReset])
+#define RomDriver_Psram_Set_IDbus_Cfg \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint32_t addr, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Set_IDbus_Cfg])
+#define RomDriver_Psram_Cache_Write_Set \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint8_t wtEn, uint8_t wbEn, uint8_t waEn)) ROM_APITABLE[ROM_API_INDEX_Psram_Cache_Write_Set])
+#define RomDriver_Psram_Write \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Write])
+#define RomDriver_Psram_Read \
+    ((int(*)(struct spi_psram_cfg_type * psramCfg, uint8_t ioMode, uint32_t addr, uint8_t * data, uint32_t len)) ROM_APITABLE[ROM_API_INDEX_Psram_Read])
+/*@} end of group ROMDRIVER_Public_Types */
+
+/** @defgroup  ROMDRIVER_Public_Constants
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Constants */
+
+/** @defgroup  ROMDRIVER_Public_Macros
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Macros */
+
+/** @defgroup  ROMDRIVER_Public_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Functions */
+
+/*@} end of group ROMDRIVER */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_ROMDRIVER_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h
new file mode 100755
index 0000000000..0cab7d1279
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sf_cfg_ext.h
@@ -0,0 +1,84 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sf_cfg_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SF_CFG_EXT_H__
+#define __BL702_SF_CFG_EXT_H__
+
+#include "string.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_ctrl.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG_EXT
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_EXT_Public_Types
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Public_Types */
+
+/** @defgroup  SF_CFG_EXT_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Public_Constants */
+
+/** @defgroup  SF_CFG_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Public_Macros */
+
+/** @defgroup  SF_CFG_EXT_Public_Functions
+ *  @{
+ */
+void bflb_sf_cfg_init_internal_flash_gpio(void);
+int bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                            uint8_t group, uint8_t bank);
+uint32_t bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg, uint8_t restore_default,
+                                        spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
+
+/*@} end of group SF_CFG_EXT_Public_Functions */
+
+/*@} end of group SF_CFG_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SF_CFG_EXT_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sflash_ext.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sflash_ext.h
new file mode 100755
index 0000000000..6897e253d8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_sflash_ext.h
@@ -0,0 +1,93 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sflah_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_SFLAH_EXT_H__
+#define __BL702_SFLAH_EXT_H__
+
+#include "bflb_sflash.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLAH_EXT
+ *  @{
+ */
+
+/** @defgroup  SFLAH_EXT_Public_Types
+ *  @{
+ */
+
+/**
+ *  @brief Serail flash protect KH25V40 type definition
+ */
+#define SFLASH_KH25V40_PROTECT_NONE         0  /*!< SFlash no protect KH25V40 */
+#define SFLASH_KH25V40_PROTECT_448KTO512K   1  /*!< SFlash protect KH25V40 448K to 512K */
+#define SFLASH_KH25V40_PROTECT_384KTO512K   2  /*!< SFlash protect KH25V40 384K to 512K */
+#define SFLASH_KH25V40_PROTECT_256KTO512K   3  /*!< SFlash protect KH25V40 256K to 512K */
+#define SFLASH_KH25V40_PROTECT_ALL          4  /*!< SFlash protect KH25V40 0K to 512K */
+
+/*@} end of group SFLAH_EXT_Public_Types */
+
+/** @defgroup  SFLAH_EXT_Public_Constants
+ *  @{
+ */
+
+/*@} end of group SFLAH_EXT_Public_Constants */
+
+/** @defgroup  SFLAH_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group SFLAH_EXT_Public_Macros */
+
+/** @defgroup  SFLAH_EXT_Public_Functions
+ *  @{
+ */
+int bflb_sflash_kh25v40_write_protect(spi_flash_cfg_type *flash_cfg, uint8_t protect);
+int bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value,
+                                  uint8_t reg_len);
+int bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value,
+                                   uint8_t reg_len);
+int bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg);
+
+/*@} end of group SFLAH_EXT_Public_Functions */
+
+/*@} end of group SFLAH_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_SFLAH_EXT_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_snflash.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_snflash.h
new file mode 100755
index 0000000000..0974d5518a
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_snflash.h
@@ -0,0 +1,183 @@
+/**
+  ******************************************************************************
+  * @file    bl702_snflash.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef NANDFLASH_XT26G01A_H
+#define NANDFLASH_XT26G01A_H
+
+#include "bl702_aon.h"
+#include "bl702_common.h"
+#include "bl702_glb.h"
+#include "bl702_hbn.h"
+#include "bl702_spi.h"
+#include "bl702_gpio.h"
+
+#include "ffconf.h"
+#include "ff.h"
+#include "diskio.h"
+
+#define FLASH_WRITE_READ_SIZE (2560)
+#define READ_PRINT_OPEN       (0)
+
+#define SPI_PIN_CLK  GLB_GPIO_PIN_11
+#define SPI_PIN_MOSI GLB_GPIO_PIN_12
+#define SPI_PIN_MISO GLB_GPIO_PIN_21
+#define SPI_PIN_CS   GLB_GPIO_PIN_10
+
+#define NANDFLASH_WRITE_ENABLE             (0x06)
+#define NANDFLASH_WRITE_DISABLE            (0x04)
+#define NANDFLASH_GET_FEATURES             (0x0F)
+#define NANDFLASH_SET_FEATURES             (0x1F)
+#define NANDFLASH_PAGE_READ_TO_CACHE       (0x13)
+#define NANDFLASH_READ_FROM_CACHE          (0x03)
+#define NANDFLASH_READ_ID                  (0x9F)
+#define NANDFLASH_PROGRAM_LOAD             (0x02)
+#define NANDFLASH_PROGRAM_LOAD_RANDOM_DATA (0x84)
+#define NANDFLASH_PROGRAM_EXECUTE          (0x10)
+#define NANDFLASH_BLOCK_ERASE              (0xD8)
+#define NANDFLASH_RESET                    (0xFF)
+
+#define NANDFLASH_BLOCK_LOCK_ADDR (0xA0)
+#define NANDFLASH_FEATURE_ADDR    (0xB0)
+#define NANDFLASH_STATUS_ADDR     (0xC0)
+#define NANDFLASH_DUMMY_BYTE      (0x00)
+#define NANDFLASH_PAGE_SIZE       (2048)
+#define NANDFLASH_PAGE_TOTAL_SIZE (2048 + 64)
+#define NANDFLASH_BLOCK_SIZE      (128 * 1024)
+#define NANDFLASH_PAGES_PER_BLOCK (64)
+
+typedef struct
+{
+    SPI_ID_Type spiNo;
+    SPI_CFG_Type spiCfg;
+    SPI_ClockCfg_Type clockCfg;
+} NANDFLASH_CFG_Type;
+
+extern NANDFLASH_CFG_Type nfCfg;
+
+typedef struct
+{
+    uint8_t Reserved0 : 1;
+    uint8_t CMP       : 1;
+    uint8_t INV       : 1;
+    uint8_t BP0       : 1;
+    uint8_t BP1       : 1;
+    uint8_t BP2       : 1;
+    uint8_t Reserved6 : 1;
+    uint8_t BRWD      : 1;
+} NANDFLASH_BLOCK_LOCK_Type;
+
+typedef struct
+{
+    uint8_t QE        : 1;
+    uint8_t Reserved1 : 1;
+    uint8_t Reserved2 : 1;
+    uint8_t Reserved3 : 1;
+    uint8_t ECC_EN    : 1;
+    uint8_t Reserved5 : 1;
+    uint8_t OTP_EN    : 1;
+    uint8_t OTP_PRT   : 1;
+} NANDFLASH_FEATURE_Type;
+
+typedef struct
+{
+    uint8_t OIP         : 1;
+    uint8_t WEL         : 1;
+    uint8_t EFAIL_ECCS0 : 1;
+    uint8_t PFAIL_ECCS1 : 1;
+    uint8_t ECCS2       : 1;
+    uint8_t ECCS3       : 1;
+    uint8_t Reserved6   : 1;
+    uint8_t Reserved7   : 1;
+} NANDFLASH_STATUS_Type;
+
+typedef enum {
+    NO_BIT_ERROR = 0,
+    ONE_BIT_ERROR_DETECTED_AND_CORRECTED = 1,
+    TWO_BIT_ERROR_DETECTED_AND_CORRECTED = 2,
+    THREE_BIT_ERROR_DETECTED_AND_CORRECTED = 3,
+    FOUR_BIT_ERROR_DETECTED_AND_CORRECTED = 4,
+    FIVE_BIT_ERROR_DETECTED_AND_CORRECTED = 5,
+    SIX_BIT_ERROR_DETECTED_AND_CORRECTED = 6,
+    SEVEN_BIT_ERROR_DETECTED_AND_CORRECTED = 7,
+    BIT_ERROR_DETECTED_AND_NOT_CORRECTED = 8,
+    EIGHT_BIT_ERROR_DETECTED_AND_CORRECTED_MAX = 9
+} NANDFLASH_ECC_Type;
+
+void ATTR_TCM_SECTION Nandflash_Psram_Cfg(void);
+void Nandflash_Init(void);
+
+void Nandflash_Gpio_Init(GLB_GPIO_Type clk, GLB_GPIO_Type mosi, GLB_GPIO_Type miso);
+void Nandflash_CS_High(void);
+void Nandflash_CS_Low(void);
+void Nandflash_Clock_Init(uint8_t enable, uint8_t div);
+void Nandflash_SPI_Init(NANDFLASH_CFG_Type *pNandflashCfg);
+
+void Nandflash_WriteEnable(NANDFLASH_CFG_Type *pNandflashCfg);
+void Nandflash_WriteDisable(NANDFLASH_CFG_Type *pNandflashCfg);
+void Nandflash_Get_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock);
+void Nandflash_Set_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock);
+void Nandflash_Get_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature);
+void Nandflash_Set_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature);
+void Nandflash_Get_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus);
+void Nandflash_Set_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus);
+
+NANDFLASH_ECC_Type Nandflash_CheckBadBlock(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum, uint8_t *buff, uint32_t len);
+
+NANDFLASH_ECC_Type Nandflash_PagesRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len);
+NANDFLASH_ECC_Type Nandflash_PageRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len);
+NANDFLASH_ECC_Type Nandflash_PageReadToCache(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr);
+void Nandflash_ReadFromCache(NANDFLASH_CFG_Type *pNandflashCfg, uint16_t offset, uint8_t *buff, uint32_t len);
+
+void Nandflash_ReadID(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pManufactureID, uint8_t *pDeviceID);
+void Nandflash_PagesProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len);
+void Nandflash_PageProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len);
+void Nandflash_ProgramLoad(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t pageOffset, const uint8_t *buff, uint32_t len);
+void Nandflash_ProgramExecute(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr);
+void Nandflash_InternalDataMove(NANDFLASH_CFG_Type *pNandflashCfg);
+void Nandflash_ProgramLoadRandomData(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len);
+void Nandflash_BlockErase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr);
+void Nandflash_Reset(NANDFLASH_CFG_Type *pNandflashCfg);
+
+void Nandflash_WriteUnprotect(NANDFLASH_CFG_Type *pNandflashCfg);
+NANDFLASH_ECC_Type Nandflash_Check_ECC_Status(NANDFLASH_CFG_Type *pNandflashCfg);
+
+int Nandflash_Disk_Status(void);
+int Nandflash_Disk_Initialize(void);
+int Nandflash_Disk_Read(BYTE *buff, LBA_t sector, UINT count);
+int Nandflash_Disk_Write(const BYTE *buff, LBA_t sector, UINT count);
+int Nandflash_Disk_Ioctl(BYTE cmd, void *buff);
+DSTATUS Nandflash_Translate_Result_Code(int result);
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h
new file mode 100755
index 0000000000..7362f8de7e
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/bl702_xip_sflash_ext.h
@@ -0,0 +1,88 @@
+/**
+  ******************************************************************************
+  * @file    bl702_xip_sflash_ext.h
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver header file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __BL702_XIP_SFLASH_EXT_H__
+#define __BL702_XIP_SFLASH_EXT_H__
+
+#include "bl702_common.h"
+#include "bflb_xip_sflash.h"
+#include "bflb_sflash.h"
+#include "bl702_sflash_ext.h"
+#include "bflb_sf_cfg.h"
+#include "bl702_sf_cfg_ext.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Types */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Constants
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Constants */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Public_Macros */
+
+/** @defgroup  XIP_SFLASH_EXT_Public_Functions
+ *  @{
+ */
+
+void bflb_xip_sflash_opt_enter(uint8_t *aes_enable);
+void bflb_xip_sflash_opt_exit(uint8_t aes_enable);
+int bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr,uint8_t *data, uint32_t len, uint8_t group, uint8_t bank);
+int bflb_xip_sflash_kh25v40_write_protect_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t protect);
+int bflb_xip_sflash_clear_status_register_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank);
+
+/*@} end of group XIP_SFLASH_EXT_Public_Functions */
+
+/*@} end of group XIP_SFLASH */
+
+/*@} end of group BL702_Peripheral_Driver */
+
+#endif /* __BL702_XIP_SFLASH_EXT_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/aon_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/aon_reg.h
new file mode 100755
index 0000000000..bb58183277
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/aon_reg.h
@@ -0,0 +1,1579 @@
+/**
+  ******************************************************************************
+  * @file    aon_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __AON_REG_H__
+#define __AON_REG_H__
+
+#include "bl702.h"
+
+/* 0x800 : aon */
+#define AON_OFFSET                     (0x800)
+#define AON_RESV                       AON_RESV
+#define AON_RESV_POS                   (0U)
+#define AON_RESV_LEN                   (8U)
+#define AON_RESV_MSK                   (((1U << AON_RESV_LEN) - 1) << AON_RESV_POS)
+#define AON_RESV_UMSK                  (~(((1U << AON_RESV_LEN) - 1) << AON_RESV_POS))
+#define AON_PU_AON_DC_TBUF             AON_PU_AON_DC_TBUF
+#define AON_PU_AON_DC_TBUF_POS         (12U)
+#define AON_PU_AON_DC_TBUF_LEN         (1U)
+#define AON_PU_AON_DC_TBUF_MSK         (((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS)
+#define AON_PU_AON_DC_TBUF_UMSK        (~(((1U << AON_PU_AON_DC_TBUF_LEN) - 1) << AON_PU_AON_DC_TBUF_POS))
+#define AON_LDO11_RT_PULLDOWN          AON_LDO11_RT_PULLDOWN
+#define AON_LDO11_RT_PULLDOWN_POS      (20U)
+#define AON_LDO11_RT_PULLDOWN_LEN      (1U)
+#define AON_LDO11_RT_PULLDOWN_MSK      (((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS)
+#define AON_LDO11_RT_PULLDOWN_UMSK     (~(((1U << AON_LDO11_RT_PULLDOWN_LEN) - 1) << AON_LDO11_RT_PULLDOWN_POS))
+#define AON_LDO11_RT_PULLDOWN_SEL      AON_LDO11_RT_PULLDOWN_SEL
+#define AON_LDO11_RT_PULLDOWN_SEL_POS  (21U)
+#define AON_LDO11_RT_PULLDOWN_SEL_LEN  (1U)
+#define AON_LDO11_RT_PULLDOWN_SEL_MSK  (((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS)
+#define AON_LDO11_RT_PULLDOWN_SEL_UMSK (~(((1U << AON_LDO11_RT_PULLDOWN_SEL_LEN) - 1) << AON_LDO11_RT_PULLDOWN_SEL_POS))
+#define AON_SW_PU_LDO11_RT             AON_SW_PU_LDO11_RT
+#define AON_SW_PU_LDO11_RT_POS         (22U)
+#define AON_SW_PU_LDO11_RT_LEN         (1U)
+#define AON_SW_PU_LDO11_RT_MSK         (((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS)
+#define AON_SW_PU_LDO11_RT_UMSK        (~(((1U << AON_SW_PU_LDO11_RT_LEN) - 1) << AON_SW_PU_LDO11_RT_POS))
+
+/* 0x804 : aon_common */
+#define AON_COMMON_OFFSET         (0x804)
+#define AON_TMUX_AON              AON_TMUX_AON
+#define AON_TMUX_AON_POS          (0U)
+#define AON_TMUX_AON_LEN          (3U)
+#define AON_TMUX_AON_MSK          (((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS)
+#define AON_TMUX_AON_UMSK         (~(((1U << AON_TMUX_AON_LEN) - 1) << AON_TMUX_AON_POS))
+#define AON_TEN_AON               AON_TEN_AON
+#define AON_TEN_AON_POS           (4U)
+#define AON_TEN_AON_LEN           (1U)
+#define AON_TEN_AON_MSK           (((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS)
+#define AON_TEN_AON_UMSK          (~(((1U << AON_TEN_AON_LEN) - 1) << AON_TEN_AON_POS))
+#define AON_DTEN_XTAL32K          AON_DTEN_XTAL32K
+#define AON_DTEN_XTAL32K_POS      (5U)
+#define AON_DTEN_XTAL32K_LEN      (1U)
+#define AON_DTEN_XTAL32K_MSK      (((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS)
+#define AON_DTEN_XTAL32K_UMSK     (~(((1U << AON_DTEN_XTAL32K_LEN) - 1) << AON_DTEN_XTAL32K_POS))
+#define AON_TEN_XTAL32K           AON_TEN_XTAL32K
+#define AON_TEN_XTAL32K_POS       (6U)
+#define AON_TEN_XTAL32K_LEN       (1U)
+#define AON_TEN_XTAL32K_MSK       (((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS)
+#define AON_TEN_XTAL32K_UMSK      (~(((1U << AON_TEN_XTAL32K_LEN) - 1) << AON_TEN_XTAL32K_POS))
+#define AON_TEN_VDDCORE_AON       AON_TEN_VDDCORE_AON
+#define AON_TEN_VDDCORE_AON_POS   (8U)
+#define AON_TEN_VDDCORE_AON_LEN   (1U)
+#define AON_TEN_VDDCORE_AON_MSK   (((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS)
+#define AON_TEN_VDDCORE_AON_UMSK  (~(((1U << AON_TEN_VDDCORE_AON_LEN) - 1) << AON_TEN_VDDCORE_AON_POS))
+#define AON_TEN_LDO11SOC_AON      AON_TEN_LDO11SOC_AON
+#define AON_TEN_LDO11SOC_AON_POS  (9U)
+#define AON_TEN_LDO11SOC_AON_LEN  (1U)
+#define AON_TEN_LDO11SOC_AON_MSK  (((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS)
+#define AON_TEN_LDO11SOC_AON_UMSK (~(((1U << AON_TEN_LDO11SOC_AON_LEN) - 1) << AON_TEN_LDO11SOC_AON_POS))
+#define AON_TEN_DCDC18_0_AON      AON_TEN_DCDC18_0_AON
+#define AON_TEN_DCDC18_0_AON_POS  (10U)
+#define AON_TEN_DCDC18_0_AON_LEN  (1U)
+#define AON_TEN_DCDC18_0_AON_MSK  (((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS)
+#define AON_TEN_DCDC18_0_AON_UMSK (~(((1U << AON_TEN_DCDC18_0_AON_LEN) - 1) << AON_TEN_DCDC18_0_AON_POS))
+#define AON_TEN_DCDC18_1_AON      AON_TEN_DCDC18_1_AON
+#define AON_TEN_DCDC18_1_AON_POS  (11U)
+#define AON_TEN_DCDC18_1_AON_LEN  (1U)
+#define AON_TEN_DCDC18_1_AON_MSK  (((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS)
+#define AON_TEN_DCDC18_1_AON_UMSK (~(((1U << AON_TEN_DCDC18_1_AON_LEN) - 1) << AON_TEN_DCDC18_1_AON_POS))
+#define AON_TEN_BG_SYS_AON        AON_TEN_BG_SYS_AON
+#define AON_TEN_BG_SYS_AON_POS    (12U)
+#define AON_TEN_BG_SYS_AON_LEN    (1U)
+#define AON_TEN_BG_SYS_AON_MSK    (((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS)
+#define AON_TEN_BG_SYS_AON_UMSK   (~(((1U << AON_TEN_BG_SYS_AON_LEN) - 1) << AON_TEN_BG_SYS_AON_POS))
+#define AON_TEN_LDO15RF_AON       AON_TEN_LDO15RF_AON
+#define AON_TEN_LDO15RF_AON_POS   (16U)
+#define AON_TEN_LDO15RF_AON_LEN   (1U)
+#define AON_TEN_LDO15RF_AON_MSK   (((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS)
+#define AON_TEN_LDO15RF_AON_UMSK  (~(((1U << AON_TEN_LDO15RF_AON_LEN) - 1) << AON_TEN_LDO15RF_AON_POS))
+#define AON_TEN_XTAL_AON          AON_TEN_XTAL_AON
+#define AON_TEN_XTAL_AON_POS      (17U)
+#define AON_TEN_XTAL_AON_LEN      (1U)
+#define AON_TEN_XTAL_AON_MSK      (((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS)
+#define AON_TEN_XTAL_AON_UMSK     (~(((1U << AON_TEN_XTAL_AON_LEN) - 1) << AON_TEN_XTAL_AON_POS))
+#define AON_DTEN_XTAL_AON         AON_DTEN_XTAL_AON
+#define AON_DTEN_XTAL_AON_POS     (18U)
+#define AON_DTEN_XTAL_AON_LEN     (1U)
+#define AON_DTEN_XTAL_AON_MSK     (((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS)
+#define AON_DTEN_XTAL_AON_UMSK    (~(((1U << AON_DTEN_XTAL_AON_LEN) - 1) << AON_DTEN_XTAL_AON_POS))
+#define AON_TEN_MBG_AON           AON_TEN_MBG_AON
+#define AON_TEN_MBG_AON_POS       (19U)
+#define AON_TEN_MBG_AON_LEN       (1U)
+#define AON_TEN_MBG_AON_MSK       (((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS)
+#define AON_TEN_MBG_AON_UMSK      (~(((1U << AON_TEN_MBG_AON_LEN) - 1) << AON_TEN_MBG_AON_POS))
+#define AON_TEN_CIP_MISC_AON      AON_TEN_CIP_MISC_AON
+#define AON_TEN_CIP_MISC_AON_POS  (20U)
+#define AON_TEN_CIP_MISC_AON_LEN  (1U)
+#define AON_TEN_CIP_MISC_AON_MSK  (((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS)
+#define AON_TEN_CIP_MISC_AON_UMSK (~(((1U << AON_TEN_CIP_MISC_AON_LEN) - 1) << AON_TEN_CIP_MISC_AON_POS))
+
+/* 0x808 : aon_misc */
+#define AON_MISC_OFFSET        (0x808)
+#define AON_SW_SOC_EN_AON      AON_SW_SOC_EN_AON
+#define AON_SW_SOC_EN_AON_POS  (0U)
+#define AON_SW_SOC_EN_AON_LEN  (1U)
+#define AON_SW_SOC_EN_AON_MSK  (((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS)
+#define AON_SW_SOC_EN_AON_UMSK (~(((1U << AON_SW_SOC_EN_AON_LEN) - 1) << AON_SW_SOC_EN_AON_POS))
+#define AON_SW_BZ_EN_AON       AON_SW_BZ_EN_AON
+#define AON_SW_BZ_EN_AON_POS   (1U)
+#define AON_SW_BZ_EN_AON_LEN   (1U)
+#define AON_SW_BZ_EN_AON_MSK   (((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS)
+#define AON_SW_BZ_EN_AON_UMSK  (~(((1U << AON_SW_BZ_EN_AON_LEN) - 1) << AON_SW_BZ_EN_AON_POS))
+
+/* 0x810 : bg_sys_top */
+#define AON_BG_SYS_TOP_OFFSET          (0x810)
+#define AON_PMIP_RESV                  AON_PMIP_RESV
+#define AON_PMIP_RESV_POS              (0U)
+#define AON_PMIP_RESV_LEN              (8U)
+#define AON_PMIP_RESV_MSK              (((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS)
+#define AON_PMIP_RESV_UMSK             (~(((1U << AON_PMIP_RESV_LEN) - 1) << AON_PMIP_RESV_POS))
+#define AON_PU_BG_SYS_AON              AON_PU_BG_SYS_AON
+#define AON_PU_BG_SYS_AON_POS          (8U)
+#define AON_PU_BG_SYS_AON_LEN          (1U)
+#define AON_PU_BG_SYS_AON_MSK          (((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS)
+#define AON_PU_BG_SYS_AON_UMSK         (~(((1U << AON_PU_BG_SYS_AON_LEN) - 1) << AON_PU_BG_SYS_AON_POS))
+#define AON_BG_SYS_START_CTRL_AON      AON_BG_SYS_START_CTRL_AON
+#define AON_BG_SYS_START_CTRL_AON_POS  (12U)
+#define AON_BG_SYS_START_CTRL_AON_LEN  (1U)
+#define AON_BG_SYS_START_CTRL_AON_MSK  (((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS)
+#define AON_BG_SYS_START_CTRL_AON_UMSK (~(((1U << AON_BG_SYS_START_CTRL_AON_LEN) - 1) << AON_BG_SYS_START_CTRL_AON_POS))
+
+/* 0x814 : dcdc18_top_0 */
+#define AON_DCDC18_TOP_0_OFFSET            (0x814)
+#define AON_DCDC18_VOUT_SEL_AON            AON_DCDC18_VOUT_SEL_AON
+#define AON_DCDC18_VOUT_SEL_AON_POS        (1U)
+#define AON_DCDC18_VOUT_SEL_AON_LEN        (5U)
+#define AON_DCDC18_VOUT_SEL_AON_MSK        (((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS)
+#define AON_DCDC18_VOUT_SEL_AON_UMSK       (~(((1U << AON_DCDC18_VOUT_SEL_AON_LEN) - 1) << AON_DCDC18_VOUT_SEL_AON_POS))
+#define AON_DCDC18_VPFM_AON                AON_DCDC18_VPFM_AON
+#define AON_DCDC18_VPFM_AON_POS            (8U)
+#define AON_DCDC18_VPFM_AON_LEN            (4U)
+#define AON_DCDC18_VPFM_AON_MSK            (((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS)
+#define AON_DCDC18_VPFM_AON_UMSK           (~(((1U << AON_DCDC18_VPFM_AON_LEN) - 1) << AON_DCDC18_VPFM_AON_POS))
+#define AON_DCDC18_OSC_2M_MODE_AON         AON_DCDC18_OSC_2M_MODE_AON
+#define AON_DCDC18_OSC_2M_MODE_AON_POS     (12U)
+#define AON_DCDC18_OSC_2M_MODE_AON_LEN     (1U)
+#define AON_DCDC18_OSC_2M_MODE_AON_MSK     (((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS)
+#define AON_DCDC18_OSC_2M_MODE_AON_UMSK    (~(((1U << AON_DCDC18_OSC_2M_MODE_AON_LEN) - 1) << AON_DCDC18_OSC_2M_MODE_AON_POS))
+#define AON_DCDC18_OSC_FREQ_TRIM_AON       AON_DCDC18_OSC_FREQ_TRIM_AON
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_POS   (16U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_LEN   (4U)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_MSK   (((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS)
+#define AON_DCDC18_OSC_FREQ_TRIM_AON_UMSK  (~(((1U << AON_DCDC18_OSC_FREQ_TRIM_AON_LEN) - 1) << AON_DCDC18_OSC_FREQ_TRIM_AON_POS))
+#define AON_DCDC18_SLOPE_CURR_SEL_AON      AON_DCDC18_SLOPE_CURR_SEL_AON
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_POS  (20U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_LEN  (5U)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_MSK  (((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS)
+#define AON_DCDC18_SLOPE_CURR_SEL_AON_UMSK (~(((1U << AON_DCDC18_SLOPE_CURR_SEL_AON_LEN) - 1) << AON_DCDC18_SLOPE_CURR_SEL_AON_POS))
+#define AON_DCDC18_STOP_OSC_AON            AON_DCDC18_STOP_OSC_AON
+#define AON_DCDC18_STOP_OSC_AON_POS        (25U)
+#define AON_DCDC18_STOP_OSC_AON_LEN        (1U)
+#define AON_DCDC18_STOP_OSC_AON_MSK        (((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS)
+#define AON_DCDC18_STOP_OSC_AON_UMSK       (~(((1U << AON_DCDC18_STOP_OSC_AON_LEN) - 1) << AON_DCDC18_STOP_OSC_AON_POS))
+#define AON_DCDC18_SLOW_OSC_AON            AON_DCDC18_SLOW_OSC_AON
+#define AON_DCDC18_SLOW_OSC_AON_POS        (26U)
+#define AON_DCDC18_SLOW_OSC_AON_LEN        (1U)
+#define AON_DCDC18_SLOW_OSC_AON_MSK        (((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS)
+#define AON_DCDC18_SLOW_OSC_AON_UMSK       (~(((1U << AON_DCDC18_SLOW_OSC_AON_LEN) - 1) << AON_DCDC18_SLOW_OSC_AON_POS))
+#define AON_DCDC18_OSC_INHIBIT_T2_AON      AON_DCDC18_OSC_INHIBIT_T2_AON
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_POS  (27U)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_LEN  (1U)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_MSK  (((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS)
+#define AON_DCDC18_OSC_INHIBIT_T2_AON_UMSK (~(((1U << AON_DCDC18_OSC_INHIBIT_T2_AON_LEN) - 1) << AON_DCDC18_OSC_INHIBIT_T2_AON_POS))
+#define AON_DCDC18_SSTART_TIME_AON         AON_DCDC18_SSTART_TIME_AON
+#define AON_DCDC18_SSTART_TIME_AON_POS     (28U)
+#define AON_DCDC18_SSTART_TIME_AON_LEN     (2U)
+#define AON_DCDC18_SSTART_TIME_AON_MSK     (((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS)
+#define AON_DCDC18_SSTART_TIME_AON_UMSK    (~(((1U << AON_DCDC18_SSTART_TIME_AON_LEN) - 1) << AON_DCDC18_SSTART_TIME_AON_POS))
+#define AON_DCDC18_RDY_AON                 AON_DCDC18_RDY_AON
+#define AON_DCDC18_RDY_AON_POS             (31U)
+#define AON_DCDC18_RDY_AON_LEN             (1U)
+#define AON_DCDC18_RDY_AON_MSK             (((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS)
+#define AON_DCDC18_RDY_AON_UMSK            (~(((1U << AON_DCDC18_RDY_AON_LEN) - 1) << AON_DCDC18_RDY_AON_POS))
+
+/* 0x818 : dcdc18_top_1 */
+#define AON_DCDC18_TOP_1_OFFSET           (0x818)
+#define AON_DCDC18_FORCE_CS_ZVS_AON       AON_DCDC18_FORCE_CS_ZVS_AON
+#define AON_DCDC18_FORCE_CS_ZVS_AON_POS   (0U)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_LEN   (1U)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_MSK   (((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS)
+#define AON_DCDC18_FORCE_CS_ZVS_AON_UMSK  (~(((1U << AON_DCDC18_FORCE_CS_ZVS_AON_LEN) - 1) << AON_DCDC18_FORCE_CS_ZVS_AON_POS))
+#define AON_DCDC18_CS_DELAY_AON           AON_DCDC18_CS_DELAY_AON
+#define AON_DCDC18_CS_DELAY_AON_POS       (1U)
+#define AON_DCDC18_CS_DELAY_AON_LEN       (3U)
+#define AON_DCDC18_CS_DELAY_AON_MSK       (((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS)
+#define AON_DCDC18_CS_DELAY_AON_UMSK      (~(((1U << AON_DCDC18_CS_DELAY_AON_LEN) - 1) << AON_DCDC18_CS_DELAY_AON_POS))
+#define AON_DCDC18_ZVS_TD_OPT_AON         AON_DCDC18_ZVS_TD_OPT_AON
+#define AON_DCDC18_ZVS_TD_OPT_AON_POS     (4U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_LEN     (3U)
+#define AON_DCDC18_ZVS_TD_OPT_AON_MSK     (((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS)
+#define AON_DCDC18_ZVS_TD_OPT_AON_UMSK    (~(((1U << AON_DCDC18_ZVS_TD_OPT_AON_LEN) - 1) << AON_DCDC18_ZVS_TD_OPT_AON_POS))
+#define AON_DCDC18_NONOVERLAP_TD_AON      AON_DCDC18_NONOVERLAP_TD_AON
+#define AON_DCDC18_NONOVERLAP_TD_AON_POS  (8U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_LEN  (5U)
+#define AON_DCDC18_NONOVERLAP_TD_AON_MSK  (((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS)
+#define AON_DCDC18_NONOVERLAP_TD_AON_UMSK (~(((1U << AON_DCDC18_NONOVERLAP_TD_AON_LEN) - 1) << AON_DCDC18_NONOVERLAP_TD_AON_POS))
+#define AON_DCDC18_RC_SEL_AON             AON_DCDC18_RC_SEL_AON
+#define AON_DCDC18_RC_SEL_AON_POS         (16U)
+#define AON_DCDC18_RC_SEL_AON_LEN         (4U)
+#define AON_DCDC18_RC_SEL_AON_MSK         (((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS)
+#define AON_DCDC18_RC_SEL_AON_UMSK        (~(((1U << AON_DCDC18_RC_SEL_AON_LEN) - 1) << AON_DCDC18_RC_SEL_AON_POS))
+#define AON_DCDC18_CHF_SEL_AON            AON_DCDC18_CHF_SEL_AON
+#define AON_DCDC18_CHF_SEL_AON_POS        (20U)
+#define AON_DCDC18_CHF_SEL_AON_LEN        (4U)
+#define AON_DCDC18_CHF_SEL_AON_MSK        (((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS)
+#define AON_DCDC18_CHF_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CHF_SEL_AON_LEN) - 1) << AON_DCDC18_CHF_SEL_AON_POS))
+#define AON_DCDC18_CFB_SEL_AON            AON_DCDC18_CFB_SEL_AON
+#define AON_DCDC18_CFB_SEL_AON_POS        (24U)
+#define AON_DCDC18_CFB_SEL_AON_LEN        (4U)
+#define AON_DCDC18_CFB_SEL_AON_MSK        (((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS)
+#define AON_DCDC18_CFB_SEL_AON_UMSK       (~(((1U << AON_DCDC18_CFB_SEL_AON_LEN) - 1) << AON_DCDC18_CFB_SEL_AON_POS))
+#define AON_DCDC18_EN_ANTIRING_AON        AON_DCDC18_EN_ANTIRING_AON
+#define AON_DCDC18_EN_ANTIRING_AON_POS    (28U)
+#define AON_DCDC18_EN_ANTIRING_AON_LEN    (1U)
+#define AON_DCDC18_EN_ANTIRING_AON_MSK    (((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS)
+#define AON_DCDC18_EN_ANTIRING_AON_UMSK   (~(((1U << AON_DCDC18_EN_ANTIRING_AON_LEN) - 1) << AON_DCDC18_EN_ANTIRING_AON_POS))
+#define AON_DCDC18_PULLDOWN_AON           AON_DCDC18_PULLDOWN_AON
+#define AON_DCDC18_PULLDOWN_AON_POS       (29U)
+#define AON_DCDC18_PULLDOWN_AON_LEN       (1U)
+#define AON_DCDC18_PULLDOWN_AON_MSK       (((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS)
+#define AON_DCDC18_PULLDOWN_AON_UMSK      (~(((1U << AON_DCDC18_PULLDOWN_AON_LEN) - 1) << AON_DCDC18_PULLDOWN_AON_POS))
+
+/* 0x81C : ldo11soc_and_dctest */
+#define AON_LDO11SOC_AND_DCTEST_OFFSET     (0x81C)
+#define AON_PU_LDO11SOC_AON                AON_PU_LDO11SOC_AON
+#define AON_PU_LDO11SOC_AON_POS            (0U)
+#define AON_PU_LDO11SOC_AON_LEN            (1U)
+#define AON_PU_LDO11SOC_AON_MSK            (((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS)
+#define AON_PU_LDO11SOC_AON_UMSK           (~(((1U << AON_PU_LDO11SOC_AON_LEN) - 1) << AON_PU_LDO11SOC_AON_POS))
+#define AON_LDO11SOC_SSTART_SEL_AON        AON_LDO11SOC_SSTART_SEL_AON
+#define AON_LDO11SOC_SSTART_SEL_AON_POS    (4U)
+#define AON_LDO11SOC_SSTART_SEL_AON_LEN    (1U)
+#define AON_LDO11SOC_SSTART_SEL_AON_MSK    (((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS)
+#define AON_LDO11SOC_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO11SOC_SSTART_SEL_AON_LEN) - 1) << AON_LDO11SOC_SSTART_SEL_AON_POS))
+#define AON_LDO11SOC_SSTART_DELAY_AON      AON_LDO11SOC_SSTART_DELAY_AON
+#define AON_LDO11SOC_SSTART_DELAY_AON_POS  (8U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO11SOC_SSTART_DELAY_AON_MSK  (((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS)
+#define AON_LDO11SOC_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO11SOC_SSTART_DELAY_AON_LEN) - 1) << AON_LDO11SOC_SSTART_DELAY_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_AON          AON_LDO11SOC_PULLDOWN_AON
+#define AON_LDO11SOC_PULLDOWN_AON_POS      (10U)
+#define AON_LDO11SOC_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO11SOC_PULLDOWN_AON_MSK      (((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO11SOC_PULLDOWN_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_AON_POS))
+#define AON_LDO11SOC_PULLDOWN_SEL_AON      AON_LDO11SOC_PULLDOWN_SEL_AON
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_POS  (11U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS)
+#define AON_LDO11SOC_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO11SOC_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO11SOC_PULLDOWN_SEL_AON_POS))
+#define AON_LDO11SOC_VTH_SEL_AON           AON_LDO11SOC_VTH_SEL_AON
+#define AON_LDO11SOC_VTH_SEL_AON_POS       (12U)
+#define AON_LDO11SOC_VTH_SEL_AON_LEN       (2U)
+#define AON_LDO11SOC_VTH_SEL_AON_MSK       (((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS)
+#define AON_LDO11SOC_VTH_SEL_AON_UMSK      (~(((1U << AON_LDO11SOC_VTH_SEL_AON_LEN) - 1) << AON_LDO11SOC_VTH_SEL_AON_POS))
+#define AON_LDO11SOC_CC_AON                AON_LDO11SOC_CC_AON
+#define AON_LDO11SOC_CC_AON_POS            (24U)
+#define AON_LDO11SOC_CC_AON_LEN            (2U)
+#define AON_LDO11SOC_CC_AON_MSK            (((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS)
+#define AON_LDO11SOC_CC_AON_UMSK           (~(((1U << AON_LDO11SOC_CC_AON_LEN) - 1) << AON_LDO11SOC_CC_AON_POS))
+#define AON_LDO11SOC_RDY_AON               AON_LDO11SOC_RDY_AON
+#define AON_LDO11SOC_RDY_AON_POS           (28U)
+#define AON_LDO11SOC_RDY_AON_LEN           (1U)
+#define AON_LDO11SOC_RDY_AON_MSK           (((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS)
+#define AON_LDO11SOC_RDY_AON_UMSK          (~(((1U << AON_LDO11SOC_RDY_AON_LEN) - 1) << AON_LDO11SOC_RDY_AON_POS))
+#define AON_LDO11SOC_POWER_GOOD_AON        AON_LDO11SOC_POWER_GOOD_AON
+#define AON_LDO11SOC_POWER_GOOD_AON_POS    (29U)
+#define AON_LDO11SOC_POWER_GOOD_AON_LEN    (1U)
+#define AON_LDO11SOC_POWER_GOOD_AON_MSK    (((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS)
+#define AON_LDO11SOC_POWER_GOOD_AON_UMSK   (~(((1U << AON_LDO11SOC_POWER_GOOD_AON_LEN) - 1) << AON_LDO11SOC_POWER_GOOD_AON_POS))
+#define AON_PU_VDDCORE_MISC_AON            AON_PU_VDDCORE_MISC_AON
+#define AON_PU_VDDCORE_MISC_AON_POS        (30U)
+#define AON_PU_VDDCORE_MISC_AON_LEN        (1U)
+#define AON_PU_VDDCORE_MISC_AON_MSK        (((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS)
+#define AON_PU_VDDCORE_MISC_AON_UMSK       (~(((1U << AON_PU_VDDCORE_MISC_AON_LEN) - 1) << AON_PU_VDDCORE_MISC_AON_POS))
+#define AON_PMIP_DC_TP_OUT_EN_AON          AON_PMIP_DC_TP_OUT_EN_AON
+#define AON_PMIP_DC_TP_OUT_EN_AON_POS      (31U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_LEN      (1U)
+#define AON_PMIP_DC_TP_OUT_EN_AON_MSK      (((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS)
+#define AON_PMIP_DC_TP_OUT_EN_AON_UMSK     (~(((1U << AON_PMIP_DC_TP_OUT_EN_AON_LEN) - 1) << AON_PMIP_DC_TP_OUT_EN_AON_POS))
+
+/* 0x820 : psw_irrcv */
+#define AON_PSW_IRRCV_OFFSET   (0x820)
+#define AON_PU_IR_PSW_AON      AON_PU_IR_PSW_AON
+#define AON_PU_IR_PSW_AON_POS  (0U)
+#define AON_PU_IR_PSW_AON_LEN  (1U)
+#define AON_PU_IR_PSW_AON_MSK  (((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS)
+#define AON_PU_IR_PSW_AON_UMSK (~(((1U << AON_PU_IR_PSW_AON_LEN) - 1) << AON_PU_IR_PSW_AON_POS))
+
+/* 0x880 : rf_top_aon */
+#define AON_RF_TOP_AON_OFFSET             (0x880)
+#define AON_PU_MBG_AON                    AON_PU_MBG_AON
+#define AON_PU_MBG_AON_POS                (0U)
+#define AON_PU_MBG_AON_LEN                (1U)
+#define AON_PU_MBG_AON_MSK                (((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS)
+#define AON_PU_MBG_AON_UMSK               (~(((1U << AON_PU_MBG_AON_LEN) - 1) << AON_PU_MBG_AON_POS))
+#define AON_PU_LDO15RF_AON                AON_PU_LDO15RF_AON
+#define AON_PU_LDO15RF_AON_POS            (1U)
+#define AON_PU_LDO15RF_AON_LEN            (1U)
+#define AON_PU_LDO15RF_AON_MSK            (((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS)
+#define AON_PU_LDO15RF_AON_UMSK           (~(((1U << AON_PU_LDO15RF_AON_LEN) - 1) << AON_PU_LDO15RF_AON_POS))
+#define AON_PU_SFREG_AON                  AON_PU_SFREG_AON
+#define AON_PU_SFREG_AON_POS              (2U)
+#define AON_PU_SFREG_AON_LEN              (1U)
+#define AON_PU_SFREG_AON_MSK              (((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS)
+#define AON_PU_SFREG_AON_UMSK             (~(((1U << AON_PU_SFREG_AON_LEN) - 1) << AON_PU_SFREG_AON_POS))
+#define AON_PU_XTAL_BUF_AON               AON_PU_XTAL_BUF_AON
+#define AON_PU_XTAL_BUF_AON_POS           (4U)
+#define AON_PU_XTAL_BUF_AON_LEN           (1U)
+#define AON_PU_XTAL_BUF_AON_MSK           (((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS)
+#define AON_PU_XTAL_BUF_AON_UMSK          (~(((1U << AON_PU_XTAL_BUF_AON_LEN) - 1) << AON_PU_XTAL_BUF_AON_POS))
+#define AON_PU_XTAL_AON                   AON_PU_XTAL_AON
+#define AON_PU_XTAL_AON_POS               (5U)
+#define AON_PU_XTAL_AON_LEN               (1U)
+#define AON_PU_XTAL_AON_MSK               (((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS)
+#define AON_PU_XTAL_AON_UMSK              (~(((1U << AON_PU_XTAL_AON_LEN) - 1) << AON_PU_XTAL_AON_POS))
+#define AON_LDO15RF_SSTART_SEL_AON        AON_LDO15RF_SSTART_SEL_AON
+#define AON_LDO15RF_SSTART_SEL_AON_POS    (8U)
+#define AON_LDO15RF_SSTART_SEL_AON_LEN    (1U)
+#define AON_LDO15RF_SSTART_SEL_AON_MSK    (((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS)
+#define AON_LDO15RF_SSTART_SEL_AON_UMSK   (~(((1U << AON_LDO15RF_SSTART_SEL_AON_LEN) - 1) << AON_LDO15RF_SSTART_SEL_AON_POS))
+#define AON_LDO15RF_SSTART_DELAY_AON      AON_LDO15RF_SSTART_DELAY_AON
+#define AON_LDO15RF_SSTART_DELAY_AON_POS  (9U)
+#define AON_LDO15RF_SSTART_DELAY_AON_LEN  (2U)
+#define AON_LDO15RF_SSTART_DELAY_AON_MSK  (((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS)
+#define AON_LDO15RF_SSTART_DELAY_AON_UMSK (~(((1U << AON_LDO15RF_SSTART_DELAY_AON_LEN) - 1) << AON_LDO15RF_SSTART_DELAY_AON_POS))
+#define AON_LDO15RF_PULLDOWN_AON          AON_LDO15RF_PULLDOWN_AON
+#define AON_LDO15RF_PULLDOWN_AON_POS      (12U)
+#define AON_LDO15RF_PULLDOWN_AON_LEN      (1U)
+#define AON_LDO15RF_PULLDOWN_AON_MSK      (((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS)
+#define AON_LDO15RF_PULLDOWN_AON_UMSK     (~(((1U << AON_LDO15RF_PULLDOWN_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_AON_POS))
+#define AON_LDO15RF_PULLDOWN_SEL_AON      AON_LDO15RF_PULLDOWN_SEL_AON
+#define AON_LDO15RF_PULLDOWN_SEL_AON_POS  (13U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_LEN  (1U)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_MSK  (((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS)
+#define AON_LDO15RF_PULLDOWN_SEL_AON_UMSK (~(((1U << AON_LDO15RF_PULLDOWN_SEL_AON_LEN) - 1) << AON_LDO15RF_PULLDOWN_SEL_AON_POS))
+#define AON_LDO15RF_VOUT_SEL_AON          AON_LDO15RF_VOUT_SEL_AON
+#define AON_LDO15RF_VOUT_SEL_AON_POS      (16U)
+#define AON_LDO15RF_VOUT_SEL_AON_LEN      (3U)
+#define AON_LDO15RF_VOUT_SEL_AON_MSK      (((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS)
+#define AON_LDO15RF_VOUT_SEL_AON_UMSK     (~(((1U << AON_LDO15RF_VOUT_SEL_AON_LEN) - 1) << AON_LDO15RF_VOUT_SEL_AON_POS))
+#define AON_LDO15RF_CC_AON                AON_LDO15RF_CC_AON
+#define AON_LDO15RF_CC_AON_POS            (24U)
+#define AON_LDO15RF_CC_AON_LEN            (2U)
+#define AON_LDO15RF_CC_AON_MSK            (((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS)
+#define AON_LDO15RF_CC_AON_UMSK           (~(((1U << AON_LDO15RF_CC_AON_LEN) - 1) << AON_LDO15RF_CC_AON_POS))
+#define AON_LDO15RF_BYPASS_AON            AON_LDO15RF_BYPASS_AON
+#define AON_LDO15RF_BYPASS_AON_POS        (28U)
+#define AON_LDO15RF_BYPASS_AON_LEN        (1U)
+#define AON_LDO15RF_BYPASS_AON_MSK        (((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS)
+#define AON_LDO15RF_BYPASS_AON_UMSK       (~(((1U << AON_LDO15RF_BYPASS_AON_LEN) - 1) << AON_LDO15RF_BYPASS_AON_POS))
+
+/* 0x884 : xtal_cfg */
+#define AON_XTAL_CFG_OFFSET             (0x884)
+#define AON_XTAL_BK_AON                 AON_XTAL_BK_AON
+#define AON_XTAL_BK_AON_POS             (0U)
+#define AON_XTAL_BK_AON_LEN             (2U)
+#define AON_XTAL_BK_AON_MSK             (((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS)
+#define AON_XTAL_BK_AON_UMSK            (~(((1U << AON_XTAL_BK_AON_LEN) - 1) << AON_XTAL_BK_AON_POS))
+#define AON_XTAL_CAPCODE_EXTRA_AON      AON_XTAL_CAPCODE_EXTRA_AON
+#define AON_XTAL_CAPCODE_EXTRA_AON_POS  (2U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_LEN  (1U)
+#define AON_XTAL_CAPCODE_EXTRA_AON_MSK  (((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS)
+#define AON_XTAL_CAPCODE_EXTRA_AON_UMSK (~(((1U << AON_XTAL_CAPCODE_EXTRA_AON_LEN) - 1) << AON_XTAL_CAPCODE_EXTRA_AON_POS))
+#define AON_XTAL_EXT_SEL_AON            AON_XTAL_EXT_SEL_AON
+#define AON_XTAL_EXT_SEL_AON_POS        (3U)
+#define AON_XTAL_EXT_SEL_AON_LEN        (1U)
+#define AON_XTAL_EXT_SEL_AON_MSK        (((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS)
+#define AON_XTAL_EXT_SEL_AON_UMSK       (~(((1U << AON_XTAL_EXT_SEL_AON_LEN) - 1) << AON_XTAL_EXT_SEL_AON_POS))
+#define AON_XTAL_BUF_EN_AON             AON_XTAL_BUF_EN_AON
+#define AON_XTAL_BUF_EN_AON_POS         (4U)
+#define AON_XTAL_BUF_EN_AON_LEN         (4U)
+#define AON_XTAL_BUF_EN_AON_MSK         (((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS)
+#define AON_XTAL_BUF_EN_AON_UMSK        (~(((1U << AON_XTAL_BUF_EN_AON_LEN) - 1) << AON_XTAL_BUF_EN_AON_POS))
+#define AON_XTAL_BUF_HP_AON             AON_XTAL_BUF_HP_AON
+#define AON_XTAL_BUF_HP_AON_POS         (8U)
+#define AON_XTAL_BUF_HP_AON_LEN         (4U)
+#define AON_XTAL_BUF_HP_AON_MSK         (((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS)
+#define AON_XTAL_BUF_HP_AON_UMSK        (~(((1U << AON_XTAL_BUF_HP_AON_LEN) - 1) << AON_XTAL_BUF_HP_AON_POS))
+#define AON_XTAL_FAST_STARTUP_AON       AON_XTAL_FAST_STARTUP_AON
+#define AON_XTAL_FAST_STARTUP_AON_POS   (12U)
+#define AON_XTAL_FAST_STARTUP_AON_LEN   (1U)
+#define AON_XTAL_FAST_STARTUP_AON_MSK   (((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS)
+#define AON_XTAL_FAST_STARTUP_AON_UMSK  (~(((1U << AON_XTAL_FAST_STARTUP_AON_LEN) - 1) << AON_XTAL_FAST_STARTUP_AON_POS))
+#define AON_XTAL_SLEEP_AON              AON_XTAL_SLEEP_AON
+#define AON_XTAL_SLEEP_AON_POS          (13U)
+#define AON_XTAL_SLEEP_AON_LEN          (1U)
+#define AON_XTAL_SLEEP_AON_MSK          (((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS)
+#define AON_XTAL_SLEEP_AON_UMSK         (~(((1U << AON_XTAL_SLEEP_AON_LEN) - 1) << AON_XTAL_SLEEP_AON_POS))
+#define AON_XTAL_AMP_CTRL_AON           AON_XTAL_AMP_CTRL_AON
+#define AON_XTAL_AMP_CTRL_AON_POS       (14U)
+#define AON_XTAL_AMP_CTRL_AON_LEN       (2U)
+#define AON_XTAL_AMP_CTRL_AON_MSK       (((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS)
+#define AON_XTAL_AMP_CTRL_AON_UMSK      (~(((1U << AON_XTAL_AMP_CTRL_AON_LEN) - 1) << AON_XTAL_AMP_CTRL_AON_POS))
+#define AON_XTAL_CAPCODE_OUT_AON        AON_XTAL_CAPCODE_OUT_AON
+#define AON_XTAL_CAPCODE_OUT_AON_POS    (16U)
+#define AON_XTAL_CAPCODE_OUT_AON_LEN    (6U)
+#define AON_XTAL_CAPCODE_OUT_AON_MSK    (((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS)
+#define AON_XTAL_CAPCODE_OUT_AON_UMSK   (~(((1U << AON_XTAL_CAPCODE_OUT_AON_LEN) - 1) << AON_XTAL_CAPCODE_OUT_AON_POS))
+#define AON_XTAL_CAPCODE_IN_AON         AON_XTAL_CAPCODE_IN_AON
+#define AON_XTAL_CAPCODE_IN_AON_POS     (22U)
+#define AON_XTAL_CAPCODE_IN_AON_LEN     (6U)
+#define AON_XTAL_CAPCODE_IN_AON_MSK     (((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS)
+#define AON_XTAL_CAPCODE_IN_AON_UMSK    (~(((1U << AON_XTAL_CAPCODE_IN_AON_LEN) - 1) << AON_XTAL_CAPCODE_IN_AON_POS))
+#define AON_XTAL_GM_BOOST_AON           AON_XTAL_GM_BOOST_AON
+#define AON_XTAL_GM_BOOST_AON_POS       (28U)
+#define AON_XTAL_GM_BOOST_AON_LEN       (2U)
+#define AON_XTAL_GM_BOOST_AON_MSK       (((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS)
+#define AON_XTAL_GM_BOOST_AON_UMSK      (~(((1U << AON_XTAL_GM_BOOST_AON_LEN) - 1) << AON_XTAL_GM_BOOST_AON_POS))
+#define AON_XTAL_RDY_SEL_AON            AON_XTAL_RDY_SEL_AON
+#define AON_XTAL_RDY_SEL_AON_POS        (30U)
+#define AON_XTAL_RDY_SEL_AON_LEN        (2U)
+#define AON_XTAL_RDY_SEL_AON_MSK        (((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS)
+#define AON_XTAL_RDY_SEL_AON_UMSK       (~(((1U << AON_XTAL_RDY_SEL_AON_LEN) - 1) << AON_XTAL_RDY_SEL_AON_POS))
+
+/* 0x888 : tsen */
+#define AON_TSEN_OFFSET               (0x888)
+#define AON_TSEN_REFCODE_CORNER       AON_TSEN_REFCODE_CORNER
+#define AON_TSEN_REFCODE_CORNER_POS   (0U)
+#define AON_TSEN_REFCODE_CORNER_LEN   (12U)
+#define AON_TSEN_REFCODE_CORNER_MSK   (((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS)
+#define AON_TSEN_REFCODE_CORNER_UMSK  (~(((1U << AON_TSEN_REFCODE_CORNER_LEN) - 1) << AON_TSEN_REFCODE_CORNER_POS))
+#define AON_TSEN_REFCODE_RFCAL        AON_TSEN_REFCODE_RFCAL
+#define AON_TSEN_REFCODE_RFCAL_POS    (16U)
+#define AON_TSEN_REFCODE_RFCAL_LEN    (12U)
+#define AON_TSEN_REFCODE_RFCAL_MSK    (((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS)
+#define AON_TSEN_REFCODE_RFCAL_UMSK   (~(((1U << AON_TSEN_REFCODE_RFCAL_LEN) - 1) << AON_TSEN_REFCODE_RFCAL_POS))
+#define AON_XTAL_RDY                  AON_XTAL_RDY
+#define AON_XTAL_RDY_POS              (28U)
+#define AON_XTAL_RDY_LEN              (1U)
+#define AON_XTAL_RDY_MSK              (((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS)
+#define AON_XTAL_RDY_UMSK             (~(((1U << AON_XTAL_RDY_LEN) - 1) << AON_XTAL_RDY_POS))
+#define AON_XTAL_INN_CFG_EN_AON       AON_XTAL_INN_CFG_EN_AON
+#define AON_XTAL_INN_CFG_EN_AON_POS   (29U)
+#define AON_XTAL_INN_CFG_EN_AON_LEN   (1U)
+#define AON_XTAL_INN_CFG_EN_AON_MSK   (((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS)
+#define AON_XTAL_INN_CFG_EN_AON_UMSK  (~(((1U << AON_XTAL_INN_CFG_EN_AON_LEN) - 1) << AON_XTAL_INN_CFG_EN_AON_POS))
+#define AON_XTAL_RDY_INT_SEL_AON      AON_XTAL_RDY_INT_SEL_AON
+#define AON_XTAL_RDY_INT_SEL_AON_POS  (30U)
+#define AON_XTAL_RDY_INT_SEL_AON_LEN  (2U)
+#define AON_XTAL_RDY_INT_SEL_AON_MSK  (((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS)
+#define AON_XTAL_RDY_INT_SEL_AON_UMSK (~(((1U << AON_XTAL_RDY_INT_SEL_AON_LEN) - 1) << AON_XTAL_RDY_INT_SEL_AON_POS))
+
+/* 0x900 : acomp0_ctrl */
+#define AON_ACOMP0_CTRL_OFFSET    (0x900)
+#define AON_ACOMP0_EN             AON_ACOMP0_EN
+#define AON_ACOMP0_EN_POS         (0U)
+#define AON_ACOMP0_EN_LEN         (1U)
+#define AON_ACOMP0_EN_MSK         (((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS)
+#define AON_ACOMP0_EN_UMSK        (~(((1U << AON_ACOMP0_EN_LEN) - 1) << AON_ACOMP0_EN_POS))
+#define AON_ACOMP0_HYST_SELN      AON_ACOMP0_HYST_SELN
+#define AON_ACOMP0_HYST_SELN_POS  (4U)
+#define AON_ACOMP0_HYST_SELN_LEN  (3U)
+#define AON_ACOMP0_HYST_SELN_MSK  (((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS)
+#define AON_ACOMP0_HYST_SELN_UMSK (~(((1U << AON_ACOMP0_HYST_SELN_LEN) - 1) << AON_ACOMP0_HYST_SELN_POS))
+#define AON_ACOMP0_HYST_SELP      AON_ACOMP0_HYST_SELP
+#define AON_ACOMP0_HYST_SELP_POS  (7U)
+#define AON_ACOMP0_HYST_SELP_LEN  (3U)
+#define AON_ACOMP0_HYST_SELP_MSK  (((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS)
+#define AON_ACOMP0_HYST_SELP_UMSK (~(((1U << AON_ACOMP0_HYST_SELP_LEN) - 1) << AON_ACOMP0_HYST_SELP_POS))
+#define AON_ACOMP0_BIAS_PROG      AON_ACOMP0_BIAS_PROG
+#define AON_ACOMP0_BIAS_PROG_POS  (10U)
+#define AON_ACOMP0_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP0_BIAS_PROG_MSK  (((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS)
+#define AON_ACOMP0_BIAS_PROG_UMSK (~(((1U << AON_ACOMP0_BIAS_PROG_LEN) - 1) << AON_ACOMP0_BIAS_PROG_POS))
+#define AON_ACOMP0_LEVEL_SEL      AON_ACOMP0_LEVEL_SEL
+#define AON_ACOMP0_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP0_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP0_LEVEL_SEL_MSK  (((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS)
+#define AON_ACOMP0_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP0_LEVEL_SEL_LEN) - 1) << AON_ACOMP0_LEVEL_SEL_POS))
+#define AON_ACOMP0_NEG_SEL        AON_ACOMP0_NEG_SEL
+#define AON_ACOMP0_NEG_SEL_POS    (18U)
+#define AON_ACOMP0_NEG_SEL_LEN    (4U)
+#define AON_ACOMP0_NEG_SEL_MSK    (((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS)
+#define AON_ACOMP0_NEG_SEL_UMSK   (~(((1U << AON_ACOMP0_NEG_SEL_LEN) - 1) << AON_ACOMP0_NEG_SEL_POS))
+#define AON_ACOMP0_POS_SEL        AON_ACOMP0_POS_SEL
+#define AON_ACOMP0_POS_SEL_POS    (22U)
+#define AON_ACOMP0_POS_SEL_LEN    (4U)
+#define AON_ACOMP0_POS_SEL_MSK    (((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS)
+#define AON_ACOMP0_POS_SEL_UMSK   (~(((1U << AON_ACOMP0_POS_SEL_LEN) - 1) << AON_ACOMP0_POS_SEL_POS))
+#define AON_ACOMP0_MUXEN          AON_ACOMP0_MUXEN
+#define AON_ACOMP0_MUXEN_POS      (26U)
+#define AON_ACOMP0_MUXEN_LEN      (1U)
+#define AON_ACOMP0_MUXEN_MSK      (((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS)
+#define AON_ACOMP0_MUXEN_UMSK     (~(((1U << AON_ACOMP0_MUXEN_LEN) - 1) << AON_ACOMP0_MUXEN_POS))
+
+/* 0x904 : acomp1_ctrl */
+#define AON_ACOMP1_CTRL_OFFSET    (0x904)
+#define AON_ACOMP1_EN             AON_ACOMP1_EN
+#define AON_ACOMP1_EN_POS         (0U)
+#define AON_ACOMP1_EN_LEN         (1U)
+#define AON_ACOMP1_EN_MSK         (((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS)
+#define AON_ACOMP1_EN_UMSK        (~(((1U << AON_ACOMP1_EN_LEN) - 1) << AON_ACOMP1_EN_POS))
+#define AON_ACOMP1_HYST_SELN      AON_ACOMP1_HYST_SELN
+#define AON_ACOMP1_HYST_SELN_POS  (4U)
+#define AON_ACOMP1_HYST_SELN_LEN  (3U)
+#define AON_ACOMP1_HYST_SELN_MSK  (((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS)
+#define AON_ACOMP1_HYST_SELN_UMSK (~(((1U << AON_ACOMP1_HYST_SELN_LEN) - 1) << AON_ACOMP1_HYST_SELN_POS))
+#define AON_ACOMP1_HYST_SELP      AON_ACOMP1_HYST_SELP
+#define AON_ACOMP1_HYST_SELP_POS  (7U)
+#define AON_ACOMP1_HYST_SELP_LEN  (3U)
+#define AON_ACOMP1_HYST_SELP_MSK  (((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS)
+#define AON_ACOMP1_HYST_SELP_UMSK (~(((1U << AON_ACOMP1_HYST_SELP_LEN) - 1) << AON_ACOMP1_HYST_SELP_POS))
+#define AON_ACOMP1_BIAS_PROG      AON_ACOMP1_BIAS_PROG
+#define AON_ACOMP1_BIAS_PROG_POS  (10U)
+#define AON_ACOMP1_BIAS_PROG_LEN  (2U)
+#define AON_ACOMP1_BIAS_PROG_MSK  (((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS)
+#define AON_ACOMP1_BIAS_PROG_UMSK (~(((1U << AON_ACOMP1_BIAS_PROG_LEN) - 1) << AON_ACOMP1_BIAS_PROG_POS))
+#define AON_ACOMP1_LEVEL_SEL      AON_ACOMP1_LEVEL_SEL
+#define AON_ACOMP1_LEVEL_SEL_POS  (12U)
+#define AON_ACOMP1_LEVEL_SEL_LEN  (6U)
+#define AON_ACOMP1_LEVEL_SEL_MSK  (((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS)
+#define AON_ACOMP1_LEVEL_SEL_UMSK (~(((1U << AON_ACOMP1_LEVEL_SEL_LEN) - 1) << AON_ACOMP1_LEVEL_SEL_POS))
+#define AON_ACOMP1_NEG_SEL        AON_ACOMP1_NEG_SEL
+#define AON_ACOMP1_NEG_SEL_POS    (18U)
+#define AON_ACOMP1_NEG_SEL_LEN    (4U)
+#define AON_ACOMP1_NEG_SEL_MSK    (((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS)
+#define AON_ACOMP1_NEG_SEL_UMSK   (~(((1U << AON_ACOMP1_NEG_SEL_LEN) - 1) << AON_ACOMP1_NEG_SEL_POS))
+#define AON_ACOMP1_POS_SEL        AON_ACOMP1_POS_SEL
+#define AON_ACOMP1_POS_SEL_POS    (22U)
+#define AON_ACOMP1_POS_SEL_LEN    (4U)
+#define AON_ACOMP1_POS_SEL_MSK    (((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS)
+#define AON_ACOMP1_POS_SEL_UMSK   (~(((1U << AON_ACOMP1_POS_SEL_LEN) - 1) << AON_ACOMP1_POS_SEL_POS))
+#define AON_ACOMP1_MUXEN          AON_ACOMP1_MUXEN
+#define AON_ACOMP1_MUXEN_POS      (26U)
+#define AON_ACOMP1_MUXEN_LEN      (1U)
+#define AON_ACOMP1_MUXEN_MSK      (((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS)
+#define AON_ACOMP1_MUXEN_UMSK     (~(((1U << AON_ACOMP1_MUXEN_LEN) - 1) << AON_ACOMP1_MUXEN_POS))
+
+/* 0x908 : acomp_ctrl */
+#define AON_ACOMP_CTRL_OFFSET    (0x908)
+#define AON_ACOMP1_RSTN_ANA      AON_ACOMP1_RSTN_ANA
+#define AON_ACOMP1_RSTN_ANA_POS  (0U)
+#define AON_ACOMP1_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP1_RSTN_ANA_MSK  (((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS)
+#define AON_ACOMP1_RSTN_ANA_UMSK (~(((1U << AON_ACOMP1_RSTN_ANA_LEN) - 1) << AON_ACOMP1_RSTN_ANA_POS))
+#define AON_ACOMP0_RSTN_ANA      AON_ACOMP0_RSTN_ANA
+#define AON_ACOMP0_RSTN_ANA_POS  (1U)
+#define AON_ACOMP0_RSTN_ANA_LEN  (1U)
+#define AON_ACOMP0_RSTN_ANA_MSK  (((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS)
+#define AON_ACOMP0_RSTN_ANA_UMSK (~(((1U << AON_ACOMP0_RSTN_ANA_LEN) - 1) << AON_ACOMP0_RSTN_ANA_POS))
+#define AON_ACOMP1_TEST_EN       AON_ACOMP1_TEST_EN
+#define AON_ACOMP1_TEST_EN_POS   (8U)
+#define AON_ACOMP1_TEST_EN_LEN   (1U)
+#define AON_ACOMP1_TEST_EN_MSK   (((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS)
+#define AON_ACOMP1_TEST_EN_UMSK  (~(((1U << AON_ACOMP1_TEST_EN_LEN) - 1) << AON_ACOMP1_TEST_EN_POS))
+#define AON_ACOMP0_TEST_EN       AON_ACOMP0_TEST_EN
+#define AON_ACOMP0_TEST_EN_POS   (9U)
+#define AON_ACOMP0_TEST_EN_LEN   (1U)
+#define AON_ACOMP0_TEST_EN_MSK   (((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS)
+#define AON_ACOMP0_TEST_EN_UMSK  (~(((1U << AON_ACOMP0_TEST_EN_LEN) - 1) << AON_ACOMP0_TEST_EN_POS))
+#define AON_ACOMP1_TEST_SEL      AON_ACOMP1_TEST_SEL
+#define AON_ACOMP1_TEST_SEL_POS  (10U)
+#define AON_ACOMP1_TEST_SEL_LEN  (2U)
+#define AON_ACOMP1_TEST_SEL_MSK  (((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS)
+#define AON_ACOMP1_TEST_SEL_UMSK (~(((1U << AON_ACOMP1_TEST_SEL_LEN) - 1) << AON_ACOMP1_TEST_SEL_POS))
+#define AON_ACOMP0_TEST_SEL      AON_ACOMP0_TEST_SEL
+#define AON_ACOMP0_TEST_SEL_POS  (12U)
+#define AON_ACOMP0_TEST_SEL_LEN  (2U)
+#define AON_ACOMP0_TEST_SEL_MSK  (((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS)
+#define AON_ACOMP0_TEST_SEL_UMSK (~(((1U << AON_ACOMP0_TEST_SEL_LEN) - 1) << AON_ACOMP0_TEST_SEL_POS))
+#define AON_ACOMP1_OUT_RAW       AON_ACOMP1_OUT_RAW
+#define AON_ACOMP1_OUT_RAW_POS   (17U)
+#define AON_ACOMP1_OUT_RAW_LEN   (1U)
+#define AON_ACOMP1_OUT_RAW_MSK   (((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS)
+#define AON_ACOMP1_OUT_RAW_UMSK  (~(((1U << AON_ACOMP1_OUT_RAW_LEN) - 1) << AON_ACOMP1_OUT_RAW_POS))
+#define AON_ACOMP0_OUT_RAW       AON_ACOMP0_OUT_RAW
+#define AON_ACOMP0_OUT_RAW_POS   (19U)
+#define AON_ACOMP0_OUT_RAW_LEN   (1U)
+#define AON_ACOMP0_OUT_RAW_MSK   (((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS)
+#define AON_ACOMP0_OUT_RAW_UMSK  (~(((1U << AON_ACOMP0_OUT_RAW_LEN) - 1) << AON_ACOMP0_OUT_RAW_POS))
+#define AON_ACOMP_RESERVED       AON_ACOMP_RESERVED
+#define AON_ACOMP_RESERVED_POS   (24U)
+#define AON_ACOMP_RESERVED_LEN   (8U)
+#define AON_ACOMP_RESERVED_MSK   (((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS)
+#define AON_ACOMP_RESERVED_UMSK  (~(((1U << AON_ACOMP_RESERVED_LEN) - 1) << AON_ACOMP_RESERVED_POS))
+
+/* 0x90C : gpadc_reg_cmd */
+#define AON_GPADC_REG_CMD_OFFSET        (0x90C)
+#define AON_GPADC_GLOBAL_EN             AON_GPADC_GLOBAL_EN
+#define AON_GPADC_GLOBAL_EN_POS         (0U)
+#define AON_GPADC_GLOBAL_EN_LEN         (1U)
+#define AON_GPADC_GLOBAL_EN_MSK         (((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS)
+#define AON_GPADC_GLOBAL_EN_UMSK        (~(((1U << AON_GPADC_GLOBAL_EN_LEN) - 1) << AON_GPADC_GLOBAL_EN_POS))
+#define AON_GPADC_CONV_START            AON_GPADC_CONV_START
+#define AON_GPADC_CONV_START_POS        (1U)
+#define AON_GPADC_CONV_START_LEN        (1U)
+#define AON_GPADC_CONV_START_MSK        (((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS)
+#define AON_GPADC_CONV_START_UMSK       (~(((1U << AON_GPADC_CONV_START_LEN) - 1) << AON_GPADC_CONV_START_POS))
+#define AON_GPADC_SOFT_RST              AON_GPADC_SOFT_RST
+#define AON_GPADC_SOFT_RST_POS          (2U)
+#define AON_GPADC_SOFT_RST_LEN          (1U)
+#define AON_GPADC_SOFT_RST_MSK          (((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS)
+#define AON_GPADC_SOFT_RST_UMSK         (~(((1U << AON_GPADC_SOFT_RST_LEN) - 1) << AON_GPADC_SOFT_RST_POS))
+#define AON_GPADC_NEG_SEL               AON_GPADC_NEG_SEL
+#define AON_GPADC_NEG_SEL_POS           (3U)
+#define AON_GPADC_NEG_SEL_LEN           (5U)
+#define AON_GPADC_NEG_SEL_MSK           (((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS)
+#define AON_GPADC_NEG_SEL_UMSK          (~(((1U << AON_GPADC_NEG_SEL_LEN) - 1) << AON_GPADC_NEG_SEL_POS))
+#define AON_GPADC_POS_SEL               AON_GPADC_POS_SEL
+#define AON_GPADC_POS_SEL_POS           (8U)
+#define AON_GPADC_POS_SEL_LEN           (5U)
+#define AON_GPADC_POS_SEL_MSK           (((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS)
+#define AON_GPADC_POS_SEL_UMSK          (~(((1U << AON_GPADC_POS_SEL_LEN) - 1) << AON_GPADC_POS_SEL_POS))
+#define AON_GPADC_NEG_GND               AON_GPADC_NEG_GND
+#define AON_GPADC_NEG_GND_POS           (13U)
+#define AON_GPADC_NEG_GND_LEN           (1U)
+#define AON_GPADC_NEG_GND_MSK           (((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS)
+#define AON_GPADC_NEG_GND_UMSK          (~(((1U << AON_GPADC_NEG_GND_LEN) - 1) << AON_GPADC_NEG_GND_POS))
+#define AON_GPADC_MICBIAS_EN            AON_GPADC_MICBIAS_EN
+#define AON_GPADC_MICBIAS_EN_POS        (14U)
+#define AON_GPADC_MICBIAS_EN_LEN        (1U)
+#define AON_GPADC_MICBIAS_EN_MSK        (((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS)
+#define AON_GPADC_MICBIAS_EN_UMSK       (~(((1U << AON_GPADC_MICBIAS_EN_LEN) - 1) << AON_GPADC_MICBIAS_EN_POS))
+#define AON_GPADC_MICPGA_EN             AON_GPADC_MICPGA_EN
+#define AON_GPADC_MICPGA_EN_POS         (15U)
+#define AON_GPADC_MICPGA_EN_LEN         (1U)
+#define AON_GPADC_MICPGA_EN_MSK         (((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS)
+#define AON_GPADC_MICPGA_EN_UMSK        (~(((1U << AON_GPADC_MICPGA_EN_LEN) - 1) << AON_GPADC_MICPGA_EN_POS))
+#define AON_GPADC_BYP_MICBOOST          AON_GPADC_BYP_MICBOOST
+#define AON_GPADC_BYP_MICBOOST_POS      (16U)
+#define AON_GPADC_BYP_MICBOOST_LEN      (1U)
+#define AON_GPADC_BYP_MICBOOST_MSK      (((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS)
+#define AON_GPADC_BYP_MICBOOST_UMSK     (~(((1U << AON_GPADC_BYP_MICBOOST_LEN) - 1) << AON_GPADC_BYP_MICBOOST_POS))
+#define AON_GPADC_DWA_EN                AON_GPADC_DWA_EN
+#define AON_GPADC_DWA_EN_POS            (18U)
+#define AON_GPADC_DWA_EN_LEN            (1U)
+#define AON_GPADC_DWA_EN_MSK            (((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS)
+#define AON_GPADC_DWA_EN_UMSK           (~(((1U << AON_GPADC_DWA_EN_LEN) - 1) << AON_GPADC_DWA_EN_POS))
+#define AON_GPADC_MIC2_DIFF             AON_GPADC_MIC2_DIFF
+#define AON_GPADC_MIC2_DIFF_POS         (19U)
+#define AON_GPADC_MIC2_DIFF_LEN         (1U)
+#define AON_GPADC_MIC2_DIFF_MSK         (((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS)
+#define AON_GPADC_MIC2_DIFF_UMSK        (~(((1U << AON_GPADC_MIC2_DIFF_LEN) - 1) << AON_GPADC_MIC2_DIFF_POS))
+#define AON_GPADC_MIC1_DIFF             AON_GPADC_MIC1_DIFF
+#define AON_GPADC_MIC1_DIFF_POS         (20U)
+#define AON_GPADC_MIC1_DIFF_LEN         (1U)
+#define AON_GPADC_MIC1_DIFF_MSK         (((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS)
+#define AON_GPADC_MIC1_DIFF_UMSK        (~(((1U << AON_GPADC_MIC1_DIFF_LEN) - 1) << AON_GPADC_MIC1_DIFF_POS))
+#define AON_GPADC_MIC_PGA2_GAIN         AON_GPADC_MIC_PGA2_GAIN
+#define AON_GPADC_MIC_PGA2_GAIN_POS     (21U)
+#define AON_GPADC_MIC_PGA2_GAIN_LEN     (2U)
+#define AON_GPADC_MIC_PGA2_GAIN_MSK     (((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS)
+#define AON_GPADC_MIC_PGA2_GAIN_UMSK    (~(((1U << AON_GPADC_MIC_PGA2_GAIN_LEN) - 1) << AON_GPADC_MIC_PGA2_GAIN_POS))
+#define AON_GPADC_MICBOOST_32DB_EN      AON_GPADC_MICBOOST_32DB_EN
+#define AON_GPADC_MICBOOST_32DB_EN_POS  (23U)
+#define AON_GPADC_MICBOOST_32DB_EN_LEN  (1U)
+#define AON_GPADC_MICBOOST_32DB_EN_MSK  (((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS)
+#define AON_GPADC_MICBOOST_32DB_EN_UMSK (~(((1U << AON_GPADC_MICBOOST_32DB_EN_LEN) - 1) << AON_GPADC_MICBOOST_32DB_EN_POS))
+#define AON_GPADC_CHIP_SEN_PU           AON_GPADC_CHIP_SEN_PU
+#define AON_GPADC_CHIP_SEN_PU_POS       (27U)
+#define AON_GPADC_CHIP_SEN_PU_LEN       (1U)
+#define AON_GPADC_CHIP_SEN_PU_MSK       (((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS)
+#define AON_GPADC_CHIP_SEN_PU_UMSK      (~(((1U << AON_GPADC_CHIP_SEN_PU_LEN) - 1) << AON_GPADC_CHIP_SEN_PU_POS))
+#define AON_GPADC_SEN_SEL               AON_GPADC_SEN_SEL
+#define AON_GPADC_SEN_SEL_POS           (28U)
+#define AON_GPADC_SEN_SEL_LEN           (2U)
+#define AON_GPADC_SEN_SEL_MSK           (((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS)
+#define AON_GPADC_SEN_SEL_UMSK          (~(((1U << AON_GPADC_SEN_SEL_LEN) - 1) << AON_GPADC_SEN_SEL_POS))
+#define AON_GPADC_SEN_TEST_EN           AON_GPADC_SEN_TEST_EN
+#define AON_GPADC_SEN_TEST_EN_POS       (30U)
+#define AON_GPADC_SEN_TEST_EN_LEN       (1U)
+#define AON_GPADC_SEN_TEST_EN_MSK       (((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS)
+#define AON_GPADC_SEN_TEST_EN_UMSK      (~(((1U << AON_GPADC_SEN_TEST_EN_LEN) - 1) << AON_GPADC_SEN_TEST_EN_POS))
+
+/* 0x910 : gpadc_reg_config1 */
+#define AON_GPADC_REG_CONFIG1_OFFSET (0x910)
+#define AON_GPADC_CAL_OS_EN          AON_GPADC_CAL_OS_EN
+#define AON_GPADC_CAL_OS_EN_POS      (0U)
+#define AON_GPADC_CAL_OS_EN_LEN      (1U)
+#define AON_GPADC_CAL_OS_EN_MSK      (((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS)
+#define AON_GPADC_CAL_OS_EN_UMSK     (~(((1U << AON_GPADC_CAL_OS_EN_LEN) - 1) << AON_GPADC_CAL_OS_EN_POS))
+#define AON_GPADC_CONT_CONV_EN       AON_GPADC_CONT_CONV_EN
+#define AON_GPADC_CONT_CONV_EN_POS   (1U)
+#define AON_GPADC_CONT_CONV_EN_LEN   (1U)
+#define AON_GPADC_CONT_CONV_EN_MSK   (((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS)
+#define AON_GPADC_CONT_CONV_EN_UMSK  (~(((1U << AON_GPADC_CONT_CONV_EN_LEN) - 1) << AON_GPADC_CONT_CONV_EN_POS))
+#define AON_GPADC_RES_SEL            AON_GPADC_RES_SEL
+#define AON_GPADC_RES_SEL_POS        (2U)
+#define AON_GPADC_RES_SEL_LEN        (3U)
+#define AON_GPADC_RES_SEL_MSK        (((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS)
+#define AON_GPADC_RES_SEL_UMSK       (~(((1U << AON_GPADC_RES_SEL_LEN) - 1) << AON_GPADC_RES_SEL_POS))
+#define AON_GPADC_VCM_SEL_EN         AON_GPADC_VCM_SEL_EN
+#define AON_GPADC_VCM_SEL_EN_POS     (8U)
+#define AON_GPADC_VCM_SEL_EN_LEN     (1U)
+#define AON_GPADC_VCM_SEL_EN_MSK     (((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS)
+#define AON_GPADC_VCM_SEL_EN_UMSK    (~(((1U << AON_GPADC_VCM_SEL_EN_LEN) - 1) << AON_GPADC_VCM_SEL_EN_POS))
+#define AON_GPADC_VCM_HYST_SEL       AON_GPADC_VCM_HYST_SEL
+#define AON_GPADC_VCM_HYST_SEL_POS   (9U)
+#define AON_GPADC_VCM_HYST_SEL_LEN   (1U)
+#define AON_GPADC_VCM_HYST_SEL_MSK   (((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS)
+#define AON_GPADC_VCM_HYST_SEL_UMSK  (~(((1U << AON_GPADC_VCM_HYST_SEL_LEN) - 1) << AON_GPADC_VCM_HYST_SEL_POS))
+#define AON_GPADC_LOWV_DET_EN        AON_GPADC_LOWV_DET_EN
+#define AON_GPADC_LOWV_DET_EN_POS    (10U)
+#define AON_GPADC_LOWV_DET_EN_LEN    (1U)
+#define AON_GPADC_LOWV_DET_EN_MSK    (((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS)
+#define AON_GPADC_LOWV_DET_EN_UMSK   (~(((1U << AON_GPADC_LOWV_DET_EN_LEN) - 1) << AON_GPADC_LOWV_DET_EN_POS))
+#define AON_GPADC_CLK_ANA_INV        AON_GPADC_CLK_ANA_INV
+#define AON_GPADC_CLK_ANA_INV_POS    (17U)
+#define AON_GPADC_CLK_ANA_INV_LEN    (1U)
+#define AON_GPADC_CLK_ANA_INV_MSK    (((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS)
+#define AON_GPADC_CLK_ANA_INV_UMSK   (~(((1U << AON_GPADC_CLK_ANA_INV_LEN) - 1) << AON_GPADC_CLK_ANA_INV_POS))
+#define AON_GPADC_CLK_DIV_RATIO      AON_GPADC_CLK_DIV_RATIO
+#define AON_GPADC_CLK_DIV_RATIO_POS  (18U)
+#define AON_GPADC_CLK_DIV_RATIO_LEN  (3U)
+#define AON_GPADC_CLK_DIV_RATIO_MSK  (((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS)
+#define AON_GPADC_CLK_DIV_RATIO_UMSK (~(((1U << AON_GPADC_CLK_DIV_RATIO_LEN) - 1) << AON_GPADC_CLK_DIV_RATIO_POS))
+#define AON_GPADC_SCAN_LENGTH        AON_GPADC_SCAN_LENGTH
+#define AON_GPADC_SCAN_LENGTH_POS    (21U)
+#define AON_GPADC_SCAN_LENGTH_LEN    (4U)
+#define AON_GPADC_SCAN_LENGTH_MSK    (((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS)
+#define AON_GPADC_SCAN_LENGTH_UMSK   (~(((1U << AON_GPADC_SCAN_LENGTH_LEN) - 1) << AON_GPADC_SCAN_LENGTH_POS))
+#define AON_GPADC_SCAN_EN            AON_GPADC_SCAN_EN
+#define AON_GPADC_SCAN_EN_POS        (25U)
+#define AON_GPADC_SCAN_EN_LEN        (1U)
+#define AON_GPADC_SCAN_EN_MSK        (((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS)
+#define AON_GPADC_SCAN_EN_UMSK       (~(((1U << AON_GPADC_SCAN_EN_LEN) - 1) << AON_GPADC_SCAN_EN_POS))
+#define AON_GPADC_DITHER_EN          AON_GPADC_DITHER_EN
+#define AON_GPADC_DITHER_EN_POS      (26U)
+#define AON_GPADC_DITHER_EN_LEN      (1U)
+#define AON_GPADC_DITHER_EN_MSK      (((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS)
+#define AON_GPADC_DITHER_EN_UMSK     (~(((1U << AON_GPADC_DITHER_EN_LEN) - 1) << AON_GPADC_DITHER_EN_POS))
+#define AON_GPADC_V11_SEL            AON_GPADC_V11_SEL
+#define AON_GPADC_V11_SEL_POS        (27U)
+#define AON_GPADC_V11_SEL_LEN        (2U)
+#define AON_GPADC_V11_SEL_MSK        (((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS)
+#define AON_GPADC_V11_SEL_UMSK       (~(((1U << AON_GPADC_V11_SEL_LEN) - 1) << AON_GPADC_V11_SEL_POS))
+#define AON_GPADC_V18_SEL            AON_GPADC_V18_SEL
+#define AON_GPADC_V18_SEL_POS        (29U)
+#define AON_GPADC_V18_SEL_LEN        (2U)
+#define AON_GPADC_V18_SEL_MSK        (((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS)
+#define AON_GPADC_V18_SEL_UMSK       (~(((1U << AON_GPADC_V18_SEL_LEN) - 1) << AON_GPADC_V18_SEL_POS))
+
+/* 0x914 : gpadc_reg_config2 */
+#define AON_GPADC_REG_CONFIG2_OFFSET (0x914)
+#define AON_GPADC_DIFF_MODE          AON_GPADC_DIFF_MODE
+#define AON_GPADC_DIFF_MODE_POS      (2U)
+#define AON_GPADC_DIFF_MODE_LEN      (1U)
+#define AON_GPADC_DIFF_MODE_MSK      (((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS)
+#define AON_GPADC_DIFF_MODE_UMSK     (~(((1U << AON_GPADC_DIFF_MODE_LEN) - 1) << AON_GPADC_DIFF_MODE_POS))
+#define AON_GPADC_VREF_SEL           AON_GPADC_VREF_SEL
+#define AON_GPADC_VREF_SEL_POS       (3U)
+#define AON_GPADC_VREF_SEL_LEN       (1U)
+#define AON_GPADC_VREF_SEL_MSK       (((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS)
+#define AON_GPADC_VREF_SEL_UMSK      (~(((1U << AON_GPADC_VREF_SEL_LEN) - 1) << AON_GPADC_VREF_SEL_POS))
+#define AON_GPADC_VBAT_EN            AON_GPADC_VBAT_EN
+#define AON_GPADC_VBAT_EN_POS        (4U)
+#define AON_GPADC_VBAT_EN_LEN        (1U)
+#define AON_GPADC_VBAT_EN_MSK        (((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS)
+#define AON_GPADC_VBAT_EN_UMSK       (~(((1U << AON_GPADC_VBAT_EN_LEN) - 1) << AON_GPADC_VBAT_EN_POS))
+#define AON_GPADC_TSEXT_SEL          AON_GPADC_TSEXT_SEL
+#define AON_GPADC_TSEXT_SEL_POS      (5U)
+#define AON_GPADC_TSEXT_SEL_LEN      (1U)
+#define AON_GPADC_TSEXT_SEL_MSK      (((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS)
+#define AON_GPADC_TSEXT_SEL_UMSK     (~(((1U << AON_GPADC_TSEXT_SEL_LEN) - 1) << AON_GPADC_TSEXT_SEL_POS))
+#define AON_GPADC_TS_EN              AON_GPADC_TS_EN
+#define AON_GPADC_TS_EN_POS          (6U)
+#define AON_GPADC_TS_EN_LEN          (1U)
+#define AON_GPADC_TS_EN_MSK          (((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS)
+#define AON_GPADC_TS_EN_UMSK         (~(((1U << AON_GPADC_TS_EN_LEN) - 1) << AON_GPADC_TS_EN_POS))
+#define AON_GPADC_PGA_VCM            AON_GPADC_PGA_VCM
+#define AON_GPADC_PGA_VCM_POS        (7U)
+#define AON_GPADC_PGA_VCM_LEN        (2U)
+#define AON_GPADC_PGA_VCM_MSK        (((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS)
+#define AON_GPADC_PGA_VCM_UMSK       (~(((1U << AON_GPADC_PGA_VCM_LEN) - 1) << AON_GPADC_PGA_VCM_POS))
+#define AON_GPADC_PGA_OS_CAL         AON_GPADC_PGA_OS_CAL
+#define AON_GPADC_PGA_OS_CAL_POS     (9U)
+#define AON_GPADC_PGA_OS_CAL_LEN     (4U)
+#define AON_GPADC_PGA_OS_CAL_MSK     (((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS)
+#define AON_GPADC_PGA_OS_CAL_UMSK    (~(((1U << AON_GPADC_PGA_OS_CAL_LEN) - 1) << AON_GPADC_PGA_OS_CAL_POS))
+#define AON_GPADC_PGA_EN             AON_GPADC_PGA_EN
+#define AON_GPADC_PGA_EN_POS         (13U)
+#define AON_GPADC_PGA_EN_LEN         (1U)
+#define AON_GPADC_PGA_EN_MSK         (((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS)
+#define AON_GPADC_PGA_EN_UMSK        (~(((1U << AON_GPADC_PGA_EN_LEN) - 1) << AON_GPADC_PGA_EN_POS))
+#define AON_GPADC_PGA_VCMI_EN        AON_GPADC_PGA_VCMI_EN
+#define AON_GPADC_PGA_VCMI_EN_POS    (14U)
+#define AON_GPADC_PGA_VCMI_EN_LEN    (1U)
+#define AON_GPADC_PGA_VCMI_EN_MSK    (((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS)
+#define AON_GPADC_PGA_VCMI_EN_UMSK   (~(((1U << AON_GPADC_PGA_VCMI_EN_LEN) - 1) << AON_GPADC_PGA_VCMI_EN_POS))
+#define AON_GPADC_CHOP_MODE          AON_GPADC_CHOP_MODE
+#define AON_GPADC_CHOP_MODE_POS      (15U)
+#define AON_GPADC_CHOP_MODE_LEN      (2U)
+#define AON_GPADC_CHOP_MODE_MSK      (((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS)
+#define AON_GPADC_CHOP_MODE_UMSK     (~(((1U << AON_GPADC_CHOP_MODE_LEN) - 1) << AON_GPADC_CHOP_MODE_POS))
+#define AON_GPADC_BIAS_SEL           AON_GPADC_BIAS_SEL
+#define AON_GPADC_BIAS_SEL_POS       (17U)
+#define AON_GPADC_BIAS_SEL_LEN       (1U)
+#define AON_GPADC_BIAS_SEL_MSK       (((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS)
+#define AON_GPADC_BIAS_SEL_UMSK      (~(((1U << AON_GPADC_BIAS_SEL_LEN) - 1) << AON_GPADC_BIAS_SEL_POS))
+#define AON_GPADC_TEST_EN            AON_GPADC_TEST_EN
+#define AON_GPADC_TEST_EN_POS        (18U)
+#define AON_GPADC_TEST_EN_LEN        (1U)
+#define AON_GPADC_TEST_EN_MSK        (((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS)
+#define AON_GPADC_TEST_EN_UMSK       (~(((1U << AON_GPADC_TEST_EN_LEN) - 1) << AON_GPADC_TEST_EN_POS))
+#define AON_GPADC_TEST_SEL           AON_GPADC_TEST_SEL
+#define AON_GPADC_TEST_SEL_POS       (19U)
+#define AON_GPADC_TEST_SEL_LEN       (3U)
+#define AON_GPADC_TEST_SEL_MSK       (((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS)
+#define AON_GPADC_TEST_SEL_UMSK      (~(((1U << AON_GPADC_TEST_SEL_LEN) - 1) << AON_GPADC_TEST_SEL_POS))
+#define AON_GPADC_PGA2_GAIN          AON_GPADC_PGA2_GAIN
+#define AON_GPADC_PGA2_GAIN_POS      (22U)
+#define AON_GPADC_PGA2_GAIN_LEN      (3U)
+#define AON_GPADC_PGA2_GAIN_MSK      (((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS)
+#define AON_GPADC_PGA2_GAIN_UMSK     (~(((1U << AON_GPADC_PGA2_GAIN_LEN) - 1) << AON_GPADC_PGA2_GAIN_POS))
+#define AON_GPADC_PGA1_GAIN          AON_GPADC_PGA1_GAIN
+#define AON_GPADC_PGA1_GAIN_POS      (25U)
+#define AON_GPADC_PGA1_GAIN_LEN      (3U)
+#define AON_GPADC_PGA1_GAIN_MSK      (((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS)
+#define AON_GPADC_PGA1_GAIN_UMSK     (~(((1U << AON_GPADC_PGA1_GAIN_LEN) - 1) << AON_GPADC_PGA1_GAIN_POS))
+#define AON_GPADC_DLY_SEL            AON_GPADC_DLY_SEL
+#define AON_GPADC_DLY_SEL_POS        (28U)
+#define AON_GPADC_DLY_SEL_LEN        (3U)
+#define AON_GPADC_DLY_SEL_MSK        (((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS)
+#define AON_GPADC_DLY_SEL_UMSK       (~(((1U << AON_GPADC_DLY_SEL_LEN) - 1) << AON_GPADC_DLY_SEL_POS))
+#define AON_GPADC_TSVBE_LOW          AON_GPADC_TSVBE_LOW
+#define AON_GPADC_TSVBE_LOW_POS      (31U)
+#define AON_GPADC_TSVBE_LOW_LEN      (1U)
+#define AON_GPADC_TSVBE_LOW_MSK      (((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS)
+#define AON_GPADC_TSVBE_LOW_UMSK     (~(((1U << AON_GPADC_TSVBE_LOW_LEN) - 1) << AON_GPADC_TSVBE_LOW_POS))
+
+/* 0x918 : adc converation sequence 1 */
+#define AON_GPADC_REG_SCN_POS1_OFFSET (0x918)
+#define AON_GPADC_SCAN_POS_0          AON_GPADC_SCAN_POS_0
+#define AON_GPADC_SCAN_POS_0_POS      (0U)
+#define AON_GPADC_SCAN_POS_0_LEN      (5U)
+#define AON_GPADC_SCAN_POS_0_MSK      (((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS)
+#define AON_GPADC_SCAN_POS_0_UMSK     (~(((1U << AON_GPADC_SCAN_POS_0_LEN) - 1) << AON_GPADC_SCAN_POS_0_POS))
+#define AON_GPADC_SCAN_POS_1          AON_GPADC_SCAN_POS_1
+#define AON_GPADC_SCAN_POS_1_POS      (5U)
+#define AON_GPADC_SCAN_POS_1_LEN      (5U)
+#define AON_GPADC_SCAN_POS_1_MSK      (((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS)
+#define AON_GPADC_SCAN_POS_1_UMSK     (~(((1U << AON_GPADC_SCAN_POS_1_LEN) - 1) << AON_GPADC_SCAN_POS_1_POS))
+#define AON_GPADC_SCAN_POS_2          AON_GPADC_SCAN_POS_2
+#define AON_GPADC_SCAN_POS_2_POS      (10U)
+#define AON_GPADC_SCAN_POS_2_LEN      (5U)
+#define AON_GPADC_SCAN_POS_2_MSK      (((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS)
+#define AON_GPADC_SCAN_POS_2_UMSK     (~(((1U << AON_GPADC_SCAN_POS_2_LEN) - 1) << AON_GPADC_SCAN_POS_2_POS))
+#define AON_GPADC_SCAN_POS_3          AON_GPADC_SCAN_POS_3
+#define AON_GPADC_SCAN_POS_3_POS      (15U)
+#define AON_GPADC_SCAN_POS_3_LEN      (5U)
+#define AON_GPADC_SCAN_POS_3_MSK      (((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS)
+#define AON_GPADC_SCAN_POS_3_UMSK     (~(((1U << AON_GPADC_SCAN_POS_3_LEN) - 1) << AON_GPADC_SCAN_POS_3_POS))
+#define AON_GPADC_SCAN_POS_4          AON_GPADC_SCAN_POS_4
+#define AON_GPADC_SCAN_POS_4_POS      (20U)
+#define AON_GPADC_SCAN_POS_4_LEN      (5U)
+#define AON_GPADC_SCAN_POS_4_MSK      (((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS)
+#define AON_GPADC_SCAN_POS_4_UMSK     (~(((1U << AON_GPADC_SCAN_POS_4_LEN) - 1) << AON_GPADC_SCAN_POS_4_POS))
+#define AON_GPADC_SCAN_POS_5          AON_GPADC_SCAN_POS_5
+#define AON_GPADC_SCAN_POS_5_POS      (25U)
+#define AON_GPADC_SCAN_POS_5_LEN      (5U)
+#define AON_GPADC_SCAN_POS_5_MSK      (((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS)
+#define AON_GPADC_SCAN_POS_5_UMSK     (~(((1U << AON_GPADC_SCAN_POS_5_LEN) - 1) << AON_GPADC_SCAN_POS_5_POS))
+
+/* 0x91C : adc converation sequence 2 */
+#define AON_GPADC_REG_SCN_POS2_OFFSET (0x91C)
+#define AON_GPADC_SCAN_POS_6          AON_GPADC_SCAN_POS_6
+#define AON_GPADC_SCAN_POS_6_POS      (0U)
+#define AON_GPADC_SCAN_POS_6_LEN      (5U)
+#define AON_GPADC_SCAN_POS_6_MSK      (((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS)
+#define AON_GPADC_SCAN_POS_6_UMSK     (~(((1U << AON_GPADC_SCAN_POS_6_LEN) - 1) << AON_GPADC_SCAN_POS_6_POS))
+#define AON_GPADC_SCAN_POS_7          AON_GPADC_SCAN_POS_7
+#define AON_GPADC_SCAN_POS_7_POS      (5U)
+#define AON_GPADC_SCAN_POS_7_LEN      (5U)
+#define AON_GPADC_SCAN_POS_7_MSK      (((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS)
+#define AON_GPADC_SCAN_POS_7_UMSK     (~(((1U << AON_GPADC_SCAN_POS_7_LEN) - 1) << AON_GPADC_SCAN_POS_7_POS))
+#define AON_GPADC_SCAN_POS_8          AON_GPADC_SCAN_POS_8
+#define AON_GPADC_SCAN_POS_8_POS      (10U)
+#define AON_GPADC_SCAN_POS_8_LEN      (5U)
+#define AON_GPADC_SCAN_POS_8_MSK      (((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS)
+#define AON_GPADC_SCAN_POS_8_UMSK     (~(((1U << AON_GPADC_SCAN_POS_8_LEN) - 1) << AON_GPADC_SCAN_POS_8_POS))
+#define AON_GPADC_SCAN_POS_9          AON_GPADC_SCAN_POS_9
+#define AON_GPADC_SCAN_POS_9_POS      (15U)
+#define AON_GPADC_SCAN_POS_9_LEN      (5U)
+#define AON_GPADC_SCAN_POS_9_MSK      (((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS)
+#define AON_GPADC_SCAN_POS_9_UMSK     (~(((1U << AON_GPADC_SCAN_POS_9_LEN) - 1) << AON_GPADC_SCAN_POS_9_POS))
+#define AON_GPADC_SCAN_POS_10         AON_GPADC_SCAN_POS_10
+#define AON_GPADC_SCAN_POS_10_POS     (20U)
+#define AON_GPADC_SCAN_POS_10_LEN     (5U)
+#define AON_GPADC_SCAN_POS_10_MSK     (((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS)
+#define AON_GPADC_SCAN_POS_10_UMSK    (~(((1U << AON_GPADC_SCAN_POS_10_LEN) - 1) << AON_GPADC_SCAN_POS_10_POS))
+#define AON_GPADC_SCAN_POS_11         AON_GPADC_SCAN_POS_11
+#define AON_GPADC_SCAN_POS_11_POS     (25U)
+#define AON_GPADC_SCAN_POS_11_LEN     (5U)
+#define AON_GPADC_SCAN_POS_11_MSK     (((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS)
+#define AON_GPADC_SCAN_POS_11_UMSK    (~(((1U << AON_GPADC_SCAN_POS_11_LEN) - 1) << AON_GPADC_SCAN_POS_11_POS))
+
+/* 0x920 : adc converation sequence 3 */
+#define AON_GPADC_REG_SCN_NEG1_OFFSET (0x920)
+#define AON_GPADC_SCAN_NEG_0          AON_GPADC_SCAN_NEG_0
+#define AON_GPADC_SCAN_NEG_0_POS      (0U)
+#define AON_GPADC_SCAN_NEG_0_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_0_MSK      (((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS)
+#define AON_GPADC_SCAN_NEG_0_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_0_LEN) - 1) << AON_GPADC_SCAN_NEG_0_POS))
+#define AON_GPADC_SCAN_NEG_1          AON_GPADC_SCAN_NEG_1
+#define AON_GPADC_SCAN_NEG_1_POS      (5U)
+#define AON_GPADC_SCAN_NEG_1_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_1_MSK      (((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS)
+#define AON_GPADC_SCAN_NEG_1_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_1_LEN) - 1) << AON_GPADC_SCAN_NEG_1_POS))
+#define AON_GPADC_SCAN_NEG_2          AON_GPADC_SCAN_NEG_2
+#define AON_GPADC_SCAN_NEG_2_POS      (10U)
+#define AON_GPADC_SCAN_NEG_2_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_2_MSK      (((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS)
+#define AON_GPADC_SCAN_NEG_2_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_2_LEN) - 1) << AON_GPADC_SCAN_NEG_2_POS))
+#define AON_GPADC_SCAN_NEG_3          AON_GPADC_SCAN_NEG_3
+#define AON_GPADC_SCAN_NEG_3_POS      (15U)
+#define AON_GPADC_SCAN_NEG_3_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_3_MSK      (((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS)
+#define AON_GPADC_SCAN_NEG_3_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_3_LEN) - 1) << AON_GPADC_SCAN_NEG_3_POS))
+#define AON_GPADC_SCAN_NEG_4          AON_GPADC_SCAN_NEG_4
+#define AON_GPADC_SCAN_NEG_4_POS      (20U)
+#define AON_GPADC_SCAN_NEG_4_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_4_MSK      (((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS)
+#define AON_GPADC_SCAN_NEG_4_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_4_LEN) - 1) << AON_GPADC_SCAN_NEG_4_POS))
+#define AON_GPADC_SCAN_NEG_5          AON_GPADC_SCAN_NEG_5
+#define AON_GPADC_SCAN_NEG_5_POS      (25U)
+#define AON_GPADC_SCAN_NEG_5_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_5_MSK      (((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS)
+#define AON_GPADC_SCAN_NEG_5_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_5_LEN) - 1) << AON_GPADC_SCAN_NEG_5_POS))
+
+/* 0x924 : adc converation sequence 4 */
+#define AON_GPADC_REG_SCN_NEG2_OFFSET (0x924)
+#define AON_GPADC_SCAN_NEG_6          AON_GPADC_SCAN_NEG_6
+#define AON_GPADC_SCAN_NEG_6_POS      (0U)
+#define AON_GPADC_SCAN_NEG_6_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_6_MSK      (((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS)
+#define AON_GPADC_SCAN_NEG_6_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_6_LEN) - 1) << AON_GPADC_SCAN_NEG_6_POS))
+#define AON_GPADC_SCAN_NEG_7          AON_GPADC_SCAN_NEG_7
+#define AON_GPADC_SCAN_NEG_7_POS      (5U)
+#define AON_GPADC_SCAN_NEG_7_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_7_MSK      (((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS)
+#define AON_GPADC_SCAN_NEG_7_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_7_LEN) - 1) << AON_GPADC_SCAN_NEG_7_POS))
+#define AON_GPADC_SCAN_NEG_8          AON_GPADC_SCAN_NEG_8
+#define AON_GPADC_SCAN_NEG_8_POS      (10U)
+#define AON_GPADC_SCAN_NEG_8_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_8_MSK      (((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS)
+#define AON_GPADC_SCAN_NEG_8_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_8_LEN) - 1) << AON_GPADC_SCAN_NEG_8_POS))
+#define AON_GPADC_SCAN_NEG_9          AON_GPADC_SCAN_NEG_9
+#define AON_GPADC_SCAN_NEG_9_POS      (15U)
+#define AON_GPADC_SCAN_NEG_9_LEN      (5U)
+#define AON_GPADC_SCAN_NEG_9_MSK      (((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS)
+#define AON_GPADC_SCAN_NEG_9_UMSK     (~(((1U << AON_GPADC_SCAN_NEG_9_LEN) - 1) << AON_GPADC_SCAN_NEG_9_POS))
+#define AON_GPADC_SCAN_NEG_10         AON_GPADC_SCAN_NEG_10
+#define AON_GPADC_SCAN_NEG_10_POS     (20U)
+#define AON_GPADC_SCAN_NEG_10_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_10_MSK     (((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS)
+#define AON_GPADC_SCAN_NEG_10_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_10_LEN) - 1) << AON_GPADC_SCAN_NEG_10_POS))
+#define AON_GPADC_SCAN_NEG_11         AON_GPADC_SCAN_NEG_11
+#define AON_GPADC_SCAN_NEG_11_POS     (25U)
+#define AON_GPADC_SCAN_NEG_11_LEN     (5U)
+#define AON_GPADC_SCAN_NEG_11_MSK     (((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS)
+#define AON_GPADC_SCAN_NEG_11_UMSK    (~(((1U << AON_GPADC_SCAN_NEG_11_LEN) - 1) << AON_GPADC_SCAN_NEG_11_POS))
+
+/* 0x928 : gpadc_reg_status */
+#define AON_GPADC_REG_STATUS_OFFSET (0x928)
+#define AON_GPADC_DATA_RDY          AON_GPADC_DATA_RDY
+#define AON_GPADC_DATA_RDY_POS      (0U)
+#define AON_GPADC_DATA_RDY_LEN      (1U)
+#define AON_GPADC_DATA_RDY_MSK      (((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS)
+#define AON_GPADC_DATA_RDY_UMSK     (~(((1U << AON_GPADC_DATA_RDY_LEN) - 1) << AON_GPADC_DATA_RDY_POS))
+#define AON_GPADC_RESERVED          AON_GPADC_RESERVED
+#define AON_GPADC_RESERVED_POS      (16U)
+#define AON_GPADC_RESERVED_LEN      (16U)
+#define AON_GPADC_RESERVED_MSK      (((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS)
+#define AON_GPADC_RESERVED_UMSK     (~(((1U << AON_GPADC_RESERVED_LEN) - 1) << AON_GPADC_RESERVED_POS))
+
+/* 0x92C : gpadc_reg_isr */
+#define AON_GPADC_REG_ISR_OFFSET      (0x92C)
+#define AON_GPADC_NEG_SATUR           AON_GPADC_NEG_SATUR
+#define AON_GPADC_NEG_SATUR_POS       (0U)
+#define AON_GPADC_NEG_SATUR_LEN       (1U)
+#define AON_GPADC_NEG_SATUR_MSK       (((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS)
+#define AON_GPADC_NEG_SATUR_UMSK      (~(((1U << AON_GPADC_NEG_SATUR_LEN) - 1) << AON_GPADC_NEG_SATUR_POS))
+#define AON_GPADC_POS_SATUR           AON_GPADC_POS_SATUR
+#define AON_GPADC_POS_SATUR_POS       (1U)
+#define AON_GPADC_POS_SATUR_LEN       (1U)
+#define AON_GPADC_POS_SATUR_MSK       (((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS)
+#define AON_GPADC_POS_SATUR_UMSK      (~(((1U << AON_GPADC_POS_SATUR_LEN) - 1) << AON_GPADC_POS_SATUR_POS))
+#define AON_GPADC_NEG_SATUR_CLR       AON_GPADC_NEG_SATUR_CLR
+#define AON_GPADC_NEG_SATUR_CLR_POS   (4U)
+#define AON_GPADC_NEG_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_NEG_SATUR_CLR_MSK   (((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS)
+#define AON_GPADC_NEG_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_NEG_SATUR_CLR_LEN) - 1) << AON_GPADC_NEG_SATUR_CLR_POS))
+#define AON_GPADC_POS_SATUR_CLR       AON_GPADC_POS_SATUR_CLR
+#define AON_GPADC_POS_SATUR_CLR_POS   (5U)
+#define AON_GPADC_POS_SATUR_CLR_LEN   (1U)
+#define AON_GPADC_POS_SATUR_CLR_MSK   (((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS)
+#define AON_GPADC_POS_SATUR_CLR_UMSK  (~(((1U << AON_GPADC_POS_SATUR_CLR_LEN) - 1) << AON_GPADC_POS_SATUR_CLR_POS))
+#define AON_GPADC_NEG_SATUR_MASK      AON_GPADC_NEG_SATUR_MASK
+#define AON_GPADC_NEG_SATUR_MASK_POS  (8U)
+#define AON_GPADC_NEG_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_NEG_SATUR_MASK_MSK  (((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS)
+#define AON_GPADC_NEG_SATUR_MASK_UMSK (~(((1U << AON_GPADC_NEG_SATUR_MASK_LEN) - 1) << AON_GPADC_NEG_SATUR_MASK_POS))
+#define AON_GPADC_POS_SATUR_MASK      AON_GPADC_POS_SATUR_MASK
+#define AON_GPADC_POS_SATUR_MASK_POS  (9U)
+#define AON_GPADC_POS_SATUR_MASK_LEN  (1U)
+#define AON_GPADC_POS_SATUR_MASK_MSK  (((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS)
+#define AON_GPADC_POS_SATUR_MASK_UMSK (~(((1U << AON_GPADC_POS_SATUR_MASK_LEN) - 1) << AON_GPADC_POS_SATUR_MASK_POS))
+
+/* 0x930 : gpadc_reg_result */
+#define AON_GPADC_REG_RESULT_OFFSET (0x930)
+#define AON_GPADC_DATA_OUT          AON_GPADC_DATA_OUT
+#define AON_GPADC_DATA_OUT_POS      (0U)
+#define AON_GPADC_DATA_OUT_LEN      (26U)
+#define AON_GPADC_DATA_OUT_MSK      (((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS)
+#define AON_GPADC_DATA_OUT_UMSK     (~(((1U << AON_GPADC_DATA_OUT_LEN) - 1) << AON_GPADC_DATA_OUT_POS))
+
+/* 0x934 : gpadc_reg_raw_result */
+#define AON_GPADC_REG_RAW_RESULT_OFFSET (0x934)
+#define AON_GPADC_RAW_DATA              AON_GPADC_RAW_DATA
+#define AON_GPADC_RAW_DATA_POS          (0U)
+#define AON_GPADC_RAW_DATA_LEN          (12U)
+#define AON_GPADC_RAW_DATA_MSK          (((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS)
+#define AON_GPADC_RAW_DATA_UMSK         (~(((1U << AON_GPADC_RAW_DATA_LEN) - 1) << AON_GPADC_RAW_DATA_POS))
+
+/* 0x938 : gpadc_reg_define */
+#define AON_GPADC_REG_DEFINE_OFFSET (0x938)
+#define AON_GPADC_OS_CAL_DATA       AON_GPADC_OS_CAL_DATA
+#define AON_GPADC_OS_CAL_DATA_POS   (0U)
+#define AON_GPADC_OS_CAL_DATA_LEN   (16U)
+#define AON_GPADC_OS_CAL_DATA_MSK   (((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS)
+#define AON_GPADC_OS_CAL_DATA_UMSK  (~(((1U << AON_GPADC_OS_CAL_DATA_LEN) - 1) << AON_GPADC_OS_CAL_DATA_POS))
+
+/* 0x93C : hbncore_resv0 */
+#define AON_HBNCORE_RESV0_OFFSET    (0x93C)
+#define AON_HBNCORE_RESV0_DATA      AON_HBNCORE_RESV0_DATA
+#define AON_HBNCORE_RESV0_DATA_POS  (0U)
+#define AON_HBNCORE_RESV0_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV0_DATA_MSK  (((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS)
+#define AON_HBNCORE_RESV0_DATA_UMSK (~(((1U << AON_HBNCORE_RESV0_DATA_LEN) - 1) << AON_HBNCORE_RESV0_DATA_POS))
+
+/* 0x940 : hbncore_resv1 */
+#define AON_HBNCORE_RESV1_OFFSET    (0x940)
+#define AON_HBNCORE_RESV1_DATA      AON_HBNCORE_RESV1_DATA
+#define AON_HBNCORE_RESV1_DATA_POS  (0U)
+#define AON_HBNCORE_RESV1_DATA_LEN  (32U)
+#define AON_HBNCORE_RESV1_DATA_MSK  (((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS)
+#define AON_HBNCORE_RESV1_DATA_UMSK (~(((1U << AON_HBNCORE_RESV1_DATA_LEN) - 1) << AON_HBNCORE_RESV1_DATA_POS))
+
+struct aon_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[2048];
+
+    /* 0x800 : aon */
+    union {
+        struct
+        {
+            uint32_t aon_resv              : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t pu_aon_dc_tbuf        : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_19        : 7; /* [19:13],       rsvd,        0x0 */
+            uint32_t ldo11_rt_pulldown     : 1; /* [   20],        r/w,        0x0 */
+            uint32_t ldo11_rt_pulldown_sel : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sw_pu_ldo11_rt        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t reserved_23_31        : 9; /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon;
+
+    /* 0x804 : aon_common */
+    union {
+        struct
+        {
+            uint32_t tmux_aon         : 3;  /* [ 2: 0],        r/w,        0x0 */
+            uint32_t reserved_3       : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t ten_aon          : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t dten_xtal32k     : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t ten_xtal32k      : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7       : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t ten_vddcore_aon  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t ten_ldo11soc_aon : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t ten_dcdc18_0_aon : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ten_dcdc18_1_aon : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t ten_bg_sys_aon   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15   : 3;  /* [15:13],       rsvd,        0x0 */
+            uint32_t ten_ldo15rf_aon  : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t ten_xtal_aon     : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t dten_xtal_aon    : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t ten_mbg_aon      : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t ten_cip_misc_aon : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31   : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_common;
+
+    /* 0x808 : aon_misc */
+    union {
+        struct
+        {
+            uint32_t sw_soc_en_aon : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t sw_bz_en_aon  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_31 : 30; /* [31: 2],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } aon_misc;
+
+    /* 0x80c  reserved */
+    uint8_t RESERVED0x80c[4];
+
+    /* 0x810 : bg_sys_top */
+    union {
+        struct
+        {
+            uint32_t pmip_resv             : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t pu_bg_sys_aon         : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_11         : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t bg_sys_start_ctrl_aon : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t reserved_13_31        : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bg_sys_top;
+
+    /* 0x814 : dcdc18_top_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0                : 1; /* [    0],       rsvd,        0x0 */
+            uint32_t dcdc18_vout_sel_aon       : 5; /* [ 5: 1],        r/w,       0x1b */
+            uint32_t reserved_6_7              : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t dcdc18_vpfm_aon           : 4; /* [11: 8],        r/w,        0x7 */
+            uint32_t dcdc18_osc_2m_mode_aon    : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15            : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc18_osc_freq_trim_aon  : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc18_slope_curr_sel_aon : 5; /* [24:20],        r/w,        0x5 */
+            uint32_t dcdc18_stop_osc_aon       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t dcdc18_slow_osc_aon       : 1; /* [   26],        r/w,        0x0 */
+            uint32_t dcdc18_osc_inhibit_t2_aon : 1; /* [   27],        r/w,        0x1 */
+            uint32_t dcdc18_sstart_time_aon    : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t reserved_30               : 1; /* [   30],       rsvd,        0x0 */
+            uint32_t dcdc18_rdy_aon            : 1; /* [   31],          r,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } dcdc18_top_0;
+
+    /* 0x818 : dcdc18_top_1 */
+    union {
+        struct
+        {
+            uint32_t dcdc18_force_cs_zvs_aon  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t dcdc18_cs_delay_aon      : 3; /* [ 3: 1],        r/w,        0x4 */
+            uint32_t dcdc18_zvs_td_opt_aon    : 3; /* [ 6: 4],        r/w,        0x4 */
+            uint32_t reserved_7               : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t dcdc18_nonoverlap_td_aon : 5; /* [12: 8],        r/w,        0x0 */
+            uint32_t reserved_13_15           : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t dcdc18_rc_sel_aon        : 4; /* [19:16],        r/w,        0x8 */
+            uint32_t dcdc18_chf_sel_aon       : 4; /* [23:20],        r/w,        0x1 */
+            uint32_t dcdc18_cfb_sel_aon       : 4; /* [27:24],        r/w,        0x8 */
+            uint32_t dcdc18_en_antiring_aon   : 1; /* [   28],        r/w,        0x1 */
+            uint32_t dcdc18_pulldown_aon      : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31           : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dcdc18_top_1;
+
+    /* 0x81C : ldo11soc_and_dctest */
+    union {
+        struct
+        {
+            uint32_t pu_ldo11soc_aon           : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3              : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t ldo11soc_sstart_sel_aon   : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_7              : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t ldo11soc_sstart_delay_aon : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_aon     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ldo11soc_pulldown_sel_aon : 1;  /* [   11],        r/w,        0x1 */
+            uint32_t ldo11soc_vth_sel_aon      : 2;  /* [13:12],        r/w,        0x1 */
+            uint32_t reserved_14_23            : 10; /* [23:14],       rsvd,        0x0 */
+            uint32_t ldo11soc_cc_aon           : 2;  /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27            : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t ldo11soc_rdy_aon          : 1;  /* [   28],          r,        0x1 */
+            uint32_t ldo11soc_power_good_aon   : 1;  /* [   29],          r,        0x1 */
+            uint32_t pu_vddcore_misc_aon       : 1;  /* [   30],        r/w,        0x1 */
+            uint32_t pmip_dc_tp_out_en_aon     : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ldo11soc_and_dctest;
+
+    /* 0x820 : psw_irrcv */
+    union {
+        struct
+        {
+            uint32_t pu_ir_psw_aon : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } psw_irrcv;
+
+    /* 0x824  reserved */
+    uint8_t RESERVED0x824[92];
+
+    /* 0x880 : rf_top_aon */
+    union {
+        struct
+        {
+            uint32_t pu_mbg_aon               : 1; /* [    0],        r/w,        0x1 */
+            uint32_t pu_ldo15rf_aon           : 1; /* [    1],        r/w,        0x1 */
+            uint32_t pu_sfreg_aon             : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3               : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t pu_xtal_buf_aon          : 1; /* [    4],        r/w,        0x1 */
+            uint32_t pu_xtal_aon              : 1; /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7             : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t ldo15rf_sstart_sel_aon   : 1; /* [    8],        r/w,        0x1 */
+            uint32_t ldo15rf_sstart_delay_aon : 2; /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t ldo15rf_pulldown_aon     : 1; /* [   12],        r/w,        0x0 */
+            uint32_t ldo15rf_pulldown_sel_aon : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t ldo15rf_vout_sel_aon     : 3; /* [18:16],        r/w,        0x2 */
+            uint32_t reserved_19_23           : 5; /* [23:19],       rsvd,        0x0 */
+            uint32_t ldo15rf_cc_aon           : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27           : 2; /* [27:26],       rsvd,        0x0 */
+            uint32_t ldo15rf_bypass_aon       : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reserved_29_31           : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rf_top_aon;
+
+    /* 0x884 : xtal_cfg */
+    union {
+        struct
+        {
+            uint32_t xtal_bk_aon            : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t xtal_capcode_extra_aon : 1; /* [    2],        r/w,        0x0 */
+            uint32_t xtal_ext_sel_aon       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t xtal_buf_en_aon        : 4; /* [ 7: 4],        r/w,        0xf */
+            uint32_t xtal_buf_hp_aon        : 4; /* [11: 8],        r/w,        0x0 */
+            uint32_t xtal_fast_startup_aon  : 1; /* [   12],        r/w,        0x1 */
+            uint32_t xtal_sleep_aon         : 1; /* [   13],        r/w,        0x1 */
+            uint32_t xtal_amp_ctrl_aon      : 2; /* [15:14],        r/w,        0x3 */
+            uint32_t xtal_capcode_out_aon   : 6; /* [21:16],        r/w,       0x10 */
+            uint32_t xtal_capcode_in_aon    : 6; /* [27:22],        r/w,       0x10 */
+            uint32_t xtal_gm_boost_aon      : 2; /* [29:28],        r/w,        0x3 */
+            uint32_t xtal_rdy_sel_aon       : 2; /* [31:30],        r/w,        0x2 */
+        } BF;
+        uint32_t WORD;
+    } xtal_cfg;
+
+    /* 0x888 : tsen */
+    union {
+        struct
+        {
+            uint32_t tsen_refcode_corner  : 12; /* [11: 0],        r/w,      0x8ff */
+            uint32_t reserved_12_15       : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t tsen_refcode_rfcal   : 12; /* [27:16],        r/w,      0x8ff */
+            uint32_t xtal_rdy             : 1;  /* [   28],          r,        0x1 */
+            uint32_t xtal_inn_cfg_en_aon  : 1;  /* [   29],        r/w,        0x1 */
+            uint32_t xtal_rdy_int_sel_aon : 2;  /* [31:30],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } tsen;
+
+    /* 0x88c  reserved */
+    uint8_t RESERVED0x88c[116];
+
+    /* 0x900 : acomp0_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp0_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp0_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp0_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp0_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp0_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp0_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp0_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp0_ctrl;
+
+    /* 0x904 : acomp1_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp1_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3; /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t acomp1_hyst_seln : 3; /* [ 6: 4],        r/w,        0x0 */
+            uint32_t acomp1_hyst_selp : 3; /* [ 9: 7],        r/w,        0x0 */
+            uint32_t acomp1_bias_prog : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp1_level_sel : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t acomp1_neg_sel   : 4; /* [21:18],        r/w,        0x0 */
+            uint32_t acomp1_pos_sel   : 4; /* [25:22],        r/w,        0x0 */
+            uint32_t acomp1_muxen     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reserved_27_31   : 5; /* [31:27],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp1_ctrl;
+
+    /* 0x908 : acomp_ctrl */
+    union {
+        struct
+        {
+            uint32_t acomp1_rstn_ana : 1; /* [    0],        r/w,        0x1 */
+            uint32_t acomp0_rstn_ana : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_7    : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t acomp1_test_en  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t acomp0_test_en  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t acomp1_test_sel : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t acomp0_test_sel : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t reserved_14_16  : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t acomp1_out_raw  : 1; /* [   17],          r,        0x0 */
+            uint32_t reserved_18     : 1; /* [   18],       rsvd,        0x0 */
+            uint32_t acomp0_out_raw  : 1; /* [   19],          r,        0x0 */
+            uint32_t reserved_20_23  : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t acomp_reserved  : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } acomp_ctrl;
+
+    /* 0x90C : gpadc_reg_cmd */
+    union {
+        struct
+        {
+            uint32_t gpadc_global_en        : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_conv_start       : 1; /* [    1],        r/w,        0x0 */
+            uint32_t gpadc_soft_rst         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_neg_sel          : 5; /* [ 7: 3],        r/w,        0xf */
+            uint32_t gpadc_pos_sel          : 5; /* [12: 8],        r/w,        0xf */
+            uint32_t gpadc_neg_gnd          : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_micbias_en       : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_micpga_en        : 1; /* [   15],        r/w,        0x0 */
+            uint32_t gpadc_byp_micboost     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17            : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t gpadc_dwa_en           : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_mic2_diff        : 1; /* [   19],        r/w,        0x0 */
+            uint32_t gpadc_mic1_diff        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t gpadc_mic_pga2_gain    : 2; /* [22:21],        r/w,        0x0 */
+            uint32_t gpadc_micboost_32db_en : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_26         : 3; /* [26:24],       rsvd,        0x0 */
+            uint32_t gpadc_chip_sen_pu      : 1; /* [   27],        r/w,        0x0 */
+            uint32_t gpadc_sen_sel          : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t gpadc_sen_test_en      : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reserved_31            : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_cmd;
+
+    /* 0x910 : gpadc_reg_config1 */
+    union {
+        struct
+        {
+            uint32_t gpadc_cal_os_en     : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_cont_conv_en  : 1; /* [    1],        r/w,        0x1 */
+            uint32_t gpadc_res_sel       : 3; /* [ 4: 2],        r/w,        0x0 */
+            uint32_t reserved_5_7        : 3; /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t gpadc_vcm_sel_en    : 1; /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_vcm_hyst_sel  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t gpadc_lowv_det_en   : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_16      : 6; /* [16:11],       rsvd,        0x0 */
+            uint32_t gpadc_clk_ana_inv   : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_clk_div_ratio : 3; /* [20:18],        r/w,        0x3 */
+            uint32_t gpadc_scan_length   : 4; /* [24:21],        r/w,        0x0 */
+            uint32_t gpadc_scan_en       : 1; /* [   25],        r/w,        0x0 */
+            uint32_t gpadc_dither_en     : 1; /* [   26],        r/w,        0x0 */
+            uint32_t gpadc_v11_sel       : 2; /* [28:27],        r/w,        0x0 */
+            uint32_t gpadc_v18_sel       : 2; /* [30:29],        r/w,        0x0 */
+            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config1;
+
+    /* 0x914 : gpadc_reg_config2 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1      : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t gpadc_diff_mode   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t gpadc_vref_sel    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t gpadc_vbat_en     : 1; /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_tsext_sel   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t gpadc_ts_en       : 1; /* [    6],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcm     : 2; /* [ 8: 7],        r/w,        0x2 */
+            uint32_t gpadc_pga_os_cal  : 4; /* [12: 9],        r/w,        0x8 */
+            uint32_t gpadc_pga_en      : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_pga_vcmi_en : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_chop_mode   : 2; /* [16:15],        r/w,        0x3 */
+            uint32_t gpadc_bias_sel    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t gpadc_test_en     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t gpadc_test_sel    : 3; /* [21:19],        r/w,        0x0 */
+            uint32_t gpadc_pga2_gain   : 3; /* [24:22],        r/w,        0x0 */
+            uint32_t gpadc_pga1_gain   : 3; /* [27:25],        r/w,        0x0 */
+            uint32_t gpadc_dly_sel     : 3; /* [30:28],        r/w,        0x0 */
+            uint32_t gpadc_tsvbe_low   : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_config2;
+
+    /* 0x918 : adc converation sequence 1 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_pos_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos1;
+
+    /* 0x91C : adc converation sequence 2 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_pos_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_pos_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_pos2;
+
+    /* 0x920 : adc converation sequence 3 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_neg_0 : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_1 : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_2 : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_3 : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_4 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_5 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31   : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg1;
+
+    /* 0x924 : adc converation sequence 4 */
+    union {
+        struct
+        {
+            uint32_t gpadc_scan_neg_6  : 5; /* [ 4: 0],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_7  : 5; /* [ 9: 5],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_8  : 5; /* [14:10],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_9  : 5; /* [19:15],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_10 : 5; /* [24:20],        r/w,        0xf */
+            uint32_t gpadc_scan_neg_11 : 5; /* [29:25],        r/w,        0xf */
+            uint32_t reserved_30_31    : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_scn_neg2;
+
+    /* 0x928 : gpadc_reg_status */
+    union {
+        struct
+        {
+            uint32_t gpadc_data_rdy : 1;  /* [    0],          r,        0x0 */
+            uint32_t reserved_1_15  : 15; /* [15: 1],       rsvd,        0x0 */
+            uint32_t gpadc_reserved : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_status;
+
+    /* 0x92C : gpadc_reg_isr */
+    union {
+        struct
+        {
+            uint32_t gpadc_neg_satur      : 1;  /* [    0],          r,        0x0 */
+            uint32_t gpadc_pos_satur      : 1;  /* [    1],          r,        0x0 */
+            uint32_t reserved_2_3         : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_clr  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_clr  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t gpadc_neg_satur_mask : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_pos_satur_mask : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31       : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_isr;
+
+    /* 0x930 : gpadc_reg_result */
+    union {
+        struct
+        {
+            uint32_t gpadc_data_out : 26; /* [25: 0],          r,  0x1ef0000 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_result;
+
+    /* 0x934 : gpadc_reg_raw_result */
+    union {
+        struct
+        {
+            uint32_t gpadc_raw_data : 12; /* [11: 0],          r,        0x0 */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_raw_result;
+
+    /* 0x938 : gpadc_reg_define */
+    union {
+        struct
+        {
+            uint32_t gpadc_os_cal_data : 16; /* [15: 0],        r/w,        0x0 */
+            uint32_t reserved_16_31    : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_reg_define;
+
+    /* 0x93C : hbncore_resv0 */
+    union {
+        struct
+        {
+            uint32_t hbncore_resv0_data : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv0;
+
+    /* 0x940 : hbncore_resv1 */
+    union {
+        struct
+        {
+            uint32_t hbncore_resv1_data : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } hbncore_resv1;
+};
+
+typedef volatile struct aon_reg aon_reg_t;
+
+#endif /* __AON_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/bl702.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/bl702.h
new file mode 100755
index 0000000000..993fd69d65
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/bl702.h
@@ -0,0 +1,306 @@
+#ifndef __BL702_H__
+#define __BL702_H__
+
+/* This file had been modified, add USB_IRQn=43 for temp test, the irq value 43 should be checked after all. */
+
+/** @addtogroup Configuration_section_for_RISCV
+  * @{
+  */
+
+/**
+  * @brief Configuration of the Processor and Core Peripherals
+   */
+
+/* fix 57.6M */
+#define SystemCoreClockSet(val)                     \
+    if (val == 57 * 6000 * 1000) {                  \
+        BL_WR_WORD(0x4000F108, 57.6 * 1000 * 1000); \
+    } else {                                        \
+        BL_WR_WORD(0x4000F108, val);                \
+    }
+#define SystemCoreClockGet(val) BL_RD_WORD(0x4000F108)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_interrupt_number_definition
+  * @{
+  */
+
+#ifdef ARCH_ARM
+#define IRQ_NUM_BASE 0
+#endif
+
+#ifdef ARCH_RISCV
+#define IRQ_NUM_BASE 16
+#endif
+/**
+ * @brief BL702 Interrupt Number Definition, according to the selected device
+ *        in @ref Library_configuration_section
+ */
+typedef enum {
+#ifdef ARCH_ARM
+    /******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+    NonMaskableInt_IRQn = -14,   /*!< 2 Cortex-M4 Non Maskable Interrupt                                */
+    HardFault_IRQn = -13,        /*!< 3 Cortex-M4 Hard Fault Interrupt                                  */
+    MemoryManagement_IRQn = -12, /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+    BusFault_IRQn = -11,         /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+    UsageFault_IRQn = -10,       /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+    SVCall_IRQn = -5,            /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+    DebugMonitor_IRQn = -4,      /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+    PendSV_IRQn = -2,            /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+    SysTick_IRQn = -1,           /*!< 15 Cortex-M4 System Tick Interrupt                                */
+#endif
+#ifdef ARCH_RISCV
+    MSOFT_IRQn = 3,           /*!< 3 RISCV machine software Interrupt                                */
+    MTIME_IRQn = 7,           /*!< 7 RISCV machine time Interrupt                                    */
+    MEXT_IRQn = 11,           /*!< 11 RISCV external  Interrupt                                      */
+    CLIC_SOFT_PEND_IRQn = 12, /*!< 12 RISCV CLIC software pending  Interrupt                         */
+#endif
+    /******  BL702 specific Interrupt Numbers **********************************************************************/
+    BMX_ERR_IRQn = IRQ_NUM_BASE + 0,           /*!< BMX Error Interrupt                                               */
+    BMX_TO_IRQn = IRQ_NUM_BASE + 1,            /*!< BMX Timeout Interrupt                                             */
+    L1C_BMX_ERR_IRQn = IRQ_NUM_BASE + 2,       /*!< L1C BMX Error Interrupt                                           */
+    L1C_BMX_TO_IRQn = IRQ_NUM_BASE + 3,        /*!< L1C BMX Timeout Interrupt                                         */
+    SEC_BMX_ERR_IRQn = IRQ_NUM_BASE + 4,       /*!< SEC BMX Error Interrupt                                           */
+    RF_TOP_INT0_IRQn = IRQ_NUM_BASE + 5,       /*!< RF_TOP_INT0 Interrupt                                             */
+    RF_TOP_INT1_IRQn = IRQ_NUM_BASE + 6,       /*!< RF_TOP_INT1 Interrupt                                             */
+    RESERVED0 = IRQ_NUM_BASE + 7,              /*!< RESERVED Interrupt                                                */
+    DMA_BMX_ERR_IRQn = IRQ_NUM_BASE + 8,       /*!< DMA BMX Error Interrupt                                           */
+    SEC_GMAC_IRQn = IRQ_NUM_BASE + 9,          /*!< SEC_ENG_GMAC_INT Interrupt                                        */
+    SEC_CDET_IRQn = IRQ_NUM_BASE + 10,         /*!< SEC_ENG_CDET_INT Interrupt                                        */
+    SEC_PKA_IRQn = IRQ_NUM_BASE + 11,          /*!< SEC_ENG_PKA_INT  Interrupt                                        */
+    SEC_TRNG_IRQn = IRQ_NUM_BASE + 12,         /*!< SEC_ENG_TRNG_INT Interrupt                                        */
+    SEC_AES_IRQn = IRQ_NUM_BASE + 13,          /*!< SEC_ENG_AES_INT  Interrupt                                        */
+    SEC_SHA_IRQn = IRQ_NUM_BASE + 14,          /*!< SEC_ENG_SHA_INT  Interrupt                                        */
+    DMA_ALL_IRQn = IRQ_NUM_BASE + 15,          /*!< DMA ALL Interrupt                                                 */
+    MJPEG_IRQn = IRQ_NUM_BASE + 16,            /*!< MJPEG Interrupt                                                   */
+    CAM_IRQn = IRQ_NUM_BASE + 17,              /*!< CAM Interrupt                                                     */
+    I2S_IRQn = IRQ_NUM_BASE + 18,              /*!< I2S Interrupt                                                     */
+    IRTX_IRQn = IRQ_NUM_BASE + 19,             /*!< IR TX Interrupt                                                   */
+    IRRX_IRQn = IRQ_NUM_BASE + 20,             /*!< IR RX Interrupt                                                   */
+    USB_IRQn = IRQ_NUM_BASE + 21,              /*!< USB Interrupt                                                     */
+    EMAC_IRQn = IRQ_NUM_BASE + 22,             /*!< EMAC  Interrupt                                                   */
+    SF_CTRL_IRQn = IRQ_NUM_BASE + 23,          /*!< SF_CTRL   Interrupt                                               */
+    RESERVED1 = IRQ_NUM_BASE + 24,             /*!< RESERVED  Interrupt                                               */
+    GPADC_DMA_IRQn = IRQ_NUM_BASE + 25,        /*!< GPADC_DMA Interrupt                                               */
+    EFUSE_IRQn = IRQ_NUM_BASE + 26,            /*!< Efuse Interrupt                                                   */
+    SPI_IRQn = IRQ_NUM_BASE + 27,              /*!< SPI   Interrupt                                                   */
+    RESERVED2 = IRQ_NUM_BASE + 28,             /*!< RESERVED Interrupt                                                */
+    UART0_IRQn = IRQ_NUM_BASE + 29,            /*!< UART  Interrupt                                                   */
+    UART1_IRQn = IRQ_NUM_BASE + 30,            /*!< UART1 Interrupt                                                   */
+    RESERVED3 = IRQ_NUM_BASE + 31,             /*!< RESERVED Interrupt                                                */
+    I2C_IRQn = IRQ_NUM_BASE + 32,              /*!< I2C   Interrupt                                                   */
+    RESERVED4 = IRQ_NUM_BASE + 33,             /*!< RESERVED Interrupt                                                */
+    PWM_IRQn = IRQ_NUM_BASE + 34,              /*!< PWM   Interrupt                                                   */
+    RESERVED5 = IRQ_NUM_BASE + 35,             /*!< RESERVED Interrupt                                                */
+    TIMER_CH0_IRQn = IRQ_NUM_BASE + 36,        /*!< Timer Channel 0 Interrupt                                         */
+    TIMER_CH1_IRQn = IRQ_NUM_BASE + 37,        /*!< Timer Channel 1 Interrupt                                         */
+    TIMER_WDT_IRQn = IRQ_NUM_BASE + 38,        /*!< Timer Watch Dog Interrupt                                         */
+    KYS_IRQn = IRQ_NUM_BASE + 39,              /*!< KYS Interrupt                                                     */
+    QDEC0_IRQn = IRQ_NUM_BASE + 40,            /*!< QDEC0 Interrupt                                                   */
+    QDEC1_IRQn = IRQ_NUM_BASE + 41,            /*!< QDEC1 Interrupt                                                   */
+    QDEC2_IRQn = IRQ_NUM_BASE + 42,            /*!< QDEC2 Interrupt                                                   */
+    RESERVED6 = IRQ_NUM_BASE + 43,             /*!< RESERVED Interrupt                                                */
+    GPIO_INT0_IRQn = IRQ_NUM_BASE + 44,        /*!< GPIO_INT0 Interrupt                                               */
+    TOUCH_IRQn = IRQ_NUM_BASE + 45,            /*!< TOUCH Interrupt                                                   */
+    RESERVED7 = IRQ_NUM_BASE + 46,             /*!< RESERVED Interrupt                                                */
+    M154_REQ_ENH_ACK_IRQn = IRQ_NUM_BASE + 47, /*!< M154_REQ Interrupt                                                */
+    M154_IRQn = IRQ_NUM_BASE + 48,             /*!< M154 Interrupt                                                    */
+    M154_AES_IRQn = IRQ_NUM_BASE + 49,         /*!< M154_AES Interrupt                                                */
+    PDS_WAKEUP_IRQn = IRQ_NUM_BASE + 50,       /*!< PDS Wakeup Interrupt                                              */
+    HBN_OUT0_IRQn = IRQ_NUM_BASE + 51,         /*!< Hibernate out 0 Interrupt                                         */
+    HBN_OUT1_IRQn = IRQ_NUM_BASE + 52,         /*!< Hibernate out 1 Interrupt                                         */
+    BOR_IRQn = IRQ_NUM_BASE + 53,              /*!< BOR Interrupt                                                     */
+    WIFI_IRQn = IRQ_NUM_BASE + 54,             /*!< WIFI To CPU Interrupt                                             */
+    BZ_PHY_IRQn = IRQ_NUM_BASE + 55,           /*!< BZ_PHY Interrupt                                                  */
+    BLE_IRQn = IRQ_NUM_BASE + 56,              /*!< BLE Interrupt                                                     */
+    MAC_TXRX_TIMER_IRQn = IRQ_NUM_BASE + 57,   /*!< mac_int_tx_rx_timer Interrupt                                     */
+    MAC_TXRX_MISC_IRQn = IRQ_NUM_BASE + 58,    /*!< mac_int_tx_rx_misc Interrupt                                      */
+    MAC_RX_TRG_IRQn = IRQ_NUM_BASE + 59,       /*!< mac_int_rx_trigger Interrupt                                      */
+    MAC_TX_TRG_IRQn = IRQ_NUM_BASE + 60,       /*!< mac_int_tx_trigger Interrupt                                      */
+    MAC_GEN_IRQn = IRQ_NUM_BASE + 61,          /*!< mac_int_gen Interrupt                                             */
+    MAC_PORT_TRG_IRQn = IRQ_NUM_BASE + 62,     /*!< mac_int_port_trigger Interrupt                                    */
+    WIFI_IPC_PUBLIC_IRQn = IRQ_NUM_BASE + 63,  /*!< wifi IPC public Interrupt                                         */
+    IRQn_LAST,
+} IRQn_Type;
+
+/**
+ * @brief BL702 Memory Map Definitions
+ */
+#define BL702_FLASH_XIP_BASE        0x23000000
+#define BL702_FLASH_XIP_END         (0x23000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP0_BASE 0x33000000
+#define BL702_FLASH_XIP_REMAP0_END  (0x33000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP1_BASE 0x43000000
+#define BL702_FLASH_XIP_REMAP1_END  (0x43000000 + 16 * 1024 * 1024)
+#define BL702_FLASH_XIP_REMAP2_BASE 0x53000000
+#define BL702_FLASH_XIP_REMAP2_END  (0x53000000 + 16 * 1024 * 1024)
+
+#define BL702_PSRAM_XIP_BASE        0x24000000
+#define BL702_PSRAM_XIP_END         (0x24000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP0_BASE 0x34000000
+#define BL702_PSRAM_XIP_REMAP0_END  (0x34000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP1_BASE 0x44000000
+#define BL702_PSRAM_XIP_REMAP1_END  (0x44000000 + 16 * 1024 * 1024)
+#define BL702_PSRAM_XIP_REMAP2_BASE 0x54000000
+#define BL702_PSRAM_XIP_REMAP2_END  (0x54000000 + 16 * 1024 * 1024)
+
+#define BL702_WRAM_BASE        0x42020000
+#define BL702_WRAM_END         (0x42020000 + 56 * 1024)
+#define BL702_WRAM_REMAP0_BASE 0x22020000
+#define BL702_WRAM_REMAP0_END  (0x22020000 + 56 * 1024)
+#define BL702_WRAM_REMAP1_BASE 0x32020000
+#define BL702_WRAM_REMAP1_END  (0x32020000 + 56 * 1024)
+#define BL702_WRAM_REMAP2_BASE 0x52020000
+#define BL702_WRAM_REMAP2_END  (0x52020000 + 56 * 1024)
+
+#define BL702_TCM_BASE        0x22010000
+#define BL702_TCM_END         (0x22010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP0_BASE 0x32010000
+#define BL702_TCM_REMAP0_END  (0x32010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP1_BASE 0x42010000
+#define BL702_TCM_REMAP1_END  (0x42010000 + (16 + 48) * 1024)
+#define BL702_TCM_REMAP2_BASE 0x52010000
+#define BL702_TCM_REMAP2_END  (0x52010000 + (16 + 48) * 1024)
+/*@} end of group Memory_Map_Section */
+
+/* BL702 peripherals base address */
+#define GLB_BASE         ((uint32_t)0x40000000)
+#define RF_BASE          ((uint32_t)0x40001000)
+#define BZ_PHY_BASE      ((uint32_t)0x40001000)
+#define BZ_PHY_AGC_BASE  ((uint32_t)0x40001000)
+#define GPIP_BASE        ((uint32_t)0x40002000) /*!< AUX module base address */
+#define SEC_DBG_BASE     ((uint32_t)0x40003000) /*!< Security Debug module base address */
+#define SEC_ENG_BASE     ((uint32_t)0x40004000) /*!< Security Engine module base address */
+#define TZC_SEC_BASE     ((uint32_t)0x40005000) /*!< Trustzone control security base address */
+#define TZC_NSEC_BASE    ((uint32_t)0x40006000) /*!< Trustzone control none-security base address */
+#define EF_DATA_BASE     ((uint32_t)0x40007000)
+#define EF_CTRL_BASE     ((uint32_t)0x40007000)
+#define CCI_BASE         ((uint32_t)0x40008000)
+#define L1C_BASE         ((uint32_t)0x40009000) /*!< L1 cache config base address */
+#define UART0_BASE       ((uint32_t)0x4000A000)
+#define UART1_BASE       ((uint32_t)0x4000A100)
+#define SPI_BASE         ((uint32_t)0x4000A200)
+#define I2C_BASE         ((uint32_t)0x4000A300)
+#define PWM_BASE         ((uint32_t)0x4000A400)
+#define TIMER_BASE       ((uint32_t)0x4000A500)
+#define IR_BASE          ((uint32_t)0x4000A600)
+#define CKS_BASE         ((uint32_t)0x4000A700)
+#define QDEC0_BASE       ((uint32_t)0x4000A800)
+#define QDEC1_BASE       ((uint32_t)0x4000A840)
+#define QDEC2_BASE       ((uint32_t)0x4000A880)
+#define KYS_BASE         ((uint32_t)0x4000A900)
+#define I2S_BASE         ((uint32_t)0x4000AA00)
+#define CAM_BASE         ((uint32_t)0x4000AD00)
+#define MJPEG_BASE       ((uint32_t)0x4000AE00)
+#define SF_CTRL_BASE     ((uint32_t)0x4000B000)
+#define SF_CTRL_BUF_BASE ((uint32_t)0x4000B700)
+#define DMA_BASE         ((uint32_t)0x4000C000)
+#define EMAC_BASE        ((uint32_t)0x4000D000)
+#define USB_BASE         ((uint32_t)0x4000D800)
+#define PDS_BASE         ((uint32_t)0x4000E000) /*!< Power down sleep module base address */
+#define HBN_BASE         ((uint32_t)0x4000F000) /*!< Hibernate module base address */
+#define AON_BASE         ((uint32_t)0x4000F000) /*!< Always on module base address */
+#define MAC154_BASE      ((uint32_t)0x4C000000) /*!< MAC154 module base address */
+
+#define HBN_RAM_BASE ((uint32_t)0x40010000)
+
+typedef enum {
+    BL_AHB_SLAVE1_GLB = 0x00,
+    BL_AHB_SLAVE1_MIX = 0x01,
+    BL_AHB_SLAVE1_GPIP = 0x02,
+    BL_AHB_SLAVE1_SEC_DBG = 0x03,
+    BL_AHB_SLAVE1_SEC = 0x04,
+    BL_AHB_SLAVE1_TZ1 = 0x05,
+    BL_AHB_SLAVE1_TZ2 = 0x06,
+    BL_AHB_SLAVE1_EFUSE = 0x07,
+    BL_AHB_SLAVE1_CCI = 0x08,
+    BL_AHB_SLAVE1_L1C = 0x09,
+    BL_AHB_SLAVE1_S1A_ALL = 0x0A,
+    BL_AHB_SLAVE1_SFC = 0x0B,
+    BL_AHB_SLAVE1_DMA = 0x0C,
+    BL_AHB_SLAVE1_EMAC = 0x0D,
+    BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM = 0x0E,
+    BL_AHB_SLAVE1_RSVD0F = 0x0F,
+    BL_AHB_SLAVE1_UART0 = 0x10,
+    BL_AHB_SLAVE1_UART1 = 0x11,
+    BL_AHB_SLAVE1_SPI = 0x12,
+    BL_AHB_SLAVE1_I2C = 0x13,
+    BL_AHB_SLAVE1_PWM = 0x14,
+    BL_AHB_SLAVE1_TMR = 0x15,
+    BL_AHB_SLAVE1_IRR = 0x16,
+    BL_AHB_SLAVE1_CKS = 0x17,
+    BL_AHB_SLAVE1_QDEC = 0x18,
+    BL_AHB_SLAVE1_KYS = 0x19,
+    BL_AHB_SLAVE1_I2S = 0x1A,
+    BL_AHB_SLAVE1_RSVD1B = 0x1B,
+    BL_AHB_SLAVE1_USB = 0x1C,
+    BL_AHB_SLAVE1_CAM = 0x1D,
+    BL_AHB_SLAVE1_MJPEG = 0x1E,
+    BL_AHB_SLAVE1_MAX = 0x1F,
+} BL_AHB_Slave1_Type;
+
+typedef enum {
+    BL_AHB_SEC_ENG_AES0 = 0,
+    BL_AHB_SEC_ENG_AES1,
+    BL_AHB_SEC_ENG_SHA0,
+    BL_AHB_SEC_ENG_SHA1,
+} BL_AHB_Sec_Eng_Type;
+
+typedef enum {
+    BL_AHB_DMA0_CH0 = 0,
+    BL_AHB_DMA0_CH1,
+    BL_AHB_DMA0_CH2,
+    BL_AHB_DMA0_CH3,
+    BL_AHB_DMA0_CH4,
+    BL_AHB_DMA0_CH5,
+    BL_AHB_DMA0_CH6,
+    BL_AHB_DMA0_CH7,
+} BL_AHB_DMA0_CHNL_Type;
+
+typedef enum {
+    BL_AHB_SLAVE2_WIFI_CFG = 0,
+    BL_AHB_SLAVE2_MAX,
+} BL_AHB_Slave2_Type;
+
+typedef enum {
+    BL_AHB_SLAVE3_BLE = 0,
+    BL_AHB_SLAVE3_MAX,
+} BL_AHB_Slave3_Type;
+
+typedef enum {
+    BL_CORE_MASTER_IBUS_CPU = 0,
+    BL_CORE_MASTER_DBUS_CPU,
+    BL_CORE_MASTER_BUS_S2F,
+    BL_CORE_MASTER_MAX,
+} BL_Core_Master_Type;
+
+typedef enum {
+    BL_CORE_SLAVE0_DTCM_CPU = 0,
+    BL_CORE_SLAVE0_MAX,
+} BL_Core_Slave0_Type;
+
+typedef enum {
+    BL_CORE_SLAVE1_XIP_CPU = 0,
+    BL_CORE_SLAVE1_ITCM_CPU,
+    BL_CORE_SLAVE1_ROM,
+    BL_CORE_SLAVE1_MAX,
+} BL_Core_Slave1_Type;
+
+typedef enum {
+    BL_CORE_SLAVE2_F2S = 0,
+    BL_CORE_SLAVE2_MAX,
+} BL_Core_Slave2_Type;
+
+/**
+  * @}
+  */
+#include 
+
+/**
+  * @}
+  */
+
+#endif
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_ctrl_reg.h
new file mode 100755
index 0000000000..b7e95371b2
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_ctrl_reg.h
@@ -0,0 +1,812 @@
+/**
+  ******************************************************************************
+  * @file    ef_ctrl_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __EF_CTRL_REG_H__
+#define __EF_CTRL_REG_H__
+
+#include "bl702.h"
+
+/* 0x800 : ef_if_ctrl_0 */
+#define EF_CTRL_EF_IF_CTRL_0_OFFSET           (0x800)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE      EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS  (0U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN  (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_MSK  (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_UMSK (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_P1_DONE_POS))
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE         EF_CTRL_EF_IF_0_AUTOLOAD_DONE
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS     (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN     (1U)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_MSK     (((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS)
+#define EF_CTRL_EF_IF_0_AUTOLOAD_DONE_UMSK    (~(((1U << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_LEN) - 1) << EF_CTRL_EF_IF_0_AUTOLOAD_DONE_POS))
+#define EF_CTRL_EF_IF_0_BUSY                  EF_CTRL_EF_IF_0_BUSY
+#define EF_CTRL_EF_IF_0_BUSY_POS              (2U)
+#define EF_CTRL_EF_IF_0_BUSY_LEN              (1U)
+#define EF_CTRL_EF_IF_0_BUSY_MSK              (((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS)
+#define EF_CTRL_EF_IF_0_BUSY_UMSK             (~(((1U << EF_CTRL_EF_IF_0_BUSY_LEN) - 1) << EF_CTRL_EF_IF_0_BUSY_POS))
+#define EF_CTRL_EF_IF_0_RW                    EF_CTRL_EF_IF_0_RW
+#define EF_CTRL_EF_IF_0_RW_POS                (3U)
+#define EF_CTRL_EF_IF_0_RW_LEN                (1U)
+#define EF_CTRL_EF_IF_0_RW_MSK                (((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS)
+#define EF_CTRL_EF_IF_0_RW_UMSK               (~(((1U << EF_CTRL_EF_IF_0_RW_LEN) - 1) << EF_CTRL_EF_IF_0_RW_POS))
+#define EF_CTRL_EF_IF_0_TRIG                  EF_CTRL_EF_IF_0_TRIG
+#define EF_CTRL_EF_IF_0_TRIG_POS              (4U)
+#define EF_CTRL_EF_IF_0_TRIG_LEN              (1U)
+#define EF_CTRL_EF_IF_0_TRIG_MSK              (((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS)
+#define EF_CTRL_EF_IF_0_TRIG_UMSK             (~(((1U << EF_CTRL_EF_IF_0_TRIG_LEN) - 1) << EF_CTRL_EF_IF_0_TRIG_POS))
+#define EF_CTRL_EF_IF_0_MANUAL_EN             EF_CTRL_EF_IF_0_MANUAL_EN
+#define EF_CTRL_EF_IF_0_MANUAL_EN_POS         (5U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_LEN         (1U)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_MSK         (((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS)
+#define EF_CTRL_EF_IF_0_MANUAL_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_0_MANUAL_EN_LEN) - 1) << EF_CTRL_EF_IF_0_MANUAL_EN_POS))
+#define EF_CTRL_EF_IF_0_CYC_MODIFY            EF_CTRL_EF_IF_0_CYC_MODIFY
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_POS        (6U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_LEN        (1U)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_MSK        (((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS)
+#define EF_CTRL_EF_IF_0_CYC_MODIFY_UMSK       (~(((1U << EF_CTRL_EF_IF_0_CYC_MODIFY_LEN) - 1) << EF_CTRL_EF_IF_0_CYC_MODIFY_POS))
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL          EF_CTRL_EF_CLK_SAHB_DATA_SEL
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS      (7U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN      (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_MSK      (((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_SEL_UMSK     (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_SEL_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_SEL_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL          EF_CTRL_EF_IF_PROT_CODE_CTRL
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_POS      (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN      (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_MSK      (((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CTRL_UMSK     (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CTRL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CTRL_POS))
+#define EF_CTRL_EF_IF_POR_DIG                 EF_CTRL_EF_IF_POR_DIG
+#define EF_CTRL_EF_IF_POR_DIG_POS             (16U)
+#define EF_CTRL_EF_IF_POR_DIG_LEN             (1U)
+#define EF_CTRL_EF_IF_POR_DIG_MSK             (((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS)
+#define EF_CTRL_EF_IF_POR_DIG_UMSK            (~(((1U << EF_CTRL_EF_IF_POR_DIG_LEN) - 1) << EF_CTRL_EF_IF_POR_DIG_POS))
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE         EF_CTRL_EF_CLK_SAHB_DATA_GATE
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS     (17U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN     (1U)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_MSK     (((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS)
+#define EF_CTRL_EF_CLK_SAHB_DATA_GATE_UMSK    (~(((1U << EF_CTRL_EF_CLK_SAHB_DATA_GATE_LEN) - 1) << EF_CTRL_EF_CLK_SAHB_DATA_GATE_POS))
+#define EF_CTRL_EF_IF_AUTO_RD_EN              EF_CTRL_EF_IF_AUTO_RD_EN
+#define EF_CTRL_EF_IF_AUTO_RD_EN_POS          (18U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_LEN          (1U)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_MSK          (((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS)
+#define EF_CTRL_EF_IF_AUTO_RD_EN_UMSK         (~(((1U << EF_CTRL_EF_IF_AUTO_RD_EN_LEN) - 1) << EF_CTRL_EF_IF_AUTO_RD_EN_POS))
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK         EF_CTRL_EF_IF_CYC_MODIFY_LOCK
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS     (19U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN     (1U)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_MSK     (((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS)
+#define EF_CTRL_EF_IF_CYC_MODIFY_LOCK_UMSK    (~(((1U << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_LEN) - 1) << EF_CTRL_EF_IF_CYC_MODIFY_LOCK_POS))
+#define EF_CTRL_EF_IF_0_INT                   EF_CTRL_EF_IF_0_INT
+#define EF_CTRL_EF_IF_0_INT_POS               (20U)
+#define EF_CTRL_EF_IF_0_INT_LEN               (1U)
+#define EF_CTRL_EF_IF_0_INT_MSK               (((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS)
+#define EF_CTRL_EF_IF_0_INT_UMSK              (~(((1U << EF_CTRL_EF_IF_0_INT_LEN) - 1) << EF_CTRL_EF_IF_0_INT_POS))
+#define EF_CTRL_EF_IF_0_INT_CLR               EF_CTRL_EF_IF_0_INT_CLR
+#define EF_CTRL_EF_IF_0_INT_CLR_POS           (21U)
+#define EF_CTRL_EF_IF_0_INT_CLR_LEN           (1U)
+#define EF_CTRL_EF_IF_0_INT_CLR_MSK           (((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS)
+#define EF_CTRL_EF_IF_0_INT_CLR_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_CLR_LEN) - 1) << EF_CTRL_EF_IF_0_INT_CLR_POS))
+#define EF_CTRL_EF_IF_0_INT_SET               EF_CTRL_EF_IF_0_INT_SET
+#define EF_CTRL_EF_IF_0_INT_SET_POS           (22U)
+#define EF_CTRL_EF_IF_0_INT_SET_LEN           (1U)
+#define EF_CTRL_EF_IF_0_INT_SET_MSK           (((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS)
+#define EF_CTRL_EF_IF_0_INT_SET_UMSK          (~(((1U << EF_CTRL_EF_IF_0_INT_SET_LEN) - 1) << EF_CTRL_EF_IF_0_INT_SET_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_CYC           EF_CTRL_EF_IF_PROT_CODE_CYC
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_POS       (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_LEN       (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_MSK       (((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_CYC_UMSK      (~(((1U << EF_CTRL_EF_IF_PROT_CODE_CYC_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_CYC_POS))
+
+/* 0x804 : ef_if_cyc_0 */
+#define EF_CTRL_EF_IF_CYC_0_OFFSET     (0x804)
+#define EF_CTRL_EF_IF_CYC_RD_DMY       EF_CTRL_EF_IF_CYC_RD_DMY
+#define EF_CTRL_EF_IF_CYC_RD_DMY_POS   (0U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DMY_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DMY_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DMY_POS))
+#define EF_CTRL_EF_IF_CYC_RD_DAT       EF_CTRL_EF_IF_CYC_RD_DAT
+#define EF_CTRL_EF_IF_CYC_RD_DAT_POS   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS)
+#define EF_CTRL_EF_IF_CYC_RD_DAT_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_DAT_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_DAT_POS))
+#define EF_CTRL_EF_IF_CYC_RD_ADR       EF_CTRL_EF_IF_CYC_RD_ADR
+#define EF_CTRL_EF_IF_CYC_RD_ADR_POS   (12U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_RD_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_RD_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_RD_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_CS           EF_CTRL_EF_IF_CYC_CS
+#define EF_CTRL_EF_IF_CYC_CS_POS       (18U)
+#define EF_CTRL_EF_IF_CYC_CS_LEN       (6U)
+#define EF_CTRL_EF_IF_CYC_CS_MSK       (((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS)
+#define EF_CTRL_EF_IF_CYC_CS_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_S      EF_CTRL_EF_IF_CYC_PD_CS_S
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_POS  (24U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_LEN  (8U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_S_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_S_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_S_POS))
+
+/* 0x808 : ef_if_cyc_1 */
+#define EF_CTRL_EF_IF_CYC_1_OFFSET     (0x808)
+#define EF_CTRL_EF_IF_CYC_PI           EF_CTRL_EF_IF_CYC_PI
+#define EF_CTRL_EF_IF_CYC_PI_POS       (0U)
+#define EF_CTRL_EF_IF_CYC_PI_LEN       (6U)
+#define EF_CTRL_EF_IF_CYC_PI_MSK       (((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS)
+#define EF_CTRL_EF_IF_CYC_PI_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PI_LEN) - 1) << EF_CTRL_EF_IF_CYC_PI_POS))
+#define EF_CTRL_EF_IF_CYC_PP           EF_CTRL_EF_IF_CYC_PP
+#define EF_CTRL_EF_IF_CYC_PP_POS       (6U)
+#define EF_CTRL_EF_IF_CYC_PP_LEN       (8U)
+#define EF_CTRL_EF_IF_CYC_PP_MSK       (((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS)
+#define EF_CTRL_EF_IF_CYC_PP_UMSK      (~(((1U << EF_CTRL_EF_IF_CYC_PP_LEN) - 1) << EF_CTRL_EF_IF_CYC_PP_POS))
+#define EF_CTRL_EF_IF_CYC_WR_ADR       EF_CTRL_EF_IF_CYC_WR_ADR
+#define EF_CTRL_EF_IF_CYC_WR_ADR_POS   (14U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_LEN   (6U)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_MSK   (((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS)
+#define EF_CTRL_EF_IF_CYC_WR_ADR_UMSK  (~(((1U << EF_CTRL_EF_IF_CYC_WR_ADR_LEN) - 1) << EF_CTRL_EF_IF_CYC_WR_ADR_POS))
+#define EF_CTRL_EF_IF_CYC_PS_CS        EF_CTRL_EF_IF_CYC_PS_CS
+#define EF_CTRL_EF_IF_CYC_PS_CS_POS    (20U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_LEN    (6U)
+#define EF_CTRL_EF_IF_CYC_PS_CS_MSK    (((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS)
+#define EF_CTRL_EF_IF_CYC_PS_CS_UMSK   (~(((1U << EF_CTRL_EF_IF_CYC_PS_CS_LEN) - 1) << EF_CTRL_EF_IF_CYC_PS_CS_POS))
+#define EF_CTRL_EF_IF_CYC_PD_CS_H      EF_CTRL_EF_IF_CYC_PD_CS_H
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_POS  (26U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_LEN  (6U)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_MSK  (((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS)
+#define EF_CTRL_EF_IF_CYC_PD_CS_H_UMSK (~(((1U << EF_CTRL_EF_IF_CYC_PD_CS_H_LEN) - 1) << EF_CTRL_EF_IF_CYC_PD_CS_H_POS))
+
+/* 0x80C : ef_if_0_manual */
+#define EF_CTRL_EF_IF_0_MANUAL_OFFSET       (0x80C)
+#define EF_CTRL_EF_IF_A                     EF_CTRL_EF_IF_A
+#define EF_CTRL_EF_IF_A_POS                 (0U)
+#define EF_CTRL_EF_IF_A_LEN                 (10U)
+#define EF_CTRL_EF_IF_A_MSK                 (((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS)
+#define EF_CTRL_EF_IF_A_UMSK                (~(((1U << EF_CTRL_EF_IF_A_LEN) - 1) << EF_CTRL_EF_IF_A_POS))
+#define EF_CTRL_EF_IF_PD                    EF_CTRL_EF_IF_PD
+#define EF_CTRL_EF_IF_PD_POS                (10U)
+#define EF_CTRL_EF_IF_PD_LEN                (1U)
+#define EF_CTRL_EF_IF_PD_MSK                (((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS)
+#define EF_CTRL_EF_IF_PD_UMSK               (~(((1U << EF_CTRL_EF_IF_PD_LEN) - 1) << EF_CTRL_EF_IF_PD_POS))
+#define EF_CTRL_EF_IF_PS                    EF_CTRL_EF_IF_PS
+#define EF_CTRL_EF_IF_PS_POS                (11U)
+#define EF_CTRL_EF_IF_PS_LEN                (1U)
+#define EF_CTRL_EF_IF_PS_MSK                (((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS)
+#define EF_CTRL_EF_IF_PS_UMSK               (~(((1U << EF_CTRL_EF_IF_PS_LEN) - 1) << EF_CTRL_EF_IF_PS_POS))
+#define EF_CTRL_EF_IF_STROBE                EF_CTRL_EF_IF_STROBE
+#define EF_CTRL_EF_IF_STROBE_POS            (12U)
+#define EF_CTRL_EF_IF_STROBE_LEN            (1U)
+#define EF_CTRL_EF_IF_STROBE_MSK            (((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS)
+#define EF_CTRL_EF_IF_STROBE_UMSK           (~(((1U << EF_CTRL_EF_IF_STROBE_LEN) - 1) << EF_CTRL_EF_IF_STROBE_POS))
+#define EF_CTRL_EF_IF_PGENB                 EF_CTRL_EF_IF_PGENB
+#define EF_CTRL_EF_IF_PGENB_POS             (13U)
+#define EF_CTRL_EF_IF_PGENB_LEN             (1U)
+#define EF_CTRL_EF_IF_PGENB_MSK             (((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS)
+#define EF_CTRL_EF_IF_PGENB_UMSK            (~(((1U << EF_CTRL_EF_IF_PGENB_LEN) - 1) << EF_CTRL_EF_IF_PGENB_POS))
+#define EF_CTRL_EF_IF_LOAD                  EF_CTRL_EF_IF_LOAD
+#define EF_CTRL_EF_IF_LOAD_POS              (14U)
+#define EF_CTRL_EF_IF_LOAD_LEN              (1U)
+#define EF_CTRL_EF_IF_LOAD_MSK              (((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS)
+#define EF_CTRL_EF_IF_LOAD_UMSK             (~(((1U << EF_CTRL_EF_IF_LOAD_LEN) - 1) << EF_CTRL_EF_IF_LOAD_POS))
+#define EF_CTRL_EF_IF_CSB                   EF_CTRL_EF_IF_CSB
+#define EF_CTRL_EF_IF_CSB_POS               (15U)
+#define EF_CTRL_EF_IF_CSB_LEN               (1U)
+#define EF_CTRL_EF_IF_CSB_MSK               (((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS)
+#define EF_CTRL_EF_IF_CSB_UMSK              (~(((1U << EF_CTRL_EF_IF_CSB_LEN) - 1) << EF_CTRL_EF_IF_CSB_POS))
+#define EF_CTRL_EF_IF_0_Q                   EF_CTRL_EF_IF_0_Q
+#define EF_CTRL_EF_IF_0_Q_POS               (16U)
+#define EF_CTRL_EF_IF_0_Q_LEN               (8U)
+#define EF_CTRL_EF_IF_0_Q_MSK               (((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS)
+#define EF_CTRL_EF_IF_0_Q_UMSK              (~(((1U << EF_CTRL_EF_IF_0_Q_LEN) - 1) << EF_CTRL_EF_IF_0_Q_POS))
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL      EF_CTRL_EF_IF_PROT_CODE_MANUAL
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS  (24U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN  (8U)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_MSK  (((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS)
+#define EF_CTRL_EF_IF_PROT_CODE_MANUAL_UMSK (~(((1U << EF_CTRL_EF_IF_PROT_CODE_MANUAL_LEN) - 1) << EF_CTRL_EF_IF_PROT_CODE_MANUAL_POS))
+
+/* 0x810 : ef_if_0_status */
+#define EF_CTRL_EF_IF_0_STATUS_OFFSET (0x810)
+#define EF_CTRL_EF_IF_0_STATUS        EF_CTRL_EF_IF_0_STATUS
+#define EF_CTRL_EF_IF_0_STATUS_POS    (0U)
+#define EF_CTRL_EF_IF_0_STATUS_LEN    (32U)
+#define EF_CTRL_EF_IF_0_STATUS_MSK    (((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS)
+#define EF_CTRL_EF_IF_0_STATUS_UMSK   (~(((1U << EF_CTRL_EF_IF_0_STATUS_LEN) - 1) << EF_CTRL_EF_IF_0_STATUS_POS))
+
+/* 0x814 : ef_if_cfg_0 */
+#define EF_CTRL_EF_IF_CFG_0_OFFSET         (0x814)
+#define EF_CTRL_EF_IF_SF_AES_MODE          EF_CTRL_EF_IF_SF_AES_MODE
+#define EF_CTRL_EF_IF_SF_AES_MODE_POS      (0U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_LEN      (2U)
+#define EF_CTRL_EF_IF_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS)
+#define EF_CTRL_EF_IF_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_IF_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_IF_SF_AES_MODE_POS))
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE      EF_CTRL_EF_IF_SBOOT_SIGN_MODE
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS)
+#define EF_CTRL_EF_IF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_SIGN_MODE_POS))
+#define EF_CTRL_EF_IF_SBOOT_EN             EF_CTRL_EF_IF_SBOOT_EN
+#define EF_CTRL_EF_IF_SBOOT_EN_POS         (4U)
+#define EF_CTRL_EF_IF_SBOOT_EN_LEN         (2U)
+#define EF_CTRL_EF_IF_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS)
+#define EF_CTRL_EF_IF_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_IF_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_IF_SBOOT_EN_POS))
+#define EF_CTRL_EF_IF_CPU1_ENC_EN          EF_CTRL_EF_IF_CPU1_ENC_EN
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_POS      (6U)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS)
+#define EF_CTRL_EF_IF_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU1_ENC_EN_POS))
+#define EF_CTRL_EF_IF_CPU0_ENC_EN          EF_CTRL_EF_IF_CPU0_ENC_EN
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_POS      (7U)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS)
+#define EF_CTRL_EF_IF_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_IF_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_CPU0_ENC_EN_POS))
+#define EF_CTRL_EF_IF_BOOT_SEL             EF_CTRL_EF_IF_BOOT_SEL
+#define EF_CTRL_EF_IF_BOOT_SEL_POS         (8U)
+#define EF_CTRL_EF_IF_BOOT_SEL_LEN         (4U)
+#define EF_CTRL_EF_IF_BOOT_SEL_MSK         (((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS)
+#define EF_CTRL_EF_IF_BOOT_SEL_UMSK        (~(((1U << EF_CTRL_EF_IF_BOOT_SEL_LEN) - 1) << EF_CTRL_EF_IF_BOOT_SEL_POS))
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL         EF_CTRL_EF_IF_SF_KEY_0_SEL
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_POS     (12U)
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN     (2U)
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_MSK     (((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS)
+#define EF_CTRL_EF_IF_SF_KEY_0_SEL_UMSK    (~(((1U << EF_CTRL_EF_IF_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_IF_SF_KEY_0_SEL_POS))
+#define EF_CTRL_EF_IF_SDU_DIS              EF_CTRL_EF_IF_SDU_DIS
+#define EF_CTRL_EF_IF_SDU_DIS_POS          (14U)
+#define EF_CTRL_EF_IF_SDU_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_SDU_DIS_MSK          (((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS)
+#define EF_CTRL_EF_IF_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_SDU_DIS_LEN) - 1) << EF_CTRL_EF_IF_SDU_DIS_POS))
+#define EF_CTRL_EF_IF_BLE_DIS              EF_CTRL_EF_IF_BLE_DIS
+#define EF_CTRL_EF_IF_BLE_DIS_POS          (15U)
+#define EF_CTRL_EF_IF_BLE_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_BLE_DIS_MSK          (((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS)
+#define EF_CTRL_EF_IF_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_BLE_DIS_LEN) - 1) << EF_CTRL_EF_IF_BLE_DIS_POS))
+#define EF_CTRL_EF_IF_WIFI_DIS             EF_CTRL_EF_IF_WIFI_DIS
+#define EF_CTRL_EF_IF_WIFI_DIS_POS         (16U)
+#define EF_CTRL_EF_IF_WIFI_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS)
+#define EF_CTRL_EF_IF_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_IF_WIFI_DIS_POS))
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN         EF_CTRL_EF_IF_0_KEY_ENC_EN
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_POS     (17U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN     (1U)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_IF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_IF_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_IF_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_IF_CAM_DIS              EF_CTRL_EF_IF_CAM_DIS
+#define EF_CTRL_EF_IF_CAM_DIS_POS          (18U)
+#define EF_CTRL_EF_IF_CAM_DIS_LEN          (1U)
+#define EF_CTRL_EF_IF_CAM_DIS_MSK          (((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS)
+#define EF_CTRL_EF_IF_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_IF_CAM_DIS_LEN) - 1) << EF_CTRL_EF_IF_CAM_DIS_POS))
+#define EF_CTRL_EF_IF_M154_DIS             EF_CTRL_EF_IF_M154_DIS
+#define EF_CTRL_EF_IF_M154_DIS_POS         (19U)
+#define EF_CTRL_EF_IF_M154_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_M154_DIS_MSK         (((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS)
+#define EF_CTRL_EF_IF_M154_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_M154_DIS_LEN) - 1) << EF_CTRL_EF_IF_M154_DIS_POS))
+#define EF_CTRL_EF_IF_CPU1_DIS             EF_CTRL_EF_IF_CPU1_DIS
+#define EF_CTRL_EF_IF_CPU1_DIS_POS         (20U)
+#define EF_CTRL_EF_IF_CPU1_DIS_LEN         (1U)
+#define EF_CTRL_EF_IF_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS)
+#define EF_CTRL_EF_IF_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_IF_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU1_DIS_POS))
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS      EF_CTRL_EF_IF_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS  (21U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN  (1U)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_SE_DBG_DIS           EF_CTRL_EF_IF_SE_DBG_DIS
+#define EF_CTRL_EF_IF_SE_DBG_DIS_POS       (22U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_LEN       (1U)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_IF_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS        EF_CTRL_EF_IF_EFUSE_DBG_DIS
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS    (23U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN    (1U)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_IF_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_IF_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_IF_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS       EF_CTRL_EF_IF_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS   (24U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN   (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS       EF_CTRL_EF_IF_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_IF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_IF_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_IF_DBG_MODE             EF_CTRL_EF_IF_DBG_MODE
+#define EF_CTRL_EF_IF_DBG_MODE_POS         (28U)
+#define EF_CTRL_EF_IF_DBG_MODE_LEN         (4U)
+#define EF_CTRL_EF_IF_DBG_MODE_MSK         (((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS)
+#define EF_CTRL_EF_IF_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_IF_DBG_MODE_LEN) - 1) << EF_CTRL_EF_IF_DBG_MODE_POS))
+
+/* 0x818 : ef_sw_cfg_0 */
+#define EF_CTRL_EF_SW_CFG_0_OFFSET         (0x818)
+#define EF_CTRL_EF_SW_SF_AES_MODE          EF_CTRL_EF_SW_SF_AES_MODE
+#define EF_CTRL_EF_SW_SF_AES_MODE_POS      (0U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_LEN      (2U)
+#define EF_CTRL_EF_SW_SF_AES_MODE_MSK      (((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS)
+#define EF_CTRL_EF_SW_SF_AES_MODE_UMSK     (~(((1U << EF_CTRL_EF_SW_SF_AES_MODE_LEN) - 1) << EF_CTRL_EF_SW_SF_AES_MODE_POS))
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE      EF_CTRL_EF_SW_SBOOT_SIGN_MODE
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_MSK  (((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS)
+#define EF_CTRL_EF_SW_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_SIGN_MODE_POS))
+#define EF_CTRL_EF_SW_SBOOT_EN             EF_CTRL_EF_SW_SBOOT_EN
+#define EF_CTRL_EF_SW_SBOOT_EN_POS         (4U)
+#define EF_CTRL_EF_SW_SBOOT_EN_LEN         (2U)
+#define EF_CTRL_EF_SW_SBOOT_EN_MSK         (((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS)
+#define EF_CTRL_EF_SW_SBOOT_EN_UMSK        (~(((1U << EF_CTRL_EF_SW_SBOOT_EN_LEN) - 1) << EF_CTRL_EF_SW_SBOOT_EN_POS))
+#define EF_CTRL_EF_SW_CPU1_ENC_EN          EF_CTRL_EF_SW_CPU1_ENC_EN
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_POS      (6U)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS)
+#define EF_CTRL_EF_SW_CPU1_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU1_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU1_ENC_EN_POS))
+#define EF_CTRL_EF_SW_CPU0_ENC_EN          EF_CTRL_EF_SW_CPU0_ENC_EN
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_POS      (7U)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_LEN      (1U)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_MSK      (((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS)
+#define EF_CTRL_EF_SW_CPU0_ENC_EN_UMSK     (~(((1U << EF_CTRL_EF_SW_CPU0_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_CPU0_ENC_EN_POS))
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL         EF_CTRL_EF_SW_SF_KEY_0_SEL
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_POS     (12U)
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN     (2U)
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_MSK     (((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS)
+#define EF_CTRL_EF_SW_SF_KEY_0_SEL_UMSK    (~(((1U << EF_CTRL_EF_SW_SF_KEY_0_SEL_LEN) - 1) << EF_CTRL_EF_SW_SF_KEY_0_SEL_POS))
+#define EF_CTRL_EF_SW_SDU_DIS              EF_CTRL_EF_SW_SDU_DIS
+#define EF_CTRL_EF_SW_SDU_DIS_POS          (14U)
+#define EF_CTRL_EF_SW_SDU_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_SDU_DIS_MSK          (((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS)
+#define EF_CTRL_EF_SW_SDU_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_SDU_DIS_LEN) - 1) << EF_CTRL_EF_SW_SDU_DIS_POS))
+#define EF_CTRL_EF_SW_BLE_DIS              EF_CTRL_EF_SW_BLE_DIS
+#define EF_CTRL_EF_SW_BLE_DIS_POS          (15U)
+#define EF_CTRL_EF_SW_BLE_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_BLE_DIS_MSK          (((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS)
+#define EF_CTRL_EF_SW_BLE_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_BLE_DIS_LEN) - 1) << EF_CTRL_EF_SW_BLE_DIS_POS))
+#define EF_CTRL_EF_SW_WIFI_DIS             EF_CTRL_EF_SW_WIFI_DIS
+#define EF_CTRL_EF_SW_WIFI_DIS_POS         (16U)
+#define EF_CTRL_EF_SW_WIFI_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_WIFI_DIS_MSK         (((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS)
+#define EF_CTRL_EF_SW_WIFI_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_WIFI_DIS_LEN) - 1) << EF_CTRL_EF_SW_WIFI_DIS_POS))
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN         EF_CTRL_EF_SW_0_KEY_ENC_EN
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_POS     (17U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN     (1U)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_MSK     (((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS)
+#define EF_CTRL_EF_SW_0_KEY_ENC_EN_UMSK    (~(((1U << EF_CTRL_EF_SW_0_KEY_ENC_EN_LEN) - 1) << EF_CTRL_EF_SW_0_KEY_ENC_EN_POS))
+#define EF_CTRL_EF_SW_CAM_DIS              EF_CTRL_EF_SW_CAM_DIS
+#define EF_CTRL_EF_SW_CAM_DIS_POS          (18U)
+#define EF_CTRL_EF_SW_CAM_DIS_LEN          (1U)
+#define EF_CTRL_EF_SW_CAM_DIS_MSK          (((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS)
+#define EF_CTRL_EF_SW_CAM_DIS_UMSK         (~(((1U << EF_CTRL_EF_SW_CAM_DIS_LEN) - 1) << EF_CTRL_EF_SW_CAM_DIS_POS))
+#define EF_CTRL_EF_SW_M154_DIS             EF_CTRL_EF_SW_M154_DIS
+#define EF_CTRL_EF_SW_M154_DIS_POS         (19U)
+#define EF_CTRL_EF_SW_M154_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_M154_DIS_MSK         (((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS)
+#define EF_CTRL_EF_SW_M154_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_M154_DIS_LEN) - 1) << EF_CTRL_EF_SW_M154_DIS_POS))
+#define EF_CTRL_EF_SW_CPU1_DIS             EF_CTRL_EF_SW_CPU1_DIS
+#define EF_CTRL_EF_SW_CPU1_DIS_POS         (20U)
+#define EF_CTRL_EF_SW_CPU1_DIS_LEN         (1U)
+#define EF_CTRL_EF_SW_CPU1_DIS_MSK         (((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS)
+#define EF_CTRL_EF_SW_CPU1_DIS_UMSK        (~(((1U << EF_CTRL_EF_SW_CPU1_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU1_DIS_POS))
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS      EF_CTRL_EF_SW_CPU_RST_DBG_DIS
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS  (21U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN  (1U)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_MSK  (((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_CPU_RST_DBG_DIS_UMSK (~(((1U << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_CPU_RST_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_SE_DBG_DIS           EF_CTRL_EF_SW_SE_DBG_DIS
+#define EF_CTRL_EF_SW_SE_DBG_DIS_POS       (22U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_LEN       (1U)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_MSK       (((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_SE_DBG_DIS_UMSK      (~(((1U << EF_CTRL_EF_SW_SE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_SE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS        EF_CTRL_EF_SW_EFUSE_DBG_DIS
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS    (23U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN    (1U)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_MSK    (((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS)
+#define EF_CTRL_EF_SW_EFUSE_DBG_DIS_UMSK   (~(((1U << EF_CTRL_EF_SW_EFUSE_DBG_DIS_LEN) - 1) << EF_CTRL_EF_SW_EFUSE_DBG_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS       EF_CTRL_EF_SW_DBG_JTAG_1_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS   (24U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN   (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_1_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_1_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS       EF_CTRL_EF_SW_DBG_JTAG_0_DIS
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_MSK   (((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS)
+#define EF_CTRL_EF_SW_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_LEN) - 1) << EF_CTRL_EF_SW_DBG_JTAG_0_DIS_POS))
+#define EF_CTRL_EF_SW_DBG_MODE             EF_CTRL_EF_SW_DBG_MODE
+#define EF_CTRL_EF_SW_DBG_MODE_POS         (28U)
+#define EF_CTRL_EF_SW_DBG_MODE_LEN         (4U)
+#define EF_CTRL_EF_SW_DBG_MODE_MSK         (((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS)
+#define EF_CTRL_EF_SW_DBG_MODE_UMSK        (~(((1U << EF_CTRL_EF_SW_DBG_MODE_LEN) - 1) << EF_CTRL_EF_SW_DBG_MODE_POS))
+
+/* 0x81C : ef_reserved */
+#define EF_CTRL_EF_RESERVED_OFFSET (0x81C)
+#define EF_CTRL_EF_RESERVED        EF_CTRL_EF_RESERVED
+#define EF_CTRL_EF_RESERVED_POS    (0U)
+#define EF_CTRL_EF_RESERVED_LEN    (32U)
+#define EF_CTRL_EF_RESERVED_MSK    (((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS)
+#define EF_CTRL_EF_RESERVED_UMSK   (~(((1U << EF_CTRL_EF_RESERVED_LEN) - 1) << EF_CTRL_EF_RESERVED_POS))
+
+/* 0x820 : ef_if_ana_trim_0 */
+#define EF_CTRL_EF_IF_ANA_TRIM_0_OFFSET (0x820)
+#define EF_CTRL_EF_IF_ANA_TRIM_0        EF_CTRL_EF_IF_ANA_TRIM_0
+#define EF_CTRL_EF_IF_ANA_TRIM_0_POS    (0U)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_LEN    (32U)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_MSK    (((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS)
+#define EF_CTRL_EF_IF_ANA_TRIM_0_UMSK   (~(((1U << EF_CTRL_EF_IF_ANA_TRIM_0_LEN) - 1) << EF_CTRL_EF_IF_ANA_TRIM_0_POS))
+
+/* 0x824 : ef_if_sw_usage_0 */
+#define EF_CTRL_EF_IF_SW_USAGE_0_OFFSET (0x824)
+#define EF_CTRL_EF_IF_SW_USAGE_0        EF_CTRL_EF_IF_SW_USAGE_0
+#define EF_CTRL_EF_IF_SW_USAGE_0_POS    (0U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_LEN    (32U)
+#define EF_CTRL_EF_IF_SW_USAGE_0_MSK    (((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS)
+#define EF_CTRL_EF_IF_SW_USAGE_0_UMSK   (~(((1U << EF_CTRL_EF_IF_SW_USAGE_0_LEN) - 1) << EF_CTRL_EF_IF_SW_USAGE_0_POS))
+
+/* 0xA00 : ef_crc_ctrl_0 */
+#define EF_CTRL_EF_CRC_CTRL_0_OFFSET    (0xA00)
+#define EF_CTRL_EF_CRC_BUSY             EF_CTRL_EF_CRC_BUSY
+#define EF_CTRL_EF_CRC_BUSY_POS         (0U)
+#define EF_CTRL_EF_CRC_BUSY_LEN         (1U)
+#define EF_CTRL_EF_CRC_BUSY_MSK         (((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS)
+#define EF_CTRL_EF_CRC_BUSY_UMSK        (~(((1U << EF_CTRL_EF_CRC_BUSY_LEN) - 1) << EF_CTRL_EF_CRC_BUSY_POS))
+#define EF_CTRL_EF_CRC_TRIG             EF_CTRL_EF_CRC_TRIG
+#define EF_CTRL_EF_CRC_TRIG_POS         (1U)
+#define EF_CTRL_EF_CRC_TRIG_LEN         (1U)
+#define EF_CTRL_EF_CRC_TRIG_MSK         (((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS)
+#define EF_CTRL_EF_CRC_TRIG_UMSK        (~(((1U << EF_CTRL_EF_CRC_TRIG_LEN) - 1) << EF_CTRL_EF_CRC_TRIG_POS))
+#define EF_CTRL_EF_CRC_EN               EF_CTRL_EF_CRC_EN
+#define EF_CTRL_EF_CRC_EN_POS           (2U)
+#define EF_CTRL_EF_CRC_EN_LEN           (1U)
+#define EF_CTRL_EF_CRC_EN_MSK           (((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS)
+#define EF_CTRL_EF_CRC_EN_UMSK          (~(((1U << EF_CTRL_EF_CRC_EN_LEN) - 1) << EF_CTRL_EF_CRC_EN_POS))
+#define EF_CTRL_EF_CRC_MODE             EF_CTRL_EF_CRC_MODE
+#define EF_CTRL_EF_CRC_MODE_POS         (3U)
+#define EF_CTRL_EF_CRC_MODE_LEN         (1U)
+#define EF_CTRL_EF_CRC_MODE_MSK         (((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS)
+#define EF_CTRL_EF_CRC_MODE_UMSK        (~(((1U << EF_CTRL_EF_CRC_MODE_LEN) - 1) << EF_CTRL_EF_CRC_MODE_POS))
+#define EF_CTRL_EF_CRC_ERROR            EF_CTRL_EF_CRC_ERROR
+#define EF_CTRL_EF_CRC_ERROR_POS        (4U)
+#define EF_CTRL_EF_CRC_ERROR_LEN        (1U)
+#define EF_CTRL_EF_CRC_ERROR_MSK        (((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS)
+#define EF_CTRL_EF_CRC_ERROR_UMSK       (~(((1U << EF_CTRL_EF_CRC_ERROR_LEN) - 1) << EF_CTRL_EF_CRC_ERROR_POS))
+#define EF_CTRL_EF_CRC_DOUT_INV_EN      EF_CTRL_EF_CRC_DOUT_INV_EN
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_POS  (5U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_LEN  (1U)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS)
+#define EF_CTRL_EF_CRC_DOUT_INV_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_INV_EN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_INV_EN_POS))
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN      EF_CTRL_EF_CRC_DOUT_ENDIAN
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_POS  (6U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN  (1U)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_MSK  (((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DOUT_ENDIAN_UMSK (~(((1U << EF_CTRL_EF_CRC_DOUT_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_DIN_ENDIAN       EF_CTRL_EF_CRC_DIN_ENDIAN
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_POS   (7U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_LEN   (1U)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_MSK   (((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS)
+#define EF_CTRL_EF_CRC_DIN_ENDIAN_UMSK  (~(((1U << EF_CTRL_EF_CRC_DIN_ENDIAN_LEN) - 1) << EF_CTRL_EF_CRC_DIN_ENDIAN_POS))
+#define EF_CTRL_EF_CRC_INT              EF_CTRL_EF_CRC_INT
+#define EF_CTRL_EF_CRC_INT_POS          (8U)
+#define EF_CTRL_EF_CRC_INT_LEN          (1U)
+#define EF_CTRL_EF_CRC_INT_MSK          (((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS)
+#define EF_CTRL_EF_CRC_INT_UMSK         (~(((1U << EF_CTRL_EF_CRC_INT_LEN) - 1) << EF_CTRL_EF_CRC_INT_POS))
+#define EF_CTRL_EF_CRC_INT_CLR          EF_CTRL_EF_CRC_INT_CLR
+#define EF_CTRL_EF_CRC_INT_CLR_POS      (9U)
+#define EF_CTRL_EF_CRC_INT_CLR_LEN      (1U)
+#define EF_CTRL_EF_CRC_INT_CLR_MSK      (((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS)
+#define EF_CTRL_EF_CRC_INT_CLR_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_CLR_LEN) - 1) << EF_CTRL_EF_CRC_INT_CLR_POS))
+#define EF_CTRL_EF_CRC_INT_SET          EF_CTRL_EF_CRC_INT_SET
+#define EF_CTRL_EF_CRC_INT_SET_POS      (10U)
+#define EF_CTRL_EF_CRC_INT_SET_LEN      (1U)
+#define EF_CTRL_EF_CRC_INT_SET_MSK      (((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS)
+#define EF_CTRL_EF_CRC_INT_SET_UMSK     (~(((1U << EF_CTRL_EF_CRC_INT_SET_LEN) - 1) << EF_CTRL_EF_CRC_INT_SET_POS))
+#define EF_CTRL_EF_CRC_LOCK             EF_CTRL_EF_CRC_LOCK
+#define EF_CTRL_EF_CRC_LOCK_POS         (11U)
+#define EF_CTRL_EF_CRC_LOCK_LEN         (1U)
+#define EF_CTRL_EF_CRC_LOCK_MSK         (((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS)
+#define EF_CTRL_EF_CRC_LOCK_UMSK        (~(((1U << EF_CTRL_EF_CRC_LOCK_LEN) - 1) << EF_CTRL_EF_CRC_LOCK_POS))
+#define EF_CTRL_EF_CRC_SLP_N            EF_CTRL_EF_CRC_SLP_N
+#define EF_CTRL_EF_CRC_SLP_N_POS        (16U)
+#define EF_CTRL_EF_CRC_SLP_N_LEN        (16U)
+#define EF_CTRL_EF_CRC_SLP_N_MSK        (((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS)
+#define EF_CTRL_EF_CRC_SLP_N_UMSK       (~(((1U << EF_CTRL_EF_CRC_SLP_N_LEN) - 1) << EF_CTRL_EF_CRC_SLP_N_POS))
+
+/* 0xA04 : ef_crc_ctrl_1 */
+#define EF_CTRL_EF_CRC_CTRL_1_OFFSET  (0xA04)
+#define EF_CTRL_EF_CRC_DATA_0_EN      EF_CTRL_EF_CRC_DATA_0_EN
+#define EF_CTRL_EF_CRC_DATA_0_EN_POS  (0U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_LEN  (32U)
+#define EF_CTRL_EF_CRC_DATA_0_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_0_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_0_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_0_EN_POS))
+
+/* 0xA08 : ef_crc_ctrl_2 */
+#define EF_CTRL_EF_CRC_CTRL_2_OFFSET  (0xA08)
+#define EF_CTRL_EF_CRC_DATA_1_EN      EF_CTRL_EF_CRC_DATA_1_EN
+#define EF_CTRL_EF_CRC_DATA_1_EN_POS  (0U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_LEN  (32U)
+#define EF_CTRL_EF_CRC_DATA_1_EN_MSK  (((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS)
+#define EF_CTRL_EF_CRC_DATA_1_EN_UMSK (~(((1U << EF_CTRL_EF_CRC_DATA_1_EN_LEN) - 1) << EF_CTRL_EF_CRC_DATA_1_EN_POS))
+
+/* 0xA0C : ef_crc_ctrl_3 */
+#define EF_CTRL_EF_CRC_CTRL_3_OFFSET (0xA0C)
+#define EF_CTRL_EF_CRC_IV            EF_CTRL_EF_CRC_IV
+#define EF_CTRL_EF_CRC_IV_POS        (0U)
+#define EF_CTRL_EF_CRC_IV_LEN        (32U)
+#define EF_CTRL_EF_CRC_IV_MSK        (((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS)
+#define EF_CTRL_EF_CRC_IV_UMSK       (~(((1U << EF_CTRL_EF_CRC_IV_LEN) - 1) << EF_CTRL_EF_CRC_IV_POS))
+
+/* 0xA10 : ef_crc_ctrl_4 */
+#define EF_CTRL_EF_CRC_CTRL_4_OFFSET (0xA10)
+#define EF_CTRL_EF_CRC_GOLDEN        EF_CTRL_EF_CRC_GOLDEN
+#define EF_CTRL_EF_CRC_GOLDEN_POS    (0U)
+#define EF_CTRL_EF_CRC_GOLDEN_LEN    (32U)
+#define EF_CTRL_EF_CRC_GOLDEN_MSK    (((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS)
+#define EF_CTRL_EF_CRC_GOLDEN_UMSK   (~(((1U << EF_CTRL_EF_CRC_GOLDEN_LEN) - 1) << EF_CTRL_EF_CRC_GOLDEN_POS))
+
+/* 0xA14 : ef_crc_ctrl_5 */
+#define EF_CTRL_EF_CRC_CTRL_5_OFFSET (0xA14)
+#define EF_CTRL_EF_CRC_DOUT          EF_CTRL_EF_CRC_DOUT
+#define EF_CTRL_EF_CRC_DOUT_POS      (0U)
+#define EF_CTRL_EF_CRC_DOUT_LEN      (32U)
+#define EF_CTRL_EF_CRC_DOUT_MSK      (((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS)
+#define EF_CTRL_EF_CRC_DOUT_UMSK     (~(((1U << EF_CTRL_EF_CRC_DOUT_LEN) - 1) << EF_CTRL_EF_CRC_DOUT_POS))
+
+struct ef_ctrl_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[2048];
+
+    /* 0x800 : ef_if_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_0_autoload_p1_done : 1; /* [    0],          r,        0x1 */
+            uint32_t ef_if_0_autoload_done    : 1; /* [    1],          r,        0x1 */
+            uint32_t ef_if_0_busy             : 1; /* [    2],          r,        0x0 */
+            uint32_t ef_if_0_rw               : 1; /* [    3],        r/w,        0x0 */
+            uint32_t ef_if_0_trig             : 1; /* [    4],        r/w,        0x0 */
+            uint32_t ef_if_0_manual_en        : 1; /* [    5],        r/w,        0x0 */
+            uint32_t ef_if_0_cyc_modify       : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_clk_sahb_data_sel     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t ef_if_prot_code_ctrl     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t ef_if_por_dig            : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_clk_sahb_data_gate    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t ef_if_auto_rd_en         : 1; /* [   18],        r/w,        0x1 */
+            uint32_t ef_if_cyc_modify_lock    : 1; /* [   19],        r/w,        0x0 */
+            uint32_t ef_if_0_int              : 1; /* [   20],          r,        0x0 */
+            uint32_t ef_if_0_int_clr          : 1; /* [   21],        r/w,        0x1 */
+            uint32_t ef_if_0_int_set          : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reserved_23              : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t ef_if_prot_code_cyc      : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_ctrl_0;
+
+    /* 0x804 : ef_if_cyc_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_cyc_rd_dmy  : 6; /* [ 5: 0],        r/w,        0x0 */
+            uint32_t ef_if_cyc_rd_dat  : 6; /* [11: 6],        r/w,        0x1 */
+            uint32_t ef_if_cyc_rd_adr  : 6; /* [17:12],        r/w,        0x0 */
+            uint32_t ef_if_cyc_cs      : 6; /* [23:18],        r/w,        0x0 */
+            uint32_t ef_if_cyc_pd_cs_s : 8; /* [31:24],        r/w,       0x16 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cyc_0;
+
+    /* 0x808 : ef_if_cyc_1 */
+    union {
+        struct
+        {
+            uint32_t ef_if_cyc_pi      : 6; /* [ 5: 0],        r/w,        0x9 */
+            uint32_t ef_if_cyc_pp      : 8; /* [13: 6],        r/w,       0x98 */
+            uint32_t ef_if_cyc_wr_adr  : 6; /* [19:14],        r/w,        0x1 */
+            uint32_t ef_if_cyc_ps_cs   : 6; /* [25:20],        r/w,        0x2 */
+            uint32_t ef_if_cyc_pd_cs_h : 6; /* [31:26],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cyc_1;
+
+    /* 0x80C : ef_if_0_manual */
+    union {
+        struct
+        {
+            uint32_t ef_if_a                : 10; /* [ 9: 0],        r/w,        0x0 */
+            uint32_t ef_if_pd               : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t ef_if_ps               : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t ef_if_strobe           : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t ef_if_pgenb            : 1;  /* [   13],        r/w,        0x1 */
+            uint32_t ef_if_load             : 1;  /* [   14],        r/w,        0x1 */
+            uint32_t ef_if_csb              : 1;  /* [   15],        r/w,        0x1 */
+            uint32_t ef_if_0_q              : 8;  /* [23:16],          r,        0x0 */
+            uint32_t ef_if_prot_code_manual : 8;  /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_0_manual;
+
+    /* 0x810 : ef_if_0_status */
+    union {
+        struct
+        {
+            uint32_t ef_if_0_status : 32; /* [31: 0],          r,     0xe400 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_0_status;
+
+    /* 0x814 : ef_if_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_sf_aes_mode     : 2; /* [ 1: 0],          r,        0x0 */
+            uint32_t ef_if_sboot_sign_mode : 2; /* [ 3: 2],          r,        0x0 */
+            uint32_t ef_if_sboot_en        : 2; /* [ 5: 4],          r,        0x0 */
+            uint32_t ef_if_cpu1_enc_en     : 1; /* [    6],          r,        0x0 */
+            uint32_t ef_if_cpu0_enc_en     : 1; /* [    7],          r,        0x0 */
+            uint32_t ef_if_boot_sel        : 4; /* [11: 8],          r,        0x0 */
+            uint32_t ef_if_sf_key_0_sel    : 2; /* [13:12],          r,        0x0 */
+            uint32_t ef_if_sdu_dis         : 1; /* [   14],          r,        0x0 */
+            uint32_t ef_if_ble_dis         : 1; /* [   15],          r,        0x0 */
+            uint32_t ef_if_wifi_dis        : 1; /* [   16],          r,        0x0 */
+            uint32_t ef_if_0_key_enc_en    : 1; /* [   17],          r,        0x0 */
+            uint32_t ef_if_cam_dis         : 1; /* [   18],          r,        0x0 */
+            uint32_t ef_if_m154_dis        : 1; /* [   19],          r,        0x0 */
+            uint32_t ef_if_cpu1_dis        : 1; /* [   20],          r,        0x0 */
+            uint32_t ef_if_cpu_rst_dbg_dis : 1; /* [   21],          r,        0x0 */
+            uint32_t ef_if_se_dbg_dis      : 1; /* [   22],          r,        0x0 */
+            uint32_t ef_if_efuse_dbg_dis   : 1; /* [   23],          r,        0x0 */
+            uint32_t ef_if_dbg_jtag_1_dis  : 2; /* [25:24],          r,        0x0 */
+            uint32_t ef_if_dbg_jtag_0_dis  : 2; /* [27:26],          r,        0x0 */
+            uint32_t ef_if_dbg_mode        : 4; /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_cfg_0;
+
+    /* 0x818 : ef_sw_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sw_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t ef_sw_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t ef_sw_sboot_en        : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t ef_sw_cpu1_enc_en     : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_sw_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_11         : 4; /* [11: 8],       rsvd,        0x0 */
+            uint32_t ef_sw_sf_key_0_sel    : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t ef_sw_sdu_dis         : 1; /* [   14],        r/w,        0x0 */
+            uint32_t ef_sw_ble_dis         : 1; /* [   15],        r/w,        0x0 */
+            uint32_t ef_sw_wifi_dis        : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_sw_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t ef_sw_cam_dis         : 1; /* [   18],        r/w,        0x0 */
+            uint32_t ef_sw_m154_dis        : 1; /* [   19],        r/w,        0x0 */
+            uint32_t ef_sw_cpu1_dis        : 1; /* [   20],        r/w,        0x0 */
+            uint32_t ef_sw_cpu_rst_dbg_dis : 1; /* [   21],        r/w,        0x0 */
+            uint32_t ef_sw_se_dbg_dis      : 1; /* [   22],        r/w,        0x0 */
+            uint32_t ef_sw_efuse_dbg_dis   : 1; /* [   23],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_jtag_1_dis  : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
+            uint32_t ef_sw_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_sw_cfg_0;
+
+    /* 0x81C : ef_reserved */
+    union {
+        struct
+        {
+            uint32_t ef_reserved : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } ef_reserved;
+
+    /* 0x820 : ef_if_ana_trim_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_ana_trim_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_ana_trim_0;
+
+    /* 0x824 : ef_if_sw_usage_0 */
+    union {
+        struct
+        {
+            uint32_t ef_if_sw_usage_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_if_sw_usage_0;
+
+    /* 0x828  reserved */
+    uint8_t RESERVED0x828[472];
+
+    /* 0xA00 : ef_crc_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_busy        : 1;  /* [    0],          r,        0x0 */
+            uint32_t ef_crc_trig        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t ef_crc_en          : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t ef_crc_mode        : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t ef_crc_error       : 1;  /* [    4],          r,        0x0 */
+            uint32_t ef_crc_dout_inv_en : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t ef_crc_dout_endian : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t ef_crc_din_endian  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t ef_crc_int         : 1;  /* [    8],          r,        0x0 */
+            uint32_t ef_crc_int_clr     : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t ef_crc_int_set     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t ef_crc_lock        : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15     : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t ef_crc_slp_n       : 16; /* [31:16],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_0;
+
+    /* 0xA04 : ef_crc_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_data_0_en : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_1;
+
+    /* 0xA08 : ef_crc_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_data_1_en : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_2;
+
+    /* 0xA0C : ef_crc_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_iv : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_3;
+
+    /* 0xA10 : ef_crc_ctrl_4 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_golden : 32; /* [31: 0],        r/w, 0xc2a8fa9dL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_4;
+
+    /* 0xA14 : ef_crc_ctrl_5 */
+    union {
+        struct
+        {
+            uint32_t ef_crc_dout : 32; /* [31: 0],          r, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } ef_crc_ctrl_5;
+};
+
+typedef volatile struct ef_ctrl_reg ef_ctrl_reg_t;
+
+#endif /* __EF_CTRL_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_data_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_data_reg.h
new file mode 100755
index 0000000000..b9811de4ac
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/ef_data_reg.h
@@ -0,0 +1,762 @@
+/**
+  ******************************************************************************
+  * @file    EF_DATA_reg.h
+  * @version V1.2
+  * @date    2020-04-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __EF_DATA_REG_H__
+#define __EF_DATA_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : ef_cfg_0 */
+#define EF_DATA_EF_CFG_0_OFFSET         (0x0)
+#define EF_DATA_EF_SF_AES_MODE          EF_DATA_EF_SF_AES_MODE
+#define EF_DATA_EF_SF_AES_MODE_POS      (0U)
+#define EF_DATA_EF_SF_AES_MODE_LEN      (2U)
+#define EF_DATA_EF_SF_AES_MODE_MSK      (((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS)
+#define EF_DATA_EF_SF_AES_MODE_UMSK     (~(((1U << EF_DATA_EF_SF_AES_MODE_LEN) - 1) << EF_DATA_EF_SF_AES_MODE_POS))
+#define EF_DATA_EF_SBOOT_SIGN_MODE      EF_DATA_EF_SBOOT_SIGN_MODE
+#define EF_DATA_EF_SBOOT_SIGN_MODE_POS  (2U)
+#define EF_DATA_EF_SBOOT_SIGN_MODE_LEN  (2U)
+#define EF_DATA_EF_SBOOT_SIGN_MODE_MSK  (((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS)
+#define EF_DATA_EF_SBOOT_SIGN_MODE_UMSK (~(((1U << EF_DATA_EF_SBOOT_SIGN_MODE_LEN) - 1) << EF_DATA_EF_SBOOT_SIGN_MODE_POS))
+#define EF_DATA_EF_SBOOT_EN             EF_DATA_EF_SBOOT_EN
+#define EF_DATA_EF_SBOOT_EN_POS         (4U)
+#define EF_DATA_EF_SBOOT_EN_LEN         (2U)
+#define EF_DATA_EF_SBOOT_EN_MSK         (((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS)
+#define EF_DATA_EF_SBOOT_EN_UMSK        (~(((1U << EF_DATA_EF_SBOOT_EN_LEN) - 1) << EF_DATA_EF_SBOOT_EN_POS))
+#define EF_DATA_EF_CPU0_ENC_EN          EF_DATA_EF_CPU0_ENC_EN
+#define EF_DATA_EF_CPU0_ENC_EN_POS      (7U)
+#define EF_DATA_EF_CPU0_ENC_EN_LEN      (1U)
+#define EF_DATA_EF_CPU0_ENC_EN_MSK      (((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS)
+#define EF_DATA_EF_CPU0_ENC_EN_UMSK     (~(((1U << EF_DATA_EF_CPU0_ENC_EN_LEN) - 1) << EF_DATA_EF_CPU0_ENC_EN_POS))
+#define EF_DATA_EF_BOOT_SEL             EF_DATA_EF_BOOT_SEL
+#define EF_DATA_EF_BOOT_SEL_POS         (8U)
+#define EF_DATA_EF_BOOT_SEL_LEN         (4U)
+#define EF_DATA_EF_BOOT_SEL_MSK         (((1U << EF_DATA_EF_BOOT_SEL_LEN) - 1) << EF_DATA_EF_BOOT_SEL_POS)
+#define EF_DATA_EF_BOOT_SEL_UMSK        (~(((1U << EF_DATA_EF_BOOT_SEL_LEN) - 1) << EF_DATA_EF_BOOT_SEL_POS))
+#define EF_DATA_EF_SF_KEY_0_SEL         EF_DATA_EF_SF_KEY_0_SEL
+#define EF_DATA_EF_SF_KEY_0_SEL_POS     (12U)
+#define EF_DATA_EF_SF_KEY_0_SEL_LEN     (2U)
+#define EF_DATA_EF_SF_KEY_0_SEL_MSK     (((1U << EF_DATA_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_EF_SF_KEY_0_SEL_POS)
+#define EF_DATA_EF_SF_KEY_0_SEL_UMSK    (~(((1U << EF_DATA_EF_SF_KEY_0_SEL_LEN) - 1) << EF_DATA_EF_SF_KEY_0_SEL_POS))
+#define EF_DATA_EF_0_KEY_ENC_EN         EF_DATA_EF_0_KEY_ENC_EN
+#define EF_DATA_EF_0_KEY_ENC_EN_POS     (17U)
+#define EF_DATA_EF_0_KEY_ENC_EN_LEN     (1U)
+#define EF_DATA_EF_0_KEY_ENC_EN_MSK     (((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS)
+#define EF_DATA_EF_0_KEY_ENC_EN_UMSK    (~(((1U << EF_DATA_EF_0_KEY_ENC_EN_LEN) - 1) << EF_DATA_EF_0_KEY_ENC_EN_POS))
+#define EF_DATA_EF_DBG_JTAG_0_DIS       EF_DATA_EF_DBG_JTAG_0_DIS
+#define EF_DATA_EF_DBG_JTAG_0_DIS_POS   (26U)
+#define EF_DATA_EF_DBG_JTAG_0_DIS_LEN   (2U)
+#define EF_DATA_EF_DBG_JTAG_0_DIS_MSK   (((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS)
+#define EF_DATA_EF_DBG_JTAG_0_DIS_UMSK  (~(((1U << EF_DATA_EF_DBG_JTAG_0_DIS_LEN) - 1) << EF_DATA_EF_DBG_JTAG_0_DIS_POS))
+#define EF_DATA_EF_DBG_MODE             EF_DATA_EF_DBG_MODE
+#define EF_DATA_EF_DBG_MODE_POS         (28U)
+#define EF_DATA_EF_DBG_MODE_LEN         (4U)
+#define EF_DATA_EF_DBG_MODE_MSK         (((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS)
+#define EF_DATA_EF_DBG_MODE_UMSK        (~(((1U << EF_DATA_EF_DBG_MODE_LEN) - 1) << EF_DATA_EF_DBG_MODE_POS))
+
+/* 0x4 : ef_dbg_pwd_low */
+#define EF_DATA_EF_DBG_PWD_LOW_OFFSET (0x4)
+#define EF_DATA_EF_DBG_PWD_LOW        EF_DATA_EF_DBG_PWD_LOW
+#define EF_DATA_EF_DBG_PWD_LOW_POS    (0U)
+#define EF_DATA_EF_DBG_PWD_LOW_LEN    (32U)
+#define EF_DATA_EF_DBG_PWD_LOW_MSK    (((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS)
+#define EF_DATA_EF_DBG_PWD_LOW_UMSK   (~(((1U << EF_DATA_EF_DBG_PWD_LOW_LEN) - 1) << EF_DATA_EF_DBG_PWD_LOW_POS))
+
+/* 0x8 : ef_dbg_pwd_high */
+#define EF_DATA_EF_DBG_PWD_HIGH_OFFSET (0x8)
+#define EF_DATA_EF_DBG_PWD_HIGH        EF_DATA_EF_DBG_PWD_HIGH
+#define EF_DATA_EF_DBG_PWD_HIGH_POS    (0U)
+#define EF_DATA_EF_DBG_PWD_HIGH_LEN    (32U)
+#define EF_DATA_EF_DBG_PWD_HIGH_MSK    (((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS)
+#define EF_DATA_EF_DBG_PWD_HIGH_UMSK   (~(((1U << EF_DATA_EF_DBG_PWD_HIGH_LEN) - 1) << EF_DATA_EF_DBG_PWD_HIGH_POS))
+
+/* 0xC : ef_ana_trim_0 */
+#define EF_DATA_EF_ANA_TRIM_0_OFFSET (0xC)
+#define EF_DATA_EF_ANA_TRIM_0        EF_DATA_EF_ANA_TRIM_0
+#define EF_DATA_EF_ANA_TRIM_0_POS    (0U)
+#define EF_DATA_EF_ANA_TRIM_0_LEN    (32U)
+#define EF_DATA_EF_ANA_TRIM_0_MSK    (((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS)
+#define EF_DATA_EF_ANA_TRIM_0_UMSK   (~(((1U << EF_DATA_EF_ANA_TRIM_0_LEN) - 1) << EF_DATA_EF_ANA_TRIM_0_POS))
+
+/* 0x10 : ef_sw_usage_0 */
+#define EF_DATA_EF_SW_USAGE_0_OFFSET (0x10)
+#define EF_DATA_EF_SW_USAGE_0        EF_DATA_EF_SW_USAGE_0
+#define EF_DATA_EF_SW_USAGE_0_POS    (0U)
+#define EF_DATA_EF_SW_USAGE_0_LEN    (32U)
+#define EF_DATA_EF_SW_USAGE_0_MSK    (((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS)
+#define EF_DATA_EF_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_EF_SW_USAGE_0_LEN) - 1) << EF_DATA_EF_SW_USAGE_0_POS))
+
+/* 0x14 : ef_wifi_mac_low */
+#define EF_DATA_EF_WIFI_MAC_LOW_OFFSET (0x14)
+#define EF_DATA_EF_WIFI_MAC_LOW        EF_DATA_EF_WIFI_MAC_LOW
+#define EF_DATA_EF_WIFI_MAC_LOW_POS    (0U)
+#define EF_DATA_EF_WIFI_MAC_LOW_LEN    (32U)
+#define EF_DATA_EF_WIFI_MAC_LOW_MSK    (((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS)
+#define EF_DATA_EF_WIFI_MAC_LOW_UMSK   (~(((1U << EF_DATA_EF_WIFI_MAC_LOW_LEN) - 1) << EF_DATA_EF_WIFI_MAC_LOW_POS))
+
+/* 0x18 : ef_wifi_mac_high */
+#define EF_DATA_EF_WIFI_MAC_HIGH_OFFSET (0x18)
+#define EF_DATA_EF_WIFI_MAC_HIGH        EF_DATA_EF_WIFI_MAC_HIGH
+#define EF_DATA_EF_WIFI_MAC_HIGH_POS    (0U)
+#define EF_DATA_EF_WIFI_MAC_HIGH_LEN    (32U)
+#define EF_DATA_EF_WIFI_MAC_HIGH_MSK    (((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS)
+#define EF_DATA_EF_WIFI_MAC_HIGH_UMSK   (~(((1U << EF_DATA_EF_WIFI_MAC_HIGH_LEN) - 1) << EF_DATA_EF_WIFI_MAC_HIGH_POS))
+
+/* 0x1C : ef_key_slot_0_w0 */
+#define EF_DATA_EF_KEY_SLOT_0_W0_OFFSET (0x1C)
+#define EF_DATA_EF_KEY_SLOT_0_W0        EF_DATA_EF_KEY_SLOT_0_W0
+#define EF_DATA_EF_KEY_SLOT_0_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W0_POS))
+
+/* 0x20 : ef_key_slot_0_w1 */
+#define EF_DATA_EF_KEY_SLOT_0_W1_OFFSET (0x20)
+#define EF_DATA_EF_KEY_SLOT_0_W1        EF_DATA_EF_KEY_SLOT_0_W1
+#define EF_DATA_EF_KEY_SLOT_0_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W1_POS))
+
+/* 0x24 : ef_key_slot_0_w2 */
+#define EF_DATA_EF_KEY_SLOT_0_W2_OFFSET (0x24)
+#define EF_DATA_EF_KEY_SLOT_0_W2        EF_DATA_EF_KEY_SLOT_0_W2
+#define EF_DATA_EF_KEY_SLOT_0_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W2_POS))
+
+/* 0x28 : ef_key_slot_0_w3 */
+#define EF_DATA_EF_KEY_SLOT_0_W3_OFFSET (0x28)
+#define EF_DATA_EF_KEY_SLOT_0_W3        EF_DATA_EF_KEY_SLOT_0_W3
+#define EF_DATA_EF_KEY_SLOT_0_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_0_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_0_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_0_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_0_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_0_W3_POS))
+
+/* 0x2C : ef_key_slot_1_w0 */
+#define EF_DATA_EF_KEY_SLOT_1_W0_OFFSET (0x2C)
+#define EF_DATA_EF_KEY_SLOT_1_W0        EF_DATA_EF_KEY_SLOT_1_W0
+#define EF_DATA_EF_KEY_SLOT_1_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W0_POS))
+
+/* 0x30 : ef_key_slot_1_w1 */
+#define EF_DATA_EF_KEY_SLOT_1_W1_OFFSET (0x30)
+#define EF_DATA_EF_KEY_SLOT_1_W1        EF_DATA_EF_KEY_SLOT_1_W1
+#define EF_DATA_EF_KEY_SLOT_1_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W1_POS))
+
+/* 0x34 : ef_key_slot_1_w2 */
+#define EF_DATA_EF_KEY_SLOT_1_W2_OFFSET (0x34)
+#define EF_DATA_EF_KEY_SLOT_1_W2        EF_DATA_EF_KEY_SLOT_1_W2
+#define EF_DATA_EF_KEY_SLOT_1_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W2_POS))
+
+/* 0x38 : ef_key_slot_1_w3 */
+#define EF_DATA_EF_KEY_SLOT_1_W3_OFFSET (0x38)
+#define EF_DATA_EF_KEY_SLOT_1_W3        EF_DATA_EF_KEY_SLOT_1_W3
+#define EF_DATA_EF_KEY_SLOT_1_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_1_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_1_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_1_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_1_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_1_W3_POS))
+
+/* 0x3C : ef_key_slot_2_w0 */
+#define EF_DATA_EF_KEY_SLOT_2_W0_OFFSET (0x3C)
+#define EF_DATA_EF_KEY_SLOT_2_W0        EF_DATA_EF_KEY_SLOT_2_W0
+#define EF_DATA_EF_KEY_SLOT_2_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W0_POS))
+
+/* 0x40 : ef_key_slot_2_w1 */
+#define EF_DATA_EF_KEY_SLOT_2_W1_OFFSET (0x40)
+#define EF_DATA_EF_KEY_SLOT_2_W1        EF_DATA_EF_KEY_SLOT_2_W1
+#define EF_DATA_EF_KEY_SLOT_2_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W1_POS))
+
+/* 0x44 : ef_key_slot_2_w2 */
+#define EF_DATA_EF_KEY_SLOT_2_W2_OFFSET (0x44)
+#define EF_DATA_EF_KEY_SLOT_2_W2        EF_DATA_EF_KEY_SLOT_2_W2
+#define EF_DATA_EF_KEY_SLOT_2_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W2_POS))
+
+/* 0x48 : ef_key_slot_2_w3 */
+#define EF_DATA_EF_KEY_SLOT_2_W3_OFFSET (0x48)
+#define EF_DATA_EF_KEY_SLOT_2_W3        EF_DATA_EF_KEY_SLOT_2_W3
+#define EF_DATA_EF_KEY_SLOT_2_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_2_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_2_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_2_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_2_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_2_W3_POS))
+
+/* 0x4C : ef_key_slot_3_w0 */
+#define EF_DATA_EF_KEY_SLOT_3_W0_OFFSET (0x4C)
+#define EF_DATA_EF_KEY_SLOT_3_W0        EF_DATA_EF_KEY_SLOT_3_W0
+#define EF_DATA_EF_KEY_SLOT_3_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W0_POS))
+
+/* 0x50 : ef_key_slot_3_w1 */
+#define EF_DATA_EF_KEY_SLOT_3_W1_OFFSET (0x50)
+#define EF_DATA_EF_KEY_SLOT_3_W1        EF_DATA_EF_KEY_SLOT_3_W1
+#define EF_DATA_EF_KEY_SLOT_3_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W1_POS))
+
+/* 0x54 : ef_key_slot_3_w2 */
+#define EF_DATA_EF_KEY_SLOT_3_W2_OFFSET (0x54)
+#define EF_DATA_EF_KEY_SLOT_3_W2        EF_DATA_EF_KEY_SLOT_3_W2
+#define EF_DATA_EF_KEY_SLOT_3_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W2_POS))
+
+/* 0x58 : ef_key_slot_3_w3 */
+#define EF_DATA_EF_KEY_SLOT_3_W3_OFFSET (0x58)
+#define EF_DATA_EF_KEY_SLOT_3_W3        EF_DATA_EF_KEY_SLOT_3_W3
+#define EF_DATA_EF_KEY_SLOT_3_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_3_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_3_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_3_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_3_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_3_W3_POS))
+
+/* 0x5C : ef_key_slot_4_w0 */
+#define EF_DATA_EF_KEY_SLOT_4_W0_OFFSET (0x5C)
+#define EF_DATA_EF_KEY_SLOT_4_W0        EF_DATA_EF_KEY_SLOT_4_W0
+#define EF_DATA_EF_KEY_SLOT_4_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W0_POS))
+
+/* 0x60 : ef_key_slot_4_w1 */
+#define EF_DATA_EF_KEY_SLOT_4_W1_OFFSET (0x60)
+#define EF_DATA_EF_KEY_SLOT_4_W1        EF_DATA_EF_KEY_SLOT_4_W1
+#define EF_DATA_EF_KEY_SLOT_4_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W1_POS))
+
+/* 0x64 : ef_key_slot_4_w2 */
+#define EF_DATA_EF_KEY_SLOT_4_W2_OFFSET (0x64)
+#define EF_DATA_EF_KEY_SLOT_4_W2        EF_DATA_EF_KEY_SLOT_4_W2
+#define EF_DATA_EF_KEY_SLOT_4_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W2_POS))
+
+/* 0x68 : ef_key_slot_4_w3 */
+#define EF_DATA_EF_KEY_SLOT_4_W3_OFFSET (0x68)
+#define EF_DATA_EF_KEY_SLOT_4_W3        EF_DATA_EF_KEY_SLOT_4_W3
+#define EF_DATA_EF_KEY_SLOT_4_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_4_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_4_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_4_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_4_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_4_W3_POS))
+
+/* 0x6C : ef_key_slot_5_w0 */
+#define EF_DATA_EF_KEY_SLOT_5_W0_OFFSET (0x6C)
+#define EF_DATA_EF_KEY_SLOT_5_W0        EF_DATA_EF_KEY_SLOT_5_W0
+#define EF_DATA_EF_KEY_SLOT_5_W0_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W0_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W0_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W0_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W0_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W0_POS))
+
+/* 0x70 : ef_key_slot_5_w1 */
+#define EF_DATA_EF_KEY_SLOT_5_W1_OFFSET (0x70)
+#define EF_DATA_EF_KEY_SLOT_5_W1        EF_DATA_EF_KEY_SLOT_5_W1
+#define EF_DATA_EF_KEY_SLOT_5_W1_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W1_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W1_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W1_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W1_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W1_POS))
+
+/* 0x74 : ef_key_slot_5_w2 */
+#define EF_DATA_EF_KEY_SLOT_5_W2_OFFSET (0x74)
+#define EF_DATA_EF_KEY_SLOT_5_W2        EF_DATA_EF_KEY_SLOT_5_W2
+#define EF_DATA_EF_KEY_SLOT_5_W2_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W2_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W2_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W2_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W2_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W2_POS))
+
+/* 0x78 : ef_key_slot_5_w3 */
+#define EF_DATA_EF_KEY_SLOT_5_W3_OFFSET (0x78)
+#define EF_DATA_EF_KEY_SLOT_5_W3        EF_DATA_EF_KEY_SLOT_5_W3
+#define EF_DATA_EF_KEY_SLOT_5_W3_POS    (0U)
+#define EF_DATA_EF_KEY_SLOT_5_W3_LEN    (32U)
+#define EF_DATA_EF_KEY_SLOT_5_W3_MSK    (((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS)
+#define EF_DATA_EF_KEY_SLOT_5_W3_UMSK   (~(((1U << EF_DATA_EF_KEY_SLOT_5_W3_LEN) - 1) << EF_DATA_EF_KEY_SLOT_5_W3_POS))
+
+/* 0x7C : EF_DATA_lock */
+#define EF_DATA_LOCK_OFFSET               (0x7C)
+#define EF_DATA_EF_ANA_TRIM_1             EF_DATA_EF_ANA_TRIM_1
+#define EF_DATA_EF_ANA_TRIM_1_POS         (0U)
+#define EF_DATA_EF_ANA_TRIM_1_LEN         (13U)
+#define EF_DATA_EF_ANA_TRIM_1_MSK         (((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS)
+#define EF_DATA_EF_ANA_TRIM_1_UMSK        (~(((1U << EF_DATA_EF_ANA_TRIM_1_LEN) - 1) << EF_DATA_EF_ANA_TRIM_1_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L      EF_DATA_WR_LOCK_KEY_SLOT_4_L
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS  (13U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_L_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L      EF_DATA_WR_LOCK_KEY_SLOT_5_L
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS  (14U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_L_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_L_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_L_POS))
+#define EF_DATA_WR_LOCK_BOOT_MODE         EF_DATA_WR_LOCK_BOOT_MODE
+#define EF_DATA_WR_LOCK_BOOT_MODE_POS     (15U)
+#define EF_DATA_WR_LOCK_BOOT_MODE_LEN     (1U)
+#define EF_DATA_WR_LOCK_BOOT_MODE_MSK     (((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS)
+#define EF_DATA_WR_LOCK_BOOT_MODE_UMSK    (~(((1U << EF_DATA_WR_LOCK_BOOT_MODE_LEN) - 1) << EF_DATA_WR_LOCK_BOOT_MODE_POS))
+#define EF_DATA_WR_LOCK_DBG_PWD           EF_DATA_WR_LOCK_DBG_PWD
+#define EF_DATA_WR_LOCK_DBG_PWD_POS       (16U)
+#define EF_DATA_WR_LOCK_DBG_PWD_LEN       (1U)
+#define EF_DATA_WR_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS)
+#define EF_DATA_WR_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_WR_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_WR_LOCK_DBG_PWD_POS))
+#define EF_DATA_WR_LOCK_SW_USAGE_0        EF_DATA_WR_LOCK_SW_USAGE_0
+#define EF_DATA_WR_LOCK_SW_USAGE_0_POS    (17U)
+#define EF_DATA_WR_LOCK_SW_USAGE_0_LEN    (1U)
+#define EF_DATA_WR_LOCK_SW_USAGE_0_MSK    (((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS)
+#define EF_DATA_WR_LOCK_SW_USAGE_0_UMSK   (~(((1U << EF_DATA_WR_LOCK_SW_USAGE_0_LEN) - 1) << EF_DATA_WR_LOCK_SW_USAGE_0_POS))
+#define EF_DATA_WR_LOCK_WIFI_MAC          EF_DATA_WR_LOCK_WIFI_MAC
+#define EF_DATA_WR_LOCK_WIFI_MAC_POS      (18U)
+#define EF_DATA_WR_LOCK_WIFI_MAC_LEN      (1U)
+#define EF_DATA_WR_LOCK_WIFI_MAC_MSK      (((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS)
+#define EF_DATA_WR_LOCK_WIFI_MAC_UMSK     (~(((1U << EF_DATA_WR_LOCK_WIFI_MAC_LEN) - 1) << EF_DATA_WR_LOCK_WIFI_MAC_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_0        EF_DATA_WR_LOCK_KEY_SLOT_0
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_POS    (19U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_1        EF_DATA_WR_LOCK_KEY_SLOT_1
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_POS    (20U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_2        EF_DATA_WR_LOCK_KEY_SLOT_2
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_POS    (21U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_3        EF_DATA_WR_LOCK_KEY_SLOT_3
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_POS    (22U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_LEN    (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H      EF_DATA_WR_LOCK_KEY_SLOT_4_H
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS  (23U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_4_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_4_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_4_H_POS))
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H      EF_DATA_WR_LOCK_KEY_SLOT_5_H
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS  (24U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN  (1U)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_MSK  (((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS)
+#define EF_DATA_WR_LOCK_KEY_SLOT_5_H_UMSK (~(((1U << EF_DATA_WR_LOCK_KEY_SLOT_5_H_LEN) - 1) << EF_DATA_WR_LOCK_KEY_SLOT_5_H_POS))
+#define EF_DATA_RD_LOCK_DBG_PWD           EF_DATA_RD_LOCK_DBG_PWD
+#define EF_DATA_RD_LOCK_DBG_PWD_POS       (25U)
+#define EF_DATA_RD_LOCK_DBG_PWD_LEN       (1U)
+#define EF_DATA_RD_LOCK_DBG_PWD_MSK       (((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS)
+#define EF_DATA_RD_LOCK_DBG_PWD_UMSK      (~(((1U << EF_DATA_RD_LOCK_DBG_PWD_LEN) - 1) << EF_DATA_RD_LOCK_DBG_PWD_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_0        EF_DATA_RD_LOCK_KEY_SLOT_0
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_POS    (26U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_0_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_0_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_0_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_1        EF_DATA_RD_LOCK_KEY_SLOT_1
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_POS    (27U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_1_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_1_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_1_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_2        EF_DATA_RD_LOCK_KEY_SLOT_2
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_POS    (28U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_2_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_2_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_2_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_3        EF_DATA_RD_LOCK_KEY_SLOT_3
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_POS    (29U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_3_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_3_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_3_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_4        EF_DATA_RD_LOCK_KEY_SLOT_4
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_POS    (30U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_4_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_4_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_4_POS))
+#define EF_DATA_RD_LOCK_KEY_SLOT_5        EF_DATA_RD_LOCK_KEY_SLOT_5
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_POS    (31U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_LEN    (1U)
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_MSK    (((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS)
+#define EF_DATA_RD_LOCK_KEY_SLOT_5_UMSK   (~(((1U << EF_DATA_RD_LOCK_KEY_SLOT_5_LEN) - 1) << EF_DATA_RD_LOCK_KEY_SLOT_5_POS))
+
+struct EF_DATA_reg {
+    /* 0x0 : ef_cfg_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sf_aes_mode     : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t ef_sboot_sign_mode : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t rsvd0              : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t rsvd1              : 1; /* [    6],        r/w,        0x0 */
+            uint32_t ef_cpu0_enc_en     : 1; /* [    7],        r/w,        0x0 */
+            uint32_t ef_boot_sel        : 4; /* [11: 8],        r/w,        0x0 */
+            uint32_t ef_sf_key_0_sel    : 2; /* [13:12],        r/w,        0x0 */
+            uint32_t rsvd2              : 1; /* [   14],        r/w,        0x0 */
+            uint32_t rsvd3              : 1; /* [   15],        r/w,        0x0 */
+            uint32_t rsvd4              : 1; /* [   16],        r/w,        0x0 */
+            uint32_t ef_0_key_enc_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t rsvd5              : 1; /* [   18],        r/w,        0x0 */
+            uint32_t rsvd6              : 1; /* [   19],        r/w,        0x0 */
+            uint32_t rsvd7              : 1; /* [   20],        r/w,        0x0 */
+            uint32_t rsvd8              : 1; /* [   21],        r/w,        0x0 */
+            uint32_t rsvd9              : 1; /* [   22],        r/w,        0x0 */
+            uint32_t rsvd10             : 1; /* [   23],        r/w,        0x0 */
+            uint32_t rsvd11             : 2; /* [25:24],        r/w,        0x0 */
+            uint32_t ef_dbg_jtag_0_dis  : 2; /* [27:26],        r/w,        0x0 */
+            uint32_t ef_dbg_mode        : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_cfg_0;
+
+    /* 0x4 : ef_dbg_pwd_low */
+    union {
+        struct
+        {
+            uint32_t ef_dbg_pwd_low : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_dbg_pwd_low;
+
+    /* 0x8 : ef_dbg_pwd_high */
+    union {
+        struct
+        {
+            uint32_t ef_dbg_pwd_high : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_dbg_pwd_high;
+
+    /* 0xC : ef_ana_trim_0 */
+    union {
+        struct
+        {
+            uint32_t ef_ana_trim_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_ana_trim_0;
+
+    /* 0x10 : ef_sw_usage_0 */
+    union {
+        struct
+        {
+            uint32_t ef_sw_usage_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_sw_usage_0;
+
+    /* 0x14 : ef_wifi_mac_low */
+    union {
+        struct
+        {
+            uint32_t ef_wifi_mac_low : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_wifi_mac_low;
+
+    /* 0x18 : ef_wifi_mac_high */
+    union {
+        struct
+        {
+            uint32_t ef_wifi_mac_high : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_wifi_mac_high;
+
+    /* 0x1C : ef_key_slot_0_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w0;
+
+    /* 0x20 : ef_key_slot_0_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w1;
+
+    /* 0x24 : ef_key_slot_0_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w2;
+
+    /* 0x28 : ef_key_slot_0_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_0_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_0_w3;
+
+    /* 0x2C : ef_key_slot_1_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w0;
+
+    /* 0x30 : ef_key_slot_1_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w1;
+
+    /* 0x34 : ef_key_slot_1_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w2;
+
+    /* 0x38 : ef_key_slot_1_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_1_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_1_w3;
+
+    /* 0x3C : ef_key_slot_2_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w0;
+
+    /* 0x40 : ef_key_slot_2_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w1;
+
+    /* 0x44 : ef_key_slot_2_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w2;
+
+    /* 0x48 : ef_key_slot_2_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_2_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_2_w3;
+
+    /* 0x4C : ef_key_slot_3_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w0;
+
+    /* 0x50 : ef_key_slot_3_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w1;
+
+    /* 0x54 : ef_key_slot_3_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w2;
+
+    /* 0x58 : ef_key_slot_3_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_3_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_3_w3;
+
+    /* 0x5C : ef_key_slot_4_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w0;
+
+    /* 0x60 : ef_key_slot_4_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w1;
+
+    /* 0x64 : ef_key_slot_4_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w2;
+
+    /* 0x68 : ef_key_slot_4_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_4_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_4_w3;
+
+    /* 0x6C : ef_key_slot_5_w0 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w0;
+
+    /* 0x70 : ef_key_slot_5_w1 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w1;
+
+    /* 0x74 : ef_key_slot_5_w2 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w2;
+
+    /* 0x78 : ef_key_slot_5_w3 */
+    union {
+        struct
+        {
+            uint32_t ef_key_slot_5_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } ef_key_slot_5_w3;
+
+    /* 0x7C : EF_DATA_lock */
+    union {
+        struct
+        {
+            uint32_t ef_ana_trim_1        : 13; /* [12: 0],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_4_l : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_5_l : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t wr_lock_boot_mode    : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t wr_lock_dbg_pwd      : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t wr_lock_sw_usage_0   : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t wr_lock_wifi_mac     : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_0   : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_1   : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_2   : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_3   : 1;  /* [   22],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_4_h : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t wr_lock_key_slot_5_h : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t rd_lock_dbg_pwd      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_0   : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_1   : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_2   : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_3   : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_4   : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t rd_lock_key_slot_5   : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } EF_DATA_lock;
+};
+
+typedef volatile struct EF_DATA_reg EF_DATA_reg_t;
+
+#endif /* __EF_DATA_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/glb_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/glb_reg.h
new file mode 100755
index 0000000000..19fd12de59
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/glb_reg.h
@@ -0,0 +1,5498 @@
+/**
+  ******************************************************************************
+  * @file    glb_reg.h
+  * @version V1.2
+  * @date    2020-07-08
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __GLB_REG_H__
+#define __GLB_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : clk_cfg0 */
+#define GLB_CLK_CFG0_OFFSET       (0x0)
+#define GLB_REG_PLL_EN            GLB_REG_PLL_EN
+#define GLB_REG_PLL_EN_POS        (0U)
+#define GLB_REG_PLL_EN_LEN        (1U)
+#define GLB_REG_PLL_EN_MSK        (((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS)
+#define GLB_REG_PLL_EN_UMSK       (~(((1U << GLB_REG_PLL_EN_LEN) - 1) << GLB_REG_PLL_EN_POS))
+#define GLB_REG_FCLK_EN           GLB_REG_FCLK_EN
+#define GLB_REG_FCLK_EN_POS       (1U)
+#define GLB_REG_FCLK_EN_LEN       (1U)
+#define GLB_REG_FCLK_EN_MSK       (((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS)
+#define GLB_REG_FCLK_EN_UMSK      (~(((1U << GLB_REG_FCLK_EN_LEN) - 1) << GLB_REG_FCLK_EN_POS))
+#define GLB_REG_HCLK_EN           GLB_REG_HCLK_EN
+#define GLB_REG_HCLK_EN_POS       (2U)
+#define GLB_REG_HCLK_EN_LEN       (1U)
+#define GLB_REG_HCLK_EN_MSK       (((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS)
+#define GLB_REG_HCLK_EN_UMSK      (~(((1U << GLB_REG_HCLK_EN_LEN) - 1) << GLB_REG_HCLK_EN_POS))
+#define GLB_REG_BCLK_EN           GLB_REG_BCLK_EN
+#define GLB_REG_BCLK_EN_POS       (3U)
+#define GLB_REG_BCLK_EN_LEN       (1U)
+#define GLB_REG_BCLK_EN_MSK       (((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS)
+#define GLB_REG_BCLK_EN_UMSK      (~(((1U << GLB_REG_BCLK_EN_LEN) - 1) << GLB_REG_BCLK_EN_POS))
+#define GLB_REG_PLL_SEL           GLB_REG_PLL_SEL
+#define GLB_REG_PLL_SEL_POS       (4U)
+#define GLB_REG_PLL_SEL_LEN       (2U)
+#define GLB_REG_PLL_SEL_MSK       (((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS)
+#define GLB_REG_PLL_SEL_UMSK      (~(((1U << GLB_REG_PLL_SEL_LEN) - 1) << GLB_REG_PLL_SEL_POS))
+#define GLB_HBN_ROOT_CLK_SEL      GLB_HBN_ROOT_CLK_SEL
+#define GLB_HBN_ROOT_CLK_SEL_POS  (6U)
+#define GLB_HBN_ROOT_CLK_SEL_LEN  (2U)
+#define GLB_HBN_ROOT_CLK_SEL_MSK  (((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS)
+#define GLB_HBN_ROOT_CLK_SEL_UMSK (~(((1U << GLB_HBN_ROOT_CLK_SEL_LEN) - 1) << GLB_HBN_ROOT_CLK_SEL_POS))
+#define GLB_REG_HCLK_DIV          GLB_REG_HCLK_DIV
+#define GLB_REG_HCLK_DIV_POS      (8U)
+#define GLB_REG_HCLK_DIV_LEN      (8U)
+#define GLB_REG_HCLK_DIV_MSK      (((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS)
+#define GLB_REG_HCLK_DIV_UMSK     (~(((1U << GLB_REG_HCLK_DIV_LEN) - 1) << GLB_REG_HCLK_DIV_POS))
+#define GLB_REG_BCLK_DIV          GLB_REG_BCLK_DIV
+#define GLB_REG_BCLK_DIV_POS      (16U)
+#define GLB_REG_BCLK_DIV_LEN      (8U)
+#define GLB_REG_BCLK_DIV_MSK      (((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS)
+#define GLB_REG_BCLK_DIV_UMSK     (~(((1U << GLB_REG_BCLK_DIV_LEN) - 1) << GLB_REG_BCLK_DIV_POS))
+#define GLB_FCLK_SW_STATE         GLB_FCLK_SW_STATE
+#define GLB_FCLK_SW_STATE_POS     (24U)
+#define GLB_FCLK_SW_STATE_LEN     (3U)
+#define GLB_FCLK_SW_STATE_MSK     (((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS)
+#define GLB_FCLK_SW_STATE_UMSK    (~(((1U << GLB_FCLK_SW_STATE_LEN) - 1) << GLB_FCLK_SW_STATE_POS))
+#define GLB_CHIP_RDY              GLB_CHIP_RDY
+#define GLB_CHIP_RDY_POS          (27U)
+#define GLB_CHIP_RDY_LEN          (1U)
+#define GLB_CHIP_RDY_MSK          (((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS)
+#define GLB_CHIP_RDY_UMSK         (~(((1U << GLB_CHIP_RDY_LEN) - 1) << GLB_CHIP_RDY_POS))
+#define GLB_ID                    GLB_ID
+#define GLB_ID_POS                (28U)
+#define GLB_ID_LEN                (4U)
+#define GLB_ID_MSK                (((1U << GLB_ID_LEN) - 1) << GLB_ID_POS)
+#define GLB_ID_UMSK               (~(((1U << GLB_ID_LEN) - 1) << GLB_ID_POS))
+
+/* 0x4 : clk_cfg1 */
+#define GLB_CLK_CFG1_OFFSET              (0x4)
+#define GLB_QDEC_CLK_DIV                 GLB_QDEC_CLK_DIV
+#define GLB_QDEC_CLK_DIV_POS             (0U)
+#define GLB_QDEC_CLK_DIV_LEN             (5U)
+#define GLB_QDEC_CLK_DIV_MSK             (((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS)
+#define GLB_QDEC_CLK_DIV_UMSK            (~(((1U << GLB_QDEC_CLK_DIV_LEN) - 1) << GLB_QDEC_CLK_DIV_POS))
+#define GLB_QDEC_CLK_SEL                 GLB_QDEC_CLK_SEL
+#define GLB_QDEC_CLK_SEL_POS             (7U)
+#define GLB_QDEC_CLK_SEL_LEN             (1U)
+#define GLB_QDEC_CLK_SEL_MSK             (((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS)
+#define GLB_QDEC_CLK_SEL_UMSK            (~(((1U << GLB_QDEC_CLK_SEL_LEN) - 1) << GLB_QDEC_CLK_SEL_POS))
+#define GLB_USB_CLK_EN                   GLB_USB_CLK_EN
+#define GLB_USB_CLK_EN_POS               (8U)
+#define GLB_USB_CLK_EN_LEN               (1U)
+#define GLB_USB_CLK_EN_MSK               (((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS)
+#define GLB_USB_CLK_EN_UMSK              (~(((1U << GLB_USB_CLK_EN_LEN) - 1) << GLB_USB_CLK_EN_POS))
+#define GLB_DLL_48M_DIV_EN               GLB_DLL_48M_DIV_EN
+#define GLB_DLL_48M_DIV_EN_POS           (9U)
+#define GLB_DLL_48M_DIV_EN_LEN           (1U)
+#define GLB_DLL_48M_DIV_EN_MSK           (((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS)
+#define GLB_DLL_48M_DIV_EN_UMSK          (~(((1U << GLB_DLL_48M_DIV_EN_LEN) - 1) << GLB_DLL_48M_DIV_EN_POS))
+#define GLB_REG_I2S_CLK_SEL              GLB_REG_I2S_CLK_SEL
+#define GLB_REG_I2S_CLK_SEL_POS          (12U)
+#define GLB_REG_I2S_CLK_SEL_LEN          (1U)
+#define GLB_REG_I2S_CLK_SEL_MSK          (((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS)
+#define GLB_REG_I2S_CLK_SEL_UMSK         (~(((1U << GLB_REG_I2S_CLK_SEL_LEN) - 1) << GLB_REG_I2S_CLK_SEL_POS))
+#define GLB_REG_I2S0_CLK_EN              GLB_REG_I2S0_CLK_EN
+#define GLB_REG_I2S0_CLK_EN_POS          (13U)
+#define GLB_REG_I2S0_CLK_EN_LEN          (1U)
+#define GLB_REG_I2S0_CLK_EN_MSK          (((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS)
+#define GLB_REG_I2S0_CLK_EN_UMSK         (~(((1U << GLB_REG_I2S0_CLK_EN_LEN) - 1) << GLB_REG_I2S0_CLK_EN_POS))
+#define GLB_REG_I2S_0_REF_CLK_OE         GLB_REG_I2S_0_REF_CLK_OE
+#define GLB_REG_I2S_0_REF_CLK_OE_POS     (14U)
+#define GLB_REG_I2S_0_REF_CLK_OE_LEN     (1U)
+#define GLB_REG_I2S_0_REF_CLK_OE_MSK     (((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS)
+#define GLB_REG_I2S_0_REF_CLK_OE_UMSK    (~(((1U << GLB_REG_I2S_0_REF_CLK_OE_LEN) - 1) << GLB_REG_I2S_0_REF_CLK_OE_POS))
+#define GLB_BLE_CLK_SEL                  GLB_BLE_CLK_SEL
+#define GLB_BLE_CLK_SEL_POS              (16U)
+#define GLB_BLE_CLK_SEL_LEN              (6U)
+#define GLB_BLE_CLK_SEL_MSK              (((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS)
+#define GLB_BLE_CLK_SEL_UMSK             (~(((1U << GLB_BLE_CLK_SEL_LEN) - 1) << GLB_BLE_CLK_SEL_POS))
+#define GLB_BLE_EN                       GLB_BLE_EN
+#define GLB_BLE_EN_POS                   (24U)
+#define GLB_BLE_EN_LEN                   (1U)
+#define GLB_BLE_EN_MSK                   (((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS)
+#define GLB_BLE_EN_UMSK                  (~(((1U << GLB_BLE_EN_LEN) - 1) << GLB_BLE_EN_POS))
+#define GLB_M154_ZBEN                    GLB_M154_ZBEN
+#define GLB_M154_ZBEN_POS                (25U)
+#define GLB_M154_ZBEN_LEN                (1U)
+#define GLB_M154_ZBEN_MSK                (((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS)
+#define GLB_M154_ZBEN_UMSK               (~(((1U << GLB_M154_ZBEN_LEN) - 1) << GLB_M154_ZBEN_POS))
+#define GLB_REG_CAM_REF_CLK_EN           GLB_REG_CAM_REF_CLK_EN
+#define GLB_REG_CAM_REF_CLK_EN_POS       (28U)
+#define GLB_REG_CAM_REF_CLK_EN_LEN       (1U)
+#define GLB_REG_CAM_REF_CLK_EN_MSK       (((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS)
+#define GLB_REG_CAM_REF_CLK_EN_UMSK      (~(((1U << GLB_REG_CAM_REF_CLK_EN_LEN) - 1) << GLB_REG_CAM_REF_CLK_EN_POS))
+#define GLB_REG_CAM_REF_CLK_SRC_SEL      GLB_REG_CAM_REF_CLK_SRC_SEL
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_POS  (29U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_LEN  (1U)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_MSK  (((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS)
+#define GLB_REG_CAM_REF_CLK_SRC_SEL_UMSK (~(((1U << GLB_REG_CAM_REF_CLK_SRC_SEL_LEN) - 1) << GLB_REG_CAM_REF_CLK_SRC_SEL_POS))
+#define GLB_REG_CAM_REF_CLK_DIV          GLB_REG_CAM_REF_CLK_DIV
+#define GLB_REG_CAM_REF_CLK_DIV_POS      (30U)
+#define GLB_REG_CAM_REF_CLK_DIV_LEN      (2U)
+#define GLB_REG_CAM_REF_CLK_DIV_MSK      (((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS)
+#define GLB_REG_CAM_REF_CLK_DIV_UMSK     (~(((1U << GLB_REG_CAM_REF_CLK_DIV_LEN) - 1) << GLB_REG_CAM_REF_CLK_DIV_POS))
+
+/* 0x8 : clk_cfg2 */
+#define GLB_CLK_CFG2_OFFSET       (0x8)
+#define GLB_UART_CLK_DIV          GLB_UART_CLK_DIV
+#define GLB_UART_CLK_DIV_POS      (0U)
+#define GLB_UART_CLK_DIV_LEN      (3U)
+#define GLB_UART_CLK_DIV_MSK      (((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS)
+#define GLB_UART_CLK_DIV_UMSK     (~(((1U << GLB_UART_CLK_DIV_LEN) - 1) << GLB_UART_CLK_DIV_POS))
+#define GLB_UART_CLK_EN           GLB_UART_CLK_EN
+#define GLB_UART_CLK_EN_POS       (4U)
+#define GLB_UART_CLK_EN_LEN       (1U)
+#define GLB_UART_CLK_EN_MSK       (((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS)
+#define GLB_UART_CLK_EN_UMSK      (~(((1U << GLB_UART_CLK_EN_LEN) - 1) << GLB_UART_CLK_EN_POS))
+#define GLB_HBN_UART_CLK_SEL      GLB_HBN_UART_CLK_SEL
+#define GLB_HBN_UART_CLK_SEL_POS  (7U)
+#define GLB_HBN_UART_CLK_SEL_LEN  (1U)
+#define GLB_HBN_UART_CLK_SEL_MSK  (((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS)
+#define GLB_HBN_UART_CLK_SEL_UMSK (~(((1U << GLB_HBN_UART_CLK_SEL_LEN) - 1) << GLB_HBN_UART_CLK_SEL_POS))
+#define GLB_SF_CLK_DIV            GLB_SF_CLK_DIV
+#define GLB_SF_CLK_DIV_POS        (8U)
+#define GLB_SF_CLK_DIV_LEN        (3U)
+#define GLB_SF_CLK_DIV_MSK        (((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS)
+#define GLB_SF_CLK_DIV_UMSK       (~(((1U << GLB_SF_CLK_DIV_LEN) - 1) << GLB_SF_CLK_DIV_POS))
+#define GLB_SF_CLK_EN             GLB_SF_CLK_EN
+#define GLB_SF_CLK_EN_POS         (11U)
+#define GLB_SF_CLK_EN_LEN         (1U)
+#define GLB_SF_CLK_EN_MSK         (((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS)
+#define GLB_SF_CLK_EN_UMSK        (~(((1U << GLB_SF_CLK_EN_LEN) - 1) << GLB_SF_CLK_EN_POS))
+#define GLB_SF_CLK_SEL            GLB_SF_CLK_SEL
+#define GLB_SF_CLK_SEL_POS        (12U)
+#define GLB_SF_CLK_SEL_LEN        (2U)
+#define GLB_SF_CLK_SEL_MSK        (((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS)
+#define GLB_SF_CLK_SEL_UMSK       (~(((1U << GLB_SF_CLK_SEL_LEN) - 1) << GLB_SF_CLK_SEL_POS))
+#define GLB_SF_CLK_SEL2           GLB_SF_CLK_SEL2
+#define GLB_SF_CLK_SEL2_POS       (14U)
+#define GLB_SF_CLK_SEL2_LEN       (2U)
+#define GLB_SF_CLK_SEL2_MSK       (((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS)
+#define GLB_SF_CLK_SEL2_UMSK      (~(((1U << GLB_SF_CLK_SEL2_LEN) - 1) << GLB_SF_CLK_SEL2_POS))
+#define GLB_IR_CLK_DIV            GLB_IR_CLK_DIV
+#define GLB_IR_CLK_DIV_POS        (16U)
+#define GLB_IR_CLK_DIV_LEN        (6U)
+#define GLB_IR_CLK_DIV_MSK        (((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS)
+#define GLB_IR_CLK_DIV_UMSK       (~(((1U << GLB_IR_CLK_DIV_LEN) - 1) << GLB_IR_CLK_DIV_POS))
+#define GLB_IR_CLK_EN             GLB_IR_CLK_EN
+#define GLB_IR_CLK_EN_POS         (23U)
+#define GLB_IR_CLK_EN_LEN         (1U)
+#define GLB_IR_CLK_EN_MSK         (((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS)
+#define GLB_IR_CLK_EN_UMSK        (~(((1U << GLB_IR_CLK_EN_LEN) - 1) << GLB_IR_CLK_EN_POS))
+#define GLB_DMA_CLK_EN            GLB_DMA_CLK_EN
+#define GLB_DMA_CLK_EN_POS        (24U)
+#define GLB_DMA_CLK_EN_LEN        (8U)
+#define GLB_DMA_CLK_EN_MSK        (((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS)
+#define GLB_DMA_CLK_EN_UMSK       (~(((1U << GLB_DMA_CLK_EN_LEN) - 1) << GLB_DMA_CLK_EN_POS))
+
+/* 0xC : clk_cfg3 */
+#define GLB_CLK_CFG3_OFFSET            (0xC)
+#define GLB_SPI_CLK_DIV                GLB_SPI_CLK_DIV
+#define GLB_SPI_CLK_DIV_POS            (0U)
+#define GLB_SPI_CLK_DIV_LEN            (5U)
+#define GLB_SPI_CLK_DIV_MSK            (((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS)
+#define GLB_SPI_CLK_DIV_UMSK           (~(((1U << GLB_SPI_CLK_DIV_LEN) - 1) << GLB_SPI_CLK_DIV_POS))
+#define GLB_CFG_SEL_ETH_REF_CLK_O      GLB_CFG_SEL_ETH_REF_CLK_O
+#define GLB_CFG_SEL_ETH_REF_CLK_O_POS  (5U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_LEN  (1U)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS)
+#define GLB_CFG_SEL_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_SEL_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_SEL_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_REF_CLK_O      GLB_CFG_INV_ETH_REF_CLK_O
+#define GLB_CFG_INV_ETH_REF_CLK_O_POS  (6U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_LEN  (1U)
+#define GLB_CFG_INV_ETH_REF_CLK_O_MSK  (((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS)
+#define GLB_CFG_INV_ETH_REF_CLK_O_UMSK (~(((1U << GLB_CFG_INV_ETH_REF_CLK_O_LEN) - 1) << GLB_CFG_INV_ETH_REF_CLK_O_POS))
+#define GLB_CFG_INV_ETH_TX_CLK         GLB_CFG_INV_ETH_TX_CLK
+#define GLB_CFG_INV_ETH_TX_CLK_POS     (7U)
+#define GLB_CFG_INV_ETH_TX_CLK_LEN     (1U)
+#define GLB_CFG_INV_ETH_TX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS)
+#define GLB_CFG_INV_ETH_TX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_TX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_TX_CLK_POS))
+#define GLB_SPI_CLK_EN                 GLB_SPI_CLK_EN
+#define GLB_SPI_CLK_EN_POS             (8U)
+#define GLB_SPI_CLK_EN_LEN             (1U)
+#define GLB_SPI_CLK_EN_MSK             (((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS)
+#define GLB_SPI_CLK_EN_UMSK            (~(((1U << GLB_SPI_CLK_EN_LEN) - 1) << GLB_SPI_CLK_EN_POS))
+#define GLB_CFG_INV_RF_TEST_CLK_O      GLB_CFG_INV_RF_TEST_CLK_O
+#define GLB_CFG_INV_RF_TEST_CLK_O_POS  (9U)
+#define GLB_CFG_INV_RF_TEST_CLK_O_LEN  (1U)
+#define GLB_CFG_INV_RF_TEST_CLK_O_MSK  (((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS)
+#define GLB_CFG_INV_RF_TEST_CLK_O_UMSK (~(((1U << GLB_CFG_INV_RF_TEST_CLK_O_LEN) - 1) << GLB_CFG_INV_RF_TEST_CLK_O_POS))
+#define GLB_CFG_INV_ETH_RX_CLK         GLB_CFG_INV_ETH_RX_CLK
+#define GLB_CFG_INV_ETH_RX_CLK_POS     (10U)
+#define GLB_CFG_INV_ETH_RX_CLK_LEN     (1U)
+#define GLB_CFG_INV_ETH_RX_CLK_MSK     (((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS)
+#define GLB_CFG_INV_ETH_RX_CLK_UMSK    (~(((1U << GLB_CFG_INV_ETH_RX_CLK_LEN) - 1) << GLB_CFG_INV_ETH_RX_CLK_POS))
+#define GLB_I2C_CLK_DIV                GLB_I2C_CLK_DIV
+#define GLB_I2C_CLK_DIV_POS            (16U)
+#define GLB_I2C_CLK_DIV_LEN            (8U)
+#define GLB_I2C_CLK_DIV_MSK            (((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS)
+#define GLB_I2C_CLK_DIV_UMSK           (~(((1U << GLB_I2C_CLK_DIV_LEN) - 1) << GLB_I2C_CLK_DIV_POS))
+#define GLB_I2C_CLK_EN                 GLB_I2C_CLK_EN
+#define GLB_I2C_CLK_EN_POS             (24U)
+#define GLB_I2C_CLK_EN_LEN             (1U)
+#define GLB_I2C_CLK_EN_MSK             (((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS)
+#define GLB_I2C_CLK_EN_UMSK            (~(((1U << GLB_I2C_CLK_EN_LEN) - 1) << GLB_I2C_CLK_EN_POS))
+#define GLB_CHIP_CLK_OUT_0_SEL         GLB_CHIP_CLK_OUT_0_SEL
+#define GLB_CHIP_CLK_OUT_0_SEL_POS     (28U)
+#define GLB_CHIP_CLK_OUT_0_SEL_LEN     (2U)
+#define GLB_CHIP_CLK_OUT_0_SEL_MSK     (((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS)
+#define GLB_CHIP_CLK_OUT_0_SEL_UMSK    (~(((1U << GLB_CHIP_CLK_OUT_0_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_0_SEL_POS))
+#define GLB_CHIP_CLK_OUT_1_SEL         GLB_CHIP_CLK_OUT_1_SEL
+#define GLB_CHIP_CLK_OUT_1_SEL_POS     (30U)
+#define GLB_CHIP_CLK_OUT_1_SEL_LEN     (2U)
+#define GLB_CHIP_CLK_OUT_1_SEL_MSK     (((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS)
+#define GLB_CHIP_CLK_OUT_1_SEL_UMSK    (~(((1U << GLB_CHIP_CLK_OUT_1_SEL_LEN) - 1) << GLB_CHIP_CLK_OUT_1_SEL_POS))
+
+/* 0x10 : swrst_cfg0 */
+#define GLB_SWRST_CFG0_OFFSET (0x10)
+#define GLB_SWRST_S00         GLB_SWRST_S00
+#define GLB_SWRST_S00_POS     (0U)
+#define GLB_SWRST_S00_LEN     (1U)
+#define GLB_SWRST_S00_MSK     (((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS)
+#define GLB_SWRST_S00_UMSK    (~(((1U << GLB_SWRST_S00_LEN) - 1) << GLB_SWRST_S00_POS))
+#define GLB_SWRST_S01         GLB_SWRST_S01
+#define GLB_SWRST_S01_POS     (1U)
+#define GLB_SWRST_S01_LEN     (1U)
+#define GLB_SWRST_S01_MSK     (((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS)
+#define GLB_SWRST_S01_UMSK    (~(((1U << GLB_SWRST_S01_LEN) - 1) << GLB_SWRST_S01_POS))
+#define GLB_SWRST_S20         GLB_SWRST_S20
+#define GLB_SWRST_S20_POS     (4U)
+#define GLB_SWRST_S20_LEN     (1U)
+#define GLB_SWRST_S20_MSK     (((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS)
+#define GLB_SWRST_S20_UMSK    (~(((1U << GLB_SWRST_S20_LEN) - 1) << GLB_SWRST_S20_POS))
+#define GLB_SWRST_S30         GLB_SWRST_S30
+#define GLB_SWRST_S30_POS     (8U)
+#define GLB_SWRST_S30_LEN     (1U)
+#define GLB_SWRST_S30_MSK     (((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS)
+#define GLB_SWRST_S30_UMSK    (~(((1U << GLB_SWRST_S30_LEN) - 1) << GLB_SWRST_S30_POS))
+
+/* 0x14 : swrst_cfg1 */
+#define GLB_SWRST_CFG1_OFFSET (0x14)
+#define GLB_SWRST_S10         GLB_SWRST_S10
+#define GLB_SWRST_S10_POS     (0U)
+#define GLB_SWRST_S10_LEN     (1U)
+#define GLB_SWRST_S10_MSK     (((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS)
+#define GLB_SWRST_S10_UMSK    (~(((1U << GLB_SWRST_S10_LEN) - 1) << GLB_SWRST_S10_POS))
+#define GLB_SWRST_S11         GLB_SWRST_S11
+#define GLB_SWRST_S11_POS     (1U)
+#define GLB_SWRST_S11_LEN     (1U)
+#define GLB_SWRST_S11_MSK     (((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS)
+#define GLB_SWRST_S11_UMSK    (~(((1U << GLB_SWRST_S11_LEN) - 1) << GLB_SWRST_S11_POS))
+#define GLB_SWRST_S12         GLB_SWRST_S12
+#define GLB_SWRST_S12_POS     (2U)
+#define GLB_SWRST_S12_LEN     (1U)
+#define GLB_SWRST_S12_MSK     (((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS)
+#define GLB_SWRST_S12_UMSK    (~(((1U << GLB_SWRST_S12_LEN) - 1) << GLB_SWRST_S12_POS))
+#define GLB_SWRST_S13         GLB_SWRST_S13
+#define GLB_SWRST_S13_POS     (3U)
+#define GLB_SWRST_S13_LEN     (1U)
+#define GLB_SWRST_S13_MSK     (((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS)
+#define GLB_SWRST_S13_UMSK    (~(((1U << GLB_SWRST_S13_LEN) - 1) << GLB_SWRST_S13_POS))
+#define GLB_SWRST_S14         GLB_SWRST_S14
+#define GLB_SWRST_S14_POS     (4U)
+#define GLB_SWRST_S14_LEN     (1U)
+#define GLB_SWRST_S14_MSK     (((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS)
+#define GLB_SWRST_S14_UMSK    (~(((1U << GLB_SWRST_S14_LEN) - 1) << GLB_SWRST_S14_POS))
+#define GLB_SWRST_S15         GLB_SWRST_S15
+#define GLB_SWRST_S15_POS     (5U)
+#define GLB_SWRST_S15_LEN     (1U)
+#define GLB_SWRST_S15_MSK     (((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS)
+#define GLB_SWRST_S15_UMSK    (~(((1U << GLB_SWRST_S15_LEN) - 1) << GLB_SWRST_S15_POS))
+#define GLB_SWRST_S16         GLB_SWRST_S16
+#define GLB_SWRST_S16_POS     (6U)
+#define GLB_SWRST_S16_LEN     (1U)
+#define GLB_SWRST_S16_MSK     (((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS)
+#define GLB_SWRST_S16_UMSK    (~(((1U << GLB_SWRST_S16_LEN) - 1) << GLB_SWRST_S16_POS))
+#define GLB_SWRST_S17         GLB_SWRST_S17
+#define GLB_SWRST_S17_POS     (7U)
+#define GLB_SWRST_S17_LEN     (1U)
+#define GLB_SWRST_S17_MSK     (((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS)
+#define GLB_SWRST_S17_UMSK    (~(((1U << GLB_SWRST_S17_LEN) - 1) << GLB_SWRST_S17_POS))
+#define GLB_SWRST_S18         GLB_SWRST_S18
+#define GLB_SWRST_S18_POS     (8U)
+#define GLB_SWRST_S18_LEN     (1U)
+#define GLB_SWRST_S18_MSK     (((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS)
+#define GLB_SWRST_S18_UMSK    (~(((1U << GLB_SWRST_S18_LEN) - 1) << GLB_SWRST_S18_POS))
+#define GLB_SWRST_S19         GLB_SWRST_S19
+#define GLB_SWRST_S19_POS     (9U)
+#define GLB_SWRST_S19_LEN     (1U)
+#define GLB_SWRST_S19_MSK     (((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS)
+#define GLB_SWRST_S19_UMSK    (~(((1U << GLB_SWRST_S19_LEN) - 1) << GLB_SWRST_S19_POS))
+#define GLB_SWRST_S1A         GLB_SWRST_S1A
+#define GLB_SWRST_S1A_POS     (10U)
+#define GLB_SWRST_S1A_LEN     (1U)
+#define GLB_SWRST_S1A_MSK     (((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS)
+#define GLB_SWRST_S1A_UMSK    (~(((1U << GLB_SWRST_S1A_LEN) - 1) << GLB_SWRST_S1A_POS))
+#define GLB_SWRST_S1B         GLB_SWRST_S1B
+#define GLB_SWRST_S1B_POS     (11U)
+#define GLB_SWRST_S1B_LEN     (1U)
+#define GLB_SWRST_S1B_MSK     (((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS)
+#define GLB_SWRST_S1B_UMSK    (~(((1U << GLB_SWRST_S1B_LEN) - 1) << GLB_SWRST_S1B_POS))
+#define GLB_SWRST_S1C         GLB_SWRST_S1C
+#define GLB_SWRST_S1C_POS     (12U)
+#define GLB_SWRST_S1C_LEN     (1U)
+#define GLB_SWRST_S1C_MSK     (((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS)
+#define GLB_SWRST_S1C_UMSK    (~(((1U << GLB_SWRST_S1C_LEN) - 1) << GLB_SWRST_S1C_POS))
+#define GLB_SWRST_S1D         GLB_SWRST_S1D
+#define GLB_SWRST_S1D_POS     (13U)
+#define GLB_SWRST_S1D_LEN     (1U)
+#define GLB_SWRST_S1D_MSK     (((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS)
+#define GLB_SWRST_S1D_UMSK    (~(((1U << GLB_SWRST_S1D_LEN) - 1) << GLB_SWRST_S1D_POS))
+#define GLB_SWRST_S1E         GLB_SWRST_S1E
+#define GLB_SWRST_S1E_POS     (14U)
+#define GLB_SWRST_S1E_LEN     (1U)
+#define GLB_SWRST_S1E_MSK     (((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS)
+#define GLB_SWRST_S1E_UMSK    (~(((1U << GLB_SWRST_S1E_LEN) - 1) << GLB_SWRST_S1E_POS))
+#define GLB_SWRST_S1F         GLB_SWRST_S1F
+#define GLB_SWRST_S1F_POS     (15U)
+#define GLB_SWRST_S1F_LEN     (1U)
+#define GLB_SWRST_S1F_MSK     (((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS)
+#define GLB_SWRST_S1F_UMSK    (~(((1U << GLB_SWRST_S1F_LEN) - 1) << GLB_SWRST_S1F_POS))
+#define GLB_SWRST_S1A0        GLB_SWRST_S1A0
+#define GLB_SWRST_S1A0_POS    (16U)
+#define GLB_SWRST_S1A0_LEN    (1U)
+#define GLB_SWRST_S1A0_MSK    (((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS)
+#define GLB_SWRST_S1A0_UMSK   (~(((1U << GLB_SWRST_S1A0_LEN) - 1) << GLB_SWRST_S1A0_POS))
+#define GLB_SWRST_S1A1        GLB_SWRST_S1A1
+#define GLB_SWRST_S1A1_POS    (17U)
+#define GLB_SWRST_S1A1_LEN    (1U)
+#define GLB_SWRST_S1A1_MSK    (((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS)
+#define GLB_SWRST_S1A1_UMSK   (~(((1U << GLB_SWRST_S1A1_LEN) - 1) << GLB_SWRST_S1A1_POS))
+#define GLB_SWRST_S1A2        GLB_SWRST_S1A2
+#define GLB_SWRST_S1A2_POS    (18U)
+#define GLB_SWRST_S1A2_LEN    (1U)
+#define GLB_SWRST_S1A2_MSK    (((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS)
+#define GLB_SWRST_S1A2_UMSK   (~(((1U << GLB_SWRST_S1A2_LEN) - 1) << GLB_SWRST_S1A2_POS))
+#define GLB_SWRST_S1A3        GLB_SWRST_S1A3
+#define GLB_SWRST_S1A3_POS    (19U)
+#define GLB_SWRST_S1A3_LEN    (1U)
+#define GLB_SWRST_S1A3_MSK    (((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS)
+#define GLB_SWRST_S1A3_UMSK   (~(((1U << GLB_SWRST_S1A3_LEN) - 1) << GLB_SWRST_S1A3_POS))
+#define GLB_SWRST_S1A4        GLB_SWRST_S1A4
+#define GLB_SWRST_S1A4_POS    (20U)
+#define GLB_SWRST_S1A4_LEN    (1U)
+#define GLB_SWRST_S1A4_MSK    (((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS)
+#define GLB_SWRST_S1A4_UMSK   (~(((1U << GLB_SWRST_S1A4_LEN) - 1) << GLB_SWRST_S1A4_POS))
+#define GLB_SWRST_S1A5        GLB_SWRST_S1A5
+#define GLB_SWRST_S1A5_POS    (21U)
+#define GLB_SWRST_S1A5_LEN    (1U)
+#define GLB_SWRST_S1A5_MSK    (((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS)
+#define GLB_SWRST_S1A5_UMSK   (~(((1U << GLB_SWRST_S1A5_LEN) - 1) << GLB_SWRST_S1A5_POS))
+#define GLB_SWRST_S1A6        GLB_SWRST_S1A6
+#define GLB_SWRST_S1A6_POS    (22U)
+#define GLB_SWRST_S1A6_LEN    (1U)
+#define GLB_SWRST_S1A6_MSK    (((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS)
+#define GLB_SWRST_S1A6_UMSK   (~(((1U << GLB_SWRST_S1A6_LEN) - 1) << GLB_SWRST_S1A6_POS))
+#define GLB_SWRST_S1A7        GLB_SWRST_S1A7
+#define GLB_SWRST_S1A7_POS    (23U)
+#define GLB_SWRST_S1A7_LEN    (1U)
+#define GLB_SWRST_S1A7_MSK    (((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS)
+#define GLB_SWRST_S1A7_UMSK   (~(((1U << GLB_SWRST_S1A7_LEN) - 1) << GLB_SWRST_S1A7_POS))
+#define GLB_SWRST_S1A8        GLB_SWRST_S1A8
+#define GLB_SWRST_S1A8_POS    (24U)
+#define GLB_SWRST_S1A8_LEN    (1U)
+#define GLB_SWRST_S1A8_MSK    (((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS)
+#define GLB_SWRST_S1A8_UMSK   (~(((1U << GLB_SWRST_S1A8_LEN) - 1) << GLB_SWRST_S1A8_POS))
+#define GLB_SWRST_S1A9        GLB_SWRST_S1A9
+#define GLB_SWRST_S1A9_POS    (25U)
+#define GLB_SWRST_S1A9_LEN    (1U)
+#define GLB_SWRST_S1A9_MSK    (((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS)
+#define GLB_SWRST_S1A9_UMSK   (~(((1U << GLB_SWRST_S1A9_LEN) - 1) << GLB_SWRST_S1A9_POS))
+#define GLB_SWRST_S1AA        GLB_SWRST_S1AA
+#define GLB_SWRST_S1AA_POS    (26U)
+#define GLB_SWRST_S1AA_LEN    (1U)
+#define GLB_SWRST_S1AA_MSK    (((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS)
+#define GLB_SWRST_S1AA_UMSK   (~(((1U << GLB_SWRST_S1AA_LEN) - 1) << GLB_SWRST_S1AA_POS))
+#define GLB_SWRST_S1AB        GLB_SWRST_S1AB
+#define GLB_SWRST_S1AB_POS    (27U)
+#define GLB_SWRST_S1AB_LEN    (1U)
+#define GLB_SWRST_S1AB_MSK    (((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS)
+#define GLB_SWRST_S1AB_UMSK   (~(((1U << GLB_SWRST_S1AB_LEN) - 1) << GLB_SWRST_S1AB_POS))
+#define GLB_SWRST_S1AC        GLB_SWRST_S1AC
+#define GLB_SWRST_S1AC_POS    (28U)
+#define GLB_SWRST_S1AC_LEN    (1U)
+#define GLB_SWRST_S1AC_MSK    (((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS)
+#define GLB_SWRST_S1AC_UMSK   (~(((1U << GLB_SWRST_S1AC_LEN) - 1) << GLB_SWRST_S1AC_POS))
+#define GLB_SWRST_S1AD        GLB_SWRST_S1AD
+#define GLB_SWRST_S1AD_POS    (29U)
+#define GLB_SWRST_S1AD_LEN    (1U)
+#define GLB_SWRST_S1AD_MSK    (((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS)
+#define GLB_SWRST_S1AD_UMSK   (~(((1U << GLB_SWRST_S1AD_LEN) - 1) << GLB_SWRST_S1AD_POS))
+#define GLB_SWRST_S1AE        GLB_SWRST_S1AE
+#define GLB_SWRST_S1AE_POS    (30U)
+#define GLB_SWRST_S1AE_LEN    (1U)
+#define GLB_SWRST_S1AE_MSK    (((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS)
+#define GLB_SWRST_S1AE_UMSK   (~(((1U << GLB_SWRST_S1AE_LEN) - 1) << GLB_SWRST_S1AE_POS))
+
+/* 0x18 : swrst_cfg2 */
+#define GLB_SWRST_CFG2_OFFSET         (0x18)
+#define GLB_REG_CTRL_PWRON_RST        GLB_REG_CTRL_PWRON_RST
+#define GLB_REG_CTRL_PWRON_RST_POS    (0U)
+#define GLB_REG_CTRL_PWRON_RST_LEN    (1U)
+#define GLB_REG_CTRL_PWRON_RST_MSK    (((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS)
+#define GLB_REG_CTRL_PWRON_RST_UMSK   (~(((1U << GLB_REG_CTRL_PWRON_RST_LEN) - 1) << GLB_REG_CTRL_PWRON_RST_POS))
+#define GLB_REG_CTRL_CPU_RESET        GLB_REG_CTRL_CPU_RESET
+#define GLB_REG_CTRL_CPU_RESET_POS    (1U)
+#define GLB_REG_CTRL_CPU_RESET_LEN    (1U)
+#define GLB_REG_CTRL_CPU_RESET_MSK    (((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS)
+#define GLB_REG_CTRL_CPU_RESET_UMSK   (~(((1U << GLB_REG_CTRL_CPU_RESET_LEN) - 1) << GLB_REG_CTRL_CPU_RESET_POS))
+#define GLB_REG_CTRL_SYS_RESET        GLB_REG_CTRL_SYS_RESET
+#define GLB_REG_CTRL_SYS_RESET_POS    (2U)
+#define GLB_REG_CTRL_SYS_RESET_LEN    (1U)
+#define GLB_REG_CTRL_SYS_RESET_MSK    (((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS)
+#define GLB_REG_CTRL_SYS_RESET_UMSK   (~(((1U << GLB_REG_CTRL_SYS_RESET_LEN) - 1) << GLB_REG_CTRL_SYS_RESET_POS))
+#define GLB_REG_CTRL_RESET_DUMMY      GLB_REG_CTRL_RESET_DUMMY
+#define GLB_REG_CTRL_RESET_DUMMY_POS  (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_LEN  (4U)
+#define GLB_REG_CTRL_RESET_DUMMY_MSK  (((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS)
+#define GLB_REG_CTRL_RESET_DUMMY_UMSK (~(((1U << GLB_REG_CTRL_RESET_DUMMY_LEN) - 1) << GLB_REG_CTRL_RESET_DUMMY_POS))
+#define GLB_PKA_CLK_SEL               GLB_PKA_CLK_SEL
+#define GLB_PKA_CLK_SEL_POS           (24U)
+#define GLB_PKA_CLK_SEL_LEN           (1U)
+#define GLB_PKA_CLK_SEL_MSK           (((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS)
+#define GLB_PKA_CLK_SEL_UMSK          (~(((1U << GLB_PKA_CLK_SEL_LEN) - 1) << GLB_PKA_CLK_SEL_POS))
+
+/* 0x1C : swrst_cfg3 */
+#define GLB_SWRST_CFG3_OFFSET (0x1C)
+
+/* 0x20 : cgen_cfg0 */
+#define GLB_CGEN_CFG0_OFFSET (0x20)
+#define GLB_CGEN_M           GLB_CGEN_M
+#define GLB_CGEN_M_POS       (0U)
+#define GLB_CGEN_M_LEN       (8U)
+#define GLB_CGEN_M_MSK       (((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS)
+#define GLB_CGEN_M_UMSK      (~(((1U << GLB_CGEN_M_LEN) - 1) << GLB_CGEN_M_POS))
+
+/* 0x24 : cgen_cfg1 */
+#define GLB_CGEN_CFG1_OFFSET (0x24)
+#define GLB_CGEN_S1          GLB_CGEN_S1
+#define GLB_CGEN_S1_POS      (0U)
+#define GLB_CGEN_S1_LEN      (16U)
+#define GLB_CGEN_S1_MSK      (((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS)
+#define GLB_CGEN_S1_UMSK     (~(((1U << GLB_CGEN_S1_LEN) - 1) << GLB_CGEN_S1_POS))
+#define GLB_CGEN_S1A         GLB_CGEN_S1A
+#define GLB_CGEN_S1A_POS     (16U)
+#define GLB_CGEN_S1A_LEN     (16U)
+#define GLB_CGEN_S1A_MSK     (((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS)
+#define GLB_CGEN_S1A_UMSK    (~(((1U << GLB_CGEN_S1A_LEN) - 1) << GLB_CGEN_S1A_POS))
+
+/* 0x28 : cgen_cfg2 */
+#define GLB_CGEN_CFG2_OFFSET (0x28)
+#define GLB_CGEN_S2          GLB_CGEN_S2
+#define GLB_CGEN_S2_POS      (0U)
+#define GLB_CGEN_S2_LEN      (1U)
+#define GLB_CGEN_S2_MSK      (((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS)
+#define GLB_CGEN_S2_UMSK     (~(((1U << GLB_CGEN_S2_LEN) - 1) << GLB_CGEN_S2_POS))
+#define GLB_CGEN_S3          GLB_CGEN_S3
+#define GLB_CGEN_S3_POS      (4U)
+#define GLB_CGEN_S3_LEN      (1U)
+#define GLB_CGEN_S3_MSK      (((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS)
+#define GLB_CGEN_S3_UMSK     (~(((1U << GLB_CGEN_S3_LEN) - 1) << GLB_CGEN_S3_POS))
+
+/* 0x2C : cgen_cfg3 */
+#define GLB_CGEN_CFG3_OFFSET (0x2C)
+
+/* 0x30 : MBIST_CTL */
+#define GLB_MBIST_CTL_OFFSET            (0x30)
+#define GLB_IROM_MBIST_MODE             GLB_IROM_MBIST_MODE
+#define GLB_IROM_MBIST_MODE_POS         (0U)
+#define GLB_IROM_MBIST_MODE_LEN         (1U)
+#define GLB_IROM_MBIST_MODE_MSK         (((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS)
+#define GLB_IROM_MBIST_MODE_UMSK        (~(((1U << GLB_IROM_MBIST_MODE_LEN) - 1) << GLB_IROM_MBIST_MODE_POS))
+#define GLB_HSRAM_MEM_MBIST_MODE        GLB_HSRAM_MEM_MBIST_MODE
+#define GLB_HSRAM_MEM_MBIST_MODE_POS    (1U)
+#define GLB_HSRAM_MEM_MBIST_MODE_LEN    (1U)
+#define GLB_HSRAM_MEM_MBIST_MODE_MSK    (((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS)
+#define GLB_HSRAM_MEM_MBIST_MODE_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_MODE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_MODE_POS))
+#define GLB_HSRAM_CACHE_MBIST_MODE      GLB_HSRAM_CACHE_MBIST_MODE
+#define GLB_HSRAM_CACHE_MBIST_MODE_POS  (2U)
+#define GLB_HSRAM_CACHE_MBIST_MODE_LEN  (1U)
+#define GLB_HSRAM_CACHE_MBIST_MODE_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS)
+#define GLB_HSRAM_CACHE_MBIST_MODE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_MODE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_MODE_POS))
+#define GLB_TAG_MBIST_MODE              GLB_TAG_MBIST_MODE
+#define GLB_TAG_MBIST_MODE_POS          (3U)
+#define GLB_TAG_MBIST_MODE_LEN          (1U)
+#define GLB_TAG_MBIST_MODE_MSK          (((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS)
+#define GLB_TAG_MBIST_MODE_UMSK         (~(((1U << GLB_TAG_MBIST_MODE_LEN) - 1) << GLB_TAG_MBIST_MODE_POS))
+#define GLB_OCRAM_MBIST_MODE            GLB_OCRAM_MBIST_MODE
+#define GLB_OCRAM_MBIST_MODE_POS        (4U)
+#define GLB_OCRAM_MBIST_MODE_LEN        (1U)
+#define GLB_OCRAM_MBIST_MODE_MSK        (((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS)
+#define GLB_OCRAM_MBIST_MODE_UMSK       (~(((1U << GLB_OCRAM_MBIST_MODE_LEN) - 1) << GLB_OCRAM_MBIST_MODE_POS))
+#define GLB_EM_RAM_MBIST_MODE           GLB_EM_RAM_MBIST_MODE
+#define GLB_EM_RAM_MBIST_MODE_POS       (5U)
+#define GLB_EM_RAM_MBIST_MODE_LEN       (1U)
+#define GLB_EM_RAM_MBIST_MODE_MSK       (((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS)
+#define GLB_EM_RAM_MBIST_MODE_UMSK      (~(((1U << GLB_EM_RAM_MBIST_MODE_LEN) - 1) << GLB_EM_RAM_MBIST_MODE_POS))
+#define GLB_REG_MBIST_RST_N             GLB_REG_MBIST_RST_N
+#define GLB_REG_MBIST_RST_N_POS         (31U)
+#define GLB_REG_MBIST_RST_N_LEN         (1U)
+#define GLB_REG_MBIST_RST_N_MSK         (((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS)
+#define GLB_REG_MBIST_RST_N_UMSK        (~(((1U << GLB_REG_MBIST_RST_N_LEN) - 1) << GLB_REG_MBIST_RST_N_POS))
+
+/* 0x34 : MBIST_STAT */
+#define GLB_MBIST_STAT_OFFSET           (0x34)
+#define GLB_IROM_MBIST_DONE             GLB_IROM_MBIST_DONE
+#define GLB_IROM_MBIST_DONE_POS         (0U)
+#define GLB_IROM_MBIST_DONE_LEN         (1U)
+#define GLB_IROM_MBIST_DONE_MSK         (((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS)
+#define GLB_IROM_MBIST_DONE_UMSK        (~(((1U << GLB_IROM_MBIST_DONE_LEN) - 1) << GLB_IROM_MBIST_DONE_POS))
+#define GLB_HSRAM_MEM_MBIST_DONE        GLB_HSRAM_MEM_MBIST_DONE
+#define GLB_HSRAM_MEM_MBIST_DONE_POS    (1U)
+#define GLB_HSRAM_MEM_MBIST_DONE_LEN    (1U)
+#define GLB_HSRAM_MEM_MBIST_DONE_MSK    (((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS)
+#define GLB_HSRAM_MEM_MBIST_DONE_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_DONE_LEN) - 1) << GLB_HSRAM_MEM_MBIST_DONE_POS))
+#define GLB_HSRAM_CACHE_MBIST_DONE      GLB_HSRAM_CACHE_MBIST_DONE
+#define GLB_HSRAM_CACHE_MBIST_DONE_POS  (2U)
+#define GLB_HSRAM_CACHE_MBIST_DONE_LEN  (1U)
+#define GLB_HSRAM_CACHE_MBIST_DONE_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS)
+#define GLB_HSRAM_CACHE_MBIST_DONE_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_DONE_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_DONE_POS))
+#define GLB_TAG_MBIST_DONE              GLB_TAG_MBIST_DONE
+#define GLB_TAG_MBIST_DONE_POS          (3U)
+#define GLB_TAG_MBIST_DONE_LEN          (1U)
+#define GLB_TAG_MBIST_DONE_MSK          (((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS)
+#define GLB_TAG_MBIST_DONE_UMSK         (~(((1U << GLB_TAG_MBIST_DONE_LEN) - 1) << GLB_TAG_MBIST_DONE_POS))
+#define GLB_OCRAM_MBIST_DONE            GLB_OCRAM_MBIST_DONE
+#define GLB_OCRAM_MBIST_DONE_POS        (4U)
+#define GLB_OCRAM_MBIST_DONE_LEN        (1U)
+#define GLB_OCRAM_MBIST_DONE_MSK        (((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS)
+#define GLB_OCRAM_MBIST_DONE_UMSK       (~(((1U << GLB_OCRAM_MBIST_DONE_LEN) - 1) << GLB_OCRAM_MBIST_DONE_POS))
+#define GLB_EM_RAM_MBIST_DONE           GLB_EM_RAM_MBIST_DONE
+#define GLB_EM_RAM_MBIST_DONE_POS       (5U)
+#define GLB_EM_RAM_MBIST_DONE_LEN       (1U)
+#define GLB_EM_RAM_MBIST_DONE_MSK       (((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS)
+#define GLB_EM_RAM_MBIST_DONE_UMSK      (~(((1U << GLB_EM_RAM_MBIST_DONE_LEN) - 1) << GLB_EM_RAM_MBIST_DONE_POS))
+#define GLB_IROM_MBIST_FAIL             GLB_IROM_MBIST_FAIL
+#define GLB_IROM_MBIST_FAIL_POS         (16U)
+#define GLB_IROM_MBIST_FAIL_LEN         (1U)
+#define GLB_IROM_MBIST_FAIL_MSK         (((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS)
+#define GLB_IROM_MBIST_FAIL_UMSK        (~(((1U << GLB_IROM_MBIST_FAIL_LEN) - 1) << GLB_IROM_MBIST_FAIL_POS))
+#define GLB_HSRAM_MEM_MBIST_FAIL        GLB_HSRAM_MEM_MBIST_FAIL
+#define GLB_HSRAM_MEM_MBIST_FAIL_POS    (17U)
+#define GLB_HSRAM_MEM_MBIST_FAIL_LEN    (1U)
+#define GLB_HSRAM_MEM_MBIST_FAIL_MSK    (((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS)
+#define GLB_HSRAM_MEM_MBIST_FAIL_UMSK   (~(((1U << GLB_HSRAM_MEM_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_MEM_MBIST_FAIL_POS))
+#define GLB_HSRAM_CACHE_MBIST_FAIL      GLB_HSRAM_CACHE_MBIST_FAIL
+#define GLB_HSRAM_CACHE_MBIST_FAIL_POS  (18U)
+#define GLB_HSRAM_CACHE_MBIST_FAIL_LEN  (1U)
+#define GLB_HSRAM_CACHE_MBIST_FAIL_MSK  (((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS)
+#define GLB_HSRAM_CACHE_MBIST_FAIL_UMSK (~(((1U << GLB_HSRAM_CACHE_MBIST_FAIL_LEN) - 1) << GLB_HSRAM_CACHE_MBIST_FAIL_POS))
+#define GLB_TAG_MBIST_FAIL              GLB_TAG_MBIST_FAIL
+#define GLB_TAG_MBIST_FAIL_POS          (19U)
+#define GLB_TAG_MBIST_FAIL_LEN          (1U)
+#define GLB_TAG_MBIST_FAIL_MSK          (((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS)
+#define GLB_TAG_MBIST_FAIL_UMSK         (~(((1U << GLB_TAG_MBIST_FAIL_LEN) - 1) << GLB_TAG_MBIST_FAIL_POS))
+#define GLB_OCRAM_MBIST_FAIL            GLB_OCRAM_MBIST_FAIL
+#define GLB_OCRAM_MBIST_FAIL_POS        (20U)
+#define GLB_OCRAM_MBIST_FAIL_LEN        (1U)
+#define GLB_OCRAM_MBIST_FAIL_MSK        (((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS)
+#define GLB_OCRAM_MBIST_FAIL_UMSK       (~(((1U << GLB_OCRAM_MBIST_FAIL_LEN) - 1) << GLB_OCRAM_MBIST_FAIL_POS))
+#define GLB_EM_RAM_MBIST_FAIL           GLB_EM_RAM_MBIST_FAIL
+#define GLB_EM_RAM_MBIST_FAIL_POS       (21U)
+#define GLB_EM_RAM_MBIST_FAIL_LEN       (1U)
+#define GLB_EM_RAM_MBIST_FAIL_MSK       (((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS)
+#define GLB_EM_RAM_MBIST_FAIL_UMSK      (~(((1U << GLB_EM_RAM_MBIST_FAIL_LEN) - 1) << GLB_EM_RAM_MBIST_FAIL_POS))
+
+/* 0x50 : bmx_cfg1 */
+#define GLB_BMX_CFG1_OFFSET          (0x50)
+#define GLB_BMX_TIMEOUT_EN           GLB_BMX_TIMEOUT_EN
+#define GLB_BMX_TIMEOUT_EN_POS       (0U)
+#define GLB_BMX_TIMEOUT_EN_LEN       (4U)
+#define GLB_BMX_TIMEOUT_EN_MSK       (((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS)
+#define GLB_BMX_TIMEOUT_EN_UMSK      (~(((1U << GLB_BMX_TIMEOUT_EN_LEN) - 1) << GLB_BMX_TIMEOUT_EN_POS))
+#define GLB_BMX_ARB_MODE             GLB_BMX_ARB_MODE
+#define GLB_BMX_ARB_MODE_POS         (4U)
+#define GLB_BMX_ARB_MODE_LEN         (2U)
+#define GLB_BMX_ARB_MODE_MSK         (((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS)
+#define GLB_BMX_ARB_MODE_UMSK        (~(((1U << GLB_BMX_ARB_MODE_LEN) - 1) << GLB_BMX_ARB_MODE_POS))
+#define GLB_BMX_ERR_EN               GLB_BMX_ERR_EN
+#define GLB_BMX_ERR_EN_POS           (8U)
+#define GLB_BMX_ERR_EN_LEN           (1U)
+#define GLB_BMX_ERR_EN_MSK           (((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS)
+#define GLB_BMX_ERR_EN_UMSK          (~(((1U << GLB_BMX_ERR_EN_LEN) - 1) << GLB_BMX_ERR_EN_POS))
+#define GLB_BMX_BUSY_OPTION_DIS      GLB_BMX_BUSY_OPTION_DIS
+#define GLB_BMX_BUSY_OPTION_DIS_POS  (9U)
+#define GLB_BMX_BUSY_OPTION_DIS_LEN  (1U)
+#define GLB_BMX_BUSY_OPTION_DIS_MSK  (((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS)
+#define GLB_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << GLB_BMX_BUSY_OPTION_DIS_LEN) - 1) << GLB_BMX_BUSY_OPTION_DIS_POS))
+#define GLB_BMX_GATING_DIS           GLB_BMX_GATING_DIS
+#define GLB_BMX_GATING_DIS_POS       (10U)
+#define GLB_BMX_GATING_DIS_LEN       (1U)
+#define GLB_BMX_GATING_DIS_MSK       (((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS)
+#define GLB_BMX_GATING_DIS_UMSK      (~(((1U << GLB_BMX_GATING_DIS_LEN) - 1) << GLB_BMX_GATING_DIS_POS))
+#define GLB_HSEL_OPTION              GLB_HSEL_OPTION
+#define GLB_HSEL_OPTION_POS          (12U)
+#define GLB_HSEL_OPTION_LEN          (4U)
+#define GLB_HSEL_OPTION_MSK          (((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS)
+#define GLB_HSEL_OPTION_UMSK         (~(((1U << GLB_HSEL_OPTION_LEN) - 1) << GLB_HSEL_OPTION_POS))
+#define GLB_PDS_APB_CFG              GLB_PDS_APB_CFG
+#define GLB_PDS_APB_CFG_POS          (16U)
+#define GLB_PDS_APB_CFG_LEN          (8U)
+#define GLB_PDS_APB_CFG_MSK          (((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS)
+#define GLB_PDS_APB_CFG_UMSK         (~(((1U << GLB_PDS_APB_CFG_LEN) - 1) << GLB_PDS_APB_CFG_POS))
+#define GLB_HBN_APB_CFG              GLB_HBN_APB_CFG
+#define GLB_HBN_APB_CFG_POS          (24U)
+#define GLB_HBN_APB_CFG_LEN          (8U)
+#define GLB_HBN_APB_CFG_MSK          (((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS)
+#define GLB_HBN_APB_CFG_UMSK         (~(((1U << GLB_HBN_APB_CFG_LEN) - 1) << GLB_HBN_APB_CFG_POS))
+
+/* 0x54 : bmx_cfg2 */
+#define GLB_BMX_CFG2_OFFSET       (0x54)
+#define GLB_BMX_ERR_ADDR_DIS      GLB_BMX_ERR_ADDR_DIS
+#define GLB_BMX_ERR_ADDR_DIS_POS  (0U)
+#define GLB_BMX_ERR_ADDR_DIS_LEN  (1U)
+#define GLB_BMX_ERR_ADDR_DIS_MSK  (((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS)
+#define GLB_BMX_ERR_ADDR_DIS_UMSK (~(((1U << GLB_BMX_ERR_ADDR_DIS_LEN) - 1) << GLB_BMX_ERR_ADDR_DIS_POS))
+#define GLB_BMX_ERR_DEC           GLB_BMX_ERR_DEC
+#define GLB_BMX_ERR_DEC_POS       (4U)
+#define GLB_BMX_ERR_DEC_LEN       (1U)
+#define GLB_BMX_ERR_DEC_MSK       (((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS)
+#define GLB_BMX_ERR_DEC_UMSK      (~(((1U << GLB_BMX_ERR_DEC_LEN) - 1) << GLB_BMX_ERR_DEC_POS))
+#define GLB_BMX_ERR_TZ            GLB_BMX_ERR_TZ
+#define GLB_BMX_ERR_TZ_POS        (5U)
+#define GLB_BMX_ERR_TZ_LEN        (1U)
+#define GLB_BMX_ERR_TZ_MSK        (((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS)
+#define GLB_BMX_ERR_TZ_UMSK       (~(((1U << GLB_BMX_ERR_TZ_LEN) - 1) << GLB_BMX_ERR_TZ_POS))
+#define GLB_REG_W_THRE_BMX        GLB_REG_W_THRE_BMX
+#define GLB_REG_W_THRE_BMX_POS    (8U)
+#define GLB_REG_W_THRE_BMX_LEN    (2U)
+#define GLB_REG_W_THRE_BMX_MSK    (((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS)
+#define GLB_REG_W_THRE_BMX_UMSK   (~(((1U << GLB_REG_W_THRE_BMX_LEN) - 1) << GLB_REG_W_THRE_BMX_POS))
+#define GLB_REG_W_THRE_L1C        GLB_REG_W_THRE_L1C
+#define GLB_REG_W_THRE_L1C_POS    (10U)
+#define GLB_REG_W_THRE_L1C_LEN    (2U)
+#define GLB_REG_W_THRE_L1C_MSK    (((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS)
+#define GLB_REG_W_THRE_L1C_UMSK   (~(((1U << GLB_REG_W_THRE_L1C_LEN) - 1) << GLB_REG_W_THRE_L1C_POS))
+#define GLB_BMX_DBG_SEL           GLB_BMX_DBG_SEL
+#define GLB_BMX_DBG_SEL_POS       (28U)
+#define GLB_BMX_DBG_SEL_LEN       (4U)
+#define GLB_BMX_DBG_SEL_MSK       (((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS)
+#define GLB_BMX_DBG_SEL_UMSK      (~(((1U << GLB_BMX_DBG_SEL_LEN) - 1) << GLB_BMX_DBG_SEL_POS))
+
+/* 0x58 : bmx_err_addr */
+#define GLB_BMX_ERR_ADDR_OFFSET (0x58)
+#define GLB_BMX_ERR_ADDR        GLB_BMX_ERR_ADDR
+#define GLB_BMX_ERR_ADDR_POS    (0U)
+#define GLB_BMX_ERR_ADDR_LEN    (32U)
+#define GLB_BMX_ERR_ADDR_MSK    (((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS)
+#define GLB_BMX_ERR_ADDR_UMSK   (~(((1U << GLB_BMX_ERR_ADDR_LEN) - 1) << GLB_BMX_ERR_ADDR_POS))
+
+/* 0x5C : bmx_dbg_out */
+#define GLB_BMX_DBG_OUT_OFFSET (0x5C)
+#define GLB_BMX_DBG_OUT        GLB_BMX_DBG_OUT
+#define GLB_BMX_DBG_OUT_POS    (0U)
+#define GLB_BMX_DBG_OUT_LEN    (32U)
+#define GLB_BMX_DBG_OUT_MSK    (((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS)
+#define GLB_BMX_DBG_OUT_UMSK   (~(((1U << GLB_BMX_DBG_OUT_LEN) - 1) << GLB_BMX_DBG_OUT_POS))
+
+/* 0x60 : rsv0 */
+#define GLB_RSV0_OFFSET (0x60)
+
+/* 0x64 : rsv1 */
+#define GLB_RSV1_OFFSET (0x64)
+
+/* 0x68 : rsv2 */
+#define GLB_RSV2_OFFSET (0x68)
+
+/* 0x6C : rsv3 */
+#define GLB_RSV3_OFFSET (0x6C)
+
+/* 0x70 : sram_ret */
+#define GLB_SRAM_RET_OFFSET   (0x70)
+#define GLB_REG_SRAM_RET      GLB_REG_SRAM_RET
+#define GLB_REG_SRAM_RET_POS  (0U)
+#define GLB_REG_SRAM_RET_LEN  (32U)
+#define GLB_REG_SRAM_RET_MSK  (((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS)
+#define GLB_REG_SRAM_RET_UMSK (~(((1U << GLB_REG_SRAM_RET_LEN) - 1) << GLB_REG_SRAM_RET_POS))
+
+/* 0x74 : sram_slp */
+#define GLB_SRAM_SLP_OFFSET   (0x74)
+#define GLB_REG_SRAM_SLP      GLB_REG_SRAM_SLP
+#define GLB_REG_SRAM_SLP_POS  (0U)
+#define GLB_REG_SRAM_SLP_LEN  (32U)
+#define GLB_REG_SRAM_SLP_MSK  (((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS)
+#define GLB_REG_SRAM_SLP_UMSK (~(((1U << GLB_REG_SRAM_SLP_LEN) - 1) << GLB_REG_SRAM_SLP_POS))
+
+/* 0x78 : sram_parm */
+#define GLB_SRAM_PARM_OFFSET   (0x78)
+#define GLB_REG_SRAM_PARM      GLB_REG_SRAM_PARM
+#define GLB_REG_SRAM_PARM_POS  (0U)
+#define GLB_REG_SRAM_PARM_LEN  (32U)
+#define GLB_REG_SRAM_PARM_MSK  (((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS)
+#define GLB_REG_SRAM_PARM_UMSK (~(((1U << GLB_REG_SRAM_PARM_LEN) - 1) << GLB_REG_SRAM_PARM_POS))
+
+/* 0x7C : seam_misc */
+#define GLB_SEAM_MISC_OFFSET (0x7C)
+#define GLB_EM_SEL           GLB_EM_SEL
+#define GLB_EM_SEL_POS       (0U)
+#define GLB_EM_SEL_LEN       (4U)
+#define GLB_EM_SEL_MSK       (((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS)
+#define GLB_EM_SEL_UMSK      (~(((1U << GLB_EM_SEL_LEN) - 1) << GLB_EM_SEL_POS))
+
+/* 0x80 : glb_parm */
+#define GLB_PARM_OFFSET                   (0x80)
+#define GLB_JTAG_SWAP_SET                 GLB_JTAG_SWAP_SET
+#define GLB_JTAG_SWAP_SET_POS             (0U)
+#define GLB_JTAG_SWAP_SET_LEN             (8U)
+#define GLB_JTAG_SWAP_SET_MSK             (((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS)
+#define GLB_JTAG_SWAP_SET_UMSK            (~(((1U << GLB_JTAG_SWAP_SET_LEN) - 1) << GLB_JTAG_SWAP_SET_POS))
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3      GLB_CFG_SFLASH2_SWAP_IO0_IO3
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS  (8U)
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN  (1U)
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_MSK  (((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS)
+#define GLB_CFG_SFLASH2_SWAP_IO0_IO3_UMSK (~(((1U << GLB_CFG_SFLASH2_SWAP_IO0_IO3_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_IO0_IO3_POS))
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2       GLB_CFG_SFLASH2_SWAP_CS_IO2
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_POS   (9U)
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN   (1U)
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_MSK   (((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS)
+#define GLB_CFG_SFLASH2_SWAP_CS_IO2_UMSK  (~(((1U << GLB_CFG_SFLASH2_SWAP_CS_IO2_LEN) - 1) << GLB_CFG_SFLASH2_SWAP_CS_IO2_POS))
+#define GLB_CFG_FLASH_SCENARIO            GLB_CFG_FLASH_SCENARIO
+#define GLB_CFG_FLASH_SCENARIO_POS        (10U)
+#define GLB_CFG_FLASH_SCENARIO_LEN        (2U)
+#define GLB_CFG_FLASH_SCENARIO_MSK        (((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS)
+#define GLB_CFG_FLASH_SCENARIO_UMSK       (~(((1U << GLB_CFG_FLASH_SCENARIO_LEN) - 1) << GLB_CFG_FLASH_SCENARIO_POS))
+#define GLB_REG_SPI_0_MASTER_MODE         GLB_REG_SPI_0_MASTER_MODE
+#define GLB_REG_SPI_0_MASTER_MODE_POS     (12U)
+#define GLB_REG_SPI_0_MASTER_MODE_LEN     (1U)
+#define GLB_REG_SPI_0_MASTER_MODE_MSK     (((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS)
+#define GLB_REG_SPI_0_MASTER_MODE_UMSK    (~(((1U << GLB_REG_SPI_0_MASTER_MODE_LEN) - 1) << GLB_REG_SPI_0_MASTER_MODE_POS))
+#define GLB_REG_SPI_0_SWAP                GLB_REG_SPI_0_SWAP
+#define GLB_REG_SPI_0_SWAP_POS            (13U)
+#define GLB_REG_SPI_0_SWAP_LEN            (1U)
+#define GLB_REG_SPI_0_SWAP_MSK            (((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS)
+#define GLB_REG_SPI_0_SWAP_UMSK           (~(((1U << GLB_REG_SPI_0_SWAP_LEN) - 1) << GLB_REG_SPI_0_SWAP_POS))
+#define GLB_REG_CCI_USE_JTAG_PIN          GLB_REG_CCI_USE_JTAG_PIN
+#define GLB_REG_CCI_USE_JTAG_PIN_POS      (16U)
+#define GLB_REG_CCI_USE_JTAG_PIN_LEN      (1U)
+#define GLB_REG_CCI_USE_JTAG_PIN_MSK      (((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS)
+#define GLB_REG_CCI_USE_JTAG_PIN_UMSK     (~(((1U << GLB_REG_CCI_USE_JTAG_PIN_LEN) - 1) << GLB_REG_CCI_USE_JTAG_PIN_POS))
+#define GLB_P1_ADC_TEST_WITH_CCI          GLB_P1_ADC_TEST_WITH_CCI
+#define GLB_P1_ADC_TEST_WITH_CCI_POS      (17U)
+#define GLB_P1_ADC_TEST_WITH_CCI_LEN      (1U)
+#define GLB_P1_ADC_TEST_WITH_CCI_MSK      (((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS)
+#define GLB_P1_ADC_TEST_WITH_CCI_UMSK     (~(((1U << GLB_P1_ADC_TEST_WITH_CCI_LEN) - 1) << GLB_P1_ADC_TEST_WITH_CCI_POS))
+#define GLB_P2_DAC_TEST_WITH_CCI          GLB_P2_DAC_TEST_WITH_CCI
+#define GLB_P2_DAC_TEST_WITH_CCI_POS      (18U)
+#define GLB_P2_DAC_TEST_WITH_CCI_LEN      (1U)
+#define GLB_P2_DAC_TEST_WITH_CCI_MSK      (((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS)
+#define GLB_P2_DAC_TEST_WITH_CCI_UMSK     (~(((1U << GLB_P2_DAC_TEST_WITH_CCI_LEN) - 1) << GLB_P2_DAC_TEST_WITH_CCI_POS))
+#define GLB_P3_CCI_USE_IO_0_2_7           GLB_P3_CCI_USE_IO_0_2_7
+#define GLB_P3_CCI_USE_IO_0_2_7_POS       (19U)
+#define GLB_P3_CCI_USE_IO_0_2_7_LEN       (1U)
+#define GLB_P3_CCI_USE_IO_0_2_7_MSK       (((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS)
+#define GLB_P3_CCI_USE_IO_0_2_7_UMSK      (~(((1U << GLB_P3_CCI_USE_IO_0_2_7_LEN) - 1) << GLB_P3_CCI_USE_IO_0_2_7_POS))
+#define GLB_P4_ADC_TEST_WITH_JTAG         GLB_P4_ADC_TEST_WITH_JTAG
+#define GLB_P4_ADC_TEST_WITH_JTAG_POS     (20U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_LEN     (1U)
+#define GLB_P4_ADC_TEST_WITH_JTAG_MSK     (((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS)
+#define GLB_P4_ADC_TEST_WITH_JTAG_UMSK    (~(((1U << GLB_P4_ADC_TEST_WITH_JTAG_LEN) - 1) << GLB_P4_ADC_TEST_WITH_JTAG_POS))
+#define GLB_P5_DAC_TEST_WITH_JTAG         GLB_P5_DAC_TEST_WITH_JTAG
+#define GLB_P5_DAC_TEST_WITH_JTAG_POS     (21U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_LEN     (1U)
+#define GLB_P5_DAC_TEST_WITH_JTAG_MSK     (((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS)
+#define GLB_P5_DAC_TEST_WITH_JTAG_UMSK    (~(((1U << GLB_P5_DAC_TEST_WITH_JTAG_LEN) - 1) << GLB_P5_DAC_TEST_WITH_JTAG_POS))
+#define GLB_P6_JTAG_USE_IO_0_2_7          GLB_P6_JTAG_USE_IO_0_2_7
+#define GLB_P6_JTAG_USE_IO_0_2_7_POS      (23U)
+#define GLB_P6_JTAG_USE_IO_0_2_7_LEN      (1U)
+#define GLB_P6_JTAG_USE_IO_0_2_7_MSK      (((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS)
+#define GLB_P6_JTAG_USE_IO_0_2_7_UMSK     (~(((1U << GLB_P6_JTAG_USE_IO_0_2_7_LEN) - 1) << GLB_P6_JTAG_USE_IO_0_2_7_POS))
+#define GLB_UART_SWAP_SET                 GLB_UART_SWAP_SET
+#define GLB_UART_SWAP_SET_POS             (24U)
+#define GLB_UART_SWAP_SET_LEN             (4U)
+#define GLB_UART_SWAP_SET_MSK             (((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS)
+#define GLB_UART_SWAP_SET_UMSK            (~(((1U << GLB_UART_SWAP_SET_LEN) - 1) << GLB_UART_SWAP_SET_POS))
+#define GLB_REG_KYS_DRV_VAL               GLB_REG_KYS_DRV_VAL
+#define GLB_REG_KYS_DRV_VAL_POS           (29U)
+#define GLB_REG_KYS_DRV_VAL_LEN           (1U)
+#define GLB_REG_KYS_DRV_VAL_MSK           (((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS)
+#define GLB_REG_KYS_DRV_VAL_UMSK          (~(((1U << GLB_REG_KYS_DRV_VAL_LEN) - 1) << GLB_REG_KYS_DRV_VAL_POS))
+#define GLB_REG_EXT_RST_SMT               GLB_REG_EXT_RST_SMT
+#define GLB_REG_EXT_RST_SMT_POS           (30U)
+#define GLB_REG_EXT_RST_SMT_LEN           (1U)
+#define GLB_REG_EXT_RST_SMT_MSK           (((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS)
+#define GLB_REG_EXT_RST_SMT_UMSK          (~(((1U << GLB_REG_EXT_RST_SMT_LEN) - 1) << GLB_REG_EXT_RST_SMT_POS))
+#define GLB_PIN_SEL_EMAC_CAM              GLB_PIN_SEL_EMAC_CAM
+#define GLB_PIN_SEL_EMAC_CAM_POS          (31U)
+#define GLB_PIN_SEL_EMAC_CAM_LEN          (1U)
+#define GLB_PIN_SEL_EMAC_CAM_MSK          (((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS)
+#define GLB_PIN_SEL_EMAC_CAM_UMSK         (~(((1U << GLB_PIN_SEL_EMAC_CAM_LEN) - 1) << GLB_PIN_SEL_EMAC_CAM_POS))
+
+/* 0x84 : PDM_CLK_CTRL */
+#define GLB_PDM_CLK_CTRL_OFFSET   (0x84)
+#define GLB_REG_PDM0_CLK_DIV      GLB_REG_PDM0_CLK_DIV
+#define GLB_REG_PDM0_CLK_DIV_POS  (0U)
+#define GLB_REG_PDM0_CLK_DIV_LEN  (6U)
+#define GLB_REG_PDM0_CLK_DIV_MSK  (((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS)
+#define GLB_REG_PDM0_CLK_DIV_UMSK (~(((1U << GLB_REG_PDM0_CLK_DIV_LEN) - 1) << GLB_REG_PDM0_CLK_DIV_POS))
+#define GLB_REG_PDM0_CLK_EN       GLB_REG_PDM0_CLK_EN
+#define GLB_REG_PDM0_CLK_EN_POS   (7U)
+#define GLB_REG_PDM0_CLK_EN_LEN   (1U)
+#define GLB_REG_PDM0_CLK_EN_MSK   (((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS)
+#define GLB_REG_PDM0_CLK_EN_UMSK  (~(((1U << GLB_REG_PDM0_CLK_EN_LEN) - 1) << GLB_REG_PDM0_CLK_EN_POS))
+
+/* 0x88 : GPIO_USE_PSRAM__IO */
+#define GLB_GPIO_USE_PSRAM__IO_OFFSET  (0x88)
+#define GLB_CFG_GPIO_USE_PSRAM_IO      GLB_CFG_GPIO_USE_PSRAM_IO
+#define GLB_CFG_GPIO_USE_PSRAM_IO_POS  (0U)
+#define GLB_CFG_GPIO_USE_PSRAM_IO_LEN  (6U)
+#define GLB_CFG_GPIO_USE_PSRAM_IO_MSK  (((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS)
+#define GLB_CFG_GPIO_USE_PSRAM_IO_UMSK (~(((1U << GLB_CFG_GPIO_USE_PSRAM_IO_LEN) - 1) << GLB_CFG_GPIO_USE_PSRAM_IO_POS))
+
+/* 0x90 : CPU_CLK_CFG */
+#define GLB_CPU_CLK_CFG_OFFSET      (0x90)
+#define GLB_CPU_RTC_DIV             GLB_CPU_RTC_DIV
+#define GLB_CPU_RTC_DIV_POS         (0U)
+#define GLB_CPU_RTC_DIV_LEN         (17U)
+#define GLB_CPU_RTC_DIV_MSK         (((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS)
+#define GLB_CPU_RTC_DIV_UMSK        (~(((1U << GLB_CPU_RTC_DIV_LEN) - 1) << GLB_CPU_RTC_DIV_POS))
+#define GLB_CPU_RTC_EN              GLB_CPU_RTC_EN
+#define GLB_CPU_RTC_EN_POS          (18U)
+#define GLB_CPU_RTC_EN_LEN          (1U)
+#define GLB_CPU_RTC_EN_MSK          (((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS)
+#define GLB_CPU_RTC_EN_UMSK         (~(((1U << GLB_CPU_RTC_EN_LEN) - 1) << GLB_CPU_RTC_EN_POS))
+#define GLB_CPU_RTC_SEL             GLB_CPU_RTC_SEL
+#define GLB_CPU_RTC_SEL_POS         (19U)
+#define GLB_CPU_RTC_SEL_LEN         (1U)
+#define GLB_CPU_RTC_SEL_MSK         (((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS)
+#define GLB_CPU_RTC_SEL_UMSK        (~(((1U << GLB_CPU_RTC_SEL_LEN) - 1) << GLB_CPU_RTC_SEL_POS))
+#define GLB_DEBUG_NDRESET_GATE      GLB_DEBUG_NDRESET_GATE
+#define GLB_DEBUG_NDRESET_GATE_POS  (20U)
+#define GLB_DEBUG_NDRESET_GATE_LEN  (1U)
+#define GLB_DEBUG_NDRESET_GATE_MSK  (((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS)
+#define GLB_DEBUG_NDRESET_GATE_UMSK (~(((1U << GLB_DEBUG_NDRESET_GATE_LEN) - 1) << GLB_DEBUG_NDRESET_GATE_POS))
+
+/* 0xA4 : GPADC_32M_SRC_CTRL */
+#define GLB_GPADC_32M_SRC_CTRL_OFFSET (0xA4)
+#define GLB_GPADC_32M_CLK_DIV         GLB_GPADC_32M_CLK_DIV
+#define GLB_GPADC_32M_CLK_DIV_POS     (0U)
+#define GLB_GPADC_32M_CLK_DIV_LEN     (6U)
+#define GLB_GPADC_32M_CLK_DIV_MSK     (((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS)
+#define GLB_GPADC_32M_CLK_DIV_UMSK    (~(((1U << GLB_GPADC_32M_CLK_DIV_LEN) - 1) << GLB_GPADC_32M_CLK_DIV_POS))
+#define GLB_GPADC_32M_CLK_SEL         GLB_GPADC_32M_CLK_SEL
+#define GLB_GPADC_32M_CLK_SEL_POS     (7U)
+#define GLB_GPADC_32M_CLK_SEL_LEN     (1U)
+#define GLB_GPADC_32M_CLK_SEL_MSK     (((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS)
+#define GLB_GPADC_32M_CLK_SEL_UMSK    (~(((1U << GLB_GPADC_32M_CLK_SEL_LEN) - 1) << GLB_GPADC_32M_CLK_SEL_POS))
+#define GLB_GPADC_32M_DIV_EN          GLB_GPADC_32M_DIV_EN
+#define GLB_GPADC_32M_DIV_EN_POS      (8U)
+#define GLB_GPADC_32M_DIV_EN_LEN      (1U)
+#define GLB_GPADC_32M_DIV_EN_MSK      (((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS)
+#define GLB_GPADC_32M_DIV_EN_UMSK     (~(((1U << GLB_GPADC_32M_DIV_EN_LEN) - 1) << GLB_GPADC_32M_DIV_EN_POS))
+
+/* 0xA8 : DIG32K_WAKEUP_CTRL */
+#define GLB_DIG32K_WAKEUP_CTRL_OFFSET   (0xA8)
+#define GLB_DIG_32K_DIV                 GLB_DIG_32K_DIV
+#define GLB_DIG_32K_DIV_POS             (0U)
+#define GLB_DIG_32K_DIV_LEN             (11U)
+#define GLB_DIG_32K_DIV_MSK             (((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS)
+#define GLB_DIG_32K_DIV_UMSK            (~(((1U << GLB_DIG_32K_DIV_LEN) - 1) << GLB_DIG_32K_DIV_POS))
+#define GLB_DIG_32K_EN                  GLB_DIG_32K_EN
+#define GLB_DIG_32K_EN_POS              (12U)
+#define GLB_DIG_32K_EN_LEN              (1U)
+#define GLB_DIG_32K_EN_MSK              (((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS)
+#define GLB_DIG_32K_EN_UMSK             (~(((1U << GLB_DIG_32K_EN_LEN) - 1) << GLB_DIG_32K_EN_POS))
+#define GLB_DIG_32K_COMP                GLB_DIG_32K_COMP
+#define GLB_DIG_32K_COMP_POS            (13U)
+#define GLB_DIG_32K_COMP_LEN            (1U)
+#define GLB_DIG_32K_COMP_MSK            (((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS)
+#define GLB_DIG_32K_COMP_UMSK           (~(((1U << GLB_DIG_32K_COMP_LEN) - 1) << GLB_DIG_32K_COMP_POS))
+#define GLB_DIG_512K_DIV                GLB_DIG_512K_DIV
+#define GLB_DIG_512K_DIV_POS            (16U)
+#define GLB_DIG_512K_DIV_LEN            (7U)
+#define GLB_DIG_512K_DIV_MSK            (((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS)
+#define GLB_DIG_512K_DIV_UMSK           (~(((1U << GLB_DIG_512K_DIV_LEN) - 1) << GLB_DIG_512K_DIV_POS))
+#define GLB_DIG_512K_EN                 GLB_DIG_512K_EN
+#define GLB_DIG_512K_EN_POS             (24U)
+#define GLB_DIG_512K_EN_LEN             (1U)
+#define GLB_DIG_512K_EN_MSK             (((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS)
+#define GLB_DIG_512K_EN_UMSK            (~(((1U << GLB_DIG_512K_EN_LEN) - 1) << GLB_DIG_512K_EN_POS))
+#define GLB_DIG_512K_COMP               GLB_DIG_512K_COMP
+#define GLB_DIG_512K_COMP_POS           (25U)
+#define GLB_DIG_512K_COMP_LEN           (1U)
+#define GLB_DIG_512K_COMP_MSK           (((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS)
+#define GLB_DIG_512K_COMP_UMSK          (~(((1U << GLB_DIG_512K_COMP_LEN) - 1) << GLB_DIG_512K_COMP_POS))
+#define GLB_DIG_CLK_SRC_SEL             GLB_DIG_CLK_SRC_SEL
+#define GLB_DIG_CLK_SRC_SEL_POS         (28U)
+#define GLB_DIG_CLK_SRC_SEL_LEN         (2U)
+#define GLB_DIG_CLK_SRC_SEL_MSK         (((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS)
+#define GLB_DIG_CLK_SRC_SEL_UMSK        (~(((1U << GLB_DIG_CLK_SRC_SEL_LEN) - 1) << GLB_DIG_CLK_SRC_SEL_POS))
+#define GLB_REG_EN_PLATFORM_WAKEUP      GLB_REG_EN_PLATFORM_WAKEUP
+#define GLB_REG_EN_PLATFORM_WAKEUP_POS  (31U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_LEN  (1U)
+#define GLB_REG_EN_PLATFORM_WAKEUP_MSK  (((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS)
+#define GLB_REG_EN_PLATFORM_WAKEUP_UMSK (~(((1U << GLB_REG_EN_PLATFORM_WAKEUP_LEN) - 1) << GLB_REG_EN_PLATFORM_WAKEUP_POS))
+
+/* 0xAC : WIFI_BT_COEX_CTRL */
+#define GLB_WIFI_BT_COEX_CTRL_OFFSET (0xAC)
+#define GLB_COEX_BT_CHANNEL          GLB_COEX_BT_CHANNEL
+#define GLB_COEX_BT_CHANNEL_POS      (0U)
+#define GLB_COEX_BT_CHANNEL_LEN      (7U)
+#define GLB_COEX_BT_CHANNEL_MSK      (((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS)
+#define GLB_COEX_BT_CHANNEL_UMSK     (~(((1U << GLB_COEX_BT_CHANNEL_LEN) - 1) << GLB_COEX_BT_CHANNEL_POS))
+#define GLB_COEX_BT_PTI              GLB_COEX_BT_PTI
+#define GLB_COEX_BT_PTI_POS          (7U)
+#define GLB_COEX_BT_PTI_LEN          (4U)
+#define GLB_COEX_BT_PTI_MSK          (((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS)
+#define GLB_COEX_BT_PTI_UMSK         (~(((1U << GLB_COEX_BT_PTI_LEN) - 1) << GLB_COEX_BT_PTI_POS))
+#define GLB_COEX_BT_BW               GLB_COEX_BT_BW
+#define GLB_COEX_BT_BW_POS           (11U)
+#define GLB_COEX_BT_BW_LEN           (1U)
+#define GLB_COEX_BT_BW_MSK           (((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS)
+#define GLB_COEX_BT_BW_UMSK          (~(((1U << GLB_COEX_BT_BW_LEN) - 1) << GLB_COEX_BT_BW_POS))
+#define GLB_EN_GPIO_BT_COEX          GLB_EN_GPIO_BT_COEX
+#define GLB_EN_GPIO_BT_COEX_POS      (12U)
+#define GLB_EN_GPIO_BT_COEX_LEN      (1U)
+#define GLB_EN_GPIO_BT_COEX_MSK      (((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS)
+#define GLB_EN_GPIO_BT_COEX_UMSK     (~(((1U << GLB_EN_GPIO_BT_COEX_LEN) - 1) << GLB_EN_GPIO_BT_COEX_POS))
+
+/* 0xB0 : BZ_COEX_CTRL */
+#define GLB_BZ_COEX_CTRL_OFFSET    (0xB0)
+#define GLB_COEX_EN                GLB_COEX_EN
+#define GLB_COEX_EN_POS            (0U)
+#define GLB_COEX_EN_LEN            (1U)
+#define GLB_COEX_EN_MSK            (((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS)
+#define GLB_COEX_EN_UMSK           (~(((1U << GLB_COEX_EN_LEN) - 1) << GLB_COEX_EN_POS))
+#define GLB_WLAN_EN                GLB_WLAN_EN
+#define GLB_WLAN_EN_POS            (1U)
+#define GLB_WLAN_EN_LEN            (1U)
+#define GLB_WLAN_EN_MSK            (((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS)
+#define GLB_WLAN_EN_UMSK           (~(((1U << GLB_WLAN_EN_LEN) - 1) << GLB_WLAN_EN_POS))
+#define GLB_BLE_RX_IGNORE          GLB_BLE_RX_IGNORE
+#define GLB_BLE_RX_IGNORE_POS      (2U)
+#define GLB_BLE_RX_IGNORE_LEN      (1U)
+#define GLB_BLE_RX_IGNORE_MSK      (((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS)
+#define GLB_BLE_RX_IGNORE_UMSK     (~(((1U << GLB_BLE_RX_IGNORE_LEN) - 1) << GLB_BLE_RX_IGNORE_POS))
+#define GLB_M154_RX_IGNORE         GLB_M154_RX_IGNORE
+#define GLB_M154_RX_IGNORE_POS     (3U)
+#define GLB_M154_RX_IGNORE_LEN     (1U)
+#define GLB_M154_RX_IGNORE_MSK     (((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS)
+#define GLB_M154_RX_IGNORE_UMSK    (~(((1U << GLB_M154_RX_IGNORE_LEN) - 1) << GLB_M154_RX_IGNORE_POS))
+#define GLB_BZ_PRI_THR             GLB_BZ_PRI_THR
+#define GLB_BZ_PRI_THR_POS         (4U)
+#define GLB_BZ_PRI_THR_LEN         (4U)
+#define GLB_BZ_PRI_THR_MSK         (((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS)
+#define GLB_BZ_PRI_THR_UMSK        (~(((1U << GLB_BZ_PRI_THR_LEN) - 1) << GLB_BZ_PRI_THR_POS))
+#define GLB_BZ_PRI_EN              GLB_BZ_PRI_EN
+#define GLB_BZ_PRI_EN_POS          (8U)
+#define GLB_BZ_PRI_EN_LEN          (1U)
+#define GLB_BZ_PRI_EN_MSK          (((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS)
+#define GLB_BZ_PRI_EN_UMSK         (~(((1U << GLB_BZ_PRI_EN_LEN) - 1) << GLB_BZ_PRI_EN_POS))
+#define GLB_BZ_PRI_POL             GLB_BZ_PRI_POL
+#define GLB_BZ_PRI_POL_POS         (9U)
+#define GLB_BZ_PRI_POL_LEN         (1U)
+#define GLB_BZ_PRI_POL_MSK         (((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS)
+#define GLB_BZ_PRI_POL_UMSK        (~(((1U << GLB_BZ_PRI_POL_LEN) - 1) << GLB_BZ_PRI_POL_POS))
+#define GLB_BZ_ACTIVE_POL          GLB_BZ_ACTIVE_POL
+#define GLB_BZ_ACTIVE_POL_POS      (10U)
+#define GLB_BZ_ACTIVE_POL_LEN      (1U)
+#define GLB_BZ_ACTIVE_POL_MSK      (((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS)
+#define GLB_BZ_ACTIVE_POL_UMSK     (~(((1U << GLB_BZ_ACTIVE_POL_LEN) - 1) << GLB_BZ_ACTIVE_POL_POS))
+#define GLB_BZ_ABORT_POL           GLB_BZ_ABORT_POL
+#define GLB_BZ_ABORT_POL_POS       (11U)
+#define GLB_BZ_ABORT_POL_LEN       (1U)
+#define GLB_BZ_ABORT_POL_MSK       (((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS)
+#define GLB_BZ_ABORT_POL_UMSK      (~(((1U << GLB_BZ_ABORT_POL_LEN) - 1) << GLB_BZ_ABORT_POL_POS))
+#define GLB_COEX_PRI               GLB_COEX_PRI
+#define GLB_COEX_PRI_POS           (12U)
+#define GLB_COEX_PRI_LEN           (1U)
+#define GLB_COEX_PRI_MSK           (((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS)
+#define GLB_COEX_PRI_UMSK          (~(((1U << GLB_COEX_PRI_LEN) - 1) << GLB_COEX_PRI_POS))
+#define GLB_FORCE_M154_WIN         GLB_FORCE_M154_WIN
+#define GLB_FORCE_M154_WIN_POS     (13U)
+#define GLB_FORCE_M154_WIN_LEN     (1U)
+#define GLB_FORCE_M154_WIN_MSK     (((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS)
+#define GLB_FORCE_M154_WIN_UMSK    (~(((1U << GLB_FORCE_M154_WIN_LEN) - 1) << GLB_FORCE_M154_WIN_POS))
+#define GLB_FORCE_BLE_WIN          GLB_FORCE_BLE_WIN
+#define GLB_FORCE_BLE_WIN_POS      (14U)
+#define GLB_FORCE_BLE_WIN_LEN      (1U)
+#define GLB_FORCE_BLE_WIN_MSK      (((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS)
+#define GLB_FORCE_BLE_WIN_UMSK     (~(((1U << GLB_FORCE_BLE_WIN_LEN) - 1) << GLB_FORCE_BLE_WIN_POS))
+#define GLB_COEX_OPTION            GLB_COEX_OPTION
+#define GLB_COEX_OPTION_POS        (15U)
+#define GLB_COEX_OPTION_LEN        (1U)
+#define GLB_COEX_OPTION_MSK        (((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS)
+#define GLB_COEX_OPTION_UMSK       (~(((1U << GLB_COEX_OPTION_LEN) - 1) << GLB_COEX_OPTION_POS))
+#define GLB_COEX_FORCE_CH          GLB_COEX_FORCE_CH
+#define GLB_COEX_FORCE_CH_POS      (16U)
+#define GLB_COEX_FORCE_CH_LEN      (7U)
+#define GLB_COEX_FORCE_CH_MSK      (((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS)
+#define GLB_COEX_FORCE_CH_UMSK     (~(((1U << GLB_COEX_FORCE_CH_LEN) - 1) << GLB_COEX_FORCE_CH_POS))
+#define GLB_M154_RX_ABORT_DIS      GLB_M154_RX_ABORT_DIS
+#define GLB_M154_RX_ABORT_DIS_POS  (24U)
+#define GLB_M154_RX_ABORT_DIS_LEN  (1U)
+#define GLB_M154_RX_ABORT_DIS_MSK  (((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS)
+#define GLB_M154_RX_ABORT_DIS_UMSK (~(((1U << GLB_M154_RX_ABORT_DIS_LEN) - 1) << GLB_M154_RX_ABORT_DIS_POS))
+#define GLB_M154_TX_ABORT_DIS      GLB_M154_TX_ABORT_DIS
+#define GLB_M154_TX_ABORT_DIS_POS  (25U)
+#define GLB_M154_TX_ABORT_DIS_LEN  (1U)
+#define GLB_M154_TX_ABORT_DIS_MSK  (((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS)
+#define GLB_M154_TX_ABORT_DIS_UMSK (~(((1U << GLB_M154_TX_ABORT_DIS_LEN) - 1) << GLB_M154_TX_ABORT_DIS_POS))
+#define GLB_BLE_RX_ABORT_DIS       GLB_BLE_RX_ABORT_DIS
+#define GLB_BLE_RX_ABORT_DIS_POS   (26U)
+#define GLB_BLE_RX_ABORT_DIS_LEN   (1U)
+#define GLB_BLE_RX_ABORT_DIS_MSK   (((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS)
+#define GLB_BLE_RX_ABORT_DIS_UMSK  (~(((1U << GLB_BLE_RX_ABORT_DIS_LEN) - 1) << GLB_BLE_RX_ABORT_DIS_POS))
+#define GLB_BLE_TX_ABORT_DIS       GLB_BLE_TX_ABORT_DIS
+#define GLB_BLE_TX_ABORT_DIS_POS   (27U)
+#define GLB_BLE_TX_ABORT_DIS_LEN   (1U)
+#define GLB_BLE_TX_ABORT_DIS_MSK   (((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS)
+#define GLB_BLE_TX_ABORT_DIS_UMSK  (~(((1U << GLB_BLE_TX_ABORT_DIS_LEN) - 1) << GLB_BLE_TX_ABORT_DIS_POS))
+#define GLB_COEX_ARB               GLB_COEX_ARB
+#define GLB_COEX_ARB_POS           (28U)
+#define GLB_COEX_ARB_LEN           (4U)
+#define GLB_COEX_ARB_MSK           (((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS)
+#define GLB_COEX_ARB_UMSK          (~(((1U << GLB_COEX_ARB_LEN) - 1) << GLB_COEX_ARB_POS))
+
+/* 0xC0 : UART_SIG_SEL_0 */
+#define GLB_UART_SIG_SEL_0_OFFSET (0xC0)
+#define GLB_UART_SIG_0_SEL        GLB_UART_SIG_0_SEL
+#define GLB_UART_SIG_0_SEL_POS    (0U)
+#define GLB_UART_SIG_0_SEL_LEN    (4U)
+#define GLB_UART_SIG_0_SEL_MSK    (((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS)
+#define GLB_UART_SIG_0_SEL_UMSK   (~(((1U << GLB_UART_SIG_0_SEL_LEN) - 1) << GLB_UART_SIG_0_SEL_POS))
+#define GLB_UART_SIG_1_SEL        GLB_UART_SIG_1_SEL
+#define GLB_UART_SIG_1_SEL_POS    (4U)
+#define GLB_UART_SIG_1_SEL_LEN    (4U)
+#define GLB_UART_SIG_1_SEL_MSK    (((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS)
+#define GLB_UART_SIG_1_SEL_UMSK   (~(((1U << GLB_UART_SIG_1_SEL_LEN) - 1) << GLB_UART_SIG_1_SEL_POS))
+#define GLB_UART_SIG_2_SEL        GLB_UART_SIG_2_SEL
+#define GLB_UART_SIG_2_SEL_POS    (8U)
+#define GLB_UART_SIG_2_SEL_LEN    (4U)
+#define GLB_UART_SIG_2_SEL_MSK    (((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS)
+#define GLB_UART_SIG_2_SEL_UMSK   (~(((1U << GLB_UART_SIG_2_SEL_LEN) - 1) << GLB_UART_SIG_2_SEL_POS))
+#define GLB_UART_SIG_3_SEL        GLB_UART_SIG_3_SEL
+#define GLB_UART_SIG_3_SEL_POS    (12U)
+#define GLB_UART_SIG_3_SEL_LEN    (4U)
+#define GLB_UART_SIG_3_SEL_MSK    (((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS)
+#define GLB_UART_SIG_3_SEL_UMSK   (~(((1U << GLB_UART_SIG_3_SEL_LEN) - 1) << GLB_UART_SIG_3_SEL_POS))
+#define GLB_UART_SIG_4_SEL        GLB_UART_SIG_4_SEL
+#define GLB_UART_SIG_4_SEL_POS    (16U)
+#define GLB_UART_SIG_4_SEL_LEN    (4U)
+#define GLB_UART_SIG_4_SEL_MSK    (((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS)
+#define GLB_UART_SIG_4_SEL_UMSK   (~(((1U << GLB_UART_SIG_4_SEL_LEN) - 1) << GLB_UART_SIG_4_SEL_POS))
+#define GLB_UART_SIG_5_SEL        GLB_UART_SIG_5_SEL
+#define GLB_UART_SIG_5_SEL_POS    (20U)
+#define GLB_UART_SIG_5_SEL_LEN    (4U)
+#define GLB_UART_SIG_5_SEL_MSK    (((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS)
+#define GLB_UART_SIG_5_SEL_UMSK   (~(((1U << GLB_UART_SIG_5_SEL_LEN) - 1) << GLB_UART_SIG_5_SEL_POS))
+#define GLB_UART_SIG_6_SEL        GLB_UART_SIG_6_SEL
+#define GLB_UART_SIG_6_SEL_POS    (24U)
+#define GLB_UART_SIG_6_SEL_LEN    (4U)
+#define GLB_UART_SIG_6_SEL_MSK    (((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS)
+#define GLB_UART_SIG_6_SEL_UMSK   (~(((1U << GLB_UART_SIG_6_SEL_LEN) - 1) << GLB_UART_SIG_6_SEL_POS))
+#define GLB_UART_SIG_7_SEL        GLB_UART_SIG_7_SEL
+#define GLB_UART_SIG_7_SEL_POS    (28U)
+#define GLB_UART_SIG_7_SEL_LEN    (4U)
+#define GLB_UART_SIG_7_SEL_MSK    (((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS)
+#define GLB_UART_SIG_7_SEL_UMSK   (~(((1U << GLB_UART_SIG_7_SEL_LEN) - 1) << GLB_UART_SIG_7_SEL_POS))
+
+/* 0xD0 : DBG_SEL_LL */
+#define GLB_DBG_SEL_LL_OFFSET    (0xD0)
+#define GLB_REG_DBG_LL_CTRL      GLB_REG_DBG_LL_CTRL
+#define GLB_REG_DBG_LL_CTRL_POS  (0U)
+#define GLB_REG_DBG_LL_CTRL_LEN  (32U)
+#define GLB_REG_DBG_LL_CTRL_MSK  (((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS)
+#define GLB_REG_DBG_LL_CTRL_UMSK (~(((1U << GLB_REG_DBG_LL_CTRL_LEN) - 1) << GLB_REG_DBG_LL_CTRL_POS))
+
+/* 0xD4 : DBG_SEL_LH */
+#define GLB_DBG_SEL_LH_OFFSET    (0xD4)
+#define GLB_REG_DBG_LH_CTRL      GLB_REG_DBG_LH_CTRL
+#define GLB_REG_DBG_LH_CTRL_POS  (0U)
+#define GLB_REG_DBG_LH_CTRL_LEN  (32U)
+#define GLB_REG_DBG_LH_CTRL_MSK  (((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS)
+#define GLB_REG_DBG_LH_CTRL_UMSK (~(((1U << GLB_REG_DBG_LH_CTRL_LEN) - 1) << GLB_REG_DBG_LH_CTRL_POS))
+
+/* 0xD8 : DBG_SEL_HL */
+#define GLB_DBG_SEL_HL_OFFSET    (0xD8)
+#define GLB_REG_DBG_HL_CTRL      GLB_REG_DBG_HL_CTRL
+#define GLB_REG_DBG_HL_CTRL_POS  (0U)
+#define GLB_REG_DBG_HL_CTRL_LEN  (32U)
+#define GLB_REG_DBG_HL_CTRL_MSK  (((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS)
+#define GLB_REG_DBG_HL_CTRL_UMSK (~(((1U << GLB_REG_DBG_HL_CTRL_LEN) - 1) << GLB_REG_DBG_HL_CTRL_POS))
+
+/* 0xDC : DBG_SEL_HH */
+#define GLB_DBG_SEL_HH_OFFSET    (0xDC)
+#define GLB_REG_DBG_HH_CTRL      GLB_REG_DBG_HH_CTRL
+#define GLB_REG_DBG_HH_CTRL_POS  (0U)
+#define GLB_REG_DBG_HH_CTRL_LEN  (32U)
+#define GLB_REG_DBG_HH_CTRL_MSK  (((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS)
+#define GLB_REG_DBG_HH_CTRL_UMSK (~(((1U << GLB_REG_DBG_HH_CTRL_LEN) - 1) << GLB_REG_DBG_HH_CTRL_POS))
+
+/* 0xE0 : debug */
+#define GLB_DEBUG_OFFSET  (0xE0)
+#define GLB_DEBUG_OE      GLB_DEBUG_OE
+#define GLB_DEBUG_OE_POS  (0U)
+#define GLB_DEBUG_OE_LEN  (1U)
+#define GLB_DEBUG_OE_MSK  (((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS)
+#define GLB_DEBUG_OE_UMSK (~(((1U << GLB_DEBUG_OE_LEN) - 1) << GLB_DEBUG_OE_POS))
+#define GLB_DEBUG_I       GLB_DEBUG_I
+#define GLB_DEBUG_I_POS   (1U)
+#define GLB_DEBUG_I_LEN   (31U)
+#define GLB_DEBUG_I_MSK   (((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS)
+#define GLB_DEBUG_I_UMSK  (~(((1U << GLB_DEBUG_I_LEN) - 1) << GLB_DEBUG_I_POS))
+
+/* 0x100 : GPIO_CFGCTL0 */
+#define GLB_GPIO_CFGCTL0_OFFSET      (0x100)
+#define GLB_REG_GPIO_0_IE            GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS        (0U)
+#define GLB_REG_GPIO_0_IE_LEN        (1U)
+#define GLB_REG_GPIO_0_IE_MSK        (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK       (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT           GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS       (1U)
+#define GLB_REG_GPIO_0_SMT_LEN       (1U)
+#define GLB_REG_GPIO_0_SMT_MSK       (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK      (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV           GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS       (2U)
+#define GLB_REG_GPIO_0_DRV_LEN       (2U)
+#define GLB_REG_GPIO_0_DRV_MSK       (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK      (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU            GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS        (4U)
+#define GLB_REG_GPIO_0_PU_LEN        (1U)
+#define GLB_REG_GPIO_0_PU_MSK        (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK       (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD            GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS        (5U)
+#define GLB_REG_GPIO_0_PD_LEN        (1U)
+#define GLB_REG_GPIO_0_PD_MSK        (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK       (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL      GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE            GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS        (16U)
+#define GLB_REG_GPIO_1_IE_LEN        (1U)
+#define GLB_REG_GPIO_1_IE_MSK        (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK       (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT           GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS       (17U)
+#define GLB_REG_GPIO_1_SMT_LEN       (1U)
+#define GLB_REG_GPIO_1_SMT_MSK       (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK      (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV           GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS       (18U)
+#define GLB_REG_GPIO_1_DRV_LEN       (2U)
+#define GLB_REG_GPIO_1_DRV_MSK       (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK      (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU            GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS        (20U)
+#define GLB_REG_GPIO_1_PU_LEN        (1U)
+#define GLB_REG_GPIO_1_PU_MSK        (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK       (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD            GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS        (21U)
+#define GLB_REG_GPIO_1_PD_LEN        (1U)
+#define GLB_REG_GPIO_1_PD_MSK        (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK       (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL      GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+
+/* 0x104 : GPIO_CFGCTL1 */
+#define GLB_GPIO_CFGCTL1_OFFSET      (0x104)
+#define GLB_REG_GPIO_2_IE            GLB_REG_GPIO_2_IE
+#define GLB_REG_GPIO_2_IE_POS        (0U)
+#define GLB_REG_GPIO_2_IE_LEN        (1U)
+#define GLB_REG_GPIO_2_IE_MSK        (((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS)
+#define GLB_REG_GPIO_2_IE_UMSK       (~(((1U << GLB_REG_GPIO_2_IE_LEN) - 1) << GLB_REG_GPIO_2_IE_POS))
+#define GLB_REG_GPIO_2_SMT           GLB_REG_GPIO_2_SMT
+#define GLB_REG_GPIO_2_SMT_POS       (1U)
+#define GLB_REG_GPIO_2_SMT_LEN       (1U)
+#define GLB_REG_GPIO_2_SMT_MSK       (((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS)
+#define GLB_REG_GPIO_2_SMT_UMSK      (~(((1U << GLB_REG_GPIO_2_SMT_LEN) - 1) << GLB_REG_GPIO_2_SMT_POS))
+#define GLB_REG_GPIO_2_DRV           GLB_REG_GPIO_2_DRV
+#define GLB_REG_GPIO_2_DRV_POS       (2U)
+#define GLB_REG_GPIO_2_DRV_LEN       (2U)
+#define GLB_REG_GPIO_2_DRV_MSK       (((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS)
+#define GLB_REG_GPIO_2_DRV_UMSK      (~(((1U << GLB_REG_GPIO_2_DRV_LEN) - 1) << GLB_REG_GPIO_2_DRV_POS))
+#define GLB_REG_GPIO_2_PU            GLB_REG_GPIO_2_PU
+#define GLB_REG_GPIO_2_PU_POS        (4U)
+#define GLB_REG_GPIO_2_PU_LEN        (1U)
+#define GLB_REG_GPIO_2_PU_MSK        (((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS)
+#define GLB_REG_GPIO_2_PU_UMSK       (~(((1U << GLB_REG_GPIO_2_PU_LEN) - 1) << GLB_REG_GPIO_2_PU_POS))
+#define GLB_REG_GPIO_2_PD            GLB_REG_GPIO_2_PD
+#define GLB_REG_GPIO_2_PD_POS        (5U)
+#define GLB_REG_GPIO_2_PD_LEN        (1U)
+#define GLB_REG_GPIO_2_PD_MSK        (((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS)
+#define GLB_REG_GPIO_2_PD_UMSK       (~(((1U << GLB_REG_GPIO_2_PD_LEN) - 1) << GLB_REG_GPIO_2_PD_POS))
+#define GLB_REG_GPIO_2_FUNC_SEL      GLB_REG_GPIO_2_FUNC_SEL
+#define GLB_REG_GPIO_2_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_2_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_2_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS)
+#define GLB_REG_GPIO_2_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_2_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_2_FUNC_SEL_POS))
+#define GLB_REG_GPIO_3_IE            GLB_REG_GPIO_3_IE
+#define GLB_REG_GPIO_3_IE_POS        (16U)
+#define GLB_REG_GPIO_3_IE_LEN        (1U)
+#define GLB_REG_GPIO_3_IE_MSK        (((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS)
+#define GLB_REG_GPIO_3_IE_UMSK       (~(((1U << GLB_REG_GPIO_3_IE_LEN) - 1) << GLB_REG_GPIO_3_IE_POS))
+#define GLB_REG_GPIO_3_SMT           GLB_REG_GPIO_3_SMT
+#define GLB_REG_GPIO_3_SMT_POS       (17U)
+#define GLB_REG_GPIO_3_SMT_LEN       (1U)
+#define GLB_REG_GPIO_3_SMT_MSK       (((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS)
+#define GLB_REG_GPIO_3_SMT_UMSK      (~(((1U << GLB_REG_GPIO_3_SMT_LEN) - 1) << GLB_REG_GPIO_3_SMT_POS))
+#define GLB_REG_GPIO_3_DRV           GLB_REG_GPIO_3_DRV
+#define GLB_REG_GPIO_3_DRV_POS       (18U)
+#define GLB_REG_GPIO_3_DRV_LEN       (2U)
+#define GLB_REG_GPIO_3_DRV_MSK       (((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS)
+#define GLB_REG_GPIO_3_DRV_UMSK      (~(((1U << GLB_REG_GPIO_3_DRV_LEN) - 1) << GLB_REG_GPIO_3_DRV_POS))
+#define GLB_REG_GPIO_3_PU            GLB_REG_GPIO_3_PU
+#define GLB_REG_GPIO_3_PU_POS        (20U)
+#define GLB_REG_GPIO_3_PU_LEN        (1U)
+#define GLB_REG_GPIO_3_PU_MSK        (((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS)
+#define GLB_REG_GPIO_3_PU_UMSK       (~(((1U << GLB_REG_GPIO_3_PU_LEN) - 1) << GLB_REG_GPIO_3_PU_POS))
+#define GLB_REG_GPIO_3_PD            GLB_REG_GPIO_3_PD
+#define GLB_REG_GPIO_3_PD_POS        (21U)
+#define GLB_REG_GPIO_3_PD_LEN        (1U)
+#define GLB_REG_GPIO_3_PD_MSK        (((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS)
+#define GLB_REG_GPIO_3_PD_UMSK       (~(((1U << GLB_REG_GPIO_3_PD_LEN) - 1) << GLB_REG_GPIO_3_PD_POS))
+#define GLB_REG_GPIO_3_FUNC_SEL      GLB_REG_GPIO_3_FUNC_SEL
+#define GLB_REG_GPIO_3_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_3_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_3_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS)
+#define GLB_REG_GPIO_3_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_3_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_3_FUNC_SEL_POS))
+
+/* 0x108 : GPIO_CFGCTL2 */
+#define GLB_GPIO_CFGCTL2_OFFSET      (0x108)
+#define GLB_REG_GPIO_4_IE            GLB_REG_GPIO_4_IE
+#define GLB_REG_GPIO_4_IE_POS        (0U)
+#define GLB_REG_GPIO_4_IE_LEN        (1U)
+#define GLB_REG_GPIO_4_IE_MSK        (((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS)
+#define GLB_REG_GPIO_4_IE_UMSK       (~(((1U << GLB_REG_GPIO_4_IE_LEN) - 1) << GLB_REG_GPIO_4_IE_POS))
+#define GLB_REG_GPIO_4_SMT           GLB_REG_GPIO_4_SMT
+#define GLB_REG_GPIO_4_SMT_POS       (1U)
+#define GLB_REG_GPIO_4_SMT_LEN       (1U)
+#define GLB_REG_GPIO_4_SMT_MSK       (((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS)
+#define GLB_REG_GPIO_4_SMT_UMSK      (~(((1U << GLB_REG_GPIO_4_SMT_LEN) - 1) << GLB_REG_GPIO_4_SMT_POS))
+#define GLB_REG_GPIO_4_DRV           GLB_REG_GPIO_4_DRV
+#define GLB_REG_GPIO_4_DRV_POS       (2U)
+#define GLB_REG_GPIO_4_DRV_LEN       (2U)
+#define GLB_REG_GPIO_4_DRV_MSK       (((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS)
+#define GLB_REG_GPIO_4_DRV_UMSK      (~(((1U << GLB_REG_GPIO_4_DRV_LEN) - 1) << GLB_REG_GPIO_4_DRV_POS))
+#define GLB_REG_GPIO_4_PU            GLB_REG_GPIO_4_PU
+#define GLB_REG_GPIO_4_PU_POS        (4U)
+#define GLB_REG_GPIO_4_PU_LEN        (1U)
+#define GLB_REG_GPIO_4_PU_MSK        (((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS)
+#define GLB_REG_GPIO_4_PU_UMSK       (~(((1U << GLB_REG_GPIO_4_PU_LEN) - 1) << GLB_REG_GPIO_4_PU_POS))
+#define GLB_REG_GPIO_4_PD            GLB_REG_GPIO_4_PD
+#define GLB_REG_GPIO_4_PD_POS        (5U)
+#define GLB_REG_GPIO_4_PD_LEN        (1U)
+#define GLB_REG_GPIO_4_PD_MSK        (((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS)
+#define GLB_REG_GPIO_4_PD_UMSK       (~(((1U << GLB_REG_GPIO_4_PD_LEN) - 1) << GLB_REG_GPIO_4_PD_POS))
+#define GLB_REG_GPIO_4_FUNC_SEL      GLB_REG_GPIO_4_FUNC_SEL
+#define GLB_REG_GPIO_4_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_4_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_4_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS)
+#define GLB_REG_GPIO_4_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_4_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_4_FUNC_SEL_POS))
+#define GLB_REG_GPIO_5_IE            GLB_REG_GPIO_5_IE
+#define GLB_REG_GPIO_5_IE_POS        (16U)
+#define GLB_REG_GPIO_5_IE_LEN        (1U)
+#define GLB_REG_GPIO_5_IE_MSK        (((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS)
+#define GLB_REG_GPIO_5_IE_UMSK       (~(((1U << GLB_REG_GPIO_5_IE_LEN) - 1) << GLB_REG_GPIO_5_IE_POS))
+#define GLB_REG_GPIO_5_SMT           GLB_REG_GPIO_5_SMT
+#define GLB_REG_GPIO_5_SMT_POS       (17U)
+#define GLB_REG_GPIO_5_SMT_LEN       (1U)
+#define GLB_REG_GPIO_5_SMT_MSK       (((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS)
+#define GLB_REG_GPIO_5_SMT_UMSK      (~(((1U << GLB_REG_GPIO_5_SMT_LEN) - 1) << GLB_REG_GPIO_5_SMT_POS))
+#define GLB_REG_GPIO_5_DRV           GLB_REG_GPIO_5_DRV
+#define GLB_REG_GPIO_5_DRV_POS       (18U)
+#define GLB_REG_GPIO_5_DRV_LEN       (2U)
+#define GLB_REG_GPIO_5_DRV_MSK       (((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS)
+#define GLB_REG_GPIO_5_DRV_UMSK      (~(((1U << GLB_REG_GPIO_5_DRV_LEN) - 1) << GLB_REG_GPIO_5_DRV_POS))
+#define GLB_REG_GPIO_5_PU            GLB_REG_GPIO_5_PU
+#define GLB_REG_GPIO_5_PU_POS        (20U)
+#define GLB_REG_GPIO_5_PU_LEN        (1U)
+#define GLB_REG_GPIO_5_PU_MSK        (((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS)
+#define GLB_REG_GPIO_5_PU_UMSK       (~(((1U << GLB_REG_GPIO_5_PU_LEN) - 1) << GLB_REG_GPIO_5_PU_POS))
+#define GLB_REG_GPIO_5_PD            GLB_REG_GPIO_5_PD
+#define GLB_REG_GPIO_5_PD_POS        (21U)
+#define GLB_REG_GPIO_5_PD_LEN        (1U)
+#define GLB_REG_GPIO_5_PD_MSK        (((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS)
+#define GLB_REG_GPIO_5_PD_UMSK       (~(((1U << GLB_REG_GPIO_5_PD_LEN) - 1) << GLB_REG_GPIO_5_PD_POS))
+#define GLB_REG_GPIO_5_FUNC_SEL      GLB_REG_GPIO_5_FUNC_SEL
+#define GLB_REG_GPIO_5_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_5_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_5_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS)
+#define GLB_REG_GPIO_5_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_5_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_5_FUNC_SEL_POS))
+
+/* 0x10C : GPIO_CFGCTL3 */
+#define GLB_GPIO_CFGCTL3_OFFSET      (0x10C)
+#define GLB_REG_GPIO_6_IE            GLB_REG_GPIO_6_IE
+#define GLB_REG_GPIO_6_IE_POS        (0U)
+#define GLB_REG_GPIO_6_IE_LEN        (1U)
+#define GLB_REG_GPIO_6_IE_MSK        (((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS)
+#define GLB_REG_GPIO_6_IE_UMSK       (~(((1U << GLB_REG_GPIO_6_IE_LEN) - 1) << GLB_REG_GPIO_6_IE_POS))
+#define GLB_REG_GPIO_6_SMT           GLB_REG_GPIO_6_SMT
+#define GLB_REG_GPIO_6_SMT_POS       (1U)
+#define GLB_REG_GPIO_6_SMT_LEN       (1U)
+#define GLB_REG_GPIO_6_SMT_MSK       (((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS)
+#define GLB_REG_GPIO_6_SMT_UMSK      (~(((1U << GLB_REG_GPIO_6_SMT_LEN) - 1) << GLB_REG_GPIO_6_SMT_POS))
+#define GLB_REG_GPIO_6_DRV           GLB_REG_GPIO_6_DRV
+#define GLB_REG_GPIO_6_DRV_POS       (2U)
+#define GLB_REG_GPIO_6_DRV_LEN       (2U)
+#define GLB_REG_GPIO_6_DRV_MSK       (((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS)
+#define GLB_REG_GPIO_6_DRV_UMSK      (~(((1U << GLB_REG_GPIO_6_DRV_LEN) - 1) << GLB_REG_GPIO_6_DRV_POS))
+#define GLB_REG_GPIO_6_PU            GLB_REG_GPIO_6_PU
+#define GLB_REG_GPIO_6_PU_POS        (4U)
+#define GLB_REG_GPIO_6_PU_LEN        (1U)
+#define GLB_REG_GPIO_6_PU_MSK        (((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS)
+#define GLB_REG_GPIO_6_PU_UMSK       (~(((1U << GLB_REG_GPIO_6_PU_LEN) - 1) << GLB_REG_GPIO_6_PU_POS))
+#define GLB_REG_GPIO_6_PD            GLB_REG_GPIO_6_PD
+#define GLB_REG_GPIO_6_PD_POS        (5U)
+#define GLB_REG_GPIO_6_PD_LEN        (1U)
+#define GLB_REG_GPIO_6_PD_MSK        (((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS)
+#define GLB_REG_GPIO_6_PD_UMSK       (~(((1U << GLB_REG_GPIO_6_PD_LEN) - 1) << GLB_REG_GPIO_6_PD_POS))
+#define GLB_REG_GPIO_6_FUNC_SEL      GLB_REG_GPIO_6_FUNC_SEL
+#define GLB_REG_GPIO_6_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_6_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_6_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS)
+#define GLB_REG_GPIO_6_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_6_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_6_FUNC_SEL_POS))
+#define GLB_REG_GPIO_7_IE            GLB_REG_GPIO_7_IE
+#define GLB_REG_GPIO_7_IE_POS        (16U)
+#define GLB_REG_GPIO_7_IE_LEN        (1U)
+#define GLB_REG_GPIO_7_IE_MSK        (((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS)
+#define GLB_REG_GPIO_7_IE_UMSK       (~(((1U << GLB_REG_GPIO_7_IE_LEN) - 1) << GLB_REG_GPIO_7_IE_POS))
+#define GLB_REG_GPIO_7_SMT           GLB_REG_GPIO_7_SMT
+#define GLB_REG_GPIO_7_SMT_POS       (17U)
+#define GLB_REG_GPIO_7_SMT_LEN       (1U)
+#define GLB_REG_GPIO_7_SMT_MSK       (((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS)
+#define GLB_REG_GPIO_7_SMT_UMSK      (~(((1U << GLB_REG_GPIO_7_SMT_LEN) - 1) << GLB_REG_GPIO_7_SMT_POS))
+#define GLB_REG_GPIO_7_DRV           GLB_REG_GPIO_7_DRV
+#define GLB_REG_GPIO_7_DRV_POS       (18U)
+#define GLB_REG_GPIO_7_DRV_LEN       (2U)
+#define GLB_REG_GPIO_7_DRV_MSK       (((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS)
+#define GLB_REG_GPIO_7_DRV_UMSK      (~(((1U << GLB_REG_GPIO_7_DRV_LEN) - 1) << GLB_REG_GPIO_7_DRV_POS))
+#define GLB_REG_GPIO_7_PU            GLB_REG_GPIO_7_PU
+#define GLB_REG_GPIO_7_PU_POS        (20U)
+#define GLB_REG_GPIO_7_PU_LEN        (1U)
+#define GLB_REG_GPIO_7_PU_MSK        (((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS)
+#define GLB_REG_GPIO_7_PU_UMSK       (~(((1U << GLB_REG_GPIO_7_PU_LEN) - 1) << GLB_REG_GPIO_7_PU_POS))
+#define GLB_REG_GPIO_7_PD            GLB_REG_GPIO_7_PD
+#define GLB_REG_GPIO_7_PD_POS        (21U)
+#define GLB_REG_GPIO_7_PD_LEN        (1U)
+#define GLB_REG_GPIO_7_PD_MSK        (((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS)
+#define GLB_REG_GPIO_7_PD_UMSK       (~(((1U << GLB_REG_GPIO_7_PD_LEN) - 1) << GLB_REG_GPIO_7_PD_POS))
+#define GLB_REG_GPIO_7_FUNC_SEL      GLB_REG_GPIO_7_FUNC_SEL
+#define GLB_REG_GPIO_7_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_7_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_7_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS)
+#define GLB_REG_GPIO_7_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_7_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_7_FUNC_SEL_POS))
+
+/* 0x110 : GPIO_CFGCTL4 */
+#define GLB_GPIO_CFGCTL4_OFFSET      (0x110)
+#define GLB_REG_GPIO_8_IE            GLB_REG_GPIO_8_IE
+#define GLB_REG_GPIO_8_IE_POS        (0U)
+#define GLB_REG_GPIO_8_IE_LEN        (1U)
+#define GLB_REG_GPIO_8_IE_MSK        (((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS)
+#define GLB_REG_GPIO_8_IE_UMSK       (~(((1U << GLB_REG_GPIO_8_IE_LEN) - 1) << GLB_REG_GPIO_8_IE_POS))
+#define GLB_REG_GPIO_8_SMT           GLB_REG_GPIO_8_SMT
+#define GLB_REG_GPIO_8_SMT_POS       (1U)
+#define GLB_REG_GPIO_8_SMT_LEN       (1U)
+#define GLB_REG_GPIO_8_SMT_MSK       (((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS)
+#define GLB_REG_GPIO_8_SMT_UMSK      (~(((1U << GLB_REG_GPIO_8_SMT_LEN) - 1) << GLB_REG_GPIO_8_SMT_POS))
+#define GLB_REG_GPIO_8_DRV           GLB_REG_GPIO_8_DRV
+#define GLB_REG_GPIO_8_DRV_POS       (2U)
+#define GLB_REG_GPIO_8_DRV_LEN       (2U)
+#define GLB_REG_GPIO_8_DRV_MSK       (((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS)
+#define GLB_REG_GPIO_8_DRV_UMSK      (~(((1U << GLB_REG_GPIO_8_DRV_LEN) - 1) << GLB_REG_GPIO_8_DRV_POS))
+#define GLB_REG_GPIO_8_PU            GLB_REG_GPIO_8_PU
+#define GLB_REG_GPIO_8_PU_POS        (4U)
+#define GLB_REG_GPIO_8_PU_LEN        (1U)
+#define GLB_REG_GPIO_8_PU_MSK        (((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS)
+#define GLB_REG_GPIO_8_PU_UMSK       (~(((1U << GLB_REG_GPIO_8_PU_LEN) - 1) << GLB_REG_GPIO_8_PU_POS))
+#define GLB_REG_GPIO_8_PD            GLB_REG_GPIO_8_PD
+#define GLB_REG_GPIO_8_PD_POS        (5U)
+#define GLB_REG_GPIO_8_PD_LEN        (1U)
+#define GLB_REG_GPIO_8_PD_MSK        (((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS)
+#define GLB_REG_GPIO_8_PD_UMSK       (~(((1U << GLB_REG_GPIO_8_PD_LEN) - 1) << GLB_REG_GPIO_8_PD_POS))
+#define GLB_REG_GPIO_8_FUNC_SEL      GLB_REG_GPIO_8_FUNC_SEL
+#define GLB_REG_GPIO_8_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_8_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_8_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS)
+#define GLB_REG_GPIO_8_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_8_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_8_FUNC_SEL_POS))
+#define GLB_REG_GPIO_9_IE            GLB_REG_GPIO_9_IE
+#define GLB_REG_GPIO_9_IE_POS        (16U)
+#define GLB_REG_GPIO_9_IE_LEN        (1U)
+#define GLB_REG_GPIO_9_IE_MSK        (((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS)
+#define GLB_REG_GPIO_9_IE_UMSK       (~(((1U << GLB_REG_GPIO_9_IE_LEN) - 1) << GLB_REG_GPIO_9_IE_POS))
+#define GLB_REG_GPIO_9_SMT           GLB_REG_GPIO_9_SMT
+#define GLB_REG_GPIO_9_SMT_POS       (17U)
+#define GLB_REG_GPIO_9_SMT_LEN       (1U)
+#define GLB_REG_GPIO_9_SMT_MSK       (((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS)
+#define GLB_REG_GPIO_9_SMT_UMSK      (~(((1U << GLB_REG_GPIO_9_SMT_LEN) - 1) << GLB_REG_GPIO_9_SMT_POS))
+#define GLB_REG_GPIO_9_DRV           GLB_REG_GPIO_9_DRV
+#define GLB_REG_GPIO_9_DRV_POS       (18U)
+#define GLB_REG_GPIO_9_DRV_LEN       (2U)
+#define GLB_REG_GPIO_9_DRV_MSK       (((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS)
+#define GLB_REG_GPIO_9_DRV_UMSK      (~(((1U << GLB_REG_GPIO_9_DRV_LEN) - 1) << GLB_REG_GPIO_9_DRV_POS))
+#define GLB_REG_GPIO_9_PU            GLB_REG_GPIO_9_PU
+#define GLB_REG_GPIO_9_PU_POS        (20U)
+#define GLB_REG_GPIO_9_PU_LEN        (1U)
+#define GLB_REG_GPIO_9_PU_MSK        (((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS)
+#define GLB_REG_GPIO_9_PU_UMSK       (~(((1U << GLB_REG_GPIO_9_PU_LEN) - 1) << GLB_REG_GPIO_9_PU_POS))
+#define GLB_REG_GPIO_9_PD            GLB_REG_GPIO_9_PD
+#define GLB_REG_GPIO_9_PD_POS        (21U)
+#define GLB_REG_GPIO_9_PD_LEN        (1U)
+#define GLB_REG_GPIO_9_PD_MSK        (((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS)
+#define GLB_REG_GPIO_9_PD_UMSK       (~(((1U << GLB_REG_GPIO_9_PD_LEN) - 1) << GLB_REG_GPIO_9_PD_POS))
+#define GLB_REG_GPIO_9_FUNC_SEL      GLB_REG_GPIO_9_FUNC_SEL
+#define GLB_REG_GPIO_9_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_9_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_9_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS)
+#define GLB_REG_GPIO_9_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_9_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_9_FUNC_SEL_POS))
+
+/* 0x114 : GPIO_CFGCTL5 */
+#define GLB_GPIO_CFGCTL5_OFFSET       (0x114)
+#define GLB_REG_GPIO_10_IE            GLB_REG_GPIO_10_IE
+#define GLB_REG_GPIO_10_IE_POS        (0U)
+#define GLB_REG_GPIO_10_IE_LEN        (1U)
+#define GLB_REG_GPIO_10_IE_MSK        (((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS)
+#define GLB_REG_GPIO_10_IE_UMSK       (~(((1U << GLB_REG_GPIO_10_IE_LEN) - 1) << GLB_REG_GPIO_10_IE_POS))
+#define GLB_REG_GPIO_10_SMT           GLB_REG_GPIO_10_SMT
+#define GLB_REG_GPIO_10_SMT_POS       (1U)
+#define GLB_REG_GPIO_10_SMT_LEN       (1U)
+#define GLB_REG_GPIO_10_SMT_MSK       (((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS)
+#define GLB_REG_GPIO_10_SMT_UMSK      (~(((1U << GLB_REG_GPIO_10_SMT_LEN) - 1) << GLB_REG_GPIO_10_SMT_POS))
+#define GLB_REG_GPIO_10_DRV           GLB_REG_GPIO_10_DRV
+#define GLB_REG_GPIO_10_DRV_POS       (2U)
+#define GLB_REG_GPIO_10_DRV_LEN       (2U)
+#define GLB_REG_GPIO_10_DRV_MSK       (((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS)
+#define GLB_REG_GPIO_10_DRV_UMSK      (~(((1U << GLB_REG_GPIO_10_DRV_LEN) - 1) << GLB_REG_GPIO_10_DRV_POS))
+#define GLB_REG_GPIO_10_PU            GLB_REG_GPIO_10_PU
+#define GLB_REG_GPIO_10_PU_POS        (4U)
+#define GLB_REG_GPIO_10_PU_LEN        (1U)
+#define GLB_REG_GPIO_10_PU_MSK        (((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS)
+#define GLB_REG_GPIO_10_PU_UMSK       (~(((1U << GLB_REG_GPIO_10_PU_LEN) - 1) << GLB_REG_GPIO_10_PU_POS))
+#define GLB_REG_GPIO_10_PD            GLB_REG_GPIO_10_PD
+#define GLB_REG_GPIO_10_PD_POS        (5U)
+#define GLB_REG_GPIO_10_PD_LEN        (1U)
+#define GLB_REG_GPIO_10_PD_MSK        (((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS)
+#define GLB_REG_GPIO_10_PD_UMSK       (~(((1U << GLB_REG_GPIO_10_PD_LEN) - 1) << GLB_REG_GPIO_10_PD_POS))
+#define GLB_REG_GPIO_10_FUNC_SEL      GLB_REG_GPIO_10_FUNC_SEL
+#define GLB_REG_GPIO_10_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_10_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_10_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS)
+#define GLB_REG_GPIO_10_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_10_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_10_FUNC_SEL_POS))
+#define GLB_REG_GPIO_11_IE            GLB_REG_GPIO_11_IE
+#define GLB_REG_GPIO_11_IE_POS        (16U)
+#define GLB_REG_GPIO_11_IE_LEN        (1U)
+#define GLB_REG_GPIO_11_IE_MSK        (((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS)
+#define GLB_REG_GPIO_11_IE_UMSK       (~(((1U << GLB_REG_GPIO_11_IE_LEN) - 1) << GLB_REG_GPIO_11_IE_POS))
+#define GLB_REG_GPIO_11_SMT           GLB_REG_GPIO_11_SMT
+#define GLB_REG_GPIO_11_SMT_POS       (17U)
+#define GLB_REG_GPIO_11_SMT_LEN       (1U)
+#define GLB_REG_GPIO_11_SMT_MSK       (((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS)
+#define GLB_REG_GPIO_11_SMT_UMSK      (~(((1U << GLB_REG_GPIO_11_SMT_LEN) - 1) << GLB_REG_GPIO_11_SMT_POS))
+#define GLB_REG_GPIO_11_DRV           GLB_REG_GPIO_11_DRV
+#define GLB_REG_GPIO_11_DRV_POS       (18U)
+#define GLB_REG_GPIO_11_DRV_LEN       (2U)
+#define GLB_REG_GPIO_11_DRV_MSK       (((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS)
+#define GLB_REG_GPIO_11_DRV_UMSK      (~(((1U << GLB_REG_GPIO_11_DRV_LEN) - 1) << GLB_REG_GPIO_11_DRV_POS))
+#define GLB_REG_GPIO_11_PU            GLB_REG_GPIO_11_PU
+#define GLB_REG_GPIO_11_PU_POS        (20U)
+#define GLB_REG_GPIO_11_PU_LEN        (1U)
+#define GLB_REG_GPIO_11_PU_MSK        (((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS)
+#define GLB_REG_GPIO_11_PU_UMSK       (~(((1U << GLB_REG_GPIO_11_PU_LEN) - 1) << GLB_REG_GPIO_11_PU_POS))
+#define GLB_REG_GPIO_11_PD            GLB_REG_GPIO_11_PD
+#define GLB_REG_GPIO_11_PD_POS        (21U)
+#define GLB_REG_GPIO_11_PD_LEN        (1U)
+#define GLB_REG_GPIO_11_PD_MSK        (((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS)
+#define GLB_REG_GPIO_11_PD_UMSK       (~(((1U << GLB_REG_GPIO_11_PD_LEN) - 1) << GLB_REG_GPIO_11_PD_POS))
+#define GLB_REG_GPIO_11_FUNC_SEL      GLB_REG_GPIO_11_FUNC_SEL
+#define GLB_REG_GPIO_11_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_11_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_11_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS)
+#define GLB_REG_GPIO_11_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_11_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_11_FUNC_SEL_POS))
+
+/* 0x118 : GPIO_CFGCTL6 */
+#define GLB_GPIO_CFGCTL6_OFFSET       (0x118)
+#define GLB_REG_GPIO_12_IE            GLB_REG_GPIO_12_IE
+#define GLB_REG_GPIO_12_IE_POS        (0U)
+#define GLB_REG_GPIO_12_IE_LEN        (1U)
+#define GLB_REG_GPIO_12_IE_MSK        (((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS)
+#define GLB_REG_GPIO_12_IE_UMSK       (~(((1U << GLB_REG_GPIO_12_IE_LEN) - 1) << GLB_REG_GPIO_12_IE_POS))
+#define GLB_REG_GPIO_12_SMT           GLB_REG_GPIO_12_SMT
+#define GLB_REG_GPIO_12_SMT_POS       (1U)
+#define GLB_REG_GPIO_12_SMT_LEN       (1U)
+#define GLB_REG_GPIO_12_SMT_MSK       (((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS)
+#define GLB_REG_GPIO_12_SMT_UMSK      (~(((1U << GLB_REG_GPIO_12_SMT_LEN) - 1) << GLB_REG_GPIO_12_SMT_POS))
+#define GLB_REG_GPIO_12_DRV           GLB_REG_GPIO_12_DRV
+#define GLB_REG_GPIO_12_DRV_POS       (2U)
+#define GLB_REG_GPIO_12_DRV_LEN       (2U)
+#define GLB_REG_GPIO_12_DRV_MSK       (((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS)
+#define GLB_REG_GPIO_12_DRV_UMSK      (~(((1U << GLB_REG_GPIO_12_DRV_LEN) - 1) << GLB_REG_GPIO_12_DRV_POS))
+#define GLB_REG_GPIO_12_PU            GLB_REG_GPIO_12_PU
+#define GLB_REG_GPIO_12_PU_POS        (4U)
+#define GLB_REG_GPIO_12_PU_LEN        (1U)
+#define GLB_REG_GPIO_12_PU_MSK        (((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS)
+#define GLB_REG_GPIO_12_PU_UMSK       (~(((1U << GLB_REG_GPIO_12_PU_LEN) - 1) << GLB_REG_GPIO_12_PU_POS))
+#define GLB_REG_GPIO_12_PD            GLB_REG_GPIO_12_PD
+#define GLB_REG_GPIO_12_PD_POS        (5U)
+#define GLB_REG_GPIO_12_PD_LEN        (1U)
+#define GLB_REG_GPIO_12_PD_MSK        (((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS)
+#define GLB_REG_GPIO_12_PD_UMSK       (~(((1U << GLB_REG_GPIO_12_PD_LEN) - 1) << GLB_REG_GPIO_12_PD_POS))
+#define GLB_REG_GPIO_12_FUNC_SEL      GLB_REG_GPIO_12_FUNC_SEL
+#define GLB_REG_GPIO_12_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_12_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_12_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS)
+#define GLB_REG_GPIO_12_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_12_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_12_FUNC_SEL_POS))
+#define GLB_REG_GPIO_13_IE            GLB_REG_GPIO_13_IE
+#define GLB_REG_GPIO_13_IE_POS        (16U)
+#define GLB_REG_GPIO_13_IE_LEN        (1U)
+#define GLB_REG_GPIO_13_IE_MSK        (((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS)
+#define GLB_REG_GPIO_13_IE_UMSK       (~(((1U << GLB_REG_GPIO_13_IE_LEN) - 1) << GLB_REG_GPIO_13_IE_POS))
+#define GLB_REG_GPIO_13_SMT           GLB_REG_GPIO_13_SMT
+#define GLB_REG_GPIO_13_SMT_POS       (17U)
+#define GLB_REG_GPIO_13_SMT_LEN       (1U)
+#define GLB_REG_GPIO_13_SMT_MSK       (((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS)
+#define GLB_REG_GPIO_13_SMT_UMSK      (~(((1U << GLB_REG_GPIO_13_SMT_LEN) - 1) << GLB_REG_GPIO_13_SMT_POS))
+#define GLB_REG_GPIO_13_DRV           GLB_REG_GPIO_13_DRV
+#define GLB_REG_GPIO_13_DRV_POS       (18U)
+#define GLB_REG_GPIO_13_DRV_LEN       (2U)
+#define GLB_REG_GPIO_13_DRV_MSK       (((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS)
+#define GLB_REG_GPIO_13_DRV_UMSK      (~(((1U << GLB_REG_GPIO_13_DRV_LEN) - 1) << GLB_REG_GPIO_13_DRV_POS))
+#define GLB_REG_GPIO_13_PU            GLB_REG_GPIO_13_PU
+#define GLB_REG_GPIO_13_PU_POS        (20U)
+#define GLB_REG_GPIO_13_PU_LEN        (1U)
+#define GLB_REG_GPIO_13_PU_MSK        (((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS)
+#define GLB_REG_GPIO_13_PU_UMSK       (~(((1U << GLB_REG_GPIO_13_PU_LEN) - 1) << GLB_REG_GPIO_13_PU_POS))
+#define GLB_REG_GPIO_13_PD            GLB_REG_GPIO_13_PD
+#define GLB_REG_GPIO_13_PD_POS        (21U)
+#define GLB_REG_GPIO_13_PD_LEN        (1U)
+#define GLB_REG_GPIO_13_PD_MSK        (((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS)
+#define GLB_REG_GPIO_13_PD_UMSK       (~(((1U << GLB_REG_GPIO_13_PD_LEN) - 1) << GLB_REG_GPIO_13_PD_POS))
+#define GLB_REG_GPIO_13_FUNC_SEL      GLB_REG_GPIO_13_FUNC_SEL
+#define GLB_REG_GPIO_13_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_13_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_13_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS)
+#define GLB_REG_GPIO_13_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_13_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_13_FUNC_SEL_POS))
+
+/* 0x11C : GPIO_CFGCTL7 */
+#define GLB_GPIO_CFGCTL7_OFFSET       (0x11C)
+#define GLB_REG_GPIO_14_IE            GLB_REG_GPIO_14_IE
+#define GLB_REG_GPIO_14_IE_POS        (0U)
+#define GLB_REG_GPIO_14_IE_LEN        (1U)
+#define GLB_REG_GPIO_14_IE_MSK        (((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS)
+#define GLB_REG_GPIO_14_IE_UMSK       (~(((1U << GLB_REG_GPIO_14_IE_LEN) - 1) << GLB_REG_GPIO_14_IE_POS))
+#define GLB_REG_GPIO_14_SMT           GLB_REG_GPIO_14_SMT
+#define GLB_REG_GPIO_14_SMT_POS       (1U)
+#define GLB_REG_GPIO_14_SMT_LEN       (1U)
+#define GLB_REG_GPIO_14_SMT_MSK       (((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS)
+#define GLB_REG_GPIO_14_SMT_UMSK      (~(((1U << GLB_REG_GPIO_14_SMT_LEN) - 1) << GLB_REG_GPIO_14_SMT_POS))
+#define GLB_REG_GPIO_14_DRV           GLB_REG_GPIO_14_DRV
+#define GLB_REG_GPIO_14_DRV_POS       (2U)
+#define GLB_REG_GPIO_14_DRV_LEN       (2U)
+#define GLB_REG_GPIO_14_DRV_MSK       (((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS)
+#define GLB_REG_GPIO_14_DRV_UMSK      (~(((1U << GLB_REG_GPIO_14_DRV_LEN) - 1) << GLB_REG_GPIO_14_DRV_POS))
+#define GLB_REG_GPIO_14_PU            GLB_REG_GPIO_14_PU
+#define GLB_REG_GPIO_14_PU_POS        (4U)
+#define GLB_REG_GPIO_14_PU_LEN        (1U)
+#define GLB_REG_GPIO_14_PU_MSK        (((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS)
+#define GLB_REG_GPIO_14_PU_UMSK       (~(((1U << GLB_REG_GPIO_14_PU_LEN) - 1) << GLB_REG_GPIO_14_PU_POS))
+#define GLB_REG_GPIO_14_PD            GLB_REG_GPIO_14_PD
+#define GLB_REG_GPIO_14_PD_POS        (5U)
+#define GLB_REG_GPIO_14_PD_LEN        (1U)
+#define GLB_REG_GPIO_14_PD_MSK        (((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS)
+#define GLB_REG_GPIO_14_PD_UMSK       (~(((1U << GLB_REG_GPIO_14_PD_LEN) - 1) << GLB_REG_GPIO_14_PD_POS))
+#define GLB_REG_GPIO_14_FUNC_SEL      GLB_REG_GPIO_14_FUNC_SEL
+#define GLB_REG_GPIO_14_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_14_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_14_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS)
+#define GLB_REG_GPIO_14_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_14_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_14_FUNC_SEL_POS))
+#define GLB_REG_GPIO_15_IE            GLB_REG_GPIO_15_IE
+#define GLB_REG_GPIO_15_IE_POS        (16U)
+#define GLB_REG_GPIO_15_IE_LEN        (1U)
+#define GLB_REG_GPIO_15_IE_MSK        (((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS)
+#define GLB_REG_GPIO_15_IE_UMSK       (~(((1U << GLB_REG_GPIO_15_IE_LEN) - 1) << GLB_REG_GPIO_15_IE_POS))
+#define GLB_REG_GPIO_15_SMT           GLB_REG_GPIO_15_SMT
+#define GLB_REG_GPIO_15_SMT_POS       (17U)
+#define GLB_REG_GPIO_15_SMT_LEN       (1U)
+#define GLB_REG_GPIO_15_SMT_MSK       (((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS)
+#define GLB_REG_GPIO_15_SMT_UMSK      (~(((1U << GLB_REG_GPIO_15_SMT_LEN) - 1) << GLB_REG_GPIO_15_SMT_POS))
+#define GLB_REG_GPIO_15_DRV           GLB_REG_GPIO_15_DRV
+#define GLB_REG_GPIO_15_DRV_POS       (18U)
+#define GLB_REG_GPIO_15_DRV_LEN       (2U)
+#define GLB_REG_GPIO_15_DRV_MSK       (((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS)
+#define GLB_REG_GPIO_15_DRV_UMSK      (~(((1U << GLB_REG_GPIO_15_DRV_LEN) - 1) << GLB_REG_GPIO_15_DRV_POS))
+#define GLB_REG_GPIO_15_PU            GLB_REG_GPIO_15_PU
+#define GLB_REG_GPIO_15_PU_POS        (20U)
+#define GLB_REG_GPIO_15_PU_LEN        (1U)
+#define GLB_REG_GPIO_15_PU_MSK        (((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS)
+#define GLB_REG_GPIO_15_PU_UMSK       (~(((1U << GLB_REG_GPIO_15_PU_LEN) - 1) << GLB_REG_GPIO_15_PU_POS))
+#define GLB_REG_GPIO_15_PD            GLB_REG_GPIO_15_PD
+#define GLB_REG_GPIO_15_PD_POS        (21U)
+#define GLB_REG_GPIO_15_PD_LEN        (1U)
+#define GLB_REG_GPIO_15_PD_MSK        (((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS)
+#define GLB_REG_GPIO_15_PD_UMSK       (~(((1U << GLB_REG_GPIO_15_PD_LEN) - 1) << GLB_REG_GPIO_15_PD_POS))
+#define GLB_REG_GPIO_15_FUNC_SEL      GLB_REG_GPIO_15_FUNC_SEL
+#define GLB_REG_GPIO_15_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_15_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_15_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS)
+#define GLB_REG_GPIO_15_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_15_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_15_FUNC_SEL_POS))
+
+/* 0x120 : GPIO_CFGCTL8 */
+#define GLB_GPIO_CFGCTL8_OFFSET       (0x120)
+#define GLB_REG_GPIO_16_IE            GLB_REG_GPIO_16_IE
+#define GLB_REG_GPIO_16_IE_POS        (0U)
+#define GLB_REG_GPIO_16_IE_LEN        (1U)
+#define GLB_REG_GPIO_16_IE_MSK        (((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS)
+#define GLB_REG_GPIO_16_IE_UMSK       (~(((1U << GLB_REG_GPIO_16_IE_LEN) - 1) << GLB_REG_GPIO_16_IE_POS))
+#define GLB_REG_GPIO_16_SMT           GLB_REG_GPIO_16_SMT
+#define GLB_REG_GPIO_16_SMT_POS       (1U)
+#define GLB_REG_GPIO_16_SMT_LEN       (1U)
+#define GLB_REG_GPIO_16_SMT_MSK       (((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS)
+#define GLB_REG_GPIO_16_SMT_UMSK      (~(((1U << GLB_REG_GPIO_16_SMT_LEN) - 1) << GLB_REG_GPIO_16_SMT_POS))
+#define GLB_REG_GPIO_16_DRV           GLB_REG_GPIO_16_DRV
+#define GLB_REG_GPIO_16_DRV_POS       (2U)
+#define GLB_REG_GPIO_16_DRV_LEN       (2U)
+#define GLB_REG_GPIO_16_DRV_MSK       (((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS)
+#define GLB_REG_GPIO_16_DRV_UMSK      (~(((1U << GLB_REG_GPIO_16_DRV_LEN) - 1) << GLB_REG_GPIO_16_DRV_POS))
+#define GLB_REG_GPIO_16_PU            GLB_REG_GPIO_16_PU
+#define GLB_REG_GPIO_16_PU_POS        (4U)
+#define GLB_REG_GPIO_16_PU_LEN        (1U)
+#define GLB_REG_GPIO_16_PU_MSK        (((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS)
+#define GLB_REG_GPIO_16_PU_UMSK       (~(((1U << GLB_REG_GPIO_16_PU_LEN) - 1) << GLB_REG_GPIO_16_PU_POS))
+#define GLB_REG_GPIO_16_PD            GLB_REG_GPIO_16_PD
+#define GLB_REG_GPIO_16_PD_POS        (5U)
+#define GLB_REG_GPIO_16_PD_LEN        (1U)
+#define GLB_REG_GPIO_16_PD_MSK        (((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS)
+#define GLB_REG_GPIO_16_PD_UMSK       (~(((1U << GLB_REG_GPIO_16_PD_LEN) - 1) << GLB_REG_GPIO_16_PD_POS))
+#define GLB_REG_GPIO_16_FUNC_SEL      GLB_REG_GPIO_16_FUNC_SEL
+#define GLB_REG_GPIO_16_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_16_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_16_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS)
+#define GLB_REG_GPIO_16_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_16_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_16_FUNC_SEL_POS))
+#define GLB_REG_GPIO_17_IE            GLB_REG_GPIO_17_IE
+#define GLB_REG_GPIO_17_IE_POS        (16U)
+#define GLB_REG_GPIO_17_IE_LEN        (1U)
+#define GLB_REG_GPIO_17_IE_MSK        (((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS)
+#define GLB_REG_GPIO_17_IE_UMSK       (~(((1U << GLB_REG_GPIO_17_IE_LEN) - 1) << GLB_REG_GPIO_17_IE_POS))
+#define GLB_REG_GPIO_17_SMT           GLB_REG_GPIO_17_SMT
+#define GLB_REG_GPIO_17_SMT_POS       (17U)
+#define GLB_REG_GPIO_17_SMT_LEN       (1U)
+#define GLB_REG_GPIO_17_SMT_MSK       (((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS)
+#define GLB_REG_GPIO_17_SMT_UMSK      (~(((1U << GLB_REG_GPIO_17_SMT_LEN) - 1) << GLB_REG_GPIO_17_SMT_POS))
+#define GLB_REG_GPIO_17_DRV           GLB_REG_GPIO_17_DRV
+#define GLB_REG_GPIO_17_DRV_POS       (18U)
+#define GLB_REG_GPIO_17_DRV_LEN       (2U)
+#define GLB_REG_GPIO_17_DRV_MSK       (((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS)
+#define GLB_REG_GPIO_17_DRV_UMSK      (~(((1U << GLB_REG_GPIO_17_DRV_LEN) - 1) << GLB_REG_GPIO_17_DRV_POS))
+#define GLB_REG_GPIO_17_PU            GLB_REG_GPIO_17_PU
+#define GLB_REG_GPIO_17_PU_POS        (20U)
+#define GLB_REG_GPIO_17_PU_LEN        (1U)
+#define GLB_REG_GPIO_17_PU_MSK        (((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS)
+#define GLB_REG_GPIO_17_PU_UMSK       (~(((1U << GLB_REG_GPIO_17_PU_LEN) - 1) << GLB_REG_GPIO_17_PU_POS))
+#define GLB_REG_GPIO_17_PD            GLB_REG_GPIO_17_PD
+#define GLB_REG_GPIO_17_PD_POS        (21U)
+#define GLB_REG_GPIO_17_PD_LEN        (1U)
+#define GLB_REG_GPIO_17_PD_MSK        (((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS)
+#define GLB_REG_GPIO_17_PD_UMSK       (~(((1U << GLB_REG_GPIO_17_PD_LEN) - 1) << GLB_REG_GPIO_17_PD_POS))
+#define GLB_REG_GPIO_17_FUNC_SEL      GLB_REG_GPIO_17_FUNC_SEL
+#define GLB_REG_GPIO_17_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_17_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_17_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS)
+#define GLB_REG_GPIO_17_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_17_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_17_FUNC_SEL_POS))
+
+/* 0x124 : GPIO_CFGCTL9 */
+#define GLB_GPIO_CFGCTL9_OFFSET       (0x124)
+#define GLB_REG_GPIO_18_IE            GLB_REG_GPIO_18_IE
+#define GLB_REG_GPIO_18_IE_POS        (0U)
+#define GLB_REG_GPIO_18_IE_LEN        (1U)
+#define GLB_REG_GPIO_18_IE_MSK        (((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS)
+#define GLB_REG_GPIO_18_IE_UMSK       (~(((1U << GLB_REG_GPIO_18_IE_LEN) - 1) << GLB_REG_GPIO_18_IE_POS))
+#define GLB_REG_GPIO_18_SMT           GLB_REG_GPIO_18_SMT
+#define GLB_REG_GPIO_18_SMT_POS       (1U)
+#define GLB_REG_GPIO_18_SMT_LEN       (1U)
+#define GLB_REG_GPIO_18_SMT_MSK       (((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS)
+#define GLB_REG_GPIO_18_SMT_UMSK      (~(((1U << GLB_REG_GPIO_18_SMT_LEN) - 1) << GLB_REG_GPIO_18_SMT_POS))
+#define GLB_REG_GPIO_18_DRV           GLB_REG_GPIO_18_DRV
+#define GLB_REG_GPIO_18_DRV_POS       (2U)
+#define GLB_REG_GPIO_18_DRV_LEN       (2U)
+#define GLB_REG_GPIO_18_DRV_MSK       (((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS)
+#define GLB_REG_GPIO_18_DRV_UMSK      (~(((1U << GLB_REG_GPIO_18_DRV_LEN) - 1) << GLB_REG_GPIO_18_DRV_POS))
+#define GLB_REG_GPIO_18_PU            GLB_REG_GPIO_18_PU
+#define GLB_REG_GPIO_18_PU_POS        (4U)
+#define GLB_REG_GPIO_18_PU_LEN        (1U)
+#define GLB_REG_GPIO_18_PU_MSK        (((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS)
+#define GLB_REG_GPIO_18_PU_UMSK       (~(((1U << GLB_REG_GPIO_18_PU_LEN) - 1) << GLB_REG_GPIO_18_PU_POS))
+#define GLB_REG_GPIO_18_PD            GLB_REG_GPIO_18_PD
+#define GLB_REG_GPIO_18_PD_POS        (5U)
+#define GLB_REG_GPIO_18_PD_LEN        (1U)
+#define GLB_REG_GPIO_18_PD_MSK        (((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS)
+#define GLB_REG_GPIO_18_PD_UMSK       (~(((1U << GLB_REG_GPIO_18_PD_LEN) - 1) << GLB_REG_GPIO_18_PD_POS))
+#define GLB_REG_GPIO_18_FUNC_SEL      GLB_REG_GPIO_18_FUNC_SEL
+#define GLB_REG_GPIO_18_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_18_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_18_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS)
+#define GLB_REG_GPIO_18_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_18_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_18_FUNC_SEL_POS))
+#define GLB_REG_GPIO_19_IE            GLB_REG_GPIO_19_IE
+#define GLB_REG_GPIO_19_IE_POS        (16U)
+#define GLB_REG_GPIO_19_IE_LEN        (1U)
+#define GLB_REG_GPIO_19_IE_MSK        (((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS)
+#define GLB_REG_GPIO_19_IE_UMSK       (~(((1U << GLB_REG_GPIO_19_IE_LEN) - 1) << GLB_REG_GPIO_19_IE_POS))
+#define GLB_REG_GPIO_19_SMT           GLB_REG_GPIO_19_SMT
+#define GLB_REG_GPIO_19_SMT_POS       (17U)
+#define GLB_REG_GPIO_19_SMT_LEN       (1U)
+#define GLB_REG_GPIO_19_SMT_MSK       (((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS)
+#define GLB_REG_GPIO_19_SMT_UMSK      (~(((1U << GLB_REG_GPIO_19_SMT_LEN) - 1) << GLB_REG_GPIO_19_SMT_POS))
+#define GLB_REG_GPIO_19_DRV           GLB_REG_GPIO_19_DRV
+#define GLB_REG_GPIO_19_DRV_POS       (18U)
+#define GLB_REG_GPIO_19_DRV_LEN       (2U)
+#define GLB_REG_GPIO_19_DRV_MSK       (((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS)
+#define GLB_REG_GPIO_19_DRV_UMSK      (~(((1U << GLB_REG_GPIO_19_DRV_LEN) - 1) << GLB_REG_GPIO_19_DRV_POS))
+#define GLB_REG_GPIO_19_PU            GLB_REG_GPIO_19_PU
+#define GLB_REG_GPIO_19_PU_POS        (20U)
+#define GLB_REG_GPIO_19_PU_LEN        (1U)
+#define GLB_REG_GPIO_19_PU_MSK        (((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS)
+#define GLB_REG_GPIO_19_PU_UMSK       (~(((1U << GLB_REG_GPIO_19_PU_LEN) - 1) << GLB_REG_GPIO_19_PU_POS))
+#define GLB_REG_GPIO_19_PD            GLB_REG_GPIO_19_PD
+#define GLB_REG_GPIO_19_PD_POS        (21U)
+#define GLB_REG_GPIO_19_PD_LEN        (1U)
+#define GLB_REG_GPIO_19_PD_MSK        (((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS)
+#define GLB_REG_GPIO_19_PD_UMSK       (~(((1U << GLB_REG_GPIO_19_PD_LEN) - 1) << GLB_REG_GPIO_19_PD_POS))
+#define GLB_REG_GPIO_19_FUNC_SEL      GLB_REG_GPIO_19_FUNC_SEL
+#define GLB_REG_GPIO_19_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_19_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_19_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS)
+#define GLB_REG_GPIO_19_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_19_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_19_FUNC_SEL_POS))
+
+/* 0x128 : GPIO_CFGCTL10 */
+#define GLB_GPIO_CFGCTL10_OFFSET      (0x128)
+#define GLB_REG_GPIO_20_IE            GLB_REG_GPIO_20_IE
+#define GLB_REG_GPIO_20_IE_POS        (0U)
+#define GLB_REG_GPIO_20_IE_LEN        (1U)
+#define GLB_REG_GPIO_20_IE_MSK        (((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS)
+#define GLB_REG_GPIO_20_IE_UMSK       (~(((1U << GLB_REG_GPIO_20_IE_LEN) - 1) << GLB_REG_GPIO_20_IE_POS))
+#define GLB_REG_GPIO_20_SMT           GLB_REG_GPIO_20_SMT
+#define GLB_REG_GPIO_20_SMT_POS       (1U)
+#define GLB_REG_GPIO_20_SMT_LEN       (1U)
+#define GLB_REG_GPIO_20_SMT_MSK       (((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS)
+#define GLB_REG_GPIO_20_SMT_UMSK      (~(((1U << GLB_REG_GPIO_20_SMT_LEN) - 1) << GLB_REG_GPIO_20_SMT_POS))
+#define GLB_REG_GPIO_20_DRV           GLB_REG_GPIO_20_DRV
+#define GLB_REG_GPIO_20_DRV_POS       (2U)
+#define GLB_REG_GPIO_20_DRV_LEN       (2U)
+#define GLB_REG_GPIO_20_DRV_MSK       (((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS)
+#define GLB_REG_GPIO_20_DRV_UMSK      (~(((1U << GLB_REG_GPIO_20_DRV_LEN) - 1) << GLB_REG_GPIO_20_DRV_POS))
+#define GLB_REG_GPIO_20_PU            GLB_REG_GPIO_20_PU
+#define GLB_REG_GPIO_20_PU_POS        (4U)
+#define GLB_REG_GPIO_20_PU_LEN        (1U)
+#define GLB_REG_GPIO_20_PU_MSK        (((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS)
+#define GLB_REG_GPIO_20_PU_UMSK       (~(((1U << GLB_REG_GPIO_20_PU_LEN) - 1) << GLB_REG_GPIO_20_PU_POS))
+#define GLB_REG_GPIO_20_PD            GLB_REG_GPIO_20_PD
+#define GLB_REG_GPIO_20_PD_POS        (5U)
+#define GLB_REG_GPIO_20_PD_LEN        (1U)
+#define GLB_REG_GPIO_20_PD_MSK        (((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS)
+#define GLB_REG_GPIO_20_PD_UMSK       (~(((1U << GLB_REG_GPIO_20_PD_LEN) - 1) << GLB_REG_GPIO_20_PD_POS))
+#define GLB_REG_GPIO_20_FUNC_SEL      GLB_REG_GPIO_20_FUNC_SEL
+#define GLB_REG_GPIO_20_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_20_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_20_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS)
+#define GLB_REG_GPIO_20_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_20_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_20_FUNC_SEL_POS))
+#define GLB_REG_GPIO_21_IE            GLB_REG_GPIO_21_IE
+#define GLB_REG_GPIO_21_IE_POS        (16U)
+#define GLB_REG_GPIO_21_IE_LEN        (1U)
+#define GLB_REG_GPIO_21_IE_MSK        (((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS)
+#define GLB_REG_GPIO_21_IE_UMSK       (~(((1U << GLB_REG_GPIO_21_IE_LEN) - 1) << GLB_REG_GPIO_21_IE_POS))
+#define GLB_REG_GPIO_21_SMT           GLB_REG_GPIO_21_SMT
+#define GLB_REG_GPIO_21_SMT_POS       (17U)
+#define GLB_REG_GPIO_21_SMT_LEN       (1U)
+#define GLB_REG_GPIO_21_SMT_MSK       (((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS)
+#define GLB_REG_GPIO_21_SMT_UMSK      (~(((1U << GLB_REG_GPIO_21_SMT_LEN) - 1) << GLB_REG_GPIO_21_SMT_POS))
+#define GLB_REG_GPIO_21_DRV           GLB_REG_GPIO_21_DRV
+#define GLB_REG_GPIO_21_DRV_POS       (18U)
+#define GLB_REG_GPIO_21_DRV_LEN       (2U)
+#define GLB_REG_GPIO_21_DRV_MSK       (((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS)
+#define GLB_REG_GPIO_21_DRV_UMSK      (~(((1U << GLB_REG_GPIO_21_DRV_LEN) - 1) << GLB_REG_GPIO_21_DRV_POS))
+#define GLB_REG_GPIO_21_PU            GLB_REG_GPIO_21_PU
+#define GLB_REG_GPIO_21_PU_POS        (20U)
+#define GLB_REG_GPIO_21_PU_LEN        (1U)
+#define GLB_REG_GPIO_21_PU_MSK        (((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS)
+#define GLB_REG_GPIO_21_PU_UMSK       (~(((1U << GLB_REG_GPIO_21_PU_LEN) - 1) << GLB_REG_GPIO_21_PU_POS))
+#define GLB_REG_GPIO_21_PD            GLB_REG_GPIO_21_PD
+#define GLB_REG_GPIO_21_PD_POS        (21U)
+#define GLB_REG_GPIO_21_PD_LEN        (1U)
+#define GLB_REG_GPIO_21_PD_MSK        (((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS)
+#define GLB_REG_GPIO_21_PD_UMSK       (~(((1U << GLB_REG_GPIO_21_PD_LEN) - 1) << GLB_REG_GPIO_21_PD_POS))
+#define GLB_REG_GPIO_21_FUNC_SEL      GLB_REG_GPIO_21_FUNC_SEL
+#define GLB_REG_GPIO_21_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_21_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_21_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS)
+#define GLB_REG_GPIO_21_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_21_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_21_FUNC_SEL_POS))
+
+/* 0x12C : GPIO_CFGCTL11 */
+#define GLB_GPIO_CFGCTL11_OFFSET      (0x12C)
+#define GLB_REG_GPIO_22_IE            GLB_REG_GPIO_22_IE
+#define GLB_REG_GPIO_22_IE_POS        (0U)
+#define GLB_REG_GPIO_22_IE_LEN        (1U)
+#define GLB_REG_GPIO_22_IE_MSK        (((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS)
+#define GLB_REG_GPIO_22_IE_UMSK       (~(((1U << GLB_REG_GPIO_22_IE_LEN) - 1) << GLB_REG_GPIO_22_IE_POS))
+#define GLB_REG_GPIO_22_SMT           GLB_REG_GPIO_22_SMT
+#define GLB_REG_GPIO_22_SMT_POS       (1U)
+#define GLB_REG_GPIO_22_SMT_LEN       (1U)
+#define GLB_REG_GPIO_22_SMT_MSK       (((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS)
+#define GLB_REG_GPIO_22_SMT_UMSK      (~(((1U << GLB_REG_GPIO_22_SMT_LEN) - 1) << GLB_REG_GPIO_22_SMT_POS))
+#define GLB_REG_GPIO_22_DRV           GLB_REG_GPIO_22_DRV
+#define GLB_REG_GPIO_22_DRV_POS       (2U)
+#define GLB_REG_GPIO_22_DRV_LEN       (2U)
+#define GLB_REG_GPIO_22_DRV_MSK       (((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS)
+#define GLB_REG_GPIO_22_DRV_UMSK      (~(((1U << GLB_REG_GPIO_22_DRV_LEN) - 1) << GLB_REG_GPIO_22_DRV_POS))
+#define GLB_REG_GPIO_22_PU            GLB_REG_GPIO_22_PU
+#define GLB_REG_GPIO_22_PU_POS        (4U)
+#define GLB_REG_GPIO_22_PU_LEN        (1U)
+#define GLB_REG_GPIO_22_PU_MSK        (((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS)
+#define GLB_REG_GPIO_22_PU_UMSK       (~(((1U << GLB_REG_GPIO_22_PU_LEN) - 1) << GLB_REG_GPIO_22_PU_POS))
+#define GLB_REG_GPIO_22_PD            GLB_REG_GPIO_22_PD
+#define GLB_REG_GPIO_22_PD_POS        (5U)
+#define GLB_REG_GPIO_22_PD_LEN        (1U)
+#define GLB_REG_GPIO_22_PD_MSK        (((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS)
+#define GLB_REG_GPIO_22_PD_UMSK       (~(((1U << GLB_REG_GPIO_22_PD_LEN) - 1) << GLB_REG_GPIO_22_PD_POS))
+#define GLB_REG_GPIO_22_FUNC_SEL      GLB_REG_GPIO_22_FUNC_SEL
+#define GLB_REG_GPIO_22_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_22_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_22_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS)
+#define GLB_REG_GPIO_22_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_22_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_22_FUNC_SEL_POS))
+#define GLB_REG_GPIO_23_IE            GLB_REG_GPIO_23_IE
+#define GLB_REG_GPIO_23_IE_POS        (16U)
+#define GLB_REG_GPIO_23_IE_LEN        (1U)
+#define GLB_REG_GPIO_23_IE_MSK        (((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS)
+#define GLB_REG_GPIO_23_IE_UMSK       (~(((1U << GLB_REG_GPIO_23_IE_LEN) - 1) << GLB_REG_GPIO_23_IE_POS))
+#define GLB_REG_GPIO_23_SMT           GLB_REG_GPIO_23_SMT
+#define GLB_REG_GPIO_23_SMT_POS       (17U)
+#define GLB_REG_GPIO_23_SMT_LEN       (1U)
+#define GLB_REG_GPIO_23_SMT_MSK       (((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS)
+#define GLB_REG_GPIO_23_SMT_UMSK      (~(((1U << GLB_REG_GPIO_23_SMT_LEN) - 1) << GLB_REG_GPIO_23_SMT_POS))
+#define GLB_REG_GPIO_23_DRV           GLB_REG_GPIO_23_DRV
+#define GLB_REG_GPIO_23_DRV_POS       (18U)
+#define GLB_REG_GPIO_23_DRV_LEN       (2U)
+#define GLB_REG_GPIO_23_DRV_MSK       (((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS)
+#define GLB_REG_GPIO_23_DRV_UMSK      (~(((1U << GLB_REG_GPIO_23_DRV_LEN) - 1) << GLB_REG_GPIO_23_DRV_POS))
+#define GLB_REG_GPIO_23_PU            GLB_REG_GPIO_23_PU
+#define GLB_REG_GPIO_23_PU_POS        (20U)
+#define GLB_REG_GPIO_23_PU_LEN        (1U)
+#define GLB_REG_GPIO_23_PU_MSK        (((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS)
+#define GLB_REG_GPIO_23_PU_UMSK       (~(((1U << GLB_REG_GPIO_23_PU_LEN) - 1) << GLB_REG_GPIO_23_PU_POS))
+#define GLB_REG_GPIO_23_PD            GLB_REG_GPIO_23_PD
+#define GLB_REG_GPIO_23_PD_POS        (21U)
+#define GLB_REG_GPIO_23_PD_LEN        (1U)
+#define GLB_REG_GPIO_23_PD_MSK        (((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS)
+#define GLB_REG_GPIO_23_PD_UMSK       (~(((1U << GLB_REG_GPIO_23_PD_LEN) - 1) << GLB_REG_GPIO_23_PD_POS))
+#define GLB_REG_GPIO_23_FUNC_SEL      GLB_REG_GPIO_23_FUNC_SEL
+#define GLB_REG_GPIO_23_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_23_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_23_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS)
+#define GLB_REG_GPIO_23_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_23_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_23_FUNC_SEL_POS))
+
+/* 0x130 : GPIO_CFGCTL12 */
+#define GLB_GPIO_CFGCTL12_OFFSET      (0x130)
+#define GLB_REG_GPIO_24_IE            GLB_REG_GPIO_24_IE
+#define GLB_REG_GPIO_24_IE_POS        (0U)
+#define GLB_REG_GPIO_24_IE_LEN        (1U)
+#define GLB_REG_GPIO_24_IE_MSK        (((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS)
+#define GLB_REG_GPIO_24_IE_UMSK       (~(((1U << GLB_REG_GPIO_24_IE_LEN) - 1) << GLB_REG_GPIO_24_IE_POS))
+#define GLB_REG_GPIO_24_SMT           GLB_REG_GPIO_24_SMT
+#define GLB_REG_GPIO_24_SMT_POS       (1U)
+#define GLB_REG_GPIO_24_SMT_LEN       (1U)
+#define GLB_REG_GPIO_24_SMT_MSK       (((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS)
+#define GLB_REG_GPIO_24_SMT_UMSK      (~(((1U << GLB_REG_GPIO_24_SMT_LEN) - 1) << GLB_REG_GPIO_24_SMT_POS))
+#define GLB_REG_GPIO_24_DRV           GLB_REG_GPIO_24_DRV
+#define GLB_REG_GPIO_24_DRV_POS       (2U)
+#define GLB_REG_GPIO_24_DRV_LEN       (2U)
+#define GLB_REG_GPIO_24_DRV_MSK       (((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS)
+#define GLB_REG_GPIO_24_DRV_UMSK      (~(((1U << GLB_REG_GPIO_24_DRV_LEN) - 1) << GLB_REG_GPIO_24_DRV_POS))
+#define GLB_REG_GPIO_24_PU            GLB_REG_GPIO_24_PU
+#define GLB_REG_GPIO_24_PU_POS        (4U)
+#define GLB_REG_GPIO_24_PU_LEN        (1U)
+#define GLB_REG_GPIO_24_PU_MSK        (((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS)
+#define GLB_REG_GPIO_24_PU_UMSK       (~(((1U << GLB_REG_GPIO_24_PU_LEN) - 1) << GLB_REG_GPIO_24_PU_POS))
+#define GLB_REG_GPIO_24_PD            GLB_REG_GPIO_24_PD
+#define GLB_REG_GPIO_24_PD_POS        (5U)
+#define GLB_REG_GPIO_24_PD_LEN        (1U)
+#define GLB_REG_GPIO_24_PD_MSK        (((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS)
+#define GLB_REG_GPIO_24_PD_UMSK       (~(((1U << GLB_REG_GPIO_24_PD_LEN) - 1) << GLB_REG_GPIO_24_PD_POS))
+#define GLB_REG_GPIO_24_FUNC_SEL      GLB_REG_GPIO_24_FUNC_SEL
+#define GLB_REG_GPIO_24_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_24_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_24_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS)
+#define GLB_REG_GPIO_24_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_24_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_24_FUNC_SEL_POS))
+#define GLB_REG_GPIO_25_IE            GLB_REG_GPIO_25_IE
+#define GLB_REG_GPIO_25_IE_POS        (16U)
+#define GLB_REG_GPIO_25_IE_LEN        (1U)
+#define GLB_REG_GPIO_25_IE_MSK        (((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS)
+#define GLB_REG_GPIO_25_IE_UMSK       (~(((1U << GLB_REG_GPIO_25_IE_LEN) - 1) << GLB_REG_GPIO_25_IE_POS))
+#define GLB_REG_GPIO_25_SMT           GLB_REG_GPIO_25_SMT
+#define GLB_REG_GPIO_25_SMT_POS       (17U)
+#define GLB_REG_GPIO_25_SMT_LEN       (1U)
+#define GLB_REG_GPIO_25_SMT_MSK       (((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS)
+#define GLB_REG_GPIO_25_SMT_UMSK      (~(((1U << GLB_REG_GPIO_25_SMT_LEN) - 1) << GLB_REG_GPIO_25_SMT_POS))
+#define GLB_REG_GPIO_25_DRV           GLB_REG_GPIO_25_DRV
+#define GLB_REG_GPIO_25_DRV_POS       (18U)
+#define GLB_REG_GPIO_25_DRV_LEN       (2U)
+#define GLB_REG_GPIO_25_DRV_MSK       (((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS)
+#define GLB_REG_GPIO_25_DRV_UMSK      (~(((1U << GLB_REG_GPIO_25_DRV_LEN) - 1) << GLB_REG_GPIO_25_DRV_POS))
+#define GLB_REG_GPIO_25_PU            GLB_REG_GPIO_25_PU
+#define GLB_REG_GPIO_25_PU_POS        (20U)
+#define GLB_REG_GPIO_25_PU_LEN        (1U)
+#define GLB_REG_GPIO_25_PU_MSK        (((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS)
+#define GLB_REG_GPIO_25_PU_UMSK       (~(((1U << GLB_REG_GPIO_25_PU_LEN) - 1) << GLB_REG_GPIO_25_PU_POS))
+#define GLB_REG_GPIO_25_PD            GLB_REG_GPIO_25_PD
+#define GLB_REG_GPIO_25_PD_POS        (21U)
+#define GLB_REG_GPIO_25_PD_LEN        (1U)
+#define GLB_REG_GPIO_25_PD_MSK        (((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS)
+#define GLB_REG_GPIO_25_PD_UMSK       (~(((1U << GLB_REG_GPIO_25_PD_LEN) - 1) << GLB_REG_GPIO_25_PD_POS))
+#define GLB_REG_GPIO_25_FUNC_SEL      GLB_REG_GPIO_25_FUNC_SEL
+#define GLB_REG_GPIO_25_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_25_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_25_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS)
+#define GLB_REG_GPIO_25_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_25_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_25_FUNC_SEL_POS))
+
+/* 0x134 : GPIO_CFGCTL13 */
+#define GLB_GPIO_CFGCTL13_OFFSET      (0x134)
+#define GLB_REG_GPIO_26_IE            GLB_REG_GPIO_26_IE
+#define GLB_REG_GPIO_26_IE_POS        (0U)
+#define GLB_REG_GPIO_26_IE_LEN        (1U)
+#define GLB_REG_GPIO_26_IE_MSK        (((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS)
+#define GLB_REG_GPIO_26_IE_UMSK       (~(((1U << GLB_REG_GPIO_26_IE_LEN) - 1) << GLB_REG_GPIO_26_IE_POS))
+#define GLB_REG_GPIO_26_SMT           GLB_REG_GPIO_26_SMT
+#define GLB_REG_GPIO_26_SMT_POS       (1U)
+#define GLB_REG_GPIO_26_SMT_LEN       (1U)
+#define GLB_REG_GPIO_26_SMT_MSK       (((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS)
+#define GLB_REG_GPIO_26_SMT_UMSK      (~(((1U << GLB_REG_GPIO_26_SMT_LEN) - 1) << GLB_REG_GPIO_26_SMT_POS))
+#define GLB_REG_GPIO_26_DRV           GLB_REG_GPIO_26_DRV
+#define GLB_REG_GPIO_26_DRV_POS       (2U)
+#define GLB_REG_GPIO_26_DRV_LEN       (2U)
+#define GLB_REG_GPIO_26_DRV_MSK       (((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS)
+#define GLB_REG_GPIO_26_DRV_UMSK      (~(((1U << GLB_REG_GPIO_26_DRV_LEN) - 1) << GLB_REG_GPIO_26_DRV_POS))
+#define GLB_REG_GPIO_26_PU            GLB_REG_GPIO_26_PU
+#define GLB_REG_GPIO_26_PU_POS        (4U)
+#define GLB_REG_GPIO_26_PU_LEN        (1U)
+#define GLB_REG_GPIO_26_PU_MSK        (((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS)
+#define GLB_REG_GPIO_26_PU_UMSK       (~(((1U << GLB_REG_GPIO_26_PU_LEN) - 1) << GLB_REG_GPIO_26_PU_POS))
+#define GLB_REG_GPIO_26_PD            GLB_REG_GPIO_26_PD
+#define GLB_REG_GPIO_26_PD_POS        (5U)
+#define GLB_REG_GPIO_26_PD_LEN        (1U)
+#define GLB_REG_GPIO_26_PD_MSK        (((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS)
+#define GLB_REG_GPIO_26_PD_UMSK       (~(((1U << GLB_REG_GPIO_26_PD_LEN) - 1) << GLB_REG_GPIO_26_PD_POS))
+#define GLB_REG_GPIO_26_FUNC_SEL      GLB_REG_GPIO_26_FUNC_SEL
+#define GLB_REG_GPIO_26_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_26_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_26_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS)
+#define GLB_REG_GPIO_26_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_26_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_26_FUNC_SEL_POS))
+#define GLB_REG_GPIO_27_IE            GLB_REG_GPIO_27_IE
+#define GLB_REG_GPIO_27_IE_POS        (16U)
+#define GLB_REG_GPIO_27_IE_LEN        (1U)
+#define GLB_REG_GPIO_27_IE_MSK        (((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS)
+#define GLB_REG_GPIO_27_IE_UMSK       (~(((1U << GLB_REG_GPIO_27_IE_LEN) - 1) << GLB_REG_GPIO_27_IE_POS))
+#define GLB_REG_GPIO_27_SMT           GLB_REG_GPIO_27_SMT
+#define GLB_REG_GPIO_27_SMT_POS       (17U)
+#define GLB_REG_GPIO_27_SMT_LEN       (1U)
+#define GLB_REG_GPIO_27_SMT_MSK       (((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS)
+#define GLB_REG_GPIO_27_SMT_UMSK      (~(((1U << GLB_REG_GPIO_27_SMT_LEN) - 1) << GLB_REG_GPIO_27_SMT_POS))
+#define GLB_REG_GPIO_27_DRV           GLB_REG_GPIO_27_DRV
+#define GLB_REG_GPIO_27_DRV_POS       (18U)
+#define GLB_REG_GPIO_27_DRV_LEN       (2U)
+#define GLB_REG_GPIO_27_DRV_MSK       (((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS)
+#define GLB_REG_GPIO_27_DRV_UMSK      (~(((1U << GLB_REG_GPIO_27_DRV_LEN) - 1) << GLB_REG_GPIO_27_DRV_POS))
+#define GLB_REG_GPIO_27_PU            GLB_REG_GPIO_27_PU
+#define GLB_REG_GPIO_27_PU_POS        (20U)
+#define GLB_REG_GPIO_27_PU_LEN        (1U)
+#define GLB_REG_GPIO_27_PU_MSK        (((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS)
+#define GLB_REG_GPIO_27_PU_UMSK       (~(((1U << GLB_REG_GPIO_27_PU_LEN) - 1) << GLB_REG_GPIO_27_PU_POS))
+#define GLB_REG_GPIO_27_PD            GLB_REG_GPIO_27_PD
+#define GLB_REG_GPIO_27_PD_POS        (21U)
+#define GLB_REG_GPIO_27_PD_LEN        (1U)
+#define GLB_REG_GPIO_27_PD_MSK        (((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS)
+#define GLB_REG_GPIO_27_PD_UMSK       (~(((1U << GLB_REG_GPIO_27_PD_LEN) - 1) << GLB_REG_GPIO_27_PD_POS))
+#define GLB_REG_GPIO_27_FUNC_SEL      GLB_REG_GPIO_27_FUNC_SEL
+#define GLB_REG_GPIO_27_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_27_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_27_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS)
+#define GLB_REG_GPIO_27_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_27_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_27_FUNC_SEL_POS))
+
+/* 0x138 : GPIO_CFGCTL14 */
+#define GLB_GPIO_CFGCTL14_OFFSET      (0x138)
+#define GLB_REG_GPIO_28_IE            GLB_REG_GPIO_28_IE
+#define GLB_REG_GPIO_28_IE_POS        (0U)
+#define GLB_REG_GPIO_28_IE_LEN        (1U)
+#define GLB_REG_GPIO_28_IE_MSK        (((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS)
+#define GLB_REG_GPIO_28_IE_UMSK       (~(((1U << GLB_REG_GPIO_28_IE_LEN) - 1) << GLB_REG_GPIO_28_IE_POS))
+#define GLB_REG_GPIO_28_SMT           GLB_REG_GPIO_28_SMT
+#define GLB_REG_GPIO_28_SMT_POS       (1U)
+#define GLB_REG_GPIO_28_SMT_LEN       (1U)
+#define GLB_REG_GPIO_28_SMT_MSK       (((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS)
+#define GLB_REG_GPIO_28_SMT_UMSK      (~(((1U << GLB_REG_GPIO_28_SMT_LEN) - 1) << GLB_REG_GPIO_28_SMT_POS))
+#define GLB_REG_GPIO_28_DRV           GLB_REG_GPIO_28_DRV
+#define GLB_REG_GPIO_28_DRV_POS       (2U)
+#define GLB_REG_GPIO_28_DRV_LEN       (2U)
+#define GLB_REG_GPIO_28_DRV_MSK       (((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS)
+#define GLB_REG_GPIO_28_DRV_UMSK      (~(((1U << GLB_REG_GPIO_28_DRV_LEN) - 1) << GLB_REG_GPIO_28_DRV_POS))
+#define GLB_REG_GPIO_28_PU            GLB_REG_GPIO_28_PU
+#define GLB_REG_GPIO_28_PU_POS        (4U)
+#define GLB_REG_GPIO_28_PU_LEN        (1U)
+#define GLB_REG_GPIO_28_PU_MSK        (((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS)
+#define GLB_REG_GPIO_28_PU_UMSK       (~(((1U << GLB_REG_GPIO_28_PU_LEN) - 1) << GLB_REG_GPIO_28_PU_POS))
+#define GLB_REG_GPIO_28_PD            GLB_REG_GPIO_28_PD
+#define GLB_REG_GPIO_28_PD_POS        (5U)
+#define GLB_REG_GPIO_28_PD_LEN        (1U)
+#define GLB_REG_GPIO_28_PD_MSK        (((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS)
+#define GLB_REG_GPIO_28_PD_UMSK       (~(((1U << GLB_REG_GPIO_28_PD_LEN) - 1) << GLB_REG_GPIO_28_PD_POS))
+#define GLB_REG_GPIO_28_FUNC_SEL      GLB_REG_GPIO_28_FUNC_SEL
+#define GLB_REG_GPIO_28_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_28_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_28_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS)
+#define GLB_REG_GPIO_28_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_28_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_28_FUNC_SEL_POS))
+#define GLB_REG_GPIO_29_IE            GLB_REG_GPIO_29_IE
+#define GLB_REG_GPIO_29_IE_POS        (16U)
+#define GLB_REG_GPIO_29_IE_LEN        (1U)
+#define GLB_REG_GPIO_29_IE_MSK        (((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS)
+#define GLB_REG_GPIO_29_IE_UMSK       (~(((1U << GLB_REG_GPIO_29_IE_LEN) - 1) << GLB_REG_GPIO_29_IE_POS))
+#define GLB_REG_GPIO_29_SMT           GLB_REG_GPIO_29_SMT
+#define GLB_REG_GPIO_29_SMT_POS       (17U)
+#define GLB_REG_GPIO_29_SMT_LEN       (1U)
+#define GLB_REG_GPIO_29_SMT_MSK       (((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS)
+#define GLB_REG_GPIO_29_SMT_UMSK      (~(((1U << GLB_REG_GPIO_29_SMT_LEN) - 1) << GLB_REG_GPIO_29_SMT_POS))
+#define GLB_REG_GPIO_29_DRV           GLB_REG_GPIO_29_DRV
+#define GLB_REG_GPIO_29_DRV_POS       (18U)
+#define GLB_REG_GPIO_29_DRV_LEN       (2U)
+#define GLB_REG_GPIO_29_DRV_MSK       (((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS)
+#define GLB_REG_GPIO_29_DRV_UMSK      (~(((1U << GLB_REG_GPIO_29_DRV_LEN) - 1) << GLB_REG_GPIO_29_DRV_POS))
+#define GLB_REG_GPIO_29_PU            GLB_REG_GPIO_29_PU
+#define GLB_REG_GPIO_29_PU_POS        (20U)
+#define GLB_REG_GPIO_29_PU_LEN        (1U)
+#define GLB_REG_GPIO_29_PU_MSK        (((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS)
+#define GLB_REG_GPIO_29_PU_UMSK       (~(((1U << GLB_REG_GPIO_29_PU_LEN) - 1) << GLB_REG_GPIO_29_PU_POS))
+#define GLB_REG_GPIO_29_PD            GLB_REG_GPIO_29_PD
+#define GLB_REG_GPIO_29_PD_POS        (21U)
+#define GLB_REG_GPIO_29_PD_LEN        (1U)
+#define GLB_REG_GPIO_29_PD_MSK        (((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS)
+#define GLB_REG_GPIO_29_PD_UMSK       (~(((1U << GLB_REG_GPIO_29_PD_LEN) - 1) << GLB_REG_GPIO_29_PD_POS))
+#define GLB_REG_GPIO_29_FUNC_SEL      GLB_REG_GPIO_29_FUNC_SEL
+#define GLB_REG_GPIO_29_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_29_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_29_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS)
+#define GLB_REG_GPIO_29_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_29_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_29_FUNC_SEL_POS))
+
+/* 0x13C : GPIO_CFGCTL15 */
+#define GLB_GPIO_CFGCTL15_OFFSET      (0x13C)
+#define GLB_REG_GPIO_30_IE            GLB_REG_GPIO_30_IE
+#define GLB_REG_GPIO_30_IE_POS        (0U)
+#define GLB_REG_GPIO_30_IE_LEN        (1U)
+#define GLB_REG_GPIO_30_IE_MSK        (((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS)
+#define GLB_REG_GPIO_30_IE_UMSK       (~(((1U << GLB_REG_GPIO_30_IE_LEN) - 1) << GLB_REG_GPIO_30_IE_POS))
+#define GLB_REG_GPIO_30_SMT           GLB_REG_GPIO_30_SMT
+#define GLB_REG_GPIO_30_SMT_POS       (1U)
+#define GLB_REG_GPIO_30_SMT_LEN       (1U)
+#define GLB_REG_GPIO_30_SMT_MSK       (((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS)
+#define GLB_REG_GPIO_30_SMT_UMSK      (~(((1U << GLB_REG_GPIO_30_SMT_LEN) - 1) << GLB_REG_GPIO_30_SMT_POS))
+#define GLB_REG_GPIO_30_DRV           GLB_REG_GPIO_30_DRV
+#define GLB_REG_GPIO_30_DRV_POS       (2U)
+#define GLB_REG_GPIO_30_DRV_LEN       (2U)
+#define GLB_REG_GPIO_30_DRV_MSK       (((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS)
+#define GLB_REG_GPIO_30_DRV_UMSK      (~(((1U << GLB_REG_GPIO_30_DRV_LEN) - 1) << GLB_REG_GPIO_30_DRV_POS))
+#define GLB_REG_GPIO_30_PU            GLB_REG_GPIO_30_PU
+#define GLB_REG_GPIO_30_PU_POS        (4U)
+#define GLB_REG_GPIO_30_PU_LEN        (1U)
+#define GLB_REG_GPIO_30_PU_MSK        (((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS)
+#define GLB_REG_GPIO_30_PU_UMSK       (~(((1U << GLB_REG_GPIO_30_PU_LEN) - 1) << GLB_REG_GPIO_30_PU_POS))
+#define GLB_REG_GPIO_30_PD            GLB_REG_GPIO_30_PD
+#define GLB_REG_GPIO_30_PD_POS        (5U)
+#define GLB_REG_GPIO_30_PD_LEN        (1U)
+#define GLB_REG_GPIO_30_PD_MSK        (((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS)
+#define GLB_REG_GPIO_30_PD_UMSK       (~(((1U << GLB_REG_GPIO_30_PD_LEN) - 1) << GLB_REG_GPIO_30_PD_POS))
+#define GLB_REG_GPIO_30_FUNC_SEL      GLB_REG_GPIO_30_FUNC_SEL
+#define GLB_REG_GPIO_30_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_30_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_30_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS)
+#define GLB_REG_GPIO_30_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_30_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_30_FUNC_SEL_POS))
+#define GLB_REG_GPIO_31_IE            GLB_REG_GPIO_31_IE
+#define GLB_REG_GPIO_31_IE_POS        (16U)
+#define GLB_REG_GPIO_31_IE_LEN        (1U)
+#define GLB_REG_GPIO_31_IE_MSK        (((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS)
+#define GLB_REG_GPIO_31_IE_UMSK       (~(((1U << GLB_REG_GPIO_31_IE_LEN) - 1) << GLB_REG_GPIO_31_IE_POS))
+#define GLB_REG_GPIO_31_SMT           GLB_REG_GPIO_31_SMT
+#define GLB_REG_GPIO_31_SMT_POS       (17U)
+#define GLB_REG_GPIO_31_SMT_LEN       (1U)
+#define GLB_REG_GPIO_31_SMT_MSK       (((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS)
+#define GLB_REG_GPIO_31_SMT_UMSK      (~(((1U << GLB_REG_GPIO_31_SMT_LEN) - 1) << GLB_REG_GPIO_31_SMT_POS))
+#define GLB_REG_GPIO_31_DRV           GLB_REG_GPIO_31_DRV
+#define GLB_REG_GPIO_31_DRV_POS       (18U)
+#define GLB_REG_GPIO_31_DRV_LEN       (2U)
+#define GLB_REG_GPIO_31_DRV_MSK       (((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS)
+#define GLB_REG_GPIO_31_DRV_UMSK      (~(((1U << GLB_REG_GPIO_31_DRV_LEN) - 1) << GLB_REG_GPIO_31_DRV_POS))
+#define GLB_REG_GPIO_31_PU            GLB_REG_GPIO_31_PU
+#define GLB_REG_GPIO_31_PU_POS        (20U)
+#define GLB_REG_GPIO_31_PU_LEN        (1U)
+#define GLB_REG_GPIO_31_PU_MSK        (((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS)
+#define GLB_REG_GPIO_31_PU_UMSK       (~(((1U << GLB_REG_GPIO_31_PU_LEN) - 1) << GLB_REG_GPIO_31_PU_POS))
+#define GLB_REG_GPIO_31_PD            GLB_REG_GPIO_31_PD
+#define GLB_REG_GPIO_31_PD_POS        (21U)
+#define GLB_REG_GPIO_31_PD_LEN        (1U)
+#define GLB_REG_GPIO_31_PD_MSK        (((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS)
+#define GLB_REG_GPIO_31_PD_UMSK       (~(((1U << GLB_REG_GPIO_31_PD_LEN) - 1) << GLB_REG_GPIO_31_PD_POS))
+#define GLB_REG_GPIO_31_FUNC_SEL      GLB_REG_GPIO_31_FUNC_SEL
+#define GLB_REG_GPIO_31_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_31_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_31_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS)
+#define GLB_REG_GPIO_31_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_31_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_31_FUNC_SEL_POS))
+
+/* 0x140 : GPIO_CFGCTL16 */
+#define GLB_GPIO_CFGCTL16_OFFSET (0x140)
+#define GLB_REG_GPIO_32_IE       GLB_REG_GPIO_32_IE
+#define GLB_REG_GPIO_32_IE_POS   (0U)
+#define GLB_REG_GPIO_32_IE_LEN   (1U)
+#define GLB_REG_GPIO_32_IE_MSK   (((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS)
+#define GLB_REG_GPIO_32_IE_UMSK  (~(((1U << GLB_REG_GPIO_32_IE_LEN) - 1) << GLB_REG_GPIO_32_IE_POS))
+#define GLB_REG_GPIO_32_SMT      GLB_REG_GPIO_32_SMT
+#define GLB_REG_GPIO_32_SMT_POS  (1U)
+#define GLB_REG_GPIO_32_SMT_LEN  (1U)
+#define GLB_REG_GPIO_32_SMT_MSK  (((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS)
+#define GLB_REG_GPIO_32_SMT_UMSK (~(((1U << GLB_REG_GPIO_32_SMT_LEN) - 1) << GLB_REG_GPIO_32_SMT_POS))
+#define GLB_REG_GPIO_32_DRV      GLB_REG_GPIO_32_DRV
+#define GLB_REG_GPIO_32_DRV_POS  (2U)
+#define GLB_REG_GPIO_32_DRV_LEN  (2U)
+#define GLB_REG_GPIO_32_DRV_MSK  (((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS)
+#define GLB_REG_GPIO_32_DRV_UMSK (~(((1U << GLB_REG_GPIO_32_DRV_LEN) - 1) << GLB_REG_GPIO_32_DRV_POS))
+#define GLB_REG_GPIO_32_PU       GLB_REG_GPIO_32_PU
+#define GLB_REG_GPIO_32_PU_POS   (4U)
+#define GLB_REG_GPIO_32_PU_LEN   (1U)
+#define GLB_REG_GPIO_32_PU_MSK   (((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS)
+#define GLB_REG_GPIO_32_PU_UMSK  (~(((1U << GLB_REG_GPIO_32_PU_LEN) - 1) << GLB_REG_GPIO_32_PU_POS))
+#define GLB_REG_GPIO_32_PD       GLB_REG_GPIO_32_PD
+#define GLB_REG_GPIO_32_PD_POS   (5U)
+#define GLB_REG_GPIO_32_PD_LEN   (1U)
+#define GLB_REG_GPIO_32_PD_MSK   (((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS)
+#define GLB_REG_GPIO_32_PD_UMSK  (~(((1U << GLB_REG_GPIO_32_PD_LEN) - 1) << GLB_REG_GPIO_32_PD_POS))
+#define GLB_REG_GPIO_33_IE       GLB_REG_GPIO_33_IE
+#define GLB_REG_GPIO_33_IE_POS   (16U)
+#define GLB_REG_GPIO_33_IE_LEN   (1U)
+#define GLB_REG_GPIO_33_IE_MSK   (((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS)
+#define GLB_REG_GPIO_33_IE_UMSK  (~(((1U << GLB_REG_GPIO_33_IE_LEN) - 1) << GLB_REG_GPIO_33_IE_POS))
+#define GLB_REG_GPIO_33_SMT      GLB_REG_GPIO_33_SMT
+#define GLB_REG_GPIO_33_SMT_POS  (17U)
+#define GLB_REG_GPIO_33_SMT_LEN  (1U)
+#define GLB_REG_GPIO_33_SMT_MSK  (((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS)
+#define GLB_REG_GPIO_33_SMT_UMSK (~(((1U << GLB_REG_GPIO_33_SMT_LEN) - 1) << GLB_REG_GPIO_33_SMT_POS))
+#define GLB_REG_GPIO_33_DRV      GLB_REG_GPIO_33_DRV
+#define GLB_REG_GPIO_33_DRV_POS  (18U)
+#define GLB_REG_GPIO_33_DRV_LEN  (2U)
+#define GLB_REG_GPIO_33_DRV_MSK  (((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS)
+#define GLB_REG_GPIO_33_DRV_UMSK (~(((1U << GLB_REG_GPIO_33_DRV_LEN) - 1) << GLB_REG_GPIO_33_DRV_POS))
+#define GLB_REG_GPIO_33_PU       GLB_REG_GPIO_33_PU
+#define GLB_REG_GPIO_33_PU_POS   (20U)
+#define GLB_REG_GPIO_33_PU_LEN   (1U)
+#define GLB_REG_GPIO_33_PU_MSK   (((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS)
+#define GLB_REG_GPIO_33_PU_UMSK  (~(((1U << GLB_REG_GPIO_33_PU_LEN) - 1) << GLB_REG_GPIO_33_PU_POS))
+#define GLB_REG_GPIO_33_PD       GLB_REG_GPIO_33_PD
+#define GLB_REG_GPIO_33_PD_POS   (21U)
+#define GLB_REG_GPIO_33_PD_LEN   (1U)
+#define GLB_REG_GPIO_33_PD_MSK   (((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS)
+#define GLB_REG_GPIO_33_PD_UMSK  (~(((1U << GLB_REG_GPIO_33_PD_LEN) - 1) << GLB_REG_GPIO_33_PD_POS))
+
+/* 0x144 : GPIO_CFGCTL17 */
+#define GLB_GPIO_CFGCTL17_OFFSET (0x144)
+#define GLB_REG_GPIO_34_IE       GLB_REG_GPIO_34_IE
+#define GLB_REG_GPIO_34_IE_POS   (0U)
+#define GLB_REG_GPIO_34_IE_LEN   (1U)
+#define GLB_REG_GPIO_34_IE_MSK   (((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS)
+#define GLB_REG_GPIO_34_IE_UMSK  (~(((1U << GLB_REG_GPIO_34_IE_LEN) - 1) << GLB_REG_GPIO_34_IE_POS))
+#define GLB_REG_GPIO_34_SMT      GLB_REG_GPIO_34_SMT
+#define GLB_REG_GPIO_34_SMT_POS  (1U)
+#define GLB_REG_GPIO_34_SMT_LEN  (1U)
+#define GLB_REG_GPIO_34_SMT_MSK  (((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS)
+#define GLB_REG_GPIO_34_SMT_UMSK (~(((1U << GLB_REG_GPIO_34_SMT_LEN) - 1) << GLB_REG_GPIO_34_SMT_POS))
+#define GLB_REG_GPIO_34_DRV      GLB_REG_GPIO_34_DRV
+#define GLB_REG_GPIO_34_DRV_POS  (2U)
+#define GLB_REG_GPIO_34_DRV_LEN  (2U)
+#define GLB_REG_GPIO_34_DRV_MSK  (((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS)
+#define GLB_REG_GPIO_34_DRV_UMSK (~(((1U << GLB_REG_GPIO_34_DRV_LEN) - 1) << GLB_REG_GPIO_34_DRV_POS))
+#define GLB_REG_GPIO_34_PU       GLB_REG_GPIO_34_PU
+#define GLB_REG_GPIO_34_PU_POS   (4U)
+#define GLB_REG_GPIO_34_PU_LEN   (1U)
+#define GLB_REG_GPIO_34_PU_MSK   (((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS)
+#define GLB_REG_GPIO_34_PU_UMSK  (~(((1U << GLB_REG_GPIO_34_PU_LEN) - 1) << GLB_REG_GPIO_34_PU_POS))
+#define GLB_REG_GPIO_34_PD       GLB_REG_GPIO_34_PD
+#define GLB_REG_GPIO_34_PD_POS   (5U)
+#define GLB_REG_GPIO_34_PD_LEN   (1U)
+#define GLB_REG_GPIO_34_PD_MSK   (((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS)
+#define GLB_REG_GPIO_34_PD_UMSK  (~(((1U << GLB_REG_GPIO_34_PD_LEN) - 1) << GLB_REG_GPIO_34_PD_POS))
+#define GLB_REG_GPIO_35_IE       GLB_REG_GPIO_35_IE
+#define GLB_REG_GPIO_35_IE_POS   (16U)
+#define GLB_REG_GPIO_35_IE_LEN   (1U)
+#define GLB_REG_GPIO_35_IE_MSK   (((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS)
+#define GLB_REG_GPIO_35_IE_UMSK  (~(((1U << GLB_REG_GPIO_35_IE_LEN) - 1) << GLB_REG_GPIO_35_IE_POS))
+#define GLB_REG_GPIO_35_SMT      GLB_REG_GPIO_35_SMT
+#define GLB_REG_GPIO_35_SMT_POS  (17U)
+#define GLB_REG_GPIO_35_SMT_LEN  (1U)
+#define GLB_REG_GPIO_35_SMT_MSK  (((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS)
+#define GLB_REG_GPIO_35_SMT_UMSK (~(((1U << GLB_REG_GPIO_35_SMT_LEN) - 1) << GLB_REG_GPIO_35_SMT_POS))
+#define GLB_REG_GPIO_35_DRV      GLB_REG_GPIO_35_DRV
+#define GLB_REG_GPIO_35_DRV_POS  (18U)
+#define GLB_REG_GPIO_35_DRV_LEN  (2U)
+#define GLB_REG_GPIO_35_DRV_MSK  (((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS)
+#define GLB_REG_GPIO_35_DRV_UMSK (~(((1U << GLB_REG_GPIO_35_DRV_LEN) - 1) << GLB_REG_GPIO_35_DRV_POS))
+#define GLB_REG_GPIO_35_PU       GLB_REG_GPIO_35_PU
+#define GLB_REG_GPIO_35_PU_POS   (20U)
+#define GLB_REG_GPIO_35_PU_LEN   (1U)
+#define GLB_REG_GPIO_35_PU_MSK   (((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS)
+#define GLB_REG_GPIO_35_PU_UMSK  (~(((1U << GLB_REG_GPIO_35_PU_LEN) - 1) << GLB_REG_GPIO_35_PU_POS))
+#define GLB_REG_GPIO_35_PD       GLB_REG_GPIO_35_PD
+#define GLB_REG_GPIO_35_PD_POS   (21U)
+#define GLB_REG_GPIO_35_PD_LEN   (1U)
+#define GLB_REG_GPIO_35_PD_MSK   (((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS)
+#define GLB_REG_GPIO_35_PD_UMSK  (~(((1U << GLB_REG_GPIO_35_PD_LEN) - 1) << GLB_REG_GPIO_35_PD_POS))
+
+/* 0x148 : GPIO_CFGCTL18 */
+#define GLB_GPIO_CFGCTL18_OFFSET (0x148)
+#define GLB_REG_GPIO_36_IE       GLB_REG_GPIO_36_IE
+#define GLB_REG_GPIO_36_IE_POS   (0U)
+#define GLB_REG_GPIO_36_IE_LEN   (1U)
+#define GLB_REG_GPIO_36_IE_MSK   (((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS)
+#define GLB_REG_GPIO_36_IE_UMSK  (~(((1U << GLB_REG_GPIO_36_IE_LEN) - 1) << GLB_REG_GPIO_36_IE_POS))
+#define GLB_REG_GPIO_36_SMT      GLB_REG_GPIO_36_SMT
+#define GLB_REG_GPIO_36_SMT_POS  (1U)
+#define GLB_REG_GPIO_36_SMT_LEN  (1U)
+#define GLB_REG_GPIO_36_SMT_MSK  (((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS)
+#define GLB_REG_GPIO_36_SMT_UMSK (~(((1U << GLB_REG_GPIO_36_SMT_LEN) - 1) << GLB_REG_GPIO_36_SMT_POS))
+#define GLB_REG_GPIO_36_DRV      GLB_REG_GPIO_36_DRV
+#define GLB_REG_GPIO_36_DRV_POS  (2U)
+#define GLB_REG_GPIO_36_DRV_LEN  (2U)
+#define GLB_REG_GPIO_36_DRV_MSK  (((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS)
+#define GLB_REG_GPIO_36_DRV_UMSK (~(((1U << GLB_REG_GPIO_36_DRV_LEN) - 1) << GLB_REG_GPIO_36_DRV_POS))
+#define GLB_REG_GPIO_36_PU       GLB_REG_GPIO_36_PU
+#define GLB_REG_GPIO_36_PU_POS   (4U)
+#define GLB_REG_GPIO_36_PU_LEN   (1U)
+#define GLB_REG_GPIO_36_PU_MSK   (((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS)
+#define GLB_REG_GPIO_36_PU_UMSK  (~(((1U << GLB_REG_GPIO_36_PU_LEN) - 1) << GLB_REG_GPIO_36_PU_POS))
+#define GLB_REG_GPIO_36_PD       GLB_REG_GPIO_36_PD
+#define GLB_REG_GPIO_36_PD_POS   (5U)
+#define GLB_REG_GPIO_36_PD_LEN   (1U)
+#define GLB_REG_GPIO_36_PD_MSK   (((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS)
+#define GLB_REG_GPIO_36_PD_UMSK  (~(((1U << GLB_REG_GPIO_36_PD_LEN) - 1) << GLB_REG_GPIO_36_PD_POS))
+#define GLB_REG_GPIO_37_IE       GLB_REG_GPIO_37_IE
+#define GLB_REG_GPIO_37_IE_POS   (16U)
+#define GLB_REG_GPIO_37_IE_LEN   (1U)
+#define GLB_REG_GPIO_37_IE_MSK   (((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS)
+#define GLB_REG_GPIO_37_IE_UMSK  (~(((1U << GLB_REG_GPIO_37_IE_LEN) - 1) << GLB_REG_GPIO_37_IE_POS))
+#define GLB_REG_GPIO_37_SMT      GLB_REG_GPIO_37_SMT
+#define GLB_REG_GPIO_37_SMT_POS  (17U)
+#define GLB_REG_GPIO_37_SMT_LEN  (1U)
+#define GLB_REG_GPIO_37_SMT_MSK  (((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS)
+#define GLB_REG_GPIO_37_SMT_UMSK (~(((1U << GLB_REG_GPIO_37_SMT_LEN) - 1) << GLB_REG_GPIO_37_SMT_POS))
+#define GLB_REG_GPIO_37_DRV      GLB_REG_GPIO_37_DRV
+#define GLB_REG_GPIO_37_DRV_POS  (18U)
+#define GLB_REG_GPIO_37_DRV_LEN  (2U)
+#define GLB_REG_GPIO_37_DRV_MSK  (((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS)
+#define GLB_REG_GPIO_37_DRV_UMSK (~(((1U << GLB_REG_GPIO_37_DRV_LEN) - 1) << GLB_REG_GPIO_37_DRV_POS))
+#define GLB_REG_GPIO_37_PU       GLB_REG_GPIO_37_PU
+#define GLB_REG_GPIO_37_PU_POS   (20U)
+#define GLB_REG_GPIO_37_PU_LEN   (1U)
+#define GLB_REG_GPIO_37_PU_MSK   (((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS)
+#define GLB_REG_GPIO_37_PU_UMSK  (~(((1U << GLB_REG_GPIO_37_PU_LEN) - 1) << GLB_REG_GPIO_37_PU_POS))
+#define GLB_REG_GPIO_37_PD       GLB_REG_GPIO_37_PD
+#define GLB_REG_GPIO_37_PD_POS   (21U)
+#define GLB_REG_GPIO_37_PD_LEN   (1U)
+#define GLB_REG_GPIO_37_PD_MSK   (((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS)
+#define GLB_REG_GPIO_37_PD_UMSK  (~(((1U << GLB_REG_GPIO_37_PD_LEN) - 1) << GLB_REG_GPIO_37_PD_POS))
+
+/* 0x180 : GPIO_CFGCTL30 */
+#define GLB_GPIO_CFGCTL30_OFFSET (0x180)
+#define GLB_REG_GPIO_0_I         GLB_REG_GPIO_0_I
+#define GLB_REG_GPIO_0_I_POS     (0U)
+#define GLB_REG_GPIO_0_I_LEN     (1U)
+#define GLB_REG_GPIO_0_I_MSK     (((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS)
+#define GLB_REG_GPIO_0_I_UMSK    (~(((1U << GLB_REG_GPIO_0_I_LEN) - 1) << GLB_REG_GPIO_0_I_POS))
+#define GLB_REG_GPIO_1_I         GLB_REG_GPIO_1_I
+#define GLB_REG_GPIO_1_I_POS     (1U)
+#define GLB_REG_GPIO_1_I_LEN     (1U)
+#define GLB_REG_GPIO_1_I_MSK     (((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS)
+#define GLB_REG_GPIO_1_I_UMSK    (~(((1U << GLB_REG_GPIO_1_I_LEN) - 1) << GLB_REG_GPIO_1_I_POS))
+#define GLB_REG_GPIO_2_I         GLB_REG_GPIO_2_I
+#define GLB_REG_GPIO_2_I_POS     (2U)
+#define GLB_REG_GPIO_2_I_LEN     (1U)
+#define GLB_REG_GPIO_2_I_MSK     (((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS)
+#define GLB_REG_GPIO_2_I_UMSK    (~(((1U << GLB_REG_GPIO_2_I_LEN) - 1) << GLB_REG_GPIO_2_I_POS))
+#define GLB_REG_GPIO_3_I         GLB_REG_GPIO_3_I
+#define GLB_REG_GPIO_3_I_POS     (3U)
+#define GLB_REG_GPIO_3_I_LEN     (1U)
+#define GLB_REG_GPIO_3_I_MSK     (((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS)
+#define GLB_REG_GPIO_3_I_UMSK    (~(((1U << GLB_REG_GPIO_3_I_LEN) - 1) << GLB_REG_GPIO_3_I_POS))
+#define GLB_REG_GPIO_4_I         GLB_REG_GPIO_4_I
+#define GLB_REG_GPIO_4_I_POS     (4U)
+#define GLB_REG_GPIO_4_I_LEN     (1U)
+#define GLB_REG_GPIO_4_I_MSK     (((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS)
+#define GLB_REG_GPIO_4_I_UMSK    (~(((1U << GLB_REG_GPIO_4_I_LEN) - 1) << GLB_REG_GPIO_4_I_POS))
+#define GLB_REG_GPIO_5_I         GLB_REG_GPIO_5_I
+#define GLB_REG_GPIO_5_I_POS     (5U)
+#define GLB_REG_GPIO_5_I_LEN     (1U)
+#define GLB_REG_GPIO_5_I_MSK     (((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS)
+#define GLB_REG_GPIO_5_I_UMSK    (~(((1U << GLB_REG_GPIO_5_I_LEN) - 1) << GLB_REG_GPIO_5_I_POS))
+#define GLB_REG_GPIO_6_I         GLB_REG_GPIO_6_I
+#define GLB_REG_GPIO_6_I_POS     (6U)
+#define GLB_REG_GPIO_6_I_LEN     (1U)
+#define GLB_REG_GPIO_6_I_MSK     (((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS)
+#define GLB_REG_GPIO_6_I_UMSK    (~(((1U << GLB_REG_GPIO_6_I_LEN) - 1) << GLB_REG_GPIO_6_I_POS))
+#define GLB_REG_GPIO_7_I         GLB_REG_GPIO_7_I
+#define GLB_REG_GPIO_7_I_POS     (7U)
+#define GLB_REG_GPIO_7_I_LEN     (1U)
+#define GLB_REG_GPIO_7_I_MSK     (((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS)
+#define GLB_REG_GPIO_7_I_UMSK    (~(((1U << GLB_REG_GPIO_7_I_LEN) - 1) << GLB_REG_GPIO_7_I_POS))
+#define GLB_REG_GPIO_8_I         GLB_REG_GPIO_8_I
+#define GLB_REG_GPIO_8_I_POS     (8U)
+#define GLB_REG_GPIO_8_I_LEN     (1U)
+#define GLB_REG_GPIO_8_I_MSK     (((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS)
+#define GLB_REG_GPIO_8_I_UMSK    (~(((1U << GLB_REG_GPIO_8_I_LEN) - 1) << GLB_REG_GPIO_8_I_POS))
+#define GLB_REG_GPIO_9_I         GLB_REG_GPIO_9_I
+#define GLB_REG_GPIO_9_I_POS     (9U)
+#define GLB_REG_GPIO_9_I_LEN     (1U)
+#define GLB_REG_GPIO_9_I_MSK     (((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS)
+#define GLB_REG_GPIO_9_I_UMSK    (~(((1U << GLB_REG_GPIO_9_I_LEN) - 1) << GLB_REG_GPIO_9_I_POS))
+#define GLB_REG_GPIO_10_I        GLB_REG_GPIO_10_I
+#define GLB_REG_GPIO_10_I_POS    (10U)
+#define GLB_REG_GPIO_10_I_LEN    (1U)
+#define GLB_REG_GPIO_10_I_MSK    (((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS)
+#define GLB_REG_GPIO_10_I_UMSK   (~(((1U << GLB_REG_GPIO_10_I_LEN) - 1) << GLB_REG_GPIO_10_I_POS))
+#define GLB_REG_GPIO_11_I        GLB_REG_GPIO_11_I
+#define GLB_REG_GPIO_11_I_POS    (11U)
+#define GLB_REG_GPIO_11_I_LEN    (1U)
+#define GLB_REG_GPIO_11_I_MSK    (((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS)
+#define GLB_REG_GPIO_11_I_UMSK   (~(((1U << GLB_REG_GPIO_11_I_LEN) - 1) << GLB_REG_GPIO_11_I_POS))
+#define GLB_REG_GPIO_12_I        GLB_REG_GPIO_12_I
+#define GLB_REG_GPIO_12_I_POS    (12U)
+#define GLB_REG_GPIO_12_I_LEN    (1U)
+#define GLB_REG_GPIO_12_I_MSK    (((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS)
+#define GLB_REG_GPIO_12_I_UMSK   (~(((1U << GLB_REG_GPIO_12_I_LEN) - 1) << GLB_REG_GPIO_12_I_POS))
+#define GLB_REG_GPIO_13_I        GLB_REG_GPIO_13_I
+#define GLB_REG_GPIO_13_I_POS    (13U)
+#define GLB_REG_GPIO_13_I_LEN    (1U)
+#define GLB_REG_GPIO_13_I_MSK    (((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS)
+#define GLB_REG_GPIO_13_I_UMSK   (~(((1U << GLB_REG_GPIO_13_I_LEN) - 1) << GLB_REG_GPIO_13_I_POS))
+#define GLB_REG_GPIO_14_I        GLB_REG_GPIO_14_I
+#define GLB_REG_GPIO_14_I_POS    (14U)
+#define GLB_REG_GPIO_14_I_LEN    (1U)
+#define GLB_REG_GPIO_14_I_MSK    (((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS)
+#define GLB_REG_GPIO_14_I_UMSK   (~(((1U << GLB_REG_GPIO_14_I_LEN) - 1) << GLB_REG_GPIO_14_I_POS))
+#define GLB_REG_GPIO_15_I        GLB_REG_GPIO_15_I
+#define GLB_REG_GPIO_15_I_POS    (15U)
+#define GLB_REG_GPIO_15_I_LEN    (1U)
+#define GLB_REG_GPIO_15_I_MSK    (((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS)
+#define GLB_REG_GPIO_15_I_UMSK   (~(((1U << GLB_REG_GPIO_15_I_LEN) - 1) << GLB_REG_GPIO_15_I_POS))
+#define GLB_REG_GPIO_16_I        GLB_REG_GPIO_16_I
+#define GLB_REG_GPIO_16_I_POS    (16U)
+#define GLB_REG_GPIO_16_I_LEN    (1U)
+#define GLB_REG_GPIO_16_I_MSK    (((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS)
+#define GLB_REG_GPIO_16_I_UMSK   (~(((1U << GLB_REG_GPIO_16_I_LEN) - 1) << GLB_REG_GPIO_16_I_POS))
+#define GLB_REG_GPIO_17_I        GLB_REG_GPIO_17_I
+#define GLB_REG_GPIO_17_I_POS    (17U)
+#define GLB_REG_GPIO_17_I_LEN    (1U)
+#define GLB_REG_GPIO_17_I_MSK    (((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS)
+#define GLB_REG_GPIO_17_I_UMSK   (~(((1U << GLB_REG_GPIO_17_I_LEN) - 1) << GLB_REG_GPIO_17_I_POS))
+#define GLB_REG_GPIO_18_I        GLB_REG_GPIO_18_I
+#define GLB_REG_GPIO_18_I_POS    (18U)
+#define GLB_REG_GPIO_18_I_LEN    (1U)
+#define GLB_REG_GPIO_18_I_MSK    (((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS)
+#define GLB_REG_GPIO_18_I_UMSK   (~(((1U << GLB_REG_GPIO_18_I_LEN) - 1) << GLB_REG_GPIO_18_I_POS))
+#define GLB_REG_GPIO_19_I        GLB_REG_GPIO_19_I
+#define GLB_REG_GPIO_19_I_POS    (19U)
+#define GLB_REG_GPIO_19_I_LEN    (1U)
+#define GLB_REG_GPIO_19_I_MSK    (((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS)
+#define GLB_REG_GPIO_19_I_UMSK   (~(((1U << GLB_REG_GPIO_19_I_LEN) - 1) << GLB_REG_GPIO_19_I_POS))
+#define GLB_REG_GPIO_20_I        GLB_REG_GPIO_20_I
+#define GLB_REG_GPIO_20_I_POS    (20U)
+#define GLB_REG_GPIO_20_I_LEN    (1U)
+#define GLB_REG_GPIO_20_I_MSK    (((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS)
+#define GLB_REG_GPIO_20_I_UMSK   (~(((1U << GLB_REG_GPIO_20_I_LEN) - 1) << GLB_REG_GPIO_20_I_POS))
+#define GLB_REG_GPIO_21_I        GLB_REG_GPIO_21_I
+#define GLB_REG_GPIO_21_I_POS    (21U)
+#define GLB_REG_GPIO_21_I_LEN    (1U)
+#define GLB_REG_GPIO_21_I_MSK    (((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS)
+#define GLB_REG_GPIO_21_I_UMSK   (~(((1U << GLB_REG_GPIO_21_I_LEN) - 1) << GLB_REG_GPIO_21_I_POS))
+#define GLB_REG_GPIO_22_I        GLB_REG_GPIO_22_I
+#define GLB_REG_GPIO_22_I_POS    (22U)
+#define GLB_REG_GPIO_22_I_LEN    (1U)
+#define GLB_REG_GPIO_22_I_MSK    (((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS)
+#define GLB_REG_GPIO_22_I_UMSK   (~(((1U << GLB_REG_GPIO_22_I_LEN) - 1) << GLB_REG_GPIO_22_I_POS))
+#define GLB_REG_GPIO_23_I        GLB_REG_GPIO_23_I
+#define GLB_REG_GPIO_23_I_POS    (23U)
+#define GLB_REG_GPIO_23_I_LEN    (1U)
+#define GLB_REG_GPIO_23_I_MSK    (((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS)
+#define GLB_REG_GPIO_23_I_UMSK   (~(((1U << GLB_REG_GPIO_23_I_LEN) - 1) << GLB_REG_GPIO_23_I_POS))
+#define GLB_REG_GPIO_24_I        GLB_REG_GPIO_24_I
+#define GLB_REG_GPIO_24_I_POS    (24U)
+#define GLB_REG_GPIO_24_I_LEN    (1U)
+#define GLB_REG_GPIO_24_I_MSK    (((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS)
+#define GLB_REG_GPIO_24_I_UMSK   (~(((1U << GLB_REG_GPIO_24_I_LEN) - 1) << GLB_REG_GPIO_24_I_POS))
+#define GLB_REG_GPIO_25_I        GLB_REG_GPIO_25_I
+#define GLB_REG_GPIO_25_I_POS    (25U)
+#define GLB_REG_GPIO_25_I_LEN    (1U)
+#define GLB_REG_GPIO_25_I_MSK    (((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS)
+#define GLB_REG_GPIO_25_I_UMSK   (~(((1U << GLB_REG_GPIO_25_I_LEN) - 1) << GLB_REG_GPIO_25_I_POS))
+#define GLB_REG_GPIO_26_I        GLB_REG_GPIO_26_I
+#define GLB_REG_GPIO_26_I_POS    (26U)
+#define GLB_REG_GPIO_26_I_LEN    (1U)
+#define GLB_REG_GPIO_26_I_MSK    (((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS)
+#define GLB_REG_GPIO_26_I_UMSK   (~(((1U << GLB_REG_GPIO_26_I_LEN) - 1) << GLB_REG_GPIO_26_I_POS))
+#define GLB_REG_GPIO_27_I        GLB_REG_GPIO_27_I
+#define GLB_REG_GPIO_27_I_POS    (27U)
+#define GLB_REG_GPIO_27_I_LEN    (1U)
+#define GLB_REG_GPIO_27_I_MSK    (((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS)
+#define GLB_REG_GPIO_27_I_UMSK   (~(((1U << GLB_REG_GPIO_27_I_LEN) - 1) << GLB_REG_GPIO_27_I_POS))
+#define GLB_REG_GPIO_28_I        GLB_REG_GPIO_28_I
+#define GLB_REG_GPIO_28_I_POS    (28U)
+#define GLB_REG_GPIO_28_I_LEN    (1U)
+#define GLB_REG_GPIO_28_I_MSK    (((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS)
+#define GLB_REG_GPIO_28_I_UMSK   (~(((1U << GLB_REG_GPIO_28_I_LEN) - 1) << GLB_REG_GPIO_28_I_POS))
+#define GLB_REG_GPIO_29_I        GLB_REG_GPIO_29_I
+#define GLB_REG_GPIO_29_I_POS    (29U)
+#define GLB_REG_GPIO_29_I_LEN    (1U)
+#define GLB_REG_GPIO_29_I_MSK    (((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS)
+#define GLB_REG_GPIO_29_I_UMSK   (~(((1U << GLB_REG_GPIO_29_I_LEN) - 1) << GLB_REG_GPIO_29_I_POS))
+#define GLB_REG_GPIO_30_I        GLB_REG_GPIO_30_I
+#define GLB_REG_GPIO_30_I_POS    (30U)
+#define GLB_REG_GPIO_30_I_LEN    (1U)
+#define GLB_REG_GPIO_30_I_MSK    (((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS)
+#define GLB_REG_GPIO_30_I_UMSK   (~(((1U << GLB_REG_GPIO_30_I_LEN) - 1) << GLB_REG_GPIO_30_I_POS))
+#define GLB_REG_GPIO_31_I        GLB_REG_GPIO_31_I
+#define GLB_REG_GPIO_31_I_POS    (31U)
+#define GLB_REG_GPIO_31_I_LEN    (1U)
+#define GLB_REG_GPIO_31_I_MSK    (((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS)
+#define GLB_REG_GPIO_31_I_UMSK   (~(((1U << GLB_REG_GPIO_31_I_LEN) - 1) << GLB_REG_GPIO_31_I_POS))
+
+/* 0x184 : GPIO_CFGCTL31 */
+#define GLB_GPIO_CFGCTL31_OFFSET (0x184)
+
+/* 0x188 : GPIO_CFGCTL32 */
+#define GLB_GPIO_CFGCTL32_OFFSET (0x188)
+#define GLB_REG_GPIO_0_O         GLB_REG_GPIO_0_O
+#define GLB_REG_GPIO_0_O_POS     (0U)
+#define GLB_REG_GPIO_0_O_LEN     (1U)
+#define GLB_REG_GPIO_0_O_MSK     (((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS)
+#define GLB_REG_GPIO_0_O_UMSK    (~(((1U << GLB_REG_GPIO_0_O_LEN) - 1) << GLB_REG_GPIO_0_O_POS))
+#define GLB_REG_GPIO_1_O         GLB_REG_GPIO_1_O
+#define GLB_REG_GPIO_1_O_POS     (1U)
+#define GLB_REG_GPIO_1_O_LEN     (1U)
+#define GLB_REG_GPIO_1_O_MSK     (((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS)
+#define GLB_REG_GPIO_1_O_UMSK    (~(((1U << GLB_REG_GPIO_1_O_LEN) - 1) << GLB_REG_GPIO_1_O_POS))
+#define GLB_REG_GPIO_2_O         GLB_REG_GPIO_2_O
+#define GLB_REG_GPIO_2_O_POS     (2U)
+#define GLB_REG_GPIO_2_O_LEN     (1U)
+#define GLB_REG_GPIO_2_O_MSK     (((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS)
+#define GLB_REG_GPIO_2_O_UMSK    (~(((1U << GLB_REG_GPIO_2_O_LEN) - 1) << GLB_REG_GPIO_2_O_POS))
+#define GLB_REG_GPIO_3_O         GLB_REG_GPIO_3_O
+#define GLB_REG_GPIO_3_O_POS     (3U)
+#define GLB_REG_GPIO_3_O_LEN     (1U)
+#define GLB_REG_GPIO_3_O_MSK     (((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS)
+#define GLB_REG_GPIO_3_O_UMSK    (~(((1U << GLB_REG_GPIO_3_O_LEN) - 1) << GLB_REG_GPIO_3_O_POS))
+#define GLB_REG_GPIO_4_O         GLB_REG_GPIO_4_O
+#define GLB_REG_GPIO_4_O_POS     (4U)
+#define GLB_REG_GPIO_4_O_LEN     (1U)
+#define GLB_REG_GPIO_4_O_MSK     (((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS)
+#define GLB_REG_GPIO_4_O_UMSK    (~(((1U << GLB_REG_GPIO_4_O_LEN) - 1) << GLB_REG_GPIO_4_O_POS))
+#define GLB_REG_GPIO_5_O         GLB_REG_GPIO_5_O
+#define GLB_REG_GPIO_5_O_POS     (5U)
+#define GLB_REG_GPIO_5_O_LEN     (1U)
+#define GLB_REG_GPIO_5_O_MSK     (((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS)
+#define GLB_REG_GPIO_5_O_UMSK    (~(((1U << GLB_REG_GPIO_5_O_LEN) - 1) << GLB_REG_GPIO_5_O_POS))
+#define GLB_REG_GPIO_6_O         GLB_REG_GPIO_6_O
+#define GLB_REG_GPIO_6_O_POS     (6U)
+#define GLB_REG_GPIO_6_O_LEN     (1U)
+#define GLB_REG_GPIO_6_O_MSK     (((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS)
+#define GLB_REG_GPIO_6_O_UMSK    (~(((1U << GLB_REG_GPIO_6_O_LEN) - 1) << GLB_REG_GPIO_6_O_POS))
+#define GLB_REG_GPIO_7_O         GLB_REG_GPIO_7_O
+#define GLB_REG_GPIO_7_O_POS     (7U)
+#define GLB_REG_GPIO_7_O_LEN     (1U)
+#define GLB_REG_GPIO_7_O_MSK     (((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS)
+#define GLB_REG_GPIO_7_O_UMSK    (~(((1U << GLB_REG_GPIO_7_O_LEN) - 1) << GLB_REG_GPIO_7_O_POS))
+#define GLB_REG_GPIO_8_O         GLB_REG_GPIO_8_O
+#define GLB_REG_GPIO_8_O_POS     (8U)
+#define GLB_REG_GPIO_8_O_LEN     (1U)
+#define GLB_REG_GPIO_8_O_MSK     (((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS)
+#define GLB_REG_GPIO_8_O_UMSK    (~(((1U << GLB_REG_GPIO_8_O_LEN) - 1) << GLB_REG_GPIO_8_O_POS))
+#define GLB_REG_GPIO_9_O         GLB_REG_GPIO_9_O
+#define GLB_REG_GPIO_9_O_POS     (9U)
+#define GLB_REG_GPIO_9_O_LEN     (1U)
+#define GLB_REG_GPIO_9_O_MSK     (((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS)
+#define GLB_REG_GPIO_9_O_UMSK    (~(((1U << GLB_REG_GPIO_9_O_LEN) - 1) << GLB_REG_GPIO_9_O_POS))
+#define GLB_REG_GPIO_10_O        GLB_REG_GPIO_10_O
+#define GLB_REG_GPIO_10_O_POS    (10U)
+#define GLB_REG_GPIO_10_O_LEN    (1U)
+#define GLB_REG_GPIO_10_O_MSK    (((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS)
+#define GLB_REG_GPIO_10_O_UMSK   (~(((1U << GLB_REG_GPIO_10_O_LEN) - 1) << GLB_REG_GPIO_10_O_POS))
+#define GLB_REG_GPIO_11_O        GLB_REG_GPIO_11_O
+#define GLB_REG_GPIO_11_O_POS    (11U)
+#define GLB_REG_GPIO_11_O_LEN    (1U)
+#define GLB_REG_GPIO_11_O_MSK    (((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS)
+#define GLB_REG_GPIO_11_O_UMSK   (~(((1U << GLB_REG_GPIO_11_O_LEN) - 1) << GLB_REG_GPIO_11_O_POS))
+#define GLB_REG_GPIO_12_O        GLB_REG_GPIO_12_O
+#define GLB_REG_GPIO_12_O_POS    (12U)
+#define GLB_REG_GPIO_12_O_LEN    (1U)
+#define GLB_REG_GPIO_12_O_MSK    (((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS)
+#define GLB_REG_GPIO_12_O_UMSK   (~(((1U << GLB_REG_GPIO_12_O_LEN) - 1) << GLB_REG_GPIO_12_O_POS))
+#define GLB_REG_GPIO_13_O        GLB_REG_GPIO_13_O
+#define GLB_REG_GPIO_13_O_POS    (13U)
+#define GLB_REG_GPIO_13_O_LEN    (1U)
+#define GLB_REG_GPIO_13_O_MSK    (((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS)
+#define GLB_REG_GPIO_13_O_UMSK   (~(((1U << GLB_REG_GPIO_13_O_LEN) - 1) << GLB_REG_GPIO_13_O_POS))
+#define GLB_REG_GPIO_14_O        GLB_REG_GPIO_14_O
+#define GLB_REG_GPIO_14_O_POS    (14U)
+#define GLB_REG_GPIO_14_O_LEN    (1U)
+#define GLB_REG_GPIO_14_O_MSK    (((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS)
+#define GLB_REG_GPIO_14_O_UMSK   (~(((1U << GLB_REG_GPIO_14_O_LEN) - 1) << GLB_REG_GPIO_14_O_POS))
+#define GLB_REG_GPIO_15_O        GLB_REG_GPIO_15_O
+#define GLB_REG_GPIO_15_O_POS    (15U)
+#define GLB_REG_GPIO_15_O_LEN    (1U)
+#define GLB_REG_GPIO_15_O_MSK    (((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS)
+#define GLB_REG_GPIO_15_O_UMSK   (~(((1U << GLB_REG_GPIO_15_O_LEN) - 1) << GLB_REG_GPIO_15_O_POS))
+#define GLB_REG_GPIO_16_O        GLB_REG_GPIO_16_O
+#define GLB_REG_GPIO_16_O_POS    (16U)
+#define GLB_REG_GPIO_16_O_LEN    (1U)
+#define GLB_REG_GPIO_16_O_MSK    (((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS)
+#define GLB_REG_GPIO_16_O_UMSK   (~(((1U << GLB_REG_GPIO_16_O_LEN) - 1) << GLB_REG_GPIO_16_O_POS))
+#define GLB_REG_GPIO_17_O        GLB_REG_GPIO_17_O
+#define GLB_REG_GPIO_17_O_POS    (17U)
+#define GLB_REG_GPIO_17_O_LEN    (1U)
+#define GLB_REG_GPIO_17_O_MSK    (((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS)
+#define GLB_REG_GPIO_17_O_UMSK   (~(((1U << GLB_REG_GPIO_17_O_LEN) - 1) << GLB_REG_GPIO_17_O_POS))
+#define GLB_REG_GPIO_18_O        GLB_REG_GPIO_18_O
+#define GLB_REG_GPIO_18_O_POS    (18U)
+#define GLB_REG_GPIO_18_O_LEN    (1U)
+#define GLB_REG_GPIO_18_O_MSK    (((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS)
+#define GLB_REG_GPIO_18_O_UMSK   (~(((1U << GLB_REG_GPIO_18_O_LEN) - 1) << GLB_REG_GPIO_18_O_POS))
+#define GLB_REG_GPIO_19_O        GLB_REG_GPIO_19_O
+#define GLB_REG_GPIO_19_O_POS    (19U)
+#define GLB_REG_GPIO_19_O_LEN    (1U)
+#define GLB_REG_GPIO_19_O_MSK    (((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS)
+#define GLB_REG_GPIO_19_O_UMSK   (~(((1U << GLB_REG_GPIO_19_O_LEN) - 1) << GLB_REG_GPIO_19_O_POS))
+#define GLB_REG_GPIO_20_O        GLB_REG_GPIO_20_O
+#define GLB_REG_GPIO_20_O_POS    (20U)
+#define GLB_REG_GPIO_20_O_LEN    (1U)
+#define GLB_REG_GPIO_20_O_MSK    (((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS)
+#define GLB_REG_GPIO_20_O_UMSK   (~(((1U << GLB_REG_GPIO_20_O_LEN) - 1) << GLB_REG_GPIO_20_O_POS))
+#define GLB_REG_GPIO_21_O        GLB_REG_GPIO_21_O
+#define GLB_REG_GPIO_21_O_POS    (21U)
+#define GLB_REG_GPIO_21_O_LEN    (1U)
+#define GLB_REG_GPIO_21_O_MSK    (((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS)
+#define GLB_REG_GPIO_21_O_UMSK   (~(((1U << GLB_REG_GPIO_21_O_LEN) - 1) << GLB_REG_GPIO_21_O_POS))
+#define GLB_REG_GPIO_22_O        GLB_REG_GPIO_22_O
+#define GLB_REG_GPIO_22_O_POS    (22U)
+#define GLB_REG_GPIO_22_O_LEN    (1U)
+#define GLB_REG_GPIO_22_O_MSK    (((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS)
+#define GLB_REG_GPIO_22_O_UMSK   (~(((1U << GLB_REG_GPIO_22_O_LEN) - 1) << GLB_REG_GPIO_22_O_POS))
+#define GLB_REG_GPIO_23_O        GLB_REG_GPIO_23_O
+#define GLB_REG_GPIO_23_O_POS    (23U)
+#define GLB_REG_GPIO_23_O_LEN    (1U)
+#define GLB_REG_GPIO_23_O_MSK    (((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS)
+#define GLB_REG_GPIO_23_O_UMSK   (~(((1U << GLB_REG_GPIO_23_O_LEN) - 1) << GLB_REG_GPIO_23_O_POS))
+#define GLB_REG_GPIO_24_O        GLB_REG_GPIO_24_O
+#define GLB_REG_GPIO_24_O_POS    (24U)
+#define GLB_REG_GPIO_24_O_LEN    (1U)
+#define GLB_REG_GPIO_24_O_MSK    (((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS)
+#define GLB_REG_GPIO_24_O_UMSK   (~(((1U << GLB_REG_GPIO_24_O_LEN) - 1) << GLB_REG_GPIO_24_O_POS))
+#define GLB_REG_GPIO_25_O        GLB_REG_GPIO_25_O
+#define GLB_REG_GPIO_25_O_POS    (25U)
+#define GLB_REG_GPIO_25_O_LEN    (1U)
+#define GLB_REG_GPIO_25_O_MSK    (((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS)
+#define GLB_REG_GPIO_25_O_UMSK   (~(((1U << GLB_REG_GPIO_25_O_LEN) - 1) << GLB_REG_GPIO_25_O_POS))
+#define GLB_REG_GPIO_26_O        GLB_REG_GPIO_26_O
+#define GLB_REG_GPIO_26_O_POS    (26U)
+#define GLB_REG_GPIO_26_O_LEN    (1U)
+#define GLB_REG_GPIO_26_O_MSK    (((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS)
+#define GLB_REG_GPIO_26_O_UMSK   (~(((1U << GLB_REG_GPIO_26_O_LEN) - 1) << GLB_REG_GPIO_26_O_POS))
+#define GLB_REG_GPIO_27_O        GLB_REG_GPIO_27_O
+#define GLB_REG_GPIO_27_O_POS    (27U)
+#define GLB_REG_GPIO_27_O_LEN    (1U)
+#define GLB_REG_GPIO_27_O_MSK    (((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS)
+#define GLB_REG_GPIO_27_O_UMSK   (~(((1U << GLB_REG_GPIO_27_O_LEN) - 1) << GLB_REG_GPIO_27_O_POS))
+#define GLB_REG_GPIO_28_O        GLB_REG_GPIO_28_O
+#define GLB_REG_GPIO_28_O_POS    (28U)
+#define GLB_REG_GPIO_28_O_LEN    (1U)
+#define GLB_REG_GPIO_28_O_MSK    (((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS)
+#define GLB_REG_GPIO_28_O_UMSK   (~(((1U << GLB_REG_GPIO_28_O_LEN) - 1) << GLB_REG_GPIO_28_O_POS))
+#define GLB_REG_GPIO_29_O        GLB_REG_GPIO_29_O
+#define GLB_REG_GPIO_29_O_POS    (29U)
+#define GLB_REG_GPIO_29_O_LEN    (1U)
+#define GLB_REG_GPIO_29_O_MSK    (((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS)
+#define GLB_REG_GPIO_29_O_UMSK   (~(((1U << GLB_REG_GPIO_29_O_LEN) - 1) << GLB_REG_GPIO_29_O_POS))
+#define GLB_REG_GPIO_30_O        GLB_REG_GPIO_30_O
+#define GLB_REG_GPIO_30_O_POS    (30U)
+#define GLB_REG_GPIO_30_O_LEN    (1U)
+#define GLB_REG_GPIO_30_O_MSK    (((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS)
+#define GLB_REG_GPIO_30_O_UMSK   (~(((1U << GLB_REG_GPIO_30_O_LEN) - 1) << GLB_REG_GPIO_30_O_POS))
+#define GLB_REG_GPIO_31_O        GLB_REG_GPIO_31_O
+#define GLB_REG_GPIO_31_O_POS    (31U)
+#define GLB_REG_GPIO_31_O_LEN    (1U)
+#define GLB_REG_GPIO_31_O_MSK    (((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS)
+#define GLB_REG_GPIO_31_O_UMSK   (~(((1U << GLB_REG_GPIO_31_O_LEN) - 1) << GLB_REG_GPIO_31_O_POS))
+
+/* 0x18C : GPIO_CFGCTL33 */
+#define GLB_GPIO_CFGCTL33_OFFSET (0x18C)
+
+/* 0x190 : GPIO_CFGCTL34 */
+#define GLB_GPIO_CFGCTL34_OFFSET (0x190)
+#define GLB_REG_GPIO_0_OE        GLB_REG_GPIO_0_OE
+#define GLB_REG_GPIO_0_OE_POS    (0U)
+#define GLB_REG_GPIO_0_OE_LEN    (1U)
+#define GLB_REG_GPIO_0_OE_MSK    (((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS)
+#define GLB_REG_GPIO_0_OE_UMSK   (~(((1U << GLB_REG_GPIO_0_OE_LEN) - 1) << GLB_REG_GPIO_0_OE_POS))
+#define GLB_REG_GPIO_1_OE        GLB_REG_GPIO_1_OE
+#define GLB_REG_GPIO_1_OE_POS    (1U)
+#define GLB_REG_GPIO_1_OE_LEN    (1U)
+#define GLB_REG_GPIO_1_OE_MSK    (((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS)
+#define GLB_REG_GPIO_1_OE_UMSK   (~(((1U << GLB_REG_GPIO_1_OE_LEN) - 1) << GLB_REG_GPIO_1_OE_POS))
+#define GLB_REG_GPIO_2_OE        GLB_REG_GPIO_2_OE
+#define GLB_REG_GPIO_2_OE_POS    (2U)
+#define GLB_REG_GPIO_2_OE_LEN    (1U)
+#define GLB_REG_GPIO_2_OE_MSK    (((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS)
+#define GLB_REG_GPIO_2_OE_UMSK   (~(((1U << GLB_REG_GPIO_2_OE_LEN) - 1) << GLB_REG_GPIO_2_OE_POS))
+#define GLB_REG_GPIO_3_OE        GLB_REG_GPIO_3_OE
+#define GLB_REG_GPIO_3_OE_POS    (3U)
+#define GLB_REG_GPIO_3_OE_LEN    (1U)
+#define GLB_REG_GPIO_3_OE_MSK    (((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS)
+#define GLB_REG_GPIO_3_OE_UMSK   (~(((1U << GLB_REG_GPIO_3_OE_LEN) - 1) << GLB_REG_GPIO_3_OE_POS))
+#define GLB_REG_GPIO_4_OE        GLB_REG_GPIO_4_OE
+#define GLB_REG_GPIO_4_OE_POS    (4U)
+#define GLB_REG_GPIO_4_OE_LEN    (1U)
+#define GLB_REG_GPIO_4_OE_MSK    (((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS)
+#define GLB_REG_GPIO_4_OE_UMSK   (~(((1U << GLB_REG_GPIO_4_OE_LEN) - 1) << GLB_REG_GPIO_4_OE_POS))
+#define GLB_REG_GPIO_5_OE        GLB_REG_GPIO_5_OE
+#define GLB_REG_GPIO_5_OE_POS    (5U)
+#define GLB_REG_GPIO_5_OE_LEN    (1U)
+#define GLB_REG_GPIO_5_OE_MSK    (((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS)
+#define GLB_REG_GPIO_5_OE_UMSK   (~(((1U << GLB_REG_GPIO_5_OE_LEN) - 1) << GLB_REG_GPIO_5_OE_POS))
+#define GLB_REG_GPIO_6_OE        GLB_REG_GPIO_6_OE
+#define GLB_REG_GPIO_6_OE_POS    (6U)
+#define GLB_REG_GPIO_6_OE_LEN    (1U)
+#define GLB_REG_GPIO_6_OE_MSK    (((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS)
+#define GLB_REG_GPIO_6_OE_UMSK   (~(((1U << GLB_REG_GPIO_6_OE_LEN) - 1) << GLB_REG_GPIO_6_OE_POS))
+#define GLB_REG_GPIO_7_OE        GLB_REG_GPIO_7_OE
+#define GLB_REG_GPIO_7_OE_POS    (7U)
+#define GLB_REG_GPIO_7_OE_LEN    (1U)
+#define GLB_REG_GPIO_7_OE_MSK    (((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS)
+#define GLB_REG_GPIO_7_OE_UMSK   (~(((1U << GLB_REG_GPIO_7_OE_LEN) - 1) << GLB_REG_GPIO_7_OE_POS))
+#define GLB_REG_GPIO_8_OE        GLB_REG_GPIO_8_OE
+#define GLB_REG_GPIO_8_OE_POS    (8U)
+#define GLB_REG_GPIO_8_OE_LEN    (1U)
+#define GLB_REG_GPIO_8_OE_MSK    (((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS)
+#define GLB_REG_GPIO_8_OE_UMSK   (~(((1U << GLB_REG_GPIO_8_OE_LEN) - 1) << GLB_REG_GPIO_8_OE_POS))
+#define GLB_REG_GPIO_9_OE        GLB_REG_GPIO_9_OE
+#define GLB_REG_GPIO_9_OE_POS    (9U)
+#define GLB_REG_GPIO_9_OE_LEN    (1U)
+#define GLB_REG_GPIO_9_OE_MSK    (((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS)
+#define GLB_REG_GPIO_9_OE_UMSK   (~(((1U << GLB_REG_GPIO_9_OE_LEN) - 1) << GLB_REG_GPIO_9_OE_POS))
+#define GLB_REG_GPIO_10_OE       GLB_REG_GPIO_10_OE
+#define GLB_REG_GPIO_10_OE_POS   (10U)
+#define GLB_REG_GPIO_10_OE_LEN   (1U)
+#define GLB_REG_GPIO_10_OE_MSK   (((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS)
+#define GLB_REG_GPIO_10_OE_UMSK  (~(((1U << GLB_REG_GPIO_10_OE_LEN) - 1) << GLB_REG_GPIO_10_OE_POS))
+#define GLB_REG_GPIO_11_OE       GLB_REG_GPIO_11_OE
+#define GLB_REG_GPIO_11_OE_POS   (11U)
+#define GLB_REG_GPIO_11_OE_LEN   (1U)
+#define GLB_REG_GPIO_11_OE_MSK   (((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS)
+#define GLB_REG_GPIO_11_OE_UMSK  (~(((1U << GLB_REG_GPIO_11_OE_LEN) - 1) << GLB_REG_GPIO_11_OE_POS))
+#define GLB_REG_GPIO_12_OE       GLB_REG_GPIO_12_OE
+#define GLB_REG_GPIO_12_OE_POS   (12U)
+#define GLB_REG_GPIO_12_OE_LEN   (1U)
+#define GLB_REG_GPIO_12_OE_MSK   (((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS)
+#define GLB_REG_GPIO_12_OE_UMSK  (~(((1U << GLB_REG_GPIO_12_OE_LEN) - 1) << GLB_REG_GPIO_12_OE_POS))
+#define GLB_REG_GPIO_13_OE       GLB_REG_GPIO_13_OE
+#define GLB_REG_GPIO_13_OE_POS   (13U)
+#define GLB_REG_GPIO_13_OE_LEN   (1U)
+#define GLB_REG_GPIO_13_OE_MSK   (((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS)
+#define GLB_REG_GPIO_13_OE_UMSK  (~(((1U << GLB_REG_GPIO_13_OE_LEN) - 1) << GLB_REG_GPIO_13_OE_POS))
+#define GLB_REG_GPIO_14_OE       GLB_REG_GPIO_14_OE
+#define GLB_REG_GPIO_14_OE_POS   (14U)
+#define GLB_REG_GPIO_14_OE_LEN   (1U)
+#define GLB_REG_GPIO_14_OE_MSK   (((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS)
+#define GLB_REG_GPIO_14_OE_UMSK  (~(((1U << GLB_REG_GPIO_14_OE_LEN) - 1) << GLB_REG_GPIO_14_OE_POS))
+#define GLB_REG_GPIO_15_OE       GLB_REG_GPIO_15_OE
+#define GLB_REG_GPIO_15_OE_POS   (15U)
+#define GLB_REG_GPIO_15_OE_LEN   (1U)
+#define GLB_REG_GPIO_15_OE_MSK   (((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS)
+#define GLB_REG_GPIO_15_OE_UMSK  (~(((1U << GLB_REG_GPIO_15_OE_LEN) - 1) << GLB_REG_GPIO_15_OE_POS))
+#define GLB_REG_GPIO_16_OE       GLB_REG_GPIO_16_OE
+#define GLB_REG_GPIO_16_OE_POS   (16U)
+#define GLB_REG_GPIO_16_OE_LEN   (1U)
+#define GLB_REG_GPIO_16_OE_MSK   (((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS)
+#define GLB_REG_GPIO_16_OE_UMSK  (~(((1U << GLB_REG_GPIO_16_OE_LEN) - 1) << GLB_REG_GPIO_16_OE_POS))
+#define GLB_REG_GPIO_17_OE       GLB_REG_GPIO_17_OE
+#define GLB_REG_GPIO_17_OE_POS   (17U)
+#define GLB_REG_GPIO_17_OE_LEN   (1U)
+#define GLB_REG_GPIO_17_OE_MSK   (((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS)
+#define GLB_REG_GPIO_17_OE_UMSK  (~(((1U << GLB_REG_GPIO_17_OE_LEN) - 1) << GLB_REG_GPIO_17_OE_POS))
+#define GLB_REG_GPIO_18_OE       GLB_REG_GPIO_18_OE
+#define GLB_REG_GPIO_18_OE_POS   (18U)
+#define GLB_REG_GPIO_18_OE_LEN   (1U)
+#define GLB_REG_GPIO_18_OE_MSK   (((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS)
+#define GLB_REG_GPIO_18_OE_UMSK  (~(((1U << GLB_REG_GPIO_18_OE_LEN) - 1) << GLB_REG_GPIO_18_OE_POS))
+#define GLB_REG_GPIO_19_OE       GLB_REG_GPIO_19_OE
+#define GLB_REG_GPIO_19_OE_POS   (19U)
+#define GLB_REG_GPIO_19_OE_LEN   (1U)
+#define GLB_REG_GPIO_19_OE_MSK   (((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS)
+#define GLB_REG_GPIO_19_OE_UMSK  (~(((1U << GLB_REG_GPIO_19_OE_LEN) - 1) << GLB_REG_GPIO_19_OE_POS))
+#define GLB_REG_GPIO_20_OE       GLB_REG_GPIO_20_OE
+#define GLB_REG_GPIO_20_OE_POS   (20U)
+#define GLB_REG_GPIO_20_OE_LEN   (1U)
+#define GLB_REG_GPIO_20_OE_MSK   (((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS)
+#define GLB_REG_GPIO_20_OE_UMSK  (~(((1U << GLB_REG_GPIO_20_OE_LEN) - 1) << GLB_REG_GPIO_20_OE_POS))
+#define GLB_REG_GPIO_21_OE       GLB_REG_GPIO_21_OE
+#define GLB_REG_GPIO_21_OE_POS   (21U)
+#define GLB_REG_GPIO_21_OE_LEN   (1U)
+#define GLB_REG_GPIO_21_OE_MSK   (((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS)
+#define GLB_REG_GPIO_21_OE_UMSK  (~(((1U << GLB_REG_GPIO_21_OE_LEN) - 1) << GLB_REG_GPIO_21_OE_POS))
+#define GLB_REG_GPIO_22_OE       GLB_REG_GPIO_22_OE
+#define GLB_REG_GPIO_22_OE_POS   (22U)
+#define GLB_REG_GPIO_22_OE_LEN   (1U)
+#define GLB_REG_GPIO_22_OE_MSK   (((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS)
+#define GLB_REG_GPIO_22_OE_UMSK  (~(((1U << GLB_REG_GPIO_22_OE_LEN) - 1) << GLB_REG_GPIO_22_OE_POS))
+#define GLB_REG_GPIO_23_OE       GLB_REG_GPIO_23_OE
+#define GLB_REG_GPIO_23_OE_POS   (23U)
+#define GLB_REG_GPIO_23_OE_LEN   (1U)
+#define GLB_REG_GPIO_23_OE_MSK   (((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS)
+#define GLB_REG_GPIO_23_OE_UMSK  (~(((1U << GLB_REG_GPIO_23_OE_LEN) - 1) << GLB_REG_GPIO_23_OE_POS))
+#define GLB_REG_GPIO_24_OE       GLB_REG_GPIO_24_OE
+#define GLB_REG_GPIO_24_OE_POS   (24U)
+#define GLB_REG_GPIO_24_OE_LEN   (1U)
+#define GLB_REG_GPIO_24_OE_MSK   (((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS)
+#define GLB_REG_GPIO_24_OE_UMSK  (~(((1U << GLB_REG_GPIO_24_OE_LEN) - 1) << GLB_REG_GPIO_24_OE_POS))
+#define GLB_REG_GPIO_25_OE       GLB_REG_GPIO_25_OE
+#define GLB_REG_GPIO_25_OE_POS   (25U)
+#define GLB_REG_GPIO_25_OE_LEN   (1U)
+#define GLB_REG_GPIO_25_OE_MSK   (((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS)
+#define GLB_REG_GPIO_25_OE_UMSK  (~(((1U << GLB_REG_GPIO_25_OE_LEN) - 1) << GLB_REG_GPIO_25_OE_POS))
+#define GLB_REG_GPIO_26_OE       GLB_REG_GPIO_26_OE
+#define GLB_REG_GPIO_26_OE_POS   (26U)
+#define GLB_REG_GPIO_26_OE_LEN   (1U)
+#define GLB_REG_GPIO_26_OE_MSK   (((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS)
+#define GLB_REG_GPIO_26_OE_UMSK  (~(((1U << GLB_REG_GPIO_26_OE_LEN) - 1) << GLB_REG_GPIO_26_OE_POS))
+#define GLB_REG_GPIO_27_OE       GLB_REG_GPIO_27_OE
+#define GLB_REG_GPIO_27_OE_POS   (27U)
+#define GLB_REG_GPIO_27_OE_LEN   (1U)
+#define GLB_REG_GPIO_27_OE_MSK   (((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS)
+#define GLB_REG_GPIO_27_OE_UMSK  (~(((1U << GLB_REG_GPIO_27_OE_LEN) - 1) << GLB_REG_GPIO_27_OE_POS))
+#define GLB_REG_GPIO_28_OE       GLB_REG_GPIO_28_OE
+#define GLB_REG_GPIO_28_OE_POS   (28U)
+#define GLB_REG_GPIO_28_OE_LEN   (1U)
+#define GLB_REG_GPIO_28_OE_MSK   (((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS)
+#define GLB_REG_GPIO_28_OE_UMSK  (~(((1U << GLB_REG_GPIO_28_OE_LEN) - 1) << GLB_REG_GPIO_28_OE_POS))
+#define GLB_REG_GPIO_29_OE       GLB_REG_GPIO_29_OE
+#define GLB_REG_GPIO_29_OE_POS   (29U)
+#define GLB_REG_GPIO_29_OE_LEN   (1U)
+#define GLB_REG_GPIO_29_OE_MSK   (((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS)
+#define GLB_REG_GPIO_29_OE_UMSK  (~(((1U << GLB_REG_GPIO_29_OE_LEN) - 1) << GLB_REG_GPIO_29_OE_POS))
+#define GLB_REG_GPIO_30_OE       GLB_REG_GPIO_30_OE
+#define GLB_REG_GPIO_30_OE_POS   (30U)
+#define GLB_REG_GPIO_30_OE_LEN   (1U)
+#define GLB_REG_GPIO_30_OE_MSK   (((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS)
+#define GLB_REG_GPIO_30_OE_UMSK  (~(((1U << GLB_REG_GPIO_30_OE_LEN) - 1) << GLB_REG_GPIO_30_OE_POS))
+#define GLB_REG_GPIO_31_OE       GLB_REG_GPIO_31_OE
+#define GLB_REG_GPIO_31_OE_POS   (31U)
+#define GLB_REG_GPIO_31_OE_LEN   (1U)
+#define GLB_REG_GPIO_31_OE_MSK   (((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS)
+#define GLB_REG_GPIO_31_OE_UMSK  (~(((1U << GLB_REG_GPIO_31_OE_LEN) - 1) << GLB_REG_GPIO_31_OE_POS))
+
+/* 0x194 : GPIO_CFGCTL35 */
+#define GLB_GPIO_CFGCTL35_OFFSET (0x194)
+
+/* 0x1A0 : GPIO_INT_MASK1 */
+#define GLB_GPIO_INT_MASK1_OFFSET   (0x1A0)
+#define GLB_REG_GPIO_INT_MASK1      GLB_REG_GPIO_INT_MASK1
+#define GLB_REG_GPIO_INT_MASK1_POS  (0U)
+#define GLB_REG_GPIO_INT_MASK1_LEN  (32U)
+#define GLB_REG_GPIO_INT_MASK1_MSK  (((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS)
+#define GLB_REG_GPIO_INT_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT_MASK1_LEN) - 1) << GLB_REG_GPIO_INT_MASK1_POS))
+
+/* 0x1A8 : GPIO_INT_STAT1 */
+#define GLB_GPIO_INT_STAT1_OFFSET (0x1A8)
+#define GLB_GPIO_INT_STAT1        GLB_GPIO_INT_STAT1
+#define GLB_GPIO_INT_STAT1_POS    (0U)
+#define GLB_GPIO_INT_STAT1_LEN    (32U)
+#define GLB_GPIO_INT_STAT1_MSK    (((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS)
+#define GLB_GPIO_INT_STAT1_UMSK   (~(((1U << GLB_GPIO_INT_STAT1_LEN) - 1) << GLB_GPIO_INT_STAT1_POS))
+
+/* 0x1B0 : GPIO_INT_CLR1 */
+#define GLB_GPIO_INT_CLR1_OFFSET   (0x1B0)
+#define GLB_REG_GPIO_INT_CLR1      GLB_REG_GPIO_INT_CLR1
+#define GLB_REG_GPIO_INT_CLR1_POS  (0U)
+#define GLB_REG_GPIO_INT_CLR1_LEN  (32U)
+#define GLB_REG_GPIO_INT_CLR1_MSK  (((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS)
+#define GLB_REG_GPIO_INT_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT_CLR1_LEN) - 1) << GLB_REG_GPIO_INT_CLR1_POS))
+
+/* 0x1C0 : GPIO_INT_MODE_SET1 */
+#define GLB_GPIO_INT_MODE_SET1_OFFSET   (0x1C0)
+#define GLB_REG_GPIO_INT_MODE_SET1      GLB_REG_GPIO_INT_MODE_SET1
+#define GLB_REG_GPIO_INT_MODE_SET1_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET1_LEN  (30U)
+#define GLB_REG_GPIO_INT_MODE_SET1_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS)
+#define GLB_REG_GPIO_INT_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET1_POS))
+
+/* 0x1C4 : GPIO_INT_MODE_SET2 */
+#define GLB_GPIO_INT_MODE_SET2_OFFSET   (0x1C4)
+#define GLB_REG_GPIO_INT_MODE_SET2      GLB_REG_GPIO_INT_MODE_SET2
+#define GLB_REG_GPIO_INT_MODE_SET2_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET2_LEN  (30U)
+#define GLB_REG_GPIO_INT_MODE_SET2_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS)
+#define GLB_REG_GPIO_INT_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET2_POS))
+
+/* 0x1C8 : GPIO_INT_MODE_SET3 */
+#define GLB_GPIO_INT_MODE_SET3_OFFSET   (0x1C8)
+#define GLB_REG_GPIO_INT_MODE_SET3      GLB_REG_GPIO_INT_MODE_SET3
+#define GLB_REG_GPIO_INT_MODE_SET3_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET3_LEN  (30U)
+#define GLB_REG_GPIO_INT_MODE_SET3_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS)
+#define GLB_REG_GPIO_INT_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET3_POS))
+
+/* 0x1CC : GPIO_INT_MODE_SET4 */
+#define GLB_GPIO_INT_MODE_SET4_OFFSET   (0x1CC)
+#define GLB_REG_GPIO_INT_MODE_SET4      GLB_REG_GPIO_INT_MODE_SET4
+#define GLB_REG_GPIO_INT_MODE_SET4_POS  (0U)
+#define GLB_REG_GPIO_INT_MODE_SET4_LEN  (6U)
+#define GLB_REG_GPIO_INT_MODE_SET4_MSK  (((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS)
+#define GLB_REG_GPIO_INT_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT_MODE_SET4_POS))
+
+/* 0x1D0 : GPIO_INT2_MASK1 */
+#define GLB_GPIO_INT2_MASK1_OFFSET   (0x1D0)
+#define GLB_REG_GPIO_INT2_MASK1      GLB_REG_GPIO_INT2_MASK1
+#define GLB_REG_GPIO_INT2_MASK1_POS  (0U)
+#define GLB_REG_GPIO_INT2_MASK1_LEN  (32U)
+#define GLB_REG_GPIO_INT2_MASK1_MSK  (((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS)
+#define GLB_REG_GPIO_INT2_MASK1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MASK1_LEN) - 1) << GLB_REG_GPIO_INT2_MASK1_POS))
+
+/* 0x1D4 : GPIO_INT2_STAT1 */
+#define GLB_GPIO_INT2_STAT1_OFFSET (0x1D4)
+#define GLB_GPIO_INT2_STAT1        GLB_GPIO_INT2_STAT1
+#define GLB_GPIO_INT2_STAT1_POS    (0U)
+#define GLB_GPIO_INT2_STAT1_LEN    (32U)
+#define GLB_GPIO_INT2_STAT1_MSK    (((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS)
+#define GLB_GPIO_INT2_STAT1_UMSK   (~(((1U << GLB_GPIO_INT2_STAT1_LEN) - 1) << GLB_GPIO_INT2_STAT1_POS))
+
+/* 0x1D8 : GPIO_INT2_CLR1 */
+#define GLB_GPIO_INT2_CLR1_OFFSET   (0x1D8)
+#define GLB_REG_GPIO_INT2_CLR1      GLB_REG_GPIO_INT2_CLR1
+#define GLB_REG_GPIO_INT2_CLR1_POS  (0U)
+#define GLB_REG_GPIO_INT2_CLR1_LEN  (32U)
+#define GLB_REG_GPIO_INT2_CLR1_MSK  (((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS)
+#define GLB_REG_GPIO_INT2_CLR1_UMSK (~(((1U << GLB_REG_GPIO_INT2_CLR1_LEN) - 1) << GLB_REG_GPIO_INT2_CLR1_POS))
+
+/* 0x1DC : GPIO_INT2_MODE_SET1 */
+#define GLB_GPIO_INT2_MODE_SET1_OFFSET   (0x1DC)
+#define GLB_REG_GPIO_INT2_MODE_SET1      GLB_REG_GPIO_INT2_MODE_SET1
+#define GLB_REG_GPIO_INT2_MODE_SET1_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET1_LEN  (30U)
+#define GLB_REG_GPIO_INT2_MODE_SET1_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET1_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET1_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET1_POS))
+
+/* 0x1E0 : GPIO_INT2_MODE_SET2 */
+#define GLB_GPIO_INT2_MODE_SET2_OFFSET   (0x1E0)
+#define GLB_REG_GPIO_INT2_MODE_SET2      GLB_REG_GPIO_INT2_MODE_SET2
+#define GLB_REG_GPIO_INT2_MODE_SET2_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET2_LEN  (30U)
+#define GLB_REG_GPIO_INT2_MODE_SET2_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET2_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET2_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET2_POS))
+
+/* 0x1E4 : GPIO_INT2_MODE_SET3 */
+#define GLB_GPIO_INT2_MODE_SET3_OFFSET   (0x1E4)
+#define GLB_REG_GPIO_INT2_MODE_SET3      GLB_REG_GPIO_INT2_MODE_SET3
+#define GLB_REG_GPIO_INT2_MODE_SET3_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET3_LEN  (30U)
+#define GLB_REG_GPIO_INT2_MODE_SET3_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET3_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET3_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET3_POS))
+
+/* 0x1E8 : GPIO_INT2_MODE_SET4 */
+#define GLB_GPIO_INT2_MODE_SET4_OFFSET   (0x1E8)
+#define GLB_REG_GPIO_INT2_MODE_SET4      GLB_REG_GPIO_INT2_MODE_SET4
+#define GLB_REG_GPIO_INT2_MODE_SET4_POS  (0U)
+#define GLB_REG_GPIO_INT2_MODE_SET4_LEN  (6U)
+#define GLB_REG_GPIO_INT2_MODE_SET4_MSK  (((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS)
+#define GLB_REG_GPIO_INT2_MODE_SET4_UMSK (~(((1U << GLB_REG_GPIO_INT2_MODE_SET4_LEN) - 1) << GLB_REG_GPIO_INT2_MODE_SET4_POS))
+
+/* 0x200 : dll */
+#define GLB_DLL_OFFSET               (0x200)
+#define GLB_DTEST_EN_DLL_REFCLK      GLB_DTEST_EN_DLL_REFCLK
+#define GLB_DTEST_EN_DLL_REFCLK_POS  (0U)
+#define GLB_DTEST_EN_DLL_REFCLK_LEN  (1U)
+#define GLB_DTEST_EN_DLL_REFCLK_MSK  (((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS)
+#define GLB_DTEST_EN_DLL_REFCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_REFCLK_LEN) - 1) << GLB_DTEST_EN_DLL_REFCLK_POS))
+#define GLB_DTEST_EN_DLL_OUTCLK      GLB_DTEST_EN_DLL_OUTCLK
+#define GLB_DTEST_EN_DLL_OUTCLK_POS  (1U)
+#define GLB_DTEST_EN_DLL_OUTCLK_LEN  (1U)
+#define GLB_DTEST_EN_DLL_OUTCLK_MSK  (((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS)
+#define GLB_DTEST_EN_DLL_OUTCLK_UMSK (~(((1U << GLB_DTEST_EN_DLL_OUTCLK_LEN) - 1) << GLB_DTEST_EN_DLL_OUTCLK_POS))
+#define GLB_TEN_DLL                  GLB_TEN_DLL
+#define GLB_TEN_DLL_POS              (2U)
+#define GLB_TEN_DLL_LEN              (1U)
+#define GLB_TEN_DLL_MSK              (((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS)
+#define GLB_TEN_DLL_UMSK             (~(((1U << GLB_TEN_DLL_LEN) - 1) << GLB_TEN_DLL_POS))
+#define GLB_DLL_CLK_MMDIV_EN         GLB_DLL_CLK_MMDIV_EN
+#define GLB_DLL_CLK_MMDIV_EN_POS     (3U)
+#define GLB_DLL_CLK_MMDIV_EN_LEN     (1U)
+#define GLB_DLL_CLK_MMDIV_EN_MSK     (((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS)
+#define GLB_DLL_CLK_MMDIV_EN_UMSK    (~(((1U << GLB_DLL_CLK_MMDIV_EN_LEN) - 1) << GLB_DLL_CLK_MMDIV_EN_POS))
+#define GLB_DLL_CLK_288M_EN          GLB_DLL_CLK_288M_EN
+#define GLB_DLL_CLK_288M_EN_POS      (4U)
+#define GLB_DLL_CLK_288M_EN_LEN      (1U)
+#define GLB_DLL_CLK_288M_EN_MSK      (((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS)
+#define GLB_DLL_CLK_288M_EN_UMSK     (~(((1U << GLB_DLL_CLK_288M_EN_LEN) - 1) << GLB_DLL_CLK_288M_EN_POS))
+#define GLB_DLL_CLK_144M_EN          GLB_DLL_CLK_144M_EN
+#define GLB_DLL_CLK_144M_EN_POS      (5U)
+#define GLB_DLL_CLK_144M_EN_LEN      (1U)
+#define GLB_DLL_CLK_144M_EN_MSK      (((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS)
+#define GLB_DLL_CLK_144M_EN_UMSK     (~(((1U << GLB_DLL_CLK_144M_EN_LEN) - 1) << GLB_DLL_CLK_144M_EN_POS))
+#define GLB_DLL_CLK_96M_EN           GLB_DLL_CLK_96M_EN
+#define GLB_DLL_CLK_96M_EN_POS       (6U)
+#define GLB_DLL_CLK_96M_EN_LEN       (1U)
+#define GLB_DLL_CLK_96M_EN_MSK       (((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS)
+#define GLB_DLL_CLK_96M_EN_UMSK      (~(((1U << GLB_DLL_CLK_96M_EN_LEN) - 1) << GLB_DLL_CLK_96M_EN_POS))
+#define GLB_DLL_CLK_57P6M_EN         GLB_DLL_CLK_57P6M_EN
+#define GLB_DLL_CLK_57P6M_EN_POS     (7U)
+#define GLB_DLL_CLK_57P6M_EN_LEN     (1U)
+#define GLB_DLL_CLK_57P6M_EN_MSK     (((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS)
+#define GLB_DLL_CLK_57P6M_EN_UMSK    (~(((1U << GLB_DLL_CLK_57P6M_EN_LEN) - 1) << GLB_DLL_CLK_57P6M_EN_POS))
+#define GLB_DLL_VCTRL_SEL            GLB_DLL_VCTRL_SEL
+#define GLB_DLL_VCTRL_SEL_POS        (8U)
+#define GLB_DLL_VCTRL_SEL_LEN        (3U)
+#define GLB_DLL_VCTRL_SEL_MSK        (((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS)
+#define GLB_DLL_VCTRL_SEL_UMSK       (~(((1U << GLB_DLL_VCTRL_SEL_LEN) - 1) << GLB_DLL_VCTRL_SEL_POS))
+#define GLB_DLL_PRECHG_SEL           GLB_DLL_PRECHG_SEL
+#define GLB_DLL_PRECHG_SEL_POS       (12U)
+#define GLB_DLL_PRECHG_SEL_LEN       (1U)
+#define GLB_DLL_PRECHG_SEL_MSK       (((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS)
+#define GLB_DLL_PRECHG_SEL_UMSK      (~(((1U << GLB_DLL_PRECHG_SEL_LEN) - 1) << GLB_DLL_PRECHG_SEL_POS))
+#define GLB_DLL_PRECHG_REG           GLB_DLL_PRECHG_REG
+#define GLB_DLL_PRECHG_REG_POS       (13U)
+#define GLB_DLL_PRECHG_REG_LEN       (1U)
+#define GLB_DLL_PRECHG_REG_MSK       (((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS)
+#define GLB_DLL_PRECHG_REG_UMSK      (~(((1U << GLB_DLL_PRECHG_REG_LEN) - 1) << GLB_DLL_PRECHG_REG_POS))
+#define GLB_DLL_PRECHG_EN            GLB_DLL_PRECHG_EN
+#define GLB_DLL_PRECHG_EN_POS        (14U)
+#define GLB_DLL_PRECHG_EN_LEN        (1U)
+#define GLB_DLL_PRECHG_EN_MSK        (((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS)
+#define GLB_DLL_PRECHG_EN_UMSK       (~(((1U << GLB_DLL_PRECHG_EN_LEN) - 1) << GLB_DLL_PRECHG_EN_POS))
+#define GLB_DLL_VCTRL_FORCE_EN       GLB_DLL_VCTRL_FORCE_EN
+#define GLB_DLL_VCTRL_FORCE_EN_POS   (15U)
+#define GLB_DLL_VCTRL_FORCE_EN_LEN   (1U)
+#define GLB_DLL_VCTRL_FORCE_EN_MSK   (((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS)
+#define GLB_DLL_VCTRL_FORCE_EN_UMSK  (~(((1U << GLB_DLL_VCTRL_FORCE_EN_LEN) - 1) << GLB_DLL_VCTRL_FORCE_EN_POS))
+#define GLB_DLL_POST_DIV             GLB_DLL_POST_DIV
+#define GLB_DLL_POST_DIV_POS         (16U)
+#define GLB_DLL_POST_DIV_LEN         (4U)
+#define GLB_DLL_POST_DIV_MSK         (((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS)
+#define GLB_DLL_POST_DIV_UMSK        (~(((1U << GLB_DLL_POST_DIV_LEN) - 1) << GLB_DLL_POST_DIV_POS))
+#define GLB_DLL_DELAY_SEL            GLB_DLL_DELAY_SEL
+#define GLB_DLL_DELAY_SEL_POS        (20U)
+#define GLB_DLL_DELAY_SEL_LEN        (2U)
+#define GLB_DLL_DELAY_SEL_MSK        (((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS)
+#define GLB_DLL_DELAY_SEL_UMSK       (~(((1U << GLB_DLL_DELAY_SEL_LEN) - 1) << GLB_DLL_DELAY_SEL_POS))
+#define GLB_DLL_CP_OP_EN             GLB_DLL_CP_OP_EN
+#define GLB_DLL_CP_OP_EN_POS         (22U)
+#define GLB_DLL_CP_OP_EN_LEN         (1U)
+#define GLB_DLL_CP_OP_EN_MSK         (((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS)
+#define GLB_DLL_CP_OP_EN_UMSK        (~(((1U << GLB_DLL_CP_OP_EN_LEN) - 1) << GLB_DLL_CP_OP_EN_POS))
+#define GLB_DLL_CP_HIZ               GLB_DLL_CP_HIZ
+#define GLB_DLL_CP_HIZ_POS           (23U)
+#define GLB_DLL_CP_HIZ_LEN           (1U)
+#define GLB_DLL_CP_HIZ_MSK           (((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS)
+#define GLB_DLL_CP_HIZ_UMSK          (~(((1U << GLB_DLL_CP_HIZ_LEN) - 1) << GLB_DLL_CP_HIZ_POS))
+#define GLB_DLL_REFCLK_SEL           GLB_DLL_REFCLK_SEL
+#define GLB_DLL_REFCLK_SEL_POS       (28U)
+#define GLB_DLL_REFCLK_SEL_LEN       (1U)
+#define GLB_DLL_REFCLK_SEL_MSK       (((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS)
+#define GLB_DLL_REFCLK_SEL_UMSK      (~(((1U << GLB_DLL_REFCLK_SEL_LEN) - 1) << GLB_DLL_REFCLK_SEL_POS))
+#define GLB_DLL_RESET                GLB_DLL_RESET
+#define GLB_DLL_RESET_POS            (29U)
+#define GLB_DLL_RESET_LEN            (1U)
+#define GLB_DLL_RESET_MSK            (((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS)
+#define GLB_DLL_RESET_UMSK           (~(((1U << GLB_DLL_RESET_LEN) - 1) << GLB_DLL_RESET_POS))
+#define GLB_PU_DLL                   GLB_PU_DLL
+#define GLB_PU_DLL_POS               (30U)
+#define GLB_PU_DLL_LEN               (1U)
+#define GLB_PU_DLL_MSK               (((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS)
+#define GLB_PU_DLL_UMSK              (~(((1U << GLB_PU_DLL_LEN) - 1) << GLB_PU_DLL_POS))
+#define GLB_PPU_DLL                  GLB_PPU_DLL
+#define GLB_PPU_DLL_POS              (31U)
+#define GLB_PPU_DLL_LEN              (1U)
+#define GLB_PPU_DLL_MSK              (((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS)
+#define GLB_PPU_DLL_UMSK             (~(((1U << GLB_PPU_DLL_LEN) - 1) << GLB_PPU_DLL_POS))
+
+/* 0x224 : led_driver */
+#define GLB_LED_DRIVER_OFFSET         (0x224)
+#define GLB_LED_DIN_REG               GLB_LED_DIN_REG
+#define GLB_LED_DIN_REG_POS           (0U)
+#define GLB_LED_DIN_REG_LEN           (1U)
+#define GLB_LED_DIN_REG_MSK           (((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS)
+#define GLB_LED_DIN_REG_UMSK          (~(((1U << GLB_LED_DIN_REG_LEN) - 1) << GLB_LED_DIN_REG_POS))
+#define GLB_LED_DIN_SEL               GLB_LED_DIN_SEL
+#define GLB_LED_DIN_SEL_POS           (1U)
+#define GLB_LED_DIN_SEL_LEN           (1U)
+#define GLB_LED_DIN_SEL_MSK           (((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS)
+#define GLB_LED_DIN_SEL_UMSK          (~(((1U << GLB_LED_DIN_SEL_LEN) - 1) << GLB_LED_DIN_SEL_POS))
+#define GLB_LED_DIN_POLARITY_SEL      GLB_LED_DIN_POLARITY_SEL
+#define GLB_LED_DIN_POLARITY_SEL_POS  (2U)
+#define GLB_LED_DIN_POLARITY_SEL_LEN  (1U)
+#define GLB_LED_DIN_POLARITY_SEL_MSK  (((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS)
+#define GLB_LED_DIN_POLARITY_SEL_UMSK (~(((1U << GLB_LED_DIN_POLARITY_SEL_LEN) - 1) << GLB_LED_DIN_POLARITY_SEL_POS))
+#define GLB_LEDDRV_IBIAS              GLB_LEDDRV_IBIAS
+#define GLB_LEDDRV_IBIAS_POS          (4U)
+#define GLB_LEDDRV_IBIAS_LEN          (4U)
+#define GLB_LEDDRV_IBIAS_MSK          (((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS)
+#define GLB_LEDDRV_IBIAS_UMSK         (~(((1U << GLB_LEDDRV_IBIAS_LEN) - 1) << GLB_LEDDRV_IBIAS_POS))
+#define GLB_IR_RX_GPIO_SEL            GLB_IR_RX_GPIO_SEL
+#define GLB_IR_RX_GPIO_SEL_POS        (8U)
+#define GLB_IR_RX_GPIO_SEL_LEN        (4U)
+#define GLB_IR_RX_GPIO_SEL_MSK        (((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS)
+#define GLB_IR_RX_GPIO_SEL_UMSK       (~(((1U << GLB_IR_RX_GPIO_SEL_LEN) - 1) << GLB_IR_RX_GPIO_SEL_POS))
+#define GLB_LEDDRV_OUT_EN             GLB_LEDDRV_OUT_EN
+#define GLB_LEDDRV_OUT_EN_POS         (28U)
+#define GLB_LEDDRV_OUT_EN_LEN         (2U)
+#define GLB_LEDDRV_OUT_EN_MSK         (((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS)
+#define GLB_LEDDRV_OUT_EN_UMSK        (~(((1U << GLB_LEDDRV_OUT_EN_LEN) - 1) << GLB_LEDDRV_OUT_EN_POS))
+#define GLB_PU_LEDDRV                 GLB_PU_LEDDRV
+#define GLB_PU_LEDDRV_POS             (31U)
+#define GLB_PU_LEDDRV_LEN             (1U)
+#define GLB_PU_LEDDRV_MSK             (((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS)
+#define GLB_PU_LEDDRV_UMSK            (~(((1U << GLB_PU_LEDDRV_LEN) - 1) << GLB_PU_LEDDRV_POS))
+
+/* 0x228 : usb_xcvr */
+#define GLB_USB_XCVR_OFFSET       (0x228)
+#define GLB_USB_LDO_VFB           GLB_USB_LDO_VFB
+#define GLB_USB_LDO_VFB_POS       (0U)
+#define GLB_USB_LDO_VFB_LEN       (3U)
+#define GLB_USB_LDO_VFB_MSK       (((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS)
+#define GLB_USB_LDO_VFB_UMSK      (~(((1U << GLB_USB_LDO_VFB_LEN) - 1) << GLB_USB_LDO_VFB_POS))
+#define GLB_PU_USB_LDO            GLB_PU_USB_LDO
+#define GLB_PU_USB_LDO_POS        (3U)
+#define GLB_PU_USB_LDO_LEN        (1U)
+#define GLB_PU_USB_LDO_MSK        (((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS)
+#define GLB_PU_USB_LDO_UMSK       (~(((1U << GLB_PU_USB_LDO_LEN) - 1) << GLB_PU_USB_LDO_POS))
+#define GLB_USB_ROUT_NMOS         GLB_USB_ROUT_NMOS
+#define GLB_USB_ROUT_NMOS_POS     (4U)
+#define GLB_USB_ROUT_NMOS_LEN     (3U)
+#define GLB_USB_ROUT_NMOS_MSK     (((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS)
+#define GLB_USB_ROUT_NMOS_UMSK    (~(((1U << GLB_USB_ROUT_NMOS_LEN) - 1) << GLB_USB_ROUT_NMOS_POS))
+#define GLB_USB_ROUT_PMOS         GLB_USB_ROUT_PMOS
+#define GLB_USB_ROUT_PMOS_POS     (8U)
+#define GLB_USB_ROUT_PMOS_LEN     (3U)
+#define GLB_USB_ROUT_PMOS_MSK     (((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS)
+#define GLB_USB_ROUT_PMOS_UMSK    (~(((1U << GLB_USB_ROUT_PMOS_LEN) - 1) << GLB_USB_ROUT_PMOS_POS))
+#define GLB_USB_OEB_SEL           GLB_USB_OEB_SEL
+#define GLB_USB_OEB_SEL_POS       (12U)
+#define GLB_USB_OEB_SEL_LEN       (1U)
+#define GLB_USB_OEB_SEL_MSK       (((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS)
+#define GLB_USB_OEB_SEL_UMSK      (~(((1U << GLB_USB_OEB_SEL_LEN) - 1) << GLB_USB_OEB_SEL_POS))
+#define GLB_USB_OEB_REG           GLB_USB_OEB_REG
+#define GLB_USB_OEB_REG_POS       (13U)
+#define GLB_USB_OEB_REG_LEN       (1U)
+#define GLB_USB_OEB_REG_MSK       (((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS)
+#define GLB_USB_OEB_REG_UMSK      (~(((1U << GLB_USB_OEB_REG_LEN) - 1) << GLB_USB_OEB_REG_POS))
+#define GLB_USB_OEB               GLB_USB_OEB
+#define GLB_USB_OEB_POS           (14U)
+#define GLB_USB_OEB_LEN           (1U)
+#define GLB_USB_OEB_MSK           (((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS)
+#define GLB_USB_OEB_UMSK          (~(((1U << GLB_USB_OEB_LEN) - 1) << GLB_USB_OEB_POS))
+#define GLB_USB_DATA_CONVERT      GLB_USB_DATA_CONVERT
+#define GLB_USB_DATA_CONVERT_POS  (16U)
+#define GLB_USB_DATA_CONVERT_LEN  (1U)
+#define GLB_USB_DATA_CONVERT_MSK  (((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS)
+#define GLB_USB_DATA_CONVERT_UMSK (~(((1U << GLB_USB_DATA_CONVERT_LEN) - 1) << GLB_USB_DATA_CONVERT_POS))
+#define GLB_USB_ENUM              GLB_USB_ENUM
+#define GLB_USB_ENUM_POS          (20U)
+#define GLB_USB_ENUM_LEN          (1U)
+#define GLB_USB_ENUM_MSK          (((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS)
+#define GLB_USB_ENUM_UMSK         (~(((1U << GLB_USB_ENUM_LEN) - 1) << GLB_USB_ENUM_POS))
+#define GLB_USB_SPD               GLB_USB_SPD
+#define GLB_USB_SPD_POS           (21U)
+#define GLB_USB_SPD_LEN           (1U)
+#define GLB_USB_SPD_MSK           (((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS)
+#define GLB_USB_SPD_UMSK          (~(((1U << GLB_USB_SPD_LEN) - 1) << GLB_USB_SPD_POS))
+#define GLB_USB_SUS               GLB_USB_SUS
+#define GLB_USB_SUS_POS           (22U)
+#define GLB_USB_SUS_LEN           (1U)
+#define GLB_USB_SUS_MSK           (((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS)
+#define GLB_USB_SUS_UMSK          (~(((1U << GLB_USB_SUS_LEN) - 1) << GLB_USB_SUS_POS))
+#define GLB_PU_USB                GLB_PU_USB
+#define GLB_PU_USB_POS            (23U)
+#define GLB_PU_USB_LEN            (1U)
+#define GLB_PU_USB_MSK            (((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS)
+#define GLB_PU_USB_UMSK           (~(((1U << GLB_PU_USB_LEN) - 1) << GLB_PU_USB_POS))
+#define GLB_USB_BD                GLB_USB_BD
+#define GLB_USB_BD_POS            (24U)
+#define GLB_USB_BD_LEN            (1U)
+#define GLB_USB_BD_MSK            (((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS)
+#define GLB_USB_BD_UMSK           (~(((1U << GLB_USB_BD_LEN) - 1) << GLB_USB_BD_POS))
+#define GLB_USB_VIM               GLB_USB_VIM
+#define GLB_USB_VIM_POS           (25U)
+#define GLB_USB_VIM_LEN           (1U)
+#define GLB_USB_VIM_MSK           (((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS)
+#define GLB_USB_VIM_UMSK          (~(((1U << GLB_USB_VIM_LEN) - 1) << GLB_USB_VIM_POS))
+#define GLB_USB_VIP               GLB_USB_VIP
+#define GLB_USB_VIP_POS           (26U)
+#define GLB_USB_VIP_LEN           (1U)
+#define GLB_USB_VIP_MSK           (((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS)
+#define GLB_USB_VIP_UMSK          (~(((1U << GLB_USB_VIP_LEN) - 1) << GLB_USB_VIP_POS))
+#define GLB_USB_RCV               GLB_USB_RCV
+#define GLB_USB_RCV_POS           (27U)
+#define GLB_USB_RCV_LEN           (1U)
+#define GLB_USB_RCV_MSK           (((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS)
+#define GLB_USB_RCV_UMSK          (~(((1U << GLB_USB_RCV_LEN) - 1) << GLB_USB_RCV_POS))
+
+/* 0x22C : usb_xcvr_config */
+#define GLB_USB_XCVR_CONFIG_OFFSET   (0x22C)
+#define GLB_USB_V_HYS_M              GLB_USB_V_HYS_M
+#define GLB_USB_V_HYS_M_POS          (0U)
+#define GLB_USB_V_HYS_M_LEN          (2U)
+#define GLB_USB_V_HYS_M_MSK          (((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS)
+#define GLB_USB_V_HYS_M_UMSK         (~(((1U << GLB_USB_V_HYS_M_LEN) - 1) << GLB_USB_V_HYS_M_POS))
+#define GLB_USB_V_HYS_P              GLB_USB_V_HYS_P
+#define GLB_USB_V_HYS_P_POS          (2U)
+#define GLB_USB_V_HYS_P_LEN          (2U)
+#define GLB_USB_V_HYS_P_MSK          (((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS)
+#define GLB_USB_V_HYS_P_UMSK         (~(((1U << GLB_USB_V_HYS_P_LEN) - 1) << GLB_USB_V_HYS_P_POS))
+#define GLB_USB_BD_VTH               GLB_USB_BD_VTH
+#define GLB_USB_BD_VTH_POS           (4U)
+#define GLB_USB_BD_VTH_LEN           (3U)
+#define GLB_USB_BD_VTH_MSK           (((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS)
+#define GLB_USB_BD_VTH_UMSK          (~(((1U << GLB_USB_BD_VTH_LEN) - 1) << GLB_USB_BD_VTH_POS))
+#define GLB_REG_USB_USE_XCVR         GLB_REG_USB_USE_XCVR
+#define GLB_REG_USB_USE_XCVR_POS     (7U)
+#define GLB_REG_USB_USE_XCVR_LEN     (1U)
+#define GLB_REG_USB_USE_XCVR_MSK     (((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS)
+#define GLB_REG_USB_USE_XCVR_UMSK    (~(((1U << GLB_REG_USB_USE_XCVR_LEN) - 1) << GLB_REG_USB_USE_XCVR_POS))
+#define GLB_USB_STR_DRV              GLB_USB_STR_DRV
+#define GLB_USB_STR_DRV_POS          (8U)
+#define GLB_USB_STR_DRV_LEN          (3U)
+#define GLB_USB_STR_DRV_MSK          (((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS)
+#define GLB_USB_STR_DRV_UMSK         (~(((1U << GLB_USB_STR_DRV_LEN) - 1) << GLB_USB_STR_DRV_POS))
+#define GLB_REG_USB_USE_CTRL         GLB_REG_USB_USE_CTRL
+#define GLB_REG_USB_USE_CTRL_POS     (11U)
+#define GLB_REG_USB_USE_CTRL_LEN     (1U)
+#define GLB_REG_USB_USE_CTRL_MSK     (((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS)
+#define GLB_REG_USB_USE_CTRL_UMSK    (~(((1U << GLB_REG_USB_USE_CTRL_LEN) - 1) << GLB_REG_USB_USE_CTRL_POS))
+#define GLB_USB_RES_PULLUP_TUNE      GLB_USB_RES_PULLUP_TUNE
+#define GLB_USB_RES_PULLUP_TUNE_POS  (12U)
+#define GLB_USB_RES_PULLUP_TUNE_LEN  (3U)
+#define GLB_USB_RES_PULLUP_TUNE_MSK  (((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS)
+#define GLB_USB_RES_PULLUP_TUNE_UMSK (~(((1U << GLB_USB_RES_PULLUP_TUNE_LEN) - 1) << GLB_USB_RES_PULLUP_TUNE_POS))
+#define GLB_USB_SLEWRATE_M_FALL      GLB_USB_SLEWRATE_M_FALL
+#define GLB_USB_SLEWRATE_M_FALL_POS  (16U)
+#define GLB_USB_SLEWRATE_M_FALL_LEN  (3U)
+#define GLB_USB_SLEWRATE_M_FALL_MSK  (((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS)
+#define GLB_USB_SLEWRATE_M_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_M_FALL_LEN) - 1) << GLB_USB_SLEWRATE_M_FALL_POS))
+#define GLB_USB_SLEWRATE_M_RISE      GLB_USB_SLEWRATE_M_RISE
+#define GLB_USB_SLEWRATE_M_RISE_POS  (20U)
+#define GLB_USB_SLEWRATE_M_RISE_LEN  (3U)
+#define GLB_USB_SLEWRATE_M_RISE_MSK  (((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS)
+#define GLB_USB_SLEWRATE_M_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_M_RISE_LEN) - 1) << GLB_USB_SLEWRATE_M_RISE_POS))
+#define GLB_USB_SLEWRATE_P_FALL      GLB_USB_SLEWRATE_P_FALL
+#define GLB_USB_SLEWRATE_P_FALL_POS  (24U)
+#define GLB_USB_SLEWRATE_P_FALL_LEN  (3U)
+#define GLB_USB_SLEWRATE_P_FALL_MSK  (((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS)
+#define GLB_USB_SLEWRATE_P_FALL_UMSK (~(((1U << GLB_USB_SLEWRATE_P_FALL_LEN) - 1) << GLB_USB_SLEWRATE_P_FALL_POS))
+#define GLB_USB_SLEWRATE_P_RISE      GLB_USB_SLEWRATE_P_RISE
+#define GLB_USB_SLEWRATE_P_RISE_POS  (28U)
+#define GLB_USB_SLEWRATE_P_RISE_LEN  (3U)
+#define GLB_USB_SLEWRATE_P_RISE_MSK  (((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS)
+#define GLB_USB_SLEWRATE_P_RISE_UMSK (~(((1U << GLB_USB_SLEWRATE_P_RISE_LEN) - 1) << GLB_USB_SLEWRATE_P_RISE_POS))
+
+/* 0x308 : gpdac_ctrl */
+#define GLB_GPDAC_CTRL_OFFSET    (0x308)
+#define GLB_GPDACA_RSTN_ANA      GLB_GPDACA_RSTN_ANA
+#define GLB_GPDACA_RSTN_ANA_POS  (0U)
+#define GLB_GPDACA_RSTN_ANA_LEN  (1U)
+#define GLB_GPDACA_RSTN_ANA_MSK  (((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS)
+#define GLB_GPDACA_RSTN_ANA_UMSK (~(((1U << GLB_GPDACA_RSTN_ANA_LEN) - 1) << GLB_GPDACA_RSTN_ANA_POS))
+#define GLB_GPDACB_RSTN_ANA      GLB_GPDACB_RSTN_ANA
+#define GLB_GPDACB_RSTN_ANA_POS  (1U)
+#define GLB_GPDACB_RSTN_ANA_LEN  (1U)
+#define GLB_GPDACB_RSTN_ANA_MSK  (((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS)
+#define GLB_GPDACB_RSTN_ANA_UMSK (~(((1U << GLB_GPDACB_RSTN_ANA_LEN) - 1) << GLB_GPDACB_RSTN_ANA_POS))
+#define GLB_GPDAC_TEST_EN        GLB_GPDAC_TEST_EN
+#define GLB_GPDAC_TEST_EN_POS    (7U)
+#define GLB_GPDAC_TEST_EN_LEN    (1U)
+#define GLB_GPDAC_TEST_EN_MSK    (((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS)
+#define GLB_GPDAC_TEST_EN_UMSK   (~(((1U << GLB_GPDAC_TEST_EN_LEN) - 1) << GLB_GPDAC_TEST_EN_POS))
+#define GLB_GPDAC_REF_SEL        GLB_GPDAC_REF_SEL
+#define GLB_GPDAC_REF_SEL_POS    (8U)
+#define GLB_GPDAC_REF_SEL_LEN    (1U)
+#define GLB_GPDAC_REF_SEL_MSK    (((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS)
+#define GLB_GPDAC_REF_SEL_UMSK   (~(((1U << GLB_GPDAC_REF_SEL_LEN) - 1) << GLB_GPDAC_REF_SEL_POS))
+#define GLB_GPDAC_TEST_SEL       GLB_GPDAC_TEST_SEL
+#define GLB_GPDAC_TEST_SEL_POS   (9U)
+#define GLB_GPDAC_TEST_SEL_LEN   (3U)
+#define GLB_GPDAC_TEST_SEL_MSK   (((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS)
+#define GLB_GPDAC_TEST_SEL_UMSK  (~(((1U << GLB_GPDAC_TEST_SEL_LEN) - 1) << GLB_GPDAC_TEST_SEL_POS))
+#define GLB_GPDAC_RESERVED       GLB_GPDAC_RESERVED
+#define GLB_GPDAC_RESERVED_POS   (24U)
+#define GLB_GPDAC_RESERVED_LEN   (8U)
+#define GLB_GPDAC_RESERVED_MSK   (((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS)
+#define GLB_GPDAC_RESERVED_UMSK  (~(((1U << GLB_GPDAC_RESERVED_LEN) - 1) << GLB_GPDAC_RESERVED_POS))
+
+/* 0x30C : gpdac_actrl */
+#define GLB_GPDAC_ACTRL_OFFSET  (0x30C)
+#define GLB_GPDAC_A_EN          GLB_GPDAC_A_EN
+#define GLB_GPDAC_A_EN_POS      (0U)
+#define GLB_GPDAC_A_EN_LEN      (1U)
+#define GLB_GPDAC_A_EN_MSK      (((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS)
+#define GLB_GPDAC_A_EN_UMSK     (~(((1U << GLB_GPDAC_A_EN_LEN) - 1) << GLB_GPDAC_A_EN_POS))
+#define GLB_GPDAC_IOA_EN        GLB_GPDAC_IOA_EN
+#define GLB_GPDAC_IOA_EN_POS    (1U)
+#define GLB_GPDAC_IOA_EN_LEN    (1U)
+#define GLB_GPDAC_IOA_EN_MSK    (((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS)
+#define GLB_GPDAC_IOA_EN_UMSK   (~(((1U << GLB_GPDAC_IOA_EN_LEN) - 1) << GLB_GPDAC_IOA_EN_POS))
+#define GLB_GPDAC_A_RNG         GLB_GPDAC_A_RNG
+#define GLB_GPDAC_A_RNG_POS     (18U)
+#define GLB_GPDAC_A_RNG_LEN     (2U)
+#define GLB_GPDAC_A_RNG_MSK     (((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS)
+#define GLB_GPDAC_A_RNG_UMSK    (~(((1U << GLB_GPDAC_A_RNG_LEN) - 1) << GLB_GPDAC_A_RNG_POS))
+#define GLB_GPDAC_A_OUTMUX      GLB_GPDAC_A_OUTMUX
+#define GLB_GPDAC_A_OUTMUX_POS  (20U)
+#define GLB_GPDAC_A_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_A_OUTMUX_MSK  (((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS)
+#define GLB_GPDAC_A_OUTMUX_UMSK (~(((1U << GLB_GPDAC_A_OUTMUX_LEN) - 1) << GLB_GPDAC_A_OUTMUX_POS))
+
+/* 0x310 : gpdac_bctrl */
+#define GLB_GPDAC_BCTRL_OFFSET  (0x310)
+#define GLB_GPDAC_B_EN          GLB_GPDAC_B_EN
+#define GLB_GPDAC_B_EN_POS      (0U)
+#define GLB_GPDAC_B_EN_LEN      (1U)
+#define GLB_GPDAC_B_EN_MSK      (((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS)
+#define GLB_GPDAC_B_EN_UMSK     (~(((1U << GLB_GPDAC_B_EN_LEN) - 1) << GLB_GPDAC_B_EN_POS))
+#define GLB_GPDAC_IOB_EN        GLB_GPDAC_IOB_EN
+#define GLB_GPDAC_IOB_EN_POS    (1U)
+#define GLB_GPDAC_IOB_EN_LEN    (1U)
+#define GLB_GPDAC_IOB_EN_MSK    (((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS)
+#define GLB_GPDAC_IOB_EN_UMSK   (~(((1U << GLB_GPDAC_IOB_EN_LEN) - 1) << GLB_GPDAC_IOB_EN_POS))
+#define GLB_GPDAC_B_RNG         GLB_GPDAC_B_RNG
+#define GLB_GPDAC_B_RNG_POS     (18U)
+#define GLB_GPDAC_B_RNG_LEN     (2U)
+#define GLB_GPDAC_B_RNG_MSK     (((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS)
+#define GLB_GPDAC_B_RNG_UMSK    (~(((1U << GLB_GPDAC_B_RNG_LEN) - 1) << GLB_GPDAC_B_RNG_POS))
+#define GLB_GPDAC_B_OUTMUX      GLB_GPDAC_B_OUTMUX
+#define GLB_GPDAC_B_OUTMUX_POS  (20U)
+#define GLB_GPDAC_B_OUTMUX_LEN  (3U)
+#define GLB_GPDAC_B_OUTMUX_MSK  (((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS)
+#define GLB_GPDAC_B_OUTMUX_UMSK (~(((1U << GLB_GPDAC_B_OUTMUX_LEN) - 1) << GLB_GPDAC_B_OUTMUX_POS))
+
+/* 0x314 : gpdac_data */
+#define GLB_GPDAC_DATA_OFFSET (0x314)
+#define GLB_GPDAC_B_DATA      GLB_GPDAC_B_DATA
+#define GLB_GPDAC_B_DATA_POS  (0U)
+#define GLB_GPDAC_B_DATA_LEN  (10U)
+#define GLB_GPDAC_B_DATA_MSK  (((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS)
+#define GLB_GPDAC_B_DATA_UMSK (~(((1U << GLB_GPDAC_B_DATA_LEN) - 1) << GLB_GPDAC_B_DATA_POS))
+#define GLB_GPDAC_A_DATA      GLB_GPDAC_A_DATA
+#define GLB_GPDAC_A_DATA_POS  (16U)
+#define GLB_GPDAC_A_DATA_LEN  (10U)
+#define GLB_GPDAC_A_DATA_MSK  (((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS)
+#define GLB_GPDAC_A_DATA_UMSK (~(((1U << GLB_GPDAC_A_DATA_LEN) - 1) << GLB_GPDAC_A_DATA_POS))
+
+/* 0xE00 : chip_revision */
+#define GLB_CHIP_REVISION_OFFSET (0xE00)
+#define GLB_CHIP_REV             GLB_CHIP_REV
+#define GLB_CHIP_REV_POS         (0U)
+#define GLB_CHIP_REV_LEN         (4U)
+#define GLB_CHIP_REV_MSK         (((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS)
+#define GLB_CHIP_REV_UMSK        (~(((1U << GLB_CHIP_REV_LEN) - 1) << GLB_CHIP_REV_POS))
+
+/* 0xF00 : tzc_glb_ctrl_0 */
+#define GLB_TZC_GLB_CTRL_0_OFFSET             (0xF00)
+#define GLB_TZC_GLB_SWRST_S00_LOCK            GLB_TZC_GLB_SWRST_S00_LOCK
+#define GLB_TZC_GLB_SWRST_S00_LOCK_POS        (0U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S00_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S00_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S00_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S01_LOCK            GLB_TZC_GLB_SWRST_S01_LOCK
+#define GLB_TZC_GLB_SWRST_S01_LOCK_POS        (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S01_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S01_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S01_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S30_LOCK            GLB_TZC_GLB_SWRST_S30_LOCK
+#define GLB_TZC_GLB_SWRST_S30_LOCK_POS        (8U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_LEN        (1U)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_MSK        (((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S30_LOCK_UMSK       (~(((1U << GLB_TZC_GLB_SWRST_S30_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S30_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK       GLB_TZC_GLB_CTRL_PWRON_RST_LOCK
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS   (12U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_PWRON_RST_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK       GLB_TZC_GLB_CTRL_CPU_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS   (13U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_CPU_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK       GLB_TZC_GLB_CTRL_SYS_RESET_LOCK
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS   (14U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_MSK   (((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_SYS_RESET_LOCK_POS))
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK      GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS  (15U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_MSK  (((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS)
+#define GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_UMSK (~(((1U << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_LEN) - 1) << GLB_TZC_GLB_CTRL_UNGATED_AP_LOCK_POS))
+#define GLB_TZC_GLB_MISC_LOCK                 GLB_TZC_GLB_MISC_LOCK
+#define GLB_TZC_GLB_MISC_LOCK_POS             (25U)
+#define GLB_TZC_GLB_MISC_LOCK_LEN             (1U)
+#define GLB_TZC_GLB_MISC_LOCK_MSK             (((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS)
+#define GLB_TZC_GLB_MISC_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_MISC_LOCK_LEN) - 1) << GLB_TZC_GLB_MISC_LOCK_POS))
+#define GLB_TZC_GLB_SRAM_LOCK                 GLB_TZC_GLB_SRAM_LOCK
+#define GLB_TZC_GLB_SRAM_LOCK_POS             (26U)
+#define GLB_TZC_GLB_SRAM_LOCK_LEN             (1U)
+#define GLB_TZC_GLB_SRAM_LOCK_MSK             (((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS)
+#define GLB_TZC_GLB_SRAM_LOCK_UMSK            (~(((1U << GLB_TZC_GLB_SRAM_LOCK_LEN) - 1) << GLB_TZC_GLB_SRAM_LOCK_POS))
+#define GLB_TZC_GLB_L2C_LOCK                  GLB_TZC_GLB_L2C_LOCK
+#define GLB_TZC_GLB_L2C_LOCK_POS              (27U)
+#define GLB_TZC_GLB_L2C_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_L2C_LOCK_MSK              (((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS)
+#define GLB_TZC_GLB_L2C_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_L2C_LOCK_LEN) - 1) << GLB_TZC_GLB_L2C_LOCK_POS))
+#define GLB_TZC_GLB_BMX_LOCK                  GLB_TZC_GLB_BMX_LOCK
+#define GLB_TZC_GLB_BMX_LOCK_POS              (28U)
+#define GLB_TZC_GLB_BMX_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_BMX_LOCK_MSK              (((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS)
+#define GLB_TZC_GLB_BMX_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_BMX_LOCK_LEN) - 1) << GLB_TZC_GLB_BMX_LOCK_POS))
+#define GLB_TZC_GLB_DBG_LOCK                  GLB_TZC_GLB_DBG_LOCK
+#define GLB_TZC_GLB_DBG_LOCK_POS              (29U)
+#define GLB_TZC_GLB_DBG_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_DBG_LOCK_MSK              (((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS)
+#define GLB_TZC_GLB_DBG_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_DBG_LOCK_LEN) - 1) << GLB_TZC_GLB_DBG_LOCK_POS))
+#define GLB_TZC_GLB_MBIST_LOCK                GLB_TZC_GLB_MBIST_LOCK
+#define GLB_TZC_GLB_MBIST_LOCK_POS            (30U)
+#define GLB_TZC_GLB_MBIST_LOCK_LEN            (1U)
+#define GLB_TZC_GLB_MBIST_LOCK_MSK            (((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS)
+#define GLB_TZC_GLB_MBIST_LOCK_UMSK           (~(((1U << GLB_TZC_GLB_MBIST_LOCK_LEN) - 1) << GLB_TZC_GLB_MBIST_LOCK_POS))
+#define GLB_TZC_GLB_CLK_LOCK                  GLB_TZC_GLB_CLK_LOCK
+#define GLB_TZC_GLB_CLK_LOCK_POS              (31U)
+#define GLB_TZC_GLB_CLK_LOCK_LEN              (1U)
+#define GLB_TZC_GLB_CLK_LOCK_MSK              (((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS)
+#define GLB_TZC_GLB_CLK_LOCK_UMSK             (~(((1U << GLB_TZC_GLB_CLK_LOCK_LEN) - 1) << GLB_TZC_GLB_CLK_LOCK_POS))
+
+/* 0xF04 : tzc_glb_ctrl_1 */
+#define GLB_TZC_GLB_CTRL_1_OFFSET       (0xF04)
+#define GLB_TZC_GLB_SWRST_S20_LOCK      GLB_TZC_GLB_SWRST_S20_LOCK
+#define GLB_TZC_GLB_SWRST_S20_LOCK_POS  (0U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S20_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S20_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S21_LOCK      GLB_TZC_GLB_SWRST_S21_LOCK
+#define GLB_TZC_GLB_SWRST_S21_LOCK_POS  (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S21_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S21_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S22_LOCK      GLB_TZC_GLB_SWRST_S22_LOCK
+#define GLB_TZC_GLB_SWRST_S22_LOCK_POS  (2U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S22_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S22_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S23_LOCK      GLB_TZC_GLB_SWRST_S23_LOCK
+#define GLB_TZC_GLB_SWRST_S23_LOCK_POS  (3U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S23_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S23_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S24_LOCK      GLB_TZC_GLB_SWRST_S24_LOCK
+#define GLB_TZC_GLB_SWRST_S24_LOCK_POS  (4U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S24_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S24_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S25_LOCK      GLB_TZC_GLB_SWRST_S25_LOCK
+#define GLB_TZC_GLB_SWRST_S25_LOCK_POS  (5U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S25_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S25_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S26_LOCK      GLB_TZC_GLB_SWRST_S26_LOCK
+#define GLB_TZC_GLB_SWRST_S26_LOCK_POS  (6U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S26_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S26_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S27_LOCK      GLB_TZC_GLB_SWRST_S27_LOCK
+#define GLB_TZC_GLB_SWRST_S27_LOCK_POS  (7U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S27_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S27_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S28_LOCK      GLB_TZC_GLB_SWRST_S28_LOCK
+#define GLB_TZC_GLB_SWRST_S28_LOCK_POS  (8U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S28_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S28_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S29_LOCK      GLB_TZC_GLB_SWRST_S29_LOCK
+#define GLB_TZC_GLB_SWRST_S29_LOCK_POS  (9U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S29_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S29_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2A_LOCK      GLB_TZC_GLB_SWRST_S2A_LOCK
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_POS  (10U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2B_LOCK      GLB_TZC_GLB_SWRST_S2B_LOCK
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_POS  (11U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2C_LOCK      GLB_TZC_GLB_SWRST_S2C_LOCK
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_POS  (12U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2D_LOCK      GLB_TZC_GLB_SWRST_S2D_LOCK
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_POS  (13U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2E_LOCK      GLB_TZC_GLB_SWRST_S2E_LOCK
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_POS  (14U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S2F_LOCK      GLB_TZC_GLB_SWRST_S2F_LOCK
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_POS  (15U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S2F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S2F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S2F_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S10_LOCK      GLB_TZC_GLB_SWRST_S10_LOCK
+#define GLB_TZC_GLB_SWRST_S10_LOCK_POS  (16U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S10_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S10_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S11_LOCK      GLB_TZC_GLB_SWRST_S11_LOCK
+#define GLB_TZC_GLB_SWRST_S11_LOCK_POS  (17U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S11_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S11_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S12_LOCK      GLB_TZC_GLB_SWRST_S12_LOCK
+#define GLB_TZC_GLB_SWRST_S12_LOCK_POS  (18U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S12_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S12_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S13_LOCK      GLB_TZC_GLB_SWRST_S13_LOCK
+#define GLB_TZC_GLB_SWRST_S13_LOCK_POS  (19U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S13_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S13_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S14_LOCK      GLB_TZC_GLB_SWRST_S14_LOCK
+#define GLB_TZC_GLB_SWRST_S14_LOCK_POS  (20U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S14_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S14_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S15_LOCK      GLB_TZC_GLB_SWRST_S15_LOCK
+#define GLB_TZC_GLB_SWRST_S15_LOCK_POS  (21U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S15_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S15_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S16_LOCK      GLB_TZC_GLB_SWRST_S16_LOCK
+#define GLB_TZC_GLB_SWRST_S16_LOCK_POS  (22U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S16_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S16_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S17_LOCK      GLB_TZC_GLB_SWRST_S17_LOCK
+#define GLB_TZC_GLB_SWRST_S17_LOCK_POS  (23U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S17_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S17_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S18_LOCK      GLB_TZC_GLB_SWRST_S18_LOCK
+#define GLB_TZC_GLB_SWRST_S18_LOCK_POS  (24U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S18_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S18_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S19_LOCK      GLB_TZC_GLB_SWRST_S19_LOCK
+#define GLB_TZC_GLB_SWRST_S19_LOCK_POS  (25U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S19_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S19_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1A_LOCK      GLB_TZC_GLB_SWRST_S1A_LOCK
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_POS  (26U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1A_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1A_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1A_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1B_LOCK      GLB_TZC_GLB_SWRST_S1B_LOCK
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_POS  (27U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1B_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1B_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1B_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1C_LOCK      GLB_TZC_GLB_SWRST_S1C_LOCK
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_POS  (28U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1C_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1C_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1C_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1D_LOCK      GLB_TZC_GLB_SWRST_S1D_LOCK
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_POS  (29U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1D_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1D_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1D_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1E_LOCK      GLB_TZC_GLB_SWRST_S1E_LOCK
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_POS  (30U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1E_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1E_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1E_LOCK_POS))
+#define GLB_TZC_GLB_SWRST_S1F_LOCK      GLB_TZC_GLB_SWRST_S1F_LOCK
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_POS  (31U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_MSK  (((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS)
+#define GLB_TZC_GLB_SWRST_S1F_LOCK_UMSK (~(((1U << GLB_TZC_GLB_SWRST_S1F_LOCK_LEN) - 1) << GLB_TZC_GLB_SWRST_S1F_LOCK_POS))
+
+/* 0xF08 : tzc_glb_ctrl_2 */
+#define GLB_TZC_GLB_CTRL_2_OFFSET     (0xF08)
+#define GLB_TZC_GLB_GPIO_0_LOCK       GLB_TZC_GLB_GPIO_0_LOCK
+#define GLB_TZC_GLB_GPIO_0_LOCK_POS   (0U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_0_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_0_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_0_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_0_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_1_LOCK       GLB_TZC_GLB_GPIO_1_LOCK
+#define GLB_TZC_GLB_GPIO_1_LOCK_POS   (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_1_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_1_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_1_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_1_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_2_LOCK       GLB_TZC_GLB_GPIO_2_LOCK
+#define GLB_TZC_GLB_GPIO_2_LOCK_POS   (2U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_2_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_2_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_2_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_2_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_3_LOCK       GLB_TZC_GLB_GPIO_3_LOCK
+#define GLB_TZC_GLB_GPIO_3_LOCK_POS   (3U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_3_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_3_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_3_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_3_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_4_LOCK       GLB_TZC_GLB_GPIO_4_LOCK
+#define GLB_TZC_GLB_GPIO_4_LOCK_POS   (4U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_4_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_4_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_4_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_4_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_5_LOCK       GLB_TZC_GLB_GPIO_5_LOCK
+#define GLB_TZC_GLB_GPIO_5_LOCK_POS   (5U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_5_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_5_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_5_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_5_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_6_LOCK       GLB_TZC_GLB_GPIO_6_LOCK
+#define GLB_TZC_GLB_GPIO_6_LOCK_POS   (6U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_6_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_6_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_6_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_6_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_7_LOCK       GLB_TZC_GLB_GPIO_7_LOCK
+#define GLB_TZC_GLB_GPIO_7_LOCK_POS   (7U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_7_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_7_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_7_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_7_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_8_LOCK       GLB_TZC_GLB_GPIO_8_LOCK
+#define GLB_TZC_GLB_GPIO_8_LOCK_POS   (8U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_8_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_8_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_8_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_8_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_9_LOCK       GLB_TZC_GLB_GPIO_9_LOCK
+#define GLB_TZC_GLB_GPIO_9_LOCK_POS   (9U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_LEN   (1U)
+#define GLB_TZC_GLB_GPIO_9_LOCK_MSK   (((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_9_LOCK_UMSK  (~(((1U << GLB_TZC_GLB_GPIO_9_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_9_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_10_LOCK      GLB_TZC_GLB_GPIO_10_LOCK
+#define GLB_TZC_GLB_GPIO_10_LOCK_POS  (10U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_10_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_10_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_10_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_10_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_11_LOCK      GLB_TZC_GLB_GPIO_11_LOCK
+#define GLB_TZC_GLB_GPIO_11_LOCK_POS  (11U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_11_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_11_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_11_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_11_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_12_LOCK      GLB_TZC_GLB_GPIO_12_LOCK
+#define GLB_TZC_GLB_GPIO_12_LOCK_POS  (12U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_12_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_12_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_12_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_12_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_13_LOCK      GLB_TZC_GLB_GPIO_13_LOCK
+#define GLB_TZC_GLB_GPIO_13_LOCK_POS  (13U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_13_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_13_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_13_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_13_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_14_LOCK      GLB_TZC_GLB_GPIO_14_LOCK
+#define GLB_TZC_GLB_GPIO_14_LOCK_POS  (14U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_14_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_14_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_14_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_14_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_15_LOCK      GLB_TZC_GLB_GPIO_15_LOCK
+#define GLB_TZC_GLB_GPIO_15_LOCK_POS  (15U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_15_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_15_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_15_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_15_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_16_LOCK      GLB_TZC_GLB_GPIO_16_LOCK
+#define GLB_TZC_GLB_GPIO_16_LOCK_POS  (16U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_16_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_16_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_16_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_16_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_17_LOCK      GLB_TZC_GLB_GPIO_17_LOCK
+#define GLB_TZC_GLB_GPIO_17_LOCK_POS  (17U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_17_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_17_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_17_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_17_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_18_LOCK      GLB_TZC_GLB_GPIO_18_LOCK
+#define GLB_TZC_GLB_GPIO_18_LOCK_POS  (18U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_18_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_18_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_18_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_18_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_19_LOCK      GLB_TZC_GLB_GPIO_19_LOCK
+#define GLB_TZC_GLB_GPIO_19_LOCK_POS  (19U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_19_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_19_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_19_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_19_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_20_LOCK      GLB_TZC_GLB_GPIO_20_LOCK
+#define GLB_TZC_GLB_GPIO_20_LOCK_POS  (20U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_20_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_20_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_20_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_20_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_21_LOCK      GLB_TZC_GLB_GPIO_21_LOCK
+#define GLB_TZC_GLB_GPIO_21_LOCK_POS  (21U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_21_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_21_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_21_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_21_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_22_LOCK      GLB_TZC_GLB_GPIO_22_LOCK
+#define GLB_TZC_GLB_GPIO_22_LOCK_POS  (22U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_22_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_22_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_22_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_22_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_23_LOCK      GLB_TZC_GLB_GPIO_23_LOCK
+#define GLB_TZC_GLB_GPIO_23_LOCK_POS  (23U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_23_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_23_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_23_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_23_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_24_LOCK      GLB_TZC_GLB_GPIO_24_LOCK
+#define GLB_TZC_GLB_GPIO_24_LOCK_POS  (24U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_24_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_24_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_24_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_24_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_25_LOCK      GLB_TZC_GLB_GPIO_25_LOCK
+#define GLB_TZC_GLB_GPIO_25_LOCK_POS  (25U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_25_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_25_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_25_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_25_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_26_LOCK      GLB_TZC_GLB_GPIO_26_LOCK
+#define GLB_TZC_GLB_GPIO_26_LOCK_POS  (26U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_26_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_26_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_26_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_26_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_27_LOCK      GLB_TZC_GLB_GPIO_27_LOCK
+#define GLB_TZC_GLB_GPIO_27_LOCK_POS  (27U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_27_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_27_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_27_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_27_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_28_LOCK      GLB_TZC_GLB_GPIO_28_LOCK
+#define GLB_TZC_GLB_GPIO_28_LOCK_POS  (28U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_28_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_28_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_28_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_28_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_29_LOCK      GLB_TZC_GLB_GPIO_29_LOCK
+#define GLB_TZC_GLB_GPIO_29_LOCK_POS  (29U)
+#define GLB_TZC_GLB_GPIO_29_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_29_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_29_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_29_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_29_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_30_LOCK      GLB_TZC_GLB_GPIO_30_LOCK
+#define GLB_TZC_GLB_GPIO_30_LOCK_POS  (30U)
+#define GLB_TZC_GLB_GPIO_30_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_30_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_30_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_30_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_30_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_31_LOCK      GLB_TZC_GLB_GPIO_31_LOCK
+#define GLB_TZC_GLB_GPIO_31_LOCK_POS  (31U)
+#define GLB_TZC_GLB_GPIO_31_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_31_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_31_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_31_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_31_LOCK_POS))
+
+/* 0xF0C : tzc_glb_ctrl_3 */
+#define GLB_TZC_GLB_CTRL_3_OFFSET     (0xF0C)
+#define GLB_TZC_GLB_GPIO_32_LOCK      GLB_TZC_GLB_GPIO_32_LOCK
+#define GLB_TZC_GLB_GPIO_32_LOCK_POS  (0U)
+#define GLB_TZC_GLB_GPIO_32_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_32_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_32_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_32_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_32_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_33_LOCK      GLB_TZC_GLB_GPIO_33_LOCK
+#define GLB_TZC_GLB_GPIO_33_LOCK_POS  (1U)
+#define GLB_TZC_GLB_GPIO_33_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_33_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_33_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_33_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_33_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_34_LOCK      GLB_TZC_GLB_GPIO_34_LOCK
+#define GLB_TZC_GLB_GPIO_34_LOCK_POS  (2U)
+#define GLB_TZC_GLB_GPIO_34_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_34_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_34_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_34_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_34_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_35_LOCK      GLB_TZC_GLB_GPIO_35_LOCK
+#define GLB_TZC_GLB_GPIO_35_LOCK_POS  (3U)
+#define GLB_TZC_GLB_GPIO_35_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_35_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_35_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_35_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_35_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_36_LOCK      GLB_TZC_GLB_GPIO_36_LOCK
+#define GLB_TZC_GLB_GPIO_36_LOCK_POS  (4U)
+#define GLB_TZC_GLB_GPIO_36_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_36_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_36_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_36_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_36_LOCK_POS))
+#define GLB_TZC_GLB_GPIO_37_LOCK      GLB_TZC_GLB_GPIO_37_LOCK
+#define GLB_TZC_GLB_GPIO_37_LOCK_POS  (5U)
+#define GLB_TZC_GLB_GPIO_37_LOCK_LEN  (1U)
+#define GLB_TZC_GLB_GPIO_37_LOCK_MSK  (((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS)
+#define GLB_TZC_GLB_GPIO_37_LOCK_UMSK (~(((1U << GLB_TZC_GLB_GPIO_37_LOCK_LEN) - 1) << GLB_TZC_GLB_GPIO_37_LOCK_POS))
+
+struct glb_reg {
+    /* 0x0 : clk_cfg0 */
+    union {
+        struct
+        {
+            uint32_t reg_pll_en       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_fclk_en      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_hclk_en      : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reg_bclk_en      : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reg_pll_sel      : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t hbn_root_clk_sel : 2; /* [ 7: 6],          r,        0x0 */
+            uint32_t reg_hclk_div     : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t reg_bclk_div     : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t fclk_sw_state    : 3; /* [26:24],          r,        0x0 */
+            uint32_t chip_rdy         : 1; /* [   27],          r,        0x0 */
+            uint32_t glb_id           : 4; /* [31:28],          r,        0x7 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg0;
+
+    /* 0x4 : clk_cfg1 */
+    union {
+        struct
+        {
+            uint32_t qdec_clk_div            : 5; /* [ 4: 0],        r/w,       0x1f */
+            uint32_t reserved_5_6            : 2; /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t qdec_clk_sel            : 1; /* [    7],        r/w,        0x0 */
+            uint32_t usb_clk_en              : 1; /* [    8],        r/w,        0x1 */
+            uint32_t dll_48m_div_en          : 1; /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10_11          : 2; /* [11:10],       rsvd,        0x0 */
+            uint32_t reg_i2s_clk_sel         : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_i2s0_clk_en         : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_i2s_0_ref_clk_oe    : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reserved_15             : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t ble_clk_sel             : 6; /* [21:16],        r/w,       0x10 */
+            uint32_t reserved_22_23          : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t ble_en                  : 1; /* [   24],        r/w,        0x1 */
+            uint32_t m154_zbEn               : 1; /* [   25],        r/w,        0x1 */
+            uint32_t reserved_26_27          : 2; /* [27:26],       rsvd,        0x0 */
+            uint32_t reg_cam_ref_clk_en      : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg_cam_ref_clk_src_sel : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_cam_ref_clk_div     : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg1;
+
+    /* 0x8 : clk_cfg2 */
+    union {
+        struct
+        {
+            uint32_t uart_clk_div     : 3; /* [ 2: 0],        r/w,        0x7 */
+            uint32_t reserved_3       : 1; /* [    3],       rsvd,        0x0 */
+            uint32_t uart_clk_en      : 1; /* [    4],        r/w,        0x1 */
+            uint32_t reserved_5_6     : 2; /* [ 6: 5],       rsvd,        0x0 */
+            uint32_t hbn_uart_clk_sel : 1; /* [    7],          r,        0x0 */
+            uint32_t sf_clk_div       : 3; /* [10: 8],        r/w,        0x3 */
+            uint32_t sf_clk_en        : 1; /* [   11],        r/w,        0x1 */
+            uint32_t sf_clk_sel       : 2; /* [13:12],        r/w,        0x2 */
+            uint32_t sf_clk_sel2      : 2; /* [15:14],        r/w,        0x0 */
+            uint32_t ir_clk_div       : 6; /* [21:16],        r/w,        0xf */
+            uint32_t reserved_22      : 1; /* [   22],       rsvd,        0x0 */
+            uint32_t ir_clk_en        : 1; /* [   23],        r/w,        0x1 */
+            uint32_t dma_clk_en       : 8; /* [31:24],        r/w,       0xff */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg2;
+
+    /* 0xC : clk_cfg3 */
+    union {
+        struct
+        {
+            uint32_t spi_clk_div           : 5; /* [ 4: 0],        r/w,        0x3 */
+            uint32_t cfg_sel_eth_ref_clk_o : 1; /* [    5],        r/w,        0x0 */
+            uint32_t cfg_inv_eth_ref_clk_o : 1; /* [    6],        r/w,        0x1 */
+            uint32_t cfg_inv_eth_tx_clk    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t spi_clk_en            : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cfg_inv_rf_test_clk_o : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cfg_inv_eth_rx_clk    : 1; /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_15        : 5; /* [15:11],       rsvd,        0x0 */
+            uint32_t i2c_clk_div           : 8; /* [23:16],        r/w,       0xff */
+            uint32_t i2c_clk_en            : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_27        : 3; /* [27:25],       rsvd,        0x0 */
+            uint32_t chip_clk_out_0_sel    : 2; /* [29:28],        r/w,        0x0 */
+            uint32_t chip_clk_out_1_sel    : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clk_cfg3;
+
+    /* 0x10 : swrst_cfg0 */
+    union {
+        struct
+        {
+            uint32_t swrst_s00     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s01     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3  : 2;  /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t swrst_s20     : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_7  : 3;  /* [ 7: 5],       rsvd,        0x0 */
+            uint32_t swrst_s30     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31 : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg0;
+
+    /* 0x14 : swrst_cfg1 */
+    union {
+        struct
+        {
+            uint32_t swrst_s10   : 1; /* [    0],        r/w,        0x0 */
+            uint32_t swrst_s11   : 1; /* [    1],        r/w,        0x0 */
+            uint32_t swrst_s12   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t swrst_s13   : 1; /* [    3],        r/w,        0x0 */
+            uint32_t swrst_s14   : 1; /* [    4],        r/w,        0x0 */
+            uint32_t swrst_s15   : 1; /* [    5],        r/w,        0x0 */
+            uint32_t swrst_s16   : 1; /* [    6],        r/w,        0x0 */
+            uint32_t swrst_s17   : 1; /* [    7],        r/w,        0x0 */
+            uint32_t swrst_s18   : 1; /* [    8],        r/w,        0x0 */
+            uint32_t swrst_s19   : 1; /* [    9],        r/w,        0x0 */
+            uint32_t swrst_s1a   : 1; /* [   10],        r/w,        0x0 */
+            uint32_t swrst_s1b   : 1; /* [   11],        r/w,        0x0 */
+            uint32_t swrst_s1c   : 1; /* [   12],        r/w,        0x0 */
+            uint32_t swrst_s1d   : 1; /* [   13],        r/w,        0x0 */
+            uint32_t swrst_s1e   : 1; /* [   14],        r/w,        0x0 */
+            uint32_t swrst_s1f   : 1; /* [   15],        r/w,        0x0 */
+            uint32_t swrst_s1a0  : 1; /* [   16],        r/w,        0x0 */
+            uint32_t swrst_s1a1  : 1; /* [   17],        r/w,        0x0 */
+            uint32_t swrst_s1a2  : 1; /* [   18],        r/w,        0x0 */
+            uint32_t swrst_s1a3  : 1; /* [   19],        r/w,        0x0 */
+            uint32_t swrst_s1a4  : 1; /* [   20],        r/w,        0x0 */
+            uint32_t swrst_s1a5  : 1; /* [   21],        r/w,        0x0 */
+            uint32_t swrst_s1a6  : 1; /* [   22],        r/w,        0x0 */
+            uint32_t swrst_s1a7  : 1; /* [   23],        r/w,        0x0 */
+            uint32_t swrst_s1a8  : 1; /* [   24],        r/w,        0x0 */
+            uint32_t swrst_s1a9  : 1; /* [   25],        r/w,        0x0 */
+            uint32_t swrst_s1aa  : 1; /* [   26],        r/w,        0x0 */
+            uint32_t swrst_s1ab  : 1; /* [   27],        r/w,        0x0 */
+            uint32_t swrst_s1ac  : 1; /* [   28],        r/w,        0x0 */
+            uint32_t swrst_s1ad  : 1; /* [   29],        r/w,        0x0 */
+            uint32_t swrst_s1ae  : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reserved_31 : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg1;
+
+    /* 0x18 : swrst_cfg2 */
+    union {
+        struct
+        {
+            uint32_t reg_ctrl_pwron_rst   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reg_ctrl_cpu_reset   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_ctrl_sys_reset   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t reg_ctrl_reset_dummy : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t reserved_8_23        : 16; /* [23: 8],       rsvd,        0x0 */
+            uint32_t pka_clk_sel          : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t reserved_25_31       : 7;  /* [31:25],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg2;
+
+    /* 0x1C : swrst_cfg3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } swrst_cfg3;
+
+    /* 0x20 : cgen_cfg0 */
+    union {
+        struct
+        {
+            uint32_t cgen_m        : 8;  /* [ 7: 0],        r/w,       0xff */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg0;
+
+    /* 0x24 : cgen_cfg1 */
+    union {
+        struct
+        {
+            uint32_t cgen_s1  : 16; /* [15: 0],        r/w,     0xcfff */
+            uint32_t cgen_s1a : 16; /* [31:16],        r/w,     0x9b23 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg1;
+
+    /* 0x28 : cgen_cfg2 */
+    union {
+        struct
+        {
+            uint32_t cgen_s2       : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3  : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t cgen_s3       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_31 : 27; /* [31: 5],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg2;
+
+    /* 0x2C : cgen_cfg3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cgen_cfg3;
+
+    /* 0x30 : MBIST_CTL */
+    union {
+        struct
+        {
+            uint32_t irom_mbist_mode        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t hsram_mem_mbist_mode   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t hsram_cache_mbist_mode : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t tag_mbist_mode         : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t ocram_mbist_mode       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t em_ram_mbist_mode      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_30          : 25; /* [30: 6],       rsvd,        0x0 */
+            uint32_t reg_mbist_rst_n        : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MBIST_CTL;
+
+    /* 0x34 : MBIST_STAT */
+    union {
+        struct
+        {
+            uint32_t irom_mbist_done        : 1;  /* [    0],          r,        0x0 */
+            uint32_t hsram_mem_mbist_done   : 1;  /* [    1],          r,        0x0 */
+            uint32_t hsram_cache_mbist_done : 1;  /* [    2],          r,        0x0 */
+            uint32_t tag_mbist_done         : 1;  /* [    3],          r,        0x0 */
+            uint32_t ocram_mbist_done       : 1;  /* [    4],          r,        0x0 */
+            uint32_t em_ram_mbist_done      : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_15          : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t irom_mbist_fail        : 1;  /* [   16],          r,        0x0 */
+            uint32_t hsram_mem_mbist_fail   : 1;  /* [   17],          r,        0x0 */
+            uint32_t hsram_cache_mbist_fail : 1;  /* [   18],          r,        0x0 */
+            uint32_t tag_mbist_fail         : 1;  /* [   19],          r,        0x0 */
+            uint32_t ocram_mbist_fail       : 1;  /* [   20],          r,        0x0 */
+            uint32_t em_ram_mbist_fail      : 1;  /* [   21],          r,        0x0 */
+            uint32_t reserved_22_31         : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } MBIST_STAT;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[24];
+
+    /* 0x50 : bmx_cfg1 */
+    union {
+        struct
+        {
+            uint32_t bmx_timeout_en      : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t bmx_arb_mode        : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t bmx_err_en          : 1; /* [    8],        r/w,        0x0 */
+            uint32_t bmx_busy_option_dis : 1; /* [    9],        r/w,        0x0 */
+            uint32_t bmx_gating_dis      : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t hsel_option         : 4; /* [15:12],        r/w,        0x0 */
+            uint32_t pds_apb_cfg         : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t hbn_apb_cfg         : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg1;
+
+    /* 0x54 : bmx_cfg2 */
+    union {
+        struct
+        {
+            uint32_t bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
+            uint32_t bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_7     : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_w_thre_bmx   : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reg_w_thre_l1c   : 2;  /* [11:10],        r/w,        0x0 */
+            uint32_t reserved_12_27   : 16; /* [27:12],       rsvd,        0x0 */
+            uint32_t bmx_dbg_sel      : 4;  /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_cfg2;
+
+    /* 0x58 : bmx_err_addr */
+    union {
+        struct
+        {
+            uint32_t bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_err_addr;
+
+    /* 0x5C : bmx_dbg_out */
+    union {
+        struct
+        {
+            uint32_t bmx_dbg_out : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } bmx_dbg_out;
+
+    /* 0x60 : rsv0 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv0;
+
+    /* 0x64 : rsv1 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv1;
+
+    /* 0x68 : rsv2 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rsv2;
+
+    /* 0x6C : rsv3 */
+    union {
+        struct
+        {
+            uint32_t rsvd_31_0 : 32; /* [31: 0],       rsvd, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } rsv3;
+
+    /* 0x70 : sram_ret */
+    union {
+        struct
+        {
+            uint32_t reg_sram_ret : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_ret;
+
+    /* 0x74 : sram_slp */
+    union {
+        struct
+        {
+            uint32_t reg_sram_slp : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sram_slp;
+
+    /* 0x78 : sram_parm */
+    union {
+        struct
+        {
+            uint32_t reg_sram_parm : 32; /* [31: 0],        r/w, 0x6a4c0c0c */
+        } BF;
+        uint32_t WORD;
+    } sram_parm;
+
+    /* 0x7C : seam_misc */
+    union {
+        struct
+        {
+            uint32_t em_sel        : 4;  /* [ 3: 0],        r/w,        0x3 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } seam_misc;
+
+    /* 0x80 : glb_parm */
+    union {
+        struct
+        {
+            uint32_t jtag_swap_set            : 8; /* [ 7: 0],        r/w,        0x4 */
+            uint32_t cfg_sflash2_swap_io0_io3 : 1; /* [    8],        r/w,        0x0 */
+            uint32_t cfg_sflash2_swap_cs_io2  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t cfg_flash_scenario       : 2; /* [11:10],        r/w,        0x0 */
+            uint32_t reg_spi_0_master_mode    : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_spi_0_swap           : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t reg_cci_use_jtag_pin     : 1; /* [   16],        r/w,        0x1 */
+            uint32_t p1_adc_test_with_cci     : 1; /* [   17],        r/w,        0x0 */
+            uint32_t p2_dac_test_with_cci     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t p3_cci_use_io_0_2_7      : 1; /* [   19],        r/w,        0x0 */
+            uint32_t p4_adc_test_with_jtag    : 1; /* [   20],        r/w,        0x0 */
+            uint32_t p5_dac_test_with_jtag    : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22              : 1; /* [   22],       rsvd,        0x0 */
+            uint32_t p6_jtag_use_io_0_2_7     : 1; /* [   23],        r/w,        0x0 */
+            uint32_t uart_swap_set            : 4; /* [27:24],        r/w,        0x0 */
+            uint32_t reserved_28              : 1; /* [   28],       rsvd,        0x0 */
+            uint32_t reg_kys_drv_val          : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_ext_rst_smt          : 1; /* [   30],        r/w,        0x0 */
+            uint32_t pin_sel_emac_cam         : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } glb_parm;
+
+    /* 0x84 : PDM_CLK_CTRL */
+    union {
+        struct
+        {
+            uint32_t reg_pdm0_clk_div : 6;  /* [ 5: 0],        r/w,        0x1 */
+            uint32_t reserved_6       : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t reg_pdm0_clk_en  : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t reserved_8_31    : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDM_CLK_CTRL;
+
+    /* 0x88 : GPIO_USE_PSRAM__IO */
+    union {
+        struct
+        {
+            uint32_t cfg_gpio_use_psram_io : 6;  /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_31         : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_USE_PSRAM__IO;
+
+    /* 0x8c  reserved */
+    uint8_t RESERVED0x8c[4];
+
+    /* 0x90 : CPU_CLK_CFG */
+    union {
+        struct
+        {
+            uint32_t cpu_rtc_div        : 17; /* [16: 0],        r/w,       0x10 */
+            uint32_t reserved_17        : 1;  /* [   17],       rsvd,        0x0 */
+            uint32_t cpu_rtc_en         : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t cpu_rtc_sel        : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t debug_ndreset_gate : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31     : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } CPU_CLK_CFG;
+
+    /* 0x94  reserved */
+    uint8_t RESERVED0x94[16];
+
+    /* 0xA4 : GPADC_32M_SRC_CTRL */
+    union {
+        struct
+        {
+            uint32_t gpadc_32m_clk_div : 6;  /* [ 5: 0],        r/w,        0x2 */
+            uint32_t reserved_6        : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t gpadc_32m_clk_sel : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_32m_div_en  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31     : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPADC_32M_SRC_CTRL;
+
+    /* 0xA8 : DIG32K_WAKEUP_CTRL */
+    union {
+        struct
+        {
+            uint32_t dig_32k_div            : 11; /* [10: 0],        r/w,      0x3e8 */
+            uint32_t reserved_11            : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t dig_32k_en             : 1;  /* [   12],        r/w,        0x1 */
+            uint32_t dig_32k_comp           : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15         : 2;  /* [15:14],       rsvd,        0x0 */
+            uint32_t dig_512k_div           : 7;  /* [22:16],        r/w,       0x3e */
+            uint32_t reserved_23            : 1;  /* [   23],       rsvd,        0x0 */
+            uint32_t dig_512k_en            : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t dig_512k_comp          : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t reserved_26_27         : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t dig_clk_src_sel        : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t reserved_30            : 1;  /* [   30],       rsvd,        0x0 */
+            uint32_t reg_en_platform_wakeup : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DIG32K_WAKEUP_CTRL;
+
+    /* 0xAC : WIFI_BT_COEX_CTRL */
+    union {
+        struct
+        {
+            uint32_t coex_bt_channel : 7;  /* [ 6: 0],        r/w,        0x0 */
+            uint32_t coex_bt_pti     : 4;  /* [10: 7],        r/w,        0x0 */
+            uint32_t coex_bt_bw      : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t en_gpio_bt_coex : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_31  : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } WIFI_BT_COEX_CTRL;
+
+    /* 0xB0 : BZ_COEX_CTRL */
+    union {
+        struct
+        {
+            uint32_t coex_en           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t wlan_en           : 1; /* [    1],        r/w,        0x0 */
+            uint32_t ble_rx_ignore     : 1; /* [    2],        r/w,        0x0 */
+            uint32_t m154_rx_ignore    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t bz_pri_thr        : 4; /* [ 7: 4],        r/w,        0x0 */
+            uint32_t bz_pri_en         : 1; /* [    8],        r/w,        0x1 */
+            uint32_t bz_pri_pol        : 1; /* [    9],        r/w,        0x1 */
+            uint32_t bz_active_pol     : 1; /* [   10],        r/w,        0x1 */
+            uint32_t bz_abort_pol      : 1; /* [   11],        r/w,        0x1 */
+            uint32_t coex_pri          : 1; /* [   12],        r/w,        0x0 */
+            uint32_t force_m154_win    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t force_ble_win     : 1; /* [   14],        r/w,        0x0 */
+            uint32_t coex_option       : 1; /* [   15],        r/w,        0x0 */
+            uint32_t coex_force_ch     : 7; /* [22:16],        r/w,        0x4 */
+            uint32_t reserved_23       : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t m154_rx_abort_dis : 1; /* [   24],        r/w,        0x0 */
+            uint32_t m154_tx_abort_dis : 1; /* [   25],        r/w,        0x0 */
+            uint32_t ble_rx_abort_dis  : 1; /* [   26],        r/w,        0x0 */
+            uint32_t ble_tx_abort_dis  : 1; /* [   27],        r/w,        0x0 */
+            uint32_t coex_arb          : 4; /* [31:28],          r,        0x8 */
+        } BF;
+        uint32_t WORD;
+    } BZ_COEX_CTRL;
+
+    /* 0xb4  reserved */
+    uint8_t RESERVED0xb4[12];
+
+    /* 0xC0 : UART_SIG_SEL_0 */
+    union {
+        struct
+        {
+            uint32_t uart_sig_0_sel : 4; /* [ 3: 0],        r/w,        0x0 */
+            uint32_t uart_sig_1_sel : 4; /* [ 7: 4],        r/w,        0x1 */
+            uint32_t uart_sig_2_sel : 4; /* [11: 8],        r/w,        0x2 */
+            uint32_t uart_sig_3_sel : 4; /* [15:12],        r/w,        0x3 */
+            uint32_t uart_sig_4_sel : 4; /* [19:16],        r/w,        0x4 */
+            uint32_t uart_sig_5_sel : 4; /* [23:20],        r/w,        0x5 */
+            uint32_t uart_sig_6_sel : 4; /* [27:24],        r/w,        0x6 */
+            uint32_t uart_sig_7_sel : 4; /* [31:28],        r/w,        0x7 */
+        } BF;
+        uint32_t WORD;
+    } UART_SIG_SEL_0;
+
+    /* 0xc4  reserved */
+    uint8_t RESERVED0xc4[12];
+
+    /* 0xD0 : DBG_SEL_LL */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_ll_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_LL;
+
+    /* 0xD4 : DBG_SEL_LH */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_lh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_LH;
+
+    /* 0xD8 : DBG_SEL_HL */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_hl_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_HL;
+
+    /* 0xDC : DBG_SEL_HH */
+    union {
+        struct
+        {
+            uint32_t reg_dbg_hh_ctrl : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } DBG_SEL_HH;
+
+    /* 0xE0 : debug */
+    union {
+        struct
+        {
+            uint32_t debug_oe : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t debug_i  : 31; /* [31: 1],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } debug;
+
+    /* 0xe4  reserved */
+    uint8_t RESERVED0xe4[28];
+
+    /* 0x100 : GPIO_CFGCTL0 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_0_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_0_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_func_sel : 5; /* [12: 8],        r/w,        0xe */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_1_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_1_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_func_sel : 5; /* [28:24],        r/w,        0xe */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL0;
+
+    /* 0x104 : GPIO_CFGCTL1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_2_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_2_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_2_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_2_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_2_func_sel : 5; /* [12: 8],        r/w,        0xe */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_3_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_3_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_3_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_3_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL1;
+
+    /* 0x108 : GPIO_CFGCTL2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_4_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_4_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_4_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_4_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_4_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_5_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_5_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_5_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_5_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL2;
+
+    /* 0x10C : GPIO_CFGCTL3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_6_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_6_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_6_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_6_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_6_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_7_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_7_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_7_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_7_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL3;
+
+    /* 0x110 : GPIO_CFGCTL4 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_8_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_8_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_8_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_8_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_8_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_ie       : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_9_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_9_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_9_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_9_func_sel : 5; /* [28:24],        r/w,        0xe */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL4;
+
+    /* 0x114 : GPIO_CFGCTL5 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_10_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_10_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_10_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_10_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_10_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_11_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_11_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_11_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_11_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL5;
+
+    /* 0x118 : GPIO_CFGCTL6 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_12_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_12_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_12_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_12_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_12_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_13_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_13_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_13_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_13_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL6;
+
+    /* 0x11C : GPIO_CFGCTL7 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_14_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_14_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_14_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_14_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_14_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_15_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_15_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_15_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_15_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL7;
+
+    /* 0x120 : GPIO_CFGCTL8 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_16_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_16_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_16_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_16_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_16_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_17_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_17_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_17_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_17_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL8;
+
+    /* 0x124 : GPIO_CFGCTL9 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_18_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_18_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_18_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_18_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_18_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_19_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_19_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_19_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_19_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL9;
+
+    /* 0x128 : GPIO_CFGCTL10 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_20_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_20_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_20_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_20_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_20_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_21_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_21_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_21_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL10;
+
+    /* 0x12C : GPIO_CFGCTL11 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_22_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_22_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_22_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_22_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_22_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_23_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_23_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_23_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_23_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL11;
+
+    /* 0x130 : GPIO_CFGCTL12 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_24_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_24_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_24_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_24_pd       : 1; /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_24_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_25_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_25_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_25_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_25_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL12;
+
+    /* 0x134 : GPIO_CFGCTL13 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_26_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_26_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_26_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_26_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_26_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_27_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_27_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_27_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_27_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL13;
+
+    /* 0x138 : GPIO_CFGCTL14 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_28_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_28_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_28_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_28_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_28_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_29_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_29_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_29_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_29_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_29_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL14;
+
+    /* 0x13C : GPIO_CFGCTL15 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_30_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_30_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_30_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_30_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_30_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_30_func_sel : 5; /* [12: 8],        r/w,        0xb */
+            uint32_t reserved_13_15       : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_31_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_31_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_31_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_31_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_31_func_sel : 5; /* [28:24],        r/w,        0xb */
+            uint32_t reserved_29_31       : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL15;
+
+    /* 0x140 : GPIO_CFGCTL16 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_32_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_32_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_32_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_32_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_32_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_33_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_33_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_33_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_33_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_33_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL16;
+
+    /* 0x144 : GPIO_CFGCTL17 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_34_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_34_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_34_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_34_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_34_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_35_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_35_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_35_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_35_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_35_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL17;
+
+    /* 0x148 : GPIO_CFGCTL18 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_36_ie  : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_36_smt : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_36_drv : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_36_pu  : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_36_pd  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_15   : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_37_ie  : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_37_smt : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_37_drv : 2;  /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_37_pu  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_37_pd  : 1;  /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_31  : 10; /* [31:22],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL18;
+
+    /* 0x14c  reserved */
+    uint8_t RESERVED0x14c[52];
+
+    /* 0x180 : GPIO_CFGCTL30 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_i  : 1; /* [    0],          r,        0x0 */
+            uint32_t reg_gpio_1_i  : 1; /* [    1],          r,        0x0 */
+            uint32_t reg_gpio_2_i  : 1; /* [    2],          r,        0x0 */
+            uint32_t reg_gpio_3_i  : 1; /* [    3],          r,        0x0 */
+            uint32_t reg_gpio_4_i  : 1; /* [    4],          r,        0x0 */
+            uint32_t reg_gpio_5_i  : 1; /* [    5],          r,        0x0 */
+            uint32_t reg_gpio_6_i  : 1; /* [    6],          r,        0x0 */
+            uint32_t reg_gpio_7_i  : 1; /* [    7],          r,        0x0 */
+            uint32_t reg_gpio_8_i  : 1; /* [    8],          r,        0x0 */
+            uint32_t reg_gpio_9_i  : 1; /* [    9],          r,        0x0 */
+            uint32_t reg_gpio_10_i : 1; /* [   10],          r,        0x0 */
+            uint32_t reg_gpio_11_i : 1; /* [   11],          r,        0x0 */
+            uint32_t reg_gpio_12_i : 1; /* [   12],          r,        0x0 */
+            uint32_t reg_gpio_13_i : 1; /* [   13],          r,        0x0 */
+            uint32_t reg_gpio_14_i : 1; /* [   14],          r,        0x0 */
+            uint32_t reg_gpio_15_i : 1; /* [   15],          r,        0x0 */
+            uint32_t reg_gpio_16_i : 1; /* [   16],          r,        0x0 */
+            uint32_t reg_gpio_17_i : 1; /* [   17],          r,        0x0 */
+            uint32_t reg_gpio_18_i : 1; /* [   18],          r,        0x0 */
+            uint32_t reg_gpio_19_i : 1; /* [   19],          r,        0x0 */
+            uint32_t reg_gpio_20_i : 1; /* [   20],          r,        0x0 */
+            uint32_t reg_gpio_21_i : 1; /* [   21],          r,        0x0 */
+            uint32_t reg_gpio_22_i : 1; /* [   22],          r,        0x0 */
+            uint32_t reg_gpio_23_i : 1; /* [   23],          r,        0x0 */
+            uint32_t reg_gpio_24_i : 1; /* [   24],          r,        0x0 */
+            uint32_t reg_gpio_25_i : 1; /* [   25],          r,        0x0 */
+            uint32_t reg_gpio_26_i : 1; /* [   26],          r,        0x0 */
+            uint32_t reg_gpio_27_i : 1; /* [   27],          r,        0x0 */
+            uint32_t reg_gpio_28_i : 1; /* [   28],          r,        0x0 */
+            uint32_t reg_gpio_29_i : 1; /* [   29],          r,        0x0 */
+            uint32_t reg_gpio_30_i : 1; /* [   30],          r,        0x0 */
+            uint32_t reg_gpio_31_i : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL30;
+
+    /* 0x184 : GPIO_CFGCTL31 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL31;
+
+    /* 0x188 : GPIO_CFGCTL32 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_o  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_1_o  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg_gpio_2_o  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg_gpio_3_o  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg_gpio_4_o  : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_5_o  : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_6_o  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_gpio_7_o  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_gpio_8_o  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_gpio_9_o  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reg_gpio_10_o : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg_gpio_11_o : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg_gpio_12_o : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_gpio_13_o : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_gpio_14_o : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg_gpio_15_o : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg_gpio_16_o : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_17_o : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reg_gpio_18_o : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_o : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg_gpio_20_o : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_o : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reg_gpio_22_o : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reg_gpio_23_o : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reg_gpio_24_o : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_25_o : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reg_gpio_26_o : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reg_gpio_27_o : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reg_gpio_28_o : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg_gpio_29_o : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_gpio_30_o : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reg_gpio_31_o : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL32;
+
+    /* 0x18C : GPIO_CFGCTL33 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL33;
+
+    /* 0x190 : GPIO_CFGCTL34 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_oe  : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_gpio_1_oe  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reg_gpio_2_oe  : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reg_gpio_3_oe  : 1; /* [    3],        r/w,        0x0 */
+            uint32_t reg_gpio_4_oe  : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_5_oe  : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reg_gpio_6_oe  : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_gpio_7_oe  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_gpio_8_oe  : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_gpio_9_oe  : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reg_gpio_10_oe : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg_gpio_11_oe : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg_gpio_12_oe : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_gpio_13_oe : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reg_gpio_14_oe : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reg_gpio_15_oe : 1; /* [   15],        r/w,        0x0 */
+            uint32_t reg_gpio_16_oe : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reg_gpio_17_oe : 1; /* [   17],        r/w,        0x0 */
+            uint32_t reg_gpio_18_oe : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reg_gpio_19_oe : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reg_gpio_20_oe : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_21_oe : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reg_gpio_22_oe : 1; /* [   22],        r/w,        0x0 */
+            uint32_t reg_gpio_23_oe : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reg_gpio_24_oe : 1; /* [   24],        r/w,        0x0 */
+            uint32_t reg_gpio_25_oe : 1; /* [   25],        r/w,        0x0 */
+            uint32_t reg_gpio_26_oe : 1; /* [   26],        r/w,        0x0 */
+            uint32_t reg_gpio_27_oe : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reg_gpio_28_oe : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg_gpio_29_oe : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_gpio_30_oe : 1; /* [   30],        r/w,        0x0 */
+            uint32_t reg_gpio_31_oe : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL34;
+
+    /* 0x194 : GPIO_CFGCTL35 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_31 : 32; /* [31: 0],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL35;
+
+    /* 0x198  reserved */
+    uint8_t RESERVED0x198[8];
+
+    /* 0x1A0 : GPIO_INT_MASK1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mask1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MASK1;
+
+    /* 0x1a4  reserved */
+    uint8_t RESERVED0x1a4[4];
+
+    /* 0x1A8 : GPIO_INT_STAT1 */
+    union {
+        struct
+        {
+            uint32_t gpio_int_stat1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_STAT1;
+
+    /* 0x1ac  reserved */
+    uint8_t RESERVED0x1ac[4];
+
+    /* 0x1B0 : GPIO_INT_CLR1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_clr1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_CLR1;
+
+    /* 0x1b4  reserved */
+    uint8_t RESERVED0x1b4[12];
+
+    /* 0x1C0 : GPIO_INT_MODE_SET1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set1 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET1;
+
+    /* 0x1C4 : GPIO_INT_MODE_SET2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set2 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET2;
+
+    /* 0x1C8 : GPIO_INT_MODE_SET3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set3 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET3;
+
+    /* 0x1CC : GPIO_INT_MODE_SET4 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int_mode_set4 : 6;  /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_31          : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT_MODE_SET4;
+
+    /* 0x1D0 : GPIO_INT2_MASK1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mask1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MASK1;
+
+    /* 0x1D4 : GPIO_INT2_STAT1 */
+    union {
+        struct
+        {
+            uint32_t gpio_int2_stat1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_STAT1;
+
+    /* 0x1D8 : GPIO_INT2_CLR1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_clr1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_CLR1;
+
+    /* 0x1DC : GPIO_INT2_MODE_SET1 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set1 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET1;
+
+    /* 0x1E0 : GPIO_INT2_MODE_SET2 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set2 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET2;
+
+    /* 0x1E4 : GPIO_INT2_MODE_SET3 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set3 : 30; /* [29: 0],        r/w,        0x0 */
+            uint32_t reserved_30_31          : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET3;
+
+    /* 0x1E8 : GPIO_INT2_MODE_SET4 */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_int2_mode_set4 : 6;  /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_31           : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_INT2_MODE_SET4;
+
+    /* 0x1ec  reserved */
+    uint8_t RESERVED0x1ec[20];
+
+    /* 0x200 : dll */
+    union {
+        struct
+        {
+            uint32_t dtest_en_dll_refclk : 1; /* [    0],        r/w,        0x0 */
+            uint32_t dtest_en_dll_outclk : 1; /* [    1],        r/w,        0x0 */
+            uint32_t ten_dll             : 1; /* [    2],        r/w,        0x0 */
+            uint32_t dll_clk_mmdiv_en    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t dll_clk_288M_en     : 1; /* [    4],        r/w,        0x1 */
+            uint32_t dll_clk_144M_en     : 1; /* [    5],        r/w,        0x1 */
+            uint32_t dll_clk_96M_en      : 1; /* [    6],        r/w,        0x1 */
+            uint32_t dll_clk_57p6M_en    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t dll_vctrl_sel       : 3; /* [10: 8],        r/w,        0x4 */
+            uint32_t reserved_11         : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t dll_prechg_sel      : 1; /* [   12],        r/w,        0x0 */
+            uint32_t dll_prechg_reg      : 1; /* [   13],        r/w,        0x1 */
+            uint32_t dll_prechg_en       : 1; /* [   14],        r/w,        0x1 */
+            uint32_t dll_vctrl_force_en  : 1; /* [   15],        r/w,        0x0 */
+            uint32_t dll_post_div        : 4; /* [19:16],        r/w,        0x2 */
+            uint32_t dll_delay_sel       : 2; /* [21:20],        r/w,        0x1 */
+            uint32_t dll_cp_op_en        : 1; /* [   22],        r/w,        0x1 */
+            uint32_t dll_cp_hiz          : 1; /* [   23],        r/w,        0x0 */
+            uint32_t reserved_24_27      : 4; /* [27:24],       rsvd,        0x0 */
+            uint32_t dll_refclk_sel      : 1; /* [   28],        r/w,        0x0 */
+            uint32_t dll_reset           : 1; /* [   29],        r/w,        0x1 */
+            uint32_t pu_dll              : 1; /* [   30],        r/w,        0x0 */
+            uint32_t ppu_dll             : 1; /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dll;
+
+    /* 0x204  reserved */
+    uint8_t RESERVED0x204[32];
+
+    /* 0x224 : led_driver */
+    union {
+        struct
+        {
+            uint32_t led_din_reg          : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t led_din_sel          : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t led_din_polarity_sel : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3           : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t leddrv_ibias         : 4;  /* [ 7: 4],        r/w,        0x8 */
+            uint32_t ir_rx_gpio_sel       : 4;  /* [11: 8],        r/w,        0x0 */
+            uint32_t reserved_12_27       : 16; /* [27:12],       rsvd,        0x0 */
+            uint32_t leddrv_out_en        : 2;  /* [29:28],        r/w,        0x3 */
+            uint32_t reserved_30          : 1;  /* [   30],       rsvd,        0x0 */
+            uint32_t pu_leddrv            : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } led_driver;
+
+    /* 0x228 : usb_xcvr */
+    union {
+        struct
+        {
+            uint32_t usb_ldo_vfb      : 3; /* [ 2: 0],        r/w,        0x3 */
+            uint32_t pu_usb_ldo       : 1; /* [    3],        r/w,        0x0 */
+            uint32_t usb_rout_nmos    : 3; /* [ 6: 4],        r/w,        0x3 */
+            uint32_t reserved_7       : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t usb_rout_pmos    : 3; /* [10: 8],        r/w,        0x3 */
+            uint32_t reserved_11      : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t usb_oeb_sel      : 1; /* [   12],         rw,        0x0 */
+            uint32_t usb_oeb_reg      : 1; /* [   13],         rw,        0x1 */
+            uint32_t usb_oeb          : 1; /* [   14],          r,        0x1 */
+            uint32_t reserved_15      : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t usb_data_convert : 1; /* [   16],         rw,        0x0 */
+            uint32_t reserved_17_19   : 3; /* [19:17],       rsvd,        0x0 */
+            uint32_t usb_enum         : 1; /* [   20],        r/w,        0x0 */
+            uint32_t usb_spd          : 1; /* [   21],        r/w,        0x1 */
+            uint32_t usb_sus          : 1; /* [   22],        r/w,        0x0 */
+            uint32_t pu_usb           : 1; /* [   23],        r/w,        0x0 */
+            uint32_t usb_bd           : 1; /* [   24],          r,        0x0 */
+            uint32_t usb_vim          : 1; /* [   25],          r,        0x0 */
+            uint32_t usb_vip          : 1; /* [   26],          r,        0x0 */
+            uint32_t usb_rcv          : 1; /* [   27],          r,        0x0 */
+            uint32_t reserved_28_31   : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_xcvr;
+
+    /* 0x22C : usb_xcvr_config */
+    union {
+        struct
+        {
+            uint32_t usb_v_hys_m         : 2; /* [ 1: 0],        r/w,        0x1 */
+            uint32_t usb_v_hys_p         : 2; /* [ 3: 2],        r/w,        0x1 */
+            uint32_t usb_bd_vth          : 3; /* [ 6: 4],        r/w,        0x1 */
+            uint32_t reg_usb_use_xcvr    : 1; /* [    7],        r/w,        0x1 */
+            uint32_t usb_str_drv         : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t reg_usb_use_ctrl    : 1; /* [   11],        r/w,        0x1 */
+            uint32_t usb_res_pullup_tune : 3; /* [14:12],        r/w,        0x2 */
+            uint32_t reserved_15         : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t usb_slewrate_m_fall : 3; /* [18:16],        r/w,        0x3 */
+            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t usb_slewrate_m_rise : 3; /* [22:20],        r/w,        0x4 */
+            uint32_t reserved_23         : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t usb_slewrate_p_fall : 3; /* [26:24],        r/w,        0x3 */
+            uint32_t reserved_27         : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t usb_slewrate_p_rise : 3; /* [30:28],        r/w,        0x4 */
+            uint32_t reserved_31         : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } usb_xcvr_config;
+
+    /* 0x230  reserved */
+    uint8_t RESERVED0x230[216];
+
+    /* 0x308 : gpdac_ctrl */
+    union {
+        struct
+        {
+            uint32_t gpdaca_rstn_ana : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t gpdacb_rstn_ana : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t reserved_2_6    : 5;  /* [ 6: 2],       rsvd,        0x0 */
+            uint32_t gpdac_test_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpdac_ref_sel   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpdac_test_sel  : 3;  /* [11: 9],        r/w,        0x0 */
+            uint32_t reserved_12_23  : 12; /* [23:12],       rsvd,        0x0 */
+            uint32_t gpdac_reserved  : 8;  /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } gpdac_ctrl;
+
+    /* 0x30C : gpdac_actrl */
+    union {
+        struct
+        {
+            uint32_t gpdac_a_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_ioa_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_a_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_a_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_actrl;
+
+    /* 0x310 : gpdac_bctrl */
+    union {
+        struct
+        {
+            uint32_t gpdac_b_en     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_iob_en   : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_17  : 16; /* [17: 2],       rsvd,        0x0 */
+            uint32_t gpdac_b_rng    : 2;  /* [19:18],        r/w,        0x3 */
+            uint32_t gpdac_b_outmux : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_31 : 9;  /* [31:23],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_bctrl;
+
+    /* 0x314 : gpdac_data */
+    union {
+        struct
+        {
+            uint32_t gpdac_b_data   : 10; /* [ 9: 0],        r/w,        0x0 */
+            uint32_t reserved_10_15 : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t gpdac_a_data   : 10; /* [25:16],        r/w,        0x0 */
+            uint32_t reserved_26_31 : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_data;
+
+    /* 0x318  reserved */
+    uint8_t RESERVED0x318[2792];
+
+    /* 0xE00 : chip_revision */
+    union {
+        struct
+        {
+            uint32_t chip_rev      : 4;  /* [ 3: 0],          r,        0x0 */
+            uint32_t reserved_4_31 : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } chip_revision;
+
+    /* 0xe04  reserved */
+    uint8_t RESERVED0xe04[252];
+
+    /* 0xF00 : tzc_glb_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_swrst_s00_lock       : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s01_lock       : 1; /* [    1],          r,        0x0 */
+            uint32_t reserved_2_7                 : 6; /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t tzc_glb_swrst_s30_lock       : 1; /* [    8],          r,        0x0 */
+            uint32_t reserved_9_11                : 3; /* [11: 9],       rsvd,        0x0 */
+            uint32_t tzc_glb_ctrl_pwron_rst_lock  : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_cpu_reset_lock  : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_sys_reset_lock  : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_ctrl_ungated_ap_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t reserved_16_24               : 9; /* [24:16],       rsvd,        0x0 */
+            uint32_t tzc_glb_misc_lock            : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_sram_lock            : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_l2c_lock             : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_bmx_lock             : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_dbg_lock             : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_mbist_lock           : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_clk_lock             : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_0;
+
+    /* 0xF04 : tzc_glb_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_swrst_s20_lock : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s21_lock : 1; /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s22_lock : 1; /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s23_lock : 1; /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s24_lock : 1; /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s25_lock : 1; /* [    5],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s26_lock : 1; /* [    6],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s27_lock : 1; /* [    7],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s28_lock : 1; /* [    8],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s29_lock : 1; /* [    9],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2a_lock : 1; /* [   10],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2b_lock : 1; /* [   11],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2c_lock : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2d_lock : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2e_lock : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s2f_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s10_lock : 1; /* [   16],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s11_lock : 1; /* [   17],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s12_lock : 1; /* [   18],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s13_lock : 1; /* [   19],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s14_lock : 1; /* [   20],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s15_lock : 1; /* [   21],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s16_lock : 1; /* [   22],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s17_lock : 1; /* [   23],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s18_lock : 1; /* [   24],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s19_lock : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1a_lock : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1b_lock : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1c_lock : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1d_lock : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1e_lock : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_swrst_s1f_lock : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_1;
+
+    /* 0xF08 : tzc_glb_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_gpio_0_lock  : 1; /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_gpio_1_lock  : 1; /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_gpio_2_lock  : 1; /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_gpio_3_lock  : 1; /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_gpio_4_lock  : 1; /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_gpio_5_lock  : 1; /* [    5],          r,        0x0 */
+            uint32_t tzc_glb_gpio_6_lock  : 1; /* [    6],          r,        0x0 */
+            uint32_t tzc_glb_gpio_7_lock  : 1; /* [    7],          r,        0x0 */
+            uint32_t tzc_glb_gpio_8_lock  : 1; /* [    8],          r,        0x0 */
+            uint32_t tzc_glb_gpio_9_lock  : 1; /* [    9],          r,        0x0 */
+            uint32_t tzc_glb_gpio_10_lock : 1; /* [   10],          r,        0x0 */
+            uint32_t tzc_glb_gpio_11_lock : 1; /* [   11],          r,        0x0 */
+            uint32_t tzc_glb_gpio_12_lock : 1; /* [   12],          r,        0x0 */
+            uint32_t tzc_glb_gpio_13_lock : 1; /* [   13],          r,        0x0 */
+            uint32_t tzc_glb_gpio_14_lock : 1; /* [   14],          r,        0x0 */
+            uint32_t tzc_glb_gpio_15_lock : 1; /* [   15],          r,        0x0 */
+            uint32_t tzc_glb_gpio_16_lock : 1; /* [   16],          r,        0x0 */
+            uint32_t tzc_glb_gpio_17_lock : 1; /* [   17],          r,        0x0 */
+            uint32_t tzc_glb_gpio_18_lock : 1; /* [   18],          r,        0x0 */
+            uint32_t tzc_glb_gpio_19_lock : 1; /* [   19],          r,        0x0 */
+            uint32_t tzc_glb_gpio_20_lock : 1; /* [   20],          r,        0x0 */
+            uint32_t tzc_glb_gpio_21_lock : 1; /* [   21],          r,        0x0 */
+            uint32_t tzc_glb_gpio_22_lock : 1; /* [   22],          r,        0x0 */
+            uint32_t tzc_glb_gpio_23_lock : 1; /* [   23],          r,        0x0 */
+            uint32_t tzc_glb_gpio_24_lock : 1; /* [   24],          r,        0x0 */
+            uint32_t tzc_glb_gpio_25_lock : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_glb_gpio_26_lock : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_glb_gpio_27_lock : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_glb_gpio_28_lock : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_glb_gpio_29_lock : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_glb_gpio_30_lock : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_glb_gpio_31_lock : 1; /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_2;
+
+    /* 0xF0C : tzc_glb_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t tzc_glb_gpio_32_lock : 1;  /* [    0],          r,        0x0 */
+            uint32_t tzc_glb_gpio_33_lock : 1;  /* [    1],          r,        0x0 */
+            uint32_t tzc_glb_gpio_34_lock : 1;  /* [    2],          r,        0x0 */
+            uint32_t tzc_glb_gpio_35_lock : 1;  /* [    3],          r,        0x0 */
+            uint32_t tzc_glb_gpio_36_lock : 1;  /* [    4],          r,        0x0 */
+            uint32_t tzc_glb_gpio_37_lock : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_31        : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_glb_ctrl_3;
+};
+
+typedef volatile struct glb_reg glb_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : GPIO_CFGCTL */
+#define GLB_GPIO_CFGCTL_OFFSET       (0x0)
+#define GLB_REG_GPIO_0_IE            GLB_REG_GPIO_0_IE
+#define GLB_REG_GPIO_0_IE_POS        (0U)
+#define GLB_REG_GPIO_0_IE_LEN        (1U)
+#define GLB_REG_GPIO_0_IE_MSK        (((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS)
+#define GLB_REG_GPIO_0_IE_UMSK       (~(((1U << GLB_REG_GPIO_0_IE_LEN) - 1) << GLB_REG_GPIO_0_IE_POS))
+#define GLB_REG_GPIO_0_SMT           GLB_REG_GPIO_0_SMT
+#define GLB_REG_GPIO_0_SMT_POS       (1U)
+#define GLB_REG_GPIO_0_SMT_LEN       (1U)
+#define GLB_REG_GPIO_0_SMT_MSK       (((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS)
+#define GLB_REG_GPIO_0_SMT_UMSK      (~(((1U << GLB_REG_GPIO_0_SMT_LEN) - 1) << GLB_REG_GPIO_0_SMT_POS))
+#define GLB_REG_GPIO_0_DRV           GLB_REG_GPIO_0_DRV
+#define GLB_REG_GPIO_0_DRV_POS       (2U)
+#define GLB_REG_GPIO_0_DRV_LEN       (2U)
+#define GLB_REG_GPIO_0_DRV_MSK       (((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS)
+#define GLB_REG_GPIO_0_DRV_UMSK      (~(((1U << GLB_REG_GPIO_0_DRV_LEN) - 1) << GLB_REG_GPIO_0_DRV_POS))
+#define GLB_REG_GPIO_0_PU            GLB_REG_GPIO_0_PU
+#define GLB_REG_GPIO_0_PU_POS        (4U)
+#define GLB_REG_GPIO_0_PU_LEN        (1U)
+#define GLB_REG_GPIO_0_PU_MSK        (((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS)
+#define GLB_REG_GPIO_0_PU_UMSK       (~(((1U << GLB_REG_GPIO_0_PU_LEN) - 1) << GLB_REG_GPIO_0_PU_POS))
+#define GLB_REG_GPIO_0_PD            GLB_REG_GPIO_0_PD
+#define GLB_REG_GPIO_0_PD_POS        (5U)
+#define GLB_REG_GPIO_0_PD_LEN        (1U)
+#define GLB_REG_GPIO_0_PD_MSK        (((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS)
+#define GLB_REG_GPIO_0_PD_UMSK       (~(((1U << GLB_REG_GPIO_0_PD_LEN) - 1) << GLB_REG_GPIO_0_PD_POS))
+#define GLB_REG_GPIO_0_FUNC_SEL      GLB_REG_GPIO_0_FUNC_SEL
+#define GLB_REG_GPIO_0_FUNC_SEL_POS  (8U)
+#define GLB_REG_GPIO_0_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_0_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS)
+#define GLB_REG_GPIO_0_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_0_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_0_FUNC_SEL_POS))
+#define GLB_REG_GPIO_1_IE            GLB_REG_GPIO_1_IE
+#define GLB_REG_GPIO_1_IE_POS        (16U)
+#define GLB_REG_GPIO_1_IE_LEN        (1U)
+#define GLB_REG_GPIO_1_IE_MSK        (((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS)
+#define GLB_REG_GPIO_1_IE_UMSK       (~(((1U << GLB_REG_GPIO_1_IE_LEN) - 1) << GLB_REG_GPIO_1_IE_POS))
+#define GLB_REG_GPIO_1_SMT           GLB_REG_GPIO_1_SMT
+#define GLB_REG_GPIO_1_SMT_POS       (17U)
+#define GLB_REG_GPIO_1_SMT_LEN       (1U)
+#define GLB_REG_GPIO_1_SMT_MSK       (((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS)
+#define GLB_REG_GPIO_1_SMT_UMSK      (~(((1U << GLB_REG_GPIO_1_SMT_LEN) - 1) << GLB_REG_GPIO_1_SMT_POS))
+#define GLB_REG_GPIO_1_DRV           GLB_REG_GPIO_1_DRV
+#define GLB_REG_GPIO_1_DRV_POS       (18U)
+#define GLB_REG_GPIO_1_DRV_LEN       (2U)
+#define GLB_REG_GPIO_1_DRV_MSK       (((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS)
+#define GLB_REG_GPIO_1_DRV_UMSK      (~(((1U << GLB_REG_GPIO_1_DRV_LEN) - 1) << GLB_REG_GPIO_1_DRV_POS))
+#define GLB_REG_GPIO_1_PU            GLB_REG_GPIO_1_PU
+#define GLB_REG_GPIO_1_PU_POS        (20U)
+#define GLB_REG_GPIO_1_PU_LEN        (1U)
+#define GLB_REG_GPIO_1_PU_MSK        (((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS)
+#define GLB_REG_GPIO_1_PU_UMSK       (~(((1U << GLB_REG_GPIO_1_PU_LEN) - 1) << GLB_REG_GPIO_1_PU_POS))
+#define GLB_REG_GPIO_1_PD            GLB_REG_GPIO_1_PD
+#define GLB_REG_GPIO_1_PD_POS        (21U)
+#define GLB_REG_GPIO_1_PD_LEN        (1U)
+#define GLB_REG_GPIO_1_PD_MSK        (((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS)
+#define GLB_REG_GPIO_1_PD_UMSK       (~(((1U << GLB_REG_GPIO_1_PD_LEN) - 1) << GLB_REG_GPIO_1_PD_POS))
+#define GLB_REG_GPIO_1_FUNC_SEL      GLB_REG_GPIO_1_FUNC_SEL
+#define GLB_REG_GPIO_1_FUNC_SEL_POS  (24U)
+#define GLB_REG_GPIO_1_FUNC_SEL_LEN  (5U)
+#define GLB_REG_GPIO_1_FUNC_SEL_MSK  (((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS)
+#define GLB_REG_GPIO_1_FUNC_SEL_UMSK (~(((1U << GLB_REG_GPIO_1_FUNC_SEL_LEN) - 1) << GLB_REG_GPIO_1_FUNC_SEL_POS))
+
+struct glb_gpio_reg {
+    /* 0x0 : GPIO_CFGCTL */
+    union {
+        struct
+        {
+            uint32_t reg_gpio_0_ie       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_gpio_0_smt      : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_gpio_0_drv      : 2; /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pu       : 1; /* [    4],        r/w,        0x0 */
+            uint32_t reg_gpio_0_pd       : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7        : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t reg_gpio_0_func_sel : 5; /* [12: 8],        r/w,        0xe */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_ie       : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_gpio_1_smt      : 1; /* [   17],        r/w,        0x1 */
+            uint32_t reg_gpio_1_drv      : 2; /* [19:18],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pu       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t reg_gpio_1_pd       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t reserved_22_23      : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t reg_gpio_1_func_sel : 5; /* [28:24],        r/w,        0xe */
+            uint32_t reserved_29_31      : 3; /* [31:29],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } GPIO_CFGCTL;
+};
+
+typedef volatile struct glb_gpio_reg glb_gpio_reg_t;
+
+#define GLB_GPIO_OFFSET           0x100
+#define GLB_GPIO_INPUT_OFFSET     0x180
+#define GLB_GPIO_OUTPUT_OFFSET    0x188
+#define GLB_GPIO_OUTPUT_EN_OFFSET 0x190
+
+#endif /* __GLB_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/gpip_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/gpip_reg.h
new file mode 100755
index 0000000000..13a5e89201
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/gpip_reg.h
@@ -0,0 +1,317 @@
+/**
+  ******************************************************************************
+  * @file    gpip_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __GPIP_REG_H__
+#define __GPIP_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : gpadc_config */
+#define GPIP_GPADC_CONFIG_OFFSET           (0x0)
+#define GPIP_GPADC_DMA_EN                  GPIP_GPADC_DMA_EN
+#define GPIP_GPADC_DMA_EN_POS              (0U)
+#define GPIP_GPADC_DMA_EN_LEN              (1U)
+#define GPIP_GPADC_DMA_EN_MSK              (((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS)
+#define GPIP_GPADC_DMA_EN_UMSK             (~(((1U << GPIP_GPADC_DMA_EN_LEN) - 1) << GPIP_GPADC_DMA_EN_POS))
+#define GPIP_GPADC_FIFO_CLR                GPIP_GPADC_FIFO_CLR
+#define GPIP_GPADC_FIFO_CLR_POS            (1U)
+#define GPIP_GPADC_FIFO_CLR_LEN            (1U)
+#define GPIP_GPADC_FIFO_CLR_MSK            (((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS)
+#define GPIP_GPADC_FIFO_CLR_UMSK           (~(((1U << GPIP_GPADC_FIFO_CLR_LEN) - 1) << GPIP_GPADC_FIFO_CLR_POS))
+#define GPIP_GPADC_FIFO_NE                 GPIP_GPADC_FIFO_NE
+#define GPIP_GPADC_FIFO_NE_POS             (2U)
+#define GPIP_GPADC_FIFO_NE_LEN             (1U)
+#define GPIP_GPADC_FIFO_NE_MSK             (((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS)
+#define GPIP_GPADC_FIFO_NE_UMSK            (~(((1U << GPIP_GPADC_FIFO_NE_LEN) - 1) << GPIP_GPADC_FIFO_NE_POS))
+#define GPIP_GPADC_FIFO_FULL               GPIP_GPADC_FIFO_FULL
+#define GPIP_GPADC_FIFO_FULL_POS           (3U)
+#define GPIP_GPADC_FIFO_FULL_LEN           (1U)
+#define GPIP_GPADC_FIFO_FULL_MSK           (((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS)
+#define GPIP_GPADC_FIFO_FULL_UMSK          (~(((1U << GPIP_GPADC_FIFO_FULL_LEN) - 1) << GPIP_GPADC_FIFO_FULL_POS))
+#define GPIP_GPADC_RDY                     GPIP_GPADC_RDY
+#define GPIP_GPADC_RDY_POS                 (4U)
+#define GPIP_GPADC_RDY_LEN                 (1U)
+#define GPIP_GPADC_RDY_MSK                 (((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS)
+#define GPIP_GPADC_RDY_UMSK                (~(((1U << GPIP_GPADC_RDY_LEN) - 1) << GPIP_GPADC_RDY_POS))
+#define GPIP_GPADC_FIFO_OVERRUN            GPIP_GPADC_FIFO_OVERRUN
+#define GPIP_GPADC_FIFO_OVERRUN_POS        (5U)
+#define GPIP_GPADC_FIFO_OVERRUN_LEN        (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_MSK        (((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_UMSK       (~(((1U << GPIP_GPADC_FIFO_OVERRUN_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN           GPIP_GPADC_FIFO_UNDERRUN
+#define GPIP_GPADC_FIFO_UNDERRUN_POS       (6U)
+#define GPIP_GPADC_FIFO_UNDERRUN_LEN       (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MSK       (((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_UMSK      (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_POS))
+#define GPIP_GPADC_FIFO_RDY                GPIP_GPADC_FIFO_RDY
+#define GPIP_GPADC_FIFO_RDY_POS            (7U)
+#define GPIP_GPADC_FIFO_RDY_LEN            (1U)
+#define GPIP_GPADC_FIFO_RDY_MSK            (((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS)
+#define GPIP_GPADC_FIFO_RDY_UMSK           (~(((1U << GPIP_GPADC_FIFO_RDY_LEN) - 1) << GPIP_GPADC_FIFO_RDY_POS))
+#define GPIP_GPADC_RDY_CLR                 GPIP_GPADC_RDY_CLR
+#define GPIP_GPADC_RDY_CLR_POS             (8U)
+#define GPIP_GPADC_RDY_CLR_LEN             (1U)
+#define GPIP_GPADC_RDY_CLR_MSK             (((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS)
+#define GPIP_GPADC_RDY_CLR_UMSK            (~(((1U << GPIP_GPADC_RDY_CLR_LEN) - 1) << GPIP_GPADC_RDY_CLR_POS))
+#define GPIP_GPADC_FIFO_OVERRUN_CLR        GPIP_GPADC_FIFO_OVERRUN_CLR
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_POS    (9U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_LEN    (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_MSK    (((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_CLR_UMSK   (~(((1U << GPIP_GPADC_FIFO_OVERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_CLR_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR       GPIP_GPADC_FIFO_UNDERRUN_CLR
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_POS   (10U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN   (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_MSK   (((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_CLR_UMSK  (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_CLR_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_CLR_POS))
+#define GPIP_GPADC_RDY_MASK                GPIP_GPADC_RDY_MASK
+#define GPIP_GPADC_RDY_MASK_POS            (12U)
+#define GPIP_GPADC_RDY_MASK_LEN            (1U)
+#define GPIP_GPADC_RDY_MASK_MSK            (((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS)
+#define GPIP_GPADC_RDY_MASK_UMSK           (~(((1U << GPIP_GPADC_RDY_MASK_LEN) - 1) << GPIP_GPADC_RDY_MASK_POS))
+#define GPIP_GPADC_FIFO_OVERRUN_MASK       GPIP_GPADC_FIFO_OVERRUN_MASK
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_POS   (13U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_LEN   (1U)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_MSK   (((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS)
+#define GPIP_GPADC_FIFO_OVERRUN_MASK_UMSK  (~(((1U << GPIP_GPADC_FIFO_OVERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_OVERRUN_MASK_POS))
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK      GPIP_GPADC_FIFO_UNDERRUN_MASK
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_POS  (14U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN  (1U)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_MSK  (((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS)
+#define GPIP_GPADC_FIFO_UNDERRUN_MASK_UMSK (~(((1U << GPIP_GPADC_FIFO_UNDERRUN_MASK_LEN) - 1) << GPIP_GPADC_FIFO_UNDERRUN_MASK_POS))
+#define GPIP_GPADC_FIFO_RDY_MASK           GPIP_GPADC_FIFO_RDY_MASK
+#define GPIP_GPADC_FIFO_RDY_MASK_POS       (15U)
+#define GPIP_GPADC_FIFO_RDY_MASK_LEN       (1U)
+#define GPIP_GPADC_FIFO_RDY_MASK_MSK       (((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS)
+#define GPIP_GPADC_FIFO_RDY_MASK_UMSK      (~(((1U << GPIP_GPADC_FIFO_RDY_MASK_LEN) - 1) << GPIP_GPADC_FIFO_RDY_MASK_POS))
+#define GPIP_GPADC_FIFO_DATA_COUNT         GPIP_GPADC_FIFO_DATA_COUNT
+#define GPIP_GPADC_FIFO_DATA_COUNT_POS     (16U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_LEN     (6U)
+#define GPIP_GPADC_FIFO_DATA_COUNT_MSK     (((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS)
+#define GPIP_GPADC_FIFO_DATA_COUNT_UMSK    (~(((1U << GPIP_GPADC_FIFO_DATA_COUNT_LEN) - 1) << GPIP_GPADC_FIFO_DATA_COUNT_POS))
+#define GPIP_GPADC_FIFO_THL                GPIP_GPADC_FIFO_THL
+#define GPIP_GPADC_FIFO_THL_POS            (22U)
+#define GPIP_GPADC_FIFO_THL_LEN            (2U)
+#define GPIP_GPADC_FIFO_THL_MSK            (((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS)
+#define GPIP_GPADC_FIFO_THL_UMSK           (~(((1U << GPIP_GPADC_FIFO_THL_LEN) - 1) << GPIP_GPADC_FIFO_THL_POS))
+
+/* 0x4 : gpadc_dma_rdata */
+#define GPIP_GPADC_DMA_RDATA_OFFSET (0x4)
+#define GPIP_GPADC_DMA_RDATA        GPIP_GPADC_DMA_RDATA
+#define GPIP_GPADC_DMA_RDATA_POS    (0U)
+#define GPIP_GPADC_DMA_RDATA_LEN    (26U)
+#define GPIP_GPADC_DMA_RDATA_MSK    (((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS)
+#define GPIP_GPADC_DMA_RDATA_UMSK   (~(((1U << GPIP_GPADC_DMA_RDATA_LEN) - 1) << GPIP_GPADC_DMA_RDATA_POS))
+
+/* 0x40 : gpdac_config */
+#define GPIP_GPDAC_CONFIG_OFFSET (0x40)
+#define GPIP_GPDAC_EN            GPIP_GPDAC_EN
+#define GPIP_GPDAC_EN_POS        (0U)
+#define GPIP_GPDAC_EN_LEN        (1U)
+#define GPIP_GPDAC_EN_MSK        (((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS)
+#define GPIP_GPDAC_EN_UMSK       (~(((1U << GPIP_GPDAC_EN_LEN) - 1) << GPIP_GPDAC_EN_POS))
+#define GPIP_GPDAC_EN2           GPIP_GPDAC_EN2
+#define GPIP_GPDAC_EN2_POS       (1U)
+#define GPIP_GPDAC_EN2_LEN       (1U)
+#define GPIP_GPDAC_EN2_MSK       (((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS)
+#define GPIP_GPDAC_EN2_UMSK      (~(((1U << GPIP_GPDAC_EN2_LEN) - 1) << GPIP_GPDAC_EN2_POS))
+#define GPIP_DSM_MODE            GPIP_DSM_MODE
+#define GPIP_DSM_MODE_POS        (4U)
+#define GPIP_DSM_MODE_LEN        (2U)
+#define GPIP_DSM_MODE_MSK        (((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS)
+#define GPIP_DSM_MODE_UMSK       (~(((1U << GPIP_DSM_MODE_LEN) - 1) << GPIP_DSM_MODE_POS))
+#define GPIP_GPDAC_MODE          GPIP_GPDAC_MODE
+#define GPIP_GPDAC_MODE_POS      (8U)
+#define GPIP_GPDAC_MODE_LEN      (3U)
+#define GPIP_GPDAC_MODE_MSK      (((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS)
+#define GPIP_GPDAC_MODE_UMSK     (~(((1U << GPIP_GPDAC_MODE_LEN) - 1) << GPIP_GPDAC_MODE_POS))
+#define GPIP_GPDAC_CH_A_SEL      GPIP_GPDAC_CH_A_SEL
+#define GPIP_GPDAC_CH_A_SEL_POS  (16U)
+#define GPIP_GPDAC_CH_A_SEL_LEN  (4U)
+#define GPIP_GPDAC_CH_A_SEL_MSK  (((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS)
+#define GPIP_GPDAC_CH_A_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_A_SEL_LEN) - 1) << GPIP_GPDAC_CH_A_SEL_POS))
+#define GPIP_GPDAC_CH_B_SEL      GPIP_GPDAC_CH_B_SEL
+#define GPIP_GPDAC_CH_B_SEL_POS  (20U)
+#define GPIP_GPDAC_CH_B_SEL_LEN  (4U)
+#define GPIP_GPDAC_CH_B_SEL_MSK  (((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS)
+#define GPIP_GPDAC_CH_B_SEL_UMSK (~(((1U << GPIP_GPDAC_CH_B_SEL_LEN) - 1) << GPIP_GPDAC_CH_B_SEL_POS))
+
+/* 0x44 : gpdac_dma_config */
+#define GPIP_GPDAC_DMA_CONFIG_OFFSET (0x44)
+#define GPIP_GPDAC_DMA_TX_EN         GPIP_GPDAC_DMA_TX_EN
+#define GPIP_GPDAC_DMA_TX_EN_POS     (0U)
+#define GPIP_GPDAC_DMA_TX_EN_LEN     (1U)
+#define GPIP_GPDAC_DMA_TX_EN_MSK     (((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS)
+#define GPIP_GPDAC_DMA_TX_EN_UMSK    (~(((1U << GPIP_GPDAC_DMA_TX_EN_LEN) - 1) << GPIP_GPDAC_DMA_TX_EN_POS))
+#define GPIP_GPDAC_DMA_FORMAT        GPIP_GPDAC_DMA_FORMAT
+#define GPIP_GPDAC_DMA_FORMAT_POS    (4U)
+#define GPIP_GPDAC_DMA_FORMAT_LEN    (2U)
+#define GPIP_GPDAC_DMA_FORMAT_MSK    (((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS)
+#define GPIP_GPDAC_DMA_FORMAT_UMSK   (~(((1U << GPIP_GPDAC_DMA_FORMAT_LEN) - 1) << GPIP_GPDAC_DMA_FORMAT_POS))
+
+/* 0x48 : gpdac_dma_wdata */
+#define GPIP_GPDAC_DMA_WDATA_OFFSET (0x48)
+#define GPIP_GPDAC_DMA_WDATA        GPIP_GPDAC_DMA_WDATA
+#define GPIP_GPDAC_DMA_WDATA_POS    (0U)
+#define GPIP_GPDAC_DMA_WDATA_LEN    (32U)
+#define GPIP_GPDAC_DMA_WDATA_MSK    (((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS)
+#define GPIP_GPDAC_DMA_WDATA_UMSK   (~(((1U << GPIP_GPDAC_DMA_WDATA_LEN) - 1) << GPIP_GPDAC_DMA_WDATA_POS))
+
+/* 0x4C : gpdac_tx_fifo_status */
+#define GPIP_GPDAC_TX_FIFO_STATUS_OFFSET (0x4C)
+#define GPIP_TX_FIFO_EMPTY               GPIP_TX_FIFO_EMPTY
+#define GPIP_TX_FIFO_EMPTY_POS           (0U)
+#define GPIP_TX_FIFO_EMPTY_LEN           (1U)
+#define GPIP_TX_FIFO_EMPTY_MSK           (((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS)
+#define GPIP_TX_FIFO_EMPTY_UMSK          (~(((1U << GPIP_TX_FIFO_EMPTY_LEN) - 1) << GPIP_TX_FIFO_EMPTY_POS))
+#define GPIP_TX_FIFO_FULL                GPIP_TX_FIFO_FULL
+#define GPIP_TX_FIFO_FULL_POS            (1U)
+#define GPIP_TX_FIFO_FULL_LEN            (1U)
+#define GPIP_TX_FIFO_FULL_MSK            (((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS)
+#define GPIP_TX_FIFO_FULL_UMSK           (~(((1U << GPIP_TX_FIFO_FULL_LEN) - 1) << GPIP_TX_FIFO_FULL_POS))
+#define GPIP_TX_CS                       GPIP_TX_CS
+#define GPIP_TX_CS_POS                   (2U)
+#define GPIP_TX_CS_LEN                   (2U)
+#define GPIP_TX_CS_MSK                   (((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS)
+#define GPIP_TX_CS_UMSK                  (~(((1U << GPIP_TX_CS_LEN) - 1) << GPIP_TX_CS_POS))
+#define GPIP_TXFIFORDPTR                 GPIP_TXFIFORDPTR
+#define GPIP_TXFIFORDPTR_POS             (4U)
+#define GPIP_TXFIFORDPTR_LEN             (3U)
+#define GPIP_TXFIFORDPTR_MSK             (((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS)
+#define GPIP_TXFIFORDPTR_UMSK            (~(((1U << GPIP_TXFIFORDPTR_LEN) - 1) << GPIP_TXFIFORDPTR_POS))
+#define GPIP_TXFIFOWRPTR                 GPIP_TXFIFOWRPTR
+#define GPIP_TXFIFOWRPTR_POS             (8U)
+#define GPIP_TXFIFOWRPTR_LEN             (2U)
+#define GPIP_TXFIFOWRPTR_MSK             (((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS)
+#define GPIP_TXFIFOWRPTR_UMSK            (~(((1U << GPIP_TXFIFOWRPTR_LEN) - 1) << GPIP_TXFIFOWRPTR_POS))
+
+struct gpip_reg {
+    /* 0x0 : gpadc_config */
+    union {
+        struct
+        {
+            uint32_t gpadc_dma_en             : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpadc_fifo_clr           : 1; /* [    1],        w1c,        0x0 */
+            uint32_t gpadc_fifo_ne            : 1; /* [    2],          r,        0x0 */
+            uint32_t gpadc_fifo_full          : 1; /* [    3],          r,        0x0 */
+            uint32_t gpadc_rdy                : 1; /* [    4],          r,        0x0 */
+            uint32_t gpadc_fifo_overrun       : 1; /* [    5],          r,        0x0 */
+            uint32_t gpadc_fifo_underrun      : 1; /* [    6],          r,        0x0 */
+            uint32_t gpadc_fifo_rdy           : 1; /* [    7],          r,        0x0 */
+            uint32_t gpadc_rdy_clr            : 1; /* [    8],        w1c,        0x0 */
+            uint32_t gpadc_fifo_overrun_clr   : 1; /* [    9],        w1c,        0x0 */
+            uint32_t gpadc_fifo_underrun_clr  : 1; /* [   10],        w1c,        0x0 */
+            uint32_t reserved_11              : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t gpadc_rdy_mask           : 1; /* [   12],        r/w,        0x0 */
+            uint32_t gpadc_fifo_overrun_mask  : 1; /* [   13],        r/w,        0x0 */
+            uint32_t gpadc_fifo_underrun_mask : 1; /* [   14],        r/w,        0x0 */
+            uint32_t gpadc_fifo_rdy_mask      : 1; /* [   15],        r/w,        0x1 */
+            uint32_t gpadc_fifo_data_count    : 6; /* [21:16],          r,        0x0 */
+            uint32_t gpadc_fifo_thl           : 2; /* [23:22],        r/w,        0x0 */
+            uint32_t rsvd_31_24               : 8; /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_config;
+
+    /* 0x4 : gpadc_dma_rdata */
+    union {
+        struct
+        {
+            uint32_t gpadc_dma_rdata : 26; /* [25: 0],          r,        0x0 */
+            uint32_t rsvd_31_26      : 6;  /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpadc_dma_rdata;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[56];
+
+    /* 0x40 : gpdac_config */
+    union {
+        struct
+        {
+            uint32_t gpdac_en       : 1; /* [    0],        r/w,        0x0 */
+            uint32_t gpdac_en2      : 1; /* [    1],        r/w,        0x0 */
+            uint32_t reserved_2_3   : 2; /* [ 3: 2],       rsvd,        0x0 */
+            uint32_t dsm_mode       : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_7   : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t gpdac_mode     : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t reserved_11_15 : 5; /* [15:11],       rsvd,        0x0 */
+            uint32_t gpdac_ch_a_sel : 4; /* [19:16],        r/w,        0x0 */
+            uint32_t gpdac_ch_b_sel : 4; /* [23:20],        r/w,        0x0 */
+            uint32_t rsvd_31_24     : 8; /* [31:24],       rsvd,        0xd */
+        } BF;
+        uint32_t WORD;
+    } gpdac_config;
+
+    /* 0x44 : gpdac_dma_config */
+    union {
+        struct
+        {
+            uint32_t gpdac_dma_tx_en  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3     : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t gpdac_dma_format : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6_31    : 26; /* [31: 6],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_dma_config;
+
+    /* 0x48 : gpdac_dma_wdata */
+    union {
+        struct
+        {
+            uint32_t gpdac_dma_wdata : 32; /* [31: 0],          w,          x */
+        } BF;
+        uint32_t WORD;
+    } gpdac_dma_wdata;
+
+    /* 0x4C : gpdac_tx_fifo_status */
+    union {
+        struct
+        {
+            uint32_t tx_fifo_empty  : 1;  /* [    0],          r,        0x0 */
+            uint32_t tx_fifo_full   : 1;  /* [    1],          r,        0x0 */
+            uint32_t tx_cs          : 2;  /* [ 3: 2],          r,        0x0 */
+            uint32_t TxFifoRdPtr    : 3;  /* [ 6: 4],          r,        0x4 */
+            uint32_t reserved_7     : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t TxFifoWrPtr    : 2;  /* [ 9: 8],          r,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } gpdac_tx_fifo_status;
+};
+
+typedef volatile struct gpip_reg gpip_reg_t;
+
+#endif /* __GPIP_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/hbn_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/hbn_reg.h
new file mode 100755
index 0000000000..26a2158ca0
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/hbn_reg.h
@@ -0,0 +1,814 @@
+/**
+  ******************************************************************************
+  * @file    hbn_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __HBN_REG_H__
+#define __HBN_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : HBN_CTL */
+#define HBN_CTL_OFFSET                (0x0)
+#define HBN_RTC_CTL                   HBN_RTC_CTL
+#define HBN_RTC_CTL_POS               (0U)
+#define HBN_RTC_CTL_LEN               (7U)
+#define HBN_RTC_CTL_MSK               (((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS)
+#define HBN_RTC_CTL_UMSK              (~(((1U << HBN_RTC_CTL_LEN) - 1) << HBN_RTC_CTL_POS))
+#define HBN_MODE                      HBN_MODE
+#define HBN_MODE_POS                  (7U)
+#define HBN_MODE_LEN                  (1U)
+#define HBN_MODE_MSK                  (((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS)
+#define HBN_MODE_UMSK                 (~(((1U << HBN_MODE_LEN) - 1) << HBN_MODE_POS))
+#define HBN_TRAP_MODE                 HBN_TRAP_MODE
+#define HBN_TRAP_MODE_POS             (8U)
+#define HBN_TRAP_MODE_LEN             (1U)
+#define HBN_TRAP_MODE_MSK             (((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS)
+#define HBN_TRAP_MODE_UMSK            (~(((1U << HBN_TRAP_MODE_LEN) - 1) << HBN_TRAP_MODE_POS))
+#define HBN_PWRDN_HBN_CORE            HBN_PWRDN_HBN_CORE
+#define HBN_PWRDN_HBN_CORE_POS        (9U)
+#define HBN_PWRDN_HBN_CORE_LEN        (1U)
+#define HBN_PWRDN_HBN_CORE_MSK        (((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS)
+#define HBN_PWRDN_HBN_CORE_UMSK       (~(((1U << HBN_PWRDN_HBN_CORE_LEN) - 1) << HBN_PWRDN_HBN_CORE_POS))
+#define HBN_PWRDN_HBN_RTC             HBN_PWRDN_HBN_RTC
+#define HBN_PWRDN_HBN_RTC_POS         (11U)
+#define HBN_PWRDN_HBN_RTC_LEN         (1U)
+#define HBN_PWRDN_HBN_RTC_MSK         (((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS)
+#define HBN_PWRDN_HBN_RTC_UMSK        (~(((1U << HBN_PWRDN_HBN_RTC_LEN) - 1) << HBN_PWRDN_HBN_RTC_POS))
+#define HBN_SW_RST                    HBN_SW_RST
+#define HBN_SW_RST_POS                (12U)
+#define HBN_SW_RST_LEN                (1U)
+#define HBN_SW_RST_MSK                (((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS)
+#define HBN_SW_RST_UMSK               (~(((1U << HBN_SW_RST_LEN) - 1) << HBN_SW_RST_POS))
+#define HBN_DIS_PWR_OFF_LDO11         HBN_DIS_PWR_OFF_LDO11
+#define HBN_DIS_PWR_OFF_LDO11_POS     (13U)
+#define HBN_DIS_PWR_OFF_LDO11_LEN     (1U)
+#define HBN_DIS_PWR_OFF_LDO11_MSK     (((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS)
+#define HBN_DIS_PWR_OFF_LDO11_UMSK    (~(((1U << HBN_DIS_PWR_OFF_LDO11_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_POS))
+#define HBN_DIS_PWR_OFF_LDO11_RT      HBN_DIS_PWR_OFF_LDO11_RT
+#define HBN_DIS_PWR_OFF_LDO11_RT_POS  (14U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_LEN  (1U)
+#define HBN_DIS_PWR_OFF_LDO11_RT_MSK  (((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS)
+#define HBN_DIS_PWR_OFF_LDO11_RT_UMSK (~(((1U << HBN_DIS_PWR_OFF_LDO11_RT_LEN) - 1) << HBN_DIS_PWR_OFF_LDO11_RT_POS))
+#define HBN_LDO11_RT_VOUT_SEL         HBN_LDO11_RT_VOUT_SEL
+#define HBN_LDO11_RT_VOUT_SEL_POS     (15U)
+#define HBN_LDO11_RT_VOUT_SEL_LEN     (4U)
+#define HBN_LDO11_RT_VOUT_SEL_MSK     (((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS)
+#define HBN_LDO11_RT_VOUT_SEL_UMSK    (~(((1U << HBN_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_LDO11_RT_VOUT_SEL_POS))
+#define HBN_LDO11_AON_VOUT_SEL        HBN_LDO11_AON_VOUT_SEL
+#define HBN_LDO11_AON_VOUT_SEL_POS    (19U)
+#define HBN_LDO11_AON_VOUT_SEL_LEN    (4U)
+#define HBN_LDO11_AON_VOUT_SEL_MSK    (((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS)
+#define HBN_LDO11_AON_VOUT_SEL_UMSK   (~(((1U << HBN_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_LDO11_AON_VOUT_SEL_POS))
+#define HBN_PU_DCDC18_AON             HBN_PU_DCDC18_AON
+#define HBN_PU_DCDC18_AON_POS         (23U)
+#define HBN_PU_DCDC18_AON_LEN         (1U)
+#define HBN_PU_DCDC18_AON_MSK         (((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS)
+#define HBN_PU_DCDC18_AON_UMSK        (~(((1U << HBN_PU_DCDC18_AON_LEN) - 1) << HBN_PU_DCDC18_AON_POS))
+#define HBN_RTC_DLY_OPTION            HBN_RTC_DLY_OPTION
+#define HBN_RTC_DLY_OPTION_POS        (24U)
+#define HBN_RTC_DLY_OPTION_LEN        (1U)
+#define HBN_RTC_DLY_OPTION_MSK        (((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS)
+#define HBN_RTC_DLY_OPTION_UMSK       (~(((1U << HBN_RTC_DLY_OPTION_LEN) - 1) << HBN_RTC_DLY_OPTION_POS))
+#define HBN_PWR_ON_OPTION             HBN_PWR_ON_OPTION
+#define HBN_PWR_ON_OPTION_POS         (25U)
+#define HBN_PWR_ON_OPTION_LEN         (1U)
+#define HBN_PWR_ON_OPTION_MSK         (((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS)
+#define HBN_PWR_ON_OPTION_UMSK        (~(((1U << HBN_PWR_ON_OPTION_LEN) - 1) << HBN_PWR_ON_OPTION_POS))
+#define HBN_SRAM_SLP_OPTION           HBN_SRAM_SLP_OPTION
+#define HBN_SRAM_SLP_OPTION_POS       (26U)
+#define HBN_SRAM_SLP_OPTION_LEN       (1U)
+#define HBN_SRAM_SLP_OPTION_MSK       (((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS)
+#define HBN_SRAM_SLP_OPTION_UMSK      (~(((1U << HBN_SRAM_SLP_OPTION_LEN) - 1) << HBN_SRAM_SLP_OPTION_POS))
+#define HBN_SRAM_SLP                  HBN_SRAM_SLP
+#define HBN_SRAM_SLP_POS              (27U)
+#define HBN_SRAM_SLP_LEN              (1U)
+#define HBN_SRAM_SLP_MSK              (((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS)
+#define HBN_SRAM_SLP_UMSK             (~(((1U << HBN_SRAM_SLP_LEN) - 1) << HBN_SRAM_SLP_POS))
+#define HBN_STATE                     HBN_STATE
+#define HBN_STATE_POS                 (28U)
+#define HBN_STATE_LEN                 (4U)
+#define HBN_STATE_MSK                 (((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS)
+#define HBN_STATE_UMSK                (~(((1U << HBN_STATE_LEN) - 1) << HBN_STATE_POS))
+
+/* 0x4 : HBN_TIME_L */
+#define HBN_TIME_L_OFFSET (0x4)
+#define HBN_TIME_L        HBN_TIME_L
+#define HBN_TIME_L_POS    (0U)
+#define HBN_TIME_L_LEN    (32U)
+#define HBN_TIME_L_MSK    (((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS)
+#define HBN_TIME_L_UMSK   (~(((1U << HBN_TIME_L_LEN) - 1) << HBN_TIME_L_POS))
+
+/* 0x8 : HBN_TIME_H */
+#define HBN_TIME_H_OFFSET (0x8)
+#define HBN_TIME_H        HBN_TIME_H
+#define HBN_TIME_H_POS    (0U)
+#define HBN_TIME_H_LEN    (8U)
+#define HBN_TIME_H_MSK    (((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS)
+#define HBN_TIME_H_UMSK   (~(((1U << HBN_TIME_H_LEN) - 1) << HBN_TIME_H_POS))
+
+/* 0xC : RTC_TIME_L */
+#define HBN_RTC_TIME_L_OFFSET     (0xC)
+#define HBN_RTC_TIME_LATCH_L      HBN_RTC_TIME_LATCH_L
+#define HBN_RTC_TIME_LATCH_L_POS  (0U)
+#define HBN_RTC_TIME_LATCH_L_LEN  (32U)
+#define HBN_RTC_TIME_LATCH_L_MSK  (((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS)
+#define HBN_RTC_TIME_LATCH_L_UMSK (~(((1U << HBN_RTC_TIME_LATCH_L_LEN) - 1) << HBN_RTC_TIME_LATCH_L_POS))
+
+/* 0x10 : RTC_TIME_H */
+#define HBN_RTC_TIME_H_OFFSET     (0x10)
+#define HBN_RTC_TIME_LATCH_H      HBN_RTC_TIME_LATCH_H
+#define HBN_RTC_TIME_LATCH_H_POS  (0U)
+#define HBN_RTC_TIME_LATCH_H_LEN  (8U)
+#define HBN_RTC_TIME_LATCH_H_MSK  (((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS)
+#define HBN_RTC_TIME_LATCH_H_UMSK (~(((1U << HBN_RTC_TIME_LATCH_H_LEN) - 1) << HBN_RTC_TIME_LATCH_H_POS))
+#define HBN_RTC_TIME_LATCH        HBN_RTC_TIME_LATCH
+#define HBN_RTC_TIME_LATCH_POS    (31U)
+#define HBN_RTC_TIME_LATCH_LEN    (1U)
+#define HBN_RTC_TIME_LATCH_MSK    (((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS)
+#define HBN_RTC_TIME_LATCH_UMSK   (~(((1U << HBN_RTC_TIME_LATCH_LEN) - 1) << HBN_RTC_TIME_LATCH_POS))
+
+/* 0x14 : HBN_IRQ_MODE */
+#define HBN_IRQ_MODE_OFFSET         (0x14)
+#define HBN_PIN_WAKEUP_MODE         HBN_PIN_WAKEUP_MODE
+#define HBN_PIN_WAKEUP_MODE_POS     (0U)
+#define HBN_PIN_WAKEUP_MODE_LEN     (3U)
+#define HBN_PIN_WAKEUP_MODE_MSK     (((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS)
+#define HBN_PIN_WAKEUP_MODE_UMSK    (~(((1U << HBN_PIN_WAKEUP_MODE_LEN) - 1) << HBN_PIN_WAKEUP_MODE_POS))
+#define HBN_PIN_WAKEUP_MASK         HBN_PIN_WAKEUP_MASK
+#define HBN_PIN_WAKEUP_MASK_POS     (3U)
+#define HBN_PIN_WAKEUP_MASK_LEN     (5U)
+#define HBN_PIN_WAKEUP_MASK_MSK     (((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS)
+#define HBN_PIN_WAKEUP_MASK_UMSK    (~(((1U << HBN_PIN_WAKEUP_MASK_LEN) - 1) << HBN_PIN_WAKEUP_MASK_POS))
+#define HBN_REG_AON_PAD_IE_SMT      HBN_REG_AON_PAD_IE_SMT
+#define HBN_REG_AON_PAD_IE_SMT_POS  (8U)
+#define HBN_REG_AON_PAD_IE_SMT_LEN  (5U)
+#define HBN_REG_AON_PAD_IE_SMT_MSK  (((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS)
+#define HBN_REG_AON_PAD_IE_SMT_UMSK (~(((1U << HBN_REG_AON_PAD_IE_SMT_LEN) - 1) << HBN_REG_AON_PAD_IE_SMT_POS))
+#define HBN_REG_EN_HW_PU_PD         HBN_REG_EN_HW_PU_PD
+#define HBN_REG_EN_HW_PU_PD_POS     (16U)
+#define HBN_REG_EN_HW_PU_PD_LEN     (1U)
+#define HBN_REG_EN_HW_PU_PD_MSK     (((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS)
+#define HBN_REG_EN_HW_PU_PD_UMSK    (~(((1U << HBN_REG_EN_HW_PU_PD_LEN) - 1) << HBN_REG_EN_HW_PU_PD_POS))
+#define HBN_IRQ_BOR_EN              HBN_IRQ_BOR_EN
+#define HBN_IRQ_BOR_EN_POS          (18U)
+#define HBN_IRQ_BOR_EN_LEN          (1U)
+#define HBN_IRQ_BOR_EN_MSK          (((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS)
+#define HBN_IRQ_BOR_EN_UMSK         (~(((1U << HBN_IRQ_BOR_EN_LEN) - 1) << HBN_IRQ_BOR_EN_POS))
+#define HBN_IRQ_ACOMP0_EN           HBN_IRQ_ACOMP0_EN
+#define HBN_IRQ_ACOMP0_EN_POS       (20U)
+#define HBN_IRQ_ACOMP0_EN_LEN       (2U)
+#define HBN_IRQ_ACOMP0_EN_MSK       (((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS)
+#define HBN_IRQ_ACOMP0_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP0_EN_LEN) - 1) << HBN_IRQ_ACOMP0_EN_POS))
+#define HBN_IRQ_ACOMP1_EN           HBN_IRQ_ACOMP1_EN
+#define HBN_IRQ_ACOMP1_EN_POS       (22U)
+#define HBN_IRQ_ACOMP1_EN_LEN       (2U)
+#define HBN_IRQ_ACOMP1_EN_MSK       (((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS)
+#define HBN_IRQ_ACOMP1_EN_UMSK      (~(((1U << HBN_IRQ_ACOMP1_EN_LEN) - 1) << HBN_IRQ_ACOMP1_EN_POS))
+#define HBN_PIN_WAKEUP_SEL          HBN_PIN_WAKEUP_SEL
+#define HBN_PIN_WAKEUP_SEL_POS      (24U)
+#define HBN_PIN_WAKEUP_SEL_LEN      (3U)
+#define HBN_PIN_WAKEUP_SEL_MSK      (((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS)
+#define HBN_PIN_WAKEUP_SEL_UMSK     (~(((1U << HBN_PIN_WAKEUP_SEL_LEN) - 1) << HBN_PIN_WAKEUP_SEL_POS))
+#define HBN_PIN_WAKEUP_EN           HBN_PIN_WAKEUP_EN
+#define HBN_PIN_WAKEUP_EN_POS       (27U)
+#define HBN_PIN_WAKEUP_EN_LEN       (1U)
+#define HBN_PIN_WAKEUP_EN_MSK       (((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS)
+#define HBN_PIN_WAKEUP_EN_UMSK      (~(((1U << HBN_PIN_WAKEUP_EN_LEN) - 1) << HBN_PIN_WAKEUP_EN_POS))
+
+/* 0x18 : HBN_IRQ_STAT */
+#define HBN_IRQ_STAT_OFFSET (0x18)
+#define HBN_IRQ_STAT        HBN_IRQ_STAT
+#define HBN_IRQ_STAT_POS    (0U)
+#define HBN_IRQ_STAT_LEN    (32U)
+#define HBN_IRQ_STAT_MSK    (((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS)
+#define HBN_IRQ_STAT_UMSK   (~(((1U << HBN_IRQ_STAT_LEN) - 1) << HBN_IRQ_STAT_POS))
+
+/* 0x1C : HBN_IRQ_CLR */
+#define HBN_IRQ_CLR_OFFSET (0x1C)
+#define HBN_IRQ_CLR        HBN_IRQ_CLR
+#define HBN_IRQ_CLR_POS    (0U)
+#define HBN_IRQ_CLR_LEN    (32U)
+#define HBN_IRQ_CLR_MSK    (((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS)
+#define HBN_IRQ_CLR_UMSK   (~(((1U << HBN_IRQ_CLR_LEN) - 1) << HBN_IRQ_CLR_POS))
+
+/* 0x20 : HBN_PIR_CFG */
+#define HBN_PIR_CFG_OFFSET    (0x20)
+#define HBN_PIR_HPF_SEL       HBN_PIR_HPF_SEL
+#define HBN_PIR_HPF_SEL_POS   (0U)
+#define HBN_PIR_HPF_SEL_LEN   (2U)
+#define HBN_PIR_HPF_SEL_MSK   (((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS)
+#define HBN_PIR_HPF_SEL_UMSK  (~(((1U << HBN_PIR_HPF_SEL_LEN) - 1) << HBN_PIR_HPF_SEL_POS))
+#define HBN_PIR_LPF_SEL       HBN_PIR_LPF_SEL
+#define HBN_PIR_LPF_SEL_POS   (2U)
+#define HBN_PIR_LPF_SEL_LEN   (1U)
+#define HBN_PIR_LPF_SEL_MSK   (((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS)
+#define HBN_PIR_LPF_SEL_UMSK  (~(((1U << HBN_PIR_LPF_SEL_LEN) - 1) << HBN_PIR_LPF_SEL_POS))
+#define HBN_PIR_DIS           HBN_PIR_DIS
+#define HBN_PIR_DIS_POS       (4U)
+#define HBN_PIR_DIS_LEN       (2U)
+#define HBN_PIR_DIS_MSK       (((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS)
+#define HBN_PIR_DIS_UMSK      (~(((1U << HBN_PIR_DIS_LEN) - 1) << HBN_PIR_DIS_POS))
+#define HBN_PIR_EN            HBN_PIR_EN
+#define HBN_PIR_EN_POS        (7U)
+#define HBN_PIR_EN_LEN        (1U)
+#define HBN_PIR_EN_MSK        (((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS)
+#define HBN_PIR_EN_UMSK       (~(((1U << HBN_PIR_EN_LEN) - 1) << HBN_PIR_EN_POS))
+#define HBN_GPADC_CGEN        HBN_GPADC_CGEN
+#define HBN_GPADC_CGEN_POS    (8U)
+#define HBN_GPADC_CGEN_LEN    (1U)
+#define HBN_GPADC_CGEN_MSK    (((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS)
+#define HBN_GPADC_CGEN_UMSK   (~(((1U << HBN_GPADC_CGEN_LEN) - 1) << HBN_GPADC_CGEN_POS))
+#define HBN_GPADC_NOSYNC      HBN_GPADC_NOSYNC
+#define HBN_GPADC_NOSYNC_POS  (9U)
+#define HBN_GPADC_NOSYNC_LEN  (1U)
+#define HBN_GPADC_NOSYNC_MSK  (((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS)
+#define HBN_GPADC_NOSYNC_UMSK (~(((1U << HBN_GPADC_NOSYNC_LEN) - 1) << HBN_GPADC_NOSYNC_POS))
+
+/* 0x24 : HBN_PIR_VTH */
+#define HBN_PIR_VTH_OFFSET (0x24)
+#define HBN_PIR_VTH        HBN_PIR_VTH
+#define HBN_PIR_VTH_POS    (0U)
+#define HBN_PIR_VTH_LEN    (14U)
+#define HBN_PIR_VTH_MSK    (((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS)
+#define HBN_PIR_VTH_UMSK   (~(((1U << HBN_PIR_VTH_LEN) - 1) << HBN_PIR_VTH_POS))
+
+/* 0x28 : HBN_PIR_INTERVAL */
+#define HBN_PIR_INTERVAL_OFFSET (0x28)
+#define HBN_PIR_INTERVAL        HBN_PIR_INTERVAL
+#define HBN_PIR_INTERVAL_POS    (0U)
+#define HBN_PIR_INTERVAL_LEN    (12U)
+#define HBN_PIR_INTERVAL_MSK    (((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS)
+#define HBN_PIR_INTERVAL_UMSK   (~(((1U << HBN_PIR_INTERVAL_LEN) - 1) << HBN_PIR_INTERVAL_POS))
+
+/* 0x2C : HBN_MISC */
+#define HBN_MISC_OFFSET             (0x2C)
+#define HBN_BOR_SEL                 HBN_BOR_SEL
+#define HBN_BOR_SEL_POS             (0U)
+#define HBN_BOR_SEL_LEN             (1U)
+#define HBN_BOR_SEL_MSK             (((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS)
+#define HBN_BOR_SEL_UMSK            (~(((1U << HBN_BOR_SEL_LEN) - 1) << HBN_BOR_SEL_POS))
+#define HBN_BOR_VTH                 HBN_BOR_VTH
+#define HBN_BOR_VTH_POS             (1U)
+#define HBN_BOR_VTH_LEN             (1U)
+#define HBN_BOR_VTH_MSK             (((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS)
+#define HBN_BOR_VTH_UMSK            (~(((1U << HBN_BOR_VTH_LEN) - 1) << HBN_BOR_VTH_POS))
+#define HBN_PU_BOR                  HBN_PU_BOR
+#define HBN_PU_BOR_POS              (2U)
+#define HBN_PU_BOR_LEN              (1U)
+#define HBN_PU_BOR_MSK              (((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS)
+#define HBN_PU_BOR_UMSK             (~(((1U << HBN_PU_BOR_LEN) - 1) << HBN_PU_BOR_POS))
+#define HBN_R_BOR_OUT               HBN_R_BOR_OUT
+#define HBN_R_BOR_OUT_POS           (3U)
+#define HBN_R_BOR_OUT_LEN           (1U)
+#define HBN_R_BOR_OUT_MSK           (((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS)
+#define HBN_R_BOR_OUT_UMSK          (~(((1U << HBN_R_BOR_OUT_LEN) - 1) << HBN_R_BOR_OUT_POS))
+#define HBN_FLASH_PULLUP_AON        HBN_FLASH_PULLUP_AON
+#define HBN_FLASH_PULLUP_AON_POS    (16U)
+#define HBN_FLASH_PULLUP_AON_LEN    (6U)
+#define HBN_FLASH_PULLUP_AON_MSK    (((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS)
+#define HBN_FLASH_PULLUP_AON_UMSK   (~(((1U << HBN_FLASH_PULLUP_AON_LEN) - 1) << HBN_FLASH_PULLUP_AON_POS))
+#define HBN_FLASH_PULLDOWN_AON      HBN_FLASH_PULLDOWN_AON
+#define HBN_FLASH_PULLDOWN_AON_POS  (24U)
+#define HBN_FLASH_PULLDOWN_AON_LEN  (6U)
+#define HBN_FLASH_PULLDOWN_AON_MSK  (((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS)
+#define HBN_FLASH_PULLDOWN_AON_UMSK (~(((1U << HBN_FLASH_PULLDOWN_AON_LEN) - 1) << HBN_FLASH_PULLDOWN_AON_POS))
+
+/* 0x30 : HBN_GLB */
+#define HBN_GLB_OFFSET                    (0x30)
+#define HBN_ROOT_CLK_SEL                  HBN_ROOT_CLK_SEL
+#define HBN_ROOT_CLK_SEL_POS              (0U)
+#define HBN_ROOT_CLK_SEL_LEN              (2U)
+#define HBN_ROOT_CLK_SEL_MSK              (((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS)
+#define HBN_ROOT_CLK_SEL_UMSK             (~(((1U << HBN_ROOT_CLK_SEL_LEN) - 1) << HBN_ROOT_CLK_SEL_POS))
+#define HBN_UART_CLK_SEL                  HBN_UART_CLK_SEL
+#define HBN_UART_CLK_SEL_POS              (2U)
+#define HBN_UART_CLK_SEL_LEN              (1U)
+#define HBN_UART_CLK_SEL_MSK              (((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS)
+#define HBN_UART_CLK_SEL_UMSK             (~(((1U << HBN_UART_CLK_SEL_LEN) - 1) << HBN_UART_CLK_SEL_POS))
+#define HBN_F32K_SEL                      HBN_F32K_SEL
+#define HBN_F32K_SEL_POS                  (3U)
+#define HBN_F32K_SEL_LEN                  (2U)
+#define HBN_F32K_SEL_MSK                  (((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS)
+#define HBN_F32K_SEL_UMSK                 (~(((1U << HBN_F32K_SEL_LEN) - 1) << HBN_F32K_SEL_POS))
+#define HBN_PU_RC32K                      HBN_PU_RC32K
+#define HBN_PU_RC32K_POS                  (5U)
+#define HBN_PU_RC32K_LEN                  (1U)
+#define HBN_PU_RC32K_MSK                  (((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS)
+#define HBN_PU_RC32K_UMSK                 (~(((1U << HBN_PU_RC32K_LEN) - 1) << HBN_PU_RC32K_POS))
+#define HBN_LDO11_RT_ILOAD_SEL            HBN_LDO11_RT_ILOAD_SEL
+#define HBN_LDO11_RT_ILOAD_SEL_POS        (6U)
+#define HBN_LDO11_RT_ILOAD_SEL_LEN        (2U)
+#define HBN_LDO11_RT_ILOAD_SEL_MSK        (((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS)
+#define HBN_LDO11_RT_ILOAD_SEL_UMSK       (~(((1U << HBN_LDO11_RT_ILOAD_SEL_LEN) - 1) << HBN_LDO11_RT_ILOAD_SEL_POS))
+#define HBN_RESET_EVENT                   HBN_RESET_EVENT
+#define HBN_RESET_EVENT_POS               (8U)
+#define HBN_RESET_EVENT_LEN               (5U)
+#define HBN_RESET_EVENT_MSK               (((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS)
+#define HBN_RESET_EVENT_UMSK              (~(((1U << HBN_RESET_EVENT_LEN) - 1) << HBN_RESET_EVENT_POS))
+#define HBN_CLEAR_RESET_EVENT             HBN_CLEAR_RESET_EVENT
+#define HBN_CLEAR_RESET_EVENT_POS         (13U)
+#define HBN_CLEAR_RESET_EVENT_LEN         (1U)
+#define HBN_CLEAR_RESET_EVENT_MSK         (((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS)
+#define HBN_CLEAR_RESET_EVENT_UMSK        (~(((1U << HBN_CLEAR_RESET_EVENT_LEN) - 1) << HBN_CLEAR_RESET_EVENT_POS))
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON      HBN_SW_LDO11SOC_VOUT_SEL_AON
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_POS  (16U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN  (4U)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_MSK  (((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS)
+#define HBN_SW_LDO11SOC_VOUT_SEL_AON_UMSK (~(((1U << HBN_SW_LDO11SOC_VOUT_SEL_AON_LEN) - 1) << HBN_SW_LDO11SOC_VOUT_SEL_AON_POS))
+#define HBN_SW_LDO11_RT_VOUT_SEL          HBN_SW_LDO11_RT_VOUT_SEL
+#define HBN_SW_LDO11_RT_VOUT_SEL_POS      (24U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_LEN      (4U)
+#define HBN_SW_LDO11_RT_VOUT_SEL_MSK      (((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS)
+#define HBN_SW_LDO11_RT_VOUT_SEL_UMSK     (~(((1U << HBN_SW_LDO11_RT_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_RT_VOUT_SEL_POS))
+#define HBN_SW_LDO11_AON_VOUT_SEL         HBN_SW_LDO11_AON_VOUT_SEL
+#define HBN_SW_LDO11_AON_VOUT_SEL_POS     (28U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_LEN     (4U)
+#define HBN_SW_LDO11_AON_VOUT_SEL_MSK     (((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS)
+#define HBN_SW_LDO11_AON_VOUT_SEL_UMSK    (~(((1U << HBN_SW_LDO11_AON_VOUT_SEL_LEN) - 1) << HBN_SW_LDO11_AON_VOUT_SEL_POS))
+
+/* 0x34 : HBN_SRAM */
+#define HBN_SRAM_OFFSET      (0x34)
+#define HBN_RETRAM_EMA       HBN_RETRAM_EMA
+#define HBN_RETRAM_EMA_POS   (0U)
+#define HBN_RETRAM_EMA_LEN   (3U)
+#define HBN_RETRAM_EMA_MSK   (((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS)
+#define HBN_RETRAM_EMA_UMSK  (~(((1U << HBN_RETRAM_EMA_LEN) - 1) << HBN_RETRAM_EMA_POS))
+#define HBN_RETRAM_EMAW      HBN_RETRAM_EMAW
+#define HBN_RETRAM_EMAW_POS  (3U)
+#define HBN_RETRAM_EMAW_LEN  (2U)
+#define HBN_RETRAM_EMAW_MSK  (((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS)
+#define HBN_RETRAM_EMAW_UMSK (~(((1U << HBN_RETRAM_EMAW_LEN) - 1) << HBN_RETRAM_EMAW_POS))
+#define HBN_RETRAM_RET       HBN_RETRAM_RET
+#define HBN_RETRAM_RET_POS   (6U)
+#define HBN_RETRAM_RET_LEN   (1U)
+#define HBN_RETRAM_RET_MSK   (((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS)
+#define HBN_RETRAM_RET_UMSK  (~(((1U << HBN_RETRAM_RET_LEN) - 1) << HBN_RETRAM_RET_POS))
+#define HBN_RETRAM_SLP       HBN_RETRAM_SLP
+#define HBN_RETRAM_SLP_POS   (7U)
+#define HBN_RETRAM_SLP_LEN   (1U)
+#define HBN_RETRAM_SLP_MSK   (((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS)
+#define HBN_RETRAM_SLP_UMSK  (~(((1U << HBN_RETRAM_SLP_LEN) - 1) << HBN_RETRAM_SLP_POS))
+
+/* 0x100 : HBN_RSV0 */
+#define HBN_RSV0_OFFSET (0x100)
+#define HBN_RSV0        HBN_RSV0
+#define HBN_RSV0_POS    (0U)
+#define HBN_RSV0_LEN    (32U)
+#define HBN_RSV0_MSK    (((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS)
+#define HBN_RSV0_UMSK   (~(((1U << HBN_RSV0_LEN) - 1) << HBN_RSV0_POS))
+
+/* 0x104 : HBN_RSV1 */
+#define HBN_RSV1_OFFSET (0x104)
+#define HBN_RSV1        HBN_RSV1
+#define HBN_RSV1_POS    (0U)
+#define HBN_RSV1_LEN    (32U)
+#define HBN_RSV1_MSK    (((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS)
+#define HBN_RSV1_UMSK   (~(((1U << HBN_RSV1_LEN) - 1) << HBN_RSV1_POS))
+
+/* 0x108 : HBN_RSV2 */
+#define HBN_RSV2_OFFSET (0x108)
+#define HBN_RSV2        HBN_RSV2
+#define HBN_RSV2_POS    (0U)
+#define HBN_RSV2_LEN    (32U)
+#define HBN_RSV2_MSK    (((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS)
+#define HBN_RSV2_UMSK   (~(((1U << HBN_RSV2_LEN) - 1) << HBN_RSV2_POS))
+
+/* 0x10C : HBN_RSV3 */
+#define HBN_RSV3_OFFSET (0x10C)
+#define HBN_RSV3        HBN_RSV3
+#define HBN_RSV3_POS    (0U)
+#define HBN_RSV3_LEN    (32U)
+#define HBN_RSV3_MSK    (((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS)
+#define HBN_RSV3_UMSK   (~(((1U << HBN_RSV3_LEN) - 1) << HBN_RSV3_POS))
+
+/* 0x200 : rc32k_ctrl0 */
+#define HBN_RC32K_CTRL0_OFFSET         (0x200)
+#define HBN_RC32K_CAL_DONE             HBN_RC32K_CAL_DONE
+#define HBN_RC32K_CAL_DONE_POS         (0U)
+#define HBN_RC32K_CAL_DONE_LEN         (1U)
+#define HBN_RC32K_CAL_DONE_MSK         (((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS)
+#define HBN_RC32K_CAL_DONE_UMSK        (~(((1U << HBN_RC32K_CAL_DONE_LEN) - 1) << HBN_RC32K_CAL_DONE_POS))
+#define HBN_RC32K_RDY                  HBN_RC32K_RDY
+#define HBN_RC32K_RDY_POS              (1U)
+#define HBN_RC32K_RDY_LEN              (1U)
+#define HBN_RC32K_RDY_MSK              (((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS)
+#define HBN_RC32K_RDY_UMSK             (~(((1U << HBN_RC32K_RDY_LEN) - 1) << HBN_RC32K_RDY_POS))
+#define HBN_RC32K_CAL_INPROGRESS       HBN_RC32K_CAL_INPROGRESS
+#define HBN_RC32K_CAL_INPROGRESS_POS   (2U)
+#define HBN_RC32K_CAL_INPROGRESS_LEN   (1U)
+#define HBN_RC32K_CAL_INPROGRESS_MSK   (((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS)
+#define HBN_RC32K_CAL_INPROGRESS_UMSK  (~(((1U << HBN_RC32K_CAL_INPROGRESS_LEN) - 1) << HBN_RC32K_CAL_INPROGRESS_POS))
+#define HBN_RC32K_CAL_DIV              HBN_RC32K_CAL_DIV
+#define HBN_RC32K_CAL_DIV_POS          (3U)
+#define HBN_RC32K_CAL_DIV_LEN          (2U)
+#define HBN_RC32K_CAL_DIV_MSK          (((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS)
+#define HBN_RC32K_CAL_DIV_UMSK         (~(((1U << HBN_RC32K_CAL_DIV_LEN) - 1) << HBN_RC32K_CAL_DIV_POS))
+#define HBN_RC32K_CAL_PRECHARGE        HBN_RC32K_CAL_PRECHARGE
+#define HBN_RC32K_CAL_PRECHARGE_POS    (5U)
+#define HBN_RC32K_CAL_PRECHARGE_LEN    (1U)
+#define HBN_RC32K_CAL_PRECHARGE_MSK    (((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS)
+#define HBN_RC32K_CAL_PRECHARGE_UMSK   (~(((1U << HBN_RC32K_CAL_PRECHARGE_LEN) - 1) << HBN_RC32K_CAL_PRECHARGE_POS))
+#define HBN_RC32K_DIG_CODE_FR_CAL      HBN_RC32K_DIG_CODE_FR_CAL
+#define HBN_RC32K_DIG_CODE_FR_CAL_POS  (6U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_LEN  (10U)
+#define HBN_RC32K_DIG_CODE_FR_CAL_MSK  (((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS)
+#define HBN_RC32K_DIG_CODE_FR_CAL_UMSK (~(((1U << HBN_RC32K_DIG_CODE_FR_CAL_LEN) - 1) << HBN_RC32K_DIG_CODE_FR_CAL_POS))
+#define HBN_RC32K_VREF_DLY             HBN_RC32K_VREF_DLY
+#define HBN_RC32K_VREF_DLY_POS         (16U)
+#define HBN_RC32K_VREF_DLY_LEN         (2U)
+#define HBN_RC32K_VREF_DLY_MSK         (((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS)
+#define HBN_RC32K_VREF_DLY_UMSK        (~(((1U << HBN_RC32K_VREF_DLY_LEN) - 1) << HBN_RC32K_VREF_DLY_POS))
+#define HBN_RC32K_ALLOW_CAL            HBN_RC32K_ALLOW_CAL
+#define HBN_RC32K_ALLOW_CAL_POS        (18U)
+#define HBN_RC32K_ALLOW_CAL_LEN        (1U)
+#define HBN_RC32K_ALLOW_CAL_MSK        (((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS)
+#define HBN_RC32K_ALLOW_CAL_UMSK       (~(((1U << HBN_RC32K_ALLOW_CAL_LEN) - 1) << HBN_RC32K_ALLOW_CAL_POS))
+#define HBN_RC32K_EXT_CODE_EN          HBN_RC32K_EXT_CODE_EN
+#define HBN_RC32K_EXT_CODE_EN_POS      (19U)
+#define HBN_RC32K_EXT_CODE_EN_LEN      (1U)
+#define HBN_RC32K_EXT_CODE_EN_MSK      (((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS)
+#define HBN_RC32K_EXT_CODE_EN_UMSK     (~(((1U << HBN_RC32K_EXT_CODE_EN_LEN) - 1) << HBN_RC32K_EXT_CODE_EN_POS))
+#define HBN_RC32K_CAL_EN               HBN_RC32K_CAL_EN
+#define HBN_RC32K_CAL_EN_POS           (20U)
+#define HBN_RC32K_CAL_EN_LEN           (1U)
+#define HBN_RC32K_CAL_EN_MSK           (((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS)
+#define HBN_RC32K_CAL_EN_UMSK          (~(((1U << HBN_RC32K_CAL_EN_LEN) - 1) << HBN_RC32K_CAL_EN_POS))
+#define HBN_RC32K_CODE_FR_EXT          HBN_RC32K_CODE_FR_EXT
+#define HBN_RC32K_CODE_FR_EXT_POS      (22U)
+#define HBN_RC32K_CODE_FR_EXT_LEN      (10U)
+#define HBN_RC32K_CODE_FR_EXT_MSK      (((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS)
+#define HBN_RC32K_CODE_FR_EXT_UMSK     (~(((1U << HBN_RC32K_CODE_FR_EXT_LEN) - 1) << HBN_RC32K_CODE_FR_EXT_POS))
+
+/* 0x204 : xtal32k */
+#define HBN_XTAL32K_OFFSET            (0x204)
+#define HBN_XTAL32K_HIZ_EN            HBN_XTAL32K_HIZ_EN
+#define HBN_XTAL32K_HIZ_EN_POS        (0U)
+#define HBN_XTAL32K_HIZ_EN_LEN        (1U)
+#define HBN_XTAL32K_HIZ_EN_MSK        (((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS)
+#define HBN_XTAL32K_HIZ_EN_UMSK       (~(((1U << HBN_XTAL32K_HIZ_EN_LEN) - 1) << HBN_XTAL32K_HIZ_EN_POS))
+#define HBN_XTAL32K_LOWV_EN           HBN_XTAL32K_LOWV_EN
+#define HBN_XTAL32K_LOWV_EN_POS       (1U)
+#define HBN_XTAL32K_LOWV_EN_LEN       (1U)
+#define HBN_XTAL32K_LOWV_EN_MSK       (((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS)
+#define HBN_XTAL32K_LOWV_EN_UMSK      (~(((1U << HBN_XTAL32K_LOWV_EN_LEN) - 1) << HBN_XTAL32K_LOWV_EN_POS))
+#define HBN_XTAL32K_EXT_SEL           HBN_XTAL32K_EXT_SEL
+#define HBN_XTAL32K_EXT_SEL_POS       (2U)
+#define HBN_XTAL32K_EXT_SEL_LEN       (1U)
+#define HBN_XTAL32K_EXT_SEL_MSK       (((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS)
+#define HBN_XTAL32K_EXT_SEL_UMSK      (~(((1U << HBN_XTAL32K_EXT_SEL_LEN) - 1) << HBN_XTAL32K_EXT_SEL_POS))
+#define HBN_XTAL32K_AMP_CTRL          HBN_XTAL32K_AMP_CTRL
+#define HBN_XTAL32K_AMP_CTRL_POS      (3U)
+#define HBN_XTAL32K_AMP_CTRL_LEN      (2U)
+#define HBN_XTAL32K_AMP_CTRL_MSK      (((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS)
+#define HBN_XTAL32K_AMP_CTRL_UMSK     (~(((1U << HBN_XTAL32K_AMP_CTRL_LEN) - 1) << HBN_XTAL32K_AMP_CTRL_POS))
+#define HBN_XTAL32K_REG               HBN_XTAL32K_REG
+#define HBN_XTAL32K_REG_POS           (5U)
+#define HBN_XTAL32K_REG_LEN           (2U)
+#define HBN_XTAL32K_REG_MSK           (((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS)
+#define HBN_XTAL32K_REG_UMSK          (~(((1U << HBN_XTAL32K_REG_LEN) - 1) << HBN_XTAL32K_REG_POS))
+#define HBN_XTAL32K_OUTBUF_STRE       HBN_XTAL32K_OUTBUF_STRE
+#define HBN_XTAL32K_OUTBUF_STRE_POS   (7U)
+#define HBN_XTAL32K_OUTBUF_STRE_LEN   (1U)
+#define HBN_XTAL32K_OUTBUF_STRE_MSK   (((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS)
+#define HBN_XTAL32K_OUTBUF_STRE_UMSK  (~(((1U << HBN_XTAL32K_OUTBUF_STRE_LEN) - 1) << HBN_XTAL32K_OUTBUF_STRE_POS))
+#define HBN_XTAL32K_OTF_SHORT         HBN_XTAL32K_OTF_SHORT
+#define HBN_XTAL32K_OTF_SHORT_POS     (8U)
+#define HBN_XTAL32K_OTF_SHORT_LEN     (1U)
+#define HBN_XTAL32K_OTF_SHORT_MSK     (((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS)
+#define HBN_XTAL32K_OTF_SHORT_UMSK    (~(((1U << HBN_XTAL32K_OTF_SHORT_LEN) - 1) << HBN_XTAL32K_OTF_SHORT_POS))
+#define HBN_XTAL32K_INV_STRE          HBN_XTAL32K_INV_STRE
+#define HBN_XTAL32K_INV_STRE_POS      (9U)
+#define HBN_XTAL32K_INV_STRE_LEN      (2U)
+#define HBN_XTAL32K_INV_STRE_MSK      (((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS)
+#define HBN_XTAL32K_INV_STRE_UMSK     (~(((1U << HBN_XTAL32K_INV_STRE_LEN) - 1) << HBN_XTAL32K_INV_STRE_POS))
+#define HBN_XTAL32K_CAPBANK           HBN_XTAL32K_CAPBANK
+#define HBN_XTAL32K_CAPBANK_POS       (11U)
+#define HBN_XTAL32K_CAPBANK_LEN       (6U)
+#define HBN_XTAL32K_CAPBANK_MSK       (((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS)
+#define HBN_XTAL32K_CAPBANK_UMSK      (~(((1U << HBN_XTAL32K_CAPBANK_LEN) - 1) << HBN_XTAL32K_CAPBANK_POS))
+#define HBN_XTAL32K_AC_CAP_SHORT      HBN_XTAL32K_AC_CAP_SHORT
+#define HBN_XTAL32K_AC_CAP_SHORT_POS  (17U)
+#define HBN_XTAL32K_AC_CAP_SHORT_LEN  (1U)
+#define HBN_XTAL32K_AC_CAP_SHORT_MSK  (((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS)
+#define HBN_XTAL32K_AC_CAP_SHORT_UMSK (~(((1U << HBN_XTAL32K_AC_CAP_SHORT_LEN) - 1) << HBN_XTAL32K_AC_CAP_SHORT_POS))
+#define HBN_PU_XTAL32K_BUF            HBN_PU_XTAL32K_BUF
+#define HBN_PU_XTAL32K_BUF_POS        (18U)
+#define HBN_PU_XTAL32K_BUF_LEN        (1U)
+#define HBN_PU_XTAL32K_BUF_MSK        (((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS)
+#define HBN_PU_XTAL32K_BUF_UMSK       (~(((1U << HBN_PU_XTAL32K_BUF_LEN) - 1) << HBN_PU_XTAL32K_BUF_POS))
+#define HBN_PU_XTAL32K                HBN_PU_XTAL32K
+#define HBN_PU_XTAL32K_POS            (19U)
+#define HBN_PU_XTAL32K_LEN            (1U)
+#define HBN_PU_XTAL32K_MSK            (((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS)
+#define HBN_PU_XTAL32K_UMSK           (~(((1U << HBN_PU_XTAL32K_LEN) - 1) << HBN_PU_XTAL32K_POS))
+
+struct hbn_reg {
+    /* 0x0 : HBN_CTL */
+    union {
+        struct
+        {
+            uint32_t rtc_ctl                  : 7; /* [ 6: 0],        r/w,        0x0 */
+            uint32_t hbn_mode                 : 1; /* [    7],          w,        0x0 */
+            uint32_t trap_mode                : 1; /* [    8],          r,        0x0 */
+            uint32_t pwrdn_hbn_core           : 1; /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10              : 1; /* [   10],       rsvd,        0x0 */
+            uint32_t pwrdn_hbn_rtc            : 1; /* [   11],        r/w,        0x0 */
+            uint32_t sw_rst                   : 1; /* [   12],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t hbn_dis_pwr_off_ldo11_rt : 1; /* [   14],        r/w,        0x0 */
+            uint32_t hbn_ldo11_rt_vout_sel    : 4; /* [18:15],        r/w,        0xa */
+            uint32_t hbn_ldo11_aon_vout_sel   : 4; /* [22:19],        r/w,        0xa */
+            uint32_t pu_dcdc18_aon            : 1; /* [   23],        r/w,        0x1 */
+            uint32_t rtc_dly_option           : 1; /* [   24],        r/w,        0x0 */
+            uint32_t pwr_on_option            : 1; /* [   25],        r/w,        0x0 */
+            uint32_t sram_slp_option          : 1; /* [   26],        r/w,        0x0 */
+            uint32_t sram_slp                 : 1; /* [   27],          r,        0x0 */
+            uint32_t hbn_state                : 4; /* [31:28],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_CTL;
+
+    /* 0x4 : HBN_TIME_L */
+    union {
+        struct
+        {
+            uint32_t hbn_time_l : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_L;
+
+    /* 0x8 : HBN_TIME_H */
+    union {
+        struct
+        {
+            uint32_t hbn_time_h    : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_TIME_H;
+
+    /* 0xC : RTC_TIME_L */
+    union {
+        struct
+        {
+            uint32_t rtc_time_latch_l : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_L;
+
+    /* 0x10 : RTC_TIME_H */
+    union {
+        struct
+        {
+            uint32_t rtc_time_latch_h : 8;  /* [ 7: 0],          r,        0x0 */
+            uint32_t reserved_8_30    : 23; /* [30: 8],       rsvd,        0x0 */
+            uint32_t rtc_time_latch   : 1;  /* [   31],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } RTC_TIME_H;
+
+    /* 0x14 : HBN_IRQ_MODE */
+    union {
+        struct
+        {
+            uint32_t hbn_pin_wakeup_mode : 3; /* [ 2: 0],        r/w,        0x5 */
+            uint32_t hbn_pin_wakeup_mask : 5; /* [ 7: 3],        r/w,        0x0 */
+            uint32_t reg_aon_pad_ie_smt  : 5; /* [12: 8],        r/w,       0x1f */
+            uint32_t reserved_13_15      : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t reg_en_hw_pu_pd     : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reserved_17         : 1; /* [   17],       rsvd,        0x0 */
+            uint32_t irq_bor_en          : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19         : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t irq_acomp0_en       : 2; /* [21:20],        r/w,        0x0 */
+            uint32_t irq_acomp1_en       : 2; /* [23:22],        r/w,        0x0 */
+            uint32_t pin_wakeup_sel      : 3; /* [26:24],        r/w,        0x3 */
+            uint32_t pin_wakeup_en       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t reserved_28_31      : 4; /* [31:28],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_MODE;
+
+    /* 0x18 : HBN_IRQ_STAT */
+    union {
+        struct
+        {
+            uint32_t irq_stat : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_STAT;
+
+    /* 0x1C : HBN_IRQ_CLR */
+    union {
+        struct
+        {
+            uint32_t irq_clr : 32; /* [31: 0],          w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_IRQ_CLR;
+
+    /* 0x20 : HBN_PIR_CFG */
+    union {
+        struct
+        {
+            uint32_t pir_hpf_sel    : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t pir_lpf_sel    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3     : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t pir_dis        : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reserved_6     : 1;  /* [    6],       rsvd,        0x0 */
+            uint32_t pir_en         : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t gpadc_cgen     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t gpadc_nosync   : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31 : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_CFG;
+
+    /* 0x24 : HBN_PIR_VTH */
+    union {
+        struct
+        {
+            uint32_t pir_vth        : 14; /* [13: 0],        r/w,      0x3ff */
+            uint32_t reserved_14_31 : 18; /* [31:14],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_VTH;
+
+    /* 0x28 : HBN_PIR_INTERVAL */
+    union {
+        struct
+        {
+            uint32_t pir_interval   : 12; /* [11: 0],        r/w,      0xa3d */
+            uint32_t reserved_12_31 : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_PIR_INTERVAL;
+
+    /* 0x2C : HBN_MISC */
+    union {
+        struct
+        {
+            uint32_t bor_sel                : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t bor_vth                : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t pu_bor                 : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t r_bor_out              : 1;  /* [    3],          r,        0x0 */
+            uint32_t reserved_4_15          : 12; /* [15: 4],       rsvd,        0x0 */
+            uint32_t hbn_flash_pullup_aon   : 6;  /* [21:16],        r/w,        0x0 */
+            uint32_t reserved_22_23         : 2;  /* [23:22],       rsvd,        0x0 */
+            uint32_t hbn_flash_pulldown_aon : 6;  /* [29:24],        r/w,        0x0 */
+            uint32_t reserved_30_31         : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_MISC;
+
+    /* 0x30 : HBN_GLB */
+    union {
+        struct
+        {
+            uint32_t hbn_root_clk_sel         : 2; /* [ 1: 0],        r/w,        0x0 */
+            uint32_t hbn_uart_clk_sel         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t hbn_f32k_sel             : 2; /* [ 4: 3],        r/w,        0x0 */
+            uint32_t hbn_pu_rc32k             : 1; /* [    5],        r/w,        0x1 */
+            uint32_t ldo11_rt_iload_sel       : 2; /* [ 7: 6],        r/w,        0x1 */
+            uint32_t hbn_reset_event          : 5; /* [12: 8],          r,        0x0 */
+            uint32_t hbn_clear_reset_event    : 1; /* [   13],        r/w,        0x0 */
+            uint32_t reserved_14_15           : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t sw_ldo11soc_vout_sel_aon : 4; /* [19:16],        r/w,        0xa */
+            uint32_t reserved_20_23           : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t sw_ldo11_rt_vout_sel     : 4; /* [27:24],        r/w,        0xa */
+            uint32_t sw_ldo11_aon_vout_sel    : 4; /* [31:28],        r/w,        0xa */
+        } BF;
+        uint32_t WORD;
+    } HBN_GLB;
+
+    /* 0x34 : HBN_SRAM */
+    union {
+        struct
+        {
+            uint32_t retram_ema    : 3;  /* [ 2: 0],        r/w,        0x3 */
+            uint32_t retram_emaw   : 2;  /* [ 4: 3],        r/w,        0x1 */
+            uint32_t reserved_5    : 1;  /* [    5],       rsvd,        0x0 */
+            uint32_t retram_ret    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t retram_slp    : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t reserved_8_31 : 24; /* [31: 8],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_SRAM;
+
+    /* 0x38  reserved */
+    uint8_t RESERVED0x38[200];
+
+    /* 0x100 : HBN_RSV0 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV0;
+
+    /* 0x104 : HBN_RSV1 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV1 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV1;
+
+    /* 0x108 : HBN_RSV2 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV2;
+
+    /* 0x10C : HBN_RSV3 */
+    union {
+        struct
+        {
+            uint32_t HBN_RSV3 : 32; /* [31: 0],        r/w, 0xffffffffL */
+        } BF;
+        uint32_t WORD;
+    } HBN_RSV3;
+
+    /* 0x110  reserved */
+    uint8_t RESERVED0x110[240];
+
+    /* 0x200 : rc32k_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t rc32k_cal_done        : 1;  /* [    0],          r,        0x1 */
+            uint32_t rc32k_rdy             : 1;  /* [    1],          r,        0x1 */
+            uint32_t rc32k_cal_inprogress  : 1;  /* [    2],          r,        0x0 */
+            uint32_t rc32k_cal_div         : 2;  /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32k_cal_precharge   : 1;  /* [    5],          r,        0x0 */
+            uint32_t rc32k_dig_code_fr_cal : 10; /* [15: 6],          r,      0x200 */
+            uint32_t rc32k_vref_dly        : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t rc32k_allow_cal       : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t rc32k_ext_code_en     : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t rc32k_cal_en          : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21           : 1;  /* [   21],       rsvd,        0x0 */
+            uint32_t rc32k_code_fr_ext     : 10; /* [31:22],        r/w,      0x12c */
+        } BF;
+        uint32_t WORD;
+    } rc32k_ctrl0;
+
+    /* 0x204 : xtal32k */
+    union {
+        struct
+        {
+            uint32_t xtal32k_hiz_en       : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t xtal32k_lowv_en      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t xtal32k_ext_sel      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t xtal32k_amp_ctrl     : 2;  /* [ 4: 3],        r/w,        0x1 */
+            uint32_t xtal32k_reg          : 2;  /* [ 6: 5],        r/w,        0x1 */
+            uint32_t xtal32k_outbuf_stre  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t xtal32k_otf_short    : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t xtal32k_inv_stre     : 2;  /* [10: 9],        r/w,        0x1 */
+            uint32_t xtal32k_capbank      : 6;  /* [16:11],        r/w,       0x20 */
+            uint32_t xtal32k_ac_cap_short : 1;  /* [   17],        r/w,        0x1 */
+            uint32_t pu_xtal32k_buf       : 1;  /* [   18],        r/w,        0x1 */
+            uint32_t pu_xtal32k           : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } xtal32k;
+};
+
+typedef volatile struct hbn_reg hbn_reg_t;
+
+#endif /* __HBN_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/l1c_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/l1c_reg.h
new file mode 100755
index 0000000000..f9ae45eddb
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/l1c_reg.h
@@ -0,0 +1,366 @@
+/**
+  ******************************************************************************
+  * @file    l1c_reg.h
+  * @version V1.2
+  * @date    2020-07-08
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __L1C_REG_H__
+#define __L1C_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : l1c_config */
+#define L1C_CONFIG_OFFSET            (0x0)
+#define L1C_CACHEABLE                L1C_CACHEABLE
+#define L1C_CACHEABLE_POS            (0U)
+#define L1C_CACHEABLE_LEN            (1U)
+#define L1C_CACHEABLE_MSK            (((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS)
+#define L1C_CACHEABLE_UMSK           (~(((1U << L1C_CACHEABLE_LEN) - 1) << L1C_CACHEABLE_POS))
+#define L1C_CNT_EN                   L1C_CNT_EN
+#define L1C_CNT_EN_POS               (1U)
+#define L1C_CNT_EN_LEN               (1U)
+#define L1C_CNT_EN_MSK               (((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS)
+#define L1C_CNT_EN_UMSK              (~(((1U << L1C_CNT_EN_LEN) - 1) << L1C_CNT_EN_POS))
+#define L1C_INVALID_EN               L1C_INVALID_EN
+#define L1C_INVALID_EN_POS           (2U)
+#define L1C_INVALID_EN_LEN           (1U)
+#define L1C_INVALID_EN_MSK           (((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS)
+#define L1C_INVALID_EN_UMSK          (~(((1U << L1C_INVALID_EN_LEN) - 1) << L1C_INVALID_EN_POS))
+#define L1C_INVALID_DONE             L1C_INVALID_DONE
+#define L1C_INVALID_DONE_POS         (3U)
+#define L1C_INVALID_DONE_LEN         (1U)
+#define L1C_INVALID_DONE_MSK         (((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS)
+#define L1C_INVALID_DONE_UMSK        (~(((1U << L1C_INVALID_DONE_LEN) - 1) << L1C_INVALID_DONE_POS))
+#define L1C_WT_EN                    L1C_WT_EN
+#define L1C_WT_EN_POS                (4U)
+#define L1C_WT_EN_LEN                (1U)
+#define L1C_WT_EN_MSK                (((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS)
+#define L1C_WT_EN_UMSK               (~(((1U << L1C_WT_EN_LEN) - 1) << L1C_WT_EN_POS))
+#define L1C_WB_EN                    L1C_WB_EN
+#define L1C_WB_EN_POS                (5U)
+#define L1C_WB_EN_LEN                (1U)
+#define L1C_WB_EN_MSK                (((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS)
+#define L1C_WB_EN_UMSK               (~(((1U << L1C_WB_EN_LEN) - 1) << L1C_WB_EN_POS))
+#define L1C_WA_EN                    L1C_WA_EN
+#define L1C_WA_EN_POS                (6U)
+#define L1C_WA_EN_LEN                (1U)
+#define L1C_WA_EN_MSK                (((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS)
+#define L1C_WA_EN_UMSK               (~(((1U << L1C_WA_EN_LEN) - 1) << L1C_WA_EN_POS))
+#define L1C_RANDOM_REPLACE           L1C_RANDOM_REPLACE
+#define L1C_RANDOM_REPLACE_POS       (7U)
+#define L1C_RANDOM_REPLACE_LEN       (1U)
+#define L1C_RANDOM_REPLACE_MSK       (((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS)
+#define L1C_RANDOM_REPLACE_UMSK      (~(((1U << L1C_RANDOM_REPLACE_LEN) - 1) << L1C_RANDOM_REPLACE_POS))
+#define L1C_WAY_DIS                  L1C_WAY_DIS
+#define L1C_WAY_DIS_POS              (8U)
+#define L1C_WAY_DIS_LEN              (4U)
+#define L1C_WAY_DIS_MSK              (((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS)
+#define L1C_WAY_DIS_UMSK             (~(((1U << L1C_WAY_DIS_LEN) - 1) << L1C_WAY_DIS_POS))
+#define L1C_IROM_2T_ACCESS           L1C_IROM_2T_ACCESS
+#define L1C_IROM_2T_ACCESS_POS       (12U)
+#define L1C_IROM_2T_ACCESS_LEN       (1U)
+#define L1C_IROM_2T_ACCESS_MSK       (((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS)
+#define L1C_IROM_2T_ACCESS_UMSK      (~(((1U << L1C_IROM_2T_ACCESS_LEN) - 1) << L1C_IROM_2T_ACCESS_POS))
+#define L1C_BYPASS                   L1C_BYPASS
+#define L1C_BYPASS_POS               (14U)
+#define L1C_BYPASS_LEN               (1U)
+#define L1C_BYPASS_MSK               (((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS)
+#define L1C_BYPASS_UMSK              (~(((1U << L1C_BYPASS_LEN) - 1) << L1C_BYPASS_POS))
+#define L1C_BMX_ERR_EN               L1C_BMX_ERR_EN
+#define L1C_BMX_ERR_EN_POS           (15U)
+#define L1C_BMX_ERR_EN_LEN           (1U)
+#define L1C_BMX_ERR_EN_MSK           (((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS)
+#define L1C_BMX_ERR_EN_UMSK          (~(((1U << L1C_BMX_ERR_EN_LEN) - 1) << L1C_BMX_ERR_EN_POS))
+#define L1C_BMX_ARB_MODE             L1C_BMX_ARB_MODE
+#define L1C_BMX_ARB_MODE_POS         (16U)
+#define L1C_BMX_ARB_MODE_LEN         (2U)
+#define L1C_BMX_ARB_MODE_MSK         (((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS)
+#define L1C_BMX_ARB_MODE_UMSK        (~(((1U << L1C_BMX_ARB_MODE_LEN) - 1) << L1C_BMX_ARB_MODE_POS))
+#define L1C_BMX_TIMEOUT_EN           L1C_BMX_TIMEOUT_EN
+#define L1C_BMX_TIMEOUT_EN_POS       (20U)
+#define L1C_BMX_TIMEOUT_EN_LEN       (4U)
+#define L1C_BMX_TIMEOUT_EN_MSK       (((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS)
+#define L1C_BMX_TIMEOUT_EN_UMSK      (~(((1U << L1C_BMX_TIMEOUT_EN_LEN) - 1) << L1C_BMX_TIMEOUT_EN_POS))
+#define L1C_BMX_BUSY_OPTION_DIS      L1C_BMX_BUSY_OPTION_DIS
+#define L1C_BMX_BUSY_OPTION_DIS_POS  (24U)
+#define L1C_BMX_BUSY_OPTION_DIS_LEN  (1U)
+#define L1C_BMX_BUSY_OPTION_DIS_MSK  (((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS)
+#define L1C_BMX_BUSY_OPTION_DIS_UMSK (~(((1U << L1C_BMX_BUSY_OPTION_DIS_LEN) - 1) << L1C_BMX_BUSY_OPTION_DIS_POS))
+#define L1C_EARLY_RESP_DIS           L1C_EARLY_RESP_DIS
+#define L1C_EARLY_RESP_DIS_POS       (25U)
+#define L1C_EARLY_RESP_DIS_LEN       (1U)
+#define L1C_EARLY_RESP_DIS_MSK       (((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS)
+#define L1C_EARLY_RESP_DIS_UMSK      (~(((1U << L1C_EARLY_RESP_DIS_LEN) - 1) << L1C_EARLY_RESP_DIS_POS))
+#define L1C_WRAP_DIS                 L1C_WRAP_DIS
+#define L1C_WRAP_DIS_POS             (26U)
+#define L1C_WRAP_DIS_LEN             (1U)
+#define L1C_WRAP_DIS_MSK             (((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS)
+#define L1C_WRAP_DIS_UMSK            (~(((1U << L1C_WRAP_DIS_LEN) - 1) << L1C_WRAP_DIS_POS))
+#define L1C_FLUSH_EN                 L1C_FLUSH_EN
+#define L1C_FLUSH_EN_POS             (28U)
+#define L1C_FLUSH_EN_LEN             (1U)
+#define L1C_FLUSH_EN_MSK             (((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS)
+#define L1C_FLUSH_EN_UMSK            (~(((1U << L1C_FLUSH_EN_LEN) - 1) << L1C_FLUSH_EN_POS))
+#define L1C_FLUSH_DONE               L1C_FLUSH_DONE
+#define L1C_FLUSH_DONE_POS           (29U)
+#define L1C_FLUSH_DONE_LEN           (1U)
+#define L1C_FLUSH_DONE_MSK           (((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS)
+#define L1C_FLUSH_DONE_UMSK          (~(((1U << L1C_FLUSH_DONE_LEN) - 1) << L1C_FLUSH_DONE_POS))
+
+/* 0x4 : hit_cnt_lsb */
+#define L1C_HIT_CNT_LSB_OFFSET (0x4)
+#define L1C_HIT_CNT_LSB        L1C_HIT_CNT_LSB
+#define L1C_HIT_CNT_LSB_POS    (0U)
+#define L1C_HIT_CNT_LSB_LEN    (32U)
+#define L1C_HIT_CNT_LSB_MSK    (((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS)
+#define L1C_HIT_CNT_LSB_UMSK   (~(((1U << L1C_HIT_CNT_LSB_LEN) - 1) << L1C_HIT_CNT_LSB_POS))
+
+/* 0x8 : hit_cnt_msb */
+#define L1C_HIT_CNT_MSB_OFFSET (0x8)
+#define L1C_HIT_CNT_MSB        L1C_HIT_CNT_MSB
+#define L1C_HIT_CNT_MSB_POS    (0U)
+#define L1C_HIT_CNT_MSB_LEN    (32U)
+#define L1C_HIT_CNT_MSB_MSK    (((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS)
+#define L1C_HIT_CNT_MSB_UMSK   (~(((1U << L1C_HIT_CNT_MSB_LEN) - 1) << L1C_HIT_CNT_MSB_POS))
+
+/* 0xC : miss_cnt */
+#define L1C_MISS_CNT_OFFSET (0xC)
+#define L1C_MISS_CNT        L1C_MISS_CNT
+#define L1C_MISS_CNT_POS    (0U)
+#define L1C_MISS_CNT_LEN    (32U)
+#define L1C_MISS_CNT_MSK    (((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS)
+#define L1C_MISS_CNT_UMSK   (~(((1U << L1C_MISS_CNT_LEN) - 1) << L1C_MISS_CNT_POS))
+
+/* 0x10 : l1c_misc */
+#define L1C_MISC_OFFSET (0x10)
+#define L1C_FSM         L1C_FSM
+#define L1C_FSM_POS     (28U)
+#define L1C_FSM_LEN     (3U)
+#define L1C_FSM_MSK     (((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS)
+#define L1C_FSM_UMSK    (~(((1U << L1C_FSM_LEN) - 1) << L1C_FSM_POS))
+
+/* 0x200 : l1c_bmx_err_addr_en */
+#define L1C_BMX_ERR_ADDR_EN_OFFSET (0x200)
+#define L1C_BMX_ERR_ADDR_DIS       L1C_BMX_ERR_ADDR_DIS
+#define L1C_BMX_ERR_ADDR_DIS_POS   (0U)
+#define L1C_BMX_ERR_ADDR_DIS_LEN   (1U)
+#define L1C_BMX_ERR_ADDR_DIS_MSK   (((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS)
+#define L1C_BMX_ERR_ADDR_DIS_UMSK  (~(((1U << L1C_BMX_ERR_ADDR_DIS_LEN) - 1) << L1C_BMX_ERR_ADDR_DIS_POS))
+#define L1C_BMX_ERR_DEC            L1C_BMX_ERR_DEC
+#define L1C_BMX_ERR_DEC_POS        (4U)
+#define L1C_BMX_ERR_DEC_LEN        (1U)
+#define L1C_BMX_ERR_DEC_MSK        (((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS)
+#define L1C_BMX_ERR_DEC_UMSK       (~(((1U << L1C_BMX_ERR_DEC_LEN) - 1) << L1C_BMX_ERR_DEC_POS))
+#define L1C_BMX_ERR_TZ             L1C_BMX_ERR_TZ
+#define L1C_BMX_ERR_TZ_POS         (5U)
+#define L1C_BMX_ERR_TZ_LEN         (1U)
+#define L1C_BMX_ERR_TZ_MSK         (((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS)
+#define L1C_BMX_ERR_TZ_UMSK        (~(((1U << L1C_BMX_ERR_TZ_LEN) - 1) << L1C_BMX_ERR_TZ_POS))
+#define L1C_HSEL_OPTION            L1C_HSEL_OPTION
+#define L1C_HSEL_OPTION_POS        (16U)
+#define L1C_HSEL_OPTION_LEN        (4U)
+#define L1C_HSEL_OPTION_MSK        (((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS)
+#define L1C_HSEL_OPTION_UMSK       (~(((1U << L1C_HSEL_OPTION_LEN) - 1) << L1C_HSEL_OPTION_POS))
+
+/* 0x204 : l1c_bmx_err_addr */
+#define L1C_BMX_ERR_ADDR_OFFSET (0x204)
+#define L1C_BMX_ERR_ADDR        L1C_BMX_ERR_ADDR
+#define L1C_BMX_ERR_ADDR_POS    (0U)
+#define L1C_BMX_ERR_ADDR_LEN    (32U)
+#define L1C_BMX_ERR_ADDR_MSK    (((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS)
+#define L1C_BMX_ERR_ADDR_UMSK   (~(((1U << L1C_BMX_ERR_ADDR_LEN) - 1) << L1C_BMX_ERR_ADDR_POS))
+
+/* 0x208 : irom1_misr_dataout_0 */
+#define L1C_IROM1_MISR_DATAOUT_0_OFFSET (0x208)
+#define L1C_IROM1_MISR_DATAOUT_0        L1C_IROM1_MISR_DATAOUT_0
+#define L1C_IROM1_MISR_DATAOUT_0_POS    (0U)
+#define L1C_IROM1_MISR_DATAOUT_0_LEN    (32U)
+#define L1C_IROM1_MISR_DATAOUT_0_MSK    (((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS)
+#define L1C_IROM1_MISR_DATAOUT_0_UMSK   (~(((1U << L1C_IROM1_MISR_DATAOUT_0_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_0_POS))
+
+/* 0x20C : irom1_misr_dataout_1 */
+#define L1C_IROM1_MISR_DATAOUT_1_OFFSET (0x20C)
+#define L1C_IROM1_MISR_DATAOUT_1        L1C_IROM1_MISR_DATAOUT_1
+#define L1C_IROM1_MISR_DATAOUT_1_POS    (0U)
+#define L1C_IROM1_MISR_DATAOUT_1_LEN    (32U)
+#define L1C_IROM1_MISR_DATAOUT_1_MSK    (((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS)
+#define L1C_IROM1_MISR_DATAOUT_1_UMSK   (~(((1U << L1C_IROM1_MISR_DATAOUT_1_LEN) - 1) << L1C_IROM1_MISR_DATAOUT_1_POS))
+
+/* 0x210 : cpu_clk_gate */
+#define L1C_CPU_CLK_GATE_OFFSET       (0x210)
+#define L1C_FORCE_E21_CLOCK_ON_0      L1C_FORCE_E21_CLOCK_ON_0
+#define L1C_FORCE_E21_CLOCK_ON_0_POS  (0U)
+#define L1C_FORCE_E21_CLOCK_ON_0_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_0_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS)
+#define L1C_FORCE_E21_CLOCK_ON_0_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_0_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_0_POS))
+#define L1C_FORCE_E21_CLOCK_ON_1      L1C_FORCE_E21_CLOCK_ON_1
+#define L1C_FORCE_E21_CLOCK_ON_1_POS  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_1_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_1_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS)
+#define L1C_FORCE_E21_CLOCK_ON_1_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_1_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_1_POS))
+#define L1C_FORCE_E21_CLOCK_ON_2      L1C_FORCE_E21_CLOCK_ON_2
+#define L1C_FORCE_E21_CLOCK_ON_2_POS  (2U)
+#define L1C_FORCE_E21_CLOCK_ON_2_LEN  (1U)
+#define L1C_FORCE_E21_CLOCK_ON_2_MSK  (((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS)
+#define L1C_FORCE_E21_CLOCK_ON_2_UMSK (~(((1U << L1C_FORCE_E21_CLOCK_ON_2_LEN) - 1) << L1C_FORCE_E21_CLOCK_ON_2_POS))
+
+struct l1c_reg {
+    /* 0x0 : l1c_config */
+    union {
+        struct
+        {
+            uint32_t l1c_cacheable           : 1; /* [    0],        r/w,        0x0 */
+            uint32_t l1c_cnt_en              : 1; /* [    1],        r/w,        0x0 */
+            uint32_t l1c_invalid_en          : 1; /* [    2],        r/w,        0x0 */
+            uint32_t l1c_invalid_done        : 1; /* [    3],          r,        0x0 */
+            uint32_t l1c_wt_en               : 1; /* [    4],        r/w,        0x0 */
+            uint32_t l1c_wb_en               : 1; /* [    5],        r/w,        0x1 */
+            uint32_t l1c_wa_en               : 1; /* [    6],        r/w,        0x1 */
+            uint32_t l1c_random_replace      : 1; /* [    7],        r/w,        0x0 */
+            uint32_t l1c_way_dis             : 4; /* [11: 8],        r/w,        0xf */
+            uint32_t irom_2t_access          : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13             : 1; /* [   13],       rsvd,        0x0 */
+            uint32_t l1c_bypass              : 1; /* [   14],        r/w,        0x0 */
+            uint32_t l1c_bmx_err_en          : 1; /* [   15],        r/w,        0x0 */
+            uint32_t l1c_bmx_arb_mode        : 2; /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_19          : 2; /* [19:18],       rsvd,        0x0 */
+            uint32_t l1c_bmx_timeout_en      : 4; /* [23:20],        r/w,        0x0 */
+            uint32_t l1c_bmx_busy_option_dis : 1; /* [   24],        r/w,        0x0 */
+            uint32_t early_resp_dis          : 1; /* [   25],        r/w,        0x1 */
+            uint32_t wrap_dis                : 1; /* [   26],        r/w,        0x1 */
+            uint32_t reserved_27             : 1; /* [   27],       rsvd,        0x0 */
+            uint32_t l1c_flush_en            : 1; /* [   28],        r/w,        0x0 */
+            uint32_t l1c_flush_done          : 1; /* [   29],          r,        0x0 */
+            uint32_t reserved_31_30          : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_config;
+
+    /* 0x4 : hit_cnt_lsb */
+    union {
+        struct
+        {
+            uint32_t hit_cnt_lsb : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hit_cnt_lsb;
+
+    /* 0x8 : hit_cnt_msb */
+    union {
+        struct
+        {
+            uint32_t hit_cnt_msb : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } hit_cnt_msb;
+
+    /* 0xC : miss_cnt */
+    union {
+        struct
+        {
+            uint32_t miss_cnt : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } miss_cnt;
+
+    /* 0x10 : l1c_misc */
+    union {
+        struct
+        {
+            uint32_t reserved_0_27 : 28; /* [27: 0],       rsvd,        0x0 */
+            uint32_t l1c_fsm       : 3;  /* [30:28],          r,        0x0 */
+            uint32_t reserved_31   : 1;  /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_misc;
+
+    /* 0x14  reserved */
+    uint8_t RESERVED0x14[492];
+
+    /* 0x200 : l1c_bmx_err_addr_en */
+    union {
+        struct
+        {
+            uint32_t l1c_bmx_err_addr_dis : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t l1c_bmx_err_dec      : 1;  /* [    4],          r,        0x0 */
+            uint32_t l1c_bmx_err_tz       : 1;  /* [    5],          r,        0x0 */
+            uint32_t reserved_6_15        : 10; /* [15: 6],       rsvd,        0x0 */
+            uint32_t l1c_hsel_option      : 4;  /* [19:16],        r/w,        0x0 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_bmx_err_addr_en;
+
+    /* 0x204 : l1c_bmx_err_addr */
+    union {
+        struct
+        {
+            uint32_t l1c_bmx_err_addr : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } l1c_bmx_err_addr;
+
+    /* 0x208 : irom1_misr_dataout_0 */
+    union {
+        struct
+        {
+            uint32_t irom1_misr_dataout_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_0;
+
+    /* 0x20C : irom1_misr_dataout_1 */
+    union {
+        struct
+        {
+            uint32_t irom1_misr_dataout_1 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } irom1_misr_dataout_1;
+
+    /* 0x210 : cpu_clk_gate */
+    union {
+        struct
+        {
+            uint32_t force_e21_clock_on_0 : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t force_e21_clock_on_1 : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t force_e21_clock_on_2 : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_31        : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } cpu_clk_gate;
+};
+
+typedef volatile struct l1c_reg l1c_reg_t;
+
+#endif /* __L1C_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/pds_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/pds_reg.h
new file mode 100755
index 0000000000..9b2a0d6261
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/pds_reg.h
@@ -0,0 +1,1411 @@
+/**
+  ******************************************************************************
+  * @file    pds_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __PDS_REG_H__
+#define __PDS_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : PDS_CTL */
+#define PDS_CTL_OFFSET                     (0x0)
+#define PDS_START_PS                       PDS_START_PS
+#define PDS_START_PS_POS                   (0U)
+#define PDS_START_PS_LEN                   (1U)
+#define PDS_START_PS_MSK                   (((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS)
+#define PDS_START_PS_UMSK                  (~(((1U << PDS_START_PS_LEN) - 1) << PDS_START_PS_POS))
+#define PDS_CR_SLEEP_FOREVER               PDS_CR_SLEEP_FOREVER
+#define PDS_CR_SLEEP_FOREVER_POS           (1U)
+#define PDS_CR_SLEEP_FOREVER_LEN           (1U)
+#define PDS_CR_SLEEP_FOREVER_MSK           (((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS)
+#define PDS_CR_SLEEP_FOREVER_UMSK          (~(((1U << PDS_CR_SLEEP_FOREVER_LEN) - 1) << PDS_CR_SLEEP_FOREVER_POS))
+#define PDS_CR_XTAL_FORCE_OFF              PDS_CR_XTAL_FORCE_OFF
+#define PDS_CR_XTAL_FORCE_OFF_POS          (2U)
+#define PDS_CR_XTAL_FORCE_OFF_LEN          (1U)
+#define PDS_CR_XTAL_FORCE_OFF_MSK          (((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS)
+#define PDS_CR_XTAL_FORCE_OFF_UMSK         (~(((1U << PDS_CR_XTAL_FORCE_OFF_LEN) - 1) << PDS_CR_XTAL_FORCE_OFF_POS))
+#define PDS_CR_WIFI_PDS_SAVE_STATE         PDS_CR_WIFI_PDS_SAVE_STATE
+#define PDS_CR_WIFI_PDS_SAVE_STATE_POS     (3U)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_LEN     (1U)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_MSK     (((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS)
+#define PDS_CR_WIFI_PDS_SAVE_STATE_UMSK    (~(((1U << PDS_CR_WIFI_PDS_SAVE_STATE_LEN) - 1) << PDS_CR_WIFI_PDS_SAVE_STATE_POS))
+#define PDS_CR_PDS_PD_DCDC18               PDS_CR_PDS_PD_DCDC18
+#define PDS_CR_PDS_PD_DCDC18_POS           (4U)
+#define PDS_CR_PDS_PD_DCDC18_LEN           (1U)
+#define PDS_CR_PDS_PD_DCDC18_MSK           (((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS)
+#define PDS_CR_PDS_PD_DCDC18_UMSK          (~(((1U << PDS_CR_PDS_PD_DCDC18_LEN) - 1) << PDS_CR_PDS_PD_DCDC18_POS))
+#define PDS_CR_PDS_PD_BG_SYS               PDS_CR_PDS_PD_BG_SYS
+#define PDS_CR_PDS_PD_BG_SYS_POS           (5U)
+#define PDS_CR_PDS_PD_BG_SYS_LEN           (1U)
+#define PDS_CR_PDS_PD_BG_SYS_MSK           (((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS)
+#define PDS_CR_PDS_PD_BG_SYS_UMSK          (~(((1U << PDS_CR_PDS_PD_BG_SYS_LEN) - 1) << PDS_CR_PDS_PD_BG_SYS_POS))
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD      PDS_CR_PDS_CTRL_GPIO_IE_PU_PD
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS  (6U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN  (1U)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_MSK  (((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS)
+#define PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_UMSK (~(((1U << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_LEN) - 1) << PDS_CR_PDS_CTRL_GPIO_IE_PU_PD_POS))
+#define PDS_CR_PDS_CTRL_PU_FLASH           PDS_CR_PDS_CTRL_PU_FLASH
+#define PDS_CR_PDS_CTRL_PU_FLASH_POS       (7U)
+#define PDS_CR_PDS_CTRL_PU_FLASH_LEN       (1U)
+#define PDS_CR_PDS_CTRL_PU_FLASH_MSK       (((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS)
+#define PDS_CR_PDS_CTRL_PU_FLASH_UMSK      (~(((1U << PDS_CR_PDS_CTRL_PU_FLASH_LEN) - 1) << PDS_CR_PDS_CTRL_PU_FLASH_POS))
+#define PDS_CR_PDS_GATE_CLK                PDS_CR_PDS_GATE_CLK
+#define PDS_CR_PDS_GATE_CLK_POS            (8U)
+#define PDS_CR_PDS_GATE_CLK_LEN            (1U)
+#define PDS_CR_PDS_GATE_CLK_MSK            (((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS)
+#define PDS_CR_PDS_GATE_CLK_UMSK           (~(((1U << PDS_CR_PDS_GATE_CLK_LEN) - 1) << PDS_CR_PDS_GATE_CLK_POS))
+#define PDS_CR_PDS_MEM_STBY                PDS_CR_PDS_MEM_STBY
+#define PDS_CR_PDS_MEM_STBY_POS            (9U)
+#define PDS_CR_PDS_MEM_STBY_LEN            (1U)
+#define PDS_CR_PDS_MEM_STBY_MSK            (((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS)
+#define PDS_CR_PDS_MEM_STBY_UMSK           (~(((1U << PDS_CR_PDS_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MEM_STBY_POS))
+#define PDS_CR_SW_PU_FLASH                 PDS_CR_SW_PU_FLASH
+#define PDS_CR_SW_PU_FLASH_POS             (10U)
+#define PDS_CR_SW_PU_FLASH_LEN             (1U)
+#define PDS_CR_SW_PU_FLASH_MSK             (((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS)
+#define PDS_CR_SW_PU_FLASH_UMSK            (~(((1U << PDS_CR_SW_PU_FLASH_LEN) - 1) << PDS_CR_SW_PU_FLASH_POS))
+#define PDS_CR_PDS_ISO_EN                  PDS_CR_PDS_ISO_EN
+#define PDS_CR_PDS_ISO_EN_POS              (11U)
+#define PDS_CR_PDS_ISO_EN_LEN              (1U)
+#define PDS_CR_PDS_ISO_EN_MSK              (((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS)
+#define PDS_CR_PDS_ISO_EN_UMSK             (~(((1U << PDS_CR_PDS_ISO_EN_LEN) - 1) << PDS_CR_PDS_ISO_EN_POS))
+#define PDS_CR_PDS_WAIT_XTAL_RDY           PDS_CR_PDS_WAIT_XTAL_RDY
+#define PDS_CR_PDS_WAIT_XTAL_RDY_POS       (12U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_LEN       (1U)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_MSK       (((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS)
+#define PDS_CR_PDS_WAIT_XTAL_RDY_UMSK      (~(((1U << PDS_CR_PDS_WAIT_XTAL_RDY_LEN) - 1) << PDS_CR_PDS_WAIT_XTAL_RDY_POS))
+#define PDS_CR_PDS_PWR_OFF                 PDS_CR_PDS_PWR_OFF
+#define PDS_CR_PDS_PWR_OFF_POS             (13U)
+#define PDS_CR_PDS_PWR_OFF_LEN             (1U)
+#define PDS_CR_PDS_PWR_OFF_MSK             (((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS)
+#define PDS_CR_PDS_PWR_OFF_UMSK            (~(((1U << PDS_CR_PDS_PWR_OFF_LEN) - 1) << PDS_CR_PDS_PWR_OFF_POS))
+#define PDS_CR_PDS_PD_XTAL                 PDS_CR_PDS_PD_XTAL
+#define PDS_CR_PDS_PD_XTAL_POS             (14U)
+#define PDS_CR_PDS_PD_XTAL_LEN             (1U)
+#define PDS_CR_PDS_PD_XTAL_MSK             (((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS)
+#define PDS_CR_PDS_PD_XTAL_UMSK            (~(((1U << PDS_CR_PDS_PD_XTAL_LEN) - 1) << PDS_CR_PDS_PD_XTAL_POS))
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON        PDS_CR_PDS_SOC_ENB_FORCE_ON
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_POS    (15U)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN    (1U)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_MSK    (((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS)
+#define PDS_CR_PDS_SOC_ENB_FORCE_ON_UMSK   (~(((1U << PDS_CR_PDS_SOC_ENB_FORCE_ON_LEN) - 1) << PDS_CR_PDS_SOC_ENB_FORCE_ON_POS))
+#define PDS_CR_PDS_RST_SOC_EN              PDS_CR_PDS_RST_SOC_EN
+#define PDS_CR_PDS_RST_SOC_EN_POS          (16U)
+#define PDS_CR_PDS_RST_SOC_EN_LEN          (1U)
+#define PDS_CR_PDS_RST_SOC_EN_MSK          (((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS)
+#define PDS_CR_PDS_RST_SOC_EN_UMSK         (~(((1U << PDS_CR_PDS_RST_SOC_EN_LEN) - 1) << PDS_CR_PDS_RST_SOC_EN_POS))
+#define PDS_CR_PDS_RC32M_OFF_DIS           PDS_CR_PDS_RC32M_OFF_DIS
+#define PDS_CR_PDS_RC32M_OFF_DIS_POS       (17U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_LEN       (1U)
+#define PDS_CR_PDS_RC32M_OFF_DIS_MSK       (((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS)
+#define PDS_CR_PDS_RC32M_OFF_DIS_UMSK      (~(((1U << PDS_CR_PDS_RC32M_OFF_DIS_LEN) - 1) << PDS_CR_PDS_RC32M_OFF_DIS_POS))
+#define PDS_CR_PDS_LDO_VSEL_EN             PDS_CR_PDS_LDO_VSEL_EN
+#define PDS_CR_PDS_LDO_VSEL_EN_POS         (18U)
+#define PDS_CR_PDS_LDO_VSEL_EN_LEN         (1U)
+#define PDS_CR_PDS_LDO_VSEL_EN_MSK         (((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS)
+#define PDS_CR_PDS_LDO_VSEL_EN_UMSK        (~(((1U << PDS_CR_PDS_LDO_VSEL_EN_LEN) - 1) << PDS_CR_PDS_LDO_VSEL_EN_POS))
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN      PDS_CR_PDS_RAM_LP_WITH_CLK_EN
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS  (19U)
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN  (1U)
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_MSK  (((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS)
+#define PDS_CR_PDS_RAM_LP_WITH_CLK_EN_UMSK (~(((1U << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_LEN) - 1) << PDS_CR_PDS_RAM_LP_WITH_CLK_EN_POS))
+#define PDS_CR_NP_WFI_MASK                 PDS_CR_NP_WFI_MASK
+#define PDS_CR_NP_WFI_MASK_POS             (21U)
+#define PDS_CR_NP_WFI_MASK_LEN             (1U)
+#define PDS_CR_NP_WFI_MASK_MSK             (((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS)
+#define PDS_CR_NP_WFI_MASK_UMSK            (~(((1U << PDS_CR_NP_WFI_MASK_LEN) - 1) << PDS_CR_NP_WFI_MASK_POS))
+#define PDS_CR_PDS_PD_LDO11                PDS_CR_PDS_PD_LDO11
+#define PDS_CR_PDS_PD_LDO11_POS            (22U)
+#define PDS_CR_PDS_PD_LDO11_LEN            (1U)
+#define PDS_CR_PDS_PD_LDO11_MSK            (((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS)
+#define PDS_CR_PDS_PD_LDO11_UMSK           (~(((1U << PDS_CR_PDS_PD_LDO11_LEN) - 1) << PDS_CR_PDS_PD_LDO11_POS))
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN        PDS_CR_PDS_FORCE_RAM_CLK_EN
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_POS    (23U)
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_MSK    (((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS)
+#define PDS_CR_PDS_FORCE_RAM_CLK_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_RAM_CLK_EN_LEN) - 1) << PDS_CR_PDS_FORCE_RAM_CLK_EN_POS))
+#define PDS_CR_PDS_LDO_VOL                 PDS_CR_PDS_LDO_VOL
+#define PDS_CR_PDS_LDO_VOL_POS             (24U)
+#define PDS_CR_PDS_LDO_VOL_LEN             (4U)
+#define PDS_CR_PDS_LDO_VOL_MSK             (((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS)
+#define PDS_CR_PDS_LDO_VOL_UMSK            (~(((1U << PDS_CR_PDS_LDO_VOL_LEN) - 1) << PDS_CR_PDS_LDO_VOL_POS))
+#define PDS_CR_PDS_CTRL_RF                 PDS_CR_PDS_CTRL_RF
+#define PDS_CR_PDS_CTRL_RF_POS             (28U)
+#define PDS_CR_PDS_CTRL_RF_LEN             (2U)
+#define PDS_CR_PDS_CTRL_RF_MSK             (((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS)
+#define PDS_CR_PDS_CTRL_RF_UMSK            (~(((1U << PDS_CR_PDS_CTRL_RF_LEN) - 1) << PDS_CR_PDS_CTRL_RF_POS))
+#define PDS_CR_PDS_CTRL_PLL                PDS_CR_PDS_CTRL_PLL
+#define PDS_CR_PDS_CTRL_PLL_POS            (30U)
+#define PDS_CR_PDS_CTRL_PLL_LEN            (2U)
+#define PDS_CR_PDS_CTRL_PLL_MSK            (((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS)
+#define PDS_CR_PDS_CTRL_PLL_UMSK           (~(((1U << PDS_CR_PDS_CTRL_PLL_LEN) - 1) << PDS_CR_PDS_CTRL_PLL_POS))
+
+/* 0x4 : PDS_TIME1 */
+#define PDS_TIME1_OFFSET           (0x4)
+#define PDS_CR_SLEEP_DURATION      PDS_CR_SLEEP_DURATION
+#define PDS_CR_SLEEP_DURATION_POS  (0U)
+#define PDS_CR_SLEEP_DURATION_LEN  (32U)
+#define PDS_CR_SLEEP_DURATION_MSK  (((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS)
+#define PDS_CR_SLEEP_DURATION_UMSK (~(((1U << PDS_CR_SLEEP_DURATION_LEN) - 1) << PDS_CR_SLEEP_DURATION_POS))
+
+/* 0xC : PDS_INT */
+#define PDS_INT_OFFSET                    (0xC)
+#define PDS_RO_PDS_WAKE_INT               PDS_RO_PDS_WAKE_INT
+#define PDS_RO_PDS_WAKE_INT_POS           (0U)
+#define PDS_RO_PDS_WAKE_INT_LEN           (1U)
+#define PDS_RO_PDS_WAKE_INT_MSK           (((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS)
+#define PDS_RO_PDS_WAKE_INT_UMSK          (~(((1U << PDS_RO_PDS_WAKE_INT_LEN) - 1) << PDS_RO_PDS_WAKE_INT_POS))
+#define PDS_RO_PDS_RF_DONE_INT            PDS_RO_PDS_RF_DONE_INT
+#define PDS_RO_PDS_RF_DONE_INT_POS        (2U)
+#define PDS_RO_PDS_RF_DONE_INT_LEN        (1U)
+#define PDS_RO_PDS_RF_DONE_INT_MSK        (((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS)
+#define PDS_RO_PDS_RF_DONE_INT_UMSK       (~(((1U << PDS_RO_PDS_RF_DONE_INT_LEN) - 1) << PDS_RO_PDS_RF_DONE_INT_POS))
+#define PDS_RO_PDS_PLL_DONE_INT           PDS_RO_PDS_PLL_DONE_INT
+#define PDS_RO_PDS_PLL_DONE_INT_POS       (3U)
+#define PDS_RO_PDS_PLL_DONE_INT_LEN       (1U)
+#define PDS_RO_PDS_PLL_DONE_INT_MSK       (((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS)
+#define PDS_RO_PDS_PLL_DONE_INT_UMSK      (~(((1U << PDS_RO_PDS_PLL_DONE_INT_LEN) - 1) << PDS_RO_PDS_PLL_DONE_INT_POS))
+#define PDS_RESET_EVENT                   PDS_RESET_EVENT
+#define PDS_RESET_EVENT_POS               (4U)
+#define PDS_RESET_EVENT_LEN               (3U)
+#define PDS_RESET_EVENT_MSK               (((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS)
+#define PDS_RESET_EVENT_UMSK              (~(((1U << PDS_RESET_EVENT_LEN) - 1) << PDS_RESET_EVENT_POS))
+#define PDS_CLR_RESET_EVENT               PDS_CLR_RESET_EVENT
+#define PDS_CLR_RESET_EVENT_POS           (7U)
+#define PDS_CLR_RESET_EVENT_LEN           (1U)
+#define PDS_CLR_RESET_EVENT_MSK           (((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS)
+#define PDS_CLR_RESET_EVENT_UMSK          (~(((1U << PDS_CLR_RESET_EVENT_LEN) - 1) << PDS_CLR_RESET_EVENT_POS))
+#define PDS_CR_PDS_WAKE_INT_MASK          PDS_CR_PDS_WAKE_INT_MASK
+#define PDS_CR_PDS_WAKE_INT_MASK_POS      (8U)
+#define PDS_CR_PDS_WAKE_INT_MASK_LEN      (1U)
+#define PDS_CR_PDS_WAKE_INT_MASK_MSK      (((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS)
+#define PDS_CR_PDS_WAKE_INT_MASK_UMSK     (~(((1U << PDS_CR_PDS_WAKE_INT_MASK_LEN) - 1) << PDS_CR_PDS_WAKE_INT_MASK_POS))
+#define PDS_CR_PDS_RF_DONE_INT_MASK       PDS_CR_PDS_RF_DONE_INT_MASK
+#define PDS_CR_PDS_RF_DONE_INT_MASK_POS   (10U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_LEN   (1U)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_MSK   (((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_RF_DONE_INT_MASK_UMSK  (~(((1U << PDS_CR_PDS_RF_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_RF_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_PLL_DONE_INT_MASK      PDS_CR_PDS_PLL_DONE_INT_MASK
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_POS  (11U)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_LEN  (1U)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_MSK  (((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS)
+#define PDS_CR_PDS_PLL_DONE_INT_MASK_UMSK (~(((1U << PDS_CR_PDS_PLL_DONE_INT_MASK_LEN) - 1) << PDS_CR_PDS_PLL_DONE_INT_MASK_POS))
+#define PDS_CR_PDS_INT_CLR                PDS_CR_PDS_INT_CLR
+#define PDS_CR_PDS_INT_CLR_POS            (15U)
+#define PDS_CR_PDS_INT_CLR_LEN            (1U)
+#define PDS_CR_PDS_INT_CLR_MSK            (((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS)
+#define PDS_CR_PDS_INT_CLR_UMSK           (~(((1U << PDS_CR_PDS_INT_CLR_LEN) - 1) << PDS_CR_PDS_INT_CLR_POS))
+#define PDS_CR_PDS_WAKEUP_SRC_EN          PDS_CR_PDS_WAKEUP_SRC_EN
+#define PDS_CR_PDS_WAKEUP_SRC_EN_POS      (16U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_LEN      (8U)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_MSK      (((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS)
+#define PDS_CR_PDS_WAKEUP_SRC_EN_UMSK     (~(((1U << PDS_CR_PDS_WAKEUP_SRC_EN_LEN) - 1) << PDS_CR_PDS_WAKEUP_SRC_EN_POS))
+#define PDS_RO_PDS_WAKEUP_EVENT           PDS_RO_PDS_WAKEUP_EVENT
+#define PDS_RO_PDS_WAKEUP_EVENT_POS       (24U)
+#define PDS_RO_PDS_WAKEUP_EVENT_LEN       (8U)
+#define PDS_RO_PDS_WAKEUP_EVENT_MSK       (((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS)
+#define PDS_RO_PDS_WAKEUP_EVENT_UMSK      (~(((1U << PDS_RO_PDS_WAKEUP_EVENT_LEN) - 1) << PDS_RO_PDS_WAKEUP_EVENT_POS))
+
+/* 0x10 : PDS_CTL2 */
+#define PDS_CTL2_OFFSET                    (0x10)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF        PDS_CR_PDS_FORCE_NP_PWR_OFF
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_POS    (0U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_NP_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF        PDS_CR_PDS_FORCE_BZ_PWR_OFF
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS    (2U)
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_BZ_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF       PDS_CR_PDS_FORCE_USB_PWR_OFF
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_POS   (3U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_USB_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_NP_ISO_EN         PDS_CR_PDS_FORCE_NP_ISO_EN
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_POS     (4U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_NP_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_NP_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN         PDS_CR_PDS_FORCE_BZ_ISO_EN
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_POS     (6U)
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_BZ_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_USB_ISO_EN        PDS_CR_PDS_FORCE_USB_ISO_EN
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_POS    (7U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_LEN    (1U)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_MSK    (((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_USB_ISO_EN_UMSK   (~(((1U << PDS_CR_PDS_FORCE_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_USB_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_NP_PDS_RST        PDS_CR_PDS_FORCE_NP_PDS_RST
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_POS    (8U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_NP_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_NP_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_NP_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST        PDS_CR_PDS_FORCE_BZ_PDS_RST
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_POS    (10U)
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_BZ_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BZ_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_USB_PDS_RST       PDS_CR_PDS_FORCE_USB_PDS_RST
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_POS   (11U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_USB_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_USB_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_USB_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY       PDS_CR_PDS_FORCE_NP_MEM_STBY
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_POS   (12U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_NP_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY       PDS_CR_PDS_FORCE_BZ_MEM_STBY
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS   (14U)
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_BZ_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY      PDS_CR_PDS_FORCE_USB_MEM_STBY
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_POS  (15U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_USB_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK       PDS_CR_PDS_FORCE_NP_GATE_CLK
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_POS   (16U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_NP_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK       PDS_CR_PDS_FORCE_BZ_GATE_CLK
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS   (18U)
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_BZ_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BZ_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK      PDS_CR_PDS_FORCE_USB_GATE_CLK
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_POS  (19U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_USB_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_USB_GATE_CLK_POS))
+
+/* 0x14 : PDS_CTL3 */
+#define PDS_CTL3_OFFSET                     (0x14)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF       PDS_CR_PDS_FORCE_MISC_PWR_OFF
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_MISC_PWR_OFF_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF        PDS_CR_PDS_FORCE_BLE_PWR_OFF
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS    (2U)
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_MSK    (((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS)
+#define PDS_CR_PDS_FORCE_BLE_PWR_OFF_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PWR_OFF_POS))
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN         PDS_CR_PDS_FORCE_BLE_ISO_EN
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_POS     (5U)
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN     (1U)
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_MSK     (((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS)
+#define PDS_CR_PDS_FORCE_BLE_ISO_EN_UMSK    (~(((1U << PDS_CR_PDS_FORCE_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_ISO_EN_POS))
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST       PDS_CR_PDS_FORCE_MISC_PDS_RST
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_POS   (7U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN   (1U)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_MSK   (((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_MISC_PDS_RST_UMSK  (~(((1U << PDS_CR_PDS_FORCE_MISC_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST        PDS_CR_PDS_FORCE_BLE_PDS_RST
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_POS    (8U)
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN    (1U)
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_MSK    (((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS)
+#define PDS_CR_PDS_FORCE_BLE_PDS_RST_UMSK   (~(((1U << PDS_CR_PDS_FORCE_BLE_PDS_RST_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_PDS_RST_POS))
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY      PDS_CR_PDS_FORCE_MISC_MEM_STBY
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS  (10U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_MISC_MEM_STBY_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY       PDS_CR_PDS_FORCE_BLE_MEM_STBY
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS   (11U)
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_MSK   (((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS)
+#define PDS_CR_PDS_FORCE_BLE_MEM_STBY_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_MEM_STBY_POS))
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK      PDS_CR_PDS_FORCE_MISC_GATE_CLK
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS  (13U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN  (1U)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_MSK  (((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_MISC_GATE_CLK_UMSK (~(((1U << PDS_CR_PDS_FORCE_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_MISC_GATE_CLK_POS))
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK       PDS_CR_PDS_FORCE_BLE_GATE_CLK
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS   (14U)
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN   (1U)
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_MSK   (((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS)
+#define PDS_CR_PDS_FORCE_BLE_GATE_CLK_UMSK  (~(((1U << PDS_CR_PDS_FORCE_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_FORCE_BLE_GATE_CLK_POS))
+#define PDS_CR_PDS_NP_ISO_EN                PDS_CR_PDS_NP_ISO_EN
+#define PDS_CR_PDS_NP_ISO_EN_POS            (24U)
+#define PDS_CR_PDS_NP_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_NP_ISO_EN_MSK            (((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS)
+#define PDS_CR_PDS_NP_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_NP_ISO_EN_LEN) - 1) << PDS_CR_PDS_NP_ISO_EN_POS))
+#define PDS_CR_PDS_BZ_ISO_EN                PDS_CR_PDS_BZ_ISO_EN
+#define PDS_CR_PDS_BZ_ISO_EN_POS            (27U)
+#define PDS_CR_PDS_BZ_ISO_EN_LEN            (1U)
+#define PDS_CR_PDS_BZ_ISO_EN_MSK            (((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS)
+#define PDS_CR_PDS_BZ_ISO_EN_UMSK           (~(((1U << PDS_CR_PDS_BZ_ISO_EN_LEN) - 1) << PDS_CR_PDS_BZ_ISO_EN_POS))
+#define PDS_CR_PDS_BLE_ISO_EN               PDS_CR_PDS_BLE_ISO_EN
+#define PDS_CR_PDS_BLE_ISO_EN_POS           (28U)
+#define PDS_CR_PDS_BLE_ISO_EN_LEN           (1U)
+#define PDS_CR_PDS_BLE_ISO_EN_MSK           (((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS)
+#define PDS_CR_PDS_BLE_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_BLE_ISO_EN_LEN) - 1) << PDS_CR_PDS_BLE_ISO_EN_POS))
+#define PDS_CR_PDS_USB_ISO_EN               PDS_CR_PDS_USB_ISO_EN
+#define PDS_CR_PDS_USB_ISO_EN_POS           (29U)
+#define PDS_CR_PDS_USB_ISO_EN_LEN           (1U)
+#define PDS_CR_PDS_USB_ISO_EN_MSK           (((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS)
+#define PDS_CR_PDS_USB_ISO_EN_UMSK          (~(((1U << PDS_CR_PDS_USB_ISO_EN_LEN) - 1) << PDS_CR_PDS_USB_ISO_EN_POS))
+#define PDS_CR_PDS_MISC_ISO_EN              PDS_CR_PDS_MISC_ISO_EN
+#define PDS_CR_PDS_MISC_ISO_EN_POS          (30U)
+#define PDS_CR_PDS_MISC_ISO_EN_LEN          (1U)
+#define PDS_CR_PDS_MISC_ISO_EN_MSK          (((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS)
+#define PDS_CR_PDS_MISC_ISO_EN_UMSK         (~(((1U << PDS_CR_PDS_MISC_ISO_EN_LEN) - 1) << PDS_CR_PDS_MISC_ISO_EN_POS))
+
+/* 0x18 : PDS_CTL4 */
+#define PDS_CTL4_OFFSET                  (0x18)
+#define PDS_CR_PDS_NP_PWR_OFF            PDS_CR_PDS_NP_PWR_OFF
+#define PDS_CR_PDS_NP_PWR_OFF_POS        (0U)
+#define PDS_CR_PDS_NP_PWR_OFF_LEN        (1U)
+#define PDS_CR_PDS_NP_PWR_OFF_MSK        (((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS)
+#define PDS_CR_PDS_NP_PWR_OFF_UMSK       (~(((1U << PDS_CR_PDS_NP_PWR_OFF_LEN) - 1) << PDS_CR_PDS_NP_PWR_OFF_POS))
+#define PDS_CR_PDS_NP_RESET              PDS_CR_PDS_NP_RESET
+#define PDS_CR_PDS_NP_RESET_POS          (1U)
+#define PDS_CR_PDS_NP_RESET_LEN          (1U)
+#define PDS_CR_PDS_NP_RESET_MSK          (((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS)
+#define PDS_CR_PDS_NP_RESET_UMSK         (~(((1U << PDS_CR_PDS_NP_RESET_LEN) - 1) << PDS_CR_PDS_NP_RESET_POS))
+#define PDS_CR_PDS_NP_MEM_STBY           PDS_CR_PDS_NP_MEM_STBY
+#define PDS_CR_PDS_NP_MEM_STBY_POS       (2U)
+#define PDS_CR_PDS_NP_MEM_STBY_LEN       (1U)
+#define PDS_CR_PDS_NP_MEM_STBY_MSK       (((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS)
+#define PDS_CR_PDS_NP_MEM_STBY_UMSK      (~(((1U << PDS_CR_PDS_NP_MEM_STBY_LEN) - 1) << PDS_CR_PDS_NP_MEM_STBY_POS))
+#define PDS_CR_PDS_NP_GATE_CLK           PDS_CR_PDS_NP_GATE_CLK
+#define PDS_CR_PDS_NP_GATE_CLK_POS       (3U)
+#define PDS_CR_PDS_NP_GATE_CLK_LEN       (1U)
+#define PDS_CR_PDS_NP_GATE_CLK_MSK       (((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS)
+#define PDS_CR_PDS_NP_GATE_CLK_UMSK      (~(((1U << PDS_CR_PDS_NP_GATE_CLK_LEN) - 1) << PDS_CR_PDS_NP_GATE_CLK_POS))
+#define PDS_CR_PDS_BZ_PWR_OFF            PDS_CR_PDS_BZ_PWR_OFF
+#define PDS_CR_PDS_BZ_PWR_OFF_POS        (12U)
+#define PDS_CR_PDS_BZ_PWR_OFF_LEN        (1U)
+#define PDS_CR_PDS_BZ_PWR_OFF_MSK        (((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS)
+#define PDS_CR_PDS_BZ_PWR_OFF_UMSK       (~(((1U << PDS_CR_PDS_BZ_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BZ_PWR_OFF_POS))
+#define PDS_CR_PDS_BZ_RESET              PDS_CR_PDS_BZ_RESET
+#define PDS_CR_PDS_BZ_RESET_POS          (13U)
+#define PDS_CR_PDS_BZ_RESET_LEN          (1U)
+#define PDS_CR_PDS_BZ_RESET_MSK          (((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS)
+#define PDS_CR_PDS_BZ_RESET_UMSK         (~(((1U << PDS_CR_PDS_BZ_RESET_LEN) - 1) << PDS_CR_PDS_BZ_RESET_POS))
+#define PDS_CR_PDS_BZ_MEM_STBY           PDS_CR_PDS_BZ_MEM_STBY
+#define PDS_CR_PDS_BZ_MEM_STBY_POS       (14U)
+#define PDS_CR_PDS_BZ_MEM_STBY_LEN       (1U)
+#define PDS_CR_PDS_BZ_MEM_STBY_MSK       (((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS)
+#define PDS_CR_PDS_BZ_MEM_STBY_UMSK      (~(((1U << PDS_CR_PDS_BZ_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BZ_MEM_STBY_POS))
+#define PDS_CR_PDS_BZ_GATE_CLK           PDS_CR_PDS_BZ_GATE_CLK
+#define PDS_CR_PDS_BZ_GATE_CLK_POS       (15U)
+#define PDS_CR_PDS_BZ_GATE_CLK_LEN       (1U)
+#define PDS_CR_PDS_BZ_GATE_CLK_MSK       (((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS)
+#define PDS_CR_PDS_BZ_GATE_CLK_UMSK      (~(((1U << PDS_CR_PDS_BZ_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BZ_GATE_CLK_POS))
+#define PDS_CR_PDS_BLE_PWR_OFF           PDS_CR_PDS_BLE_PWR_OFF
+#define PDS_CR_PDS_BLE_PWR_OFF_POS       (16U)
+#define PDS_CR_PDS_BLE_PWR_OFF_LEN       (1U)
+#define PDS_CR_PDS_BLE_PWR_OFF_MSK       (((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS)
+#define PDS_CR_PDS_BLE_PWR_OFF_UMSK      (~(((1U << PDS_CR_PDS_BLE_PWR_OFF_LEN) - 1) << PDS_CR_PDS_BLE_PWR_OFF_POS))
+#define PDS_CR_PDS_BLE_RESET             PDS_CR_PDS_BLE_RESET
+#define PDS_CR_PDS_BLE_RESET_POS         (17U)
+#define PDS_CR_PDS_BLE_RESET_LEN         (1U)
+#define PDS_CR_PDS_BLE_RESET_MSK         (((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS)
+#define PDS_CR_PDS_BLE_RESET_UMSK        (~(((1U << PDS_CR_PDS_BLE_RESET_LEN) - 1) << PDS_CR_PDS_BLE_RESET_POS))
+#define PDS_CR_PDS_BLE_MEM_STBY          PDS_CR_PDS_BLE_MEM_STBY
+#define PDS_CR_PDS_BLE_MEM_STBY_POS      (18U)
+#define PDS_CR_PDS_BLE_MEM_STBY_LEN      (1U)
+#define PDS_CR_PDS_BLE_MEM_STBY_MSK      (((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS)
+#define PDS_CR_PDS_BLE_MEM_STBY_UMSK     (~(((1U << PDS_CR_PDS_BLE_MEM_STBY_LEN) - 1) << PDS_CR_PDS_BLE_MEM_STBY_POS))
+#define PDS_CR_PDS_BLE_GATE_CLK          PDS_CR_PDS_BLE_GATE_CLK
+#define PDS_CR_PDS_BLE_GATE_CLK_POS      (19U)
+#define PDS_CR_PDS_BLE_GATE_CLK_LEN      (1U)
+#define PDS_CR_PDS_BLE_GATE_CLK_MSK      (((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS)
+#define PDS_CR_PDS_BLE_GATE_CLK_UMSK     (~(((1U << PDS_CR_PDS_BLE_GATE_CLK_LEN) - 1) << PDS_CR_PDS_BLE_GATE_CLK_POS))
+#define PDS_CR_PDS_USB_PWR_OFF           PDS_CR_PDS_USB_PWR_OFF
+#define PDS_CR_PDS_USB_PWR_OFF_POS       (20U)
+#define PDS_CR_PDS_USB_PWR_OFF_LEN       (1U)
+#define PDS_CR_PDS_USB_PWR_OFF_MSK       (((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS)
+#define PDS_CR_PDS_USB_PWR_OFF_UMSK      (~(((1U << PDS_CR_PDS_USB_PWR_OFF_LEN) - 1) << PDS_CR_PDS_USB_PWR_OFF_POS))
+#define PDS_CR_PDS_USB_RESET             PDS_CR_PDS_USB_RESET
+#define PDS_CR_PDS_USB_RESET_POS         (21U)
+#define PDS_CR_PDS_USB_RESET_LEN         (1U)
+#define PDS_CR_PDS_USB_RESET_MSK         (((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS)
+#define PDS_CR_PDS_USB_RESET_UMSK        (~(((1U << PDS_CR_PDS_USB_RESET_LEN) - 1) << PDS_CR_PDS_USB_RESET_POS))
+#define PDS_CR_PDS_USB_MEM_STBY          PDS_CR_PDS_USB_MEM_STBY
+#define PDS_CR_PDS_USB_MEM_STBY_POS      (22U)
+#define PDS_CR_PDS_USB_MEM_STBY_LEN      (1U)
+#define PDS_CR_PDS_USB_MEM_STBY_MSK      (((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS)
+#define PDS_CR_PDS_USB_MEM_STBY_UMSK     (~(((1U << PDS_CR_PDS_USB_MEM_STBY_LEN) - 1) << PDS_CR_PDS_USB_MEM_STBY_POS))
+#define PDS_CR_PDS_USB_GATE_CLK          PDS_CR_PDS_USB_GATE_CLK
+#define PDS_CR_PDS_USB_GATE_CLK_POS      (23U)
+#define PDS_CR_PDS_USB_GATE_CLK_LEN      (1U)
+#define PDS_CR_PDS_USB_GATE_CLK_MSK      (((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS)
+#define PDS_CR_PDS_USB_GATE_CLK_UMSK     (~(((1U << PDS_CR_PDS_USB_GATE_CLK_LEN) - 1) << PDS_CR_PDS_USB_GATE_CLK_POS))
+#define PDS_CR_PDS_MISC_PWR_OFF          PDS_CR_PDS_MISC_PWR_OFF
+#define PDS_CR_PDS_MISC_PWR_OFF_POS      (24U)
+#define PDS_CR_PDS_MISC_PWR_OFF_LEN      (1U)
+#define PDS_CR_PDS_MISC_PWR_OFF_MSK      (((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_PWR_OFF_UMSK     (~(((1U << PDS_CR_PDS_MISC_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_PWR_OFF_POS))
+#define PDS_CR_PDS_MISC_RESET            PDS_CR_PDS_MISC_RESET
+#define PDS_CR_PDS_MISC_RESET_POS        (25U)
+#define PDS_CR_PDS_MISC_RESET_LEN        (1U)
+#define PDS_CR_PDS_MISC_RESET_MSK        (((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS)
+#define PDS_CR_PDS_MISC_RESET_UMSK       (~(((1U << PDS_CR_PDS_MISC_RESET_LEN) - 1) << PDS_CR_PDS_MISC_RESET_POS))
+#define PDS_CR_PDS_MISC_MEM_STBY         PDS_CR_PDS_MISC_MEM_STBY
+#define PDS_CR_PDS_MISC_MEM_STBY_POS     (26U)
+#define PDS_CR_PDS_MISC_MEM_STBY_LEN     (1U)
+#define PDS_CR_PDS_MISC_MEM_STBY_MSK     (((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS)
+#define PDS_CR_PDS_MISC_MEM_STBY_UMSK    (~(((1U << PDS_CR_PDS_MISC_MEM_STBY_LEN) - 1) << PDS_CR_PDS_MISC_MEM_STBY_POS))
+#define PDS_CR_PDS_MISC_GATE_CLK         PDS_CR_PDS_MISC_GATE_CLK
+#define PDS_CR_PDS_MISC_GATE_CLK_POS     (27U)
+#define PDS_CR_PDS_MISC_GATE_CLK_LEN     (1U)
+#define PDS_CR_PDS_MISC_GATE_CLK_MSK     (((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS)
+#define PDS_CR_PDS_MISC_GATE_CLK_UMSK    (~(((1U << PDS_CR_PDS_MISC_GATE_CLK_LEN) - 1) << PDS_CR_PDS_MISC_GATE_CLK_POS))
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF      PDS_CR_PDS_MISC_ANA_PWR_OFF
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_POS  (30U)
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN  (1U)
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_MSK  (((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_ANA_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_ANA_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_ANA_PWR_OFF_POS))
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF      PDS_CR_PDS_MISC_DIG_PWR_OFF
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_POS  (31U)
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN  (1U)
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_MSK  (((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS)
+#define PDS_CR_PDS_MISC_DIG_PWR_OFF_UMSK (~(((1U << PDS_CR_PDS_MISC_DIG_PWR_OFF_LEN) - 1) << PDS_CR_PDS_MISC_DIG_PWR_OFF_POS))
+
+/* 0x1C : pds_stat */
+#define PDS_STAT_OFFSET           (0x1C)
+#define PDS_RO_PDS_STATE          PDS_RO_PDS_STATE
+#define PDS_RO_PDS_STATE_POS      (0U)
+#define PDS_RO_PDS_STATE_LEN      (4U)
+#define PDS_RO_PDS_STATE_MSK      (((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS)
+#define PDS_RO_PDS_STATE_UMSK     (~(((1U << PDS_RO_PDS_STATE_LEN) - 1) << PDS_RO_PDS_STATE_POS))
+#define PDS_RO_PDS_RF_STATE       PDS_RO_PDS_RF_STATE
+#define PDS_RO_PDS_RF_STATE_POS   (8U)
+#define PDS_RO_PDS_RF_STATE_LEN   (4U)
+#define PDS_RO_PDS_RF_STATE_MSK   (((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS)
+#define PDS_RO_PDS_RF_STATE_UMSK  (~(((1U << PDS_RO_PDS_RF_STATE_LEN) - 1) << PDS_RO_PDS_RF_STATE_POS))
+#define PDS_RO_PDS_PLL_STATE      PDS_RO_PDS_PLL_STATE
+#define PDS_RO_PDS_PLL_STATE_POS  (16U)
+#define PDS_RO_PDS_PLL_STATE_LEN  (2U)
+#define PDS_RO_PDS_PLL_STATE_MSK  (((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS)
+#define PDS_RO_PDS_PLL_STATE_UMSK (~(((1U << PDS_RO_PDS_PLL_STATE_LEN) - 1) << PDS_RO_PDS_PLL_STATE_POS))
+
+/* 0x20 : pds_ram1 */
+#define PDS_RAM1_OFFSET           (0x20)
+#define PDS_CR_PDS_RAM_RET1N      PDS_CR_PDS_RAM_RET1N
+#define PDS_CR_PDS_RAM_RET1N_POS  (0U)
+#define PDS_CR_PDS_RAM_RET1N_LEN  (4U)
+#define PDS_CR_PDS_RAM_RET1N_MSK  (((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS)
+#define PDS_CR_PDS_RAM_RET1N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET1N_LEN) - 1) << PDS_CR_PDS_RAM_RET1N_POS))
+#define PDS_CR_PDS_RAM_RET2N      PDS_CR_PDS_RAM_RET2N
+#define PDS_CR_PDS_RAM_RET2N_POS  (4U)
+#define PDS_CR_PDS_RAM_RET2N_LEN  (4U)
+#define PDS_CR_PDS_RAM_RET2N_MSK  (((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS)
+#define PDS_CR_PDS_RAM_RET2N_UMSK (~(((1U << PDS_CR_PDS_RAM_RET2N_LEN) - 1) << PDS_CR_PDS_RAM_RET2N_POS))
+#define PDS_CR_PDS_RAM_PGEN       PDS_CR_PDS_RAM_PGEN
+#define PDS_CR_PDS_RAM_PGEN_POS   (8U)
+#define PDS_CR_PDS_RAM_PGEN_LEN   (4U)
+#define PDS_CR_PDS_RAM_PGEN_MSK   (((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS)
+#define PDS_CR_PDS_RAM_PGEN_UMSK  (~(((1U << PDS_CR_PDS_RAM_PGEN_LEN) - 1) << PDS_CR_PDS_RAM_PGEN_POS))
+
+/* 0x30 : pds_gpio_set_pu_pd */
+#define PDS_GPIO_SET_PU_PD_OFFSET     (0x30)
+#define PDS_CR_PDS_GPIO_22_17_PD      PDS_CR_PDS_GPIO_22_17_PD
+#define PDS_CR_PDS_GPIO_22_17_PD_POS  (0U)
+#define PDS_CR_PDS_GPIO_22_17_PD_LEN  (6U)
+#define PDS_CR_PDS_GPIO_22_17_PD_MSK  (((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS)
+#define PDS_CR_PDS_GPIO_22_17_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PD_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PD_POS))
+#define PDS_CR_PDS_GPIO_22_17_PU      PDS_CR_PDS_GPIO_22_17_PU
+#define PDS_CR_PDS_GPIO_22_17_PU_POS  (8U)
+#define PDS_CR_PDS_GPIO_22_17_PU_LEN  (6U)
+#define PDS_CR_PDS_GPIO_22_17_PU_MSK  (((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS)
+#define PDS_CR_PDS_GPIO_22_17_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_22_17_PU_LEN) - 1) << PDS_CR_PDS_GPIO_22_17_PU_POS))
+#define PDS_CR_PDS_GPIO_28_23_PD      PDS_CR_PDS_GPIO_28_23_PD
+#define PDS_CR_PDS_GPIO_28_23_PD_POS  (16U)
+#define PDS_CR_PDS_GPIO_28_23_PD_LEN  (6U)
+#define PDS_CR_PDS_GPIO_28_23_PD_MSK  (((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS)
+#define PDS_CR_PDS_GPIO_28_23_PD_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PD_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PD_POS))
+#define PDS_CR_PDS_GPIO_28_23_PU      PDS_CR_PDS_GPIO_28_23_PU
+#define PDS_CR_PDS_GPIO_28_23_PU_POS  (24U)
+#define PDS_CR_PDS_GPIO_28_23_PU_LEN  (6U)
+#define PDS_CR_PDS_GPIO_28_23_PU_MSK  (((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS)
+#define PDS_CR_PDS_GPIO_28_23_PU_UMSK (~(((1U << PDS_CR_PDS_GPIO_28_23_PU_LEN) - 1) << PDS_CR_PDS_GPIO_28_23_PU_POS))
+
+/* 0x40 : pds_gpio_int */
+#define PDS_GPIO_INT_OFFSET      (0x40)
+#define PDS_GPIO_INT_MASK        PDS_GPIO_INT_MASK
+#define PDS_GPIO_INT_MASK_POS    (0U)
+#define PDS_GPIO_INT_MASK_LEN    (1U)
+#define PDS_GPIO_INT_MASK_MSK    (((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS)
+#define PDS_GPIO_INT_MASK_UMSK   (~(((1U << PDS_GPIO_INT_MASK_LEN) - 1) << PDS_GPIO_INT_MASK_POS))
+#define PDS_GPIO_INT_STAT        PDS_GPIO_INT_STAT
+#define PDS_GPIO_INT_STAT_POS    (1U)
+#define PDS_GPIO_INT_STAT_LEN    (1U)
+#define PDS_GPIO_INT_STAT_MSK    (((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS)
+#define PDS_GPIO_INT_STAT_UMSK   (~(((1U << PDS_GPIO_INT_STAT_LEN) - 1) << PDS_GPIO_INT_STAT_POS))
+#define PDS_GPIO_INT_CLR         PDS_GPIO_INT_CLR
+#define PDS_GPIO_INT_CLR_POS     (2U)
+#define PDS_GPIO_INT_CLR_LEN     (1U)
+#define PDS_GPIO_INT_CLR_MSK     (((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS)
+#define PDS_GPIO_INT_CLR_UMSK    (~(((1U << PDS_GPIO_INT_CLR_LEN) - 1) << PDS_GPIO_INT_CLR_POS))
+#define PDS_GPIO_INT_MODE        PDS_GPIO_INT_MODE
+#define PDS_GPIO_INT_MODE_POS    (4U)
+#define PDS_GPIO_INT_MODE_LEN    (3U)
+#define PDS_GPIO_INT_MODE_MSK    (((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS)
+#define PDS_GPIO_INT_MODE_UMSK   (~(((1U << PDS_GPIO_INT_MODE_LEN) - 1) << PDS_GPIO_INT_MODE_POS))
+#define PDS_GPIO_INT_SELECT      PDS_GPIO_INT_SELECT
+#define PDS_GPIO_INT_SELECT_POS  (8U)
+#define PDS_GPIO_INT_SELECT_LEN  (3U)
+#define PDS_GPIO_INT_SELECT_MSK  (((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS)
+#define PDS_GPIO_INT_SELECT_UMSK (~(((1U << PDS_GPIO_INT_SELECT_LEN) - 1) << PDS_GPIO_INT_SELECT_POS))
+
+/* 0x300 : rc32m_ctrl0 */
+#define PDS_RC32M_CTRL0_OFFSET         (0x300)
+#define PDS_RC32M_CAL_DONE             PDS_RC32M_CAL_DONE
+#define PDS_RC32M_CAL_DONE_POS         (0U)
+#define PDS_RC32M_CAL_DONE_LEN         (1U)
+#define PDS_RC32M_CAL_DONE_MSK         (((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS)
+#define PDS_RC32M_CAL_DONE_UMSK        (~(((1U << PDS_RC32M_CAL_DONE_LEN) - 1) << PDS_RC32M_CAL_DONE_POS))
+#define PDS_RC32M_RDY                  PDS_RC32M_RDY
+#define PDS_RC32M_RDY_POS              (1U)
+#define PDS_RC32M_RDY_LEN              (1U)
+#define PDS_RC32M_RDY_MSK              (((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS)
+#define PDS_RC32M_RDY_UMSK             (~(((1U << PDS_RC32M_RDY_LEN) - 1) << PDS_RC32M_RDY_POS))
+#define PDS_RC32M_CAL_INPROGRESS       PDS_RC32M_CAL_INPROGRESS
+#define PDS_RC32M_CAL_INPROGRESS_POS   (2U)
+#define PDS_RC32M_CAL_INPROGRESS_LEN   (1U)
+#define PDS_RC32M_CAL_INPROGRESS_MSK   (((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS)
+#define PDS_RC32M_CAL_INPROGRESS_UMSK  (~(((1U << PDS_RC32M_CAL_INPROGRESS_LEN) - 1) << PDS_RC32M_CAL_INPROGRESS_POS))
+#define PDS_RC32M_CAL_DIV              PDS_RC32M_CAL_DIV
+#define PDS_RC32M_CAL_DIV_POS          (3U)
+#define PDS_RC32M_CAL_DIV_LEN          (2U)
+#define PDS_RC32M_CAL_DIV_MSK          (((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS)
+#define PDS_RC32M_CAL_DIV_UMSK         (~(((1U << PDS_RC32M_CAL_DIV_LEN) - 1) << PDS_RC32M_CAL_DIV_POS))
+#define PDS_RC32M_CAL_PRECHARGE        PDS_RC32M_CAL_PRECHARGE
+#define PDS_RC32M_CAL_PRECHARGE_POS    (5U)
+#define PDS_RC32M_CAL_PRECHARGE_LEN    (1U)
+#define PDS_RC32M_CAL_PRECHARGE_MSK    (((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS)
+#define PDS_RC32M_CAL_PRECHARGE_UMSK   (~(((1U << PDS_RC32M_CAL_PRECHARGE_LEN) - 1) << PDS_RC32M_CAL_PRECHARGE_POS))
+#define PDS_RC32M_DIG_CODE_FR_CAL      PDS_RC32M_DIG_CODE_FR_CAL
+#define PDS_RC32M_DIG_CODE_FR_CAL_POS  (6U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_LEN  (8U)
+#define PDS_RC32M_DIG_CODE_FR_CAL_MSK  (((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS)
+#define PDS_RC32M_DIG_CODE_FR_CAL_UMSK (~(((1U << PDS_RC32M_DIG_CODE_FR_CAL_LEN) - 1) << PDS_RC32M_DIG_CODE_FR_CAL_POS))
+#define PDS_RC32M_ALLOW_CAL            PDS_RC32M_ALLOW_CAL
+#define PDS_RC32M_ALLOW_CAL_POS        (17U)
+#define PDS_RC32M_ALLOW_CAL_LEN        (1U)
+#define PDS_RC32M_ALLOW_CAL_MSK        (((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS)
+#define PDS_RC32M_ALLOW_CAL_UMSK       (~(((1U << PDS_RC32M_ALLOW_CAL_LEN) - 1) << PDS_RC32M_ALLOW_CAL_POS))
+#define PDS_RC32M_REFCLK_HALF          PDS_RC32M_REFCLK_HALF
+#define PDS_RC32M_REFCLK_HALF_POS      (18U)
+#define PDS_RC32M_REFCLK_HALF_LEN      (1U)
+#define PDS_RC32M_REFCLK_HALF_MSK      (((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS)
+#define PDS_RC32M_REFCLK_HALF_UMSK     (~(((1U << PDS_RC32M_REFCLK_HALF_LEN) - 1) << PDS_RC32M_REFCLK_HALF_POS))
+#define PDS_RC32M_EXT_CODE_EN          PDS_RC32M_EXT_CODE_EN
+#define PDS_RC32M_EXT_CODE_EN_POS      (19U)
+#define PDS_RC32M_EXT_CODE_EN_LEN      (1U)
+#define PDS_RC32M_EXT_CODE_EN_MSK      (((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS)
+#define PDS_RC32M_EXT_CODE_EN_UMSK     (~(((1U << PDS_RC32M_EXT_CODE_EN_LEN) - 1) << PDS_RC32M_EXT_CODE_EN_POS))
+#define PDS_RC32M_CAL_EN               PDS_RC32M_CAL_EN
+#define PDS_RC32M_CAL_EN_POS           (20U)
+#define PDS_RC32M_CAL_EN_LEN           (1U)
+#define PDS_RC32M_CAL_EN_MSK           (((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS)
+#define PDS_RC32M_CAL_EN_UMSK          (~(((1U << PDS_RC32M_CAL_EN_LEN) - 1) << PDS_RC32M_CAL_EN_POS))
+#define PDS_RC32M_PD                   PDS_RC32M_PD
+#define PDS_RC32M_PD_POS               (21U)
+#define PDS_RC32M_PD_LEN               (1U)
+#define PDS_RC32M_PD_MSK               (((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS)
+#define PDS_RC32M_PD_UMSK              (~(((1U << PDS_RC32M_PD_LEN) - 1) << PDS_RC32M_PD_POS))
+#define PDS_RC32M_CODE_FR_EXT          PDS_RC32M_CODE_FR_EXT
+#define PDS_RC32M_CODE_FR_EXT_POS      (22U)
+#define PDS_RC32M_CODE_FR_EXT_LEN      (8U)
+#define PDS_RC32M_CODE_FR_EXT_MSK      (((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS)
+#define PDS_RC32M_CODE_FR_EXT_UMSK     (~(((1U << PDS_RC32M_CODE_FR_EXT_LEN) - 1) << PDS_RC32M_CODE_FR_EXT_POS))
+
+/* 0x304 : rc32m_ctrl1 */
+#define PDS_RC32M_CTRL1_OFFSET      (0x304)
+#define PDS_RC32M_TEST_EN           PDS_RC32M_TEST_EN
+#define PDS_RC32M_TEST_EN_POS       (0U)
+#define PDS_RC32M_TEST_EN_LEN       (1U)
+#define PDS_RC32M_TEST_EN_MSK       (((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS)
+#define PDS_RC32M_TEST_EN_UMSK      (~(((1U << PDS_RC32M_TEST_EN_LEN) - 1) << PDS_RC32M_TEST_EN_POS))
+#define PDS_RC32M_SOFT_RST          PDS_RC32M_SOFT_RST
+#define PDS_RC32M_SOFT_RST_POS      (1U)
+#define PDS_RC32M_SOFT_RST_LEN      (1U)
+#define PDS_RC32M_SOFT_RST_MSK      (((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS)
+#define PDS_RC32M_SOFT_RST_UMSK     (~(((1U << PDS_RC32M_SOFT_RST_LEN) - 1) << PDS_RC32M_SOFT_RST_POS))
+#define PDS_RC32M_CLK_SOFT_RST      PDS_RC32M_CLK_SOFT_RST
+#define PDS_RC32M_CLK_SOFT_RST_POS  (2U)
+#define PDS_RC32M_CLK_SOFT_RST_LEN  (1U)
+#define PDS_RC32M_CLK_SOFT_RST_MSK  (((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS)
+#define PDS_RC32M_CLK_SOFT_RST_UMSK (~(((1U << PDS_RC32M_CLK_SOFT_RST_LEN) - 1) << PDS_RC32M_CLK_SOFT_RST_POS))
+#define PDS_RC32M_CLK_INV           PDS_RC32M_CLK_INV
+#define PDS_RC32M_CLK_INV_POS       (3U)
+#define PDS_RC32M_CLK_INV_LEN       (1U)
+#define PDS_RC32M_CLK_INV_MSK       (((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS)
+#define PDS_RC32M_CLK_INV_UMSK      (~(((1U << PDS_RC32M_CLK_INV_LEN) - 1) << PDS_RC32M_CLK_INV_POS))
+#define PDS_RC32M_CLK_FORCE_ON      PDS_RC32M_CLK_FORCE_ON
+#define PDS_RC32M_CLK_FORCE_ON_POS  (4U)
+#define PDS_RC32M_CLK_FORCE_ON_LEN  (1U)
+#define PDS_RC32M_CLK_FORCE_ON_MSK  (((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS)
+#define PDS_RC32M_CLK_FORCE_ON_UMSK (~(((1U << PDS_RC32M_CLK_FORCE_ON_LEN) - 1) << PDS_RC32M_CLK_FORCE_ON_POS))
+#define PDS_RC32M_RESERVED          PDS_RC32M_RESERVED
+#define PDS_RC32M_RESERVED_POS      (24U)
+#define PDS_RC32M_RESERVED_LEN      (8U)
+#define PDS_RC32M_RESERVED_MSK      (((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS)
+#define PDS_RC32M_RESERVED_UMSK     (~(((1U << PDS_RC32M_RESERVED_LEN) - 1) << PDS_RC32M_RESERVED_POS))
+
+/* 0x400 : pu_rst_clkpll */
+#define PDS_PU_RST_CLKPLL_OFFSET      (0x400)
+#define PDS_CLKPLL_SDM_RESET          PDS_CLKPLL_SDM_RESET
+#define PDS_CLKPLL_SDM_RESET_POS      (0U)
+#define PDS_CLKPLL_SDM_RESET_LEN      (1U)
+#define PDS_CLKPLL_SDM_RESET_MSK      (((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS)
+#define PDS_CLKPLL_SDM_RESET_UMSK     (~(((1U << PDS_CLKPLL_SDM_RESET_LEN) - 1) << PDS_CLKPLL_SDM_RESET_POS))
+#define PDS_CLKPLL_RESET_POSTDIV      PDS_CLKPLL_RESET_POSTDIV
+#define PDS_CLKPLL_RESET_POSTDIV_POS  (1U)
+#define PDS_CLKPLL_RESET_POSTDIV_LEN  (1U)
+#define PDS_CLKPLL_RESET_POSTDIV_MSK  (((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS)
+#define PDS_CLKPLL_RESET_POSTDIV_UMSK (~(((1U << PDS_CLKPLL_RESET_POSTDIV_LEN) - 1) << PDS_CLKPLL_RESET_POSTDIV_POS))
+#define PDS_CLKPLL_RESET_FBDV         PDS_CLKPLL_RESET_FBDV
+#define PDS_CLKPLL_RESET_FBDV_POS     (2U)
+#define PDS_CLKPLL_RESET_FBDV_LEN     (1U)
+#define PDS_CLKPLL_RESET_FBDV_MSK     (((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS)
+#define PDS_CLKPLL_RESET_FBDV_UMSK    (~(((1U << PDS_CLKPLL_RESET_FBDV_LEN) - 1) << PDS_CLKPLL_RESET_FBDV_POS))
+#define PDS_CLKPLL_RESET_REFDIV       PDS_CLKPLL_RESET_REFDIV
+#define PDS_CLKPLL_RESET_REFDIV_POS   (3U)
+#define PDS_CLKPLL_RESET_REFDIV_LEN   (1U)
+#define PDS_CLKPLL_RESET_REFDIV_MSK   (((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS)
+#define PDS_CLKPLL_RESET_REFDIV_UMSK  (~(((1U << PDS_CLKPLL_RESET_REFDIV_LEN) - 1) << PDS_CLKPLL_RESET_REFDIV_POS))
+#define PDS_CLKPLL_PU_POSTDIV         PDS_CLKPLL_PU_POSTDIV
+#define PDS_CLKPLL_PU_POSTDIV_POS     (4U)
+#define PDS_CLKPLL_PU_POSTDIV_LEN     (1U)
+#define PDS_CLKPLL_PU_POSTDIV_MSK     (((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS)
+#define PDS_CLKPLL_PU_POSTDIV_UMSK    (~(((1U << PDS_CLKPLL_PU_POSTDIV_LEN) - 1) << PDS_CLKPLL_PU_POSTDIV_POS))
+#define PDS_CLKPLL_PU_FBDV            PDS_CLKPLL_PU_FBDV
+#define PDS_CLKPLL_PU_FBDV_POS        (5U)
+#define PDS_CLKPLL_PU_FBDV_LEN        (1U)
+#define PDS_CLKPLL_PU_FBDV_MSK        (((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS)
+#define PDS_CLKPLL_PU_FBDV_UMSK       (~(((1U << PDS_CLKPLL_PU_FBDV_LEN) - 1) << PDS_CLKPLL_PU_FBDV_POS))
+#define PDS_CLKPLL_PU_CLAMP_OP        PDS_CLKPLL_PU_CLAMP_OP
+#define PDS_CLKPLL_PU_CLAMP_OP_POS    (6U)
+#define PDS_CLKPLL_PU_CLAMP_OP_LEN    (1U)
+#define PDS_CLKPLL_PU_CLAMP_OP_MSK    (((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS)
+#define PDS_CLKPLL_PU_CLAMP_OP_UMSK   (~(((1U << PDS_CLKPLL_PU_CLAMP_OP_LEN) - 1) << PDS_CLKPLL_PU_CLAMP_OP_POS))
+#define PDS_CLKPLL_PU_PFD             PDS_CLKPLL_PU_PFD
+#define PDS_CLKPLL_PU_PFD_POS         (7U)
+#define PDS_CLKPLL_PU_PFD_LEN         (1U)
+#define PDS_CLKPLL_PU_PFD_MSK         (((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS)
+#define PDS_CLKPLL_PU_PFD_UMSK        (~(((1U << PDS_CLKPLL_PU_PFD_LEN) - 1) << PDS_CLKPLL_PU_PFD_POS))
+#define PDS_CLKPLL_PU_CP              PDS_CLKPLL_PU_CP
+#define PDS_CLKPLL_PU_CP_POS          (8U)
+#define PDS_CLKPLL_PU_CP_LEN          (1U)
+#define PDS_CLKPLL_PU_CP_MSK          (((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS)
+#define PDS_CLKPLL_PU_CP_UMSK         (~(((1U << PDS_CLKPLL_PU_CP_LEN) - 1) << PDS_CLKPLL_PU_CP_POS))
+#define PDS_PU_CLKPLL_SFREG           PDS_PU_CLKPLL_SFREG
+#define PDS_PU_CLKPLL_SFREG_POS       (9U)
+#define PDS_PU_CLKPLL_SFREG_LEN       (1U)
+#define PDS_PU_CLKPLL_SFREG_MSK       (((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS)
+#define PDS_PU_CLKPLL_SFREG_UMSK      (~(((1U << PDS_PU_CLKPLL_SFREG_LEN) - 1) << PDS_PU_CLKPLL_SFREG_POS))
+#define PDS_PU_CLKPLL                 PDS_PU_CLKPLL
+#define PDS_PU_CLKPLL_POS             (10U)
+#define PDS_PU_CLKPLL_LEN             (1U)
+#define PDS_PU_CLKPLL_MSK             (((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS)
+#define PDS_PU_CLKPLL_UMSK            (~(((1U << PDS_PU_CLKPLL_LEN) - 1) << PDS_PU_CLKPLL_POS))
+
+/* 0x404 : clkpll_top_ctrl */
+#define PDS_CLKPLL_TOP_CTRL_OFFSET     (0x404)
+#define PDS_CLKPLL_POSTDIV             PDS_CLKPLL_POSTDIV
+#define PDS_CLKPLL_POSTDIV_POS         (0U)
+#define PDS_CLKPLL_POSTDIV_LEN         (7U)
+#define PDS_CLKPLL_POSTDIV_MSK         (((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS)
+#define PDS_CLKPLL_POSTDIV_UMSK        (~(((1U << PDS_CLKPLL_POSTDIV_LEN) - 1) << PDS_CLKPLL_POSTDIV_POS))
+#define PDS_CLKPLL_REFDIV_RATIO        PDS_CLKPLL_REFDIV_RATIO
+#define PDS_CLKPLL_REFDIV_RATIO_POS    (8U)
+#define PDS_CLKPLL_REFDIV_RATIO_LEN    (4U)
+#define PDS_CLKPLL_REFDIV_RATIO_MSK    (((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS)
+#define PDS_CLKPLL_REFDIV_RATIO_UMSK   (~(((1U << PDS_CLKPLL_REFDIV_RATIO_LEN) - 1) << PDS_CLKPLL_REFDIV_RATIO_POS))
+#define PDS_CLKPLL_XTAL_RC32M_SEL      PDS_CLKPLL_XTAL_RC32M_SEL
+#define PDS_CLKPLL_XTAL_RC32M_SEL_POS  (12U)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_LEN  (1U)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_MSK  (((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS)
+#define PDS_CLKPLL_XTAL_RC32M_SEL_UMSK (~(((1U << PDS_CLKPLL_XTAL_RC32M_SEL_LEN) - 1) << PDS_CLKPLL_XTAL_RC32M_SEL_POS))
+#define PDS_CLKPLL_REFCLK_SEL          PDS_CLKPLL_REFCLK_SEL
+#define PDS_CLKPLL_REFCLK_SEL_POS      (16U)
+#define PDS_CLKPLL_REFCLK_SEL_LEN      (1U)
+#define PDS_CLKPLL_REFCLK_SEL_MSK      (((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS)
+#define PDS_CLKPLL_REFCLK_SEL_UMSK     (~(((1U << PDS_CLKPLL_REFCLK_SEL_LEN) - 1) << PDS_CLKPLL_REFCLK_SEL_POS))
+#define PDS_CLKPLL_VG11_SEL            PDS_CLKPLL_VG11_SEL
+#define PDS_CLKPLL_VG11_SEL_POS        (20U)
+#define PDS_CLKPLL_VG11_SEL_LEN        (2U)
+#define PDS_CLKPLL_VG11_SEL_MSK        (((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS)
+#define PDS_CLKPLL_VG11_SEL_UMSK       (~(((1U << PDS_CLKPLL_VG11_SEL_LEN) - 1) << PDS_CLKPLL_VG11_SEL_POS))
+#define PDS_CLKPLL_RESV                PDS_CLKPLL_RESV
+#define PDS_CLKPLL_RESV_POS            (24U)
+#define PDS_CLKPLL_RESV_LEN            (2U)
+#define PDS_CLKPLL_RESV_MSK            (((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS)
+#define PDS_CLKPLL_RESV_UMSK           (~(((1U << PDS_CLKPLL_RESV_LEN) - 1) << PDS_CLKPLL_RESV_POS))
+
+/* 0x408 : clkpll_cp */
+#define PDS_CLKPLL_CP_OFFSET          (0x408)
+#define PDS_CLKPLL_SEL_CP_BIAS        PDS_CLKPLL_SEL_CP_BIAS
+#define PDS_CLKPLL_SEL_CP_BIAS_POS    (0U)
+#define PDS_CLKPLL_SEL_CP_BIAS_LEN    (1U)
+#define PDS_CLKPLL_SEL_CP_BIAS_MSK    (((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS)
+#define PDS_CLKPLL_SEL_CP_BIAS_UMSK   (~(((1U << PDS_CLKPLL_SEL_CP_BIAS_LEN) - 1) << PDS_CLKPLL_SEL_CP_BIAS_POS))
+#define PDS_CLKPLL_ICP_5U             PDS_CLKPLL_ICP_5U
+#define PDS_CLKPLL_ICP_5U_POS         (4U)
+#define PDS_CLKPLL_ICP_5U_LEN         (2U)
+#define PDS_CLKPLL_ICP_5U_MSK         (((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS)
+#define PDS_CLKPLL_ICP_5U_UMSK        (~(((1U << PDS_CLKPLL_ICP_5U_LEN) - 1) << PDS_CLKPLL_ICP_5U_POS))
+#define PDS_CLKPLL_ICP_1U             PDS_CLKPLL_ICP_1U
+#define PDS_CLKPLL_ICP_1U_POS         (6U)
+#define PDS_CLKPLL_ICP_1U_LEN         (2U)
+#define PDS_CLKPLL_ICP_1U_MSK         (((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS)
+#define PDS_CLKPLL_ICP_1U_UMSK        (~(((1U << PDS_CLKPLL_ICP_1U_LEN) - 1) << PDS_CLKPLL_ICP_1U_POS))
+#define PDS_CLKPLL_INT_FRAC_SW        PDS_CLKPLL_INT_FRAC_SW
+#define PDS_CLKPLL_INT_FRAC_SW_POS    (8U)
+#define PDS_CLKPLL_INT_FRAC_SW_LEN    (1U)
+#define PDS_CLKPLL_INT_FRAC_SW_MSK    (((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS)
+#define PDS_CLKPLL_INT_FRAC_SW_UMSK   (~(((1U << PDS_CLKPLL_INT_FRAC_SW_LEN) - 1) << PDS_CLKPLL_INT_FRAC_SW_POS))
+#define PDS_CLKPLL_CP_STARTUP_EN      PDS_CLKPLL_CP_STARTUP_EN
+#define PDS_CLKPLL_CP_STARTUP_EN_POS  (9U)
+#define PDS_CLKPLL_CP_STARTUP_EN_LEN  (1U)
+#define PDS_CLKPLL_CP_STARTUP_EN_MSK  (((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS)
+#define PDS_CLKPLL_CP_STARTUP_EN_UMSK (~(((1U << PDS_CLKPLL_CP_STARTUP_EN_LEN) - 1) << PDS_CLKPLL_CP_STARTUP_EN_POS))
+#define PDS_CLKPLL_CP_OPAMP_EN        PDS_CLKPLL_CP_OPAMP_EN
+#define PDS_CLKPLL_CP_OPAMP_EN_POS    (10U)
+#define PDS_CLKPLL_CP_OPAMP_EN_LEN    (1U)
+#define PDS_CLKPLL_CP_OPAMP_EN_MSK    (((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS)
+#define PDS_CLKPLL_CP_OPAMP_EN_UMSK   (~(((1U << PDS_CLKPLL_CP_OPAMP_EN_LEN) - 1) << PDS_CLKPLL_CP_OPAMP_EN_POS))
+
+/* 0x40C : clkpll_rz */
+#define PDS_CLKPLL_RZ_OFFSET     (0x40C)
+#define PDS_CLKPLL_C4_EN         PDS_CLKPLL_C4_EN
+#define PDS_CLKPLL_C4_EN_POS     (0U)
+#define PDS_CLKPLL_C4_EN_LEN     (1U)
+#define PDS_CLKPLL_C4_EN_MSK     (((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS)
+#define PDS_CLKPLL_C4_EN_UMSK    (~(((1U << PDS_CLKPLL_C4_EN_LEN) - 1) << PDS_CLKPLL_C4_EN_POS))
+#define PDS_CLKPLL_R4            PDS_CLKPLL_R4
+#define PDS_CLKPLL_R4_POS        (4U)
+#define PDS_CLKPLL_R4_LEN        (2U)
+#define PDS_CLKPLL_R4_MSK        (((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS)
+#define PDS_CLKPLL_R4_UMSK       (~(((1U << PDS_CLKPLL_R4_LEN) - 1) << PDS_CLKPLL_R4_POS))
+#define PDS_CLKPLL_R4_SHORT      PDS_CLKPLL_R4_SHORT
+#define PDS_CLKPLL_R4_SHORT_POS  (8U)
+#define PDS_CLKPLL_R4_SHORT_LEN  (1U)
+#define PDS_CLKPLL_R4_SHORT_MSK  (((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS)
+#define PDS_CLKPLL_R4_SHORT_UMSK (~(((1U << PDS_CLKPLL_R4_SHORT_LEN) - 1) << PDS_CLKPLL_R4_SHORT_POS))
+#define PDS_CLKPLL_C3            PDS_CLKPLL_C3
+#define PDS_CLKPLL_C3_POS        (12U)
+#define PDS_CLKPLL_C3_LEN        (2U)
+#define PDS_CLKPLL_C3_MSK        (((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS)
+#define PDS_CLKPLL_C3_UMSK       (~(((1U << PDS_CLKPLL_C3_LEN) - 1) << PDS_CLKPLL_C3_POS))
+#define PDS_CLKPLL_CZ            PDS_CLKPLL_CZ
+#define PDS_CLKPLL_CZ_POS        (14U)
+#define PDS_CLKPLL_CZ_LEN        (2U)
+#define PDS_CLKPLL_CZ_MSK        (((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS)
+#define PDS_CLKPLL_CZ_UMSK       (~(((1U << PDS_CLKPLL_CZ_LEN) - 1) << PDS_CLKPLL_CZ_POS))
+#define PDS_CLKPLL_RZ            PDS_CLKPLL_RZ
+#define PDS_CLKPLL_RZ_POS        (16U)
+#define PDS_CLKPLL_RZ_LEN        (3U)
+#define PDS_CLKPLL_RZ_MSK        (((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS)
+#define PDS_CLKPLL_RZ_UMSK       (~(((1U << PDS_CLKPLL_RZ_LEN) - 1) << PDS_CLKPLL_RZ_POS))
+
+/* 0x410 : clkpll_fbdv */
+#define PDS_CLKPLL_FBDV_OFFSET         (0x410)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK      PDS_CLKPLL_SEL_SAMPLE_CLK
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_POS  (0U)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_LEN  (2U)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_MSK  (((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS)
+#define PDS_CLKPLL_SEL_SAMPLE_CLK_UMSK (~(((1U << PDS_CLKPLL_SEL_SAMPLE_CLK_LEN) - 1) << PDS_CLKPLL_SEL_SAMPLE_CLK_POS))
+#define PDS_CLKPLL_SEL_FB_CLK          PDS_CLKPLL_SEL_FB_CLK
+#define PDS_CLKPLL_SEL_FB_CLK_POS      (2U)
+#define PDS_CLKPLL_SEL_FB_CLK_LEN      (2U)
+#define PDS_CLKPLL_SEL_FB_CLK_MSK      (((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS)
+#define PDS_CLKPLL_SEL_FB_CLK_UMSK     (~(((1U << PDS_CLKPLL_SEL_FB_CLK_LEN) - 1) << PDS_CLKPLL_SEL_FB_CLK_POS))
+
+/* 0x414 : clkpll_vco */
+#define PDS_CLKPLL_VCO_OFFSET     (0x414)
+#define PDS_CLKPLL_VCO_SPEED      PDS_CLKPLL_VCO_SPEED
+#define PDS_CLKPLL_VCO_SPEED_POS  (0U)
+#define PDS_CLKPLL_VCO_SPEED_LEN  (3U)
+#define PDS_CLKPLL_VCO_SPEED_MSK  (((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS)
+#define PDS_CLKPLL_VCO_SPEED_UMSK (~(((1U << PDS_CLKPLL_VCO_SPEED_LEN) - 1) << PDS_CLKPLL_VCO_SPEED_POS))
+#define PDS_CLKPLL_SHRTR          PDS_CLKPLL_SHRTR
+#define PDS_CLKPLL_SHRTR_POS      (3U)
+#define PDS_CLKPLL_SHRTR_LEN      (1U)
+#define PDS_CLKPLL_SHRTR_MSK      (((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS)
+#define PDS_CLKPLL_SHRTR_UMSK     (~(((1U << PDS_CLKPLL_SHRTR_LEN) - 1) << PDS_CLKPLL_SHRTR_POS))
+
+/* 0x418 : clkpll_sdm */
+#define PDS_CLKPLL_SDM_OFFSET      (0x418)
+#define PDS_CLKPLL_SDMIN           PDS_CLKPLL_SDMIN
+#define PDS_CLKPLL_SDMIN_POS       (0U)
+#define PDS_CLKPLL_SDMIN_LEN       (24U)
+#define PDS_CLKPLL_SDMIN_MSK       (((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS)
+#define PDS_CLKPLL_SDMIN_UMSK      (~(((1U << PDS_CLKPLL_SDMIN_LEN) - 1) << PDS_CLKPLL_SDMIN_POS))
+#define PDS_CLKPLL_DITHER_SEL      PDS_CLKPLL_DITHER_SEL
+#define PDS_CLKPLL_DITHER_SEL_POS  (24U)
+#define PDS_CLKPLL_DITHER_SEL_LEN  (2U)
+#define PDS_CLKPLL_DITHER_SEL_MSK  (((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS)
+#define PDS_CLKPLL_DITHER_SEL_UMSK (~(((1U << PDS_CLKPLL_DITHER_SEL_LEN) - 1) << PDS_CLKPLL_DITHER_SEL_POS))
+#define PDS_CLKPLL_SDM_FLAG        PDS_CLKPLL_SDM_FLAG
+#define PDS_CLKPLL_SDM_FLAG_POS    (28U)
+#define PDS_CLKPLL_SDM_FLAG_LEN    (1U)
+#define PDS_CLKPLL_SDM_FLAG_MSK    (((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS)
+#define PDS_CLKPLL_SDM_FLAG_UMSK   (~(((1U << PDS_CLKPLL_SDM_FLAG_LEN) - 1) << PDS_CLKPLL_SDM_FLAG_POS))
+#define PDS_CLKPLL_SDM_BYPASS      PDS_CLKPLL_SDM_BYPASS
+#define PDS_CLKPLL_SDM_BYPASS_POS  (29U)
+#define PDS_CLKPLL_SDM_BYPASS_LEN  (1U)
+#define PDS_CLKPLL_SDM_BYPASS_MSK  (((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS)
+#define PDS_CLKPLL_SDM_BYPASS_UMSK (~(((1U << PDS_CLKPLL_SDM_BYPASS_LEN) - 1) << PDS_CLKPLL_SDM_BYPASS_POS))
+
+/* 0x41C : clkpll_output_en */
+#define PDS_CLKPLL_OUTPUT_EN_OFFSET  (0x41C)
+#define PDS_CLKPLL_EN_480M           PDS_CLKPLL_EN_480M
+#define PDS_CLKPLL_EN_480M_POS       (0U)
+#define PDS_CLKPLL_EN_480M_LEN       (1U)
+#define PDS_CLKPLL_EN_480M_MSK       (((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS)
+#define PDS_CLKPLL_EN_480M_UMSK      (~(((1U << PDS_CLKPLL_EN_480M_LEN) - 1) << PDS_CLKPLL_EN_480M_POS))
+#define PDS_CLKPLL_EN_240M           PDS_CLKPLL_EN_240M
+#define PDS_CLKPLL_EN_240M_POS       (1U)
+#define PDS_CLKPLL_EN_240M_LEN       (1U)
+#define PDS_CLKPLL_EN_240M_MSK       (((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS)
+#define PDS_CLKPLL_EN_240M_UMSK      (~(((1U << PDS_CLKPLL_EN_240M_LEN) - 1) << PDS_CLKPLL_EN_240M_POS))
+#define PDS_CLKPLL_EN_192M           PDS_CLKPLL_EN_192M
+#define PDS_CLKPLL_EN_192M_POS       (2U)
+#define PDS_CLKPLL_EN_192M_LEN       (1U)
+#define PDS_CLKPLL_EN_192M_MSK       (((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS)
+#define PDS_CLKPLL_EN_192M_UMSK      (~(((1U << PDS_CLKPLL_EN_192M_LEN) - 1) << PDS_CLKPLL_EN_192M_POS))
+#define PDS_CLKPLL_EN_160M           PDS_CLKPLL_EN_160M
+#define PDS_CLKPLL_EN_160M_POS       (3U)
+#define PDS_CLKPLL_EN_160M_LEN       (1U)
+#define PDS_CLKPLL_EN_160M_MSK       (((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS)
+#define PDS_CLKPLL_EN_160M_UMSK      (~(((1U << PDS_CLKPLL_EN_160M_LEN) - 1) << PDS_CLKPLL_EN_160M_POS))
+#define PDS_CLKPLL_EN_120M           PDS_CLKPLL_EN_120M
+#define PDS_CLKPLL_EN_120M_POS       (4U)
+#define PDS_CLKPLL_EN_120M_LEN       (1U)
+#define PDS_CLKPLL_EN_120M_MSK       (((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS)
+#define PDS_CLKPLL_EN_120M_UMSK      (~(((1U << PDS_CLKPLL_EN_120M_LEN) - 1) << PDS_CLKPLL_EN_120M_POS))
+#define PDS_CLKPLL_EN_96M            PDS_CLKPLL_EN_96M
+#define PDS_CLKPLL_EN_96M_POS        (5U)
+#define PDS_CLKPLL_EN_96M_LEN        (1U)
+#define PDS_CLKPLL_EN_96M_MSK        (((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS)
+#define PDS_CLKPLL_EN_96M_UMSK       (~(((1U << PDS_CLKPLL_EN_96M_LEN) - 1) << PDS_CLKPLL_EN_96M_POS))
+#define PDS_CLKPLL_EN_80M            PDS_CLKPLL_EN_80M
+#define PDS_CLKPLL_EN_80M_POS        (6U)
+#define PDS_CLKPLL_EN_80M_LEN        (1U)
+#define PDS_CLKPLL_EN_80M_MSK        (((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS)
+#define PDS_CLKPLL_EN_80M_UMSK       (~(((1U << PDS_CLKPLL_EN_80M_LEN) - 1) << PDS_CLKPLL_EN_80M_POS))
+#define PDS_CLKPLL_EN_48M            PDS_CLKPLL_EN_48M
+#define PDS_CLKPLL_EN_48M_POS        (7U)
+#define PDS_CLKPLL_EN_48M_LEN        (1U)
+#define PDS_CLKPLL_EN_48M_MSK        (((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS)
+#define PDS_CLKPLL_EN_48M_UMSK       (~(((1U << PDS_CLKPLL_EN_48M_LEN) - 1) << PDS_CLKPLL_EN_48M_POS))
+#define PDS_CLKPLL_EN_32M            PDS_CLKPLL_EN_32M
+#define PDS_CLKPLL_EN_32M_POS        (8U)
+#define PDS_CLKPLL_EN_32M_LEN        (1U)
+#define PDS_CLKPLL_EN_32M_MSK        (((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS)
+#define PDS_CLKPLL_EN_32M_UMSK       (~(((1U << PDS_CLKPLL_EN_32M_LEN) - 1) << PDS_CLKPLL_EN_32M_POS))
+#define PDS_CLKPLL_EN_DIV2_480M      PDS_CLKPLL_EN_DIV2_480M
+#define PDS_CLKPLL_EN_DIV2_480M_POS  (9U)
+#define PDS_CLKPLL_EN_DIV2_480M_LEN  (1U)
+#define PDS_CLKPLL_EN_DIV2_480M_MSK  (((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS)
+#define PDS_CLKPLL_EN_DIV2_480M_UMSK (~(((1U << PDS_CLKPLL_EN_DIV2_480M_LEN) - 1) << PDS_CLKPLL_EN_DIV2_480M_POS))
+
+/* 0x420 : clkpll_test_enable */
+#define PDS_CLKPLL_TEST_ENABLE_OFFSET    (0x420)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK      PDS_DTEN_CLKPLL_POSTDIV_CLK
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_POS  (0U)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN  (1U)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_MSK  (((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS)
+#define PDS_DTEN_CLKPLL_POSTDIV_CLK_UMSK (~(((1U << PDS_DTEN_CLKPLL_POSTDIV_CLK_LEN) - 1) << PDS_DTEN_CLKPLL_POSTDIV_CLK_POS))
+#define PDS_DTEN_CLK96M                  PDS_DTEN_CLK96M
+#define PDS_DTEN_CLK96M_POS              (1U)
+#define PDS_DTEN_CLK96M_LEN              (1U)
+#define PDS_DTEN_CLK96M_MSK              (((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS)
+#define PDS_DTEN_CLK96M_UMSK             (~(((1U << PDS_DTEN_CLK96M_LEN) - 1) << PDS_DTEN_CLK96M_POS))
+#define PDS_DTEN_CLK32M                  PDS_DTEN_CLK32M
+#define PDS_DTEN_CLK32M_POS              (2U)
+#define PDS_DTEN_CLK32M_LEN              (1U)
+#define PDS_DTEN_CLK32M_MSK              (((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS)
+#define PDS_DTEN_CLK32M_UMSK             (~(((1U << PDS_DTEN_CLK32M_LEN) - 1) << PDS_DTEN_CLK32M_POS))
+#define PDS_DTEN_CLKPLL_FSDM             PDS_DTEN_CLKPLL_FSDM
+#define PDS_DTEN_CLKPLL_FSDM_POS         (3U)
+#define PDS_DTEN_CLKPLL_FSDM_LEN         (1U)
+#define PDS_DTEN_CLKPLL_FSDM_MSK         (((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS)
+#define PDS_DTEN_CLKPLL_FSDM_UMSK        (~(((1U << PDS_DTEN_CLKPLL_FSDM_LEN) - 1) << PDS_DTEN_CLKPLL_FSDM_POS))
+#define PDS_DTEN_CLKPLL_FREF             PDS_DTEN_CLKPLL_FREF
+#define PDS_DTEN_CLKPLL_FREF_POS         (4U)
+#define PDS_DTEN_CLKPLL_FREF_LEN         (1U)
+#define PDS_DTEN_CLKPLL_FREF_MSK         (((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS)
+#define PDS_DTEN_CLKPLL_FREF_UMSK        (~(((1U << PDS_DTEN_CLKPLL_FREF_LEN) - 1) << PDS_DTEN_CLKPLL_FREF_POS))
+#define PDS_DTEN_CLKPLL_FIN              PDS_DTEN_CLKPLL_FIN
+#define PDS_DTEN_CLKPLL_FIN_POS          (5U)
+#define PDS_DTEN_CLKPLL_FIN_LEN          (1U)
+#define PDS_DTEN_CLKPLL_FIN_MSK          (((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS)
+#define PDS_DTEN_CLKPLL_FIN_UMSK         (~(((1U << PDS_DTEN_CLKPLL_FIN_LEN) - 1) << PDS_DTEN_CLKPLL_FIN_POS))
+#define PDS_TEN_CLKPLL_SFREG             PDS_TEN_CLKPLL_SFREG
+#define PDS_TEN_CLKPLL_SFREG_POS         (6U)
+#define PDS_TEN_CLKPLL_SFREG_LEN         (1U)
+#define PDS_TEN_CLKPLL_SFREG_MSK         (((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS)
+#define PDS_TEN_CLKPLL_SFREG_UMSK        (~(((1U << PDS_TEN_CLKPLL_SFREG_LEN) - 1) << PDS_TEN_CLKPLL_SFREG_POS))
+#define PDS_TEN_CLKPLL                   PDS_TEN_CLKPLL
+#define PDS_TEN_CLKPLL_POS               (7U)
+#define PDS_TEN_CLKPLL_LEN               (1U)
+#define PDS_TEN_CLKPLL_MSK               (((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS)
+#define PDS_TEN_CLKPLL_UMSK              (~(((1U << PDS_TEN_CLKPLL_LEN) - 1) << PDS_TEN_CLKPLL_POS))
+#define PDS_CLKPLL_DC_TP_OUT_EN          PDS_CLKPLL_DC_TP_OUT_EN
+#define PDS_CLKPLL_DC_TP_OUT_EN_POS      (8U)
+#define PDS_CLKPLL_DC_TP_OUT_EN_LEN      (1U)
+#define PDS_CLKPLL_DC_TP_OUT_EN_MSK      (((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS)
+#define PDS_CLKPLL_DC_TP_OUT_EN_UMSK     (~(((1U << PDS_CLKPLL_DC_TP_OUT_EN_LEN) - 1) << PDS_CLKPLL_DC_TP_OUT_EN_POS))
+
+struct pds_reg {
+    /* 0x0 : PDS_CTL */
+    union {
+        struct
+        {
+            uint32_t pds_start_ps              : 1; /* [    0],        w1p,        0x0 */
+            uint32_t cr_sleep_forever          : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_xtal_force_off         : 1; /* [    2],        r/w,        0x0 */
+            uint32_t cr_wifi_pds_save_state    : 1; /* [    3],        r/w,        0x0 */
+            uint32_t cr_pds_pd_dcdc18          : 1; /* [    4],        r/w,        0x0 */
+            uint32_t cr_pds_pd_bg_sys          : 1; /* [    5],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_gpio_ie_pu_pd : 1; /* [    6],        r/w,        0x0 */
+            uint32_t cr_pds_ctrl_pu_flash      : 1; /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_gate_clk           : 1; /* [    8],        r/w,        0x1 */
+            uint32_t cr_pds_mem_stby           : 1; /* [    9],        r/w,        0x1 */
+            uint32_t cr_sw_pu_flash            : 1; /* [   10],        r/w,        0x1 */
+            uint32_t cr_pds_iso_en             : 1; /* [   11],        r/w,        0x1 */
+            uint32_t cr_pds_wait_xtal_rdy      : 1; /* [   12],        r/w,        0x0 */
+            uint32_t cr_pds_pwr_off            : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_pd_xtal            : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_soc_enb_force_on   : 1; /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_rst_soc_en         : 1; /* [   16],        r/w,        0x0 */
+            uint32_t cr_pds_rc32m_off_dis      : 1; /* [   17],        r/w,        0x0 */
+            uint32_t cr_pds_ldo_vsel_en        : 1; /* [   18],        r/w,        0x0 */
+            uint32_t cr_pds_ram_lp_with_clk_en : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20               : 1; /* [   20],       rsvd,        0x0 */
+            uint32_t cr_np_wfi_mask            : 1; /* [   21],        r/w,        0x0 */
+            uint32_t cr_pds_pd_ldo11           : 1; /* [   22],        r/w,        0x0 */
+            uint32_t cr_pds_force_ram_clk_en   : 1; /* [   23],        r/w,        0x0 */
+            uint32_t cr_pds_ldo_vol            : 4; /* [27:24],        r/w,        0xa */
+            uint32_t cr_pds_ctrl_rf            : 2; /* [29:28],        r/w,        0x1 */
+            uint32_t cr_pds_ctrl_pll           : 2; /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL;
+
+    /* 0x4 : PDS_TIME1 */
+    union {
+        struct
+        {
+            uint32_t cr_sleep_duration : 32; /* [31: 0],        r/w,      0xca8 */
+        } BF;
+        uint32_t WORD;
+    } PDS_TIME1;
+
+    /* 0x8  reserved */
+    uint8_t RESERVED0x8[4];
+
+    /* 0xC : PDS_INT */
+    union {
+        struct
+        {
+            uint32_t ro_pds_wake_int          : 1; /* [    0],          r,        0x0 */
+            uint32_t reserved_1               : 1; /* [    1],       rsvd,        0x0 */
+            uint32_t ro_pds_rf_done_int       : 1; /* [    2],          r,        0x0 */
+            uint32_t ro_pds_pll_done_int      : 1; /* [    3],          r,        0x0 */
+            uint32_t pds_reset_event          : 3; /* [ 6: 4],          r,        0x0 */
+            uint32_t pds_clr_reset_event      : 1; /* [    7],          w,        0x0 */
+            uint32_t cr_pds_wake_int_mask     : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9               : 1; /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_rf_done_int_mask  : 1; /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_pll_done_int_mask : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_14           : 3; /* [14:12],       rsvd,        0x0 */
+            uint32_t cr_pds_int_clr           : 1; /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_wakeup_src_en     : 8; /* [23:16],        r/w,       0xff */
+            uint32_t ro_pds_wakeup_event      : 8; /* [31:24],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_INT;
+
+    /* 0x10 : PDS_CTL2 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_force_np_pwr_off   : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1                : 1;  /* [    1],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_pwr_off   : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_pwr_off  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_iso_en    : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5                : 1;  /* [    5],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_iso_en    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_iso_en   : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_pds_rst   : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9                : 1;  /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_pds_rst   : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_pds_rst  : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_mem_stby  : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13               : 1;  /* [   13],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_mem_stby  : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_mem_stby : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t cr_pds_force_np_gate_clk  : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17               : 1;  /* [   17],       rsvd,        0x0 */
+            uint32_t cr_pds_force_bz_gate_clk  : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t cr_pds_force_usb_gate_clk : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20_31            : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL2;
+
+    /* 0x14 : PDS_CTL3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0                 : 1; /* [    0],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pwr_off  : 1; /* [    1],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_pwr_off   : 1; /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_4               : 2; /* [ 4: 3],       rsvd,        0x0 */
+            uint32_t cr_pds_force_ble_iso_en    : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6                 : 1; /* [    6],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_pds_rst  : 1; /* [    7],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_pds_rst   : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9                 : 1; /* [    9],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_mem_stby : 1; /* [   10],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_mem_stby  : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12                : 1; /* [   12],       rsvd,        0x0 */
+            uint32_t cr_pds_force_misc_gate_clk : 1; /* [   13],        r/w,        0x0 */
+            uint32_t cr_pds_force_ble_gate_clk  : 1; /* [   14],        r/w,        0x0 */
+            uint32_t reserved_15_23             : 9; /* [23:15],       rsvd,        0x0 */
+            uint32_t cr_pds_np_iso_en           : 1; /* [   24],        r/w,        0x1 */
+            uint32_t reserved_25_26             : 2; /* [26:25],       rsvd,        0x0 */
+            uint32_t cr_pds_bz_iso_en           : 1; /* [   27],        r/w,        0x1 */
+            uint32_t cr_pds_ble_iso_en          : 1; /* [   28],        r/w,        0x1 */
+            uint32_t cr_pds_usb_iso_en          : 1; /* [   29],        r/w,        0x1 */
+            uint32_t cr_pds_misc_iso_en         : 1; /* [   30],        r/w,        0x1 */
+            uint32_t reserved_31                : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL3;
+
+    /* 0x18 : PDS_CTL4 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_np_pwr_off       : 1; /* [    0],        r/w,        0x1 */
+            uint32_t cr_pds_np_reset         : 1; /* [    1],        r/w,        0x1 */
+            uint32_t cr_pds_np_mem_stby      : 1; /* [    2],        r/w,        0x1 */
+            uint32_t cr_pds_np_gate_clk      : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_11           : 8; /* [11: 4],       rsvd,        0x0 */
+            uint32_t cr_pds_bz_pwr_off       : 1; /* [   12],        r/w,        0x1 */
+            uint32_t cr_pds_bz_reset         : 1; /* [   13],        r/w,        0x1 */
+            uint32_t cr_pds_bz_mem_stby      : 1; /* [   14],        r/w,        0x1 */
+            uint32_t cr_pds_bz_gate_clk      : 1; /* [   15],        r/w,        0x1 */
+            uint32_t cr_pds_ble_pwr_off      : 1; /* [   16],        r/w,        0x1 */
+            uint32_t cr_pds_ble_reset        : 1; /* [   17],        r/w,        0x1 */
+            uint32_t cr_pds_ble_mem_stby     : 1; /* [   18],        r/w,        0x1 */
+            uint32_t cr_pds_ble_gate_clk     : 1; /* [   19],        r/w,        0x1 */
+            uint32_t cr_pds_usb_pwr_off      : 1; /* [   20],        r/w,        0x1 */
+            uint32_t cr_pds_usb_reset        : 1; /* [   21],        r/w,        0x1 */
+            uint32_t cr_pds_usb_mem_stby     : 1; /* [   22],        r/w,        0x1 */
+            uint32_t cr_pds_usb_gate_clk     : 1; /* [   23],        r/w,        0x1 */
+            uint32_t cr_pds_misc_pwr_off     : 1; /* [   24],        r/w,        0x1 */
+            uint32_t cr_pds_misc_reset       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t cr_pds_misc_mem_stby    : 1; /* [   26],        r/w,        0x1 */
+            uint32_t cr_pds_misc_gate_clk    : 1; /* [   27],        r/w,        0x1 */
+            uint32_t reserved_28_29          : 2; /* [29:28],       rsvd,        0x0 */
+            uint32_t cr_pds_misc_ana_pwr_off : 1; /* [   30],        r/w,        0x1 */
+            uint32_t cr_pds_misc_dig_pwr_off : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } PDS_CTL4;
+
+    /* 0x1C : pds_stat */
+    union {
+        struct
+        {
+            uint32_t ro_pds_state     : 4;  /* [ 3: 0],          r,        0x0 */
+            uint32_t reserved_4_7     : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t ro_pds_rf_state  : 4;  /* [11: 8],          r,        0x0 */
+            uint32_t reserved_12_15   : 4;  /* [15:12],       rsvd,        0x0 */
+            uint32_t ro_pds_pll_state : 2;  /* [17:16],          r,        0x0 */
+            uint32_t reserved_18_31   : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_stat;
+
+    /* 0x20 : pds_ram1 */
+    union {
+        struct
+        {
+            uint32_t cr_pds_ram_ret1n : 4;  /* [ 3: 0],        r/w,        0xf */
+            uint32_t cr_pds_ram_ret2n : 4;  /* [ 7: 4],        r/w,        0x0 */
+            uint32_t cr_pds_ram_pgen  : 4;  /* [11: 8],        r/w,        0x0 */
+            uint32_t reserved_12_31   : 20; /* [31:12],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_ram1;
+
+    /* 0x24  reserved */
+    uint8_t RESERVED0x24[12];
+
+    /* 0x30 : pds_gpio_set_pu_pd */
+    union {
+        struct
+        {
+            uint32_t cr_pds_gpio_22_17_pd : 6; /* [ 5: 0],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_22_17_pu : 6; /* [13: 8],        r/w,        0x0 */
+            uint32_t reserved_14_15       : 2; /* [15:14],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_28_23_pd : 6; /* [21:16],        r/w,        0x0 */
+            uint32_t reserved_22_23       : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t cr_pds_gpio_28_23_pu : 6; /* [29:24],        r/w,        0x0 */
+            uint32_t reserved_30_31       : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_set_pu_pd;
+
+    /* 0x34  reserved */
+    uint8_t RESERVED0x34[12];
+
+    /* 0x40 : pds_gpio_int */
+    union {
+        struct
+        {
+            uint32_t pds_gpio_int_mask   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t pds_gpio_int_stat   : 1;  /* [    1],          r,        0x0 */
+            uint32_t pds_gpio_int_clr    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3          : 1;  /* [    3],       rsvd,        0x0 */
+            uint32_t pds_gpio_int_mode   : 3;  /* [ 6: 4],        r/w,        0x0 */
+            uint32_t reserved_7          : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t pds_gpio_int_select : 3;  /* [10: 8],        r/w,        0x0 */
+            uint32_t reserved_11_31      : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pds_gpio_int;
+
+    /* 0x44  reserved */
+    uint8_t RESERVED0x44[700];
+
+    /* 0x300 : rc32m_ctrl0 */
+    union {
+        struct
+        {
+            uint32_t rc32m_cal_done        : 1; /* [    0],          r,        0x0 */
+            uint32_t rc32m_rdy             : 1; /* [    1],          r,        0x0 */
+            uint32_t rc32m_cal_inprogress  : 1; /* [    2],          r,        0x0 */
+            uint32_t rc32m_cal_div         : 2; /* [ 4: 3],        r/w,        0x3 */
+            uint32_t rc32m_cal_precharge   : 1; /* [    5],          r,        0x0 */
+            uint32_t rc32m_dig_code_fr_cal : 8; /* [13: 6],          r,        0x0 */
+            uint32_t reserved_14_16        : 3; /* [16:14],       rsvd,        0x0 */
+            uint32_t rc32m_allow_cal       : 1; /* [   17],        r/w,        0x0 */
+            uint32_t rc32m_refclk_half     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t rc32m_ext_code_en     : 1; /* [   19],        r/w,        0x1 */
+            uint32_t rc32m_cal_en          : 1; /* [   20],        r/w,        0x0 */
+            uint32_t rc32m_pd              : 1; /* [   21],        r/w,        0x0 */
+            uint32_t rc32m_code_fr_ext     : 8; /* [29:22],        r/w,       0x60 */
+            uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl0;
+
+    /* 0x304 : rc32m_ctrl1 */
+    union {
+        struct
+        {
+            uint32_t rc32m_test_en      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t rc32m_soft_rst     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t rc32m_clk_soft_rst : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t rc32m_clk_inv      : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t rc32m_clk_force_on : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_23      : 19; /* [23: 5],       rsvd,        0x0 */
+            uint32_t rc32m_reserved     : 8;  /* [31:24],        r/w,        0xf */
+        } BF;
+        uint32_t WORD;
+    } rc32m_ctrl1;
+
+    /* 0x308  reserved */
+    uint8_t RESERVED0x308[248];
+
+    /* 0x400 : pu_rst_clkpll */
+    union {
+        struct
+        {
+            uint32_t clkpll_sdm_reset     : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t clkpll_reset_postdiv : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t clkpll_reset_fbdv    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t clkpll_reset_refdiv  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t clkpll_pu_postdiv    : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t clkpll_pu_fbdv       : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t clkpll_pu_clamp_op   : 1;  /* [    6],        r/w,        0x1 */
+            uint32_t clkpll_pu_pfd        : 1;  /* [    7],        r/w,        0x1 */
+            uint32_t clkpll_pu_cp         : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t pu_clkpll_sfreg      : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t pu_clkpll            : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } pu_rst_clkpll;
+
+    /* 0x404 : clkpll_top_ctrl */
+    union {
+        struct
+        {
+            uint32_t clkpll_postdiv        : 7; /* [ 6: 0],        r/w,       0x14 */
+            uint32_t reserved_7            : 1; /* [    7],       rsvd,        0x0 */
+            uint32_t clkpll_refdiv_ratio   : 4; /* [11: 8],        r/w,        0x4 */
+            uint32_t clkpll_xtal_rc32m_sel : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_15        : 3; /* [15:13],       rsvd,        0x0 */
+            uint32_t clkpll_refclk_sel     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_19        : 3; /* [19:17],       rsvd,        0x0 */
+            uint32_t clkpll_vg11_sel       : 2; /* [21:20],        r/w,        0x1 */
+            uint32_t reserved_22_23        : 2; /* [23:22],       rsvd,        0x0 */
+            uint32_t clkpll_resv           : 2; /* [25:24],        r/w,        0x1 */
+            uint32_t reserved_26_31        : 6; /* [31:26],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_top_ctrl;
+
+    /* 0x408 : clkpll_cp */
+    union {
+        struct
+        {
+            uint32_t clkpll_sel_cp_bias   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_3         : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t clkpll_icp_5u        : 2;  /* [ 5: 4],        r/w,        0x0 */
+            uint32_t clkpll_icp_1u        : 2;  /* [ 7: 6],        r/w,        0x1 */
+            uint32_t clkpll_int_frac_sw   : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t clkpll_cp_startup_en : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t clkpll_cp_opamp_en   : 1;  /* [   10],        r/w,        0x1 */
+            uint32_t reserved_11_31       : 21; /* [31:11],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_cp;
+
+    /* 0x40C : clkpll_rz */
+    union {
+        struct
+        {
+            uint32_t clkpll_c4_en    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1_3    : 3;  /* [ 3: 1],       rsvd,        0x0 */
+            uint32_t clkpll_r4       : 2;  /* [ 5: 4],        r/w,        0x2 */
+            uint32_t reserved_6_7    : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t clkpll_r4_short : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_11   : 3;  /* [11: 9],       rsvd,        0x0 */
+            uint32_t clkpll_c3       : 2;  /* [13:12],        r/w,        0x2 */
+            uint32_t clkpll_cz       : 2;  /* [15:14],        r/w,        0x2 */
+            uint32_t clkpll_rz       : 3;  /* [18:16],        r/w,        0x5 */
+            uint32_t reserved_19_31  : 13; /* [31:19],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_rz;
+
+    /* 0x410 : clkpll_fbdv */
+    union {
+        struct
+        {
+            uint32_t clkpll_sel_sample_clk : 2;  /* [ 1: 0],        r/w,        0x1 */
+            uint32_t clkpll_sel_fb_clk     : 2;  /* [ 3: 2],        r/w,        0x1 */
+            uint32_t reserved_4_31         : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_fbdv;
+
+    /* 0x414 : clkpll_vco */
+    union {
+        struct
+        {
+            uint32_t clkpll_vco_speed : 3;  /* [ 2: 0],        r/w,        0x6 */
+            uint32_t clkpll_shrtr     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t reserved_4_31    : 28; /* [31: 4],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_vco;
+
+    /* 0x418 : clkpll_sdm */
+    union {
+        struct
+        {
+            uint32_t clkpll_sdmin      : 24; /* [23: 0],        r/w,   0x600000 */
+            uint32_t clkpll_dither_sel : 2;  /* [25:24],        r/w,        0x0 */
+            uint32_t reserved_26_27    : 2;  /* [27:26],       rsvd,        0x0 */
+            uint32_t clkpll_sdm_flag   : 1;  /* [   28],        r/w,        0x1 */
+            uint32_t clkpll_sdm_bypass : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t reserved_30_31    : 2;  /* [31:30],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_sdm;
+
+    /* 0x41C : clkpll_output_en */
+    union {
+        struct
+        {
+            uint32_t clkpll_en_480m      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t clkpll_en_240m      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t clkpll_en_192m      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t clkpll_en_160m      : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t clkpll_en_120m      : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t clkpll_en_96m       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t clkpll_en_80m       : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t clkpll_en_48m       : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t clkpll_en_32m       : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t clkpll_en_div2_480m : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_31      : 22; /* [31:10],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_output_en;
+
+    /* 0x420 : clkpll_test_enable */
+    union {
+        struct
+        {
+            uint32_t dten_clkpll_postdiv_clk : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t dten_clk96M             : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t dten_clk32M             : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t dten_clkpll_fsdm        : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t dten_clkpll_fref        : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t dten_clkpll_fin         : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t ten_clkpll_sfreg        : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t ten_clkpll              : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t clkpll_dc_tp_out_en     : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t reserved_9_31           : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } clkpll_test_enable;
+};
+
+typedef volatile struct pds_reg pds_reg_t;
+
+#endif /* __PDS_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/sf_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/sf_ctrl_reg.h
new file mode 100755
index 0000000000..45eda74109
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/sf_ctrl_reg.h
@@ -0,0 +1,2735 @@
+/**
+  ******************************************************************************
+  * @file    sf_ctrl_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __SF_CTRL_REG_H__
+#define __SF_CTRL_REG_H__
+
+#include "bl702.h"
+
+/* 0x0 : sf_ctrl_0 */
+#define SF_CTRL_0_OFFSET                  (0x0)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL      SF_CTRL_SF_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS  (2U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN  (1U)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SF_RX_INV_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_GATE_EN        SF_CTRL_SF_CLK_OUT_GATE_EN
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_POS    (3U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_LEN    (1U)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_MSK    (((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS)
+#define SF_CTRL_SF_CLK_OUT_GATE_EN_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_GATE_EN_LEN) - 1) << SF_CTRL_SF_CLK_OUT_GATE_EN_POS))
+#define SF_CTRL_SF_CLK_OUT_INV_SEL        SF_CTRL_SF_CLK_OUT_INV_SEL
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_POS    (4U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_LEN    (1U)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL      SF_CTRL_SF_CLK_SAHB_SRAM_SEL
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS  (5U)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN  (1U)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_MSK  (((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS)
+#define SF_CTRL_SF_CLK_SAHB_SRAM_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_LEN) - 1) << SF_CTRL_SF_CLK_SAHB_SRAM_SEL_POS))
+#define SF_CTRL_SF_IF_READ_DLY_N          SF_CTRL_SF_IF_READ_DLY_N
+#define SF_CTRL_SF_IF_READ_DLY_N_POS      (8U)
+#define SF_CTRL_SF_IF_READ_DLY_N_LEN      (3U)
+#define SF_CTRL_SF_IF_READ_DLY_N_MSK      (((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS)
+#define SF_CTRL_SF_IF_READ_DLY_N_UMSK     (~(((1U << SF_CTRL_SF_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_N_POS))
+#define SF_CTRL_SF_IF_READ_DLY_EN         SF_CTRL_SF_IF_READ_DLY_EN
+#define SF_CTRL_SF_IF_READ_DLY_EN_POS     (11U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_LEN     (1U)
+#define SF_CTRL_SF_IF_READ_DLY_EN_MSK     (((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS)
+#define SF_CTRL_SF_IF_READ_DLY_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF_IF_READ_DLY_EN_POS))
+#define SF_CTRL_SF_IF_INT                 SF_CTRL_SF_IF_INT
+#define SF_CTRL_SF_IF_INT_POS             (16U)
+#define SF_CTRL_SF_IF_INT_LEN             (1U)
+#define SF_CTRL_SF_IF_INT_MSK             (((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS)
+#define SF_CTRL_SF_IF_INT_UMSK            (~(((1U << SF_CTRL_SF_IF_INT_LEN) - 1) << SF_CTRL_SF_IF_INT_POS))
+#define SF_CTRL_SF_IF_INT_CLR             SF_CTRL_SF_IF_INT_CLR
+#define SF_CTRL_SF_IF_INT_CLR_POS         (17U)
+#define SF_CTRL_SF_IF_INT_CLR_LEN         (1U)
+#define SF_CTRL_SF_IF_INT_CLR_MSK         (((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS)
+#define SF_CTRL_SF_IF_INT_CLR_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_CLR_LEN) - 1) << SF_CTRL_SF_IF_INT_CLR_POS))
+#define SF_CTRL_SF_IF_INT_SET             SF_CTRL_SF_IF_INT_SET
+#define SF_CTRL_SF_IF_INT_SET_POS         (18U)
+#define SF_CTRL_SF_IF_INT_SET_LEN         (1U)
+#define SF_CTRL_SF_IF_INT_SET_MSK         (((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS)
+#define SF_CTRL_SF_IF_INT_SET_UMSK        (~(((1U << SF_CTRL_SF_IF_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_INT_SET_POS))
+#define SF_CTRL_SF_AES_DLY_MODE           SF_CTRL_SF_AES_DLY_MODE
+#define SF_CTRL_SF_AES_DLY_MODE_POS       (19U)
+#define SF_CTRL_SF_AES_DLY_MODE_LEN       (1U)
+#define SF_CTRL_SF_AES_DLY_MODE_MSK       (((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS)
+#define SF_CTRL_SF_AES_DLY_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_DLY_MODE_LEN) - 1) << SF_CTRL_SF_AES_DLY_MODE_POS))
+#define SF_CTRL_SF_AES_DOUT_ENDIAN        SF_CTRL_SF_AES_DOUT_ENDIAN
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_POS    (20U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_LEN    (1U)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_MSK    (((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS)
+#define SF_CTRL_SF_AES_DOUT_ENDIAN_UMSK   (~(((1U << SF_CTRL_SF_AES_DOUT_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_DOUT_ENDIAN_POS))
+#define SF_CTRL_SF_AES_CTR_PLUS_EN        SF_CTRL_SF_AES_CTR_PLUS_EN
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_POS    (21U)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_LEN    (1U)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_MSK    (((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS)
+#define SF_CTRL_SF_AES_CTR_PLUS_EN_UMSK   (~(((1U << SF_CTRL_SF_AES_CTR_PLUS_EN_LEN) - 1) << SF_CTRL_SF_AES_CTR_PLUS_EN_POS))
+#define SF_CTRL_SF_AES_KEY_ENDIAN         SF_CTRL_SF_AES_KEY_ENDIAN
+#define SF_CTRL_SF_AES_KEY_ENDIAN_POS     (22U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_LEN     (1U)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_MSK     (((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS)
+#define SF_CTRL_SF_AES_KEY_ENDIAN_UMSK    (~(((1U << SF_CTRL_SF_AES_KEY_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_KEY_ENDIAN_POS))
+#define SF_CTRL_SF_AES_IV_ENDIAN          SF_CTRL_SF_AES_IV_ENDIAN
+#define SF_CTRL_SF_AES_IV_ENDIAN_POS      (23U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_LEN      (1U)
+#define SF_CTRL_SF_AES_IV_ENDIAN_MSK      (((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS)
+#define SF_CTRL_SF_AES_IV_ENDIAN_UMSK     (~(((1U << SF_CTRL_SF_AES_IV_ENDIAN_LEN) - 1) << SF_CTRL_SF_AES_IV_ENDIAN_POS))
+#define SF_CTRL_SF_ID                     SF_CTRL_SF_ID
+#define SF_CTRL_SF_ID_POS                 (24U)
+#define SF_CTRL_SF_ID_LEN                 (8U)
+#define SF_CTRL_SF_ID_MSK                 (((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS)
+#define SF_CTRL_SF_ID_UMSK                (~(((1U << SF_CTRL_SF_ID_LEN) - 1) << SF_CTRL_SF_ID_POS))
+
+/* 0x4 : sf_ctrl_1 */
+#define SF_CTRL_1_OFFSET                (0x4)
+#define SF_CTRL_SF_IF_SR_PAT_MASK       SF_CTRL_SF_IF_SR_PAT_MASK
+#define SF_CTRL_SF_IF_SR_PAT_MASK_POS   (0U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_LEN   (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_MSK   (((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS)
+#define SF_CTRL_SF_IF_SR_PAT_MASK_UMSK  (~(((1U << SF_CTRL_SF_IF_SR_PAT_MASK_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_MASK_POS))
+#define SF_CTRL_SF_IF_SR_PAT            SF_CTRL_SF_IF_SR_PAT
+#define SF_CTRL_SF_IF_SR_PAT_POS        (8U)
+#define SF_CTRL_SF_IF_SR_PAT_LEN        (8U)
+#define SF_CTRL_SF_IF_SR_PAT_MSK        (((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS)
+#define SF_CTRL_SF_IF_SR_PAT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_PAT_LEN) - 1) << SF_CTRL_SF_IF_SR_PAT_POS))
+#define SF_CTRL_SF_IF_SR_INT            SF_CTRL_SF_IF_SR_INT
+#define SF_CTRL_SF_IF_SR_INT_POS        (16U)
+#define SF_CTRL_SF_IF_SR_INT_LEN        (1U)
+#define SF_CTRL_SF_IF_SR_INT_MSK        (((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS)
+#define SF_CTRL_SF_IF_SR_INT_UMSK       (~(((1U << SF_CTRL_SF_IF_SR_INT_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_POS))
+#define SF_CTRL_SF_IF_SR_INT_EN         SF_CTRL_SF_IF_SR_INT_EN
+#define SF_CTRL_SF_IF_SR_INT_EN_POS     (17U)
+#define SF_CTRL_SF_IF_SR_INT_EN_LEN     (1U)
+#define SF_CTRL_SF_IF_SR_INT_EN_MSK     (((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS)
+#define SF_CTRL_SF_IF_SR_INT_EN_UMSK    (~(((1U << SF_CTRL_SF_IF_SR_INT_EN_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_EN_POS))
+#define SF_CTRL_SF_IF_SR_INT_SET        SF_CTRL_SF_IF_SR_INT_SET
+#define SF_CTRL_SF_IF_SR_INT_SET_POS    (18U)
+#define SF_CTRL_SF_IF_SR_INT_SET_LEN    (1U)
+#define SF_CTRL_SF_IF_SR_INT_SET_MSK    (((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS)
+#define SF_CTRL_SF_IF_SR_INT_SET_UMSK   (~(((1U << SF_CTRL_SF_IF_SR_INT_SET_LEN) - 1) << SF_CTRL_SF_IF_SR_INT_SET_POS))
+#define SF_CTRL_SF_IF_0_ACK_LAT         SF_CTRL_SF_IF_0_ACK_LAT
+#define SF_CTRL_SF_IF_0_ACK_LAT_POS     (20U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_LEN     (3U)
+#define SF_CTRL_SF_IF_0_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_0_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_0_ACK_LAT_POS))
+#define SF_CTRL_SF_IF_REG_HOLD          SF_CTRL_SF_IF_REG_HOLD
+#define SF_CTRL_SF_IF_REG_HOLD_POS      (24U)
+#define SF_CTRL_SF_IF_REG_HOLD_LEN      (1U)
+#define SF_CTRL_SF_IF_REG_HOLD_MSK      (((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS)
+#define SF_CTRL_SF_IF_REG_HOLD_UMSK     (~(((1U << SF_CTRL_SF_IF_REG_HOLD_LEN) - 1) << SF_CTRL_SF_IF_REG_HOLD_POS))
+#define SF_CTRL_SF_IF_REG_WP            SF_CTRL_SF_IF_REG_WP
+#define SF_CTRL_SF_IF_REG_WP_POS        (25U)
+#define SF_CTRL_SF_IF_REG_WP_LEN        (1U)
+#define SF_CTRL_SF_IF_REG_WP_MSK        (((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS)
+#define SF_CTRL_SF_IF_REG_WP_UMSK       (~(((1U << SF_CTRL_SF_IF_REG_WP_LEN) - 1) << SF_CTRL_SF_IF_REG_WP_POS))
+#define SF_CTRL_SF_AHB2SIF_STOPPED      SF_CTRL_SF_AHB2SIF_STOPPED
+#define SF_CTRL_SF_AHB2SIF_STOPPED_POS  (26U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_LEN  (1U)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_MSK  (((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS)
+#define SF_CTRL_SF_AHB2SIF_STOPPED_UMSK (~(((1U << SF_CTRL_SF_AHB2SIF_STOPPED_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOPPED_POS))
+#define SF_CTRL_SF_AHB2SIF_STOP         SF_CTRL_SF_AHB2SIF_STOP
+#define SF_CTRL_SF_AHB2SIF_STOP_POS     (27U)
+#define SF_CTRL_SF_AHB2SIF_STOP_LEN     (1U)
+#define SF_CTRL_SF_AHB2SIF_STOP_MSK     (((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS)
+#define SF_CTRL_SF_AHB2SIF_STOP_UMSK    (~(((1U << SF_CTRL_SF_AHB2SIF_STOP_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STOP_POS))
+#define SF_CTRL_SF_IF_FN_SEL            SF_CTRL_SF_IF_FN_SEL
+#define SF_CTRL_SF_IF_FN_SEL_POS        (28U)
+#define SF_CTRL_SF_IF_FN_SEL_LEN        (1U)
+#define SF_CTRL_SF_IF_FN_SEL_MSK        (((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS)
+#define SF_CTRL_SF_IF_FN_SEL_UMSK       (~(((1U << SF_CTRL_SF_IF_FN_SEL_LEN) - 1) << SF_CTRL_SF_IF_FN_SEL_POS))
+#define SF_CTRL_SF_IF_EN                SF_CTRL_SF_IF_EN
+#define SF_CTRL_SF_IF_EN_POS            (29U)
+#define SF_CTRL_SF_IF_EN_LEN            (1U)
+#define SF_CTRL_SF_IF_EN_MSK            (((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS)
+#define SF_CTRL_SF_IF_EN_UMSK           (~(((1U << SF_CTRL_SF_IF_EN_LEN) - 1) << SF_CTRL_SF_IF_EN_POS))
+#define SF_CTRL_SF_AHB2SIF_EN           SF_CTRL_SF_AHB2SIF_EN
+#define SF_CTRL_SF_AHB2SIF_EN_POS       (30U)
+#define SF_CTRL_SF_AHB2SIF_EN_LEN       (1U)
+#define SF_CTRL_SF_AHB2SIF_EN_MSK       (((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS)
+#define SF_CTRL_SF_AHB2SIF_EN_UMSK      (~(((1U << SF_CTRL_SF_AHB2SIF_EN_LEN) - 1) << SF_CTRL_SF_AHB2SIF_EN_POS))
+#define SF_CTRL_SF_AHB2SRAM_EN          SF_CTRL_SF_AHB2SRAM_EN
+#define SF_CTRL_SF_AHB2SRAM_EN_POS      (31U)
+#define SF_CTRL_SF_AHB2SRAM_EN_LEN      (1U)
+#define SF_CTRL_SF_AHB2SRAM_EN_MSK      (((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS)
+#define SF_CTRL_SF_AHB2SRAM_EN_UMSK     (~(((1U << SF_CTRL_SF_AHB2SRAM_EN_LEN) - 1) << SF_CTRL_SF_AHB2SRAM_EN_POS))
+
+/* 0x8 : sf_if_sahb_0 */
+#define SF_CTRL_SF_IF_SAHB_0_OFFSET      (0x8)
+#define SF_CTRL_SF_IF_BUSY               SF_CTRL_SF_IF_BUSY
+#define SF_CTRL_SF_IF_BUSY_POS           (0U)
+#define SF_CTRL_SF_IF_BUSY_LEN           (1U)
+#define SF_CTRL_SF_IF_BUSY_MSK           (((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS)
+#define SF_CTRL_SF_IF_BUSY_UMSK          (~(((1U << SF_CTRL_SF_IF_BUSY_LEN) - 1) << SF_CTRL_SF_IF_BUSY_POS))
+#define SF_CTRL_SF_IF_0_TRIG             SF_CTRL_SF_IF_0_TRIG
+#define SF_CTRL_SF_IF_0_TRIG_POS         (1U)
+#define SF_CTRL_SF_IF_0_TRIG_LEN         (1U)
+#define SF_CTRL_SF_IF_0_TRIG_MSK         (((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS)
+#define SF_CTRL_SF_IF_0_TRIG_UMSK        (~(((1U << SF_CTRL_SF_IF_0_TRIG_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_POS))
+#define SF_CTRL_SF_IF_0_DAT_BYTE         SF_CTRL_SF_IF_0_DAT_BYTE
+#define SF_CTRL_SF_IF_0_DAT_BYTE_POS     (2U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_LEN     (10U)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DAT_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DAT_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DMY_BYTE         SF_CTRL_SF_IF_0_DMY_BYTE
+#define SF_CTRL_SF_IF_0_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_0_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_0_ADR_BYTE         SF_CTRL_SF_IF_0_ADR_BYTE
+#define SF_CTRL_SF_IF_0_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_0_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_0_CMD_BYTE         SF_CTRL_SF_IF_0_CMD_BYTE
+#define SF_CTRL_SF_IF_0_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_0_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_0_DAT_RW           SF_CTRL_SF_IF_0_DAT_RW
+#define SF_CTRL_SF_IF_0_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_0_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS)
+#define SF_CTRL_SF_IF_0_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_RW_POS))
+#define SF_CTRL_SF_IF_0_DAT_EN           SF_CTRL_SF_IF_0_DAT_EN
+#define SF_CTRL_SF_IF_0_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_0_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS)
+#define SF_CTRL_SF_IF_0_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DAT_EN_POS))
+#define SF_CTRL_SF_IF_0_DMY_EN           SF_CTRL_SF_IF_0_DMY_EN
+#define SF_CTRL_SF_IF_0_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_0_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS)
+#define SF_CTRL_SF_IF_0_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_0_DMY_EN_POS))
+#define SF_CTRL_SF_IF_0_ADR_EN           SF_CTRL_SF_IF_0_ADR_EN
+#define SF_CTRL_SF_IF_0_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_0_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS)
+#define SF_CTRL_SF_IF_0_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_0_ADR_EN_POS))
+#define SF_CTRL_SF_IF_0_CMD_EN           SF_CTRL_SF_IF_0_CMD_EN
+#define SF_CTRL_SF_IF_0_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_0_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_0_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS)
+#define SF_CTRL_SF_IF_0_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_0_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_EN_POS))
+#define SF_CTRL_SF_IF_0_SPI_MODE         SF_CTRL_SF_IF_0_SPI_MODE
+#define SF_CTRL_SF_IF_0_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_0_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_0_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_0_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_0_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN      SF_CTRL_SF_IF_0_QPI_MODE_EN
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_0_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_0_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_0_QPI_MODE_EN_POS))
+
+/* 0xC : sf_if_sahb_1 */
+#define SF_CTRL_SF_IF_SAHB_1_OFFSET    (0xC)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0      SF_CTRL_SF_IF_0_CMD_BUF_0
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_0_POS))
+
+/* 0x10 : sf_if_sahb_2 */
+#define SF_CTRL_SF_IF_SAHB_2_OFFSET    (0x10)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1      SF_CTRL_SF_IF_0_CMD_BUF_1
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_0_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_0_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_0_CMD_BUF_1_POS))
+
+/* 0x14 : sf_if_iahb_0 */
+#define SF_CTRL_SF_IF_IAHB_0_OFFSET      (0x14)
+#define SF_CTRL_SF_IF_1_DMY_BYTE         SF_CTRL_SF_IF_1_DMY_BYTE
+#define SF_CTRL_SF_IF_1_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_1_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_1_ADR_BYTE         SF_CTRL_SF_IF_1_ADR_BYTE
+#define SF_CTRL_SF_IF_1_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_1_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_1_CMD_BYTE         SF_CTRL_SF_IF_1_CMD_BYTE
+#define SF_CTRL_SF_IF_1_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_1_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_1_DAT_RW           SF_CTRL_SF_IF_1_DAT_RW
+#define SF_CTRL_SF_IF_1_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_1_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS)
+#define SF_CTRL_SF_IF_1_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_RW_POS))
+#define SF_CTRL_SF_IF_1_DAT_EN           SF_CTRL_SF_IF_1_DAT_EN
+#define SF_CTRL_SF_IF_1_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_1_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS)
+#define SF_CTRL_SF_IF_1_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DAT_EN_POS))
+#define SF_CTRL_SF_IF_1_DMY_EN           SF_CTRL_SF_IF_1_DMY_EN
+#define SF_CTRL_SF_IF_1_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_1_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS)
+#define SF_CTRL_SF_IF_1_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_1_DMY_EN_POS))
+#define SF_CTRL_SF_IF_1_ADR_EN           SF_CTRL_SF_IF_1_ADR_EN
+#define SF_CTRL_SF_IF_1_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_1_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS)
+#define SF_CTRL_SF_IF_1_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_1_ADR_EN_POS))
+#define SF_CTRL_SF_IF_1_CMD_EN           SF_CTRL_SF_IF_1_CMD_EN
+#define SF_CTRL_SF_IF_1_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_1_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_1_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS)
+#define SF_CTRL_SF_IF_1_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_1_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_EN_POS))
+#define SF_CTRL_SF_IF_1_SPI_MODE         SF_CTRL_SF_IF_1_SPI_MODE
+#define SF_CTRL_SF_IF_1_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_1_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_1_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_1_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_1_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN      SF_CTRL_SF_IF_1_QPI_MODE_EN
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_1_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_1_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_1_QPI_MODE_EN_POS))
+
+/* 0x18 : sf_if_iahb_1 */
+#define SF_CTRL_SF_IF_IAHB_1_OFFSET    (0x18)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0      SF_CTRL_SF_IF_1_CMD_BUF_0
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_0_POS))
+
+/* 0x1C : sf_if_iahb_2 */
+#define SF_CTRL_SF_IF_IAHB_2_OFFSET    (0x1C)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1      SF_CTRL_SF_IF_1_CMD_BUF_1
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_1_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_1_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_1_CMD_BUF_1_POS))
+
+/* 0x20 : sf_if_status_0 */
+#define SF_CTRL_SF_IF_STATUS_0_OFFSET (0x20)
+#define SF_CTRL_SF_IF_STATUS_0        SF_CTRL_SF_IF_STATUS_0
+#define SF_CTRL_SF_IF_STATUS_0_POS    (0U)
+#define SF_CTRL_SF_IF_STATUS_0_LEN    (32U)
+#define SF_CTRL_SF_IF_STATUS_0_MSK    (((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS)
+#define SF_CTRL_SF_IF_STATUS_0_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_0_LEN) - 1) << SF_CTRL_SF_IF_STATUS_0_POS))
+
+/* 0x24 : sf_if_status_1 */
+#define SF_CTRL_SF_IF_STATUS_1_OFFSET (0x24)
+#define SF_CTRL_SF_IF_STATUS_1        SF_CTRL_SF_IF_STATUS_1
+#define SF_CTRL_SF_IF_STATUS_1_POS    (0U)
+#define SF_CTRL_SF_IF_STATUS_1_LEN    (32U)
+#define SF_CTRL_SF_IF_STATUS_1_MSK    (((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS)
+#define SF_CTRL_SF_IF_STATUS_1_UMSK   (~(((1U << SF_CTRL_SF_IF_STATUS_1_LEN) - 1) << SF_CTRL_SF_IF_STATUS_1_POS))
+
+/* 0x28 : sf_aes */
+#define SF_CTRL_SF_AES_OFFSET         (0x28)
+#define SF_CTRL_SF_AES_EN             SF_CTRL_SF_AES_EN
+#define SF_CTRL_SF_AES_EN_POS         (0U)
+#define SF_CTRL_SF_AES_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_EN_MSK         (((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS)
+#define SF_CTRL_SF_AES_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_EN_LEN) - 1) << SF_CTRL_SF_AES_EN_POS))
+#define SF_CTRL_SF_AES_MODE           SF_CTRL_SF_AES_MODE
+#define SF_CTRL_SF_AES_MODE_POS       (1U)
+#define SF_CTRL_SF_AES_MODE_LEN       (2U)
+#define SF_CTRL_SF_AES_MODE_MSK       (((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS)
+#define SF_CTRL_SF_AES_MODE_UMSK      (~(((1U << SF_CTRL_SF_AES_MODE_LEN) - 1) << SF_CTRL_SF_AES_MODE_POS))
+#define SF_CTRL_SF_AES_PREF_TRIG      SF_CTRL_SF_AES_PREF_TRIG
+#define SF_CTRL_SF_AES_PREF_TRIG_POS  (3U)
+#define SF_CTRL_SF_AES_PREF_TRIG_LEN  (1U)
+#define SF_CTRL_SF_AES_PREF_TRIG_MSK  (((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS)
+#define SF_CTRL_SF_AES_PREF_TRIG_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_TRIG_LEN) - 1) << SF_CTRL_SF_AES_PREF_TRIG_POS))
+#define SF_CTRL_SF_AES_PREF_BUSY      SF_CTRL_SF_AES_PREF_BUSY
+#define SF_CTRL_SF_AES_PREF_BUSY_POS  (4U)
+#define SF_CTRL_SF_AES_PREF_BUSY_LEN  (1U)
+#define SF_CTRL_SF_AES_PREF_BUSY_MSK  (((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS)
+#define SF_CTRL_SF_AES_PREF_BUSY_UMSK (~(((1U << SF_CTRL_SF_AES_PREF_BUSY_LEN) - 1) << SF_CTRL_SF_AES_PREF_BUSY_POS))
+#define SF_CTRL_SF_AES_STATUS         SF_CTRL_SF_AES_STATUS
+#define SF_CTRL_SF_AES_STATUS_POS     (5U)
+#define SF_CTRL_SF_AES_STATUS_LEN     (27U)
+#define SF_CTRL_SF_AES_STATUS_MSK     (((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS)
+#define SF_CTRL_SF_AES_STATUS_UMSK    (~(((1U << SF_CTRL_SF_AES_STATUS_LEN) - 1) << SF_CTRL_SF_AES_STATUS_POS))
+
+/* 0x2C : sf_ahb2sif_status */
+#define SF_CTRL_SF_AHB2SIF_STATUS_OFFSET (0x2C)
+#define SF_CTRL_SF_AHB2SIF_STATUS        SF_CTRL_SF_AHB2SIF_STATUS
+#define SF_CTRL_SF_AHB2SIF_STATUS_POS    (0U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_LEN    (32U)
+#define SF_CTRL_SF_AHB2SIF_STATUS_MSK    (((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS)
+#define SF_CTRL_SF_AHB2SIF_STATUS_UMSK   (~(((1U << SF_CTRL_SF_AHB2SIF_STATUS_LEN) - 1) << SF_CTRL_SF_AHB2SIF_STATUS_POS))
+
+/* 0x30 : sf_if_io_dly_0 */
+#define SF_CTRL_SF_IF_IO_DLY_0_OFFSET   (0x30)
+#define SF_CTRL_SF_CS_DLY_SEL           SF_CTRL_SF_CS_DLY_SEL
+#define SF_CTRL_SF_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS)
+#define SF_CTRL_SF_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS_DLY_SEL_POS))
+#define SF_CTRL_SF_CS2_DLY_SEL          SF_CTRL_SF_CS2_DLY_SEL
+#define SF_CTRL_SF_CS2_DLY_SEL_POS      (2U)
+#define SF_CTRL_SF_CS2_DLY_SEL_LEN      (2U)
+#define SF_CTRL_SF_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL      SF_CTRL_SF_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_OE_DLY_SEL       SF_CTRL_SF_DQS_OE_DLY_SEL
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DI_DLY_SEL       SF_CTRL_SF_DQS_DI_DLY_SEL
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_DQS_DO_DLY_SEL       SF_CTRL_SF_DQS_DO_DLY_SEL
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_DQS_DO_DLY_SEL_POS))
+
+/* 0x34 : sf_if_io_dly_1 */
+#define SF_CTRL_SF_IF_IO_DLY_1_OFFSET   (0x34)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL      SF_CTRL_SF_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL      SF_CTRL_SF_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL      SF_CTRL_SF_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_0_DO_DLY_SEL_POS))
+
+/* 0x38 : sf_if_io_dly_2 */
+#define SF_CTRL_SF_IF_IO_DLY_2_OFFSET   (0x38)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL      SF_CTRL_SF_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL      SF_CTRL_SF_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL      SF_CTRL_SF_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_1_DO_DLY_SEL_POS))
+
+/* 0x3C : sf_if_io_dly_3 */
+#define SF_CTRL_SF_IF_IO_DLY_3_OFFSET   (0x3C)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL      SF_CTRL_SF_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL      SF_CTRL_SF_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL      SF_CTRL_SF_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_2_DO_DLY_SEL_POS))
+
+/* 0x40 : sf_if_io_dly_4 */
+#define SF_CTRL_SF_IF_IO_DLY_4_OFFSET   (0x40)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL      SF_CTRL_SF_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL      SF_CTRL_SF_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL      SF_CTRL_SF_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF_IO_3_DO_DLY_SEL_POS))
+
+/* 0x44 : sf_reserved */
+#define SF_CTRL_SF_RESERVED_OFFSET (0x44)
+#define SF_CTRL_SF_RESERVED        SF_CTRL_SF_RESERVED
+#define SF_CTRL_SF_RESERVED_POS    (0U)
+#define SF_CTRL_SF_RESERVED_LEN    (32U)
+#define SF_CTRL_SF_RESERVED_MSK    (((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS)
+#define SF_CTRL_SF_RESERVED_UMSK   (~(((1U << SF_CTRL_SF_RESERVED_LEN) - 1) << SF_CTRL_SF_RESERVED_POS))
+
+/* 0x48 : sf2_if_io_dly_0 */
+#define SF_CTRL_SF2_IF_IO_DLY_0_OFFSET   (0x48)
+#define SF_CTRL_SF2_CS_DLY_SEL           SF_CTRL_SF2_CS_DLY_SEL
+#define SF_CTRL_SF2_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF2_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF2_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS)
+#define SF_CTRL_SF2_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF2_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS_DLY_SEL_POS))
+#define SF_CTRL_SF2_CS2_DLY_SEL          SF_CTRL_SF2_CS2_DLY_SEL
+#define SF_CTRL_SF2_CS2_DLY_SEL_POS      (2U)
+#define SF_CTRL_SF2_CS2_DLY_SEL_LEN      (2U)
+#define SF_CTRL_SF2_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF2_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF2_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL      SF_CTRL_SF2_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF2_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL       SF_CTRL_SF2_DQS_OE_DLY_SEL
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL       SF_CTRL_SF2_DQS_DI_DLY_SEL
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL       SF_CTRL_SF2_DQS_DO_DLY_SEL
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF2_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_DQS_DO_DLY_SEL_POS))
+
+/* 0x4C : sf2_if_io_dly_1 */
+#define SF_CTRL_SF2_IF_IO_DLY_1_OFFSET   (0x4C)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL      SF_CTRL_SF2_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL      SF_CTRL_SF2_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL      SF_CTRL_SF2_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_0_DO_DLY_SEL_POS))
+
+/* 0x50 : sf2_if_io_dly_2 */
+#define SF_CTRL_SF2_IF_IO_DLY_2_OFFSET   (0x50)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL      SF_CTRL_SF2_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL      SF_CTRL_SF2_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL      SF_CTRL_SF2_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_1_DO_DLY_SEL_POS))
+
+/* 0x54 : sf2_if_io_dly_3 */
+#define SF_CTRL_SF2_IF_IO_DLY_3_OFFSET   (0x54)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL      SF_CTRL_SF2_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL      SF_CTRL_SF2_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL      SF_CTRL_SF2_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_2_DO_DLY_SEL_POS))
+
+/* 0x58 : sf2_if_io_dly_4 */
+#define SF_CTRL_SF2_IF_IO_DLY_4_OFFSET   (0x58)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL      SF_CTRL_SF2_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL      SF_CTRL_SF2_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL      SF_CTRL_SF2_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF2_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF2_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF2_IO_3_DO_DLY_SEL_POS))
+
+/* 0x5C : sf3_if_io_dly_0 */
+#define SF_CTRL_SF3_IF_IO_DLY_0_OFFSET   (0x5C)
+#define SF_CTRL_SF3_CS_DLY_SEL           SF_CTRL_SF3_CS_DLY_SEL
+#define SF_CTRL_SF3_CS_DLY_SEL_POS       (0U)
+#define SF_CTRL_SF3_CS_DLY_SEL_LEN       (2U)
+#define SF_CTRL_SF3_CS_DLY_SEL_MSK       (((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS)
+#define SF_CTRL_SF3_CS_DLY_SEL_UMSK      (~(((1U << SF_CTRL_SF3_CS_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS_DLY_SEL_POS))
+#define SF_CTRL_SF3_CS2_DLY_SEL          SF_CTRL_SF3_CS2_DLY_SEL
+#define SF_CTRL_SF3_CS2_DLY_SEL_POS      (2U)
+#define SF_CTRL_SF3_CS2_DLY_SEL_LEN      (2U)
+#define SF_CTRL_SF3_CS2_DLY_SEL_MSK      (((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS)
+#define SF_CTRL_SF3_CS2_DLY_SEL_UMSK     (~(((1U << SF_CTRL_SF3_CS2_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CS2_DLY_SEL_POS))
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL      SF_CTRL_SF3_CLK_OUT_DLY_SEL
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS)
+#define SF_CTRL_SF3_CLK_OUT_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_CLK_OUT_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL       SF_CTRL_SF3_DQS_OE_DLY_SEL
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_POS   (26U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_OE_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL       SF_CTRL_SF3_DQS_DI_DLY_SEL
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_POS   (28U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DI_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL       SF_CTRL_SF3_DQS_DO_DLY_SEL
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_POS   (30U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN   (2U)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_MSK   (((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_DQS_DO_DLY_SEL_UMSK  (~(((1U << SF_CTRL_SF3_DQS_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_DQS_DO_DLY_SEL_POS))
+
+/* 0x60 : sf3_if_io_dly_1 */
+#define SF_CTRL_SF3_IF_IO_DLY_1_OFFSET   (0x60)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL      SF_CTRL_SF3_IO_0_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL      SF_CTRL_SF3_IO_0_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL      SF_CTRL_SF3_IO_0_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_0_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_0_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_0_DO_DLY_SEL_POS))
+
+/* 0x64 : sf3_if_io_dly_2 */
+#define SF_CTRL_SF3_IF_IO_DLY_2_OFFSET   (0x64)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL      SF_CTRL_SF3_IO_1_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL      SF_CTRL_SF3_IO_1_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL      SF_CTRL_SF3_IO_1_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_1_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_1_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_1_DO_DLY_SEL_POS))
+
+/* 0x68 : sf3_if_io_dly_3 */
+#define SF_CTRL_SF3_IF_IO_DLY_3_OFFSET   (0x68)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL      SF_CTRL_SF3_IO_2_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL      SF_CTRL_SF3_IO_2_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL      SF_CTRL_SF3_IO_2_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_2_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_2_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_2_DO_DLY_SEL_POS))
+
+/* 0x6C : sf3_if_io_dly_4 */
+#define SF_CTRL_SF3_IF_IO_DLY_4_OFFSET   (0x6C)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL      SF_CTRL_SF3_IO_3_OE_DLY_SEL
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS  (0U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_OE_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_OE_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_OE_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL      SF_CTRL_SF3_IO_3_DI_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS  (8U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DI_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DI_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DI_DLY_SEL_POS))
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL      SF_CTRL_SF3_IO_3_DO_DLY_SEL
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS  (16U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN  (2U)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_MSK  (((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS)
+#define SF_CTRL_SF3_IO_3_DO_DLY_SEL_UMSK (~(((1U << SF_CTRL_SF3_IO_3_DO_DLY_SEL_LEN) - 1) << SF_CTRL_SF3_IO_3_DO_DLY_SEL_POS))
+
+/* 0x70 : sf_ctrl_2 */
+#define SF_CTRL_2_OFFSET                (0x70)
+#define SF_CTRL_SF_IF_PAD_SEL           SF_CTRL_SF_IF_PAD_SEL
+#define SF_CTRL_SF_IF_PAD_SEL_POS       (0U)
+#define SF_CTRL_SF_IF_PAD_SEL_LEN       (2U)
+#define SF_CTRL_SF_IF_PAD_SEL_MSK       (((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_UMSK      (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_POS))
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK      SF_CTRL_SF_IF_PAD_SEL_LOCK
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_POS  (3U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN  (1U)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_MSK  (((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS)
+#define SF_CTRL_SF_IF_PAD_SEL_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_PAD_SEL_LOCK_LEN) - 1) << SF_CTRL_SF_IF_PAD_SEL_LOCK_POS))
+#define SF_CTRL_SF_IF_DTR_EN            SF_CTRL_SF_IF_DTR_EN
+#define SF_CTRL_SF_IF_DTR_EN_POS        (4U)
+#define SF_CTRL_SF_IF_DTR_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_DTR_EN_MSK        (((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS)
+#define SF_CTRL_SF_IF_DTR_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DTR_EN_LEN) - 1) << SF_CTRL_SF_IF_DTR_EN_POS))
+#define SF_CTRL_SF_IF_DQS_EN            SF_CTRL_SF_IF_DQS_EN
+#define SF_CTRL_SF_IF_DQS_EN_POS        (5U)
+#define SF_CTRL_SF_IF_DQS_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_DQS_EN_MSK        (((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS)
+#define SF_CTRL_SF_IF_DQS_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_DQS_EN_LEN) - 1) << SF_CTRL_SF_IF_DQS_EN_POS))
+#define SF_CTRL_SF_IF_BK_SWAP           SF_CTRL_SF_IF_BK_SWAP
+#define SF_CTRL_SF_IF_BK_SWAP_POS       (28U)
+#define SF_CTRL_SF_IF_BK_SWAP_LEN       (1U)
+#define SF_CTRL_SF_IF_BK_SWAP_MSK       (((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS)
+#define SF_CTRL_SF_IF_BK_SWAP_UMSK      (~(((1U << SF_CTRL_SF_IF_BK_SWAP_LEN) - 1) << SF_CTRL_SF_IF_BK_SWAP_POS))
+#define SF_CTRL_SF_IF_BK2_MODE          SF_CTRL_SF_IF_BK2_MODE
+#define SF_CTRL_SF_IF_BK2_MODE_POS      (29U)
+#define SF_CTRL_SF_IF_BK2_MODE_LEN      (1U)
+#define SF_CTRL_SF_IF_BK2_MODE_MSK      (((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS)
+#define SF_CTRL_SF_IF_BK2_MODE_UMSK     (~(((1U << SF_CTRL_SF_IF_BK2_MODE_LEN) - 1) << SF_CTRL_SF_IF_BK2_MODE_POS))
+#define SF_CTRL_SF_IF_BK2_EN            SF_CTRL_SF_IF_BK2_EN
+#define SF_CTRL_SF_IF_BK2_EN_POS        (30U)
+#define SF_CTRL_SF_IF_BK2_EN_LEN        (1U)
+#define SF_CTRL_SF_IF_BK2_EN_MSK        (((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS)
+#define SF_CTRL_SF_IF_BK2_EN_UMSK       (~(((1U << SF_CTRL_SF_IF_BK2_EN_LEN) - 1) << SF_CTRL_SF_IF_BK2_EN_POS))
+#define SF_CTRL_SF_IF_0_BK_SEL          SF_CTRL_SF_IF_0_BK_SEL
+#define SF_CTRL_SF_IF_0_BK_SEL_POS      (31U)
+#define SF_CTRL_SF_IF_0_BK_SEL_LEN      (1U)
+#define SF_CTRL_SF_IF_0_BK_SEL_MSK      (((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS)
+#define SF_CTRL_SF_IF_0_BK_SEL_UMSK     (~(((1U << SF_CTRL_SF_IF_0_BK_SEL_LEN) - 1) << SF_CTRL_SF_IF_0_BK_SEL_POS))
+
+/* 0x74 : sf_ctrl_3 */
+#define SF_CTRL_3_OFFSET                (0x74)
+#define SF_CTRL_SF_CMDS_WRAP_LEN        SF_CTRL_SF_CMDS_WRAP_LEN
+#define SF_CTRL_SF_CMDS_WRAP_LEN_POS    (0U)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_LEN    (4U)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_MSK    (((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS)
+#define SF_CTRL_SF_CMDS_WRAP_LEN_UMSK   (~(((1U << SF_CTRL_SF_CMDS_WRAP_LEN_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_LEN_POS))
+#define SF_CTRL_SF_CMDS_EN              SF_CTRL_SF_CMDS_EN
+#define SF_CTRL_SF_CMDS_EN_POS          (4U)
+#define SF_CTRL_SF_CMDS_EN_LEN          (1U)
+#define SF_CTRL_SF_CMDS_EN_MSK          (((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS)
+#define SF_CTRL_SF_CMDS_EN_UMSK         (~(((1U << SF_CTRL_SF_CMDS_EN_LEN) - 1) << SF_CTRL_SF_CMDS_EN_POS))
+#define SF_CTRL_SF_CMDS_BT_DLY          SF_CTRL_SF_CMDS_BT_DLY
+#define SF_CTRL_SF_CMDS_BT_DLY_POS      (5U)
+#define SF_CTRL_SF_CMDS_BT_DLY_LEN      (3U)
+#define SF_CTRL_SF_CMDS_BT_DLY_MSK      (((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS)
+#define SF_CTRL_SF_CMDS_BT_DLY_UMSK     (~(((1U << SF_CTRL_SF_CMDS_BT_DLY_LEN) - 1) << SF_CTRL_SF_CMDS_BT_DLY_POS))
+#define SF_CTRL_SF_CMDS_BT_EN           SF_CTRL_SF_CMDS_BT_EN
+#define SF_CTRL_SF_CMDS_BT_EN_POS       (8U)
+#define SF_CTRL_SF_CMDS_BT_EN_LEN       (1U)
+#define SF_CTRL_SF_CMDS_BT_EN_MSK       (((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS)
+#define SF_CTRL_SF_CMDS_BT_EN_UMSK      (~(((1U << SF_CTRL_SF_CMDS_BT_EN_LEN) - 1) << SF_CTRL_SF_CMDS_BT_EN_POS))
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI      SF_CTRL_SF_CMDS_WRAP_Q_INI
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_POS  (9U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN  (1U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_MSK  (((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS)
+#define SF_CTRL_SF_CMDS_WRAP_Q_INI_UMSK (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_INI_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_INI_POS))
+#define SF_CTRL_SF_CMDS_WRAP_MODE       SF_CTRL_SF_CMDS_WRAP_MODE
+#define SF_CTRL_SF_CMDS_WRAP_MODE_POS   (10U)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_LEN   (1U)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_MSK   (((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS)
+#define SF_CTRL_SF_CMDS_WRAP_MODE_UMSK  (~(((1U << SF_CTRL_SF_CMDS_WRAP_MODE_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_MODE_POS))
+#define SF_CTRL_SF_CMDS_WRAP_Q          SF_CTRL_SF_CMDS_WRAP_Q
+#define SF_CTRL_SF_CMDS_WRAP_Q_POS      (11U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_LEN      (1U)
+#define SF_CTRL_SF_CMDS_WRAP_Q_MSK      (((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS)
+#define SF_CTRL_SF_CMDS_WRAP_Q_UMSK     (~(((1U << SF_CTRL_SF_CMDS_WRAP_Q_LEN) - 1) << SF_CTRL_SF_CMDS_WRAP_Q_POS))
+#define SF_CTRL_SF_IF_1_ACK_LAT         SF_CTRL_SF_IF_1_ACK_LAT
+#define SF_CTRL_SF_IF_1_ACK_LAT_POS     (29U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_LEN     (3U)
+#define SF_CTRL_SF_IF_1_ACK_LAT_MSK     (((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS)
+#define SF_CTRL_SF_IF_1_ACK_LAT_UMSK    (~(((1U << SF_CTRL_SF_IF_1_ACK_LAT_LEN) - 1) << SF_CTRL_SF_IF_1_ACK_LAT_POS))
+
+/* 0x78 : sf_if_iahb_3 */
+#define SF_CTRL_SF_IF_IAHB_3_OFFSET      (0x78)
+#define SF_CTRL_SF_IF_2_DMY_BYTE         SF_CTRL_SF_IF_2_DMY_BYTE
+#define SF_CTRL_SF_IF_2_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_2_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_2_ADR_BYTE         SF_CTRL_SF_IF_2_ADR_BYTE
+#define SF_CTRL_SF_IF_2_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_2_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_2_CMD_BYTE         SF_CTRL_SF_IF_2_CMD_BYTE
+#define SF_CTRL_SF_IF_2_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_2_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_2_DAT_RW           SF_CTRL_SF_IF_2_DAT_RW
+#define SF_CTRL_SF_IF_2_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_2_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS)
+#define SF_CTRL_SF_IF_2_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_RW_POS))
+#define SF_CTRL_SF_IF_2_DAT_EN           SF_CTRL_SF_IF_2_DAT_EN
+#define SF_CTRL_SF_IF_2_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_2_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS)
+#define SF_CTRL_SF_IF_2_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DAT_EN_POS))
+#define SF_CTRL_SF_IF_2_DMY_EN           SF_CTRL_SF_IF_2_DMY_EN
+#define SF_CTRL_SF_IF_2_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_2_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS)
+#define SF_CTRL_SF_IF_2_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_2_DMY_EN_POS))
+#define SF_CTRL_SF_IF_2_ADR_EN           SF_CTRL_SF_IF_2_ADR_EN
+#define SF_CTRL_SF_IF_2_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_2_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS)
+#define SF_CTRL_SF_IF_2_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_2_ADR_EN_POS))
+#define SF_CTRL_SF_IF_2_CMD_EN           SF_CTRL_SF_IF_2_CMD_EN
+#define SF_CTRL_SF_IF_2_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_2_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_2_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS)
+#define SF_CTRL_SF_IF_2_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_2_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_EN_POS))
+#define SF_CTRL_SF_IF_2_SPI_MODE         SF_CTRL_SF_IF_2_SPI_MODE
+#define SF_CTRL_SF_IF_2_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_2_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_2_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_2_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_2_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN      SF_CTRL_SF_IF_2_QPI_MODE_EN
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_2_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_2_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_2_QPI_MODE_EN_POS))
+
+/* 0x7C : sf_if_iahb_4 */
+#define SF_CTRL_SF_IF_IAHB_4_OFFSET    (0x7C)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0      SF_CTRL_SF_IF_2_CMD_BUF_0
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_0_POS))
+
+/* 0x80 : sf_if_iahb_5 */
+#define SF_CTRL_SF_IF_IAHB_5_OFFSET    (0x80)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1      SF_CTRL_SF_IF_2_CMD_BUF_1
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_2_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_2_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_2_CMD_BUF_1_POS))
+
+/* 0x84 : sf_if_iahb_6 */
+#define SF_CTRL_SF_IF_IAHB_6_OFFSET      (0x84)
+#define SF_CTRL_SF_IF_3_ADR_BYTE         SF_CTRL_SF_IF_3_ADR_BYTE
+#define SF_CTRL_SF_IF_3_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_3_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_3_CMD_BYTE         SF_CTRL_SF_IF_3_CMD_BYTE
+#define SF_CTRL_SF_IF_3_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_3_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_3_ADR_EN           SF_CTRL_SF_IF_3_ADR_EN
+#define SF_CTRL_SF_IF_3_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_3_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_3_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS)
+#define SF_CTRL_SF_IF_3_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_3_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_3_ADR_EN_POS))
+#define SF_CTRL_SF_IF_3_CMD_EN           SF_CTRL_SF_IF_3_CMD_EN
+#define SF_CTRL_SF_IF_3_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_3_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_3_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS)
+#define SF_CTRL_SF_IF_3_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_3_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_EN_POS))
+#define SF_CTRL_SF_IF_3_SPI_MODE         SF_CTRL_SF_IF_3_SPI_MODE
+#define SF_CTRL_SF_IF_3_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_3_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_3_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_3_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_3_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN      SF_CTRL_SF_IF_3_QPI_MODE_EN
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_3_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_3_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_3_QPI_MODE_EN_POS))
+
+/* 0x88 : sf_if_iahb_7 */
+#define SF_CTRL_SF_IF_IAHB_7_OFFSET    (0x88)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0      SF_CTRL_SF_IF_3_CMD_BUF_0
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_3_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_0_POS))
+
+/* 0x8C : sf_if_iahb_8 */
+#define SF_CTRL_SF_IF_IAHB_8_OFFSET    (0x8C)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1      SF_CTRL_SF_IF_3_CMD_BUF_1
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_3_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_3_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_3_CMD_BUF_1_POS))
+
+/* 0x90 : sf_if_iahb_9 */
+#define SF_CTRL_SF_IF_IAHB_9_OFFSET      (0x90)
+#define SF_CTRL_SF_IF_4_DMY_BYTE         SF_CTRL_SF_IF_4_DMY_BYTE
+#define SF_CTRL_SF_IF_4_DMY_BYTE_POS     (12U)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_LEN     (5U)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS)
+#define SF_CTRL_SF_IF_4_DMY_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_DMY_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_BYTE_POS))
+#define SF_CTRL_SF_IF_4_ADR_BYTE         SF_CTRL_SF_IF_4_ADR_BYTE
+#define SF_CTRL_SF_IF_4_ADR_BYTE_POS     (17U)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS)
+#define SF_CTRL_SF_IF_4_ADR_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_ADR_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_BYTE_POS))
+#define SF_CTRL_SF_IF_4_CMD_BYTE         SF_CTRL_SF_IF_4_CMD_BYTE
+#define SF_CTRL_SF_IF_4_CMD_BYTE_POS     (20U)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_LEN     (3U)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_MSK     (((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS)
+#define SF_CTRL_SF_IF_4_CMD_BYTE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_CMD_BYTE_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BYTE_POS))
+#define SF_CTRL_SF_IF_4_DAT_RW           SF_CTRL_SF_IF_4_DAT_RW
+#define SF_CTRL_SF_IF_4_DAT_RW_POS       (23U)
+#define SF_CTRL_SF_IF_4_DAT_RW_LEN       (1U)
+#define SF_CTRL_SF_IF_4_DAT_RW_MSK       (((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS)
+#define SF_CTRL_SF_IF_4_DAT_RW_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DAT_RW_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_RW_POS))
+#define SF_CTRL_SF_IF_4_DAT_EN           SF_CTRL_SF_IF_4_DAT_EN
+#define SF_CTRL_SF_IF_4_DAT_EN_POS       (24U)
+#define SF_CTRL_SF_IF_4_DAT_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_DAT_EN_MSK       (((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS)
+#define SF_CTRL_SF_IF_4_DAT_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DAT_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DAT_EN_POS))
+#define SF_CTRL_SF_IF_4_DMY_EN           SF_CTRL_SF_IF_4_DMY_EN
+#define SF_CTRL_SF_IF_4_DMY_EN_POS       (25U)
+#define SF_CTRL_SF_IF_4_DMY_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_DMY_EN_MSK       (((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS)
+#define SF_CTRL_SF_IF_4_DMY_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_DMY_EN_LEN) - 1) << SF_CTRL_SF_IF_4_DMY_EN_POS))
+#define SF_CTRL_SF_IF_4_ADR_EN           SF_CTRL_SF_IF_4_ADR_EN
+#define SF_CTRL_SF_IF_4_ADR_EN_POS       (26U)
+#define SF_CTRL_SF_IF_4_ADR_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_ADR_EN_MSK       (((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS)
+#define SF_CTRL_SF_IF_4_ADR_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_ADR_EN_LEN) - 1) << SF_CTRL_SF_IF_4_ADR_EN_POS))
+#define SF_CTRL_SF_IF_4_CMD_EN           SF_CTRL_SF_IF_4_CMD_EN
+#define SF_CTRL_SF_IF_4_CMD_EN_POS       (27U)
+#define SF_CTRL_SF_IF_4_CMD_EN_LEN       (1U)
+#define SF_CTRL_SF_IF_4_CMD_EN_MSK       (((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS)
+#define SF_CTRL_SF_IF_4_CMD_EN_UMSK      (~(((1U << SF_CTRL_SF_IF_4_CMD_EN_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_EN_POS))
+#define SF_CTRL_SF_IF_4_SPI_MODE         SF_CTRL_SF_IF_4_SPI_MODE
+#define SF_CTRL_SF_IF_4_SPI_MODE_POS     (28U)
+#define SF_CTRL_SF_IF_4_SPI_MODE_LEN     (3U)
+#define SF_CTRL_SF_IF_4_SPI_MODE_MSK     (((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS)
+#define SF_CTRL_SF_IF_4_SPI_MODE_UMSK    (~(((1U << SF_CTRL_SF_IF_4_SPI_MODE_LEN) - 1) << SF_CTRL_SF_IF_4_SPI_MODE_POS))
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN      SF_CTRL_SF_IF_4_QPI_MODE_EN
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_POS  (31U)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN  (1U)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_MSK  (((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS)
+#define SF_CTRL_SF_IF_4_QPI_MODE_EN_UMSK (~(((1U << SF_CTRL_SF_IF_4_QPI_MODE_EN_LEN) - 1) << SF_CTRL_SF_IF_4_QPI_MODE_EN_POS))
+
+/* 0x94 : sf_if_iahb_10 */
+#define SF_CTRL_SF_IF_IAHB_10_OFFSET   (0x94)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0      SF_CTRL_SF_IF_4_CMD_BUF_0
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_POS  (0U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_LEN  (32U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_MSK  (((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS)
+#define SF_CTRL_SF_IF_4_CMD_BUF_0_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_0_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_0_POS))
+
+/* 0x98 : sf_if_iahb_11 */
+#define SF_CTRL_SF_IF_IAHB_11_OFFSET   (0x98)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1      SF_CTRL_SF_IF_4_CMD_BUF_1
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_POS  (0U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_LEN  (32U)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_MSK  (((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS)
+#define SF_CTRL_SF_IF_4_CMD_BUF_1_UMSK (~(((1U << SF_CTRL_SF_IF_4_CMD_BUF_1_LEN) - 1) << SF_CTRL_SF_IF_4_CMD_BUF_1_POS))
+
+/* 0x9C : sf_if_iahb_12 */
+#define SF_CTRL_SF_IF_IAHB_12_OFFSET       (0x9C)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL      SF_CTRL_SF2_CLK_SF_RX_INV_SEL
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS  (2U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN  (1U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_MSK  (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SEL_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SEL_POS))
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC      SF_CTRL_SF2_CLK_SF_RX_INV_SRC
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS  (3U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN  (1U)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_MSK  (((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS)
+#define SF_CTRL_SF2_CLK_SF_RX_INV_SRC_UMSK (~(((1U << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_LEN) - 1) << SF_CTRL_SF2_CLK_SF_RX_INV_SRC_POS))
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL        SF_CTRL_SF2_CLK_OUT_INV_SEL
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_POS    (4U)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN    (1U)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF2_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF2_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF2_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL        SF_CTRL_SF3_CLK_OUT_INV_SEL
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_POS    (5U)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN    (1U)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_MSK    (((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS)
+#define SF_CTRL_SF3_CLK_OUT_INV_SEL_UMSK   (~(((1U << SF_CTRL_SF3_CLK_OUT_INV_SEL_LEN) - 1) << SF_CTRL_SF3_CLK_OUT_INV_SEL_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_N          SF_CTRL_SF2_IF_READ_DLY_N
+#define SF_CTRL_SF2_IF_READ_DLY_N_POS      (8U)
+#define SF_CTRL_SF2_IF_READ_DLY_N_LEN      (3U)
+#define SF_CTRL_SF2_IF_READ_DLY_N_MSK      (((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_N_UMSK     (~(((1U << SF_CTRL_SF2_IF_READ_DLY_N_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_N_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_EN         SF_CTRL_SF2_IF_READ_DLY_EN
+#define SF_CTRL_SF2_IF_READ_DLY_EN_POS     (11U)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_LEN     (1U)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_MSK     (((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_EN_UMSK    (~(((1U << SF_CTRL_SF2_IF_READ_DLY_EN_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_EN_POS))
+#define SF_CTRL_SF2_IF_READ_DLY_SRC        SF_CTRL_SF2_IF_READ_DLY_SRC
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_POS    (12U)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_LEN    (1U)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_MSK    (((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS)
+#define SF_CTRL_SF2_IF_READ_DLY_SRC_UMSK   (~(((1U << SF_CTRL_SF2_IF_READ_DLY_SRC_LEN) - 1) << SF_CTRL_SF2_IF_READ_DLY_SRC_POS))
+
+/* 0x100 : sf_ctrl_prot_en_rd */
+#define SF_CTRL_PROT_EN_RD_OFFSET         (0x100)
+#define SF_CTRL_PROT_EN_RD                SF_CTRL_PROT_EN_RD
+#define SF_CTRL_PROT_EN_RD_POS            (0U)
+#define SF_CTRL_PROT_EN_RD_LEN            (1U)
+#define SF_CTRL_PROT_EN_RD_MSK            (((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS)
+#define SF_CTRL_PROT_EN_RD_UMSK           (~(((1U << SF_CTRL_PROT_EN_RD_LEN) - 1) << SF_CTRL_PROT_EN_RD_POS))
+#define SF_CTRL_ID0_EN_RD                 SF_CTRL_ID0_EN_RD
+#define SF_CTRL_ID0_EN_RD_POS             (1U)
+#define SF_CTRL_ID0_EN_RD_LEN             (1U)
+#define SF_CTRL_ID0_EN_RD_MSK             (((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS)
+#define SF_CTRL_ID0_EN_RD_UMSK            (~(((1U << SF_CTRL_ID0_EN_RD_LEN) - 1) << SF_CTRL_ID0_EN_RD_POS))
+#define SF_CTRL_ID1_EN_RD                 SF_CTRL_ID1_EN_RD
+#define SF_CTRL_ID1_EN_RD_POS             (2U)
+#define SF_CTRL_ID1_EN_RD_LEN             (1U)
+#define SF_CTRL_ID1_EN_RD_MSK             (((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS)
+#define SF_CTRL_ID1_EN_RD_UMSK            (~(((1U << SF_CTRL_ID1_EN_RD_LEN) - 1) << SF_CTRL_ID1_EN_RD_POS))
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK      SF_CTRL_SF_IF_0_TRIG_WR_LOCK
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS  (30U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN  (1U)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_MSK  (((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS)
+#define SF_CTRL_SF_IF_0_TRIG_WR_LOCK_UMSK (~(((1U << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_LEN) - 1) << SF_CTRL_SF_IF_0_TRIG_WR_LOCK_POS))
+#define SF_CTRL_SF_DBG_DIS                SF_CTRL_SF_DBG_DIS
+#define SF_CTRL_SF_DBG_DIS_POS            (31U)
+#define SF_CTRL_SF_DBG_DIS_LEN            (1U)
+#define SF_CTRL_SF_DBG_DIS_MSK            (((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS)
+#define SF_CTRL_SF_DBG_DIS_UMSK           (~(((1U << SF_CTRL_SF_DBG_DIS_LEN) - 1) << SF_CTRL_SF_DBG_DIS_POS))
+
+/* 0x104 : sf_ctrl_prot_en */
+#define SF_CTRL_PROT_EN_OFFSET (0x104)
+#define SF_CTRL_PROT_EN        SF_CTRL_PROT_EN
+#define SF_CTRL_PROT_EN_POS    (0U)
+#define SF_CTRL_PROT_EN_LEN    (1U)
+#define SF_CTRL_PROT_EN_MSK    (((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS)
+#define SF_CTRL_PROT_EN_UMSK   (~(((1U << SF_CTRL_PROT_EN_LEN) - 1) << SF_CTRL_PROT_EN_POS))
+#define SF_CTRL_ID0_EN         SF_CTRL_ID0_EN
+#define SF_CTRL_ID0_EN_POS     (1U)
+#define SF_CTRL_ID0_EN_LEN     (1U)
+#define SF_CTRL_ID0_EN_MSK     (((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS)
+#define SF_CTRL_ID0_EN_UMSK    (~(((1U << SF_CTRL_ID0_EN_LEN) - 1) << SF_CTRL_ID0_EN_POS))
+#define SF_CTRL_ID1_EN         SF_CTRL_ID1_EN
+#define SF_CTRL_ID1_EN_POS     (2U)
+#define SF_CTRL_ID1_EN_LEN     (1U)
+#define SF_CTRL_ID1_EN_MSK     (((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS)
+#define SF_CTRL_ID1_EN_UMSK    (~(((1U << SF_CTRL_ID1_EN_LEN) - 1) << SF_CTRL_ID1_EN_POS))
+
+/* 0x200 : sf_aes_key_r0_0 */
+#define SF_CTRL_SF_AES_KEY_R0_0_OFFSET (0x200)
+#define SF_CTRL_SF_AES_KEY_R0_0        SF_CTRL_SF_AES_KEY_R0_0
+#define SF_CTRL_SF_AES_KEY_R0_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS)
+#define SF_CTRL_SF_AES_KEY_R0_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_0_POS))
+
+/* 0x204 : sf_aes_key_r0_1 */
+#define SF_CTRL_SF_AES_KEY_R0_1_OFFSET (0x204)
+#define SF_CTRL_SF_AES_KEY_R0_1        SF_CTRL_SF_AES_KEY_R0_1
+#define SF_CTRL_SF_AES_KEY_R0_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS)
+#define SF_CTRL_SF_AES_KEY_R0_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_1_POS))
+
+/* 0x208 : sf_aes_key_r0_2 */
+#define SF_CTRL_SF_AES_KEY_R0_2_OFFSET (0x208)
+#define SF_CTRL_SF_AES_KEY_R0_2        SF_CTRL_SF_AES_KEY_R0_2
+#define SF_CTRL_SF_AES_KEY_R0_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS)
+#define SF_CTRL_SF_AES_KEY_R0_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_2_POS))
+
+/* 0x20C : sf_aes_key_r0_3 */
+#define SF_CTRL_SF_AES_KEY_R0_3_OFFSET (0x20C)
+#define SF_CTRL_SF_AES_KEY_R0_3        SF_CTRL_SF_AES_KEY_R0_3
+#define SF_CTRL_SF_AES_KEY_R0_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS)
+#define SF_CTRL_SF_AES_KEY_R0_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_3_POS))
+
+/* 0x210 : sf_aes_key_r0_4 */
+#define SF_CTRL_SF_AES_KEY_R0_4_OFFSET (0x210)
+#define SF_CTRL_SF_AES_KEY_R0_4        SF_CTRL_SF_AES_KEY_R0_4
+#define SF_CTRL_SF_AES_KEY_R0_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS)
+#define SF_CTRL_SF_AES_KEY_R0_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_4_POS))
+
+/* 0x214 : sf_aes_key_r0_5 */
+#define SF_CTRL_SF_AES_KEY_R0_5_OFFSET (0x214)
+#define SF_CTRL_SF_AES_KEY_R0_5        SF_CTRL_SF_AES_KEY_R0_5
+#define SF_CTRL_SF_AES_KEY_R0_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS)
+#define SF_CTRL_SF_AES_KEY_R0_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_5_POS))
+
+/* 0x218 : sf_aes_key_r0_6 */
+#define SF_CTRL_SF_AES_KEY_R0_6_OFFSET (0x218)
+#define SF_CTRL_SF_AES_KEY_R0_6        SF_CTRL_SF_AES_KEY_R0_6
+#define SF_CTRL_SF_AES_KEY_R0_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS)
+#define SF_CTRL_SF_AES_KEY_R0_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_6_POS))
+
+/* 0x21C : sf_aes_key_r0_7 */
+#define SF_CTRL_SF_AES_KEY_R0_7_OFFSET (0x21C)
+#define SF_CTRL_SF_AES_KEY_R0_7        SF_CTRL_SF_AES_KEY_R0_7
+#define SF_CTRL_SF_AES_KEY_R0_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R0_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R0_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS)
+#define SF_CTRL_SF_AES_KEY_R0_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R0_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R0_7_POS))
+
+/* 0x220 : sf_aes_iv_r0_w0 */
+#define SF_CTRL_SF_AES_IV_R0_W0_OFFSET (0x220)
+#define SF_CTRL_SF_AES_IV_R0_W0        SF_CTRL_SF_AES_IV_R0_W0
+#define SF_CTRL_SF_AES_IV_R0_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS)
+#define SF_CTRL_SF_AES_IV_R0_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W0_POS))
+
+/* 0x224 : sf_aes_iv_r0_w1 */
+#define SF_CTRL_SF_AES_IV_R0_W1_OFFSET (0x224)
+#define SF_CTRL_SF_AES_IV_R0_W1        SF_CTRL_SF_AES_IV_R0_W1
+#define SF_CTRL_SF_AES_IV_R0_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS)
+#define SF_CTRL_SF_AES_IV_R0_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W1_POS))
+
+/* 0x228 : sf_aes_iv_r0_w2 */
+#define SF_CTRL_SF_AES_IV_R0_W2_OFFSET (0x228)
+#define SF_CTRL_SF_AES_IV_R0_W2        SF_CTRL_SF_AES_IV_R0_W2
+#define SF_CTRL_SF_AES_IV_R0_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS)
+#define SF_CTRL_SF_AES_IV_R0_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W2_POS))
+
+/* 0x22C : sf_aes_iv_r0_w3 */
+#define SF_CTRL_SF_AES_IV_R0_W3_OFFSET (0x22C)
+#define SF_CTRL_SF_AES_IV_R0_W3        SF_CTRL_SF_AES_IV_R0_W3
+#define SF_CTRL_SF_AES_IV_R0_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R0_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R0_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS)
+#define SF_CTRL_SF_AES_IV_R0_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R0_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R0_W3_POS))
+
+/* 0x230 : sf_aes_cfg_r0 */
+#define SF_CTRL_SF_AES_CFG_R0_OFFSET            (0x230)
+#define SF_CTRL_SF_AES_REGION_R0_END            SF_CTRL_SF_AES_REGION_R0_END
+#define SF_CTRL_SF_AES_REGION_R0_END_POS        (0U)
+#define SF_CTRL_SF_AES_REGION_R0_END_LEN        (14U)
+#define SF_CTRL_SF_AES_REGION_R0_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS)
+#define SF_CTRL_SF_AES_REGION_R0_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_R0_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_END_POS))
+#define SF_CTRL_SF_AES_REGION_R0_START          SF_CTRL_SF_AES_REGION_R0_START
+#define SF_CTRL_SF_AES_REGION_R0_START_POS      (14U)
+#define SF_CTRL_SF_AES_REGION_R0_START_LEN      (14U)
+#define SF_CTRL_SF_AES_REGION_R0_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS)
+#define SF_CTRL_SF_AES_REGION_R0_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_R0_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_START_POS))
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN      SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_EN             SF_CTRL_SF_AES_REGION_R0_EN
+#define SF_CTRL_SF_AES_REGION_R0_EN_POS         (30U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_REGION_R0_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS)
+#define SF_CTRL_SF_AES_REGION_R0_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_R0_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_EN_POS))
+#define SF_CTRL_SF_AES_REGION_R0_LOCK           SF_CTRL_SF_AES_REGION_R0_LOCK
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_R0_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_R0_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_R0_LOCK_POS))
+
+/* 0x300 : sf_aes_key_r1_0 */
+#define SF_CTRL_SF_AES_KEY_R1_0_OFFSET (0x300)
+#define SF_CTRL_SF_AES_KEY_R1_0        SF_CTRL_SF_AES_KEY_R1_0
+#define SF_CTRL_SF_AES_KEY_R1_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS)
+#define SF_CTRL_SF_AES_KEY_R1_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_0_POS))
+
+/* 0x304 : sf_aes_key_r1_1 */
+#define SF_CTRL_SF_AES_KEY_R1_1_OFFSET (0x304)
+#define SF_CTRL_SF_AES_KEY_R1_1        SF_CTRL_SF_AES_KEY_R1_1
+#define SF_CTRL_SF_AES_KEY_R1_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS)
+#define SF_CTRL_SF_AES_KEY_R1_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_1_POS))
+
+/* 0x308 : sf_aes_key_r1_2 */
+#define SF_CTRL_SF_AES_KEY_R1_2_OFFSET (0x308)
+#define SF_CTRL_SF_AES_KEY_R1_2        SF_CTRL_SF_AES_KEY_R1_2
+#define SF_CTRL_SF_AES_KEY_R1_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS)
+#define SF_CTRL_SF_AES_KEY_R1_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_2_POS))
+
+/* 0x30C : sf_aes_key_r1_3 */
+#define SF_CTRL_SF_AES_KEY_R1_3_OFFSET (0x30C)
+#define SF_CTRL_SF_AES_KEY_R1_3        SF_CTRL_SF_AES_KEY_R1_3
+#define SF_CTRL_SF_AES_KEY_R1_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS)
+#define SF_CTRL_SF_AES_KEY_R1_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_3_POS))
+
+/* 0x310 : sf_aes_key_r1_4 */
+#define SF_CTRL_SF_AES_KEY_R1_4_OFFSET (0x310)
+#define SF_CTRL_SF_AES_KEY_R1_4        SF_CTRL_SF_AES_KEY_R1_4
+#define SF_CTRL_SF_AES_KEY_R1_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS)
+#define SF_CTRL_SF_AES_KEY_R1_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_4_POS))
+
+/* 0x314 : sf_aes_key_r1_5 */
+#define SF_CTRL_SF_AES_KEY_R1_5_OFFSET (0x314)
+#define SF_CTRL_SF_AES_KEY_R1_5        SF_CTRL_SF_AES_KEY_R1_5
+#define SF_CTRL_SF_AES_KEY_R1_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS)
+#define SF_CTRL_SF_AES_KEY_R1_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_5_POS))
+
+/* 0x318 : sf_aes_key_r1_6 */
+#define SF_CTRL_SF_AES_KEY_R1_6_OFFSET (0x318)
+#define SF_CTRL_SF_AES_KEY_R1_6        SF_CTRL_SF_AES_KEY_R1_6
+#define SF_CTRL_SF_AES_KEY_R1_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS)
+#define SF_CTRL_SF_AES_KEY_R1_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_6_POS))
+
+/* 0x31C : sf_aes_key_r1_7 */
+#define SF_CTRL_SF_AES_KEY_R1_7_OFFSET (0x31C)
+#define SF_CTRL_SF_AES_KEY_R1_7        SF_CTRL_SF_AES_KEY_R1_7
+#define SF_CTRL_SF_AES_KEY_R1_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R1_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R1_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS)
+#define SF_CTRL_SF_AES_KEY_R1_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R1_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R1_7_POS))
+
+/* 0x320 : sf_aes_iv_r1_w0 */
+#define SF_CTRL_SF_AES_IV_R1_W0_OFFSET (0x320)
+#define SF_CTRL_SF_AES_IV_R1_W0        SF_CTRL_SF_AES_IV_R1_W0
+#define SF_CTRL_SF_AES_IV_R1_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS)
+#define SF_CTRL_SF_AES_IV_R1_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W0_POS))
+
+/* 0x324 : sf_aes_iv_r1_w1 */
+#define SF_CTRL_SF_AES_IV_R1_W1_OFFSET (0x324)
+#define SF_CTRL_SF_AES_IV_R1_W1        SF_CTRL_SF_AES_IV_R1_W1
+#define SF_CTRL_SF_AES_IV_R1_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS)
+#define SF_CTRL_SF_AES_IV_R1_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W1_POS))
+
+/* 0x328 : sf_aes_iv_r1_w2 */
+#define SF_CTRL_SF_AES_IV_R1_W2_OFFSET (0x328)
+#define SF_CTRL_SF_AES_IV_R1_W2        SF_CTRL_SF_AES_IV_R1_W2
+#define SF_CTRL_SF_AES_IV_R1_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS)
+#define SF_CTRL_SF_AES_IV_R1_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W2_POS))
+
+/* 0x32C : sf_aes_iv_r1_w3 */
+#define SF_CTRL_SF_AES_IV_R1_W3_OFFSET (0x32C)
+#define SF_CTRL_SF_AES_IV_R1_W3        SF_CTRL_SF_AES_IV_R1_W3
+#define SF_CTRL_SF_AES_IV_R1_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R1_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R1_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS)
+#define SF_CTRL_SF_AES_IV_R1_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R1_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R1_W3_POS))
+
+/* 0x330 : sf_aes_r1 */
+#define SF_CTRL_SF_AES_R1_OFFSET         (0x330)
+#define SF_CTRL_SF_AES_R1_END            SF_CTRL_SF_AES_R1_END
+#define SF_CTRL_SF_AES_R1_END_POS        (0U)
+#define SF_CTRL_SF_AES_R1_END_LEN        (14U)
+#define SF_CTRL_SF_AES_R1_END_MSK        (((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS)
+#define SF_CTRL_SF_AES_R1_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R1_END_LEN) - 1) << SF_CTRL_SF_AES_R1_END_POS))
+#define SF_CTRL_SF_AES_R1_START          SF_CTRL_SF_AES_R1_START
+#define SF_CTRL_SF_AES_R1_START_POS      (14U)
+#define SF_CTRL_SF_AES_R1_START_LEN      (14U)
+#define SF_CTRL_SF_AES_R1_START_MSK      (((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS)
+#define SF_CTRL_SF_AES_R1_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R1_START_LEN) - 1) << SF_CTRL_SF_AES_R1_START_POS))
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN      SF_CTRL_SF_AES_R1_HW_KEY_EN
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R1_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R1_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R1_EN             SF_CTRL_SF_AES_R1_EN
+#define SF_CTRL_SF_AES_R1_EN_POS         (30U)
+#define SF_CTRL_SF_AES_R1_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_R1_EN_MSK         (((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS)
+#define SF_CTRL_SF_AES_R1_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R1_EN_LEN) - 1) << SF_CTRL_SF_AES_R1_EN_POS))
+#define SF_CTRL_SF_AES_R1_LOCK           SF_CTRL_SF_AES_R1_LOCK
+#define SF_CTRL_SF_AES_R1_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_R1_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_R1_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS)
+#define SF_CTRL_SF_AES_R1_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R1_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R1_LOCK_POS))
+
+/* 0x400 : sf_aes_key_r2_0 */
+#define SF_CTRL_SF_AES_KEY_R2_0_OFFSET (0x400)
+#define SF_CTRL_SF_AES_KEY_R2_0        SF_CTRL_SF_AES_KEY_R2_0
+#define SF_CTRL_SF_AES_KEY_R2_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS)
+#define SF_CTRL_SF_AES_KEY_R2_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_0_POS))
+
+/* 0x404 : sf_aes_key_r2_1 */
+#define SF_CTRL_SF_AES_KEY_R2_1_OFFSET (0x404)
+#define SF_CTRL_SF_AES_KEY_R2_1        SF_CTRL_SF_AES_KEY_R2_1
+#define SF_CTRL_SF_AES_KEY_R2_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS)
+#define SF_CTRL_SF_AES_KEY_R2_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_1_POS))
+
+/* 0x408 : sf_aes_key_r2_2 */
+#define SF_CTRL_SF_AES_KEY_R2_2_OFFSET (0x408)
+#define SF_CTRL_SF_AES_KEY_R2_2        SF_CTRL_SF_AES_KEY_R2_2
+#define SF_CTRL_SF_AES_KEY_R2_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS)
+#define SF_CTRL_SF_AES_KEY_R2_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_2_POS))
+
+/* 0x40C : sf_aes_key_r2_3 */
+#define SF_CTRL_SF_AES_KEY_R2_3_OFFSET (0x40C)
+#define SF_CTRL_SF_AES_KEY_R2_3        SF_CTRL_SF_AES_KEY_R2_3
+#define SF_CTRL_SF_AES_KEY_R2_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS)
+#define SF_CTRL_SF_AES_KEY_R2_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_3_POS))
+
+/* 0x410 : sf_aes_key_r2_4 */
+#define SF_CTRL_SF_AES_KEY_R2_4_OFFSET (0x410)
+#define SF_CTRL_SF_AES_KEY_R2_4        SF_CTRL_SF_AES_KEY_R2_4
+#define SF_CTRL_SF_AES_KEY_R2_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS)
+#define SF_CTRL_SF_AES_KEY_R2_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_4_POS))
+
+/* 0x414 : sf_aes_key_r2_5 */
+#define SF_CTRL_SF_AES_KEY_R2_5_OFFSET (0x414)
+#define SF_CTRL_SF_AES_KEY_R2_5        SF_CTRL_SF_AES_KEY_R2_5
+#define SF_CTRL_SF_AES_KEY_R2_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS)
+#define SF_CTRL_SF_AES_KEY_R2_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_5_POS))
+
+/* 0x418 : sf_aes_key_r2_6 */
+#define SF_CTRL_SF_AES_KEY_R2_6_OFFSET (0x418)
+#define SF_CTRL_SF_AES_KEY_R2_6        SF_CTRL_SF_AES_KEY_R2_6
+#define SF_CTRL_SF_AES_KEY_R2_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS)
+#define SF_CTRL_SF_AES_KEY_R2_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_6_POS))
+
+/* 0x41C : sf_aes_key_r2_7 */
+#define SF_CTRL_SF_AES_KEY_R2_7_OFFSET (0x41C)
+#define SF_CTRL_SF_AES_KEY_R2_7        SF_CTRL_SF_AES_KEY_R2_7
+#define SF_CTRL_SF_AES_KEY_R2_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_R2_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_R2_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS)
+#define SF_CTRL_SF_AES_KEY_R2_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_R2_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_R2_7_POS))
+
+/* 0x420 : sf_aes_iv_r2_w0 */
+#define SF_CTRL_SF_AES_IV_R2_W0_OFFSET (0x420)
+#define SF_CTRL_SF_AES_IV_R2_W0        SF_CTRL_SF_AES_IV_R2_W0
+#define SF_CTRL_SF_AES_IV_R2_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS)
+#define SF_CTRL_SF_AES_IV_R2_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W0_POS))
+
+/* 0x424 : sf_aes_iv_r2_w1 */
+#define SF_CTRL_SF_AES_IV_R2_W1_OFFSET (0x424)
+#define SF_CTRL_SF_AES_IV_R2_W1        SF_CTRL_SF_AES_IV_R2_W1
+#define SF_CTRL_SF_AES_IV_R2_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS)
+#define SF_CTRL_SF_AES_IV_R2_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W1_POS))
+
+/* 0x428 : sf_aes_iv_r2_w2 */
+#define SF_CTRL_SF_AES_IV_R2_W2_OFFSET (0x428)
+#define SF_CTRL_SF_AES_IV_R2_W2        SF_CTRL_SF_AES_IV_R2_W2
+#define SF_CTRL_SF_AES_IV_R2_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS)
+#define SF_CTRL_SF_AES_IV_R2_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W2_POS))
+
+/* 0x42C : sf_aes_iv_r2_w3 */
+#define SF_CTRL_SF_AES_IV_R2_W3_OFFSET (0x42C)
+#define SF_CTRL_SF_AES_IV_R2_W3        SF_CTRL_SF_AES_IV_R2_W3
+#define SF_CTRL_SF_AES_IV_R2_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_R2_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_R2_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS)
+#define SF_CTRL_SF_AES_IV_R2_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_R2_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_R2_W3_POS))
+
+/* 0x430 : sf_aes_r2 */
+#define SF_CTRL_SF_AES_R2_OFFSET         (0x430)
+#define SF_CTRL_SF_AES_R2_END            SF_CTRL_SF_AES_R2_END
+#define SF_CTRL_SF_AES_R2_END_POS        (0U)
+#define SF_CTRL_SF_AES_R2_END_LEN        (14U)
+#define SF_CTRL_SF_AES_R2_END_MSK        (((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS)
+#define SF_CTRL_SF_AES_R2_END_UMSK       (~(((1U << SF_CTRL_SF_AES_R2_END_LEN) - 1) << SF_CTRL_SF_AES_R2_END_POS))
+#define SF_CTRL_SF_AES_R2_START          SF_CTRL_SF_AES_R2_START
+#define SF_CTRL_SF_AES_R2_START_POS      (14U)
+#define SF_CTRL_SF_AES_R2_START_LEN      (14U)
+#define SF_CTRL_SF_AES_R2_START_MSK      (((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS)
+#define SF_CTRL_SF_AES_R2_START_UMSK     (~(((1U << SF_CTRL_SF_AES_R2_START_LEN) - 1) << SF_CTRL_SF_AES_R2_START_POS))
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN      SF_CTRL_SF_AES_R2_HW_KEY_EN
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_R2_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_R2_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_R2_EN             SF_CTRL_SF_AES_R2_EN
+#define SF_CTRL_SF_AES_R2_EN_POS         (30U)
+#define SF_CTRL_SF_AES_R2_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_R2_EN_MSK         (((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS)
+#define SF_CTRL_SF_AES_R2_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_R2_EN_LEN) - 1) << SF_CTRL_SF_AES_R2_EN_POS))
+#define SF_CTRL_SF_AES_R2_LOCK           SF_CTRL_SF_AES_R2_LOCK
+#define SF_CTRL_SF_AES_R2_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_R2_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_R2_LOCK_MSK       (((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS)
+#define SF_CTRL_SF_AES_R2_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_R2_LOCK_LEN) - 1) << SF_CTRL_SF_AES_R2_LOCK_POS))
+
+/* 0x434 : sf_id0_offset */
+#define SF_CTRL_SF_ID0_OFFSET_OFFSET (0x434)
+#define SF_CTRL_SF_ID0_OFFSET        SF_CTRL_SF_ID0_OFFSET
+#define SF_CTRL_SF_ID0_OFFSET_POS    (0U)
+#define SF_CTRL_SF_ID0_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_ID0_OFFSET_MSK    (((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS)
+#define SF_CTRL_SF_ID0_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_ID0_OFFSET_POS))
+
+/* 0x438 : sf_id1_offset */
+#define SF_CTRL_SF_ID1_OFFSET_OFFSET (0x438)
+#define SF_CTRL_SF_ID1_OFFSET        SF_CTRL_SF_ID1_OFFSET
+#define SF_CTRL_SF_ID1_OFFSET_POS    (0U)
+#define SF_CTRL_SF_ID1_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_ID1_OFFSET_MSK    (((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS)
+#define SF_CTRL_SF_ID1_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_ID1_OFFSET_POS))
+
+/* 0x43C : sf_bk2_id0_offset */
+#define SF_CTRL_SF_BK2_ID0_OFFSET_OFFSET (0x43C)
+#define SF_CTRL_SF_BK2_ID0_OFFSET        SF_CTRL_SF_BK2_ID0_OFFSET
+#define SF_CTRL_SF_BK2_ID0_OFFSET_POS    (0U)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_MSK    (((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS)
+#define SF_CTRL_SF_BK2_ID0_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_BK2_ID0_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID0_OFFSET_POS))
+
+/* 0x440 : sf_bk2_id1_offset */
+#define SF_CTRL_SF_BK2_ID1_OFFSET_OFFSET (0x440)
+#define SF_CTRL_SF_BK2_ID1_OFFSET        SF_CTRL_SF_BK2_ID1_OFFSET
+#define SF_CTRL_SF_BK2_ID1_OFFSET_POS    (0U)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_LEN    (24U)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_MSK    (((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS)
+#define SF_CTRL_SF_BK2_ID1_OFFSET_UMSK   (~(((1U << SF_CTRL_SF_BK2_ID1_OFFSET_LEN) - 1) << SF_CTRL_SF_BK2_ID1_OFFSET_POS))
+
+struct sf_ctrl_reg {
+    /* 0x0 : sf_ctrl_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1         : 2; /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t sf_clk_sf_rx_inv_sel : 1; /* [    2],        r/w,        0x1 */
+            uint32_t sf_clk_out_gate_en   : 1; /* [    3],        r/w,        0x1 */
+            uint32_t sf_clk_out_inv_sel   : 1; /* [    4],        r/w,        0x1 */
+            uint32_t sf_clk_sahb_sram_sel : 1; /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_7         : 2; /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t sf_if_read_dly_n     : 3; /* [10: 8],        r/w,        0x0 */
+            uint32_t sf_if_read_dly_en    : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reserved_12_15       : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t sf_if_int            : 1; /* [   16],          r,        0x0 */
+            uint32_t sf_if_int_clr        : 1; /* [   17],        r/w,        0x1 */
+            uint32_t sf_if_int_set        : 1; /* [   18],        r/w,        0x0 */
+            uint32_t sf_aes_dly_mode      : 1; /* [   19],        r/w,        0x0 */
+            uint32_t sf_aes_dout_endian   : 1; /* [   20],        r/w,        0x1 */
+            uint32_t sf_aes_ctr_plus_en   : 1; /* [   21],        r/w,        0x0 */
+            uint32_t sf_aes_key_endian    : 1; /* [   22],        r/w,        0x1 */
+            uint32_t sf_aes_iv_endian     : 1; /* [   23],        r/w,        0x1 */
+            uint32_t sf_id                : 8; /* [31:24],        r/w,       0x1a */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_0;
+
+    /* 0x4 : sf_ctrl_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_sr_pat_mask  : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t sf_if_sr_pat       : 8; /* [15: 8],        r/w,        0x0 */
+            uint32_t sf_if_sr_int       : 1; /* [   16],          r,        0x0 */
+            uint32_t sf_if_sr_int_en    : 1; /* [   17],        r/w,        0x0 */
+            uint32_t sf_if_sr_int_set   : 1; /* [   18],        r/w,        0x0 */
+            uint32_t reserved_19        : 1; /* [   19],       rsvd,        0x0 */
+            uint32_t sf_if_0_ack_lat    : 3; /* [22:20],        r/w,        0x6 */
+            uint32_t reserved_23        : 1; /* [   23],       rsvd,        0x0 */
+            uint32_t sf_if_reg_hold     : 1; /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_reg_wp       : 1; /* [   25],        r/w,        0x1 */
+            uint32_t sf_ahb2sif_stopped : 1; /* [   26],          r,        0x0 */
+            uint32_t sf_ahb2sif_stop    : 1; /* [   27],        r/w,        0x0 */
+            uint32_t sf_if_fn_sel       : 1; /* [   28],        r/w,        0x1 */
+            uint32_t sf_if_en           : 1; /* [   29],        r/w,        0x1 */
+            uint32_t sf_ahb2sif_en      : 1; /* [   30],        r/w,        0x1 */
+            uint32_t sf_ahb2sram_en     : 1; /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_1;
+
+    /* 0x8 : sf_if_sahb_0 */
+    union {
+        struct
+        {
+            uint32_t sf_if_busy          : 1;  /* [    0],          r,        0x0 */
+            uint32_t sf_if_0_trig        : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_byte    : 10; /* [11: 2],        r/w,        0x0 */
+            uint32_t sf_if_0_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_0_adr_byte    : 3;  /* [19:17],        r/w,        0x0 */
+            uint32_t sf_if_0_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_0_dat_en      : 1;  /* [   24],        r/w,        0x0 */
+            uint32_t sf_if_0_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_0_adr_en      : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t sf_if_0_cmd_en      : 1;  /* [   27],        r/w,        0x0 */
+            uint32_t sf_if_0_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_0_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_0;
+
+    /* 0xC : sf_if_sahb_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_0_cmd_buf_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_1;
+
+    /* 0x10 : sf_if_sahb_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_0_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_sahb_2;
+
+    /* 0x14 : sf_if_iahb_0 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_1_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_1_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_1_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_1_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_1_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_1_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_1_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_1_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_1_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_1_qpi_mode_en : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_0;
+
+    /* 0x18 : sf_if_iahb_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_1_cmd_buf_0 : 32; /* [31: 0],        r/w,  0x3000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_1;
+
+    /* 0x1C : sf_if_iahb_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_1_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_2;
+
+    /* 0x20 : sf_if_status_0 */
+    union {
+        struct
+        {
+            uint32_t sf_if_status_0 : 32; /* [31: 0],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_status_0;
+
+    /* 0x24 : sf_if_status_1 */
+    union {
+        struct
+        {
+            uint32_t sf_if_status_1 : 32; /* [31: 0],          r, 0x20000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_status_1;
+
+    /* 0x28 : sf_aes */
+    union {
+        struct
+        {
+            uint32_t sf_aes_en        : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t sf_aes_mode      : 2;  /* [ 2: 1],        r/w,        0x0 */
+            uint32_t sf_aes_pref_trig : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf_aes_pref_busy : 1;  /* [    4],          r,        0x0 */
+            uint32_t sf_aes_status    : 27; /* [31: 5],          r,        0x2 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes;
+
+    /* 0x2C : sf_ahb2sif_status */
+    union {
+        struct
+        {
+            uint32_t sf_ahb2sif_status : 32; /* [31: 0],          r, 0x10000003 */
+        } BF;
+        uint32_t WORD;
+    } sf_ahb2sif_status;
+
+    /* 0x30 : sf_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t sf_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reserved_4_7       : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t sf_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25     : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_0;
+
+    /* 0x34 : sf_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_1;
+
+    /* 0x38 : sf_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_2;
+
+    /* 0x3C : sf_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_3;
+
+    /* 0x40 : sf_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7       : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15     : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31     : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_io_dly_4;
+
+    /* 0x44 : sf_reserved */
+    union {
+        struct
+        {
+            uint32_t sf_reserved : 32; /* [31: 0],        r/w,     0xffff */
+        } BF;
+        uint32_t WORD;
+    } sf_reserved;
+
+    /* 0x48 : sf2_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf2_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t sf2_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reserved_4_7        : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t sf2_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf2_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf2_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf2_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_0;
+
+    /* 0x4C : sf2_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_1;
+
+    /* 0x50 : sf2_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_2;
+
+    /* 0x54 : sf2_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_3;
+
+    /* 0x58 : sf2_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf2_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf2_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf2_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf2_if_io_dly_4;
+
+    /* 0x5C : sf3_if_io_dly_0 */
+    union {
+        struct
+        {
+            uint32_t sf3_cs_dly_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t sf3_cs2_dly_sel     : 2;  /* [ 3: 2],        r/w,        0x0 */
+            uint32_t reserved_4_7        : 4;  /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t sf3_clk_out_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_25      : 16; /* [25:10],       rsvd,        0x0 */
+            uint32_t sf3_dqs_oe_dly_sel  : 2;  /* [27:26],        r/w,        0x0 */
+            uint32_t sf3_dqs_di_dly_sel  : 2;  /* [29:28],        r/w,        0x0 */
+            uint32_t sf3_dqs_do_dly_sel  : 2;  /* [31:30],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_0;
+
+    /* 0x60 : sf3_if_io_dly_1 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_0_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_0_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_0_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_1;
+
+    /* 0x64 : sf3_if_io_dly_2 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_1_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_1_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_1_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_2;
+
+    /* 0x68 : sf3_if_io_dly_3 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_2_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_2_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_2_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_3;
+
+    /* 0x6C : sf3_if_io_dly_4 */
+    union {
+        struct
+        {
+            uint32_t sf3_io_3_oe_dly_sel : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2_7        : 6;  /* [ 7: 2],       rsvd,        0x0 */
+            uint32_t sf3_io_3_di_dly_sel : 2;  /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reserved_10_15      : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t sf3_io_3_do_dly_sel : 2;  /* [17:16],        r/w,        0x0 */
+            uint32_t reserved_18_31      : 14; /* [31:18],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf3_if_io_dly_4;
+
+    /* 0x70 : sf_ctrl_2 */
+    union {
+        struct
+        {
+            uint32_t sf_if_pad_sel      : 2;  /* [ 1: 0],        r/w,        0x0 */
+            uint32_t reserved_2         : 1;  /* [    2],       rsvd,        0x0 */
+            uint32_t sf_if_pad_sel_lock : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf_if_dtr_en       : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t sf_if_dqs_en       : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t reserved_6_27      : 22; /* [27: 6],       rsvd,        0x0 */
+            uint32_t sf_if_bk_swap      : 1;  /* [   28],        r/w,        0x0 */
+            uint32_t sf_if_bk2_mode     : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_if_bk2_en       : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_if_0_bk_sel     : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_2;
+
+    /* 0x74 : sf_ctrl_3 */
+    union {
+        struct
+        {
+            uint32_t sf_cmds_wrap_len   : 4;  /* [ 3: 0],        r/w,        0x6 */
+            uint32_t sf_cmds_en         : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t sf_cmds_bt_dly     : 3;  /* [ 7: 5],        r/w,        0x2 */
+            uint32_t sf_cmds_bt_en      : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_q_ini : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_mode  : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t sf_cmds_wrap_q     : 1;  /* [   11],          r,        0x0 */
+            uint32_t reserved_12_28     : 17; /* [28:12],       rsvd,        0x0 */
+            uint32_t sf_if_1_ack_lat    : 3;  /* [31:29],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_3;
+
+    /* 0x78 : sf_if_iahb_3 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_2_dmy_byte    : 5;  /* [16:12],        r/w,        0x0 */
+            uint32_t sf_if_2_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_2_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_2_dat_rw      : 1;  /* [   23],        r/w,        0x1 */
+            uint32_t sf_if_2_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_2_dmy_en      : 1;  /* [   25],        r/w,        0x0 */
+            uint32_t sf_if_2_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_2_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_2_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_2_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_3;
+
+    /* 0x7C : sf_if_iahb_4 */
+    union {
+        struct
+        {
+            uint32_t sf_if_2_cmd_buf_0 : 32; /* [31: 0],        r/w, 0x38000000 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_4;
+
+    /* 0x80 : sf_if_iahb_5 */
+    union {
+        struct
+        {
+            uint32_t sf_if_2_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_5;
+
+    /* 0x84 : sf_if_iahb_6 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_16       : 17; /* [16: 0],       rsvd,        0x0 */
+            uint32_t sf_if_3_adr_byte    : 3;  /* [19:17],        r/w,        0x0 */
+            uint32_t sf_if_3_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t reserved_23_25      : 3;  /* [25:23],       rsvd,        0x0 */
+            uint32_t sf_if_3_adr_en      : 1;  /* [   26],        r/w,        0x0 */
+            uint32_t sf_if_3_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_3_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_3_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_6;
+
+    /* 0x88 : sf_if_iahb_7 */
+    union {
+        struct
+        {
+            uint32_t sf_if_3_cmd_buf_0 : 32; /* [31: 0],        r/w, 0xc0000000L */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_7;
+
+    /* 0x8C : sf_if_iahb_8 */
+    union {
+        struct
+        {
+            uint32_t sf_if_3_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_8;
+
+    /* 0x90 : sf_if_iahb_9 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_11       : 12; /* [11: 0],       rsvd,        0x0 */
+            uint32_t sf_if_4_dmy_byte    : 5;  /* [16:12],        r/w,        0x2 */
+            uint32_t sf_if_4_adr_byte    : 3;  /* [19:17],        r/w,        0x2 */
+            uint32_t sf_if_4_cmd_byte    : 3;  /* [22:20],        r/w,        0x0 */
+            uint32_t sf_if_4_dat_rw      : 1;  /* [   23],        r/w,        0x0 */
+            uint32_t sf_if_4_dat_en      : 1;  /* [   24],        r/w,        0x1 */
+            uint32_t sf_if_4_dmy_en      : 1;  /* [   25],        r/w,        0x1 */
+            uint32_t sf_if_4_adr_en      : 1;  /* [   26],        r/w,        0x1 */
+            uint32_t sf_if_4_cmd_en      : 1;  /* [   27],        r/w,        0x1 */
+            uint32_t sf_if_4_spi_mode    : 3;  /* [30:28],        r/w,        0x0 */
+            uint32_t sf_if_4_qpi_mode_en : 1;  /* [   31],        r/w,        0x1 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_9;
+
+    /* 0x94 : sf_if_iahb_10 */
+    union {
+        struct
+        {
+            uint32_t sf_if_4_cmd_buf_0 : 32; /* [31: 0],        r/w, 0xeb000000L */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_10;
+
+    /* 0x98 : sf_if_iahb_11 */
+    union {
+        struct
+        {
+            uint32_t sf_if_4_cmd_buf_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_11;
+
+    /* 0x9C : sf_if_iahb_12 */
+    union {
+        struct
+        {
+            uint32_t reserved_0_1          : 2;  /* [ 1: 0],       rsvd,        0x0 */
+            uint32_t sf2_clk_sf_rx_inv_sel : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t sf2_clk_sf_rx_inv_src : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t sf2_clk_out_inv_sel   : 1;  /* [    4],        r/w,        0x1 */
+            uint32_t sf3_clk_out_inv_sel   : 1;  /* [    5],        r/w,        0x1 */
+            uint32_t reserved_6_7          : 2;  /* [ 7: 6],       rsvd,        0x0 */
+            uint32_t sf2_if_read_dly_n     : 3;  /* [10: 8],        r/w,        0x0 */
+            uint32_t sf2_if_read_dly_en    : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t sf2_if_read_dly_src   : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t reserved_13_31        : 19; /* [31:13],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_if_iahb_12;
+
+    /* 0xa0  reserved */
+    uint8_t RESERVED0xa0[96];
+
+    /* 0x100 : sf_ctrl_prot_en_rd */
+    union {
+        struct
+        {
+            uint32_t sf_ctrl_prot_en_rd   : 1;  /* [    0],          r,        0x1 */
+            uint32_t sf_ctrl_id0_en_rd    : 1;  /* [    1],          r,        0x1 */
+            uint32_t sf_ctrl_id1_en_rd    : 1;  /* [    2],          r,        0x1 */
+            uint32_t reserved_3_29        : 27; /* [29: 3],       rsvd,        0x0 */
+            uint32_t sf_if_0_trig_wr_lock : 1;  /* [   30],          r,        0x0 */
+            uint32_t sf_dbg_dis           : 1;  /* [   31],          r,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_prot_en_rd;
+
+    /* 0x104 : sf_ctrl_prot_en */
+    union {
+        struct
+        {
+            uint32_t sf_ctrl_prot_en : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t sf_ctrl_id0_en  : 1;  /* [    1],        r/w,        0x1 */
+            uint32_t sf_ctrl_id1_en  : 1;  /* [    2],        r/w,        0x1 */
+            uint32_t reserved_3_31   : 29; /* [31: 3],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_ctrl_prot_en;
+
+    /* 0x108  reserved */
+    uint8_t RESERVED0x108[248];
+
+    /* 0x200 : sf_aes_key_r0_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_0;
+
+    /* 0x204 : sf_aes_key_r0_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_1;
+
+    /* 0x208 : sf_aes_key_r0_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_2;
+
+    /* 0x20C : sf_aes_key_r0_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_3;
+
+    /* 0x210 : sf_aes_key_r0_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_4;
+
+    /* 0x214 : sf_aes_key_r0_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_5;
+
+    /* 0x218 : sf_aes_key_r0_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_6;
+
+    /* 0x21C : sf_aes_key_r0_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r0_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r0_7;
+
+    /* 0x220 : sf_aes_iv_r0_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w0;
+
+    /* 0x224 : sf_aes_iv_r0_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w1;
+
+    /* 0x228 : sf_aes_iv_r0_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w2;
+
+    /* 0x22C : sf_aes_iv_r0_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r0_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r0_w3;
+
+    /* 0x230 : sf_aes_cfg_r0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_region_r0_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_region_r0_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28                : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_region_r0_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_region_r0_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_region_r0_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_cfg_r0;
+
+    /* 0x234  reserved */
+    uint8_t RESERVED0x234[204];
+
+    /* 0x300 : sf_aes_key_r1_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_0;
+
+    /* 0x304 : sf_aes_key_r1_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_1;
+
+    /* 0x308 : sf_aes_key_r1_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_2;
+
+    /* 0x30C : sf_aes_key_r1_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_3;
+
+    /* 0x310 : sf_aes_key_r1_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_4;
+
+    /* 0x314 : sf_aes_key_r1_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_5;
+
+    /* 0x318 : sf_aes_key_r1_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_6;
+
+    /* 0x31C : sf_aes_key_r1_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r1_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r1_7;
+
+    /* 0x320 : sf_aes_iv_r1_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w0;
+
+    /* 0x324 : sf_aes_iv_r1_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w1;
+
+    /* 0x328 : sf_aes_iv_r1_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w2;
+
+    /* 0x32C : sf_aes_iv_r1_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r1_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r1_w3;
+
+    /* 0x330 : sf_aes_r1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_r1_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_r1_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_r1_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_r1_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_r1_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_r1;
+
+    /* 0x334  reserved */
+    uint8_t RESERVED0x334[204];
+
+    /* 0x400 : sf_aes_key_r2_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_0;
+
+    /* 0x404 : sf_aes_key_r2_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_1;
+
+    /* 0x408 : sf_aes_key_r2_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_2;
+
+    /* 0x40C : sf_aes_key_r2_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_3;
+
+    /* 0x410 : sf_aes_key_r2_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_4;
+
+    /* 0x414 : sf_aes_key_r2_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_5;
+
+    /* 0x418 : sf_aes_key_r2_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_6;
+
+    /* 0x41C : sf_aes_key_r2_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_r2_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_r2_7;
+
+    /* 0x420 : sf_aes_iv_r2_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w0;
+
+    /* 0x424 : sf_aes_iv_r2_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w1;
+
+    /* 0x428 : sf_aes_iv_r2_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w2;
+
+    /* 0x42C : sf_aes_iv_r2_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_r2_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_r2_w3;
+
+    /* 0x430 : sf_aes_r2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_r2_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_r2_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28         : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_r2_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_r2_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_r2_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_r2;
+
+    /* 0x434 : sf_id0_offset */
+    union {
+        struct
+        {
+            uint32_t sf_id0_offset  : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_id0_offset;
+
+    /* 0x438 : sf_id1_offset */
+    union {
+        struct
+        {
+            uint32_t sf_id1_offset  : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31 : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_id1_offset;
+
+    /* 0x43C : sf_bk2_id0_offset */
+    union {
+        struct
+        {
+            uint32_t sf_bk2_id0_offset : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31    : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_bk2_id0_offset;
+
+    /* 0x440 : sf_bk2_id1_offset */
+    union {
+        struct
+        {
+            uint32_t sf_bk2_id1_offset : 24; /* [23: 0],        r/w,        0x0 */
+            uint32_t reserved_24_31    : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_bk2_id1_offset;
+};
+
+typedef volatile struct sf_ctrl_reg sf_ctrl_reg_t;
+
+/*Following is reg patch*/
+
+/* 0x0 : sf_aes_key_0 */
+#define SF_CTRL_SF_AES_KEY_0_OFFSET (0x0)
+#define SF_CTRL_SF_AES_KEY_0        SF_CTRL_SF_AES_KEY_0
+#define SF_CTRL_SF_AES_KEY_0_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_0_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_0_MSK    (((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS)
+#define SF_CTRL_SF_AES_KEY_0_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_0_LEN) - 1) << SF_CTRL_SF_AES_KEY_0_POS))
+
+/* 0x4 : sf_aes_key_1 */
+#define SF_CTRL_SF_AES_KEY_1_OFFSET (0x4)
+#define SF_CTRL_SF_AES_KEY_1        SF_CTRL_SF_AES_KEY_1
+#define SF_CTRL_SF_AES_KEY_1_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_1_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_1_MSK    (((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS)
+#define SF_CTRL_SF_AES_KEY_1_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_1_LEN) - 1) << SF_CTRL_SF_AES_KEY_1_POS))
+
+/* 0x8 : sf_aes_key_2 */
+#define SF_CTRL_SF_AES_KEY_2_OFFSET (0x8)
+#define SF_CTRL_SF_AES_KEY_2        SF_CTRL_SF_AES_KEY_2
+#define SF_CTRL_SF_AES_KEY_2_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_2_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_2_MSK    (((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS)
+#define SF_CTRL_SF_AES_KEY_2_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_2_LEN) - 1) << SF_CTRL_SF_AES_KEY_2_POS))
+
+/* 0xc : sf_aes_key_3 */
+#define SF_CTRL_SF_AES_KEY_3_OFFSET (0xc)
+#define SF_CTRL_SF_AES_KEY_3        SF_CTRL_SF_AES_KEY_3
+#define SF_CTRL_SF_AES_KEY_3_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_3_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_3_MSK    (((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS)
+#define SF_CTRL_SF_AES_KEY_3_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_3_LEN) - 1) << SF_CTRL_SF_AES_KEY_3_POS))
+
+/* 0x10 : sf_aes_key_4 */
+#define SF_CTRL_SF_AES_KEY_4_OFFSET (0x10)
+#define SF_CTRL_SF_AES_KEY_4        SF_CTRL_SF_AES_KEY_4
+#define SF_CTRL_SF_AES_KEY_4_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_4_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_4_MSK    (((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS)
+#define SF_CTRL_SF_AES_KEY_4_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_4_LEN) - 1) << SF_CTRL_SF_AES_KEY_4_POS))
+
+/* 0x14 : sf_aes_key_5 */
+#define SF_CTRL_SF_AES_KEY_5_OFFSET (0x14)
+#define SF_CTRL_SF_AES_KEY_5        SF_CTRL_SF_AES_KEY_5
+#define SF_CTRL_SF_AES_KEY_5_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_5_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_5_MSK    (((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS)
+#define SF_CTRL_SF_AES_KEY_5_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_5_LEN) - 1) << SF_CTRL_SF_AES_KEY_5_POS))
+
+/* 0x18 : sf_aes_key_6 */
+#define SF_CTRL_SF_AES_KEY_6_OFFSET (0x18)
+#define SF_CTRL_SF_AES_KEY_6        SF_CTRL_SF_AES_KEY_6
+#define SF_CTRL_SF_AES_KEY_6_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_6_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_6_MSK    (((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS)
+#define SF_CTRL_SF_AES_KEY_6_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_6_LEN) - 1) << SF_CTRL_SF_AES_KEY_6_POS))
+
+/* 0x1c : sf_aes_key_7 */
+#define SF_CTRL_SF_AES_KEY_7_OFFSET (0x1c)
+#define SF_CTRL_SF_AES_KEY_7        SF_CTRL_SF_AES_KEY_7
+#define SF_CTRL_SF_AES_KEY_7_POS    (0U)
+#define SF_CTRL_SF_AES_KEY_7_LEN    (32U)
+#define SF_CTRL_SF_AES_KEY_7_MSK    (((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS)
+#define SF_CTRL_SF_AES_KEY_7_UMSK   (~(((1U << SF_CTRL_SF_AES_KEY_7_LEN) - 1) << SF_CTRL_SF_AES_KEY_7_POS))
+
+/* 0x20 : sf_aes_iv_w0 */
+#define SF_CTRL_SF_AES_IV_W0_OFFSET (0x20)
+#define SF_CTRL_SF_AES_IV_W0        SF_CTRL_SF_AES_IV_W0
+#define SF_CTRL_SF_AES_IV_W0_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W0_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W0_MSK    (((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS)
+#define SF_CTRL_SF_AES_IV_W0_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W0_LEN) - 1) << SF_CTRL_SF_AES_IV_W0_POS))
+
+/* 0x24 : sf_aes_iv_w1 */
+#define SF_CTRL_SF_AES_IV_W1_OFFSET (0x24)
+#define SF_CTRL_SF_AES_IV_W1        SF_CTRL_SF_AES_IV_W1
+#define SF_CTRL_SF_AES_IV_W1_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W1_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W1_MSK    (((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS)
+#define SF_CTRL_SF_AES_IV_W1_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W1_LEN) - 1) << SF_CTRL_SF_AES_IV_W1_POS))
+
+/* 0x28 : sf_aes_iv_w2 */
+#define SF_CTRL_SF_AES_IV_W2_OFFSET (0x28)
+#define SF_CTRL_SF_AES_IV_W2        SF_CTRL_SF_AES_IV_W2
+#define SF_CTRL_SF_AES_IV_W2_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W2_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W2_MSK    (((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS)
+#define SF_CTRL_SF_AES_IV_W2_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W2_LEN) - 1) << SF_CTRL_SF_AES_IV_W2_POS))
+
+/* 0x2c : sf_aes_iv_w3 */
+#define SF_CTRL_SF_AES_IV_W3_OFFSET (0x2c)
+#define SF_CTRL_SF_AES_IV_W3        SF_CTRL_SF_AES_IV_W3
+#define SF_CTRL_SF_AES_IV_W3_POS    (0U)
+#define SF_CTRL_SF_AES_IV_W3_LEN    (32U)
+#define SF_CTRL_SF_AES_IV_W3_MSK    (((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS)
+#define SF_CTRL_SF_AES_IV_W3_UMSK   (~(((1U << SF_CTRL_SF_AES_IV_W3_LEN) - 1) << SF_CTRL_SF_AES_IV_W3_POS))
+
+/* 0x30 : sf_aes_cfg */
+#define SF_CTRL_SF_AES_CFG_OFFSET            (0x30)
+#define SF_CTRL_SF_AES_REGION_END            SF_CTRL_SF_AES_REGION_END
+#define SF_CTRL_SF_AES_REGION_END_POS        (0U)
+#define SF_CTRL_SF_AES_REGION_END_LEN        (14U)
+#define SF_CTRL_SF_AES_REGION_END_MSK        (((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS)
+#define SF_CTRL_SF_AES_REGION_END_UMSK       (~(((1U << SF_CTRL_SF_AES_REGION_END_LEN) - 1) << SF_CTRL_SF_AES_REGION_END_POS))
+#define SF_CTRL_SF_AES_REGION_START          SF_CTRL_SF_AES_REGION_START
+#define SF_CTRL_SF_AES_REGION_START_POS      (14U)
+#define SF_CTRL_SF_AES_REGION_START_LEN      (14U)
+#define SF_CTRL_SF_AES_REGION_START_MSK      (((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS)
+#define SF_CTRL_SF_AES_REGION_START_UMSK     (~(((1U << SF_CTRL_SF_AES_REGION_START_LEN) - 1) << SF_CTRL_SF_AES_REGION_START_POS))
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN      SF_CTRL_SF_AES_REGION_HW_KEY_EN
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS  (29U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN  (1U)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_MSK  (((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS)
+#define SF_CTRL_SF_AES_REGION_HW_KEY_EN_UMSK (~(((1U << SF_CTRL_SF_AES_REGION_HW_KEY_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_HW_KEY_EN_POS))
+#define SF_CTRL_SF_AES_REGION_EN             SF_CTRL_SF_AES_REGION_EN
+#define SF_CTRL_SF_AES_REGION_EN_POS         (30U)
+#define SF_CTRL_SF_AES_REGION_EN_LEN         (1U)
+#define SF_CTRL_SF_AES_REGION_EN_MSK         (((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS)
+#define SF_CTRL_SF_AES_REGION_EN_UMSK        (~(((1U << SF_CTRL_SF_AES_REGION_EN_LEN) - 1) << SF_CTRL_SF_AES_REGION_EN_POS))
+#define SF_CTRL_SF_AES_REGION_LOCK           SF_CTRL_SF_AES_REGION_LOCK
+#define SF_CTRL_SF_AES_REGION_LOCK_POS       (31U)
+#define SF_CTRL_SF_AES_REGION_LOCK_LEN       (1U)
+#define SF_CTRL_SF_AES_REGION_LOCK_MSK       (((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS)
+#define SF_CTRL_SF_AES_REGION_LOCK_UMSK      (~(((1U << SF_CTRL_SF_AES_REGION_LOCK_LEN) - 1) << SF_CTRL_SF_AES_REGION_LOCK_POS))
+
+struct sf_ctrl_aes_region_reg {
+    /* 0x0 : sf_aes_key_0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_0;
+
+    /* 0x4 : sf_aes_key_1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_1;
+
+    /* 0x8 : sf_aes_key_2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_2;
+
+    /* 0xc : sf_aes_key_3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_3;
+
+    /* 0x10 : sf_aes_key_4 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_4 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_4;
+
+    /* 0x14 : sf_aes_key_5 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_5 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_5;
+
+    /* 0x18 : sf_aes_key_6 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_6 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_6;
+
+    /* 0x1c : sf_aes_key_7 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_key_7 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_key_7;
+
+    /* 0x20 : sf_aes_iv_w0 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w0 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w0;
+
+    /* 0x24 : sf_aes_iv_w1 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w1 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w1;
+
+    /* 0x28 : sf_aes_iv_w2 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w2 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w2;
+
+    /* 0x2c : sf_aes_iv_w3 */
+    union {
+        struct
+        {
+            uint32_t sf_aes_iv_w3 : 32; /* [31: 0],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_iv_w3;
+
+    /* 0x30 : sf_aes_cfg */
+    union {
+        struct
+        {
+            uint32_t sf_aes_region_end       : 14; /* [13: 0],        r/w,     0x3fff */
+            uint32_t sf_aes_region_start     : 14; /* [27:14],        r/w,        0x0 */
+            uint32_t reserved_28             : 1;  /* [   28],       rsvd,        0x0 */
+            uint32_t sf_aes_region_hw_key_en : 1;  /* [   29],        r/w,        0x0 */
+            uint32_t sf_aes_region_en        : 1;  /* [   30],        r/w,        0x0 */
+            uint32_t sf_aes_region_lock      : 1;  /* [   31],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sf_aes_cfg;
+};
+
+typedef volatile struct sf_ctrl_aes_region_reg sf_ctrl_aes_region_reg_t;
+
+#define SF_CTRL_AES_REGION_OFFSET 0x200
+
+#endif /* __SF_CTRL_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/tzc_sec_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/tzc_sec_reg.h
new file mode 100755
index 0000000000..e436b8c4c0
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/include/hardware/tzc_sec_reg.h
@@ -0,0 +1,256 @@
+/**
+  ******************************************************************************
+  * @file    tzc_sec_reg.h
+  * @version V1.2
+  * @date    2020-03-30
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __TZC_SEC_REG_H__
+#define __TZC_SEC_REG_H__
+
+#include "bl702.h"
+
+/* 0x40 : tzc_rom_ctrl */
+#define TZC_SEC_TZC_ROM_CTRL_OFFSET     (0x40)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN      TZC_SEC_TZC_ROM0_R0_ID0_EN
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_POS  (0U)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN      TZC_SEC_TZC_ROM0_R1_ID0_EN
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_POS  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN      TZC_SEC_TZC_ROM1_R0_ID0_EN
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_POS  (2U)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN      TZC_SEC_TZC_ROM1_R1_ID0_EN
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_POS  (3U)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_ID0_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN      TZC_SEC_TZC_ROM0_R0_ID1_EN
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_POS  (8U)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN      TZC_SEC_TZC_ROM0_R1_ID1_EN
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_POS  (9U)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN      TZC_SEC_TZC_ROM1_R0_ID1_EN
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_POS  (10U)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN      TZC_SEC_TZC_ROM1_R1_ID1_EN
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_POS  (11U)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN  (1U)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_ID1_EN_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_ID1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_ID1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_EN          TZC_SEC_TZC_ROM0_R0_EN
+#define TZC_SEC_TZC_ROM0_R0_EN_POS      (16U)
+#define TZC_SEC_TZC_ROM0_R0_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM0_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS)
+#define TZC_SEC_TZC_ROM0_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_EN_POS))
+#define TZC_SEC_TZC_ROM0_R1_EN          TZC_SEC_TZC_ROM0_R1_EN
+#define TZC_SEC_TZC_ROM0_R1_EN_POS      (17U)
+#define TZC_SEC_TZC_ROM0_R1_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM0_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS)
+#define TZC_SEC_TZC_ROM0_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM0_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_EN_POS))
+#define TZC_SEC_TZC_ROM1_R0_EN          TZC_SEC_TZC_ROM1_R0_EN
+#define TZC_SEC_TZC_ROM1_R0_EN_POS      (18U)
+#define TZC_SEC_TZC_ROM1_R0_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM1_R0_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS)
+#define TZC_SEC_TZC_ROM1_R0_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R0_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_EN_POS))
+#define TZC_SEC_TZC_ROM1_R1_EN          TZC_SEC_TZC_ROM1_R1_EN
+#define TZC_SEC_TZC_ROM1_R1_EN_POS      (19U)
+#define TZC_SEC_TZC_ROM1_R1_EN_LEN      (1U)
+#define TZC_SEC_TZC_ROM1_R1_EN_MSK      (((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS)
+#define TZC_SEC_TZC_ROM1_R1_EN_UMSK     (~(((1U << TZC_SEC_TZC_ROM1_R1_EN_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_EN_POS))
+#define TZC_SEC_TZC_ROM0_R0_LOCK        TZC_SEC_TZC_ROM0_R0_LOCK
+#define TZC_SEC_TZC_ROM0_R0_LOCK_POS    (24U)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS)
+#define TZC_SEC_TZC_ROM0_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_LOCK_POS))
+#define TZC_SEC_TZC_ROM0_R1_LOCK        TZC_SEC_TZC_ROM0_R1_LOCK
+#define TZC_SEC_TZC_ROM0_R1_LOCK_POS    (25U)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS)
+#define TZC_SEC_TZC_ROM0_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_LOCK_POS))
+#define TZC_SEC_TZC_ROM1_R0_LOCK        TZC_SEC_TZC_ROM1_R0_LOCK
+#define TZC_SEC_TZC_ROM1_R0_LOCK_POS    (26U)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS)
+#define TZC_SEC_TZC_ROM1_R0_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_LOCK_POS))
+#define TZC_SEC_TZC_ROM1_R1_LOCK        TZC_SEC_TZC_ROM1_R1_LOCK
+#define TZC_SEC_TZC_ROM1_R1_LOCK_POS    (27U)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS)
+#define TZC_SEC_TZC_ROM1_R1_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_LOCK_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_LOCK_POS))
+#define TZC_SEC_TZC_SBOOT_DONE          TZC_SEC_TZC_SBOOT_DONE
+#define TZC_SEC_TZC_SBOOT_DONE_POS      (28U)
+#define TZC_SEC_TZC_SBOOT_DONE_LEN      (4U)
+#define TZC_SEC_TZC_SBOOT_DONE_MSK      (((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS)
+#define TZC_SEC_TZC_SBOOT_DONE_UMSK     (~(((1U << TZC_SEC_TZC_SBOOT_DONE_LEN) - 1) << TZC_SEC_TZC_SBOOT_DONE_POS))
+
+/* 0x44 : tzc_rom0_r0 */
+#define TZC_SEC_TZC_ROM0_R0_OFFSET     (0x44)
+#define TZC_SEC_TZC_ROM0_R0_END        TZC_SEC_TZC_ROM0_R0_END
+#define TZC_SEC_TZC_ROM0_R0_END_POS    (0U)
+#define TZC_SEC_TZC_ROM0_R0_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM0_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS)
+#define TZC_SEC_TZC_ROM0_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_END_POS))
+#define TZC_SEC_TZC_ROM0_R0_START      TZC_SEC_TZC_ROM0_R0_START
+#define TZC_SEC_TZC_ROM0_R0_START_POS  (16U)
+#define TZC_SEC_TZC_ROM0_R0_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM0_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS)
+#define TZC_SEC_TZC_ROM0_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R0_START_POS))
+
+/* 0x48 : tzc_rom0_r1 */
+#define TZC_SEC_TZC_ROM0_R1_OFFSET     (0x48)
+#define TZC_SEC_TZC_ROM0_R1_END        TZC_SEC_TZC_ROM0_R1_END
+#define TZC_SEC_TZC_ROM0_R1_END_POS    (0U)
+#define TZC_SEC_TZC_ROM0_R1_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM0_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS)
+#define TZC_SEC_TZC_ROM0_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM0_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_END_POS))
+#define TZC_SEC_TZC_ROM0_R1_START      TZC_SEC_TZC_ROM0_R1_START
+#define TZC_SEC_TZC_ROM0_R1_START_POS  (16U)
+#define TZC_SEC_TZC_ROM0_R1_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM0_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS)
+#define TZC_SEC_TZC_ROM0_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM0_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM0_R1_START_POS))
+
+/* 0x4C : tzc_rom1_r0 */
+#define TZC_SEC_TZC_ROM1_R0_OFFSET     (0x4C)
+#define TZC_SEC_TZC_ROM1_R0_END        TZC_SEC_TZC_ROM1_R0_END
+#define TZC_SEC_TZC_ROM1_R0_END_POS    (0U)
+#define TZC_SEC_TZC_ROM1_R0_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM1_R0_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS)
+#define TZC_SEC_TZC_ROM1_R0_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R0_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_END_POS))
+#define TZC_SEC_TZC_ROM1_R0_START      TZC_SEC_TZC_ROM1_R0_START
+#define TZC_SEC_TZC_ROM1_R0_START_POS  (16U)
+#define TZC_SEC_TZC_ROM1_R0_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM1_R0_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS)
+#define TZC_SEC_TZC_ROM1_R0_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R0_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R0_START_POS))
+
+/* 0x50 : tzc_rom1_r1 */
+#define TZC_SEC_TZC_ROM1_R1_OFFSET     (0x50)
+#define TZC_SEC_TZC_ROM1_R1_END        TZC_SEC_TZC_ROM1_R1_END
+#define TZC_SEC_TZC_ROM1_R1_END_POS    (0U)
+#define TZC_SEC_TZC_ROM1_R1_END_LEN    (16U)
+#define TZC_SEC_TZC_ROM1_R1_END_MSK    (((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS)
+#define TZC_SEC_TZC_ROM1_R1_END_UMSK   (~(((1U << TZC_SEC_TZC_ROM1_R1_END_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_END_POS))
+#define TZC_SEC_TZC_ROM1_R1_START      TZC_SEC_TZC_ROM1_R1_START
+#define TZC_SEC_TZC_ROM1_R1_START_POS  (16U)
+#define TZC_SEC_TZC_ROM1_R1_START_LEN  (16U)
+#define TZC_SEC_TZC_ROM1_R1_START_MSK  (((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS)
+#define TZC_SEC_TZC_ROM1_R1_START_UMSK (~(((1U << TZC_SEC_TZC_ROM1_R1_START_LEN) - 1) << TZC_SEC_TZC_ROM1_R1_START_POS))
+
+struct tzc_sec_reg {
+    /* 0x0  reserved */
+    uint8_t RESERVED0x0[64];
+
+    /* 0x40 : tzc_rom_ctrl */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r0_id0_en : 1; /* [    0],        r/w,        0x1 */
+            uint32_t tzc_rom0_r1_id0_en : 1; /* [    1],        r/w,        0x1 */
+            uint32_t tzc_rom1_r0_id0_en : 1; /* [    2],        r/w,        0x1 */
+            uint32_t tzc_rom1_r1_id0_en : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reserved_4_7       : 4; /* [ 7: 4],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_id1_en : 1; /* [    8],        r/w,        0x1 */
+            uint32_t tzc_rom0_r1_id1_en : 1; /* [    9],        r/w,        0x1 */
+            uint32_t tzc_rom1_r0_id1_en : 1; /* [   10],        r/w,        0x1 */
+            uint32_t tzc_rom1_r1_id1_en : 1; /* [   11],        r/w,        0x1 */
+            uint32_t reserved_12_15     : 4; /* [15:12],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_en     : 1; /* [   16],        r/w,        0x0 */
+            uint32_t tzc_rom0_r1_en     : 1; /* [   17],        r/w,        0x0 */
+            uint32_t tzc_rom1_r0_en     : 1; /* [   18],        r/w,        0x0 */
+            uint32_t tzc_rom1_r1_en     : 1; /* [   19],        r/w,        0x0 */
+            uint32_t reserved_20_23     : 4; /* [23:20],       rsvd,        0x0 */
+            uint32_t tzc_rom0_r0_lock   : 1; /* [   24],        r/w,        0x0 */
+            uint32_t tzc_rom0_r1_lock   : 1; /* [   25],        r/w,        0x0 */
+            uint32_t tzc_rom1_r0_lock   : 1; /* [   26],        r/w,        0x0 */
+            uint32_t tzc_rom1_r1_lock   : 1; /* [   27],        r/w,        0x0 */
+            uint32_t tzc_sboot_done     : 4; /* [31:28],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom_ctrl;
+
+    /* 0x44 : tzc_rom0_r0 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom0_r0_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom0_r0;
+
+    /* 0x48 : tzc_rom0_r1 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom0_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom0_r1_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom0_r1;
+
+    /* 0x4C : tzc_rom1_r0 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom1_r0_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom1_r0_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom1_r0;
+
+    /* 0x50 : tzc_rom1_r1 */
+    union {
+        struct
+        {
+            uint32_t tzc_rom1_r1_end   : 16; /* [15: 0],        r/w,     0xffff */
+            uint32_t tzc_rom1_r1_start : 16; /* [31:16],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tzc_rom1_r1;
+};
+
+typedef volatile struct tzc_sec_reg tzc_sec_reg_t;
+
+#endif /* __TZC_SEC_REG_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/port/bl702_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/port/bl702_clock.c
new file mode 100755
index 0000000000..e8f37c0610
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/port/bl702_clock.c
@@ -0,0 +1,19 @@
+#include "bflb_clock.h"
+#include "bl702_clock.h"
+
+uint32_t bflb_clk_get_system_clock(uint8_t type)
+{
+    return 0;
+}
+
+uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
+{
+    if (type == BFLB_DEVICE_TYPE_UART) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0);
+    } else if (type == BFLB_DEVICE_TYPE_SPI) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0);
+    } else if (type == BFLB_DEVICE_TYPE_I2C) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2C0);
+    }
+    return 0;
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_aon.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_aon.c
new file mode 100755
index 0000000000..d166455860
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_aon.c
@@ -0,0 +1,582 @@
+/**
+  ******************************************************************************
+  * @file    bl702_aon.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_aon.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  AON
+ *  @{
+ */
+
+/** @defgroup  AON_Private_Macros
+ *  @{
+ */
+#define AON_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group AON_Private_Macros */
+
+/** @defgroup  AON_Private_Types
+ *  @{
+ */
+
+/*@} end of group AON_Private_Types */
+
+/** @defgroup  AON_Private_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Private_Variables */
+
+/** @defgroup  AON_Global_Variables
+ *  @{
+ */
+
+/*@} end of group AON_Global_Variables */
+
+/** @defgroup  AON_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group AON_Private_Fun_Declaration */
+
+/** @defgroup  AON_Private_Functions
+ *  @{
+ */
+
+/*@} end of group AON_Private_Functions */
+
+/** @defgroup  AON_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Power on MXX band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off MXX band gap
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_MBG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Power OFF */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_On_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+    uint32_t timeOut = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* Polling for ready */
+    do {
+        BL702_Delay_US(10);
+        timeOut++;
+        tmpVal = BL_RD_REG(AON_BASE, AON_TSEN);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, AON_XTAL_RDY) && timeOut < 120);
+
+    if (timeOut >= 120) {
+        return TIMEOUT;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set XTAL cap code
+ *
+ * @param  capIn: Cap code in
+ * @param  capOut: Cap code out
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON, capIn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_OUT_AON, capOut);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    BL702_Delay_US(100);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get XTAL cap code
+ *
+ * @param  None
+ *
+ * @return Cap code
+ *
+*******************************************************************************/
+uint8_t ATTR_CLOCK_SECTION AON_Get_Xtal_CapCode(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, AON_XTAL_CAPCODE_IN_AON);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set XTAL cap code
+ *
+ * @param  extra: cap cpde extra aon
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION AON_Set_Xtal_CapCode_Extra(uint8_t extra)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    if (extra) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, AON_XTAL_CAPCODE_EXTRA_AON);
+    }
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK BL_Err_Type ATTR_CLOCK_SECTION AON_Power_Off_XTAL(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_XTAL_BUF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off bandgap system
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_BG(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power up RF for PLL to work */
+    tmpVal = BL_RD_REG(AON_BASE, AON_BG_SYS_TOP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_BG_SYS_AON);
+    BL_WR_REG(AON_BASE, AON_BG_SYS_TOP, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on LDO11
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO11_SOC(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off LDO11
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO11_SOC(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO11SOC_AON);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    BL702_Delay_US(55);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power on */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(90);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off LDO15_RF
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_LDO15_RF(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* ldo15rf power off */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power on source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_On_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power on sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(10);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power off source follow regular
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Power_Off_SFReg(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off sfreg */
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off the power can be shut down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Enter_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* power off bz */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    /* gating Clock, no more use */
+    //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
+    //tmpVal=tmpVal&(~(1<<6));
+    //tmpVal=tmpVal&(~(1<<7));
+    //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_LowPower_Exit_PDS0(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_RF_TOP_AON);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_MBG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(20);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_LDO15RF_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(60);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_PU_SFREG_AON);
+    BL_WR_REG(AON_BASE, AON_RF_TOP_AON, tmpVal);
+
+    BL702_Delay_US(20);
+
+    /* power on bz */
+    tmpVal = BL_RD_REG(AON_BASE, AON_MISC);
+    tmpVal = BL_SET_REG_BIT(tmpVal, AON_SW_BZ_EN_AON);
+    BL_WR_REG(AON_BASE, AON_MISC, tmpVal);
+
+    /* ungating Clock, no more use */
+    //tmpVal=BL_RD_REG(GLB_BASE,GLB_CGEN_CFG0);
+    //tmpVal=tmpVal|((1<<6));
+    //tmpVal=tmpVal|((1<<7));
+    //BL_WR_REG(GLB_BASE,GLB_CGEN_CFG0,tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on the power powered down in PDS0
+ *
+ * @param  delay: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION AON_Set_LDO11_SOC_Sstart_Delay(uint8_t delay)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((delay <= 0x3));
+
+    /* config ldo11soc_sstart_delay_aon */
+    tmpVal = BL_RD_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_LDO11SOC_SSTART_DELAY_AON, delay);
+    BL_WR_REG(AON_BASE, AON_LDO11SOC_AND_DCTEST, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param
+ *
+ * @return
+ *
+*******************************************************************************/
+BL_Err_Type AON_Set_DCDC18_Top_0(uint8_t voutSel, uint8_t vpfm)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
+    //dcdc18_vout_sel_aon, 1.425V*1.05=1.5V
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_SEL_AON, voutSel);
+    //dcdc18_vpfm_aon
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VPFM_AON, vpfm);
+    BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param
+ *
+ * @return
+ *
+*******************************************************************************/
+BL_Err_Type AON_Set_Xtal_Cfg(uint8_t gmBoost, uint8_t ampCtrl, uint8_t fastStartup)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(AON_BASE, AON_XTAL_CFG);
+    //xtal_gm_boost
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_GM_BOOST_AON, gmBoost);
+    //xtal_amp_ctrl
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_AMP_CTRL_AON, ampCtrl);
+    //xtal_fast_startup
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_XTAL_FAST_STARTUP_AON, fastStartup);
+    BL_WR_REG(AON_BASE, AON_XTAL_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/*@} end of group AON_Public_Functions */
+
+/*@} end of group AON */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_clock.c
new file mode 100755
index 0000000000..0ad6d8715d
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_clock.c
@@ -0,0 +1,738 @@
+/**
+  ******************************************************************************
+  * @file    bl702_clock.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_clock.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  CLOCK
+ *  @{
+ */
+
+/** @defgroup  CLOCK_Private_Macros
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Macros */
+
+/** @defgroup  CLOCK_Private_Types
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Types */
+
+/** @defgroup  CLOCK_Private_Variables
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Variables */
+
+/** @defgroup  CLOCK_Global_Variables
+ *  @{
+ */
+
+/*@} end of group CLOCK_Global_Variables */
+
+/** @defgroup  CLOCK_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Fun_Declaration */
+
+/** @defgroup  CLOCK_Private_Functions
+ *  @{
+ */
+
+/*@} end of group CLOCK_Private_Functions */
+
+/** @defgroup  CLOCK_Public_Functions
+ *  @{
+ */
+
+static inline uint32_t Clock_Xtal_Output(void)
+{
+    /* 32m */
+    return (32 * 1000 * 1000);
+}
+
+static inline uint32_t Clock_XClk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* rc32m */
+        return (32 * 1000 * 1000);
+    } else {
+        /* xtal */
+        return Clock_Xtal_Output();
+    }
+}
+
+static inline uint8_t Clock_Get_MCU_XClk_Sel_Val(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL);
+
+    return (tmpVal & 0x1);
+}
+
+static inline uint8_t Clock_Get_MCU_Root_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL);
+
+    return ((tmpVal >> 1) & 0x1);
+}
+
+static inline uint32_t Clock_MCU_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* pll 57.6m */
+        return (576 * 100 * 1000);
+    } else if (sel == 1) {
+        /* pll 96m */
+        return (96 * 1000 * 1000);
+    } else if (sel == 2) {
+        /* pll 144m */
+        return (144 * 1000 * 1000);
+    } else if (sel == 3) {
+        /* pll 120m */
+        return (120 * 1000 * 1000);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint32_t Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
+{
+    uint32_t tmpVal;
+
+    if (sel == 0) {
+        /* xclk */
+        return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+    } else if (sel == 1) {
+        /* pll */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL);
+        return Clock_MCU_Clk_Mux_Output(tmpVal);
+    } else {
+        return 0;
+    }
+}
+
+static inline uint8_t Clock_Get_MCU_HClk_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
+}
+
+static inline uint8_t Clock_Get_Peri_BClk_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
+}
+
+static inline uint32_t Clock_F32k_Mux_Output(uint8_t sel)
+{
+    uint32_t tmpVal;
+    uint32_t div = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    div = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV);
+
+    if (sel == 0) {
+        /* src32K */
+        return (32 * 1000);
+    } else if (sel == 1) {
+        /* xtal 32K */
+        return (32 * 1000);
+    } else {
+        return Clock_Xtal_Output() / (div + 1);
+    }
+}
+
+static inline uint8_t Clock_Get_F32k_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);
+}
+
+static inline uint32_t Clock_Get_AUPLL_Output()
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM), PDS_CLKPLL_SDMIN);
+
+    if (tmpVal == 0x374BC6) {
+        /* aupll 12288000 */
+        return (12288000);
+    } else if (tmpVal == 0x32CCED) {
+        if (BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL), PDS_CLKPLL_POSTDIV) == 36) {
+            /* aupll 11289600 */
+            return (11289600);
+        } else {
+            /* aupll 5644800 */
+            return (5644800);
+        }
+    } else if (tmpVal == 0x6E978D) {
+        /* aupll 24576000 */
+        return (24576000);
+    } else if (tmpVal == 0x6C0000) {
+        /* aupll 24000000 */
+        return (24000000);
+    } else {
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get System Clock
+ *
+ * @param  type: System clock type
+ *
+ * @return System clock value
+ *
+*******************************************************************************/
+uint32_t Clock_System_Clock_Get(BL_System_Clock_Type type)
+{
+    uint32_t clock = 0;
+    uint32_t div = 0;
+
+    switch (type) {
+        case BL_SYSTEM_CLOCK_XCLK:
+            /*!< mcu xclk clock */
+            return Clock_XClk_Mux_Output(Clock_Get_MCU_XClk_Sel_Val());
+
+        case BL_SYSTEM_CLOCK_ROOT:
+            /*!< mcu root clock */
+            return Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+
+        case BL_SYSTEM_CLOCK_FCLK:
+            /*!< mcu fast clock/cpu clock */
+            clock = Clock_MCU_Root_Clk_Mux_Output(Clock_Get_MCU_Root_Clk_Sel_Val());
+            div = Clock_Get_MCU_HClk_Div_Val();
+            return clock / (div + 1);
+
+        case BL_SYSTEM_CLOCK_BCLK:
+            /*!< mcu peri bus clock */
+            clock = Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
+            div = Clock_Get_Peri_BClk_Div_Val();
+            return clock / (div + 1);
+
+        case BL_SYSTEM_CLOCK_XTAL:
+            /*!< xtal clock */
+            return Clock_Xtal_Output();
+
+        case BL_SYSTEM_CLOCK_F32K:
+            /*!< f32k clock */
+            return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+
+        default:
+            return 0;
+    }
+}
+
+static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* fclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
+    } else {
+        /* 96m */
+        return (96 * 1000 * 1000);
+    }
+}
+
+static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_UART_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
+}
+
+static inline uint32_t Clock_SPI_Clk_Mux_Output(void)
+{
+    /* pbclk */
+    return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+}
+
+static inline uint8_t Clock_Get_SPI_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
+}
+
+static inline uint32_t Clock_I2C_Clk_Mux_Output()
+{
+    /* pbclk */
+    return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+}
+
+static inline uint8_t Clock_Get_I2C_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
+}
+
+static inline uint32_t Clock_I2S_Clk_Mux_Output(void)
+{
+    /* aupll clk */
+    return Clock_Get_AUPLL_Output();
+}
+
+static inline uint8_t Clock_Get_GPADC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* aupll clk */
+        return Clock_Get_AUPLL_Output();
+    } else {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    }
+}
+
+static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
+}
+
+static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
+{
+    uint32_t div = 0;
+
+    if (sel == 1) {
+        /* f32k clk */
+        return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+    } else {
+        div = Clock_Get_GPADC_Div_Val();
+        return Clock_GPADC_Clk_Output(Clock_Get_GPADC_32M_Clk_Sel_Val()) / (div + 1);
+    }
+}
+
+static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_EN);
+}
+
+static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* pll 32m */
+        return (32 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else {
+        /* aupll clk */
+        return Clock_Get_AUPLL_Output();
+    }
+}
+
+static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
+}
+
+static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
+}
+
+// static inline uint32_t Clock_PWM_Clk_Mux_Output(uint8_t sel)
+// {
+//     if (sel == 0) {
+//         /* xclk */
+//         return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+//     } else if (sel == 1) {
+//         /* pbclk */
+//         return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+//     } else {
+//         /* f32k clk */
+//         return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+//     }
+// }
+
+//  static inline uint8_t Clock_Get_PWM_Div_Val(void)
+// {
+//     uint32_t tmpVal;
+
+//     tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CLKDIV);
+
+//     return tmpVal;
+// }
+
+//  static inline uint8_t Clock_Get_PWM_Clk_Sel_Val(void)
+// {
+//     uint32_t tmpVal;
+
+//     tmpVal = BL_RD_REG(PWM_BASE + PWM_CHANNEL_OFFSET, PWM_CONFIG);
+
+//     return BL_GET_REG_BITS_VAL(tmpVal, PWM_REG_CLK_SEL);
+// }
+
+static inline uint32_t Clock_IR_Clk_Mux_Output(void)
+{
+    /* xclk */
+    return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+}
+
+static inline uint8_t Clock_Get_IR_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
+}
+
+static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else {
+        /* 96m */
+        return (96 * 1000 * 1000);
+    }
+}
+
+static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
+}
+
+static inline uint8_t Clock_Get_CAM_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV);
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
+}
+
+static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* 144m */
+        return (144 * 1000 * 1000);
+    } else if (sel == 1) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else {
+        /* 57.6m */
+        return (576 * 100 * 1000);
+    }
+}
+
+static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* sf sel2 */
+        return Clock_SF_SEL2_Clk_Mux_Output(Clock_Get_SF_Clk_Sel2_Val());
+    } else if (sel == 1) {
+        /* 72m */
+        return (72 * 1000 * 1000);
+    } else if (sel == 2) {
+        /* pbclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_BCLK);
+    } else {
+        /* 96m */
+        return (96 * 1000 * 1000);
+    }
+}
+
+static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_SF_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);
+}
+
+static inline uint32_t Clock_QDEC_Clk_Mux_Output(uint8_t sel)
+{
+    if (sel == 0) {
+        /* xclk */
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_XCLK);
+    } else {
+        /* f32k clk */
+        return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+    }
+}
+
+static inline uint8_t Clock_Get_QDEC_Clk_Sel_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_SEL);
+}
+
+static inline uint8_t Clock_Get_QDEC_Div_Val(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_DIV);
+}
+
+// static inline uint32_t Clock_TIMER_Clk_Mux_Output(uint8_t sel)
+// {
+//     if (sel == 0) {
+//         /* fclk */
+//         return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_FCLK);
+//     } else if (sel == 1) {
+//         /* f32k clk */
+//         return Clock_F32k_Mux_Output(Clock_Get_F32k_Sel_Val());
+//     } else if (sel == 2) {
+//         /* 1k */
+//         return (1000);
+//     } else {
+//         /* 32m */
+//         return (32 * 1000 * 1000);
+//     }
+// }
+
+//  static inline uint8_t Clock_Get_TIMER0_Clk_Sel_Val(void)
+// {
+//     uint32_t tmpVal;
+
+//     tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+
+//     return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_1);
+// }
+
+//  static inline uint8_t Clock_Get_TIMER1_Clk_Sel_Val(void)
+// {
+//     uint32_t tmpVal;
+
+//     tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+
+//     return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_2);
+// }
+
+//  static inline uint8_t Clock_Get_WDT_Clk_Sel_Val(void)
+// {
+//     uint32_t tmpVal;
+
+//     tmpVal = BL_RD_REG(TIMER_BASE, TIMER_TCCR);
+
+//     return BL_GET_REG_BITS_VAL(tmpVal, TIMER_CS_WDT);
+// }
+
+/****************************************************************************/ /**
+ * @brief  Get Peripheral Clock
+ *
+ * @param  type: Peripheral clock type
+ *
+ * @return Peripheral clock value
+ *
+*******************************************************************************/
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
+{
+    uint32_t clock = 0;
+    uint32_t div = 0;
+
+    switch (type) {
+        /*!< uart0 clock */
+        case BL_PERIPHERAL_CLOCK_UART0:
+            ATTR_FALLTHROUGH();
+
+        /*!< uart1 clock */
+        case BL_PERIPHERAL_CLOCK_UART1:
+            clock = Clock_UART_Clk_Mux_Output(Clock_Get_UART_Clk_Sel_Val());
+            div = Clock_Get_UART_Div_Val();
+            return clock / (div + 1);
+
+        /*!< FLASH clock */
+        case BL_PERIPHERAL_CLOCK_FLASH:
+            clock = Clock_SF_SEL_Clk_Mux_Output(Clock_Get_SF_Clk_Sel_Val());
+            div = Clock_Get_SF_Div_Val();
+            return clock / (div + 1);
+
+        /*!< spi0 clock */
+        case BL_PERIPHERAL_CLOCK_SPI0:
+            clock = Clock_SPI_Clk_Mux_Output();
+            div = Clock_Get_SPI_Div_Val();
+            return clock / (div + 1);
+
+        /*!< i2c0 clock */
+        case BL_PERIPHERAL_CLOCK_I2C0:
+            clock = Clock_I2C_Clk_Mux_Output();
+            div = Clock_Get_I2C_Div_Val();
+            return clock / (div + 1);
+
+        /*!< I2S clock */
+        case BL_PERIPHERAL_CLOCK_I2S:
+            clock = Clock_I2S_Clk_Mux_Output();
+            return clock;
+
+        /*!< GPADC clock */
+        case BL_PERIPHERAL_CLOCK_GPADC:
+            return Clock_GPADC_Clk_Mux_Output(Clock_Get_GPADC_Clk_Sel_Val());
+
+        /*!< GPDAC clock */
+        case BL_PERIPHERAL_CLOCK_GPDAC:
+            clock = Clock_GPDAC_Clk_Mux_Output(Clock_Get_GPDAC_Clk_Sel_Val());
+            div = Clock_Get_GPDAC_Div_Val();
+            return clock / (div + 1);
+
+        /*!< PWM clock */
+        // case BL_PERIPHERAL_CLOCK_PWM:
+        //     clock = Clock_PWM_Clk_Mux_Output(Clock_Get_PWM_Clk_Sel_Val());
+        //     div = Clock_Get_PWM_Div_Val();
+        //     return clock / div;
+
+        /*!< IR clock */
+        case BL_PERIPHERAL_CLOCK_IR:
+            clock = Clock_IR_Clk_Mux_Output();
+            div = Clock_Get_IR_Div_Val();
+            return clock / (div + 1);
+
+        /*!< CAM clock */
+        case BL_PERIPHERAL_CLOCK_CAM:
+            clock = Clock_CAM_Clk_Mux_Output(Clock_Get_CAM_Clk_Sel_Val());
+            div = Clock_Get_CAM_Div_Val();
+            return clock / (div + 1);
+
+        /*!< QDEC clock */
+        case BL_PERIPHERAL_CLOCK_QDEC:
+            clock = Clock_QDEC_Clk_Mux_Output(Clock_Get_QDEC_Clk_Sel_Val());
+            div = Clock_Get_QDEC_Div_Val();
+            return clock / (div + 1);
+
+            /*!< TIMER0 clock */
+            // case BL_PERIPHERAL_CLOCK_TIMER0:
+            //     return Clock_TIMER_Clk_Mux_Output(Clock_Get_TIMER0_Clk_Sel_Val());
+
+            // /*!< TIMER1 clock */
+            // case BL_PERIPHERAL_CLOCK_TIMER1:
+            //     return Clock_TIMER_Clk_Mux_Output(Clock_Get_TIMER1_Clk_Sel_Val());
+
+            // /*!< WDT clock */
+            // case BL_PERIPHERAL_CLOCK_WDT:
+            //     return Clock_TIMER_Clk_Mux_Output(Clock_Get_WDT_Clk_Sel_Val());
+
+        default:
+            return 0;
+    }
+}
+
+/*@} end of group CLOCK_Public_Functions */
+
+/*@} end of group CLOCK */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_common.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_common.c
new file mode 100755
index 0000000000..a9fafc0355
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_common.c
@@ -0,0 +1,204 @@
+/**
+  ******************************************************************************
+  * @file    bl702_common.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "l1c_reg.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Periph_Driver
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  core:  systemcoreclock
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+#ifdef ARCH_ARM
+#ifndef __GNUC__
+__WEAK
+__ASM void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    lsrs r0, #0x10 muls r0, r1, r0 mov r2, r0 lsrs r2, #0x04 lsrs r2, #0x03 cmp r2, #0x01 beq end cmp r2, #0x00 beq end loop mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 mov r0, r0 subs r2, r2, #0x01 cmp r2, #0x00 bne loop end bx lr
+}
+#else
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    __asm__ __volatile__(
+        "lsr r0,#0x10\n\t"
+        "mul r0,r1,r0\n\t"
+        "mov r2,r0\n\t"
+        "lsr r2,#0x04\n\t"
+        "lsr r2,#0x03\n\t"
+        "cmp r2,#0x01\n\t"
+        "beq end\n\t"
+        "cmp r2,#0x00\n\t"
+        "beq end\n"
+        "loop :"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "mov r0,r0\n\t"
+        "sub r2,r2,#0x01\n\t"
+        "cmp r2,#0x00\n\t"
+        "bne loop\n"
+        "end :"
+        "mov r0,r0\n\t");
+}
+#endif
+#endif
+#ifdef ARCH_RISCV
+__WEAK
+void ATTR_TCM_SECTION ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    uint32_t codeAddress = 0;
+    uint32_t divVal = 40;
+
+    codeAddress = (uint32_t)&ASM_Delay_Us;
+
+    /* 1M=100K*10, so multiple is 10 */
+    /* loop function take 4 instructions, so instructionNum is 4 */
+    /* if codeAddress locate at IROM space and irom_2t_access is 1, then irom2TAccess=2, else irom2TAccess=1 */
+    /* divVal = multiple*instructionNum*irom2TAccess */
+    if (((codeAddress & (0xF << 24)) >> 24) == 0x01) {
+        /* IROM space */
+        if (BL_GET_REG_BITS_VAL(BL_RD_REG(L1C_BASE, L1C_CONFIG), L1C_IROM_2T_ACCESS)) {
+            /* instruction 2T */
+            divVal = 80;
+        }
+    }
+
+    __asm__ __volatile__(
+        ".align 4\n\t"
+        "lw       a4,%1\n\t"
+        "lui   a5,0x18\n\t"
+        "addi  a5,a5,1696\n\t"
+        "divu  a5,a4,a5\n\t"
+        "sw       a5,%1\n\t"
+        "lw       a4,%1\n\t"
+        "lw       a5,%0\n\t"
+        "mul   a5,a4,a5\n\t"
+        "sw       a5,%1\n\t"
+        "lw       a4,%1\n\t"
+        "lw       a5,%2\n\t"
+        "divu  a5,a4,a5\n\t"
+        "sw    a5,%1\n\t"
+        "lw    a5,%1\n\t"
+        "li    a4,0x1\n\t"
+        "beq   a5,zero,end\n\t"
+        "beq   a5,a4,end\n\t"
+        "nop\n\t"
+        "nop\n\t"
+        ".align 4\n\t"
+        "loop  :\n"
+        "addi  a4,a5,-1\n\t"
+        "mv    a5,a4\n\t"
+        "bnez  a5,loop\n\t"
+        "nop\n\t"
+        "end   :\n\t"
+        "nop\n"
+        :                                  /* output */
+        : "m"(cnt), "m"(core), "m"(divVal) /* input */
+        : "t1", "a4", "a5"                 /* destruct description */
+    );
+}
+#endif
+#endif
+
+/****************************************************************************/ /**
+ * @brief      delay us
+ *
+ * @param[in]  cnt:  delay cnt us
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION BL702_Delay_US(uint32_t cnt)
+{
+    ASM_Delay_Us(SystemCoreClockGet(), cnt);
+}
+#endif
+/****************************************************************************/ /**
+ * @brief      delay ms
+ *
+ * @param[in]  cnt:  delay cnt ms
+ *
+ * @return none
+ *
+ *******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION BL702_Delay_MS(uint32_t cnt)
+{
+    uint32_t i = 0;
+    uint32_t count = 0;
+
+    if (cnt >= 1024) {
+        /* delay (n*1024) ms */
+        count = 1024;
+
+        for (i = 0; i < (cnt / 1024); i++) {
+            BL702_Delay_US(1024 * 1000);
+        }
+    }
+
+    if (cnt & 0x3FF) {
+        /* delay (1-1023)ms */
+        count = cnt & 0x3FF;
+        BL702_Delay_US(count * 1000);
+    }
+
+    //BL702_Delay_US(((cnt<<10)-(cnt<<4)-(cnt<<3)));
+}
+#endif
+
+/*
+char *_sbrk(int incr)
+{}
+*/
+/*@} end of group DRIVER_Public_Functions */
+
+/*@} end of group DRIVER_COMMON */
+
+/*@} end of group BL702_Periph_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_ef_cfg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_ef_cfg.c
new file mode 100755
index 0000000000..46c3137792
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_ef_cfg.c
@@ -0,0 +1,410 @@
+/**
+  ******************************************************************************
+  * @file    bl702_ef_ctrl.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_ef_cfg.h"
+#include "bl702_glb.h"
+#include "hardware/ef_data_reg.h"
+
+extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+
+static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
+    {
+        .name = "rc32m",
+        .en_addr = 0x78 * 8 + 1,
+        .parity_addr = 0x78 * 8 + 0,
+        .value_addr = 0x7C * 8 + 4,
+        .value_len = 8,
+    },
+    {
+        .name = "rc32k",
+        .en_addr = 0xEC * 8 + 19,
+        .parity_addr = 0xEC * 8 + 18,
+        .value_addr = 0xEC * 8 + 8,
+        .value_len = 10,
+    },
+    {
+        .name = "gpadc_gain",
+        .en_addr = 0xF0 * 8 + 27,
+        .parity_addr = 0xF0 * 8 + 26,
+        .value_addr = 0xF0 * 8 + 14,
+        .value_len = 12,
+    },
+    {
+        .name = "tsen",
+        .en_addr = 0xF0 * 8 + 13,
+        .parity_addr = 0xF0 * 8 + 12,
+        .value_addr = 0xF0 * 8 + 0,
+        .value_len = 12,
+    }
+};
+
+static GLB_ROOT_CLK_Type rtClk;
+static uint8_t bdiv, hdiv;
+
+/****************************************************************************/ /**
+ * @brief  Efuse read write switch clock save
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void  ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_save(void)
+{
+    /* all API should be place at tcm section */
+    bdiv = GLB_Get_BCLK_Div();
+    hdiv = GLB_Get_HCLK_Div();
+    rtClk = GLB_Get_Root_CLK_Sel();
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
+    GLB_Set_System_CLK_Div(0, 0);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read write switch clock restore
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_efuse_switch_cpu_clock_restore(void)
+{
+    /* all API should be place at tcm section */
+    GLB_Set_System_CLK_Div(hdiv, bdiv);
+    HBN_Set_ROOT_CLK_Sel(rtClk);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse get trim list
+ *
+ * @param  trim_list: Trim list pointer
+ *
+ * @return Trim list count
+ *
+*******************************************************************************/
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
+{
+    *ptrim_list = &trim_list[0];
+    return sizeof(trim_list) / sizeof(trim_list[0]);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read device info
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
+{
+    uint32_t *p = (uint32_t *)deviceInfo;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, p, 1, 1);
+}
+
+void bflb_efuse_get_chipid(uint8_t chipid[8])
+{
+    bflb_efuse_read_mac_address_opt(0, chipid, 1);
+    chipid[6] = 0;
+    chipid[7] = 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Whether MAC address slot is empty
+ *
+ * @param  slot: MAC address slot
+ * @param  reload: whether  reload to check
+ *
+ * @return 0 for all slots full,1 for others
+ *
+*******************************************************************************/
+uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
+{
+    uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
+    uint32_t part1Empty = 0, part2Empty = 0;
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmp2, 1, reload);
+    }
+
+    part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
+    part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
+
+    return (part1Empty && part2Empty);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse write optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  program: Whether program
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval;
+    uint32_t i = 0, cnt;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    /* Change to local order */
+    for (i = 0; i < 3; i++) {
+        tmpval = mac[i];
+        mac[i] = mac[5 - i];
+        mac[5 - i] = tmpval;
+    }
+
+    /* The low 32 bits */
+    tmpval = BL_RDWD_FRM_BYTEP(maclow);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, program);
+    }
+
+    /* The high 16 bits */
+    tmpval = machigh[0] + (machigh[1] << 8);
+    cnt = 0;
+
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    tmpval |= ((cnt & 0x3f) << 16);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, program);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  reload: Whether reload
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval = 0;
+    uint32_t i = 0;
+    uint32_t cnt = 0;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W0_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_LOW_OFFSET, &tmpval, 1, reload);
+    }
+
+    BL_WRWD_TO_BYTEP(maclow, tmpval);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_KEY_SLOT_5_W1_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_DBG_PWD_HIGH_OFFSET, &tmpval, 1, reload);
+    }
+
+    machigh[0] = tmpval & 0xff;
+    machigh[1] = (tmpval >> 8) & 0xff;
+
+    /* Check parity */
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) {
+        /* Change to network order */
+        for (i = 0; i < 3; i++) {
+            tmpval = mac[i];
+            mac[i] = mac[5 - i];
+            mac[5 - i] = tmpval;
+        }
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+float bflb_efuse_get_adc_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+    uint32_t tmp;
+
+    float coe = 1.0;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
+
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            tmp = trim.value;
+
+            if (tmp & 0x800) {
+                tmp = ~tmp;
+                tmp += 1;
+                tmp = tmp & 0xfff;
+                coe = (1.0 + ((float)tmp / 2048.0));
+            } else {
+                coe = (1.0 - ((float)tmp / 2048.0));
+            }
+        }
+    }
+
+    return coe;
+}
+
+uint32_t bflb_efuse_get_adc_tsen_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            return trim.value;
+        }
+    }
+
+    return 2042;
+}
+
+void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
+{
+    uint32_t tmpval = 0;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+    *sign = ((tmpval & EF_DATA_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_EF_SBOOT_SIGN_MODE_POS) & 0x01;
+    *aes = ((tmpval & EF_DATA_EF_SF_AES_MODE_MSK) >> EF_DATA_EF_SF_AES_MODE_POS);
+}
+
+void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if (index > 5) {
+        return;
+    }
+
+    bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+}
+
+void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if (index > 5) {
+        return;
+    }
+
+    bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+}
+
+void bflb_efuse_lock_aes_key_write(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if (index > 5) {
+        return;
+    }
+    /* write lock */
+    if (index <= 3) {
+        lock |= (1 << (index + 19));
+    } else {
+        lock |= (1 << (index + 19));
+        lock |= (1 << (index - 4 + 13));
+    }
+    bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
+}
+
+void bflb_efuse_lock_aes_key_read(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if (index > 5) {
+        return;
+    }
+    /* read lock */
+    lock |= (1 << (index + 26));
+
+    bflb_ef_ctrl_write_direct(NULL, 0x7c, &lock, 1, 1);
+}
+
+void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
+{
+    if (index != 0) {
+        return;
+    }
+    bflb_ef_ctrl_write_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
+}
+
+void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
+{
+    if (index != 0) {
+        return;
+    }
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_glb.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_glb.c
new file mode 100755
index 0000000000..eda05c7746
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_glb.c
@@ -0,0 +1,4056 @@
+/**
+  ******************************************************************************
+  * @file    bl702_glb.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_glb.h"
+#include "bl702_hbn.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  GLB
+ *  @{
+ */
+
+/** @defgroup  GLB_Private_Macros
+ *  @{
+ */
+#define GLB_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+#define GLB_GPIO_Get_Reg(pin)       (glb_gpio_reg_t *)(GLB_BASE + GLB_GPIO_OFFSET + (pin / 2) * 4)
+#define GLB_GPIO_INT0_NUM           (32)
+#define GLB_REG_BCLK_DIS_TRUE       (*(volatile uint32_t *)(0x40000FFC) = (0x00000001))
+#define GLB_REG_BCLK_DIS_FALSE      (*(volatile uint32_t *)(0x40000FFC) = (0x00000000))
+#define GLB_GPIO_INT0_CLEAR_TIMEOUT (32)
+
+/*@} end of group GLB_Private_Macros */
+
+/** @defgroup  GLB_Private_Types
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Types */
+
+/** @defgroup  GLB_Private_Variables
+ *  @{
+ */
+static intCallback_Type *glbBmxErrIntCbfArra[BMX_ERR_INT_ALL] = { NULL };
+static intCallback_Type *glbBmxToIntCbfArra[BMX_TO_INT_ALL] = { NULL };
+static intCallback_Type *glbGpioInt0CbfArra[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                   NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
+static intCallback_Type *glbGpioInt0CbfArra2[GLB_GPIO_INT0_NUM] = { NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
+                                                                    NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL };
+
+/*@} end of group GLB_Private_Variables */
+
+/** @defgroup  GLB_Global_Variables
+ *  @{
+ */
+
+/*@} end of group GLB_Global_Variables */
+
+/** @defgroup  GLB_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Fun_Declaration */
+
+/** @defgroup  GLB_Private_Functions
+ *  @{
+ */
+
+/*@} end of group GLB_Private_Functions */
+
+/** @defgroup  GLB_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  get root clock selection
+ *
+ * @param  None
+ *
+ * @return root clock selection
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+GLB_ROOT_CLK_Type ATTR_CLOCK_SECTION GLB_Get_Root_CLK_Sel(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    switch (BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_ROOT_CLK_SEL)) {
+        case 0:
+            return GLB_ROOT_CLK_RC32M;
+        case 1:
+            return GLB_ROOT_CLK_XTAL;
+        case 2:
+        case 3:
+            return GLB_ROOT_CLK_DLL;
+        default:
+            return GLB_ROOT_CLK_RC32M;
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set System clock divider
+ *
+ * @param  hclkDiv: HCLK divider
+ * @param  bclkDiv: BCLK divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* recommend: fclk<=160MHz, bclk<=80MHz */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, hclkDiv);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, bclkDiv);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    //SystemCoreClockSet(SystemCoreClockGet() / ((uint16_t)hclkDiv + 1));
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get Bus clock divider
+ *
+ * @param  None
+ *
+ * @return Clock Divider
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION GLB_Get_BCLK_Div(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get CPU clock divider
+ *
+ * @param  None
+ *
+ * @return Clock Divider
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_CLOCK_SECTION GLB_Get_HCLK_Div(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  update SystemCoreClock value
+ *
+ * @param  xtalType: XTAL frequency type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType)
+{
+    CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));
+
+    switch (xtalType) {
+        case GLB_DLL_XTAL_NONE:
+            break;
+        case GLB_DLL_XTAL_32M:
+            SystemCoreClockSet(32000000);
+            break;
+        case GLB_DLL_XTAL_RC32M:
+            SystemCoreClockSet(32000000);
+            break;
+        default:
+            break;
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set System clock
+ *
+ * @param  xtalType: XTAL frequency type
+ * @param  clkFreq: clock frequency selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));
+    CHECK_PARAM(IS_GLB_SYS_CLK_TYPE(clkFreq));
+
+    /* reg_bclk_en = reg_hclk_en = reg_fclk_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_BCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_HCLK_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_FCLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+
+    /* Before config XTAL and DLL ,make sure root clk is from RC32M */
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_RC32M);
+    GLB_Set_System_CLK_Div(0, 0);
+    SystemCoreClockSet(32 * 1000 * 1000);
+
+    if (xtalType == GLB_DLL_XTAL_NONE) {
+        if (clkFreq == GLB_SYS_CLK_RC32M) {
+            return SUCCESS;
+        } else {
+            return ERROR;
+        }
+    }
+
+    if (xtalType != GLB_DLL_XTAL_RC32M) {
+        /* power on xtal first */
+        AON_Power_On_XTAL();
+    }
+
+    /* Bl702 make PLL Setting out of RF, so following setting can be removed*/
+    //AON_Power_On_MBG();
+    //AON_Power_On_LDO15_RF();
+
+    /* always power up PLL and enable all PLL clock output */
+    //PDS_Power_On_PLL((PDS_PLL_XTAL_Type)xtalType);
+    //BL702_Delay_US(55);
+    //PDS_Enable_PLL_All_Clks();
+
+    /* always power up DLL and enable all DLL clock output */
+    GLB_Power_Off_DLL();
+    GLB_Power_On_DLL(xtalType);
+    GLB_Enable_DLL_All_Clks();
+
+    /* reg_pll_en = 1, cannot be zero */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PLL_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+
+    /* select pll output clock before select root clock */
+    if (clkFreq >= GLB_SYS_CLK_DLL57P6M) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PLL_SEL, clkFreq - GLB_SYS_CLK_DLL57P6M);
+        BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    }
+    /* select root clock */
+    switch (clkFreq) {
+        case GLB_SYS_CLK_RC32M:
+            break;
+        case GLB_SYS_CLK_XTAL:
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_XTAL);
+            Update_SystemCoreClockWith_XTAL(xtalType);
+            break;
+        case GLB_SYS_CLK_DLL57P6M:
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
+            SystemCoreClockSet(57 * 6000 * 1000);
+            break;
+        case GLB_SYS_CLK_DLL96M:
+            L1C_IROM_2T_Access_Set(ENABLE);
+            GLB_Set_System_CLK_Div(0, 1);
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
+            SystemCoreClockSet(96 * 1000 * 1000);
+            break;
+        case GLB_SYS_CLK_DLL144M:
+            L1C_IROM_2T_Access_Set(ENABLE);
+            GLB_Set_System_CLK_Div(0, 1);
+            HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_DLL);
+            SystemCoreClockSet(144 * 1000 * 1000);
+            break;
+        default:
+            break;
+    }
+
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  This is demo for user that use RC32M as default bootup clock instead of DLL,when APP is
+ *         started, this function can be called to set DLL to 160M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION System_Core_Clock_Update_From_RC32M(void)
+{
+    SF_Ctrl_Cfg_Type sfCtrlCfg = {
+        .owner = SF_CTRL_OWNER_IAHB,
+        .clkDelay = 1,
+        .clkInvert = 1,
+        .rxClkInvert = 1,
+        .doDelay = 0,
+        .diDelay = 0,
+        .oeDelay = 0,
+    };
+    /* Use RC32M as DLL ref source to set up DLL to 144M */
+    GLB_Set_System_CLK(GLB_DLL_XTAL_RC32M, GLB_SYS_CLK_DLL144M);
+    /* Flash controller also need changes since system (bus) clock changed */
+    SF_Ctrl_Enable(&sfCtrlCfg);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set CAM clock
+ *
+ * @param  enable: Enable or disable CAM clock
+ * @param  clkSel: CAM clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_CAM_CLK(uint8_t enable, GLB_CAM_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CAM_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CAM_REF_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set mac154 and zigbee clock
+ *
+ * @param  enable: Enable or disable mac154 and zigbee clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MAC154_ZIGBEE_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_M154_ZBEN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_M154_ZBEN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set BLE clock
+ *
+ * @param  enable: Enable or disable BLE clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_BLE_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BLE_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BLE_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2S clock
+ *
+ * @param  enable: Enable or disable I2S clock
+ * @param  outRef: I2S output ref clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2S_CLK(uint8_t enable, GLB_I2S_OUT_REF_CLK_Type outRef)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_I2S_OUT_REF_CLK_TYPE(outRef));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_0_REF_CLK_OE, outRef);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_I2S0_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set USB clock
+ *
+ * @param  enable: Enable or disable USB clock
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_USB_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_48M_DIV_EN, 1);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_USB_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_USB_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set QDEC clock
+ *
+ * @param  clkSel: QDEC clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_QDEC_CLK(GLB_QDEC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_QDEC_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_QDEC_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DMA clock
+ *
+ * @param  enable: Enable or disable DMA clock
+ * @param  clk: DMA ID type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DMA_CLK(uint8_t enable, GLB_DMA_CLK_ID_Type clk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN);
+    if (enable) {
+        tmpVal2 |= (1 << clk);
+    } else {
+        tmpVal2 &= (~(1 << clk));
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DMA_CLK_EN, tmpVal2);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set IR clock divider
+ *
+ * @param  enable: enable or disable IR clock
+ * @param  clkSel: IR clock type
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_IR_CLK(uint8_t enable, GLB_IR_CLK_SRC_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_IR_CLK_SRC_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x3F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_IR_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set sflash clock
+ *
+ * @param  enable: Enable or disable sflash clock
+ * @param  clkSel: sflash clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+    GLB_DLL_CLK_Type clk;
+
+    CHECK_PARAM(IS_GLB_SFLASH_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x7));
+
+    /* disable SFLASH clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Select flash clock, all Flash CLKs are divied by DLL_288M */
+    clk = GLB_DLL_CLK_288M;
+    GLB_Enable_DLL_Clk(clk);
+    /* clock divider */
+    /* Select flash clock, all Flash CLKs are divied by DLL_288M */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV, div);
+    switch (clkSel) {
+        case GLB_SFLASH_CLK_144M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x0);
+            break;
+        case GLB_SFLASH_CLK_XCLK:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x1);
+            break;
+        case GLB_SFLASH_CLK_57P6M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2, 0x3);
+            break;
+        case GLB_SFLASH_CLK_72M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x1);
+            break;
+        case GLB_SFLASH_CLK_BCLK:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x2);
+            break;
+        case GLB_SFLASH_CLK_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL, 0x3);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* enable or disable flash clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SF_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set UART clock
+ *
+ * @param  enable: Enable or disable UART clock
+ * @param  clkSel: UART clock type
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_UART_CLK(uint8_t enable, HBN_UART_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x7));
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    /* disable UART clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Set div */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    /* Select clock source for uart */
+    HBN_Set_UART_CLK_Sel(clkSel);
+
+    /* Set enable or disable */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG2);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_UART_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select chip clock out 0 type
+ *
+ * @param  clkSel: chip clock out type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Out_0_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_0_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select chip clock out 1 type
+ *
+ * @param  clkSel: chip clock out type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Chip_Out_1_CLK_Sel(GLB_CHIP_CLK_OUT_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_CHIP_CLK_OUT_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CHIP_CLK_OUT_1_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set I2C clock
+ *
+ * @param  enable: Enable or disable I2C clock
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_I2C_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_I2C_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth rx clock
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_RX_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_RX_CLK);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert rf test clock out
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_RF_TEST_O_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_RF_TEST_CLK_O);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set SPI clock
+ *
+ * @param  enable: Enable or disable SPI clock
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((div <= 0x1F));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_SPI_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth tx clock
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_TX_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_TX_CLK);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  invert eth ref clock out
+ *
+ * @param  enable: invert or not invert
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Invert_ETH_REF_O_CLK(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_INV_ETH_REF_CLK_O);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select eth ref clock out
+ *
+ * @param  clkSel: eth ref clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ETH_REF_O_CLK_Sel(GLB_ETH_REF_CLK_OUT_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_SEL_ETH_REF_CLK_O, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG3, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select PKA clock source
+ *
+ * @param  clkSel: PKA clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_PKA_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Software system reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_System_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL702_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software CPU reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_CPU_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL702_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Software power on reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_SW_POR_Reset(void)
+{
+    /***********************************************************************************/
+    /*                                 NOTE                                            */
+    /* "GLB_REG_BCLK_DIS_TRUE + GLB_REG_BCLK_DIS_FALSE" will stop bclk a little while. */
+    /* OCRAM use bclk as source clock. Pay attention to risks when using this API.     */
+    /***********************************************************************************/
+    uint32_t tmpVal;
+
+    /* Swicth clock to 32M as default */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* HCLK is RC32M , so BCLK/HCLK no need divider */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CLK_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV, 0);
+    BL_WR_REG(GLB_BASE, GLB_CLK_CFG0, tmpVal);
+    GLB_REG_BCLK_DIS_TRUE;
+    GLB_REG_BCLK_DIS_FALSE;
+    GLB_CLK_SET_DUMMY_WAIT;
+
+    /* Do reset */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_SYS_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_CPU_RESET);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CTRL_PWRON_RST);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG2, tmpVal);
+
+    /* waiting for reset */
+    while (1) {
+        BL702_Delay_US(10);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Reset slave 1
+ *
+ * @param  slave1: slave num
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_Slave1_Reset(BL_AHB_Slave1_Type slave1)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal &= (~(1 << slave1));
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal |= (1 << slave1);
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+    BL_DRV_DUMMY;
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SWRST_CFG1);
+    tmpVal &= (~(1 << slave1));
+    BL_WR_REG(GLB_BASE, GLB_SWRST_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  clock gate
+ *
+ * @param  enable: ENABLE or DISABLE
+ * @param  slave1: AHB slaveClk type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_AHB_Slave1_Clock_Gate(uint8_t enable, BL_AHB_Slave1_Type slave1)
+{
+    /* gate QDEC <=> gate QDEC0 + QDEC1 +QDEC2 + I2S */
+    /* gate I2S  <=> gate I2S + QDEC2                */
+
+    uint32_t tmpVal = 0;
+
+    if ((BL_AHB_SLAVE1_GLB == slave1) || (BL_AHB_SLAVE1_TZ2 == slave1) ||
+        (BL_AHB_SLAVE1_CCI == slave1) || (BL_AHB_SLAVE1_L1C == slave1) ||
+        (BL_AHB_SLAVE1_PDS_HBN_AON_HBNRAM == slave1)) {
+        /* not support */
+        return ERROR;
+    }
+
+    /* gate QDEC and I2S */
+    if (BL_AHB_SLAVE1_QDEC == slave1) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+        if (enable) {
+            /* clear bit means clock gate */
+            tmpVal &= (~(1 << 0x18));
+            tmpVal &= (~(1 << 0x19));
+            tmpVal &= (~(1 << 0x1A));
+        } else {
+            /* set bit means clock pass */
+            tmpVal |= (1 << 0x18);
+            tmpVal |= (1 << 0x19);
+            tmpVal |= (1 << 0x1A);
+        }
+        BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+        return SUCCESS;
+    }
+
+    /* gate KYS */
+    if (BL_AHB_SLAVE1_KYS == slave1) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+        if (enable) {
+            /* clear bit means clock gate */
+            tmpVal &= (~(1 << 0x1B));
+        } else {
+            /* set bit means clock pass */
+            tmpVal |= (1 << 0x1B);
+        }
+        BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+        return SUCCESS;
+    }
+
+    /* gate I2S and QDEC2 */
+    if (BL_AHB_SLAVE1_I2S == slave1) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+        if (enable) {
+            /* clear bit means clock gate */
+            tmpVal &= (~(1 << 0x1A));
+        } else {
+            /* set bit means clock pass */
+            tmpVal |= (1 << 0x1A);
+        }
+        BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+        return SUCCESS;
+    }
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    if (enable) {
+        /* clear bit means clock gate */
+        tmpVal &= (~(1 << slave1));
+    } else {
+        /* set bit means clock pass */
+        tmpVal |= (1 << slave1);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get IPs clock gate value
+ *
+ * @param  None
+ *
+ * @return clock gate value
+ *
+*******************************************************************************/
+uint64_t GLB_PER_Clock_Gate_Status_Get(void)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t targetBit = 0;
+    uint64_t targetVal = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    for (uint8_t i = 0; i < 64; i++) {
+        targetBit = 0;
+        switch (i) {
+            case GLB_AHB_CLOCK_IP_CPU:
+                targetBit = tmpValCfg0 & (1 << 0);
+                break;
+            case GLB_AHB_CLOCK_IP_SDU:
+                targetBit = tmpValCfg0 & (1 << 1);
+                break;
+            case GLB_AHB_CLOCK_IP_SEC:
+                targetBit = (tmpValCfg0 & (1 << 2)) && (tmpValCfg1 & (1 << 3)) && (tmpValCfg1 & (1 << 4));
+                break;
+            case GLB_AHB_CLOCK_IP_DMA_0:
+                targetBit = (tmpValCfg0 & (1 << 3)) && (tmpValCfg1 & (1 << 12));
+                break;
+            case GLB_AHB_CLOCK_IP_DMA_1:
+                break;
+            case GLB_AHB_CLOCK_IP_DMA_2:
+                break;
+            case GLB_AHB_CLOCK_IP_CCI:
+                targetBit = tmpValCfg0 & (1 << 4);
+                break;
+            case GLB_AHB_CLOCK_IP_RF_TOP:
+                break;
+            case GLB_AHB_CLOCK_IP_GPIP:
+                targetBit = tmpValCfg1 & (1 << 2);
+                break;
+            case GLB_AHB_CLOCK_IP_TZC:
+                targetBit = tmpValCfg1 & (1 << 5);
+                break;
+            case GLB_AHB_CLOCK_IP_EF_CTRL:
+                targetBit = tmpValCfg1 & (1 << 7);
+                break;
+            case GLB_AHB_CLOCK_IP_SF_CTRL:
+                targetBit = tmpValCfg1 & (1 << 11);
+                break;
+            case GLB_AHB_CLOCK_IP_EMAC:
+                targetBit = tmpValCfg1 & (1 << 13);
+                break;
+            case GLB_AHB_CLOCK_IP_UART0:
+                targetBit = tmpValCfg1 & (1 << 16);
+                break;
+            case GLB_AHB_CLOCK_IP_UART1:
+                targetBit = tmpValCfg1 & (1 << 17);
+                break;
+            case GLB_AHB_CLOCK_IP_UART2:
+                break;
+            case GLB_AHB_CLOCK_IP_UART3:
+                break;
+            case GLB_AHB_CLOCK_IP_UART4:
+                break;
+            case GLB_AHB_CLOCK_IP_SPI:
+                targetBit = tmpValCfg1 & (1 << 18);
+                break;
+            case GLB_AHB_CLOCK_IP_I2C:
+                targetBit = tmpValCfg1 & (1 << 19);
+                break;
+            case GLB_AHB_CLOCK_IP_PWM:
+                targetBit = tmpValCfg1 & (1 << 20);
+                break;
+            case GLB_AHB_CLOCK_IP_TIMER:
+                targetBit = tmpValCfg1 & (1 << 21);
+                break;
+            case GLB_AHB_CLOCK_IP_IR:
+                targetBit = tmpValCfg1 & (1 << 22);
+                break;
+            case GLB_AHB_CLOCK_IP_CHECKSUM:
+                targetBit = tmpValCfg1 & (1 << 23);
+                break;
+            case GLB_AHB_CLOCK_IP_QDEC:
+                targetBit = (tmpValCfg1 & (1 << 24)) && (tmpValCfg1 & (1 << 25)) && (tmpValCfg1 & (1 << 26));
+                break;
+            case GLB_AHB_CLOCK_IP_KYS:
+                targetBit = tmpValCfg1 & (1 << 27);
+                break;
+            case GLB_AHB_CLOCK_IP_I2S:
+                targetBit = tmpValCfg1 & (1 << 26);
+                break;
+            case GLB_AHB_CLOCK_IP_USB11:
+                targetBit = tmpValCfg1 & (1 << 28);
+                break;
+            case GLB_AHB_CLOCK_IP_CAM:
+                targetBit = tmpValCfg1 & (1 << 29);
+                break;
+            case GLB_AHB_CLOCK_IP_MJPEG:
+                targetBit = tmpValCfg1 & (1 << 30);
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                targetBit = (tmpValCfg2 & (1 << 0)) && (tmpValCfg2 & (1 << 4));
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                targetBit = tmpValCfg2 & (1 << 0);
+                break;
+            case GLB_AHB_CLOCK_IP_ZB_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                break;
+            case GLB_AHB_CLOCK_IP_WIFI_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                break;
+            case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                break;
+            case GLB_AHB_CLOCK_IP_EMI_MISC:
+                break;
+            case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                break;
+            case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                break;
+            case GLB_AHB_CLOCK_IP_USB20:
+                break;
+            case GLB_AHB_CLOCK_IP_MIX2:
+                break;
+            case GLB_AHB_CLOCK_IP_AUDIO:
+                break;
+            case GLB_AHB_CLOCK_IP_SDH:
+                break;
+            default:
+                break;
+        }
+        if (!targetBit) {
+            targetVal |= ((uint64_t)1 << i);
+        }
+    }
+
+    return targetVal;
+}
+
+/****************************************************************************/ /**
+ * @brief  get first 1 from u64, then clear it
+ *
+ * @param  val: target value
+ * @param  bit: first 1 in bit
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *bit)
+{
+    if (!*val) {
+        return ERROR;
+    }
+
+    for (uint8_t i = 0; i < 64; i++) {
+        if ((*val) & ((uint64_t)1 << i)) {
+            *bit = i;
+            (*val) &= ~((uint64_t)1 << i);
+            break;
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  hold IPs clock
+ *
+ * @param  ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t bitfield = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    while (ips) {
+        if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+            switch (bitfield) {
+                case GLB_AHB_CLOCK_IP_CPU:
+                    tmpValCfg0 &= ~(1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_SDU:
+                    tmpValCfg0 &= ~(1 << 1);
+                    break;
+                case GLB_AHB_CLOCK_IP_SEC:
+                    tmpValCfg0 &= ~(1 << 2);
+                    tmpValCfg1 &= ~(1 << 3);
+                    tmpValCfg1 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_0:
+                    tmpValCfg0 &= ~(1 << 3);
+                    tmpValCfg1 &= ~(1 << 12);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_1:
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_2:
+                    break;
+                case GLB_AHB_CLOCK_IP_CCI:
+                    tmpValCfg0 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_RF_TOP:
+                    break;
+                case GLB_AHB_CLOCK_IP_GPIP:
+                    tmpValCfg1 &= ~(1 << 2);
+                    break;
+                case GLB_AHB_CLOCK_IP_TZC:
+                    tmpValCfg1 &= ~(1 << 5);
+                    break;
+                case GLB_AHB_CLOCK_IP_EF_CTRL:
+                    tmpValCfg1 &= ~(1 << 7);
+                    break;
+                case GLB_AHB_CLOCK_IP_SF_CTRL:
+                    tmpValCfg1 &= ~(1 << 11);
+                    break;
+                case GLB_AHB_CLOCK_IP_EMAC:
+                    tmpValCfg1 &= ~(1 << 13);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART0:
+                    tmpValCfg1 &= ~(1 << 16);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART1:
+                    tmpValCfg1 &= ~(1 << 17);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART2:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART3:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART4:
+                    break;
+                case GLB_AHB_CLOCK_IP_SPI:
+                    tmpValCfg1 &= ~(1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C:
+                    tmpValCfg1 &= ~(1 << 19);
+                    break;
+                case GLB_AHB_CLOCK_IP_PWM:
+                    tmpValCfg1 &= ~(1 << 20);
+                    break;
+                case GLB_AHB_CLOCK_IP_TIMER:
+                    tmpValCfg1 &= ~(1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_IR:
+                    tmpValCfg1 &= ~(1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_CHECKSUM:
+                    tmpValCfg1 &= ~(1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_QDEC:
+                    tmpValCfg1 &= ~(1 << 24);
+                    tmpValCfg1 &= ~(1 << 25);
+                    tmpValCfg1 &= ~(1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_KYS:
+                    tmpValCfg1 &= ~(1 << 27);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2S:
+                    tmpValCfg1 &= ~(1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB11:
+                    tmpValCfg1 &= ~(1 << 28);
+                    break;
+                case GLB_AHB_CLOCK_IP_CAM:
+                    tmpValCfg1 &= ~(1 << 29);
+                    break;
+                case GLB_AHB_CLOCK_IP_MJPEG:
+                    tmpValCfg1 &= ~(1 << 30);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                    tmpValCfg2 &= ~(1 << 0);
+                    tmpValCfg2 &= ~(1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                    tmpValCfg2 &= ~(1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_EMI_MISC:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_USB20:
+                    break;
+                case GLB_AHB_CLOCK_IP_MIX2:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUDIO:
+                    break;
+                case GLB_AHB_CLOCK_IP_SDH:
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  release IPs clock
+ *
+ * @param  ips: GLB_AHB_CLOCK_IP_xxx | GLB_AHB_CLOCK_IP_xxx | ......
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)
+{
+    /* api request from cjy */
+
+    uint32_t tmpValCfg0 = 0;
+    uint32_t tmpValCfg1 = 0;
+    uint32_t tmpValCfg2 = 0;
+    uint32_t bitfield = 0;
+
+    tmpValCfg0 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG0);
+    tmpValCfg1 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG1);
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    while (ips) {
+        if (SUCCESS == GLB_Get_And_Clr_First_Set_From_U64(&ips, &bitfield)) {
+            switch (bitfield) {
+                case GLB_AHB_CLOCK_IP_CPU:
+                    tmpValCfg0 |= (1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_SDU:
+                    tmpValCfg0 |= (1 << 1);
+                    break;
+                case GLB_AHB_CLOCK_IP_SEC:
+                    tmpValCfg0 |= (1 << 2);
+                    tmpValCfg1 |= (1 << 3);
+                    tmpValCfg1 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_0:
+                    tmpValCfg0 |= (1 << 3);
+                    tmpValCfg1 |= (1 << 12);
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_1:
+                    break;
+                case GLB_AHB_CLOCK_IP_DMA_2:
+                    break;
+                case GLB_AHB_CLOCK_IP_CCI:
+                    tmpValCfg0 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_RF_TOP:
+                    break;
+                case GLB_AHB_CLOCK_IP_GPIP:
+                    tmpValCfg1 |= (1 << 2);
+                    break;
+                case GLB_AHB_CLOCK_IP_TZC:
+                    tmpValCfg1 |= (1 << 5);
+                    break;
+                case GLB_AHB_CLOCK_IP_EF_CTRL:
+                    tmpValCfg1 |= (1 << 7);
+                    break;
+                case GLB_AHB_CLOCK_IP_SF_CTRL:
+                    tmpValCfg1 |= (1 << 11);
+                    break;
+                case GLB_AHB_CLOCK_IP_EMAC:
+                    tmpValCfg1 |= (1 << 13);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART0:
+                    tmpValCfg1 |= (1 << 16);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART1:
+                    tmpValCfg1 |= (1 << 17);
+                    break;
+                case GLB_AHB_CLOCK_IP_UART2:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART3:
+                    break;
+                case GLB_AHB_CLOCK_IP_UART4:
+                    break;
+                case GLB_AHB_CLOCK_IP_SPI:
+                    tmpValCfg1 |= (1 << 18);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2C:
+                    tmpValCfg1 |= (1 << 19);
+                    break;
+                case GLB_AHB_CLOCK_IP_PWM:
+                    tmpValCfg1 |= (1 << 20);
+                    break;
+                case GLB_AHB_CLOCK_IP_TIMER:
+                    tmpValCfg1 |= (1 << 21);
+                    break;
+                case GLB_AHB_CLOCK_IP_IR:
+                    tmpValCfg1 |= (1 << 22);
+                    break;
+                case GLB_AHB_CLOCK_IP_CHECKSUM:
+                    tmpValCfg1 |= (1 << 23);
+                    break;
+                case GLB_AHB_CLOCK_IP_QDEC:
+                    tmpValCfg1 |= (1 << 24);
+                    tmpValCfg1 |= (1 << 25);
+                    tmpValCfg1 |= (1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_KYS:
+                    tmpValCfg1 |= (1 << 27);
+                    break;
+                case GLB_AHB_CLOCK_IP_I2S:
+                    tmpValCfg1 |= (1 << 26);
+                    break;
+                case GLB_AHB_CLOCK_IP_USB11:
+                    tmpValCfg1 |= (1 << 28);
+                    break;
+                case GLB_AHB_CLOCK_IP_CAM:
+                    tmpValCfg1 |= (1 << 29);
+                    break;
+                case GLB_AHB_CLOCK_IP_MJPEG:
+                    tmpValCfg1 |= (1 << 30);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_NORMAL:
+                    tmpValCfg2 |= (1 << 0);
+                    tmpValCfg2 |= (1 << 4);
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_NORMAL:
+                    tmpValCfg2 |= (1 << 0);
+                    break;
+                case GLB_AHB_CLOCK_IP_ZB_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_WIFI_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_NORMAL:
+                    break;
+                case GLB_AHB_CLOCK_IP_BT_BLE_2_LP:
+                    break;
+                case GLB_AHB_CLOCK_IP_EMI_MISC:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM0_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_PSRAM1_CTRL:
+                    break;
+                case GLB_AHB_CLOCK_IP_USB20:
+                    break;
+                case GLB_AHB_CLOCK_IP_MIX2:
+                    break;
+                case GLB_AHB_CLOCK_IP_AUDIO:
+                    break;
+                case GLB_AHB_CLOCK_IP_SDH:
+                    break;
+                default:
+                    break;
+            }
+        }
+    }
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG0, tmpValCfg0);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG1, tmpValCfg1);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX init
+ *
+ * @param  BmxCfg: BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Init(BMX_Cfg_Type *BmxCfg)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((BmxCfg->timeoutEn) <= 0xF);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_TIMEOUT_EN, BmxCfg->timeoutEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_EN, BmxCfg->errEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_BMX_ARB_MODE, BmxCfg->arbMod);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(BMX_ERR_IRQn, BMX_ERR_IRQHandler);
+    Interrupt_Handler_Register(BMX_TO_IRQn, BMX_TO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX address monitor enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Addr_Monitor_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX address monitor disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_Addr_Monitor_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG2, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX bus error response enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_BusErrResponse_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX bus error response disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_BMX_BusErrResponse_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG1);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_BMX_ERR_EN);
+    BL_WR_REG(GLB_BASE, GLB_BMX_CFG1, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get BMX error status
+ *
+ * @param  errType: BMX error status type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_BMX_Get_Status(BMX_BUS_ERR_Type errType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_BMX_BUS_ERR_TYPE(errType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_BMX_CFG2);
+    if (errType == BMX_BUS_ERR_TRUSTZONE_DECODE) {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_TZ) ? SET : RESET;
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_BMX_ERR_DEC) ? SET : RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get BMX error address
+ *
+ * @param  None
+ *
+ * @return NP BMX error address
+ *
+*******************************************************************************/
+uint32_t GLB_BMX_Get_Err_Addr(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_BMX_ERR_ADDR);
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX error interrupt callback install
+ *
+ * @param  intType: BMX error interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type BMX_ERR_INT_Callback_Install(BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_BMX_ERR_INT_TYPE(intType));
+
+    glbBmxErrIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX ERR interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_ERR_IRQHandler(void)
+{
+    BMX_ERR_INT_Type intType;
+
+    for (intType = BMX_ERR_INT_ERR; intType < BMX_ERR_INT_ALL; intType++) {
+        if (glbBmxErrIntCbfArra[intType] != NULL) {
+            glbBmxErrIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("BMX_ERR_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  BMX timeout interrupt callback install
+ *
+ * @param  intType: BMX timeout interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type BMX_TIMEOUT_INT_Callback_Install(BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_BMX_TO_INT_TYPE(intType));
+
+    glbBmxToIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  BMX Time Out interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void BMX_TO_IRQHandler(void)
+{
+    BMX_TO_INT_Type intType;
+
+    for (intType = BMX_TO_INT_TIMEOUT; intType < BMX_TO_INT_ALL; intType++) {
+        if (glbBmxToIntCbfArra[intType] != NULL) {
+            glbBmxToIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("BMX_TO_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set sram_ret value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_RET(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_RET, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_ret value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_RET(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_RET);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_slp value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_SLP(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_SLP, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_slp value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_SLP(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_SLP);
+}
+
+/****************************************************************************/ /**
+ * @brief  set sram_param value
+ *
+ * @param  value: value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SRAM_PARM(uint32_t value)
+{
+    BL_WR_REG(GLB_BASE, GLB_SRAM_PARM, value);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get sram_parm value
+ *
+ * @param  None
+ *
+ * @return value
+ *
+*******************************************************************************/
+uint32_t GLB_Get_SRAM_PARM(void)
+{
+    return BL_RD_REG(GLB_BASE, GLB_SRAM_PARM);
+}
+
+/****************************************************************************/ /**
+ * @brief  select EM type
+ *
+ * @param  emType: EM type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_EM_Sel(GLB_EM_Type emType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_EM_TYPE(emType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, emType);
+    BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select pin as EMAC or CAM
+ *
+ * @param  pinType: pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_SWAP_EMAC_CAM_Pin(GLB_EMAC_CAM_PIN_Type pinType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_EMAC_CAM_PIN_TYPE(pinType));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PIN_SEL_EMAC_CAM, pinType);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  EXT_RST PAD SMT
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Ext_Rst_Smt(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_EXT_RST_SMT);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Key Scan Column Drive
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Kys_Drv_Col(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_KYS_DRV_VAL);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap UART gpio pins sig function
+ *
+ * @param  swapSel: UART swap set gpio pins selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Sig_Swap_Set(uint8_t swapSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((swapSel <= 0xF));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, swapSel);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap JTAG gpio pins function
+ *
+ * @param  swapSel: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_JTAG_Sig_Swap_Set(uint8_t swapSel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((swapSel <= 0xFF));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_JTAG_SWAP_SET, swapSel);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  CCI use GPIO 0 1 2 7
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CCI_Use_IO_0_1_2_7(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_P3_CCI_USE_IO_0_2_7);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  CCI use JTAG pin
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CCI_Use_Jtag_Pin(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_CCI_USE_JTAG_PIN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  swap SPI0 MOSI with MISO
+ *
+ * @param  newState: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Swap_SPI_0_MOSI_With_MISO(BL_Fun_Type newState)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_SWAP, newState);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select SPI_0 act mode
+ *
+ * @param  mod: SPI work mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_SPI_PAD_ACT_AS_TYPE(mod));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_SPI_0_MASTER_MODE, mod);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  use internal flash
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_Flash(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  use external flash
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_External_Flash(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Deswap internal flash pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Deswap_Flash_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Swap internal flash CS and IO2 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_CS_IO2_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_CS_IO2);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Swap internal flash IO3 and IO0 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_IO0_IO3_Pin(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CFG_SFLASH2_SWAP_IO0_IO3);
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Swap internal flash IO3 and IO0 pin
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Swap_Flash_Pin(void)
+{
+    /*To be removed*/
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select internal psram
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION GLB_Select_Internal_PSram(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set PDM clock
+ *
+ * @param  enable: Enable or disable PDM clock
+ * @param  div: clock divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_PDM_CLK(uint8_t enable, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
+    BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_PDM0_CLK_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PDM_CLK_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_PDM0_CLK_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_PDM_CLK_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set MTimer clock
+ *
+ * @param  enable: enable or disable MTimer clock
+ * @param  clkSel: clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_MTimer_CLK(uint8_t enable, GLB_MTIMER_CLK_Type clkSel, uint32_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_MTIMER_CLK_TYPE(clkSel));
+    CHECK_PARAM((div <= 0x1FFFF));
+
+    /* disable MTimer clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_SEL, clkSel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CPU_RTC_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_CPU_CLK_CFG);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_CPU_RTC_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_CPU_CLK_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set ADC clock
+ *
+ * @param  enable: enable or disable ADC clock
+ * @param  clkSel: ADC clock selection
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_ADC_CLK(uint8_t enable, GLB_ADC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_ADC_CLK_TYPE(clkSel));
+
+    /* disable ADC clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_GPADC_32M_DIV_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_GPADC_32M_SRC_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DAC clock
+ *
+ * @param  enable: enable frequency divider or not
+ * @param  clkSel: ADC clock selection
+ * @param  div: src divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DAC_CLK(uint8_t enable, GLB_DAC_CLK_Type clkSel, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_DAC_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    }
+
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  select DIG clock source
+ *
+ * @param  clkSel: DIG clock selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_CLK_Sel(GLB_DIG_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+    uint32_t dig512kEn;
+    uint32_t dig32kEn;
+
+    /* disable DIG512K and DIG32K clock first */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    dig512kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN);
+    dig32kEn = BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL, clkSel);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    /* repristinate DIG512K and DIG32K clock */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_EN, dig512kEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_EN, dig32kEn);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 512K clock
+ *
+ * @param  enable: enable or disable DIG 512K clock
+ * @param  compensation: enable or disable DIG 512K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_512K_CLK(uint8_t enable, uint8_t compensation, uint8_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (compensation) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_COMP);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_512K_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set DIG 32K clock
+ *
+ * @param  enable: enable or disable DIG 32K clock
+ * @param  compensation: enable or disable DIG 32K clock compensation
+ * @param  div: divider
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_DIG_32K_CLK(uint8_t enable, uint8_t compensation, uint16_t div)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (compensation) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_COMP);
+    }
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DIG_32K_DIV, div);
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_DIG_32K_EN);
+    }
+    BL_WR_REG(GLB_BASE, GLB_DIG32K_WAKEUP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set BT coex signal
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, the AP JTAG will be replaced by BT Coex Signal
+ * @param  bandWidth: BT Bandwidth
+ * @param  pti: BT Packet Traffic Information
+ * @param  channel: BT Channel
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_BT_Coex_Signal(uint8_t enable, GLB_BT_BANDWIDTH_Type bandWidth, uint8_t pti, uint8_t channel)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_BT_BANDWIDTH_TYPE(bandWidth));
+    CHECK_PARAM((pti <= 0xF));
+    CHECK_PARAM((channel <= 78));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_BW, bandWidth);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_PTI, pti);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_COEX_BT_CHANNEL, channel);
+    BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL);
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EN_GPIO_BT_COEX, 0);
+    }
+    BL_WR_REG(GLB_BASE, GLB_WIFI_BT_COEX_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select UART signal function
+ *
+ * @param  sig: UART signal
+ * @param  fun: UART function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_UART_Fun_Sel(GLB_UART_SIG_Type sig, GLB_UART_SIG_FUN_Type fun)
+{
+    uint32_t sig_pos = 0;
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_UART_SIG_TYPE(sig));
+    CHECK_PARAM(IS_GLB_UART_SIG_FUN_TYPE(fun));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_UART_SIG_SEL_0);
+    sig_pos = (sig * 4);
+    /* Clear original val */
+    tmpVal &= (~(0xf << sig_pos));
+    /* Set new value */
+    tmpVal |= (fun << sig_pos);
+    BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power off DLL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_Off_DLL(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* GLB->dll.BF.ppu_dll = 0;   */
+    /* GLB->dll.BF.pu_dll = 0;    */
+    /* GLB->dll.BF.dll_reset = 1; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  power on DLL
+ *
+ * @param  xtalType: DLL xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DLL_XTAL_TYPE(xtalType));
+
+    /* GLB->dll.BF.dll_refclk_sel = XXX; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    switch (xtalType) {
+        case GLB_DLL_XTAL_NONE:
+            return ERROR;
+        case GLB_DLL_XTAL_32M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 0);
+            break;
+        case GLB_DLL_XTAL_RC32M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_REFCLK_SEL, 1);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    /* GLB->dll.BF.dll_prechg_sel = 1;   */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_PRECHG_SEL, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    /* GLB->dll.BF.ppu_dll = 1;   */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PPU_DLL, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    BL702_Delay_US(2);
+
+    /* GLB->dll.BF.pu_dll = 1; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_DLL, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    BL702_Delay_US(2);
+
+    /* GLB->dll.BF.dll_reset = 0; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_RESET, 0);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    /* delay for settling */
+    BL702_Delay_US(5);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  enable all DLL output clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* GLB->dll.WORD = GLB->dll.WORD | 0x000000f8; include 288m and mmdiv */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  enable one of DLL output clock
+ *
+ * @param  dllClk: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    switch (dllClk) {
+        case GLB_DLL_CLK_57P6M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 1);
+            break;
+        case GLB_DLL_CLK_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 1);
+            break;
+        case GLB_DLL_CLK_144M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 1);
+            break;
+        case GLB_DLL_CLK_288M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 1);
+            break;
+        case GLB_DLL_CLK_MMDIV:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 1);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  disable all DLL output clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* GLB->dll.WORD = GLB->dll.WORD & ~0x000000f8; */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0);
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  disable one of DLL output clock
+ *
+ * @param  dllClk: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_GLB_DLL_CLK_TYPE(dllClk));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_DLL);
+    switch (dllClk) {
+        case GLB_DLL_CLK_57P6M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_57P6M_EN, 0);
+            break;
+        case GLB_DLL_CLK_96M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_96M_EN, 0);
+            break;
+        case GLB_DLL_CLK_144M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_144M_EN, 0);
+            break;
+        case GLB_DLL_CLK_288M:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_288M_EN, 0);
+            break;
+        case GLB_DLL_CLK_MMDIV:
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_DLL_CLK_MMDIV_EN, 0);
+            break;
+        default:
+            break;
+    }
+    BL_WR_REG(GLB_BASE, GLB_DLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select ir rx gpio (gpio17~gpio31)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_RX_GPIO_Sel(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    /* Select gpio between gpio17 and gpio31 */
+    if (gpio > 16 && gpio < 32) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_IR_RX_GPIO_SEL, gpio - 16);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable ir led driver
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Enable led driver */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_SET_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable ir led driver
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* Disable led driver */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_PU_LEDDRV);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable ir led driver gpio output(gpio 22 or 23)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Output_Enable(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpio == GLB_GPIO_PIN_22) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 1);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    } else if (gpio == GLB_GPIO_PIN_23) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) | 2);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable ir led driver gpio output(gpio 22 or 23)
+ *
+ * @param  gpio: IR gpio selected
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Output_Disable(GLB_GPIO_Type gpio)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpio == GLB_GPIO_PIN_22) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~1);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    } else if (gpio == GLB_GPIO_PIN_23) {
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN, BL_GET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_OUT_EN) & ~2);
+        BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set ir led driver ibias
+ *
+ * @param  ibias: Ibias value,0x0:0mA~0xf:120mA,8mA/step
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_IR_LED_Driver_Ibias(uint8_t ibias)
+{
+    uint32_t tmpVal = 0;
+
+    /* Set driver ibias */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LED_DRIVER);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LEDDRV_IBIAS, ibias & 0xF);
+    BL_WR_REG(GLB_BASE, GLB_LED_DRIVER, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO initialization
+ *
+ * @param  cfg: GPIO configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+    uint8_t gpioPin = cfg->gpioPin;
+    uint8_t realPin;
+    uint32_t *pOut;
+    uint32_t pos;
+    uint32_t tmpOut;
+    uint32_t tmpVal;
+
+    /* drive strength(drive) = 0  <=>  8.0mA  @ 3.3V */
+    /* drive strength(drive) = 1  <=>  9.6mA  @ 3.3V */
+    /* drive strength(drive) = 2  <=>  11.2mA @ 3.3V */
+    /* drive strength(drive) = 3  <=>  12.8mA @ 3.3V */
+
+    pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+    pos = gpioPin % 32;
+    tmpOut = *pOut;
+
+    /* Disable output anyway*/
+    tmpOut &= (~(1 << pos));
+    *pOut = tmpOut;
+
+    realPin = gpioPin;
+    /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            realPin += 9;
+        }
+    }
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4);
+    if (realPin % 2 == 0) {
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            /* Set input or output */
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+                tmpOut |= (1 << pos);
+            } else {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            }
+
+            /* Set pull up or down */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+            if (cfg->pullType == GPIO_PULL_UP) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            } else if (cfg->pullType == GPIO_PULL_DOWN) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+            }
+        } else {
+            /* analog mode */
+
+            /* clear ie && oe */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+            tmpOut &= ~(1 << pos);
+
+            /* clear pu && pd */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_PD);
+        }
+
+        /* set drive && smt && func */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_DRV, cfg->drive);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_SMT, cfg->smtCtrl);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
+    } else {
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            /* Set input or output */
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+                tmpOut |= (1 << pos);
+            } else {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+            }
+
+            /* Set pull up or down */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+            if (cfg->pullType == GPIO_PULL_UP) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            } else if (cfg->pullType == GPIO_PULL_DOWN) {
+                tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+            }
+        } else {
+            /* analog mode */
+
+            /* clear ie && oe */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+            tmpOut &= ~(1 << pos);
+
+            /* clear pu && pd */
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PU);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_PD);
+        }
+
+        /* set drive && smt && func */
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_DRV, cfg->drive);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_SMT, cfg->smtCtrl);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
+    }
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal);
+
+    *pOut = tmpOut;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        uint32_t aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+
+        if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+            /* not analog mode */
+
+            if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                aonPadIeSmt &= ~(1 << (gpioPin - 9));
+            } else {
+                aonPadIeSmt |= (1 << (gpioPin - 9));
+            }
+        } else {
+            /* analog mode */
+
+            /* clear aon pad ie */
+            aonPadIeSmt &= ~(1 << (gpioPin - 9));
+        }
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+            if (gpioPin % 2 == 0) {
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL, cfg->gpioFun);
+            } else {
+                tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL, cfg->gpioFun);
+            }
+            BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+            /* sf pad use GPIO23-GPIO28 pinmux&&outputEn */
+            pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+            pos = gpioPin % 32;
+            tmpOut = *pOut;
+            /* Disable output anyway*/
+            tmpOut &= (~(1 << pos));
+            *pOut = tmpOut;
+            if (cfg->gpioMode != GPIO_MODE_ANALOG) {
+                /* not analog mode */
+
+                if (cfg->gpioMode == GPIO_MODE_OUTPUT) {
+                    tmpOut |= (1 << pos);
+                }
+            }
+            *pOut = tmpOut;
+        }
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  init GPIO function in pin list
+ *
+ * @param  gpioFun: GPIO pin function
+ * @param  pinList: GPIO pin list
+ * @param  cnt: GPIO pin count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Func_Init(GLB_GPIO_FUNC_Type gpioFun, GLB_GPIO_Type *pinList, uint8_t cnt)
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_0,
+        .gpioFun = (uint8_t)gpioFun,
+        .gpioMode = GPIO_MODE_AF,
+        .pullType = GPIO_PULL_UP,
+        .drive = 1,
+        .smtCtrl = 1
+    };
+
+    if (gpioFun == GPIO_FUN_ANALOG) {
+        gpioCfg.gpioMode = GPIO_MODE_ANALOG;
+    }
+
+    for (uint8_t i = 0; i < cnt; i++) {
+        gpioCfg.gpioPin = pinList[i];
+        GLB_GPIO_Init(&gpioCfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t pinOffset;
+    uint32_t aonPadIeSmt;
+    uint8_t realPin;
+
+    realPin = gpioPin;
+    /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            realPin += 9;
+        }
+    }
+
+    pinOffset = (realPin >> 1) << 2;
+    tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
+    if (realPin % 2 == 0) {
+        /* [0] is ie */
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    } else {
+        /* [16] is ie */
+        tmpVal = BL_SET_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+    }
+    *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+        aonPadIeSmt |= (1 << (gpioPin - 9));
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set input function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_INPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t pinOffset;
+    uint32_t aonPadIeSmt;
+    uint8_t realPin;
+
+    realPin = gpioPin;
+    /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            realPin += 9;
+        }
+    }
+
+    pinOffset = (realPin >> 1) << 2;
+    tmpVal = *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset);
+    if (realPin % 2 == 0) {
+        /* [0] is ie */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_0_IE);
+    } else {
+        /* [16] is ie */
+        tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_REG_GPIO_1_IE);
+    }
+    *(uint32_t *)(GLB_BASE + GLB_GPIO_OFFSET + pinOffset) = tmpVal;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+        aonPadIeSmt &= ~(1 << (gpioPin - 9));
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function enable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
+    tmpVal = tmpVal | (1 << gpioPin);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set output function disable
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_CFGCTL34);
+    tmpVal = tmpVal & ~(1 << gpioPin);
+    BL_WR_REG(GLB_BASE, GLB_GPIO_CFGCTL34, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO set High-Z
+ *
+ * @param  gpioPin: GPIO pin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+    uint32_t *pOut;
+    uint32_t pos;
+    uint32_t tmpOut;
+    uint32_t tmpVal;
+    uint32_t aonPadIeSmt;
+    uint8_t realPin;
+
+    /* always on pads IE control (in HBN) */
+    if (gpioPin >= 9 && gpioPin <= 13) {
+        tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+        aonPadIeSmt = BL_GET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT);
+        aonPadIeSmt &= ~(1 << (gpioPin - 9));
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aonPadIeSmt);
+        BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    }
+
+    realPin = gpioPin;
+    /* sf pad use exclusive ie/pd/pu/drive/smtctrl */
+    if (gpioPin >= 23 && gpioPin <= 28) {
+        if ((BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) & (1 << (gpioPin - 23))) > 0) {
+            realPin += 9;
+        }
+    }
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4);
+
+    /* pu=0, pd=0, ie=0 */
+    if (realPin % 2 == 0) {
+        tmpVal = (tmpVal & 0xffffff00);
+    } else {
+        tmpVal = (tmpVal & 0xff00ffff);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + realPin / 2 * 4, tmpVal);
+
+    pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET + ((gpioPin >> 5) << 2));
+    pos = gpioPin % 32;
+    tmpOut = *pOut;
+
+    /* Disable output anyway*/
+    tmpOut &= (~(1 << pos));
+    *pOut = tmpOut;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    /* func_sel=swgpio */
+    if (gpioPin % 2 == 0) {
+        tmpVal = (tmpVal & 0xffff00ff);
+        tmpVal |= 0x0B00;
+    } else {
+        tmpVal = (tmpVal & 0x00ffffff);
+        tmpVal |= (0x0B00 << 16);
+    }
+
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4, tmpVal);
+
+    /* Disable output anyway*/
+    *pOut = tmpOut;
+
+    return SUCCESS;
+}
+
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Pad_HZ(void)
+{
+    uint32_t tmpVal;
+    uint32_t offset;
+
+    if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x00) {
+        return ERROR;
+    }
+
+    for (offset = 23; offset <= 28; offset++) {
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
+        /* pu=0, pd=0, ie=0 */
+        if (offset % 2 == 0) {
+            tmpVal = (tmpVal & 0xffffff00);
+        } else {
+            tmpVal = (tmpVal & 0xff00ffff);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
+
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
+        /* func_sel=swgpio */
+        if (offset % 2 == 0) {
+            tmpVal = (tmpVal & 0xffff00ff);
+            tmpVal |= 0x0B00;
+        } else {
+            tmpVal = (tmpVal & 0x00ffffff);
+            tmpVal |= (0x0B00 << 16);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
+    }
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
+    tmpVal &= 0xE07FFFFF;
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);
+
+    return SUCCESS;
+}
+
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Psram_Pad_HZ(void)
+{
+    uint32_t tmpVal;
+    uint32_t offset;
+
+    if (BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO) != 0x3F) {
+        return ERROR;
+    }
+
+    for (offset = 32; offset <= 37; offset++) {
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4);
+        /* pu=0, pd=0, ie=0 */
+        if (offset % 2 == 0) {
+            tmpVal = (tmpVal & 0xffffff00);
+        } else {
+            tmpVal = (tmpVal & 0xff00ffff);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + offset / 2 * 4, tmpVal);
+
+        tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4);
+        /* func_sel=swgpio */
+        if ((offset - 9) % 2 == 0) {
+            tmpVal = (tmpVal & 0xffff00ff);
+            tmpVal |= 0x0B00;
+        } else {
+            tmpVal = (tmpVal & 0x00ffffff);
+            tmpVal |= (0x0B00 << 16);
+        }
+        BL_WR_WORD(GLB_BASE + GLB_GPIO_OFFSET + (offset - 9) / 2 * 4, tmpVal);
+    }
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET);
+    tmpVal &= 0xE07FFFFF;
+    BL_WR_WORD(GLB_BASE + GLB_GPIO_OUTPUT_EN_OFFSET, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GPIO function
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO function
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint8_t ATTR_TCM_SECTION GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_WORD(GLB_BASE + GLB_GPIO_OFFSET + gpioPin / 2 * 4);
+
+    if (gpioPin % 2 == 0) {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_0_FUNC_SEL);
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_GPIO_1_FUNC_SEL);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Write GPIO
+ *
+ * @param  gpioPin: GPIO type
+ * @param  val: GPIO value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Write(GLB_GPIO_Type gpioPin, uint32_t val)
+{
+    uint32_t *pOut = (uint32_t *)(GLB_BASE + GLB_GPIO_OUTPUT_OFFSET + ((gpioPin >> 5) << 2));
+    uint32_t pos = gpioPin % 32;
+    uint32_t tmpOut;
+
+    tmpOut = *pOut;
+    if (val > 0) {
+        tmpOut |= (1 << pos);
+    } else {
+        tmpOut &= (~(1 << pos));
+    }
+    *pOut = tmpOut;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read GPIO
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return GPIO value
+ *
+*******************************************************************************/
+uint32_t GLB_GPIO_Read(GLB_GPIO_Type gpioPin)
+{
+    uint32_t *p = (uint32_t *)(GLB_BASE + GLB_GPIO_INPUT_OFFSET + ((gpioPin >> 5) << 2));
+    uint32_t pos = gpioPin % 32;
+
+    if ((*p) & (1 << pos)) {
+        return 1;
+    } else {
+        return 0;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intMask: GPIO interrupt MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntMask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MASK1);
+        if (intMask == MASK) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MASK1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intClear: GPIO interrupt clear or unclear
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_IntClear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_CLR1);
+        if (intClear == SET) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_CLR1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GLB GPIO interrrupt status
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_Get_GPIO_IntStatus(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_STAT1);
+    }
+
+    return (tmpVal & (1 << gpioPin)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mode
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intCtlMod: GPIO interrupt control mode
+ * @param  intTrgMod: GPIO interrupt trigger mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_GPIO_IntMod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod)
+{
+    uint32_t tmpVal;
+    uint32_t tmpGpioPin;
+
+    CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
+    CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 ~ GPIO9 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
+        tmpGpioPin = gpioPin;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_20) {
+        /* GPIO10 ~ GPIO19 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_30) {
+        /* GPIO20 ~ GPIO29 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3, tmpVal);
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get GPIO interrupt control mode
+ *
+ * @param  gpioPin: GPIO pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_IntCtlMod(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t bitVal;
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 - GPIO9 */
+        bitVal = gpioPin - 0;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET1);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
+        /* GPIO10 - GPIO19 */
+        bitVal = gpioPin - 10;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET2);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) {
+        /* GPIO20 - GPIO29 */
+        bitVal = gpioPin - 20;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET3);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        bitVal = gpioPin - 30;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT_MODE_SET4);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask 2
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intMask: GPIO interrupt MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Int2Mask(GLB_GPIO_Type gpioPin, BL_Mask_Type intMask)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MASK1);
+        if (intMask == MASK) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MASK1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mask 2
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intClear: GPIO interrupt clear or unclear
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_Int2Clear(GLB_GPIO_Type gpioPin, BL_Sts_Type intClear)
+{
+    uint32_t tmpVal;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_CLR1);
+        if (intClear == SET) {
+            tmpVal = tmpVal | (1 << gpioPin);
+        } else {
+            tmpVal = tmpVal & ~(1 << gpioPin);
+        }
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_CLR1, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get GLB GPIO interrrupt status 2
+ *
+ * @param  gpioPin: GPIO type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type GLB_Get_GPIO_Int2Status(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal = 0;
+
+    if (gpioPin < 32) {
+        /* GPIO0 ~ GPIO31 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_STAT1);
+    }
+
+    return (tmpVal & (1 << gpioPin)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set GLB GPIO interrupt mode 2
+ *
+ * @param  gpioPin: GPIO type
+ * @param  intCtlMod: GPIO interrupt control mode
+ * @param  intTrgMod: GPIO interrupt trigger mode
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_GPIO_Int2Mod(GLB_GPIO_Type gpioPin, GLB_GPIO_INT_CONTROL_Type intCtlMod, GLB_GPIO_INT_TRIG_Type intTrgMod)
+{
+    uint32_t tmpVal;
+    uint32_t tmpGpioPin;
+
+    CHECK_PARAM(IS_GLB_GPIO_INT_CONTROL_TYPE(intCtlMod));
+    CHECK_PARAM(IS_GLB_GPIO_INT_TRIG_TYPE(intTrgMod));
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 ~ GPIO9 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1);
+        tmpGpioPin = gpioPin;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_20) {
+        /* GPIO10 ~ GPIO19 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_10;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2, tmpVal);
+    } else if (gpioPin < GLB_GPIO_PIN_30) {
+        /* GPIO20 ~ GPIO29 */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_20;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3, tmpVal);
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
+        tmpGpioPin = gpioPin - GLB_GPIO_PIN_30;
+        tmpVal = (tmpVal & ~(0x7 << (3 * tmpGpioPin))) | (((intCtlMod << 2) | intTrgMod) << (3 * tmpGpioPin));
+        BL_WR_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get GPIO interrupt control mode 2
+ *
+ * @param  gpioPin: GPIO pin type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+GLB_GPIO_INT_CONTROL_Type GLB_Get_GPIO_Int2CtlMod(GLB_GPIO_Type gpioPin)
+{
+    uint32_t tmpVal;
+    uint32_t bitVal;
+
+    if (gpioPin < GLB_GPIO_PIN_10) {
+        /* GPIO0 - GPIO9 */
+        bitVal = gpioPin - 0;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET1);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_9) && (gpioPin < GLB_GPIO_PIN_20)) {
+        /* GPIO10 - GPIO19 */
+        bitVal = gpioPin - 10;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET2);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else if ((gpioPin > GLB_GPIO_PIN_19) && (gpioPin < GLB_GPIO_PIN_30)) {
+        /* GPIO20 - GPIO29 */
+        bitVal = gpioPin - 20;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET3);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    } else {
+        /* GPIO30 ~ GPIO31 not recommend */
+        bitVal = gpioPin - 30;
+        tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_INT2_MODE_SET4);
+        tmpVal = (tmpVal & (0x7 << (bitVal * 3))) >> (bitVal * 3);
+        return (tmpVal >> 2) ? GLB_GPIO_INT_CONTROL_ASYNC : GLB_GPIO_INT_CONTROL_SYNC;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO INT0 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_IRQHandler_Install(void)
+{
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(GPIO_INT0_IRQn, GPIO_INT0_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler callback install
+ *
+ * @param  gpioPin: GPIO pin type
+ * @param  cbFun: callback function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_Callback_Install(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
+{
+    if (gpioPin < 32) {
+        glbGpioInt0CbfArra[gpioPin] = cbFun;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler callback install2
+ *
+ * @param  gpioPin: GPIO pin type
+ * @param  cbFun: callback function
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_GPIO_INT0_Callback_Install2(GLB_GPIO_Type gpioPin, intCallback_Type *cbFun)
+{
+    if (gpioPin < 32) {
+        glbGpioInt0CbfArra2[gpioPin] = cbFun;
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  GPIO interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void GPIO_INT0_IRQHandler(void)
+{
+    GLB_GPIO_Type gpioPin;
+    uint32_t timeOut = 0;
+
+    for (gpioPin = GLB_GPIO_PIN_0; gpioPin <= GLB_GPIO_PIN_31; gpioPin++) {
+        if (SET == GLB_Get_GPIO_IntStatus(gpioPin)) {
+            GLB_GPIO_IntClear(gpioPin, SET);
+
+            /* timeout check */
+            timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+            do {
+                timeOut--;
+            } while ((SET == GLB_Get_GPIO_IntStatus(gpioPin)) && timeOut);
+            if (!timeOut) {
+                //MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+            }
+
+            /* if timeOut==0, GPIO interrupt status not cleared */
+            GLB_GPIO_IntClear(gpioPin, RESET);
+
+            if (glbGpioInt0CbfArra[gpioPin] != NULL) {
+                /* Call the callback function */
+                glbGpioInt0CbfArra[gpioPin]();
+            }
+        }
+        if (SET == GLB_Get_GPIO_Int2Status(gpioPin)) {
+            GLB_GPIO_Int2Clear(gpioPin, SET);
+
+            /* timeout check */
+            timeOut = GLB_GPIO_INT0_CLEAR_TIMEOUT;
+            do {
+                timeOut--;
+            } while ((SET == GLB_Get_GPIO_Int2Status(gpioPin)) && timeOut);
+            if (!timeOut) {
+                //MSG("WARNING: Clear GPIO interrupt status fail.\r\n");
+            }
+
+            /* if timeOut==0, GPIO interrupt status not cleared */
+            GLB_GPIO_Int2Clear(gpioPin, RESET);
+
+            if (glbGpioInt0CbfArra2[gpioPin] != NULL) {
+                /* Call the callback function */
+                glbGpioInt0CbfArra2[gpioPin]();
+            }
+        }
+    }
+}
+#endif
+
+/*@} end of group GLB_Public_Functions */
+
+/*@} end of group GLB */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_hbn.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_hbn.c
new file mode 100755
index 0000000000..ee7fc70899
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_hbn.c
@@ -0,0 +1,2031 @@
+/**
+  ******************************************************************************
+  * @file    bl702_hbn.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_hbn.h"
+#include "bl702_glb.h"
+#include "bflb_xip_sflash.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  HBN
+ *  @{
+ */
+
+/** @defgroup  HBN_Private_Macros
+ *  @{
+ */
+#define HBN_CLK_SET_DUMMY_WAIT \
+    {                          \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+        __NOP();               \
+    }
+
+/*@} end of group HBN_Private_Macros */
+
+/** @defgroup  HBN_Private_Types
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Types */
+
+/** @defgroup  HBN_Private_Variables
+ *  @{
+ */
+static intCallback_Type *hbnInt0CbfArra[HBN_OUT0_MAX] = { NULL, NULL, NULL, NULL, NULL, NULL };
+static intCallback_Type *hbnInt1CbfArra[HBN_OUT1_MAX] = { NULL, NULL, NULL, NULL };
+
+/*@} end of group HBN_Private_Variables */
+
+/** @defgroup  HBN_Global_Variables
+ *  @{
+ */
+
+/*@} end of group HBN_Global_Variables */
+
+/** @defgroup  HBN_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Fun_Declaration */
+
+/** @defgroup  HBN_Private_Functions
+ *  @{
+ */
+
+/*@} end of group HBN_Private_Functions */
+
+/** @defgroup  HBN_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enter HBN
+ *
+ * @param  cfg: HBN APP Config
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
+{
+    uint32_t valLow = 0, valHigh = 0;
+    uint64_t val;
+
+    /* work clock select */
+    if (cfg->useXtal32k) {
+        HBN_32K_Sel(HBN_32K_XTAL);
+    } else {
+        HBN_32K_Sel(HBN_32K_RC);
+        HBN_Power_Off_Xtal_32K();
+    }
+
+    /* turn off RC32K during HBN */
+    if ((cfg->hbnLevel) >= HBN_LEVEL_2) {
+        HBN_Power_Off_RC32K();
+    } else {
+        HBN_Power_On_RC32K();
+    }
+
+    /* clear aon pad interrupt before config them */
+    HBN_Clear_IRQ(HBN_INT_GPIO9);
+    HBN_Clear_IRQ(HBN_INT_GPIO10);
+    HBN_Clear_IRQ(HBN_INT_GPIO11);
+    HBN_Clear_IRQ(HBN_INT_GPIO12);
+    HBN_Clear_IRQ(HBN_INT_GPIO13);
+
+    /* always disable HBN pin pull up/down to reduce PDS/HBN current, 0x4000F014[16]=0 */
+    HBN_Hw_Pu_Pd_Cfg(DISABLE);
+
+    HBN_Pin_WakeUp_Mask(~(cfg->gpioWakeupSrc));
+
+    if (cfg->gpioWakeupSrc != 0) {
+        HBN_Aon_Pad_IeSmt_Cfg(cfg->gpioWakeupSrc);
+        HBN_GPIO_INT_Enable(cfg->gpioTrigType);
+    } else {
+        HBN_Aon_Pad_IeSmt_Cfg(0);
+    }
+
+    /* HBN RTC config and enable */
+    if (cfg->sleepTime != 0) {
+        // set rtc enable flag
+        BL_WR_WORD(0x40010FFC, 0x1);
+
+        HBN_Clear_RTC_Counter();
+        HBN_Get_RTC_Timer_Val(&valLow, &valHigh);
+        val = valLow + ((uint64_t)valHigh << 32);
+        val += cfg->sleepTime;
+        HBN_Set_RTC_Timer(HBN_RTC_INT_DELAY_0T, val & 0xffffffff, val >> 32, HBN_RTC_COMP_BIT0_39);
+        HBN_Enable_RTC_Counter();
+    }
+
+    HBN_Power_Down_Flash(cfg->flashCfg);
+
+    switch (cfg->flashPinCfg) {
+        case 0:
+            HBN_Set_Pad_23_28_Pullup();
+            break;
+
+        case 1:
+            /* need do nothing */
+            break;
+
+        case 2:
+            /* need do nothing */
+            break;
+
+        case 3:
+            /* can do nothing */
+            break;
+
+        default:
+            break;
+    }
+
+    GLB_Set_System_CLK(GLB_DLL_XTAL_NONE, GLB_SYS_CLK_RC32M);
+
+    /* power off xtal */
+    AON_Power_Off_XTAL();
+
+    HBN_Enable_Ext(cfg->gpioWakeupSrc, cfg->ldoLevel, cfg->hbnLevel);
+}
+
+/****************************************************************************/ /**
+ * @brief  power down and switch clock
+ *
+ * @param  flashCfg: None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg)
+{
+    spi_flash_cfg_type bhFlashCfg;
+
+    if (flashCfg == NULL) {
+        /* fix this some time */
+        /* SFlash_Cache_Flush(); */
+        bflb_xip_sflash_read_via_cache_need_lock(BL702_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg),
+                                                 sizeof(spi_flash_cfg_type), 0, 0);
+        /* fix this some time */
+        /* SFlash_Cache_Flush(); */
+
+        bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+        bflb_sflash_reset_continue_read(&bhFlashCfg);
+    } else {
+        bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+        bflb_sflash_reset_continue_read(flashCfg);
+    }
+
+    bflb_sflash_powerdown();
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN mode
+ *
+ * @param  aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to
+ *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param  ldoLevel: LDO volatge level
+ * @param  hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable_Ext(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+    CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+    /* Setting from guide */
+    /* RAM Retion, no longer use */
+    /* BL_WR_REG(HBN_BASE,HBN_SRAM,0x24); */
+
+    /* AON GPIO IE */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    /* HBN mode LDO level */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Select RC32M */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbnLevel) {
+        case HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_2:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_3:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        BL702_Delay_MS(1000);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Reset HBN mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_Reset(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Reset HBN mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_SW_RST);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  reset HBN by software
+ *
+ * @param  npXtalType: NP clock type
+ * @param  bclkDiv: NP clock div
+ * @param  apXtalType: AP clock type
+ * @param  fclkDiv: AP clock div
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_App_Reset(uint8_t npXtalType, uint8_t bclkDiv, uint8_t apXtalType, uint8_t fclkDiv)
+{
+    uint32_t tmp[12];
+
+    tmp[0] = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmp[1] = BL_RD_REG(HBN_BASE, HBN_TIME_L);
+    tmp[2] = BL_RD_REG(HBN_BASE, HBN_TIME_H);
+    tmp[3] = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmp[4] = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmp[5] = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmp[6] = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmp[7] = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmp[8] = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmp[9] = BL_RD_REG(HBN_BASE, HBN_RSV0);
+    tmp[10] = BL_RD_REG(HBN_BASE, HBN_RSV1);
+    tmp[11] = BL_RD_REG(HBN_BASE, HBN_RSV2);
+    /* DO HBN reset */
+    HBN_Reset();
+    /* HBN need 3 32k cyclce to recovery */
+    BL702_Delay_US(100);
+    /* Recover HBN value */
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, tmp[1]);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, tmp[2]);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmp[0]);
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmp[3]);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmp[4]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmp[5]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmp[6]);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmp[7]);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmp[8]);
+    BL_WR_REG(HBN_BASE, HBN_RSV0, tmp[9]);
+    BL_WR_REG(HBN_BASE, HBN_RSV1, tmp[10]);
+    BL_WR_REG(HBN_BASE, HBN_RSV2, tmp[11]);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Disable HBN mode */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Enable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Disable HBN PIR
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PIR_EN);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Config HBN PIR interrupt
+ *
+ * @param  pirIntCfg: HBN PIR interrupt configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_INT_Config(HBN_PIR_INT_CFG_Type *pirIntCfg)
+{
+    uint32_t tmpVal;
+    uint32_t bit4 = 0;
+    uint32_t bit5 = 0;
+    uint32_t bitVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+
+    /* low trigger interrupt */
+    if (pirIntCfg->lowIntEn == ENABLE) {
+        bit5 = 0;
+    } else {
+        bit5 = 1;
+    }
+
+    /* high trigger interrupt */
+    if (pirIntCfg->highIntEn == ENABLE) {
+        bit4 = 0;
+    } else {
+        bit4 = 1;
+    }
+
+    bitVal = bit4 | (bit5 << 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_DIS, bitVal);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR low pass filter
+ *
+ * @param  lpf: HBN PIR low pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_LPF_Sel(HBN_PIR_LPF_Type lpf)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_LPF_TYPE(lpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_LPF_SEL, lpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select HBN PIR high pass filter
+ *
+ * @param  hpf: HBN PIR high pass filter selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_PIR_HPF_Sel(HBN_PIR_HPF_Type hpf)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_PIR_HPF_TYPE(hpf));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_CFG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_HPF_SEL, hpf);
+    BL_WR_REG(HBN_BASE, HBN_PIR_CFG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR threshold value
+ *
+ * @param  threshold: HBN PIR threshold value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Threshold(uint16_t threshold)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((threshold <= 0x3FFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH, threshold);
+    BL_WR_REG(HBN_BASE, HBN_PIR_VTH, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR threshold value
+ *
+ * @param  None
+ *
+ * @return HBN PIR threshold value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Threshold(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_VTH);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_VTH);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN PIR interval value
+ *
+ * @param  interval: HBN PIR interval value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_PIR_Interval(uint16_t interval)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM((interval <= 0xFFF));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL, interval);
+    BL_WR_REG(HBN_BASE, HBN_PIR_INTERVAL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN PIR interval value
+ *
+ * @param  None
+ *
+ * @return HBN PIR interval value
+ *
+*******************************************************************************/
+uint16_t HBN_Get_PIR_Interval(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_PIR_INTERVAL);
+
+    return BL_GET_REG_BITS_VAL(tmpVal, HBN_PIR_INTERVAL);
+}
+
+/****************************************************************************/ /**
+ * @brief  get HBN bor out state
+ *
+ * @param  None
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_BOR_OUT_State(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_MISC), HBN_R_BOR_OUT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN bor config
+ *
+ * @param  enable: ENABLE or DISABLE, if enable, Power up Brown Out Reset
+ * @param  threshold: bor threshold
+ * @param  mode: bor work mode with por
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOR_Config(uint8_t enable, HBN_BOR_THRES_Type threshold, HBN_BOR_MODE_Type mode)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_BOR_THRES_TYPE(threshold));
+    CHECK_PARAM(IS_HBN_BOR_MODE_TYPE(mode));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 1);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PU_BOR, 0);
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, threshold);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_SEL, mode);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11aon voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Aon_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11rt voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Rt_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11soc voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_Soc_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11 all voltage out
+ *
+ * @param  ldoLevel: LDO volatge level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11_All_Vout(HBN_LDO_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_AON_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11_RT_VOUT_SEL, ldoLevel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_SW_LDO11SOC_VOUT_SEL_AON, ldoLevel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set ldo11rt drive strength
+ *
+ * @param  strength: ldo11rt drive strength
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Ldo11rt_Drive_Strength(HBN_LDO11RT_DRIVE_STRENGTH_Type strength)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO11RT_DRIVE_STRENGTH_TYPE(strength));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_LDO11_RT_ILOAD_SEL, strength);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN select 32K
+ *
+ * @param  clkType: HBN 32k clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_32K_Sel(HBN_32K_CLK_Type clkType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_32K_CLK_TYPE(clkType));
+
+    HBN_Trim_RC32K();
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL, clkType);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select uart clock source
+ *
+ * @param  clkSel: uart clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_UART_CLK_Sel(HBN_UART_CLK_Type clkSel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_UART_CLK_TYPE(clkSel));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_UART_CLK_SEL, clkSel);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select xclk clock source
+ *
+ * @param  xClk: xclk clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_XCLK_CLK_Sel(HBN_XCLK_CLK_Type xClk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_XCLK_CLK_TYPE(xClk));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    switch (xClk) {
+        case HBN_XCLK_CLK_RC32M:
+            tmpVal2 &= (~(1 << 0));
+            break;
+
+        case HBN_XCLK_CLK_XTAL:
+            tmpVal2 |= (1 << 0);
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Select root clk source
+ *
+ * @param  rootClk: root clock type selection
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ROOT_CLK_TYPE(rootClk));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL);
+
+    switch (rootClk) {
+        case HBN_ROOT_CLK_RC32M:
+            tmpVal2 = 0x0;
+            break;
+
+        case HBN_ROOT_CLK_XTAL:
+            tmpVal2 = 0x1;
+            break;
+
+        case HBN_ROOT_CLK_DLL:
+            tmpVal2 |= (1 << 1);
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    HBN_CLK_SET_DUMMY_WAIT;
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM sleep mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_HRAM_slp(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set HBN_RAM retension mode
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_HRAM_Ret(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_SRAM);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RETRAM_SLP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RETRAM_RET);
+    BL_WR_REG(HBN_BASE, HBN_SRAM, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    /* Delay >1s */
+    BL702_Delay_US(1100);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off XTAL 32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_Xtal_32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_XTAL32K);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_XTAL32K_BUF);
+    BL_WR_REG(HBN_BASE, HBN_XTAL32K, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power on RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_On_RC32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    /* Delay >800us */
+    BL702_Delay_US(880);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Power off RC3K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Power_Off_RC32K(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_RC32K);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32K
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION HBN_Trim_RC32K(void)
+{
+    Efuse_Ana_RC32K_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32K_Trim(&trim);
+
+    if (trim.trimRc32kExtCodeEn) {
+        if (trim.trimRc32kCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32kCodeFrExt, 10)) {
+            tmpVal = BL_RD_REG(HBN_BASE, HBN_RC32K_CTRL0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RC32K_CODE_FR_EXT, trim.trimRc32kCodeFrExt);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RC32K_EXT_CODE_EN);
+            BL_WR_REG(HBN_BASE, HBN_RC32K_CTRL0, tmpVal);
+            BL702_Delay_US(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get HBN status flag
+ *
+ * @param  None
+ *
+ * @return HBN status flag value
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Status_Flag(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV0);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN status flag
+ *
+ * @param  flag: Status Flag
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Status_Flag(uint32_t flag)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV0, flag);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get HBN wakeup address
+ *
+ * @param  None
+ *
+ * @return HBN wakeup address
+ *
+*******************************************************************************/
+uint32_t HBN_Get_Wakeup_Addr(void)
+{
+    return BL_RD_REG(HBN_BASE, HBN_RSV1);
+}
+
+/****************************************************************************/ /**
+ * @brief  Set HBN wakeup address
+ *
+ * @param  addr: HBN wakeup address
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_Wakeup_Addr(uint32_t addr)
+{
+    BL_WR_REG(HBN_BASE, HBN_RSV1, addr);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffffe);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer counter
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_RTC_Counter(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set RTC control bit0 */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal | 0x01);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN set RTC timer configuration
+ *
+ * @param  delay: RTC interrupt delay 32 clocks
+ * @param  compValLow: RTC interrupt commpare value low 32 bits
+ * @param  compValHigh: RTC interrupt commpare value high 32 bits
+ * @param  compMode: RTC interrupt commpare
+ *                   mode:HBN_RTC_COMP_BIT0_39,HBN_RTC_COMP_BIT0_23,HBN_RTC_COMP_BIT13_39
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_RTC_Timer(HBN_RTC_INT_Delay_Type delay, uint32_t compValLow, uint32_t compValHigh, uint8_t compMode)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_RTC_INT_DELAY_TYPE(delay));
+
+    BL_WR_REG(HBN_BASE, HBN_TIME_L, compValLow);
+    BL_WR_REG(HBN_BASE, HBN_TIME_H, compValHigh & 0xff);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Set interrupt delay option */
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_RTC_DLY_OPTION, delay);
+    /* Set RTC compare mode */
+    tmpVal |= (compMode << 1);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get RTC async timer count value
+ *
+ * @param  valLow: RTC count value pointer for low 32 bits
+ * @param  valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+static BL_Err_Type HBN_Get_RTC_Timer_Async_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+    uint32_t tmpVal;
+
+    /* Tigger RTC val read */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_RTC_TIME_LATCH);
+    BL_WR_REG(HBN_BASE, HBN_RTC_TIME_H, tmpVal);
+
+    /* Read RTC val */
+    *valLow = BL_RD_REG(HBN_BASE, HBN_RTC_TIME_L);
+    *valHigh = (BL_RD_REG(HBN_BASE, HBN_RTC_TIME_H) & 0xff);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get RTC timer count value
+ *
+ * @param  valLow: RTC count value pointer for low 32 bits
+ * @param  valHigh: RTC count value pointer for high 8 bits
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Get_RTC_Timer_Val(uint32_t *valLow, uint32_t *valHigh)
+{
+    uint32_t tmpValLow, tmpValHigh, tmpValLow1, tmpValHigh1;
+    uint64_t val, val1;
+
+    do {
+        HBN_Get_RTC_Timer_Async_Val(&tmpValLow, &tmpValHigh);
+        val = ((uint64_t)tmpValHigh << 32) | ((uint64_t)tmpValLow);
+        HBN_Get_RTC_Timer_Async_Val(&tmpValLow1, &tmpValHigh1);
+        val1 = ((uint64_t)tmpValHigh1 << 32) | ((uint64_t)tmpValLow1);
+    } while (val1 < val);
+
+    *valLow = tmpValLow1;
+    *valHigh = tmpValHigh1;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear RTC timer interrupt,this function must be called to clear delayed rtc IRQ
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_RTC_INT(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    /* Clear RTC commpare:bit1-3 for clearing Delayed RTC IRQ */
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal & 0xfffffff1);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable GPIO interrupt
+ *
+ * @param  gpioIntTrigType: HBN GPIO interrupt trigger type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Enable(HBN_GPIO_INT_Trigger_Type gpioIntTrigType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_GPIO_INT_TRIGGER_TYPE(gpioIntTrigType));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MODE, gpioIntTrigType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable GPIO interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_GPIO_INT_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, 0);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_INT_State(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    /* Check the parameters */
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_STAT);
+
+    if (tmpVal & (1 << irqType)) {
+        return SET;
+    } else {
+        return RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN get pin wakeup mode value
+ *
+ * @param  None
+ *
+ * @return HBN pin wakeup mode value
+ *
+*******************************************************************************/
+uint8_t HBN_Get_Pin_Wakeup_Mode(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(HBN_BASE, HBN_IRQ_MODE), HBN_PIN_WAKEUP_MODE);
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN clear interrupt status
+ *
+ * @param  irqType: HBN interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_IRQ(HBN_INT_Type irqType)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_INT_TYPE(irqType));
+
+    /* set clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal |= (1 << irqType);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    /* unset clear bit */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_CLR);
+    tmpVal &= (~(1 << irqType));
+    BL_WR_REG(HBN_BASE, HBN_IRQ_CLR, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN hardware pullup or pulldown configuration
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Hw_Pu_Pd_Cfg(uint8_t enable)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN Config AON pad input and SMT
+ *
+ * @param  padCfg: AON pad config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Aon_Pad_IeSmt_Cfg(uint8_t padCfg)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, padCfg);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN wakeup pin mask configuration
+ *
+ * @param  maskVal: mask value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Pin_WakeUp_Mask(uint8_t maskVal)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_MASK, maskVal);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP0 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+    tmpVal2 = tmpVal2 | (1 << edge);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP0 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp0_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN);
+    tmpVal2 = tmpVal2 & (~(1 << edge));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP0_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable ACOMP1 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+    tmpVal2 = tmpVal2 | (1 << edge);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable ACOMP1 interrupt
+ *
+ * @param  edge: HBN acomp interrupt edge type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_AComp1_IRQ(HBN_ACOMP_INT_EDGE_Type edge)
+{
+    uint32_t tmpVal;
+    uint32_t tmpVal2;
+
+    CHECK_PARAM(IS_HBN_ACOMP_INT_EDGE_TYPE(edge));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal2 = BL_GET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN);
+    tmpVal2 = tmpVal2 & (~(1 << edge));
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_IRQ_ACOMP1_EN, tmpVal2);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN enable BOR interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Enable_BOR_IRQ(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN disable BOR interrupt
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Disable_BOR_IRQ(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_IRQ_BOR_EN);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get HBN reset event status
+ *
+ * @param  event: HBN reset event type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type HBN_Get_Reset_Event(HBN_RST_EVENT_Type event)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, HBN_RESET_EVENT);
+
+    return (tmpVal & (1 << event)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  clear HBN reset event status
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Clear_Reset_Event(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_CLEAR_RESET_EVENT);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out0 install interrupt callback
+ *
+ * @param  intType: HBN out0 interrupt type
+ * @param  cbFun: HBN out0 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out0_Callback_Install(HBN_OUT0_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT0_INT_TYPE(intType));
+
+    hbnInt0CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out1 install interrupt callback
+ *
+ * @param  intType: HBN out1 interrupt type
+ * @param  cbFun: HBN out1 interrupt callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out1_Callback_Install(HBN_OUT1_INT_Type intType, intCallback_Type *cbFun)
+{
+    /* Check the parameters */
+    CHECK_PARAM(IS_HBN_OUT1_INT_TYPE(intType));
+
+    hbnInt1CbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN GPIO debug pull config
+ *
+ * @param  pupdEn: Enable or disable GPIO pull down and pull up
+ * @param  dlyEn: Enable or disable GPIO wakeup delay function
+ * @param  dlySec: GPIO wakeup delay sec 1 to 7
+ * @param  gpioIrq: HBN GPIO num
+ * @param  gpioMask: HBN GPIO MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(((dlySec >= 1) && (dlySec <= 7)));
+    CHECK_PARAM((gpioIrq >= HBN_INT_GPIO9) && (gpioIrq <= HBN_INT_GPIO13));
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_EN, dlyEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_PIN_WAKEUP_SEL, dlySec);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_EN_HW_PU_PD, pupdEn);
+
+    if (gpioMask != UNMASK) {
+        tmpVal = tmpVal | (1 << (gpioIrq + 8));
+    } else {
+        tmpVal = tmpVal & ~(1 << (gpioIrq + 8));
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 pull none
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullnone(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 pull up
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pullup(void)
+{
+    uint32_t tmpVal = 0;
+
+    /********************************************/
+    /* GPIO28 is bootpin, so leave it pull none */
+    /********************************************/
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x00);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 pull down
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_Pulldown(void)
+{
+    uint32_t tmpVal = 0;
+
+    /********************************************/
+    /* GPIO28 is bootpin, so leave it pull none */
+    /********************************************/
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x00);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set pad 23-28 active ie
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION HBN_Set_Pad_23_28_ActiveIE(void)
+{
+    uint32_t tmpVal = 0;
+
+    /********************************************/
+    /* GPIO28 is bootpin, so leave it pull none */
+    /********************************************/
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLDOWN_AON, 0x1F);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_FLASH_PULLUP_AON, 0x1F);
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Set BOR config
+ *
+ * @param  cfg: Enable or disable
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Set_BOR_Cfg(HBN_BOR_CFG_Type *cfg)
+{
+    uint32_t tmpVal = 0;
+
+    if (cfg->enableBorInt) {
+        HBN_Enable_BOR_IRQ();
+    } else {
+        HBN_Disable_BOR_IRQ();
+    }
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_MISC);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_BOR_VTH, cfg->borThreshold);
+
+    if (cfg->enablePorInBor) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_BOR_SEL);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_BOR_SEL);
+    }
+
+    if (cfg->enableBor) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PU_BOR);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PU_BOR);
+    }
+
+    BL_WR_REG(HBN_BASE, HBN_MISC, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT0 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void HBN_OUT0_IRQHandler(void)
+{
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO9)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO9);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO9] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO9]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO10)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO10);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO10] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO10]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO11)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO11);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO11] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO11]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO12)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO12);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO12] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO12]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_GPIO13)) {
+        HBN_Clear_IRQ(HBN_INT_GPIO13);
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_GPIO13] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_GPIO13]();
+        }
+    }
+
+    if (SET == HBN_Get_INT_State(HBN_INT_RTC)) {
+        HBN_Clear_IRQ(HBN_INT_RTC);
+        HBN_Clear_RTC_INT();
+
+        if (hbnInt0CbfArra[HBN_OUT0_INT_RTC] != NULL) {
+            hbnInt0CbfArra[HBN_OUT0_INT_RTC]();
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN OUT1 interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void HBN_OUT1_IRQHandler(void)
+{
+    /* PIR */
+    if (SET == HBN_Get_INT_State(HBN_INT_PIR)) {
+        HBN_Clear_IRQ(HBN_INT_PIR);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_PIR] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_PIR]();
+        }
+    }
+
+    /* BOR */
+    if (SET == HBN_Get_INT_State(HBN_INT_BOR)) {
+        HBN_Clear_IRQ(HBN_INT_BOR);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_BOR] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_BOR]();
+        }
+    }
+
+    /* ACOMP0 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP0)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP0);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP0]();
+        }
+    }
+
+    /* ACOMP1 */
+    if (SET == HBN_Get_INT_State(HBN_INT_ACOMP1)) {
+        HBN_Clear_IRQ(HBN_INT_ACOMP1);
+
+        if (hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1] != NULL) {
+            hbnInt1CbfArra[HBN_OUT1_INT_ACOMP1]();
+        }
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable HBN mode
+ *
+ * @param  aGPIOIeCfg: AON GPIO IE config,Bit0->GPIO18. Bit(s) of Wakeup GPIO(s) must not be set to
+ *                     0(s),say when use GPIO7 as wake up pin,aGPIOIeCfg should be 0x01.
+ * @param  ldoLevel: LDO volatge level
+ * @param  hbnLevel: HBN work level
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_HBN_LDO_LEVEL_TYPE(ldoLevel));
+    CHECK_PARAM(IS_HBN_LEVEL_TYPE(hbnLevel));
+
+    /* Setting from guide */
+    /* RAM Retion */
+    BL_WR_REG(HBN_BASE, HBN_SRAM, 0x24);
+    /* AON GPIO IE */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_IRQ_MODE);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_REG_AON_PAD_IE_SMT, aGPIOIeCfg);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_REG_EN_HW_PU_PD);
+    BL_WR_REG(HBN_BASE, HBN_IRQ_MODE, tmpVal);
+    ///* Power off 1.8V */
+    //tmpVal=BL_RD_REG(AON_BASE,AON_PMIP);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO11_SOC);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_RF);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_TOPLDO18_IO);
+    ///* SOC11 enum is not the same as VDD11*/
+    //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_SOC_VOUT_SEL,ldoLevel-1);
+    //BL_WR_REG(AON_BASE,AON_PMIP,tmpVal);
+    //
+    ///* Set RT voltage */
+    //tmpVal=BL_RD_REG(AON_BASE,AON);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW3);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW2);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_SW1);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_TOPLDO18_IO_BYPASS);
+    //tmpVal=BL_CLR_REG_BIT(tmpVal,AON_PU_LDO18_AON);
+    ///* RT11 enum is not the same as VDD11*/
+    //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_TOPLDO11_RT_VOUT_SEL,ldoLevel-1);
+    //tmpVal=BL_SET_REG_BITS_VAL(tmpVal,AON_VDD11_SEL,ldoLevel);
+    //BL_WR_REG(AON_BASE,AON,tmpVal);
+
+    /* Select RC32M */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_GLB);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, HBN_ROOT_CLK_SEL, 0);
+    BL_WR_REG(HBN_BASE, HBN_GLB, tmpVal);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Set HBN flag */
+    BL_WR_REG(HBN_BASE, HBN_RSV0, HBN_STATUS_ENTER_FLAG);
+
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+
+    /* Set HBN level, (HBN_PWRDN_HBN_RAM not use) */
+    switch (hbnLevel) {
+        case HBN_LEVEL_0:
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_1:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_2:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        case HBN_LEVEL_3:
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_CORE);
+            tmpVal = BL_SET_REG_BIT(tmpVal, HBN_PWRDN_HBN_RTC);
+            break;
+
+        default:
+            break;
+    }
+
+    /* Set power on option:0 for por reset twice for robust 1 for reset only once*/
+    tmpVal = BL_CLR_REG_BIT(tmpVal, HBN_PWR_ON_OPTION);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    /* Enable HBN mode */
+    tmpVal = BL_RD_REG(HBN_BASE, HBN_CTL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, HBN_MODE);
+    BL_WR_REG(HBN_BASE, HBN_CTL, tmpVal);
+
+    while (1) {
+        BL702_Delay_MS(1000);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out0 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out0_IRQHandler_Install(void)
+{
+    Interrupt_Handler_Register(HBN_OUT0_IRQn, HBN_OUT0_IRQHandler);
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  HBN out1 IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type HBN_Out1_IRQHandler_Install(void)
+{
+    Interrupt_Handler_Register(HBN_OUT1_IRQn, HBN_OUT1_IRQHandler);
+    return SUCCESS;
+}
+
+/*@} end of group HBN_Public_Functions */
+
+/*@} end of group HBN */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_l1c.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_l1c.c
new file mode 100755
index 0000000000..f298f972f1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_l1c.c
@@ -0,0 +1,647 @@
+/**
+  ******************************************************************************
+  * @file    bl702_l1c.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_l1c.h"
+#include "bl702_common.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  L1C
+ *  @{
+ */
+
+/** @defgroup  L1C_Private_Macros
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Macros */
+
+/** @defgroup  L1C_Private_Types
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Types */
+
+/** @defgroup  L1C_Private_Variables
+ *  @{
+ */
+static intCallback_Type *l1cBmxErrIntCbfArra[L1C_BMX_ERR_INT_ALL] = { NULL };
+static intCallback_Type *l1cBmxToIntCbfArra[L1C_BMX_TO_INT_ALL] = { NULL };
+
+/*@} end of group L1C_Private_Variables */
+
+/** @defgroup  L1C_Global_Variables
+ *  @{
+ */
+
+/*@} end of group L1C_Global_Variables */
+
+/** @defgroup  L1C_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Fun_Declaration */
+
+/** @defgroup  L1C_Private_Functions
+ *  @{
+ */
+
+/*@} end of group L1C_Private_Functions */
+
+/** @defgroup  L1C_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Enable cache
+ *
+ * @param  wayDisable: cache way disable config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Enable_Set(uint8_t wayDisable)
+{
+    uint32_t tmpVal;
+    uint32_t cnt = 0;
+    uint8_t finWayDisable = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CNT_EN);
+    finWayDisable = BL_GET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    /*Set Tag RAM to zero */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_INVALID_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_INVALID_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Polling for invalid done */
+    do {
+        BL702_Delay_US(1);
+        cnt++;
+        tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_INVALID_DONE) && cnt < 100);
+
+    /* data flush */
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_FLUSH_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    /* Left space for hardware change status*/
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    /* Polling for flush done */
+    do {
+        BL702_Delay_US(1);
+        cnt++;
+        tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    } while (!BL_IS_REG_BIT_SET(tmpVal, L1C_FLUSH_DONE) && cnt < 100);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_FLUSH_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BYPASS);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BYPASS);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CNT_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (wayDisable != 0xff) {
+        finWayDisable = wayDisable;
+    }
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WAY_DIS);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal |= (finWayDisable << L1C_WAY_DIS_POS);
+
+    /* If way disable is 0x0f, cacheable can't be set */
+    if (finWayDisable != 0x0f) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C cache write set
+ *
+ * @param  wtEn: L1C write through enable
+ * @param  wbEn: L1C write back enable
+ * @param  waEn: L1C write allocate enable
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION L1C_Cache_Write_Set(BL_Fun_Type wtEn, BL_Fun_Type wbEn, BL_Fun_Type waEn)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (wtEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WT_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WT_EN);
+    }
+
+    if (wbEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WB_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WB_EN);
+    }
+
+    if (waEn) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WA_EN);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WA_EN);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Flush cache external api
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION L1C_Cache_Flush(void)
+{
+    uint32_t tmpVal;
+
+    /* Disable early respone */
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    L1C_Cache_Enable_Set((tmpVal >> L1C_WAY_DIS_POS) & 0xf);
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+    __NOP();
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get cache hit count
+ *
+ * @param  hitCountLow: hit count low 32 bits pointer
+ * @param  hitCountHigh: hit count high 32 bits pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh)
+{
+    *hitCountLow = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_LSB);
+    *hitCountHigh = BL_RD_REG(L1C_BASE, L1C_HIT_CNT_MSB);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Get cache miss count
+ *
+ * @param  None
+ *
+ * @return Cache miss count
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+uint32_t ATTR_TCM_SECTION L1C_Cache_Miss_Count_Get(void)
+{
+    return BL_RD_REG(L1C_BASE, L1C_MISS_CNT);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable read from flash or psram with cache
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION L1C_Cache_Read_Disable(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  wrap set
+ *
+ * @param  wrap: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Wrap(BL_Fun_Type wrap)
+{
+    uint32_t tmpVal = 0;
+    uint8_t cacheEn = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    cacheEn = BL_IS_REG_BIT_SET(L1C_BASE, L1C_CACHEABLE);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (wrap == ENABLE) {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_WRAP_DIS);
+    } else {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_WRAP_DIS);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (cacheEn != 0) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+        BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+    }
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  cache way disable set
+ *
+ * @param  disableVal: cache way disable value
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_Set_Way_Disable(uint8_t disableVal)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_WAY_DIS, disableVal);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    if (disableVal != 0x0f) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_CACHEABLE);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_CACHEABLE);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set for ROM 2T access if CPU freq >120MHz
+ *
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_TCM_SECTION L1C_IROM_2T_Access_Set(uint8_t enable)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+
+    if (enable) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_IROM_2T_ACCESS);
+    }
+
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX init
+ *
+ * @param  l1cBmxCfg: L1C BMX config
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Init(L1C_BMX_Cfg_Type *l1cBmxCfg)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM((l1cBmxCfg->timeoutEn) <= 0xF);
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_TIMEOUT_EN, l1cBmxCfg->timeoutEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_EN, l1cBmxCfg->errEn);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, L1C_BMX_ARB_MODE, l1cBmxCfg->arbMod);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+#ifndef BFLB_USE_HAL_DRIVER
+    Interrupt_Handler_Register(L1C_BMX_ERR_IRQn, L1C_BMX_ERR_IRQHandler);
+    Interrupt_Handler_Register(L1C_BMX_TO_IRQn, L1C_BMX_TO_IRQHandler);
+#endif
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX address monitor enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Addr_Monitor_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX address monitor disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_Addr_Monitor_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_ADDR_DIS);
+    BL_WR_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX bus error response enable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_BusErrResponse_Enable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_SET_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX bus error response disable
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_BusErrResponse_Disable(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_CONFIG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, L1C_BMX_ERR_EN);
+    BL_WR_REG(L1C_BASE, L1C_CONFIG, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Get L1C BMX error status
+ *
+ * @param  errType: L1C BMX error status type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type L1C_BMX_Get_Status(L1C_BMX_BUS_ERR_Type errType)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_L1C_BMX_BUS_ERR_TYPE(errType));
+
+    tmpVal = BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR_EN);
+
+    if (errType == L1C_BMX_BUS_ERR_TRUSTZONE_DECODE) {
+        return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_TZ) ? SET : RESET;
+    } else {
+        return BL_GET_REG_BITS_VAL(tmpVal, L1C_BMX_ERR_DEC) ? SET : RESET;
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get L1C BMX error address
+ *
+ * @param  None
+ *
+ * @return NP L1C BMX error address
+ *
+*******************************************************************************/
+uint32_t L1C_BMX_Get_Err_Addr(void)
+{
+    return BL_RD_REG(L1C_BASE, L1C_BMX_ERR_ADDR);
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX error interrupt callback install
+ *
+ * @param  intType: L1C BMX error interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_ERR_INT_Callback_Install(L1C_BMX_ERR_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_L1C_BMX_ERR_INT_TYPE(intType));
+
+    l1cBmxErrIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX ERR interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_ERR_IRQHandler(void)
+{
+    L1C_BMX_ERR_INT_Type intType;
+
+    for (intType = L1C_BMX_ERR_INT_ERR; intType < L1C_BMX_ERR_INT_ALL; intType++) {
+        if (l1cBmxErrIntCbfArra[intType] != NULL) {
+            l1cBmxErrIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("L1C_BMX_ERR_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX timeout interrupt callback install
+ *
+ * @param  intType: L1C BMX timeout interrupt type
+ * @param  cbFun: callback
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type L1C_BMX_TIMEOUT_INT_Callback_Install(L1C_BMX_TO_INT_Type intType, intCallback_Type *cbFun)
+{
+    CHECK_PARAM(IS_L1C_BMX_TO_INT_TYPE(intType));
+
+    l1cBmxToIntCbfArra[intType] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  L1C BMX Time Out interrupt IRQ handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_HAL_DRIVER
+void L1C_BMX_TO_IRQHandler(void)
+{
+    L1C_BMX_TO_INT_Type intType;
+
+    for (intType = L1C_BMX_TO_INT_TIMEOUT; intType < L1C_BMX_TO_INT_ALL; intType++) {
+        if (l1cBmxToIntCbfArra[intType] != NULL) {
+            l1cBmxToIntCbfArra[intType]();
+        }
+    }
+
+    while (1) {
+        //MSG("L1C_BMX_TO_IRQHandler\r\n");
+        BL702_Delay_MS(1000);
+    }
+}
+#endif
+
+/*@} end of group L1C_Public_Functions */
+
+/*@} end of group L1C */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_pds.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_pds.c
new file mode 100755
index 0000000000..4aedd1e627
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_pds.c
@@ -0,0 +1,1364 @@
+/**
+  ******************************************************************************
+  * @file    bl702_pds.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702.h"
+#include "bl702_pds.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  PDS
+ *  @{
+ */
+
+/** @defgroup  PDS_Private_Macros
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Macros */
+
+/** @defgroup  PDS_Private_Types
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Types */
+
+/** @defgroup  PDS_Private_Variables
+ *  @{
+ */
+static intCallback_Type *pdsIntCbfArra[PDS_INT_MAX][1] = { { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL }, { NULL } };
+
+/*@} end of group PDS_Private_Variables */
+
+/** @defgroup  PDS_Global_Variables
+ *  @{
+ */
+
+/*@} end of group PDS_Global_Variables */
+
+/** @defgroup  PDS_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Fun_Declaration */
+
+/** @defgroup  PDS_Private_Functions
+ *  @{
+ */
+
+/*@} end of group PDS_Private_Functions */
+
+/** @defgroup  PDS_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  power down sleep ram configure
+ *
+ * @param  ramCfg: power down sleep force ram configuration
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_RAM_Config(PDS_RAM_CFG_Type *ramCfg)
+{
+    if (NULL == ramCfg) {
+        return ERROR;
+    }
+
+    /* PDS_RAM1 config */
+    BL_WR_REG(PDS_BASE, PDS_RAM1, *(uint32_t *)ramCfg);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep set pad configure
+ *
+ * @param  pin: power down sleep pad num
+ * @param  cfg: power down sleep pad type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Pad_Config(PDS_PAD_PIN_Type pin, PDS_PAD_CFG_Type cfg)
+{
+    uint32_t tmpVal = 0;
+    uint32_t tmpPu = 0;
+    uint32_t tmpPd = 0;
+
+    if (pin < PDS_PAD_PIN_GPIO_23) {
+        /* GPIO17 - GPIO22 */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);
+
+        switch (cfg) {
+            case PDS_PAD_CFG_PULL_NONE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
+                break;
+
+            case PDS_PAD_CFG_PULL_DOWN:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) & ~(1 << pin);
+                break;
+
+            case PDS_PAD_CFG_PULL_UP:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) & ~(1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
+                break;
+
+            case PDS_PAD_CFG_ACTIVE_IE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD) | (1 << pin);
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU) | (1 << pin);
+                break;
+
+            default:
+                break;
+        }
+
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PD, tmpPd);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_22_17_PU, tmpPu);
+        BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
+    } else {
+        /* GPIO23 - GPIO28 */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_SET_PU_PD);
+
+        switch (cfg) {
+            case PDS_PAD_CFG_PULL_NONE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            case PDS_PAD_CFG_PULL_DOWN:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            case PDS_PAD_CFG_PULL_UP:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) & ~(1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            case PDS_PAD_CFG_ACTIVE_IE:
+                tmpPd = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                tmpPu = BL_GET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU) | (1 << (pin - PDS_PAD_PIN_GPIO_23));
+                break;
+
+            default:
+                break;
+        }
+
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PD, tmpPd);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CR_PDS_GPIO_28_23_PU, tmpPu);
+        BL_WR_REG(PDS_BASE, PDS_GPIO_SET_PU_PD, tmpVal);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Enable power down sleep
+ *
+ * @param  cfg: power down sleep configuration 1
+ * @param  cfg4: power down sleep configuration 2
+ * @param  pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_App_Enable(PDS_CTL_Type *cfg, PDS_CTL4_Type *cfg4, uint32_t pdsSleepCnt)
+{
+    uint32_t tmpVal=0;
+    /* PDS sleep time 1~PDS_WARMUP_LATENCY_CNT <=> error */
+    /* PDS sleep time >PDS_WARMUP_LATENCY_CNT <=> correct */
+    if ((pdsSleepCnt) && (pdsSleepCnt <= PDS_WARMUP_LATENCY_CNT)) {
+        return ERROR;
+    } else if (pdsSleepCnt > PDS_WARMUP_LATENCY_CNT) {
+        BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_LATENCY_CNT);
+    } else {
+        /* PDS sleep time 0 ,means mask pds_timer wakeup  */
+    }
+
+    /* PDS_CTL4 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL4, *(uint32_t *)cfg4);
+
+    /* PDS_CTL config */
+    if (cfg->pdsStart) {
+        /* clear pds int */
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+        BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg & ~(1 << 0)));
+        BL_WR_REG(PDS_BASE, PDS_CTL, (*(uint32_t *)cfg | (1 << 0)));
+    } else {
+        BL_WR_REG(PDS_BASE, PDS_CTL, *(uint32_t *)cfg);
+    }
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  cfg2: power down sleep force configuration 1
+ * @param  cfg3: power down sleep force configuration 2
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Force_Config(PDS_CTL2_Type *cfg2, PDS_CTL3_Type *cfg3)
+{
+    /* PDS_CTL2 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL2, *(uint32_t *)cfg2);
+
+    /* PDS_CTL3 config */
+    BL_WR_REG(PDS_BASE, PDS_CTL3, *(uint32_t *)cfg3);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep force configure
+ *
+ * @param  defaultLvCfg: power down sleep default level configuration
+ * @param  pdsSleepCnt: power down sleep time count
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type ATTR_TCM_SECTION PDS_Default_Level_Config(PDS_DEFAULT_LV_CFG_Type *defaultLvCfg, uint32_t pdsSleepCnt)
+{
+    PDS_Force_Config((PDS_CTL2_Type *)&(defaultLvCfg->pdsCtl2), (PDS_CTL3_Type *)&(defaultLvCfg->pdsCtl3));
+    PDS_App_Enable((PDS_CTL_Type *)&(defaultLvCfg->pdsCtl), (PDS_CTL4_Type *)&(defaultLvCfg->pdsCtl4), pdsSleepCnt);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep int enable
+ *
+ * @param  intType: PDS int type
+ * @param  enable: ENABLE or DISABLE
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntEn(PDS_INT_Type intType, BL_Fun_Type enable)
+{
+    uint32_t offset = 0;
+    uint32_t tmpVal = 0;
+
+    if ((intType < PDS_INT_PDS_SLEEP_CNT) || (intType > PDS_INT_KYS_QDEC)) {
+        return ERROR;
+    }
+
+    switch (intType) {
+        case PDS_INT_WAKEUP:
+        case PDS_INT_RF_DONE:
+        case PDS_INT_PLL_DONE:
+            return ERROR;
+
+        case PDS_INT_PDS_SLEEP_CNT:
+            offset = 16;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT0:
+            offset = 17;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT1:
+            offset = 18;
+            break;
+
+        case PDS_INT_GPIO_IRQ:
+            offset = 19;
+            break;
+
+        case PDS_INT_IRRX:
+            offset = 20;
+            break;
+
+        case PDS_INT_BLE_SLP_IRQ:
+            offset = 21;
+            break;
+
+        case PDS_INT_USB_WKUP:
+            offset = 22;
+            break;
+
+        case PDS_INT_KYS_QDEC:
+            offset = 23;
+            break;
+
+        case PDS_INT_MAX:
+            break;
+
+        default:
+            break;
+    }
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+
+    if (enable) {
+        tmpVal = tmpVal | (1 << offset);
+    } else {
+        tmpVal = tmpVal & ~(1 << offset);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep int mask
+ *
+ * @param  intType: PDS int type
+ * @param  intMask: MASK or UNMASK
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntMask(PDS_INT_Type intType, BL_Mask_Type intMask)
+{
+    uint32_t offset = 0;
+    uint32_t tmpVal = 0;
+
+    if (intType > PDS_INT_PLL_DONE) {
+        return ERROR;
+    }
+
+    switch (intType) {
+        case PDS_INT_WAKEUP:
+            offset = 8;
+            break;
+
+        case PDS_INT_RF_DONE:
+            offset = 10;
+            break;
+
+        case PDS_INT_PLL_DONE:
+            offset = 11;
+            break;
+
+        case PDS_INT_PDS_SLEEP_CNT:
+        case PDS_INT_HBN_IRQ_OUT0:
+        case PDS_INT_HBN_IRQ_OUT1:
+        case PDS_INT_GPIO_IRQ:
+        case PDS_INT_IRRX:
+        case PDS_INT_BLE_SLP_IRQ:
+        case PDS_INT_USB_WKUP:
+        case PDS_INT_KYS_QDEC:
+        case PDS_INT_MAX:
+        default:
+            return ERROR;
+    }
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+
+    if (intMask != UNMASK) {
+        tmpVal = tmpVal | (1 << offset);
+    } else {
+        tmpVal = tmpVal & ~(1 << offset);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep int status
+ *
+ * @param  intType: PDS int type
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_IntStatus(PDS_INT_Type intType)
+{
+    uint32_t offset = 0;
+
+    switch (intType) {
+        case PDS_INT_WAKEUP:
+            offset = 0;
+            break;
+
+        case PDS_INT_RF_DONE:
+            offset = 2;
+            break;
+
+        case PDS_INT_PLL_DONE:
+            offset = 3;
+            break;
+
+        case PDS_INT_PDS_SLEEP_CNT:
+            offset = 24;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT0:
+            offset = 25;
+            break;
+
+        case PDS_INT_HBN_IRQ_OUT1:
+            offset = 26;
+            break;
+
+        case PDS_INT_GPIO_IRQ:
+            offset = 27;
+            break;
+
+        case PDS_INT_IRRX:
+            offset = 28;
+            break;
+
+        case PDS_INT_BLE_SLP_IRQ:
+            offset = 29;
+            break;
+
+        case PDS_INT_USB_WKUP:
+            offset = 30;
+            break;
+
+        case PDS_INT_KYS_QDEC:
+            offset = 31;
+            break;
+
+        case PDS_INT_MAX:
+            break;
+
+        default:
+            break;
+    }
+
+    return (BL_RD_REG(PDS_BASE, PDS_INT) & (1 << offset)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  clear power down sleep int status
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_IntClear(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CR_PDS_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep PLL status
+ *
+ * @param  None
+ *
+ * @return PDS PLL status
+ *
+*******************************************************************************/
+PDS_PLL_STS_Type PDS_Get_PdsPllStstus(void)
+{
+    return (PDS_PLL_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_PLL_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep RF status
+ *
+ * @param  None
+ *
+ * @return PDS RF status
+ *
+*******************************************************************************/
+PDS_RF_STS_Type PDS_Get_PdsRfStstus(void)
+{
+    return (PDS_RF_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_RF_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep status
+ *
+ * @param  None
+ *
+ * @return PDS status
+ *
+*******************************************************************************/
+PDS_STS_Type PDS_Get_PdsStstus(void)
+{
+    return (PDS_STS_Type)BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_STAT), PDS_RO_PDS_STATE);
+}
+
+/****************************************************************************/ /**
+ * @brief  power down sleep clear reset event
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Clear_Reset_Event(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLR_RESET_EVENT);
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  get power down sleep reset event
+ *
+ * @param  event: power down sleep reset event
+ *
+ * @return SET or RESET
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_Reset_Event(PDS_RST_EVENT_Type event)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal, PDS_RESET_EVENT);
+
+    return (tmpVal & (1 << event)) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt config
+ *
+ * @param  src: PDS VDDCORE src pin num
+ * @param  mode: PDS VDDCORE src pin interrupt type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntCfg(PDS_VDDCORE_GPIO_SRC_Type src, PDS_AON_GPIO_INT_Trigger_Type mode)
+{
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_PDS_VDDCORE_GPIO_SRC_TYPE(src));
+    CHECK_PARAM(IS_PDS_AON_GPIO_INT_Trigger_TYPE(mode));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_SELECT, src);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_GPIO_INT_MODE, mode);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt mask
+ *
+ * @param  intMask: None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntMask(BL_Mask_Type intMask)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+
+    if (intMask != UNMASK) {
+        tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
+    } else {
+        tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_MASK);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt mask
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Sts_Type PDS_Get_Vddcore_GPIO_IntStatus(void)
+{
+    return BL_GET_REG_BITS_VAL(BL_RD_REG(PDS_BASE, PDS_GPIO_INT), PDS_GPIO_INT_STAT) ? SET : RESET;
+}
+
+/****************************************************************************/ /**
+ * @brief  set power down sleep VDDCORE gpio interrupt mask
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Vddcore_GPIO_IntClear(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_GPIO_INT);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_GPIO_INT_CLR);
+    BL_WR_REG(PDS_BASE, PDS_GPIO_INT, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Install PDS interrupt callback function
+ *
+ * @param  intType: PDS int type
+ * @param  cbFun: cbFun: Pointer to interrupt callback function. The type should be void (*fn)(void)
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Int_Callback_Install(PDS_INT_Type intType, intCallback_Type *cbFun)
+{
+    pdsIntCbfArra[intType][0] = cbFun;
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  Trim RC32M
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Trim_RC32M(void)
+{
+    Efuse_Ana_RC32M_Trim_Type trim;
+    int32_t tmpVal = 0;
+
+    EF_Ctrl_Read_RC32M_Trim(&trim);
+
+    if (trim.trimRc32mExtCodeEn) {
+        if (trim.trimRc32mCodeFrExtParity == EF_Ctrl_Get_Trim_Parity(trim.trimRc32mCodeFrExt, 8)) {
+            tmpVal = BL_RD_REG(PDS_BASE, PDS_RC32M_CTRL0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_RC32M_CODE_FR_EXT, trim.trimRc32mCodeFrExt);
+            tmpVal = BL_SET_REG_BIT(tmpVal, PDS_RC32M_EXT_CODE_EN);
+            BL_WR_REG(PDS_BASE, PDS_RC32M_CTRL0, tmpVal);
+            BL702_Delay_US(2);
+            return SUCCESS;
+        }
+    }
+
+    return ERROR;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select RC32M as PLL ref source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_RC32M_As_PLL_Ref(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Select XTAL as PLL ref source
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Select_XTAL_As_PLL_Ref(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_XTAL_RC32M_SEL);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power on PLL
+ *
+ * @param  xtalType: xtal type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_XTAL_TYPE(xtalType));
+
+    /**************************/
+    /* select PLL XTAL source */
+    /**************************/
+
+    if ((xtalType == PDS_PLL_XTAL_RC32M) || (xtalType == PDS_PLL_XTAL_NONE)) {
+        PDS_Trim_RC32M();
+        PDS_Select_RC32M_As_PLL_Ref();
+    } else {
+        PDS_Select_XTAL_As_PLL_Ref();
+    }
+
+    /*******************************************/
+    /* PLL power down first, not indispensable */
+    /*******************************************/
+    /* power off PLL first, this step is not indispensable */
+    PDS_Power_Off_PLL();
+
+    /********************/
+    /* PLL param config */
+    /********************/
+
+    /* clkpll_icp_1u */
+    /* clkpll_icp_5u */
+    /* clkpll_int_frac_sw */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_CP);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_1U, 0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_ICP_5U, 2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_INT_FRAC_SW, 0);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_CP, tmpVal);
+
+    /* clkpll_c3 */
+    /* clkpll_cz */
+    /* clkpll_rz */
+    /* clkpll_r4 */
+    /* clkpll_r4_short */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_RZ);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_C3, 3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_CZ, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RZ, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4_SHORT, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_R4, 2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_RZ, tmpVal);
+
+    /* clkpll_refdiv_ratio */
+    /* clkpll_postdiv */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 0x14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    /* clkpll_sdmin */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, 0x3C0000);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
+
+    /* clkpll_sel_fb_clk */
+    /* clkpll_sel_sample_clk can be 0/1, default is 1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_FBDV);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_FB_CLK, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SEL_SAMPLE_CLK, 1);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_FBDV, tmpVal);
+
+    /*************************/
+    /* PLL power up sequence */
+    /*************************/
+
+    /* pu_clkpll_sfreg=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_US(5);
+
+    /* pu_clkpll=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /* clkpll_pu_cp=1 */
+    /* clkpll_pu_pfd=1 */
+    /* clkpll_pu_fbdv=1 */
+    /* clkpll_pu_postdiv=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_US(5);
+
+    /* clkpll_sdm_reset=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL702_Delay_US(1);
+    /* clkpll_reset_fbdv=1 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_SET_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL702_Delay_US(2);
+    /* clkpll_reset_fbdv=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_RESET_FBDV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+    BL702_Delay_US(1);
+    /* clkpll_sdm_reset=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_SDM_RESET);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+/** PLL output config **/
+/*
+[8]    1'h0    r/w    clkpll_en_32m
+[7]    1'h0    r/w    clkpll_en_48m
+[6]    1'h0    r/w    clkpll_en_80m
+[5]    1'h0    r/w    clkpll_en_96m
+[4]    1'h0    r/w    clkpll_en_120m
+[3]    1'h0    r/w    clkpll_en_160m
+[2]    1'h0    r/w    clkpll_en_192m
+[1]    1'h0    r/w    clkpll_en_240m
+[0]    1'h0    r/w    clkpll_en_480m
+*/
+
+/****************************************************************************/ /**
+ * @brief  Enable all PLL clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal |= 0x1FF;
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable all PLL clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_All_Clks(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal &= (~0x1FF);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable PLL clock
+ *
+ * @param  pllClk: PLL clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal |= (1 << pllClk);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Disable PLL clock
+ *
+ * @param  pllClk: PLL clock type
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    uint32_t tmpVal = 0;
+
+    /* Check parameter*/
+    CHECK_PARAM(IS_PDS_PLL_CLK_TYPE(pllClk));
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN);
+    tmpVal &= (~(1 << pllClk));
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_OUTPUT_EN, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power off PLL
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Power_Off_PLL(void)
+{
+    uint32_t tmpVal = 0;
+
+    /* pu_clkpll_sfreg=0 */
+    /* pu_clkpll=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL_SFREG);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_PU_CLKPLL);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /* clkpll_pu_cp=0 */
+    /* clkpll_pu_pfd=0 */
+    /* clkpll_pu_fbdv=0 */
+    /* clkpll_pu_postdiv=0 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_CP);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_PFD);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_FBDV);
+    tmpVal = BL_CLR_REG_BIT(tmpVal, PDS_CLKPLL_PU_POSTDIV);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    return SUCCESS;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Set Audio PLL clock
+ *
+ * @param  audioPLLFreq: Audio PLL sel frequency , have two vaild input 12.288 or 11.289 MHZ
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+__WEAK
+BL_Err_Type ATTR_CLOCK_SECTION PDS_Set_Audio_PLL_Freq(PDS_AUDIO_PLL_Type audioPLLFreq)
+{
+    uint32_t sdmin_table[] = { 0x374BC6, 0x32CCED, 0x32CCED, 0x6E978D, 0x6C0000, 0x3E8000};
+    uint32_t tmpVal = 0;
+
+    CHECK_PARAM(IS_PDS_AUDIO_PLL_TYPE(audioPLLFreq));
+
+    /*set PDS_CLKPLL_REFDIV_RATIO as 0x2 */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_REFDIV_RATIO, 0x2);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    /*set clkpll_sdmin as sdmin*/
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_SDM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_SDMIN, (uint32_t)sdmin_table[audioPLLFreq % (sizeof(sdmin_table) / sizeof(sdmin_table[0]))]);
+
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_SDM, tmpVal);
+
+    /*reset pll */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_PU_RST_CLKPLL);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL_SFREG, 1);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_MS(10);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_PU_CLKPLL, 1);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 1);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    BL702_Delay_MS(10);
+
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_RESET_FBDV, 0);
+    BL_WR_REG(PDS_BASE, PDS_PU_RST_CLKPLL, tmpVal);
+
+    /*set div for audio pll */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+
+    if (audioPLLFreq != AUDIO_PLL_5644800_HZ) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 36);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_POSTDIV, 72);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  PDS software reset
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Reset(void)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = *(uint32_t *)0x40000010;
+    tmpVal = tmpVal | (1 << 14);
+    *(uint32_t *)0x40000010 = tmpVal;
+
+    tmpVal = *(uint32_t *)0x40000010;
+    tmpVal = tmpVal & ~(1 << 14);
+    *(uint32_t *)0x40000010 = tmpVal;
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Enable power down sleep
+ *
+ * @param  cfg: power down sleep configuration 1
+ * @param  pdsSleepCnt: power down sleep count cycle
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt)
+{
+    uint32_t *p = (uint32_t *)cfg;
+
+    if (pdsSleepCnt - PDS_WARMUP_CNT <= 0) {
+        return;
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_TIME1, pdsSleepCnt - PDS_WARMUP_CNT);
+
+    /* Set PDS control register  */
+    BL_WR_REG(PDS_BASE, PDS_CTL, *p);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS Auto mode wake up counter config
+ *
+ * @param  sleepDuration: sleep time, total pds = sleep_duration + max_warmup_cnt (32K clock cycles),
+ *                        recommend maxWarmCnt*N+2
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Auto_Time_Config(uint32_t sleepDuration)
+{
+    /* PDS_TIME1 */
+    BL_WR_REG(PDS_BASE, PDS_TIME1, sleepDuration);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS Auto mode config and enable
+ *
+ * @param  powerCfg: PDS Auto mode power domain config
+ * @param  normalCfg: PDS Auto mode power normal config
+ * @param  enable: PDS Auto mode Enable or Disable
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable)
+{
+    uint32_t pdsCtl = 0;
+
+    CHECK_PARAM(IS_PDS_LDO_VOLTAGE_TYPE(normalCfg->vddcoreVol));
+
+    /* power config */
+    pdsCtl |= (powerCfg->mbgPower << 31) |
+              (powerCfg->ldo18rfPower << 30) |
+              (powerCfg->sfregPower << 29) |
+              (powerCfg->pllPower << 28) |
+              (powerCfg->cpu0Power << 19) |
+              (powerCfg->rc32mPower << 17) |
+              (powerCfg->xtalPower << 14) |
+              (powerCfg->allPower << 13) |
+              (powerCfg->isoPower << 11) |
+              (powerCfg->bzPower << 10) |
+              (powerCfg->sramDisStanby << 9) |
+              (powerCfg->cgPower << 8) |
+              (powerCfg->cpu1Power << 7) |
+              (powerCfg->usbPower << 3);
+    pdsCtl = BL_SET_REG_BITS_VAL(pdsCtl, PDS_CR_PDS_LDO_VOL, normalCfg->vddcoreVol);
+    pdsCtl |= (normalCfg->vddcoreVolEn << 18) |
+              (normalCfg->cpu0NotNeedWFI << 21) |
+              (normalCfg->cpu1NotNeedWFI << 20) |
+              (normalCfg->busReset << 16) |
+              (normalCfg->disIrqWakeUp << 15) |
+              (normalCfg->powerOffXtalForever << 2) |
+              (normalCfg->sleepForever << 1);
+    BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);
+
+    pdsCtl = BL_RD_REG(PDS_BASE, PDS_CTL);
+
+    if (enable) {
+        pdsCtl |= (1 << 0);
+    } else {
+        pdsCtl &= ~(1 << 0);
+    }
+
+    BL_WR_REG(PDS_BASE, PDS_CTL, pdsCtl);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS force turn off XXX domain
+ *
+ * @param  domain: PDS domain
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain)
+{
+    uint32_t tmpVal = 0;
+
+    /* memory sleep */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_MEM_STBY_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* gate clock */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_GATE_CLK_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* pds reset */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_PDS_RST_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* isolation on */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_ISO_EN_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* power off */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal |= 1 << (domain + PDS_FORCE_PWR_OFF_OFFSET);
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  PDS force turn on XXX domain
+ *
+ * @param  domain: PDS domain
+ *
+ * @return None
+ *
+*******************************************************************************/
+#ifndef BFLB_USE_ROM_DRIVER
+__WEAK
+void ATTR_TCM_SECTION PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain)
+{
+    uint32_t tmpVal = 0;
+
+    /* power on */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_PWR_OFF_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* isolation off */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_ISO_EN_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* pds de_reset */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_PDS_RST_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* memory active */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_MEM_STBY_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+
+    /* clock on */
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CTL2);
+    tmpVal &= ~(1 << (domain + PDS_FORCE_GATE_CLK_OFFSET));
+    BL_WR_REG(PDS_BASE, PDS_CTL2, tmpVal);
+}
+#endif
+
+/****************************************************************************/ /**
+ * @brief  Power down sleep wake up interrupt handler
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void PDS_WAKEUP_IRQHandler(void)
+{
+    for (PDS_INT_Type intType = PDS_INT_WAKEUP; intType < PDS_INT_MAX; intType++) {
+        if (PDS_Get_IntStatus(intType) && (pdsIntCbfArra[intType][0] != NULL)) {
+            pdsIntCbfArra[intType][0]();
+        }
+    }
+    PDS_Set_Vddcore_GPIO_IntClear();
+    PDS_IntClear();
+}
+
+/****************************************************************************/ /**
+ * @brief  PDS wakeup IRQHandler install
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type PDS_WAKEUP_IRQHandler_Install(void)
+{
+    Interrupt_Handler_Register(PDS_WAKEUP_IRQn, PDS_WAKEUP_IRQHandler);
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief
+ *
+ * @param
+ *
+ * @return
+ *
+*******************************************************************************/
+BL_Err_Type PDS_Set_Clkpll_Top_Ctrl(uint8_t vg11Sel)
+{
+    uint32_t tmpVal = 0;
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL);
+    //clkpll_vg11_sel
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PDS_CLKPLL_VG11_SEL, vg11Sel);
+    BL_WR_REG(PDS_BASE, PDS_CLKPLL_TOP_CTRL, tmpVal);
+
+    return SUCCESS;
+}
+
+/*@} end of group PDS_Public_Functions */
+
+/*@} end of group PDS */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romapi.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romapi.c
new file mode 100755
index 0000000000..b55270ddbf
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romapi.c
@@ -0,0 +1,1125 @@
+#include "bl702_romdriver.h"
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_On_MBG(void)
+{
+    return RomDriver_AON_Power_On_MBG();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_Off_MBG(void)
+{
+    return RomDriver_AON_Power_Off_MBG();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_On_XTAL(void)
+{
+    return RomDriver_AON_Power_On_XTAL();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Set_Xtal_CapCode(uint8_t capIn, uint8_t capOut)
+{
+    return RomDriver_AON_Set_Xtal_CapCode(capIn, capOut);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    AON_Power_Off_XTAL(void)
+{
+    return RomDriver_AON_Power_Off_XTAL();
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION void ASM_Delay_Us(uint32_t core, uint32_t cnt)
+{
+    RomDriver_ASM_Delay_Us(core, cnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_US(uint32_t cnt)
+{
+    RomDriver_BL702_Delay_US(cnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void BL702_Delay_MS(uint32_t cnt)
+{
+    RomDriver_BL702_Delay_MS(cnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemCpy(void *dst, const void *src, uint32_t n)
+{
+    return RomDriver_BL702_MemCpy(dst, src, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t *
+    BL702_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n)
+{
+    return RomDriver_BL702_MemCpy4(dst, src, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void* BL702_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n) {
+    return RomDriver_BL702_MemCpy_Fast(pdst, psrc, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void *ARCH_MemCpy_Fast(void *pdst, const void *psrc, uint32_t n)
+{
+    return RomDriver_ARCH_MemCpy_Fast(pdst, psrc, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void *BL702_MemSet(void *s, uint8_t c, uint32_t n)
+{
+    return RomDriver_BL702_MemSet(s, c, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t *
+    BL702_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n)
+{
+    return RomDriver_BL702_MemSet4(dst, val, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int BL702_MemCmp(const void *s1, const void *s2, uint32_t n)
+{
+    return RomDriver_BL702_MemCmp(s1, s2, n);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    BFLB_Soft_CRC32(void *dataIn, uint32_t len)
+{
+    return RomDriver_BFLB_Soft_CRC32(dataIn, len);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    GLB_ROOT_CLK_Type
+    GLB_Get_Root_CLK_Sel(void)
+{
+    return RomDriver_GLB_Get_Root_CLK_Sel();
+}
+#if 0
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Set_System_CLK_Div(uint8_t hclkDiv, uint8_t bclkDiv)
+{
+    return RomDriver_GLB_Set_System_CLK_Div(hclkDiv, bclkDiv);
+}
+#endif
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    uint8_t
+    GLB_Get_BCLK_Div(void)
+{
+    return RomDriver_GLB_Get_BCLK_Div();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    uint8_t
+    GLB_Get_HCLK_Div(void)
+{
+    return RomDriver_GLB_Get_HCLK_Div();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    Update_SystemCoreClockWith_XTAL(GLB_DLL_XTAL_Type xtalType)
+{
+    return RomDriver_Update_SystemCoreClockWith_XTAL(xtalType);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Set_System_CLK(GLB_DLL_XTAL_Type xtalType, GLB_SYS_CLK_Type clkFreq)
+{
+    return RomDriver_GLB_Set_System_CLK(xtalType, clkFreq);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    System_Core_Clock_Update_From_RC32M(void)
+{
+    return RomDriver_System_Core_Clock_Update_From_RC32M();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Set_SF_CLK(uint8_t enable, GLB_SFLASH_CLK_Type clkSel, uint8_t div)
+{
+    return RomDriver_GLB_Set_SF_CLK(enable, clkSel, div);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Power_Off_DLL(void)
+{
+    return RomDriver_GLB_Power_Off_DLL();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Power_On_DLL(GLB_DLL_XTAL_Type xtalType)
+{
+    return RomDriver_GLB_Power_On_DLL(xtalType);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Enable_DLL_All_Clks(void)
+{
+    return RomDriver_GLB_Enable_DLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Enable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    return RomDriver_GLB_Enable_DLL_Clk(dllClk);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Disable_DLL_All_Clks(void)
+{
+    return RomDriver_GLB_Disable_DLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    GLB_Disable_DLL_Clk(GLB_DLL_CLK_Type dllClk)
+{
+    return RomDriver_GLB_Disable_DLL_Clk(dllClk);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_SW_System_Reset(void)
+{
+    return RomDriver_GLB_SW_System_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_SW_CPU_Reset(void)
+{
+    return RomDriver_GLB_SW_CPU_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_SW_POR_Reset(void)
+{
+    return RomDriver_GLB_SW_POR_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Select_Internal_Flash(void)
+{
+    return RomDriver_GLB_Select_Internal_Flash();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Swap_Flash_Pin(void)
+{
+    return RomDriver_GLB_Swap_Flash_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Swap_Flash_CS_IO2_Pin(void)
+{
+    return RomDriver_GLB_Swap_Flash_CS_IO2_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Swap_Flash_IO0_IO3_Pin(void)
+{
+    return RomDriver_GLB_Swap_Flash_IO0_IO3_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Select_Internal_PSram(void)
+{
+    return RomDriver_GLB_Select_Internal_PSram();
+}
+
+/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_Init(GLB_GPIO_Cfg_Type *cfg)
+{
+    return RomDriver_GLB_GPIO_Init(cfg);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_OUTPUT_Enable(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_OUTPUT_Enable(gpioPin);
+}
+#endif
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_OUTPUT_Disable(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_OUTPUT_Disable(gpioPin);
+}
+#endif
+
+/* aon pads GPIO9~GPIO13 IE controlled by HBN reg_aon_pad_ie_smt, abandon romdriver for this reason */
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+BL_Err_Type GLB_GPIO_Set_HZ(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_Set_HZ(gpioPin);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Deswap_Flash_Pin(void)
+{
+    return RomDriver_GLB_Deswap_Flash_Pin();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    GLB_Select_External_Flash(void)
+{
+    return RomDriver_GLB_Select_External_Flash();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint8_t
+    GLB_GPIO_Get_Fun(GLB_GPIO_Type gpioPin)
+{
+    return RomDriver_GLB_GPIO_Get_Fun(gpioPin);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Sts_Type
+    EF_Ctrl_Busy(void)
+{
+    return RomDriver_EF_Ctrl_Busy();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Sw_AHB_Clk_0(void)
+{
+    RomDriver_EF_Ctrl_Sw_AHB_Clk_0();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Load_Efuse_R0(void)
+{
+    RomDriver_EF_Ctrl_Load_Efuse_R0();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void EF_Ctrl_Clear(uint32_t index, uint32_t len)
+{
+    RomDriver_EF_Ctrl_Clear(index, len);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    uint8_t
+    EF_Ctrl_Get_Trim_Parity(uint32_t val, uint8_t len)
+{
+    return RomDriver_EF_Ctrl_Get_Trim_Parity(val, len);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32K_Trim(Efuse_Ana_RC32K_Trim_Type *trim)
+{
+    RomDriver_EF_Ctrl_Read_RC32K_Trim(trim);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION void EF_Ctrl_Read_RC32M_Trim(Efuse_Ana_RC32M_Trim_Type *trim)
+{
+    RomDriver_EF_Ctrl_Read_RC32M_Trim(trim);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Trim_RC32M(void)
+{
+    return RomDriver_PDS_Trim_RC32M();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Select_RC32M_As_PLL_Ref(void)
+{
+    return RomDriver_PDS_Select_RC32M_As_PLL_Ref();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Select_XTAL_As_PLL_Ref(void)
+{
+    return RomDriver_PDS_Select_XTAL_As_PLL_Ref();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Power_On_PLL(PDS_PLL_XTAL_Type xtalType)
+{
+    return RomDriver_PDS_Power_On_PLL(xtalType);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Enable_PLL_All_Clks(void)
+{
+    return RomDriver_PDS_Enable_PLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Disable_PLL_All_Clks(void)
+{
+    return RomDriver_PDS_Disable_PLL_All_Clks();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Enable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    return RomDriver_PDS_Enable_PLL_Clk(pllClk);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Disable_PLL_Clk(PDS_PLL_CLK_Type pllClk)
+{
+    return RomDriver_PDS_Disable_PLL_Clk(pllClk);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    PDS_Power_Off_PLL(void)
+{
+    return RomDriver_PDS_Power_Off_PLL();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Reset(void)
+{
+    RomDriver_PDS_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Enable(PDS_CFG_Type *cfg, uint32_t pdsSleepCnt)
+{
+    RomDriver_PDS_Enable(cfg, pdsSleepCnt);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Time_Config(uint32_t sleepDuration)
+{
+    RomDriver_PDS_Auto_Time_Config(sleepDuration);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Auto_Enable(PDS_AUTO_POWER_DOWN_CFG_Type *powerCfg, PDS_AUTO_NORMAL_CFG_Type *normalCfg, BL_Fun_Type enable)
+{
+    RomDriver_PDS_Auto_Enable(powerCfg, normalCfg, enable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_Off(PDS_FORCE_Type domain)
+{
+    RomDriver_PDS_Manual_Force_Turn_Off(domain);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void PDS_Manual_Force_Turn_On(PDS_FORCE_Type domain)
+{
+    RomDriver_PDS_Manual_Force_Turn_On(domain);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void HBN_Enable(uint8_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel)
+{
+    RomDriver_HBN_Enable(aGPIOIeCfg, ldoLevel, hbnLevel);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    HBN_Reset(void)
+{
+    return RomDriver_HBN_Reset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    HBN_GPIO_Dbg_Pull_Cfg(BL_Fun_Type pupdEn, BL_Fun_Type dlyEn, uint8_t dlySec, HBN_INT_Type gpioIrq, BL_Mask_Type gpioMask)
+{
+    return RomDriver_HBN_GPIO_Dbg_Pull_Cfg(pupdEn, dlyEn, dlySec, gpioIrq, gpioMask);
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    HBN_Trim_RC32K(void)
+{
+    return RomDriver_HBN_Trim_RC32K();
+}
+
+__ALWAYS_INLINE ATTR_CLOCK_SECTION
+    BL_Err_Type
+    HBN_Set_ROOT_CLK_Sel(HBN_ROOT_CLK_Type rootClk)
+{
+    return RomDriver_HBN_Set_ROOT_CLK_Sel(rootClk);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_state_save(spi_flash_cfg_type *p_flash_cfg, uint32_t *offset, uint8_t group, uint8_t bank)
+{
+    return RomDriver_XIP_SFlash_State_Save(p_flash_cfg, offset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_state_restore(spi_flash_cfg_type *p_flash_cfg, uint32_t offset, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_State_Restore(p_flash_cfg, io_mode, offset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_erase_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t startaddr, int len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_Erase_Need_Lock(p_flash_cfg, io_mode, startaddr, startaddr+len-1);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_write_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_Write_Need_Lock(p_flash_cfg, io_mode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_read_need_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_Read_Need_Lock(p_flash_cfg, io_mode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_get_jedecid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_GetJedecId_Need_Lock(p_flash_cfg, io_mode, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_get_deviceid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t is_32bits_addr, uint8_t *data, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_GetDeviceId_Need_Lock(p_flash_cfg, io_mode, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_get_uniqueid_need_lock(spi_flash_cfg_type *p_flash_cfg, uint8_t *data, uint8_t id_len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_GetUniqueId_Need_Lock(p_flash_cfg, io_mode, data, id_len);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr, uint8_t *data, uint32_t len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_Read_Via_Cache_Need_Lock(addr, data, len);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_xip_sflash_read_with_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *dst, int len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_Read_With_Lock(p_flash_cfg, io_mode, addr, dst, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_xip_sflash_write_with_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, uint8_t *src, int len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_Write_With_Lock(p_flash_cfg, io_mode, addr, src, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_xip_sflash_erase_with_lock(spi_flash_cfg_type *p_flash_cfg, uint32_t addr, int len, uint8_t group, uint8_t bank)
+{
+    uint8_t io_mode = p_flash_cfg->io_mode & 0xf;
+    return RomDriver_XIP_SFlash_Erase_With_Lock(p_flash_cfg, io_mode, addr, len);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_init(const struct sf_ctrl_cfg_type *p_sf_ctrl_cfg)
+{
+    RomDriver_SFlash_Init(p_sf_ctrl_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_sflash_setspimode(uint8_t mode)
+{
+    return RomDriver_SFlash_SetSPIMode(mode);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_read_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Read_Reg(flash_cfg, reg_index, reg_value, reg_len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_write_reg(spi_flash_cfg_type *flash_cfg, uint8_t reg_index, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Write_Reg(flash_cfg, reg_index, reg_value, reg_len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t readRegCmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Read_Reg_With_Cmd(flash_cfg, readRegCmd, reg_value, reg_len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t writeRegCmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    return RomDriver_SFlash_Write_Reg_With_Cmd(flash_cfg, writeRegCmd, reg_value, reg_len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_busy(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Busy(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Write_Enable(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_qspi_enable(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Qspi_Enable(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_volatile_reg_write_enable(spi_flash_cfg_type *flash_cfg)
+{
+    RomDriver_SFlash_Volatile_Reg_Write_Enable(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_chip_erase(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Chip_Erase(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_sector_erase(spi_flash_cfg_type *flash_cfg, uint32_t secNum)
+{
+    return RomDriver_SFlash_Sector_Erase(flash_cfg, secNum);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_blk32_erase(spi_flash_cfg_type *flash_cfg, uint32_t blkNum)
+{
+    return RomDriver_SFlash_Blk32_Erase(flash_cfg, blkNum);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_blk64_erase(spi_flash_cfg_type *flash_cfg, uint32_t blkNum)
+{
+    return RomDriver_SFlash_Blk64_Erase(flash_cfg, blkNum);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_erase(spi_flash_cfg_type *flash_cfg, uint32_t startaddr, uint32_t endaddr)
+{
+    return RomDriver_SFlash_Erase(flash_cfg, startaddr, endaddr);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_program(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_SFlash_Program(flash_cfg, io_mode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_get_uniqueid(uint8_t *data, uint8_t id_len)
+{
+    RomDriver_SFlash_GetUniqueId(data, id_len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_get_jedecid(spi_flash_cfg_type *flash_cfg, uint8_t *data)
+{
+    RomDriver_SFlash_GetJedecId(flash_cfg, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_get_deviceid(uint8_t *data, uint8_t is_32bits_addr)
+{
+    RomDriver_SFlash_GetDeviceId(data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_powerdown(void)
+{
+    RomDriver_SFlash_Powerdown();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_release_powerdown(spi_flash_cfg_type *flash_cfg)
+{
+    RomDriver_SFlash_Releae_Powerdown(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_restore_from_powerdown(spi_flash_cfg_type *p_flash_cfg, uint8_t flash_cont_read, uint8_t bank)
+{
+    return RomDriver_SFlash_Restore_From_Powerdown(p_flash_cfg, flash_cont_read);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_set_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+    RomDriver_SFlash_SetBurstWrap(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_disable_burst_wrap(spi_flash_cfg_type *flash_cfg)
+{
+    RomDriver_SFlash_DisableBurstWrap(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_software_reset(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Software_Reset(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_reset_continue_read(spi_flash_cfg_type *flash_cfg)
+{
+    return RomDriver_SFlash_Reset_Continue_Read(flash_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_set_idbus_cfg(spi_flash_cfg_type *flash_cfg,
+                              uint8_t io_mode, uint8_t contRead, uint32_t addr, uint32_t len, uint8_t bank)
+{
+    return RomDriver_SFlash_Set_IDbus_Cfg(flash_cfg, io_mode, contRead, addr, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_idbus_read_enable(spi_flash_cfg_type *flash_cfg, uint8_t io_mode, uint8_t contRead, uint8_t bank)
+{
+    return RomDriver_SFlash_IDbus_Read_Enable(flash_cfg, io_mode, contRead);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_cache_read_enable(spi_flash_cfg_type *flash_cfg,
+                             uint8_t io_mode, uint8_t contRead, uint8_t wayDisable)
+{
+    return RomDriver_SFlash_Cache_Read_Enable(flash_cfg, io_mode, contRead, wayDisable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sflash_cache_read_disable(void)
+{
+    RomDriver_SFlash_Cache_Read_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sflash_read(spi_flash_cfg_type *flash_cfg,
+                uint8_t io_mode, uint8_t contRead, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_SFlash_Read(flash_cfg, io_mode, contRead, addr, data, len);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Cache_Enable_Set(uint8_t wayDisable)
+{
+    return RomDriver_L1C_Cache_Enable_Set(wayDisable);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_l1c_cache_write_set(uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
+{
+    RomDriver_L1C_Cache_Write_Set(wt_en, wb_en, wa_en);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Cache_Flush(uint8_t wayDisable)
+{
+    return RomDriver_L1C_Cache_Flush(wayDisable);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Hit_Count_Get(uint32_t *hitCountLow, uint32_t *hitCountHigh)
+{
+    RomDriver_L1C_Cache_Hit_Count_Get(hitCountLow, hitCountHigh);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    L1C_Cache_Miss_Count_Get(void)
+{
+    return RomDriver_L1C_Cache_Miss_Count_Get();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void L1C_Cache_Read_Disable(void)
+{
+    RomDriver_L1C_Cache_Read_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Set_Wrap(BL_Fun_Type wrap)
+{
+    return RomDriver_L1C_Set_Wrap(wrap);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_Set_Way_Disable(uint8_t disableVal)
+{
+    return RomDriver_L1C_Set_Way_Disable(disableVal);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    BL_Err_Type
+    L1C_IROM_2T_Access_Set(uint8_t enable)
+{
+    return RomDriver_L1C_IROM_2T_Access_Set(enable);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_enable(const struct sf_ctrl_cfg_type *cfg)
+{
+    RomDriver_SF_Ctrl_Enable(cfg);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void bflb_sf_ctrl_psram_init(struct sf_ctrl_psram_cfg *psram_cfg)
+{
+    RomDriver_SF_Ctrl_Psram_Init(psram_cfg);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint8_t
+    bflb_sf_ctrl_get_clock_delay(void)
+{
+    return RomDriver_SF_Ctrl_Get_Clock_Delay();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_set_clock_delay(uint8_t delay)
+{
+    RomDriver_SF_Ctrl_Set_Clock_Delay(delay);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_cmds_set(struct sf_ctrl_cmds_cfg *cmds_cfg, uint8_t sel)
+{
+    RomDriver_SF_Ctrl_Cmds_Set(cmds_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_set_owner(uint8_t owner)
+{
+    RomDriver_SF_Ctrl_Set_Owner(owner);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_disable(void)
+{
+    RomDriver_SF_Ctrl_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_select_pad(uint8_t sel)
+{
+    RomDriver_SF_Ctrl_Select_Pad(sel);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_select_bank(uint8_t sel)
+{
+    RomDriver_SF_Ctrl_Select_Bank(sel);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_enable_be(void)
+{
+    RomDriver_SF_Ctrl_AES_Enable_BE();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_enable_le(void)
+{
+    RomDriver_SF_Ctrl_AES_Enable_LE();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_region(uint8_t region, uint8_t enable,
+                                                             uint8_t hw_key, uint32_t start_addr, uint32_t end_addr, uint8_t locked)
+{
+    RomDriver_SF_Ctrl_AES_Set_Region(region, enable, hw_key, start_addr, end_addr, locked);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_key(uint8_t region, uint8_t *key, uint8_t key_type)
+{
+    RomDriver_SF_Ctrl_AES_Set_Key(region, key, key_type);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_key_be(uint8_t region, uint8_t *key, uint8_t key_type)
+{
+    RomDriver_SF_Ctrl_AES_Set_Key_BE(region, key, key_type);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_iv(uint8_t region, uint8_t *iv, uint32_t addr_offset)
+{
+    RomDriver_SF_Ctrl_AES_Set_IV(region, iv, addr_offset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_set_iv_be(uint8_t region, uint8_t *iv, uint32_t addr_offset)
+{
+    RomDriver_SF_Ctrl_AES_Set_IV_BE(region, iv, addr_offset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_enable(void)
+{
+    RomDriver_SF_Ctrl_AES_Enable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_aes_disable(void)
+{
+    RomDriver_SF_Ctrl_AES_Disable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint8_t
+    bflb_sf_ctrl_is_aes_enable(void)
+{
+    return RomDriver_SF_Ctrl_Is_AES_Enable();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_set_flash_image_offset(uint32_t addr_offset, uint8_t group, uint8_t bank)
+{
+    RomDriver_SF_Ctrl_Set_Flash_Image_Offset(addr_offset);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    bflb_sf_ctrl_get_flash_image_offset(uint8_t group, uint8_t bank)
+{
+    return RomDriver_SF_Ctrl_Get_Flash_Image_Offset();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_select_clock(uint8_t sahb_type)
+{
+    RomDriver_SF_Ctrl_Select_Clock(sahb_type);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_sendcmd(struct sf_ctrl_cmd_cfg_type *cfg)
+{
+    RomDriver_SF_Ctrl_SendCmd(cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_flash_read_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+    RomDriver_SF_Ctrl_Flash_Read_Icache_Set(cfg, cmd_valid);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_psram_write_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+    RomDriver_SF_Ctrl_Psram_Write_Icache_Set(cfg, cmd_valid);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_ctrl_psram_read_icache_set(struct sf_ctrl_cmd_cfg_type *cfg, uint8_t cmd_valid)
+{
+    RomDriver_SF_Ctrl_Psram_Read_Icache_Set(cfg, cmd_valid);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint8_t
+    bflb_sf_ctrl_get_busy_state(void)
+{
+    return RomDriver_SF_Ctrl_GetBusyState();
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION int bflb_sf_cfg_deinit_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+    return RomDriver_SF_Cfg_Deinit_Ext_Flash_Gpio(ext_flash_pin);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_sf_cfg_init_ext_flash_gpio(uint8_t ext_flash_pin)
+{
+    RomDriver_SF_Cfg_Init_Ext_Flash_Gpio(ext_flash_pin);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_sf_cfg_get_flash_cfg_need_lock(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    return RomDriver_SF_Cfg_Get_Flash_Cfg_Need_Lock(flash_id, p_flash_cfg);
+}
+
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void bflb_sf_cfg_init_flash_gpio(uint8_t flash_pin_cfg, uint8_t restore_default)
+{
+    RomDriver_SF_Cfg_Init_Flash_Gpio(flash_pin_cfg, restore_default);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    uint32_t
+    bflb_sf_cfg_flash_identify(uint8_t callFromFlash, uint8_t flash_pin_cfg, uint8_t restore_default,
+                          spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    uint8_t auto_scan = 0;
+    uint8_t flash_pin = 0;
+    auto_scan = ((flash_pin_cfg >> 7) & 1);
+    flash_pin = (flash_pin_cfg & 0x7F);
+    return RomDriver_SF_Cfg_Flash_Identify(callFromFlash, auto_scan, flash_pin, restore_default, p_flash_cfg);
+}
+/******************************************************************************/
+
+/******************************************************************************/
+#if 0
+__ALWAYS_INLINE ATTR_TCM_SECTION
+void bflb_psram_init(struct spi_psram_cfg_type *psram_cfg, struct sf_ctrl_cmds_cfg *cmds_cfg, struct sf_ctrl_psram_cfg *psram_cfg)
+{
+    RomDriver_Psram_Init(psram_cfg, cmds_cfg, psram_cfg);
+}
+#endif
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_psram_readreg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
+{
+    RomDriver_Psram_ReadReg(psram_cfg, reg_value);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_psram_writereg(struct spi_psram_cfg_type *psram_cfg, uint8_t *reg_value)
+{
+    RomDriver_Psram_WriteReg(psram_cfg, reg_value);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_setdrivestrength(struct spi_psram_cfg_type *psram_cfg)
+{
+    return RomDriver_Psram_SetDriveStrength(psram_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_setburstwrap(struct spi_psram_cfg_type *psram_cfg)
+{
+    return RomDriver_Psram_SetBurstWrap(psram_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION void bflb_psram_readid(struct spi_psram_cfg_type *psram_cfg, uint8_t *data)
+{
+    RomDriver_Psram_ReadId(psram_cfg, data);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_enterquadmode(struct spi_psram_cfg_type *psram_cfg)
+{
+    return RomDriver_Psram_EnterQuadMode(psram_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_exitquadmode(struct spi_psram_cfg_type *psram_cfg)
+{
+    return RomDriver_Psram_ExitQuadMode(psram_cfg);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_toggleburstlength(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
+{
+    return RomDriver_Psram_ToggleBurstLength(psram_cfg, ctrl_mode);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_softwarereset(struct spi_psram_cfg_type *psram_cfg, uint8_t ctrl_mode)
+{
+    return RomDriver_Psram_SoftwareReset(psram_cfg, ctrl_mode);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_set_idbus_cfg(struct spi_psram_cfg_type *psram_cfg,
+                        uint8_t io_mode, uint32_t addr, uint32_t len)
+{
+    return RomDriver_Psram_Set_IDbus_Cfg(psram_cfg, io_mode, addr, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_cache_write_set(struct spi_psram_cfg_type *psram_cfg, uint8_t io_mode,
+                               uint8_t wt_en, uint8_t wb_en, uint8_t wa_en)
+{
+    return RomDriver_Psram_Cache_Write_Set(psram_cfg, io_mode, wt_en, wb_en, wa_en);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_write(struct spi_psram_cfg_type *psram_cfg,
+                uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_Psram_Write(psram_cfg, io_mode, addr, data, len);
+}
+
+__ALWAYS_INLINE ATTR_TCM_SECTION
+    int
+    bflb_psram_read(struct spi_psram_cfg_type *psram_cfg,
+               uint8_t io_mode, uint32_t addr, uint8_t *data, uint32_t len)
+{
+    return RomDriver_Psram_Read(psram_cfg, io_mode, addr, data, len);
+}
+/******************************************************************************/
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romdriver.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romdriver.c
new file mode 100755
index 0000000000..31c57ca562
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_romdriver.c
@@ -0,0 +1,246 @@
+#include "bl702_romdriver.h"
+#include 
+
+/** @addtogroup  BL702_Periph_Driver
+ *  @{
+ */
+
+/** @defgroup ROMDRIVER
+ *  @brief ROMDRIVER common functions
+ *  @{
+ */
+
+/** @defgroup ROMDRIVER_Private_Type
+ *  @{
+ */
+uint32_t const romDriverTable[] = {
+    0x07020001,
+    0x00000000,
+    0x00000000,
+    0x00000000,
+
+    [ROM_API_INDEX_AON_Power_On_MBG] = (uint32_t)AON_Power_On_MBG,
+    [ROM_API_INDEX_AON_Power_Off_MBG] = (uint32_t)AON_Power_Off_MBG,
+    [ROM_API_INDEX_AON_Power_On_XTAL] = (uint32_t)AON_Power_On_XTAL,
+    [ROM_API_INDEX_AON_Set_Xtal_CapCode] = (uint32_t)AON_Set_Xtal_CapCode,
+    [ROM_API_INDEX_AON_Power_Off_XTAL] = (uint32_t)AON_Power_Off_XTAL,
+
+    [ROM_API_INDEX_ASM_Delay_Us] = (uint32_t)ASM_Delay_Us,
+    [ROM_API_INDEX_BL702_Delay_US] = (uint32_t)BL702_Delay_US,
+    [ROM_API_INDEX_BL702_Delay_MS] = (uint32_t)BL702_Delay_MS,
+    [ROM_API_INDEX_BL702_MemCpy] = (uint32_t)BL702_MemCpy,
+    [ROM_API_INDEX_BL702_MemCpy4] = (uint32_t)BL702_MemCpy4,
+    [ROM_API_INDEX_BL702_MemCpy_Fast] = (uint32_t)BL702_MemCpy_Fast,
+    [ROM_API_INDEX_ARCH_MemCpy_Fast] = (uint32_t)ARCH_MemCpy_Fast,
+    [ROM_API_INDEX_BL702_MemSet] = (uint32_t)BL702_MemSet,
+    [ROM_API_INDEX_BL702_MemSet4] = (uint32_t)BL702_MemSet4,
+    [ROM_API_INDEX_BL702_MemCmp] = (uint32_t)BL702_MemCmp,
+    [ROM_API_INDEX_BFLB_Soft_CRC32] = (uint32_t)BFLB_Soft_CRC32,
+
+    [ROM_API_INDEX_GLB_Get_Root_CLK_Sel] = (uint32_t)GLB_Get_Root_CLK_Sel,
+    [ROM_API_INDEX_GLB_Set_System_CLK_Div] = (uint32_t)GLB_Set_System_CLK_Div,
+    [ROM_API_INDEX_GLB_Get_BCLK_Div] = (uint32_t)GLB_Get_BCLK_Div,
+    [ROM_API_INDEX_GLB_Get_HCLK_Div] = (uint32_t)GLB_Get_HCLK_Div,
+    [ROM_API_INDEX_Update_SystemCoreClockWith_XTAL] = (uint32_t)Update_SystemCoreClockWith_XTAL,
+    [ROM_API_INDEX_GLB_Set_System_CLK] = (uint32_t)GLB_Set_System_CLK,
+    [ROM_API_INDEX_System_Core_Clock_Update_From_RC32M] = (uint32_t)System_Core_Clock_Update_From_RC32M,
+    [ROM_API_INDEX_GLB_Set_SF_CLK] = (uint32_t)GLB_Set_SF_CLK,
+    [ROM_API_INDEX_GLB_Power_Off_DLL] = (uint32_t)GLB_Power_Off_DLL,
+    [ROM_API_INDEX_GLB_Power_On_DLL] = (uint32_t)GLB_Power_On_DLL,
+    [ROM_API_INDEX_GLB_Enable_DLL_All_Clks] = (uint32_t)GLB_Enable_DLL_All_Clks,
+    [ROM_API_INDEX_GLB_Enable_DLL_Clk] = (uint32_t)GLB_Enable_DLL_Clk,
+    [ROM_API_INDEX_GLB_Disable_DLL_All_Clks] = (uint32_t)GLB_Disable_DLL_All_Clks,
+    [ROM_API_INDEX_GLB_Disable_DLL_Clk] = (uint32_t)GLB_Disable_DLL_Clk,
+    [ROM_API_INDEX_GLB_SW_System_Reset] = (uint32_t)GLB_SW_System_Reset,
+    [ROM_API_INDEX_GLB_SW_CPU_Reset] = (uint32_t)GLB_SW_CPU_Reset,
+    [ROM_API_INDEX_GLB_SW_POR_Reset] = (uint32_t)GLB_SW_POR_Reset,
+    [ROM_API_INDEX_GLB_Select_Internal_Flash] = (uint32_t)GLB_Select_Internal_Flash,
+    [ROM_API_INDEX_GLB_Swap_Flash_Pin] = (uint32_t)GLB_Swap_Flash_Pin,
+    [ROM_API_INDEX_GLB_Swap_Flash_CS_IO2_Pin] = (uint32_t)GLB_Swap_Flash_CS_IO2_Pin,
+    [ROM_API_INDEX_GLB_Swap_Flash_IO0_IO3_Pin] = (uint32_t)GLB_Swap_Flash_IO0_IO3_Pin,
+    [ROM_API_INDEX_GLB_Select_Internal_PSram] = (uint32_t)GLB_Select_Internal_PSram,
+    [ROM_API_INDEX_GLB_GPIO_Init] = (uint32_t)GLB_GPIO_Init,
+    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Enable] = (uint32_t)GLB_GPIO_OUTPUT_Enable,
+    [ROM_API_INDEX_GLB_GPIO_OUTPUT_Disable] = (uint32_t)GLB_GPIO_OUTPUT_Disable,
+    [ROM_API_INDEX_GLB_GPIO_Set_HZ] = (uint32_t)GLB_GPIO_Set_HZ,
+    [ROM_API_INDEX_GLB_Deswap_Flash_Pin] = (uint32_t)GLB_Deswap_Flash_Pin,
+    [ROM_API_INDEX_GLB_Select_External_Flash] = (uint32_t)GLB_Select_External_Flash,
+    [ROM_API_INDEX_GLB_GPIO_Get_Fun] = (uint32_t)GLB_GPIO_Get_Fun,
+
+    [ROM_API_INDEX_EF_Ctrl_Busy] = (uint32_t)EF_Ctrl_Busy,
+    [ROM_API_INDEX_EF_Ctrl_Sw_AHB_Clk_0] = (uint32_t)EF_Ctrl_Sw_AHB_Clk_0,
+    [ROM_API_INDEX_EF_Ctrl_Load_Efuse_R0] = (uint32_t)EF_Ctrl_Load_Efuse_R0,
+    [ROM_API_INDEX_EF_Ctrl_Clear] = (uint32_t)EF_Ctrl_Clear,
+    [ROM_API_INDEX_EF_Ctrl_Get_Trim_Parity] = (uint32_t)EF_Ctrl_Get_Trim_Parity,
+    [ROM_API_INDEX_EF_Ctrl_Read_RC32K_Trim] = (uint32_t)EF_Ctrl_Read_RC32K_Trim,
+    [ROM_API_INDEX_EF_Ctrl_Read_RC32M_Trim] = (uint32_t)EF_Ctrl_Read_RC32M_Trim,
+
+    [ROM_API_INDEX_PDS_Trim_RC32M] = (uint32_t)PDS_Trim_RC32M,
+    [ROM_API_INDEX_PDS_Select_RC32M_As_PLL_Ref] = (uint32_t)PDS_Select_RC32M_As_PLL_Ref,
+    [ROM_API_INDEX_PDS_Select_XTAL_As_PLL_Ref] = (uint32_t)PDS_Select_XTAL_As_PLL_Ref,
+    [ROM_API_INDEX_PDS_Power_On_PLL] = (uint32_t)PDS_Power_On_PLL,
+    [ROM_API_INDEX_PDS_Enable_PLL_All_Clks] = (uint32_t)PDS_Enable_PLL_All_Clks,
+    [ROM_API_INDEX_PDS_Disable_PLL_All_Clks] = (uint32_t)PDS_Disable_PLL_All_Clks,
+    [ROM_API_INDEX_PDS_Enable_PLL_Clk] = (uint32_t)PDS_Enable_PLL_Clk,
+    [ROM_API_INDEX_PDS_Disable_PLL_Clk] = (uint32_t)PDS_Disable_PLL_Clk,
+    [ROM_API_INDEX_PDS_Power_Off_PLL] = (uint32_t)PDS_Power_Off_PLL,
+    [ROM_API_INDEX_PDS_Reset] = (uint32_t)PDS_Reset,
+    [ROM_API_INDEX_PDS_Enable] = (uint32_t)PDS_Enable,
+    [ROM_API_INDEX_PDS_Auto_Time_Config] = (uint32_t)PDS_Auto_Time_Config,
+    [ROM_API_INDEX_PDS_Auto_Enable] = (uint32_t)PDS_Auto_Enable,
+    [ROM_API_INDEX_PDS_Manual_Force_Turn_Off] = (uint32_t)PDS_Manual_Force_Turn_Off,
+    [ROM_API_INDEX_PDS_Manual_Force_Turn_On] = (uint32_t)PDS_Manual_Force_Turn_On,
+
+    [ROM_API_INDEX_HBN_Enable] = (uint32_t)HBN_Enable,
+    [ROM_API_INDEX_HBN_Reset] = (uint32_t)HBN_Reset,
+    [ROM_API_INDEX_HBN_GPIO_Dbg_Pull_Cfg] = (uint32_t)HBN_GPIO_Dbg_Pull_Cfg,
+    [ROM_API_INDEX_HBN_Trim_RC32K] = (uint32_t)HBN_Trim_RC32K,
+    [ROM_API_INDEX_HBN_Set_ROOT_CLK_Sel] = (uint32_t)HBN_Set_ROOT_CLK_Sel,
+
+    [ROM_API_INDEX_XIP_SFlash_State_Save] = (uint32_t)XIP_SFlash_State_Save,
+    [ROM_API_INDEX_XIP_SFlash_State_Restore] = (uint32_t)XIP_SFlash_State_Restore,
+    [ROM_API_INDEX_XIP_SFlash_Erase_Need_Lock] = (uint32_t)XIP_SFlash_Erase_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Write_Need_Lock] = (uint32_t)XIP_SFlash_Write_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_Need_Lock] = (uint32_t)XIP_SFlash_Read_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetJedecId_Need_Lock] = (uint32_t)XIP_SFlash_GetJedecId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetDeviceId_Need_Lock] = (uint32_t)XIP_SFlash_GetDeviceId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_GetUniqueId_Need_Lock] = (uint32_t)XIP_SFlash_GetUniqueId_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_Via_Cache_Need_Lock] = (uint32_t)XIP_SFlash_Read_Via_Cache_Need_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Read_With_Lock] = (uint32_t)XIP_SFlash_Read_With_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Write_With_Lock] = (uint32_t)XIP_SFlash_Write_With_Lock,
+    [ROM_API_INDEX_XIP_SFlash_Erase_With_Lock] = (uint32_t)XIP_SFlash_Erase_With_Lock,
+
+    [ROM_API_INDEX_SFlash_Init] = (uint32_t)SFlash_Init,
+    [ROM_API_INDEX_SFlash_SetSPIMode] = (uint32_t)SFlash_SetSPIMode,
+    [ROM_API_INDEX_SFlash_Read_Reg] = (uint32_t)SFlash_Read_Reg,
+    [ROM_API_INDEX_SFlash_Write_Reg] = (uint32_t)SFlash_Write_Reg,
+    [ROM_API_INDEX_SFlash_Read_Reg_With_Cmd] = (uint32_t)SFlash_Read_Reg_With_Cmd,
+    [ROM_API_INDEX_SFlash_Write_Reg_With_Cmd] = (uint32_t)SFlash_Write_Reg_With_Cmd,
+    [ROM_API_INDEX_SFlash_Busy] = (uint32_t)SFlash_Busy,
+    [ROM_API_INDEX_SFlash_Write_Enable] = (uint32_t)SFlash_Write_Enable,
+    [ROM_API_INDEX_SFlash_Qspi_Enable] = (uint32_t)SFlash_Qspi_Enable,
+    [ROM_API_INDEX_SFlash_Volatile_Reg_Write_Enable] = (uint32_t)SFlash_Volatile_Reg_Write_Enable,
+    [ROM_API_INDEX_SFlash_Chip_Erase] = (uint32_t)SFlash_Chip_Erase,
+    [ROM_API_INDEX_SFlash_Sector_Erase] = (uint32_t)SFlash_Sector_Erase,
+    [ROM_API_INDEX_SFlash_Blk32_Erase] = (uint32_t)SFlash_Blk32_Erase,
+    [ROM_API_INDEX_SFlash_Blk64_Erase] = (uint32_t)SFlash_Blk64_Erase,
+    [ROM_API_INDEX_SFlash_Erase] = (uint32_t)SFlash_Erase,
+    [ROM_API_INDEX_SFlash_Program] = (uint32_t)SFlash_Program,
+    [ROM_API_INDEX_SFlash_GetUniqueId] = (uint32_t)SFlash_GetUniqueId,
+    [ROM_API_INDEX_SFlash_GetJedecId] = (uint32_t)SFlash_GetJedecId,
+    [ROM_API_INDEX_SFlash_GetDeviceId] = (uint32_t)SFlash_GetDeviceId,
+    [ROM_API_INDEX_SFlash_Powerdown] = (uint32_t)SFlash_Powerdown,
+    [ROM_API_INDEX_SFlash_Releae_Powerdown] = (uint32_t)SFlash_Releae_Powerdown,
+    [ROM_API_INDEX_SFlash_Restore_From_Powerdown] = (uint32_t)SFlash_Restore_From_Powerdown,
+    [ROM_API_INDEX_SFlash_SetBurstWrap] = (uint32_t)SFlash_SetBurstWrap,
+    [ROM_API_INDEX_SFlash_DisableBurstWrap] = (uint32_t)SFlash_DisableBurstWrap,
+    [ROM_API_INDEX_SFlash_Software_Reset] = (uint32_t)SFlash_Software_Reset,
+    [ROM_API_INDEX_SFlash_Reset_Continue_Read] = (uint32_t)SFlash_Reset_Continue_Read,
+    [ROM_API_INDEX_SFlash_Set_IDbus_Cfg] = (uint32_t)SFlash_Set_IDbus_Cfg,
+    [ROM_API_INDEX_SFlash_IDbus_Read_Enable] = (uint32_t)SFlash_IDbus_Read_Enable,
+    [ROM_API_INDEX_SFlash_Cache_Read_Enable] = (uint32_t)SFlash_Cache_Read_Enable,
+    [ROM_API_INDEX_SFlash_Cache_Read_Disable] = (uint32_t)SFlash_Cache_Read_Disable,
+    [ROM_API_INDEX_SFlash_Read] = (uint32_t)SFlash_Read,
+
+    [ROM_API_INDEX_L1C_Cache_Enable_Set] = (uint32_t)L1C_Cache_Enable_Set,
+    [ROM_API_INDEX_L1C_Cache_Write_Set] = (uint32_t)L1C_Cache_Write_Set,
+    [ROM_API_INDEX_L1C_Cache_Flush] = (uint32_t)L1C_Cache_Flush,
+    [ROM_API_INDEX_L1C_Cache_Hit_Count_Get] = (uint32_t)L1C_Cache_Hit_Count_Get,
+    [ROM_API_INDEX_L1C_Cache_Miss_Count_Get] = (uint32_t)L1C_Cache_Miss_Count_Get,
+    [ROM_API_INDEX_L1C_Cache_Read_Disable] = (uint32_t)L1C_Cache_Read_Disable,
+    [ROM_API_INDEX_L1C_Set_Wrap] = (uint32_t)L1C_Set_Wrap,
+    [ROM_API_INDEX_L1C_Set_Way_Disable] = (uint32_t)L1C_Set_Way_Disable,
+    [ROM_API_INDEX_L1C_IROM_2T_Access_Set] = (uint32_t)L1C_IROM_2T_Access_Set,
+
+    [ROM_API_INDEX_SF_Ctrl_Enable] = (uint32_t)SF_Ctrl_Enable,
+    [ROM_API_INDEX_SF_Ctrl_Psram_Init] = (uint32_t)SF_Ctrl_Psram_Init,
+    [ROM_API_INDEX_SF_Ctrl_Get_Clock_Delay] = (uint32_t)SF_Ctrl_Get_Clock_Delay,
+    [ROM_API_INDEX_SF_Ctrl_Set_Clock_Delay] = (uint32_t)SF_Ctrl_Set_Clock_Delay,
+    [ROM_API_INDEX_SF_Ctrl_Cmds_Set] = (uint32_t)SF_Ctrl_Cmds_Set,
+    [ROM_API_INDEX_SF_Ctrl_Set_Owner] = (uint32_t)SF_Ctrl_Set_Owner,
+    [ROM_API_INDEX_SF_Ctrl_Disable] = (uint32_t)SF_Ctrl_Disable,
+    [ROM_API_INDEX_SF_Ctrl_Select_Pad] = (uint32_t)SF_Ctrl_Select_Pad,
+    [ROM_API_INDEX_SF_Ctrl_Select_Bank] = (uint32_t)SF_Ctrl_Select_Bank,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable_BE] = (uint32_t)SF_Ctrl_AES_Enable_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable_LE] = (uint32_t)SF_Ctrl_AES_Enable_LE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Region] = (uint32_t)SF_Ctrl_AES_Set_Region,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key] = (uint32_t)SF_Ctrl_AES_Set_Key,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_Key_BE] = (uint32_t)SF_Ctrl_AES_Set_Key_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV] = (uint32_t)SF_Ctrl_AES_Set_IV,
+    [ROM_API_INDEX_SF_Ctrl_AES_Set_IV_BE] = (uint32_t)SF_Ctrl_AES_Set_IV_BE,
+    [ROM_API_INDEX_SF_Ctrl_AES_Enable] = (uint32_t)SF_Ctrl_AES_Enable,
+    [ROM_API_INDEX_SF_Ctrl_AES_Disable] = (uint32_t)SF_Ctrl_AES_Disable,
+    [ROM_API_INDEX_SF_Ctrl_Is_AES_Enable] = (uint32_t)SF_Ctrl_Is_AES_Enable,
+    [ROM_API_INDEX_SF_Ctrl_Set_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Set_Flash_Image_Offset,
+    [ROM_API_INDEX_SF_Ctrl_Get_Flash_Image_Offset] = (uint32_t)SF_Ctrl_Get_Flash_Image_Offset,
+    [ROM_API_INDEX_SF_Ctrl_Select_Clock] = (uint32_t)SF_Ctrl_Select_Clock,
+    [ROM_API_INDEX_SF_Ctrl_SendCmd] = (uint32_t)SF_Ctrl_SendCmd,
+    [ROM_API_INDEX_SF_Ctrl_Flash_Read_Icache_Set] = (uint32_t)SF_Ctrl_Flash_Read_Icache_Set,
+    [ROM_API_INDEX_SF_Ctrl_Psram_Write_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Write_Icache_Set,
+    [ROM_API_INDEX_SF_Ctrl_Psram_Read_Icache_Set] = (uint32_t)SF_Ctrl_Psram_Read_Icache_Set,
+    [ROM_API_INDEX_SF_Ctrl_GetBusyState] = (uint32_t)SF_Ctrl_GetBusyState,
+    [ROM_API_INDEX_SF_Cfg_Deinit_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Deinit_Ext_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Init_Ext_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Ext_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Get_Flash_Cfg_Need_Lock] = (uint32_t)SF_Cfg_Get_Flash_Cfg_Need_Lock,
+    [ROM_API_INDEX_SF_Cfg_Init_Flash_Gpio] = (uint32_t)SF_Cfg_Init_Flash_Gpio,
+    [ROM_API_INDEX_SF_Cfg_Flash_Identify] = (uint32_t)SF_Cfg_Flash_Identify,
+
+    [ROM_API_INDEX_Psram_Init] = (uint32_t)Psram_Init,
+    [ROM_API_INDEX_Psram_ReadReg] = (uint32_t)Psram_ReadReg,
+    [ROM_API_INDEX_Psram_WriteReg] = (uint32_t)Psram_WriteReg,
+    [ROM_API_INDEX_Psram_SetDriveStrength] = (uint32_t)Psram_SetDriveStrength,
+    [ROM_API_INDEX_Psram_SetBurstWrap] = (uint32_t)Psram_SetBurstWrap,
+    [ROM_API_INDEX_Psram_ReadId] = (uint32_t)Psram_ReadId,
+    [ROM_API_INDEX_Psram_EnterQuadMode] = (uint32_t)Psram_EnterQuadMode,
+    [ROM_API_INDEX_Psram_ExitQuadMode] = (uint32_t)Psram_ExitQuadMode,
+    [ROM_API_INDEX_Psram_ToggleBurstLength] = (uint32_t)Psram_ToggleBurstLength,
+    [ROM_API_INDEX_Psram_SoftwareReset] = (uint32_t)Psram_SoftwareReset,
+    [ROM_API_INDEX_Psram_Set_IDbus_Cfg] = (uint32_t)Psram_Set_IDbus_Cfg,
+    [ROM_API_INDEX_Psram_Cache_Write_Set] = (uint32_t)Psram_Cache_Write_Set,
+    [ROM_API_INDEX_Psram_Write] = (uint32_t)Psram_Write,
+    [ROM_API_INDEX_Psram_Read] = (uint32_t)Psram_Read,
+
+    [ROM_API_INDEX_FUNC_INVALID_START... ROM_API_INDEX_FUNC_LAST_ENTRY] = 0xdeedbeef,
+};
+
+/*@} end of group ROMDRIVER_Private_Type*/
+
+/** @defgroup ROMDRIVER_Private_Defines
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Defines */
+
+/** @defgroup ROMDRIVER_Private_Variables
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Variables */
+
+/** @defgroup ROMDRIVER_Global_Variables
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Global_Variables */
+
+/** @defgroup ROMDRIVER_Private_FunctionDeclaration
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_FunctionDeclaration */
+
+/** @defgroup ROMDRIVER_Private_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Private_Functions */
+
+/** @defgroup ROMDRIVER_Public_Functions
+ *  @{
+ */
+
+/*@} end of group ROMDRIVER_Public_Functions */
+
+/*@} end of group ROMDRIVER_COMMON */
+
+/*@} end of group BL702_Periph_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c
new file mode 100755
index 0000000000..79404c3e5c
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sf_cfg_ext.c
@@ -0,0 +1,710 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sf_cfg_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_glb.h"
+#include "bflb_sf_cfg.h"
+#include "bl702_sf_cfg_ext.h"
+#include "bflb_xip_sflash.h"
+#include "bl702_romdriver.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SF_CFG_EXT
+ *  @{
+ */
+
+/** @defgroup  SF_CFG_EXT_Private_Macros
+ *  @{
+ */
+#define BFLB_FLASH_CFG_MAGIC "FCFG"
+
+/*@} end of group SF_CFG_EXT_Private_Macros */
+
+/** @defgroup  SF_CFG_EXT_Private_Types
+ *  @{
+ */
+typedef struct
+{
+    uint32_t jedec_id;
+    char *name;
+    const spi_flash_cfg_type *cfg;
+} flash_info_t;
+
+/*@} end of group SF_CFG_EXT_Private_Types */
+
+/** @defgroup  SF_CFG_EXT_Private_Variables
+ *  @{
+ */
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_gd_md_40d = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0x51,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0xA0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = 0x11,
+    .clk_delay = 1,
+    .clk_invert = 0x3f,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 20 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_mx_kh25 = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc2,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x00,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x00,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 0,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = 0x11,
+    .clk_delay = 1,
+    .clk_invert = 0x01,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_fm_q80 = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xc8,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x02,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x01,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0xA0,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x01,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1200,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION spi_flash_cfg_type flashcfg_winb_16jv = {
+    .reset_c_read_cmd = 0xff,
+    .reset_c_read_cmd_size = 3,
+    .mid = 0xef,
+
+    .de_burst_wrap_cmd = 0x77,
+    .de_burst_wrap_cmd_dmy_clk = 0x3,
+    .de_burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .de_burst_wrap_data = 0xF0,
+
+    /*reg*/
+    .write_enable_cmd = 0x06,
+    .wr_enable_index = 0x00,
+    .wr_enable_bit = 0x01,
+    .wr_enable_read_reg_len = 0x01,
+
+    .qe_index = 1,
+    .qe_bit = 0x01,
+    .qe_write_reg_len = 0x01,
+    .qe_read_reg_len = 0x1,
+
+    .busy_index = 0,
+    .busy_bit = 0x00,
+    .busy_read_reg_len = 0x1,
+    .release_powerdown = 0xab,
+
+    .read_reg_cmd[0] = 0x05,
+    .read_reg_cmd[1] = 0x35,
+    .write_reg_cmd[0] = 0x01,
+    .write_reg_cmd[1] = 0x31,
+
+    .fast_read_qio_cmd = 0xeb,
+    .fr_qio_dmy_clk = 16 / 8,
+    .c_read_support = 1,
+    .c_read_mode = 0x20,
+
+    .burst_wrap_cmd = 0x77,
+    .burst_wrap_cmd_dmy_clk = 0x3,
+    .burst_wrap_data_mode = SF_CTRL_DATA_4_LINES,
+    .burst_wrap_data = 0x40,
+    /*erase*/
+    .chip_erase_cmd = 0xc7,
+    .sector_erase_cmd = 0x20,
+    .blk32_erase_cmd = 0x52,
+    .blk64_erase_cmd = 0xd8,
+    /*write*/
+    .page_program_cmd = 0x02,
+    .qpage_program_cmd = 0x32,
+    .qpp_addr_mode = SF_CTRL_ADDR_1_LINE,
+
+    .io_mode = SF_CTRL_QIO_MODE,
+    .clk_delay = 1,
+    .clk_invert = 0x01,
+
+    .reset_en_cmd = 0x66,
+    .reset_cmd = 0x99,
+    .c_rexit = 0xff,
+    .wr_enable_write_reg_len = 0x00,
+
+    /*id*/
+    .jedec_id_cmd = 0x9f,
+    .jedec_id_cmd_dmy_clk = 0,
+    .qpi_jedec_id_cmd = 0x9f,
+    .qpi_jedec_id_cmd_dmy_clk = 0x00,
+    .sector_size = 4,
+    .page_size = 256,
+
+    /*read*/
+    .fast_read_cmd = 0x0b,
+    .fr_dmy_clk = 8 / 8,
+    .qpi_fast_read_cmd = 0x0b,
+    .qpi_fr_dmy_clk = 8 / 8,
+    .fast_read_do_cmd = 0x3b,
+    .fr_do_dmy_clk = 8 / 8,
+    .fast_read_dio_cmd = 0xbb,
+    .fr_dio_dmy_clk = 0,
+    .fast_read_qo_cmd = 0x6b,
+    .fr_qo_dmy_clk = 8 / 8,
+
+    .qpi_fast_read_qio_cmd = 0xeb,
+    .qpi_fr_qio_dmy_clk = 16 / 8,
+    .qpi_page_program_cmd = 0x02,
+    .write_vreg_enable_cmd = 0x50,
+
+    /* qpi mode */
+    .enter_qpi = 0x38,
+    .exit_qpi = 0xff,
+
+    /*AC*/
+    .time_e_sector = 300,
+    .time_e_32k = 1600,
+    .time_e_64k = 1200,
+    .time_page_pgm = 5,
+    .time_ce = 33 * 1000,
+    .pd_delay = 20,
+    .qe_data = 0,
+};
+
+static const ATTR_TCM_CONST_SECTION flash_info_t flash_infos[] = {
+    {
+        .jedec_id = 0x134051,
+        .name = "GD_MD04D_04_33",
+        .cfg = &flashcfg_gd_md_40d,
+    },
+    {
+        .jedec_id = 0x1320c2,
+        .name = "MX_KH40_04_33",
+        .cfg = &flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x1420c2,
+        .name = "MX_KH80_08_33",
+        .cfg = &flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x1520c2,
+        .name = "MX_KH16_16_33",
+        .cfg = &flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x1440A1,
+        .name = "FM_25Q80_80_33",
+        .cfg = &flashcfg_fm_q80,
+    },
+    {
+        .jedec_id = 0x1570EF,
+        .name = "Winb_16JV_16_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x1870EF,
+        .name = "Winb_128JV_128_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x15605E,
+        .name = "ZB_VQ16_16_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x144020,
+        .name = "XM_25QH80_80_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x154020,
+        .name = "XM_25QH16_16_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x164020,
+        .name = "XM_25QH32_32_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x174020,
+        .name = "XM_25QH64_64_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x13325E,
+        .name = "ZB_D40B_80_33",
+        .cfg = &flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x14325E,
+        .name = "ZB_D80B_80_33",
+        .cfg = &flashcfg_mx_kh25,
+    },
+    {
+        .jedec_id = 0x15405E,
+        .name = "ZB_25Q16B_15_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x16405E,
+        .name = "ZB_25Q32B_16_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+    {
+        .jedec_id = 0x1560EB,
+        .name = "TH_25Q16HB_16_33",
+        .cfg = &flashcfg_fm_q80,
+    },
+    {
+        .jedec_id = 0x15345E,
+        .name = "ZB_25Q16A_15_33",
+        .cfg = &flashcfg_winb_16jv,
+    },
+};
+
+/*@} end of group SF_CFG_EXT_Private_Variables */
+
+/** @defgroup  SF_CFG_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Global_Variables */
+
+/** @defgroup  SF_CFG_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SF_CFG_EXT_Private_Fun_Declaration */
+
+/** @defgroup  SF_CFG_EXT_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  Init internal flash GPIO
+ *
+ * @param  None
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_sf_cfg_Init_Internal_Flash_Gpio(void)
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_0,
+        .gpioFun = GPIO_FUN_GPIO,
+        .gpioMode = GPIO_MODE_INPUT,
+        .pullType = GPIO_PULL_NONE,
+        .drive = 0,
+        .smtCtrl = 1,
+    };
+
+    /* Turn on Flash pad, GPIO23 - GPIO28 */
+    for (uint32_t pin = 23; pin < 29; pin++) {
+        gpioCfg.gpioPin = pin;
+
+        if (pin == 25) {
+            gpioCfg.pullType = GPIO_PULL_DOWN;
+        } else {
+            gpioCfg.pullType = GPIO_PULL_NONE;
+        }
+
+        GLB_GPIO_Init(&gpioCfg);
+    }
+}
+
+/****************************************************************************/ /**
+ * @brief  Get flash config according to flash ID
+ *
+ * @param  flash_id: Flash ID
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sf_cfg_get_flash_cfg_need_lock_ext(uint32_t flash_id, spi_flash_cfg_type *p_flash_cfg,
+                                                             uint8_t group, uint8_t bank)
+{
+    uint32_t i;
+    uint8_t buf[sizeof(spi_flash_cfg_type) + 8];
+    uint32_t crc, *pCrc;
+    char flash_cfg_magic[] = "FCFG";
+
+    if (flash_id == 0) {
+        bflb_xip_sflash_read_via_cache_need_lock(8 + BL702_FLASH_XIP_BASE, buf, sizeof(spi_flash_cfg_type) + 8, group, bank);
+
+        if (BL702_MemCmp(buf, flash_cfg_magic, 4) == 0) {
+            crc = BFLB_Soft_CRC32((uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+            pCrc = (uint32_t *)(buf + 4 + sizeof(spi_flash_cfg_type));
+
+            if (*pCrc == crc) {
+                BL702_MemCpy_Fast(p_flash_cfg, (uint8_t *)buf + 4, sizeof(spi_flash_cfg_type));
+                return SUCCESS;
+            }
+        }
+    } else {
+        if (bflb_sf_cfg_get_flash_cfg_need_lock(flash_id, p_flash_cfg, group, bank) == SUCCESS) {
+            /* 0x134051 flash cfg is wrong in rom, find again */
+            if ((flash_id&0xFFFFFF) != 0x134051) {
+                return SUCCESS;
+            }
+        }
+
+        for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+            if (flash_infos[i].jedec_id == flash_id) {
+                BL702_MemCpy_Fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+                return SUCCESS;
+            }
+        }
+    }
+
+    return ERROR;
+}
+
+/****************************************************************************/ /**
+ * @brief  Identify one flash
+ *
+ * @param  call_from_flash: code run at flash or ram
+ * @param  auto_scan: Auto scan all GPIO pin
+ * @param  flash_pin_cfg: Specify flash GPIO config, not auto scan
+ * @param  restore_default: Wether restore default flash GPIO config
+ * @param  p_flash_cfg: Flash config pointer
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return Flash ID
+ *
+*******************************************************************************/
+uint32_t ATTR_TCM_SECTION bflb_sf_cfg_flash_identify_ext(uint8_t call_from_flash, uint8_t flash_pin_cfg,
+                  uint8_t restore_default, spi_flash_cfg_type *p_flash_cfg, uint8_t group, uint8_t bank)
+{
+    uint32_t jedec_id = 0;
+    uint32_t i = 0;
+    uint32_t ret = 0;
+
+    ret = bflb_sf_cfg_flash_identify(call_from_flash, flash_pin_cfg, restore_default, p_flash_cfg, group, bank);
+
+    if ((ret & BFLB_FLASH_ID_VALID_FLAG) != 0) {
+        /* 0x134051 flash cfg is wrong in rom, find again */
+        if ((ret&0xFFFFFF) != 0x134051) {
+            return ret;
+        }
+    }
+
+    jedec_id = (ret & 0xffffff);
+
+    for (i = 0; i < sizeof(flash_infos) / sizeof(flash_infos[0]); i++) {
+        if (flash_infos[i].jedec_id == jedec_id) {
+            BL702_MemCpy_Fast(p_flash_cfg, flash_infos[i].cfg, sizeof(spi_flash_cfg_type));
+            break;
+        }
+    }
+
+    if (i == sizeof(flash_infos) / sizeof(flash_infos[0])) {
+        return jedec_id;
+    } else {
+        return (jedec_id | BFLB_FLASH_ID_VALID_FLAG);
+    }
+}
+
+/*@} end of group SF_CFG_EXT_Public_Functions */
+
+/*@} end of group SF_CFG_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sflash_ext.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sflash_ext.c
new file mode 100755
index 0000000000..b38c579fd3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_sflash_ext.c
@@ -0,0 +1,274 @@
+/**
+  ******************************************************************************
+  * @file    bl702_sflash_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2019 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bflb_sf_ctrl.h"
+#include "bl702_sflash_ext.h"
+#include "l1c_reg.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  SFLASH_EXT
+ *  @{
+ */
+
+/** @defgroup  SFLASH_EXT_Private_Macros
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Macros */
+
+/** @defgroup  SFLASH_EXT_Private_Types
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Types */
+
+/** @defgroup  SFLASH_EXT_Private_Variables
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Variables */
+
+/** @defgroup  SFLASH_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Global_Variables */
+
+/** @defgroup  SFLASH_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Fun_Declaration */
+
+/** @defgroup  SFLASH_EXT_Private_Functions
+ *  @{
+ */
+
+/*@} end of group SFLASH_EXT_Private_Functions */
+
+/** @defgroup  SFLASH_EXT_Public_Functions
+ *  @{
+ */
+
+/****************************************************************************/ /**
+ * @brief  KH25V40 flash write protect set
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  protect: protect area
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_kh25v40_write_protect(spi_flash_cfg_type *flash_cfg, uint8_t protect)
+{
+    uint32_t stat = 0, ret;
+
+    bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1);
+    if (((stat >> 2) & 0xf) == protect) {
+        return 0;
+    }
+
+    stat |= ((protect << 2) & 0xff);
+
+    ret = bflb_sflash_write_enable(flash_cfg);
+    if (0 != ret) {
+        return -1;
+    }
+
+    bflb_sflash_write_reg(flash_cfg, 0, (uint8_t *)&stat, 1);
+    bflb_sflash_read_reg(flash_cfg, 0, (uint8_t *)&stat, 1);
+    if (((stat >> 2) & 0xf) == protect) {
+        return 0;
+    }
+
+    return -1;
+}
+
+/****************************************************************************/ /**
+ * @brief  Read flash register with read command
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  read_reg_cmd: read command
+ * @param  reg_value: register value pointer to store data
+ * @param  reg_len: register value length
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_read_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+    uint32_t cnt = 0;
+
+    if (((uint32_t)&flash_cmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        BL702_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    flash_cmd.cmd_buf[0] = read_reg_cmd << 24;
+    flash_cmd.rw_flag = SF_CTRL_READ;
+    flash_cmd.nb_data = reg_len;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    while (SET == bflb_sf_ctrl_get_busy_state()) {
+        BL702_Delay_US(1);
+        cnt++;
+
+        if (cnt > 1000) {
+            return -1;
+        }
+    }
+
+    BL702_MemCpy(reg_value, flash_ctrl_buf, reg_len);
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Write flash register with write command
+ *
+ * @param  flash_cfg: Serial flash parameter configuration pointer
+ * @param  read_reg_cmd: write command
+ * @param  reg_value: register value pointer storing data
+ * @param  reg_len: register value length
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_sflash_write_reg_with_cmd(spi_flash_cfg_type *flash_cfg, uint8_t read_reg_cmd, uint8_t *reg_value, uint8_t reg_len)
+{
+    uint8_t *const flash_ctrl_buf = (uint8_t *)SF_CTRL_BUF_BASE;
+    uint32_t cnt = 0;
+    struct sf_ctrl_cmd_cfg_type flash_cmd;
+
+    if (((uint32_t)&flash_cmd) % 4 == 0) {
+        BL702_MemSet4((uint32_t *)&flash_cmd, 0, sizeof(flash_cmd) / 4);
+    } else {
+        BL702_MemSet(&flash_cmd, 0, sizeof(flash_cmd));
+    }
+
+    BL702_MemCpy(flash_ctrl_buf, reg_value, reg_len);
+
+    flash_cmd.cmd_buf[0] = read_reg_cmd << 24;
+    flash_cmd.rw_flag = SF_CTRL_WRITE;
+    flash_cmd.nb_data = reg_len;
+
+    bflb_sf_ctrl_sendcmd(&flash_cmd);
+
+    /* take 40ms for tw(write status register) as default */
+    while (SET == bflb_sflash_busy(flash_cfg)) {
+        BL702_Delay_US(100);
+        cnt++;
+
+        if (cnt > 400) {
+            return -1;
+        }
+    }
+
+    return 0;
+}
+
+/****************************************************************************//**
+ * @brief  Clear flash status register
+ *
+ * @param  p_flash_cfg: Flash configuration pointer
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int ATTR_TCM_SECTION bflb_sflash_clear_status_register(spi_flash_cfg_type *p_flash_cfg)
+{
+    uint32_t ret = 0;
+    uint32_t qe_value = 0;
+    uint32_t reg_value = 0;
+    uint32_t read_value = 0;
+    uint8_t readreg_value0 = 0;
+    uint8_t readreg_value1 = 0;
+
+    if((p_flash_cfg->io_mode&0xf)==SF_CTRL_QO_MODE || (p_flash_cfg->io_mode&0xf)==SF_CTRL_QIO_MODE){
+        qe_value = 1;
+    }
+
+    bflb_sflash_read_reg(p_flash_cfg, 0, (uint8_t *)&readreg_value0, 1);
+    bflb_sflash_read_reg(p_flash_cfg, 1, (uint8_t *)&readreg_value1, 1);
+    read_value = (readreg_value0|(readreg_value1<<8));
+    if ((read_value & (~((1<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit)) |
+                        (1<<(p_flash_cfg->busy_index*8+p_flash_cfg->busy_bit)) |
+                        (1<<(p_flash_cfg->wr_enable_index*8+p_flash_cfg->wr_enable_bit))))) == 0){
+        return 0;
+    }
+
+    ret = bflb_sflash_write_enable(p_flash_cfg);
+    if (0 != ret) {
+        return -1;
+    }
+    if (p_flash_cfg->qe_write_reg_len == 2) {
+        reg_value = (qe_value<<(p_flash_cfg->qe_index*8+p_flash_cfg->qe_bit));
+        bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 2);
+    } else {
+        if (p_flash_cfg->qe_index == 0) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(p_flash_cfg, 0, (uint8_t *)®_value, 1);
+        ret = bflb_sflash_write_enable(p_flash_cfg);
+        if (0 != ret) {
+            return -1;
+        }
+        if (p_flash_cfg->qe_index == 1) {
+            reg_value = (qe_value<qe_bit);
+        } else {
+            reg_value = 0;
+        }
+        bflb_sflash_write_reg(p_flash_cfg, 1, (uint8_t *)®_value, 1);
+    }
+    return 0;
+}
+
+/*@} end of group SFLASH_EXT_Public_Functions */
+
+/*@} end of group SFLASH_EXT */
+
+/*@} end of group BL702_Peripheral_Driver */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_snflash.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_snflash.c
new file mode 100755
index 0000000000..4489a6d1ca
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_snflash.c
@@ -0,0 +1,890 @@
+/**
+  ******************************************************************************
+  * @file    bl702_snflash.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_snflash.h"
+#include "bl702_psram.h"
+
+#define PSRAM_ADDR            (0x24000000)
+#define DISK_SECTOR_SIZE      (512)
+#define PSRAM_READ_ERITE_SIZE (256)
+
+static void Nandflash_Erase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum);
+static void Nandflash_PageReadToPsram(uint32_t addr, uint32_t len);
+static void ATTR_TCM_SECTION Nandflash_Psram_Write(uint8_t *buff, uint32_t len, uint32_t psramWriteOffsite);
+static void ATTR_TCM_SECTION Nandflash_Psram_Read(uint8_t *buff, uint32_t readLen, uint32_t psramReadOffsite);
+static void Nandflash_PageWriteToPsram(const uint8_t *buff, uint32_t addr, uint32_t len);
+static void Nandflash_PageProgramFromPsram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum);
+
+NANDFLASH_CFG_Type nfCfg = {
+    .spiNo = SPI_ID_0,
+    .spiCfg = {
+        DISABLE,                      /* Disable de-glitch function */
+        DISABLE,                      /* Disable master continuous transfer mode */
+        SPI_BYTE_INVERSE_BYTE0_FIRST, /* The byte 0 is sent first in SPI transfer */
+        SPI_BIT_INVERSE_MSB_FIRST,    /* MSB is sent first in SPI transfer */
+        SPI_CLK_PHASE_INVERSE_0,      /* SPI clock phase */
+        SPI_CLK_POLARITY_LOW,         /* SPI clock plarity */
+        SPI_FRAME_SIZE_8              /* SPI frame size 8-bit(also the valid width for each fifo entry) */
+    },
+    .clockCfg = {
+        1, /* Length of start condition */
+        1, /* Length of stop condition */
+        1, /* Length of data phase 0,affecting clock */
+        1, /* Length of data phase 1,affecting clock */
+        1  /* Length of interval between frame */
+    }
+};
+
+static void ATTR_TCM_SECTION Nandflash_Psram_Write(uint8_t *buff, uint32_t len, uint32_t psramWriteOffsite)
+{
+    uint32_t i = 0;
+    uint32_t psramStartAddr = PSRAM_ADDR + psramWriteOffsite;
+
+    for (i = 0; i < len / PSRAM_READ_ERITE_SIZE; i++) {
+        BL702_MemCpy_Fast((void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), buff, PSRAM_READ_ERITE_SIZE);
+        buff += PSRAM_READ_ERITE_SIZE;
+    }
+
+    /*if len is not an integral multiple of PSRAM_READ_ERITE_SIZE need memcpy once again*/
+    if (len % PSRAM_READ_ERITE_SIZE != 0) {
+        BL702_MemCpy_Fast((void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), buff, len % PSRAM_READ_ERITE_SIZE);
+        buff += (len % PSRAM_READ_ERITE_SIZE);
+    }
+}
+
+static void ATTR_TCM_SECTION Nandflash_Psram_Read(uint8_t *buff, uint32_t readLen, uint32_t psramReadOffsite)
+{
+    uint32_t i = 0;
+    uint32_t psramStartAddr = PSRAM_ADDR + psramReadOffsite;
+
+    for (i = 0; i < readLen / PSRAM_READ_ERITE_SIZE; i++) {
+        BL702_MemCpy_Fast(buff, (void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), PSRAM_READ_ERITE_SIZE);
+        buff += PSRAM_READ_ERITE_SIZE;
+    }
+
+    /*if len is not an integral multiple of PSRAM_READ_ERITE_SIZE need memcpy once again*/
+    if (readLen % PSRAM_READ_ERITE_SIZE != 0) {
+        BL702_MemCpy_Fast(buff, (void *)(psramStartAddr + i * PSRAM_READ_ERITE_SIZE), readLen % PSRAM_READ_ERITE_SIZE);
+    }
+}
+
+void ATTR_TCM_SECTION Nandflash_Psram_Cfg()
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_17,
+        .gpioFun = GPIO17_FUN_SF_IO_0_SF2_CS2,
+        .gpioMode = GPIO_MODE_OUTPUT,
+        .pullType = GPIO_PULL_UP,
+        .drive = 3,
+        .smtCtrl = 1,
+    };
+
+    SPI_Psram_Cfg_Type apMemory1604 = {
+        .readIdCmd = 0x9F,
+        .readIdDmyClk = 0,
+        .burstToggleCmd = 0xC0,
+        .resetEnableCmd = 0x66,
+        .resetCmd = 0x99,
+        .enterQuadModeCmd = 0x35,
+        .exitQuadModeCmd = 0xF5,
+        .readRegCmd = 0xB5,
+        .readRegDmyClk = 1,
+        .writeRegCmd = 0xB1,
+        .readCmd = 0x03,
+        .readDmyClk = 0,
+        .fReadCmd = 0x0B,
+        .fReadDmyClk = 1,
+        .fReadQuadCmd = 0xEB,
+        .fReadQuadDmyClk = 3,
+        .writeCmd = 0x02,
+        .quadWriteCmd = 0x38,
+        .pageSize = 512,
+        .ctrlMode = PSRAM_SPI_CTRL_MODE,
+        .driveStrength = PSRAM_DRIVE_STRENGTH_50_OHMS,
+        .burstLength = PSRAM_BURST_LENGTH_512_BYTES,
+    };
+
+    SF_Ctrl_Cmds_Cfg cmdsCfg = {
+        .cmdsEn = ENABLE,
+        .burstToggleEn = ENABLE,
+        .wrapModeEn = DISABLE,
+        .wrapLen = SF_CTRL_WRAP_LEN_512,
+    };
+
+    SF_Ctrl_Psram_Cfg sfCtrlPsramCfg = {
+        .owner = SF_CTRL_OWNER_SAHB,
+        .padSel = SF_CTRL_PAD_SEL_DUAL_CS_SF2,
+        .bankSel = SF_CTRL_SEL_PSRAM,
+        .psramRxClkInvertSrc = ENABLE,
+        .psramRxClkInvertSel = ENABLE,
+        .psramDelaySrc = ENABLE,
+        .psramClkDelay = 0,
+    };
+    uint8_t psramId[8] = { 0 };
+    uint32_t wt_en = 1;
+    uint32_t wb_en = 0;
+    uint32_t wa_en = 0;
+    uint32_t i = 0;
+
+    GLB_GPIO_Init(&gpioCfg);
+
+    Psram_Init(&apMemory1604, &cmdsCfg, &sfCtrlPsramCfg);
+    Psram_SoftwareReset(&apMemory1604, apMemory1604.ctrlMode);
+    Psram_ReadId(&apMemory1604, psramId);
+
+    Psram_Cache_Write_Set(&apMemory1604, SF_CTRL_QIO_MODE, wt_en, wb_en, wa_en);
+    L1C_Cache_Enable_Set(0x0f);
+}
+
+void Nandflash_Gpio_Init(GLB_GPIO_Type clk, GLB_GPIO_Type mosi, GLB_GPIO_Type miso)
+{
+    GLB_GPIO_Cfg_Type gpioCfg = {
+        .gpioPin = GLB_GPIO_PIN_0,
+        .gpioFun = GPIO_FUN_SPI0,
+        .gpioMode = GPIO_MODE_OUTPUT,
+        .pullType = GPIO_PULL_NONE,
+        .drive = 0,
+        .smtCtrl = 1
+    };
+
+    /* cs */
+    gpioCfg.gpioPin = SPI_PIN_CS;
+    gpioCfg.gpioFun = 11;
+    GLB_GPIO_Init(&gpioCfg);
+    GLB_GPIO_INPUT_Disable(gpioCfg.gpioPin);
+    GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin);
+    Nandflash_CS_High();
+
+    /* clk */
+    gpioCfg.gpioPin = clk;
+    gpioCfg.gpioFun = GPIO_FUN_SPI0;
+    GLB_GPIO_Init(&gpioCfg);
+    GLB_GPIO_INPUT_Disable(gpioCfg.gpioPin);
+    GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin);
+
+    /* mosi */
+    gpioCfg.gpioPin = mosi;
+    gpioCfg.gpioFun = GPIO_FUN_SPI0;
+    GLB_GPIO_Init(&gpioCfg);
+    GLB_GPIO_INPUT_Enable(gpioCfg.gpioPin);
+    GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin);
+
+    /* miso */
+    gpioCfg.gpioPin = miso;
+    gpioCfg.gpioFun = GPIO_FUN_SPI0;
+    GLB_GPIO_Init(&gpioCfg);
+    GLB_GPIO_INPUT_Enable(gpioCfg.gpioPin);
+    GLB_GPIO_OUTPUT_Enable(gpioCfg.gpioPin);
+
+    GLB_Set_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_MASTER);
+}
+
+void Nandflash_CS_High(void)
+{
+    GLB_GPIO_Write(SPI_PIN_CS, 1);
+}
+
+void Nandflash_CS_Low(void)
+{
+    GLB_GPIO_Write(SPI_PIN_CS, 0);
+}
+
+void Nandflash_Clock_Init(uint8_t enable, uint8_t div)
+{
+    GLB_Set_SPI_CLK(enable, div);
+    GLB_AHB_Slave1_Clock_Gate(DISABLE, BL_AHB_SLAVE1_SPI);
+}
+
+void Nandflash_SPI_Init(NANDFLASH_CFG_Type *pNandflashCfg)
+{
+    SPI_Disable(SPI_ID_0, SPI_WORK_MODE_MASTER);
+    SPI_IntMask(SPI_ID_0, SPI_INT_ALL, MASK);
+    SPI_Init(pNandflashCfg->spiNo, &(pNandflashCfg->spiCfg));
+    SPI_ClockConfig(pNandflashCfg->spiNo, &(pNandflashCfg->clockCfg));
+    SPI_Enable(SPI_ID_0, SPI_WORK_MODE_MASTER);
+}
+
+void Nandflash_SendRecv(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *sendBuff, uint8_t *recvBuff, uint32_t len)
+{
+    SPI_SendRecv_8bits(pNandflashCfg->spiNo, sendBuff, recvBuff, len, SPI_TIMEOUT_DISABLE);
+}
+
+void Nandflash_WriteEnable(NANDFLASH_CFG_Type *pNandflashCfg)
+{
+    uint8_t cmd[1] = { 0 };
+    uint8_t pBlockLock = 0xff;
+
+    cmd[0] = NANDFLASH_WRITE_ENABLE;
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 1, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    /*check block lock status*/
+    Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock);
+
+    if (pBlockLock != 0) {
+        // MSG_ERR("Get BlockLock in Nandflash Write Enable and return %0x\r\n", pBlockLock);
+    }
+}
+
+void Nandflash_WriteDisable(NANDFLASH_CFG_Type *pNandflashCfg)
+{
+    uint8_t cmd[1] = { 0 };
+
+    cmd[0] = NANDFLASH_WRITE_DISABLE;
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 1, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+}
+
+void Nandflash_Get_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock)
+{
+    uint8_t cmd[2] = { 0 };
+    uint8_t ack[1] = { 0 };
+
+    cmd[0] = NANDFLASH_GET_FEATURES;
+    cmd[1] = NANDFLASH_BLOCK_LOCK_ADDR;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE);
+    SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 1, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    *pBlockLock = ack[0];
+}
+
+void Nandflash_Set_BlockLock(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pBlockLock)
+{
+    uint8_t cmd[3] = { 0 };
+
+    cmd[0] = NANDFLASH_SET_FEATURES;
+    cmd[1] = NANDFLASH_BLOCK_LOCK_ADDR;
+    cmd[2] = *pBlockLock;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+}
+
+void Nandflash_Get_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature)
+{
+    uint8_t cmd[2] = { 0 };
+    uint8_t ack[1] = { 0 };
+
+    cmd[0] = NANDFLASH_GET_FEATURES;
+    cmd[1] = NANDFLASH_FEATURE_ADDR;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE);
+    SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 1, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    *pFeature = ack[0];
+}
+
+void Nandflash_Set_Feature(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pFeature)
+{
+    uint8_t cmd[3] = { 0 };
+
+    cmd[0] = NANDFLASH_GET_FEATURES;
+    cmd[1] = NANDFLASH_FEATURE_ADDR;
+    cmd[2] = *pFeature;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+}
+
+void Nandflash_Get_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus)
+{
+    uint8_t cmd[2] = { 0 };
+    uint8_t ack[1] = { 0 };
+
+    cmd[0] = NANDFLASH_GET_FEATURES;
+    cmd[1] = NANDFLASH_STATUS_ADDR;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE);
+    SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 1, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    *pStatus = ack[0];
+}
+
+void Nandflash_Set_Status(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pStatus)
+{
+    uint8_t cmd[3] = { 0 };
+
+    cmd[0] = NANDFLASH_GET_FEATURES;
+    cmd[1] = NANDFLASH_STATUS_ADDR;
+    cmd[2] = *pStatus;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+}
+
+NANDFLASH_ECC_Type Nandflash_CheckBadBlock(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum, uint8_t *buff, uint32_t len)
+{
+    uint32_t pageNum = 0, pageAddr = 0;
+    NANDFLASH_ECC_Type ecc = 0;
+
+    pageNum = blockNum * NANDFLASH_PAGES_PER_BLOCK;
+
+    pageAddr = pageNum * NANDFLASH_PAGE_SIZE;
+
+    if (len) {
+        //read to cache
+        ecc = Nandflash_PageReadToCache(pNandflashCfg, pageAddr);
+
+        /* read from cache */
+        Nandflash_ReadFromCache(pNandflashCfg, NANDFLASH_PAGE_SIZE, buff, len);
+    }
+
+    return ecc;
+}
+
+NANDFLASH_ECC_Type Nandflash_PageRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len)
+{
+    NANDFLASH_ECC_Type ecc = 0;
+    uint32_t pageAddr = addr & 0xFFFFF800;
+    uint32_t readLen = 0;
+    uint32_t pageOffset = addr - pageAddr;
+
+    if ((pageOffset + len) <= NANDFLASH_PAGE_SIZE) {
+        readLen = len;
+    } else {
+        readLen = NANDFLASH_PAGE_SIZE - pageOffset;
+    }
+
+    memset(buff, 0, len);
+
+    if (readLen) {
+        /* read to cache */
+        ecc = Nandflash_PageReadToCache(pNandflashCfg, pageAddr);
+
+        /* read from cache */
+        Nandflash_ReadFromCache(pNandflashCfg, pageOffset, buff, readLen);
+    }
+
+    return ecc;
+}
+
+NANDFLASH_ECC_Type Nandflash_PagesRead(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len)
+{
+    NANDFLASH_ECC_Type ecc = 0;
+    uint32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0;
+    uint32_t readLen = 0, pageOffset = 0, beginAddr = addr;
+
+    startPageNum = addr / NANDFLASH_PAGE_SIZE;
+    endPageNum = (addr + len - 1) / NANDFLASH_PAGE_SIZE;
+
+    memset(buff, 0, len);
+
+    if (len > 0) {
+        for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) {
+            pageOffset = addr % NANDFLASH_PAGE_SIZE;
+
+            if (absolutePageNum == startPageNum) {
+                if (beginAddr + len >= NANDFLASH_PAGE_SIZE) {
+                    readLen = (startPageNum + 1) * NANDFLASH_PAGE_SIZE - beginAddr;
+                } else {
+                    readLen = len;
+                }
+            } else if ((startPageNum < absolutePageNum) && (absolutePageNum < endPageNum)) {
+                readLen = NANDFLASH_PAGE_SIZE;
+            } else if (absolutePageNum == endPageNum) {
+                readLen = (beginAddr + len) - (endPageNum * NANDFLASH_PAGE_SIZE);
+            }
+
+            /* read to cache */
+            ecc = Nandflash_PageReadToCache(pNandflashCfg, absolutePageNum * NANDFLASH_PAGE_SIZE);
+            /* read from cache */
+            Nandflash_ReadFromCache(pNandflashCfg, pageOffset, buff, readLen);
+
+            addr = (absolutePageNum + 1) * NANDFLASH_PAGE_SIZE;
+            buff += readLen;
+        }
+    }
+
+    return ecc;
+}
+NANDFLASH_ECC_Type Nandflash_PageReadToCache(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr)
+{
+    uint8_t feature = 0;
+    uint8_t cmd[4] = { 0 };
+    uint8_t status = 0xff;
+    uint8_t pBlockLock = 0xff;
+    NANDFLASH_ECC_Type ecc = 0;
+    uint32_t blockNum = 0;
+    uint32_t pageNum = 0;
+    uint32_t absolutePageNum = 0;
+    uint16_t cmds = 0;
+    /* enable ECC */
+    Nandflash_Get_Feature(pNandflashCfg, &feature);
+    ((NANDFLASH_FEATURE_Type *)(&feature))->ECC_EN = 1;
+    Nandflash_Set_Feature(pNandflashCfg, &feature);
+
+    absolutePageNum = addr / NANDFLASH_PAGE_SIZE;
+    blockNum = absolutePageNum / NANDFLASH_PAGES_PER_BLOCK;
+    pageNum = absolutePageNum % NANDFLASH_PAGES_PER_BLOCK;
+    /* page read to cache */
+    cmd[0] = NANDFLASH_PAGE_READ_TO_CACHE;
+    cmd[1] = NANDFLASH_DUMMY_BYTE;
+    cmds = (uint16_t)(blockNum << 6) | (uint16_t)pageNum;
+    cmd[2] = (uint8_t)(cmds >> 8);
+    cmd[3] = (uint8_t)(cmds >> 0);
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    /*check block lock status*/
+    Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock);
+
+    if (pBlockLock != 0) {
+        // MSG_ERR("Get BlockLock in Nandflash PageRead To Cache and return %0x\r\n", pBlockLock);
+    }
+
+    BL702_Delay_MS(20);
+
+    /* Operation In Progress */
+    do {
+        Nandflash_Get_Status(pNandflashCfg, &status);
+    } while ((((NANDFLASH_STATUS_Type *)(&status))->OIP));
+
+    /* get ecc */
+    Nandflash_Get_Status(pNandflashCfg, &status);
+    ecc = status;
+
+    return ecc;
+}
+
+void Nandflash_ReadFromCache(NANDFLASH_CFG_Type *pNandflashCfg, uint16_t offset, uint8_t *buff, uint32_t len)
+{
+    uint32_t readLen = len;
+    uint8_t cmd[4] = { 0 };
+    uint8_t pBlockLock = 0xff;
+
+    if (!buff) {
+        return;
+    }
+
+    if (readLen > NANDFLASH_PAGE_SIZE) {
+        readLen = NANDFLASH_PAGE_SIZE;
+    }
+
+    /* read from cache */
+    cmd[0] = NANDFLASH_READ_FROM_CACHE;
+    cmd[1] = (uint8_t)((offset >> 8) & 0x0F);
+    cmd[2] = (uint8_t)((offset >> 0) & 0xFF);
+    cmd[3] = NANDFLASH_DUMMY_BYTE;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE);
+    SPI_Recv_8bits(pNandflashCfg->spiNo, buff, readLen, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    /*check block lock status*/
+    Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock);
+
+    if (pBlockLock != 0) {
+        // MSG_ERR("Get BlockLock in Nandflash Read From Cache Erase and return %0x\r\n", pBlockLock);
+    }
+}
+
+void Nandflash_ReadID(NANDFLASH_CFG_Type *pNandflashCfg, uint8_t *pManufactureID, uint8_t *pDeviceID)
+{
+    uint8_t cmd[2] = { 0 };
+    uint8_t ack[2] = { 0 };
+
+    cmd[0] = NANDFLASH_READ_ID;
+    cmd[1] = NANDFLASH_DUMMY_BYTE;
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 2, SPI_TIMEOUT_DISABLE);
+    SPI_Recv_8bits(pNandflashCfg->spiNo, ack, 2, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    *pManufactureID = ack[0];
+    *pDeviceID = ack[1];
+}
+
+void Nandflash_PageProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len)
+{
+    uint32_t pageAddr = addr & 0xFFFFF800;
+    uint32_t writeLen = 0;
+    uint32_t pageOffset = addr - pageAddr;
+
+    if ((pageOffset + len) <= NANDFLASH_PAGE_SIZE) {
+        writeLen = len;
+    } else {
+        writeLen = NANDFLASH_PAGE_SIZE - pageOffset;
+    }
+
+    if (writeLen) {
+        /* program load */
+        Nandflash_ProgramLoad(pNandflashCfg, pageOffset, buff, writeLen);
+
+        /* write enable */
+        Nandflash_WriteEnable(pNandflashCfg);
+
+        /* program execute */
+        Nandflash_ProgramExecute(pNandflashCfg, pageAddr);
+    }
+
+    return;
+}
+
+void Nandflash_PagesProgram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, const uint8_t *buff, uint32_t len)
+{
+    int32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0;
+    uint32_t writeLen = 0, pageAddr = 0;
+    uint32_t pageOffset = 0, begin_addr = addr;
+
+    startPageNum = addr / NANDFLASH_PAGE_SIZE;
+    endPageNum = (addr + len - 1) / NANDFLASH_PAGE_SIZE;
+
+    if (len > 0) {
+        for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) {
+            pageOffset = 0;
+            pageAddr = absolutePageNum * NANDFLASH_PAGE_SIZE;
+
+            if (absolutePageNum == startPageNum) {
+                if (begin_addr + len >= NANDFLASH_PAGE_SIZE) {
+                    writeLen = (startPageNum + 1) * NANDFLASH_PAGE_SIZE - begin_addr;
+                } else {
+                    writeLen = len;
+                }
+
+                pageOffset = begin_addr % NANDFLASH_PAGE_SIZE;
+            } else if ((startPageNum < absolutePageNum) && (absolutePageNum < endPageNum)) {
+                writeLen = NANDFLASH_PAGE_SIZE;
+                pageOffset = 0;
+            } else if (absolutePageNum == endPageNum) {
+                writeLen = (begin_addr + len) - (endPageNum * NANDFLASH_PAGE_SIZE);
+                pageOffset = 0;
+            }
+
+            if (writeLen) {
+                /* program load */
+                Nandflash_ProgramLoad(pNandflashCfg, pageOffset, buff, writeLen);
+
+                /* write enable */
+                Nandflash_WriteEnable(pNandflashCfg);
+
+                /* program execute */
+                Nandflash_ProgramExecute(pNandflashCfg, pageAddr);
+            }
+
+            buff += writeLen;
+        }
+    }
+}
+
+void Nandflash_ProgramLoad(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t pageOffset, const uint8_t *buff, uint32_t len)
+{
+    uint8_t cmd[3] = { 0 };
+    uint32_t writeLen = len;
+    uint8_t pBlockLock = 0xff;
+
+    if (!buff) {
+        return;
+    }
+
+    if (len > NANDFLASH_PAGE_SIZE) {
+        writeLen = NANDFLASH_PAGE_SIZE;
+    } else {
+    }
+
+    cmd[0] = NANDFLASH_PROGRAM_LOAD;
+    cmd[1] = (uint8_t)((pageOffset >> 8) & 0x0F);
+    cmd[2] = (uint8_t)((pageOffset >> 0) & 0xFF);
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 3, SPI_TIMEOUT_DISABLE);
+    SPI_Send_8bits(pNandflashCfg->spiNo, (uint8_t *)buff, writeLen, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    /*check block lock status*/
+    Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock);
+
+    if (pBlockLock != 0) {
+        // MSG_ERR("Get BlockLock in Nandflash Program Load and return %0x\r\n", pBlockLock);
+    }
+}
+
+void Nandflash_ProgramExecute(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr)
+{
+    uint8_t feature = 0;
+    uint8_t cmd[4] = { 0 };
+    uint8_t status = 0xff;
+    uint8_t pBlockLock = 0xff;
+    uint32_t absolutePageNum = 0;
+    uint16_t cmds = 0;
+    uint32_t blockNum = 0;
+    uint32_t pageNum = 0;
+    absolutePageNum = addr / NANDFLASH_PAGE_SIZE;
+    blockNum = absolutePageNum / NANDFLASH_PAGES_PER_BLOCK;
+    pageNum = absolutePageNum % NANDFLASH_PAGES_PER_BLOCK;
+
+    /* enable ECC */
+    Nandflash_Get_Feature(pNandflashCfg, &feature);
+    ((NANDFLASH_FEATURE_Type *)(&feature))->ECC_EN = 1;
+    Nandflash_Set_Feature(pNandflashCfg, &feature);
+
+    /* program execute */
+    cmd[0] = NANDFLASH_PROGRAM_EXECUTE;
+    cmd[1] = NANDFLASH_DUMMY_BYTE;
+    cmds = (uint16_t)(blockNum << 6) | (uint16_t)pageNum;
+    cmd[2] = (uint8_t)(cmds >> 8);
+    cmd[3] = (uint8_t)(cmds >> 0);
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    /*check block lock status*/
+    Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock);
+
+    if (pBlockLock != 0) {
+        // MSG_ERR("Get BlockLock in Nandflash Program Execute and return %0x\r\n", pBlockLock);
+    }
+
+    /* Operation In Progress */
+    do {
+        Nandflash_Get_Status(pNandflashCfg, &status);
+    } while ((((NANDFLASH_STATUS_Type *)(&status))->OIP));
+}
+
+void Nandflash_InternalDataMove(NANDFLASH_CFG_Type *pNandflashCfg)
+{
+}
+
+void Nandflash_ProgramLoadRandomData(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr, uint8_t *buff, uint32_t len)
+{
+}
+
+static void Nandflash_Erase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum)
+{
+    uint8_t cmd[4] = { 0 };
+    uint16_t cmds = 0;
+    uint8_t pBlockLock = 0xff;
+
+    /* block erase */
+    cmd[0] = NANDFLASH_BLOCK_ERASE;
+    cmd[1] = NANDFLASH_DUMMY_BYTE;
+    cmds = (uint16_t)(blockNum << 6);
+    cmd[2] = (uint8_t)(cmds >> 8);
+    cmd[3] = (uint8_t)(cmds >> 0);
+
+    Nandflash_CS_High();
+    Nandflash_CS_Low();
+    SPI_Send_8bits(pNandflashCfg->spiNo, cmd, 4, SPI_TIMEOUT_DISABLE);
+    Nandflash_CS_High();
+
+    /*check block lock status*/
+    Nandflash_Get_BlockLock(pNandflashCfg, &pBlockLock);
+
+    if (pBlockLock != 0) {
+        // MSG_ERR("Get BlockLock in Nandflash Erase and return %0x\r\n", pBlockLock);
+    }
+}
+
+void Nandflash_BlockErase(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t addr)
+{
+    uint8_t status = 0xff;
+    uint32_t blockNum = 0;
+    blockNum = addr / NANDFLASH_BLOCK_SIZE;
+
+    Nandflash_WriteEnable(pNandflashCfg);
+    Nandflash_Erase(pNandflashCfg, blockNum);
+
+    /* Operation In Progress */
+    do {
+        Nandflash_Get_Status(pNandflashCfg, &status);
+    } while ((((NANDFLASH_STATUS_Type *)(&status))->OIP));
+}
+
+void Nandflash_Reset(NANDFLASH_CFG_Type *pNandflashCfg)
+{
+}
+
+void Nandflash_WriteUnprotect(NANDFLASH_CFG_Type *pNandflashCfg)
+{
+}
+
+NANDFLASH_ECC_Type Nandflash_Check_ECC_Status(NANDFLASH_CFG_Type *pNandflashCfg)
+{
+    return NO_BIT_ERROR;
+}
+
+int Nandflash_Disk_Status(void)
+{
+    return 0;
+}
+
+int Nandflash_Disk_Initialize(void)
+{
+    return 0;
+}
+
+int Nandflash_Disk_Read(BYTE *buff, LBA_t sector, UINT count)
+{
+    //512 bytes in a sector
+    uint32_t startAddr = sector * DISK_SECTOR_SIZE;
+    uint32_t len = count * DISK_SECTOR_SIZE;
+    NANDFLASH_ECC_Type ecc = 0;
+
+    if (len > 0) {
+        ecc = Nandflash_PagesRead(&nfCfg, startAddr, buff, len);
+    }
+
+    return 0;
+}
+
+void Nandflash_PageReadToPsram(uint32_t addr, uint32_t len)
+{
+    uint32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0;
+    uint32_t beginAddr = addr, psramWriteOffsite = 0;
+    uint8_t readBuff[NANDFLASH_PAGE_SIZE];
+
+    startPageNum = addr / NANDFLASH_PAGE_SIZE;
+    endPageNum = (addr + len - 1) / NANDFLASH_PAGE_SIZE;
+
+    if (len > 0) {
+        for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) {
+            memset(readBuff, 0, sizeof(readBuff));
+
+            Nandflash_PageRead(&nfCfg, beginAddr, readBuff, NANDFLASH_PAGE_SIZE);
+            Nandflash_Psram_Write(readBuff, NANDFLASH_PAGE_SIZE, psramWriteOffsite);
+
+            beginAddr = (absolutePageNum + 1) * NANDFLASH_PAGE_SIZE;
+            psramWriteOffsite += NANDFLASH_PAGE_SIZE;
+        }
+    }
+}
+
+static void Nandflash_PageWriteToPsram(const uint8_t *buff, uint32_t psramWriteOffsite, uint32_t len)
+{
+    if (len > 0) {
+        return Nandflash_Psram_Write((uint8_t *)buff, len, psramWriteOffsite);
+    }
+}
+
+static void Nandflash_PageProgramFromPsram(NANDFLASH_CFG_Type *pNandflashCfg, uint32_t blockNum)
+{
+    uint8_t psramReadBuf[NANDFLASH_PAGE_SIZE];
+    uint32_t startPageNum = 0, endPageNum = 0, absolutePageNum = 0;
+    uint32_t psramReadOffsite = 0;
+
+    startPageNum = blockNum * NANDFLASH_PAGES_PER_BLOCK;
+    endPageNum = (blockNum + 1) * NANDFLASH_PAGES_PER_BLOCK - 1;
+
+    for (absolutePageNum = startPageNum; absolutePageNum <= endPageNum; absolutePageNum++) {
+        memset(psramReadBuf, 0, NANDFLASH_PAGE_SIZE);
+        Nandflash_Psram_Read(psramReadBuf, NANDFLASH_PAGE_SIZE, psramReadOffsite);
+        Nandflash_PageProgram(pNandflashCfg, absolutePageNum * NANDFLASH_PAGE_SIZE, psramReadBuf, NANDFLASH_PAGE_SIZE);
+        psramReadOffsite += NANDFLASH_PAGE_SIZE;
+    }
+}
+
+int Nandflash_Disk_Write(const BYTE *buff, LBA_t sector, UINT count)
+{
+    uint32_t addr = sector * DISK_SECTOR_SIZE;
+    uint32_t len = count * DISK_SECTOR_SIZE;
+    uint32_t startBlockNum = 0, endBlockNum = 0, absoluteBlockNum = 0;
+    uint32_t writeLen = 0, beginAddr = addr;
+
+    startBlockNum = addr / NANDFLASH_BLOCK_SIZE;
+    endBlockNum = (addr + len - 1) / NANDFLASH_BLOCK_SIZE;
+
+    if (len > 0) {
+        Nandflash_Psram_Cfg();
+
+        for (absoluteBlockNum = startBlockNum; absoluteBlockNum <= endBlockNum; absoluteBlockNum++) {
+            if (absoluteBlockNum == startBlockNum) {
+                if (addr + len >= NANDFLASH_BLOCK_SIZE) {
+                    writeLen = (absoluteBlockNum + 1) * NANDFLASH_BLOCK_SIZE - addr;
+                } else {
+                    writeLen = len;
+                }
+            } else if ((startBlockNum < absoluteBlockNum) && (absoluteBlockNum < endBlockNum)) {
+                writeLen = NANDFLASH_BLOCK_SIZE;
+            } else if (absoluteBlockNum == endBlockNum) {
+                writeLen = (addr + len) - (endBlockNum * NANDFLASH_BLOCK_SIZE);
+            }
+
+            /*read data from block to psram*/
+            Nandflash_PageReadToPsram(absoluteBlockNum * NANDFLASH_BLOCK_SIZE, NANDFLASH_BLOCK_SIZE);
+            /*update program data to psram*/
+            Nandflash_PageWriteToPsram(buff, beginAddr % NANDFLASH_BLOCK_SIZE, writeLen);
+            /*erase block*/
+            Nandflash_BlockErase(&nfCfg, absoluteBlockNum * NANDFLASH_BLOCK_SIZE);
+            /*program data from psram to block*/
+            Nandflash_PageProgramFromPsram(&nfCfg, absoluteBlockNum);
+
+            buff += writeLen;
+            beginAddr = (absoluteBlockNum + 1) * NANDFLASH_BLOCK_SIZE;
+        }
+    }
+
+    return 0;
+}
+
+int Nandflash_Disk_Ioctl(BYTE cmd, void *buff)
+{
+    return 0;
+}
+
+void Nandflash_Init()
+{
+    Nandflash_Gpio_Init(SPI_PIN_CLK, SPI_PIN_MISO, SPI_PIN_MOSI);
+    Nandflash_Clock_Init(ENABLE, 0x1F);
+    Nandflash_SPI_Init(&nfCfg);
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c
new file mode 100755
index 0000000000..fcd7d25e5f
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/src/bl702_xip_sflash_ext.c
@@ -0,0 +1,197 @@
+/**
+  ******************************************************************************
+  * @file    bl702_xip_sflash_ext.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+
+#include "bl702_xip_sflash_ext.h"
+
+/** @addtogroup  BL702_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  XIP_SFLASH
+ *  @{
+ */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Macros
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Macros */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Types
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Types */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Variables */
+
+/** @defgroup  XIP_SFLASH_EXT_Global_Variables
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Global_Variables */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Fun_Declaration
+ *  @{
+ */
+
+/*@} end of group XIP_SFLASH_EXT_Private_Fun_Declaration */
+
+/** @defgroup  XIP_SFLASH_EXT_Private_Functions
+ *  @{
+ */
+
+/****************************************************************************//**
+ * @brief  XIP SFlash option save
+ *
+ * @param  aes_enable: AES enable status pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_enter(uint8_t *aes_enable)
+{
+    *aes_enable = bflb_sf_ctrl_is_aes_enable();
+
+    if (*aes_enable) {
+        bflb_sf_ctrl_aes_disable();
+    }
+}
+
+/****************************************************************************//**
+ * @brief  XIP SFlash option restore
+ *
+ * @param  aes_enable: AES enable status
+ *
+ * @return None
+ *
+*******************************************************************************/
+void ATTR_TCM_SECTION bflb_xip_sflash_opt_exit(uint8_t aes_enable)
+{
+    if (aes_enable) {
+        bflb_sf_ctrl_aes_enable();
+    }
+}
+
+/****************************************************************************//**
+ * @brief  Read data from flash via XIP
+ *
+ * @param  addr: flash read start address
+ * @param  data: data pointer to store data read from flash
+ * @param  len: data length to read
+ * @param  group: CPU group id 0 or 1
+ * @param  bank: Flash bank select
+ *
+ * @return BFLB_RET:0 means success and other value means error
+ *
+*******************************************************************************/
+__WEAK
+int ATTR_TCM_SECTION bflb_xip_sflash_read_via_cache_need_lock(uint32_t addr,uint8_t *data, uint32_t len,
+                                                              uint8_t group, uint8_t bank)
+{
+    uint32_t offset;
+
+    if(addr>=BL702_FLASH_XIP_BASE && addr
+
+/* This code executes before _start, which is contained inside the C library.
+ * In embedded systems we want to ensure that _enter, which contains the first
+ * code to be executed, can be loaded at a specific address.  To enable this
+ * feature we provide the '.text.metal.init.enter' section, which is
+ * defined to have the first address being where execution should start. */
+    .section .init
+    .global __start
+    .type   __start, %function
+__start:
+    .cfi_startproc
+
+    /* Inform the debugger that there is nowhere to backtrace past _enter. */
+    .cfi_undefined ra
+
+    /* The absolute first thing that must happen is configuring the global
+     * pointer register, which must be done with relaxation disabled because
+     * it's not valid to obtain the address of any symbol without GP
+     * configured.  The C environment might go ahead and do this again, but
+     * that's safe as it's a fixed register. */
+.option push
+.option norelax
+    la gp, __global_pointer$
+.option pop
+
+    /* Disable global interrupt */
+    csrci mstatus,8
+
+    /* Set up a simple trap vector to catch anything that goes wrong early in
+     * the boot process. */
+    la t0, default_trap_handler
+    # /* enable CLIC Vectored mode */
+    ori	t0,t0,3
+    csrw mtvec, t0
+    /* enable chicken bit if core is bullet series*/
+    la t0, __metal_chicken_bit
+    beqz t0, 1f
+    csrwi 0x7C1, 0
+1:
+
+    /* There may be pre-initialization routines inside the MBI code that run in
+     * C, so here we set up a C environment.  First we set up a stack pointer,
+     * which is left as a weak reference in order to allow initialization
+     * routines that do not need a stack to be set up to transparently be
+     * called. */
+    .weak __StackTop
+    la sp, __StackTop
+
+    /* Intial the mtvt, MUST BE 64 bytes aligned*/
+    .weak __Vectors
+    la t0, __Vectors
+    csrw mtvt, t0
+
+#ifdef __riscv_float_abi_single
+    /* deal with FP */
+    /* Is F extension present? */
+    csrr t0, misa
+    andi t0, t0, (1 << ('F' - 'A'))
+    beqz t0, 1f
+    /* If so, enable it */
+    li t0, MSTATUS_FS
+    csrs mstatus, t0
+    fssr x0
+1:
+#endif
+
+    /* Check for an initialization routine and call it if one exists, otherwise
+     * just skip over the call entirely.   Note that __metal_initialize isn't
+     * actually a full C function, as it doesn't end up with the .bss or .data
+     * segments having been initialized.  This is done to avoid putting a
+     * burden on systems that can be initialized without having a C environment
+     * set up. */
+    jal SystemInit
+
+    /* start load code to itcm like. */
+    jal start_load
+
+    jal System_Post_Init
+
+    /* At this point we can enter the C runtime's startup file.  The arguments
+     * to this function are designed to match those provided to the SEE, just
+     * so we don't have to write another ABI. */
+    csrr a0, mhartid
+    li a1, 0
+    li a2, 0
+    jal entry
+
+    csrci mstatus, (1 << 3)
+
+__exit:
+    j __exit
+
+    .cfi_endproc
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/start_load.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/start_load.c
old mode 100644
new mode 100755
similarity index 70%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/start_load.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/start_load.c
index fcae972b98..b09830c474
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/GCC/start_load.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/start_load.c
@@ -1,6 +1,27 @@
+/**
+ * @file start_load.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+
 #include 
-#include "bl808.h"
-#include "bl808_glb.h"
 
 #define __STARTUP_CLEAR_BSS 1
 
@@ -18,8 +39,6 @@ extern uint32_t __tcm_code_start__;
 extern uint32_t __tcm_code_end__;
 extern uint32_t __tcm_data_start__;
 extern uint32_t __tcm_data_end__;
-extern uint32_t __system_ram_data_start__;
-extern uint32_t __system_ram_data_end__;
 extern uint32_t __ram_data_start__;
 extern uint32_t __ram_data_end__;
 extern uint32_t __bss_start__;
@@ -37,10 +56,6 @@ extern uint32_t __HeapLimit;
 //extern uint32_t __zero_table_start__;
 //extern uint32_t __zero_table_end__;
 
-#if defined(DUAL_CORE)
-volatile uintptr_t ATTR_MP_SHARE_DATA_SECTION master_copy_done = 0;
-#endif
-
 void start_load(void)
 {
     uint32_t *pSrc, *pDest;
@@ -62,14 +77,6 @@ void start_load(void)
         *pDest++ = *pSrc++;
     }
 
-    /* BF Add system RAM data copy */
-    pSrc = &__system_ram_load_addr;
-    pDest = &__system_ram_data_start__;
-
-    for (; pDest < &__system_ram_data_end__;) {
-        *pDest++ = *pSrc++;
-    }
-
     /* BF Add OCARAM data copy */
     pSrc = &__ram_load_addr;
     pDest = &__ram_data_start__;
@@ -94,19 +101,4 @@ void start_load(void)
     }
 
 #endif
-
-    /* Bootrom not use dcache,so ignore this flush*/
-#ifndef BOOTROM
-    csi_dcache_clean();
-#endif
-
-#if defined(DUAL_CORE)
-    __DSB();
-
-    if (GLB_CORE_ID_M0 == GLB_Get_Core_Type()) {
-        master_copy_done = 0xE906DAD5;
-    }
-
-    __DSB();
-#endif
-}
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/system_bl702.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/system_bl702.c
new file mode 100755
index 0000000000..979eaa160b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl702/std/startup/system_bl702.c
@@ -0,0 +1,112 @@
+/**
+ * @file system_bl702.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bl702_glb.h"
+#include "bl702_hbn.h"
+#include "bl702_aon.h"
+#include 
+
+void SystemInit(void)
+{
+    uint32_t *p;
+    uint8_t i;
+    uint32_t tmpVal = 0;
+    uint8_t flashCfg = 0;
+    uint8_t psramCfg = 0;
+    uint8_t isInternalFlash = 0;
+    uint8_t isInternalPsram = 0;
+
+    /* global IRQ disable */
+    __disable_irq();
+
+    tmpVal = BL_RD_REG(PDS_BASE, PDS_INT);
+    tmpVal |= (1 << 8);      /*mask pds wakeup*/
+    tmpVal |= (1 << 10);     /*mask rf done*/
+    tmpVal |= (1 << 11);     /*mask pll done*/
+    tmpVal &= ~(0xff << 16); /*mask all pds wakeup source int*/
+    BL_WR_REG(PDS_BASE, PDS_INT, tmpVal);
+
+    /* GLB_Set_EM_Sel(GLB_EM_0KB); */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_SEAM_MISC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_EM_SEL, 0x00); //GLB_EM_0KB
+    BL_WR_REG(GLB_BASE, GLB_SEAM_MISC, tmpVal);
+
+    /* Restore default setting*/
+    /* GLB_UART_Sig_Swap_Set(UART_SIG_SWAP_NONE); */
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_PARM);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_UART_SWAP_SET, 0x00); //UART_SIG_SWAP_NONE
+    BL_WR_REG(GLB_BASE, GLB_PARM, tmpVal);
+
+    /* CLear all interrupt */
+    p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIE_OFFSET);
+
+    for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+        p[i] = 0;
+    }
+
+    p = (uint32_t *)(CLIC_HART0_BASE + CLIC_INTIP_OFFSET);
+
+    for (i = 0; i < (IRQn_LAST + 3) / 4; i++) {
+        p[i] = 0;
+    }
+
+    /* SF io select from efuse value */
+    tmpVal = BL_RD_WORD(0x40007074);
+    flashCfg = ((tmpVal >> 26) & 7);
+    psramCfg = ((tmpVal >> 24) & 3);
+    if (flashCfg == 1 || flashCfg == 2) {
+        isInternalFlash = 1;
+    } else {
+        isInternalFlash = 0;
+    }
+    if (psramCfg == 1) {
+        isInternalPsram = 1;
+    } else {
+        isInternalPsram = 0;
+    }
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO);
+    if (isInternalFlash == 1 && isInternalPsram == 0) {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x3f);
+    } else {
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_CFG_GPIO_USE_PSRAM_IO, 0x00);
+    }
+    BL_WR_REG(GLB_BASE, GLB_GPIO_USE_PSRAM__IO, tmpVal);
+
+    BL_WR_REG(GLB_BASE, GLB_UART_SIG_SEL_0, 0xffffffff);
+
+    /* init bor for all platform */
+    // HBN_BOR_CFG_Type borCfg = { 0 /* pu_bor */, 0 /* irq_bor_en */, 1 /* bor_vth */, 0 /* bor_sel */ };
+    // HBN_Set_BOR_Cfg(&borCfg);
+    /* dcdc 1.8v -> 1.5v */
+    tmpVal = BL_RD_REG(AON_BASE, AON_DCDC18_TOP_0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VOUT_SEL_AON, 0xC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, AON_DCDC18_VPFM_AON, 0x3);
+    BL_WR_REG(AON_BASE, AON_DCDC18_TOP_0, tmpVal);
+}
+
+void System_Post_Init(void)
+{
+    PDS_Trim_RC32M();
+    HBN_Trim_RC32K();
+    /* global IRQ enable */
+    __enable_irq();
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript
new file mode 100755
index 0000000000..d568364440
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/SConscript
@@ -0,0 +1,69 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src     = []
+
+CPPPATH = [cwd]
+CPPDEFINES = []
+
+if GetDepend('BL808_CORE_M0'):
+    src += Split("""
+        std/startup/m0/start.S
+        std/startup/m0/vector.S
+        std/startup/m0/riscv_fpu.S
+        std/startup/m0/start_load.c
+        std/startup/m0/system_bl808.c
+        std/startup/m0/interrupt.c
+    """)
+    CPPDEFINES += ['CPU_M0']
+
+elif GetDepend('BL808_CORE_LP'):
+    src += Split("""
+        std/startup/lp/start.S
+        std/startup/lp/vector.S
+        std/startup/lp/riscv_fpu.S
+        std/startup/lp/start_load.c
+        std/startup/lp/system_bl808.c
+        std/startup/lp/interrupt.c
+    """)
+    CPPDEFINES += ['CPU_LP']
+
+elif GetDepend('BL808_CORE_D0'):
+    src += Split("""
+        std/startup/d0/start.S
+        std/startup/d0/vector.S
+        std/startup/d0/riscv_fpu.S
+        std/startup/d0/start_load.c
+        std/startup/d0/system_bl808.c
+        std/startup/d0/interrupt.c
+    """)
+    CPPDEFINES += ['CPU_D0']
+    
+src += Split("""
+    std/src/bl808_aon.c
+    std/src/bl808_clock.c
+    std/src/bl808_common.c
+    std/src/bl808_ef_cfg.c
+    std/src/bl808_glb.c
+    std/src/bl808_glb_gpio.c
+    std/src/bl808_hbn.c
+    std/src/bl808_l1c.c
+    std/src/bl808_pds.c
+    std/src/bl808_sdh.c
+    std/src/bl808_tzc_sec.c
+    std/src/bl808_psram_uhs.c
+    std/src/bl808_uhs_phy.c
+    std/port/bl808_clock.c
+""")
+
+CPPPATH += [cwd + r'/std/include',
+        cwd + r'/std/include/hardware']
+
+CPPDEFINES += ['CONFIG_IRQ_NUM=80', 'BFLB_USE_HAL_DRIVER', 'BL808', 'default_interrupt_handler=SW_handler']
+LOCAL_CFLAGS = ' -DARCH_RISCV'
+
+group = DefineGroup('bl808', src, depend = ['BSP_USING_BL808'], CPPPATH = CPPPATH, CPPDEFINES = CPPDEFINES, LOCAL_CFLAGS = LOCAL_CFLAGS)
+
+Return('group')
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aon.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_aon.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_aon.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_aon.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_clock.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_clock.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_clock.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_clock.h
index 989f922d0e..774743d686
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_clock.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_clock.h
@@ -132,7 +132,7 @@ typedef enum {
     BL_PERIPHERAL_CLOCK_PKA,         /*!< PKA clock */
     BL_PERIPHERAL_CLOCK_EMI,         /*!< EMI clock */
     BL_PERIPHERAL_CLOCK_H264,        /*!< H264 clock */
-    BL_PERIPHERAL_CLOCK_DSP2,         /*!< DSP2 clock */
+    BL_PERIPHERAL_CLOCK_SUB,         /*!< SUB clock */
     BL_PERIPHERAL_CLOCK_MAX,
 } BL_Peripheral_Type;
 
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_common.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_common.h
new file mode 100755
index 0000000000..a89c01cba9
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_common.h
@@ -0,0 +1,192 @@
+#ifndef __BL808_COMMON_H__
+#define __BL808_COMMON_H__
+
+#include "bl808.h"
+#include "bflb_core.h"
+
+#ifndef __set_MSP
+#define __set_MSP(msp) __ASM volatile("add sp, x0, %0" ::"r"(msp))
+#endif
+
+/** @addtogroup  BL808_Peripheral_Driver
+ *  @{
+ */
+
+/** @addtogroup  COMMON
+ *  @{
+ */
+
+/**
+ * @brief Memory access macro
+ */
+#define BL_RD_WORD(addr)       (*((volatile uint32_t *)(uintptr_t)(addr)))
+#define BL_WR_WORD(addr, val)  ((*(volatile uint32_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_SHORT(addr)      (*((volatile uint16_t *)(uintptr_t)(addr)))
+#define BL_WR_SHORT(addr, val) ((*(volatile uint16_t *)(uintptr_t)(addr)) = (val))
+#define BL_RD_BYTE(addr)       (*((volatile uint8_t *)(uintptr_t)(addr)))
+#define BL_WR_BYTE(addr, val)  ((*(volatile uint8_t *)(uintptr_t)(addr)) = (val))
+#define BL_RDWD_FRM_BYTEP(p)   ((p[3] << 24) | (p[2] << 16) | (p[1] << 8) | (p[0]))
+
+#define BL_WRWD_TO_BYTEP(p, val)   \
+    {                              \
+        p[0] = val & 0xff;         \
+        p[1] = (val >> 8) & 0xff;  \
+        p[2] = (val >> 16) & 0xff; \
+        p[3] = (val >> 24) & 0xff; \
+    }
+/**
+ * @brief Register access macro
+ */
+#define BL_RD_REG16(addr, regname)                BL_RD_SHORT(addr + regname##_OFFSET)
+#define BL_WR_REG16(addr, regname, val)           BL_WR_SHORT(addr + regname##_OFFSET, val)
+#define BL_RD_REG(addr, regname)                  BL_RD_WORD(addr + regname##_OFFSET)
+#define BL_WR_REG(addr, regname, val)             BL_WR_WORD(addr + regname##_OFFSET, val)
+#define BL_SET_REG_BIT(val, bitname)              ((val) | (1U << bitname##_POS))
+#define BL_CLR_REG_BIT(val, bitname)              ((val)&bitname##_UMSK)
+#define BL_GET_REG_BITS_VAL(val, bitname)         (((val)&bitname##_MSK) >> bitname##_POS)
+#define BL_SET_REG_BITS_VAL(val, bitname, bitval) (((val)&bitname##_UMSK) | ((uint32_t)(bitval) << bitname##_POS))
+#define BL_IS_REG_BIT_SET(val, bitname)           (((val) & (1U << (bitname##_POS))) != 0)
+#define BL_DRV_DUMMY           \
+    {                          \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+        __ASM volatile("nop"); \
+    }
+
+/** @defgroup  COMMON_Public_Types
+ *  @{
+ */
+#ifdef BIT
+#undef BIT
+#define BIT(n) (1UL << (n))
+#else
+#define BIT(n) (1UL << (n))
+#endif
+
+/**
+ * @brief Null Type definition
+ */
+#ifndef NULL
+#define NULL 0
+#endif
+
+/**
+ * @brief Error type definition
+ */
+typedef enum {
+    SUCCESS = 0,
+    ERROR = 1,
+    TIMEOUT = 2,
+    INVALID = 3, /* invalid arguments */
+    NORESC = 4   /* no resource or resource temperary unavailable */
+} BL_Err_Type;
+
+/**
+ * @brief Functional type definition
+ */
+typedef enum {
+    DISABLE = 0,
+    ENABLE = 1,
+} BL_Fun_Type;
+
+/**
+ * @brief Status type definition
+ */
+typedef enum {
+    RESET = 0,
+    SET = 1,
+} BL_Sts_Type;
+
+/**
+ * @brief Mask type definition
+ */
+typedef enum {
+    UNMASK = 0,
+    MASK = 1
+} BL_Mask_Type;
+
+/**
+ * @brief Logical status Type definition
+ */
+typedef enum {
+    LOGIC_LO = 0,
+    LOGIC_HI = !LOGIC_LO
+} LogicalStatus;
+
+/**
+ * @brief Active status Type definition
+ */
+typedef enum {
+    DEACTIVE = 0,
+    ACTIVE = !DEACTIVE
+} ActiveStatus;
+
+/**
+ *  @brief Interrupt callback function type
+ */
+typedef void(intCallback_Type)(void);
+typedef void (*pFunc)(void);
+
+#ifdef DEBUG
+void check_failed(uint8_t *file, uint32_t line);
+#define CHECK_PARAM(expr) ((expr) ? (void)0 : check_failed((uint8_t *)__FILE__, __LINE__))
+#else
+#define CHECK_PARAM(expr) ((void)0)
+#endif /* DEBUG */
+
+/** @defgroup  COMMON_Public_Types
+ *  @{
+ */
+
+/*@} end of group COMMON_Public_Types */
+
+/** @defgroup  COMMON_Public_Constants
+ *  @{
+ */
+
+/** @defgroup DRIVER_INT_PERIPH
+ *  @{
+ */
+#define IS_INT_PERIPH(INT_PERIPH) ((INT_PERIPH) < IRQn_LAST)
+
+/*@} end of group DRIVER_INT_PERIPH */
+
+/** @defgroup DRIVER_INT_MASK
+ *  @{
+ */
+#define IS_BL_MASK_TYPE(type) (((type) == MASK) || ((type) == UNMASK))
+
+#define ARCH_MemCpy      arch_memcpy
+#define ARCH_MemSet      arch_memset
+#define ARCH_MemCmp      arch_memcmp
+#define ARCH_MemCpy4     arch_memcpy4
+#define arch_memcpy_fast arch_memcpy_fast
+#define ARCH_MemSet4     arch_memset4
+#define BFLB_Soft_CRC32  bflb_soft_crc32
+#define CPU_Interrupt_Enable(irq)
+#define CPU_Interrupt_Disable(irq)
+#define Interrupt_Handler_Register(irq, callback)
+/*@} end of group COMMON_Public_Constants */
+
+/** @defgroup DRIVER_Public_FunctionDeclaration
+ *  @brief DRIVER functions declaration
+ *  @{
+ */
+
+void ASM_Delay_Us(uint32_t core, uint32_t cnt, uint32_t loopT);
+void arch_delay_us(uint32_t cnt);
+void arch_delay_ms(uint32_t cnt);
+
+void *ARCH_MemCpy(void *dst, const void *src, uint32_t n);
+uint32_t *ARCH_MemCpy4(uint32_t *dst, const uint32_t *src, uint32_t n);
+void *arch_memcpy_fast(void *pdst, const void *psrc, uint32_t n);
+void *ARCH_MemSet(void *s, uint8_t c, uint32_t n);
+uint32_t *ARCH_MemSet4(uint32_t *dst, const uint32_t val, uint32_t n);
+int ARCH_MemCmp(const void *s1, const void *s2, uint32_t n);
+
+void C906_All_Int_Enable(void);
+void C906_All_Int_Disable(void);
+/*@} end of group DRIVER_COMMON  */
+
+#endif /* __BL808_COMMON_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_probe.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ef_cfg.h
old mode 100644
new mode 100755
similarity index 65%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_probe.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ef_cfg.h
index 860ed11358..5ba6c94e77
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_osd_probe.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ef_cfg.h
@@ -1,13 +1,13 @@
 /**
   ******************************************************************************
-  * @file    bl808_osd_probe.h
+  * @file    bl808_ef_cfg.h
   * @version V1.0
   * @date
   * @brief   This file is the standard driver header file
   ******************************************************************************
   * @attention
   *
-  * 
© COPYRIGHT(c) 2021 Bouffalo Lab

+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

   *
   * Redistribution and use in source and binary forms, with or without modification,
   * are permitted provided that the following conditions are met:
@@ -33,62 +33,58 @@
   *
   ******************************************************************************
   */
+#ifndef __BL808_EF_CFG_H__
+#define __BL808_EF_CFG_H__
 
-#ifndef __BL808_OSD_PROBE_H__
-#define __BL808_OSD_PROBE_H__
-
-#include 
+#include "bflb_ef_ctrl.h"
 #include "bl808_common.h"
-#include "osd_probe_reg.h"
 
 /** @addtogroup  BL808_Peripheral_Driver
  *  @{
  */
 
-/** @addtogroup  OSD_PROBE
+/** @addtogroup  EF_CTRL
  *  @{
  */
 
-/** @defgroup  OSD_PROBE_Public_Macros
+/** @defgroup  EF_CTRL_Public_Types
  *  @{
  */
 
-/** @defgroup  OSD_PROBE max supported pointers definitions
+/**
+ *  @brief Efuse analog device info type definition
+ */
+typedef struct
+{
+    uint8_t chipInfo;   /*!< Efuse chip revision */
+    uint8_t memoryInfo; /*!< Efuse memory info 0:no memory, 8:1MB flash */
+    uint8_t psramInfo;  /*!< Efuse psram info 0:no psram, 1:WB 4MB, 2:UHS 32MB, 3:UHS 64MB, 4:WB 32MB, 5:WB 16MB */
+    uint8_t deviceInfo; /*!< Efuse device information */
+} bflb_efuse_device_info_type;
+
+/*@} end of group EF_CTRL_Public_Types */
+
+/** @defgroup  EF_CTRL_Public_Constants
  *  @{
  */
 
-#define OSD_PROBE_ADDR_MAX_INDEX (32)
+/*@} end of group EF_CTRL_Public_Constants */
 
-/*@} end of group OSD_PROBE_Public_Macros */
-
-/** @defgroup  OSD_PROBE_Public_Constants
+/** @defgroup  EF_CTRL_Public_Macros
  *  @{
  */
 
-/*@} end of group OSD_PROBE_Public_Constants */
+/*@} end of group EF_CTRL_Public_Macros */
 
-/** @defgroup  OSD_PROBE_Public_Types
+/** @defgroup  EF_CTRL_Public_Functions
  *  @{
  */
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo);
 
-/*@} end of group OSD_PROBE_Public_Types */
+/*@} end of group EF_CTRL_Public_Functions */
 
-/** @defgroup  OSD_PROBE_Public_Functions
- *  @{
- */
-
-BL_Err_Type osd_probe_set_addr(uintptr_t index, uintptr_t x, uintptr_t y);
-BL_Err_Type osd_probe_get_addr(uintptr_t index, uintptr_t *x, uintptr_t *y);
-BL_Err_Type osd_probe_get_count(uintptr_t *cnt);
-BL_Err_Type osd_probe_get_result(uintptr_t *res);
-BL_Err_Type osd_probe_get_ctrl(uintptr_t *ctrl);
-BL_Err_Type osd_probe_set_threshold(uintptr_t luma);
-BL_Err_Type osd_probe_get_threshold(uintptr_t *luma);
-
-/*@} end of group OSD_PROBE_Public_Functions */
-
-/*@} end of group OSD_PROBE */
+/*@} end of group EF_CTRL */
 
 /*@} end of group BL808_Peripheral_Driver */
 
-#endif
+#endif /* __BL808_EF_CFG_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_ctrl.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ef_ctrl.h
old mode 100644
new mode 100755
similarity index 87%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_ctrl.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ef_ctrl.h
index 9869abf85f..d9524a0e78
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ef_ctrl.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ef_ctrl.h
@@ -132,10 +132,10 @@ typedef struct
  */
 typedef struct
 {
-    uint32_t trimDcdc11VoutAon         :  4;  /*!< Efuse analog trim:dcdc11_vout_trim_aon */
-    uint32_t trimDcdc11VoutAonParity   :  1;  /*!< Efuse analog trim:dcdc11_vout_trim_aon_parity */
-    uint32_t trimDcdc11VoutAonEn       :  1;  /*!< Efuse analog trim:dcdc11_vout_trim_aon_en */
-    uint32_t reserved                  : 26;  /*!< Efuse analog trim:reserved */
+    uint32_t trimDcdc11VoutAon       : 4;  /*!< Efuse analog trim:dcdc11_vout_trim_aon */
+    uint32_t trimDcdc11VoutAonParity : 1;  /*!< Efuse analog trim:dcdc11_vout_trim_aon_parity */
+    uint32_t trimDcdc11VoutAonEn     : 1;  /*!< Efuse analog trim:dcdc11_vout_trim_aon_en */
+    uint32_t reserved                : 26; /*!< Efuse analog trim:reserved */
 } Efuse_Ana_DCDC11_Trim_Type;
 
 /**
@@ -143,10 +143,10 @@ typedef struct
  */
 typedef struct
 {
-    uint32_t trimDcdc18VoutAon         :  4;  /*!< Efuse analog trim:dcdc18_vout_trim_aon */
-    uint32_t trimDcdc18VoutAonParity   :  1;  /*!< Efuse analog trim:dcdc18_vout_trim_aon_parity */
-    uint32_t trimDcdc18VoutAonEn       :  1;  /*!< Efuse analog trim:dcdc18_vout_trim_aon_en */
-    uint32_t reserved                  : 26;  /*!< Efuse analog trim:reserved */
+    uint32_t trimDcdc18VoutAon       : 4;  /*!< Efuse analog trim:dcdc18_vout_trim_aon */
+    uint32_t trimDcdc18VoutAonParity : 1;  /*!< Efuse analog trim:dcdc18_vout_trim_aon_parity */
+    uint32_t trimDcdc18VoutAonEn     : 1;  /*!< Efuse analog trim:dcdc18_vout_trim_aon_en */
+    uint32_t reserved                : 26; /*!< Efuse analog trim:reserved */
 } Efuse_Ana_DCDC18_Trim_Type;
 
 /**
@@ -154,10 +154,10 @@ typedef struct
  */
 typedef struct
 {
-    uint32_t trimLdo18flashVoutAon         :  4;  /*!< Efuse analog trim:ldo18flash_vout_trim */
-    uint32_t trimLdo18flashVoutAonParity   :  1;  /*!< Efuse analog trim:ldo18flash_vout_trim_parity */
-    uint32_t trimLdo18flashVoutAonEn       :  1;  /*!< Efuse analog trim:ldo18flash_vout_trim_en */
-    uint32_t reserved                      : 26;  /*!< Efuse analog trim:reserved */
+    uint32_t trimLdo18flashVoutAon       : 4;  /*!< Efuse analog trim:ldo18flash_vout_trim */
+    uint32_t trimLdo18flashVoutAonParity : 1;  /*!< Efuse analog trim:ldo18flash_vout_trim_parity */
+    uint32_t trimLdo18flashVoutAonEn     : 1;  /*!< Efuse analog trim:ldo18flash_vout_trim_en */
+    uint32_t reserved                    : 26; /*!< Efuse analog trim:reserved */
 } Efuse_Ana_LDO18FLASH_Trim_Type;
 
 /**
@@ -165,10 +165,10 @@ typedef struct
  */
 typedef struct
 {
-    uint32_t trimUsb20rcalAon           :  6;  /*!< Efuse analog trim:usb20_rcal_code_aon */
-    uint32_t trimUsb20rcalAonParity     :  1;  /*!< Efuse analog trim:usb20_rcal_code_aon_parity */
-    uint32_t trimUsb20rcalAonEn         :  1;  /*!< Efuse analog trim:usb20_rcal_code_aon_en */
-    uint32_t reserved                   : 24;  /*!< Efuse analog trim:reserved */
+    uint32_t trimUsb20rcalAon       : 6;  /*!< Efuse analog trim:usb20_rcal_code_aon */
+    uint32_t trimUsb20rcalAonParity : 1;  /*!< Efuse analog trim:usb20_rcal_code_aon_parity */
+    uint32_t trimUsb20rcalAonEn     : 1;  /*!< Efuse analog trim:usb20_rcal_code_aon_en */
+    uint32_t reserved               : 24; /*!< Efuse analog trim:reserved */
 } Efuse_Ana_USB20RCAL_Trim_Type;
 
 /**
@@ -359,12 +359,8 @@ void EF_Ctrl_Write_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len, uint8
 void EF_Ctrl_Read_AES_Key(uint8_t index, uint32_t *keyData, uint32_t len);
 void EF_Ctrl_Writelock_AES_Key(uint8_t index, uint8_t program);
 void EF_Ctrl_Readlock_AES_Key(uint8_t index, uint8_t program);
-void EF_Ctrl_Program_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
-void EF_Ctrl_Program_Direct_R1(uint32_t index, uint32_t *data, uint32_t len);
-void EF_Ctrl_Read_Direct_R0(uint32_t index, uint32_t *data, uint32_t len);
-void EF_Ctrl_Read_Direct_R1(uint32_t index, uint32_t *data, uint32_t len);
-void EF_Ctrl_Program_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len);
-void EF_Ctrl_Read_Direct(uint32_t region, uint32_t index, uint32_t *data, uint32_t len);
+void EF_Ctrl_Program_Direct(uint32_t offset, uint32_t *pword, uint32_t count);
+void EF_Ctrl_Read_Direct(uint32_t offset, uint32_t *pword, uint32_t count);
 void EF_Ctrl_Clear(uint8_t region, uint32_t index, uint32_t len);
 void EF_Ctrl_Crc_Enable(void);
 BL_Sts_Type EF_Ctrl_Crc_Is_Busy(void);
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_glb.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb.h
old mode 100644
new mode 100755
similarity index 95%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_glb.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb.h
index 82fa982e2d..156335ad54
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_glb.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb.h
@@ -42,12 +42,11 @@
 #include "pds_reg.h"
 #include "bl808_gpio.h"
 #include "bl808_hbn.h"
-#include "bl808_sf_ctrl.h"
-#include "bl808_sf_cfg.h"
 #include "bl808_aon.h"
-#include "bl808_ef_ctrl.h"
 #include "bl808_pds.h"
 #include "bl808_common.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
 
 /** @addtogroup  BL808_Peripheral_Driver
  *  @{
@@ -144,15 +143,15 @@ typedef enum {
  */
 typedef enum {
     GLB_DSP_ALL_INT_BUS_DEC_ERR_INT = 0,      /*!< bus_dec_err_int */
-    GLB_DSP_ALL_INT_DSP2_AWB3_INT = 1,         /*!< dsp2_awb3_int */
+    GLB_DSP_ALL_INT_RSV1_INT = 1,             /*!< rsv1 */
     GLB_DSP_ALL_INT_IPC2_NP2AP_IRQ = 2,       /*!< |ipc2_np2ap_irq */
     GLB_DSP_ALL_INT_RSV3 = 3,                 /*!< rsv3 */
     GLB_DSP_ALL_INT_UART0_INT = 4,            /*!< uart0_int */
     GLB_DSP_ALL_INT_I2C0_INT = 5,             /*!< i2c0_int */
     GLB_DSP_ALL_INT_I2C1_INT = 6,             /*!< i2c1_int */
     GLB_DSP_ALL_INT_SPI_INT = 7,              /*!< spi_int */
-    GLB_DSP_ALL_INT_DSP2_AE_INT = 8,           /*!< dsp2_ae_int */
-    GLB_DSP_ALL_INT_DSP2_AWB_INT = 9,          /*!< dsp2_awb_int */
+    GLB_DSP_ALL_INT_RSV4_INT = 8,             /*!< rsv4 */
+    GLB_DSP_ALL_INT_RSV5_INT = 9,             /*!< rsv5 */
     GLB_DSP_ALL_INT_SEOF1_INT = 10,           /*!< seof1_int */
     GLB_DSP_ALL_INT_SEOF2_INT = 11,           /*!< seof2_int */
     GLB_DSP_ALL_INT_SEOF3_INT = 12,           /*!< seof3_int */
@@ -197,13 +196,13 @@ typedef enum {
     GLB_DSP_ALL_INT_RSV51 = 51,               /*!< rsv51 */
     GLB_DSP_ALL_INT_OSDDP_INT = 52,           /*!< osdDP_int */
     GLB_DSP_ALL_INT_DBI_INT = 53,             /*!< dbi_int */
-    GLB_DSP_ALL_INT_DSP2_WDR_INT = 54,         /*!< dsp2_wdr_int */
+    GLB_DSP_ALL_INT_RSV6_INT = 54,            /*!< rsv6 */
     GLB_DSP_ALL_INT_OSDA_INT = 55,            /*!< osdA_int */
     GLB_DSP_ALL_INT_OSDB_INT = 56,            /*!< osdB_int */
     GLB_DSP_ALL_INT_OSD_PB_INT = 57,          /*!< osd_pb_int */
-    GLB_DSP_ALL_INT_DSP2_AWB2_INT = 58,        /*!< dsp2_awb2_int */
+    GLB_DSP_ALL_INT_RSV7_INT = 58,            /*!< rsv7 */
     GLB_DSP_ALL_INT_MIPI_DSI_INT = 59,        /*!< mipi_dsi_int */
-    GLB_DSP_ALL_INT_DSP2_AE_HIST_INT = 60,     /*!< dsp2_ae_hist_int */
+    GLB_DSP_ALL_INT_RSV8_INT = 60,            /*!< rsv8 */
     GLB_DSP_ALL_INT_MM_TIMER_IRQ2 = 61,       /*!< mm_timer_irq2 */
     GLB_DSP_ALL_INT_MM_TIMER_IRQ3 = 62,       /*!< mm_timer_irq3 */
     GLB_DSP_ALL_INT_MM_WDT_IRQ = 63,          /*!< mm_wdt_irq */
@@ -731,9 +730,9 @@ typedef enum {
     GLB_AHB_DSP_SW_SWRST_PDM0 = 44,
     GLB_AHB_DSP_SW_SWRST_PDM1 = 45,
     GLB_AHB_DSP_SW_SWRST_PUHS = 47,
-    GLB_AHB_DSP_SW_SWRST_DSP2_MISC = 64,
-    GLB_AHB_DSP_SW_SWRST_DSP2_MAIN = 65,
-    GLB_AHB_DSP_SW_SWRST_DSP2_TSRC = 66,
+    GLB_AHB_DSP_SW_SWRST_SUB_MISC = 64,
+    GLB_AHB_DSP_SW_SWRST_SUB_MAIN = 65,
+    GLB_AHB_DSP_SW_SWRST_SUB_TSRC = 66,
     GLB_AHB_DSP_SW_SWRST_DP_TSRC = 67,
     GLB_AHB_DSP_SW_SWRST_NR3D_CTRL = 68,
     GLB_AHB_DSP_SW_SWRST_DVP2BUSA = 69,
@@ -741,7 +740,7 @@ typedef enum {
     GLB_AHB_DSP_SW_SWRST_DVP2BUSC = 71,
     GLB_AHB_DSP_SW_SWRST_DVP2BUSD = 72,
     GLB_AHB_DSP_SW_SWRST_MIPI = 73,
-    GLB_AHB_DSP_SW_SWRST_DSP2_REG = 80,
+    GLB_AHB_DSP_SW_SWRST_SUB_REG = 80,
     GLB_AHB_DSP_SW_SWRST_DVP2BUSE = 81,
     GLB_AHB_DSP_SW_SWRST_DVP2BUSF = 82,
     GLB_AHB_DSP_SW_SWRST_DVP2BUSG = 83,
@@ -1124,22 +1123,22 @@ typedef enum {
 } GLB_DSP_DP_CLK_Type;
 
 /**
- *  @brief GLB DSP DSP2 clock type definition
+ *  @brief GLB DSP clock type definition
  */
 typedef enum {
-    GLB_DSP_DSP2_CLK_MUXPLL_160M, /*!< Select muxpll 160M as DSP2 clock */
-    GLB_DSP_DSP2_CLK_MUXPLL_240M, /*!< Select muxpll 240M as DSP2 clock */
-    GLB_DSP_DSP2_CLK_CPUPLL_400M, /*!< Select cpupll 400M as DSP2 clock */
-    GLB_DSP_DSP2_CLK_DSP_XCLK,    /*!< Select dsp xclk as DSP2 clock */
-} GLB_DSP_DSP2_CLK_Type;
+    GLB_DSP_CLK_MUXPLL_160M, /*!< Select muxpll 160M as DSP sub clock */
+    GLB_DSP_CLK_MUXPLL_240M, /*!< Select muxpll 240M as DSP sub clock */
+    GLB_DSP_CLK_CPUPLL_400M, /*!< Select cpupll 400M as DSP sub clock */
+    GLB_DSP_CLK_DSP_XCLK,    /*!< Select dsp xclk as DSP sub clock */
+} GLB_DSP_CLK_Type;
 
 /**
  *  @brief GLB DSP H264 clock type definition
  */
 typedef enum {
-    GLB_DSP_H264_DSP_MUXPLL_160M, /*!< Select dsp muxpll 160M as DSP2 clock */
-    GLB_DSP_H264_DSP_MUXPLL_240M, /*!< Select dsp muxpll 240M as DSP2 clock */
-    GLB_DSP_H264_DSP_MUXPLL_320M, /*!< Select dsp muxpll 320M as DSP2 clock */
+    GLB_DSP_H264_DSP_MUXPLL_160M, /*!< Select dsp muxpll 160M as SUB clock */
+    GLB_DSP_H264_DSP_MUXPLL_240M, /*!< Select dsp muxpll 240M as SUB clock */
+    GLB_DSP_H264_DSP_MUXPLL_320M, /*!< Select dsp muxpll 320M as SUB clock */
 } GLB_DSP_H264_CLK_Type;
 
 /**
@@ -1210,19 +1209,19 @@ typedef enum {
 } GLB_DSP_PERIPHERAL_Type;
 
 /**
- *  @brief GLB DSP dsp2 sub type definition
+ *  @brief GLB DSP sub type definition
  */
 typedef enum {
-    GLB_DSP_DSP2_SUB_DSP2_MISC = 0, /*!< dsp2_misc */
-    GLB_DSP_DSP2_SUB_DVP2BUSA = 1, /*!< dvp2busA */
-    GLB_DSP_DSP2_SUB_DVP2BUSB = 2, /*!< dvp2busB */
-    GLB_DSP_DSP2_SUB_DVP2BUSC = 3, /*!< dvp2busC */
-    GLB_DSP_DSP2_SUB_OSD_DRAW = 4, /*!< osd_draw */
-    GLB_DSP_DSP2_SUB_DP = 5,       /*!< display */
-    GLB_DSP_DSP2_SUB_IMG_PR = 16,  /*!< img_pr scaler/yuv2rgb */
-    GLB_DSP_DSP2_SUB_SCLRA = 17,   /*!< ScalerA */
-    GLB_DSP_DSP2_SUB_SCLRB = 18,   /*!< ScalerB */
-} GLB_DSP_DSP2_SUB_Type;
+    GLB_DSP_SUB_MISC = 0,     /*!< sub_misc */
+    GLB_DSP_SUB_DVP2BUSA = 1, /*!< dvp2busA */
+    GLB_DSP_SUB_DVP2BUSB = 2, /*!< dvp2busB */
+    GLB_DSP_SUB_DVP2BUSC = 3, /*!< dvp2busC */
+    GLB_DSP_SUB_OSD_DRAW = 4, /*!< osd_draw */
+    GLB_DSP_SUB_DP = 5,       /*!< display */
+    GLB_DSP_SUB_IMG_PR = 16,  /*!< img_pr scaler/yuv2rgb */
+    GLB_DSP_SUB_SCLRA = 17,   /*!< ScalerA */
+    GLB_DSP_SUB_SCLRB = 18,   /*!< ScalerB */
+} GLB_DSP_SUB_Type;
 
 /**
  *  @brief GLB DSP codec sub type definition
@@ -1240,6 +1239,28 @@ typedef enum {
     GLB_DSP_IMAGE_SENSOR_RG_IS = 1, /*!< Image sensor */
 } GLB_DSP_IMAGE_SENSOR_Type;
 
+/**
+ *  @brief GLB LDO15CIS level type definition
+ */
+typedef enum {
+    GLB_LDO15CIS_LEVEL_1P00V = 0,  /*!< GLB LDO15CIS voltage 1.00V */
+    GLB_LDO15CIS_LEVEL_1P05V = 1,  /*!< GLB LDO15CIS voltage 1.05V */
+    GLB_LDO15CIS_LEVEL_1P10V = 2,  /*!< GLB LDO15CIS voltage 1.10V */
+    GLB_LDO15CIS_LEVEL_1P15V = 3,  /*!< GLB LDO15CIS voltage 1.15V */
+    GLB_LDO15CIS_LEVEL_1P20V = 4,  /*!< GLB LDO15CIS voltage 1.20V */
+    GLB_LDO15CIS_LEVEL_1P30V = 5,  /*!< GLB LDO15CIS voltage 1.30V */
+    GLB_LDO15CIS_LEVEL_1P40V = 6,  /*!< GLB LDO15CIS voltage 1.40V */
+    GLB_LDO15CIS_LEVEL_1P45V = 7,  /*!< GLB LDO15CIS voltage 1.45V */
+    GLB_LDO15CIS_LEVEL_1P50V = 8,  /*!< GLB LDO15CIS voltage 1.50V */
+    GLB_LDO15CIS_LEVEL_1P55V = 9,  /*!< GLB LDO15CIS voltage 1.55V */
+    GLB_LDO15CIS_LEVEL_1P60V = 10, /*!< GLB LDO15CIS voltage 1.60V */
+    GLB_LDO15CIS_LEVEL_1P65V = 11, /*!< GLB LDO15CIS voltage 1.65V */
+    GLB_LDO15CIS_LEVEL_1P70V = 12, /*!< GLB LDO15CIS voltage 1.70V */
+    GLB_LDO15CIS_LEVEL_1P75V = 13, /*!< GLB LDO15CIS voltage 1.75V */
+    GLB_LDO15CIS_LEVEL_1P80V = 14, /*!< GLB LDO15CIS voltage 1.80V */
+    GLB_LDO15CIS_LEVEL_1P85V = 15, /*!< GLB LDO15CIS voltage 1.85V */
+} GLB_LDO15CIS_LEVEL_Type;
+
 /*@} end of group GLB_Public_Types */
 
 /** @defgroup  GLB_Public_Constants
@@ -1265,15 +1286,15 @@ typedef enum {
  *  @{
  */
 #define IS_GLB_DSP_ALL_INT_TYPE(type) (((type) == GLB_DSP_ALL_INT_BUS_DEC_ERR_INT) ||     \
-                                       ((type) == GLB_DSP_ALL_INT_DSP2_AWB3_INT) ||        \
+                                       ((type) == GLB_DSP_ALL_INT_RSV1_INT) ||        \
                                        ((type) == GLB_DSP_ALL_INT_IPC2_NP2AP_IRQ) ||      \
                                        ((type) == GLB_DSP_ALL_INT_RSV3) ||                \
                                        ((type) == GLB_DSP_ALL_INT_UART0_INT) ||           \
                                        ((type) == GLB_DSP_ALL_INT_I2C0_INT) ||            \
                                        ((type) == GLB_DSP_ALL_INT_I2C1_INT) ||            \
                                        ((type) == GLB_DSP_ALL_INT_SPI_INT) ||             \
-                                       ((type) == GLB_DSP_ALL_INT_DSP2_AE_INT) ||          \
-                                       ((type) == GLB_DSP_ALL_INT_DSP2_AWB_INT) ||         \
+                                       ((type) == GLB_DSP_ALL_INT_RSV4_INT) ||          \
+                                       ((type) == GLB_DSP_ALL_INT_RSV5_INT) ||         \
                                        ((type) == GLB_DSP_ALL_INT_SEOF1_INT) ||           \
                                        ((type) == GLB_DSP_ALL_INT_SEOF2_INT) ||           \
                                        ((type) == GLB_DSP_ALL_INT_SEOF3_INT) ||           \
@@ -1318,13 +1339,13 @@ typedef enum {
                                        ((type) == GLB_DSP_ALL_INT_RSV51) ||               \
                                        ((type) == GLB_DSP_ALL_INT_OSDDP_INT) ||           \
                                        ((type) == GLB_DSP_ALL_INT_DBI_INT) ||             \
-                                       ((type) == GLB_DSP_ALL_INT_DSP2_WDR_INT) ||         \
+                                       ((type) == GLB_DSP_ALL_INT_RSV6_INT) ||         \
                                        ((type) == GLB_DSP_ALL_INT_OSDA_INT) ||            \
                                        ((type) == GLB_DSP_ALL_INT_OSDB_INT) ||            \
                                        ((type) == GLB_DSP_ALL_INT_OSD_PB_INT) ||          \
-                                       ((type) == GLB_DSP_ALL_INT_DSP2_AWB2_INT) ||        \
+                                       ((type) == GLB_DSP_ALL_INT_RSV7_INT) ||        \
                                        ((type) == GLB_DSP_ALL_INT_MIPI_DSI_INT) ||        \
-                                       ((type) == GLB_DSP_ALL_INT_DSP2_AE_HIST_INT) ||     \
+                                       ((type) == GLB_DSP_ALL_INT_RSV8_INT) ||     \
                                        ((type) == GLB_DSP_ALL_INT_MM_TIMER_IRQ2) ||       \
                                        ((type) == GLB_DSP_ALL_INT_MM_TIMER_IRQ3) ||       \
                                        ((type) == GLB_DSP_ALL_INT_MM_WDT_IRQ))
@@ -1792,9 +1813,9 @@ typedef enum {
                                       ((type) == GLB_AHB_DSP_SW_SWRST_PDM0) ||            \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_PDM1) ||            \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_PUHS) ||            \
-                                      ((type) == GLB_AHB_DSP_SW_SWRST_DSP2_MISC) ||        \
-                                      ((type) == GLB_AHB_DSP_SW_SWRST_DSP2_MAIN) ||        \
-                                      ((type) == GLB_AHB_DSP_SW_SWRST_DSP2_TSRC) ||        \
+                                      ((type) == GLB_AHB_DSP_SW_SWRST_SUB_MISC) ||        \
+                                      ((type) == GLB_AHB_DSP_SW_SWRST_SUB_MAIN) ||        \
+                                      ((type) == GLB_AHB_DSP_SW_SWRST_SUB_TSRC) ||        \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_DP_TSRC) ||         \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_NR3D_CTRL) ||       \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSA) ||        \
@@ -1802,7 +1823,7 @@ typedef enum {
                                       ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSC) ||        \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSD) ||        \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_MIPI) ||            \
-                                      ((type) == GLB_AHB_DSP_SW_SWRST_DSP2_REG) ||         \
+                                      ((type) == GLB_AHB_DSP_SW_SWRST_SUB_REG) ||         \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSE) ||        \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSF) ||        \
                                       ((type) == GLB_AHB_DSP_SW_SWRST_DVP2BUSG) ||        \
@@ -2104,13 +2125,13 @@ typedef enum {
 #define IS_GLB_DSP_DP_CLK_TYPE(type) (((type) == GLB_DSP_DP_CLK_DISPLAY_PLL) || \
                                       ((type) == GLB_DSP_DP_CLK_DSP_XCLK))
 
-/** @defgroup  GLB_DSP_DSP2_CLK_TYPE
+/** @defgroup  GLB_DSP_CLK_TYPE
  *  @{
  */
-#define IS_GLB_DSP_DSP2_CLK_TYPE(type) (((type) == GLB_DSP_DSP2_CLK_MUXPLL_160M) || \
-                                       ((type) == GLB_DSP_DSP2_CLK_MUXPLL_240M) || \
-                                       ((type) == GLB_DSP_DSP2_CLK_CPUPLL_400M) || \
-                                       ((type) == GLB_DSP_DSP2_CLK_DSP_XCLK))
+#define IS_GLB_DSP_CLK_TYPE(type) (((type) == GLB_DSP_CLK_MUXPLL_160M) || \
+                                       ((type) == GLB_DSP_CLK_MUXPLL_240M) || \
+                                       ((type) == GLB_DSP_CLK_CPUPLL_400M) || \
+                                       ((type) == GLB_DSP_CLK_DSP_XCLK))
 
 /** @defgroup  GLB_DSP_H264_CLK_TYPE
  *  @{
@@ -2172,18 +2193,18 @@ typedef enum {
                                           ((type) == GLB_DSP_PERIPHERAL_TIMER) ||   \
                                           ((type) == GLB_DSP_PERIPHERAL_I2S0))
 
-/** @defgroup  GLB_DSP_DSP2_SUB_TYPE
+/** @defgroup  GLB_DSP_SUB_TYPE
  *  @{
  */
-#define IS_GLB_DSP_DSP2_SUB_TYPE(type) (((type) == GLB_DSP_DSP2_SUB_DSP2_MISC) || \
-                                       ((type) == GLB_DSP_DSP2_SUB_DVP2BUSA) || \
-                                       ((type) == GLB_DSP_DSP2_SUB_DVP2BUSB) || \
-                                       ((type) == GLB_DSP_DSP2_SUB_DVP2BUSC) || \
-                                       ((type) == GLB_DSP_DSP2_SUB_OSD_DRAW) || \
-                                       ((type) == GLB_DSP_DSP2_SUB_DP) ||       \
-                                       ((type) == GLB_DSP_DSP2_SUB_IMG_PR) ||   \
-                                       ((type) == GLB_DSP_DSP2_SUB_SCLRA) ||    \
-                                       ((type) == GLB_DSP_DSP2_SUB_SCLRB))
+#define IS_GLB_DSP_SUB_TYPE(type) (((type) == GLB_DSP_SUB_MISC) || \
+                                   ((type) == GLB_DSP_SUB_DVP2BUSA) || \
+                                   ((type) == GLB_DSP_SUB_DVP2BUSB) || \
+                                   ((type) == GLB_DSP_SUB_DVP2BUSC) || \
+                                   ((type) == GLB_DSP_SUB_OSD_DRAW) || \
+                                   ((type) == GLB_DSP_SUB_DP) ||       \
+                                   ((type) == GLB_DSP_SUB_IMG_PR) ||   \
+                                   ((type) == GLB_DSP_SUB_SCLRA) ||    \
+                                   ((type) == GLB_DSP_SUB_SCLRB))
 
 /** @defgroup  GLB_DSP_CODEC_SUB_TYPE
  *  @{
@@ -2197,6 +2218,26 @@ typedef enum {
  */
 #define IS_GLB_DSP_IMAGE_SENSOR_TYPE(type) (((type) == GLB_DSP_IMAGE_SENSOR_RG_IS))
 
+/** @defgroup  GLB_LDO15CIS_LEVEL_TYPE
+ *  @{
+ */
+#define IS_GLB_LDO15CIS_LEVEL_TYPE(type) (((type) == GLB_LDO15CIS_LEVEL_1P00V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P05V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P10V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P15V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P20V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P30V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P40V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P45V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P50V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P55V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P60V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P65V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P70V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P75V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P80V) || \
+                                          ((type) == GLB_LDO15CIS_LEVEL_1P85V))
+
 /*@} end of group GLB_Public_Constants */
 
 /** @defgroup  GLB_Public_Macros
@@ -2273,6 +2314,7 @@ extern const GLB_WAC_PLL_Cfg_Type audioPllCfg_442P368M[GLB_XTAL_MAX];
 extern const GLB_WAC_PLL_Cfg_Type audioPllCfg_451P584M[GLB_XTAL_MAX];
 extern const GLB_WAC_PLL_Cfg_Type cpuPllCfg_380M[GLB_XTAL_MAX];
 extern const GLB_WAC_PLL_Cfg_Type cpuPllCfg_400M[GLB_XTAL_MAX];
+extern const GLB_WAC_PLL_Cfg_Type cpuPllCfg_440M[GLB_XTAL_MAX];
 extern const GLB_WAC_PLL_Cfg_Type cpuPllCfg_480M[GLB_XTAL_MAX];
 extern const GLB_MU_PLL_Cfg_Type mipiPllCfg_1500M[GLB_XTAL_MAX];
 extern const GLB_MU_PLL_Cfg_Type uhsPllCfg_2100M[GLB_XTAL_MAX];
@@ -2411,7 +2453,7 @@ BL_Err_Type GLB_Set_SDH_CLK(uint8_t enable, GLB_SDH_CLK_Type clkSel, uint8_t div
 BL_Err_Type GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_Type group, uint8_t swap);
 BL_Err_Type GLB_Swap_DSP_SPI_0_MOSI_With_MISO(BL_Fun_Type newState);
 BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod);
-BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel);
+BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t subSramRel, uint8_t blaiSramRel);
 BL_Err_Type GLB_Swap_MCU_SPI_0_MOSI_With_MISO(BL_Fun_Type newState);
 BL_Err_Type GLB_Set_MCU_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod);
 BL_Err_Type GLB_Set_Flash_IO_PARM(uint8_t selEmbedded, uint8_t swap);
@@ -2420,6 +2462,8 @@ BL_Err_Type GLB_AHB_MCU_Software_Reset(GLB_AHB_MCU_SW_Type swrst);
 BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst);
 BL_Err_Type GLB_PER_Clock_Gate(uint64_t ips);
 BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips);
+BL_Err_Type GLB_PSRAM_PER_Clock_Gate(void);
+BL_Err_Type GLB_PSRAM_PER_Clock_UnGate(void);
 BL_Err_Type GLB_PLL_CGEN_Clock_Gate(GLB_PLL_CGEN_Type clk);
 BL_Err_Type GLB_PLL_CGEN_Clock_UnGate(GLB_PLL_CGEN_Type clk);
 BL_Err_Type GLB_Set_PKA_CLK_Sel(GLB_PKA_CLK_Type clkSel);
@@ -2448,7 +2492,7 @@ BL_Err_Type GLB_Trim_LDO18FLASH_Vout(void);
 /*----------*/
 BL_Err_Type GLB_Set_DSP_CNN_CLK(uint8_t enable, GLB_DSP_CNN_CLK_Type clkSel, uint8_t div);
 BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8_t div);
-BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div);
+BL_Err_Type GLB_Set_DSP_CLK(uint8_t enable, GLB_DSP_CLK_Type clkSel, uint8_t div);
 BL_Err_Type GLB_Set_DSP_H264_CLK(uint8_t enable, GLB_DSP_H264_CLK_Type clkSel, uint8_t div);
 BL_Err_Type GLB_Set_DSP_SPI_CLK(uint8_t enable, GLB_DSP_SPI_CLK_Type clkSel, uint8_t div);
 BL_Err_Type GLB_Set_DSP_UART0_CLK(uint8_t enable, GLB_DSP_UART_CLK_Type uartClk, uint8_t div);
@@ -2458,7 +2502,7 @@ BL_Err_Type GLB_Set_DSP_I2C1_CLK(uint8_t enable, GLB_DSP_I2C_CLK_Type clkSel, ui
 /*----------*/
 BL_Err_Type GLB_DSP_SW_System_Reset(GLB_DSP_SW_SYSTEM_Type sysPart);
 BL_Err_Type GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type periPart);
-BL_Err_Type GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part);
+BL_Err_Type GLB_DSP_Sub_Reset(GLB_DSP_SUB_Type subPart);
 BL_Err_Type GLB_DSP_Codec_Sub_Reset(GLB_DSP_CODEC_SUB_Type codecPart);
 BL_Err_Type GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Type imageSensorPart);
 /*----------*/
@@ -2468,6 +2512,10 @@ BL_Err_Type GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Typ
 BL_Err_Type GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList);
 BL_Err_Type GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t divRatio);
 BL_Err_Type GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList);
+/*----------*/
+BL_Err_Type GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_Type ldoLevel);
+BL_Err_Type GLB_CSI_Config_MIPIPLL(uint8_t postDivSel, uint32_t sdmin);
+BL_Err_Type GLB_CSI_Power_Up_MIPIPLL(void);
 /*----------*/;
 
 /*@} end of group GLB_Public_Functions */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_glb_gpio.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb_gpio.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_glb_gpio.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb_gpio.h
index 1cc3871cc4..40eed3fad1
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_glb_gpio.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_glb_gpio.h
@@ -41,12 +41,11 @@
 #include "pds_reg.h"
 #include "bl808_gpio.h"
 #include "bl808_hbn.h"
-#include "bl808_sf_ctrl.h"
-#include "bl808_sf_cfg.h"
 #include "bl808_aon.h"
-#include "bl808_ef_ctrl.h"
 #include "bl808_pds.h"
 #include "bl808_common.h"
+#include "bflb_sf_ctrl.h"
+#include "bflb_sf_cfg.h"
 
 /** @addtogroup  BL808_Peripheral_Driver
  *  @{
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_gpio.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_gpio.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_gpio.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_gpio.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_hbn.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_hbn.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_hbn.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_hbn.h
index ece53d49db..6f151ee28e
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_hbn.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_hbn.h
@@ -39,8 +39,8 @@
 #include "hbn_reg.h"
 #include "bl808_aon.h"
 #include "bl808_l1c.h"
-#include "bl808_sflash.h"
 #include "bl808_common.h"
+#include "bflb_sflash.h"
 
 /** @addtogroup  BL808_Peripheral_Driver
  *  @{
@@ -323,7 +323,7 @@ typedef struct
     uint32_t sleepTime;                     /*!< HBN sleep time */
     uint8_t gpioWakeupSrc;                  /*!< GPIO Wakeup source */
     HBN_GPIO_INT_Trigger_Type gpioTrigType; /*!< GPIO Triger type */
-    SPI_Flash_Cfg_Type *flashCfg;           /*!< Flash config pointer, used when power down flash */
+    spi_flash_cfg_type *flashCfg;           /*!< Flash config pointer, used when power down flash */
     HBN_LEVEL_Type hbnLevel;                /*!< HBN level */
     HBN_LDO_LEVEL_Type ldoLevel;            /*!< LDO level */
     uint8_t dcdcPuSeq;                      /*!< power on dcdc sequence */
@@ -571,7 +571,7 @@ void HBN_OUT1_IRQHandler(void);
 #endif
 /*----------*/
 void HBN_Mode_Enter(HBN_APP_CFG_Type *cfg);
-void HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg);
+void HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg);
 void HBN_Enable(uint32_t aGPIOIeCfg, HBN_LDO_LEVEL_Type ldoLevel, HBN_LEVEL_Type hbnLevel, uint8_t dcdcPuSeq);
 BL_Err_Type HBN_Reset(void);
 /*----------*/
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ipc.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ipc.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_ipc.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_ipc.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_l1c.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_l1c.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_l1c.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_l1c.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pds.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_pds.h
old mode 100644
new mode 100755
similarity index 98%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pds.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_pds.h
index 1658ccd642..6dd9acc995
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_pds.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_pds.h
@@ -38,13 +38,12 @@
 
 #include "pds_reg.h"
 #include "glb_reg.h"
-#include "bl808_ef_ctrl.h"
 #include "bl808_clock.h"
 #include "bl808_aon.h"
 #include "bl808_hbn.h"
-#include "bl808_sflash.h"
-#include "bl808_sf_ctrl.h"
 #include "bl808_common.h"
+#include "bflb_sflash.h"
+#include "bflb_sf_ctrl.h"
 
 /** @addtogroup  BL808_Peripheral_Driver
  *  @{
@@ -373,7 +372,7 @@ typedef struct
     uint8_t xtalType;                                 /*!< XTal type, used when user choose turn off PLL, PDS will turn on when exit PDS mode */
     uint8_t flashContRead;                            /*!< Whether enable flash continue read */
     uint32_t sleepTime;                               /*!< PDS sleep time */
-    SPI_Flash_Cfg_Type *flashCfg;                     /*!< Flash config pointer, used when power down flash */
+    spi_flash_cfg_type *flashCfg;                     /*!< Flash config pointer, used when power down flash */
     PDS_LDO_LEVEL_Type ldoLevel;                      /*!< LDO level */
     void (*preCbFun)(void);                           /*!< Pre callback function */
     void (*postCbFun)(void);                          /*!< Post callback function */
@@ -474,8 +473,8 @@ BL_Err_Type PDS_Set_GPIO_Pad_IntMask(GLB_GPIO_Type pad, BL_Mask_Type intMask);
 BL_Err_Type PDS_Set_GPIO_Pad_IntMode(PDS_GPIO_INT_SET_Type set, PDS_GPIO_INT_TRIG_Type trig);
 BL_Err_Type PDS_Set_GPIO_Pad_IntClr(PDS_GPIO_INT_SET_Type set);
 BL_Sts_Type PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad);
-BL_Err_Type PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg);
-BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg);
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg);
+BL_Err_Type PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg);
 BL_Err_Type PDS_Set_MCU0_Clock_Enable(void);
 BL_Err_Type PDS_Set_MCU0_Clock_Disable(void);
 BL_Err_Type PDS_Set_MCU0_Reset_Address(uint32_t addr);
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_psram.h
old mode 100644
new mode 100755
similarity index 95%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_psram.h
index 9d6d250fcd..f199d599a3
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_psram.h
@@ -172,11 +172,11 @@ typedef enum {
  *  @brief PSRAM Burst Length type definition
  */
 typedef enum {
-    PSRAM_WINBOND_BURST_LENGTH_128_BYTES, /*!< Burst Length 128 bytes */
-    PSRAM_WINBOND_BURST_LENGTH_64_BYTES,  /*!< Burst Length 64 bytes */
-    PSRAM_WINBOND_BURST_LENGTH_16_BYTES,  /*!< Burst Length 16 bytes */
-    PSRAM_WINBOND_BURST_LENGTH_32_BYTES,  /*!< Burst Length 32 bytes */
-    PSRAM_WINBOND_BURST_LENGTH_512_BYTES, /*!< Burst Length 512 only for HyperBus3 */
+    PSRAM_WINBOND_BURST_LENGTH_128_BYTES = 0x4, /*!< Burst Length 128 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_64_BYTES,        /*!< Burst Length 64 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_16_BYTES,        /*!< Burst Length 16 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_32_BYTES,        /*!< Burst Length 32 bytes */
+    PSRAM_WINBOND_BURST_LENGTH_512_BYTES,       /*!< Burst Length 512 only for HyperBus3 */
 } PSRAM_Winbond_Burst_Length;
 
 /**
@@ -251,6 +251,7 @@ typedef struct
     PSRAM_Ctrl_Vendor_Type vendor;  /*!< PSRAM Vendor */
     PSRAM_Ctrl_Io_Mode_Type ioMode; /*!< PSRAM interface mode */
     PSRAM_Ctrl_Size_Type size;      /*!< PSRAM size */
+    uint32_t dqs_delay;             /*!< PSRAM dqs delay value */
 } PSRAM_Ctrl_Cfg_Type;
 
 /**
@@ -465,12 +466,12 @@ typedef struct
  *  @{
  */
 void PSram_Ctrl_Init(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Cfg_Type *psramCtrlCfg);
-void PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);
-void PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,
-                                  PSRAM_Winbond_Cfg_Type *reg_cfg);
-void PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);
-void PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,
-                                PSRAM_APMemory_Cfg_Type *reg_cfg);
+BL_Err_Type PSram_Ctrl_Winbond_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr, uint16_t *regVal);
+BL_Err_Type PSram_Ctrl_Winbond_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_Winbond_Cfg_Reg_Type reg_addr,
+                                         PSRAM_Winbond_Cfg_Type *reg_cfg);
+BL_Err_Type PSram_Ctrl_ApMem_Read_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr, uint16_t *regVal);
+BL_Err_Type PSram_Ctrl_ApMem_Write_Reg(PSRAM_ID_Type PSRAM_ID, PSRAM_Ctrl_ApMem_Cfg_Reg_Type reg_addr,
+                                       PSRAM_APMemory_Cfg_Type *reg_cfg);
 void PSram_Ctrl_ApMem_Reset(PSRAM_ID_Type PSRAM_ID);
 void PSram_Ctrl_CK_Sel(PSRAM_ID_Type PSRAM_ID, PSRAM_Clock_Type clkSel);
 void PSram_Ctrl_Winbond_Reset(PSRAM_ID_Type PSRAM_ID);
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram_uhs.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_psram_uhs.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram_uhs.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_psram_uhs.h
index 740b0180fa..df36925897
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_psram_uhs.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_psram_uhs.h
@@ -263,6 +263,7 @@ int PSram_UHS_Read_Reg(uint32_t reg_addr, uint8_t *regVal);
 int PSram_UHS_Write_Reg(PSRAM_UHS_Write_Reg_Cfg_Type *regCfg);
 int PSram_UHS_Construct_Cmd(PSRAM_UHS_CMD_Type cmd);
 void Psram_UHS_x16_Init(uint32_t uhs_pll_clk);
+void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg);
 /*@} end of group PSRAM_UHS_Public_Functions */
 
 /*@} end of group PSRAM_UHS */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sdh.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_sdh.h
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sdh.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_sdh.h
index 5497548d34..5eb0fc7e8a
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_sdh.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_sdh.h
@@ -936,9 +936,8 @@ struct SDH_Handle_Cfg_Tag {
 /** @defgroup  SDH_Public_Functions
  *  @{
  */
-#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
 void SDH_MMC1_IRQHandler(void);
-#endif
+
 void SDH_Reset(void);
 void SDH_Set_Timeout(uint8_t tmo);
 void SDH_SetSdClock(uint32_t srcClock, uint32_t busClock);
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_tzc_sec.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_tzc_sec.h
old mode 100644
new mode 100755
similarity index 97%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_tzc_sec.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_tzc_sec.h
index 15ddd5bf5b..345008117a
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/inc/bl808_tzc_sec.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_tzc_sec.h
@@ -69,7 +69,7 @@ typedef enum {
     TZC_SEC_MASTER_D0,     /*!< TZC Master:D0 */
     TZC_SEC_MASTER_BLAI,   /*!< TZC Master:BLAI */
     TZC_SEC_MASTER_CODEC,  /*!< TZC Master:CODEC */
-    TZC_SEC_MASTER_DSP2,    /*!< TZC Master:DSP2 */
+    TZC_SEC_MASTER_ISP,    /*!< TZC Master:ISP */
     TZC_SEC_MASTER_2DDMA,  /*!< TZC Master:2D DMA */
     TZC_SEC_MASTER_DMA2,   /*!< TZC Master:DMA2 */
     TZC_SEC_MASTER_MAX,    /*!< TZC Master max */
@@ -127,8 +127,8 @@ typedef enum {
     TZC_SEC_MM_SLAVE_RSVD5,     /*!< TZC MM Slave:reserved5 */
     TZC_SEC_MM_SLAVE_UHS_PSRAM, /*!< TZC MM Slave:uhs psram */
 
-    TZC_SEC_MM_SLAVE_DSP2_MISC = 16, /*!< TZC MM Slave:DSP2 MISC */
-    TZC_SEC_MM_SLAVE_DSP2_TOP,       /*!< TZC MM Slave:DSP2 TOP */
+    TZC_SEC_MM_SLAVE_ISP_MISC = 16, /*!< TZC MM Slave:ISP MISC */
+    TZC_SEC_MM_SLAVE_ISP_TOP,       /*!< TZC MM Slave:ISP TOP */
     TZC_SEC_MM_SLAVE_DVP_MISC,      /*!< TZC MM Slave:DVP MISC */
     TZC_SEC_MM_SLAVE_OSD_A,         /*!< TZC MM Slave:OSD_A */
     TZC_SEC_MM_SLAVE_OSD_B,         /*!< TZC MM Slave:OSD_B */
@@ -136,10 +136,10 @@ typedef enum {
     TZC_SEC_MM_SLAVE_AWB3_CORE,     /*!< TZC MM Slave:AWB3 core */
     TZC_SEC_MM_SLAVE_AWB3_SRAM,     /*!< TZC MM Slave:AWB3 SRAM */
     TZC_SEC_MM_SLAVE_RSVD6,         /*!< TZC MM Slave:Reserved */
-    TZC_SEC_MM_SLAVE_DSP2_AE_SRAM,   /*!< TZC MM Slave:DSP2 AE SRAM */
+    TZC_SEC_MM_SLAVE_ISP_AE_SRAM,   /*!< TZC MM Slave:ISP AE SRAM */
     TZC_SEC_MM_SLAVE_MIPI,          /*!< TZC MM Slave:MIPI(DSI & CSI )*/
     TZC_SEC_MM_SLAVE_DBI,           /*!< TZC MM Slave:DBI */
-    TZC_SEC_MM_SLAVE_DSP2_AWB_SRAM,  /*!< TZC MM Slave:DSP2 AWB SRAM */
+    TZC_SEC_MM_SLAVE_ISP_AWB_SRAM,  /*!< TZC MM Slave:ISP AWB SRAM */
 
     TZC_SEC_MM_SLAVE_CODEC_MISC = 32, /*!< TZC MM Slave:Codec misc */
     TZC_SEC_MM_SLAVE_MJPEG,           /*!< TZC MM Slave:MJPEG */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_uhs_phy.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_uhs_phy.h
new file mode 100755
index 0000000000..a2560b0634
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/bl808_uhs_phy.h
@@ -0,0 +1,117 @@
+#ifndef __UHS_PHY_H__
+#define __UHS_PHY_H__
+
+#include "bl808_common.h"
+#include "bl808_psram_uhs.h"
+#include "bl808_glb.h"
+
+#ifndef CAL_MODE
+#define CAL_MODE (0)        // 0 is for sw call, 1 is for phy test, 2 is for ate cal
+#endif
+
+enum {
+    UHS_LATENCY_CODE_533 = 3, // "0"
+    UHS_LATENCY_CODE_800 = 3, // "1"
+    UHS_LATENCY_CODE_933 = 3, // "2"
+    UHS_LATENCY_CODE_1066 = 3,
+    UHS_LATENCY_CODE_RESERVED = 3, //"4"
+    UHS_LATENCY_CODE_400 = 3, //"5"
+    UHS_LATENCY_CODE_333 = 3, //"6"
+    UHS_LATENCY_CODE_200 = 3, //"7"
+};
+
+enum{
+    UHS_REGR_GNT_ERR = 1,
+    UHS_REGR_DONE_ERR,
+    UHS_REGW_GNT_ERR,
+    UHS_REGW_DONE_ERR,
+    UHS_LATENCY_CODE_WRITE_ERR,
+    UHS_INIT_ARRAY_WRITE_ERR,
+    UHS_REG_READ_CAL_ERR,
+    UHS_REG_WRITE_CAL_ERR,
+    UHS_ARRAY_READ_LAT_ERR,
+    UHS_ARRAY_WRITE_CK_ERR,
+    UHS_ARRAY_READ_CAL_ERR,
+    UHS_ARRAY_WRITE_CAL_ERR,
+    UHS_CACHE_ENABLE_ERR,
+    UHS_CACHE_DISABLE_ERR,
+    UHS_CACHE_RECOVER_ERR,
+    UHS_REG_WRITE_2kM_ERR,
+    UHS_BAD_DIE_ERR,
+    UHS_DIAGONAL_TEST_ERR,
+    UHS_ALL_ADDR_TEST_ERR,
+};
+
+#if CAL_MODE != 2
+typedef struct
+{
+    uint8_t rl              :6;
+    uint8_t rdqs            :4;
+    uint8_t rdq             :4;
+    uint8_t wl              :5;
+    uint8_t wdqs            :4;
+    uint8_t wdq             :4;
+    uint8_t ck              :4;
+    uint8_t err_type;
+    uint8_t err_sub_type;
+    uint8_t cal_mode;
+    uint16_t datarate;
+    uint8_t rwindow;
+    uint8_t rwindow_begin;
+    uint8_t rwindow_end;
+    uint8_t wwindow;
+    uint8_t wwindow_begin;
+    uint8_t wwindow_end;
+    uint8_t cal_done;
+    uint32_t crc_res;
+} uhs_phy_cal_res_struct;
+#else
+typedef struct
+{
+    uint32_t rl;
+    uint32_t rdqs;
+    uint32_t rdq;
+    uint32_t wl;
+    uint32_t wdqs;
+    uint32_t wdq;
+    uint32_t ck;
+    uint32_t err_type;
+    uint32_t err_sub_type;
+    uint32_t cal_mode;
+    uint32_t datarate;
+    uint32_t rwindow;
+    uint32_t rwindow_begin;
+    uint32_t rwindow_end;
+    uint32_t wwindow;
+    uint32_t wwindow_begin;
+    uint32_t wwindow_end;
+    uint32_t cal_done;
+    uint32_t crc_res;
+} uhs_phy_cal_res_struct;
+#endif
+extern uhs_phy_cal_res_struct* uhs_phy_cal_res;
+
+// function call
+void uhs_phy_init(PSRAM_UHS_Cfg_Type *cfg);
+void uhs_phy_pwr_down(void);
+uint8_t mr_read_back(void);
+void set_odt_en(void);
+// for htol test api
+uint8_t uhs_all_addr_test(void);
+
+// for test or debug in example main.c
+void soft_reset(void);
+void uhs_reset(uint8_t ma_rb);
+void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1);
+uint8_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1);
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq);
+//
+void set_uhs_latency_r(uint32_t uhs_latency);
+void set_uhs_latency_w(uint32_t uhs_latency);
+void cfg_dq_drv(uint32_t dq);
+void cfg_dqs_drv(uint32_t dqs);
+void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv);
+void cfg_dq_rx(uint8_t dq);
+void cfg_dqs_rx(uint8_t dqs);
+
+#endif  // __UHS_PHY_H__
\ No newline at end of file
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/aon_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/aon_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/aon_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/aon_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/bl808.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/bl808.h
old mode 100644
new mode 100755
similarity index 97%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/bl808.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/bl808.h
index 9542fd607a..b96b9b687b
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/bl808.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/bl808.h
@@ -146,15 +146,15 @@ typedef enum {
 #if defined(CPU_D0)
     /******  BL808 specific Interrupt Numbers **********************************************************************/
     BMX_DSP_BUS_ERR_IRQn = IRQ_NUM_BASE + 0,  /*!< BMX DSP BUS Error Interrupt                                       */
-    DSP2_AWB2_IRQn = IRQ_NUM_BASE + 1,         /*!< DSP2 AWB3 Interrupt                                                */
+    D0_RESERVED1_IRQn = IRQ_NUM_BASE + 1,     /*!< D0 reserved1 Interrupt                                            */
     D0_RESERVED2_IRQn = IRQ_NUM_BASE + 2,     /*!< IPC reserved Interrupt                                            */
     D0_RESERVED3_IRQn = IRQ_NUM_BASE + 3,     /*!< UART4 reserved Interrupt                                          */
     UART3_IRQn = IRQ_NUM_BASE + 4,            /*!< UART3 Interrupt                                                   */
     I2C2_IRQn = IRQ_NUM_BASE + 5,             /*!< I2C2 Interrupt                                                    */
     I2C3_IRQn = IRQ_NUM_BASE + 6,             /*!< I2C3 Interrupt                                                    */
     SPI1_IRQn = IRQ_NUM_BASE + 7,             /*!< SPI1 Interrupt                                                    */
-    DSP2_AE_IRQn = IRQ_NUM_BASE + 8,           /*!< DSP2 AE Interrupt                                                  */
-    DSP2_AWB0_IRQn = IRQ_NUM_BASE + 9,         /*!< DSP2 AWB1 Interrupt                                                */
+    D0_RESERVED4_IRQn = IRQ_NUM_BASE + 8,     /*!< D0 reserved4 Interrupt                                            */
+    D0_RESERVED5_IRQn = IRQ_NUM_BASE + 9,     /*!< D0 reserved5 Interrupt                                            */
     SEOF_INT0_IRQn = IRQ_NUM_BASE + 10,       /*!< SEOF INT0 Interrupt                                               */
     SEOF_INT1_IRQn = IRQ_NUM_BASE + 11,       /*!< SEOF INT1 Interrupt                                               */
     SEOF_INT2_IRQn = IRQ_NUM_BASE + 12,       /*!< SEOF INT2 Interrupt                                               */
@@ -199,13 +199,13 @@ typedef enum {
     RESERVED2_IRQn = IRQ_NUM_BASE + 51,       /*!< Reserved Interrupt                                                */
     OSD_IRQn = IRQ_NUM_BASE + 52,             /*!< OSD Interrupt                                                     */
     DBI_IRQn = IRQ_NUM_BASE + 53,             /*!< DBI Interrupt                                                     */
-    DSP2_WDR_IRQn = IRQ_NUM_BASE + 54,         /*!< DSP2 WDR Interrupt                                                 */
+    D0_RESERVED6_IRQn = IRQ_NUM_BASE + 54,    /*!< D0_RESERVED6 Interrupt                                            */
     OSDA_BUS_DRAIN_IRQn = IRQ_NUM_BASE + 55,  /*!< OSDA Bus Drain Interrupt                                          */
     OSDB_BUS_DRAIN_IRQn = IRQ_NUM_BASE + 56,  /*!< OSDB Bus Drain Interrupt                                          */
     OSD_PB_IRQn = IRQ_NUM_BASE + 57,          /*!< OSD PB Interrupt                                                  */
-    DSP2_AWB1_IRQn = IRQ_NUM_BASE + 58,        /*!< DSP2 AWB2 Interrupt                                                */
+    D0_RESERVED7_IRQn = IRQ_NUM_BASE + 58,    /*!< D0_RESERVED7 Interrupt                                            */
     MIPI_DSI_IRQn = IRQ_NUM_BASE + 59,        /*!< MIPI DSI Interrupt                                                */
-    DSP2_AE_HIST_IRQn = IRQ_NUM_BASE + 60,     /*!< DSP2 AE HIST Interrupt                                             */
+    D0_RESERVED8_IRQn = IRQ_NUM_BASE + 60,    /*!< D0_RESERVED8 Interrupt                                            */
     TIMER1_CH0_IRQn = IRQ_NUM_BASE + 61,      /*!< Timer1 Channel 0 Interrupt                                        */
     TIMER1_CH1_IRQn = IRQ_NUM_BASE + 62,      /*!< Timer1 Channel 1 Interrupt                                        */
     TIMER1_WDT_IRQn = IRQ_NUM_BASE + 63,      /*!< Timer1 Watch Dog Interrupt                                        */
@@ -219,14 +219,14 @@ typedef enum {
 /* Add following macro definition in order to pass the compilation */
 #if defined(CPU_M0) || defined(CPU_LP)
 #define BMX_DSP_BUS_ERR_IRQn (IRQn_LAST)
-#define DSP2_AWB2_IRQn        (IRQn_LAST)
+#define D0_RESERVED1_IRQn    (IRQn_LAST)
 #define D0_RESERVED2_IRQn    (IRQn_LAST)
 #define UART3_IRQn           (IRQn_LAST)
 #define I2C2_IRQn            (IRQn_LAST)
 #define I2C3_IRQn            (IRQn_LAST)
 #define SPI1_IRQn            (IRQn_LAST)
-#define DSP2_AE_IRQn          (IRQn_LAST)
-#define DSP2_AWB0_IRQn        (IRQn_LAST)
+#define D0_RESERVED4_IRQn    (IRQn_LAST)
+#define D0_RESERVED5_IRQn    (IRQn_LAST)
 #define SEOF_INT0_IRQn       (IRQn_LAST)
 #define SEOF_INT1_IRQn       (IRQn_LAST)
 #define SEOF_INT2_IRQn       (IRQn_LAST)
@@ -270,13 +270,13 @@ typedef enum {
 #define RESERVED2_IRQn       (IRQn_LAST)
 #define OSD_IRQn             (IRQn_LAST)
 #define DBI_IRQn             (IRQn_LAST)
-#define DSP2_WDR_IRQn         (IRQn_LAST)
+#define D0_RESERVED6_IRQn    (IRQn_LAST)
 #define OSDA_BUS_DRAIN_IRQn  (IRQn_LAST)
 #define OSDB_BUS_DRAIN_IRQn  (IRQn_LAST)
 #define OSD_PB_IRQn          (IRQn_LAST)
-#define DSP2_AWB1_IRQn        (IRQn_LAST)
+#define D0_RESERVED7_IRQn    (IRQn_LAST)
 #define MIPI_DSI_IRQn        (IRQn_LAST)
-#define DSP2_AE_HIST_IRQn     (IRQn_LAST)
+#define D0_RESERVED8_IRQn    (IRQn_LAST)
 #define TIMER1_CH0_IRQn      (IRQn_LAST)
 #define TIMER1_CH1_IRQn      (IRQn_LAST)
 #define TIMER1_WDT_IRQn      (IRQn_LAST)
@@ -462,9 +462,9 @@ typedef enum {
 #define TIMER1_BASE      ((uint32_t)0x30009000)
 #define PSRAM_UHS_BASE   ((uint32_t)0x3000f000)
 
-/* DSP2_SUBSYS */
-#define DSP2_MISC_BASE        ((uint32_t)0x30010000)
-#define DSP2_BASE             ((uint32_t)0x30011000)
+/* SUBSYS */
+#define SUB_MISC_BASE        ((uint32_t)0x30010000)
+#define SUB_BASE             ((uint32_t)0x30011000)
 #define DVP0_BASE            ((uint32_t)0x30012000)
 #define DVP1_BASE            ((uint32_t)0x30012100)
 #define DVP2_BASE            ((uint32_t)0x30012200)
@@ -489,6 +489,7 @@ typedef enum {
 #define MIPI_BASE            ((uint32_t)0x3001a000)
 #define DBI_BASE             ((uint32_t)0x3001b000)
 #define DSI_BASE             ((uint32_t)0x3001a100)
+#define CSI_BASE             ((uint32_t)0x3001a000)
 
 /* CODEC_SUBSYS */
 #define CODEC_MISC_BASE ((uint32_t)0x30020000)
@@ -639,7 +640,6 @@ typedef enum {
   * @}
   */
 #include 
-#include 
 /* ARM CPU include files */
 #ifdef ARCH_ARM
 #ifdef CPU_AP_CM4
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cci_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/cci_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/cci_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/cci_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/codec_misc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/codec_misc_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/codec_misc_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/codec_misc_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ef_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ef_ctrl_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ef_ctrl_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ef_ctrl_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ef_data_0_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ef_data_0_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ef_data_0_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ef_data_0_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ef_data_1_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ef_data_1_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ef_data_1_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ef_data_1_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/glb_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/glb_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/glb_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/glb_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/gpip_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/gpip_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/gpip_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/gpip_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/hbn_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/hbn_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/hbn_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/hbn_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ipc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ipc_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/ipc_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/ipc_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mcu_misc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mcu_misc_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mcu_misc_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mcu_misc_reg.h
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mm_glb_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mm_glb_reg.h
new file mode 100755
index 0000000000..6e9f0e2629
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mm_glb_reg.h
@@ -0,0 +1,726 @@
+/**
+  ******************************************************************************
+  * @file    mm_glb_reg.h
+  * @version V1.0
+  * @date    2021-07-12
+  * @brief   This file is the description of.IP register
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#ifndef __MM_GLB_REG_H__
+#define __MM_GLB_REG_H__
+
+#include "bl808.h"
+
+/* 0x0 : mm_clk_ctrl_cpu */
+#define MM_GLB_MM_CLK_CTRL_CPU_OFFSET        (0x0)
+#define MM_GLB_REG_PLL_EN                    MM_GLB_REG_PLL_EN
+#define MM_GLB_REG_PLL_EN_POS                (0U)
+#define MM_GLB_REG_PLL_EN_LEN                (1U)
+#define MM_GLB_REG_PLL_EN_MSK                (((1U << MM_GLB_REG_PLL_EN_LEN) - 1) << MM_GLB_REG_PLL_EN_POS)
+#define MM_GLB_REG_PLL_EN_UMSK               (~(((1U << MM_GLB_REG_PLL_EN_LEN) - 1) << MM_GLB_REG_PLL_EN_POS))
+#define MM_GLB_REG_CPU_CLK_EN                MM_GLB_REG_CPU_CLK_EN
+#define MM_GLB_REG_CPU_CLK_EN_POS            (1U)
+#define MM_GLB_REG_CPU_CLK_EN_LEN            (1U)
+#define MM_GLB_REG_CPU_CLK_EN_MSK            (((1U << MM_GLB_REG_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_CPU_CLK_EN_POS)
+#define MM_GLB_REG_CPU_CLK_EN_UMSK           (~(((1U << MM_GLB_REG_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_CPU_CLK_EN_POS))
+#define MM_GLB_REG_BCLK_EN                   MM_GLB_REG_BCLK_EN
+#define MM_GLB_REG_BCLK_EN_POS               (2U)
+#define MM_GLB_REG_BCLK_EN_LEN               (1U)
+#define MM_GLB_REG_BCLK_EN_MSK               (((1U << MM_GLB_REG_BCLK_EN_LEN) - 1) << MM_GLB_REG_BCLK_EN_POS)
+#define MM_GLB_REG_BCLK_EN_UMSK              (~(((1U << MM_GLB_REG_BCLK_EN_LEN) - 1) << MM_GLB_REG_BCLK_EN_POS))
+#define MM_GLB_REG_MM_CPU_CLK_EN             MM_GLB_REG_MM_CPU_CLK_EN
+#define MM_GLB_REG_MM_CPU_CLK_EN_POS         (3U)
+#define MM_GLB_REG_MM_CPU_CLK_EN_LEN         (1U)
+#define MM_GLB_REG_MM_CPU_CLK_EN_MSK         (((1U << MM_GLB_REG_MM_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_MM_CPU_CLK_EN_POS)
+#define MM_GLB_REG_MM_CPU_CLK_EN_UMSK        (~(((1U << MM_GLB_REG_MM_CPU_CLK_EN_LEN) - 1) << MM_GLB_REG_MM_CPU_CLK_EN_POS))
+#define MM_GLB_REG_UART_CLK_SEL              MM_GLB_REG_UART_CLK_SEL
+#define MM_GLB_REG_UART_CLK_SEL_POS          (4U)
+#define MM_GLB_REG_UART_CLK_SEL_LEN          (2U)
+#define MM_GLB_REG_UART_CLK_SEL_MSK          (((1U << MM_GLB_REG_UART_CLK_SEL_LEN) - 1) << MM_GLB_REG_UART_CLK_SEL_POS)
+#define MM_GLB_REG_UART_CLK_SEL_UMSK         (~(((1U << MM_GLB_REG_UART_CLK_SEL_LEN) - 1) << MM_GLB_REG_UART_CLK_SEL_POS))
+#define MM_GLB_REG_I2C_CLK_SEL               MM_GLB_REG_I2C_CLK_SEL
+#define MM_GLB_REG_I2C_CLK_SEL_POS           (6U)
+#define MM_GLB_REG_I2C_CLK_SEL_LEN           (1U)
+#define MM_GLB_REG_I2C_CLK_SEL_MSK           (((1U << MM_GLB_REG_I2C_CLK_SEL_LEN) - 1) << MM_GLB_REG_I2C_CLK_SEL_POS)
+#define MM_GLB_REG_I2C_CLK_SEL_UMSK          (~(((1U << MM_GLB_REG_I2C_CLK_SEL_LEN) - 1) << MM_GLB_REG_I2C_CLK_SEL_POS))
+#define MM_GLB_REG_SPI_CLK_SEL               MM_GLB_REG_SPI_CLK_SEL
+#define MM_GLB_REG_SPI_CLK_SEL_POS           (7U)
+#define MM_GLB_REG_SPI_CLK_SEL_LEN           (1U)
+#define MM_GLB_REG_SPI_CLK_SEL_MSK           (((1U << MM_GLB_REG_SPI_CLK_SEL_LEN) - 1) << MM_GLB_REG_SPI_CLK_SEL_POS)
+#define MM_GLB_REG_SPI_CLK_SEL_UMSK          (~(((1U << MM_GLB_REG_SPI_CLK_SEL_LEN) - 1) << MM_GLB_REG_SPI_CLK_SEL_POS))
+#define MM_GLB_REG_CPU_CLK_SEL               MM_GLB_REG_CPU_CLK_SEL
+#define MM_GLB_REG_CPU_CLK_SEL_POS           (8U)
+#define MM_GLB_REG_CPU_CLK_SEL_LEN           (2U)
+#define MM_GLB_REG_CPU_CLK_SEL_MSK           (((1U << MM_GLB_REG_CPU_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_CLK_SEL_POS)
+#define MM_GLB_REG_CPU_CLK_SEL_UMSK          (~(((1U << MM_GLB_REG_CPU_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_CLK_SEL_POS))
+#define MM_GLB_REG_XCLK_CLK_SEL              MM_GLB_REG_XCLK_CLK_SEL
+#define MM_GLB_REG_XCLK_CLK_SEL_POS          (10U)
+#define MM_GLB_REG_XCLK_CLK_SEL_LEN          (1U)
+#define MM_GLB_REG_XCLK_CLK_SEL_MSK          (((1U << MM_GLB_REG_XCLK_CLK_SEL_LEN) - 1) << MM_GLB_REG_XCLK_CLK_SEL_POS)
+#define MM_GLB_REG_XCLK_CLK_SEL_UMSK         (~(((1U << MM_GLB_REG_XCLK_CLK_SEL_LEN) - 1) << MM_GLB_REG_XCLK_CLK_SEL_POS))
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL          MM_GLB_REG_CPU_ROOT_CLK_SEL
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_POS      (11U)
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN      (1U)
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_MSK      (((1U << MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_ROOT_CLK_SEL_POS)
+#define MM_GLB_REG_CPU_ROOT_CLK_SEL_UMSK     (~(((1U << MM_GLB_REG_CPU_ROOT_CLK_SEL_LEN) - 1) << MM_GLB_REG_CPU_ROOT_CLK_SEL_POS))
+#define MM_GLB_REG_MMCPU0_CLK_EN             MM_GLB_REG_MMCPU0_CLK_EN
+#define MM_GLB_REG_MMCPU0_CLK_EN_POS         (12U)
+#define MM_GLB_REG_MMCPU0_CLK_EN_LEN         (1U)
+#define MM_GLB_REG_MMCPU0_CLK_EN_MSK         (((1U << MM_GLB_REG_MMCPU0_CLK_EN_LEN) - 1) << MM_GLB_REG_MMCPU0_CLK_EN_POS)
+#define MM_GLB_REG_MMCPU0_CLK_EN_UMSK        (~(((1U << MM_GLB_REG_MMCPU0_CLK_EN_LEN) - 1) << MM_GLB_REG_MMCPU0_CLK_EN_POS))
+#define MM_GLB_REG_BCLK1X_SEL                MM_GLB_REG_BCLK1X_SEL
+#define MM_GLB_REG_BCLK1X_SEL_POS            (13U)
+#define MM_GLB_REG_BCLK1X_SEL_LEN            (2U)
+#define MM_GLB_REG_BCLK1X_SEL_MSK            (((1U << MM_GLB_REG_BCLK1X_SEL_LEN) - 1) << MM_GLB_REG_BCLK1X_SEL_POS)
+#define MM_GLB_REG_BCLK1X_SEL_UMSK           (~(((1U << MM_GLB_REG_BCLK1X_SEL_LEN) - 1) << MM_GLB_REG_BCLK1X_SEL_POS))
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE      MM_GLB_REG_BCLK2X_DIV_ACT_PULSE
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS  (18U)
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN  (1U)
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_MSK  (((1U << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS)
+#define MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_UMSK (~(((1U << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_ACT_PULSE_POS))
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS         MM_GLB_REG_BCLK2X_DIV_BYPASS
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_POS     (19U)
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN     (1U)
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_MSK     (((1U << MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_BYPASS_POS)
+#define MM_GLB_REG_BCLK2X_DIV_BYPASS_UMSK    (~(((1U << MM_GLB_REG_BCLK2X_DIV_BYPASS_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_BYPASS_POS))
+#define MM_GLB_STS_BCLK2X_PROT_DONE          MM_GLB_STS_BCLK2X_PROT_DONE
+#define MM_GLB_STS_BCLK2X_PROT_DONE_POS      (20U)
+#define MM_GLB_STS_BCLK2X_PROT_DONE_LEN      (1U)
+#define MM_GLB_STS_BCLK2X_PROT_DONE_MSK      (((1U << MM_GLB_STS_BCLK2X_PROT_DONE_LEN) - 1) << MM_GLB_STS_BCLK2X_PROT_DONE_POS)
+#define MM_GLB_STS_BCLK2X_PROT_DONE_UMSK     (~(((1U << MM_GLB_STS_BCLK2X_PROT_DONE_LEN) - 1) << MM_GLB_STS_BCLK2X_PROT_DONE_POS))
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT        MM_GLB_REG_BCLK2X_SW_DONE_CNT
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS    (24U)
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN    (4U)
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_MSK    (((1U << MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN) - 1) << MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS)
+#define MM_GLB_REG_BCLK2X_SW_DONE_CNT_UMSK   (~(((1U << MM_GLB_REG_BCLK2X_SW_DONE_CNT_LEN) - 1) << MM_GLB_REG_BCLK2X_SW_DONE_CNT_POS))
+#define MM_GLB_CPU_CLK_SW_STATE              MM_GLB_CPU_CLK_SW_STATE
+#define MM_GLB_CPU_CLK_SW_STATE_POS          (28U)
+#define MM_GLB_CPU_CLK_SW_STATE_LEN          (3U)
+#define MM_GLB_CPU_CLK_SW_STATE_MSK          (((1U << MM_GLB_CPU_CLK_SW_STATE_LEN) - 1) << MM_GLB_CPU_CLK_SW_STATE_POS)
+#define MM_GLB_CPU_CLK_SW_STATE_UMSK         (~(((1U << MM_GLB_CPU_CLK_SW_STATE_LEN) - 1) << MM_GLB_CPU_CLK_SW_STATE_POS))
+
+/* 0x4 : mm_clk_cpu */
+#define MM_GLB_MM_CLK_CPU_OFFSET       (0x4)
+#define MM_GLB_REG_CPU_CLK_DIV         MM_GLB_REG_CPU_CLK_DIV
+#define MM_GLB_REG_CPU_CLK_DIV_POS     (0U)
+#define MM_GLB_REG_CPU_CLK_DIV_LEN     (8U)
+#define MM_GLB_REG_CPU_CLK_DIV_MSK     (((1U << MM_GLB_REG_CPU_CLK_DIV_LEN) - 1) << MM_GLB_REG_CPU_CLK_DIV_POS)
+#define MM_GLB_REG_CPU_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_CPU_CLK_DIV_LEN) - 1) << MM_GLB_REG_CPU_CLK_DIV_POS))
+#define MM_GLB_REG_CNN_CLK_DIV_EN      MM_GLB_REG_CNN_CLK_DIV_EN
+#define MM_GLB_REG_CNN_CLK_DIV_EN_POS  (8U)
+#define MM_GLB_REG_CNN_CLK_DIV_EN_LEN  (1U)
+#define MM_GLB_REG_CNN_CLK_DIV_EN_MSK  (((1U << MM_GLB_REG_CNN_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_EN_POS)
+#define MM_GLB_REG_CNN_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_CNN_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_EN_POS))
+#define MM_GLB_REG_CNN_CLK_SEL         MM_GLB_REG_CNN_CLK_SEL
+#define MM_GLB_REG_CNN_CLK_SEL_POS     (9U)
+#define MM_GLB_REG_CNN_CLK_SEL_LEN     (2U)
+#define MM_GLB_REG_CNN_CLK_SEL_MSK     (((1U << MM_GLB_REG_CNN_CLK_SEL_LEN) - 1) << MM_GLB_REG_CNN_CLK_SEL_POS)
+#define MM_GLB_REG_CNN_CLK_SEL_UMSK    (~(((1U << MM_GLB_REG_CNN_CLK_SEL_LEN) - 1) << MM_GLB_REG_CNN_CLK_SEL_POS))
+#define MM_GLB_REG_CNN_CLK_DIV         MM_GLB_REG_CNN_CLK_DIV
+#define MM_GLB_REG_CNN_CLK_DIV_POS     (12U)
+#define MM_GLB_REG_CNN_CLK_DIV_LEN     (3U)
+#define MM_GLB_REG_CNN_CLK_DIV_MSK     (((1U << MM_GLB_REG_CNN_CLK_DIV_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_POS)
+#define MM_GLB_REG_CNN_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_CNN_CLK_DIV_LEN) - 1) << MM_GLB_REG_CNN_CLK_DIV_POS))
+#define MM_GLB_REG_BCLK2X_DIV          MM_GLB_REG_BCLK2X_DIV
+#define MM_GLB_REG_BCLK2X_DIV_POS      (16U)
+#define MM_GLB_REG_BCLK2X_DIV_LEN      (8U)
+#define MM_GLB_REG_BCLK2X_DIV_MSK      (((1U << MM_GLB_REG_BCLK2X_DIV_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_POS)
+#define MM_GLB_REG_BCLK2X_DIV_UMSK     (~(((1U << MM_GLB_REG_BCLK2X_DIV_LEN) - 1) << MM_GLB_REG_BCLK2X_DIV_POS))
+#define MM_GLB_REG_BCLK1X_DIV          MM_GLB_REG_BCLK1X_DIV
+#define MM_GLB_REG_BCLK1X_DIV_POS      (24U)
+#define MM_GLB_REG_BCLK1X_DIV_LEN      (8U)
+#define MM_GLB_REG_BCLK1X_DIV_MSK      (((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS)
+#define MM_GLB_REG_BCLK1X_DIV_UMSK     (~(((1U << MM_GLB_REG_BCLK1X_DIV_LEN) - 1) << MM_GLB_REG_BCLK1X_DIV_POS))
+
+/* 0x8 : dp_clk */
+#define MM_GLB_DP_CLK_OFFSET          (0x8)
+#define MM_GLB_REG_CLK_DIV_EN         MM_GLB_REG_CLK_DIV_EN
+#define MM_GLB_REG_CLK_DIV_EN_POS     (0U)
+#define MM_GLB_REG_CLK_DIV_EN_LEN     (1U)
+#define MM_GLB_REG_CLK_DIV_EN_MSK     (((1U << MM_GLB_REG_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CLK_DIV_EN_POS)
+#define MM_GLB_REG_CLK_DIV_EN_UMSK    (~(((1U << MM_GLB_REG_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_CLK_DIV_EN_POS))
+#define MM_GLB_REG_CLK_SEL            MM_GLB_REG_CLK_SEL
+#define MM_GLB_REG_CLK_SEL_POS        (1U)
+#define MM_GLB_REG_CLK_SEL_LEN        (2U)
+#define MM_GLB_REG_CLK_SEL_MSK        (((1U << MM_GLB_REG_CLK_SEL_LEN) - 1) << MM_GLB_REG_CLK_SEL_POS)
+#define MM_GLB_REG_CLK_SEL_UMSK       (~(((1U << MM_GLB_REG_CLK_SEL_LEN) - 1) << MM_GLB_REG_CLK_SEL_POS))
+#define MM_GLB_REG_CLK_DIV            MM_GLB_REG_CLK_DIV
+#define MM_GLB_REG_CLK_DIV_POS        (8U)
+#define MM_GLB_REG_CLK_DIV_LEN        (8U)
+#define MM_GLB_REG_CLK_DIV_MSK        (((1U << MM_GLB_REG_CLK_DIV_LEN) - 1) << MM_GLB_REG_CLK_DIV_POS)
+#define MM_GLB_REG_CLK_DIV_UMSK       (~(((1U << MM_GLB_REG_CLK_DIV_LEN) - 1) << MM_GLB_REG_CLK_DIV_POS))
+#define MM_GLB_REG_DP_CLK_DIV_EN      MM_GLB_REG_DP_CLK_DIV_EN
+#define MM_GLB_REG_DP_CLK_DIV_EN_POS  (16U)
+#define MM_GLB_REG_DP_CLK_DIV_EN_LEN  (1U)
+#define MM_GLB_REG_DP_CLK_DIV_EN_MSK  (((1U << MM_GLB_REG_DP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_EN_POS)
+#define MM_GLB_REG_DP_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_DP_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_EN_POS))
+#define MM_GLB_REG_DP_CLK_SEL         MM_GLB_REG_DP_CLK_SEL
+#define MM_GLB_REG_DP_CLK_SEL_POS     (17U)
+#define MM_GLB_REG_DP_CLK_SEL_LEN     (1U)
+#define MM_GLB_REG_DP_CLK_SEL_MSK     (((1U << MM_GLB_REG_DP_CLK_SEL_LEN) - 1) << MM_GLB_REG_DP_CLK_SEL_POS)
+#define MM_GLB_REG_DP_CLK_SEL_UMSK    (~(((1U << MM_GLB_REG_DP_CLK_SEL_LEN) - 1) << MM_GLB_REG_DP_CLK_SEL_POS))
+#define MM_GLB_REG_DP_CLK_DIV         MM_GLB_REG_DP_CLK_DIV
+#define MM_GLB_REG_DP_CLK_DIV_POS     (20U)
+#define MM_GLB_REG_DP_CLK_DIV_LEN     (4U)
+#define MM_GLB_REG_DP_CLK_DIV_MSK     (((1U << MM_GLB_REG_DP_CLK_DIV_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_POS)
+#define MM_GLB_REG_DP_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_DP_CLK_DIV_LEN) - 1) << MM_GLB_REG_DP_CLK_DIV_POS))
+
+/* 0xC : codec_clk */
+#define MM_GLB_CODEC_CLK_OFFSET         (0xC)
+#define MM_GLB_REG_H264_CLK_DIV_EN      MM_GLB_REG_H264_CLK_DIV_EN
+#define MM_GLB_REG_H264_CLK_DIV_EN_POS  (8U)
+#define MM_GLB_REG_H264_CLK_DIV_EN_LEN  (1U)
+#define MM_GLB_REG_H264_CLK_DIV_EN_MSK  (((1U << MM_GLB_REG_H264_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_EN_POS)
+#define MM_GLB_REG_H264_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_H264_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_EN_POS))
+#define MM_GLB_REG_H264_CLK_SEL         MM_GLB_REG_H264_CLK_SEL
+#define MM_GLB_REG_H264_CLK_SEL_POS     (9U)
+#define MM_GLB_REG_H264_CLK_SEL_LEN     (2U)
+#define MM_GLB_REG_H264_CLK_SEL_MSK     (((1U << MM_GLB_REG_H264_CLK_SEL_LEN) - 1) << MM_GLB_REG_H264_CLK_SEL_POS)
+#define MM_GLB_REG_H264_CLK_SEL_UMSK    (~(((1U << MM_GLB_REG_H264_CLK_SEL_LEN) - 1) << MM_GLB_REG_H264_CLK_SEL_POS))
+#define MM_GLB_REG_H264_CLK_DIV         MM_GLB_REG_H264_CLK_DIV
+#define MM_GLB_REG_H264_CLK_DIV_POS     (12U)
+#define MM_GLB_REG_H264_CLK_DIV_LEN     (3U)
+#define MM_GLB_REG_H264_CLK_DIV_MSK     (((1U << MM_GLB_REG_H264_CLK_DIV_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_POS)
+#define MM_GLB_REG_H264_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_H264_CLK_DIV_LEN) - 1) << MM_GLB_REG_H264_CLK_DIV_POS))
+
+/* 0x10 : mm_clk_ctrl_peri */
+#define MM_GLB_MM_CLK_CTRL_PERI_OFFSET   (0x10)
+#define MM_GLB_REG_I2C0_CLK_DIV          MM_GLB_REG_I2C0_CLK_DIV
+#define MM_GLB_REG_I2C0_CLK_DIV_POS      (0U)
+#define MM_GLB_REG_I2C0_CLK_DIV_LEN      (8U)
+#define MM_GLB_REG_I2C0_CLK_DIV_MSK      (((1U << MM_GLB_REG_I2C0_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_POS)
+#define MM_GLB_REG_I2C0_CLK_DIV_UMSK     (~(((1U << MM_GLB_REG_I2C0_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_POS))
+#define MM_GLB_REG_I2C0_CLK_DIV_EN       MM_GLB_REG_I2C0_CLK_DIV_EN
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_POS   (8U)
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_LEN   (1U)
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_MSK   (((1U << MM_GLB_REG_I2C0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_EN_POS)
+#define MM_GLB_REG_I2C0_CLK_DIV_EN_UMSK  (~(((1U << MM_GLB_REG_I2C0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_DIV_EN_POS))
+#define MM_GLB_REG_I2C0_CLK_EN           MM_GLB_REG_I2C0_CLK_EN
+#define MM_GLB_REG_I2C0_CLK_EN_POS       (9U)
+#define MM_GLB_REG_I2C0_CLK_EN_LEN       (1U)
+#define MM_GLB_REG_I2C0_CLK_EN_MSK       (((1U << MM_GLB_REG_I2C0_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_EN_POS)
+#define MM_GLB_REG_I2C0_CLK_EN_UMSK      (~(((1U << MM_GLB_REG_I2C0_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C0_CLK_EN_POS))
+#define MM_GLB_REG_UART0_CLK_DIV_EN      MM_GLB_REG_UART0_CLK_DIV_EN
+#define MM_GLB_REG_UART0_CLK_DIV_EN_POS  (16U)
+#define MM_GLB_REG_UART0_CLK_DIV_EN_LEN  (1U)
+#define MM_GLB_REG_UART0_CLK_DIV_EN_MSK  (((1U << MM_GLB_REG_UART0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_EN_POS)
+#define MM_GLB_REG_UART0_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_UART0_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_EN_POS))
+#define MM_GLB_REG_UART0_CLK_DIV         MM_GLB_REG_UART0_CLK_DIV
+#define MM_GLB_REG_UART0_CLK_DIV_POS     (17U)
+#define MM_GLB_REG_UART0_CLK_DIV_LEN     (3U)
+#define MM_GLB_REG_UART0_CLK_DIV_MSK     (((1U << MM_GLB_REG_UART0_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_POS)
+#define MM_GLB_REG_UART0_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_UART0_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART0_CLK_DIV_POS))
+#define MM_GLB_REG_SPI_CLK_DIV_EN        MM_GLB_REG_SPI_CLK_DIV_EN
+#define MM_GLB_REG_SPI_CLK_DIV_EN_POS    (23U)
+#define MM_GLB_REG_SPI_CLK_DIV_EN_LEN    (1U)
+#define MM_GLB_REG_SPI_CLK_DIV_EN_MSK    (((1U << MM_GLB_REG_SPI_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_EN_POS)
+#define MM_GLB_REG_SPI_CLK_DIV_EN_UMSK   (~(((1U << MM_GLB_REG_SPI_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_EN_POS))
+#define MM_GLB_REG_SPI_CLK_DIV           MM_GLB_REG_SPI_CLK_DIV
+#define MM_GLB_REG_SPI_CLK_DIV_POS       (24U)
+#define MM_GLB_REG_SPI_CLK_DIV_LEN       (8U)
+#define MM_GLB_REG_SPI_CLK_DIV_MSK       (((1U << MM_GLB_REG_SPI_CLK_DIV_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_POS)
+#define MM_GLB_REG_SPI_CLK_DIV_UMSK      (~(((1U << MM_GLB_REG_SPI_CLK_DIV_LEN) - 1) << MM_GLB_REG_SPI_CLK_DIV_POS))
+
+/* 0x18 : mm_clk_ctrl_peri3 */
+#define MM_GLB_MM_CLK_CTRL_PERI3_OFFSET  (0x18)
+#define MM_GLB_REG_I2C1_CLK_DIV          MM_GLB_REG_I2C1_CLK_DIV
+#define MM_GLB_REG_I2C1_CLK_DIV_POS      (0U)
+#define MM_GLB_REG_I2C1_CLK_DIV_LEN      (8U)
+#define MM_GLB_REG_I2C1_CLK_DIV_MSK      (((1U << MM_GLB_REG_I2C1_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_POS)
+#define MM_GLB_REG_I2C1_CLK_DIV_UMSK     (~(((1U << MM_GLB_REG_I2C1_CLK_DIV_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_POS))
+#define MM_GLB_REG_I2C1_CLK_DIV_EN       MM_GLB_REG_I2C1_CLK_DIV_EN
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_POS   (8U)
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_LEN   (1U)
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_MSK   (((1U << MM_GLB_REG_I2C1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_EN_POS)
+#define MM_GLB_REG_I2C1_CLK_DIV_EN_UMSK  (~(((1U << MM_GLB_REG_I2C1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_DIV_EN_POS))
+#define MM_GLB_REG_I2C1_CLK_EN           MM_GLB_REG_I2C1_CLK_EN
+#define MM_GLB_REG_I2C1_CLK_EN_POS       (9U)
+#define MM_GLB_REG_I2C1_CLK_EN_LEN       (1U)
+#define MM_GLB_REG_I2C1_CLK_EN_MSK       (((1U << MM_GLB_REG_I2C1_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_EN_POS)
+#define MM_GLB_REG_I2C1_CLK_EN_UMSK      (~(((1U << MM_GLB_REG_I2C1_CLK_EN_LEN) - 1) << MM_GLB_REG_I2C1_CLK_EN_POS))
+#define MM_GLB_REG_UART1_CLK_DIV_EN      MM_GLB_REG_UART1_CLK_DIV_EN
+#define MM_GLB_REG_UART1_CLK_DIV_EN_POS  (16U)
+#define MM_GLB_REG_UART1_CLK_DIV_EN_LEN  (1U)
+#define MM_GLB_REG_UART1_CLK_DIV_EN_MSK  (((1U << MM_GLB_REG_UART1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_EN_POS)
+#define MM_GLB_REG_UART1_CLK_DIV_EN_UMSK (~(((1U << MM_GLB_REG_UART1_CLK_DIV_EN_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_EN_POS))
+#define MM_GLB_REG_UART1_CLK_DIV         MM_GLB_REG_UART1_CLK_DIV
+#define MM_GLB_REG_UART1_CLK_DIV_POS     (17U)
+#define MM_GLB_REG_UART1_CLK_DIV_LEN     (3U)
+#define MM_GLB_REG_UART1_CLK_DIV_MSK     (((1U << MM_GLB_REG_UART1_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_POS)
+#define MM_GLB_REG_UART1_CLK_DIV_UMSK    (~(((1U << MM_GLB_REG_UART1_CLK_DIV_LEN) - 1) << MM_GLB_REG_UART1_CLK_DIV_POS))
+
+/* 0x40 : mm_sw_sys_reset */
+#define MM_GLB_MM_SW_SYS_RESET_OFFSET     (0x40)
+#define MM_GLB_REG_CTRL_SYS_RESET         MM_GLB_REG_CTRL_SYS_RESET
+#define MM_GLB_REG_CTRL_SYS_RESET_POS     (0U)
+#define MM_GLB_REG_CTRL_SYS_RESET_LEN     (1U)
+#define MM_GLB_REG_CTRL_SYS_RESET_MSK     (((1U << MM_GLB_REG_CTRL_SYS_RESET_LEN) - 1) << MM_GLB_REG_CTRL_SYS_RESET_POS)
+#define MM_GLB_REG_CTRL_SYS_RESET_UMSK    (~(((1U << MM_GLB_REG_CTRL_SYS_RESET_LEN) - 1) << MM_GLB_REG_CTRL_SYS_RESET_POS))
+#define MM_GLB_REG_CTRL_PWRON_RST         MM_GLB_REG_CTRL_PWRON_RST
+#define MM_GLB_REG_CTRL_PWRON_RST_POS     (2U)
+#define MM_GLB_REG_CTRL_PWRON_RST_LEN     (1U)
+#define MM_GLB_REG_CTRL_PWRON_RST_MSK     (((1U << MM_GLB_REG_CTRL_PWRON_RST_LEN) - 1) << MM_GLB_REG_CTRL_PWRON_RST_POS)
+#define MM_GLB_REG_CTRL_PWRON_RST_UMSK    (~(((1U << MM_GLB_REG_CTRL_PWRON_RST_LEN) - 1) << MM_GLB_REG_CTRL_PWRON_RST_POS))
+#define MM_GLB_REG_CTRL_MMCPU0_RESET      MM_GLB_REG_CTRL_MMCPU0_RESET
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_POS  (8U)
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_LEN  (1U)
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_MSK  (((1U << MM_GLB_REG_CTRL_MMCPU0_RESET_LEN) - 1) << MM_GLB_REG_CTRL_MMCPU0_RESET_POS)
+#define MM_GLB_REG_CTRL_MMCPU0_RESET_UMSK (~(((1U << MM_GLB_REG_CTRL_MMCPU0_RESET_LEN) - 1) << MM_GLB_REG_CTRL_MMCPU0_RESET_POS))
+
+/* 0x44 : sw_reset_mm_peri */
+#define MM_GLB_SW_RESET_MM_PERI_OFFSET (0x44)
+#define MM_GLB_SWRST_MM_MISC           MM_GLB_SWRST_MM_MISC
+#define MM_GLB_SWRST_MM_MISC_POS       (0U)
+#define MM_GLB_SWRST_MM_MISC_LEN       (1U)
+#define MM_GLB_SWRST_MM_MISC_MSK       (((1U << MM_GLB_SWRST_MM_MISC_LEN) - 1) << MM_GLB_SWRST_MM_MISC_POS)
+#define MM_GLB_SWRST_MM_MISC_UMSK      (~(((1U << MM_GLB_SWRST_MM_MISC_LEN) - 1) << MM_GLB_SWRST_MM_MISC_POS))
+#define MM_GLB_SWRST_DMA               MM_GLB_SWRST_DMA
+#define MM_GLB_SWRST_DMA_POS           (1U)
+#define MM_GLB_SWRST_DMA_LEN           (1U)
+#define MM_GLB_SWRST_DMA_MSK           (((1U << MM_GLB_SWRST_DMA_LEN) - 1) << MM_GLB_SWRST_DMA_POS)
+#define MM_GLB_SWRST_DMA_UMSK          (~(((1U << MM_GLB_SWRST_DMA_LEN) - 1) << MM_GLB_SWRST_DMA_POS))
+#define MM_GLB_SWRST_UART0             MM_GLB_SWRST_UART0
+#define MM_GLB_SWRST_UART0_POS         (2U)
+#define MM_GLB_SWRST_UART0_LEN         (1U)
+#define MM_GLB_SWRST_UART0_MSK         (((1U << MM_GLB_SWRST_UART0_LEN) - 1) << MM_GLB_SWRST_UART0_POS)
+#define MM_GLB_SWRST_UART0_UMSK        (~(((1U << MM_GLB_SWRST_UART0_LEN) - 1) << MM_GLB_SWRST_UART0_POS))
+#define MM_GLB_SWRST_I2C0              MM_GLB_SWRST_I2C0
+#define MM_GLB_SWRST_I2C0_POS          (3U)
+#define MM_GLB_SWRST_I2C0_LEN          (1U)
+#define MM_GLB_SWRST_I2C0_MSK          (((1U << MM_GLB_SWRST_I2C0_LEN) - 1) << MM_GLB_SWRST_I2C0_POS)
+#define MM_GLB_SWRST_I2C0_UMSK         (~(((1U << MM_GLB_SWRST_I2C0_LEN) - 1) << MM_GLB_SWRST_I2C0_POS))
+#define MM_GLB_SWRST_I2C1              MM_GLB_SWRST_I2C1
+#define MM_GLB_SWRST_I2C1_POS          (4U)
+#define MM_GLB_SWRST_I2C1_LEN          (1U)
+#define MM_GLB_SWRST_I2C1_MSK          (((1U << MM_GLB_SWRST_I2C1_LEN) - 1) << MM_GLB_SWRST_I2C1_POS)
+#define MM_GLB_SWRST_I2C1_UMSK         (~(((1U << MM_GLB_SWRST_I2C1_LEN) - 1) << MM_GLB_SWRST_I2C1_POS))
+#define MM_GLB_SWRST_IPC               MM_GLB_SWRST_IPC
+#define MM_GLB_SWRST_IPC_POS           (5U)
+#define MM_GLB_SWRST_IPC_LEN           (1U)
+#define MM_GLB_SWRST_IPC_MSK           (((1U << MM_GLB_SWRST_IPC_LEN) - 1) << MM_GLB_SWRST_IPC_POS)
+#define MM_GLB_SWRST_IPC_UMSK          (~(((1U << MM_GLB_SWRST_IPC_LEN) - 1) << MM_GLB_SWRST_IPC_POS))
+#define MM_GLB_SWRST_DMA2D             MM_GLB_SWRST_DMA2D
+#define MM_GLB_SWRST_DMA2D_POS         (6U)
+#define MM_GLB_SWRST_DMA2D_LEN         (1U)
+#define MM_GLB_SWRST_DMA2D_MSK         (((1U << MM_GLB_SWRST_DMA2D_LEN) - 1) << MM_GLB_SWRST_DMA2D_POS)
+#define MM_GLB_SWRST_DMA2D_UMSK        (~(((1U << MM_GLB_SWRST_DMA2D_LEN) - 1) << MM_GLB_SWRST_DMA2D_POS))
+#define MM_GLB_SWRST_SPI               MM_GLB_SWRST_SPI
+#define MM_GLB_SWRST_SPI_POS           (8U)
+#define MM_GLB_SWRST_SPI_LEN           (1U)
+#define MM_GLB_SWRST_SPI_MSK           (((1U << MM_GLB_SWRST_SPI_LEN) - 1) << MM_GLB_SWRST_SPI_POS)
+#define MM_GLB_SWRST_SPI_UMSK          (~(((1U << MM_GLB_SWRST_SPI_LEN) - 1) << MM_GLB_SWRST_SPI_POS))
+#define MM_GLB_SWRST_TIMER             MM_GLB_SWRST_TIMER
+#define MM_GLB_SWRST_TIMER_POS         (9U)
+#define MM_GLB_SWRST_TIMER_LEN         (1U)
+#define MM_GLB_SWRST_TIMER_MSK         (((1U << MM_GLB_SWRST_TIMER_LEN) - 1) << MM_GLB_SWRST_TIMER_POS)
+#define MM_GLB_SWRST_TIMER_UMSK        (~(((1U << MM_GLB_SWRST_TIMER_LEN) - 1) << MM_GLB_SWRST_TIMER_POS))
+#define MM_GLB_SWRST_I2S0              MM_GLB_SWRST_I2S0
+#define MM_GLB_SWRST_I2S0_POS          (10U)
+#define MM_GLB_SWRST_I2S0_LEN          (1U)
+#define MM_GLB_SWRST_I2S0_MSK          (((1U << MM_GLB_SWRST_I2S0_LEN) - 1) << MM_GLB_SWRST_I2S0_POS)
+#define MM_GLB_SWRST_I2S0_UMSK         (~(((1U << MM_GLB_SWRST_I2S0_LEN) - 1) << MM_GLB_SWRST_I2S0_POS))
+#define MM_GLB_SWRST_I2S1              MM_GLB_SWRST_I2S1
+#define MM_GLB_SWRST_I2S1_POS          (11U)
+#define MM_GLB_SWRST_I2S1_LEN          (1U)
+#define MM_GLB_SWRST_I2S1_MSK          (((1U << MM_GLB_SWRST_I2S1_LEN) - 1) << MM_GLB_SWRST_I2S1_POS)
+#define MM_GLB_SWRST_I2S1_UMSK         (~(((1U << MM_GLB_SWRST_I2S1_LEN) - 1) << MM_GLB_SWRST_I2S1_POS))
+#define MM_GLB_SWRST_PDM0              MM_GLB_SWRST_PDM0
+#define MM_GLB_SWRST_PDM0_POS          (12U)
+#define MM_GLB_SWRST_PDM0_LEN          (1U)
+#define MM_GLB_SWRST_PDM0_MSK          (((1U << MM_GLB_SWRST_PDM0_LEN) - 1) << MM_GLB_SWRST_PDM0_POS)
+#define MM_GLB_SWRST_PDM0_UMSK         (~(((1U << MM_GLB_SWRST_PDM0_LEN) - 1) << MM_GLB_SWRST_PDM0_POS))
+#define MM_GLB_SWRST_PDM1              MM_GLB_SWRST_PDM1
+#define MM_GLB_SWRST_PDM1_POS          (13U)
+#define MM_GLB_SWRST_PDM1_LEN          (1U)
+#define MM_GLB_SWRST_PDM1_MSK          (((1U << MM_GLB_SWRST_PDM1_LEN) - 1) << MM_GLB_SWRST_PDM1_POS)
+#define MM_GLB_SWRST_PDM1_UMSK         (~(((1U << MM_GLB_SWRST_PDM1_LEN) - 1) << MM_GLB_SWRST_PDM1_POS))
+#define MM_GLB_SWRST_UART1             MM_GLB_SWRST_UART1
+#define MM_GLB_SWRST_UART1_POS         (14U)
+#define MM_GLB_SWRST_UART1_LEN         (1U)
+#define MM_GLB_SWRST_UART1_MSK         (((1U << MM_GLB_SWRST_UART1_LEN) - 1) << MM_GLB_SWRST_UART1_POS)
+#define MM_GLB_SWRST_UART1_UMSK        (~(((1U << MM_GLB_SWRST_UART1_LEN) - 1) << MM_GLB_SWRST_UART1_POS))
+#define MM_GLB_SWRST_PUHS              MM_GLB_SWRST_PUHS
+#define MM_GLB_SWRST_PUHS_POS          (15U)
+#define MM_GLB_SWRST_PUHS_LEN          (1U)
+#define MM_GLB_SWRST_PUHS_MSK          (((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS)
+#define MM_GLB_SWRST_PUHS_UMSK         (~(((1U << MM_GLB_SWRST_PUHS_LEN) - 1) << MM_GLB_SWRST_PUHS_POS))
+
+/* 0x48 : sw_reset_sub */
+#define MM_GLB_SW_RESET_SUB_OFFSET  (0x48)
+#define MM_GLB_SWRST_MISC           MM_GLB_SWRST_MISC
+#define MM_GLB_SWRST_MISC_POS       (0U)
+#define MM_GLB_SWRST_MISC_LEN       (1U)
+#define MM_GLB_SWRST_MISC_MSK       (((1U << MM_GLB_SWRST_MISC_LEN) - 1) << MM_GLB_SWRST_MISC_POS)
+#define MM_GLB_SWRST_MISC_UMSK      (~(((1U << MM_GLB_SWRST_MISC_LEN) - 1) << MM_GLB_SWRST_MISC_POS))
+#define MM_GLB_SWRST_MAIN           MM_GLB_SWRST_MAIN
+#define MM_GLB_SWRST_MAIN_POS       (1U)
+#define MM_GLB_SWRST_MAIN_LEN       (1U)
+#define MM_GLB_SWRST_MAIN_MSK       (((1U << MM_GLB_SWRST_MAIN_LEN) - 1) << MM_GLB_SWRST_MAIN_POS)
+#define MM_GLB_SWRST_MAIN_UMSK      (~(((1U << MM_GLB_SWRST_MAIN_LEN) - 1) << MM_GLB_SWRST_MAIN_POS))
+#define MM_GLB_SWRST_TSRC           MM_GLB_SWRST_TSRC
+#define MM_GLB_SWRST_TSRC_POS       (2U)
+#define MM_GLB_SWRST_TSRC_LEN       (1U)
+#define MM_GLB_SWRST_TSRC_MSK       (((1U << MM_GLB_SWRST_TSRC_LEN) - 1) << MM_GLB_SWRST_TSRC_POS)
+#define MM_GLB_SWRST_TSRC_UMSK      (~(((1U << MM_GLB_SWRST_TSRC_LEN) - 1) << MM_GLB_SWRST_TSRC_POS))
+#define MM_GLB_SWRST_DP_TSRC        MM_GLB_SWRST_DP_TSRC
+#define MM_GLB_SWRST_DP_TSRC_POS    (3U)
+#define MM_GLB_SWRST_DP_TSRC_LEN    (1U)
+#define MM_GLB_SWRST_DP_TSRC_MSK    (((1U << MM_GLB_SWRST_DP_TSRC_LEN) - 1) << MM_GLB_SWRST_DP_TSRC_POS)
+#define MM_GLB_SWRST_DP_TSRC_UMSK   (~(((1U << MM_GLB_SWRST_DP_TSRC_LEN) - 1) << MM_GLB_SWRST_DP_TSRC_POS))
+#define MM_GLB_SWRST_NR3D_CTRL      MM_GLB_SWRST_NR3D_CTRL
+#define MM_GLB_SWRST_NR3D_CTRL_POS  (4U)
+#define MM_GLB_SWRST_NR3D_CTRL_LEN  (1U)
+#define MM_GLB_SWRST_NR3D_CTRL_MSK  (((1U << MM_GLB_SWRST_NR3D_CTRL_LEN) - 1) << MM_GLB_SWRST_NR3D_CTRL_POS)
+#define MM_GLB_SWRST_NR3D_CTRL_UMSK (~(((1U << MM_GLB_SWRST_NR3D_CTRL_LEN) - 1) << MM_GLB_SWRST_NR3D_CTRL_POS))
+#define MM_GLB_SWRST_DVP2BUSA       MM_GLB_SWRST_DVP2BUSA
+#define MM_GLB_SWRST_DVP2BUSA_POS   (5U)
+#define MM_GLB_SWRST_DVP2BUSA_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSA_MSK   (((1U << MM_GLB_SWRST_DVP2BUSA_LEN) - 1) << MM_GLB_SWRST_DVP2BUSA_POS)
+#define MM_GLB_SWRST_DVP2BUSA_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSA_LEN) - 1) << MM_GLB_SWRST_DVP2BUSA_POS))
+#define MM_GLB_SWRST_DVP2BUSB       MM_GLB_SWRST_DVP2BUSB
+#define MM_GLB_SWRST_DVP2BUSB_POS   (6U)
+#define MM_GLB_SWRST_DVP2BUSB_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSB_MSK   (((1U << MM_GLB_SWRST_DVP2BUSB_LEN) - 1) << MM_GLB_SWRST_DVP2BUSB_POS)
+#define MM_GLB_SWRST_DVP2BUSB_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSB_LEN) - 1) << MM_GLB_SWRST_DVP2BUSB_POS))
+#define MM_GLB_SWRST_DVP2BUSC       MM_GLB_SWRST_DVP2BUSC
+#define MM_GLB_SWRST_DVP2BUSC_POS   (7U)
+#define MM_GLB_SWRST_DVP2BUSC_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSC_MSK   (((1U << MM_GLB_SWRST_DVP2BUSC_LEN) - 1) << MM_GLB_SWRST_DVP2BUSC_POS)
+#define MM_GLB_SWRST_DVP2BUSC_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSC_LEN) - 1) << MM_GLB_SWRST_DVP2BUSC_POS))
+#define MM_GLB_SWRST_DVP2BUSD       MM_GLB_SWRST_DVP2BUSD
+#define MM_GLB_SWRST_DVP2BUSD_POS   (8U)
+#define MM_GLB_SWRST_DVP2BUSD_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSD_MSK   (((1U << MM_GLB_SWRST_DVP2BUSD_LEN) - 1) << MM_GLB_SWRST_DVP2BUSD_POS)
+#define MM_GLB_SWRST_DVP2BUSD_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSD_LEN) - 1) << MM_GLB_SWRST_DVP2BUSD_POS))
+#define MM_GLB_SWRST_MIPI           MM_GLB_SWRST_MIPI
+#define MM_GLB_SWRST_MIPI_POS       (9U)
+#define MM_GLB_SWRST_MIPI_LEN       (1U)
+#define MM_GLB_SWRST_MIPI_MSK       (((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS)
+#define MM_GLB_SWRST_MIPI_UMSK      (~(((1U << MM_GLB_SWRST_MIPI_LEN) - 1) << MM_GLB_SWRST_MIPI_POS))
+#define MM_GLB_SWRST_DVP2BUSE       MM_GLB_SWRST_DVP2BUSE
+#define MM_GLB_SWRST_DVP2BUSE_POS   (17U)
+#define MM_GLB_SWRST_DVP2BUSE_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSE_MSK   (((1U << MM_GLB_SWRST_DVP2BUSE_LEN) - 1) << MM_GLB_SWRST_DVP2BUSE_POS)
+#define MM_GLB_SWRST_DVP2BUSE_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSE_LEN) - 1) << MM_GLB_SWRST_DVP2BUSE_POS))
+#define MM_GLB_SWRST_DVP2BUSF       MM_GLB_SWRST_DVP2BUSF
+#define MM_GLB_SWRST_DVP2BUSF_POS   (18U)
+#define MM_GLB_SWRST_DVP2BUSF_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSF_MSK   (((1U << MM_GLB_SWRST_DVP2BUSF_LEN) - 1) << MM_GLB_SWRST_DVP2BUSF_POS)
+#define MM_GLB_SWRST_DVP2BUSF_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSF_LEN) - 1) << MM_GLB_SWRST_DVP2BUSF_POS))
+#define MM_GLB_SWRST_DVP2BUSG       MM_GLB_SWRST_DVP2BUSG
+#define MM_GLB_SWRST_DVP2BUSG_POS   (19U)
+#define MM_GLB_SWRST_DVP2BUSG_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSG_MSK   (((1U << MM_GLB_SWRST_DVP2BUSG_LEN) - 1) << MM_GLB_SWRST_DVP2BUSG_POS)
+#define MM_GLB_SWRST_DVP2BUSG_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSG_LEN) - 1) << MM_GLB_SWRST_DVP2BUSG_POS))
+#define MM_GLB_SWRST_DVP2BUSH       MM_GLB_SWRST_DVP2BUSH
+#define MM_GLB_SWRST_DVP2BUSH_POS   (20U)
+#define MM_GLB_SWRST_DVP2BUSH_LEN   (1U)
+#define MM_GLB_SWRST_DVP2BUSH_MSK   (((1U << MM_GLB_SWRST_DVP2BUSH_LEN) - 1) << MM_GLB_SWRST_DVP2BUSH_POS)
+#define MM_GLB_SWRST_DVP2BUSH_UMSK  (~(((1U << MM_GLB_SWRST_DVP2BUSH_LEN) - 1) << MM_GLB_SWRST_DVP2BUSH_POS))
+
+/* 0x4C : sw_reset_codec_sub */
+#define MM_GLB_SW_RESET_CODEC_SUB_OFFSET (0x4C)
+#define MM_GLB_SWRST_CODEC_MISC          MM_GLB_SWRST_CODEC_MISC
+#define MM_GLB_SWRST_CODEC_MISC_POS      (0U)
+#define MM_GLB_SWRST_CODEC_MISC_LEN      (1U)
+#define MM_GLB_SWRST_CODEC_MISC_MSK      (((1U << MM_GLB_SWRST_CODEC_MISC_LEN) - 1) << MM_GLB_SWRST_CODEC_MISC_POS)
+#define MM_GLB_SWRST_CODEC_MISC_UMSK     (~(((1U << MM_GLB_SWRST_CODEC_MISC_LEN) - 1) << MM_GLB_SWRST_CODEC_MISC_POS))
+#define MM_GLB_SWRST_MJPEG               MM_GLB_SWRST_MJPEG
+#define MM_GLB_SWRST_MJPEG_POS           (1U)
+#define MM_GLB_SWRST_MJPEG_LEN           (1U)
+#define MM_GLB_SWRST_MJPEG_MSK           (((1U << MM_GLB_SWRST_MJPEG_LEN) - 1) << MM_GLB_SWRST_MJPEG_POS)
+#define MM_GLB_SWRST_MJPEG_UMSK          (~(((1U << MM_GLB_SWRST_MJPEG_LEN) - 1) << MM_GLB_SWRST_MJPEG_POS))
+#define MM_GLB_SWRST_H264                MM_GLB_SWRST_H264
+#define MM_GLB_SWRST_H264_POS            (2U)
+#define MM_GLB_SWRST_H264_LEN            (1U)
+#define MM_GLB_SWRST_H264_MSK            (((1U << MM_GLB_SWRST_H264_LEN) - 1) << MM_GLB_SWRST_H264_POS)
+#define MM_GLB_SWRST_H264_UMSK           (~(((1U << MM_GLB_SWRST_H264_LEN) - 1) << MM_GLB_SWRST_H264_POS))
+#define MM_GLB_SWRST_MJPEG_DEC           MM_GLB_SWRST_MJPEG_DEC
+#define MM_GLB_SWRST_MJPEG_DEC_POS       (3U)
+#define MM_GLB_SWRST_MJPEG_DEC_LEN       (1U)
+#define MM_GLB_SWRST_MJPEG_DEC_MSK       (((1U << MM_GLB_SWRST_MJPEG_DEC_LEN) - 1) << MM_GLB_SWRST_MJPEG_DEC_POS)
+#define MM_GLB_SWRST_MJPEG_DEC_UMSK      (~(((1U << MM_GLB_SWRST_MJPEG_DEC_LEN) - 1) << MM_GLB_SWRST_MJPEG_DEC_POS))
+#define MM_GLB_SWRST_CNN                 MM_GLB_SWRST_CNN
+#define MM_GLB_SWRST_CNN_POS             (4U)
+#define MM_GLB_SWRST_CNN_LEN             (1U)
+#define MM_GLB_SWRST_CNN_MSK             (((1U << MM_GLB_SWRST_CNN_LEN) - 1) << MM_GLB_SWRST_CNN_POS)
+#define MM_GLB_SWRST_CNN_UMSK            (~(((1U << MM_GLB_SWRST_CNN_LEN) - 1) << MM_GLB_SWRST_CNN_POS))
+#define MM_GLB_SWRST_VRAM                MM_GLB_SWRST_VRAM
+#define MM_GLB_SWRST_VRAM_POS            (16U)
+#define MM_GLB_SWRST_VRAM_LEN            (1U)
+#define MM_GLB_SWRST_VRAM_MSK            (((1U << MM_GLB_SWRST_VRAM_LEN) - 1) << MM_GLB_SWRST_VRAM_POS)
+#define MM_GLB_SWRST_VRAM_UMSK           (~(((1U << MM_GLB_SWRST_VRAM_LEN) - 1) << MM_GLB_SWRST_VRAM_POS))
+
+/* 0x50 : image_sensor_ctrl */
+#define MM_GLB_IMAGE_SENSOR_CTRL_OFFSET (0x50)
+#define MM_GLB_RG_IS_RST_N              MM_GLB_RG_IS_RST_N
+#define MM_GLB_RG_IS_RST_N_POS          (0U)
+#define MM_GLB_RG_IS_RST_N_LEN          (1U)
+#define MM_GLB_RG_IS_RST_N_MSK          (((1U << MM_GLB_RG_IS_RST_N_LEN) - 1) << MM_GLB_RG_IS_RST_N_POS)
+#define MM_GLB_RG_IS_RST_N_UMSK         (~(((1U << MM_GLB_RG_IS_RST_N_LEN) - 1) << MM_GLB_RG_IS_RST_N_POS))
+
+/* 0x60 : tz_mm_clkrst */
+#define MM_GLB_TZ_MM_CLKRST_OFFSET         (0x60)
+#define MM_GLB_TZC_MM_SWRST_LOCK           MM_GLB_TZC_MM_SWRST_LOCK
+#define MM_GLB_TZC_MM_SWRST_LOCK_POS       (0U)
+#define MM_GLB_TZC_MM_SWRST_LOCK_LEN       (1U)
+#define MM_GLB_TZC_MM_SWRST_LOCK_MSK       (((1U << MM_GLB_TZC_MM_SWRST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SWRST_LOCK_POS)
+#define MM_GLB_TZC_MM_SWRST_LOCK_UMSK      (~(((1U << MM_GLB_TZC_MM_SWRST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SWRST_LOCK_POS))
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK       MM_GLB_TZC_MM_SYS_RESET_LOCK
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_POS   (1U)
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN   (1U)
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_MSK   (((1U << MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SYS_RESET_LOCK_POS)
+#define MM_GLB_TZC_MM_SYS_RESET_LOCK_UMSK  (~(((1U << MM_GLB_TZC_MM_SYS_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_SYS_RESET_LOCK_POS))
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK       MM_GLB_TZC_MM_PWRON_RST_LOCK
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_POS   (2U)
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN   (1U)
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_MSK   (((1U << MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_PWRON_RST_LOCK_POS)
+#define MM_GLB_TZC_MM_PWRON_RST_LOCK_UMSK  (~(((1U << MM_GLB_TZC_MM_PWRON_RST_LOCK_LEN) - 1) << MM_GLB_TZC_MM_PWRON_RST_LOCK_POS))
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK      MM_GLB_TZC_MM_CPU0_RESET_LOCK
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS  (3U)
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN  (1U)
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_MSK  (((1U << MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS)
+#define MM_GLB_TZC_MM_CPU0_RESET_LOCK_UMSK (~(((1U << MM_GLB_TZC_MM_CPU0_RESET_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CPU0_RESET_LOCK_POS))
+#define MM_GLB_TZC_MM_CLK_LOCK             MM_GLB_TZC_MM_CLK_LOCK
+#define MM_GLB_TZC_MM_CLK_LOCK_POS         (4U)
+#define MM_GLB_TZC_MM_CLK_LOCK_LEN         (1U)
+#define MM_GLB_TZC_MM_CLK_LOCK_MSK         (((1U << MM_GLB_TZC_MM_CLK_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CLK_LOCK_POS)
+#define MM_GLB_TZC_MM_CLK_LOCK_UMSK        (~(((1U << MM_GLB_TZC_MM_CLK_LOCK_LEN) - 1) << MM_GLB_TZC_MM_CLK_LOCK_POS))
+
+struct mm_glb_reg {
+    /* 0x0 : mm_clk_ctrl_cpu */
+    union {
+        struct {
+            uint32_t reg_pll_en               : 1; /* [    0],        r/w,        0x1 */
+            uint32_t reg_cpu_clk_en           : 1; /* [    1],        r/w,        0x1 */
+            uint32_t reg_bclk_en              : 1; /* [    2],        r/w,        0x1 */
+            uint32_t reg_mm_cpu_clk_en        : 1; /* [    3],        r/w,        0x1 */
+            uint32_t reg_uart_clk_sel         : 2; /* [ 5: 4],        r/w,        0x0 */
+            uint32_t reg_i2c_clk_sel          : 1; /* [    6],        r/w,        0x0 */
+            uint32_t reg_spi_clk_sel          : 1; /* [    7],        r/w,        0x0 */
+            uint32_t reg_cpu_clk_sel          : 2; /* [ 9: 8],        r/w,        0x0 */
+            uint32_t reg_xclk_clk_sel         : 1; /* [   10],        r/w,        0x0 */
+            uint32_t reg_cpu_root_clk_sel     : 1; /* [   11],        r/w,        0x0 */
+            uint32_t reg_mmcpu0_clk_en        : 1; /* [   12],        r/w,        0x0 */
+            uint32_t reg_bclk1x_sel           : 2; /* [14:13],        r/w,        0x0 */
+            uint32_t reserved_15_17           : 3; /* [17:15],       rsvd,        0x0 */
+            uint32_t reg_bclk2x_div_act_pulse : 1; /* [   18],        w1p,        0x0 */
+            uint32_t reg_bclk2x_div_bypass    : 1; /* [   19],        r/w,        0x0 */
+            uint32_t sts_bclk2x_prot_done     : 1; /* [   20],          r,        0x1 */
+            uint32_t reserved_21_23           : 3; /* [23:21],       rsvd,        0x0 */
+            uint32_t reg_bclk2x_sw_done_cnt   : 4; /* [27:24],        r/w,        0x5 */
+            uint32_t cpu_clk_sw_state         : 3; /* [30:28],          r,        0x0 */
+            uint32_t reserved_31              : 1; /* [   31],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mm_clk_ctrl_cpu;
+
+    /* 0x4 : mm_clk_cpu */
+    union {
+        struct {
+            uint32_t reg_cpu_clk_div    : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_cnn_clk_div_en : 1; /* [    8],        r/w,        0x1 */
+            uint32_t reg_cnn_clk_sel    : 2; /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11        : 1; /* [   11],       rsvd,        0x0 */
+            uint32_t reg_cnn_clk_div    : 3; /* [14:12],        r/w,        0x0 */
+            uint32_t reserved_15        : 1; /* [   15],       rsvd,        0x0 */
+            uint32_t reg_bclk2x_div     : 8; /* [23:16],        r/w,        0x0 */
+            uint32_t reg_bclk1x_div     : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mm_clk_cpu;
+
+    /* 0x8 : dp_clk */
+    union {
+        struct {
+            uint32_t reserved_0_15     : 16; /* [15: 0],       rsvd,        0x0 */
+            uint32_t reg_dp_clk_div_en : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_dp_clk_sel    : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t reserved_18_19    : 2;  /* [19:18],       rsvd,        0x0 */
+            uint32_t reg_dp_clk_div    : 4;  /* [23:20],        r/w,        0x0 */
+            uint32_t reserved_24_31    : 8;  /* [31:24],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } dp_clk;
+
+    /* 0xC : codec_clk */
+    union {
+        struct {
+            uint32_t reserved_0_7        : 8;  /* [ 7: 0],       rsvd,        0x0 */
+            uint32_t reg_h264_clk_div_en : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reg_h264_clk_sel    : 2;  /* [10: 9],        r/w,        0x0 */
+            uint32_t reserved_11         : 1;  /* [   11],       rsvd,        0x0 */
+            uint32_t reg_h264_clk_div    : 3;  /* [14:12],        r/w,        0x0 */
+            uint32_t reserved_15_31      : 17; /* [31:15],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } codec_clk;
+
+    /* 0x10 : mm_clk_ctrl_peri */
+    union {
+        struct {
+            uint32_t reg_i2c0_clk_div     : 8; /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_i2c0_clk_div_en  : 1; /* [    8],        r/w,        0x1 */
+            uint32_t reg_i2c0_clk_en      : 1; /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10_15       : 6; /* [15:10],       rsvd,        0x0 */
+            uint32_t reg_uart0_clk_div_en : 1; /* [   16],        r/w,        0x1 */
+            uint32_t reg_uart0_clk_div    : 3; /* [19:17],        r/w,        0x0 */
+            uint32_t reserved_20_22       : 3; /* [22:20],       rsvd,        0x0 */
+            uint32_t reg_spi_clk_div_en   : 1; /* [   23],        r/w,        0x1 */
+            uint32_t reg_spi_clk_div      : 8; /* [31:24],        r/w,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mm_clk_ctrl_peri;
+
+    /* 0x14  reserved */
+    uint8_t RESERVED0x14[4];
+
+    /* 0x18 : mm_clk_ctrl_peri3 */
+    union {
+        struct {
+            uint32_t reg_i2c1_clk_div     : 8;  /* [ 7: 0],        r/w,        0x0 */
+            uint32_t reg_i2c1_clk_div_en  : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reg_i2c1_clk_en      : 1;  /* [    9],        r/w,        0x1 */
+            uint32_t reserved_10_15       : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t reg_uart1_clk_div_en : 1;  /* [   16],        r/w,        0x1 */
+            uint32_t reg_uart1_clk_div    : 3;  /* [19:17],        r/w,        0x0 */
+            uint32_t reserved_20_31       : 12; /* [31:20],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mm_clk_ctrl_peri3;
+
+    /* 0x1c  reserved */
+    uint8_t RESERVED0x1c[36];
+
+    /* 0x40 : mm_sw_sys_reset */
+    union {
+        struct {
+            uint32_t reg_ctrl_sys_reset    : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t reserved_1            : 1;  /* [    1],       rsvd,        0x0 */
+            uint32_t reg_ctrl_pwron_rst    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t reserved_3_7          : 5;  /* [ 7: 3],       rsvd,        0x0 */
+            uint32_t reg_ctrl_mmcpu0_reset : 1;  /* [    8],        r/w,        0x1 */
+            uint32_t reserved_9_31         : 23; /* [31: 9],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } mm_sw_sys_reset;
+
+    /* 0x44 : sw_reset_mm_peri */
+    union {
+        struct {
+            uint32_t swrst_mm_misc  : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t swrst_dma      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t swrst_uart0    : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t swrst_i2c0     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t swrst_i2c1     : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t swrst_ipc      : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t swrst_dma2d    : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reserved_7     : 1;  /* [    7],       rsvd,        0x0 */
+            uint32_t swrst_spi      : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t swrst_timer    : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t swrst_i2s0     : 1;  /* [   10],        r/w,        0x0 */
+            uint32_t swrst_i2s1     : 1;  /* [   11],        r/w,        0x0 */
+            uint32_t swrst_pdm0     : 1;  /* [   12],        r/w,        0x0 */
+            uint32_t swrst_pdm1     : 1;  /* [   13],        r/w,        0x0 */
+            uint32_t swrst_uart1    : 1;  /* [   14],        r/w,        0x0 */
+            uint32_t swrst_pUHS     : 1;  /* [   15],        r/w,        0x0 */
+            uint32_t reserved_16_31 : 16; /* [31:16],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sw_reset_mm_peri;
+
+    /* 0x48 : sw_reset_sub */
+    union {
+        struct {
+            uint32_t swrst_misc      : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t swrst_main      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t swrst_tsrc      : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t swrst_dp_tsrc   : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t swrst_nr3d_ctrl : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t swrst_dvp2busA  : 1;  /* [    5],        r/w,        0x0 */
+            uint32_t swrst_dvp2busB  : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t swrst_dvp2busC  : 1;  /* [    7],        r/w,        0x0 */
+            uint32_t swrst_dvp2busD  : 1;  /* [    8],        r/w,        0x0 */
+            uint32_t swrst_mipi      : 1;  /* [    9],        r/w,        0x0 */
+            uint32_t reserved_10_15  : 6;  /* [15:10],       rsvd,        0x0 */
+            uint32_t swrst_reg       : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t swrst_dvp2busE  : 1;  /* [   17],        r/w,        0x0 */
+            uint32_t swrst_dvp2busF  : 1;  /* [   18],        r/w,        0x0 */
+            uint32_t swrst_dvp2busG  : 1;  /* [   19],        r/w,        0x0 */
+            uint32_t swrst_dvp2busH  : 1;  /* [   20],        r/w,        0x0 */
+            uint32_t reserved_21_31  : 11; /* [31:21],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sw_reset_sub;
+
+    /* 0x4C : sw_reset_codec_sub */
+    union {
+        struct {
+            uint32_t swrst_codec_misc : 1;  /* [    0],        r/w,        0x0 */
+            uint32_t swrst_mjpeg      : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t swrst_h264       : 1;  /* [    2],        r/w,        0x0 */
+            uint32_t swrst_mjpeg_dec  : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t swrst_cnn        : 1;  /* [    4],        r/w,        0x0 */
+            uint32_t reserved_5_15    : 11; /* [15: 5],       rsvd,        0x0 */
+            uint32_t swrst_vram       : 1;  /* [   16],        r/w,        0x0 */
+            uint32_t reserved_17_31   : 15; /* [31:17],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } sw_reset_codec_sub;
+
+    /* 0x50 : image_sensor_ctrl */
+    union {
+        struct {
+            uint32_t rg_is_rst_n   : 1;  /* [    0],        r/w,        0x1 */
+            uint32_t reserved_1_31 : 31; /* [31: 1],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } image_sensor_ctrl;
+
+    /* 0x54  reserved */
+    uint8_t RESERVED0x54[12];
+
+    /* 0x60 : tz_mm_clkrst */
+    union {
+        struct {
+            uint32_t tzc_mm_swrst_lock      : 1;  /* [    0],          r,        0x0 */
+            uint32_t tzc_mm_sys_reset_lock  : 1;  /* [    1],          r,        0x0 */
+            uint32_t tzc_mm_pwron_rst_lock  : 1;  /* [    2],          r,        0x0 */
+            uint32_t tzc_mm_cpu0_reset_lock : 1;  /* [    3],          r,        0x0 */
+            uint32_t tzc_mm_clk_lock        : 1;  /* [    4],          r,        0x0 */
+            uint32_t reserved_5_31          : 27; /* [31: 5],       rsvd,        0x0 */
+        } BF;
+        uint32_t WORD;
+    } tz_mm_clkrst;
+};
+
+typedef volatile struct mm_glb_reg mm_glb_reg_t;
+
+#endif /* __MM_GLB_REG_H__ */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mm_misc_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mm_misc_reg.h
old mode 100644
new mode 100755
similarity index 88%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mm_misc_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mm_misc_reg.h
index f7425e4481..fc07a350f9
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/mm_misc_reg.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/mm_misc_reg.h
@@ -143,11 +143,11 @@
 #define MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN  (1U)
 #define MM_MISC_REG_MMINFRA_BERR_INT_EN_MSK  (((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS)
 #define MM_MISC_REG_MMINFRA_BERR_INT_EN_UMSK (~(((1U << MM_MISC_REG_MMINFRA_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_INT_EN_POS))
-#define MM_MISC_REG_DSP2_BERR_INT_EN          MM_MISC_REG_DSP2_BERR_INT_EN
-#define MM_MISC_REG_DSP2_BERR_INT_EN_POS      (1U)
-#define MM_MISC_REG_DSP2_BERR_INT_EN_LEN      (1U)
-#define MM_MISC_REG_DSP2_BERR_INT_EN_MSK      (((1U << MM_MISC_REG_DSP2_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_DSP2_BERR_INT_EN_POS)
-#define MM_MISC_REG_DSP2_BERR_INT_EN_UMSK     (~(((1U << MM_MISC_REG_DSP2_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_DSP2_BERR_INT_EN_POS))
+#define MM_MISC_REG_BERR_INT_EN              MM_MISC_REG_BERR_INT_EN
+#define MM_MISC_REG_BERR_INT_EN_POS          (1U)
+#define MM_MISC_REG_BERR_INT_EN_LEN          (1U)
+#define MM_MISC_REG_BERR_INT_EN_MSK          (((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS)
+#define MM_MISC_REG_BERR_INT_EN_UMSK         (~(((1U << MM_MISC_REG_BERR_INT_EN_LEN) - 1) << MM_MISC_REG_BERR_INT_EN_POS))
 #define MM_MISC_REG_CODEC_BERR_INT_EN        MM_MISC_REG_CODEC_BERR_INT_EN
 #define MM_MISC_REG_CODEC_BERR_INT_EN_POS    (2U)
 #define MM_MISC_REG_CODEC_BERR_INT_EN_LEN    (1U)
@@ -232,11 +232,11 @@
 #define MM_MISC_REG_VRAM_SRAM_REL_LEN  (1U)
 #define MM_MISC_REG_VRAM_SRAM_REL_MSK  (((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS)
 #define MM_MISC_REG_VRAM_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_REL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_REL_POS))
-#define MM_MISC_REG_DSPL2_SRAM_REL      MM_MISC_REG_DSPL2_SRAM_REL
-#define MM_MISC_REG_DSPL2_SRAM_REL_POS  (6U)
-#define MM_MISC_REG_DSPL2_SRAM_REL_LEN  (1U)
-#define MM_MISC_REG_DSPL2_SRAM_REL_MSK  (((1U << MM_MISC_REG_DSPL2_SRAM_REL_LEN) - 1) << MM_MISC_REG_DSPL2_SRAM_REL_POS)
-#define MM_MISC_REG_DSPL2_SRAM_REL_UMSK (~(((1U << MM_MISC_REG_DSPL2_SRAM_REL_LEN) - 1) << MM_MISC_REG_DSPL2_SRAM_REL_POS))
+#define MM_MISC_REG_SUB_SRAM_REL       MM_MISC_REG_SUB_SRAM_REL
+#define MM_MISC_REG_SUB_SRAM_REL_POS   (6U)
+#define MM_MISC_REG_SUB_SRAM_REL_LEN   (1U)
+#define MM_MISC_REG_SUB_SRAM_REL_MSK   (((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS)
+#define MM_MISC_REG_SUB_SRAM_REL_UMSK  (~(((1U << MM_MISC_REG_SUB_SRAM_REL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_REL_POS))
 #define MM_MISC_REG_BLAI_SRAM_REL      MM_MISC_REG_BLAI_SRAM_REL
 #define MM_MISC_REG_BLAI_SRAM_REL_POS  (7U)
 #define MM_MISC_REG_BLAI_SRAM_REL_LEN  (1U)
@@ -252,11 +252,11 @@
 #define MM_MISC_REG_VRAM_SRAM_SEL_LEN  (1U)
 #define MM_MISC_REG_VRAM_SRAM_SEL_MSK  (((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS)
 #define MM_MISC_REG_VRAM_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_VRAM_SRAM_SEL_LEN) - 1) << MM_MISC_REG_VRAM_SRAM_SEL_POS))
-#define MM_MISC_REG_DSPL2_SRAM_SEL      MM_MISC_REG_DSPL2_SRAM_SEL
-#define MM_MISC_REG_DSPL2_SRAM_SEL_POS  (14U)
-#define MM_MISC_REG_DSPL2_SRAM_SEL_LEN  (1U)
-#define MM_MISC_REG_DSPL2_SRAM_SEL_MSK  (((1U << MM_MISC_REG_DSPL2_SRAM_SEL_LEN) - 1) << MM_MISC_REG_DSPL2_SRAM_SEL_POS)
-#define MM_MISC_REG_DSPL2_SRAM_SEL_UMSK (~(((1U << MM_MISC_REG_DSPL2_SRAM_SEL_LEN) - 1) << MM_MISC_REG_DSPL2_SRAM_SEL_POS))
+#define MM_MISC_REG_SUB_SRAM_SEL       MM_MISC_REG_SUB_SRAM_SEL
+#define MM_MISC_REG_SUB_SRAM_SEL_POS   (14U)
+#define MM_MISC_REG_SUB_SRAM_SEL_LEN   (1U)
+#define MM_MISC_REG_SUB_SRAM_SEL_MSK   (((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS)
+#define MM_MISC_REG_SUB_SRAM_SEL_UMSK  (~(((1U << MM_MISC_REG_SUB_SRAM_SEL_LEN) - 1) << MM_MISC_REG_SUB_SRAM_SEL_POS))
 #define MM_MISC_REG_BLAI_SRAM_SEL      MM_MISC_REG_BLAI_SRAM_SEL
 #define MM_MISC_REG_BLAI_SRAM_SEL_POS  (15U)
 #define MM_MISC_REG_BLAI_SRAM_SEL_LEN  (1U)
@@ -310,21 +310,21 @@
 #define MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN   (1U)
 #define MM_MISC_REG_SRAM_CDC_RAM_NAP_MSK   (((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS)
 #define MM_MISC_REG_SRAM_CDC_RAM_NAP_UMSK  (~(((1U << MM_MISC_REG_SRAM_CDC_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_CDC_RAM_NAP_POS))
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVS       MM_MISC_REG_SRAM_DSP2_RAM_DVS
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVS_POS   (24U)
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVS_LEN   (4U)
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVS_MSK   (((1U << MM_MISC_REG_SRAM_DSP2_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_DSP2_RAM_DVS_POS)
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVS_UMSK  (~(((1U << MM_MISC_REG_SRAM_DSP2_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_DSP2_RAM_DVS_POS))
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVSE      MM_MISC_REG_SRAM_DSP2_RAM_DVSE
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVSE_POS  (28U)
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVSE_LEN  (1U)
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVSE_MSK  (((1U << MM_MISC_REG_SRAM_DSP2_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_DSP2_RAM_DVSE_POS)
-#define MM_MISC_REG_SRAM_DSP2_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_DSP2_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_DSP2_RAM_DVSE_POS))
-#define MM_MISC_REG_SRAM_DSP2_RAM_NAP       MM_MISC_REG_SRAM_DSP2_RAM_NAP
-#define MM_MISC_REG_SRAM_DSP2_RAM_NAP_POS   (29U)
-#define MM_MISC_REG_SRAM_DSP2_RAM_NAP_LEN   (1U)
-#define MM_MISC_REG_SRAM_DSP2_RAM_NAP_MSK   (((1U << MM_MISC_REG_SRAM_DSP2_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_DSP2_RAM_NAP_POS)
-#define MM_MISC_REG_SRAM_DSP2_RAM_NAP_UMSK  (~(((1U << MM_MISC_REG_SRAM_DSP2_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_DSP2_RAM_NAP_POS))
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS       MM_MISC_REG_SRAM_SUB_RAM_DVS
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_POS   (24U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN   (4U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_MSK   (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVS_UMSK  (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVS_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVS_POS))
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE      MM_MISC_REG_SRAM_SUB_RAM_DVSE
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS  (28U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN  (1U)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_MSK  (((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS)
+#define MM_MISC_REG_SRAM_SUB_RAM_DVSE_UMSK (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_DVSE_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_DVSE_POS))
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP       MM_MISC_REG_SRAM_SUB_RAM_NAP
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_POS   (29U)
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN   (1U)
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_MSK   (((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS)
+#define MM_MISC_REG_SRAM_SUB_RAM_NAP_UMSK  (~(((1U << MM_MISC_REG_SRAM_SUB_RAM_NAP_LEN) - 1) << MM_MISC_REG_SRAM_SUB_RAM_NAP_POS))
 
 /* 0xA0 : MM_INT_STA0 */
 #define MM_MISC_MM_INT_STA0_OFFSET (0xA0)
@@ -420,11 +420,11 @@
 
 /* 0x140 : mm_berr_cfg0 */
 #define MM_MISC_MM_BERR_CFG0_OFFSET      (0x140)
-#define MM_MISC_REG_DSP2_BERR_EN          MM_MISC_REG_DSP2_BERR_EN
-#define MM_MISC_REG_DSP2_BERR_EN_POS      (0U)
-#define MM_MISC_REG_DSP2_BERR_EN_LEN      (3U)
-#define MM_MISC_REG_DSP2_BERR_EN_MSK      (((1U << MM_MISC_REG_DSP2_BERR_EN_LEN) - 1) << MM_MISC_REG_DSP2_BERR_EN_POS)
-#define MM_MISC_REG_DSP2_BERR_EN_UMSK     (~(((1U << MM_MISC_REG_DSP2_BERR_EN_LEN) - 1) << MM_MISC_REG_DSP2_BERR_EN_POS))
+#define MM_MISC_REG_BERR_EN          MM_MISC_REG_BERR_EN
+#define MM_MISC_REG_BERR_EN_POS      (0U)
+#define MM_MISC_REG_BERR_EN_LEN      (3U)
+#define MM_MISC_REG_BERR_EN_MSK      (((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS)
+#define MM_MISC_REG_BERR_EN_UMSK     (~(((1U << MM_MISC_REG_BERR_EN_LEN) - 1) << MM_MISC_REG_BERR_EN_POS))
 #define MM_MISC_REG_CODEC_BERR_EN        MM_MISC_REG_CODEC_BERR_EN
 #define MM_MISC_REG_CODEC_BERR_EN_POS    (8U)
 #define MM_MISC_REG_CODEC_BERR_EN_LEN    (3U)
@@ -443,11 +443,11 @@
 
 /* 0x144 : mm_berr_cfg1 */
 #define MM_MISC_MM_BERR_CFG1_OFFSET         (0x144)
-#define MM_MISC_REG_DSP2_BERR_CLR            MM_MISC_REG_DSP2_BERR_CLR
-#define MM_MISC_REG_DSP2_BERR_CLR_POS        (0U)
-#define MM_MISC_REG_DSP2_BERR_CLR_LEN        (1U)
-#define MM_MISC_REG_DSP2_BERR_CLR_MSK        (((1U << MM_MISC_REG_DSP2_BERR_CLR_LEN) - 1) << MM_MISC_REG_DSP2_BERR_CLR_POS)
-#define MM_MISC_REG_DSP2_BERR_CLR_UMSK       (~(((1U << MM_MISC_REG_DSP2_BERR_CLR_LEN) - 1) << MM_MISC_REG_DSP2_BERR_CLR_POS))
+#define MM_MISC_REG_BERR_CLR                MM_MISC_REG_BERR_CLR
+#define MM_MISC_REG_BERR_CLR_POS            (0U)
+#define MM_MISC_REG_BERR_CLR_LEN            (1U)
+#define MM_MISC_REG_BERR_CLR_MSK            (((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS)
+#define MM_MISC_REG_BERR_CLR_UMSK           (~(((1U << MM_MISC_REG_BERR_CLR_LEN) - 1) << MM_MISC_REG_BERR_CLR_POS))
 #define MM_MISC_REG_CODEC_BERR_CLR          MM_MISC_REG_CODEC_BERR_CLR
 #define MM_MISC_REG_CODEC_BERR_CLR_POS      (1U)
 #define MM_MISC_REG_CODEC_BERR_CLR_LEN      (1U)
@@ -463,11 +463,11 @@
 #define MM_MISC_REG_MMINFRA_BERR_CLR_LEN    (1U)
 #define MM_MISC_REG_MMINFRA_BERR_CLR_MSK    (((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS)
 #define MM_MISC_REG_MMINFRA_BERR_CLR_UMSK   (~(((1U << MM_MISC_REG_MMINFRA_BERR_CLR_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_CLR_POS))
-#define MM_MISC_REG_DSP2_BERR_LAST           MM_MISC_REG_DSP2_BERR_LAST
-#define MM_MISC_REG_DSP2_BERR_LAST_POS       (8U)
-#define MM_MISC_REG_DSP2_BERR_LAST_LEN       (1U)
-#define MM_MISC_REG_DSP2_BERR_LAST_MSK       (((1U << MM_MISC_REG_DSP2_BERR_LAST_LEN) - 1) << MM_MISC_REG_DSP2_BERR_LAST_POS)
-#define MM_MISC_REG_DSP2_BERR_LAST_UMSK      (~(((1U << MM_MISC_REG_DSP2_BERR_LAST_LEN) - 1) << MM_MISC_REG_DSP2_BERR_LAST_POS))
+#define MM_MISC_REG_BERR_LAST               MM_MISC_REG_BERR_LAST
+#define MM_MISC_REG_BERR_LAST_POS           (8U)
+#define MM_MISC_REG_BERR_LAST_LEN           (1U)
+#define MM_MISC_REG_BERR_LAST_MSK           (((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS)
+#define MM_MISC_REG_BERR_LAST_UMSK          (~(((1U << MM_MISC_REG_BERR_LAST_LEN) - 1) << MM_MISC_REG_BERR_LAST_POS))
 #define MM_MISC_REG_CODEC_BERR_LAST         MM_MISC_REG_CODEC_BERR_LAST
 #define MM_MISC_REG_CODEC_BERR_LAST_POS     (9U)
 #define MM_MISC_REG_CODEC_BERR_LAST_LEN     (1U)
@@ -483,11 +483,11 @@
 #define MM_MISC_REG_MMINFRA_BERR_LAST_LEN   (1U)
 #define MM_MISC_REG_MMINFRA_BERR_LAST_MSK   (((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS)
 #define MM_MISC_REG_MMINFRA_BERR_LAST_UMSK  (~(((1U << MM_MISC_REG_MMINFRA_BERR_LAST_LEN) - 1) << MM_MISC_REG_MMINFRA_BERR_LAST_POS))
-#define MM_MISC_STS_DSP2_BERR                MM_MISC_STS_DSP2_BERR
-#define MM_MISC_STS_DSP2_BERR_POS            (16U)
-#define MM_MISC_STS_DSP2_BERR_LEN            (1U)
-#define MM_MISC_STS_DSP2_BERR_MSK            (((1U << MM_MISC_STS_DSP2_BERR_LEN) - 1) << MM_MISC_STS_DSP2_BERR_POS)
-#define MM_MISC_STS_DSP2_BERR_UMSK           (~(((1U << MM_MISC_STS_DSP2_BERR_LEN) - 1) << MM_MISC_STS_DSP2_BERR_POS))
+#define MM_MISC_STS_BERR                    MM_MISC_STS_BERR
+#define MM_MISC_STS_BERR_POS                (16U)
+#define MM_MISC_STS_BERR_LEN                (1U)
+#define MM_MISC_STS_BERR_MSK                (((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS)
+#define MM_MISC_STS_BERR_UMSK               (~(((1U << MM_MISC_STS_BERR_LEN) - 1) << MM_MISC_STS_BERR_POS))
 #define MM_MISC_STS_CODEC_BERR              MM_MISC_STS_CODEC_BERR
 #define MM_MISC_STS_CODEC_BERR_POS          (17U)
 #define MM_MISC_STS_CODEC_BERR_LEN          (1U)
@@ -503,11 +503,11 @@
 #define MM_MISC_STS_MMINFRA_BERR_LEN        (1U)
 #define MM_MISC_STS_MMINFRA_BERR_MSK        (((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS)
 #define MM_MISC_STS_MMINFRA_BERR_UMSK       (~(((1U << MM_MISC_STS_MMINFRA_BERR_LEN) - 1) << MM_MISC_STS_MMINFRA_BERR_POS))
-#define MM_MISC_STS_DSP2_BERR_WRITE          MM_MISC_STS_DSP2_BERR_WRITE
-#define MM_MISC_STS_DSP2_BERR_WRITE_POS      (24U)
-#define MM_MISC_STS_DSP2_BERR_WRITE_LEN      (1U)
-#define MM_MISC_STS_DSP2_BERR_WRITE_MSK      (((1U << MM_MISC_STS_DSP2_BERR_WRITE_LEN) - 1) << MM_MISC_STS_DSP2_BERR_WRITE_POS)
-#define MM_MISC_STS_DSP2_BERR_WRITE_UMSK     (~(((1U << MM_MISC_STS_DSP2_BERR_WRITE_LEN) - 1) << MM_MISC_STS_DSP2_BERR_WRITE_POS))
+#define MM_MISC_STS_BERR_WRITE              MM_MISC_STS_BERR_WRITE
+#define MM_MISC_STS_BERR_WRITE_POS          (24U)
+#define MM_MISC_STS_BERR_WRITE_LEN          (1U)
+#define MM_MISC_STS_BERR_WRITE_MSK          (((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS)
+#define MM_MISC_STS_BERR_WRITE_UMSK         (~(((1U << MM_MISC_STS_BERR_WRITE_LEN) - 1) << MM_MISC_STS_BERR_WRITE_POS))
 #define MM_MISC_STS_CODEC_BERR_WRITE        MM_MISC_STS_CODEC_BERR_WRITE
 #define MM_MISC_STS_CODEC_BERR_WRITE_POS    (25U)
 #define MM_MISC_STS_CODEC_BERR_WRITE_LEN    (1U)
@@ -526,16 +526,16 @@
 
 /* 0x148 : mm_berr_cfg2 */
 #define MM_MISC_MM_BERR_CFG2_OFFSET     (0x148)
-#define MM_MISC_STS_DSP2_BERR_SRC        MM_MISC_STS_DSP2_BERR_SRC
-#define MM_MISC_STS_DSP2_BERR_SRC_POS    (0U)
-#define MM_MISC_STS_DSP2_BERR_SRC_LEN    (3U)
-#define MM_MISC_STS_DSP2_BERR_SRC_MSK    (((1U << MM_MISC_STS_DSP2_BERR_SRC_LEN) - 1) << MM_MISC_STS_DSP2_BERR_SRC_POS)
-#define MM_MISC_STS_DSP2_BERR_SRC_UMSK   (~(((1U << MM_MISC_STS_DSP2_BERR_SRC_LEN) - 1) << MM_MISC_STS_DSP2_BERR_SRC_POS))
-#define MM_MISC_STS_DSP2_BERR_ID         MM_MISC_STS_DSP2_BERR_ID
-#define MM_MISC_STS_DSP2_BERR_ID_POS     (8U)
-#define MM_MISC_STS_DSP2_BERR_ID_LEN     (4U)
-#define MM_MISC_STS_DSP2_BERR_ID_MSK     (((1U << MM_MISC_STS_DSP2_BERR_ID_LEN) - 1) << MM_MISC_STS_DSP2_BERR_ID_POS)
-#define MM_MISC_STS_DSP2_BERR_ID_UMSK    (~(((1U << MM_MISC_STS_DSP2_BERR_ID_LEN) - 1) << MM_MISC_STS_DSP2_BERR_ID_POS))
+#define MM_MISC_STS_BERR_SRC            MM_MISC_STS_BERR_SRC
+#define MM_MISC_STS_BERR_SRC_POS        (0U)
+#define MM_MISC_STS_BERR_SRC_LEN        (3U)
+#define MM_MISC_STS_BERR_SRC_MSK        (((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS)
+#define MM_MISC_STS_BERR_SRC_UMSK       (~(((1U << MM_MISC_STS_BERR_SRC_LEN) - 1) << MM_MISC_STS_BERR_SRC_POS))
+#define MM_MISC_STS_BERR_ID             MM_MISC_STS_BERR_ID
+#define MM_MISC_STS_BERR_ID_POS         (8U)
+#define MM_MISC_STS_BERR_ID_LEN         (4U)
+#define MM_MISC_STS_BERR_ID_MSK         (((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS)
+#define MM_MISC_STS_BERR_ID_UMSK        (~(((1U << MM_MISC_STS_BERR_ID_LEN) - 1) << MM_MISC_STS_BERR_ID_POS))
 #define MM_MISC_STS_CODEC_BERR_SRC      MM_MISC_STS_CODEC_BERR_SRC
 #define MM_MISC_STS_CODEC_BERR_SRC_POS  (16U)
 #define MM_MISC_STS_CODEC_BERR_SRC_LEN  (3U)
@@ -572,11 +572,11 @@
 
 /* 0x150 : mm_berr_cfg4 */
 #define MM_MISC_MM_BERR_CFG4_OFFSET    (0x150)
-#define MM_MISC_STS_DSP2_BERR_ADDR      MM_MISC_STS_DSP2_BERR_ADDR
-#define MM_MISC_STS_DSP2_BERR_ADDR_POS  (0U)
-#define MM_MISC_STS_DSP2_BERR_ADDR_LEN  (32U)
-#define MM_MISC_STS_DSP2_BERR_ADDR_MSK  (((1U << MM_MISC_STS_DSP2_BERR_ADDR_LEN) - 1) << MM_MISC_STS_DSP2_BERR_ADDR_POS)
-#define MM_MISC_STS_DSP2_BERR_ADDR_UMSK (~(((1U << MM_MISC_STS_DSP2_BERR_ADDR_LEN) - 1) << MM_MISC_STS_DSP2_BERR_ADDR_POS))
+#define MM_MISC_STS_BERR_ADDR          MM_MISC_STS_BERR_ADDR
+#define MM_MISC_STS_BERR_ADDR_POS      (0U)
+#define MM_MISC_STS_BERR_ADDR_LEN      (32U)
+#define MM_MISC_STS_BERR_ADDR_MSK      (((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS)
+#define MM_MISC_STS_BERR_ADDR_UMSK     (~(((1U << MM_MISC_STS_BERR_ADDR_LEN) - 1) << MM_MISC_STS_BERR_ADDR_POS))
 
 /* 0x154 : mm_berr_cfg5 */
 #define MM_MISC_MM_BERR_CFG5_OFFSET      (0x154)
@@ -680,7 +680,7 @@ struct mm_misc_reg {
     union {
         struct {
             uint32_t reg_mminfra_berr_int_en : 1;  /* [    0],        r/w,        0x0 */
-            uint32_t reg_dsp2_berr_int_en     : 1;  /* [    1],        r/w,        0x0 */
+            uint32_t reg_berr_int_en         : 1;  /* [    1],        r/w,        0x0 */
             uint32_t reg_codec_berr_int_en   : 1;  /* [    2],        r/w,        0x0 */
             uint32_t reg_mmcpu_berr_int_en   : 1;  /* [    3],        r/w,        0x0 */
             uint32_t reserved_4_7            : 4;  /* [ 7: 4],       rsvd,        0x0 */
@@ -734,13 +734,13 @@ struct mm_misc_reg {
             uint32_t reserved_3        : 1;  /* [    3],       rsvd,        0x0 */
             uint32_t reg_vram_sram_rel : 1;  /* [    4],        r/w,        0x0 */
             uint32_t reserved_5        : 1;  /* [    5],       rsvd,        0x0 */
-            uint32_t reg_dspl2_sram_rel : 1;  /* [    6],        r/w,        0x0 */
+            uint32_t reg_sub_sram_rel  : 1;  /* [    6],        r/w,        0x0 */
             uint32_t reg_blai_sram_rel : 1;  /* [    7],        r/w,        0x0 */
             uint32_t reg_h2pf_sram_sel : 3;  /* [10: 8],          r,        0x0 */
             uint32_t reserved_11       : 1;  /* [   11],       rsvd,        0x0 */
             uint32_t reg_vram_sram_sel : 1;  /* [   12],          r,        0x0 */
             uint32_t reserved_13       : 1;  /* [   13],       rsvd,        0x0 */
-            uint32_t reg_dspl2_sram_sel : 1;  /* [   14],          r,        0x0 */
+            uint32_t reg_sub_sram_sel  : 1;  /* [   14],          r,        0x0 */
             uint32_t reg_blai_sram_sel : 1;  /* [   15],          r,        0x0 */
             uint32_t reserved_16_31    : 16; /* [31:16],       rsvd,        0x0 */
         } BF;
@@ -765,9 +765,9 @@ struct mm_misc_reg {
             uint32_t reg_sram_cdc_ram_dvse : 1; /* [   20],        r/w,        0x0 */
             uint32_t reg_sram_cdc_ram_nap  : 1; /* [   21],        r/w,        0x0 */
             uint32_t reserved_22_23        : 2; /* [23:22],       rsvd,        0x0 */
-            uint32_t reg_sram_dsp2_ram_dvs  : 4; /* [27:24],        r/w,        0xc */
-            uint32_t reg_sram_dsp2_ram_dvse : 1; /* [   28],        r/w,        0x0 */
-            uint32_t reg_sram_dsp2_ram_nap  : 1; /* [   29],        r/w,        0x0 */
+            uint32_t reg_sram_sub_ram_dvs  : 4; /* [27:24],        r/w,        0xc */
+            uint32_t reg_sram_sub_ram_dvse : 1; /* [   28],        r/w,        0x0 */
+            uint32_t reg_sram_sub_ram_nap  : 1; /* [   29],        r/w,        0x0 */
             uint32_t reserved_30_31        : 2; /* [31:30],       rsvd,        0x0 */
         } BF;
         uint32_t WORD;
@@ -866,7 +866,7 @@ struct mm_misc_reg {
     /* 0x140 : mm_berr_cfg0 */
     union {
         struct {
-            uint32_t reg_dsp2_berr_en     : 3; /* [ 2: 0],        r/w,        0x7 */
+            uint32_t reg_berr_en         : 3; /* [ 2: 0],        r/w,        0x7 */
             uint32_t reserved_3_7        : 5; /* [ 7: 3],       rsvd,        0x0 */
             uint32_t reg_codec_berr_en   : 3; /* [10: 8],        r/w,        0x7 */
             uint32_t reserved_11_15      : 5; /* [15:11],       rsvd,        0x0 */
@@ -881,22 +881,22 @@ struct mm_misc_reg {
     /* 0x144 : mm_berr_cfg1 */
     union {
         struct {
-            uint32_t reg_dsp2_berr_clr       : 1; /* [    0],        r/w,        0x0 */
+            uint32_t reg_berr_clr           : 1; /* [    0],        r/w,        0x0 */
             uint32_t reg_codec_berr_clr     : 1; /* [    1],        r/w,        0x0 */
             uint32_t reg_mmcpu_berr_clr     : 1; /* [    2],        r/w,        0x0 */
             uint32_t reg_mminfra_berr_clr   : 1; /* [    3],        r/w,        0x0 */
             uint32_t reserved_4_7           : 4; /* [ 7: 4],       rsvd,        0x0 */
-            uint32_t reg_dsp2_berr_last      : 1; /* [    8],        r/w,        0x0 */
+            uint32_t reg_berr_last          : 1; /* [    8],        r/w,        0x0 */
             uint32_t reg_codec_berr_last    : 1; /* [    9],        r/w,        0x0 */
             uint32_t reg_mmcpu_berr_last    : 1; /* [   10],        r/w,        0x0 */
             uint32_t reg_mminfra_berr_last  : 1; /* [   11],        r/w,        0x0 */
             uint32_t reserved_12_15         : 4; /* [15:12],       rsvd,        0x0 */
-            uint32_t sts_dsp2_berr           : 1; /* [   16],          r,        0x0 */
+            uint32_t sts_berr               : 1; /* [   16],          r,        0x0 */
             uint32_t sts_codec_berr         : 1; /* [   17],          r,        0x0 */
             uint32_t sts_mmcpu_berr         : 1; /* [   18],          r,        0x0 */
             uint32_t sts_mminfra_berr       : 1; /* [   19],          r,        0x0 */
             uint32_t reserved_20_23         : 4; /* [23:20],       rsvd,        0x0 */
-            uint32_t sts_dsp2_berr_write     : 1; /* [   24],          r,        0x0 */
+            uint32_t sts_berr_write         : 1; /* [   24],          r,        0x0 */
             uint32_t sts_codec_berr_write   : 1; /* [   25],          r,        0x0 */
             uint32_t sts_mmcpu_berr_write   : 1; /* [   26],          r,        0x0 */
             uint32_t sts_mminfra_berr_write : 1; /* [   27],          r,        0x0 */
@@ -908,9 +908,9 @@ struct mm_misc_reg {
     /* 0x148 : mm_berr_cfg2 */
     union {
         struct {
-            uint32_t sts_dsp2_berr_src   : 3; /* [ 2: 0],          r,        0x0 */
+            uint32_t sts_berr_src       : 3; /* [ 2: 0],          r,        0x0 */
             uint32_t reserved_3_7       : 5; /* [ 7: 3],       rsvd,        0x0 */
-            uint32_t sts_dsp2_berr_id    : 4; /* [11: 8],          r,        0x0 */
+            uint32_t sts_berr_id        : 4; /* [11: 8],          r,        0x0 */
             uint32_t reserved_12_15     : 4; /* [15:12],       rsvd,        0x0 */
             uint32_t sts_codec_berr_src : 3; /* [18:16],          r,        0x0 */
             uint32_t reserved_19_23     : 5; /* [23:19],       rsvd,        0x0 */
@@ -938,7 +938,7 @@ struct mm_misc_reg {
     /* 0x150 : mm_berr_cfg4 */
     union {
         struct {
-            uint32_t sts_dsp2_berr_addr : 32; /* [31: 0],          r,        0x0 */
+            uint32_t sts_berr_addr : 32; /* [31: 0],          r,        0x0 */
         } BF;
         uint32_t WORD;
     } mm_berr_cfg4;
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pds_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/pds_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/pds_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/pds_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/psram_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/psram_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/psram_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/psram_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/psram_uhs_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/psram_uhs_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/psram_uhs_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/psram_uhs_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sdh_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/sdh_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sdh_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/sdh_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sf_ctrl_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/sf_ctrl_reg.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/sf_ctrl_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/sf_ctrl_reg.h
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/tzc_nsec_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/tzc_nsec_reg.h
old mode 100644
new mode 100755
similarity index 93%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/tzc_nsec_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/tzc_nsec_reg.h
index b1cfa23530..2cc613fdc6
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/tzc_nsec_reg.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/tzc_nsec_reg.h
@@ -1171,11 +1171,11 @@
 #define TZC_NSEC_TZC_CODEC_TZMID_LEN           (1U)
 #define TZC_NSEC_TZC_CODEC_TZMID_MSK           (((1U << TZC_NSEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_POS)
 #define TZC_NSEC_TZC_CODEC_TZMID_UMSK          (~(((1U << TZC_NSEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_POS))
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID          TZC_NSEC_TZC_DSP2_SUBSYS_TZMID
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_POS      (3U)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LEN      (1U)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_MSK      (((1U << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LEN) - 1) << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_POS)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_UMSK     (~(((1U << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LEN) - 1) << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_POS))
+#define TZC_NSEC_TZC_SUBSYS_TZMID              TZC_NSEC_TZC_SUBSYS_TZMID
+#define TZC_NSEC_TZC_SUBSYS_TZMID_POS          (3U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LEN          (1U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_MSK          (((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_POS)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_UMSK         (~(((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_POS))
 #define TZC_NSEC_TZC_X2DDMA_TZMID              TZC_NSEC_TZC_X2DDMA_TZMID
 #define TZC_NSEC_TZC_X2DDMA_TZMID_POS          (4U)
 #define TZC_NSEC_TZC_X2DDMA_TZMID_LEN          (1U)
@@ -1201,11 +1201,11 @@
 #define TZC_NSEC_TZC_CODEC_TZMID_SEL_LEN       (1U)
 #define TZC_NSEC_TZC_CODEC_TZMID_SEL_MSK       (((1U << TZC_NSEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_SEL_POS)
 #define TZC_NSEC_TZC_CODEC_TZMID_SEL_UMSK      (~(((1U << TZC_NSEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_SEL_POS))
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL      TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_POS  (19U)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_LEN  (1U)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_MSK  (((1U << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_POS)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_SEL_POS))
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL          TZC_NSEC_TZC_SUBSYS_TZMID_SEL
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_POS      (19U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_LEN      (1U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_MSK      (((1U << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_POS)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_SEL_UMSK     (~(((1U << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_SEL_POS))
 #define TZC_NSEC_TZC_X2DDMA_TZMID_SEL          TZC_NSEC_TZC_X2DDMA_TZMID_SEL
 #define TZC_NSEC_TZC_X2DDMA_TZMID_SEL_POS      (20U)
 #define TZC_NSEC_TZC_X2DDMA_TZMID_SEL_LEN      (1U)
@@ -1234,11 +1234,11 @@
 #define TZC_NSEC_TZC_CODEC_TZMID_LOCK_LEN       (1U)
 #define TZC_NSEC_TZC_CODEC_TZMID_LOCK_MSK       (((1U << TZC_NSEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_LOCK_POS)
 #define TZC_NSEC_TZC_CODEC_TZMID_LOCK_UMSK      (~(((1U << TZC_NSEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_TZMID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK      TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_POS  (3U)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_LEN  (1U)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_MSK  (((1U << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_SUBSYS_TZMID_LOCK_POS))
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK          TZC_NSEC_TZC_SUBSYS_TZMID_LOCK
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_POS      (3U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_LEN      (1U)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_MSK      (((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_POS)
+#define TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_UMSK     (~(((1U << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_NSEC_TZC_SUBSYS_TZMID_LOCK_POS))
 #define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK          TZC_NSEC_TZC_X2DDMA_TZMID_LOCK
 #define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_POS      (4U)
 #define TZC_NSEC_TZC_X2DDMA_TZMID_LOCK_LEN      (1U)
@@ -1334,87 +1334,87 @@
 #define TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_MMPERI_S1F_TZSID_EN_POS))
 
 /* 0x30C : tzc_mm_bmx_s1 */
-#define TZC_NSEC_TZC_MM_BMX_S1_OFFSET      (0x30C)
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_EN      TZC_NSEC_TZC_DSP2_S10_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_EN_POS  (0U)
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S10_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S10_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_EN      TZC_NSEC_TZC_DSP2_S11_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_EN_POS  (2U)
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S11_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S11_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_EN      TZC_NSEC_TZC_DSP2_S12_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_EN_POS  (4U)
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S12_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S12_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_EN      TZC_NSEC_TZC_DSP2_S13_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_EN_POS  (6U)
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S13_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S13_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_EN      TZC_NSEC_TZC_DSP2_S14_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_EN_POS  (8U)
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S14_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S14_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_EN      TZC_NSEC_TZC_DSP2_S15_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_EN_POS  (10U)
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S15_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S15_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_EN      TZC_NSEC_TZC_DSP2_S16_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_EN_POS  (12U)
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S16_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S16_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_EN      TZC_NSEC_TZC_DSP2_S17_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_EN_POS  (14U)
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S17_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S17_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_EN      TZC_NSEC_TZC_DSP2_S18_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_EN_POS  (16U)
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S18_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S18_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_EN      TZC_NSEC_TZC_DSP2_S19_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_EN_POS  (18U)
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S19_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S19_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_EN      TZC_NSEC_TZC_DSP2_S1A_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_POS  (20U)
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1A_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_EN      TZC_NSEC_TZC_DSP2_S1B_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_POS  (22U)
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1B_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_EN      TZC_NSEC_TZC_DSP2_S1C_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_POS  (24U)
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1C_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_EN      TZC_NSEC_TZC_DSP2_S1D_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_POS  (26U)
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1D_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_EN      TZC_NSEC_TZC_DSP2_S1E_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_POS  (28U)
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1E_TZSID_EN_POS))
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_EN      TZC_NSEC_TZC_DSP2_S1F_TZSID_EN
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_POS  (30U)
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_LEN  (2U)
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_POS)
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1F_TZSID_EN_POS))
+#define TZC_NSEC_TZC_MM_BMX_S1_OFFSET  (0x30C)
+#define TZC_NSEC_TZC_S10_TZSID_EN      TZC_NSEC_TZC_S10_TZSID_EN
+#define TZC_NSEC_TZC_S10_TZSID_EN_POS  (0U)
+#define TZC_NSEC_TZC_S10_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S10_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S10_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S11_TZSID_EN      TZC_NSEC_TZC_S11_TZSID_EN
+#define TZC_NSEC_TZC_S11_TZSID_EN_POS  (2U)
+#define TZC_NSEC_TZC_S11_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S11_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S11_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S12_TZSID_EN      TZC_NSEC_TZC_S12_TZSID_EN
+#define TZC_NSEC_TZC_S12_TZSID_EN_POS  (4U)
+#define TZC_NSEC_TZC_S12_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S12_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S12_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S13_TZSID_EN      TZC_NSEC_TZC_S13_TZSID_EN
+#define TZC_NSEC_TZC_S13_TZSID_EN_POS  (6U)
+#define TZC_NSEC_TZC_S13_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S13_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S13_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S14_TZSID_EN      TZC_NSEC_TZC_S14_TZSID_EN
+#define TZC_NSEC_TZC_S14_TZSID_EN_POS  (8U)
+#define TZC_NSEC_TZC_S14_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S14_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S14_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S15_TZSID_EN      TZC_NSEC_TZC_S15_TZSID_EN
+#define TZC_NSEC_TZC_S15_TZSID_EN_POS  (10U)
+#define TZC_NSEC_TZC_S15_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S15_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S15_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S16_TZSID_EN      TZC_NSEC_TZC_S16_TZSID_EN
+#define TZC_NSEC_TZC_S16_TZSID_EN_POS  (12U)
+#define TZC_NSEC_TZC_S16_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S16_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S16_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S17_TZSID_EN      TZC_NSEC_TZC_S17_TZSID_EN
+#define TZC_NSEC_TZC_S17_TZSID_EN_POS  (14U)
+#define TZC_NSEC_TZC_S17_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S17_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S17_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S18_TZSID_EN      TZC_NSEC_TZC_S18_TZSID_EN
+#define TZC_NSEC_TZC_S18_TZSID_EN_POS  (16U)
+#define TZC_NSEC_TZC_S18_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S18_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S18_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S19_TZSID_EN      TZC_NSEC_TZC_S19_TZSID_EN
+#define TZC_NSEC_TZC_S19_TZSID_EN_POS  (18U)
+#define TZC_NSEC_TZC_S19_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S19_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S19_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1A_TZSID_EN      TZC_NSEC_TZC_S1A_TZSID_EN
+#define TZC_NSEC_TZC_S1A_TZSID_EN_POS  (20U)
+#define TZC_NSEC_TZC_S1A_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S1A_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1A_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1B_TZSID_EN      TZC_NSEC_TZC_S1B_TZSID_EN
+#define TZC_NSEC_TZC_S1B_TZSID_EN_POS  (22U)
+#define TZC_NSEC_TZC_S1B_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S1B_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1B_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1C_TZSID_EN      TZC_NSEC_TZC_S1C_TZSID_EN
+#define TZC_NSEC_TZC_S1C_TZSID_EN_POS  (24U)
+#define TZC_NSEC_TZC_S1C_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S1C_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1C_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1D_TZSID_EN      TZC_NSEC_TZC_S1D_TZSID_EN
+#define TZC_NSEC_TZC_S1D_TZSID_EN_POS  (26U)
+#define TZC_NSEC_TZC_S1D_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S1D_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1D_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1E_TZSID_EN      TZC_NSEC_TZC_S1E_TZSID_EN
+#define TZC_NSEC_TZC_S1E_TZSID_EN_POS  (28U)
+#define TZC_NSEC_TZC_S1E_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S1E_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1E_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_EN_POS))
+#define TZC_NSEC_TZC_S1F_TZSID_EN      TZC_NSEC_TZC_S1F_TZSID_EN
+#define TZC_NSEC_TZC_S1F_TZSID_EN_POS  (30U)
+#define TZC_NSEC_TZC_S1F_TZSID_EN_LEN  (2U)
+#define TZC_NSEC_TZC_S1F_TZSID_EN_MSK  (((1U << TZC_NSEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_EN_POS)
+#define TZC_NSEC_TZC_S1F_TZSID_EN_UMSK (~(((1U << TZC_NSEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_EN_POS))
 
 /* 0x310 : tzc_mm_bmx_s2 */
 #define TZC_NSEC_TZC_MM_BMX_S2_OFFSET        (0x310)
@@ -1664,86 +1664,86 @@
 #define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_LEN  (1U)
 #define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_MSK  (((1U << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_POS)
 #define TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_CODEC_S1F_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_POS    (16U)
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S10_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_POS    (17U)
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S11_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_POS    (18U)
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S12_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_POS    (19U)
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S13_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_POS    (20U)
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S14_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_POS    (21U)
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S15_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_POS    (22U)
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S16_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_POS    (23U)
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S17_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_POS    (24U)
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S18_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_POS    (25U)
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S19_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_POS    (26U)
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1A_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_POS    (27U)
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1B_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_POS    (28U)
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1C_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_POS    (29U)
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1D_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_POS    (30U)
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1E_TZSID_LOCK_POS))
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK        TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_POS    (31U)
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_LEN    (1U)
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_MSK    (((1U << TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_POS)
-#define TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_UMSK   (~(((1U << TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_DSP2_S1F_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S10_TZSID_LOCK            TZC_NSEC_TZC_S10_TZSID_LOCK
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_POS        (16U)
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S10_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S10_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S11_TZSID_LOCK            TZC_NSEC_TZC_S11_TZSID_LOCK
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_POS        (17U)
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S11_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S11_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S12_TZSID_LOCK            TZC_NSEC_TZC_S12_TZSID_LOCK
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_POS        (18U)
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S12_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S12_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S13_TZSID_LOCK            TZC_NSEC_TZC_S13_TZSID_LOCK
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_POS        (19U)
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S13_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S13_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S14_TZSID_LOCK            TZC_NSEC_TZC_S14_TZSID_LOCK
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_POS        (20U)
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S14_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S14_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S15_TZSID_LOCK            TZC_NSEC_TZC_S15_TZSID_LOCK
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_POS        (21U)
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S15_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S15_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S16_TZSID_LOCK            TZC_NSEC_TZC_S16_TZSID_LOCK
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_POS        (22U)
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S16_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S16_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S17_TZSID_LOCK            TZC_NSEC_TZC_S17_TZSID_LOCK
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_POS        (23U)
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S17_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S17_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S18_TZSID_LOCK            TZC_NSEC_TZC_S18_TZSID_LOCK
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_POS        (24U)
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S18_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S18_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S19_TZSID_LOCK            TZC_NSEC_TZC_S19_TZSID_LOCK
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_POS        (25U)
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S19_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S19_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK            TZC_NSEC_TZC_S1A_TZSID_LOCK
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_POS        (26U)
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1A_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1A_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK            TZC_NSEC_TZC_S1B_TZSID_LOCK
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_POS        (27U)
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1B_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1B_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK            TZC_NSEC_TZC_S1C_TZSID_LOCK
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_POS        (28U)
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1C_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1C_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK            TZC_NSEC_TZC_S1D_TZSID_LOCK
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_POS        (29U)
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1D_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1D_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK            TZC_NSEC_TZC_S1E_TZSID_LOCK
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_POS        (30U)
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1E_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1E_TZSID_LOCK_POS))
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK            TZC_NSEC_TZC_S1F_TZSID_LOCK
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_POS        (31U)
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_LEN        (1U)
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_MSK        (((1U << TZC_NSEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_LOCK_POS)
+#define TZC_NSEC_TZC_S1F_TZSID_LOCK_UMSK       (~(((1U << TZC_NSEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_NSEC_TZC_S1F_TZSID_LOCK_POS))
 
 /* 0x340 : tzc_l2sram_tzsrg_ctrl */
 #define TZC_NSEC_TZC_L2SRAM_TZSRG_CTRL_OFFSET   (0x340)
@@ -3133,14 +3133,14 @@ struct tzc_nsec_reg {
             uint32_t tzc_mmcpu_tzmid          : 1;  /* [    0],          r,        0x0 */
             uint32_t tzc_blai_tzmid           : 1;  /* [    1],          r,        0x0 */
             uint32_t tzc_codec_tzmid          : 1;  /* [    2],          r,        0x0 */
-            uint32_t tzc_dsp2_subsys_tzmid     : 1;  /* [    3],          r,        0x0 */
+            uint32_t tzc_subsys_tzmid         : 1;  /* [    3],          r,        0x0 */
             uint32_t tzc_x2ddma_tzmid         : 1;  /* [    4],          r,        0x0 */
             uint32_t tzc_xdma_tzmid           : 1;  /* [    5],          r,        0x0 */
             uint32_t reserved_6_15            : 10; /* [15: 6],       rsvd,        0x0 */
             uint32_t tzc_mmcpu_tzmid_sel      : 1;  /* [   16],          r,        0x1 */
             uint32_t tzc_blai_tzmid_sel       : 1;  /* [   17],          r,        0x1 */
             uint32_t tzc_codec_tzmid_sel      : 1;  /* [   18],          r,        0x1 */
-            uint32_t tzc_dsp2_subsys_tzmid_sel : 1;  /* [   19],          r,        0x1 */
+            uint32_t tzc_subsys_tzmid_sel     : 1;  /* [   19],          r,        0x1 */
             uint32_t tzc_x2ddma_tzmid_sel     : 1;  /* [   20],          r,        0x1 */
             uint32_t tzc_xdma_tzmid_sel       : 1;  /* [   21],          r,        0x1 */
             uint32_t reserved_22_31           : 10; /* [31:22],       rsvd,        0x0 */
@@ -3154,7 +3154,7 @@ struct tzc_nsec_reg {
             uint32_t tzc_mmcpu_tzmid_lock      : 1;  /* [    0],          r,        0x0 */
             uint32_t tzc_blai_tzmid_lock       : 1;  /* [    1],          r,        0x0 */
             uint32_t tzc_codec_tzmid_lock      : 1;  /* [    2],          r,        0x0 */
-            uint32_t tzc_dsp2_subsys_tzmid_lock : 1;  /* [    3],          r,        0x0 */
+            uint32_t tzc_subsys_tzmid_lock     : 1;  /* [    3],          r,        0x0 */
             uint32_t tzc_x2ddma_tzmid_lock     : 1;  /* [    4],          r,        0x0 */
             uint32_t tzc_xdma_tzmid_lock       : 1;  /* [    5],          r,        0x0 */
             uint32_t reserved_6_31             : 26; /* [31: 6],       rsvd,        0x0 */
@@ -3188,22 +3188,22 @@ struct tzc_nsec_reg {
     /* 0x30C : tzc_mm_bmx_s1 */
     union {
         struct {
-            uint32_t tzc_dsp2_s10_tzsid_en : 2; /* [ 1: 0],          r,        0x3 */
-            uint32_t tzc_dsp2_s11_tzsid_en : 2; /* [ 3: 2],          r,        0x3 */
-            uint32_t tzc_dsp2_s12_tzsid_en : 2; /* [ 5: 4],          r,        0x3 */
-            uint32_t tzc_dsp2_s13_tzsid_en : 2; /* [ 7: 6],          r,        0x3 */
-            uint32_t tzc_dsp2_s14_tzsid_en : 2; /* [ 9: 8],          r,        0x3 */
-            uint32_t tzc_dsp2_s15_tzsid_en : 2; /* [11:10],          r,        0x3 */
-            uint32_t tzc_dsp2_s16_tzsid_en : 2; /* [13:12],          r,        0x3 */
-            uint32_t tzc_dsp2_s17_tzsid_en : 2; /* [15:14],          r,        0x3 */
-            uint32_t tzc_dsp2_s18_tzsid_en : 2; /* [17:16],          r,        0x3 */
-            uint32_t tzc_dsp2_s19_tzsid_en : 2; /* [19:18],          r,        0x3 */
-            uint32_t tzc_dsp2_s1a_tzsid_en : 2; /* [21:20],          r,        0x3 */
-            uint32_t tzc_dsp2_s1b_tzsid_en : 2; /* [23:22],          r,        0x3 */
-            uint32_t tzc_dsp2_s1c_tzsid_en : 2; /* [25:24],          r,        0x3 */
-            uint32_t tzc_dsp2_s1d_tzsid_en : 2; /* [27:26],          r,        0x3 */
-            uint32_t tzc_dsp2_s1e_tzsid_en : 2; /* [29:28],          r,        0x3 */
-            uint32_t tzc_dsp2_s1f_tzsid_en : 2; /* [31:30],          r,        0x3 */
+            uint32_t tzc_s10_tzsid_en : 2; /* [ 1: 0],          r,        0x3 */
+            uint32_t tzc_s11_tzsid_en : 2; /* [ 3: 2],          r,        0x3 */
+            uint32_t tzc_s12_tzsid_en : 2; /* [ 5: 4],          r,        0x3 */
+            uint32_t tzc_s13_tzsid_en : 2; /* [ 7: 6],          r,        0x3 */
+            uint32_t tzc_s14_tzsid_en : 2; /* [ 9: 8],          r,        0x3 */
+            uint32_t tzc_s15_tzsid_en : 2; /* [11:10],          r,        0x3 */
+            uint32_t tzc_s16_tzsid_en : 2; /* [13:12],          r,        0x3 */
+            uint32_t tzc_s17_tzsid_en : 2; /* [15:14],          r,        0x3 */
+            uint32_t tzc_s18_tzsid_en : 2; /* [17:16],          r,        0x3 */
+            uint32_t tzc_s19_tzsid_en : 2; /* [19:18],          r,        0x3 */
+            uint32_t tzc_s1a_tzsid_en : 2; /* [21:20],          r,        0x3 */
+            uint32_t tzc_s1b_tzsid_en : 2; /* [23:22],          r,        0x3 */
+            uint32_t tzc_s1c_tzsid_en : 2; /* [25:24],          r,        0x3 */
+            uint32_t tzc_s1d_tzsid_en : 2; /* [27:26],          r,        0x3 */
+            uint32_t tzc_s1e_tzsid_en : 2; /* [29:28],          r,        0x3 */
+            uint32_t tzc_s1f_tzsid_en : 2; /* [31:30],          r,        0x3 */
         } BF;
         uint32_t WORD;
     } tzc_mm_bmx_s1;
@@ -3274,22 +3274,22 @@ struct tzc_nsec_reg {
             uint32_t tzc_codec_s1d_tzsid_lock : 1; /* [   13],          r,        0x0 */
             uint32_t tzc_codec_s1e_tzsid_lock : 1; /* [   14],          r,        0x0 */
             uint32_t tzc_codec_s1f_tzsid_lock : 1; /* [   15],          r,        0x0 */
-            uint32_t tzc_dsp2_s10_tzsid_lock   : 1; /* [   16],          r,        0x0 */
-            uint32_t tzc_dsp2_s11_tzsid_lock   : 1; /* [   17],          r,        0x0 */
-            uint32_t tzc_dsp2_s12_tzsid_lock   : 1; /* [   18],          r,        0x0 */
-            uint32_t tzc_dsp2_s13_tzsid_lock   : 1; /* [   19],          r,        0x0 */
-            uint32_t tzc_dsp2_s14_tzsid_lock   : 1; /* [   20],          r,        0x0 */
-            uint32_t tzc_dsp2_s15_tzsid_lock   : 1; /* [   21],          r,        0x0 */
-            uint32_t tzc_dsp2_s16_tzsid_lock   : 1; /* [   22],          r,        0x0 */
-            uint32_t tzc_dsp2_s17_tzsid_lock   : 1; /* [   23],          r,        0x0 */
-            uint32_t tzc_dsp2_s18_tzsid_lock   : 1; /* [   24],          r,        0x0 */
-            uint32_t tzc_dsp2_s19_tzsid_lock   : 1; /* [   25],          r,        0x0 */
-            uint32_t tzc_dsp2_s1a_tzsid_lock   : 1; /* [   26],          r,        0x0 */
-            uint32_t tzc_dsp2_s1b_tzsid_lock   : 1; /* [   27],          r,        0x0 */
-            uint32_t tzc_dsp2_s1c_tzsid_lock   : 1; /* [   28],          r,        0x0 */
-            uint32_t tzc_dsp2_s1d_tzsid_lock   : 1; /* [   29],          r,        0x0 */
-            uint32_t tzc_dsp2_s1e_tzsid_lock   : 1; /* [   30],          r,        0x0 */
-            uint32_t tzc_dsp2_s1f_tzsid_lock   : 1; /* [   31],          r,        0x0 */
+            uint32_t tzc_s10_tzsid_lock       : 1; /* [   16],          r,        0x0 */
+            uint32_t tzc_s11_tzsid_lock       : 1; /* [   17],          r,        0x0 */
+            uint32_t tzc_s12_tzsid_lock       : 1; /* [   18],          r,        0x0 */
+            uint32_t tzc_s13_tzsid_lock       : 1; /* [   19],          r,        0x0 */
+            uint32_t tzc_s14_tzsid_lock       : 1; /* [   20],          r,        0x0 */
+            uint32_t tzc_s15_tzsid_lock       : 1; /* [   21],          r,        0x0 */
+            uint32_t tzc_s16_tzsid_lock       : 1; /* [   22],          r,        0x0 */
+            uint32_t tzc_s17_tzsid_lock       : 1; /* [   23],          r,        0x0 */
+            uint32_t tzc_s18_tzsid_lock       : 1; /* [   24],          r,        0x0 */
+            uint32_t tzc_s19_tzsid_lock       : 1; /* [   25],          r,        0x0 */
+            uint32_t tzc_s1a_tzsid_lock       : 1; /* [   26],          r,        0x0 */
+            uint32_t tzc_s1b_tzsid_lock       : 1; /* [   27],          r,        0x0 */
+            uint32_t tzc_s1c_tzsid_lock       : 1; /* [   28],          r,        0x0 */
+            uint32_t tzc_s1d_tzsid_lock       : 1; /* [   29],          r,        0x0 */
+            uint32_t tzc_s1e_tzsid_lock       : 1; /* [   30],          r,        0x0 */
+            uint32_t tzc_s1f_tzsid_lock       : 1; /* [   31],          r,        0x0 */
         } BF;
         uint32_t WORD;
     } tzc_mm_bmx_s_lock1;
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/tzc_sec_reg.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/tzc_sec_reg.h
old mode 100644
new mode 100755
similarity index 90%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/tzc_sec_reg.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/tzc_sec_reg.h
index 450c8def46..bdce232ec9
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/regs/tzc_sec_reg.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/include/hardware/tzc_sec_reg.h
@@ -1155,100 +1155,100 @@
 #define TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_UMSK (~(((1U << TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_LEN) - 1) << TZC_SEC_TZC_SF_TZSRG_R3_START_MSB_POS))
 
 /* 0x300 : tzc_mm_bmx_tzmid */
-#define TZC_SEC_TZC_MM_BMX_TZMID_OFFSET       (0x300)
-#define TZC_SEC_TZC_MMCPU_TZMID               TZC_SEC_TZC_MMCPU_TZMID
-#define TZC_SEC_TZC_MMCPU_TZMID_POS           (0U)
-#define TZC_SEC_TZC_MMCPU_TZMID_LEN           (1U)
-#define TZC_SEC_TZC_MMCPU_TZMID_MSK           (((1U << TZC_SEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_POS)
-#define TZC_SEC_TZC_MMCPU_TZMID_UMSK          (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_POS))
-#define TZC_SEC_TZC_BLAI_TZMID                TZC_SEC_TZC_BLAI_TZMID
-#define TZC_SEC_TZC_BLAI_TZMID_POS            (1U)
-#define TZC_SEC_TZC_BLAI_TZMID_LEN            (1U)
-#define TZC_SEC_TZC_BLAI_TZMID_MSK            (((1U << TZC_SEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_POS)
-#define TZC_SEC_TZC_BLAI_TZMID_UMSK           (~(((1U << TZC_SEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_POS))
-#define TZC_SEC_TZC_CODEC_TZMID               TZC_SEC_TZC_CODEC_TZMID
-#define TZC_SEC_TZC_CODEC_TZMID_POS           (2U)
-#define TZC_SEC_TZC_CODEC_TZMID_LEN           (1U)
-#define TZC_SEC_TZC_CODEC_TZMID_MSK           (((1U << TZC_SEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_POS)
-#define TZC_SEC_TZC_CODEC_TZMID_UMSK          (~(((1U << TZC_SEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_POS))
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID          TZC_SEC_TZC_DSP2_SUBSYS_TZMID
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_POS      (3U)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LEN      (1U)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_MSK      (((1U << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LEN) - 1) << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_POS)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_UMSK     (~(((1U << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LEN) - 1) << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_POS))
-#define TZC_SEC_TZC_X2DDMA_TZMID              TZC_SEC_TZC_X2DDMA_TZMID
-#define TZC_SEC_TZC_X2DDMA_TZMID_POS          (4U)
-#define TZC_SEC_TZC_X2DDMA_TZMID_LEN          (1U)
-#define TZC_SEC_TZC_X2DDMA_TZMID_MSK          (((1U << TZC_SEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_POS)
-#define TZC_SEC_TZC_X2DDMA_TZMID_UMSK         (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_POS))
-#define TZC_SEC_TZC_XDMA_TZMID                TZC_SEC_TZC_XDMA_TZMID
-#define TZC_SEC_TZC_XDMA_TZMID_POS            (5U)
-#define TZC_SEC_TZC_XDMA_TZMID_LEN            (1U)
-#define TZC_SEC_TZC_XDMA_TZMID_MSK            (((1U << TZC_SEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_POS)
-#define TZC_SEC_TZC_XDMA_TZMID_UMSK           (~(((1U << TZC_SEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_POS))
-#define TZC_SEC_TZC_MMCPU_TZMID_SEL           TZC_SEC_TZC_MMCPU_TZMID_SEL
-#define TZC_SEC_TZC_MMCPU_TZMID_SEL_POS       (16U)
-#define TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN       (1U)
-#define TZC_SEC_TZC_MMCPU_TZMID_SEL_MSK       (((1U << TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_SEL_POS)
-#define TZC_SEC_TZC_MMCPU_TZMID_SEL_UMSK      (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_SEL_POS))
-#define TZC_SEC_TZC_BLAI_TZMID_SEL            TZC_SEC_TZC_BLAI_TZMID_SEL
-#define TZC_SEC_TZC_BLAI_TZMID_SEL_POS        (17U)
-#define TZC_SEC_TZC_BLAI_TZMID_SEL_LEN        (1U)
-#define TZC_SEC_TZC_BLAI_TZMID_SEL_MSK        (((1U << TZC_SEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_SEL_POS)
-#define TZC_SEC_TZC_BLAI_TZMID_SEL_UMSK       (~(((1U << TZC_SEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_SEL_POS))
-#define TZC_SEC_TZC_CODEC_TZMID_SEL           TZC_SEC_TZC_CODEC_TZMID_SEL
-#define TZC_SEC_TZC_CODEC_TZMID_SEL_POS       (18U)
-#define TZC_SEC_TZC_CODEC_TZMID_SEL_LEN       (1U)
-#define TZC_SEC_TZC_CODEC_TZMID_SEL_MSK       (((1U << TZC_SEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_SEL_POS)
-#define TZC_SEC_TZC_CODEC_TZMID_SEL_UMSK      (~(((1U << TZC_SEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_SEL_POS))
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL      TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_POS  (19U)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_LEN  (1U)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_MSK  (((1U << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_POS)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_SEL_POS))
-#define TZC_SEC_TZC_X2DDMA_TZMID_SEL          TZC_SEC_TZC_X2DDMA_TZMID_SEL
-#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS      (20U)
-#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN      (1U)
-#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_MSK      (((1U << TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS)
-#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_UMSK     (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS))
-#define TZC_SEC_TZC_XDMA_TZMID_SEL            TZC_SEC_TZC_XDMA_TZMID_SEL
-#define TZC_SEC_TZC_XDMA_TZMID_SEL_POS        (21U)
-#define TZC_SEC_TZC_XDMA_TZMID_SEL_LEN        (1U)
-#define TZC_SEC_TZC_XDMA_TZMID_SEL_MSK        (((1U << TZC_SEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_SEL_POS)
-#define TZC_SEC_TZC_XDMA_TZMID_SEL_UMSK       (~(((1U << TZC_SEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_SEL_POS))
+#define TZC_SEC_TZC_MM_BMX_TZMID_OFFSET   (0x300)
+#define TZC_SEC_TZC_MMCPU_TZMID           TZC_SEC_TZC_MMCPU_TZMID
+#define TZC_SEC_TZC_MMCPU_TZMID_POS       (0U)
+#define TZC_SEC_TZC_MMCPU_TZMID_LEN       (1U)
+#define TZC_SEC_TZC_MMCPU_TZMID_MSK       (((1U << TZC_SEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_POS)
+#define TZC_SEC_TZC_MMCPU_TZMID_UMSK      (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_POS))
+#define TZC_SEC_TZC_BLAI_TZMID            TZC_SEC_TZC_BLAI_TZMID
+#define TZC_SEC_TZC_BLAI_TZMID_POS        (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_LEN        (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_MSK        (((1U << TZC_SEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_POS)
+#define TZC_SEC_TZC_BLAI_TZMID_UMSK       (~(((1U << TZC_SEC_TZC_BLAI_TZMID_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_POS))
+#define TZC_SEC_TZC_CODEC_TZMID           TZC_SEC_TZC_CODEC_TZMID
+#define TZC_SEC_TZC_CODEC_TZMID_POS       (2U)
+#define TZC_SEC_TZC_CODEC_TZMID_LEN       (1U)
+#define TZC_SEC_TZC_CODEC_TZMID_MSK       (((1U << TZC_SEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_POS)
+#define TZC_SEC_TZC_CODEC_TZMID_UMSK      (~(((1U << TZC_SEC_TZC_CODEC_TZMID_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_POS))
+#define TZC_SEC_TZC_SUBSYS_TZMID          TZC_SEC_TZC_SUBSYS_TZMID
+#define TZC_SEC_TZC_SUBSYS_TZMID_POS      (3U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LEN      (1U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_MSK      (((1U << TZC_SEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_POS)
+#define TZC_SEC_TZC_SUBSYS_TZMID_UMSK     (~(((1U << TZC_SEC_TZC_SUBSYS_TZMID_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_POS))
+#define TZC_SEC_TZC_X2DDMA_TZMID          TZC_SEC_TZC_X2DDMA_TZMID
+#define TZC_SEC_TZC_X2DDMA_TZMID_POS      (4U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LEN      (1U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_MSK      (((1U << TZC_SEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_POS)
+#define TZC_SEC_TZC_X2DDMA_TZMID_UMSK     (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_POS))
+#define TZC_SEC_TZC_XDMA_TZMID            TZC_SEC_TZC_XDMA_TZMID
+#define TZC_SEC_TZC_XDMA_TZMID_POS        (5U)
+#define TZC_SEC_TZC_XDMA_TZMID_LEN        (1U)
+#define TZC_SEC_TZC_XDMA_TZMID_MSK        (((1U << TZC_SEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_POS)
+#define TZC_SEC_TZC_XDMA_TZMID_UMSK       (~(((1U << TZC_SEC_TZC_XDMA_TZMID_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_POS))
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL       TZC_SEC_TZC_MMCPU_TZMID_SEL
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_POS   (16U)
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN   (1U)
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_MSK   (((1U << TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_SEL_POS)
+#define TZC_SEC_TZC_MMCPU_TZMID_SEL_UMSK  (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_SEL_POS))
+#define TZC_SEC_TZC_BLAI_TZMID_SEL        TZC_SEC_TZC_BLAI_TZMID_SEL
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_POS    (17U)
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_LEN    (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_MSK    (((1U << TZC_SEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_SEL_POS)
+#define TZC_SEC_TZC_BLAI_TZMID_SEL_UMSK   (~(((1U << TZC_SEC_TZC_BLAI_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_SEL_POS))
+#define TZC_SEC_TZC_CODEC_TZMID_SEL       TZC_SEC_TZC_CODEC_TZMID_SEL
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_POS   (18U)
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_LEN   (1U)
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_MSK   (((1U << TZC_SEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_SEL_POS)
+#define TZC_SEC_TZC_CODEC_TZMID_SEL_UMSK  (~(((1U << TZC_SEC_TZC_CODEC_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_SEL_POS))
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL      TZC_SEC_TZC_SUBSYS_TZMID_SEL
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_POS  (19U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_LEN  (1U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_MSK  (((1U << TZC_SEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_SEL_POS)
+#define TZC_SEC_TZC_SUBSYS_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_SUBSYS_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_SEL_POS))
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL      TZC_SEC_TZC_X2DDMA_TZMID_SEL
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS  (20U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN  (1U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_MSK  (((1U << TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS)
+#define TZC_SEC_TZC_X2DDMA_TZMID_SEL_UMSK (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_SEL_POS))
+#define TZC_SEC_TZC_XDMA_TZMID_SEL        TZC_SEC_TZC_XDMA_TZMID_SEL
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_POS    (21U)
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_LEN    (1U)
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_MSK    (((1U << TZC_SEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_SEL_POS)
+#define TZC_SEC_TZC_XDMA_TZMID_SEL_UMSK   (~(((1U << TZC_SEC_TZC_XDMA_TZMID_SEL_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_SEL_POS))
 
 /* 0x304 : tzc_mm_bmx_tzmid_lock */
-#define TZC_SEC_TZC_MM_BMX_TZMID_LOCK_OFFSET   (0x304)
-#define TZC_SEC_TZC_MMCPU_TZMID_LOCK           TZC_SEC_TZC_MMCPU_TZMID_LOCK
-#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS       (0U)
-#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN       (1U)
-#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_MSK       (((1U << TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS)
-#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_UMSK      (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS))
-#define TZC_SEC_TZC_BLAI_TZMID_LOCK            TZC_SEC_TZC_BLAI_TZMID_LOCK
-#define TZC_SEC_TZC_BLAI_TZMID_LOCK_POS        (1U)
-#define TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN        (1U)
-#define TZC_SEC_TZC_BLAI_TZMID_LOCK_MSK        (((1U << TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_LOCK_POS)
-#define TZC_SEC_TZC_BLAI_TZMID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_LOCK_POS))
-#define TZC_SEC_TZC_CODEC_TZMID_LOCK           TZC_SEC_TZC_CODEC_TZMID_LOCK
-#define TZC_SEC_TZC_CODEC_TZMID_LOCK_POS       (2U)
-#define TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN       (1U)
-#define TZC_SEC_TZC_CODEC_TZMID_LOCK_MSK       (((1U << TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_LOCK_POS)
-#define TZC_SEC_TZC_CODEC_TZMID_LOCK_UMSK      (~(((1U << TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK      TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_POS  (3U)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_LEN  (1U)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_MSK  (((1U << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_SUBSYS_TZMID_LOCK_POS))
-#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK          TZC_SEC_TZC_X2DDMA_TZMID_LOCK
-#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS      (4U)
-#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN      (1U)
-#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_MSK      (((1U << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS)
-#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_UMSK     (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS))
-#define TZC_SEC_TZC_XDMA_TZMID_LOCK            TZC_SEC_TZC_XDMA_TZMID_LOCK
-#define TZC_SEC_TZC_XDMA_TZMID_LOCK_POS        (5U)
-#define TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN        (1U)
-#define TZC_SEC_TZC_XDMA_TZMID_LOCK_MSK        (((1U << TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_LOCK_POS)
-#define TZC_SEC_TZC_XDMA_TZMID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_MM_BMX_TZMID_LOCK_OFFSET (0x304)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK         TZC_SEC_TZC_MMCPU_TZMID_LOCK
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS     (0U)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN     (1U)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_MSK     (((1U << TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_MMCPU_TZMID_LOCK_UMSK    (~(((1U << TZC_SEC_TZC_MMCPU_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_MMCPU_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK          TZC_SEC_TZC_BLAI_TZMID_LOCK
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_POS      (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN      (1U)
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_MSK      (((1U << TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_BLAI_TZMID_LOCK_UMSK     (~(((1U << TZC_SEC_TZC_BLAI_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_BLAI_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK         TZC_SEC_TZC_CODEC_TZMID_LOCK
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_POS     (2U)
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN     (1U)
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_MSK     (((1U << TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_CODEC_TZMID_LOCK_UMSK    (~(((1U << TZC_SEC_TZC_CODEC_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK        TZC_SEC_TZC_SUBSYS_TZMID_LOCK
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_POS    (3U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_MSK    (((1U << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_SUBSYS_TZMID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_SUBSYS_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK        TZC_SEC_TZC_X2DDMA_TZMID_LOCK
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS    (4U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN    (1U)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_MSK    (((1U << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_X2DDMA_TZMID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_X2DDMA_TZMID_LOCK_POS))
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK          TZC_SEC_TZC_XDMA_TZMID_LOCK
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_POS      (5U)
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN      (1U)
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_MSK      (((1U << TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_LOCK_POS)
+#define TZC_SEC_TZC_XDMA_TZMID_LOCK_UMSK     (~(((1U << TZC_SEC_TZC_XDMA_TZMID_LOCK_LEN) - 1) << TZC_SEC_TZC_XDMA_TZMID_LOCK_POS))
 
 /* 0x308 : tzc_mm_bmx_s0 */
 #define TZC_SEC_TZC_MM_BMX_S0_OFFSET         (0x308)
@@ -1334,87 +1334,87 @@
 #define TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_MMPERI_S1F_TZSID_EN_POS))
 
 /* 0x30C : tzc_mm_bmx_s1 */
-#define TZC_SEC_TZC_MM_BMX_S1_OFFSET      (0x30C)
-#define TZC_SEC_TZC_DSP2_S10_TZSID_EN      TZC_SEC_TZC_DSP2_S10_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S10_TZSID_EN_POS  (0U)
-#define TZC_SEC_TZC_DSP2_S10_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S10_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S10_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S10_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S10_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S11_TZSID_EN      TZC_SEC_TZC_DSP2_S11_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S11_TZSID_EN_POS  (2U)
-#define TZC_SEC_TZC_DSP2_S11_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S11_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S11_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S11_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S11_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S12_TZSID_EN      TZC_SEC_TZC_DSP2_S12_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S12_TZSID_EN_POS  (4U)
-#define TZC_SEC_TZC_DSP2_S12_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S12_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S12_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S12_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S12_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S13_TZSID_EN      TZC_SEC_TZC_DSP2_S13_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S13_TZSID_EN_POS  (6U)
-#define TZC_SEC_TZC_DSP2_S13_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S13_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S13_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S13_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S13_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S14_TZSID_EN      TZC_SEC_TZC_DSP2_S14_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S14_TZSID_EN_POS  (8U)
-#define TZC_SEC_TZC_DSP2_S14_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S14_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S14_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S14_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S14_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S15_TZSID_EN      TZC_SEC_TZC_DSP2_S15_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S15_TZSID_EN_POS  (10U)
-#define TZC_SEC_TZC_DSP2_S15_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S15_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S15_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S15_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S15_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S16_TZSID_EN      TZC_SEC_TZC_DSP2_S16_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S16_TZSID_EN_POS  (12U)
-#define TZC_SEC_TZC_DSP2_S16_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S16_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S16_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S16_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S16_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S17_TZSID_EN      TZC_SEC_TZC_DSP2_S17_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S17_TZSID_EN_POS  (14U)
-#define TZC_SEC_TZC_DSP2_S17_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S17_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S17_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S17_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S17_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S18_TZSID_EN      TZC_SEC_TZC_DSP2_S18_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S18_TZSID_EN_POS  (16U)
-#define TZC_SEC_TZC_DSP2_S18_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S18_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S18_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S18_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S18_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S19_TZSID_EN      TZC_SEC_TZC_DSP2_S19_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S19_TZSID_EN_POS  (18U)
-#define TZC_SEC_TZC_DSP2_S19_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S19_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S19_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S19_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S19_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_EN      TZC_SEC_TZC_DSP2_S1A_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_EN_POS  (20U)
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1A_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1A_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_EN      TZC_SEC_TZC_DSP2_S1B_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_EN_POS  (22U)
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1B_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1B_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_EN      TZC_SEC_TZC_DSP2_S1C_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_EN_POS  (24U)
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1C_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1C_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_EN      TZC_SEC_TZC_DSP2_S1D_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_EN_POS  (26U)
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1D_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1D_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_EN      TZC_SEC_TZC_DSP2_S1E_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_EN_POS  (28U)
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1E_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1E_TZSID_EN_POS))
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_EN      TZC_SEC_TZC_DSP2_S1F_TZSID_EN
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_EN_POS  (30U)
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_EN_LEN  (2U)
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_DSP2_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1F_TZSID_EN_POS)
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_DSP2_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_DSP2_S1F_TZSID_EN_POS))
+#define TZC_SEC_TZC_MM_BMX_S1_OFFSET  (0x30C)
+#define TZC_SEC_TZC_S10_TZSID_EN      TZC_SEC_TZC_S10_TZSID_EN
+#define TZC_SEC_TZC_S10_TZSID_EN_POS  (0U)
+#define TZC_SEC_TZC_S10_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S10_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_EN_POS)
+#define TZC_SEC_TZC_S10_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S10_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_EN_POS))
+#define TZC_SEC_TZC_S11_TZSID_EN      TZC_SEC_TZC_S11_TZSID_EN
+#define TZC_SEC_TZC_S11_TZSID_EN_POS  (2U)
+#define TZC_SEC_TZC_S11_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S11_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_EN_POS)
+#define TZC_SEC_TZC_S11_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S11_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_EN_POS))
+#define TZC_SEC_TZC_S12_TZSID_EN      TZC_SEC_TZC_S12_TZSID_EN
+#define TZC_SEC_TZC_S12_TZSID_EN_POS  (4U)
+#define TZC_SEC_TZC_S12_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S12_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_EN_POS)
+#define TZC_SEC_TZC_S12_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S12_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_EN_POS))
+#define TZC_SEC_TZC_S13_TZSID_EN      TZC_SEC_TZC_S13_TZSID_EN
+#define TZC_SEC_TZC_S13_TZSID_EN_POS  (6U)
+#define TZC_SEC_TZC_S13_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S13_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_EN_POS)
+#define TZC_SEC_TZC_S13_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S13_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_EN_POS))
+#define TZC_SEC_TZC_S14_TZSID_EN      TZC_SEC_TZC_S14_TZSID_EN
+#define TZC_SEC_TZC_S14_TZSID_EN_POS  (8U)
+#define TZC_SEC_TZC_S14_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S14_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_EN_POS)
+#define TZC_SEC_TZC_S14_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S14_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_EN_POS))
+#define TZC_SEC_TZC_S15_TZSID_EN      TZC_SEC_TZC_S15_TZSID_EN
+#define TZC_SEC_TZC_S15_TZSID_EN_POS  (10U)
+#define TZC_SEC_TZC_S15_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S15_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_EN_POS)
+#define TZC_SEC_TZC_S15_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S15_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_EN_POS))
+#define TZC_SEC_TZC_S16_TZSID_EN      TZC_SEC_TZC_S16_TZSID_EN
+#define TZC_SEC_TZC_S16_TZSID_EN_POS  (12U)
+#define TZC_SEC_TZC_S16_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S16_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_EN_POS)
+#define TZC_SEC_TZC_S16_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S16_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_EN_POS))
+#define TZC_SEC_TZC_S17_TZSID_EN      TZC_SEC_TZC_S17_TZSID_EN
+#define TZC_SEC_TZC_S17_TZSID_EN_POS  (14U)
+#define TZC_SEC_TZC_S17_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S17_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_EN_POS)
+#define TZC_SEC_TZC_S17_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S17_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_EN_POS))
+#define TZC_SEC_TZC_S18_TZSID_EN      TZC_SEC_TZC_S18_TZSID_EN
+#define TZC_SEC_TZC_S18_TZSID_EN_POS  (16U)
+#define TZC_SEC_TZC_S18_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S18_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_EN_POS)
+#define TZC_SEC_TZC_S18_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S18_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_EN_POS))
+#define TZC_SEC_TZC_S19_TZSID_EN      TZC_SEC_TZC_S19_TZSID_EN
+#define TZC_SEC_TZC_S19_TZSID_EN_POS  (18U)
+#define TZC_SEC_TZC_S19_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S19_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_EN_POS)
+#define TZC_SEC_TZC_S19_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S19_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1A_TZSID_EN      TZC_SEC_TZC_S1A_TZSID_EN
+#define TZC_SEC_TZC_S1A_TZSID_EN_POS  (20U)
+#define TZC_SEC_TZC_S1A_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S1A_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1A_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1A_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1B_TZSID_EN      TZC_SEC_TZC_S1B_TZSID_EN
+#define TZC_SEC_TZC_S1B_TZSID_EN_POS  (22U)
+#define TZC_SEC_TZC_S1B_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S1B_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1B_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1B_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1C_TZSID_EN      TZC_SEC_TZC_S1C_TZSID_EN
+#define TZC_SEC_TZC_S1C_TZSID_EN_POS  (24U)
+#define TZC_SEC_TZC_S1C_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S1C_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1C_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1C_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1D_TZSID_EN      TZC_SEC_TZC_S1D_TZSID_EN
+#define TZC_SEC_TZC_S1D_TZSID_EN_POS  (26U)
+#define TZC_SEC_TZC_S1D_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S1D_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1D_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1D_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1E_TZSID_EN      TZC_SEC_TZC_S1E_TZSID_EN
+#define TZC_SEC_TZC_S1E_TZSID_EN_POS  (28U)
+#define TZC_SEC_TZC_S1E_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S1E_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1E_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1E_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_EN_POS))
+#define TZC_SEC_TZC_S1F_TZSID_EN      TZC_SEC_TZC_S1F_TZSID_EN
+#define TZC_SEC_TZC_S1F_TZSID_EN_POS  (30U)
+#define TZC_SEC_TZC_S1F_TZSID_EN_LEN  (2U)
+#define TZC_SEC_TZC_S1F_TZSID_EN_MSK  (((1U << TZC_SEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_EN_POS)
+#define TZC_SEC_TZC_S1F_TZSID_EN_UMSK (~(((1U << TZC_SEC_TZC_S1F_TZSID_EN_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_EN_POS))
 
 /* 0x310 : tzc_mm_bmx_s2 */
 #define TZC_SEC_TZC_MM_BMX_S2_OFFSET        (0x310)
@@ -1664,86 +1664,86 @@
 #define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_LEN  (1U)
 #define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_MSK  (((1U << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_POS)
 #define TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_UMSK (~(((1U << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_CODEC_S1F_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S10_TZSID_LOCK        TZC_SEC_TZC_DSP2_S10_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_POS    (16U)
-#define TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S10_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S11_TZSID_LOCK        TZC_SEC_TZC_DSP2_S11_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_POS    (17U)
-#define TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S11_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S12_TZSID_LOCK        TZC_SEC_TZC_DSP2_S12_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_POS    (18U)
-#define TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S12_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S13_TZSID_LOCK        TZC_SEC_TZC_DSP2_S13_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_POS    (19U)
-#define TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S13_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S14_TZSID_LOCK        TZC_SEC_TZC_DSP2_S14_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_POS    (20U)
-#define TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S14_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S15_TZSID_LOCK        TZC_SEC_TZC_DSP2_S15_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_POS    (21U)
-#define TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S15_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S16_TZSID_LOCK        TZC_SEC_TZC_DSP2_S16_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_POS    (22U)
-#define TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S16_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S17_TZSID_LOCK        TZC_SEC_TZC_DSP2_S17_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_POS    (23U)
-#define TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S17_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S18_TZSID_LOCK        TZC_SEC_TZC_DSP2_S18_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_POS    (24U)
-#define TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S18_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S19_TZSID_LOCK        TZC_SEC_TZC_DSP2_S19_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_POS    (25U)
-#define TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S19_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK        TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_POS    (26U)
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1A_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK        TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_POS    (27U)
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1B_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK        TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_POS    (28U)
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1C_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK        TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_POS    (29U)
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1D_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK        TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_POS    (30U)
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1E_TZSID_LOCK_POS))
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK        TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_POS    (31U)
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_LEN    (1U)
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_MSK    (((1U << TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_POS)
-#define TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_UMSK   (~(((1U << TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_DSP2_S1F_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S10_TZSID_LOCK            TZC_SEC_TZC_S10_TZSID_LOCK
+#define TZC_SEC_TZC_S10_TZSID_LOCK_POS        (16U)
+#define TZC_SEC_TZC_S10_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S10_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S10_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S10_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S10_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S11_TZSID_LOCK            TZC_SEC_TZC_S11_TZSID_LOCK
+#define TZC_SEC_TZC_S11_TZSID_LOCK_POS        (17U)
+#define TZC_SEC_TZC_S11_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S11_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S11_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S11_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S11_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S12_TZSID_LOCK            TZC_SEC_TZC_S12_TZSID_LOCK
+#define TZC_SEC_TZC_S12_TZSID_LOCK_POS        (18U)
+#define TZC_SEC_TZC_S12_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S12_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S12_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S12_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S12_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S13_TZSID_LOCK            TZC_SEC_TZC_S13_TZSID_LOCK
+#define TZC_SEC_TZC_S13_TZSID_LOCK_POS        (19U)
+#define TZC_SEC_TZC_S13_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S13_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S13_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S13_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S13_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S14_TZSID_LOCK            TZC_SEC_TZC_S14_TZSID_LOCK
+#define TZC_SEC_TZC_S14_TZSID_LOCK_POS        (20U)
+#define TZC_SEC_TZC_S14_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S14_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S14_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S14_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S14_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S15_TZSID_LOCK            TZC_SEC_TZC_S15_TZSID_LOCK
+#define TZC_SEC_TZC_S15_TZSID_LOCK_POS        (21U)
+#define TZC_SEC_TZC_S15_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S15_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S15_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S15_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S15_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S16_TZSID_LOCK            TZC_SEC_TZC_S16_TZSID_LOCK
+#define TZC_SEC_TZC_S16_TZSID_LOCK_POS        (22U)
+#define TZC_SEC_TZC_S16_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S16_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S16_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S16_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S16_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S17_TZSID_LOCK            TZC_SEC_TZC_S17_TZSID_LOCK
+#define TZC_SEC_TZC_S17_TZSID_LOCK_POS        (23U)
+#define TZC_SEC_TZC_S17_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S17_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S17_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S17_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S17_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S18_TZSID_LOCK            TZC_SEC_TZC_S18_TZSID_LOCK
+#define TZC_SEC_TZC_S18_TZSID_LOCK_POS        (24U)
+#define TZC_SEC_TZC_S18_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S18_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S18_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S18_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S18_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S19_TZSID_LOCK            TZC_SEC_TZC_S19_TZSID_LOCK
+#define TZC_SEC_TZC_S19_TZSID_LOCK_POS        (25U)
+#define TZC_SEC_TZC_S19_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S19_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S19_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S19_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S19_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1A_TZSID_LOCK            TZC_SEC_TZC_S1A_TZSID_LOCK
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_POS        (26U)
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1A_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S1A_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1A_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1B_TZSID_LOCK            TZC_SEC_TZC_S1B_TZSID_LOCK
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_POS        (27U)
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1B_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S1B_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1B_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1C_TZSID_LOCK            TZC_SEC_TZC_S1C_TZSID_LOCK
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_POS        (28U)
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1C_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S1C_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1C_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1D_TZSID_LOCK            TZC_SEC_TZC_S1D_TZSID_LOCK
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_POS        (29U)
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1D_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S1D_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1D_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1E_TZSID_LOCK            TZC_SEC_TZC_S1E_TZSID_LOCK
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_POS        (30U)
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1E_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S1E_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1E_TZSID_LOCK_POS))
+#define TZC_SEC_TZC_S1F_TZSID_LOCK            TZC_SEC_TZC_S1F_TZSID_LOCK
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_POS        (31U)
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_LEN        (1U)
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_MSK        (((1U << TZC_SEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_LOCK_POS)
+#define TZC_SEC_TZC_S1F_TZSID_LOCK_UMSK       (~(((1U << TZC_SEC_TZC_S1F_TZSID_LOCK_LEN) - 1) << TZC_SEC_TZC_S1F_TZSID_LOCK_POS))
 
 /* 0x340 : tzc_l2sram_tzsrg_ctrl */
 #define TZC_SEC_TZC_L2SRAM_TZSRG_CTRL_OFFSET   (0x340)
@@ -3133,14 +3133,14 @@ struct tzc_sec_reg {
             uint32_t tzc_mmcpu_tzmid          : 1;  /* [    0],        r/w,        0x0 */
             uint32_t tzc_blai_tzmid           : 1;  /* [    1],        r/w,        0x0 */
             uint32_t tzc_codec_tzmid          : 1;  /* [    2],        r/w,        0x0 */
-            uint32_t tzc_dsp2_subsys_tzmid     : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t tzc_subsys_tzmid     : 1;  /* [    3],        r/w,        0x0 */
             uint32_t tzc_x2ddma_tzmid         : 1;  /* [    4],        r/w,        0x0 */
             uint32_t tzc_xdma_tzmid           : 1;  /* [    5],        r/w,        0x0 */
             uint32_t reserved_6_15            : 10; /* [15: 6],       rsvd,        0x0 */
             uint32_t tzc_mmcpu_tzmid_sel      : 1;  /* [   16],        r/w,        0x1 */
             uint32_t tzc_blai_tzmid_sel       : 1;  /* [   17],        r/w,        0x1 */
             uint32_t tzc_codec_tzmid_sel      : 1;  /* [   18],        r/w,        0x1 */
-            uint32_t tzc_dsp2_subsys_tzmid_sel : 1;  /* [   19],        r/w,        0x1 */
+            uint32_t tzc_subsys_tzmid_sel : 1;  /* [   19],        r/w,        0x1 */
             uint32_t tzc_x2ddma_tzmid_sel     : 1;  /* [   20],        r/w,        0x1 */
             uint32_t tzc_xdma_tzmid_sel       : 1;  /* [   21],        r/w,        0x1 */
             uint32_t reserved_22_31           : 10; /* [31:22],       rsvd,        0x0 */
@@ -3154,7 +3154,7 @@ struct tzc_sec_reg {
             uint32_t tzc_mmcpu_tzmid_lock      : 1;  /* [    0],        r/w,        0x0 */
             uint32_t tzc_blai_tzmid_lock       : 1;  /* [    1],        r/w,        0x0 */
             uint32_t tzc_codec_tzmid_lock      : 1;  /* [    2],        r/w,        0x0 */
-            uint32_t tzc_dsp2_subsys_tzmid_lock : 1;  /* [    3],        r/w,        0x0 */
+            uint32_t tzc_subsys_tzmid_lock : 1;  /* [    3],        r/w,        0x0 */
             uint32_t tzc_x2ddma_tzmid_lock     : 1;  /* [    4],        r/w,        0x0 */
             uint32_t tzc_xdma_tzmid_lock       : 1;  /* [    5],        r/w,        0x0 */
             uint32_t reserved_6_31             : 26; /* [31: 6],       rsvd,        0x0 */
@@ -3188,22 +3188,22 @@ struct tzc_sec_reg {
     /* 0x30C : tzc_mm_bmx_s1 */
     union {
         struct {
-            uint32_t tzc_dsp2_s10_tzsid_en : 2; /* [ 1: 0],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s11_tzsid_en : 2; /* [ 3: 2],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s12_tzsid_en : 2; /* [ 5: 4],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s13_tzsid_en : 2; /* [ 7: 6],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s14_tzsid_en : 2; /* [ 9: 8],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s15_tzsid_en : 2; /* [11:10],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s16_tzsid_en : 2; /* [13:12],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s17_tzsid_en : 2; /* [15:14],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s18_tzsid_en : 2; /* [17:16],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s19_tzsid_en : 2; /* [19:18],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s1a_tzsid_en : 2; /* [21:20],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s1b_tzsid_en : 2; /* [23:22],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s1c_tzsid_en : 2; /* [25:24],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s1d_tzsid_en : 2; /* [27:26],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s1e_tzsid_en : 2; /* [29:28],        r/w,        0x3 */
-            uint32_t tzc_dsp2_s1f_tzsid_en : 2; /* [31:30],        r/w,        0x3 */
+            uint32_t tzc_s10_tzsid_en : 2; /* [ 1: 0],        r/w,        0x3 */
+            uint32_t tzc_s11_tzsid_en : 2; /* [ 3: 2],        r/w,        0x3 */
+            uint32_t tzc_s12_tzsid_en : 2; /* [ 5: 4],        r/w,        0x3 */
+            uint32_t tzc_s13_tzsid_en : 2; /* [ 7: 6],        r/w,        0x3 */
+            uint32_t tzc_s14_tzsid_en : 2; /* [ 9: 8],        r/w,        0x3 */
+            uint32_t tzc_s15_tzsid_en : 2; /* [11:10],        r/w,        0x3 */
+            uint32_t tzc_s16_tzsid_en : 2; /* [13:12],        r/w,        0x3 */
+            uint32_t tzc_s17_tzsid_en : 2; /* [15:14],        r/w,        0x3 */
+            uint32_t tzc_s18_tzsid_en : 2; /* [17:16],        r/w,        0x3 */
+            uint32_t tzc_s19_tzsid_en : 2; /* [19:18],        r/w,        0x3 */
+            uint32_t tzc_s1a_tzsid_en : 2; /* [21:20],        r/w,        0x3 */
+            uint32_t tzc_s1b_tzsid_en : 2; /* [23:22],        r/w,        0x3 */
+            uint32_t tzc_s1c_tzsid_en : 2; /* [25:24],        r/w,        0x3 */
+            uint32_t tzc_s1d_tzsid_en : 2; /* [27:26],        r/w,        0x3 */
+            uint32_t tzc_s1e_tzsid_en : 2; /* [29:28],        r/w,        0x3 */
+            uint32_t tzc_s1f_tzsid_en : 2; /* [31:30],        r/w,        0x3 */
         } BF;
         uint32_t WORD;
     } tzc_mm_bmx_s1;
@@ -3274,22 +3274,22 @@ struct tzc_sec_reg {
             uint32_t tzc_codec_s1d_tzsid_lock : 1; /* [   13],        r/w,        0x0 */
             uint32_t tzc_codec_s1e_tzsid_lock : 1; /* [   14],        r/w,        0x0 */
             uint32_t tzc_codec_s1f_tzsid_lock : 1; /* [   15],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s10_tzsid_lock   : 1; /* [   16],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s11_tzsid_lock   : 1; /* [   17],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s12_tzsid_lock   : 1; /* [   18],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s13_tzsid_lock   : 1; /* [   19],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s14_tzsid_lock   : 1; /* [   20],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s15_tzsid_lock   : 1; /* [   21],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s16_tzsid_lock   : 1; /* [   22],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s17_tzsid_lock   : 1; /* [   23],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s18_tzsid_lock   : 1; /* [   24],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s19_tzsid_lock   : 1; /* [   25],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s1a_tzsid_lock   : 1; /* [   26],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s1b_tzsid_lock   : 1; /* [   27],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s1c_tzsid_lock   : 1; /* [   28],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s1d_tzsid_lock   : 1; /* [   29],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s1e_tzsid_lock   : 1; /* [   30],        r/w,        0x0 */
-            uint32_t tzc_dsp2_s1f_tzsid_lock   : 1; /* [   31],        r/w,        0x0 */
+            uint32_t tzc_s10_tzsid_lock       : 1; /* [   16],        r/w,        0x0 */
+            uint32_t tzc_s11_tzsid_lock       : 1; /* [   17],        r/w,        0x0 */
+            uint32_t tzc_s12_tzsid_lock       : 1; /* [   18],        r/w,        0x0 */
+            uint32_t tzc_s13_tzsid_lock       : 1; /* [   19],        r/w,        0x0 */
+            uint32_t tzc_s14_tzsid_lock       : 1; /* [   20],        r/w,        0x0 */
+            uint32_t tzc_s15_tzsid_lock       : 1; /* [   21],        r/w,        0x0 */
+            uint32_t tzc_s16_tzsid_lock       : 1; /* [   22],        r/w,        0x0 */
+            uint32_t tzc_s17_tzsid_lock       : 1; /* [   23],        r/w,        0x0 */
+            uint32_t tzc_s18_tzsid_lock       : 1; /* [   24],        r/w,        0x0 */
+            uint32_t tzc_s19_tzsid_lock       : 1; /* [   25],        r/w,        0x0 */
+            uint32_t tzc_s1a_tzsid_lock       : 1; /* [   26],        r/w,        0x0 */
+            uint32_t tzc_s1b_tzsid_lock       : 1; /* [   27],        r/w,        0x0 */
+            uint32_t tzc_s1c_tzsid_lock       : 1; /* [   28],        r/w,        0x0 */
+            uint32_t tzc_s1d_tzsid_lock       : 1; /* [   29],        r/w,        0x0 */
+            uint32_t tzc_s1e_tzsid_lock       : 1; /* [   30],        r/w,        0x0 */
+            uint32_t tzc_s1f_tzsid_lock       : 1; /* [   31],        r/w,        0x0 */
         } BF;
         uint32_t WORD;
     } tzc_mm_bmx_s_lock1;
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/port/bl808_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/port/bl808_clock.c
new file mode 100755
index 0000000000..7927058be8
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/port/bl808_clock.c
@@ -0,0 +1,21 @@
+#include "bflb_clock.h"
+#include "bl808_clock.h"
+
+uint32_t bflb_clk_get_system_clock(uint8_t type)
+{
+    return 0;
+}
+
+uint32_t bflb_clk_get_peripheral_clock(uint8_t type, uint8_t idx)
+{
+    if (type == BFLB_DEVICE_TYPE_UART) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_UART0);
+    } else if (type == BFLB_DEVICE_TYPE_SPI) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SPI0);
+    } else if (type == BFLB_DEVICE_TYPE_I2C) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_I2C0);
+    } else if (type == BFLB_DEVICE_TYPE_SDH) {
+        return Clock_Peripheral_Clock_Get(BL_PERIPHERAL_CLOCK_SDH);
+    }
+    return 0;
+}
\ No newline at end of file
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aon.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_aon.c
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aon.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_aon.c
index 9e1684aabb..d7cd0f7d3c
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_aon.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_aon.c
@@ -338,7 +338,7 @@ BL_Err_Type ATTR_CLOCK_SECTION AON_Trim_USB20_RCAL(void)
     Efuse_Ana_USB20RCAL_Trim_Type trim;
     uint32_t tmpVal = 0;
 
-    EF_Ctrl_Read_USB20RCAL_Trim(&trim);
+    //EF_Ctrl_Read_USB20RCAL_Trim(&trim); //FixZc
     if (trim.trimUsb20rcalAonEn) {
         if (trim.trimUsb20rcalAonParity == EF_Ctrl_Get_Trim_Parity(trim.trimUsb20rcalAon, 6)) {
             tmpVal = BL_RD_REG(AON_BASE, AON_PSW_IRRCV);
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_clock.c
old mode 100644
new mode 100755
similarity index 82%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_clock.c
index c3bfbd22d3..46b94265fc
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_clock.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_clock.c
@@ -84,7 +84,7 @@
  *  @{
  */
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut)
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t pllOut)
 {
     uint8_t xtalType = 0;
     uint32_t tmpVal = 0;
@@ -94,8 +94,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t
     tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_WIFI_PLL_CFG6), GLB_WIFIPLL_SDMIN);
 
     if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
-        switch (xtalType)
-        {
+        switch (xtalType) {
             /* Calculation method:* wifipll_sdmin / calculationDiv * xtal_freq * 1000 * 1000 / cpupll_refdiv_ratio */
             case GLB_XTAL_NONE:
                 return (0);
@@ -130,7 +129,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t
         return (0);
     }
 
-    if ( (vcoFreq >= 955000000) && (vcoFreq <= 965000000) ) {
+    if ((vcoFreq >= 955000000) && (vcoFreq <= 965000000)) {
         /* vcoFreq:959920000~960000000 */
         return (pllOut);
     } else {
@@ -138,7 +137,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_WIFI_PLL_Output(uint32_t
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t pllOut)
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t pllOut)
 {
     uint8_t xtalType = 0;
     uint32_t tmpVal = 0;
@@ -148,8 +147,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t
     tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_CPU_PLL_CFG6), CCI_CPUPLL_SDMIN);
 
     if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
-        switch (xtalType)
-        {
+        switch (xtalType) {
             /* Calculation method:xtal_freq * 1000 * cpupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */
             case GLB_XTAL_NONE:
                 return (0);
@@ -159,15 +157,15 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t
                 break;
             case GLB_XTAL_32M:
                 /* 480000000;400000000;380000000 */
-                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             case GLB_XTAL_38P4M:
                 /* 480000000;399998250;379996750 */
-                vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             case GLB_XTAL_40M:
                 /* 480000000;400000000;380000000 */
-                vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             case GLB_XTAL_26M:
                 /* 479997000;399997500;379996000 */
@@ -175,7 +173,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t
                 break;
             case GLB_XTAL_RC32M:
                 /* 480000000;400000000;380000000 */
-                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             default:
                 return (0);
@@ -184,13 +182,13 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t
         return (0);
     }
 
-    if ( (vcoFreq >= 475000000) && (vcoFreq <= 485000000) ) {
+    if ((vcoFreq >= 475000000) && (vcoFreq <= 485000000)) {
         /* vcoFreq:479997000~480000000 */
         return (pllOut / 100 * 120);
-    } else if ( (vcoFreq >= 395000000 && vcoFreq <= 405000000) ) {
+    } else if ((vcoFreq >= 395000000 && vcoFreq <= 405000000)) {
         /* vcoFreq:399996000~400000000 */
         return (pllOut);
-    } else if ( (vcoFreq >= 375000000 && vcoFreq <= 385000000) ) {
+    } else if ((vcoFreq >= 375000000 && vcoFreq <= 385000000)) {
         /* vcoFreq:379996000~380000000 */
         return (pllOut / 100 * 95);
     } else {
@@ -198,7 +196,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_CPU_PLL_Output(uint32_t
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clockAupllType)
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL_Type clockAupllType)
 {
     uint8_t xtalType = 0;
     uint32_t tmpVal = 0;
@@ -208,8 +206,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL
     tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG6), CCI_AUPLL_SDMIN);
 
     if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
-        switch (xtalType)
-        {
+        switch (xtalType) {
             /* Calculation method:xtal_freq * 1000 * aupll_sdmin / calculationDiv * 1000 / cpupll_refdiv_ratio */
             case GLB_XTAL_NONE:
                 return (0);
@@ -219,15 +216,15 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL
                 break;
             case GLB_XTAL_32M:
                 /* 442367000;451582000 */
-                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             case GLB_XTAL_38P4M:
                 /* 442364000;451579500; */
-                vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 384 * 100 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             case GLB_XTAL_40M:
                 /* 442368000;451582000 */
-                vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 40 * 1000 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             case GLB_XTAL_26M:
                 /* 442368000;451578500 */
@@ -235,7 +232,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL
                 break;
             case GLB_XTAL_RC32M:
                 /* 442367000;451582000 */
-                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000  / 4);
+                vcoFreq = 32 * 1000 * tmpVal / calculationDiv * (1000 / 4);
                 break;
             default:
                 return (0);
@@ -244,10 +241,10 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL
         return (0);
     }
 
-    if ( (vcoFreq >= 451000000) && (vcoFreq <= 452000000) ) {
+    if ((vcoFreq >= 451000000) && (vcoFreq <= 452000000)) {
         /* vcoFreq:451578500~451582000 */
         vcoFreq = 451584000;
-    } else if ( (vcoFreq >= 442000000) && (vcoFreq <= 443000000) ) {
+    } else if ((vcoFreq >= 442000000) && (vcoFreq <= 443000000)) {
         /* vcoFreq:442364000~442368000 */
         vcoFreq = 442368000;
     } else {
@@ -278,17 +275,16 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_AUPLL_Output(CLOCK_AUPLL
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output()
+static inline uint32_t ATTR_CLOCK_SECTION Clock_Get_Audio_PLL_Output()
 {
     uint32_t tmpVal = 0;
 
     tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(CCI_BASE, CCI_AUDIO_PLL_CFG1), CCI_AUPLL_POSTDIV);
 
     return Clock_Get_AUPLL_Output(CLOCK_AUPLL_DIV1) / tmpVal;
-
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
 {
     uint8_t xtalType = 0;
     uint32_t tmpVal = 0;
@@ -298,8 +294,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
     tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG6), GLB_MIPIPLL_SDMIN);
 
     if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
-        switch (xtalType)
-        {
+        switch (xtalType) {
             /* Calculation method:xtal_freq * 1000 or 500 * mipipll_sdmin / calculationDiv * 1000 or 2000 / cpupll_refdiv_ratio */
             case GLB_XTAL_NONE:
                 return (0);
@@ -309,15 +304,15 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
                 break;
             case GLB_XTAL_32M:
                 /* 1500000000 */
-                vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000  / 2);
+                vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);
                 break;
             case GLB_XTAL_38P4M:
                 /* 1500000000 */
-                vcoFreq = 384 * 50 * tmpVal / calculationDiv * (2000  / 2);
+                vcoFreq = 384 * 50 * tmpVal / calculationDiv * (2000 / 2);
                 break;
             case GLB_XTAL_40M:
                 /* 1500000000 */
-                vcoFreq = 40 * 500 * tmpVal / calculationDiv * (2000  / 2);
+                vcoFreq = 40 * 500 * tmpVal / calculationDiv * (2000 / 2);
                 break;
             case GLB_XTAL_26M:
                 /* 1499989000 */
@@ -325,7 +320,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
                 break;
             case GLB_XTAL_RC32M:
                 /* 1500000000 */
-                vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000  / 2);
+                vcoFreq = 32 * 500 * tmpVal / calculationDiv * (2000 / 2);
                 break;
             default:
                 return (0);
@@ -334,7 +329,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
         return (0);
     }
 
-    if ( (vcoFreq >= 1490000000) && (vcoFreq <= 1510000000) ) {
+    if ((vcoFreq >= 1490000000) && (vcoFreq <= 1510000000)) {
         /* vcoFreq:1499989000~1500000000 */
         return (1500000000);
     } else {
@@ -342,7 +337,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_MIPI_PLL_Output()
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
+static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
 {
     uint8_t xtalType = 0;
     uint32_t tmpVal = 0;
@@ -352,8 +347,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
     tmpVal = BL_GET_REG_BITS_VAL(BL_RD_REG(GLB_BASE, GLB_UHS_PLL_CFG6), GLB_UHSPLL_SDMIN);
 
     if (HBN_Get_Xtal_Type(&xtalType) == SUCCESS) {
-        switch (xtalType)
-        {
+        switch (xtalType) {
             /* Calculation method:xtal_freq * 500 or 250 * uhspll_sdmin / calculationDiv * 2000 or 4000 / cpupll_refdiv_ratio */
             case GLB_XTAL_NONE:
                 return (0);
@@ -363,15 +357,15 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
                 break;
             case GLB_XTAL_32M:
                 /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */
-                vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000  / 2);
+                vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);
                 break;
             case GLB_XTAL_38P4M:
                 /* 2299996000;2199992000;2100000000;1999996000;1599992000;1500000000;1399996000;1065992000;799996000;666992000;399992000 */
-                vcoFreq = 384 * 25 * tmpVal / calculationDiv * (4000  / 2);
+                vcoFreq = 384 * 25 * tmpVal / calculationDiv * (4000 / 2);
                 break;
             case GLB_XTAL_40M:
                 /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1065996000;800000000;666992000;400000000 */
-                vcoFreq = 40 * 250 * tmpVal / calculationDiv * (4000  / 2);
+                vcoFreq = 40 * 250 * tmpVal / calculationDiv * (4000 / 2);
                 break;
             case GLB_XTAL_26M:
                 /* 2299996000;2199996000;2099994000;1999994000;1599990000;1499988000;1399988000;1066000000;799994000;666998000;399990000 */
@@ -379,7 +373,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
                 break;
             case GLB_XTAL_RC32M:
                 /* 2300000000;2200000000;2100000000;2000000000;1600000000;1500000000;1400000000;1066000000;800000000;667000000;400000000 */
-                vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000  / 2);
+                vcoFreq = 32 * 250 * tmpVal / calculationDiv * (4000 / 2);
                 break;
             default:
                 return (0);
@@ -388,37 +382,37 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
         return (0);
     }
 
-    if ( (vcoFreq >= 2295000000) && (vcoFreq <= 2305000000) ) {
+    if ((vcoFreq >= 2295000000) && (vcoFreq <= 2305000000)) {
         /* vcoFreq:2299992000~2300000000 */
         return (2300000000);
-    } else if ( (vcoFreq >= 2195000000) && (vcoFreq <= 2205000000) ) {
+    } else if ((vcoFreq >= 2195000000) && (vcoFreq <= 2205000000)) {
         /* vcoFreq:2199992000~2200000000 */
         return (2200000000);
-    } else if ( (vcoFreq >= 2095000000) && (vcoFreq <= 2105000000) ) {
+    } else if ((vcoFreq >= 2095000000) && (vcoFreq <= 2105000000)) {
         /* vcoFreq:2099994000~2100000000 */
         return (2100000000);
-    } else if ( (vcoFreq >= 1995000000 && vcoFreq <= 2005000000) ) {
+    } else if ((vcoFreq >= 1995000000 && vcoFreq <= 2005000000)) {
         /* vcoFreq:1999992000~2000000000 */
         return (2000000000);
-    } else if ( (vcoFreq >= 1595000000 && vcoFreq <= 1605000000) ) {
+    } else if ((vcoFreq >= 1595000000 && vcoFreq <= 1605000000)) {
         /* vcoFreq:1599990000~1600000000 */
         return (1600000000);
-    } else if ( (vcoFreq >= 1495000000 && vcoFreq <= 1505000000) ) {
+    } else if ((vcoFreq >= 1495000000 && vcoFreq <= 1505000000)) {
         /* vcoFreq:1499988000~1500000000 */
         return (1500000000);
-    } else if ( (vcoFreq >= 1395000000 && vcoFreq <= 1405000000) ) {
+    } else if ((vcoFreq >= 1395000000 && vcoFreq <= 1405000000)) {
         /* vcoFreq:1399988000~1400000000 */
         return (1400000000);
-    } else if ( (vcoFreq >= 1064000000 && vcoFreq <= 1068000000) ) {
+    } else if ((vcoFreq >= 1064000000 && vcoFreq <= 1068000000)) {
         /* vcoFreq:1065992000~1066000000 */
         return (1066000000);
-    } else if ( (vcoFreq >= 799000000 && vcoFreq <= 801000000) ) {
+    } else if ((vcoFreq >= 799000000 && vcoFreq <= 801000000)) {
         /* vcoFreq:799992000~800000000 */
         return (800000000);
-    } else if ( (vcoFreq >= 666000000 && vcoFreq <= 668000000) ) {
+    } else if ((vcoFreq >= 666000000 && vcoFreq <= 668000000)) {
         /* vcoFreq:666992000~667000000 */
         return (667000000);
-    } else if ( (vcoFreq >= 399000000 && vcoFreq <= 401000000) ) {
+    } else if ((vcoFreq >= 399000000 && vcoFreq <= 401000000)) {
         /* vcoFreq:399990000~400000000 */
         return (400000000);
     } else {
@@ -426,22 +420,22 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_UHS_PLL_Output()
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Get_WIFI_PLL_Output(uint32_t pllOut)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Get_WIFI_PLL_Output(uint32_t pllOut)
 {
     return Clock_Get_WIFI_PLL_Output(pllOut);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_WIFI_PLL_Output(uint32_t pllOut)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_WIFI_PLL_Output(uint32_t pllOut)
 {
     return Clock_Get_WIFI_PLL_Output(pllOut);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_CPU_PLL_Output(uint32_t pllOut)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_EMI_Get_CPU_PLL_Output(uint32_t pllOut)
 {
     return Clock_Get_CPU_PLL_Output(pllOut);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
 {
     uint8_t xtalType = 0;
 
@@ -469,7 +463,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Xtal_Output(void)
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* rc32m */
@@ -482,7 +476,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_XClk_Mux_Output(uint8_t sel)
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
 {
     uint32_t tmpVal;
     uint32_t div = 0;
@@ -501,7 +495,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_F32k_Mux_Output(uint8_t sel)
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -510,7 +504,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_F32k_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, HBN_F32K_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm wifi pll 320m */
@@ -523,7 +517,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_320M_Clk_Mux_Output(uint
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -532,7 +526,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_320M_Sel_Val(v
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_320M_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm wifi pll 240m */
@@ -545,7 +539,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_240M_Clk_Mux_Output(uint
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -554,7 +548,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_240M_Sel_Val(v
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_240M_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm wifi pll 160m */
@@ -567,7 +561,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_160M_Clk_Mux_Output(uint
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -576,7 +570,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_DSP_Get_Muxpll_160M_Sel_Val(v
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_MM_MUXPLL_160M_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* wifi pll 160m */
@@ -595,7 +589,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_160M_Clk_Mux_Output(uint8_t
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -604,7 +598,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_160M_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_160M_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* wifi pll 80m */
@@ -623,7 +617,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_80M_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -632,7 +626,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Muxpll_80M_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_TOP_MUXPLL_80M_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* cpu pll 400m */
@@ -651,7 +645,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -661,7 +655,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_XClk_Sel_Val(void)
     return (tmpVal & 0x1);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -671,7 +665,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_Root_Clk_Sel_Val(void
     return ((tmpVal >> 1) & 0x1);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint8_t sel)
 {
     uint32_t tmpVal;
 
@@ -688,7 +682,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MCU_Root_Clk_Mux_Output(uint
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -697,7 +691,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MCU_HClk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_HCLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -706,7 +700,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Peri_BClk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_BCLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -715,7 +709,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_LP_Clk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, PDS_REG_PICO_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* rc32m */
@@ -728,7 +722,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_XClk_Mux_Output(uint8_t
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -737,7 +731,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_XClk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_XCLK_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -746,7 +740,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_Root_Clk_Sel_Val(void
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_ROOT_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm mux 240m */
@@ -762,7 +756,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint8_t sel)
 {
     uint32_t tmpVal;
 
@@ -779,7 +773,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_Root_Clk_Mux_Output(uint
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -788,7 +782,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_HClk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CPU_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -797,7 +791,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_BClk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK2X_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -806,7 +800,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_MM_Bclk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void)
+static inline uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -815,7 +809,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MM_BClk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_BCLK1X_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_MM_BCLK_Mux_Output(uint8_t sel)
+static inline uint32_t ATTR_CLOCK_SECTION Clock_DSP_MM_BCLK_Mux_Output(uint8_t sel)
 {
     if (sel == 0 || sel == 1) {
         /* mm xclk */
@@ -912,7 +906,7 @@ uint32_t ATTR_CLOCK_SECTION Clock_System_Clock_Get(BL_System_Clock_Type type)
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_EMI_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mcu pbclk */
@@ -934,7 +928,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_EMI_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Div_Val(void)
+static inline uint8_t Clock_Get_EMI_Clk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -943,7 +937,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_EMI_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -952,7 +946,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_EMI_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk(void)
+static inline uint32_t Clock_Get_EMI_Clk(void)
 {
     uint32_t div = 0;
 
@@ -961,7 +955,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_EMI_Clk(void)
     return Clock_EMI_Clk_Mux_Output(Clock_Get_EMI_Clk_Sel_Val()) / (div + 1);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PARAMB_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_PARAMB_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* emi cpu pll 400m */
@@ -977,7 +971,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PARAMB_Clk_Mux_Output(uint8_
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Div_Val(void)
+static inline uint8_t Clock_Get_PSRAMB_Clk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -986,7 +980,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_PSRAMB_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -995,7 +989,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_PSRAMB_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk(void)
+static inline uint32_t Clock_Get_PSRAMB_Clk(void)
 {
     uint32_t div = 0;
 
@@ -1004,7 +998,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_PSRAMB_Clk(void)
     return Clock_PARAMB_Clk_Mux_Output(Clock_Get_PSRAMB_Clk_Sel_Val()) / (div + 1);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP2_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm mux 160m */
@@ -1017,40 +1011,41 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP2_Clk_Mux_Output(uint8_t
         return Clock_Get_CPU_PLL_Output(400 * 1000 * 1000);
     } else if (sel == 3) {
         /* mm xclk */
-        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);;
+        return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_DSP_XCLK);
+        ;
     } else {
         return 0;
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP2_Clk_Div_Val(void)
+static inline uint8_t Clock_Get_Clk_Div_Val(void)
 {
     uint32_t tmpVal;
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
 
-    return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_DIV);
+    return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP2_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
 
-    return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_SEL);
+    return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_DSP2_Clk(void)
+static inline uint32_t Clock_Get_Clk(void)
 {
     uint32_t div = 0;
 
-    div = Clock_Get_DSP2_Clk_Div_Val();
+    div = Clock_Get_Clk_Div_Val();
 
-    return Clock_DSP2_Clk_Mux_Output(Clock_Get_DSP2_Clk_Sel_Val()) / (div + 1);
+    return Clock_Clk_Mux_Output(Clock_Get_Clk_Sel_Val()) / (div + 1);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_H264_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_H264_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm mux 160m */
@@ -1066,7 +1061,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_H264_Clk_Mux_Output(uint8_t
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Div_Val(void)
+static inline uint8_t Clock_Get_H264_Clk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1075,7 +1070,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_H264_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1084,7 +1079,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_H264_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk(void)
+static inline uint32_t Clock_Get_H264_Clk(void)
 {
     uint32_t div = 0;
 
@@ -1093,7 +1088,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_H264_Clk(void)
     return Clock_H264_Clk_Mux_Output(Clock_Get_H264_Clk_Sel_Val()) / (div + 1);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_BLAI_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_BLAI_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm mux 160m */
@@ -1109,7 +1104,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_BLAI_Clk_Mux_Output(uint8_t
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Div_Val(void)
+static inline uint8_t Clock_Get_BLAI_Clk_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1118,7 +1113,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_BLAI_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1127,7 +1122,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CNN_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk(void)
+static inline uint32_t Clock_Get_BLAI_Clk(void)
 {
     uint32_t div = 0;
 
@@ -1136,7 +1131,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_BLAI_Clk(void)
     return Clock_BLAI_Clk_Mux_Output(Clock_Get_BLAI_Clk_Sel_Val()) / (div + 1);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MIPI_Div_Val(void)
+static inline uint8_t Clock_Get_MIPI_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1145,12 +1140,12 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_MIPI_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_MIPI_Clk_Mux_Output(void)
+static inline uint32_t Clock_MIPI_Clk_Mux_Output(void)
 {
     return Clock_Get_MIPI_PLL_Output();
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Display_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_Display_Clk_Mux_Output(uint8_t sel)
 {
     uint32_t div = 0;
 
@@ -1166,25 +1161,25 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Display_Clk_Mux_Output(uint8
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Div_Val(void)
+static inline uint8_t Clock_Get_Display_Clk_Div_Val(void)
 {
     uint32_t tmpVal;
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
 
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_Display_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
 
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk(void)
+static inline uint32_t Clock_Get_Display_Clk(void)
 {
     uint32_t div = 0;
 
@@ -1193,7 +1188,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Get_Display_Clk(void)
     return Clock_Display_Clk_Mux_Output(Clock_Get_Display_Clk_Sel_Val()) / (div + 1);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_UART_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mcu pbclk */
@@ -1207,7 +1202,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_UART_Clk_Mux_Output(uint8_t
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_UART_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1216,7 +1211,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Clk_Sel_Val(void)
     return ((BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL2) << 1) | BL_GET_REG_BITS_VAL(tmpVal, GLB_HBN_UART_CLK_SEL));
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void)
+static inline uint8_t Clock_Get_UART_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1225,7 +1220,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_UART_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_UART_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_UART_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_DSP_UART_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm pbclk */
@@ -1241,7 +1236,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_UART_Clk_Mux_Output(uint
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_DSP_UART_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1250,7 +1245,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART_Clk_Sel_Val(void
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART0_Div_Val(void)
+static inline uint8_t Clock_Get_DSP_UART0_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1259,7 +1254,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART0_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART0_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART1_Div_Val(void)
+static inline uint8_t Clock_Get_DSP_UART1_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1268,7 +1263,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_UART1_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_UART1_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PKA_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_PKA_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mcu pbclk */
@@ -1281,7 +1276,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PKA_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PKA_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_PKA_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1290,13 +1285,13 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PKA_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_PKA_CLK_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_IR_Clk_Mux_Output(void)
+static inline uint32_t Clock_IR_Clk_Mux_Output(void)
 {
     /* xclk */
     return Clock_System_Clock_Get(BL_SYSTEM_CLOCK_MCU_XCLK);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void)
+static inline uint8_t Clock_Get_IR_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1305,7 +1300,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_IR_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_IR_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void)
+static inline uint8_t Clock_Get_SF_Clk_Sel2_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1314,7 +1309,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel2_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL2);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_SF_SEL2_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* wifi pll 120m */
@@ -1331,7 +1326,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL2_Clk_Mux_Output(uint8
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_SF_SEL_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* sf sel2 */
@@ -1348,7 +1343,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SF_SEL_Clk_Mux_Output(uint8_
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_SF_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1357,7 +1352,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void)
+static inline uint8_t Clock_Get_SF_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1366,7 +1361,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SF_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_SF_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_SPI_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mux 160Mkz */
@@ -1377,7 +1372,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SPI_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_SPI_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1386,7 +1381,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void)
+static inline uint8_t Clock_Get_SPI_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1395,7 +1390,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SPI_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_SPI_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_SPI_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_DSP_SPI_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm mux 160m */
@@ -1408,7 +1403,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_SPI_Clk_Mux_Output(uint8
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_DSP_SPI_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1417,7 +1412,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Div_Val(void)
+static inline uint8_t Clock_Get_DSP_SPI_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1426,7 +1421,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_SPI_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_SPI_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_I2C_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mcu pbclk */
@@ -1439,7 +1434,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_I2C_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_I2C_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1448,7 +1443,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void)
+static inline uint8_t Clock_Get_I2C_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1457,7 +1452,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2C_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_I2C_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_I2C_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_DSP_I2C_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* mm pbclk */
@@ -1468,7 +1463,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DSP_I2C_Clk_Mux_Output(uint8
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_DSP_I2C_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1477,7 +1472,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C0_Div_Val(void)
+static inline uint8_t Clock_Get_DSP_I2C0_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1486,7 +1481,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C0_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C0_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C1_Div_Val(void)
+static inline uint8_t Clock_Get_DSP_I2C1_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1495,7 +1490,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DSP_I2C1_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, MM_GLB_REG_I2C1_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel)
+static inline uint32_t Clock_GPADC_Clk_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* audio pll clk */
@@ -1506,7 +1501,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Output(uint8_t sel
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_GPADC_32M_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1515,7 +1510,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_32M_Clk_Sel_Val(voi
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void)
+static inline uint8_t Clock_Get_GPADC_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1524,7 +1519,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_GPADC_32M_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_GPADC_Clk_Mux_Output(uint8_t sel)
 {
     uint32_t div = 0;
 
@@ -1537,13 +1532,13 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPADC_Clk_Mux_Output(uint8_t
     }
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_PDM_Clk_Mux_Output(void)
+static inline uint32_t Clock_PDM_Clk_Mux_Output(void)
 {
     /* audio pll clk */
     return Clock_Get_Audio_PLL_Output();
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PDM_Div_Val(void)
+static inline uint8_t Clock_Get_PDM_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1552,13 +1547,13 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_PDM_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_PDM_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_I2S_Clk_Mux_Output(void)
+static inline uint32_t Clock_I2S_Clk_Mux_Output(void)
 {
     /* audio pll clk */
     return Clock_Get_Audio_PLL_Output();
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2S_Div_Val(void)
+static inline uint8_t Clock_Get_I2S_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1567,13 +1562,13 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_I2S_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_I2S_REF_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_ADC_Clk_Mux_Output(void)
+static inline uint32_t Clock_ADC_Clk_Mux_Output(void)
 {
     /* audio pll clk */
     return Clock_Get_Audio_PLL_Output();
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_ADC_Div_Val(void)
+static inline uint8_t Clock_Get_ADC_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1582,7 +1577,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_ADC_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_ADC_CLK_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_GPADC_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1591,7 +1586,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPADC_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, HBN_GPADC_CS);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_GPDAC_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* wifi pll 32m */
@@ -1605,7 +1600,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_GPDAC_Clk_Mux_Output(uint8_t
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void)
+static inline uint8_t Clock_Get_GPDAC_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1614,7 +1609,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_512K_DIV);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_GPDAC_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1623,13 +1618,13 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_GPDAC_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_DIG_CLK_SRC_SEL);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_DAC_Clk_Mux_Output(void)
+static inline uint32_t Clock_DAC_Clk_Mux_Output(void)
 {
     /* audio pll clk */
     return Clock_Get_Audio_PLL_Output();
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DAC_Div_Val(void)
+static inline uint8_t Clock_Get_DAC_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1638,7 +1633,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_DAC_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_AUDIO_DAC_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SDH_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_SDH_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* wifi pll 96m */
@@ -1649,7 +1644,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_SDH_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_SDH_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1658,7 +1653,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Div_Val(void)
+static inline uint8_t Clock_Get_SDH_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1667,7 +1662,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_SDH_Div_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_SDH_CLK_DIV);
 }
 
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t sel)
+static inline uint32_t Clock_CAM_Clk_Mux_Output(uint8_t sel)
 {
     if (sel == 0) {
         /* xclk */
@@ -1683,7 +1678,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_CAM_Clk_Mux_Output(uint8_t s
     }
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void)
+static inline uint8_t Clock_Get_CAM_Clk_Sel_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1692,7 +1687,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Clk_Sel_Val(void)
     return BL_GET_REG_BITS_VAL(tmpVal, GLB_REG_CAM_REF_CLK_SRC_SEL);
 }
 
-__UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void)
+static inline uint8_t Clock_Get_CAM_Div_Val(void)
 {
     uint32_t tmpVal;
 
@@ -1708,7 +1703,7 @@ __UNUSED__ static uint8_t ATTR_CLOCK_SECTION Clock_Get_CAM_Div_Val(void)
  * @return Audio ADC clock value
  *
 *******************************************************************************/
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_ADC_Clock_Get(void)
+static inline uint32_t Clock_Audio_ADC_Clock_Get(void)
 {
     uint32_t clock = 0;
     uint32_t div = 0;
@@ -1726,7 +1721,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_ADC_Clock_Get(void)
  * @return Audio DAC clock value
  *
 *******************************************************************************/
-__UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_DAC_Clock_Get(void)
+static inline uint32_t Clock_Audio_DAC_Clock_Get(void)
 {
     uint32_t clock = 0;
     uint32_t div = 0;
@@ -1746,7 +1741,7 @@ __UNUSED__ static uint32_t ATTR_CLOCK_SECTION Clock_Audio_DAC_Clock_Get(void)
  * @return Peripheral1 clock value
  *
 *******************************************************************************/
-uint32_t ATTR_CLOCK_SECTION Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
+uint32_t Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
 {
     uint32_t clock = 0;
     uint32_t div = 0;
@@ -1889,9 +1884,9 @@ uint32_t ATTR_CLOCK_SECTION Clock_Peripheral_Clock_Get(BL_Peripheral_Type type)
         case BL_PERIPHERAL_CLOCK_H264:
             return Clock_Get_H264_Clk();
 
-        /*!< DSP2 clock */
-        case BL_PERIPHERAL_CLOCK_DSP2:
-            return Clock_Get_DSP2_Clk();
+        /*!< DSP Sub clock */
+        case BL_PERIPHERAL_CLOCK_SUB:
+            return Clock_Get_Clk();
 #endif
         default:
             return 0;
@@ -2202,17 +2197,17 @@ uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_US(void)
 
     if (mtimer_counter < 10) {
         mtimer_counter = CPU_Get_CPU_Cycle();
-        return (uint32_t)mtimer_counter/(clk/1000000);
+        return (uint32_t)mtimer_counter / (clk / 1000000);
     }
 
-    if(clk>1000*1000){
+    if (clk > 1000 * 1000) {
         /* system_clock > 1MHz  ==>  mtimer_clock is 1MHz */
         /* return mtimer_count after mtimer_init_1MHz */
         return CPU_Get_MTimer_Counter();
-    }else{
+    } else {
         /* system_clock < 1MHz  ==>  mtimer_clock is 1KHz */
         /* return mtimer_count*1000 after mtimer_init_1KHz */
-        return CPU_Get_MTimer_Counter()*1000;
+        return CPU_Get_MTimer_Counter() * 1000;
     }
 }
 
@@ -2231,24 +2226,24 @@ uint64_t ATTR_CLOCK_SECTION CPU_Get_MTimer_MS(void)
 
     if (mtimer_counter < 10) {
         mtimer_counter = CPU_Get_CPU_Cycle();
-        return (uint32_t)mtimer_counter/(clk/1000);
+        return (uint32_t)mtimer_counter / (clk / 1000);
     }
 
-    if(clk>1000*1000){
+    if (clk > 1000 * 1000) {
         /* system_clock > 1MHz  ==>  mtimer_clock is 1MHz */
         /* return mtimer_count/1000 after mtimer_init_1MHz */
         mtimer_counter = CPU_Get_MTimer_Counter();
 #ifndef CONFIG_SUPPORT_U32_DIV_ONLY
-        return  mtimer_counter/1000;
+        return mtimer_counter / 1000;
 #else
-        if(mtimer_counter<(1<<30)){
-            return (uint32_t)mtimer_counter/1000;
-        }else{
+        if (mtimer_counter < (1 << 30)) {
+            return (uint32_t)mtimer_counter / 1000;
+        } else {
             //return CPU_Get_MTimer_Counter()/1000;
-            return (mtimer_counter>>10)+(mtimer_counter>>15)-(mtimer_counter>>17)+(mtimer_counter>>21);
+            return (mtimer_counter >> 10) + (mtimer_counter >> 15) - (mtimer_counter >> 17) + (mtimer_counter >> 21);
         }
 #endif
-    }else{
+    } else {
         /* system_clock < 1MHz  ==>  mtimer_clock is 1KHz */
         /* return mtimer_count after mtimer_init_1KHz */
         return CPU_Get_MTimer_Counter();
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_common.c
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_common.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_common.c
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_ef_cfg.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_ef_cfg.c
new file mode 100755
index 0000000000..b4559f9384
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_ef_cfg.c
@@ -0,0 +1,434 @@
+/**
+  ******************************************************************************
+  * @file    bl808_ef_cfg.c
+  * @version V1.0
+  * @date
+  * @brief   This file is the standard driver c file
+  ******************************************************************************
+  * @attention
+  *
+  * 
© COPYRIGHT(c) 2020 Bouffalo Lab

+  *
+  * Redistribution and use in source and binary forms, with or without modification,
+  * are permitted provided that the following conditions are met:
+  *   1. Redistributions of source code must retain the above copyright notice,
+  *      this list of conditions and the following disclaimer.
+  *   2. Redistributions in binary form must reproduce the above copyright notice,
+  *      this list of conditions and the following disclaimer in the documentation
+  *      and/or other materials provided with the distribution.
+  *   3. Neither the name of Bouffalo Lab nor the names of its contributors
+  *      may be used to endorse or promote products derived from this software
+  *      without specific prior written permission.
+  *
+  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+  * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+  * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+  * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+  *
+  ******************************************************************************
+  */
+#include "bl808_ef_cfg.h"
+#include "hardware/ef_data_0_reg.h"
+#include "hardware/ef_data_1_reg.h"
+
+extern int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload);
+
+static const bflb_ef_ctrl_com_trim_cfg_t trim_list[] = {
+    {
+        .name = "rc32m",
+        .en_addr = 0x78 * 8 + 1,
+        .parity_addr = 0x78 * 8 + 0,
+        .value_addr = 0x7C * 8 + 4,
+        .value_len = 8,
+    },
+    {
+        .name = "rc32k",
+        .en_addr = 0xEC * 8 + 19,
+        .parity_addr = 0xEC * 8 + 18,
+        .value_addr = 0xEC * 8 + 8,
+        .value_len = 10,
+    },
+    {
+        .name = "gpadc_gain",
+        .en_addr = 0xF0 * 8 + 27,
+        .parity_addr = 0xF0 * 8 + 26,
+        .value_addr = 0xF0 * 8 + 14,
+        .value_len = 12,
+    },
+    {
+        .name = "tsen",
+        .en_addr = 0xF0 * 8 + 13,
+        .parity_addr = 0xF0 * 8 + 12,
+        .value_addr = 0xF0 * 8 + 0,
+        .value_len = 12,
+    },
+    {
+        .name = "usb20",
+        .en_addr = 0xF8 * 8 + 15,
+        .parity_addr = 0xF8 * 8 + 14,
+        .value_addr = 0xF8 * 8 + 8,
+        .value_len = 6,
+    },
+    {
+        .name = "dcdc11_trim",
+        .en_addr = 0x78 * 8 + 31,
+        .parity_addr = 0x78 * 8 + 30,
+        .value_addr = 0x78 * 8 + 26,
+        .value_len = 4,
+    },
+    {
+        .name = "dcdc18_trim",
+        .en_addr = 0x78 * 8 + 25,
+        .parity_addr = 0x78 * 8 + 24,
+        .value_addr = 0x78 * 8 + 20,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo28cis_trim",
+        .en_addr = 0x78 * 8 + 13,
+        .parity_addr = 0x78 * 8 + 12,
+        .value_addr = 0x78 * 8 + 8,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo15cis_trim",
+        .en_addr = 0x78 * 8 + 13,
+        .parity_addr = 0x78 * 8 + 12,
+        .value_addr = 0x78 * 8 + 8,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo18flash_trim",
+        .en_addr = 0xEC * 8 + 31,
+        .parity_addr = 0xEC * 8 + 30,
+        .value_addr = 0xEC * 8 + 26,
+        .value_len = 4,
+    },
+    {
+        .name = "ldo12uhs_trim",
+        .en_addr = 0xEC * 8 + 25,
+        .parity_addr = 0xEC * 8 + 24,
+        .value_addr = 0xEC * 8 + 20,
+        .value_len = 4,
+    },
+};
+
+/****************************************************************************/ /**
+ * @brief  Efuse get trim list
+ *
+ * @param  trim_list: Trim list pointer
+ *
+ * @return Trim list count
+ *
+*******************************************************************************/
+uint32_t bflb_ef_ctrl_get_common_trim_list(const bflb_ef_ctrl_com_trim_cfg_t **ptrim_list)
+{
+    *ptrim_list = &trim_list[0];
+    return sizeof(trim_list) / sizeof(trim_list[0]);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read device info
+ *
+ * @param  deviceInfo: info pointer
+ *
+ * @return None
+ *
+*******************************************************************************/
+void bflb_ef_ctrl_get_device_info(bflb_efuse_device_info_type *deviceInfo)
+{
+    uint32_t tmpval;
+
+    //tmpVal = BL_RD_REG(EF_DATA_BASE, EF_DATA_0_EF_WIFI_MAC_HIGH);
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, 1);
+
+    deviceInfo->chipInfo = (tmpval >> 29) & 0x7;
+    deviceInfo->memoryInfo = (tmpval >> 27) & 0x3;
+    deviceInfo->psramInfo = (tmpval >> 25) & 0x3;
+    deviceInfo->deviceInfo = (tmpval >> 22) & 0x7;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+
+    deviceInfo->psramInfo |= ((tmpval >> 20) & 0x1) << 2;
+}
+
+void bflb_efuse_get_chipid(uint8_t chipid[8])
+{
+    bflb_efuse_read_mac_address_opt(0, chipid, 1);
+    chipid[6] = 0;
+    chipid[7] = 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Whether MAC address slot is empty
+ *
+ * @param  slot: MAC address slot
+ * @param  reload: whether  reload to check
+ *
+ * @return 0 for all slots full,1 for others
+ *
+*******************************************************************************/
+uint8_t bflb_efuse_is_mac_address_slot_empty(uint8_t slot, uint8_t reload)
+{
+    uint32_t tmp1 = 0xffffffff, tmp2 = 0xffffffff;
+    uint32_t part1Empty = 0, part2Empty = 0;
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmp2, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmp1, 1, reload);
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmp2, 1, reload);
+    }
+
+    part1Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp1, 0, 32));
+    part2Empty = (bflb_ef_ctrl_is_all_bits_zero(tmp2, 0, 22));
+
+    return (part1Empty && part2Empty);
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse write optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  program: Whether program
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_write_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t program)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval;
+    uint32_t i = 0, cnt;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    /* Change to local order */
+    for (i = 0; i < 3; i++) {
+        tmpval = mac[i];
+        mac[i] = mac[5 - i];
+        mac[5 - i] = tmpval;
+    }
+
+    /* The low 32 bits */
+    tmpval = BL_RDWD_FRM_BYTEP(maclow);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, program);
+    }
+
+    /* The high 16 bits */
+    tmpval = machigh[0] + (machigh[1] << 8);
+    cnt = 0;
+
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    tmpval |= ((cnt & 0x3f) << 16);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, program);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmpval, 1, program);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, program);
+    }
+
+    return 0;
+}
+
+/****************************************************************************/ /**
+ * @brief  Efuse read optional MAC address
+ *
+ * @param  slot: MAC address slot
+ * @param  mac[6]: MAC address buffer
+ * @param  reload: Whether reload
+ *
+ * @return 0 or -1
+ *
+*******************************************************************************/
+int bflb_efuse_read_mac_address_opt(uint8_t slot, uint8_t mac[6], uint8_t reload)
+{
+    uint8_t *maclow = (uint8_t *)mac;
+    uint8_t *machigh = (uint8_t *)(mac + 4);
+    uint32_t tmpval = 0;
+    uint32_t i = 0;
+    uint32_t cnt = 0;
+
+    if (slot >= 3) {
+        return -1;
+    }
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_LOW_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_2_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W1_OFFSET, &tmpval, 1, reload);
+    }
+
+    BL_WRWD_TO_BYTEP(maclow, tmpval);
+
+    if (slot == 0) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_WIFI_MAC_HIGH_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 1) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_3_OFFSET, &tmpval, 1, reload);
+    } else if (slot == 2) {
+        bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_KEY_SLOT_11_W2_OFFSET, &tmpval, 1, reload);
+    }
+
+    machigh[0] = tmpval & 0xff;
+    machigh[1] = (tmpval >> 8) & 0xff;
+
+    /* Check parity */
+    for (i = 0; i < 6; i++) {
+        cnt += bflb_ef_ctrl_get_byte_zero_cnt(mac[i]);
+    }
+
+    if ((cnt & 0x3f) == ((tmpval >> 16) & 0x3f)) {
+        /* Change to network order */
+        for (i = 0; i < 3; i++) {
+            tmpval = mac[i];
+            mac[i] = mac[5 - i];
+            mac[5 - i] = tmpval;
+        }
+        return 0;
+    } else {
+        return -1;
+    }
+}
+
+float bflb_efuse_get_adc_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+    uint32_t tmp;
+
+    float coe = 1.0;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "gpadc_gain", &trim, 1);
+
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            tmp = trim.value;
+
+            if (tmp & 0x800) {
+                tmp = ~tmp;
+                tmp += 1;
+                tmp = tmp & 0xfff;
+                coe = (1.0 + ((float)tmp / 2048.0));
+            } else {
+                coe = (1.0 - ((float)tmp / 2048.0));
+            }
+        }
+    }
+
+    return coe;
+}
+
+uint32_t bflb_efuse_get_adc_tsen_trim(void)
+{
+    bflb_ef_ctrl_com_trim_t trim;
+
+    bflb_ef_ctrl_read_common_trim(NULL, "tsen", &trim, 1);
+    if (trim.en) {
+        if (trim.parity == bflb_ef_ctrl_get_trim_parity(trim.value, trim.len)) {
+            return trim.value;
+        }
+    }
+
+    return 2042;
+}
+
+void bflb_efuse_read_secure_boot(uint8_t *sign, uint8_t *aes)
+{
+    uint32_t tmpval = 0;
+
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_CFG_0_OFFSET, &tmpval, 1, 1);
+    *sign = ((tmpval & EF_DATA_0_EF_SBOOT_SIGN_MODE_MSK) >> EF_DATA_0_EF_SBOOT_SIGN_MODE_POS) & 0x01;
+    *aes = ((tmpval & EF_DATA_0_EF_SF_AES_MODE_MSK) >> EF_DATA_0_EF_SF_AES_MODE_POS);
+}
+
+void bflb_efuse_write_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 5 : index);
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_write_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_write_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
+    }
+}
+
+void bflb_efuse_read_aes_key(uint8_t index, uint8_t *data, uint32_t len)
+{
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 5 : index);
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_read_direct(NULL, 0x1C + index * 4, (uint32_t *)data, len, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        /* Every key is 4 words len*/
+        bflb_ef_ctrl_read_direct(NULL, 0x80 + index * 4, (uint32_t *)data, len, 1);
+    }
+}
+
+void bflb_efuse_lock_aes_key_write(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 8 : index);
+        lock |= (1 << (index + 17));
+        bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)&lock, 1, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        lock |= (1 << (index + 15));
+        bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)&lock, 1, 1);
+    }
+}
+
+void bflb_efuse_lock_aes_key_read(uint8_t index)
+{
+    uint32_t lock = 0;
+
+    if ((index <= 3) || (index == 11)) {
+        index = ((index == 11) ? 4 : index);
+        lock |= (1 << (index + 27));
+        bflb_ef_ctrl_write_direct(NULL, 0x7c, (uint32_t *)lock, 1, 1);
+    } else if ((index < 11) && (index > 3)) {
+        index = index - 4;
+        lock |= (1 << (index + 25));
+        bflb_ef_ctrl_write_direct(NULL, 0xfc, (uint32_t *)lock, 1, 1);
+    }
+}
+
+void bflb_efuse_write_sw_usage(uint32_t index, uint32_t usage, uint8_t program)
+{
+    bflb_ef_ctrl_write_direct(NULL, EF_DATA_0_EF_SW_USAGE_0_OFFSET + index * 4, &usage, 1, program);
+}
+
+void bflb_efuse_read_sw_usage(uint32_t index, uint32_t *usage)
+{
+    bflb_ef_ctrl_read_direct(NULL, EF_DATA_0_EF_SW_USAGE_0_OFFSET + index * 4, (uint32_t *)usage, 1, 1);
+}
\ No newline at end of file
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb.c
old mode 100644
new mode 100755
similarity index 89%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb.c
index f93045554b..239ba7d115
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb.c
@@ -81,8 +81,6 @@ static BL_Err_Type GLB_Get_And_Clr_First_Set_From_U64(uint64_t *val, uint32_t *b
  *  @{
  */
 
-
-
 /* WiFi PLL Config*/
 const GLB_WAC_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION wifiPllBasicCfg_32M_38P4M_40M = {
     .clkpllRefdivRatio = 2,  /*!< pll_refdiv_ratio */
@@ -238,6 +236,15 @@ const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_400M[GLB_XTAL_MAX]
     { &cpuPllBasicCfg_24M_26M, 0xF627 },        /*!< XTAL is 26M */
     { &cpuPllBasicCfg_32M_38P4M_40M, 0x19000 }, /*!< XTAL is RC32M */
 };
+const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_440M[GLB_XTAL_MAX] = {
+    { NULL, 0x0 },                              /*!< XTAL is None */
+    { &cpuPllBasicCfg_24M_26M, 0x12555 },       /*!< XTAL is 24M */
+    { &cpuPllBasicCfg_32M_38P4M_40M, 0x1B800 }, /*!< XTAL is 32M */
+    { &cpuPllBasicCfg_32M_38P4M_40M, 0x16EAA }, /*!< XTAL is 38.4M */
+    { &cpuPllBasicCfg_32M_38P4M_40M, 0x16000 }, /*!< XTAL is 40M */
+    { &cpuPllBasicCfg_24M_26M, 0x10EC4 },       /*!< XTAL is 26M */
+    { &cpuPllBasicCfg_32M_38P4M_40M, 0x1B800 }, /*!< XTAL is RC32M */
+};
 const GLB_WAC_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION cpuPllCfg_480M[GLB_XTAL_MAX] = {
     { NULL, 0x0 },                              /*!< XTAL is None */
     { &cpuPllBasicCfg_24M_26M, 0x14000 },       /*!< XTAL is 24M */
@@ -296,42 +303,42 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION mipiPllCfg_1500M[GLB_XTAL_MAX
 
 /* uhs PLL 2100 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_24M = {
-    .clkpllRefdivRatio = 1,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 1,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_32M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_38P4M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_40M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2100BasicCfg_26M = {
-    .clkpllRefdivRatio = 1,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2100/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 1,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2100 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX] = {
-    { NULL, 0x0 },                      /*!< XTAL is None */
+    { NULL, 0x0 },                          /*!< XTAL is None */
     { &uhsPll2100BasicCfg_24M, 0x2BC00 },   /*!< XTAL is 24M */
     { &uhsPll2100BasicCfg_32M, 0x41A00 },   /*!< XTAL is 32M */
     { &uhsPll2100BasicCfg_38P4M, 0x36B00 }, /*!< XTAL is 38.4M */
@@ -342,39 +349,39 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2100M[GLB_XTAL_MAX]
 
 /* uhs PLL 1400 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_24M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 4,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 4,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_32M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 4,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 4,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_38P4M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 4,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 4,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_40M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 4,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 4,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1400MCfg_26M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 4,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 4,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX] = {
     { NULL, 0x0 },                      /*!< XTAL is None */
@@ -388,39 +395,39 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1400M[GLB_XTAL_MAX]
 
 /* uhs PLL 1500 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_24M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_32M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_38P4M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_40M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1500MCfg_26M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1500/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1500 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX] = {
     { NULL, 0x0 },                      /*!< XTAL is None */
@@ -434,42 +441,42 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1500M[GLB_XTAL_MAX]
 
 /* uhs PLL 1600 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_24M = {
-    .clkpllRefdivRatio = 1,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 1,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_32M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_38P4M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_40M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1600BasicCfg_26M = {
-    .clkpllRefdivRatio = 1,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 5,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1600/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 1,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 5,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1600 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX] = {
-    { NULL, 0x0 },                      /*!< XTAL is None */
+    { NULL, 0x0 },                          /*!< XTAL is None */
     { &uhsPll1600BasicCfg_24M, 0x21555 },   /*!< XTAL is 24M */
     { &uhsPll1600BasicCfg_32M, 0x32000 },   /*!< XTAL is 32M */
     { &uhsPll1600BasicCfg_38P4M, 0x29AAA }, /*!< XTAL is 38.4M */
@@ -480,180 +487,180 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1600M[GLB_XTAL_MAX]
 
 /* uhs PLL 400 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_24M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_32M = {
-    .clkpllRefdivRatio = 4,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 4,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_38P4M = {
-    .clkpllRefdivRatio = 4,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 4,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_40M = {
-    .clkpllRefdivRatio = 4,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 4,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll400BasicCfg_26M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 400/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 400 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_400M[GLB_XTAL_MAX] = {
-    { NULL, 0x0 },                      /*!< XTAL is None */
-    { &uhsPll400BasicCfg_24M, 0x19000 },    /*!< XTAL is 24M */
-    { &uhsPll400BasicCfg_32M, 0x19000 },    /*!< XTAL is 32M */
-    { &uhsPll400BasicCfg_38P4M, 0x14D55 },  /*!< XTAL is 38.4M */
-    { &uhsPll400BasicCfg_40M, 0x14000 },    /*!< XTAL is 40M */
-    { &uhsPll400BasicCfg_26M, 0x1713B },    /*!< XTAL is 26M */
-    { &uhsPll400BasicCfg_32M, 0x19000 },    /*!< XTAL is RC32M */
+    { NULL, 0x0 },                         /*!< XTAL is None */
+    { &uhsPll400BasicCfg_24M, 0x19000 },   /*!< XTAL is 24M */
+    { &uhsPll400BasicCfg_32M, 0x19000 },   /*!< XTAL is 32M */
+    { &uhsPll400BasicCfg_38P4M, 0x14D55 }, /*!< XTAL is 38.4M */
+    { &uhsPll400BasicCfg_40M, 0x14000 },   /*!< XTAL is 40M */
+    { &uhsPll400BasicCfg_26M, 0x1713B },   /*!< XTAL is 26M */
+    { &uhsPll400BasicCfg_32M, 0x19000 },   /*!< XTAL is RC32M */
 };
 
 /* uhs PLL 667 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_24M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_32M = {
-    .clkpllRefdivRatio = 4,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 4,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_38P4M = {
-    .clkpllRefdivRatio = 4,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 4,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_40M = {
-    .clkpllRefdivRatio = 4,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 4,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll667BasicCfg_26M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 1,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 667/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 1,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 667 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_667M[GLB_XTAL_MAX] = {
-    { NULL, 0x0 },                      /*!< XTAL is None */
-    { &uhsPll667BasicCfg_24M, 0x29B00 },    /*!< XTAL is 24M */
-    { &uhsPll667BasicCfg_32M, 0x29B00 },    /*!< XTAL is 32M */
-    { &uhsPll667BasicCfg_38P4M, 0x22BD5 },  /*!< XTAL is 38.4M */
-    { &uhsPll667BasicCfg_40M, 0x21599 },    /*!< XTAL is 40M */
-    { &uhsPll667BasicCfg_26M, 0x267B1 },    /*!< XTAL is 26M */
-    { &uhsPll667BasicCfg_32M, 0x29B00 },    /*!< XTAL is RC32M */
+    { NULL, 0x0 },                         /*!< XTAL is None */
+    { &uhsPll667BasicCfg_24M, 0x29B00 },   /*!< XTAL is 24M */
+    { &uhsPll667BasicCfg_32M, 0x29B00 },   /*!< XTAL is 32M */
+    { &uhsPll667BasicCfg_38P4M, 0x22BD5 }, /*!< XTAL is 38.4M */
+    { &uhsPll667BasicCfg_40M, 0x21599 },   /*!< XTAL is 40M */
+    { &uhsPll667BasicCfg_26M, 0x267B1 },   /*!< XTAL is 26M */
+    { &uhsPll667BasicCfg_32M, 0x29B00 },   /*!< XTAL is RC32M */
 };
 
 /* uhs PLL 800 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_24M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 2,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_32M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 2,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_38P4M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 2,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_40M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 2,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll800BasicCfg_26M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 2,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 800/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,         /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,        /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 2,            /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 800 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_800M[GLB_XTAL_MAX] = {
-    { NULL, 0x0 },                      /*!< XTAL is None */
-    { &uhsPll800BasicCfg_24M, 0x21555 },    /*!< XTAL is 24M */
-    { &uhsPll800BasicCfg_32M, 0x25800 },    /*!< XTAL is 32M */
-    { &uhsPll800BasicCfg_38P4M, 0x1F400 },  /*!< XTAL is 38.4M */
-    { &uhsPll800BasicCfg_40M, 0x1E000 },    /*!< XTAL is 40M */
-    { &uhsPll800BasicCfg_26M, 0x1EC4E },    /*!< XTAL is 26M */
-    { &uhsPll800BasicCfg_32M, 0x25800 },    /*!< XTAL is RC32M */
+    { NULL, 0x0 },                         /*!< XTAL is None */
+    { &uhsPll800BasicCfg_24M, 0x21555 },   /*!< XTAL is 24M */
+    { &uhsPll800BasicCfg_32M, 0x25800 },   /*!< XTAL is 32M */
+    { &uhsPll800BasicCfg_38P4M, 0x1F400 }, /*!< XTAL is 38.4M */
+    { &uhsPll800BasicCfg_40M, 0x1E000 },   /*!< XTAL is 40M */
+    { &uhsPll800BasicCfg_26M, 0x1EC4E },   /*!< XTAL is 26M */
+    { &uhsPll800BasicCfg_32M, 0x25800 },   /*!< XTAL is RC32M */
 };
 
 /* uhs PLL 1066 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_24M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 3,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_32M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 3,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_38P4M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 3,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_40M = {
-    .clkpllRefdivRatio = 3,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 3,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 3,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll1066BasicCfg_26M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 3,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 1066/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 3,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 1066 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX] = {
-    { NULL, 0x0 },                      /*!< XTAL is None */
+    { NULL, 0x0 },                          /*!< XTAL is None */
     { &uhsPll1066BasicCfg_24M, 0x2C6AA },   /*!< XTAL is 24M */
     { &uhsPll1066BasicCfg_32M, 0x31F80 },   /*!< XTAL is 32M */
     { &uhsPll1066BasicCfg_38P4M, 0x29A40 }, /*!< XTAL is 38.4M */
@@ -664,42 +671,42 @@ const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_1066M[GLB_XTAL_MAX]
 
 /* uhs PLL 2000 Config*/
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_24M = {
-    .clkpllRefdivRatio = 1,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 1,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_32M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_38P4M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_40M = {
-    .clkpllRefdivRatio = 2,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 2,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 2,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 2,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_CFG_BASIC_Type ATTR_CLOCK_CONST_SECTION uhsPll2000BasicCfg_26M = {
-    .clkpllRefdivRatio = 1,     /*!< pll_refdiv_ratio */
-    .clkpllSelSampleClk = 1,    /*!< pll_sel_sample_clk */
-    .clkpllVcoSpeed = 7,        /*!< pll_vco_speed */
-    .clkpllEvenDivEn = 1,       /*!< pll_even_div_en */
-    .clkpllEvenDivRatio = 2000/50, /*!< pll_even_div_ratio */
+    .clkpllRefdivRatio = 1,          /*!< pll_refdiv_ratio */
+    .clkpllSelSampleClk = 1,         /*!< pll_sel_sample_clk */
+    .clkpllVcoSpeed = 7,             /*!< pll_vco_speed */
+    .clkpllEvenDivEn = 1,            /*!< pll_even_div_en */
+    .clkpllEvenDivRatio = 2000 / 50, /*!< pll_even_div_ratio */
 };
 const GLB_MU_PLL_Cfg_Type ATTR_CLOCK_CONST_SECTION uhsPllCfg_2000M[GLB_XTAL_MAX] = {
-    { NULL, 0x0 },                      /*!< XTAL is None */
+    { NULL, 0x0 },                          /*!< XTAL is None */
     { &uhsPll2000BasicCfg_24M, 0x29AAA },   /*!< XTAL is 24M */
     { &uhsPll2000BasicCfg_32M, 0x3E800 },   /*!< XTAL is 32M */
     { &uhsPll2000BasicCfg_38P4M, 0x34155 }, /*!< XTAL is 38.4M */
@@ -1255,7 +1262,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Power_On_WAC_PLL(GLB_WAC_PLL_Type pllType, co
     /* aupll : cfg1, aupll_postdiv = 0x12 or 0x14 */
     if (GLB_WAC_PLL_AUPLL == pllType) {
         tmpVal = BL_RD_WORD(REG_PLL_BASE_ADDRESS + 4 * 1);
-        if ((cfg->clkpllSdmin==0x12D0E)||(cfg->clkpllSdmin==0x1C395)||(cfg->clkpllSdmin==0x17851)||(cfg->clkpllSdmin==0x16944)||(cfg->clkpllSdmin==0x115E5)) {
+        if ((cfg->clkpllSdmin == 0x12D0E) || (cfg->clkpllSdmin == 0x1C395) || (cfg->clkpllSdmin == 0x17851) || (cfg->clkpllSdmin == 0x16944) || (cfg->clkpllSdmin == 0x115E5)) {
             /* 451.548 */
             tmpVal = BL_SET_REG_BITS_VAL(tmpVal, CCI_AUPLL_POSTDIV, 0x14);
         } else {
@@ -1568,9 +1575,9 @@ BL_Err_Type GLB_Set_Display_CLK(uint8_t enable, GLB_DISP_CLK_Type srcClk, uint8_
     }
 
     tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG1);
-    if(enable){
+    if (enable) {
         tmpVal = BL_SET_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);
-    }else{
+    } else {
         tmpVal = BL_CLR_REG_BIT(tmpVal, GLB_MIPIPLL_EVEN_DIV_EN);
     }
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_EVEN_DIV_RATIO, evenNum);
@@ -1613,23 +1620,23 @@ BL_Err_Type GLB_Set_EMAC_CLK(uint8_t enable)
 *******************************************************************************/
 BL_Err_Type GLB_Output_EMAC_CLK(uint8_t gpio)
 {
-    uint32_t regAddr=GLB_BASE+GLB_GPIO_CFG0_OFFSET+(gpio<<2);
-    uint32_t regVal=0x00040F03;
+    uint32_t regAddr = GLB_BASE + GLB_GPIO_CFG0_OFFSET + (gpio << 2);
+    uint32_t regVal = 0x00040F03;
 
-    if( ( gpio != GLB_GPIO_PIN_6 ) && \
-        ( gpio != GLB_GPIO_PIN_14 ) && \
-        ( gpio != GLB_GPIO_PIN_12 ) && \
-        ( gpio != GLB_GPIO_PIN_30 ) ){
+    if ((gpio != GLB_GPIO_PIN_6) &&
+        (gpio != GLB_GPIO_PIN_14) &&
+        (gpio != GLB_GPIO_PIN_12) &&
+        (gpio != GLB_GPIO_PIN_30)) {
         return ERROR;
     }
     /* set gpio in debug function */
-    BL_WR_WORD(regAddr,regVal);
+    BL_WR_WORD(regAddr, regVal);
 
     /* select signal */
-    BL_WR_WORD(0x200002E0+((gpio-6)/8)*4,0x80000010);
+    BL_WR_WORD(0x200002E0 + ((gpio - 6) / 8) * 4, 0x80000010);
 
     /* output */
-    BL_WR_WORD(0x200002F0,0x01);
+    BL_WR_WORD(0x200002F0, 0x01);
 
     return SUCCESS;
 }
@@ -4172,20 +4179,20 @@ BL_Err_Type GLB_Set_DSP_SPI_0_ACT_MOD_Sel(GLB_SPI_PAD_ACT_AS_Type mod)
  *
  * @param  h2pfSramRel: make pfh_64k0,pfh_64k1,pfh_64k0 writable
  * @param  vramSramRel: make l2_vram writable
- * @param  dspl2SramRel: make dspl2_32k0,dspl2_32k1 writable
+ * @param  subSramRel:  make sub_32k0,sub_32k1 writable
  * @param  blaiSramRel: make blai_64k0,blai_64k1 writable
  *
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t dspl2SramRel, uint8_t blaiSramRel)
+BL_Err_Type GLB_Set_DSP_L2SRAM_Available_Size(uint8_t h2pfSramRel, uint8_t vramSramRel, uint8_t subSramRel, uint8_t blaiSramRel)
 {
     uint32_t tmpVal = 0;
 
     tmpVal = BL_RD_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_H2PF_SRAM_REL, h2pfSramRel);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_VRAM_SRAM_REL, vramSramRel);
-    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_DSPL2_SRAM_REL, dspl2SramRel);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_SUB_SRAM_REL, subSramRel);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_MISC_REG_BLAI_SRAM_REL, blaiSramRel);
     BL_WR_REG(MM_MISC_BASE, MM_MISC_VRAM_CTRL, tmpVal);
 
@@ -4337,7 +4344,7 @@ BL_Err_Type GLB_AHB_DSP_Software_Reset(GLB_AHB_DSP_SW_Type swrst)
         regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_MM_PERI_OFFSET;
     } else if (swrst < 96) {
         bit = swrst - 64;
-        regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_DSP2_SUB_OFFSET;
+        regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_SUB_OFFSET;
     } else if (swrst < 128) {
         bit = swrst - 96;
         regAddr = MM_GLB_BASE + MM_GLB_SW_RESET_CODEC_SUB_OFFSET;
@@ -4789,6 +4796,50 @@ BL_Err_Type GLB_PER_Clock_UnGate(uint64_t ips)
     return SUCCESS;
 }
 
+/****************************************************************************/ /**
+ * @brief  hold PSRAM clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PSRAM_PER_Clock_Gate(void)
+{
+    uint32_t tmpValCfg2 = 0;
+
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    /* GLB_AHB_CLOCK_IP_PSRAM0_CTRL */
+    tmpValCfg2 &= ~(1 << 17);
+    /* GLB_AHB_CLOCK_IP_PSRAM1_CTRL */
+    tmpValCfg2 &= ~(1 << 18);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  release PSRAM clock
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_PSRAM_PER_Clock_UnGate(void)
+{
+    uint32_t tmpValCfg2 = 0;
+
+    tmpValCfg2 = BL_RD_REG(GLB_BASE, GLB_CGEN_CFG2);
+    /* GLB_AHB_CLOCK_IP_PSRAM0_CTRL */
+    tmpValCfg2 |= (1 << 17);
+    /* GLB_AHB_CLOCK_IP_PSRAM1_CTRL */
+    tmpValCfg2 |= (1 << 18);
+    BL_WR_REG(GLB_BASE, GLB_CGEN_CFG2, tmpValCfg2);
+
+    return SUCCESS;
+}
+
 /****************************************************************************/ /**
  * @brief  gate pll clock cgen
  *
@@ -5096,9 +5147,9 @@ BL_Err_Type GLB_Get_Auto_Calc_Xtal_Type(GLB_XTAL_Type *calcXtalType)
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue)
+BL_Err_Type ATTR_TCM_SECTION GLB_Set_Flash_Id_Value(uint32_t idValue)
 {
-    BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue|BFLB_FLASH_ID_VALID_FLAG));
+    BL_WR_REG(GLB_BASE, GLB_HW_RSV1, (idValue | BFLB_FLASH_ID_VALID_FLAG));
 
     return SUCCESS;
 }
@@ -5111,13 +5162,13 @@ BL_Err_Type GLB_Set_Flash_Id_Value(uint32_t idValue)
  * @return flash id
  *
 *******************************************************************************/
-uint32_t GLB_Get_Flash_Id_Value(void)
+uint32_t ATTR_TCM_SECTION GLB_Get_Flash_Id_Value(void)
 {
     uint32_t tmpVal = 0;
 
     tmpVal = BL_RD_REG(GLB_BASE, GLB_HW_RSV1);
-    if ((tmpVal&BFLB_FLASH_ID_VALID_FLAG) != 0) {
-        return (tmpVal&BFLB_FLASH_ID_VALID_MASK);
+    if ((tmpVal & BFLB_FLASH_ID_VALID_FLAG) != 0) {
+        return (tmpVal & BFLB_FLASH_ID_VALID_MASK);
     }
 
     return 0x00000000;
@@ -5395,7 +5446,7 @@ BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8
     CHECK_PARAM(IS_GLB_DSP_DP_CLK_TYPE(clkSel));
     CHECK_PARAM((div <= 0xF));
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_DIV, div);
     tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DP_CLK_SEL, clkSel);
     if (enable) {
@@ -5403,36 +5454,36 @@ BL_Err_Type GLB_Set_DSP_DP_CLK(uint8_t enable, GLB_DSP_DP_CLK_Type clkSel, uint8
     } else {
         tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DP_CLK_DIV_EN);
     }
-    BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal);
+    BL_WR_REG(MM_GLB_BASE, MM_GLB_DP_CLK, tmpVal);
 
     return SUCCESS;
 }
 
 /****************************************************************************/ /**
- * @brief  set dsp2 clock
+ * @brief  set DSP clock
  *
  * @param  enable: ENABLE or DISABLE
- * @param  clkSel: dsp2 clock type
+ * @param  clkSel: DSP clock type
  * @param  div: div
  *
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type GLB_Set_DSP_DSP2_CLK(uint8_t enable, GLB_DSP_DSP2_CLK_Type clkSel, uint8_t div)
+BL_Err_Type GLB_Set_DSP_CLK(uint8_t enable, GLB_DSP_CLK_Type clkSel, uint8_t div)
 {
     uint32_t tmpVal = 0;
 
-    CHECK_PARAM(IS_GLB_DSP_DSP2_CLK_TYPE(clkSel));
+    CHECK_PARAM(IS_GLB_DSP_CLK_TYPE(clkSel));
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK);
-    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_DIV, div);
-    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_DSP2_CLK_SEL, clkSel);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_DP_CLK);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_DIV, div);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, MM_GLB_REG_CLK_SEL, clkSel);
     if (enable) {
-        tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN);
+        tmpVal = BL_SET_REG_BIT(tmpVal, MM_GLB_REG_CLK_DIV_EN);
     } else {
-        tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_DSP2_CLK_DIV_EN);
+        tmpVal = BL_CLR_REG_BIT(tmpVal, MM_GLB_REG_CLK_DIV_EN);
     }
-    BL_WR_REG(MM_GLB_BASE, MM_GLB_DSP2_DP_CLK, tmpVal);
+    BL_WR_REG(MM_GLB_BASE, MM_GLB_DP_CLK, tmpVal);
 
     return SUCCESS;
 }
@@ -5721,30 +5772,30 @@ BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Peripheral_Reset(GLB_DSP_PERIPHERAL_Type pe
 }
 
 /****************************************************************************/ /**
- * @brief  dsp2 sub reset
+ * @brief  sub reset
  *
- * @param  dsp2Part: reset type
+ * @param  subPart: reset type
  *
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_TCM_SECTION GLB_DSP_DSP2_Sub_Reset(GLB_DSP_DSP2_SUB_Type dsp2Part)
+BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Sub_Reset(GLB_DSP_SUB_Type subPart)
 {
     uint32_t tmpVal = 0;
 
-    CHECK_PARAM(IS_GLB_DSP_DSP2_SUB_TYPE(dsp2Part));
+    CHECK_PARAM(IS_GLB_DSP_SUB_TYPE(subPart));
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);
-    tmpVal &= ~(1 << dsp2Part);
-    BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB);
+    tmpVal &= ~(1 << subPart);
+    BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB, tmpVal);
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);
-    tmpVal |= (1 << dsp2Part);
-    BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB);
+    tmpVal |= (1 << subPart);
+    BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB, tmpVal);
 
-    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB);
-    tmpVal &= ~(1 << dsp2Part);
-    BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_DSP2_SUB, tmpVal);
+    tmpVal = BL_RD_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB);
+    tmpVal &= ~(1 << subPart);
+    BL_WR_REG(MM_GLB_BASE, MM_GLB_SW_RESET_SUB, tmpVal);
 
     return SUCCESS;
 }
@@ -5816,7 +5867,7 @@ BL_Err_Type ATTR_TCM_SECTION GLB_DSP_Image_Sensor_Reset(GLB_DSP_IMAGE_SENSOR_Typ
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList)
 {
     GLB_PLL_REF_CLK_Type refClk;
 
@@ -5842,7 +5893,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_WIFI_PLL(GLB_XTAL_Type xtalType, const
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList)
 {
     GLB_PLL_REF_CLK_Type refClk;
 
@@ -5868,7 +5919,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_AUDIO_PLL(GLB_XTAL_Type xtalType, cons
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type * pllCfgList)
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const GLB_WAC_PLL_Cfg_Type *pllCfgList)
 {
     GLB_PLL_REF_CLK_Type refClk;
 
@@ -5894,7 +5945,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_CPU_PLL(GLB_XTAL_Type xtalType, const
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type *pllCfgList)
 {
     GLB_PLL_REF_CLK_Type refClk;
 
@@ -5944,7 +5995,7 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_MIPI_PLL_Div(uint8_t divEn, uint8_t di
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type * pllCfgList)
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const GLB_MU_PLL_Cfg_Type *pllCfgList)
 {
     GLB_PLL_REF_CLK_Type refClk;
 
@@ -5961,6 +6012,83 @@ BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL(GLB_XTAL_Type xtalType, const
     return SUCCESS;
 }
 
+/****************************************************************************/ /**
+ * @brief  set ldo15cis vout select
+ *
+ * @param  ldoLevel: ldo level
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_Set_Ldo15cis_Vout(GLB_LDO15CIS_LEVEL_Type ldoLevel)
+{
+    uint32_t tmpVal;
+
+    CHECK_PARAM(IS_GLB_LDO15CIS_LEVEL_TYPE(ldoLevel));
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO15CIS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO15CIS_VOUT_SEL, ldoLevel);
+    BL_WR_REG(GLB_BASE, GLB_LDO15CIS, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  config mipipll for CSI
+ *
+ * @param  postDivSel: mipipll post div sel
+ * @param  sdmin: mipipll sdmin
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CSI_Config_MIPIPLL(uint8_t postDivSel, uint32_t sdmin)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG5);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_VCO_POSTDIV_SEL, postDivSel);
+    BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG5, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG6);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_SDMIN, sdmin);
+    BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG6, tmpVal);
+
+    return SUCCESS;
+}
+
+/****************************************************************************/ /**
+ * @brief  power up mipipll for CSI
+ *
+ * @param  None
+ *
+ * @return SUCCESS or ERROR
+ *
+*******************************************************************************/
+BL_Err_Type GLB_CSI_Power_Up_MIPIPLL(void)
+{
+    uint32_t tmpVal;
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_MIPIPLL_SFREG, 1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_PU_MIPIPLL, 1);
+    BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_FBDV_RSTB, 1);
+    BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_FBDV_RSTB, 0);
+    BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+    arch_delay_us(2);
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_MIPI_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_MIPIPLL_FBDV_RSTB, 1);
+    BL_WR_REG(GLB_BASE, GLB_MIPI_PLL_CFG0, tmpVal);
+
+    return SUCCESS;
+}
+
 /*@} end of group GLB_Public_Functions */
 
 /*@} end of group GLB */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb_gpio.c
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_glb_gpio.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_glb_gpio.c
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_hbn.c
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_hbn.c
index f77cf0b4e4..8baba5029a
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_hbn.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_hbn.c
@@ -36,7 +36,7 @@
 
 #include "bl808_hbn.h"
 #include "bl808_glb.h"
-#include "bl808_xip_sflash.h"
+#include "bflb_xip_sflash.h"
 
 /** @addtogroup  BL808_Peripheral_Driver
  *  @{
@@ -157,24 +157,24 @@ void ATTR_TCM_SECTION HBN_Mode_Enter(HBN_APP_CFG_Type *cfg)
  * @return None
  *
 *******************************************************************************/
-void ATTR_TCM_SECTION HBN_Power_Down_Flash(SPI_Flash_Cfg_Type *flashCfg)
+void ATTR_TCM_SECTION HBN_Power_Down_Flash(spi_flash_cfg_type *flashCfg)
 {
-    SPI_Flash_Cfg_Type bhFlashCfg;
+    spi_flash_cfg_type bhFlashCfg;
 
     if (flashCfg == NULL) {
-        L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type));
-        XIP_SFlash_Read_Via_Cache_Need_Lock(BL808_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg),
-                                            sizeof(SPI_Flash_Cfg_Type), 0, 0);
-        L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(SPI_Flash_Cfg_Type));
+        L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(spi_flash_cfg_type));
+        bflb_xip_sflash_read_via_cache_need_lock(BL808_FLASH_XIP_BASE + 8 + 4, (uint8_t *)(&bhFlashCfg),
+                                            sizeof(spi_flash_cfg_type), 0, 0);
+        L1C_DCache_Invalid_By_Addr(BL808_FLASH_XIP_BASE + 8 + 4, sizeof(spi_flash_cfg_type));
 
-        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
-        SFlash_Reset_Continue_Read(&bhFlashCfg);
+        bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+        bflb_sflash_reset_continue_read(&bhFlashCfg);
     } else {
-        SF_Ctrl_Set_Owner(SF_CTRL_OWNER_SAHB);
-        SFlash_Reset_Continue_Read(flashCfg);
+        bflb_sf_ctrl_set_owner(SF_CTRL_OWNER_SAHB);
+        bflb_sflash_reset_continue_read(flashCfg);
     }
 
-    SFlash_Powerdown();
+    bflb_sflash_powerdown();
 }
 
 /****************************************************************************/ /**
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_l1c.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_l1c.c
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_l1c.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_l1c.c
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_pds.c
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_pds.c
index 4a8f3d8592..a2c24c8121
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_pds.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_pds.c
@@ -335,7 +335,7 @@ BL_Sts_Type ATTR_TCM_SECTION PDS_Get_GPIO_Pad_IntStatus(GLB_GPIO_Type pad)
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinCfg)
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(uint8_t pinCfg)
 {
     switch (pinCfg) {
         case SF_IO_EXT_SF2:
@@ -360,7 +360,7 @@ BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None(SF_Ctrl_Pin_Select pinC
  * @return SUCCESS or ERROR
  *
 *******************************************************************************/
-BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(SF_Ctrl_Pin_Select pinCfg)
+BL_Err_Type ATTR_TCM_SECTION PDS_Set_Flash_Pad_Pull_None_Fast(uint8_t pinCfg)
 {
     uint32_t tmpVal;
 
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram_uhs.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_psram_uhs.c
old mode 100644
new mode 100755
similarity index 98%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram_uhs.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_psram_uhs.c
index 1b3f6cca84..1f06618aff
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_psram_uhs.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_psram_uhs.c
@@ -35,6 +35,7 @@
   */
 
 #include "bl808_psram_uhs.h"
+#include "bl808_uhs_phy.h"
 #include "bl808_common.h"
 #include "bl808_glb.h"
 #include "psram_uhs_reg.h"
@@ -91,7 +92,7 @@ int config_uhs_phy(uint32_t datarate)
     uint32_t tmpVal = 0;
 
     if (datarate > 1866) {
-        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA0A1323);
+        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F0A1323);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0b030404);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x050e0419);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x0a6a1c1c);
@@ -102,7 +103,7 @@ int config_uhs_phy(uint32_t datarate)
         BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
 
     } else if (datarate > 1600) {
-        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA283203);
+        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F283203);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x0a020303);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040d0416);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x091e1818);
@@ -113,7 +114,7 @@ int config_uhs_phy(uint32_t datarate)
         BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
 
     } else if (datarate > 1066) {
-        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA270212);
+        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x09020303);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x040c0313);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x07d11515);
@@ -123,7 +124,7 @@ int config_uhs_phy(uint32_t datarate)
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 1);
         BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
     } else if (datarate > 800) {
-        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA270212);
+        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F270212);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x06010202);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0309020d);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x05360e0e);
@@ -134,7 +135,7 @@ int config_uhs_phy(uint32_t datarate)
         BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
 
     } else if (datarate > 666) {
-        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA041020);
+        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F041020);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x0208010a);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03e90b0b);
@@ -144,7 +145,7 @@ int config_uhs_phy(uint32_t datarate)
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
         BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
     } else if (datarate > 400) {
-        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA130010);
+        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F130010);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x05000101);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02080108);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x03420909);
@@ -154,7 +155,7 @@ int config_uhs_phy(uint32_t datarate)
         tmpVal = BL_SET_REG_BITS_VAL(tmpVal, PSRAM_UHS_PHY_WL_CEN_ANA, 0);
         BL_WR_REG(PSRAM_UHS_BASE, PSRAM_UHS_PHY_CFG_50, tmpVal);
     } else {
-        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0xAA020010);
+        BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_30_OFFSET, 0x0F020010);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_34_OFFSET, 0x04000101);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_38_OFFSET, 0x02070106);
         BL_WR_WORD(PSRAM_UHS_BASE + PSRAM_UHS_PHY_CFG_3C_OFFSET, 0x01f50606);
@@ -327,7 +328,7 @@ void Psram_UHS_Init(PSRAM_UHS_Cfg_Type *cfg)
 
     /* set refresh paramater */
     /* 1. auto refresh clock source is pck_t, Adjust pck_t_div so that the frequency is around ~50Mhz */
-/*     tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);
+    /*     tmpVal = BL_RD_REG(PSRAM_UHS_BASE, PSRAM_UHS_UHS_MANUAL);
     tmpVal &= 0x00ffffff;
 
     if (cfg->pck_freq >= 2200) {
@@ -820,6 +821,13 @@ void Psram_UHS_x16_Init(uint32_t uhs_pll_clk)
     PSram_UHS_Write_Reg(&writeReg);
 }
 
+void Psram_UHS_x16_Init_Override(PSRAM_UHS_Cfg_Type *cfg)
+{
+    /* first initial psram controller*/
+    Psram_UHS_Init(cfg);
+
+    uhs_phy_init(cfg);
+}
 /*@} end of group PSRAM_UHS_Public_Functions */
 
 /*@} end of group PSRAM_UHS */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sdh.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_sdh.c
old mode 100644
new mode 100755
similarity index 98%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sdh.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_sdh.c
index d7ae372553..b877bab318
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_sdh.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_sdh.c
@@ -75,9 +75,7 @@ static SDH_Handle_Cfg_Type *sdhHandle = NULL;
 /** @defgroup  SDH_Private_Fun_Declaration
  *  @{
  */
-#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
 static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle);
-#endif
 
 /*@} end of group SDH_Private_Fun_Declaration */
 
@@ -904,7 +902,7 @@ SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint3
     }
 
     /* Calculate the start entry for multiple descriptor mode, ADMA engine is not stop, so update the descriptor
-    data address and data size is enough */
+	data address and data size is enough */
     if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
         for (i = 0U; i < maxEntries; i++) {
             if ((adma2Entries[i].attribute & SDH_ADMA2_DESC_FLAG_VALID) == 0U) {
@@ -944,7 +942,7 @@ SDH_Stat_Type SDH_CreateADMA2Descriptor(SDH_ADMA2_Desc_Type *adma2Entries, uint3
     }
 
     /* add a dummy valid ADMA descriptor for multiple descriptor mode, this is useful when transfer boot data, the ADMA
-    engine  will not stop at block gap */
+	engine  will not stop at block gap */
     if (flag == SDH_ADMA_FLAG_MULTI_DESC) {
         //adma2Entries[startEntries + 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;
         adma2Entries[i - 1U].attribute |= SDH_ADMA2_DESC_FLAG_TRANSFER;
@@ -977,7 +975,7 @@ SDH_Stat_Type SDH_SetInternalDmaConfig(SDH_DMA_Cfg_Type *dmaCfg, const uint32_t
         }
 
         /* In simple DMA mode if use auto CMD23, address should load to ADMA addr,
-             and block count should load to DS_ADDR*/
+		     and block count should load to DS_ADDR*/
         if (enAutoCmd23) {
             BL_WR_REG(SDH_BASE, SDH_SD_ADMA_SYS_ADDR_1, (uintptr_t)data);
         } else {
@@ -1041,7 +1039,7 @@ SDH_Stat_Type SDH_CreateAdmaEntryConfig(SDH_DMA_Cfg_Type *dmaCfg, SDH_Data_Cfg_T
     }
 
     /* For internal dma, internal DMA configurations should not update the configurations when continous transfer the
-     * boot data, only the DMA descriptor need update */
+	 * boot data, only the DMA descriptor need update */
     if ((stat == SDH_STAT_SUCCESS) && (dataCfg->dataType != SDH_TRANS_DATA_BOOT_CONT)) {
         stat = SDH_SetInternalDmaConfig(dmaCfg, data, dataCfg->enableAutoCommand23);
     }
@@ -1109,10 +1107,10 @@ SDH_Stat_Type SDH_TransferBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Type
     }
 
     /*
-    tmp = BL_RD_REG16(SDH_BASE,SDH_SD_ADMA_ERROR_STATUS);
-    bflb_platform_printf("SDH_SD_ADMA_ERROR_STATUS->0x%x!\r\n",tmp);
-    tmp = BL_RD_REG16(SDH_BASE,SDH_SD_AUTO_CMD12_ERROR_STATUS);
-    */
+	tmp = BL_RD_REG16(SDH_BASE,SDH_SD_ADMA_ERROR_STATUS);
+	bflb_platform_printf("SDH_SD_ADMA_ERROR_STATUS->0x%x!\r\n",tmp);
+	tmp = BL_RD_REG16(SDH_BASE,SDH_SD_AUTO_CMD12_ERROR_STATUS);
+	*/
 
     /* Wait for transferring data finish */
     if ((dataCfg != NULL) && (stat == SDH_STAT_SUCCESS)) {
@@ -1173,14 +1171,14 @@ SDH_Stat_Type SDH_TransferNonBlocking(SDH_DMA_Cfg_Type *dmaCfg, SDH_Trans_Cfg_Ty
     }
 
 #if 0
-    SDH_SendCommand(cmdCfg);
+	SDH_SendCommand(cmdCfg);
 
 
-    /* Wait command done */
-    if((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL))
-    {
-        stat = SDH_WaitCommandDone(cmdCfg);
-    }
+	/* Wait command done */
+	if((dataCfg == NULL) || (dataCfg->dataType == SDH_TRANS_DATA_NORMAL))
+	{
+		stat = SDH_WaitCommandDone(cmdCfg);
+	}
 
 #endif
 
@@ -1227,7 +1225,6 @@ void SDH_InstallHandleCallback(SDH_Handle_Cfg_Type *handle,
  * @return None
  *
 *******************************************************************************/
-#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
 static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
 {
     uint32_t intFlag, intMask;
@@ -1343,7 +1340,6 @@ static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
 
     SDH_ClearIntStatus(intFlag);
 }
-#endif
 
 /****************************************************************************/ /**
  * @brief  SDH interrupt handler
@@ -1353,12 +1349,10 @@ static void SDH_IntHandler(IRQn_Type intPeriph, SDH_Handle_Cfg_Type *handle)
  * @return None
  *
 *******************************************************************************/
-#if (defined BOOTROM) || (!defined BFLB_USE_HAL_DRIVER)
 void SDH_MMC1_IRQHandler(void)
 {
     SDH_IntHandler(SDH_IRQn, sdhHandle);
 }
-#endif
 
 /*@} end of group SDH_Public_Functions */
 
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_tzc_sec.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_tzc_sec.c
old mode 100644
new mode 100755
similarity index 99%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_tzc_sec.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_tzc_sec.c
index 8cdafef270..6ae89f3fa5
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/std_drv/src/bl808_tzc_sec.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_tzc_sec.c
@@ -196,7 +196,7 @@ void Tzc_Sec_Set_MM_Slave_Group(TZC_SEC_MM_Slave_Type slaveType, uint8_t group)
     }
     group = 1 << (group);
 
-    if (slaveType < TZC_SEC_MM_SLAVE_DSP2_MISC) {
+    if (slaveType < TZC_SEC_MM_SLAVE_ISP_MISC) {
         /* set group */
         tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S0);
         tmpVal &= (~(3 << (slaveType * 2)));
@@ -209,7 +209,7 @@ void Tzc_Sec_Set_MM_Slave_Group(TZC_SEC_MM_Slave_Type slaveType, uint8_t group)
         BL_WR_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S_LOCK0, tmpVal);
 
     } else if (slaveType < TZC_SEC_MM_SLAVE_CODEC_MISC) {
-        slaveType -= TZC_SEC_MM_SLAVE_DSP2_MISC;
+        slaveType -= TZC_SEC_MM_SLAVE_ISP_MISC;
 
         /* set group */
         tmpVal = BL_RD_REG(TZ1_BASE, TZC_SEC_TZC_MM_BMX_S1);
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c
new file mode 100755
index 0000000000..72d5a6fc81
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/src/bl808_uhs_phy.c
@@ -0,0 +1,2894 @@
+#include "bl808_uhs_phy.h"
+#include 
+#include 
+#include 
+#include "psram_uhs_reg.h"
+#include "glb_reg.h"
+#include "pds_reg.h"
+
+#define bl808_DBG_RF (0)    // 0 is for commit with only err log, 1 is for all debug log, 2 is for key debug log
+#if bl808_DBG_RF == 1
+    #define uhs_phy_printf_debug printf  // debug mode
+    #define uhs_phy_printf printf 
+    #define uhs_phy_printfe printf
+#elif bl808_DBG_RF == 2
+    #define uhs_phy_printf_debug(...)
+    #define uhs_phy_printf printf  // commit it out in release version, use to collect data
+    // #define uhs_phy_printf(...) //  used in release version
+    #define uhs_phy_printfe printf
+#else
+    #define uhs_phy_printf_debug(...)
+    #define uhs_phy_printf(...)
+    #define uhs_phy_printfe printf
+#endif
+
+#define ODT_EN (0)
+// #define PSRAM_32MB (0)
+#define CACHE_EN (0)        // unused !
+
+static uhs_phy_cal_res_struct cal_res;
+uhs_phy_cal_res_struct* uhs_phy_cal_res = &cal_res;
+static uint8_t err_flag = 0;
+#define CHECK_ERR_FLAG(func,args) {\
+    func args;\
+    if(err_flag)return err_flag;\
+}
+
+static uint32_t cache_state = 0;
+static uint8_t uhs_latency_code = 1;
+static uint32_t dqs_dq_delta = 0;
+static uint32_t dcache_original = 0;
+static uint32_t dcache_current = 0;
+static uint32_t dcache_end = 0;
+static uint8_t regr_done_err = 0;
+static uint8_t reg_read_err = 0;
+static uint8_t reg_write_err = 0;
+static uint8_t init_array_write_err = 0;
+static uint8_t array_read_err = 0;
+static uint32_t addr_dump = 0x3000F000;
+// 
+static uint32_t addr_rarray = 0x50000000;
+static uint32_t data0_rarray = 0x12345678;
+static uint32_t data1_rarray = 0x87654321;
+// uint32_t datarate_glb;
+static uint32_t latency_wr[2] = {9,30};
+static PSRAM_UHS_Cfg_Type *cfg_glb;
+// static uint32_t addr_sr[3] = {0x3000f014,0x3000f018,0x3000f020};
+// static uint32_t val_sr[3] = {0x0,0x0,0x0};
+static uint32_t latency_wr_2kM[2] = {13,41};
+static uint8_t cal_done_flag = 0;
+static uint8_t print_flag = 0;
+// static uint32_t latency_wr_2kM_init[2] = {13,36};
+static uint8_t flag_ck1 = 0;
+static uint8_t flag_ck2 = 0;
+
+void set_uhs_latency_w(uint32_t uhs_latency);
+void set_uhs_latency_r(uint32_t uhs_latency);
+void uhs_reset(uint8_t ma_rb);
+void uhs_phy_reg_dump(void);
+void set_or_uhs(void);
+uint8_t mr_read_back(void);
+uint8_t uhs_phy_init_core(PSRAM_UHS_Cfg_Type *cfg);
+
+void uhs_phy_delay_us(uint32_t us)
+{
+    arch_delay_us(us);
+}
+
+void uhs_phy_delay_ms(uint32_t ms)
+{
+    arch_delay_ms(ms);
+}
+
+void uhs_phy_af_reg(uint32_t REG_PCK_T_DIV,uint32_t REG_WIN_CYCLE,uint32_t REG_WIN_REF_CNT,uint32_t REG_REFI_CYCLE,uint32_t REG_BUST_CYCLE)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,REG_PCK_T_DIV);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,REG_WIN_CYCLE);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,REG_WIN_REF_CNT);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,REG_REFI_CYCLE);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,REG_BUST_CYCLE);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal);
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+}
+
+void uhs_phy_af_onoff(uint8_t onoff){
+    uint32_t tmpVal = 0;
+
+    if(onoff){
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+        uhs_phy_delay_us(50);
+        // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1);
+        // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+        // uhs_phy_delay_us(50);
+    }else{
+        // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x0);
+        // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+        // uhs_phy_delay_us(50);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x0);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+        uhs_phy_delay_us(50);
+    }
+}
+
+void uhs_phy_af_cfg(void)
+{
+    // uint32_t tmpVal = 0;
+
+    uhs_phy_af_onoff(0);
+
+    if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB && cfg_glb->isHighTem == PSRAM_UHS_HIGH_TEMP){
+        if(cfg_glb->pck_freq == 2000){
+            uhs_phy_af_reg(0x4,0xF423F,0x2000,0x79,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1900){
+            uhs_phy_af_reg(0x4,0xE7EEF,0x2000,0x72,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1800){
+            uhs_phy_af_reg(0x4,0xDBB9F,0x2000,0x6C,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1700){
+            uhs_phy_af_reg(0x4,0xCF84F,0x2000,0x66,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1600){
+            uhs_phy_af_reg(0x4,0xC34FF,0x2000,0x60,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1500){
+            uhs_phy_af_reg(0x4,0xB71AF,0x2000,0x5A,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1400){
+            uhs_phy_af_reg(0x4,0xAAE5F,0x2000,0x54,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1300){
+            uhs_phy_af_reg(0x4,0x9EB0F,0x2000,0x4E,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1200){
+            uhs_phy_af_reg(0x4,0x927BF,0x2000,0x48,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1100){
+            uhs_phy_af_reg(0x4,0x8646F,0x2000,0x42,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1000){
+            uhs_phy_af_reg(0x4,0x7A11F,0x2000,0x3C,0x3);
+        }
+        else if(cfg_glb->pck_freq == 900){
+            uhs_phy_af_reg(0x4,0x6DDCF,0x2000,0x35,0x3);
+        }
+        else{
+            uhs_phy_af_reg(0x4,0x61A7F,0x2000,0x2F,0x3);
+        }
+    }
+    else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        if(cfg_glb->pck_freq == 2000){
+            uhs_phy_af_reg(0x4,0x1E847F,0x2000,0xF3,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1900){
+            uhs_phy_af_reg(0x4,0x1CFDDF,0x2000,0xE6,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1800){
+            uhs_phy_af_reg(0x4,0x1B773F,0x2000,0xDA,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1700){
+            uhs_phy_af_reg(0x4,0x19F09F,0x2000,0xCE,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1600){
+            uhs_phy_af_reg(0x4,0x1869FF,0x2000,0xC2,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1500){
+            uhs_phy_af_reg(0x4,0x16E35F,0x2000,0xB6,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1400){
+            uhs_phy_af_reg(0x4,0x155CBF,0x2000,0xA9,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1300){
+            uhs_phy_af_reg(0x4,0x13D61F,0x2000,0x9D,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1200){
+            uhs_phy_af_reg(0x4,0x124F7F,0x2000,0x91,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1100){
+            uhs_phy_af_reg(0x4,0x10C8DF,0x2000,0x85,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1000){
+            uhs_phy_af_reg(0x4,0xF423F,0x2000,0x79,0x3);
+        }
+        else if(cfg_glb->pck_freq == 900){
+            uhs_phy_af_reg(0x4,0xDBB9F,0x2000,0x6C,0x3);
+        }
+        else{
+            uhs_phy_af_reg(0x4,0xC34FF,0x2000,0x60,0x3);
+        }
+    }
+    else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB && cfg_glb->isHighTem == PSRAM_UHS_HIGH_TEMP){
+        if(cfg_glb->pck_freq == 2000){
+            uhs_phy_af_reg(0x4,0xF423F,0x1000,0xF3,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1900){
+            uhs_phy_af_reg(0x4,0xE7EEF,0x1000,0xE6,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1800){
+            uhs_phy_af_reg(0x4,0xDBB9F,0x1000,0xDA,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1700){
+            uhs_phy_af_reg(0x4,0xCF84F,0x1000,0xCE,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1600){
+            uhs_phy_af_reg(0x4,0xC34FF,0x1000,0xC2,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1500){
+            uhs_phy_af_reg(0x4,0xB71AF,0x1000,0xB6,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1400){
+            uhs_phy_af_reg(0x4,0xAAE5F,0x1000,0xA9,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1300){
+            uhs_phy_af_reg(0x4,0x9EB0F,0x1000,0x9D,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1200){
+            uhs_phy_af_reg(0x4,0x927BF,0x1000,0x91,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1100){
+            uhs_phy_af_reg(0x4,0x8646F,0x1000,0x85,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1000){
+            uhs_phy_af_reg(0x4,0x7A11F,0x1000,0x79,0x3);
+        }
+        else if(cfg_glb->pck_freq == 900){
+            uhs_phy_af_reg(0x4,0x6DDCF,0x1000,0x6C,0x3);
+        }
+        else{
+            uhs_phy_af_reg(0x4,0x61A7F,0x1000,0x60,0x3);
+        }
+    }
+    else{
+        if(cfg_glb->pck_freq == 2000){
+            uhs_phy_af_reg(0x4,0x1E847F,0x1000,0x1E7,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1900){
+            uhs_phy_af_reg(0x4,0x1CFDDF,0x1000,0x1CE,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1800){
+            uhs_phy_af_reg(0x4,0x1B773F,0x1000,0x1B6,0x6);
+        }
+        else if(cfg_glb->pck_freq == 1700){
+            uhs_phy_af_reg(0x4,0x19F09F,0x1000,0x19E,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1600){
+            uhs_phy_af_reg(0x4,0x1869FF,0x1000,0x185,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1500){
+            uhs_phy_af_reg(0x4,0x16E35F,0x1000,0x16D,0x5);
+        }
+        else if(cfg_glb->pck_freq == 1400){
+            uhs_phy_af_reg(0x4,0x155CBF,0x1000,0x154,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1300){
+            uhs_phy_af_reg(0x4,0x13D61F,0x1000,0x13C,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1200){
+            uhs_phy_af_reg(0x4,0x124F7F,0x1000,0x123,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1100){
+            uhs_phy_af_reg(0x4,0x10C8DF,0x1000,0x10B,0x4);
+        }
+        else if(cfg_glb->pck_freq == 1000){
+            uhs_phy_af_reg(0x4,0xF423F,0x1000,0xF3,0x3);
+        }
+        else if(cfg_glb->pck_freq == 900){
+            uhs_phy_af_reg(0x4,0xDBB9F,0x1000,0xDA,0x3);
+        }
+        else{
+            uhs_phy_af_reg(0x4,0xC34FF,0x1000,0xC2,0x3);
+        }
+    }
+
+    uhs_phy_af_onoff(1);
+}
+
+void Psram_UHS_Init_Override(PSRAM_UHS_Cfg_Type *cfg){
+    uint32_t tmpVal = 0;
+
+    Psram_UHS_Init(cfg);
+    if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x1);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x1f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+    }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+    }
+
+    #if CAL_MODE == 1
+    uhs_phy_af_cfg();
+    #endif
+
+    set_or_uhs();
+
+    tmpVal = BL_RD_REG(GLB_BASE, GLB_LDO12UHS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal, GLB_LDO12UHS_VOUT_SEL, 5);
+    BL_WR_REG(GLB_BASE, GLB_LDO12UHS, tmpVal);
+    uhs_phy_printf("GLB_LDO12UHS: %lx\r\n",tmpVal);
+    uhs_phy_delay_us(250);
+}
+
+void power_up_mm(uint8_t off)
+{
+    uint32_t tmpVal = 0;
+    if (off == 0)
+    {
+        // power up MM domain
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(150);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        // uhs_phy_delay_us(10);
+        // uhs_phy_delay_ms(1);
+    }
+    else
+    {
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_ISO_EN,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_GATE_CLK,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_MEM_STBY,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PDS_RST,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+        uhs_phy_delay_us(150);
+        tmpVal = BL_RD_REG(PDS_BASE,PDS_CTL2);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PDS_CR_PDS_FORCE_MM_PWR_OFF,off);
+        BL_WR_REG(PDS_BASE,PDS_CTL2,tmpVal);
+    }
+    uhs_phy_delay_us(100);
+}
+
+void power_up_uhspll(void)
+{
+    // power_up_uhspll
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL,0x1);
+    BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+    uhs_phy_delay_us(10);
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDM_RSTB,0x0);
+    BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+    uhs_phy_delay_us(50);
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SDM_RSTB,0x1);
+    BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+    uhs_phy_delay_us(50);
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x0);
+    BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+    uhs_phy_delay_us(50);
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_FBDV_RSTB,0x1);
+    BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG0,tmpVal);
+    uhs_phy_delay_us(50);
+}
+
+void power_up_ldo12uhs(void)
+{
+    // use internal LDO 
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_VOUT_SEL,0x5);
+    BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+    uhs_phy_delay_us(200);
+    // use external LDO
+    // tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN,0x0);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x1);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0);
+    // BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+}
+
+void set_cen_ck_ckn(void)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+    uhs_phy_delay_us(10);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xfc);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x1);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+    uhs_phy_delay_us(10);
+}
+
+void set_or_uhs(void)
+{
+    uint32_t tmpVal = 0;
+    
+    if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x1);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+    }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PSRAM_TYPE,0x2);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+    }
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,0x8);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,0xB);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,0x7);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,0x7);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,0x6);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,0x6);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_SR,0x2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_SR,0x2);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_P_REG,0x3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_DN_N_REG,0x3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_P_REG,0x3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_UP_N_REG,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0N_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_RX,0x0); 
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1N_DLY_RX,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+    uhs_phy_delay_us(200);
+}
+
+void switch_to_ldo12uhs(void)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcc);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+    uhs_phy_delay_us(200);
+}
+
+void release_cen_ck_ckn(void)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xcf);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY0,0x0);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+    uhs_phy_delay_us(10);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_P_REG,0x3);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ_OE_MID_N_REG,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+    uhs_phy_delay_us(10);
+}
+
+void uhs_phy_pwr_down(void)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_LDO12UHS_PULLDOWN_SEL,0x0);
+    BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+    uhs_phy_delay_us(100);
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_LDO12UHS,0x0);
+    BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DMY1,0xff);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_40,tmpVal);
+    uhs_phy_delay_us(100);
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_LDO12UHS);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_PU_UHSPLL_SFREG,0x0);
+    BL_WR_REG(GLB_BASE,GLB_LDO12UHS,tmpVal);
+    uhs_phy_delay_us(100);
+}
+
+void psram_init(void)
+{
+    uint8_t i;
+    uint32_t tmpVal = 0;
+    for (i = 0; i < 1; i++){
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        // if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        //     tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x1f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+        // }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        //     tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_ADDRMB_MSK,0x3f); // 3F -> 512Mb psram, 1F -> 256Mb psram
+        // }
+        // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_LINEAR_BND_B,0xb);
+        // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_INIT_EN,0x1);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_GLBR_PULSE,0x1);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+        uhs_phy_delay_us(100);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+        uhs_phy_delay_us(100);
+    }
+
+    // // psram auto refresh at 2000Mbps
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_CYCLE,0x001E0C4);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_1,tmpVal);
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_WIN_REF_CNT,0x1007);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REFI_CYCLE,0x01d);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_2,tmpVal);
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_BUST_CYCLE,0x1);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_AUTO_FRESH_4,tmpVal);
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_PCK_T_DIV,0x40);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_MANUAL,tmpVal);
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0x1);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+    // // psram cmd timing < 2000Mbps
+    // BL_WR_WORD(0x3000F030,0x18090610);
+}
+
+void set_uhs_phy_init(void)
+{
+    // set phy & controller
+    uint32_t tmpVal = 0;
+    // default latency(800MHz)
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,0x2);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,0x7);
+    // // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x0);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,0x1);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,0x2);
+    // // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x1);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,0x2);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,0x2);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_CTRL_HW,0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x05000501);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x02080108);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x03e90b0b);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x040b0308);
+    }else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x09020303);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x040c0313);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x07d11515);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x060f050c);
+    }
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_CEN_ANA,0x1);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,tmpVal);
+    uhs_phy_delay_us(100);
+}
+
+void set_uhs_phy(void)
+{
+    uint32_t tmpVal = 0;
+    // set phy & controller
+    // latency code=3 (1066MHz)
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a1323);  // if fail than use 0x0f391323 
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a0313); // tDQSS -> -1
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,0x0f0a3233); // tDQSS -> 1
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0x0);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_CTRL_HW,0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_VREF_MODE,0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_OE_TIMER,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    set_uhs_latency_w(latency_wr[0]);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_34,0x0b030404);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_38,0x050e0418);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_3C,0x0a6a1c1c);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_44,0x07110710);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_50,0x01333333);
+
+    uhs_phy_delay_us(100);
+} 
+
+uint8_t uhs_err_handler(uint8_t err)
+{
+    err_flag = 1;
+    uhs_phy_cal_res->err_type = err;
+#ifndef BFLB_BOOT2
+    switch (err) {
+        case UHS_REGR_GNT_ERR:
+            uhs_phy_printfe("UHS_REGR_GNT_ERR\r\n");
+            break;
+        case UHS_REGR_DONE_ERR:
+            uhs_phy_printfe("UHS_REGR_DONE_ERR = %d\r\n",regr_done_err);
+            uhs_phy_cal_res->err_sub_type = regr_done_err;
+            break;
+        case UHS_REGW_GNT_ERR:
+            uhs_phy_printfe("UHS_REGW_GNT_ERR\r\n");
+            break;            
+        case UHS_REGW_DONE_ERR:
+            uhs_phy_printfe("UHS_REGW_DONE_ERR\r\n");
+            break;
+        case UHS_LATENCY_CODE_WRITE_ERR:
+            uhs_phy_printfe("UHS_LATENCY_CODE_WRITE_ERR\r\n");
+            break;
+        case UHS_INIT_ARRAY_WRITE_ERR:
+            uhs_phy_printfe("UHS_INIT_ARRAY_WRITE_ERR = %d\r\n",init_array_write_err);
+            uhs_phy_cal_res->err_sub_type = init_array_write_err;
+            break;         
+        case UHS_REG_READ_CAL_ERR:
+            uhs_phy_printfe("UHS_REG_READ_CAL_ERR = %d\r\n",reg_read_err);
+            uhs_phy_cal_res->err_sub_type = reg_read_err;
+            break;
+        case UHS_REG_WRITE_CAL_ERR:
+            uhs_phy_printfe("UHS_REG_WRITE_CAL_ERR = %d\r\n",reg_write_err);
+            uhs_phy_cal_res->err_sub_type = reg_write_err;
+            break;
+        case UHS_ARRAY_READ_LAT_ERR:
+            uhs_phy_printfe("UHS_ARRAY_READ_LAT_ERR = %d\r\n",array_read_err);
+            uhs_phy_cal_res->err_sub_type = array_read_err;
+            break;
+        case UHS_ARRAY_WRITE_CK_ERR:
+            uhs_phy_printfe("UHS_ARRAY_WRITE_CK_ERR\r\n");
+            break;
+        case UHS_ARRAY_READ_CAL_ERR:
+            uhs_phy_printfe("UHS_ARRAY_READ_CAL_ERR\r\n");
+            break;
+        case UHS_ARRAY_WRITE_CAL_ERR:
+            uhs_phy_printfe("UHS_ARRAY_WRITE_CAL_ERR\r\n");
+            break;
+        case UHS_CACHE_ENABLE_ERR:
+            uhs_phy_printfe("UHS_CACHE_ENABLE_ERR\r\n");
+            break;
+        case UHS_CACHE_DISABLE_ERR:
+            uhs_phy_printfe("UHS_CACHE_DISABLE_ERR\r\n");
+            break;
+        case UHS_CACHE_RECOVER_ERR:
+            uhs_phy_printfe("UHS_CACHE_RECOVER_ERR\r\n");
+            break;
+        case UHS_REG_WRITE_2kM_ERR:
+            uhs_phy_printfe("UHS_REG_WRITE_2kM_ERR\r\n");
+            break;
+        case UHS_BAD_DIE_ERR:
+            uhs_phy_printfe("UHS_BAD_DIE_ERR\r\n");
+            break;
+        case UHS_DIAGONAL_TEST_ERR:
+            uhs_phy_printfe("UHS_DIAGONAL_TEST_ERR\r\n");
+            break;
+        case UHS_ALL_ADDR_TEST_ERR:
+            uhs_phy_printfe("UHS_ALL_ADDR_TEST_ERR\r\n");
+            break;
+        default:
+            break;
+    }
+    uhs_phy_printfe("ERR_AT %ldMbps\r\n",cfg_glb->pck_freq);
+    uhs_phy_reg_dump();
+#else
+    uhs_phy_printfe("uhs_err_handler:%d\r\n",err);
+#endif
+    #if CAL_MODE == 0 || CAL_MODE == 1
+    while(1){
+        uhs_phy_printfe("%d",err);
+        uhs_phy_delay_ms(10000);
+    };
+    #endif
+    return err_flag;
+}
+
+void uhs_phy_reg_dump(void){
+    uint32_t len = 0x150;
+    uint32_t i = 0;
+
+    // uhs_phy_printf_debug("UHS_PHY_REG_DUMP_START\r\n");
+    // for(i = 0;i <= len;i = i+4){
+    //     uhs_phy_printf_debug("0x%lx,0x%lx\r\n",(addr_dump + i),*((volatile uint32_t*)(addr_dump + i)));
+    // }
+    // uhs_phy_printf_debug("UHS_PHY_REG_DUMP_END\r\n");
+    uhs_phy_printfe("UHS_PHY_REG_DUMP_START\r\n");
+    for(i = 0;i <= len;i = i+4){
+        uhs_phy_printfe("0x%lx,0x%lx\r\n",(addr_dump + i),*((volatile uint32_t*)(addr_dump + i)));
+    }
+    uhs_phy_printfe("UHS_PHY_REG_DUMP_END\r\n");
+}
+
+uint8_t uhs_reg_w(uint32_t uhs_latency,uint32_t uhs_drive,uint32_t ma,uint32_t BL_32)
+{
+    uint32_t tmpVal = 0;
+    uint32_t count = 0;
+    if(ma == 0)
+    {
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_LATENCY,uhs_latency);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_DRIVE_ST,uhs_drive); 
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal);
+    }
+    else if(ma == 2)
+    {
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE);
+        if (BL_32 == 1){
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x1);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x1);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0);
+        }else if (BL_32 == 2){
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x1);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x1);
+        }else{
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_64,0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_32,0x0);
+            tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_UHS_BL_16,0x0);
+        }  
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_PSRAM_CONFIGURE,tmpVal);
+    }
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1);  //reg_config_req
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+    // uhs_phy_printf_debug("reg_w GNT while\r\n");
+    while (1)
+    {
+        if (count == 100000){
+            return uhs_err_handler(UHS_REGW_GNT_ERR);
+        }
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT);
+        if (tmpVal == 1)
+        {
+            uhs_phy_printf_debug("reg_w GNT pass\r\n");
+            break;
+        }
+        count ++;   
+    }
+    
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1);  //reg_regw_pulse
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+
+    count = 0;
+    while (1)
+    {
+        if (count == 100000){
+            return uhs_err_handler(UHS_REGW_DONE_ERR);
+        }
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGW_DONE); //regw_done
+        if (tmpVal == 1)
+        {
+            uhs_phy_printf_debug("reg_w DONE pass\r\n");
+            break;
+        }
+        count ++;
+    }
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0);  //reg_config_req
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+    uhs_phy_delay_us(10);
+
+    return 0;
+}
+
+uint8_t uhs_reg_r(uint32_t ma,uint8_t flag)
+{
+    uint32_t tmpVal = 0;
+    // uint32_t tmpInd = 0;
+    uint32_t count = 0;
+    uint8_t opc = 1;
+
+    if (flag == 1){
+        uhs_phy_af_onoff(0);
+
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_FORCE_FSM,0x1);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+        uhs_phy_delay_us(50);
+    }
+
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,ma); //reg_mode_reg
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1);  //reg_config_req
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+    while (1)
+    {
+        if (count == 100000){
+            return uhs_err_handler(UHS_REGR_GNT_ERR);
+        }
+        uhs_phy_delay_us(10);
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+        tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_GNT);
+        if (tmpVal == 1)
+        {
+            uhs_phy_printf_debug("reg_r GNT pass\r\n");
+            break;
+        }
+        count ++;
+    }
+    
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGR_PULSE,0x1);  //reg_regr_pulse
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+
+    count = 0;
+    while (1)
+    {
+        if (flag == 1){
+            if (count == 100){
+                regr_done_err = 2;
+                return uhs_err_handler(UHS_REGR_DONE_ERR);
+            }
+            uhs_phy_delay_us(20);
+            tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); //regr_done
+            if (tmpVal == 1){
+                uhs_phy_printf_debug("reg_r DONE pass\r\n");
+                break;
+            }
+            count ++;
+
+            // if (tmpVal == 1){
+            //     uhs_phy_printf_debug("reg_r DONE pass\r\n");
+            //     opc = 1;
+            // }else{
+            //     uhs_phy_printf_debug("reg_r DONE fail\r\n");
+            //     opc = 0;
+            // }
+            // break;
+        }
+        else{
+            if (count == 100000){
+                regr_done_err = 1;
+                return uhs_err_handler(UHS_REGR_DONE_ERR);
+            }
+            uhs_phy_delay_us(10);
+            tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+            tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_STS_REGR_DONE); //regr_done
+            if (tmpVal == 1){
+                uhs_phy_printf_debug("reg_r DONE pass\r\n");
+                break;
+            }
+            count ++;
+        }         
+    }
+
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0);  //reg_config_req
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+    if (opc == 0){
+        uhs_reset(0);
+    }
+
+    if (flag == 1){
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48);
+        tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_FORCE_FSM,0x0);
+        BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_48,tmpVal);
+        uhs_phy_delay_us(50);
+
+        uhs_phy_af_onoff(1);
+    }
+
+    uhs_phy_delay_us(10);
+    return opc;
+}
+
+
+void cfg_dq_rx(uint8_t dq){
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_RX,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_RX,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+    uhs_phy_delay_us(10);
+}
+
+void cfg_dqs_rx(uint8_t dqs){
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DIFF_DLY_RX,dqs);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DIFF_DLY_RX,dqs);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+    uhs_phy_delay_us(10);
+}
+
+void cfg_ck_cen_drv(uint8_t array_ck_dly_drv,uint8_t array_cen_dly_drv){
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CK_DLY_DRV,array_ck_dly_drv);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_CEN_DLY_DRV,array_cen_dly_drv);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00,tmpVal);
+    uhs_phy_delay_us(50);
+}
+
+void uhs_reset(uint8_t ma_rb)
+{
+	// uint32_t tmpVal = 0;
+    // uint32_t len = 0x150;
+    // uint32_t val_sr[len>>2];
+    // int32_t i = 0;
+
+    uhs_phy_printf("IN_UHS_RESET\r\n");
+
+    // for( i = len ; i >= 0 ; i = i-4 ){
+    //     if( i != 0x4 ){
+    //         val_sr[i>>2] = *((volatile uint32_t*)(addr_dump + i));
+    //     }
+    // }
+
+    // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    // tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_AF_EN,0);
+    // BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+    // uhs_phy_delay_us(100);
+
+	// tmpVal = BL_RD_WORD(0x30007044);
+	// tmpVal = tmpVal | 0x00008000;
+	// BL_WR_WORD(0x30007044,tmpVal);
+	// uhs_phy_delay_us(100);
+	// tmpVal = tmpVal & 0xFFFF7FFF;
+	// BL_WR_WORD(0x30007044,tmpVal);
+    // uhs_phy_delay_us(200);
+	
+	// BL_WR_WORD(0x3000F030,0x18090610);
+
+	// #if PSRAM_32MB
+    // PSRAM_UHS_Cfg_Type psramCfg = {
+	// 	datarate,
+	// 	PSRAM_MEM_SIZE_32MB,
+	// 	PSRAM_PAGE_SIZE_2KB,
+	// 	0,
+    // };
+    // #else
+	// PSRAM_UHS_Cfg_Type psramCfg = {
+	// 	datarate,
+	// 	PSRAM_MEM_SIZE_64MB,
+	// 	PSRAM_PAGE_SIZE_2KB,
+	// 	0,
+    // };
+    // #endif
+	// Psram_UHS_Init_Override(cfg_glb); //controller init
+	
+    // set_or_uhs();
+	// set_uhs_phy();
+
+    // for( i = len ; i >= 0 ; i = i-4 ){
+    //     if( i != 0x4 ){
+    //         *((volatile uint32_t*)(addr_dump + i)) = val_sr[i>>2];
+    //     }
+    // }
+    // uhs_phy_delay_us(400);
+
+    if (ma_rb){
+        mr_read_back();
+    }else{
+        power_up_mm(1);
+        uhs_phy_pwr_down();
+        latency_wr_2kM[1] --;
+        uhs_phy_init_core(cfg_glb);
+    }
+
+    uhs_phy_printf("OUT_UHS_RESET\r\n");
+}
+
+void set_uhs_latency_r(uint32_t uhs_latency)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_ANA,uhs_latency%4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_RL_DIG,uhs_latency/4);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    uhs_phy_delay_us(50);
+}
+
+void set_uhs_latency_w(uint32_t uhs_latency)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_ANA,uhs_latency%4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DIG,uhs_latency/4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_ANA,(uhs_latency+1)%4);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_PHY_WL_DQ_DIG,(uhs_latency+1)/4);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    uhs_phy_delay_us(50);
+}
+
+uint8_t mr_read_back(void)
+{
+    uint8_t cnt1;
+    uint32_t tmpVal;
+    for (cnt1=0;cnt1<=4;cnt1++){
+        if(cnt1 != 3){
+            CHECK_ERR_FLAG(uhs_reg_r,(cnt1,0));
+            tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+            uhs_phy_printf("MA%d = 0x%lx\r\n",cnt1,tmpVal);
+        }
+    }
+    return 0;
+}
+
+uint8_t reg_read_cal(void)
+{
+    uint32_t tmpVal = 0;
+    uint32_t tmpVal_1 = 1;
+    uint32_t uhs_latency = 42;
+    int32_t i = 0;
+    uint8_t dqs_dq_flag = 0;
+    uint32_t reg_dqs = 0;
+    uint32_t reg_dq = 0;
+
+    // for(uhs_latency = 41; uhs_latency > 0; uhs_latency --)
+    for(uhs_latency = latency_wr_2kM[1]; uhs_latency > 0; uhs_latency --)
+    {
+        if(uhs_latency == 34)
+        {
+            reg_read_err = 1;
+            return uhs_err_handler(UHS_REG_READ_CAL_ERR);
+        }
+        uhs_phy_printf_debug("reg read cal 1st by latency= %ld\r\n",uhs_latency);
+        set_uhs_latency_r(uhs_latency);
+    
+        // sweep dqs
+        cfg_dq_rx(0);
+        for(i = 15; i >= 0; i --)
+        {
+            cfg_dqs_rx(i);
+            // tmpVal_1 = uhs_reg_r(0,1);
+            CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+            if (cal_done_flag == 1)
+                return 0;
+            tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+            uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 1st dqs--, 0x%lx\r\n",tmpVal);
+            if(tmpVal == ((2<<3)+uhs_latency_code) && (tmpVal_1 == 1)){
+                uhs_phy_printf_debug("reg read pass by dqs= %ld\r\n",i); 
+                // reg_dqs = i;
+                dqs_dq_flag = 1;
+                break;
+            }              
+            else{
+                uhs_phy_printf_debug("reg read fail by dqs= %ld\r\n",i);
+            }
+			// if(tmpVal_1 == 0){
+			// 	uhs_phy_printf_debug("read done not found!!!\r\n");
+			// 	// uhs_reset(datarate);
+			// 	set_uhs_latency_r(uhs_latency);
+			// 	cfg_dq_rx(0);
+			// }
+        }
+
+        // sweep dq 
+        cfg_dqs_rx(0);
+        for(i = 15; i >=0; i --)
+        {
+            cfg_dq_rx(i);
+            // tmpVal_1 = uhs_reg_r(0,1);
+            CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+            if (cal_done_flag == 1)
+                return 0;
+            tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+            uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 1st dq--, 0x%lx\r\n",tmpVal);
+            if(tmpVal == ((2<<3)+uhs_latency_code) && (tmpVal_1 == 1)){
+                uhs_phy_printf_debug("reg read pass by dq= %ld\r\n",i);
+                // reg_dq = i;
+                dqs_dq_flag = 1;
+                break; 
+            }  
+            else{
+                uhs_phy_printf_debug("reg read fail by dq= %ld\r\n",i);
+            }
+			// if(tmpVal_1 == 0){
+			// 	uhs_phy_printf_debug("read done not found!!!\r\n");
+			// 	// uhs_reset(datarate);
+			// 	set_uhs_latency_r(uhs_latency);
+			// 	cfg_dqs_rx(0);
+			// }
+        }    
+        if (dqs_dq_flag == 1){
+            dqs_dq_flag = 0;
+
+            uhs_latency = uhs_latency - 2;
+            uhs_phy_printf_debug("reg read cal 2nd by latency= %ld\r\n",uhs_latency);
+            set_uhs_latency_r(uhs_latency);  //got a good robust uhs_latency
+            latency_wr[1] = uhs_latency;
+            //******verify the uhs_latency and get dqs/dq timing
+            //sweep dqs
+            cfg_dq_rx(0);
+            for(i = 15; i >= 0; i --)
+            {
+                cfg_dqs_rx(i);
+                CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+                tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+                uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dqs--, 0x%lx\r\n",tmpVal);
+                if(tmpVal == ((2<<3)+uhs_latency_code))
+                {
+                    uhs_phy_printf("reg read pass by --dqs= %ld\r\n",i);
+                    reg_dqs += i;
+                    dqs_dq_flag = 1;
+                    break;
+                }
+                else{
+                    uhs_phy_printf_debug("reg read fail by dqs= %ld\r\n",i);
+                }
+            }
+            for(i = 0; i <= 15; i ++)
+            {
+                cfg_dqs_rx(i);
+                CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+                tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+                uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dqs++, 0x%lx\r\n",tmpVal);
+                if(tmpVal == ((2<<3)+uhs_latency_code))
+                {
+                    uhs_phy_printf("reg read pass by ++dqs= %ld\r\n",i);
+                    reg_dqs += i;
+                    dqs_dq_flag = 1;
+                    break; 
+                }
+                else{
+                    uhs_phy_printf_debug("reg read fail by dqs= %ld\r\n",i);
+                }
+            }
+            // sweep dq 
+            cfg_dqs_rx(0);
+            for(i = 15; i >= 0; i --)
+            {
+                cfg_dq_rx(i);
+                CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+                tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+                uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dq--, 0x%lx\r\n",tmpVal);
+                if(tmpVal == ((2<<3)+uhs_latency_code))
+                {
+                    uhs_phy_printf("reg read pass by --dq= %ld\r\n",i);
+                    reg_dq += i;
+                    dqs_dq_flag = 1;
+                    break;
+                }
+                else{
+                    uhs_phy_printf_debug("reg read fail by dq= %ld\r\n",i);
+                }
+            }
+            for(i = 0; i <= 15; i ++)
+            {
+                cfg_dq_rx(i);
+                CHECK_ERR_FLAG(uhs_reg_r,(0,0));
+                tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+                uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 2nd dq++, 0x%lx\r\n",tmpVal);
+                if(tmpVal == ((2<<3)+uhs_latency_code))
+                {
+                    uhs_phy_printf("reg read pass by ++dq= %ld\r\n",i);
+                    reg_dq += i;
+                    dqs_dq_flag = 1;
+                    break;
+                }  
+                else{
+                    uhs_phy_printf_debug("reg read fail by dq= %ld\r\n",i);
+                }
+            }
+            
+            if(dqs_dq_flag == 0)
+            {
+                reg_read_err = 2;
+                return uhs_err_handler(UHS_REG_READ_CAL_ERR);
+            }
+
+            if(reg_dqs >= reg_dq)
+            {
+                reg_dqs = (reg_dqs-reg_dq)/2;
+                reg_dq = 0;
+            }
+            else
+            {
+                reg_dq = (reg_dq-reg_dqs)/2;
+                reg_dqs = 0;
+            }
+            
+            // set dqs & dq by register read calibration result 
+            cfg_dqs_rx(reg_dqs);
+            cfg_dq_rx(reg_dq);
+            CHECK_ERR_FLAG(mr_read_back,());
+            uhs_phy_printf("reg_read_cal pass, latency= %ld, dqs= %ld, dq= %ld\r\n",uhs_latency,reg_dqs,reg_dq);
+            break;
+        }
+    }
+
+    return 0;
+}
+
+void cfg_dq_drv(uint32_t dq){
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM0_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DM1_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_04,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ15_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ14_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_24,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ13_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ12_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_20,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ11_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ10_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_1C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ9_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ8_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_18,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ7_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ6_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_14,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ5_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ4_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_10,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ3_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ2_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_0C,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ1_DLY_DRV,dq);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV,dq);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08,tmpVal);
+    // uhs_phy_delay_us(10);
+}
+
+void cfg_dqs_drv(uint32_t dqs){
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS0_DLY_DRV,dqs);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_28,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQS1_DLY_DRV,dqs);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_2C,tmpVal);
+    uhs_phy_delay_us(10);
+}
+
+uint8_t reg_write_cal(void)  //only need sweep dqs
+{
+    uint32_t tmpVal = 0;
+    // uint32_t tmpVal_1 = 0;
+    int32_t i = 0;
+    uint32_t reg_dqs;
+    uint32_t reg_dq = 0;
+    uint32_t reg_dqs1 = 0;
+    uint32_t reg_dqs2 = 0;
+    uint8_t dqs_dq_flag1 = 0;
+    uint8_t dqs_dq_flag2 = 0;
+    // reg_write_err = 0;
+
+    // sweep1 dqs
+    for(i = 15; i >=0; i --)
+    {
+        cfg_dqs_drv(i); 
+        CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,1)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==1
+        CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+        if(tmpVal == (16 + 32))
+            {
+                uhs_phy_printf("reg write pass by -- dqs1= %ld\r\n",i); 
+                reg_dqs1 = i;
+                dqs_dq_flag1 = 1;
+                break; 
+            }              
+        else{
+            uhs_phy_printf_debug("reg write fail by -- dqs1= %ld\r\n",i);
+        }
+    }        
+    // sweep2 dqs 
+    for(i = 0; i <=15; i ++)
+    {
+        cfg_dqs_drv(i);
+        CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,2));  //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==0,BL_64==1
+        CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+        if(tmpVal == (8 + 16))
+            {
+                uhs_phy_printf("reg write pass by ++ dqs2= %ld\r\n",i);
+                reg_dqs2 = i;
+                dqs_dq_flag2 = 1;
+                break; 
+            }              
+        else{
+            uhs_phy_printf_debug("reg write fail by ++ dqs2= %ld\r\n",i);
+        }
+    }           
+
+    if(dqs_dq_flag1 == 1 && dqs_dq_flag2 == 1){
+        reg_dqs = (reg_dqs1 + reg_dqs2) / 2 ;
+    }else if(dqs_dq_flag1 == 1 && dqs_dq_flag2 == 0){
+        reg_dqs = reg_dqs1;
+    }else if(dqs_dq_flag1 == 0 && dqs_dq_flag2 == 1){
+        reg_dqs = reg_dqs2;
+    }
+    else{
+        reg_write_err = 1;
+        return uhs_err_handler(UHS_REG_WRITE_CAL_ERR);
+    }
+
+    // if ck_dly_drv = 4, fix reg_dqs to 0
+	tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+	tmpVal = (tmpVal >> 16) & 0xF;
+	if(tmpVal == 4){
+		reg_dqs = 0;
+	}
+    // set dqs by register write cal result 
+    cfg_dqs_drv(reg_dqs);
+    CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,2,0)); //uhs_latency_code==3,uhs_drive==2,ma==2,BL_32==1
+    CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+    if(tmpVal == 0){   
+        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+        reg_dq = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV);
+        uhs_phy_printf("reg write cal pass dqs= %ld, dq= %ld\r\n",reg_dqs,reg_dq);
+    }              
+    else{
+        reg_write_err = 2;
+        return uhs_err_handler(UHS_REG_WRITE_CAL_ERR);
+    } 
+    
+    dqs_dq_delta = 16 + reg_dqs - reg_dq;
+    uhs_phy_printf("reg_write_cal return dqs_dq_delta= %ld\r\n",dqs_dq_delta);
+
+    return 0;
+}
+
+void array_write_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1)
+{
+    uint32_t addr_tmp = addr;
+    uint32_t data = data0;
+    uint32_t i = 0;
+
+    if (print_flag){
+        uhs_phy_printf("IN_ARRAY_WRITE_FIX\r\n");
+    }
+    for(i = 0; i < (len>>2); i ++)
+    {
+        addr_tmp = (i << 2) + addr;
+        if((i % 2) == 0)
+            data = data0 + i;
+        else
+            data = data1 + i;
+
+        BL_WR_WORD(addr_tmp,data); 
+    }
+    if (print_flag){
+        uhs_phy_printf("BEFORE CACHE FUCNTION\r\n");
+    }
+    if (cache_state){
+        // #if CACHE_EN
+        __DSB();
+        __ISB();
+        L1C_DCache_Clean_Invalid_All();
+        __DSB();
+        __ISB();
+        // #endif
+    }
+    uhs_phy_delay_us(10);
+    if (print_flag){
+        uhs_phy_printf("OUT_ARRAY_WRITE_FIX\r\n");
+    }
+}
+
+uint8_t array_read_fix(uint32_t addr,uint32_t len,uint32_t data0,uint32_t data1)
+{
+    uint8_t array_read_pass = 1;
+    uint32_t addr_tmp = addr;
+    uint32_t data = data0;
+    uint32_t data_read = 0;
+    uint32_t i = 0;
+
+    if (print_flag){
+        uhs_phy_printf("IN_ARRAY_READ_FIX\r\n");
+    }
+    for(i = 0; i < (len>>2); i ++)
+    {
+        // data_read = 0;
+        // data_read += *((volatile uint8_t *)(addr+(i<<2)+3));
+        // data_read <<= 8;
+        // data_read += *((volatile uint8_t *)(addr+(i<<2)+2));
+        // data_read <<= 8;
+        // data_read += *((volatile uint8_t *)(addr+(i<<2)+1));
+        // data_read <<= 8;
+        // data_read += *((volatile uint8_t *)(addr+(i<<2)+0));
+
+        addr_tmp = (i << 2) + addr;
+        data_read = BL_RD_WORD(addr_tmp);
+        if((i % 2) == 0)
+            data = data0 + i;
+        else
+            data = data1 + i;
+
+        if (print_flag && i == 0){
+            uhs_phy_printf("addr 0x%lx, write_val 0x%lx, read_val 0x%lx\r\n",addr_tmp,data,data_read);
+        }
+        if(data_read != data){
+            array_read_pass = 0;
+            uhs_phy_printf("addr 0x%lx, write_val 0x%lx, read_val error 0x%lx\r\n",addr_tmp,data,data_read);
+            break;
+        }
+    }
+    if (print_flag){
+        uhs_phy_printf("BEFORE CACHE FUCNTION\r\n");
+    }
+    if (cache_state){
+        // #if CACHE_EN
+        __DSB();
+        __ISB();
+        L1C_DCache_Clean_Invalid_All();
+        __DSB();
+        __ISB();
+        // #endif
+    }
+    uhs_phy_delay_us(10);
+    if (print_flag){
+        uhs_phy_printf("OUT_ARRAY_READ_FIX\r\n");
+    }
+    return array_read_pass;
+}
+
+void set_ck_dly_drv(uint32_t array_ck_dly_drv)
+{
+    uint32_t array_dqx_dly_drv = 0;
+    uint32_t array_dqsx_dly_drv = 0;
+    uint32_t array_cen_dly_drv = 0;
+
+    uhs_phy_delay_us(10);  // ck modify need time
+
+    array_dqx_dly_drv = (array_ck_dly_drv >=4) ? (array_ck_dly_drv-4) : 0;
+    array_cen_dly_drv = array_dqx_dly_drv + 1;
+    array_dqx_dly_drv = (array_dqx_dly_drv > 15) ? 15 : array_dqx_dly_drv;
+    array_cen_dly_drv = (array_cen_dly_drv > 15) ? 15 : array_cen_dly_drv;
+    array_dqsx_dly_drv = (array_dqsx_dly_drv > 15) ? 15 : array_dqsx_dly_drv;
+
+    cfg_dq_drv(array_dqx_dly_drv);
+    // cfg_dqs_drv(array_dqsx_dly_drv);
+    cfg_ck_cen_drv(array_ck_dly_drv,array_cen_dly_drv);
+    // uhs_phy_printf_debug("array_dqx_dly_drv= %ld,array_dqsx_dly_drv= %ld,array_ck_dly_drv= %ld,array_cen_dly_drv= %ld\r\n",array_dqx_dly_drv,array_dqsx_dly_drv,array_ck_dly_drv,array_cen_dly_drv); //debug
+    // uhs_phy_delay_us(50); // ck modify need time
+}
+
+uint8_t array_read_latency_cal(void)
+{
+    // uint32_t tmpVal = 0;
+    uint32_t uhs_latency = 42;
+    // uint8_t array_ck_dly_drv_val[3] = {15,4,9};
+    uint8_t array_ck_dly_drv_val[3] = {4,9,15};
+    uint8_t ck_i;
+    uint32_t array_ck_dly_drv = 0;
+    int32_t i = 0;
+    uint32_t array_dqs = 0;
+    uint32_t array_dq = 0;
+    uint32_t dqs_flag;
+    uint32_t dq_flag;
+    uint32_t len = 128;
+    uint8_t rwindow = 0;
+
+    for(uhs_latency = latency_wr[1]; uhs_latency > 0; uhs_latency --)
+    {
+        if(uhs_latency == 34)
+        {
+            array_read_err = 1;
+            return uhs_err_handler(UHS_ARRAY_READ_LAT_ERR);
+        }
+
+        uhs_phy_printf_debug("array read cal by latency= %ld\r\n",uhs_latency);
+        set_uhs_latency_r(uhs_latency);
+
+        for (ck_i = 0; ck_i < (sizeof(array_ck_dly_drv_val)/sizeof(array_ck_dly_drv_val[0])); ck_i++){
+            array_ck_dly_drv = array_ck_dly_drv_val[ck_i];
+            set_ck_dly_drv(array_ck_dly_drv);
+            uhs_phy_printf_debug("array read cal by ck= %ld\r\n",array_ck_dly_drv);
+
+            rwindow = 0;
+
+            // sweep dqs
+            cfg_dq_rx(0);
+            for(i = 15; i >= 0; i --)
+            {
+                cfg_dqs_rx(i);
+                dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+                if(dqs_flag == 1)
+                {
+                    uhs_phy_printf("array_read_dqs_dq_cal pass by --dqs= %ld\r\n",i); 
+                    array_dqs += i;
+                    rwindow += i;
+                    uhs_phy_cal_res->rwindow_end = i;
+                    break; 
+                }
+            }
+            for(i = 0; i <= 15; i ++)
+            {
+                cfg_dqs_rx(i);
+                dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+                if(dqs_flag == 1)
+                {
+                    uhs_phy_printf("array_read_dqs_dq_cal pass by ++dqs= %ld\r\n",i); 
+                    array_dqs += i;
+                    rwindow = (i > 0) ? (rwindow - i) : (rwindow + 1);
+                    uhs_phy_cal_res->rwindow_begin = i;
+                    break; 
+                }
+            }
+            // sweep dq
+            cfg_dqs_rx(0);
+            for(i = 15; i >= 0; i --)
+            {
+                cfg_dq_rx(i);
+                dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+                if(dq_flag == 1)
+                {
+                    uhs_phy_printf("array_read_dqs_dq_cal pass by --dq= %ld\r\n",i);  
+                    array_dq += i;
+                    rwindow += i;
+                    break; 
+                }                  
+            }
+            for(i = 0; i <= 15; i ++)
+            {
+                cfg_dq_rx(i);
+                dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+                if(dq_flag == 1)
+                {
+                    uhs_phy_printf("array_read_dqs_dq_cal pass by ++dq= %ld\r\n",i);  
+                    array_dq += i;
+                    rwindow -= i;
+                    break; 
+                }                  
+            }
+
+            if(dqs_flag == 1 || dq_flag == 1){
+                if(array_dqs >= array_dq)
+                {
+                    array_dqs = (array_dqs-array_dq)/2;
+                    array_dq = 0;
+                }
+                else
+                {
+                    #if CAL_MODE == 2
+                    array_read_err = 2;
+                    return uhs_err_handler(UHS_ARRAY_READ_LAT_ERR);
+                    #endif
+                    array_dq = (array_dq-array_dqs)/2;
+                    array_dqs = 0;
+                }
+                cfg_dq_rx(array_dq);
+                cfg_dqs_rx(array_dqs);
+                uhs_phy_printf("array_read_dqs_dq_cal valid code number= %d\r\n",rwindow);
+                uhs_phy_cal_res->rwindow = rwindow;
+                uhs_phy_cal_res->rdqs = array_dqs;
+                uhs_phy_cal_res->rdq = array_dq;
+                uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs= %ld, array_dq= %ld\r\n",array_dqs,array_dq);
+                break;
+            }
+        }
+        if(dqs_flag == 1 || dq_flag == 1){
+            uhs_phy_cal_res->rl = uhs_latency;
+            uhs_phy_printf("array_read_latency_cal pass, latency= %ld, ck= %ld\r\n",uhs_latency,array_ck_dly_drv);
+            break;
+        }
+    }
+
+    return 0;
+}
+
+uint8_t array_write_ck_cal(void)
+{
+    uint32_t array_ck_dly_drv = 0;
+    uint32_t array_ck_dly_drv1 = 15;
+    uint32_t array_ck_dly_drv2 = 4;
+    uint32_t flag_1 = 0;
+    uint32_t flag_2 = 0;
+    uint32_t len = 1024<<4;
+
+    for(array_ck_dly_drv = 4; array_ck_dly_drv <= 15; array_ck_dly_drv ++)
+    {
+        set_ck_dly_drv(array_ck_dly_drv);
+        flag_2 = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+        if (flag_2 == 0){
+            uhs_phy_printf("array_write_ck_cal ck++ = %ld, flag_2 = %ld\r\n",array_ck_dly_drv,flag_2);
+        }
+        if(flag_2 == 0 && flag_ck2 == 0){
+            flag_ck2 = 1;
+            uhs_phy_printf("array_write_ck_cal fail by ++ck= %ld\r\n",array_ck_dly_drv);
+            array_ck_dly_drv2 = array_ck_dly_drv;
+            // break;
+        }
+    }
+    if (flag_ck2 == 1)
+        flag_2 = 0;
+    for(array_ck_dly_drv = 15; array_ck_dly_drv >= 4; array_ck_dly_drv --)
+    {
+        set_ck_dly_drv(array_ck_dly_drv);
+        flag_1 = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+        if (flag_1 == 0){
+            uhs_phy_printf("array_write_ck_cal ck-- = %ld, flag_1 = %ld\r\n",array_ck_dly_drv,flag_1);
+        }
+        if(flag_1 == 0 && flag_ck1 == 0){
+            flag_ck1 = 1;
+            uhs_phy_printf("array_write_ck_cal fail by --ck= %ld\r\n",array_ck_dly_drv);
+            array_ck_dly_drv1 = array_ck_dly_drv;
+            // break;
+        }
+    }
+    if (flag_ck1 == 1)
+        flag_1 = 0;
+
+    if (flag_1 == 0 && flag_2 == 0){
+        if(array_ck_dly_drv1 == 15 && array_ck_dly_drv2 == 4)
+        {
+            return uhs_err_handler(UHS_ARRAY_WRITE_CK_ERR);
+        }
+        else if ((15 - array_ck_dly_drv1) >= (array_ck_dly_drv2 - 4)){
+            array_ck_dly_drv = 15;
+        }
+        else{
+            array_ck_dly_drv = 4;
+        }
+    }
+    else if (flag_1 == 0 && flag_2 == 1){
+        array_ck_dly_drv = (array_ck_dly_drv1 > 9) ? 4 : 15;
+    }else if (flag_1 == 1 && flag_2 == 0){
+        array_ck_dly_drv = (array_ck_dly_drv2 > 9) ? 4 : 15;
+    }
+    else {
+        array_ck_dly_drv = (15 + 4) / 2;         
+    }
+
+    set_ck_dly_drv(array_ck_dly_drv);
+    uhs_phy_cal_res->ck = array_ck_dly_drv;
+    uhs_phy_printf("array_write_ck_cal pass, ck= %ld\r\n",array_ck_dly_drv);
+
+    return 0;
+}
+
+uint8_t array_read_dqs_dq_cal(void)
+{
+    int32_t i = 0;
+    uint32_t array_dqs = 0;
+    uint32_t array_dq = 0;
+    uint32_t dqs_flag;
+    uint32_t dq_flag;
+    uint32_t len = 128;
+
+    // sweep dqs
+    cfg_dq_rx(0);
+
+    for(i = 15; i >= 0; i --)
+    {
+        cfg_dqs_rx(i);
+        dqs_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+        if(dqs_flag == 1)
+        {
+            uhs_phy_printf("array_read_dqs_dq_cal pass by dqs= %ld\r\n",i); 
+            array_dqs = i;
+            break; 
+        }
+    }
+    // sweep dq 
+    cfg_dqs_rx(0);
+    for(i = 15; i >=0; i --)
+    {
+        cfg_dq_rx(i);
+        dq_flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+        if(dq_flag == 1)
+        {
+            uhs_phy_printf("array_read_dqs_dq_cal pass by dq= %ld\r\n",i);  
+            array_dq = i;
+            break; 
+        }                  
+    }
+    if(dqs_flag == 0 && dq_flag == 0)
+    {
+        return uhs_err_handler(UHS_ARRAY_READ_CAL_ERR);
+    }
+    if(array_dqs > array_dq)
+    {
+        array_dqs = (array_dqs-array_dq)/2;
+        array_dq = 0;
+    }
+    else
+    {
+        array_dq = (array_dq-array_dqs)/2;
+        array_dqs = 0;
+    }
+    cfg_dq_rx(array_dq);
+    cfg_dqs_rx(array_dqs);
+    uhs_phy_printf("array_read_dqs_dq_cal pass by array_dqs= %ld, array_dq= %ld\r\n",array_dqs,array_dq);
+
+    return 0;
+}
+
+uint8_t array_write_dqs_dq_cal(void)
+{
+    uint32_t tmpVal = 0;
+    int32_t i = 0;
+    uint32_t dqs_flag1 = 0;
+    uint32_t dqs_flag2 = 0;
+    uint32_t array_dqs_dly_drv = 0;
+    uint32_t array_dqs_dly_drv1 = 0;
+    uint32_t array_dqs_dly_drv2 = 0;
+
+    uint32_t addr = 0x50000000;
+    uint32_t len = 128;
+    uint32_t data0 = 0x23456789;
+    uint32_t data1 = 0x98765432;
+
+    uint8_t wwindow = 0;
+
+    for(i = 15; i >= 0; i --)
+    {  
+        cfg_dqs_drv(i);  
+        array_write_fix(addr,len,data0,data1);
+        dqs_flag1 = array_read_fix(addr,len,data0,data1);
+        if(dqs_flag1 == 1)
+        {
+            uhs_phy_printf("array_write_dqs_dq_cal pass by -- dqs1= %ld\r\n",i);
+            array_dqs_dly_drv1 = i;
+            uhs_phy_cal_res->wwindow_end = i;
+            break;  
+        }              
+        else
+        {
+            uhs_phy_printf_debug("array_write_dqs_dq_cal fail by -- dqs1= %ld\r\n",i);
+        }
+    }
+    for(i = 0; i <= 15; i ++)
+    {
+        cfg_dqs_drv(i);
+        array_write_fix(addr,len,data1,data0);
+        dqs_flag2 = array_read_fix(addr,len,data1,data0);
+        if(dqs_flag2 == 1)
+        {
+            uhs_phy_printf("array_write_dqs_dq_cal pass by ++ dqs2= %ld\r\n",i);
+            array_dqs_dly_drv2 = i;
+            uhs_phy_cal_res->wwindow_begin = i;
+            break;
+        }              
+        else
+        {
+            uhs_phy_printf_debug("array_write_dqs_dq_cal fail by ++ dqs2= %ld\r\n",i);
+        }
+    }
+    
+    if(dqs_flag1 == 1 && dqs_flag2 == 1)
+    {
+        array_dqs_dly_drv = (array_dqs_dly_drv1 + array_dqs_dly_drv2) / 2 ;
+    }
+    else if(dqs_flag1 == 1 && dqs_flag2 == 0){
+        array_dqs_dly_drv = array_dqs_dly_drv1;
+    }else if(dqs_flag1 == 0 && dqs_flag2 == 1){
+        array_dqs_dly_drv = array_dqs_dly_drv2;
+    }else{
+        return uhs_err_handler(UHS_ARRAY_WRITE_CAL_ERR);
+    }
+
+    //debug
+    // array_dqs_dly_drv = 4;
+
+    // if ck_dly_drv = 4, fix dqsx_dly_drv to 0
+	tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_00);
+	tmpVal = (tmpVal >> 16) & 0xF;
+	if(tmpVal == 4){
+		array_dqs_dly_drv = 0;
+        uhs_phy_cal_res->wwindow_begin = 0;
+	}
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_08);
+    tmpVal = BL_GET_REG_BITS_VAL(tmpVal,PSRAM_UHS_DQ0_DLY_DRV);
+
+    wwindow = (array_dqs_dly_drv > 0) ? (array_dqs_dly_drv1 - array_dqs_dly_drv2 + 1) : (array_dqs_dly_drv1 - 0 + 1);
+    uhs_phy_printf("array_write_dqs_dq_cal valid code number= %d\r\n",wwindow);
+    uhs_phy_cal_res->wwindow = wwindow;
+    uhs_phy_cal_res->wdqs = array_dqs_dly_drv;
+    uhs_phy_cal_res->wdq = tmpVal;
+    uhs_phy_printf("array_write_dqs_dq_cal pass by array_dqs_dly_drv= %ld,array_dq_dly_drv= %ld\r\n",array_dqs_dly_drv,tmpVal);
+    // set dqs by register write cal result 
+    cfg_dqs_drv(array_dqs_dly_drv);
+
+    return 0;
+}
+
+BL_Err_Type ATTR_CLOCK_SECTION GLB_Config_UHS_PLL_Freq(GLB_XTAL_Type xtalType, uint32_t pllFreq)
+{
+    uint32_t xtalFreq = 0;
+    uint32_t factor = 0;
+    GLB_MU_PLL_CFG_BASIC_Type uhsPllMCfg = {
+        .clkpllRefdivRatio = 1,         /*!< pll_refdiv_ratio */
+        .clkpllSelSampleClk = 2,        /*!< pll_sel_sample_clk */
+        .clkpllVcoSpeed = 7,            /*!< pll_vco_speed */
+        .clkpllEvenDivEn = 1,           /*!< pll_even_div_en */
+        .clkpllEvenDivRatio = 2100/50,  /*!< pll_even_div_ratio */
+    };
+    GLB_MU_PLL_Cfg_Type uhsPllCfg[GLB_XTAL_MAX] = {
+        { NULL, 0x0 },          /*!< XTAL is None */
+        { &uhsPllMCfg, 0x0 },   /*!< XTAL is 24M */
+        { &uhsPllMCfg, 0x0 },   /*!< XTAL is 32M */
+        { &uhsPllMCfg, 0x0 },   /*!< XTAL is 38.4M */
+        { &uhsPllMCfg, 0x0 },   /*!< XTAL is 40M */
+        { &uhsPllMCfg, 0x0 },   /*!< XTAL is 26M */
+        { &uhsPllMCfg, 0x0 },   /*!< XTAL is RC32M */
+    };
+    GLB_PLL_REF_CLK_Type refClk;
+
+    /* calc clkpllRefdivRatio */
+    switch(xtalType){
+        case GLB_XTAL_NONE:
+            return ERROR;
+        case GLB_XTAL_24M:
+            xtalFreq = 240;
+            uhsPllMCfg.clkpllRefdivRatio = 1;
+            break;
+        case GLB_XTAL_32M:
+            xtalFreq = 320;
+            uhsPllMCfg.clkpllRefdivRatio = 2;
+            break;
+        case GLB_XTAL_38P4M:
+            xtalFreq = 384;
+            uhsPllMCfg.clkpllRefdivRatio = 2;
+            break;
+        case GLB_XTAL_40M:
+            xtalFreq = 400;
+            uhsPllMCfg.clkpllRefdivRatio = 2;
+            break;
+        case GLB_XTAL_26M:
+            xtalFreq = 260;
+            uhsPllMCfg.clkpllRefdivRatio = 1;
+            break;
+        case GLB_XTAL_RC32M:
+            xtalFreq = 320;
+            uhsPllMCfg.clkpllRefdivRatio = 2;
+            break;
+        default :
+            break;
+    }
+    /* calc clkpllSelSampleClk */
+    factor = pllFreq*20480/(xtalFreq/uhsPllMCfg.clkpllRefdivRatio);
+    if(factor<32*2048){
+        uhsPllMCfg.clkpllSelSampleClk = 0;
+    }else if(factor<64*2048){
+        uhsPllMCfg.clkpllSelSampleClk = 1;
+    }else if(factor<128*2048){
+        uhsPllMCfg.clkpllSelSampleClk = 2;
+    }else{
+        uhsPllMCfg.clkpllSelSampleClk = 2;
+    }
+    /* calc clkpllVcoSpeed */
+    if(pllFreq<800){
+        uhsPllMCfg.clkpllVcoSpeed = 1;
+    }else if(pllFreq<1000){
+        uhsPllMCfg.clkpllVcoSpeed = 2;
+    }else if(pllFreq<1200){
+        uhsPllMCfg.clkpllVcoSpeed = 3;
+    }else if(pllFreq<1500){
+        uhsPllMCfg.clkpllVcoSpeed = 4;
+    }else if(pllFreq<1700){
+        uhsPllMCfg.clkpllVcoSpeed = 5;
+    }else if(pllFreq<1900){
+        uhsPllMCfg.clkpllVcoSpeed = 6;
+    }else if(pllFreq<2200){
+        uhsPllMCfg.clkpllVcoSpeed = 7;
+    }else{
+        uhsPllMCfg.clkpllVcoSpeed = 8;
+    }
+    /* calc clkpllEvenDivRatio */
+    uhsPllMCfg.clkpllEvenDivRatio = pllFreq/50;
+    /* calc clkpllSdmin */
+    uhsPllCfg[GLB_XTAL_24M].clkpllSdmin = factor;
+    uhsPllCfg[GLB_XTAL_32M].clkpllSdmin = factor;
+    uhsPllCfg[GLB_XTAL_38P4M].clkpllSdmin = factor;
+    uhsPllCfg[GLB_XTAL_40M].clkpllSdmin = factor;
+    uhsPllCfg[GLB_XTAL_26M].clkpllSdmin = factor;
+    uhsPllCfg[GLB_XTAL_RC32M].clkpllSdmin = factor;
+    
+    if (xtalType == GLB_XTAL_RC32M) {
+        refClk = GLB_PLL_REFCLK_RC32M;
+    } else {
+        refClk = GLB_PLL_REFCLK_XTAL;
+    }
+    
+    // GLB_Power_Off_MU_PLL(GLB_MU_PLL_UHSPLL);
+    GLB_MU_PLL_Ref_Clk_Sel(GLB_MU_PLL_UHSPLL, refClk);
+    GLB_Power_On_MU_PLL(GLB_MU_PLL_UHSPLL, &(uhsPllCfg[xtalType]), 1);
+    
+    return SUCCESS;
+}
+
+uint8_t init_reg_write(void){
+    uint32_t tmpVal = 0;
+    uint8_t wl_i;
+    uint32_t wl;
+    uint32_t wdqs;
+    // uint8_t wdq_val[3] = {0,11,5};
+    uint8_t wdq_val[3] = {0,5,11};
+    uint8_t wdq_i;
+    uint32_t wdq;
+    uint32_t rl;
+    uint32_t rdqs;
+    uint32_t rdq;
+    uint8_t rl_i;
+    uint8_t wl_val_32[6] = {1,0,2,3,4,5};
+    uint8_t rl_val_32[5] = {36,37,38,39,40};
+    uint8_t wl_val_64[6] = {9,8,10,7,11,6};
+    uint8_t rl_val_64[5] = {36,37,38,39,40};
+    uint8_t wl_val[6];
+    uint8_t rl_val[5];
+
+    if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+            wl_val[wl_i] = wl_val_32[wl_i];
+        }
+        for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){
+            rl_val[rl_i] = rl_val_32[rl_i];
+        }
+	}else if(cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+            wl_val[wl_i] = wl_val_64[wl_i];
+        }
+        for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){
+            rl_val[rl_i] = rl_val_64[rl_i];
+        }
+	}
+
+	// set to 2000Mbps
+    for (rl_i = 0; rl_i < (sizeof(rl_val)/sizeof(rl_val[0])); rl_i++){
+        rl = rl_val[rl_i];
+        set_uhs_latency_r(rl);
+        for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+            wl = wl_val[wl_i];
+            latency_wr[0] = wl;
+            set_uhs_latency_w(wl);
+            for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){
+                wdq = wdq_val[wdq_i];
+                cfg_dq_drv(wdq);
+                cfg_ck_cen_drv(wdq + 4,wdq + 1);
+                for (wdqs = 0; wdqs <= 15; wdqs++){
+                    cfg_dqs_drv(wdqs);
+                    set_uhs_phy_init();
+                    CHECK_ERR_FLAG(uhs_reg_w,(uhs_latency_code,2,0,0)); //uhs_latency_code==3,uhs_drive==2,ma==0,BL_32==0
+                    set_uhs_phy();
+                    rdq = 0;
+                    cfg_dq_rx(rdq);
+                    for (rdqs = 0; rdqs <= 15; rdqs++){
+                        cfg_dqs_rx(rdqs);
+                        CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+                        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+                        uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 = 0x%lx, rdqs++\r\n",tmpVal);
+                        if(tmpVal == ((2<<3)+uhs_latency_code)){
+                            uhs_phy_printf("LATENCY_CODE_WRITE_SUCCESS, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                            return 0;
+                        }
+                        else{
+                            uhs_phy_printf_debug("LATENCY_CODE_WRITE_FAIL, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                        }
+                    }
+                    rdqs = 0;
+                    cfg_dqs_rx(rdqs);
+                    for (rdq = 0; rdq <= 15; rdq++){
+                        cfg_dq_rx(rdq);
+                        CHECK_ERR_FLAG(uhs_reg_r,(0,1));
+                        tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+                        uhs_phy_printf_debug("PSRAM_UHS_UHS_CMD>>24 = 0x%lx, rdq++\r\n",tmpVal);
+                        if(tmpVal == ((2<<3)+uhs_latency_code)){
+                            uhs_phy_printf("LATENCY_CODE_WRITE_SUCCESS, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                            return 0;
+                        }
+                        else{
+                            uhs_phy_printf_debug("LATENCY_CODE_WRITE_FAIL, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                        }
+                    }
+                }
+            }
+        }
+    }
+    return uhs_err_handler(UHS_LATENCY_CODE_WRITE_ERR);
+}
+
+uint8_t init_array_write(void){
+    uint8_t wl_val[6] = {13,12,14,11,15,10};
+    uint8_t wl_i;
+    uint32_t wl;
+    uint32_t wdqs;
+    // uint8_t wdq_val[3] = {0,11,5};
+    uint8_t wdq_val[3] = {0,5,11};
+    uint8_t wdq_i;
+    uint32_t wdq;
+    uint32_t rl;
+    uint32_t rdqs;
+    uint32_t rdq;
+    uint32_t len = 1024<<4;
+    uint32_t flag = 0;
+    print_flag = 1;
+
+    for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+        wl = wl_val[wl_i];
+        latency_wr[0] = wl;
+        set_uhs_latency_w(wl);
+        for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){
+            wdq = wdq_val[wdq_i];
+            cfg_dq_drv(wdq);
+            cfg_ck_cen_drv(wdq + 4,wdq + 1);
+            for (wdqs = 0; wdqs <= 15; wdqs++){
+                cfg_dqs_drv(wdqs);
+                array_write_fix(addr_rarray,len,data0_rarray,data1_rarray);
+                for (rl = latency_wr[1]; rl >= 35; rl--){
+                    set_uhs_latency_r(rl);
+                    rdq = 0;
+                    cfg_dq_rx(rdq);
+                    for (rdqs = 0; rdqs <= 15; rdqs++){
+                        cfg_dqs_rx(rdqs);
+                        flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+                        if(flag == 1){
+                            uhs_phy_printf("INIT_ARRAY_WRITE_SUCCESS, rdqs++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                            print_flag = 0;
+                            #if CAL_MODE == 2
+                            if(wl != 13){
+                                init_array_write_err = 2;
+                                return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR);
+                            }
+                            #endif
+                            uhs_phy_cal_res->wl = wl;
+                            return 0;
+                        }    
+                        else{
+                            uhs_phy_printf_debug("INIT_ARRAY_WRITE_FAIL, rdqs++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                        }                    
+                    }
+                    rdqs = 0;
+                    cfg_dqs_rx(rdqs);
+                    for (rdq = 0; rdq <= 15; rdq++){
+                        cfg_dq_rx(rdq);
+                        flag = array_read_fix(addr_rarray,len,data0_rarray,data1_rarray);
+                        if(flag == 1){
+                            uhs_phy_printf("INIT_ARRAY_WRITE_SUCCESS, rdq++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                            print_flag = 0;
+                            #if CAL_MODE == 2
+                            if(wl != 13){
+                                init_array_write_err = 2;
+                                return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR);
+                            }
+                            #endif
+                            uhs_phy_cal_res->wl = wl;
+                            return 0;
+                        }    
+                        else{
+                            uhs_phy_printf_debug("INIT_ARRAY_WRITE_FAIL, rdq++, wl = %ld, wdqs = %ld, wdq = %ld, rl = %ld, rdqs = %ld, rdq = %ld\r\n",wl,wdqs,wdq,rl,rdqs,rdq);
+                        }                    
+                    }
+                }
+            }
+        }
+    }
+    init_array_write_err = 1;
+    return uhs_err_handler(UHS_INIT_ARRAY_WRITE_ERR);
+}
+
+void set_odt_en(void){
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_RSVD_REG);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MR2_2_0,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_RSVD_REG,tmpVal);
+
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_MODE_REG,0x2); //reg_mode_reg
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x1);  //reg_config_req
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+    uhs_phy_delay_us(10);
+
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_REGW_PULSE,0x1);  //reg_regw_pulse
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD,tmpVal);
+    uhs_phy_delay_us(10);
+
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_REG_CONFIG_REQ,0x0);  //reg_config_req
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_BASIC,tmpVal);
+
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL,0xf);  // odt_sel
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_30,tmpVal);
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_HW,0x1);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,PSRAM_UHS_ODT_SEL_DLY,0x3);
+    BL_WR_REG(PSRAM_UHS_BASE,PSRAM_UHS_PHY_CFG_4C,tmpVal);
+}
+
+uint8_t init_reg_write_2kM(void){
+    uint32_t tmpVal = 0;
+    uint8_t wl_val[6] = {13,12,14,11,15,10};
+    uint8_t wl_i;
+    uint32_t wl;
+    uint32_t wdqs;
+    // uint8_t wdq_val[3] = {0,11,5};
+    uint8_t wdq_val[3] = {0,5,11};
+    uint8_t wdq_i;
+    uint32_t wdq;
+
+	// set to 2000Mbps
+    for (wl_i = 0; wl_i < (sizeof(wl_val)/sizeof(wl_val[0])); wl_i++){
+        wl = wl_val[wl_i];
+        latency_wr[0] = wl;
+        set_uhs_latency_w(wl);
+        for (wdq_i = 0; wdq_i < (sizeof(wdq_val)/sizeof(wdq_val[0])); wdq_i++){
+            wdq = wdq_val[wdq_i];
+            cfg_dq_drv(wdq);
+            cfg_ck_cen_drv(wdq + 4,wdq + 1);
+            for (wdqs = 0; wdqs <= 15; wdqs++){
+                cfg_dqs_drv(wdqs);
+                set_odt_en();
+                CHECK_ERR_FLAG(uhs_reg_r,(2,0));
+                tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+                uhs_phy_printf_debug("MA2 = 0x%lx\r\n",tmpVal);
+                if(tmpVal == 3){
+                    uhs_phy_printf("2kM_REG_WRITE_SUCCESS, wl = %ld, wdqs = %ld, wdq = %ld\r\n",wl,wdqs,wdq);
+                    return 0;
+                }
+                else{
+                    uhs_phy_printf_debug("2kM_REG_WRITE_FAIL, wl = %ld, wdqs = %ld, wdq = %ld\r\n",wl,wdqs,wdq);
+                }
+            }
+        }
+    }
+    return uhs_err_handler(UHS_REG_WRITE_2kM_ERR);
+}
+
+uint8_t self_cal()
+{
+    uint32_t tmpVal = 0;
+    uint32_t datarate;
+    datarate = cfg_glb->pck_freq;
+
+    if (datarate >= 933*2){
+        uhs_latency_code = UHS_LATENCY_CODE_1066;
+    }else if(datarate >= 800*2){
+        uhs_latency_code = UHS_LATENCY_CODE_933;
+    }else if(datarate >= 533*2){
+        uhs_latency_code = UHS_LATENCY_CODE_800;
+    }else if(datarate >= 400*2){
+        uhs_latency_code = UHS_LATENCY_CODE_533;
+    }else if(datarate >= 333*2){
+        uhs_latency_code = UHS_LATENCY_CODE_400;
+    }else if(datarate >= 200*2){
+        uhs_latency_code = UHS_LATENCY_CODE_333;
+    }else{
+        uhs_latency_code = UHS_LATENCY_CODE_200;
+    }
+    // #if PSRAM_32MB
+	// PSRAM_UHS_Cfg_Type psramCfg = {
+    //     datarate,
+    //     PSRAM_MEM_SIZE_32MB,
+    //     PSRAM_PAGE_SIZE_2KB,
+    //     0,
+    // };
+	// #else
+    // PSRAM_UHS_Cfg_Type psramCfg = {
+    //     datarate,
+    //     PSRAM_MEM_SIZE_64MB,
+    //     PSRAM_PAGE_SIZE_2KB,
+    //     0,
+    // };
+    // #endif
+
+    uhs_phy_printf("********** INIT_REG_WRITE **********\r\n");
+    CHECK_ERR_FLAG(init_reg_write,()); //write latency code
+    // uhs_phy_printf("START_CAL_AT %ldMbps\r\n",datarate);
+    // datarate_glb = datarate;
+    // ramsize_glb = cfg->psramMemSize;
+    GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,datarate);
+    Psram_UHS_Init_Override(cfg_glb); //controller init
+    set_uhs_phy();
+
+    #if CAL_MODE == 0
+    return 0;
+    // then load efuse, to set uhs phy regs
+    // call set_odt_en(), to set psram odt MR if need
+    // call mr_read_back()
+    #endif
+
+    uhs_phy_printf("********** REG_READ_CAL **********\r\n");
+    // uhs_phy_reg_dump();
+    // ******register read latency & dqs & dq calibration
+    CHECK_ERR_FLAG(reg_read_cal,());
+    if (cal_done_flag == 1)
+        return 0;
+    // if (datarate >= 1800){
+    //     latency_wr[1] = 39;
+    // }else if(datarate >= 1600){
+    //     latency_wr[1] = 38;
+    // }else if(datarate >= 1100){
+    //     latency_wr[1] = 37;
+    // }else{
+    //     latency_wr[1] = 36;
+    // }
+
+    CHECK_ERR_FLAG(uhs_reg_r,(1,0));
+    tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+    if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        tmpVal &= 0x10;
+    }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        tmpVal &= 0x20;
+    }
+    if (tmpVal != 0){
+        return uhs_err_handler(UHS_BAD_DIE_ERR);
+    }
+
+    uhs_phy_printf("UHS_PHY_CAL, ODT_EN = %d\r\n",ODT_EN);
+    #if ODT_EN
+    uhs_phy_printf("********** INIT_REG_WRITE_2kM **********\r\n");
+    CHECK_ERR_FLAG(init_reg_write_2kM,());
+    #endif
+
+    uhs_phy_printf("********** INIT_ARRAY_WRITE **********\r\n");
+    #if bl808_DBG_RF == 2
+    uhs_phy_reg_dump();
+    #endif
+    // reg_write_cal();
+    CHECK_ERR_FLAG(init_array_write,());
+    uhs_phy_printf("********** ARRAY_READ_CAL **********\r\n");
+    // uhs_phy_reg_dump();
+    // ******array read latency & dqs & dq calibration
+    CHECK_ERR_FLAG(array_read_latency_cal,());
+    uhs_phy_printf("********** ARRAY_WRITE_CK_CAL **********\r\n");
+    // uhs_phy_reg_dump();
+    flag_ck1 = 0;
+    flag_ck2 = 0;
+    CHECK_ERR_FLAG(array_write_ck_cal,());
+    uhs_phy_printf("********** ARRAY_WRITE_CAL **********\r\n");
+    // uhs_phy_reg_dump();
+    // array_read_dqs_dq_cal();  //calibrated in array_read_latency_cal
+    CHECK_ERR_FLAG(array_write_dqs_dq_cal,());
+    // uhs_phy_reg_dump();
+
+    return 0;
+}
+
+void soft_reset(void)
+{
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_SWRST_CFG2);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_REG_CTRL_PWRON_RST,0x1); // soft power on reset
+    BL_WR_REG(GLB_BASE,GLB_SWRST_CFG2,tmpVal);
+    uhs_phy_delay_ms(1);
+}
+
+uint8_t uhs_diagonal_test(uint32_t data0,uint32_t data1)
+{
+    uint32_t RA = 0x0; //X_address
+    uint32_t CA = 0x0; //Y_address
+    uint32_t CA_init = 0x0;
+    uint32_t dataTmp;
+    uint32_t STRESS_TEST_BASE = 0x50000000;
+    uint32_t RowAddr = 0x3fff; //256Mb X_address
+
+    if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        RowAddr = 0x3fff;
+    }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        RowAddr = 0x7fff;
+    }
+
+    // data0
+    for (RA = 0x0; RA <= RowAddr; RA++){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        CA_init = (RA & 0x7f) << 3;
+        for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0;
+        }
+    }
+    for (RA = 0x0; RA <= RowAddr; RA++){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        CA_init = (RA & 0x7f) << 3;
+        for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+            if(dataTmp != data0){
+                uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+                uhs_phy_printfe("data_w data0: 0x%lx\r\n", data0);
+                uhs_phy_printfe("addr_r data0: 0x%lx\r\n", dataTmp);
+                return uhs_err_handler(UHS_DIAGONAL_TEST_ERR);
+            }
+        }
+    }
+    // data1
+    for (RA = 0x0; RA <= RowAddr; RA++){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        CA_init = (RA & 0x7f) << 3;
+        for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            *((volatile uint32_t*)(STRESS_TEST_BASE)) = data1;
+        }
+    }
+    for (RA = 0x0; RA <= RowAddr; RA++){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        CA_init = (RA & 0x7f) << 3;
+        for (CA = CA_init; CA <= CA_init + 0x7; CA = CA + 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+            if(dataTmp != data1){
+                uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+                uhs_phy_printfe("data_w data1: 0x%lx\r\n", data1);
+                uhs_phy_printfe("addr_r data1: 0x%lx\r\n", dataTmp);
+                return uhs_err_handler(UHS_DIAGONAL_TEST_ERR);
+            }
+        }
+    }
+
+    uhs_phy_printf("uhs_diagonal_test success\r\n");
+    return 0;
+}
+
+uint8_t uhs_all_addr_test(void)
+{
+    int32_t RA = 0x0; //X_address
+    int32_t CA = 0x0; //Y_address
+    uint32_t dataTmp;
+    uint32_t STRESS_TEST_BASE = 0x50000000;
+    uint32_t RowAddr = 0x3fff; //256Mb X_address
+    uint32_t data0 = 0xffffffff;
+    uint32_t data1 = 0x00000000;
+
+    if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        RowAddr = 0x3fff;
+    }else if (cfg_glb->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        RowAddr = 0x7fff;
+    }
+
+    // ****** Y_address -> X_address
+    //data0
+    for (RA = 0x0; RA <= RowAddr; RA++){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        for (CA = 0x0; CA <= 0x3ff; CA = CA + 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0; 
+        }
+    }         
+    for (RA = 0x0; RA <= RowAddr; RA++){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        for(CA = 0x0; CA <= 0x3ff; CA = CA + 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+            if(dataTmp != data0){
+                uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+                uhs_phy_printfe("data_w data0 first: 0x%lx\r\n", data0);
+                uhs_phy_printfe("addr_r data0 first: 0x%lx\r\n", dataTmp);
+                return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR);
+            }
+        }
+    }
+    // data1
+    for (RA = 0x0; RA <= RowAddr; RA++){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        for (CA = 0x0; CA <= 0x3ff; CA = CA + 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            *((volatile uint32_t*)(STRESS_TEST_BASE)) = data1;
+        }
+    }
+    // ****** X_address -> Y_address    
+    // data1 
+    for (RA = RowAddr; RA >= 0x0; RA--){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        for(CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+            if(dataTmp != data1){
+                uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+                uhs_phy_printfe("data_w data1: 0x%lx\r\n", data1);
+                uhs_phy_printfe("addr_r data1: 0x%lx\r\n", dataTmp);
+                return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR);
+            }
+        }
+    }
+    //data0
+    for (RA = RowAddr; RA >= 0x0; RA--){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        for (CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            *((volatile uint32_t*)(STRESS_TEST_BASE)) = data0;
+        }
+    }      
+    for (RA = RowAddr; RA >= 0x0; RA--){
+        STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFC0007FF;
+        STRESS_TEST_BASE = STRESS_TEST_BASE | (RA<<11); // STRESS_TEST_BASE[25:11] = RA[14:0]
+        for(CA = 0x3ff - 1; CA >= 0x0; CA = CA - 2){
+            STRESS_TEST_BASE = STRESS_TEST_BASE & 0xFFFFF800;
+            STRESS_TEST_BASE = STRESS_TEST_BASE | (CA<<1); // STRESS_TEST_BASE[10:2] = CA[9:1], STRESS_TEST_BASE[1:0] = 0;
+            dataTmp = *((volatile uint32_t*)(STRESS_TEST_BASE));
+            if(dataTmp != data0){
+                uhs_phy_printfe("addr: 0x%lx\r\n", STRESS_TEST_BASE);
+                uhs_phy_printfe("data_w data0 second: 0x%lx\r\n", data0);
+                uhs_phy_printfe("addr_r data0 second: 0x%lx\r\n", dataTmp);
+                return uhs_err_handler(UHS_ALL_ADDR_TEST_ERR);
+            }
+        }
+    }
+    uhs_phy_printf("uhs_all_addr_test success\r\n");
+    return 0;   
+}
+
+
+void dump_uhs_phy_cal_res(void)
+{
+    #if CAL_MODE != 2
+    // dump uhs_phy_cal_res
+    uhs_phy_printf("uhs_phy_cal_res->cal_mode = %d\r\n",uhs_phy_cal_res->cal_mode);
+    uhs_phy_printf("uhs_phy_cal_res->err_type = %d\r\n",uhs_phy_cal_res->err_type);
+    uhs_phy_printf("uhs_phy_cal_res->err_sub_type = %d\r\n",uhs_phy_cal_res->err_sub_type);
+    uhs_phy_printf("uhs_phy_cal_res->datarate = %d\r\n",uhs_phy_cal_res->datarate);
+    uhs_phy_printf("uhs_phy_cal_res->rl = %d\r\n",uhs_phy_cal_res->rl);
+    uhs_phy_printf("uhs_phy_cal_res->rdqs = %d\r\n",uhs_phy_cal_res->rdqs);
+    uhs_phy_printf("uhs_phy_cal_res->rdq = %d\r\n",uhs_phy_cal_res->rdq);
+    uhs_phy_printf("uhs_phy_cal_res->rwindow = %d\r\n",uhs_phy_cal_res->rwindow);
+    uhs_phy_printf("uhs_phy_cal_res->rwindow_begin = %d\r\n",uhs_phy_cal_res->rwindow_begin);
+    uhs_phy_printf("uhs_phy_cal_res->rwindow_end = %d\r\n",uhs_phy_cal_res->rwindow_end);
+    uhs_phy_printf("uhs_phy_cal_res->ck = %d\r\n",uhs_phy_cal_res->ck);
+    uhs_phy_printf("uhs_phy_cal_res->wl = %d\r\n",uhs_phy_cal_res->wl);
+    uhs_phy_printf("uhs_phy_cal_res->wdqs = %d\r\n",uhs_phy_cal_res->wdqs);
+    uhs_phy_printf("uhs_phy_cal_res->wdq = %d\r\n",uhs_phy_cal_res->wdq);
+    uhs_phy_printf("uhs_phy_cal_res->wwindow = %d\r\n",uhs_phy_cal_res->wwindow);
+    uhs_phy_printf("uhs_phy_cal_res->wwindow_begin = %d\r\n",uhs_phy_cal_res->wwindow_begin);
+    uhs_phy_printf("uhs_phy_cal_res->wwindow_end = %d\r\n",uhs_phy_cal_res->wwindow_end);
+    uhs_phy_printf("uhs_phy_cal_res->cal_done = %d\r\n",uhs_phy_cal_res->cal_done);
+    uhs_phy_printf("uhs_phy_cal_res->crc_res = %lx\r\n",uhs_phy_cal_res->crc_res);
+    #else
+    // dump uhs_phy_cal_res
+    uhs_phy_printf("uhs_phy_cal_res->cal_mode = %ld\r\n",uhs_phy_cal_res->cal_mode);
+    uhs_phy_printf("uhs_phy_cal_res->err_type = %lx\r\n",uhs_phy_cal_res->err_type);
+    uhs_phy_printf("uhs_phy_cal_res->err_sub_type = %ld\r\n",uhs_phy_cal_res->err_sub_type);
+    uhs_phy_printf("uhs_phy_cal_res->datarate = %ld\r\n",uhs_phy_cal_res->datarate);
+    uhs_phy_printf("uhs_phy_cal_res->rl = %ld\r\n",uhs_phy_cal_res->rl);
+    uhs_phy_printf("uhs_phy_cal_res->rdqs = %ld\r\n",uhs_phy_cal_res->rdqs);
+    uhs_phy_printf("uhs_phy_cal_res->rdq = %ld\r\n",uhs_phy_cal_res->rdq);
+    uhs_phy_printf("uhs_phy_cal_res->rwindow = %ld\r\n",uhs_phy_cal_res->rwindow);
+    uhs_phy_printf("uhs_phy_cal_res->rwindow_begin = %ld\r\n",uhs_phy_cal_res->rwindow_begin);
+    uhs_phy_printf("uhs_phy_cal_res->rwindow_end = %ld\r\n",uhs_phy_cal_res->rwindow_end);
+    uhs_phy_printf("uhs_phy_cal_res->ck = %ld\r\n",uhs_phy_cal_res->ck);
+    uhs_phy_printf("uhs_phy_cal_res->wl = %ld\r\n",uhs_phy_cal_res->wl);
+    uhs_phy_printf("uhs_phy_cal_res->wdqs = %ld\r\n",uhs_phy_cal_res->wdqs);
+    uhs_phy_printf("uhs_phy_cal_res->wdq = %ld\r\n",uhs_phy_cal_res->wdq);
+    uhs_phy_printf("uhs_phy_cal_res->wwindow = %ld\r\n",uhs_phy_cal_res->wwindow);
+    uhs_phy_printf("uhs_phy_cal_res->wwindow_begin = %ld\r\n",uhs_phy_cal_res->wwindow_begin);
+    uhs_phy_printf("uhs_phy_cal_res->wwindow_end = %ld\r\n",uhs_phy_cal_res->wwindow_end);
+    uhs_phy_printf("uhs_phy_cal_res->cal_done = %lx\r\n",uhs_phy_cal_res->cal_done);
+    uhs_phy_printf("uhs_phy_cal_res->crc_res = %lx\r\n",uhs_phy_cal_res->crc_res);
+    #endif
+}
+
+void uhs_phy_init(PSRAM_UHS_Cfg_Type *cfg)
+{
+    memset((void*)uhs_phy_cal_res, 0, sizeof(uhs_phy_cal_res_struct));
+    uhs_phy_cal_res->cal_mode = CAL_MODE;
+    uhs_phy_cal_res->datarate = cfg->pck_freq;
+
+    err_flag = 0;
+
+    __DSB();
+    __ISB();
+    cache_state = __get_MHCR();
+    cache_state &= (0x1<<1);
+    __DSB();
+    __ISB();
+
+    cfg_glb = cfg;
+    latency_wr_2kM[1] = 41;
+    uhs_phy_init_core(cfg);
+}
+
+extern uint32_t ATTR_TCM_SECTION BFLB_Soft_CRC32(void *dataIn, uint32_t len);
+uint8_t uhs_phy_init_core(PSRAM_UHS_Cfg_Type *cfg)
+{
+    cal_done_flag = 0;
+    if(latency_wr_2kM[1] == 34)
+    {
+        reg_read_err = 3;
+        return uhs_err_handler(UHS_REG_READ_CAL_ERR);
+    }
+
+    uint32_t pck_freq_temp;
+
+    uhs_phy_printf_debug("uhs phy init\r\n");
+    if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        uhs_phy_printf("\r\n########## START_CAL_AT %ldMbps, PSRAM_MEM_SIZE_32MB, CACHE_EN = %ld ##########\r\n",cfg->pck_freq,cache_state);
+	}else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        uhs_phy_printf("\r\n########## START_CAL_AT %ldMbps, PSRAM_MEM_SIZE_64MB, CACHE_EN = %ld ##########\r\n",cfg->pck_freq,cache_state);
+    }
+    #if CAL_MODE != 2
+        uhs_phy_printf("CAL_MODE = %d\r\n",uhs_phy_cal_res->cal_mode);
+    #else
+        uhs_phy_printf("CAL_MODE = %ld\r\n",uhs_phy_cal_res->cal_mode);
+    #endif
+
+    power_up_mm(0);
+    power_up_uhspll();
+    
+    power_up_ldo12uhs();
+    set_cen_ck_ckn();
+
+    set_or_uhs();
+    switch_to_ldo12uhs();
+    release_cen_ck_ckn();
+
+    uint32_t tmpVal = 0;
+    tmpVal = BL_RD_REG(GLB_BASE,GLB_UHS_PLL_CFG9);
+    tmpVal = BL_SET_REG_BITS_VAL(tmpVal,GLB_UHSPLL_SSC_EN,0x0); // uhspll_ssc_en
+    BL_WR_REG(GLB_BASE,GLB_UHS_PLL_CFG9,tmpVal);
+    pck_freq_temp = cfg->pck_freq;
+    if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        cfg->pck_freq = 800;
+        // PSRAM_UHS_Cfg_Type psramCfg = {
+        //     800,
+        //     PSRAM_MEM_SIZE_32MB,
+        //     PSRAM_PAGE_SIZE_2KB,
+        //     0,
+        // };
+
+        GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,800);    //stuck
+        Psram_UHS_Init_Override(cfg);  // controller init
+        set_uhs_phy_init();         // phy init
+        set_uhs_latency_w(1);
+        set_uhs_latency_r(17);
+        psram_init();               // psram init after set freq & set_phy
+
+        // uhs_reg_r(0,1);
+        // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+        // uhs_phy_printf_debug("readout MA0 = 0x%lx\r\n",tmpVal);
+        // if(tmpVal == ((2<<3)+5))    // 700M --> default uhs_latency_code == 5
+        // {
+        //     uhs_phy_printf_debug("register read pass at 700Mbps\r\n");
+        // }
+        // else{
+        //     uhs_phy_printf_debug("register read fail at 700Mbps\r\n");
+        // }
+    }
+	else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        cfg->pck_freq = 1400;
+        // PSRAM_UHS_Cfg_Type psramCfg = {
+        //     1400,
+        //     PSRAM_MEM_SIZE_64MB,
+        //     PSRAM_PAGE_SIZE_2KB,
+        //     0,
+        // };
+
+        GLB_Config_UHS_PLL_Freq(GLB_XTAL_40M,1400);    //stuck
+        Psram_UHS_Init_Override(cfg);  // controller init
+        set_uhs_phy_init();         // phy init
+        set_uhs_latency_w(9);
+        set_uhs_latency_r(30);
+        psram_init();               // psram init after set freq & set_phy
+
+        // uhs_reg_r(0,1);
+        // tmpVal = BL_RD_REG(PSRAM_UHS_BASE,PSRAM_UHS_UHS_CMD)>>24;
+        // if(tmpVal == ((2<<3)+1))    // 1400M --> default uhs_latency_code == 1
+        // {
+        //     uhs_phy_printf_debug("register read pass at 1400Mbps\r\n");
+        // }
+        // else{
+        //     uhs_phy_printf_debug("register read fail at 1400Mbps\r\n");
+        // }
+    }
+    
+    cfg->pck_freq = pck_freq_temp;
+    self_cal();
+    uhs_phy_delay_ms(1);
+    cal_done_flag = 1;
+    #if CAL_MODE == 2
+    if(err_flag == 0){
+        uhs_phy_printf("********** UHS_DIAGONAL_TEST **********\r\n");
+        uhs_diagonal_test(0x5555aaaa,0xaaaa5555);
+        // uhs_phy_printf("********** UHS_ALL_ADDR_TEST **********\r\n");
+        // uhs_all_addr_test();
+    }
+    // uhs_phy_printfe("!!!!!!!!!! uhs_phy_cal_res->err_type = %d !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type);l
+    uint32_t magic_os = 0x89abcdef;
+    uhs_phy_cal_res->err_type += magic_os;
+    uhs_phy_cal_res->cal_done = magic_os;
+    uhs_phy_cal_res->crc_res = BFLB_Soft_CRC32(uhs_phy_cal_res, sizeof(uhs_phy_cal_res_struct)-4);
+    #elif CAL_MODE == 1
+    uhs_phy_cal_res->cal_done = 1;
+    uhs_phy_cal_res->crc_res = BFLB_Soft_CRC32(uhs_phy_cal_res, sizeof(uhs_phy_cal_res_struct)-4);
+    #endif
+
+    #if CAL_MODE != 2
+    uhs_phy_printf("!!!!!!!!!! uhs_phy_cal_res->err_type = %d !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type);
+    #else
+    uhs_phy_printf("!!!!!!!!!! uhs_phy_cal_res->err_type = %lx !!!!!!!!!!\r\n",uhs_phy_cal_res->err_type);
+    #endif
+
+    dump_uhs_phy_cal_res();
+    return uhs_phy_cal_res->err_type;
+
+    //get dcache original state
+    __DSB();
+    __ISB();
+    dcache_original = __get_MHCR();
+    dcache_original &= (0x1<<1);
+    __DSB();
+    __ISB();
+    uhs_phy_printf_debug("dcache_original= 0x%lx\r\n",dcache_original);
+
+    uhs_phy_printf("UHS_PHY_CAL, CACHE_EN = %d\r\n",CACHE_EN);
+    #if CACHE_EN
+    csi_dcache_enable();
+    #else
+    csi_dcache_disable();
+    #endif
+
+    //get dcache current state
+    __DSB();
+    __ISB();
+    dcache_current = __get_MHCR();
+    dcache_current &= (0x1<<1);
+    __DSB();
+    __ISB();
+    uhs_phy_printf_debug("dcache_current= 0x%lx\r\n",dcache_current);
+
+    cfg->pck_freq = pck_freq_temp;
+    #if CACHE_EN
+    if(dcache_current == (0x1<<1))
+    {
+        self_cal();
+    }
+    else
+    {
+        uhs_phy_printf_debug("dcache enable fail\r\n");
+        return uhs_err_handler(UHS_CACHE_ENABLE_ERR);
+    }
+    if (dcache_original == 0)
+    {     
+            csi_dcache_disable();       
+    }  
+    #else
+    if(dcache_current == 0x0)
+    {
+        self_cal();
+    }
+    else
+    {
+        uhs_phy_printf_debug("dcache disable fail\r\n");
+        return uhs_err_handler(UHS_CACHE_DISABLE_ERR);
+    } 
+    if (dcache_original == (0x1<<1))
+    {     
+        csi_dcache_enable();       
+    }
+    #endif
+
+    //get dcache end state
+    __DSB();
+    __ISB();
+    dcache_end = __get_MHCR();
+    dcache_end &= (0x1<<1);
+    __DSB();
+    __ISB();
+    if(dcache_end == dcache_original)
+    {
+        uhs_phy_printf_debug("dcache state right , dcache_state= 0x%lx\r\n",dcache_end);
+    }
+    else
+    {
+        uhs_phy_printf_debug("dcache state error\r\n");
+        return uhs_err_handler(UHS_CACHE_RECOVER_ERR);
+    }
+
+    uhs_phy_delay_ms(1);
+
+    if (cfg->psramMemSize == PSRAM_MEM_SIZE_32MB){
+        uhs_phy_printf("########## END_CAL_AT %ldMbps, PSRAM_MEM_SIZE_32MB ##########\r\n",cfg->pck_freq);
+    }else if(cfg->psramMemSize == PSRAM_MEM_SIZE_64MB){
+        uhs_phy_printf("########## END_CAL_AT %ldMbps, PSRAM_MEM_SIZE_64MB ##########\r\n",cfg->pck_freq);
+    }
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/interrupt.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/interrupt.c
new file mode 100755
index 0000000000..6a59413339
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/interrupt.c
@@ -0,0 +1,154 @@
+#include "bflb_core.h"
+#include 
+#include "irq_ctx.h"
+#include "bl808_glb.h"
+
+extern void riscv_savefpu(const uintptr_t *regs);
+extern void riscv_restorefpu(const uintptr_t *regs);
+
+#define RV_EXCEPTION_NUM (16)
+typedef uintptr_t (*exception_handler)(uintptr_t cause, uintptr_t val, uintptr_t *regs);
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM] __attribute__((aligned(16)));
+
+static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs) __attribute__((noreturn));
+static uintptr_t exception_handler_default(uintptr_t cause, uintptr_t val, uintptr_t *regs)
+{
+    printf("\n\rUn-handled Exception on CPU %d:\n\r", GLB_Get_Core_Type());
+    // clang-format off
+    printf("mstatus = 0x%16llx, FS=%d, MPP=%d, MPIE=%d\n\r", regs[REG_INT_CTX_NDX],
+                                                     (regs[REG_INT_CTX_NDX] >> 13) & 0x3,
+                                                     (regs[REG_INT_CTX_NDX] >> 11) & 0x3,
+                                                     (regs[REG_INT_CTX_NDX] >> 7) & 1);
+    printf("mcause: %d, mtval = 0x%16llx, mepc = 0x%16llx\n\r\n\r", (cause & 0xf), val, regs[REG_EPC_NDX]);
+
+const char *mcause_str[] = {
+    "Instruction address misaligned",
+    "Instruction access fault",
+    "Illegal instruction",
+    "Breakpoint",
+    "Load address misaligned",
+    "Load access fault",
+    "Store/AMO address misaligned",
+    "Store/AMO access fault",
+    "Environment call from U-mode",
+    "Environment call from S-mode",
+    "RSVD",
+    "Environment call from M-mode",
+    "Instruction page fault",
+    "Load page fault",
+    "RSVD",
+    "Store/AMO page fault"
+};
+    if ((cause & 0xf))
+        printf("%s\r\n\r\n", mcause_str[cause & 0xf]);
+
+#ifdef CONFIG_TRAP_DUMP_ALL_REGS
+    printf("ra = 0x%16llx  ", regs[REG_RA]); printf("sp = 0x%16llx  ", regs[REG_SP]); printf("gp = 0x%16llx  ", regs[REG_GP]);
+    printf("tp = 0x%16llx  ", regs[REG_TP]); printf("\n\r");
+
+    printf("t0 = 0x%16llx  ", regs[REG_T0]); printf("t1 = 0x%16llx  ", regs[REG_T1]); printf("t2 = 0x%16llx  ", regs[REG_T2]);
+    printf("t3 = 0x%16llx  ", regs[REG_T3]); printf("\n\r");
+    printf("t4 = 0x%16llx  ", regs[REG_T4]); printf("t5 = 0x%16llx  ", regs[REG_T5]); printf("t6 = 0x%16llx  ", regs[REG_T6]);
+    printf("\n\r");
+
+    printf("a0 = 0x%16llx  ", regs[REG_A0]); printf("a1 = 0x%16llx  ", regs[REG_A1]); printf("a2 = 0x%16llx  ", regs[REG_A2]);
+    printf("a3 = 0x%16llx  ", regs[REG_A3]); printf("\n\r");
+    printf("a4 = 0x%16llx  ", regs[REG_A4]); printf("a5 = 0x%16llx  ", regs[REG_A5]); printf("a6 = 0x%16llx  ", regs[REG_A6]);
+    printf("a7 = 0x%16llx  ", regs[REG_A7]); printf("\n\r");
+
+    printf("s0 = 0x%16llx  ", regs[REG_S0]); printf("s1 = 0x%16llx  ", regs[REG_S1]); printf("s2 = 0x%16llx  ", regs[REG_S2]);
+    printf("s3 = 0x%16llx  ", regs[REG_S3]); printf("\n\r");
+    printf("s4 = 0x%16llx  ", regs[REG_S4]); printf("s5 = 0x%16llx  ", regs[REG_S5]); printf("s6 = 0x%16llx  ", regs[REG_S6]);
+    printf("s7 = 0x%16llx  ", regs[REG_S7]); printf("\n\r");
+    printf("s8 = 0x%16llx  ", regs[REG_S8]); printf("s9 = 0x%16llx  ", regs[REG_S9]); printf("s10 = 0x%16llx ", regs[REG_S10]);
+    printf("s11 = 0x%16llx  ", regs[REG_S11]); printf("\n\r");
+#endif
+    // clang-format on
+    printf("\n\r");
+
+    while (1) {
+    }
+}
+
+static uintptr_t exception_handler_ECALL_M(uintptr_t cause, uintptr_t val, uintptr_t *regs)
+{
+    regs[REG_EPC_NDX] += 4;
+    __asm volatile("nop" ::
+                       : "memory");
+
+    return 0;
+}
+
+static exception_handler exception_handlers[RV_EXCEPTION_NUM] = {
+    exception_handler_default, /*  0: Instruction Address Misaligned */
+    exception_handler_default, /*  1: Instruction Access Fault */
+    exception_handler_default, /*  2: Illegal Instruction */
+    exception_handler_default, /*  3: Breakpoint */
+    exception_handler_default, /*  4: Load Address Misaligned */
+    exception_handler_default, /*  5: Load Access Fault */
+    exception_handler_default, /*  6: Store/AMO Address Misaligned */
+    exception_handler_default, /*  7: Store/AMO Access Fault */
+    exception_handler_default, /*  8: Environment Call from U-mode */
+    exception_handler_default, /*  9: Environment Call from S-mode */
+    exception_handler_default, /* 10: Environment Call from H-mode */
+    exception_handler_ECALL_M, /* 11: Environment Call from M-mode */
+    exception_handler_default, /* 12: Instruction Page Fault */
+    exception_handler_default, /* 13: Load Page Fault */
+    exception_handler_default, /* 14: Reserved */
+    exception_handler_default, /* 15: Store/AMO Page Fault */
+};
+
+exception_handler exception_handler_install(uintptr_t vec, exception_handler handler)
+{
+    exception_handler previous = NULL;
+
+    if (RV_EXCEPTION_NUM > vec) {
+        previous = exception_handlers[vec];
+        exception_handlers[vec] = handler;
+    }
+
+    return previous;
+}
+
+uintptr_t *trap_c(uintptr_t cause, uintptr_t *regs)
+{
+    uint32_t vec = 0;
+    uintptr_t tval = __get_MTVAL();
+
+    riscv_savefpu(regs);
+
+    vec = cause & 0x3FF;
+
+    if (RV_EXCEPTION_NUM > vec) {
+        exception_handlers[vec](cause, tval, regs);
+    } else {
+        while (1)
+            ;
+    }
+
+    riscv_restorefpu(regs);
+
+    return regs;
+}
+
+void interrupt_entry(uint64_t irq_num)
+{
+    irq_callback handler;
+    void *arg;
+    // volatile uint32_t irq_num;
+
+    //irq_num = PLIC->PLIC_H0_MCLAIM & 0x3ff;
+
+    if (irq_num < CONFIG_IRQ_NUM) {
+        handler = g_irqvector[irq_num].handler;
+        arg = g_irqvector[irq_num].arg;
+        if (handler) {
+            handler(irq_num, arg);
+        } else {
+        }
+    } else {
+    }
+}
\ No newline at end of file
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/irq_ctx.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/irq_ctx.h
old mode 100644
new mode 100755
similarity index 100%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/irq_ctx.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/irq_ctx.h
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/riscv_fpu.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/riscv_fpu.S
new file mode 100755
index 0000000000..a88e6230d4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/riscv_fpu.S
@@ -0,0 +1,221 @@
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+#if defined(CONFIG_ARCH_FPU)
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Symbols
+ ************************************************************************************/
+
+	.globl		riscv_fpuconfig
+	.globl		riscv_savefpu
+	.globl		riscv_savefpu_force
+	.globl		riscv_restorefpu
+
+	.file		"riscv_fpu.S"
+
+#define FS_MASK		0x6000
+#define FS_OFF		0x0000
+#define FS_INITIAL	0x2000
+#define FS_CLEAN	0x4000
+#define FS_DIRTY	0x6000
+
+#if defined(CONFIG_ARCH_DPFPU)
+#  define FLOAD		fld
+#  define FSTORE	fsd
+#  define LOAD		ld
+#  define STORE		sd
+#elif defined(CONFIG_ARCH_QPFPU)
+#  define FLOAD		flq
+#  define FSTORE	fsq
+#else
+#  define FLOAD		flw
+#  define FSTORE	fsw
+#  define LOAD		lw
+#  define STORE		sw
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: riscv_fpuconfig
+ *
+ * Description:
+ *   init fpu
+ *
+ * C Function Prototype:
+ *   void riscv_fpuconfig(void);
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   This function does not return anything explicitly.
+ *
+ ************************************************************************************/
+
+	.type		riscv_fpuconfig, function
+
+riscv_fpuconfig:
+	li			a0, FS_INITIAL
+	csrs		mstatus, a0
+	csrwi		fcsr, 0
+	ret
+
+/************************************************************************************
+ * Name: riscv_savefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in A0), save the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void riscv_savefpu(uintptr_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area in which to save the floating point
+ *     registers
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+	.type		riscv_savefpu, function
+
+riscv_savefpu:
+	LOAD	t0, REG_INT_CTX(a0)
+	li		t1, FS_MASK
+	and		t2, t0, t1
+	li		t1, FS_DIRTY
+	bne		t2, t1, 1f
+	li		t1, ~FS_MASK
+	and		t0, t0, t1
+	li		t1, FS_CLEAN
+	or		t0, t0, t1
+	STORE	t0, REG_INT_CTX(a0)
+
+	/* Store all floating point registers */
+riscv_savefpu_force:
+
+	FSTORE		f0,  REG_F0(a0)
+	FSTORE		f1,  REG_F1(a0)
+	FSTORE		f2,  REG_F2(a0)
+	FSTORE		f3,  REG_F3(a0)
+	FSTORE		f4,  REG_F4(a0)
+	FSTORE		f5,  REG_F5(a0)
+	FSTORE		f6,  REG_F6(a0)
+	FSTORE		f7,  REG_F7(a0)
+	FSTORE		f8,  REG_F8(a0)
+	FSTORE		f9,  REG_F9(a0)
+	FSTORE		f10, REG_F10(a0)
+	FSTORE		f11, REG_F11(a0)
+	FSTORE		f12, REG_F12(a0)
+	FSTORE		f13, REG_F13(a0)
+	FSTORE		f14, REG_F14(a0)
+	FSTORE		f15, REG_F15(a0)
+	FSTORE		f16, REG_F16(a0)
+	FSTORE		f17, REG_F17(a0)
+	FSTORE		f18, REG_F18(a0)
+	FSTORE		f19, REG_F19(a0)
+	FSTORE		f20, REG_F20(a0)
+	FSTORE		f21, REG_F21(a0)
+	FSTORE		f22, REG_F22(a0)
+	FSTORE		f23, REG_F23(a0)
+	FSTORE		f24, REG_F24(a0)
+	FSTORE		f25, REG_F25(a0)
+	FSTORE		f26, REG_F26(a0)
+	FSTORE		f27, REG_F27(a0)
+	FSTORE		f28, REG_F28(a0)
+	FSTORE		f29, REG_F29(a0)
+	FSTORE		f30, REG_F30(a0)
+	FSTORE		f31, REG_F31(a0)
+
+	frcsr		t0
+	STORE		t0, REG_FCSR(a0)
+
+1:
+	ret
+
+/************************************************************************************
+ * Name: riscv_restorefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in A0), restore the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void riscv_restorefpu(const uintptr_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area containing the floating point
+ *     registers.
+ *
+ * Returned Value:
+ *   This function does not return anything explicitly.  However, it is called from
+ *   interrupt level assembly logic that assumes that r0 is preserved.
+ *
+ ************************************************************************************/
+
+	.type		riscv_restorefpu, function
+
+riscv_restorefpu:
+	LOAD	t0, REG_INT_CTX(a0)
+	li		t1, FS_MASK
+	and		t2, t0, t1
+	li		t1, FS_INITIAL
+	ble		t2, t1, 1f
+
+	/* Load all floating point registers */
+
+	FLOAD		f0, REG_F0(a0)
+	FLOAD		f1, REG_F1(a0)
+	FLOAD		f2, REG_F2(a0)
+	FLOAD		f3, REG_F3(a0)
+	FLOAD		f4, REG_F4(a0)
+	FLOAD		f5, REG_F5(a0)
+	FLOAD		f6, REG_F6(a0)
+	FLOAD		f7, REG_F7(a0)
+	FLOAD		f8, REG_F8(a0)
+	FLOAD		f9, REG_F9(a0)
+	FLOAD		f10, REG_F10(a0)
+	FLOAD		f11, REG_F11(a0)
+	FLOAD		f12, REG_F12(a0)
+	FLOAD		f13, REG_F13(a0)
+	FLOAD		f14, REG_F14(a0)
+	FLOAD		f15, REG_F15(a0)
+	FLOAD		f16, REG_F16(a0)
+	FLOAD		f17, REG_F17(a0)
+	FLOAD		f18, REG_F18(a0)
+	FLOAD		f19, REG_F19(a0)
+	FLOAD		f20, REG_F20(a0)
+	FLOAD		f21, REG_F21(a0)
+	FLOAD		f22, REG_F22(a0)
+	FLOAD		f23, REG_F23(a0)
+	FLOAD		f24, REG_F24(a0)
+	FLOAD		f25, REG_F25(a0)
+	FLOAD		f26, REG_F26(a0)
+	FLOAD		f27, REG_F27(a0)
+	FLOAD		f28, REG_F28(a0)
+	FLOAD		f29, REG_F29(a0)
+	FLOAD		f30, REG_F30(a0)
+	FLOAD		f31, REG_F31(a0)
+
+	/* Store the floating point control and status register */
+
+	LOAD		t0, REG_FCSR(a0)
+	fscsr		t0
+
+1:
+	ret
+
+#endif /* CONFIG_ARCH_FPU */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/startup.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start.S
old mode 100644
new mode 100755
similarity index 85%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/startup.S
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start.S
index dcf433f498..b2d73760aa
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/startup.S
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start.S
@@ -1,14 +1,13 @@
 /*
  * Copyright (C) 2016-2020 Bouffalo Lab
  */
-#include "riscv_encoding.h"
+#include 
 
-_start:
-    .text
+    .section .init
     .align  2
-    .globl  Reset_Handler
-    .type   Reset_Handler, %function
-Reset_Handler:
+    .globl  __start
+    .type   __start, %function
+__start:
 .option push
 .option norelax
     la      gp, __global_pointer$
@@ -77,20 +76,16 @@ Reset_Handler:
     la      sp, __StackTop
     csrw    mscratch, sp
 
-#ifndef __NO_SYSTEM_INIT
-    jal     System_Init
-#endif
+    jal     SystemInit
 
     /* start load code to itcm like. */
     jal     start_load
 
-#ifndef __NO_BOARD_INIT
     jal     System_Post_Init
-#endif
 
     jal     main
 
-    .size   Reset_Handler, . - Reset_Handler
+    .size   __start, . - __start
 
 __exit:
     j      __exit
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start_load.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start_load.c
new file mode 100755
index 0000000000..12adf18aa3
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/start_load.c
@@ -0,0 +1,84 @@
+#include 
+
+#define __STARTUP_CLEAR_BSS 1
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __itcm_load_addr;
+extern uint32_t __dtcm_load_addr;
+extern uint32_t __system_ram_load_addr;
+extern uint32_t __ram_load_addr;
+extern uint32_t __nocache_ram_load_addr;
+
+extern uint32_t __text_code_start__;
+extern uint32_t __text_code_end__;
+extern uint32_t __tcm_code_start__;
+extern uint32_t __tcm_code_end__;
+extern uint32_t __tcm_data_start__;
+extern uint32_t __tcm_data_end__;
+extern uint32_t __ram_data_start__;
+extern uint32_t __ram_data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __noinit_data_start__;
+extern uint32_t __noinit_data_end__;
+extern uint32_t __nocache_ram_data_start__;
+extern uint32_t __nocache_ram_data_end__;
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+//extern uint32_t __copy_table_start__;
+//extern uint32_t __copy_table_end__;
+//extern uint32_t __zero_table_start__;
+//extern uint32_t __zero_table_end__;
+
+void start_load(void)
+{
+    uint32_t *pSrc, *pDest;
+    uint32_t *pTable __attribute__((unused));
+
+    /* Copy ITCM code */
+    pSrc = &__itcm_load_addr;
+    pDest = &__tcm_code_start__;
+
+    for (; pDest < &__tcm_code_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* Copy DTCM code */
+    pSrc = &__dtcm_load_addr;
+    pDest = &__tcm_data_start__;
+
+    for (; pDest < &__tcm_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* BF Add OCARAM data copy */
+    pSrc = &__ram_load_addr;
+    pDest = &__ram_data_start__;
+
+    for (; pDest < &__ram_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+#ifdef __STARTUP_CLEAR_BSS
+    /*  Single BSS section scheme.
+	 *
+	 *  The BSS section is specified by following symbols
+	 *    __bss_start__: start of the BSS section.
+	 *    __bss_end__: end of the BSS section.
+	 *
+	 *  Both addresses must be aligned to 4 bytes boundary.
+	 */
+    pDest = &__bss_start__;
+
+    for (; pDest < &__bss_end__;) {
+        *pDest++ = 0ul;
+    }
+
+#endif
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/system_bl808.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/system_bl808.c
new file mode 100755
index 0000000000..f4f940a764
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/system_bl808.c
@@ -0,0 +1,56 @@
+#include "bl808_clock.h"
+#include "bl808_ef_cfg.h"
+
+#define BL808_B0 (0x0)
+#define BL808_B1 (0x1)
+
+void SystemInit(void)
+{
+    uintptr_t tmpVal = 0;
+
+    while ((BL_RD_WORD(IPC_SYNC_ADDR1) != IPC_SYNC_FLAG) ||
+           (BL_RD_WORD(IPC_SYNC_ADDR2) != IPC_SYNC_FLAG)) {
+        // clang-format off
+        __NOP(); __NOP(); __NOP(); __NOP();
+        __NOP(); __NOP(); __NOP(); __NOP();
+        __NOP(); __NOP(); __NOP(); __NOP();
+        __NOP(); __NOP(); __NOP(); __NOP();
+        // clang-format on
+        /* if cache is off, comment this and this api need to start load itcm*/
+        // L1C_DCache_Invalid_By_Addr(IPC_SYNC_ADDR1, 8);
+    };
+    /* clear this flags for system reboot */
+    BL_WR_WORD(IPC_SYNC_ADDR1, 0x0);
+    BL_WR_WORD(IPC_SYNC_ADDR2, 0x0);
+
+    /* turn on cache to speed up boot sequence */
+    csi_icache_enable();
+    csi_dcache_enable();
+
+    /* enable I/D Cache preload. */
+    tmpVal = __get_MHINT();
+    tmpVal |= (1 << 8) | (1 << 2);
+    /* clear AMR */
+    tmpVal &= (~0x18);
+    __set_MHINT(tmpVal);
+}
+
+void System_Post_Init(void)
+{
+    csi_dcache_clean();
+    csi_icache_invalid();
+
+    /* fix amr setting */
+    uintptr_t tmpVal = 0;
+    bflb_efuse_device_info_type chip_info;
+    bflb_ef_ctrl_get_device_info(&chip_info);
+    /* if not B0 enable AMR */
+    if (chip_info.chipInfo != BL808_B0) {
+        tmpVal = __get_MHINT();
+        tmpVal |= (1 << 3);
+        __set_MHINT(tmpVal);
+    }
+
+    /* global IRQ enable */
+    __enable_irq();
+}
\ No newline at end of file
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/vectors.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/vector.S
old mode 100644
new mode 100755
similarity index 98%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/vectors.S
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/vector.S
index c72d0d3b17..42102d1316
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/d0/source/GCC/vectors.S
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/d0/vector.S
@@ -139,16 +139,15 @@ Mcoret_Handler:
     la      t2, CORET_IRQHandler
     jalr    t2
 #else
-    la      t0, g_irqvector
-    addi    t0, t0, 7*8
-    ld      t2, (t0)
+    li      a0, 7
+    la      t2, interrupt_entry
     jalr    t2
 #endif
     csrc    mstatus, 8
 
     li      t0, MSTATUS_PRV1
     csrs    mstatus, t0
-    
+
     fld     ft0, (0 +0 )(sp)
     fld     ft1, (4 +4 )(sp)
     fld     ft2, (8 +8 )(sp)
@@ -251,11 +250,10 @@ Sirq_Handler:
     fsd     ft11,(76+76)(sp)
 
     andi    t2, t2, 0x3FF
+    mv      a0, t2
     slli    t2, t2, 3
 
-    la      t0, g_irqvector
-    add     t0, t0, t2
-    ld      t2, (t0)
+    la      t2, interrupt_entry
     jalr    t2
 
     csrc    sstatus, 2
@@ -377,11 +375,10 @@ Sirq_Handler_M:
     fsd     ft11,(76+76)(sp)
 
     andi    t2, t2, 0x3FF
+    mv      a0, t2
     slli    t2, t2, 3
 
-    la      t0, g_irqvector
-    add     t0, t0, t2
-    ld      t2, (t0)
+    la      t2, interrupt_entry
     jalr    t2
 
     csrc    mstatus, 8
@@ -508,11 +505,10 @@ Default_IRQHandler:
     sw      t1, 0(t0)
 
     andi    t2, t2, 0x3FF
+    mv      a0, t2
     slli    t2, t2, 3
 
-    la      t0, g_irqvector
-    add     t0, t0, t2
-    ld      t2, (t0)
+    la      t2, interrupt_entry
     jalr    t2
 
     csrc    mstatus, 8
@@ -534,7 +530,7 @@ Default_IRQHandler:
 
     li      t0, MSTATUS_PRV1
     csrs    mstatus, t0
-    
+
     fld     ft0, (0 +0 )(sp)
     fld     ft1, (4 +4 )(sp)
     fld     ft2, (8 +8 )(sp)
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/interrupt.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/interrupt.c
new file mode 100755
index 0000000000..a9a4275dba
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/interrupt.c
@@ -0,0 +1,206 @@
+/**
+ * @file interrupt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bflb_core.h"
+#include 
+#include "irq_ctx.h"
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
+
+extern void default_trap_handler(void);
+extern void default_interrupt_handler(void);
+
+const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*  3: M-mode Soft IRQ   */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*  7: M-mode Timer IRQ  */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+
+    default_interrupt_handler, //BMX_ERR_IRQHandler_Wrapper,              /* 16 +  0 */
+    default_interrupt_handler, //BMX_TO_IRQHandler_Wrapper,               /* 16 +  1 */
+    default_interrupt_handler, //L1C_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  2 */
+    default_interrupt_handler, //L1C_BMX_TO_IRQHandler_Wrapper,           /* 16 +  3 */
+    default_interrupt_handler, //SEC_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  4 */
+    default_interrupt_handler, //RF_TOP_INT0_IRQHandler_Wrapper,          /* 16 +  5 */
+    default_interrupt_handler, //RF_TOP_INT1_IRQHandler_Wrapper,          /* 16 +  6 */
+    default_interrupt_handler, //SDIO_IRQHandler_Wrapper,                 /* 16 +  7 */
+    default_interrupt_handler, //DMA_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  8 */
+    default_interrupt_handler, //SEC_GMAC_IRQHandler_Wrapper,             /* 16 +  9 */
+    default_interrupt_handler, //SEC_CDET_IRQHandler_Wrapper,             /* 16 + 10 */
+    default_interrupt_handler, //SEC_PKA_IRQHandler_Wrapper,              /* 16 + 11 */
+    default_interrupt_handler, //SEC_TRNG_IRQHandler_Wrapper,             /* 16 + 12 */
+    default_interrupt_handler, //SEC_AES_IRQHandler_Wrapper,              /* 16 + 13 */
+    default_interrupt_handler, //SEC_SHA_IRQHandler_Wrapper,              /* 16 + 14 */
+    default_interrupt_handler, //DMA_ALL_IRQHandler_Wrapper,              /* 16 + 15 */
+    default_interrupt_handler, //0,                                       /* 16 + 16 */
+    default_interrupt_handler, //0,                                       /* 16 + 17 */
+    default_interrupt_handler, //0,                                       /* 16 + 18 */
+    default_interrupt_handler, //IRTX_IRQHandler_Wrapper,                 /* 16 + 19 */
+    default_interrupt_handler, //IRRX_IRQHandler_Wrapper,                 /* 16 + 20 */
+    default_interrupt_handler, //0,                                       /* 16 + 21 */
+    default_interrupt_handler, //0,                                       /* 16 + 22 */
+    default_interrupt_handler, //SF_CTRL_IRQHandler_Wrapper,              /* 16 + 23 */
+    default_interrupt_handler, //0,                                       /* 16 + 24 */
+    default_interrupt_handler, //GPADC_DMA_IRQHandler_Wrapper,            /* 16 + 25 */
+    default_interrupt_handler, //EFUSE_IRQHandler_Wrapper,                /* 16 + 26 */
+    default_interrupt_handler, //SPI_IRQHandler_Wrapper,                  /* 16 + 27 */
+    default_interrupt_handler, //0,                                       /* 16 + 28 */
+    default_interrupt_handler, //UART0_IRQHandler_Wrapper,                /* 16 + 29 */
+    default_interrupt_handler, //UART1_IRQHandler_Wrapper,                /* 16 + 30 */
+    default_interrupt_handler, //0,                                       /* 16 + 31 */
+    default_interrupt_handler, //I2C_IRQHandler_Wrapper,                  /* 16 + 32 */
+    default_interrupt_handler, //0,                                       /* 16 + 33 */
+    default_interrupt_handler, //PWM_IRQHandler_Wrapper,                  /* 16 + 34 */
+    default_interrupt_handler, //0,                                       /* 16 + 35 */
+    default_interrupt_handler, //TIMER_CH0_IRQHandler_Wrapper,            /* 16 + 36 */
+    default_interrupt_handler, //TIMER_CH1_IRQHandler_Wrapper,            /* 16 + 37 */
+    default_interrupt_handler, //TIMER_WDT_IRQHandler_Wrapper,            /* 16 + 38 */
+    default_interrupt_handler, //0,                                       /* 16 + 39 */
+    default_interrupt_handler, //0,                                       /* 16 + 40 */
+    default_interrupt_handler, //0,                                       /* 16 + 41 */
+    default_interrupt_handler, //0,                                       /* 16 + 42 */
+    default_interrupt_handler, //0,                                       /* 16 + 43 */
+    default_interrupt_handler, //GPIO_INT0_IRQHandler_Wrapper,            /* 16 + 44 */
+    default_interrupt_handler, //0,                                       /* 16 + 45 */
+    default_interrupt_handler, //0,                                       /* 16 + 46 */
+    default_interrupt_handler, //0,                                       /* 16 + 47 */
+    default_interrupt_handler, //0,                                       /* 16 + 48 */
+    default_interrupt_handler, //0,                                       /* 16 + 49 */
+    default_interrupt_handler, //PDS_WAKEUP_IRQHandler_Wrapper,           /* 16 + 50 */
+    default_interrupt_handler, //HBN_OUT0_IRQHandler_Wrapper,             /* 16 + 51 */
+    default_interrupt_handler, //HBN_OUT1_IRQHandler_Wrapper,             /* 16 + 52 */
+    default_interrupt_handler, //BOR_IRQHandler_Wrapper,                  /* 16 + 53 */
+    default_interrupt_handler, //WIFI_IRQHandler_Wrapper,                 /* 16 + 54 */
+    default_interrupt_handler, //BZ_PHY_IRQHandler_Wrapper,               /* 16 + 55 */
+    default_interrupt_handler, //BLE_IRQHandler_Wrapper,                  /* 16 + 56 */
+    default_interrupt_handler, //MAC_TXRX_TIMER_IRQHandler_Wrapper,       /* 16 + 57 */
+    default_interrupt_handler, //MAC_TXRX_MISC_IRQHandler_Wrapper,        /* 16 + 58 */
+    default_interrupt_handler, //MAC_RX_TRG_IRQHandler_Wrapper,           /* 16 + 59 */
+    default_interrupt_handler, //MAC_TX_TRG_IRQHandler_Wrapper,           /* 16 + 60 */
+    default_interrupt_handler, //MAC_GEN_IRQHandler_Wrapper,              /* 16 + 61 */
+    default_interrupt_handler, //MAC_PORT_TRG_IRQHandler_Wrapper,         /* 16 + 62 */
+    default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper,      /* 16 + 63 */
+};
+
+void exception_entry(uintptr_t *regs)
+{
+    unsigned long cause;
+    unsigned long epc;
+    unsigned long tval;
+
+    printf("exception_entry\r\n");
+
+    cause = READ_CSR(CSR_MCAUSE);
+    printf("mcause=%08x\r\n", (int)cause);
+    epc = READ_CSR(CSR_MEPC);
+    printf("mepc:%08x\r\n", (int)epc);
+    tval = READ_CSR(CSR_MTVAL);
+    printf("mtval:%08x\r\n", (int)tval);
+
+    cause = (cause & 0x3ff);
+
+    const char *mcause_str[] = {
+        "Instruction address misaligned",
+        "Instruction access fault",
+        "Illegal instruction",
+        "Breakpoint",
+        "Load address misaligned",
+        "Load access fault",
+        "Store/AMO address misaligned",
+        "Store/AMO access fault",
+        "Environment call from U-mode",
+        "Environment call from S-mode",
+        "RSVD",
+        "Environment call from M-mode",
+        "Instruction page fault",
+        "Load page fault",
+        "RSVD",
+        "Store/AMO page fault"
+    };
+
+    printf("%s\r\n", mcause_str[cause & 0xf]);
+// clang-format off
+#ifdef CONFIG_TRAP_DUMP_ALL_REGS
+    printf("ra = 0x%08x  ", regs[REG_RA]); printf("sp = 0x%08x  ", regs[REG_SP]); printf("gp = 0x%08x  ", regs[REG_GP]);
+    printf("tp = 0x%08x  ", regs[REG_TP]); printf("\n\r");
+
+    printf("t0 = 0x%08x  ", regs[REG_T0]); printf("t1 = 0x%08x  ", regs[REG_T1]); printf("t2 = 0x%08x  ", regs[REG_T2]);
+    printf("t3 = 0x%08x  ", regs[REG_T3]); printf("\n\r");
+    printf("t4 = 0x%08x  ", regs[REG_T4]); printf("t5 = 0x%08x  ", regs[REG_T5]); printf("t6 = 0x%08x  ", regs[REG_T6]);
+    printf("\n\r");
+
+    printf("a0 = 0x%08x  ", regs[REG_A0]); printf("a1 = 0x%08x  ", regs[REG_A1]); printf("a2 = 0x%08x  ", regs[REG_A2]);
+    printf("a3 = 0x%08x  ", regs[REG_A3]); printf("\n\r");
+    printf("a4 = 0x%08x  ", regs[REG_A4]); printf("a5 = 0x%08x  ", regs[REG_A5]); printf("a6 = 0x%08x  ", regs[REG_A6]);
+    printf("a7 = 0x%08x  ", regs[REG_A7]); printf("\n\r");
+
+    printf("s0 = 0x%08x  ", regs[REG_S0]); printf("s1 = 0x%08x  ", regs[REG_S1]); printf("s2 = 0x%08x  ", regs[REG_S2]);
+    printf("s3 = 0x%08x  ", regs[REG_S3]); printf("\n\r");
+    printf("s4 = 0x%08x  ", regs[REG_S4]); printf("s5 = 0x%08x  ", regs[REG_S5]); printf("s6 = 0x%08x  ", regs[REG_S6]);
+    printf("s7 = 0x%08x  ", regs[REG_S7]); printf("\n\r");
+    printf("s8 = 0x%08x  ", regs[REG_S8]); printf("s9 = 0x%08x  ", regs[REG_S9]); printf("s10 = 0x%08x ", regs[REG_S10]);
+    printf("s11 = 0x%08x  ", regs[REG_S11]); printf("\n\r");
+#endif
+    // clang-format on
+    if ((cause == 8) || (cause == 11)) {
+        epc += 4;
+        WRITE_CSR(CSR_MEPC, epc);
+    } else {
+        while (1) {
+        }
+    }
+}
+
+void interrupt_entry(void)
+{
+    irq_callback handler;
+    void *arg;
+    volatile uint32_t mcause = 0UL;
+    uint32_t irq_num;
+
+    mcause = READ_CSR(CSR_MCAUSE);
+    irq_num = mcause & 0x3FF;
+
+    if (irq_num < CONFIG_IRQ_NUM) {
+        handler = g_irqvector[irq_num].handler;
+        arg = g_irqvector[irq_num].arg;
+        if (handler) {
+            handler(irq_num, arg);
+        } else {
+        }
+    } else {
+    }
+}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/irq_ctx.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/irq_ctx.h
old mode 100644
new mode 100755
similarity index 97%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/irq_ctx.h
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/irq_ctx.h
index c27df38306..4c9bc7dd7d
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/irq_ctx.h
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/irq_ctx.h
@@ -11,8 +11,6 @@
 
 /* Configuration ************************************************************/
 
-#define CONFIG_ARCH_FPU
-
 /* Processor PC */
 
 #define REG_EPC_NDX 0
@@ -350,6 +348,7 @@
 #define REG_T5 REG_X30
 #define REG_T6 REG_X31
 
+#ifndef __ASSEMBLY__
 /****************************************************************************
  * Public Types
  ****************************************************************************/
@@ -361,5 +360,13 @@
 /****************************************************************************
  * Public Function Prototypes
  ****************************************************************************/
+# ifdef CONFIG_ARCH_FPU
+    extern void riscv_savefpu(uintptr_t *regs);
+    extern void riscv_restorefpu(uintptr_t *regs);
+# else
+    void riscv_savefpu(uintptr_t *regs) {};
+    void riscv_restorefpu(uintptr_t *regs) {};
+# endif
+#endif /* !__ASSEMBLY__ */
 
 #endif /* __IRQ_CTX_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/riscv_fpu.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/riscv_fpu.S
new file mode 100755
index 0000000000..a88e6230d4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/riscv_fpu.S
@@ -0,0 +1,221 @@
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+#if defined(CONFIG_ARCH_FPU)
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Symbols
+ ************************************************************************************/
+
+	.globl		riscv_fpuconfig
+	.globl		riscv_savefpu
+	.globl		riscv_savefpu_force
+	.globl		riscv_restorefpu
+
+	.file		"riscv_fpu.S"
+
+#define FS_MASK		0x6000
+#define FS_OFF		0x0000
+#define FS_INITIAL	0x2000
+#define FS_CLEAN	0x4000
+#define FS_DIRTY	0x6000
+
+#if defined(CONFIG_ARCH_DPFPU)
+#  define FLOAD		fld
+#  define FSTORE	fsd
+#  define LOAD		ld
+#  define STORE		sd
+#elif defined(CONFIG_ARCH_QPFPU)
+#  define FLOAD		flq
+#  define FSTORE	fsq
+#else
+#  define FLOAD		flw
+#  define FSTORE	fsw
+#  define LOAD		lw
+#  define STORE		sw
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: riscv_fpuconfig
+ *
+ * Description:
+ *   init fpu
+ *
+ * C Function Prototype:
+ *   void riscv_fpuconfig(void);
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   This function does not return anything explicitly.
+ *
+ ************************************************************************************/
+
+	.type		riscv_fpuconfig, function
+
+riscv_fpuconfig:
+	li			a0, FS_INITIAL
+	csrs		mstatus, a0
+	csrwi		fcsr, 0
+	ret
+
+/************************************************************************************
+ * Name: riscv_savefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in A0), save the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void riscv_savefpu(uintptr_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area in which to save the floating point
+ *     registers
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+	.type		riscv_savefpu, function
+
+riscv_savefpu:
+	LOAD	t0, REG_INT_CTX(a0)
+	li		t1, FS_MASK
+	and		t2, t0, t1
+	li		t1, FS_DIRTY
+	bne		t2, t1, 1f
+	li		t1, ~FS_MASK
+	and		t0, t0, t1
+	li		t1, FS_CLEAN
+	or		t0, t0, t1
+	STORE	t0, REG_INT_CTX(a0)
+
+	/* Store all floating point registers */
+riscv_savefpu_force:
+
+	FSTORE		f0,  REG_F0(a0)
+	FSTORE		f1,  REG_F1(a0)
+	FSTORE		f2,  REG_F2(a0)
+	FSTORE		f3,  REG_F3(a0)
+	FSTORE		f4,  REG_F4(a0)
+	FSTORE		f5,  REG_F5(a0)
+	FSTORE		f6,  REG_F6(a0)
+	FSTORE		f7,  REG_F7(a0)
+	FSTORE		f8,  REG_F8(a0)
+	FSTORE		f9,  REG_F9(a0)
+	FSTORE		f10, REG_F10(a0)
+	FSTORE		f11, REG_F11(a0)
+	FSTORE		f12, REG_F12(a0)
+	FSTORE		f13, REG_F13(a0)
+	FSTORE		f14, REG_F14(a0)
+	FSTORE		f15, REG_F15(a0)
+	FSTORE		f16, REG_F16(a0)
+	FSTORE		f17, REG_F17(a0)
+	FSTORE		f18, REG_F18(a0)
+	FSTORE		f19, REG_F19(a0)
+	FSTORE		f20, REG_F20(a0)
+	FSTORE		f21, REG_F21(a0)
+	FSTORE		f22, REG_F22(a0)
+	FSTORE		f23, REG_F23(a0)
+	FSTORE		f24, REG_F24(a0)
+	FSTORE		f25, REG_F25(a0)
+	FSTORE		f26, REG_F26(a0)
+	FSTORE		f27, REG_F27(a0)
+	FSTORE		f28, REG_F28(a0)
+	FSTORE		f29, REG_F29(a0)
+	FSTORE		f30, REG_F30(a0)
+	FSTORE		f31, REG_F31(a0)
+
+	frcsr		t0
+	STORE		t0, REG_FCSR(a0)
+
+1:
+	ret
+
+/************************************************************************************
+ * Name: riscv_restorefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in A0), restore the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void riscv_restorefpu(const uintptr_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area containing the floating point
+ *     registers.
+ *
+ * Returned Value:
+ *   This function does not return anything explicitly.  However, it is called from
+ *   interrupt level assembly logic that assumes that r0 is preserved.
+ *
+ ************************************************************************************/
+
+	.type		riscv_restorefpu, function
+
+riscv_restorefpu:
+	LOAD	t0, REG_INT_CTX(a0)
+	li		t1, FS_MASK
+	and		t2, t0, t1
+	li		t1, FS_INITIAL
+	ble		t2, t1, 1f
+
+	/* Load all floating point registers */
+
+	FLOAD		f0, REG_F0(a0)
+	FLOAD		f1, REG_F1(a0)
+	FLOAD		f2, REG_F2(a0)
+	FLOAD		f3, REG_F3(a0)
+	FLOAD		f4, REG_F4(a0)
+	FLOAD		f5, REG_F5(a0)
+	FLOAD		f6, REG_F6(a0)
+	FLOAD		f7, REG_F7(a0)
+	FLOAD		f8, REG_F8(a0)
+	FLOAD		f9, REG_F9(a0)
+	FLOAD		f10, REG_F10(a0)
+	FLOAD		f11, REG_F11(a0)
+	FLOAD		f12, REG_F12(a0)
+	FLOAD		f13, REG_F13(a0)
+	FLOAD		f14, REG_F14(a0)
+	FLOAD		f15, REG_F15(a0)
+	FLOAD		f16, REG_F16(a0)
+	FLOAD		f17, REG_F17(a0)
+	FLOAD		f18, REG_F18(a0)
+	FLOAD		f19, REG_F19(a0)
+	FLOAD		f20, REG_F20(a0)
+	FLOAD		f21, REG_F21(a0)
+	FLOAD		f22, REG_F22(a0)
+	FLOAD		f23, REG_F23(a0)
+	FLOAD		f24, REG_F24(a0)
+	FLOAD		f25, REG_F25(a0)
+	FLOAD		f26, REG_F26(a0)
+	FLOAD		f27, REG_F27(a0)
+	FLOAD		f28, REG_F28(a0)
+	FLOAD		f29, REG_F29(a0)
+	FLOAD		f30, REG_F30(a0)
+	FLOAD		f31, REG_F31(a0)
+
+	/* Store the floating point control and status register */
+
+	LOAD		t0, REG_FCSR(a0)
+	fscsr		t0
+
+1:
+	ret
+
+#endif /* CONFIG_ARCH_FPU */
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/startup.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start.S
old mode 100644
new mode 100755
similarity index 59%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/startup.S
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start.S
index 6748461791..2e56400942
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/startup.S
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start.S
@@ -2,50 +2,44 @@
  * Copyright (C) 2016-2020 Bouffalo Lab
  */
 
-_start:
-    .text
+    .section .init
     .align  2
-    .globl  Reset_Handler
-    .type   Reset_Handler, %function
-Reset_Handler:
+    .globl  __start
+    .type   __start, %function
+__start:
 .option push
 .option norelax
     la      gp, __global_pointer$
 .option pop
-    /* disable global IRQ */
     csrci   mstatus, 8
-    csrw    mcycle, zero
-    csrw    minstret, zero
 
-    la      a0, Default_Handler
+    /* mtvec: for all exceptions and non-vector mode IRQs */
+    la      a0, default_trap_handler
     ori     a0, a0, 3
     csrw    mtvec, a0
 
+    /* mtvt: for all vector mode IRQs */
     la      a0, __Vectors
     csrw    mtvt, a0
-
+    
     .weak __StackTop
     la      sp, __StackTop
     csrw    mscratch, sp
 
     /* Load data section removed */
-    
+
     /* Clear bss section removed */
 
-#ifndef __NO_SYSTEM_INIT
-    jal     System_Init
-#endif
-  
+    jal     SystemInit
+
     /* start load code to itcm like. */
     jal     start_load
 
-#ifndef __NO_BOARD_INIT
     jal     System_Post_Init
-#endif
 
-    jal     main
+    jal     entry
 
-    .size   Reset_Handler, . - Reset_Handler
+    .size   __start, . - __start
 
 __exit:
     j      __exit
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start_load.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start_load.c
new file mode 100755
index 0000000000..f9715fccac
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/start_load.c
@@ -0,0 +1,92 @@
+#include 
+
+#define __STARTUP_CLEAR_BSS 1
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __itcm_load_addr;
+extern uint32_t __dtcm_load_addr;
+extern uint32_t __system_ram_load_addr;
+extern uint32_t __ram_load_addr;
+extern uint32_t __nocache_ram_load_addr;
+
+extern uint32_t __text_code_start__;
+extern uint32_t __text_code_end__;
+extern uint32_t __tcm_code_start__;
+extern uint32_t __tcm_code_end__;
+extern uint32_t __tcm_data_start__;
+extern uint32_t __tcm_data_end__;
+extern uint32_t __ram_data_start__;
+extern uint32_t __ram_data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __noinit_data_start__;
+extern uint32_t __noinit_data_end__;
+extern uint32_t __nocache_ram_data_start__;
+extern uint32_t __nocache_ram_data_end__;
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+//extern uint32_t __copy_table_start__;
+//extern uint32_t __copy_table_end__;
+//extern uint32_t __zero_table_start__;
+//extern uint32_t __zero_table_end__;
+
+void start_load(void)
+{
+    uint32_t *pSrc, *pDest;
+    uint32_t *pTable __attribute__((unused));
+
+    /* Copy ITCM code */
+    pSrc = &__itcm_load_addr;
+    pDest = &__tcm_code_start__;
+
+    for (; pDest < &__tcm_code_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* Copy DTCM code */
+    pSrc = &__dtcm_load_addr;
+    pDest = &__tcm_data_start__;
+
+    for (; pDest < &__tcm_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* BF Add OCARAM data copy */
+    pSrc = &__ram_load_addr;
+    pDest = &__ram_data_start__;
+
+    for (; pDest < &__ram_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* BF Add no cache ram data copy */
+    pSrc = &__nocache_ram_load_addr;
+    pDest = &__nocache_ram_data_start__;
+
+    for (; pDest < &__nocache_ram_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+#ifdef __STARTUP_CLEAR_BSS
+    /*  Single BSS section scheme.
+	 *
+	 *  The BSS section is specified by following symbols
+	 *    __bss_start__: start of the BSS section.
+	 *    __bss_end__: end of the BSS section.
+	 *
+	 *  Both addresses must be aligned to 4 bytes boundary.
+	 */
+    pDest = &__bss_start__;
+
+    for (; pDest < &__bss_end__;) {
+        *pDest++ = 0ul;
+    }
+
+#endif
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/system_bl808.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/system_bl808.c
new file mode 100755
index 0000000000..3daccc9c9b
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/system_bl808.c
@@ -0,0 +1,24 @@
+#include "bl808.h"
+
+void SystemInit(void)
+{
+    uint32_t i = 0;
+
+    /* get interrupt level from info */
+    CLIC->CLICCFG = (((CLIC->CLICINFO & CLIC_INFO_CLICINTCTLBITS_Msk) >> CLIC_INFO_CLICINTCTLBITS_Pos) << CLIC_CLICCFG_NLBIT_Pos);
+
+    /* Every interrupt should be clear by software*/
+    for (i = 0; i < IRQn_LAST; i++) {
+        CLIC->CLICINT[i].IE = 0;
+        CLIC->CLICINT[i].IP = 0;
+        CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
+    }
+
+    CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
+}
+
+void System_Post_Init(void)
+{
+    /* global IRQ enable */
+    __enable_irq();
+}
\ No newline at end of file
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/vectors.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/vector.S
old mode 100644
new mode 100755
similarity index 53%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/vectors.S
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/vector.S
index d702b851ba..2cbe3bed5c
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/lp/source/GCC/vectors.S
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/lp/vector.S
@@ -34,14 +34,11 @@ g_trap_sp:
 irq_nested_level:
 .long 0
 
-.text
-
-#ifndef CONFIG_OS_SUPPORT
     .align  2
-    .global Default_IRQHandler
-    .weak   Default_IRQHandler
-    .type   Default_IRQHandler, %function
-Default_IRQHandler:
+    .global default_interrupt_handler
+    .weak   default_interrupt_handler
+    .type   default_interrupt_handler, %function
+default_interrupt_handler:
     addi    sp, sp, -48
     sw      t0, 4(sp)
     sw      t1, 8(sp)
@@ -64,9 +61,7 @@ Default_IRQHandler:
     csrw    mscratch, t1
     slli    t1, t1, 2
 
-    la      t0, g_irqvector
-    add     t0, t0, t1
-    lw      t2, (t0)
+    la      t2, interrupt_entry
     jalr    t2
 
     /* deal N+32 irq */
@@ -74,9 +69,7 @@ Default_IRQHandler:
     add     t1, t1,32
     slli    t1, t1, 2
     
-    la      t0, g_irqvector
-    add     t0, t0, t1
-    lw      t2, (t0)
+    la      t2, interrupt_entry
     jalr    t2
 
     csrc    mstatus, 8
@@ -108,121 +101,6 @@ Default_IRQHandler:
 
     addi    sp, sp, 48
     mret
-#else
-    .align  2
-    .global Default_IRQHandler
-    .weak   Default_IRQHandler
-    .type   Default_IRQHandler, %function
-Default_IRQHandler:
-    addi    sp, sp, -8
-    sw      t0, 0(sp)
-    sw      t1, 4(sp)
-
-    la      t0, irq_nested_level
-    lw      t1, (t0)
-    addi    t1, t1, 1
-    sw      t1, (t0)
-    li      t0, 1
-    bgt     t1, t0, .Lnested1
-
-    lw      t0, 0(sp)
-    lw      t1, 4(sp)
-    addi    sp, sp, 8
-
-    csrw    mscratch, sp
-    la      sp, __StackTop
-    j       .Lnested2
-.Lnested1:
-    lw      t0, 0(sp)
-    lw      t1, 4(sp)
-    addi    sp, sp, 8
-.Lnested2:
-    addi    sp, sp, -48
-    sw      t0, 4(sp)
-    sw      t1, 8(sp)
-    csrr    t0, mepc
-    csrr    t1, mcause
-    sw      t1, 40(sp)
-    sw      t0, 44(sp)
-
-    csrs    mstatus, 8
-
-    sw      ra, 0(sp)
-    sw      t2, 12(sp)
-    sw      a0, 16(sp)
-    sw      a1, 20(sp)
-    sw      a2, 24(sp)
-    sw      a3, 28(sp)
-    sw      a4, 32(sp)
-    sw      a5, 36(sp)
-
-    andi    t1, t1, 0x3FF
-    slli    t1, t1, 2
-
-    la      t0, g_irqvector
-    add     t0, t0, t1
-    lw      t2, (t0)
-    jalr    t2
-
-    csrc    mstatus, 8
-
-    lw      a1, 40(sp)
-    andi    a0, a1, 0x3FF
-
-    /* clear pending */
-    li      a2, 0xE000E100
-    add     a2, a2, a0
-    lb      a3, 0(a2)
-    li      a4, 1
-    not     a4, a4
-    and     a5, a4, a3
-    sb      a5, 0(a2)
-
-    la      t0, irq_nested_level
-    lw      t1, (t0)
-    addi    t1, t1, -1
-    sw      t1, (t0)
-    bgt     t1, zero, .Lnested3
-
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
-    csrw    mcause, a1
-    lw      t0, 44(sp)
-    csrw    mepc, t0
-    lw      ra, 0(sp)
-    lw      t0, 4(sp)
-    lw      t1, 8(sp)
-    lw      t2, 12(sp)
-    lw      a0, 16(sp)
-    lw      a1, 20(sp)
-    lw      a2, 24(sp)
-    lw      a3, 28(sp)
-    lw      a4, 32(sp)
-    lw      a5, 36(sp)
-
-    csrr    sp, mscratch
-    mret
-
-.Lnested3:
-    li      t0, MSTATUS_PRV1
-    csrs    mstatus, t0
-    csrw    mcause, a1
-    lw      t0, 44(sp)
-    csrw    mepc, t0
-    lw      ra, 0(sp)
-    lw      t0, 4(sp)
-    lw      t1, 8(sp)
-    lw      t2, 12(sp)
-    lw      a0, 16(sp)
-    lw      a1, 20(sp)
-    lw      a2, 24(sp)
-    lw      a3, 28(sp)
-    lw      a4, 32(sp)
-    lw      a5, 36(sp)
-
-    addi    sp, sp, 48
-    mret
-#endif
 
 /******************************************************************************
  * Functions:
@@ -230,8 +108,9 @@ Default_IRQHandler:
  * default exception handler
  ******************************************************************************/
     .align  2
-    .global trap
-    .type   trap, %function
+    .global default_trap_handler
+    .type   default_trap_handler, %function
+default_trap_handler:
 trap:
     /* Check for interrupt */
     addi    sp, sp, -4
@@ -268,7 +147,7 @@ trap:
     mv      sp, a0
     sw      t0, REG_X5(sp)
 
-    jal     trap_c
+    jal     exception_entry
 
     lw      t0, REG_INT_CTX(sp)
     csrw    mstatus, t0
@@ -296,23 +175,6 @@ trap:
 .Lirq:
     lw      t0, 0x0(sp)
     addi    sp, sp, 4
-    j       Default_IRQHandler
+    j       default_interrupt_handler
 
-    .align  6
-    .weak   Default_Handler
-    .global Default_Handler
-    .type   Default_Handler, %function
-Default_Handler:
-    j      trap
-    .size   Default_Handler, . - Default_Handler
-
-/*    Macro to define default handlers. Default handler
- *    will be weak symbol and just dead loops. They can be
- *    overwritten by other handlers */
-    .macro  def_irq_handler handler_name
-    .weak   \handler_name
-    .globl  \handler_name
-    .set    \handler_name, Default_Handler
-    .endm
-
-    def_irq_handler Mtspend_Handler
+    .size   default_trap_handler, . - default_trap_handler
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c
new file mode 100755
index 0000000000..b48bed4759
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/interrupt.c
@@ -0,0 +1,185 @@
+/**
+ * @file interrupt.c
+ * @brief
+ *
+ * Copyright (c) 2021 Bouffalolab team
+ *
+ * Licensed to the Apache Software Foundation (ASF) under one or more
+ * contributor license agreements.  See the NOTICE file distributed with
+ * this work for additional information regarding copyright ownership.  The
+ * ASF licenses this file to you under the Apache License, Version 2.0 (the
+ * "License"); you may not use this file except in compliance with the
+ * License.  You may obtain a copy of the License at
+ *
+ *   http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.  See the
+ * License for the specific language governing permissions and limitations
+ * under the License.
+ *
+ */
+#include "bflb_core.h"
+#include 
+#include "irq_ctx.h"
+
+typedef void (*pFunc)(void);
+
+struct bflb_irq_info_s g_irqvector[CONFIG_IRQ_NUM];
+
+extern void default_trap_handler(void);
+extern void default_interrupt_handler(void);
+
+const pFunc __Vectors[] __attribute__((section(".vector"), aligned(64))) = {
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*  3: M-mode Soft IRQ   */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*  7: M-mode Timer IRQ  */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+    default_interrupt_handler, /*         */
+
+    default_interrupt_handler, //BMX_ERR_IRQHandler_Wrapper,              /* 16 +  0 */
+    default_interrupt_handler, //BMX_TO_IRQHandler_Wrapper,               /* 16 +  1 */
+    default_interrupt_handler, //L1C_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  2 */
+    default_interrupt_handler, //L1C_BMX_TO_IRQHandler_Wrapper,           /* 16 +  3 */
+    default_interrupt_handler, //SEC_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  4 */
+    default_interrupt_handler, //RF_TOP_INT0_IRQHandler_Wrapper,          /* 16 +  5 */
+    default_interrupt_handler, //RF_TOP_INT1_IRQHandler_Wrapper,          /* 16 +  6 */
+    default_interrupt_handler, //SDIO_IRQHandler_Wrapper,                 /* 16 +  7 */
+    default_interrupt_handler, //DMA_BMX_ERR_IRQHandler_Wrapper,          /* 16 +  8 */
+    default_interrupt_handler, //SEC_GMAC_IRQHandler_Wrapper,             /* 16 +  9 */
+    default_interrupt_handler, //SEC_CDET_IRQHandler_Wrapper,             /* 16 + 10 */
+    default_interrupt_handler, //SEC_PKA_IRQHandler_Wrapper,              /* 16 + 11 */
+    default_interrupt_handler, //SEC_TRNG_IRQHandler_Wrapper,             /* 16 + 12 */
+    default_interrupt_handler, //SEC_AES_IRQHandler_Wrapper,              /* 16 + 13 */
+    default_interrupt_handler, //SEC_SHA_IRQHandler_Wrapper,              /* 16 + 14 */
+    default_interrupt_handler, //DMA_ALL_IRQHandler_Wrapper,              /* 16 + 15 */
+    default_interrupt_handler, //0,                                       /* 16 + 16 */
+    default_interrupt_handler, //0,                                       /* 16 + 17 */
+    default_interrupt_handler, //0,                                       /* 16 + 18 */
+    default_interrupt_handler, //IRTX_IRQHandler_Wrapper,                 /* 16 + 19 */
+    default_interrupt_handler, //IRRX_IRQHandler_Wrapper,                 /* 16 + 20 */
+    default_interrupt_handler, //0,                                       /* 16 + 21 */
+    default_interrupt_handler, //0,                                       /* 16 + 22 */
+    default_interrupt_handler, //SF_CTRL_IRQHandler_Wrapper,              /* 16 + 23 */
+    default_interrupt_handler, //0,                                       /* 16 + 24 */
+    default_interrupt_handler, //GPADC_DMA_IRQHandler_Wrapper,            /* 16 + 25 */
+    default_interrupt_handler, //EFUSE_IRQHandler_Wrapper,                /* 16 + 26 */
+    default_interrupt_handler, //SPI_IRQHandler_Wrapper,                  /* 16 + 27 */
+    default_interrupt_handler, //0,                                       /* 16 + 28 */
+    default_interrupt_handler, //UART0_IRQHandler_Wrapper,                /* 16 + 29 */
+    default_interrupt_handler, //UART1_IRQHandler_Wrapper,                /* 16 + 30 */
+    default_interrupt_handler, //0,                                       /* 16 + 31 */
+    default_interrupt_handler, //I2C_IRQHandler_Wrapper,                  /* 16 + 32 */
+    default_interrupt_handler, //0,                                       /* 16 + 33 */
+    default_interrupt_handler, //PWM_IRQHandler_Wrapper,                  /* 16 + 34 */
+    default_interrupt_handler, //0,                                       /* 16 + 35 */
+    default_interrupt_handler, //TIMER_CH0_IRQHandler_Wrapper,            /* 16 + 36 */
+    default_interrupt_handler, //TIMER_CH1_IRQHandler_Wrapper,            /* 16 + 37 */
+    default_interrupt_handler, //TIMER_WDT_IRQHandler_Wrapper,            /* 16 + 38 */
+    default_interrupt_handler, //0,                                       /* 16 + 39 */
+    default_interrupt_handler, //0,                                       /* 16 + 40 */
+    default_interrupt_handler, //0,                                       /* 16 + 41 */
+    default_interrupt_handler, //0,                                       /* 16 + 42 */
+    default_interrupt_handler, //0,                                       /* 16 + 43 */
+    default_interrupt_handler, //GPIO_INT0_IRQHandler_Wrapper,            /* 16 + 44 */
+    default_interrupt_handler, //0,                                       /* 16 + 45 */
+    default_interrupt_handler, //0,                                       /* 16 + 46 */
+    default_interrupt_handler, //0,                                       /* 16 + 47 */
+    default_interrupt_handler, //0,                                       /* 16 + 48 */
+    default_interrupt_handler, //0,                                       /* 16 + 49 */
+    default_interrupt_handler, //PDS_WAKEUP_IRQHandler_Wrapper,           /* 16 + 50 */
+    default_interrupt_handler, //HBN_OUT0_IRQHandler_Wrapper,             /* 16 + 51 */
+    default_interrupt_handler, //HBN_OUT1_IRQHandler_Wrapper,             /* 16 + 52 */
+    default_interrupt_handler, //BOR_IRQHandler_Wrapper,                  /* 16 + 53 */
+    default_interrupt_handler, //WIFI_IRQHandler_Wrapper,                 /* 16 + 54 */
+    default_interrupt_handler, //BZ_PHY_IRQHandler_Wrapper,               /* 16 + 55 */
+    default_interrupt_handler, //BLE_IRQHandler_Wrapper,                  /* 16 + 56 */
+    default_interrupt_handler, //MAC_TXRX_TIMER_IRQHandler_Wrapper,       /* 16 + 57 */
+    default_interrupt_handler, //MAC_TXRX_MISC_IRQHandler_Wrapper,        /* 16 + 58 */
+    default_interrupt_handler, //MAC_RX_TRG_IRQHandler_Wrapper,           /* 16 + 59 */
+    default_interrupt_handler, //MAC_TX_TRG_IRQHandler_Wrapper,           /* 16 + 60 */
+    default_interrupt_handler, //MAC_GEN_IRQHandler_Wrapper,              /* 16 + 61 */
+    default_interrupt_handler, //MAC_PORT_TRG_IRQHandler_Wrapper,         /* 16 + 62 */
+    default_interrupt_handler, //WIFI_IPC_PUBLIC_IRQHandler_Wrapper,      /* 16 + 63 */
+};
+
+void exception_entry(uintptr_t *regs)
+{
+    unsigned long cause;
+    unsigned long epc;
+    unsigned long tval;
+
+    printf("exception_entry\r\n");
+
+    cause = READ_CSR(CSR_MCAUSE);
+    printf("mcause=%08x\r\n", (int)cause);
+    epc = READ_CSR(CSR_MEPC);
+    printf("mepc:%08x\r\n", (int)epc);
+    tval = READ_CSR(CSR_MTVAL);
+    printf("mtval:%08x\r\n", (int)tval);
+
+    cause = (cause & 0x3ff);
+
+#ifndef CONFIG_TRAP_DUMP_DISABLE
+    const char *mcause_str[] = {
+        "Instruction address misaligned",
+        "Instruction access fault",
+        "Illegal instruction",
+        "Breakpoint",
+        "Load address misaligned",
+        "Load access fault",
+        "Store/AMO address misaligned",
+        "Store/AMO access fault",
+        "Environment call from U-mode",
+        "Environment call from S-mode",
+        "RSVD",
+        "Environment call from M-mode",
+        "Instruction page fault",
+        "Load page fault",
+        "RSVD",
+        "Store/AMO page fault"
+    };
+
+    printf("%s\r\n", mcause_str[cause & 0xf]);
+#endif
+    if ((cause == 8) || (cause == 11)) {
+        epc += 4;
+        WRITE_CSR(CSR_MEPC, epc);
+    } else {
+        while (1) {
+        }
+    }
+}
+
+void interrupt_entry(void)
+{
+    irq_callback handler;
+    void *arg;
+    volatile uint32_t mcause = 0UL;
+    uint32_t irq_num;
+
+    mcause = READ_CSR(CSR_MCAUSE);
+    irq_num = mcause & 0x3FF;
+
+    if (irq_num < CONFIG_IRQ_NUM) {
+        handler = g_irqvector[irq_num].handler;
+        arg = g_irqvector[irq_num].arg;
+        if (handler) {
+            handler(irq_num, arg);
+        } else {
+        }
+    } else {
+    }
+}
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/irq_ctx.h b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/irq_ctx.h
new file mode 100755
index 0000000000..24fe032ab2
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/irq_ctx.h
@@ -0,0 +1,378 @@
+#ifndef __IRQ_CTX_H__
+#define __IRQ_CTX_H__
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#if defined(__riscv_flen)
+# define CONFIG_ARCH_FPU
+#else
+# undef CONFIG_ARCH_FPU
+#endif
+
+/* Processor PC */
+
+#define REG_EPC_NDX 0
+
+/* General pupose registers
+ * $0: Zero register does not need to be saved
+ * $1: ra (return address)
+ */
+
+#define REG_X1_NDX 1
+
+/* $2: Stack POinter
+ * $3: Global Pointer
+ * $4: Thread Pointer
+ */
+
+#define REG_X2_NDX 2
+#define REG_X3_NDX 3
+#define REG_X4_NDX 4
+
+/* $5-$7 = t0-t3: Temporary registers */
+
+#define REG_X5_NDX 5
+#define REG_X6_NDX 6
+#define REG_X7_NDX 7
+
+/* $8: s0 / fp Frame pointer */
+
+#define REG_X8_NDX 8
+
+/* $89 s1 Saved register */
+
+#define REG_X9_NDX 9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_X10_NDX 10
+#define REG_X11_NDX 11
+#define REG_X12_NDX 12
+#define REG_X13_NDX 13
+#define REG_X14_NDX 14
+#define REG_X15_NDX 15
+#define REG_X16_NDX 16
+#define REG_X17_NDX 17
+
+/* $18-$27 = s2-s11: Saved registers */
+
+#define REG_X18_NDX 18
+#define REG_X19_NDX 19
+#define REG_X20_NDX 20
+#define REG_X21_NDX 21
+#define REG_X22_NDX 22
+#define REG_X23_NDX 23
+#define REG_X24_NDX 24
+#define REG_X25_NDX 25
+#define REG_X26_NDX 26
+#define REG_X27_NDX 27
+
+/* $28-31 = t3-t6: Temporary (Volatile) registers */
+
+#define REG_X28_NDX 28
+#define REG_X29_NDX 29
+#define REG_X30_NDX 30
+#define REG_X31_NDX 31
+
+/* Interrupt Context register */
+
+#define REG_INT_CTX_NDX 32
+
+#define INT_XCPT_REGS 33
+
+#define INT_XCPT_SIZE (4 * INT_XCPT_REGS)
+
+#ifdef CONFIG_ARCH_FPU
+
+#define FPU_REG_SIZE 1 /* size in uint32_t */
+
+#define REG_F0_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 0)
+#define REG_F1_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 1)
+#define REG_F2_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 2)
+#define REG_F3_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 3)
+#define REG_F4_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 4)
+#define REG_F5_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 5)
+#define REG_F6_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 6)
+#define REG_F7_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 7)
+#define REG_F8_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 8)
+#define REG_F9_NDX   (INT_XCPT_REGS + FPU_REG_SIZE * 9)
+#define REG_F10_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 10)
+#define REG_F11_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 11)
+#define REG_F12_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 12)
+#define REG_F13_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 13)
+#define REG_F14_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 14)
+#define REG_F15_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 15)
+#define REG_F16_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 16)
+#define REG_F17_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 17)
+#define REG_F18_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 18)
+#define REG_F19_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 19)
+#define REG_F20_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 20)
+#define REG_F21_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 21)
+#define REG_F22_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 22)
+#define REG_F23_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 23)
+#define REG_F24_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 24)
+#define REG_F25_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 25)
+#define REG_F26_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 26)
+#define REG_F27_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 27)
+#define REG_F28_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 28)
+#define REG_F29_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 29)
+#define REG_F30_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 30)
+#define REG_F31_NDX  (INT_XCPT_REGS + FPU_REG_SIZE * 31)
+#define REG_FCSR_NDX (INT_XCPT_REGS + FPU_REG_SIZE * 32)
+
+#define FPU_XCPT_REGS (FPU_REG_SIZE * 33)
+#else
+#define FPU_XCPT_REGS 0
+#endif
+
+#define XCPTCONTEXT_REGS (INT_XCPT_REGS + FPU_XCPT_REGS)
+
+#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
+
+/* In assembly language, values have to be referenced as byte address
+ * offsets.  But in C, it is more convenient to reference registers as
+ * register save table offsets.
+ */
+
+#ifdef __ASSEMBLY__
+#define REG_EPC     (4 * REG_EPC_NDX)
+#define REG_X1      (4 * REG_X1_NDX)
+#define REG_X2      (4 * REG_X2_NDX)
+#define REG_X3      (4 * REG_X3_NDX)
+#define REG_X4      (4 * REG_X4_NDX)
+#define REG_X5      (4 * REG_X5_NDX)
+#define REG_X6      (4 * REG_X6_NDX)
+#define REG_X7      (4 * REG_X7_NDX)
+#define REG_X8      (4 * REG_X8_NDX)
+#define REG_X9      (4 * REG_X9_NDX)
+#define REG_X10     (4 * REG_X10_NDX)
+#define REG_X11     (4 * REG_X11_NDX)
+#define REG_X12     (4 * REG_X12_NDX)
+#define REG_X13     (4 * REG_X13_NDX)
+#define REG_X14     (4 * REG_X14_NDX)
+#define REG_X15     (4 * REG_X15_NDX)
+#define REG_X16     (4 * REG_X16_NDX)
+#define REG_X17     (4 * REG_X17_NDX)
+#define REG_X18     (4 * REG_X18_NDX)
+#define REG_X19     (4 * REG_X19_NDX)
+#define REG_X20     (4 * REG_X20_NDX)
+#define REG_X21     (4 * REG_X21_NDX)
+#define REG_X22     (4 * REG_X22_NDX)
+#define REG_X23     (4 * REG_X23_NDX)
+#define REG_X24     (4 * REG_X24_NDX)
+#define REG_X25     (4 * REG_X25_NDX)
+#define REG_X26     (4 * REG_X26_NDX)
+#define REG_X27     (4 * REG_X27_NDX)
+#define REG_X28     (4 * REG_X28_NDX)
+#define REG_X29     (4 * REG_X29_NDX)
+#define REG_X30     (4 * REG_X30_NDX)
+#define REG_X31     (4 * REG_X31_NDX)
+#define REG_INT_CTX (4 * REG_INT_CTX_NDX)
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0   (4 * REG_F0_NDX)
+#define REG_F1   (4 * REG_F1_NDX)
+#define REG_F2   (4 * REG_F2_NDX)
+#define REG_F3   (4 * REG_F3_NDX)
+#define REG_F4   (4 * REG_F4_NDX)
+#define REG_F5   (4 * REG_F5_NDX)
+#define REG_F6   (4 * REG_F6_NDX)
+#define REG_F7   (4 * REG_F7_NDX)
+#define REG_F8   (4 * REG_F8_NDX)
+#define REG_F9   (4 * REG_F9_NDX)
+#define REG_F10  (4 * REG_F10_NDX)
+#define REG_F11  (4 * REG_F11_NDX)
+#define REG_F12  (4 * REG_F12_NDX)
+#define REG_F13  (4 * REG_F13_NDX)
+#define REG_F14  (4 * REG_F14_NDX)
+#define REG_F15  (4 * REG_F15_NDX)
+#define REG_F16  (4 * REG_F16_NDX)
+#define REG_F17  (4 * REG_F17_NDX)
+#define REG_F18  (4 * REG_F18_NDX)
+#define REG_F19  (4 * REG_F19_NDX)
+#define REG_F20  (4 * REG_F20_NDX)
+#define REG_F21  (4 * REG_F21_NDX)
+#define REG_F22  (4 * REG_F22_NDX)
+#define REG_F23  (4 * REG_F23_NDX)
+#define REG_F24  (4 * REG_F24_NDX)
+#define REG_F25  (4 * REG_F25_NDX)
+#define REG_F26  (4 * REG_F26_NDX)
+#define REG_F27  (4 * REG_F27_NDX)
+#define REG_F28  (4 * REG_F28_NDX)
+#define REG_F29  (4 * REG_F29_NDX)
+#define REG_F30  (4 * REG_F30_NDX)
+#define REG_F31  (4 * REG_F31_NDX)
+#define REG_FCSR (4 * REG_FCSR_NDX)
+#endif
+
+#else
+#define REG_EPC     REG_EPC_NDX
+#define REG_X1      REG_X1_NDX
+#define REG_X2      REG_X2_NDX
+#define REG_X3      REG_X3_NDX
+#define REG_X4      REG_X4_NDX
+#define REG_X5      REG_X5_NDX
+#define REG_X6      REG_X6_NDX
+#define REG_X7      REG_X7_NDX
+#define REG_X8      REG_X8_NDX
+#define REG_X9      REG_X9_NDX
+#define REG_X10     REG_X10_NDX
+#define REG_X11     REG_X11_NDX
+#define REG_X12     REG_X12_NDX
+#define REG_X13     REG_X13_NDX
+#define REG_X14     REG_X14_NDX
+#define REG_X15     REG_X15_NDX
+#define REG_X16     REG_X16_NDX
+#define REG_X17     REG_X17_NDX
+#define REG_X18     REG_X18_NDX
+#define REG_X19     REG_X19_NDX
+#define REG_X20     REG_X20_NDX
+#define REG_X21     REG_X21_NDX
+#define REG_X22     REG_X22_NDX
+#define REG_X23     REG_X23_NDX
+#define REG_X24     REG_X24_NDX
+#define REG_X25     REG_X25_NDX
+#define REG_X26     REG_X26_NDX
+#define REG_X27     REG_X27_NDX
+#define REG_X28     REG_X28_NDX
+#define REG_X29     REG_X29_NDX
+#define REG_X30     REG_X30_NDX
+#define REG_X31     REG_X31_NDX
+#define REG_INT_CTX REG_INT_CTX_NDX
+
+#ifdef CONFIG_ARCH_FPU
+#define REG_F0   REG_F0_NDX
+#define REG_F1   REG_F1_NDX
+#define REG_F2   REG_F2_NDX
+#define REG_F3   REG_F3_NDX
+#define REG_F4   REG_F4_NDX
+#define REG_F5   REG_F5_NDX
+#define REG_F6   REG_F6_NDX
+#define REG_F7   REG_F7_NDX
+#define REG_F8   REG_F8_NDX
+#define REG_F9   REG_F9_NDX
+#define REG_F10  REG_F10_NDX
+#define REG_F11  REG_F11_NDX
+#define REG_F12  REG_F12_NDX
+#define REG_F13  REG_F13_NDX
+#define REG_F14  REG_F14_NDX
+#define REG_F15  REG_F15_NDX
+#define REG_F16  REG_F16_NDX
+#define REG_F17  REG_F17_NDX
+#define REG_F18  REG_F18_NDX
+#define REG_F19  REG_F19_NDX
+#define REG_F20  REG_F20_NDX
+#define REG_F21  REG_F21_NDX
+#define REG_F22  REG_F22_NDX
+#define REG_F23  REG_F23_NDX
+#define REG_F24  REG_F24_NDX
+#define REG_F25  REG_F25_NDX
+#define REG_F26  REG_F26_NDX
+#define REG_F27  REG_F27_NDX
+#define REG_F28  REG_F28_NDX
+#define REG_F29  REG_F29_NDX
+#define REG_F30  REG_F30_NDX
+#define REG_F31  REG_F31_NDX
+#define REG_FCSR REG_FCSR_NDX
+#endif
+
+#endif
+
+/* Now define more user friendly alternative name that can be used either
+ * in assembly or C contexts.
+ */
+
+/* $1 = ra: Return address */
+
+#define REG_RA REG_X1
+
+/* $2 = sp:  The value of the stack pointer on return from the exception */
+
+#define REG_SP REG_X2
+
+/* $3 = gp: Only needs to be saved under conditions where there are
+ * multiple, per-thread values for the GP.
+ */
+
+#define REG_GP REG_X3
+
+/* $4 = tp:  Thread Pointer */
+
+#define REG_TP REG_X4
+
+/* $5-$7 = t0-t2: Caller saved temporary registers */
+
+#define REG_T0 REG_X5
+#define REG_T1 REG_X6
+#define REG_T2 REG_X7
+
+/* $8 = either s0 or fp:  Depends if a frame pointer is used or not */
+
+#define REG_S0 REG_X8
+#define REG_FP REG_X8
+
+/* $9 = s1: Caller saved register */
+
+#define REG_S1 REG_X9
+
+/* $10-$17 = a0-a7: Argument registers */
+
+#define REG_A0 REG_X10
+#define REG_A1 REG_X11
+#define REG_A2 REG_X12
+#define REG_A3 REG_X13
+#define REG_A4 REG_X14
+#define REG_A5 REG_X15
+#define REG_A6 REG_X16
+#define REG_A7 REG_X17
+
+/* $18-$27 = s2-s11: Callee saved registers */
+
+#define REG_S2  REG_X18
+#define REG_S3  REG_X19
+#define REG_S4  REG_X20
+#define REG_S5  REG_X21
+#define REG_S6  REG_X22
+#define REG_S7  REG_X23
+#define REG_S8  REG_X24
+#define REG_S9  REG_X25
+#define REG_S10 REG_X26
+#define REG_S11 REG_X27
+
+/* $28-$31 = t3-t6: Caller saved temporary registers */
+
+#define REG_T3 REG_X28
+#define REG_T4 REG_X29
+#define REG_T5 REG_X30
+#define REG_T6 REG_X31
+
+#ifndef __ASSEMBLY__
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+# ifdef CONFIG_ARCH_FPU
+    extern void riscv_savefpu(uintptr_t *regs);
+    extern void riscv_restorefpu(uintptr_t *regs);
+# else
+    void riscv_savefpu(uintptr_t *regs) {};
+    void riscv_restorefpu(uintptr_t *regs) {};
+# endif
+#endif /* !__ASSEMBLY__ */
+
+#endif /* __IRQ_CTX_H__ */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/riscv_fpu.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/riscv_fpu.S
new file mode 100755
index 0000000000..a88e6230d4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/riscv_fpu.S
@@ -0,0 +1,221 @@
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+#if defined(CONFIG_ARCH_FPU)
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Symbols
+ ************************************************************************************/
+
+	.globl		riscv_fpuconfig
+	.globl		riscv_savefpu
+	.globl		riscv_savefpu_force
+	.globl		riscv_restorefpu
+
+	.file		"riscv_fpu.S"
+
+#define FS_MASK		0x6000
+#define FS_OFF		0x0000
+#define FS_INITIAL	0x2000
+#define FS_CLEAN	0x4000
+#define FS_DIRTY	0x6000
+
+#if defined(CONFIG_ARCH_DPFPU)
+#  define FLOAD		fld
+#  define FSTORE	fsd
+#  define LOAD		ld
+#  define STORE		sd
+#elif defined(CONFIG_ARCH_QPFPU)
+#  define FLOAD		flq
+#  define FSTORE	fsq
+#else
+#  define FLOAD		flw
+#  define FSTORE	fsw
+#  define LOAD		lw
+#  define STORE		sw
+#endif
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Name: riscv_fpuconfig
+ *
+ * Description:
+ *   init fpu
+ *
+ * C Function Prototype:
+ *   void riscv_fpuconfig(void);
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Value:
+ *   This function does not return anything explicitly.
+ *
+ ************************************************************************************/
+
+	.type		riscv_fpuconfig, function
+
+riscv_fpuconfig:
+	li			a0, FS_INITIAL
+	csrs		mstatus, a0
+	csrwi		fcsr, 0
+	ret
+
+/************************************************************************************
+ * Name: riscv_savefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in A0), save the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void riscv_savefpu(uintptr_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area in which to save the floating point
+ *     registers
+ *
+ * Returned Value:
+ *   None
+ *
+ ************************************************************************************/
+
+	.type		riscv_savefpu, function
+
+riscv_savefpu:
+	LOAD	t0, REG_INT_CTX(a0)
+	li		t1, FS_MASK
+	and		t2, t0, t1
+	li		t1, FS_DIRTY
+	bne		t2, t1, 1f
+	li		t1, ~FS_MASK
+	and		t0, t0, t1
+	li		t1, FS_CLEAN
+	or		t0, t0, t1
+	STORE	t0, REG_INT_CTX(a0)
+
+	/* Store all floating point registers */
+riscv_savefpu_force:
+
+	FSTORE		f0,  REG_F0(a0)
+	FSTORE		f1,  REG_F1(a0)
+	FSTORE		f2,  REG_F2(a0)
+	FSTORE		f3,  REG_F3(a0)
+	FSTORE		f4,  REG_F4(a0)
+	FSTORE		f5,  REG_F5(a0)
+	FSTORE		f6,  REG_F6(a0)
+	FSTORE		f7,  REG_F7(a0)
+	FSTORE		f8,  REG_F8(a0)
+	FSTORE		f9,  REG_F9(a0)
+	FSTORE		f10, REG_F10(a0)
+	FSTORE		f11, REG_F11(a0)
+	FSTORE		f12, REG_F12(a0)
+	FSTORE		f13, REG_F13(a0)
+	FSTORE		f14, REG_F14(a0)
+	FSTORE		f15, REG_F15(a0)
+	FSTORE		f16, REG_F16(a0)
+	FSTORE		f17, REG_F17(a0)
+	FSTORE		f18, REG_F18(a0)
+	FSTORE		f19, REG_F19(a0)
+	FSTORE		f20, REG_F20(a0)
+	FSTORE		f21, REG_F21(a0)
+	FSTORE		f22, REG_F22(a0)
+	FSTORE		f23, REG_F23(a0)
+	FSTORE		f24, REG_F24(a0)
+	FSTORE		f25, REG_F25(a0)
+	FSTORE		f26, REG_F26(a0)
+	FSTORE		f27, REG_F27(a0)
+	FSTORE		f28, REG_F28(a0)
+	FSTORE		f29, REG_F29(a0)
+	FSTORE		f30, REG_F30(a0)
+	FSTORE		f31, REG_F31(a0)
+
+	frcsr		t0
+	STORE		t0, REG_FCSR(a0)
+
+1:
+	ret
+
+/************************************************************************************
+ * Name: riscv_restorefpu
+ *
+ * Description:
+ *   Given the pointer to a register save area (in A0), restore the state of the
+ *   floating point registers.
+ *
+ * C Function Prototype:
+ *   void riscv_restorefpu(const uintptr_t *regs);
+ *
+ * Input Parameters:
+ *   regs - A pointer to the register save area containing the floating point
+ *     registers.
+ *
+ * Returned Value:
+ *   This function does not return anything explicitly.  However, it is called from
+ *   interrupt level assembly logic that assumes that r0 is preserved.
+ *
+ ************************************************************************************/
+
+	.type		riscv_restorefpu, function
+
+riscv_restorefpu:
+	LOAD	t0, REG_INT_CTX(a0)
+	li		t1, FS_MASK
+	and		t2, t0, t1
+	li		t1, FS_INITIAL
+	ble		t2, t1, 1f
+
+	/* Load all floating point registers */
+
+	FLOAD		f0, REG_F0(a0)
+	FLOAD		f1, REG_F1(a0)
+	FLOAD		f2, REG_F2(a0)
+	FLOAD		f3, REG_F3(a0)
+	FLOAD		f4, REG_F4(a0)
+	FLOAD		f5, REG_F5(a0)
+	FLOAD		f6, REG_F6(a0)
+	FLOAD		f7, REG_F7(a0)
+	FLOAD		f8, REG_F8(a0)
+	FLOAD		f9, REG_F9(a0)
+	FLOAD		f10, REG_F10(a0)
+	FLOAD		f11, REG_F11(a0)
+	FLOAD		f12, REG_F12(a0)
+	FLOAD		f13, REG_F13(a0)
+	FLOAD		f14, REG_F14(a0)
+	FLOAD		f15, REG_F15(a0)
+	FLOAD		f16, REG_F16(a0)
+	FLOAD		f17, REG_F17(a0)
+	FLOAD		f18, REG_F18(a0)
+	FLOAD		f19, REG_F19(a0)
+	FLOAD		f20, REG_F20(a0)
+	FLOAD		f21, REG_F21(a0)
+	FLOAD		f22, REG_F22(a0)
+	FLOAD		f23, REG_F23(a0)
+	FLOAD		f24, REG_F24(a0)
+	FLOAD		f25, REG_F25(a0)
+	FLOAD		f26, REG_F26(a0)
+	FLOAD		f27, REG_F27(a0)
+	FLOAD		f28, REG_F28(a0)
+	FLOAD		f29, REG_F29(a0)
+	FLOAD		f30, REG_F30(a0)
+	FLOAD		f31, REG_F31(a0)
+
+	/* Store the floating point control and status register */
+
+	LOAD		t0, REG_FCSR(a0)
+	fscsr		t0
+
+1:
+	ret
+
+#endif /* CONFIG_ARCH_FPU */
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start.S
new file mode 100755
index 0000000000..bea95f0dc6
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start.S
@@ -0,0 +1,57 @@
+/*
+ * Copyright (C) 2016-2020 Bouffalo Lab
+ */
+
+    .section .init
+    .align  2
+    .globl  __start
+    .type   __start, %function
+__start:
+.option push
+.option norelax
+    la      gp, __global_pointer$
+.option pop
+    csrci   mstatus, 8
+
+    /* mtvec: for all exceptions and non-vector mode IRQs */
+    la      a0, default_trap_handler
+    ori     a0, a0, 3
+    csrw    mtvec, a0
+
+    /* mtvt: for all vector mode IRQs */
+    la      a0, __Vectors
+    csrw    mtvt, a0
+
+#if defined(__riscv_flen)
+    /* FP: initial state */
+    csrr    t0, mstatus
+    li      t1, ~0x6000
+    and     t0, t0, t1
+    li      t1, 0x2000
+    or      t0, t0, t1
+    csrw    mstatus, t0
+    /* csrwi   fcsr, 0 */
+#endif
+
+    .weak __StackTop
+    la      sp, __StackTop
+    csrw    mscratch, sp
+
+    /* Load data section removed */
+
+    /* Clear bss section removed */
+
+    jal     SystemInit
+
+    /* start load code to itcm like. */
+    jal     start_load
+
+    jal     System_Post_Init
+
+    jal     entry
+
+    .size   __start, . - __start
+
+__exit:
+    j      __exit
+
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start_load.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start_load.c
new file mode 100755
index 0000000000..f9715fccac
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/start_load.c
@@ -0,0 +1,92 @@
+#include 
+
+#define __STARTUP_CLEAR_BSS 1
+
+/*----------------------------------------------------------------------------
+  Linker generated Symbols
+ *----------------------------------------------------------------------------*/
+extern uint32_t __itcm_load_addr;
+extern uint32_t __dtcm_load_addr;
+extern uint32_t __system_ram_load_addr;
+extern uint32_t __ram_load_addr;
+extern uint32_t __nocache_ram_load_addr;
+
+extern uint32_t __text_code_start__;
+extern uint32_t __text_code_end__;
+extern uint32_t __tcm_code_start__;
+extern uint32_t __tcm_code_end__;
+extern uint32_t __tcm_data_start__;
+extern uint32_t __tcm_data_end__;
+extern uint32_t __ram_data_start__;
+extern uint32_t __ram_data_end__;
+extern uint32_t __bss_start__;
+extern uint32_t __bss_end__;
+extern uint32_t __noinit_data_start__;
+extern uint32_t __noinit_data_end__;
+extern uint32_t __nocache_ram_data_start__;
+extern uint32_t __nocache_ram_data_end__;
+
+extern uint32_t __StackTop;
+extern uint32_t __StackLimit;
+extern uint32_t __HeapBase;
+extern uint32_t __HeapLimit;
+
+//extern uint32_t __copy_table_start__;
+//extern uint32_t __copy_table_end__;
+//extern uint32_t __zero_table_start__;
+//extern uint32_t __zero_table_end__;
+
+void start_load(void)
+{
+    uint32_t *pSrc, *pDest;
+    uint32_t *pTable __attribute__((unused));
+
+    /* Copy ITCM code */
+    pSrc = &__itcm_load_addr;
+    pDest = &__tcm_code_start__;
+
+    for (; pDest < &__tcm_code_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* Copy DTCM code */
+    pSrc = &__dtcm_load_addr;
+    pDest = &__tcm_data_start__;
+
+    for (; pDest < &__tcm_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* BF Add OCARAM data copy */
+    pSrc = &__ram_load_addr;
+    pDest = &__ram_data_start__;
+
+    for (; pDest < &__ram_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+    /* BF Add no cache ram data copy */
+    pSrc = &__nocache_ram_load_addr;
+    pDest = &__nocache_ram_data_start__;
+
+    for (; pDest < &__nocache_ram_data_end__;) {
+        *pDest++ = *pSrc++;
+    }
+
+#ifdef __STARTUP_CLEAR_BSS
+    /*  Single BSS section scheme.
+	 *
+	 *  The BSS section is specified by following symbols
+	 *    __bss_start__: start of the BSS section.
+	 *    __bss_end__: end of the BSS section.
+	 *
+	 *  Both addresses must be aligned to 4 bytes boundary.
+	 */
+    pDest = &__bss_start__;
+
+    for (; pDest < &__bss_end__;) {
+        *pDest++ = 0ul;
+    }
+
+#endif
+}
diff --git a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.c b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/system_bl808.c
old mode 100644
new mode 100755
similarity index 70%
rename from bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.c
rename to bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/system_bl808.c
index cc74156652..8c9e9dc63c
--- a/bsp/bl808/m0/libraries/platform/soc/bl808/bl808_e907_std/bl808_bsp_driver/startup/m0/source/system_bl808.c
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/system_bl808.c
@@ -1,34 +1,9 @@
-#include "bl808.h"
 #include "bl808_clock.h"
 #include "bl808_pds.h"
 #include "tzc_sec_reg.h"
 #include "rv_hart.h"
 #include "rv_pmp.h"
 
-/*----------------------------------------------------------------------------
-  Define clocks
- *----------------------------------------------------------------------------*/
-#define SYSTEM_CLOCK (32000000UL)
-
-/*----------------------------------------------------------------------------
-  System initialization function
- *----------------------------------------------------------------------------*/
-
-__WEAK__ void System_Environment_Init(void)
-{
-    csi_icache_enable();
-    csi_dcache_enable();
-
-    /* enable preload $ AMR for D$ */
-    __set_MHINT(0x000c);
-}
-
-void System_BOR_Init(void)
-{
-    //HBN_BOR_CFG_Type borCfg = {1/* pu_bor */, 0/* irq_bor_en */, 1/* bor_vth */, 1/* bor_sel */};
-    //HBN_Set_BOR_Cfg(&borCfg);
-}
-
 static void Tzc_Sec_PSRAMA_Access_Set_Not_Lock(uint8_t region, uint32_t startAddr, uint32_t endAddr, uint8_t group)
 {
     uint32_t tmpVal = 0;
@@ -78,7 +53,7 @@ static void pmp_init(void)
     rvpmp_init(pmp_entry_tab, sizeof(pmp_entry_tab) / sizeof(pmp_config_entry_t));
 }
 
-void System_Init(void)
+void SystemInit(void)
 {
     uint32_t i = 0;
 
@@ -104,8 +79,8 @@ void System_Init(void)
 
     /* Every interrupt should be clear by software*/
     for (i = 0; i < IRQn_LAST; i++) {
-        CLIC->CLICINT[i].IP = 0;
         CLIC->CLICINT[i].IE = 0;
+        CLIC->CLICINT[i].IP = 0;
         CLIC->CLICINT[i].ATTR = 1; /* use vector interrupt */
     }
 
@@ -113,59 +88,37 @@ void System_Init(void)
     /* tspend use positive interrupt */
     CLIC->CLICINT[MSOFT_IRQn].ATTR = 0x3;
 
-#ifndef CONFIG_OS_SUPPORT
-    /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack */
+    csi_dcache_enable();
+    csi_icache_enable();
+
+    /* enable preload $ AMR for D$ */
+    __set_MHINT(0x000c);
+
+    /* disable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop*/
     uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus |= (0x03 << 16);
+    mexstatus &= ~(0x3 << 16);
     __set_MEXSTATUS(mexstatus);
-#else
-    /* enable mexstatus SPUSHEN and SPSWAPEN for ipush/ipop and irq stack*/
-    uint32_t mexstatus = __get_MEXSTATUS();
-    mexstatus |= (0x3 << 16);
-    __set_MEXSTATUS(mexstatus);
-#endif
 
-    System_Environment_Init();
-
-    /* init bor for all platform */
-    System_BOR_Init();
-
-    GLB_Set_EM_Sel(GLB_WRAM160KB_EM0KB);
-}
-
-__WEAK__ void System_Post_Init(void)
-{
-    PDS_Power_On_MM_System();
+    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO0_GPIO11, 0);
+    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO12_GPIO23, 0);
+    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO24_GPIO35, 0);
+    GLB_UART_Sig_Swap_Set(GLB_UART_SIG_SWAP_GRP_GPIO36_GPIO45, 0);
 
     BL_WR_REG(GLB_BASE, GLB_UART_CFG1, 0xffffffff);
     BL_WR_REG(GLB_BASE, GLB_UART_CFG2, 0x0000ffff);
 
+    GLB_Set_EM_Sel(GLB_WRAM160KB_EM0KB);
+}
+
+void System_Post_Init(void)
+{
+    csi_dcache_clean();
+    csi_icache_invalid();
+
+    PDS_Power_On_MM_System();
     /* make D0 all ram avalable for mcu usage */
     GLB_Set_DSP_L2SRAM_Available_Size(3, 1, 1, 1);
 
-    System_Interrupt_Init();
-
-    CPU_Interrupt_Enable(MSOFT_IRQn);
-
     /* global IRQ enable */
     __enable_irq();
-}
-
-void System_NVIC_SetPriority(IRQn_Type IRQn, uint32_t PreemptPriority, uint32_t SubPriority)
-{
-    csi_vic_set_prio(IRQn, PreemptPriority);
-}
-
-int32_t drv_get_cpu_id(void)
-{
-    return __get_MHARTID();
-}
-
-int32_t drv_get_cpu_freq(int32_t idx)
-{
-    return 32 * 1000 * 1000UL;
-}
-
-#if defined(DUAL_CORE)
-extern void Reset_Handler(void);
-#endif
+}
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/vector.S b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/vector.S
new file mode 100755
index 0000000000..8b605245d1
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/drivers/soc/bl808/std/startup/m0/vector.S
@@ -0,0 +1,320 @@
+/*
+ * Copyright (C) 2017-2019 Alibaba Group Holding Limited
+ */
+ /******************************************************************************
+ * @file     vectors.S
+ * @brief    define default vector handlers. Should use with
+ *           GCC for CSKY Embedded Processors
+ * @version  V1.0
+ * @date     28. Nove 2017
+ ******************************************************************************/
+#define __ASSEMBLY__
+#include "irq_ctx.h"
+
+/* Enable interrupts when returning from the handler */
+#define MSTATUS_PRV1 0x1880
+
+.section .bss.g_trap_stack
+
+    .align 4
+    .global g_trap_sp_base
+    .global g_trap_sp
+g_trap_sp_base:
+#if defined(__riscv_flen)
+    .space 1024
+#else
+    .space 512
+#endif
+g_trap_sp:
+#if 0
+.section .bss.g_irq_stack
+    .align 4
+    .global g_irq_sp_base
+    .global g_irq_sp
+g_irq_sp_base:
+    .space 1024
+g_irq_sp:
+#endif
+/******************************************************************************
+ * Functions:
+ *     void default_interrupt_handler(void);
+ * default handler for all the vector mode IRQs
+ ******************************************************************************/
+
+    .section .text.vectors.default_interrupt_handler, "ax", %progbits
+    .align  6
+    .global default_interrupt_handler
+    .weak   default_interrupt_handler
+    /* FreeRTOS will define tspend_handler for context switch */
+    .type   default_interrupt_handler, %function
+default_interrupt_handler:
+    /* ipush */
+    addi  sp, sp, -76
+
+    /* save x5 x6 then save mepc mcause */
+    sw    x5, 4(sp)
+    sw    x6, 8(sp)
+    csrr  t0, mepc
+    csrr  t1, mcause
+    sw    t1, 64(sp)
+    sw    t0, 68(sp)
+    csrr  t0, mscratch
+    sw    t0, 72(sp)
+    /* save regs */
+    sw      x1, 0(sp)
+    sw      x7, 12(sp)
+    sw      x10, 16(sp)
+    sw      x11, 20(sp)
+    sw      x12, 24(sp)
+    sw      x13, 28(sp)
+    sw      x14, 32(sp)
+    sw      x15, 36(sp)
+    sw      x16, 40(sp)
+    sw      x17, 44(sp)
+    sw      x28, 48(sp)
+    sw      x29, 52(sp)
+    sw      x30, 56(sp)
+    sw      x31, 60(sp)
+
+    /*
+     * IRQ stack contents after ipush:
+     * ~mem addr high:
+     * +  0:  <--- init IRQ sp (mscratch)
+     * -  4:  mepc
+     * -  8:  mcause
+     * - 12:  x1  (ra)
+     * - 16:  x5  (t0)
+     * - 20:  x6  (t1)
+     * - 24:  x7  (t2)
+     * - 28:  x10 (a0)
+     * - 32:  x11 (a1)
+     * - 36:  x12 (a2)
+     * - 40:  x13 (a3)
+     * - 44:  x14 (a4)
+     * - 48:  x15 (a5)
+     * - 52:  x16 (a6)
+     * - 56:  x17 (a7)
+     * - 60:  x28 (t3)
+     * - 64:  x29 (t4)
+     * - 68:  x30 (t5)
+     * - 72:  x31 (t6)   <--- current IRQ sp
+     * ~mem addr low:
+     */
+    /* WARNING: global IRQ enabled by ipush */
+    csrs    mstatus, 8
+
+    /* keep stack 16bytes aligned */
+    addi    sp, sp, -88
+
+    /* - 76:  mstatus  */
+    csrr    t1, mstatus
+    sw      t1, 84(sp)
+    srli    t2, t1, 13
+    andi    t2, t2, 0x3
+    li      t0, 0x3
+    bne     t2, t0,  .F_RegNotSave1
+
+    fsw     ft0, 0(sp)
+    fsw     ft1, 4(sp)
+    fsw     ft2, 8(sp)
+    fsw     ft3, 12(sp)
+    fsw     ft4, 16(sp)
+    fsw     ft5, 20(sp)
+    fsw     ft6, 24(sp)
+    fsw     ft7, 28(sp)
+    fsw     fa0, 32(sp)
+    fsw     fa1, 36(sp)
+    fsw     fa2, 40(sp)
+    fsw     fa3, 44(sp)
+    fsw     fa4, 48(sp)
+    fsw     fa5, 52(sp)
+    fsw     fa6, 56(sp)
+    fsw     fa7, 60(sp)
+    fsw     ft8, 64(sp)
+    fsw     ft9, 68(sp)
+    fsw     ft10,72(sp)
+    fsw     ft11,76(sp)
+.F_RegNotSave1:
+
+    csrr    a0, mcause
+    andi    t1, a0, 0x3FF
+    /* get ISR */
+    la      t2, interrupt_entry
+    jalr    t2
+
+    lw      t1, 84(sp)
+    srli    t2, t1, 13
+    andi    t2, t2, 0x3
+    li      t0, 0x3
+    bne     t2, t0,  .F_RegNotLoad
+
+    flw     ft0, 0(sp)
+    flw     ft1, 4(sp)
+    flw     ft2, 8(sp)
+    flw     ft3, 12(sp)
+    flw     ft4, 16(sp)
+    flw     ft5, 20(sp)
+    flw     ft6, 24(sp)
+    flw     ft7, 28(sp)
+    flw     fa0, 32(sp)
+    flw     fa1, 36(sp)
+    flw     fa2, 40(sp)
+    flw     fa3, 44(sp)
+    flw     fa4, 48(sp)
+    flw     fa5, 52(sp)
+    flw     fa6, 56(sp)
+    flw     fa7, 60(sp)
+    flw     ft8, 64(sp)
+    flw     ft9, 68(sp)
+    flw     ft10,72(sp)
+    flw     ft11,76(sp)
+
+.F_RegNotLoad:
+    addi    sp, sp, 88
+    /* mret included, and IRQ tail-chain may happen */
+    /* ipop */
+
+    csrc    mstatus, 8
+    /* restore mepc mcause mscrath */
+    lw      t0, 68(sp)
+    csrw    mepc, t0
+    lw      t0, 64(sp)
+    csrw    mcause, t0
+    lw      t0, 72(sp)
+    csrw    mscratch, t0
+    /* restore regs */
+    lw      x1, 0(sp)
+    lw      x5, 4(sp)
+    lw      x6, 8(sp)
+    lw      x7, 12(sp)
+    lw      x10, 16(sp)
+    lw      x11, 20(sp)
+    lw      x12, 24(sp)
+    lw      x13, 28(sp)
+    lw      x14, 32(sp)
+    lw      x15, 36(sp)
+    lw      x16, 40(sp)
+    lw      x17, 44(sp)
+    lw      x28, 48(sp)
+    lw      x29, 52(sp)
+    lw      x30, 56(sp)
+    lw      x31, 60(sp)
+
+    addi    sp, sp, 76
+    mret
+
+    .size   default_interrupt_handler, . - default_interrupt_handler
+
+/******************************************************************************
+ * Functions:
+ *     void trap(void);
+ * default handler for exceptions and non-vector mode IRQs
+ ******************************************************************************/
+    .section .text.vectors.default_trap_handler, "ax", %progbits
+    .align  6
+    .global trap
+    .type   trap, %function
+    .weak   default_trap_handler
+    .global default_trap_handler
+    .type   default_trap_handler, %function
+default_trap_handler:
+trap:
+    /* Check for interrupt */
+    sw      t0, -4(sp)
+    csrr    t0, mcause
+
+    /* IRQ, but in non-vector mode */
+    blt     t0, x0, .Lirq
+
+    la      t0, g_trap_sp
+    addi    t0, t0, -XCPTCONTEXT_SIZE
+    sw      x1, REG_X1(t0)
+    sw      x2, REG_X2(t0)
+    sw      x3, REG_X3(t0)
+    sw      x4, REG_X4(t0)
+    sw      x6, REG_X6(t0)
+    sw      x7, REG_X7(t0)
+    sw      x8, REG_X8(t0)
+    sw      x9, REG_X9(t0)
+    sw      x10, REG_X10(t0)
+    sw      x11, REG_X11(t0)
+    sw      x12, REG_X12(t0)
+    sw      x13, REG_X13(t0)
+    sw      x14, REG_X14(t0)
+    sw      x15, REG_X15(t0)
+    sw      x16, REG_X16(t0)
+    sw      x17, REG_X17(t0)
+    sw      x18, REG_X18(t0)
+    sw      x19, REG_X19(t0)
+    sw      x20, REG_X20(t0)
+    sw      x21, REG_X21(t0)
+    sw      x22, REG_X22(t0)
+    sw      x23, REG_X23(t0)
+    sw      x24, REG_X24(t0)
+    sw      x25, REG_X25(t0)
+    sw      x26, REG_X26(t0)
+    sw      x27, REG_X27(t0)
+    sw      x28, REG_X28(t0)
+    sw      x29, REG_X29(t0)
+    sw      x30, REG_X30(t0)
+    sw      x31, REG_X31(t0)
+    csrr    a0, mepc
+    sw      a0, REG_EPC(t0)
+    csrr    a0, mstatus
+    sw      a0, REG_INT_CTX(t0)
+
+    mv      a0, t0
+    lw      t0, -4(sp)
+    mv      sp, a0
+    sw      t0, REG_X5(sp)
+
+    jal     exception_entry
+
+    lw      t0, REG_INT_CTX(sp)
+    csrw    mstatus, t0
+    lw      t0, REG_EPC(sp)
+    csrw    mepc, t0
+
+    lw      x31, REG_X31(sp)
+    lw      x30, REG_X30(sp)
+    lw      x29, REG_X29(sp)
+    lw      x28, REG_X28(sp)
+    lw      x27, REG_X27(sp)
+    lw      x26, REG_X26(sp)
+    lw      x25, REG_X25(sp)
+    lw      x24, REG_X24(sp)
+    lw      x23, REG_X23(sp)
+    lw      x22, REG_X22(sp)
+    lw      x21, REG_X21(sp)
+    lw      x20, REG_X20(sp)
+    lw      x19, REG_X19(sp)
+    lw      x18, REG_X18(sp)
+    lw      x17, REG_X17(sp)
+    lw      x16, REG_X16(sp)
+    lw      x15, REG_X15(sp)
+    lw      x14, REG_X14(sp)
+    lw      x13, REG_X13(sp)
+    lw      x12, REG_X12(sp)
+    lw      x11, REG_X11(sp)
+    lw      x10, REG_X10(sp)
+    lw      x9,  REG_X9(sp)
+    lw      x8,  REG_X8(sp)
+    lw      x7,  REG_X7(sp)
+    lw      x6,  REG_X6(sp)
+    lw      x5,  REG_X5(sp)
+    lw      x4,  REG_X4(sp)
+    lw      x3,  REG_X3(sp)
+    lw      x1,  REG_X1(sp)
+    lw      x2,  REG_X2(sp)
+
+    mret
+
+.Lirq:
+    lw      t0, -4(sp)
+/* MSOFT IRQ for FreeRTOS context switch
+ * Config MSOFT IRQ to non-vector mode
+ * tspend_handler is a weak alias to default_interrupt_handler
+ */
+    j       default_interrupt_handler
+
+    .size   default_trap_handler, . - default_trap_handler
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt
new file mode 100755
index 0000000000..d64151b6b4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/bl_mcu_sdk/tools/bflb_tools/bflb_fw_post_proc/usage.txt
@@ -0,0 +1,17 @@
+bflb_fw_post_proc is a command line firmware process tool to update correct bootheder information and encrypt or sign firmware.
+In order to achieve this goal, some parameters must be specified:
+  --chipname:  chipname that you are buiding
+  --brdcfgdir: board config directory that you are using,this is used to copy boot2 like file to image directory
+  --imgfile: image file that you want to deal with,',' can be used to split multiple files and '*' can be used to match the only one file
+  --key: AES key when you want to encrypt you image with AES CTR
+  --iv: AES iv when you want to encrypt you image with AES CTR
+  --xtsmode: xts mode enable when you want to encrypt you image with AES xts and your chip support
+  --privatekey: private key of ecc-256 in pem format
+  --publickey: public key of ecc-256 in pem format
+
+Examples:
+bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin
+bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin,./build/build_out/boot2_*.bin
+bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin --key=000102030405060708090A0B0C0D0E0F --iv=100102030405060708090A0B00000000
+bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin --key=000102030405060708090A0B0C0D0E0F101112131415161718191A1B1C1D1E1F --iv=100102030405060708090A0B00000000 --xtsmode=1
+bflb_fw_post_proc --chipname=bl616 --brdcfgdir=bsp/board/bl616dk/config --imgfile=./build/build_out/helloworld_bl616.bin --privatekey=privatekey_uecc.pem --publickey=publickey_uecc.pem
\ No newline at end of file
diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/Kconfig b/bsp/bouffalo_lab/libraries/rt_drivers/Kconfig
new file mode 100755
index 0000000000..aae14d8fa4
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/Kconfig
@@ -0,0 +1,89 @@
+menu "General Drivers Configuration"
+
+    config BSP_USING_GPIO
+        bool "Enable GPIO"
+        select RT_USING_PIN
+        default y
+
+    menu "General Purpose UARTs"
+
+    menuconfig BSP_USING_UART0
+        bool "Enable UART0"
+        default y
+        if BSP_USING_UART0
+            choice
+                prompt "UART0 TX PIN"
+                default UART0_TX_USING_GPIO16 if BSP_USING_BL60X
+                default UART0_TX_USING_GPIO21 if BSP_USING_BL61X
+                default UART0_TX_USING_GPIO14 if BSP_USING_BL70X
+                default UART0_TX_USING_GPIO14 if BSP_USING_BL808
+
+                config UART0_TX_USING_GPIO14
+                    bool "GPIO_14"
+                config UART0_TX_USING_GPIO16
+                    bool "GPIO_16"
+                config UART0_TX_USING_GPIO21
+                    bool "GPIO_21"
+            endchoice
+            choice
+                prompt "UART0 RX PIN"
+                default UART0_RX_USING_GPIO7 if BSP_USING_BL60X
+                default UART0_RX_USING_GPIO22 if BSP_USING_BL61X
+                default UART0_RX_USING_GPIO23 if BSP_USING_BL70X
+                default UART0_RX_USING_GPIO15 if BSP_USING_BL808
+
+                config UART0_RX_USING_GPIO7
+                    bool "GPIO_7"
+                config UART0_RX_USING_GPIO15
+                    bool "GPIO_15"
+                config UART0_RX_USING_GPIO22
+                    bool "GPIO_22"
+                config UART0_RX_USING_GPIO23
+                    bool "GPIO_23"
+            endchoice
+        endif
+        
+    menuconfig BSP_USING_UART1
+        bool "Enable UART1"
+        default n
+        if BSP_USING_UART1
+            choice
+                prompt "UART1 TX PIN"
+                default UART1_TX_USING_GPIO4 if BSP_USING_BL60X
+                default UART1_TX_USING_GPIO16 if BSP_USING_BL61X
+                default UART1_TX_USING_GPIO26 if BSP_USING_BL70X
+                default UART1_TX_USING_GPIO18 if BSP_USING_BL808
+
+                config UART1_TX_USING_GPIO4
+                    bool "GPIO_4"
+                config UART1_TX_USING_GPIO16
+                    bool "GPIO_16"
+                config UART1_TX_USING_GPIO18
+                    bool "GPIO_18"
+                config UART1_TX_USING_GPIO26
+                    bool "GPIO_26"
+            endchoice
+            choice
+                prompt "UART1 RX PIN"
+                default UART1_RX_USING_GPIO3 if BSP_USING_BL60X
+                default UART1_RX_USING_GPIO17 if BSP_USING_BL61X
+                default UART1_RX_USING_GPIO27 if BSP_USING_BL70X
+                default UART1_RX_USING_GPIO19 if BSP_USING_BL808
+
+                config UART1_RX_USING_GPIO3
+                    bool "GPIO_3"
+                config UART1_RX_USING_GPIO5
+                    bool "GPIO_5"
+                config UART1_RX_USING_GPIO17
+                    bool "GPIO_17"
+                config UART1_RX_USING_GPIO19
+                    bool "GPIO_19"
+                config UART1_RX_USING_GPIO27
+                    bool "GPIO_27"
+            endchoice
+        endif
+
+    endmenu
+
+endmenu
+
diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/SConscript b/bsp/bouffalo_lab/libraries/rt_drivers/SConscript
new file mode 100755
index 0000000000..dd083d98dc
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/SConscript
@@ -0,0 +1,25 @@
+# RT-Thread building script for component
+
+from building import *
+
+cwd     = GetCurrentDir()
+src = ['drv_uart.c']
+CPPPATH = [cwd]
+
+if GetDepend('BSP_USING_GPIO'):
+    src += ['drv_gpio.c']
+
+if  GetDepend('BSP_USING_I2C'):
+    src += ['drv_i2c.c']
+
+group = DefineGroup('rt_drivers', src, depend = [''], CPPPATH = CPPPATH)
+
+objs = [group]
+
+list = os.listdir(cwd)
+
+for item in list:
+    if os.path.isfile(os.path.join(cwd, item, 'SConscript')):
+        objs = objs + SConscript(os.path.join(item, 'SConscript'))
+
+Return('objs')
diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c
new file mode 100755
index 0000000000..226f3a2a66
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.c
@@ -0,0 +1,229 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/01/5      chushicheng  first version
+ *
+ */
+
+#include "drv_gpio.h"
+#include 
+
+#define DBG_TAG              "drv.gpio"
+#define DBG_LVL               DBG_INFO
+#include 
+
+#ifdef RT_USING_PIN
+static struct bflb_device_s *gpio;
+
+static struct rt_pin_irq_hdr pin_irq_hdr_tab[GPIO_MAX];
+
+static void gpio_isr(int irq, void *arg)
+{
+    rt_base_t i;
+    for(i = 0; i < GPIO_MAX; i ++)
+    {
+        if(pin_irq_hdr_tab[i].pin != -1)
+        {
+            bool intstatus = bflb_gpio_get_intstatus(gpio, i);
+            if (intstatus) {
+                bflb_gpio_int_clear(gpio, i);
+                if(pin_irq_hdr_tab[i].hdr)
+                    pin_irq_hdr_tab[i].hdr(pin_irq_hdr_tab[i].args);
+            }
+        }
+    }
+
+}
+
+static void _pin_write(rt_device_t dev, rt_base_t pin, rt_base_t value)
+{
+    if(value)
+        bflb_gpio_set(gpio, pin);
+    else
+        bflb_gpio_reset(gpio, pin);
+}
+
+static int _pin_read(rt_device_t dev, rt_base_t pin)
+{
+    return bflb_gpio_read(gpio, pin);
+}
+
+static void _pin_mode(rt_device_t dev, rt_base_t pin, rt_base_t mode)
+{
+    rt_uint32_t cfgset = 0;
+
+    switch(mode)
+    {
+        case PIN_MODE_OUTPUT:
+            cfgset = GPIO_OUTPUT;
+            break;
+
+        case PIN_MODE_INPUT:
+            cfgset = GPIO_INPUT;
+            break;
+
+        case PIN_MODE_INPUT_PULLUP:
+            cfgset = GPIO_INPUT | GPIO_PULLUP;
+            break;
+
+        case PIN_MODE_INPUT_PULLDOWN:
+            cfgset =  GPIO_INPUT | GPIO_PULLDOWN;
+            break;
+
+        case PIN_MODE_OUTPUT_OD:
+            cfgset = GPIO_OUTPUT | GPIO_FLOAT;
+            break;
+
+        default:
+            cfgset = GPIO_OUTPUT | GPIO_FLOAT;
+            break;
+    }
+
+    cfgset |= GPIO_SMT_EN | GPIO_DRV_0;
+    bflb_gpio_init(gpio, pin, cfgset);
+}
+
+static rt_err_t _pin_attach_irq(struct rt_device *device, rt_int32_t pin,
+                                rt_uint32_t irq_mode, void (*hdr)(void *args), void *args)
+{
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+    if(pin_irq_hdr_tab[pin].pin == pin &&
+        pin_irq_hdr_tab[pin].hdr == hdr &&
+        pin_irq_hdr_tab[pin].mode == irq_mode &&
+        pin_irq_hdr_tab[pin].args == args)
+    {
+        rt_hw_interrupt_enable(level);
+        return RT_EOK;
+    }
+
+    if(pin_irq_hdr_tab[pin].pin != -1)
+    {
+        rt_hw_interrupt_enable(level);
+        return -RT_EBUSY;
+    }
+
+    pin_irq_hdr_tab[pin].pin = pin;
+    pin_irq_hdr_tab[pin].mode = irq_mode;
+    pin_irq_hdr_tab[pin].hdr = hdr;
+    pin_irq_hdr_tab[pin].args = args;
+
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_detach_irq(struct rt_device *device, rt_int32_t pin)
+{
+    rt_base_t level;
+
+    level = rt_hw_interrupt_disable();
+
+    if(pin_irq_hdr_tab[pin].pin == -1)
+    {
+        rt_hw_interrupt_enable(level);
+
+        return RT_EOK;
+    }
+
+    pin_irq_hdr_tab[pin].pin = -1;
+    pin_irq_hdr_tab[pin].mode = 0;
+    pin_irq_hdr_tab[pin].hdr = RT_NULL;
+    pin_irq_hdr_tab[pin].args = RT_NULL;
+
+    rt_hw_interrupt_enable(level);
+
+    return RT_EOK;
+}
+
+static rt_err_t _pin_irq_enable(struct rt_device *device, rt_base_t pin,
+                                rt_uint32_t enabled)
+{
+    rt_base_t level;
+    rt_uint8_t trig_mode = 0;
+
+    if (enabled == PIN_IRQ_ENABLE)
+    {
+        level = rt_hw_interrupt_disable();
+
+        if(pin_irq_hdr_tab[pin].pin == -1)
+        {
+            rt_hw_interrupt_enable(level);
+            return -RT_ENOSYS;
+        }
+
+        switch (pin_irq_hdr_tab[pin].mode)
+        {
+            case PIN_IRQ_MODE_RISING:
+                trig_mode = GPIO_INT_TRIG_MODE_SYNC_RISING_EDGE;
+                break;
+
+            case PIN_IRQ_MODE_FALLING:
+                trig_mode = GPIO_INT_TRIG_MODE_SYNC_FALLING_EDGE;
+                break;
+
+            case PIN_IRQ_MODE_RISING_FALLING:
+                trig_mode = GPIO_INT_TRIG_MODE_ASYNC_FALLING_EDGE;
+                break;
+
+            case PIN_IRQ_MODE_HIGH_LEVEL:
+                trig_mode = GPIO_INT_TRIG_MODE_SYNC_HIGH_LEVEL;
+                break;
+
+            case PIN_IRQ_MODE_LOW_LEVEL:
+                trig_mode = GPIO_INT_TRIG_MODE_SYNC_LOW_LEVEL;
+                break;
+        }
+
+        bflb_gpio_int_init(gpio, pin, trig_mode);
+        bflb_gpio_int_mask(gpio, pin, false);
+
+        rt_hw_interrupt_enable(level);
+    }
+    else if(enabled == PIN_IRQ_DISABLE)
+    {
+        level = rt_hw_interrupt_disable();
+        bflb_gpio_int_mask(gpio, pin, true);
+
+        rt_hw_interrupt_enable(level);
+    }
+    else
+    {
+        return -RT_ENOSYS;
+    }
+    return RT_EOK;
+}
+
+const static struct rt_pin_ops bl_drv_pin_ops =
+{
+    _pin_mode,
+    _pin_write,
+    _pin_read,
+    _pin_attach_irq,
+    _pin_detach_irq,
+    _pin_irq_enable,
+    NULL,
+};
+
+int rt_hw_pin_init(void)
+{
+    rt_uint8_t i;
+
+    for(i = 0; i < GPIO_MAX; i ++)
+    {
+        pin_irq_hdr_tab[i].pin = -1;
+    }
+    gpio = bflb_device_get_by_name("gpio");
+    bflb_irq_attach(gpio->irq_num, gpio_isr, gpio);
+    bflb_irq_enable(gpio->irq_num);
+
+    return rt_device_pin_register("pin", &bl_drv_pin_ops, RT_NULL);
+}
+INIT_BOARD_EXPORT(rt_hw_pin_init);
+
+#endif /*RT_USING_PIN */
diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.h b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.h
new file mode 100755
index 0000000000..fda320a221
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_gpio.h
@@ -0,0 +1,23 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2023/01/5      chushicheng  first version
+ *
+ */
+
+#ifndef __DRV_GPIO_H__
+#define __DRV_GPIO_H__
+
+#include 
+#include "rtdevice.h"
+#include 
+#include "bflb_gpio.h"
+
+#define GPIO_MAX            (GPIO_PIN_45 + 1)
+int rt_hw_pin_init(void);
+
+#endif /* __DRV_GPIO_H__ */
diff --git a/bsp/bouffalo_lab/libraries/rt_drivers/drv_uart.c b/bsp/bouffalo_lab/libraries/rt_drivers/drv_uart.c
new file mode 100755
index 0000000000..5a4d8e958f
--- /dev/null
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_uart.c
@@ -0,0 +1,305 @@
+/*
+ * Copyright (c) 2006-2023, RT-Thread Development Team
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Change Logs:
+ * Date           Author       Notes
+* 2022/12/25     flyingcys    first version
+*/
+
+#include 
+#include 
+#include 
+
+#include "board.h"
+#include "drv_uart.h"
+
+#define DBG_TAG "DRV.UART"
+#define DBG_LVL DBG_WARNING
+#include 
+
+#define UART_DEFAULT_BAUDRATE 2000000
+
+// uart0
+#ifdef UART0_TX_USING_GPIO14
+#define UART0_GPIO_TX           GPIO_PIN_14
+#elif defined(UART0_TX_USING_GPIO16)
+#define UART0_GPIO_TX           GPIO_PIN_16
+#elif defined(UART0_TX_USING_GPIO21)
+#define UART0_GPIO_TX           GPIO_PIN_21
+#endif
+
+#ifdef UART0_RX_USING_GPIO7
+#define UART0_GPIO_RX           GPIO_PIN_7
+#elif defined(UART0_RX_USING_GPIO15)
+#define UART0_GPIO_RX           GPIO_PIN_15
+#elif defined(UART0_RX_USING_GPIO22)
+#define UART0_GPIO_RX           GPIO_PIN_22
+#elif defined(UART0_RX_USING_GPIO23)
+#define UART0_GPIO_RX           GPIO_PIN_23
+#endif
+
+// uart1
+#ifdef UART1_TX_USING_GPIO4
+#define UART1_GPIO_TX           GPIO_PIN_4
+#elif defined(UART1_TX_USING_GPIO16)
+#define UART1_GPIO_TX           GPIO_PIN_16
+#elif defined(UART1_TX_USING_GPIO18)
+#define UART1_GPIO_TX           GPIO_PIN_18
+#elif defined(UART1_TX_USING_GPIO26)
+#define UART1_GPIO_TX           GPIO_PIN_26
+#endif
+
+#ifdef UART1_RX_USING_GPIO3
+#define UART1_GPIO_RX           GPIO_PIN_3
+#elif defined(UART1_RX_USING_GPIO5)
+#define UART1_GPIO_RX           GPIO_PIN_5
+#elif defined(UART1_RX_USING_GPIO17)
+#define UART1_GPIO_RX           GPIO_PIN_17
+#elif defined(UART1_RX_USING_GPIO19)
+#define UART1_GPIO_RX           GPIO_PIN_19
+#elif defined(UART1_RX_USING_GPIO27)
+#define UART1_GPIO_RX           GPIO_PIN_27
+#endif
+
+static struct bflb_device_s    *gpio;
+
+struct device_uart
+{
+    struct rt_serial_device serial;
+    struct bflb_device_s    *bflb_device;
+};
+
+static void _uart_rx_irq(int irq, void *arg)
+{
+    struct rt_serial_device *serial = (struct rt_serial_device *)arg;
+    RT_ASSERT(serial != RT_NULL);
+
+    struct device_uart *uart = serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart->bflb_device != RT_NULL);
+
+    uint32_t intstatus = bflb_uart_get_intstatus(uart->bflb_device);
+    if (intstatus & UART_INTSTS_RX_FIFO)
+    {
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+
+    if (intstatus & UART_INTSTS_RTO)
+    {
+        bflb_uart_int_clear(uart->bflb_device, UART_INTCLR_RTO);
+        rt_hw_serial_isr(serial, RT_SERIAL_EVENT_RX_IND);
+    }
+}
+
+static rt_err_t _uart_configure(struct rt_serial_device *serial, struct serial_configure *serial_cfg)
+{
+    struct device_uart *uart = RT_NULL;
+    struct bflb_uart_config_s uart_cfg;
+
+    RT_ASSERT(serial != RT_NULL);
+    RT_ASSERT(serial_cfg != RT_NULL);
+
+    uart = serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart->bflb_device != RT_NULL);
+
+    uart_cfg.baudrate = UART_DEFAULT_BAUDRATE;
+    uart_cfg.data_bits = UART_DATA_BITS_8;
+    uart_cfg.stop_bits = UART_STOP_BITS_1;
+    uart_cfg.parity = UART_PARITY_NONE;
+    uart_cfg.flow_ctrl = 0;
+    uart_cfg.tx_fifo_threshold = 7;
+    uart_cfg.rx_fifo_threshold = 7;
+
+    uart_cfg.baudrate = serial_cfg->baud_rate;
+
+    switch (serial_cfg->data_bits)
+    {
+        case DATA_BITS_5:
+            uart_cfg.data_bits = UART_DATA_BITS_5;
+            break;
+
+        case DATA_BITS_6:
+            uart_cfg.data_bits = UART_DATA_BITS_6;
+            break;
+
+        case DATA_BITS_7:
+            uart_cfg.data_bits = UART_DATA_BITS_7;
+            break;
+
+        case DATA_BITS_8:
+            uart_cfg.data_bits = UART_DATA_BITS_8;
+            break;
+
+        default:
+            uart_cfg.data_bits = UART_DATA_BITS_8;
+            break;
+    }
+
+    switch (serial_cfg->stop_bits)
+    {
+        case STOP_BITS_1:
+            uart_cfg.stop_bits = UART_STOP_BITS_1;
+            break;
+
+        case STOP_BITS_2:
+            uart_cfg.stop_bits = UART_STOP_BITS_2;
+            break;
+
+        default:
+            uart_cfg.stop_bits = UART_STOP_BITS_1;
+            break;
+    }
+
+    switch (serial_cfg->parity)
+    {
+        case PARITY_NONE:
+            uart_cfg.parity = UART_PARITY_NONE;
+            break;
+
+        case PARITY_ODD:
+            uart_cfg.parity = UART_PARITY_ODD;
+            break;
+
+        case PARITY_EVEN:
+            uart_cfg.parity = UART_PARITY_EVEN;
+            break;
+
+        default:
+            uart_cfg.parity = UART_PARITY_NONE;
+            break;
+    }
+
+    bflb_uart_init(uart->bflb_device, &uart_cfg);
+
+    return RT_EOK;
+}
+
+static rt_err_t _uart_control(struct rt_serial_device *serial, int cmd, void *arg)
+{
+    struct device_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart->bflb_device != RT_NULL);
+
+    switch (cmd)
+    {
+    /* disable interrupt */
+    case RT_DEVICE_CTRL_CLR_INT:
+        bflb_irq_disable(uart->bflb_device->irq_num);
+        bflb_irq_attach(uart->bflb_device->irq_num, NULL, NULL);
+        break;
+
+    /* enable interrupt */
+    case RT_DEVICE_CTRL_SET_INT:
+        bflb_uart_rxint_mask(uart->bflb_device, false);
+        bflb_irq_attach(uart->bflb_device->irq_num, _uart_rx_irq, serial);
+        bflb_irq_enable(uart->bflb_device->irq_num);
+        break;
+    }
+    return RT_EOK;
+}
+
+static int _uart_putc(struct rt_serial_device *serial, char c)
+{
+    struct device_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+
+    uart = serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart->bflb_device != RT_NULL);
+
+    bflb_uart_putchar(uart->bflb_device, c);
+
+    return 1;
+}
+
+static int _uart_getc(struct rt_serial_device *serial)
+{
+    int ch = -1;
+    struct device_uart *uart;
+
+    RT_ASSERT(serial != RT_NULL);
+    uart = serial->parent.user_data;
+    RT_ASSERT(uart != RT_NULL);
+    RT_ASSERT(uart->bflb_device != RT_NULL);
+
+    ch = bflb_uart_getchar(uart->bflb_device);
+
+    return ch;
+}
+
+static const struct rt_uart_ops _uart_ops =
+{
+    .configure = _uart_configure,
+    .control = _uart_control,
+    .putc = _uart_putc,
+    .getc = _uart_getc,
+    .dma_transmit = RT_NULL
+};
+
+/*
+ * UART Initiation
+ */
+int rt_hw_uart_init(void)
+{
+    rt_err_t result = 0;
+
+    struct serial_configure config = RT_SERIAL_CONFIG_DEFAULT;
+    struct rt_serial_device *serial;
+    struct device_uart      *uart;
+
+    gpio = bflb_device_get_by_name("gpio");
+
+#ifdef BSP_USING_UART0
+    static struct device_uart bl_uart0;
+
+    serial  = &bl_uart0.serial;
+    uart    = &bl_uart0;
+
+    serial->ops              = &_uart_ops;
+    serial->config           = config;
+    serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
+
+    uart->bflb_device = bflb_device_get_by_name("uart0");
+
+    bflb_gpio_uart_init(gpio, UART0_GPIO_TX, GPIO_UART_FUNC_UART0_TX);
+    bflb_gpio_uart_init(gpio, UART0_GPIO_RX, GPIO_UART_FUNC_UART0_RX);
+
+    /* register USART device */
+    result = rt_hw_serial_register(serial,
+                                    "uart0",
+                                    RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                                    uart);
+    RT_ASSERT(result == RT_EOK);
+#endif
+
+#ifdef BSP_USING_UART1
+    static struct device_uart bl_uart1;
+
+    serial  = &bl_uart1.serial;
+    uart    = &bl_uart1;
+
+    serial->ops              = &_uart_ops;
+    serial->config           = config;
+    serial->config.baud_rate = UART_DEFAULT_BAUDRATE;
+
+    uart->bflb_device = bflb_device_get_by_name("uart1");
+    bflb_gpio_uart_init(gpio, UART1_GPIO_TX, GPIO_UART_FUNC_UART1_TX);
+    bflb_gpio_uart_init(gpio, UART1_GPIO_RX, GPIO_UART_FUNC_UART1_RX);
+
+    /* register USART device */
+    result = rt_hw_serial_register(serial,
+                                    "uart1",
+                                    RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX,
+                                    uart);
+    RT_ASSERT(result == RT_EOK);
+#endif
+    return 0;
+}
diff --git a/bsp/bl808/m0/drivers/drv_uart.h b/bsp/bouffalo_lab/libraries/rt_drivers/drv_uart.h
old mode 100644
new mode 100755
similarity index 84%
rename from bsp/bl808/m0/drivers/drv_uart.h
rename to bsp/bouffalo_lab/libraries/rt_drivers/drv_uart.h
index f9158348d2..f70c981d6b
--- a/bsp/bl808/m0/drivers/drv_uart.h
+++ b/bsp/bouffalo_lab/libraries/rt_drivers/drv_uart.h
@@ -15,10 +15,8 @@
 #include "rtdevice.h"
 #include 
 
-#include "bl_uart.h"
-#include "bl808_uart.h"
-
-#include "uart_config.h"
+#include "bflb_uart.h"
+#include "bflb_gpio.h"
 
 int rt_hw_uart_init(void);
 
diff --git a/libcpu/risc-v/SConscript b/libcpu/risc-v/SConscript
index 2883d63ce5..41549d03ee 100644
--- a/libcpu/risc-v/SConscript
+++ b/libcpu/risc-v/SConscript
@@ -18,7 +18,7 @@ else :
     group = group + SConscript(os.path.join('common', 'SConscript'))
 
 # cpu porting code files
-if  rtconfig.CPU == "e9xx" or rtconfig.CPU == "c906":
+if  rtconfig.CPU == "c906":
     group = group + SConscript(os.path.join(rtconfig.VENDOR, rtconfig.CPU, 'SConscript'))
 elif rtconfig.CPU in list:
     group = group + SConscript(os.path.join(rtconfig.CPU, 'SConscript'))
diff --git a/libcpu/risc-v/t-head/e9xx/SConscript b/libcpu/risc-v/t-head/e9xx/SConscript
deleted file mode 100644
index 92133bfb47..0000000000
--- a/libcpu/risc-v/t-head/e9xx/SConscript
+++ /dev/null
@@ -1,12 +0,0 @@
-# RT-Thread building script for component
-
-from building import *
-
-cwd     = GetCurrentDir()
-src     = Glob('*.c') + Glob('*.cpp') + Glob('*_gcc.S')
-CPPPATH = [cwd]
-ASFLAGS = ''
-
-group = DefineGroup('CPU', src, depend = [''], CPPPATH = CPPPATH, ASFLAGS = ASFLAGS)
-
-Return('group')
diff --git a/libcpu/risc-v/t-head/e9xx/interrupt_gcc.S b/libcpu/risc-v/t-head/e9xx/interrupt_gcc.S
deleted file mode 100644
index d727e4df87..0000000000
--- a/libcpu/risc-v/t-head/e9xx/interrupt_gcc.S
+++ /dev/null
@@ -1,224 +0,0 @@
-/*
- * Copyright (c) 2006-2018, RT-Thread Development Team
- *
- * SPDX-License-Identifier: Apache-2.0
- *
- * Change Logs:
- * Date           Author       Notes
- * 2022/12/25     flyingcys    first version
- */
-#include "cpuport.h"
-
-.align 2
-.global IRQ_Handler
-IRQ_Handler:
-#ifdef ARCH_RISCV_FPU
-    addi    sp, sp, -32 * FREGBYTES
-
-    FSTORE  f0, 0 * FREGBYTES(sp)
-    FSTORE  f1, 1 * FREGBYTES(sp)
-    FSTORE  f2, 2 * FREGBYTES(sp)
-    FSTORE  f3, 3 * FREGBYTES(sp)
-    FSTORE  f4, 4 * FREGBYTES(sp)
-    FSTORE  f5, 5 * FREGBYTES(sp)
-    FSTORE  f6, 6 * FREGBYTES(sp)
-    FSTORE  f7, 7 * FREGBYTES(sp)
-    FSTORE  f8, 8 * FREGBYTES(sp)
-    FSTORE  f9, 9 * FREGBYTES(sp)
-    FSTORE  f10, 10 * FREGBYTES(sp)
-    FSTORE  f11, 11 * FREGBYTES(sp)
-    FSTORE  f12, 12 * FREGBYTES(sp)
-    FSTORE  f13, 13 * FREGBYTES(sp)
-    FSTORE  f14, 14 * FREGBYTES(sp)
-    FSTORE  f15, 15 * FREGBYTES(sp)
-    FSTORE  f16, 16 * FREGBYTES(sp)
-    FSTORE  f17, 17 * FREGBYTES(sp)
-    FSTORE  f18, 18 * FREGBYTES(sp)
-    FSTORE  f19, 19 * FREGBYTES(sp)
-    FSTORE  f20, 20 * FREGBYTES(sp)
-    FSTORE  f21, 21 * FREGBYTES(sp)
-    FSTORE  f22, 22 * FREGBYTES(sp)
-    FSTORE  f23, 23 * FREGBYTES(sp)
-    FSTORE  f24, 24 * FREGBYTES(sp)
-    FSTORE  f25, 25 * FREGBYTES(sp)
-    FSTORE  f26, 26 * FREGBYTES(sp)
-    FSTORE  f27, 27 * FREGBYTES(sp)
-    FSTORE  f28, 28 * FREGBYTES(sp)
-    FSTORE  f29, 29 * FREGBYTES(sp)
-    FSTORE  f30, 30 * FREGBYTES(sp)
-    FSTORE  f31, 31 * FREGBYTES(sp)
-#endif
-
-	addi sp, sp, - (32 * REGBYTES)
-	STORE x1, 1 * REGBYTES( sp )			//x1:ra
-
-	STORE x4, 4 * REGBYTES( sp )
-	STORE x5, 5 * REGBYTES( sp )
-	STORE x6, 6 * REGBYTES( sp )
-	STORE x7, 7 * REGBYTES( sp )
-	STORE x8, 8 * REGBYTES( sp )
-	STORE x9, 9 * REGBYTES( sp )
-	STORE x10, 10 * REGBYTES( sp )
-	STORE x11, 11 * REGBYTES( sp )
-	STORE x12, 12 * REGBYTES( sp )
-	STORE x13, 13 * REGBYTES( sp )
-	STORE x14, 14 * REGBYTES( sp )
-	STORE x15, 15 * REGBYTES( sp )
-	STORE x16, 16 * REGBYTES( sp )
-	STORE x17, 17 * REGBYTES( sp )
-	STORE x18, 18 * REGBYTES( sp )
-	STORE x19, 19 * REGBYTES( sp )
-	STORE x20, 20 * REGBYTES( sp )
-	STORE x21, 21 * REGBYTES( sp )
-	STORE x22, 22 * REGBYTES( sp )
-	STORE x23, 23 * REGBYTES( sp )
-	STORE x24, 24 * REGBYTES( sp )
-	STORE x25, 25 * REGBYTES( sp )
-	STORE x26, 26 * REGBYTES( sp )
-	STORE x27, 27 * REGBYTES( sp )
-	STORE x28, 28 * REGBYTES( sp )
-	STORE x29, 29 * REGBYTES( sp )
-	STORE x30, 30 * REGBYTES( sp )
-	STORE x31, 31 * REGBYTES( sp )
-
-    csrr a0, mepc
-	STORE a0, 0 * REGBYTES( sp )			//epc
-
-    csrr a0, mstatus
-	STORE a0, 2 * REGBYTES( sp )			//mstatus
-
-    /* Save the thread stack frame base to mscratch */
-    csrw mscratch, sp
-
-    /* switch to interrupt stack */
-    la sp, __StackTop
-
-    /* interrupt handle */
-	la a0, rt_interrupt_enter
-	jalr a0
-
-	csrr a0, mcause
-	li t0, 0x807FFFFF
-	and a0, a0, t0
-
-	srli a2, a0, __riscv_xlen - 1		/* MSB of mcause is 1 if handing an asynchronous interrupt - shift to LSB to clear other bits. */
-	beq a2, x0, handle_synchronous		/* Branch past interrupt handing if not asynchronous. */
-
-	csrr  t1, mcause
-	andi  t1, t1, 0x3FF
-	slli  t1, t1, 2
-	la  t0, g_irqvector
-	add t0, t0, t1
-	lw  t2, 0(t0)
-	jalr t2
-	
-	j processed_source
-
-handle_synchronous:
-//	la t0, exception_entry
-//	jalr t0
-
-processed_source:
-
-	la a0, rt_interrupt_leave
-	jalr a0
-
-    /* switch to thread stack */
-    csrr  sp, mscratch
-
-   /* need to switch new thread */
-    la    a0, rt_thread_switch_interrupt_flag
-    lw    a1, 0(a0)
-    beqz  a1, interrupt_exit
-	
-	sw zero, 0(a0)
-
-	la    a0, rt_interrupt_from_thread
-	LOAD  a1, 0(a0)
-	STORE sp, 0(a1)
-
-	la    a0, rt_interrupt_to_thread
-	LOAD  a1, 0(a0)
-	LOAD  sp, 0(a1)
-
-interrupt_exit:
-    /* resw ra to mepc */
-    LOAD a0,   0 * REGBYTES(sp)
-    csrw mepc, a0
-
-    LOAD x1,   1 * REGBYTES(sp)
-
-    li    t0, 0x00007800
-    csrw  mstatus, t0
-
-    LOAD a0,   2 * REGBYTES(sp)
-    csrs mstatus, a0
-
-    LOAD x4,   4 * REGBYTES(sp)
-    LOAD x5,   5 * REGBYTES(sp)
-    LOAD x6,   6 * REGBYTES(sp)
-    LOAD x7,   7 * REGBYTES(sp)
-    LOAD x8,   8 * REGBYTES(sp)
-    LOAD x9,   9 * REGBYTES(sp)
-    LOAD x10, 10 * REGBYTES(sp)
-    LOAD x11, 11 * REGBYTES(sp)
-    LOAD x12, 12 * REGBYTES(sp)
-    LOAD x13, 13 * REGBYTES(sp)
-    LOAD x14, 14 * REGBYTES(sp)
-    LOAD x15, 15 * REGBYTES(sp)
-    LOAD x16, 16 * REGBYTES(sp)
-    LOAD x17, 17 * REGBYTES(sp)
-    LOAD x18, 18 * REGBYTES(sp)
-    LOAD x19, 19 * REGBYTES(sp)
-    LOAD x20, 20 * REGBYTES(sp)
-    LOAD x21, 21 * REGBYTES(sp)
-    LOAD x22, 22 * REGBYTES(sp)
-    LOAD x23, 23 * REGBYTES(sp)
-    LOAD x24, 24 * REGBYTES(sp)
-    LOAD x25, 25 * REGBYTES(sp)
-    LOAD x26, 26 * REGBYTES(sp)
-    LOAD x27, 27 * REGBYTES(sp)
-    LOAD x28, 28 * REGBYTES(sp)
-    LOAD x29, 29 * REGBYTES(sp)
-    LOAD x30, 30 * REGBYTES(sp)
-    LOAD x31, 31 * REGBYTES(sp)
-
-    addi sp,  sp, 32 * REGBYTES
-#ifdef ARCH_RISCV_FPU
-    FLOAD   f0, 0 * FREGBYTES(sp)
-    FLOAD   f1, 1 * FREGBYTES(sp)
-    FLOAD   f2, 2 * FREGBYTES(sp)
-    FLOAD   f3, 3 * FREGBYTES(sp)
-    FLOAD   f4, 4 * FREGBYTES(sp)
-    FLOAD   f5, 5 * FREGBYTES(sp)
-    FLOAD   f6, 6 * FREGBYTES(sp)
-    FLOAD   f7, 7 * FREGBYTES(sp)
-    FLOAD   f8, 8 * FREGBYTES(sp)
-    FLOAD   f9, 9 * FREGBYTES(sp)
-    FLOAD   f10, 10 * FREGBYTES(sp)
-    FLOAD   f11, 11 * FREGBYTES(sp)
-    FLOAD   f12, 12 * FREGBYTES(sp)
-    FLOAD   f13, 13 * FREGBYTES(sp)
-    FLOAD   f14, 14 * FREGBYTES(sp)
-    FLOAD   f15, 15 * FREGBYTES(sp)
-    FLOAD   f16, 16 * FREGBYTES(sp)
-    FLOAD   f17, 17 * FREGBYTES(sp)
-    FLOAD   f18, 18 * FREGBYTES(sp)
-    FLOAD   f19, 19 * FREGBYTES(sp)
-    FLOAD   f20, 20 * FREGBYTES(sp)
-    FLOAD   f21, 21 * FREGBYTES(sp)
-    FLOAD   f22, 22 * FREGBYTES(sp)
-    FLOAD   f23, 23 * FREGBYTES(sp)
-    FLOAD   f24, 24 * FREGBYTES(sp)
-    FLOAD   f25, 25 * FREGBYTES(sp)
-    FLOAD   f26, 26 * FREGBYTES(sp)
-    FLOAD   f27, 27 * FREGBYTES(sp)
-    FLOAD   f28, 28 * FREGBYTES(sp)
-    FLOAD   f29, 29 * FREGBYTES(sp)
-    FLOAD   f30, 30 * FREGBYTES(sp)
-    FLOAD   f31, 31 * FREGBYTES(sp)
-
-    addi    sp, sp, 32 * FREGBYTES
-#endif
-
-	mret

A4*DOpQmp2>6sSz=DqVlM^o&WfX5rmdS&3Aoos$OFcRMM*>xr^(b2
zvo?ysr%^fdeAj4xlMmDr{zBh+qyfB^;os1&4M=vlt&Ga3iuiTW<}b|20`!24uD&!%tx}FI
z00|qVNd!Bkl#_fI%}24-;`L`tq0_ZfH0Iv8kKXyJ|**ERQD6N!Dbdmae`v
zN-D1~L7@lC6dLQOQtGSxI2t_%
zV{+G>(d;ycyb~0oOLO@pHLzoV^{m#!E~~+@G(iw?@nb7!2X^Z)GM;;-eBkM^o;KlqIx%09Ws|CGSo
zDlI~>l^WFGIF{b36v6LnyBu%kI2@%N`bQoj!=eR#vbI!yPi-N4L9aU7#ncx;GD_?YqdEc{gy_-eftpmnm;JGuRUM8^?LYf@O#-H);q(hrbT7f8LHeXBJJxk{-KZOO
zkT5YfcTv2<4pNULA49O**`aLT^5VL6OIXFa|AO4BSSELcXt68I=6y
z_l$=93lBVar~hBVI}`9`0N&RC?<~OkD&U<8cwYv*le1u)M4ZLF1U-EwPZ#AND{>P1
zCl(m{8;=?KgI9>IbG7X}1gV~s9gy-Fq~z(r8*#7~j!T>bcp<=d?(c=;{N(_*;{5x1
z;h%YGIEM3o+zT)F;5mu&AMS-?JXXL{fb;L_g`Wg?9>CrCcRmU)063;|=Z;?ZG00y9
za9r<@?Y(fT2VRBqzt;=L?ZWvnyf6KE06z`zeK>znZ+=WahM&gyxAwwMd*E*Tedx#e
zG5v0SioN+Ue=wij?JekqV>)rWFnq}7UO2{&`GfhebJL^nhxm(o;h265ck_RPf)kAK
z6;Te{_qb+ni5`zlg=KH>qBFG(6<<3nb$ib4KT}tIq4JO4&bjjX*MDkyyP;(L$PGkN
zw^76Vp1|=Wye|{mokS(um_HDvvk=2N!4~{y!q!zpU|GBIrGo2k+zqv3sW^8xIuCz;
z1>cwp=kAoazcCHx@po5=S;1-6oFt?&xaIksw)PK*8ymfNu+&ZNkjh~^#rV5Dx(=ro
zd+<#DMXCqay91}+zHJoS+x=`^-N?408{NpqGXyW{M(}@ShT@W#pBVE_s0VbFn=2Ue
zPB*`#e!!S^u2*odi!n4$hxu0sIq}#j)RVwbSKG%OP#WOgk+Z`Cf2Li*;T&F`<1)B6
zK7P;($I^=7hXDS}Ed?jl;Kfwz!IbZkYAA->(ioI#_WN0aV=Oz|*d=)WKP5QsX`KJ0
z2an%R5*&}ILVzFj;=dumamz3sZwvgO1>Tn7{QJE5TYB+hxR(=t&As?>y&rk=JA3nE
zUGbThp6`3{_odTIKW;DXT`wQ}zLWCf_CAvT8wu{s?`@ag6$y^VU|&4>Uq71vA%8sd
zQ{2GLQa8^eAwVoH0s5{hocf`3)?sZ**&X9CGDJpqu
zGCkq;t8>yXq$kWOofQdV%t_xpODX4ncH_P?*Z2?Td(3?p<@+buoMQ5|Je^lsa6e$F
zz_NMn+-diGEuA@GsVbwij&-#y_)z`9?up9NYP1FRge6N3?-jl@^-|f0MR2lgAe=U1
zSsH=me0cpjWsV+Vdyc}{){k4iosp!p&=}yBMhx?VnZ=89
zhateN=RW=fw`q$Kk6XY3I?>xBxP+_fU$K1r{=Z_Ge8i0c*{>YRLZrbJ+f0
zVAuQ^sX?>0Np*;p4LOpI&oA>r)|(_Pzu*fz=SVsf&jOQ=KOz}xJo56lN1*RWn*HMw
zQdv9(@r;pQitFE~bhY&qVk!d_Qmrni6~02GTz>AaEs%z1kY}KNNeaC*PCn*^cxikF
zIM4mbZHUmy7aOH2B~IQ-zt
zi$l^+lH|BP|4sY%NTodez0b{!P>^`R-Dl8#%wa#UvVa>P2bgD=TKIzg#N2RG>ybE|
zcL7*TUb)1%7l5UNIe|Hj^Dh7i!QAt5I)At4+r#U8kVBmA<#zr~=%vem!z1rlvH{Q4
z9+>O;=z}az|3YoOJo$K=_Y3pn9N1cTd|+KJji!g=1KQ_J!Q8Sw965f_)?y=0^Umqs
zG7CP0@ofM)LvX8I+jERqzikQ8Fn1x2eoI2gc<1((;{^;p^+xDV9=F%P$cymqd3H=9eO
z^3AQ}+HC*v0Zaj-K3wxaU)K9xZts1+Wyk5vgYq(bAAr3DaaRm+4AHYD_-?*Cw!i*z
z{*`K2yK;A4gH`(7?m^o3?|cWfDz=SZmcQ*3_OP+wVFQR>tzr>c@2o}a(gu*#zYJ52j<1f@!_I^pyb3QuBoplKXahy?C!PS$E>UxKyp|wy@jSO|
z5nVH=>WNcNmX~~c_)6*5$D2+xd~vbjLUsM^y3Vur&OE4H+hV!C{`*Z=2R;~d|A~7~
z-ihuU*&cg)Y}@lc$Nw|oN5c<`Tb5t{^Y?$bnh~%hQZ@RQNdM8%6(b$E?S(I5{;$;!
z)Gyf_GckZbIeJ|j*lUv6r)+qR&SQT!97zx0BeCgY9`5}lLmUOqM3Ow{D+zRp@K--|jD&BuX^q{>`)+&Ou}V4cp1Wj^YyOnNy>O%K
zBX`YLjNKb%+LfU3ziYuIuNd8Q`sI~DumTtM@(!TW`laGk%w^0ih>~mD`45~^_JPp{
z&YAmw49Re=;u;t?-%GM|>!i1ysxmKkn@{F=yTU18)biP5&bQW>cTNyWF5%B
z&j);AU%?!kJE=LgS}-hBoYxm+V~y+Bd)pXmbnlC~_wu~^Vrl~R%wR9C{0E%-8l0c^
zg2RsrZV;<`o3LG!W>Q~)#_wR>TR
zaptyn?$+a~
zk<}8t*sPbVP^_cCv}$tFWv6
z08<%Do(nK9~DKBSv
zN8b57-!DTZ+|4Jd?2H^;&d24{!@C~hFhw!GKGaEwH$MQkyma;03iqK7*zJP74j9MS
zD+y6fco&-S_m4QM9&`)gc+S1@-EgvKq#66wA%=*$g>3Rl#D{G0aGB6!KI1sT;UEiY
z`7I>%%hkYJ(s+5*hr0RxtUSd(+}a98kZd30k9!7VB=if~hMXvdTL?OkQh%uo&I7<(
zfBj86&dm>@YM9`)~Z(+*OOP*Y+g?_(1Qz
zfuytRt|L3U?9)RKtXvbs+^$c;9Ck*b5SX{nO9qHhgFRB$k#{;w`k}CEnUhdJc}Cj=
zDbAb#k1@0t_LsXpQGakN0V3QWmn4Cvq=0MR*n{SZ!4M(K%&okf54T)ED$Xb6;EmW*
zF6I&`wA&M&QYWhk2K~=coIgLPiVkyYWle}bK1vo@&-
zqV6GYI6u2fz79@ENVM&`p3ZHCSp73a$y?JMn;oFXueOr77i9-dBf%Xpjz<#2W6sRuS?O^5NTSf#c#8w@7=XAymnNi2!_K4Glp}h5K(4XS+
zI22&&zd@bT3elix4A!Y8LmC76Y;7yVW()$&w%7eO7V9`O&Xvg&tYrZMWun$o8$^Lf
zQRh%-FUa;@a}5ObHln>IXoX=5BQu(rJ@n;GGUEqK0)wBQFmsrx`As!4!$rnqsAMAO
zshdoO>r93F+0J}Vp9g&P0igrm*gsR!;tq&e1_*e@J<
zs=x7)J-}GymMXeBssf^zkx5sDj_UU?Rrw}eGek>Q$njeT`d(PQUG@P}>ss-VmjK!BxNW7xf3bQ|!4<0*{!)_=-H^UeKfv=K%Uxm|MMDJRWI&n;R6
z^JXIIV_AUCdhr0pf!DO_g`$PnqEKnNjcca!od*Vju1kT~QCRV&QssIP^1%Hc5c^Ld
zKBx*b1b?FgPOCTvH9k0LfD+xE1MEvdD+}`VE`JqW0zDyL@6k0Oo?a@%(Gg!IDY(8h
zqNhTuJn14%m)=#P4Pve|V>*yc!0{6MkhA0Ned&fO^@qenu-C4r4-*pu=DF(qx>(8z
zd|A*1{W@u#L;A|^taYq|nye_tWBs75wU2%mLWImEB7!i;s&ZjJIjb9@MVee~Wj}^-
zanKeF1uizRROJTft(DLwc$4Ux-H!k%8PY)*d+na*1stX6UJtvivt8@F+{ZJ`tVR1P
z&N%Q*aF*&ll_}ri`{2~OXt)anZi8EY+#Fh6DkOV)Vb>^-DOaESxa!aSuse&=yXq%@
z57A!zDSs*p+WSLvC6z^1leMn;k6VSg(PzlB@pW<7&j!D-#tN)eVa@U7M!@FWqo-b<
z=Fwlf1}?fO%#E)ltG{^fDFi3m9A&@GF#-md<)MVoZxf7ws}M1WEhl}%9cd$W;rDY5gdX3CxAl=*@!WUexiL}&
zH|*N1`9ZhJ!u9wBqZBQP&oJWiim%kllA_Sz^|59#bOd6P?)I>&;3k&95va7dbW6R?
zwC^;EUhk=2g!=2x>SO?0ir{|5ws)=%J{^{-CWaCb7JQRkgTRh?0>L?%z#Ls@d3k1c
zAf6een`iKTag^|G8lE3Z^|&{n2etw~zpPIzHS((j7Q)ZHc*m
zbE#3PC;e<#s#K5r?mXl_K-*oamvDVotu6CldCzsEr|M*xJ?_slAf_R=@tycek=aGj
zb=ZCjI1Tp#f_^%84c|#8X$^eW96mLY(lF9&Iz-8%z7{DYFEK|5$xZaPQ!d6@B~7qv
z3BTo#Lbi{X0ApVsVS!mD73AzThWL2C$~NLJ(3kZe*Sm8{c`mwF#6fpSQ%xYs`$-z@
ztU%Pejy!XDRJlYswH?}jf~6d)-Vqe>3LZhu&BJ;gmbq{XR)21Z*#Y_C?yw^&xPu3@
z5!Ur)N}|;<9YY{W8)VnaNU-c_gnpJC%fU$VMy+&eHKh*bCx201uj0SA%L}Mzn3qev
z?alP%qN@W81=OCxH-KmP5Dzi9SupxTjJOUg8f$;vd>20ld+?`v``p{xo_6hY9r^A<
zQGQh=&0@)pk!IN;iioNx*JCb&x6G|+cg^Al9|C%H@|R%VavfQ4zKH`LA>3GaH{bdb
z=H_{Wm+O=NfvpfS32M^exzfXtU7*4Di}KB?uV6-rI)mpnx=u8g*U75Q$W)b+47)yV
z-s$&%{OtuxF&ReVpe|&pF+)8^&!uxYy1WfXzw}VP5Af}ls8jtRM;~qVfr$FaS4754
z#aFV7*$>_rkv8`aHvmrvA0fWlb#=ivurBlTseV7`#2r9UI9`Dz0KHOVxrFoT7#kI-
zmFlWG0QS&(H_B#c!QO^eM_i;EVCAAK{3+VpSHkjJa80;(ftDkak42l|wn2BBst$oX
zY-QyO!=WF92={pNwBx^F{BF5v$8#Ij#;*EjI`JKL@Vg583?;xDTj(JWd|`=#tK
z9Y{t;H&}ndPZlC5N3^Q5ebCW^p4x4|@lIUwC4-kzM-Be=(0MxJ(!+iz1AWsDHdOYn
zh|mcq<3P^t<`;kI$@x`AH%_~UC|$ux*?u1am%~13;S<-9kK0Ti`4H56wts()f8zxB
z3o#d7yR_*1B)iQzNz1?d0`a32*P8;TtE4t@WwQO+WX$tAkA6J2Gi6K4d*$|kA0+Da
zpSq6t{RBEJoH%AOCWXfZk_oI_7k>0qdb;%|Sg)(?4C;ZMfrPvH=~qlfoh+{g)*`Y(
zXGprgPHI;U^oafh=%<#6=@M4qB+%O&IUFpKHorXl_Zd;yEYWn82Ycomo<&!|$yKlJ
z;kw}*;lbT0SeNudul{PD`dtI=D-@u8yk4o?8`M@j<#Z~aN?8FR{;I6i+)CkvUud-
zS6^;_p|9hHJw$6arlyIx!!r3NyWlJ=tO3%p5UwTJQ4V(=@@++48=?~Ww;>14L`pTq
z3z#C=2)tU5u+C<9=8$_7L9bSyE)ywyL*yr56Uhl1a|~sV_i#xL_DBB@?n$ktYP0M)
z#&`kFx|HlrQ6D~roH6_?_I2IRH+LKKOl;9r$n~>%rv41KWqU)Z^T3du|
z{GMNMDy!5*;?y%jiTMRcf%8diuid7MCAoaTb@1r&MMX%VGYzYZ#CGnZae_*{b6YFi
zym-?dojc-mtWaoFo{>$P3-_x*ytNU=7_z!4l-1I3GSL9%RX&CJ54X+^9%QJMq^rxR
z6NOUy9L=R1ZV~2>z?`-h8qd3D#%S54>F-u4jjWZzH!rPi^(_@X
zn^$n^N%$=EfZnRCRW!{hoI1
zx@J0{og7uHRvm)1gN{fMz$XDd#?Tw41Lczef8-wEiUbQN?|bKf)b<=`w>0|fHHcJy
z$UMM1ci?rtx}Yb{;0Nb`>7klwRS-=<>DLT`vzKMyZH8026!;hyTpe@m}rOFWCT~ZLanlg43b^E8B}Hf|Hy7U224p
zEnEf
zut6>}=As~1I)~?|%lYXJkfG#)n%-}>eJkkT6rzrhBs2S9SR(ek9BU-NkDlf(xh!A#
zrD?xT@z9sGr3E=RF!$0qVg>dpXW17usr}`seTFPCQ^s~x!<|Iz$~)+*_bzWrbKIFB
zE{lUXx4LH%oGWRY!A`ZnNhAYemr;JU*AK!O6-L1>gB!SJY(=N>i8}xD`E4`eC=#jr
zT_opiIu8-raAz=0|L#^kv7DtluP=i0C7-6>eJ>qOir-0}aYc3jPJdQXM)ecdNwzBl
zUEYLCn)a91vAN}S1=UBvHcC}F^Wc7n@y@mOpJ#A+0GX{?^giZE65PKad2LH_Wi_y4
z!OZW`2nV<|LEtIw4|MT{{lKwsjy=uVkS#K|0yb2(yw-+o`y}n@C+nN6+
z?cc(abgIbAM~gjzQ%ZkW6iIbY$;!x7y}m;Add9rBa7|u1X1t=BH$P);mIvmhGim-@
zRc02yVE)3zSxc69i%4|q7D)M3{DOt6+=V3g>n6KDcR>sOMjwtIAruxDS6M_`J90E%h`RjnX_nderl=qj6stvgW8p
z#i?RrVl^K82@_vVRV6G~uryY+WGN8*eB_d+`pS=S@q%RwUx>_nYJBQc)p(GfrSRdd
z@7a+tBjX+bF6aqk00DIJ3)LZt6W2IFsJ_#qwc
zq2VS48O9roxIU>2W{1QLoZ1JrIBV&$#cx0CjPY+|@o%c8EO_g!IT`$$y?MP5)m+Rx
zZ$C)=Jt-@5UWRH8uEB%N!%mM3y88ns$9l)Z@RX?&CyqcUW>lGSTEF;AW`ec)sJykn6;^I~~7?xpkQ
zXDx;|_Y-PZyp%^7SxeB;#c#X&f8m=MXhp_S{*BB9?(cbvm#%b|U%c4;T#`9&0VW2n
zQ$#Anq1h-KIS?YU2}EB0!P-A_i%Yb=6H`9y+<(vd!{-;Ly|d4ETy}Sam|f%;)br@i
zgA<3Zw0xYn>knlY{9+xCpVm8u_H8MF__aFnj((x(uOyOa4Q;93em5e@Is#^yIqP^{;D^sPY@ko#XN+XRnAn@$E0)kDs>S
zF+XUw_Pr4#x^J~lZ#Z9eV_3M(~ub30*zwAWe{nu_DCswt_TnsrBI8Ip96B4;@mT=(*
z%ersEe~H|X{OR=*q1V&Dx&89=y25GhxxEj*fBOn`|4;lOvR3k03-R>$TCXCW&u74-
z@q$OAgZ|H2$b0qs{G~8`ct4=F1Vc(Hu2h=5l3*Hp`HhS>v);&fJ5%-YvL$Z$?M=gT
z`zntv2V2CD1$y}HxxG3YU<;Nl{XeZ;4^UHAx<5C`O@da121NRFHxQ*lm8T+7UBxIQ
z5k%|XcHO5`jDWnYf+)3p^L#@{LJVk;jeo1%3f5BH?T*4~rrqZvD1@q2aYdwKePg4g
zw(E$Fh**{P`|iz6;`F`hj3X9kKQYD|jn2(t|e;qu5
zqN3u$^)w#{^Y2`|z_YapZ~cch7dfai#B|u1S)3P5`2^p9ysz~IJ~w9!vab^+Ev?|P
ztPIHFJS3LM%UQ2olLH@WLy+s@vnTpXIV<5E<-u@)_KobKyqsth_t&2$xKz^g;Y*)4
zTZ@UAoP`3>T?nL`;Ys}BhyV3K@&U4EY52NU{5oI8;`UU&vVpTdX8&wX2Hc+N^;e2M+BkP5HEBOS8{^9B45
z?P|f(kotTUIdc9x5X%T@3yaNWc$UF^8#Mo}&dy)s?>E8ELCXbaf#zSKkZ5axb`?fX
zPLVdZ2(FkkIHhazW(V6}pheG#_axls0`yk!^;GzytEj!?y9%BJTvxw?D)zD1mLm8S
zTAyPfrmvAaDABJ7xZb}07n1*N)XHVrg52D77(~=m?HCN*oFAl09fpHylZ$f{}TckAzpCp12ts!VU
zO4m~tr2c5SuUzoenZ_ByJHWj`Mlt75cNxC2Yn3Ho6;UUFG5X%^8Of3zOpj|1feTQTN*1y`Tx0hFa#q-3JOQ)KMI5d&z&WhdmVAru><-Lfa)|vre
z9H~uL6I!n7JjFV7HYbo*|7aii3x2=^u>M=D9GrOA*05+sSRRmG-PT&8y05azBX4fO
z7kAGP@%$A+SkOwVvL)V`V5_$^GjllY-Qhm68Wb$U&MQ8d?tP6H5NXoNYoN_wDRBPD
zS!d(Y%r6jj>sfR{hJAjr*T_GucQ~1@q!vi7TMbkntxyvxNZAqwRHS)N7ufdN#$x@H
zN&JBO3c$5DDmX=3kQ_m!cy_#^FVfZ9F~rh^s0dqjfVgaeSDj={ccTxX54R3|-as{3
zj2t3M3Pe^zlfj)B5o=!@2aYG;aXNuMyfDO)_5}8@3vXR7xVXT5^P4!}968jZV|`3^
zO4f2T4lEEnP6=Ym3&|Ry6tLGmYK-vf95o2>&{?eWr5Y1mtx;*(5&1`s_*1%?YH%oS
z{a5V&zFA}1uk2%Er$3oiXP|s!17m0~oy@ar>|FcgI9*seC&m9(WJnP}>M?OO9P9Yp
z{6*&C9vQ7FeHjZbv$FgB)GskRYU~_pryhY#@J43X`(m-O6vPZkPmQp58Lbmqe3sUe
zr3B~NggWCP8`-I`6FMWKOtf?O`FLBbeMxNKx$;<5`)NB>KVj#>P_i>E;aNKrFOIii
zwegyWN+oVbVjD~-C%(b`JjWsse+kPH#uo3rV
z*5(1M%Jdeq74tVRVJWYPg$<9eW!?N?oAU#adkg_%gwyynDeT*_Hjq?1cI*Aq_r
zLG1?fH``@|c5`ibk!|<7iX$;TZ^+wjn=6#+A`>xVrkt}ItR^6LRQpwTnND5JR9avq!*evZaCg&g@X)&N6@yu^6_yV?xC1?F}w>
zB&%wX+Ik1Hd;q2<{8F$K5b}QmpTWQr%ZW_tb?*O&NqCB+P*+D4R(9TNpkPt{)
zh21GgQFkKeM3#QWt-Oac;=eHhpNH|Upet!C{iOX(F@1uVF6*oumNxAS%7R5oj<-}2
zj5SUv!9O733`GtUTa$8okeVJcOqGxB)GS=wOh?9jEl69S3#I>aVYIFYTIBDC7APW-i7#--Mm
z@$!gD-e@t#eWbb8!-3yF?#;e!mwCTE
z@YtNwD>HBFV&?3lvc$nh_4O&u+=$8|d*a}eEK$`lW74krlr`+lT}4*S?|V7Br9S7c
zj4##v{sEVmdyd&l6W3g3cB^;9;77WBpfjjZqt7`odu##vPI>N0Qv9ie7BF}4B`Ld;
z@rE(f3D{wJYx?Fj+x6)*n|?O^2Xkbes
z9>1h=`183W$+26KRC^@JM
zPyK-(i}CkxVnIzn{F!#J8@n0dn0wHJ9QdoKnWXlZg53@s=*v*Gg`HviaS%
zca*@h3XE7oiYr}1-=V02_HT^pAl#kZ;C;{i7`bJiHDJ%mJJ%Fu*HgYx;MXFHZsmo3
zfosc{#J0fW3>>+c?W>{e>o
zEw@{FUMTgMJ9#Je1Ef-$T87LB>#3~DmHdMC%Hb!6r^efE?-_nliiHXMTmem?S0?Xf
zh=Ps(6|v}PdL1mv`y~A4!>~NO4R3LXt_jIl>2o^}v#rZ|7_
zz|OtykbGb9Pf7Z-B9KRN{!w
z;%%pWGZJrf^?WbzSpJVi-h4N6RN_6Le~2}ccAiMQnKZNhrtC6ekV%v43@8m-vGzg9
zeb`$g)h;q6Q~j@Av}Q>4Csfo`Oxir9JjK~IUTT5s(IYlz{Ijhf+t{<(M{QU<{>R#|
zB9mHit&G~S!VzmPP6@Omd)oE?Lrca^4sJ>G%3^;W2CqBSa$z61Lk#R`~df|}m_SAS=
zaXanIa4Ahwv5!_|nwo9gJk$K%c6P*A@93b2JfC6b(mutxPX{M9y6vhXO7B+B(~XN3
zH@L6|WY=u@H!&IZYgn*fXa1>G
zOxDttTxUA?-6~c*9lu>WOP;c>681;(-6e(}aeoHA!(1vhfaXG-Yb595@kRpLd8Tqk
zsdMzQPF_J@b>M7&;CQsUL5{bD)ieqi`v?}JOxbbkqQw+qa`8r-J#texkBwI~?ezY;
z`zd{|cuPAT3Hv%ybRUeL?o2-5ZlwKwie{6U^(eliU4F9bK*RRPZes6Tk1QYDN9GYX
zW!p{SUKYo~cfdkrZHZ(&PDuEgT}`!|FU5E2=h#uz2fy%E!xmF#LzM{#7wp|3SvYTMdj=CvUJG;A$1xlzHffY@|f;)uy>YF
zcF0a`F6geTA~Z;F4dRm)PbA4|(L^aZ>p`3bbs1le-35;{OF}r}nAtL$>NEF!udsS1
zgBdjrob{jXY*NXQirsZ!@HX$k=_t5!p7vM#@p@)ho`51(;Y=#owiD8*Sdk&3ROZ_6
zr4u>ME*&>WG!@3$}Z>Gmm@B^|h9yi=XY(p!`?@@T#s-L6H==jh9pP?TWMi=Jd?(@}B&DhW6;n~NY3p42Xi(jIy4J|CeR_!4Ss+kK>gp>{{-#Ao*
zbMY*|qk{3_VQ3oKp%C6@55v=z>Um?LBbKB6iyI^D21-BQgWd1<(F?uO^YYCXm|wB8
zN0lZUnPujT<-3E`TOjBrkKw-
zk9NTorECHl$PMIv#r=i-mitcjolG_l(HeZ+;}C1^4;+uE7%4CJ@9WxS08RjUcbT$i--V>8*ksA*74)&>%U|FE?q$vcvzz#WZO}
zo1!e1B{^$CAWznWK%OjpzFkKXW
zZ{YU@{Ay=2o$ouvDf!|azoaUc(oBBIQ6Z&ywn~!fcamh4k#+BI##+*QbgxGj@seeM~==F`lkpCB2&I
z6F5=7L3$0-zr>i5uK%6%511Zt=;uhkPkJNM|B}Me^lv5fCek@Ue~$E%q{{?-80n`-
zmkatx(wj+F2>LkETS(^xeJbf5(v^Zfi}Y5~Re}zvpAMABdW6+gRQ*!Y4>0{i1a*bx
z`1B-B)ZZW-{guj?Fz^aV*9-kKobr!b;nzoyzCLgrx5(Ik26QdyC8VQ11pS5jHk1A#
ZR@502VmjM=`beL?m-Gva{u+cw_P_hPaBBbn

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_release_v8.0.7.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/boot2_bl602_release_v8.0.7.bin
new file mode 100755
index 0000000000000000000000000000000000000000..c3008f36d033416dd7af9b7a7d1b9c02bdd270d0
GIT binary patch
literal 42096
zcmeFadt4Mp_BdMIGu=IdC}4v?7URGODr*cnDoNIu9-IfDA~E<%a3eOvxQX%o+OKZF
znI0Gwk+g^;y1wFzZ(@{*PGZ(DATNzUbQLgb63qz2WOdN+P$Tj?H9aGk-S2+yy`THJ
z|6K6{-F>R+)TvXaPMtb+s*E!vB@+lC!vupd01?C+McuNU$bLiKjfiU1)JB>dh58VE
zh(8ctptp#h$)8Cw84-{XkpxNnH$ja-_yaxHy{mhrjO5_AbvSWEendVB#Vij*KP?>c
z_hi5=mm@+3`EG>9`~hiXXptEz#Xl;9Twi|to%{WN`LnuxTFC#B7yxPTODwala
zx3lzw!G-3G!!;1Qe#_+dwMhNs_y0K$v;h$nQRQ@1wAr4H)P&x}p_TZrYOS)Vu#V_%
z$-MgY9)T4q?z_;U$t=YUDs;G^Z=Wxny?9T>8AsB0ma6^bQ?E?_=GDeO*3Z58#)UuC
z6B>VU1CuE3<9B7as}uCdeRrg$vb<
zzaackkXniuB2j;hdYkq2<#_)6J{Vtw<%}R!cXkUK)I=K!OJLt5Ae`j`LO+@Cl`9Ybg06`#Viqw&Zpb&cxaaczsKTw
zk^~pGC{55gmDE3_G(83F9jzwhNF60dS-K1_CSRyev*4J`JW0zh-Hv`Ri|e(CrhPsr
z%JQlpaZPoNIPJmG&xMj>PTQq)Z)XUo_lMa%l=j!#WyUC^4PeIv
zA=cR0O+ovcQOH!fief@8xRS3fCcc*P3PC`Bv^HaHPzk3c)@2g@=)OK
zz@9PSc&^>enJhg>%~R0c-^IRx)OL_FHx`->6NSn!NE-*{Jp*NQpXb#F(Z41N66-+Tnd6|7pnY;q5S)ek2kByKHh6VWW=8#)W=az!QD@
zjaI~j=*LEzXWtZz>ixG9smaj0@ASsS4Y3;efHq$bzn(c%3bY75L%p~&qh_5q8MBDX
z-5Tmcz#9{SYaU+!<8b`*H@E6z+epL;8;0&Fa3ROL1N2(MB>#v4i7rQ-$*3hMqnOQf
ziJhH(&IO%q@%}KnX_jv9-feU?Rkw-M%cQriU15{_S!!dn3#tC=MLSDv_`M5d{yE5w
zTQ@E=%Ya)J6GBY>vf%dUX!F3*EJIAlX?T0F)EOlI5oS1$zFndDAR8l*D;b5lxx#Rf
z8mgTXf#=1Arb{iyM1~`6LOVGwbbP^i3VL*a$++9yC+nFLg{A|>!@JK-QYaKIRpv}P
zNCoDHe#DO+UeD=2)ld#&M`~eazy*Dr-qQ=}=&Gsu2a2~*02N>u@8Q85Kap}!KPrG8
ze~HJHBcOc?ep~1Ga$C!X#O@Z#uwICV*?ZBfXfw_avj#=Q=p#)=0_{G9A$Xirj#?e*
zZXLx%jtd38kTD^G?#qIVu}&YVKKvlz!QwwnFh-l5sH@(&UhdZC7@sgY>lr*2@yO2f
z#eaA8hk439BhBGi$~=~Orq}pqWlEEy?N)l*WP*YpoGu#oW4|C6@oA(
z=LW@nc*@q=*}udiQE`Oi2lPW?$WSESRglvkG|=scpP{Mo|4(v8Mj*i|7!Kpr2W
zAbCN7_*br?wZYLj8d(!!0iTVQX?d)A{M63+SvJPg&zg)`xr2_@5J7njVeFphz2ud-zRC;fOcbi3_btcq3{4M4M
zr5H~Ws`Qk56M6G~|1itI>zWB0-K;I%x_0{7LA?AN;{TMZ(P)Tw`%6lo~tUC#F6XPb9OpKVM
zp{8jsBUDkT!>t7O*<-oKtURfnQTg9x;X0@KCMKkk!d+@~LwL>(0AUF6ys&Z33~vI7dB
zB?{#$oKu+x8s;j8Dat6dWmn4tx}*^6TUiwi(m+EE84vltGbqb=+-j=CHD%Il$1y)X
zw4N4}Qr)dIuc(jUZ&lIIa+>c~-;e)im0YBOtA6!QLkWr}>s9;;Js|?8F^6S9Kjt#;
z!#vHm8Hv593BDuI;$tjO$#1JhCQPGc7|@ttKW@!3zHHCZCzOgbNAq+&P_dbIhSc9@
z-yDh#89s-$B{NRn`iFcIt`{*pQ$GM`VVnc%@5=To5NnD@0Y5}pKnAm$k&UWHrb-Ik
zyT(szMf~3z(3dchU{nuK^efKRfc!2v$jUOAGJ|u#8*MD@pxKS_h__Vs2g`@%->d8|
zE+2|8UjDCC|FlgPgd5|Fvwz6BXLDnDNV>NEgZ$L7Qheu!L9a6;Fp#c3T)IRj!!%Snv+ktidd?%yST6_(L1jz=2+y(0~qSk1t>qP_vQOH6R;vgwtd*1bm4N
zq>Z@*T0|qX08c78zUnv$H9;;7lrAoOKd1e38`X~ZyLv*S=y2;;btVPvIS=C-C_pO+
zioR^`n$8Dd2@XNwM$D-)1Ln=mW72r4bocb+&q2oIWroQoyFzCl-ECNKERNP%E+5rjEWHryhDOPIf>$5$sY9>`qP{aWqanxGYW`bv{l#oR|Rc3Dj577LnG*
z!3g6N3f8QhIJT;NyvQIf+QPRTKr9V#&R0=*1h0_h3^S?9w6eijT0#%C=+3
zd8xPnm*azuAy(hfy)M&aq>#9x!!LZ@u{>-6Y@a|;FK()|hiPL$>GHQ*$iRd>Ojuc}
zp3ND6W@^<#DdKpcshU9%kUO<3L~CjQ4Abo}k9CkKTE3H3QuAPxXAaB@%I;5}C{(K`
zB7jzJZbu~rR^yuU;Yq@qg3;a&5n_%aGf-<`G$!b!+x4=Lggta%S&E)j1fyhkO((XR
zU?fM-C0kRN7P&
zq7*GV<1?gTI!XR^GZ|9$c*g0p`2y9V5T
zxXpOcNa^|ZX4F`X*HP;-LtYM>Mg&BhrE8R8JF)5=ffmZd<
z>%@w!G6Re^Dtc?OL-wp3$?Ab$BXo$JRtj3RlC&^<>tRyi&Ik{J7u_SYwS&Zb4vbILMJPmJ0P^+7(fDmRpBNm3e7QY^rh4Nb
zw(%H9MWZAY{}nPslMTGiKC#s;74J7Z9ctWR*CYo)j!sly{4308#%E$>h!BjTqE!|GJ#Q1L(VhZ+@jOxy4_d=96XZ1ry(eHiHW}e
z>k=~&Fwz-Bow>u!)m_lVC6pvYB)*qOfn6r)i%VRJL(&&=tSZBav8X5bN{0}XF;>s*@RyBbli_V_o0mF!Ia?EW*Q8rk1Do28L6Ju9aqT7ga#
z7_E>;6YNL)rI4bYt2tfzT#cB0ygQacLmidp}GA|g{)Xn-rll>W&3%s0(
zG>Xr-5J!r`jTQQWpKDhHaN-!^r}^I0_NHGS|Y~91NGFJ
zn#hAvn^JW!gSy)!Ck}gOP{+|yx8z#fl3R~wIyq602Ra%k+ue(@GeU&mYW2I<^!cOS
z^5BwsYY%;5Yl@@5j%RY4Kxx^TGhjYuw1JLE4onT6dHB|5kFJ=h+e2YnMGewD*4^7D
z3MP5RWwqMNuVzxFHiIl*>MhHEZHZ7152W7Dp`1!sbN2JTgo353v
zUYu0BW4^R{6W1$mQEzE{#t@=4;TB%W(e;UScqJEYK5Q<2pY8L9%;KUeoa~Sp{04G)
zz9G~wP#+#&5O3A@oj@fGJIE^=M)OV0zPyh;hG*uD;t`|bsp@B)*N1e2<_hT?dnJBL
z{3;IgJ?N+t*)vlDlQnb$$G24@O?Cs4Mf%(dxj0T2dW|n)#WQkiGXyU0noHOk8z
z|H}|!ymcd&Xh|wKUf{Y~`T&<1r%Np0L)%BObgN9cDNCOODTD5shWOk%Q
zACbF%x_Fv;S{CJV%Qt>h5kKeir^o4X^Tt*1_bbQt-K18Xxm8;Le&(x#S}%RXE2|ZJ
zMzfDIAh>-SCt8BhMTcZru?*_R&+U8)u!0}VL5`lu|EVJiRuaJtu=;U`^5{AEyg2@+&&~hvJxtS^amKH2Y7d*ZK>?M#HFUlAE5^CHll~+2KcV76v(<`_~!YVF(t~5H|
z>Ab7$2A;S@s1n4Qde=?!D!Z%7T2=dE`rtF3R^X
z<0@YMya(rVI&Z0Q6((b#{F+_Nj_qQz!KVR!+21T5DInXS)o
zZT`8`6h82QyB~Zf;oknE<&3+xU#bjC-W;ELb`4kZf%@PwVtkQCY1OJD22=b1rO!B>
zQ)GTzlkD8g{Fur)cQDOfSq2`<*M9j-P<+kDN3Xyr)nQ1_&HFyl4b2#PH4QIY7Nt43I1zrrut+_y~KuYgoXN6G{v|6Usjds--_
zpW>{t3Ft$c{RmwN7a>IG-qVo@*gs}9I=8hwR1XJ_+Hi`zWEYu5B>$tG)&_{3K}g7o
zsGzH?%*T`sd`~80rOfwow0Xx@GiL?p`E)xu>7vpIqmB$q&>nAv$IVN$V`U;+kImsw3Jw
zV*M!Vach1{mXU}Lt5io(1ly-omJ7bJ`^c2YARPz(V%0s^d1Kq}Gg){iN}j3<(S4nl
zke6B^7Op2kDz0Vol?=)6^g(>C91YYzZatC{vHgfg9Hsx(zC*5aIP=oGOhc5&c`NoF
zp+8+3m~cfqB3m0^6B@X2vm#)=dUKY>0`_BU2coNr3l$S$8vQ4&X&eg@@X~`4PH|S^
zmNq~(L{MJTZr4Xt$Ocy`qsnnF7vzO*EH;m@^1o!G@n%yb`1u66PlV-o!3$7+XMt%*
z0(hRxNnH79c8&ZEHS5WT$@bLmi}M^M9LHQ3t=_e<5O#3ME-h(3yJqn-56h#H#2qo)@Uo{e0=Nxkx%W0`}0>#m9qx(lmDzPVZjn#S3n!hYDW6#iDr)1bj&e}Mp>5xvj<&)+uTR%lKI9NRUHEqFs+r?viUV2*tLajn(!}pLAm@L_
zfW|QUeBL56Zt;ORgP;<4vQz%zL0rqUk)hX!grI}eWHtJb2!**O9f^<6V`~wjMeBKJ-{tYOZf9IUN%KmC|RW(T6jB1
zJ>pXZ=Or|ji!v6GRP7_OaSX|odB
z_&3M7qZ8Ufbg4Sa}^LVRM(R?eH!8C#A2y)_)=V~3a
zJ=*FFqy8xyQlZ4S`Q{eVt%0wM!#0ImbI4^NGZdDXtk2iZ=$c_I#eaoTTsN*4d=Ax&
z&yBxloV>_w(>d2SUk7Ugtc9}$)PfTrE#$
z#-*-Gy`1OV!d!IQu;|bi&=M#EoKz%xN|bDsMah-N3!&!}>cQ6)>ZmrwH5@~7wR9&g
zuO9j#?1atG;_<3sW`M_ZG|+Og6!aL_+PLpst*`%e-xu3CkqU;EjW5JrIp<%QM(|!T
z)!gyI+zq#XmGXW6K^pAI%OQe5PPwi=`?2$PRQ+!Eh?7RFQ@Q`be;Tn)w&9|8#2z(b
zDcpy9!aZ_vFT8v-C?Uv(CF9;
z`E`kYZ@&T*1?_&eO|AMcG2ljoP@p1ocfcaSJ{dfhVy=9@waXsxHMR(%&9X=;k*vnFb?_alB~HInTso4D=N*aFEHyDrl-
zRFBw8(~u7(W-DN4K1@r++Xj7x*uMuMv9`P0*7*>Dx7^=H7FGu8z*_dEX^0HHM|FkR
zwta>I!9%?ti8Xh-*>`Cg_CATe8*H6-5&yKGToVG`gcgRdb<`8jBn6goQZc%UAXd-X6D}
zx|jED?#6P-x*B1QDu-FzSEtR=M+kIP;V!%bqUtL$=q|_ry`96B8d&MSiY*Me-SM8=
zYP)PN`T_g1S1(SilMT}&y!KA2oqmR{pL+Jy8oUC>){d;2@)=<+u^u;z_d9WI~ZrsY1YIMu2f$oA8H#QOL=P^)Ia+r?
z?Tp@VcmwOp(U>w}!)2EYo+g9bM_k$YYf-s4kAc+>Lx>IONNXx*)Dh1UnCthD*a8|3
zKilLF1mpf9TnC@+LrQq(+yTpLgV@K5cV7#PMsm8PR+w5K<#2R*o-SQ@}|%GPF*y{h_n#=Z<@&
zp7K9x7{Q$?Chx;D)yjp$~se`W}
zv7+!(WRNCnL)$00%gG^4{wR%tGz!W|X*8tKkJ1=O
zgZXTGvb&rD(iD%$$`flI{R3oKPeYm;b_6gD$j)ExA!)BAd0CCzNy~{s2
zWth>%G?6)6AV(SQy>DwcKo&5zh8A)r7wB01!AwV2FqU=P$CvZMDoj<&P#8B8d@xl$
zN&~;C%7@=Vqmv)J_<^Y^1+Uigz`o1Nr}xm8@}}jrujm@ko@c5`M-}Ko9Rg9M3_xu>1$WpKS*_?>edd3Wd@;pAEZ`~(6#P0V2RqNg;zSv&&}s!&
z-Jlc1O}0RXA_{u1AMt!A$hAu64qX=k>&G9MzbI_bo~f{|{W=fxJOak6TGc)p_Ld<|
zD@+TmRfUzov$OO2Frc-kZn`$wERC_N2k;6}(mwJSuo3->Tv7_Rzek5eN?NA-#)BS;
zFg>Z-aHH^sdKVL;-qjK#JHW(D%foNDuB0jxo&nsgjW&{&
zPTiq@p>BG)DN##ep2>6sS!|BiVlM^o&WfX5rsqtp0Nm>%Q&*&D^+
z)2Ix3zH>Cc$p`8Qf3bHx(!N!ft%nodoveRH{~QnflQsWJf0?E?UMg+=7d<#7e*7o;
z7xkh)U-O^n-~ET)^+?pd_;2Xf1|&M%Rz^is`S_e@^OxpC0eV12S6v#ZRw+m4gM^LL
z#Dkqu!bv`irlZ(u@%l5S(y7{Mn@Xt3n_y4q*tAXRUDcyOmPZrkBx^EWOIO_iugpDiYt)Kq|ifVDvfni3H5beERCLrF}dsR
zXm&b8-U*7)CE5JaYS=NrdRA*OiscfD*=-XaSF`tbswWx_v8~oJyBa+D*_#
z27NYr6L<|ht*qfhD>J%%Yz=pMyttwQ)A2zE;;&_skN2u~if9#*b<3ctuiyUh`
zVclbynw=FNbq4gO`QG@)F(zf7v6LjlB}}zM2@#1GbQoj!7q~xJbJnC{i-NQZ
zb`)5UFRcI48g9&zFxKPP!MPQ2)+%#c>TQjJ`|c6;wSQ1>-*~=u>-F$e@A=xNpA0!K
zc)kwlUxu_=&)3KLS&-(X@u+?ur0w^leXai((jrnylD(0H(*D2?mWW9b_2>2av?5!;
z&BtTeEj)Nl-hv3+d0!s`Z`2@&4u1n;$HAY1BYRoeG7-{WhV;pmcC72@+L1TxAYo#5
z_TuplJ4ij2dDH$+MBF^Gof}TE;tBZ1w|Q0f>ck+4oLYNQgZd+jX2l?$0bezya3=k_xHeY{xX1DasGWh@XtLp
z9K-oP>4BGd@SMc?5BI<^9xLF<$N6{lz)u1^7vS#vJ0FMV102)2b4L&S804=6IIefl
z_8z#^1FyvS-|vCrcH#UO-kbhhfS(5VKAgX>CqJei!%yS8on_X
z&fP6`e`6ZXV7rK#$X9!-@4degH48|ofKQZQ=P!H%TH&-y`oo;?f
z{eUs;T(96@7h`a)4)d=7a^kU5peKQ&uGUZ5p)|m~BWH&P{%o6q!#TV>$7OJDeDbgd
zj-?gD4*~qy+X_yq!HcQLgDKA?)ldYvr7~~9oV=Oz|*d=)0KP5QsX`KJ02an&+
z5*&}I0)QX&;=dumamz3sZwvgO1>Tn7{QJE5n|ttMxR(=tO+EN=y&rq?JA3kDUGce>
zo*#Pf_omZJKW;DXT`wQ}zL)aj_CA*XTM6#X?`@ag6$y^VU~fEm-#niG5q~`NQ{OW~1a8^eAwT>5*s4LWYZ`ipG?hReN&X90CAu4feB0cfW
zYjaaCq{huInH>pZ%t_xnODPw8e&c~N+xQRX`^*Cv<@+bwoMPg&T%A{1a6e$Fz_NMn
z+-diGEuA@GsY;`?j&-#z{7C)b?n%niYP1FRge6N3?-jm0?NaHm#c-~yKb$pVSsH=m
ze0Y71GD{CJzWw1W8VhI9SZp~!9B_X)lg7e%G#1XI1-Kk9{ebhs3A9j`*sENRVqrge99L`uIYH<(Yxevo&E?U^vup3J}^p7;Q
z-7Wfz56+OSod(gvEJP2pCZIqzj9^W}%KFQqv-+E&wf$wkC;FRyUluSDc&6aOjkRw4
zSw>f@tFbpOzfYaM8NbRZrSId(?FXRC)1keju
zvta3SWBXXa1tjhODAw~hcac7+f-Ikk^~kjz>&LC%&PY;PU<`0eBZm3G%;Lql!w}%s
zbDw;Q+q6ZA$1Pw1o#^cmT*6iPuUJ0$;9s#!IpW3=Dq)!db>mh`HROGXIc)zguxtK|
z)Sy{gr8-2*hAc_P=aqUP>rIlDU-%`Sb0i&#XMrilACru=9(noOW6*ac&Hl*=sVp9Y
zc*e*p!S!!cx>~ynFqMG{sa6-%3SS{oE$vy`hnxS9ub2FQr6qk~9DeZS#Ube@
zNpf6Y{HFbTq*9*#-sk2o_w;+`-ORO4s0zvKCmvAM$@D50qygqU~X9-jT}E{YmpJBdFOO*nS~$0
z_%;BYA-L79?O8^w-?oHkn0pXMza=hYf^&QG@q7lKdL#5FkK3!^Wa&zf^Liozd$wTx
zcm~_lu!k+TGh|$BHl)##*NbJUBSj01_@5g{>VOc4@4Zz-vxGRQOhUi`!d@s)(+h2D%?@AS{
zUAeoj!z%q=*8uGYcfW^P7275(&)aqid)Qd;umMD`Rxt=pR}AcY=z&tOnn%#q9W4Ms
z+}au7oASlJQP|JejQ2A#CrQsa6PM1B$4KXzW0xZ}oQI|a*!93C>0ORN|5!R$H5$Y5
ziN#8b%h7%Lm%;vS$bJmTb~(Op{3SBR4S|w5@ZG>JYkO(8kq1BX$436CHk2=4x;b!k
z&#Xo4(gu)KzYI~09$z&|4?7cb@G86nkxa0^qYV_npLha1yF~Tb30i{8#`E0r#dP(6
z%BM~}T~_?v;VUKI9B({P|K-K<3srS@YCF!}Kl89=U9;u-`X4r3?f-DVgQxC4eK)#e
zMBAu4V_RRiHU6J*KN)^p(!ApOpMUtv)wF=6k*d+ZMEZ}8E+65*Z7+BU^M9SbzkccF
zpwUbHBS(i5C%EFcrzWhQuwq*CwCU5UrjMPmf5w2BmYFM(nveBM1qn7Vk-haiq6-(y*FmLLc3XQcAu_?1)9y
zGkk6{>>==Z%_#QR;yzI8@+-K02fPIhVc_j5hFO&oCAmhPXjkw*93Z90AfQFwE{8MR
ze(iFIPKEPdURv^vJe;>JF!Da_V7XzxIHm{FaHox@wq)#j?Z1;
zFKcWVx7&o*F>q#cT06PcPU+KPrSfH_CcC{8%D&b&tFN``SZ^NTu?sP#WRpLf;8}P8
zx5~H4H`l=XU4m1_{Ch2OFKq*jyrQXpxRLMMBo6|vIJZdJ0(#NsHc-f$8UFx%z)QGJ
z3@gLbFvAYwnzz4Zg&ajcQ~FCUx@j`**dWn4+3w|2lRXwnh8d5VayR6=!i=B8b4N90
zgqXNZEy&AZ>eiF6B|}k1ld<9o=o3agDH546XriDdLeFBi91>W=rrQGMan_*vUZdYG#s^iVTf^N
zw{`5+@3XI+cFm4Gip4^-nKBUIK~%=7WpdbWlq0WHVJ}qFnGxWdrHqSU2Or-EK-ZF0
z61|yXiIHs>g5b7|%U0sf(Z6!tTZuuw)ZC=$j^u!-oNhfd|K
z%N$`LZcspLnFnUtB<=X&aTBJ)>!p()gjIy;pa+C&AI#q5U-3*thz|C$iK45pul*2H
z8H=T|`aK;1zD;RFUYrP#-$9^FjP2d`HeLJ*{!<_Kzl#&6<<|82BJ|7i8oz=vG#(MO
z0x;df^EHmHRPWlaz#|-EhjWLDz=?L|L3dYh*QUU)0w=~Q?sl&Yv31ZyEp;h3YejqR
z`CQ+xLMGnJBP#8T99_=C<35^hU
z4|&7+Ii2zxI3pp^w(EK-w;7`K&lDzZO?7N`fF8fvLgHSO9XO2ycg#2*Nf42biXbAs
z4MkTKy@cB{N-z1wahvju-?~RHu3csfgt%Jh$vzOPNX-e4jKzPwV|XtDo$=xhHzvxs
zSGWda{gPc)9gu{*;n3^-JLRxKy9tp?q=$PK+3YNX%ovMAcq+eYoJh26n-XxU@vAEn
z^G~gV^Y)pMFI1I)r=YWYY*kbDrBcihSL;hZ-{J6^B$XKq)-Eu&Z-D6Ob28&4h)JyU
ziEzg#KaX*Xm>9fR8=P9K7D*Q-H)iYsDK
zfT`~Wbyf?+gQhT8raOkPN
z#!L19W2IZF=&Go4h+{@3T_rlI-@{bqnRHDMFI_IjZ|&#@`L`QA{ZYgJ^+TjJz?wqP
zCb*95{9A9I7Mvmv|JofHN7qWR>LSRisVWeGRa4MRYmKbDRmJyjrbk$Dd5E??^6s%j
z0pf4bzL%oS!6lxX2xqrs*=Soxyh;=nuLs38F_~&6`Y>=|#u`H-JF&KZW?9
zO3)DejdnP%;vCTM@T37sbanKzF9WSC$k)64Rdg}*gnYe6*MxX_sQ|}Ee4U`+de?}C
zhgN#hMVv0Zt3(?_U1`R&Bb$IDCiWp``@IL!9aZX&h)H0tT~Qw7-W^%u%n#O<*Ms$aJ82H6vo9u
zTQC&3*vL{98=$vVL7U)BqHj(g0;Ht7jWG7uJue72PSd?2c3Wq=a=hHfGtKP9`^(Qb
z@J(=*sy!7+-{Je<)VpZ74Fzt4TYuafT2&$>dU|2kNRTO4uN%4QKKXHX2Bmk^J^KU1
zd-bLKsSIfEkI@xW23bYcxa#s+gn7|t$g|^XW3i_Ven%P0u~vmO$5$Hxn{$tzdSkjr
zf9>kO_@*##d<|Lk<@>`CoNaUL{B^DoFu*JiC4@ekU<6!+m_c*_N_nYr4ByUC^Ij-|
zyA&McS$*AHgR+)a;5^T%zlhy43#yGryDuF@)PsRzsZt|Q-9o-DP;{&^-uHDouuJHA3>c2RUK
zw%-Cy!@Yo@pFX*U@1&Eo2EJM7jDDq&n+=KAV1t5c0>iY@PIbL
zy53Alv^r*B2*hcF?3x(~mN}i!&$eSZ7-8P1mCmgu)x!MbFUspw{10|{J{1k~a*4OS
z>AqZaRe&L%+Eef*@N6MOL=0>ajQ$WMt^p{K?)v_x84@T{~SzNdIsORXpR4z-GyW!|p9?JItzTFaasy}4uqpdy=Q~&H0kug)_
zD_F+t2XBl>oBM_vfG32HFun>-iF^y|GEblC_k&K{4itss6<8e5E5(*eIIoVeQIT4y
zuF3;o550e*bfy;UZD@7GMYER+_-`1$TW;F%+=jKWtIn?j-(m;9tFdQJ(%_CSyxJMx)am7v@R6nJ
zj04})d3eL9jr+@!zLW0m#P@c-QyUvf#=&^o1osU+gHLHCgu9NMD}hy3W*;>2I<6f<
zsl!nJM!5ekh?fg0;CR3Tm51izz@POX^Wp!h$)x)|?@Y!T4Kz!DP5Gf)Q`Ew&Q~3$>
zU$$wVHW4_{C&@EQaE)#VrUGRyjb6_OQvR5C!n`c~_$@F$6!whCDIbVTLU?BNl?iOF
zvXAJK5T3i?vZvpLqd;$#gq@TB$%B2)1q`8JeFOMg2c4YUB(*^(0e$i?!0(=jpUdkNTk$^i3PsP?^6X
zLMNPz1v$HySM-%9=htanIPE^7bonP``+W#p4tu4APhCgyT1_AO5Yz&;Z(ojo^91+{
zF&AFHwD|mFyUjXT%fIp>@skzTn*`^pq&9J-vi;gb%=220e*9!-(w3z6%j^L^O4RE=
za~*O01Uf97IA$^?gvSPwajaYye)Lpos`Y1BudD40>W006xO;i2S4>8oEVmlgBC-N!
zNUFb1YF8HYi2elVr{+ni5?0|P(AyL_6fBZfzg+zHSy9;}(R7sud*&RTMOVYwRj=;h
zy5JQbhuotGdbR3wsYu~FB0mM2NKV+8V<>Zihf8v>Kl*-nUurc~lVQ&?
zju+sxOY!a`_2HvQ>W|8j)@6oXQ-U3bqj6!SJ;iiD3H}kV32818`=_EIzV7*qb%of*
z@BRg+vPxYfPCX+On_q+!IHA<~`W?zxoXzK72ahgaScnul(~yctZ09~6DX7#tx3$3C
zi#P4j*~3nc5(nqMyxMcuMZzn5p509^JX8ps2ojX
z>EQGQX_}Fa`0H)pr=boe37QSdWc!BkPe;lUEf?@Tyt`ii$G|3$>I2%EBli@5t?3^5
z=sQ@8^}3r+im1cZksyaVCCCN#AUKJ<{0yF{y&jI@>=EW5{k=-1k+o9z?xl4tz9quv
z^Yc%goG$|^&SYol_+PG*;{}<4LZ&LXrz_hCw=&lI;JQb6bkdyq61|(|t%W2+t>}4I
zA@m}rTFWCT~ZLW47g7cyPE8UAJg0q|dU1Efh
zEnEfHNoMB3uz2iwIo3dcA3eoga(SNe
zE7N|R;*l?FOEYqAVD6`K#7gW{&af|TRQtA!_kJpz6~CK0^NQ>Mod2w#jOwSZlWb=Q
zy1WUOH0>{|WwXm_^Q(?-V5wx4GZ$`%nBZJzzcrJ~1;`xL;tw!S65s{~$!lAjEvtqd
z3uZyLMmWH&4FXSbU(kaLBJ=b3gjN`@^h3gEgS!A<5Y}aCf-8}&pc28J7doBWWtVnK
zW&UMk-wOlJ_4_mgJ=^xH;x+y3*Ji6Cm-h8R=rsd=&v<9qlGOlFy|Zwc>WziV-%0;B
zY5x|Upi@PrKVIxHoKpIuqDZQHYDQYR>W!7EH`3<6jcfAKG4oZ``~_+AGCVLhoe2x(
zsnRp}g$ouf$ymD7TSTH;w@}Kj;ukJj?Jgw2r=)1zAl1?(yecg{-CZ&==DAhF0oBrF
zzX2^1mKLIc>?Z`OD@nd`Gn`ZSLC{p00Sr7zw90Z_00zJ-p_Z
zFI~29fhuMdL=&u%_~52hqMml3x6g;Pc;^zs%EQG*a`z=#ejs9F6<9hv~(Sk)C&{|CeC-0toKDdG6kR0rx&&l+rO+B1HP0Y%u;th9A-4
z9vW^^kYR$si0hNeV0K8{z^T1pOEQ)%U-HhQ&Y19K2LG07>cY3*o}0$M)sxo?QO(25
z^Y(+(-;*=a=clRW;u<{IJnZzypu0bC@+j|k7@9O~(xhPs#f%)K89iof>~qg+<0k0z
z225`cENw2Ip792Tb%7VAfa#v8Bm%a**2<}I4P5a(GAJ&gk}@N*lNEa)JAqz922;b^guX?>HOsz(@6Z*YtXK%a|w6m|pO)z233Np!uVCH|}Ng
z7i27fH}?~2Sh9>qX&Fn=vL)}h`+w0}X=r8IGXBluJ+#GyGT6FCqfG6_Up{?XbueTz%9z8h0Ex7kJb3-)abk5#%*BvHf#Zb5-64@VvxN&k
zT5`S(|0Qxm;%C=SgkDem_RcFaY73^j=k{Ls{_QK&{Xg-C$XLZ^EW*>{>phBi0iOnw
z#)}?}4*EZ15%1OS3zot3;r)Qx;tWa2xKe5IN`PtXl{eGg%6K#FopjYJ%a^+4wA=t_P^8E8U-)xwRzZ}~zInbOBq0X0$i~0bZUt+p?si9EHPh~M5fnnzs<v|4Vr&fXXmf+_nYA7pyh(IK=ZFqNVK&;y9%Qx
zr%0Py1XoNNoYJ*&H=#e~Ez%lBpI%R2CWz-2^jJ|h!MzUlF)8pDhAcRW8
z3U3r%FuqNzCupPCTyd
zs|T@+`J)bkhc8sKtIf<0kR6zgFK&HodF?i=xiLLf{^x~Dd*fp==GyDi`RoH9M0A>LhbD5}S+O4<{5m$Qycbc_S~CEg
zBX#L&Ld#X3qgbcT<^=NUAMGQ5!4J3q)_;qYgX0g|8yC$8%LCG@+gfK-_f=JUup?``31smJ&R7ru+LBS8u_OU4ky!<)&a?NtC8xX6>35SDOl9W
zkwaujfyioTGT0L%V(p9L!14q<&J~~!&kwPrJ%K&!!&}!2HZHK={3Z@KM-KJqSRa#}
zl(im-0}lj`bAs6NLb8S^1?+W<8YBEVM-4(ebQZhvQmu)u)~Ylei2Nf*{7GGH4OkSn
z{3~{V->fz5Q}(g3)1OSMH&8yZfiX0g&gNM*cCLMLoGvV#lj46XGNcF~^_aLCj&*!)
z{vva6kBnB8zKjK%S^52b>X(@9wRR4*Q;)zVm?JaneX&?s3gU*Or$*SjjJ64_K1=J#
zQi5}BLcQ^zjqKFg37wHqF4{Tte7r5zz9csATzRaj{j{CxpRjX&DA}2o@T?t*7suPM
z+IUSwr4qX%@eL+a5aZxJo?{V+avx@HJj1nw0byX%XP?JeJuk4>N>`i50Algr@wIov
zSz89eLQFX<@B^7MKEqDuCLLyRF9A;}M7LwVSa9)Aws_lw3X37axQY>$R(Xx~t%XGM
zhWFx{Zh*CnlN+{jR-=LqGUaXnDV_NlJ3uT*!N!%QS;UUOnKF6E3X(#fTq?FpwH
zp>~7$n{6^eySYkUWZS&1;z*3o8}jzs=1Qfy$VA+jDQE2ls|m;*)jri-rc>9jRc!95
z#fZ=Z-yz)_dS%yrls}2KT;y~i)yz(Oio0(x9hD5Z3&hQRf$OWL5lCPmFZfsu;WElw
z4Xo6L#op~V9tCnwlvzz9Wn1Y
z!u}MbsIMUBM3#Qqt-OacV!$y1pNH|Upet!C{e=BZF@1uVF1u1SEN$9plm(BJ9B-*4
z$fbmQMcbC1j@tVq{F8_EzUUCmD#%%SrE0(1Y4kqd`4F1+<3_Y7qLV=$cZ|}9c0Pct
z-wdSrmR@T85lHvG7o^7I$fr+8$|oGU&~B1S1!=82+ORH(A6HhoE|mVyh0(gcybi1s
zvn;7oP8wU~b&h^us$Q9L{1?q6PicGe6kVTk=D*I$jK4F^G+Z!vzv*~v-g=aISGGKk
zG1ePb815Oozi4^n-P7@Ch4G$ors;xdioJnDa3iXU?1_Uk;GWjKsUozE^CswwjUQhl3jcs3#eB>{6&@cT#k{o`?1BomE*Osg+
zrM!CRYU!gv_(~7f(?5`xge}`!nMl#K;{(kZ@6W_Yb2FP`L)m(~;nEr&f=UlJ~
z8x6p!Iib{N?&KZV50FZ2Y8^5otf#6vSMm!ws)nB!o*Hkvy?gixDHbL$bOkhpUYWd$
zAqqDBSHz>I>22o^lX#rZ|7_
zz|OtykbGbR#|
zB9mHit(@Ai!VzmPP6@Omd)oE?Lrca^4sJ>Gk7_jK(Pkex?2r=GG+U%3l>v|$;BIS`p8Y;L^fX4yuYF
ze$Y;BF6geRCNxNJ4dRm)&m_re)kG;d>j9hxbqQaO-35;{OF}qenb|y>>NEF!udsS1
zgBvvtto5JnXjaLQirsbK@HX$p`6#$^p7vM#@p@)ho`51(;Z!Qw*5lHsSdk&3ROZ_6
zr4u>ME@&>WG$@3$}Z>Gmp^B^|h9yi=XY(p!`?@@T#s-JwOzXX(q9P?TWMi=Jd?sGL#&DhW6;n~NY^E2rAi(jIyl2(>rtML#9)y#z`LdphJY#6G+
z$#@pvQNj7}Ff4o=B`7p#1KDuM);ME_YYI{C)O5Q_N?a
zN4wy%QZ|7NKfB!3EjW{&Sn0WE0V(m;1GTn_D=&^1O;{%GopRZ2p-xv7Su}M?x$}=$_f9Ff5_O}J)Z_^L+x6QshU}vB&
z59R;VSGEvs`+RwzAMO+e%04qT+Wvp~JQNT4&*{MR;P>yD*qVdiO>>xT7=DczOc#aU
z8~A+zzuMVM=lf1^O1`+qFR3b|G?QO)R7z={Es~`Aog|sIl{vx?!}9+P{fvA1sqr2>
zHviiUTHtP`N61|Gcbs&_^a%FhE*LvWdZD1dNctJy^{Haaj9nysFVl}@jHl~YNv~o0
z1Wwd%kY3C5FEOU1>whQx1ExnD`Z?0?litMizof7<{aXpWnRHIjpCkPQ=`ukdM*2z8
z<$^wv^cK<;fMvpGvxibfuurBE5}tm7oLarvoXn9$|GARlk(<{Y*a*L0zFa
zK0S#O^*2aIf2A@e47@_p^+Nv)r~Knq`1KK_uMb?uEi(3>0bNUaDe0&WL4TpXO{9N_
Z6?Mjhn9f$8KGLV}A^kj~zXsuv{VyvhYU%(0

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_autoboot_v2.71.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_autoboot_v2.71.bin
new file mode 100755
index 0000000000000000000000000000000000000000..1e4262b22f24c067300c64a6f504e956ca5ed858
GIT binary patch
literal 192528
zcmeEv3sh5A*8jOlZZ1J7!3&}-Rv?O%QH!ExY%2yNM6gw~KE}5gU+uIN+N$-NVG4#z
z#208#w6!g2)z)v?K^aXSV*v&6En1&_g3&V0OnadP(N^I9+xI4loz8sU_h0M3)_;9V
zT_NXv_St8jefHUVpOb{7F{vD5ENNttEr@a4{LSs!x7b@u*Uq@=@bQ=QnnA1+*NJ^Xj4fmfMKZH?){kpxqeW_Ms!Ka}gSE4J?@$9cz!R*aBQIk{A
zwob=5Ey`W*9`iVhWz1NsL9h5{WNgdIC*B-nKG$vAhVS0DUVrYf#n;ka?!NiqPYNsk
z+&^yEf6Pz|GM2trC_p#&|J}#HeGJ^kzBx2Q5Eayl6tp==4yM2`knplKUOhE
zB+pF66Il?yj`#ensx5Q}YVy}UE|Rn;JMUL&+4-rzR90rp;4L@CTkh#!Di?~j(Eqq1
zs}5~mn`>XPPh$$_(WmG6eQlxhsK=_NB8hUXuiBUHV|Q~m&v~g>6Z4XZ#l*h!G_&ip
z>?LCiD}oXsK1g55S+lK04XkHk_c8Fl5CaKMj!#OBA0Pj}aA^03bRPrvF>oIP_c3rE1NSlTe~AH-e+Ag+
zG%))4{$=Gn>BO-%pQmU=36Ym{VQ!k
z<}`P-HsPgoUCj90ZIZ|vK9`L~`|iATN$E_DYYxlC)b!oCFU{7)46==(Qc|ZeG8_Nm
zUYjT#8`~Oe&sv~GJmci;?^EYYI6EO>%HAoFQ`b+`O#6Ox1fVnb)+UI&HC1L^7Tqdy
zo4Ev+vrn{HU?%$y^=x?-&JKqoD+va36QGh%T5sW9Qq@F}*L^OhUYVO=XxwN+f7sIH*3S4Ki|JA8+_t7T!>s(G}Qe2^*MJ_j{p}pDVgQ-`!Bq%O2aj#`PU|kebYctQA
zqY-(&_{IR=fH7`&d$%;BwJ!Yd|
zG5TQzLmk$)ncpa1&4NX0%TWhY${n`eEIP-&MtFeQXS1pN>~yVlFcYoK?c(C*K$(?i
zIBbKNy-?_q87XHOr-VJZ?$Gigngxe#0<*s%JfO8Ea?AQVY;)PV(^{L3yMUFNX8%u*BI{d=}GO2X)LFR@hPbOk1*hc^X(
zg2Y}#-xFAc=gV+8D}5BkS1>!kM;Gf8HOWL97;kuSDlnVe-R-^xh$Ox@wHp5F^KRZ|
zch>tEZ1((meSpoLTkqGyW?xb7C-Rn_d6D0i`HgzM@4SBMcs)H^zT>Syy}vv_{nYA#
z5hfQ{G`IF~)>c!bv}4G7Wdz;U5r(-~i=*YgL=HfC}3v6*rO$zh6aiNtF1rU18D
z=kwJxm1WQ>a5)7VIE9dV}opU3y}Y8>Esqo+~GmCZMITD
z4SjD@)ArhU+q&cSyn1p&V4}07{UhhM?Gz?1<1S*BEhEJuGv}Eq{OA%GA9w0`H`bxW
zvCC=PEyYO(K;2OXX*H*myM%@jyL0S6?PB7T9gIulb>;$o$@HR_t7S)AwYer&+T-A;+uRyVgx!uI_7HqUESZOgM0q?ENBbHP3jx#BUG$2E8@6-CK`47EKTV7I&NH4eE_xF&v9_woVEX
zOat6)t)ZSR7ZoV2BT>~q3k$Nz4DSvHNt47R&+Zv-yR-*iYyGKYdEVHBnT
zLR-hO6y7v8?e$HkH;ok+EM=Qc_qApWX)eS10c8k&oYhq?goB&;fi~`@wX}Tw3u*E{
zrPT{YHO-O4GdIsHqLc6Lx;Tlg6h0~{7%7d4ee)6%FLq_(sJ8alB}bUQfYoFyI5eP0
zYZ92Wa>qB0q~2_eReZ&B+n%#uBQ6w~ePdS+@%GsHhdD>m5GKBI^Y-%bL=CDpgdbjqKevYIN7Q3(;m&?cgmFHR)yQJp8*jGMa+w`U1=(*rS1&286@+`F%
zd-i_6ig~5;N|}9ASFU1lYe?zhQbzq~M-5?aeNB67*XA{L!A~b8*+VWNC7hjK<4CeH
zw_j6xYd7tviLA6aggd6E)DXrk&J4M}Cdn^$;RiJO#?}z(`N};#yY)u2vA7J7bDQ06
z{&c(A>+^229{8F(k+}qYcYh(SsPjn4R$8=+xh91$S9MFfsMj06&0nbxJG6IWK?0xG
z{d&dX=hsT}fWeZd))pKLQ%07cN6($&m)}isO%7o+m!cpTX&yF>s!jFTlRQHC58;=tMTX!{Y96`Q8I8#96rD3b(jSgGxHsqM
z2p5m};1k)r5mC7=zLG^s!xl+|a(tRGgEg
z?uQB-PG-^W5V8!}e4aWA^UILv(UPds8KuOaVnb!)h|FM5z=k&J#fI>LMWSN(0n4^y_3u`wpFUg$CED^vamdQO>k`SArVS?y!wiLt936zlN4ushu!T
zA#d|Mbgd0MN8?MOnk#H~a6h;+a8D9NbRO`ZO8DoG+`&J}elZejs6pjCN5OgQft!hc
zmn(b)`O^<|ly#6}xtxE^P1I@rr?$Hn+XHmQ12nsxH?$E%(?_~CnwkBe-WY6iwOnWq
ztJX#xWvTdU;Ecz$w(g8SjyAI{=WA_!S;*hDwrAM$kSOfBi(T@P>^(1PkXxX@BCznw
z`9q4SoEtS<)fd~F^V2>@S^dQaP`3L;g4;$?5z1o!i;>>>`Xby
zY|3eAiJCr0P1hj3PaYe0ycOwd^v(JHYC3SDO*EkGEQRCD)XiA!{xh>=Rr1yYLtG0$
z!N9|oN*{I&l?R5a)a{c8X??ES_cJUia1w;Qe=rNnfAWsdPlavx59ZLeR!Sp?djDi@
zX>SVwENyNRbO^KvZZ$e6?WQ_*?v-vS@>STEkQA)y(3nq0PpG^lI-@i()&&bDZp<;
zNBn~NB0A;+-`5T(t8Fr^HVSPS8FVr;1nVa+3ZqI2HQ8MHFn8j`dS+L)9}V=hD$?$47O7+%aM;dahyC6X8`8}7+U6u?u8AE|teooz
zK7uAXZ*Sg!oRFk!E5R4_+5Q~#zSoQ%Pf1a^&|ahi)}1MZkYfOC)G>lpvYGUaOw<{>
z2gFG#yl({^Ns;#9><3*5Z_#_4gWKw>0IZpi;nV1c`fg_DCF
zNlhAuHAfSJIb1y4Vf!=S-C$Xp{131QYdwZ1dlqGVjiL=BSiN
zvk)bzl9I!^0l3&O+>tn#f1_4wtJDlil9Eb`zG02|b8)VGvaTG)ho
zt*c#s4rU=`9c%4TWI*58vJ<A9;6r|iHtR+kPgVAl>fk_s_i
zoXG>%>Pw3*DyNgi{MgWojG%hYt9F?VKGChQUE!l=N;kH{4NO$#x5Ig#)kI7v||5)q}ZMXP(7T
zRmtotom}bC3EaB+Qs>90WxrCdb5!@@JZqgll`c)>&i_;@P`c+v{g1ARO)N@UH+<`Y
zxI*ifv_2yzte>En@_q80l(Q)bqxX)Ee3I6vYod;el4cCASg;Idi|b`1ozKYFR=M-w
z_%Ay0#YvydypVhNSoxT*re2zJZvNT*D?eH#*M5B+EAEFP%^I6Mt4VV!*wu6{u*Z$CDE{l_#ySng7BpL;+VibEC!1ozwYb`|3{mNNL>A{?{G0
zCeZIyR+{(Qc%sDEr9Wym=i7fUbD!j0kjCWBk>uL9J}<3*5*&#*@|f4a3$LAeEjuxw
zn7Eo;TULWMFl$%6v(^Wcyi%}VFVbLFXlUPs8SdP>bZAmgZB=|TL_+_zYuj+u6^}0Ix*7eaG|m${X3Xnt#sJtqV<>2dZM@W3BTBS&kuj8^+zl3wmvK)y*!~vO!W^7`jf|cZ9#hJkgy7(+$?2jSXC*_7&((W9hC{NDdcIaRl
zPNU8g%(zb)0R9e$e7F|$`0jtTk77RE4(nXt=Mg{jz7H$J+Y+q<;NwGrm}XGruH(-U
z$MDG{Bm?Nb8k+Y}9-!MxQqI_tkbgL;b2x2vA$LV6t?vVVukzJ1SQQe+N|ZPTn3hj)
z){fR6+AXkV^-ZK>_rI#ov)LbL(gfLX#_w_Uwr}RN)q^$QEE>n*U{DRUAK-1j0`0q+
zqu9EmlJ%J~lOdZqs&yJ|b+BefnY2=S_^MX=+Z_F%Q<8O^jmGwdw@f8qJ;$vpyW2w(
z=cvBQEi1DN{>&Ac$7ZY@bfVEM4(-aQ{(h+f=P;kPSUJs)Y+d5YJsjAazi$3{MMo8#
z_wDOA`Fl0Eu6i508xwUFy}OWEa3VhfjMdJ{-(rE>)8b_FKK~Z&+z1R>FeBf*k@Q`p
zC+T)jBpC9;4jxEyEv;|2>n<}Fv>~bCVe*bQtsg~U(LKg9Q4_mp({UH83!)<>IQ4A<9H76QOE@-d}O;&
zhZzKi?3A5s@7zg898(Nv2y{QunMsMnGfV47b8#nP4Ufm$U+AxO3By?9>)?pT#GKAp
z*@1;Y#XZ0w9$llZ>q$~d?iK0SW^f&6%4^47^VB`l%2|gMy98zw4a|7iZTJ_QP&0#g
zAt=VbNe7DI6^iN9q*Ev+^e)9Xj)Pi2HJ}8xCW+(?qDR+~K1^!kS2;iz-4EFV4Vo+Z
zAluMWG(O&~P|xv7jQboH;f?9gO0eeJ13o%&9KVYECRiO@`@6EEI0FJ^UF3tgo
z9*R2*YbWd>j~%|&4&7L7SsV6|fss-KJ~M_A$3J~BQp$(}mT#>nrxLSns%HSs%41~U
zvR}dr5+^nLRajTB`>7|FDCLZab3tBo4q9#Aokw-wYD$5f6&9=7u|JH#-?x77ohSAt
ztL>5QfUJmEqklB9x0&G@(GKZUy!OD_x8$I@wXwD%pPSax8A
zYiSF+6&mE=SJBz%a{h+uS8xtm=RF5K6?^wogHupL`(HYah{inY?TWHx87Vd9JZ(bc
zxiP24pP-#<63${Ge?4u$%Ds7x6r8k1JO?>9a|nMFoX&fuay9>mG`XS7t+ifH+dP8!
zQk0~bvVMXpIS`LJi+xzZY{Opb?wm-e_lPs-P3>pWv8hL>uap`$`c_9KN=lzAhpsv~
zgnB%%qW^IID0DX7K4~L9C7pF5?g&I`HYm3|++vDX@%hx6i)
zTgnbiC-(_5b!}vqZ6=iO1&fyG_~R*ED@Iuom7
z{t~YmS4r)n&v0s0vGc*Y=$ukGQhU+H
zmSuct8(Qg;Kxy7hUF%p~qDj}t_>{cl#mSE_F(;JSvx+p^`GK5V`{-wOu9tS3lS-(0
zp2DKGN7!~g9=T&LZF7FVN^rfuL_*
z=Pwa13f1)Diyj_%18jI9gF_uJe`PLtK+i1{f
zB@L=QvxPln!tOM?VcK3xk0kOifUm*qn)&Oj!y@1b@X|?~|8VYu?5Y2XbQNPRkmpF`
zcTxXKGg+oy&tp<;aXU}qgo1{Zqn5#<-027H+#!pyrt1jHn2}$
z4y}2*S*Vf2$1i=F&k2uS`Tj~deEkwPJV&%Uos%6qt0&9GF5RPZ-_IQ{U6AB(O_!&o
zLT|Y)FRSH*-#B*Kej^*#cfC`NY5IBFKwkB4WTyF*9HY@Zy?6urG&H2#WW2@d4sb!h
zrgyc&p$CtMB;SLHF4p)v2
z8fz1~3ZBr!T32s4Q7SZ8VsG`~o?dLgSl2If+u(V>Q^*6{c^F?O?>MF)K1F5;;e?M-
zwVd_6vZtFvQRBsV_tyAcpc*t<*dV4jcA!@H943c<{}R<&=f++JEgf&&>{zqPF70Bm
zLmHT#SN1qqPbw6tXEC&QQ`TVCFuTjv9OR!`v*Hk0xTU0jY2$`fs2WzGyHbufguRk_
zTrm<Gz78BS$)o*kJ}Iyzuf7b{8!H0qF6<;Oufj{2lW=r(RkB}
z@1&Vu@Rgf=C#`z5FYTQ>X=uyblB_YkU9Yr7d#bv3>ra^tWQosXKHa3L*DXf-_#ns)
zArX`#cFkc}lhA3-SZja2h`F0t!b+V>k}kYoxW%&ES+%q^G;=MDvY>j4&7N)0DE87U
z*q4wNR_&t~-|p}0>7=_^shPK6#@eIqHTb)@Ol@l&!qzf1cMrl7y(J}t(_qoV430tD
z%G#Sl_S93Vy$oIp=#i{eVIz0vkZ(afq}>5I10%^2Ic)ep<8|VQ*dbZ0q8#(!YVwPc
z-is3Xbgf)d_EpdT8WCC3RC}NO$6Qu8QWUPXcM)JmzD-u^4T>j~8TjxAzvVAQ7lr{J
zBuSr!1^Zq(+(#$8HDCm1RV8QQ#v#%B%9Q$5RDU1pXFuXz
znrG-p4U5YtFZ*$WHRKU@Xdl6wS4*>Pg^W53HNNoCN;#!Ic+W0!zr>fkIuQ!&Fb=k2iDcp>`mvro=Z8ySIc~IpS
zJt78KU7=RaUhU%)v}1`AcCdG?p#Ks4inIZq;J4eu%v8Jfmd|`LBb8AtTq>UxR&a@K9S3W$poL9wg=okU
zV3!hlX<_lJ=~>~}m9v7^!4rsiCJAjKpL3I1B7H1**yypNFZbFZHOZJi#FVp)!t;|>
zm<3A%jeIKT&Mj25gZ9B8j;=9n+rL62-AYaSN4^t|8+;#@yA@MtwQETtP_b0e3;eW2
z2oI`PxhdgDYpq~g9b2um_iX4#I5K|&jX@thJlZN?8?ls=*TP*a8LX!88!;HqpFwA3
zZj{BmSX6HSvh8AKEDGQ7=BO54@*VKyQ2UOk+<5oJWXMYwhlxeGEW%+AYa#1ed+S1i6!Vu8()(xR&4C0p!SC78$A7V&CLEFAAE91{}I>CZl#{nvH^Cca}S_=Ej$f~bD@5<
z#hrAMypC=!&i``0D_7rTB0L!=$7Z2(uikHQzPP{^VcJ#?Y&hd_789--gKYLrSB;=}
z|EmuW*MK!#cmi~0z6uL#zb1@G7awA+0F_T>rbm=G(GI+lnk>NYo5;6>ke?E)$9Hlc
zQgcUapjDT_I0&H`zDHW)>}&4N5vRv14bHrXQW+~k^Tcd
zGCO&Ov1$JOSiK{|T#CZQVVCm*+}(#fb-*{?RE(D+Tb45VL5La1lBL9A5IcWBs>-%;
zN${8|y2+l&m%!s%0!6>BtotEx$<08|wf$}4;;xM3MRh%pZvrIW<@n^em%^H8b4}jG
zOst88SzMFgMRY@N#GY}wuR~lagrA28WmvgythAn#`ZcrKP+wB(hgrl)HqM2Qxa0=B
z+k`B%VL6k3J|Fg22WI`%0g7$#m)iOI7I8Wkxs4EqM4ytM&_v^JnCDD{q>S
zxukSyH4}@HxN-2a$?VE6xV5$s?S_?qFr^V?m*EWg*uQMMXA`L4CxY>VSz(sUC9V)N
z*O>2`bdjCOKAA7A%#pEap#SuBaHj^Z#1!=
zz0p+sPj57Zj|o=ZZ^9prga0MeldR-h>~!e(;7=^UQqB^dGq9jR9RTU#{byAEJ@A0{
z>wzV$ac%ncQ|%jB8~2@NzqUlTn}1vXrm)G6vD-I&|9@(^ee_7Dqax7)u#
z+rHS%_Ak7#U?uNthuF>bBi>k`lJ`l6*vEIMo${%iuMUFBKV;qW&zDYhh!#WfG2!!w_nYFBPWisF2;TFr
z@&}gC4<{2CC=>3<`2Q$Ec%Xj|#Gd@m!CjvJ<{w|d%~DOe|Mxxy?qlHpF$QS;5g)-G
z#}bu)h!{(R`N}_)x2PawjnL|{IMQ$3{g-I*XA}Lfd9lt_+5`(eD-Ex*-{Vz*EPSTp
z#7G}1Pdtj9f&A2<#%miMIJ}|DjSG3{%B2x%o8v9&cf$xU0p-e-5qGctC;xm>
zn_N<{SS}y;pt+Yep>ckNRTL5*gmf9+BMCacf~`8ae5)bb3O~~aw)RG8%S#szyVyCt=hbp-Ni#&x3`G&o)CQ*K|qy2z5=bw)<1u#b^-ovcL9
z*1T{k_b}Pur(RNRMT08MAENX|o{K)bTQX${EPlDjC%-CN(ueUW?#iz6%ZJk8t)J55eeW8~X*tQ&A
z5OabVbVpjd!>#pfT;2A|_HoUO@1IJ;$xeJ-$BENAaW3H@=6YS=_F7$^cj9KkCn@>W
zIfb$%^+6NU!BXCtMJCxh@8azKZtg4GQ%hbXhnLLs{H?Ir>i!JzsT7~#xl-61U*;~v
zNSzZFW!r`%y=&#(aU|iqE!bBd*4bC?*GYosuSMTMfe)I^bLVMk}9BU
zk<-si_R?^aTvNAj6nxXOlg)F9Hg!h1recBm9lyYhRV7NgK5|X=d~c0kA%7luv!^|d
zzct)EwQTlW?^ydG-)>$^ZAsmcZ};ZU@#gnOewsHt0QqU&{Mp|2A4UEwZy5RjZk9KH
zrkYlTw2B$t@Id6x@a9if;pC>{)JM1WQfud9{Ile&_;h~0dxtiG)*c6I8vL96@S4g}
z+=9efV$(_A1z0c3=|TPFnDAHStcc0r9Kj0z2&EeunUjcv@D{nCaj4p}G)S&Vn`qvI
zH3$3K-LuRK@ets9oKmmITW<(Q^-QRDXqZ~B
z8+4Io)Qgr=2QKl}Go!yTzfkWP)a&c5hyJRD;WZf<{k`ag^D*?7BG1k?sg?q=4p2@!
z?ypwa=+tTsX3z@6k8$+LiHu*+7w3E@GxchUM7$GpEB%`M1Zk5I`Gqzj-lMW;k*inm00*+xg7M5G(JTls4|qe}|*`ieA04_+?@s6(~O@4M_kK~HvDJdfS>LMk3r(T@h
zFqnfLjI3$pua?>8u4Iz#r2DS6HZq0uQt?5`z0K6}SIMr_3@=7Gl~GvNtf3WS`2)iG
zW)0l{Rjf&=v;RP4%6~7}JjUiWIdyg>l`H=p;tx09R_gp-xi6Yp{0g-WkDUTlGe#_Or0yrZcqs!laG9;@?9ub(?^2$=qO19`)*yRjxO(Je@wxS$Wabm)?e>;#vp>D%W07Ic@Y
zH%)`3;B#m~BX5yy>D9%rL;o2`acKPNec{E>dQ)n31X^q$O|R+w`f!T3D!0`rMr)Bc
zP}IS@eJ_5UdS3QA_4_>js=aNRhE`hD`*jR@!%d%4N(0@r`+Vzl$4Cm?`
z<2WlQ^QY;R#L=p}{O!?W6jR64tfYnghBUP|;GqzgQOPtQfFVSP6x+(+ldVRQbOeCSdmwS6ihtofz^SHm3$fm^m^h9YM`Q}`2!q~$G#
zX7h>4ClbwqpoB>OsNN8AH*?_W;Qw!lxbF_yOg}S@LUMY>n7tO4w6$&`$*AcWslFAo
zECYNxcvr%c7;X8uIoPKya#r{w
z(7M7is9X6O53SYhxx!4dvm_B(em~4+3+&W>KCP{~mW64`t%f79e6vO_nboB1JG+Eb
zmyi|b)|VufI_ovso%$}+%HAT_8iJL!ZU}x=Z7x0YGxfUY2VJ^f$Ck0yuzQ(`ccp@N
zIeAD({E=8`m&Oc;OpmlojSr%}O}ne70``)g-~RXe%=_Cv_eq?GJU6qG&QxcQ;zn_{
z-XnV#$FAiep?70;ryul5Uor7!OJMdW$og0trNT9M@Cj_gaqJVV#D6`{{BT=*Gm3q`
zF<1Y|M%V)bJ+J%SR!e`9>nksfs>9ur=ps5d^tSox+84I4gBy51Q`UL9TO4R&dO*aD
z%A9<;%sj*^Yh0ySYP9+GMDs=X3H5RIC;te?&fFQ203OwE1KrY2a75Wsac4d*cJf6{
zY)ieyaGGMJ2(7Cpyusf7PW{Y94X@@AJ{24G^jl>lr(yTSPC$|xdMk(s^Yz9l_fn#c
zX>rHcVa3hrt~%b8n^fxx&1HrKLo3k+`L1EdIGOL#U*zmL7j-UuJ!f}b)MpCzRrP*k
z0XCQ8tpc4%zlUwtSFmt+w=}XKYxiQUmAqTz@^vwuhkSl5s$ZDaHiSLN_@p?=qyYzS
z2=As!BWkYPFgvzmobF6Ja5q|On|P-d$8FaDGA-3E4(nJNGD*Yi-W^kDb-00VtmL7P
zN6%xYl&rC$K4}mzGC)}+gD9VJB5_8PVv!z$S&5NjEMd{PzC1{+cr}9`gjMyZFO5$^
zc}g9O^8J0OqTZrMACPhRq2Lm#A4cxdE53a2Bg*@=T)rpTm!`Bd6seD){l4xNE`eqd
zQfxl0OV~H3(;WA(ZC_hIl_>jPjVc!svO229UcR@e2#9mg7R&scX$m_N)C+EUic
zo?z%BjLS81_%ulrs%{Z9z}6KJLNs1nVWymVc%Vimk`6-MQDwIGRpMTD)~s=b@?3?3
zRuyQlTgw$WJmz=4RiXAG{U>Jb0bg2t&~Aw=Szg|{gs5g+XF$MS{158cRJ7{~#nvyQ
zS%OV+2DNR9+?Bdpl04=pz^%{qo>}-;{fe$-mwF$XCO
z{)M-+);i{}H8NT$U0~xTuN6M+-g?iWWcv-Z))|CHAl%E_+N;f4>tJtdWljI8HIihA
z2gAEjYnSSEqF~h8SJyKY$JRa2D81stvHNg&qGMNXMEp|9y_FxoATv~v!@@D=C31Q8
zVqZyfHA?nzMpP`Jl8`t0wV+JZ`*L~wOTIGXJ5K)XDVL~!%|W{N4qcBxFV55ho*KP9
zr(W;#6T{mA7`q#-y}~B27={(Pm*?ej?xo04U2Kj}Smsw?H7*7hU+FiCdNm{dNv^o0
zCD7FAuQPE@E~WKq3Tv4um)AW@o_*AZr=b2vYSrZzuMzz?&F}qw?Ki>Ch;z2IU*v-!
z57a%EVDr-MRFkewGv3zE*ga`GLUZtPkxero$HdoZUbKmZGaC0`?A(ZHCY$tinl6*K
z<1cU9^eNsfn&AMq#Yz7|;<$BlJl*l;jrEL%AO&n6K--sg?^u1jKjnxzKdGbzBbar-
zi%#XA30^;5hb;s-Sv1csAGHmS-0my}ezQ%PXd4mWevNFTvMn
zBPGH;y~VUUr}s(oFl_?xi#ME1j3@8f@`~x{N?eo_d`ugZw9V>m>2uJ>q(OKCX49bq
zZk)-MdDG8fJQMbm;TbH>27T+Wa=tbWp}&M|H=XYqGWs6%)~N)}E&aV%
z;E$ut5d+Hx?S=o&C1u!mm2jI5r_^uXkSfYT*BgYx~sps;bc5
z;|`wV+!H`;QYH4hipNA<5a%+~aWvl|e-!*OdzgbK8m$~kG`jWIo(*|z=6RIM8xc3B
z9Z=ijkD~riZ}=F-=M77MD1L}LG%^+vmND)KVQ>S^p|%Os7vU5#4pxBaL2$V8t%E%N
zz5d=2!`TA~!^;lD2T7!fXeg`o@rw8$MK{s#*4MriEqI1Yz?#stD4ce2Mr4(~I_gkL
z#i_5(esSTm&%jmGH35E-SFiEX0r59lKMyGDD7(JvN0#Ws*Ao4cZ%mm#^}^JoX?Sk~
ze1`NU#$gGOyRw_16EU36LyzlLJ)eYcv#ZeJ5T7;*>b?Ig;8-m=S2p{Gn$K7<3dTeTl?@Ub-s#s}8eDZ-J#6e+@qu
zZ>18Ir9|XdCA$J~=2zN7!>Uw*UsN6K>Uo
z3~s**M;$CJ1V_y9s*k;Wb;kJoPL`7H4rgjpttxZbqc0x%f9L;|H`#Jzk=0885i#X
zd|by|HC_5zE?M_#$8>@L=gc`B(`e67cGGg&Pw8Bs?CaPslzn|A@yu|oJ-c4>y+xJf
z>GVOGALxj)(gHiCs^<|oi^J=H-m)r$C*+dGCH@#$T^#;q&7SPbSJz~**0(0LSb;7f
zUGO~E(iR_N;IXFJ@-*D?+PoJn`lLS6qd4$tl&CM)i7ht*>V&m;#A_&6$SOHE#SDJntqv0$V)fw*YVqrutj)$|xcy!d^oD`Zs(dQODkJ
zhadIG$UU{~#Li>Kj+{Dtw(`Qk&&p?hrE;Vg9)BnV)zeF)4X}
za#YI36#eM$!HIf<6N#X@etrfXH`~_`t<`BrQZs3{5pk(W(Jz;bn?|j8mNnfB>$a`PQSEFq`QwJO-#E@>
zh~PXw-TKkwH;{X(>~6n-xm07vr~h@oi^{3rY^C3t#cIFDbJTv%JgxMb+0^jg?6>x<
zHl;?6@E!H+#)$imzMPzw!gm<)IE)zgK1xo1piSmDRfmq-kTEss(YeQ9sq2(0mkfMT
zX(zquZ};|`h7oh@?ugAoNn+Tn1FI?yao*RM=-m!?Zb{+kp)wmz
z=gl=6N)q8kpWz0NftINxun<1lT3&Zx)#lTln>lT;+>OPHk%^QycD*mJ^#?cfF+sKu
zKEFx2!K{h-H$PWbuhWZ)qc)GhV_MoZ~+#+A@-)_~lOZ
z>|^~8tj{M%Vs%K)E8g=E()K*=qt(0RG9JSXvyDF9BV_~LVb{w#f|RmkTWi
zKF#wwlo&TuDRJKB?Fp8tlAs||I+PeVn9fgbvNYj?Q`YaX`@~?yWy&QPgZ8=a_O@=I
z($)@Js@hvs7T}3_w?m1HN7ZpH_4X$H0q_jKTOrgkPa_}KUpe3H!1+$$R#vnT)USJo
z5(9tbg9S4F0PJMH1HSs6-#0IWc=H~cy>6FY)ipY2`0fFSa4^GKJV%z)
zimWJwdW8TnM+m@Oi|(aDAxlv#>ELexVt0wd9k?lZ@x;AB=iuISzXSIB$hXvUlKOY6-Xe2<~?CGB`~K6K59Ww>2*o7FHEX9kPD07WW9>un`}&|KMaj65W-c5>PGa2n;w`=>o)MO@SsyJ=^Z+!vQ~Ot`O)1
zvMC2=<$oyijB~s+w_^1g*$o38rmDE1*}N3(ipc^*8Fy
zpaC{$2U6=LEvbWt`~NLu3BTzGS=p7lkbysh|1)&F7rJ$tyU;aGCFt6}_^+Ug&e<((
z$GObALa=K^{DF3?pywQkI_ACQb7i~cZS1@_+2l3(L6?AA*xA^v7U8xVv)p{TPO)U%
z{PgD2>I-}~KP628DBvfB0{*%Sb!MGb#w584d2T=lD!|!av4P&D0(I6^8sMzW`4tKk
zsN*0Ei$o1Nl^W)isSs?PpKS%_BM9bmN(gt}JZ^B{oUi5dfhiq#Z;|Lnr_#@kpV5yp
zMy^TYBCUm?N#_z`^md`i|6VK-u4qm`^WT{MC`^}2>Ynvcn&YsO;qJw%Z@L0Mmwr|c
zYf4#9LL#)$LKny6x0!ZIB|GY|8x38(E29bCIrFtB;UdYZXA54i#rv{v3f&yIHE%Yf
zSE2ev*TzuhMi{i6KD20mk#-6!s^|x<*#@UFuq*I?#ueR7{p@|5Qz_NH(mkTVdsLN%o|Bp;GJ7
zTB363xn3@bpFnsqX`0wk?`hO}1MrN`PKbDe})OWP{6zmzsof7phPpD1szTK%bCGAOBVmBZQf0}pd7D_Hq61T2V;zVH~pQ9
z{nHpT&x^~cyYr4zXC10MWO^I>hOt1A1jaazkiq~Y_`kp?!Ntvz`lFB$uSW>6b&2BtTStD
z_HX*|VrX9$?B@#I&4w1mUhl&>dJFCL?*2x?k)mf;bnAzov2PZP9d~JPk!L|aUDQ3W
zPoA8<^;zN|ZmeXo^uXKcdBqL{YYA3)7cn=u)t3j!Ef#lE0>PVNfCYFYl>hD*EG8ut
z5BO@}+%9?TKqYAbzSMgxCM9*9wEDr!mv_eoRFdZJOH*1=Z9pZQp@UsyHQ9{swE_9w
z1n~Ne+=GpzXFRKf?^JBSu5f^C0Frf4L%WAU*$B<@&>IEn+XTu=!b`i+Ij*I27QNWT
zrN^l;`(ig2Y00~`bk$mWL)wA`pf(T|0Mh!`Av_iqfC&gg+g6(o3&32~8SlBsKWMEv
zNDab$`9~2hL>Q;W+C|@Mt$#+CZrT5-QERPaPoi`nLRXPG4yj`swALns(-6*=VRhhK
zd9n0ah*)z;BCLS-(265V?ad=}njnj^V
zbz@Wnw_e{xSTB@*^9|R9k6mz)ThEu)S94wTvGeuZHht{8c`Q;Wy%xf46SSj(@uJ$%
zwNK@fpNuK&3^VnpBPmC)2iycEYW4P@n|j5Q#F+l8&F^Rx?E_>WuEpQ1>_>d7Ts-c#
zr0s}-SI>x(l$wVa--h=us%t$wD%){EKK3tjRS&`u0}W(H<=rs^4>fu7ll
zv-zDKgcfE00Y$gV#RKP|B~dn}ow+SC{!UMY~{7_VQW3V{6IbOWb6z`hU
z6kj@O7mHp|y5g^v*fASf?4ev1?IeClt$}AujeX#hC06^X1w4|@9^jIu;yzsEp{#1t
zPJuJM(}#oApELb&0W-ZH%E`rNhzAQ*cvA>k#D<7Of>DKe*UY;kQ)i>$;ktb!T}R>d
z)5uDa`_14(Ztx+OpljuAc<90{d3x=?f|GQTw4aiGVm$CU1m`Gl
z@H;0d^D$r-zs!+mbLAypp;MH|`v;gDw{Vi`3ywZ6zz4ZMu=}SX?O}L5R|jJ)rRzog
zg`4!M5q_h=Us|B8?#1YrG{A4PuHcQ#u|t|+=ixV^w`lSDsIFr5m#Zr(e0+>(N!ell
z2>KZ8IFFY^ar%OEN9V7GvERw**`4W>lfU-v?iZP&?(}G9wd<`t8l=w-tu;RC
zYmN7|w&?m(Wz_qbMql}4cOGmFLe?I)51!1jMd@k$jEv}Ve<>H9MdjUn(iZK{v`<49
zc~wr2(87O^?YEGRI7up+!|$FX4|fwh*NOK+k~6euNRo2tueHCw(X~N)uW90qu!WwqJk4@3*jHUrWMpM6Rqv?@|AXC)9AXBgSAXDVHAguKUF3=vp
z8>vPR%2$1i*M1r*0$}q91ZjI^2RVQbZC@_P(YL~=jm|bYqT`Jrm`iZMf}a1V
zBdd+EhN~z8wBg~M>fGR5c%`1rfdy151f+qhcCQqra|p?~(JNJ$FMx|weS-bM&(qoe
z<^i3n`-99sZ|7#TQJbG*V(+p%9dGb#-rOc`@aM+ou9V`l(dKX8bE{CE(Mj%1SU{I$
zOgi@dO0vYH)aaGh^634asYjyoU~z4Tc*yR@2a7pV+g(d>lL5b?LURUui|Nq!V5~gu
zC=}rq|C@r>62*tOrZj>7R{UYxX4mEJ7BkA9B3Qf1#o3wQIu|Dgoq167$9rHce`^h24zd+3xzM;4Ey4aq83#WR1HGJkN^Z!Wu#m;$
z{AnUT*M@*D-a{PKeY9$Md7u32=V<9UtF;ZG?qW2x_f(rZkr
z4JkX3OEly6o!otaX@f-%ZzcZN>_-@|`kP0{gREi1x1{CAd-SdJ4ivp4Bk7?3PRm?v
z-+(hjaoy9nwF3{|x>;wGcd_ZW4t#zM;gDV(;A21zNGMP5P~%-N7`UUu{>y6A;ndQ;Lo_OCr^*R>kNa6W%80GIf$t}N
zmgDV#-ivSsDm|3PD6kz+d^4y;sQ~L~*c-kzvl8w9`rcLm)hYaPi5HXPJtEm~gW-V|
zPypvALSIbUYjKK!qj%>-NeFO}{hKBH}pJ0diL`+PuniVx;zdm5SS}O
ze*=9U3({Jw-PlvqAVqrJAZY(ElUv9uPa|F4N#Ib5|4jj9ZQgiXsWr4Xm4S7sh*+1)f9v
zR=jWqkE3flvFj_kD$!egyTJM`eoCGIim%ymn~m
zHPB0V#of~38S|*L(&F1{Y3^a`$Mo`+XsE!ep;4dFZ?ug+r!%JH$Tfe;G8yr%pAIjX
zcgFhb;|VQnOL4+`A8r{ID-A)DJO+&wb3Yhb|!
zYOj;fA+!!b1QUZTJZ0fhzD`s=eoAfnhEgo)hJ$fg+f1i*UyzVWtO7~
zzZ;;ekE&7bm6)|vm^I{)ZJ&P@oXp@_`Rpv$s#UW@L-H*5aOA?`C_O25t_^_}-y-_2
z{CL?rSOIwR7ZAfz6QA>?$5CxiUi7Xy?y#jPA$yJx>=F|72L*z?!eO6#y9@O5vuh?(
zJ^L0R7&-)a5V-Uiu-VG92aXubAb0UbJ;lbwP4I(k#)m7h47^sJ!PXpd2-(a&t4Z&G
z#R4}gO1{q5>fggwljLf;k4KC-E^1767XC+WM6*{w|vID|%KA4A_9XSX#O9YPRiw={KeSnHG#
zlsUBex;rBXdT}^@&rdl!NVX^Cf}o7X13pNKv~ofEbdz=+_xwJGb(~WBbh}nR?oRE2
zFK}+EElRf0a>2OgttgkKlpEWs)u-Jlx97KY2OQQ6CFf5+Y4sU*a)O@CL{7Gn6ZoT6
zpM57MW8p-!wob`ebW^KecPHn}{AZA}RmnMhL#y9avp8g>i68qS!dsj
zoC+l;{|BwU;!aLu+7RTNQF7!)t^UlNoN==QpmWB1d|o;xx;ACqV*JPCGw$Loei2sq
zRTzU3$TJ;p{`4arOkwaKc)JM$HXWiELNS+op+TFfy=j9l`9ecC9rvdF`jRj7*rwCo
zv?nh4LUEfu^`==aeX8Cy>zOOwnGXwDb4Q^^2$b?lZYk_xNKPDHPvAM5lOmuSM8GMQ0MI_gzS+%xo
zE%ZcM>{L#mNO3qrBxufGQK*x5+yBq
z!Mkz4YFeD43C5{&dR&e7Y&kXVu$t?f5qHX~XYCPpP7T=}hF2Ws$K{-?iMyce9++3+
zLuTSh_?Xw=1K#Aux64^Q(|uf2ok^;b9zctry8qmLfI3v;#W
zC!1+b^iF^6VSz25Op@@Hk;{v=*$g%lEK^knuGl>5p|4fAjPoRJ(?*>S-)lSa^ysP`(X
zS>fnQqb0wD4f{7dw$ZdLlsi(r`gqN8I*HJ`YmUjiIUX-`y|GGbZRYGtS~QS7v4SG?
z$!n*l;)Nz-_TQ;R?Jfb5fjyu_Ly|pNU#BMq*!DOMtnw^uxlN}VyaHe*$h141i*W+M
z3j}G;%QYDf0y{}F%C!8;ocA_sL(dzuQkDC*so*d%B};skkqINQayUSb-&{M7+g&Az
zPk1>2tpU?(yKtXVg}lR^0P@H$$oM~;eF2!XUouIWYt%`OTwNa^U
zXTX+4tjPa+-b)PH<=5Zu;|KHJ-Ost_-Fxo2XVFR}w%ZeFe6sva;wR56pDEWM`5SJ~
z5Q6}kDVHhFa@sW0{QDf(`#Wq_7B>&De~huNZO|c)@~0#~3uY$1l|)MuKJuneoJpe@
zuF=F;8s{+<_#5SBAnj?SJ*{K7$w+tM*EEmWJxNr~QD;sn#{VMEtBdg`syZ~qsw)~%
zIHM^R8Z@GMsk&HwMJ;NAHN_fUBl;aw7yEUn#eNOy;(lk;Vt=IfNBRJy4?y}rqz^>8
zKib2eS*>9tZ4TZB`|<;?V;yP}Lm=lIqhy$qSw`>%`my5OlD@U8Xl01{h~xznnPJv3
zK=(Y!nG}uX*1%RBaxGDI$dbj>7D=dg3J{4d%Bbus?TI9y4%?ZoXjVK$>Nk!y$o
zRv!gc;~7hn3Rn&ScIW;mb_uh^8=KX|o14{SC58G)#fXf`HLDnLqf0GrcB!=?CWP1J
zg}C%tg1DhfUA)1m7PIi1h2M-W4Yc$$qP_W~in(Q_zT;@ViOSIOb$9
zGc97aON|(sYH`a|oX-Tme;k{dQ3?v5xy-Z51S2|TJmLgr#Fz0xL7f<)WM&^@P7=j(
z(ZV3Y{<%8fzh7TDgGa_d)FolSl?c6(nLUSTP6%(P`5dIqivn@RdoO=NBl>$jt_pE7
zpzYF{T2<-3&+kiPRdH6!b6JN|=FyCZMJ=Ge<0Al|Zjf&0GUk|$#Fw&>M`g}veyc0RO;8S_Viibe`4#G-=9yVD$R6=13PC_@}R(eOA
zP1sQbZ;4X-0@|mRS37a<^{sbhESRim1%>Ys7~qBxOYyf4f8_$ayW+Ofvwr4G<`I|n
zDwCf2V?O_O}J&P`^GtgFcsYrLYkH+B8AA4_fWq>^r+*JCT)zUxLo&TEDK
zd=mL0Y26ZMEL4(4pw^a&^=^@YS6U!#qx{w_X_MW-Iky)ho)E==su%E5<*G+ni{(W+H9|5~(gqw_WHW%mE)s(r-EFssTI$(y(5u80-wt
za{+Z3gQfgDA&GRGu+GO*Ik^OKLqWSnDgk<4nCbHF88ixM43m#d#)+qsddB)6^7FJQ
z?>Bv+u+H>CVf!x`ibb&8v(EHFvF>ZHoQ=kykE2nbFE;B$xWNhC6t1~`;SQ6fc{#h)
zVper2p3qA>-3K}vakOb6Y%e3b7Rqa;kaevJ@|;Z;)J1+?`@(BZY8@-+B3eON
zSFmwqK=r)1K%J4Bq-x}G>gH2v9mV{Ns?Z1HjD`F;5*%lso3muma?FV8^4kub?
zDll4Hl!BvfX0>mA+Q{_Yz`Zk59~Kh@avEqmnY9BS?9
z!btFOZyqutAtu|Jc2l(7#SG4P+eLIfuNC?+H3$
z9{wYgRUl4-UH5k6u?essl;==&oMx~!^}+A<*kIcoP(6}HB+G`qT0UcJ{q+^r*3^}s
z2k4{n0;*+7By7js(F9V*QHdF!-dm!7ji?~OA^w#33&vka0~2)QnIptI-J9p-r&NvM
z2{BfRux^PrfQPX%3#XXVuPUUJdG!o8r-b3=Es?Z{Cgcvzf`5lJ8V}`Dp2d?l&|ovux>w7MFn$9m83QW-O++GoMYN5kW!(
zoXTrqT-p^oy+OPD?RqNANTUv<>J%K6!pYu~em8c6R!`Pk9NH2wkh0`cF!
zZzDN=FXCEIT`&DU4K7J_e1GOch>CaN8!rTWQ>5MeN~V(9=FUqHKmrx3>BdOoQfaL3
z=bBdy=OQznhE>CZ)ju2~^)Xe-o$>xAeXMGDT&xZEsi`XupQ@T_Ukb^#yfb()$<1zH
z2%8l$J}+xFnb#9WiOvcBCyyNkPKOKJdCbiJ0jE|*gmhiPsr8rOw1jY)OE}&0lQ>m%
z%Q#)TR_Ht#eUiTYUZfll7qi0oGJY)cmar3eegNi)qr#)r9-V&~PN%tmvbJru%*nIXW
zZNGl2(xzoW8kO+aZg_`>ea(paUT%c77v3e%R>y6(<>B518UM<_87{U`Fvi6`(!o^P
z=3qYd>fJ_L&)`e$FY<5ESl$-a&iQ$-U|jTvj3xTWV~&icm}QW^b}^LVIAdqDX9ady
zelg>eQZ8AL%etiJ_jVMg-NKia#W-$t`d141aqgo%?b;pvS?$99ta5LS0FGLTS+>@6QOc!OClK!-M&Ld7s*$0oA
zlfO|&qs<6s-rFIj`o^@|;=cUNZOsb8soZ-CEJ`4a2^&>&Z|~GI&aA&;P44U^J(ViL
z=NYEbJ|`|S+uhi5tI+Ls=SkSC{@toM(+{^sv<1!ioLZ}1g*&5z>{H_r`Qg>Za?lAy
z{)_xqCin;507(Rw|fB+f`*z;{lN9V&#Wqu1Y
zVdtgWma?gj{U}W-Gd(mlb6}4E$fx7>dk_JdjWd@oFz$?acwD^`N=3cea+
zTxOQLvE$ax>+au0e@C_TudTY?8d3Dxv(g-={)RPbsz5c+gvf0r{fNk8mU#`}4qj$7
z@q>-hKFK7GqdR8QN~GUQ6r275B9T9If39#iIA!HwiEtF!B%uMQjdFq6ozrk5E%><}`?-r5$h
zDBVb0-=GBWeCc}(4;f&==SL}|p}<>OQ&(x|P11SBuDw-FZzN|oVn;Y2cy}uq9{7gA
ztv>P9bjpI4vtP;f)YS@{=})E&aY)wH)d~^X`jG9PTokU=kiE5>0&e|SD90-0
zta`<10_SNr{eJKfnKMb5L%e{TYF`^^OV7Uo-{Y(vy8BxkS51r<)x3p;tIWRt;42*w
zQouiY%aMQeyHemiU3zz-1lIa3l6NJ4IdX?~_3F0Gh}t2RmTlq6gsm#o>h1G4>jVb=
zf!1yo_qnL$Xht6}nW)Rj>w9~GE%0^n%H~gmQ`z0y<;ZCi6@jAm4qip4%Ab}sN8XOQ
z1$bu>pKn$RQT1kNOeMlrOPOh_CRKYrn%TW^$a?MC!Hn4<45xS{LWy8EvzkHX&Cr3t
zJGalY!BQq{*!s$(vyj?KDXvVMOfnrgkH8W5gkzpkNE0$08fa4Zo$j4bU9-F=bizmc
z%MN=_@1)v?vdTAAJ3BiQm(4yqJAVG5`B4k<7N~yPIc?cfXP=6nerWpd{_w>gH24m?Klfl_
zJutEU9!wxjSWlRkbQIEU8Dn;ovupdG?zO!_xzpNJs@y^d*eIbk+ixv
z^#K-`PVHgle`Zd3+~2);1Nesl4E#gF$I{xYyRd2QU>^7MHf-7A_-}#BVc}A5^wvrMVmSeB|7Ux#%yrPk+hx^ruCC49#EKL29wqq)C%o&HRa0YvvOa
zuQ&S@?S|yT%KT={eOQ+$Le}7u=C4fL$6YPz-*mu&ta_0_S_?|;8*tA6ZIWT|%QS3u
zUr8(B=;JkA>Y6I28hb~ndMoV$n46-MP}&97Ztlb`pi?nlri5^&5s0w;AJylGZ=}4@
z6KXLYWO_EUf1E0C@q3v$*$&~$-jwX=*#ovaLZX=S*jvv1U@xEs``Adl(m7x=~Q4+Gbb-$9DmqQM_$TFrF7
z#>Lwhd=bL0q$m@X_*}I0DD&a=^Vt;jMVpUNpj}okmUm+B%Wzmi8<@D)Rw4cdJQr?T
zxh1<+BegmVrBkqyK#!|Th;S^!K3vos0pEoYVo^(kcQ4jOw=F|zkGUDHes3Jr_e?5Zsad-)wT(kYztSNO~
zsRG$7>6G{$4LGgZ4sQ>y4>w%e{_N&}`i{|I1_w083NOO);5O9_m!yPV3w$S1&Y1vZ
zFZnpE<(q$;7FOA*VvqA@veI7b$eNBkml~3K
zO?Nii0E)p}P;IPBYR`Cp8I#{%$hyB3Qba#`gLLuMvzuX8(uMkwEs-;Y0Rszlr*I)lgN?qxc%u@Xjf^`|lvb5RVI<1G@8Ec2no%H7PHxLfT|
z1lOj7IR4P-@303mW32DzkPaJZ(@|tYtV198VhzgtCSo?jlH;1wF>el{5Mh1F$OzjY
z9LncSIg?{U%b3gtiiAZyYfW9ftG&-C?Ffk`n%6&?4~&G_r1(H
zd%=vm=a0(FMjBD!=bLArm_37Nk?e36ozcDa
ze@mSOeghr(AxvyWGvlYya>C5}^32=SN^Yc)g`|DXn0zrpV8e{KMP2!&Dy%j!;ZXi;
zqfMYb$@hUUlUGg1H?Kac?hXm6o1GArpese>VO9K0o2nw;{Owic+EDq62s4^r`%<+w
zG_3XqEySaR*Ul=bg|GxC>f^R>CLez&-@W+iEx9(;o9V>5(4BV=CUjW&QbJZ`*8&rt
z9}cQJSQS+FN>y0xiYf_{QKn~j{tk^tc0J?4aG!LVt&VK0K*)1S^J1DUdmX^NmhFnd
z_91i=Gp;BG;FjwOzE}P~TAaYbYP8^l!fK=_(wMiv|494I;t$~1llBPEofrw-{|
z+tt#GT3yZfzq_hiN~7;?M?!3_6OjAYXerrsoS<|6zP0l_|k-cRrmEn-+Jk0D-o!UG}n3Mel
zQQ#UzZyu!aTlj&+H5*nP1}1IF9-&Y!gKd;ZV-B;~VN37d8=
ze|A&E1-C+Tt2MdRxmtop?qve{h|Bs?>Vy0&yBW>R>vyb@r&fESP$xh5k3eHYSXqO*6fxU``iH~w~2#hjhCvPnCGpxqWL^-ALKop;-phg{(r?^McLpXoB$&GSwKz`r78a1uSD|ZKfL*rUFO+DjE7v;q8
zqtfVBjwC?H-^E{+@+YfJ4NkoOMe`-Szdmo|Z)>W6zmg+Jol(+(|67aCSD}Z?WrL_+
z;uQ&gO(VQ?`T_nud*zmTJ=-B~;1fYkgFq#X5ZF;mZo>}jT$1@Ai2&N`acGom60
zo?+p~OdZ5%xh2f+AQ2vBl)lkt7xv#~N^)rmL23+Hg$wLJ`P#P2Z03J+Y0
z(}3-=1Y2M0c>3;1X1Cu;a|8>d>vM{@ofk(eV5_vT=>AR(fWu(*-JNMI=l>0zOjeY#O~
zydsl4$KVU=#i=@D+(q3V7=4tj&}e`(blnX{=u)O~c{k3=!VMb92B9H)VZAv|T1S$G
zeoyO&m!7?AB4E>CW<2dE(N6Do_qOv1+6k|BZ`RywP3rv?e%?K$hd(D;4n)LkFncoclM#_Kw
zu!UxeX2LV4NmXqrC(*B8JN!(rMz{9zZ7SLR+jFLxblyVTrsEL!q>Zfc+F7}tc6Aq`
zfn)FWl&e+Mr2EQU!Z#mP3)t%=?Ks>iV*cEJzxbpC`+q;LZSGUN5~viUUAosCtI?b)c!5N;1UAu>mpTovrv
zwj8?68dKoEbLi#yp8*m@yCT!%4r#xs!}wnR?K38+H$-cc`%CzAt+ao5a#()jVGDBF
zLzxj5W;#Wt85o!yH4E9v=v`6+1~-{V>1qwcKnE3bmrMI3V1ETUnr1fQ&3
zVUd-Z{TXbXQ)jqiHngUmaF=J2z6x}NQ-^NUD(h#_Im-4mN$w$;+63#){;c668{O$<
ze*&p{YSsF?@11E?E+zfAwyOH^S2(I|a$j$`Rca%><8^hslm_U#T5guwG)S9RJN*>3
zFWHW7gmtlsHvoR5kZn1SluOukS2-y~vTZ?14aXb)erE@fEqCYEE~wtWfuLAuk&&h+2ER5M}uwN(x*jS<9tne@L_X*7xk49i}3I?$H&~2qx)9wr!pBkxL$!
z+FEYGCmfCc(2yhiG~PHj<0BjHS`Nc&GDeEXMts9ISR|~KTYt+%t)J+ixXh%>v8syN
z0UmC(bV`2j+o}#caz-;vV_aIrP9xi~zB2`Aph?i0+S)`gtvnKwNizgHAz1qmt{?0H
zUy?NR5UnSk{;EkYi1ebOY#%|>Vr8oTe|#ji>!kUw^Uc5i*IsOC
zOy(tBYTktC9E!s&1Rd^hwzej%dP$~))_)Ks_ePIvOff@uvDY$<8pHG|qRzda
zUXy-p&=|OvwomLQ*s>22Z2pIQu+8|~3tJ!BPFnSxm$py*jYiV?$xqSt^Y8qSwue^!
zkhU)zxQn)vW!{dt#Ra&xhDsAy@VK()eiVq-i8Ilxcft*(3kHm$onL9p6B-ZD~}(
zrhN%c3-!$0jF%Zvbqe0^FEJu4Q$TBt*m^#sp+7D)5i=$+4*P7lqud1?N_u5ssy
z=8aCG`4v^r#XET~T4Q3xsnR7Q52nT1S_31*MIfxIrn^FUxB#4PpFYJi1j>i`VsNUWkZvhTqb;4)|
z>Q#fM#M&G6v4V@^czDqm2p>&Y`zwVr=vm~>17B}4PupTm0#|8wagMNPMym~F9(QQ{
zqB$)ma+Q9KT&(IWH}{RXj!Kun#jgL7St>l9=U6|I)2c^uXA9;Q#KxcH9NVH9$F5LD
zy9@X6mT#H&cg6bm>K&QUoFn@|?uy_@kK`N{k<x%5Ju@u8tG=`AlWw
zS+1C0%TyjY!imcBOzhJr$Bk!;RY%y?o25g5)F&{49--(;Xw3o=M
z+FS4ba1B}M{NWn%;Gw(MkiejO*O2Rj?p;Gp1^&$bn7r~%cxmW|`{P@C
z@7^C*whi6vTk-qsXvynN(2PwyOEXplF2KXlB=_Fg|9@&ni~F;*QY2qEhPg}bz4_BS
z+KCy>W|9ZZrTm(&mSXAbdGAWGHupV;P7
zfA32DUA?zInU{k1lGB&qW$VmcJ2u8wNzhciM|3&ypAwIgT=j*A$GO=1AL4ONl-=QR
zlGjyGFS{=KzAvvXiK>wzAg&rkXLQo}E#6#~M6nR>XsII2;%Z)0SV!l&m2D@EQz=T>
zT6gKqm2KId#KFUk6h*OZ*KN5basJ*^Z|OqUnNhx6@_*uc^Oo6KcM2`8{L)(&`ni2t
z^p^6Dq!k`*y(7^SuWWm(_s8pbQ@y1NT?2mY>l=M+^u2k@Y^~G$b!FSc4c@vxKayQ<
z`ReW73tIx%Nd7XM930{68|Q!q-
zmLiRf#oJ@r<+u$fYI%$+GmV`?QM*u*WY(~s7#H_@E%%*2POxo=<&$S)D!Z05xEJm1
z2|I(^M4lxHr4Es7Q^Ih&m}|qk0EwkIvU98@I)0p7kLsMsrjqCJzmy+C`599F=UJ5<
zOPMqHKbW1KO*aw=h|F;nV_@%CHH?AgEUiWBvM#}!PS=WZt7GtR#(d4LBJVm~-;q`m
zeZ|mB8E5|9u5$2WRrrQ4W>?|Frnl_12TZk9p3YS`aI0N;<{gFC+M)8yBOGaf_XLwI
z2)L%Uy>u42=>Ok+>Yd3|ylJS!|JR&pQtpHAd2?+_w2K^Qf0I5qYOZ|OnIe~7lDu0m
zTO?I4yhu`V+U+l`cGx=nx%lDCE7DzuwyW#5=BQTa>l(R9aeoh9UxTx@0Z@={(bmM?3sag3
zFUxJndi}DT84_c}Z(IqF#&LlpdmssBOy)l>dD{)sQ_JRGbtw!}_B^zOCmaSE`ZhAN742%|Vh27YlW2+1!_zs$rMPIIwO|5*`|Q=DpLVkdvh
zh5SWKt7j{l&T%1*;pRj3;7@tQ)_Nw^
zb%DE?C&I&1rK_3yQ+~1SGIKM(IHUcZ*_?RP?ZVQ(Yov9T{LzIo-I84T!B`e<=og}H!evBW!nSXtkJZ>YiX@L4g>J64(E
zL67gxIqyyDLyuj|P~s@H%G0w{jkq^`7PsXrt#IZSo0+Ww-B?g9xs`DyidgrNP@Yeo
zZ6?s2&AU{VRw22pZ0Qvg=QJhGcG#nrn5~_l3i*4L@3SnkLD{fZHh1SE$2%fgleke0
z%mE|5*AjQoo3|ag4>P5?h=a^-;K}1!>g3kM=ZjJ
zwwTN(k&f@7ZQ^$}Q;glL=vHWqW_8zHwBdz7wj*MV?m^MLY6GkhMtF0`0)gNoy_>bG
zo<0t(b=!ib=ip6MmWj+dHuvb5jTIZ=(=6C**Qm_4ekx1z3MOU)Ye+LVHjHP}zJ78a
zrNC}eVZPa}h|Sy}`2brr$fk4$8GC1Cd_vY$MVB62(c=KdFn-1H+~?p&Yh^BL3@p<8
zKvGg6$x4Eaq~%MIB%xiTO41y#)WYT~?E`w3pUvNOA_ghh#KuQBTO^CmE#oYc1Tm+X
ziL+20_5;eJv^a~o^QuZNoe?4CHZznj=TNB(Z>gTE3b|Bc1X;}aN@-4T(T(0xEmxu8
z(HLkEm0Ys_Zp`qD&F(F7S9;3RBo%Z&+9IeRL`)5{0Ct#E86`SbVgF)
zdu5B()Y4N>=LAIWek2wM3|Z&VZa{m%F6;xe^F_>obmaS1CSZOmle%_D4CMyzA&;F}
z7>pNOAPLjT0OsMiK*C65Jy#->KubmuRhzO&)ktZU64&+t7eP@>^2-+262(>*teiO5
z9BydubH78oo^)bYoqP~C>^YFJ=D-`>edKQ*-Q
zx8HExz)fx_bHjyE1)Mt}?os)PB`QA-+HqukYJo-t2d#@p)%4A^xD#KDJ8|frAPyrJ
zZ)BWTF>+xhbf<2Zpw+PD||94rpl
zTvxaedhXl)QHOamg-^NG8*Vt@@^Y9Y`zCME{Gyf2$(iBC!WOX<3s?!ytQfu8sa2&8
zcJK)~@Gz9$8j$q*3PdqKc
zf>-_~@o&vdn5Uz_z0Uos&RaTsnc|pb_hl|~@`$1vaVV@D9y?U;=`f$pW#~;1wmC9X
z4@>hqT42SIq3mqfEGuD)A>_bjzJ0w*ELx68)jm2Je?+Q{(Nk?pseN|%40vWyF!}jxNS7J=eXSG4oXbk9`rQR2QP}oSj5bZvD>@`*4A9&wY9-`lbx277LV2ly#~-rOG!VeLv5L-e?WDn2_L%%De_i
z=F}$b;3y{QXr*w3p|t>>w{kZKk;mxXdRBcYBHcV>-JiMhL{lBzNp=R9RjL4-Hn>i|
zEO?jcRMYAbXTofSMHc#Lq6)=`@vM)MJzuqeuR2N?1U-$Wbb{pGpx>
zIkNOV^qLCK3Smy1YVo`eBN*8{=&;mgpwuQSJ;PrOU=O_0N+vX0&<+9&iepOQBb$L1
zFj|@S6t(gWS{dFvXhfB_&rBm(Tbi?+3NZqG3OLPDY5T9J^c0kiY92I79y^`oRLS18
zY6sTO=(PuZvpd!cRS_)QN8}#%;WYXf3r`{NpEX^!TKDTb`bupyk|>L!r?LC
zclb1{UCLb8Dvp;{7NrurqcL~)15RZTBJe6fDcD)Z4O%Z8T_R%J9
zq;LLGm
z;`#|~vz;uT2JW?F8gQdDh);0XmoSx~-HZ+;U%x;*8CTYrv(TX3KAfr4Y-cuToL}KP
z+u)b0-IM_BIGYeVxDd2_HD_V{+#TA4?p|jUSyf1vpGtb+E@Fw#dq5qS=
zwnR^5cGqz+{h7r!Gv}wYL~mf^`fV}
z(pKhV%K54^!vy=msySV9|MMX!p4vovb<|NE{{-VuYI5au%yM4ICya_)t^>`cgoaNc
zZrr`I<+jZfeo|u!I~j<-VfgdXyCzr6Y=^&=1Aa1P8*{~ihxyznu?X}Y-G|-_K<}AK
z=FKQebRT-(2C6Oxy<0%-lM+5M$X*-P
zu3FHf`0IFb!1*U0G=#Bx|`f`>2>(Bvf*7}w)sIqGF!3pYxv{%FNct+
zCi}~2Z-_C&S>-WNfzg#4*w0Ri`|w0#Ey7s$;BWYN{>{;dWCLsG%m9bg%DcC2ys68<
zIGmro2R_s8u(upQ)S7@q=5c-seyi7cb#r?{!|Q9-fC`esn{1GBu1ON3VCmB&jt1V~
zrwJ>IyfQ@LccfDBLs}#{q_ZdDWl5`#@eNr+Z`9}^N5ZFTRqefj%G1AjCZW2yA}^%W!?Pt+49)8MDVWKh`ZWNx(njZu-{nX&Gz?di)Q&c}k%i9k|$QW+eo)tm8X;sx6?FyMYKrhc|m6FM4%(X|G6tcTeOMswmQD{i4HQuwqI-VPxFXC1xE>y7QsQ;Jnvb~+JM@Jg
ze5OyWtFER!M}~xWpVaDmQ+$|BReCV{CeBEYr&NW<71k9@4y&19leP3@pAiHr69>Nt
z)&WfwnQX$SqHuj==9_gBtb1%x@Qd-v`P6DNqrv`M$oTdSnXeHe-($ogqMtW@B<~I6
zL89%XnIO&-J9Tx&EXeR>tyIfpOosb`z^&KLRpW?}UYMIs;9HYDNqIPHe18ni84O{dU^2c!hA<*~wv=h@k=}Kf
zaG5b@w=2xItjwx?=O$0ctWSh-8;Y0%l%561NK{CM0t+0WlEvB_KGQ_2k
z_L%DU)TTq$F&ir27pC_zV)=fk)zmZMpxLabHLzmP!>kybgYO5Y6?i2|gXhLYT7qmU
z^wCH!&FiDa2LqzRO6MwDJ)}q}q?s+t=DFE>dvhr!#~OI0_^O4`{-NG~K)r9J@U@WW
zJqI;VnN}uZ?TTBTJ*328GxUNJd{@57fV4nqxKOEK_XZJS?*q2IMVZWaLnGZ_6
z_uD*9{dSDHdw$$YyKnf)CVI*?oH#Ygc8@mF+*+CwFFixzDoGM&98M{obrllD%pAB-Zf43O?6D4c7%F@eoEWWqviJb-6T6(C&}8pb-TZlsczy%
zcsIl@DC4@?-(j07&4F)T<@9Y(crNS3qg
z5>7gyW9c44Yos-Vn}>O6=Gi;Zys^I2@-=DRHHK)GG<>{vT??uo+JMN18_bL+RPfe+6n&5najdMp3Q}b5qn#c-qw^`AE@!3#&mgf
z%cE+Xm6KWzzbsUu?ZJP;hMzTO=c}odrA!z!WRrP{vVY&N+N%Za!$O-!2F9O$WcWd7
zZ;mrU?rANzuKiHlW`%dM+3b)a?o;So+%uxse!qpaL?Wa8fA=%x))i-dZe-bRH`lMz
zG90@i=;?5Mj)6+k*&C9}Ad)3JI)#ADuN*2S0J0Y~$qY!MO!Vf1#l2AZtxw`AYjlIE
zBKSos+aA2^gXp4Hs`v4mF)I#JFH#R=(d=n+^^dGj4QC#S91o5Fv8@5A?D>sm5i4}2
zro^elcrzhI^Es;U`L*if22cvVs84j(w+*fO-6}5HFxV2M9Lz=4hgn8gJzBO6pSJ4L
z{E&Aa^6o?4VB`&!WY$uB+rO~a>KCbLN8gW_yPj6hQZEl#TlF<6N+C}{#%6eR3xK+SbH?P(;Xl(%Cf}a=JB~7}>73nWzLf8NEZ;qM~Q2sS~ytaEH-D?@l2gu}4@a
zNotA9)WP0DE40kA2m(00vVg_#6)iGljMG(Zu#^hw0X)UwaCEBL=43$&L~T(CjAgH&
zj$8J3Row3#YH%3PUP8paPS_81hOnn7@{HQTqZDfEpvQECPYKfv?8O>Fmim<)4eS}T
zs$#!e#*n3P?6PIJ
z>vKtCUI2V+8AId?9%D(ef?kh;L=v}Mn_8;{k@LNSGnAOKgGf0aY
z1;-kp4YTsNoOT0up?()**FdTsd70A2J9#F|sZQorWj_mlB$v^eb-Z&R?kd*b?j@NS
z?BhpMABHEK@on(5K)POzma=|m^9j^{6!(&sdZ2-XUo~2Yy!@z~S_3Z$l==kYOT7*`
zN0)y}_EyL_gj8R;Gqf6|wQGc1+U5D6A!@_=C<5{!w_QAB(g$q_JWYl|>qE9Pyq=?-so4gpu&$0UsDq?Vfk0n|y2N1O~Rea;j3N
z6Vg2XBA$Wg2H+EAl~3qY0k={@_6WNzAHp8J{RyN!=Ct`UYu9vSODT_8MkpWC4(#eB
zFB#XfC~l+}@y=r$Qe#*1Z0yoAcrT&ZdaSa`g=b(DdBEG{?kvX@9$(BmNHIKC*}=1)
zXNi$`i#9ywZS2X
z&_&7b&h;E~Jxlbwb;yu=-l!(VLT`JO7J>{~gtscM@QCX8PCBK%vf0T;aPWDtuRfhC
zRa&lZ*2VW@@CENXosN~9l-8$9E5+5h{lrp?z6|fQ
z$CkEZ-1X@_ME&bh5Cu!eilqdL)#4Oxz)QqTcx92_Q;1#z#1$)O#p
zR3)@Q6yy;g(gv<^RBJ#0v)G^w&cyjkK3!0RG#>KXgze)E?oAIvLp^^*R8FoT){uj<
zO1u9lrwzAh?F?&prHb0txx8)bV_AdS-FZ{1w7dG&NWiJVcgL*@sy5hGVDCzG(5Q#E
z124+;2Tl0)(jE5m5t#RM=cCnzbF-X+cZGWZtJArUdgh5^+SlXzv^Z7p5ECNplrin;
zmS}4lypIZXomK8d|n*g{_bcH@1Q9~1Y3I?D`kG4SjJ>M6(m+*Y*%G%-F!
z^72#J0*c!w?F-b`MbCO2fmJo;a)z_4dbSQX5r{i|$+>jmUtx`zSefBu-pk9G1f8q>
z&9~i!uG=(|T$#y^d+dw!{or;w!+D6(RO3@#BR>@4zN?QBr22m1-&)eO!lN}}Y0G+@
za8dzz^JJv0=gRChtXL{|@OYcPH>6qlbonD94GiSzslatAa_6W=qI`TWzo>Bk;A`~7npPZ=s8cI|I)C4F
zM;`mAwZaO&0U2X5BjF!_BqF;Ig+-RpA({bGY{MSAEg!tS99LcTI)JmWP;FR0IWXi_YH)|drz()HgBEb9Jyj>9B0geQuMYYU|K1G#prkpKlhPUZWPooS@?fZ*k8~F>
z<|0op%2%?XOI=DBbfvB)YVkbFzEUJiODQJXs%*_N{2Cq)98V^z1syf*MV@Eo*^~7y74jf_IB{#X%!|5?0NC
zt!}a$m`FO+lYmvXBg6C~tB0KHaywMEyL0b5gSEv|_wtYD#z9VwHLaZ_I`z<)C@X+=
zq!!wdWA)J#hpcsM(a3HS?qHcKCNZ#tAShOT=FeWqBHeBOCryZY23mU3=m*ZW0W?4*x}n96v4=)M4&^%fc%DkNHCvm9
zRx=!-Axy>pxmCi87b}Dj!bC)fjFHq(!h{zK_mosp$yBXe@?y{rO4id^#}I>?Gu(pU
z3rLSh#u26vC}f|629G&0{Q=rvzq7H83(;7@h7DAnCD)`dn$H?
z)E*~B2bo0-mybKN(Cf_Z_*mhxK2V6vFyFi?-BE~Jpq47#wxp--45b+`|E5i;EevIj
z=I^u<1!xNe7QVUTKAUYG*e%KEp##}A;~<@wxsXdtHExrKb2MggOZ}a;wE4J8$kv`;
zqbEH(;3YA+AHi*L*&j%2k!Aa`>~v_Gvk{}rXna6x&rtF4@TxVcSm}aSc7YLbdJ)0-
ziX-tCi9ZHwiof)$C}sqOLlAC?R=lSo9e*Nj6b=aP{1(z%VzhRb+I@fXP0~*-whBum
zJyo0M7w^MNQjVoX&aucj#p#|B_{G$^t<2lTSPg!P^?wah)p7&_7jP3pcT;n
zdl{}1-_sYvn~Lpn?2%&htZSzAK)~+E+&V)(8q?(-ir0Jk^!(~NFk-tWtz1|V98dkz
z-I?tJ5$P+FuMeX;p}9wWH$kMAkQfICJ6J(oiOkWV+p(MgLUt&k_jJp%5Cf8(%q&f0BREN~6D;cn!ye}sQh
z*;0;ksVd~4TaJWwehKG7JUxXyh9YNa{q9?8F+r;kO)|l0p%=ceWnr-D$+XOqcPZ*>Y%)5jr8Uyu%
zxLi^{)15R{8snR8sYknA2|o5Ke0j`G_z6Xe+?8-C#@9Wqeg5gaZNb7`+i}aiwfvUF
z)Q@rRjQ$?n{UnOB;#mLX671VcoOrgl)C_bwmvSZ*vuP5|n6@Aq_NBHDzzYg71+>Qf
zE0=I9M*NW#Q*SVvYDMNM6FdbzgsyAVNuA~o_+g~!4gDdc(--qNyn#{4!mLfT*A5@(
z>WgXj5c`(|F=3VZcVryG45*mEcwUftNxjOL|9DlQ6)xU1pZ;0_$WvALGCG(aQk@r9
z-kIZoRdHZP^V`A>I2`MVLFC
z()aEoU;jtO8Gi?7ZwQ4J`cAzV>ptkE7LCzMdo};`_CO
z+*vb-LydwzH_)t1p+vcEt8jW|B_!KbcglIzmhJ=NSJ_OFpB2M`S@kda#=%8Kro0CE
zJ)QSTS|U%Iw4p|JrUhOomE;ACyiv-(A2-!+6)DSzVkOR5Ea{X>9Q{Zxar8up49V6UkOCX_2qxGP0s(wmrpH3
zdrK^taC(ni;!0NKIie4
zx(Ms%qE`LP=jC@{F|fB7v9h(Ee7w6BL(Vy}H7RhSG#8~pvL*fi^uTvBi{99|L6W>B
zTaYUAo{RbGn-|&QmZgM5@~g5W>7A5&A81>EXZ+6ZF$+a4Xk)jueirv{UPANx>~@-2
z+?3{%ulr%(2A*A&(YU9+w3cE(=ms
z@*OqKz(@@=k|kPegnl)&b(WI1c$?9-g6=I_#|Ch^XlSTK2`^ZpOfL{^!g3D#nD{r>
zES!R7p~di&H9A!rEA%Xuv+g`YFK?yU
z@q>o4OFJP)j99`ZGovBt(FHMjwE8E=GL}$^w#(kT$HW^K{nyTo1W)@CKlR$Z>T|wz)#|Bl~9wBzk
za@dK^gEc7iq%q2M^}mzrCNq1eZZ_&B_pLjcsYOj4YMM}UfTz~QSLIqu|D5uxov&7)
zgbO8_QNq`&6YlnUf^-^Y-50`ASfECGdJgooQS_qRhEv@QyH*`1NIiw3o#iAUkzhBN
zWvmd~!A9qREsy|7aK{kbsmtURbn0ZLXUIoFWtRZon$A9>p!$6wAI%^}fmFA8v8VU`
zOm|PXZU7^E0Vwj(d)Ynp`@%n(8RD(~oTq+2W=qfgy8cY^x2V4c_3ii6_d!3J8Rn^d
zaRDR~eP(=wQJU{ans2LFo@WoFqY2WB^Qbqfan}r^Jk7AxJo+vuM;Rg6ApFes*1BtM
z`_$?S+XJ3j5i=uAG`cIV?R-_cxwH2nA@;Tlcx`55m%B(#z2qU}TY=fd!WCE!N3+jn
zk7mZ9_GR>`pDy?5RCV{#oI2KbBCb^BALV)V$V~xdeV>_q#OQ%_42?P>VNX2uPqX@w
zO1dBDaY8P52z{SkQh_|GyGIrKJ?Ob}E^?N!;+WHmM>FG%=-()ho<>)BD<9)7!?^SB
zjJqDVnj}yTqY4kR&SE-!|3Eutt+9(m7e-wKugCC_AK%No>_v0QJ4hvz=D3~ABg
zh5ESHu-c@;!)i6g6=fsYsFK$E_9);e%GpqD&|P8l*R#)H#c7Y4t#|4mbyz)U6_!?Ad{L1L^&f7hkv7Bu@0$85av4(-x7Z$u(eMvDMTiLS^W_DuPb#0pbO?a4Nzm
zAYF-sBp4c|Es>sQB|Z1aU4y$cZ|)l4R?3y3c12{67yBs5=QdhfXoBW<=D*38ugiOS
z6O#VSQz^-3GIC_
z`0(k9lKBxxx`aoVYw)Poa>rs*j%6N6^0SDD5yX)&T9OsWwvL%5^H=c3?3op(Diw17
zj_l`n$pbTXcp(y}NhuA#3Q#=e#D^id{A%JaBpk|R<#)Lh_!Ki|;+bK~Ah*AP-3S(J
zkZmpIgkapq3FbxX90PG1=iloeDO7e|mDVJ0i4jr>9f!Ljt#05t`o=qP6Nr7uTjCM9
zgc`Gq8#ZR$Vw6y!jZjYs@K)#@dJew6%c<`8*0=S)QR!Tiwww2$bPGzKq0)atX@0MiUW@eQ4Bd}<(+^7N
zcePICOI>Kap>ON^F?Q7%ly;dTRk7<@*x1+3;#Tx3EADqKwy3U1Ikl?T-=lr$Milp@
z`OMS8z{!`f_Vn4|ex9cxj;3d@XBQxz
zCg9`?v>N~KcpBnp;FB*PV5wa9m+>@Ii=z6yy-2RL^!F*+Aremm%;0A5UY>?Hnw}uv
zu1-)>8}L*cko>INh7LRpQJEm|G@t{?3&$_uX#x`G%PlxnGEV~^=l=soL;TEO8vh(m
zO>i{C&-8@5?U!;i#LtW(
z{F=PAehEiIwH`pN0E3sK8S<*uB5^d|Etl4Y*yYP1&HHhVhWHui1qF=N%Y70@Lo=$C
zIGWf$%ClP8g0Dm3+kTRx2?%&%kCCuLbNUfq32ugNWe=j>J3qnCfTF73$*sjQh$33H^Lrh$t~;8<=OkQ
zg_gYK{f}fpDDh8}@Wnk(#Lm2Mz&lFPOGrTmIoX=J}u={QE8qNO&L
zG1`zTq*pS!8L{nM7)P{*%M&y-juy2%4jP3^?Hz$7ce&v0oy#)`-hM54(So-}E>{q|
zecjc|nC1Y>2v`HlP9ynq}35ZqgbYH`{f#N|dS
zxB@|u_QsqnK*Zu^Dmzjg`@%j3FtM?J{3H4TL`)_0SY(U>CZ-Qe%#p0cD#9aRVk(y(
zVq!a8tRugXJ%y9lazuf+LYgFzU4!JE_uS;%_|@Cb)rqCh_)(lun!hMj1e(nET~QYN
z7IZ%voNqRyG_Tzl4*oV3cIBU@rw)Nf%`ye@^Po+a(dkc8oHj^tD359}C%mL8jYtJ(o;x#)=9hI{j6O)NF{T-%OlqmraHlZ
zQhE7#jFj##rH^cWvHdsFQ$+KN@5oR`Qa?hZlsX2fGCUE@uY%9;b5if6Ew5r8@r2#}
zMJI5GyHt9Mw!d`FB|n*7I(NeJ^kTuMp4=6<&GnO?g_psXNq9q~lb0c#lb&JyyF$XD
zx5kUek?@96FQ8w~v;76smhi?!yC~iBEKm=gXVVIB5uRuJtM7WoWq%o^Bjho-UdElK
z=UI3KH9gO!S5Q-e9}vBQo+P}Xr&ll<&$I9nIK_b;SYEvGvHWCu^<59tu9t}K^yI(#
zt_L31t7yS5-E)J2IO?jl3&hikqq}e#!|ba9A_$+-N|OXmZIR>uQ}*rwQI+}s_&Iat
z%$Y&14i_;@;3%M#X|&DOr*J@q@zTXgBwO0lqq6O8soSc#pZEwKh7pxp1CAOMUP-pB
zq@1=k1q4R(hNfa=iHl0s8dzM!M1HULIWvISw!iNm1Lr)?bDqold7k(4e%{wy`y6Aa
ziD`LScZ1soj$DOx?)s$L`PYR+TaCTS-VIL|?Pp2;zP>h|-=;|@#mt}v`c|!d32tz$
zsLMSESWm}9k{=CFcRO9PmG!2!_EytuITo$0LrZ6LH~1QEG$cMMFLaJcKnu93+|DC<
z(CiU5$mT{{=N@)prjmdSXDIExDGa+ab$qJvCH?h#X8|vB;VT!v7&nVF^GM$ZxQinX
zV9`349-0%w9w`9#k0Z^w@NDP=)YR&Xt2+CR0mpT6L?_SHr9z9(J&f$Zxt-QwZ~p$>
z-y8qW|GKm6N8&)PE
zo}i<%i~AQ}wUj3v!mX}hG9V!DbPq$EsGT;045zzloxG1yC$yY+AEizj?~ABY2Mz+G
z)Cpb14cSS2YChuIbN|v+K~L;(fw;X%sS~pu{(kDeQy1sI2fd=M6}8Y7M878DzEF))
zZ+c5v!{49v?^*w$RHe6+J^cM={{75#oByT{ShW}9KW^YM5)rpez|Ec6wl*D?Fx4DNy@5D#mp5pU-!2}sMw-rh7
zHDZKLARsjnH?Zxk!$~ShmXO5r#NB`*EVa|kajTCJ{^8n~v*lcDoe!;D+_a&icHRej
z#0MTAe2k$k&wjJ}$Vf}f{^ZrN+I|_fvMY3Y+}dk0p`C*WH=x-U)BQi72j{bL?$rqM__jS}SgJ^%8aDkr}{<97`XpzwB
zxK1=AaVt#%N4(DM9g)x%iZTr`Gnu#He1>jEM3Fdh0w=lcOAu
z^!6=(8PLr#W^_-4&Ye=$w!r9neMNt&QnoJAu{K6;guWi#BB14llIX#ZcIdP)=J<>X
zPntIRQCoO2M$-z-Cfv@o(d-nX52J}+W(SW9+%r$Aq78>BmYYCeQfvaArxnL)*@cnHDnjQ>DbSUqWlW%n^pj6**z>l=9Fj>1rjz8zi4(
zw&%LRa(}t8qnpVLZy7$X&(HGf5rP3#^Pp99UD2Mxs+#{XI42Y(j+oy>$wv~vFm
z+KJYAPvO7#ukznQ94e`n*P5_vz<-&IRb2g*M|;&pyeoBY%r=E(DLS;f@Qq8zV!i?|
zY&Y_uou}($z!S6aX4t5B>Zg6tg9vVF{r4|c_rg6nyK^2rMf+jg>cKmrGH>c>NEAD9
zKVu5dt36T9y1q(nXW>_C#XFs}LRQ1)>a@IR4nL;Z=+{2d;oH8#=-bX!X;+)$4XYXH
z<^K^RdAUJ4@jmO&GR@MAyI7;4eWW@cd)uh?cfLkDHagvZkF72&c9kcrJ_5*tz?vB1*d+*wo^gDad9+x$
zm^}^3BbBQ-pvRt7=xK5LC6qeA@)q*VcB~M#j;L?1t1^fD<4=SRY~2j5!l3V6QerjE
zv@2&U&YkPW3QF9RBCzmI$aHU{JX!N;!vak>;F5I(-qc%yur`
ze!=WO6pJF%oVje=I_iVBzmx{t?CEWf(p&0*DfD{Z1bLh@GnCrBQgBay->AnEWN*6K
z=T%mk2|Beg_vHj1mkxAHXqlDZw1MKIa1_5$0Cx{K@j75$-UAE3qldAlR>Gc@>Cve3
z=gj6T5!wY@jNl`mYSqAE
zO=DaNiv>i0J65nsHtEhGPFU}nD+RT}N#c>>Osk&(oH+#4W*?QNnL+;pisj=}VqCXE
z<>MZ)K#s-TM#og2c;ZT7;&S9gcl%=B`}RVL-dPBV8?0u#ed&Zv{8MJQ3wAq@!1)BS
zu321CczGK$AsteQA!966t-z~ycKEb03wKb8k&onv7oeuy{U*+5rBoVpW2sa?1*K4_
z3nX(yO4~MYG=>;$2VN)1;8#BmKxQE7#PY>z1c2pGdSS9`^P*1-crDSLs$8>k^*w8h
z>7yCyukq8KK3GkxaO8~AqvohFkO>J{iu`3PPRH1sDD@rq|4w=b{ztozv#8IcQL8+A
z@IPc7=y9}%zu|dPWeXkA7|%vJ|KK^cePP2GoAh}lQ?+JIqU3}4%jpqJqDxAh&;IMx
zmf^lP$d24aQs>RfQg7A{idH<1EMNS@p~ZhAzkZJ%QGNW8E>z{3@MLxx@R&wfr9RgJ
zU{6+Y01`qgoi#gqbksil^|deDgHvWwIWu*QEsL*?&zr|O!t$7wjYF;jA3!@%xK0sx
z=!+iLmF08>k+j{B*AuW~Y6znFtzo3xAzCh$>NZi`;|A(}=fj)Mr{9%pGH;W(WcE@A
zjp}LJ&Ev5^st<{{+9s_J)bz|=I>q=QE&3U~$F5#d^ykR?0nJ$YAHpem_`&4)N;&29AOCsbgLMS=z5lMXbKB}>7`wVT7hltN
z@8i88v|CjyaqlrXrY@AVTrL1b5OX4wd$SHZWEHRGig%vYQa-(XH7H;2&5xt}oKVF6
zBs-N*P#QBnOd%`)A9oF0Yz{Dtf)Pe_gaUh<=a8RC^dfif6OLt_+(x0N;H!drk5e14
zkEqEU<_NKY&!VH-0D2>%H;a|Hhw}DSd^As`#kbTxT_GJ|PZ@c;Ud?+`?GJI(6Gx3aYRkt2;Ea;Bm4FL4V$n(gtmwT>x;mE?|zLIehgq+(w5k4hMy|wP`5m+o6Ev_ST`s&{0e@bYbIl
z)n?dIw2?Ysex?*BBA
zwJl!{pCXHmu4N2#HNCb3Z>6bumP#I8`-+38SM5)NQ`BdK{`H)V#sx7@%odDV|^H7eCfB0
z=|?81N*|aQuRm=za&l*4P^~^mPj_gCumzr6DGHeJDg1=kZ;ad)f9@o#!cNA*o*4gU
z#xhBz4W&uz8rF$L6^vNyV#GioyvNYJ>EB1*7V@CzO_2<5S@?8Ic(uC^d$SW~jVeA^hPZCwx<6U0_a6
zB5l1gYgsKQJ-Ykvw9m*+;hy@Ql~ccGxwP-uBt1ru=m?7gzf@oo*4Oe>M`CV`4W2F*
z&@<^bJKh*gUN4mQdz?GpfMi*D*6DKtbOLf-ppp*#AEJ%&LIW%VL&PFsK}ZV4>-@nf
zH-TsPr_NxTu4R1#A}8OjDNdoaDwPUDb9FzglTU7ExUW-K$16OW1-*;b?f?Em4?wlh`s8|IHxs{&x4M7uQeduAu}yXiUGD$Qs@iHoSe
ziMh`%hJwP$jo}Qs7USvbv|8u}3_pXtV(>yn3>nFqKsmfL^GwQ|SI^0$)$#Hv?|ecR
zS}R?s7)9D!uo#il*q$rxa_Tsi`~8uhL8#{wf@N>0v7xIkGnXKGrJ!Y%@U04U?rW^X
zQv$RcLzyI9;!4TCVI=K5_E8B^KM)Q~ynm`$KJG@T3anc=xKGLjCN(E
zUG)pZeL=fPXg4vpD&=dmThCPK8qM6-R2$WG-|I_0COvM>?tYTiC-{HF1yxd-Zb`A<
zlH$B2rQ((p*DWc+Eh%BQq{QBmV!9>8dP_>$Eh!ndq%0epqKsLtlNzj-0E
z>7n}(50WKc2fAXb6yB+I;a+aS7r-+cpoy?x;N6`Kd$R?!Ce?iRQc#tH^6jTVQ~m*#
z9E2I|X*Myad&cu2tX!>s$PkI_w$-+(r&Kl*f7{d-~DSf
zMP+B^(fLWO(CB2R^&2i$SV;P}+_sd3A2}8NY=3S>=dHQWx%jaHwjqu%L@1sa!sHc>
zu$pkv<_aN&(6Me^Uz1QOhizjb2n$mir-TKL5T32cUd``Z=P1>k>Yv
zDVwaBso~{vsGTQ^V5w=huOlp%J!hX4*0QbwG5NAB*;W|6m|uE)&Qh|bCLM)G3LX5?
z0OPt?W|uQ{!SjVU?}{ETeCZf@QcqgP#o4qnFu4g<$eCesND34G(l-p3wt%S>aI3hH
z8CnH7CG1vpO=jad3#34`x(DlPa-~^~8YM!BmF_#xvz-Tu^Xlh?b3EKLvb{ZANcUFU
zNw;>v)*vcvw_W<|BC{#&+$rENy@DlWM~GcHVV>Vhn$roez)5m)VFHs6PsBAV9U-70
zDJDb`&dM1pvnE_nXWc$ScEfT4m@U7}1ndugtgQq=f-cUd7mR}KqC?mY>Sen^Rq(<;
zge?KEf7|H30mxrm*m(AgI=7%za0~O=t~}ZRU2qLZiAM8`{6U4bSUzH`%z+`jqJx-LeJ3o3
ziiz0(F1R5wk)Xzv3Nt`Gf3Cm@FcT}C%2`dYQ{eWdDTDIF%Gial%j$<8=N1^7?jJ(5
zb4%ex#e#5v@*-G*=4$M7)7WX`H0qYL&UW(i(DGSDJJrZlSTnq{q*7D40`;3Lb7YH<
zL9NrfIJWzRUut=r+H!c;jae>lJyh?1o$cXW%51ka_I*MSn43&6@KTLb15qRBfBUoh
zTTY(;HZx6yZ%b0qx10X$&1a`%PhpcYKao-^G&UhusCCLt&@KDiL^DMG$h`N7(TSa;
ztXfBoyD$3#M~`h=Wf@mtbZfH@OaubM$%rOVcw$iU0ge;Y*ENY~5_!E`5#gc%$Hke}X^(MY)io(aL#%&XK@t3EYgt`F25id7B_^^tBD4+OZ4<33j*(4Z_sGKi5
zrPQ@G@4dk$U!O6?a_-fd!s{p6+Q)68+c3p(DLgFA*ug}vM)V|Y%gB3s=~jb#Gk81D
z(hW_w8vph;X08u(V!pNFzHepej?j_zl+|SD={vV^jyz&bYT?x;+*TAWyJ}hR5Lp&%
zZ;j-(Tce;44v!1nz^JESn~t;!dsJrl7~I3q0-!=N$E#1ebaeshw|abg^|KEjbLq5<
zX$TWY+ODu$Kl-87r868+%eYYHLw8&IkrF`47b6J<xX)
zrsksr%2BDf(=cb!@p%)t!p7
z249;28~uZ)EAtH~G4fT?bajN)GnK0^6wpYrFcN4-&8BZqQk!idUcwve$F8ZgOEY)|
zI-6#BG`{iVJ39GlL`G^A%%^Ph9o4$G^uN@q`NBrEPIOe}Ds}33Glza0wpQ8giQv#x
zA1i>?E&M*5n9XfJFrz?lboFw(obuatCUdFd`gP9H>vz5C@>j5Oak1cG>bkg%zE=vW
z{=JSBw>pvHxO#2HF8zf9MU!J|7<}9;M8q^c3|V#PvnY&EUhU;qj={}3^0yQ%~Io9uU8Ieb(jAH
zn64R8^XD-ZoEC5W1PSgMABEOyik-2fkWU5_w*KS;ECcU5Kl!2tUp^yq7E;UAxBI8f
zT}>7g>ie1@%1ogiz<&>wR`}F3drEoaQ&~0tpBN1!$&uU@)gEgzef9ds8>Sh38GX>3
z(oZ`y#t1~WzRj5K%St(SaC2>lIOePh`zxDZpX;m=uA5u_uk^aH%v+|V=#D;V!5W?*
z#-Z)RKU3|*!4=ED^To)9#Ai_J-=Uq`KN#rUpxzUQTIt>GRonI&wGm8`HZdz2?G_e_
z!!~Ig+9=LwVD;hUlHUdSzY9h?B@l1S$(m^p7I*eRA-O>Ur4YL}BcCH&+N!f+p`kz3|&
zzflDVjTm^9ky0CVYTUD$T!TJO-%_gmsjYFv$I7g2bAzAcu;((l!cHfLJ;J4E8G{zw
z({^|*Sl0@QvZXlZM*oWB(hq(#ee8^lGkj)UoASr0Ure1k?W1X9AKv)zBj7D(r&wG@
zC+KhaaStDvb~174Rb73oz#i<8Xi9-i9{k#Rp9O9IGs$*6={<$yt0GphBU&
zfghud%UXLxXb#cy60FnKXs_M@&cech`VN2D*8I*Vh<;68i^2bfoPCBj`X!B%i^~a(
zv)*eZeVhlUk=$y-$}3C8Pot=E@$-4`y}P*Q^GPRRv(9Mf?t^X#a4?+!;VWwe$WLl|
z!%r4EAV;g}HnIQG;bb2LzBoA7+~~T{-#&Wpqp%dX{@@dY$v3PV|HPC+rN+X|y3hM-
zsujXlennb~sP{fqqX!&rwGOR5IAvH$L<)TszvMS)VS;=>ITr#`E*C_@_B0hb65Uw;
zu{e_u?Jg~brM3V|lC4E{=z*<2gj^mcizzg#5AagXma3lnlyY-X16kV)u7l1N;_GW?
zXNJ=0az!~^OkFD&qHj?9MAS}HCQf*&`K1|Wto>ZI69W<_@=lN#M3^iFK6fb^8oXp@
zkl%=ieJ&k~du>W~roykkLZ`uav9c@6)d@YsSvV1|K-vbniqRh{Ec@JrTX)$kegUte
zH+;9MGKXwo#LZo+A|^?zg+N**SD!q$bdzpLA<@z?^+X}!{yEeY0$L87_?`mO%!kQi
zl80{&*?N{yH}hdHcN&l}BtGZT_4dVQ#KI3uD&Vx$A`2`vjc++k)W|+X0
zZ3XY$Zd^ish{mgLg0W_44|#lf6M3;YiJ)8+e=GQ}NdtG&Q3?GlZR%oIr|&c=Pbp!
zgU68LgWvY<1NGVLfAR7MgKys?1vL$)y}fz}hhGis5+8cChAbNIyoPhw2dO?o9$#84
zFMriWsd1D#6{%C<1GB4d6J)&~35yFa)2TUjAa9A{*JhXCw?MJhL=JsHUzz|-n#X&<
z?cf;IciOke^`X{$OonrPCf!JAV?@a$5mfRc2jzqIkAlP)-par;fS!$#w;GbwslH<@
zKEjnkgN)SZZ+%fCQhj_A(Gy<20-ac;G}6?O?wE=(6?77}WY9=4GwpO&uz|W_0y}9`
z%7{N@@{w6E5?=h4D460?__U3dEw{%Y3ydkQ&Ns9|23zNf-|J}NV2aY>A2#X30|+Tn^q+TVJ;Q`BA$1A
zhsZ9it2RLjBQy@Sq8eNS{OowjWAAytTn5WCJQI)cnZ&DF6GlX8Dd}#JWeEt0qYw%i4H)
ze&%dTL~I}D4q;NibmWI9HPlQQn=6+8o%tSqDuc
z8BVOz1V1Hibw_f)->Q)xH8Int%W-w=>pYj5qalBM&@N?+Pp)D%>Yy3-)}RlXF!&u8m@PVtGE88MKVA(G
zD>EXgPsW$<{FV>}+pS2kT!;o#K$)OkSmj4$i`y%rNxK9(sL|k?Mx$gj;1f;Wx44Sj
zC^;>MOI*6RaC$oS`CDC)l2JEYq3_EEF|hw>cCbN{XU>94O&LU}F9Yf)b72m?pjsb_og
zFBQIIK3r&A@}uAgS%oOc&x4Qh&sxVaLGSo$cR+ociM*!8>H;4$yG~U@2U56d0XDoC
z$W=6C#U=ksARlO-lipSqptrp%%P8=iBFXD+rD(_1cb|_)e#-19u`;i%rS+7nU4PI8
zPk|Q-Pqw9l`_+&<%5Cfx0vsLP0g2yHiMo9e=7%y8=WP};gEI>=*WTai$Os1Sz9Bh6
z@xiLf{5>Yo&blXI^ZjK^RNJOkStvn2_HG+8Jd5ft$gG+g
zlEZjo1Ry@>ijrS!qraARqgsn4sjYl(F>q{u4ioLkNkIKY4}o@nh`dWxKX#V<&B+zI
zK=SH>)AK4$D_F>O1*{CIX}L8G#QMvk@1v{fHHLZf)cP0)L+QTcm}
z{w`F~1K=AUlt%Sq)#30ol28j+`)>at_v_7P66!P!E*G^a1d>bzv{`qzkgy;3$*hD=
z9fDbxaHuye;fO=1?n!7Q2^U~DCE-LmlW
zn(2+fjp=88TdkRS4pJ+({s-$rR!QpCu11_D_^+rAsKZRWJ>-^>Qcsz
zTgRp7;2C1_q3I`rPh`7m=sawXIP+4qWiR-Eot*)w_4`v1Cyc&n7^8keF*-;N
zfcXgU_Jh9Lws)>>POkUMyZ^4=|Mp&+RT8?GT{hNoU+%*8zH_vS$!oJM60542`3s`T
zC^{lMY`_;bGgt#^d0s95wYNMUtCU~pEpLlc%D><(Z&1sB=`CM>ms0-E-tv~amGXaD
z*gog*@#k1yUo(Ou>9_`E}Je7lW$~_$GPCYo40;=&;<|N
zN*sdcxTL6Z@(s#Ymrr&qJKxv&CHfeo#w9p_$SEBGZRLdrmbAB(ztL(!59Lu-f9O5>
zn+)){h-h9!r^8AZu0vvBXx{|-y?bJny+SiKr>e=R0d6gf?}=q4qmZK1f*QyZ
zC`my&!2zVZPPacd2B`wmZk#oSH7@U&7;nha#LwEGnQEw7*273n!94J-7BoC050~i6
z*Z?`!?k~sK{W0UXuMk(I%5K+yCk!nOq_L3CwyXV6eLqlJZfdLAI19e-2etKt+Ll8=
z%vy{#7NvB7)%|V7P+M*qz1AeOb2~iaL|XVtn+-PO-*^Taou!G;W?
z2to1U{B82-u=XzL4Y^!UU(n(1u=Xg=pX1pmq}76JFdaL60`5F|Jdekj{w~iOgSWAO
zd-J)%*V+g^+-SD}@8{u}Ha{_699N;lgByq_;t<~Dr1SQnv@SgSR;-M#)aYS^5pqjB
zR7rhxTlqU{m#FlLf-B6}>k0<_XIpu|nv)-R;^--P7w_=k5m#IJV|j_649-g#>&dGE
zez4zlQ{MJCHP7}A@SE+*$AiCX_)g8^|Bm)@Cft-4^R4H*?Pzc1f%gV~m-~(9yUl1X
ztMsP4uFpK*z1CKA_QsVxgTGsMQq4nr)uNHTkMH)vC`{Qs2i~KV&|xJggJ$pUa1%at
z=&FT|gAvbuvZk}|Wo7<53u_iY5_FL8Cp5qH*jHJ`dT4<{=N0!0eecYUv#zccoFjMX
zu=l@g|J`#1j})|jDZ{`1r2=TF!r#6Ug;M`AJdChGRLg*N#1nN_)0%&`d~Nxc@P3T@
z(YZpYObB!=OJ+J-9m{ff*s>oA{Uw&y2ExpK-YJ2h6APPRq
zo4Pb}P->$mqKEBS^!NC-573v$wxYJJ1P^#e{Jt%#?G&E%&X3qkYf&$w;RFDc34Df6apU)y+t#?~civoY%Jip~3>s&-cLXm-4H`jn
zlxKC%!^+=(?&E+CAm#7odFo`~eK1tM-;(IbV(Zs@_?=v-BLw*KSkm
zS8zk4x4do6p!y>{eZ(6@OO(91=IjnTFNO>Xb1
zD{hOi$mkzWLF7F^P9o4B>L
z3$yq4f%et>>E8U!O8yRS{>|KOCeg2sxO?~HWhY0KZ_X(`nvfH1`xG%6Bh1f#o?l&7
z9bqor2QT(aP&u0%ZTmUa6CFB|jfiNMlTasyX2V-C%fPG45dJbd
zMY82-U)wJVo0v#MpS{8aS;EW7+aj+89tdi=twgbNnc8m=Lbf0ircAK(beOO|2tU}M
zM=*WZrM*wsE{J3EQk8hbYAA(eIWG7)cjVM{*{lwJJTz*ytnJWl$CdR8S*0F8j`j4fj&%P`)fDqUcSH=mqRtz$DEQWys$M$KAGIE`10i4H
zYTPaOS?}VkTY1=v^4*A>Tf%35=RKovJ~4~@2p0T&6QGlj3;MCS7`mo_YSsg_m@5S?
zvqymLi(5a5?n+$BR-WV*TYRV{pceuI};~2RSW~w8Yc$zFl9+|6kU@j
zSgn-R=37NSM95|g=)wE^1-G0w2Hvw-z?ULYliyfTcTRz|cLkcCqj4b`Yab%VT~-W2)BvxT(X&{QYN5vDzfg>fZf|
zu6X5NpwaT-S-FC@fr@VQSYJkhi}z+{j`F?x;%>xJ_yG}#%r1NfntiuCdh#k0Z*I>F
zxs-2oX0Rr{I^em&M+(VCsW;?#=)}1AiHstdioUu^wCi@agzLU9b#XJtFtj=dp7kf%
z8nfo}hycj~Pe#|_WC)CW5_12@$U6q(plGij_%3c{j*j?O*_L=+mu56!*TAg*m8~7R
zU9eS-Wwr<%I@L2i`A2gIi!{=At)ZMXggF52h!A?$VsTVrkT@m;Tw%pg15mYa6B_M@5Lg-92o{vj5@<&Ib>0Y1;@>Nj&bEOab9g-hyCK62~M(rQ6k0V#@yxL
z&4?>WHaEG#Zs-mO%%%mbB}K46jw}|nVh1w+L-m@3>x1oRseUWyxj$WFcx!xEH{)2E
z5m58(=rz&^VW_ExgOubz7e#zK=ax@RfuGx8=p>9{9L^YKx08AV`;a?x!L!}%d|YXV
zYnsByz;rY+H5$Nbp+-n3WmDi)bD=nDhql+s){A}yZMId8tO?>qWe3TCB{zl*lE>5p
za$~at<*|u@3APaI{{x5=01fvrP>BKIRxTx&f&Ix}yL}aGUEyBrV_WIuQUM#n-WB%6
zRKkSa@<8coB{|3fZXFJ=uQEdP(U4sq-bXgr%W*%m}h#z<8TkoamV
zw8aqFrmU6Ok`D<%fxyV_26lv1%)ba&ZOOW*0snP2wI+`29*5O5TO8g!?$Re*g^z#F
zQrjBZ$-5!B#~k7w?&IkNk3CB%sUMioXW)c8KXS_T0`riof2IAqRoj351H+_GCVHnb
zXA|+f;>wb4o2lB`5i$%rQug|5yT|0Mj)&}tN#_xi9H3Un);rp&<0*ew2$>d
zV)A}39MUHbKw-w@|5q4n+Uo*T2r`IZ64g7?nA;jH214o*gx}C6CR}I{NCb9LH`!iK9@ued70oYm9>Vw_@;l
zUC*n8ZwOxU%+}~l859dg3~P#(XU4{4TSi;(7St3Y&&(LpSt#Dt9fxQ{$@D#}P#05c
zoyzw$))BzuVn~N>i$Uuv`p)2teCjoglSU(=kBCIh^p2ul(l_BL=sR{3aMJaaPLsgI
zr9Wvr1$)p_c3}Pvov5kPZPA?2MWi8yh>mQT$4^2O*RH&n%pUrmI*K5({7zQ}as92I
zmrOc6smvPO_*7%W37d7xkPeMY=<-31F8u_ZxYo7eunvtVXmw&JetPsLOsgGCnW=F;
zUBKy}!B4j_i=K1w8a&tYyoKg4QKVU<`Js8SeL{Og*C1Pe1B^5pm??yjQ+Q^xaI7#I
z=Md~Lv`ifK8ng*z>k^cik20w!V;NKi`J*WR1LSW*ekt;8H|NJtekbxTApa!t>u=7F
z>+oPB`(g)=_+B<9E-?i&u3PCe3e7r181ltljO_5Gy+-qc#MgDv4xd{6
zRdi(zZ~2G#LA87`2j1c9Q;gk+%EET*3=8=A&)~Eo+5s~$+>7sAXl-mBWCgYhh(fi}
zITdjO4NPeq?m^7>IHFJVX2Sum2FU~-9C%m)(`ryL0qK}v*Q7x2ooNjI^;)rS!sok)
zewW>@USoF{6TUBRP4Pa8YqMfC#k`?gNOawco)ZtdK{z-VkoR72RVeHSyMIw!rM!BLpe}_6AVX?YW#v+m=3mk8_KsN)D>UeuGxSWb>
z$K{O6RZFv%{&U3nUf0jRq!?e`FAWzW%-ILasCIys*!qaXi0a~lv@eMMrT_OR6fE`Eo9eB>Ywu5yK<>$_%-fl>D;MHnhI(KG
z-M7*?;sU%gFjI3zAC=afXLh_Pt?JMu*dr!g=;JI`82-XQ)OMo#>5bA=J9SF2rEC$7
z!P3y6%?vJ^wB&lpq!Igq_sQEq37}j{ao2Tm^Cjka$e6YWR~Xj1-QE&mxL#rw%Rk54
zxxG~C@vpM2EkTCsax8=R;w6)6eg?Iv)pWXz%ef~{jVelW#9rd-;BTIZs6JzsR>iV|
zS8KHgp6c2yGnY*&s|L?!5LAh>ry2*~;CF77S<-D~*m`|p%k5il#PeItD()fQ_g+X-
zZ;vZ*_tr)$=jSUT=+b&KcnC*Nn09_f0cEdv-ghRHBv-Q*70$m7
zV_k!Hclup=F;=CRw^^lbyM}6meIu}jFkW`MHF@7fCwu!U{6+1Zic7pDOD6Ft@xi%F
z>e{S*mu{MafmVVp{TS2V%2hk_Vv(*NCz;S9s0?S|B%3w91X>Nr9es<}GW)LduQ4yw
z3>T+i~dbh5Urty0Y;jXNmhog7^~c_^Bm}*N3bXi*uQ^)=QAzY)=)7PBJCd8f~st
z+^mCr{YNFxG6E$yihVIqotOUTaX;JT-Ze-Vbj~Ge@ybR`L$U5Xc+T$f`7v6ZW7jxs
z(srApz`xAzG2^NRCT~(z>jloSqB9_SaFCXMu0fi1FzACYqP
zu&|C}q!-=no>gZiWgk_`v@B}6ac0uFpQP1#tx;}ZWQT=U}UAj~4^GnO)Xm;l(1&cy%rlY&4JWrToLylDpyt?bv_p
z-DMq|Cs(XuxQfZ(H_G^151rCg%z8J@V-G|qCe%PgsF|OVZKT@Jp?BFQf@8>m
zKJoUR8{E^E`nulIsO;js@X`=@3ABkgY8hUR-IPz>BY#SkVFLcZrh`OYO|qhUnaEi^fS%yvH(dMtfVMvr5+xQ|rZ~LG=Tt
zl6Srdw>$V`c=+JU;Q6GTMy*nZ2HXju9kP9JZ85d9!)cEVKAXcm^{OY+R78J_wq>Wl
z2B6(bXHrdPy9U=ZfO!qd*L0pl+q|?|-)G*k-m~TA(>weUcXA$Z((z6)#%AMpH$#<)Uq5w(ydQE|@CUmzm
zGu7~>d`iHcITt4RonWLj4NPWOOIU@6|EcmDsqOuV1DN<8%gywO7hY5Ms}R#PsMKW8
zW#h7r06Lv~1e~70zuXS+FVZeC+27scIgyj5&{~bkYI&*S2GJlkH)8fMF}4Rvh<{VS
z?nV=
zHjd4CG0-qRsJ=HXq6WC;0AJ&s3-}8xd(Z8?9e6RmoH`G2>yxoV`r0e){9$=!4!B`z
zngcrrd#DDsdbf98qqV&m^J$~`-1oeTX7kxBs?V~Q@Y=+tS+|_veizi)RH>e9%j2M*
z>Nl=*?lQYV=~Yr
z$qHQxa}J_U#VjYI?mW_Z#BK19oYoAweDJDPZzY}^#O2JiEduz*YKt$x->ym@d0LFh
zGJ?~=HKEO==h0?D32~WeEI-GJx3+UDogRK^RdNJ86wOT@kv}UNYdvppEx)|>Z^jiN
zm$;^6#*qeozeN(d2T?MFLz1+KS@Bw%+4!6PPUEoPB@vDuan1$qhzWWjr=jcK@|bYr
z^kb`@`~h{?j1QEC@}slWKC1ULHfZX8;t*j+EmkoR;UJ3iiJRvEb&k*BmZ9!Gtk51R
zNjN(u*L%jq^Ce~~IV;;}2~o@b3=Zno-Z@h-zZdU^ob#)TNJf9-;2FR_-MT@xt;zn*
zAu!sAqv=+%a7cI4$v`-mN+FHx3i{IqY8||@?>a~PYD9=EBP@E?oBHI;5cK{Edx`ee
z8{PV3!VV#ajlAKtw)VE-u{m-o?jWfa@K)Ocu+ukExyL$T5!~L^kTrQu|7k(;MBLYZ
zR8K4QR2kd{!YeHB3ia2!FD(In%2#c>y(I|~k{ygHnR&F~>1s#_SKl+}uJ!l@>N&Ky
z%1nZp0n}M3xCuv@%kFRUo=Z#Q+v?yD*}_q9v6%mctnF*JDda
z%VL{s3e_Z))fsg$o!em#KxM`wt{7^yIrR!m&KeGTB`QRzzcN)b%@23^h3$p!((J0*
zJp+wT=mxx#l&l~^eHux6{IRIRE@;~>YadC^^kS=+YfhCOH
z_f_d$cACwC$O`R`9jeR`hgw+Cn94$CH;9%d-9geJ#95Z-#WGRnyzrvB^7qTwSJFB=
zsNH#tlxO0Mp<0$;M0huT!F??FHn3&j0f)x9l{q6W4UCcYhjOc=+~$ex9O@$oO+3Nw
zr*+eJh^?n}5%31Vi%!}Y8}0Rl?T;Pz_EO~((OQ^r*@PH&u$obBsuRHT1kQhrc=u{b
zxRPRdeWeo=PBEQFK%r$>VgUDAAHdE
zcYZMP+A`R`w=C)LrY*c;e$J;_cnYRT{iR4|RJ~ox2FUQ*|
z%yXe}uHMeoeHrmPN9!^s0^a?hPn3a}@Q0!=QhUNy;Y)D#UZ?pYK8Mk8o{{Y&TefMR
z>=YWGTw)7sYo9)^tvV3CI*abz60r3~OW-JlYNa)I&peusOhkuoeXdgR!ZjfU7WyxB
z`9cHFlVV7b{ukU^!TkrdM6pHsp%eKTo_A>}<;Hs7dOE3WhFVryOf}iPZ+(;(>wR0^
zrANC9JSDp*&+dKuYnKo8%IbL!N|6>(E3Na@(&$qreO=*skFrXC>(&!*S$Gw=KD&$T
zQZU<`t?6~|le_<^yZ@=R|4DemTh7$~wk*vf3o&JrS(5$^gk`@f3o8#F^Fb3
zrWVrllR_%-df_;%!KfXT3M}%CEI<>iFrgG$8DEFj%T_H@mE$yvOv#|L`qyfhc%Ew5
z4u49}Y55{ZsbNpaFMS_fH&*EZWSs41o53p(q<{`)vpu1d`X}buXFzA>RQO@<%KXIo
zQ1alsqbD-2(E5FdFm6%XXS5UPMC4#`T0{Dm0gwr|8#7|HVmaAX3i>6GaH&tQ28C55
zSwcPtTb6-TL@Gooy^pa%<7GI-w1!Ryyqdd*lY|+uO*JH6hUU%d)Jt%tY_X|yPW1ht
zLPggguCE}^JfBg%Y>!PPNCbR3a8h{syI(Co7z!&I9bq}_IlBp8CX|YXZa`pR!=Rf<
z|7Zj1U16XD?XlK~W9n0eHQn>%wxl2U#474KHEK@lpCS%;o-)!s-?^m-&y(F6aZ=5-
zE{>>CpDHZro~MkI^ux5z$JO3bcVEK;`x8D*I+OzI4BDwGE^;gUVxlObfZyUkP0)GF
zC&Q=b8<{ijMEuTogQajAq`BFQgxezGnl_KL!_P<|;;Ji{-o1JnH@{UeNL?ulv;>2eTwc4zbFHud@@|{fPOhk=;R()$TH?L5i*q}Jn(Kh>CQBKT#4BQ@X%XER18&WDs^%qCdyh#^;CTeXSVqOE}j0%ER$OC{xZX>2-CdyI*LW!sAP
zxyjk+F}_FqR3(lo>X9wS6v;lcKE7;wm-&O*CXcUJrLNCiu2`Hp7!#z2xzLba?T!=`MqJZ@$+nSwXge?PF`U>NQ
zed9uNHAnn?nq}hake1KW`^nes?;DIc+H#Vwi~ibRq7~rZ;0ipAmczfo6_*`SS9`^s
zuuBd$u12|B$l>j+cRF;2)ohtP7{$JbnU;7*+bN$#38+l<<+;WPRG#f$F^X&HXUPcBdx
zE+LwSN7eUfoUq*uZfibzUQLhDQJPJFT<8N>FC*vf7Luhx_WTh1*ZhS|iL&rI$C9Pc
zTKEln955_rFGQ(wZm(aY8w#Jy0zC(g1!<7vUcA$*Ujjd}fwVG`8PK-80h%0M%@X+CSy
ztBJyU6qFiKY=kecb^?roQ$ua|3l4loRNqIXpwF;2j~<}<;Iqq9*V}u+rDZ#z_Yduw
zA)UYv(>3AsZ(F7BDwxa=_yrCi-4BN_TSNbs_osMoJD|mypM4i}WOKm5%pULQwZSU2
zy7a14+Wqxva52gfSK8?v(t|HVw6n#(QwOZ7qzJd9#NLu(y(J~%mK6Ko6q1lu2v=oy
zn5L#lZKq;zzQDv?MZBhS%E_pD2QVCP>7ro)bzgvTN(Q2Ty05Vw8`_mq67Sx5ugrl?
z!&o|hNoR~j>;ga?r?23@ejisM1Q2aZk|3O-%{Y_&U~}M4=?-2C{AIa|&f*WrIvwd`
zpHdNj+D$bzE4^92kDl8-&)9)qO5uDo;Wg5(35QmLb`hODoE0&z5wluODOOILXha{`
z3?CUu0`)Al@bqV#^%!z%m@7+28o$12{iJ+IspnrtPb1gwgBA_^FhD*&690XS!t5wm
zS>V6f40{dyZ;lqrTZh6Hcqpyw`Afx6SFlmH?wisDVwgMFkvlV09M%NCU(J0O*6vFN)q&pZ|8R2q$y@qzB;$IPV1oU4V*)&WXE(D9i
zUBl(njNu9%%oViH7fdM-jfl}QvtlIqiiJgSH~kk!xNjF>5rc1riMQbwf!_%HZpUw!
zaJv|e-*EhH!!H6q>@~vB#X`%gO*e3x3v9N^Y4d`4iw76A(SPV?pwIJyJ!yM?A?@ry
z+Nj~4a_YB19mD0c{xtR5o72>9k%n9T37TE3CV#TZ_LL``8n42L~
z+%;To>Q7T4baR^eEz-aNsU--BxMyajtv{;rEO^Vp=7sMOU+B?>C+f0O#;vZ*%eLH;
zXRz=os+ou
z$2n9C?FfDiPZ?oi7_Ek!kjk7VJm)QJ!&&xCaj1%BmRIF-%U|s=y{&
z_2d+SlEcx)ZTLmtHv+%gwZm{<--dM-qJAx0eg*IA)bd!snxy#Ab=W~OJdpOR
zWI+6?dP8CK3hwnMj05a2Obo>@Oc>UgA{v{5&*7%CTPu!e3ifKly5MyXxR=|KdvP}`
zhK3VOjnf$RLXL}F@S)HI?O3C&v(I!N;!&@J*MZ$1K8x1cpF>P(XvxOv`n6=?Sr5@X
z#JH{;X~^gPhpm!dj}Os^qFvZcE5fVqTUJ|~q2QQXW}If0=xZ^!BUB90hSDrg_0n7a
z&-1)Dm*yEBB_WHlKIxtB1FAgpwvJ#HQYdwfnuF=wjj?H_s5bN_^8OQ>vI-{?tT&BK
z8Hz8W&O*}u6}Mj8Z4&13q?6UPinppGY~6kT-v9npiGgAvkbH}@x+2Wpz5zN~;D%}*
zJ%S#Fzn2OCp9uGFRT~)hj8}|H_yC8%Xeh1^^n{w9Eq*8uTH8XWa@!^jBu-eQpDlC<
z<2BMy#C#^LLFiABz8-1$QEp%UgUPmoFHe5&AX~1yukEjwL%rqRZ)9to_VQ2k3EPdKs#d1jrlM8YydwL8%YhzJoqMycK#!U3>W@L9g8MD?tMQ#56uk1L
zpjB~-$_?{MPACu9aS(rc{gY>&#J4-3d(~ce9e*1OzlYDQkG;|r8ZSwV6Q5J>6~Av#
zWydo=HLb>d2j2b2J0L&J1!%jFk~LZK*9Iz9Y9(Z)mctmAjbdyEH(ARLvF<$lU9w)W
zN&6D?r1fu$K;;K)XxYO3ak2Q;C~)F|;bySbs%5Zh%Z}yA%I)Mq%tv6^p@$CA*SuxP
z`nEvx6Ud3&_8tCe6`MHrSc~zmTFsP38le&MxBloSuKxPJqx$8F93S|&TLgbqKH~Ok
zis@~x+pQ5yj!;gmQ&q<^`EJ&0wRI4r%`LizC=o7*&*nD4yASvG~r!~_dsR}
z-r1VZYS2G$PPV+Z_pZ;VufQP>Z`zAedipAB`QcA~nU){B3K2AzRq%PjAR-uidE}t6B@|KXomRZf$A(1(q85VD?(0t@HZVQ73
z&`S6$AI*kXs&sCqDmOH-WoF~G-cSc07+ck_n`$_syGm^YdD;jnY_T+7rF!Bm6&gf!
z*d{Q3sKr#T_-f`Y^U@E~ilce)N<|tUTmNKmqR~{LyT@sQe=my3c=-soe;r$v;%lk0
z3yGNp(+}^c=Njg-vU>pwjw9|KI@Y+(%1V#v{JDlDNMFZF9d1oo3U;=>H?+7A7T~$9
zX2r%^D=k0eOFs4138ixSVQQQD;BEf|+E0H3Eo-R{_c_%XmK0X;-R9+?(t_Q%VT3X8
zK6e;7ab*2`CgnA+Y(!snO?7Y5s+Dr)&ouVQGw1FKA{=DXlf>89jF@
zh2c&vV5&0qYpR4UGjwKJ-5QF5P?FU7!*epfh9X6*%$oj4@648wr#enpz4ejx=?S+3
z<0?5yb$|8afxY=(q#qu=mus-G;jU*ElUE(DKcibc7DI=29{0AJk%stbVR@}*A0FFK
zikLTnv6&G~nE;7Y#M^g&v4sknL|G0K$e#hU%{){#ID2<-9$eDJJ
zg$5$!mDT>b7a?O#H>^{hhc~&d>Y>_a)_$@&NxSQjUF#CF#3As{IxHXZYd^j5={mFV
zZx1l{XF=jH#pTOrH
zrLEJ%FI|Uq8owLtRy}-fSI8@yYXuKbws7!ZV6iMq>c}C$o6}5}13GmPtS4Jz)}qVrm`QdRPs_z##{1SS
zFZdB!aS07S!jgnWAg7eFj(l1V`OufK>3Rwz9lYCGGFi#V-_AYFv%@To8Q(IJT^s61
z`_!DjhEI|5+|lr;7mXdFuM(Qf@#F+YB!Uz*k(_Xx5<%jEzrg(nz)NjfcL_oQ++ZP$&8M4L3ghshQR(t%&T0
zv!`lmL#81{))3hI8UkbaC`;JDruAn`V>^m2)Y8-0k8N3TU>j1SaRboC%s)HdZgURQ0FQ}1M}PX30I
zQg-W=+O*pZRNEhGxx4(B7Ng%)smRy=6^pc*A4>3?o2#yefD3ZPVTMi4c2nO*x|N%+
zd)cC0))$L}@zJ(l-z9*OJ{}(bVYgJ^(lgqYp8ekwWS=i=(Fou3$&c)fexxPDul;dX
z=V^H+R`E=%;?cBTx}J^XRZbjrMuB6?+>-X+
zxEvQlnai%KRSo9&?r#`sP3rnaTa{bStkadQ>{TLl^hTVr8N03rsAD_&PZw7CDVrll
zJ3qYql&v=cK9=EOMy~XM*V(prTAaQ&dOyhDmyo~VgO+DqU!?A(HV%A@wW-GngH6Kc
zRl)W3RRphpdG^oU?~?rN3igm!R_xXJ7*Rvz968o`>ysrN;#Ql-=1Be*G|)&(@${$4
zaG14_HVEx0ufB)4Rf}=4DbVDwK`*Lt;d_gF4VFuL)o&KQh4!4ceg*AUoJ^>hx6NPJ
zc=t}?me6R`JC`F5I~zJd6e|w9Dh?Ph3)b2US7~5q=gsJs>t{V_yf?@AKuM@JBumm7
zd?kaAp0hs3%GN*Pyn>Binh*RA8j-Mx{>LYd1B#WKSeGbHMS64Tu;T;+?09IoVWi%Ai~n
z70JA3-bN$44d#V3h5vV*GZWbRJip)b{y)FZ=l83R%-QGc>)LCtwf5R;tt}F@>G*z`
zI3CpL<3h65?ta7?U&!gq1)z#%j%ubDxSm&jx@!r%p+YQa_OEF8Ur(F)DTuWrdNhHs
zyvZ2(-U2j11zt#%e+v)2@llXIje={MQgfp5c*d$vm%
zZ|6cFm-;9rXe8~Y9I8szzXbhvq>r)xl#YGC%|GP1B>55^FD`;E;P5ApCd&!G-9(pc
z|JjCSc3Vq!vSat#n@RQ;SCpHzuzusKxVZi$(Q#xaA9A=>T$DfebhJq~wEH2Qn|@av
zA@AmBQ>!#)nzAShw-B=9E`6z;U1?+0M`x#F;hh?GXcWZ>{IfkeU+!^H*(Z?oIFy~x
zzeHy&wXfSZ#8!$Os-oz%(^+myt`;#rif}^GdV)_{5Ar3}mq6c*Z)ne-3SIl(a?;Ku
ztP;CYTW|6^toI%@R?ztxa2VQB*dMu|{dc$AA`X-2{s2t5UrHOU|TpV{;X%=yLp`KlZ++M)+
zSvQClobmH5*&2gCj59RsN5d+Wn`&I@YVPvm+nA9%ly3B_+uBUEO6wIp_qrF}lFJeX
z_{W3MG$tHq?GrQ6skNwhdNDL6ci?wbf8-nJhBXe2n^&GtsSTPY1?}>2b3%JpKNeV8
zxI~jEB1%$l4Rq47ZW}xAyOK^lui?*k6l1j?(@Sq&)Q~rsmj#2i>@+G8wutY>`Nl89
z_X6ouW&I0LiR(VE75MsSvX78mWb10`OI928j}?%0#N#GAbT^O)T*eB$>IrV6sxMb2
zie{>NV@LRO!GXu??)7aZJhm~vIJxorXoHp&I{0ghY=OXAzJL5cgiVaICup~|zAe8T
zVe4|(YQBgVOE!fiyHEv73qBFvJbA(NR`!JS{BYy$?3;+?=4vh3>tcj$%FR~XpDKBB
zTg{g>6-zIE!^exJFyd&}Qp+mnuDkahF)kB*6>}xnyBA_Ff?6&t%%a+*nl60Y
zlJSVoz7XxU-{y6{UmIb2`~b#8{+-cJ!Lx4_?ul5q{^8-EtskZvhloY{u!26si0VK7
zpx8(~yxLS8cl&xqaJ#7DWa{U76+b9j0%08R<_o
zmco9VE^ZZWfiQErN_ph$0
z%g76qEX+Zv)80+_Ex~VNF5eqkh6oYBV`tdXh$Uh6-iIumg49@7jVo_(@w6MDI?Kx}
zj&^EgUoGFg3b4LIPnho|O4z^BsAt+yqQ0Zu(k_sV#na5iRObsHMJy5Hy1T`=-Q}JR
zfwz?X6LGt!M-g<#Iw3*Bn=S7&F)h}Sz_Ua~mI
z{u-&iR?HxtM^Y9jIiJN-UkPUi*>~Du<@-?t-iiuH_lJq5J9BR+1Wo8D{e$^xy>6fe
z8fCS<`(;)D+JaNg0R2NZ)HuVgBuxzT)XWuwwV%6nVEQ5XDR)+Sz5HbEtE(@1X=6L^
z*={$Or5mk-%Nk&Sf-nFYuG;~XzZt_sKX0a965k>0$ZA;4o>Vhs3jUo|Lqnlqy|a2-*IA#;AEp(TlCJ_q_YrG)
zTyQk;O3PA;jKp)6TunEb(}aW55WNLnH}+a9;9G(RIaHQK6f^1OANrLy)O~-j)_kh@
zxwn_Oqzvcj^=9+pf&cL-HLHZVVMpp5&aG%WU1!B8p4j
zQ7DYTUa-kXu*9kJ(>d@cB3SX}RnVzy%)Oze5n2{CsP)TLYNGMaY@nV29?C~OzVYq}xK!@W;(|9+*~d9#O3*=tnlG3OEC
zucN1(_V&{q%&(T60XJUkab6UBx~sRb06nwETW4_3Y>bco&l|
zMOY=_i~t-ivpI7c6u!}F3A=$O$29EmtWvS}Bi5Qtny{R3aY(*?xlNsI!hBq&F})k-
zqi?IM=FJ+5$Hlmkp&`!Pn?~|01a*_viQ{HdM|Jgq{$ZlNeZHD_F3MlHul(}%rkUR&K`S
z-W9N|YJ@~i^S;&Wve%S}L&TYlFWC^t-faF{(5PHd9+&
z$4`I%lxN%@?HPb$dKi^Q?R6p0z3t
z8c7=q%kl2$wIgB)&Byum_m}m4US?Zxt<*dKaXAire*8Ql(_+T7QB`;8MjOCCWmwwI
zw6ICU7cwK_<7tLRvZA3|oaQe_D$SDzuJ=-3#tR
z+*z2TnKJL%3Q+F>$K~@P__}4}@llJQfi^K(KSM+0oDTKY0XZ6?%%2rT-
zL^E^{*9rr5aYY9qU!y&hq888^T>-xC9=*=NgI9^4D!L`dV59>7eL!S^X&-Jw9AKpp
zOEFJ!G|rqF_*kgf?nPB~-C{GZI`Ksg?9YUX!kjt6oXB9tz{Env6Qp$}?c2NHZ7_X9jlaYtZ5lxr~sy*Rp7fK4+#*S047Cyd!h=?p3wp-2|^6FC~g1ZRJsD#GrB@WmlR7rDE
zS6C)WmKmK-N}PM60$3&1eomtmPUISeQ%w|eUWu6R+(y0zc8SpG)VxUdn5!tFfwt!M
zdqtPPAyk<x$@^F-;&(@u$Vy~j|bVal+VQ-|p4Ey=y0S-+UmM9L{>#fgwgq}maG0%<5X
zcnI_Zp<_bglYpyn*qKjG?iAl!MILwF`jXM_#yK>h!6EVC`BDkwojfWe9&236TQV{%
zz82P7n4kI!Nnxh&f}y-$ej~Yvq9xH*dXhu%#Q{*%F|7AOyO=hjH6Yi4jp%#5mP|;`zceQ^``bXH$na5*!*k
zcFT5^uj;X>jA0!l>_BB@qxeXaTh)9=2Hc1G1Eiv>u!+s|wfwU;
zD{27l0No|nY^voh_=Tv;#0nP|H+wfH#SkEwLR~ku5^*c+gX~Y*LJmYM@s;&pzj{(1
zTE=LvE5ED4yO!hnlI_eA=zk|(#wqtPedu=Mr+D_ER@Elr|JVtYV
zkD%?smE~JT0nFA_k&rZSo
zm=bR8@|C}b@*13U@^gJyUBv@m)%Q|P`!E)CIBOPvFXcJ^x=G_&9#k?D#%Q
zFKsa0AK=hdfQDwXQNT^mZR3Toh@1r%OU+mJrSIQq_RT_9-63z*{pr#pJM`8w4>R?4Pe)IZIi5(U)%B5ZQnd^KA9Df&8jDp&H?ahE6~
za`-Ey=7N3choGJL3sjh<_3LQ~6aDR$JlD2ncl!P9x}RR=tCv5<
zsl2yC^g=Pxwne0qfvjFZC&-z%D99<;vjpp?W25e6pMQLupbY1H2|L?@5jTi#kINE;|9Y1U5_~WeL$W1
zdM8ir-J?~P07f0nR5e=$=L*dgfr!Id~(TuydjML*z
z#Kk9kmJkjK+ZS^O4DMehrj>`uSQX`-O}0&8l>%?TZAhebIpBk!qF2a`W)eVJcYTA56b+)Z`AllyJ`{6@}@EK~k0F@)Z^|G^q-^Zg=D3Gy>Y|
z(;h$34Xel)Wo3$Ls%nbO@?4hUY;wUt!5*gw*_PRvJhO%TTyBa@+;=v4)e%VT!EENV
znWtTM8S=Z()^OXjdUABE6~;>1C8nF-HiGHD%d*RQe=+TD=JkJ-5c@OnR61*8&s&P
zoLE`#gKoI}C&&o>WoYvf)WBspSb|QSc07YI#IS7a_usyTCiCFA3U6pVM%LK3?RRg<
zkR7|F$hm%=QX2;5S#eqFT5^M=?=&*zGxO&7}t&kj4AcxwDn^*LG3GO0eAW_8IRJ3J6N
zS#kn{f$KrHJHWQ@1@6jDvt^a06XrXpTY7prH^QE9FGUDMWcZhx)Rut38hp2EI#>eQ
z1tL#7oXbtaTx+f7IMpT1#au|u*wLv}R&&aq>5WJuPr$1rwFkSCp1XpWjB2VK(RT4A
z3dSm=VMbk<{0PjwioSW?YWh7f=LB)O#+LH*SlKw}RK3oaS_+-dq^Dxa7xnmwu}+?mpI3Fmss=vj*R
z@FmaN@9jdaOwKe$ia61$5>|y7h-C*%Sf6`)7w{qXHZ+S7xgX__mXDWCb+LOs0n4Go
z6q8$u&mGRQ?08uV*wWB?nu>Cep8RFbpZQm1$}hK;p;Hw({!IAM2uaFLtN5@&YX%J4
zUuE6WEmNBmt(eT2On?b=(m4$*5_mA`?oN{~-5QsoO3aapmCQ}
z7i}9A`Ks0$c&Ub`jHk~_<$vD^NTesP^74NTq7q
zn+`~P!cRwfA9%{R+^aLLJEBXUm=0gx-x?H3V2Y^GorS)GyO@I>*>5R$%~Z{l+>MIM
zm~EL35GU}K)S>L{>$I7ju-JLDryxqb9wgJuDe^
zAv6;#usvXTAy$|E$w9yr6cML%OK~RrB%c7-4%4NdKHtrFudD8?g=sqIhJ$hify)dN
z6SB8a-uD+H8Ya!(GrIJ3s3FV9CtQ?h0aNaVT%Pre&baxY1S3{In@TLi3H^?NBd`zfWFVk=4KKM&7|m$*Zb#6CIG{i(}U<4~WY~
zKePH_41dc6w$|+f?Fhawh-8SYz%o0=5R>4tysrgEbPvi-n1NLUKFM~>^t9)Hqdv4p
zsn^|ysjq_qDhEreiFk7N11KBK($S^?D+Cdk2`H8opg7_FZyz_1EUMgU&Y<6k
zX8a!uZ?!pOK|j8>45z~Z%IB*c4}~+b^>{vKFCtGm_~bx2GXJFg>Jx*OK4~Aa#OpSO
zTequ}*B&}o}Nc`E15MebG`hgH0UU(-D~+B#iroiY2k_pWFr9Wg&^XMA!3gst=qMkC*1DiCi!2b$yxLjl
zVu8GqtQ`6rP&xPnHmX3kFK;ifU;-k{))X7>#;*HGXS5$&1K*niiir~tA)OHwXq6Ai
zriLWFV&mBfp366X*O&C+hPpu8uOYS`p4VVDEZQbUeWKn`zc#yKV6W)VCQf%O(LO8$
zCQctKj)C-+Jjzp?*y1{g@rvdZjwR+5n4ghyI(Mb8BzGm!NivkH@{oUo{A_Xne-i!B
z2ks`&hzU;mhzS|`56l_V^5NZnnPu!DIw_EF3-OdJ`rIDdFxwXgpC-En^^jv>
z6D?hTSCmf3Hro%`hrb;hws>QQ&b;arpuC%SMETjBKE6FfBu?;T-JnC!wUPTFap
zQaT~pwAVB?{!;uK=FIZ8-LhWA-73HjWX6ih3;Mmy{Iwd`-Gzu?BdTYo1Q0U%QX!QtV`>
z25PrsfNxdJSrcmw*Mcvt*=JdnqxQYUT7!hsbq!is=%jZz$Id8@6%S%2H=*?!nswj&
z?kzUjrL<*5uBvsN&>EqVnG=Y@UvtIandlY8f^`<2l&IA;P^(=o!ei2^5?0sulzX5-
zzo<{3rG2!ly-)X-J7?8T_pe53#hdp|HNAzca~mtf{s;WjqL}QZ18%A$+9E;hz+CD-
z!LZk^iNk5VflI$@Y2T!v_XYci4ip_}rGKD)jpa_@i%)B*$+&-<-BRQ_YVtg+>27L^
ze>RdINKTPyl6vm4Ve*+P>>I0;h$ToA8)Ke+c;%A?bt2t55ZtlYI57oO<@KgpG#*5o
z3Yo9mztyFUC_kEOj8Ww%-PV5n;u3zg_x;>J*psWjRF06;HE;t
z7r^}9czxMPi6RnYaUb3s#BG`f84b6Z6ZGy)@aS$fd-I0ul+!Z&bA9la=TNy>GY_X+
zD6j0NnMXO`!#=lL1#c>@Xq&_LWzK@xZLKx^r^%xqXZ3Y12bnT!z1wG0T+0#1T|>!x3-@v)i0*bOgn*>7wPO+n^4i
zb9E`S0)czMljo$T2%4a|onwW9er!kqI8)&t?D)#>MdC`3yOBnH=O?QfoVq$UZ
z@g}(^hj+_8He;T$6RE#9cf-=<$7#F0dFu;$xTv?ccMYB$eunx=79NSGWDAc;^-V7K4%(yNivt8)V4VWL(?l!pey`i+`9I4pD9s<_STE@`#6s
zae_8sI?a}~Ul7}H#M
zy+U7-z=1y_IxS(!axe71#-f9A9h!{0vGyA9i^j)pA&MvV7XF=u-)@8WiZ}0ER@E+A
zi@fP;@c7Zk#*}kcC{30;va}|sY;$x*b)D$Z8L^9YlTK)*2dnXi?iVR1Q3_gT#G8Ko
zBO3k}au0In6xGlZPf?q&x=0qHG>t}Is+mW0T?uOBmyfzV>pyAg9BV1K#nNLfwv%eu
zRWd97feI+Sd6D&016J$Y%sBGd@Xkt3aB4Rhh5Y`oFdN7@Y;n_ftIju98{?rFvJ1Rf}`p3|R0g2>Yh|IpgaZ{20;JN(=U}hj+PJxefJZX5;zq
zfG?*ge}xauk+$yg*~4Z{#zjc-lOHAP%-@V6Ssyo!{)#ZH?s&B6nv|ccQLvk{b*YfX
z5oPbasN}_XcT=$~fItbL3FPF{&xF@4w=R#18{CevY_B;)oY|NcgrN
zC-|62YD?KKcdm7-W?r|7bZ{QBxsi7eqzz6xVCkR@xSyVFmgt1UZ!qh5vG>M9=M{7k
zJ`vzTIXQC|4^wVau|q}+zYS~LvhXuz;6F23W?fO`4+~jY97}uit1RDr*8R_^$LO8+
z#{kA$e!Re?Gt#`{qU~=g%CTO)@;so$9eo|XDv;zD|B9E!gL#oTC@^L&Z_1YFlX7$J
z9E#1XhM(}GhiR04S!RuqWJ1z`r=(7#6ZPM|S9Kc+A1b!Sm^^`YupukE9Ts3;HK>p%
zb;@v}&4HT4Ld(+c;W@^eCQg`m?0)HGjq%}x^a+M1ZnoLw5XB;YX}=^>qU~}eC52{z
zWH?#AT%xH3C0XVDt3=no#GkJioV89oHbFEC1?W)$$$f$R*DDhXQjUScvBrhGX|`){
z6+r^Cnj!Cx$(qw*+lpHif89nt|0yYd8;*VBev9>cw$68#gM1PMeBbi+aQ}DDyWck-
z#)%MmEn^!?ey4vGNn0_PZNe;^$ju!%JZP8@z!Wl!a4$i?DWlXc&Eb_P$8fg7Z4sX=
z(CvlZabDXKkclZ&6V>9EK*}(Bsb;elJwzylr-;>)T|!?pCbS@WO7f
zR7XgSf3{zfRw>mN6f0EUYI$u%@V@6<5>Jrkw`Ok9zL^M))Qa!+Hr$xLE%bfEdc_Vz
zTazFAJ7k;RYZu4LF%~HLJ86dCi6v6APRy3%f
z-2=DCuF*lN|D-|Y6Og|yyl_)z+%`I-N@uia;EDEu209bmO-6YSQeH_uxbV!4zxu%m
znwu@3ANjf*J~Y3LEEi4KcU@R`nJD#)KXvV-P5a1}T4gsY!L{@qZm6D065~b9Q->^z
zzxTzZl;>NQg1%%uFKIa-RnJ)`QCJ6LM2W_-9V7j#Ly`oqH{314iCVFAl1g7>YT~ze
z^w0E;QU4yDttC3kW|^U9&FcA^UFttUku0_o-SFU^k3G_5=td50m5_$jGWP^1tLM(~<`~qd?3+8!
z0o@oh(ogwM@8$P3zW2fZ;eSuNLyYD(>WOu$dH#ld^6pC7TV=g-q14=IxNmPYS1~M8
z+FMmUf?2>!m*1pP`VY3w(^g@hBw0OqvzpKShVyfxl_Y7CgiVrmnQf5$OMCyrGB(D|
z#|<~8f_;(uqie$t6~tRAKZCVruMN-(DsQR+jC4K~6yUw!-Q6mMlI)q76BLjgj~mr4
ztUPu9m+0!qN^jPXlhN^|rrG5I#!*sEM1}j}{(O>`8Kg8HqUFwQ
zMv`c{o9*8MI#aKItsI)WUsG>;v-TXyL_CHqd&w?r(y8Z9&_2Nh43qW~uizIuzwu`%
zRzt0ODy&Kh^aqwwY0aNaWfcJ
zYKU>$S0MjZCvP_*{>;0O=XS_4IK7pj-0@`U>AmKuak#-dFnu^_L!iZC^$$^eW9)}s
zz8SRFyx8se;m+M9nlqs9i*gArM@M0O
z(bp;E^ei;>V^a>wZ_=c%K}kpBsfLIg%JrF4^8DA29&ZczPtNO-#>Nv=hpZ-;0)A(D
z!~Ss3=XTdo^KW>wsBo{@b5Qf!)VLx@r5_{5%pBkNA#b*0S?;`8VbBANc7h8pWVtc^
zlI||r0y!AjMR)b!`_)W}Vv+
zloV~^=nR%ko-u7VA_Z`@Ij}-0n2Pq_ubOe1dYlL>p!E48Gp>2F)_;hI*fmUnNKP%v
zEx9eqtu-y42TwLTG-`$6^BOipbeWlA@ji!It#a}|utWO{pH)k8Bk2B{(S`Z@PC;)>
zt5s2by3Mu|DfrO8t8=8e_{qp6R7Eqb%w*?hGe
zfA^7o~S%ieQy7y
z+V2njSodrFZ%1z(yK|!X6y3hF`b^=X<`!#d*c9bP1>=?alBuk)6UVHjdo%SVVJxF>
z=s=euE6cIyw-&?PRCc{@@IYbwO|EZkq}!ngX3Yx0`UbN+I87y&Dt)4>wYf#9x1?M3
zN~VmAg}?P1i08eRlfPdwI9I&E4CU`IXUAVTedss1HRd|kHH2fz-czE%@h%R=trIgH
z*(LJ3-j4&DUTnW@6(8yTaG0fgDwE%DcnmwJRsFY7|ENzH;ZXxYt*0sS?v>L&c~pDH
z(Wo*78dX;TZRjntl)aT~(XfoXP6JPjrTcx}HI@#Gj@=tOHttf~8>U66oyM1rkDjo1
z!q|zICccrDlkh;|mc&6Lsz;1Z`aWsi$eiaMcz(rjU0yy?lU!R=XlR;N_xVvA#S6;-aC
zt5fzpDc+X6QHaa>cZ*{yq49f@xW&a9NLd?5no(}AdDA)H&Q^K4|BUs#+nY7&gKX#%
z{u(LJp@Dx-(|p#~d-XhVZQO9RfZ~04rr){iqMmHZS%AItg8sO(KBT5J=SkZ{qvw^T
z<~2qSpL?g9(Kc*o{F=QJjT=->b(7KZ>Int4j#G&R`LTw;AC07^v&=aI`eWt{GjNYo
z80^GCRSfa|KmG9c4_z1E+n`Bv8TcD4r6L_%?S)?^8gZ7N)uEVjV_Ssq9yY_w+U!Z*48h_sY92>C`@J)Lv^pTg%0k)?B|F
zrSsI=EA^2#njuZBko&AbpD7P?xGjSUrSlP=cOuSlFFdnd-rGO}w}5smICGQq+DqRg
z&9Q&?BA+BZUtMO$Tx5OprE*gOo8hJ$Bnxqg(0MOiy1FP_VS#07pk#MM=@<>m(r;;a({GR0da`XlI3(BeV?RiA
zD?V1DuTxy!tY1H(USDw;hYoI(Yt_6d*Q$9F^Yh_rE{8@${Lb`>ZdK`3x&ySPaYp_y
z{Y@WwwqlKWO;ysqWi^Wrz@k*6!#d9!dJkF*5z%^XvBBHuKD7K;Pv(i{vlYu~C~s@d
zZVBnJzqnF{b~EV`)>NkqP1$!U)}r0YsP;9nbaq9%#%`ul`|f`;csBX}!e49vbmO;}
zB#ZjBK}{?M?xLF8>}kA@vW!ohWB
zd)!9VHN;>iA0xf0H>dBiis>J?#=OSnKOTn6__*}OYwY>Q;6v-;icG@I1@PWkzYRLH
zx%AY$m5<*5>27Q-tlXpRB>7FA91%qKo=gr65v8;-GKo>z*egu5oAADGtE3+`Nw!*A
z9%nbDBH9nxwR!7@tQ5@@fkbrutFxGw-L9?7sNAIKq}*=qB+T#3y4MJ>X6G8PqukVh
z2!4H-{h(uhf3~WDaw6Wn^fr!du5rvyU>|xU`;=VG9_ad&YhJLHnU&VKc1)QFIlbfB
z&d%Jm%!=E%d6THRm*7pFmFc)~Lld%%-ia!D_9jQYZCMO?9XX*Z>+TWO!ZHTuKUs*v
z%HD$yo{fES!~qKR#ZUgWtpCVWoSGm}oe$#QQhumWSU)f;td;GU74629F{7}wGjlBX
zLo>L^t8Fb9~
zL-T~I^%++=$J=R+Cr|Ep8z=n#{G?5uU0AGbH!EmvL!`Ow?%~aAPSVU~OEYWt%`Cn9
zr}N6K8I5`6{+!qLt@FzH=C$#K|30rfp7+ly*LGf46bAn<=9Qf?%g|QSyfVxy`!bDS4P|ZU(2$FWf<(7-Ajb?YemT*O~2c&m!tgvDm@E2jrXA#GW;CA%iL-_o6=dwCni_7GZnR
z4L`2r#^;uZ)Q25$5*y{LIFMf4Cl24I3IF^h{-r#Q}TN)xWLL
zmwt}BDEGrw>lE%5`hn>`_?_uL3gFrw77-ccCNwCxFH2qr$&JsupszuMoB0BNK`}Cn
z{_YO*k7}ne6Stk#VNZ%1FUwsC0c6?%r~{^~C9J?2eUO@^*F*_4$+PFL9P
zay9y_Y9^{Zt6k0dEHxttC#K+IhUG??rD$y68<8bZ*o?<)4p%wtKQ_2K)=_S__{aQt%a^!>SfhTZ}NqJxqjcfH_(fK1^#at
zXiqcLmom*md+G##3vZ%5zQCXJEwrav=l_<8_LLiZ-^6#&o?^R8?lqr{_P8g?eJLy2
z9RH)-^QKEDO1sfYvu{BPfUC)|=!}mXsZ8
zR~$21x2i&8jsa>a)u%TR3tbbcFS!vKWR%+#-}M@!79!qo=uV@~t=v`_s@$yVZQUH#
zTe-#7+q$K)w{oj0%(^u$OdqD=0xFX#gZHQG?{+Bt5Jfkn)oi~4EP31W)7Ia8BU$A&
z&YF|vBFYX6z_*Hrty@~Wx4;_{kG}L(hYC$ySdWGnvb57^K1J;NE7KVAlcAZm*D20(I@^5PBU7d6p^@>@TRgzoEhnJpnMvvbi8(0lz}X3O;V
zWVzQ^51JYlCmiq0{61!6_emOcXugcft(re!SZ7
zsZ3ip-y>VV%Fx-S^na@#u-e!&+XU_2f8Ed3WXhYHs;ueC@%zYIFQzNk8+J(lknW_1
z?jQH~Lc>m2K@_=d{`PJ1*ObY31q=UniQIo#g0Mi=?%Ps>jjqjz(gvCU`dR_HlTT|X
zd5qQ6nUis|su1a9tLa7NORqtCwAD1nm*&?ZJ<4iQ`SP3ILwck&wU57iG15ssJYSFX
zX=>%;F2u?k8iLzIL>}ji-aHoThecakIGi4@o$2HwO`!daZ>bm
zOTMN9ysZSBto;4>>^o4k3GN6`JO`YoDH*8a4wf8myX%l1w>qjGaiC-{JL
z3c;=geNWICKLi&mWIEby*cv)@HeMr5Z|K>*I^*(qy$zm$#*H=&{^~{gyHWb9hmTD#
zxE%EaD2n~a+I%WDw3IRCFB
zk5aadylN{vt9f`2*DqWN@8Lg7iYU1-uS}d_ZVR>6a{MNE(sA%NsBc+XCi?AuYUUTA
zT+1>l$MbX2shZNn4AO6|f(Leg%w#8<$G#a$zOUeJw+j!(yt#~w7&@^^*;C9qe
zl6RFiTk_9tY&p{2A4PipaxbFHUH|JmPwvt>Usc<^q3-Fe819d5fH-o$k=M911_^>I
zal@ZXaj5q*8xeC;{;eZ>VV{mHiq?=rOn`pV^nrhu=C>i9S~-0$R&odH<^&%V5I;h?
zz4f@=PbEG^I>>r_yPryYf^<9U<^%rpPNV~^o3(x_L20c_C90g@uUhNL?d-dKf^7lE
zCAi+kn#MoZ-|>rouD9@S4xaH_i>P&nzVI4@)mGCnXtt8R2$p>ra$DUcfH7|0Y#NGy#
z*H~8#iCVv>$Z6kh9J1CBSOy!S|KRi`i5&M&ti?%7K=5f(|Fkn~;yBNoAMf-}ttelR
zdJUeI#-`J*gwzAj0VURx9iEJZbWepJim)<_Qcgr15M@BXkR@LtTF1_%k;}^L4i&IQ
zhM+AD5LCeqtPT(~3X~fVY^UP=5UefC9|ve)#QM;)?AW*`32r6d0*YZp6p7#`rtD{D
z`jQ`+6_D14-uWlKGhxzb7EtUQ@Fe9{oa~vCQ*c}4i93)+PJb)^
z^E#jT;s1O;TQ2>3{Uoa8+KNbYH5xZjhZw*Y@d5f$#2nLZJ!^{c8Yjm?p8b^WqoDKkG}sl`Sz#7xBB7Hsyv>x>e0
zc^U1Y%}I+9(PNM!$A-uROMXDRd*P8C44w{ag9G!w^B`(*5#lcYDR<2Baz&XqM!HKU5*${hyy7X6^3~NlVFQBL
zA5mD{-0c8MeLo&DSclsx+?3PnHnSfp&5!91se}hl<+U>qbHx}M>FJ)|?6kk$n=njtmX>Np`C&VFOyXpr8K8-sOnX;O7!Y$jQA-mH_p*5#FnM~
zl$I5RDsaokXogv^r^`S|bAjIXM;f;j-G2+h6i_ZJ?tYCFy~)k%=*c(Me!!0)-!n>1
zhTikEWLXF256EdPp0Zr>s1x`lkDmU+U&FZ~DnTi<_lO_TramaInUS&U-yuUWwybP?g8nn;C5E^*G#EKe4LI(b@$Q`mXdOdfHGsJq7>h&ABO3u0e2c_DfSG>p!!{1ai
zui2>V%o*apSH81GuTpW&YCNsph*zSsd9T!ou;xte@Fmp~
z`9o%EW_kD7wTR{^=P^BAcOvIp>Deu3jvhO4^i2J^x=V+?ul;fVuhk#f^*ympI%1vF
zD~>9T=^x+}ic^X+inDmH@J2OGn-idg-k5AfgTt_DdQy!PpN=2sjS7BIXb|Cs^B0Mq8Iq~o`=@m
zrTUl050;`}@p0hj{|G?*yN~zCBN0d9E@nh2xRpFT
z@gqMQsRg{yg343SaEB~ASvT^{hZf-*S`X7M3gXfjZ`7=ba<4*F(5rT!9(h(Z{O+0$
zIs%hSd>^k1F3oZ97Zu7HoB&p<$%7boFKt}e(CjI^+3fG7q$wPN^;TkcAr>Mc_SBDM
z-AZ!?;{=ajR^I`%L|wYrp}wdLgXI`bzci=2F41i4*wpOlezKWHN_8BJjVG(DVn3{Q
z4kvvtK?vjcRS-v-@jWVds3v2CSn9Edj|LbY!Sp|h+x#1
z@Y*hF0Wi#h_XJ>zl|LBc8$M;X|NRAtTY{p+A%FbPU2?9fC(vH}g4DF#6c@HNBCMiX
zv0qWEIHah{OtaMXMLbE$A87+dB%}N=i@J}7-q5I^OOC1^Dj?Dm#Tf)VvM!8pXgRJo
zQs4|(Y=jV)Eu}yivO*IHVqOovu$fozhIzmD^>`BS<7w_buN<<7q?&7ULgEWdIGbSX
zO-pKtno2B>4~fSfhUall+Y7nWVqH$}_#!D+$z02%5|x~*cRYC+^0+g;#YR0jid^fY
zT*eH`3ndDFE{Yn*Pr&>v`l1|X33uUrAVYE-#%GwF3U6LHor-kyYpKw*%IOJ6KRzRM
z1LW=Sqy8Psy%bADK|qk5tj2T|vs#}^pJMrsLN1|bCJrKNfxheb`^~tc~
zIJu~7#R{S$#~-nbDH*Q?zZCclh#u#DkXok{QH>p;0~xK4aPgWReVrJJ^NWirK|O^l
z&85{Qszps&*NrQ`Z}t?`NGokH#)cd`AGaKG>0>_*#As>GXH$7!RL-w?#3YkA4ng8;
z9=XR+?$HecnLPJjJYpGNlGt17RfrnvA%uF>8@WT&$el{LXI`eCa_&{g
zoz=mgdlluLK)F|5Bsfq6Y^~lhu>>b76p20rQRF7~kVj9?7XqmyT7fSMWR0jD!2=n|
z8W?|X^gj{ugv8am#BU6|rnZ_fbNm?cdpWOfM`@0;$8VILhI0BKdXvp<#4p-EJ&^G<
z?>L(q+8Y@AH-BAd=>p^y?9#JUz!$BYFBthY^am9m)F$6$$TY~e3i*OH16hC67m9p*
z|ACA%cNq@)HN;x;08Z|qx_h82D}`4?kT!C)UU%zvUSn5#I%y;crc3+)#4Y5nW&*ac)P|uZcUp*7i>R;;Fs|nIp1PqOJ$6v8&4}7&L`ETg
z4|+AGWT4fIUYXFV+#IP_YK^bHLVeGs-$k`n?Rj5)k6_;={?%?+XI`ppbT!QxVo0F2
zPr?CzM7CJPl)gDA)tp`l{bD0x+UDv7z$JAG@J_srI|M|;dYem_N9!zHq-t
zBICR55%nFe0g5GW_+~{NF8hfVJ(NRlZfpSMc6hy}p%mik(h_N?}#ABa7rWh~^bV
z@fGcC^LeZ?wU>3Y`o3rY&u6K3yS@>4tX4MK|3!=T(x}H9zLg`@fBY-;e8Wj_40y;<
z|F?hRtEC<4AMa{n@R!U@5!9iI0m0r`!K3A`ruH;S^f$%RUfY=MqxeKSOU9W}L;Mu~
zCemXQQW5P{8ZY94MwN_7OFh2Z*TyBJlb=gH?&GqMy`xG-PfPvU_gw_XC>b>)^=sdE
z5gestOqk`W71$N0XRZsU96(9|*h`hP(>VN7a)zx*Fa4}Utf
z!1tZMhO~KP>MH;D?~sn4o4U&X{YRutsi|Fj-}!K)+lYe`W`M4&UImtkfzf;+Z3G$HJqcHvT`Ech;;Y9DD@UGVlkfyn)sU
z6|Cr>a{NVRSyZS9QAe+JYL*y1x9{A|Ol>PsAC+$J;Y^s#mo-hKWLOgb^9yz@Ga)mreUdL$6p%%#st?w<*@K-hf0?a^VE`I
zjzy!ND_!AOIr_P9w-B`Kw&S5~obc@DOc?i{%+Y-!=d5%w;lVeVbH;ygLfRV6V99{p
zWd!HEf#^9ObYO;919m)mZuhda`CE#oub;Z!S~iNkQD{g)9o@Hbj?NP}$FnanN1BTn
z-u{_6dR*az9#3%2pB~{Hy7_3QFB6_U&YV|^n2=V;8IrzYCkmY}Rx!u8X`JDee{hDY
z132Nq&CFnNa?S()!3`;1WOn|&iWy#hi#ZSU=WZ@D#9BD#d7ed21t(ZD$hVmRx@I_CJcA9I{OiMC#0!n&=fsTmMNe2etyOi2F>
zQ22rg-@XK>ZQ&eU#&gb0e1GLN&N=NXCiIxc3~!ZT%xEKHA9G$VMw!)I&o$H^!>h{y
zof)+IWFIa&S~Sezth8}Xu|H?fI@sPgVGZE!c!CQra-4>>&@n*#GWMlEVRpZnhS6Yj
z?*Yd9i=@68{(g`%T*r)AUZK4!mss%N8s)|gz=mq{bsE~;1?X(%9Nkkn!;eXTTLE`<
znRCWdnA^GR!9v4pySZJlz81ZD34Qqi-?y@!#m>tEu}crDt?G@TQQwgB?zSv=~RF@rmoZ^%%h7bgKR>VY9XoZC{M
z{IHIDaCJEFE0uHPZ|0l{%_xnzIlT*`eh*NYfq5>#IKRjG8N@knf59BZb1`?Yl6e*_
zA2`6hT;TkFJul^GHq;S8P;n7=K|@!WK*r)sun+^7OWLJ@EZ-(TL%-CpLrUCj~;
z2*U|BJqyAejujmg5o;VPJ1QP5umql0S~rbm$`3lSaJO~SN)}#i-E@S7@3(I1$c5M9
z8y9{E@44_gyywE}6ZT*~5ftONJr8#ks5UN-aqdVDLv*2i>td{P62t28E-}V%_0h08
zL3O=4W@Atv#8D`#=!hJ;u-cfUJzhce^4YNcF&Xb&7F4gk8HUKVLh*0ad)<2~KiV5{
zD*DWzvrnEYwYJ};+@w&IT9uoIsluw2n-;0U_A58-RfW~!Js)-m@A&iV5)=3Ks#Q*PR?
z6rLMQl#Mei>_;Hap(M^Qx`q9^{>*yo$BWtY_k{;GV}=1ERC
z{|u`wA}T7R0goTr3M%|LTJ?ZJPvD%dEWnxpj(4BW3@c}FwN}H+YmpPQn&^4=E1=MN
ziEiI1G}MmZ>Xs0FHzY=&SD-X$$Jvl#!z<5nV~dGqMkhLSo0&5K+~m8Sz;vR+gttRD
z<;MLi%x!pO1~=X2Yyjs-2VHutiaB4+=bShTGN_WU)|}S{9%bo_z*2_d?&#Gv_Z~Va|%U9}8*iJI(@cz6A~yT*V3G*wxOT-{uSl9_57e
zkD2qzG|urIG?(jQz@O}#V;six9w^(lC)s$1v+676I16k7h6!h1;+$0loa4bQoHOYp
z>uHl91rFqVt(he{90K@a+H@A_FuVpnVwr=nHUr8ZGUvfpIOkoAeMTDQb2VxJEPg?r
zLqCINEC2_288qH`@E_cRYkqxi`Wk1_42;gYc{n$HjY0J$b4)tJgl?c?KLldNdvVsX
z;Y#7X^Pp1C06SX%`wxI&kOj`pWsY@Mm_zuH6W#;W`mQf}6u}67&Jk~O&R@(J#m8vx
zRls%u=AaA`!pmG(!3j`TT0?K6uS-$x31+x!miV>v-eJyJTg?n30fBCt0iRt`-|OBJ
z9s0z%i3%BN!V=)ZgWC`gi#l
z=P&U5@0jBp&X%grtY!M)TRFWUjZ+{|_5Ck0?VAr+agl!bGiVksvZo7_!=R=|{|)^d
z%qe-Ffh*=Pts;}@slbx)khg0yIJp2a_pd?reF5R>gvHuli$ERon11aVJ5;D&+<_VU
zBU4h};f53{soS|BC0fN0rso`Hnl_S?--I+gRf!$K4x4gu6Stv&;38Mv!)Y2MU&Soc
ze-iEM?19C~_$8ces{Rc0vo$TKKhorK+FyHf`b&8B&?^k|3>US#LTA?<}-QnJ#6k9PZrL3Lz%FIX@7;pUJYzqy9xb*%*xRN6rl^-3#l*5ZT-2hJiekV9GbcjbPp;M0p9VoxM4H&Q!eS8Ly
z04D_Hs)2nywZe*rT<&TpWMvo>=d#*|Gd>DY4$$xY*vX3~3HN=jet
zWIJ2wTuF*38-4GJaTEQUecSFmmipjIGc(WQN5^l#xow-evh4IsnVvE{N6x6^mcpJS
z$B$&%Dhb?4;;G{pA9AO3f;ThiTv
z@4TMvjCPH9Gu~l1zYm%8-}bt)>ADery`Fl8Jo9*ao*{odn@(@Nblr%*UeBGJD~H|=
z;x^)%I2Lbxblr%*UeAl1%TI5g;x^(so!$oMiW3U)c01?FrMK^J8*xn>kGFYr-H5+v
zmviOQ+w!IYs!HlQ}V8Ixgd?YwectZ=6=O!Nw
z)_D7Af#90tW5Lkbf7b#VB`P-Lt}x$d5|W7O+WDN?fi>*Yo0kM};s$W$eWym?&fq2EX?{x0+wQjqgIm~9Oro@-JA(l
zE|OLJYpJ1?#wW)NWfWD`nGN;9{Uh>57rdW?_9qO_ho!jWmmj~M*Ztswpg-)sd)_tZ
zPVU%hSC$hIX?YBuL~}2U6@5ZIe*pH%Vfa0Ocr!D?aFBiUz~hL5-DE%X;NcPZZBuBk
z?zp4d@^Jpo`epBe7GfLh!}Fdox$K!MI7_0G%7!W7_1~UD3FO=aR{Z2Fi)|j)dJj0`
zP!4w+lDG@O`I9f~z9TI$Ew3E8T}pnr{f@K;;77uq&R6D7-V^i=^+o&kVGnb(HzSjo
zSx1mPns@o4y@Q2b{NU1Pn-{x|zFeEK@(XVnBH}&BXXdR2q$$p8;Qo>^$Y>IcObkPD
zKB>di+un1aNe_r4I(q*e8gqB-wSBYv=f8Cxw!WS;`1)7N_S08{)x*qvRM(?KuE!DL
zG`pz86p8@zzUN^o6QkgBh?Mj1jUJKrps#JpwjAUb>VIkLvu7@C{c3A)hYcAH-|GeW
zH5%5~qaW?Qw6(_>Z4n%|slIU(or+SY__E$kZ@JT{K3`x{#YRyHAObU8Vv3XpkB5te
za4slz0ZPV`1?{ff76-ohmM_oig_%fb3dhX|FC)|Kv`bqrg-qYa(Pwv}4=2di+_U$O
z=j!@CXREFrm0r{Z%4m~?Zm4C_X
zbo8qa=)ayEeA-={nJ{eF6iY%0d-%a=y`Ev1sV}y9vTLlYw3pVOIea}oEk(S)S#xRq
zg2JE1bGt=kB6z{tv5@v6cIM=DeUGUBuWyKPx{ke1!iOP7-Lc5~i*#n5B)Puh_4o5H
zZC$nBBg^jv{I~ICF~C*3Q+?q@Uga8Xx_Axq
zh&{<>B+0;{8?g0>7dxOQ0b4J9c=Ei17a=BSN=n`m?4)Aq
zQ!fgr|Bu=59#gy_`t--2!&@tQR(0OP8Lzz9W?||t|MX_?xjN&y7ux_=VD2yfxEgbG
zFt`#~=@5%wmc~FS&PMRz>JBX!Z%Le`i&GF&sddU0ninn{A4u5#03_|6^8I7JF46K*
zqetXS1a04uciZ5%J!(xrOhP=3wQtVzoV9PxlpuBeT85+KuaK?sI{p$Dwnp_;{(Q)J
zv*gkH7tNo1ayRJ+7;oKzDrBn&`mhtEzSsQ8^LOWk@1|fJY3A>`eq?`j$lmvJ9B#_B
z7yAqDp#7kQU6%Gkk*bK+ew8w%I@~9RQLZY=uRXDhB3#EEkn^0c(laa1BGEIl=e^o6
zV6A)8KAb1?H|$H=+V6|uInL7OOkVwX-?i>H_puWCrY&QGFY$o8BxL~d>&5(Zj9DcY
z!oI>%aFMzmKYcIzoUi_MNSY;u5a&MdxD}gC(r4lkoQ05Me|30%uKUCMI~ILBYq&>h7`aT~LJ?q}3
z%W=07zUim9@u_m*P2i!A6}r0Bvj`D9c+%?&#-@H9a|F2E?~6#h|2O6uawms)lu32-
zA?LU5KIj^RtQ_l8IoF1#IM+LqId4WPXjnZC>DDKeyHW04=cTms273cujdbU_eM6Xg
zd2rYi?25$N1^(tgAb;pN*fE=(
zHaRsR^~1t~(aA+03o-i=aLSmgR}p(#GGdzB9ng0!-tvAv&UAE8y=u2q-Z_lwM13~3
zFo-dw#
znQTCWZ_(=V>8X`Pt2~Ftx*db)$gvE+;^(*C0e*-i}$`;~)+&DlPG>Th<_
zu4TyB6-hkx&S0rOtQ1|z1csF$^H*k`_f(k?+_y2wyzy?
z>b`|Vs+iBOa>qEdj0~196&H>2>2ZH&hUf3s_$`4BDtB_J>yPlP_RVjr^r__$j4_;gJu{SnT@`l}AscLmUew51mLVg3#>}w3)W8M^#?6D>9mwj3H~uL``u47Z0e0i2L2YB%{DGRMwWDn@W!M@ro(iuCEg=
zt>3-gJH+P<#>e-^`oN~HXte+Of#HGdbgdyC@jZDLzFzk0Z(>R;`A91atzjthr90EB
zDzpX<%R{tV%U`v|0KD!kh$tM8zGwIRDPNnJ8);2MesxHaHHb7nAF%O5Z)hp8i9G>(
z%J72JaP8K*Xui2FvQ{yWvxV4&{#3w5eM~|hvH#WfegLB>tTw++E*R_XT;tHy+6P6P
z7+Nu96nOpqLyi)9qb0>cmerYA8yzXnzJ6wDG_v)GWsVe-xzZ_PXocha(t6&hPyg~y
zH@>y%#?C?q)qZJWJOY^ink?A9KCe|GErEnGCtMM6$)ih;Ydz6Y|b
zU>_yp)^GE)O&yq~7dP4ztlTcUN3Cr0DoIsLcmlRif$+e}RZJ^yk}vL*5qWJ>Aj|WL
zaef|R4Zlb3Vq4-^*T6eD`+nDuRBrhfUYtyS46A8#6`<9#g{w^)&&BIfv~!1=xkepg
zXQe+n0pY>@?iBmj<+W5Em<$URMcvypMYjwiPf#?hMe)k#2c<6+jy67F20J|CSP>lXN$9SXn%J#97G`roV
zc3XMFyEC<8C(%3lx*v84(rUgF=VT$vMs*L_3!Ja(sKOfAI-_;cq(M~vOrZYMJH9EpRZS1L%RVAtWQV&dbXMdHD
zdZR8s-90|lk-D(RgvL>tn;TcwG&>37*Or_pu^+bYI~Y9WUgahjO&{MDKmG9Uf^84~
zEvPj$fWO?4D_5qu)j$n%depocGX`gDN_P5Q-?MeQFON;}nRoqgm!1A>-MSyH>qarq6wnUN|a!%{Wy@Q_2u%T>F_
zqe`9mqN&e(MhY}Z)>DmavIXlIPU+b{rNnKpf_86)os010l~V~dwh5NV@ff|^ZNwC`
zTbNAW-;uV#v#==5)D2Ri$jW`lAZyl!?E#w-RdSVRZ|3eZxurFAOvoFxws;dOW
zXa8aTJ#(EKJ^Wnfsq2-8{FTQJcb>ccUCEr&n&Yf}^x@%oBXWxKcjoQNQ7aDg(WJBX
zalQ@6lY;D=j+*X1M-$1RczB%OryNRRA#iV%qQpDh0!JHdlB<{
z6V|^8=DxLeJ*R?8_|g0yzx<2$k4yf7{rjgzm#r9U8=JiU!9~?eo?Jp-p7YQ0BaW(j
zPn_E}X~e+vZRx|0kEp!VKPzL7|2w=n>c&3)|D^U{?cwL&r2V0x2Vg7Ew=VVvj(VWv
zWTsH-j~qgIc}Rh6?255deozsk+O=5K2gRAaF~eO4EY=lKuN=MTR8OYilnBcDI*ABR1EkDy0elWs>}
zUw6^?2Ts{GMTo>cP?dVOvBw|Vjn>6&YR7olTOP?~1!VDcex*eDd0bi75bMi$P3Xz1
z|J8`xB_XEPpT}OCrjGgXKC29CV#ZUA$XF7|=(Kp8UHx$3i3TtlupDWC!({V1#~0sSmFg%^BH@k!}9+FZ2%2hnsPK
zA9x=2ejq(Oe95=|$NV2IHfQ1X+xuWG{O^LuzlSg0BUsE?a&GZB{}KPwzG{41H{>z@
zxBmB+j983QVQ-%lZ=?wAPgc%3K4kIJdDVHZd_H6`m-+y{^?U4yctT|=UK;o8eJ
zaCt9R{{gaV#IK@Vx28n9hChIJ&qd=otO##Me}Bg75gD?HF5<@j=_^`;A-CCrQDx>n
zKS_FHRAuoZ%^Anu&&M7-8+Krb>Pzq@WwkOKMvPT!3$(3^P3jBJ2(B!gThM<`FCMKv
z>GKXs>BSG@uw#EuG(S8$+B-ZYn*RkC?fu1`p8T!ZJ-xT4^yF{jdbU401#@$Gobkjn
zZ3frv+GS7j8ykCcYkzb%tT%|(MfB)5+_;qV?0CY7oqqK{8|~ZD@}&>W%qj#2`RP7v
z&o_cpoc9B4hxGq&cJb=x$ec^}<5=63CE@#gcA;Z+xJ-ntrRlx!^9b(3mEY{<(Vm9(
zV*etGQro69ZEj{MA;Z%fWmjS8DqIEYcid2xZ?zOA5lh)MwqQEEe8a*pvsMY}3&
z=?Pu{3Dne+FGKHhdNb_&`M&K@qHfA9BKthc=$`Y)jJ!aRcEa#TK#*tz)Z^c@-u(HI!2EdnzjXJJfYW^Q*C2KuenXO?C4;omS2B=`
z*Xl7Orh2|{5{)fi!g#h>J@>wYOm2YH@^0!EcG0*=`bW#BUW`SPVwjOHo|64y+u$^L
z9w0nHcC5GU@~JbckW>FQ*gPaQr%06a?$yljiQiI5pF|}`UL~31|ArFrSmKG4S?jXJj!t_&x>%3IwniZmb~A#
zSDP1MU*1iAI>I*UXv&1QCuEOTUwnqsBNwIg%24}CQ!N?@oEr6Qc6l$4I$C-RIleu%
z>tv@#rr?x%#{?ZQvJN>(SPy6TkMjc8%F!wM{zj$S@
z=RuF)G&*XoEzHO+hqa?eTQ4>BlZU7_)D)1W%2G?mp(Wb9d^YFA>T*r$ZrW6qNXaMm
zW^9T*cY*fw@9BTq^`rM)zYsjGyE=Q7k&MU(VE
zy}Q!SA=;JM)RziDubYXZixeMzZu0X}RfjlEZ7RYZHsplLqP$N&$u^ZMOG#JRmy?Bb
z)n7VpXW__WIxLFnqi5YPWTqq^-J3Bdx7WkT2bRCv2u9
z5E|@?w5R=}j*rHux88OvmIl?8arM+v)wnsVH%H^dX#kIr~Y^aOC}Z
z5W5D>j@s+dqFOpMvAIJQn>tFbsEvp$k?MqvJzCoLX1vn-m4vqVeQ96Kn`cBU%ExL3zL<|3RWCY
zTQfN&5OO1$0bIftv2odV?eMX!40KR=`S&Q_D`Fz~%nYxzjW}QLVyiV^i{sHxC*~CA
zz1dB>x~PMHADI5$eT*c=gT6x)_dn|GZos5;p+Di|>IsR_^qd>p%(k;Re#DWt7JJmi
zQo5Os%kcy90C0jPMGNHBP$Q)Ao72@vM==M^rJ8Wo*85$>v6-obB6cYbg-Omi_e|lpB$-U47*BbZeBxo2{@1sJ=*i
zTLeFg7SY(D1jI53*kjPtu1=aX
zX4e|3naX3A+nX632QeRlhbT>(8(|xH6n`Bfk7=0^cGW4}4J^9dm#*4Fcju+6iJ@Q1
zfj=N8Y0Ma{TYya)lbkHm{FqFWs{UCn#~Wigzwk8)kJ%Rnb^e
z-Tr<~-ltB_j_sUh)AsJ3mD@YziPK~B7T2cy*@W4oz8HjK`ZAiI>4gD3yO^Nra!gukU;>mH+d5O&kQd)HJfQjOS~sj7cXw
zBH~P*6Q=~Wb2l$D@u=xdZbb&!{(VyNF<*CM)kS3Hw6mRSMy*vBN!JJ}&(=MA)oA(f
zPi@=VrmFoyz4%Z!X4|_QbM&XrEWTU**HPa-v0VZ1`-0N0H9Db+OK^CmqEcHMx`b`aC1yp-(>T{A^%=aD?zJ
z`Pjr9+}lSU#Yqhlc;JiG_xU?5t_qi%$yJeCkEyQ}a=oVdM9QtNh$U`$u4uz47C2$H
ztUXV9;4_RrCKSmRAscVLmeG`wym!?8f*|-ttp&YhHQc=u
zcFqaR+`*T3ww}FhV1RIUV$SkzJM#!v&2JV;)z&xnpC?{(DDdzu>hZn1^}svsb44b9
zFm<}`fV;rkKG)3IGPRK$>0G$Ivz8UydFFSYja+=;Ggnr)cCU0cJfEleKsR>R?&QGV
zig)FIy}dHUwSH{xrn9-q3^WTO&MQ3drv&s?eg&E*?`oUcQ5u6p)
zKBp*l*U!T`Wx@lW|NNT)6aEyI2b;EcwFq5oBU;vlqi$+-^&x6WkTkKTgE-lnON~Rt
z7%TkG3#C5_k^pJbWd7f9bpm$#L^$Mm5w?jr$;U<=rP(gdOPP?i>*t;ioAAUgk_jt!
z(qG_q%g>b>Fk#8A&iN_Mn}RQ#p5nZNpV2qY@P9WKPs}0CMz!>4pf@v%&9yhO;eF^I
z?r)od+|k{!vaNe|4|a>$f}m?}dHJg=4V)y`9a+Fw-a)~Ryp8rt>(}k3ygLmow6ZlV
zfdcDKUqe1XpJ+JK5|ZNtE@h#HXYlc`+tYCJLbyJ%cMUIF{&#QM9(cfE*V}p7ZDoUe
z23AHYJqfu1tatrB>3r8|t$}adJt?EJF4AZkI%MhWtLjTQBeT@bxYXqbsn!KM1iK!{
zF*E&EwOAfO%c^Mg%-qG!w*K1>IO+9Y#=9UhC$&$uRVtNjqj;DR{xyJ=c;tq-n7aEv
zwBlkqOZD-KM{bOq8PMN)-x>XLr1Gab;QgoXSi<9kXrcu=iRAso!*jCl@KV?MBWzDda~u_9{wR8_
z2?s&*$P0WY|KTP!5LsipjSwP}a|kl(vIwTmnDh&*it<}Wss~z4+X3Z!SJ$-;_YNh<
z=I%3FbBfj50y6fG?)6a*jm2B)6bYx@c%VaI4KrYo+DGbT6gHm6YK9lj3yy7ple_7B
zv|WXMQIq1?wnDzFsYAmmXjCp%g6EP0!-C0vAJ81mA2uRsVL0a;;2@RWAnFrXfG~c!LF(Sm{g0%W`T3u#vdE>CU
z{HB$)JR*z5Z8Fx?nsmEh)RrI90^Ki0h{=VCqZbCY1)liyP@%V6#B3P>=^yAPXU&-u+ltYjyOj+^0On(-*R}R=bqs69wYJmWtt!A|NM`QDDe=@
z#BcPxdv6ZX^E^C%_!GheEzsDZ^4+4A9HRL%0^$MmrVPEw_nn(R75T~O>0+_0^J!jn
zTRi4=WqCV6fUw6%5Kq7N$$<2Sb*j&Z?bfac1u5E;hLkBfm+t#CC4Gk;j9^)?P#$XS
z@aa^e293$k8uwBig59hoR{S>l6M61^Sl!&j9z9oDLvYZ<35*}oof(UyU5LJ5jcnu+
z^P5QXo14VS(&G8kf7k^`2U;VsPAY1J<(}}>^*XeCqL1F<@t1Zb=j83y9H{G-?(CDj
z=9m_WI~DOH%7|=0e)sQ2`{z%wM!V;TE}R4h7uef**%t(?5h~lwF|XJHiwJTsGZ7e)
zzJv?reN`N2i=RK$SXBN!)!7!`)@md~ZvQ-}2@}kIynTcx_(h7_b`{dfqP$(Os|!PR
zdOEY!=oPsw4>3*_eI2$aELuGDtK#q&vchAC7Y|f@W;hRgXtmw2eZ-QBpN|ey6^~f9
zRD~&j`QNkG)0^v0d|$N12|`2T@Aj&W9#QY-W>4hOvXPIhAEz#i
zic*kyMM+u@-m%rK`)b@2J(>Y-6zY*Z@#I$%s=<+)LOrQQXmb3pbXW%>Xw`;#(zvuu
zqpR-M9%@V}EA0NRdaB&6z(yDKDMAZ4bM%Cb
zKLE)fIof2Y`Krt}x2Ua`@&Br8YU3rQ);>%3t@1ZbDMqE#YIN^WPrc3CjsC;u@)4t!
z7iP&)Qk#|>k9A~Q+_2NIAvhatpI^56WhC^t);&n$G-L0;QIW&5sj0iVxW-1%7?8fQ
z{p4<+$7l{+qtVdVjQHluh|}vTYpkoOYl(9Td95!6=?dFjI+E}i)srTT8`+QC*frv3qNHp_yL;8OG93&&;+*xoBjG_
zALCA-yGvU&q0UZs_ix>iM%S-C8t8j34gY_1y^d8WIB5=+D(eJBzoduCZ4t;(>i^~Y
zg~QScMhj#0rY$xlquiziGZ@w~@e(&$O7T9rY*m@Jd=pzW`oL&)q15f*SI%^GO*yPd
zO>Oc^4Q+C!#K|)S&Rg!oN*VTpc}>ffOBd-#PH9PxI09YUG~5-VeG+W
z^4w5|T7byzSwpeYw-o*uHLA)sf1WHgEofQBAE>~I267Y1#JtPonxX9Vy(jjbNcWb)
zBbctutHHOWOv{XCr^;wXg-m!^vraDiTktn;{ATr^cB4N$`osH7Z4M(01b+E`QNbA6
zTbv}|l#Hg1TBlyQ)>k{IeVVtbT8V|GX
zZtUr*F>iY&Kcp^funB2;><*l~+0fCjOcge>>EBQf^_q(Coi8ohW5gA=Yc-8Mtamro
zgY%|0c^sHq{>S~Wo)5^j-e?&+aQ+zXduT5;NX!2&zf>wYOMkGSllE-MhgnYiod{1E
z;&I^tlkNMb(z(z{z*qi2fJaQ){Fu?&%eNpl#lf=ACAhtw4CoOaWV1NA?BZ2*m4huW
zyN>ILZu#XC9fHTTSmG1i346We9?1BrD~WDor^t5Y&}o%gr4RcFe9V;-WE;)wxbjqi
z)28~ccHUy&m?a6W>~j0Y>=4RQ=6lz|8pQoeZ1pWcsT&&ruk~`o*ugGWmgu(XZ)^H|
zH}%2Fx0Vu}g#5w-_shbjZ<7!sE0(!p_J0fi$*-{r`F0@UtbH>Pfu4ov(z@MsS!vuVUsF1{abD?
z?NTzZ3-IMF&=(!oWO$tPxm%d*6`7nXvS%Tj<*~3-N(}X3S36IVT|&LH;L}D-oFD&-
z4o3NVsr}A2=$`ta%){PEwD0P_8Re^ymr(psU*MTdf&Q~VbHtTE2jb*hjPr23q#khC
zl0=MCgw1Yh9L8B}j#HDM1$t4Yk7PqeDp&z|Mq>(!EDJW&4yCCWmV@R94gEFydPA8c
z$-$J2_!LD#pVCq9ymI2|W;ytM+vKR*dG(RLJjUwoY{z)3w%ME$z+dwVi1mu56Eu6=
zI96&`7AtotmF3V-Ay;48jC#>e9$N5Hpa9R(K8xY{3i5W5QggTFY~1m
zVmP+A2^N4mhjDSn(^c27&jT2D<{IIU?7*A`@Z$l$Lh+WOcYzDJ4wu?k8kIzCy<8nB
zqb(%~Gix>-bx@A-`C83h(Gn<$qS1@^sgHxI|
z+2lBI`>7(Ri|6zT{14fp&k8|*C`ML%wB6pwbU#^n8#>flky9H1gFsaWJ=6V-ZoO%<
zO_q61ehA-JZnkMf5_V^2!nRR~ITxAws?HRCHgF00=`0>6V(GZA?x1#v7GM|T
z2~va}kWw@OI62k9X$kmY&k~JMX)3poeC-^k;%lbt{}|`y@HnwrGRL_YY!)37;-C^BW;xh
z1DYdq?7omq&y2^sVvgE_&@b^lts!dheIsZtPz@_Rz7GW5S}f+estOsQXZ&5Qu1H8C
z{Hw2qzEAjf!o)x2L^Ue{jw9BhS@#JXe*iQHFOTBD*nC2YS}53L(3SCz#_yH8N|_AJ
z47mP%PzcZa*<#pVY2MdeRWi_CA$TJ2P&+Mh3dXL#9OCt&AXBCZ$a~NX`U1`pOr~K@
zvHwiT2=O#Vr53+sH8wd4bNX5>hjXx*9ECZZeS)cTYdJZprh}fLUn%;_CwOJr3G+LB
zDY7xf^JblTO*3%G0l0)Pe!xBjIt`=~?v%XREE+rVnf!BQx{@dQ6ydZJf
zG~o5iz)#SW62*P%!7Vj+=uV7nDS6H>Yc^-BO>?=<|^uY(CWSvHIirg%9%`gtd!Fe
zW-(>UZ@qFP(QZvycI1AJrM1Ga7j`)O&6CZFWPcrt5Nm~Lj&6MvAw
zAM|N)d=l}8%LgK4;twyznfyVi1n&9E{&{=}yhHcJrpO_TBRm!vW6>L{Y~R-uTs9_qwl?`gh6ruA(-H==)l=U5f&J2Txn{
z{SD~bltBk}>bbL-_lN^@#ccXg;7ru%6t!;@JnoR^PoqAm6l>24w{lklQ*t-CE!pn?
zo~|>3j_~+v;Q@yav#3A_v`WdP~ZWM{vR{|y(706r=1PnwI2HFYWTwEEa
z#FhdUSWiIq=(E9lmsQzFhfv#ViLQXp#K%GNji7lRd>qg8+}aeS!@=t(kjJ1OvR35A
z^4dz^Bw(x0+zq-Tn#aAb0{2Ao75E-_9steb8MT#!ETf8g1#-WmLx1^-$=gWw$rX1_}ay$op@rGNLMBG;awpD0*Cg8lutrr1a8ReW(RRcLvO0x4y=t1qS
z5z)+bYc_KYUykzw2XL+-zv5hjQn)LF`m-**^fka1FxF0{Axp?zOu>F}Ih4-HeUlmX
z4KE=5RzBIl$+34~uX#BqpKe6|F<<@*ZsfjTTEa+E_f-2HOi?EvjZZ$PGuNS>})w*;xj%X@TZ6`6CDYq9@M&VR}ss@jYH07mC35
zoH{-v$~Y5Du^)FUm5>QV0j96Y1wSum`rSQ&SMlIg;78O~KWINleTDvm)BR+WRi{h8
zmmLYH6MYeDM=>@IeN80(-mh85_w)?+9nk4|DUPHRSnnfs!j;!WyV-}B+UJ!Tz&=WP
zHA!+qe?a|7@t|K1(;8nUnb6##YiCaq75AM2=z%0_c45H%uwq1pQ?rQ)c;@qC5^7nZ@+V3g9g2
z^EVDewm1s+y+10iMw;9a@A4NGz?RChxy|F8-c7a+TMp$q|JknzEF|&Op
z{kjt;^YEtvSm4wRU*njWUrvHwF_r8@l;@ROVP=I)}^sggU%o&`Fq?@;OkOwNbJ(n)YG
z`4z$0SbSk;CyxNmH~;Txbls0>G)s&zX>_d<{17x+AeuZ&c1AI^XYJi#+!(DD0_Oog
z1KIU~<2z(KXtAf=rg&$&^*qquY(Di=59W({H_PO<`-W%w;vWvF#N+0kL
z{qu+1VV>yjr0a0~7i7`i4jQ~ptB&JDvv$Sq1Fhowf1=fXS8t?M%@0~_tX`n50vxMA
z!=_AeMyfG_Lro9|$$2=%!N1GKR^mLV%T=mfOUIM0MHXbtcO
z9ps!JBomD+JU@`uBkEg(=S?P_6Cc)s-bXkrmAmCQ$b`orp9wZJZx$bMhhfsF7}c12zR!()2d>qdbG7264RK(%20?Fn
zBY0kM9Q6Nmlux>i)@Z~x)V?8%0ela-KH-hJU!<{dYENM}wV@`8{Y^RqjR(R1iT>$5
zc)&0VFV?jw5$JPHgIgath9kKr$LBEhLCK-y(|n@O!Lgi@(`fctjkJTun%$@
z7cuz_{D;^1ugSaX&TQ$#FYEsqKB@zKFl|8=-hr3bt$Vw(Zrrza-dp&!uBGdL;`?=H
z+Hb7Wlm&HPVGcnrCLGr_LLO|;e7Q{jb1e8TWC_-d`0i~Z(zzb>w-db896M}UpqDk^
z^-+jK4$BS5Cyw~Mv8uk^5S{IEW(H`4#+PL`qLM0Pv;Wws0^Eh)tdYh~IBDW1`ll6w
zR!#$dp+6D+8xbd(!IR)ohMlbmvUg<&GVX5kon9M@bz>6nA3A((GjNOM+=2SQyGZVk
zOe-p9^2^N&AbU|3_q|)NZji8!8wxuN%8@O~F0mK-$5S*ohiGul3tbqo;2dJX8Dhc7
z9%`etrmdY5<#zla2#LdL%^tUr@aq#;)t^cM6{`^y)|y4b+sgeS5WE>IoK4w-cDH;_;2Kjv}3
zSLBDgii~x4F}Yg;vYldl&=Ub$hhFmmQX`-bhe{5W*&)w}hxOas1*aon
zI7t?ql$d&~zmX;GDe$qPYv3h-lduJFTGt>WA{8h5ZLna~@0!Vr3Kp9D5Gv0*O9!`2OYAy|QyevmP5Ce4wYvUo?`^=HJN&Hi4ZZ&3bwb=HfVTDWM0dcI|Z
zw(=?`hah_jTafkdCS={LVsdN_GNA>KXXza#&k#7}o4@l~U#wA2M78*|Rmr6|8HwU|m~-djqztEqGqzR!-OOauIUMWq@XyaLx$i
ziQ+xNoA%tyCfJTLvF^n8&UV<+@crCO+8U7BN4a`y6y_gS0Hdy&gkf=%oNoMCdAS6}qv+KUUqMy0`?r+Ke*=nJPY
z{pA;|x|`-<4c5%m*%{co;Dm0SVOKB53D%kn>oSZ1c6PjLfsMHe?_n1?S8P*fWk9~4
zgDoQt`ZKNHtg>>>1@yZKb;4I6Wk62Hp|2q~@nzLs)k}X6C3(X&u)UPw%mlfzO*lw1Y4vW)!sp{)tk#X
z(;m9uE5P|1*hFeMb#^9rXeKg3ffr^uATO)HvtjdnY71axz8j_1!6pLRuT~h#^c}@a
z@olo^o%m-A%H+gyT1`CkuIAsW)3+wbm>aA&v7YYFwDZ^}B3{5fG5sB}tJ0^<}n8R-96V@(LB);p9`a(91)+A!+
zc1?u+I40B#JrdvJ8&-0w?2n*t+qCnbi|}*eL3k%5k#37}GU~VJtKU`Vj<9V9=$j@Z
z5$nnL7n%Bq>4$^g41T&7&tq&3HzLeH%Ry0w+|lBXgNAD0Gr1Grf*;0~GO~+kaUReM
z?&BKa%Lu_<4Y>oo!jv^RcJ{*h7?L$M$Qm1DjSaHK23f;F)^ON	`kNhkZv3`;Hj)
z9g+OuN&aYnr5e#<$=xW#&yn0EzZLqVou6#B0bbE$#EGN_VQi*ufCzXI>#cQ&!hl{|
zD2SHsi|E{Z(cU#b>;moqPx}S%DZEQ`+D!ddz#REuGlc#td*U(YfDtR<%rbodGw495
zyPf{0cI1ozN9E*s_`%Pj2s_;7I^yu=D9Ce8-Md+o$;Ms*{t^d0u?RR>4f>-jP&JKA
znevXQo2#%x&^(*C<2Wgra~*ZkuEsdgf8Y-FYiY4v^8Shq`OA|uL%Io66P#CmdNn@MYLeiOE|2VGG)ezpFT(XA@c2-aH*St
z6WIGhH-hgg1f2uE1nmUud1S}q>lP@@LBwzh%+#?e8sHDX*qfn~R5o&IAMkkfUGNCr
zuD(?(Lf-%$!RBC;15bDx&9fQMFGI>tf1(HqBM(j<)|@dUCSqrIh34(bo|iw?luuEvG%9BmXvwX3}x4yEc{Mkl>v
zzO6n)iFP$nz*-&SdQjrkg@PUNJNOp5F0N`0U!2$>e4Dzxn^WvGyk%`~US=
zyL4&Nm;aS6O?viEbZL2!rAupn0Y0oQW!lxN3$&95p?gA?&hKXF(z#cWeWL>J?}5IQ
z#F@JEg%)ICzl&*$Zu*HX{T}3?)KkrJLYH*Wa6f9lZQDy1UG0>&Y2SC@POV@*E#Fm))H1VLYF0J@JF!gEd
zU_gHSr(wSZZa-Za7w-pu5&bt=`g9qy^yxC-Fz}glY4nwJXiJ}-@%{B@)K}mWG9LVs
zK7F*`5C408dWNM>ADwaW|E5o``x$+D#?R=}{lfb6y6?Mm0OB`TD-sWtWA>Z!8+LJI
z2gZFuGp9Ut9(I4&6G(mw60Ljx&+?mmty+&O9dbs5(c$a9tFKn
zsD$qqIGD=K7DU##Sms5wk~P~?=kjnKiHIPEdWum$y;9EWFOBm9xA_`Zo(@+ZQ#
z)QUBvz$p<=Lso})buLAF!#72G@Iw*6d))H|^cC>U<4)w%zrgf{DrDpRj_LewdAUyn
zzTFAEdo-s==XqtB-=_OV^182@X_e%shA*$ankhXxu%-~XB&rXado<`swk=P_l}
zMDzi&$L;|PPBVQZeo^P4e%sN<
z1(??YlQy*Yx1eK`o3dYi>@~>la!y;f4sE`O=g^raL0=8UGp#8ewkW_WzTVRBCdYuk
zL$95-wWq1qIwa6we@i!E7jO@~NyJIViB7RguN7gJ4tRc|*JcTFF6pvP$a-8mby*g=
z#nf-?bcHV42fA!{eFzydSax&+twEP{kR4`SlbYZN>#8$ajYP-K>#Dx6t~wF&@J3yA
zvZbp+wtTH&4F9b@nFC$C?#vM*&hZm{((!-SCrRh`m;DQU665-jK8dm2pidHPNUxL0
zEWZg0>h|7_`#
z$1Qylb7VwF#il+f;(A@5EdJl?lW4nBpG3Q1eez>VpQL%5(bkD;)_UR0M?d9_z_|}0
zoBy@n7_Ku&1bR4N1Yi>lo-~@SEUWmmj$a@)$l4f;(fs
z(6Aeu{K%$%QEG?3R_4ftY3l8)#0i{PpvINk^~}DUkuSv&Pk;{@F?MDhu5wKLTMNNhW-sA**kJ
zvanATeGAyZGXqRLA*RX__z$%o6&lfL_td7zu>FUa{DKS{0M?YoY}h+9!Q0|UryDH8
zZw$TC@*9f`Hqc_obq4=urCTXPd+@nhzE^yM_rT9)#Q^_=KNk0}ZAiToX_Z?out(^#
z`f}uxGW*ao^lNIz@H<5ED|Grf;9rOV-dvRJfOTIx>?K$WkiVYb9movZ&--1VIt&(~
z_$|m^-Y}!pK4g1qkjg?lQIW!Dt42PHDQfv`JOVqhn@sD-ROIYMVqr@
zyZq}G9iM4Zp6ZKdStgw1Kn(oEH4ETZk2K-*mfenZ>TnZR;Y)*m$Ap1$r_3o!16Us}
zW$G~r(Z^vw@x1mf7!p33zW2ApNHr2!q8ec%$rZ<&>qeF}UM3t^v)_g_`tO5wH`8By
zi)q`@enBee;(*O;QbRNJU(OMlx;{Y!2i<28@AsqA5SHkB|JvrViEV
zzaV>reG+gjEF<$z&Nk&+*2&pwp>uYp|5(i`o2~iB!p{IZoatvU{aLfR+FOhE`Z^!c
zi2s>7+9bmFQD(aiG0N`B-p4pXqE&Q99>R&@Nxj~u~cPJnmJ{cDpB@{jMlk#7J$O<(f=j&5iC
zm~L%Sj7hg^?4m+++Y|O?;EkLI--^9_KYZ&G<)y$4iq~LSF($pjhfMx;%eP*hV*1xn
z-tu|%``*O6MDRzVt)-51xs&dx4CcT{7mtGm|74cyg|lm@To%f8(%@(*-K0U3N4fGO
zlLn8NG-$$mbb!_`oSGUSTY%|LR(`|>%74rUsINHzx9PW+>fN1ufX0aWYl)`KdF!HS
z={$#|onK-D|9N>_f
zW0V$Z#+e6w5!(pAQxRf2VDBXQLPiYOi24I|7jBh_W)@!4RAH4l*JMcm5MU>GiH%g}sO7@Sk{z{oQuJ!lp)wx0w7t
zj0YwUsOz`g;wdw(VGrV;Wvm&ye0e0_JAHYbGA%N6OQ%dT?K6cT)0d~$#&JX=q^H1_
z{oniY$XzuD4RnQ}mM>3`Zd{-Jx4t~`YlHW>mEy6SV&CuX@^_nlaDprO!GUiW
zZ4z*bo#q%!2ihKUE@|_;7bepyA}C6rj9RiC{mG|_QPUa@V_@^P>GhIn;YK4484_Gd#L5br>}Z&`et?q?u3oq27u
zaGq?{{Z`ZWsK@k`TR45@FP(LUaon;In)KhVkm~5fJ8BpBNU`E4OrBTQufTk7)_JB`
zO@JKp=c4|8tBph_?Bb4G^r?c%s5!8A6TRY`oGyPh`fb|yK+ndi7So?ic6QUBT{q*n
zVOxc>EX^?-G2Rk$tu|*IF(Oxm@6TNBwBKo!(1HE1xi&UJ_dWYtWo|LkU}r_FAyZdC
zpUB({9)b0z&)N?lOGi`GNg+G!zcKgo1mM5Q5h4(q1v!S;j<-ZXMtr+AbqdxymC%_*
zyBxm*`+s03g)ahflGkZHBHliR;w%6gP90m09A1^Xl=up3@5hu<3;$}iP~Fg7>fHFg
znS9}ZVUrB|IoiV7R)mgPS)vqy)-tz%zuul=#?}$;hC(!#(4T4EP5i+8m_E*{GH(V^!s%Y_Exl?D2Qa+Ro@aIhtH;{?n(#soz@Fo{ZIY*{+r)N
zN_Ofu)j=}V>NoV@pY+>|OGLjF_#ZI$psgGFZQh&sa~1p&evKI&R3Fwp9q{Wj`0ug*
zX*u|}09#^1in4zT^rw2aHW~JE@+Ftd*n_!E(WLd@*IV4`p)Gbz+6tX`3)YTPOgo_x
z^A7C9(D$)6Fm3OhyeziCTpKBv3;2crV>^R?h`~RE@km{JvQSTl9&gnlo4B{`Dvg!k
z54`R$`%3+!y=RCuKh^fKde54=b!p;
z=IT%3g;)sg8%a3(0`Nhun8%sB3hl8>E+}GJ{rMj95NK=0wX
zkviw*JaG8+yTd;IW(_u9JsxWhYmBB11aSj6#iRf+R^XN3HPqiEtV^iBgsUWH0fTy)
z55g_XN&S^uFzzDw1HSe?F$|RnudL^
z3FE^vQ%+-V67(QT-ea5^bO)^Kd&mhdW1cXtD+!+^{DQzi*ysDlv4?z8ok`vMJbSKyX#X
z&F~|+4k<-w7q&ptKbc8!W6;}UXPSO3t#BmP;33!>!B1$*DH+hwd3upcgf@zb+2m+5LO3_rtrl>33|4u5+NyxfEp+CGPGPh*cY%Je&9_=VHN
z=LiSX90&L&;I{^IyA(c&FrJYNlnGx})wZL2yF6TE8@zOo&#ttLT7!T&2Hksm4`YbbbBVv}7K%Mc@<1|E~fjPqrn
zHN+o8iZ;qf;4MQLig65J&ZSuRdaG#OILg>a?=(Coy;1YU0`6PdiS7u`s1A(rnj(bU
z^uJ!d$!uSDl$!0E{c10_Yx59KC83Q~k|;MG04&6I^_eDz`YOpAf&qDsnc|OcOlK!VPAvP5BMK*Tb*MNAGcyo^~)oHvM+d=!-O}h^IM;V)p+3}`ap}w2X
z=Oy8JsNL*;mel;S&(}!gA8hn)20S*T;e=M~-T$bRc|XLSx)0Mhexr}$-!0_;Kg6De
z;L9oPa1G3W%xZ$atOhY?AQe
z>_Y}Dz`r=+kxFAJ3+85Jk*@)Ja~*n9Jg2S!?-kO_dX#kVG?do`@EUw??ja6;XZj~l
z9=6GAX1}n0R|~11S&)y2l|ldLxv@s-!gGwp8q+GWH)KiX`y6^79?L4Jo%)|7c3{2G
zcuAMaS6K_#^NZ+Xh~~Vjk5tCgJMo_08K}>!HSgC=%KzYm~o&K3rG7EyPg+Vet+n5Jv8KZqUQt?J{@B&1K!X)_~3Jm
zsbmzJqX?Ded%_2k-z8R>dMJH^OyGFtV@9tVpOxZSDeP>OIH}QsH*_TQS>TMmm1e8}
zecQ=j!CR3N16gDIfW5!5NuLL~8Nd(vi5agVB4**Oa_HIU8^!I4kTt=$5FVrsh
z^3^WByH>Jy_Em%4O>&waQjUG~mEnGuoBcL&g6-aPJeRh(`Sef+pN7mLS%}Su5N#A^
zLNP$HP-XH~BUfxSGb&4v8FP~$yO0eE-^oIgrPKRD;cK~hMIBg!0e2yvKnD&}He4$g
zy+bjME#Mb#)nI>98S;vW5lKAgh`(}431F`t=$tZX>EM}Nv|a%JVASozTW}%;a9}fF
zDrGWxEa_07d*TOiWN$=$6kCGvcj3b9BiDFO7;i+#z%|umd$EyS$&`I!DeA@g&(?_j
zbMX{ohq;RdtSwn+*h9cCOWt+j%8m6Ii>tx!`?c#eo2;>}AwA@Fi}%--iz*XEbB{LK
zrh1X36}lqYap1IB5%VBoy=Tha2FSd4b6%0h)a-+j+vqk5%1xd?c_)+r_Kf2g3#**e
zPA93DI4;rruWKPV{=fFV1w5|eO0&8p*|M=Mfi;9TWw1atvS>Z9g$K#fRZEtzUY1(6
zjG{EH?%Pu1esTM@9ti=3N8+#y1`L6auyF_p#_)j?k_=ylC5B~)hcFD;B?+5l@;QMo
zOMn4FJP9NowEwB9d;4~)WsAuylkBH!S6AIrr%s(ZRdwoh>Wbt?vLxA&%!I5y7iKFD
zk-fK+73%JHV(tcc(U>LrO!Rpg5C4_uVeKmQAMC6iU4%L$`s|>P3FIc);463k^aIO2
z=g}L`4wS9V9-6<9{hCgqZZ;h(
z!gf=uwGBbon7{N1=$ZdrtN3@Zq(
z!1pvtFkf4=m&*Hl(0)G{#u+}o!1T(~KgHY=C+;0lM6M?p~bP-{6Mb+oGd;(6=azF<0?WigtA_<@fd;x9Ib~9>zN25tFxccJPUa
zImY#IJ#KQZ5rMxPRxpgMoA)E}FR-2#BVtB^fhcdCL=J66BE~xtiKG>M!37e3?Ytj}
zuO$*@BtFX1$*QU$p*U{gyZX0h&7&>p$17_OLH&VH^bR-($+jJupNyImD
z*44Jz@y1w9)rRT}o;P6XK*H0ekMQbhUgN2$RWy8&n2M{e*?7^0jWr_OP*49b?>7U6
zC`}-d@<$;Zf6_<O^N2(DK$5?h6;wXa|3yn
z*|d84d4F(B52d5Jkw>oDz-At%8YDgqJrLsIguxBnly%aj#}dXAZ;nP2K?s7k1tL*B
zRK;7;hC%Hqs)tRUihNS%krXcv@sTN0Pa&xb|LFN(W@g56^zL>o#%>FgJ;MfsdY~@E
zbKqZ?=AxFlKJH@euesPe9d35nh5#!3Wf-xiPkHk$6@(+ybfFvgj
zo(P9iy2**nR60fM$TIX#rMQtYc_a=HF^4BL>etbD{Xvw$!fQ1GDU>i880F=j`pL@j
zkob=vW1`?l%KOv7pq>&`lA#ob40MC?r!WW-b)(FsUHbpP-42@HRdf$K=&yBzbMtlo
zRW>iH)q9)r`;Zo9?%IuTx4?Y??#poZ!tH~581CC}--9~{_YB-~aOIvFNQJSHD1?np
z3l9}T4V39nq*h
zie4HV3&i7klmsE*#G8W2RBeWSC542jSOViS+A#yIFgnYHPc(J@gL2P~SHkY!gep@hZ*(X`Sj
zB2wrbZYH>>DsD{5=2n4MGo3=#Ya|V!cJ1ht?5yE*G&&{YiB5(L@4N;7%?Yl$1|yA68x1+09u`o41Siw|4QiNE8~Ldyq62R-Ff?8#Efgz)_AJA(D+4
ztwZ`qni@i7I5J6%2jg}28*wNb3hCC3bNvu)#8V~$h3Hc~$tFZ9k!4yOg=Gab`}$jm
zmu4Sh-EA#?Z%2Q#*4Zk;t=%Fh!rS{ge67HXhl6|q(>$FALLn4?vfNWQSsB%72&KG<
zMqg{QmuM2MXn^@qSxX>^`UvSYN<;L~EF-3eA^~oRi}jMuQ6o4_(ohW67vg$YWL-bm
zKpfPIVzaL17BP=Qd=`~HGtNVLIFOFY$xAah$52hf5mg@xqQe_-C-0_GxHH;Z96fWkGX__pcne_Gdckt$MOcO$t+}q#ZPddCu&OR(K
zHI`XmnO{GqEF4Nx3WfJ<0a(Cf9ja-J086+YPD4>-@Z@_Ks!R|RX(1F*Ra9V^lu3~>
zW6PI{9_mYs(zF8NKs==t
z2k?<6am>4kQ!6}ZekEvmN)TGfS3r9jLY4sw}gJNV@zLd8b
zM#5OtjWR`I$*3Nq=`HEHRisxW?`dk5%+6+Gxfr!2N%@kMmyIa0v-!#7J&RS8-R2{%
zue->@X&@JZ&chUV$&r;<*~;*;c0-K8VfvMA
zy^?gOttk)>{b6?#CfhwmT)W|0ZQWCcRQ0mm*ICV;^o-Pgssz?Mbum!@;tRT%!xv*Z
zH91mg2{{HxMjDtR7z1!n
z6;ucw3pMm(XL-D;K8gUidFzeUVgt6#lOkxwH=W-#F2wjlrLUpMw8#sY?sM-w(f8
z`8(jhyV9jiDSsRMO2pG*_|C7qs;eP^nXcuBlF{;)SVKJo;
zK^6(iIILeoBQXiXq#ip5=|oyak!}<;ubYk66L9A!lV?UZO{(F
z<^j12L4Xk?p>{SZbV(TMLE=fpPc6T}YI^8rYA~qFz|I8`p_MT?HX|u)|Hx&BP&81%
zQWHWKh%to*215_(*lU88#pZ%JrgNy~v|dGYXhIjB7{)Tp8mg#_ygbOUSPEgEBAZDS
zM?`JLi3H7|IPG~T1?R)Njx`_c^H^&UZz6+6av=2{0t^DPakA4vSBvG0B)YwgQ@8K%
zcDC|15V+(-T;xVw(~}!M1+Y>Dx57;h{M@h;#|nEL__<*xjumcq;OB;&I99mRfu9?8
z;#lEc2YznYiDQL*4*cA(6UPbFL&VQhMhQ8xVmd3NxG#*
z`4?4PBtq3H;)qNBd#&Ku|8({&t8{NK9CMxFe!*Q|xVI=-+;qaeWz()1_cetd6#ZNA
z(G#v({>K%_iiO4Vt4*SRk&-}f;%I9FYF_G_#3C|gZ7p&{!e`oJftDwbKBJNmaR62xj8s=p-ZMdXMJ$*mT1Hmrl|Q
zyV=)C>XUp@o2=JJgwjECi%vThm??Sn@kmhb#@yNY-mhaVXiA8k#s*R!#SYOX{51XJ
zbDd4}CLa&M@RTb5okscIq~5vm*{0sVxifxJ!P!l%u_WeBq!wjY@5X}N24z%HRKg^ZA%3a)D$3sr?9*v0fGM?(IjY4C;y
zjy-;g%%s4+CUVgofTk^-Z2J1M*fhRt(6qb&YxYN}odEx_N_tZ~&$)mKfdVdh=s6P^#91E>$
zq-hFxHB2h_d6)xvs@F&XL@^eTkQ_y(Wa4?+<)Uc@+jg_`C6uv;ZxR!_oLZCT2W(2pbS@q)A1my
zNTXNR*7(geF+C>QRwK{A;#l=zerxFCehNASZ6=_2#NK~ngE#|7gs~51Km~AYwkCo*
z{a66$YnT|c9qD4JQTq+sVW?^!nm*e9Am(--FVG&kwm^IC%>oUkh@!}kZ&R%s>RpQ)!OIxwstn}kmaWRSDIT7we)n;
z3Xmp8qzi{IS=80bP&5*!FwNWqUSDeqMOD&&Ih|uen5_)+p?+VpZvdxIL*9X|UfM$B
zcrdT4(>(Rn_4RbV5gio2*bGNl{YvfY#J%`9xL}!=VCtMGWmLq=>kux%QjLm&t&s4E(QP7!o+l?Y^GEyZ0`uZ!9V-yAX7~QhRE9
z$%|(e)_6;czp|2Xz`&!czS_-7HSY_>jI&@TB-1n6-Dhky?bLj3ATb=p70*H(qIR!OnXZahq@_XYtVjW*yRW_87@IxEPnep
zD?T;N=)8b`8n{JG?s}5*G-xhvlJ$EX;1q_uYCfyNR4<=LxCC&wi*33|g>OBF^W7@!
zTF1P%Sz*R*!spNm-|j1{Uv+Nj*>{2dHJ6oE+%0_ODZy0Z9>iZWggR&V<0mpa{dJUS
zpSLs#7kv=ry2cMaP_Bn5p28@X9Y(n*JTp{7ZLjW|L>u&gv+CQD-r>i+FHC(OG@tU8
zntuIXiGnhNUiN$-aDfv@Vg7I>nL3kwSyW(3W$3Ri1sG1V{eQiwdWcxe*-AXEaLt+Fr2
z!EZ@{8*S>yiqg-p^(8C8yNlJVB>2j=E~B!a=3-ZU4En)JL-Hy)v9jY#7rRNoOQCam
z3vb`enCFCld40t>F0{?*0#TpkNLMuNt~ek5Za3pFnJ*;&0^yfctRwhIGEWq?aJR~{
zPUX3KW#tZ%AC!&A3%DXLz!shb2`os!A%TLwDL!buzHriY%`%*9lK$aMSN+hXEqgB8
z-JA!uHxKMvd0+k)>
z;cpy%C>Q$Y`~Jo^YVM!9|KR<_`+D|$Vc$RRTm8V!2fp>d`wukj|J?q6+JEwc!w=r~
z;2RItJT&zeRHi>)X=iix`CY|jC!Tm>+1+0}wd|a8&MA9v|Jt(J+S;lA{#Kc4yhW)b7@7jg5w<7Hqk@jAs-H)`7mQ^8(&K_*{
zV6%o!!mwdP8%x!m3oZ~RD!N*45GQYLeeA3o-uU$<+Ef+09I4
zE!MdU?c?Im5l3|(h|`bbB$I2B845h2rKnQDpgh~;@AMOG@Ac%+35H=#jL+>K!coz|lcQ*kX?-V>tFg%o=p2Old
z^X|kKQAh;+BQ_-Iy{8+lt&O#I5A^!Cdc~M7!rk6Zim#~1?54qzB$-a)kSh`o>DcDH
zgx6zlj$iFSQD?XtJf1ablM^&ryS?2R+6d1x{>ZlPc7
z+jodp*6eNRZ}v%8UvpRQK(7o-xZl^_hsBz};RutCkBU*jitp>#ycxS(S$IZdbQGr%
zK3J9E7#`*)b}EaOzrCl^D-tQ%?Sz&ufy$@7V{>~JK5Pv0;&*gw-rk<={R7x|$%N(D
zRG};g6}+Px2iuu&UYus{rLt@a5ARA0A#RbgXb`S5U-eFOr9E7RhToYt;o&`lhca75
zAlb`sHhT&#$YjEKaln$_tI-*`q=humH(}&e8Ma
zW5tMkJXdd!dDM9>UZ2S$G}=&GGmo68KUY_)^YuJ=Suy`HdEtl#=3M0|SmQHT=%j_E
z5iB`^V=!Mc^`I$E;}}DHz{H+1ws>SXv^pVCk^cRo0D<_d(Px-^kkA}>AGZKDw=?)-<*jlcSmAp-ehZb
zEbZ9lP++JPvaMjUXa=H;?B+@Xlz~QAh5y8yAQaPMwtf~+v9ey%Arn^4p
z@%H9Ue{+k+FONjD4&NH$Z!Wy*dE(W~3r}n5o);b!FdK1I#i$-9QDq9!J&3axf8U_r
z+tuuE?dtXI@XOL13%9MKt;gT94Z~zxXU}$-U{3sA92EEU_4FN&F4%xPB_m!K>COWm
za{W;Fkne}Wul+FiqFQE=N1K>K<|Oyt_8lE<{(){UMA8Jt72q$oz
zC{wEHJd|iKA%-k=vgjZw-M^bvuKaX79S#V?fx!vRhW)-C|CZJr6|lYNYwhaswF)2(;Bn~$mK8XWmv$mh;QpQZ6rFM7
zx*ZlQ%2p)1ju4w1n~KA(7$ben`q|TrYSBy_HG}lxaD5wgfbuSWV190kpN4~DKUlb(
z_OC9@4ga+xE)Cax*%;mz!EcAZ1pYz5m%-l$Us)!Sg}8lFNZl8yr29pD{Y
z6*qn863!gRS-9$E(Hy8u+}TjHU~F!}u-=h#C6A9_CoQ;BH~mI%T&$8Z8*VSd9wK>q
zp;nHC>FKQ9^+(oTOs>dP?vI8GA6NEtnOSCSOEH
z;n@K7-r+@@xZnYQBc{PZDDj184nd(y*0m=@F2xV#SgjqwD{
zj4{zRafu@lC#zFMD+9#lCd|bnArUDrlEea|xb!z0j@c!y5;!9yerhaGbJ2Qf@-6d7
z(j8L286EelTX!6@b_W7&exgTlvLB%o7M8UT%%tBro|BY0(+UFBXr^RjUKbU+oD`1|
z;oclkugQwsvW=QFq$8J`pe5JoZe*s7ba?Z`<*9#|0b_|JOz~v_B*0q1!Z>Ai
zn~?^OjxZ0DJU4$AlB&C`j6utN&BTKKnH
zfm_o)aJ$8;Z|1y3arOZK8uUX7mnLA~Z$*VjqES{OC;ZJUHi7w)ZGjXnW)
z1kQa8#&Ni_;40xZ!nMO~gA2hKaMN%%tM_M-W~ifY>o9MjTa&a@r#p4tNQ$f{af=B@
zcevAGt$u+izb(-^8PtQ;APT_
zE9LgZc+O$Exsi9orGY7BK)QmiV#UA{U8)jClKJq2$uUkXt$U#sj=G^A$Y|b
z69YTN7yz(>b<%!T-i#sdES#K7Rb0P`kC9y1+||RSA#^tL85*TCE+cN)46L)Ruv)z2$LpVkhx-M(F|H1EkC{i;thCNLNn$tHmb6nISrPflnS-Fx
zT6|$+R7e2d*ih{Yb<%<_D~LG@-5J7uvuI(M4@Gf%n!d{r2wg#!?&zNWByKI>D-0EO
zERAeK{bWDeCa*sP!gS4>roX(RdV?7F+H`Eh;zoW5qK&6xBZ$YiB$}{jC^EgTuX{6%
zfOKz3fY~vUum<_iS4L7}Ex5!arkvE)ImW$8EG-Zc7YAXVtB{Fm3`6*mC5RZ5d0=(#
zr8PRwhT#(fx?wtiDQqX>doDDBE-6oM(bVTza9rJxot&u4T#3`j6G1`~iZrrm0u
zUL6w~R&&nN)#O;to%77eFdLgQ4)ar*d(9aig2g(qf|V=2Qlu~~`S+SWQe^&?L_8cB
zCD~_$Evlr&u82X{|1xe()TwUj1c=ecUyP|1aVcEjkWA6?L>PB9ar7W+lB$gC$HlZ9
zEtzh`p#S4`x!xg80XZHqW#iU0ogvR~CR~khr&xgquoWgSN0vhFL%4{Fbq_=Htf9M_
zL{dEEX{G}8bgzl?aVxli*ze3R-kK_5%{P%Ed
zgpq$B*4S7st!p-N>{D2&{@N9x28{5z*m%bgrtpr*4{seW0
zoHAKy5NW5v*&r3y5rvB(6UR(T2#)mGGO$vKJsD=FHrf9!7!KL|<*l{9IRvXLU%x>p`ybaFO13s?7jW9OX=<6w@
zmE^t7>@rZCoJLvSL$c#3eXIDEO8)fFohkx*D-x4hs-3dCE^KDEaLdU`hH}{82n&=+hnaxhFAHY4~u5`uLTde?Ghs
z*(YuCY9Pp}Gi*`W8Iyzra!y|++Om#pRKlQ21Hh(wOkUdN$uoTz29Hh4&Np`ybKua5
z;X~HptbQQuVJy8SOi@uXajno<-Hgf$b(Y~z0W7sDUq^G}N3-MOx$$u;-Y&OP6|=|T
zx%sq;#O}KAM(tMbhAaQ+j|ac=_5b~yUk^RC?c(2@_?sQ~UAyVFAAjPE2k+Xy_$AlS
zbtgS>L-p$a{^?}{=I|572jBep^!Pl^$$;d=7vh+wy(bS{d>2BPurLLFI%4a
z+Scd~PJQjRAFW>W#h=`8(TXF!xl0{kf;Hy6*QodN9PpD7HvitOUHuWd
zD^y;M%D*g6-cFuQ%M(xh{tmn!eHQ0fKm6$2dn!Ms@;s6!eyTT!7v-GG
ztvE(pZkl)h!L2<6NATMmbS;<@KMI^~IPIBC-lwTFBaS==5xy4iFTpTH$x^?yalt~$v*^l0B)bcC)m9ze4_(qAWS-)vDHmx&Gym%qo|6XUKQ=KlFE__#J5yJ26XEUq>Uo|WMqJ!sCK2e~F_a^4%1i!pcV|!T>`zoB}
zJMb5R3ldn6z=8x8B(NZX1qm!jU_k;45?GMHf&>;Mupog22`ot9|3?XU@X>u|x&AMS
CB++O9

literal 0
HcmV?d00001

diff --git a/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_v2.71.bin b/bsp/bouffalo_lab/bl60x/board/builtin_imgs/mfg_bl602_gu_33c89c10b_40m_v2.71.bin
new file mode 100755
index 0000000000000000000000000000000000000000..36bcc07cd5ad4214a828823b88520e69db4d02b8
GIT binary patch
literal 192528
zcmeFa3sh7`wl`jn?RQUGLhpYuBz_d+(}FNE(yMF~*WcCfR}*$Iai;u6>KW#dPhAs}3K3S+5zyI&q!2
zC%KQ=Z@Ir~{;tuaG7bfqhSPBW$?-!NMcA*~+uN6FH5Pmt`f(+?5*^R}nib6cFehqq
zD%#fR7^g+K8{K1`WU-7HYc=Q<|BQ_7-s0DNjOop}-0lH?ENLGdHT9e4^P~Qj)zqfz
z^Zb~uW8YE>GWOx3l{3-JgMSY&@Bjl3Fz^5a4>0fm0}n9p00R#&@Bjl3Fz^5a4>0fm
z1OGz|6meWnS2lMhG)>o2-C@kAEHujf5~t7;3~iJJWNkBcNN%Fg?hT6TWwFO`)UGkD95@s@k`m&%2rE%ZOG
z$f`q|*XP=o?AMsWdGzUdaerIrJnFHksYs$+>vH?j{p?=umN~B!Yhqq8v6$Fbo@I8O
zmc3$(VMS0P#0TjsIcv7HsDbsY&no^sSL}9b6SNn0$GAd=usucQow|fog2+o1aT`};
zsagk}PxG4Ua@#EwF7Y^;gkRD**0R|pm-~k36VBi4;{vRU+cS3DvbO%nVp+!u=XDyN{O}B$JEp+q`qwDf#bSa
znZe?#O@Zre_P;tc?mpTCf1S(eOo}V?v&iMfG_*Ind@%JYmjuN{ChoIr0IZ8*YHj9u
zb2K8)7vCt04~neRABoQ4lDZ#TYelQ!v!9HVs4Pk{W4ffIg+FmGt>z`FBUw?$s>f^;
zEJi=9V5r0THuD?ht68u}Z8_>tO1Z<i?*9s3&`)oFqpPjC?4rZdYxm{e`94NE$
z42Nwnvlj|oG9%?I`MODa;+_x1=VBzYcfM`BW?h6waXl~S6OP}yMNENMoAc*?iH45oUXv6^zaA4
zpCGXp(f0&a;rTLL&PpGJ@fFMt@X^JFL`^c$2F4p+oC?e)cXzw510spj`
z?9O^WgUy~_uMe=li{|!z&f02AW(nwUDhx
zt|c0CF@v|ZKG~y8#gi_w?w~gmaeKcvWIF2$^?LE3*~To6J~mUXAURCYEsq5Sorm_rL1umyx1E&zOGxz92uyUgw14FMww=PnW!y!~vUQ|bWad0mg&$o4h}x-H#90w8ts&+Un+ZN!XEJ-{yI}s%=G9PFl}9
zc2%_p39X@~0hii5TdI*8A5^+vKT9bmD54InT^*g5cVfl}>MKR^^|mj^uwp>Yyb-RJ
z!R*a7&7YR?g)COTg}q;-t>zi8m-rol-=MeVw)^XG$D;`%z~XN6yh*(gEQaIJ&elmm
zf@y%etu@rM^^yXG{s?iIuxX8NgndpJ?D*d;Fw5qVn89{e?#;l(`I`?*N#;=SB#go|
zKxpe&mcpCIroFNG%;vG;f~9QpnZDMHAY~)KhVa#w3e2ye<4l&
zr?h&(sHQoRc;@DrMRfArU6&@YRl-L_1tX0I+m7gOigvBoG#^v&{f91K>#V)BiF!r?%*miyCH+nAkaKT~Dx*|*M
z#h!h@uVP;5yi#W0+?A_X+!|84xRg;p+EGK8TVK=O+O>JDUGURMN%oM-NC{^b);f}`
z%7Z-`!t`E9yK_vXvI?X0Ayg%vIgeF6#BhZ}V5_!w&D;RFJ^u
zb-z)u_{DY7JYcZonRNw+!jzFE=+Seh_!ak3T$4i>&7~*^Mw*AsBl$e;hPbq)Ra_u&
zo0VE_eJ#eiIG>=K2nr$`P07f;xc$806zvpSz@KDe_@lD1mK{iqnlKM57~v<(P%*y1
zXonrh%f{kK_zdH$5x-iqu}N!#A3c)8Mi5s~NulV=2A@XjxlpS6Ug(`C*5{
zMuK+z!Vc5wzcTdOvdpET(6an?K2h`)H8$&Zexuuc6P#zNS!ish9V3CCv3BKWG+s*I
zJk=Fi#dQ&a9JIr*#>~*nd{?N%QS6_}qu(z^bI0NrAQ$23C#aS9rPS)ZIJJ5?h4hx3
zwZ|J*^1nE)_N3i?#ON}EW~|GQYT9+vNK#qkN&V@l;|?3oG?g0c>$eYMuQ1juRz7+d~UVeeq(F-bjx1PsKk)ry!AP=
zvac9RlC()W&S4GasKuQ_zPHRtJeNp3S%F$<&DGK(Prutj-KQ_G#~60Vpy`%K+rFev
zK%J#1e4yxZIZ6g@t=wt>wiJBgn==TsGjFxH>O>uZG3D>ie*;io$qzJ+l;^2_7ll?8+BnUldM2iaHb)bP9`skwcdZAgA=sB1|mBTD5R>kkdgzy6bF!_GF*
z+R~0%Zf1E3`|6CfkA1Gj!X^{lhF$W-ZoffcH_Dmz>`qWa+MTwMYG~`o?$^RCA^6F75|+2JT6sh|UB4Qwjh4(YyFZ*)K+74K=8o=NLGTJ#Y*0
z?{bB&Ab|W*4CZzC(vfrm3*zOFAMp**7h8G5fX)6cd1KWlD+384RQ+p
znN2w(Em6}4sp%S|_sL`9PP8I@t-d+mUrh&2w220^ouzP`nYtNk+<#`4tV-T`aENOG
zC>VIyTIs{Cq4MBxmAZZMAg#~!`+tT-1x|vn_YY=a#ZTT5`l+xD|G^yE)=FsvQSYD3
zE$wXq!tMN>Bsuv;7;`0mSjV^#aX0aFWnPY_9368+e>ytv{k!vSJ$fP5yY4VEmq)s~
zVrIV5`)T_egJh=dW8g01tkj)-F?w8wIZ0OLWZ4P`WLj+$+B!1mRAva)XMQC1d5KOeS;z8e9nf0!NeI3;7oNm0f4;*aQ7<9j8yQFQl>?A%3QWGnQ-X%p!qQEqiBC}NJR%pjfP_T&oz2U7lBc&nH
zRF=K!>0-EZuRKTP{X3Q?jZD;MlMDGVeY_+$1iqi0
zNII7&DPhXF38Zx)eTyoSK>uH|VNC&LDQVJo*0NSYI1gm5-=^L4-
zGj)$3Obr1?Z?>`d`MDsj?&jfO{LtB|DV7DcMl7v
z20N0PG!AQyCI)l3c(}v%XTZNNmEhlQi=2?TRvZ$-tarx?87wJ8OA^?Yzdd8#lk?m$
zDUoI&N>U{yhjk-xv2nN~aWMa8t=3kl8I&X?l@@)&8uRO*#n5T(n=fg4tS&98XJ_-{
zj%<0yfihx?6WA)fRIlts_BBO*&rkm{0z@
z!&a!FKGs2c=WVf}EokKmT8)&tn|n7ql607xLckL#B@b~V1>cRGeG*z3UXrPADY3M$
z3H4gnxc(f>LdrVU+N;QbzOiK|b}x%MGSTfwB#3j^zQoe=*BDOOfp4xU9bCY!A9N%Y
zV!Sw$2d>kX7F|+KCyn{Bp_dpz^`2X$(J>c^E{RU1A$#%+$B4GZNUBDUW=*9Hx#3I!
z;A7C^aBGuFokf~Cf;w+IgtII=kx$+OX)^Al+|YAFq_p-)N#_ac{S#=Rr(8R$6`0X!
zZ8^H_C?ghyvX6>9ZAFUaP)hFD*Uurk9sBPf`jgXP?ZthfTWh<@SFK&h2ArhTv_ohF
zJXo!Hd~&38eIOt)_HI=nDQf~n0g|`>$B?Z5caYTfYsq5#kC5UbipI(>tmMbFt1m
zi=(QN*;hHa(xnr)_4TFBk5S8hwO;3_?!|f5Ie#i$n#f)FsZ^kJ&&~QDT@#yFl(c^M
zwgqv8)-P#&Mo!o;K{Mt1uUa|c#^v|6tH`UY0q4@H`_HhWf+=60~F>3m?_
zHE0Yu$J28;6J|NjW->Ig?!}I$CvYlHT5B`^g;|IKu6E`|i=8{C^U3x#o%E5?xS{=T
zIBZRz-)pQi@3-+piLpz6)NIMO|6t}m$-5|x$(})uY(s}KmB@k
zVn8u*HMzE|25n&0u6bvz4=8z+V82nM!LHEIz8f>#xp(WBH#`e}cbl^wutX(pO4KKR
zKV{C;b5j$h?VA=keZ%xLV1~C|a1%F7sfh;f9gw#WJVk#o>YQA={4+W+(&=!avM-QK
zvKIW7V>0IPwH>vUj@+BtDLdn^^}?<|ZFJlhsHH!h
z^|kb;<3DeS&dszFL-+i%J%L)Cg>!W;;CQgkk*L$rPNYo?*7ajSNwgc$ywj{dQ7PB9
zelV7$nin!z0ACLb#n3q>NY;)22t7tvZ+xmoGY`y1)ztsBUmG@d7mXUH9
z`&l0CXOUkJAC3A9@PFcf%tSLbF;T%v^04B}-~?TK7BKe55bTq3!z^h}4pEdRXK*`o
zFb!u=X9{NACk+692Sq+y3wnI_zuHGJpKgbBF7Wf1A9~-972<7))&cPGAwf(tsB+iw
z=ZRzZWD=4A^j{6l`zR04?IS5?Y)QyJ9Mw6Twz`nJDwNju0l!!I>RGG`31cNn90N?t
zCpl|J>ksV~ShM;j(y{wr)92aj4>f6mY&hfhxOT@kbK2^`8gLek<47>5hT0GCwqJqv
zUCmK!{V~biv$ITEr9E;@EB$Sbe$Z*jy52@(d(&H{60n}<)|cJu
zp^0-;U*ndQ*#&>*3e96P)(tw@=oW`|WmNxwRDpAtPg|^<=0~i*{}X1}&J8Z{9@u
zF4B{9J0ube`C*3+Cb^c@x7&4BmBLMMgLZWljz8Z?BRLuj_^Uiv3(Y`
zgvvpWmn*Xf+9Szw{1=lxn|e9-$e6EYUL+3se9h2RAFYZ57hS&5TI)EG1AG*60SX`4
zA=F_8!67?kC)+!B(hi_@z*_d&$V*aVZ|=@2~fLRxLGU_G3CN=bD7Gn8@Eq8?b6$o+AY(tr0Ik&dnUc9|NcJo~c~TKO#+TD06GAH`2C@
zAifkOX{KzLph^zJqt0O;RxsPJ&$=fkQtCb8EP7M>nRI;WQR*wD#*Mz!k%^Mh=c=Kr
zPYt0S53cM#oIeJgjkix44P?O*ZPksm3qz&;9m%m-^lRFZ=z>Imvl0mrIJ2`VUn5-G+X-pgh|ShJ7xm
zk+}q;kxsirGo~($tnat(&|uN!Tre)KlFrF}f=pc-*%g}!<$J;6CfT}UzoC^P36jpl
z>X^U8>r5QZYp`LSfgO5k<*vs3UU%J)(RFxiSHn^bol+oWCxhV+J560f(7snpXT)H}70CFJc
zo7eeEgbTTL(K%1I!Zvk;zdXJxiZ+f`)Y=<-CHN56q!alj)mC2H^Fy?8T;#8{)9NDo
zc|7-~qK%>zM=Q4d0PtBY*XAGRt?!!84qprj7wc@lZ#AB&W^CZ!Ezw@*4!_O~tTW|B$Oq2(h_@=62J%
zT~kSeYR_z8&zP_~&2E^s&(b4_JPhD#FuP{{dh4(Vcmlj~3ggKuJ_)Nz;JF!klRSLZ5w{oK~z*ybXZ!0&bJwZ>}FcKFjBXN3VK+l^nidi5s3H+Fj1cj$PH0Wn-7_(Yf#Ej+ZV8#MyKKLajT^e&Eypzdylo(_`ZqGu{7R0|Xr5iXk$oB(Qf@NdW_1U-
zAYjwGT4k0V=*40(um~;8J#CUSSIlc_k8SS5-H$uV?>u3IJMxJUb&2CkTl#Q^gbIf%
zM+c3yiCqIvXkx8vHl8dM8Z5E5`*6=LHejq97P@Wlyx%3{0q#7EuakEiQxKmbvxIQM
z$EaG)`d-9FJWor-d&#YZ}m@M2<(!aEE!zxq_tI$0u#~Z?4
zNj(XKqofB3Y(h=P{pd($woVqkVi3
zdc&+8Ua(Ti{Q_w{tj-K^BiTQFnYG51>hU0kNNwH{$>nVP#7;fdao62fV)=wSxO
zplxOC%^`d0Y1Li^uLbl-R;#d)dveIPpdQlhfSiGmWQiO${GahUaYXEpELKsDd2luP
zMM>{PiF~?Nt||K}XaJ3ftZAyf&;DaBD;y~b*V?-Xup{3gtMx|3lgbQy_=Df_m!k{A
zfDe+S&p`6$tczm}*7(OTyB4!MqmzPtuN>~96W$syg0rfUGjZdP=>26%{VJ-zAN8{z
zb1%&^bfkvGWt5lwq`?~Um^-wO;LWS0*|tJP9flfT_-Lh^QlE44)`;*ZDf!8G#p7k`
zG#*mwbxn^dcoGF)XC&KGEC1~4L3nL^gX~jP?#4G7%gDOy*qsz^#@+`-`XX*vH~&WwrD)4QR2zW=UyL)$x)ocH?d~ajj{
z!{+{$skmN=A$*O(s$E!rWQz@+e!6C6f0z$GHKhND8)mms&uQ5RJJb1xP`(zP2E@5g
zzuMwXxV#1V2dzquLm}q@i>bK*Nj0nd#7tg
zP`v-Ohlp#y8ZJBqIx}B`g|%N3Mx=`mu~vY}Co|JyN}Om1UP(kQ*Xqcai*_BTq=ZLfCpt*xo@nro|O7Ev)WK!QtO9V#7Q>Jg^#%8
zCcN8(EVN-cn|~o6_E-mIefa>zHuy{Je0>`{H_N@4S^hGko8>kN^_}OH3oW|z^e755AfADz%pMNCj5`u9H^XLC`95>?b8%;+U_wV0m
zVn2JMsraAXXbK+_ti0cZKO6`DOQ}q(wZEpsctA>RzSJRhyM3+_(!!G~V<3dV;Hii5r16sL5`r*ghJ2rB=Ob>BZn}`^qAC
z-@nQqSVBLXOkki)xG&@XM-jpU{d*|()PD}{^5QrD_zG^8YSM$h4>0fm1OFdmfYu-J
z5$tg+QTd06u|$}!{8M?03PRQhtuBir{novIi57o0(GQy!>s+Nxu;8=Gu$=t|UKPl~
zXF5)d^r7;^qu5!bvEuNP-6p489-+25-lBdti~ti*u3Q;$_v(N0
z&nLCXB^8V1@^KHFdubCI=T}%oA@N~Im*G8=AA0HXh(NhKt*5tK54mPa>yfceTvUlFi+5O$zSGcE^yhsi&nd$jkVYAi!8RAnZKErdhusOcW
zU5Jr7CoIag4M}>}%Dv-A!g*V;uQ{T#uR5TU1kYcK+TU}pwRwIhYSAV=#e(#n?@l(|
z8>dlpSf651iIGVMEM(d5XxAsWsrT=vtmo6x7KNuz5(@<`K8tEcDp1Q7W1tKA<*391
zmY;hCsI@07+LU;RugF&FFCCI0>MedRF#Q?1ByE;`S~08v7C-y(-E5D=cmX+U~Pu8DX}O>tLip&PT^469H>)md9BT*7Q!*dge|)Vw>sJlh7!W8En)K1g$f
z?t=}oK_4!(Fy02sqs{Y&`ZhYz56e(>#Z&^8t0KCC6%Wb||9vC*?1hW)HFD`20(&G?
zK-VItpPlTb;V8MLZs92Sre`Oc=Mrt|jB-uI0`)t7fg7tzlyrUMn(X=B8oxsRJo08w
zdlG+ZxOr;X?77~t_CvniyqMaOx+CB2&7b4V?~nX6Z+HOm)4ch!z3o4a{8`>G^a0!~
zZ~ja*tqN%sGrZw}$e-cOpRU5mO~1Ep3jYYD8ycCDh=cGJxu9{V+OsrBu1T9{
z-i$Q}{^#zE)~OZ0Q3o-%nZuP{;NJ~zG?DK;Lr&eh%nR`l;Cq}>ugF_(2uJlysCRgn
zTCW>)k!IA3mQx2V@zyh=zcIg1?>W@#>#c|Ws)pe;85#Y(?1l3Q^p_&f&Niu*06Lc&6n*8PRuV1H_s*54-2Q_s$
z=>a<7)NSl*MajpgHQCT=rH^uxU0|m(RW2@np`vV2s&N1pr0RIbSCS?_JF!P{Me>vs5q@=%lD$(e
z&TbgYK@UdOwDRR;_PMK=q&wxlr>%`lA-z<5kaBM`wR}0*m73wjD5o+C>zXyRVl2N$
zSl_In8=#6cDRuVmsZ9BQNH&kLxlK-;ok``&e~0*^&3BYK|DoI$O)Y+nT8GEb5o+hI
z)~pY$`051h4uLt|u`%sCPIlh5dGr^fmu2utbn8@q@!`s(BMC=`9)IFw+-W)07_7Bs
zGdZ;;2rDer@;izFE2(T5g(QS#zeb@vf@7&#wjf|%DrdD~grr|3Ki$$xyEV%)mQAjh
z4?o)ToOM9XTJ$uu@(J`pc6!a}xTA7vYJghb*opeedX-|-m*r&&QD4Ow6r#SE5`ykI
z39uO`H8PjV8jTdD8_HHKR*yf$)NnR#Y0^kaw6HGAWKs0OSj`d~)dGA_aJPW0V$ZiQ
zGw>t|&Lp~HwQ?lrblw~dR$cLmtUc1A+V(%gdj0|3@>Ov8j*~k-cJs52OE!!#0$#F&
zMHPdlM;lq>c~e&o{j#Cp?a{KOL1pc?T@tdBd%xyz&CQ1K-{?lMK!$swF%7btexaWzggdt
zv~&#-(9pF6Lc3U8@9)ctaAf40^>yuZ^GVHtjD%i&6F-~|
zeLFLbvw|{znqEm9t;);a9zRYobxh4lTG($$Q+pF0N@177escq(Q$uDUkn!`OCA{p2
z(nY$yiGud@e54xIcT>WBbY2`b=bz1oE;Ulyr!vBtZyInd+<_3dWm{$_at1VoKb1)H
zRSwPOQ?l6z|+D1-x6`(9kiK#b{vJ|^o%k4EG}tV-9(a6(=$?i
zD`;5;_>iV%a^bYg)3(lvgg?A@#~6)ubYzg17e$?WKSwUlcmbA%^06Pgr0hnKkI_XP
zHR-dNoW6cE#pLvHDeCuL8&*`RB@!#De7RHgA0UoIkk$PIJAne(z)|2JC>K6P-KUG6
zk*o%a<2wM~#ZMzVmP(_Cgnbq>uZaZgspVm088PQzo$3;&b+&j{!qXUS`M5dQr!8_;
z_+!wz!ZWB_`C1RH)g8IQOtZ5j5n6sf%w`Mh)P6p#t-6+lY09mJqp^ImMlPAvr0hGp
zg;bZ273bEMB$hhsHQHVJF4W4tBG?*&m9}mQepPKQJ@Yg5y5t94x?jhZvDUDAnTmI(
zf_FK2NJ#wASZTM$42VpRwM>llAhoG_xsHI+dub7oQFI&vy;wNXOH4W
zakkzgdl$#9;~}AUV|J$>^hsYa@m5P<_9)2uSR19nb$IXzY~u;+6RpI5J#Yz!cUr%_0z5Si~nTr~h=Mg>?8}{_uWhAFz_r*>?k{Ws|hzRrb#wqtw
zqK<2E$Jk-T&FZc?-j$nF>k7?fh6O__(FXahVaGU?@6uo5>^YZoE`2>`cV5zG3ij3Y
zeq;eQm*cGhok_o!?a)`SaCo;gvLI{sVy%_DTjcWfF`h?!el4nBnASFgJB`MwDWa9)nqlkz*`j(Yd}nNUeA^gCB%d^|&vM
zPeOT09gOn*eW{|}qDLQ)arvR(5~?3Y?$WEieDEX6`?XxYH`cAa_pt3)S3i{~`(KSJ7ZS2Ms>WWvwmXh$y-AL#edw1))fnL`-*Hsy
z!+ojuk1D9AvO0fpRO5R1>TragU#p{Pe8iV}cdSo=Iv(yY)(suU8gbuP_ehvO%o5sC
z*38~u=p&3PG;{bgNffGX6EwiqRS`loUR+_OoO*bmMkbODLfuhiwr@FcFFR}2xI%fZ
z!a=JFG}x`>svI8kJKw5Mdy)PVGxv}$Ek0e*DZ`zpmY
zETdV1O>zdcZHnBTx<`^c<|x3e&-I>J_}Ap}vkJFWVN-LHmYj0C1YY4fy>0gSEzFeF
z%*YA{FR9zai$ZL~QAB>@kEX1hzMP*Z$D4k~m!3Hhd`4N@(K%YIYZu8$4YPjKTH!GV
zDGdIFx3$(f=CCy~S}9#%<0h{aKJET`FQ8=mO|{lpghwFU%iG%WX03Iwx3#jSf7KdE
zGQ@-7-Ke!o^*T{7YVB+4nTliUUTBnF^WoTiq&(5FJ2xVJDdpbIk6(}(s>osCnDY|3
zJbSUPq`4X;`#2*imQYE^8~s{Prs{pUJpL758S)(`|Mry2)W7Bs-Ft_wN1zvH>H$xU
z-kwvh_xXw8Z2^qkjn-ac6Icwx3f;%^ayj=(h#x{I476VdNqZ$%#_RPo+r;f>cdk||0A{P@{8Aqew^k%{C@2>!Ow_uwsb(`
zgCP&py^vt@((Y7~u1+)F*3Z~IX$L}c@N$t&Ga$#r*J)n1iH5Tp_h9VYh-oI9^mUpp
zlXu`RZ`=GS-YlBo0Jp_S|3l)qb#px3@#c;7tcD;3Y#%_|mv;YHeY`*As5(EXqy;0G
zb-;^G<(~;&KVF9|1UXqey+(tXCjI=nBz
z*JvXp!acpkv?r(cDf2LG0`QABoJ@=-@7nT;>FG*bloWhS8TT(B(8r`fcmrnh
z;e&3R$(DK3&tp6j_LkutBfOfl=yNr->H_Bf*)1qn^V{y#%aZHV&h|glspR?;0}t9`n|z1kNq}
zy;$H+pv@5j%Le37PnZexW#BbOsIQ2TgRGtXw&%jHI@LHfA!(m?UifO@|EcTy)%L2Y
z(B6{{p5xpTKy6Yb_PmNGL|qW)GSqQ2-y(ku{4#r(gC`oT97;60?bn`-d2Qx-l*=0t
zH>Vv`+vAU+{!nlDIL7A+4#o#bq={%KtM&1U_#j0$(eT#Sz7#EZhD*Sj(6uO>c5y~zmA*Ra
za7xALug-mO@w3msRn#>Bev((O@zMeDH(EarDeEY^zUxPp=)~6({gZD_nLqX7)TC*6
zZv%XW^d`n+dw1TuVypyjpR?o^|5X;8#K_13E(WP_Z?&0>Ax7`
zPJUsGJH8b-xZ@Xh1TT>hM3enOitJh@`Zz;{gHy|{x`Q&tmpm*YYZda8I-(%Cyt=+xPA(B_H%
zu+3E@adl45*F#!O;e)w~i4~KNmC@P;O`g|$fqieVUB`DJ2nKhHA^jd+s_KPNaXsfu
z+CI@c0t4o+d*nnusb4oawZP=j@ZWiJI$`{wXAc^56eoR&#DQMAD*LMrvr2D)r5b+?
zKNsYK(_OI;rE)&~{F2fCFWehGu%*a`+Kf)orIIG$)5=PEuqC`d=xb2YaB2Cfrs
z)rAahzXwMhEG+~_%e$*dRCBvz;;@GJsyfuy5q{>pj2CaXG-vB%Xuov|rfSQ+>L~xpwLQOr)kPT>
z?*V*V$6PgC`dThozr15Q!GLq-oQ`RQM$>=(+uzKVEexYnLsule4h
z%JOvjAk7bS#93*99aGiwh@8dYbwF=f6~dEpN#hcKjI1sWf3s#!_T{TIsr(`-c=Zh39lhZcQOAL&sXcr{AYm+Qoqn*sKRsx_h>tCYjHfY!3V
z(ZM%*W>;P=ktLECeebMfPLxZ|u1U=atdxe
zw(iM^&Q<3OI=}0{?{iVPbo&}N{tI4o6CQyr9`aiNI0jSwt$1Y=krQDrA%FdwzLBV7
zZ@9~kdSv9D-hOh|@#9BNA30Zf@z7`GGrv+fQVfsR;xMupoqZkcPvI0d-n7h5yqK7j
zd>}b0WmAfN^!MOIy}^k@P+dPi1CN{SYl+tCzUC5je&3Gb!w$ybsMDZSsJyH`=t
z4nsV*!#{!pma4VbVW6YX$uX&!wA+Zd)THQ_OU6y3Ry@m^ZiRK*UgW5Dwwe5K!`W{f
zXEH=^o}X_2X!0A#JyUkC-@sg|vGdday5B|R)Ni)ZZ_Q%0-xE1%zh|FS`ps-=_;2=G
z`&OG$BS-j-dUj*P{YPI(&P(AtjCdSIjC&s?XFkv-bDXL}$8E@%n)K-0E~B${V}Em)H7(8~T_a
z+XtWDBHdut#Qa;It1H;|y2gsEpRXg8Zb~#Rr&&2oc;>gXkldnWc&fx$$kfX^}VovUI_8#y*7K@ZoR5&bk6YI0}$b0hPBAosDJTBp2*i4
z=&!L8{Y~#oe;WemZwc-eh$Hl3R^da#7FulP^rQmnpyjyq5X1}pp2P?3=M{;%N(TjK9
zKLY)Ps@5;kjC0V8H|Lkun>qL%L+4A{@#cK!ni0!zyXZEnVJ^-L7JUU`sXg6>X3oW@
z_Iw5}JF1%VlyWWZ5x!|7K5YNN$$BKZD?ufoTGA01aI(?`h|8J+O^$lD!_kKWe$rea
z&CY|sv*)=OGa2M_oESI826(-E?=tM?!Se+d6)=y)%5>oxbFYn)2ZwSVznK^L8~
zN7{jNnRkU?*NXT(?N~uCI1+Wtd&}qQ4$a%xd2zDIYx09G0k^QTv0E*|Z8v7Q^=zGD
z$+-3Dt!LF2_-=hlngUS3PYMP6bvNqFI-`t9auxF2fDTlEv%g{ky+;M=tgAG@S)21K
z6e>{1K^PW^8gwc(%qvqN*fu}g3eHCm%;%I4?!0;2;J`Uw%jpACI_};g(T`50pPfIW
zA7zYOlg33_3qzC6CB*3MLX-dfSR`E0oPg%PG5t}PE|=6j@1r!w5hugli`CzB1%597
ztRB{svYv!QXrqNLj>&H`?UYJ(%wsnix_Vbe6TEZgYf-{Ql2y+ZykLv>W&a>_bKusz
z*^FL=>X%)cLYW(3(02OJq60O+)E;TSW)U)S=D!`Yl-SWA68N^S+4z4HMJtyu(oc8mCGgBlkSH~
ztw(E#%Ax0axg>r9;l-qBV#mCvQR_{>Gd?>p-p#{nfP>V}Sxu0y8wqQ~gwxbg`dE+<}UF6zU)JDUBYqMVWHZpptI1?edM31#OcC~e0e+x;
z0IKw>846EOn^+ZR{Jy0!0!S<2;@lh1>9$vD2W3=qY7#0UIx;ro#tB
zE`D6mPCItnreE-w>uJr}3c_GhE=l~$IpavT!0^Uhee3kYGuD-y3p@OmbF^wH*R)-j
z{=wZjr28=+oYPkIVU7y|X=A^JUC&?6!W&{)7CrUzr|)6MUk2#M{i~6N&sRqp*gzu<
z9|idTsjRxXq*L(W!n>?B{Ms_oClh~JmH`g)Qe3&pYpP#@&Ozlmi|D?4T&4RMs2g0(
zo4<(WoNm8EnlSLKqGSk&JEFfh{-jB(V*^(0(DvfwhK%QZyPE;~?wKaXMEp=RY&f&d
zuC>{}>BEbmeOa)dD|8PVS`>Su59jDDwA;J;8wp2>o?X$cA9>EcMKE^UrNKp>2mN$W
z_rN}Ra{9LCiG#SYlF8BoZ>JX(I}ofTSmj;B+~8JU9wfI|+)W7tZ;AmH;E_=NyI-)F
zlvF(AtATU7o;;AHjrfnL9ziz)tBcPSXcliAPj9=Z9Xgjb6ID+=OX{0
zwdNo-2>0b5N4OASoEmEveXq6t8DY9*|EET+wURxJ(t!wFL+UuBj&0Cdn-ESzIA4a<
zfphU02%q^5e1q$U(vN@VNNR)~a3JTfWpLUt*_?JPhu3D$GRK&BygVDkX_Lm`jpZ~>
zI}+B7Q4!n*eHUSaQ2Na`To*oe!6j}3Us_+ybG4z=knBAGGXMhHJ
zW-HF-cY6?8l>G-3-7XgooQIY~*_e*od*Bf73v6F1wF~;#BuwXR6gItGKb`19ZO04U
z9l1CoP08IZ%v8RMg_+=M-2J_(rLApp@p`q?+mL9C4M7SI?4s~PQQ?ij;^gLd@nTcF
zYf@8u>8RZ-dS&U#zgl9)Y+|v8b6K>L_$9Rlo-sA{q0^RF?WY#-NIH9fOPY%NaFvI%
zs!h8D&h$(gXg=O^Tp*qUZq+I`
ze4Y26jZO^x6RAJqFmK)`u@H~vUy_UWKCN;VCuD!Fx5!s|Utt&v?UVXqyt+^Mq?WVF
z3E;mEV`I0DFpk~P5yt%XpTp>ytF!zvoC6c?odU8Sz6a--b^i)Z(n->OO8SZMz~>O0
zqrk!Mo}|pjfnEGEN1n}|!pNh0c;PqS`jJ1@m
z7xfo!(W^%IjRt>dfwsCAqhHbhztOsaH!;UfX@;GL--zC##p|QGiZx%Zsi^SrF`^}9
zhy5eyW3b}_UJ}LW3(_5(zZ%AVC#Pq3rc+M-x_i4{WQw}eqn$ObYdXKZb!uynK0CD5
z__(h%-rL%u8_$$c?`Io*<&)icur&x-d)+>GGRqdFr|~l~qRaiITzD3hclSwKv_I26
z4PE3lIXyxP|3P-ZLO$Xosc4S8dx|{VP4HYN-U~_2(4rwp%B8>F{{AM{MgbDi+I4%1
z_FMao(!w9bu5&YcsK8MTyxm`fw~8-m6ZS~joz?xjAJ0xo$GZo6AK!Xx
zfn9uYIcD4-U)YV2_s0us*!?~>MXxuS1_T*R{j!aw$0CAEQ3Hcaz2bvRk>i4})*HA$
zdjM~w8bK&u^)X)iX{ZQ*%_ETSOsNKH%nacEtX)8!D+>C!{i7N$pEz4^r7}
z2BZe4E%Zhz{|TkW`yo|OQzMXCRZgjOdZa!Ai-?p%d(I}jlp{e(uYG*Oo;+2*s_>Hv
z@GH@tYtXqu44k;hz{Rhq$o7YaK&sY1FFVowJa&E9JA&SESPhW%Q-XK{_@U9Bx5eMp
z(gcs#>n)<>Zv=l0ybalH#HL8e5nd6b?Ufzm06w&Rxgba13ZphU+vtdnH-=y?!37I?
z{-chpHpUvRq72Z6hj*%TgLC1PdNv0ZP^l1*2Cm+-N|eqcBiUg_6t8x
zXa8FVb*}CYGyl9@ThK;revXN~%kp%*!Lwyco4C=R8=t#MiqA%yzkScGLU~pvxiet_
zU6wKF`1`BK5|dJ+S6<7b_kX4yjn0F`wISjWyB{Ac=1gsOEyYa+{E7_uIF)u5`DUQT{Z++Ep&j&IH%FG&$((!=gXl18ezP
zyQuq+9nXn-T?^Z@i{Hi!I^2rKp5N5&;`ailxK9fye;cTLFWZ27|2y)V+B^>@woONDnRhWu9sSx>{pvbXCX>lo}Ya%xa_UugX!rzIM1{^7g2$WV+Y-M91k
z-hu46UseU7{g>cB1z53Pi75YKg*V1`M}IFI^PK?00RL|Z_BYEo_=yy1jAMxsiC_hB5jei-OR};O`E<5$E
z&|nrq|JVqX54I{oKEkE9)Z>4vj=p`9R2mNcL05
zs~X6+KG!DcaBqfmu%f=}XuTeChee*rK*NiVQv@J=!IcP(uWwC4(nw&oM8Q|lVQ
zGt#&Jc{Q?%M$MVZ!`8I40XGWpCSKVEf=+E|F|`y+d;)QgIbgdu%3p!>02|a(EhLQZv{}D#xIw6F-hJdk_|T)
z9%=yvaDF26#iYF!rx-YTcTSXq02k@6Ysd93b@t*SRsD5C&!ePgzhLvU?N+SI+>H|f(%j@#dn
zYCtQ{KY(uX>is+$g>O`y43cMN`^%?y}+xYW3V@i%(^QSD65%2ox
z@RE6FtiL{<(89J9C%hNpT>7jEN2tIILY!p(^b#8?xw`V)CsIYO{n?vrpCsb`UVN_S
zt!sCVJ2{(Uqrmcn0Y#pzO>OYetFW)S39T!9_4GG2`!<#8FImL%H{*M(+`dUXKh%<-
zi_f|LjW6=v>YEsAb7~Y$@*LLotvq|+h`|hU7jM*4Y+T#~Kgec$xDw02Yvmbi?O}(I&Fr(9
z^bS}oaI>Q1>wK*~o+C+n^)qt8z~AEy_n3HpN3}n!w6IiV$}wpM>P=hNiGBDrt;B#7
zxnS?_e9-Rw$zdC(K$~4nxI5^^iC81gE_lWP>_J}75;Sswao!HidXDlxbUTFg%pTw5
z=Kv?fx4%Q!%j_xiUBT=ln>st-g=~MCzU!FX+Vqe^Xk_*=^v!X0Ta(ct1aWptQx}J|
zP8mU&L#wa5JA$B>hvWDBl(U0mds;3C%4j_3gQQ3+7o<-&Y1eZv?sr(nDYehEYxU#q
z)*kp0=cd}CWE(9PjC;|Fa%oDrv8`Ht+TC({e_MCZVa-r-{`8YppK&)Q==n_KWGgv=
zKWg>acXKipPDE?#m7GPlwEFdTbI#6x4msPDoHIAI`fYb}2F{bv+Fm8+@n)@l@7as5sxA{|Vn&tAR>Rq$$8M$9=|6x>rpCccShcbic-Qq4a=}@f`?|(NCnui4mk3@&a&4Mb
zYs=O`Po%|873D4aB-TR;^tzTcBh?h^aJgW8GD%Y>y(vTUy>ZTid&`zZ_oS*Z*7GCeu0k7?@PO-DV0m;07-IJ{W$@
zkA6dB)g|1<-TEvfFyov3$gAbOe%e0%bmoNyz_Ht(Wmh};1h5OTwofOddWEg3=3ASvTebq)z671PU{tm0aA_ULt8`~o%(=Q@?
zG4kx0K@+pBD~it9=;R&bCdhmcVLtnr!u{EhGE=cXdoG&BHltU6h0}mnBp^Tf*g?E7
zSG!@dndU_A^w%B{*ow&{32z;_qG-F#U^BroRdw*H&9edeT7}CvPvJIg)P?YUwxiFk
znJn4x3k9q^{VW_AvL_JKPEQznpyuTvJ!}|9g3Pc?m9nQNR{QXS<5C^lqH(F+gqg99^D85egoui$VXZo%AXsL`R;Z@a`B`>?*1EJR+GW&6q_&*_
zTNbe*|L=J(F=&@xf4`3(%zJk~=bm@(x#ymRH1fA5X{8c7?C~@{S^g&RlV?}XmTQpw
z4L4|rK>*E^E0kwBW14OLeKzd<9X2bAn+MoGMp@U@>yStJ)8e27GaKJZyrmHzd1Eln
zq>&8QU}7u{3m6OhjdHV)_B7I-)-l{vq`UBITEOg?A}Z&pGo}>bf05_aMfej{9hxFl
zvqluoYKnwbtEMa>XRk%rfZeuvaWejRGDU%k4h-&wWTAL;#(J^<+hkUkLU
z1Cj2J_V8y`YZytJgSWxH{NU?YhuXv-$T`O;8Rk@`5xjwZym+^yZ(S0t3=toZynrGz
z%sCF|o+mkzqM^(h*s4RWCBhC_vY65$X||aQR3Sx~kQxIY+y&t4yHV`8j3F;NG#RYc
zFY1dEpncer2H~XDpC7z9j#}6g%bA?di`FJ}Mr;xO7j1&N2!CcAt|Z)c;`W;`o8A!5
z)kgrUj{>W)jHOWpEC&I*^M4e(gxR7^P3od8O=_}|Lj8myL`LPBRE)UEr53li)Y>2u
z!t3%vOxhel+*qnE+UQh^nfT4bZ+e#oT6!AM-lQqAyENj4m1;2~SW}cCXvEF<-7IJv
z^U|5w7BS1EMhs20xb-T|XM*29j!#c70foe9V?@ME4QD)0?nMaZr(2R(MEpwuVTrsx?GyuCsKIDYAFK-C}?
z3kj{`6ZOB~8$)eNiCwxW;7Ux=Z%m+NpRfcrhIAIe$rbC&T1d--<*!MrQG%b_^IOu#
z?ytw`^-s_s-nwUz`@WHqCt~up=+%XVz2a7OA+(7Z^GAY;MhYp!lKiQAQXQSJKLHjI
zzqcE)z>ov#SfaxW51xuRZO_?MJ;8%(;S2FO^RsOVg4=?xn#En#76k)VP`eGB}(lJXrEeMV_FVmfGk^CEY-;$5y(1*NuUk
z*9!gl1oB1Fx;4gFpd^hztt|uV-4X+@v_RTM`K?=1r@Dt^-(HG%LKFk4{0`3fC9Ahq
z$56|3H>*0~5bEOL=T^ob+#9Z^sUdT
z&7;;22iKHMY<&*+N0R%Slt8Qm0UUZZSr;wjHgV_avHG$*+!j#HXzrk
zzs$+Mskr4G0=abI44eE*J|Cs0OS9yhlvt9!(AdQ-LIO!8>8sq6`gvxQz1%L{kkbi0
zP^(Uvlo1<~=HL@~8Wr|g=4}mo4f3{>x4tfiPfX$iJk<1OSeM@K)dO`1d@uQe)(V#<
znU{3=d1+g9;^_uRo5;(5M!EGLEwdYrn2yAm+wv59A*GFh5C7d=)q`V{6F$T_KP5(U
zsLp)_a`4V}f652NbdV3%XueSLaqg8N$+6?A<0>+`^^WdtfA@`}x60s~pK9#>mOc7(
zHnsM2L520|Ge?Pcx;M|u
zPpKM0Cad8!rTWW4PV?N`{i!<}OGOKmrx5>BdN7
zQfRF2=a`d5a^dMu!>ZxIsvnM#`j{@|&U$~dK3X+0CfbJk)RfgnPFGI1FNb7X-Wj}@
zWt^_};Ply~7f(fHvc~j=lA67B2drMNUtV8dubyZPOALGwb`#(*!^V%M|KqXO
zGYZQ-S1;t7yQm)
zEo7h4_Uo6FIwKR(sJO@Wz&kwbYev=ea-*!h@GgP2I&Qly5BDxg|5rNBaM2ZlF(&$v
z4yM935A(54?>5?chF*4mk#~#6^0u&U-p_jl<03y~ERjbabEH4TtbqKri=h<9Sv#XW
zC$KB>iWsMqa@m4h)+If^x3ehq7QVDh#&N6Dze321aUbhx*Y51kY8Urs&1=3VfE4#0}GEl2YR=r88uB+&_fpo!;r`C(<9MGg8F85ItmaPhCzhU6Nr+_|uwsk2o!*
zA3SDG{6-;-Ha(PiZ>N~z8`B<(`^q=BHLD1xa_`BoD1kI4WK8wFy;ILPv;K-TxwDq_
zRHz7_XPFB7yqJtEcSFmq0=L_pD`B(hcS-YR9%&708$9oGYON{>cSeWUrzRru!>bKt
zpc9Jx7yj9}3~%&@MW>!SvGn+gV=p$ghFyB~)pR;rV^(;n_RBv{C#Q#S=Q7~~f80j1
zzbe2|`XQrv$!6d_6c}fjjN9bJsUB*fD23+Rb!tlq=C12u_!!m!0%$B?&$lTZoewh=
zc`eMOU6*fLN~b^eqco+=@X*xkffd3d9-0C!h^At52>^|hH!v;Rg#51hvWyTLXgv_zG
zwgoInGZNP~C=NVd+Frv$23YXX(Oyk__wXZ6tC-|Dz(V#J81tt?z+_WcK6
z>4=a5{?S{G{Hx!U0`KY4yAvg_)^C-(EBVWjJG5)ov~5Au4zZ+kD_1IPQ>oVMShz(e
zFz^qwZi~3zMJ-1%`hclKT~1!#+cU%hUnj3@`9wIK)xATGoJLU*C~EJ}Bsx|8w5&P&
zcEl~fJBRpuvs#F#GfQJC7PeVRP1`gn+6$4)o=w9xXx9y8%no5B#VZkt1-qHm3^H$l
z4h-J8{icnUQeoq^SEihU)K*GyW#D9z;mCdjj=(1!_mo1Kkm1lklfv&z@1&~gl|8|e
zKH^_?*n4`X)I5|~wz)i;xLkg^ddnik?CP9O=Fp!O-1yCRBfKX
znimMty}4L;i#e8Q{+04RZeM@KA+)UzOpRV+V?SQYpZd5fFXT5l!Byt=QrwEQtrr9T
z&cI&yPm0*>vCwHA{~L-bIRURy=j?so0r^Xa4RFU;IIX@38xG
z4<~CohySqJ90AzhmRA
zUg&6!8o&^I^X`VvoWstyiQ5P|_7xdAR`fwv{bwI^sUx6MF)(uP-<`J1g%i)N>BbLJ=u%x>FX-Ye}0^IzqIJu_60P9
z$x>f?R^FMrWgU#x1}<2dyAjWa&o7^k{)Y7FFY%uKwCIna`Aa=SE!LPcsdB3sKhbLS
zLW1HICqcYTf>@LK(=cD2KPC2~*a>%50%(eCAnPutO39p+;v?a#z0Ikr^M|*vo{p>_
z{%F>!HCnzyxRwRohcK+1gO6s3QC(XtkpjvwO4J%nZ*rU^xeYlkC&@HPqN%8%uO1rq
zhz>$>Gx-b0Ubsy+lF_Hb)>15M-)bqX+uE^1ENS1`n)o30?Yga0j^0D{)fU`@am^Q<
zB&)C*<}B88N0rQYXi-mNCe?^3*o)dG9}!bVvaoE?V2xY2M~bczS_Q6h8&;qc>KEQi
zqPj8Cqts7CH~M+2i{5B-QeQ|5o$Bq2t5Y(Ir%sc4@%GVsSWL0v+_eWHsRNP|1#qo+?0%yW+Sg}E%l2QiJ~r=ULhpZ`777ys^qnp^bCpq};RPeZ+Us*F{F
z-V62aQpkh4>k>uC8hXn7m5KYft3~~r4p@*?Eip)IL5Y1M?irv>G6H^?
zM$GLiX(b$eytYeSUFlR~?cLim*wWx^7hgSH-JKHPC3i=w`0^Dqju%j(6lPV9Z@4oh%76Z2XU;%~rn
z;r7*AvuZR_t0Pc487m3&xJrdE#|rGjg-v1bT^J@7wuE{2VqIiAV<{2Bv_jWpT`Z#?
zQD})k)Si=$t{^5kxZ``rRaF?ZL3K%5puwLG@AxLe{*8z#LKyVd!)PCem%ypjJD$y)
zR_m22kj;`#iSN;X)2i*rj?lVL!{r^%ZV9OC7#m`6Kx3@n5-bmHQ{7NWO6aw~cOvDy
z2~hTukHZ@NLgsPTXC}>2lw=Xth5B+)FL;uo6!}t|$U8HGH$@M@US{g(?cQ?c123#+
zX3WcM?DNJ#Z|ywp!lT4aDGm+;~
zLsGBl&SL99F_;Ugjde-w84oaH^7{)}_qRfd=tpmmF5Y@}3+zg|P(R$|$5GnauGXQ|
zz(IgiA0_Y9j}ZF%@kdM*h?_)b@aUX>3nVSP$Z
z57{Uj&f`tlQ=@}RnT&dhghf4TOahwOX>1Jrx!f)Zqrd#IhtBl+I!Ywgu2%BFmwTbpaaW_$qNWtgaWWS&`&Xk!PhKms5N#D|(s|uL;#zw5dpn`ZV(gp7kMyz65Ri}Sa
z)?NW$6>7lhdy!?d{TU0q20Cm(3_mS8=v_t|+u0laS`b^2=Y-u3bPk{4Vqv9}69KN)
zHSa*))>;ev20HSBnCSE-#!sc?gxUAyns=y`+-M^UN&CEUd19Erh8S^+y8261NKJg)
z;k>y}9W=OhZd^#5t^|>XRk5>es`5PZw^x1;^Dnn{kRZ5tQFg?TbcW6Ak>lqJ*`=rxsb!1@$LY`Ba7t>tX>j3Vx
zY|RSWhtN$-Z&nPzEmt$XSN=a*oWMe=wcvz8s--B>n76?HNc;qzlFuQ^G=7I7C77Y7
z4(VOn)zXVvT}}AEyRutKqwi}{&bS88KmlJ>*6#47CX@qCw1@)L^q{u5d
zjkmkcJC!|Sl00m0Ipf093f6d9dcvCRN=wNwnZGU_NRnAu=lAJ`aaM;NYtn{M%s4xT
z8+-DY-xDk{0$Y^Q1mF4Y+~D2}Q+dV#YgC3=)1hun%sNAny=5zvk&x&-%usAHQ19V|_jBDt
zg^$5=^kjiElUBso(~*doviy}P`8*egsnEsu9U|1{Ga(L%4aj<
zHt$*a?B=kGZiVJnYhtT&jRcR}%Ovy>lli682l-icGn$*%?^q>Iuku8pPJHkmfyUN^
z${IhV4$;8qW6g%rGw#_EXO(+z0Dbk|Iz;s*SIYImbErJkR>YA#^y-Al
zx&wAUo+6BuS*JH*eh%XAU4kZb*5{T<4Yp00C!d(L3s2fELBW1~
zcidEMcNeqGxXm)%rfo;8*{!qoy90`E69>&2FIPUXz*}!s(*@i<$a^@&NvEFt|BAoz
zzCFF^!Y&Oh@h4`XH_V(l4od7sFAdTCLAfc%h(6irwj7Jx`=Mq
zZs#_+odt3`?&pM?7o2h)`OqM`8E0ib#Oy0Nl%OVo{JwiNYFZOl?-}w9jcf4?^{nPD
z%8BB~q|&V%Nq~^Qo4+FEPgR@hop}F?=1Y2ieZlD8R#yUl#Yd4ktGEOIw-#NfL=RU=
z2T{MoD-!&g26*Z81N?jU$t}&$-bS3db9Tl7srh9{IqKLVrj8NWGfWW+-gUH{bu?{Y
zM8#luhJ_z9^(|1oYy8~95BUm6MzO`Z7H+&UFuWnar;Ah$_T#@EVw(bXhGuN~^
z0o7+Fnx_mp*ZOZaXb%NTb458jrJM^tlJnn)#2jw8HwUu?2@#Ei#f=n30!u+i4-2g9
z(+#Q<u)%MmopVByKz<)ZqP_J3iVlw>&&^*
zI+8H_ds;`l^z2;|0h|x_A>B=gM(M^a^L;MVRQr96*3+#c*=BN
zEH@Px9qnBlAeX+_b#6o6N%cD5$0Z-3TFwf_6JRO?w-hxVD(gy+A`_-5!g
zQvUNtEHqm*6P`IusBB9)T#c$a%~$R+zWIn6z+NY5$Kg&9^XLBir6(oW|ND7uQy1gN#_qPMK1F+`
zi=|agZkN{Cw3H)8NT5@8f8riuyPX<)#Hh8aZYSF-n$9rYSy&a>o=w_x;r57=B6F0<
zQNgZl>*3q1F&X|lhhJIv86Z)#D>6*(p!SG3(wo_!f5&2zSJ!t&c*{#^W5}yB;pOV(`y`D8b;?5es`YL!`#36UhAsY5d
z@X6X07Fj7-pTX8SWtKZ?V{6JucUcDMt3XFMW%wqovThEYqikQ3FYeRUUlgtY(JBxV(~`LAGOkXA00jlb|)FwUJ<2eKabAW(amdu=XKb
zKiC7lBw_erT2DOvRgqp0=|x4@K7yvj>Je-I`3e~Ej%A7~)R^WIxD@fxsY@YLPf
zns9JsMEW@!-O&tpMp@-{Rv)5vvfN%A&8(CuX?S6jHPx7OdZAOMnBlwGYZ*q3VP+*!
z=e|#`NxwE|4BSiGCl3&8S%(NV|HD4mW_|93tq*M{Bt7S)?UR3_k+gpDQ?&j3J3plD
z;T1om?TZKRqV0s)&)h@X2@@9FL)!^~^NF_Uo{r?5vc~HCV~ZLOY$OVJYY#!RdOtzb
zy59%UgQvU@^`-6Evt`Vl+%3WLA@)|tRlUA6KAJvd21yNN+8$o|$iMHU?Th;+))Q@8
z8kDeUUxw2{9Wy`uWkyt;hWGo+j0npVP#^ZgzBGS5&NH9+(tI{}=X18xL-TE3n!mVv
z!UdvvqmyWURV8%sPTdQ6RK@|o3j1fG|9pabb%77=x2n8wgGyiR3IUbA)TJ{~sew-t#6+nVcScz!;)?@RZ|{k<00*!-
zVYCDFs-e@O?G5^9!NqYryl4!Bk0z}B6~bBcEOHlsuQ!>eZP6xytFXH`M@S^2)dn+<
zJG6e0oR$;03cm&}T6K<_|Hgbrg-hU~H+;z~7aq@bY#7aH)uXv{`SbImW6yDp?U9UQ
zcQB*fjr(}Zx6J#yqy2mJj*Ljok@Xr3A$G9SP6%*ai$Q5Bfi8eLDs}#zfJjoR)t}zugHC&Oho2{s=;`7~@`NWIeWzxzw
zYY+Khkz(bvz4cGlFaTbluQT$D^I5G4r$<;!ml>LM+AUG9l}6aQE8Nz1=4syLI=0N#
zgl)e{p8LvOtFE*^Chqm*?bn=xlz*TuA%C|q>
z+41|XA%O#=9VK!1r-Z||GJbAaM{?vD?a_1PaU4R61Dt(YLltyi9<)=yfzH1xy$
z@vVJ#?~kk7hHvq$_#wMSm8LI>r;NfTzd++T3KeeO9{8?Hl5-%Rd+$Hwj
z{OKL-9){ts$}Z-}lZP
zQDgGF4#|pK=Ax)4;-uuBpt+d1`#q_zYjR%~tD?YvJzrfW^>y(}>WBI>2l*)wrRw`n
zZ1btVccuQW-rJwdOTl}|nal99b@r|u8{?}WXe!?$x}5w^iN{H-{KCWIT&vN^-IsjdmsgiW)j$ytlg7{)opgSSwv;ANEW|rnsz|fAnwAvQ(z$MR+sPAD
zic+@KUVd|RTh=Er@USCAQEc0NTdql*zc2p0P;vGVjx@k~
zhL9}?xTdy!bQZbf|KEM;oy}3aX{f;e*PN+R?t|}nb8SkriyUZwlRh|Vu71~>C+F-*
zoh?bmNJ14lT^Ffh9ad;N880sNmqQ{Q~0MU@=v2ohM5
zyjw6^BvmiCL{f6v?Juu!*gE{V*pbXD(p`tPtLwJrm{#cQ4H6(5>Bc;?psv97ejc2h
zgg60x!pERSmnL8r#1Q8hwd2cD8lQY
zA+eOa9&FabOVm=eUYp**P>quthF#vQSL>-IxgE#?w|Lv|L4cJ{vegj_OP4-bt$U3{
zzv%T}be5Af;K({PV+^b}jDH`KVKVz8f{&mdMX|}ia~R3?$4RHKbo>4A8{}|U?e~Z0
zTply@+IiW+VQz$l*wns6S-X0*MX{-WiKbRKa0
z4$modjDy1&A-x!Qh&DMD74|0SR8W!rrT1i@#K~Y_9;>xSNGAk32~@b8if9u`=HmPS
zAGq2AoC2~snMt{%cdy-mQ-BRMR1us*7{fWz@rzSIP+n2m6(-tnhKqjs&x)Yzq7*9=
zJ@sQQ=r3Yw9b3_Oo(pmmr7mNlr=90=^To8mkle0O{3*Z4qGajJaWhA>z9XFg{*+r}
ztz)8H7rC3cB0M}*xSF^>?KFcx}lnr}jb9Wwcyd$DD
zi5pYT95mv4Ep`un^R^@BVWuPpagf=KJb7G8nc5ovd{H!CtS3I`vShg>7MDsZp19w+
zG_ZlzKC#5L6#FJtA+74F=u4ShP2UEsc=Gq*u+}ZzsV5s``1u?)aXDF>V0Uldsdp$1
zqbRM!7M1ZN((ygCP5#biin5y(-3pD-tnRvtHoOqXc0{bvJt(qQZGbhxC~po~AP{_{
zce5_(=@Zaew=HUX4&GE{naG^u^N)?&RK5v5&4!rm8kO1BPi1LZ#YAmn4XFml#))j|
z*H7-J6xeMl%s1N=(HR>hA7Dv?Y)bcFWAB{wPsqBe@bZJJdK|zQ#;-V$^BnwWtjcXb
zLCkJqVk}gL{ebc)EyiN*ysDB*r-z9-O$_DBIaDg$TdL=(LN3)1Miz6vQks)oWP`U<
z%T;K2G=v>YBYC%&*Mu8xOGLWoz1nGsi1j?L!!yP!mD?um^SUb})iZ1*|3TQx3imt)
zosksyUfHTOwe;lIIswtUABp(_L)Lk;8_-^`8~Xt5d|~q-9r?bM30T<5q^uhjMY%)v
zlE+Rh494>>l7wk>0P}E6AYmlDjw=?5p(Ue;s7cuD#&_yR7Cr7_$v
zQQV0&J8rmc;3hYix#7a70?wZl_p1EFVwE2U?KrYNwLqhSgVsg3YUY+2+=(y6ojCMQ
z5QmYAH8Ret7`ZSTx>Gky&}!IvY6^5fvTnF^cJ2{)C103dGdt_uk9}u^*2K4mJTS7A
z**Z8AqiGEY8%c1AZwOm`{IIT>ux{J7nu&j!F!{(xc%@z-r}Eoj1NjuA9@|`u|$u^qtDWC0jHd#tJP~HQ`arQf&v%
z_dRso5&eO7dAi-B^VZ^+cw>L#2Gg36)AamU8B_8Kxi}^@cBg4f;rXfWrw={(o}FtF
za5M7Cr;FfozeN+-KUZxUbE~xK!tQ2q6XK@VecC+ppHzj{6Ykwyj^WX#Cci8LnAY1pM@x)Ohe?kKACm|X+Xs{9-A
zf7|X3YKz*T77`~fY4hQNPTW2mdold>|C2Z!%opMcZ&x*>et=aRy}kVqy?1;cIGVn=
zzLXIEYuyVUV1Jtg9gjCMBvt4eEe!J{ucDBE30QMnG=+4r<|;R6TG3gZ5*MzO@%
zDE>uggjfDX@o!Cyn5SdFz0Uos&RaTsnc}z=_hqbb@`$1vb~vOA9y?U;=`f$p73fV6
zwmZ^Q4@>hqR$#@^!R%bvEGuD)A!Ng5zI}sBEL@35)jm3!cvPy5(Nk?piG6P9EO=&7
zF!#)R1l2`})|L==c&6ImZ6d%kJ`Uv-2q2zqpHxEN|>)iJc8>{Jhk
zH4m;+Ic?YpOKc%AX#+Nz{W=50;(hnoR*HokAKUa)u8bp1G#U>4GUewVq
zeg(aB6O8^O2Snuj9_%rpd(V7fl`~S^bCJBfIaX|D;dyiK|2UAD2^+E
zk8B27z-VQ`Q`E{kXk}#6pi!0HJ~NDDZE4PQD#S4KDd03qrR~3>($i2nqG`|=dF*tS
zQzd%Ws-0LrBi9}B&F*+FRE4l`AC+^&m$TKIvlo;&^36Uur@XEG1?zKo>LK{I@}4b0
z2}j0(-{DiSb}4gUt2j|wS(Hlfj>eol4>*;Dh`_6aH4S28$-7Uk7y>UV8YT0<1F$Rb
zq{6@6pmv2ArDQ}-so+OhO0Aw8zCa8`&Pb&~9H3MTMNSd!2-nK?hDC2}MC&J6RXDrNqx?AoO7pP6PU={LwydR)y5Vxa~S
ztw{En#=*zMl3Qw4q}tcNn`2uyPHw>+=y!|Yq3JIJF{^tx*pO{AvpEePEL
zmd^-(YWq`0;7r?OVzwFLY8TcHuw*EQv|JlZR+pJ3_qTa%{0blC1^vhKr4{3QRD6DD
zkHMxqT}d_ySlM?>+Ch95xV%B+=W3tn@oe+4JjN-Eg=c_L<@?zil_^z+DzTq{@^upR
zt6uc9SJKLyO1@B;YM5j{R5`Cp?tdX9#nT&UuZ}pTL#cKev~
zAD_MV>{#$C4`MY>a`aRBY5l(Xt0UvuLGWY&(%t0N%df+il@0F-v&|0@lDUdqU&9~A
ze>sEa+3YazzE7k?us@^6ksBpX;eX9PH`R^GjB
z(@kAA#^LqSge&GmrDr@LRRstDD;s99mbs7F3WJ+GvB6b8Uhc0ZX4o
zaV+o#KTTL!^1u>beuY}c%qItGX=CPBz?-Z
z^%XvvZX4pE=~D2G@pI#oo$#3fh#>95%&HoiM}w#1^-K)Ayo}B-dPepz6kbQW^_nQ6
z_rU#&XJ)uUW~yh8odG`;CWFFOD|4fDZ;S~C&y00%T~A*Qfo3@Fjik}U0U+8YT9SOi
z+6+5rg_Uo4$X^kBFYh=MCS$mMM`jrHrd3sOv@2xn1id_?Rc7oAobJ%H2@a%Cc`73+
z47mG!n0sI}m5eK-I%sd6$QXno_F;jzTRJ`9G*C!&i0=6%6ACdC;CgtRNr~6>YCh)F
z@6;E3@R>fPwyKKu92pYgeNw9KP4QtiMd`upn>Zsqo?ICkQ&5{fHKclyP1e$reMS(h
zObq-YSO+wgXRvW&3Pbhb8E@83vhKA-z%Rxt7gDOsj0XF20pr^{WWGiWe~%FhiGJSr
zk-RsM2Z^?mW`a0V?C8b$Q{!MILi3T9a(BAc*a0ia4W7JpNz+eBxYlTj$&aA?_51dt
zY8P1`o_;h=Hv@by&T^Xl=8gT75!uu9X*;Oa-)prv{|v2t&mLoPoU=0pH6w(>
zcE>pro&u#O$lhx-c(Pf@i}a+tXyGfpb}-rTTN%q=1;%~j+D)vA{T%!ZoZ~jW*UH34
z_}c&QyPx_lRSly?dtq)oiEmBzB<10(@%=G4XE20;{Hgc~8N!I{*;1ypM@o_kB>dpq
z0=yl&z9S=RaWzqgjJue?0epC!_7C;FL?e(bAs&OdBTq?vT1s8}sP4X6$i|_IetxQX
zWhs-|aB7PA_b%rB^qo_Cx(?gltZAIWXExSM%28I!y%VPq$P-ohXsA$-X^5}JIV-4d
z>u107l}gaarEEAQ#}7_LjIDXti>P$?ajw|4&+EMkx&j#vWqmIfRo@$)Vg5t0ipKfm
z@n`fE!WG7x)vhq#vNB2g&rh9{QK9NW1hg{>v%6h2$r`Hf=u%dR2Q;_E!Z?=3doL~S
zwP#PAlXt%M@dEd@h~86E9>R0}l>A!kx7a&%_`~VDzh|6BuzzZ(?}cq**j7fdRaq5n
zH?U@V3u29QOMN6&=1;A#=IO-)*KU6{wIok0>}Hnq;Y0%l%5BwGLNdV1t+0WlEvB_K
zFvO*i_L%C#^v1*1aU09w7pC_LV)=fk)zmTKpt-E5HL&8~hgoq*HohO6R^XK=6`mWH
zXbH0E&_^S^G_Q{u9}I{NE1j!sb&w(@lV-Loo9E{4>&>B<9Bbi~;;R-$`-eLJ0d>BW
z!q-B)_Z(DDWm=iAb*pZ9_K;$S&Cm-@@Ll;P1JWWjNw9|F4l*?sa-+84-^wzri#L$^
z1vhUwGa!@XrfDg0HL`>vqQsTp%dslowU#p>XOyyW>43oZB>
zDc_t~0$ajK8!iXCgIykL0a+$&iJZoyeh`aq*$2Y`NrQ?Yfj==1{*510KVaDpYr9I4
z2h(cqy`x9`WO&ivX2NN6qhq0sF}LRRcdR|?|9PtpYX^9ShV4pP>cF6p_KUVZby_<1PlWJGr0D0vJ|-ty(gd-G3!F7E0>fo6mvZ-B`cw*Ud**&;6_9c}vC<;(G#1|ISkoT|9Z|
zN3gV>uoQ~DYpFq{nN+~d(=alf(n&&+s7WIjkM9g}FN|Oaji5X4=A98p=|+k2M*Mo=
zXFe$P-f!~+_1iJ#?)h;q@4n$H8}BJwfAaJg+dbMy^J{2Myz~r-t0YOBebh2{IRjd-
zYP;M0xkX0Calwi^=Ewn#_Bwy_R%L(_z2eTYVUVT*p5rB&_`W;fShhJ`IcT$f--kOv
z8*^;$!%vik*&@83!<|Efc4*?2*(ZExnU7no`O9FFZGg9pIwma-vI4dP`pagnBVb~^
zG;-;Lp5oQU+m`YCP0kCoXMc9ZOEy(DY%*6sdI
zrnvB4M{giI3C&*`yb6b^dKFpp%Et1;UP7pqJ
zjk_Bo?rYuu@s+*gDO-Q?SoXmP_g|FX`0~O6JT(2$fN_Yz*ev@rsmFKn*0&>^JB@1N
zuuNy^Wt?<^$J0HA)<|mzw*d3f#Itvzd1HO4;j2@ysas-K2YsF
zjp=gfmPgevCp)DMep#qQ+k^jx4L@tn%2QJ*OQ|qu*kG528z6souwLMy)zRy+}QfMYE^PH9xXK)t`MNd?Gjk#I^>cvgbFN
zMXb;nnqsFCtFzHh+Ar4*GhsIteo5pXW;B*xBDp>&1^i
za`)WQ3McDH=&;5~r<3z^=hv!_89*ucqCU}C-!`=B_o%o?!%$0vawr#37h)M@^=R4F
zf7+@~^+Vo$$h!}DLy5+WcwG!$FPNT#{w+~%nBs-({SF0UkcJO
zYS-f&F#@qUwXN|1!HAIgq_b-ze;hs$>}Qtd3N%UX8ziiFJQ&*%P~r`{pdx=S{RlTMNS4Drff+0)e
z=oKq)*XNSP#v#{{eoj%NivA;d>ug{vuBupZFUEwra_)RCDf0`}(Jhq90dC0M)mp*H
zQD3+z^M{63af_Px7+KP%d#B1E^E1Ha#F%wjp&Pca;^_9r=v}Mn_8;>i@LNeKnAOKg
zGf0aY1;<*U4YTsNoOT0up?;U5*FvfueudH|I(a655p7A*fw}tAYCs!ZWanJmBq0cc!D6#~1SsQVfq(
zbnxuwnPNEJA`Oo@c^+e~XbHxQp$1Z<{yfi^y(gsB@XnzweKGK^u>28}E=Gz~>Ki_=
zM#^taK9Nnzl;16*t$@G}IuaE(&NCHXzRQRs2T!!1j#JGni@sgYiX-c!_ijM59Jw^U
zI%#|obP@8qa|6d*&lEjx9WvyeH>!!T(Az$xg&>0#;jM~h9#I|NNu#t^wmA7P4n8mT
z*QIeKO3U>vy4ZdUzTo|5(y)?S)?{U@z>QWFzK8u+(zsGXs#6tkyC*1V2U!`5Wmi%t
zO}kbH+OhxW`@2)uz!ypt{ItAV`|ea{I#KZ&JhxA+=#0RZ`6%07dt)lm&W&1dR8Gv$
z>bawQe2(iPb|Uc
zOYu&7Y)L!DU6e6&}uh)|>qGF7p?=D7rm~EvlxXJ*&3o-q=
zHi#pI4J2#gNuMF0FyTqu!Rr&qM=I;K^_6ZZQvTmv<3t)OAXo~890B*rwfXZ#zTG^w_~Egz4>8isOPPU$j&iD
z8?td$Y4<0c30mTaX2;j?znY>s|>bP*t=33
zH0qJ9LjArrp6G>82{80J0A`Dm5l{2Zs?UEvU932o(1B#_6_(xElw3Y!~{t@
zWmJ2bCDNJ-@1sKJ+a0u$rZ@#9Ze_2aH4|bhB0s`l#~J{yLOt*<#Hit82rIo9btauF
zRmOL$rBxL4QFtZZX8NoOX%n5nPhzhXw$c}X-FW|%$HW7m&Qe266g)eDddjdrw^i;0
zO-xLdy!=$Ofa3N``vUcK$+KREVO5Q~lI|?6nybT21maF#b}pa%S6E}lSEM_c_j0qR
zKo(0KS8B539{Un~Ke(MvcOIrR)x_l2$Pb0M|LS7|slK21x0W=m@MyJI
z(y~D(oKisEJQZmhxKg_fE0zi#Jl>}74QW<>CDzL}@jwf{W0NIZ7-5-7ZKvsivskUL
zvI=EVMywR~yU?Pp4L6MGVxj6`+<89?U6hAWCk-R&kw&z)CC%ATW!O1KC$P8Vb$u{s
zf9FRWB!Etj{0tFkgkDG`y8IE51_tuQkG@~^2=JRz?_ZNMdnvnSv~Jw
zUrJ7uA683ms=TYVAOla2zMuLMQl%AGdUhRSL5(KdmbJjg3;okM!MjDeVxW;e
z1*>MjHaA%gOeUS`DZr}Rk#72t)kDs8xg9Fo-MROj#oFSjd*#P-V<0ETn$}JdojPbt
zl;%S_QVZ?K@%l)LL)JRJaCEl`cd$&eNenDzNHdxwO2mO8{u#x}`>vGHm>jwxxIt~x
zU*EAyFn{c1-nUV|0|grOdwK8Yke>{iX-kvq7$`hl~p2Mth(ZfLP%?7<^^2$g+J|b~?Px*?>`|H$0%Vr>po_c-0zHq;$b6yTFJz
zy@=p^#nJc+#~*_=#b5eW6fuIrAqY1`E8bI(jz1AM3I_#uUJL0hFFxIL_#3qqX`|-p#
z&=7%oYljc|?uoF^7SZo`$
z>$(KT%|9_uZh(#gYtB|hIqru?kWV+o&`FCTt&k_jy#nrtf8(%q&e>yGDsc6<;cnou
ze}sNg(NczUsVeA@TaJWwVHxK_JUxXyiXvxe{q9?CF+r;kO)|l0p%=b4d&9*YBZGxTJCk#>x=G{UB
zje+_>TrR1fnNAujjqy#l)T7<51RwhqzC7k8{Dh)Kt~peS@pVsYpMQF9Td=U#cHDAr
zE4yVe^<&(-BEJWBKZW9~I5vE_4Ey#nC!Q@XH3OZ_<(x^yY@R|hrp=FpeW~pO@Pa~A
zKCN;8$|2l}VSi-BlpD5F+B-oU72LFVR~
zYex=t^~JP%nEgwFn6OIyJJJth22@O7EH6mCq+Dgpf4r*D3YTu0&wQ-_E$am8Iwc140dC$gEKmwE*BIE5_N;hmt@s;4cd5pWS|
z#!2w!M8f-+4F9+sg8#W(8U8gA{9;%m#sdr(-NQ@&rR7g`o9CAd^k4w#gn{>R@+Axm
z-9n`={BxZIo0n4G{HHs=>|b6iaF`u46WPxTg_r&aYeauU8#xyrIpQtf7i%N>V9lL;
z^*>r6;d}Sdum2-;8)#OhP@-J7RX8)d0+Q{@JLNoUOZUNvNj6jXXGO4JR{e{(a@8gZlz0M%4BBkjOti(Bs#hr4AV;{*Sjy3nv2p3Q7*s-`)
zs(btkIp?@HhrFSA@=km!=be!Aux3VFhCfVj?GasayQk6?NIjqOl|YnSU;ani<@}F)
z`P4$Bx5TnZXZFe^&iG1vPF}I)_Rp2ex#yaDv6qHb8U6qX=t0~~?4i9itZ?!}@OQQC
zIghv0C0IX~wCZO+FTV>*fxV@Om96#U
zlH@JXf>fFJT*_bHvcwj%A~`6WPs)^}cT(&`^sIUa&-%ULe|p=c~Xm^xD5zJzn7d53iz|p3HrfE5AP1;A~Ql^Qxxv7
z#^ol#K2IEZ4P}pp>YNI2FwQbr4%Hp1-59q6-W&`i8xdbo>&VF10eg_JOTR1IM8C{h
z$AZD|H|WUS#Aw$J24`a4Ja_iIOwHF(o6K7b>^3E@bmu?ZGoWw^AN|r_p=Ys@b>|v-
zc`MD1A2gI*+DX}B*fKVe84F2|ZZM-qtABzlV;QAryX?JtO}uf*f9={t@U$;Oj#=C9
zdw-`UwHF-hjdD}ZP@Ug;#5L$58QJLerKtbfUK58F_N>@WYZQDn36zK0<&gl~d)7=xQ8^8!(0E#^HUV2aczVMG_hI#8h=c(V1+1hizu0NCbE$XjDefvH2ebA3(
zMtEvpS_H{NpBW!zl;%5}=G$tP=h*}4Sc3G@0_u%w+%>}}Pcv*akG%`ZF-Ax>2tRYZ
zweFhRKDGM7_JF5W*z9lQaESY`rhUqPSxnR1^_Rd+AVsbfPY;!0KgQJz9W(Wt}X_Qq2G
zG^-z}r2By$C**>M(f65U<;bJDdsWfjgPuF*BWDFGjytn-EHlxF{*ChJX>=90@-XgF
zj63hnxa)wcDMCfJ4ml>|KoT?V%2G(z!U|*Lk@vjztx)k_@=R8=tVK;3%XMaWcLN#rT4C*k{ENC^#dPDON9Gq)
z;p^4{H|x9Mqk9}=N?T{
zD#9orT?vOI7#gN6;htwDJ@?67i@P*$?pokh%9WvZg{6}h`v}SBHd;8CyTj>V=N%RHRqXJKKZh$CUNBrA|@9WzYkui%Z@Gb>J2
z3grGBSLO4#7QW}00pm@xQ4?}YKHN;;?IF!rE?{X>dDQ3>ZGb2_&Zhr&2
z5iHms+gi#ALvSA_n3t?~48(1mf3JVIP|Vyk5c+_DgCZ~kZ$4EFkGq0
z`~@GqR=~~X5cWc*Smp$$W=HF`zODa_O6Q=o-Mkm2TTuEemHrz_^ZTUq8lieBHsM!$9rx1v{B@qlZoMb#|j)Tp9=kM^Y-
zQQVgvXac+)fXiiGDn#Fqu@g-0YHzm%gP
zer62e*W|7BOE?;;^#E!G7`z$rL;CguUrXf-j8!M#Lqx4C}6x^?vpqg
zno+I9(M11Ip4EyLd>sae$8ptWC?`rBK$QT9MfPHBHG
z*WRBku;i}ne>4+X8Ch%o7_Q=SO#L0)joz7CqF;NBDOa8Toh7HmuV>KdE#TN-bK&&A
z+{@*<{CbAZ%Zy&r!Pf9Pf2P}#Tk4lQ{3v|VG_y-px`E6oF30Yd{3~juf&Esc;~0Ii
zmfBdsXoH$buVic!V%xhgjz|rcD`;pOEoyljGzyp6I|572O2OMZmunKd{aSJ(1#gdB
zjv#pZx~rFQO#zlsum;L4BdtN41!f-dep4
zzFNd>?Odc2u0H_&tQ9BpwQZxopI!3AQ~-U!t`u@n*cZNd#w0zB#nUY5DXQtk?B7aH
z;Y}}MNA2gye*xS1FKJ@^g68%epQ`KUl6Yt_h_~YN^ynsts*K>L;Aig#=GJ
zo?Y^D1f?UUHI*4n&o22ns_BJy+g
zrRT9ydHH#qlaIu5BaJYh|*g3s`CQtu@#uVNnY
zgx&r{Cvb?nRCE^^>24m%*1wctfOZ-Pj#M6pnyKoxA?5hI82%pkQlkop3d-s5-%KU%)oH=vm
z%pg~Xix?(w6wt~v+GguhI3UA#>0%|4Ep6&i*><=8D|=0;oR9(G}-l7J0oDDAx|47)RRe5&y!{q=ii0WWjmD;K{QH;Xj$NZ$vz
ziz5$U(K?qNniInwDFFA6Bh9(+Z0H2k)as0@I{S_R$8~Z>`H~g=2+jIuw|J~p=WTQ?){0m>RN9Er@LyMypK{Rw48V!rA`{}i>Olv
z4g#ap30=hv*-3nAKH}SR|I$@KPwa4kxV=fK6SE!ue(Jwd7w5kRy`ruawa^wszb4|o
zP>oV=dP`Zu-=FpGS^uF_rMHwl{QYPC{mg$T^_I7kJ6zt*11=W*e<-=rTT&Q~k)mY%
ze=1qtG@KyAZL^{zZ$O=f|4`>;o6w9r?53OC?w4tMR
z-UoZc2Oc1NjG->iezW_?NK4HAD^E&hf%ezqW{>6`;(tRC$CgzK&r=K`6^Y}pA
z+7}wsz3iS{nJ4l5D2#M3#zwn&HcmXPGSb;DjPRey7nXweb<{6|Xn&k=fu9%tvkp3F
zkpW7E
zqa2U)_AP%I(9JStbWeoNol@4e!03B@MSrSNwl31KHb!rRz8>8opyh^==)sV7=(I5A
z_>2lqnl}1TTX-@?(+bTd+|ISp>=dI9qlsT;2agQgGf%3b4TooWd(NDyuBAkQy>((X
z!4Gu<{l%JP2lg=LOa-ABVS0EbA@2>!g_{W|F9
zMY^CFWLyR98u)u6ECW8+_7ln&Y2=lwY1}kEv=jY9+%P
zB%frq=eogif4Q-vo5>7s89uMi&+_XLf&o?YpjC8T(VoJpn*T94F7TcQe-{3o%!Es{
za{me1iPm{f;lKE=^4~%nDyf#&ny_oYf0>O{T>X_td(}m}D|K(oHicy=I<&j+jZ4U4
zz5*|7H}avKr|V?E6SMJV*r<5wr+v|b2ySZq_b*oW!aX^=a~?fK`(fPb!8@WdZ|Z4C
z6gzQ0V+zl!JyFiOzDjLp;a6+LJDs#bR>SA&w7h8!Kc?B}*FMtW+rGl++s;*KSDWJv
zs~PF#{}Cj4xj{PdKI_mj&C-m!SfinRq&gpa+o<+;zD7GXK1Z6H%B!<5@q0?Y8?!Ys
zN0L&xN3Ig2pRgUDku+=9tY3=8T)BGc>c=}S?X6rLv-Nlbh_AT#$9iuud=u9SW380>zUPE8(XZeqq4_Xuta)@_}7?m3(n?k6wLe
zdI_qSJq^kum8&?Q$DUQ_X>t1{lsdrj7V^z@tPr-2sBf>UGKc)*PlOI^-3+e6pzmE$
zVl~dRD`zauo$JR6O5Btpu<%aF(V0G6ce%iuYG+&_*ZU~7H{_oFbdyfohn>!4hF&R{
zN#ZfQ#iO(hbh2^M(k5oTHJtD`S7KF8J5QQ|+mUu)P`N2eIfrhM=A1=3eG#(E
zb}rt2!R$a3iz3vVxoq4z>Vvnxlm^`F>1~hFTk3%+^m^X}d7Lvdl-j*ga8G~VsK*mz
zZ@Sv&RaTk_I<+zP4s=XtnU&zQf#RcZ6u(gbcMmx6I$&Pj0}H^Thq0$t!k(4s
z(Wvw2>zO~Vu9NEJfcC=nH>1y2(+67#U;3J=E
z)xcs+V_XW01w?>5RCPceSnrxE1+~IS;*sJ^tDga!IRw;ZAC;z=LH`4a<>ORh
zT(?5y;~udX+Z$5fwq;!0uSa^yvK`(oew_Cku@SqO<6tY*7?>4Z)EQ)ajeb~}*3
z`2@1ASzJA(
zrBJC0By&Vc+ct1Ch8S%JUMI=mS3eFwW+3Xs^2KTdfaOqnVX|!VqE8HXEzzB-T(fia
zJ!_2VqZ#V2@zb6@SWT>O{ADao$Jm@G^&R;CPI?FaN4t=-sL!NP
zt2}$~KV%)~akPiO;dxVK3mwrI&qg}`;5oK^VZ#`k^m!#ywPsDCj@(63=grGfZ`KZqRy>X@U;MS^1}p|9Rnqbp-dl|E{!i+v;W*ySh0S
zU(WehsqfH`-o)+FaQ4nVR}Yiq0zPu2btgJbwX*SsCdSxdf|a6i`Tfu_A**a#C%nM5K2Q>G_}mOy
zEqI63kR$cNauV3;>XRm20C2Z1V2+|WeDyQjMu#pA2Zgt_X(;I1p@8M~)}hAGQA{*+
zVdHhxX4q1VRfS0z7utq5DyaA8y
z|1^=cEng3xB8!c#WejvRy|x5zrKx$AN*-SOii49>sOM<%ICAD9@gKW#R0a%W;ttv*RlcW8&O1)f|f3YhUJ{DjzVjNBG~?j)?jPR7EX
z82@L+GD)QkrAg}=)`>+Gj9Bbq#6UMA1~p;a_X{nEGL!V_F*NF7v<$$s6Kg
z&PBYNofQkn_5;4_HX4O$gYUp8B4ZQ@>}qwC~v@Jw}k|2#W*1RA3X<*YZ?HVs4EM
zo-P*9GwC-w-WW|@FO>ItoIBruWLbIE>2m{g0&-rUk`DbJqK)!G11tkW#3ErqND9U4
z{J|+VfoJ%q&S0CaWqku8C*Q6qPNB6bl?p?1bw8|=Pi|+puTxmZD?FRz?>MeWH2&T{
zF-b`BPn7Y*RtfGz$LkuF^gbP5`?IxzF}LCTQfG}_47tb{3meWG?T_ii;4a2dc(e!F
zx#zPjJDpW_cOvNsXIrEh-At9O)hs>P&3t4R9bKUCTd((oO13secIGn2_Bu}fkeHvh
zt~Ae9%R6*>u_oK7|K_*ZR-^yy|KZZMGgbB*=8sgX0$`v-yEOBAW+(K!={egf&1gc2
zi>SYexz8?!g2Ks-;S9PKB&&j0K@$xC}
zd_osmD_y7NuAB{gIzRsOJ-cWpAjlp{p-5mmqqjpkZ(@Onrmz|x%kgXCr&a|n(1cl6zcsNE8O!%ysjaU%2K)bhFT4kqrESmM6GBq`%&0|
z+p1R9Gt@49S><1!$bFr`%BQTXd@_UO@IT4FR!6g5gLad2@%~?<-Nan{N4xdtX?3EE
zc4ehq^$Wy(LAyz4H!-&=q|Z+J#NnKev;NF_}
zc_Fjuq5BaJk|kdUx?-yo-l=urUT(q{z%v`5iLhYc-JK14vjwy!)qM9-P?dx7?WaLg
z{sER8gcSpC0Dp-MDaRAAm&o*Vf_HAUWtGA^O|bXZm#LrFxW-k
z{cANvWoPEm`AMzN=wzq$8!lE@Ncy+jwv>e*ITikFe{M$St+~*-_^|@EA&xLaD4rR@
z4yfT{fM6X5%^wq(HU02kUEcrCE&{B|?dn?mN)4od=5Z>gR=XJlr#~y**q=
z_g36Vw|2qSAS!LQUHa@IvnlP|Dc~@@f+b}~h+R2hp5IHF(+RM^Npf;w0+SC<#5F4&
zA)p~CCPWg>${8!OCR|Ww-9AHh!*T+cEx*kK><@petpq`WF3zVHjDqc=L)Z@LWxGOE
z@WMZYEdj89+vvUl$X{I8c=n7sx1d#U3-j8pJlX(Va1Cye0g|sUj5~FaCB1Rr=!M2G
z9dNoa6u4$PbmnoUKCmvKRHw69;XOP=$4gmVfhHNgbJL96zWLI+E=G>!7^$uz(sUL5
z)9*jeg{@+xv6t4taB4hUKTLY!VuTpk
z!qAwo?=sd;lBPRDd8=6d4U@A^dZH-Q;S7eorcFz0Qw;20;OGfv_++Wn0MFm;0ll+q
zh}1cXiP-=yxFIr;pvIL7GeA9muD}T}6Dys{SxvB0;P$2|gYv}6*oCmm>W3fa78slE
zA40TqOW{Suf^dNHB3OdvYV32<*lFZ6>Xx+5cJlMk@>xYY)yP#?GrY5;Qd7AC^_whn
zWQ&kNt<$?Ww)=%&YI&U6a(LH`SuSrqRPTSC?crU@Y_~P`eL@hJn@lk9QjJstQ6uPo
z`?LF7PM-fZGfjnWOH$FdoBr+1XQyOOVUsgIky0x(HX&E2b;?fAE&JR=GerK#y!VOG
ziJhdZT1Sq%FZ%;Wj;k;41GOxNvLil$e|xSaz4PnCpU}MZhAE?^S?dmF@(%LJHh9?V
z=yM?E=AM!bAE-0f>)Mq3p7rp@UVUl0Ig!rv&-G{0C!2&o4@YS_cn!EwH9z)F2yRq&
zZ*OaUqbL1gzYK7gvygL$gHK17U}hjUxektV^m+YD(=$Vf|NKnhOO0G?-E7=0eU0#V
zr05IAoS*&D^z5aojJ6aSin-OPDEHSHr0E_q_1s3s#hJ`sPtcv(r5nN+aaULL6_xvR
zaun_kIv0A~1M5`vCcbHk!pEw{Z4-C#m#3SAx&XovFE>8;u!?~wpZH=A9(pj@Bp8mU
zoG&}2)U`G5y}>45pE1UA?$w&Y>nGaU$8Dn9FvW2xJS@%F!9=e{^dxP|$a{O~R)c#p
zcstP24NbQi|MoX#t`Br#zO~}MZ)NF@(2@3()nw@DJGXI;JYr31;ngPGRunF~YFY3Q
zSr%+>jpVjlqo5BCj|<(vsHb3?j9mY#2op%!uCQA_`k~dOGaOONxKQRpcU$|B5Hwr)XxqRyS9;h|i
zuk}4pXA+o3(=%A{z$LDqn54`wS8!IJ(eLm#MxRx!`6<~}_F>1GX)|bzJkZb^{MBYT
z%!h%tZRj7FAB5!v#|lk41916q9nFtRCom@gPjEon{qyCDAq;GnqqvyEWQ`1NlP+tQ
z6Zg`wCn9kdjSAwb%fP3m8&ll&`7c{5@<)wrf*PEn{6Rp!W-+yuBo(3
zGk69%n`U`5zVYNcI{9iuMrswzr)=~c)w;LzztpPv!bY`DbX4Xlb?SIChkhKkR@v=|
z;LuecD}dH5{63tR&22w0qd;(U^>VwM^4oSMbE)I{b*Z;Zxo6f@tfp!XC`*%Z>LwEXO_qiAW4?Lzv@3jEB3;~O^!yR-veFg1i(z*(Ac?^BSERtVra3;HVs#Brr~0UKm>
zW^pESOA2dYMerbe@f?^TZ}-JXC}3=m`|DjD(AHafa;>97TkTlZJrO+q@-pVvHHf@Y
zgqtO5ChXrwPyKQK3k~VhT(Br}Y0nX#<44S_HvM2*#F^5tX0km*66$sl!2hH%I`I2j%W#gq?aQpr}D*o@^Yel@qfpa-Z@RI
zG+AJJtW_=->u`rLdtRg7hG9-|
zhIL;@ovb`VVB}e#kDj&yL;l3z)NO!vVB^_OyfrWt)1
zebAfIPdhZm2t>EO&6w`XN;!9Mb8Uz?=Bx_)E1O`S>#P#4n_K>`^t!RkTc)Mxjy`F@
z8lE7=q3y&!Q|-jT70bW##mI)lXHe_kp`F`580g)g-V=vf>D}#B+x8l@5loUcF)JGF
z78Z)bHfbE%D9&hL_2K1`-v%Z#*qi%KzF4%C$Kf9=Fpzg
zM6b$D8O9PP;3Fq@QV$Dt;U}XVoB-&ONarhn|Bd
zx#ay1eBFOUz#>`*+|=gfRHyH!o<=;0RP&DSfN|i9ndBzGH0^g^bRqAwwFh+4sSG3Z
zLQlJaAES-ST6;uj4$<=xtkc$LuigR9!oq?24u9F!{LUwceobDB!T*MweTFysC5@Ad
z%L$FM-fJa&oCl|o+-k$hD@(>tqo{K6^Lg;SySV4`Nhe{m&S>cFgKi0MFr5J5D{BSF
zPilI@PZl~LN2}^KvH#NHWFG~-I5^kb=(^C~K6>w?uoSrd;1h(&H>@20#FRp%#=_0I
z&--ht6~b43MOurf_dZpl2OMs-4y`^oWmrl?3Vjv7
z>uYCchSKSBMLAteT`L%(Z&3S0)J{|;PI#*Mr5R_e{am#Z0}?0lPLLQxm@Ec9cPSbg
zykuvP--w8PE**<|ZAx~g!mqzVr@?r!vMbBg2|dJFI1#Tv+6KCc(H|=;``m?FciAj{
z0k5Mse7CAHhiqZQ&0VV^CP}M>Kw2eNpFFp8lWs{N(b6&XL?Pn-In)&bS`M7}o&wX%
zhsk4-hi?wqdX`Z)^Ijd9gW(pj;JyEBLQT1$B2G*vhRZZDrUCsa~0&
zr+4*tMC0m+p8XO%2uwsy1%ve**w%Qo7H5*VsujI~zc}0j5*^*nPDiVghi0%j`y18g
zEXBEl$B^TL-}deU_1Wxy@$v_QZ{H*ZH4Ue|y?O|TUk&UMA9}ThEE?~;hI7~lsXjv<
zUs^0Lf7M2*ag;h0sZ-$tv#W0tWW65=iwiH)sX2BaZ;9g9W|!c%K(W?D4t+singC6j
z$9ur-;270++PBE{q1Jp%hI4%;-AHI-M9Cx(RPrMS<%9N*g2Wi!%D^*#o{f^X8j{ti
zzGEyt!j(dUjMV6FeNiJ)eS8zq6JEXoomizb($taen2IqKbP~5@&`2>e?Q~bLfx2P>
zJ84wPh(BfWlL{qYvWN$xt;phEqdEMFJ?WN+0Zcs0G
z>{T%}c7*n{`}Cwo6nWL@eWxE&QjRMBHK&h)Go<)PvacfPxZ;}$Uazp5RwV{uE*1bH
zo_BnQ$S$p`HbDv_G!C|+8e9YX?0Cv!?|Hvm2Fo)%6OZwk#dNFpT1DS%4Q;bN&;U>F
zdD0hdA0Hjjm5!VgCZW!ij@#g$LH9llzKfxeGyRUExSY1N_db!+);xU<`^cDb-Y-fk
zGL-_c{_eQ|p&
zf*ne+wq;{S*Di}^{(oyMxgV>qJ?)7S*9`DEv0CNPK8(?(y}xKu6lQz+%$CsPzF)rw
z5Pu%Lu;2To6z#)JFSE!!A%(X#eg>~K38xPheRlfG5h;lo4&buJrpz#Yfe1e;;&%Mr
z#1EcS5c!EIYC@!hor325eI5J6t%4RajauRP(++he;QyFf_y&?3I^fbQaJ__<*Sc<~
zaTRlZAN+9oX4s*xWxG1I5ZadqtLJeQiIA%A?(E@g~Qu3|RopfMU{eDOzU
z=QprJb;cW=0q~a~-{>{CV_p+Ef!)HnAup<6L>=1Jpbwfb_#GFREjo-cOkj*Z
zUJVc{Ga{)^#+UH?mJkKotw^z4hz3+ZnV?=+%TZX4KyjsZ4p>}%i;@t)zuG~=TIVy#TPIA
zsC+?h^v&rnPCtqA8kEJ#udhx*c`eFoQC{l^14r7a
zXM6H56~1IXTxeYKqu>Zxg(%6-gOBphTE{X$@AzwXKz*Buyr#wK0v|NHPE|t(Qn+dX
zHoO?fRWxM9CI3qxA84PG-c}Z%x4kRNDDa#j$?I;VXvfuepN~j>%IqkyGOw+r^^~h!
zf6xU_ffou-wxxsn)sQ^OZR{2T939;OiQiF)x_uGmhcXi9Z5A?vGYd1<-rwrT2nO%I
zAvr?v!K%vqJu{@o4C(*z$y^>Dm#P<@0EeYI;466ZumE$AEL|4~A35Y1nt!0JeB?Sm
z)vLae!+2u^AU^1dl3#42zm|5RT8kyAt$c4WaBP1L6Ya@KK>bAzfp&k0yh~L-c9#6j
z$rZXl^6G-q^D0g&Sjct-%CYV&oOI>no%1C8cy?z&qq2fVjzM3;2R&5M)hOW;qWw)PzzZ5ZvP_p>&<5p>NE{57quw_l1v4(S$DUPupjry
ztb|V;f?1bvs5dR)h(oCENoXVq7hpFf;Y2!WV+1HEr54FB#m9DokUDFrLI5opCXJytaRzEA`27l5ajS>1Tdht(kcaQY*Lq2kS#tN$S?FMw}-2uc!{F!%VzA&_16ct*z6TAPqC>
zQpS#3$EE1t8DjFG=_i6uWV>tVJZz6R^HQ~CFZh6+odKxh-J?78`%@7ojJ|0Yqkcm%
zI!F$H`3Ug#gTC9gcdl+uuJ_Bk|E}Nv_FkJ+61tdOHr8@q?!xxIbF_-dYqKp9tE!p#
z3!=&>IwCx5z!x?%SOaQ#UM>H%w>%%KlwasAZ;MmPzu+xzP|JVmEnk0^QvT20@|L@m
z@_$;`KJqi#-7cXhd4ljExW|G&`J-{)m|fAn;{m<3ZR@uxshBM)|8%{_2&#fol&I9V|Jx{vdBXeb59=T>2ZS{M9Od
z1C_sK{52xx8p`30D`c%dh(4gL^^?L|&P=lHqvwB4B3YYfeLey{z!rg#v>c<62l@-2
zZn{QKGy=;rx+B988};aC_e}c1%+Jxtw|;og
z1rOXx9D?V#q^NT84a!%SPj)Oj-`Dvi`WU3fB{+b{DIEcA<%I{9w6~SN(P}~u!JVZY_-OiDf0DkfPLr
z8psnUNkKZn0i?T5w?8)qsRGk(oHd3uF7KHbZ^+Zc&)T4wYN%S)!$?lSJn*d+G(02^
zm*~sb06Es~FUQ#ZG2^(e5LczjZr6Y(3@r_$v5?QUtNl=YKTun4YOC5f3%>6Mwe^JB
zmP0_yT8uUprF4PS{cXiiTW%V?)+DrZJ3Qk=TLwclwNU9DX|Qn5Kn>9F&+VG%8EFi`
z%I%*>YpGg=lU+mKl1Dvwv7KdLr7+=6@7J9vfN`|~BYY`+n;VJSd4Qu8_tCg+^zL0y
z6)6EV8Ae-oUzCg!U%PZ`;duGbKLWv;G}&*rzf{J9+|fxiMHrx59xkHDK?6dfCc6%zRW14hGy;R7|?1f%F~
zoLkmF(4JUF@i}&l1F))^QKGp}SgWncl3o*nU6>z8K?7Zg%LqE5`t!A>?iXcovy*Ur
z@YOG_T6;;#wqgn5>dF;%zY*4Rvh>&PKzQX~=v(+*&B7ht*ChC4DRl_K%VPOOJtF)<
z=7F8}5^m@2tJ7)}pI9}xpja^Y)>%Eu-|o4-u5^(&-M=Ro9)WSgTHI|PR-;0j`ngU+>{sdt>?S#Xm90#_XdBL`;F(j
z&1f&H^rpP7&ph9~)>d@(#+5yTzgu@w%|m?EqLICi@AkqdOxZmL-lLV!VI?SoX7BEB
z6Fzn5s)de&5zl_IrnB#5W&S%0YZgEfbdc~TG{5!OS6Rk-Xn{iK7558$@63*~uC5iF
zBX{Yr_rGla-E#$x6tsUS!@vHe0%)ni-@X!sQvWhMjIcpe%Yb&o6LnY9nt!)^ZTXk*
zevJFkxk9N-2y`qz14QnfJF5%xZn
z8#|aMKwLa!v|Fuu$kX(WZnV7)ZFOt4(njUKUg>9d4kIC+B}v_-5&<6YM={cRVVI*k
znL++=lxLBDJET(@n;OSPp@zqM>DU+AiY9(_|6ZDhGC=(ERujQE7WTl1!HwPD3yM|W
zR`l4;lb;|((^mA(+b2I5L;=L8^IN}YK!bv!t}QG&+cZ$B$Ww}6erXUby~vYld-2#H
z3O>u5x-@f8YNIEjhwWMP_xQFC(3i-zqPDFB4|qrXzAdZm6rT0a3H%;;=C-1{w>SVB
z`0o4Og{U3ej=W)zV-AzI8^Q_0lOC`Me1=bPn*?H!k}8(J>}~cpnU!O0Suw5_Lg5cUyb~#-dVh}^c>39
zZd2=5a6_ZFylu{)`XfE%>;HuEdp8ZLzu8-U)h4xmrIvP2s%1@{T8om(#Cqm5|2KnD
z13jsHarmGbB0Z^=683|{pnGh@Z_puj^0=I~qJ`)A8bh+Aw~;l_w|N%O%SDBa(Y66i
zZttoqZi}(yBdXXtMKaPp+Opm$QSL}ZcRO6&
zD4U^80;PT!r#m7^(;H429VkoXN$@-UnJ3K%Ur}n>@T=Z(kvL=2v{+b8tKZ&r)msjp
zy(#KNzb9f|d&;P*j?AVTU}PdZJ8MtD(|UAAWS$lNts=d$5yk&(`NUUo?_Aeb{_Of)
zX4XPHvc#a>SbgQ@_b6sr(b4T9;^v9b_>JP3wxWQy2bHr&*KJA}mt*9|oA;1EqN27f
z!^|_x!TW}pht&+5^i&PXS5kZZHTQoJ==tJkIm)6WeSzIkF}Sp@VSS>JUj%O!T+(iv
zxV5zlv-kIb_SO99-u%r<{tj>c&D?G#(XWoUd-vpJCr6cU&M7{ckP~hD6fqhj%+G(G
zUtLxmVJ_VVFZN7OIh!19`#IJVBd;+L<_kZH(Hoh=E?B9S_Z=X)AEeR?#lTL;u?aIm
z&*}9FXnQVS9DTwSrsWOu9zC)|i@1GuYcp$!IsU{U-KnXKh-jCSP$!0F!&@=Sz^ls;
z{xUm7vgK)C+b;^6m`FsQy}|@p!pq6qBCiD=2x_^lM6q+3+HVm;wjdLxOtAEHn6N(x
zKiHs0Fn!piy-(OKh-33om3YKzFJ^v9Jy@=-Tur^0+DNe=b*Ct@-r#fFL}fP
zX^lZE3dO(Bk9K%S{&_!+Po|wF^l{N7W{k@pp%db`mwnfx~70?)&sSe
zD+MmIM}Y2&TR(~JN?giTp5zu=e6`y3`*_$0O58>L=p!yW6DK!S3vp$<>%K2_aWls-v^of$
z^(WdIv*z=N0LcPRM%UqF2#kCZa{tK4I|k#RXs;jmE^cOyj`&yEmUvy4W;9{fz^wn3
ztsS~uuvLy_wg??M)iXZ%M{@{^G}3pip`0~@IRNg65PH{Qaa3ZEI4&qqyfZsc99tYH
z#zh5*F%yEs=*NRN>u6@gRB6t)L&xU)IEoqn<1)nI8;w(fx4|ZGJTo@$#UjKU8-)~`
z7Aee%$~TZ)WKoC($IX0>apf{`UTt58{onOE+v?O{mEaueHCn7;a==xTj}Id0UN^J
z752qc!i3%OKTzX(`u$-1Zk|8+LCCXVbLht)J&9Ns&;a77J#3ZmrAgn;E{}s=PJq4$l`ktxK23|jG2=GKgRj)jQLe+ZrtfLh2HP-_Rx|TxbbLL={>+
z_STV^X~x_IQM5+IV*FldWi|*DafNHT7~P}9e-WJ*qq$QtF(%LsxcPTw7Kp_SG2E#I
zW47o8ooEoCpDDiD6-PI(!MCoNwUU7!PA7#CCq???;-jl3vGthyndy`FD^KmI>5~&+
zx72utesVY>`%b^ZbPc8Xsoglqm%C{F+ooJ?3v7QW+X5bXV6`saYJy*H1>@=v`FyNa
zOW3+Ct9cA;ITwq}RxSC14}zX&d%zY3C0MQ2$Y1DL>Fk{<4w=D;qfoki;`fAWjDq>M
zV(@ug&#Q!Q2ww8c*62+c6bnZTYl@a<#>Qk@MqBU})D$Dn%ox*IDBji`hiF8}^gXOl
z7gKAU%J((a5y0ePNQZ8VLF+5}&ftuE>NSm%MkAt+h(ylxj-p=DH{mJhJ9ZOr()E>2
zlfcBKKWRJ#d(cyMVEzuBsHxL!(VWmlq#=fgj%=C7PeK&euDqDc9{Qg;iXgN6PFDtT
z{jHyuOgcTO%o^PIRAa;mn{~^O4vkCb@ibz&%fdh{nus~t?4
zsc}AC!0DjDPq#6Po^$aUJlFHQh2}6(q*$R%OlchMLCp9#qEGZ@!vU`b$pju8cvu3{YEUr&>6l>Gq(JYTX$=1LTCs1!
z=evl0m))*jV|N%6zAtZ0@ji-cvtl*HyrEl2blr=d6A!!P4){b)1#J=8J_ei*U})jV
zmChFfDZ;mUx~gBGWE4Nog;iA&GEvqTq<^HQgU6)c}-
zu)KDMiQaksNqEAXkF(`r?9a$WB8`x*U!JC7+>Bm4HqKJ*$2z2wbd%D3DU{c^}vmERtbxVmed`g
zUi|@aa>Fm_&0`zb`iR7c>f(d6FNpr7|Mw^qEcMr$>aD?R?@y6H?#Zjn+nKW~7vf=t
zdSC?Ix6(P{0=zRYQ*%ZimDZhScDyOA>d++EBPLzw<1AMg{=z`icB1>~jnY*+bxN_N
zY!QyZ($JvI3@)3re?+cmrW|G2G3^@REe^u8VBIucW#wg(rsnfdVONc?OSie^IOd-?jhgz
zUPx1Kk1KHZ)D@!S`En^eT&yJ`>yn_
zF)!2%7pP5fr?Bql5E@K{5Pa{yU>b{BeLi){F+NP`5q=6zrz{8jRrF2~bz`|~YgD;S
zkk&di@o62*lENilR@r+L>F#Rbxbw^;U|HqME7wGwk4A-P(v)3Oh!46l%OSJ}s4KyX
zS8kmj{<1?zX4J6>WvhjcoMl$lBK^CAN!04J50p^E?n-CX`%cDKAFN;+bth0;|7l-a{Dj)NvhgEliTg!@_!8~-sU?fohpZKgbD6c)OOW4ePZf(!G9}g;
zZLU__tb=|1M7
zwWXjzYGkqaDzj&ON`qK@8kR-pV5@777X!PQUDjgZ#UjmkbuJTZG>`A4{KM6fyW$4z
z*njNZWgVO+SFB>Vipk(N%J^FkozhjzdN^BY3r_1u-X$yDe_Pt*|R8MPVwQ$6_-YQ*M?LWT>
zlqmC&4OaPx=d{dEy80c?&qb`JNIL(MF2SBYsUEk(SVW48&+TGb)*ZZYd|j>X^rV`V
zVsR6*yHw&`8oKcgoHlc(9-o>tO^x`36CN_?mZ9@{mf%(od)syN)l-vB?_1my;im7-
zxy0yYkOE&~o`aoiMXGrFr5o|~X{@vc_k~D!YuSq2kyHAp?Bc!f(hzwGw23%s8EoQX
znd9rkk)Pk7yhPWfWmJ>HjyfU@7{euoz9XnmzRmTKeS<6Lr;vWA4xG^{mNQ)DQtSF?
zUX+&2u&
z^#iApcfJX?JNRUH_~6Un`J|mjtx|^u+zFu_vVCxEF}1YAX^#y)o5MZzswdM_M1PF7
zWv9RfpxsMnQcY*O2G=xzc@4_fbe=@pytG>1XWp{jv*qT~JNy!NavpHf@nklCZt}06
z*rW?V*jJ4eUFo6uLN2?)HAyC{cEZE=zv-n>iB9qXBm$a=Duq>B``L9dx$v{H+sNmY
zfqyh}d5^ja2e9qW`#Km0O}H$dN@k4quD<*uWoAc+iP=-io#YwGcdLe?07?3KO@Xc^
zbhk4z)$pc#O2D2u7bf|gV5Bt-OlDY1ScQlGsq!1C?fr=ZnD`#c&Gd;EUQ_q05YsfM
z)MU_Q%bY8NDPL6sbSh4I&=EJSjTgsw@UP10
z0-P5%j?H;7&@euzzBetR2Ds(`U*nw%_zNt1&+WY(crm`5IuCK{ld(hk+AHn+VR>c_
zxM6CV13L$Ms0Oxrw|8EnwY?ehX`}hv_q>Z{^Vuw_&$5^B+Qg<=x18X97u4BQsh(`h
zOal?k?WMT=E_>;hVxot7KwE%vQP+@y8&rB`
zqmMSBB*GkIx%?xYu3AvAROUaOwCXPO-YonsIWW6Hil&)|TG^KgWulC+6g@mibN_?!Pu33?%?q3hoA
zm~i9tW2>J00d?4n50r-TqqEgMs`oTDXzG6A5Mf6xRxuIbAd2*fo96*_j?dwiq3%Ac
z&>kvDI6EfSd&b1`C1xr)E8A!ZQOo`e4(iw5Ia4ve7w?Ch^Q((UMt|er8Nff?xGGN$2wsV+}_rZHF-||X+iQt
z+}D3pPb>9Q8QcfLD=hE|_1C*EEdhSYS8cn!B?%Lf9gHfOd9>l_YDfrI-!tg0_4ozq
zIkdRSOoEvK)LALxyxyoq#QIPlMCzEy=79#ZGE#t5Ai7A!02Xk&FrvVsC6zgr!x-_`
zV@pWOVw-FV)g+bG8Few8+hGqtWyT|}7;3dS^$JYR8V-9UDnzNjGF3Cp4|n;6?S=2s
z?5f&51K#`Yy3QxRwwL=dgZX*u@k4%>h*%8I8~^7v_!kQ~09<(TKlh?>af{!OE_sxJ
zC5+woRq0-Kn$3d93hj>_s>~6GT3FGT%0gy0h?XYZLDC__S(fL;GEwKe@S?i%_siH<
z(mFe+-Fb|ZXX1>ZT9#l$csG8*eJuDkuw~!@hsL>;IU_C&jFI+-a;v1==85eb>LUnE
zJi+d#b<=ls)t4zZ3bJc}Mzlya4rJd@DbTs{x|a?)d)m7%Zf!N{f(h#%
ze9-oHelYUdGT6VjEa~y4ExcmnbC9;;Uju1{4Jb$BJ-4LC+d@E@w*^p%oO(+-uUj@Jkrq)at@G8==u;+rUEz6;vPysJ))Q}8con!l
zyNm2nFx#B1>2>duyZ@=X|EabANqECs&eZ?p?0*XDe~RsYvi3iv^*?3wKP~Hjvg0W+
zh-NsZ7Si;SLMrik;W(_ps2!CGEb@&kKohJmp%hvfUx(MrRxMMN<1~v*$)L0P*J_w}
zo@&?*e@f74`65WEVNb~~eIH#nR_Os`ob6|u!7C7?fDUG}J)xBPC+68_KxgJu_+jtL
z{KWcD^5DFqCo-?l`hAEnZc*E3v=iw>Qja_-SgzOq#yXiD(X5lYEJ8)A`W<-GSWTYxupotlieC|
zQq8q4j;K+eDlF-qr;L>J!?e%G)!tKgU&90Y6FyBklmhDv+Nmloax45|q9~$(-{L?`
z(0R-!!>8vPnKSQ1{LXiSrEnXhx!H__+altcHjlK!&qyKSswQ?CRp%@Ay;5qwTaoHt$_vtVy=QqCFOT%Y&ubUjERF~
z+lu$O$=T>JzDN92C5|fUkuAp*$v(6`zHED!`GeXfkFQvzuFqYrSe!Z-6QqZ^(2!o_
z3WH9T@@`#@ND_-&vEFxK4ZQg(`KrA#?m~;A>p&MR8k?ikGJmc{{W4=M&aQH-s>trY
zv}HZJgHm0iHAyb2*H-^LEXWoa`7G@gSy
z0?YItpdlC+k$6t=6C6>)rfjl2ZfP4odt$U5{7XQ8ms#9d@j6MnOlT$Bnw?^VEdyHm
z3gd=-<3e*aNBn)7W#a3Qme14s$=B`g8;m*Ha+0r${@P%o72x0C3OtRL!@t56mmN}9
zd&QlwOAa=!M!8(b;q9$=I&{sG*lBZ?Y_N#K7qDUxB(bmH1S}TdJG2$L>kBlsI`U><
zL|i@kFTT+V32bX0KV-r!>ClV1QL}P~&~n?y*IaktPMrfu?wU2*jM}Z^&;9MWDdH=C
zV#PqnScc*k1S`t4^L=BqU)zWuM*5x#Uu-yTooV1iU>y9ApXZ3-Gx`9IXQA)1Fr)%R(fu-y%AYd(5jO^?x0noWRQ=mS_UBj@fGlBGiS{1E)t{Dn=4vhX^`
zlBLjE_zja^n2Q^6>w~odNu9F~Hv--4EDgDOw*i;#|Qf#NL(Qf19@eM{iNbpnlp0ZNgfFmm0*r!FLv8pA4tz&c-$$jO&#*R+9-#W*v&&Q0+k3&KWjmqw
z5AB*Eoxl&%HR1JdTcz(Rn9LCP1r8wH4~H;YL;sier+9BWpv9V>eHV0ObHKsO9`EV3
z!78=7^r}?a{q<^aG0GBG+UXtAgD*t1v&Fwt2dt{32)Crf-jZUyB_-pQ6#L*5l8{yi
zS7mpYrlv`4r($rvz{Fieyry%?$*6h
z9qDABQW1aJO*J(uy;;AHp4&ao*nwY4;e0gVHPWsLhgO4j5uH7p6)~?7vsz9mR!*E~
zL?77<9~nsk^(?jU^k?l}S;J?`ndky?=juy*Xhr$+kD6Q-HOT|!Euu-?}o6-ehm^;{!J2O=r)&##_(|Iwx
zB3KL(La~QKMI(N}uHj;cd$<_dG+Yd;7%q+!hGQ*9piBg;eM4P5?gKXdNijtECPHqg
zhZRxtgZMV0u}O?*3YOCW
z1dGF6!{yYB;R+ti6|~P6OeqkJh|w~$VkG&Bg+*~U{TD~LZx>+^gKvh3x8WCo-w6C}
z$8VT$yBLn&aQtq=F9JX8HNw!vLd&a7H*lK^Y_`g2^MZMc2N$)`f9PkR&+~#kX?uSm
z?d(9>sNtS+>bF51!{xO8H1*q?)6{Q~hFks#nq90Wf3ombR;K^@Ntn^V_50M@-e7tq
zJmocoPC53ms?%X>21l-WMPY)BP;xR!x7*4G>atVDt**?=
zw%n6vu<$9WoDjN)f6B9N@$1x)hL@_b2Jh&IrmJdU!5SJTEa|V|L>(p?@e9@tyJDr8
zFUI}HIaCbo2!0Ju8DU}=t%jVC%A6-W=Phi*TDuuBq9YhzA@6*+2M*oJsu9g}!*E~UhIJOAel1*oCO?T!%ocCk8Z5y_QL$Chz!N_F
zq2@zt1)e}7KF67=^}_PH(pF%{aGEo@NvEV=c@C=Yi<@>sx{r1;Tw*g-Qq
zkoK%(K>VtDLt*p^?)4{(1MDzN48<=@7}l908k>U8;ij`&D~@Oi_G-hr;B^qVm)nwi
zaW^c6h7(PV(-`(bj*DIJq0j{FSfj18&vYN+QLlv8f!!ZIi`LqoLriIC$;RsXwPfL0
z579itxUL*&$mjltt&(4l57CICUD!=4!mICFR$H8*;Fw!xoMx8jYcaSZR1DFE(kxH)
z(p&$}^Sn2g<{2I(A&as;>7DNbsyy?yj$js2D0PmSgX!Fjv1z8LHuNU){u7(B3MUh+
zH;qjhiZ7zhLel;fw_e^iTkTs3+l`^BR;JpfqE*`z`gW@tq$O
zyz-`?RdI^S4f9G)C=b|i5Py38lV_g9w>zMF)n0fVe;W(GhtI8#z0wsLFG-9OpHuG@
zzi&`w$1^`Qt;T%^-u=isAV19oXuFV-HCgi41}au+C1j2$n~aN>dCX0X<(Ww2_?j^)Y9?c_nsM_}2ZhYr%$
zyk*Jywm|a}$cfzc9sX(+n>hAZi}9~o&6GwOp%L@9{^%#J{`$Y8`sIooANaUi1bRzc(I(yaMk~*ZW3#Od>*DPf%~DFUhF0aVYMc7tZT|$?Pk#h0YpDYzG}-X^d1aXl6_)tu^Tx
zJ$EXF;Z81KsxtO#s)Q~xbY@!J8j6BYlGORbb27h%B1Npsn*K=d%$AX-I!;)<^^x`I
z3AY2|DmhAZfA!;mz4>3HA0EAzYp}85u4fjLR~@fEqgy=|Lx*-A_qLmnhWKe=d97z3
z9@|igm^Xp3nc?zGKUN;=$2giUGR1C3Qwr%0aXVW7xOQfK%PT%NsAl^9j5Yfxjh?i~
znRbtb1|sE^)&9B{A!ANAtW%zcH@U9rq1tEGezH1AyX%o%>k_lXA@I*SEFbb~KfUqk
zI0#qs+W;E^EC44!%Tc`r#XIU3@ddX!kwIQ
z<8|$3Iqfc%EYw?)yE^0wKjwusoA&L2zuQ0BKz$qxInbh8f{0CbA;!TYEVnJ6ky9UG
z6V_Fwt<%IWU59lVzZ?GSoh_jc^uVJbv)IK>qmdhJ!u&tx{>ug|c$MD&nEM4JHr9D<
zjU#jGVN(d+Y#mDR$@7Rmn~e0rGm2J5V*vgqvv~g!n0u6#Nk8O0VG@I4Y8~2oSPjI$
zA`$qyam8-fJgIhMuuO=_&4#REu$7_LBlRzNqaIkxCmw4#s=IOGv7#q2L;B1x<9)ft
z`_?Tl_z_xh2@OBOl7vPeriR}om0QoO)0M95RU&otMx3%4yRHYQV>|j!7gqTx
znMWuJnP|*|v9DoW3`DKgi#gkiX%BmSNd6Zz&`3-1
z^ry;jn6;2L2<<7azK6I~i*d0j(B!Z|FRF3jdy9JwmP>opZx+6V_MEqV1?^XyOsJW+
z&0pAf_fF!L&}h{=mm?258#+N0D-OFV4j3>C*4hkLX<%sQ&FGiwXFX}WH^=xuNvJj?
zOVS#AC4-Nivp&bl)<5FBf{kCA5Bv_}yqYZdb1BPN_#tFan>OBVH-`!#veb4_FFkWn
zFQ;r|)%{xv57Sk-b~C)0Yh9mmNj(M2Z*#2nng76QY5D)h+`GU8j-Mx{>LYd1B#WKSeGbHMS64Tu;T;+?09IoVWi%Ai~n
z70JA3-bN$44d#V3h5vV*GZWbRJip)b{y)FZ=l83R%-QGc>)LCtwf5R;t^KV+5Q*A!
ze7{T_59;)BAz5p8KVpq9L$3EcZAM#w1d)JI<%HjE
zqD!{_Y(q1Rgi%FS9>zwuRET>p~jII@!uIb16)%Ab2W+N2xW{gBR0
zzpIXrcXPCvwC7KSuKjO0
zX=f5viCw9!H~Agbdyg6`=zI-03~edwk6h6HyIXD%he>pQ1drQnoZb_UiM9dO_4=^B
zoL*Icvk;L{Ia)dXvZl|e>@(Npva}{608RfsL9XBQx!2v&L^}a4jytS0i@3Z{&#ppl
zFJStt8$=7v`1zJ>jlmzr85;JZVU@~FH7<2Eclq&c%*Y)|H+t4>ZKhhK^@^T*-3xEY
zWeEfPMqDd4HB`LTDI%!$Ajh**hNvEFI@aH>CdSzlwA)(W
zmS2vrbvbM`Uqp;0o5GS^sDh;hp9pWBykL4OdqR4CxN&#(O~i6@wU+F4F~T#akOixNYA)2bsS1I(ONz-DY8?5e=+c(1$8C@
z;}+K7?n=TuSVhDELJO;1PvB%#tcvYzLh4Q{v}KDJmx;cLxf1N%3$YhLEf*GMQSDMq
z7d~#uc*JL4h<4j=^Sa-!jj%m_0AnKm&giG$*|!S!L@ZqY@Nm%957Ui9#G-vzK_6m7
z^&fvwY@{AuZ7PnteLW+%T~u*0^?LhBxqs)YFkfZG$-n&37c{aKBPp+(@ttuf%5P7*
zTY+dM@Mo&2NtLw{WOb|8@+y7cP1VMByvmPFy?L+uybDm}yzUq9Ys2q(*p{jkNPk9H
z)=DqAkg=69fh>S53kf61mWePR=%yRh-)3>{f
z^rsq2VLwh6w+gpFm^odgJoi^mhJoWkpVs)yf87sboQh4E=|11!@2fP=QlHw=HrXpr
z9%Y0L&@7kM>l$i*f!Q*x3DUj3-3^@JeyYJuuU(rM^?-J0{vKriB-E2v
z(_`gjh
z|bfrGwmo*-_dSq7s$rqY35?8^M#KhmWXlP-D2GC
za!-fATgv{4xLwqv2)bjPkf7nsmUo(%7VAjhS*W-Ev9cM!13NHuRzO<011I&4D_t1H
znb$&kp&T8zZFX@X@JR=Ek}&}|^9{-W8RSO}I;`wt{(|Jur`^Mi?GGs9^C9`$$dc)&
zE*Jgzn2~ZkjvSfCTXUShI_>LH8^O^pr*ZLQy_WC=;@P;%*OD{_U99{39c|@sW2r6m
z+Qo8zjZ|MNW)ROKDGQXG&*G`CgtLR}JMFOY{U`!&MFph$!$i}axi=JoCUlhk!F;t|
zH&6qOvRdE$GAjUW!6|2e{-GOcoMBgzCI)(H=8D1E&)qsO{gC{WJ1f0jelqvf)fc_A
zu^sqqw;RmTjn=_s4KP4K7yu2|?SRVPjA5dmH&ZW(?+_V6$?Qrw};W;I>W>{&fzHLPY&s+lqc|4yr+q0q42S-q|6tWV|-(~3*USAnAY
zh&4SfIGT8+Whq5Q;yFvMrkl)Z!og{X-U6>1d#x4lEy05vD$62@nRN3H{mL8azCT!N
zKGl431lZwdP!n&(?%aj@s@iEDI2B8~D(i%PTsO1x7
z`yHCp1iS6<=^`FYkjs|fw(w&o|EZDUSk8S!&g;=N-4N#C-Y2<#zf$eI*+Zx7H7fO(
z^N8@*(bG=*`^Kyr>IJU0I|`zHG^WRXdctL`Ii}Gsh0oKjVjq<%uG|e;e!rA@c60)~
zi^-QFtdej>01lVgoVg7O-)Oaj-N2J$8uoZrso47wYt1H2SWdV&BwxSWrp`8DJ}%Rk
z-i`Cow^dg2W{t(;VqD445NGa9Bl#7Ax=HKAakHtTy81x>Fj3z=Urjt0!Da9>z&p44|!v9@0p*3mpG
zH{){e3fNXPLL#Sm-)eT*Ys$nS;>^bK8}d4rcT%*@%WPcY$b|0_{8A-g>-HWcd9up^
zK#Rfpq-B`qcGtbIK&Y@<7F<<${ec7M&W4{EbzjPwIW4vhnM>~diy8Fo5H)7dXk}}*!_JTvWU)Y+F7ZjzOkOXT?q7<#Qkladf;Ym96
zY8;cz5*L5wV2kejbr&F=N`Os=IWf4d9hNnRjgksP};5@_7+_-7@m{s725~n;5O1p&@ckhkEOP91T(C&k7@Q=?oVZ
zSW5rw>z*w*nEouZs*=89In-g@L-bqJxmH(Vj|C3uuk50AF{HUgzM!tHe(g-I8N4Qi1
zu+oU7m?t?JXHE@#EYxiGqN=)Xv63QK=gFr~eho+raf8A>48D_}!AmpNS~DSV)zVK+
z{~73_KfOu+WrkagUnZx<*1(v*>>je^}4`1|{N
zz*T5Bvxj6$vID|RTR-c
zTXXxpqD$Zqs!SbLF#6)%@j`Qt#TLZ?CFKKGH&ra%{B5Q#Or)rPX#S5bMoBHEU)H_~2){e1EOho%cl6o>5f*5^G!&mr-zf<_O4
zG!z^>1p0x{F(L6uz|}bH%qJ&zitnu=k2`OD$>?|E9GcMJkofR?sRZ&)9u*RgH7?~X
z85tH|3+pY+PyL0YFjIKJP~I=Ukz7R4ld$4Cdb8@sWTt-Sa&6tbIc>HhcfzEc6Q#$t
z9IdUdt2=t=MD3aV=c+GNe!q7}wMD}}81tfXSj19o{Hp<9`CHrV=bA@KnLrJ@Ou)GjAxhQ`Bj<5~e4fNQ@ux*@*C@)k)I;u}cZKr$e-}(gJV2
zJH{d6&ai@zc&R^wj+!g9XK+J=CBIPlM&hWomgkHi=<_QHhsPFq)&|~^TdBJ1&1!s-
zi)}e`O5HuwkM^1GE?nC_nQqfh|#Af3-IbUVx5FXs}kfGT~n*vsA^W|d!4pVp%|F0ThfG#)jBo+_
zp_gvK{LhltY7o|eN=56m1ep3Ntv%3$3tggttCjGxg?^=;b#bUV^OgW@C+cH(4y{Ta
zqdC7v(01X<@-3r)=^YT8OZs{gUuhIAUquw*+i<>s1h&$d3tHR{
zqHw^oPo^Iw558*(mPYEG>`omT9~6vHE3uw6@0w!}VI1@TBTr~>*fgrmVPk%YHhmFk
zd5{nC&0IU+Q@dzWcur|fwrN9Tna$FL?+|UeHvp?XGsRB=a?iV$a%~ss
z%xU+{6p8f|0g`OQBbP+m6_pCa3Z3-`@V1+PnDV4)_PX=l8H$}g@r?`Vj`_H`aY27}
ze4nM4Hkj@YaA+$)L$lc^;3nv{@j_Tc&Vq}j=BxYC_wO|OW}&O@kT+}c3`$9K2HqK=
zuLlj6znUKMW*J{g_NR0^MWkO1O7fNMA)MHZIS73v$@fO=h3_x>zJ?-xmW4CvLzl3&
z9Ml9XKo4;v(|_+_mJpHC9X;H9o$4SfWm7QfpXN`A0_uMeHaTs+8ZG`5eVsg&EBWiV
zOOz2g{FPF3!M^lE(9Zk?DooS*^|XYE{&q{AYg@BB{r+~{&$j(~VG>u8nc7>n@(G>Q
z%OB%Z-rFI1p%`h~BGSn~RvJvq?JX>{+(6qTOlG$l(dzsH_G4@;zpk
z9;)4+Q@5qIuKH+YT*4r6kUiS=QNA~dMLm7kkB7S&fKQS4<6+q1+Fa~$17ZKJM;!e=
zpiX_glPCA?Q7Hs6Rjn8(mf9_ImH2W9G;uAhg2nU7ji@5^^_b(IE%EM%=igM2;+orHefj9OcJ7qOa+biGj&MN5=;2vBd
zsEvIl?G_EpxF73j*897tu8Zo}}K7E*mrJvM&
z>zDWG_i<ufY=E*QToOs}-uJPEz$kivj@?q^T)$44;&9Mu-yqwQOZp$^>$bGhsy^8dNt7Q_9c{L#nwYnw`GcKi9+H7x
zc|*0lQXkrf(?lN!2ND$@*=t
zA*TM2Z40CuDrHHBbSH=cVjp|}7PAV2*as2%cpecOlW`VUeyDnhn_s^fj=
z=m;BsK(AD(m^T_J`s;g=wbXTyHtk`{R8c{i
zXw+~kq=J1%<*8%@ZYf#6F52XILu{t!bH&l7i{*o7hn-D4HU6mjoUCV=R3A;Vx@3?Y
z9tfQ*If22z^`P4wVB7ZscV(y9vP#nl^BvSJJw2TpVNbZ1A_O8b{L4*hOTb_azFRdN
zECKBTk*6Kb<)&e-wN`VS>XPPSE~IAc=u|4JIpxpvMx>D^;8l{^gWXBbT|rDnHPw!2
zyZ90XV-?acqpnPT1m<2v-#l+M{hpX}f;e4cOL=6(+k|cWh`BDQ<=8Kvu?L0)mkfUHG<`9ZPfQoh9#s?WOzF9Vb3JAB
zEJb|ylIQLBb|F_LXBs0#oaj{vtHKP#vI8cp&%M11_>g-Wn#G9Rk8()M$4jTW*gcnd|071
z1BUIdvTo^?sZEMjOy*1`zyvz!oCX#NJQ#I%r%9J?jZ0A_=19;f6AEqIl-zq0Eb1oE
zxJ#;wwvCE>Rcj5rRKruo)90n~zwZPj(vw$t`M;dX)7RH=(_KNi3|ZD^!FQe&+PheF
zIIrhT2P8h>rz5=&JY`(&)fv|v(WOsJhp+E%4GJYNMbzldLf^q%%t4Rrw-mf)s%A>=
zM#W{!woC_z6L?GNQ1%LCfLo#x#&geS({gz&36_70_rxCn+A?jxGXw*DGYAaZ)+G##~9raIWi_4se
zFj>mK4*8RiKSh^*^*s8RioD~ftVgB2TZc7~*&QopjebBMrEd5qptcvrwylYmYC@SY
z@|s{OswOG{E~6XKwBW-s3I=!1weO;P&gMZ}0ZeYt3_COY1~}
zr3^{Z)JB4S5bb!%Xn}GA{nH@@SQ-;_>DdXKL^0wNyFH*4i!`0EU!rwC9AgSYUi1GR
zmJGWPnh6%z9C#W1?`FK$Rd?3HG#zxqLAip!
zWrm3f+1n`Z`->3`ljiRkUHUrIkY(f(E=sh3DR)CI&w55@+rdr!Dzf1wj`caz5=U%@g3aSb|@5Z%~EE>R)yv@8G25RaLr)4#@JwvFnxx
z#ATzOS^Y4Ezhwej>-K?m1Ya0LGDKEjnH^(@NpM--*McLu2W2PBz$yZtWIJYh+Vj6r
zAKIhT>+ZwU*Fgc5gQe9(Jh}S;l#OQTXw!fdf(T6V3i)XF6<7Pir2BV>nlCvsq^>V}
z#~+K`ps}<&&Ukow)-+qq(^OKl&)}#z9W;@!w}*EUAqSvL{5Bg6*B)O$==2fBu6w3-woN)iQj~hr9Rc+j6}h
zmkFI}9Q;Z8DD~U=@cJ_1iple#cZFnBKM(s=g+bMCsQv?$%CwL1@+ZCIvXV&;%>ynI#>H3DSf+
z0cqgeDKczuwi#SMZf0=aIFc?%mM7TYc8ZL|{fIO*PiK@)hD9?Y4bMlIoyJ++e}Ufy
z<AJcdL!VDqg~`>7E?zown~|j!SyacjfQF7P)3k#+umT*tcUv
z&D+4P)_3`McdzT)`|b`a^2oQaksXYDHc$RsB67veo&qz6)yHZ$^yAtUn8Ol|8$Uj1UHaUPl
ziGJtYZ@DWDgF&}W_jCh&7L>Rm*U69?=?l6(th{mHDB_zH$mF3KUNC!9U720z63$37B%im)mT1xT$R(dGd2;EVrI;7(;0j59q{h4iklk6t;&Zu^
za!=$W<{TAOr#E)sRiGb@=Rcv|pU1tSt#Y2iM57n!I#$Tvn}2CXb~(mR}EXB5YZ2QibI(0UEc
zx^I5>78~tS+Oi^7)w)h-jZn$V2}I$qxnl54^onA^Itx!q)an|j)h-v|F=ijK6>KTyBMawqV`r?u2%+&|84DRLb(c^=ku
zH?_q-8_5qOr^qx(J$KnK`OFpeja5p-5+sU^F;73d^2vfak!~Fb?pSP`m;$Qudebc$
z528(l%whxBa6|~9vo4JD(@w)n&C&5LXyRg~DTZ<8Z0N>K52Kz!%+$diRgkvEfc`vi
zQz79CV194BzU-t#5ec%m4{r|QHqC>KhFi@EdiN%HbT^y5c|&%}X&L^xKKRRXsNAfX
zhf^+;SN7A)qa5&IpWCg1Hx*a3&EfkpXTj{Y)|&oP%ISM8t8o({N(0*SD2gJl)tB_+
zEWB1710Ok19?VNSW|x)A=u>tg(NCOtW)STV<4;YH&##wg_7oANv0T5!#6-DW
z^So92#6((IUuX5++xjVyepD>T|
zeAnRb7kpMi|A3u$JLa+6zD4!4>7gwy!{5u8Wy)dV2r9eb2snh0aDx)fT0z`fwfbJ9};P0-xVu|h#VHlzTYsqhbWeC78daV5y!uhW<%jQG!{JH3L!V}z7gNRh|h_M
z(uglS@6ZH-&M1)&>tIIH9kKzZT8}qb+P7nJZ-^4@`iY)p+9FfIggJ<<#)|gyiQo?>
z?{)58p)X0`z@HJFmM~?x7y4gg(LuQmO~&0=dky$S<72lF#S?oA|IWg1w?TZxn|Cg&
zY8S0V-t;wi{ODt2%DF3)CQBY!S`$>ZIXa`dPW0%E*hRZZC$!Ro)%ZjAi9H2u
zNj2;$nHB#)1(e>r$a<;)t95Q>9QkZ`XC)^%wVRAWet%e)4dfiQxamtYTfhsJ9~qS&
zs50c*P)~1Fc>dYg^nI3`T*X;4^_RGLYb=t^X52#md%D@P_T=v-mp5;P_iGpB|N1@-
zH5Re4{yUHAc;3&Wru@mHF2wz79#zqXM@=3Ub4KP2f$w7FJPlu9o;O=M!vnvAO6BJ|
zcVoZs78?s{sBQduW#|%)Z1B*tj3ceN5Bx+l-mbVA}cnDxBad*h+=
z3OWg&2ymgCoVkmKDYvQEA)|%ghBax8mhV36{^!(V
z^v?TZ0AnscUf|LhY2Ix{ZVn6=&cDa(0
zLbE_JoGf21(bR&Htn&U$G&mD#ri#4=ex^6J_!Q8Z+UyT|GVei
z@0$v5h6a)4z(Otr*NUVHQs0<_;VlG)xF!3K>SYmmuJjQRGQ{)xl=wBFOH>5hQi0nVOS@@riV4^I)}
zX?~omx4;&#FUpfl4!?BBAYZTOypPVHaB^KB$Dx?Xc1-i;y`GnzvcN?pse~bSD^_ZF
zVYgVSBc#SZ+pkHhlHwytX2E-*YaBCrI;KGq-5pOaw=2#dmufZcN`6`o3Yk
zVh5tF$&dXVvd!wP=pfa9(jfB*$X^#;xT!O48y!-mGg>t8MEgJkoeAzHqr3+xuOuH_c;?1m
z{on-6&6dxPd|eJ7n%_p2ize*5E-buElzPUWx^~j0ePm0mvYVCQTKWz*R8J*|@uKFb
zLzczg`{Gi{^Q}ukU$UN;v>cGC=d6<`tOGKlL}S^Gk^a>oNrKlK?iS%htynrqr7toy
z@moClXL`q|e~-@A5}jqU%+RxD_595)^`D?f7Tbw#cyQ0h9_cc4BL~}@O*TGr*{7pe
zBiM7-V9zmBPS+GUY&Atl8>wfm6Iglpr{C0XK4+#kIE8)>)=l{prVx{UOW{1k8~d*S
z_j6y#Jbfyf5Sd`cO~tuvfjB+YVI`Lx3`+B
z7?vsRt*RcuEMTU~Z&E4!2V3W9tFTX!te(7C&F6l@`8m-_lC(*}CP}-@Hpu>^z5ihu
z8{_8Vh8t7CzR3O2wc&>f;w_b*!P>Le2IvKqH&p>fI-d#(@LurlZk0kw_DswP3doMf
zjcONGp1S`_baiBbQsWEVE+)bl53pWp(9N&AUc@Qa<_
z_%jr%q1HVW)~!qCLBls6`-}NPyMu^@cyQk4MA`?@ei1vx;In3WLhN9~)StOp+S|{#
z84N2m#JKG%kbkR_w;K_E=3U5hJ7gK0-pWw!crx|$Uh~vA+~6IUKAf~6&|y&bO7Ml98DF@{@Y0}rAq@(dvLqrbc`b;W${_97Nw}t#C=XFVA;|Z!mRufDC
zzcamIf4Jv!yX&a=H@sO?xYz7CsQGPbToI(wkC9_$j&J;sH`}o+cV4V8=mADM!G#yH
z+!%jJcNgt(-aj90>Weauy-$z?1V5nNSrSGbg&WzHp~q&{!$Up33k^t+Vk+9YwhJY*
z&g}?FiZ*d{2FoVTn6?{{0=U{7SfLb5Mf>kp%{WaxP6QTE`uvd@*SuNlKSV_A8m2%b
zrxxXw+!p25nikK4Cz~A_wZiau4I3i5%uKO(pF^!yIr$&hp?!wWswKG*bpOrh!u)-w
zpf{$~s;Iu+FB!2KTrc4?C07HFnF88b-4PL=OS3qm#2n?)WGQ&_Mr(u7)W^RTy;<*U
zzFH1){QuN{0+;=}dhY|34_5cw9|lSgQ5RVseRR;VCr=DHHSA3M*~D{o?xTB8RGz6m
zxBpV@_lJJ0`?dbJqqmOTInjKIZr@pbrf^Yni?uXtigKfZ@k)KkR94uDW7g8Wnfj72
zmeDtKpi7aJ*S9v(?N9`>W`$sVgIOM&rjkpQKGD_M+@jQ5
z(ye+WQ%1(Z-}(*2^WMwJ-!B=QE8bv+@^_fC#ID8qB!^yJpy_N+atQz~?^#j(1I
zD%Z}{Df^xjZ%f`N#AW@v#j%yp_`ONo;$jV?tPLd1D7V+V>6~w8t32I*#(LiE%^LMV
zHuMR9jTGq6z`v(yKI`kfdY-s8Zn#=N@jg7$@7#4!Pd4Q&z+QSmf81FgQd64qq-~{6)
zxJN1sc4DC_hIs#nzILpuKP}8G)s1yr98Yxaz
zaf|tz%6?TXG*0I{_)}L~!^IY{4kN2n_N&BudYg^6wwC34c$Ksy$kxk-BM
zrEikv*uQ&`Pm-RmF0*4UvOfA!xha9oa8nMFg}6lMyq7LrU`1RJp=k~aw{r)D+&OH@
zd*S)rmwjn_(r$SuP^~X{545@+?n+C{p8~r@TZ_IFHUzkl!C=Q;5ZYgTX&4+Cg!I^7Tq#4lnRE$js#Auh>^l`}(Qai_`=UZCgJ7+c<-#=
z1|8a5dTQRv$8UgiH?|g5?$LIV{3cJ12%>vWCWnTIQrZ}q#3*g-6(-tEc;B~G(hr*?
zTP-b*vzt;8?T75zy!As?ie`#HBD((7SO;)MvfNEGk5=5*5W1lW_Mw$9yff`OmTV>feGu
zF7f(J)t&x_Ev-xAsU`PA_qRlm7rXBl7HAdZXHU>1tqsBRzn=q#CB2)Z7)hs9-{;c|
zI_CVLdBWBDjH{gE?KH=eCwIJ!6aIgG(k9O?EY`N06*RXY(%g3U@a8oqX=byfnYH_7
zmfro-dF9rO#=LTW&TISDdF6cb+W5kMpVuAF`{$KwJFhDWgZ~%v%1)VOXsc;n8RnJ!
z%Xtlu=5=jaI}UKTpt>L0G_Sj)dHurM25+c-Xdfk#^95;4Gj@`rZUIkfIaH!
z-`40$KgV5^`(dkf3U>?r!1N#d&h#GzaP1F^h>UU*8Wh}@C9i|z#^+to*C4{pe1X59
z7#T)?cZc~$wbPi1+fHznhnwQ51VOp}S(iv9rXikwy+VwjzfVN?OP~eMR_V4}p(}a>
z3OA&X<^)e~1>zQgpo-vqq-D;;eM885<$slzI38K|`SX)5pP*D`qrEKxHCIQ+Y0Zua
zmpKbGmF>;=tLDwPuO}O^EF`U%ILVv0qc2(8I5hPNJwtSVbr<*^^QNmNL)V*Z%1R-p
zE9`f<8hutZ6V;y8u4a9fnh}I?%cG>7qMFF#Q%v*bHHK1MspWF*Jl@pzqBkR5^rj1P
z@n|uxry!=V1uow_KZ<)dFk(b^XvtiTzu)0j8x1?3xtvZZ=si5#ay7;wu(F~awtb^#
z622hEkOKJ`(Unz}AGb2n83ytwS5j8EjCTAb!UL(S%OdIfuQk$lvYDV9h!C+6d_}2*
zT0zjLTVm!afiYj^?8HeFZzntseUL*u2*Umtj01Z5sj?1JvS>^$k^BWq#o8RY8?MTN
z{9Wk=JIX70U`_WXvj=wL#)Mo(@`0nP4zwg}}=taN+
z|F;aZry1%?ndYHAb%MWzH_;wn;LrIM+EcCbf6GLB$_>76;yY+hvE3#2n$Jdi+!N)#
zlojo9PfO*n{&@ZcK+@Q_Foxz+qXC!F4A*CYUu!(;8k%XAgzlR_l*4iBP4Xy9
z$_}+Fjv1|6RiQD*05z5B)0>Eet_jtb+z1Ua%I%8pdW}&F5pOtjr%~rtZmSGcZdUcS
zZjS4%++yo(-BQ_Gxm6Wr-5M9B4^wdgl}VMs`&0IJJCuHiq8rj`wqF63yzTjE>+imi
ztnwOX%}H|+WrqdeTgAiHEiK+#;Ejn#U;3&;g{Cg7M?(x*+G#YOBKG~2X_NKgx5Cn6
z5i2}QANpBn@i1X^Kg2{3HN|@aAUR5T@rLq?n&?9Lt)E6h_jS9>mJpZOx#$Pzy?!sV
zW%_%v+-s}{O%00^j(28$A2YK1B#k;WUqsu
z(v1zFl+%iwH@+~?Mk#f!@9*5+S#q#S{XXgjalfe
zs{|Z-r{k}!w{AaTJNHhf7;i-a7({sdncVyxw)nj
zd_X#dVAq1aC+LhHf{PV09ql%34V^k0uaTxV^z2@pae2Jn2G2m_MwKM$P=?HHclD
z|JRX6DO*QgwH2P#JiLeN7p{c&@Si0`lw6osCeARog<5MleiJsLrjOR4R>8Bqv(`cW5{(@%%X%Y0LyQ+$Zl3|LpDPAN_CJVl!D94O;T05B0Yb(7g6S}|8<@xcWIrks_ouT_w-f__eVEC9J$}fYg`(G
z1i_WK;ZLSG)ccu@h`A~M){(uiPe&F-YseucK)-4Fz`slL+YnE!oW2(;xr23cf{zM_
zA0ge|dfe`(5+5TSWIev!PbEG<6VrTNO57dcR3
zZ-dHftgD7Zt>07Rv~M>KS!)O^gALJtaQc!&j{7Ip;-n=Y__V2i+8H)+oM+CDclxJR
zlrKoV22V?4(`i>i>H+A066?thPsT#Jr@{|KSQ$nsCn64rG9X~ck}nahW9QPyWo34U
z3RojU&=v;>s$d6J2M8Jk$_)s%Q}KQX))wZE12iyVedt+sY}}Isw~}uG#jqlZMDP<+
z_Omm6$&btmNb5uI{1e}qFljUkD0U8bl5#6f_RPsCxGnNUOK_8l{20QI!UNy-cEH~P
zQUZeE$*MkqJ>a?SSAH|EIylUH$-Ks`bIW){aEUe_mEPQQz2=h%{@przotEqL*U(z0
zzm@-aozML6f4-kBm;Swe64i2TMI^c!jhm=L4B(6S0DUQ9j%l}^HAQ)ilj9-JeoFW8
z`so_cvGKJ;$%s7ZPlvU^f%)Hg5Vg1nahLy;J7)RvlH36<
z8#=i?wLc5ACJ<+iz0OgoGW+f$Xm3rK2wy0)F$!($Xw!yx*c*C5>u-ao|4K*OHtO57
zQFRpk(fpMP$v(V@Gx{!3f5f?6RVI@B&=FF=^gt`a
z0YU7KD6DSoc7Ub69}gL7*eTJxs(>A+!3B4Tk}=d#bds2#HD>Tvi|ff({=pVpC!Ar
zmJIDj?G1&ksB9k+X`?va6vNw_+~H1y-J87PPMHmQ#^j!*r6TSda}PN`xT;jd8~6Hi
zVuENId{G`Vf7WX>hK0e?1(s0mJ=Y>^Qsk554vi?4JY>D$i7cNsg5<`qL<3(Uc^=qJ
z_JmB|PPFPY_(4y(+=`#6+@7^MeWyH$dod60TQrOi`&<
zbI`pTyQd&htfX~fvr;YNN`k3W5@5rJ0pGiJ4j2Pn5Oh;4Z=5B)q=VJWNqp2EuZK3@
zY97k*@dFSSoSw7E5=(DnddNgpa|P$nPC0;75?}
z86_t}?|E9Xtb_9hyb`4#^kYu7hY3BqvM1LI+I~t$heA%s
z4Oa>sB9($tuXNUElm>Hy(m{K7+;Hb8LUh$dw;1j=vEMd27KJGti~A{s#VDl?hm?^tc&boIL>Y|OT4`&$lt1@T3o;$`FVm(Ur`i)#A=iL8;Qti+yUSx*h
zZz`JCY*cpU4DsJ9-&vzqsW@jfo>p%}EPq4IC1vw!J&zI9G$`LG+{j;M&4nA)hzXy(
zVh`c>M?V{$$YZn?+R`23U3QZ;F?IJA5t>T(^HmW`vP~W(|Dz0Dtdpp`SL#Gqb0&BA
zlIn^4Au~0zy!-50MDvvMm>#b?k#nx}?3Ob}kDWMrrv6;rr9{<#0w>W}RDo>(Ux
zu}_Da9GZS-e+xqZ+5p3D81sOtzxIVOTXisYZ%V#}D*I1-~e?2llHj
za)j-YL`jllrYuGJrAw>1J#;3MRhF!V4wj52wV(-ATdWQEovgOxGz3BR8v#wx3w(Re
zL+kER{mbJAOHr`+IB@iT1R(z1$9v?Fh$C?qGolpSN}ir_A|*cUv$XI@t0$?Sy)|Nb
z(ut(_k)Ms!0$ylAmLzbPa8~Nr#i|`GthiMlDacPVc_Hfr8$Fff=4i`?*Lk&E?w+UUsQ&{atxnI
zR#C0kuc%cVQq*OpS!(+to+Rauv;iZMQGS?3-A6-jXjIT8N7WA%5b25H3<4fm7e+X=
z9M>BuaE2^4LI}*3QlJc3p@{@BuLob)%qw`qyx;qJJPG*mGpB#A6S`^SGz&gTQI4~OyYN1cAvq4?Gt5qfH?N#dMLPPmRA^e|^aP|I
zpOLx&@^<)9|BmHeilw3;piEku1UIn@JnW;AAG37Gms+HVPLPNm0{kNhX5KACD_3rp
z>ooPi{0?Zl10V`92M|Vt1LY`j^P_-*LWz699k^SjRJ7d4#ok@jD3|8DVf{QzF%2%<
z_0#{V?!bqBrqoPHa*4@Di~yA?cldBt`1PnG(Xh212wu9}6#k9+
zWY}?>TvWDV1<{e?k66Z(jMsu+3j78{k8?jrty7Aq#*WZ|jMhiEcukMKP7KBQ#YL5%
zp2C&p(rOdcq9(2D#+BbUdx~nLl{Oe-Lk^ygTMoJOu^$Iwv^3|lsk|>L=hr-9l1Utg
zAn`Si+~X+s=!Stzp8GEzv5YTC>@D>wM2+&90saxogpznU
z_bTMh>fq14igHh&+$%2<94G>|R&SYDf)f>rL?41Ea+7<=qo?N!fm9N$z?TKGM%0er
zfsAAgjK4Sfp9pzE;_6-EHwIo)Tg{j`ehm4&oY%LbG{@QFH%d=KIeiel$>uiV7ww-O
z$atD}oXrjG4UGMpzb>?N0dfm=>Demai&oATjC>pVgNhGolkYNQ8suAre8HN5tUu}t
zMLxd&K*pK73n&u2K
zBv9KY;ebCPTdZPA-yD=`POpT1u@NzCbM*q?k~#%=Ctk-L0wQ9)%_YpEbrvpik$`tk
ztHv*p@!j@_`VQ9s#gaFCv!V_cf9YdMDG6_dw%CMR?J;*z##!>Hf|2X%J{V89p!q~2
zsC#oyF>5vP2@zc4WV7eNThbb!dBJzS>JDL^_ltq-QJN`~PV3{)j0te4ALoGI;Y!Gv
zqJ~#VoN8^3k5f_JG2q&!dw}O>mKCrhQfH~N$x~t0jyLFeKrlT=O|}GSCF+P#ga2Qc
zMwT6$y<~Iobpu&ORCy@E;c?s}sZ|`ud#&oKhvFStx@slrg*G_Et((f3zD$ltS(_4=
zb|+yZC=|^Ddfx*0Oup!&kBFZd<$giH+V;*W->T#*c<-!U-^w|~PNzYou&UXSMe-X&
z^NOPQigvd7JXV?7%Q{+pUo?Q{v(&p?-v~TbD;w?qqD6aY)Z-1`%8}|n{*`*Z;UqW)
zJmjeV+rRPE(hl{HcQrBiOXj8s>QKdiVDGHp(ehVQdm1JBo8oD&ZOryje4?Et<4ma`
zeu{q+>9Gl^i1sRt7jZ$OO2(w69^dV2;}X)z&!rysaaqXTQ6;0NrGD-EE`no}jGB@9
zwePzKj#4u6wbWGqcW|7Nq}i#dZMbyFhy|%*eBVvC@jY>9>KK3hzaX73Cbhs{{tu*w
zKb>0O`_5lO+B`CKmH+#9NXO4jUFHA&BhseS)Gog7d^pl^Q&PM5zc(WtJ2*9DcekOg
z31j1-pQ)tC33Toy*kD4c%TrWM2RBm6-Lrr&O
zZ4UXz3=*?Va!f7KNJZN}vjabeZ*W^yY84dm%n`U_;Zac=|DVh|Yt|DEJ_2hQ_=8m5
zK`1q9n}P5yitx
zQaf9KrJ1gqJ~I0O{eV>u=p%Y})j#}rSAF=y6VHGAg;yiuK3;s-@E7|HgwTH
z{7ILH6HitS*_##6Id+vMM5F%*tM;KA&83Tlj+_=!UkwOGbr+_rdIBrEFT11}rv4hY
zpO>oX=Is#8D&Et}dpE|S`-ej{?w1(rGw+7iJ5;d|F~YU9@H&S|=oPbX{NR|YyRL>G
za;Thr>5ibZFJrV7yJC`JW{2+|G|Hj6{grz77V~P;u+*{RFO7d=f@`62Sa`KVrAvr;
zYRNFiqS4Qlu5hdz{am<8^zuzG$f&p?prxW=LwwS*_W6j
z&BY9F|I8dcu5dz+CphO%k8lp%e6-V-3C|v9&Z|XCNGs$FNnf!Oh0YhNm}A^D&hW}V
zIK$NeobcdgX0SLp=Yjv=h7>O{JO5tA3@^XMoCo@IHn{?ckgf`${Gi^K?qaE`OnvA-M73Bs@F(K*DG-@*ys!iRIgY36+KBj)^R1m}3}
zb>E&bL28%U^QNtJ}G2Xc^Er_!1XcwA19g
zoX;6XASZee?wC~M)L8L8akb!R;2Z@poONRzb9~#6IZmHMTdy!--B#4p3nHIcFxmzw#RAoc0wHddy>nx5_YPw2`roIWHHZ%xbRZ8tRYX
z)#ZTB4BCCN50@P+8s>0T+Bm1!pEGD3Y;T;f25@&g!G#w&PQzO07$ANb`_i80OS2dQr`@JKgb!bW5z76(B73xEO>B@a$^TzLpAz34ejm%bT)I2?x~#N$0We5
zfV;ZPIpZnJ?OgU?q2aaN+^%KLgeSS9v59M(2exxx<_q2b#tB`2;Og>)ai@R}53}|8
z&Z}3^9uKV2y;mj;tcy{FvCmzIOiXKFvD$L!WV-Xd--Qy2gJ6Z_2)UE
z`$wE3Z4Wcdc!Ybt(0Mfh^SYj3!wC<)!@>&q6yT}j3LF8TSfi{{U*5&Iv_Z0D1H*9(B!_!JW%DWGK;#lYkiYzz`qK
zZ7EQGSjRoMIvn_w$~p2kbIycjl*Zhg-i1-W2dK=zJQrY`-(&p@;+(g?V2
zJd2hO9N=CqaQp|IiVlj1HI9`X6%Q6z0?#Y0n?^I`2OU|s+q!8b3$M0rI>N&DTQ_y&
z!fWx33qOSSTzDPcbK&&~d$6AfigDbYhr0??8<)p8cch0Qy3oFLG1fVWVfA>I7-P8l
zXjq+~x?UZ#F{lsXD3n!nL=Ih8ZA{W0ub_JQY}o#ojQ1`Js#o6(Lu6Z___yl4?md+s
z?Tt7UeP+7P&23e
zAb?pv9q(bB=V-(zFFkc<3rK9B~2qYp~+Jz^uH9nfeFk{COF3E?>zh
zH|}#ccZf!h<(p_qbRgq<03z
z9>~pm-_iXTGrYD0byU%Bal{2_ntKsFf$O&3a^t}5O
zP-wkGx9=1hYDaK&ONhQ35+l$nP@1&kY)G-;m1nuJ#Y8is6CJwE%$Wdg@?B40I?-Xm
z+aa8C<9-(AHoP)}n{IP9fODjSF1=R8oUi6{PMif9R7qHCpwpoJ&U@cMS7zpvWw;Ic
z06|%gzIs4QGC>s_php?3?mZw5VDSN0y87t*L;-|J2KM}V=Ya%n&-=oe&(Ja`Y$De7
zt5uxi+v&Jl`VJG`16Me+nyY*NsFk2(xO0X%-UHo#>k#-C@`0N;bVESt{{Th)72IM8
zU~!J^O*AA1a?J(KpZ?CQ+XJv}i#X?qzjKCPK19zx!kT)Wi(Kpc`76#a@=@;jwT6-F
zxbbTpx)x?F3s4HrK7*Qjq3`FJ^OvtMXGPqPg|zk^XMs200*4B&;skQ+YUj^ybA|(t
zazgsY%z0%R=lBkq%XKl}Pj=2R4r6)`lb~K)20+&n~I&
zb?*refo7&n!w3N9_Y6Nlez;r4UN0g(DCj^VCl<)u^wl7Y^ei(3*qO8ad~Rxj^25cP
zp~lXAzs@o4VJ39`fqT6$u~2yEIx}3g0^0>ZFOchL`~R4G^Y|#Lbbt6%S65Yc2!T-9
zz{u7t!YJcdN|Za3=|C1lKvW>;MNvx#Nb>tWRh@v2b3gaq&-=&wN2e-Pr_S=6XFJdHoae}i-(W0n
za-=tD(-pvOJ}`MLWWyi8Q*Prl`65&P0r~^>YST9YPAAxhh1$(`n@^PcFp}xNfz?{S
zxD)-J4SZV!*uTp*uhvsHvu{`H-~ArF|Af;Og9SH
z^Qq&C`40}@*$(c*BJEMg&BPi|lm3r4Ie9X)l$(J+7nd+O5t20K4NiLmV)b!}T
zp`U{}CI2&U#ayOUWHCJzSTY{+c5Nmn7eeO#HNd_vBwU@aSo>=+sAC?}uU%t@iu8*+
zFk^pYO6oh@kRl~@J2#|Ms~E!c+`~-MMso6-kcOu!u|wElQ!Z}eHWU(EryxRcFVs|$yi`E0a)hJuqeGZ-crm9N!0F%b1V@Gr@kk|f>XD!W<#)FM19qa1
z&ma=ugrHnCu&<|9Sn-hSoo2zcdA8m4?#swydAFd9JH#za)e@maLDCZzxjxLZKe$r4
z2q?Fevw@SJgxr4*xcVt%yz7sv?2oKQtToB`g*Mx`l}4YKMZ5NI%N%u@ByFdhmHmEO
z^m@nW4e7no*N%=Bmy5|ONAAC4uj|9j?M7^$x>2mcK0})^i&d+Z&bv4tbNT9Nt3?QO-wxxWI-ZleaD%!Vb3)
zx$^H@d9@+PrejCY^gYP7Y1fcBUoRM!vLRP(dze!-r+A}h(8|WB+4F51yiT7_pTT>(YM*V?cQUl53V#b^E`fZ{05xcwy7)2PS2F-DZ_K+%t~%4
z>`8L`NT#ilz?~#cJK^BuY51-5GwnnkPLwJEAIf9$X+NjTjOF%tv}t}$uNJu!kIerU
z@3QZ~DY!o{SM1x&B}Q`_#lJCE{MY6=OCRQ{PweZZN!h&O3%UbjWAvsWwjciRzmwgP
z?iPIK$=J?l*N7+c9ftG!kV*e-k1L0+8}ZkZQO}TP9&gVx8*#Z8}ZkZaVO`>
zrMH8)jkqR`#al03H{!1+<3-Npqqk3S8*!aZZ~b(|359sOopa^U+jqE)xF(Lr+kCoi
z#9y?_xeDm*d2S=F)9EeF4xB!IBmSaYn`<$>9c0^xYvLrlT|(E5`1|Y0UIT60TuZ6M
zQ?`w`PNx#f=(-VqEo=~gTY!#4(D`yl@8`(>b?5};1-c_QCruVh#j(tH8n`h!P~&`B
z^Us@wedU3yPjPljZSsLY)0|(!nvs-zDA08OCY$e>0eQ?ik7b|3B#~+7NAgwGT^B*qj^7Iq+
zJ-C0u9@G8Uk;W==tHCr5Xz8F6^;!xX^OY84HiO7YU8pMHcp}(K|n=f5M26JEc
ze?Onzhcl|L|7wMr;}qArJ>_<;d&b%^YEHFndGLsL2(kwZ&+UHJipU%dkN-r_kMKm>
z`nC`#&NtC~|DQ)EdcW>}V}^aAF2wLoZV1TsNv(ek44eFAVDRLY-8Z(mY|$%|e=t24
zlvig&?zY@1w+Lm4DcF^{(Z^IL&o&?v^EUSoA4OimSN
zl|D7IGk*%);0LT1BvlC73dejbwY6&T@hrJGLK;=*C`AN1a}Bby+Xi0G1y3gfP`wm$
zOmk%B^i7E#PPx|SPej1LnucZhM
zIz^hYh9Z(9UyjHfykwl*tE!3XSW_f)~2x*@;q1h9%Tw9F3JM<1Uw
zZMb#1$m9R@cRuH^kfLkSeDghPi+b0
z-1{|hV8n7>X`_SofzW+Uur1#D?}4&|Wv=zGkKqe&WE)N$6O&HBQtWWlYLbKFGG0kH
zXMzPqvWkB#HMG+BZ)_jA$ygy99S6qo+;huwG2
zy9V9K9b4_nb|NAzpTU!8?uD_UPpIb)z+O2FzXuR+W=0qevX35k98s{F?1vsaJffg&
z3hmV$cXV4m&i`4z>|M}8Y=eDx{xc?*J#z(TNt999FeSYH+jA&^oSVRkpPXf}EyJ}w
z1DtUvhr10)+=amW$rpCtk(QX2A4G1K(qC@BBkckBk+7%pmHCtR1Uy5%(cXR7!yN6&
z%wlHN5oC|%UEXNVV4)X3xGdV{!LFk(*QTue!c&fj_zdJT^Hc-U6z4T?f9V)xG>Jwg
zhM_p0)ZyxF?>W$<2gDH_y?+mlxjXjSz8U=aZ=Hv&uO|(@{?)Sm^c7+CFmoT(^(c|+
zafCR{E-EpFBEUTFWiXYAQSdoL$_4jEkH~+}+csreE^-X@zqIw)Gncl0wKcHAh75=A
z^@98w4QuStk9J?$+T)D22#(uS?>LH1MX6JKd2gpD=ya;j7ur;@QB?ehz)Y8zBIU#5
z;bI}23yNKUlJR6=yDP87fp5O$gZaHM6A4Y>xEbMPWV)SpY3rqs>H9eP>`wII1o@hK
z_Wto)UEk+y)zzcYgStQ&ZL-h}wM?4aHU;q*TfYje1Yi2v++T0;Q94_E;NirS4}mqM
zW5|ZB*;Av3ct;gr7NXUh2oddnMPtT(vtG#36^%1cqFwz{Wk~F!mp;0*_5QEm#liU<
zF-~NlMXcohXo{q|asF+q$>V*r`;BMxyQ2BAgQEwO)4Au`+$M=jRac7KZ`P{|MPB!LVYwDrc`>44
zv!NBwYmz$489jaN8=Vb35f%5wbsos2R_q=&xoo%aWg_s>!o(qaOUK0SCs?#iq2B)&
zGoyfxe)R$U*OP-!yNfduh7FryNho0tKRB(|GYm8J#kP!`8Y?U9rS)eHU(ZiV5$|u-
zTw1@N=%?}AZV{OXUa)p7q`iopIr&}RBkKR_8)BTUWABsjVTe(8Eb{y!otY;|uJ3sL
z{enwdmu<()c`a;x$HZ3j{ODJOm$v?LyS&&AY@Pqe@_PaQZG3qQaMkWqUwDyMxkj5V
zUc)?MPqG6mN(={qg7U){350o%e9YD=)TLnEJ~s8~k>LTH_a!5Km+6o6C64+BauPkh*>?!%^~A$X0nBe~AlQqxz~~
zKIFVv^634G=1)Gkn{)(>w{AfdvQ-4U*a=eKYyRZe$c`$OZ%ZnRYYsQN|{m}?vukPR~6;go>)#1uHz2K`Oa7AnU!ae=o#7b
zUTqk#*1c&T&J+3@_9boY_r>sBXW4TmuYSDmTKAj#SSfwembt;3c)(qnG64DYVtzWt
z?9vNiUtt-zNL`PgzL&kuSN}RB&5}Zhb02uzip?hJGw}${LddnhI=mpy{b9i!i#{GU
zJonKu_5O$m&wWpEa{f)QY4>J_3JdIj*4BP|C{Ou4pqmAy!}Gy^9VuVZ9^ePPpAU(i
zb??&UxLXO|^i$mURJrIT@X*JKT;1wfga{ry>GcI;Q@@Tm0^IKRMI_$;8*>f0lS4ep
zq`LW#^ILZxbPYmQj`gXWYr|8V>z&D*Co>f^tR9DS>yygeDEF@OQrdZgy#cRAy7S!L
zA+S$5p-vd+r6LVtC!S%c)q|Xo(^4uSfKwd~r
zi1DT_zt@wI%U!79ho>_B-lsSM$V!}Px
zF`JV%IW-~m!=l2`$;BTFG5Zp5%9yKHF?(AwVw&3>(04B0@_qr%baYU?YPVG0IgIK=
zeKxfyfIP&g`|$>wXXrRkcLbZhZ`D5NrX2p~78XOQY@HD>CQoXTZ$fM1u#Sv!)+eSO
z!`awbY(Ru}(dyvz)XL&j8HdN@jj>&&**<^j
zZ+6qJWyshSNj&w=V5vW>96`M^zG(Q~C=N7I?~IuZ-!J)5CRwT}4Da6yPdwYRH0#DW
z`C%Y)PxyR{!-rUlDB$pd6+!y%5HoE(I#FKx$**A^Jz7JM=(_R7Z5F+2U
zuN`yhzJPLR%LBdR_>nv$dmy3bs&O`We*P=%Qg+qf%e-r<;&g3T6iyx93#E#Av*Wt6;rld
zUng8zzk9uBh}Rj2kMEE5flXb}X#e#C!~HqwT0=bId-5-Qz3kWD#FSd{kyaR5!%*f;
zccxcWXbl-GAJJ|tf7KfO@Vd7kqHsX^p561Od~IfKq%{%w)gejNAkzH2-^LHUp{2wo
z_5|!H!wXZxwOi|=`R2OFTE#%l7GW3qQ+^xuF$sOd{#V=kevGE5+Wb1XaICv?jYC&!
z9~5z7XvLIK;Pv|tIZEk`mJ|zFR%d2ybfi4{`kAHC$krp4J5o^QN~esW6^`>u>v^X>
z{mVby_|~c$I}06D`=u>b?N+;78P)vT{Ds-k;W{q8zU(6Q{KqPHtv919J7^k
zRt9D04~~@lFQ8?-e*Y0@8J8?Ap{xB(om#`QW!BxZTYLQd*{%1taM3sy2|2kb2JX`O
z9>}tSeUyw_zb&I}>cBL;q|v5e<#yRUYGs>8NvdMP6R?E}ga=lxVp@5Vd~v6Y$Zwkh
zS)N~l^YajE_&stL+Y-mR2Hwfp_q&Fqa?8K);AHw^SWTO&0Ii-aTy5HTE?$?SojcUb
zHR=#MEBnz22oLUer`X3Xuch+9WLU5$`ko~3h=PHnmFL5DRD(0EI3774Jwxv`Ihtos
zK2xu(W=C>|_%z`lMR8Bsdh@jLz^7o1ZTcjfv16m0$gY7c_zglHx}n_k@vzk$P8^F`
z;}Z`c(}M9_06e{}-^B*3)d?#HqA%3@-De!*p%ZfIqIXyV>}JG6G5YTu~@>lZRHK`&eV>bMDOV9e%K{QtNBixlZ9*>)jeb{aK5gi3TtHRjMhn$22uGlm9mt|
zY3T7Z>>f`%I{j#=iJ6@>aM4rulHP7vBxzsa9r?7z9EllOP%(Y{p?q~}9ZQ|GHWjDy
zAr9~$Y&+}Dyq|m9mx*KPWIW_7I^cR|5QlS&5!XGbn}*iZ=m`6?v8PH`m8R}XJuuy!
z^HoCXjk^4F_xMyt>cV0Z8b@hvZd_T@>?Dj|TY93@e%QY6VBnN{m78EReSBN|^uxak
zv_1T{fY#Ii{&Gj2T$$!p{WZ*)q2||^F*svWa?erO|V3c$LQT|
zBc`z3!esjXj>S?Lh$A8M)^Uo_LavdiC&objKP0gO`vPS+`vSeK
zx=K)d_8;coGuOG%!_Re|x?Xw6S9$Dk=eg_OmCiY>InLTgA0D1RBDbVqXa25Swc6X&)~8Zj_^Tl(YjWac=pYf=09%}@gb%_0w*}qx*$qwo@!3h11QXgI~nlrK)BisDtU+5j4
z4>#lfKFE03^MUm6@Fm~+9`k*;*qnviZ|{S(@V^Tp{~o@0k6HPGGZ}Kg}r@JypbZbKUq2F_>jd<=U3;y^7)X(T|%YhTLWg
zMwOfU{3Pj(QI#c&G-n)pzW{siY}kPzsxQHtl-Be=40ZbAP&
zy?C_xq}MYjr58Vp!;bwu(fsh7XwUGJX#N*mwC5Lldh)mC^z_`C(v!c9>)HP36wJ-#
zamEwRv>9BtYnL;U-`LorTl=HCVZA}LE}}=j;l`z;=fo3E?DVPs*=XOERv>+7W>z6M
z$WQlSd%h8*lKdZFJEZ@Ivx`?hN9J6*AII9RED7HiunQfl!(}3DElux*pGR;PuKZ><
zkM=aQ7yB1kl-f3>X>%KUTneTZ2dQ1~+R``c)d8
z=8R$Le>6Ktqouqt6La}=J2PzJcQ=-B+SMnUpDK_je|%RNCc*-Gy%v;ty!r7vG7BVY
zC2iIdC7$mrqdw96WG4)d_yvhZKt29V>&>4Z@z0N^|I2nC@jJ~oe+^*w;Ws2HS~5v1
zeI*mQcoVyfpGC(+mnB#dX9)pO4~$m9lCE$^m&VHb^?q<^%0>cLnvDTWyZ;wjlD
zwhc~`=K;bKWXF2jF0VSX3OV&}gUv%?bBaYt?_SLeulOyM^h#86MD8xHv7qXjnkRBJ
z9>H$Jir+n~d;Zjo+WDqCYkQQwZfRWdscy$sW8i_&S318^-vCJN%BLL1^1KMgsAICk
zY{~m=d$oBH_T}B=rz32mj;2g_dqU25^~Gm6J#tY>uS~VCG}WR3|EW>m<^+3XsH3IF
zkmEbUcHDOQW3BuaZqpg>k`pH978*1`PQ)Q{8G`5YM%gmROPiZfWV(Kbk;<-%q
zRPiL;U+=E;afo(hHua?<(CcR6=px03pPT&rRMjDlQ=5vhhYdNQvMKMASF%mz%2U!+
z_T^+DUGaDjO%RDx5U}o}4PrAUK9J_JZ>2`X*a4Je19(@SsUe10p
zV>t4DJ&0WcXGiVL(4ty8G_kou7MnWCuBeTOERpJjjXhf0_h!D*`;~;Y_~Zkx#6PfG
z&G_WETKC>;{^!=b^6#1R&pD@(z2WTr=X^N9(A&n;Z~nyQc-5&ZVSyaZRG)NP~PSTh$S~owNHYT}XXKX+Sq!zQHdCQbp4!lYZ(2hQGt+PZ~?qqg|a?XLBHSg<6>Utoq$dYv$%
zVXM_&OD-M)Hql!l67QGN`yaNFW}zG$%C*I4kw$8-26|S89TOf8Jo6u&se#=Q=T|8jNanfls`L>?d_B8e0mIX+6_+3b7uVK
zPN!YSxa~8iJvt-yvrZ08SzL_An;MCi!AB?sKeHslPu|yezL$dk{9Y3WK`u3o>@1V<
zwN=KXlO7RqCeMje{M)&kmzj9f^d`3=lWhN9DfyVUyRqsbGIQG5&NZXfs*9v+1eIs&
zp1o?ceE6rf?QK)lexY7`s2j8GU5+{W(`Odn4gPi1w@+-B{cRmp+vU0A*sscs_Tn9~
zxHZhNJ}Ig693
zT!weT6Q9X*BRIn$ZZ#T;KbC>{77uLrY(s`3optMCom)>jiaBa>C-3!UjD&|i`Ly%1
zfqudf!nfpO6LWEIA9)lfHB8`vFIL~@@3gooTy7>;MQ%N&zE;Hbn(7rPx4t5ly5+f|
z4X0S(gxT`;eCdJDF#ecOBwvhdyaifjQ%dsQQTvx;El9NR`8K@0Ddcdy?&k=C;2X6T
z^p@3d_fFV3$3JriAM9*BXWKwO;qJuT<=uAX6Rw)yER?FPZ|*-&yylSq;a$|@dw1*p
zciiWSP5xl&bl(AYfwz6GnX_eTBe~MKaC>JhE4cH_?>-y3_`+wd>~QTK>1=pDPxJn6
z?5^F({=b#%D)@SPrT=%kcKT25Lj8b7jmfW!rQI>3Lz(8g4SR~t+BRkf5$%N;;CK4K
zT>ufB71lndICj_1!#ZWc1E2r=n*kI46qW~@ws*A%U2G#-)`g>PYIXG?YDthZv8IDK
z*_%s^LnRn1{Lc%eKMIlnY13r>-*9yTcKbv)Cr%MW|o+1
zZ)C&!&^O%IHU+t(yJKZr_v{|*7PAFF*PdYT)s+TLlIxBvU@ZTjU`O6Y`=#~kc2nM+
zh89}cnwCI;^{1~PAD~Y(oM{QkaRQgJP{T9$c-ZY}IC&vlAKANxmoNXjCv6Wr;IQlM
zyzI8JK|TX3BbA$KLux9*;l*;yB9Gz}fHboN#CC7h92W@lXL@`F_C
zf*pcg_vf0Keydt6kDz5$w0dUlVrN_b?FXFn`Y+>MkeQR(C)+BO%CS*A%n08az)C!F
zLtISV{U2I!F`cFQ_{1YOM$QcAZ@uq~{y9?l(;e`>(|0W4aY8iF0-Z$i{^H@eIrnjC
z-1wY(b5e6Mxcl0s=8Th_t9#?@+rQDuQO=8Hx9wG5cZ$6;z(e~IZzDeJKNIG&-HzHu
zOe9r_)uZras?=xbv+E-@m
z^-}#4F2jyk*n%uPk)tU_=t=Lt-tDfeeK~24o};mK(3P{ry5IddxP=G3#DZ}D5Am^V!+Dq{~Xb*(?b_JlOY
zQ9c;`W
zF`&|dohGfv`l+#(sx~58O>C1Jn|ch+P@f6*B&h82$^UU5G@1m)oyH0c?`hqnHaA4l
zTY7FVv5xenu9eQYhCT(-F>|d%Bg6aey*L%BEHErR8d;c#Vsz;f<_W?Fv8d{*u~hi(
z8D!5Mwg2l8motof|9A2qZejzGHMZLbAu>6aAfqmeVCsxXzrd=fpmn5rpw+Y;P`-C{
zUF&eqP=ajUKC?BaSiQ|JWB=%0FZIw^yroW&aN11v6QasyM#Fsa9Xjlb}%ELX85ACbrjWM2e?J=iE&1GphE1%@2kcjx@7nqp5#n({TKze#
zE;G6Oaadh`)5=;Nk;RfW8S83Ix?M18gU2*~_lpr?a#7;wh5l{+Cq6w?Mg?c!*}=H+ufPHwWl>KAu1P31NcfZ|qR{Zc$4P(fk>H@c?>Lj@}e_&&{8T{N(g>
zu~^>uG{3qn9&@`g*iH~2>@gC=)9-yUApK#T>N8@ywJSnliZ-PoWs1(Fdp}J{-=PO0
zST-z_hgv(lI@PE_V=}bHy;O%_H*1L%zm5Jxo_ilwH#f0I&z02>95itPbj*n`(&>%64)+8nDUqZJ!d_=x&FlaMO&O8G&KHhuj=R#^?qK?L@q4{
z`N;Zl>cXff1({crr1jt(Tiv?1#!bVEB^#+34+?(eFnf_5dZ%;t3{{*5*zYO`&0v2yojo8k>}dQt-$UEHS_
zE#S=26E^+;B!lE=lcnaXGT+>ywqC~ntFEbymzY}nEZw)t-!!Edl~SwGy+=LuHh(wz
z51-3Nj9OlpElWvlT5>$rk!^9qPQ!-aY_xrT+3J^((BoS70FBd(y#q%@4$r2h?&{(i
z8$n}0`pWi`yS*7kbLbk4hQ?;ZH(y4aURPOTT}@p}oKwheeJMa!*zOu91j>$em5*$0
z9hUA*|Lf-*V)LM7y9+Ke)Z8n?|W(Z|D)@5tV+R2bFfrdCouXXJruM>
zAV;b1m+u!1ODh~LjMbaA*p$qmO$%f)tYzXQZnTu*d34#Ta!+s*TQ&N?Xmz2~?ci6=
zbahP-)}*F3`K5+7IZNW?nF8ktda+W5{a{|xvgOhS>7|z+T{b_#a{w{?^Ca#L5oMP>
zuuK?xaG5+e)S(t4vU}E0?DQ>zKSqtJvdy0-OHB(}mhlHFaH4_SgfcPjGP!0bdwuVT
zy(iK=W$*~5Yx8RGZ5h+D;@PQkno%JOUe@fB%l;Pl%^Sa2{iogN50C!vUQ?UH2>t$F
zzF%B8hV~XG2{@%>bGl=GEFX+zzgxOj`g&QC$o@7z?uTVhBL3X9q0zx_5gmNl;Lf&U
zthPMZku0Q}y+Z5ME7$sJ2enW0*4c{ORMBJY7-!9@F*5qMYF}Hd*3i%c^yB5|U?q6c7ZwW}<*Z_E~mm|gwcDeFI
zw^e^z)91UX4_3all;|Yn7aq7@7B+pGgcw<|+!eF`Tli0YjaA6E0}*HKorwtaY($sV
z?XDxA3Sm)jDp|H&c>x=p+a!n5Qe=+n08K4`PlF_AsphyHRuga^QDEwRhoGi9B9f$@
z;6P0s$}}lOnTNfKSz8!vxOR9XkbO{MNfOI;4J={$ye35TRwBC$GoPbwE(`6TPTn{K
z&g!VcN+q;Q$;2+em$yJ)bX=3+ank2*VX{YLa-PVZg>aU~!cr+Q)Q4T|JV|y5_0ED%
z8!>S{{4Y8fW4B9dneJptN&({uSQ-%@kf1uXEp`;&jQU6R|*}7lk+gn
z!|{@Oz+p=gF-{RSyQy&)XNfsZO@bEaL76_14H>Cm1>_lxDIl_J*ibu^rV>~Vnj<`WR>
z6-_5-_PBAZ)UGU6?ouj)&`=>)U)qd%(N7*)@KT{(cl1rcnKw)?j^}hg=Bgg>g$7G~
z(C0OFw%-tt>VB(aHJN>Swr)m!K;oGC`v&Oubv<+(g`yQF;X7tiV5`wH8(91%^j#2!
z>hLe~WfEdIwzvrvfIEkAamLeC*Ran67m?Bp&
zd5VKmnl{CM7
zgvYrV<1D{noaNWY3GK%kr_B9$oHF7ku8&g|q)yzo#`)xldTX3#t|$o@M+N3cuELnC
zxuG+cX@2xt&}}^W9+Eh@($O_XN>&j44cKJhx%wKumGIt&IhrkT>f8{b)2ce?nJ$Lh
z3g$>#Wx;^v$Q-*jWYe?aF|U}T_5k!td{1kLT72IKn)6q~N{{dT0k;;5xvr{0M(7!T
zSF0-$k_i9mtD)}`{+%%KPdQP|ih<*ZwP@D80>>W!4Z_Q#I50M^kfIg|HW_qf{G;)E
z<*qU&Lo)-ee;*LS^M1Aj_E(zsbyt;4v{wY42t3qIi=2Y7>o13Ry*R*>X#(;dG=si?
zvjmfAm{aUOQ!+z5jZvw^Z&{5^j>4S2R?FcWY$iuxPG_HB>fBmRj;iUPXXsao{_+W4
znRdebPG5>_jPbl#r(V+xTyg*|A&eielwfD5g_plEgt@B)T=1-K6unCcL~-DC--G|Q
zcPKANoHh-3{W9IPG5&}MK7+Z6`X02pFGY>ynZ9x+
zQyweh^n_VVnZ1kY@iVda6tJClz$UK*&zJ&8l%Z4`7oZ$niZy-
z8TG^;Wbg-lS{$E5{NeI}2$}f9i*Y7@P%43YzVd$_UjpyYy|F2B2;&HkMaEe4#wwd$
zQ3a1W`dwWP9=5}#wgL~k#$(;<-V!&J?HUihp|Ude8d&2Ydg>gHbx(9eJPkUnMgQjx
zG=}NFL0>hSDIvfbFeaGG6`=FETWsbW%-O{>^iiu2fK$MuOzf@-_fPRxp?@@oo$$8q
z74Ut1F6bOMDnEvArh@(nmwaV5y{ep3TgyO`v4A&z_13-aEu;QjGQO**O(OcfR&Cd!
zK;MDW7JYvM`Zi_Ift`BZZ00%Q09`Sgz7#kUbvi}u8wHO$Rr}JAkL_jDRCN{@S>!VR~;>u*Xy{DmQURK7oFQDv%pR;`Nn)NoEBy7X$zU(S(6^
z0yq~}&MC2FfCbhQkUjcr@ZM!rHqs%~_FAGV;4|@Y(0n6ko(CVtGd-_1Md@(x`U&JQ
z=!dKod9l2<5;zIi>N9tP?uh1b@2$W+(R>BI2cG*u^LR#WB_YeGqF#aA@95B9zGCt=
zl6~?t%suo2#ouhxr7JcabPsyx^*rzr;t7rf$i8OKm%(Y7pd(Kf3xsK1c^PFOqZH_X
zid4(g>X}S^3%^&Z;F$?xJs-q#&=+sGWl6++6<}M1wr2v)o7{Ra;FTHVl&TuYkus8<
zUqTORca4Z4fz%48kE9a8PuP3>7}m$wt%sAG7VWm?qUk|i_4*O
zPVSq`uy1$)>9_L922PH>3wzCjoP4?w{l|RyF1V5Vf@ujOP2E%NdoV?vd^Aptkwl&7
zc&!K+)h$pXn{B2}?BGd1y^B2Q>RTe_Vm4?5_@UD^3;Iq^ye}pCU7+?oVApGBn!1&-
z*pa9euVhB46m>&AkR>QrbOG{lCL%W+k!G1gQeIi?mM8<^->&3DX`v0>Vzw=i*~aQF}2St
zHGqAT^lFmihW>#1lj1?Y8BA+@nPftLBi9K}A*_AbqC?IaivGL~zmqj53Xhx+cjJe7
zA^xS&oYk$Xra3X}2U=wjup3)RbHu6RDiJw~F$kdZ$=@)gXcP38jZB&4V~X-PXk-@C
zD=UDrsL$7kXmqL)VW+n6o$OVeH!4+^rA6B9*b!J!F7Tjhu6MPiqD7Dui=k>;}u-XM`p%`Jo4e>~e
z#mCI{ne^*UoYYG&&)yJp3@=kpOVe>eREH^(n;J0Jz$wC2>`ymwbUcHD0eCkH
zoP0O%Az>_2W0H8Y-U#3b#--vMNAw-ISV~t!PX*i60?+}CeTDQ`C*E2(i}5lxGmKX@
z-9a$KoB;n64`3L71^R3PBb?AOWk%nCw)(4iWRblc@iz5LO$3etmVhJd_5GPzSPu)Y
zvz^LnSOaOao^+gD03Rvf+n$;`PKWWlRX*KV$2{fLk!}jU6a8X*E4et7HF%v`TgQD&QwK@y*>ut5YR+l06%AR^Or2`2}5v$6QX&Q2ZyoNxZ$)9AV%(`dFBW76naC-@;~v`{p8mh6mTYR}rc!?-b8
zD+0~~eg?AZ1IKsBcFxhz)O}fE*
z;}K~q)rETY{D`*f;WEGnst0p&sFSv2JK#Wcz1N5Ao1p9cK09a%bnSKPQ$07(b!8WA
z>6KpKA^PVFxx+ls-AUKs`Y*_$y&W`oomL&kiDvDJ-3wa9_y0tz{jT0ftC|nA+E~3n
zT?IH+frd?);*3;d1c#a+4wCb6ipxDH13n=03_Mdu#ze;*S|(^?bu2?xbkGTCqj8=I
zU(g!h4?4&_KS(ATS$KXRtw+?i2+x~LJSRS^1%e$~Fy8w9Br+8pL>n#mVJ&Qp(S+{@
z@E~}$Y+8L&6~wX++mnBDn>Qtp6_#G-+^oO=3K2fX+s>?
ztpU)R-Uyyo5(oW19p#g5qcs}w4Yh9wV*uZSu1|QQ?iXonoZ3?uPHm`(Vt^NeNb{J1vH=Nb6_l|lkh4>c6TY5TRP6Ig;G1#(y(~nqOJ~7f1p)Cmphdg4O^GQ0
z{0a7FS|D@VsSnCDJ4fSE^B|KEmjWHht;C-PPpyT#sRNERQ~3*>{9DO$rs(sC4?6xx
zwl~>h>ZGS`xUbT%PA7XBXyh-l=nf4p&G-W~ESC~W4iwVbdjgSW$G;bc${~Qbc3t577Bffjvh;*(;{p|#AHP;TC
z7U*RSczqNik;8HW@`)opZ>*|sH$-QIId`Bw
z@Gg=&B-4t6On$j}0c0=A;=Xqa)(sNYaYJE;K{>KT*(LTu|9FZ9=MW9fd7uj;7Mw#Y
zI72Kr*+Xr#)-;xiKEU2@#3fw_!^(qqZHQa9Ax@n`j5>7bXdABZUk%_9!_FawokNT}
zo<9d2JBO3);1`jgQ^@!ihV^Iii8SO&gWiHZYJd3xSr;2PobW{U!Ud|M*&&k-{s!_%
z{l`2G_=@~+SCO&qE+%(NK((FaHVCqsSO3m(O$0=5zlXZXA#3`89QldBT
zhod;j!wcI_$gRKeZ&(+A9#E&=`%X@F94%G4z3ax5h(GXMb#!2PoH7gtN?1pzlOSsCBCM|w{{TcPMKX7=)MLnw!{!q!GGCSlM@vwfI
zyWn&r3@6EglM+*p^*6G_Jq12id=0z=a1yovPU{+EM5N+mzYP|w`du@5QQ=|}2l2j5
znT2*7kS+21F*eNQc-Xo@F9a*l(hoA`&7?V!Qx@;2yZ(&$v)SKE^bN{?ug-drQ;Qaj
zP|vrF&{kgM0RZNb}MJ6;q@+`f>x(t&=_uqD^D`~v
zL?%)^gPyJU=h(D2x`7VnacX-FBYU>yxPo=<7OZP)aBsktwFS>>+{)=1UM@yXxlGVZ
z6V4fdJW)JHc+;Mn)dbs77S^5k-q{XY8or;Kh5PS;XLts?n||SLF5uvpytKJPJLW{D
zN%T$1aw}I3a!Pv{r%Q8eO731>@jPqOc@J{AO0bE&fHO=k^XiKpTzhc=*r+tv^EA(u
z4t?P?roa4xRd>@otihU@Iy)147o5xl+PUa^ed(O8Z#9X>_aU?em`Rui6OQ0>l3~Ho
zwCg~>@3d`xBf_o`J`*tE}kKWnTn++oqidU4)+#55hYkiF8|(lTp7#U;VB^cZ6-*
zPv0~diC9m@zsS@_Og|j_X7JO!cphVOxDjCnS`LUZTD@<9FYiBR4k0DuOgRHSZ*4Q9xY>+h^WDSRXM;!JYaoBgn
zu`)#+WE<58{id9Mx01`5XNTe28e(cvEEvT
zC=BSeMS^JQzKG5(5ba&_!!F<+@U&k5pTfIDr_I!V16k&(kTt^(<90hsKse3nzGTGQGz+d8^Cl&)It3iL1
z1*)czDO27tb#oPV2%2XTcN`~0bFQOK+SM2*`VZWpel0DrYd+vk0N)7>zz@^cX$L;E
zgRb4s0c`rz<0#93C$W%owPW;Hv{}>8)gIvn%^~V!rMSLs!jNM%~@zdvMKSaJ=
z6E1Z#Z~}XO=tl5;g`ji5m!O@1J&){oeBA=2Ie-{Wftfm1MFadH7<)5xlFCL-?E@aK
zz6&0~+ts&fMd%yABiI~_An=5@(LAd$@b~s=7S*1oC3Pw6qluDTnR$TGzI4Lf7amW*
z7@3{MWa2W}cw#~}WhUxn@BzgiV8&wFuOG1^-i<)HpRzvuwm?P^>I&(TIvRJ+>C;ZUmH
zWpvUz=G*E+lxSBI1+3LEt_LMvT`1TQzk_d~>*A{B0#@LIvR5$sr^5e;=t9iZnKt9Q
z_%?M#v(1<_=bABVA9NaXKHD^m1@qHpBv842SB=`{Yna=1BT@qYkxX8O|C|568*6{U
zvHxF>wM&;KefeMM(xhkqM34I*SE}eH3**7Zi
z{vPN{Nt~%mUuZ!V_Pdz2=%%0O((geIN(Yw%
z15=;I4hH1Me;W2%;P%s%aq&Lz7twc+Y6>C;F1{qVonr)OCD^wAj?|8M&Ax}VXfXZ(yl-7l<9ulv4B2OxffwIcCQIcC2p
zzhM_gc3|8mG;_*R=VAAUJ%Qx6Akn(_|17`B*Q)in(jjL?SU%Frv1Pg-ZB-p#zK1v7$mY^~Fj~iJHT-2SrYq+Xx-JiPIi~3|mmo$#HllHo_m-itn3v
zrC=g_ORZQ#3Y-%0G-P#%SLaf+H+)m12R{@6yvIFnKwkmhJnlqJ{R>QQs6sa0@0ia2
zmY4fP;M<+hyGL`1be>n1`E0sxB(Hm`nN~@DYWVW%tC`ZH18WMAOQQO)xkrPJM80YL
z$`!0jL{69Lky&jn(>*P`o}Y~Gm)gkoCLc!~&O6~>Y=JGk%Iq8QaHR?V<6ATSBkD2q
zcOFwlO++6cd+Zs2!D*(C#4qYRbllTSNy76xQ!zh&rk9+-nG{Y=+5J6iS9ii+cn04b
z$8S6OxB&B7Xwrrj{}yzNpeg(1$6kZ%4szPMb!hWNJcrIa3HoX%o@q_-utfo0@%5H|
zH#r9U9eVAwtvyY>)**og`&+sRyMTM>O(IS@PIQW0daVe%v_In~dTq8K=aDY!gsjK4
zQD1E2ialPHK_@Xu&z3z)kt*wysqjE>#7qW
z4{y{}CtJEIWXsnY#_-?jley5v>&_f8;v7HGCmsKHeUfy3U-`e#Co!%c>5~}S4f-U(
zhV(j_?9$^aqh!)2M^}m(`ETQ55Ca2U8}V7ntP)GV%Yt4w`S|}xpOmRzOUtk8le88I
z>yt9{NzkJkx{FPjy5G_#eVZBDg+7UPJM~GlNAm{02z?SdT9-Zv_{G7V+Nn>5=k^AD
z^3Rq&dEC+`F-Jy(RATCrBCgl<$&&xQK8dzF^+~iF)+ax<^huh>8Eu`oW~~>_eDqV^
z2%P&6viV>8jbX=1g71sgY|1>?a$oy1XeSA_t#s2TtQ}7?{l@ZS(wDJbB6}S8u2x@f
z`jC}5`w@!;ISd_5mPbPGg6>z71)UN+w>%E^3VVwB){qqJyN-c=2EPg3b@`E-Adle#
zA-FU43k|!m$&YOM7o~RiYh{jXn5N#&N}a%&1!`Q-u4nb-i~=c+cmjOLh_N&4AV1s?
ztWy@KbV>%5St`YtWscyAGH9cZ=_7&OuZa@i30%CP1%
zI^AFyeq-pBmfu)puz{99t~2;QE8R*F+Jn#4^1b34ya#?ZD+c%{{IR%)ZA0p%NUPjx
zp*=#M)t4iml-Y-#pE|u%QoR8`(xlIu2}%TdZY=bx9oPTQ-_c{$UDN~P0h&~SciRZO64eMBNuD^~TsN}p@iO7Sn*BDc(SIMX
zyP5vtTTI)I_6t)%7YA%+o1$cnoqWi^f76FdbYR#HkPmsTPBc^`rCWGgnrhNW-MVY$
z+`@iB{Z;IkGx$W6sCx9b9r2pLHNvgTzMcMnLn`7LG?He+>Cc+g)!tgP
z*Vp-oM*Ppz(IyeTk22d`(ejApM_$(qz5qY61Ab(}Rq`W;c>wv_r1r4C6uwe(o$U_$
zk%OfsUXBg>k;g$^|4(Swtn>8sIy-6iThZ|&KXL?*IRV}=_pePlC^)|JM!o_3G=0hc
zJG!0mW4g6TF(%!vv5N}PZBN*nfj4qKd@J_ge)!fW%1eP86tBUuV@!I551IVymTx_n
zV*1xn-tu|%``*O6MDRzVt)-51xs&dx4CcT{7mtGm|74cyg|lm@TsF#e(%@(*-K0U3
zN4a2T9mwZTjt{dUq!upfRHUTB2!l
z-nwWSdV8lo`Dbam-_@Vev^)cKGZGM=k2+q4O#(8;lF>7EVZULs;sXxvH~@XP-Hn)c#N7I!N5H;e!UgkZ
z(XQKq$BagOb~R+9W8jVbh7MP6`XE-lgN#VRo&Us7dcA8`Veg?i{3l*wf43d5u&I&a
zEhhgDiTWBc*=}x*n{|I8EeKaUmnT#PG4T9Op6TN(katS`%F>D^yTTbaU9VI
z=_&AK|M$K;vR7e!cHNg(16^UL<;xSK8`o$5tuK%K+TeX|rDQCp*!R1;{N1J>oZw1+
zaNrxp+vV>*dOz#{o&N3`@IUf**SM7!_|n4uZbkl%spE?sid5{T{jeAp{BMnR%&8Ug
zpMdq`6!^L04U7|VFX=3t@a!g{l{1}kNb#R{lfN5n?CRnVb^T6JY&69SqwcRY
zJAB+R&dN?7w~6P#WAw3t@EN|{<3D~!KJInj5U&o)2doLh{%ptt;vJ~>EsKxS{S4%$
zGp}tH&XcXW-)j0E^_aeL3#ZTgrL)d3j$1ZDlm7b^Q5~IlN9_V1DOUW1$@A*^6`JqO
zI?pt#36NvHJk;NBwUOwAUEGm}K2=Z|H5c}7qF0=g)8)@bzfBt-=-F7+V*0bm&Tjg%
z>t-A`Y^!jVr8$Np##>^Z)#i*NM&zpS{h7<1_B*W-I1c{NDP*VpH|BmGKm1p@LIh&7Ajc5f@s=pah;P@XPQiMo
z5<0VJm*aO}{}1e>@I^pQ@;a?Y#M{SEoCRRRsbho4;Z?ayiLbEseoQH|@ULbI)eYUH
z&W-Pz$rlb7Hp#G`qb;m$Md+xNrAjeqEo%$->+LCKY#rflC`5A!{h8+7#1G7m>Epag
zW2bmh8avqs%(07Sf2%hItg(+nzh4(&Z$p9VAn&enSubNx#jwMD$yM{{eFk+Pb0N=DmqOSHUmg*O<{k^UvlY;J($}ROqX=!eXY?pYI`0F2reSu)i#}+qKL)F?Qi@
zIp#P=v}N`KHc&YhI23|z0QgW0hspEN-=Emzx?l#MS{KX^8)k>C)rwgv?YD*IN8P&x
z^d6oYsdH}51BYL~JM80c)?oA1BEr9QVe149zJ!sx#(bBW!S#j_)ofxQzD3^U=pt=V32Z~=4
z+@NjPD*PEtwLv$THH3Hr=n*_^ZF8$pAheo&#hx9iOD@htteON}5Bdo9k*W6DzTiQi
zY1sFgFg`ppGelTV2eAVV!n&BEE!fb3vnUP4YI&93Z!0gF=Xr9
zd9=<&KWM$$A3E0w_!!Oc!#30tyc{r?dmRR{l)>c8z;*v5$sgtx0B7v|ky0>UHU;|(
z2(GHQ8Ga@;b(Y{az9Yr;cw4@mz%Ic+vo7@Y3#8^nSN&s
zpKzM^9N~bP>j2*b{MKM@m%=9z#xs(EGU3ar+IEz0muF3-`p?MXdg8T!;n86l?y0?J
zS(MA~wJmn}uF^+!BxfBauZxziOM;ROGordS6H)`Hkz%=UFhnc2SCulAr_n}>KR32m&BM7i+*U?H}v&onvIS4rLw9FR8PUD2c=
z&6mzxA4(m_^I`Up^gpc$v7w+Zva##l2E?Ppn|pMrPUF?s4%)|V+I7%B%GhMgjyL5B
z_1%0vFA2{>?PmY8rRJY~zD6SdV54U<;ISbMC$wVk{zqlZ^C9-seVE4a8@(L=ZW#yo
zA@(c;Urt$vYhWg1RulYXHHbkAajxM(#G_>~*9ZyonPGE{K<2#JO|2%b@O2gpUfYLU
zOHGi=QUtAmw7Fsj_V&W=T8;g`0mwi62H`g(fbtS&%nG%uF`@}?UEJp;UsACRu=Y*G
zvvTH=uvc3|dHgmCxZ=0bjw^l}d0g?^Xu}o1jU2A{ZDhFOXU-vZ<7-7;E8f3Iz<$FD
z!uLk4XlPeE+Cs)^vc*;{+lD!kIxr7z@{1TR?`uTaD_SG!z#JnUKN394<^fKD{vy>i
zjliSQ81w%EjJE)`03j9`O5o2glG-T~0LA+2RoI(56mz8s*kh=}*4fdnq{D~eXuhOn
zK(9%|K4icG{EH(VsWg_cKwfq>`5Le{*P%DXbLtxKULnn_M@a`yLwQ{Qufg}`9^&wK
zrhfwEVVk^W_6zHGwTSwe4f%*z8T5~y8*8L4JjYn9F|8tdL$+kT&!zX_v8H0ND?q%x-7iTCu*Kz(MtdE}c8_hGHnPIGkQPazuT
zA)kQLYEP+Wz`p>ofK5&O5a2CvSAQNhc@_Ay@G{fSJqbE|zNZ>j>EMR|r#Gkl^ZU1+
zkHmYCAL7M(%*9W?UuC|x^Fu%jo6G+B{R;EF4efJipZllp*FKLqPb0eFjHt?bIbP%_
z&I)IBK~~@%J}yOQaw7{u5A}7yj02@uINGn+^}NvX`$M1Wp&`E$Jtvs(=@@f4@P_8W
z3!iIDC8O9JMW{626F!*yF0s?8iGkV?ltPIb}U}vkuNsSh~p(CNs0%!EC
zG-Czm+fM!p-in+U$Qt7V?0t<*`aH-@KYq|p%y<f>>_{Cc_*xyu+ykcTR5)V4!uUu06*sBLRr%YNpcxD%^7s5XnbvyAEoJav2
z*bJCTSxg>FIuz)h_(2@m8&My{mSFr{xG?+3H9jMZHzH)J
zYsCJ!c#5&Z+{FUcmMk>vA>fxK?>cei#`=uK)!_I2+Vz@E)>zk&9&)?I`)h-u%0$uJ
zqm8zyUSw&7u84LVIBizMJcwBDnXL*WR~)$5mWuR<|TuHnt_OhVZ5g7RW{xtp~R7AX&O<$r9GfQp*-7
zO4I7TEj8|!Z{OAha0jowzj)=Y#bV6>yCAe9=GwCxdq~&+uJmu+
zY&uwmHOo`)&OCbLUD)DMe}^l$g{>^P1vXdj%sl#Y!12YTAnuUv!B>-l(V0SgCFyAJ
zg`X}8-h9Zl2mLkp`oox?J-lcS&fIEuJ%TSU(RltbR)F>encz!DGXItMyK%4FvIy%K
zRuEi)?`f1^zP4yDmG}3c{eCcvGkko3>6NE{in%4|?s^Y*O$yPE_BNrNW85h&JePkL
zYpN%)4*iV1o_gikBXl1Fbh-Q7y*RVK!412&MMw9bZ&4UyuHvB-?dn|0@9jNq(dTIm
zRS-PwJ;)I}7EQ~qHGTGe*hSE~`|P(0+RTizMzV)2RQFX?h3U
zv)=&iSMU6(m~S@i0naoy-cy7=i@7KG_@#{dT;uGxvwv}6NFTq@G^hGKjCI5#CU5EN
z;1dyZjO*ii+~i&(0)IKIU>I9B??>WaU_C8H#Eb+3QQkU<9NLUTjCUpyNh|t-3nc#9
zc|Q_gOC-!le3Yk?RaI30&6~YEh(xikqrYX{Hr|pjbl#>1%(S6zq;hNNNHoN^=|(D&
zh;QVqt8KI6jj@`l4b>SuZ@|=ngr`j(;nmf=##2+PX!s&A6<1xe@uCeIYec%Cp8jFp
zZw3renm{7uk3u^Bq>%`6GmzRLONUF3R3jpevFtR&Q3f*>9?gmOwLth81n_3+v83NL
zA~A%sY4!B;{@|D%N=J1gk6g8Z%{)vsNPHT4AjHE7gB!Xj>!eGMC5$QF9E~P|5Cm@v
zM521AinpW2!~U;$%)NWIz{ZrGW1WSxREk>Bn}WUhbJ}a*U@j9G
z$;$GO_>UlCqToo%`_sXoo)T1&p%jMlbhO!fG9PU$a_@k~2CW!1txZQBK!+jAB$4TsKaQooC
z4JV({Cg~R|->dxIX4DVsOvFbizJDxXnDB>ugTs6P)mU9U!VT)W<*7=ZM8l4ORq}h-N(CH`pct;+}y#1Zy^o!wGH!*
zXjC6XFAa_b;&DAnf)H@xO~GWUHbdV@At5T3!1#=I%s?xQ4z@F`2dBWbh!lC3rx6i|
z>8T5=c}fo^;vtmJ${F9YT6^wVl1C_QBAx62<4V&hGEC{J^#V_dh?}Iz6hbmFp&Kf(
zV$~uAzGM*0?X-ZwKr)yJA-U>r&{r|%`)D$ffNG$=ITjfm6J>G0qKOGvb_EkkXgm;2
zE1e=Dh2G(2f{Uu+#-wa+6?iq%DP+Ay(hzFbj!wzW8cs)}Q!<|DWXM2nqSa=Tku~D#<)#=8B%n~~!F62KOkFqf(ULZ>7Q=}w`<|;~+H;w4f
zGEF>T@*t8yw@&G%NJ4$zZ-OqhqvNGlX-O{&CXa{j)E{%=S_M(a#MMB2M?5hR=fOlQ
z7KqCR*&Yb);G#iE`Q-Lt)rFniob|MMyLf+V7jKJ1q2aj)NpoSrSjAykGVlhk-HUT41%hq9rNZrwQ7579moErKGvy|2U93cPqY$R{w((|I5iLh&cdJ#~|nQJscR
z%A08PwKjW+CgF+(m>-q31d^zakY1xSL?6vEVtObN;Fh>pFXuPQh^Ekw3QRy?|Jfw#M>8PB%G=p;t)ifMY^|2s2oS_6I=L({#SUQf$
zEJR33iy%XNgS=mlr!dJKkC;=#nBhXDfsZ~dco+QyAxAQ{e5vT6zQia^DM@$$lCE1tdPVY{re?|PY&MpQQCpIfFIjonh$1_ipG@AfSVh@w
zKH~bii#(hLav|tEOo5jiS&5Y$My{Y}tC-b{>gGmkf-BlNMuABsQ^&hVSG|GBzF^V-
zD&?+l=w0Agby~w|P=#RdWMG+E?9I%_ZA1r*5N#c4O|+HDoc)SCFn`Ey$AE1f=
zU)k0xNr&2+0`brvb~jnNbRReV7*fp69pi?po=+t
zF{V?KBbAnrV}N9&feE!3OGCrdZQ+;!j0#CICiN?r4@U#3F`1R69
z{h4!Ing;(Z&>eyQD*Pb)Qqb*%{}R?0N##f3|7wv->wy1_6J6RE{7LvJ_%D~bv;h45
z@SBx?8T@xwy0j_fZ-ZZncv`GnUEjT-S||KM_%
z1}a!;Lg)f9rqIA(=s_KOP0+H~TrkIU4%M92tB4Lw=)x1jScX|c6_t^f2RRl?A?#CR
zGpXW;sLeQ$pg9z$JrAYee0bNf=A(TcYc1kUWY9J(pR;u7uxXFQ^8+PJYVXp%}H|)f*!tD+BM_8rtpKJ
ze=9zE!d1)vxB^+Ruy}s8N%SvL66j4FZEZl!OMR1AM5ZvStrWXZXt$MW7m9+uMAQ_G
znPK3>eh8@oHS-mkov~gWJ<0(ZOQe7ksZq0b8Xz&LDi;gEOq?8@WTag0(L5iUZW!Rw
zNt$6d`#MQ|l22-r^%{v#I%sauX~zOHC9ggn3F_ULJ3HU|b*u$V39-}IKSu=kIFn--3Na0(TE|Vn7PT0{*d(5zxmKR{n9t#99n)vZsOXG>D`!PohSFE8#
zHCgdB$BC~#PP`{id_e4;`e`qDls1+x;oXCN-{4k%OE*nDFxMINM?#bQk_LV;y;qoH
zp>>TkO#!clNd-R-b0AOk8YzG%#v&4uqsWv@JWsn^G|gb!ZkE1;GWPI|^8KZ>^siRF
z6@PR>!tc5^JDnB(Vg0E4KZeeH^R19aJ(ut;t*T)SuHomM$9L#{G&@KuY77aK;i_;t
z9%L11^y=Cgzqux+$3)v|#H8&^XSRe0c-Q%M~S(Pjd2qO%p8%s`h`Q0y8e+N4DBw)VFS
z5p=i;P=72i2^vTvvWke#Df=bmAJU_NDc(q3RfR>h_&T~;`~2S4&gRQxxoQ8E=GH?k
zJ>9edq{$KK!XZo+b@eh7jl?NTGdF?P*V;l+mGoau=hzTtE5m%K-`DILz$w&_cc816
zwh%cU%3
zTKrR)f$OSwxmaT>!i)Eca0Av<#cxl$>q|>dJ$nm-q;R;tzcIqya#p~?7+^nw-j-xn*z25?N^3fjxdwq64b@w
zw|}$ZQ`3yj3;3sjTh!#PCpk}p=Hez4z2L*zQX!d=a!y*7wBJed1=Mn!e^cmOf~L7{53P
zN166{OOtTX2T`tT{NMxSdYIxVjB?pwl#9YMLp9X)>b^;|K@T{qzAfn;e%$-Q)b~O2
zDQ~Iy_n`TdmrcS?9wOSnb>ojoJrCTH7KD+{k7PQ)T^Ts?B)Gsqo0XjA9
zOI_^fA>_XsbcmN10pH#7g-I&s|AH)#rueA0^p+AWwCn#cc96n9M_YZ>TY7tm#ynr<
z?3`bKC&~lq*DT&zDBvR8T8et2a=98_C!D65U6lSPXj1yO8GE{9+C4~h3)u8;y&NqJ
z_zb3g;G?LipdO#}Zg?N~s*Y=cC+fJcu&`l9&@8KPwU!oB{Sq&Q$TN$VCeaTC^;wQ|Mbqwz^WpDyGY*saLh>&Vep$sjf}bSwL}3ee
zt32yep1W68UPkhRvJrU!SL6lQ!m}WO1qnDLQ1Ca!2d&o^PP(pHhLcUwKfLLxAG)+<
z&tHmi%)4
zz27+ejl&P+LjQc<-}pw&{ZscJyuWx~&%Q70`{#YDAK3B0w;p)^fu{YR+y77dPkwOt
z!TTP3Y|cKvtGMjM6HhF=`-`WRopa7PWe@IOTUJ|JTlVn+1RO4-1`K-tg#dAJN)O=WMt6)&5Zm?*=rU-tQ3yO8!)r2Qh&-ix&Rk@nHDDrC{w
zgY6z{*3d~9HjHRvsoHbF1>!_SSL+SpI(MOcTpT*$s15{i`f;3Oa!s;)Dea&b5q~;~%>XRWCjDZ2#;;CGVFDl!<=*uM
z&-(g};;5uf9vS1D?3n3c`6g_ZWMb#{3A
zQ@@z8;7y)8>@fQi@Y(O50-eQdDJ(!g4&sZkMEv`{;W=oB;!fH%b$N(`Fg+RKWWnNX^|9V9
z^oxD_4)MyGy)FICJ_+k9E?`%b8lhYL)6qc
zdY*i&7?F?X>J2iFI?u)HGkJtY8)|FjkrVaj>S}eqo+mFW=07Gc9MQm>t2_m3dKSvg#uGwc
z3q;~jH6Btlo;{I4&^QClfT+$%_51)2v>)(;@x#=k%Ck!V)K|gL)_|*|fYKUHNt}$#M
z(Wo=QpuF*seWr&)$oB1ivW@`J=9XGcH)4!L8b%g4yc8!QnE6*Khx3e872>4BPlm^I
z*XKOm-rVVLZt?i#k%-peTSNTKg;zaKyqbC8X)WFJ!lMFaBd)3#)#D_pOhLK_arWZx
z8}xg-n*FU^y}rx*vNXrSZR=?3@%L=QFxl4Gvt1^b6TcS+#eID}eaE8
z^T3B(KNLRX`=Rh_KMcO8mRaP{CgzYi$-TGzvW_>KD-MV>ni@JX1*#Y26z
zLxgl%hiY|5liKJU{2)zl^JSeqkbG{UIn$sUIoLT?pTjwQrq4Nbra5VZg}RQ!amXKx
z?wDJF*0wnmXf_Qj+-Yu#V@oHQ>U`7Gwzd{h;gyAblxQ#^hAein=pZTGznfLA{B%4Xu$7mNfdR!#I9Zurp`2wR8cquHDU35c
zWD*OA(nPcBXg+0u!3oZW{k|Umme$KEV0+Qm+STK06+j%oikar>r_x-U{m_lt0$NX(XL
zGsuZ6Zu-zAoH>xQaMjJCIZ&Cnv!Q6g*xZC+y(8yJ9v{I@T5yMM`i8DRpwgiDmkGDza+BhM$PMQ_Imr~yiOt_P*7un$I$ON
z-BhKNKReT{y$SaLTuWs;!A(snWyw=|i3v8!E5%q=$zvEvBh)c^&o}
z;|ZD>W1?;15=SCVR;P+q28hi~n2Se3B2r!?i3LV+>2Ee1vrAkha7IY{)L5YAqV>|`
zTjr6ZJEVRyI__7u?l@-c4g}i#M33TRKSC)iENdZ{Nxx$}Cni@WHsl;X0?Ib$V?mQ@aBojQ~xjn#u7`I;>!X^fVF~!
zamwsABMlxMX_CE%xZd@`+V>QJ9>v@E_`APCV;S{%W8MZR%dn^
zFI|D6JM&dA?F^*o8aiqO>Jau&&W3B-6UuxW#lzbJ@hFx@k$5=4y=fRhOE}de7f+n-
zD~YO>??hGV5BaV(&C8P&>O?WW&Au!nS-cavzWCqcgiM{rOgQff*FPGgj19dR}Rol0!hvl
zH5*Q;?nIGu#7~ug`pN^HGvXe!r9Aj^Q(3y4+H~Kx+8XJvuakbYFly@CHVKn1+*`RC
zeFE+XockJ#<8WueRl;qAYlqtg7lJe3rr~Z@@6RI5P)Fa^VctTwCTXcocj~;66j@K=
z788!{aHqps{Q^^dTcUL`s3&R2<*jkkn8KGipqroxV!;62VHCE8l^9x*K|5?>5Rxyz
z%cK`q%I%BsoWpc;Bkzby15?U?bOl|-ih(D(R3(li^Wh1TW1L!A_d+ckbwfXrp(#`r
zQ}LK526l)s0AK~{r2VYC8AIM#I60ZBxPB8KBe}4-tA|TN=xpXQG-lyh+$%b*@$ra}
zh>M*=oVwCoM%=O)SZ7^fwRp*o*FOsn_X~7mTpj8jGmoxWX`OYF#BQ)HX{S80BJ!0p
z2SKH^_`=4hkO021q1qSfqy=AA5OWr~GlczS(ZVnvisJS(eU~8+x{@y4(LMc1+*-g_
z7%J>o8rg>W$$qv?UVjLL>6$l9e|bgq1~Krp>DY+HjrE4n6vtuM-4f3I{jHJd|aEVDwIjOC4jC++>S|B7Y4#GZHArsXYhVUgz5HTq8
z!0O&hYjmCs!zTuG!*l>s*iOdxTxbMcQl8$Tsn4_Ez9K40K`mgO&**#@kYH>KCID$n
zyVX3sIwm%(=A5Ui$+4U}=b4jXHa2G*=BG6GnlnBGi*;fJD_4A_NMTy??=^j-$owsd
zcsMdjvd;)xR7s0n5reS*W!##mQ{B`F5TlR37*j3cQnuibD@Ma1j;j9){*w
zLw7Zaqq?3?5lb$Sg
zs`R*@d|FnjtqGe>R=hq;%*#t#4wxLljeLI3%39|70
z3F;0xWwO#B(oTi5K`O2z3Kv5rj+vGa9O<*m<1-S87-e7!ZjN}1?F^4n8XQ==`W_j
z2+L(OL9&Qumw)a=Rz}(Qln>>B?bIBJ*?1Nk)Pi!`ffc9Pft>~hEA%-E+z-d+u;^ne
z@}{^QZ`V~O@45M#6!w5n3;D}U(SC7)OYJd|ZPYVQj9^
z*HcI<$$OpIWuQ1Yjk3OnWXDtbR`D&B{OO@PRRs1{Bqp^~JAF51o2hg%iBFALAB(Z$
zZ24JjT{aGi@hdz3
ze0U?WPuk?wK#)~u*rKvCCJ71ToW4x7WgXe5gh7=CfKBz7ytK`eXZkP<9-Ee(Z|*4O
zz@ZhxhpfX{{Xp2mSb9yEqM~HtTA{PL8I>36EW@7ySZYec`K)5`|T;U|m_zWMX%`xm|ZCG$65dh*H0mtOts<|p2M=AI`@p8M*u
z)rrbquiJmUdFjg!9QgRpcD+B|x3%%E*fZ7p4xL|c;0M=S_Wj?UaQKd{=~YK#m0c^B*Z2EUOZC57dgXZ4KRorB8!C<4zWUnt@7)qUZC~=g
zYUlZw{
z|CU>O6=89wRxWoKENc=;@q@h>Y*gTLZnVtNLnw;?)8{;sm{?iwWRn5gAuO6`%Fg